diff --git a/kmod-dinghai.spec b/kmod-dinghai.spec
index 834d8d06b0152d19ecf6db3b60be14a1a02c80aa..5a75361dc8bc8120a0a08668446f5415517392df 100644
--- a/kmod-dinghai.spec
+++ b/kmod-dinghai.spec
@@ -47,10 +47,9 @@ pushd src/crypto/zsda
 popd
 pushd src/net/build
     ./build.pl -t clean --ksrc /usr/src/kernels/%{kernel}.%{_arch}
-    ./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF \
-    -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH \
-    -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP \
-    -m CONFIG_ZXDH_MSGQ -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP -m CONFIG_DINGHAI_TSN \
+    ./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX \
+    -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST \
+    -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP -m CONFIG_ZXDH_MSGQ -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP \
     --ksrc /usr/src/kernels/%{kernel}.%{_arch}
 popd
 
diff --git a/src/net/.gitignore b/src/net/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..8693e5a585f27f14fc6408236b104771039e92c6
--- /dev/null
+++ b/src/net/.gitignore
@@ -0,0 +1,16 @@
+autoconf.h
+# Compiled files
+*.ko
+*.mod.c
+*.mod.o
+*.o
+*.o.cmd
+*.cmd
+*.mod
+*.o.d
+
+# Generated files
+Module.symvers
+Module.markers
+modules.order
+.vscode/settings.json
diff --git a/src/net/Makefile b/src/net/Makefile
index c7829d27c2a905903efe225a2df440811fb04a9b..880aae0c127127acb466fc6d83c08497115f9768 100755
--- a/src/net/Makefile
+++ b/src/net/Makefile
@@ -2,6 +2,6 @@ EXTRA_CFLAGS += -I$(CWD)/include
 EXTRA_CFLAGS += -I$(CWD)/drivers/net/ethernet/dinghai/zf_mpf/epc
 
 subdir-ccflags-y += -include $(CWD)/autoconf.h
-obj-$(CONFIG_DINGHAI_ETH) += drivers/net/ethernet/dinghai/
-obj-$(CONFIG_ZXDH_AUXILIARY) += drivers/base/
+obj-$(CONFIG_DINGHAI_ETH)  += drivers/net/ethernet/dinghai/
+obj-m += drivers/base/
 obj-m += drivers/pcie/zxdh_pcie/
\ No newline at end of file
diff --git a/src/net/README.MD b/src/net/README.MD
index 7c31da72bb8971492d2a21a3c4cb38ed9ebafc50..dedeb67987fe12e80536be8e77b3d6a81b651ac1 100644
--- a/src/net/README.MD
+++ b/src/net/README.MD
@@ -1,7 +1,7 @@
 # 源码编译驱动
 ## build
 cd ./build
-./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP -m CONFIG_ZXDH_MSGQ -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP -m CONFIG_DINGHAI_TSN
+./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP -m CONFIG_ZXDH_MSGQ -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP
 
 ## build clean
 cd ./build
@@ -12,26 +12,26 @@ cd ./build
 2. You can also use the "build.sh" compilation script under the root directory of the source code: ./build.sh
 
 3. If you are using ZF server or your architecture is aarch64, and you want to compile the mpf.ko driver to run on ZF.
-./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP -m CONFIG_DINGHAI_ZF_MPF -m PCIE_ZF_EPC_OPEN
+./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP -m CONFIG_DINGHAI_ZF_MPF -m PCIE_ZF_EPC_OPEN
 
 4. **<font color="red">Note: CONFIG_DINGHAI_ZF_MPF  is used for the ZF platform(aarch64), CONFIG_DINGHAI_MPF is used for the x86_64 platform, and the two cannot be used at the same time.</font>**
 
 5. If you want to test 1588, you need to add the compile option CONFIG_ZXDH_1588 and open macro TIME_STAMP_1588, otherwise do not add the compile option CONFIG_ZXDH_1588.
 example,
-./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP -m CONFIG_ZXDH_MSGQ -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP -m CONFIG_DINGHAI_TSN
+./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP -m CONFIG_ZXDH_MSGQ -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP
 
 6. ## Modify the queue pairs
 If you want to modify the queue pairs, you should add the "max_pairs=*" parameter after "insmod zxdh_en_aux.ko". If you do not add the "max_pairs=*" parameter after "insmod zxdh_en_aux.ko", the default queue pairs in the driver are used for initialization. For example:
 insmod zxdh_en_aux.ko max_pairs=16
 
 7. If you want to test Hot-Plug PF(hpf), you need to add the compile option CONFIG_DINGHAI_HPF. For example:
-./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_HPF
+./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP -m CONFIG_ZXDH_MSGQ -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP -m CONFIG_DINGHAI_HPF
 
 8. rpm包相关
 ## Compile and Install driver module
 ```
 cd ./build
-./build.pl -t {all|install} -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP
+./build.pl -t {all|install} -m CONFIG_DINGHAI_ETH -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP
 ```
 - These drivers will be compiled and they will not only appear in the local directory, but also be copied to **/lib/modules/\<KERNEL VER\>/updates/drivers/net/ethernet/zte/zxdh/**
 - The install location listed above is the default location. This may differ for various Linux distributions.
@@ -58,7 +58,7 @@ cd ./build
 ## cross compile
 If you want to use source code to cross-compile, for example, the host is the x86_64 platform and the target is the aarch64 platform, you need to add 3 additional parameters.
 ``` shell
-./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF -m CONFIG_DINGHAI_ZF_MPF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP --ksrc /path/kernel/source --cross_compile /path/cross/compile/tools/aarch64-pc-linux-gnu- --target_arch aarch64
+./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_DINGHAI_PF -m CONFIG_DINGHAI_ZF_MPF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP --ksrc /path/kernel/source --cross_compile /path/cross/compile/tools/aarch64-pc-linux-gnu- --target_arch aarch64
 ```
 - --ksrc kernel source path
 - --cross_compile cross compile tools path
@@ -92,7 +92,7 @@ zxdh_zf_mpf_rpm_build.sh -h
 - `zxdh_np.ko`
 - `zxdh_pf.ko`
 - `zxdh_en_aux.ko`
-- `zxdh_auxiliary.ko`(内核是否支持`auxiliary`总线,都会生成该驱动)
+- `zxdh_auxiliary.ko`(如果内核不支持`auxiliary`总线,那么就会生成该驱动)
 
 其中`zxdh-smartnic-config-*******.rpm`包里包含配置文件
 - `dpu_init.cfg`或者`smart-nic_init.cfg`
@@ -106,7 +106,7 @@ zxdh_zf_mpf_rpm_build.sh -h
 - `zxdh_cmd.ko`
 - `zxdh_np.ko`
 - `zxdh_mpf.ko`
-- `zxdh_auxiliary.ko`(内核是否支持`auxiliary`总线,都会生成该驱动)
+- `zxdh_auxiliary.ko`(如果内核不支持`auxiliary`总线,那么就会生成该驱动)
 
 ## `zxdh_zf_mpf_rpm_build.sh`脚本
 该脚本支持交叉编译, 但是目标架构必须是`aarch64`, 和使用不同内核源码编译, 具体参数见`zxdh_zf_mpf_rpm_build.sh -h`
diff --git a/src/net/build.sh b/src/net/build.sh
index 3ff31dc77bc288226d633c5f69655181c0fd7180..abd28fbe8dd036eff14e7a3f2de959ed5879846e 100755
--- a/src/net/build.sh
+++ b/src/net/build.sh
@@ -7,7 +7,6 @@ unload_drivers() {
     echo "卸载驱动"
     rmmod zxdh_en_aux
     rmmod zxdh_pf
-    rmmod zxdh_tsn
     rmmod zxdh_ptp
     rmmod zxdh_np
     rmmod zxdh_cmd
@@ -18,10 +17,7 @@ compile_zxdh_kernel() {
     echo "编译zxdh_kernel"
     cd $path/build
     ./build.pl -t clean
-    ./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF \
-    -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH \
-    -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP \
-    -m CONFIG_ZXDH_MSGQ -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP -m CONFIG_DINGHAI_TSN
+    ./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP -m CONFIG_ZXDH_MSGQ -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP
 }
 
 load_zxdh_kernel() {
@@ -31,7 +27,6 @@ load_zxdh_kernel() {
     insmod net/ethernet/dinghai/zxdh_cmd.ko
     insmod net/ethernet/dinghai/zxdh_np.ko
     insmod net/ethernet/dinghai/zxdh_ptp.ko
-    insmod net/ethernet/dinghai/zxdh_tsn.ko
     insmod net/ethernet/dinghai/zxdh_pf.ko
     insmod net/ethernet/dinghai/zxdh_en_aux.ko
 }
diff --git a/src/net/build/Makefile b/src/net/build/Makefile
index b32d748768e01ecb28d6a0412d51071cca8da530..262d1714d970a874207a9df497b5a07d231eabf2 100755
--- a/src/net/build/Makefile
+++ b/src/net/build/Makefile
@@ -50,7 +50,7 @@ LINUXINCLUDE=\
 
 zxdh_en_aux_udev_rule_file:
 	@echo 'ACTION!="add", GOTO="drivers_end"' > ${ZXDH_EN_AUX_UDEV_RULE}.rules
-	@echo 'ENV{MODALIAS}=="zxdh_auxiliary:zxdh_pf.en_aux", RUN{builtin}+="kmod load zxdh_en_aux"' >> ${ZXDH_EN_AUX_UDEV_RULE}.rules
+	@echo 'ENV{MODALIAS}=="auxiliary:zxdh_pf.en_aux", RUN{builtin}+="kmod load zxdh_en_aux"' >> ${ZXDH_EN_AUX_UDEV_RULE}.rules
 	@echo 'LABEL="drivers_end"' >> ${ZXDH_EN_AUX_UDEV_RULE}.rules
 
 
@@ -83,11 +83,13 @@ kernel:
 modules_install:
 	@echo "Installing kernel modules..."
 	+$(call kernelbuild, modules_install)
+	${auxiliary_post_install}
+
 
 ##############################
 #  Build and install kernel  #
 ##############################
-all: kernel modules_install zxdh_en_aux_udev_rule_install
+all: kernel modules_install
 	@echo "Running depmod..."
 	$(call cmd_depmod)
 	$(call cmd_initramfs)
@@ -106,8 +108,9 @@ clean:
 ##############################
 modules_uninstall:
 	rm -rf ${INSTALL_MOD_PATH}/lib/modules/${KVER}/${INSTALL_MOD_DIR}
+	${auxiliary_post_uninstall}
 
-uninstall: clean modules_uninstall zxdh_en_aux_udev_rule_uninstall
+uninstall: clean modules_uninstall
 	$(call cmd_depmod)
 	$(call cmd_initramfs)
 
diff --git a/src/net/build/build.pl b/src/net/build/build.pl
index 42bd19790dee0990398b4fa64ed5b4d35429dc56..f5d5bd4bc4b5d07358db9ac571768b7cc99ead1d 100755
--- a/src/net/build/build.pl
+++ b/src/net/build/build.pl
@@ -10,20 +10,17 @@ use File::Temp;
 use Cwd;
 use Term::ANSIColor qw(:constants);
 use Data::Dumper;
-use Scalar::Util 'reftype';
 
 my $CWD     = getcwd;
 
 my $compile_arg = "";
-my $num_cores = scalar(`cat /proc/cpuinfo | grep -c '^processor'`);
-$num_cores -= 1 unless $num_cores == 1;
+
 my $autoconf_h = $CWD.'/../autoconf.h';
 my $target_name;
 my $auto_config= "";
 my $ksrc = "";
 my $cross_compile = "";
 my $target_arch = "";
-my $driver_version = "";
 print $autoconf_h."\n";
 
 while ( $#ARGV >= 0 ) {
@@ -39,9 +36,6 @@ while ( $#ARGV >= 0 ) {
         my $mod = shift(@ARGV);
         $auto_config = $auto_config."\n"."#define ".$mod." 2";
         $compile_arg = $compile_arg." ".$mod."=y";
-    } elsif ( $cmd_flag eq "--dri_ver" ) {
-        my $mod = shift(@ARGV);
-        $compile_arg = $compile_arg." CONFIG_DRIVER_VERSION=".$mod;
     } elsif ( $cmd_flag eq "--ksrc" ) {
         $ksrc = shift(@ARGV);
         $compile_arg = $compile_arg." "."KSRC=".$ksrc;
@@ -51,21 +45,17 @@ while ( $#ARGV >= 0 ) {
     } elsif ( $cmd_flag eq "--target_arch" ) {
         $target_arch = shift(@ARGV);
         $compile_arg = $compile_arg." "."TARGET_ARCH=".$target_arch;
-    } elsif ( $cmd_flag eq "-j" ) {
-        $num_cores = shift(@ARGV);
     } elsif ( $cmd_flag eq "--help" or $cmd_flag eq "-h" ) {
         usage();
         exit 0;
     }
 }
-
 system("cat >$autoconf_h<<EOF \
 $auto_config \
 EOF\
 ");
 
-if ($target_name eq 'kernel') {
-    $compile_arg = $compile_arg." "."-j".$num_cores;
-}
 print "make ".$compile_arg."\n";
+
 exec("make ".$compile_arg);
+
diff --git a/src/net/build/check_aux_bus b/src/net/build/check_aux_bus
new file mode 100755
index 0000000000000000000000000000000000000000..f3e1b54c3ed96ab6439a3ea6d4a8d842f42c579a
--- /dev/null
+++ b/src/net/build/check_aux_bus
@@ -0,0 +1,235 @@
+#!/bin/bash
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (C) 2021, Intel Corporation
+#
+# Helper script to detect if auxiliary bus support. This script
+#
+# returns 0 when:
+# - CONFIG_AUXILIARY_BUS=y
+# - auxiliary_bus.h was found
+#
+# Returning 0 means the driver build/install doesn't need OOT
+# auxiliary bus
+#
+# returns 1 when:
+#	- CONFIG_AUXILIARY_BUS=n (or any value that's not "=y")
+#	- kernel configuration was incorrect
+#	- kernel configuration file was not found
+#
+# Returning 1 means something bad/unexpected happened and the
+# driver build/install should treat this as a failure
+#
+# returns 2 when:
+#	-  When OOT auxiliary is needed regardless if a previous OOT
+#	   auxiliary was already. This is done because the driver
+#	   always needs to build against auxiliary.o to avoid
+#	   warnings/errors since auxiliary.o is built-in to the
+#	   driver's makefile
+#
+# Returning 2 means the driver build/install needs OOT auxiliary
+# bus
+#
+# returns 3 when:
+#	- A file and/or directory does not exist
+#
+# Returning 3 means something bad/unexpected happened and the
+# driver build/install should treat this as a failure
+#
+# Note: when ksrc and build-kernel are both specified on the
+# command line and build-kernel is not in the same location
+# as ksrc, then ksrc takes precedence. For example:
+# 	./check_aux_bus --ksrc=/lib/modules/5.8.0/source --build-kernel=5.10.0
+#
+# In this case the kernel config file won't be searched for and
+# the script will only check to see if the in-tree/OOT auxiliary_bus.h
+# file exists at ksrc.
+
+msg()
+{
+	if [ $verbose == 1 ]; then
+		echo -e $1
+	fi
+}
+
+exit_builtin_auxiliary_enabled() { exit 0; }
+exit_kconfig_invalid() { exit 1; }
+exit_need_oot_auxiliary() { exit 2; }
+exit_not_found_failure() { exit 3; }
+
+find_aux_bus_inc()
+{
+	aux_bus_inc=$(find -L ${ksrc} -name "auxiliary_bus.h")
+	msg "auxiliary_bus.h location: ${aux_bus_inc}"
+}
+
+LINUX_INCLUDE_DIR="include/linux"
+
+set_build_kernel()
+{
+	build_kernel=$(uname -r)
+}
+
+find_kernel_source()
+{
+	# All the default places to look for kernel source
+	test_dirs=(/lib/modules/${build_kernel}/source \
+		   /lib/modules/${build_kernel}/build \
+		   /usr/src/linux-${build_kernel} \
+		   /usr/src/linux-$(echo ${build_kernel} | sed 's/-.*//') \
+		   /usr/src/kernel-headers-${build_kernel} \
+		   /usr/src/kernel-source-${build_kernel} \
+		   /usr/src/linux-$(echo ${build_kernel} | sed 's/\([0-9]*\.[0-9]*\)\..*/\1/') \
+		   /usr/src/linux \
+		   /usr/src/kernels/${build_kernel} \
+		   /usr/src/kernels)
+
+	# Save the first valid kernel source path
+	for dir in "${test_dirs[@]}"; do
+		if [ -d ${dir}/${LINUX_INCLUDE_DIR} ]; then
+			ksrc=${dir}
+			break
+		fi
+	done
+
+	if [ -z ${ksrc} ]; then
+		echo "*** Kernel header files not in any of the expected locations."
+		echo "*** Install the appropriate kernel development package, e.g."
+		echo "kernel-devel, for building kernel modules and try again"
+		exit_not_found_failure
+	fi
+}
+
+find_config_file()
+{
+	# only search for kernel .config file if build_kernel is pointing
+	# in the same tree as ksrc (see not about ksrc and build_kernel
+	# both set in the scripts header comment)
+	if [[ "$ksrc" != *"/lib/modules/${build_kernel}"* ]]; then
+		msg "ksrc=$ksrc not the same as location generated from build_kernel=\"/lib/modules/${build_kernel}\", not searching for kernel .config file"
+	else
+		kbuild_dir="/lib/modules/${build_kernel}/build"
+
+		file_locations=(${kbuild_dir}/include/generated/autoconf.h \
+				${kbuild_dir}/include/linux/autoconf.h \
+				/boot/bmlinux.autoconf.h)
+
+		for file in "${file_locations[@]}"; do
+			if [ -f ${file} ]; then
+				kconfig=${file}
+				break
+			fi
+		done
+
+		if [ -z ${kconfig} ]; then
+			msg "Kernel config file not found at any of the expected locations."
+		fi
+	fi
+}
+
+get_config_auxiliary_bus()
+{
+	# CONFIG_AUXILIARY_BUS=0 corresponds to CONFIG_AUXILIARY_BUS=n
+	# CONFIG_AUXILIARY_BUS=1 corresponds to CONFIG_AUXILIARY_BUS=y
+	# CONFIG_AUXILIARY_BUS= corresponds to CONFIG_AUXILIARY_BUS not available in the kernel
+	CONFIG_AUXILIARY_BUS=$(grep CONFIG_AUXILIARY_BUS ${kconfig} | awk -F" " '{print $3}')
+	msg "CONFIG_AUXILIARY_BUS=${CONFIG_AUXILIARY_BUS}"
+}
+
+ksrc=""
+build_kernel=""
+verbose=0
+
+usage()
+{
+	script=$(basename $0)
+	echo -e "usage:"
+	echo -e "\t$script [options]"
+	echo -e "\n\toptions:"
+	echo -e "\t -v, --verbose"
+	echo -e "\t -h, --help"
+	echo -e "\n\trun script against specified kernel source"
+	echo -e "\t -k, --ksrc \"/lib/modules/5.12.0/source\""
+	echo -e "\n\trun script with kernel version (kernel version used to find kernel source programatically)"
+	echo -e "\t -b, --build-kernel \"5.8.0\""
+}
+
+options=$(getopt -o "k:b:vh" --long ksrc:,build-kernel:,verbose,help -- "$@")
+eval set -- "$options"
+while :; do
+	case $1 in
+	-k|--ksrc) ksrc=$2; shift;;
+	-b|--build-kernel) build_kernel=$2; shift;;
+	-v|--verbose) verbose=1 ;;
+	-h|--help) usage && exit 0;;
+	--) shift; break;;
+	 esac
+	 shift
+done
+
+if [ $verbose == 1 ]; then
+	set -x
+fi
+
+# both build_kernel and ksrc are unset so programatically determine build_kernel
+if [ -z $build_kernel ] && [ -z $ksrc ]; then
+	set_build_kernel
+fi
+
+# only programatically search for kernel source if ksrc not set on command line
+if [ -z $ksrc ]; then
+	find_kernel_source
+fi
+
+find_config_file
+
+if [ ! -z $kconfig ]; then
+	# if we found the kernel .config file then exit the script based on various
+	# conditions that depend on the CONFIG_AUXILIARY_BUS string being found
+	get_config_auxiliary_bus
+
+	if [ -z "$CONFIG_AUXILIARY_BUS" ]; then
+		msg "CONFIG_AUXILIARY_BUS not found in ${kconfig}."
+		# CONFIG_AUXILIARY_BUS string was not found, so OOT auxiliary is needed
+		exit_need_oot_auxiliary
+	elif [ "$CONFIG_AUXILIARY_BUS" = "1" ]; then
+		msg "CONFIG_AUXILIARY_BUS=y in ${kconfig}."
+		# CONFIG_AUXILIARY_BUS=y, so OOT auxiliary is not needed
+		exit_builtin_auxiliary_enabled
+	else
+		msg ""
+		msg "kernel $build_kernel supports auxiliary bus, but CONFIG_AUXILIARY_BUS"
+		msg "is not set in ${kconfig}. Rebuild your kernel with"
+		msg "CONFIG_AUXILIARY_BUS=y"
+		msg ""
+		# CONFIG_AUXILIARY_BUS is not "=y", but the string was found, so report
+		# the failure so it can be used to fail build/install
+		exit_kconfig_invalid
+	fi
+else
+	if [ ! -d ${ksrc}/${LINUX_INCLUDE_DIR} ] && [ ! -d ${ksrc}/source/${LINUX_INCLUDE_DIR} ]; then
+		echo "${ksrc}/${LINUX_INCLUDE_DIR} and ${ksrc}/source/${LINUX_INCLUDE_DIR} do not exist"
+		exit_not_found_failure
+	fi
+
+	# We didn't find a kernel .config file, so check to see if auxiliary_bus.h
+	# is found in the kernel source include directory
+	find_aux_bus_inc
+
+	if [ -f "$aux_bus_inc" ]; then
+		# AUXILIARY_MODULE_PREFIX is defined only in out-of-tree auxiliary bus
+		if [ $(grep -c AUXILIARY_MODULE_PREFIX $aux_bus_inc) -eq 0 ]; then
+			msg "in-tree auxiliary_bus.h found at ${ksrc}/${LINUX_INCLUDE_DIR}"
+			# If auxiliary_bus.h is included at ${ksrc} and it isn't our OOT version, then
+			# don't build OOT auxiliary as part of the driver makefile
+			exit_builtin_auxiliary_enabled
+		else
+			msg "OOT auxiliary_bus.h found at ${ksrc}/${LINUX_INCLUDE_DIR}"
+			# If auxiliary bus is included at ${ksrc} and it is our OOT version, then
+			# build OOT auxiliary as part of the driver makefile
+			exit_need_oot_auxiliary
+		fi
+	else
+		msg "auxiliary_bus.h not found at ${ksrc}/${LINUX_INCLUDE_DIR}"
+		exit_need_oot_auxiliary
+	fi
+fi
diff --git a/src/net/build/config.mk b/src/net/build/config.mk
index b533a4eb477032eee326476e16db962f4f2d102c..b5176b40cf91f03b5154a5aff262c7d3d58ac6c7 100644
--- a/src/net/build/config.mk
+++ b/src/net/build/config.mk
@@ -342,6 +342,47 @@ endif
 # prevent over-writing built-in modules files.
 export INSTALL_MOD_DIR ?= updates/drivers/net/ethernet/zte/${DRIVER}
 
+#################
+# Auxiliary Bus #
+#################
+# If the check_aux_bus script exists, then this driver depends on the
+# auxiliary module. Run the script to determine if we need to include
+# auxiliary files with this build.
+
+$(shell chmod 777 check_aux_bus)
+
+ifneq ($(call test_file,./check_aux_bus),)
+NEED_AUX_BUS := $(shell ./check_aux_bus --ksrc="${KSRC}" --build-kernel="${BUILD_KERNEL}" >/dev/null 2>&1; echo $$?)
+endif # check_aux_bus exists
+
+# The out-of-tree auxiliary module we ship should be moved into this
+# directory as part of installation.
+export INSTALL_AUX_DIR ?= updates/drivers/net/ethernet/zte/auxiliary
+
+# If we're installing auxiliary bus out-of-tree, the following steps are
+# necessary to ensure the relevant files get put in place.
+ifeq (${NEED_AUX_BUS},2)
+define auxiliary_post_install
+	install -D -m 644 ../Module.symvers ${INSTALL_MOD_PATH}/lib/modules/${KVER}/extern-symvers/zxdh_auxiliary.symvers
+	install -d ${INSTALL_MOD_PATH}/lib/modules/${KVER}/${INSTALL_AUX_DIR}
+	mv -f ${INSTALL_MOD_PATH}/lib/modules/${KVER}/${INSTALL_MOD_DIR}/drivers/base/zxdh_auxiliary.ko \
+	      ${INSTALL_MOD_PATH}/lib/modules/${KVER}/${INSTALL_AUX_DIR}/zxdh_auxiliary.ko
+	install -D -m 644 ../include/linux/dinghai/auxiliary_bus.h ${INSTALL_MOD_PATH}/${KSRC}/include/linux/auxiliary_bus.h
+endef
+else
+auxiliary_post_install =
+endif
+
+ifeq (${NEED_AUX_BUS},2)
+define auxiliary_post_uninstall
+	rm -f ${INSTALL_MOD_PATH}/lib/modules/${KVER}/extern-symvers/zxdh_auxiliary.symvers
+	rm -f ${INSTALL_MOD_PATH}/lib/modules/${KVER}/${INSTALL_AUX_DIR}/zxdh_auxiliary.ko
+	rm -f ${INSTALL_MOD_PATH}/${KSRC}/include/linux/auxiliary_bus.h
+endef
+else
+auxiliary_post_uninstall =
+endif
+
 ######################
 # Kernel Build Macro #
 ######################
@@ -383,4 +424,5 @@ kernelbuild = $(call warn_signed_modules) \
               $(if ${NEED_CROSS_COMPILE}, CROSS_COMPILE=$(CROSS_COMPILE)) \
               $(if ${DISABLE_MODULE_SIGNING},CONFIG_MODULE_SIG=n) \
               $(if ${DISABLE_MODULE_SIGNING},CONFIG_MODULE_SIG_ALL=) \
+              $(if ${NEED_AUX_BUS},NEED_AUX_BUS="${NEED_AUX_BUS}") \
               ${2} ${1}
diff --git a/src/net/build/spec/zxdh-eth.spec.example b/src/net/build/spec/zxdh-eth.spec.example
index 5a526665fcfab744e33e47b82f93c7294c4c766e..cac77fa5c2715daf9481011b1a8c60ff7ea2cfe1 100644
--- a/src/net/build/spec/zxdh-eth.spec.example
+++ b/src/net/build/spec/zxdh-eth.spec.example
@@ -8,8 +8,6 @@
 %{!?_config_version: %global _config_version 1.0}
 %{!?_config_release: %global _config_release 1}
 
-%{!?ETH_DRI_VER: %global ETH_DRI_VER 1.0-1}
-
 %{!?KSRC: %global KSRC /lib/modules/%(uname -r)/source}
 %{!?target: %global target %(uname -m)}
 
@@ -84,28 +82,24 @@ cd ./build
 %if 0%{?CROSS_COMPILE:1}
 # cross compile
 
-./build.pl -t kernel -m CONFIG_DINGHAI_ETH                -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF \
+./build.pl -t kernel -m CONFIG_DINGHAI_ETH                -m CONFIG_DINGHAI_PF \
                      -m CONFIG_ZXDH_SF                    -m CONFIG_DINGHAI_EN_AUX \
                      -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS   -m HAVE_DEV_PM_DOMAIN_ATTACH \
                      -m HAVE_BUS_FIND_DEVICE_GET_CONST    -m CONFIG_DINGHAI_DH_CMD \
                      -m CONFIG_DINGHAI_NP                 -m CONFIG_ZXDH_MSGQ \
                      -m CONFIG_ZXDH_1588                  -m CONFIG_DINGHAI_PTP \
-                     -m CONFIG_DINGHAI_TSN\
                      --ksrc %{KSRC} \
                      --cross_compile %{CROSS_COMPILE} \
-                     --target_arch %{target} \
-                     --dri_ver %{ETH_DRI_VER}
+                     --target_arch %{target}
 %else
 # no cross compile
-./build.pl -t kernel -m CONFIG_DINGHAI_ETH                -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF \
+./build.pl -t kernel -m CONFIG_DINGHAI_ETH                -m CONFIG_DINGHAI_PF \
                      -m CONFIG_ZXDH_SF                    -m CONFIG_DINGHAI_EN_AUX \
                      -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS   -m HAVE_DEV_PM_DOMAIN_ATTACH \
                      -m HAVE_BUS_FIND_DEVICE_GET_CONST    -m CONFIG_DINGHAI_DH_CMD \
                      -m CONFIG_DINGHAI_NP                 -m CONFIG_ZXDH_MSGQ \
                      -m CONFIG_ZXDH_1588                  -m CONFIG_DINGHAI_PTP \
-                     -m CONFIG_DINGHAI_TSN\
-                     --ksrc %{KSRC} \
-                     --dri_ver %{ETH_DRI_VER}
+                     --ksrc %{KSRC}
 %endif
 
 %install
@@ -113,17 +107,27 @@ cd ./build
 
 export INSTALL_MOD_PATH=%{buildroot}
 export INSTALL_MOD_DIR=%{install_mod_dir}
+export INSTALL_AUX_DIR=%{install_mod_dir}/auxiliary
 export KSRC=%{KSRC}
 make modules_install INSTALL_MOD_PATH=%{buildroot} INSTALL_MOD_DIR=%{install_mod_dir} KSRC=%{KSRC}
 
 # Remove modules files that we do not want to include
 find %{buildroot}/lib/modules/ -name 'modules.*' -exec rm -f {} \;
+find %{buildroot}/lib/modules/ -name 'zxdh_auxiliary.symvers' -exec rm -f {} \;
+find %{buildroot}/lib/modules/ -name 'auxiliary_bus.h' -exec rm -f {} \;
+%if 0%{?NEED_AUX_BUS:1}
+if [ -d %{buildroot}%{KSRC} ]; then
+	rm -rf %{buildroot}%{KSRC};
+fi
+%endif
 
 cd %{buildroot}
 find lib -name "*.ko" -printf "/%p\n" \
 	>%{_builddir}/zxdh_kernel/file.list
 export _ksrc=%{KSRC}
 
+
+
 # Add config files
 %if %{IS_RHEL_VENDOR}
 %if ! 0%{?fedora}
@@ -140,12 +144,11 @@ done
 %endif
 %endif
 
-# Add zxdh_en_aux udev conf
-
-%{__install} -d %{buildroot}%{_sysconfdir}/udev/rules.d/
-echo 'ACTION!="add", GOTO="drivers_end"' > %{buildroot}%{_sysconfdir}/udev/rules.d/80-%{name}-zxdh_en_aux-drivers.rules
-echo 'ENV{MODALIAS}=="zxdh_auxiliary:zxdh_pf.en_aux", RUN{builtin}+="kmod load zxdh_en_aux"' >> %{buildroot}%{_sysconfdir}/udev/rules.d/80-%{name}-zxdh_en_aux-drivers.rules
-echo 'LABEL="drivers_end"' >> %{buildroot}%{_sysconfdir}/udev/rules.d/80-%{name}-zxdh_en_aux-drivers.rules
+# Add zxdh_en_aux modprobe conf
+%if 0%{?NEED_AUX_BUS:1}
+%{__install} -d %{buildroot}%{_sysconfdir}/modprobe.d/
+echo "install zxdh_pf /sbin/modprobe --ignore-install zxdh_pf && /sbin/modprobe zxdh_en_aux" > %{buildroot}%{_sysconfdir}/modprobe.d/zxdh_en_aux.conf
+%endif
 
 cd $HOME/rpmbuild/BUILD/zxdh_kernel/build/zxdh_config
 %{__install} -m 644 ./%{_config_file}.cfg %{buildroot}%{_sysconfdir}
@@ -160,7 +163,9 @@ rm -rf %{buildroot}
 %endif
 %endif
 
-%{_sysconfdir}/udev/rules.d/80-%{name}-zxdh_en_aux-drivers.rules
+%if 0%{?NEED_AUX_BUS:1}
+%config(noreplace) %{_sysconfdir}/modprobe.d/zxdh_en_aux.conf
+%endif
 
 
 
diff --git a/src/net/build/spec/zxdh-hpf.spec.example b/src/net/build/spec/zxdh-hpf.spec.example
index 3dd09b05c3fbd12e3d0f92dea33cd32eb1838e7a..da93c71957d6dccc6de28752c617358661d1ccaa 100644
--- a/src/net/build/spec/zxdh-hpf.spec.example
+++ b/src/net/build/spec/zxdh-hpf.spec.example
@@ -4,8 +4,6 @@
 %{!?_version: %global _version 1.0}
 %{!?_release: %global _release 1}
 
-%{!?HPF_DRI_VER: %global HPF_DRI_VER 1.0-1}
-
 %{!?KSRC: %global KSRC /lib/modules/%(uname -r)/source}
 %{!?target: %global target %(uname -m)}
 
@@ -65,15 +63,17 @@ cd ./build
 %if 0%{?CROSS_COMPILE:1}
 # cross compile
 ./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_DINGHAI_HPF -m CONFIG_DINGHAI_DH_CMD  -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS\
+                     -m HAVE_DEV_PM_DOMAIN_ATTACH \
+                     -m HAVE_BUS_FIND_DEVICE_GET_CONST \
                      --ksrc %{KSRC} \
                      --cross_compile %{CROSS_COMPILE} \
-                     --target_arch %{target} \
-                     --dri_ver %{HPF_DRI_VER}
+                     --target_arch %{target}
 %else
 # no cross compile
 ./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_DINGHAI_HPF -m CONFIG_DINGHAI_DH_CMD  -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS\
-                     --ksrc %{KSRC} \
-                     --dri_ver %{HPF_DRI_VER}
+                     -m HAVE_DEV_PM_DOMAIN_ATTACH \
+                     -m HAVE_BUS_FIND_DEVICE_GET_CONST \
+                     --ksrc %{KSRC}
 %endif
 
 %install
@@ -81,11 +81,21 @@ cd ./build
 
 export INSTALL_MOD_PATH=%{buildroot}
 export INSTALL_MOD_DIR=%{install_mod_dir}
+export INSTALL_AUX_DIR=%{install_mod_dir}/auxiliary
 export KSRC=%{KSRC}
 make modules_install INSTALL_MOD_PATH=%{buildroot} INSTALL_MOD_DIR=%{install_mod_dir} KSRC=%{KSRC}
 
 # Remove modules files that we do not want to include
 find %{buildroot}/lib/modules/ -name 'modules.*' -exec rm -f {} \;
+find %{buildroot}/lib/modules/ -name 'zxdh_auxiliary.symvers' -exec rm -f {} \;
+find %{buildroot}/lib/modules/ -name 'auxiliary_bus.h' -exec rm -f {} \;
+
+%if 0%{?NEED_AUX_BUS:1}
+find %{buildroot}/lib/modules/ -name '*auxiliary.ko' -exec rm -f {} \;
+if [ -d %{buildroot}%{KSRC} ]; then
+	rm -rf %{buildroot}%{KSRC};
+fi
+%endif
 
 cd %{buildroot}
 find lib -name "*.ko" -printf "/%p\n" \
diff --git a/src/net/build/spec/zxdh-zf-mpf.spec.example b/src/net/build/spec/zxdh-zf-mpf.spec.example
index d918da7e707c96beffb2a92aa2acc23e0714567d..fa8eacdacedd1486a84949521cc6cafd1f32a457 100644
--- a/src/net/build/spec/zxdh-zf-mpf.spec.example
+++ b/src/net/build/spec/zxdh-zf-mpf.spec.example
@@ -4,8 +4,6 @@
 %{!?_version: %global _version 1.0}
 %{!?_release: %global _release 1}
 
-%{!?ZF_MPF_DRI_VER: %global ZF_MPF_DRI_VER 1.0-1}
-
 %{!?KSRC: %global KSRC /lib/modules/%(uname -r)/source}
 %{!?target: %global target aarch64}
 
@@ -65,24 +63,22 @@ cd ./build
 
 %if 0%{?CROSS_COMPILE:1}
 # cross compile
-./build.pl -t kernel -m CONFIG_DINGHAI_ETH         -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_ZF_MPF \
+./build.pl -t kernel -m CONFIG_DINGHAI_ETH         -m CONFIG_DINGHAI_ZF_MPF \
                      -m PCIE_ZF_EPC_OPEN           -m CONFIG_DINGHAI_DH_CMD \
                      -m CONFIG_ZXDH_SF             -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS \
                      -m HAVE_DEV_PM_DOMAIN_ATTACH  -m HAVE_BUS_FIND_DEVICE_GET_CONST \
                      -m CONFIG_ZF_GDMA \
                      --ksrc %{KSRC} \
                      --cross_compile %{CROSS_COMPILE} \
-                     --target_arch %{target} \
-                     --dri_ver %{ZF_MPF_DRI_VER}
+                     --target_arch %{target}
 %else
 # no cross compile
-./build.pl -t kernel -m CONFIG_DINGHAI_ETH         -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_ZF_MPF \
+./build.pl -t kernel -m CONFIG_DINGHAI_ETH         -m CONFIG_DINGHAI_ZF_MPF \
                      -m PCIE_ZF_EPC_OPEN           -m CONFIG_DINGHAI_DH_CMD \
                      -m CONFIG_ZXDH_SF             -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS \
                      -m HAVE_DEV_PM_DOMAIN_ATTACH  -m HAVE_BUS_FIND_DEVICE_GET_CONST \
                      -m CONFIG_ZF_GDMA \
-                     --ksrc %{KSRC} \
-                     --dri_ver %{ZF_MPF_DRI_VER}
+                     --ksrc %{KSRC}
 %endif
 
 %install
@@ -97,6 +93,13 @@ make modules_install INSTALL_MOD_PATH=%{buildroot} INSTALL_MOD_DIR=%{install_mod
 find %{buildroot}/lib/modules/ -name 'modules.*' -exec rm -f {} \;
 find %{buildroot}/lib/modules/ -name '*zf_epf.ko' -exec rm -f {} \;
 
+%if 0%{?NEED_AUX_BUS:1}
+find %{buildroot}/lib/modules/ -name '*auxiliary.ko' -exec rm -f {} \;
+if [ -d %{buildroot}%{KSRC} ]; then
+	rm -rf %{buildroot}%{KSRC};
+fi
+%endif
+
 cd %{buildroot}
 find lib -name "*.ko" -printf "/%p\n" \
 	>%{_builddir}/zxdh_kernel/zf_mpf_file.list
diff --git a/src/net/ci_cmd.sh b/src/net/ci_cmd.sh
old mode 100755
new mode 100644
diff --git a/src/net/compat/config.h b/src/net/compat/config.h
old mode 100755
new mode 100644
diff --git a/src/net/compile.sh b/src/net/compile.sh
index c249b036254db3ab58d06f376b49cc9d3e341089..864e607f7b281412f15f4287eb642eea73b91466 100755
--- a/src/net/compile.sh
+++ b/src/net/compile.sh
@@ -4,7 +4,6 @@
 compile_stage=$1 #四种取值：verifyci、gateci、postci、versionci
 build_no=$2
 chg_no=$3
-rpm_ver_no="2.24.20.02"
 
 
 #ver_path不变，各组件只需修改root_dir
@@ -20,13 +19,13 @@ if [ "$compile_stage" = "verifyci" ]; then
   echo "NXI_NXE_DPU_host_x86_file:"$NXI_NXE_DPU_host_x86_file
   DPU_zf_aarch64_file=$(ls /lib/modules/ | grep "aarch64_${DPU_CGS_kernel_aarch64}$")
   echo "DPU_zf_aarch64_file:"$DPU_zf_aarch64_file
-
+ 
   echo "start check x86 pf driver"
   compile_path=${root_dir}/build
   rm -f $compile_path/zxdh_kernel_compile.txt $compile_path/zxdh_kernel_compile_fail_result.txt
   cd ${compile_path}
   ./build.pl -t clean --ksrc /lib/modules/$NXI_NXE_DPU_host_x86_file
-  ./build.pl -t kernel --ksrc /lib/modules/$NXI_NXE_DPU_host_x86_file -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP -m CONFIG_ZXDH_MSGQ -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP -m CONFIG_DINGHAI_TSN \
+  ./build.pl -t kernel --ksrc /lib/modules/$NXI_NXE_DPU_host_x86_file -m CONFIG_DINGHAI_ETH -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP -m CONFIG_ZXDH_MSGQ -m CONFIG_ZXDH_1588 -m CONFIG_DINGHAI_PTP \
   >>$compile_path/zxdh_kernel_compile.txt 2>$compile_path/zxdh_kernel_compile_fail_result.txt
   status=$?
   echo "***************print x86 en_pf_compile.txt***************"
@@ -65,7 +64,7 @@ if [ "$compile_stage" = "verifyci" ]; then
   ./build.pl -t kernel --ksrc /lib/modules/$DPU_zf_aarch64_file \
                        --cross_compile /opt/aarch64_cgslv6.01_gcc8.3.1_glibc2.28/bin/aarch64-pc-linux-gnu- \
                        --target_arch aarch64 \
-                       -m CONFIG_DINGHAI_ZF_MPF -m PCIE_ZF_EPC_OPEN -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_ZXDH_SF -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_ZF_GDMA \
+                       -m CONFIG_DINGHAI_ZF_MPF -m PCIE_ZF_EPC_OPEN -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_SF -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_ZF_GDMA \
   >>$compile_path/zxdh_kernel_compile.txt 2>$compile_path/zxdh_kernel_compile_fail_result.txt
   status=$?
   echo "***************print arm zf_mpf_compile.txt***************"
@@ -96,12 +95,9 @@ if [ $compile_stage = "postci" ]; then
   cd $root_dir/kernel-src
   rm -f *\.tgz
   date=$(date +%Y%m%d%H%M%S)
-  version=${rpm_ver_no}
-  dri_version=${rpm_ver_no}-${date}
-
-  pf_tgz_name=$root_dir/kernel-src/zxdh-eth-${version}-${date}.src.tgz
-  host_hpf_tgz_name=$root_dir/kernel-src/zxdh-neo-host-hpf-${version}-${date}.src.tgz
-  zf_mpf_tgz_name=$root_dir/kernel-src/zxdh-neo-mpf-${version}-${date}.src.tgz
+  pf_tgz_name=$root_dir/kernel-src/zxdh-eth-${build_no}.${chg_no}.${date}.src.tgz
+  host_hpf_tgz_name=$root_dir/kernel-src/zxdh-neo-host-hpf-${build_no}.${chg_no}.${date}.src.tgz
+  zf_mpf_tgz_name=$root_dir/kernel-src/zxdh-neo-mpf-${build_no}.${chg_no}.${date}.src.tgz
   tar czvf $pf_tgz_name --exclude=$root_dir/kernel-src $root_dir
   result=$?
   #判断结果
@@ -117,6 +113,7 @@ if [ $compile_stage = "postci" ]; then
   #开始生成rpm包
   cd $root_dir
   rm -f *\.rpm
+  version=${build_no}.${chg_no}
   echo "[NXI/NXE]交叉编译生成host-arm下的rpm包,使用[en_pf]源码"
   ./zxdh_eth_rpm_build.sh \
   --ksrc /lib/modules/$NXI_NXE_DPU_host_aarch64_file  \
@@ -124,16 +121,14 @@ if [ $compile_stage = "postci" ]; then
   --target-arch aarch64 \
   --dist .cgsl${NXI_Host_CGS_kernel_aarch64:1} \
   --rpm-driver-version "${version}" --rpm-driver-release "${date}" \
-  --rpm-config-version "${version}" --rpm-config-release "${date}" --rpm-config-name zxdh-dpu-config \
-  --eth-driver-version "${dri_version}"
+  --rpm-config-version "${version}" --rpm-config-release "${date}" --rpm-config-name zxdh-dpu-config
 
   echo "[NXI/NXE]生成host-x86下的rpm包,使用[en_pf]源码"
   ./zxdh_eth_rpm_build.sh \
   --ksrc /lib/modules/$NXI_NXE_DPU_host_x86_file  \
   --dist .cgsl${NXI_Host_CGS_kernel_X86:1} \
   --rpm-driver-version "${version}" --rpm-driver-release "${date}" \
-  --rpm-config-version "${version}" --rpm-config-release "${date}" \
-  --eth-driver-version "${dri_version}"
+  --rpm-config-version "${version}" --rpm-config-release "${date}"
 
   echo "[DPU]交叉编译生成host-arm下的rpm包,使用[function_hotplug]源码"
   ./zxdh_hpf_rpm_build.sh \
@@ -141,15 +136,13 @@ if [ $compile_stage = "postci" ]; then
   --cross-compile /opt/aarch64_cgslv6.01_gcc8.3.1_glibc2.28/bin/aarch64-pc-linux-gnu- \
   --target-arch aarch64 \
   --dist .cgsl${NXI_Host_CGS_kernel_aarch64:1} \
-  --rpm-driver-version "${version}" --rpm-driver-release "${date}" \
-  --hpf-driver-version "${dri_version}"
+  --rpm-driver-version "${version}" --rpm-driver-release "${date}" 
 
   echo "[DPU]生成host-x86下的rpm包,使用[function_hotplug]源码"
   ./zxdh_hpf_rpm_build.sh \
   --ksrc /lib/modules/$NXI_NXE_DPU_host_x86_file  \
   --dist .cgsl${NXI_Host_CGS_kernel_X86:1} \
-  --rpm-driver-version "${version}" --rpm-driver-release "${date}" \
-  --hpf-driver-version "${dri_version}"
+  --rpm-driver-version "${version}" --rpm-driver-release "${date}" 
 
   echo "[DPU]交叉编译生成zf-arm下的rpm包,使用[en_pf]源码"
   ./zxdh_eth_rpm_build.sh \
@@ -159,21 +152,18 @@ if [ $compile_stage = "postci" ]; then
   --dist .cgsl${DPU_CGS_kernel_aarch64:1} \
   --rpm-driver-name "zxdh-eth" \
   --rpm-driver-version "${version}" --rpm-driver-release "${date}" \
-  --rpm-config-version "${version}" --rpm-config-release "${date}" \
-  --eth-driver-version "${dri_version}"
+  --rpm-config-version "${version}" --rpm-config-release "${date}"
 
   echo "[DPU]生成zf-arm下的rpm包,使用[zf_mpf]源码"
   ./zxdh_zf_mpf_rpm_build.sh \
   --ksrc /lib/modules/$DPU_zf_aarch64_file  \
   --cross-compile /opt/aarch64_cgslv6.01_gcc8.3.1_glibc2.28/bin/aarch64-pc-linux-gnu- \
   --dist .cgsl${DPU_CGS_kernel_aarch64:1} \
-  --rpm-driver-version "${version}" --rpm-driver-release "${date}" \
-  --zf-mpf-driver-version "${dri_version}"
+  --rpm-driver-version "${version}" --rpm-driver-release "${date}" 
 
   #TODO
   echo "查看全部rpm包"
   ls
-
   exit 0
 fi
 
@@ -192,12 +182,9 @@ if [ $compile_stage = "versionci" ]; then
   cd $root_dir/kernel-src
   rm -f *\.tgz
   date=$(date +%Y%m%d%H%M%S)
-  version=${rpm_ver_no}
-  dri_version=${rpm_ver_no}-${date}
-
-  pf_tgz_name=$root_dir/kernel-src/zxdh-eth-${version}-${date}-daily.src.tgz
-  host_hpf_tgz_name=$root_dir/kernel-src/zxdh-neo-host-hpf-${version}-${date}-daily.src.tgz
-  zf_mpf_tgz_name=$root_dir/kernel-src/zxdh-neo-mpf-${version}-${date}-daily.src.tgz
+  pf_tgz_name=$root_dir/kernel-src/zxdh-eth-${build_no}.${chg_no}.${date}-daily.src.tgz
+  host_hpf_tgz_name=$root_dir/kernel-src/zxdh-neo-host-hpf-${build_no}.${chg_no}.${date}-daily.src.tgz
+  zf_mpf_tgz_name=$root_dir/kernel-src/zxdh-neo-mpf-${build_no}.${chg_no}.${date}-daily.src.tgz
   tar czvf $pf_tgz_name --exclude=$root_dir/kernel-src $root_dir
   result=$?
   #判断结果
@@ -213,6 +200,7 @@ if [ $compile_stage = "versionci" ]; then
   #开始生成rpm包
   cd $root_dir
   rm -f *\.rpm
+  version=${build_no}.${chg_no}
   echo "[NXI/NXE]交叉编译生成host-arm下的rpm包,使用[en_pf]源码"
   ./zxdh_eth_rpm_build.sh \
   --ksrc /lib/modules/$NXI_NXE_DPU_host_aarch64_file  \
@@ -220,16 +208,14 @@ if [ $compile_stage = "versionci" ]; then
   --target-arch aarch64 \
   --dist .cgsl${NXI_Host_CGS_kernel_aarch64:1} \
   --rpm-driver-version "${version}" --rpm-driver-release "${date}" \
-  --rpm-config-version "${version}" --rpm-config-release "${date}" --rpm-config-name zxdh-dpu-config \
-  --eth-driver-version "${dri_version}"
+  --rpm-config-version "${version}" --rpm-config-release "${date}" --rpm-config-name zxdh-dpu-config
 
   echo "[NXI/NXE]生成host-x86下的rpm包,使用[en_pf]源码"
   ./zxdh_eth_rpm_build.sh \
   --ksrc /lib/modules/$NXI_NXE_DPU_host_x86_file  \
   --dist .cgsl${NXI_Host_CGS_kernel_X86:1} \
   --rpm-driver-version "${version}" --rpm-driver-release "${date}" \
-  --rpm-config-version "${version}" --rpm-config-release "${date}" \
-  --eth-driver-version "${dri_version}"
+  --rpm-config-version "${version}" --rpm-config-release "${date}"
 
   echo "[DPU]交叉编译生成host-arm下的rpm包,使用[function_hotplug]源码"
   ./zxdh_hpf_rpm_build.sh \
@@ -237,15 +223,13 @@ if [ $compile_stage = "versionci" ]; then
   --cross-compile /opt/aarch64_cgslv6.01_gcc8.3.1_glibc2.28/bin/aarch64-pc-linux-gnu- \
   --target-arch aarch64 \
   --dist .cgsl${NXI_Host_CGS_kernel_aarch64:1} \
-  --rpm-driver-version "${version}" --rpm-driver-release "${date}" \
-  --hpf-driver-version "${dri_version}"
+  --rpm-driver-version "${version}" --rpm-driver-release "${date}" 
 
   echo "[DPU]生成host-x86下的rpm包,使用[function_hotplug]源码"
   ./zxdh_hpf_rpm_build.sh \
   --ksrc /lib/modules/$NXI_NXE_DPU_host_x86_file  \
   --dist .cgsl${NXI_Host_CGS_kernel_X86:1} \
-  --rpm-driver-version "${version}" --rpm-driver-release "${date}" \
-  --hpf-driver-version "${dri_version}"
+  --rpm-driver-version "${version}" --rpm-driver-release "${date}" 
 
   echo "[DPU]交叉编译生成zf-arm下的rpm包,使用[en_pf]源码"
   ./zxdh_eth_rpm_build.sh \
@@ -255,16 +239,14 @@ if [ $compile_stage = "versionci" ]; then
   --dist .cgsl${DPU_CGS_kernel_aarch64:1} \
   --rpm-driver-name "zxdh-eth" \
   --rpm-driver-version "${version}" --rpm-driver-release "${date}" \
-  --rpm-config-version "${version}" --rpm-config-release "${date}" \
-  --eth-driver-version "${dri_version}"
+  --rpm-config-version "${version}" --rpm-config-release "${date}"
 
   echo "[DPU]生成zf-arm下的rpm包,使用[zf_mpf]源码"
   ./zxdh_zf_mpf_rpm_build.sh \
   --ksrc /lib/modules/$DPU_zf_aarch64_file  \
   --cross-compile /opt/aarch64_cgslv6.01_gcc8.3.1_glibc2.28/bin/aarch64-pc-linux-gnu- \
   --dist .cgsl${DPU_CGS_kernel_aarch64:1} \
-  --rpm-driver-version "${version}" --rpm-driver-release "${date}" \
-  --zf-mpf-driver-version "${dri_version}"
+  --rpm-driver-version "${version}" --rpm-driver-release "${date}" 
 
   #TODO
   echo "查看全部rpm包"
diff --git a/src/net/drivers/base/Makefile b/src/net/drivers/base/Makefile
old mode 100755
new mode 100644
index 4f40a2eed03bdc40f4ebf270086e77d90ef6761f..3457ecf804c8ff764140d1c87b8510194b1c407c
--- a/src/net/drivers/base/Makefile
+++ b/src/net/drivers/base/Makefile
@@ -1,6 +1,9 @@
 subdir-ccflags-y += -I$(CWD)/include
 subdir-ccflags-y += -include $(CWD)/autoconf.h
-ccflags-y += -Werror
+
+ifeq (${NEED_AUX_BUS},2)
+EXTRA_CFLAGS += -DAUX_BUS_NO_SUPPORT
 
 obj-m += zxdh_auxiliary.o
-zxdh_auxiliary-y += en_auxiliary.o
\ No newline at end of file
+zxdh_auxiliary-y += auxiliary.o
+endif
\ No newline at end of file
diff --git a/src/net/drivers/base/auxiliary.c b/src/net/drivers/base/auxiliary.c
new file mode 100644
index 0000000000000000000000000000000000000000..b1f3e01ddc044fb016408f1c3086bbfef46a856a
--- /dev/null
+++ b/src/net/drivers/base/auxiliary.c
@@ -0,0 +1,500 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019-2020 Intel Corporation
+ *
+ * Please see Documentation/driver-api/auxiliary_bus.rst for more information.
+ */
+
+#ifdef pr_fmt
+#undef pr_fmt
+#endif
+
+#define pr_fmt(fmt) "%s:%s: " fmt, KBUILD_MODNAME, __func__
+
+#include <linux/dinghai/driver.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/string.h>
+#ifdef AUX_BUS_NO_SUPPORT
+#include <linux/dinghai/auxiliary_bus.h>
+#else
+#include <linux/auxiliary_bus.h>
+#endif
+#include <linux/acpi.h>
+#ifdef CONFIG_COMPAT_AUXILIARY_EXTERNAL_INIT
+#include "base.h"
+#endif
+
+/**
+ * DOC: PURPOSE
+ *
+ * In some subsystems, the functionality of the core device (PCI/ACPI/other) is
+ * too complex for a single device to be managed by a monolithic driver (e.g.
+ * Sound Open Firmware), multiple devices might implement a common intersection
+ * of functionality (e.g. NICs + RDMA), or a driver may want to export an
+ * interface for another subsystem to drive (e.g. SIOV Physical Function export
+ * Virtual Function management).  A split of the functionality into child-
+ * devices representing sub-domains of functionality makes it possible to
+ * compartmentalize, layer, and distribute domain-specific concerns via a Linux
+ * device-driver model.
+ *
+ * An example for this kind of requirement is the audio subsystem where a
+ * single IP is handling multiple entities such as HDMI, Soundwire, local
+ * devices such as mics/speakers etc. The split for the core's functionality
+ * can be arbitrary or be defined by the DSP firmware topology and include
+ * hooks for test/debug. This allows for the audio core device to be minimal
+ * and focused on hardware-specific control and communication.
+ *
+ * Each auxiliary_device represents a part of its parent functionality. The
+ * generic behavior can be extended and specialized as needed by encapsulating
+ * an auxiliary_device within other domain-specific structures and the use of
+ * .ops callbacks. Devices on the auxiliary bus do not share any structures and
+ * the use of a communication channel with the parent is domain-specific.
+ *
+ * Note that ops are intended as a way to augment instance behavior within a
+ * class of auxiliary devices, it is not the mechanism for exporting common
+ * infrastructure from the parent. Consider EXPORT_SYMBOL_NS() to convey
+ * infrastructure from the parent module to the auxiliary module(s).
+ */
+
+/**
+ * DOC: USAGE
+ *
+ * The auxiliary bus is to be used when a driver and one or more kernel
+ * modules, who share a common header file with the driver, need a mechanism to
+ * connect and provide access to a shared object allocated by the
+ * auxiliary_device's registering driver.  The registering driver for the
+ * auxiliary_device(s) and the kernel module(s) registering auxiliary_drivers
+ * can be from the same subsystem, or from multiple subsystems.
+ *
+ * The emphasis here is on a common generic interface that keeps subsystem
+ * customization out of the bus infrastructure.
+ *
+ * One example is a PCI network device that is RDMA-capable and exports a child
+ * device to be driven by an auxiliary_driver in the RDMA subsystem.  The PCI
+ * driver allocates and registers an auxiliary_device for each physical
+ * function on the NIC.  The RDMA driver registers an auxiliary_driver that
+ * claims each of these auxiliary_devices.  This conveys data/ops published by
+ * the parent PCI device/driver to the RDMA auxiliary_driver.
+ *
+ * Another use case is for the PCI device to be split out into multiple sub
+ * functions.  For each sub function an auxiliary_device is created.  A PCI sub
+ * function driver binds to such devices that creates its own one or more class
+ * devices.  A PCI sub function auxiliary device is likely to be contained in a
+ * struct with additional attributes such as user defined sub function number
+ * and optional attributes such as resources and a link to the parent device.
+ * These attributes could be used by systemd/udev; and hence should be
+ * initialized before a driver binds to an auxiliary_device.
+ *
+ * A key requirement for utilizing the auxiliary bus is that there is no
+ * dependency on a physical bus, device, register accesses or regmap support.
+ * These individual devices split from the core cannot live on the platform bus
+ * as they are not physical devices that are controlled by DT/ACPI.  The same
+ * argument applies for not using MFD in this scenario as MFD relies on
+ * individual function devices being physical devices.
+ */
+
+/**
+ * DOC: EXAMPLE
+ *
+ * Auxiliary devices are created and registered by a subsystem-level core
+ * device that needs to break up its functionality into smaller fragments. One
+ * way to extend the scope of an auxiliary_device is to encapsulate it within a
+ * domain- pecific structure defined by the parent device. This structure
+ * contains the auxiliary_device and any associated shared data/callbacks
+ * needed to establish the connection with the parent.
+ *
+ * An example is:
+ *
+ * .. code-block:: c
+ *
+ *         struct foo {
+ *        struct auxiliary_device auxdev;
+ *        void (*connect)(struct auxiliary_device *auxdev);
+ *        void (*disconnect)(struct auxiliary_device *auxdev);
+ *        void *data;
+ *        };
+ *
+ * The parent device then registers the auxiliary_device by calling
+ * auxiliary_device_init(), and then auxiliary_device_add(), with the pointer
+ * to the auxdev member of the above structure. The parent provides a name for
+ * the auxiliary_device that, combined with the parent's KBUILD_MODNAME,
+ * creates a match_name that is be used for matching and binding with a driver.
+ *
+ * Whenever an auxiliary_driver is registered, based on the match_name, the
+ * auxiliary_driver's probe() is invoked for the matching devices.  The
+ * auxiliary_driver can also be encapsulated inside custom drivers that make
+ * the core device's functionality extensible by adding additional
+ * domain-specific ops as follows:
+ *
+ * .. code-block:: c
+ *
+ *    struct my_ops {
+ *        void (*send)(struct auxiliary_device *auxdev);
+ *        void (*receive)(struct auxiliary_device *auxdev);
+ *    };
+ *
+ *
+ *    struct my_driver {
+ *        struct auxiliary_driver auxiliary_drv;
+ *        const struct my_ops ops;
+ *    };
+ *
+ * An example of this type of usage is:
+ *
+ * .. code-block:: c
+ *
+ *    const struct auxiliary_device_id my_auxiliary_id_table[] = {
+ *        { .name = "foo_mod.foo_dev" },
+ *        { },
+ *    };
+ *
+ *    const struct my_ops my_custom_ops = {
+ *        .send = my_tx,
+ *        .receive = my_rx,
+ *    };
+ *
+ *    const struct my_driver my_drv = {
+ *        .auxiliary_drv = {
+ *            .name = "myauxiliarydrv",
+ *            .id_table = my_auxiliary_id_table,
+ *            .probe = my_probe,
+ *            .remove = my_remove,
+ *            .shutdown = my_shutdown,
+ *        },
+ *        .ops = my_custom_ops,
+ *    };
+ */
+
+static const struct auxiliary_device_id *
+auxiliary_match_id(const struct auxiliary_device_id *id,
+				   const struct auxiliary_device *auxdev)
+{
+	for (; id->name[0]; id++) {
+		const char *p = strrchr(dev_name(&auxdev->dev), '.');
+		int32_t match_size;
+
+		if (!p) {
+			continue;
+		}
+		match_size = p - dev_name(&auxdev->dev);
+
+		/* use dev_name(&auxdev->dev) prefix before last '.' char to match to */
+		if (strlen(id->name) == match_size &&
+			!strncmp(dev_name(&auxdev->dev), id->name, match_size)) {
+			return id;
+		}
+	}
+
+	return NULL;
+}
+
+static int32_t auxiliary_match(struct device *dev, struct device_driver *drv)
+{
+	struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
+	struct auxiliary_driver *auxdrv = to_auxiliary_drv(drv);
+
+	return !!auxiliary_match_id(auxdrv->id_table, auxdev);
+}
+
+static int32_t auxiliary_uevent(struct device *dev, struct kobj_uevent_env *env)
+{
+	const char *name;
+	const char *p;
+
+	name = dev_name(dev);
+	p = strrchr(name, '.');
+
+	return add_uevent_var(env, "MODALIAS=%s%.*s", AUXILIARY_MODULE_PREFIX,
+						  (int32_t)(p - name), name);
+}
+
+static const struct dev_pm_ops auxiliary_dev_pm_ops = { SET_RUNTIME_PM_OPS(
+		pm_generic_runtime_suspend, pm_generic_runtime_resume,
+		NULL) SET_SYSTEM_SLEEP_PM_OPS(pm_generic_suspend, pm_generic_resume) };
+
+static int32_t auxiliary_bus_probe(struct device *dev)
+{
+	struct auxiliary_driver *auxdrv = to_auxiliary_drv(dev->driver);
+	struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
+	int32_t ret = 0;
+
+#ifdef HAVE_DEV_PM_DOMAIN_ATTACH
+	ret = dev_pm_domain_attach(dev, true);
+
+	/* In case of old kernels 4.17 and below do nothing in case of
+   * failure of ENODEV */
+	if (ret == -ENODEV) {
+		ret = 0;
+	}
+
+	if (ret != 0) {
+		LOG_WARN("Failed to attach to PM Domain : %d\n", ret);
+		return ret;
+	}
+#else
+	acpi_dev_pm_attach(dev, true);
+#endif
+
+	ret = auxdrv->probe(auxdev, auxiliary_match_id(auxdrv->id_table, auxdev));
+	if (ret != 0)
+#ifdef HAVE_DEV_PM_DOMAIN_ATTACH
+		dev_pm_domain_detach(dev, true);
+#else
+		acpi_dev_pm_detach(dev, true);
+#endif
+
+	return ret;
+}
+
+#ifdef HAVE_BUS_TYPE_REMOVE_RETURN_VOID
+static void auxiliary_bus_remove(struct device *dev)
+#else
+static int32_t auxiliary_bus_remove(struct device *dev)
+#endif
+{
+	struct auxiliary_driver *auxdrv = to_auxiliary_drv(dev->driver);
+	struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
+
+	if (auxdrv->remove) {
+		auxdrv->remove(auxdev);
+	}
+#ifdef HAVE_DEV_PM_DOMAIN_ATTACH
+	dev_pm_domain_detach(dev, true);
+#else
+	acpi_dev_pm_detach(dev, true);
+#endif
+
+#ifndef HAVE_BUS_TYPE_REMOVE_RETURN_VOID
+	return 0;
+#endif
+}
+
+static void auxiliary_bus_shutdown(struct device *dev)
+{
+	struct auxiliary_driver *auxdrv = NULL;
+	struct auxiliary_device *auxdev = NULL;
+
+	if (dev->driver) {
+		auxdrv = to_auxiliary_drv(dev->driver);
+		auxdev = to_auxiliary_dev(dev);
+	}
+
+	if (auxdrv && auxdrv->shutdown) {
+		auxdrv->shutdown(auxdev);
+	}
+}
+
+static struct bus_type auxiliary_bus_type = {
+	.name = "auxiliary",
+	.probe = auxiliary_bus_probe,
+	.remove = auxiliary_bus_remove,
+	.shutdown = auxiliary_bus_shutdown,
+	.match = auxiliary_match,
+	.uevent = auxiliary_uevent,
+	.pm = &auxiliary_dev_pm_ops,
+};
+
+/**
+ * auxiliary_device_init - check auxiliary_device and initialize
+ * @auxdev: auxiliary device struct
+ *
+ * This is the second step in the three-step process to register an
+ * auxiliary_device.
+ *
+ * When this function returns an error code, then the device_initialize will
+ * *not* have been performed, and the caller will be responsible to free any
+ * memory allocated for the auxiliary_device in the error path directly.
+ *
+ * It returns 0 on success.  On success, the device_initialize has been
+ * performed.  After this point any error unwinding will need to include a call
+ * to auxiliary_device_uninit().  In this post-initialize error scenario, a call
+ * to the device's .release callback will be triggered, and all memory clean-up
+ * is expected to be handled there.
+ */
+int32_t auxiliary_device_init(struct auxiliary_device *auxdev)
+{
+	struct device *dev = &auxdev->dev;
+
+	if (!dev->parent) {
+		LOG_ERR("auxiliary_device has a NULL dev->parent\n");
+		return -EINVAL;
+	}
+
+	if (!auxdev->name) {
+		LOG_ERR("auxiliary_device has a NULL name\n");
+		return -EINVAL;
+	}
+
+	dev->bus = &auxiliary_bus_type;
+	device_initialize(&auxdev->dev);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(auxiliary_device_init);
+
+/**
+ * __auxiliary_device_add - add an auxiliary bus device
+ * @auxdev: auxiliary bus device to add to the bus
+ * @modname: name of the parent device's driver module
+ *
+ * This is the third step in the three-step process to register an
+ * auxiliary_device.
+ *
+ * This function must be called after a successful call to
+ * auxiliary_device_init(), which will perform the device_initialize.  This
+ * means that if this returns an error code, then a call to
+ * auxiliary_device_uninit() must be performed so that the .release callback
+ * will be triggered to free the memory associated with the auxiliary_device.
+ *
+ * The expectation is that users will call the "auxiliary_device_add" macro so
+ * that the caller's KBUILD_MODNAME is automatically inserted for the modname
+ * parameter.  Only if a user requires a custom name would this version be
+ * called directly.
+ */
+int32_t __auxiliary_device_add(struct auxiliary_device *auxdev,
+							   const char *modname)
+{
+	struct device *dev = &auxdev->dev;
+	int32_t ret = 0;
+
+	if (!modname) {
+		LOG_ERR("auxiliary device modname is NULL\n");
+		return -EINVAL;
+	}
+
+	ret = dev_set_name(dev, "%s.%s.%d", modname, auxdev->name, auxdev->id);
+	if (ret != 0) {
+		LOG_ERR("auxiliary device dev_set_name failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = device_add(dev);
+	if (ret != 0) {
+		LOG_ERR("adding auxiliary device failed!: %d\n", ret);
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(__auxiliary_device_add);
+
+/**
+ * auxiliary_find_device - auxiliary device iterator for locating a particular
+ * device.
+ * @start: Device to begin with
+ * @data: Data to pass to match function
+ * @match: Callback function to check device
+ *
+ * This function returns a reference to a device that is 'found'
+ * for later use, as determined by the @match callback.
+ *
+ * The reference returned should be released with put_device().
+ *
+ * The callback should return 0 if the device doesn't match and non-zero
+ * if it does.  If the callback returns non-zero, this function will
+ * return to the caller and not iterate over any more devices.
+ */
+#if defined(HAVE_LINUX_DEVICE_BUS_H) || defined(HAVE_BUS_FIND_DEVICE_GET_CONST)
+struct auxiliary_device *
+auxiliary_find_device(struct device *start, const void *data,
+					  int32_t (*match)(struct device *dev, const void *data))
+#else
+struct auxiliary_device *
+auxiliary_find_device(struct device *start, void *data,
+					  int32_t (*match)(struct device *dev, void *data))
+#endif /* HAVE_BUS_FIND_DEVICE_GET_CONST || HAVE_LINUX_DEVICE_BUS_H */
+{
+	struct device *dev = NULL;
+
+	dev = bus_find_device(&auxiliary_bus_type, start, data, match);
+	if (dev == NULL) {
+		return NULL;
+	}
+
+	return to_auxiliary_dev(dev);
+}
+EXPORT_SYMBOL_GPL(auxiliary_find_device);
+
+/**
+ * __auxiliary_driver_register - register a driver for auxiliary bus devices
+ * @auxdrv: auxiliary_driver structure
+ * @owner: owning module/driver
+ * @modname: KBUILD_MODNAME for parent driver
+ *
+ * The expectation is that users will call the "auxiliary_driver_register"
+ * macro so that the caller's KBUILD_MODNAME is automatically inserted for the
+ * modname parameter.  Only if a user requires a custom name would this version
+ * be called directly.
+ */
+int32_t __auxiliary_driver_register(struct auxiliary_driver *auxdrv,
+									struct module *owner, const char *modname)
+{
+	int32_t ret = 0;
+
+	if (WARN_ON(!auxdrv->probe) || WARN_ON(!auxdrv->id_table)) {
+		return -EINVAL;
+	}
+
+	if (auxdrv->name) {
+		auxdrv->driver.name =
+				kasprintf(GFP_KERNEL, "%s.%s", modname, auxdrv->name);
+	} else {
+		auxdrv->driver.name = kasprintf(GFP_KERNEL, "%s", modname);
+	}
+	if (!auxdrv->driver.name) {
+		return -ENOMEM;
+	}
+
+	auxdrv->driver.owner = owner;
+	auxdrv->driver.bus = &auxiliary_bus_type;
+	auxdrv->driver.mod_name = modname;
+
+	ret = driver_register(&auxdrv->driver);
+	if (ret) {
+		kfree(auxdrv->driver.name);
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(__auxiliary_driver_register);
+
+/**
+ * auxiliary_driver_unregister - unregister a driver
+ * @auxdrv: auxiliary_driver structure
+ */
+void auxiliary_driver_unregister(struct auxiliary_driver *auxdrv)
+{
+	driver_unregister(&auxdrv->driver);
+	kfree(auxdrv->driver.name);
+}
+EXPORT_SYMBOL_GPL(auxiliary_driver_unregister);
+
+#ifdef CONFIG_COMPAT_AUXILIARY_EXTERNAL_INIT
+void __init auxiliary_bus_init(void)
+{
+	WARN_ON(bus_register(&auxiliary_bus_type));
+}
+#else
+static int32_t __init auxiliary_bus_init(void)
+{
+	return bus_register(&auxiliary_bus_type);
+}
+
+static void __exit auxiliary_bus_exit(void)
+{
+	bus_unregister(&auxiliary_bus_type);
+}
+
+module_init(auxiliary_bus_init);
+module_exit(auxiliary_bus_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Auxiliary Bus");
+MODULE_INFO(supported, "external");
+MODULE_AUTHOR("David Ertman <david.m.ertman@intel.com>");
+MODULE_AUTHOR("Kiran Patil <kiran.patil@intel.com>");
+#endif
diff --git a/src/net/drivers/base/en_auxiliary.c b/src/net/drivers/base/en_auxiliary.c
deleted file mode 100644
index fb7232b8f67f54bc6da3e505ac89eec72602d35c..0000000000000000000000000000000000000000
--- a/src/net/drivers/base/en_auxiliary.c
+++ /dev/null
@@ -1,368 +0,0 @@
-
-#ifdef pr_fmt
-#undef pr_fmt
-#endif
-
-#define pr_fmt(fmt) "%s:%s: " fmt, KBUILD_MODNAME, __func__
-
-#include <linux/dinghai/driver.h>
-#include <linux/device.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/pm_domain.h>
-#include <linux/pm_runtime.h>
-#include <linux/string.h>
-#include <linux/dinghai/auxiliary_bus.h>
-#include <linux/acpi.h>
-#ifdef CONFIG_COMPAT_AUXILIARY_EXTERNAL_INIT
-#include "base.h"
-#endif
-
-
-static const struct zxdh_auxiliary_device_id *zxdh_auxiliary_match_id(const struct zxdh_auxiliary_device_id *id,
-                                                                      const struct zxdh_auxiliary_device *auxdev)
-{
-    for (; id->name[0]; id++)
-    {
-        const char *p = strrchr(dev_name(&auxdev->dev), '.');
-        int32_t match_size;
-
-        if (!p)
-        {
-            continue;
-        }
-        match_size = p - dev_name(&auxdev->dev);
-
-        /* use dev_name(&auxdev->dev) prefix before last '.' char to match to */
-        if (strlen(id->name) == match_size &&
-            !strncmp(dev_name(&auxdev->dev), id->name, match_size))
-        {
-            return id;
-        }
-    }
-
-    return NULL;
-}
-
-static int32_t zxdh_auxiliary_match(struct device *dev, struct device_driver *drv)
-{
-    struct zxdh_auxiliary_device *auxdev = zxdh_to_auxiliary_dev(dev);
-    struct zxdh_auxiliary_driver *auxdrv = zxdh_to_auxiliary_drv(drv);
-
-    return !!zxdh_auxiliary_match_id(auxdrv->id_table, auxdev);
-}
-
-static int32_t zxdh_auxiliary_uevent(struct device *dev, struct kobj_uevent_env *env)
-{
-    const char *name;
-    const char *p;
-
-    name = dev_name(dev);
-    p = strrchr(name, '.');
-
-    return add_uevent_var(env, "MODALIAS=%s%.*s", ZXDH_AUXILIARY_MODULE_PREFIX, (int32_t)(p - name), name);
-}
-
-static const struct dev_pm_ops zxdh_auxiliary_dev_pm_ops = {
-    SET_RUNTIME_PM_OPS(pm_generic_runtime_suspend, pm_generic_runtime_resume, NULL)
-    SET_SYSTEM_SLEEP_PM_OPS(pm_generic_suspend, pm_generic_resume)
-};
-
-static int32_t zxdh_auxiliary_bus_probe(struct device *dev)
-{
-    struct zxdh_auxiliary_driver *auxdrv = zxdh_to_auxiliary_drv(dev->driver);
-    struct zxdh_auxiliary_device *auxdev = zxdh_to_auxiliary_dev(dev);
-    int32_t ret = 0;
-
-#ifdef HAVE_DEV_PM_DOMAIN_ATTACH
-    ret = dev_pm_domain_attach(dev, true);
-
-    /* In case of old kernels 4.17 and below do nothing in case of
-     * failure of ENODEV */
-    if (ret == -ENODEV)
-    {
-        ret = 0;
-    }
-
-    if (ret != 0)
-    {
-        LOG_WARN("Failed to attach to PM Domain : %d\n", ret);
-        return ret;
-    }
-#else
-    acpi_dev_pm_attach(dev, true);
-#endif
-
-    ret = auxdrv->probe(auxdev, zxdh_auxiliary_match_id(auxdrv->id_table, auxdev));
-    if (ret != 0)
-#ifdef HAVE_DEV_PM_DOMAIN_ATTACH
-        dev_pm_domain_detach(dev, true);
-#else
-        acpi_dev_pm_detach(dev, true);
-#endif
-
-    return ret;
-}
-
-#ifdef HAVE_BUS_TYPE_REMOVE_RETURN_VOID
-static void zxdh_auxiliary_bus_remove(struct device *dev)
-#else
-static int32_t zxdh_auxiliary_bus_remove(struct device *dev)
-#endif
-{
-    struct zxdh_auxiliary_driver *auxdrv = zxdh_to_auxiliary_drv(dev->driver);
-    struct zxdh_auxiliary_device *auxdev = zxdh_to_auxiliary_dev(dev);
-
-    if (auxdrv->remove)
-    {
-        auxdrv->remove(auxdev);
-    }
-#ifdef HAVE_DEV_PM_DOMAIN_ATTACH
-    dev_pm_domain_detach(dev, true);
-#else
-    acpi_dev_pm_detach(dev, true);
-#endif
-
-#ifndef HAVE_BUS_TYPE_REMOVE_RETURN_VOID
-    return 0;
-#endif
-}
-
-static void zxdh_auxiliary_bus_shutdown(struct device *dev)
-{
-    struct zxdh_auxiliary_driver *auxdrv = NULL;
-    struct zxdh_auxiliary_device *auxdev = NULL;
-
-    if (dev->driver)
-    {
-        auxdrv = zxdh_to_auxiliary_drv(dev->driver);
-        auxdev = zxdh_to_auxiliary_dev(dev);
-    }
-
-    if (auxdrv && auxdrv->shutdown)
-    {
-        auxdrv->shutdown(auxdev);
-    }
-}
-
-static struct bus_type zxdh_auxiliary_bus_type = {
-    .name     = "zxdh_auxiliary",
-    .probe    = zxdh_auxiliary_bus_probe,
-    .remove   = zxdh_auxiliary_bus_remove,
-    .shutdown = zxdh_auxiliary_bus_shutdown,
-    .match    = zxdh_auxiliary_match,
-    .uevent   = zxdh_auxiliary_uevent,
-    .pm       = &zxdh_auxiliary_dev_pm_ops,
-};
-
-/**
- * zxdh_auxiliary_device_init - check zxdh_auxiliary_device and initialize
- * @auxdev: auxiliary device struct
- *
- * This is the second step in the three-step process to register an
- * zxdh_auxiliary_device.
- *
- * When this function returns an error code, then the device_initialize will
- * *not* have been performed, and the caller will be responsible to free any
- * memory allocated for the zxdh_auxiliary_device in the error path directly.
- *
- * It returns 0 on success.  On success, the device_initialize has been
- * performed.  After this point any error unwinding will need to include a call
- * to zxdh_auxiliary_device_uninit().  In this post-initialize error scenario, a call
- * to the device's .release callback will be triggered, and all memory clean-up
- * is expected to be handled there.
- */
-int32_t zxdh_auxiliary_device_init(struct zxdh_auxiliary_device *auxdev)
-{
-    struct device *dev = &auxdev->dev;
-
-    if (!dev->parent)
-    {
-        LOG_ERR("zxdh_auxiliary_device has a NULL dev->parent\n");
-        return -EINVAL;
-    }
-
-    if (!auxdev->name)
-    {
-        LOG_ERR("zxdh_auxiliary_device has a NULL name\n");
-        return -EINVAL;
-    }
-
-    dev->bus = &zxdh_auxiliary_bus_type;
-    device_initialize(&auxdev->dev);
-
-    return 0;
-}
-EXPORT_SYMBOL_GPL(zxdh_auxiliary_device_init);
-
-/**
- * zxdh_aux_dev_add - add an auxiliary bus device
- * @auxdev: auxiliary bus device to add to the bus
- * @modname: name of the parent device's driver module
- *
- * This is the third step in the three-step process to register an
- * zxdh_auxiliary_device.
- *
- * This function must be called after a successful call to
- * zxdh_auxiliary_device_init(), which will perform the device_initialize.  This
- * means that if this returns an error code, then a call to
- * zxdh_auxiliary_device_uninit() must be performed so that the .release callback
- * will be triggered to free the memory associated with the zxdh_auxiliary_device.
- *
- * The expectation is that users will call the "zxdh_auxiliary_device_add" macro so
- * that the caller's KBUILD_MODNAME is automatically inserted for the modname
- * parameter.  Only if a user requires a custom name would this version be
- * called directly.
- */
-int32_t zxdh_aux_dev_add(struct zxdh_auxiliary_device *auxdev, const char *modname)
-{
-    struct device *dev = &auxdev->dev;
-    int32_t ret        = 0;
-
-    if (!modname)
-    {
-        LOG_ERR( "zxdh auxiliary device modname is NULL\n");
-        return -EINVAL;
-    }
-
-    ret = dev_set_name(dev, "%s.%s.%d", modname, auxdev->name, auxdev->id);
-    if (ret != 0)
-    {
-        LOG_ERR( "zxdh auxiliary device dev_set_name failed: %d\n", ret);
-        return ret;
-    }
-
-    ret = device_add(dev);
-    if (ret != 0)
-    {
-        LOG_ERR( "adding zxdh auxiliary device failed!: %d\n", ret);
-    }
-
-    return ret;
-}
-EXPORT_SYMBOL_GPL(zxdh_aux_dev_add);
-
-/**
- * zxdh_auxiliary_find_device - auxiliary device iterator for locating a particular device.
- * @start: Device to begin with
- * @data: Data to pass to match function
- * @match: Callback function to check device
- *
- * This function returns a reference to a device that is 'found'
- * for later use, as determined by the @match callback.
- *
- * The reference returned should be released with put_device().
- *
- * The callback should return 0 if the device doesn't match and non-zero
- * if it does.  If the callback returns non-zero, this function will
- * return to the caller and not iterate over any more devices.
- */
-#if defined(HAVE_LINUX_DEVICE_BUS_H) || defined(HAVE_BUS_FIND_DEVICE_GET_CONST)
-struct zxdh_auxiliary_device *
-zxdh_auxiliary_find_device(struct device *start,
-                           const void *data,
-                           int32_t (*match)(struct device *dev, const void *data))
-#else
-struct zxdh_auxiliary_device *
-zxdh_auxiliary_find_device(struct device *start,
-                           void *data,
-                           int32_t (*match)(struct device *dev, void *data))
-#endif /* HAVE_BUS_FIND_DEVICE_GET_CONST || HAVE_LINUX_DEVICE_BUS_H */
-{
-    struct device *dev = NULL;
-
-    dev = bus_find_device(&zxdh_auxiliary_bus_type, start, data, match);
-    if (dev == NULL)
-    {
-        return NULL;
-    }
-
-    return zxdh_to_auxiliary_dev(dev);
-}
-EXPORT_SYMBOL_GPL(zxdh_auxiliary_find_device);
-
-/**
- * zxdh_aux_drv_register - register a driver for auxiliary bus devices
- * @auxdrv: zxdh_auxiliary_driver structure
- * @owner: owning module/driver
- * @modname: KBUILD_MODNAME for parent driver
- *
- * The expectation is that users will call the "zxdh_auxiliary_driver_register"
- * macro so that the caller's KBUILD_MODNAME is automatically inserted for the
- * modname parameter.  Only if a user requires a custom name would this version
- * be called directly.
- */
-int32_t zxdh_aux_drv_register(struct zxdh_auxiliary_driver *auxdrv,
-                              struct module *owner, const char *modname)
-{
-    int32_t ret = 0;
-
-    if (WARN_ON(!auxdrv->probe) || WARN_ON(!auxdrv->id_table))
-    {
-        return -EINVAL;
-    }
-
-    if (auxdrv->name)
-    {
-        auxdrv->driver.name = kasprintf(GFP_KERNEL, "%s.%s", modname, auxdrv->name);
-    }
-    else
-    {
-        auxdrv->driver.name = kasprintf(GFP_KERNEL, "%s", modname);
-    }
-    if (!auxdrv->driver.name)
-    {
-        return -ENOMEM;
-    }
-
-    auxdrv->driver.owner = owner;
-    auxdrv->driver.bus = &zxdh_auxiliary_bus_type;
-    auxdrv->driver.mod_name = modname;
-
-    ret = driver_register(&auxdrv->driver);
-    if (ret)
-    {
-        kfree(auxdrv->driver.name);
-    }
-
-    return ret;
-}
-EXPORT_SYMBOL_GPL(zxdh_aux_drv_register);
-
-/**
- * zxdh_auxiliary_driver_unregister - unregister a driver
- * @auxdrv: zxdh_auxiliary_driver structure
- */
-void zxdh_auxiliary_driver_unregister(struct zxdh_auxiliary_driver *auxdrv)
-{
-    driver_unregister(&auxdrv->driver);
-    kfree(auxdrv->driver.name);
-}
-EXPORT_SYMBOL_GPL(zxdh_auxiliary_driver_unregister);
-
-#ifdef CONFIG_COMPAT_AUXILIARY_EXTERNAL_INIT
-void __init zxdh_auxiliary_bus_init(void)
-{
-    WARN_ON(bus_register(&zxdh_auxiliary_bus_type));
-}
-#else
-static int32_t __init zxdh_auxiliary_bus_init(void)
-{
-    return bus_register(&zxdh_auxiliary_bus_type);
-}
-
-static void __exit zxdh_auxiliary_bus_exit(void)
-{
-    bus_unregister(&zxdh_auxiliary_bus_type);
-}
-
-module_init(zxdh_auxiliary_bus_init);
-module_exit(zxdh_auxiliary_bus_exit);
-
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("Auxiliary Bus");
-MODULE_INFO(supported, "external");
-MODULE_AUTHOR("David Ertman <david.m.ertman@intel.com>");
-MODULE_AUTHOR("Kiran Patil <kiran.patil@intel.com>");
-#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/Kconfig b/src/net/drivers/net/ethernet/dinghai/Kconfig
old mode 100755
new mode 100644
diff --git a/src/net/drivers/net/ethernet/dinghai/Makefile b/src/net/drivers/net/ethernet/dinghai/Makefile
old mode 100755
new mode 100644
index 2f40270519ad16d50e0cbf0fd151457229f53afe..4e5173101c4a5121b458300df9e6599be4ee2417
--- a/src/net/drivers/net/ethernet/dinghai/Makefile
+++ b/src/net/drivers/net/ethernet/dinghai/Makefile
@@ -1,8 +1,10 @@
 subdir-ccflags-y += -I$(src)
 subdir-ccflags-y += -I$(CWD)/include/
 subdir-ccflags-y += -include $(CWD)/autoconf.h
-ccflags-y += -Werror
 
+ifeq (${NEED_AUX_BUS},2)
+EXTRA_CFLAGS += -DAUX_BUS_NO_SUPPORT
+endif
 
 ifeq ($(CONFIG_ZXDH_MSGQ),m)
 EXTRA_CFLAGS += -DZXDH_MSGQ
@@ -12,14 +14,6 @@ ifeq ($(CONFIG_DINGHAI_SEC),m)
 EXTRA_CFLAGS += -DZXDH_SEC
 endif
 
-ifeq ($(CONFIG_DRIVER_VERSION),)
-EXTRA_CFLAGS += -DDRIVER_VERSION_VAL=\"1.0-1\"
-$(info CONFIG_PF_MPF_DRIVER_VERSION is null, EXTRA_CFLAGS=$(EXTRA_CFLAGS))
-else
-EXTRA_CFLAGS += -DDRIVER_VERSION_VAL=\"$(CONFIG_DRIVER_VERSION)\"
-$(info CONFIG_PF_MPF_DRIVER_VERSION is not null, EXTRA_CFLAGS=$(EXTRA_CFLAGS))
-endif
-
 obj-$(CONFIG_DINGHAI_DH_CMD) += zxdh_cmd.o
 zxdh_cmd-y := dh_cmd.o  cmd/msg_main.o cmd/msg_chan_lock.o cmd/msg_chan_test.o
 
@@ -34,14 +28,14 @@ ifdef PCIE_ZF_EPC_OPEN
 zxdh_zf_mpf-y := events.o eq.o pci_irq.o devlink.o \
                 zf_mpf/zf_mpf.o zf_mpf/zf_events.o zf_mpf/irq.o zf_mpf/eq.o zf_mpf/devlink.o zf_mpf/cfg_sf.o \
                 zf_mpf/epc/pcie-zte-zf-epc.o zf_mpf/epc/pcie-zte-zf-hdma.o zf_mpf/epc/virt-dma.o zf_mpf/zxdh_reset_zf.o \
-                zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.o zf_mpf/fuc_hotplug/fuc_hotplug.o zf_mpf/zf_reset_finish_flag.o zf_mpf/zf_chan_ioctl.o
+                zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.o zf_mpf/fuc_hotplug/fuc_hotplug.o zf_mpf/zf_reset_finish_flag.o
 obj-m += zxdh_zf_epf.o
 my_api-objs := zf_mpf/epc/pcie-zte-zf-epc.o
 zxdh_zf_epf-y := zf_mpf/epf/pcie-zte-zf-epf.o
 else
 zxdh_zf_mpf-y := events.o eq.o pci_irq.o devlink.o \
                 zf_mpf/zf_mpf.o zf_mpf/zf_events.o zf_mpf/irq.o zf_mpf/eq.o zf_mpf/devlink.o zf_mpf/cfg_sf.o zf_mpf/zxdh_reset_zf.o \
-                zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.o zf_mpf/fuc_hotplug/fuc_hotplug.o zf_mpf/zf_reset_finish_flag.o zf_mpf/zf_chan_ioctl.o
+                zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.o zf_mpf/fuc_hotplug/fuc_hotplug.o zf_mpf/zf_reset_finish_flag.o
 endif
 zxdh_zf_mpf-$(CONFIG_ZXDH_SF) += irq_affinity.o en_sf.o en_sf/eq.o en_sf/irq.o en_sf/devlink.o
 zxdh_zf_mpf-$(CONFIG_ZF_GDMA) += zf_mpf/gdma.o
@@ -55,17 +49,15 @@ zxdh_pf-$(CONFIG_ZXDH_SF) += irq_affinity.o en_sf.o en_sf/eq.o en_sf/irq.o en_sf
 obj-$(CONFIG_DINGHAI_EN_AUX) += zxdh_en_aux.o
 zxdh_en_aux-y := en_aux.o eq.o pci_irq.o irq_affinity.o en_aux/queue.o en_aux/en_cmd.o en_aux/eq.o \
                  en_aux/events.o en_ethtool/ethtool.o en_aux/en_ioctl.o \
-                 en_aux/dcbnl/en_dcbnl.o en_aux/dcbnl/en_dcbnl_api.o \
+                 en_aux/dcbnl/en_dcbnl.o en_aux/dcbnl/en_dcbnl_api.o en_plcr.o \
                  zxdh_tools/zxdh_tools_ioctl.o zxdh_tools/zxdh_tools_netlink.o
 zxdh_en_aux-$(CONFIG_ZXDH_1588) += en_aux/en_1588_pkt_proc.o en_aux/en_1588_pkt_proc_func.o
 zxdh_en_aux-$(CONFIG_DINGHAI_SEC) += en_aux/drs_sec_dtb.o
 zxdh_en_aux-$(CONFIG_ZXDH_MSGQ) += en_aux/priv_queue.o
 
 obj-$(CONFIG_DINGHAI_PTP)  += zxdh_ptp.o
-zxdh_ptp-y :=en_ptp/tod_driver.o en_ptp/tod_driver_stub.o en_ptp/zxdh_ptp.o
 
-obj-$(CONFIG_DINGHAI_TSN)  += zxdh_tsn.o
-zxdh_tsn-y :=en_tsn/zxdh_tsn.o en_tsn/zxdh_tsn_reg.o en_tsn/zxdh_tsn_ioctl.o
+zxdh_ptp-y :=en_ptp/tod_driver.o en_ptp/tod_driver_stub.o en_ptp/zxdh_ptp.o
 
 include $(CWD)/drivers/net/ethernet/dinghai/en_np/Makefile
 
diff --git a/src/net/drivers/net/ethernet/dinghai/cmd.c b/src/net/drivers/net/ethernet/dinghai/cmd.c
old mode 100755
new mode 100644
index a8e46fc19f2e625ba93207c46a4848529998e0db..fc2e8ae861f4c3d088ff11f179bcb2eb355ddef1
--- a/src/net/drivers/net/ethernet/dinghai/cmd.c
+++ b/src/net/drivers/net/ethernet/dinghai/cmd.c
@@ -1,35 +1,38 @@
-#include <linux/dinghai/driver.h>
-#include <linux/types.h>
-#include <linux/dinghai/device.h>
-#include <linux/dinghai/dh_ifc.h>
-
-static int32_t cmd_status_err(struct dh_core_dev *dev, int32_t err, uint16_t opcode, void *out)
-{
-    u8 status = DH_GET(mbox_out, out, status);
-
-    return err;
-}
-static int32_t cmd_exec(struct dh_core_dev *dev, void *in, int32_t in_size, void *out,
-                        int32_t out_size, zxdh_cmd_cbk_t callback, void *context,
-                        bool force_polling)
-{
-    return 0;
-}
-
-int32_t zxdh_cmd_do(struct dh_core_dev *dev, void *in, int32_t in_size, void *out, int32_t out_size)
-{
-    int32_t err     = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
-    uint16_t opcode = DH_GET(mbox_in, in, opcode);
-
-    err = cmd_status_err(dev, err, opcode, out);
-
-    return err;
-}
-EXPORT_SYMBOL(zxdh_cmd_do);
-
-int32_t zxdh_cmd_exec(struct dh_core_dev *dev, void *in, int32_t in_size, void *out, int32_t out_size)
-{
-    int32_t err = zxdh_cmd_do(dev, in, in_size, out, out_size);
-
-    return zxdh_cmd_check(dev, err, in, out);
+#include <linux/dinghai/driver.h>
+#include <linux/types.h>
+#include <linux/dinghai/device.h>
+#include <linux/dinghai/dh_ifc.h>
+
+static int32_t cmd_status_err(struct dh_core_dev *dev, int32_t err,
+							  uint16_t opcode, void *out)
+{
+	u8 status = DH_GET(mbox_out, out, status);
+
+	return err;
+}
+static int32_t cmd_exec(struct dh_core_dev *dev, void *in, int32_t in_size,
+						void *out, int32_t out_size, zxdh_cmd_cbk_t callback,
+						void *context, bool force_polling)
+{
+	return 0;
+}
+
+int32_t zxdh_cmd_do(struct dh_core_dev *dev, void *in, int32_t in_size,
+					void *out, int32_t out_size)
+{
+	int32_t err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
+	uint16_t opcode = DH_GET(mbox_in, in, opcode);
+
+	err = cmd_status_err(dev, err, opcode, out);
+
+	return err;
+}
+EXPORT_SYMBOL(zxdh_cmd_do);
+
+int32_t zxdh_cmd_exec(struct dh_core_dev *dev, void *in, int32_t in_size,
+					  void *out, int32_t out_size)
+{
+	int32_t err = zxdh_cmd_do(dev, in, in_size, out, out_size);
+
+	return zxdh_cmd_check(dev, err, in, out);
 }
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_lock.c b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_lock.c
index daf77d40b2072ae6909220c9bc19e868c6dcee13..541c91a17b363df3728215751481c9a68b3c710c 100644
--- a/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_lock.c
+++ b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_lock.c
@@ -1,6 +1,7 @@
 #include <linux/mutex.h>
 #include "msg_chan_lock.h"
 #include "msg_chan_priv.h"
+
 /*****************************************
 [src/dst]时应该将消息发到硬件锁还是软件所
 src/dst: TO_RISC, TO_PFVF, TO_MPF
@@ -10,13 +11,12 @@ VF:        0         0       1
 ******************************************/
 
 /*/PF0-7 DIRECT_CHNA/(PF0)VF0-VF32/(PF1)VF0-VF32/...*/
-struct mutex lock_array[LOCK_ARR_LENGTH] = {0};
+struct mutex lock_array[LOCK_ARR_LENGTH] = { 0 };
 
-uint8_t lock_type_tbl[BAR_MSG_SRC_NUM][BAR_MSG_DST_NUM] =
-{
-    {LOCK_TYPE_HARD, LOCK_TYPE_HARD, LOCK_TYPE_HARD},
-    {LOCK_TYPE_SOFT, LOCK_TYPE_SOFT, LOCK_TYPE_HARD},
-    {LOCK_TYPE_HARD, LOCK_TYPE_HARD, LOCK_TYPE_HARD}
+uint8_t lock_type_tbl[BAR_MSG_SRC_NUM][BAR_MSG_DST_NUM] = {
+	{ LOCK_TYPE_HARD, LOCK_TYPE_HARD, LOCK_TYPE_HARD },
+	{ LOCK_TYPE_SOFT, LOCK_TYPE_SOFT, LOCK_TYPE_HARD },
+	{ LOCK_TYPE_HARD, LOCK_TYPE_HARD, LOCK_TYPE_HARD }
 };
 
 /**
@@ -24,79 +24,73 @@ uint8_t lock_type_tbl[BAR_MSG_SRC_NUM][BAR_MSG_DST_NUM] =
  * @src_pcieid: pcie_id
  * @result: 软件数组的索引值
  */
-uint16_t pcieid_to_lockid(uint16_t src_pcieid,  uint8_t dst)
+uint16_t pcieid_to_lockid(uint16_t src_pcieid, uint8_t dst)
 {
-    uint16_t lock_id = 0;
-    uint16_t pf_idx = 0;
-    uint16_t vf_idx = 0;
-    uint16_t ep_idx = 0;
-
-    pf_idx = (src_pcieid & PCIEID_PF_IDX_MASK) >> PCIEID_PF_IDX_OFFSET;
-    vf_idx = (src_pcieid & PCIEID_VF_IDX_MASK);
-    ep_idx = (src_pcieid & PCIEID_EP_IDX_MASK) >> PCIEID_EP_IDX_OFFSET ;
-    switch (dst)
-    {
-    case MSG_CHAN_END_RISC:
-        {
-            if (src_pcieid & PCIEID_IS_PF_MASK)
-            {
-                lock_id = MULTIPLY_BY_8(ep_idx) + pf_idx;
-            }
-            else
-            {
-                lock_id =  MULTIPLY_BY_256(ep_idx) +  MULTIPLY_BY_32(pf_idx) + vf_idx + MULTIPLY_BY_32(1);
-            }
-            break;
-        }
-    case MSG_CHAN_END_VF:
-        {
-            lock_id = MULTIPLY_BY_8(ep_idx) + pf_idx + MULTIPLY_BY_32(1 + VF_NUM_PER_PF);
-            break;
-        }
-    case MSG_CHAN_END_PF:
-        {
-            lock_id = MULTIPLY_BY_8(ep_idx) + pf_idx + MULTIPLY_BY_32(2 + VF_NUM_PER_PF);
-            break;
-        }
-    default:
-        {
-            lock_id = 0;
-            break;
-        }
-    }
-
-    if (lock_id >= LOCK_ARR_LENGTH)
-    {
-        lock_id = 0;
-    }
-
-    return lock_id;
+	uint16_t lock_id = 0;
+	uint16_t pf_idx = 0;
+	uint16_t vf_idx = 0;
+	uint16_t ep_idx = 0;
+
+	pf_idx = (src_pcieid & PCIEID_PF_IDX_MASK) >> PCIEID_PF_IDX_OFFSET;
+	vf_idx = (src_pcieid & PCIEID_VF_IDX_MASK);
+	ep_idx = (src_pcieid & PCIEID_EP_IDX_MASK) >> PCIEID_EP_IDX_OFFSET;
+	switch (dst) {
+	case MSG_CHAN_END_RISC: {
+		if (src_pcieid & PCIEID_IS_PF_MASK) {
+			lock_id = MULTIPLY_BY_8(ep_idx) + pf_idx;
+		} else {
+			lock_id = MULTIPLY_BY_256(ep_idx) + MULTIPLY_BY_32(pf_idx) +
+					  vf_idx + MULTIPLY_BY_32(1);
+		}
+		break;
+	}
+	case MSG_CHAN_END_VF: {
+		lock_id = MULTIPLY_BY_8(ep_idx) + pf_idx +
+				  MULTIPLY_BY_32(1 + VF_NUM_PER_PF);
+		break;
+	}
+	case MSG_CHAN_END_PF: {
+		lock_id = MULTIPLY_BY_8(ep_idx) + pf_idx +
+				  MULTIPLY_BY_32(2 + VF_NUM_PER_PF);
+		break;
+	}
+	default: {
+		lock_id = 0;
+		break;
+	}
+	}
+
+	if (lock_id >= LOCK_ARR_LENGTH) {
+		lock_id = 0;
+	}
+
+	return lock_id;
 }
 
 void bar_soft_lock(uint16_t src_pcieid, uint8_t dst)
 {
-    uint16_t lockid = 0;
+	uint16_t lockid = 0;
 
-    lockid = pcieid_to_lockid(src_pcieid, dst);
-    mutex_lock(&lock_array[lockid]);
+	lockid = pcieid_to_lockid(src_pcieid, dst);
+	mutex_lock(&lock_array[lockid]);
 }
 
 void bar_soft_unlock(uint16_t src_pcieid, uint8_t dst)
 {
-    uint16_t lockid = 0;
+	uint16_t lockid = 0;
 
-    lockid = pcieid_to_lockid(src_pcieid, dst);
-    mutex_unlock(&lock_array[lockid]);
+	lockid = pcieid_to_lockid(src_pcieid, dst);
+	mutex_unlock(&lock_array[lockid]);
 }
 
 void bar_hard_lock(void)
 {
-    return;
+	return;
 }
 
 void bar_hard_unlock(void)
 {
-    return;
+	return;
 }
 
 /**
@@ -105,12 +99,11 @@ void bar_hard_unlock(void)
  */
 void bar_init_lock_arr(void)
 {
-    int idx = 0;
+	int idx = 0;
 
-    for (idx = 0; idx < ARR_LEN(lock_array); idx++)
-    {
-        mutex_init(&lock_array[idx]);
-    }
+	for (idx = 0; idx < ARR_LEN(lock_array); idx++) {
+		mutex_init(&lock_array[idx]);
+	}
 }
 
 /**
@@ -122,28 +115,24 @@ void bar_init_lock_arr(void)
  */
 int bar_chan_lock(uint8_t src, uint8_t dst, uint16_t src_pcieid)
 {
-    uint16_t idx = 0;
-    uint8_t src_index = 0;
-    uint8_t dst_index = 0;
-
-    src_index =  bar_msg_row_index_trans(src);
-    dst_index =  bar_msg_col_index_trans(dst);
-    if (src_index == BAR_MSG_SRC_ERR || dst_index == BAR_MSG_DST_ERR)
-    {
-        BAR_LOG_ERR("lock ERR: chan doesn't exist.\n");
-        return BAR_MSG_ERR_TYPE;
-    }
-    idx = lock_type_tbl[src_index][dst_index];
-    if (idx == LOCK_TYPE_SOFT)
-    {
-        bar_soft_lock(src_pcieid, dst);
-    }
-    else
-    {
-        bar_hard_lock();
-        BAR_LOG_INFO("hard_lock.\n");
-    }
-    return BAR_MSG_OK;
+	uint16_t idx = 0;
+	uint8_t src_index = 0;
+	uint8_t dst_index = 0;
+
+	src_index = __bar_msg_row_index_trans(src);
+	dst_index = __bar_msg_col_index_trans(dst);
+	if (src_index == BAR_MSG_SRC_ERR || dst_index == BAR_MSG_DST_ERR) {
+		BAR_LOG_ERR("lock ERR: chan doesn't exist.\n");
+		return BAR_MSG_ERR_TYPE;
+	}
+	idx = lock_type_tbl[src_index][dst_index];
+	if (idx == LOCK_TYPE_SOFT) {
+		bar_soft_lock(src_pcieid, dst);
+	} else {
+		bar_hard_lock();
+		BAR_LOG_INFO("hard_lock.\n");
+	}
+	return BAR_MSG_OK;
 }
 
 /**
@@ -155,25 +144,21 @@ int bar_chan_lock(uint8_t src, uint8_t dst, uint16_t src_pcieid)
  */
 int bar_chan_unlock(uint8_t src, uint8_t dst, uint16_t src_pcieid)
 {
-    uint16_t idx = 0;
-    uint8_t src_index = 0;
-    uint8_t dst_index = 0;
-
-    src_index =  bar_msg_row_index_trans(src);
-    dst_index =  bar_msg_col_index_trans(dst);
-    if (src_index == BAR_MSG_SRC_ERR || dst_index == BAR_MSG_DST_ERR)
-    {
-        BAR_LOG_ERR("unlock ERR: chan doesn't exist.\n");
-        return BAR_MSG_ERR_TYPE;
-    }
-    idx = lock_type_tbl[src_index][dst_index];
-    if (idx == LOCK_TYPE_SOFT)
-    {
-        bar_soft_unlock(src_pcieid, dst);
-    }
-    else
-    {
-        bar_hard_unlock();
-    }
-    return BAR_MSG_OK;
+	uint16_t idx = 0;
+	uint8_t src_index = 0;
+	uint8_t dst_index = 0;
+
+	src_index = __bar_msg_row_index_trans(src);
+	dst_index = __bar_msg_col_index_trans(dst);
+	if (src_index == BAR_MSG_SRC_ERR || dst_index == BAR_MSG_DST_ERR) {
+		BAR_LOG_ERR("unlock ERR: chan doesn't exist.\n");
+		return BAR_MSG_ERR_TYPE;
+	}
+	idx = lock_type_tbl[src_index][dst_index];
+	if (idx == LOCK_TYPE_SOFT) {
+		bar_soft_unlock(src_pcieid, dst);
+	} else {
+		bar_hard_unlock();
+	}
+	return BAR_MSG_OK;
 }
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_lock.h b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_lock.h
index beea9b0406170750ff71d0534f456a4d5653f514..93f6ad5aaddb21eec117216e2a9227bf266774a5 100644
--- a/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_lock.h
+++ b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_lock.h
@@ -5,35 +5,32 @@
 extern "C" {
 #endif
 
-#define ARR_LEN(arr)             (sizeof(arr)/sizeof(arr[0]))
+#define ARR_LEN(arr) (sizeof(arr) / sizeof(arr[0]))
 
 /* PCIEID位域掩码*/
-#define PCIEID_IS_PF_MASK        (0x0800)
-#define PCIEID_PF_IDX_MASK       (0x0700)
-#define PCIEID_VF_IDX_MASK       (0x00ff)
-#define PCIEID_EP_IDX_MASK       (0x7000)
-#define PF0_PCIEID               (0x0800)
+#define PCIEID_IS_PF_MASK (0x0800)
+#define PCIEID_PF_IDX_MASK (0x0700)
+#define PCIEID_VF_IDX_MASK (0x00ff)
+#define PCIEID_EP_IDX_MASK (0x7000)
+#define PF0_PCIEID (0x0800)
 
 /* PCIEID位域偏移*/
-#define PCIEID_PF_IDX_OFFSET     (8)
-#define PCIEID_EP_IDX_OFFSET     (12)
-
-
-
+#define PCIEID_PF_IDX_OFFSET (8)
+#define PCIEID_EP_IDX_OFFSET (12)
 
 /* 硬件锁软件锁*/
-#define LOCK_TYPE_HARD           0
-#define LOCK_TYPE_SOFT           0
+#define LOCK_TYPE_HARD 0
+#define LOCK_TYPE_SOFT 0
 
-#define  MAX_EP_NUM         4
-#define  PF_NUM_PER_EP      8
-#define  VF_NUM_PER_PF      32
+#define MAX_EP_NUM 4
+#define PF_NUM_PER_EP 8
+#define VF_NUM_PER_PF 32
 
-#define MULTIPLY_BY_8(x)   ((x) << 3)
-#define MULTIPLY_BY_32(x)  ((x) << 5)
+#define MULTIPLY_BY_8(x) ((x) << 3)
+#define MULTIPLY_BY_32(x) ((x) << 5)
 #define MULTIPLY_BY_256(x) ((x) << 8)
 
-#define LOCK_ARR_LENGTH   (MAX_EP_NUM * PF_NUM_PER_EP * (3 + VF_NUM_PER_PF))
+#define LOCK_ARR_LENGTH (MAX_EP_NUM * PF_NUM_PER_EP * (3 + VF_NUM_PER_PF))
 
 void bar_init_lock_arr(void);
 
diff --git a/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_priv.h b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_priv.h
index 1533ef54d6ed770e9621b4989598e6df0e0f2919..4521a721bcf77ca986e382b264b84f294914e7f3 100644
--- a/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_priv.h
+++ b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_priv.h
@@ -11,78 +11,79 @@ extern "C" {
 #include <linux/dinghai/dh_cmd.h>
 #include <linux/dinghai/kcompat.h>
 #include <linux/dinghai/log.h>
+
 /* <bar通道宏定义>*/
-#define BAR_KFREE_PTR(ptr)   { \
-    if (ptr != NULL)           \
-    {                          \
-        kfree(ptr);            \
-    }                          \
-    ptr = NULL;                \
-}
+#define BAR_KFREE_PTR(ptr) \
+	{                      \
+		if (ptr != NULL) { \
+			kfree(ptr);    \
+		}                  \
+		ptr = NULL;        \
+	}
 
-#define BAR_LOG_ERR(fmt, arg...)    DH_LOG_ERR(MODULE_CMD, fmt, ##arg);
-#define BAR_LOG_INFO(fmt, arg...)   DH_LOG_INFO(MODULE_CMD, fmt, ##arg);
-#define BAR_LOG_DEBUG(fmt, arg...)  DH_LOG_DEBUG(MODULE_CMD, fmt, ##arg);
-#define BAR_LOG_WARN(fmt, arg...)   DH_LOG_WARNING(MODULE_CMD, fmt, ##arg);
+#define BAR_LOG_ERR(fmt, arg...) DH_LOG_ERR(MODULE_CMD, fmt, ##arg);
+#define BAR_LOG_INFO(fmt, arg...) DH_LOG_INFO(MODULE_CMD, fmt, ##arg);
+#define BAR_LOG_DEBUG(fmt, arg...) DH_LOG_DEBUG(MODULE_CMD, fmt, ##arg);
+#define BAR_LOG_WARN(fmt, arg...) DH_LOG_WARNING(MODULE_CMD, fmt, ##arg);
 
-#define HOST_OR_ZX                   0
+#define HOST_OR_ZX 0
 
-#define MAX_MSG_BUFF_NUM             0xffff
+#define MAX_MSG_BUFF_NUM 0xffff
 
-#define BAR_ALIGN_WORD_MASK          0xffffffc
-#define BAR_MSG_ADDR_CHAN_INTERVAL   (1024*2)
+#define BAR_ALIGN_WORD_MASK 0xffffffc
+#define BAR_MSG_ADDR_CHAN_INTERVAL (1024 * 2)
 
 /* 消息类型*/
-#define BAR_CHAN_MSG_SYNC            0
-#define BAR_CHAN_MSG_ASYNC           1
-#define BAR_CHAN_MSG_NO_EMEC         0
-#define BAR_CHAN_MSG_EMEC            1
-#define BAR_CHAN_MSG_NO_ACK          0
-#define BAR_CHAN_MSG_ACK             1
+#define BAR_CHAN_MSG_SYNC 0
+#define BAR_CHAN_MSG_ASYNC 1
+#define BAR_CHAN_MSG_NO_EMEC 0
+#define BAR_CHAN_MSG_EMEC 1
+#define BAR_CHAN_MSG_NO_ACK 0
+#define BAR_CHAN_MSG_ACK 1
 
 /* payload, valid和内容的偏移*/
-#define BAR_MSG_PLAYLOAD_OFFSET      (sizeof(struct bar_msg_header))
-#define BAR_MSG_LEN_OFFSET           2
-#define BAR_MSG_VALID_OFFSET         0
+#define BAR_MSG_PLAYLOAD_OFFSET (sizeof(struct bar_msg_header))
+#define BAR_MSG_LEN_OFFSET 2
+#define BAR_MSG_VALID_OFFSET 0
 
 /* valid字段的掩码*/
-#define BAR_MSG_VALID_MASK           1
+#define BAR_MSG_VALID_MASK 1
 
 /* reps_buff的偏移*/
-#define REPS_HEADER_VALID_OFFSET     0
-#define REPS_HEADER_LEN_OFFSET       1
-#define REPS_HEADER_PAYLOAD_OFFSET   4
+#define REPS_HEADER_VALID_OFFSET 0
+#define REPS_HEADER_LEN_OFFSET 1
+#define REPS_HEADER_PAYLOAD_OFFSET 4
 
-#define REPS_HEADER_REPLYED          0xff
+#define REPS_HEADER_REPLYED 0xff
 
 /* 通道状态*/
-#define BAR_MSG_CHAN_USABLE          0
-#define BAR_MSG_CHAN_USED            1
+#define BAR_MSG_CHAN_USABLE 0
+#define BAR_MSG_CHAN_USED 1
 
 /* 超时时间 = 100 us *30000次轮询 = 3s*/
-#define BAR_MSG_POLLING_SPAN_US      100
-#define BAR_MSG_TIMEOUT_TH           30000
+#define BAR_MSG_POLLING_SPAN_US 100
+#define BAR_MSG_TIMEOUT_TH 30000
 
 /* vf,pf,mpf总数*/
-#define BAR_DRIVER_TOTAL_NUM        (BAR_MPF_NUM + BAR_PF_NUM + BAR_VF_NUM)
+#define BAR_DRIVER_TOTAL_NUM (BAR_MPF_NUM + BAR_PF_NUM + BAR_VF_NUM)
 
 /* bar的通道偏移*/
-#define BAR_INDEX_TO_RISC            0
-#define BAR_MPF_NUM                  1
+#define BAR_INDEX_TO_RISC 0
+#define BAR_MPF_NUM 1
 
 /* 定时器周期宏*/
-#define BAR_MSGID_FREE_THRESHOLD     (jiffies + msecs_to_jiffies(2000))
+#define BAR_MSGID_FREE_THRESHOLD (jiffies + msecs_to_jiffies(2000))
 
 /* 管理pf信息*/
-#define BAR_MSG_OFFSET               (0x2000)
-#define MPF_VENDOR_ID                (0x16c3)
-#define MPF_DEVICE_ID                (0x8045)
+#define BAR_MSG_OFFSET (0x2000)
+#define MPF_VENDOR_ID (0x16c3)
+#define MPF_DEVICE_ID (0x8045)
 
 enum {
-    TYPE_SEND_NP = 0x0,
-    TYPE_SEND_DRS = 0x01,
-    TYPE_SEND_DTP = 0x10,
-    TYPE_END,
+	TYPE_SEND_NP = 0x0,
+	TYPE_SEND_DRS = 0x01,
+	TYPE_SEND_DTP = 0x10,
+	TYPE_END,
 };
 
 /**************************************************************************
@@ -92,203 +93,240 @@ enum {
  * 3、智能网卡带ddr:     SCENE_NIC_WITH_DDR
  * 4、智能网卡不带ddr:   SCENE_NIC_NO_DDR
  * 5、普卡：            SCENE_STD_NIC
-**************************************************************************/
+ **************************************************************************/
 #define SCENE_TEST
 
 #ifdef SCENE_HOST_IN_DPU
-#define BAR_PF_NUM                   31
-#define BAR_VF_NUM                   1024
-#define BAR_INDEX_PF_TO_VF           1
-#define BAR_INDEX_MPF_TO_MPF         1
-#define BAR_INDEX_MPF_TO_PFVF        0xff
-#define BAR_INDEX_PFVF_TO_MPF        0xff
+#define BAR_PF_NUM 31
+#define BAR_VF_NUM 1024
+#define BAR_INDEX_PF_TO_VF 1
+#define BAR_INDEX_MPF_TO_MPF 1
+#define BAR_INDEX_MPF_TO_PFVF 0xff
+#define BAR_INDEX_PFVF_TO_MPF 0xff
 #endif
 
-#ifdef  SCENE_ZF_IN_DPU
-#define BAR_PF_NUM                   7
-#define BAR_VF_NUM                   128
-#define BAR_INDEX_PF_TO_VF           0xff
-#define BAR_INDEX_MPF_TO_MPF         1
-#define BAR_INDEX_MPF_TO_PFVF        0xff
-#define BAR_INDEX_PFVF_TO_MPF        0xff
+#ifdef SCENE_ZF_IN_DPU
+#define BAR_PF_NUM 7
+#define BAR_VF_NUM 128
+#define BAR_INDEX_PF_TO_VF 0xff
+#define BAR_INDEX_MPF_TO_MPF 1
+#define BAR_INDEX_MPF_TO_PFVF 0xff
+#define BAR_INDEX_PFVF_TO_MPF 0xff
 #endif
 
-#ifdef  SCENE_NIC_WITH_DDR
-#define BAR_PF_NUM                   31
-#define BAR_VF_NUM                   1024
-#define BAR_INDEX_PF_TO_VF           1
-#define BAR_INDEX_MPF_TO_MPF         0xff
-#define BAR_INDEX_MPF_TO_PFVF        0xff
-#define BAR_INDEX_PFVF_TO_MPF        0xff
+#ifdef SCENE_NIC_WITH_DDR
+#define BAR_PF_NUM 31
+#define BAR_VF_NUM 1024
+#define BAR_INDEX_PF_TO_VF 1
+#define BAR_INDEX_MPF_TO_MPF 0xff
+#define BAR_INDEX_MPF_TO_PFVF 0xff
+#define BAR_INDEX_PFVF_TO_MPF 0xff
 #endif
 
-#ifdef  SCENE_NIC_NO_DDR
-#define BAR_PF_NUM                   31
-#define BAR_VF_NUM                   1024
-#define BAR_INDEX_PF_TO_VF           1
-#define BAR_INDEX_MPF_TO_MPF         0xff
-#define BAR_INDEX_MPF_TO_PFVF        1
-#define BAR_INDEX_PFVF_TO_MPF        2
+#ifdef SCENE_NIC_NO_DDR
+#define BAR_PF_NUM 31
+#define BAR_VF_NUM 1024
+#define BAR_INDEX_PF_TO_VF 1
+#define BAR_INDEX_MPF_TO_MPF 0xff
+#define BAR_INDEX_MPF_TO_PFVF 1
+#define BAR_INDEX_PFVF_TO_MPF 2
 #endif
 
-#ifdef  SCENE_STD_NIC
-#define BAR_PF_NUM                   7
-#define BAR_VF_NUM                   256
-#define BAR_INDEX_PF_TO_VF           1
-#define BAR_INDEX_MPF_TO_MPF         0xff
-#define BAR_INDEX_MPF_TO_PFVF        1
-#define BAR_INDEX_PFVF_TO_MPF        2
+#ifdef SCENE_STD_NIC
+#define BAR_PF_NUM 7
+#define BAR_VF_NUM 256
+#define BAR_INDEX_PF_TO_VF 1
+#define BAR_INDEX_MPF_TO_MPF 0xff
+#define BAR_INDEX_MPF_TO_PFVF 1
+#define BAR_INDEX_PFVF_TO_MPF 2
 #endif
 
-#ifdef  SCENE_TEST
-#define BAR_PF_NUM                   7
-#define BAR_VF_NUM                   256
-#define BAR_INDEX_PF_TO_VF           0
-#define BAR_INDEX_MPF_TO_MPF         0xff
-#define BAR_INDEX_MPF_TO_PFVF        0
-#define BAR_INDEX_PFVF_TO_MPF        0
+#ifdef SCENE_TEST
+#define BAR_PF_NUM 7
+#define BAR_VF_NUM 256
+#define BAR_INDEX_PF_TO_VF 0
+#define BAR_INDEX_MPF_TO_MPF 0xff
+#define BAR_INDEX_MPF_TO_PFVF 0
+#define BAR_INDEX_PFVF_TO_MPF 0
 #endif
 
 /* 左边通道还是右边通道*/
-#define BAR_SUBCHAN_INDEX_SEND      0
-#define BAR_SUBCHAN_INDEX_RECV      1
+#define BAR_SUBCHAN_INDEX_SEND 0
+#define BAR_SUBCHAN_INDEX_RECV 1
 
 /* 消息源索引*/
-#define BAR_MSG_SRC_NUM             3
-#define BAR_MSG_SRC_MPF             0
-#define BAR_MSG_SRC_PF              1
-#define BAR_MSG_SRC_VF              2
-#define BAR_MSG_SRC_ERR             0xff
+#define BAR_MSG_SRC_NUM 3
+#define BAR_MSG_SRC_MPF 0
+#define BAR_MSG_SRC_PF 1
+#define BAR_MSG_SRC_VF 2
+#define BAR_MSG_SRC_ERR 0xff
 
 /* 消息目的索引*/
-#define BAR_MSG_DST_NUM             3
-#define BAR_MSG_DST_RISC            0
-#define BAR_MSG_DST_MPF             2
-#define BAR_MSG_DST_PFVF            1
-#define BAR_MSG_DST_ERR             0xff
+#define BAR_MSG_DST_NUM 3
+#define BAR_MSG_DST_RISC 0
+#define BAR_MSG_DST_MPF 2
+#define BAR_MSG_DST_PFVF 1
+#define BAR_MSG_DST_ERR 0xff
 
 /* msg_id项标志位状态*/
-#define REPS_INFO_FLAG_USABLE       0
-#define REPS_INFO_FLAG_USED         1
-
-#define BAR_MSG_PAYLOAD_MAX_LEN     (BAR_MSG_ADDR_CHAN_INTERVAL - sizeof(struct bar_msg_header))
+#define REPS_INFO_FLAG_USABLE 0
+#define REPS_INFO_FLAG_USED 1
 
-#define BAR_MSG_POL_MASK                (0x10)
-#define BAR_MSG_POL_OFFSET              (4)
+#define BAR_MSG_PAYLOAD_MAX_LEN \
+	(BAR_MSG_ADDR_CHAN_INTERVAL - sizeof(struct bar_msg_header))
 
-enum {
-    CHECK_STATE_OK = 0,
-    CHECK_STATE_EVENT_EXCEED = 1,
-    CHECK_STATE_EVENT_NOT_EXIST = 2,
-    CHECK_STATE_EVENT_ERR_RET = 4,
-    CHECK_STATE_EVENT_ERR_REPS_LEN = 5,
-};
+#define BAR_MSG_POL_MASK (0x10)
+#define BAR_MSG_POL_OFFSET (4)
 
-struct zxdh_pcie_bar_msg_internal
-{
-    uint32_t id;        /**< the msg id that passing through */
-    uint64_t virt_addr; /**< pcie bar mapping virtual addr */
+struct zxdh_pcie_bar_msg_internal {
+	uint32_t id; /**< the msg id that passing through */
+	uint64_t virt_addr; /**< pcie bar mapping virtual addr */
 };
 
 /* bar通道消息头 */
-struct bar_msg_header
-{
-    uint8_t valid: 1;               /* 消息通道状态 */
-    uint8_t sync:  1;               /* 同步消息or异步消息*/
-    uint8_t emec:  1;               /* 消息是否紧急 */
-    uint8_t ack:  1;                /* 是否是回复消息*/
-    uint8_t poll:  1;
-    uint8_t check;
-    uint16_t event_id;              /* 请求的消息处理函数标识 */
-    uint16_t len;                   /* 消息长度 */
-    uint16_t msg_id;                /* 消息id*/
-    uint16_t src_pcieid;
-    uint16_t dst_pcieid;                   /* 用于pf给vf发消息*/
+struct bar_msg_header {
+	uint8_t valid : 1; /* 消息通道状态 */
+	uint8_t sync : 1; /* 同步消息or异步消息*/
+	uint8_t emec : 1; /* 消息是否紧急 */
+	uint8_t ack : 1; /* 是否是回复消息*/
+	uint8_t poll : 1;
+	uint8_t rsv;
+	uint16_t event_id; /* 请求的消息处理函数标识 */
+	uint16_t len; /* 消息长度 */
+	uint16_t msg_id; /* 消息id*/
+	uint16_t src_pcieid;
+	uint16_t dst_pcieid; /* 用于pf给vf发消息*/
 };
 
 /* 根据消息的msgid查询回复缓存的地址和长度*/
-struct msgid_reps_info
-{
-    void *reps_buffer;                   /* reps的地址*/
-    uint16_t id;                         /* msg_id*/
-    uint16_t buffer_len;                 /* buffer的最大长度*/
-    uint16_t flag;                       /* 该条目是否被分配，已经非配和未被分配*/
-    struct timer_list id_timer;          /* 该id对应的定时器*/
+struct msgid_reps_info {
+	void *reps_buffer; /* reps的地址*/
+	uint16_t id; /* msg_id*/
+	uint16_t buffer_len; /* buffer的最大长度*/
+	uint16_t flag; /* 该条目是否被分配，已经非配和未被分配*/
+	struct timer_list id_timer; /* 该id对应的定时器*/
 };
 
-struct msix_msg
-{
-    uint16_t pcie_id;
-    uint16_t vector_risc;
-    uint16_t vector_pfvf;
-    uint16_t vector_mpf;
+struct msix_msg {
+	uint16_t pcie_id;
+	uint16_t vector_risc;
+	uint16_t vector_pfvf;
+	uint16_t vector_mpf;
 };
-struct offset_get_msg
-{
-    uint16_t pcie_id;
-    uint16_t type;
+struct offset_get_msg {
+	uint16_t pcie_id;
+	uint16_t type;
 };
 
-struct bar_offset_reps
-{
-    uint16_t check;
-    uint16_t rsv;
-    uint32_t offset;
-    uint32_t length;
-}__attribute__((packed));
-
-struct bar_recv_msg
-{
-    uint8_t replied;
-    uint16_t reps_len;
-    uint8_t rsv1;
-    union
-    {
-        struct bar_offset_reps offset_reps;
-        uint8_t data[BAR_MSG_PAYLOAD_MAX_LEN - 4];
-    };
-}__attribute__((packed));
-
-struct msgid_ring
-{
-    uint16_t msg_id;
-    spinlock_t lock;
-    struct msgid_reps_info reps_info_tbl[MAX_MSG_BUFF_NUM];
+struct bar_offset_reps {
+	uint16_t check;
+	uint16_t rsv;
+	uint32_t offset;
+	uint32_t length;
+} __attribute__((packed));
+
+struct bar_recv_msg {
+	uint8_t replied;
+	uint16_t reps_len;
+	uint8_t rsv1;
+	union {
+		struct bar_offset_reps offset_reps;
+		uint8_t data[ZXDH_NET_MAX_ACK_LEN - 4];
+	};
+} __attribute__((packed));
+
+struct msgid_ring {
+	uint16_t msg_id;
+	spinlock_t lock;
+	struct msgid_reps_info reps_info_tbl[MAX_MSG_BUFF_NUM];
 };
 
 /* 异步消息相关实体*/
-struct async_msg_entity
-{
-    struct task_struct *async_proc;        /* 异步队列消息线程*/
-    struct mutex async_qlock;              /* 易怒队列入队锁*/
-    struct bar_async_node *noemq_head;     /* 非紧急队列头*/
-    struct bar_async_node *noemq_tail;     /* 非紧急队列尾部*/
-    struct bar_async_node *emq_head;       /* 紧急队列头*/
-    struct bar_async_node *emq_tail;       /* 紧急队列尾部*/
+struct async_msg_entity {
+	struct task_struct *async_proc; /* 异步队列消息线程*/
+	struct mutex async_qlock; /* 易怒队列入队锁*/
+	struct bar_async_node *noemq_head; /* 非紧急队列头*/
+	struct bar_async_node *noemq_tail; /* 非紧急队列尾部*/
+	struct bar_async_node *emq_head; /* 紧急队列头*/
+	struct bar_async_node *emq_tail; /* 紧急队列尾部*/
 };
 
 /* 异步消息队列节点*/
-struct bar_async_node
-{
-    uint32_t msg_id;
-    void *payload_addr;     /**< 消息净荷起始地址，有用户创建并填充 */
-    uint64_t payload_len;   /**< 消息净荷长度. */
-    uint64_t subchan_addr;  /**< 消息发送到哪个2K, 由virt_addr, src, dst共同决定，计算交给common来做>**/
-    uint32_t event_id;     /**< 消息发送模块，描述消息哪个模块发送 */
-    uint16_t src_pcieid;
-    uint16_t dst_pcieid;           /**< 消息目的的bdf号，适用于PF与VF公用4K的时候用>**/
-    uint16_t emec;          /**< 消息紧急类型，异步消息可以分为紧急消息和非紧急消息>**/
-    uint16_t ack;
-    uint8_t src;
-    uint8_t dst;
-    struct bar_async_node *next;
+struct bar_async_node {
+	uint32_t msg_id;
+	void *payload_addr; /**< 消息净荷起始地址，有用户创建并填充 */
+	uint64_t payload_len; /**< 消息净荷长度. */
+	uint64_t subchan_addr; /* < 消息发送到哪个2K, 由virt_addr, src,
+							dst共同决定，计算交给common来做> */
+	uint32_t event_id; /**< 消息发送模块，描述消息哪个模块发送 */
+	uint16_t src_pcieid;
+	uint16_t dst_pcieid; /**< 消息目的的bdf号，适用于PF与VF公用4K的时候用>**/
+	uint16_t emec; /**< 消息紧急类型，异步消息可以分为紧急消息和非紧急消息>**/
+	uint16_t ack;
+	uint8_t src;
+	uint8_t dst;
+	struct bar_async_node *next;
 };
 
-uint8_t bar_msg_col_index_trans(uint8_t dst);
-uint8_t bar_msg_row_index_trans(uint8_t src);
+/* <Bar通道内部函数申明> */
+int __bar_chan_send_para_check(struct zxdh_pci_bar_msg *in,
+							   struct zxdh_msg_recviver_mem *result);
+void __bar_chan_subchan_addr_get(struct zxdh_pci_bar_msg *in,
+								 uint64_t *subchan_addr);
+void __bar_chan_sync_fill_header(uint32_t msg_id, struct zxdh_pci_bar_msg *in,
+								 struct bar_msg_header *msg_header);
+uint16_t __bar_chan_msg_send(uint64_t subchan_addr, void *payload_addr,
+							 uint16_t payload_len,
+							 struct bar_msg_header *msg_header);
+
+void __bar_msg_ack_async_msg_proc(struct bar_msg_header *msg_header,
+								  uint8_t *reciver_buff);
+void __bar_msg_noack_async_msg_proc(uint64_t reps_addr,
+									struct bar_msg_header *msg_header,
+									uint8_t *reciver_buff, uint8_t src,
+									uint8_t dst, void *dev);
+void __bar_msg_sync_msg_proc(uint64_t reply_addr,
+							 struct bar_msg_header *msg_header,
+							 uint8_t *reciver_buff, void *dev);
+uint16_t __bar_chan_msg_header_set(uint64_t subchan_addr,
+								   struct bar_msg_header *msg_header);
+uint16_t __bar_chan_msg_header_get(uint64_t subchan_addr,
+								   struct bar_msg_header *msg_header);
+uint16_t __bar_chan_msg_header_check(struct bar_msg_header *msg_header);
+uint16_t
+__bar_chan_callback_register_check(uint8_t event_id,
+								   zxdh_bar_chan_msg_recv_callback callback);
+uint16_t __bar_chan_msg_payload_set(uint64_t subchan_addr, uint8_t *msg,
+									uint16_t len);
+uint16_t __bar_chan_msg_payload_get(uint64_t subchan_addr, uint8_t *msg,
+									uint16_t len);
+uint16_t __bar_chan_msg_valid_set(uint64_t subchan_addr, uint8_t valid_label);
+uint16_t __bar_chan_msg_poltag_set(uint64_t subchan_addr, uint8_t label);
+uint16_t __bar_msg_valid_stat_get(uint64_t subchan_addr);
+uint16_t __bar_chan_sync_msg_reps_get(uint64_t subchan_addr,
+									  uint64_t recv_buffer, uint16_t buffer_len,
+									  uint16_t msg_id);
+int __bar_chan_msgid_allocate(uint16_t *msgid);
+void __bar_chan_msgid_free(uint16_t msg_id);
+struct bar_async_node *
+__bar_chan_async_node_create(uint16_t msg_id, struct zxdh_pci_bar_msg *in);
+uint16_t __bar_chan_async_node_add(struct bar_async_node *node);
+uint16_t __bar_chan_async_node_del(struct bar_async_node *node);
+void __bar_msg_async_list_admin(void);
+uint16_t __bar_msg_async_list_parse(struct bar_async_node *node);
+uint16_t bar_msg_src_parse(struct zxdh_pci_bar_msg *in);
+
+uint16_t __bar_chan_save_recv_info(struct zxdh_msg_recviver_mem *result,
+								   uint16_t *msg_id);
+int __bar_chan_reg_write(uint64_t subchan_addr, uint32_t offset, uint32_t data);
+int __bar_chan_reg_read(uint64_t subchan_addr, uint32_t offset,
+						uint32_t *pdata);
+uint8_t __bar_msg_col_index_trans(uint8_t dst);
+uint8_t __bar_msg_row_index_trans(uint8_t src);
+void bar_chan_timer_callback(struct timer_list *timer);
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* _ZXDH_MSG_CHAN_PRIV_H_  */
+#endif /* _ZXDH_MSG_CHAN_PRIV_H_  */
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_test.c b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_test.c
index 1de7b5246042cb9732aef2d11ec79e3254709313..3f22cbb38c4a214abed490aff4c93241597e4e37 100644
--- a/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_test.c
+++ b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_test.c
@@ -10,139 +10,129 @@
 #ifdef BAR_MSG_TEST
 
 /*计算方法： risc时间戳 - host时间戳*/
-#define   HOST_RISC_DIFF        (307762)
+#define HOST_RISC_DIFF (307762)
 
 uint64_t print_time(char *str)
 {
-    ktime_t kt = ktime_get();
-    s64 us_since_boot = ktime_to_us(kt);
-    LOG_INFO(KERN_INFO "%s timestamp: %llu us\n", str, us_since_boot);
-    return us_since_boot;
+	ktime_t kt = ktime_get();
+	s64 us_since_boot = ktime_to_us(kt);
+	LOG_INFO(KERN_INFO "%s timestamp: %llu us\n", str, us_since_boot);
+	return us_since_boot;
 }
-struct msg_time_statis_reps
-{
-    uint16_t sum_check;
-
-    uint64_t risc_recv_msg_t;
-    uint64_t risc_push_msg_t;
-    uint64_t risc_pop_msg_t;
-    uint64_t risc_msg_proc_t;
-    uint64_t risc_notice_peer_t;
+struct msg_time_statis_reps {
+	uint16_t sum_check;
+
+	uint64_t risc_recv_msg_t;
+	uint64_t risc_push_msg_t;
+	uint64_t risc_pop_msg_t;
+	uint64_t risc_msg_proc_t;
+	uint64_t risc_notice_peer_t;
 } __attribute__((packed));
 
-struct msg_time_host_risc
-{
-    uint64_t host_send_msg_t;
-    uint64_t host_recv_msg_t;
-    struct msg_time_statis_reps risc_time;
-}__attribute__((packed));
+struct msg_time_host_risc {
+	uint64_t host_send_msg_t;
+	uint64_t host_recv_msg_t;
+	struct msg_time_statis_reps risc_time;
+} __attribute__((packed));
 
-struct msg_time_host_risc global_time_stat = {0};
+struct msg_time_host_risc global_time_stat = { 0 };
 
 void print_risc_time_stamp(struct msg_time_host_risc *stat)
 {
-#if 0
-    LOF_INFO("host_send_msg_t:    %llu us.\n", stat->host_send_msg_t);
-    LOF_INFO("risc_recv_msg_t:    %llu us.\n", stat->risc_time.risc_recv_msg_t);
-    LOF_INFO("risc_push_msg_t:    %llu us.\n", stat->risc_time.risc_push_msg_t);
-    LOF_INFO("risc_pop_msg_t:     %llu us.\n", stat->risc_time.risc_pop_msg_t);
-    LOF_INFO("risc_msg_proc_t:    %llu us.\n", stat->risc_time.risc_msg_proc_t);
-    LOF_INFO("risc_notice_peer_t: %llu us.\n", stat->risc_time.risc_notice_peer_t);
-    LOF_INFO("host_recv_msg_t:    %llu us.\n", stat->host_recv_msg_t);
-#endif
-    LOG_INFO("risc recv->msg push:         %llu us.\n", stat->risc_time.risc_push_msg_t - stat->risc_time.risc_recv_msg_t);
-    LOG_INFO("risc push->risc pop:         %llu us.\n", stat->risc_time.risc_pop_msg_t - stat->risc_time.risc_push_msg_t);
-    LOG_INFO("risc pop->before proc   :    %llu us.\n", stat->risc_time.risc_msg_proc_t- stat->risc_time.risc_pop_msg_t);
-    LOG_INFO("after proc->risc set valid:  %llu us.\n", stat->risc_time.risc_notice_peer_t - stat->risc_time.risc_msg_proc_t);
+	LOG_INFO("risc recv->msg push:         %llu us.\n",
+			 stat->risc_time.risc_push_msg_t - stat->risc_time.risc_recv_msg_t);
+	LOG_INFO("risc push->risc pop:         %llu us.\n",
+			 stat->risc_time.risc_pop_msg_t - stat->risc_time.risc_push_msg_t);
+	LOG_INFO("risc pop->before proc   :    %llu us.\n",
+			 stat->risc_time.risc_msg_proc_t - stat->risc_time.risc_pop_msg_t);
+	LOG_INFO("after proc->risc set valid:  %llu us.\n",
+			 stat->risc_time.risc_notice_peer_t -
+					 stat->risc_time.risc_msg_proc_t);
 }
 
 uint16_t sum_func(void *data, uint16_t len)
 {
-    uint64_t result = 0;
-    int idx = 0;
-    uint16_t ret = 0;
-
-    if (data == NULL)
-    {
-        return 0;
-    }
-
-    for (idx = 0; idx < len; idx++)
-    {
-        result += *((uint8_t *)data + idx);
-    }
-
-    ret = (uint16_t)result;
-    return ret;
+	uint64_t result = 0;
+	int idx = 0;
+	uint16_t ret = 0;
+
+	if (data == NULL) {
+		return 0;
+	}
+
+	for (idx = 0; idx < len; idx++) {
+		result += *((uint8_t *)data + idx);
+	}
+
+	ret = (uint16_t)result;
+	return ret;
 }
 
 uint16_t test_sync_send(void)
 {
-    struct zxdh_pci_bar_msg in = {0};
-    struct zxdh_msg_recviver_mem result = {0};
-    uint16_t payload_len = 0;
-    uint64_t bar_base_addr = 0;
-    void *payload_addr = NULL;
-    uint8_t recv_buffer[200] = {0};
-    uint16_t reps = 0;
-    uint16_t ret = 0;
-
-    payload_len = 100;
-    payload_addr = kmalloc(payload_len, GFP_KERNEL);
-    if (!payload_addr)
-    {
-        LOG_ERR("malloca failed");
-        return 0xaa;
-    }
-    get_random_bytes(payload_addr, payload_len);
-    LOG_INFO("sync send msg len: %x", payload_len);
-
-    in.src_pcieid = 0x900;
-    in.virt_addr = 0;
-    in.payload_addr = payload_addr;
-    in.payload_len = payload_len;
-    in.src = MSG_CHAN_END_MPF;
-    in.dst = MSG_CHAN_END_RISC;
-    in.event_id = 50;
-
-    /* 构造result接收参数*/
-    result.recv_buffer = recv_buffer;
-    result.buffer_len = sizeof(recv_buffer);
-
-    /* 调用发送接口*/
-    LOG_INFO("start to sync send test.");
-    global_time_stat.host_send_msg_t = print_time("before send.") + HOST_RISC_DIFF;
-    ret = zxdh_bar_chan_sync_msg_send(&in, &result);
-    global_time_stat.host_recv_msg_t = print_time("after send.") + HOST_RISC_DIFF;
-
-    if (ret != BAR_MSG_OK)
-    {
-        LOG_ERR("sync send failed");
-        ret = 0xAA;
-        goto out;
-    }
-
-    struct msg_time_statis_reps *reps_ptr = (struct msg_time_statis_reps*)((uint8_t *)result.recv_buffer + 4);
-    if (reps_ptr->sum_check == sum_func(payload_addr, payload_len))
-    {
-        memcpy(&global_time_stat.risc_time, (void*)reps_ptr, sizeof(struct msg_time_statis_reps));
-        print_risc_time_stamp(&global_time_stat);
-        ret = 0;
-        LOG_ERR("reps validate success: %d", reps);
-        goto out;
-    }
-    else
-    {
-        LOG_ERR("reps valide failed: %d", reps);
-        ret = 0xAA;
-    }
-
-out:
-    if (!payload_addr)
-    {
-        kfree(payload_addr);
-        payload_addr = NULL;
-    }
-    return ret;
+	struct zxdh_pci_bar_msg in = { 0 };
+	struct zxdh_msg_recviver_mem result = { 0 };
+	uint16_t payload_len = 0;
+	uint64_t bar_base_addr = 0;
+	void *payload_addr = NULL;
+	uint8_t recv_buffer[200] = { 0 };
+	uint16_t reps = 0;
+	uint16_t ret = 0;
+
+	payload_len = 100;
+	payload_addr = kmalloc(payload_len, GFP_KERNEL);
+	if (!payload_addr) {
+		LOG_ERR("malloca failed");
+		return 0xaa;
+	}
+	get_random_bytes(payload_addr, payload_len);
+	LOG_INFO("sync send msg len: %x", payload_len);
+
+	in.src_pcieid = 0x900;
+	in.virt_addr = 0;
+	in.payload_addr = payload_addr;
+	in.payload_len = payload_len;
+	in.src = MSG_CHAN_END_MPF;
+	in.dst = MSG_CHAN_END_RISC;
+	in.event_id = 50;
+
+	/* 构造result接收参数*/
+	result.recv_buffer = recv_buffer;
+	result.buffer_len = sizeof(recv_buffer);
+
+	/* 调用发送接口*/
+	LOG_INFO("start to sync send test.");
+	global_time_stat.host_send_msg_t =
+			print_time("before send.") + HOST_RISC_DIFF;
+	ret = zxdh_bar_chan_sync_msg_send(&in, &result);
+	global_time_stat.host_recv_msg_t =
+			print_time("after send.") + HOST_RISC_DIFF;
+
+	if (ret != BAR_MSG_OK) {
+		LOG_ERR("sync send failed");
+		ret = 0xAA;
+		goto exit;
+	}
+
+	struct msg_time_statis_reps *reps_ptr =
+			(struct msg_time_statis_reps *)((uint8_t *)result.recv_buffer + 4);
+	if (reps_ptr->sum_check == sum_func(payload_addr, payload_len)) {
+		memcpy(&global_time_stat.risc_time, (void *)reps_ptr,
+			   sizeof(struct msg_time_statis_reps));
+		print_risc_time_stamp(&global_time_stat);
+		ret = 0;
+		LOG_ERR("reps validate success: %d", reps);
+		goto exit;
+	} else {
+		LOG_ERR("reps valide failed: %d", reps);
+		ret = 0xAA;
+	}
+
+exit:
+	if (!payload_addr) {
+		kfree(payload_addr);
+		payload_addr = NULL;
+	}
+	return ret;
 }
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_ver.h b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_ver.h
index b3575d2d3ef763680a274b66d10239b6e3cd2ebb..485300c445a8a95f22289382c97f418fa86a394e 100644
--- a/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_ver.h
+++ b/src/net/drivers/net/ethernet/dinghai/cmd/msg_chan_ver.h
@@ -1,16 +1,11 @@
 #ifndef _ZXDH_MSG_CHAN_VERSION_H_
 #define _ZXDH_MSG_CHAN_VERSION_H_
 
-#ifdef DRIVER_VERSION_VAL
-    #define DRV_VERSION DRIVER_VERSION_VAL
-#else
-    #define DRV_VERSION "1.0-1"
-#endif
-
-#define DRV_RELDATE	"December 1, 2022"
-#define DRV_NAME	"msg_chan"
-#define DRV_DESCRIPTION	"DPU MSG Channel Driver"
+#define DRV_VERSION "1.0.1"
+#define DRV_RELDATE "December 1, 2022"
+#define DRV_NAME "msg_chan"
+#define DRV_DESCRIPTION "DPU MSG Channel Driver"
 
 #define hbond_version DRV_DESCRIPTION ": v" DRV_VERSION " (" DRV_RELDATE ")\n"
 
-#endif  /* _ZXDH_MSG_CHAN_VERSION_H_ */
\ No newline at end of file
+#endif /* _ZXDH_MSG_CHAN_VERSION_H_ */
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/cmd/msg_main.c b/src/net/drivers/net/ethernet/dinghai/cmd/msg_main.c
index 599e6e5c1179c5fdc7246edd0498b1d4eb2d4fcd..c84cb27771e3474ae5bc8aed0e5bfb75e21fa5c7 100644
--- a/src/net/drivers/net/ethernet/dinghai/cmd/msg_main.c
+++ b/src/net/drivers/net/ethernet/dinghai/cmd/msg_main.c
@@ -1,31 +1,30 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/kthread.h>
-
 #include "msg_chan_ver.h"
 #include "msg_chan_priv.h"
 
 static int __init msg_chan_init(void)
 {
-    BAR_LOG_INFO("%s init. version %s\n", DRV_DESCRIPTION, DRV_VERSION);
-    zxdh_bar_msg_chan_init();
+	zxdh_bar_msg_chan_init();
 
 #ifdef TEST
-    BAR_TestApp();
+	BAR_TestApp();
 #endif
+	BAR_LOG_INFO("%s init. version %s\n", DRV_DESCRIPTION, DRV_VERSION);
 
-    return 0;
+	return 0;
 }
 
 static void __exit msg_chan_exit(void)
 {
-    zxdh_bar_msg_chan_remove();
-    BAR_LOG_INFO("%s exit.\n", DRV_DESCRIPTION);
+	BAR_LOG_INFO("%s exit.\n", DRV_DESCRIPTION);
+	zxdh_bar_msg_chan_remove();
 }
 
 module_init(msg_chan_init);
 module_exit(msg_chan_exit);
-MODULE_LICENSE("Dual BSD/GPL");
+MODULE_LICENSE("GPL");
 MODULE_VERSION(DRV_VERSION);
 MODULE_DESCRIPTION(DRV_DESCRIPTION ", v" DRV_VERSION);
-MODULE_AUTHOR("ZTE Corporation");
+MODULE_AUTHOR("Zte Corporation");
diff --git a/src/net/drivers/net/ethernet/dinghai/devlink.c b/src/net/drivers/net/ethernet/dinghai/devlink.c
old mode 100755
new mode 100644
index f244c9027c30e6bd10db6124711edaffeab231f6..03453bfa17e2e4058b5170757a89a6bcefad31ba
--- a/src/net/drivers/net/ethernet/dinghai/devlink.c
+++ b/src/net/drivers/net/ethernet/dinghai/devlink.c
@@ -1,50 +1,52 @@
-#include <linux/dinghai/devlink.h>
-#include <linux/dinghai/driver.h>
-
-#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
-    int32_t zxdh_devlink_register(struct devlink *devlink)
-#else
-    int32_t zxdh_devlink_register(struct devlink *devlink, struct device *dev)
-#endif
-{
-    struct dh_core_dev *dh_dev = devlink_priv(devlink);
-    int32_t err = 0;
-
-#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
-        devlink_register(devlink);
-#else
-        devlink_register(devlink, dev);
-#endif
-
-    err = dh_dev->devlink_ops->params_register(devlink);
-    if (err != 0)
-    {
-        LOG_ERR("params_register failed: %d\n", err);
-        return err;
-    }
-
-    return err;
-}
-
-struct devlink *zxdh_devlink_alloc(struct device *dev, struct devlink_ops *dh_devlink_ops, size_t priv_size)
-{
-#ifdef HAVE_DEVLINK_ALLOC_GET_1_PARAMS
-    return devlink_alloc(dh_devlink_ops, sizeof(struct dh_core_dev) + priv_size);
-#else
-    return devlink_alloc(dh_devlink_ops, sizeof(struct dh_core_dev) + priv_size, dev);
-#endif
-}
-
-void zxdh_devlink_free(struct devlink *devlink)
-{
-    devlink_free(devlink);
-}
-
-void zxdh_devlink_unregister(struct devlink *devlink)
-{
-    struct dh_core_dev *dev = devlink_priv(devlink);
-
-    dev->devlink_ops->params_unregister(devlink);
-
-    devlink_unregister(devlink);
-}
+#include <linux/dinghai/devlink.h>
+#include <linux/dinghai/driver.h>
+
+#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
+int32_t zxdh_devlink_register(struct devlink *devlink)
+#else
+int32_t zxdh_devlink_register(struct devlink *devlink, struct device *dev)
+#endif
+{
+	struct dh_core_dev *dh_dev = devlink_priv(devlink);
+	int32_t err = 0;
+
+#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
+	devlink_register(devlink);
+#else
+	devlink_register(devlink, dev);
+#endif
+
+	err = dh_dev->devlink_ops->params_register(devlink);
+	if (err != 0) {
+		return err;
+	}
+
+	return err;
+}
+
+struct devlink *zxdh_devlink_alloc(struct device *dev,
+								   struct devlink_ops *dh_devlink_ops,
+								   size_t priv_size)
+{
+#ifdef HAVE_DEVLINK_ALLOC_GET_1_PARAMS
+	return devlink_alloc(dh_devlink_ops,
+						 sizeof(struct dh_core_dev) + priv_size);
+#else
+	return devlink_alloc(dh_devlink_ops, sizeof(struct dh_core_dev) + priv_size,
+						 dev);
+#endif
+}
+
+void zxdh_devlink_free(struct devlink *devlink)
+{
+	devlink_free(devlink);
+}
+
+void zxdh_devlink_unregister(struct devlink *devlink)
+{
+	struct dh_core_dev *dev = devlink_priv(devlink);
+
+	dev->devlink_ops->params_unregister(devlink);
+
+	devlink_unregister(devlink);
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/dh_cmd.c b/src/net/drivers/net/ethernet/dinghai/dh_cmd.c
index 704cf4afc6576fea3ca58cdf74b5cf1e16a976ca..8163e9858c2acd993af3b023cb52f3ba0bf7dbd6 100644
--- a/src/net/drivers/net/ethernet/dinghai/dh_cmd.c
+++ b/src/net/drivers/net/ethernet/dinghai/dh_cmd.c
@@ -16,24 +16,24 @@ MPF:       0         0       0
 PF:        0         0       1
 VF:        0         1       1
 ******************************************/
-uint8_t subchan_id_tbl[BAR_MSG_SRC_NUM][BAR_MSG_DST_NUM] =
-{
-    {BAR_SUBCHAN_INDEX_SEND, BAR_SUBCHAN_INDEX_SEND, BAR_SUBCHAN_INDEX_SEND},
-    {BAR_SUBCHAN_INDEX_SEND, BAR_SUBCHAN_INDEX_SEND, BAR_SUBCHAN_INDEX_RECV},
-    {BAR_SUBCHAN_INDEX_SEND, BAR_SUBCHAN_INDEX_RECV, BAR_SUBCHAN_INDEX_RECV}
+uint8_t subchan_id_tbl[BAR_MSG_SRC_NUM][BAR_MSG_DST_NUM] = {
+	{ BAR_SUBCHAN_INDEX_SEND, BAR_SUBCHAN_INDEX_SEND, BAR_SUBCHAN_INDEX_SEND },
+	{ BAR_SUBCHAN_INDEX_SEND, BAR_SUBCHAN_INDEX_SEND, BAR_SUBCHAN_INDEX_RECV },
+	{ BAR_SUBCHAN_INDEX_SEND, BAR_SUBCHAN_INDEX_RECV, BAR_SUBCHAN_INDEX_RECV }
 };
 
-uint8_t chan_id_tbl[BAR_MSG_SRC_NUM][BAR_MSG_DST_NUM] =
-{
-    {BAR_INDEX_TO_RISC, BAR_INDEX_MPF_TO_PFVF, BAR_INDEX_MPF_TO_MPF},
-    {BAR_INDEX_TO_RISC, BAR_INDEX_PF_TO_VF,    BAR_INDEX_PFVF_TO_MPF},
-    {BAR_INDEX_TO_RISC, BAR_INDEX_PF_TO_VF,    BAR_INDEX_PFVF_TO_MPF}
+uint8_t chan_id_tbl[BAR_MSG_SRC_NUM][BAR_MSG_DST_NUM] = {
+	{ BAR_INDEX_TO_RISC, BAR_INDEX_MPF_TO_PFVF, BAR_INDEX_MPF_TO_MPF },
+	{ BAR_INDEX_TO_RISC, BAR_INDEX_PF_TO_VF, BAR_INDEX_PFVF_TO_MPF },
+	{ BAR_INDEX_TO_RISC, BAR_INDEX_PF_TO_VF, BAR_INDEX_PFVF_TO_MPF }
 };
 
 void *internal_addr;
 
 bool is_mpf_scaned = FALSE;
 
+struct async_msg_entity async_en;
+
 static struct msgid_ring g_msgid_ring;
 
 /* 消息处理函数表*/
@@ -41,730 +41,967 @@ zxdh_bar_chan_msg_recv_callback msg_recv_func_tbl[MSG_MODULE_NUM];
 
 void bar_chan_check_chan_stats(int ret, uint64_t addr)
 {
-    struct bar_msg_header *hdr = (struct bar_msg_header*)addr;
-
-    if (ret == 0)
-    {
-        return;
-    }
-    /* check bar msg_header*/
-    BAR_LOG_ERR("bar msg err, ret: %d, valid: %u, msg_id: %u, event_id: %u, "
-                 "ack: %u, src_pcieid: 0x%x, dst_pcieid: 0x%x, chan_addr: 0x%llx.\n",
-                 ret, hdr->valid, hdr->msg_id, hdr->event_id, hdr->ack, hdr->src_pcieid, hdr->dst_pcieid, addr);
+	struct bar_msg_header *hdr = (struct bar_msg_header *)addr;
+
+	if (ret == 0) {
+		return;
+	}
+	/* check bar msg_header*/
+	LOG_INFO(
+			"bar msg err, ret: %d, valid: %u, msg_id: %u, event_id: %u, "
+			"ack: %u, src_pcieid: 0x%x, dst_pcieid: 0x%x, chan_addr: 0x%llx.\n",
+			ret, hdr->valid, hdr->msg_id, hdr->event_id, hdr->ack,
+			hdr->src_pcieid, hdr->dst_pcieid, addr);
 }
 
-uint16_t bar_msg_src_parse(struct zxdh_pci_bar_msg *in)
-{
-    if (in == NULL)
-    {
-        return BAR_MSG_ERR_NULL;
-    }
-
-    if (in->src == MSG_CHAN_END_MPF)
-    {
-        if (!is_mpf_scaned)
-        {
-            return  BAR_MSG_ERR_MPF_NOT_SCANED;
-        }
-        in->virt_addr = (uint64_t)internal_addr + BAR_MSG_OFFSET;
-        in->src_pcieid = PF0_PCIEID;
-    }
-    return BAR_MSG_OK;
-}
-
-void bar_chan_sync_fill_header(uint32_t msg_id, struct zxdh_pci_bar_msg *in, struct bar_msg_header *msg_header)
+/**
+ * zxdh_bar_chan_sync_msg_send - 通过PCIE BAR空间发送同步消息
+ * @in: 消息发送信息
+ * @result: 消息结果反馈
+ * @return: 0 成功，其他失败
+ */
+int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in,
+								struct zxdh_msg_recviver_mem *result)
 {
-    memset(msg_header, 0, sizeof(*msg_header));
-    msg_header->sync        = BAR_CHAN_MSG_SYNC;
-    msg_header->event_id   = in->event_id;
-    msg_header->len         = in->payload_len;
-    msg_header->msg_id      = msg_id;
-    msg_header->dst_pcieid  = in->dst_pcieid;
-    msg_header->src_pcieid  = in->src_pcieid;
+	int ret = 0;
+	uint16_t valid = 0;
+	uint16_t time_out_cnt = 0;
+	uint16_t msg_id = 0;
+	uint64_t subchan_addr = 0;
+	struct bar_msg_header msg_header = { 0 };
+
+	ret = bar_msg_src_parse(in);
+	if (ret != BAR_MSG_OK) {
+		goto exit;
+	}
+
+	ret = __bar_chan_send_para_check(in, result);
+	if (ret != BAR_MSG_OK) {
+		BAR_LOG_ERR("para check failed, %d.", ret);
+		goto exit;
+	}
+
+	/* 申请msg_id,并将缓存信息存放到表中*/
+	ret = __bar_chan_save_recv_info(result, &msg_id);
+	if (ret != BAR_MSG_OK) {
+		BAR_LOG_ERR("msg_id allocated failed.");
+		goto exit;
+	}
+	/* 计算2K通道的地址*/
+	__bar_chan_subchan_addr_get(in, &subchan_addr);
+	/* 填充消息头*/
+	__bar_chan_sync_fill_header(msg_id, in, &msg_header);
+	/* 给通道上锁，根据src和dst判断是分配硬件锁还是软件锁*/
+	bar_chan_lock(in->src, in->dst, in->src_pcieid);
+
+	/* 消息头、消息体发送到bar空间， valid置位*/
+	__bar_chan_msg_send(subchan_addr, in->payload_addr, in->payload_len,
+						&msg_header);
+	/* 轮询等待消息回复*/
+	do {
+		usleep_range(BAR_MSG_POLLING_SPAN_US, BAR_MSG_POLLING_SPAN_US + 10);
+		valid = __bar_msg_valid_stat_get(subchan_addr);
+		time_out_cnt++;
+	} while ((time_out_cnt < BAR_MSG_TIMEOUT_TH) &&
+			 (BAR_MSG_CHAN_USED == valid));
+
+	/* 如果超时恢复标志位*/
+	if ((BAR_MSG_TIMEOUT_TH == time_out_cnt) &&
+		(BAR_MSG_CHAN_USABLE != valid)) {
+		__bar_chan_msg_valid_set(subchan_addr, BAR_MSG_CHAN_USABLE);
+		__bar_chan_msg_poltag_set(subchan_addr, 0);
+		BAR_LOG_ERR("BAR MSG ERR: msg_id: %d time out.\n", msg_header.msg_id);
+		ret = BAR_MSG_ERR_TIME_OUT;
+	} else {
+		/* 从消息头中取出回复消息的长度len,
+     * 从payload中取出消息内容，放到本地缓存reps_buff*/
+		ret = __bar_chan_sync_msg_reps_get(subchan_addr,
+										   (uint64_t)result->recv_buffer,
+										   result->buffer_len, msg_id);
+	}
+	__bar_chan_msgid_free(msg_id);
+	/*通道解锁*/
+	bar_chan_unlock(in->src, in->dst, in->src_pcieid);
+
+exit:
+	bar_chan_check_chan_stats(ret, subchan_addr);
+	return ret;
 }
+EXPORT_SYMBOL(zxdh_bar_chan_sync_msg_send);
 
-int bar_chan_msgid_allocate(uint16_t *msgid)
+uint16_t bar_msg_src_parse(struct zxdh_pci_bar_msg *in)
 {
-    int ret = BAR_MSG_OK;
-    uint16_t msg_id = 0;
-    struct msgid_reps_info *msgid_reps_info = NULL;
-    uint16_t count = 0;
-
-    spin_lock(&g_msgid_ring.lock);
-    msg_id = g_msgid_ring.msg_id;
-    do
-    {
-        count++;
-        ++msg_id;
-        msg_id %= MAX_MSG_BUFF_NUM;
-        msgid_reps_info = &g_msgid_ring.reps_info_tbl[msg_id];
-
-    }while(msgid_reps_info->flag != REPS_INFO_FLAG_USABLE && (count < MAX_MSG_BUFF_NUM));
-
-    if (count >= MAX_MSG_BUFF_NUM)
-    {
-        ret = -1;
-        goto out;
-    }
-
-    msgid_reps_info->flag = REPS_INFO_FLAG_USED;
-    g_msgid_ring.msg_id = msg_id;
-    *msgid = msg_id;
-
-out:
-    spin_unlock(&g_msgid_ring.lock);
-    return ret;
+	if (in == NULL) {
+		return BAR_MSG_ERR_NULL;
+	}
+
+	if (in->src == MSG_CHAN_END_MPF) {
+		if (!is_mpf_scaned) {
+			return BAR_MSG_ERR_MPF_NOT_SCANED;
+		}
+		in->virt_addr = (uint64_t)internal_addr + BAR_MSG_OFFSET;
+		in->src_pcieid = PF0_PCIEID;
+	}
+	return BAR_MSG_OK;
 }
 
-uint16_t bar_chan_save_recv_info(struct zxdh_msg_recviver_mem *result, uint16_t *msg_id)
+void __bar_chan_sync_fill_header(uint32_t msg_id, struct zxdh_pci_bar_msg *in,
+								 struct bar_msg_header *msg_header)
 {
-    int ret = 0;
-    struct msgid_reps_info *reps_info = NULL;
-
-    ret = bar_chan_msgid_allocate(msg_id);
-    if (ret == -1)
-    {
-        return BAR_MSG_ERR_MSGID;
-    }
-    reps_info = &g_msgid_ring.reps_info_tbl[*msg_id];
-    reps_info->reps_buffer = result->recv_buffer;
-    reps_info->buffer_len = result->buffer_len;
-
-    return BAR_MSG_OK;
+	memset(msg_header, 0, sizeof(*msg_header));
+	msg_header->sync = BAR_CHAN_MSG_SYNC;
+	msg_header->event_id = in->event_id;
+	msg_header->len = in->payload_len;
+	msg_header->msg_id = msg_id;
+	msg_header->dst_pcieid = in->dst_pcieid;
+	msg_header->src_pcieid = in->src_pcieid;
 }
 
-void bar_chan_msgid_free(uint16_t msg_id)
+int __bar_chan_msgid_allocate(uint16_t *msgid)
 {
-    struct msgid_reps_info *msgid_reps_info = NULL;
-    if (msg_id >= MAX_MSG_BUFF_NUM)
-    {
-        return;
-    }
-    msgid_reps_info = &g_msgid_ring.reps_info_tbl[msg_id];
-    spin_lock(&g_msgid_ring.lock);
-    msgid_reps_info->flag = REPS_INFO_FLAG_USABLE;
-    spin_unlock(&g_msgid_ring.lock);
-    return;
+	uint16_t msg_id = 0;
+	struct msgid_reps_info *msgid_reps_info = NULL;
+	uint16_t count = 0;
+
+	spin_lock(&g_msgid_ring.lock);
+	msg_id = g_msgid_ring.msg_id;
+	do {
+		count++;
+		msg_id = (msg_id >= (MAX_MSG_BUFF_NUM - 1)) ? 0 : msg_id + 1;
+		msgid_reps_info = &g_msgid_ring.reps_info_tbl[msg_id];
+
+	} while (msgid_reps_info->flag != REPS_INFO_FLAG_USABLE &&
+			 (count < MAX_MSG_BUFF_NUM));
+
+	if (count >= MAX_MSG_BUFF_NUM) {
+		spin_unlock(&g_msgid_ring.lock);
+		return -1;
+	}
+
+	msgid_reps_info->flag = REPS_INFO_FLAG_USED;
+	g_msgid_ring.msg_id = msg_id;
+	*msgid = msg_id;
+
+	spin_unlock(&g_msgid_ring.lock);
+	return BAR_MSG_OK;
 }
 
-uint8_t bar_msg_row_index_trans(uint8_t src)
+void __bar_chan_msgid_free(uint16_t msg_id)
 {
-    uint8_t src_index = 0;
-
-    switch (src)
-    {
-        case MSG_CHAN_END_MPF:
-        {
-            src_index = BAR_MSG_SRC_MPF;
-            break;
-        }
-        case MSG_CHAN_END_PF:
-        {
-            src_index = BAR_MSG_SRC_PF;
-            break;
-        }
-        case MSG_CHAN_END_VF:
-        {
-            src_index = BAR_MSG_SRC_VF;
-            break;
-        }
-        default:
-        {
-            src_index = BAR_MSG_SRC_ERR;
-            break;
-        }
-    }
-    return src_index;
-}
+	struct msgid_reps_info *msgid_reps_info =
+			&g_msgid_ring.reps_info_tbl[msg_id];
 
-uint8_t bar_msg_col_index_trans(uint8_t dst)
-{
-    uint8_t dst_index = 0;
-
-    switch (dst)
-    {
-        case MSG_CHAN_END_MPF:
-        {
-            dst_index = BAR_MSG_DST_MPF;
-            break;
-        }
-        case MSG_CHAN_END_PF:
-        {
-            dst_index = BAR_MSG_DST_PFVF;
-            break;
-        }
-        case MSG_CHAN_END_VF:
-        {
-            dst_index = BAR_MSG_DST_PFVF;
-            break;
-        }
-        case MSG_CHAN_END_RISC:
-        {
-            dst_index = BAR_MSG_DST_RISC;
-            break;
-        }
-        default:
-        {
-            dst_index = BAR_MSG_SRC_ERR;
-            break;
-        }
-    }
-    return dst_index;
+	spin_lock(&g_msgid_ring.lock);
+	msgid_reps_info->flag = REPS_INFO_FLAG_USABLE;
+	spin_unlock(&g_msgid_ring.lock);
+	return;
 }
 
-int bar_chan_send_para_check(struct zxdh_pci_bar_msg *in, struct zxdh_msg_recviver_mem *result)
+int __bar_chan_send_para_check(struct zxdh_pci_bar_msg *in,
+							   struct zxdh_msg_recviver_mem *result)
 {
-    uint8_t src_index = 0;
-    uint8_t dst_index = 0;
-
-    if (in == NULL || result == NULL)
-    {
-        BAR_LOG_ERR("send para ERR: null para.\n");
-        return  BAR_MSG_ERR_NULL_PARA;
-    }
-
-    src_index =  bar_msg_row_index_trans((uint8_t)in->src);
-    dst_index =  bar_msg_col_index_trans((uint8_t)in->dst);
-    if (src_index == BAR_MSG_SRC_ERR || dst_index == BAR_MSG_DST_ERR)
-    {
-        BAR_LOG_ERR("send para ERR: chan doesn't exist.\n");
-        return BAR_MSG_ERR_TYPE;
-    }
-    if (in->event_id > MSG_MODULE_NUM)
-    {
-        BAR_LOG_ERR("send para ERR: invalid event_id: %d.\n", in->event_id);
-        return BAR_MSG_ERR_MODULE;
-    }
-    if (in->payload_addr == NULL)
-    {
-        BAR_LOG_ERR("send para ERR: null message.\n");
-        return BAR_MSG_ERR_BODY_NULL;
-    }
-    if (in->payload_len > BAR_MSG_PAYLOAD_MAX_LEN)
-    {
-        BAR_LOG_ERR("send para ERR: len %x is too long.\n", in->payload_len);
-        return BAR_MSG_ERR_LEN;
-    }
-    if (in->virt_addr == 0 || result->recv_buffer == NULL)
-    {
-        BAR_LOG_ERR("send para ERR: virt_addr or recv_buffer is NULL.\n");
-        return BAR_MSG_ERR_VIRTADDR_NULL;
-    }
-    if (result->buffer_len < REPS_HEADER_PAYLOAD_OFFSET)
-    {
-        BAR_LOG_ERR("recv buffer's len: %d is short than mininal 4 bytes\n", result->buffer_len);
-    }
-    return BAR_MSG_OK;
+	uint8_t src_index = 0;
+	uint8_t dst_index = 0;
+
+	if (in == NULL || result == NULL) {
+		BAR_LOG_ERR("send para ERR: null para.\n");
+		return BAR_MSG_ERR_NULL_PARA;
+	}
+
+	src_index = __bar_msg_row_index_trans(in->src);
+	dst_index = __bar_msg_col_index_trans(in->dst);
+	if (src_index == BAR_MSG_SRC_ERR || dst_index == BAR_MSG_DST_ERR) {
+		BAR_LOG_ERR("send para ERR: chan doesn't exist.\n");
+		return BAR_MSG_ERR_TYPE;
+	}
+	if (in->event_id > MSG_MODULE_NUM) {
+		BAR_LOG_ERR("send para ERR: invalid event_id: %d.\n", in->event_id);
+		return BAR_MSG_ERR_MODULE;
+	}
+	if (in->payload_addr == NULL) {
+		BAR_LOG_ERR("send para ERR: null message.\n");
+		return BAR_MSG_ERR_BODY_NULL;
+	}
+	if (in->payload_len > BAR_MSG_PAYLOAD_MAX_LEN) {
+		BAR_LOG_ERR("send para ERR: len %x is too long.\n", in->payload_len);
+		return BAR_MSG_ERR_LEN;
+	}
+	if (in->virt_addr == 0 || result->recv_buffer == NULL) {
+		BAR_LOG_ERR("send para ERR: virt_addr or recv_buffer is NULL.\n");
+		return BAR_MSG_ERR_VIRTADDR_NULL;
+	}
+	if (result->buffer_len < REPS_HEADER_PAYLOAD_OFFSET) {
+		BAR_LOG_ERR("recv buffer's len: %d is short than mininal 4 bytes\n",
+					result->buffer_len);
+	}
+	return BAR_MSG_OK;
 }
 
 /* 根据用户提供的src和dst和当前的场景来推算2K的偏移*/
-void bar_chan_subchan_addr_get(struct zxdh_pci_bar_msg *in, uint64_t *subchan_addr)
+void __bar_chan_subchan_addr_get(struct zxdh_pci_bar_msg *in,
+								 uint64_t *subchan_addr)
 {
-    uint8_t src_index, dst_index;
-    uint16_t chan_id, subchan_id;
+	uint8_t src_index, dst_index;
+	uint16_t chan_id, subchan_id;
 
-    src_index =  bar_msg_row_index_trans((uint8_t)in->src);
-    dst_index =  bar_msg_col_index_trans((uint8_t)in->dst);
+	src_index = __bar_msg_row_index_trans(in->src);
+	dst_index = __bar_msg_col_index_trans(in->dst);
 
-    if (src_index == BAR_MSG_SRC_ERR || dst_index == BAR_MSG_DST_ERR)
-    {
-        return;
-    }
+	if (src_index == BAR_MSG_SRC_ERR || dst_index == BAR_MSG_DST_ERR) {
+		return;
+	}
 
-    chan_id = chan_id_tbl[src_index][dst_index];
-    subchan_id = subchan_id_tbl[src_index][dst_index];
-    *subchan_addr = in->virt_addr + (2 * chan_id + subchan_id) * BAR_MSG_ADDR_CHAN_INTERVAL;
-    return;
+	chan_id = chan_id_tbl[src_index][dst_index];
+	subchan_id = subchan_id_tbl[src_index][dst_index];
+	*subchan_addr = in->virt_addr +
+					(2 * chan_id + subchan_id) * BAR_MSG_ADDR_CHAN_INTERVAL;
+	return;
 }
 
-int bar_chan_reg_write(uint64_t subchan_addr, uint32_t offset, uint32_t data)
+static char payload_temp_buf[BAR_MSG_ADDR_CHAN_INTERVAL] = { 0 };
+uint16_t __bar_chan_msg_send(uint64_t subchan_addr, void *payload_addr,
+							 uint16_t payload_len,
+							 struct bar_msg_header *msg_header)
 {
-    uint32_t algin_offset = (offset & BAR_ALIGN_WORD_MASK);
+	uint8_t *msg = (uint8_t *)(payload_addr);
+	struct bar_msg_header hdr_read = { 0 };
+	uint16_t valid = 0;
 
-    if (algin_offset >= BAR_MSG_ADDR_CHAN_INTERVAL)
-    {
-        return -EADDRNOTAVAIL;
-    }
+	__bar_chan_msg_header_set(subchan_addr, msg_header);
+	__bar_chan_msg_header_get(subchan_addr, &hdr_read);
 
-    writel(data, (volatile void*)(subchan_addr + algin_offset));
-    return 0;
-}
+	__bar_chan_msg_payload_set(subchan_addr, msg, payload_len);
+	__bar_chan_msg_payload_get(subchan_addr, payload_temp_buf, payload_len);
 
-int bar_chan_reg_read(uint64_t subchan_addr, uint32_t offset, uint32_t *pdata)
-{
-    uint32_t algin_offset = (offset & BAR_ALIGN_WORD_MASK);
+	__bar_chan_msg_valid_set(subchan_addr, BAR_MSG_CHAN_USED);
+	valid = __bar_msg_valid_stat_get(subchan_addr);
 
-    if (algin_offset >= BAR_MSG_ADDR_CHAN_INTERVAL)
-    {
-        return -EADDRNOTAVAIL;
-    }
-
-    *pdata = readl((const volatile void *)(subchan_addr + algin_offset));
-    return 0;
+	return BAR_MSG_OK;
 }
 
-uint16_t bar_chan_msg_header_set(uint64_t subchan_addr, struct bar_msg_header *msg_header)
+uint16_t __bar_chan_msg_header_set(uint64_t subchan_addr,
+								   struct bar_msg_header *msg_header)
 {
-    uint32_t *data = (uint32_t*)msg_header;
-    uint16_t idx = 0;
+	uint32_t *data = (uint32_t *)msg_header;
+	uint16_t idx = 0;
 
-    for (idx = 0; idx < (BAR_MSG_PLAYLOAD_OFFSET >> 2); idx++)
-    {
-        bar_chan_reg_write(subchan_addr, idx * 4, *(data + idx));
-    }
+	for (idx = 0; idx < (BAR_MSG_PLAYLOAD_OFFSET >> 2); idx++) {
+		__bar_chan_reg_write(subchan_addr, idx * 4, *(data + idx));
+	}
 
-    return BAR_MSG_OK;
+	return BAR_MSG_OK;
 }
 
-uint16_t bar_chan_msg_header_get(uint64_t subchan_addr, struct bar_msg_header *msg_header)
+uint16_t __bar_chan_msg_header_get(uint64_t subchan_addr,
+								   struct bar_msg_header *msg_header)
 {
-    uint32_t *data = (uint32_t*)msg_header;
-    uint16_t idx = 0;
+	uint32_t *data = (uint32_t *)msg_header;
+	uint16_t idx = 0;
 
-    for (idx = 0; idx < (BAR_MSG_PLAYLOAD_OFFSET >> 2); idx++)
-    {
-        bar_chan_reg_read(subchan_addr, idx * 4, data + idx);
-    }
+	for (idx = 0; idx < (BAR_MSG_PLAYLOAD_OFFSET >> 2); idx++) {
+		__bar_chan_reg_read(subchan_addr, idx * 4, data + idx);
+	}
 
-    return BAR_MSG_OK;
+	return BAR_MSG_OK;
 }
 
-uint16_t bar_chan_msg_payload_set(uint64_t subchan_addr, uint8_t *msg, uint16_t len)
+uint16_t __bar_chan_msg_payload_set(uint64_t subchan_addr, uint8_t *msg,
+									uint16_t len)
 {
-    uint32_t *data = (uint32_t*)msg;
-    uint32_t count = (len / sizeof(uint32_t));
-    uint32_t remain = (len % sizeof(uint32_t));
-    uint32_t ix = 0, remain_data = 0;
-
-    for (ix = 0; ix < count; ix++)
-    {
-        bar_chan_reg_write(subchan_addr, 4 * ix + BAR_MSG_PLAYLOAD_OFFSET, *(data + ix));
-    }
-    for (ix = 0; ix < remain; ix++)
-    {
-        remain_data  |= *((uint8_t *)(msg + (len - remain + ix))) << (8 * ix);
-    }
-    bar_chan_reg_write(subchan_addr, 4 * count + BAR_MSG_PLAYLOAD_OFFSET, remain_data);
-
-    return BAR_MSG_OK;
+	uint32_t *data = (uint32_t *)msg;
+	uint32_t count = (len / sizeof(uint32_t));
+	uint32_t remain = (len % sizeof(uint32_t));
+	uint32_t ix = 0, remain_data = 0;
+
+	for (ix = 0; ix < count; ix++) {
+		__bar_chan_reg_write(subchan_addr, 4 * ix + BAR_MSG_PLAYLOAD_OFFSET,
+							 *(data + ix));
+	}
+	for (ix = 0; ix < remain; ix++) {
+		remain_data |= *((uint8_t *)(msg + (len - remain + ix))) << (8 * ix);
+	}
+	__bar_chan_reg_write(subchan_addr, 4 * count + BAR_MSG_PLAYLOAD_OFFSET,
+						 remain_data);
+
+	return BAR_MSG_OK;
 }
 
-uint16_t bar_chan_msg_payload_get(uint64_t subchan_addr, uint8_t *msg, uint16_t len)
+uint16_t __bar_chan_msg_payload_get(uint64_t subchan_addr, uint8_t *msg,
+									uint16_t len)
 {
-    uint32_t *data = (uint32_t*)msg;
-    uint32_t count = (len / sizeof(uint32_t));
-    uint32_t remain = (len % sizeof(uint32_t));
-    uint32_t ix = 0, remain_data = 0;
-
-    for (ix = 0; ix < count; ix++)
-    {
-        bar_chan_reg_read(subchan_addr, 4 * ix + BAR_MSG_PLAYLOAD_OFFSET, (data + ix));
-    }
-    bar_chan_reg_read(subchan_addr, 4 * count + BAR_MSG_PLAYLOAD_OFFSET, &remain_data);
-    for (ix = 0; ix < remain; ix++)
-    {
-        *((uint8_t *)(msg + (len - remain + ix))) = remain_data >> (8 * ix);
-    }
-    return BAR_MSG_OK;
+	uint32_t *data = (uint32_t *)msg;
+	uint32_t count = (len / sizeof(uint32_t));
+	uint32_t remain = (len % sizeof(uint32_t));
+	uint32_t ix = 0, remain_data = 0;
+
+	for (ix = 0; ix < count; ix++) {
+		__bar_chan_reg_read(subchan_addr, 4 * ix + BAR_MSG_PLAYLOAD_OFFSET,
+							(data + ix));
+	}
+	__bar_chan_reg_read(subchan_addr, 4 * count + BAR_MSG_PLAYLOAD_OFFSET,
+						&remain_data);
+	for (ix = 0; ix < remain; ix++) {
+		*((uint8_t *)(msg + (len - remain + ix))) = remain_data >> (8 * ix);
+	}
+	return BAR_MSG_OK;
 }
 
-uint16_t  bar_chan_msg_valid_set(uint64_t subchan_addr, uint8_t valid_label)
+uint16_t __bar_chan_msg_valid_set(uint64_t subchan_addr, uint8_t valid_label)
 {
-    uint32_t data = 0;
+	uint32_t data = 0;
 
-    bar_chan_reg_read(subchan_addr, BAR_MSG_VALID_OFFSET, &data);
-    data &= (~BAR_MSG_VALID_MASK);
-    data |= (uint32_t)valid_label;
-    bar_chan_reg_write(subchan_addr, BAR_MSG_VALID_OFFSET, data);
+	__bar_chan_reg_read(subchan_addr, BAR_MSG_VALID_OFFSET, &data);
+	data &= (~BAR_MSG_VALID_MASK);
+	data |= (uint32_t)valid_label;
+	__bar_chan_reg_write(subchan_addr, BAR_MSG_VALID_OFFSET, data);
 
-    return BAR_MSG_OK;
+	return BAR_MSG_OK;
 }
 
-uint16_t bar_msg_valid_stat_get(uint64_t subchan_addr)
+uint16_t __bar_msg_valid_stat_get(uint64_t subchan_addr)
 {
-    uint32_t data = 0;
+	uint32_t data = 0;
 
-    bar_chan_reg_read(subchan_addr, BAR_MSG_VALID_OFFSET, &data);
-    if (BAR_MSG_CHAN_USABLE == (data & BAR_MSG_VALID_MASK))
-    {
-        return BAR_MSG_CHAN_USABLE;
-    }
+	__bar_chan_reg_read(subchan_addr, BAR_MSG_VALID_OFFSET, &data);
+	if (BAR_MSG_CHAN_USABLE == (data & BAR_MSG_VALID_MASK)) {
+		return BAR_MSG_CHAN_USABLE;
+	}
 
-    return BAR_MSG_CHAN_USED;
+	return BAR_MSG_CHAN_USED;
 }
 
-uint16_t  bar_chan_msg_poltag_set(uint64_t subchan_addr, uint8_t label)
+uint16_t __bar_chan_msg_poltag_set(uint64_t subchan_addr, uint8_t label)
 {
-    uint32_t data = 0;
+	uint32_t data = 0;
 
-    bar_chan_reg_read(subchan_addr, BAR_MSG_VALID_OFFSET, &data);
-    data &= (~(uint32_t)BAR_MSG_POL_MASK);
-    data |= ((uint32_t)label << BAR_MSG_POL_OFFSET);
-    bar_chan_reg_write(subchan_addr, BAR_MSG_VALID_OFFSET, data);
+	__bar_chan_reg_read(subchan_addr, BAR_MSG_VALID_OFFSET, &data);
+	data &= (~(uint32_t)BAR_MSG_POL_MASK);
+	data |= ((uint32_t)label << BAR_MSG_POL_OFFSET);
+	__bar_chan_reg_write(subchan_addr, BAR_MSG_VALID_OFFSET, data);
 
-    return BAR_MSG_OK;
+	return BAR_MSG_OK;
 }
 
-static uint8_t payload_temp_buf[BAR_MSG_ADDR_CHAN_INTERVAL] = {0};
-uint16_t bar_chan_msg_send(uint64_t subchan_addr, void *payload_addr, uint16_t payload_len, struct bar_msg_header *msg_header)
+uint16_t __bar_chan_sync_msg_reps_get(uint64_t subchan_addr,
+									  uint64_t recv_buffer, uint16_t buffer_len,
+									  uint16_t send_msg_id)
 {
-    uint8_t *msg = (uint8_t*)(payload_addr);
-    struct bar_msg_header hdr_read = {0};
-    uint16_t valid = 0;
-
-    bar_chan_msg_header_set(subchan_addr, msg_header);
-    bar_chan_msg_header_get(subchan_addr, &hdr_read);
-
-    bar_chan_msg_payload_set(subchan_addr, msg, payload_len);
-    bar_chan_msg_payload_get(subchan_addr, payload_temp_buf, payload_len);
-
-    bar_chan_msg_valid_set(subchan_addr, BAR_MSG_CHAN_USED);
-    valid = bar_msg_valid_stat_get(subchan_addr);
-
-    return BAR_MSG_OK;
+	uint16_t recv_msg_id = 0;
+	uint16_t recv_len = 0;
+	uint8_t *recv_msg = (uint8_t *)recv_buffer;
+	struct bar_msg_header msg_header;
+	struct msgid_reps_info *reps_info = NULL;
+
+	/*从消息头中取出消息回复的长度，取出msg_id，如果msg_id对应的usable的话，该条同步回复作废*/
+	memset(&msg_header, 0, sizeof(msg_header));
+	__bar_chan_msg_header_get(subchan_addr, &msg_header);
+	recv_len = msg_header.len;
+	recv_msg_id = msg_header.msg_id;
+
+	if (recv_msg_id != send_msg_id) {
+		BAR_LOG_ERR("send msg id: %d, but get reply msg id: %d.\n", send_msg_id,
+					recv_msg_id);
+		return BAR_MSG_ERR_REPLY;
+	}
+
+	reps_info = &g_msgid_ring.reps_info_tbl[recv_msg_id];
+	if (reps_info->flag != REPS_INFO_FLAG_USED) {
+		BAR_LOG_ERR("msg_id: %d is release", recv_msg_id);
+		return BAR_MSG_ERR_REPLY;
+	}
+	if (recv_len > buffer_len - REPS_HEADER_PAYLOAD_OFFSET) {
+		BAR_LOG_ERR("reps_buf_len is %d, but reps_msg_len is %d", buffer_len,
+					recv_len + 4);
+		return BAR_MSG_ERR_REPSBUFF_LEN;
+	}
+
+	/* 从reps_buff + 4的位置拷贝进回复数据*/
+	__bar_chan_msg_payload_get(subchan_addr,
+							   recv_msg + REPS_HEADER_PAYLOAD_OFFSET, recv_len);
+
+	/* 拷贝数据长度*/
+	*(uint16_t *)(recv_msg + REPS_HEADER_LEN_OFFSET) = recv_len;
+	/* reps头valid置位*/
+	*recv_msg = REPS_HEADER_REPLYED;
+
+	return BAR_MSG_OK;
 }
 
-int bar_chan_recv_func_check(uint16_t check)
+uint8_t __bar_msg_row_index_trans(uint8_t src)
 {
-    if (CHECK_STATE_OK == check)
-    {
-        return BAR_MSG_OK;
-    }
-    else
-    {
-        BAR_LOG_ERR("recv func check failed, check field: 0x%x", check);
-        return BAR_MSG_ERR_USR_RET_ERR;
-    }
+	uint8_t src_index = 0;
+
+	switch (src) {
+	case MSG_CHAN_END_MPF: {
+		src_index = BAR_MSG_SRC_MPF;
+		break;
+	}
+	case MSG_CHAN_END_PF: {
+		src_index = BAR_MSG_SRC_PF;
+		break;
+	}
+	case MSG_CHAN_END_VF: {
+		src_index = BAR_MSG_SRC_VF;
+		break;
+	}
+	default: {
+		src_index = BAR_MSG_SRC_ERR;
+		break;
+	}
+	}
+	return src_index;
 }
 
-int bar_chan_sync_msg_reps_get(uint64_t subchan_addr, uint64_t recv_buffer, uint16_t buffer_len, uint16_t send_msg_id)
+uint8_t __bar_msg_col_index_trans(uint8_t dst)
 {
-    int ret = BAR_MSG_OK;
-    uint16_t recv_msg_id = 0;
-    uint16_t recv_len = 0;
-    uint8_t *recv_msg =  (uint8_t*)recv_buffer;
-    struct bar_msg_header msg_header;
-    struct msgid_reps_info *reps_info = NULL;
-
-    /*从消息头中取出消息回复的长度，取出msg_id，如果msg_id对应的usable的话，该条同步回复作废*/
-    memset(&msg_header, 0, sizeof(msg_header));
-    bar_chan_msg_header_get(subchan_addr, &msg_header);
-    recv_len = msg_header.len;
-    recv_msg_id = msg_header.msg_id;
-
-    if (recv_msg_id != send_msg_id)
-    {
-        BAR_LOG_ERR("send msg id: %d, but get reply msg id: %d.\n", send_msg_id, recv_msg_id);
-        ret = BAR_MSG_ERR_REPLY;
-        goto out;
-    }
-
-    reps_info = &g_msgid_ring.reps_info_tbl[recv_msg_id];
-    if (reps_info->flag != REPS_INFO_FLAG_USED)
-    {
-        BAR_LOG_ERR("msg_id: %d is release", recv_msg_id);
-        ret = BAR_MSG_ERR_REPLY;
-        goto out;
-    }
-    if (recv_len > buffer_len - REPS_HEADER_PAYLOAD_OFFSET)
-    {
-        BAR_LOG_ERR("reps_buf_len is %d, but reps_msg_len is %d", buffer_len, recv_len + 4);
-        ret = BAR_MSG_ERR_REPSBUFF_LEN;
-        goto out;
-    }
-
-    /* 从reps_buff + 4的位置拷贝进回复数据*/
-    bar_chan_msg_payload_get(subchan_addr, recv_msg + REPS_HEADER_PAYLOAD_OFFSET, recv_len);
-
-    ret = bar_chan_recv_func_check(msg_header.check);
-    if (ret != BAR_MSG_OK)
-    {
-        goto out;
-    }
-
-    /* 拷贝数据长度*/
-    *(uint16_t*)(recv_msg + REPS_HEADER_LEN_OFFSET) = recv_len;
-    /* reps头valid置位*/
-    *recv_msg = REPS_HEADER_REPLYED;
-
-out:
-    return ret;
+	uint8_t dst_index = 0;
+
+	switch (dst) {
+	case MSG_CHAN_END_MPF: {
+		dst_index = BAR_MSG_DST_MPF;
+		break;
+	}
+	case MSG_CHAN_END_PF: {
+		dst_index = BAR_MSG_DST_PFVF;
+		break;
+	}
+	case MSG_CHAN_END_VF: {
+		dst_index = BAR_MSG_DST_PFVF;
+		break;
+	}
+	case MSG_CHAN_END_RISC: {
+		dst_index = BAR_MSG_DST_RISC;
+		break;
+	}
+	default: {
+		dst_index = BAR_MSG_SRC_ERR;
+		break;
+	}
+	}
+	return dst_index;
 }
 
-uint64_t subchan_addr_cal(uint64_t virt_addr, uint8_t chan_id, uint8_t subchan_id)
+int __bar_chan_reg_write(uint64_t subchan_addr, uint32_t offset, uint32_t data)
 {
-    return virt_addr + (2 * chan_id + subchan_id) * BAR_MSG_ADDR_CHAN_INTERVAL;
+	uint32_t algin_offset = (offset & BAR_ALIGN_WORD_MASK);
+
+	if (algin_offset >= BAR_MSG_ADDR_CHAN_INTERVAL) {
+		return -EADDRNOTAVAIL;
+	}
+
+	writel(data, (volatile void *)(subchan_addr + algin_offset));
+	return 0;
 }
 
-uint64_t recv_addr_get(uint8_t src_type, uint8_t dst_type, uint64_t virt_addr)
+int __bar_chan_reg_read(uint64_t subchan_addr, uint32_t offset, uint32_t *pdata)
 {
-    uint8_t chan_id = 0;
-    uint8_t subchan_id = 0;
-    uint8_t src = bar_msg_col_index_trans(src_type);
-    uint8_t dst = bar_msg_row_index_trans(dst_type);
-
-    if (src >= BAR_MSG_SRC_NUM || dst >= BAR_MSG_DST_NUM)
-    {
-        return 0;
-    }
-    /* 接收通道id和发送通道id相同*/
-    chan_id = chan_id_tbl[dst][src];
-    /* 接收子通道id和发送子通道相反*/
-    subchan_id = (!!subchan_id_tbl[dst][src])? BAR_SUBCHAN_INDEX_SEND : BAR_SUBCHAN_INDEX_RECV;
-    return subchan_addr_cal(virt_addr, chan_id, subchan_id);
+	uint32_t algin_offset = (offset & BAR_ALIGN_WORD_MASK);
+
+	if (algin_offset >= BAR_MSG_ADDR_CHAN_INTERVAL) {
+		return -EADDRNOTAVAIL;
+	}
+
+	*pdata = readl((const volatile void *)(subchan_addr + algin_offset));
+	return 0;
 }
 
-uint64_t reply_addr_get(uint8_t sync, uint8_t src_type, uint8_t dst_type, uint64_t virt_addr)
+uint64_t subchan_addr_cal(uint64_t virt_addr, uint8_t chan_id,
+						  uint8_t subchan_id)
 {
-    uint8_t chan_id = 0;
-    uint8_t subchan_id = 0;
-    uint64_t recv_rep_addr = 0;
-    uint8_t src = bar_msg_col_index_trans(src_type);
-    uint8_t dst = bar_msg_row_index_trans(dst_type);
-
-    if (src == BAR_MSG_SRC_ERR || dst == BAR_MSG_DST_ERR)
-    {
-        return 0;
-    }
-
-    chan_id = chan_id_tbl[dst][src];
-    subchan_id = (!!subchan_id_tbl[dst][src])? BAR_SUBCHAN_INDEX_SEND : BAR_SUBCHAN_INDEX_RECV;
-    if (sync == BAR_CHAN_MSG_SYNC) //同步消息
-    {
-        recv_rep_addr = subchan_addr_cal(virt_addr, chan_id, subchan_id);
-    }
-    else
-    {
-        recv_rep_addr = subchan_addr_cal(virt_addr, chan_id, 1 - subchan_id);
-    }
-    return recv_rep_addr;
+	return virt_addr + (2 * chan_id + subchan_id) * BAR_MSG_ADDR_CHAN_INTERVAL;
 }
 
-uint16_t bar_chan_msg_header_check(struct bar_msg_header *msg_header)
+uint64_t recv_addr_get(uint8_t src_type, uint8_t dst_type, uint64_t virt_addr)
 {
-    uint8_t event_id = 0;
-    uint16_t len = 0;
-
-    if (msg_header == NULL)
-    {
-        return BAR_MSG_ERR_NULL;
-    }
-    if (msg_header->valid != BAR_MSG_CHAN_USED)
-    {
-        BAR_LOG_ERR("recv header ERR: valid label is not used.\n");
-        return BAR_MSG_ERR_MODULE;
-    }
-    event_id = msg_header->event_id;
-    if (event_id >= (uint8_t)MSG_MODULE_NUM)
-    {
-        BAR_LOG_ERR("recv header ERR: invalid event_id: %d.\n", event_id);
-        return BAR_MSG_ERR_MODULE;
-    }
-    len = msg_header->len;
-    if (len > BAR_MSG_PAYLOAD_MAX_LEN)
-    {
-        BAR_LOG_ERR("recv header ERR: invalid mesg len: %d.\n", len);
-        return BAR_MSG_ERR_LEN;
-    }
-    if (msg_header->ack == BAR_CHAN_MSG_NO_ACK && msg_recv_func_tbl[msg_header->event_id] == NULL)
-    {
-        BAR_LOG_DEBUG("recv header ERR: module:%d  doesn't register", event_id);
-        return BAR_MSG_ERR_MODULE_NOEXIST;
-    }
-    return BAR_MSG_OK;
+	uint8_t chan_id = 0;
+	uint8_t subchan_id = 0;
+	uint8_t src = __bar_msg_col_index_trans(src_type);
+	uint8_t dst = __bar_msg_row_index_trans(dst_type);
+
+	if (src >= BAR_MSG_SRC_NUM || dst >= BAR_MSG_DST_NUM) {
+		return 0;
+	}
+	/* 接收通道id和发送通道id相同*/
+	chan_id = chan_id_tbl[dst][src];
+	/* 接收子通道id和发送子通道相反*/
+	subchan_id = (!!subchan_id_tbl[dst][src]) ? BAR_SUBCHAN_INDEX_SEND :
+												  BAR_SUBCHAN_INDEX_RECV;
+	return subchan_addr_cal(virt_addr, chan_id, subchan_id);
 }
 
+uint64_t reply_addr_get(uint8_t sync, uint8_t src_type, uint8_t dst_type,
+						uint64_t virt_addr)
+{
+	uint8_t chan_id = 0;
+	uint8_t subchan_id = 0;
+	uint64_t recv_rep_addr = 0;
+	uint8_t src = __bar_msg_col_index_trans(src_type);
+	uint8_t dst = __bar_msg_row_index_trans(dst_type);
+
+	if (src == BAR_MSG_SRC_ERR || dst == BAR_MSG_DST_ERR) {
+		return 0;
+	}
+
+	chan_id = chan_id_tbl[dst][src];
+	subchan_id = (!!subchan_id_tbl[dst][src]) ? BAR_SUBCHAN_INDEX_SEND :
+												  BAR_SUBCHAN_INDEX_RECV;
+	if (sync == BAR_CHAN_MSG_SYNC) { //同步消息
+		recv_rep_addr = subchan_addr_cal(virt_addr, chan_id, subchan_id);
+	} else {
+		recv_rep_addr = subchan_addr_cal(virt_addr, chan_id, 1 - subchan_id);
+	}
+	return recv_rep_addr;
+}
 
-/* 同步消息接收处理*/
-void bar_msg_sync_msg_proc(uint64_t reply_addr, struct bar_msg_header *msg_header, uint8_t *reciver_buff, void *dev)
+void swap_src_dst(struct bar_msg_header *msg_header)
 {
-    uint16_t reps_len = 0;
-    uint8_t *reps_buffer = NULL;
-    zxdh_bar_chan_msg_recv_callback  recv_func = NULL;
-
-    reps_buffer = kmalloc(BAR_MSG_PAYLOAD_MAX_LEN, GFP_KERNEL);
-    if (reps_buffer == NULL)
-    {
-        return;
-    }
-    /* 查询消息处理函数，处理消息，消息处理的结果放到reps_buffer中， 长度放到reps_len中*/
-    recv_func = msg_recv_func_tbl[msg_header->event_id];
-    recv_func(reciver_buff, msg_header->len, reps_buffer, &reps_len, dev);
-    msg_header->ack = BAR_CHAN_MSG_ACK;
-    msg_header->len = reps_len;
-    /* 计算回复消息2K的地址*/
-    bar_chan_msg_header_set(reply_addr, msg_header);
-    bar_chan_msg_payload_set(reply_addr, reps_buffer, reps_len);
-    bar_chan_msg_valid_set(reply_addr, BAR_MSG_CHAN_USABLE);
-
-    BAR_KFREE_PTR(reps_buffer);
-    return;
+	uint16_t temp = 0;
+
+	if (!msg_header) {
+		return;
+	}
+	temp = msg_header->src_pcieid;
+	msg_header->src_pcieid = msg_header->dst_pcieid;
+	msg_header->dst_pcieid = temp;
 }
 
 /* 统一的中断处理函数*/
 int zxdh_bar_irq_recv(uint8_t src, uint8_t dst, uint64_t virt_addr, void *dev)
 {
-    uint64_t recv_addr = 0;
-    uint64_t reps_addr = 0;
-    struct bar_msg_header msg_header = {0};
-    uint8_t *recved_msg = NULL;
-    uint16_t ret = 0;
-
-    /*1 接收消息地址*/
-    recv_addr = recv_addr_get(src, dst, virt_addr);
-    BAR_LOG_DEBUG("recv_addr: 0x%llx, \nvirt_addr: 0x%llx", recv_addr, virt_addr);
-    if (recv_addr == 0)
-    {
-        BAR_LOG_DEBUG("invalid driver type");
-        return BAR_MSG_ERR_NULL;
-    }
-    /*2 取消息头并检查是否合法*/
-    bar_chan_msg_header_get(recv_addr, &msg_header);
-    ret = bar_chan_msg_header_check(&msg_header);
-    if (ret != BAR_MSG_OK)
-    {
-        bar_chan_check_chan_stats(ret, recv_addr);
-        return ret;
-    }
-    /*3 创建消息payload buf，取出消息暂存*/
-    recved_msg = kmalloc(msg_header.len, GFP_KERNEL);
-    if (recved_msg == NULL)
-    {
-        BAR_LOG_DEBUG("create temp buff failed");
-        return BAR_MSG_ERR_NULL;
-    }
-    bar_chan_msg_payload_get(recv_addr, recved_msg, msg_header.len);
-
-    /*4 根据来的是同步消息还是异步消息计算回复消息地址*/
-    reps_addr = reply_addr_get(msg_header.sync, src, dst, virt_addr);
-
-    /*5 如果是同步消息，走同步消息流程*/
-    if (msg_header.sync == BAR_CHAN_MSG_SYNC)
-    {
-        bar_msg_sync_msg_proc(reps_addr, &msg_header, recved_msg, dev);
-        goto out;
-    }
-
-    /*6 不应该为异步消息，先置位告诉对方已收到消息*/
-    BAR_LOG_DEBUG("%d end set valid", dst);
-    //TODO set 错误码
-    bar_chan_msg_poltag_set(recv_addr, 0);
-    bar_chan_msg_valid_set(recv_addr, BAR_MSG_CHAN_USABLE);
-
-out:
-    kfree(recved_msg);
-    return BAR_MSG_OK;
+	uint64_t recv_addr = 0;
+	uint64_t reps_addr = 0;
+	struct bar_msg_header msg_header = { 0 };
+	uint8_t *recved_msg = NULL;
+	uint16_t ret = 0;
+
+	/*1 接收消息地址*/
+	recv_addr = recv_addr_get(src, dst, virt_addr);
+	BAR_LOG_DEBUG("recv_addr: 0x%llx, \nvirt_addr: 0x%llx", recv_addr,
+				  virt_addr);
+	if (recv_addr == 0) {
+		BAR_LOG_DEBUG("invalid driver type");
+		return BAR_MSG_ERR_NULL;
+	}
+	/*2 取消息头并检查是否合法*/
+	__bar_chan_msg_header_get(recv_addr, &msg_header);
+	ret = __bar_chan_msg_header_check(&msg_header);
+	if (ret != BAR_MSG_OK) {
+		bar_chan_check_chan_stats(ret, recv_addr);
+		return ret;
+	}
+	/*3 创建消息payload buf，取出消息暂存*/
+	recved_msg = kmalloc(msg_header.len, GFP_KERNEL);
+	if (recved_msg == NULL) {
+		BAR_LOG_DEBUG("create temp buff failed");
+		return BAR_MSG_ERR_NULL;
+	}
+	__bar_chan_msg_payload_get(recv_addr, recved_msg, msg_header.len);
+
+	/*4 根据来的是同步消息还是异步消息计算回复消息地址*/
+	reps_addr = reply_addr_get(msg_header.sync, src, dst, virt_addr);
+
+	/*5 如果是同步消息，走同步消息流程*/
+	if (msg_header.sync == BAR_CHAN_MSG_SYNC) {
+		__bar_msg_sync_msg_proc(reps_addr, &msg_header, recved_msg, dev);
+		goto exit;
+	}
+
+	/*6 异步消息，先置位告诉对方已收到消息*/
+	BAR_LOG_DEBUG("%d end set valid", dst);
+	__bar_chan_msg_valid_set(recv_addr, BAR_MSG_CHAN_USABLE);
+	__bar_chan_msg_poltag_set(recv_addr, 0);
+	if (msg_header.ack == BAR_CHAN_MSG_ACK) {
+		/* 7 如果是回复消息，按照回复消息处理流程*/
+		__bar_msg_ack_async_msg_proc(&msg_header, recved_msg);
+		goto exit;
+	} else {
+		/* 8 异步非回复消息*/
+		swap_src_dst(&msg_header);
+		__bar_msg_noack_async_msg_proc(reps_addr, &msg_header, recved_msg, src,
+									   dst, dev);
+	}
+
+exit:
+	kfree(recved_msg);
+	return BAR_MSG_OK;
 }
 EXPORT_SYMBOL(zxdh_bar_irq_recv);
 
-int32_t call_msg_recv_func_tbl(uint16_t event_id, void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev)
+int32_t call_msg_recv_func_tbl(uint16_t event_id, void *pay_load, uint16_t len,
+							   void *reps_buffer, uint16_t *reps_len, void *dev)
 {
-    zxdh_bar_chan_msg_recv_callback recv_func = NULL;
+	zxdh_bar_chan_msg_recv_callback recv_func = NULL;
 
-    recv_func = msg_recv_func_tbl[event_id];
-    if (unlikely(recv_func == NULL))
-    {
-        BAR_LOG_ERR("event_id[%d] unregister\n", event_id);
-        return BAR_MSG_ERR_MODULE_NOEXIST;
-    }
+	recv_func = msg_recv_func_tbl[event_id];
+	if (unlikely(recv_func == NULL)) {
+		BAR_LOG_ERR("event_id[%d] unregister\n", event_id);
+		return BAR_MSG_ERR_MODULE_NOEXIST;
+	}
 
-    return recv_func(pay_load, len, reps_buffer, reps_len, dev);
+	return recv_func(pay_load, len, reps_buffer, reps_len, dev);
 }
 EXPORT_SYMBOL(call_msg_recv_func_tbl);
 
+/* 同步消息接收处理*/
+void __bar_msg_sync_msg_proc(uint64_t reply_addr,
+							 struct bar_msg_header *msg_header,
+							 uint8_t *reciver_buff, void *dev)
+{
+	uint16_t reps_len = 0;
+	uint8_t *reps_buffer = NULL;
+	zxdh_bar_chan_msg_recv_callback recv_func = NULL;
+
+	reps_buffer = kmalloc(BAR_MSG_PAYLOAD_MAX_LEN, GFP_KERNEL);
+	if (reps_buffer == NULL) {
+		return;
+	}
+	/* 查询消息处理函数，处理消息，消息处理的结果放到reps_buffer中，
+   * 长度放到reps_len中*/
+	recv_func = msg_recv_func_tbl[msg_header->event_id];
+	recv_func(reciver_buff, msg_header->len, reps_buffer, &reps_len, dev);
+	msg_header->ack = BAR_CHAN_MSG_ACK;
+	msg_header->len = reps_len;
+	/* 计算回复消息2K的地址*/
+	__bar_chan_msg_header_set(reply_addr, msg_header);
+	__bar_chan_msg_payload_set(reply_addr, reps_buffer, reps_len);
+	__bar_chan_msg_valid_set(reply_addr, BAR_MSG_CHAN_USABLE);
+
+	BAR_KFREE_PTR(reps_buffer);
+	return;
+}
+
+/* 异步回复消息处理*/
+void __bar_msg_ack_async_msg_proc(struct bar_msg_header *msg_header,
+								  uint8_t *reciver_buff)
+{
+	struct msgid_reps_info *reps_info =
+			&g_msgid_ring.reps_info_tbl[msg_header->msg_id];
+	uint8_t *reps_buffer = (uint8_t *)reps_info->reps_buffer;
+
+	if ((msg_header->len) > (reps_info->buffer_len) - 4) {
+		BAR_LOG_ERR(
+				"reciver ERR: recv_buffer is too short to store reply msg.");
+		goto free_id;
+	}
+	memcpy(reps_buffer + 4, reciver_buff, msg_header->len);
+	*(uint16_t *)(reps_buffer + 1) = msg_header->len;
+	*(uint8_t *)(reps_info->reps_buffer) = REPS_HEADER_REPLYED;
+
+free_id:
+	__bar_chan_msgid_free(msg_header->msg_id);
+	return;
+}
+
+/* 异步非回复消息处理*/
+void __bar_msg_noack_async_msg_proc(uint64_t reps_addr,
+									struct bar_msg_header *msg_header,
+									uint8_t *reciver_buff, uint8_t src,
+									uint8_t dst, void *dev)
+{
+	uint16_t reps_len = 0;
+	uint8_t *temp_buffer = NULL;
+	zxdh_bar_chan_msg_recv_callback recv_func = NULL;
+	struct bar_async_node *node = NULL;
+
+	/* 查询消息处理函数，处理消息，消息处理的结果放到reps_buff中，
+   * 长度放到reps_len中*/
+	recv_func = msg_recv_func_tbl[msg_header->event_id];
+	temp_buffer = kmalloc(BAR_MSG_PAYLOAD_MAX_LEN, GFP_KERNEL);
+	if (temp_buffer == NULL) {
+		BAR_LOG_ERR("msg reply err: fail to allocate temp_buffer.\n");
+		return;
+	}
+	recv_func(reciver_buff, msg_header->len, temp_buffer, &reps_len, dev);
+
+	node = (struct bar_async_node *)kmalloc(sizeof(*node), GFP_KERNEL);
+	if (node == NULL) {
+		BAR_LOG_ERR("msg reply err: fail to allocate temp_buffer.\n");
+		BAR_KFREE_PTR(temp_buffer);
+		return;
+	}
+
+	node->subchan_addr = reps_addr;
+	node->payload_addr = (void *)temp_buffer;
+	node->payload_len = reps_len;
+	node->ack = BAR_CHAN_MSG_ACK;
+
+	node->msg_id = msg_header->msg_id;
+	node->event_id = msg_header->event_id;
+	node->dst_pcieid = msg_header->dst_pcieid;
+	node->src_pcieid = msg_header->src_pcieid;
+	node->emec = msg_header->emec;
+	node->src = src;
+	node->dst = dst;
+
+	__bar_chan_async_node_add(node);
+	return;
+}
+
+uint16_t __bar_chan_msg_header_check(struct bar_msg_header *msg_header)
+{
+	uint8_t event_id = 0;
+	uint16_t len = 0;
+
+	if (msg_header == NULL) {
+		return BAR_MSG_ERR_NULL;
+	}
+	if (msg_header->valid != BAR_MSG_CHAN_USED) {
+		BAR_LOG_ERR("recv header ERR: valid label is not used.\n");
+		return BAR_MSG_ERR_MODULE;
+	}
+	event_id = msg_header->event_id;
+	if (event_id >= (uint8_t)MSG_MODULE_NUM) {
+		BAR_LOG_ERR("recv header ERR: invalid event_id: %d.\n", event_id);
+		return BAR_MSG_ERR_MODULE;
+	}
+	len = msg_header->len;
+	if (len > BAR_MSG_PAYLOAD_MAX_LEN) {
+		BAR_LOG_ERR("recv header ERR: invalid mesg len: %d.\n", len);
+		return BAR_MSG_ERR_LEN;
+	}
+	if (msg_header->ack == BAR_CHAN_MSG_NO_ACK &&
+		msg_recv_func_tbl[msg_header->event_id] == NULL) {
+		BAR_LOG_DEBUG("recv header ERR: module:%d  doesn't register", event_id);
+		return BAR_MSG_ERR_MODULE_NOEXIST;
+	}
+	return BAR_MSG_OK;
+}
 
 /**
- * zxdh_bar_chan_sync_msg_send - 通过PCIE BAR空间发送同步消息
+ * zxdh_bar_chan_async_msg_send - 通过PCIE BAR空间发送异步消息
  * @in: 消息发送信息
  * @result: 消息结果反馈
  * @return: 0 成功，其他失败
  */
-int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in, struct zxdh_msg_recviver_mem *result)
+int zxdh_bar_chan_async_msg_send(struct zxdh_pci_bar_msg *in,
+								 struct zxdh_msg_recviver_mem *result)
 {
-    int ret = 0;
-    uint16_t valid = 0;
-    uint16_t time_out_cnt = 0;
-    uint16_t msg_id = 0;
-    uint64_t subchan_addr = 0;
-    struct bar_msg_header msg_header = {0};
-
-    ret =  bar_msg_src_parse(in);
-    if (ret != BAR_MSG_OK)
-    {
-        goto out;
-    }
-
-    ret = bar_chan_send_para_check(in, result);
-    if (ret != BAR_MSG_OK)
-    {
-        BAR_LOG_ERR("para check failed, %d.", ret);
-        goto out;
-    }
-
-    /* 申请msg_id,并将缓存信息存放到表中*/
-    ret = bar_chan_save_recv_info(result, &msg_id);
-    if (ret != BAR_MSG_OK)
-    {
-       BAR_LOG_ERR("msg_id allocated failed.");
-       goto out;
-    }
-    /* 计算2K通道的地址*/
-    bar_chan_subchan_addr_get(in, &subchan_addr);
-    /* 填充消息头*/
-    bar_chan_sync_fill_header(msg_id, in, &msg_header);
-    /* 给通道上锁，根据src和dst判断是分配硬件锁还是软件锁*/
-    bar_chan_lock((uint8_t)in->src, (uint8_t)in->dst, in->src_pcieid);
-
-    /* 消息头、消息体发送到bar空间， valid置位*/
-    bar_chan_msg_send(subchan_addr, in->payload_addr, in->payload_len, &msg_header);
-    /* 轮询等待消息回复*/
-    do
-    {
-        usleep_range(BAR_MSG_POLLING_SPAN_US, BAR_MSG_POLLING_SPAN_US + 10);
-        valid = bar_msg_valid_stat_get(subchan_addr);
-        time_out_cnt++;
-    }while((time_out_cnt < BAR_MSG_TIMEOUT_TH) && (BAR_MSG_CHAN_USED == valid));
-
-    /* 如果超时恢复标志位*/
-    if ((BAR_MSG_TIMEOUT_TH == time_out_cnt) && (BAR_MSG_CHAN_USABLE != valid))
-    {
-        bar_chan_msg_valid_set(subchan_addr, BAR_MSG_CHAN_USABLE);
-        bar_chan_msg_poltag_set(subchan_addr, 0);
-        BAR_LOG_ERR("BAR MSG ERR: msg_id: %d time out.\n", msg_header.msg_id);
-        ret =  BAR_MSG_ERR_TIME_OUT;
-    }
-    else
-    {
-        /* 从消息头中取出回复消息的长度len, 从payload中取出消息内容，放到本地缓存reps_buff*/
-        ret = bar_chan_sync_msg_reps_get(subchan_addr, (uint64_t)result->recv_buffer, result->buffer_len, msg_id);
-    }
-    bar_chan_msgid_free(msg_id);
-    /*通道解锁*/
-    bar_chan_unlock((uint8_t)in->src, (uint8_t)in->dst, in->src_pcieid);
-    bar_chan_check_chan_stats(ret, subchan_addr);
-out:
-    return ret;
+	struct bar_async_node *node = NULL;
+	uint16_t ret = 0;
+	uint16_t msg_id = 0;
+
+	ret = bar_msg_src_parse(in);
+	if (ret != BAR_MSG_OK) {
+		goto exit;
+	}
+
+	ret = __bar_chan_send_para_check(in, result);
+	if (ret != BAR_MSG_OK) {
+		BAR_LOG_ERR("para check failed, %d.", ret);
+		goto exit;
+	}
+
+	ret = __bar_chan_save_recv_info(result, &msg_id);
+	if (ret != BAR_MSG_OK) {
+		BAR_LOG_DEBUG("msg_id allocate failed");
+		goto exit;
+	}
+
+	/* 创造节点, 并将节点插入到列表中去*/
+	node = __bar_chan_async_node_create(msg_id, in);
+	if (!node) {
+		BAR_LOG_ERR("creating node failed.\n");
+		return BAR_MSG_ERR_NULL;
+	}
+	__bar_chan_async_node_add(node);
+
+exit:
+	return ret;
+}
+EXPORT_SYMBOL(zxdh_bar_chan_async_msg_send);
+
+uint16_t __bar_chan_save_recv_info(struct zxdh_msg_recviver_mem *result,
+								   uint16_t *msg_id)
+{
+	int ret = 0;
+	struct msgid_reps_info *reps_info = NULL;
+
+	ret = __bar_chan_msgid_allocate(msg_id);
+	if (ret == -1) {
+		return BAR_MSG_ERR_MSGID;
+	}
+	reps_info = &g_msgid_ring.reps_info_tbl[*msg_id];
+	reps_info->reps_buffer = result->recv_buffer;
+	reps_info->buffer_len = result->buffer_len;
+
+	return BAR_MSG_OK;
+}
+
+struct bar_async_node *__bar_chan_async_node_create(uint16_t msg_id,
+													struct zxdh_pci_bar_msg *in)
+{
+	struct bar_async_node *node = NULL;
+	uint8_t *payload_addr = NULL;
+	uint64_t subchan_addr = 0;
+
+	node = (struct bar_async_node *)kmalloc(sizeof(*node), GFP_KERNEL);
+	if (!node) {
+		BAR_LOG_ERR("ERR: mallocation for node failed\n");
+		return NULL;
+	}
+	node->msg_id = msg_id;
+	payload_addr = (uint8_t *)kmalloc(in->payload_len, GFP_KERNEL);
+	if (!payload_addr) {
+		kfree(node);
+		BAR_LOG_ERR("ERR: malloc for payload failed\n");
+		return NULL;
+	}
+
+	__bar_chan_subchan_addr_get(in, &subchan_addr);
+
+	memcpy(payload_addr, in->payload_addr, in->payload_len);
+	node->payload_addr = payload_addr;
+	node->payload_len = in->payload_len;
+	node->subchan_addr = subchan_addr;
+	node->event_id = in->event_id;
+	node->msg_id = msg_id;
+	node->dst_pcieid = in->dst_pcieid;
+	node->src_pcieid = in->src_pcieid;
+	node->emec = in->emec;
+	node->ack = BAR_CHAN_MSG_NO_ACK;
+	node->next = NULL;
+	node->src = in->src;
+	node->dst = in->dst;
+
+	return node;
+}
+
+/* 送入node, 插入到head, tail指向的队列中*/
+void async_list_tail_insert(struct bar_async_node **head,
+							struct bar_async_node *node,
+							struct bar_async_node **tail)
+{
+	if (*tail == NULL) {
+		*head = node;
+	} else {
+		(*tail)->next = node;
+	}
+	*tail = node;
+	(*tail)->next = NULL;
+	return;
+}
+
+uint16_t __bar_chan_async_node_add(struct bar_async_node *node)
+{
+	if (node == NULL) {
+		return BAR_MSG_ERR_NULL;
+	}
+	mutex_lock(&async_en.async_qlock);
+	if (node->emec == BAR_CHAN_MSG_EMEC) {
+		async_list_tail_insert(&async_en.emq_head, node, &async_en.emq_tail);
+	} else {
+		async_list_tail_insert(&async_en.noemq_head, node,
+							   &async_en.noemq_tail);
+	}
+	mutex_unlock(&async_en.async_qlock);
+	return 0;
+}
+
+uint16_t async_list_head_del(struct bar_async_node **head,
+							 struct bar_async_node *node,
+							 struct bar_async_node **tail)
+{
+	struct bar_async_node *temp_node = NULL;
+	if (node == NULL || *head == NULL || *head != node) {
+		return 0xaa;
+	}
+
+	temp_node = *head;
+	*head = (*head)->next;
+
+	if (*head == NULL) {
+		*tail = NULL;
+	}
+	if (temp_node->payload_addr != NULL) {
+		kfree(temp_node->payload_addr);
+		temp_node->payload_addr = NULL;
+	}
+	kfree(temp_node);
+	temp_node = NULL;
+	return 0;
+}
+
+/* 删除节点函数*/
+uint16_t __bar_chan_async_node_del(struct bar_async_node *node)
+{
+	uint16_t ret = 0;
+
+	if (node->emec == BAR_CHAN_MSG_EMEC) {
+		ret = async_list_head_del(&async_en.emq_head, node, &async_en.emq_tail);
+	} else {
+		ret = async_list_head_del(&async_en.noemq_head, node,
+								  &async_en.noemq_tail);
+	}
+
+	return ret;
 }
-EXPORT_SYMBOL(zxdh_bar_chan_sync_msg_send);
 
-static int bar_chan_callback_register_check(uint8_t event_id, zxdh_bar_chan_msg_recv_callback callback)
+/* 消息队列消费者*/
+void __bar_msg_async_list_admin(void)
 {
-    if (event_id >= (uint8_t)MSG_MODULE_NUM)
-    {
-        BAR_LOG_ERR("register ERR: invalid event_id: %d.\n", event_id);
-        return BAR_MSG_ERR_MODULE;
-    }
-    if (callback == NULL)
-    {
-        BAR_LOG_ERR("register ERR: null callback.\n");
-        return BAR_MEG_ERR_NULL_FUNC;
-    }
-    if (msg_recv_func_tbl[event_id] != NULL)
-    {
-        BAR_LOG_ERR("register ERR: repeat register.\n");
-        return BAR_MSG_ERR_REPEAT_REGISTER;
-    }
-    return BAR_MSG_OK;
+	while (1) {
+		if (kthread_should_stop()) {
+			break;
+		}
+		if (NULL != async_en.emq_head) {
+			__bar_msg_async_list_parse(async_en.emq_head);
+		} else if (NULL != async_en.noemq_head) {
+			__bar_msg_async_list_parse(async_en.noemq_head);
+		} else {
+			msleep(1);
+		}
+	}
+	return;
+}
+
+/* 送入两个队列的头指针进行消费*/
+uint16_t __bar_msg_async_list_parse(struct bar_async_node *node)
+{
+	struct bar_msg_header msg_header;
+	uint16_t time_out_cnt = 0, valid = 0;
+	struct msgid_reps_info *reps_info =
+			&g_msgid_ring.reps_info_tbl[node->msg_id];
+
+	/* 填充消息头*/
+	memset(&msg_header, 0, sizeof(msg_header));
+	msg_header.sync = BAR_CHAN_MSG_ASYNC;
+	msg_header.event_id = node->event_id;
+	msg_header.len = node->payload_len;
+	msg_header.src_pcieid = node->src_pcieid; // pf跟vf通信需要
+	msg_header.dst_pcieid = node->dst_pcieid; // pf跟vf通信需要
+	msg_header.msg_id = node->msg_id;
+	msg_header.ack = node->ack;
+
+	/* TODO:给通道上锁*/
+	bar_chan_lock(node->src, node->dst, node->src_pcieid);
+
+	/* 设置消息头和消息体， 将消息头、消息体填充, valid置位封装成一步*/
+	__bar_chan_msg_send(node->subchan_addr, node->payload_addr,
+						node->payload_len, &msg_header);
+
+	if (node->ack == BAR_CHAN_MSG_NO_ACK) {
+		mod_timer(&reps_info->id_timer, BAR_MSGID_FREE_THRESHOLD);
+	}
+
+	do {
+		usleep_range(BAR_MSG_POLLING_SPAN_US, BAR_MSG_POLLING_SPAN_US + 10);
+		valid = __bar_msg_valid_stat_get(node->subchan_addr);
+		time_out_cnt++;
+	} while ((time_out_cnt < BAR_MSG_TIMEOUT_TH) &&
+			 (BAR_MSG_CHAN_USED == valid));
+
+	/* 如果超时恢复标志位*/
+	if ((BAR_MSG_TIMEOUT_TH == time_out_cnt) &&
+		(BAR_MSG_CHAN_USABLE != valid)) {
+		__bar_chan_msg_valid_set(node->subchan_addr, BAR_MSG_CHAN_USABLE);
+		__bar_chan_msg_poltag_set(node->subchan_addr, 0);
+		BAR_LOG_ERR("BAR MSG ERR: chan reply time out.\n");
+	}
+
+	bar_chan_unlock(node->src, node->dst, node->src_pcieid);
+	__bar_chan_async_node_del(node);
+
+	return 0;
 }
 
 /**
@@ -774,22 +1011,41 @@ static int bar_chan_callback_register_check(uint8_t event_id, zxdh_bar_chan_msg_
  * @return: 0 成功，其他失败
  * 一般在驱动初始化时调用
  */
-int zxdh_bar_chan_msg_recv_register(uint8_t event_id, zxdh_bar_chan_msg_recv_callback callback)
+int zxdh_bar_chan_msg_recv_register(uint8_t event_id,
+									zxdh_bar_chan_msg_recv_callback callback)
 {
-    int ret = 0;
+	uint16_t ret = 0;
 
-    ret = bar_chan_callback_register_check(event_id, callback);
+	ret = __bar_chan_callback_register_check(event_id, callback);
 
-    if (BAR_MSG_OK == ret)
-    {
-        msg_recv_func_tbl[event_id] = callback;
-        BAR_LOG_DEBUG("register module: %d success.\n", event_id);
-    }
+	if (BAR_MSG_OK == ret) {
+		msg_recv_func_tbl[event_id] = callback;
+		BAR_LOG_DEBUG("register module: %d success.\n", event_id);
+	}
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(zxdh_bar_chan_msg_recv_register);
 
+uint16_t
+__bar_chan_callback_register_check(uint8_t event_id,
+								   zxdh_bar_chan_msg_recv_callback callback)
+{
+	if (event_id >= (uint8_t)MSG_MODULE_NUM) {
+		BAR_LOG_ERR("register ERR: invalid event_id: %d.\n", event_id);
+		return BAR_MSG_ERR_MODULE;
+	}
+	if (callback == NULL) {
+		BAR_LOG_ERR("register ERR: null callback.\n");
+		return BAR_MEG_ERR_NULL_FUNC;
+	}
+	if (msg_recv_func_tbl[event_id] != NULL) {
+		BAR_LOG_ERR("register ERR: repeat register.\n");
+		return BAR_MSG_ERR_REPEAT_REGISTER;
+	}
+	return BAR_MSG_OK;
+}
+
 /**
  * zxdh_bar_chan_msg_recv_unregister - PCIE BAR空间消息方式，解注册消息接收回调
  * @event_id: 内核PCIE设备地址
@@ -798,157 +1054,178 @@ EXPORT_SYMBOL(zxdh_bar_chan_msg_recv_register);
  */
 int zxdh_bar_chan_msg_recv_unregister(uint8_t event_id)
 {
-    if (event_id >= (uint8_t)MSG_MODULE_NUM)
-    {
-        BAR_LOG_ERR("unregister ERR: invalid event_id :%d.\n", event_id);
-        return BAR_MSG_ERR_MODULE;
-    }
-    if (msg_recv_func_tbl[event_id] == NULL)
-    {
-        BAR_LOG_ERR("unregister ERR: null proccess func.\n");
-        return BAR_MSG_ERR_UNGISTER;
-    }
-    msg_recv_func_tbl[event_id] = NULL;
-    BAR_LOG_DEBUG("unregister module %d success.\n", event_id);
-    return BAR_MSG_OK;
+	if (event_id >= (uint8_t)MSG_MODULE_NUM) {
+		BAR_LOG_ERR("unregister ERR: invalid event_id :%d.\n", event_id);
+		return BAR_MSG_ERR_MODULE;
+	}
+	if (msg_recv_func_tbl[event_id] == NULL) {
+		BAR_LOG_ERR("unregister ERR: null proccess func.\n");
+		return BAR_MSG_ERR_UNGISTER;
+	}
+	msg_recv_func_tbl[event_id] = NULL;
+	BAR_LOG_DEBUG("unregister module %d success.\n", event_id);
+	return BAR_MSG_OK;
 }
 EXPORT_SYMBOL(zxdh_bar_chan_msg_recv_unregister);
 
 int bar_mpf_addr_ioremap(void)
 {
-    uint64_t addr;
-    uint64_t len;
-    struct pci_dev *pdev = NULL;
-
-    pdev = pci_get_device(MPF_VENDOR_ID, MPF_DEVICE_ID, NULL);
-
-    if (pdev == NULL)
-    {
-        BAR_LOG_DEBUG("not found device: deviceID %x, VendorID: %x", MPF_DEVICE_ID, MPF_VENDOR_ID);
-        return -EINVAL;
-    }
-
-    addr = pci_resource_start(pdev, 0);
-    len = pci_resource_len(pdev, 0);
-    if (addr == 0 || len == 0)
-    {
-        BAR_LOG_ERR("pci resouce addr or len is 0\n");
-        return -EINVAL;
-    }
-
-    internal_addr = ioremap(addr, len);
-    if (IS_ERR_OR_NULL(internal_addr))
-    {
-        BAR_LOG_ERR("ioremap failed, internal_addr=0x%p\n", internal_addr);
-        return -ENOMEM;
-    }
-    is_mpf_scaned = TRUE;
-
-    return BAR_MSG_OK;
+	uint64_t addr;
+	uint64_t len;
+	struct pci_dev *pdev = NULL;
+
+	pdev = pci_get_device(MPF_VENDOR_ID, MPF_DEVICE_ID, NULL);
+
+	if (pdev == NULL) {
+		BAR_LOG_DEBUG("not found device: deviceID %x, VendorID: %x",
+					  MPF_DEVICE_ID, MPF_VENDOR_ID);
+		return -EINVAL;
+	}
+
+	addr = pci_resource_start(pdev, 0);
+	len = pci_resource_len(pdev, 0);
+	if (addr == 0 || len == 0) {
+		BAR_LOG_ERR("pci resouce addr or len is 0\n");
+		return -EINVAL;
+	}
+
+	internal_addr = ioremap(addr, len);
+	if (IS_ERR_OR_NULL(internal_addr)) {
+		BAR_LOG_ERR("ioremap failed, internal_addr=0x%p\n", internal_addr);
+		return -ENOMEM;
+	}
+	is_mpf_scaned = TRUE;
+
+	return BAR_MSG_OK;
 }
 
 void bar_mpf_addr_iounmap(void)
 {
-    if (internal_addr != NULL)
-    {
-        iounmap(internal_addr);
-    }
-    internal_addr = NULL;
-    is_mpf_scaned = FALSE;
-    return;
+	if (internal_addr != NULL) {
+		iounmap(internal_addr);
+	}
+	internal_addr = NULL;
+	is_mpf_scaned = FALSE;
+	return;
 }
 
 int bar_msgid_ring_init(void)
 {
-    uint16_t msg_id = 0;
-    struct msgid_reps_info *reps_info = NULL;
-
-    spin_lock_init(&g_msgid_ring.lock);
-    for( msg_id = 0; msg_id < MAX_MSG_BUFF_NUM; msg_id++)
-    {
-        reps_info = &(g_msgid_ring.reps_info_tbl[msg_id]);
-        reps_info->id = msg_id;
-        reps_info->flag = REPS_INFO_FLAG_USABLE;
-    }
-    return BAR_MSG_OK;
+	uint16_t msg_id = 0;
+	struct msgid_reps_info *reps_info = NULL;
+
+	spin_lock_init(&g_msgid_ring.lock);
+	for (msg_id = 0; msg_id < MAX_MSG_BUFF_NUM; msg_id++) {
+		reps_info = &(g_msgid_ring.reps_info_tbl[msg_id]);
+		timer_setup(&reps_info->id_timer, bar_chan_timer_callback, 0);
+		reps_info->id = msg_id;
+		reps_info->flag = REPS_INFO_FLAG_USABLE;
+	}
+	return BAR_MSG_OK;
 }
 
 void bar_msgid_ring_free(void)
 {
-    uint16_t msg_id = 0;
-    struct msgid_reps_info *reps_info = NULL;
-
-    for (msg_id = 0; msg_id < MAX_MSG_BUFF_NUM; msg_id++)
-    {
-        reps_info = &g_msgid_ring.reps_info_tbl[msg_id];
-        del_timer_sync(&reps_info->id_timer);
-    }
+	uint16_t msg_id = 0;
+	struct msgid_reps_info *reps_info = NULL;
+
+	for (msg_id = 0; msg_id < MAX_MSG_BUFF_NUM; msg_id++) {
+		reps_info = &g_msgid_ring.reps_info_tbl[msg_id];
+		del_timer_sync(&reps_info->id_timer);
+	}
+}
+
+void bar_async_queue_free(void)
+{
+	uint16_t ret = 0;
+
+	while (NULL != async_en.noemq_head) {
+		ret = __bar_chan_async_node_del(async_en.noemq_head);
+		if (ret != BAR_MSG_OK) {
+			break;
+		}
+	}
+	while (NULL != async_en.emq_head) {
+		ret = __bar_chan_async_node_del(async_en.emq_head);
+		if (ret != BAR_MSG_OK) {
+			break;
+		}
+	}
 }
 
 extern uint16_t test_sync_send(void);
 int zxdh_bar_msg_chan_init(void)
 {
-    int16_t ret = 0;
-
-    /* msg_id锁初始化*/
-    bar_init_lock_arr();
-    bar_msgid_ring_init();
-
-    /* 管理pf地址映射*/
-    ret = bar_mpf_addr_ioremap();
-    if (ret != BAR_MSG_OK)
-    {
-        BAR_LOG_DEBUG("mpf do not exit, but do not impact the msg chan.\n");
-    }
+	int16_t ret = 0;
+
+	/* 异步消息处理线程*/
+	async_en.async_proc = kthread_run((void *)&__bar_msg_async_list_admin, NULL,
+									  "msg-pro-thread");
+	if (async_en.async_proc == NULL) {
+		BAR_LOG_ERR("async-msg_proc pthread: msg process create failed.\n");
+		return BAR_MSG_ERR_NULL;
+	}
+
+	/* msg_id锁初始化*/
+	bar_init_lock_arr();
+	bar_msgid_ring_init();
+
+	/* 管理pf地址映射*/
+	ret = bar_mpf_addr_ioremap();
+	if (ret != BAR_MSG_OK) {
+		BAR_LOG_DEBUG("mpf do not exit, but do not impact the msg chan.\n");
+	}
 
 #ifdef BAR_MSG_TEST
-    test_sync_send();
+	test_sync_send();
 #endif
 
-    return BAR_MSG_OK;
+	return BAR_MSG_OK;
 }
 
 void bar_chan_timer_callback(struct timer_list *timer)
 {
-    struct msgid_reps_info *reps_info = NULL;
-
-    reps_info = container_of(timer, struct msgid_reps_info, id_timer);
-    if (reps_info->flag == REPS_INFO_FLAG_USED)
-    {
-        reps_info->reps_buffer = NULL;
-        reps_info->buffer_len = 0;
-        reps_info->flag = REPS_INFO_FLAG_USABLE;
-        BAR_LOG_ERR("RECV ERR: get async reply time out, free msg_id: %u.\n", reps_info->id);
-    }
-    else
-    {
-        BAR_LOG_DEBUG("RECV NOTICE: get async reply message success.\n");
-    }
-    return;
+	struct msgid_reps_info *reps_info = NULL;
+
+	reps_info = container_of(timer, struct msgid_reps_info, id_timer);
+	if (reps_info->flag == REPS_INFO_FLAG_USED) {
+		reps_info->reps_buffer = NULL;
+		reps_info->buffer_len = 0;
+		reps_info->flag = REPS_INFO_FLAG_USABLE;
+		BAR_LOG_ERR("RECV ERR: get async reply time out, free msg_id: %d.\n",
+					reps_info->id);
+	} else {
+		BAR_LOG_DEBUG("RECV NOTICE: get async reply message success.\n");
+	}
+	return;
 }
 
 int zxdh_bar_msg_chan_remove(void)
 {
-
-    bar_msgid_ring_free();
-    /* mpf解ioremap*/
-    bar_mpf_addr_iounmap();
-    /* 消息链表资源释放*/
-
-    BAR_LOG_DEBUG("zxdh_msg_chan_bar remove success");
-
-    return 0;
+	/* 异步消息处理线程退出*/
+	if (async_en.async_proc != NULL) {
+		kthread_stop(async_en.async_proc);
+		async_en.async_proc = NULL;
+	}
+	bar_msgid_ring_free();
+	/* mpf解ioremap*/
+	bar_mpf_addr_iounmap();
+	/* 消息链表资源释放*/
+	bar_async_queue_free();
+
+	BAR_LOG_DEBUG("zxdh_msg_chan_bar remove success");
+
+	return 0;
 }
 
 uint16_t bar_get_sum(uint8_t *ptr, uint8_t len)
 {
-    int idx = 0;
-    uint64_t sum = 0;
-    for (idx = 0; idx < len; idx++)
-    {
-        sum += *(ptr + idx);
-    }
-    return (uint16_t)sum;
+	int idx = 0;
+	uint64_t sum = 0;
+	for (idx = 0; idx < len; idx++) {
+		sum += *(ptr + idx);
+	}
+	return (uint16_t)sum;
 }
 
 /**
@@ -959,250 +1236,212 @@ uint16_t bar_get_sum(uint8_t *ptr, uint8_t len)
  */
 int zxdh_bar_enable_chan(struct msix_para *_msix_para, uint16_t *vport)
 {
-    int ret = 0;
-    uint8_t recv_buf[12] = {0};
-    uint16_t check_token, sum_res;
-#if 0
-    uint32_t domain, bus, devid, function;
-#endif
-    struct msix_msg msix_msg = {0};
-    struct zxdh_pci_bar_msg in = {0};
-    struct zxdh_msg_recviver_mem result = {0};
-
-    if (!_msix_para || !_msix_para->pdev)
-    {
-        return -BAR_MSG_ERR_NULL;
-    }
-#if 0
-    sscanf(pci_name(_msix_para->pdev), "%x:%x:%x.%u", &domain, &bus, &devid, &function);
-    msix_msg.bdf = BDF_ECAM(bus, devid, function);
-#endif
-    msix_msg.pcie_id = _msix_para->pcie_id;
-    msix_msg.vector_risc = _msix_para->vector_risc;
-    msix_msg.vector_pfvf = _msix_para->vector_pfvf;
-    msix_msg.vector_mpf = _msix_para->vector_mpf;
-
-    in.payload_addr = &msix_msg;
-    in.payload_len = sizeof(msix_msg);
-    in.virt_addr = _msix_para->virt_addr;
-    in.src = _msix_para->driver_type;
-    in.dst = MSG_CHAN_END_RISC;
-    in.event_id = MODULE_MSIX;
-    in.src_pcieid = _msix_para->pcie_id;
-
-    result.recv_buffer = recv_buf;
-    result.buffer_len = sizeof(recv_buf);
-
-    ret = zxdh_bar_chan_sync_msg_send(&in, &result);
-    if (ret != BAR_MSG_OK)
-    {
-        return -ret;
-    }
-
-    check_token = *(uint16_t *)(recv_buf + 6);
-    sum_res = bar_get_sum((uint8_t *)&msix_msg, sizeof(msix_msg));
-    if (check_token != sum_res)
-    {
-        BAR_LOG_DEBUG("expect token: 0x%x, get token: 0x%x.\n", sum_res, check_token);
-        return -BAR_MSG_ERR_NOT_MATCH;
-    }
-    *vport = *(uint16_t *)(recv_buf + 8);
-    BAR_LOG_DEBUG("vport of %s get success.\n", pci_name(_msix_para->pdev));
-    return BAR_MSG_OK;
+	int ret = 0;
+	uint8_t recv_buf[12] = { 0 };
+	uint16_t check_token, sum_res;
+	struct msix_msg msix_msg = { 0 };
+	struct zxdh_pci_bar_msg in = { 0 };
+	struct zxdh_msg_recviver_mem result = { 0 };
+
+	if (!_msix_para || !_msix_para->pdev) {
+		return -BAR_MSG_ERR_NULL;
+	}
+	msix_msg.pcie_id = _msix_para->pcie_id;
+	msix_msg.vector_risc = _msix_para->vector_risc;
+	msix_msg.vector_pfvf = _msix_para->vector_pfvf;
+	msix_msg.vector_mpf = _msix_para->vector_mpf;
+
+	in.payload_addr = &msix_msg;
+	in.payload_len = sizeof(msix_msg);
+	in.virt_addr = _msix_para->virt_addr;
+	in.src = _msix_para->driver_type;
+	in.dst = MSG_CHAN_END_RISC;
+	in.event_id = MODULE_MSIX;
+	in.src_pcieid = _msix_para->pcie_id;
+
+	result.recv_buffer = recv_buf;
+	result.buffer_len = sizeof(recv_buf);
+
+	ret = zxdh_bar_chan_sync_msg_send(&in, &result);
+	if (ret != BAR_MSG_OK) {
+		return -ret;
+	}
+
+	check_token = *(uint16_t *)(recv_buf + 6);
+	sum_res = bar_get_sum((uint8_t *)&msix_msg, sizeof(msix_msg));
+	if (check_token != sum_res) {
+		BAR_LOG_DEBUG("expect token: 0x%x, get token: 0x%x.\n", sum_res,
+					  check_token);
+		return -BAR_MSG_ERR_NOT_MATCH;
+	}
+	*vport = *(uint16_t *)(recv_buf + 8);
+	BAR_LOG_DEBUG("vport of %s get success.\n", pci_name(_msix_para->pdev));
+	return BAR_MSG_OK;
 }
 EXPORT_SYMBOL(zxdh_bar_enable_chan);
 
-int zxdh_get_bar_offset(struct bar_offset_params *paras, struct bar_offset_res *res)
+int zxdh_get_bar_offset(struct bar_offset_params *paras,
+						struct bar_offset_res *res)
 {
-    int ret = 0;
-    uint16_t check_token, sum_res;
-    struct offset_get_msg send_msg = {0};
-    struct bar_recv_msg *recv_msg = NULL;
-
-    struct zxdh_pci_bar_msg in = {0};
-    struct zxdh_msg_recviver_mem result = {0};
-
-    if (!paras || !res)
-    {
-        return BAR_MSG_ERR_NULL;
-    }
-
-    send_msg.pcie_id = paras->pcie_id;
-    send_msg.type = paras->type;
-
-    in.payload_addr = &send_msg;
-    in.payload_len = sizeof(send_msg);
-    in.virt_addr = paras->virt_addr;
-    in.src = MSG_CHAN_END_PF;
-    in.dst = MSG_CHAN_END_RISC;
-    in.event_id = MODULE_OFFSET_GET;
-
-    recv_msg = kzalloc(sizeof(struct bar_recv_msg), GFP_KERNEL);
-    if (recv_msg == NULL)
-    {
-        LOG_ERR("NULL ptr\n");
-        return -1;
-    }
-    result.recv_buffer = recv_msg;
-    result.buffer_len = sizeof(struct bar_recv_msg);
-
-    ret = zxdh_bar_chan_sync_msg_send(&in, &result);
-    if (ret != BAR_MSG_OK)
-    {
-        ret = -ret;
-        goto free_msg;
-    }
-
-    check_token = recv_msg->offset_reps.check;
-    sum_res = bar_get_sum((uint8_t*)&send_msg, sizeof(send_msg));
-    if (check_token != sum_res)
-    {
-        BAR_LOG_ERR("expect token: 0x%x, get token: 0x%x.\n", sum_res, check_token);
-        ret = -BAR_MSG_ERR_NOT_MATCH;
-        goto free_msg;
-    }
-    res->bar_offset = recv_msg->offset_reps.offset;
-    res->bar_length = recv_msg->offset_reps.length;
-
-free_msg:
-    kfree(recv_msg);
-    return ret;
+	int ret = 0;
+	uint16_t check_token, sum_res;
+	struct offset_get_msg send_msg = { 0 };
+	struct bar_recv_msg recv_msg = { 0 };
+
+	struct zxdh_pci_bar_msg in = { 0 };
+	struct zxdh_msg_recviver_mem result = { 0 };
+
+	if (!paras || !res) {
+		return BAR_MSG_ERR_NULL;
+	}
+
+	send_msg.pcie_id = paras->pcie_id;
+	send_msg.type = paras->type;
+
+	in.payload_addr = &send_msg;
+	in.payload_len = sizeof(send_msg);
+	in.virt_addr = paras->virt_addr;
+	in.src = MSG_CHAN_END_PF;
+	in.dst = MSG_CHAN_END_RISC;
+	in.event_id = MODULE_OFFSET_GET;
+
+	result.recv_buffer = &recv_msg;
+	result.buffer_len = sizeof(recv_msg);
+
+	ret = zxdh_bar_chan_sync_msg_send(&in, &result);
+	if (ret != BAR_MSG_OK) {
+		return -ret;
+	}
+
+	check_token = recv_msg.offset_reps.check;
+	sum_res = bar_get_sum((uint8_t *)&send_msg, sizeof(send_msg));
+	if (check_token != sum_res) {
+		BAR_LOG_ERR("expect token: 0x%x, get token: 0x%x.\n", sum_res,
+					check_token);
+		return BAR_MSG_ERR_NOT_MATCH;
+	}
+	res->bar_offset = recv_msg.offset_reps.offset;
+	res->bar_length = recv_msg.offset_reps.length;
+	return BAR_MSG_OK;
 }
 EXPORT_SYMBOL(zxdh_get_bar_offset);
 
 void zxdh_bar_reset_valid(uint64_t subchan_addr)
 {
-    struct bar_msg_header msg_header = {0};
+	struct bar_msg_header msg_header = { 0 };
 
-    bar_chan_msg_header_get(subchan_addr, &msg_header);
+	__bar_chan_msg_header_get(subchan_addr, &msg_header);
 
-    subchan_addr += BAR_MSG_ADDR_CHAN_INTERVAL;
-    bar_chan_msg_valid_set(subchan_addr, BAR_MSG_CHAN_USABLE);
-    bar_chan_msg_poltag_set(subchan_addr, 0);
+	subchan_addr += BAR_MSG_ADDR_CHAN_INTERVAL;
+	__bar_chan_msg_valid_set(subchan_addr, BAR_MSG_CHAN_USABLE);
+	__bar_chan_msg_poltag_set(subchan_addr, 0);
 }
 EXPORT_SYMBOL(zxdh_bar_reset_valid);
 
-uint16_t zxdh_get_event_id(uint64_t subchan_addr, uint8_t src_type, uint8_t dst_type)
+uint16_t zxdh_get_event_id(uint64_t subchan_addr, uint8_t src_type,
+						   uint8_t dst_type)
 {
-    uint8_t subchan_id = 0;
-    struct bar_msg_header msg_header = {0};
-    uint8_t src = bar_msg_col_index_trans(src_type);
-    uint8_t dst = bar_msg_row_index_trans(dst_type);
-
-    if (src == BAR_MSG_SRC_ERR || dst == BAR_MSG_DST_ERR)
-    {
-        return 0;
-    }
-    /* 接收子通道id和发送子通道相反*/
-    subchan_id = (!!subchan_id_tbl[dst][src])? BAR_SUBCHAN_INDEX_SEND : BAR_SUBCHAN_INDEX_RECV;
-    subchan_addr += subchan_id * BAR_MSG_ADDR_CHAN_INTERVAL;
-    bar_chan_msg_header_get(subchan_addr, &msg_header);
-    return msg_header.event_id;
+	uint8_t subchan_id = 0;
+	struct bar_msg_header msg_header = { 0 };
+	uint8_t src = __bar_msg_col_index_trans(src_type);
+	uint8_t dst = __bar_msg_row_index_trans(dst_type);
+
+	if (src == BAR_MSG_SRC_ERR || dst == BAR_MSG_DST_ERR) {
+		return 0;
+	}
+	/* 接收子通道id和发送子通道相反*/
+	subchan_id = (!!subchan_id_tbl[dst][src]) ? BAR_SUBCHAN_INDEX_SEND :
+												  BAR_SUBCHAN_INDEX_RECV;
+	subchan_addr += subchan_id * BAR_MSG_ADDR_CHAN_INTERVAL;
+	__bar_chan_msg_header_get(subchan_addr, &msg_header);
+	return msg_header.event_id;
 }
 EXPORT_SYMBOL(zxdh_get_event_id);
 
-int32_t zxdh_send_command(uint64_t vaddr, uint16_t pcie_id, uint16_t module_id, \
-                            void *msg, void *ack, bool is_sync_msg)
+int32_t zxdh_send_command(uint64_t vaddr, uint16_t pcie_id, uint16_t module_id,
+						  void *msg, void *ack, bool is_sync_msg)
 {
-    struct zxdh_pci_bar_msg in = {0};
-    struct zxdh_msg_recviver_mem result = {0};
-    struct bar_recv_msg *bar_reps = NULL;
-    int32_t ret = 0;
-
-    if ((msg == NULL) || (ack == NULL))
-    {
-        LOG_ERR("NULL ptr\n");
-        return -1;
-    }
-
-    in.payload_addr = msg;
-    in.payload_len = sizeof(union zxdh_msg);
-
-    if (((pcie_id >> PFVF_FLAG_OFFSET) & 1) == 1)
-    {
-        in.src = MSG_CHAN_END_PF;
-    }
-    else
-    {
-        in.src = MSG_CHAN_END_VF;
-    }
-
-    bar_reps = kzalloc(sizeof(struct bar_recv_msg), GFP_KERNEL);
-    if (bar_reps == NULL)
-    {
-        LOG_ERR("NULL ptr\n");
-        return -1;
-    }
-    in.dst = MSG_CHAN_END_RISC;
-    in.event_id = module_id;
-    in.virt_addr = vaddr;
-    in.src_pcieid = pcie_id;
-    result.recv_buffer = bar_reps;
-    result.buffer_len = BAR_MSG_PAYLOAD_MAX_LEN;
-
-    switch (module_id)
-    {
-        case MODULE_VF_BAR_MSG_TO_PF:
-        {
-            in.dst = MSG_CHAN_END_PF;
-            in.dst_pcieid = FIND_PF_PCIE_ID(pcie_id);
-            in.virt_addr += ZXDH_BAR_PFVF_MSG_OFFSET;
-            break;
-        }
-        case MODULE_PF_BAR_MSG_TO_VF:
-        {
-            in.dst = MSG_CHAN_END_VF;
-            in.dst_pcieid = ((zxdh_msg_info *)msg)->hdr_vf.dst_pcie_id;
-            in.virt_addr += ZXDH_BAR_PFVF_MSG_OFFSET;
-            break;
-        }
-        case MODULE_TBL:
-        {
-            in.payload_len = MSG_STRUCT_HD_LEN + ((zxdh_msg_info *)msg)->hdr_to_cmn.write_bytes;
-            break;
-        }
-        case MODULE_PF_TIMER_TO_RISC_MSG:
-        {
-            in.payload_len = MSG_STRUCT_HD_LEN + ((zxdh_msg_info *)msg)->hdr_to_cmn.write_bytes;
-            break;
-        }
-        case MODULE_PHYPORT_QUERY:
-        {
-            in.payload_len = sizeof(struct zxdh_port_msg);
-            break;
-        }
-        case MODULE_NPSDK:
-        {
-            in.payload_len = sizeof(zxdh_cfg_np_msg);
-            break;
-        }
-    }
-
-    ret = zxdh_bar_chan_sync_msg_send(&in, &result);
-    if (ret != ZXDH_NET_ACK_OK)
-    {
-        LOG_ERR("zxdh_bar_chan_sync_msg_send failed: %d\n", ret);
-        ret = -ret;
-        goto free_reps;
-    }
-
-    if (is_sync_msg && bar_reps->replied != BAR_MSG_REPS_OK)
-    {
-        LOG_ERR("reps get failed\n");
-        ret = -1;
-        goto free_reps;
-    }
-
-    if (bar_reps->reps_len > BAR_MSG_PAYLOAD_MAX_LEN)
-    {
-        LOG_ERR("reps len too long\n");
-        ret = -1;
-        goto free_reps;
-    }
-    memcpy(ack, bar_reps->data, bar_reps->reps_len);
-
-free_reps:
-    kfree(bar_reps);
-    return ret;
+	struct zxdh_pci_bar_msg in = { 0 };
+	struct zxdh_msg_recviver_mem result = { 0 };
+	struct bar_recv_msg bar_reps = { 0 };
+	int32_t ret = 0;
+
+	if ((msg == NULL) || (ack == NULL)) {
+		LOG_ERR("NULL ptr\n");
+		return -1;
+	}
+
+	in.payload_addr = msg;
+	in.payload_len = sizeof(zxdh_msg_info);
+
+	if (((pcie_id >> PFVF_FLAG_OFFSET) & 1) == 1) {
+		in.src = MSG_CHAN_END_PF;
+	} else {
+		in.src = MSG_CHAN_END_VF;
+	}
+
+	in.dst = MSG_CHAN_END_RISC;
+	in.event_id = module_id;
+	in.virt_addr = vaddr;
+	in.src_pcieid = pcie_id;
+	result.recv_buffer = &bar_reps;
+	result.buffer_len = ZXDH_NET_MAX_ACK_LEN;
+
+	switch (module_id) {
+	case MODULE_VF_BAR_MSG_TO_PF: {
+		in.dst = MSG_CHAN_END_PF;
+		in.dst_pcieid = FIND_PF_PCIE_ID(pcie_id);
+		in.virt_addr += ZXDH_BAR_PFVF_MSG_OFFSET;
+		break;
+	}
+	case MODULE_PF_BAR_MSG_TO_VF: {
+		in.dst = MSG_CHAN_END_VF;
+		in.dst_pcieid = ((zxdh_msg_info *)msg)->hdr_vf.dst_pcie_id;
+		in.virt_addr += ZXDH_BAR_PFVF_MSG_OFFSET;
+		break;
+	}
+	case MODULE_TBL: {
+		in.payload_len = MSG_STRUCT_HD_LEN +
+						 ((zxdh_msg_info *)msg)->hdr_to_cmn.write_bytes;
+		break;
+	}
+	case MODULE_PF_TIMER_TO_RISC_MSG: {
+		in.payload_len = MSG_STRUCT_HD_LEN +
+						 ((zxdh_msg_info *)msg)->hdr_to_cmn.write_bytes;
+		break;
+	}
+	case MODULE_PHYPORT_QUERY: {
+		in.payload_len = sizeof(struct zxdh_port_msg);
+		break;
+	}
+	case MODULE_NPSDK: {
+		in.payload_len = sizeof(zxdh_cfg_np_msg);
+		break;
+	}
+	}
+
+	if (is_sync_msg) {
+		ret = zxdh_bar_chan_sync_msg_send(&in, &result);
+	} else {
+		ret = zxdh_bar_chan_async_msg_send(&in, &result);
+	}
+
+	if (ret != ZXDH_NET_ACK_OK) {
+		LOG_ERR("zxdh_bar_chan_sync_msg_send failed: %d\n", ret);
+		return -ret;
+	}
+
+	if (is_sync_msg && bar_reps.replied != BAR_MSG_REPS_OK) {
+		LOG_ERR("reps get failed\n");
+		return -1;
+	}
+
+	if (bar_reps.reps_len > ZXDH_NET_MAX_ACK_LEN) {
+		LOG_ERR("reps len too long\n");
+		return -1;
+	}
+	memcpy(ack, bar_reps.data, bar_reps.reps_len);
+
+	return ret;
 }
 EXPORT_SYMBOL(zxdh_send_command);
diff --git a/src/net/drivers/net/ethernet/dinghai/dh_procfs.c b/src/net/drivers/net/ethernet/dinghai/dh_procfs.c
index bcd6fba1936ff0928a4d8b018d86fa9a2645c4f2..30abb921e0427515d23a76f666b538c559ae6fcd 100644
--- a/src/net/drivers/net/ethernet/dinghai/dh_procfs.c
+++ b/src/net/drivers/net/ethernet/dinghai/dh_procfs.c
@@ -4,82 +4,71 @@
 
 #define DRV_NAME "dinghai"
 
-static struct fs_entry_desc fs_entry_table[] = {
-    { FS_ENTRY_BOND, "lag" },
-    {0}
-};
+static struct fs_entry_desc fs_entry_table[] = { { FS_ENTRY_BOND, "lag" },
+												 { 0 } };
 
 uint32_t find_fs_entry(uint32_t type)
 {
-    uint32_t idx = 0;
+	uint32_t idx = 0;
 
-    while (fs_entry_table[idx].file_name)
-    {
-        if (type == fs_entry_table[idx].type)
-        {
-            break;
-        }
-        idx++;
-    }
+	while (fs_entry_table[idx].file_name) {
+		if (type == fs_entry_table[idx].type) {
+			break;
+		}
+		idx++;
+	}
 
-    return idx;
+	return idx;
 }
 
 void zxdh_create_proc_dir(struct zxdh_proc_fs *procfs)
 {
-    if (!procfs->proc_dir)
-    {
-        procfs->proc_dir = proc_mkdir(DRV_NAME, NULL);
-        if (!procfs->proc_dir)
-        {
-            pr_warn("Warning: Cannot create /proc/%s\n", DRV_NAME);
-        }
-    }
+	if (!procfs->proc_dir) {
+		procfs->proc_dir = proc_mkdir(DRV_NAME, NULL);
+		if (!procfs->proc_dir) {
+			pr_warn("Warning: Cannot create /proc/%s\n", DRV_NAME);
+		}
+	}
 }
 
 void zxdh_destroy_proc_dir(struct zxdh_proc_fs *procfs)
 {
-    if (procfs->proc_dir)
-    {
-        remove_proc_entry(DRV_NAME, NULL);
-        procfs->proc_dir = NULL;
-    }
+	if (procfs->proc_dir) {
+		remove_proc_entry(DRV_NAME, NULL);
+		procfs->proc_dir = NULL;
+	}
 }
 
-void zxdh_create_proc_entry(struct zxdh_proc_fs *procfs,
-        uint32_t type, struct seq_operations *seq_ops, void *data)
+void zxdh_create_proc_entry(struct zxdh_proc_fs *procfs, uint32_t type,
+							struct seq_operations *seq_ops, void *data)
 {
-    uint32_t idx = 0;
-    char *file_name = NULL;
+	uint32_t idx = 0;
+	char *file_name = NULL;
 
-    if (procfs->proc_dir)
-    {
-        idx = find_fs_entry(type);
-        file_name = fs_entry_table[idx].file_name;
-        if (file_name && (idx < PROC_ENTRY_MAX))
-        {
-            procfs->proc_entry[idx] = proc_create_seq_data(file_name, 0444, procfs->proc_dir, seq_ops, data);
-            if (procfs->proc_entry[idx] == NULL)
-            {
-                pr_info("Cannot create /proc/%s/%s\n", DRV_NAME, file_name);
-            }
-        }
-    }
+	if (procfs->proc_dir) {
+		idx = find_fs_entry(type);
+		file_name = fs_entry_table[idx].file_name;
+		if (file_name && (idx < PROC_ENTRY_MAX)) {
+			procfs->proc_entry[idx] = proc_create_seq_data(
+					file_name, 0444, procfs->proc_dir, seq_ops, data);
+			if (procfs->proc_entry[idx] == NULL) {
+				pr_info("Cannot create /proc/%s/%s\n", DRV_NAME, file_name);
+			}
+		}
+	}
 }
 
 void zxdh_remove_proc_entry(struct zxdh_proc_fs *procfs, uint32_t type)
 {
-    uint32_t idx = 0;
-    char *file_name = NULL;
+	uint32_t idx = 0;
+	char *file_name = NULL;
 
-    if (procfs->proc_dir)
-    {
-        idx = find_fs_entry(type);
-        file_name = fs_entry_table[idx].file_name;
-        if (file_name && (idx < PROC_ENTRY_MAX))
-        {
-            remove_proc_entry(file_name, procfs->proc_dir);
-            procfs->proc_entry[idx] = NULL;
-        }
-    }
+	if (procfs->proc_dir) {
+		idx = find_fs_entry(type);
+		file_name = fs_entry_table[idx].file_name;
+		if (file_name && (idx < PROC_ENTRY_MAX)) {
+			remove_proc_entry(file_name, procfs->proc_dir);
+			procfs->proc_entry[idx] = NULL;
+		}
+	}
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/dh_procfs.h b/src/net/drivers/net/ethernet/dinghai/dh_procfs.h
index 6197957474073ab17c0da41dffe9c2fd846c6157..fb7b5f09afc96c9bd1f06cf95dbd5bcf7da2de1f 100644
--- a/src/net/drivers/net/ethernet/dinghai/dh_procfs.h
+++ b/src/net/drivers/net/ethernet/dinghai/dh_procfs.h
@@ -1,30 +1,26 @@
 #ifndef _ZXDH_PROC_FS_H_
 #define _ZXDH_PROC_FS_H_
 
-#define PROC_ENTRY_MAX      (16)
+#define PROC_ENTRY_MAX (16)
 
-struct zxdh_proc_fs
-{
-    struct proc_dir_entry *proc_dir;
-    struct proc_dir_entry *proc_entry[PROC_ENTRY_MAX];
+struct zxdh_proc_fs {
+	struct proc_dir_entry *proc_dir;
+	struct proc_dir_entry *proc_entry[PROC_ENTRY_MAX];
 };
 
-struct fs_entry_desc
-{
-    uint32_t type;
-    char *file_name;
+struct fs_entry_desc {
+	uint32_t type;
+	char *file_name;
 };
 
-enum
-{
-    FS_ENTRY_BOND = 0,
+enum {
+	FS_ENTRY_BOND = 0,
 };
 
 void zxdh_create_proc_dir(struct zxdh_proc_fs *procfs);
 void zxdh_destroy_proc_dir(struct zxdh_proc_fs *procfs);
-void zxdh_create_proc_entry(struct zxdh_proc_fs *procfs,
-        uint32_t type, struct seq_operations *seq_ops, void *data);
+void zxdh_create_proc_entry(struct zxdh_proc_fs *procfs, uint32_t type,
+							struct seq_operations *seq_ops, void *data);
 void zxdh_remove_proc_entry(struct zxdh_proc_fs *procfs, uint32_t type);
 
-
 #endif /* _ZXDH_PROC_FS_H_ */
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux.c b/src/net/drivers/net/ethernet/dinghai/en_aux.c
old mode 100755
new mode 100644
index b5c64e85438c3f695735df51622eb4a5f35989f5..16cf2ea16a69f1b3dd71d48a7630f2551ddc7e0b
--- a/src/net/drivers/net/ethernet/dinghai/en_aux.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux.c
@@ -1,4046 +1,3702 @@
-#include <linux/dinghai/auxiliary_bus.h>
-#include <linux/dinghai/driver.h>
-#include <net/devlink.h>
-#include <net/udp_tunnel.h>
-#include <linux/dinghai/devlink.h>
-#include <linux/dinghai/dh_cmd.h>
-#include <linux/netdevice.h>
-#include <linux/dinghai/en_sf.h>
-#include <linux/etherdevice.h>
-#include <linux/dinghai/helper.h>
-#include <linux/dinghai/kcompat.h>
-#include <linux/if_bridge.h>
-#include "en_aux.h"
-#include "en_ethtool/ethtool.h"
-#include "en_np/table/include/dpp_tbl_api.h"
-#include "en_np/table/include/dpp_tbl_comm.h"
-#include "en_aux/events.h"
-#include "en_aux/eq.h"
-#include "en_aux/en_cmd.h"
-#include "msg_common.h"
-#include "en_pf.h"
-#include "en_aux/en_ioctl.h"
-#include <linux/dinghai/lag.h>
-#ifdef ZXDH_MSGQ
-#include "en_aux/priv_queue.h"
-#endif
-#include "en_aux/en_1588_pkt_proc.h"
-#include "en_aux/en_cmd.h"
-#include "zxdh_tools/zxdh_tools_netlink.h"
-#include <linux/jhash.h>
-
-#ifdef ZXDH_DCBNL_OPEN
-#include "en_aux/dcbnl/en_dcbnl.h"
-#endif
-
-uint32_t max_pairs = ZXDH_MQ_PAIRS_NUM;
-module_param(max_pairs, uint, S_IRUGO | S_IWUSR);
-MODULE_PARM_DESC(max_pairs, "Max queue pairs");
-
-MODULE_LICENSE("Dual BSD/GPL");
-
-/* WARNING Do not use netif_carrier_on/off(),
-   it may affect the ethtool function */
-int32_t zxdh_en_open(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t i = 0;
-    int32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    LOG_INFO("zxdh_en_open start\n");
-    mutex_lock(&en_priv->lock);
-
-    for (i = 0; i < en_dev->curr_queue_pairs; i++)
-    {
-        /* Make sure we have some buffers: if oom use wq */
-        if (!try_fill_recv(netdev, &en_dev->rq[i], GFP_KERNEL))
-        {
-            schedule_delayed_work(&en_dev->refill, 0);
-        }
-
-        virtnet_napi_enable(en_dev->rq[i].vq, &en_dev->rq[i].napi);
-        virtnet_napi_tx_enable(netdev, en_dev->sq[i].vq, &en_dev->sq[i].napi);
-    }
-
-    mutex_unlock(&en_priv->lock);
-
-    if (!en_dev->link_up)
-    {
-        return 0;
-    }
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-    if (!en_dev->ops->is_bond(en_dev->parent))
-    {
-        if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-        {
-            return zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_VPORT_IS_UP, 1, 0);
-        }
-        return dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VPORT_IS_UP, 1);
-    }
-
-    /* 给bond-pf的端口属性表配置为up */
-    err = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VPORT_IS_UP, 1);
-    if (err != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set bond pf failed\n");
-        return err;
-    }
-
-    return dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_IS_UP, 1);
-}
-
-int32_t zxdh_en_close(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t i = 0;
-    int32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    LOG_INFO("zxdh_en_close start\n");
-    /* Make sure refill_work doesn't re-enable napi! */
-    cancel_delayed_work_sync(&en_dev->refill);
-
-    for (i = 0; i < en_dev->curr_queue_pairs; i++)
-    {
-        napi_disable(&en_dev->rq[i].napi);
-        virtnet_napi_tx_disable(&en_dev->sq[i].napi);
-    }
-
-    if (!en_dev->link_up)
-    {
-        return 0;
-    }
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-    if (!en_dev->ops->is_bond(en_dev->parent))
-    {
-        if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-        {
-            return zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_VPORT_IS_UP, 0, 0);
-        }
-        return dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VPORT_IS_UP, 0);
-    }
-
-    /* 给bond-pf的端口属性表配置为down */
-    err = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VPORT_IS_UP, 0);
-    if (err != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set bond pf failed\n");
-        return err;
-    }
-
-    return dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_IS_UP, 0);
-}
-
-void pkt_transport_protocol_parse(int8_t next_protocol, struct zxdh_net_hdr *hdr)
-{
-    if (next_protocol == IPPROTO_UDP)
-    {
-        hdr->pi_hdr.pt.type_ctx.pkt_code = PCODE_UDP;
-    }
-    else if (next_protocol == IPPROTO_TCP)
-    {
-        hdr->pi_hdr.pt.type_ctx.pkt_code = PCODE_TCP;
-    }
-    else
-    {
-        hdr->pi_hdr.pt.type_ctx.pkt_code = PCODE_IP;
-    }
-
-    return;
-}
-
-void pkt_protocol_parse(struct sk_buff *skb, struct zxdh_net_hdr *hdr, int32_t flag)
-{
-    struct ethhdr *mach = NULL;
-    struct iphdr *ipv4h = NULL;
-    struct ipv6hdr *ipv6h = NULL;
-
-    if (flag == 0)
-    {
-        if (skb->protocol == htons(ETH_P_IP))
-        {
-            ipv4h = (struct iphdr *)skb_network_header(skb);
-            hdr->pi_hdr.pt.type_ctx.ip_type = IPV4_TYPE;
-            pkt_transport_protocol_parse(ipv4h->protocol, hdr);
-        }
-        else if (skb->protocol == htons(ETH_P_IPV6))
-        {
-            ipv6h = (struct ipv6hdr *)skb_network_header(skb);
-            hdr->pi_hdr.pt.type_ctx.ip_type = IPV6_TYPE;
-            pkt_transport_protocol_parse(ipv6h->nexthdr, hdr);
-        }
-        else
-        {
-            hdr->pi_hdr.pt.type_ctx.ip_type = NOT_IP_TYPE;
-        }
-    }
-    else
-    {
-        mach = (struct ethhdr *)skb_inner_mac_header(skb);
-        if (mach->h_proto == htons(ETH_P_IP))
-        {
-            ipv4h = (struct iphdr *)skb_inner_network_header(skb);
-            hdr->pi_hdr.pt.type_ctx.ip_type = IPV4_TYPE;
-            pkt_transport_protocol_parse(ipv4h->protocol, hdr);
-        }
-        else if (mach->h_proto == htons(ETH_P_IPV6))
-        {
-            ipv6h = (struct ipv6hdr *)skb_inner_network_header(skb);
-            hdr->pi_hdr.pt.type_ctx.ip_type = IPV6_TYPE;
-            pkt_transport_protocol_parse(ipv6h->nexthdr, hdr);
-
-        }
-        else
-        {
-            hdr->pi_hdr.pt.type_ctx.ip_type = NOT_IP_TYPE;
-        }
-    }
-}
-
-int32_t pkt_is_vxlan(struct sk_buff *skb)
-{
-    switch (skb->protocol)
-    {
-        case htons(ETH_P_IP):
-            if (ip_hdr(skb)->protocol != IPPROTO_UDP)
-            {
-                return -1;
-            }
-            break;
-
-        case htons(ETH_P_IPV6):
-            if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP)
-            {
-                return -1;
-            }
-            break;
-
-        default:
-            return -1;
-    }
-
-    if (skb->inner_protocol_type != ENCAP_TYPE_ETHER || skb->inner_protocol != htons(ETH_P_TEB) ||
-        (skb_inner_mac_header(skb) - skb_transport_header(skb) != sizeof(struct udphdr) + sizeof(struct vxlanhdr)))
-    {
-        return -1;
-    }
-
-    return 0;
-}
-
-int32_t zxdh_tx_checksum_offload(struct zxdh_en_device *edev, struct sk_buff *skb, struct zxdh_net_hdr *hdr)
-{
-    if (skb->ip_summed != CHECKSUM_PARTIAL)
-    {
-        return 0;
-    }
-
-    if ((skb->inner_protocol != 0) && (pkt_is_vxlan(skb) == 0))
-    {
-        skb->encapsulation = 0x1;
-    }
-
-    if(skb->encapsulation == 0x1)
-    {
-        if ((edev->netdev->features & NETIF_F_GSO_UDP_TUNNEL_CSUM) == 0)
-        {
-            return 0;
-        }
-        hdr->pi_hdr.bttl_pi_len = ENABLE_PI_FLAG_32B;
-        hdr->pd_hdr.ol_flag |= htons(0x1 << OUTER_IP_CHECKSUM_OFFSET);
-        pkt_protocol_parse(skb, hdr, 1);
-        hdr->pi_hdr.hdr_l3_offset = htons(edev->hdr_len + skb_inner_network_offset(skb));
-        hdr->pi_hdr.hdr_l4_offset = htons(edev->hdr_len + skb_inner_transport_offset(skb));
-    }
-
-    hdr->pi_hdr.pkt_action_flag1 |= htons(0x1 << INNER_IP_CHECKSUM_OFFSET);
-    hdr->pi_hdr.pkt_action_flag2 |= 0x1 << INNER_L4_CHECKSUM_OFFSET;
-    return 0;
-}
-
-static int pd_hdr_validate_vlan(struct zxdh_en_device *edev, struct sk_buff *skb, struct zxdh_net_hdr *hdr)
-{
-    /* pf set vf vlan is done*/
-    if (edev->vlan_dev.vlan_id)
-    {
-        if (!skb_vlan_tag_present(skb))
-        {
-            hdr->pd_hdr.cvlan.tci = htons(edev->vlan_dev.vlan_id);
-            hdr->pd_hdr.cvlan.tpid = (edev->vlan_dev.protcol);
-            hdr->pd_hdr.ol_flag |= htons(TXCAP_CTAG_INSERT_EN_BIT);
-            return 0;
-        }
-        else
-        {
-            hdr->pd_hdr.svlan.tci = htons(edev->vlan_dev.vlan_id);
-            hdr->pd_hdr.svlan.tpid = (edev->vlan_dev.protcol);
-            hdr->pd_hdr.ol_flag |= htons(TXCAP_STAG_INSERT_EN_BIT);
-        }
-    }
-
-    /* insert vlan hard-accellate when skb is taged to be inserted, eg. in vlan interface case*/
-    if (skb && skb_vlan_tag_present(skb))
-    {
-        hdr->pd_hdr.cvlan.tci =  htons(skb_vlan_tag_get(skb));
-        hdr->pd_hdr.cvlan.tpid = (skb->vlan_proto);
-        hdr->pd_hdr.ol_flag |= htons(TXCAP_CTAG_INSERT_EN_BIT);
-    }
-    return 0;
-}
-
-
-int32_t pi_net_hdr_from_skb(struct zxdh_en_device *edev, struct sk_buff *skb, struct zxdh_net_hdr *hdr)
-{
-    uint32_t gso_type = 0;
-    uint16_t mss = 0;
-#ifdef TIME_STAMP_1588
-    int32_t ret = 0;
-#endif
-
-    memset(hdr, 0, sizeof(*hdr)); /* no info leak */
-    hdr->pd_len = edev->hdr_len / HDR_2B_UNIT;
-    hdr->pi_hdr.bttl_pi_len = DISABLE_PI_FIELD_PARSE + ENABLE_PI_FLAG_32B;
-    hdr->tx_port = TX_PORT_DTP;
-    hdr->pi_hdr.pt.type_ctx.pkt_src = PKT_SRC_CPU;
-    hdr->pi_hdr.eth_port_id = INVALID_ETH_PORT_ID;
-
-    if(edev->delay_statistics_enable)
-    {
-        pkt_delay_statistics_proc(skb, hdr, edev);
-    }
-
-// #ifdef TIME_STAMP_1588
-//     ret = pkt_1588_proc_xmit(skb, hdr, edev->clock_no, edev);
-//     switch (ret)
-//     {
-//         case PTP_SUCCESS:
-//         {
-//             LOG_DEBUG("pkt_1588_proc_xmit success!!!\n");
-//             return 0;
-//         }
-//         case IS_NOT_PTP_MSG:
-//         {
-//             LOG_DEBUG("not ptp msg!!\n");
-//             break;
-//         }
-//         default:
-//         {
-//             LOG_ERR("pkt_1588_proc_xmit err!!!\n");
-//             return ret;
-//         }
-//     }
-// #endif
-
-    pd_hdr_validate_vlan(edev, skb, hdr);
-
-    mss = skb_shinfo(skb)->gso_size;
-    gso_type = skb_shinfo(skb)->gso_type;
-    if(gso_type & SKB_GSO_TCPV4)
-    {
-        mss = (mss > 0) ? min(skb_shinfo(skb)->gso_size, (uint16_t)(edev->netdev->mtu - IP_BASE_HLEN - TCP_BASE_HLEN))
-                        : (uint16_t)(edev->netdev->mtu - IP_BASE_HLEN - TCP_BASE_HLEN);
-        hdr->pi_hdr.pkt_action_flag1 |= htons((mss / ETH_MTU_4B_UNIT) + NOT_IP_FRG_CSUM_FLAG);
-        hdr->pi_hdr.pkt_action_flag2 |= TCP_FRG_CSUM_FLAG; /*0x24  bit21,18: 带pi,tso,计算checksum */
-    }
-    else if(gso_type & SKB_GSO_TCPV6)
-    {
-        mss = (mss > 0) ? min(skb_shinfo(skb)->gso_size, (uint16_t)(edev->netdev->mtu - IPV6_BASE_HLEN - TCP_BASE_HLEN))
-                        : (uint16_t)(edev->netdev->mtu - IPV6_BASE_HLEN - TCP_BASE_HLEN);
-        hdr->pi_hdr.pkt_action_flag1 |= htons((mss / ETH_MTU_4B_UNIT) + NOT_IP_FRG_CSUM_FLAG);
-        hdr->pi_hdr.pkt_action_flag2 |= TCP_FRG_CSUM_FLAG; /*0x24  bit21,18: 带pi,tso,计算checksum */
-    }
-    else if(gso_type & (SKB_GSO_UDP | SKB_GSO_UDP_L4 | SKB_GSO_UDP_TUNNEL | SKB_GSO_UDP_TUNNEL_CSUM))
-    {
-        hdr->pi_hdr.pkt_action_flag1 = htons((uint16_t)(edev->netdev->mtu / ETH_MTU_4B_UNIT) + IP_FRG_CSUM_FLAG);
-        hdr->pi_hdr.pkt_action_flag2 |= NOT_TCP_FRG_CSUM_FLAG;
-    }
-    else
-    {
-        hdr->pi_hdr.pkt_action_flag1 |= htons((edev->netdev->mtu / ETH_MTU_4B_UNIT) + NOT_IP_FRG_CSUM_FLAG);
-        hdr->pi_hdr.pkt_action_flag2 |= NOT_TCP_FRG_CSUM_FLAG;
-    }
-
-    if (edev->netdev->features & NETIF_F_HW_CSUM)
-    {
-        zxdh_tx_checksum_offload(edev, skb, hdr);
-    }
-
-    if ((edev->ops->is_bond(edev->parent)) &&
-        (skb->protocol == htons(ETH_P_SLOW) || skb->protocol == htons(ETH_P_PAUSE)))
-    {
-        hdr->pd_hdr.ol_flag |= htons(PANELID_EN);
-        hdr->pd_hdr.panel_id = edev->phy_port;
-    }
-
-    #ifdef ZXDH_DCBNL_OPEN
-    if (NULL != skb->sk)
-    {
-        hdr->pd_hdr.ol_flag |= htons(ZXDH_DCBNL_SET_SK_PRIO(skb->sk->sk_priority));
-    }
-    #endif
-
-
-#ifdef TIME_STAMP_1588
-    ret = pkt_1588_proc_xmit(skb, hdr, edev->clock_no, edev);
-    switch (ret)
-    {
-        case PTP_SUCCESS:
-        {
-            LOG_DEBUG("pkt_1588_proc_xmit success!!!\n");
-            return 0;
-        }
-        case IS_NOT_PTP_MSG:
-        {
-            LOG_DEBUG("not ptp msg!!\n");
-            break;
-        }
-        default:
-        {
-            LOG_ERR("pkt_1588_proc_xmit err!!!\n");
-            return ret;
-        }
-    }
-#endif
-    return 0;
-}
-
-int32_t xmit_skb(struct net_device *netdev, struct send_queue *sq, struct sk_buff *skb)
-{
-    struct zxdh_net_hdr *hdr = NULL;
-    //const unsigned char *dest = ((struct ethhdr *)skb->data)->h_dest;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t num_sg = 0;
-    unsigned hdr_len = en_dev->hdr_len;
-    bool can_push = false;
-    uint8_t *hdr_buf = sq->hdr_buf;
-
-    can_push = en_dev->any_header_sg &&
-        !((unsigned long)skb->data & (__alignof__(*hdr) - 1)) &&
-        !skb_header_cloned(skb) && skb_headroom(skb) >= hdr_len;
-    /* Even if we can, don't push here yet as this would skew
-     * csum_start offset below. */
-    if (can_push)
-    {
-        hdr = (struct zxdh_net_hdr *)(skb->data - hdr_len);
-    }
-    else
-    {
-        memset(hdr_buf, 0, HDR_BUFFER_LEN);
-        hdr = (struct zxdh_net_hdr *)hdr_buf;
-    }
-
-    if (pi_net_hdr_from_skb(en_dev, skb, hdr))
-    {
-        return -EPROTO;
-    }
-
-    sg_init_table(sq->sg, skb_shinfo(skb)->nr_frags + (can_push ? 1 : 2));
-    if (can_push)
-    {
-        __skb_push(skb, hdr_len);
-        num_sg = skb_to_sgvec(skb, sq->sg, 0, skb->len);
-        if (unlikely(num_sg < 0))
-        {
-            return num_sg;
-        }
-        /* Pull header back to avoid skew in tx bytes calculations. */
-        __skb_pull(skb, hdr_len);
-    }
-    else
-    {
-        sg_set_buf(sq->sg, hdr, hdr_len);
-        num_sg = skb_to_sgvec(skb, sq->sg + 1, 0, skb->len);
-        if (unlikely(num_sg < 0))
-        {
-            return num_sg;
-        }
-        num_sg++;
-    }
-
-    return virtqueue_add_outbuf(sq->vq, sq->sg, num_sg, skb, GFP_ATOMIC);
-}
-
-netdev_tx_t zxdh_en_xmit(struct sk_buff *skb, struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t qnum = skb_get_queue_mapping(skb);
-    struct send_queue *sq = &en_dev->sq[qnum];
-    int32_t err = 0;
-    struct netdev_queue *txq = netdev_get_tx_queue(netdev, qnum);
-    bool kick = !netdev_xmit_more();
-    bool use_napi = sq->napi.weight;
-
-    /* Free up any pending old buffers before queueing new ones. */
-    do {
-        if (use_napi)
-        {
-            virtqueue_disable_cb(sq->vq);
-        }
-
-        free_old_xmit_skbs(netdev, sq, false);
-
-    } while (use_napi && kick && unlikely(!virtqueue_enable_cb_delayed(sq->vq)));
-
-    /* timestamp packet in software */
-    skb_tx_timestamp(skb);
-
-    /* Try to transmit */
-    err = xmit_skb(netdev, sq, skb);
-
-    /* This should not happen! */
-    if (unlikely(err))
-    {
-        netdev->stats.tx_fifo_errors++;
-        netdev->stats.tx_errors++;
-        if (net_ratelimit())
-        {
-            LOG_WARN("unexpected TXQ (%d) queue failure: %d\n", qnum, err);
-        }
-        netdev->stats.tx_dropped++;
-        dev_kfree_skb_any(skb);
-        return NETDEV_TX_OK;
-    }
-
-    /* If running out of space, stop queue to avoid getting packets that we
-     * are then unable to transmit.
-     * An alternative would be to force queuing layer to requeue the skb by
-     * returning NETDEV_TX_BUSY. However, NETDEV_TX_BUSY should not be
-     * returned in a normal path of operation: it means that driver is not
-     * maintaining the TX queue stop/start state properly, and causes
-     * the stack to do a non-trivial amount of useless work.
-     * Since most packets only take 1 or 2 ring slots, stopping the queue
-     * early means 16 slots are typically wasted.
-     */
-    if (sq->vq->num_free < 2 + MAX_SKB_FRAGS)
-    {
-        netif_stop_subqueue(netdev, qnum);
-        en_dev->hw_stats.q_stats[qnum].q_tx_stopped++;
-        if (!use_napi && unlikely(!virtqueue_enable_cb_delayed(sq->vq)))
-        {
-            /* More just got used, free them then recheck. */
-            free_old_xmit_skbs(netdev, sq, false);
-            if (sq->vq->num_free >= 2 + MAX_SKB_FRAGS)
-            {
-                netif_start_subqueue(netdev, qnum);
-                virtqueue_disable_cb(sq->vq);
-            }
-        }
-    }
-
-    if (kick || netif_xmit_stopped(txq))
-    {
-        if (virtqueue_kick_prepare_packed(sq->vq) && virtqueue_notify(sq->vq))
-        {
-            u64_stats_update_begin(&sq->stats.syncp);
-            sq->stats.kicks++;
-            u64_stats_update_end(&sq->stats.syncp);
-        }
-    }
-
-    return NETDEV_TX_OK;
-}
-
-#ifdef HAVE_NDO_GET_STATS64
-#ifdef HAVE_VOID_NDO_GET_STATS64
-static void zxdh_en_get_netdev_stats_struct(struct net_device *netdev, struct rtnl_link_stats64 *stats)
-#else
-static struct rtnl_link_stats64 *zxdh_en_get_netdev_stats_struct(struct net_device *netdev, struct rtnl_link_stats64 *stats)
-#endif
-{
-#ifdef HAVE_VOID_NDO_GET_STATS64
-    struct zxdh_en_device *en_dev = netdev_priv(netdev);
-    struct receive_queue *rq = NULL;
-    struct send_queue *sq = NULL;
-    uint32_t start = 0;
-    uint32_t i = 0;
-    uint64_t tpackets = 0;
-    uint64_t tbytes = 0;
-    uint64_t rpackets = 0;
-    uint64_t rbytes = 0;
-    uint64_t rdrops = 0;
-    uint32_t loop_cnt = en_dev->max_queue_pairs;
-    int32_t ret = 0;
-
-    if (en_dev->ops->is_bond(en_dev->parent))
-    {
-        ret = zxdh_mac_stats_get(en_dev);
-        if (ret != 0)
-        {
-            LOG_ERR("zxdh_mac_stats_get failed, ret: %d\n", ret);
-            return;
-        }
-
-        stats->rx_packets = en_dev->hw_stats.phy_stats.rx_packets_phy;
-        stats->rx_bytes   = en_dev->hw_stats.phy_stats.rx_bytes_phy;
-        stats->rx_errors  = en_dev->hw_stats.phy_stats.rx_errors;
-        stats->rx_dropped = en_dev->hw_stats.phy_stats.rx_discards;
-        stats->tx_packets = en_dev->hw_stats.phy_stats.tx_packets_phy;
-        stats->tx_bytes   = en_dev->hw_stats.phy_stats.tx_bytes_phy;
-        stats->tx_errors  = en_dev->hw_stats.phy_stats.tx_errors;
-        stats->tx_dropped = en_dev->hw_stats.phy_stats.tx_drop;
-        return;
-    }
-
-#ifdef ZXDH_MSGQ
-    NEED_MSGQ(en_dev)
-    {
-        loop_cnt--;
-    }
-#endif
-
-    for (i = 0; i < loop_cnt; ++i)
-    {
-        sq = &en_dev->sq[i];
-        rq = &en_dev->rq[i];
-        do
-        {
-            start = u64_stats_fetch_begin_irq(&sq->stats.syncp);
-            tpackets = sq->stats.packets;
-            tbytes   = sq->stats.bytes;
-        } while (u64_stats_fetch_retry_irq(&sq->stats.syncp, start));
-
-        do
-        {
-            start = u64_stats_fetch_begin_irq(&rq->stats.syncp);
-            rpackets = rq->stats.packets;
-            rbytes   = rq->stats.bytes;
-            rdrops   = rq->stats.drops;
-        } while (u64_stats_fetch_retry_irq(&rq->stats.syncp, start));
-
-        stats->rx_packets += rpackets;
-        stats->rx_bytes   += rbytes;
-        stats->rx_dropped += rdrops;
-        stats->tx_packets += tpackets;
-        stats->tx_bytes   += tbytes;
-    }
-
-    stats->rx_errors = netdev->stats.rx_errors;
-    stats->tx_errors = netdev->stats.tx_errors;
-    stats->tx_dropped = netdev->stats.tx_dropped;
-    stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
-    return;
-#else
-    return stats;
-#endif
-}
-#endif/* HAVE_VOID_NDO_GET_STATS_64 */
-
-static void zxdh_en_set_rx_mode(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    queue_work(en_priv->events->wq, &en_dev->rx_mode_set_work);
-}
-
-void rx_mode_set_handler(struct work_struct *work)
-{
-    struct zxdh_en_device *en_dev = container_of(work, struct zxdh_en_device, rx_mode_set_work);
-    bool promisc_changed = false;
-    bool allmulti_changed = false;
-    int32_t err = 0;
-    uint8_t fow = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-    ZXDH_AUX_INIT_COMP_CHECK(en_dev);
-
-    if (en_dev->ops->is_bond(en_dev->parent))
-    {
-        return;
-    }
-
-    promisc_changed = en_dev->netdev->flags & IFF_PROMISC;
-    allmulti_changed = en_dev->netdev->flags & IFF_ALLMULTI;
-    if (en_dev->promisc_enabled != promisc_changed)
-    {
-        LOG_INFO("promisc_changed: %d", promisc_changed);
-        if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-        {
-            dpp_vport_uc_promisc_set(&pf_info, promisc_changed);
-            if (!en_dev->allmulti_enabled)
-            {
-                dpp_vport_mc_promisc_set(&pf_info, promisc_changed);
-            }
-        }
-        else
-        {
-            if (!en_dev->allmulti_enabled)
-            {
-                fow = 1;
-            }
-            err = zxdh_vf_port_promisc_set(en_dev, ZXDH_PROMISC_MODE, promisc_changed, fow);
-            if (err != 0)
-            {
-                LOG_ERR("zxdh_vf_port_promisc_set failed\n");
-                return;
-            }
-        }
-        en_dev->promisc_enabled = promisc_changed;
-    }
-
-    if (en_dev->allmulti_enabled != allmulti_changed)
-    {
-        LOG_INFO("allmulti_changed: %d", allmulti_changed);
-        if (!en_dev->promisc_enabled)
-        {
-            if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-            {
-                dpp_vport_mc_promisc_set(&pf_info, allmulti_changed);
-            }
-            else
-            {
-                err = zxdh_vf_port_promisc_set(en_dev, ZXDH_ALLMULTI_MODE, allmulti_changed, fow);
-                if (err != 0)
-                {
-                    LOG_ERR("zxdh_vf_port_promisc_set failed\n");
-                    return;
-                }
-            }
-        }
-        en_dev->allmulti_enabled = allmulti_changed;
-    }
-}
-
-static int zxdh_en_bar_cfg_mac(struct net_device *netdev, const char *mac)
-{
-    int ret = 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    union zxdh_msg msg = {0};
-
-    memcpy(msg.payload.mac_cfg_msg.ifname, netdev->name, IFNAMSIZ);
-    memcpy(msg.payload.mac_cfg_msg.mac, mac, ETH_ALEN);
-    msg.payload.mac_cfg_msg.pannel_id = en_dev->panel_id;
-
-    if (en_dev->ops->is_bond(en_dev->parent))
-    {
-        msg.payload.mac_cfg_msg.pannel_id = en_dev->pannel_id;
-    }
-    msg.payload.mac_cfg_msg.ctl = 1;
-
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_CFG_MAC, &msg, &msg);
-    if (ret != 0 || msg.reps.flag != ZXDH_REPS_SUCC)
-    {
-        LOG_ERR("config mac info failed\n");
-        return -msg.reps.flag;
-    }
-    return 0;
-}
-
-static int zxdh_en_bar_del_mac(struct net_device *netdev)
-{
-    int ret = 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    union zxdh_msg msg = {0};
-
-    msg.payload.mac_cfg_msg.pannel_id = en_dev->panel_id;
-
-    if (en_dev->ops->is_bond(en_dev->parent))
-    {
-        msg.payload.mac_cfg_msg.pannel_id = en_dev->pannel_id;
-    }
-    msg.payload.mac_cfg_msg.ctl = 0;
-
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_CFG_MAC, &msg, &msg);
-    if (ret != 0 || msg.reps.flag != ZXDH_REPS_SUCC)
-    {
-        LOG_ERR("del mac info failed.\n");
-        return -msg.reps.flag;
-    }
-    return 0;
-}
-
-static int zxdh_en_set_mac(struct net_device *netdev, void *p)
-{
-    struct  sockaddr *addr         = (struct  sockaddr *)p;
-    struct  zxdh_en_device *en_dev = NULL;
-    struct  zxdh_en_priv *en_priv  = NULL;
-    struct  netdev_hw_addr *ha     = NULL;
-    bool    delete_flag            = true;
-    bool    add_flag               = true;
-    int32_t ret                    = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    if (!is_valid_ether_addr(addr->sa_data))
-    {
-        LOG_INFO("invalid mac address %pM\n", addr->sa_data);
-        return -EADDRNOTAVAIL;
-    }
-
-    if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
-    {
-        LOG_INFO("already using mac address %pM\n", addr->sa_data);
-        return 0;
-    }
-
-    list_for_each_entry(ha, &netdev->uc.list, list)
-    {
-        if (!memcmp(ha->addr, netdev->dev_addr, netdev->addr_len))
-        {
-            delete_flag = false;
-        }
-
-        if (!memcmp(ha->addr, addr->sa_data, netdev->addr_len))
-        {
-            add_flag = false;
-        }
-    }
-
-    en_priv = netdev_priv(netdev);
-    en_dev  = &en_priv->edev;
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (en_dev->ops->is_bond(en_dev->parent))
-    {
-        ether_addr_copy(netdev->dev_addr, addr->sa_data);
-        zxdh_en_bar_del_mac(netdev);
-        zxdh_en_bar_cfg_mac(netdev, netdev->dev_addr);
-        return 0;
-    }
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        if (delete_flag)
-        {
-            ret = dpp_del_mac(&pf_info, netdev->dev_addr);
-            if (ret != 0)
-            {
-                LOG_ERR("pf del mac failed, retval: %d\n", ret);
-                return ret;
-            }
-        }
-
-        if (add_flag)
-        {
-            ret = dpp_add_mac(&pf_info, addr->sa_data);
-            if (ret != 0)
-            {
-                LOG_ERR("pf add mac failed: %d\n", ret);
-                return ret;
-            }
-        }
-
-        LOG_INFO("set pf new mac address %pM\n", addr->sa_data);
-        ether_addr_copy(netdev->dev_addr, addr->sa_data);
-        if (!en_dev->ops->is_upf(en_dev->parent))
-        {
-            zxdh_en_bar_del_mac(netdev);
-            zxdh_en_bar_cfg_mac(netdev, netdev->dev_addr);
-        }
-    }
-    else
-    {
-        ret = zxdh_vf_dpp_del_mac(en_dev, netdev->dev_addr, UNFILTER_MAC, delete_flag);
-        if (ret != 0)
-        {
-            LOG_ERR("zxdh vf dpp del mac failed: %d\n", ret);
-            return ret;
-        }
-
-        if (add_flag)
-        {
-            ret = zxdh_vf_dpp_add_mac(en_dev, addr->sa_data, UNFILTER_MAC);
-            if (ret != 0)
-            {
-                LOG_ERR("zxdh vf dpp add mac failed: %d\n", ret);
-                return ret;
-            }
-            en_dev->ops->set_mac(en_dev->parent, addr->sa_data);
-        }
-
-        LOG_INFO("set vf new mac address %pM\n", addr->sa_data);
-        ether_addr_copy(netdev->dev_addr, addr->sa_data);
-    }
-
-    return ret;
-}
-
-int32_t zxdh_en_config_mtu_to_np(struct net_device *netdev, int32_t mtu_value)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t ret = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_MTU_OFFLOAD_ENABLE, 1);
-        dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_MTU, mtu_value);
-        dpp_egr_port_attr_set(&pf_info, EGR_FLAG_MTU_OFFLOAD_EN_OFF, 1);
-        dpp_egr_port_attr_set(&pf_info, EGR_FLAG_MTU, mtu_value);
-    }
-    else
-    {
-        ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_MTU_OFFLOAD_EN_OFF, 1, 0);
-        if (ret != 0)
-        {
-            LOG_ERR("zxdh_vf_egr_port_attr_set config mtu enable failed: %d\n", ret);
-            return ret;
-        }
-        ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_MTU, mtu_value, 0);
-        if (ret != 0)
-        {
-            LOG_ERR("zxdh_vf_egr_port_attr_set config mut value failed: %d\n", ret);
-            return ret;
-        }
-    }
-
-    return 0;
-}
-
-static int zxdh_en_change_mtu(struct net_device *netdev, int new_mtu)
-{
-    int32_t ret = 0;
-
-    if ((new_mtu < ETH_MIN_MTU) || (new_mtu > ZXDH_MAX_MTU))
-    {
-       return -EINVAL;
-    }
-    LOG_INFO("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
-
-    netdev->mtu = new_mtu;
-
-    ret = zxdh_en_config_mtu_to_np(netdev, new_mtu);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_en_config_mtu_to_np failed: %d\n", ret);
-        return ret;
-    }
-
-    return 0;
-}
-
-#ifdef HAVE_TX_TIMEOUT_TXQUEUE
-static void zxdh_en_tx_timeout(struct net_device *netdev, unsigned int txqueue)
-{
-    return;
-}
-#else
-static void zxdh_en_tx_timeout(struct net_device *netdev)
-{
-    return;
-}
-#endif
-
-#ifdef HAVE_VLAN_RX_REGISTER
-static void zxdh_en_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
-{
-    return;
-}
-#endif
-
-static int __attribute__((unused)) vf_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
-{
-    int ret = 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    union zxdh_msg msg = {0};
-
-    msg.payload.hdr.op_code = ZXDH_VLAN_FILTER_ADD;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.hdr.pcie_id = en_dev->pcie_id;
-    msg.payload.rx_vid_add_msg.vlan_id = vid;
-
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
-    if (ret != 0 || msg.reps.flag != ZXDH_REPS_SUCC)
-    {
-        LOG_ERR("pcieid:0x%x send msg to pf add vlan:%d failed! ret = %d, flag = 0x%x\n",
-                                                    en_dev->pcie_id,
-                                                    vid,
-                                                    ret,
-                                                    msg.reps.flag);
-        return -1;
-    }
-
-    return 0;
-}
-
-#if defined(HAVE_INT_NDO_VLAN_RX_ADD_VID) && defined(NETIF_F_HW_VLAN_CTAG_RX)
-static int zxdh_en_vlan_rx_add_vid(struct net_device *netdev, __always_unused __be16 proto, u16 vid)
-{
-    int retval = 0;
-#if 0
-    struct zxdh_en_priv *zxdev = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &zxdev->edev;
-    uint16_t pcieid = en_dev->pcie_id;
-
-    if (vid > MAX_VLAN_ID)
-    {
-        LOG_ERR("vlan id:%d input is err!\n", vid);
-        return -EINVAL;
-    }
-
-    if ((pcieid & PF_AC_MASK) == 0) /* VF */
-    {
-        retval = vf_vlan_rx_add_vid(netdev, vid);
-        goto exit;
-    }
-
-    retval = dpp_add_vlan_filter(zxdev->edev.vport, vid);
-    if (0 != retval)
-    {
-        LOG_ERR("failed to add vlan: %d\n",vid);
-        goto exit;
-    }
-    LOG_INFO("pf add vlan %d succeed.\n", vid);
-
-exit:
-#endif
-    return retval;
-}
-#elif defined(HAVE_INT_NDO_VLAN_RX_ADD_VID) && !defined(NETIF_F_HW_VLAN_CTAG_RX)
-static int zxdh_en_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
-{
-    return 0;
-}
-#else
-static void zxdh_en_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
-{
-    return;
-}
-#endif
-
-static int vf_vlan_rx_del_vid(struct net_device *netdev, u16 vid)
-{
-    int ret = 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    union zxdh_msg msg = {0};
-
-    msg.payload.hdr.op_code = ZXDH_VLAN_FILTER_DEL;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.hdr.pcie_id = en_dev->pcie_id;
-    msg.payload.rx_vid_del_msg.vlan_id = vid;
-
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
-    if (ret != 0 || msg.reps.flag != ZXDH_REPS_SUCC)
-    {
-        LOG_ERR("pcieid:0x%x send msg to pf del vlan:%d failed! ret = %d, flag = 0x%x\n",
-                                                    en_dev->pcie_id,
-                                                    vid,
-                                                    ret,
-                                                    msg.reps.flag);
-        return -1;
-    }
-
-    return 0;
-}
-
-
-#if defined(HAVE_INT_NDO_VLAN_RX_ADD_VID) && defined(NETIF_F_HW_VLAN_CTAG_RX)
-static int zxdh_en_vlan_rx_kill_vid(struct net_device *netdev, __always_unused __be16 proto, u16 vid)
-{
-    int retval = 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint16_t pcieid = en_dev->pcie_id;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (vid > MAX_VLAN_ID)
-    {
-        LOG_ERR("vlan id:%d input is err!\n", vid);
-        return -EINVAL;
-    }
-
-    if ((pcieid & PF_AC_MASK) == 0) /* VF */
-    {
-        retval = vf_vlan_rx_del_vid(netdev, vid);
-        goto exit;
-    }
-
-    retval = dpp_del_vlan_filter(&pf_info, vid);
-    if (0 != retval)
-    {
-        LOG_ERR("failed to del vlan: %d\n", vid);
-        goto exit;
-    }
-    LOG_INFO("pf del vlan %d succeed.\n", vid);
-
-exit:
-    return retval;
-}
-#elif defined(HAVE_INT_NDO_VLAN_RX_ADD_VID) && !defined(NETIF_F_HW_VLAN_CTAG_RX)
-static int zxdh_en_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
-{
-    return 0;
-}
-#else
-static void zxdh_en_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
-{
-    return;
-}
-#endif
-
-static void zxdh_en_netpoll(struct net_device *netdev)
-{
-    return;
-}
-
-#ifdef HAVE_SETUP_TC
-int zxdh_en_setup_tc(struct net_device *netdev, u8 tc)
-{
-    return 0;
-}
-
-#ifdef NETIF_F_HW_TC
-#ifdef HAVE_NDO_SETUP_TC_REMOVE_TC_TO_NETDEV
-static int __zxdh_en_setup_tc(struct net_device *netdev, enum tc_setup_type type, void *type_data)
-#elif defined(HAVE_NDO_SETUP_TC_CHAIN_INDEX)
-static int __zxdh_en_setup_tc(struct net_device *netdev, u32 handle,
-                              u32 chain_index, __be16 proto,
-                              struct tc_to_netdev *tc)
-#else
-static int __zxdh_en_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
-                              struct tc_to_netdev *tc)
-#endif
-{
-    return 0;
-}
-#endif
-#endif
-
-#ifdef HAVE_NDO_GET_PHYS_PORT_ID
-static int zxdh_en_get_phys_port_id(struct net_device *netdev, struct netdev_phys_item_id *ppid)
-{
-    return 0;
-}
-#endif /* HAVE_NDO_GET_PHYS_PORT_ID */
-
-
-static void zxdh_set_en_device(struct net_device *netdev, netdev_features_t features)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    if ((features & NETIF_F_GSO) || (features & NETIF_F_GSO_UDP) || (features & NETIF_F_GSO_UDP_L4))
-    {
-        en_dev->drs_offload = true;
-    }
-    else if ((features & NETIF_F_TSO) || (features & NETIF_F_HW_CSUM))
-    {
-        en_dev->dtp_offload = true;
-    }
-    else
-    {
-        en_dev->np_direction = true;
-    }
-
-    return;
-}
-
-static int zxdh_handle_feature(struct net_device *netdev,
-                netdev_features_t *features,
-                netdev_features_t wanted_features,
-                netdev_features_t feature,
-                zxdh_feature_handler feature_handler)
-{
-    netdev_features_t changes = wanted_features ^ netdev->features;
-    bool enable = !!(wanted_features & feature);
-    int err;
-
-    if (!(changes & feature) || feature_handler == NULL)
-    {
-        return 0;
-    }
-
-    err = feature_handler(netdev, enable);
-    if (err)
-    {
-        LOG_ERR("%s feature %pNF failed, err %d\n",
-               enable ? "Enable" : "Disable", &feature, err);
-        return err;
-    }
-
-    ZXDH_SET_FEATURE(features, feature, enable);
-    return 0;
-}
-
-static int32_t zxdh_dtp_offload_set(struct zxdh_en_device *en_dev, DPP_PF_INFO_T *pf_info)
-{
-    ZXDH_VPORT_T port_attr_entry = {0};
-    int32_t ret = 0;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        ret = dpp_egr_port_attr_get(pf_info, &port_attr_entry);
-        if (ret != 0)
-        {
-            LOG_ERR("dpp_egr_port_attr_get failed: %d\n", ret);
-            return ret;
-        }
-
-        if (!port_attr_entry.lro_offload && !port_attr_entry.ip_fragment_offload &&
-            !port_attr_entry.ip_checksum_offload && !port_attr_entry.tcp_udp_checksum_offload)
-        {
-            ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 0);
-        }
-        else
-        {
-            ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 1);
-        }
-
-        return ret;
-    }
-
-    ret = zxdh_vf_egr_port_attr_get(en_dev, &port_attr_entry);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_get failed: %d\n", ret);
-        return ret;
-    }
-
-    if (!port_attr_entry.lro_offload && !port_attr_entry.ip_fragment_offload &&
-        !port_attr_entry.ip_checksum_offload && !port_attr_entry.tcp_udp_checksum_offload)
-    {
-        ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 0, 0);
-    }
-    else
-    {
-        ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 1, 0);
-    }
-
-    return ret;
-}
-
-static int32_t set_feature_rx_checksum(struct net_device *netdev, bool enable)
-{
-    int en_value = enable ? 1 : 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    DPP_PF_INFO_T pf_info = {0};
-    int32_t ret = 0;
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IP_CHKSUM, enable);
-        if (ret != 0)
-        {
-            LOG_ERR("EGR_FLAG_IP_CHKSUM set failed: %d\n", ret);
-            return ret;
-        }
-        ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_TCP_UDP_CHKSUM, enable);
-        if (ret != 0)
-        {
-            LOG_ERR("EGR_FLAG_TCP_UDP_CHKSUM set failed: %d\n", ret);
-            return ret;
-        }
-    }
-    else if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-    {
-        ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_IP_CHKSUM, en_value, 0);
-        if (ret != 0)
-        {
-            LOG_ERR("EGR_FLAG_IP_CHKSUM set failed: %d\n", ret);
-            return ret;
-        }
-        ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_TCP_UDP_CHKSUM, en_value, 0);
-        if (ret != 0)
-        {
-            LOG_ERR("EGR_FLAG_TCP_UDP_CHKSUM set failed: %d\n", ret);
-            return ret;
-        }
-    }
-
-    return zxdh_dtp_offload_set(en_dev, &pf_info);
-}
-
-static int set_feature_tx_checksum(struct net_device *netdev, bool enable)
-{
-    if (enable)
-    {
-        netdev->features |= NETIF_F_HW_CSUM;
-    }
-    else
-    {
-        netdev->features &= ~NETIF_F_HW_CSUM;
-    }
-    return 0;
-}
-
-static int set_feature_vxlan_checksum(struct net_device *netdev, bool enable)
-{
-    int ret = 0;
-    int en_value = enable ? 1 : 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (enable)
-    {
-        netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
-    }
-    else
-    {
-        netdev->features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
-    }
-
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD, enable);
-        if (ret != 0)
-        {
-            LOG_ERR("zxdh set vxlan rx checksum failed!\n");
-            return ret;
-        }
-    }
-    else if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-    {
-        ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD, en_value, 0);
-        if (ret != 0)
-        {
-            LOG_ERR("zxdh_vf_egr_port_attr_set vxlan rx checksum failed!\n");
-            return ret;
-        }
-    }
-
-    return ret;
-}
-
-static int32_t set_feature_rxhash(struct net_device *netdev, bool enable)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        return dpp_vport_rss_en_set(&pf_info, enable);
-    }
-
-    return zxdh_vf_rss_en_set(en_dev, enable);
-}
-
-static int32_t set_vf_cvlan_filter(struct net_device *netdev, bool enable)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    union zxdh_msg msg = {0};
-    int32_t ret = 0;
-
-    msg.payload.hdr.op_code = ZXDH_VLAN_FILTER_SET;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.hdr.pcie_id = en_dev->pcie_id;
-    msg.payload.vlan_filter_set_msg.enable = enable;
-
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
-    if (ret != 0 || msg.reps.flag != ZXDH_REPS_SUCC)
-    {
-        LOG_ERR("pcieid:0x%x send msg to pf set vlan filter enable:%s failed! ret = %d, flag = 0x%x\n",
-                                                    en_dev->pcie_id,
-                                                    enable ? "enable":"disable",
-                                                    ret,
-                                                    msg.reps.flag);
-        return -1;
-    }
-
-    return 0;
-}
-
-static int __attribute__((unused)) set_feature_cvlan_filter(struct net_device *netdev, bool enable)
-{
-    int ret = 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint16_t pcieid = en_dev->pcie_id;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if ((pcieid & PF_AC_MASK) == 0) /* VF */
-    {
-        ret = set_vf_cvlan_filter(netdev, enable);
-        goto exit;
-    }
-
-    ret = dpp_vport_vlan_filter_en_set(&pf_info, enable);
-
-exit:
-    return ret;
-}
-
-static int __attribute__((unused)) set_feature_svlan_filter(struct net_device *netdev, bool enable)
-{
-    int ret = 0;
-#if 0 //TODO：STAG 暂时没有设置
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    ret = dpp_vport_vlan_qinq_en_set(en_dev->vport, enable);
-#endif
-    return ret;
-}
-
-int set_vf_qinq_tpid(struct net_device *netdev, uint16_t tpid)
-{
-    int ret = 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    union zxdh_msg msg = {0};
-
-    msg.payload.hdr.op_code = ZXDH_SET_TPID;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.tpid_cfg_msg.tpid = tpid;
-
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
-    if (ret != 0 || msg.reps.flag != ZXDH_REPS_SUCC)
-    {
-        LOG_ERR("pcieid:0x%x send msg to vfs set tpid: 0x%x failed! ret = %d.\n",
-                                                    en_dev->pcie_id,
-                                                    tpid,
-                                                    ret);
-        return -EINVAL;
-    }
-
-    return 0;
-}
-
-static int set_vf_vlan_strip(struct net_device *netdev, bool enable, uint8_t flag)
-{
-    int ret = 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    union zxdh_msg msg = {0};
-
-    msg.payload.hdr.op_code = ZXDH_VLAN_OFFLOAD_SET;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.hdr.pcie_id = en_dev->pcie_id;
-    msg.payload.vlan_strip_msg.enable = enable;
-    msg.payload.vlan_strip_msg.flag = flag;
-
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
-    if (ret != 0 || msg.reps.flag != ZXDH_REPS_SUCC)
-    {
-        LOG_ERR("pcieid:0x%x send msg to vfs set vlan strip enable:%s failed! ret = %d, flag = 0x%x\n",
-                                                    en_dev->pcie_id,
-                                                    enable ? "enable":"disable",
-                                                    ret,
-                                                    msg.reps.flag);
-        return -EINVAL;
-    }
-
-    return 0;
-}
-
-static int set_feature_vlan_strip(struct net_device *netdev, bool enable)
-{
-    int ret = 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        ret = dpp_vport_vlan_strip_set(&pf_info, enable);
-    }
-    else
-    {
-        ret = set_vf_vlan_strip(netdev, enable, VLAN_STRIP_MSG_TYPE);
-    }
-
-    return ret;
-}
-
-
-static int set_feature_qinq_strip(struct net_device *netdev, bool enable)
-{
-    int ret = 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        ret = dpp_vport_vlan_qinq_en_set(&pf_info, enable);
-    }
-    else
-    {
-        ret = set_vf_vlan_strip(netdev, enable, QINQ_STRIP_MSG_TYPE);
-    }
-
-    return ret;
-}
-
-
-static int32_t set_feature_lro(struct net_device *netdev, bool enable)
-{
-    uint32_t en_value = enable ? 1 : 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    DPP_PF_INFO_T pf_info = {0};
-    int32_t ret = 0;
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IPV4_TCP_ASSEMBLE, en_value);
-        if (ret != 0)
-        {
-            LOG_ERR("EGR_FLAG_IPV4_TCP_ASSEMBLE set failed: %d\n", ret);
-            return ret;
-        }
-        dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IPV6_TCP_ASSEMBLE, en_value);
-        if (ret != 0)
-        {
-            LOG_ERR("EGR_FLAG_IPV6_TCP_ASSEMBLE set failed: %d\n", ret);
-            return ret;
-        }
-    }
-    else
-    {
-        zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_IPV4_TCP_ASSEMBLE, en_value, 0);
-        if (ret != 0)
-        {
-            LOG_ERR("EGR_FLAG_IPV4_TCP_ASSEMBLE set failed: %d\n", ret);
-            return ret;
-        }
-        zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_IPV6_TCP_ASSEMBLE, en_value, 0);
-        if (ret != 0)
-        {
-            LOG_ERR("EGR_FLAG_IPV6_TCP_ASSEMBLE set failed: %d\n", ret);
-            return ret;
-        }
-    }
-
-    return zxdh_dtp_offload_set(en_dev, &pf_info);
-}
-
-int32_t zxdh_en_set_features(struct net_device *netdev, netdev_features_t wanted_features)
-{
-    int32_t ret = 0;
-    netdev_features_t oper_features = netdev->features;
-
-    zxdh_set_en_device(netdev, wanted_features);
-
-#define ZXDH_HANDLE_FEATURE(set_feature, handler) \
-    zxdh_handle_feature(netdev, &oper_features, wanted_features, set_feature, handler)
-
-    ret |= ZXDH_HANDLE_FEATURE(NETIF_F_RXCSUM, set_feature_rx_checksum);
-    ret |= ZXDH_HANDLE_FEATURE(NETIF_F_HW_CSUM, set_feature_tx_checksum);
-    ret |= ZXDH_HANDLE_FEATURE(NETIF_F_GSO_UDP_TUNNEL_CSUM, set_feature_vxlan_checksum);
-    ret |= ZXDH_HANDLE_FEATURE(NETIF_F_RXHASH, set_feature_rxhash);
-    ret |= ZXDH_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
-    ret |= ZXDH_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_vlan_strip);
-    ret |= ZXDH_HANDLE_FEATURE(NETIF_F_HW_VLAN_STAG_RX, set_feature_qinq_strip);
-
-    if (ret)
-    {
-        netdev->features = oper_features;
-        return -EINVAL;
-    }
-
-    return 0;
-}
-
-static uint32_t list_hw_addr_create(struct netdev_hw_addr_list *list, \
-                                    const uint8_t *addr, int32_t addr_len,  \
-                                    uint8_t addr_type, bool global,   \
-                                    bool sync)
-{
-    struct netdev_hw_addr *ha = NULL;
-
-    ha = kzalloc(sizeof(struct netdev_hw_addr), GFP_KERNEL);
-    if (ha == NULL)
-    {
-        LOG_ERR("Kzalloc struct netdev_hw_addr failed \n");
-        return 1;
-    }
-
-    /* 结构体赋值 */
-    memcpy(ha->addr, addr, addr_len);
-    ha->type       = addr_type;
-    ha->refcount   = 1; /* 引用计数 */
-    ha->global_use = global;
-    ha->synced     = sync ? 1 : 0;
-    ha->sync_cnt   = 0;
-    list_add_tail_rcu(&ha->list, &list->list);
-    list->count++; /* 链表节点加1 */
-
-    return 0;
-}
-
-static uint32_t list_hw_addr_del(struct netdev_hw_addr_list *list, struct netdev_hw_addr *ha)
-{
-    int32_t refcount = ha->refcount;
-
-    /* 引用的计数大于1，则不能删除此mac地址 */
-    if (--refcount)
-    {
-        return 1;
-    }
-
-    /* 从链表中删除此条目 */
-    list_del_rcu(&ha->list);
-
-    /* 释放ha结构体占用内存，rcu_head可以安全地释放ha占用的内存*/
-    kfree_rcu(ha, rcu_head);
-    list->count--;
-
-    return 0;
-}
-
-bool is_this_mac_exist(struct net_device *netdev, const uint8_t *addr)
-{
-    struct netdev_hw_addr *ha = NULL;
-    bool isexist = false;
-
-    /* 给net_device结构体上锁 */
-    netif_addr_lock_bh(netdev);
-
-    /* 判断此mac地址类型 */
-    if (is_unicast_ether_addr(addr))
-    {
-        /* 遍历单播mac地址链表 */
-        list_for_each_entry(ha, &netdev->uc.list, list)
-        {
-            /* 检查该单播地址链表中是否存在此mac，且此mac地址标志为单播 */
-            if ((!memcmp(ha->addr, addr, netdev->addr_len)) \
-                && (ha->type == NETDEV_HW_ADDR_T_UNICAST))
-            {
-                isexist = true;
-                goto out;
-            }
-        }
-    }
-    else
-    {
-        /* 遍历组播mac地址链表 */
-        list_for_each_entry(ha, &netdev->mc.list, list)
-        {
-            /* 检查该组播地址链表中是否存在此mac，且此mac地址类型为组播 */
-            if ((!memcmp(ha->addr, addr, netdev->addr_len)) \
-                && (ha->type == NETDEV_HW_ADDR_T_MULTICAST))
-            {
-                isexist = true;
-                goto out;
-            }
-        }
-    }
-
-out:
-    /* 给net_device结构体释放锁 */
-    netif_addr_unlock_bh(netdev);
-
-    return isexist;
-}
-
-/**
- * zxdh_dev_list_addr_add - 在地址链表中添加此mac地址
- * @netdev: 网络设备结构体
- * @addr: 要添加的mac地址
- * @addr_type: mac地址类型
- */
-int32_t zxdh_dev_list_addr_add(struct net_device *netdev, const uint8_t *addr)
-{
-    int32_t err = 0;
-
-    /* 给net_device结构体上锁 */
-    netif_addr_lock_bh(netdev);
-
-    /* 判断此mac地址类型 */
-    if (is_unicast_ether_addr(addr))
-    {
-        /* 将此mac地址添加到地址链表中 */
-        err = list_hw_addr_create(&netdev->uc, addr, netdev->addr_len, \
-                                  NETDEV_HW_ADDR_T_UNICAST, false, false);
-        if (err != 0)
-        {
-            LOG_ERR("list_hw_addr_create failed\n");
-        }
-    }
-    else
-    {
-        err = list_hw_addr_create(&netdev->mc, addr, netdev->addr_len, \
-                                 NETDEV_HW_ADDR_T_MULTICAST, false, false);
-        if (err != 0)
-        {
-            LOG_ERR("list_hw_addr_create failed\n");
-        }
-    }
-
-    /* 给net_device结构体释放锁 */
-    netif_addr_unlock_bh(netdev);
-
-    return err;
-}
-
-/**
- * zxdh_dev_list_addr_del - 在地址链表中删除此mac地址
- * @netdev: 网络设备结构体
- * @addr: 要删除的mac地址
- * @addr_type: mac地址类型
- */
-int32_t zxdh_dev_list_addr_del(struct net_device *netdev, const uint8_t *addr)
-{
-    struct netdev_hw_addr *ha = NULL;
-    int32_t err = 0;
-
-    /* 给net_device上锁 */
-    netif_addr_lock_bh(netdev);
-
-    if (is_unicast_ether_addr(addr))
-    {
-        /* 遍历单播mac地址链表 */
-        list_for_each_entry(ha, &netdev->uc.list, list)
-        {
-            /* 检查该单播地址链表中是否存在此mac，且此mac地址标志为单播 */
-            if ((!memcmp(ha->addr, addr, netdev->addr_len)) \
-                && (ha->type == NETDEV_HW_ADDR_T_UNICAST))
-            {
-                /* 从单播地址链表中删除此mac */
-                err = list_hw_addr_del(&netdev->uc, ha);
-                if (err != 0)
-                {
-                    LOG_ERR("list_hw_addr_del failed\n");
-                }
-                goto out;
-            }
-        }
-    }
-    else
-    {
-        /* 遍历组播mac地址链表 */
-        list_for_each_entry(ha, &netdev->mc.list, list)
-        {
-            /* 检查该组播地址链表中是否存在此mac，且此mac地址标志为组播 */
-            if ((!memcmp(ha->addr, addr, netdev->addr_len)) \
-                && (ha->type == NETDEV_HW_ADDR_T_MULTICAST))
-            {
-                /* 从组播地址链表中删除此mac */
-                err = list_hw_addr_del(&netdev->mc, ha);
-                if (err != 0)
-                {
-                    LOG_ERR("list_hw_addr_del failed\n");
-                }
-                goto out;
-            }
-        }
-    }
-
-out:
-    /* 给net_device结构体释放锁 */
-    netif_addr_unlock_bh(netdev);
-
-    return err;
-}
-
-#ifdef MAC_CONFIG_DEBUG
-int32_t zxdh_pf_dump_all_mac(struct zxdh_en_device *en_dev)
-{
-    MAC_VPORT_INFO *unicast_mac_arry   = NULL;
-    MAC_VPORT_INFO *multicast_mac_arry = NULL;
-    uint32_t current_unicast_num   = 0;
-    uint32_t current_multicast_num = 0;
-    int32_t err = 1;
-    int32_t i   = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    /* 开辟单播数组和组播数组*/
-    unicast_mac_arry = (MAC_VPORT_INFO *)kzalloc(sizeof(MAC_VPORT_INFO)*UNICAST_MAX_NUM, GFP_KERNEL);
-    if (unicast_mac_arry == NULL)
-    {
-        LOG_ERR("kzalloc unicast_mac_arry failed \n");
-        return err;
-    }
-
-    multicast_mac_arry = (MAC_VPORT_INFO *)kzalloc(sizeof(MAC_VPORT_INFO)*MULTICAST_MAX_NUM, GFP_KERNEL);
-    if (multicast_mac_arry == NULL)
-    {
-        LOG_ERR("kzalloc multicast_mac_arry failed \n");
-        goto out1;
-    }
-
-    /* 从NP中dump所有单播mac地址*/
-    err = dpp_unicast_mac_dump(&pf_info, unicast_mac_arry, &current_unicast_num);
-    if (err != 0)
-    {
-        LOG_ERR("dpp_unicast_mac_dump failed\n");
-        goto out2;
-    }
-
-    /* 从NP中dump所有组播mac地址*/
-    err = dpp_multicast_mac_dump(&pf_info, multicast_mac_arry, &current_multicast_num);
-    if (err != 0)
-    {
-        LOG_ERR("dpp_multicast_mac_dump failed\n");
-        goto out2;
-    }
-
-    for(i = 0; i < current_unicast_num; ++i)
-    {
-        LOG_INFO("unicast_mac_arry[%d].vport is %#x\n", i, unicast_mac_arry[i].vport);
-        LOG_INFO("unicast_mac_arry[%d].mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", i,  \
-                  unicast_mac_arry[i].addr[0], unicast_mac_arry[i].addr[1],         \
-                  unicast_mac_arry[i].addr[2], unicast_mac_arry[i].addr[3],         \
-                  unicast_mac_arry[i].addr[4], unicast_mac_arry[i].addr[5]);
-    }
-    for(i = 0; i < current_multicast_num; ++i)
-    {
-        LOG_INFO("multicast_mac_arry[%d].vport is %#x\n", i,  multicast_mac_arry[i].vport);
-        LOG_INFO("multicast_mac_arry[%d].mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", i,  \
-                 multicast_mac_arry[i].addr[0], multicast_mac_arry[i].addr[1],        \
-                 multicast_mac_arry[i].addr[2], multicast_mac_arry[i].addr[3],        \
-                 multicast_mac_arry[i].addr[4], multicast_mac_arry[i].addr[5]);
-    }
-
-out2:
-    if (multicast_mac_arry != NULL)
-    {
-        kfree(multicast_mac_arry);
-    }
-
-out1:
-    if (unicast_mac_arry != NULL)
-    {
-        kfree(unicast_mac_arry);
-    }
-
-    return err;
-}
-#endif /* MAC_CONFIG_DEBUG */
-
-int32_t unicast_mac_add(struct zxdh_en_device *en_dev, struct net_device *dev, \
-                        const uint8_t* addr, uint16_t flags)
-{
-    int32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    /* 判断目前所配置mac地址数量是否超过上限 */
-    if (en_dev->curr_unicast_num >= DEV_UNICAST_MAX_NUM-1)
-    {
-        LOG_ERR("curr_unicast_num is beyond maximum\n");
-        return -ENOSPC;
-    }
-
-    /* 遍历单播地址链表，判断是否存在此单播mac */
-    if (is_this_mac_exist(dev, addr))
-    {
-        LOG_DEBUG("Mac already exists\n");
-        if (!(flags & NLM_F_EXCL))
-        {
-            return 0;
-        }
-        return -EEXIST;
-    }
-
-    /* 如果待配置mac和本机mac相同，则不配置到NP中， 只将此mac添加到单播地址链表中 */
-    if (!memcmp(addr, dev->dev_addr, dev->addr_len))
-    {
-        goto out;
-    }
-
-    /* 将此mac地址配置到np中 */
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        err = dpp_add_mac(&pf_info, addr);
-        if (err != 0)
-        {
-            LOG_ERR("dpp_add_mac failed\n");
-            return err;
-        }
-    }
-    else
-    {
-        err = zxdh_vf_dpp_add_mac(en_dev, addr, FILTER_MAC);
-        if (err != 0)
-        {
-            LOG_ERR("zxdh_vf_dpp_add_mac failed\n");
-            return err;
-        }
-    }
-
-out:
-    /* 将此单播mac地址添加到地址链表中 */
-    err = zxdh_dev_list_addr_add(dev, addr);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_dev_list_addr_add failed\n");
-        return err;
-    }
-    en_dev->curr_unicast_num++;
-    LOG_DEBUG("curr_unicast_num is %d\n", en_dev->curr_unicast_num);
-    return err;
-}
-
-bool is_ipv6_mulicast_mac(const uint8_t *mac)
-{
-    return ((mac[0] == 0x33) && (mac[1] == 0x33));
-}
-
-int32_t multicast_mac_add(struct zxdh_en_device *en_dev, struct net_device *dev, \
-                          const uint8_t* addr, uint16_t flags)
-{
-    int32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (is_ipv6_mulicast_mac(addr))
-    {
-        LOG_ERR("invlaid ipv6 mac address\n");
-        return -EINVAL;
-    }
-
-    /* 遍历组播地址链表，判断是否存在此mac */
-    if (is_this_mac_exist(dev, addr))
-    {
-        LOG_DEBUG("Mac already exists\n");
-        if (!(flags & NLM_F_EXCL))
-        {
-            return 0;
-        }
-        return -EEXIST;
-    }
-
-    /* 将此组播mac地址配置到np中 */
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        err = dpp_multi_mac_add_member(&pf_info, addr);
-        if (err != 0)
-        {
-            if (err == DPP_RC_TABLE_RANGE_INVALID)
-            {
-                LOG_ERR("multicast mac is beyond 32\n");
-                return -ENOSPC;
-            }
-            LOG_ERR("dpp_multi_mac_add_member failed\n");
-            return err;
-        }
-    }
-    else
-    {
-        err = zxdh_vf_dpp_add_mac(en_dev, addr, FILTER_MAC);
-        if (err != 0)
-        {
-            if(err == DPP_RC_TABLE_RANGE_INVALID)
-            {
-                LOG_ERR("multicast mac is beyond 32\n");
-                return -ENOSPC;
-            }
-            LOG_ERR("zxdh_vf_dpp_add_mac failed\n");
-            return err;
-        }
-    }
-
-    /* 将此组播mac地址添加到地址链表中 */
-    err = zxdh_dev_list_addr_add(dev, addr);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_dev_list_addr_add failed\n");
-        return err;
-    }
-    return err;
-}
-
-int32_t unicast_mac_del(struct zxdh_en_device *en_dev, struct net_device *dev, const uint8_t* addr)
-{
-    int32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    /* 判断目前所配置mac地址数量是否小于0 */
-    if (en_dev->curr_unicast_num <= 0)
-    {
-        LOG_ERR("curr_unicast_num is less than 0\n");
-        return -ENOENT;
-    }
-
-    /* 遍历单播地址链表，判断是否存在此mac */
-    if(!is_this_mac_exist(dev, addr))
-    {
-        LOG_DEBUG("Mac is not exists\n");
-        return -ENOENT;
-    }
-
-    /* 如果待删除mac和本机mac相同，则不从NP中删除，只从链表中删除 */
-    if (!memcmp(addr, dev->dev_addr, dev->addr_len))
-    {
-       goto out;
-    }
-
-    /* 从np中删除此单播mac */
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        /* 此设备为PF */
-        err = dpp_del_mac(&pf_info, addr);
-        if (err != 0)
-        {
-            LOG_ERR("dpp_del_mac failed\n");
-            return err;
-        }
-        LOG_DEBUG("dpp_del_mac succeed\n");
-    }
-    else
-    {
-        /* 此设备为VF */
-        err = zxdh_vf_dpp_del_mac(en_dev, addr, FILTER_MAC, true);
-        if (err != 0)
-        {
-            LOG_ERR("zxdh_vf_dpp_del_mac failed\n");
-            return err;
-        }
-        LOG_DEBUG("zxdh_vf_dpp_del_mac succeed\n");
-    }
-
-out:
-    /* 从链表中删除单播mac */
-    err = zxdh_dev_list_addr_del(dev, addr);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_dev_list_addr_del failed\n");
-        return err;
-    }
-    en_dev->curr_unicast_num--;
-    LOG_DEBUG("curr_unicast_num is %d\n", en_dev->curr_unicast_num);
-    return err;
-}
-
-int32_t multicast_mac_del(struct zxdh_en_device *en_dev, struct net_device *dev, const uint8_t* addr)
-{
-    int32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (is_ipv6_mulicast_mac(addr))
-    {
-        LOG_ERR("invlaid ipv6 mac address\n");
-        return -EINVAL;
-    }
-
-    /* 遍历组播地址链表，判断是否存在此组播mac，如果不存在，则返回报错 */
-    if(!is_this_mac_exist(dev, addr))
-    {
-        LOG_DEBUG("Mac is not exists\n");
-        return -ENOENT;
-    }
-
-    /* 从np中删除此组播mac */
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        /* 此设备为PF */
-        err = dpp_multi_mac_del_member(&pf_info, addr);
-        if (err != 0)
-        {
-            LOG_ERR("dpp_multi_mac_del_member failed\n");
-            return err;
-        }
-        LOG_DEBUG("dpp_multi_mac_del_member succeed\n");
-    }
-    else
-    {
-        /* 此设备为VF */
-        err = zxdh_vf_dpp_del_mac(en_dev, addr, FILTER_MAC, true);
-        if (err != 0)
-        {
-            LOG_ERR("zxdh_vf_dpp_del_mac failed\n");
-            return err;
-        }
-    }
-
-    /* 从链表中删除组播mac */
-    err = zxdh_dev_list_addr_del(dev, addr);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_dev_list_addr_del failed\n");
-        return err;
-    }
-
-    return err;
-}
-
-static unsigned int mac_hash(struct zxdh_ipv6_mac_tbl *mac_tbl, const uint8_t *mac_addr)
-{
-    unsigned int mact_size_half = mac_tbl->ip6mact_size / 2;
-    uint32_t mac_part1 = (mac_addr[0] << 24) | (mac_addr[1] << 16) | (mac_addr[2] << 8) | mac_addr[3];
-    uint32_t mac_part2 = (mac_addr[4] << 8) | mac_addr[5];
-
-    uint32_t xor = mac_part1 ^ mac_part2;
-
-    return (jhash_1word(xor, 0) % mact_size_half);
-}
-
-int32_t zxdh_ip6mac_to_np(struct zxdh_en_device *en_dev, struct zxdh_ipv6_mac_tbl *ip6mac_tbl, const uint8_t *ip6mac, uint8_t action, bool need_lock)
-{
-    int32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    switch (action)
-    {
-        case ADD_IP6MAC:
-        {
-            if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-            { /* PF流程 */
-                if (need_lock)
-                {
-                    write_lock_bh(&ip6mac_tbl->lock);
-                }
-                /* 将此组播mac地址配置到np中 */
-                err = dpp_multi_mac_add_member(&pf_info, ip6mac);
-                if (err != 0)
-                {
-                    LOG_ERR("dpp_multi_mac_add_member failed, err:%d\n", err);
-                }
-                if (need_lock)
-                {
-                    write_unlock_bh(&ip6mac_tbl->lock);
-                }
-            }
-            else
-            { /* VF流程*/
-                err = zxdh_vf_dpp_add_ipv6_mac(en_dev, ip6mac);
-                if (err != 0)
-                {
-                    LOG_ERR("zxdh_vf_dpp_add_ipv6_mac failed, err:%d\n", err);
-                }
-            }
-            break;
-        }
-        case DEL_IP6MAC:
-        {
-            if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-            {/* PF流程 */
-                if (need_lock)
-                {
-                    write_lock_bh(&ip6mac_tbl->lock);
-                }
-                err = dpp_multi_mac_del_member(&pf_info, ip6mac);
-                if (err != 0)
-                {
-                    LOG_ERR("dpp_multi_mac_del_member failed, err:%d\n", err);
-                }
-                if (need_lock)
-                {
-                    write_unlock_bh(&ip6mac_tbl->lock);
-                }
-            }
-            else
-            {/* VF流程 */
-                err = zxdh_vf_dpp_del_ipv6_mac(en_dev, ip6mac);
-                if (err != 0)
-                {
-                    LOG_ERR("zxdh_vf_dpp_del_ipv6_mac failed, err:%d\n", err);
-                }
-            }
-            break;
-        }
-    }
-    return err;
-}
-
-int32_t zxdh_ip6mac_add(struct zxdh_en_device *en_dev, const uint32_t *addr6, const uint8_t *ip6mac)
-{
-    int32_t err = 0;
-    unsigned int mac_hash_val;
-    struct zxdh_ipv6_mac_tbl *ip6mac_tbl = en_dev->ops->get_ip6mac_tbl(en_dev->parent);
-    struct zxdh_ipv6_mac_entry *ce, *cte;
-
-    if (!ip6mac_tbl)
-    {
-        LOG_ERR("ip6mac_tbl is NULL\n");
-        return -ENXIO;
-    }
-
-    err = zxdh_ip6mac_to_np(en_dev, ip6mac_tbl, ip6mac, ADD_IP6MAC, TRUE);
-    if (err != 0)
-    {
-        return err;
-    }
-
-    mac_hash_val = mac_hash(ip6mac_tbl, ip6mac);
-    //如果没有报错，则说明MAC已经存在或成功存入NP
-    read_lock_bh(&ip6mac_tbl->lock);
-    list_for_each_entry(cte, &ip6mac_tbl->hash_list[mac_hash_val], list)
-    {
-        if (memcmp(cte->ipv6_mac, ip6mac, ETH_ALEN) == 0)
-        {//MAC已经存在
-            ce = cte;
-            refcount_inc(&ce->refcnt);
-            LOG_INFO("Increase Multicast MAC Address(%pM) refcnt:%d\n", ip6mac, refcount_read(&ce->refcnt));
-            read_unlock_bh(&ip6mac_tbl->lock);
-            return 0;
-        }
-    }
-    read_unlock_bh(&ip6mac_tbl->lock);
-
-    //成功新增MAC至NP，需要更新 ip6mac_tbl
-    write_lock_bh(&ip6mac_tbl->lock);
-    if (list_empty(&ip6mac_tbl->ip6mac_free_head))
-    {
-        write_unlock_bh(&ip6mac_tbl->lock);
-        err = zxdh_ip6mac_to_np(en_dev, ip6mac_tbl, ip6mac, DEL_IP6MAC, TRUE);
-        LOG_ERR("ip6mac_tbl overflow, can't add; del mac from NP, ret:%d\n",err);
-        return -ENOMEM;
-    }
-    ce = list_first_entry(&ip6mac_tbl->ip6mac_free_head, struct zxdh_ipv6_mac_entry, list);
-    list_del(&ce->list);
-    INIT_LIST_HEAD(&ce->list);
-    spin_lock_init(&ce->lock);
-    refcount_set(&ce->refcnt, 0);
-    list_add_tail(&ce->list, &ip6mac_tbl->hash_list[mac_hash_val]);
-    memcpy(ce->ipv6_mac, ip6mac, ETH_ALEN);
-    refcount_set(&ce->refcnt, 1);
-    write_unlock_bh(&ip6mac_tbl->lock);
-    LOG_INFO("Add New Multicast MAC Address: %pM, refcnt:%d\n", ip6mac, refcount_read(&ce->refcnt));
-
-    return 0;
-}
-
-int32_t zxdh_ip6mac_del(struct zxdh_en_device *en_dev, const uint32_t *addr6, const uint8_t *ip6mac)
-{
-    int32_t err = 0;
-    struct zxdh_ipv6_mac_tbl *ip6mac_tbl = en_dev->ops->get_ip6mac_tbl(en_dev->parent);
-    struct zxdh_ipv6_mac_entry *ce, *cte;
-    unsigned int mac_hash_val;
-    int32_t refcnt = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    if (!ip6mac_tbl)
-    {
-        LOG_ERR("ip6mac_tbl is NULL");
-        return -ENXIO;
-    }
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    mac_hash_val = mac_hash(ip6mac_tbl, ip6mac);
-
-    read_lock_bh(&ip6mac_tbl->lock);
-    list_for_each_entry(cte, &ip6mac_tbl->hash_list[mac_hash_val], list)
-    {
-        if (memcmp(cte->ipv6_mac, ip6mac, ETH_ALEN) == 0)
-        {//MAC存在
-            ce = cte;
-            read_unlock_bh(&ip6mac_tbl->lock);
-            goto found;
-        }
-    }
-    read_unlock_bh(&ip6mac_tbl->lock);
-    LOG_INFO("Don't Found Multicast MAC Address: %pM in Hash List\n", ip6mac);
-    return zxdh_ip6mac_to_np(en_dev, ip6mac_tbl, ip6mac, DEL_IP6MAC, TRUE);
-
-found:
-    write_lock_bh(&ip6mac_tbl->lock);
-    spin_lock_bh(&ce->lock);
-    if (!refcount_dec_and_test(&ce->refcnt))
-    {
-        LOG_INFO("Decrease Multicast MAC Address(%pM) refcnt:%d\n", ip6mac, refcount_read(&ce->refcnt));
-        spin_unlock_bh(&ce->lock);
-        write_unlock_bh(&ip6mac_tbl->lock);
-        return err;
-    }
-    //如果引用计数减到0
-    list_del(&ce->list);
-    INIT_LIST_HEAD(&ce->list);
-    list_add_tail(&ce->list, &ip6mac_tbl->ip6mac_free_head);
-    refcnt = refcount_read(&ce->refcnt);
-    spin_unlock_bh(&ce->lock);
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-    {   //VF设备需要先释放锁再发消息下表，因为PF侧会加锁
-        write_unlock_bh(&ip6mac_tbl->lock);
-        err = zxdh_ip6mac_to_np(en_dev, ip6mac_tbl, ip6mac, DEL_IP6MAC, FALSE);
-    }
-    else
-    {   //PF设备需要带锁下表
-        err = zxdh_ip6mac_to_np(en_dev, ip6mac_tbl, ip6mac, DEL_IP6MAC, FALSE);
-        write_unlock_bh(&ip6mac_tbl->lock);
-    }
-    LOG_INFO("Del Multicast MAC Address: %pM Completely, refcnt:%d, np ret:%d\n", ip6mac, refcnt, err);
-    return err;
-}
-
-int32_t zxdh_en_set_vepa(struct zxdh_en_device *en_dev, bool setting)
-{
-    struct zxdh_vf_item *vf_item = NULL;
-    bool vepa = false;
-    uint16_t vf_idx = 0;
-    int32_t ret = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    vepa = en_dev->ops->get_vepa(en_dev->parent);
-    if (setting == vepa)
-    {
-        LOG_ERR("vport(0x%x) is now %s mode\n", en_dev->vport, vepa?"vepa":"veb");
-        return 0;
-    }
-
-    en_dev->ops->set_vepa(en_dev->parent, setting);
-    ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VEPA_EN_OFF, (uint32_t)setting);
-    if (ret != 0)
-    {
-        LOG_ERR("Failed to setup vport(0x%x) %s mode, ret: %d\n", en_dev->vport, setting?"vepa":"veb", ret);
-        return ret;
-    }
-
-    for (vf_idx = 0; vf_idx < ZXDH_VF_NUM_MAX; vf_idx++)
-    {
-        vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx);
-        if (IS_ERR_OR_NULL(vf_item))
-        {
-            break;
-        }
-
-        if (vf_item->is_probed)
-        {
-            pf_info.vport = vf_item->vport;
-            ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VEPA_EN_OFF, (uint32_t)setting);
-            if (ret != 0)
-            {
-                LOG_ERR("Failed to setup vport(0x%x) %s mode, ret: %d\n", vf_item->vport, setting?"vepa":"veb", ret);
-                return ret;
-            }
-            LOG_INFO("Configure vport(0x%x) to %s mode\n", vf_item->vport, setting?"vepa":"veb");
-        }
-    }
-
-    LOG_INFO("Configure vport(0x%x) to %s mode\n", en_dev->vport, setting?"vepa":"veb");
-
-    return ret;
-}
-
-#ifdef HAVE_FDB_OPS
-#if defined(HAVE_NDO_FDB_ADD_EXTACK)
-static int zxdh_en_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
-                                         struct net_device *dev, const unsigned char *addr,
-                                         u16 vid, u16 flags, struct netlink_ext_ack *extack)
-#elif defined(HAVE_NDO_FDB_ADD_VID)
-static int zxdh_en_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
-                               struct net_device *dev, const unsigned char *addr,
-                               u16 vid, u16 flags)
-#elif defined(HAVE_NDO_FDB_ADD_NLATTR)
-static int zxdh_en_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
-                               struct net_device *dev, const unsigned char *addr,
-                               u16 flags)
-#elif defined(USE_CONST_DEV_UC_CHAR)
-static int zxdh_en_ndo_fdb_add(struct ndmsg *ndm, struct net_device *dev,
-                               const unsigned char *addr, u16 flags)
-#else
-static int zxdh_en_ndo_fdb_add(struct ndmsg *ndm, struct net_device *dev,
-                               unsigned char *addr, u16 flags)
-#endif
-{
-    struct zxdh_en_priv *en_priv  = netdev_priv(dev);
-    struct zxdh_en_device *en_dev = &en_priv->edev; /*aux层net_device的私有结构体 */
-    int32_t err = 0;
-
-#ifdef MAC_CONFIG_DEBUG
-    LOG_DEBUG("vport is %#x\n", en_dev->vport);
-    LOG_DEBUG("addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", \
-            addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
-    LOG_DEBUG("ndm_state is %u\n", ndm->ndm_state);
-#endif /* MAC_CONFIG_DEBUG */
-
-    /* 检查这个设备的ndm状态是否是静态的 */
-    if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT))
-    {
-        LOG_ERR("FDB only supports static addresses\n");
-        return -EINVAL;
-    }
-
-    /* 判断mac地址是否全0 */
-    if (is_zero_ether_addr(addr))
-    {
-        LOG_ERR("Invalid mac\n");
-        return -EINVAL;
-    }
-
-    if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
-    {
-        err = unicast_mac_add(en_dev, dev, addr, flags);
-        if (err != 0)
-        {
-            LOG_ERR("unicast_mac_add failed");
-            return err;
-        }
-    }
-    else if (is_multicast_ether_addr(addr))
-    {
-        err = multicast_mac_add(en_dev, dev, addr, flags);
-        if (err != 0)
-        {
-            LOG_ERR("multicast_mac_add failed");
-            return err;
-        }
-    }
-    else
-    {
-        err = -EINVAL;
-    }
-
-#ifdef MAC_CONFIG_DEBUG
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        err = zxdh_pf_dump_all_mac(en_dev);
-        if (err != 0)
-        {
-            LOG_INFO("zxdh_pf_dump_all_mac failed\n");
-            return err;
-        }
-    }
-#endif /* MAC_CONFIG_DEBUG */
-
-    LOG_DEBUG("zxdh_en_ndo_fdb_add end\n");
-    return err;
-}
-
-#ifdef HAVE_NDO_FEATURES_CHECK
-static netdev_features_t zxdh_en_features_check(struct sk_buff *skb, struct net_device *dev,
-                                                           netdev_features_t features)
-{
-    return features;
-}
-#endif /* HAVE_NDO_FEATURES_CHECK */
-
-#ifdef USE_CONST_DEV_UC_CHAR
-#ifdef HAVE_NDO_FDB_ADD_VID
-static int zxdh_en_ndo_fdb_del(struct ndmsg *ndm, struct nlattr **nla, struct net_device *dev,
-                             const unsigned char *addr, u16 vid)
-#else
-static int zxdh_en_ndo_fdb_del(struct ndmsg *ndm, struct net_device *dev,
-                               const unsigned char *addr)
-#endif
-#else
-#ifdef HAVE_NDO_FDB_ADD_VID
-static int zxdh_en_ndo_fdb_del(struct ndmsg *ndm, struct net_device *dev,
-                               unsigned char *addr, u16 vid)
-#else
-static int zxdh_en_ndo_fdb_del(struct ndmsg *ndm, struct net_device *dev,
-                               unsigned char *addr)
-#endif
-#endif
-{
-    struct zxdh_en_priv *en_priv  = netdev_priv(dev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t err = 0;
-
-#ifdef MAC_CONFIG_DEBUG
-    LOG_DEBUG("the vport is %#x",en_dev->vport);
-    LOG_DEBUG("the addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",\
-            addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
-    LOG_DEBUG("ndm_state is %u,\n", ndm->ndm_state);
-#endif /* MAC_CONFIG_DEBUG */
-
-    /* 检查这个设备的ndm状态是否是静态的 */
-    if (!(ndm->ndm_state & NUD_PERMANENT))
-    {
-        LOG_ERR("FDB only supports static addresses\n");
-        return -EINVAL;
-    }
-
-    /* 地址是否全为0 */
-    if (is_zero_ether_addr(addr))
-    {
-        LOG_ERR("Invalid mac address\n");
-        return -EINVAL;
-    }
-
-    /* 根据mac地址类型，对相对应地址链表做删除操作 */
-    if (is_unicast_ether_addr(addr))
-    {
-        err = unicast_mac_del(en_dev, dev, addr);
-        if (err != 0)
-        {
-            LOG_ERR("unicast_mac_del failed\n");
-            return err;
-        }
-    }
-    else if (is_multicast_ether_addr(addr))
-    {
-        err = multicast_mac_del(en_dev, dev, addr);
-        if (err != 0)
-        {
-            LOG_ERR("multicast_mac_del failed\n");
-            return err;
-        }
-    }
-    else
-    {
-        return -EINVAL;
-    }
-
-#ifdef MAC_CONFIG_DEBUG
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        /*先dump所有mac地址*/
-        err = zxdh_pf_dump_all_mac(en_dev);
-        if (err != 0)
-        {
-            LOG_ERR("zxdh_pf_dump_all_mac failed\n");
-            return err;
-        }
-    }
-#endif /* MAC_CONFIG_DEBUG */
-
-    LOG_DEBUG("zxdh_en_ndo_fdb_del end\n");
-    return err;
-}
-
-#ifdef HAVE_BRIDGE_ATTRIBS
-#if defined(HAVE_NDO_BRIDGE_SETLINK_EXTACK)
-static int zxdh_en_ndo_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
-                                      u16 flags, struct netlink_ext_ack *extack)
-#elif defined(HAVE_NDO_BRIDGE_SET_DEL_LINK_FLAGS)
-static int zxdh_en_ndo_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, u16 flags)
-#else
-static int zxdh_en_ndo_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh)
-#endif
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(dev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct nlattr *attr = NULL;
-    struct nlattr *br_spec = NULL;
-    int32_t rem = 0;
-    uint16_t mode = BRIDGE_MODE_UNDEF;
-    bool setting = false;
-
-    if(en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF)
-    {
-        return -EOPNOTSUPP;
-    }
-
-    br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
-    if (br_spec == NULL)
-    {
-        return -EINVAL;
-    }
-
-    nla_for_each_nested(attr, br_spec, rem)
-    {
-        if (nla_type(attr) != IFLA_BRIDGE_MODE)
-        {
-            continue;
-        }
-
-        if (nla_len(attr) < sizeof(mode))
-        {
-            return -EINVAL;
-        }
-
-        mode = nla_get_u16(attr);
-        if (mode > BRIDGE_MODE_VEPA)
-        {
-            return -EINVAL;
-        }
-        break;
-    }
-
-    if (mode == BRIDGE_MODE_UNDEF)
-    {
-        return -EINVAL;
-    }
-
-    setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0;
-
-    return zxdh_en_set_vepa(en_dev, setting);
-}
-
-#ifdef HAVE_NDO_BRIDGE_GETLINK_NLFLAGS
-static int zxdh_en_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
-                                      struct net_device *dev, u32 __always_unused filter_mask,
-                                      int nlflags)
-#elif defined(HAVE_BRIDGE_FILTER)
-static int zxdh_en_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
-                                      struct net_device *dev, u32 __always_unused filter_mask)
-#else
-static int zxdh_en_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
-                                      struct net_device *dev)
-#endif /* NDO_BRIDGE_STUFF */
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(dev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint8_t mode = 0;
-    bool vepa = false;
-
-    vepa = en_dev->ops->get_vepa(en_dev->parent);
-    mode = vepa ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
-
-    return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode, 0, 0, nlflags, filter_mask, NULL);
-}
-#endif /* HAVE_BRIDGE_ATTRIBS */
-#endif /* HAVE_FDB_OPS */
-
-static int32_t zxdh_pf_notify_vf_reset(struct zxdh_en_device *en_dev, int vf_idx)
-{
-    int32_t retval = 0;
-    union zxdh_msg msg = {0};
-
-    msg.payload.hdr_vf.op_code = ZXDH_SET_VF_RESET;
-    msg.payload.hdr_vf.dst_pcie_id = FIND_VF_PCIE_ID(en_dev->pcie_id, vf_idx);
-
-    retval = zxdh_send_command_to_specify(en_dev, MODULE_PF_BAR_MSG_TO_VF, &msg, &msg);
-    if(retval != 0)
-    {
-        LOG_ERR("zxdh_send_command_to_vf failed: %d\n", retval);
-    }
-    return retval;
-}
-
-static int32_t zxdh_pf_notify_vf_set_link_state(struct zxdh_en_device *en_dev, int vf_idx, bool link_up)
-{
-    int32_t retval = 0;
-    uint16_t func_no = 0;
-    uint16_t pf_no = FIND_PF_ID(en_dev->pcie_id);
-    uint8_t link_info = 0;
-    uint8_t link_up_val = 0;
-    uint8_t phyport_val = 0;
-    union zxdh_msg msg = {0};
-
-    msg.payload.hdr_to_agt.op_code = AGENT_DEV_STATUS_NOTIFY;
-    msg.payload.hdr_to_agt.pcie_id = en_dev->pcie_id;
-
-    func_no = GET_FUNC_NO(pf_no, vf_idx);
-    LOG_DEBUG("vf_idx:%d, func_no=0x%x\n",vf_idx,func_no);
-    msg.payload.pcie_msix_msg.func_no[msg.payload.pcie_msix_msg.num++] = func_no;
-    if(en_dev->ops->is_bond(en_dev->parent))
-    {
-        link_up_val = link_up ? 1 : 0;
-        phyport_val = en_dev->ops->get_pf_phy_port(en_dev->parent);
-        link_info = (phyport_val & 0x0F) << 4 | (link_up_val & 0x0F);
-        LOG_DEBUG("phyport and link_up need write to VQM, val: 0x%x\n", link_info);
-        en_dev->ops->set_vf_link_info(en_dev->parent, vf_idx, link_info);
-    }
-    else
-    {
-        en_dev->ops->set_vf_link_info(en_dev->parent, vf_idx, link_up ? 1 : 0);
-    }
-    LOG_DEBUG("msg.pcie_msix_msg.num:%d\n", msg.payload.pcie_msix_msg.num);
-    retval = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (retval != 0)
-    {
-        LOG_ERR("failed to update VF link info\n");
-    }
-    return retval;
-}
-
-static int32_t zxdh_pf_set_vf_link_state(struct zxdh_en_device *en_dev, int vf_idx, int link_status)
-{
-    int32_t retval   = 0;
-    struct zxdh_vf_item *vf_item = NULL;
-    bool pf_link_up = en_dev->ops->get_pf_link_up(en_dev->parent);
-
-    vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx);
-    switch (link_status)
-    {
-        case IFLA_VF_LINK_STATE_AUTO:
-            LOG_DEBUG("[SET_VF_LINK_STATE]--NDO set VF %d link state auto\n", vf_idx);
-            vf_item->link_forced = FALSE;
-            vf_item->link_up = pf_link_up;
-            break;
-        case IFLA_VF_LINK_STATE_ENABLE:
-            LOG_DEBUG("[SET_VF_LINK_STATE]--NDO set VF %d link state enable\n", vf_idx);
-            vf_item->link_forced = TRUE;
-            vf_item->link_up = TRUE;
-            break;
-        case IFLA_VF_LINK_STATE_DISABLE:
-            LOG_DEBUG("[SET_VF_LINK_STATE]--NDO set VF %d link state disable\n", vf_idx);
-            vf_item->link_forced = TRUE;
-            vf_item->link_up = FALSE;
-            break;
-        default:
-            LOG_ERR("[SET_VF_LINK_STATE]--NDO set VF %d - invalid link status %d\n", vf_idx, link_status);
-            return -EINVAL;
-    }
-    LOG_DEBUG("vf_item->is_probed: %s\n", vf_item->is_probed?"TRUE":"FALSE");
-    if(vf_item->is_probed)
-    {
-        /* Notify the VF of its new link state */
-        retval = zxdh_pf_notify_vf_set_link_state(en_dev, vf_idx, vf_item->link_up);
-        if (0 != retval)
-        {
-            LOG_ERR("[SET_VF_LINK_STATE]--Failed to set VF %d link state %d\n", vf_idx, vf_item->link_up);
-            return retval;
-        }
-    }
-    return retval;
-}
-
-int zxdh_en_ndo_set_vf_link_state(struct net_device *netdev, int vf_idx, int link_status)
-{
-    int num_vfs = 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct pci_dev *pdev = NULL;
-    struct dh_core_dev *dh_dev = NULL;
-
-    dh_dev = en_dev->parent;
-    pdev = en_dev->ops->get_pdev(dh_dev);
-    num_vfs = pci_num_vf(pdev);
-    if ((vf_idx < 0) || (vf_idx >= num_vfs))
-    {
-        LOG_ERR("[SET_VF_LINK_STATE]--NDO set VF link - invalid VF idx: %d\n", vf_idx);
-        return -EINVAL;
-    }
-    return zxdh_pf_set_vf_link_state(en_dev, vf_idx, link_status);
-}
-
-static int32_t zxdh_pf_set_vf_port_vlan(struct zxdh_en_device *en_dev, int vf_idx, u16 vid, u8 qos, uint16_t vlan_proto)
-{
-    int32_t retval   = 0;
-    struct zxdh_vf_item *vf_item = NULL;
-    union zxdh_msg msg = {0};
-    DPP_PF_INFO_T pf_info = {0};
-
-    /* 获取pf本地保存的vf变量*/
-    vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx);
-    if(!vf_item->is_probed)
-    {
-        LOG_DEBUG("vf %d is not probed.\n", vf_idx);
-        return -EINVAL;
-    }
-
-    if (vf_item->vlan == vid)
-    {
-        return 0;
-    }
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = vf_item->vport;
-    if (vid)
-    {
-        /* vf端口Vlan strip开启*/
-        retval = dpp_vport_vlan_strip_set(&pf_info, 1);
-        if (retval != 0)
-        {
-            LOG_ERR("dpp_vport_vlan_strip_set failed, retval: %d\n", retval);
-            return retval;
-        }
-        /* 将vlan_id add到表项中*/
-        retval = dpp_vport_vlan_filter_en_set(&pf_info, 1);
-        if (retval != 0)
-        {
-            LOG_ERR("dpp_vport_vlan_filter_en_set failed, retval: %d\n", retval);
-            return retval;
-        }
-
-        retval = dpp_add_vlan_filter(&pf_info, vid);
-        if (0 != retval)
-        {
-            LOG_ERR("failed to add vlan: %d\n",vid);
-            return retval;
-        }
-    }
-    else
-    {
-        /* vf端口vlan strip关闭*/
-        retval = dpp_vport_vlan_strip_set(&pf_info, 0);
-        if (retval != 0)
-        {
-            LOG_ERR("dpp_vport_vlan_strip_set failed, retval: %d\n", retval);
-            return retval;
-        }
-        /* 将Vlan_id 从表项中kill*/
-        retval = dpp_vport_vlan_filter_en_set(&pf_info, 0);
-        if (retval != 0)
-        {
-            LOG_ERR("dpp_vport_vlan_filter_en_set failed, retval: %d\n", retval);
-            return retval;
-        }
-
-        retval = dpp_vlan_filter_init(&pf_info);
-        if (retval != 0)
-        {
-            LOG_ERR("dpp_vlan_filter_init failed: %d\n", retval);
-            return retval;
-        }
-    }
-
-    msg.payload.hdr_vf.op_code = ZXDH_PF_SET_VF_VLAN;
-    msg.payload.hdr_vf.dst_pcie_id = FIND_VF_PCIE_ID(en_dev->pcie_id, vf_idx);
-
-    msg.payload.vf_vlan_msg.vlan_id = vid;
-    msg.payload.vf_vlan_msg.qos = qos;
-    msg.payload.vf_vlan_msg.protocl = vlan_proto;
-    msg.payload.vf_vlan_msg.vf_idx = vf_idx;
-
-    retval = zxdh_send_command_to_specify(en_dev, MODULE_PF_BAR_MSG_TO_VF, &msg, &msg);
-    if(retval != 0)
-    {
-        LOG_ERR("zxdh_send_command_to_vf failed: %d\n", retval);
-        return retval;
-    }
-
-    /* 更新pf本地的vf vlan信息，用于ip link show显示*/
-    vf_item->vlan = vid;
-    vf_item->qos = qos;
-    return retval;
-}
-
-
-int zxdh_en_ndo_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
-{
-    struct  zxdh_en_priv *en_priv  = netdev_priv(netdev);
-    struct  zxdh_en_device *en_dev = &en_priv->edev;
-    struct  zxdh_vf_item *vf_item  = NULL;
-    int32_t retval                 = 0;
-    bool    delete_flag            = true;
-    uint8_t *addr                  = NULL;
-    uint8_t i                      = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_id);
-    if (IS_ERR_OR_NULL(vf_item))
-    {
-        LOG_ERR("Failed to get vf_item, vf_id:%d\n", vf_id);
-        return PTR_ERR(vf_item);
-    }
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = vf_item->vport;
-
-    if (is_multicast_ether_addr(mac))
-    {
-        LOG_ERR("Invalid Ethernet address %pM for VF %d\n", mac, vf_id);
-        return -EINVAL;
-    }
-
-    if (ether_addr_equal(vf_item->mac, mac))
-    {
-        LOG_INFO("[SET_VF_MAC]--already using mac address %pM\n", mac);
-        return retval;
-    }
-
-    if (is_zero_ether_addr(mac))
-    {
-        eth_zero_addr(vf_item->mac);
-        vf_item->pf_set_mac = false;
-        en_dev->ops->set_vf_mac(en_dev->parent, mac, vf_id);
-        eth_zero_addr(vf_item->vf_mac_info.unicast_mac[0]);
-        goto vf_reset;
-    }
-
-    for (i = 1; i < DEV_UNICAST_MAX_NUM; ++i)
-    {
-        addr = vf_item->vf_mac_info.unicast_mac[i];
-        if (!memcmp(vf_item->mac, addr, netdev->addr_len))
-        {
-            delete_flag = false;
-        }
-    }
-
-    if (delete_flag)
-    {
-        if (!is_zero_ether_addr(vf_item->mac))
-        {
-            retval = dpp_del_mac(&pf_info, vf_item->mac);
-            if (retval != 0)
-            {
-                LOG_ERR("delete vf old mac in NP failed.\n");
-                return retval;
-            }
-        }
-    }
-
-    vf_item->pf_set_mac = true;
-    en_dev->ops->set_vf_mac(en_dev->parent, mac, vf_id);
-    ether_addr_copy(vf_item->vf_mac_info.unicast_mac[0], mac);
-    ether_addr_copy(vf_item->mac, mac);
-    LOG_INFO("[SET_VF_MAC]--setting MAC %pM on VF %d\n", mac, vf_id);
-
-vf_reset:
-    if (vf_item->is_probed)
-    {
-        retval = zxdh_pf_notify_vf_reset(en_dev, vf_id);
-        if(retval != 0)
-        {
-            LOG_ERR("zxdh_pf_notify_vf_reset failed: %d\n", retval);
-        }
-    }
-
-    return retval;
-}
-
-#ifdef IFLA_VF_VLAN_INFO_MAX
-int zxdh_en_ndo_set_vf_port_vlan(struct net_device *netdev, int vf_id,
-                                               u16 vlan_id, u8 qos, __be16 vlan_proto)
-#else
-int zxdh_en_ndo_set_vf_port_vlan(struct net_device *netdev, int vf_id, u16 vlan_id, u8 qos)
-#endif /* IFLA_VF_VLAN_INFO_MAX */
-{
-    int num_vfs = 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct pci_dev *pdev = NULL;
-    struct dh_core_dev *dh_dev = NULL;
-
-    /* Comparing with the mellnox network card, it only supports the configuration of cvlan*/
-    if (vlan_proto != htons(ETH_P_8021Q))
-    {
-        return -EPROTONOSUPPORT;
-    }
-    dh_dev = en_dev->parent;
-    pdev = en_dev->ops->get_pdev(dh_dev);
-    num_vfs = pci_num_vf(pdev);
-    if ((vf_id < 0) || (vf_id >= num_vfs))
-    {
-        LOG_ERR("[SET+VF_VLAN]--NDO set VF vlan - invalid VF idx: %d\n", vf_id);
-        return -EINVAL;
-    }
-    return zxdh_pf_set_vf_port_vlan(en_dev, vf_id, vlan_id, qos, vlan_proto);
-}
-
-int zxdh_en_ndo_set_vf_bw(struct net_device *netdev, int vf_id, int min_tx_rate, int max_tx_rate)
-{
-    return 0;
-}
-
-int zxdh_en_ndo_get_vf_config(struct net_device *netdev, int vf_idx, struct ifla_vf_info *ivi)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_vf_item *vf_item = NULL;
-
-    vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx);
-    if (IS_ERR_OR_NULL(vf_item))
-    {
-        LOG_ERR("Failed to get vf_item, vf_idx:%d\n", vf_idx);
-        return PTR_ERR(vf_item);
-    }
-
-    ivi->vf = vf_idx;
-
-    ether_addr_copy(ivi->mac, vf_item->mac);
-
-#ifdef HAVE_NDO_SET_VF_MIN_MAX_TX_RATE
-    ivi->max_tx_rate = vf_item->max_tx_rate;
-    ivi->min_tx_rate = vf_item->min_tx_rate;
-#else
-    ivi->tx_rate = vf_item->max_tx_rate;
-#endif
-
-    ivi->vlan = vf_item->vlan;
-    ivi->qos = vf_item->qos;
-
-#ifdef HAVE_NDO_SET_VF_LINK_STATE
-    if (vf_item->link_forced == false)
-    {
-        ivi->linkstate = IFLA_VF_LINK_STATE_AUTO;
-    }
-    else if (vf_item->link_up == true)
-    {
-        ivi->linkstate = IFLA_VF_LINK_STATE_ENABLE;
-    }
-    else
-    {
-        ivi->linkstate = IFLA_VF_LINK_STATE_DISABLE;
-    }
-#endif
-
-#ifdef HAVE_VF_SPOOFCHK_CONFIGURE
-    ivi->spoofchk = vf_item->spoofchk;
-#endif
-
-#ifdef HAVE_NDO_SET_VF_TRUST
-    ivi->trusted = vf_item->trusted;
-#endif
-
-    return 0;
-}
-
-int zxdh_en_ndo_set_vf_spoofchk(struct net_device *netdev, int vf_idx, bool enable)
-{
-    int ret = 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_vf_item *vf_item = NULL;
-    DPP_PF_INFO_T pf_info = {0};
-
-    vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx);
-    if (IS_ERR_OR_NULL(vf_item))
-    {
-        LOG_ERR("Failed to get vf_item, vf_idx:%d\n", vf_idx);
-        return PTR_ERR(vf_item);
-    }
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = vf_item->vport;
-    vf_item->spoofchk = enable;
-    LOG_INFO("vf %d spoof check is %s\n", vf_idx, vf_item->spoofchk? "on" : "off");
-    if (vf_item->is_probed)
-    {
-        ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_SPOOFCHK_EN_OFF, enable);
-        if (0 != ret)
-        {
-            LOG_ERR("[SET_VF_SPOOFCHK]--Failed to set vf %d spookchk %s\n", vf_idx, enable ? "on" : "off");
-            return ret;
-        }
-    }
-    return ret;
-}
-
-#ifdef HAVE_NDO_SET_VF_TRUST
-int zxdh_en_ndo_set_vf_trust(struct net_device *netdev, int vf_idx, bool setting)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_vf_item *vf_item = NULL;
-    DPP_PF_INFO_T pf_info = {0};
-
-    vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx);
-    if (IS_ERR_OR_NULL(vf_item))
-    {
-        LOG_ERR("Failed to get vf_item, vf_idx:%d\n", vf_idx);
-        return PTR_ERR(vf_item);
-    }
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = vf_item->vport;
-    vf_item->trusted = setting;
-    LOG_INFO("VF %u is now %strusted\n", vf_idx, setting ? "" : "un");
-    if (vf_item->is_probed && !vf_item->trusted)
-    {
-        LOG_DEBUG("vport[0x%x] promisc and allmulti off\n", vf_item->vport);
-        vf_item->promisc = false;
-        vf_item->mc_promisc = false;
-        dpp_vport_uc_promisc_set(&pf_info, vf_item->promisc);
-        dpp_vport_mc_promisc_set(&pf_info, vf_item->mc_promisc);
-    }
-
-    return 0;
-}
-#endif
-
-int zxdh_en_ndo_set_tx_maxrate(struct net_device *netdev, int qid, uint32_t max_rate)
-{
-    int rtn = 0;
-    zxdh_plcr_rate_limit_paras rate_limit_paras;
-
-    struct zxdh_en_priv   *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev  = &en_priv->edev;
-    struct dh_core_dev    *dh_dev  = en_dev->parent;
-    struct zxdh_pf_device *pf_dev  = dh_core_priv(dh_dev->parent);
-
-    PLCR_FUNC_DBG_ENTER();
-
-    /*1. 入参检测：队列号不能超过vf下实际的队列数*/
-    if (qid >= en_dev->curr_queue_pairs)
-    {
-        LOG_ERR("zxdh_en_ndo_set_tx_maxrate : invalid parameter qid=%d\n", qid);
-        return -EINVAL;
-    }
-#if 0
-    if (!en_dev->link_up)
-    {
-        LOG_ERR("[EN SET TX MAXRATE]--PF is not link up.\n");
-        return -EINVAL;
-    }
-    link_speed = en_dev->link_speed;
-#endif
-
-    rate_limit_paras.req_type  = E_RATE_LIMIT_REQ_QUEUE_BYTE;
-    rate_limit_paras.direction = E_RATE_LIMIT_TX;
-    rate_limit_paras.mode      = E_RATE_LIMIT_BYTE ;
-    rate_limit_paras.max_rate  = max_rate;
-    rate_limit_paras.min_rate  = 0;
-    rate_limit_paras.queue_id  = qid;
-    rate_limit_paras.vf_idx    = PLCR_INVALID_PARAM;
-    rate_limit_paras.vfid      = PLCR_INVALID_PARAM;
-    rate_limit_paras.group_id  = PLCR_INVALID_PARAM;
-
-    rtn = zxdh_plcr_unified_set_rate_limit(pf_dev, &rate_limit_paras);
-    PLCR_COMM_ASSERT(rtn);
-
-    PLCR_LOG_INFO("The maxrate of tx-%d has been set to %dMbit/s\n", qid, max_rate);
-
-    return rtn;
-}
-
-/**-------------------------------------------------------------------------------------------------------------------@n
- * 功能详述:
- *     - zxdh_en_ndo_set_vf_rate函数属于接口函数, 其功能是:
- *     - 设置vf端口发送方向，最大速率和最小保证速率
- *     - 该接口会挂接到内核的钩子上，函数声明是固定的
- *
- * 基于plcr的端口限速背景：
- *     - 1.一级flowid与vqm的2K个（接收和发送）队列是一一映射的
- *     - 2.二级flow id与vf num的映射关系
- *         端口限速，需要将vf下的发送队列（即一级flow id）映射到二级flowid
- *         二级flow id的资源是4K，dpu限制vf数量是1K，即二级flow id数量 > vf数量
- *         所以规定固定的映射关系：二级flow id前1K <---> 与1K个vf（发送）一一对应
- *         下面的链接整理了pf下vf转换成全局vf（0-1023）的原理
- *         https://i.zte.com.cn/#/space/4e62cb2b730540ff8721c1a8552b2356/wiki/page/ff8178f1304e45dc9457e92ff196cce5/view
- *     - 3.vf限速的设置
- *         项目对vf提出了最小保证带宽的需求；
- *         二级CAR的限速模板使用：双速率，三色算法，色敏模式
- *     - 4.创建vf的其它考虑
- *         参考mlx的做法，vf创建之后，默认关联到vf组0（注意：>>>>>>>>先交付vf端口限速的需求，这一步可以暂时不实现<<<<<<<<）；
- *         vf创建之后，用户设置限速才会调用到这里，用户不设置限速，vf（二级flow id）就不用关联限速模板
- *
- * 参数概述:
- *     - netdev      : 网络设备结构体指针
- *     - vf_id       ：pf内vf的编号（从0开始）
- *     - min_tx_rate : 最小保证速率
- *     - max_tx_rate : 最大速率
- *     - 返回值类型是INT32, 含义是: 错误码，正确时为S_OK
- *
- * 引用(类变量,外部变量,接口函数):
- *     - 无
- *
- * 注意：该函数挂接到pf的钩子上，只在pf下执行
- *--------------------------------------------------------------------------------------------------------------------*/
-int zxdh_en_ndo_set_vf_rate(struct net_device *netdev, int vf_id, int min_tx_rate, int max_tx_rate)
-{
-    int rtn;
-    zxdh_plcr_rate_limit_paras rate_limit_paras;
-
-    struct zxdh_en_priv   *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev  = &en_priv->edev;
-    struct dh_core_dev    *dh_dev  = en_dev->parent;
-    struct zxdh_pf_device *pf_dev  = dh_core_priv(dh_dev->parent);
-
-    PLCR_FUNC_DBG_ENTER();
-
-    rate_limit_paras.req_type  = E_RATE_LIMIT_REQ_VF_BYTE;
-    rate_limit_paras.direction = E_RATE_LIMIT_TX;
-    rate_limit_paras.mode      = E_RATE_LIMIT_BYTE ;
-    rate_limit_paras.max_rate  = max_tx_rate;
-    rate_limit_paras.min_rate  = min_tx_rate;
-    rate_limit_paras.queue_id  = PLCR_INVALID_PARAM;
-    rate_limit_paras.vf_idx    = vf_id;
-    rate_limit_paras.vfid      = PLCR_INVALID_PARAM;
-    rate_limit_paras.group_id  = PLCR_INVALID_PARAM;
-
-    rtn = zxdh_plcr_unified_set_rate_limit(pf_dev, &rate_limit_paras);
-    PLCR_COMM_ASSERT(rtn);
-
-    PLCR_LOG_INFO("The Rate of VF%d has been set to: Min Tx Rate: %dMbit/s, Max Tx Rate: %dMbit/s\n",
-                    vf_id, min_tx_rate, max_tx_rate);
-
-    return rtn;
-}
-
-const struct net_device_ops zxdh_netdev_ops = {
-    .ndo_open = zxdh_en_open,
-    .ndo_stop = zxdh_en_close,
-    .ndo_start_xmit = zxdh_en_xmit,
-
-#if defined(HAVE_NDO_GET_STATS64) || defined(HAVE_VOID_NDO_GET_STATS64)
-    .ndo_get_stats64 = zxdh_en_get_netdev_stats_struct,
-#else
-    .ndo_get_stats = zxdh_en_get_netdev_stats_struct,
-#endif
-    .ndo_set_rx_mode = zxdh_en_set_rx_mode,
-    .ndo_validate_addr = eth_validate_addr,
-    .ndo_set_mac_address = zxdh_en_set_mac,
-
-#ifdef HAVE_RHEL7_EXTENDED_MIN_MAX_MTU
-    .extended.ndo_change_mtu = zxdh_en_change_mtu,
-#else
-    .ndo_change_mtu = zxdh_en_change_mtu,
-#endif /* HAVE_RHEL7_EXTENDED_MIN_MAX_MTU */
-
-    .ndo_do_ioctl = zxdh_en_ioctl,
-#ifdef ZXDH_PLCR_OPEN
-    .ndo_set_tx_maxrate = zxdh_en_ndo_set_tx_maxrate,
-#endif
-    .ndo_tx_timeout = zxdh_en_tx_timeout,
-
-#ifdef HAVE_VLAN_RX_REGISTER
-    .ndo_vlan_rx_register = zxdh_en_vlan_rx_register,
-#endif
-    .ndo_vlan_rx_add_vid = zxdh_en_vlan_rx_add_vid,
-    .ndo_vlan_rx_kill_vid = zxdh_en_vlan_rx_kill_vid,
-
-#ifdef CONFIG_NET_POLL_CONTROLLER
-    .ndo_poll_controller = zxdh_en_netpoll,
-#endif
-
-#ifdef HAVE_SETUP_TC
-#ifdef HAVE_RHEL7_NETDEV_OPS_EXT_NDO_SETUP_TC
-    .extended.ndo_setup_tc_rh = __zxdh_en_setup_tc,
-#else
-#ifdef NETIF_F_HW_TC
-    .ndo_setup_tc = __zxdh_en_setup_tc,
-#else
-    .ndo_setup_tc = zxdh_en_setup_tc,
-#endif /* NETIF_F_HW_TC */
-#endif /* HAVE_RHEL7_NETDEV_OPS_EXT_NDO_SETUP_TC */
-#endif /* HAVE_SETUP_TC */
-
-#ifdef HAVE_RHEL7_NET_DEVICE_OPS_EXT
-    .ndo_size = sizeof(const struct net_device_ops),
-#endif
-
-#ifdef IFLA_VF_MAX
-    .ndo_set_vf_mac = zxdh_en_ndo_set_vf_mac,
-#ifdef HAVE_RHEL7_NETDEV_OPS_EXT_NDO_SET_VF_VLAN
-    .extended.ndo_set_vf_vlan = zxdh_en_ndo_set_vf_port_vlan,
-#else
-    .ndo_set_vf_vlan = zxdh_en_ndo_set_vf_port_vlan,
-#endif
-#ifdef HAVE_NDO_SET_VF_MIN_MAX_TX_RATE
-#ifdef ZXDH_PLCR_OPEN
-    .ndo_set_vf_rate = zxdh_en_ndo_set_vf_rate,
-#else
-    .ndo_set_vf_rate = zxdh_en_ndo_set_vf_bw,
-#endif
-#else
-    .ndo_set_vf_rate = zxdh_en_ndo_set_vf_bw,
-#endif
-    .ndo_get_vf_config = zxdh_en_ndo_get_vf_config,
-#ifdef HAVE_VF_SPOOFCHK_CONFIGURE
-    .ndo_set_vf_spoofchk = zxdh_en_ndo_set_vf_spoofchk,
-#endif
-#ifdef HAVE_NDO_SET_VF_TRUST
-#ifdef HAVE_RHEL7_NET_DEVICE_OPS_EXT
-    .extended.ndo_set_vf_trust = zxdh_en_ndo_set_vf_trust,
-#else
-    .ndo_set_vf_trust = zxdh_en_ndo_set_vf_trust,
-#endif /* HAVE_RHEL7_NET_DEVICE_OPS_EXT */
-#endif /* HAVE_NDO_SET_VF_TRUST */
-#endif /* IFLA_VF_MAX */
-
-#ifdef HAVE_UDP_ENC_RX_OFFLOAD
-#ifdef HAVE_VXLAN_RX_OFFLOAD
-#if IS_ENABLED(CONFIG_VXLAN)
-    .ndo_add_vxlan_port = zxdh_en_add_vxlan_port,
-    .ndo_del_vxlan_port = zxdh_en_del_vxlan_port,
-#endif
-#endif /* HAVE_VXLAN_RX_OFFLOAD */
-
-#ifdef HAVE_GENEVE_RX_OFFLOAD
-#if IS_ENABLED(CONFIG_GENEVE)
-    .ndo_add_geneve_port = zxdh_en_add_geneve_port,
-    .ndo_del_geneve_port = zxdh_en_del_geneve_port,
-#endif
-#endif /* HAVE_GENEVE_RX_OFFLOAD */
-#endif /* HAVE_UDP_ENC_RX_OFFLOAD */
-
-#ifdef HAVE_NDO_GET_PHYS_PORT_ID
-    .ndo_get_phys_port_id = zxdh_en_get_phys_port_id,
-#endif /* HAVE_NDO_GET_PHYS_PORT_ID */
-
-    .ndo_set_features = zxdh_en_set_features,
-
-#ifdef HAVE_FDB_OPS
-    .ndo_fdb_add = zxdh_en_ndo_fdb_add,
-    .ndo_fdb_del = zxdh_en_ndo_fdb_del,
-#ifdef HAVE_NDO_FEATURES_CHECK
-    .ndo_features_check = zxdh_en_features_check,
-#endif /* HAVE_NDO_FEATURES_CHECK */
-#ifdef HAVE_BRIDGE_ATTRIBS
-    .ndo_bridge_getlink = zxdh_en_ndo_bridge_getlink,
-    .ndo_bridge_setlink = zxdh_en_ndo_bridge_setlink,
-#endif /* HAVE_BRIDGE_ATTRIBS */
-#endif /* HAVE_FDB_OPS */
-
-#ifdef HAVE_UDP_TUNNEL_OPS
-    .ndo_udp_tunnel_add = udp_tunnel_nic_add_port,
-    .ndo_udp_tunnel_del = udp_tunnel_nic_del_port,
-#endif
-
-#ifdef HAVE_RHEL6_NET_DEVICE_OPS_EXT
-};
-
-/* RHEL6 keeps these operations in a separate structure */
-static const struct net_device_ops_ext zxdh_netdev_ops_ext =
-{
-    .size = sizeof(struct net_device_ops_ext),
-#endif /* HAVE_RHEL6_NET_DEVICE_OPS_EXT */
-
-#ifdef HAVE_NDO_SET_FEATURES
-    .ndo_set_features = zxdh_en_set_features,
-#endif /* HAVE_NDO_SET_FEATURES */
-
-#ifdef HAVE_NDO_SET_VF_LINK_STATE
-    .ndo_set_vf_link_state = zxdh_en_ndo_set_vf_link_state,
-#endif
-};
-
-static void priv_flags_init(struct zxdh_en_priv *priv)
-{
-    priv->edev.pflags = 0;
-
-    priv->edev.pflags &= BIT(ZXDH_PFLAG_ENABLE_LLDP); /* LLDP默认为开 */
-}
-
-static int32_t get_max_num_qs(struct zxdh_en_container *en_con)
-{
-    return en_con->ops->is_bond(en_con->parent) ? ZXDH_BOND_ETH_MQ_PAIRS_NUM : max_pairs;
-}
-
-static int32_t fw_version_init(struct zxdh_en_device *en_dev)
-{
-    int32_t ret = 0;
-    uint8_t fw_version[ETHTOOL_FWVERS_LEN] = {0};
-    uint8_t fw_version_len = 0;
-
-    ret = zxdh_en_firmware_version_get(en_dev, fw_version, &fw_version_len);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_en_firmware_version_get err, ret %d!!!!\n", ret);
-        return ret;
-    }
-    if (fw_version_len > ETHTOOL_FWVERS_LEN)
-    {
-        LOG_ERR("fw_version_len (%d) greater than 31!!!!\n", fw_version_len);
-        return -1;
-    }
-
-    fw_version[ETHTOOL_FWVERS_LEN - 1] = '\0';
-    en_dev->fw_version_len = ETHTOOL_FWVERS_LEN;
-    memcpy(en_dev->fw_version, (uint8_t *)fw_version, en_dev->fw_version_len);
-    LOG_INFO("fw_version:%s\n", en_dev->fw_version);
-
-    return 0;
-}
-
-int32_t zxdh_priv_init(struct zxdh_en_priv *priv, struct net_device *netdev)
-{
-    int32_t ret = 0;
-    struct zxdh_en_device *en_dev = &priv->edev;
-
-    mutex_init(&priv->lock);
-    priv_flags_init(priv);
-    en_dev->msglevel =  NETIF_MSG_LINK;
-
-    /* 优先级4，暂时写死不支持 */
-    en_dev->wol_support = 0;
-    en_dev->wolopts = 0;
-
-    ret = fw_version_init(en_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("fw_version_init err ret: %d\n", ret);
-        return ret;
-    }
-
-    return 0 ;
-}
-
-struct net_device *zxdh_create_netdev(struct zxdh_en_container *en_con)
-{
-    struct net_device *netdev = NULL;
-    struct zxdh_en_priv *en_priv = NULL;
-    struct dh_core_dev *dh_dev = en_con->parent;
-
-    netdev = alloc_etherdev_mqs(sizeof(struct zxdh_en_priv), get_max_num_qs(en_con), get_max_num_qs(en_con));
-    if (unlikely(netdev == NULL))
-    {
-        LOG_ERR("alloc_etherdev_mqs() failed\n");
-        return NULL;
-    }
-
-    en_priv = netdev_priv(netdev);
-
-    en_priv->edev.parent = dh_dev;
-    en_priv->edev.ops = en_con->ops;
-    en_priv->edev.netdev = netdev;
-
-    zxdh_priv_init(en_priv, netdev);
-
-    netif_carrier_off(netdev);
-    netif_tx_disable(netdev);
-    dev_net_set(netdev, dh_core_net(dh_dev));
-
-    return netdev;
-}
-
-void zxdh_netdev_features_init(struct net_device *netdev)
-{
-    netdev->features |= NETIF_F_RXCSUM |
-                        NETIF_F_HW_CSUM |
-                        NETIF_F_TSO |
-                        NETIF_F_SG |
-                        NETIF_F_GSO |
-                        NETIF_F_LRO |
-                        NETIF_F_TSO6 |
-                        NETIF_F_GRO |
-                        NETIF_F_HW_VLAN_STAG_FILTER |
-                        NETIF_F_HW_VLAN_CTAG_FILTER |
-                        NETIF_F_GSO_UDP_TUNNEL_CSUM |
-                        NETIF_F_RXHASH;
-
-    netdev->hw_features |= NETIF_F_RXCSUM |
-                        NETIF_F_HW_CSUM |
-                        NETIF_F_TSO |
-                        NETIF_F_SG |
-                        NETIF_F_GSO |
-                        NETIF_F_LRO |
-                        NETIF_F_TSO6 |
-                        NETIF_F_GRO |
-                        NETIF_F_HW_VLAN_STAG_FILTER |
-                        NETIF_F_HW_VLAN_CTAG_FILTER |
-                        NETIF_F_GSO_UDP_TUNNEL_CSUM |
-                        NETIF_F_HW_VLAN_CTAG_RX     |
-                        NETIF_F_HW_VLAN_CTAG_TX     |
-                        NETIF_F_HW_VLAN_STAG_RX     |
-                        NETIF_F_HW_VLAN_STAG_TX     |
-                        NETIF_F_RXHASH;
-
-    netdev->hw_enc_features |= NETIF_F_RXCSUM |
-                               NETIF_F_HW_CSUM |
-                               NETIF_F_GSO_UDP_TUNNEL_CSUM;
-
-    return;
-}
-
-extern const struct xfrmdev_ops zxdh_xfrmdev_ops;
-static void zxdh_build_nic_netdev(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct dh_core_dev *dh_dev = en_priv->edev.parent;
-
-    SET_NETDEV_DEV(netdev, &dh_dev->parent->pdev->dev);
-
-    netdev->netdev_ops = &zxdh_netdev_ops;
-
-#ifdef ZXDH_SEC
-    /*内核 sec相关*/
-    netdev->features |=NETIF_F_HW_ESP;
-    netdev->xfrmdev_ops = &zxdh_xfrmdev_ops;
-#endif
-
-#ifdef HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT
-    zxdh_en_set_ethtool_ops_ext(netdev);
-#else
-    zxdh_en_set_ethtool_ops(netdev);
-#endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */
-
-    zxdh_netdev_features_init(netdev);
-}
-
-int32_t zxdh_en_bond_get_mac(struct net_device *netdev, uint8_t pannel_id, uint8_t *mac)
-{
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-    struct zxdh_en_priv *en_priv  = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    msg.payload.hdr_to_agt.op_code = AGENT_FLASH_MAC_READ;
-    msg.payload.flash_read_msg.index = pannel_id;
-
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_FLASH, &msg, &msg);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_send_command_to_specify failed: %d\n", ret);
-        return ret;
-    }
-
-    LOG_INFO("bond get mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", msg.reps.flash_mac_read_msg.mac[0],\
-    msg.reps.flash_mac_read_msg.mac[1],msg.reps.flash_mac_read_msg.mac[2], msg.reps.flash_mac_read_msg.mac[3],\
-    msg.reps.flash_mac_read_msg.mac[4], msg.reps.flash_mac_read_msg.mac[5]);
-
-    ether_addr_copy(mac, msg.reps.flash_mac_read_msg.mac);
-    return ret;
-}
-
-int32_t zxdh_mac_addr_init(struct net_device *netdev)
-{
-    uint8_t mac[6] = {0};
-    uint8_t pannel_id = 0;
-    int32_t ret = 0;
-    struct zxdh_en_priv *en_priv  = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    if (en_dev->ops->is_bond(en_dev->parent))
-    {
-        pannel_id = en_dev->pannel_id;
-        ret = zxdh_en_bond_get_mac(netdev, pannel_id, mac);
-        if (ret != 0)
-        {
-            LOG_ERR("zxdh_en_bond_mac_get failed: %d\n", ret);
-        }
-    }
-    else
-    {
-        en_dev->ops->get_mac(en_dev->parent, mac);
-    }
-
-    if (!is_valid_ether_addr(mac))
-    {
-        get_random_bytes(mac, 6);
-        mac[0] &= 0xfe;
-        LOG_INFO("set random mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-    }
-    LOG_INFO("set mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-    memcpy(netdev->dev_addr, mac, 6);
-
-    return ret;
-}
-
-int32_t zxdh_status_init(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    if (en_dev->ops->if_init(en_dev->parent))
-    {
-        zxdh_vp_reset(netdev);
-    }
-
-    /* Disable VQ/configuration callbacks. */
-    zxdh_vp_disable_cbs(netdev);
-
-    zxdh_add_status(netdev, ZXDH_CONFIG_S_ACKNOWLEDGE);
-
-    zxdh_add_status(netdev, ZXDH_CONFIG_S_DRIVER);
-
-    /* fix features, not set features*/
-    zxdh_pf_features_init(netdev);
-
-    might_sleep();
-    zxdh_add_status(netdev, ZXDH_CONFIG_S_FEATURES_OK);
-    if (!zxdh_has_status(netdev, ZXDH_CONFIG_S_FEATURES_OK))
-    {
-        LOG_ERR("device refuses features ok\n");
-        return -ENODEV;
-    }
-
-    return 0;
-}
-
-void zxdh_device_ready(struct net_device *netdev)
-{
-    zxdh_vp_enable_cbs(netdev);
-
-    zxdh_add_status(netdev, ZXDH_CONFIG_S_DRIVER_OK);
-}
-
-void zxdh_link_state_notify_kernel(struct net_device *netdev)
-{
-    struct zxdh_en_priv   *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev  = &en_priv->edev;
-
-    if(en_dev->ops->get_pf_link_up(en_dev->parent))
-    {
-        netif_carrier_off(netdev);
-        udelay(10);
-        netif_carrier_on(netdev);
-    }
-    else
-    {
-        netif_carrier_on(netdev);
-        udelay(10);
-        netif_carrier_off(netdev);
-    }
-}
-
-int32_t aux_get_bond_attrs(struct zxdh_en_device *en_dev, struct zxdh_lag_attrs *attr)
-{
-    *attr = (struct zxdh_lag_attrs)
-    {
-        .pannel_id = en_dev->pannel_id,
-        .vport = en_dev->vport,
-        .slot_id = en_dev->slot_id,
-        .qid[0] = en_dev->phy_index[0],
-        .qid[1] = en_dev->phy_index[1],
-        .pcie_id = en_dev->pcie_id,
-        .phy_port = en_dev->phy_port,
-    };
-
-    LOG_INFO("bond pf: pannel %hu, vport 0x%hx, phy_qid[0] %u, phy_qid[1] %u, pcie id 0x%x\n",
-            attr->pannel_id, attr->vport, attr->qid[0], attr->qid[1], attr->pcie_id);
-
-    return 0;
-}
-
-void aux_set_netdev_name(struct net_device *netdev, uint16_t pannel_id)
-{
-    struct zxdh_en_device *en_dev = NULL;
-    struct zxdh_en_priv *en_priv = NULL;
-
-    en_priv = netdev_priv(netdev);
-    en_dev = &en_priv->edev;
-
-    if (en_dev->ops->is_bond(en_dev->parent))
-    {
-        netdev->dev_port = pannel_id + 1;
-    }
-}
-
-int32_t zxdh_en_mtu_init(struct net_device *netdev)
-{
-    netdev->min_mtu = ETH_MIN_MTU;
-    netdev->max_mtu = ZXDH_MAX_MTU;
-
-    return zxdh_en_config_mtu_to_np(netdev, ZXDH_DEFAULT_MTU);
-}
-
-static int32_t zxdh_en_dev_probe(struct zxdh_auxiliary_device *adev, const struct zxdh_auxiliary_device_id *id)
-{
-    struct zxdh_en_container *en_container = container_of(adev, struct zxdh_en_container, adev);
-    struct net_device *netdev = NULL;
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    struct zxdh_lag_attrs lag_attrs;
-    int32_t err = 0;
-    int32_t vqs_channel_num = 0;
-
-    LOG_INFO("aux level driver probe start\n");
-
-    netdev = zxdh_create_netdev(en_container);
-    if (unlikely(netdev == NULL))
-    {
-        LOG_ERR("zxdh_create_netdev is null\n");
-        err = -ENOMEM;
-        goto err_create_netdev;
-    }
-
-    zxdh_build_nic_netdev(netdev);
-
-    dev_set_drvdata(&adev->dev, netdev_priv(netdev));
-
-    en_priv = netdev_priv(netdev);
-    en_dev = &en_priv->edev;
-    en_dev->channels_num = en_dev->ops->get_channels_num(en_dev->parent);
-    en_dev->ops->set_rdma_netdev(en_dev->parent, netdev);
-    en_dev->curr_unicast_num = 0;
-    en_dev->curr_multicast_num = 0;
-    en_dev->init_comp_flag = AUX_INIT_INCOMPLETED;
-    en_dev->delay_statistics_enable = 0;
-
-    vqs_channel_num = en_dev->ops->create_vqs_channels(en_dev->parent);
-    if (vqs_channel_num < 0)
-    {
-        LOG_ERR("create_vqs_channels failed, vqs_channel_num: %d\n", vqs_channel_num);
-        err = vqs_channel_num;
-        goto err_create_vqs_channels;
-    }
-
-    err = dh_aux_eq_table_init(en_priv);
-    if (err != 0)
-    {
-        LOG_ERR("Failed to alloc IRQs: %d\n", err);
-        goto err_eq_table_init;
-    }
-
-    err = dh_aux_events_init(en_priv);
-    if (err != 0)
-    {
-        LOG_ERR("dh_aux_events_init failed: %d\n", err);
-        goto err_events_init;
-    }
-
-    err = dh_aux_eq_table_create(en_priv);
-    if (err != 0)
-    {
-        LOG_ERR("Failed to alloc EQs: %d\n", err);
-        goto err_eq_table_create;
-    }
-
-    err = zxdh_status_init(netdev);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_status_init failed: %d\n", err);
-        goto err_status_init;
-    }
-
-    en_dev->ep_bdf = en_dev->ops->get_epbdf(en_dev->parent);
-    en_dev->vport = en_dev->ops->get_vport(en_dev->parent);
-    en_dev->pcie_id = en_dev->ops->get_pcie_id(en_dev->parent);
-    en_dev->slot_id = en_dev->ops->get_slot_id(en_dev->parent);
-    LOG_INFO("ep_bdf: 0x%x, vport: 0x%x, pcie_id: %d, slot_id: %d\n", en_dev->ep_bdf, en_dev->vport, en_dev->pcie_id, en_dev->slot_id);
-
-    err = zxdh_vqs_init(netdev);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_vqs_init failed: %d\n", err);
-        goto err_vqs_init;
-    }
-
-    if (en_dev->ops->is_upf(en_dev->parent))
-    {
-        en_dev->hash_search_idx = 2;//FIXME
-    }
-    else if (!en_dev->ops->is_bond(en_dev->parent))
-    {
-        err = zxdh_hash_id_get(en_dev);
-        if (err != 0)
-        {
-            LOG_ERR("zxdh_hash_id_get failed: %d\n", err);
-            goto err_do_vqs_free;
-        }
-
-        err = zxdh_panel_id_get(en_dev);
-        if (err != 0)
-        {
-            LOG_ERR("zxdh_panel_id_get failed: %d\n", err);
-            goto err_do_vqs_free;
-        }
-    }
-
-    en_dev->hash_func = ZXDH_FUNC_TOP;
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        if (en_dev->ops->is_bond(en_dev->parent))
-        {
-            err = zxdh_aux_alloc_pannel(en_dev);
-            if (err != 0)
-            {
-                LOG_ERR("zxdh_aux_alloc_pannel failed: %d\n", err);
-                goto err_do_vqs_free;
-            }
-        }
-        else if (!en_dev->ops->is_upf(en_dev->parent))
-        {
-            err = zxdh_phyport_get(en_dev);
-            if (err != 0)
-            {
-                LOG_ERR("zxdh_phyport_get failed: %d\n", err);
-                goto err_do_vqs_free;
-            }
-        }
-
-        err = zxdh_mac_addr_init(netdev);
-        if (err != 0)
-        {
-            LOG_ERR("zxdh_mac_addr_init failed: %d\n", err);
-            goto err_do_vqs_free;
-        }
-
-        err = zxdh_pf_port_init(netdev);
-        if (err != 0)
-        {
-            LOG_ERR("zxdh_pf_port_init failed: %d\n", err);
-            goto err_do_vqs_free;
-        }
-    }
-    else
-    {
-        err = zxdh_vf_dpp_port_init(netdev);
-        if (err != 0)
-        {
-            LOG_ERR("zxdh_vf_dpp_port_init failed: %d\n", err);
-            goto err_do_vqs_free;
-        }
-    }
-
-    if (!en_dev->ops->is_bond(en_dev->parent))
-    {
-        netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
-        err = zxdh_num_channels_changed(en_dev, en_dev->curr_queue_pairs);
-        if (err != 0)
-        {
-            LOG_ERR("zxdh_num_channels_changed failed: %d\n", err);
-            goto err_do_vport_free;
-        }
-    }
-
-    err = zxdh_common_tbl_init(netdev);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_common_tlb_init failed: %d\n", err);
-        goto err_do_rxfh_free;
-    }
-
-    zxdh_device_ready(netdev);
-
-    err = zxdh_en_mtu_init(netdev);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_en_mtu_init failed: %d\n", err);
-        goto err_do_rxfh_free;
-    }
-
-    en_dev->hw_stats.q_stats = kmalloc_array(max_pairs, sizeof(struct zxdh_en_queue_stats), GFP_KERNEL);
-    if (unlikely(en_dev->hw_stats.q_stats == NULL))
-    {
-        LOG_ERR("hw_stats.q_stats kmalloc failed\n");
-        goto err_do_rxfh_free;
-    }
-    memset(en_dev->hw_stats.q_stats, 0, max_pairs * sizeof(struct zxdh_en_queue_stats));
-    memset(&en_dev->pre_stats, 0, sizeof(struct zxdh_en_vport_stats));
-
-    err = zxdh_en_vport_pre_stats_get(en_dev);
-    if(err != 0)
-    {
-        LOG_ERR("get vport pre stats failed, %d\n", err);
-        goto err_do_q_stats_free;
-    }
-
-    aux_set_netdev_name(netdev, en_dev->pannel_id);
-    err = register_netdev(netdev);
-    if (err != 0)
-    {
-        LOG_ERR("register_netdev failed, %d\n", err);
-        goto err_do_q_stats_free;
-    }
-
-    zxdh_en_bar_del_mac(netdev);
-    zxdh_en_bar_cfg_mac(netdev, netdev->dev_addr);
-    zxdh_link_state_notify_kernel(netdev);
-
-    if (en_dev->ops->is_bond(en_dev->parent))
-    {
-        aux_get_bond_attrs(en_dev, &lag_attrs);
-        zxdh_ldev_add_netdev(en_container->parent, en_dev->pannel_id, netdev, &lag_attrs);
-    }
-
-#ifdef ZXDH_PLCR_OPEN
-    err = zxdh_plcr_init(en_priv);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_plcr_init failed, %d\n", err);
-    }
-#endif
-
-    en_dev->init_comp_flag = AUX_INIT_COMPLETED;
-
-    err = dh_aux_ipv6_notifier_init(en_priv);
-    if (err != 0)
-    {
-        LOG_ERR("dh_aux_ipv6_notifier_init failed: %d\n", err);
-        goto err_ipv6_notifier_init;
-    }
-
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        en_dev->autoneg_enable = AUTONEG_ENABLE;
-        err = zxdh_en_phyport_init(en_dev);
-        if (err != 0)
-        {
-            LOG_ERR("zxdh_en_phyport_init failed: %d\n", err);
-            goto err_phyport_init;
-        }
-    }
-
-#ifdef ZXDH_MSGQ
-    NEED_MSGQ(en_dev)
-    {
-        err = zxdh_msgq_init(en_dev);
-        if (err)
-        {
-            LOG_ERR("zxdh_msgq_init failed: %d\n", err);
-            goto err_phyport_init;
-        }
-    }
-#endif
-
-    en_dev->ops->set_init_comp_flag(en_dev->parent);
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        /* clear mcode gate,successfully build the scheduling tree, and then open it again */
-        zxdh_dcbnl_set_tm_pport_mcode_gate_close(netdev);
-#ifdef ZXDH_DCBNL_OPEN
-        err = zxdh_dcbnl_initialize(netdev);
-        if (err != 0)
-        {
-            LOG_ERR("zxdh_dcbnl_initialize failed: %d\n", err);
-        }
-#endif
-    }
-
-    en_dev->ops->set_bond_num(en_dev->parent, true);
-    LOG_INFO("%s: aux level driver probe completed\n", netdev->name);
-
-    return 0;
-
-err_phyport_init:
-    dh_inet6_addr_change_notifier_unregister(&(en_dev->ipv6_notifier));
-err_ipv6_notifier_init:
-    if (en_dev->ops->is_bond(en_dev->parent))
-    {
-        aux_get_bond_attrs(en_dev, &lag_attrs);
-        zxdh_ldev_remove_netdev(en_dev->parent, netdev, &lag_attrs);
-    }
-    unregister_netdev(netdev);
-err_do_q_stats_free:
-    kfree(en_dev->hw_stats.q_stats);
-err_do_rxfh_free:
-    if (!en_dev->ops->is_bond(en_dev->parent))
-    {
-        zxdh_rxfh_del(en_dev);
-    }
-err_do_vport_free:
-    zxdh_vport_uninit(netdev);
-err_do_vqs_free:
-    zxdh_vqs_uninit(netdev);
-err_vqs_init:
-    zxdh_add_status(netdev, ZXDH_CONFIG_S_FAILED);
-err_status_init:
-    dh_aux_eq_table_destroy(en_priv);
-err_eq_table_create:
-    dh_aux_events_uninit(en_priv);
-err_events_init:
-    dh_aux_eq_table_cleanup(en_priv);
-err_eq_table_init:
-    en_dev->ops->destroy_vqs_channels(en_dev->parent);
-    en_dev->ops->release_port(en_dev->parent, en_dev->pannel_id);
-err_create_vqs_channels:
-    free_netdev(netdev);
-err_create_netdev:
-    return err;
-}
-
-static int32_t zxdh_en_dev_remove(struct zxdh_auxiliary_device *adev)
-{
-    struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)dev_get_drvdata(&adev->dev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct net_device *netdev = en_dev->netdev;
-    struct zxdh_lag_attrs lag_attrs;
-
-    LOG_INFO("%s: aux level driver remove start\n", netdev->name);
-
-    en_dev->ops->set_bond_num(en_dev->parent, false);
-    dh_inet6_addr_change_notifier_unregister(&(en_dev->ipv6_notifier));
-#ifdef ZXDH_MSGQ
-    NEED_MSGQ(en_dev)
-    {
-        zxdh_msgq_exit(en_dev);
-    }
-#endif
-
-#ifdef ZXDH_PLCR_OPEN
-    zxdh_plcr_uninit(en_priv);
-#endif
-
-    if (en_dev->ops->is_bond(en_dev->parent))
-    {
-        aux_get_bond_attrs(en_dev, &lag_attrs);
-        zxdh_ldev_remove_netdev(en_dev->parent, netdev, &lag_attrs);
-    }
-
-    #ifdef ZXDH_DCBNL_OPEN
-    zxdh_dcbnl_ets_uninit(netdev);
-    #endif
-
-    unregister_netdev(netdev);
-    kfree(en_dev->hw_stats.q_stats);
-
-    if (!en_dev->ops->is_bond(en_dev->parent))
-    {
-        zxdh_rxfh_del(en_dev);
-    }
-
-    zxdh_vport_uninit(netdev);
-
-    zxdh_vqs_uninit(netdev);
-
-    zxdh_add_status(netdev, ZXDH_CONFIG_S_FAILED);
-
-    dh_aux_eq_table_destroy(en_priv);
-    dh_aux_events_uninit(en_priv);
-    dh_aux_eq_table_cleanup(en_priv);
-    en_dev->ops->destroy_vqs_channels(en_dev->parent);
-    en_dev->ops->release_port(en_dev->parent, en_dev->pannel_id);
-    free_netdev(netdev);
-    LOG_INFO("aux level driver remove completed\n");
-
-    return 0;
-}
-
-static void zxdh_en_dev_shutdown(struct zxdh_auxiliary_device *adev)
-{
-    LOG_INFO("aux level driver shutdown start\n");
-    zxdh_en_dev_remove(adev);
-    LOG_INFO("aux level driver shutdown completed\n");
-};
-
-static const struct zxdh_auxiliary_device_id zxdh_en_dev_id_table[] = {
-    { .name = ZXDH_PF_NAME "." ZXDH_EN_DEV_ID_NAME, },
-    { },
-};
-
-MODULE_DEVICE_TABLE(zxdh_auxiliary, zxdh_en_dev_id_table);
-
-static struct zxdh_auxiliary_driver zxdh_en_driver = {
-    .name     = ZXDH_EN_DEV_ID_NAME,
-    .probe    = zxdh_en_dev_probe,
-    .remove   = zxdh_en_dev_remove,
-    .shutdown = zxdh_en_dev_shutdown,
-    .id_table = zxdh_en_dev_id_table,
-};
-
-int32_t zxdh_en_driver_register(void)
-{
-    int32_t err = 0;
-
-    if ((max_pairs == 0) || (max_pairs >= ZXDH_MAX_PAIRS_NUM))
-    {
-        LOG_INFO("max_pairs %u parameter is a invalid value, use the default value %u\n", max_pairs, ZXDH_MQ_PAIRS_NUM);
-        max_pairs = ZXDH_MQ_PAIRS_NUM;
-    }
-
-    err = zxdh_auxiliary_driver_register(&zxdh_en_driver);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_auxiliary_driver_register failed: %d\n", err);
-        goto err_aux_register;
-    }
-
-    err = dh_aux_msg_recv_func_register();
-    if (err != 0)
-    {
-        LOG_ERR("dh_aux_msg_recv_func_register failed: %d\n", err);
-        goto err_msg_recv_register;
-    }
-
-    err = zxdh_tools_netlink_register();
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_tools_msg_family register error failed: %d\n", err);
-        goto err_netlink_register;
-    }
-
-    LOG_INFO("all driver insmod completed\n");
-
-    return 0;
-
-err_netlink_register:
-    dh_aux_msg_recv_func_unregister();
-err_msg_recv_register:
-    zxdh_auxiliary_driver_unregister(&zxdh_en_driver);
-err_aux_register:
-    return err;
-}
-
-void zxdh_en_driver_unregister(void)
-{
-    LOG_INFO("driver rmmod start\n");
-    zxdh_tools_netlink_unregister();
-    dh_aux_msg_recv_func_unregister();
-    zxdh_auxiliary_driver_unregister(&zxdh_en_driver);
-}
-
-module_init(zxdh_en_driver_register);
-module_exit(zxdh_en_driver_unregister);
+#ifdef AUX_BUS_NO_SUPPORT
+#include <linux/dinghai/auxiliary_bus.h>
+#else
+#include <linux/auxiliary_bus.h>
+#endif
+#include "en_aux.h"
+#include "en_aux/en_cmd.h"
+#include "en_aux/en_ioctl.h"
+#include "en_aux/eq.h"
+#include "en_aux/events.h"
+#include "en_ethtool/ethtool.h"
+#include "en_np/table/include/dpp_tbl_api.h"
+#include "en_np/table/include/dpp_tbl_comm.h"
+#include "en_pf.h"
+#include "msg_common.h"
+#include <linux/dinghai/devlink.h>
+#include <linux/dinghai/dh_cmd.h>
+#include <linux/dinghai/driver.h>
+#include <linux/dinghai/en_sf.h>
+#include <linux/dinghai/helper.h>
+#include <linux/dinghai/kcompat.h>
+#include <linux/dinghai/lag.h>
+#include <linux/etherdevice.h>
+#include <linux/if_bridge.h>
+#include <linux/netdevice.h>
+#include <net/devlink.h>
+#include <net/udp_tunnel.h>
+#ifdef ZXDH_MSGQ
+#include "en_aux/priv_queue.h"
+#endif
+#include "en_aux/en_1588_pkt_proc.h"
+#include "en_aux/en_cmd.h"
+#include "zxdh_tools/zxdh_tools_netlink.h"
+
+#ifdef ZXDH_DCBNL_OPEN
+#include "en_aux/dcbnl/en_dcbnl.h"
+#endif
+
+uint32_t max_pairs = ZXDH_MQ_PAIRS_NUM;
+module_param(max_pairs, uint, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(max_pairs, "Max queue pairs");
+
+MODULE_LICENSE("Dual BSD/GPL");
+
+/* WARNING Do not use netif_carrier_on/off(),
+   it may affect the ethtool function */
+int32_t zxdh_en_open(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t i = 0;
+	int32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	LOG_INFO("zxdh_en_open start\n");
+	mutex_lock(&en_priv->lock);
+
+	for (i = 0; i < en_dev->curr_queue_pairs; i++) {
+		/* Make sure we have some buffers: if oom use wq */
+		if (!try_fill_recv(netdev, &en_dev->rq[i], GFP_KERNEL)) {
+			schedule_delayed_work(&en_dev->refill, 0);
+		}
+
+		virtnet_napi_enable(en_dev->rq[i].vq, &en_dev->rq[i].napi);
+		virtnet_napi_tx_enable(netdev, en_dev->sq[i].vq, &en_dev->sq[i].napi);
+	}
+
+	mutex_unlock(&en_priv->lock);
+
+	if (!en_dev->link_up) {
+		return 0;
+	}
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+	if (!en_dev->ops->is_bond(en_dev->parent)) {
+		if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+			return zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_VPORT_IS_UP, 1,
+											 0);
+		}
+		return dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VPORT_IS_UP, 1);
+	}
+
+	/* 给bond-pf的端口属性表配置为up */
+	err = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VPORT_IS_UP, 1);
+	if (err != 0) {
+		LOG_ERR("dpp_egr_port_attr_set bond pf failed\n");
+		return err;
+	}
+
+	return dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_IS_UP, 1);
+}
+
+int32_t zxdh_en_close(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t i = 0;
+	int32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	LOG_INFO("zxdh_en_close start\n");
+	/* Make sure refill_work doesn't re-enable napi! */
+	cancel_delayed_work_sync(&en_dev->refill);
+
+	for (i = 0; i < en_dev->curr_queue_pairs; i++) {
+		napi_disable(&en_dev->rq[i].napi);
+		virtnet_napi_tx_disable(&en_dev->sq[i].napi);
+	}
+
+	if (!en_dev->link_up) {
+		return 0;
+	}
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+	if (!en_dev->ops->is_bond(en_dev->parent)) {
+		if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+			return zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_VPORT_IS_UP, 0,
+											 0);
+		}
+		return dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VPORT_IS_UP, 0);
+	}
+
+	/* 给bond-pf的端口属性表配置为down */
+	err = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VPORT_IS_UP, 0);
+	if (err != 0) {
+		LOG_ERR("dpp_egr_port_attr_set bond pf failed\n");
+		return err;
+	}
+
+	return dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_IS_UP, 0);
+}
+
+void pkt_transport_protocol_parse(int8_t next_protocol,
+								  struct zxdh_net_hdr *hdr)
+{
+	if (next_protocol == IPPROTO_UDP) {
+		hdr->pi_hdr.pt.type_ctx.pkt_code = PCODE_UDP;
+	} else if (next_protocol == IPPROTO_TCP) {
+		hdr->pi_hdr.pt.type_ctx.pkt_code = PCODE_TCP;
+	} else {
+		hdr->pi_hdr.pt.type_ctx.pkt_code = PCODE_IP;
+	}
+
+	return;
+}
+
+void pkt_protocol_parse(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+						int32_t flag)
+{
+	struct ethhdr *mach = NULL;
+	struct iphdr *ipv4h = NULL;
+	struct ipv6hdr *ipv6h = NULL;
+
+	if (flag == 0) {
+		if (skb->protocol == htons(ETH_P_IP)) {
+			ipv4h = (struct iphdr *)skb_network_header(skb);
+			hdr->pi_hdr.pt.type_ctx.ip_type = IPV4_TYPE;
+			pkt_transport_protocol_parse(ipv4h->protocol, hdr);
+		} else if (skb->protocol == htons(ETH_P_IPV6)) {
+			ipv6h = (struct ipv6hdr *)skb_network_header(skb);
+			hdr->pi_hdr.pt.type_ctx.ip_type = IPV6_TYPE;
+			pkt_transport_protocol_parse(ipv6h->nexthdr, hdr);
+		} else {
+			hdr->pi_hdr.pt.type_ctx.ip_type = NOT_IP_TYPE;
+		}
+	} else {
+		mach = (struct ethhdr *)skb_inner_mac_header(skb);
+		if (mach->h_proto == htons(ETH_P_IP)) {
+			ipv4h = (struct iphdr *)skb_inner_network_header(skb);
+			hdr->pi_hdr.pt.type_ctx.ip_type = IPV4_TYPE;
+			pkt_transport_protocol_parse(ipv4h->protocol, hdr);
+		} else if (mach->h_proto == htons(ETH_P_IPV6)) {
+			ipv6h = (struct ipv6hdr *)skb_inner_network_header(skb);
+			hdr->pi_hdr.pt.type_ctx.ip_type = IPV6_TYPE;
+			pkt_transport_protocol_parse(ipv6h->nexthdr, hdr);
+		} else {
+			hdr->pi_hdr.pt.type_ctx.ip_type = NOT_IP_TYPE;
+		}
+	}
+}
+
+int32_t pkt_is_vxlan(struct sk_buff *skb)
+{
+	switch (skb->protocol) {
+	case htons(ETH_P_IP):
+		if (ip_hdr(skb)->protocol != IPPROTO_UDP) {
+			return -1;
+		}
+		break;
+
+	case htons(ETH_P_IPV6):
+		if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP) {
+			return -1;
+		}
+		break;
+
+	default:
+		return -1;
+	}
+
+	if (skb->inner_protocol_type != ENCAP_TYPE_ETHER ||
+		skb->inner_protocol != htons(ETH_P_TEB) ||
+		(skb_inner_mac_header(skb) - skb_transport_header(skb) !=
+		 sizeof(struct udphdr) + sizeof(struct vxlanhdr))) {
+		return -1;
+	}
+
+	return 0;
+}
+
+int32_t zxdh_tx_checksum_offload(struct zxdh_en_device *edev,
+								 struct sk_buff *skb, struct zxdh_net_hdr *hdr)
+{
+	if (skb->ip_summed != CHECKSUM_PARTIAL) {
+		return 0;
+	}
+
+	if ((skb->inner_protocol != 0) && (pkt_is_vxlan(skb) == 0)) {
+		skb->encapsulation = 0x1;
+	}
+
+	if ((skb->encapsulation == 0x1) &&
+		(edev->netdev->features & NETIF_F_GSO_UDP_TUNNEL_CSUM)) {
+		hdr->pi_hdr.bttl_pi_len = ENABLE_PI_FLAG_32B;
+		hdr->pd_hdr.ol_flag |= htons(0x1 << OUTER_IP_CHECKSUM_OFFSET);
+		pkt_protocol_parse(skb, hdr, 1);
+		hdr->pi_hdr.hdr_l3_offset =
+				htons(edev->hdr_len + skb_inner_network_offset(skb));
+		hdr->pi_hdr.hdr_l4_offset =
+				htons(edev->hdr_len + skb_inner_transport_offset(skb));
+	}
+
+	hdr->pi_hdr.pkt_action_flag1 |= htons(0x1 << INNER_IP_CHECKSUM_OFFSET);
+	hdr->pi_hdr.pkt_action_flag2 |= 0x1 << INNER_L4_CHECKSUM_OFFSET;
+	return 0;
+}
+
+static int pd_hdr_validate_vlan(struct zxdh_en_device *edev,
+								struct sk_buff *skb, struct zxdh_net_hdr *hdr)
+{
+	/* pf set vf vlan is done*/
+	if (edev->vlan_dev.vlan_id) {
+		if (!skb_vlan_tag_present(skb)) {
+			hdr->pd_hdr.cvlan.tci = htons(edev->vlan_dev.vlan_id);
+			hdr->pd_hdr.cvlan.tpid = htons(edev->vlan_dev.protcol);
+			hdr->pd_hdr.ol_flag |= htons(TXCAP_CTAG_INSERT_EN_BIT);
+			return 0;
+		} else {
+			hdr->pd_hdr.svlan.tci = htons(edev->vlan_dev.vlan_id);
+			hdr->pd_hdr.svlan.tpid = htons(edev->vlan_dev.protcol);
+			hdr->pd_hdr.ol_flag |= htons(TXCAP_STAG_INSERT_EN_BIT);
+		}
+	}
+
+	/* insert vlan hard-accellate when skb is taged to be inserted, eg. in vlan
+   * interface case*/
+	if (skb && skb_vlan_tag_present(skb)) {
+		hdr->pd_hdr.cvlan.tci = htons(skb_vlan_tag_get(skb));
+		hdr->pd_hdr.cvlan.tpid = (skb->vlan_proto);
+		hdr->pd_hdr.ol_flag |= htons(TXCAP_CTAG_INSERT_EN_BIT);
+	}
+	return 0;
+}
+
+int32_t pi_net_hdr_from_skb(struct zxdh_en_device *edev, struct sk_buff *skb,
+							struct zxdh_net_hdr *hdr)
+{
+	uint32_t gso_type = 0;
+	uint16_t mss = 0;
+#ifdef TIME_STAMP_1588
+	int32_t ret = 0;
+#endif
+
+	memset(hdr, 0, sizeof(*hdr)); /* no info leak */
+	hdr->pd_len = edev->hdr_len / HDR_2B_UNIT;
+	hdr->pi_hdr.bttl_pi_len = DISABLE_PI_FIELD_PARSE + ENABLE_PI_FLAG_32B;
+	hdr->tx_port = TX_PORT_DTP;
+	hdr->pi_hdr.pt.type_ctx.pkt_src = PKT_SRC_CPU;
+	hdr->pi_hdr.eth_port_id = INVALID_ETH_PORT_ID;
+
+	if (edev->delay_statistics_enable) {
+		pkt_delay_statistics_proc(skb, hdr, edev);
+	}
+
+	// #ifdef TIME_STAMP_1588
+	//     ret = pkt_1588_proc_xmit(skb, hdr, edev->clock_no, edev);
+	//     switch (ret)
+	//     {
+	//         case PTP_SUCCESS:
+	//         {
+	//             LOG_DEBUG("pkt_1588_proc_xmit success!!!\n");
+	//             return 0;
+	//         }
+	//         case IS_NOT_PTP_MSG:
+	//         {
+	//             LOG_DEBUG("not ptp msg!!\n");
+	//             break;
+	//         }
+	//         default:
+	//         {
+	//             LOG_ERR("pkt_1588_proc_xmit err!!!\n");
+	//             return ret;
+	//         }
+	//     }
+	// #endif
+
+	pd_hdr_validate_vlan(edev, skb, hdr);
+
+	gso_type = skb_shinfo(skb)->gso_type;
+	if (gso_type & SKB_GSO_TCPV4) {
+		mss = min(skb_shinfo(skb)->gso_size,
+				  (uint16_t)(edev->netdev->mtu - IP_BASE_HLEN - TCP_BASE_HLEN));
+		hdr->pi_hdr.pkt_action_flag1 |=
+				htons((mss / ETH_MTU_4B_UNIT) + NOT_IP_FRG_CSUM_FLAG);
+		hdr->pi_hdr.pkt_action_flag2 |=
+				TCP_FRG_CSUM_FLAG; /*0x24  bit21,18: 带pi,tso,计算checksum */
+	} else if (gso_type & SKB_GSO_TCPV6) {
+		mss = min(
+				skb_shinfo(skb)->gso_size,
+				(uint16_t)(edev->netdev->mtu - IPV6_BASE_HLEN - TCP_BASE_HLEN));
+		hdr->pi_hdr.pkt_action_flag1 |=
+				htons((mss / ETH_MTU_4B_UNIT) + NOT_IP_FRG_CSUM_FLAG);
+		hdr->pi_hdr.pkt_action_flag2 |=
+				TCP_FRG_CSUM_FLAG; /*0x24  bit21,18: 带pi,tso,计算checksum */
+	} else if (gso_type & (SKB_GSO_UDP | SKB_GSO_UDP_L4 | SKB_GSO_UDP_TUNNEL |
+						   SKB_GSO_UDP_TUNNEL_CSUM)) {
+		hdr->pi_hdr.pkt_action_flag1 =
+				htons((edev->netdev->mtu / ETH_MTU_4B_UNIT) + IP_FRG_CSUM_FLAG);
+	} else {
+		hdr->pi_hdr.pkt_action_flag1 |= htons(
+				(edev->netdev->mtu / ETH_MTU_4B_UNIT) + NOT_IP_FRG_CSUM_FLAG);
+		hdr->pi_hdr.pkt_action_flag2 |= NOT_TCP_FRG_CSUM_FLAG;
+	}
+
+	if (edev->netdev->features & NETIF_F_HW_CSUM) {
+		zxdh_tx_checksum_offload(edev, skb, hdr);
+	}
+
+	if ((edev->ops->is_bond(edev->parent)) &&
+		(skb->protocol == htons(ETH_P_SLOW) ||
+		 skb->protocol == htons(ETH_P_PAUSE))) {
+		hdr->pd_hdr.ol_flag |= htons(PANELID_EN);
+		hdr->pd_hdr.panel_id = edev->phy_port;
+	}
+
+#ifdef ZXDH_DCBNL_OPEN
+	if (NULL != skb->sk) {
+		hdr->pd_hdr.ol_flag |=
+				htons(ZXDH_DCBNL_SET_SK_PRIO(skb->sk->sk_priority));
+	}
+#endif
+
+#ifdef TIME_STAMP_1588
+	ret = pkt_1588_proc_xmit(skb, hdr, edev->clock_no, edev);
+	switch (ret) {
+	case PTP_SUCCESS: {
+		LOG_DEBUG("pkt_1588_proc_xmit success!!!\n");
+		return 0;
+	}
+	case IS_NOT_PTP_MSG: {
+		LOG_DEBUG("not ptp msg!!\n");
+		break;
+	}
+	default: {
+		LOG_ERR("pkt_1588_proc_xmit err!!!\n");
+		return ret;
+	}
+	}
+#endif
+	return 0;
+}
+
+int32_t xmit_skb(struct net_device *netdev, struct send_queue *sq,
+				 struct sk_buff *skb)
+{
+	struct zxdh_net_hdr *hdr = NULL;
+	// const unsigned char *dest = ((struct ethhdr *)skb->data)->h_dest;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t num_sg = 0;
+	unsigned hdr_len = en_dev->hdr_len;
+	bool can_push = false;
+	uint8_t *hdr_buf = sq->hdr_buf;
+
+	can_push = en_dev->any_header_sg &&
+			   !((unsigned long)skb->data & (__alignof__(*hdr) - 1)) &&
+			   !skb_header_cloned(skb) && skb_headroom(skb) >= hdr_len;
+	/* Even if we can, don't push here yet as this would skew
+   * csum_start offset below. */
+	if (can_push) {
+		hdr = (struct zxdh_net_hdr *)(skb->data - hdr_len);
+	} else {
+		memset(hdr_buf, 0, HDR_BUFFER_LEN);
+		hdr = (struct zxdh_net_hdr *)hdr_buf;
+	}
+
+	if (pi_net_hdr_from_skb(en_dev, skb, hdr)) {
+		return -EPROTO;
+	}
+
+	sg_init_table(sq->sg, skb_shinfo(skb)->nr_frags + (can_push ? 1 : 2));
+	if (can_push) {
+		__skb_push(skb, hdr_len);
+		num_sg = skb_to_sgvec(skb, sq->sg, 0, skb->len);
+		if (unlikely(num_sg < 0)) {
+			return num_sg;
+		}
+		/* Pull header back to avoid skew in tx bytes calculations. */
+		__skb_pull(skb, hdr_len);
+	} else {
+		sg_set_buf(sq->sg, hdr, hdr_len);
+		num_sg = skb_to_sgvec(skb, sq->sg + 1, 0, skb->len);
+		if (unlikely(num_sg < 0)) {
+			return num_sg;
+		}
+		num_sg++;
+	}
+
+	return virtqueue_add_outbuf(sq->vq, sq->sg, num_sg, skb, GFP_ATOMIC);
+}
+
+netdev_tx_t zxdh_en_xmit(struct sk_buff *skb, struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t qnum = skb_get_queue_mapping(skb);
+	struct send_queue *sq = &en_dev->sq[qnum];
+	int32_t err = 0;
+	struct netdev_queue *txq = netdev_get_tx_queue(netdev, qnum);
+	bool kick = !netdev_xmit_more();
+	bool use_napi = sq->napi.weight;
+
+	/* Free up any pending old buffers before queueing new ones. */
+	do {
+		if (use_napi) {
+			virtqueue_disable_cb(sq->vq);
+		}
+
+		free_old_xmit_skbs(netdev, sq, false);
+
+	} while (use_napi && kick &&
+			 unlikely(!virtqueue_enable_cb_delayed(sq->vq)));
+
+	/* timestamp packet in software */
+	skb_tx_timestamp(skb);
+
+	/* Try to transmit */
+	err = xmit_skb(netdev, sq, skb);
+
+	/* This should not happen! */
+	if (unlikely(err)) {
+		netdev->stats.tx_fifo_errors++;
+		netdev->stats.tx_errors++;
+		if (net_ratelimit()) {
+			LOG_WARN("unexpected TXQ (%d) queue failure: %d\n", qnum, err);
+		}
+		netdev->stats.tx_dropped++;
+		dev_kfree_skb_any(skb);
+		return NETDEV_TX_OK;
+	}
+
+	/* If running out of space, stop queue to avoid getting packets that we
+   * are then unable to transmit.
+   * An alternative would be to force queuing layer to requeue the skb by
+   * returning NETDEV_TX_BUSY. However, NETDEV_TX_BUSY should not be
+   * returned in a normal path of operation: it means that driver is not
+   * maintaining the TX queue stop/start state properly, and causes
+   * the stack to do a non-trivial amount of useless work.
+   * Since most packets only take 1 or 2 ring slots, stopping the queue
+   * early means 16 slots are typically wasted.
+   */
+	if (sq->vq->num_free < 2 + MAX_SKB_FRAGS) {
+		netif_stop_subqueue(netdev, qnum);
+		en_dev->hw_stats.q_stats[qnum].q_tx_stopped++;
+		if (!use_napi && unlikely(!virtqueue_enable_cb_delayed(sq->vq))) {
+			/* More just got used, free them then recheck. */
+			free_old_xmit_skbs(netdev, sq, false);
+			if (sq->vq->num_free >= 2 + MAX_SKB_FRAGS) {
+				netif_start_subqueue(netdev, qnum);
+				virtqueue_disable_cb(sq->vq);
+			}
+		}
+	}
+
+	if (kick || netif_xmit_stopped(txq)) {
+		if (virtqueue_kick_prepare_packed(sq->vq) && virtqueue_notify(sq->vq)) {
+			u64_stats_update_begin(&sq->stats.syncp);
+			sq->stats.kicks++;
+			u64_stats_update_end(&sq->stats.syncp);
+		}
+	}
+
+	return NETDEV_TX_OK;
+}
+
+#ifdef HAVE_NDO_GET_STATS64
+#ifdef HAVE_VOID_NDO_GET_STATS64
+static void zxdh_en_get_netdev_stats_struct(struct net_device *netdev,
+											struct rtnl_link_stats64 *stats)
+#else
+static struct rtnl_link_stats64 *
+zxdh_en_get_netdev_stats_struct(struct net_device *netdev,
+								struct rtnl_link_stats64 *stats)
+#endif
+{
+#ifdef HAVE_VOID_NDO_GET_STATS64
+	struct zxdh_en_device *en_dev = netdev_priv(netdev);
+	struct receive_queue *rq = NULL;
+	struct send_queue *sq = NULL;
+	uint32_t start = 0;
+	uint32_t i = 0;
+	uint64_t tpackets = 0;
+	uint64_t tbytes = 0;
+	uint64_t rpackets = 0;
+	uint64_t rbytes = 0;
+	uint64_t rdrops = 0;
+	uint32_t loop_cnt = en_dev->max_queue_pairs;
+	int32_t ret = 0;
+
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		ret = zxdh_mac_stats_get(en_dev);
+		if (ret != 0) {
+			LOG_ERR("zxdh_mac_stats_get failed, ret: %d\n", ret);
+			return;
+		}
+
+		stats->rx_packets = en_dev->hw_stats.phy_stats.rx_packets_phy;
+		stats->rx_bytes = en_dev->hw_stats.phy_stats.rx_bytes_phy;
+		stats->rx_errors = en_dev->hw_stats.phy_stats.rx_errors;
+		stats->rx_dropped = en_dev->hw_stats.phy_stats.rx_discards;
+		stats->tx_packets = en_dev->hw_stats.phy_stats.tx_packets_phy;
+		stats->tx_bytes = en_dev->hw_stats.phy_stats.tx_bytes_phy;
+		stats->tx_errors = en_dev->hw_stats.phy_stats.tx_errors;
+		stats->tx_dropped = en_dev->hw_stats.phy_stats.tx_drop;
+		return;
+	}
+
+#ifdef ZXDH_MSGQ
+	if (en_dev->need_msgq)
+		loop_cnt--;
+#endif
+
+	for (i = 0; i < loop_cnt; ++i) {
+		sq = &en_dev->sq[i];
+		rq = &en_dev->rq[i];
+		do {
+			start = u64_stats_fetch_begin_irq(&sq->stats.syncp);
+			tpackets = sq->stats.packets;
+			tbytes = sq->stats.bytes;
+		} while (u64_stats_fetch_retry_irq(&sq->stats.syncp, start));
+
+		do {
+			start = u64_stats_fetch_begin_irq(&rq->stats.syncp);
+			rpackets = rq->stats.packets;
+			rbytes = rq->stats.bytes;
+			rdrops = rq->stats.drops;
+		} while (u64_stats_fetch_retry_irq(&rq->stats.syncp, start));
+
+		stats->rx_packets += rpackets;
+		stats->rx_bytes += rbytes;
+		stats->rx_dropped += rdrops;
+		stats->tx_packets += tpackets;
+		stats->tx_bytes += tbytes;
+	}
+
+	stats->rx_errors = netdev->stats.rx_errors;
+	stats->tx_errors = netdev->stats.tx_errors;
+	stats->tx_dropped = netdev->stats.tx_dropped;
+	stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
+	return;
+#else
+	return stats;
+#endif
+}
+#endif /* HAVE_VOID_NDO_GET_STATS_64 */
+
+static void zxdh_en_set_rx_mode(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	queue_work(en_priv->events->wq, &en_dev->rx_mode_set_work);
+}
+
+void rx_mode_set_handler(struct work_struct *work)
+{
+	struct zxdh_en_device *en_dev =
+			container_of(work, struct zxdh_en_device, rx_mode_set_work);
+	bool promisc_changed = false;
+	bool allmulti_changed = false;
+	int32_t err = 0;
+	uint8_t fow = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+	ZXDH_AUX_INIT_COMP_CHECK(en_dev);
+
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		return;
+	}
+
+	promisc_changed = en_dev->netdev->flags & IFF_PROMISC;
+	allmulti_changed = en_dev->netdev->flags & IFF_ALLMULTI;
+	if (en_dev->promisc_enabled != promisc_changed) {
+		LOG_INFO("promisc_changed: %d", promisc_changed);
+		if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+			dpp_vport_uc_promisc_set(&pf_info, promisc_changed);
+			if (!en_dev->allmulti_enabled) {
+				dpp_vport_mc_promisc_set(&pf_info, promisc_changed);
+			}
+		} else {
+			if (!en_dev->allmulti_enabled) {
+				fow = 1;
+			}
+			err = zxdh_vf_port_promisc_set(en_dev, ZXDH_PROMISC_MODE,
+										   promisc_changed, fow);
+			if (err != 0) {
+				LOG_ERR("zxdh_vf_port_promisc_set failed\n");
+				return;
+			}
+		}
+		en_dev->promisc_enabled = promisc_changed;
+	}
+
+	if (en_dev->allmulti_enabled != allmulti_changed) {
+		LOG_INFO("allmulti_changed: %d", allmulti_changed);
+		if (!en_dev->promisc_enabled) {
+			if (en_dev->ops->get_coredev_type(en_dev->parent) ==
+				DH_COREDEV_PF) {
+				dpp_vport_mc_promisc_set(&pf_info, allmulti_changed);
+			} else {
+				err = zxdh_vf_port_promisc_set(en_dev, ZXDH_ALLMULTI_MODE,
+											   allmulti_changed, fow);
+				if (err != 0) {
+					LOG_ERR("zxdh_vf_port_promisc_set failed\n");
+					return;
+				}
+			}
+		}
+		en_dev->allmulti_enabled = allmulti_changed;
+	}
+}
+
+static int zxdh_en_bar_cfg_mac(struct net_device *netdev, const char *mac)
+{
+	int ret = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+
+	memcpy(msg.mac_cfg_msg.ifname, netdev->name, IFNAMSIZ);
+	memcpy(msg.mac_cfg_msg.mac, mac, ETH_ALEN);
+	msg.mac_cfg_msg.pannel_id = en_dev->panel_id;
+
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		msg.mac_cfg_msg.pannel_id = en_dev->pannel_id;
+	}
+	msg.mac_cfg_msg.ctl = 1;
+
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_CFG_MAC, &msg, &reps);
+	if (ret != 0 || reps.flag != ZXDH_REPS_SUCC) {
+		LOG_ERR("config mac info failed\n");
+		return -reps.flag;
+	}
+	return 0;
+}
+
+static int zxdh_en_bar_del_mac(struct net_device *netdev)
+{
+	int ret = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+
+	msg.mac_cfg_msg.pannel_id = en_dev->panel_id;
+
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		msg.mac_cfg_msg.pannel_id = en_dev->pannel_id;
+	}
+	msg.mac_cfg_msg.ctl = 0;
+
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_CFG_MAC, &msg, &reps);
+	if (ret != 0 || reps.flag != ZXDH_REPS_SUCC) {
+		LOG_ERR("del mac info failed.\n");
+		return -reps.flag;
+	}
+	return 0;
+}
+
+static int zxdh_en_set_mac(struct net_device *netdev, void *p)
+{
+	struct sockaddr *addr = (struct sockaddr *)p;
+	struct zxdh_en_device *en_dev = NULL;
+	struct zxdh_en_priv *en_priv = NULL;
+	struct netdev_hw_addr *ha = NULL;
+	bool delete_flag = true;
+	bool add_flag = true;
+	int32_t ret = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	if (!is_valid_ether_addr(addr->sa_data)) {
+		LOG_INFO("invalid mac address %pM\n", addr->sa_data);
+		return -EADDRNOTAVAIL;
+	}
+
+	if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
+		LOG_INFO("already using mac address %pM\n", addr->sa_data);
+		return 0;
+	}
+
+	list_for_each_entry(ha, &netdev->uc.list, list) {
+		if (!memcmp(ha->addr, netdev->dev_addr, netdev->addr_len)) {
+			delete_flag = false;
+		}
+
+		if (!memcmp(ha->addr, addr->sa_data, netdev->addr_len)) {
+			add_flag = false;
+		}
+	}
+
+	en_priv = netdev_priv(netdev);
+	en_dev = &en_priv->edev;
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		ether_addr_copy(netdev->dev_addr, addr->sa_data);
+		zxdh_en_bar_del_mac(netdev);
+		zxdh_en_bar_cfg_mac(netdev, netdev->dev_addr);
+		return 0;
+	}
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		if (delete_flag) {
+			ret = dpp_del_mac(&pf_info, netdev->dev_addr);
+			if (ret != 0) {
+				LOG_ERR("pf del mac failed, retval: %d\n", ret);
+				return ret;
+			}
+		}
+
+		if (add_flag) {
+			ret = dpp_add_mac(&pf_info, addr->sa_data);
+			if (ret != 0) {
+				LOG_ERR("pf add mac failed: %d\n", ret);
+				return ret;
+			}
+		}
+
+		LOG_INFO("set pf new mac address %pM\n", addr->sa_data);
+		ether_addr_copy(netdev->dev_addr, addr->sa_data);
+		zxdh_en_bar_del_mac(netdev);
+		zxdh_en_bar_cfg_mac(netdev, netdev->dev_addr);
+	} else {
+		ret = zxdh_vf_dpp_del_mac(en_dev, netdev->dev_addr, UNFILTER_MAC,
+								  delete_flag);
+		if (ret != 0) {
+			LOG_ERR("zxdh vf dpp del mac failed: %d\n", ret);
+			return ret;
+		}
+
+		if (add_flag) {
+			ret = zxdh_vf_dpp_add_mac(en_dev, addr->sa_data, UNFILTER_MAC);
+			if (ret != 0) {
+				LOG_ERR("zxdh vf dpp add mac failed: %d\n", ret);
+				return ret;
+			}
+			en_dev->ops->set_mac(en_dev->parent, addr->sa_data);
+		}
+
+		LOG_INFO("set vf new mac address %pM\n", addr->sa_data);
+		ether_addr_copy(netdev->dev_addr, addr->sa_data);
+	}
+
+	return ret;
+}
+
+int32_t zxdh_en_config_mtu_to_np(struct net_device *netdev, int32_t mtu_value)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t ret = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		dpp_panel_attr_set(&pf_info, en_dev->phy_port,
+						   PANEL_FLAG_MTU_OFFLOAD_ENABLE, 1);
+		dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_MTU,
+						   mtu_value);
+		dpp_egr_port_attr_set(&pf_info, EGR_FLAG_MTU_OFFLOAD_EN_OFF, 1);
+		dpp_egr_port_attr_set(&pf_info, EGR_FLAG_MTU, mtu_value);
+	} else {
+		ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_MTU_OFFLOAD_EN_OFF, 1,
+										0);
+		if (ret != 0) {
+			LOG_ERR("zxdh_vf_egr_port_attr_set config mtu enable failed: %d\n",
+					ret);
+			return ret;
+		}
+		ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_MTU, mtu_value, 0);
+		if (ret != 0) {
+			LOG_ERR("zxdh_vf_egr_port_attr_set config mut value failed: %d\n",
+					ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int zxdh_en_change_mtu(struct net_device *netdev, int new_mtu)
+{
+	int32_t ret = 0;
+
+	if ((new_mtu < ETH_MIN_MTU) || (new_mtu > ZXDH_MAX_MTU)) {
+		return -EINVAL;
+	}
+	LOG_INFO("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
+
+	netdev->mtu = new_mtu;
+
+	ret = zxdh_en_config_mtu_to_np(netdev, new_mtu);
+	if (ret != 0) {
+		LOG_ERR("zxdh_en_config_mtu_to_np failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+#ifdef HAVE_TX_TIMEOUT_TXQUEUE
+static void zxdh_en_tx_timeout(struct net_device *netdev, unsigned int txqueue)
+{
+	return;
+}
+#else
+static void zxdh_en_tx_timeout(struct net_device *netdev)
+{
+	return;
+}
+#endif
+
+#ifdef HAVE_VLAN_RX_REGISTER
+static void zxdh_en_vlan_rx_register(struct net_device *netdev,
+									 struct vlan_group *grp)
+{
+	return;
+}
+#endif
+
+static int vf_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
+{
+	int ret = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+
+	msg.hdr.op_code = ZXDH_VLAN_FILTER_ADD;
+	msg.hdr.vport = en_dev->vport;
+	msg.hdr.pcie_id = en_dev->pcie_id;
+	msg.rx_vid_add_msg.vlan_id = vid;
+
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+									   &reps);
+	if (ret != 0 || reps.flag != ZXDH_REPS_SUCC) {
+		LOG_ERR("pcieid:0x%x send msg to pf add vlan:%d failed! ret = %d, flag = "
+				"0x%x\n",
+				en_dev->pcie_id, vid, ret, reps.flag);
+		return -1;
+	}
+
+	return 0;
+}
+
+#if defined(HAVE_INT_NDO_VLAN_RX_ADD_VID) && defined(NETIF_F_HW_VLAN_CTAG_RX)
+static int zxdh_en_vlan_rx_add_vid(struct net_device *netdev,
+								   __always_unused __be16 proto, u16 vid)
+{
+	int retval = 0;
+	return retval;
+}
+#elif defined(HAVE_INT_NDO_VLAN_RX_ADD_VID) && !defined(NETIF_F_HW_VLAN_CTAG_RX)
+static int zxdh_en_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
+{
+	return 0;
+}
+#else
+static void zxdh_en_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
+{
+	return;
+}
+#endif
+
+static int vf_vlan_rx_del_vid(struct net_device *netdev, u16 vid)
+{
+	int ret = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+
+	msg.hdr.op_code = ZXDH_VLAN_FILTER_DEL;
+	msg.hdr.vport = en_dev->vport;
+	msg.hdr.pcie_id = en_dev->pcie_id;
+	msg.rx_vid_del_msg.vlan_id = vid;
+
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+									   &reps);
+	if (ret != 0 || reps.flag != ZXDH_REPS_SUCC) {
+		LOG_ERR("pcieid:0x%x send msg to pf del vlan:%d failed! ret = %d, flag = "
+				"0x%x\n",
+				en_dev->pcie_id, vid, ret, reps.flag);
+		return -1;
+	}
+
+	return 0;
+}
+
+#if defined(HAVE_INT_NDO_VLAN_RX_ADD_VID) && defined(NETIF_F_HW_VLAN_CTAG_RX)
+static int zxdh_en_vlan_rx_kill_vid(struct net_device *netdev,
+									__always_unused __be16 proto, u16 vid)
+{
+	int retval = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint16_t pcieid = en_dev->pcie_id;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if (vid > MAX_VLAN_ID) {
+		LOG_ERR("vlan id:%d input is err!\n", vid);
+		return -EINVAL;
+	}
+
+	if ((pcieid & PF_AC_MASK) == 0) { /* VF */
+		retval = vf_vlan_rx_del_vid(netdev, vid);
+		goto exit;
+	}
+
+	retval = dpp_del_vlan_filter(&pf_info, vid);
+	if (0 != retval) {
+		LOG_ERR("failed to del vlan: %d\n", vid);
+		goto exit;
+	}
+	LOG_INFO("pf del vlan %d succeed.\n", vid);
+
+exit:
+	return retval;
+}
+#elif defined(HAVE_INT_NDO_VLAN_RX_ADD_VID) && !defined(NETIF_F_HW_VLAN_CTAG_RX)
+static int zxdh_en_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
+{
+	return 0;
+}
+#else
+static void zxdh_en_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
+{
+	return;
+}
+#endif
+
+static void zxdh_en_netpoll(struct net_device *netdev)
+{
+	return;
+}
+
+#ifdef HAVE_SETUP_TC
+int zxdh_en_setup_tc(struct net_device *netdev, u8 tc)
+{
+	return 0;
+}
+
+#ifdef NETIF_F_HW_TC
+#ifdef HAVE_NDO_SETUP_TC_REMOVE_TC_TO_NETDEV
+static int __zxdh_en_setup_tc(struct net_device *netdev,
+							  enum tc_setup_type type, void *type_data)
+#elif defined(HAVE_NDO_SETUP_TC_CHAIN_INDEX)
+static int __zxdh_en_setup_tc(struct net_device *netdev, u32 handle,
+							  u32 chain_index, __be16 proto,
+							  struct tc_to_netdev *tc)
+#else
+static int __zxdh_en_setup_tc(struct net_device *netdev, u32 handle,
+							  __be16 proto, struct tc_to_netdev *tc)
+#endif
+{
+	return 0;
+}
+#endif
+#endif
+
+#ifdef HAVE_NDO_GET_PHYS_PORT_ID
+static int zxdh_en_get_phys_port_id(struct net_device *netdev,
+									struct netdev_phys_item_id *ppid)
+{
+	return 0;
+}
+#endif /* HAVE_NDO_GET_PHYS_PORT_ID */
+
+static void zxdh_set_en_device(struct net_device *netdev,
+							   netdev_features_t features)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	if ((features & NETIF_F_GSO) || (features & NETIF_F_GSO_UDP) ||
+		(features & NETIF_F_GSO_UDP_L4)) {
+		en_dev->drs_offload = true;
+	} else if ((features & NETIF_F_TSO) || (features & NETIF_F_HW_CSUM)) {
+		en_dev->dtp_offload = true;
+	} else {
+		en_dev->np_direction = true;
+	}
+
+	return;
+}
+
+static int zxdh_handle_feature(struct net_device *netdev,
+							   netdev_features_t *features,
+							   netdev_features_t wanted_features,
+							   netdev_features_t feature,
+							   zxdh_feature_handler feature_handler)
+{
+	netdev_features_t changes = wanted_features ^ netdev->features;
+	bool enable = !!(wanted_features & feature);
+	int err;
+
+	if (!(changes & feature) || feature_handler == NULL) {
+		return 0;
+	}
+
+	err = feature_handler(netdev, enable);
+	if (err) {
+		LOG_ERR("%s feature %pNF failed, err %d\n",
+				enable ? "Enable" : "Disable", &feature, err);
+		return err;
+	}
+
+	ZXDH_SET_FEATURE(features, feature, enable);
+	return 0;
+}
+
+static int32_t zxdh_dtp_offload_set(struct zxdh_en_device *en_dev,
+									DPP_PF_INFO_T *pf_info)
+{
+	ZXDH_VPORT_T port_attr_entry = { 0 };
+	int32_t ret = 0;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		ret = dpp_egr_port_attr_get(pf_info, &port_attr_entry);
+		if (ret != 0) {
+			LOG_ERR("dpp_egr_port_attr_get failed: %d\n", ret);
+			return ret;
+		}
+
+		if (!port_attr_entry.lro_offload &&
+			!port_attr_entry.ip_fragment_offload &&
+			!port_attr_entry.ip_checksum_offload &&
+			!port_attr_entry.tcp_udp_checksum_offload) {
+			ret = dpp_egr_port_attr_set(pf_info,
+										EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 0);
+		} else {
+			ret = dpp_egr_port_attr_set(pf_info,
+										EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 1);
+		}
+
+		return ret;
+	}
+
+	ret = zxdh_vf_egr_port_attr_get(en_dev, &port_attr_entry);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_get failed: %d\n", ret);
+		return ret;
+	}
+
+	if (!port_attr_entry.lro_offload && !port_attr_entry.ip_fragment_offload &&
+		!port_attr_entry.ip_checksum_offload &&
+		!port_attr_entry.tcp_udp_checksum_offload) {
+		ret = zxdh_vf_egr_port_attr_set(
+				en_dev, EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 0, 0);
+	} else {
+		ret = zxdh_vf_egr_port_attr_set(
+				en_dev, EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 1, 0);
+	}
+
+	return ret;
+}
+
+static int32_t set_feature_rx_checksum(struct net_device *netdev, bool enable)
+{
+	int en_value = enable ? 1 : 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	DPP_PF_INFO_T pf_info = { 0 };
+	int32_t ret = 0;
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IP_CHKSUM, enable);
+		if (ret != 0) {
+			LOG_ERR("EGR_FLAG_IP_CHKSUM set failed: %d\n", ret);
+			return ret;
+		}
+		ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_TCP_UDP_CHKSUM, enable);
+		if (ret != 0) {
+			LOG_ERR("EGR_FLAG_TCP_UDP_CHKSUM set failed: %d\n", ret);
+			return ret;
+		}
+	} else if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_IP_CHKSUM, en_value,
+										0);
+		if (ret != 0) {
+			LOG_ERR("EGR_FLAG_IP_CHKSUM set failed: %d\n", ret);
+			return ret;
+		}
+		ret = zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_TCP_UDP_CHKSUM,
+										en_value, 0);
+		if (ret != 0) {
+			LOG_ERR("EGR_FLAG_TCP_UDP_CHKSUM set failed: %d\n", ret);
+			return ret;
+		}
+	}
+
+	return zxdh_dtp_offload_set(en_dev, &pf_info);
+}
+
+static int set_feature_tx_checksum(struct net_device *netdev, bool enable)
+{
+	if (enable) {
+		netdev->features |= NETIF_F_HW_CSUM;
+	} else {
+		netdev->features &= ~NETIF_F_HW_CSUM;
+	}
+	return 0;
+}
+
+static int set_feature_vxlan_checksum(struct net_device *netdev, bool enable)
+{
+	int ret = 0;
+	int en_value = enable ? 1 : 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if (enable) {
+		netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
+	} else {
+		netdev->features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
+	}
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		ret = dpp_egr_port_attr_set(&pf_info,
+									EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD, enable);
+		if (ret != 0) {
+			LOG_ERR("zxdh set vxlan rx checksum failed!\n");
+			return ret;
+		}
+	} else if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		ret = zxdh_vf_egr_port_attr_set(
+				en_dev, EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD, en_value, 0);
+		if (ret != 0) {
+			LOG_ERR("zxdh_vf_egr_port_attr_set vxlan rx checksum failed!\n");
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+static int32_t set_feature_rxhash(struct net_device *netdev, bool enable)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		return dpp_vport_rss_en_set(&pf_info, enable);
+	}
+
+	return zxdh_vf_rss_en_set(en_dev, enable);
+}
+
+static int32_t set_vf_cvlan_filter(struct net_device *netdev, bool enable)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	int32_t ret = 0;
+
+	msg.hdr.op_code = ZXDH_VLAN_FILTER_SET;
+	msg.hdr.vport = en_dev->vport;
+	msg.hdr.pcie_id = en_dev->pcie_id;
+	msg.vlan_filter_set_msg.enable = enable;
+
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+									   &reps);
+	if (ret != 0 || reps.flag != ZXDH_REPS_SUCC) {
+		LOG_ERR("pcieid:0x%x send msg to pf set vlan filter enable:%s failed! ret "
+				"= %d, flag = 0x%x\n",
+				en_dev->pcie_id, enable ? "enable" : "disable", ret, reps.flag);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
+{
+	int ret = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint16_t pcieid = en_dev->pcie_id;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if ((pcieid & PF_AC_MASK) == 0) { /* VF */
+		ret = set_vf_cvlan_filter(netdev, enable);
+		goto exit;
+	}
+
+	ret = dpp_vport_vlan_filter_en_set(&pf_info, enable);
+
+exit:
+	return ret;
+}
+
+static int set_feature_svlan_filter(struct net_device *netdev, bool enable)
+{
+	int ret = 0;
+	return ret;
+}
+
+int set_vf_qinq_tpid(struct net_device *netdev, uint16_t tpid)
+{
+	int ret = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+
+	msg.hdr.op_code = ZXDH_SET_TPID;
+	msg.hdr.vport = en_dev->vport;
+	msg.tpid_cfg_msg.tpid = tpid;
+
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+									   &reps);
+	if (ret != 0 || reps.flag != ZXDH_REPS_SUCC) {
+		LOG_ERR("pcieid:0x%x send msg to vfs set tpid: 0x%x failed! ret = %d.\n",
+				en_dev->pcie_id, tpid, ret);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int set_vf_vlan_strip(struct net_device *netdev, bool enable,
+							 uint8_t flag)
+{
+	int ret = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+
+	msg.hdr.op_code = ZXDH_VLAN_OFFLOAD_SET;
+	msg.hdr.vport = en_dev->vport;
+	msg.hdr.pcie_id = en_dev->pcie_id;
+	msg.vlan_strip_msg.enable = enable;
+	msg.vlan_strip_msg.flag = flag;
+
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+									   &reps);
+	if (ret != 0 || reps.flag != ZXDH_REPS_SUCC) {
+		LOG_ERR("pcieid:0x%x send msg to vfs set vlan strip enable:%s failed! ret "
+				"= %d, flag = 0x%x\n",
+				en_dev->pcie_id, enable ? "enable" : "disable", ret, reps.flag);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int set_feature_vlan_strip(struct net_device *netdev, bool enable)
+{
+	int ret = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		ret = dpp_vport_vlan_strip_set(&pf_info, enable);
+	} else {
+		ret = set_vf_vlan_strip(netdev, enable, VLAN_STRIP_MSG_TYPE);
+	}
+
+	return ret;
+}
+
+static int set_feature_qinq_strip(struct net_device *netdev, bool enable)
+{
+	int ret = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		ret = dpp_vport_vlan_qinq_en_set(&pf_info, enable);
+	} else {
+		ret = set_vf_vlan_strip(netdev, enable, QINQ_STRIP_MSG_TYPE);
+	}
+
+	return ret;
+}
+
+static int32_t set_feature_lro(struct net_device *netdev, bool enable)
+{
+	uint32_t en_value = enable ? 1 : 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	DPP_PF_INFO_T pf_info = { 0 };
+	int32_t ret = 0;
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IPV4_TCP_ASSEMBLE, en_value);
+		if (ret != 0) {
+			LOG_ERR("EGR_FLAG_IPV4_TCP_ASSEMBLE set failed: %d\n", ret);
+			return ret;
+		}
+		dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IPV6_TCP_ASSEMBLE, en_value);
+		if (ret != 0) {
+			LOG_ERR("EGR_FLAG_IPV6_TCP_ASSEMBLE set failed: %d\n", ret);
+			return ret;
+		}
+	} else {
+		zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_IPV4_TCP_ASSEMBLE, en_value,
+								  0);
+		if (ret != 0) {
+			LOG_ERR("EGR_FLAG_IPV4_TCP_ASSEMBLE set failed: %d\n", ret);
+			return ret;
+		}
+		zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_IPV6_TCP_ASSEMBLE, en_value,
+								  0);
+		if (ret != 0) {
+			LOG_ERR("EGR_FLAG_IPV6_TCP_ASSEMBLE set failed: %d\n", ret);
+			return ret;
+		}
+	}
+
+	return zxdh_dtp_offload_set(en_dev, &pf_info);
+}
+
+int32_t zxdh_en_set_features(struct net_device *netdev,
+							 netdev_features_t wanted_features)
+{
+	int32_t ret = 0;
+	netdev_features_t oper_features = netdev->features;
+
+	zxdh_set_en_device(netdev, wanted_features);
+
+#define ZXDH_HANDLE_FEATURE(set_feature, handler)                             \
+	zxdh_handle_feature(netdev, &oper_features, wanted_features, set_feature, \
+						handler)
+
+	ret |= ZXDH_HANDLE_FEATURE(NETIF_F_RXCSUM, set_feature_rx_checksum);
+	ret |= ZXDH_HANDLE_FEATURE(NETIF_F_HW_CSUM, set_feature_tx_checksum);
+	ret |= ZXDH_HANDLE_FEATURE(NETIF_F_GSO_UDP_TUNNEL_CSUM,
+							   set_feature_vxlan_checksum);
+	ret |= ZXDH_HANDLE_FEATURE(NETIF_F_RXHASH, set_feature_rxhash);
+	ret |= ZXDH_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
+	ret |= ZXDH_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_vlan_strip);
+	ret |= ZXDH_HANDLE_FEATURE(NETIF_F_HW_VLAN_STAG_RX, set_feature_qinq_strip);
+
+	if (ret) {
+		netdev->features = oper_features;
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static uint32_t list_hw_addr_create(struct netdev_hw_addr_list *list,
+									const uint8_t *addr, int32_t addr_len,
+									uint8_t addr_type, bool global, bool sync)
+{
+	struct netdev_hw_addr *ha = NULL;
+
+	ha = kzalloc(sizeof(struct netdev_hw_addr), GFP_KERNEL);
+	if (ha == NULL) {
+		LOG_ERR("Kzalloc struct netdev_hw_addr failed \n");
+		return 1;
+	}
+
+	/* 结构体赋值 */
+	memcpy(ha->addr, addr, addr_len);
+	ha->type = addr_type;
+	ha->refcount = 1; /* 引用计数 */
+	ha->global_use = global;
+	ha->synced = sync ? 1 : 0;
+	ha->sync_cnt = 0;
+	list_add_tail_rcu(&ha->list, &list->list);
+	list->count++; /* 链表节点加1 */
+
+	return 0;
+}
+
+static uint32_t list_hw_addr_del(struct netdev_hw_addr_list *list,
+								 struct netdev_hw_addr *ha)
+{
+	int32_t refcount = ha->refcount;
+
+	/* 引用的计数大于1，则不能删除此mac地址 */
+	if (--refcount) {
+		return 1;
+	}
+
+	/* 从链表中删除此条目 */
+	list_del_rcu(&ha->list);
+
+	/* 释放ha结构体占用内存，rcu_head可以安全地释放ha占用的内存*/
+	kfree_rcu(ha, rcu_head);
+	list->count--;
+
+	return 0;
+}
+
+bool is_this_mac_exist(struct net_device *netdev, const uint8_t *addr)
+{
+	struct netdev_hw_addr *ha = NULL;
+	bool isexist = false;
+
+	/* 给net_device结构体上锁 */
+	netif_addr_lock_bh(netdev);
+
+	/* 判断此mac地址类型 */
+	if (is_unicast_ether_addr(addr)) {
+		/* 遍历单播mac地址链表 */
+		list_for_each_entry(ha, &netdev->uc.list, list) {
+			/* 检查该单播地址链表中是否存在此mac，且此mac地址标志为单播 */
+			if ((!memcmp(ha->addr, addr, netdev->addr_len)) &&
+				(ha->type == NETDEV_HW_ADDR_T_UNICAST)) {
+				isexist = true;
+				goto out;
+			}
+		}
+	} else {
+		/* 遍历组播mac地址链表 */
+		list_for_each_entry(ha, &netdev->mc.list, list) {
+			/* 检查该组播地址链表中是否存在此mac，且此mac地址类型为组播 */
+			if ((!memcmp(ha->addr, addr, netdev->addr_len)) &&
+				(ha->type == NETDEV_HW_ADDR_T_MULTICAST)) {
+				isexist = true;
+				goto out;
+			}
+		}
+	}
+
+out:
+	/* 给net_device结构体释放锁 */
+	netif_addr_unlock_bh(netdev);
+
+	return isexist;
+}
+
+/**
+ * zxdh_dev_list_addr_add - 在地址链表中添加此mac地址
+ * @netdev: 网络设备结构体
+ * @addr: 要添加的mac地址
+ * @addr_type: mac地址类型
+ */
+int32_t zxdh_dev_list_addr_add(struct net_device *netdev, const uint8_t *addr)
+{
+	int32_t err = 0;
+
+	/* 给net_device结构体上锁 */
+	netif_addr_lock_bh(netdev);
+
+	/* 判断此mac地址类型 */
+	if (is_unicast_ether_addr(addr)) {
+		/* 将此mac地址添加到地址链表中 */
+		err = list_hw_addr_create(&netdev->uc, addr, netdev->addr_len,
+								  NETDEV_HW_ADDR_T_UNICAST, false, false);
+		if (err != 0) {
+			LOG_ERR("list_hw_addr_create failed\n");
+		}
+	} else {
+		err = list_hw_addr_create(&netdev->mc, addr, netdev->addr_len,
+								  NETDEV_HW_ADDR_T_MULTICAST, false, false);
+		if (err != 0) {
+			LOG_ERR("list_hw_addr_create failed\n");
+		}
+	}
+
+	/* 给net_device结构体释放锁 */
+	netif_addr_unlock_bh(netdev);
+
+	return err;
+}
+
+/**
+ * zxdh_dev_list_addr_del - 在地址链表中删除此mac地址
+ * @netdev: 网络设备结构体
+ * @addr: 要删除的mac地址
+ * @addr_type: mac地址类型
+ */
+int32_t zxdh_dev_list_addr_del(struct net_device *netdev, const uint8_t *addr)
+{
+	struct netdev_hw_addr *ha = NULL;
+	int32_t err = 0;
+
+	/* 给net_device上锁 */
+	netif_addr_lock_bh(netdev);
+
+	if (is_unicast_ether_addr(addr)) {
+		/* 遍历单播mac地址链表 */
+		list_for_each_entry(ha, &netdev->uc.list, list) {
+			/* 检查该单播地址链表中是否存在此mac，且此mac地址标志为单播 */
+			if ((!memcmp(ha->addr, addr, netdev->addr_len)) &&
+				(ha->type == NETDEV_HW_ADDR_T_UNICAST)) {
+				/* 从单播地址链表中删除此mac */
+				err = list_hw_addr_del(&netdev->uc, ha);
+				if (err != 0) {
+					LOG_ERR("list_hw_addr_del failed\n");
+				}
+				goto out;
+			}
+		}
+	} else {
+		/* 遍历组播mac地址链表 */
+		list_for_each_entry(ha, &netdev->mc.list, list) {
+			/* 检查该组播地址链表中是否存在此mac，且此mac地址标志为组播 */
+			if ((!memcmp(ha->addr, addr, netdev->addr_len)) &&
+				(ha->type == NETDEV_HW_ADDR_T_MULTICAST)) {
+				/* 从组播地址链表中删除此mac */
+				err = list_hw_addr_del(&netdev->mc, ha);
+				if (err != 0) {
+					LOG_ERR("list_hw_addr_del failed\n");
+				}
+				goto out;
+			}
+		}
+	}
+
+out:
+	/* 给net_device结构体释放锁 */
+	netif_addr_unlock_bh(netdev);
+
+	return err;
+}
+
+#ifdef MAC_CONFIG_DEBUG
+int32_t zxdh_pf_dump_all_mac(struct zxdh_en_device *en_dev)
+{
+	MAC_VPORT_INFO *unicast_mac_arry = NULL;
+	MAC_VPORT_INFO *multicast_mac_arry = NULL;
+	uint32_t current_unicast_num = 0;
+	uint32_t current_multicast_num = 0;
+	int32_t err = 1;
+	int32_t i = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	/* 开辟单播数组和组播数组*/
+	unicast_mac_arry = (MAC_VPORT_INFO *)kzalloc(
+			sizeof(MAC_VPORT_INFO) * UNICAST_MAX_NUM, GFP_KERNEL);
+	if (unicast_mac_arry == NULL) {
+		LOG_ERR("kzalloc unicast_mac_arry failed \n");
+		return err;
+	}
+
+	multicast_mac_arry = (MAC_VPORT_INFO *)kzalloc(
+			sizeof(MAC_VPORT_INFO) * MULTICAST_MAX_NUM, GFP_KERNEL);
+	if (multicast_mac_arry == NULL) {
+		LOG_ERR("kzalloc multicast_mac_arry failed \n");
+		goto out1;
+	}
+
+	/* 从NP中dump所有单播mac地址*/
+	err = dpp_unicast_mac_dump(&pf_info, unicast_mac_arry,
+							   &current_unicast_num);
+	if (err != 0) {
+		LOG_ERR("dpp_unicast_mac_dump failed\n");
+		goto out2;
+	}
+
+	/* 从NP中dump所有组播mac地址*/
+	err = dpp_multicast_mac_dump(&pf_info, multicast_mac_arry,
+								 &current_multicast_num);
+	if (err != 0) {
+		LOG_ERR("dpp_multicast_mac_dump failed\n");
+		goto out2;
+	}
+
+	for (i = 0; i < current_unicast_num; ++i) {
+		LOG_INFO("unicast_mac_arry[%d].vport is %#x\n", i,
+				 unicast_mac_arry[i].vport);
+		LOG_INFO("unicast_mac_arry[%d].mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
+				 i, unicast_mac_arry[i].addr[0], unicast_mac_arry[i].addr[1],
+				 unicast_mac_arry[i].addr[2], unicast_mac_arry[i].addr[3],
+				 unicast_mac_arry[i].addr[4], unicast_mac_arry[i].addr[5]);
+	}
+	for (i = 0; i < current_multicast_num; ++i) {
+		LOG_INFO("multicast_mac_arry[%d].vport is %#x\n", i,
+				 multicast_mac_arry[i].vport);
+		LOG_INFO(
+				"multicast_mac_arry[%d].mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
+				i, multicast_mac_arry[i].addr[0], multicast_mac_arry[i].addr[1],
+				multicast_mac_arry[i].addr[2], multicast_mac_arry[i].addr[3],
+				multicast_mac_arry[i].addr[4], multicast_mac_arry[i].addr[5]);
+	}
+
+out2:
+	if (multicast_mac_arry != NULL) {
+		kfree(multicast_mac_arry);
+	}
+
+out1:
+	if (unicast_mac_arry != NULL) {
+		kfree(unicast_mac_arry);
+	}
+
+	return err;
+}
+#endif /* MAC_CONFIG_DEBUG */
+
+int32_t unicast_mac_add(struct zxdh_en_device *en_dev, struct net_device *dev,
+						const uint8_t *addr, uint16_t flags)
+{
+	int32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	/* 判断目前所配置mac地址数量是否超过上限 */
+	if (en_dev->curr_unicast_num >= DEV_UNICAST_MAX_NUM - 1) {
+		LOG_ERR("curr_unicast_num is beyond maximum\n");
+		return -ENOSPC;
+	}
+
+	/* 遍历单播地址链表，判断是否存在此单播mac */
+	if (is_this_mac_exist(dev, addr)) {
+		LOG_DEBUG("Mac already exists\n");
+		if (!(flags & NLM_F_EXCL)) {
+			return 0;
+		}
+		return -EEXIST;
+	}
+
+	/* 如果待配置mac和本机mac相同，则不配置到NP中， 只将此mac添加到单播地址链表中
+   */
+	if (!memcmp(addr, dev->dev_addr, dev->addr_len)) {
+		goto out;
+	}
+
+	/* 将此mac地址配置到np中 */
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		err = dpp_add_mac(&pf_info, addr);
+		if (err != 0) {
+			LOG_ERR("dpp_add_mac failed\n");
+			return err;
+		}
+	} else {
+		err = zxdh_vf_dpp_add_mac(en_dev, addr, FILTER_MAC);
+		if (err != 0) {
+			LOG_ERR("zxdh_vf_dpp_add_mac failed\n");
+			return err;
+		}
+	}
+
+out:
+	/* 将此单播mac地址添加到地址链表中 */
+	err = zxdh_dev_list_addr_add(dev, addr);
+	if (err != 0) {
+		LOG_ERR("zxdh_dev_list_addr_add failed\n");
+		return err;
+	}
+	en_dev->curr_unicast_num++;
+	LOG_DEBUG("curr_unicast_num is %d\n", en_dev->curr_unicast_num);
+	return err;
+}
+
+int32_t multicast_mac_add(struct zxdh_en_device *en_dev, struct net_device *dev,
+						  const uint8_t *addr, uint16_t flags)
+{
+	int32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	/* 判断目前所配置mac地址数量是否超过上限*/
+	if (en_dev->curr_multicast_num >= DEV_MULTICAST_MAX_NUM) {
+		LOG_ERR("curr_multicast_num is beyond maximum\n");
+		return -ENOSPC;
+	}
+
+	/* 遍历组播地址链表，判断是否存在此mac */
+	if (is_this_mac_exist(dev, addr)) {
+		LOG_DEBUG("Mac already exists\n");
+		if (!(flags & NLM_F_EXCL)) {
+			return 0;
+		}
+		return -EEXIST;
+	}
+
+	/* 将此组播mac地址配置到np中 */
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		err = dpp_multi_mac_add_member(&pf_info, addr);
+		if (err != 0) {
+			LOG_ERR("dpp_multi_mac_add_member failed\n");
+			return err;
+		}
+	} else {
+		err = zxdh_vf_dpp_add_mac(en_dev, addr, FILTER_MAC);
+		if (err != 0) {
+			LOG_ERR("zxdh_vf_dpp_add_mac failed\n");
+			return err;
+		}
+	}
+
+	/* 将此组播mac地址添加到地址链表中 */
+	err = zxdh_dev_list_addr_add(dev, addr);
+	if (err != 0) {
+		LOG_ERR("zxdh_dev_list_addr_add failed\n");
+		return err;
+	}
+	en_dev->curr_multicast_num++;
+	LOG_DEBUG("curr_multicast_num is %d\n", en_dev->curr_multicast_num);
+
+	return err;
+}
+
+int32_t ipv6_multicast_mac_add(struct zxdh_en_device *en_dev,
+							   struct net_device *dev, const uint8_t *addr)
+{
+	int32_t err = 1;
+	int i = 0;
+	MAC_VPORT_INFO *multicast_mac_arry = NULL;
+	uint32_t current_multicast_num = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	/* VF流程 */
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		err = zxdh_vf_dpp_add_ipv6_mac(en_dev, addr);
+		if (err != 0) {
+			LOG_ERR("zxdh_vf_dpp_add_ipv6_mac failed\n");
+			return err;
+		}
+		en_dev->curr_multicast_num++;
+		return 0;
+	}
+
+	/* PF流程 */
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	/* 开辟组播数组*/
+	multicast_mac_arry = (MAC_VPORT_INFO *)kzalloc(
+			sizeof(MAC_VPORT_INFO) * MULTICAST_MAX_NUM, GFP_KERNEL);
+	if (multicast_mac_arry == NULL) {
+		LOG_ERR("kzalloc multicast_mac_arry failed \n");
+		return err;
+	}
+
+	/* 从NP中dump所有组播mac地址、总数量*/
+	err = dpp_multicast_mac_dump(&pf_info, multicast_mac_arry,
+								 &current_multicast_num);
+	if (err != 0) {
+		LOG_ERR("dpp_multicast_mac_dump failed\n");
+		goto out;
+	}
+
+	/* 判断NP中是否已经存储此多播MAC */
+	for (i = 0; i < current_multicast_num; ++i) {
+		if (memcmp(multicast_mac_arry[i].addr, addr, ETH_ALEN) == 0) {
+			LOG_ERR("Multicast MAC Address: %pM Exist, can't add!!",
+					multicast_mac_arry[i].addr);
+			err = 0;
+			goto out;
+		}
+	}
+
+	/* 判断目前NP中所配置mac地址数量是否超过上限*/
+	if (current_multicast_num >= DEV_MULTICAST_MAX_NUM) {
+		LOG_ERR("curr_multicast_num is beyond maximum, can't add!!\n");
+		err = 1;
+		goto out;
+	}
+
+	/* 将此组播mac地址配置到np中 */
+	err = dpp_multi_mac_add_member(&pf_info, addr);
+	if (err != 0) {
+		LOG_ERR("dpp_multi_mac_add_member failed\n");
+		goto out;
+	}
+
+	en_dev->curr_multicast_num++;
+	LOG_DEBUG("%s: curr_multicast_num is %d\n", en_dev->netdev->name,
+			  en_dev->curr_multicast_num);
+
+out:
+	if (multicast_mac_arry != NULL) {
+		kfree(multicast_mac_arry);
+	}
+
+	return err;
+}
+
+int32_t unicast_mac_del(struct zxdh_en_device *en_dev, struct net_device *dev,
+						const uint8_t *addr)
+{
+	int32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	/* 判断目前所配置mac地址数量是否小于0 */
+	if (en_dev->curr_unicast_num <= 0) {
+		LOG_ERR("curr_unicast_num is less than 0\n");
+		return -ENOENT;
+	}
+
+	/* 遍历单播地址链表，判断是否存在此mac */
+	if (!is_this_mac_exist(dev, addr)) {
+		LOG_DEBUG("Mac is not exists\n");
+		return -ENOENT;
+	}
+
+	/* 如果待删除mac和本机mac相同，则不从NP中删除，只从链表中删除 */
+	if (!memcmp(addr, dev->dev_addr, dev->addr_len)) {
+		goto out;
+	}
+
+	/* 从np中删除此单播mac */
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		/* 此设备为PF */
+		err = dpp_del_mac(&pf_info, addr);
+		if (err != 0) {
+			LOG_ERR("dpp_del_mac failed\n");
+			return err;
+		}
+		LOG_DEBUG("dpp_del_mac succeed\n");
+	} else {
+		/* 此设备为VF */
+		err = zxdh_vf_dpp_del_mac(en_dev, addr, FILTER_MAC, true);
+		if (err != 0) {
+			LOG_ERR("zxdh_vf_dpp_del_mac failed\n");
+			return err;
+		}
+		LOG_DEBUG("zxdh_vf_dpp_del_mac succeed\n");
+	}
+
+out:
+	/* 从链表中删除单播mac */
+	err = zxdh_dev_list_addr_del(dev, addr);
+	if (err != 0) {
+		LOG_ERR("zxdh_dev_list_addr_del failed\n");
+		return err;
+	}
+	en_dev->curr_unicast_num--;
+	LOG_DEBUG("curr_unicast_num is %d\n", en_dev->curr_unicast_num);
+	return err;
+}
+
+int32_t multicast_mac_del(struct zxdh_en_device *en_dev, struct net_device *dev,
+						  const uint8_t *addr)
+{
+	int32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	/* 判断目前所配置mac地址数量是否小于0 */
+	if (en_dev->curr_multicast_num <= 0) {
+		LOG_ERR("curr_multicast_num is less than 0\n");
+		return -ENOENT;
+	}
+
+	/* 遍历组播地址链表，判断是否存在此组播mac，如果不存在，则返回报错 */
+	if (!is_this_mac_exist(dev, addr)) {
+		LOG_DEBUG("Mac is not exists\n");
+		return -ENOENT;
+	}
+
+	/* 从np中删除此组播mac */
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		/* 此设备为PF */
+		err = dpp_multi_mac_del_member(&pf_info, addr);
+		if (err != 0) {
+			LOG_ERR("dpp_multi_mac_del_member failed\n");
+			return err;
+		}
+		LOG_DEBUG("dpp_multi_mac_del_member succeed\n");
+	} else {
+		/* 此设备为VF */
+		err = zxdh_vf_dpp_del_mac(en_dev, addr, FILTER_MAC, true);
+		if (err != 0) {
+			LOG_ERR("zxdh_vf_dpp_del_mac failed\n");
+			return err;
+		}
+	}
+
+	/* 从链表中删除组播mac */
+	err = zxdh_dev_list_addr_del(dev, addr);
+	if (err != 0) {
+		LOG_ERR("zxdh_dev_list_addr_del failed\n");
+		return err;
+	}
+	en_dev->curr_multicast_num--;
+	LOG_DEBUG("curr_multicast_num is %d\n", en_dev->curr_multicast_num);
+
+	return err;
+}
+
+int32_t ipv6_multicast_mac_del(struct zxdh_en_device *en_dev,
+							   struct net_device *dev, const uint8_t *addr)
+{
+	int32_t err = 1;
+	int i = 0;
+	MAC_VPORT_INFO *multicast_mac_arry = NULL;
+	uint32_t current_multicast_num = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	/* VF流程 */
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		err = zxdh_vf_dpp_del_ipv6_mac(en_dev, addr);
+		if (err != 0) {
+			LOG_ERR("zxdh_vf_dpp_del_ipv6_mac failed\n");
+			return err;
+		}
+		en_dev->curr_multicast_num--;
+		return 0;
+	}
+
+	/* PF流程 */
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	/* 开辟组播数组*/
+	multicast_mac_arry = (MAC_VPORT_INFO *)kzalloc(
+			sizeof(MAC_VPORT_INFO) * MULTICAST_MAX_NUM, GFP_KERNEL);
+	if (multicast_mac_arry == NULL) {
+		LOG_ERR("kzalloc multicast_mac_arry failed \n");
+		return err;
+	}
+
+	/* 从NP中dump所有组播mac地址、总数量*/
+	err = dpp_multicast_mac_dump(&pf_info, multicast_mac_arry,
+								 &current_multicast_num);
+	if (err != 0) {
+		LOG_ERR("dpp_multicast_mac_dump failed\n");
+		goto out;
+	}
+
+	/* 判断NP中是否已经删除此多播MAC */
+	for (i = 0; i < current_multicast_num; ++i) {
+		if (memcmp(multicast_mac_arry[i].addr, addr, ETH_ALEN) != 0) {
+			LOG_ERR("Multicast MAC Address: %pM don't Exist, can't delete!!",
+					multicast_mac_arry[i].addr);
+			err = 0;
+			goto out;
+		}
+	}
+
+	/* 判断目前NP中所配置mac地址数量是否小于0 */
+	if (current_multicast_num <= 0) {
+		LOG_ERR("curr_multicast_num is less than 0\n");
+		err = 1;
+		goto out;
+	}
+
+	/* 从np中删除此组播mac */
+	err = dpp_multi_mac_del_member(&pf_info, addr);
+	if (err != 0) {
+		LOG_ERR("dpp_multi_mac_del_member failed\n");
+		goto out;
+	}
+	LOG_DEBUG("dpp_multi_mac_del_member succeed\n");
+
+	en_dev->curr_multicast_num--;
+	LOG_DEBUG("%s: curr_multicast_num is %d\n", en_dev->netdev->name,
+			  en_dev->curr_multicast_num);
+
+out:
+	if (multicast_mac_arry != NULL) {
+		kfree(multicast_mac_arry);
+	}
+
+	return err;
+}
+
+int32_t zxdh_en_set_vepa(struct zxdh_en_device *en_dev, bool setting)
+{
+	struct zxdh_vf_item *vf_item = NULL;
+	bool vepa = false;
+	uint16_t vf_idx = 0;
+	int32_t ret = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	vepa = en_dev->ops->get_vepa(en_dev->parent);
+	if (setting == vepa) {
+		LOG_ERR("vport(0x%x) is now %s mode\n", en_dev->vport,
+				vepa ? "vepa" : "veb");
+		return 0;
+	}
+
+	en_dev->ops->set_vepa(en_dev->parent, setting);
+	ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VEPA_EN_OFF,
+								(uint32_t)setting);
+	if (ret != 0) {
+		LOG_ERR("Failed to setup vport(0x%x) %s mode, ret: %d\n", en_dev->vport,
+				setting ? "vepa" : "veb", ret);
+		return ret;
+	}
+
+	for (vf_idx = 0; vf_idx < ZXDH_VF_NUM_MAX; vf_idx++) {
+		vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx);
+		if (IS_ERR_OR_NULL(vf_item)) {
+			break;
+		}
+
+		if (vf_item->is_probed) {
+			pf_info.vport = vf_item->vport;
+			ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VEPA_EN_OFF,
+										(uint32_t)setting);
+			if (ret != 0) {
+				LOG_ERR("Failed to setup vport(0x%x) %s mode, ret: %d\n",
+						vf_item->vport, setting ? "vepa" : "veb", ret);
+				return ret;
+			}
+			LOG_INFO("Configure vport(0x%x) to %s mode\n", vf_item->vport,
+					 setting ? "vepa" : "veb");
+		}
+	}
+
+	LOG_INFO("Configure vport(0x%x) to %s mode\n", en_dev->vport,
+			 setting ? "vepa" : "veb");
+
+	return ret;
+}
+
+#ifdef HAVE_FDB_OPS
+#if defined(HAVE_NDO_FDB_ADD_EXTACK)
+static int zxdh_en_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
+							   struct net_device *dev,
+							   const unsigned char *addr, u16 vid, u16 flags,
+							   struct netlink_ext_ack *extack)
+#elif defined(HAVE_NDO_FDB_ADD_VID)
+static int zxdh_en_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
+							   struct net_device *dev,
+							   const unsigned char *addr, u16 vid, u16 flags)
+#elif defined(HAVE_NDO_FDB_ADD_NLATTR)
+static int zxdh_en_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
+							   struct net_device *dev,
+							   const unsigned char *addr, u16 flags)
+#elif defined(USE_CONST_DEV_UC_CHAR)
+static int zxdh_en_ndo_fdb_add(struct ndmsg *ndm, struct net_device *dev,
+							   const unsigned char *addr, u16 flags)
+#else
+static int zxdh_en_ndo_fdb_add(struct ndmsg *ndm, struct net_device *dev,
+							   unsigned char *addr, u16 flags)
+#endif
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(dev);
+	struct zxdh_en_device *en_dev =
+			&en_priv->edev; /*aux层net_device的私有结构体 */
+	int32_t err = 0;
+
+#ifdef MAC_CONFIG_DEBUG
+	LOG_DEBUG("vport is %#x\n", en_dev->vport);
+	LOG_DEBUG("addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", addr[0], addr[1],
+			  addr[2], addr[3], addr[4], addr[5]);
+	LOG_DEBUG("ndm_state is %u\n", ndm->ndm_state);
+#endif /* MAC_CONFIG_DEBUG */
+
+	/* 检查这个设备的ndm状态是否是静态的 */
+	if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
+		LOG_ERR("FDB only supports static addresses\n");
+		return -EINVAL;
+	}
+
+	/* 判断mac地址是否全0 */
+	if (is_zero_ether_addr(addr)) {
+		LOG_ERR("Invalid mac\n");
+		return -EINVAL;
+	}
+
+	if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
+		err = unicast_mac_add(en_dev, dev, addr, flags);
+		if (err != 0) {
+			LOG_ERR("unicast_mac_add failed");
+			return err;
+		}
+	} else if (is_multicast_ether_addr(addr)) {
+		err = multicast_mac_add(en_dev, dev, addr, flags);
+		if (err != 0) {
+			LOG_ERR("multicast_mac_add failed");
+			return err;
+		}
+	} else {
+		err = -EINVAL;
+	}
+
+#ifdef MAC_CONFIG_DEBUG
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		err = zxdh_pf_dump_all_mac(en_dev);
+		if (err != 0) {
+			LOG_INFO("zxdh_pf_dump_all_mac failed\n");
+			return err;
+		}
+	}
+#endif /* MAC_CONFIG_DEBUG */
+
+	LOG_DEBUG("zxdh_en_ndo_fdb_add end\n");
+	return err;
+}
+
+#ifdef HAVE_NDO_FEATURES_CHECK
+static netdev_features_t zxdh_en_features_check(struct sk_buff *skb,
+												struct net_device *dev,
+												netdev_features_t features)
+{
+	return features;
+}
+#endif /* HAVE_NDO_FEATURES_CHECK */
+
+#ifdef USE_CONST_DEV_UC_CHAR
+#ifdef HAVE_NDO_FDB_ADD_VID
+static int zxdh_en_ndo_fdb_del(struct ndmsg *ndm, struct nlattr **nla,
+							   struct net_device *dev,
+							   const unsigned char *addr, u16 vid)
+#else
+static int zxdh_en_ndo_fdb_del(struct ndmsg *ndm, struct net_device *dev,
+							   const unsigned char *addr)
+#endif
+#else
+#ifdef HAVE_NDO_FDB_ADD_VID
+static int zxdh_en_ndo_fdb_del(struct ndmsg *ndm, struct net_device *dev,
+							   unsigned char *addr, u16 vid)
+#else
+static int zxdh_en_ndo_fdb_del(struct ndmsg *ndm, struct net_device *dev,
+							   unsigned char *addr)
+#endif
+#endif
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(dev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t err = 0;
+
+#ifdef MAC_CONFIG_DEBUG
+	LOG_DEBUG("the vport is %#x", en_dev->vport);
+	LOG_DEBUG("the addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", addr[0], addr[1],
+			  addr[2], addr[3], addr[4], addr[5]);
+	LOG_DEBUG("ndm_state is %u,\n", ndm->ndm_state);
+#endif /* MAC_CONFIG_DEBUG */
+
+	/* 检查这个设备的ndm状态是否是静态的 */
+	if (!(ndm->ndm_state & NUD_PERMANENT)) {
+		LOG_ERR("FDB only supports static addresses\n");
+		return -EINVAL;
+	}
+
+	/* 地址是否全为0 */
+	if (is_zero_ether_addr(addr)) {
+		LOG_ERR("Invalid mac address\n");
+		return -EINVAL;
+	}
+
+	/* 根据mac地址类型，对相对应地址链表做删除操作 */
+	if (is_unicast_ether_addr(addr)) {
+		err = unicast_mac_del(en_dev, dev, addr);
+		if (err != 0) {
+			LOG_ERR("unicast_mac_del failed\n");
+			return err;
+		}
+	} else if (is_multicast_ether_addr(addr)) {
+		err = multicast_mac_del(en_dev, dev, addr);
+		if (err != 0) {
+			LOG_ERR("multicast_mac_del failed\n");
+			return err;
+		}
+	} else {
+		return -EINVAL;
+	}
+
+#ifdef MAC_CONFIG_DEBUG
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		/*先dump所有mac地址*/
+		err = zxdh_pf_dump_all_mac(en_dev);
+		if (err != 0) {
+			LOG_ERR("zxdh_pf_dump_all_mac failed\n");
+			return err;
+		}
+	}
+#endif /* MAC_CONFIG_DEBUG */
+
+	LOG_DEBUG("zxdh_en_ndo_fdb_del end\n");
+	return err;
+}
+
+#ifdef HAVE_BRIDGE_ATTRIBS
+#if defined(HAVE_NDO_BRIDGE_SETLINK_EXTACK)
+static int zxdh_en_ndo_bridge_setlink(struct net_device *dev,
+									  struct nlmsghdr *nlh, u16 flags,
+									  struct netlink_ext_ack *extack)
+#elif defined(HAVE_NDO_BRIDGE_SET_DEL_LINK_FLAGS)
+static int zxdh_en_ndo_bridge_setlink(struct net_device *dev,
+									  struct nlmsghdr *nlh, u16 flags)
+#else
+static int zxdh_en_ndo_bridge_setlink(struct net_device *dev,
+									  struct nlmsghdr *nlh)
+#endif
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(dev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct nlattr *attr = NULL;
+	struct nlattr *br_spec = NULL;
+	int32_t rem = 0;
+	uint16_t mode = BRIDGE_MODE_UNDEF;
+	bool setting = false;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) {
+		return -EOPNOTSUPP;
+	}
+
+	br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
+	if (br_spec == NULL) {
+		return -EINVAL;
+	}
+
+	nla_for_each_nested(attr, br_spec, rem) {
+		if (nla_type(attr) != IFLA_BRIDGE_MODE) {
+			continue;
+		}
+
+		if (nla_len(attr) < sizeof(mode)) {
+			return -EINVAL;
+		}
+
+		mode = nla_get_u16(attr);
+		if (mode > BRIDGE_MODE_VEPA) {
+			return -EINVAL;
+		}
+		break;
+	}
+
+	if (mode == BRIDGE_MODE_UNDEF) {
+		return -EINVAL;
+	}
+
+	setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0;
+
+	return zxdh_en_set_vepa(en_dev, setting);
+}
+
+#ifdef HAVE_NDO_BRIDGE_GETLINK_NLFLAGS
+static int zxdh_en_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
+									  struct net_device *dev,
+									  u32 __always_unused filter_mask,
+									  int nlflags)
+#elif defined(HAVE_BRIDGE_FILTER)
+static int zxdh_en_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
+									  struct net_device *dev,
+									  u32 __always_unused filter_mask)
+#else
+static int zxdh_en_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
+									  struct net_device *dev)
+#endif /* NDO_BRIDGE_STUFF */
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(dev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint8_t mode = 0;
+	bool vepa = false;
+
+	vepa = en_dev->ops->get_vepa(en_dev->parent);
+	mode = vepa ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
+
+	return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode, 0, 0, nlflags,
+								   filter_mask, NULL);
+}
+#endif /* HAVE_BRIDGE_ATTRIBS */
+#endif /* HAVE_FDB_OPS */
+
+static int32_t zxdh_pf_notify_vf_reset(struct zxdh_en_device *en_dev,
+									   int vf_idx)
+{
+	int32_t retval = 0;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack;
+
+	msg.hdr_vf.op_code = ZXDH_SET_VF_RESET;
+	msg.hdr_vf.dst_pcie_id = FIND_VF_PCIE_ID(en_dev->pcie_id, vf_idx);
+
+	retval = zxdh_send_command_to_specify(en_dev, MODULE_PF_BAR_MSG_TO_VF, &msg,
+										  &ack);
+	if (retval != 0) {
+		LOG_ERR("zxdh_send_command_to_vf failed: %d\n", retval);
+	}
+	return retval;
+}
+
+static int32_t zxdh_pf_notify_vf_set_link_state(struct zxdh_en_device *en_dev,
+												int vf_idx, bool link_up)
+{
+	int32_t retval = 0;
+	uint16_t func_no = 0;
+	uint16_t pf_no = FIND_PF_ID(en_dev->pcie_id);
+	uint8_t link_info = 0;
+	uint8_t link_up_val = 0;
+	uint8_t phyport_val = 0;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack = { 0 };
+
+	msg.hdr_to_agt.op_code = AGENT_DEV_STATUS_NOTIFY;
+	msg.hdr_to_agt.pcie_id = en_dev->pcie_id;
+
+	func_no = GET_FUNC_NO(pf_no, vf_idx);
+	LOG_DEBUG("vf_idx:%d, func_no=0x%x\n", vf_idx, func_no);
+	msg.pcie_msix_msg.func_no[msg.pcie_msix_msg.num++] = func_no;
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		link_up_val = link_up ? 1 : 0;
+		phyport_val = en_dev->ops->get_pf_phy_port(en_dev->parent);
+		link_info = (phyport_val & 0x0F) << 4 | (link_up_val & 0x0F);
+		LOG_DEBUG("phyport and link_up need write to VQM, val: 0x%x\n",
+				  link_info);
+		en_dev->ops->set_vf_link_info(en_dev->parent, vf_idx, link_info);
+	} else {
+		en_dev->ops->set_vf_link_info(en_dev->parent, vf_idx, link_up ? 1 : 0);
+	}
+	LOG_DEBUG("msg.pcie_msix_msg.num:%d\n", msg.pcie_msix_msg.num);
+	retval = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &ack);
+	if (retval != 0) {
+		LOG_ERR("failed to update VF link info\n");
+	}
+	return retval;
+}
+
+static int32_t zxdh_pf_set_vf_link_state(struct zxdh_en_device *en_dev,
+										 int vf_idx, int link_status)
+{
+	int32_t retval = 0;
+	struct zxdh_vf_item *vf_item = NULL;
+	bool pf_link_up = en_dev->ops->get_pf_link_up(en_dev->parent);
+
+	vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx);
+	switch (link_status) {
+	case IFLA_VF_LINK_STATE_AUTO:
+		LOG_DEBUG("[SET_VF_LINK_STATE]--NDO set VF %d link state auto\n",
+				  vf_idx);
+		vf_item->link_forced = FALSE;
+		vf_item->link_up = pf_link_up;
+		break;
+	case IFLA_VF_LINK_STATE_ENABLE:
+		LOG_DEBUG("[SET_VF_LINK_STATE]--NDO set VF %d link state enable\n",
+				  vf_idx);
+		vf_item->link_forced = TRUE;
+		vf_item->link_up = TRUE;
+		break;
+	case IFLA_VF_LINK_STATE_DISABLE:
+		LOG_DEBUG("[SET_VF_LINK_STATE]--NDO set VF %d link state disable\n",
+				  vf_idx);
+		vf_item->link_forced = TRUE;
+		vf_item->link_up = FALSE;
+		break;
+	default:
+		LOG_ERR("[SET_VF_LINK_STATE]--NDO set VF %d - invalid link status %d\n",
+				vf_idx, link_status);
+		return -EINVAL;
+	}
+	LOG_DEBUG("vf_item->is_probed: %s\n",
+			  vf_item->is_probed ? "TRUE" : "FALSE");
+	if (vf_item->is_probed) {
+		/* Notify the VF of its new link state */
+		retval = zxdh_pf_notify_vf_set_link_state(en_dev, vf_idx,
+												  vf_item->link_up);
+		if (0 != retval) {
+			LOG_ERR("[SET_VF_LINK_STATE]--Failed to set VF %d link state %d\n",
+					vf_idx, vf_item->link_up);
+			return retval;
+		}
+	}
+	return retval;
+}
+
+int zxdh_en_ndo_set_vf_link_state(struct net_device *netdev, int vf_idx,
+								  int link_status)
+{
+	int num_vfs = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct pci_dev *pdev = NULL;
+	struct dh_core_dev *dh_dev = NULL;
+
+	dh_dev = en_dev->parent;
+	pdev = en_dev->ops->get_pdev(dh_dev);
+	num_vfs = pci_num_vf(pdev);
+	if ((vf_idx < 0) || (vf_idx >= num_vfs)) {
+		LOG_ERR("[SET_VF_LINK_STATE]--NDO set VF link - invalid VF idx: %d\n",
+				vf_idx);
+		return -EINVAL;
+	}
+	return zxdh_pf_set_vf_link_state(en_dev, vf_idx, link_status);
+}
+
+static int32_t zxdh_pf_set_vf_port_vlan(struct zxdh_en_device *en_dev,
+										int vf_idx, u16 vid, u8 qos,
+										uint16_t vlan_proto)
+{
+	int32_t retval = 0;
+	struct zxdh_vf_item *vf_item = NULL;
+	zxdh_msg_info msg;
+	zxdh_reps_info ack;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	/* 获取pf本地保存的vf变量*/
+	vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx);
+	if (!vf_item->is_probed) {
+		LOG_DEBUG("vf %d is not probed.\n", vf_idx);
+		return -EINVAL;
+	}
+
+	if (vf_item->vlan == vid) {
+		return 0;
+	}
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = vf_item->vport;
+	if (vid) {
+		/* vf端口Vlan strip开启*/
+		retval = dpp_vport_vlan_strip_set(&pf_info, 1);
+		if (retval != 0) {
+			LOG_ERR("dpp_vport_vlan_strip_set failed, retval: %d\n", retval);
+			return retval;
+		}
+		/* 将vlan_id add到表项中*/
+		retval = dpp_vport_vlan_filter_en_set(&pf_info, 1);
+		if (retval != 0) {
+			LOG_ERR("dpp_vport_vlan_filter_en_set failed, retval: %d\n",
+					retval);
+			return retval;
+		}
+
+		retval = dpp_add_vlan_filter(&pf_info, vid);
+		if (0 != retval) {
+			LOG_ERR("failed to add vlan: %d\n", vid);
+			return retval;
+		}
+	} else {
+		/* vf端口vlan strip关闭*/
+		retval = dpp_vport_vlan_strip_set(&pf_info, 0);
+		if (retval != 0) {
+			LOG_ERR("dpp_vport_vlan_strip_set failed, retval: %d\n", retval);
+			return retval;
+		}
+		/* 将Vlan_id 从表项中kill*/
+		retval = dpp_vport_vlan_filter_en_set(&pf_info, 0);
+		if (retval != 0) {
+			LOG_ERR("dpp_vport_vlan_filter_en_set failed, retval: %d\n",
+					retval);
+			return retval;
+		}
+
+		retval = dpp_vlan_filter_init(&pf_info);
+		if (retval != 0) {
+			LOG_ERR("dpp_vlan_filter_init failed: %d\n", retval);
+			return retval;
+		}
+	}
+
+	msg.hdr_vf.op_code = ZXDH_PF_SET_VF_VLAN;
+	msg.hdr_vf.dst_pcie_id = FIND_VF_PCIE_ID(en_dev->pcie_id, vf_idx);
+
+	msg.vf_vlan_msg.vlan_id = vid;
+	msg.vf_vlan_msg.qos = qos;
+	msg.vf_vlan_msg.protocl = vlan_proto;
+	msg.vf_vlan_msg.vf_idx = vf_idx;
+
+	retval = zxdh_send_command_to_specify(en_dev, MODULE_PF_BAR_MSG_TO_VF, &msg,
+										  &ack);
+	if (retval != 0) {
+		LOG_ERR("zxdh_send_command_to_vf failed: %d\n", retval);
+		return retval;
+	}
+
+	/* 更新pf本地的vf vlan信息，用于ip link show显示*/
+	vf_item->vlan = vid;
+	vf_item->qos = qos;
+	return retval;
+}
+
+int zxdh_en_ndo_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_vf_item *vf_item = NULL;
+	int32_t retval = 0;
+	bool delete_flag = true;
+	uint8_t *addr = NULL;
+	uint8_t i = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_id);
+	if (IS_ERR_OR_NULL(vf_item)) {
+		LOG_ERR("Failed to get vf_item, vf_id:%d\n", vf_id);
+		return PTR_ERR(vf_item);
+	}
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = vf_item->vport;
+
+	if (is_multicast_ether_addr(mac)) {
+		LOG_ERR("Invalid Ethernet address %pM for VF %d\n", mac, vf_id);
+		return -EINVAL;
+	}
+
+	if (ether_addr_equal(vf_item->mac, mac)) {
+		LOG_INFO("[SET_VF_MAC]--already using mac address %pM\n", mac);
+		return retval;
+	}
+
+	if (is_zero_ether_addr(mac)) {
+		eth_zero_addr(vf_item->mac);
+		vf_item->pf_set_mac = false;
+		en_dev->ops->set_vf_mac(en_dev->parent, mac, vf_id);
+		eth_zero_addr(vf_item->vf_mac_info.unicast_mac[0]);
+		goto vf_reset;
+	}
+
+	for (i = 1; i < DEV_UNICAST_MAX_NUM; ++i) {
+		addr = vf_item->vf_mac_info.unicast_mac[i];
+		if (!memcmp(vf_item->mac, addr, netdev->addr_len)) {
+			delete_flag = false;
+		}
+	}
+
+	if (delete_flag) {
+		if (!is_zero_ether_addr(vf_item->mac)) {
+			retval = dpp_del_mac(&pf_info, vf_item->mac);
+			if (retval != 0) {
+				LOG_ERR("delete vf old mac in NP failed.\n");
+				return retval;
+			}
+		}
+	}
+
+	vf_item->pf_set_mac = true;
+	en_dev->ops->set_vf_mac(en_dev->parent, mac, vf_id);
+	ether_addr_copy(vf_item->vf_mac_info.unicast_mac[0], mac);
+	ether_addr_copy(vf_item->mac, mac);
+	LOG_INFO("[SET_VF_MAC]--setting MAC %pM on VF %d\n", mac, vf_id);
+
+vf_reset:
+	if (vf_item->is_probed) {
+		retval = zxdh_pf_notify_vf_reset(en_dev, vf_id);
+		if (retval != 0) {
+			LOG_ERR("zxdh_pf_notify_vf_reset failed: %d\n", retval);
+		}
+	}
+
+	return retval;
+}
+
+#ifdef IFLA_VF_VLAN_INFO_MAX
+int zxdh_en_ndo_set_vf_port_vlan(struct net_device *netdev, int vf_id,
+								 u16 vlan_id, u8 qos, __be16 vlan_proto)
+#else
+int zxdh_en_ndo_set_vf_port_vlan(struct net_device *netdev, int vf_id,
+								 u16 vlan_id, u8 qos)
+#endif /* IFLA_VF_VLAN_INFO_MAX */
+{
+	int num_vfs = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct pci_dev *pdev = NULL;
+	struct dh_core_dev *dh_dev = NULL;
+
+	/* Comparing with the mellnox network card, it only supports the configuration
+   * of cvlan*/
+	if (vlan_proto != htons(ETH_P_8021Q)) {
+		return -EPROTONOSUPPORT;
+	}
+	dh_dev = en_dev->parent;
+	pdev = en_dev->ops->get_pdev(dh_dev);
+	num_vfs = pci_num_vf(pdev);
+	if ((vf_id < 0) || (vf_id >= num_vfs)) {
+		LOG_ERR("[SET+VF_VLAN]--NDO set VF vlan - invalid VF idx: %d\n", vf_id);
+		return -EINVAL;
+	}
+	return zxdh_pf_set_vf_port_vlan(en_dev, vf_id, vlan_id, qos, vlan_proto);
+}
+
+int zxdh_en_ndo_set_vf_bw(struct net_device *netdev, int vf_id, int min_tx_rate,
+						  int max_tx_rate)
+{
+	return 0;
+}
+
+int zxdh_en_ndo_get_vf_config(struct net_device *netdev, int vf_idx,
+							  struct ifla_vf_info *ivi)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_vf_item *vf_item = NULL;
+
+	vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx);
+	if (IS_ERR_OR_NULL(vf_item)) {
+		LOG_ERR("Failed to get vf_item, vf_idx:%d\n", vf_idx);
+		return PTR_ERR(vf_item);
+	}
+
+	ivi->vf = vf_idx;
+
+	ether_addr_copy(ivi->mac, vf_item->mac);
+
+#ifdef HAVE_NDO_SET_VF_MIN_MAX_TX_RATE
+	ivi->max_tx_rate = vf_item->max_tx_rate;
+	ivi->min_tx_rate = vf_item->min_tx_rate;
+#else
+	ivi->tx_rate = vf_item->max_tx_rate;
+#endif
+
+	ivi->vlan = vf_item->vlan;
+	ivi->qos = vf_item->qos;
+
+#ifdef HAVE_NDO_SET_VF_LINK_STATE
+	if (vf_item->link_forced == false) {
+		ivi->linkstate = IFLA_VF_LINK_STATE_AUTO;
+	} else if (vf_item->link_up == true) {
+		ivi->linkstate = IFLA_VF_LINK_STATE_ENABLE;
+	} else {
+		ivi->linkstate = IFLA_VF_LINK_STATE_DISABLE;
+	}
+#endif
+
+#ifdef HAVE_VF_SPOOFCHK_CONFIGURE
+	ivi->spoofchk = vf_item->spoofchk;
+#endif
+
+#ifdef HAVE_NDO_SET_VF_TRUST
+	ivi->trusted = vf_item->trusted;
+#endif
+
+	return 0;
+}
+
+int zxdh_en_ndo_set_vf_spoofchk(struct net_device *netdev, int vf_idx,
+								bool enable)
+{
+	int ret = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_vf_item *vf_item = NULL;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx);
+	if (IS_ERR_OR_NULL(vf_item)) {
+		LOG_ERR("Failed to get vf_item, vf_idx:%d\n", vf_idx);
+		return PTR_ERR(vf_item);
+	}
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = vf_item->vport;
+	vf_item->spoofchk = enable;
+	LOG_INFO("vf %d spoof check is %s\n", vf_idx,
+			 vf_item->spoofchk ? "on" : "off");
+	if (vf_item->is_probed) {
+		ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_SPOOFCHK_EN_OFF, enable);
+		if (0 != ret) {
+			LOG_ERR("[SET_VF_SPOOFCHK]--Failed to set vf %d spookchk %s\n",
+					vf_idx, enable ? "on" : "off");
+			return ret;
+		}
+	}
+	return ret;
+}
+
+#ifdef HAVE_NDO_SET_VF_TRUST
+int zxdh_en_ndo_set_vf_trust(struct net_device *netdev, int vf_idx,
+							 bool setting)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_vf_item *vf_item = NULL;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx);
+	if (IS_ERR_OR_NULL(vf_item)) {
+		LOG_ERR("Failed to get vf_item, vf_idx:%d\n", vf_idx);
+		return PTR_ERR(vf_item);
+	}
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = vf_item->vport;
+	vf_item->trusted = setting;
+	LOG_INFO("VF %u is now %strusted\n", vf_idx, setting ? "" : "un");
+	if (vf_item->is_probed && !vf_item->trusted) {
+		LOG_DEBUG("vport[0x%x] promisc and allmulti off\n", vf_item->vport);
+		vf_item->promisc = false;
+		vf_item->mc_promisc = false;
+		dpp_vport_uc_promisc_set(&pf_info, vf_item->promisc);
+		dpp_vport_mc_promisc_set(&pf_info, vf_item->mc_promisc);
+	}
+
+	return 0;
+}
+#endif
+
+int zxdh_en_ndo_set_tx_maxrate(struct net_device *netdev, int qid,
+							   uint32_t max_rate)
+{
+	int rtn = 0;
+	int link_speed = 0;
+	uint32_t flowid = 0;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct dh_core_dev *dh_dev = en_dev->parent;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev->parent);
+
+	LOG_INFO("zxdh_en_set_tx_maxrate start\n");
+
+	/*1. 入参检测：队列号不能超过vf下实际的队列数*/
+	if (qid >= en_dev->curr_queue_pairs) {
+		LOG_ERR("zxdh_en_ndo_set_tx_maxrate : invalid parameter qid=%d\n", qid);
+		return -EINVAL;
+	}
+
+	// if (!en_dev->link_up)
+	// {
+	//     LOG_ERR("[EN SET TX MAXRATE]--PF is not link up.\n");
+	//     return -EINVAL;
+	// }
+
+	link_speed = en_dev->link_speed;
+
+	/*2. 将vf内的队列号，转换成全局flow id；注意>>>>>>>>vqm tx队列与CAR A的flow
+   * id映射关系：一一映射<<<<<<<<*/
+	flowid = zxdh_plcr_vf_qid_2_flowid(en_priv, qid);
+	if (flowid >= PLCR_CAR_A_FLOWID_RES_NUM) {
+		LOG_ERR("zxdh_en_ndo_set_tx_maxrate : invalid parameter flowid=%d\n",
+				flowid);
+		return -EINVAL;
+	}
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		rtn = zxdh_plcr_set_rate_limit(pf_dev, E_PLCR_CAR_A, en_dev->vport,
+									   flowid, max_rate, 0);
+		if (rtn) {
+			LOG_ERR("zxdh_plcr_set_rate_limit failed: %d\n", rtn);
+			return -EINVAL;
+		}
+	} else if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		msg.hdr.op_code = ZXDH_TX_MAXRATE_SET;
+		msg.hdr.vport = en_dev->vport;
+		msg.hdr.pcie_id = en_dev->pcie_id;
+		msg.hdr.vf_id = en_dev->pcie_id & (0xff);
+
+		msg.tx_maxrate_set_msg.flowid = flowid;
+		msg.tx_maxrate_set_msg.max_rate = max_rate;
+
+		rtn = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF,
+										   &msg, &reps);
+		if (rtn) {
+			LOG_ERR("zxdh_send_command_to_specify failed: %d\n", rtn);
+			return -EINVAL;
+		}
+	}
+	LOG_INFO("The maxrate of tx-%u has been set to %u\n", qid, max_rate);
+	return rtn;
+}
+
+/**-------------------------------------------------------------------------------------------------------------------@n
+ * 功能详述:
+ *     - zxdh_en_ndo_set_vf_rate函数属于接口函数, 其功能是:
+ *     - 设置vf端口发送方向，最大速率和最小保证速率
+ *     - 该接口会挂接到内核的钩子上，函数声明是固定的
+ *
+ * 基于plcr的端口限速背景：
+ *     - 1.一级flowid与vqm的2K个（接收和发送）队列是一一映射的
+ *     - 2.二级flow id与vf num的映射关系
+ *         端口限速，需要将vf下的发送队列（即一级flow id）映射到二级flowid
+ *         二级flow id的资源是4K，dpu限制vf数量是1K，即二级flow id数量 > vf数量
+ *         所以规定固定的映射关系：二级flow id前1K <--->
+ *与1K个vf（发送）一一对应 下面的链接整理了pf下vf转换成全局vf（0-1023）的原理
+ *         https://i.zte.com.cn/#/space/4e62cb2b730540ff8721c1a8552b2356/wiki/page/ff8178f1304e45dc9457e92ff196cce5/view
+ *     - 3.vf限速的设置
+ *         项目对vf提出了最小保证带宽的需求；
+ *         二级CAR的限速模板使用：双速率，三色算法，色敏模式
+ *     - 4.创建vf的其它考虑
+ *         参考mlx的做法，vf创建之后，默认关联到vf组0（注意：>>>>>>>>先交付vf端口限速的需求，这一步可以暂时不实现<<<<<<<<）；
+ *         vf创建之后，用户设置限速才会调用到这里，用户不设置限速，vf（二级flow
+ *id）就不用关联限速模板
+ *
+ * 参数概述:
+ *     - netdev      : 网络设备结构体指针
+ *     - vf_id       ：pf内vf的编号（从0开始）
+ *     - min_tx_rate : 最小保证速率
+ *     - max_tx_rate : 最大速率
+ *     - 返回值类型是INT32, 含义是: 错误码，正确时为S_OK
+ *
+ * 引用(类变量,外部变量,接口函数):
+ *     - 无
+ *
+ * 注意：该函数挂接到pf的钩子上，只在pf下执行
+ *--------------------------------------------------------------------------------------------------------------------*/
+int zxdh_en_ndo_set_vf_rate(struct net_device *netdev, int vf_id,
+							int min_tx_rate, int max_tx_rate)
+{
+	int rtn = 0;
+	int ep_id = 0;
+	int pf_func_num = 0;
+	uint32_t flowid = 0;
+
+	struct zxdh_vf_item *vf_item;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct dh_core_dev *dh_dev = en_dev->parent;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev->parent);
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+	/*1. 计算vf是全局编号（0-1023），即为vf tx的flow id*/
+	ep_id = ((en_dev->vport & 0x7000) >> 12);
+	pf_func_num = ((en_dev->vport & 0x0700) >> 8);
+	flowid = 256 * ep_id + 32 * pf_func_num + vf_id; //每个pf下32个vf
+	vf_item = en_dev->ops->get_vf_item(en_dev->parent, (uint16_t)vf_id);
+
+	LOG_INFO("%s-%d:vf_item->vport = 0x%x, flowid = %d\n", __FUNCTION__,
+			 __LINE__, vf_item->vport, flowid);
+
+	rtn = zxdh_plcr_set_rate_limit(pf_dev, E_PLCR_CAR_B, vf_item->vport, flowid,
+								   max_tx_rate, min_tx_rate);
+	if (rtn) {
+		LOG_ERR("zxdh_plcr_set_rate_limit failed: %d\n", rtn);
+		return -EINVAL;
+	}
+	LOG_INFO(
+			"The rate of VF-%u has been set to: min_tx_rate = %u, max_tx_rate = %u\n",
+			vf_id, min_tx_rate, max_tx_rate);
+
+	return rtn;
+}
+
+const struct net_device_ops zxdh_netdev_ops = {
+	.ndo_open = zxdh_en_open,
+	.ndo_stop = zxdh_en_close,
+	.ndo_start_xmit = zxdh_en_xmit,
+
+#if defined(HAVE_NDO_GET_STATS64) || defined(HAVE_VOID_NDO_GET_STATS64)
+	.ndo_get_stats64 = zxdh_en_get_netdev_stats_struct,
+#else
+	.ndo_get_stats = zxdh_en_get_netdev_stats_struct,
+#endif
+	.ndo_set_rx_mode = zxdh_en_set_rx_mode,
+	.ndo_validate_addr = eth_validate_addr,
+	.ndo_set_mac_address = zxdh_en_set_mac,
+
+#ifdef HAVE_RHEL7_EXTENDED_MIN_MAX_MTU
+	.extended.ndo_change_mtu = zxdh_en_change_mtu,
+#else
+	.ndo_change_mtu = zxdh_en_change_mtu,
+#endif /* HAVE_RHEL7_EXTENDED_MIN_MAX_MTU */
+
+	.ndo_do_ioctl = zxdh_en_ioctl,
+#ifdef ZXDH_PLCR_OPEN
+	.ndo_set_tx_maxrate = zxdh_en_ndo_set_tx_maxrate,
+#endif
+	.ndo_tx_timeout = zxdh_en_tx_timeout,
+
+#ifdef HAVE_VLAN_RX_REGISTER
+	.ndo_vlan_rx_register = zxdh_en_vlan_rx_register,
+#endif
+	.ndo_vlan_rx_add_vid = zxdh_en_vlan_rx_add_vid,
+	.ndo_vlan_rx_kill_vid = zxdh_en_vlan_rx_kill_vid,
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+	.ndo_poll_controller = zxdh_en_netpoll,
+#endif
+
+#ifdef HAVE_SETUP_TC
+#ifdef HAVE_RHEL7_NETDEV_OPS_EXT_NDO_SETUP_TC
+	.extended.ndo_setup_tc_rh = __zxdh_en_setup_tc,
+#else
+#ifdef NETIF_F_HW_TC
+	.ndo_setup_tc = __zxdh_en_setup_tc,
+#else
+	.ndo_setup_tc = zxdh_en_setup_tc,
+#endif /* NETIF_F_HW_TC */
+#endif /* HAVE_RHEL7_NETDEV_OPS_EXT_NDO_SETUP_TC */
+#endif /* HAVE_SETUP_TC */
+
+#ifdef HAVE_RHEL7_NET_DEVICE_OPS_EXT
+	.ndo_size = sizeof(const struct net_device_ops),
+#endif
+
+#ifdef IFLA_VF_MAX
+	.ndo_set_vf_mac = zxdh_en_ndo_set_vf_mac,
+#ifdef HAVE_RHEL7_NETDEV_OPS_EXT_NDO_SET_VF_VLAN
+	.extended.ndo_set_vf_vlan = zxdh_en_ndo_set_vf_port_vlan,
+#else
+	.ndo_set_vf_vlan = zxdh_en_ndo_set_vf_port_vlan,
+#endif
+#ifdef HAVE_NDO_SET_VF_MIN_MAX_TX_RATE
+#ifdef ZXDH_PLCR_OPEN
+	.ndo_set_vf_rate = zxdh_en_ndo_set_vf_rate,
+#else
+	.ndo_set_vf_rate = zxdh_en_ndo_set_vf_bw,
+#endif
+#else
+	.ndo_set_vf_rate = zxdh_en_ndo_set_vf_bw,
+#endif
+	.ndo_get_vf_config = zxdh_en_ndo_get_vf_config,
+#ifdef HAVE_VF_SPOOFCHK_CONFIGURE
+	.ndo_set_vf_spoofchk = zxdh_en_ndo_set_vf_spoofchk,
+#endif
+#ifdef HAVE_NDO_SET_VF_TRUST
+#ifdef HAVE_RHEL7_NET_DEVICE_OPS_EXT
+	.extended.ndo_set_vf_trust = zxdh_en_ndo_set_vf_trust,
+#else
+	.ndo_set_vf_trust = zxdh_en_ndo_set_vf_trust,
+#endif /* HAVE_RHEL7_NET_DEVICE_OPS_EXT */
+#endif /* HAVE_NDO_SET_VF_TRUST */
+#endif /* IFLA_VF_MAX */
+
+#ifdef HAVE_UDP_ENC_RX_OFFLOAD
+#ifdef HAVE_VXLAN_RX_OFFLOAD
+#if IS_ENABLED(CONFIG_VXLAN)
+	.ndo_add_vxlan_port = zxdh_en_add_vxlan_port,
+	.ndo_del_vxlan_port = zxdh_en_del_vxlan_port,
+#endif
+#endif /* HAVE_VXLAN_RX_OFFLOAD */
+
+#ifdef HAVE_GENEVE_RX_OFFLOAD
+#if IS_ENABLED(CONFIG_GENEVE)
+	.ndo_add_geneve_port = zxdh_en_add_geneve_port,
+	.ndo_del_geneve_port = zxdh_en_del_geneve_port,
+#endif
+#endif /* HAVE_GENEVE_RX_OFFLOAD */
+#endif /* HAVE_UDP_ENC_RX_OFFLOAD */
+
+#ifdef HAVE_NDO_GET_PHYS_PORT_ID
+	.ndo_get_phys_port_id = zxdh_en_get_phys_port_id,
+#endif /* HAVE_NDO_GET_PHYS_PORT_ID */
+
+	.ndo_set_features = zxdh_en_set_features,
+
+#ifdef HAVE_FDB_OPS
+	.ndo_fdb_add = zxdh_en_ndo_fdb_add,
+	.ndo_fdb_del = zxdh_en_ndo_fdb_del,
+#ifdef HAVE_NDO_FEATURES_CHECK
+	.ndo_features_check = zxdh_en_features_check,
+#endif /* HAVE_NDO_FEATURES_CHECK */
+#ifdef HAVE_BRIDGE_ATTRIBS
+	.ndo_bridge_getlink = zxdh_en_ndo_bridge_getlink,
+	.ndo_bridge_setlink = zxdh_en_ndo_bridge_setlink,
+#endif /* HAVE_BRIDGE_ATTRIBS */
+#endif /* HAVE_FDB_OPS */
+	.ndo_udp_tunnel_add = udp_tunnel_nic_add_port,
+	.ndo_udp_tunnel_del = udp_tunnel_nic_del_port,
+
+#ifdef HAVE_RHEL6_NET_DEVICE_OPS_EXT
+};
+
+/* RHEL6 keeps these operations in a separate structure */
+static const struct net_device_ops_ext zxdh_netdev_ops_ext = {
+	.size = sizeof(struct net_device_ops_ext),
+#endif /* HAVE_RHEL6_NET_DEVICE_OPS_EXT */
+
+#ifdef HAVE_NDO_SET_FEATURES
+	.ndo_set_features = zxdh_en_set_features,
+#endif /* HAVE_NDO_SET_FEATURES */
+
+#ifdef HAVE_NDO_SET_VF_LINK_STATE
+	.ndo_set_vf_link_state = zxdh_en_ndo_set_vf_link_state,
+#endif
+};
+
+static void priv_flags_init(struct zxdh_en_priv *priv)
+{
+	priv->edev.pflags = 0;
+
+	priv->edev.pflags &= BIT(ZXDH_PFLAG_ENABLE_LLDP); /* LLDP默认为开 */
+}
+
+static int32_t get_max_num_qs(struct zxdh_en_container *en_con)
+{
+	return en_con->ops->is_bond(en_con->parent) ? ZXDH_BOND_ETH_MQ_PAIRS_NUM :
+													max_pairs;
+}
+
+static int32_t fw_version_init(struct zxdh_en_device *en_dev)
+{
+	int32_t ret = 0;
+	uint8_t fw_version[ETHTOOL_FWVERS_LEN] = { 0 };
+	uint8_t fw_version_len = 0;
+
+	ret = zxdh_en_firmware_version_get(en_dev, fw_version, &fw_version_len);
+	if (ret != 0) {
+		LOG_ERR("zxdh_en_firmware_version_get err, ret %d!!!!\n", ret);
+		return ret;
+	}
+	if (fw_version_len > ETHTOOL_FWVERS_LEN) {
+		LOG_ERR("fw_version_len (%d) greater than 31!!!!\n", fw_version_len);
+		return -1;
+	}
+
+	fw_version[ETHTOOL_FWVERS_LEN - 1] = '\0';
+	en_dev->fw_version_len = ETHTOOL_FWVERS_LEN;
+	memcpy(en_dev->fw_version, (uint8_t *)fw_version, en_dev->fw_version_len);
+	LOG_INFO("fw_version:%s\n", en_dev->fw_version);
+
+	return 0;
+}
+
+int32_t zxdh_priv_init(struct zxdh_en_priv *priv, struct net_device *netdev)
+{
+	int32_t ret = 0;
+	struct zxdh_en_device *en_dev = &priv->edev;
+
+	mutex_init(&priv->lock);
+	priv_flags_init(priv);
+	en_dev->msglevel = NETIF_MSG_LINK;
+
+	/* 优先级4，暂时写死不支持 */
+	en_dev->wol_support = 0;
+	en_dev->wolopts = 0;
+
+	ret = fw_version_init(en_dev);
+	if (ret != 0) {
+		LOG_ERR("fw_version_init err ret: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+struct net_device *zxdh_create_netdev(struct zxdh_en_container *en_con)
+{
+	struct net_device *netdev = NULL;
+	struct zxdh_en_priv *en_priv = NULL;
+	struct dh_core_dev *dh_dev = en_con->parent;
+
+	netdev = alloc_etherdev_mqs(sizeof(struct zxdh_en_priv),
+								get_max_num_qs(en_con), get_max_num_qs(en_con));
+	if (unlikely(netdev == NULL)) {
+		LOG_ERR("alloc_etherdev_mqs() failed\n");
+		return NULL;
+	}
+
+	en_priv = netdev_priv(netdev);
+
+	en_priv->edev.parent = dh_dev;
+	en_priv->edev.ops = en_con->ops;
+	en_priv->edev.netdev = netdev;
+
+	zxdh_priv_init(en_priv, netdev);
+
+	netif_carrier_off(netdev);
+	netif_tx_disable(netdev);
+	dev_net_set(netdev, dh_core_net(dh_dev));
+
+	return netdev;
+}
+
+void zxdh_netdev_features_init(struct net_device *netdev)
+{
+	netdev->features |= NETIF_F_RXCSUM | NETIF_F_HW_CSUM | NETIF_F_TSO |
+						NETIF_F_SG | NETIF_F_GSO | NETIF_F_LRO | NETIF_F_TSO6 |
+						NETIF_F_GRO | NETIF_F_HW_VLAN_STAG_FILTER |
+						NETIF_F_HW_VLAN_CTAG_FILTER |
+						NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_RXHASH;
+
+	netdev->hw_features |=
+			NETIF_F_RXCSUM | NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_SG |
+			NETIF_F_GSO | NETIF_F_LRO | NETIF_F_TSO6 | NETIF_F_GRO |
+			NETIF_F_HW_VLAN_STAG_FILTER | NETIF_F_HW_VLAN_CTAG_FILTER |
+			NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_HW_VLAN_CTAG_RX |
+			NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_RX |
+			NETIF_F_HW_VLAN_STAG_TX | NETIF_F_RXHASH;
+
+	netdev->hw_enc_features |= NETIF_F_RXCSUM | NETIF_F_HW_CSUM |
+							   NETIF_F_GSO_UDP_TUNNEL_CSUM;
+
+	return;
+}
+
+extern const struct xfrmdev_ops zxdh_xfrmdev_ops;
+static void zxdh_build_nic_netdev(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct dh_core_dev *dh_dev = en_priv->edev.parent;
+
+	SET_NETDEV_DEV(netdev, &dh_dev->parent->pdev->dev);
+
+	netdev->netdev_ops = &zxdh_netdev_ops;
+
+#ifdef ZXDH_SEC
+	/*内核 sec相关*/
+	netdev->features |= NETIF_F_HW_ESP;
+	netdev->xfrmdev_ops = &zxdh_xfrmdev_ops;
+#endif
+
+#ifdef HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT
+	zxdh_en_set_ethtool_ops_ext(netdev);
+#else
+	zxdh_en_set_ethtool_ops(netdev);
+#endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */
+
+	zxdh_netdev_features_init(netdev);
+}
+
+int32_t zxdh_en_bond_get_mac(struct net_device *netdev, uint8_t pannel_id,
+							 uint8_t *mac)
+{
+	int32_t ret = 0;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	msg.hdr_to_agt.op_code = AGENT_FLASH_MAC_READ;
+	msg.flash_read_msg.index = pannel_id;
+
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_FLASH, &msg, &reps);
+	if (ret != 0) {
+		LOG_ERR("zxdh_send_command_to_specify failed: %d\n", ret);
+		return ret;
+	}
+
+	LOG_INFO("bond get mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
+			 reps.flash_mac_read_msg.mac[0], reps.flash_mac_read_msg.mac[1],
+			 reps.flash_mac_read_msg.mac[2], reps.flash_mac_read_msg.mac[3],
+			 reps.flash_mac_read_msg.mac[4], reps.flash_mac_read_msg.mac[5]);
+
+	ether_addr_copy(mac, reps.flash_mac_read_msg.mac);
+	return ret;
+}
+
+int32_t zxdh_mac_addr_init(struct net_device *netdev)
+{
+	uint8_t mac[6] = { 0 };
+	uint8_t pannel_id = 0;
+	int32_t ret = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		pannel_id = en_dev->pannel_id;
+		LOG_INFO("zxdh_mac_addr_init pannel_id:%d", pannel_id);
+		ret = zxdh_en_bond_get_mac(netdev, pannel_id, mac);
+		if (ret != 0) {
+			LOG_ERR("zxdh_en_bond_mac_get failed: %d\n", ret);
+		}
+	} else {
+		en_dev->ops->get_mac(en_dev->parent, mac);
+	}
+
+	if (!is_valid_ether_addr(mac)) {
+		get_random_bytes(mac, 6);
+		mac[0] &= 0xfe;
+		LOG_INFO("set random mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0],
+				 mac[1], mac[2], mac[3], mac[4], mac[5]);
+	}
+	LOG_INFO("set  mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0], mac[1], mac[2],
+			 mac[3], mac[4], mac[5]);
+	memcpy(netdev->dev_addr, mac, 6);
+
+	return ret;
+}
+
+int32_t zxdh_status_init(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	if (en_dev->ops->if_init(en_dev->parent)) {
+		LOG_INFO("vp reset \n");
+		zxdh_vp_reset(netdev);
+	}
+
+	/* Disable VQ/configuration callbacks. */
+	zxdh_vp_disable_cbs(netdev);
+
+	zxdh_add_status(netdev, ZXDH_CONFIG_S_ACKNOWLEDGE);
+
+	zxdh_add_status(netdev, ZXDH_CONFIG_S_DRIVER);
+
+	/* fix features, not set features*/
+	zxdh_pf_features_init(netdev);
+
+	might_sleep();
+	zxdh_add_status(netdev, ZXDH_CONFIG_S_FEATURES_OK);
+	if (!zxdh_has_status(netdev, ZXDH_CONFIG_S_FEATURES_OK)) {
+		LOG_ERR("device refuses features ok\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+void zxdh_device_ready(struct net_device *netdev)
+{
+	zxdh_vp_enable_cbs(netdev);
+
+	zxdh_add_status(netdev, ZXDH_CONFIG_S_DRIVER_OK);
+}
+
+void zxdh_link_state_notify_kernel(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	if (en_dev->ops->get_pf_link_up(en_dev->parent)) {
+		netif_carrier_off(netdev);
+		udelay(10);
+		netif_carrier_on(netdev);
+	} else {
+		netif_carrier_on(netdev);
+		udelay(10);
+		netif_carrier_off(netdev);
+	}
+}
+
+int32_t aux_get_bond_attrs(struct zxdh_en_device *en_dev,
+						   struct zxdh_lag_attrs *attr)
+{
+	*attr = (struct zxdh_lag_attrs){
+		.pannel_id = en_dev->pannel_id,
+		.vport = en_dev->vport,
+		.slot_id = en_dev->slot_id,
+		.qid[0] = en_dev->phy_index[0],
+		.qid[1] = en_dev->phy_index[1],
+		.pcie_id = en_dev->pcie_id,
+		.phy_port = en_dev->phy_port,
+	};
+
+	LOG_INFO("pannel %hu, vport 0x%hx, qid[0] %u, qid[1] %u, pcie id 0x%x\n",
+			 attr->pannel_id, attr->vport, attr->qid[0], attr->qid[1],
+			 attr->pcie_id);
+
+	return 0;
+}
+
+void aux_set_netdev_name(struct net_device *netdev, uint16_t pannel_id)
+{
+	struct zxdh_en_device *en_dev = NULL;
+	struct zxdh_en_priv *en_priv = NULL;
+
+	en_priv = netdev_priv(netdev);
+	en_dev = &en_priv->edev;
+
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		netdev->dev_port = pannel_id + 1;
+	}
+}
+
+int32_t zxdh_en_mtu_init(struct net_device *netdev)
+{
+	netdev->min_mtu = ETH_MIN_MTU;
+	netdev->max_mtu = ZXDH_MAX_MTU;
+
+	return zxdh_en_config_mtu_to_np(netdev, ZXDH_DEFAULT_MTU);
+}
+
+static int32_t zxdh_en_dev_probe(struct auxiliary_device *adev,
+								 const struct auxiliary_device_id *id)
+{
+	struct zxdh_en_container *en_container =
+			container_of(adev, struct zxdh_en_container, adev);
+	struct net_device *netdev = NULL;
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	struct zxdh_lag_attrs lag_attrs;
+	int32_t err = 0;
+	int32_t vqs_channel_num = 0;
+
+	LOG_INFO("aux driver start to probe");
+
+	netdev = zxdh_create_netdev(en_container);
+	if (unlikely(netdev == NULL)) {
+		LOG_ERR("zxdh_create_netdev is null\n");
+		err = -ENOMEM;
+		goto err_create_netdev;
+	}
+
+	zxdh_build_nic_netdev(netdev);
+
+	dev_set_drvdata(&adev->dev, netdev_priv(netdev));
+
+	en_priv = netdev_priv(netdev);
+	en_dev = &en_priv->edev;
+	en_dev->channels_num = en_dev->ops->get_channels_num(en_dev->parent);
+	en_dev->ops->set_rdma_netdev(en_dev->parent, netdev);
+	en_dev->curr_unicast_num = 0;
+	en_dev->curr_multicast_num = 0;
+	en_dev->init_comp_flag = AUX_INIT_INCOMPLETED;
+	en_dev->delay_statistics_enable = 0;
+
+	vqs_channel_num = en_dev->ops->create_vqs_channels(en_dev->parent);
+	if (vqs_channel_num < 0) {
+		LOG_ERR("create_vqs_channels failed, vqs_channel_num: %d\n",
+				vqs_channel_num);
+		err = vqs_channel_num;
+		goto err_create_vqs_channels;
+	}
+
+	err = dh_aux_eq_table_init(en_priv);
+	if (err != 0) {
+		LOG_ERR("Failed to alloc IRQs: %d\n", err);
+		goto err_eq_table_init;
+	}
+
+	err = dh_aux_events_init(en_priv);
+	if (err != 0) {
+		LOG_ERR("dh_aux_events_init failed: %d\n", err);
+		goto err_events_init;
+	}
+
+	err = dh_aux_eq_table_create(en_priv);
+	if (err != 0) {
+		LOG_ERR("Failed to alloc EQs: %d\n", err);
+		goto err_eq_table_create;
+	}
+
+	err = zxdh_status_init(netdev);
+	if (err != 0) {
+		LOG_ERR("zxdh_status_init failed: %d\n", err);
+		goto err_status_init;
+	}
+
+	en_dev->ep_bdf = en_dev->ops->get_epbdf(en_dev->parent);
+	en_dev->vport = en_dev->ops->get_vport(en_dev->parent);
+	en_dev->pcie_id = en_dev->ops->get_pcie_id(en_dev->parent);
+	en_dev->slot_id = en_dev->ops->get_slot_id(en_dev->parent);
+	LOG_INFO("en_dev->ep_bdf: 0x%x, en_dev->vport: 0x%x, en_dev->pcie_id: %d\n",
+			 en_dev->ep_bdf, en_dev->vport, en_dev->pcie_id);
+
+	err = zxdh_vqs_init(netdev);
+	if (err != 0) {
+		LOG_ERR("zxdh_vqs_init failed: %d\n", err);
+		goto err_vqs_init;
+	}
+
+	if (!en_dev->ops->is_bond(en_dev->parent)) {
+		en_dev->hash_func = ZXDH_FUNC_TOP;
+		err = zxdh_hash_id_get(en_dev);
+		if (err != 0) {
+			LOG_ERR("zxdh_hash_id_get failed: %d\n", err);
+			goto err_do_vqs_free;
+		}
+
+		err = zxdh_panel_id_get(en_dev);
+		if (err != 0) {
+			LOG_ERR("zxdh_panel_id_get failed: %d\n", err);
+			goto err_do_vqs_free;
+		}
+	}
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		LOG_INFO(" en_dev->pcie_id: %x is a pf dev\n", en_dev->pcie_id);
+
+		if (!en_dev->ops->is_bond(en_dev->parent)) {
+			err = zxdh_phyport_get(en_dev);
+			if (err != 0) {
+				LOG_ERR("zxdh_phyport_get failed: %d\n", err);
+				goto err_do_vqs_free;
+			}
+		} else {
+			err = zxdh_aux_alloc_pannel(en_dev);
+			if (err != 0) {
+				LOG_ERR("zxdh_aux_alloc_pannel failed: %d\n", err);
+				goto err_do_vqs_free;
+			}
+		}
+
+		err = zxdh_mac_addr_init(netdev);
+		if (err != 0) {
+			LOG_ERR("zxdh_mac_addr_init failed: %d\n", err);
+			goto err_do_vqs_free;
+		}
+
+		err = zxdh_pf_port_init(netdev);
+		if (err != 0) {
+			LOG_ERR("zxdh_pf_port_init failed: %d\n", err);
+			goto err_do_vqs_free;
+		}
+	} else {
+		LOG_INFO(" en_dev->pcie_id: %x is a vf dev\n", en_dev->pcie_id);
+		err = zxdh_vf_dpp_port_init(netdev);
+		if (err != 0) {
+			LOG_ERR("zxdh_vf_dpp_port_init failed: %d\n", err);
+			goto err_do_vqs_free;
+		}
+	}
+
+	if (!en_dev->ops->is_bond(en_dev->parent)) {
+		netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
+		err = zxdh_num_channels_changed(en_dev, en_dev->curr_queue_pairs);
+		if (err != 0) {
+			LOG_ERR("zxdh_num_channels_changed failed: %d\n", err);
+			goto err_do_vport_free;
+		}
+	}
+
+	err = zxdh_common_tbl_init(netdev);
+	if (err != 0) {
+		LOG_ERR("zxdh_common_tlb_init failed: %d\n", err);
+		goto err_do_rxfh_free;
+	}
+
+	zxdh_device_ready(netdev);
+
+	err = zxdh_en_mtu_init(netdev);
+	if (err != 0) {
+		LOG_ERR("zxdh_en_mtu_init failed: %d\n", err);
+		goto err_do_rxfh_free;
+	}
+
+	en_dev->hw_stats.q_stats = kmalloc_array(
+			max_pairs, sizeof(struct zxdh_en_queue_stats), GFP_KERNEL);
+	if (unlikely(en_dev->hw_stats.q_stats == NULL)) {
+		LOG_ERR("hw_stats.q_stats kmalloc failed\n");
+		goto err_do_rxfh_free;
+	}
+	memset(en_dev->hw_stats.q_stats, 0,
+		   max_pairs * sizeof(struct zxdh_en_queue_stats));
+	memset(&en_dev->pre_stats, 0, sizeof(struct zxdh_en_vport_stats));
+
+	err = zxdh_en_vport_pre_stats_get(en_dev);
+	if (err != 0) {
+		LOG_ERR("get vport pre stats failed, %d\n", err);
+		goto err_do_q_stats_free;
+	}
+
+	aux_set_netdev_name(netdev, en_dev->pannel_id);
+	err = register_netdev(netdev);
+	if (err != 0) {
+		LOG_ERR("register_netdev failed, %d\n", err);
+		goto err_do_q_stats_free;
+	}
+
+	zxdh_en_bar_del_mac(netdev);
+	zxdh_en_bar_cfg_mac(netdev, netdev->dev_addr);
+	zxdh_link_state_notify_kernel(netdev);
+
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		aux_get_bond_attrs(en_dev, &lag_attrs);
+		zxdh_ldev_add_netdev(en_container->parent, en_dev->pannel_id, netdev,
+							 &lag_attrs);
+	}
+
+#ifdef ZXDH_PLCR_OPEN
+	err = zxdh_plcr_init(en_priv);
+	if (err != 0) {
+		LOG_ERR("zxdh_plcr_init failed, %d\n", err);
+	}
+#endif
+
+	en_dev->init_comp_flag = AUX_INIT_COMPLETED;
+
+	err = dh_aux_ipv6_notifier_init(en_priv);
+	if (err != 0) {
+		LOG_ERR("dh_aux_ipv6_notifier_init failed: %d\n", err);
+		goto err_ipv6_notifier_init;
+	}
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		en_dev->autoneg_enable = AUTONEG_ENABLE;
+		err = zxdh_en_phyport_init(en_dev);
+		if (err != 0) {
+			LOG_ERR("zxdh_en_phyport_init failed: %d\n", err);
+			goto err_phyport_init;
+		}
+	}
+
+#ifdef ZXDH_MSGQ
+	if (en_dev->need_msgq) {
+		err = zxdh_msgq_init(en_dev);
+		if (err) {
+			LOG_ERR("zxdh_msgq_init failed: %d\n", err);
+			goto err_phyport_init;
+		}
+	}
+#endif
+
+	en_dev->ops->set_init_comp_flag(en_dev->parent);
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		/* clear mcode gate,successfully build the scheduling tree, and then open it
+     * again */
+		zxdh_dcbnl_set_tm_pport_mcode_gate_close(netdev);
+#ifdef ZXDH_DCBNL_OPEN
+		err = zxdh_dcbnl_initialize(netdev);
+		if (err != 0) {
+			LOG_ERR("zxdh_dcbnl_initialize failed: %d\n", err);
+		}
+#endif
+	}
+
+	en_dev->ops->set_bond_num(en_dev->parent, true);
+	LOG_INFO("%s aux probe completed\n", netdev->name);
+
+	return 0;
+
+err_phyport_init:
+	dh_inet6_addr_change_notifier_unregister(&(en_dev->ipv6_notifier));
+err_ipv6_notifier_init:
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		aux_get_bond_attrs(en_dev, &lag_attrs);
+		zxdh_ldev_remove_netdev(en_dev->parent, netdev, &lag_attrs);
+	}
+	unregister_netdev(netdev);
+err_do_q_stats_free:
+	kfree(en_dev->hw_stats.q_stats);
+err_do_rxfh_free:
+	if (!en_dev->ops->is_bond(en_dev->parent)) {
+		zxdh_rxfh_del(en_dev);
+	}
+err_do_vport_free:
+	zxdh_vport_uninit(netdev);
+err_do_vqs_free:
+	zxdh_vqs_uninit(netdev);
+err_vqs_init:
+	zxdh_add_status(netdev, ZXDH_CONFIG_S_FAILED);
+err_status_init:
+	dh_aux_eq_table_destroy(en_priv);
+err_eq_table_create:
+	dh_aux_events_uninit(en_priv);
+err_events_init:
+	dh_aux_eq_table_cleanup(en_priv);
+err_eq_table_init:
+	en_dev->ops->destroy_vqs_channels(en_dev->parent);
+	en_dev->ops->release_port(en_dev->parent, en_dev->pannel_id);
+err_create_vqs_channels:
+	free_netdev(netdev);
+err_create_netdev:
+	return err;
+}
+
+static int32_t zxdh_en_dev_remove(struct auxiliary_device *adev)
+{
+	struct zxdh_en_priv *en_priv =
+			(struct zxdh_en_priv *)dev_get_drvdata(&adev->dev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct net_device *netdev = en_dev->netdev;
+	struct zxdh_lag_attrs lag_attrs;
+	int32_t ret = 0;
+
+	LOG_INFO("zxdh_en_dev_remove start\n");
+
+	en_dev->ops->set_bond_num(en_dev->parent, false);
+#ifdef ZXDH_MSGQ
+	if (en_dev->need_msgq)
+		zxdh_msgq_exit(en_dev);
+#endif
+
+#ifdef ZXDH_PLCR_OPEN
+	zxdh_plcr_uninit(en_priv);
+#endif
+
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		aux_get_bond_attrs(en_dev, &lag_attrs);
+		zxdh_ldev_remove_netdev(en_dev->parent, netdev, &lag_attrs);
+	}
+
+#ifdef ZXDH_DCBNL_OPEN
+	zxdh_dcbnl_ets_uninit(netdev);
+#endif
+
+	unregister_netdev(netdev);
+	kfree(en_dev->hw_stats.q_stats);
+
+	if (!en_dev->ops->is_bond(en_dev->parent)) {
+		zxdh_rxfh_del(en_dev);
+	}
+
+	zxdh_vport_uninit(netdev);
+
+	zxdh_vqs_uninit(netdev);
+
+	zxdh_add_status(netdev, ZXDH_CONFIG_S_FAILED);
+
+	dh_aux_eq_table_destroy(en_priv);
+	dh_aux_events_uninit(en_priv);
+	dh_aux_eq_table_cleanup(en_priv);
+	en_dev->ops->destroy_vqs_channels(en_dev->parent);
+	en_dev->ops->release_port(en_dev->parent, en_dev->pannel_id);
+	ret = dh_inet6_addr_change_notifier_unregister(&(en_dev->ipv6_notifier));
+	LOG_INFO("dh_inet6_addr_change_notifier_unregister, ret:%d\n", ret);
+	free_netdev(netdev);
+	LOG_INFO("zxdh_en_dev_remove stop\n");
+
+	return 0;
+}
+
+static void zxdh_en_dev_shutdown(struct auxiliary_device *adev)
+{
+	LOG_INFO("zxdh_en_dev_shutdown start\n");
+	zxdh_en_dev_remove(adev);
+	LOG_INFO("zxdh_en_dev_shutdown stop\n");
+};
+
+static const struct auxiliary_device_id zxdh_en_dev_id_table[] = {
+	{
+			.name = ZXDH_PF_NAME "." ZXDH_EN_DEV_ID_NAME,
+	},
+	{},
+};
+
+MODULE_DEVICE_TABLE(auxiliary, zxdh_en_dev_id_table);
+
+static struct auxiliary_driver zxdh_en_driver = {
+	.name = ZXDH_EN_DEV_ID_NAME,
+	.probe = zxdh_en_dev_probe,
+	.remove = zxdh_en_dev_remove,
+	.shutdown = zxdh_en_dev_shutdown,
+	.id_table = zxdh_en_dev_id_table,
+};
+
+int32_t zxdh_en_driver_register(void)
+{
+	int32_t err = 0;
+
+	if ((max_pairs == 0) || (max_pairs >= ZXDH_MAX_PAIRS_NUM)) {
+		LOG_INFO(
+				"max_pairs %u parameter is a invalid value, use the default value %u\n",
+				max_pairs, ZXDH_MQ_PAIRS_NUM);
+		max_pairs = ZXDH_MQ_PAIRS_NUM;
+	}
+
+	err = auxiliary_driver_register(&zxdh_en_driver);
+	if (err != 0) {
+		LOG_ERR("auxiliary_driver_register failed: %d\n", err);
+		goto err_aux_register;
+	}
+
+	err = dh_aux_msg_recv_func_register();
+	if (err != 0) {
+		LOG_ERR("dh_aux_msg_recv_func_register failed: %d\n", err);
+		goto err_msg_recv_register;
+	}
+
+	err = zxdh_tools_netlink_register();
+	if (err != 0) {
+		LOG_ERR("zxdh_tools_msg_family register error failed: %d\n", err);
+		goto err_netlink_register;
+	}
+
+	return 0;
+
+err_netlink_register:
+	dh_aux_msg_recv_func_unregister();
+err_msg_recv_register:
+	auxiliary_driver_unregister(&zxdh_en_driver);
+err_aux_register:
+	return err;
+}
+
+void zxdh_en_driver_unregister(void)
+{
+	zxdh_tools_netlink_unregister();
+	dh_aux_msg_recv_func_unregister();
+	auxiliary_driver_unregister(&zxdh_en_driver);
+}
+
+module_init(zxdh_en_driver_register);
+module_exit(zxdh_en_driver_unregister);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux.h b/src/net/drivers/net/ethernet/dinghai/en_aux.h
old mode 100755
new mode 100644
index 6c7755a718af9dbe735d05c252e276823b2c0e8c..969c95923e630aa5140ca9593819c3737afb842c
--- a/src/net/drivers/net/ethernet/dinghai/en_aux.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux.h
@@ -1,373 +1,374 @@
-#ifndef __ZXDH_EN_AUX_H__
-#define __ZXDH_EN_AUX_H__
-
-#include "msg_common.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/dh_cmd.h>
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/en_aux.h>
-#include <linux/dinghai/eq.h>
-#include <linux/compiler_types.h>
-#include <linux/types.h>
-#include "./en_aux/queue.h"
-#include "./en_aux/en_cmd.h"
-#include "./en_pf.h"
-#include "./en_aux/dcbnl/en_dcbnl.h"
-
-#define MAX_VLAN_ID    4095
-
-#define PF_AC_MASK     0x800
-#define FILTER_MAC     0xAA
-#define UNFILTER_MAC   0xFF
-
-#define AUX_INIT_INCOMPLETED  0
-#define AUX_INIT_COMPLETED    1
-
-#define IS_DELAY_STATISTICS_PKT      0
-#define IS_NOT_DELAY_STATICTICS_PKT  1
-
-#define ADD_IP6MAC 1
-#define DEL_IP6MAC 2
-
-#define ZXDH_SET_FEATURE(features, feature, enable) \
-    do {                                            \
-        if (enable)                                 \
-        {                                           \
-            *features |= feature;                   \
-        }                                           \
-        else                                        \
-        {                                           \
-            *features &= ~feature;                  \
-        }                                           \
-    } while (0)
-
-#define ZXDH_AUX_INIT_COMP_CHECK(en_dev) \
-    do {                                                   \
-        if (en_dev->init_comp_flag != AUX_INIT_COMPLETED)  \
-        {                                                  \
-            return;                          \
-        }                                                  \
-    } while (0)
-
-typedef int (*zxdh_feature_handler)(struct net_device *netdev, bool enable);
-
-extern uint32_t max_pairs;
-
-struct zxdh_rdma_if;
-struct zxdh_en_if;
-
-struct zxdh_en_container {
-    struct zxdh_auxiliary_device adev;
-    struct zxdh_rdma_dev_info *rdma_infos;
-    struct zxdh_rdma_if *rdma_ops;
-    struct zxdh_en_if *ops;
-    struct dh_core_dev *parent;
-    int32_t aux_id;
-};
-
-struct zxdh_en_queue_stats
-{
-    uint64_t q_rx_pkts;
-    uint64_t q_tx_pkts;
-    uint64_t q_rx_bytes;
-    uint64_t q_tx_bytes;
-    uint64_t q_tx_stopped;
-    uint64_t q_tx_wake;
-    uint64_t q_tx_dropped;
-};
-
-struct zxdh_en_netdev_stats
-{
-    uint64_t rx_packets;
-    uint64_t tx_packets;
-    uint64_t rx_bytes;
-    uint64_t tx_bytes;
-    uint64_t tx_queue_wake;
-    uint64_t tx_queue_stopped;
-    uint64_t tx_queue_dropped;
-};
-
-struct zxdh_en_vport_vqm_stats
-{
-    uint64_t rx_vport_packets;
-    uint64_t tx_vport_packets;
-    uint64_t rx_vport_bytes;
-    uint64_t tx_vport_bytes;
-    uint64_t rx_vport_dropped;
-};
-
-struct zxdh_en_vport_np_stats
-{
-    uint64_t rx_vport_broadcast_packets;
-    uint64_t tx_vport_broadcast_packets;
-    uint64_t rx_vport_mtu_drop_packets;
-    uint64_t tx_vport_mtu_drop_packets;
-    uint64_t rx_vport_mtu_drop_bytes;
-    uint64_t tx_vport_mtu_drop_bytes;
-    uint64_t rx_vport_plcr_drop_packets;
-    uint64_t tx_vport_plcr_drop_packets;
-    uint64_t rx_vport_plcr_drop_bytes;
-    uint64_t tx_vport_plcr_drop_bytes;
-};
-
-
-struct zxdh_en_vport_stats
-{
-    struct zxdh_en_vport_vqm_stats vqm_stats;
-    struct zxdh_en_vport_np_stats np_stats;
-};
-
-struct zxdh_en_phy_stats
-{
-    uint64_t rx_packets_phy;
-    uint64_t tx_packets_phy;
-    uint64_t rx_bytes_phy;
-    uint64_t tx_bytes_phy;
-    uint64_t rx_errors;
-    uint64_t tx_errors;
-    uint64_t rx_discards;
-    uint64_t tx_drop;
-    uint64_t rx_multicast_phy;
-    uint64_t tx_multicast_phy;
-    uint64_t rx_broadcast_phy;
-    uint64_t tx_broadcast_phy;
-    uint64_t rx_size_64_phy;
-    uint64_t rx_size_65_127;
-    uint64_t rx_size_128_255;
-    uint64_t rx_size_256_511;
-    uint64_t rx_size_512_1023;
-    uint64_t rx_size_1024_1518;
-    uint64_t rx_size_1519_mru;
-    uint64_t rx_pause;
-    uint64_t tx_pause;
-}__attribute__((packed));
-
-struct zxdh_en_hw_stats
-{
-    struct zxdh_en_netdev_stats netdev_stats;
-    struct zxdh_en_vport_stats vport_stats;
-    struct zxdh_en_phy_stats phy_stats;
-    struct zxdh_en_queue_stats *q_stats;
-};
-
-struct zxdh_vlan_dev
-{
-    uint8_t qos;
-    uint8_t rsv;
-    uint16_t protcol;
-    uint16_t vlan_id;
-};
-
-/* drs sec */
-typedef struct
-{
-   uint64_t  SecVAddr;  /*每个设备的sec私有内存的虚拟基地址*/
-   uint64_t  SecPAddr;  /*每个设备的sec私有内存的物理基地址*/
-   uint32_t  SecMemSize; /*每个设备的sec私有内存的大小*/
-}zxdh_sec_pri;
-
-
-struct zxdh_en_device {
-    struct dh_core_dev *parent;
-    struct net_device *netdev;
-    void *msgq_dev;
-    struct zxdh_en_if *ops;
-    struct zxdh_en_hw_stats hw_stats;
-    struct zxdh_en_vport_stats pre_stats;
-    struct zxdh_vlan_dev vlan_dev;
-
-    uint32_t device_id;
-    uint32_t vendor_id;
-
-    uint64_t driver_feature;
-    uint64_t device_feature;
-    uint64_t guest_feature;
-
-    struct list_head vqs_list;
-    spinlock_t vqs_list_lock;
-    uint32_t indir_rqt[ZXDH_INDIR_RQT_SIZE];
-
-    int32_t channels_num;
-
-    /* a list of queues so we can dispatch IRQs */
-    spinlock_t lock;
-    struct list_head virtqueues;
-    /* array of all queues for house-keeping */
-    struct zxdh_pci_vq_info **vqs;
-
-    struct send_queue *sq;
-    struct receive_queue *rq;
-    uint32_t status;
-
-    /* Max # of queue pairs supported by the device */
-    uint16_t curr_queue_pairs;
-    uint16_t max_queue_pairs;
-
-    bool need_msgq;
-    /* Host can handle any s/g split between our header and packet data */
-    bool any_header_sg;
-    /* Packet custom queue header size */
-    uint8_t hdr_len;
-    /* Work struct for refilling if we run low on memory. */
-    struct delayed_work refill;
-
-    /* CPU hotplug instances for online & dead */
-    struct hlist_node node;
-    struct hlist_node node_dead;
-
-    bool np_direction;
-    bool drs_offload;
-    bool dtp_offload;
-
-    uint32_t phy_index[ZXDH_MAX_QUEUES_NUM];
-
-    uint8_t link_check_bit;
-    uint8_t pannel_id;
-    uint8_t rsv[2];
-
-    uint16_t ep_bdf;
-    uint16_t pcie_id;
-    /* vfunc_active */
-    uint16_t slot_id;
-    uint16_t vport;
-    uint8_t phy_port;
-    uint8_t panel_id;
-    uint8_t hash_search_idx;
-    uint8_t hash_func;
-
-    uint32_t link_speed;
-    bool link_up;
-    uint8_t duplex;
-
-    uint32_t speed;
-    uint32_t autoneg_enable;
-    uint32_t supported_speed_modes;
-    uint32_t advertising_speed_modes;
-
-    bool promisc_enabled;
-    bool allmulti_enabled;
-    uint32_t pflags;
-    uint8_t clock_no;
-    uint32_t msglevel;
-    uint32_t wol_support;
-    uint32_t wolopts;
-    uint8_t fw_version[ETHTOOL_FWVERS_LEN];
-    uint8_t fw_version_len;
-    uint32_t vf_1588_call_np_num;
-    uint32_t ptp_tc_enable_opt;
-    uint32_t delay_statistics_enable;
-
-    struct work_struct vf_link_info_update_work;
-    struct work_struct link_info_irq_update_vf_work;
-    struct work_struct link_info_irq_process_work;
-    struct work_struct link_info_irq_update_np_work;
-    struct work_struct rx_mode_set_work;
-
-    uint8_t curr_unicast_num;
-    uint8_t curr_multicast_num;
-    struct work_struct pf_notify_vf_link_state_work;
-    struct work_struct pf2vf_msg_proc_work;
-    struct work_struct pf_notify_vf_reset_work;
-    struct work_struct service_task;
-    struct work_struct service_riscv_task;
-    struct timer_list service_timer;
-    struct timer_list service_riscv_timer;
-    struct work_struct riscv2aux_msg_proc_work;
-    /* QoS DCB */
-    struct zxdh_dcbnl_para dcb_para;
-    /* SEC */
-    zxdh_sec_pri drs_sec_pri;
-
-    /* initialization completion flag */
-    uint8_t init_comp_flag;
-
-    struct notifier_block ipv6_notifier;
-};
-
-struct zxdh_en_priv {
-    struct zxdh_en_device edev;
-    struct mutex lock;
-    struct dh_eq_table eq_table;
-    struct dh_events *events;
-};
-
-#define DEV_UNICAST_MAX_NUM     32    /* 每个PF/VF存储的单播mac转发表上限 */
-#define DEV_MULTICAST_MAX_NUM   32    /* 每个PF/VF存储的组播mac转发表上限 */
-#define UNICAST_MAX_NUM         (DEV_UNICAST_MAX_NUM * 257)
-#define MULTICAST_MAX_NUM       (DEV_MULTICAST_MAX_NUM * 257)
-
-int32_t dh_aux_eq_table_init(struct zxdh_en_priv *en_priv);
-void dh_aux_eq_table_cleanup(struct zxdh_en_priv *en_priv);
-int32_t zxdh_ip6mac_add(struct zxdh_en_device *en_dev, const uint32_t *addr6, const uint8_t *ip6mac);
-int32_t zxdh_ip6mac_del(struct zxdh_en_device *en_dev, const uint32_t *addr6, const uint8_t *ip6mac);
-struct zxdh_rdma_if {
-    void *(*get_rdma_netdev)(struct dh_core_dev *dh_dev);
-};
-
-struct zxdh_en_if {
-    uint16_t (*get_channels_num)(struct dh_core_dev *dh_dev);
-    int32_t (*create_vqs_channels)(struct dh_core_dev *dh_dev);
-    void (*destroy_vqs_channels)(struct dh_core_dev *dh_dev);
-    void (*switch_vqs_channel)(struct dh_core_dev *dh_dev, int32_t channel, int32_t op);
-    int32_t (*vqs_channel_bind_handler)(struct dh_core_dev *dh_dev, int32_t vqs_channel_num, struct dh_vq_handler *handler);
-    void (*vqs_channel_unbind_handler)(struct dh_core_dev *dh_dev, int32_t vqs_channel_num);
-    int32_t (*vq_bind_channel)(struct dh_core_dev *dh_dev, int32_t channel_num, int32_t queue_index);
-    void (*vq_unbind_channel)(struct dh_core_dev *dh_dev, int32_t queue_index);
-    int32_t (*vqs_bind_eqs)(struct dh_core_dev *dh_dev, int32_t vqs_channel_num, struct list_head *vq_node);
-    void (*vqs_unbind_eqs)(struct dh_core_dev *dh_dev, int32_t vqs_channel_num);
-    void __iomem * (*vp_modern_map_vq_notify)(struct dh_core_dev *dh_dev, uint32_t index, resource_size_t *pa);
-    void (*vp_modern_unmap_vq_notify)(struct dh_core_dev *dh_dev, void *priv);
-    int32_t (*get_phy_vq)(struct dh_core_dev *dh_dev, uint16_t index);
-    void (*activate_phy_vq)(struct dh_core_dev *dh_dev, uint32_t phy_index, int32_t queue_size, uint64_t desc_addr, uint64_t driver_addr, uint64_t device_addr);
-    void (*de_activate_phy_vq)(struct dh_core_dev *dh_dev, uint32_t phy_index);
-    int32_t (*release_phy_vq)(struct dh_core_dev *dh_dev, uint32_t *phy_index, uint16_t total_qnum);
-    void (*set_status)(struct dh_core_dev *dh_dev, uint8_t status);
-    uint8_t (*get_status)(struct dh_core_dev *dh_dev);
-    void (*set_vf_mac)(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id);
-    void (*get_vf_mac)(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id);
-    void (*set_mac)(struct dh_core_dev *dh_dev, uint8_t *mac);
-    void (*get_mac)(struct dh_core_dev *dh_dev, uint8_t *mac);
-    uint64_t (*get_features)(struct dh_core_dev *dh_dev);
-    void (*set_features)(struct dh_core_dev *dh_dev, uint64_t features);
-    uint16_t (*get_queue_num)(struct dh_core_dev *dh_dev);
-    uint16_t (*get_queue_size)(struct dh_core_dev *dh_dev, uint32_t index);
-    void (*set_queue_enable)(struct dh_core_dev *dh_dev, uint16_t index, bool enable);
-    uint32_t (*get_epbdf)(struct dh_core_dev *dh_dev);
-    uint16_t (*get_vport)(struct dh_core_dev *dh_dev);
-    uint16_t (*get_pcie_id)(struct dh_core_dev *dh_dev);
-    uint16_t (*get_slot_id)(struct dh_core_dev *dh_dev);
-    bool (*is_bond)(struct dh_core_dev *dh_dev);
-    bool (*is_upf)(struct dh_core_dev *dh_dev);
-    enum dh_coredev_type (*get_coredev_type)(struct dh_core_dev *dh_dev);
-    struct pci_dev * (*get_pdev)(struct dh_core_dev *dh_dev);
-    uint64_t (*get_bar_virt_addr)(struct dh_core_dev *dh_dev, uint8_t bar_num);
-    int32_t (*msg_send_cmd)(struct dh_core_dev *dh_dev, uint16_t module_id, void *msg, void *ack, bool is_sync);
-    int32_t (*async_eq_enable)(struct dh_core_dev *dh_dev, struct dh_eq_async *eq, const char *name, bool attach);
-    struct zxdh_vf_item *(*get_vf_item)(struct dh_core_dev *dh_dev, uint16_t vf_idx);
-    void (*set_pf_link_up) (struct dh_core_dev *dh_dev, bool link_up);
-    bool (*get_pf_link_up) (struct dh_core_dev *dh_dev);
-    void (*update_pf_link_info)(struct dh_core_dev *dh_dev, struct link_info_struct *link_info_val);
-    int32_t (*get_pf_drv_msg)(struct dh_core_dev *dh_dev, uint8_t *drv_version, uint8_t *drv_version_len);
-    void (*set_vepa) (struct dh_core_dev *dh_dev, bool setting);
-    bool (*get_vepa) (struct dh_core_dev *dh_dev);
-    void (*set_bond_num)(struct dh_core_dev *dh_dev, bool add);
-    bool (*if_init)(struct dh_core_dev *dh_dev);
-    int32_t (*request_port)(struct dh_core_dev *dh_dev, void *data);
-    int32_t (*release_port)(struct dh_core_dev *dh_dev, uint32_t port_id);
-    void (*get_link_info_from_vqm)(struct dh_core_dev *dh_dev, uint8_t *link_up);
-    void (*set_vf_link_info)(struct dh_core_dev *dh_dev, uint16_t vf_idx, uint8_t link_up);
-    void (*set_pf_phy_port)(struct dh_core_dev *dh_dev, uint8_t phy_port);
-    void (*set_rdma_netdev)(struct dh_core_dev *dh_dev, void *data);
-    uint8_t (*get_pf_phy_port)(struct dh_core_dev *dh_dev);
-    void (*set_init_comp_flag)(struct dh_core_dev *dh_dev);
-    struct zxdh_ipv6_mac_tbl * (*get_ip6mac_tbl)(struct dh_core_dev *dh_dev);
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef __ZXDH_EN_AUX_H__
+#define __ZXDH_EN_AUX_H__
+
+#include "msg_common.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/dh_cmd.h>
+#include <linux/dinghai/driver.h>
+#include <linux/dinghai/en_aux.h>
+#include <linux/dinghai/eq.h>
+#include <linux/compiler_types.h>
+#include <linux/types.h>
+#include "./en_aux/queue.h"
+#include "./en_aux/en_cmd.h"
+#include "./en_pf.h"
+#include "./en_aux/dcbnl/en_dcbnl.h"
+
+#define MAX_VLAN_ID 4095
+
+#define PF_AC_MASK 0x800
+#define FILTER_MAC 0xAA
+#define UNFILTER_MAC 0xFF
+
+#define AUX_INIT_INCOMPLETED 0
+#define AUX_INIT_COMPLETED 1
+
+#define IS_DELAY_STATISTICS_PKT 0
+#define IS_NOT_DELAY_STATICTICS_PKT 1
+
+#define ZXDH_SET_FEATURE(features, feature, enable) \
+	do {                                            \
+		if (enable) {                               \
+			*features |= feature;                   \
+		} else {                                    \
+			*features &= ~feature;                  \
+		}                                           \
+	} while (0)
+
+#define ZXDH_AUX_INIT_COMP_CHECK(en_dev)                    \
+	do {                                                    \
+		if (en_dev->init_comp_flag != AUX_INIT_COMPLETED) { \
+			return;                                         \
+		}                                                   \
+	} while (0)
+
+typedef int (*zxdh_feature_handler)(struct net_device *netdev, bool enable);
+
+extern uint32_t max_pairs;
+
+struct zxdh_rdma_if;
+struct zxdh_en_if;
+
+struct zxdh_en_container {
+	struct auxiliary_device adev;
+	struct zxdh_rdma_dev_info *rdma_infos;
+	struct zxdh_rdma_if *rdma_ops;
+	struct zxdh_en_if *ops;
+	struct dh_core_dev *parent;
+	int32_t aux_id;
+};
+
+struct zxdh_en_queue_stats {
+	uint64_t q_rx_pkts;
+	uint64_t q_tx_pkts;
+	uint64_t q_rx_bytes;
+	uint64_t q_tx_bytes;
+	uint64_t q_tx_stopped;
+	uint64_t q_tx_wake;
+	uint64_t q_tx_dropped;
+};
+
+struct zxdh_en_netdev_stats {
+	uint64_t rx_packets;
+	uint64_t tx_packets;
+	uint64_t rx_bytes;
+	uint64_t tx_bytes;
+	uint64_t tx_queue_wake;
+	uint64_t tx_queue_stopped;
+	uint64_t tx_queue_dropped;
+};
+
+struct zxdh_en_vport_vqm_stats {
+	uint64_t rx_vport_packets;
+	uint64_t tx_vport_packets;
+	uint64_t rx_vport_bytes;
+	uint64_t tx_vport_bytes;
+	uint64_t rx_vport_dropped;
+};
+
+struct zxdh_en_vport_np_stats {
+	uint64_t rx_vport_broadcast_packets;
+	uint64_t tx_vport_broadcast_packets;
+	uint64_t rx_vport_mtu_drop_packets;
+	uint64_t tx_vport_mtu_drop_packets;
+	uint64_t rx_vport_mtu_drop_bytes;
+	uint64_t tx_vport_mtu_drop_bytes;
+	uint64_t rx_vport_plcr_drop_packets;
+	uint64_t tx_vport_plcr_drop_packets;
+	uint64_t rx_vport_plcr_drop_bytes;
+	uint64_t tx_vport_plcr_drop_bytes;
+};
+
+struct zxdh_en_vport_stats {
+	struct zxdh_en_vport_vqm_stats vqm_stats;
+	struct zxdh_en_vport_np_stats np_stats;
+};
+
+struct zxdh_en_phy_stats {
+	uint64_t rx_packets_phy;
+	uint64_t tx_packets_phy;
+	uint64_t rx_bytes_phy;
+	uint64_t tx_bytes_phy;
+	uint64_t rx_errors;
+	uint64_t tx_errors;
+	uint64_t rx_discards;
+	uint64_t tx_drop;
+	uint64_t rx_multicast_phy;
+	uint64_t tx_multicast_phy;
+	uint64_t rx_broadcast_phy;
+	uint64_t tx_broadcast_phy;
+	uint64_t rx_size_64_phy;
+	uint64_t rx_size_65_127;
+	uint64_t rx_size_128_255;
+	uint64_t rx_size_256_511;
+	uint64_t rx_size_512_1023;
+	uint64_t rx_size_1024_1518;
+	uint64_t rx_size_1519_mru;
+} __attribute__((packed));
+
+struct zxdh_en_hw_stats {
+	struct zxdh_en_netdev_stats netdev_stats;
+	struct zxdh_en_vport_stats vport_stats;
+	struct zxdh_en_phy_stats phy_stats;
+	struct zxdh_en_queue_stats *q_stats;
+};
+
+struct zxdh_vlan_dev {
+	uint8_t qos;
+	uint8_t rsv;
+	uint16_t protcol;
+	uint16_t vlan_id;
+};
+
+/* drs sec */
+typedef struct {
+	uint64_t SecVAddr; /*每个设备的sec私有内存的虚拟基地址*/
+	uint64_t SecPAddr; /*每个设备的sec私有内存的物理基地址*/
+	uint32_t SecMemSize; /*每个设备的sec私有内存的大小*/
+} zxdh_sec_pri;
+
+struct zxdh_en_device {
+	struct dh_core_dev *parent;
+	struct net_device *netdev;
+	void *msgq_dev;
+	struct zxdh_en_if *ops;
+	struct zxdh_en_hw_stats hw_stats;
+	struct zxdh_en_vport_stats pre_stats;
+	struct zxdh_vlan_dev vlan_dev;
+
+	uint32_t device_id;
+	uint32_t vendor_id;
+
+	uint64_t driver_feature;
+	uint64_t device_feature;
+	uint64_t guest_feature;
+
+	struct list_head vqs_list;
+	spinlock_t vqs_list_lock;
+	uint32_t indir_rqt[ZXDH_INDIR_RQT_SIZE];
+
+	int32_t channels_num;
+
+	/* a list of queues so we can dispatch IRQs */
+	spinlock_t lock;
+	struct list_head virtqueues;
+	/* array of all queues for house-keeping */
+	struct zxdh_pci_vq_info **vqs;
+
+	struct send_queue *sq;
+	struct receive_queue *rq;
+	uint32_t status;
+
+	/* Max # of queue pairs supported by the device */
+	uint16_t curr_queue_pairs;
+	uint16_t max_queue_pairs;
+
+	bool need_msgq;
+	/* Host can handle any s/g split between our header and packet data */
+	bool any_header_sg;
+	/* Packet custom queue header size */
+	uint8_t hdr_len;
+	/* Work struct for refilling if we run low on memory. */
+	struct delayed_work refill;
+
+	/* CPU hotplug instances for online & dead */
+	struct hlist_node node;
+	struct hlist_node node_dead;
+
+	bool np_direction;
+	bool drs_offload;
+	bool dtp_offload;
+
+	uint32_t phy_index[ZXDH_MAX_QUEUES_NUM];
+
+	uint8_t link_check_bit;
+	uint8_t pannel_id;
+	uint8_t rsv[2];
+
+	uint16_t ep_bdf;
+	uint16_t pcie_id;
+	/* vfunc_active */
+	uint16_t slot_id;
+	uint16_t vport;
+	uint8_t phy_port;
+	uint8_t panel_id;
+	uint8_t hash_search_idx;
+	uint8_t hash_func;
+
+	uint32_t link_speed;
+	bool link_up;
+	uint8_t duplex;
+
+	uint32_t speed;
+	uint32_t autoneg_enable;
+	uint32_t supported_speed_modes;
+	uint32_t advertising_speed_modes;
+
+	bool promisc_enabled;
+	bool allmulti_enabled;
+	uint32_t pflags;
+	uint8_t clock_no;
+	uint32_t msglevel;
+	uint32_t wol_support;
+	uint32_t wolopts;
+	uint8_t fw_version[ETHTOOL_FWVERS_LEN];
+	uint8_t fw_version_len;
+	uint32_t vf_1588_call_np_num;
+	uint32_t ptp_tc_enable_opt;
+	uint32_t delay_statistics_enable;
+
+	struct work_struct vf_link_info_update_work;
+	struct work_struct link_info_irq_update_vf_work;
+	struct work_struct link_info_irq_process_work;
+	struct work_struct link_info_irq_update_np_work;
+	struct work_struct rx_mode_set_work;
+
+	uint8_t curr_unicast_num;
+	uint8_t curr_multicast_num;
+	struct work_struct pf_notify_vf_link_state_work;
+	struct work_struct pf2vf_msg_proc_work;
+	struct work_struct pf_notify_vf_reset_work;
+	struct work_struct service_task;
+	struct work_struct service_riscv_task;
+	struct timer_list service_timer;
+	struct timer_list service_riscv_timer;
+	struct work_struct riscv2aux_msg_proc_work;
+	/* QoS DCB */
+	struct zxdh_dcbnl_para dcb_para;
+	/* SEC */
+	zxdh_sec_pri drs_sec_pri;
+
+	/* initialization completion flag */
+	uint8_t init_comp_flag;
+
+	struct notifier_block ipv6_notifier;
+};
+
+struct zxdh_en_priv {
+	struct zxdh_en_device edev;
+	struct mutex lock;
+	struct dh_eq_table eq_table;
+	struct dh_events *events;
+};
+
+#define DEV_UNICAST_MAX_NUM 32 /* 每个PF/VF存储的单播mac转发表上限 */
+#define DEV_MULTICAST_MAX_NUM 32 /* 每个PF/VF存储的组播mac转发表上限 */
+#define UNICAST_MAX_NUM (DEV_UNICAST_MAX_NUM * 257)
+#define MULTICAST_MAX_NUM (DEV_MULTICAST_MAX_NUM * 257)
+
+int32_t dh_aux_eq_table_init(struct zxdh_en_priv *en_priv);
+void dh_aux_eq_table_cleanup(struct zxdh_en_priv *en_priv);
+int32_t ipv6_multicast_mac_add(struct zxdh_en_device *en_dev,
+							   struct net_device *dev, const uint8_t *addr);
+int32_t ipv6_multicast_mac_del(struct zxdh_en_device *en_dev,
+							   struct net_device *dev, const uint8_t *addr);
+
+struct zxdh_rdma_if {
+	void *(*get_rdma_netdev)(struct dh_core_dev *dh_dev);
+};
+
+struct zxdh_en_if {
+	uint16_t (*get_channels_num)(struct dh_core_dev *dh_dev);
+	int32_t (*create_vqs_channels)(struct dh_core_dev *dh_dev);
+	void (*destroy_vqs_channels)(struct dh_core_dev *dh_dev);
+	void (*switch_vqs_channel)(struct dh_core_dev *dh_dev, int32_t channel,
+							   int32_t op);
+	int32_t (*vqs_channel_bind_handler)(struct dh_core_dev *dh_dev,
+										int32_t vqs_channel_num,
+										struct dh_vq_handler *handler);
+	void (*vqs_channel_unbind_handler)(struct dh_core_dev *dh_dev,
+									   int32_t vqs_channel_num);
+	int32_t (*vq_bind_channel)(struct dh_core_dev *dh_dev, int32_t channel_num,
+							   int32_t queue_index);
+	void (*vq_unbind_channel)(struct dh_core_dev *dh_dev, int32_t queue_index);
+	int32_t (*vqs_bind_eqs)(struct dh_core_dev *dh_dev, int32_t vqs_channel_num,
+							struct list_head *vq_node);
+	void (*vqs_unbind_eqs)(struct dh_core_dev *dh_dev, int32_t vqs_channel_num);
+	void __iomem *(*vp_modern_map_vq_notify)(struct dh_core_dev *dh_dev,
+											 uint32_t index,
+											 resource_size_t *pa);
+	void (*vp_modern_unmap_vq_notify)(struct dh_core_dev *dh_dev, void *priv);
+	int32_t (*get_phy_vq)(struct dh_core_dev *dh_dev, uint16_t index);
+	void (*activate_phy_vq)(struct dh_core_dev *dh_dev, uint32_t phy_index,
+							int32_t queue_size, uint64_t desc_addr,
+							uint64_t driver_addr, uint64_t device_addr);
+	void (*de_activate_phy_vq)(struct dh_core_dev *dh_dev, uint32_t phy_index);
+	int32_t (*release_phy_vq)(struct dh_core_dev *dh_dev, uint32_t *phy_index,
+							  uint16_t total_qnum);
+	void (*set_status)(struct dh_core_dev *dh_dev, uint8_t status);
+	uint8_t (*get_status)(struct dh_core_dev *dh_dev);
+	void (*set_vf_mac)(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id);
+	void (*get_vf_mac)(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id);
+	void (*set_mac)(struct dh_core_dev *dh_dev, uint8_t *mac);
+	void (*get_mac)(struct dh_core_dev *dh_dev, uint8_t *mac);
+	uint64_t (*get_features)(struct dh_core_dev *dh_dev);
+	void (*set_features)(struct dh_core_dev *dh_dev, uint64_t features);
+	uint16_t (*get_queue_num)(struct dh_core_dev *dh_dev);
+	uint16_t (*get_queue_size)(struct dh_core_dev *dh_dev, uint32_t index);
+	void (*set_queue_enable)(struct dh_core_dev *dh_dev, uint16_t index,
+							 bool enable);
+	uint32_t (*get_epbdf)(struct dh_core_dev *dh_dev);
+	uint16_t (*get_vport)(struct dh_core_dev *dh_dev);
+	uint16_t (*get_pcie_id)(struct dh_core_dev *dh_dev);
+	uint16_t (*get_slot_id)(struct dh_core_dev *dh_dev);
+	bool (*is_bond)(struct dh_core_dev *dh_dev);
+	enum dh_coredev_type (*get_coredev_type)(struct dh_core_dev *dh_dev);
+	struct pci_dev *(*get_pdev)(struct dh_core_dev *dh_dev);
+	uint64_t (*get_bar_virt_addr)(struct dh_core_dev *dh_dev, uint8_t bar_num);
+	int32_t (*msg_send_cmd)(struct dh_core_dev *dh_dev, uint16_t module_id,
+							void *msg, void *ack, bool is_sync);
+	int32_t (*async_eq_enable)(struct dh_core_dev *dh_dev,
+							   struct dh_eq_async *eq, const char *name,
+							   bool attach);
+	struct zxdh_vf_item *(*get_vf_item)(struct dh_core_dev *dh_dev,
+										uint16_t vf_idx);
+	void (*set_pf_link_up)(struct dh_core_dev *dh_dev, bool link_up);
+	bool (*get_pf_link_up)(struct dh_core_dev *dh_dev);
+	void (*update_pf_link_info)(struct dh_core_dev *dh_dev,
+								struct link_info_struct *link_info_val);
+	int32_t (*get_pf_drv_msg)(struct dh_core_dev *dh_dev, uint8_t *drv_version,
+							  uint8_t *drv_version_len);
+	void (*set_vepa)(struct dh_core_dev *dh_dev, bool setting);
+	bool (*get_vepa)(struct dh_core_dev *dh_dev);
+	void (*set_bond_num)(struct dh_core_dev *dh_dev, bool add);
+	bool (*if_init)(struct dh_core_dev *dh_dev);
+	int32_t (*request_port)(struct dh_core_dev *dh_dev, void *data);
+	int32_t (*release_port)(struct dh_core_dev *dh_dev, uint32_t port_id);
+	void (*get_link_info_from_vqm)(struct dh_core_dev *dh_dev,
+								   uint8_t *link_up);
+	void (*set_vf_link_info)(struct dh_core_dev *dh_dev, uint16_t vf_idx,
+							 uint8_t link_up);
+	void (*set_pf_phy_port)(struct dh_core_dev *dh_dev, uint8_t phy_port);
+	void (*set_rdma_netdev)(struct dh_core_dev *dh_dev, void *data);
+	uint8_t (*get_pf_phy_port)(struct dh_core_dev *dh_dev);
+	void (*set_init_comp_flag)(struct dh_core_dev *dh_dev);
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl.c b/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl.c
index 34bfadd3b95f1ef9f0db394192bc658a4dd200f3..5ca72daaff49c087d31793e8d8caaa91a0c6e2f5 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl.c
@@ -1,877 +1,805 @@
-//#include <linux/device.h>
-#include "../../en_aux.h"
-#include "en_dcbnl.h"
-#include "en_np/qos/include/dpp_drv_qos.h"
-#include "en_aux/en_cmd.h"
-#include "en_dcbnl_api.h"
-
-static int zxdh_dcbnl_ieee_getets(struct net_device *netdev, struct ieee_ets *ets)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t tc = 0;
-    uint32_t j = 0;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF)
-    {
-        LOG_ERR("zxdh_dcbnl_ieee_getets: coredev type is not a PF");
-        return -EOPNOTSUPP;
-    }
-
-    ets->willing = 0;
-
-    ets->ets_cap = ZXDH_DCBNL_MAX_TRAFFIC_CLASS;
-
-    memcpy(ets->tc_tsa, en_dev->dcb_para.ets_cfg.tc_tsa, sizeof(ets->tc_tsa));
-    memcpy(ets->tc_tx_bw, en_dev->dcb_para.ets_cfg.tc_tx_bw, sizeof(ets->tc_tx_bw));
-    memcpy(ets->prio_tc, en_dev->dcb_para.ets_cfg.prio_tc, sizeof(ets->prio_tc));
-
-    for (tc = 0; tc < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; tc++)
-    {
-        if (ets->tc_tsa[tc] != IEEE_8021QAZ_TSA_ETS)
-        {
-            ets->tc_tx_bw[tc] = 0;
-        }
-    }
-
-    /* debug */
-    for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++)
-    {
-        LOG_INFO(" idx:%d, ets->tc_tsa:%d, ets->tc_tx_bw:%d, ets->prio_tc:%d \n", j,
-              ets->tc_tsa[j], ets->tc_tx_bw[j], ets->prio_tc[j]);
-    }
-
-    return 0;
-}
-
-static int zxdh_dcbnl_check_ets_maxtc(struct ieee_ets *ets)
-{
-    uint32_t i;
-
-    for (i = 0; i < ZXDH_DCBNL_MAX_PRIORITY; i++)
-    {
-        if (ets->prio_tc[i] >= ZXDH_DCBNL_MAX_TRAFFIC_CLASS)
-        {
-            LOG_ERR("dcbnl_check_ets: Failed! TC value greater than max(%d)\n", ZXDH_DCBNL_MAX_TRAFFIC_CLASS);
-            return 1;
-        }
-    }
-    return 0;
-}
-
-static int zxdh_dcbnl_check_ets_tcbw(struct ieee_ets *ets)
-{
-    bool have_ets_tc = false;
-    uint32_t bw_sum = 0;
-    uint32_t i;
-
-    for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++)
-    {
-        if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS)
-        {
-            have_ets_tc = true;
-            bw_sum += ets->tc_tx_bw[i];
-        }
-    }
-
-    if (have_ets_tc && ((bw_sum != 100) && (bw_sum != 0)))
-    {
-        LOG_ERR("dcbnl_check_ets_tcbw: Failed! ETS BW sum is illegal\n");
-        return 1;
-    }
-
-    return 0;
-}
-
-static int zxdh_dcbnl_check_ets_para(struct ieee_ets *ets)
-{
-    uint32_t err = 0;
-
-    err = zxdh_dcbnl_check_ets_maxtc(ets);
-    if (err)
-    {
-        return -EINVAL;
-    }
-
-    err = zxdh_dcbnl_check_ets_tcbw(ets);
-    if (err)
-    {
-        return -EINVAL;
-    }
-    LOG_INFO(" end \n");
-    return 0;
-}
-
-
-static int zxdh_dcbnl_ieee_divide_tc_type(struct ieee_ets *ets, uint8_t *tc_type)
-{
-    uint32_t i;
-
-    for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++)
-    {
-        switch (ets->tc_tsa[i])
-        {
-        case IEEE_8021QAZ_TSA_ETS:
-            tc_type[i] = ets->tc_tx_bw[i] ? ZXDH_DCBNL_ETS_TC : ZXDH_DCBNL_ZEROBW_ETS_TC;
-            break;
-        case IEEE_8021QAZ_TSA_STRICT:
-            tc_type[i] = ZXDH_DCBNL_STRICT_TC;
-            break;
-        case IEEE_8021QAZ_TSA_VENDOR:
-            tc_type[i] = ZXDH_DCBNL_VENDOR_TC;
-            break;
-         default:
-            tc_type[i] = ZXDH_DCBNL_STRICT_TC;
-            LOG_ERR("dcbnl: %d tsa error, change to strict \n", ets->tc_tsa[i]);
-            break;
-        }
-    }
-
-    return 0;
-}
-
-static int zxdh_dcbnl_ieee_convert_tc_bw(struct ieee_ets *ets, uint8_t *tc_type, uint8_t *tc_tx_bw)
-{
-    uint32_t i;
-    uint8_t zero_ets_bw = 0;
-    uint8_t zero_ets_num = 0;
-
-    for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++)
-    {
-        if (tc_type[i] == ZXDH_DCBNL_ZEROBW_ETS_TC)
-        {
-            zero_ets_num++;
-        }
-    }
-
-    if (zero_ets_num)
-    {
-        zero_ets_bw = (uint8_t)ZXDH_DCBNL_MAX_BW_ALLOC / zero_ets_num;
-    }
-
-    for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++)
-    {
-        switch (tc_type[i])
-        {
-            case ZXDH_DCBNL_ZEROBW_ETS_TC:
-                tc_tx_bw[i] = zero_ets_bw;
-                break;
-            case ZXDH_DCBNL_ETS_TC:
-                tc_tx_bw[i] = ets->tc_tx_bw[i];
-                break;
-            case ZXDH_DCBNL_STRICT_TC:
-            case ZXDH_DCBNL_VENDOR_TC:
-                tc_tx_bw[i] = ZXDH_DCBNL_MAX_BW_ALLOC;
-                break;
-            default:
-                break;
-        }
-    }
-    /* debug */
-    LOG_INFO(" zero_ets_num:%d, zero_ets_bw:%d \n", zero_ets_num, zero_ets_bw);
-
-    return 0;
-}
-
-static uint32_t zxdh_dcbnl_ieee_set_ets_para(struct zxdh_en_priv *en_priv, struct ieee_ets *ets)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint8_t tc_type[ZXDH_DCBNL_MAX_TRAFFIC_CLASS];
-    uint8_t tc_tx_bw[ZXDH_DCBNL_MAX_TRAFFIC_CLASS];
-    uint32_t err = 0;
-    uint32_t j = 0;
-
-    zxdh_dcbnl_ieee_divide_tc_type(ets, tc_type);
-
-    zxdh_dcbnl_ieee_convert_tc_bw(ets, tc_type, tc_tx_bw);
-
-    err = zxdh_dcbnl_set_tc_scheduling(en_priv, tc_type, tc_tx_bw);
-    if (err)
-    {
-        LOG_ERR("set_tc_scheduling failed \n");
-        return err;
-    }
-
-    err = zxdh_dcbnl_set_ets_up_tc_map(en_priv, ets->prio_tc);
-    if (err)
-    {
-        LOG_ERR("set_prio_tc_map failed \n");
-        return err;
-    }
-
-    memcpy(en_dev->dcb_para.ets_cfg.tc_tsa, ets->tc_tsa, sizeof(ets->tc_tsa));
-    memcpy(en_dev->dcb_para.ets_cfg.tc_tx_bw, ets->tc_tx_bw, sizeof(ets->tc_tx_bw));
-    memcpy(en_dev->dcb_para.ets_cfg.prio_tc, ets->prio_tc, sizeof(ets->prio_tc));
-    /* debug */
-    for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++)
-    {
-        LOG_INFO(" idx:%d, tc_tsa:%d, tc_tx_bw:%d, prio_tc:%d \n", j,
-              en_dev->dcb_para.ets_cfg.tc_tsa[j], en_dev->dcb_para.ets_cfg.tc_tx_bw[j], en_dev->dcb_para.ets_cfg.prio_tc[j]);
-
-        LOG_INFO(" idx:%d, tc_type:%d, tc_tx_bw:%d \n", j, tc_type[j], tc_tx_bw[j]);
-    }
-
-    return 0;
-}
-
-static int zxdh_dcbnl_ieee_setets(struct net_device *netdev, struct ieee_ets *ets)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t err;
-    uint32_t j = 0;
-
-    /* debug */
-    for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++)
-    {
-        LOG_INFO(" idx:%d, ets->tc_tsa:%d, ets->tc_tx_bw:%d, ets->prio_tc:%d \n", j,
-                 ets->tc_tsa[j], ets->tc_tx_bw[j], ets->prio_tc[j]);
-    }
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF)
-    {
-        LOG_ERR(" coredev type is not a PF");
-        return -EOPNOTSUPP;
-    }
-
-    err = zxdh_dcbnl_check_ets_para(ets);
-    if (err)
-    {
-        return err;
-    }
-
-    err = zxdh_dcbnl_ieee_set_ets_para(en_priv, ets);
-    if (err)
-    {
-        return err;
-    }
-
-    return 0;
-}
-
-static int zxdh_dcbnl_ieee_getpfc(struct net_device *netdev, struct ieee_pfc *pfc)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t pfc_cur_tm_en = 0;
-    uint32_t pfc_cur_mac_en = 0;
-    int32_t ret = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-    LOG_INFO("zxdh_dcbnl_ieee_getpfc start\n");
-
-    /*获取端口pfc使能函数*/
-    ret = zxdh_en_fc_mode_get(en_dev, &pfc_cur_mac_en);
-    LOG_INFO("zxdh_en_fc_mode_get:%d", pfc_cur_mac_en);
-
-    if(0 != ret)
-    {
-        LOG_ERR("zxdh_port_pfc_enable_get failed");
-        return ret;
-    }
-    ret = dpp_qmu_port_pfc_get(&pf_info, en_dev->phy_port, &pfc_cur_tm_en);
-    LOG_INFO("dpp_qmu_port_pfc_get:%d", pfc_cur_tm_en);
-
-    if(ret != 0)
-    {
-        LOG_ERR("dpp_qmu_port_pfc_get failed");
-        return ret;
-    }
-    if((pfc_cur_tm_en == 1)&&(pfc_cur_mac_en == BIT(SPM_FC_PFC_FULL)))
-    {
-        pfc->pfc_en = 255;
-    }
-    else if((pfc_cur_tm_en == 0)&&(pfc_cur_mac_en == BIT(SPM_FC_NONE)))
-    {
-        pfc->pfc_en = 0;
-    }
-    else
-    {
-        //ret = -1;
-        LOG_INFO("pfc_cur_mac_en != pfc_cur_tm_en");
-    }
-
-    LOG_INFO("zxdh_dcbnl_ieee_getpfc end\n");
-
-    return ret;
-}
-
-static int zxdh_dcbnl_ieee_setpfc(struct net_device *netdev, struct ieee_pfc *pfc)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t port_mac_en = 0;
-    uint32_t port_tm_en = 0;
-    uint32_t ret = 0;
-    uint32_t test_pfc_mac_en = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    LOG_INFO("zxdh_dcbnl_ieee_setpfc start\n");
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-    //兼容现有工具考虑，后续开发工具后可以注释掉
-    if(pfc->pfc_en != 0 && pfc->pfc_en != 0xff )
-    {
-        LOG_INFO("pfc->pfc_en input invalid: %d", pfc->pfc_en);
-        return EINVAL;
-    }
-
-    if(pfc->pfc_en != 0)
-    {
-        port_mac_en = BIT(SPM_FC_PFC_FULL);
-        port_tm_en = 1;
-    }
-    else
-    {
-        port_mac_en = BIT(SPM_FC_NONE);
-        //不使能后重新设置为初始状态阈值
-        //ret = zxdh_port_th_update_to_default(en_dev);
-
-        if(ret)
-        {
-            LOG_INFO("zxdh_port_th_update_to_last failed");
-        }
-    }
-    /*tm端口pfc使能*/
-    //ret |= dpp_qmu_port_pfc_set(&pf_info, en_dev->phy_port, port_tm_en);
-    //dpp_qmu_port_pfc_get(&pf_info, en_dev->phy_port, &test_pfc_tm_en);
-    //LOG_INFO("dpp_qmu_port_pfc_get: %d", test_pfc_tm_en);
-
-    /*mac部分端口pfc使能*/
-    ret |= zxdh_en_fc_mode_set(en_dev, port_mac_en);
-    zxdh_en_fc_mode_get(en_dev, &test_pfc_mac_en);
-    LOG_INFO("zxdh_port_pfc_enable_get: %d", test_pfc_mac_en);
-
-    if(pfc->pfc_en != 0)
-    {
-        //ret = zxdh_port_th_update(en_dev);
-    }
-
-    /*错误判断及打印*/
-    if(0 != ret)
-    {
-        LOG_ERR("zxdh_dcbnl_ieee_setpfc pfc_en:%c failed, %d", pfc->pfc_en, ret);
-    }
-
-    LOG_INFO("zxdh_dcbnl_ieee_setpfc end\n");
-
-    return ret;
-}
-
-static int zxdh_dcbnl_ieee_getmaxrate(struct net_device *netdev, struct ieee_maxrate *maxrate)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t i = 0;
-    uint32_t j = 0;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF)
-    {
-        LOG_ERR("coredev type is not a PF");
-        return -EOPNOTSUPP;
-    }
-
-    for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++)
-    {
-        if (ZXDH_DCBNL_MAXRATE_KBITPS <= en_dev->dcb_para.tc_maxrate[i])
-        {
-            maxrate->tc_maxrate[i] = 0;  //0 indicates unlimited
-        }
-        else
-        {
-            maxrate->tc_maxrate[i] = en_dev->dcb_para.tc_maxrate[i];
-        }
-    }
-
-    /* debug */
-    for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++)
-    {
-        LOG_INFO(" tc:%d,tc_maxrate:%lld \n", j, maxrate->tc_maxrate[j]);
-    }
-
-    return 0;
-}
-
-static int zxdh_dcbnl_ieee_setmaxrate(struct net_device *netdev, struct ieee_maxrate *maxrate)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t maxrate_kbps[ZXDH_DCBNL_MAX_TRAFFIC_CLASS] = {0};
-    uint32_t err,i;
-    uint32_t j = 0;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF)
-    {
-        LOG_ERR("coredev type is not a PF");
-        return -EOPNOTSUPP;
-    }
-
-    /* Values are 64 bits and specified in Kbps */
-    for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++)
-    {
-        if ((maxrate->tc_maxrate[i] == 0) || (maxrate->tc_maxrate[i] >= ZXDH_DCBNL_MAXRATE_KBITPS))
-        {
-            maxrate_kbps[i] = ZXDH_DCBNL_MAXRATE_KBITPS;
-        }
-        else if (maxrate->tc_maxrate[i] <= ZXDH_DCBNL_MINRATE_KBITPS)
-        {
-            maxrate_kbps[i] = ZXDH_DCBNL_MINRATE_KBITPS;
-        }
-        else
-        {
-            maxrate_kbps[i] = (uint32_t)maxrate->tc_maxrate[i];
-        }
-    }
-    /* debug */
-    for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++)
-    {
-        LOG_INFO(" tc:%d,maxrate->tc_maxrate:%lld,maxrate_kbps:%d \n",
-                 j, maxrate->tc_maxrate[j], maxrate_kbps[j]);
-    }
-
-    err = zxdh_dcbnl_set_tc_maxrate(en_priv, maxrate_kbps);
-    if (err)
-    {
-        return err;
-    }
-
-    return 0;
-}
-
-
-static int zxdh_dcbnl_ieee_setapp(struct net_device *netdev, struct dcb_app *app)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct dcb_app app_old;
-    bool is_new = false;
-    int err = 0;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF)
-    {
-        LOG_ERR(" coredev type is not a PF");
-        return -EOPNOTSUPP;
-    }
-
-    if ((app->selector != IEEE_8021QAZ_APP_SEL_DSCP) ||
-        (app->protocol >= ZXDH_DCBNL_MAX_DSCP) ||
-        (app->priority >= ZXDH_DCBNL_MAX_PRIORITY))
-    {
-        return -EINVAL;
-    }
-    /* Save the old entry info */
-    app_old.selector = IEEE_8021QAZ_APP_SEL_DSCP;
-    app_old.protocol = app->protocol;
-    app_old.priority = en_dev->dcb_para.dscp2prio[app->protocol];
-
-    LOG_INFO(" protocol:%d, priority:%d \n", app->protocol, app->priority);
-
-    if (!en_dev->dcb_para.dscp_app_num)
-    {
-        err =  zxdh_dcbnl_set_ets_trust(en_priv, ZXDH_DCBNL_ETS_TRUST_DSCP);
-        if (err)
-        {
-            return err;
-        }
-    }
-
-    if (app->priority != en_dev->dcb_para.dscp2prio[app->protocol])
-    {
-        err = zxdh_dcbnl_set_dscp2prio(en_priv, app->protocol, app->priority);
-        if (err)
-        {
-            zxdh_dcbnl_set_ets_trust(en_priv, ZXDH_DCBNL_ETS_TRUST_PCP);
-            return err;
-        }
-    }
-
-    /* Delete the old entry if exists */
-    err = dcb_ieee_delapp(netdev, &app_old);
-    if (err)
-    {
-        is_new = true;
-    }
-    /* Add new entry and update counter */
-    err = dcb_ieee_setapp(netdev, app);
-    if (err)
-    {
-        return err;
-    }
-    if (is_new)
-    {
-        en_dev->dcb_para.dscp_app_num++;
-    }
-    LOG_INFO(" dscp_app_num:%d \n", en_dev->dcb_para.dscp_app_num);
-
-    return err;
-}
-
-static int zxdh_dcbnl_ieee_delapp(struct net_device *netdev, struct dcb_app *app)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int err = 0;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF)
-    {
-        LOG_ERR("zxdh_dcbnl_ieee_delapp coredev type is not a PF");
-        return -EOPNOTSUPP;
-    }
-
-    if ((app->selector != IEEE_8021QAZ_APP_SEL_DSCP) ||
-        (app->protocol >= ZXDH_DCBNL_MAX_DSCP))
-    {
-        return -EINVAL;
-    }
-
-    if (!en_dev->dcb_para.dscp_app_num)
-    {
-        return -ENOENT;
-    }
-
-    if (app->priority != en_dev->dcb_para.dscp2prio[app->protocol])
-    {
-        return -ENOENT;
-    }
-
-    /* Delete the app entry */
-    err = dcb_ieee_delapp(netdev, app);
-    if (err)
-    {
-        return err;
-    }
-
-    /* Restore to default */
-    err = zxdh_dcbnl_set_dscp2prio(en_priv, app->protocol, app->protocol>>3);
-    if (err)
-    {
-        zxdh_dcbnl_set_ets_trust(en_priv, ZXDH_DCBNL_ETS_TRUST_PCP);
-        return err;
-    }
-    en_dev->dcb_para.dscp_app_num--;
-    LOG_INFO(" protocol:%d, dscp_app_num:%d \n", app->protocol, en_dev->dcb_para.dscp_app_num);
-
-    if (!en_dev->dcb_para.dscp_app_num)
-    {
-        err = zxdh_dcbnl_set_ets_trust(en_priv, ZXDH_DCBNL_ETS_TRUST_PCP);
-    }
-
-    return err;
-
-}
-#ifdef ZXDH_DCBNL_CEE_SUPPORT
-static void zxdh_dcbnl_setpgtccfgtx(struct net_device *netdev, int tc,
-                                   uint8_t prio_type, uint8_t pgid,
-                                   uint8_t bw_pct, uint8_t up_map)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_dcbnl_cee_ets *cee_ets_cfg;
-    uint32_t i;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF)
-    {
-        LOG_ERR("zxdh_dcbnl_setpgtccfgtx coredev type is not a PF");
-        return;
-    }
-
-    if ((tc < 0) || (tc >= ZXDH_DCBNL_MAX_TRAFFIC_CLASS))
-    {
-        return;
-    }
-
-    cee_ets_cfg = &en_dev->dcb_para.cee_ets_cfg;
-    for (i = 0; i < ZXDH_DCBNL_MAX_PRIORITY; i++)
-    {
-        if (up_map & BIT(i))
-        {
-            cee_ets_cfg->prio_tc[i] = tc;
-        }
-    }
-    cee_ets_cfg->tc_tsa[tc] = IEEE_8021QAZ_TSA_ETS;
-
-}
-static void zxdh_dcbnl_setpgbwgcfgtx(struct net_device *netdev, int pgid, uint8_t bw_pct)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF)
-    {
-        LOG_ERR("zxdh_dcbnl_setpgbwgcfgtx coredev type is not a PF");
-        return;
-    }
-
-    if ((pgid >= 0) && (pgid < ZXDH_DCBNL_MAX_TRAFFIC_CLASS))
-    {
-        en_dev->dcb_para.cee_ets_cfg.tc_tx_bw[pgid] = bw_pct;
-    }
-    LOG_INFO(" tc_tx_bw[%d]:%d \n", pgid, bw_pct);
-
-}
-
-static void zxdh_dcbnl_getpgtccfgtx(struct net_device *netdev, int prio,
-                                    uint8_t *prio_type, uint8_t *pgid,
-                                    uint8_t *bw_pct, uint8_t *up_map)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    /* pf检查 */
-    if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF)
-    {
-        LOG_ERR("zxdh_dcbnl_getpgtccfgtx coredev type is not a PF");
-        return;
-    }
-
-    if ((prio >= 0) && (prio < ZXDH_DCBNL_MAX_PRIORITY))
-    {
-        *pgid = en_dev->dcb_para.ets_cfg.prio_tc[prio];
-    }
-
-}
-
-static void zxdh_dcbnl_getpgbwgcfgtx(struct net_device *netdev, int pgid, uint8_t *bw_pct)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF)
-    {
-        LOG_ERR("zxdh_dcbnl_getpgbwgcfgtx coredev type is not a PF");
-        return;
-    }
-
-    if ((pgid >= 0) && (pgid < ZXDH_DCBNL_MAX_TRAFFIC_CLASS))
-    {
-        *bw_pct = en_dev->dcb_para.ets_cfg.tc_tx_bw[pgid];
-    }
-
-}
-
-
-static void zxdh_dcbnl_setpgtccfgrx(struct net_device *netdev, int prio,
-                                   uint8_t prio_type, uint8_t pgid,
-                                   uint8_t bw_pct, uint8_t up_map)
-{
-    LOG_ERR("Rx PG TC Config Not Supported.\n");
-}
-
-static void zxdh_dcbnl_setpgbwgcfgrx(struct net_device *netdev, int pgid, uint8_t bw_pct)
-{
-    LOG_ERR("Rx PG BWG Config Not Supported.\n");
-}
-
-
-static void zxdh_dcbnl_getpgtccfgrx(struct net_device *netdev, int prio,
-                                    uint8_t *prio_type, uint8_t *pgid,
-                                    uint8_t *bw_pct, uint8_t *up_map)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF)
-    {
-        LOG_ERR("zxdh_dcbnl_getpgtccfgrx coredev type is not a PF");
-        return;
-    }
-
-    if ((prio >= 0) && (prio < ZXDH_DCBNL_MAX_PRIORITY))
-    {
-        *pgid = en_dev->dcb_para.ets_cfg.prio_tc[prio];
-    }
-
-}
-
-static void zxdh_dcbnl_getpgbwgcfgrx(struct net_device *netdev, int pgid, uint8_t *bw_pct)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF)
-    {
-        LOG_ERR("zxdh_dcbnl_getpgbwgcfgrx coredev type is not a PF");
-        return;
-    }
-
-    if ((pgid >= 0) && (pgid < ZXDH_DCBNL_MAX_TRAFFIC_CLASS))
-    {
-        *bw_pct = 0;
-    }
-
-}
-
-static uint8_t zxdh_dcbnl_setall(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct ieee_ets ets = {0};
-    uint32_t i = 0;
-    uint32_t err = 0;
-    uint32_t j = 0;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF)
-    {
-        LOG_ERR("zxdh_dcbnl_setall coredev type is not a PF");
-        return 1;
-    }
-
-    ets.ets_cap = ZXDH_DCBNL_MAX_TRAFFIC_CLASS;
-    for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++)
-    {
-        ets.tc_tx_bw[i] = en_dev->dcb_para.cee_ets_cfg.tc_tx_bw[i];
-        ets.tc_rx_bw[i] = en_dev->dcb_para.cee_ets_cfg.tc_tx_bw[i];
-        ets.tc_tsa[i] = en_dev->dcb_para.cee_ets_cfg.tc_tsa[i];
-    }
-
-    for (i = 0; i < ZXDH_DCBNL_MAX_PRIORITY; i++)
-    {
-        ets.prio_tc[i] = en_dev->dcb_para.cee_ets_cfg.prio_tc[i];
-    }
-    /* debug */
-    for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++)
-    {
-        LOG_INFO(" idx:%d, tc_tsa:%d, tc_tx_bw:%d, prio_tc:%d \n", j, ets.tc_tx_bw[j], ets.tc_tsa[j], ets.prio_tc[j]);
-    }
-
-    err = zxdh_dcbnl_check_ets_para(&ets);
-    if (err)
-    {
-        return err;
-    }
-
-    err = zxdh_dcbnl_ieee_set_ets_para(en_priv, &ets);
-    if (err)
-    {
-        return err;
-    }
-
-    return 0;
-}
-
-static uint8_t zxdh_dcbnl_getstate(struct net_device *netdev)
-{
-    return ZXDH_DCBNL_CEE_STATE_UP;
-}
-
-static uint8_t zxdh_dcbnl_setstate(struct net_device *netdev, u8 state)
-{
-
-    return 0;
-}
-#endif
-
-static const struct dcbnl_rtnl_ops zxdh_dcbnl_ops ={
-    .ieee_getets    = zxdh_dcbnl_ieee_getets,
-    .ieee_setets    = zxdh_dcbnl_ieee_setets,
-    .ieee_getpfc    = zxdh_dcbnl_ieee_getpfc,
-    .ieee_setpfc    = zxdh_dcbnl_ieee_setpfc,
-
-    .ieee_getmaxrate = zxdh_dcbnl_ieee_getmaxrate,
-    .ieee_setmaxrate = zxdh_dcbnl_ieee_setmaxrate,
-
-    .ieee_setapp    = zxdh_dcbnl_ieee_setapp,
-    .ieee_delapp    = zxdh_dcbnl_ieee_delapp,
-
-#ifdef ZXDH_DCBNL_CEE_SUPPORT
-    /* CEE not support */
-    .setall         = zxdh_dcbnl_setall,
-
-    .getstate       = zxdh_dcbnl_getstate,
-    .setstate       = zxdh_dcbnl_setstate,
-
-    .setpgtccfgtx   = zxdh_dcbnl_setpgtccfgtx,
-    .setpgbwgcfgtx  = zxdh_dcbnl_setpgbwgcfgtx,
-    .getpgtccfgtx   = zxdh_dcbnl_getpgtccfgtx,
-    .getpgbwgcfgtx  = zxdh_dcbnl_getpgbwgcfgtx,
-
-    .setpgtccfgrx   = zxdh_dcbnl_setpgtccfgrx,
-    .setpgbwgcfgrx  = zxdh_dcbnl_setpgbwgcfgrx,
-    .getpgtccfgrx   = zxdh_dcbnl_getpgtccfgrx,
-    .getpgbwgcfgrx  = zxdh_dcbnl_getpgbwgcfgrx,
-#endif
-};
-
-uint32_t zxdh_dcbnl_set_tm_pport_mcode_gate_open(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    uint32_t err = 0;
-    err = zxdh_dcbnl_set_tm_gate(en_priv, 1);
-    if (err)
-    {
-        LOG_ERR(" set_tm_gate close failed \n");
-    }
-    LOG_INFO(" tm mcode gate open ");
-    return err;
-}
-
-uint32_t zxdh_dcbnl_set_tm_pport_mcode_gate_close(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    uint32_t err = 0;
-    err = zxdh_dcbnl_set_tm_gate(en_priv, 0);
-    if (err)
-    {
-        LOG_ERR(" set_tm_gate close failed \n");
-    }
-    LOG_INFO(" tm mcode gate close ");
-    return err;
-}
-
-uint32_t zxdh_dcbnl_initialize(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t err = 0;
-
-    LOG_INFO("%s dcbnl init begin\n", netdev->name);
-
-    err = zxdh_dcbnl_init_port_speed(en_priv);
-    if (err)
-    {
-        LOG_INFO("dcbnl_init_ets: init_port_speed failed \n");
-        //return err;
-    }
-
-    err = zxdh_dcbnl_init_ets_scheduling_tree(en_priv);
-    if (err)
-    {
-        LOG_ERR("dcbnl_init_ets: init_ets_scheduling_tree failed \n");
-        return err;
-    }
-
-    zxdh_dcbnl_printk_ets_tree(en_priv);
-
-    zxdh_dcbnl_pfc_init(en_priv);
-
-    en_dev->dcb_para.init_flag = ZXDH_DCBNL_INIT_FLAG;
-    netdev->dcbnl_ops = &zxdh_dcbnl_ops;
-    zxdh_dcbnl_set_tm_pport_mcode_gate_open(netdev);
-    LOG_INFO("%s dcbnl init ok ", netdev->name);
-    return 0;
-}
-
-uint32_t zxdh_dcbnl_ets_uninit(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF)
-    {
-        return 0;
-    }
-    LOG_INFO("%s dcbnl uninit begin\n", netdev->name);
-
-    en_dev->dcb_para.init_flag = 0;
-    netdev->dcbnl_ops = NULL;
-    zxdh_dcbnl_set_tm_pport_mcode_gate_close(netdev);
-
-    zxdh_dcbnl_free_flow_resources(en_priv);
-
-    zxdh_dcbnl_free_se_resources(en_priv);
-
-    LOG_INFO("%s dcbnl uninit ok ", netdev->name);
-    return 0;
-}
+//#include <linux/device.h>
+#include "../../en_aux.h"
+#include "en_dcbnl.h"
+#include "en_np/qos/include/dpp_drv_qos.h"
+#include "en_aux/en_cmd.h"
+#include "en_dcbnl_api.h"
+
+static int zxdh_dcbnl_ieee_getets(struct net_device *netdev,
+								  struct ieee_ets *ets)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t tc = 0;
+	uint32_t j = 0;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) {
+		LOG_ERR("zxdh_dcbnl_ieee_getets: coredev type is not a PF");
+		return -EOPNOTSUPP;
+	}
+
+	ets->willing = 0;
+
+	ets->ets_cap = ZXDH_DCBNL_MAX_TRAFFIC_CLASS;
+
+	memcpy(ets->tc_tsa, en_dev->dcb_para.ets_cfg.tc_tsa, sizeof(ets->tc_tsa));
+	memcpy(ets->tc_tx_bw, en_dev->dcb_para.ets_cfg.tc_tx_bw,
+		   sizeof(ets->tc_tx_bw));
+	memcpy(ets->prio_tc, en_dev->dcb_para.ets_cfg.prio_tc,
+		   sizeof(ets->prio_tc));
+
+	for (tc = 0; tc < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; tc++) {
+		if (ets->tc_tsa[tc] != IEEE_8021QAZ_TSA_ETS) {
+			ets->tc_tx_bw[tc] = 0;
+		}
+	}
+
+	/* debug */
+	for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++) {
+		LOG_INFO(
+				" idx:%d, ets->tc_tsa:%d, ets->tc_tx_bw:%d, ets->prio_tc:%d \n",
+				j, ets->tc_tsa[j], ets->tc_tx_bw[j], ets->prio_tc[j]);
+	}
+
+	return 0;
+}
+
+static int zxdh_dcbnl_check_ets_maxtc(struct ieee_ets *ets)
+{
+	uint32_t i;
+
+	for (i = 0; i < ZXDH_DCBNL_MAX_PRIORITY; i++) {
+		if (ets->prio_tc[i] >= ZXDH_DCBNL_MAX_TRAFFIC_CLASS) {
+			LOG_ERR("dcbnl_check_ets: Failed! TC value greater than max(%d)\n",
+					ZXDH_DCBNL_MAX_TRAFFIC_CLASS);
+			return 1;
+		}
+	}
+	return 0;
+}
+
+static int zxdh_dcbnl_check_ets_tcbw(struct ieee_ets *ets)
+{
+	bool have_ets_tc = false;
+	uint32_t bw_sum = 0;
+	uint32_t i;
+
+	for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++) {
+		if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) {
+			have_ets_tc = true;
+			bw_sum += ets->tc_tx_bw[i];
+		}
+	}
+
+	if (have_ets_tc && ((bw_sum != 100) && (bw_sum != 0))) {
+		LOG_ERR("dcbnl_check_ets_tcbw: Failed! ETS BW sum is illegal\n");
+		return 1;
+	}
+
+	return 0;
+}
+
+static int zxdh_dcbnl_check_ets_para(struct ieee_ets *ets)
+{
+	uint32_t err = 0;
+
+	err = zxdh_dcbnl_check_ets_maxtc(ets);
+	if (err) {
+		return -EINVAL;
+	}
+
+	err = zxdh_dcbnl_check_ets_tcbw(ets);
+	if (err) {
+		return -EINVAL;
+	}
+	LOG_INFO(" end \n");
+	return 0;
+}
+
+static int zxdh_dcbnl_ieee_divide_tc_type(struct ieee_ets *ets,
+										  uint8_t *tc_type)
+{
+	uint32_t i;
+
+	for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++) {
+		switch (ets->tc_tsa[i]) {
+		case IEEE_8021QAZ_TSA_ETS:
+			tc_type[i] = ets->tc_tx_bw[i] ? ZXDH_DCBNL_ETS_TC :
+											  ZXDH_DCBNL_ZEROBW_ETS_TC;
+			break;
+		case IEEE_8021QAZ_TSA_STRICT:
+			tc_type[i] = ZXDH_DCBNL_STRICT_TC;
+			break;
+		case IEEE_8021QAZ_TSA_VENDOR:
+			tc_type[i] = ZXDH_DCBNL_VENDOR_TC;
+			break;
+		default:
+			tc_type[i] = ZXDH_DCBNL_STRICT_TC;
+			LOG_ERR("dcbnl: %d tsa error, change to strict \n", ets->tc_tsa[i]);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static int zxdh_dcbnl_ieee_convert_tc_bw(struct ieee_ets *ets, uint8_t *tc_type,
+										 uint8_t *tc_tx_bw)
+{
+	uint32_t i;
+	uint8_t zero_ets_bw = 0;
+	uint8_t zero_ets_num = 0;
+
+	for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++) {
+		if (tc_type[i] == ZXDH_DCBNL_ZEROBW_ETS_TC) {
+			zero_ets_num++;
+		}
+	}
+
+	if (zero_ets_num) {
+		zero_ets_bw = (uint8_t)ZXDH_DCBNL_MAX_BW_ALLOC / zero_ets_num;
+	}
+
+	for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++) {
+		switch (tc_type[i]) {
+		case ZXDH_DCBNL_ZEROBW_ETS_TC:
+			tc_tx_bw[i] = zero_ets_bw;
+			break;
+		case ZXDH_DCBNL_ETS_TC:
+			tc_tx_bw[i] = ets->tc_tx_bw[i];
+			break;
+		case ZXDH_DCBNL_STRICT_TC:
+		case ZXDH_DCBNL_VENDOR_TC:
+			tc_tx_bw[i] = ZXDH_DCBNL_MAX_BW_ALLOC;
+			break;
+		default:
+			break;
+		}
+	}
+	/* debug */
+	LOG_INFO(" zero_ets_num:%d, zero_ets_bw:%d \n", zero_ets_num, zero_ets_bw);
+
+	return 0;
+}
+
+static uint32_t zxdh_dcbnl_ieee_set_ets_para(struct zxdh_en_priv *en_priv,
+											 struct ieee_ets *ets)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint8_t tc_type[ZXDH_DCBNL_MAX_TRAFFIC_CLASS];
+	uint8_t tc_tx_bw[ZXDH_DCBNL_MAX_TRAFFIC_CLASS];
+	uint32_t err = 0;
+	uint32_t j = 0;
+
+	zxdh_dcbnl_ieee_divide_tc_type(ets, tc_type);
+
+	zxdh_dcbnl_ieee_convert_tc_bw(ets, tc_type, tc_tx_bw);
+
+	err = zxdh_dcbnl_set_tc_scheduling(en_priv, tc_type, tc_tx_bw);
+	if (err) {
+		LOG_ERR("set_tc_scheduling failed \n");
+		return err;
+	}
+
+	err = zxdh_dcbnl_set_ets_up_tc_map(en_priv, ets->prio_tc);
+	if (err) {
+		LOG_ERR("set_prio_tc_map failed \n");
+		return err;
+	}
+
+	memcpy(en_dev->dcb_para.ets_cfg.tc_tsa, ets->tc_tsa, sizeof(ets->tc_tsa));
+	memcpy(en_dev->dcb_para.ets_cfg.tc_tx_bw, ets->tc_tx_bw,
+		   sizeof(ets->tc_tx_bw));
+	memcpy(en_dev->dcb_para.ets_cfg.prio_tc, ets->prio_tc,
+		   sizeof(ets->prio_tc));
+	/* debug */
+	for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++) {
+		LOG_INFO(" idx:%d, tc_tsa:%d, tc_tx_bw:%d, prio_tc:%d \n", j,
+				 en_dev->dcb_para.ets_cfg.tc_tsa[j],
+				 en_dev->dcb_para.ets_cfg.tc_tx_bw[j],
+				 en_dev->dcb_para.ets_cfg.prio_tc[j]);
+
+		LOG_INFO(" idx:%d, tc_type:%d, tc_tx_bw:%d \n", j, tc_type[j],
+				 tc_tx_bw[j]);
+	}
+
+	return 0;
+}
+
+static int zxdh_dcbnl_ieee_setets(struct net_device *netdev,
+								  struct ieee_ets *ets)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t err;
+	uint32_t j = 0;
+
+	/* debug */
+	for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++) {
+		LOG_INFO(
+				" idx:%d, ets->tc_tsa:%d, ets->tc_tx_bw:%d, ets->prio_tc:%d \n",
+				j, ets->tc_tsa[j], ets->tc_tx_bw[j], ets->prio_tc[j]);
+	}
+
+	/* 检查设备是否支持ets，cap，待补充 */
+	/*if (!DH_CAP_GEN(en_priv->parent, ets))
+  {
+      return -EOPNOTSUPP;
+  }*/
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) {
+		LOG_ERR(" coredev type is not a PF");
+		return -EOPNOTSUPP;
+	}
+
+	err = zxdh_dcbnl_check_ets_para(ets);
+	if (err) {
+		return err;
+	}
+
+	err = zxdh_dcbnl_ieee_set_ets_para(en_priv, ets);
+	if (err) {
+		return err;
+	}
+
+	return 0;
+}
+
+static int zxdh_dcbnl_ieee_getpfc(struct net_device *netdev,
+								  struct ieee_pfc *pfc)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t pfc_cur_tm_en = 0;
+	uint32_t pfc_cur_mac_en = 0;
+	int32_t ret = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+	LOG_INFO("zxdh_dcbnl_ieee_getpfc start\n");
+
+	/*获取端口pfc使能函数*/
+	ret = zxdh_en_fc_mode_get(en_dev, &pfc_cur_mac_en);
+	LOG_INFO("zxdh_en_fc_mode_get:%d", pfc_cur_mac_en);
+
+	if (0 != ret) {
+		LOG_ERR("zxdh_port_pfc_enable_get failed");
+		return ret;
+	}
+	ret = dpp_qmu_port_pfc_get(&pf_info, en_dev->phy_port, &pfc_cur_tm_en);
+	LOG_INFO("dpp_qmu_port_pfc_get:%d", pfc_cur_tm_en);
+
+	if (ret != 0) {
+		LOG_ERR("dpp_qmu_port_pfc_get failed");
+		return ret;
+	}
+	if ((pfc_cur_tm_en == 1) && (pfc_cur_mac_en == BIT(SPM_FC_PFC_FULL))) {
+		pfc->pfc_en = 255;
+	} else if ((pfc_cur_tm_en == 0) && (pfc_cur_mac_en == BIT(SPM_FC_NONE))) {
+		pfc->pfc_en = 0;
+	} else {
+		// ret = -1;
+		LOG_INFO("pfc_cur_mac_en != pfc_cur_tm_en");
+	}
+
+	LOG_INFO("zxdh_dcbnl_ieee_getpfc end\n");
+
+	return ret;
+}
+
+static int zxdh_dcbnl_ieee_setpfc(struct net_device *netdev,
+								  struct ieee_pfc *pfc)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t port_mac_en = 0;
+	uint32_t port_tm_en = 0;
+	uint32_t ret = 0;
+	uint32_t test_pfc_mac_en = 0;
+	uint32_t test_pfc_tm_en = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	LOG_INFO("zxdh_dcbnl_ieee_setpfc start\n");
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+	//兼容现有工具考虑，后续开发工具后可以注释掉
+	if (pfc->pfc_en != 0 && pfc->pfc_en != 0xff) {
+		LOG_INFO("pfc->pfc_en input invalid: %d", pfc->pfc_en);
+		return EINVAL;
+	}
+
+	if (pfc->pfc_en != 0) {
+		port_mac_en = BIT(SPM_FC_PFC_FULL);
+		port_tm_en = 1;
+	} else {
+		port_mac_en = BIT(SPM_FC_NONE);
+		//不使能后重新设置为初始状态阈值
+		ret = zxdh_port_th_update_to_default(en_dev);
+
+		if (ret) {
+			LOG_INFO("zxdh_port_th_update_to_last failed");
+		}
+	}
+	/*tm端口pfc使能*/
+	ret |= dpp_qmu_port_pfc_set(&pf_info, en_dev->phy_port, port_tm_en);
+	dpp_qmu_port_pfc_get(&pf_info, en_dev->phy_port, &test_pfc_tm_en);
+	LOG_INFO("dpp_qmu_port_pfc_get: %d", test_pfc_tm_en);
+
+	/*mac部分端口pfc使能*/
+	ret |= zxdh_en_fc_mode_set(en_dev, port_mac_en);
+	zxdh_en_fc_mode_get(en_dev, &test_pfc_mac_en);
+	LOG_INFO("zxdh_port_pfc_enable_get: %d", test_pfc_mac_en);
+
+	if (pfc->pfc_en != 0) {
+		ret = zxdh_port_th_update(en_dev);
+	}
+	if (ret) {
+		LOG_INFO("zxdh_port_th_update failed");
+	}
+
+	/*错误判断及打印*/
+	if (0 != ret) {
+		LOG_ERR("zxdh_dcbnl_ieee_setpfc pfc_en:%c failed, %d", pfc->pfc_en,
+				ret);
+	}
+
+	LOG_INFO("zxdh_dcbnl_ieee_setpfc end\n");
+
+	return ret;
+}
+
+static int zxdh_dcbnl_ieee_getmaxrate(struct net_device *netdev,
+									  struct ieee_maxrate *maxrate)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t i = 0;
+	uint32_t j = 0;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) {
+		LOG_ERR("coredev type is not a PF");
+		return -EOPNOTSUPP;
+	}
+
+	for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++) {
+		if (ZXDH_DCBNL_MAXRATE_KBITPS <= en_dev->dcb_para.tc_maxrate[i]) {
+			maxrate->tc_maxrate[i] = 0; // 0 indicates unlimited
+		} else {
+			maxrate->tc_maxrate[i] = en_dev->dcb_para.tc_maxrate[i];
+		}
+	}
+
+	/* debug */
+	for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++) {
+		LOG_INFO(" tc:%d,tc_maxrate:%lld \n", j, maxrate->tc_maxrate[j]);
+	}
+
+	return 0;
+}
+
+static int zxdh_dcbnl_ieee_setmaxrate(struct net_device *netdev,
+									  struct ieee_maxrate *maxrate)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t maxrate_kbps[ZXDH_DCBNL_MAX_TRAFFIC_CLASS] = { 0 };
+	uint32_t err, i;
+	uint32_t j = 0;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) {
+		LOG_ERR("coredev type is not a PF");
+		return -EOPNOTSUPP;
+	}
+
+	/* Values are 64 bits and specified in Kbps */
+	for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++) {
+		if ((maxrate->tc_maxrate[i] == 0) ||
+			(maxrate->tc_maxrate[i] >= ZXDH_DCBNL_MAXRATE_KBITPS)) {
+			maxrate_kbps[i] = ZXDH_DCBNL_MAXRATE_KBITPS;
+		} else if (maxrate->tc_maxrate[i] <= ZXDH_DCBNL_MINRATE_KBITPS) {
+			maxrate_kbps[i] = ZXDH_DCBNL_MINRATE_KBITPS;
+		} else {
+			maxrate_kbps[i] = (uint32_t)maxrate->tc_maxrate[i];
+		}
+	}
+	/* debug */
+	for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++) {
+		LOG_INFO(" tc:%d,maxrate->tc_maxrate:%lld,maxrate_kbps:%d \n", j,
+				 maxrate->tc_maxrate[j], maxrate_kbps[j]);
+	}
+
+	err = zxdh_dcbnl_set_tc_maxrate(en_priv, maxrate_kbps);
+	if (err) {
+		return err;
+	}
+
+	return 0;
+}
+
+static int zxdh_dcbnl_ieee_setapp(struct net_device *netdev,
+								  struct dcb_app *app)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct dcb_app app_old;
+	bool is_new = false;
+	int err = 0;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) {
+		LOG_ERR(" coredev type is not a PF");
+		return -EOPNOTSUPP;
+	}
+
+	if ((app->selector != IEEE_8021QAZ_APP_SEL_DSCP) ||
+		(app->protocol >= ZXDH_DCBNL_MAX_DSCP) ||
+		(app->priority >= ZXDH_DCBNL_MAX_PRIORITY)) {
+		return -EINVAL;
+	}
+	/* Save the old entry info */
+	app_old.selector = IEEE_8021QAZ_APP_SEL_DSCP;
+	app_old.protocol = app->protocol;
+	app_old.priority = en_dev->dcb_para.dscp2prio[app->protocol];
+
+	LOG_INFO(" protocol:%d, priority:%d \n", app->protocol, app->priority);
+
+	if (!en_dev->dcb_para.dscp_app_num) {
+		err = zxdh_dcbnl_set_ets_trust(en_priv, ZXDH_DCBNL_ETS_TRUST_DSCP);
+		if (err) {
+			return err;
+		}
+	}
+
+	if (app->priority != en_dev->dcb_para.dscp2prio[app->protocol]) {
+		err = zxdh_dcbnl_set_dscp2prio(en_priv, app->protocol, app->priority);
+		if (err) {
+			zxdh_dcbnl_set_ets_trust(en_priv, ZXDH_DCBNL_ETS_TRUST_PCP);
+			return err;
+		}
+	}
+
+	/* Delete the old entry if exists */
+	err = dcb_ieee_delapp(netdev, &app_old);
+	if (err) {
+		is_new = true;
+	}
+	/* Add new entry and update counter */
+	err = dcb_ieee_setapp(netdev, app);
+	if (err) {
+		return err;
+	}
+	if (is_new) {
+		en_dev->dcb_para.dscp_app_num++;
+	}
+	LOG_INFO(" dscp_app_num:%d \n", en_dev->dcb_para.dscp_app_num);
+
+	return err;
+}
+
+static int zxdh_dcbnl_ieee_delapp(struct net_device *netdev,
+								  struct dcb_app *app)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int err = 0;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) {
+		LOG_ERR("zxdh_dcbnl_ieee_delapp coredev type is not a PF");
+		return -EOPNOTSUPP;
+	}
+
+	if ((app->selector != IEEE_8021QAZ_APP_SEL_DSCP) ||
+		(app->protocol >= ZXDH_DCBNL_MAX_DSCP)) {
+		return -EINVAL;
+	}
+
+	if (!en_dev->dcb_para.dscp_app_num) {
+		return -ENOENT;
+	}
+
+	if (app->priority != en_dev->dcb_para.dscp2prio[app->protocol]) {
+		return -ENOENT;
+	}
+
+	/* Delete the app entry */
+	err = dcb_ieee_delapp(netdev, app);
+	if (err) {
+		return err;
+	}
+
+	/* Restore to default */
+	err = zxdh_dcbnl_set_dscp2prio(en_priv, app->protocol, app->protocol >> 3);
+	if (err) {
+		zxdh_dcbnl_set_ets_trust(en_priv, ZXDH_DCBNL_ETS_TRUST_PCP);
+		return err;
+	}
+	en_dev->dcb_para.dscp_app_num--;
+	LOG_INFO(" protocol:%d, dscp_app_num:%d \n", app->protocol,
+			 en_dev->dcb_para.dscp_app_num);
+
+	if (!en_dev->dcb_para.dscp_app_num) {
+		err = zxdh_dcbnl_set_ets_trust(en_priv, ZXDH_DCBNL_ETS_TRUST_PCP);
+	}
+
+	return err;
+}
+
+static void zxdh_dcbnl_setpgtccfgtx(struct net_device *netdev, int tc,
+									uint8_t prio_type, uint8_t pgid,
+									uint8_t bw_pct, uint8_t up_map)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_dcbnl_cee_ets *cee_ets_cfg;
+	uint32_t i;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) {
+		LOG_ERR("zxdh_dcbnl_setpgtccfgtx coredev type is not a PF");
+		return;
+	}
+
+	if ((tc < 0) || (tc >= ZXDH_DCBNL_MAX_TRAFFIC_CLASS)) {
+		return;
+	}
+
+	cee_ets_cfg = &en_dev->dcb_para.cee_ets_cfg;
+	for (i = 0; i < ZXDH_DCBNL_MAX_PRIORITY; i++) {
+		if (up_map & BIT(i)) {
+			cee_ets_cfg->prio_tc[i] = tc;
+		}
+	}
+	cee_ets_cfg->tc_tsa[tc] = IEEE_8021QAZ_TSA_ETS;
+}
+static void zxdh_dcbnl_setpgbwgcfgtx(struct net_device *netdev, int pgid,
+									 uint8_t bw_pct)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) {
+		LOG_ERR("zxdh_dcbnl_setpgbwgcfgtx coredev type is not a PF");
+		return;
+	}
+
+	if ((pgid >= 0) && (pgid < ZXDH_DCBNL_MAX_TRAFFIC_CLASS)) {
+		en_dev->dcb_para.cee_ets_cfg.tc_tx_bw[pgid] = bw_pct;
+	}
+	LOG_INFO(" tc_tx_bw[%d]:%d \n", pgid, bw_pct);
+}
+
+static void zxdh_dcbnl_getpgtccfgtx(struct net_device *netdev, int prio,
+									uint8_t *prio_type, uint8_t *pgid,
+									uint8_t *bw_pct, uint8_t *up_map)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	/* pf检查 */
+	if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) {
+		LOG_ERR("zxdh_dcbnl_getpgtccfgtx coredev type is not a PF");
+		return;
+	}
+
+	if ((prio >= 0) && (prio < ZXDH_DCBNL_MAX_PRIORITY)) {
+		*pgid = en_dev->dcb_para.ets_cfg.prio_tc[prio];
+	}
+}
+
+static void zxdh_dcbnl_getpgbwgcfgtx(struct net_device *netdev, int pgid,
+									 uint8_t *bw_pct)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) {
+		LOG_ERR("zxdh_dcbnl_getpgbwgcfgtx coredev type is not a PF");
+		return;
+	}
+
+	if ((pgid >= 0) && (pgid < ZXDH_DCBNL_MAX_TRAFFIC_CLASS)) {
+		*bw_pct = en_dev->dcb_para.ets_cfg.tc_tx_bw[pgid];
+	}
+}
+
+static void zxdh_dcbnl_setpgtccfgrx(struct net_device *netdev, int prio,
+									uint8_t prio_type, uint8_t pgid,
+									uint8_t bw_pct, uint8_t up_map)
+{
+	LOG_ERR("Rx PG TC Config Not Supported.\n");
+}
+
+static void zxdh_dcbnl_setpgbwgcfgrx(struct net_device *netdev, int pgid,
+									 uint8_t bw_pct)
+{
+	LOG_ERR("Rx PG BWG Config Not Supported.\n");
+}
+
+static void zxdh_dcbnl_getpgtccfgrx(struct net_device *netdev, int prio,
+									uint8_t *prio_type, uint8_t *pgid,
+									uint8_t *bw_pct, uint8_t *up_map)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) {
+		LOG_ERR("zxdh_dcbnl_getpgtccfgrx coredev type is not a PF");
+		return;
+	}
+
+	if ((prio >= 0) && (prio < ZXDH_DCBNL_MAX_PRIORITY)) {
+		*pgid = en_dev->dcb_para.ets_cfg.prio_tc[prio];
+	}
+}
+
+static void zxdh_dcbnl_getpgbwgcfgrx(struct net_device *netdev, int pgid,
+									 uint8_t *bw_pct)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) {
+		LOG_ERR("zxdh_dcbnl_getpgbwgcfgrx coredev type is not a PF");
+		return;
+	}
+
+	if ((pgid >= 0) && (pgid < ZXDH_DCBNL_MAX_TRAFFIC_CLASS)) {
+		*bw_pct = 0;
+	}
+}
+
+static uint8_t zxdh_dcbnl_setall(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct ieee_ets ets = { 0 };
+	uint32_t i = 0;
+	uint32_t err = 0;
+	uint32_t j = 0;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) {
+		LOG_ERR("zxdh_dcbnl_setall coredev type is not a PF");
+		return 1;
+	}
+
+	ets.ets_cap = ZXDH_DCBNL_MAX_TRAFFIC_CLASS;
+	for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; i++) {
+		ets.tc_tx_bw[i] = en_dev->dcb_para.cee_ets_cfg.tc_tx_bw[i];
+		ets.tc_rx_bw[i] = en_dev->dcb_para.cee_ets_cfg.tc_tx_bw[i];
+		ets.tc_tsa[i] = en_dev->dcb_para.cee_ets_cfg.tc_tsa[i];
+	}
+
+	for (i = 0; i < ZXDH_DCBNL_MAX_PRIORITY; i++) {
+		ets.prio_tc[i] = en_dev->dcb_para.cee_ets_cfg.prio_tc[i];
+	}
+	/* debug */
+	for (j = 0; j < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; j++) {
+		LOG_INFO(" idx:%d, tc_tsa:%d, tc_tx_bw:%d, prio_tc:%d \n", j,
+				 ets.tc_tx_bw[j], ets.tc_tsa[j], ets.prio_tc[j]);
+	}
+
+	err = zxdh_dcbnl_check_ets_para(&ets);
+	if (err) {
+		return err;
+	}
+
+	err = zxdh_dcbnl_ieee_set_ets_para(en_priv, &ets);
+	if (err) {
+		return err;
+	}
+
+	return 0;
+}
+
+static uint8_t zxdh_dcbnl_getstate(struct net_device *netdev)
+{
+	return ZXDH_DCBNL_CEE_STATE_UP;
+}
+
+static uint8_t zxdh_dcbnl_setstate(struct net_device *netdev, u8 state)
+{
+	return 0;
+}
+
+static const struct dcbnl_rtnl_ops zxdh_dcbnl_ops = {
+	.ieee_getets = zxdh_dcbnl_ieee_getets,
+	.ieee_setets = zxdh_dcbnl_ieee_setets,
+	.ieee_getpfc = zxdh_dcbnl_ieee_getpfc,
+	.ieee_setpfc = zxdh_dcbnl_ieee_setpfc,
+
+	.ieee_getmaxrate = zxdh_dcbnl_ieee_getmaxrate,
+	.ieee_setmaxrate = zxdh_dcbnl_ieee_setmaxrate,
+
+	.ieee_setapp = zxdh_dcbnl_ieee_setapp,
+	.ieee_delapp = zxdh_dcbnl_ieee_delapp,
+
+	/* CEE */
+	.setall = zxdh_dcbnl_setall,
+
+	.getstate = zxdh_dcbnl_getstate,
+	.setstate = zxdh_dcbnl_setstate,
+
+	.setpgtccfgtx = zxdh_dcbnl_setpgtccfgtx,
+	.setpgbwgcfgtx = zxdh_dcbnl_setpgbwgcfgtx,
+	.getpgtccfgtx = zxdh_dcbnl_getpgtccfgtx,
+	.getpgbwgcfgtx = zxdh_dcbnl_getpgbwgcfgtx,
+
+	/*不支持RX的配置，这里只是为了通过__dcbnl_pg_setcfg中函数指针非空检查*/
+	.setpgtccfgrx = zxdh_dcbnl_setpgtccfgrx,
+	.setpgbwgcfgrx = zxdh_dcbnl_setpgbwgcfgrx,
+	.getpgtccfgrx = zxdh_dcbnl_getpgtccfgrx,
+	.getpgbwgcfgrx = zxdh_dcbnl_getpgbwgcfgrx,
+
+};
+
+uint32_t zxdh_dcbnl_set_tm_pport_mcode_gate_open(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	uint32_t err = 0;
+	err = zxdh_dcbnl_set_tm_gate(en_priv, 1);
+	if (err) {
+		LOG_ERR(" set_tm_gate close failed \n");
+	}
+	LOG_INFO(" tm mcode gate open ");
+	return err;
+}
+
+uint32_t zxdh_dcbnl_set_tm_pport_mcode_gate_close(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	uint32_t err = 0;
+	err = zxdh_dcbnl_set_tm_gate(en_priv, 0);
+	if (err) {
+		LOG_ERR(" set_tm_gate close failed \n");
+	}
+	LOG_INFO(" tm mcode gate close ");
+	return err;
+}
+
+uint32_t zxdh_dcbnl_initialize(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t err = 0;
+
+	err = zxdh_dcbnl_init_port_speed(en_priv);
+	if (err) {
+		LOG_INFO("dcbnl_init_ets: init_port_speed failed \n");
+		// return err;
+	}
+
+	err = zxdh_dcbnl_init_ets_scheduling_tree(en_priv);
+	if (err) {
+		LOG_ERR("dcbnl_init_ets: init_ets_scheduling_tree failed \n");
+		return err;
+	}
+
+	zxdh_dcbnl_printk_ets_tree(en_priv);
+
+	zxdh_dcbnl_pfc_init(en_priv);
+
+	en_dev->dcb_para.init_flag = ZXDH_DCBNL_INIT_FLAG;
+	netdev->dcbnl_ops = &zxdh_dcbnl_ops;
+	zxdh_dcbnl_set_tm_pport_mcode_gate_open(netdev);
+	LOG_INFO(" dcbnl init ok ");
+	return 0;
+}
+
+uint32_t zxdh_dcbnl_ets_uninit(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) != DH_COREDEV_PF) {
+		return 0;
+	}
+
+	en_dev->dcb_para.init_flag = 0;
+	netdev->dcbnl_ops = NULL;
+	zxdh_dcbnl_set_tm_pport_mcode_gate_close(netdev);
+
+	zxdh_dcbnl_free_flow_resources(en_priv);
+
+	zxdh_dcbnl_free_se_resources(en_priv);
+	LOG_INFO(" dcbnl uninit ok ");
+	return 0;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl.h b/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl.h
index 2ade85abf18217f2b8d711aae559c0689ff0da47..ed463ddc183ba8c4503e466908e6b8aac70fa763 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl.h
@@ -1,213 +1,202 @@
-#ifndef __ZXDH_EN_DCBNL_H__
-#define __ZXDH_EN_DCBNL_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/device.h>
-
-/* 启用dcb会大幅度增加初始化时间，暂时先注释 */
-//#define ZXDH_DCBNL_OPEN
-
-/* CEE not support */
-//#define ZXDH_DCBNL_CEE_SUPPORT
-
-#define ZXDH_DCBNL_INIT_FLAG (0x5a5a5a5a)
-#define ZXDH_DCBNL_NULL_ID (0xffffffff)
-
-#define ZXDH_DCBNL_MAX_PRIORITY (8)
-#define ZXDH_DCBNL_MAX_TRAFFIC_CLASS (8)
-
-#define ZXDH_DCBNL_MAX_DSCP (64)
-
-#define ZXDH_DCBNL_MAX_BW_ALLOC  (100)
-#define ZXDH_DCBNL_MAX_WEIGHT    (512)
-
-#define ZXDH_DCBNL_RATEUNIT_K    (1000)
-#define ZXDH_DCBNL_RATEUNIT_M    (1000000)
-#define ZXDH_DCBNL_RATEUNIT_G    (1000000000)
-#define ZXDH_DCBNL_MAXRATE_KBITPS (400*1000000)
-#define ZXDH_DCBNL_MINRATE_KBITPS (64)
-
-#define ZXDH_DCBNL_INITRATE_KBITPS (400*1000000)
-
-#define ZXDH_DCBNL_FLOW_RATE_CIR (0)
-
-#define ZXDH_DCBNL_FLOW_RATE_CBS (2000)
-#define ZXDH_DCBNL_FLOW_RATE_EBS (4000)
-#define ZXDH_DCBNL_PORT_RATE_CBS (4000)
-
-#define ZXDH_DCBNL_FLOW_RATE_CBS_REFRESH (0)
-#define ZXDH_DCBNL_FLOW_RATE_EBS_REFRESH (0)
-
-#define ZXDH_DCBNL_FLOW_TDTH (150)
-
-#define ZXDH_DCBNL_CEE_STATE_UP  (1)
-
-#define ZXDH_DCBNL_MAX_SE_NODE_NUM      (12)
-#define ZXDH_DCBNL_MAX_TREE_LEVEL       (7)
-#define ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL  (4)
-#define ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL  (0)
-
-#define ZXDH_DCBNL_GSCHID_ID_MASK   (0xFFFF)
-#define ZXDH_DCBNL_GSCHID_ID_SHIFT  (0)
-
-#define ZXDH_DCBNL_GET_GSCHID_MSG(val,mask,shift)  ((val >> shift)&mask)
-
-enum zxdh_dcbnl_ets_trust {
-    ZXDH_DCBNL_ETS_TRUST_PCP  = 0,
-    ZXDH_DCBNL_ETS_TRUST_DSCP = 1,
-};
-
-enum zxdh_dcbnl_ets_tc_tsa {
-    ZXDH_DCBNL_VENDOR_TC     = 0,
-    ZXDH_DCBNL_STRICT_TC     = 1,
-    ZXDH_DCBNL_ETS_TC        = 2,
-    ZXDH_DCBNL_ZEROBW_ETS_TC = 3,
-};
-
-enum zxdh_dcbnl_ets_node_link_point {
-    ZXDH_DCBNL_ETS_NODE_NULL         = 0,
-    ZXDH_DCBNL_ETS_NODE_VENDOR_C     = 1,
-    ZXDH_DCBNL_ETS_NODE_STRICT_C     = 2,
-    ZXDH_DCBNL_ETS_NODE_ETS_C        = 3,
-    ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_C = 4,
-    ZXDH_DCBNL_ETS_NODE_VENDOR_E     = 5,
-    ZXDH_DCBNL_ETS_NODE_STRICT_E     = 6,
-    ZXDH_DCBNL_ETS_NODE_ETS_E        = 7,
-    ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_E = 8,
-};
-
-enum zxdh_dcbnl_se_flow_node_type {
-    ZXDH_DCBNL_ETS_NODE_FQ   = 0,
-    ZXDH_DCBNL_ETS_NODE_FQ2  = 1,
-    ZXDH_DCBNL_ETS_NODE_FQ4  = 2,
-    ZXDH_DCBNL_ETS_NODE_FQ8  = 3,
-    ZXDH_DCBNL_ETS_NODE_SP   = 4,
-    ZXDH_DCBNL_ETS_NODE_WFQ  = 5,
-    ZXDH_DCBNL_ETS_NODE_WFQ2 = 6,
-    ZXDH_DCBNL_ETS_NODE_WFQ4 = 7,
-    ZXDH_DCBNL_ETS_NODE_WFQ8 = 8,
-    ZXDH_DCBNL_ETS_NODE_FLOW = 9,
-};
-
-enum zxdh_tm_trpg_speed{
-    ZXDH_TRPG_SPEED_50G   = 0,
-    ZXDH_TRPG_SPEED_100G  = 1,
-    ZXDH_TRPG_SPEED_200G  = 2,
-    ZXDH_TRPG_SPEED_RDMA_400G = 3,
-    ZXDH_TRPG_DEFAULT = 4,
-
-    ZXDH_TRPG_SPEED_NUM,
-
-};
-struct zxdh_dcbnl_ets_se_node{
-    struct zxdh_dcbnl_ets_se_node *se_next;
-    uint64_t  gsch_id;
-    uint32_t  node_idx;
-    uint32_t  node_type;
-    uint32_t  se_id;
-    uint32_t  se_link_id;
-    uint32_t  se_link_weight;
-    uint32_t  se_link_sp;
-    uint32_t  link_point;
-};
-
-struct zxdh_dcbnl_ets_flow_node{
-    struct zxdh_dcbnl_ets_flow_node *flow_next;
-    uint64_t  gsch_id;
-    uint32_t  flow_id;
-    uint32_t  tc_id;
-    uint32_t  tc_type;
-    uint32_t  tc_tx_bw;
-    uint32_t  td_th;
-    uint32_t  c_linkid;
-    uint32_t  c_weight;
-    uint32_t  c_sp;
-    uint32_t  c_rate;
-    uint32_t  mode;
-    uint32_t  e_linkid;
-    uint32_t  e_weight;
-    uint32_t  e_sp;
-    uint32_t  e_rate;
-};
-
-struct zxdh_dcbnl_ets_node_list_head{
-    struct zxdh_dcbnl_ets_se_node *se_next;
-    struct zxdh_dcbnl_ets_flow_node *flow_next;
-    uint32_t node_num;
-};
-
-struct zxdh_dcbnl_ets_se_flow_resource{
-    uint32_t  numq;
-    uint32_t  level;
-    uint32_t  flags;
-    uint32_t  resource_id;
-    uint64_t  gsch_id;
-};
-
-struct zxdh_dcbnl_se_tree_config{
-    uint32_t  level;
-    uint32_t  idx;
-    uint32_t  type;
-    uint32_t  link_level;
-    uint32_t  link_idx;
-    uint32_t  link_weight;
-    uint32_t  link_sp;
-    uint32_t  link_point;
-};
-
-struct zxdh_dcbnl_tc_flow_config{
-    uint32_t  link_level;
-    uint32_t  tc_type;
-    uint32_t  tc_tx_bw;
-    uint32_t  c_rate;
-    uint32_t  e_rate;
-    uint32_t  td_th;
-};
-
-struct zxdh_dcbnl_tc_flow_shape_para{
-    uint32_t  cir;
-    uint32_t  cbs;
-    uint32_t  db_en;
-    uint32_t  eir;
-    uint32_t  ebs;
-};
-
-struct zxdh_dcbnl_ieee_ets {
-    uint8_t    willing;
-    uint8_t    ets_cap;
-    uint8_t    cbs;
-    uint8_t    tc_tx_bw[ZXDH_DCBNL_MAX_TRAFFIC_CLASS];
-    uint8_t    tc_tsa[ZXDH_DCBNL_MAX_TRAFFIC_CLASS];
-    uint8_t    prio_tc[ZXDH_DCBNL_MAX_PRIORITY];
-};
-
-struct zxdh_dcbnl_cee_ets {
-    uint8_t    tc_tx_bw[ZXDH_DCBNL_MAX_TRAFFIC_CLASS];
-    uint8_t    tc_tsa[ZXDH_DCBNL_MAX_TRAFFIC_CLASS];
-    uint8_t    prio_tc[ZXDH_DCBNL_MAX_PRIORITY];
-};
-
-struct zxdh_dcbnl_para {
-    uint32_t   init_flag;
-    uint32_t   trust;
-    uint32_t   dscp_app_num;
-    uint8_t    dscp2prio[ZXDH_DCBNL_MAX_DSCP];
-    uint64_t   tc_maxrate[ZXDH_DCBNL_MAX_TRAFFIC_CLASS];
-    struct zxdh_dcbnl_ieee_ets ets_cfg;
-    struct zxdh_dcbnl_cee_ets  cee_ets_cfg;
-    struct zxdh_dcbnl_ets_node_list_head ets_node_list_head[ZXDH_DCBNL_MAX_TREE_LEVEL];
-};
-
-uint32_t zxdh_dcbnl_initialize(struct net_device *netdev);
-uint32_t zxdh_dcbnl_ets_uninit(struct net_device *netdev);
-uint32_t zxdh_dcbnl_set_tm_pport_mcode_gate_open(struct net_device *netdev);
-uint32_t zxdh_dcbnl_set_tm_pport_mcode_gate_close(struct net_device *netdev);
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef __ZXDH_EN_DCBNL_H__
+#define __ZXDH_EN_DCBNL_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/device.h>
+
+/* 启用dcb会大幅度增加初始化时间，暂时先注释 */
+//#define ZXDH_DCBNL_OPEN
+
+#define ZXDH_DCBNL_INIT_FLAG (0x5a5a5a5a)
+#define ZXDH_DCBNL_NULL_ID (0xffffffff)
+
+#define ZXDH_DCBNL_MAX_PRIORITY (8)
+#define ZXDH_DCBNL_MAX_TRAFFIC_CLASS (8)
+
+#define ZXDH_DCBNL_MAX_DSCP (64)
+
+#define ZXDH_DCBNL_MAX_BW_ALLOC (100)
+#define ZXDH_DCBNL_MAX_WEIGHT (512)
+
+#define ZXDH_DCBNL_RATEUNIT_K (1000)
+#define ZXDH_DCBNL_RATEUNIT_M (1000000)
+#define ZXDH_DCBNL_RATEUNIT_G (1000000000)
+#define ZXDH_DCBNL_MAXRATE_KBITPS (400 * 1000000)
+#define ZXDH_DCBNL_MINRATE_KBITPS (64)
+
+#define ZXDH_DCBNL_FLOW_RATE_CBS (1000)
+#define ZXDH_DCBNL_FLOW_RATE_EBS (2000)
+#define ZXDH_DCBNL_PORT_RATE_CBS (1000)
+
+#define ZXDH_DCBNL_CEE_STATE_UP (1)
+
+#define ZXDH_DCBNL_MAX_SE_NODE_NUM (12)
+#define ZXDH_DCBNL_MAX_TREE_LEVEL (7)
+#define ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL (4)
+#define ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL (0)
+
+#define ZXDH_DCBNL_GSCHID_ID_MASK (0xFFFF)
+#define ZXDH_DCBNL_GSCHID_ID_SHIFT (0)
+
+#define ZXDH_DCBNL_GET_GSCHID_MSG(val, mask, shift) ((val >> shift) & mask)
+
+enum zxdh_dcbnl_ets_trust {
+	ZXDH_DCBNL_ETS_TRUST_PCP = 0,
+	ZXDH_DCBNL_ETS_TRUST_DSCP = 1,
+};
+
+enum zxdh_dcbnl_ets_tc_tsa {
+	ZXDH_DCBNL_VENDOR_TC = 0,
+	ZXDH_DCBNL_STRICT_TC = 1,
+	ZXDH_DCBNL_ETS_TC = 2,
+	ZXDH_DCBNL_ZEROBW_ETS_TC = 3,
+};
+
+enum zxdh_dcbnl_ets_node_link_point {
+	ZXDH_DCBNL_ETS_NODE_NULL = 0,
+	ZXDH_DCBNL_ETS_NODE_VENDOR_C = 1,
+	ZXDH_DCBNL_ETS_NODE_STRICT_C = 2,
+	ZXDH_DCBNL_ETS_NODE_ETS_C = 3,
+	ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_C = 4,
+	ZXDH_DCBNL_ETS_NODE_VENDOR_E = 5,
+	ZXDH_DCBNL_ETS_NODE_STRICT_E = 6,
+	ZXDH_DCBNL_ETS_NODE_ETS_E = 7,
+	ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_E = 8,
+};
+
+enum zxdh_dcbnl_se_flow_node_type {
+	ZXDH_DCBNL_ETS_NODE_FQ = 0,
+	ZXDH_DCBNL_ETS_NODE_FQ2 = 1,
+	ZXDH_DCBNL_ETS_NODE_FQ4 = 2,
+	ZXDH_DCBNL_ETS_NODE_FQ8 = 3,
+	ZXDH_DCBNL_ETS_NODE_SP = 4,
+	ZXDH_DCBNL_ETS_NODE_WFQ = 5,
+	ZXDH_DCBNL_ETS_NODE_WFQ2 = 6,
+	ZXDH_DCBNL_ETS_NODE_WFQ4 = 7,
+	ZXDH_DCBNL_ETS_NODE_WFQ8 = 8,
+	ZXDH_DCBNL_ETS_NODE_FLOW = 9,
+};
+
+enum zxdh_tm_trpg_speed {
+	ZXDH_TRPG_SPEED_50G = 0,
+	ZXDH_TRPG_SPEED_100G = 1,
+	ZXDH_TRPG_SPEED_200G = 2,
+	ZXDH_TRPG_SPEED_RDMA_400G = 3,
+	ZXDH_TRPG_DEFAULT = 4,
+
+	ZXDH_TRPG_SPEED_NUM,
+
+};
+struct zxdh_dcbnl_ets_se_node {
+	struct zxdh_dcbnl_ets_se_node *se_next;
+	uint64_t gsch_id;
+	uint32_t node_idx;
+	uint32_t node_type;
+	uint32_t se_id;
+	uint32_t se_link_id;
+	uint32_t se_link_weight;
+	uint32_t se_link_sp;
+	uint32_t link_point;
+};
+
+struct zxdh_dcbnl_ets_flow_node {
+	struct zxdh_dcbnl_ets_flow_node *flow_next;
+	uint64_t gsch_id;
+	uint32_t flow_id;
+	uint32_t tc_id;
+	uint32_t tc_type;
+	uint32_t tc_tx_bw;
+	uint32_t td_th;
+	uint32_t c_linkid;
+	uint32_t c_weight;
+	uint32_t c_sp;
+	uint32_t c_rate;
+	uint32_t mode;
+	uint32_t e_linkid;
+	uint32_t e_weight;
+	uint32_t e_sp;
+	uint32_t e_rate;
+};
+
+struct zxdh_dcbnl_ets_node_list_head {
+	struct zxdh_dcbnl_ets_se_node *se_next;
+	struct zxdh_dcbnl_ets_flow_node *flow_next;
+	uint32_t node_num;
+};
+
+struct zxdh_dcbnl_ets_se_flow_resource {
+	uint32_t numq;
+	uint32_t level;
+	uint32_t flags;
+	uint32_t resource_id;
+	uint64_t gsch_id;
+};
+
+struct zxdh_dcbnl_se_tree_config {
+	uint32_t level;
+	uint32_t idx;
+	uint32_t type;
+	uint32_t link_level;
+	uint32_t link_idx;
+	uint32_t link_weight;
+	uint32_t link_sp;
+	uint32_t link_point;
+};
+
+struct zxdh_dcbnl_tc_flow_config {
+	uint32_t link_level;
+	uint32_t tc_type;
+	uint32_t tc_tx_bw;
+	uint32_t c_rate;
+	uint32_t e_rate;
+	uint32_t td_th;
+};
+
+struct zxdh_dcbnl_tc_flow_shape_para {
+	uint32_t cir;
+	uint32_t cbs;
+	uint32_t db_en;
+	uint32_t eir;
+	uint32_t ebs;
+};
+
+struct zxdh_dcbnl_ieee_ets {
+	uint8_t willing;
+	uint8_t ets_cap;
+	uint8_t cbs;
+	uint8_t tc_tx_bw[ZXDH_DCBNL_MAX_TRAFFIC_CLASS];
+	uint8_t tc_tsa[ZXDH_DCBNL_MAX_TRAFFIC_CLASS];
+	uint8_t prio_tc[ZXDH_DCBNL_MAX_PRIORITY];
+};
+
+struct zxdh_dcbnl_cee_ets {
+	uint8_t tc_tx_bw[ZXDH_DCBNL_MAX_TRAFFIC_CLASS];
+	uint8_t tc_tsa[ZXDH_DCBNL_MAX_TRAFFIC_CLASS];
+	uint8_t prio_tc[ZXDH_DCBNL_MAX_PRIORITY];
+};
+
+struct zxdh_dcbnl_para {
+	uint32_t init_flag;
+	uint32_t trust;
+	uint32_t dscp_app_num;
+	uint8_t dscp2prio[ZXDH_DCBNL_MAX_DSCP];
+	uint64_t tc_maxrate[ZXDH_DCBNL_MAX_TRAFFIC_CLASS];
+	struct zxdh_dcbnl_ieee_ets ets_cfg;
+	struct zxdh_dcbnl_cee_ets cee_ets_cfg;
+	struct zxdh_dcbnl_ets_node_list_head
+			ets_node_list_head[ZXDH_DCBNL_MAX_TREE_LEVEL];
+};
+
+uint32_t zxdh_dcbnl_initialize(struct net_device *netdev);
+uint32_t zxdh_dcbnl_ets_uninit(struct net_device *netdev);
+uint32_t zxdh_dcbnl_set_tm_pport_mcode_gate_open(struct net_device *netdev);
+uint32_t zxdh_dcbnl_set_tm_pport_mcode_gate_close(struct net_device *netdev);
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl_api.c b/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl_api.c
index c65759c83f6331942ca9a3884a5299f8f3875806..061be5f8b7c706ca9bdd5f5fbc744006561ada34 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl_api.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl_api.c
@@ -1,1463 +1,1426 @@
-//#include <linux/device.h>
-#include "../../en_aux.h"
-#include "en_dcbnl.h"
-#include "en_dcbnl_api.h"
-#include "en_np/qos/include/dpp_drv_qos.h"
-#include "en_np/table/include/dpp_tbl_tm.h"
-#include "en_np/fc/include/dpp_drv_fc.h"
-#include "en_np/sdk/include/api/dpp_pbu_api.h"
-
-uint32_t zxdh_dcbnl_get_se_flow_resources(struct zxdh_en_device *en_dev,
-                                            struct zxdh_dcbnl_ets_se_flow_resource *tree_resource)
-{
-    uint64_t gsch_id = 0;
-    uint32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-    if (tree_resource->level == ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL)
-    {
-        err = dpp_sch_base_node_get(&pf_info, en_dev->phy_port, &gsch_id);
-    }
-    else
-    {
-        err = dpp_cosq_gsch_id_add(&pf_info, en_dev->phy_port, tree_resource->numq,
-                                   tree_resource->level, tree_resource->flags, &gsch_id);
-    }
-
-    if (err)
-    {
-        LOG_ERR("dcbnl_init_ets: get se/flow resources failed, level: %d, type: %d, err:%d \n",
-                tree_resource->level, tree_resource->flags, err);
-        return err;
-    }
-    tree_resource->gsch_id      = gsch_id;
-    tree_resource->resource_id = ZXDH_DCBNL_GET_GSCHID_MSG(gsch_id, ZXDH_DCBNL_GSCHID_ID_MASK, ZXDH_DCBNL_GSCHID_ID_SHIFT);
-    /* debug */
-    LOG_INFO(" gsch_id:0x%llx,resource_id:0x%x level:%d, flags:%d\n",
-            gsch_id, tree_resource->resource_id,tree_resource->level, tree_resource->flags);
-
-    return 0;
-}
-
-uint32_t zxdh_dcbnl_find_se_link_id(struct zxdh_en_priv *en_priv,
-                                      uint32_t level,
-                                      uint32_t link_level,
-                                      uint32_t link_idx,
-                                      uint32_t link_sp,
-                                      uint32_t *link_id)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_dcbnl_ets_se_node *se_link_node = NULL;
-    struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[link_level];
-
-    *link_id = ZXDH_DCBNL_NULL_ID;
-
-    if (level < ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL)
-    {
-        if (ets_node_list_head->se_next == NULL)
-        {
-            LOG_ERR("dcbnl: no nodes in the link_level: %d \n", link_level);
-            return 1;
-        }
-
-        se_link_node = ets_node_list_head->se_next;
-
-        while ((NULL != se_link_node) && (se_link_node->node_idx != link_idx))
-        {
-            se_link_node = se_link_node->se_next;
-        }
-
-        if (se_link_node != NULL)
-        {
-            *link_id = se_link_node->se_id + link_sp;
-        }
-        else
-        {
-            LOG_ERR("dcbnl: find se link_id failed, link_level: %d, link_idx: %d\n", link_level, link_idx);
-            return 1;
-        }
-    }
-
-    return 0;
-}
-
-uint32_t zxdh_dcbnl_save_se_resources(struct zxdh_en_priv *en_priv, struct zxdh_dcbnl_se_tree_config  *tree_node_cfg)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_dcbnl_ets_se_flow_resource tree_resource = {0};
-    struct zxdh_dcbnl_ets_se_node *new_se_node = NULL;
-    struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = NULL;
-    uint32_t level = 0;
-    uint32_t link_level = 0;
-    uint32_t link_idx = 0;
-    uint32_t link_id = 0;
-    uint32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    level = tree_node_cfg->level;
-    link_level = tree_node_cfg->link_level;
-    link_idx = tree_node_cfg->link_idx;
-
-    if ((level == 0) || (level > 4) || (link_level > 5) || (level >= link_level))
-    {
-        LOG_ERR("dcbnl_init_ets: configuration level error, level: %d, link_level: %d\n", level, link_level);
-        return 1;  //todo：考虑使用标准的错误定义
-    }
-
-    ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[level];
-
-    tree_resource.numq = 1;
-    tree_resource.level = level;
-    tree_resource.flags = tree_node_cfg->type;
-    err = zxdh_dcbnl_get_se_flow_resources(en_dev, &tree_resource);
-    if (err)
-    {
-        LOG_ERR("dcbnl_init_ets: get se resources failed, level: %d, idx: %d\n",
-                tree_resource.level, tree_node_cfg->idx);
-        return err;
-    }
-
-    err = zxdh_dcbnl_find_se_link_id(en_priv, level, link_level, link_idx, tree_node_cfg->link_sp, &link_id);
-    if (err)
-    {
-        LOG_ERR("dcbnl_init_ets: find se link_id failed, link_level: %d, link_idx: %d\n", link_level, link_idx);
-        return err;
-    }
-
-    new_se_node = kmalloc(sizeof(struct zxdh_dcbnl_ets_se_node), GFP_KERNEL);
-    if (NULL == new_se_node)
-    {
-        LOG_ERR("dcbnl_init_ets: kmalloc se node failed\n");
-        return 1;
-    }
-
-    new_se_node->se_next        = NULL;
-    new_se_node->gsch_id        = tree_resource.gsch_id;
-    new_se_node->node_idx       = tree_node_cfg->idx;
-    new_se_node->node_type      = tree_node_cfg->type;
-    new_se_node->se_id          = tree_resource.resource_id;
-    new_se_node->se_link_id     = link_id;
-    new_se_node->se_link_weight = tree_node_cfg->link_weight;
-    new_se_node->se_link_sp     = tree_node_cfg->link_sp;
-    new_se_node->link_point     = tree_node_cfg->link_point;
-
-    if (level < ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL)
-    {
-        err = dpp_crdt_se_link_set(&pf_info, new_se_node->se_id, new_se_node->se_link_id,
-                                   new_se_node->se_link_weight, new_se_node->se_link_sp);
-        if (err)
-        {
-            LOG_ERR("dcbnl_init_ets: dpp_crdt_se_link_set failed, level: %d, idx: %d, err:%d\n",
-                    level, tree_node_cfg->idx, err);
-            kfree(new_se_node);
-            return err;
-        }
-    }
-
-    new_se_node->se_next = ets_node_list_head->se_next;
-    ets_node_list_head->se_next = new_se_node;
-
-    ets_node_list_head->node_num += 1;
-
-    LOG_INFO(" level:%d, node_idx:%d, node_num:%d \n",
-             level, new_se_node->node_idx, ets_node_list_head->node_num);
-    return 0;
-}
-
-uint32_t zxdh_dcbnl_build_ets_scheduling_tree(struct zxdh_en_priv *en_priv)
-{
-    uint32_t i = 0;
-    uint32_t err = 0;
-
-    struct zxdh_dcbnl_se_tree_config ets_se_config_table[ZXDH_DCBNL_MAX_SE_NODE_NUM + 1] =
-    {
-    /*level idx     type               link_level link_idx link_weight link_sp  link_point*/
-        {4,  0, ZXDH_DCBNL_ETS_NODE_WFQ,    5,      0,          1,      0,        ZXDH_DCBNL_ETS_NODE_NULL},
-        {3,  0, ZXDH_DCBNL_ETS_NODE_FQ2,    4,      0,          1,      0,        ZXDH_DCBNL_ETS_NODE_NULL},
-        {2,  0, ZXDH_DCBNL_ETS_NODE_FQ4,    3,      0,          1,      0,        ZXDH_DCBNL_ETS_NODE_NULL},
-        {2,  1, ZXDH_DCBNL_ETS_NODE_FQ4,    3,      0,          1,      1,        ZXDH_DCBNL_ETS_NODE_NULL},
-        {1,  0, ZXDH_DCBNL_ETS_NODE_FQ,     2,      0,          1,      0,     ZXDH_DCBNL_ETS_NODE_VENDOR_C},
-        {1,  1, ZXDH_DCBNL_ETS_NODE_FQ8,    2,      0,          1,      1,     ZXDH_DCBNL_ETS_NODE_STRICT_C},
-        {1,  2, ZXDH_DCBNL_ETS_NODE_WFQ,    2,      0,          1,      2,        ZXDH_DCBNL_ETS_NODE_ETS_C},
-        {1,  3, ZXDH_DCBNL_ETS_NODE_WFQ,    2,      0,          1,      3, ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_C},
-        {1,  4, ZXDH_DCBNL_ETS_NODE_FQ,     2,      1,          1,      0,     ZXDH_DCBNL_ETS_NODE_VENDOR_E},
-        {1,  5, ZXDH_DCBNL_ETS_NODE_FQ8,    2,      1,          1,      1,     ZXDH_DCBNL_ETS_NODE_STRICT_E},
-        {1,  6, ZXDH_DCBNL_ETS_NODE_WFQ,    2,      1,          1,      2,        ZXDH_DCBNL_ETS_NODE_ETS_E},
-        {1,  7, ZXDH_DCBNL_ETS_NODE_WFQ,    2,      1,          1,      3, ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_E},
-        {0xff}
-    };
-
-    for (i = 0; i < ZXDH_DCBNL_MAX_SE_NODE_NUM && ets_se_config_table[i].level != 0xff; i++)
-    {
-        err = zxdh_dcbnl_save_se_resources(en_priv, &ets_se_config_table[i]);
-        if (err)
-        {
-            LOG_ERR("dcbnl_init_ets: build_tc_scheduling_tree failed, entry: %d\n", i);
-            return err;
-        }
-    }
-
-    return 0;
-}
-
-void zxdh_dcbnl_tc_map_to_link_point(uint32_t tc_type, uint32_t *c_type, uint32_t *e_type)
-{
-    switch (tc_type)
-    {
-        case ZXDH_DCBNL_VENDOR_TC:
-            *c_type = ZXDH_DCBNL_ETS_NODE_VENDOR_C;
-            *e_type = ZXDH_DCBNL_ETS_NODE_VENDOR_E;
-            break;
-
-        case ZXDH_DCBNL_STRICT_TC:
-            *c_type = ZXDH_DCBNL_ETS_NODE_STRICT_C;
-            *e_type = ZXDH_DCBNL_ETS_NODE_STRICT_E;
-            break;
-
-        case ZXDH_DCBNL_ETS_TC:
-            *c_type = ZXDH_DCBNL_ETS_NODE_ETS_C;
-            *e_type = ZXDH_DCBNL_ETS_NODE_ETS_E;
-            break;
-
-        case ZXDH_DCBNL_ZEROBW_ETS_TC:
-            *c_type = ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_C;
-            *e_type = ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_E;
-            break;
-        default:
-            break;
-    }
-}
-
-void zxdh_dcbnl_get_tc_weight_sp(uint32_t tc_type, uint32_t tc_tx_bw, uint32_t tc_id,
-                                           uint32_t *c_weight, uint32_t *e_weight,
-                                           uint32_t *c_sp, uint32_t *e_sp)
-{
-    if (tc_tx_bw == ZXDH_DCBNL_MAX_BW_ALLOC)
-    {
-        *c_weight = 1;
-        *e_weight = 1;
-    }
-    else
-    {
-        *c_weight = ZXDH_DCBNL_MAX_WEIGHT * tc_tx_bw / ZXDH_DCBNL_MAX_BW_ALLOC;
-        *e_weight = ZXDH_DCBNL_MAX_WEIGHT * tc_tx_bw / ZXDH_DCBNL_MAX_BW_ALLOC;
-    }
-
-    if ((tc_type == ZXDH_DCBNL_STRICT_TC) && (tc_id < ZXDH_DCBNL_MAX_TRAFFIC_CLASS))
-    {
-        *c_sp = ZXDH_DCBNL_MAX_TRAFFIC_CLASS - 1 - tc_id;
-        *e_sp = ZXDH_DCBNL_MAX_TRAFFIC_CLASS - 1 - tc_id;
-    }
-    else
-    {
-        *c_sp = 0;
-        *e_sp = 0;
-    }
-}
-
-uint32_t zxdh_dcbnl_find_flow_link_se_id(struct zxdh_en_priv *en_priv,
-                                         uint32_t  tc_type,  uint32_t link_level,
-                                         uint32_t *c_linkid, uint32_t *e_linkid,
-                                         uint32_t  c_sp,     uint32_t e_sp)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_dcbnl_ets_se_node *se_node = en_dev->dcb_para.ets_node_list_head[link_level].se_next;
-    uint32_t c_type = 0;
-    uint32_t e_type = 0;
-
-    if (NULL == se_node)
-    {
-        LOG_ERR("dcbnl: find_flow_link_se_id no nodes \n");
-        return 1;
-    }
-
-    zxdh_dcbnl_tc_map_to_link_point(tc_type, &c_type, &e_type);
-
-    *c_linkid = ZXDH_DCBNL_NULL_ID;
-    *e_linkid = ZXDH_DCBNL_NULL_ID;
-
-    while ((NULL != se_node) && ((ZXDH_DCBNL_NULL_ID == *c_linkid) || (ZXDH_DCBNL_NULL_ID == *e_linkid)))
-    {
-        if (se_node->link_point == c_type)
-        {
-            *c_linkid = se_node->se_id + c_sp;
-        }
-        else if (se_node->link_point == e_type)
-        {
-            *e_linkid = se_node->se_id + e_sp;
-        }
-
-        se_node = se_node->se_next;
-    }
-
-    if ((ZXDH_DCBNL_NULL_ID == *c_linkid) || (ZXDH_DCBNL_NULL_ID == *e_linkid))
-    {
-        LOG_ERR("dcbnl: find_flow_link_se_id failed, c_linkid: 0x%x, e_linkid: 0x%x\n", *c_linkid, *e_linkid);
-        return 1;
-    }
-    return 0;
-}
-
-uint32_t zxdh_dcbnl_get_ieee_tsa(uint32_t tc_type)
-{
-    uint32_t tsa = 0;
-    switch (tc_type)
-    {
-        case ZXDH_DCBNL_ETS_TC:
-        case ZXDH_DCBNL_ZEROBW_ETS_TC:
-            tsa = IEEE_8021QAZ_TSA_ETS;
-            break;
-        case ZXDH_DCBNL_STRICT_TC:
-            tsa = IEEE_8021QAZ_TSA_STRICT;
-            break;
-        case ZXDH_DCBNL_VENDOR_TC:
-            tsa = IEEE_8021QAZ_TSA_VENDOR;
-            break;
-        default:
-            tsa = IEEE_8021QAZ_TSA_STRICT;
-            LOG_ERR("dcbnl:tsa error, change to strict \n");
-            break;
-    }
-    return tsa;
-}
-
-uint32_t zxdh_dcbnl_save_flow_resources(struct zxdh_en_priv *en_priv,
-                                          struct zxdh_dcbnl_tc_flow_config *tc_flow_config,
-                                          struct zxdh_dcbnl_ets_se_flow_resource *tree_resource,
-                                          uint32_t tc_id)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_dcbnl_ets_flow_node *new_flow_node = NULL;
-    struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = NULL;
-    struct zxdh_dcbnl_tc_flow_shape_para p_para = {0};
-    uint32_t c_linkid = 0;
-    uint32_t e_linkid = 0;
-    uint32_t c_weight = 0;
-    uint32_t e_weight = 0;
-    uint32_t c_sp = 0;
-    uint32_t e_sp = 0;
-    uint32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (tc_flow_config->link_level != 1)
-    {
-         LOG_ERR("dcbnl_init_ets: zxdh_dcbnl_save_flow_resources link_level err\n");
-        return 1;
-    }
-
-    ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL];
-
-    if (tc_id == 0)
-    {
-        tree_resource->numq  = ZXDH_DCBNL_MAX_TRAFFIC_CLASS;
-        tree_resource->level = ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL;
-        tree_resource->flags = ZXDH_DCBNL_ETS_NODE_FLOW;
-        err = zxdh_dcbnl_get_se_flow_resources(en_dev, tree_resource);
-        if (err)
-        {
-            LOG_ERR("dcbnl_init_ets: get flow resources err\n");
-            return err;
-        }
-
-        err = dpp_tm_flowid_pport_table_set(&pf_info, en_dev->phy_port, tree_resource->resource_id);
-        if (err)
-        {
-            LOG_ERR("dcbnl_init_ets: flowid_pport_table_set failed, port: %d, flowid:%d, err:%d\n",
-                    en_dev->phy_port, tree_resource->resource_id, err);
-            return err;
-        }
-    }
-
-    zxdh_dcbnl_get_tc_weight_sp(tc_flow_config->tc_type, tc_flow_config->tc_tx_bw, tc_id, &c_weight, &e_weight, &c_sp, &e_sp);
-
-    err = zxdh_dcbnl_find_flow_link_se_id(en_priv, tc_flow_config->tc_type, tc_flow_config->link_level, &c_linkid, &e_linkid, c_sp, e_sp);
-    if (err)
-    {
-        LOG_ERR("dcbnl_init_ets init ets: find_flow_link_se_id failed, tc_id: %d, tc_type: %d\n",
-                tc_id, tc_flow_config->tc_type);
-        return err;
-    }
-
-    new_flow_node = kmalloc(sizeof(struct zxdh_dcbnl_ets_flow_node), GFP_KERNEL);
-    if (new_flow_node == NULL)
-    {
-        LOG_ERR("dcbnl_init_ets: kmalloc new flow node failed\n");
-        return 1;
-    }
-
-    new_flow_node->flow_next = NULL;
-    new_flow_node->gsch_id   = tree_resource->gsch_id + tc_id;
-    new_flow_node->flow_id   = tree_resource->resource_id + tc_id;
-    new_flow_node->tc_id     = tc_id;
-    new_flow_node->tc_type   = tc_flow_config->tc_type;
-    new_flow_node->tc_tx_bw  = tc_flow_config->tc_tx_bw;
-    new_flow_node->td_th     = tc_flow_config->td_th;
-    new_flow_node->c_linkid  = c_linkid;
-    new_flow_node->c_weight  = c_weight;
-    new_flow_node->c_sp      = c_sp;
-    new_flow_node->c_rate    = tc_flow_config->c_rate;
-    new_flow_node->mode      = 1;
-    new_flow_node->e_linkid  = e_linkid;
-    new_flow_node->e_weight  = e_weight;
-    new_flow_node->e_sp      = e_sp;
-    new_flow_node->e_rate    = tc_flow_config->e_rate;
-
-    err = dpp_flow_map_port_set(&pf_info, new_flow_node->flow_id, en_dev->phy_port);
-    if (err)
-    {
-        LOG_ERR("dcbnl_init_ets: dpp_flow_map_port_set failed, flow_id: %d, phy_port: %d, err:%d\n",
-                new_flow_node->flow_id, en_dev->phy_port, err);
-        kfree(new_flow_node);
-        return err;
-    }
-
-    err = dpp_crdt_flow_link_set(&pf_info, new_flow_node->flow_id, c_linkid, c_weight, c_sp,
-                                 new_flow_node->mode, e_linkid, e_weight, e_sp);
-    if (err)
-    {
-        LOG_ERR("dcbnl_init_ets: dpp_crdt_flow_link_set failed, flow_id: %d, c_linkid: %d, e_linkid: %d, err:%d\n",
-                new_flow_node->flow_id, c_linkid, e_linkid, err);
-        kfree(new_flow_node);
-        return err;
-    }
-
-    err = dpp_flow_td_th_set(&pf_info, new_flow_node->flow_id, new_flow_node->td_th);
-    if (err)
-    {
-        LOG_ERR("dcbnl_init_ets: dpp_flow_td_th_set failed,vport:%d flow_id: %d, td_th: %d, err:%d\n",
-                en_dev->vport, new_flow_node->flow_id, new_flow_node->td_th, err);
-        //kfree(new_flow_node);  //The default is 150
-        //return err;
-    }
-
-    p_para.cir   = new_flow_node->c_rate;
-    p_para.cbs   = ZXDH_DCBNL_FLOW_RATE_CBS;
-    p_para.db_en = 1;
-    p_para.eir   = new_flow_node->e_rate;
-    p_para.ebs   = ZXDH_DCBNL_FLOW_RATE_EBS;
-
-    err = dpp_flow_shape_set(&pf_info, new_flow_node->flow_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs);
-    if (err)
-    {
-        LOG_ERR("dcbnl_init_ets: dpp_flow_shape_set failed, vport: %d, flow_id: %d, tc_id: %d, e_rate: %d, err:%d\n",
-                en_dev->vport, new_flow_node->flow_id, new_flow_node->tc_id, new_flow_node->e_rate, err);
-    }
-    LOG_INFO("dcbnl_init_ets dpp_flow_shape_set end vport%d,phy_port:%d, flow_id:%d,tc_id:%d, cir:%d, cbs:%d, db_en:%d, eir:%d,ebs:%d,err:%d \n",
-            en_dev->vport,en_dev->phy_port, new_flow_node->flow_id,new_flow_node->tc_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs,err);
-
-    new_flow_node->flow_next = ets_node_list_head->flow_next;
-    ets_node_list_head->flow_next = new_flow_node;
-    ets_node_list_head->node_num += 1;
-
-    en_dev->dcb_para.ets_cfg.tc_tsa[tc_id] = zxdh_dcbnl_get_ieee_tsa(new_flow_node->tc_type);
-    en_dev->dcb_para.ets_cfg.tc_tx_bw[tc_id] = tc_flow_config->tc_tx_bw;
-    en_dev->dcb_para.tc_maxrate[tc_id] = new_flow_node->e_rate;
-
-    LOG_INFO(" level:%d, tc_id:%d, flow_id:%d, node_num:%d \n",
-             tree_resource->level, new_flow_node->tc_id, new_flow_node->flow_id, ets_node_list_head->node_num);
-
-    return 0;
-}
-
-uint32_t zxdh_dcbnl_scheduling_tree_link_tc(struct zxdh_en_priv *en_priv)
-{
-    struct zxdh_dcbnl_ets_se_flow_resource tree_resource;
-    uint32_t i = 0;
-    uint32_t err = 0;
-
-    struct zxdh_dcbnl_tc_flow_config ets_tc_config_table[ZXDH_DCBNL_MAX_TRAFFIC_CLASS+1] =
-    {
-    /*link_level  tc_type         tc_tx_bw  c_rate                           e_rate               td_th */
-        {1,  ZXDH_DCBNL_STRICT_TC,   100,   ZXDH_DCBNL_FLOW_RATE_CIR,  ZXDH_DCBNL_INITRATE_KBITPS,  ZXDH_DCBNL_FLOW_TDTH},
-        {1,  ZXDH_DCBNL_STRICT_TC,   100,   ZXDH_DCBNL_FLOW_RATE_CIR,  ZXDH_DCBNL_INITRATE_KBITPS,  ZXDH_DCBNL_FLOW_TDTH},
-        {1,  ZXDH_DCBNL_STRICT_TC,   100,   ZXDH_DCBNL_FLOW_RATE_CIR,  ZXDH_DCBNL_INITRATE_KBITPS,  ZXDH_DCBNL_FLOW_TDTH},
-        {1,  ZXDH_DCBNL_STRICT_TC,   100,   ZXDH_DCBNL_FLOW_RATE_CIR,  ZXDH_DCBNL_INITRATE_KBITPS,  ZXDH_DCBNL_FLOW_TDTH},
-        {1,  ZXDH_DCBNL_STRICT_TC,   100,   ZXDH_DCBNL_FLOW_RATE_CIR,  ZXDH_DCBNL_INITRATE_KBITPS,  ZXDH_DCBNL_FLOW_TDTH},
-        {1,  ZXDH_DCBNL_STRICT_TC,   100,   ZXDH_DCBNL_FLOW_RATE_CIR,  ZXDH_DCBNL_INITRATE_KBITPS,  ZXDH_DCBNL_FLOW_TDTH},
-        {1,  ZXDH_DCBNL_STRICT_TC,   100,   ZXDH_DCBNL_FLOW_RATE_CIR,  ZXDH_DCBNL_INITRATE_KBITPS,  ZXDH_DCBNL_FLOW_TDTH},
-        {1,  ZXDH_DCBNL_STRICT_TC,   100,   ZXDH_DCBNL_FLOW_RATE_CIR,  ZXDH_DCBNL_INITRATE_KBITPS,  ZXDH_DCBNL_FLOW_TDTH},
-        {0xff}
-    };
-
-    for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS && ets_tc_config_table[i].link_level != 0xff; i++)
-    {
-
-        err = zxdh_dcbnl_save_flow_resources(en_priv, &ets_tc_config_table[i], &tree_resource, i);
-        if (err)
-        {
-            LOG_ERR("dcbnl_init_ets: save_flow_resources failed, entry: %d\n", i);
-            return err;
-        }
-
-    }
-
-    return 0;
-}
-
-uint32_t zxdh_dcbnl_set_ets_trust(struct zxdh_en_priv *en_priv, uint32_t trust)
-{
-
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    err = dpp_tm_pport_trust_mode_table_set(&pf_info, en_dev->phy_port, trust);
-    if (err)
-    {
-        LOG_ERR("dcbnl_set_ets: set_ets_trust failed, vport: %d, trust: %d, err:%d\n", en_dev->vport, trust, err);
-        return err;
-    }
-    en_dev->dcb_para.trust = trust;
-    LOG_INFO(" trust:%d \n", trust);
-    return 0;
-}
-
-uint32_t zxdh_dcbnl_init_trust_and_table(struct zxdh_en_priv *en_priv)
-{
-
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t i = 0;
-    uint32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    for (i = 0; i < ZXDH_DCBNL_MAX_PRIORITY; i++)
-    {
-        err = dpp_tm_pport_up_map_table_set(&pf_info, en_dev->phy_port, i, i);  //初始时，配置一一对应
-        if (err)
-        {
-            LOG_ERR("dcbnl_init_ets: dpp_tm_pport_up_map_table_set failed, vport: %d, phy_port: %d, err:%d\n",
-                    en_dev->vport, en_dev->phy_port, err);
-            return err;
-        }
-        en_dev->dcb_para.ets_cfg.prio_tc[i] = i;
-    }
-    LOG_INFO(" vport:%d,phy_port:%d prio2tc ok \n", en_dev->vport, en_dev->phy_port);
-
-    for (i = 0; i < ZXDH_DCBNL_MAX_DSCP; i++)
-    {
-        err = dpp_tm_pport_dscp_map_table_set(&pf_info, en_dev->phy_port, i, i>>3);
-        if (err)
-        {
-            LOG_ERR("dcbnl_init_ets: dscp_map_table_set failed, vport: %d, phy_port: %d, err:%d\n",
-                    en_dev->vport, en_dev->phy_port, err);
-            return err;
-        }
-
-        en_dev->dcb_para.dscp2prio[i] = i>>3;
-    }
-    LOG_INFO("vport:%d,phy_port:%d,dscp2prio ok \n", en_dev->vport, en_dev->phy_port);
-
-    err = zxdh_dcbnl_set_ets_trust(en_priv, ZXDH_DCBNL_ETS_TRUST_PCP);
-    if (err)
-    {
-        LOG_INFO("set_ets_trust failed \n");
-        return err;
-    }
-    en_dev->dcb_para.trust = ZXDH_DCBNL_ETS_TRUST_PCP;
-    LOG_INFO(" vport:%d,phy_port:%d,trust:%d \n", en_dev->vport, en_dev->phy_port, en_dev->dcb_para.trust);
-    return 0;
-}
-
-uint32_t zxdh_dcbnl_init_ets_list(struct zxdh_en_priv *en_priv)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t level = 0;
-
-    for (level = 0; level < ZXDH_DCBNL_MAX_TREE_LEVEL; level++)
-    {
-        en_dev->dcb_para.ets_node_list_head[level].se_next = NULL;
-        en_dev->dcb_para.ets_node_list_head[level].flow_next = NULL;
-        en_dev->dcb_para.ets_node_list_head[level].node_num = 0;
-    }
-    return 0;
-}
-
-/* Normal release se*/
-uint32_t zxdh_dcbnl_free_se_resources(struct zxdh_en_priv *en_priv)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_dcbnl_ets_se_node *se_node = NULL;
-    struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = NULL;
-    uint32_t err = 0;
-    uint32_t level = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    LOG_INFO(" vport:%d, phy_port:%d \n",en_dev->vport, en_dev->phy_port);
-    for (level = 1; level <= ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL; level++)
-    {
-        ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[level];
-        while (NULL != ets_node_list_head->se_next)
-        {
-            se_node = ets_node_list_head->se_next;
-            ets_node_list_head->se_next = se_node->se_next;
-            if (level < ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL)
-            {
-                err = dpp_crdt_del_se_link_set(&pf_info, se_node->se_id, se_node->se_id);
-                if (err)
-                {
-                    LOG_ERR("dcbnl_free_ets: dpp_crdt_del_se_link_set failed, se_id: %d, err:%d \n", se_node->se_id, err);
-                }
-                LOG_INFO(" dpp_crdt_del_se_link_set");
-
-                err = dpp_cosq_gsch_id_delete(&pf_info, en_dev->phy_port, se_node->gsch_id);
-                if (err)
-                {
-                    LOG_ERR("dcbnl_free_ets: dpp_cosq_gsch_id_delete failed, se_id: %lld, err:%d \n", se_node->gsch_id, err);
-                }
-                LOG_INFO("del se id dpp_cosq_gsch_id_delete");
-            }
-            LOG_INFO(" free level:%d se_id:%x \n", level, se_node->se_id);
-            kfree(se_node);
-            ets_node_list_head->node_num -= 1;
-            LOG_INFO("current node_num:%d \n", ets_node_list_head->node_num);
-        }
-    }
-
-    return 0;
-}
-/* Normal release flow*/
-uint32_t zxdh_dcbnl_free_flow_resources(struct zxdh_en_priv *en_priv)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_dcbnl_ets_flow_node *flow_node = NULL;
-    struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL];
-    uint32_t err = 0;
-    bool have_flow = false;
-    DPP_PF_INFO_T pf_info = {0};
-    struct zxdh_dcbnl_tc_flow_shape_para p_para = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    LOG_INFO(" vport:%d, phy_port:%d \n",en_dev->vport, en_dev->phy_port);
-    while (NULL != ets_node_list_head->flow_next)
-    {
-        have_flow = true;
-        flow_node = ets_node_list_head->flow_next;
-        ets_node_list_head->flow_next = flow_node->flow_next;
-
-        p_para.cir   = 0;
-        p_para.cbs   = ZXDH_DCBNL_FLOW_RATE_CBS_REFRESH;
-        p_para.db_en = 0;
-        p_para.eir   = 0;
-        p_para.ebs   = ZXDH_DCBNL_FLOW_RATE_EBS_REFRESH;
-
-        err = dpp_flow_shape_set(&pf_info, flow_node->flow_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs);
-        if (err)
-        {
-            LOG_ERR("dcbnl_set_ets: dpp_flow_shape_set failed, vport: %d, flow_id: %d, tc_id: %d, eir: %d, err:%d\n",
-                    en_dev->vport, flow_node->flow_id, flow_node->tc_id, p_para.eir , err);
-            return err;
-        }
-        LOG_INFO("clean maxrate");
-        err = dpp_flow_td_th_set(&pf_info, flow_node->flow_id, 0);
-        if (err)
-        {
-            LOG_ERR("dcbnl_free_ets: dpp_flow_td_th_set failed,vport:%d flow_id: %d, td_th: 0, err:%d\n",
-                    en_dev->vport, flow_node->flow_id, err);
-        }
-        LOG_INFO(" clean TD ");
-
-        err = dpp_crdt_del_flow_link_set(&pf_info, flow_node->flow_id, flow_node->flow_id);
-        if (err)
-        {
-            LOG_ERR("dcbnl_free_ets: dpp_crdt_del_flow_link_set failed, flow_id: %d, err:%d \n", flow_node->flow_id, err);
-        }
-        LOG_INFO(" dpp_crdt_del_flow_link_set");
-
-        err = dpp_cosq_gsch_id_delete(&pf_info, en_dev->phy_port, flow_node->gsch_id);
-        if (err)
-        {
-            LOG_ERR("dcbnl_free_ets: dpp_cosq_gsch_id_delete failed, gsch_id: %lld ,err:%d\n", flow_node->gsch_id, err);
-        }
-        LOG_INFO("del id  dpp_cosq_gsch_id_delete");
-
-        LOG_INFO(" free level:0, flow_id:%d, tc:%d\n", flow_node->flow_id, flow_node->tc_id);
-
-        kfree(flow_node);
-        ets_node_list_head->node_num -= 1;
-        LOG_INFO("current node_num:%d \n", ets_node_list_head->node_num);
-    }
-
-    if (have_flow)
-    {
-        err = dpp_tm_flowid_pport_table_del(&pf_info, en_dev->phy_port);
-        if (err)
-        {
-        LOG_ERR("dcbnl_free_ets: dpp_tm_flowid_pport_table_del failed,vport:%d, phy_port: %d \n",
-                en_dev->vport, en_dev->phy_port);
-        }
-        LOG_INFO("del table dpp_tm_flowid_pport_table_del");
-    }
-
-    return 0;
-}
-
-/* host no reset，risc reset? */
-uint32_t zxdh_dcbnl_check_and_free_node_memory(struct zxdh_en_priv *en_priv)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_dcbnl_ets_flow_node *flow_node = NULL;
-    struct zxdh_dcbnl_ets_se_node *se_node = NULL;
-    struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = NULL;
-    uint32_t level = 0;
-
-    ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL];
-    while (NULL != ets_node_list_head->flow_next)
-    {
-        flow_node = ets_node_list_head->flow_next;
-        ets_node_list_head->flow_next = flow_node->flow_next;
-        kfree(flow_node);
-        ets_node_list_head->node_num -= 1;
-    }
-
-    for (level = 1; level < ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL + 1; level++)
-    {
-        ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[level];
-        while (NULL != ets_node_list_head->se_next)
-        {
-            se_node = ets_node_list_head->se_next;
-            ets_node_list_head->se_next = se_node->se_next;
-            kfree(se_node);
-            ets_node_list_head->node_num -= 1;
-        }
-    }
-
-    return 0;
-}
-
-uint32_t zxdh_dcbnl_set_tc_scheduling(struct zxdh_en_priv *en_priv, uint8_t *tc_type, uint8_t *tc_tx_bw)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_dcbnl_ets_flow_node *flow_node = en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL].flow_next;
-    uint32_t tc_id = 0;
-    uint32_t c_linkid = 0;
-    uint32_t e_linkid = 0;
-    uint32_t c_weight = 0;
-    uint32_t e_weight = 0;
-    uint32_t c_sp = 0;
-    uint32_t e_sp = 0;
-    uint32_t i = 0;
-    uint32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-    struct zxdh_dcbnl_tc_flow_shape_para p_para = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (NULL == flow_node)
-    {
-        LOG_ERR("dcbnl_set_ets: set_tc_scheduling no flow in the tree\n");
-        return 1;
-    }
-
-    for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS && flow_node != NULL; i++)
-    {
-        tc_id = flow_node->tc_id;
-        if ((flow_node->tc_type == tc_type[tc_id]) && (flow_node->tc_tx_bw == tc_tx_bw[tc_id]))
-        {
-            LOG_INFO("Same configuration,tc_id:%d, tc_type:%d, tc_tx_bw:%d\n",tc_id, tc_type[tc_id], tc_tx_bw[tc_id]);
-            flow_node = flow_node->flow_next;
-            continue;
-        }
-
-        zxdh_dcbnl_get_tc_weight_sp(tc_type[tc_id], tc_tx_bw[tc_id], tc_id, &c_weight, &e_weight, &c_sp, &e_sp);
-
-        err = zxdh_dcbnl_find_flow_link_se_id(en_priv, tc_type[tc_id], 1, &c_linkid, &e_linkid, c_sp, e_sp);
-        if (err)
-        {
-            LOG_ERR("dcbnl_set_ets: find_flow_link_se_id failed, tc_id: %d, tc_type: %d\n", tc_id, tc_type[tc_id]);
-            return err;
-        }
-
-        /* 1、清限速,刷新桶深,断流*/
-        p_para.cir   = 0;
-        p_para.cbs   = ZXDH_DCBNL_FLOW_RATE_CBS_REFRESH;
-        p_para.db_en = 0;
-        p_para.eir   = 0;
-        p_para.ebs   = ZXDH_DCBNL_FLOW_RATE_EBS_REFRESH;
-
-        LOG_INFO("clean maxrate vport%d,phy_port:%d, flow_id:%d,tc_id:%d, cir:%d, cbs:%d, db_en:%d, eir:%d,ebs:%d \n",
-            en_dev->vport,en_dev->phy_port, flow_node->flow_id, tc_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs);
-
-        err = dpp_flow_shape_set(&pf_info, flow_node->flow_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs);
-        if (err)
-        {
-            LOG_ERR("dcbnl_set_ets: dpp_flow_shape_set failed, vport: %d, flow_id: %d, tc_id: %d, eir: %d, err:%d\n",
-                    en_dev->vport, flow_node->flow_id, tc_id, p_para.eir , err);
-            return err;
-        }
-
-        /* 2、清TD,断流*/
-        err = dpp_flow_td_th_set(&pf_info, flow_node->flow_id, 0);
-        if (err)
-        {
-            LOG_ERR("dcbnl_set_ets: dpp_flow_td_th_set failed,vport:%d flow_id: %d, td_th: 0, err:%d\n",
-                    en_dev->vport, flow_node->flow_id, err);
-        }
-
-        /* 3、删除挂接*/
-        err = dpp_crdt_del_flow_link_set(&pf_info, flow_node->flow_id, flow_node->flow_id);
-        if (err)
-        {
-            LOG_ERR("dcbnl_set_ets: dpp_crdt_del_flow_link_set failed, vport: %d, flow_id: %d, err:%d\n",
-                    en_dev->vport, flow_node->flow_id, err);
-            return err;
-        }
-
-        /* 4、重新挂接*/
-        err = dpp_crdt_flow_link_set(&pf_info, flow_node->flow_id, c_linkid, c_weight, c_sp, 1,
-                                     e_linkid, e_weight, e_sp);
-        if (err)
-        {
-            LOG_ERR("dcbnl_set_ets: dpp_crdt_flow_link_set failed, flow_id: %d, flow_id: %d, flow_id: %d, err:%d\n",
-                    flow_node->flow_id, c_linkid, e_linkid, err);
-            return err;
-        }
-
-        /* 5、恢复TD*/
-        err = dpp_flow_td_th_set(&pf_info, flow_node->flow_id, flow_node->td_th);
-        if (err)
-        {
-            LOG_ERR("dcbnl_set_ets: dpp_flow_td_th_set failed,vport:%d flow_id: %d, td_th:%d, err:%d\n",
-                    en_dev->vport, flow_node->flow_id, flow_node->td_th, err);
-        }
-
-        /* 6、恢复限速*/
-        p_para.cir   = ZXDH_DCBNL_FLOW_RATE_CIR;
-        p_para.cbs   = ZXDH_DCBNL_FLOW_RATE_CBS;
-        p_para.db_en = 1;
-        p_para.eir   = flow_node->e_rate;
-        p_para.ebs   = ZXDH_DCBNL_FLOW_RATE_EBS;
-
-        LOG_INFO("dpp_flow_shape_set begin vport%d,phy_port:%d, flow_id:%d,tc_id:%d, cir:%d, cbs:%d, db_en:%d, eir:%d,ebs:%d \n",
-            en_dev->vport,en_dev->phy_port, flow_node->flow_id, tc_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs);
-
-        err = dpp_flow_shape_set(&pf_info, flow_node->flow_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs);
-        if (err)
-        {
-            LOG_ERR("dcbnl_set_ets: dpp_flow_shape_set failed, vport: %d, flow_id: %d, tc_id: %d, eir: %d, err:%d\n",
-                    en_dev->vport, flow_node->flow_id, tc_id, p_para.eir , err);
-            return err;
-        }
-        LOG_INFO(" dpp_flow_shape_set end");
-        flow_node->tc_type  = tc_type[tc_id];
-        flow_node->tc_tx_bw = tc_tx_bw[tc_id];
-
-        flow_node->c_linkid = c_linkid;
-        flow_node->c_weight = c_weight;
-        flow_node->c_sp     = c_sp;
-
-        flow_node->e_linkid = e_linkid;
-        flow_node->e_weight = e_weight;
-        flow_node->e_sp     = e_sp;
-
-        LOG_INFO(" tc_id:%d, tc_type:%d, c_linkid:%x, e_weight:%d, e_sp:%d ,e_linkid:%x, e_weight:%d, e_sp:%d \n",
-                 tc_id, flow_node->tc_type, flow_node->c_linkid,flow_node->c_weight, flow_node->c_sp, flow_node->e_linkid, flow_node->e_weight, flow_node->e_sp);
-
-        flow_node = flow_node->flow_next;
-    }
-
-    return 0;
-}
-
-uint32_t zxdh_dcbnl_set_ets_up_tc_map(struct zxdh_en_priv *en_priv, uint8_t *prio_tc)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t i = 0;
-    uint32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    LOG_INFO(" begin \n");
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    for (i = 0; i < ZXDH_DCBNL_MAX_PRIORITY; i++)
-    {
-        err = dpp_tm_pport_up_map_table_set(&pf_info, en_dev->phy_port, i, prio_tc[i]);
-        if (err)
-        {
-            LOG_ERR("dcbnl_set_ets:  failed, vport: %d, prio: %d, tc: %d, err:%d\n",
-                    en_dev->vport, i, prio_tc[i], err);
-            return err;
-        }
-        LOG_INFO(" vport:%d, phy_port:%d, prio:%d, tc:%d \n",en_dev->vport, en_dev->phy_port, i, prio_tc[i]);
-    }
-     return 0;
-}
-
-uint32_t zxdh_dcbnl_set_tc_maxrate(struct zxdh_en_priv *en_priv, uint32_t *maxrate)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_dcbnl_ets_flow_node *flow_node = en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL].flow_next;
-    struct zxdh_dcbnl_tc_flow_shape_para p_para = {0};
-    uint32_t tc_id = 0;
-    uint32_t i = 0;
-    uint32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (NULL == flow_node)
-    {
-        LOG_ERR("dcbnl_set_ets: set_tc_maxrate no flow in the tree\n");
-        return 1;
-    }
-
-    for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS && flow_node != NULL; i++)
-    {
-        tc_id = flow_node->tc_id;
-        if (flow_node->e_rate == maxrate[tc_id])
-        {
-            LOG_INFO("Same configuration, tc_id:%d, maxrate:%d\n", tc_id, maxrate[tc_id]);
-            flow_node = flow_node->flow_next;
-            continue;
-        }
-        /* clean CBS、EBS*/
-        p_para.cir   = 0;
-        p_para.cbs   = ZXDH_DCBNL_FLOW_RATE_CBS_REFRESH;
-        p_para.db_en = 0;
-        p_para.eir   = 0;
-        p_para.ebs   = ZXDH_DCBNL_FLOW_RATE_EBS_REFRESH;
-        LOG_INFO(" refresh maxrate ");
-        err = dpp_flow_shape_set(&pf_info, flow_node->flow_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs);
-        if (err)
-        {
-            LOG_ERR("dcbnl_set_ets: dpp_flow_shape_set failed, vport: %d, flow_id: %d, tc_id: %d, eir: %d, err:%d\n",
-                    en_dev->vport, flow_node->flow_id, tc_id, p_para.eir, err);
-            return err;
-        }
-        /* 2、set maxrate*/
-        p_para.cir   = ZXDH_DCBNL_FLOW_RATE_CIR;
-        p_para.cbs   = ZXDH_DCBNL_FLOW_RATE_CBS;
-        p_para.db_en = 1;
-        p_para.eir   = maxrate[tc_id];
-        p_para.ebs   = ZXDH_DCBNL_FLOW_RATE_EBS;
-
-        LOG_INFO(" vport%d,phy_port:%d, flow_id:%d,tc_id:%d, cir:%d, cbs:%d, db_en:%d, eir:%d,ebs:%d \n",
-            en_dev->vport,en_dev->phy_port, flow_node->flow_id, tc_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs);
-
-        err = dpp_flow_shape_set(&pf_info, flow_node->flow_id, p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs);
-        if (err)
-        {
-            LOG_ERR("dcbnl_set_ets: dpp_flow_shape_set failed, vport: %d, flow_id: %d, tc_id: %d, eir: %d, err:%d\n",
-                    en_dev->vport, flow_node->flow_id, tc_id, p_para.eir, err);
-            return err;
-        }
-
-        flow_node->e_rate = maxrate[tc_id];
-        en_dev->dcb_para.tc_maxrate[tc_id] = maxrate[tc_id];
-
-        flow_node = flow_node->flow_next;
-
-    }
-
-    return 0;
-}
-
-uint32_t zxdh_dcbnl_set_dscp2prio(struct zxdh_en_priv *en_priv, uint16_t dscp, uint8_t prio)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    err = dpp_tm_pport_dscp_map_table_set(&pf_info, en_dev->phy_port, dscp, prio);
-    if (err)
-    {
-        LOG_ERR("dcbnl_set_ets: set_dscp2prio failed, vport: %d, dscp: %d, prio: %d, err:%d\n", en_dev->vport, dscp, prio, err);
-        return err;
-    }
-    en_dev->dcb_para.dscp2prio[dscp] = prio;
-    LOG_INFO(" vport:%d, ephy_port:%d,dscp:%d, up:%d \n",en_dev->vport, en_dev->phy_port,dscp, prio);
-
-     return 0;
-}
-
-uint32_t zxdh_dcbnl_set_flow_td_th(struct zxdh_en_priv *en_priv, uint32_t* tc_td_th)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_dcbnl_ets_flow_node *flow_node = en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL].flow_next;
-    uint32_t err = 0;
-    uint32_t i = 0;
-    uint32_t tc_id = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (flow_node == NULL)
-    {
-        LOG_ERR("dcbnl_set_ets: set_flow_td_th no flow in the tree\n");
-        return 1;
-    }
-
-    if (tc_td_th == NULL)
-    {
-        LOG_ERR("dcbnl_set_ets: tc_td_th is null \n");
-        return 1;
-    }
-
-    for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS && flow_node != NULL; i++)
-    {
-        tc_id = flow_node->tc_id;
-        err = dpp_flow_td_th_set(&pf_info, flow_node->flow_id, tc_td_th[tc_id]);
-        if (err)
-        {
-            LOG_ERR("dcbnl_set_ets: set_flow_td_th failed, vport: %d, flow_id:%d, tc_id:%d, td_th: %d, err:%d\n",
-                    en_dev->vport, flow_node->flow_id, tc_id, tc_td_th[tc_id], err);
-            return err;
-        }
-        flow_node->td_th = tc_td_th[tc_id];
-        flow_node = flow_node->flow_next;
-    }
-
-    return 0;
-}
-
-uint32_t zxdh_dcbnl_get_flow_td_th(struct zxdh_en_priv *en_priv, uint32_t* tc_td_th)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_dcbnl_ets_flow_node *flow_node = en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL].flow_next;
-    uint32_t err = 0;
-    uint32_t i = 0;
-    uint32_t tc_id = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (flow_node == NULL)
-    {
-        LOG_ERR("get_flow_td_th no flow in the tree\n");
-        return 1;
-    }
-
-    if (tc_td_th == NULL)
-    {
-        LOG_ERR(" tc_td_th is null \n");
-        return 1;
-    }
-
-    for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS && flow_node != NULL; i++)
-    {
-        tc_id = flow_node->tc_id;
-        err = dpp_flow_td_th_get(&pf_info, flow_node->flow_id, &tc_td_th[tc_id]);
-        if (err)
-        {
-            LOG_ERR("get_flow_td_th failed, vport: %d, flow_id:%d, tc_id:%d, err:%d\n",
-                    en_dev->vport, flow_node->flow_id, tc_id, err);
-            return err;
-        }
-        flow_node = flow_node->flow_next;
-    }
-
-    return 0;
-}
-
-uint32_t zxdh_dcbnl_init_port_speed(struct zxdh_en_priv *en_priv)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_dcbnl_tc_flow_shape_para p_para = {0};
-    uint32_t err = 0;
-    uint32_t speed = 0;
-    uint32_t max_speed = ZXDH_DCBNL_MAXRATE_KBITPS / ZXDH_DCBNL_RATEUNIT_K;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    speed = en_dev->speed;
-    if ((0 == speed) || (speed > max_speed))
-    {
-        LOG_INFO("get port speed is : %u ,set to max:%u\n",speed, max_speed);
-        speed = max_speed;
-    }
-
-    p_para.cir   = speed * ZXDH_DCBNL_RATEUNIT_K;  //Mbps->Kbps
-    p_para.cbs   = ZXDH_DCBNL_PORT_RATE_CBS;
-    p_para.db_en = 0;
-    p_para.eir   = 0;
-    p_para.ebs   = 0;
-
-    LOG_INFO(" vport:%d,phy_port:%d, p_para.cir:%d, speed:%d \n",
-             en_dev->vport, en_dev->phy_port, p_para.cir, speed);
-
-    err = dpp_port_shape_set(&pf_info, en_dev->phy_port, p_para.cir, p_para.cbs, 1);
-    if (err)
-    {
-        LOG_ERR("dcbnl_set_ets: dpp_port_shape_set failed, port:%d, speed:%d, speed:%d,err:%d \n",
-                en_dev->phy_port, speed, p_para.cir, err);
-        return err;
-    }
-
-    return 0;
-}
-
-uint32_t zxdh_dcbnl_printk_ets_tree(struct zxdh_en_priv *en_priv)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_dcbnl_ets_flow_node *flow_node = NULL;
-    struct zxdh_dcbnl_ets_se_node *se_node = NULL;
-    struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = NULL;
-    uint32_t level = 0;
-
-    LOG_INFO(" ***vport:%d port:%d \n", en_dev->vport,en_dev->phy_port);
-
-    for (level = ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL; level > 0; level--)
-    {
-        ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[level];
-        se_node = ets_node_list_head->se_next;
-        while (NULL != se_node)
-        {
-            LOG_INFO(" se_node *** level:%d, node_idx:%d, se_id:0x%x *** \n",
-                    level, se_node->node_idx, se_node->se_id);
-            LOG_INFO(" se_node gsch_id:0x%llx, node_type:%d, se_id:0x%x \n",
-                    se_node->gsch_id, se_node->node_type, se_node->se_id);
-            LOG_INFO(" se_node se_link_id:0x%x, se_link_weight:%d, se_link_sp:%d, link_point:%d \n",
-                    se_node->se_link_id, se_node->se_link_weight, se_node->se_link_sp, se_node->link_point);
-            se_node = se_node->se_next;
-        }
-    }
-
-    ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL];
-    flow_node = ets_node_list_head->flow_next;
-    while (NULL != flow_node)
-    {
-        LOG_INFO(" flow_node *** tc_id:%d, flow_id:%d *** \n",
-                flow_node->tc_id, flow_node->flow_id);
-        LOG_INFO(" flow_node gsch_id:0x%llx,  tc_type:%d, td_th:%d \n",
-                flow_node->gsch_id, flow_node->tc_type, flow_node->td_th);
-        LOG_INFO(" flow_node c_linkid:0x%x, c_weight:%d, c_sp:%d, c_rate:%d \n",
-                flow_node->c_linkid, flow_node->c_weight,flow_node->c_sp,flow_node->c_rate);
-        LOG_INFO(" flow_node e_linkid:0x%x, e_weight:%d, e_sp:%d, e_rate:%d \n",
-                flow_node->e_linkid, flow_node->e_weight, flow_node->e_sp, flow_node->e_rate);
-        flow_node = flow_node->flow_next;
-    }
-
-    return 0;
-}
-
-uint32_t zxdh_link_speed_to_index(uint32_t link_speed)
-{
-    //50G以下统一按50G处理
-    //暂未使用RDMA端口
-    uint32_t index = ZXDH_TRPG_DEFAULT;  //riscv上默认初值
-    if(link_speed == 200000)
-    {
-        index = ZXDH_TRPG_SPEED_200G;
-    }
-    else if(link_speed == 100000)
-    {
-        index = ZXDH_TRPG_SPEED_100G;
-    }
-    else
-    {
-        index = ZXDH_TRPG_SPEED_50G;
-    }
-
-    return index;
-}
-
-DPP_PBU_PORT_TH_PARA_T port_th_para_tbl[ZXDH_TRPG_SPEED_NUM] =
-{
-    /*brief lif阈值  lif私有阈值  idma私有阈值  idma_th0 idma_th1 idma_th2 idma_th3 idma_th4 idma_th5 idma_th6 idma_th7*/
-    /*单位512byte,512代表芯片处理包粒度*/
-    {100, 140, 140, 110, 130, 150, 170, 190, 210, 230, 250},            //50G
-    {210, 280, 280, 180, 230, 280, 330, 380, 430, 480, 530},            //100G
-    {480, 560, 560, 370, 450, 550, 670, 770, 870, 970, 1070},            //200G
-    {1400, 0, 0, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500},       //400G RDMA
-    {2036, 2000, 2000, 2100, 2100, 2100, 2100, 2100, 2100, 2100, 2100}  //riscv上默认初始值
-};
-
-DPP_PBU_PORT_COS_TH_PARA_T port_cos_th_para_tbl[ZXDH_TRPG_SPEED_NUM] =
-{
-    /*单位512byte*/
-    {{100, 120, 140, 160, 180, 200, 220, 240}},         //50G
-    {{160, 210, 260, 310, 360, 410, 460, 510}},         //100G
-    {{320, 420, 480, 620, 720, 820, 920, 1020}},        //200G
-    {{1200, 1200, 2000, 2000, 2800, 2800, 2800, 2800}},  //400G RDMA
-    {{1650, 1700, 1750, 1800, 1850, 1900, 1950, 2000}} //riscv上默认初始值
-};
-
-uint32_t flow_td_th_tbl[ZXDH_TRPG_SPEED_NUM][ZXDH_DCBNL_MAX_TRAFFIC_CLASS] =
-{
-    /*单位KB*/
-    {72, 119, 166, 213, 260, 306, 353, 400},       //50G 梯度47
-    {144, 207, 269, 332, 394, 457, 519, 582},      //100G 梯度63
-    {287, 365, 443, 521, 600, 678, 756, 834},      //200G 梯度78  最小560*512/1000
-    {375, 570, 766, 961, 1156, 1352, 1547, 1742},  //400G RDMA 梯度195
-    {150, 150, 150, 150, 150, 150, 150, 150}       //riscv上默认初始值
-};
-
-uint32_t zxdh_config_param_compare_test(uint32_t tbl_index,
-                                        DPP_PBU_PORT_TH_PARA_T port_th_para,
-                                        DPP_PBU_PORT_COS_TH_PARA_T port_cos_th_para,
-                                        uint32_t *flow_td_th_para)
-{
-    uint32_t index = 0;
-    uint32_t *port_th_para_p1 = (uint32_t *)&port_th_para;
-    uint32_t *port_th_para_p2 = (uint32_t *)&port_cos_th_para_tbl[tbl_index];
-    for(index = 0; index<11; index++)
-    {
-        if(*(port_th_para_p1+index) != *(port_th_para_p2+index))
-        {
-            return false;
-        }
-    }
-    for(index = 0; index<ZXDH_DCBNL_MAX_TRAFFIC_CLASS; index++)
-    {
-        if((port_cos_th_para.cos_th[index]!= port_cos_th_para_tbl[tbl_index].cos_th[index])||
-        (flow_td_th_para[index] != flow_td_th_tbl[tbl_index][index]))
-        {
-            return false;
-        }
-    }
-    return true;
-}
-
-uint32_t zxdh_port_th_update(struct zxdh_en_device *en_dev)
-{
-    struct net_device *netdev = en_dev->netdev;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    //en_dev里面其实是包含link_speed的，填的是具体的速率值
-    uint32_t tbl_index;
-    uint32_t index;
-    uint32_t pfc_cur_mac_en = 0;
-    uint32_t ret = 0;
-    uint32_t speed = 0;
-    uint32_t max_speed = ZXDH_DCBNL_MAXRATE_KBITPS;
-    uint32_t params_check = 0;
-    DPP_PBU_PORT_TH_PARA_T port_th_para_test = {0};
-    DPP_PBU_PORT_COS_TH_PARA_T port_cos_th_para_test = {0};
-    DPP_TM_SHAPE_PP_PARA_T port_shape_para_test = {0};
-    uint32_t flow_td_th_para_test[ZXDH_DCBNL_MAX_TRAFFIC_CLASS] = {0};
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-    LOG_INFO("port speed en_dev->speed is abnormal: %d \n",en_dev->speed)
-
-    if(en_dev->speed)
-    {
-        speed = en_dev->speed *ZXDH_DCBNL_RATEUNIT_K;
-    }
-
-    zxdh_en_fc_mode_get(en_dev, &pfc_cur_mac_en);
-    if(pfc_cur_mac_en == BIT(SPM_FC_NONE))
-    {
-        LOG_INFO("port pfc & fc disable");
-        return 0;
-    }
-
-    //speed过滤
-    if ((0 == speed) || (speed > max_speed))
-    {
-        LOG_INFO("port speed is abnormal: %u \n",speed);
-        speed = max_speed;
-    }
-    ret = dpp_port_shape_set(&pf_info, en_dev->phy_port, speed, ZXDH_DCBNL_PORT_RATE_CBS, 1);
-
-    if(en_dev->phy_port > 9)
-    {
-        LOG_INFO("en_dev->phy_port not supported");
-        return 0;
-    }
-
-    tbl_index = zxdh_link_speed_to_index(en_dev->link_speed);
-
-    LOG_INFO("link_speed to tbl_index: %d", tbl_index);
-
-    if(pfc_cur_mac_en != BIT(SPM_FC_PAUSE_RX))
-    {
-        ret = dpp_port_th_set(&pf_info, en_dev->phy_port, port_th_para_tbl+tbl_index);
-
-        ret |= dpp_port_cos_th_set(&pf_info, en_dev->phy_port, port_cos_th_para_tbl+tbl_index);
-    }
-
-    //暂时规避fc下的td阈值改配
-    //if(pfc_cur_mac_en != BIT(SPM_FC_PAUSE_TX))
-    if(pfc_cur_mac_en == SPM_FC_PFC_FULL)
-    {
-        ret |= zxdh_dcbnl_set_flow_td_th(en_priv, flow_td_th_tbl[tbl_index]);
-    }
-
-    /*维测需要*/
-    dpp_port_th_get(&pf_info, en_dev->phy_port, &port_th_para_test);
-    LOG_INFO("dpp_port_th_get lif_th:%d, lif_prv:%d, idma_prv:%d \n",
-    port_th_para_test.lif_th, port_th_para_test.lif_prv, port_th_para_test.idma_prv);
-    LOG_INFO("idma_th0:%d, idma_th1:%d, idma_th2:%d, idma_th3:%d, idma_th4:%d, idma_th5:%d, idma_th6:%d, idma_th7:%d \n",
-    port_th_para_test.idma_th_cos0, port_th_para_test.idma_th_cos1, port_th_para_test.idma_th_cos2, port_th_para_test.idma_th_cos3,
-    port_th_para_test.idma_th_cos4, port_th_para_test.idma_th_cos5, port_th_para_test.idma_th_cos6, port_th_para_test.idma_th_cos7);
-
-    dpp_port_cos_th_get(&pf_info, en_dev->phy_port, &port_cos_th_para_test);
-    for(index = 0; index<ZXDH_DCBNL_MAX_TRAFFIC_CLASS; index++)
-    {
-        LOG_INFO("dpp_port_cos_th_get cos%d:%d\n", index, port_cos_th_para_test.cos_th[index]);
-    }
-    /*
-    LOG_INFO("dpp_port_cos_th_get cos0:%d, cos1:%d, cos2:%d, cos3:%d, cos4:%d, cos5:%d, cos6:%d, cos7:%d",\
-    port_cos_th_para_test->cos_th[0], port_cos_th_para_test->cos_th[1], port_cos_th_para_test->cos_th[2], port_cos_th_para_test->cos_th[3],\
-    port_cos_th_para_test->cos_th[4], port_cos_th_para_test->cos_th[6], port_cos_th_para_test->cos_th[0], port_cos_th_para_test->cos_th[0], )
-    */
-    dpp_port_shape_get(&pf_info, en_dev->phy_port, &port_shape_para_test);
-    LOG_INFO("dpp_port_shape_get cir:%d, cbs:%d, c_en:%d\n",port_shape_para_test.cir, port_shape_para_test.cbs, port_shape_para_test.c_en);
-
-    zxdh_dcbnl_get_flow_td_th(en_priv, flow_td_th_para_test);
-    for(index = 0; index<ZXDH_DCBNL_MAX_TRAFFIC_CLASS; index++)
-    {
-        LOG_INFO("zxdh_dcbnl_get_flow_td_th:tc_td_th[%d]:%d \n", index, flow_td_th_para_test[index]);
-    }
-
-    params_check = zxdh_config_param_compare_test(tbl_index, port_th_para_test, port_cos_th_para_test, flow_td_th_para_test);
-    if(params_check)
-    {
-        LOG_INFO("th_params_check OK");
-    }
-
-    return ret;
-}
-
-uint32_t zxdh_port_th_update_to_default(struct zxdh_en_device *en_dev)
-{
-    struct net_device *netdev = en_dev->netdev;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    uint32_t ret = 0;
-    uint32_t pfc_cur_mac_en = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    zxdh_en_fc_mode_get(en_dev, &pfc_cur_mac_en);
-
-    if(pfc_cur_mac_en != BIT(SPM_FC_PAUSE_TX))
-    {
-        ret = dpp_port_th_set(&pf_info, en_dev->phy_port, port_th_para_tbl+ZXDH_TRPG_DEFAULT);
-
-        ret |= dpp_port_cos_th_set(&pf_info, en_dev->phy_port, port_cos_th_para_tbl+ZXDH_TRPG_DEFAULT);
-    }
-
-    if(pfc_cur_mac_en != BIT(SPM_FC_PAUSE_RX))
-    {
-        ret |= zxdh_dcbnl_set_flow_td_th(en_priv, flow_td_th_tbl[ZXDH_TRPG_DEFAULT]);
-    }
-
-    return ret;
-}
-
-uint32_t zxdh_dcbnl_pfc_init(struct zxdh_en_priv *en_priv)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t ret = 0;
-    uint32_t test_en = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    LOG_INFO("zxdh_dcbnl_pfc_init start\n");
-
-    ret = dpp_qmu_pfc_en_set(&pf_info, 1);
-
-    if(ret)
-    {
-        LOG_ERR("dpp_qmu_pfc_en_set failed");
-    }
-
-    dpp_qmu_pfc_en_get(&pf_info, &test_en);
-    LOG_INFO("dpp_qmu_pfc_en_get:%d", test_en);
-    LOG_INFO("zxdh_dcbnl_pfc_init end\n");
-
-    return ret;
-}
-
-uint32_t zxdh_dcbnl_init_ets_scheduling_tree(struct zxdh_en_priv *en_priv)
-{
-    uint32_t err = 0;
-
-    zxdh_dcbnl_init_ets_list(en_priv);
-
-    err = zxdh_dcbnl_build_ets_scheduling_tree(en_priv);
-    if (err)
-    {
-        LOG_ERR("dcbnl_init_ets: build_tc_scheduling_tree failed \n");
-        goto init_ets_se_error;
-    }
-
-    err = zxdh_dcbnl_scheduling_tree_link_tc(en_priv);
-    if (err)
-    {
-        LOG_ERR("dcbnl_init_ets: scheduling_tree_link_tc failed \n");
-        goto init_ets_error;
-    }
-
-    err = zxdh_dcbnl_init_trust_and_table(en_priv);
-    if (err)
-    {
-        LOG_ERR("dcbnl_init_ets: init_trust_and_table failed \n");
-        goto init_ets_error;
-    }
-
-    return 0;
-
-init_ets_error:
-    zxdh_dcbnl_free_flow_resources(en_priv);
-init_ets_se_error:
-    zxdh_dcbnl_free_se_resources(en_priv);
-    LOG_INFO("dcbnl_init_ets failed \n");
-    return err;
-}
-
-uint32_t zxdh_dcbnl_set_tm_gate(struct zxdh_en_priv *en_priv, uint32_t mode)
-{
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (mode == 1)
-    {
-        err = dpp_tm_pport_mcode_switch_set(&pf_info, en_dev->phy_port, 1);
-        if (err)
-        {
-            LOG_ERR(" set_tm_gate open failed \n");
-        }
-    }
-    else if (mode == 0)
-    {
-        err = dpp_tm_pport_mcode_switch_del(&pf_info, en_dev->phy_port);
-        if (err)
-        {
-            LOG_ERR(" set_tm_gate close failed \n");
-        }
-    }
-    else
-    {
-        LOG_ERR(" error \n");
-    }
-
-    return err;
-}
+//#include <linux/device.h>
+#include "../../en_aux.h"
+#include "en_dcbnl.h"
+#include "en_dcbnl_api.h"
+#include "en_np/qos/include/dpp_drv_qos.h"
+#include "en_np/table/include/dpp_tbl_tm.h"
+#include "en_np/fc/include/dpp_drv_fc.h"
+#include "en_np/sdk/include/api/dpp_pbu_api.h"
+
+uint32_t zxdh_dcbnl_get_se_flow_resources(
+		struct zxdh_en_device *en_dev,
+		struct zxdh_dcbnl_ets_se_flow_resource *tree_resource)
+{
+	uint64_t gsch_id = 0;
+	uint32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+	if (tree_resource->level == ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL) {
+		err = dpp_sch_base_node_get(&pf_info, en_dev->phy_port, &gsch_id);
+	} else {
+		err = dpp_cosq_gsch_id_add(&pf_info, en_dev->phy_port,
+								   tree_resource->numq, tree_resource->level,
+								   tree_resource->flags, &gsch_id);
+	}
+
+	if (err) {
+		LOG_ERR("dcbnl_init_ets: get se/flow resources failed, level: %d, type: "
+				"%d, err:%d \n",
+				tree_resource->level, tree_resource->flags, err);
+		return err;
+	}
+	tree_resource->gsch_id = gsch_id;
+	tree_resource->resource_id = ZXDH_DCBNL_GET_GSCHID_MSG(
+			gsch_id, ZXDH_DCBNL_GSCHID_ID_MASK, ZXDH_DCBNL_GSCHID_ID_SHIFT);
+	/* debug */
+	LOG_INFO(" gsch_id:0x%llx,resource_id:0x%x level:%d, flags:%d\n", gsch_id,
+			 tree_resource->resource_id, tree_resource->level,
+			 tree_resource->flags);
+
+	return 0;
+}
+
+uint32_t zxdh_dcbnl_find_se_link_id(struct zxdh_en_priv *en_priv,
+									uint32_t level, uint32_t link_level,
+									uint32_t link_idx, uint32_t link_sp,
+									uint32_t *link_id)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_dcbnl_ets_se_node *se_link_node = NULL;
+	struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head =
+			&en_dev->dcb_para.ets_node_list_head[link_level];
+
+	*link_id = ZXDH_DCBNL_NULL_ID;
+
+	if (level < ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL) {
+		if (ets_node_list_head->se_next == NULL) {
+			LOG_ERR("dcbnl: no nodes in the link_level: %d \n", link_level);
+			return 1;
+		}
+
+		se_link_node = ets_node_list_head->se_next;
+
+		while ((NULL != se_link_node) && (se_link_node->node_idx != link_idx)) {
+			se_link_node = se_link_node->se_next;
+		}
+
+		if (se_link_node != NULL) {
+			*link_id = se_link_node->se_id + link_sp;
+		} else {
+			LOG_ERR("dcbnl: find se link_id failed, link_level: %d, link_idx: %d\n",
+					link_level, link_idx);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+uint32_t
+zxdh_dcbnl_save_se_resources(struct zxdh_en_priv *en_priv,
+							 struct zxdh_dcbnl_se_tree_config *tree_node_cfg)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_dcbnl_ets_se_flow_resource tree_resource = { 0 };
+	struct zxdh_dcbnl_ets_se_node *new_se_node = NULL;
+	struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = NULL;
+	uint32_t level = 0;
+	uint32_t link_level = 0;
+	uint32_t link_idx = 0;
+	uint32_t link_id = 0;
+	uint32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	level = tree_node_cfg->level;
+	link_level = tree_node_cfg->link_level;
+	link_idx = tree_node_cfg->link_idx;
+
+	if ((level == 0) || (level > 4) || (link_level > 5) ||
+		(level >= link_level)) {
+		LOG_ERR("dcbnl_init_ets: configuration level error, level: %d, link_level: "
+				"%d\n",
+				level, link_level);
+		return 1; // todo：考虑使用标准的错误定义
+	}
+
+	ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[level];
+
+	tree_resource.numq = 1;
+	tree_resource.level = level;
+	tree_resource.flags = tree_node_cfg->type;
+	err = zxdh_dcbnl_get_se_flow_resources(en_dev, &tree_resource);
+	if (err) {
+		LOG_ERR("dcbnl_init_ets: get se resources failed, level: %d, idx: %d\n",
+				tree_resource.level, tree_node_cfg->idx);
+		return err;
+	}
+
+	err = zxdh_dcbnl_find_se_link_id(en_priv, level, link_level, link_idx,
+									 tree_node_cfg->link_sp, &link_id);
+	if (err) {
+		LOG_ERR("dcbnl_init_ets: find se link_id failed, link_level: %d, link_idx: "
+				"%d\n",
+				link_level, link_idx);
+		return err;
+	}
+
+	new_se_node = kmalloc(sizeof(struct zxdh_dcbnl_ets_se_node), GFP_KERNEL);
+	if (NULL == new_se_node) {
+		LOG_ERR("dcbnl_init_ets: kmalloc se node failed\n");
+		return 1;
+	}
+
+	new_se_node->se_next = NULL;
+	new_se_node->gsch_id = tree_resource.gsch_id;
+	new_se_node->node_idx = tree_node_cfg->idx;
+	new_se_node->node_type = tree_node_cfg->type;
+	new_se_node->se_id = tree_resource.resource_id;
+	new_se_node->se_link_id = link_id;
+	new_se_node->se_link_weight = tree_node_cfg->link_weight;
+	new_se_node->se_link_sp = tree_node_cfg->link_sp;
+	new_se_node->link_point = tree_node_cfg->link_point;
+
+	if (level < ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL) {
+		err = dpp_crdt_se_link_set(&pf_info, new_se_node->se_id,
+								   new_se_node->se_link_id,
+								   new_se_node->se_link_weight,
+								   new_se_node->se_link_sp);
+		if (err) {
+			LOG_ERR("dcbnl_init_ets: dpp_crdt_se_link_set failed, level: %d, idx: "
+					"%d, err:%d\n",
+					level, tree_node_cfg->idx, err);
+			kfree(new_se_node);
+			return err;
+		}
+	}
+
+	new_se_node->se_next = ets_node_list_head->se_next;
+	ets_node_list_head->se_next = new_se_node;
+
+	ets_node_list_head->node_num += 1;
+
+	LOG_INFO(" level:%d, node_idx:%d, node_num:%d \n", level,
+			 new_se_node->node_idx, ets_node_list_head->node_num);
+	return 0;
+}
+
+uint32_t zxdh_dcbnl_build_ets_scheduling_tree(struct zxdh_en_priv *en_priv)
+{
+	uint32_t i = 0;
+	uint32_t err = 0;
+
+	struct zxdh_dcbnl_se_tree_config
+			ets_se_config_table[ZXDH_DCBNL_MAX_SE_NODE_NUM + 1] = {
+				/*level idx     type               link_level link_idx link_weight
+			 link_sp  link_point*/
+				{ 4, 0, ZXDH_DCBNL_ETS_NODE_WFQ, 5, 0, 1, 0,
+				  ZXDH_DCBNL_ETS_NODE_NULL },
+				{ 3, 0, ZXDH_DCBNL_ETS_NODE_FQ2, 4, 0, 1, 0,
+				  ZXDH_DCBNL_ETS_NODE_NULL },
+				{ 2, 0, ZXDH_DCBNL_ETS_NODE_FQ4, 3, 0, 1, 0,
+				  ZXDH_DCBNL_ETS_NODE_NULL },
+				{ 2, 1, ZXDH_DCBNL_ETS_NODE_FQ4, 3, 0, 1, 1,
+				  ZXDH_DCBNL_ETS_NODE_NULL },
+				{ 1, 0, ZXDH_DCBNL_ETS_NODE_FQ, 2, 0, 1, 0,
+				  ZXDH_DCBNL_ETS_NODE_VENDOR_C },
+				{ 1, 1, ZXDH_DCBNL_ETS_NODE_FQ8, 2, 0, 1, 1,
+				  ZXDH_DCBNL_ETS_NODE_STRICT_C },
+				{ 1, 2, ZXDH_DCBNL_ETS_NODE_WFQ, 2, 0, 1, 2,
+				  ZXDH_DCBNL_ETS_NODE_ETS_C },
+				{ 1, 3, ZXDH_DCBNL_ETS_NODE_WFQ, 2, 0, 1, 3,
+				  ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_C },
+				{ 1, 4, ZXDH_DCBNL_ETS_NODE_FQ, 2, 1, 1, 0,
+				  ZXDH_DCBNL_ETS_NODE_VENDOR_E },
+				{ 1, 5, ZXDH_DCBNL_ETS_NODE_FQ8, 2, 1, 1, 1,
+				  ZXDH_DCBNL_ETS_NODE_STRICT_E },
+				{ 1, 6, ZXDH_DCBNL_ETS_NODE_WFQ, 2, 1, 1, 2,
+				  ZXDH_DCBNL_ETS_NODE_ETS_E },
+				{ 1, 7, ZXDH_DCBNL_ETS_NODE_WFQ, 2, 1, 1, 3,
+				  ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_E },
+				{ 0xff }
+			};
+
+	for (i = 0;
+		 i < ZXDH_DCBNL_MAX_SE_NODE_NUM && ets_se_config_table[i].level != 0xff;
+		 i++) {
+		err = zxdh_dcbnl_save_se_resources(en_priv, &ets_se_config_table[i]);
+		if (err) {
+			LOG_ERR("dcbnl_init_ets: build_tc_scheduling_tree failed, entry: %d\n",
+					i);
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+void zxdh_dcbnl_tc_map_to_link_point(uint32_t tc_type, uint32_t *c_type,
+									 uint32_t *e_type)
+{
+	switch (tc_type) {
+	case ZXDH_DCBNL_VENDOR_TC:
+		*c_type = ZXDH_DCBNL_ETS_NODE_VENDOR_C;
+		*e_type = ZXDH_DCBNL_ETS_NODE_VENDOR_E;
+		break;
+
+	case ZXDH_DCBNL_STRICT_TC:
+		*c_type = ZXDH_DCBNL_ETS_NODE_STRICT_C;
+		*e_type = ZXDH_DCBNL_ETS_NODE_STRICT_E;
+		break;
+
+	case ZXDH_DCBNL_ETS_TC:
+		*c_type = ZXDH_DCBNL_ETS_NODE_ETS_C;
+		*e_type = ZXDH_DCBNL_ETS_NODE_ETS_E;
+		break;
+
+	case ZXDH_DCBNL_ZEROBW_ETS_TC:
+		*c_type = ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_C;
+		*e_type = ZXDH_DCBNL_ETS_NODE_ZEROBW_ETS_E;
+		break;
+	default:
+		break;
+	}
+}
+
+void zxdh_dcbnl_get_tc_weight_sp(uint32_t tc_type, uint32_t tc_tx_bw,
+								 uint32_t tc_id, uint32_t *c_weight,
+								 uint32_t *e_weight, uint32_t *c_sp,
+								 uint32_t *e_sp)
+{
+	if (tc_tx_bw == ZXDH_DCBNL_MAX_BW_ALLOC) {
+		*c_weight = 1;
+		*e_weight = 1;
+	} else {
+		*c_weight = ZXDH_DCBNL_MAX_WEIGHT * tc_tx_bw / ZXDH_DCBNL_MAX_BW_ALLOC;
+		*e_weight = ZXDH_DCBNL_MAX_WEIGHT * tc_tx_bw / ZXDH_DCBNL_MAX_BW_ALLOC;
+	}
+
+	if ((tc_type == ZXDH_DCBNL_STRICT_TC) &&
+		(tc_id < ZXDH_DCBNL_MAX_TRAFFIC_CLASS)) {
+		*c_sp = ZXDH_DCBNL_MAX_TRAFFIC_CLASS - 1 - tc_id;
+		*e_sp = ZXDH_DCBNL_MAX_TRAFFIC_CLASS - 1 - tc_id;
+	} else {
+		*c_sp = 0;
+		*e_sp = 0;
+	}
+}
+
+uint32_t zxdh_dcbnl_find_flow_link_se_id(struct zxdh_en_priv *en_priv,
+										 uint32_t tc_type, uint32_t link_level,
+										 uint32_t *c_linkid, uint32_t *e_linkid,
+										 uint32_t c_sp, uint32_t e_sp)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_dcbnl_ets_se_node *se_node =
+			en_dev->dcb_para.ets_node_list_head[link_level].se_next;
+	uint32_t c_type = 0;
+	uint32_t e_type = 0;
+
+	if (NULL == se_node) {
+		LOG_ERR("dcbnl: find_flow_link_se_id no nodes \n");
+		return 1;
+	}
+
+	zxdh_dcbnl_tc_map_to_link_point(tc_type, &c_type, &e_type);
+
+	*c_linkid = ZXDH_DCBNL_NULL_ID;
+	*e_linkid = ZXDH_DCBNL_NULL_ID;
+
+	while ((NULL != se_node) && ((ZXDH_DCBNL_NULL_ID == *c_linkid) ||
+								 (ZXDH_DCBNL_NULL_ID == *e_linkid))) {
+		if (se_node->link_point == c_type) {
+			*c_linkid = se_node->se_id + c_sp;
+		} else if (se_node->link_point == e_type) {
+			*e_linkid = se_node->se_id + e_sp;
+		}
+
+		se_node = se_node->se_next;
+	}
+
+	if ((ZXDH_DCBNL_NULL_ID == *c_linkid) ||
+		(ZXDH_DCBNL_NULL_ID == *e_linkid)) {
+		LOG_ERR("dcbnl: find_flow_link_se_id failed, c_linkid: 0x%x, e_linkid: 0x%x\n",
+				*c_linkid, *e_linkid);
+		return 1;
+	}
+	return 0;
+}
+
+uint32_t zxdh_dcbnl_get_ieee_tsa(uint32_t tc_type)
+{
+	uint32_t tsa = 0;
+	switch (tc_type) {
+	case ZXDH_DCBNL_ETS_TC:
+	case ZXDH_DCBNL_ZEROBW_ETS_TC:
+		tsa = IEEE_8021QAZ_TSA_ETS;
+		break;
+	case ZXDH_DCBNL_STRICT_TC:
+		tsa = IEEE_8021QAZ_TSA_STRICT;
+		break;
+	case ZXDH_DCBNL_VENDOR_TC:
+		tsa = IEEE_8021QAZ_TSA_VENDOR;
+		break;
+	default:
+		tsa = IEEE_8021QAZ_TSA_STRICT;
+		LOG_ERR("dcbnl:tsa error, change to strict \n");
+		break;
+	}
+	return tsa;
+}
+
+uint32_t zxdh_dcbnl_save_flow_resources(
+		struct zxdh_en_priv *en_priv,
+		struct zxdh_dcbnl_tc_flow_config *tc_flow_config,
+		struct zxdh_dcbnl_ets_se_flow_resource *tree_resource, uint32_t tc_id)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_dcbnl_ets_flow_node *new_flow_node = NULL;
+	struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = NULL;
+	struct zxdh_dcbnl_tc_flow_shape_para p_para = { 0 };
+	uint32_t c_linkid = 0;
+	uint32_t e_linkid = 0;
+	uint32_t c_weight = 0;
+	uint32_t e_weight = 0;
+	uint32_t c_sp = 0;
+	uint32_t e_sp = 0;
+	uint32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if (tc_flow_config->link_level != 1) {
+		LOG_ERR("dcbnl_init_ets: zxdh_dcbnl_save_flow_resources link_level err\n");
+		return 1;
+	}
+
+	ets_node_list_head =
+			&en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL];
+
+	if (tc_id == 0) {
+		tree_resource->numq = ZXDH_DCBNL_MAX_TRAFFIC_CLASS;
+		tree_resource->level = ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL;
+		tree_resource->flags = ZXDH_DCBNL_ETS_NODE_FLOW;
+		err = zxdh_dcbnl_get_se_flow_resources(en_dev, tree_resource);
+		if (err) {
+			LOG_ERR("dcbnl_init_ets: get flow resources err\n");
+			return err;
+		}
+
+		err = dpp_tm_flowid_pport_table_set(&pf_info, en_dev->phy_port,
+											tree_resource->resource_id);
+		if (err) {
+			LOG_ERR("dcbnl_init_ets: flowid_pport_table_set failed, port: %d, "
+					"flowid:%d, err:%d\n",
+					en_dev->phy_port, tree_resource->resource_id, err);
+			return err;
+		}
+	}
+
+	zxdh_dcbnl_get_tc_weight_sp(tc_flow_config->tc_type,
+								tc_flow_config->tc_tx_bw, tc_id, &c_weight,
+								&e_weight, &c_sp, &e_sp);
+
+	err = zxdh_dcbnl_find_flow_link_se_id(en_priv, tc_flow_config->tc_type,
+										  tc_flow_config->link_level, &c_linkid,
+										  &e_linkid, c_sp, e_sp);
+	if (err) {
+		LOG_ERR("dcbnl_init_ets init ets: find_flow_link_se_id failed, tc_id: %d, "
+				"tc_type: %d\n",
+				tc_id, tc_flow_config->tc_type);
+		return err;
+	}
+
+	new_flow_node =
+			kmalloc(sizeof(struct zxdh_dcbnl_ets_flow_node), GFP_KERNEL);
+	if (new_flow_node == NULL) {
+		LOG_ERR("dcbnl_init_ets: kmalloc new flow node failed\n");
+		return 1;
+	}
+
+	new_flow_node->flow_next = NULL;
+	new_flow_node->gsch_id = tree_resource->gsch_id + tc_id;
+	new_flow_node->flow_id = tree_resource->resource_id + tc_id;
+	new_flow_node->tc_id = tc_id;
+	new_flow_node->tc_type = tc_flow_config->tc_type;
+	new_flow_node->tc_tx_bw = tc_flow_config->tc_tx_bw;
+	new_flow_node->td_th = tc_flow_config->td_th;
+	new_flow_node->c_linkid = c_linkid;
+	new_flow_node->c_weight = c_weight;
+	new_flow_node->c_sp = c_sp;
+	new_flow_node->c_rate = tc_flow_config->c_rate;
+	new_flow_node->mode = 1;
+	new_flow_node->e_linkid = e_linkid;
+	new_flow_node->e_weight = e_weight;
+	new_flow_node->e_sp = e_sp;
+	new_flow_node->e_rate = tc_flow_config->e_rate;
+
+	err = dpp_flow_map_port_set(&pf_info, new_flow_node->flow_id,
+								en_dev->phy_port);
+	if (err) {
+		LOG_ERR("dcbnl_init_ets: dpp_flow_map_port_set failed, flow_id: %d, "
+				"phy_port: %d, err:%d\n",
+				new_flow_node->flow_id, en_dev->phy_port, err);
+		kfree(new_flow_node);
+		return err;
+	}
+
+	err = dpp_crdt_flow_link_set(&pf_info, new_flow_node->flow_id, c_linkid,
+								 c_weight, c_sp, new_flow_node->mode, e_linkid,
+								 e_weight, e_sp);
+	if (err) {
+		LOG_ERR("dcbnl_init_ets: dpp_crdt_flow_link_set failed, flow_id: %d, "
+				"c_linkid: %d, e_linkid: %d, err:%d\n",
+				new_flow_node->flow_id, c_linkid, e_linkid, err);
+		kfree(new_flow_node);
+		return err;
+	}
+
+	err = dpp_flow_td_th_set(&pf_info, new_flow_node->flow_id,
+							 new_flow_node->td_th);
+	if (err) {
+		LOG_ERR("dcbnl_init_ets: dpp_flow_td_th_set failed,vport:%d flow_id: %d, "
+				"td_th: %d, err:%d\n",
+				en_dev->vport, new_flow_node->flow_id, new_flow_node->td_th,
+				err);
+		// kfree(new_flow_node);  //The default is 150
+		// return err;
+	}
+
+	p_para.cir = new_flow_node->c_rate;
+	p_para.cbs = ZXDH_DCBNL_FLOW_RATE_CBS;
+	p_para.db_en = 1;
+	p_para.eir = new_flow_node->e_rate;
+	p_para.ebs = ZXDH_DCBNL_FLOW_RATE_EBS;
+
+	err = dpp_flow_shape_set(&pf_info, new_flow_node->flow_id, p_para.cir,
+							 p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs);
+	if (err) {
+		LOG_ERR("dcbnl_init_ets: dpp_flow_shape_set failed, vport: %d, flow_id: "
+				"%d, tc_id: %d, e_rate: %d, err:%d\n",
+				en_dev->vport, new_flow_node->flow_id, new_flow_node->tc_id,
+				new_flow_node->e_rate, err);
+	}
+
+	new_flow_node->flow_next = ets_node_list_head->flow_next;
+	ets_node_list_head->flow_next = new_flow_node;
+	ets_node_list_head->node_num += 1;
+
+	en_dev->dcb_para.ets_cfg.tc_tsa[tc_id] =
+			zxdh_dcbnl_get_ieee_tsa(new_flow_node->tc_type);
+	en_dev->dcb_para.ets_cfg.tc_tx_bw[tc_id] = tc_flow_config->tc_tx_bw;
+	en_dev->dcb_para.tc_maxrate[tc_id] = new_flow_node->e_rate;
+
+	LOG_INFO(" level:%d, tc_id:%d, flow_id:%d, node_num:%d \n",
+			 tree_resource->level, new_flow_node->tc_id, new_flow_node->flow_id,
+			 ets_node_list_head->node_num);
+
+	return 0;
+}
+
+uint32_t zxdh_dcbnl_scheduling_tree_link_tc(struct zxdh_en_priv *en_priv)
+{
+	struct zxdh_dcbnl_ets_se_flow_resource tree_resource;
+	uint32_t i = 0;
+	uint32_t err = 0;
+
+	struct zxdh_dcbnl_tc_flow_config
+			ets_tc_config_table[ZXDH_DCBNL_MAX_TRAFFIC_CLASS + 1] = {
+				/*link_level  tc_type         tc_tx_bw  c_rate  e_rate td_th */
+				{ 1, ZXDH_DCBNL_STRICT_TC, 100, 0, ZXDH_DCBNL_MAXRATE_KBITPS,
+				  150 },
+				{ 1, ZXDH_DCBNL_STRICT_TC, 100, 0, ZXDH_DCBNL_MAXRATE_KBITPS,
+				  150 },
+				{ 1, ZXDH_DCBNL_STRICT_TC, 100, 0, ZXDH_DCBNL_MAXRATE_KBITPS,
+				  150 },
+				{ 1, ZXDH_DCBNL_STRICT_TC, 100, 0, ZXDH_DCBNL_MAXRATE_KBITPS,
+				  150 },
+				{ 1, ZXDH_DCBNL_STRICT_TC, 100, 0, ZXDH_DCBNL_MAXRATE_KBITPS,
+				  150 },
+				{ 1, ZXDH_DCBNL_STRICT_TC, 100, 0, ZXDH_DCBNL_MAXRATE_KBITPS,
+				  150 },
+				{ 1, ZXDH_DCBNL_STRICT_TC, 100, 0, ZXDH_DCBNL_MAXRATE_KBITPS,
+				  150 },
+				{ 1, ZXDH_DCBNL_STRICT_TC, 100, 0, ZXDH_DCBNL_MAXRATE_KBITPS,
+				  150 },
+				{ 0xff }
+			};
+
+	for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS &&
+				ets_tc_config_table[i].link_level != 0xff;
+		 i++) {
+		err = zxdh_dcbnl_save_flow_resources(en_priv, &ets_tc_config_table[i],
+											 &tree_resource, i);
+		if (err) {
+			LOG_ERR("dcbnl_init_ets: save_flow_resources failed, entry: %d\n",
+					i);
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+uint32_t zxdh_dcbnl_set_ets_trust(struct zxdh_en_priv *en_priv, uint32_t trust)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	err = dpp_tm_pport_trust_mode_table_set(&pf_info, en_dev->phy_port, trust);
+	if (err) {
+		LOG_ERR("dcbnl_set_ets: set_ets_trust failed, vport: %d, trust: %d, err:%d\n",
+				en_dev->vport, trust, err);
+		return err;
+	}
+	en_dev->dcb_para.trust = trust;
+	LOG_INFO(" trust:%d \n", trust);
+	return 0;
+}
+
+uint32_t zxdh_dcbnl_init_trust_and_table(struct zxdh_en_priv *en_priv)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t i = 0;
+	uint32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	for (i = 0; i < ZXDH_DCBNL_MAX_PRIORITY; i++) {
+		err = dpp_tm_pport_up_map_table_set(&pf_info, en_dev->phy_port, i,
+											i); //初始时，配置一一对应
+		if (err) {
+			LOG_ERR("dcbnl_init_ets: dpp_tm_pport_up_map_table_set failed, vport: "
+					"%d, phy_port: %d, err:%d\n",
+					en_dev->vport, en_dev->phy_port, err);
+			return err;
+		}
+		en_dev->dcb_para.ets_cfg.prio_tc[i] = i;
+		LOG_INFO(" vport:%d,phy_port:%d prio:%d, tc:%d \n", en_dev->vport,
+				 en_dev->phy_port, i, en_dev->dcb_para.ets_cfg.prio_tc[i]);
+	}
+
+	for (i = 0; i < ZXDH_DCBNL_MAX_DSCP; i++) {
+		err = dpp_tm_pport_dscp_map_table_set(&pf_info, en_dev->phy_port, i,
+											  i >> 3);
+		if (err) {
+			LOG_ERR("dcbnl_init_ets: dscp_map_table_set failed, vport: %d, phy_port: "
+					"%d, err:%d\n",
+					en_dev->vport, en_dev->phy_port, err);
+			return err;
+		}
+
+		en_dev->dcb_para.dscp2prio[i] = i >> 3;
+		LOG_INFO("vport:%d,phy_port:%d,dscp:%d, prio:%d \n", en_dev->vport,
+				 en_dev->phy_port, i, en_dev->dcb_para.dscp2prio[i]);
+	}
+
+	err = zxdh_dcbnl_set_ets_trust(en_priv, ZXDH_DCBNL_ETS_TRUST_PCP);
+	if (err) {
+		LOG_INFO("set_ets_trust failed \n");
+		return err;
+	}
+	en_dev->dcb_para.trust = ZXDH_DCBNL_ETS_TRUST_PCP;
+	LOG_INFO(" vport:%d,phy_port:%d,trust:%d \n", en_dev->vport,
+			 en_dev->phy_port, en_dev->dcb_para.trust);
+	return 0;
+}
+
+uint32_t zxdh_dcbnl_init_ets_list(struct zxdh_en_priv *en_priv)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t level = 0;
+
+	for (level = 0; level < ZXDH_DCBNL_MAX_TREE_LEVEL; level++) {
+		en_dev->dcb_para.ets_node_list_head[level].se_next = NULL;
+		en_dev->dcb_para.ets_node_list_head[level].flow_next = NULL;
+		en_dev->dcb_para.ets_node_list_head[level].node_num = 0;
+	}
+	return 0;
+}
+
+/* Normal release se*/
+uint32_t zxdh_dcbnl_free_se_resources(struct zxdh_en_priv *en_priv)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_dcbnl_ets_se_node *se_node = NULL;
+	struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = NULL;
+	uint32_t err = 0;
+	uint32_t level = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	LOG_INFO(" vport:%d, phy_port:%d \n", en_dev->vport, en_dev->phy_port);
+	for (level = 1; level <= ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL; level++) {
+		ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[level];
+		while (NULL != ets_node_list_head->se_next) {
+			se_node = ets_node_list_head->se_next;
+			ets_node_list_head->se_next = se_node->se_next;
+			if (level < ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL) {
+				err = dpp_crdt_del_se_link_set(&pf_info, se_node->se_id,
+											   se_node->se_id);
+				if (err) {
+					LOG_ERR("dcbnl_free_ets: dpp_crdt_del_se_link_set failed, se_id: %d, "
+							"err:%d \n",
+							se_node->se_id, err);
+				}
+
+				err = dpp_cosq_gsch_id_delete(&pf_info, en_dev->phy_port,
+											  se_node->gsch_id);
+				if (err) {
+					LOG_ERR("dcbnl_free_ets: dpp_cosq_gsch_id_delete failed, se_id: "
+							"%lld, err:%d \n",
+							se_node->gsch_id, err);
+				}
+			}
+			LOG_INFO(" free level:%d se_id:%x \n", level, se_node->se_id);
+			kfree(se_node);
+			ets_node_list_head->node_num -= 1;
+			LOG_INFO("current node_num:%d \n", ets_node_list_head->node_num);
+		}
+	}
+
+	return 0;
+}
+/* Normal release flow*/
+uint32_t zxdh_dcbnl_free_flow_resources(struct zxdh_en_priv *en_priv)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_dcbnl_ets_flow_node *flow_node = NULL;
+	struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head =
+			&en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL];
+	uint32_t err = 0;
+	bool have_flow = false;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	LOG_INFO(" vport:%d, phy_port:%d \n", en_dev->vport, en_dev->phy_port);
+	while (NULL != ets_node_list_head->flow_next) {
+		have_flow = true;
+		flow_node = ets_node_list_head->flow_next;
+		ets_node_list_head->flow_next = flow_node->flow_next;
+
+		err = dpp_flow_td_th_set(&pf_info, flow_node->flow_id, 0);
+		if (err) {
+			LOG_ERR("dcbnl_free_ets: dpp_flow_td_th_set failed,vport:%d flow_id: %d, "
+					"td_th: 0, err:%d\n",
+					en_dev->vport, flow_node->flow_id, err);
+		}
+
+		err = dpp_crdt_del_flow_link_set(&pf_info, flow_node->flow_id,
+										 flow_node->flow_id);
+		if (err) {
+			LOG_ERR("dcbnl_free_ets: dpp_crdt_del_flow_link_set failed, flow_id: %d, "
+					"err:%d \n",
+					flow_node->flow_id, err);
+		}
+
+		err = dpp_cosq_gsch_id_delete(&pf_info, en_dev->phy_port,
+									  flow_node->gsch_id);
+		if (err) {
+			LOG_ERR("dcbnl_free_ets: dpp_cosq_gsch_id_delete failed, gsch_id: %lld "
+					",err:%d\n",
+					flow_node->gsch_id, err);
+		}
+
+		LOG_INFO(" free level:0, flow_id:%d, tc:%d\n", flow_node->flow_id,
+				 flow_node->tc_id);
+
+		kfree(flow_node);
+		ets_node_list_head->node_num -= 1;
+		LOG_INFO("current node_num:%d \n", ets_node_list_head->node_num);
+	}
+
+	if (have_flow) {
+		err = dpp_tm_flowid_pport_table_del(&pf_info, en_dev->phy_port);
+		if (err) {
+			LOG_ERR("dcbnl_free_ets: dpp_tm_flowid_pport_table_del failed,vport:%d, "
+					"phy_port: %d \n",
+					en_dev->vport, en_dev->phy_port);
+		}
+	}
+
+	return 0;
+}
+
+/* host no reset，risc reset? */
+uint32_t zxdh_dcbnl_check_and_free_node_memory(struct zxdh_en_priv *en_priv)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_dcbnl_ets_flow_node *flow_node = NULL;
+	struct zxdh_dcbnl_ets_se_node *se_node = NULL;
+	struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = NULL;
+	uint32_t level = 0;
+
+	ets_node_list_head =
+			&en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL];
+	while (NULL != ets_node_list_head->flow_next) {
+		flow_node = ets_node_list_head->flow_next;
+		ets_node_list_head->flow_next = flow_node->flow_next;
+		kfree(flow_node);
+		ets_node_list_head->node_num -= 1;
+	}
+
+	for (level = 1; level < ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL + 1; level++) {
+		ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[level];
+		while (NULL != ets_node_list_head->se_next) {
+			se_node = ets_node_list_head->se_next;
+			ets_node_list_head->se_next = se_node->se_next;
+			kfree(se_node);
+			ets_node_list_head->node_num -= 1;
+		}
+	}
+
+	return 0;
+}
+
+uint32_t zxdh_dcbnl_set_tc_scheduling(struct zxdh_en_priv *en_priv,
+									  uint8_t *tc_type, uint8_t *tc_tx_bw)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_dcbnl_ets_flow_node *flow_node =
+			en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL]
+					.flow_next;
+	uint32_t tc_id = 0;
+	uint32_t c_linkid = 0;
+	uint32_t e_linkid = 0;
+	uint32_t c_weight = 0;
+	uint32_t e_weight = 0;
+	uint32_t c_sp = 0;
+	uint32_t e_sp = 0;
+	uint32_t i = 0;
+	uint32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if (NULL == flow_node) {
+		LOG_ERR("dcbnl_set_ets: set_tc_scheduling no flow in the tree\n");
+		return 1;
+	}
+
+	for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS && flow_node != NULL; i++) {
+		tc_id = flow_node->tc_id;
+		if ((flow_node->tc_type == tc_type[tc_id]) &&
+			(flow_node->tc_tx_bw == tc_tx_bw[tc_id])) {
+			LOG_INFO("Same configuration,tc_id:%d, tc_type:%d, tc_tx_bw:%d\n",
+					 tc_id, tc_type[tc_id], tc_tx_bw[tc_id]);
+			flow_node = flow_node->flow_next;
+			continue;
+		}
+
+		zxdh_dcbnl_get_tc_weight_sp(tc_type[tc_id], tc_tx_bw[tc_id], tc_id,
+									&c_weight, &e_weight, &c_sp, &e_sp);
+
+		err = zxdh_dcbnl_find_flow_link_se_id(en_priv, tc_type[tc_id], 1,
+											  &c_linkid, &e_linkid, c_sp, e_sp);
+		if (err) {
+			LOG_ERR("dcbnl_set_ets: find_flow_link_se_id failed, tc_id: %d, tc_type: "
+					"%d\n",
+					tc_id, tc_type[tc_id]);
+			return err;
+		}
+
+		/* 先删除挂接 todo:后续要先限流，清TD再删挂接?*/
+		err = dpp_flow_td_th_set(&pf_info, flow_node->flow_id, 0);
+		if (err) {
+			LOG_ERR("dcbnl_set_ets: dpp_flow_td_th_set failed,vport:%d flow_id: %d, "
+					"td_th: 0, err:%d\n",
+					en_dev->vport, flow_node->flow_id, err);
+		}
+
+		err = dpp_crdt_del_flow_link_set(&pf_info, flow_node->flow_id,
+										 flow_node->flow_id);
+		if (err) {
+			LOG_ERR("dcbnl_set_ets: dpp_crdt_del_flow_link_set failed, vport: %d, "
+					"flow_id: %d, err:%d\n",
+					en_dev->vport, flow_node->flow_id, err);
+			return err;
+		}
+
+		/* 重新挂接 todo:后续要挂接、设置td，重设限速?*/
+		err = dpp_crdt_flow_link_set(&pf_info, flow_node->flow_id, c_linkid,
+									 c_weight, c_sp, 1, e_linkid, e_weight,
+									 e_sp);
+		if (err) {
+			LOG_ERR("dcbnl_set_ets: dpp_crdt_flow_link_set failed, flow_id: %d, "
+					"flow_id: %d, flow_id: %d, err:%d\n",
+					flow_node->flow_id, c_linkid, e_linkid, err);
+			return err;
+		}
+
+		err = dpp_flow_td_th_set(&pf_info, flow_node->flow_id,
+								 flow_node->td_th);
+		if (err) {
+			LOG_ERR("dcbnl_set_ets: dpp_flow_td_th_set failed,vport:%d flow_id: %d, "
+					"td_th:%d, err:%d\n",
+					en_dev->vport, flow_node->flow_id, flow_node->td_th, err);
+		}
+
+		flow_node->tc_type = tc_type[tc_id];
+		flow_node->tc_tx_bw = tc_tx_bw[tc_id];
+
+		flow_node->c_linkid = c_linkid;
+		flow_node->c_weight = c_weight;
+		flow_node->c_sp = c_sp;
+
+		flow_node->e_linkid = e_linkid;
+		flow_node->e_weight = e_weight;
+		flow_node->e_sp = e_sp;
+
+		LOG_INFO(" tc_id:%d, tc_type:%d, c_linkid:%x, e_weight:%d, e_sp:%d "
+				 ",e_linkid:%x, e_weight:%d, e_sp:%d \n",
+				 tc_id, flow_node->tc_type, flow_node->c_linkid,
+				 flow_node->c_weight, flow_node->c_sp, flow_node->e_linkid,
+				 flow_node->e_weight, flow_node->e_sp);
+
+		flow_node = flow_node->flow_next;
+	}
+
+	return 0;
+}
+
+uint32_t zxdh_dcbnl_set_ets_up_tc_map(struct zxdh_en_priv *en_priv,
+									  uint8_t *prio_tc)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t i = 0;
+	uint32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	LOG_INFO(" begin \n");
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	for (i = 0; i < ZXDH_DCBNL_MAX_PRIORITY; i++) {
+		err = dpp_tm_pport_up_map_table_set(&pf_info, en_dev->phy_port, i,
+											prio_tc[i]);
+		if (err) {
+			LOG_ERR("dcbnl_set_ets:  failed, vport: %d, prio: %d, tc: %d, err:%d\n",
+					en_dev->vport, i, prio_tc[i], err);
+			return err;
+		}
+		LOG_INFO(" vport:%d, phy_port:%d, prio:%d, tc:%d \n", en_dev->vport,
+				 en_dev->phy_port, i, prio_tc[i]);
+	}
+	return 0;
+}
+
+uint32_t zxdh_dcbnl_set_tc_maxrate(struct zxdh_en_priv *en_priv,
+								   uint32_t *maxrate)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_dcbnl_ets_flow_node *flow_node =
+			en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL]
+					.flow_next;
+	struct zxdh_dcbnl_tc_flow_shape_para p_para = { 0 };
+	uint32_t tc_id = 0;
+	uint32_t i = 0;
+	uint32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if (NULL == flow_node) {
+		LOG_ERR("dcbnl_set_ets: set_tc_maxrate no flow in the tree\n");
+		return 1;
+	}
+
+	for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS && flow_node != NULL; i++) {
+		tc_id = flow_node->tc_id;
+		if (flow_node->e_rate == maxrate[tc_id]) {
+			LOG_INFO("Same configuration, tc_id:%d, maxrate:%d\n", tc_id,
+					 maxrate[tc_id]);
+			flow_node = flow_node->flow_next;
+			continue;
+		}
+		p_para.cir = 0;
+		p_para.cbs = ZXDH_DCBNL_FLOW_RATE_CBS;
+		p_para.db_en = 1;
+		p_para.eir = maxrate[tc_id];
+		p_para.ebs = ZXDH_DCBNL_FLOW_RATE_EBS;
+
+		LOG_INFO(" vport%d,phy_port:%d, flow_id:%d,tc_id:%d, cir:%d, cbs:%d, "
+				 "db_en:%d, eir:%d,ebs:%d \n",
+				 en_dev->vport, en_dev->phy_port, flow_node->flow_id, tc_id,
+				 p_para.cir, p_para.cbs, p_para.db_en, p_para.eir, p_para.ebs);
+
+		err = dpp_flow_shape_set(&pf_info, flow_node->flow_id, p_para.cir,
+								 p_para.cbs, p_para.db_en, p_para.eir,
+								 p_para.ebs);
+		if (err) {
+			LOG_ERR("dcbnl_set_ets: dpp_flow_shape_set failed, vport: %d, flow_id: "
+					"%d, tc_id: %d, eir: %d, err:%d\n",
+					en_dev->vport, flow_node->flow_id, tc_id, maxrate[tc_id],
+					err);
+			return err;
+		}
+
+		flow_node->e_rate = maxrate[tc_id];
+		en_dev->dcb_para.tc_maxrate[tc_id] = maxrate[tc_id];
+
+		flow_node = flow_node->flow_next;
+	}
+
+	return 0;
+}
+
+uint32_t zxdh_dcbnl_set_dscp2prio(struct zxdh_en_priv *en_priv, uint16_t dscp,
+								  uint8_t prio)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	err = dpp_tm_pport_dscp_map_table_set(&pf_info, en_dev->phy_port, dscp,
+										  prio);
+	if (err) {
+		LOG_ERR("dcbnl_set_ets: set_dscp2prio failed, vport: %d, dscp: %d, prio: "
+				"%d, err:%d\n",
+				en_dev->vport, dscp, prio, err);
+		return err;
+	}
+	en_dev->dcb_para.dscp2prio[dscp] = prio;
+	LOG_INFO(" vport:%d, ephy_port:%d,dscp:%d, up:%d \n", en_dev->vport,
+			 en_dev->phy_port, dscp, prio);
+
+	return 0;
+}
+
+uint32_t zxdh_dcbnl_set_flow_td_th(struct zxdh_en_priv *en_priv,
+								   uint32_t *tc_td_th)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_dcbnl_ets_flow_node *flow_node =
+			en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL]
+					.flow_next;
+	uint32_t err = 0;
+	uint32_t i = 0;
+	uint32_t tc_id = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if (flow_node == NULL) {
+		LOG_ERR("dcbnl_set_ets: set_flow_td_th no flow in the tree\n");
+		return 1;
+	}
+
+	if (tc_td_th == NULL) {
+		LOG_ERR("dcbnl_set_ets: tc_td_th is null \n");
+		return 1;
+	}
+
+	for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS && flow_node != NULL; i++) {
+		tc_id = flow_node->tc_id;
+		err = dpp_flow_td_th_set(&pf_info, flow_node->flow_id, tc_td_th[tc_id]);
+		if (err) {
+			LOG_ERR("dcbnl_set_ets: set_flow_td_th failed, vport: %d, flow_id:%d, "
+					"tc_id:%d, td_th: %d, err:%d\n",
+					en_dev->vport, flow_node->flow_id, tc_id, tc_td_th[tc_id],
+					err);
+			return err;
+		}
+		flow_node->td_th = tc_td_th[tc_id];
+		flow_node = flow_node->flow_next;
+	}
+
+	return 0;
+}
+
+uint32_t zxdh_dcbnl_get_flow_td_th(struct zxdh_en_priv *en_priv,
+								   uint32_t *tc_td_th)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_dcbnl_ets_flow_node *flow_node =
+			en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL]
+					.flow_next;
+	uint32_t err = 0;
+	uint32_t i = 0;
+	uint32_t tc_id = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if (flow_node == NULL) {
+		LOG_ERR("get_flow_td_th no flow in the tree\n");
+		return 1;
+	}
+
+	if (tc_td_th == NULL) {
+		LOG_ERR(" tc_td_th is null \n");
+		return 1;
+	}
+
+	for (i = 0; i < ZXDH_DCBNL_MAX_TRAFFIC_CLASS && flow_node != NULL; i++) {
+		tc_id = flow_node->tc_id;
+		err = dpp_flow_td_th_get(&pf_info, flow_node->flow_id,
+								 &tc_td_th[tc_id]);
+		if (err) {
+			LOG_ERR("get_flow_td_th failed, vport: %d, flow_id:%d, tc_id:%d, err:%d\n",
+					en_dev->vport, flow_node->flow_id, tc_id, err);
+			return err;
+		}
+		flow_node = flow_node->flow_next;
+	}
+
+	return 0;
+}
+
+uint32_t zxdh_dcbnl_init_port_speed(struct zxdh_en_priv *en_priv)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_dcbnl_tc_flow_shape_para p_para = { 0 };
+	uint32_t err = 0;
+	uint32_t speed = 0;
+	uint32_t max_speed = ZXDH_DCBNL_MAXRATE_KBITPS / ZXDH_DCBNL_RATEUNIT_K;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	speed = en_dev->speed;
+	if ((0 == speed) || (speed > max_speed)) {
+		LOG_INFO("get port speed is : %u ,set to max:%u\n", speed, max_speed);
+		speed = max_speed;
+	}
+
+	p_para.cir = speed * ZXDH_DCBNL_RATEUNIT_K; // Mbps->Kbps
+	p_para.cbs = ZXDH_DCBNL_PORT_RATE_CBS;
+	p_para.db_en = 0;
+	p_para.eir = 0;
+	p_para.ebs = 0;
+
+	LOG_INFO(" vport:%d,phy_port:%d, p_para.cir:%d, speed:%d \n", en_dev->vport,
+			 en_dev->phy_port, p_para.cir, speed);
+
+	err = dpp_port_shape_set(&pf_info, en_dev->phy_port, p_para.cir, p_para.cbs,
+							 1);
+	if (err) {
+		LOG_ERR("dcbnl_set_ets: dpp_port_shape_set failed, port:%d, speed:%d, "
+				"speed:%d,err:%d \n",
+				en_dev->phy_port, speed, p_para.cir, err);
+		return err;
+	}
+
+	return 0;
+}
+
+uint32_t zxdh_dcbnl_printk_ets_tree(struct zxdh_en_priv *en_priv)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_dcbnl_ets_flow_node *flow_node = NULL;
+	struct zxdh_dcbnl_ets_se_node *se_node = NULL;
+	struct zxdh_dcbnl_ets_node_list_head *ets_node_list_head = NULL;
+	uint32_t level = 0;
+
+	LOG_INFO(" ***vport:%d port:%d \n", en_dev->vport, en_dev->phy_port);
+
+	for (level = ZXDH_DCBNL_ETS_TREE_ROOT_LEVEL; level > 0; level--) {
+		ets_node_list_head = &en_dev->dcb_para.ets_node_list_head[level];
+		se_node = ets_node_list_head->se_next;
+		while (NULL != se_node) {
+			LOG_INFO(" se_node *** level:%d, node_idx:%d, se_id:0x%x *** \n",
+					 level, se_node->node_idx, se_node->se_id);
+			LOG_INFO(" se_node gsch_id:0x%llx, node_type:%d, se_id:0x%x \n",
+					 se_node->gsch_id, se_node->node_type, se_node->se_id);
+			LOG_INFO(
+					" se_node se_link_id:0x%x, se_link_weight:%d, se_link_sp:%d, "
+					"link_point:%d \n",
+					se_node->se_link_id, se_node->se_link_weight,
+					se_node->se_link_sp, se_node->link_point);
+			se_node = se_node->se_next;
+		}
+	}
+
+	ets_node_list_head =
+			&en_dev->dcb_para.ets_node_list_head[ZXDH_DCBNL_ETS_TREE_FLOW_LEVEL];
+	flow_node = ets_node_list_head->flow_next;
+	while (NULL != flow_node) {
+		LOG_INFO(" flow_node *** tc_id:%d, flow_id:%d *** \n", flow_node->tc_id,
+				 flow_node->flow_id);
+		LOG_INFO(" flow_node gsch_id:0x%llx,  tc_type:%d, td_th:%d \n",
+				 flow_node->gsch_id, flow_node->tc_type, flow_node->td_th);
+		LOG_INFO(" flow_node c_linkid:0x%x, c_weight:%d, c_sp:%d, c_rate:%d \n",
+				 flow_node->c_linkid, flow_node->c_weight, flow_node->c_sp,
+				 flow_node->c_rate);
+		LOG_INFO(" flow_node e_linkid:0x%x, e_weight:%d, e_sp:%d, e_rate:%d \n",
+				 flow_node->e_linkid, flow_node->e_weight, flow_node->e_sp,
+				 flow_node->e_rate);
+		flow_node = flow_node->flow_next;
+	}
+
+	return 0;
+}
+
+uint32_t zxdh_link_speed_to_index(uint32_t link_speed)
+{
+	// 50G以下统一按50G处理
+	//暂未使用RDMA端口
+	uint32_t index = ZXDH_TRPG_DEFAULT; // riscv上默认初值
+	if (link_speed == 200000) {
+		index = ZXDH_TRPG_SPEED_200G;
+	} else if (link_speed == 100000) {
+		index = ZXDH_TRPG_SPEED_100G;
+	} else {
+		index = ZXDH_TRPG_SPEED_50G;
+	}
+
+	return index;
+}
+
+DPP_PBU_PORT_TH_PARA_T port_th_para_tbl[ZXDH_TRPG_SPEED_NUM] = {
+	/*brief lif阈值  lif私有阈值  idma私有阈值  idma_th0 idma_th1 idma_th2
+       idma_th3 idma_th4 idma_th5 idma_th6 idma_th7*/
+	/*单位512byte,512代表芯片处理包粒度*/
+	{ 100, 140, 140, 110, 130, 150, 170, 190, 210, 230, 250 }, // 50G
+	{ 210, 280, 280, 180, 230, 280, 330, 380, 430, 480, 530 }, // 100G
+	{ 480, 560, 560, 370, 450, 550, 670, 770, 870, 970, 1070 }, // 200G
+	{ 1400, 0, 0, 1500, 1500, 1500, 1500, 1500, 1500, 1500, 1500 }, // 400G RDMA
+	{ 2036, 2000, 2000, 2100, 2100, 2100, 2100, 2100, 2100, 2100,
+	  2100 } // riscv上默认初始值
+};
+
+DPP_PBU_PORT_COS_TH_PARA_T port_cos_th_para_tbl[ZXDH_TRPG_SPEED_NUM] = {
+	/*单位512byte*/
+	{ { 100, 120, 140, 160, 180, 200, 220, 240 } }, // 50G
+	{ { 160, 210, 260, 310, 360, 410, 460, 510 } }, // 100G
+	{ { 320, 420, 480, 620, 720, 820, 920, 1020 } }, // 200G
+	{ { 1200, 1200, 2000, 2000, 2800, 2800, 2800, 2800 } }, // 400G RDMA
+	{ { 1650, 1700, 1750, 1800, 1850, 1900, 1950, 2000 } } // riscv上默认初始值
+};
+
+uint32_t flow_td_th_tbl[ZXDH_TRPG_SPEED_NUM][ZXDH_DCBNL_MAX_TRAFFIC_CLASS] = {
+	/*单位KB*/
+	{ 72, 119, 166, 213, 260, 306, 353, 400 }, // 50G 梯度47
+	{ 144, 207, 269, 332, 394, 457, 519, 582 }, // 100G 梯度63
+	{ 287, 365, 443, 521, 600, 678, 756, 834 }, // 200G 梯度78  最小560*512/1000
+	{ 375, 570, 766, 961, 1156, 1352, 1547, 1742 }, // 400G RDMA 梯度195
+	{ 150, 150, 150, 150, 150, 150, 150, 150 } // riscv上默认初始值
+};
+
+uint32_t zxdh_config_param_compare_test(
+		uint32_t tbl_index, DPP_PBU_PORT_TH_PARA_T port_th_para,
+		DPP_PBU_PORT_COS_TH_PARA_T port_cos_th_para, uint32_t *flow_td_th_para)
+{
+	uint32_t index = 0;
+	uint32_t *port_th_para_p1 = (uint32_t *)&port_th_para;
+	uint32_t *port_th_para_p2 = (uint32_t *)&port_cos_th_para_tbl[tbl_index];
+	for (index = 0; index < 11; index++) {
+		if (*(port_th_para_p1 + index) != *(port_th_para_p2 + index)) {
+			return false;
+		}
+	}
+	for (index = 0; index < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; index++) {
+		if ((port_cos_th_para.cos_th[index] !=
+			 port_cos_th_para_tbl[tbl_index].cos_th[index]) ||
+			(flow_td_th_para[index] != flow_td_th_tbl[tbl_index][index])) {
+			return false;
+		}
+	}
+	return true;
+}
+
+uint32_t zxdh_port_th_update(struct zxdh_en_device *en_dev)
+{
+	struct net_device *netdev = en_dev->netdev;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	// en_dev里面其实是包含link_speed的，填的是具体的速率值
+	uint32_t tbl_index;
+	uint32_t index;
+	uint32_t pfc_cur_mac_en = 0;
+	uint32_t ret = 0;
+	uint32_t speed = 0;
+	uint32_t max_speed = ZXDH_DCBNL_MAXRATE_KBITPS;
+	uint32_t params_check = 0;
+	DPP_PBU_PORT_TH_PARA_T port_th_para_test = { 0 };
+	DPP_PBU_PORT_COS_TH_PARA_T port_cos_th_para_test = { 0 };
+	DPP_TM_SHAPE_PP_PARA_T port_shape_para_test = { 0 };
+	uint32_t flow_td_th_para_test[ZXDH_DCBNL_MAX_TRAFFIC_CLASS] = { 0 };
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+	LOG_INFO("port speed en_dev->speed is abnormal: %d \n", en_dev->speed)
+
+	if (en_dev->speed) {
+		speed = en_dev->speed * ZXDH_DCBNL_RATEUNIT_K;
+	}
+
+	zxdh_en_fc_mode_get(en_dev, &pfc_cur_mac_en);
+	if (pfc_cur_mac_en == BIT(SPM_FC_NONE)) {
+		LOG_INFO("port pfc & fc disable");
+		return 0;
+	}
+
+	// speed过滤
+	if ((0 == speed) || (speed > max_speed)) {
+		LOG_INFO("port speed is abnormal: %u \n", speed);
+		speed = max_speed;
+	}
+	ret = dpp_port_shape_set(&pf_info, en_dev->phy_port, speed,
+							 ZXDH_DCBNL_PORT_RATE_CBS, 1);
+
+	if (en_dev->phy_port > 9) {
+		LOG_INFO("en_dev->phy_port not supported");
+		return 0;
+	}
+
+	tbl_index = zxdh_link_speed_to_index(en_dev->link_speed);
+
+	LOG_INFO("link_speed to tbl_index: %d", tbl_index);
+
+	if (pfc_cur_mac_en != BIT(SPM_FC_PAUSE_RX)) {
+		ret = dpp_port_th_set(&pf_info, en_dev->phy_port,
+							  port_th_para_tbl + tbl_index);
+
+		ret |= dpp_port_cos_th_set(&pf_info, en_dev->phy_port,
+								   port_cos_th_para_tbl + tbl_index);
+	}
+
+	//暂时规避fc下的td阈值改配
+	// if(pfc_cur_mac_en != BIT(SPM_FC_PAUSE_TX))
+	if (pfc_cur_mac_en == SPM_FC_PFC_FULL) {
+		ret |= zxdh_dcbnl_set_flow_td_th(en_priv, flow_td_th_tbl[tbl_index]);
+	}
+
+	/*维测需要*/
+	dpp_port_th_get(&pf_info, en_dev->phy_port, &port_th_para_test);
+	LOG_INFO("dpp_port_th_get lif_th:%d, lif_prv:%d, idma_prv:%d \n",
+			 port_th_para_test.lif_th, port_th_para_test.lif_prv,
+			 port_th_para_test.idma_prv);
+	LOG_INFO("idma_th0:%d, idma_th1:%d, idma_th2:%d, idma_th3:%d, idma_th4:%d, "
+			 "idma_th5:%d, idma_th6:%d, idma_th7:%d \n",
+			 port_th_para_test.idma_th_cos0, port_th_para_test.idma_th_cos1,
+			 port_th_para_test.idma_th_cos2, port_th_para_test.idma_th_cos3,
+			 port_th_para_test.idma_th_cos4, port_th_para_test.idma_th_cos5,
+			 port_th_para_test.idma_th_cos6, port_th_para_test.idma_th_cos7);
+
+	dpp_port_cos_th_get(&pf_info, en_dev->phy_port, &port_cos_th_para_test);
+	for (index = 0; index < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; index++) {
+		LOG_INFO("dpp_port_cos_th_get cos%d:%d\n", index,
+				 port_cos_th_para_test.cos_th[index]);
+	}
+	/*
+  LOG_INFO("dpp_port_cos_th_get cos0:%d, cos1:%d, cos2:%d, cos3:%d, cos4:%d,
+  cos5:%d, cos6:%d, cos7:%d",\
+  port_cos_th_para_test->cos_th[0], port_cos_th_para_test->cos_th[1],
+  port_cos_th_para_test->cos_th[2], port_cos_th_para_test->cos_th[3],\
+  port_cos_th_para_test->cos_th[4], port_cos_th_para_test->cos_th[6],
+  port_cos_th_para_test->cos_th[0], port_cos_th_para_test->cos_th[0], )
+  */
+	dpp_port_shape_get(&pf_info, en_dev->phy_port, &port_shape_para_test);
+	LOG_INFO("dpp_port_shape_get cir:%d, cbs:%d, c_en:%d\n",
+			 port_shape_para_test.cir, port_shape_para_test.cbs,
+			 port_shape_para_test.c_en);
+
+	zxdh_dcbnl_get_flow_td_th(en_priv, flow_td_th_para_test);
+	for (index = 0; index < ZXDH_DCBNL_MAX_TRAFFIC_CLASS; index++) {
+		LOG_INFO("zxdh_dcbnl_get_flow_td_th:tc_td_th[%d]:%d \n", index,
+				 flow_td_th_para_test[index]);
+	}
+
+	params_check = zxdh_config_param_compare_test(tbl_index, port_th_para_test,
+												  port_cos_th_para_test,
+												  flow_td_th_para_test);
+	if (params_check) {
+		LOG_INFO("th_params_check OK");
+	}
+
+	return ret;
+}
+
+uint32_t zxdh_port_th_update_to_default(struct zxdh_en_device *en_dev)
+{
+	struct net_device *netdev = en_dev->netdev;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	uint32_t ret = 0;
+	uint32_t pfc_cur_mac_en = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	zxdh_en_fc_mode_get(en_dev, &pfc_cur_mac_en);
+
+	if (pfc_cur_mac_en != BIT(SPM_FC_PAUSE_TX)) {
+		ret = dpp_port_th_set(&pf_info, en_dev->phy_port,
+							  port_th_para_tbl + ZXDH_TRPG_DEFAULT);
+
+		ret |= dpp_port_cos_th_set(&pf_info, en_dev->phy_port,
+								   port_cos_th_para_tbl + ZXDH_TRPG_DEFAULT);
+	}
+
+	if (pfc_cur_mac_en != BIT(SPM_FC_PAUSE_RX)) {
+		ret |= zxdh_dcbnl_set_flow_td_th(en_priv,
+										 flow_td_th_tbl[ZXDH_TRPG_DEFAULT]);
+	}
+
+	return ret;
+}
+
+uint32_t zxdh_dcbnl_pfc_init(struct zxdh_en_priv *en_priv)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t ret = 0;
+	uint32_t test_en = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	LOG_INFO("zxdh_dcbnl_pfc_init start\n");
+
+	ret = dpp_qmu_pfc_en_set(&pf_info, 1);
+
+	if (ret) {
+		LOG_ERR("dpp_qmu_pfc_en_set failed");
+	}
+
+	dpp_qmu_pfc_en_get(&pf_info, &test_en);
+	LOG_INFO("dpp_qmu_pfc_en_get:%d", test_en);
+	LOG_INFO("zxdh_dcbnl_pfc_init end\n");
+
+	return ret;
+}
+
+uint32_t zxdh_dcbnl_init_ets_scheduling_tree(struct zxdh_en_priv *en_priv)
+{
+	uint32_t err = 0;
+
+	zxdh_dcbnl_init_ets_list(en_priv);
+
+	err = zxdh_dcbnl_build_ets_scheduling_tree(en_priv);
+	if (err) {
+		LOG_ERR("dcbnl_init_ets: build_tc_scheduling_tree failed \n");
+		goto init_ets_se_error;
+	}
+
+	err = zxdh_dcbnl_scheduling_tree_link_tc(en_priv);
+	if (err) {
+		LOG_ERR("dcbnl_init_ets: scheduling_tree_link_tc failed \n");
+		goto init_ets_error;
+	}
+
+	err = zxdh_dcbnl_init_trust_and_table(en_priv);
+	if (err) {
+		LOG_ERR("dcbnl_init_ets: init_trust_and_table failed \n");
+		goto init_ets_error;
+	}
+
+	return 0;
+
+init_ets_error:
+	zxdh_dcbnl_free_flow_resources(en_priv);
+init_ets_se_error:
+	zxdh_dcbnl_free_se_resources(en_priv);
+	LOG_INFO("dcbnl_init_ets failed \n");
+	return err;
+}
+
+uint32_t zxdh_dcbnl_set_tm_gate(struct zxdh_en_priv *en_priv, uint32_t mode)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if (mode == 1) {
+		err = dpp_tm_pport_mcode_switch_set(&pf_info, en_dev->phy_port, 1);
+		if (err) {
+			LOG_ERR(" set_tm_gate open failed \n");
+		}
+	} else if (mode == 0) {
+		err = dpp_tm_pport_mcode_switch_del(&pf_info, en_dev->phy_port);
+		if (err) {
+			LOG_ERR(" set_tm_gate close failed \n");
+		}
+	} else {
+		LOG_ERR(" error \n");
+	}
+
+	return err;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl_api.h b/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl_api.h
index 485a377fbb734c7d0740385d38dc83b86a3d6e21..e7a649ecb99bab6e322806a344e4121967047668 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl_api.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/dcbnl/en_dcbnl_api.h
@@ -1,35 +1,39 @@
-#ifndef __ZXDH_EN_DCBNL_API_H__
-#define __ZXDH_EN_DCBNL_API_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/device.h>
-
-struct zxdh_en_priv;
-
-uint32_t zxdh_dcbnl_init_port_speed(struct zxdh_en_priv *en_priv);
-uint32_t zxdh_dcbnl_init_ets_scheduling_tree(struct zxdh_en_priv *en_priv);
-uint32_t zxdh_dcbnl_printk_ets_tree(struct zxdh_en_priv *en_priv);
-uint32_t zxdh_dcbnl_pfc_init(struct zxdh_en_priv *en_priv);
-
-uint32_t zxdh_dcbnl_free_flow_resources(struct zxdh_en_priv *en_priv);
-uint32_t zxdh_dcbnl_free_se_resources(struct zxdh_en_priv *en_priv);
-
-uint32_t zxdh_dcbnl_set_tc_scheduling(struct zxdh_en_priv *en_priv, uint8_t *tc_type, uint8_t *tc_tx_bw);
-uint32_t zxdh_dcbnl_set_ets_up_tc_map(struct zxdh_en_priv *en_priv, uint8_t *prio_tc);
-uint32_t zxdh_dcbnl_set_tc_maxrate(struct zxdh_en_priv *en_priv, uint32_t *maxrate);
-uint32_t zxdh_dcbnl_set_ets_trust(struct zxdh_en_priv *en_priv, uint32_t trust);
-uint32_t zxdh_dcbnl_set_dscp2prio(struct zxdh_en_priv *en_priv, uint16_t dscp, uint8_t prio);
-
-uint32_t zxdh_port_th_update(struct zxdh_en_device *en_dev);
-uint32_t zxdh_port_th_update_to_default(struct zxdh_en_device *en_dev);
-
-uint32_t zxdh_dcbnl_set_tm_gate(struct zxdh_en_priv *en_priv, uint32_t mode);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef __ZXDH_EN_DCBNL_API_H__
+#define __ZXDH_EN_DCBNL_API_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/device.h>
+
+struct zxdh_en_priv;
+
+uint32_t zxdh_dcbnl_init_port_speed(struct zxdh_en_priv *en_priv);
+uint32_t zxdh_dcbnl_init_ets_scheduling_tree(struct zxdh_en_priv *en_priv);
+uint32_t zxdh_dcbnl_printk_ets_tree(struct zxdh_en_priv *en_priv);
+uint32_t zxdh_dcbnl_pfc_init(struct zxdh_en_priv *en_priv);
+
+uint32_t zxdh_dcbnl_free_flow_resources(struct zxdh_en_priv *en_priv);
+uint32_t zxdh_dcbnl_free_se_resources(struct zxdh_en_priv *en_priv);
+
+uint32_t zxdh_dcbnl_set_tc_scheduling(struct zxdh_en_priv *en_priv,
+									  uint8_t *tc_type, uint8_t *tc_tx_bw);
+uint32_t zxdh_dcbnl_set_ets_up_tc_map(struct zxdh_en_priv *en_priv,
+									  uint8_t *prio_tc);
+uint32_t zxdh_dcbnl_set_tc_maxrate(struct zxdh_en_priv *en_priv,
+								   uint32_t *maxrate);
+uint32_t zxdh_dcbnl_set_ets_trust(struct zxdh_en_priv *en_priv, uint32_t trust);
+uint32_t zxdh_dcbnl_set_dscp2prio(struct zxdh_en_priv *en_priv, uint16_t dscp,
+								  uint8_t prio);
+
+uint32_t zxdh_port_th_update(struct zxdh_en_device *en_dev);
+uint32_t zxdh_port_th_update_to_default(struct zxdh_en_device *en_dev);
+
+uint32_t zxdh_dcbnl_set_tm_gate(struct zxdh_en_priv *en_priv, uint32_t mode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/drs_sec_dtb.c b/src/net/drivers/net/ethernet/dinghai/en_aux/drs_sec_dtb.c
old mode 100755
new mode 100644
index 150b79f0de0c11143c993a4abfb018bd28a8317f..f48dacd8e6a64dc6a456fd042adc6c05cec6873c
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/drs_sec_dtb.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/drs_sec_dtb.c
@@ -20,7 +20,6 @@
 #include <linux/delay.h>
 #include <linux/scatterlist.h>
 #include <linux/dma-mapping.h>
-
 #include <linux/netdevice.h>
 #include <linux/pfkeyv2.h>
 #include <net/xfrm.h>
@@ -28,1033 +27,1012 @@
 #include "../en_aux.h"
 #include "drs_sec_dtb.h"
 
-
-
-UINT32 g_udDownloadSaNum = 1;     //sa表的数量
-UINT32 gudTunnelID = 0;
+UINT32 g_udDownloadSaNum = 1; // sa表的数量
+UINT32 gudTunnelID;
 UINT32 gudDtbSaNum = 1;
-E_INLINE_TYPE e_gInlineType = 0;  //0是inline入境 1是inline出境
-UINT64 guddAntiWindow = 2047;   //得配成2047，否则覆盖不到sn为0的情况
+E_INLINE_TYPE e_gInlineType; // 0是inline入境 1是inline出境
+UINT64 guddAntiWindow = 2047; //得配成2047，否则覆盖不到sn为0的情况
 
-UINT64 guddSecTestSaDtbPdVirAddr = 0;
+UINT64 guddSecTestSaDtbPdVirAddr;
 
 UINT32 gudSecTestSwanSrcIp = 0x0A04B007;
 UINT32 gudSecTestSwanDstIp = 0x0AE3656D;
 
-UINT8  gudIpType = 1;
+UINT8 gudIpType = 1;
 // 出入境分开下表需要将此字段置0，会影响入境下表
-UINT16 gusOutSaOffset=0;
-UINT32 gudOutSaId=0;
-
+UINT16 gusOutSaOffset;
+UINT32 gudOutSaId;
 
 UINT64 HalBttlSecRegBaseGet(struct zxdh_en_device *en_dev)
 {
-    PUB_CHECK_NULL_PTR_RET_ERR(en_dev);
-    return en_dev->ops->get_bar_virt_addr(en_dev->parent, 0) + 0x7000;   //0x7000是目前sec模块寄存器基地址的固定偏移,包括PF/VF
+	PUB_CHECK_NULL_PTR_RET_ERR(en_dev);
+	return en_dev->ops->get_bar_virt_addr(en_dev->parent, 0) +
+		   0x7000; // 0x7000是目前sec模块寄存器基地址的固定偏移,包括PF/VF
 }
 
-
 #if 1
-static int zxdh_ipsec_cipher_id_get(u8 ealgo, char* p_alg_name,char* p_aead_name,E_HAL_SEC_IPSEC_CIPHER_ALG *p_zxdh_ealgo_id)
+static int zxdh_ipsec_cipher_id_get(u8 ealgo, char *p_alg_name,
+									char *p_aead_name,
+									E_HAL_SEC_IPSEC_CIPHER_ALG *p_zxdh_ealgo_id)
 {
-    int i = 0;
-    T_ZXDH_EALGO atZxdhEalgo[] =
-    {
-        {"rfc7539esp(chacha20,poly1305)","",e_HAL_IPSEC_CIPHER_CHACHA},
-    };
-
-    if((NULL == p_alg_name)||(NULL == p_aead_name))
-    {
-        return -1;
-    }
-    for(i=0;i<sizeof(atZxdhEalgo)/sizeof(T_ZXDH_EALGO);i++)
-    {
-        if((0 == strcmp(p_alg_name,atZxdhEalgo[i].alg_name))||(0 == strcmp(p_alg_name,atZxdhEalgo[i].compat_name)))
-        {
-            *p_zxdh_ealgo_id = atZxdhEalgo[i].e_zxdh_ealgo_id;
-            return 0;
-        }
-        if((0 == strcmp(p_aead_name,atZxdhEalgo[i].alg_name))||(0 == strcmp(p_aead_name,atZxdhEalgo[i].compat_name)))
-        {
-            *p_zxdh_ealgo_id = atZxdhEalgo[i].e_zxdh_ealgo_id;
-            return 0;
-        }
-    }
-
-    switch (ealgo) {
-    case SADB_EALG_NULL:
-    case SADB_EALG_NONE:
-        *p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_NULL;
-        break;
-    case SADB_EALG_DESCBC:
-        *p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_DES_CBC;
-        break;
-    case SADB_EALG_3DESCBC:
-        *p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_3DES_CBC;
-        break;
-    case SADB_X_EALG_AESCBC:
-        *p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_CBC;
-        break;
-    case SADB_X_EALG_AESCTR:
-        *p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_CTR;
-        break;
-    case SADB_X_EALG_AES_CCM_ICV8:
-        *p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_CCM;
-        break;
-    case SADB_X_EALG_AES_CCM_ICV12:
-        *p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_CCM;
-        break;
-    case SADB_X_EALG_AES_CCM_ICV16:
-        *p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_CCM;
-        break;
-    case SADB_X_EALG_AES_GCM_ICV8:
-        *p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_GCM;
-	break;
-    case SADB_X_EALG_AES_GCM_ICV12:
-        *p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_GCM;
-        break;
-    case SADB_X_EALG_AES_GCM_ICV16:
-        *p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_GCM;
-        break;
-    case SADB_X_EALG_NULL_AES_GMAC:
-        *p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_GMAC;
-        break;
-        #if 0
-        //5.13不支持
-    case SADB_X_EALG_SM4CBC:
-        *p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_SM4_CBC;
-        break;
-        #endif
-    default:
-        return -1;
-    }
-
-    return 0;
+	int i = 0;
+	T_ZXDH_EALGO atZxdhEalgo[] = {
+		{ "rfc7539esp(chacha20,poly1305)", "", e_HAL_IPSEC_CIPHER_CHACHA },
+	};
+
+	if ((NULL == p_alg_name) || (NULL == p_aead_name)) {
+		return -1;
+	}
+	for (i = 0; i < sizeof(atZxdhEalgo) / sizeof(T_ZXDH_EALGO); i++) {
+		if ((0 == strcmp(p_alg_name, atZxdhEalgo[i].alg_name)) ||
+			(0 == strcmp(p_alg_name, atZxdhEalgo[i].compat_name))) {
+			*p_zxdh_ealgo_id = atZxdhEalgo[i].e_zxdh_ealgo_id;
+			return 0;
+		}
+		if ((0 == strcmp(p_aead_name, atZxdhEalgo[i].alg_name)) ||
+			(0 == strcmp(p_aead_name, atZxdhEalgo[i].compat_name))) {
+			*p_zxdh_ealgo_id = atZxdhEalgo[i].e_zxdh_ealgo_id;
+			return 0;
+		}
+	}
+
+	switch (ealgo) {
+	case SADB_EALG_NULL:
+	case SADB_EALG_NONE:
+		*p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_NULL;
+		break;
+	case SADB_EALG_DESCBC:
+		*p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_DES_CBC;
+		break;
+	case SADB_EALG_3DESCBC:
+		*p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_3DES_CBC;
+		break;
+	case SADB_X_EALG_AESCBC:
+		*p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_CBC;
+		break;
+	case SADB_X_EALG_AESCTR:
+		*p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_CTR;
+		break;
+	case SADB_X_EALG_AES_CCM_ICV8:
+		*p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_CCM;
+		break;
+	case SADB_X_EALG_AES_CCM_ICV12:
+		*p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_CCM;
+		break;
+	case SADB_X_EALG_AES_CCM_ICV16:
+		*p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_CCM;
+		break;
+	case SADB_X_EALG_AES_GCM_ICV8:
+		*p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_GCM;
+		break;
+	case SADB_X_EALG_AES_GCM_ICV12:
+		*p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_GCM;
+		break;
+	case SADB_X_EALG_AES_GCM_ICV16:
+		*p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_GCM;
+		break;
+	case SADB_X_EALG_NULL_AES_GMAC:
+		*p_zxdh_ealgo_id = e_HAL_IPSEC_CIPHER_AES_GMAC;
+		break;
+	default:
+		return -1;
+	}
+
+	return 0;
 }
 
-static int zxdh_ipsec_auth_id_get(u8 aalgo,char* p_alg_name,E_HAL_SEC_IPSEC_AUTH_ALG *p_zxdh_auth_id)
+static int zxdh_ipsec_auth_id_get(u8 aalgo, char *p_alg_name,
+								  E_HAL_SEC_IPSEC_AUTH_ALG *p_zxdh_auth_id)
 {
-    int i = 0;
-    T_ZXDH_ALGO atZxdhAlgo[] =
-    {
-        {"cmac(aes)","",e_HAL_IPSEC_AUTH_AES_CMAC32},
-    };
-
-    if(NULL == p_alg_name)
-    {
-        return -1;
-    }
-    for(i=0;i<sizeof(atZxdhAlgo)/sizeof(T_ZXDH_ALGO);i++)
-    {
-        DH_LOG_INFO(MODULE_SEC, "%s\n",p_alg_name);
-        DH_LOG_INFO(MODULE_SEC, "%s\n",atZxdhAlgo[i].alg_name);
-        if((0 == strcmp(p_alg_name,atZxdhAlgo[i].alg_name))||(0 == strcmp(p_alg_name,atZxdhAlgo[i].compat_name)))
-        {
-            *p_zxdh_auth_id = atZxdhAlgo[i].e_zxdh_auth_id;
-            return 0;
-        }
-    }
-
-    switch (aalgo) {
-    case SADB_X_AALG_NULL:
-    case SADB_AALG_NONE:
-        *p_zxdh_auth_id = e_HAL_IPSEC_AUTH_NULL;
-        break;
-    case SADB_AALG_MD5HMAC:
-        *p_zxdh_auth_id = e_HAL_IPSEC_AUTH_AES_MD5;
-        break;
-    case SADB_AALG_SHA1HMAC:
-        *p_zxdh_auth_id = e_HAL_IPSEC_AUTH_AES_SHA1;
-        break;
-    case SADB_X_AALG_SHA2_256HMAC:
-        *p_zxdh_auth_id = e_HAL_IPSEC_AUTH_AES_SHA256;
-        break;
-    case SADB_X_AALG_SHA2_384HMAC:
-        *p_zxdh_auth_id = e_HAL_IPSEC_AUTH_AES_SHA384;
-        break;
-    case SADB_X_AALG_SHA2_512HMAC:
-        *p_zxdh_auth_id = e_HAL_IPSEC_AUTH_AES_SHA512;
-        break;
-    case SADB_X_AALG_AES_XCBC_MAC:
-        *p_zxdh_auth_id = e_HAL_IPSEC_AUTH_AES_XCBCMAC;
-        break;
-        #if 0
-        //5.13不支持
-    case SADB_X_AALG_SM3_256HMAC:
-        *p_zxdh_auth_id = e_HAL_IPSEC_AUTH_SM3;    /*不清楚对不对*/
-        break;
-        #endif
-    default:
-        return -1;
-    }
-
-    return 0;
+	int i = 0;
+	T_ZXDH_ALGO atZxdhAlgo[] = {
+		{ "cmac(aes)", "", e_HAL_IPSEC_AUTH_AES_CMAC32 },
+	};
+
+	if (NULL == p_alg_name) {
+		return -1;
+	}
+	for (i = 0; i < sizeof(atZxdhAlgo) / sizeof(T_ZXDH_ALGO); i++) {
+		DH_LOG_INFO(MODULE_SEC, "%s\n", p_alg_name);
+		DH_LOG_INFO(MODULE_SEC, "%s\n", atZxdhAlgo[i].alg_name);
+		if ((0 == strcmp(p_alg_name, atZxdhAlgo[i].alg_name)) ||
+			(0 == strcmp(p_alg_name, atZxdhAlgo[i].compat_name))) {
+			*p_zxdh_auth_id = atZxdhAlgo[i].e_zxdh_auth_id;
+			return 0;
+		}
+	}
+
+	switch (aalgo) {
+	case SADB_X_AALG_NULL:
+	case SADB_AALG_NONE:
+		*p_zxdh_auth_id = e_HAL_IPSEC_AUTH_NULL;
+		break;
+	case SADB_AALG_MD5HMAC:
+		*p_zxdh_auth_id = e_HAL_IPSEC_AUTH_AES_MD5;
+		break;
+	case SADB_AALG_SHA1HMAC:
+		*p_zxdh_auth_id = e_HAL_IPSEC_AUTH_AES_SHA1;
+		break;
+	case SADB_X_AALG_SHA2_256HMAC:
+		*p_zxdh_auth_id = e_HAL_IPSEC_AUTH_AES_SHA256;
+		break;
+	case SADB_X_AALG_SHA2_384HMAC:
+		*p_zxdh_auth_id = e_HAL_IPSEC_AUTH_AES_SHA384;
+		break;
+	case SADB_X_AALG_SHA2_512HMAC:
+		*p_zxdh_auth_id = e_HAL_IPSEC_AUTH_AES_SHA512;
+		break;
+	case SADB_X_AALG_AES_XCBC_MAC:
+		*p_zxdh_auth_id = e_HAL_IPSEC_AUTH_AES_XCBCMAC;
+		break;
+	default:
+		return -1;
+	}
+
+	return 0;
 }
 
-UINT32 CmdkBttlSecSaParamConstruct(UINT32 udEntryValid,E_CMDK_SEC_IPSEC_MODE eTunnelMode,UINT32 udSeqCnterOverflow,E_CMDK_LIVETIME_TYPES eLiveTimeType,E_CMDK_SEC_SA_DF_MODE eSaDfMode,E_CMDK_SEC_ENCRYP_MODE eEncryptionMode,UINT32 udIcvLen,UINT16* pusSaParam)
+UINT32 CmdkBttlSecSaParamConstruct(UINT32 udEntryValid,
+								   E_CMDK_SEC_IPSEC_MODE eTunnelMode,
+								   UINT32 udSeqCnterOverflow,
+								   E_CMDK_LIVETIME_TYPES eLiveTimeType,
+								   E_CMDK_SEC_SA_DF_MODE eSaDfMode,
+								   E_CMDK_SEC_ENCRYP_MODE eEncryptionMode,
+								   UINT32 udIcvLen, UINT16 *pusSaParam)
 {
-    UINT32 udIcvLenNew = udIcvLen / 4;  //以4字节为单位
+	UINT32 udIcvLenNew = udIcvLen / 4; //以4字节为单位
 
-    BTTL_PUB_ID_CHECK(udEntryValid,BITWIDTH1+1);
-    BTTL_PUB_ID_CHECK(eTunnelMode,e_SEC_IPSEC_MODE_LAST);
-    BTTL_PUB_ID_CHECK(udSeqCnterOverflow,BITWIDTH1+1);
-    BTTL_PUB_ID_CHECK(eLiveTimeType,e_SEC_SA_LIVETIME_TYPE_LAST);
-    BTTL_PUB_ID_CHECK(eSaDfMode,e_SEC_SA_DF_MODE_LAST);
-    BTTL_PUB_ID_CHECK(eEncryptionMode,e_SEC_ENCRYP_MODE_LAST);
-    BTTL_PUB_ID_CHECK(udIcvLenNew,BITWIDTH6+1);
+	BTTL_PUB_ID_CHECK(udEntryValid, BITWIDTH1 + 1);
+	BTTL_PUB_ID_CHECK(eTunnelMode, e_SEC_IPSEC_MODE_LAST);
+	BTTL_PUB_ID_CHECK(udSeqCnterOverflow, BITWIDTH1 + 1);
+	BTTL_PUB_ID_CHECK(eLiveTimeType, e_SEC_SA_LIVETIME_TYPE_LAST);
+	BTTL_PUB_ID_CHECK(eSaDfMode, e_SEC_SA_DF_MODE_LAST);
+	BTTL_PUB_ID_CHECK(eEncryptionMode, e_SEC_ENCRYP_MODE_LAST);
+	BTTL_PUB_ID_CHECK(udIcvLenNew, BITWIDTH6 + 1);
 
-    //BTTL_PUB_NULL_CHECK(pusSaParam);
+	// BTTL_PUB_NULL_CHECK(pusSaParam);
 
-    *pusSaParam = udIcvLenNew|(eEncryptionMode<<6)|(eSaDfMode<<9)|(eLiveTimeType<<11)|(udSeqCnterOverflow<<13)|(eTunnelMode<<14)|(udEntryValid<<15);
+	*pusSaParam = udIcvLenNew | (eEncryptionMode << 6) | (eSaDfMode << 9) |
+				  (eLiveTimeType << 11) | (udSeqCnterOverflow << 13) |
+				  (eTunnelMode << 14) | (udEntryValid << 15);
 
-    return 0;
+	return 0;
 }
-static int zxdh_ipsec_dtb_out_sa_get(struct xfrm_state *xs,T_HAL_SA_DTB_HW_OUT* ptDtbOutSa)
+static int zxdh_ipsec_dtb_out_sa_get(struct xfrm_state *xs,
+									 T_HAL_SA_DTB_HW_OUT *ptDtbOutSa)
 {
-    int err = -EINVAL;
-    u16 usSaParam = 0;
-    u32 udIcvLen = 0;
-    E_HAL_SEC_IPSEC_AUTH_ALG zxdh_auth_id;
-    E_HAL_SEC_IPSEC_CIPHER_ALG zxdh_ealgo_id;
-    E_CMDK_SEC_ENCRYP_MODE zxdh_encpy_mode = e_SEC_ENCRYP_MODE_LAST;
-    char test_alg_name[] = "zxdh_alg_test";
-    char* p_aalg_alg_name = test_alg_name;
-    char* p_ealg_alg_name = test_alg_name;
-    char* p_aead_alg_name = test_alg_name;
-
-    if(NULL != xs->aalg)
-    {
-        p_aalg_alg_name = xs->aalg->alg_name;
-    }
-    if(NULL != xs->ealg)
-    {
-        p_ealg_alg_name = xs->ealg->alg_name;
-    }
-    if(NULL != xs->aead)
-    {
-        p_aead_alg_name = xs->aead->alg_name;
-    }
-
-    /*AH应该提前拦截*/
-    /*空加密空认证应该提前拦截*/
-
-    //DH_LOG_INFO(MODULE_SEC, "xs:0x%llx\n",xs);
-    //DH_LOG_INFO(MODULE_SEC, "ptDtbOutSa:0x%llx\n",ptDtbOutSa);
-    /*应该和pcs的思路一样  ,mlx5e_xfrm_validate_state 参数校验里去把sa的赋值做了*/
-
-    err = zxdh_ipsec_auth_id_get(xs->props.aalgo,p_aalg_alg_name,&zxdh_auth_id);
-    if (err) {
-        DH_LOG_INFO(MODULE_SEC, "Cannot offload xfrm state aalgo:%u\n",xs->props.aalgo);
-        return -EINVAL;
-    }
-    err = zxdh_ipsec_cipher_id_get(xs->props.ealgo,p_ealg_alg_name,p_aead_alg_name,&zxdh_ealgo_id);
-    if (err) {
-        DH_LOG_INFO(MODULE_SEC, "Cannot offload xfrm state ealgo:%u\n",xs->props.aalgo);
-        return -EINVAL;
-    }
-
-    //DH_LOG_INFO(MODULE_SEC, "replay_esn 0x%llx\n",xs->replay_esn);
-    ptDtbOutSa->ucAuthkeyLen       = 0;    /*默认值*/
-
-    /*处理单认证算法*/
-    if(zxdh_auth_id == e_HAL_IPSEC_AUTH_NULL)
-    {
-        zxdh_encpy_mode = e_SEC_ENCRYP_ESP_ENCRYP_MODE;
-    }
-    else
-    {
-        ptDtbOutSa->ucAuthkeyLen       = (xs->aalg->alg_key_len + 7)/8;
-        udIcvLen = (xs->aalg->alg_trunc_len + 7)/8;
-        memcpy((ptDtbOutSa->aucSaAuthKey),xs->aalg->alg_key,ptDtbOutSa->ucAuthkeyLen);
-    }
-
-    if((zxdh_ealgo_id != e_HAL_IPSEC_CIPHER_NULL)&&(zxdh_auth_id != e_HAL_IPSEC_AUTH_NULL))
-    {
-        zxdh_encpy_mode = e_SEC_ENCRYP_ESP_AUTH_AND_ESP_ENCRYP_MODE;
-    }
-    /*这里处理组合算法的4字节的salt*/
-    if((zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_GCM)||(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_CHACHA)||(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_GMAC))
-    {
-        zxdh_encpy_mode = e_SEC_ENCRYP_ESP_COMBINED_MODE;
-
-        ptDtbOutSa->ucCipherkeyLen     = (xs->aead->alg_key_len + 7)/8 - 4;
-        udIcvLen = (xs->aead->alg_icv_len+ 7)/8;
-        memcpy(&(ptDtbOutSa->udSalt), xs->aead->alg_key + ptDtbOutSa->ucCipherkeyLen,sizeof(ptDtbOutSa->udSalt));
-        memcpy((ptDtbOutSa->aucSaCipherKey),xs->aead->alg_key,ptDtbOutSa->ucCipherkeyLen);
-    }
-    /*这里处理组合算法CCM,CCM的salt是3B*/
-    else if(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_CCM)
-    {
-        zxdh_encpy_mode = e_SEC_ENCRYP_ESP_COMBINED_MODE;
-
-        ptDtbOutSa->ucCipherkeyLen     = (xs->aead->alg_key_len + 7)/8 - 3;
-        udIcvLen = (xs->aead->alg_icv_len+ 7)/8;
-        memcpy(&(ptDtbOutSa->udSalt), xs->aead->alg_key + ptDtbOutSa->ucCipherkeyLen,sizeof(ptDtbOutSa->udSalt));
-        memcpy((ptDtbOutSa->aucSaCipherKey),xs->aead->alg_key,ptDtbOutSa->ucCipherkeyLen);
-    }
-    /*这里处理有salt的单加密算法CTR,salt是4B*/
-    else if(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_CTR)
-    {
-        ptDtbOutSa->ucCipherkeyLen     = (xs->ealg->alg_key_len + 7)/8 - 4;
-        memcpy(&(ptDtbOutSa->udSalt), xs->ealg->alg_key + ptDtbOutSa->ucCipherkeyLen,sizeof(ptDtbOutSa->udSalt));
-        memcpy((ptDtbOutSa->aucSaCipherKey),xs->ealg->alg_key,ptDtbOutSa->ucCipherkeyLen);
-    }
-    /*空加密算法*/
-    else if(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_NULL)
-    {
-        zxdh_encpy_mode = e_SEC_ENCRYP_ESP_AUTH_MODE;
-        ptDtbOutSa->ucCipherkeyLen     = 0;
-    }
-    /*单加密算法,且没有salt*/
-    else
-    {
-        ptDtbOutSa->ucCipherkeyLen     = (xs->ealg->alg_key_len + 7)/8;
-        memcpy((ptDtbOutSa->aucSaCipherKey),xs->ealg->alg_key,ptDtbOutSa->ucCipherkeyLen);
-    }
-
-
-    ptDtbOutSa->udSN                = xs->replay.oseq;
-    ptDtbOutSa->uddProcessedByteCnt = xs->curlft.bytes;   //PUB_HTON64(uddProcessedByteCnt);   //没法设置,用于构造iv,  一般都是用seq构造的iv
-
-    ptDtbOutSa->udSPI          = xs->id.spi;
-    ptDtbOutSa->udSaId        = PUB_HTON32(0x80001);                //PUB_HTON32(udSaId);                             /*这个要软件自己管理,需要设计一下*/
-
-    ptDtbOutSa->ucCiperID      = zxdh_ealgo_id;
-    ptDtbOutSa->ucAuthID       = zxdh_auth_id;
-
-    //CmdkBttlSecSaParamConstruct(UINT32 udEntryValid,E_CMDK_SEC_IPSEC_MODE eTunnelMode,UINT32 udSeqCnterOverflow,E_CMDK_LIVETIME_TYPES eLiveTimeType,E_CMDK_SEC_SA_DF_MODE eSaDfMode,E_CMDK_SEC_ENCRYP_MODE eEncryptionMode,UINT32 udIcvLen,UINT16* pusSaParam)
-    //E_CMDK_SEC_ENCRYP_MODE 这个只能根据算法反推 gcm ccm gmac chacha是combine  gaucSecSwanIpv6Data
-    //udIcvLen
-    //mode的定义刚好一样E_CMDK_SEC_IPSEC_MODE ,   XFRM_MODE_TRANSPORT
-    /*这个地方还要根据算法做个转换  e_SEC_ENCRYP_ESP_COMBINED_MODE  暂时用GCM*/
-    CmdkBttlSecSaParamConstruct(1,xs->props.mode,0,e_SEC_SA_LIVETIME_TIME_TYPE,e_SEC_SA_DF_BYPASS_MODE,zxdh_encpy_mode,udIcvLen,&usSaParam);
-    ptDtbOutSa->usSaParam      = PUB_HTON16(usSaParam);
-
-
-
-    ptDtbOutSa->usFrag_State   = PUB_HTON16(0xd2c8);
-
-    ptDtbOutSa->udLifetimeSecMax  = PUB_HTON32(0xc4454766);
-    ptDtbOutSa->uddLifetimByteCntMax      = PUB_HTON64(0xffffffffffffffff);
-
-    ptDtbOutSa->ucProtocol     = xs->id.proto;     //50esp协议 51ah
-    ptDtbOutSa->ucTOS          = 0xbb;
-
-    /*esn相关*/
-    ptDtbOutSa->ucEsnFlag  = 0;  /* 默认是非ESN模式 */
-    if(xs->props.flags & XFRM_STATE_ESN)
-    {
-        if(NULL == xs->replay_esn)
-            return 1;
-        ptDtbOutSa->ucEsnFlag    = 0xff; //ucEsnFlag;    //0xff表示开启ESN,否则不开启
-        ptDtbOutSa->udSN         = xs->replay_esn->oseq;
-        ptDtbOutSa->udESN        = xs->replay_esn->oseq_hi; /*不需要考虑replay_esn为null的情况?*/
-    }
-
-    /*ipv4*/
-    if(AF_INET == xs->props.family)
-    {
-        ptDtbOutSa->ucIpType     = 1<<6;   //bit[7:6] 1:ivp4 2:ipv6    /*换成宏*/
-        ptDtbOutSa->udSrcAddress0  = xs->props.saddr.a4;
-        ptDtbOutSa->udSrcAddress1  = 0x0;
-        ptDtbOutSa->udSrcAddress2  = 0x0;
-        ptDtbOutSa->udSrcAddress3  = 0x0;
-
-        ptDtbOutSa->udDstAddress0  = xs->id.daddr.a4;
-        ptDtbOutSa->udDstAddress1  = 0x0;
-        ptDtbOutSa->udDstAddress2  = 0x0;
-        ptDtbOutSa->udDstAddress3  = 0x0;
-    }
-    /*ipv4*/
-    else if(AF_INET6 == xs->props.family)
-    {
-        ptDtbOutSa->ucIpType     = 2<<6;   //bit[7:6] 1:ivp4 2:ipv6    /*换成宏*/
-        ptDtbOutSa->udSrcAddress0  = xs->props.saddr.a6[0];
-        ptDtbOutSa->udSrcAddress1  = xs->props.saddr.a6[1];
-        ptDtbOutSa->udSrcAddress2  = xs->props.saddr.a6[2];
-        ptDtbOutSa->udSrcAddress3  = xs->props.saddr.a6[3];
-
-        ptDtbOutSa->udDstAddress0  = xs->id.daddr.a6[0];
-        ptDtbOutSa->udDstAddress1  = xs->id.daddr.a6[1];
-        ptDtbOutSa->udDstAddress2  = xs->id.daddr.a6[2];
-        ptDtbOutSa->udDstAddress3  = xs->id.daddr.a6[3];
-    }
-    else
-    {
-        return -EINVAL;  /*不可能走到这里,前面函数已经校验过了*/
-    }
-
-    ptDtbOutSa->udRSV0       = 0x0;
-    ptDtbOutSa->udRSV1       = 0x0;
-    ptDtbOutSa->udRSV2       = 0x0;
-
-    DH_LOG_INFO(MODULE_SEC, "ptDtbOutSa->ucAuthkeyLen:0x%x\n",ptDtbOutSa->ucAuthkeyLen);
-    DH_LOG_INFO(MODULE_SEC, "ptDtbOutSa->ucCipherkeyLen:0x%x\n",ptDtbOutSa->ucCipherkeyLen);
-    DH_LOG_INFO(MODULE_SEC, "zxdh_encpy_mode:0x%x\n",zxdh_encpy_mode);
-    DH_LOG_INFO(MODULE_SEC, "ptDtbOutSa->ucCiperID:0x%x\n",ptDtbOutSa->ucCiperID);
-    DH_LOG_INFO(MODULE_SEC, "ptDtbOutSa->ucAuthID:0x%x\n",ptDtbOutSa->ucAuthID);
-
-
-    return 0;
+	int err = -EINVAL;
+	u16 usSaParam = 0;
+	u32 udIcvLen = 0;
+	E_HAL_SEC_IPSEC_AUTH_ALG zxdh_auth_id;
+	E_HAL_SEC_IPSEC_CIPHER_ALG zxdh_ealgo_id;
+	E_CMDK_SEC_ENCRYP_MODE zxdh_encpy_mode = e_SEC_ENCRYP_MODE_LAST;
+	char test_alg_name[] = "zxdh_alg_test";
+	char *p_aalg_alg_name = test_alg_name;
+	char *p_ealg_alg_name = test_alg_name;
+	char *p_aead_alg_name = test_alg_name;
+
+	if (NULL != xs->aalg) {
+		p_aalg_alg_name = xs->aalg->alg_name;
+	}
+	if (NULL != xs->ealg) {
+		p_ealg_alg_name = xs->ealg->alg_name;
+	}
+	if (NULL != xs->aead) {
+		p_aead_alg_name = xs->aead->alg_name;
+	}
+
+	/*AH应该提前拦截*/
+	/*空加密空认证应该提前拦截*/
+
+	// DH_LOG_INFO(MODULE_SEC, "xs:0x%llx\n",xs);
+	// DH_LOG_INFO(MODULE_SEC, "ptDtbOutSa:0x%llx\n",ptDtbOutSa);
+	/*应该和pcs的思路一样  ,mlx5e_xfrm_validate_state 参数校验里去把sa的赋值做了*/
+
+	err = zxdh_ipsec_auth_id_get(xs->props.aalgo, p_aalg_alg_name,
+								 &zxdh_auth_id);
+	if (err) {
+		DH_LOG_INFO(MODULE_SEC, "Cannot offload xfrm state aalgo:%u\n",
+					xs->props.aalgo);
+		return -EINVAL;
+	}
+	err = zxdh_ipsec_cipher_id_get(xs->props.ealgo, p_ealg_alg_name,
+								   p_aead_alg_name, &zxdh_ealgo_id);
+	if (err) {
+		DH_LOG_INFO(MODULE_SEC, "Cannot offload xfrm state ealgo:%u\n",
+					xs->props.aalgo);
+		return -EINVAL;
+	}
+
+	// DH_LOG_INFO(MODULE_SEC, "replay_esn 0x%llx\n",xs->replay_esn);
+	ptDtbOutSa->ucAuthkeyLen = 0; /*默认值*/
+
+	/*处理单认证算法*/
+	if (zxdh_auth_id == e_HAL_IPSEC_AUTH_NULL) {
+		zxdh_encpy_mode = e_SEC_ENCRYP_ESP_ENCRYP_MODE;
+	} else {
+		ptDtbOutSa->ucAuthkeyLen = (xs->aalg->alg_key_len + 7) / 8;
+		udIcvLen = (xs->aalg->alg_trunc_len + 7) / 8;
+		memcpy((ptDtbOutSa->aucSaAuthKey), xs->aalg->alg_key,
+			   ptDtbOutSa->ucAuthkeyLen);
+	}
+
+	if ((zxdh_ealgo_id != e_HAL_IPSEC_CIPHER_NULL) &&
+		(zxdh_auth_id != e_HAL_IPSEC_AUTH_NULL)) {
+		zxdh_encpy_mode = e_SEC_ENCRYP_ESP_AUTH_AND_ESP_ENCRYP_MODE;
+	}
+	/*这里处理组合算法的4字节的salt*/
+	if ((zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_GCM) ||
+		(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_CHACHA) ||
+		(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_GMAC)) {
+		zxdh_encpy_mode = e_SEC_ENCRYP_ESP_COMBINED_MODE;
+
+		ptDtbOutSa->ucCipherkeyLen = (xs->aead->alg_key_len + 7) / 8 - 4;
+		udIcvLen = (xs->aead->alg_icv_len + 7) / 8;
+		memcpy(&(ptDtbOutSa->udSalt),
+			   xs->aead->alg_key + ptDtbOutSa->ucCipherkeyLen,
+			   sizeof(ptDtbOutSa->udSalt));
+		memcpy((ptDtbOutSa->aucSaCipherKey), xs->aead->alg_key,
+			   ptDtbOutSa->ucCipherkeyLen);
+	}
+	/*这里处理组合算法CCM,CCM的salt是3B*/
+	else if (zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_CCM) {
+		zxdh_encpy_mode = e_SEC_ENCRYP_ESP_COMBINED_MODE;
+
+		ptDtbOutSa->ucCipherkeyLen = (xs->aead->alg_key_len + 7) / 8 - 3;
+		udIcvLen = (xs->aead->alg_icv_len + 7) / 8;
+		memcpy(&(ptDtbOutSa->udSalt),
+			   xs->aead->alg_key + ptDtbOutSa->ucCipherkeyLen,
+			   sizeof(ptDtbOutSa->udSalt));
+		memcpy((ptDtbOutSa->aucSaCipherKey), xs->aead->alg_key,
+			   ptDtbOutSa->ucCipherkeyLen);
+	}
+	/*这里处理有salt的单加密算法CTR,salt是4B*/
+	else if (zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_CTR) {
+		ptDtbOutSa->ucCipherkeyLen = (xs->ealg->alg_key_len + 7) / 8 - 4;
+		memcpy(&(ptDtbOutSa->udSalt),
+			   xs->ealg->alg_key + ptDtbOutSa->ucCipherkeyLen,
+			   sizeof(ptDtbOutSa->udSalt));
+		memcpy((ptDtbOutSa->aucSaCipherKey), xs->ealg->alg_key,
+			   ptDtbOutSa->ucCipherkeyLen);
+	}
+	/*空加密算法*/
+	else if (zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_NULL) {
+		zxdh_encpy_mode = e_SEC_ENCRYP_ESP_AUTH_MODE;
+		ptDtbOutSa->ucCipherkeyLen = 0;
+	}
+	/*单加密算法,且没有salt*/
+	else {
+		ptDtbOutSa->ucCipherkeyLen = (xs->ealg->alg_key_len + 7) / 8;
+		memcpy((ptDtbOutSa->aucSaCipherKey), xs->ealg->alg_key,
+			   ptDtbOutSa->ucCipherkeyLen);
+	}
+
+	ptDtbOutSa->udSN = xs->replay.oseq;
+	ptDtbOutSa->uddProcessedByteCnt =
+			xs->curlft.bytes; // PUB_HTON64(uddProcessedByteCnt);
+	// //没法设置,用于构造iv,  一般都是用seq构造的iv
+
+	ptDtbOutSa->udSPI = xs->id.spi;
+	ptDtbOutSa->udSaId = PUB_HTON32(
+			0x80001); // PUB_HTON32(udSaId); /*这个要软件自己管理,需要设计一下*/
+
+	ptDtbOutSa->ucCiperID = zxdh_ealgo_id;
+	ptDtbOutSa->ucAuthID = zxdh_auth_id;
+
+	// CmdkBttlSecSaParamConstruct(UINT32 udEntryValid,E_CMDK_SEC_IPSEC_MODE
+	// eTunnelMode,UINT32 udSeqCnterOverflow,E_CMDK_LIVETIME_TYPES
+	// eLiveTimeType,E_CMDK_SEC_SA_DF_MODE eSaDfMode,E_CMDK_SEC_ENCRYP_MODE
+	// eEncryptionMode,UINT32 udIcvLen,UINT16* pusSaParam) E_CMDK_SEC_ENCRYP_MODE
+	// 这个只能根据算法反推 gcm ccm gmac chacha是combine  gaucSecSwanIpv6Data
+	// udIcvLen
+	// mode的定义刚好一样E_CMDK_SEC_IPSEC_MODE ,   XFRM_MODE_TRANSPORT
+	/*这个地方还要根据算法做个转换  e_SEC_ENCRYP_ESP_COMBINED_MODE  暂时用GCM*/
+	CmdkBttlSecSaParamConstruct(1, xs->props.mode, 0,
+								e_SEC_SA_LIVETIME_TIME_TYPE,
+								e_SEC_SA_DF_BYPASS_MODE, zxdh_encpy_mode,
+								udIcvLen, &usSaParam);
+	ptDtbOutSa->usSaParam = PUB_HTON16(usSaParam);
+
+	ptDtbOutSa->usFrag_State = PUB_HTON16(0xd2c8);
+
+	ptDtbOutSa->udLifetimeSecMax = PUB_HTON32(0xc4454766);
+	ptDtbOutSa->uddLifetimByteCntMax = PUB_HTON64(0xffffffffffffffff);
+
+	ptDtbOutSa->ucProtocol = xs->id.proto; // 50esp协议 51ah
+	ptDtbOutSa->ucTOS = 0xbb;
+
+	/*esn相关*/
+	ptDtbOutSa->ucEsnFlag = 0; /* 默认是非ESN模式 */
+	if (xs->props.flags & XFRM_STATE_ESN) {
+		if (NULL == xs->replay_esn)
+			return 1;
+		ptDtbOutSa->ucEsnFlag =
+				0xff; // ucEsnFlag;    //0xff表示开启ESN,否则不开启
+		ptDtbOutSa->udSN = xs->replay_esn->oseq;
+		ptDtbOutSa->udESN =
+				xs->replay_esn->oseq_hi; /*不需要考虑replay_esn为null的情况?*/
+	}
+
+	/*ipv4*/
+	if (AF_INET == xs->props.family) {
+		ptDtbOutSa->ucIpType = 1 << 6; // bit[7:6] 1:ivp4 2:ipv6    /*换成宏*/
+		ptDtbOutSa->udSrcAddress0 = xs->props.saddr.a4;
+		ptDtbOutSa->udSrcAddress1 = 0x0;
+		ptDtbOutSa->udSrcAddress2 = 0x0;
+		ptDtbOutSa->udSrcAddress3 = 0x0;
+
+		ptDtbOutSa->udDstAddress0 = xs->id.daddr.a4;
+		ptDtbOutSa->udDstAddress1 = 0x0;
+		ptDtbOutSa->udDstAddress2 = 0x0;
+		ptDtbOutSa->udDstAddress3 = 0x0;
+	}
+	/*ipv4*/
+	else if (AF_INET6 == xs->props.family) {
+		ptDtbOutSa->ucIpType = 2 << 6; // bit[7:6] 1:ivp4 2:ipv6    /*换成宏*/
+		ptDtbOutSa->udSrcAddress0 = xs->props.saddr.a6[0];
+		ptDtbOutSa->udSrcAddress1 = xs->props.saddr.a6[1];
+		ptDtbOutSa->udSrcAddress2 = xs->props.saddr.a6[2];
+		ptDtbOutSa->udSrcAddress3 = xs->props.saddr.a6[3];
+
+		ptDtbOutSa->udDstAddress0 = xs->id.daddr.a6[0];
+		ptDtbOutSa->udDstAddress1 = xs->id.daddr.a6[1];
+		ptDtbOutSa->udDstAddress2 = xs->id.daddr.a6[2];
+		ptDtbOutSa->udDstAddress3 = xs->id.daddr.a6[3];
+	} else {
+		return -EINVAL; /*不可能走到这里,前面函数已经校验过了*/
+	}
+
+	ptDtbOutSa->udRSV0 = 0x0;
+	ptDtbOutSa->udRSV1 = 0x0;
+	ptDtbOutSa->udRSV2 = 0x0;
+
+	DH_LOG_INFO(MODULE_SEC, "ptDtbOutSa->ucAuthkeyLen:0x%x\n",
+				ptDtbOutSa->ucAuthkeyLen);
+	DH_LOG_INFO(MODULE_SEC, "ptDtbOutSa->ucCipherkeyLen:0x%x\n",
+				ptDtbOutSa->ucCipherkeyLen);
+	DH_LOG_INFO(MODULE_SEC, "zxdh_encpy_mode:0x%x\n", zxdh_encpy_mode);
+	DH_LOG_INFO(MODULE_SEC, "ptDtbOutSa->ucCiperID:0x%x\n",
+				ptDtbOutSa->ucCiperID);
+	DH_LOG_INFO(MODULE_SEC, "ptDtbOutSa->ucAuthID:0x%x\n",
+				ptDtbOutSa->ucAuthID);
+
+	return 0;
 }
 
-static int zxdh_ipsec_dtb_in_sa_get(struct xfrm_state *xs,T_HAL_SA_DTB_HW_IN* ptDtbInSa)
+static int zxdh_ipsec_dtb_in_sa_get(struct xfrm_state *xs,
+									T_HAL_SA_DTB_HW_IN *ptDtbInSa)
 {
-    int err = -EINVAL;
-    u16 usSaParam = 0;
-    u32 udIcvLen = 0;
-    E_HAL_SEC_IPSEC_AUTH_ALG zxdh_auth_id;
-    E_HAL_SEC_IPSEC_CIPHER_ALG zxdh_ealgo_id;
-    E_CMDK_SEC_ENCRYP_MODE zxdh_encpy_mode = e_SEC_ENCRYP_MODE_LAST;
-    char test_alg_name[] = "zxdh_alg_test";
-    char* p_aalg_alg_name = test_alg_name;
-    char* p_ealg_alg_name = test_alg_name;
-    char* p_aead_alg_name = test_alg_name;
-
-/*应该和pcs的思路一样  ,mlx5e_xfrm_validate_state 参数校验里去把sa的赋值做了*/
-    if(NULL != xs->aalg)
-    {
-        p_aalg_alg_name = xs->aalg->alg_name;
-    }
-    if(NULL != xs->ealg)
-    {
-        p_ealg_alg_name = xs->ealg->alg_name;
-    }
-    if(NULL != xs->aead)
-    {
-        p_aead_alg_name = xs->aead->alg_name;
-    }
-    err = zxdh_ipsec_auth_id_get(xs->props.aalgo,p_aalg_alg_name,&zxdh_auth_id);
-    if (err) {
-        DH_LOG_INFO(MODULE_SEC, "Cannot offload xfrm state aalgo:%u\n",xs->props.aalgo);
-        return -EINVAL;
-    }
-    err = zxdh_ipsec_cipher_id_get(xs->props.ealgo,p_ealg_alg_name,p_aead_alg_name,&zxdh_ealgo_id);
-    if (err) {
-        DH_LOG_INFO(MODULE_SEC, "Cannot offload xfrm state ealgo:%u\n",xs->props.aalgo);
-        return -EINVAL;
-    }
-
-    ptDtbInSa->ucAuthkeyLen       = 0;    /*默认值*/
-
-    /*处理单认证算法*/
-    if(zxdh_auth_id == e_HAL_IPSEC_AUTH_NULL)
-    {
-        zxdh_encpy_mode = e_SEC_ENCRYP_ESP_ENCRYP_MODE;
-    }
-    else
-    {
-        ptDtbInSa->ucAuthkeyLen       = (xs->aalg->alg_key_len + 7)/8;
-        udIcvLen = (xs->aalg->alg_trunc_len + 7)/8;
-        memcpy((ptDtbInSa->aucSaAuthKey),xs->aalg->alg_key,ptDtbInSa->ucAuthkeyLen);
-    }
-
-    if((zxdh_ealgo_id != e_HAL_IPSEC_CIPHER_NULL)&&(zxdh_auth_id != e_HAL_IPSEC_AUTH_NULL))
-    {
-        zxdh_encpy_mode = e_SEC_ENCRYP_ESP_AUTH_AND_ESP_ENCRYP_MODE;
-    }
-    /*这里处理组合算法的4字节的salt*/
-    if((zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_GCM)||(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_CHACHA)||(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_GMAC))
-    {
-        zxdh_encpy_mode = e_SEC_ENCRYP_ESP_COMBINED_MODE;
-
-        ptDtbInSa->ucCipherkeyLen     = (xs->aead->alg_key_len + 7)/8 - 4;
-        udIcvLen = (xs->aead->alg_icv_len+ 7)/8;
-        memcpy(&(ptDtbInSa->udSalt), xs->aead->alg_key + ptDtbInSa->ucCipherkeyLen,sizeof(ptDtbInSa->udSalt));
-        memcpy((ptDtbInSa->aucSaCipherKey),xs->aead->alg_key,ptDtbInSa->ucCipherkeyLen);
-    }
-    /*这里处理组合算法CCM,CCM的salt是3B*/
-    else if(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_CCM)
-    {
-        zxdh_encpy_mode = e_SEC_ENCRYP_ESP_COMBINED_MODE;
-
-        ptDtbInSa->ucCipherkeyLen     = (xs->aead->alg_key_len + 7)/8 - 3;
-        udIcvLen = (xs->aead->alg_icv_len+ 7)/8;
-        memcpy(&(ptDtbInSa->udSalt), xs->aead->alg_key + ptDtbInSa->ucCipherkeyLen,sizeof(ptDtbInSa->udSalt));
-        memcpy((ptDtbInSa->aucSaCipherKey),xs->aead->alg_key,ptDtbInSa->ucCipherkeyLen);
-    }
-    /*这里处理有salt的单加密算法CTR,salt是4B*/
-    else if(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_CTR)
-    {
-        ptDtbInSa->ucCipherkeyLen     = (xs->ealg->alg_key_len + 7)/8 - 4;
-        memcpy(&(ptDtbInSa->udSalt), xs->ealg->alg_key + ptDtbInSa->ucCipherkeyLen,sizeof(ptDtbInSa->udSalt));
-        memcpy((ptDtbInSa->aucSaCipherKey),xs->ealg->alg_key,ptDtbInSa->ucCipherkeyLen);
-    }
-    /*空加密算法*/
-    else if(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_NULL)
-    {
-        zxdh_encpy_mode = e_SEC_ENCRYP_ESP_AUTH_MODE;
-        ptDtbInSa->ucCipherkeyLen     = 0;
-    }
-    /*单加密算法,且没有salt*/
-    else
-    {
-        ptDtbInSa->ucCipherkeyLen     = (xs->ealg->alg_key_len + 7)/8;
-        memcpy((ptDtbInSa->aucSaCipherKey),xs->ealg->alg_key,ptDtbInSa->ucCipherkeyLen);
-    }
-
-    ptDtbInSa->uddProcessedByteCnt = xs->curlft.bytes;   //PUB_HTON64(uddProcessedByteCnt);   //没法设置,用于构造iv,  一般都是用seq构造的iv
-
-    ptDtbInSa->udSPI          = xs->id.spi;
-    ptDtbInSa->udSaId        = PUB_HTON32(0x80000);            //PUB_HTON32(udSaId);                             /*这个要软件自己管理,需要设计一下*/
-
-    ptDtbInSa->ucCiperID      = zxdh_ealgo_id;
-    ptDtbInSa->ucAuthID       = zxdh_auth_id;
-
-    //CmdkBttlSecSaParamConstruct(UINT32 udEntryValid,E_CMDK_SEC_IPSEC_MODE eTunnelMode,UINT32 udSeqCnterOverflow,E_CMDK_LIVETIME_TYPES eLiveTimeType,E_CMDK_SEC_SA_DF_MODE eSaDfMode,E_CMDK_SEC_ENCRYP_MODE eEncryptionMode,UINT32 udIcvLen,UINT16* pusSaParam)
-    //CmdkBttlSecSaParamConstruct(1,x->props.mode,不确定,e_SEC_SA_LIVETIME_BYTE_TYPE(好像硬件只支持这个),E_CMDK_SEC_SA_DF_MODE(0),)
-    //E_CMDK_SEC_ENCRYP_MODE 这个只能根据算法反推 gcm ccm gmac chacha是combine  gaucSecSwanIpv6Data
-    //udIcvLen
-    //mode的定义刚好一样E_CMDK_SEC_IPSEC_MODE ,   XFRM_MODE_TRANSPORT
-    CmdkBttlSecSaParamConstruct(1,xs->props.mode,0,e_SEC_SA_LIVETIME_TIME_TYPE,e_SEC_SA_DF_BYPASS_MODE,zxdh_encpy_mode,udIcvLen,&usSaParam);
-    ptDtbInSa->usSaParam      = PUB_HTON16(usSaParam);
-
-
-
-    ptDtbInSa->usFrag_State   = PUB_HTON16(0xd2c8);
-
-    ptDtbInSa->udLifetimeSecMax  = PUB_HTON32(0xc4454766);
-    ptDtbInSa->uddLifetimByteCntMax      = PUB_HTON64(0xffffffffffffffff);
-
-    ptDtbInSa->ucProtocol     = xs->id.proto;     //50esp协议 51ah
-    ptDtbInSa->ucTOS          = 0xbb;
-
-    /*esn相关*/
-    ptDtbInSa->ucEsnFlag  = 0;  /* 默认是非ESN模式 */
-    if(xs->props.flags & XFRM_STATE_ESN)
-    {
-        if(NULL == xs->replay_esn)
-            return 1;
-        ptDtbInSa->ucEsnFlag    = 0xff; //ucEsnFlag;    //0xff表示开启ESN,否则不开启
-        ptDtbInSa->udAntiWindowHigh        = PUB_HTON32(xs->replay_esn->seq_hi); /*ESN*/
-        ptDtbInSa->udAntiWindowLow        = PUB_HTON32(xs->replay_esn->replay_window - 1); /*窗口上限sn,这里使用窗口大小-1*/
-        memcpy((void*)ptDtbInSa->aucBitmap,(void*)xs->replay_esn->bmp,xs->replay_esn->bmp_len * sizeof(__u32)); /*需要提前判断bmp_len不能太大,避免超过64(拦截窗口大小就行)*/
-    }
-
-    /*ipv4*/
-    if(AF_INET == xs->props.family)
-    {
-        ptDtbInSa->ucIpType     = 1<<6;   //bit[7:6] 1:ivp4 2:ipv6    /*换成宏*/
-        ptDtbInSa->udSrcAddress0  = xs->props.saddr.a4;
-        ptDtbInSa->udSrcAddress1  = 0x0;
-        ptDtbInSa->udSrcAddress2  = 0x0;
-        ptDtbInSa->udSrcAddress3  = 0x0;
-
-        ptDtbInSa->udDstAddress0  = xs->id.daddr.a4;
-        ptDtbInSa->udDstAddress1  = 0x0;
-        ptDtbInSa->udDstAddress2  = 0x0;
-        ptDtbInSa->udDstAddress3  = 0x0;
-    }
-    /*ipv4*/
-    else if(AF_INET6 == xs->props.family)
-    {
-        ptDtbInSa->ucIpType     = 2<<6;   //bit[7:6] 1:ivp4 2:ipv6    /*换成宏*/
-        ptDtbInSa->udSrcAddress0  = xs->props.saddr.a6[0];
-        ptDtbInSa->udSrcAddress1  = xs->props.saddr.a6[1];
-        ptDtbInSa->udSrcAddress2  = xs->props.saddr.a6[2];
-        ptDtbInSa->udSrcAddress3  = xs->props.saddr.a6[3];
-
-        ptDtbInSa->udDstAddress0  = xs->id.daddr.a6[0];
-        ptDtbInSa->udDstAddress1  = xs->id.daddr.a6[1];
-        ptDtbInSa->udDstAddress2  = xs->id.daddr.a6[2];
-        ptDtbInSa->udDstAddress3  = xs->id.daddr.a6[3];
-    }
-    else
-    {
-        return -EINVAL;  /*不可能走到这里,前面函数已经校验过了*/
-    }
-
-    ptDtbInSa->udOutSaId    = 0x0;   /*内核不需要出入境sa一起下吧,固定为0*/
-    ptDtbInSa->usOutSaOffset    = 0x0;
-
-    ptDtbInSa->udRSV0       = 0x0;
-    ptDtbInSa->udRSV1       = 0x0;
-
-    DH_LOG_INFO(MODULE_SEC, "ptDtbInSa->ucAuthkeyLen:0x%x\n",ptDtbInSa->ucAuthkeyLen);
-    DH_LOG_INFO(MODULE_SEC, "ptDtbInSa->ucCipherkeyLen:0x%x\n",ptDtbInSa->ucCipherkeyLen);
-    DH_LOG_INFO(MODULE_SEC, "zxdh_encpy_mode:0x%x\n",zxdh_encpy_mode);
-    DH_LOG_INFO(MODULE_SEC, "ptDtbInSa->ucCiperID:0x%x\n",ptDtbInSa->ucCiperID);
-    DH_LOG_INFO(MODULE_SEC, "ptDtbInSa->ucAuthID:0x%x\n",ptDtbInSa->ucAuthID);
-
-
-    return 0;
+	int err = -EINVAL;
+	u16 usSaParam = 0;
+	u32 udIcvLen = 0;
+	E_HAL_SEC_IPSEC_AUTH_ALG zxdh_auth_id;
+	E_HAL_SEC_IPSEC_CIPHER_ALG zxdh_ealgo_id;
+	E_CMDK_SEC_ENCRYP_MODE zxdh_encpy_mode = e_SEC_ENCRYP_MODE_LAST;
+	char test_alg_name[] = "zxdh_alg_test";
+	char *p_aalg_alg_name = test_alg_name;
+	char *p_ealg_alg_name = test_alg_name;
+	char *p_aead_alg_name = test_alg_name;
+
+	/*应该和pcs的思路一样  ,mlx5e_xfrm_validate_state 参数校验里去把sa的赋值做了*/
+	if (NULL != xs->aalg) {
+		p_aalg_alg_name = xs->aalg->alg_name;
+	}
+	if (NULL != xs->ealg) {
+		p_ealg_alg_name = xs->ealg->alg_name;
+	}
+	if (NULL != xs->aead) {
+		p_aead_alg_name = xs->aead->alg_name;
+	}
+	err = zxdh_ipsec_auth_id_get(xs->props.aalgo, p_aalg_alg_name,
+								 &zxdh_auth_id);
+	if (err) {
+		DH_LOG_INFO(MODULE_SEC, "Cannot offload xfrm state aalgo:%u\n",
+					xs->props.aalgo);
+		return -EINVAL;
+	}
+	err = zxdh_ipsec_cipher_id_get(xs->props.ealgo, p_ealg_alg_name,
+								   p_aead_alg_name, &zxdh_ealgo_id);
+	if (err) {
+		DH_LOG_INFO(MODULE_SEC, "Cannot offload xfrm state ealgo:%u\n",
+					xs->props.aalgo);
+		return -EINVAL;
+	}
+
+	ptDtbInSa->ucAuthkeyLen = 0; /*默认值*/
+
+	/*处理单认证算法*/
+	if (zxdh_auth_id == e_HAL_IPSEC_AUTH_NULL) {
+		zxdh_encpy_mode = e_SEC_ENCRYP_ESP_ENCRYP_MODE;
+	} else {
+		ptDtbInSa->ucAuthkeyLen = (xs->aalg->alg_key_len + 7) / 8;
+		udIcvLen = (xs->aalg->alg_trunc_len + 7) / 8;
+		memcpy((ptDtbInSa->aucSaAuthKey), xs->aalg->alg_key,
+			   ptDtbInSa->ucAuthkeyLen);
+	}
+
+	if ((zxdh_ealgo_id != e_HAL_IPSEC_CIPHER_NULL) &&
+		(zxdh_auth_id != e_HAL_IPSEC_AUTH_NULL)) {
+		zxdh_encpy_mode = e_SEC_ENCRYP_ESP_AUTH_AND_ESP_ENCRYP_MODE;
+	}
+	/*这里处理组合算法的4字节的salt*/
+	if ((zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_GCM) ||
+		(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_CHACHA) ||
+		(zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_GMAC)) {
+		zxdh_encpy_mode = e_SEC_ENCRYP_ESP_COMBINED_MODE;
+
+		ptDtbInSa->ucCipherkeyLen = (xs->aead->alg_key_len + 7) / 8 - 4;
+		udIcvLen = (xs->aead->alg_icv_len + 7) / 8;
+		memcpy(&(ptDtbInSa->udSalt),
+			   xs->aead->alg_key + ptDtbInSa->ucCipherkeyLen,
+			   sizeof(ptDtbInSa->udSalt));
+		memcpy((ptDtbInSa->aucSaCipherKey), xs->aead->alg_key,
+			   ptDtbInSa->ucCipherkeyLen);
+	}
+	/*这里处理组合算法CCM,CCM的salt是3B*/
+	else if (zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_CCM) {
+		zxdh_encpy_mode = e_SEC_ENCRYP_ESP_COMBINED_MODE;
+
+		ptDtbInSa->ucCipherkeyLen = (xs->aead->alg_key_len + 7) / 8 - 3;
+		udIcvLen = (xs->aead->alg_icv_len + 7) / 8;
+		memcpy(&(ptDtbInSa->udSalt),
+			   xs->aead->alg_key + ptDtbInSa->ucCipherkeyLen,
+			   sizeof(ptDtbInSa->udSalt));
+		memcpy((ptDtbInSa->aucSaCipherKey), xs->aead->alg_key,
+			   ptDtbInSa->ucCipherkeyLen);
+	}
+	/*这里处理有salt的单加密算法CTR,salt是4B*/
+	else if (zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_AES_CTR) {
+		ptDtbInSa->ucCipherkeyLen = (xs->ealg->alg_key_len + 7) / 8 - 4;
+		memcpy(&(ptDtbInSa->udSalt),
+			   xs->ealg->alg_key + ptDtbInSa->ucCipherkeyLen,
+			   sizeof(ptDtbInSa->udSalt));
+		memcpy((ptDtbInSa->aucSaCipherKey), xs->ealg->alg_key,
+			   ptDtbInSa->ucCipherkeyLen);
+	}
+	/*空加密算法*/
+	else if (zxdh_ealgo_id == e_HAL_IPSEC_CIPHER_NULL) {
+		zxdh_encpy_mode = e_SEC_ENCRYP_ESP_AUTH_MODE;
+		ptDtbInSa->ucCipherkeyLen = 0;
+	}
+	/*单加密算法,且没有salt*/
+	else {
+		ptDtbInSa->ucCipherkeyLen = (xs->ealg->alg_key_len + 7) / 8;
+		memcpy((ptDtbInSa->aucSaCipherKey), xs->ealg->alg_key,
+			   ptDtbInSa->ucCipherkeyLen);
+	}
+
+	ptDtbInSa->uddProcessedByteCnt =
+			xs->curlft.bytes; // PUB_HTON64(uddProcessedByteCnt);
+	// //没法设置,用于构造iv,  一般都是用seq构造的iv
+
+	ptDtbInSa->udSPI = xs->id.spi;
+	ptDtbInSa->udSaId = PUB_HTON32(
+			0x80000); // PUB_HTON32(udSaId); /*这个要软件自己管理,需要设计一下*/
+
+	ptDtbInSa->ucCiperID = zxdh_ealgo_id;
+	ptDtbInSa->ucAuthID = zxdh_auth_id;
+
+	// CmdkBttlSecSaParamConstruct(UINT32 udEntryValid,E_CMDK_SEC_IPSEC_MODE
+	// eTunnelMode,UINT32 udSeqCnterOverflow,E_CMDK_LIVETIME_TYPES
+	// eLiveTimeType,E_CMDK_SEC_SA_DF_MODE eSaDfMode,E_CMDK_SEC_ENCRYP_MODE
+	// eEncryptionMode,UINT32 udIcvLen,UINT16* pusSaParam)
+	// CmdkBttlSecSaParamConstruct(1,x->props.mode,不确定,e_SEC_SA_LIVETIME_BYTE_TYPE(好像硬件只支持这个),E_CMDK_SEC_SA_DF_MODE(0),)
+	// E_CMDK_SEC_ENCRYP_MODE 这个只能根据算法反推 gcm ccm gmac chacha是combine
+	// gaucSecSwanIpv6Data udIcvLen mode的定义刚好一样E_CMDK_SEC_IPSEC_MODE ,
+	// XFRM_MODE_TRANSPORT
+	CmdkBttlSecSaParamConstruct(1, xs->props.mode, 0,
+								e_SEC_SA_LIVETIME_TIME_TYPE,
+								e_SEC_SA_DF_BYPASS_MODE, zxdh_encpy_mode,
+								udIcvLen, &usSaParam);
+	ptDtbInSa->usSaParam = PUB_HTON16(usSaParam);
+
+	ptDtbInSa->usFrag_State = PUB_HTON16(0xd2c8);
+
+	ptDtbInSa->udLifetimeSecMax = PUB_HTON32(0xc4454766);
+	ptDtbInSa->uddLifetimByteCntMax = PUB_HTON64(0xffffffffffffffff);
+
+	ptDtbInSa->ucProtocol = xs->id.proto; // 50esp协议 51ah
+	ptDtbInSa->ucTOS = 0xbb;
+
+	/*esn相关*/
+	ptDtbInSa->ucEsnFlag = 0; /* 默认是非ESN模式 */
+	if (xs->props.flags & XFRM_STATE_ESN) {
+		if (NULL == xs->replay_esn)
+			return 1;
+		ptDtbInSa->ucEsnFlag =
+				0xff; // ucEsnFlag;    //0xff表示开启ESN,否则不开启
+		ptDtbInSa->udAntiWindowHigh =
+				PUB_HTON32(xs->replay_esn->seq_hi); /*ESN*/
+		ptDtbInSa->udAntiWindowLow =
+				PUB_HTON32(xs->replay_esn->replay_window -
+						   1); /*窗口上限sn,这里使用窗口大小-1*/
+		memcpy((void *)ptDtbInSa->aucBitmap, (void *)xs->replay_esn->bmp,
+			   xs->replay_esn->bmp_len *
+					   sizeof(__u32)); /*需要提前判断bmp_len不能太大,避免超过64(拦截窗口大小就行)*/
+	}
+
+	/*ipv4*/
+	if (AF_INET == xs->props.family) {
+		ptDtbInSa->ucIpType = 1 << 6; // bit[7:6] 1:ivp4 2:ipv6    /*换成宏*/
+		ptDtbInSa->udSrcAddress0 = xs->props.saddr.a4;
+		ptDtbInSa->udSrcAddress1 = 0x0;
+		ptDtbInSa->udSrcAddress2 = 0x0;
+		ptDtbInSa->udSrcAddress3 = 0x0;
+
+		ptDtbInSa->udDstAddress0 = xs->id.daddr.a4;
+		ptDtbInSa->udDstAddress1 = 0x0;
+		ptDtbInSa->udDstAddress2 = 0x0;
+		ptDtbInSa->udDstAddress3 = 0x0;
+	}
+	/*ipv4*/
+	else if (AF_INET6 == xs->props.family) {
+		ptDtbInSa->ucIpType = 2 << 6; // bit[7:6] 1:ivp4 2:ipv6    /*换成宏*/
+		ptDtbInSa->udSrcAddress0 = xs->props.saddr.a6[0];
+		ptDtbInSa->udSrcAddress1 = xs->props.saddr.a6[1];
+		ptDtbInSa->udSrcAddress2 = xs->props.saddr.a6[2];
+		ptDtbInSa->udSrcAddress3 = xs->props.saddr.a6[3];
+
+		ptDtbInSa->udDstAddress0 = xs->id.daddr.a6[0];
+		ptDtbInSa->udDstAddress1 = xs->id.daddr.a6[1];
+		ptDtbInSa->udDstAddress2 = xs->id.daddr.a6[2];
+		ptDtbInSa->udDstAddress3 = xs->id.daddr.a6[3];
+	} else {
+		return -EINVAL; /*不可能走到这里,前面函数已经校验过了*/
+	}
+
+	ptDtbInSa->udOutSaId = 0x0; /*内核不需要出入境sa一起下吧,固定为0*/
+	ptDtbInSa->usOutSaOffset = 0x0;
+
+	ptDtbInSa->udRSV0 = 0x0;
+	ptDtbInSa->udRSV1 = 0x0;
+
+	DH_LOG_INFO(MODULE_SEC, "ptDtbInSa->ucAuthkeyLen:0x%x\n",
+				ptDtbInSa->ucAuthkeyLen);
+	DH_LOG_INFO(MODULE_SEC, "ptDtbInSa->ucCipherkeyLen:0x%x\n",
+				ptDtbInSa->ucCipherkeyLen);
+	DH_LOG_INFO(MODULE_SEC, "zxdh_encpy_mode:0x%x\n", zxdh_encpy_mode);
+	DH_LOG_INFO(MODULE_SEC, "ptDtbInSa->ucCiperID:0x%x\n",
+				ptDtbInSa->ucCiperID);
+	DH_LOG_INFO(MODULE_SEC, "ptDtbInSa->ucAuthID:0x%x\n", ptDtbInSa->ucAuthID);
+
+	return 0;
 }
 #endif
 
-
 VOID RdlSecWrite(UINT64 uddSecBase, UINT32 udRegOff, UINT32 udRegVal)
 {
-    PUB_WRITE_REG32(uddSecBase + udRegOff, udRegVal);
+	PUB_WRITE_REG32(uddSecBase + udRegOff, udRegVal);
 }
 
-UINT32 HalSecWrite(struct zxdh_en_device *en_dev, UINT32 udSecEngineId, UINT32 udRegOff, UINT32 udRegVal)
+UINT32 HalSecWrite(struct zxdh_en_device *en_dev, UINT32 udSecEngineId,
+				   UINT32 udRegOff, UINT32 udRegVal)
 {
-    UINT64 uddBttlSecBase = 0;
-    UINT32 udSecnBaseOff = 0;
-    UINT64 uddSecnBase = 0;
+	UINT64 uddBttlSecBase = 0;
+	UINT32 udSecnBaseOff = 0;
+	UINT64 uddSecnBase = 0;
 
-    PUB_CHECK_NULL_PTR_RET_ERR(en_dev);
+	PUB_CHECK_NULL_PTR_RET_ERR(en_dev);
 
-    uddBttlSecBase = HalBttlSecRegBaseGet(en_dev);
-    //udSecnBaseOff  = udSecEngineId * REG_SEC_IDX_OFFSET;  //host不允许操作第二套
-    uddSecnBase    = uddBttlSecBase + udSecnBaseOff;
-    //DH_LOG_INFO(MODULE_SEC, "HalBttlSecRegBaseGet regBase vir:0x%llx\n",uddSecnBase);
-    //DH_LOG_INFO(MODULE_SEC, "HalBttlSecRegBaseGet regBase pa:0x%llx\n",virt_to_phys((void*)uddSecnBase));
-    RdlSecWrite(uddSecnBase, udRegOff, udRegVal);
+	uddBttlSecBase = HalBttlSecRegBaseGet(en_dev);
+	// udSecnBaseOff  = udSecEngineId * REG_SEC_IDX_OFFSET; //host不允许操作第二套
+	uddSecnBase = uddBttlSecBase + udSecnBaseOff;
+	// DH_LOG_INFO(MODULE_SEC, "HalBttlSecRegBaseGet regBase
+	// vir:0x%llx\n",uddSecnBase); DH_LOG_INFO(MODULE_SEC, "HalBttlSecRegBaseGet
+	// regBase pa:0x%llx\n",virt_to_phys((void*)uddSecnBase));
+	RdlSecWrite(uddSecnBase, udRegOff, udRegVal);
 
-    return 0;
+	return 0;
 }
 
 UINT32 RdlSecRead(UINT64 uddSecBase, UINT32 udRegOff)
 {
-    return PUB_READ_REG32(uddSecBase + udRegOff);
+	return PUB_READ_REG32(uddSecBase + udRegOff);
 }
 
-UINT32 HalSecRead(struct zxdh_en_device *en_dev, UINT32 udSecEngineId, UINT32 udRegOff)
+UINT32 HalSecRead(struct zxdh_en_device *en_dev, UINT32 udSecEngineId,
+				  UINT32 udRegOff)
 {
-    UINT64 uddBttlSecBase = 0;
-    UINT32 udSecnBaseOff = 0;
-    UINT64 uddSecnBase = 0;
+	UINT64 uddBttlSecBase = 0;
+	UINT32 udSecnBaseOff = 0;
+	UINT64 uddSecnBase = 0;
 
-    PUB_CHECK_NULL_PTR_RET_ERR(en_dev);
-    uddBttlSecBase = HalBttlSecRegBaseGet(en_dev);
-    udSecnBaseOff  = udSecEngineId * REG_SEC_IDX_OFFSET;
-    uddSecnBase    = uddBttlSecBase + udSecnBaseOff;
+	PUB_CHECK_NULL_PTR_RET_ERR(en_dev);
+	uddBttlSecBase = HalBttlSecRegBaseGet(en_dev);
+	udSecnBaseOff = udSecEngineId * REG_SEC_IDX_OFFSET;
+	uddSecnBase = uddBttlSecBase + udSecnBaseOff;
 
-    return RdlSecRead(uddSecnBase, udRegOff);
+	return RdlSecRead(uddSecnBase, udRegOff);
 }
 
-
 UINT64 HalBttlVaToVpa(struct zxdh_en_device *en_dev, UINT64 pVaAddr)
 {
-    PUB_CHECK_NULL_PTR_RET_ERR(en_dev);
-    return (UINT64)virt_to_phys((void*)pVaAddr);
+	PUB_CHECK_NULL_PTR_RET_ERR(en_dev);
+	return (UINT64)virt_to_phys((void *)pVaAddr);
 }
 
 UINT64 HalBttlVpaToVa(struct zxdh_en_device *en_dev, UINT64 pVpaAddr)
 {
-    PUB_CHECK_NULL_PTR_RET_ERR(en_dev);
-    return (UINT64)phys_to_virt(pVpaAddr);
-}
-
-#if 0
-VOID PubDumpBuf(UINT8 *pucBuf, UINT32 udLen)
-{
-    UINT32 i = 0;
-    UINT32 j = 0;
-    UINT8 *pucPtr =NULL;
-
-    pucPtr = pucBuf;
-    for( j=0; j<48; j++ )
-    {
-        PUB_PRINTF("-");
-    }
-    PUB_PRINTF("\n");
-
-    for( i=0; i<udLen; i++ )
-    {
-        PUB_PRINTF("%02X ", pucPtr[i] );
-        if ( 15 == i%16 )
-        {
-            PUB_PRINTF("   *");
-            PUB_PRINTF("*\n");
-        }
-    }
-
-    if ( 0 == udLen%16 )
-    {
-        PUB_PRINTF("\n");
-    }
-    else
-    {
-        for ( i=(udLen%16); i<16; i++ )
-        {
-            PUB_PRINTF("   ");
-        }
-        PUB_PRINTF("   *");
-        PUB_PRINTF("\n\n");
-    }
+	PUB_CHECK_NULL_PTR_RET_ERR(en_dev);
+	return (UINT64)phys_to_virt(pVpaAddr);
 }
-#endif
 
 void BttlPubDump(unsigned char *ucBuf, UINT32 udLen)
 {
-    int i = 0;
-    int j = 0;
-    unsigned char *ptr =NULL;
-
-    ptr = ucBuf;
-
-    if (ucBuf == NULL || udLen == 0)
-    {
-        return;
-    }
-
-    for( j=0; j<64; j++ )
-    {
-        printk("-");
-    }
-    printk("\n");
-
-    for( i=0; i<udLen; i++ )
-    {
-        if ( 0 == i%16 )
-        {
-            printk("0x%08x ", (i/16)*16);
-        }
-        printk("%02X ", ptr[i] );
-        if ( 15 == i%16 )
-        {
-            printk("   *");
-            printk("*\n");
-        }
-    }
-
-    if ( 0 == udLen%16 )
-    {
-        printk("\n");
-    }
-    else
-    {
-        for ( i=(udLen%16); i<16; i++ )
-        {
-            printk("   ");
-        }
-        printk("   *");
-        printk("\n\n");
-    }
-
-    return;
+	int i = 0;
+	int j = 0;
+	unsigned char *ptr = NULL;
+
+	ptr = ucBuf;
+
+	if (ucBuf == NULL || udLen == 0) {
+		return;
+	}
+
+	for (j = 0; j < 64; j++) {
+		printk("-");
+	}
+	printk("\n");
+
+	for (i = 0; i < udLen; i++) {
+		if (0 == i % 16) {
+			printk("0x%08x ", (i / 16) * 16);
+		}
+		printk("%02X ", ptr[i]);
+		if (15 == i % 16) {
+			printk("   *");
+			printk("*\n");
+		}
+	}
+
+	if (0 == udLen % 16) {
+		printk("\n");
+	} else {
+		for (i = (udLen % 16); i < 16; i++) {
+			printk("   ");
+		}
+		printk("   *");
+		printk("\n\n");
+	}
+
+	return;
 }
 
-UINT32 CmdkBttlTestSaAckRslGet(UINT64 uddSaVirAddr,E_CMDK_DTB_SA_CMD_TYPE eDtbSaCmdType,UINT32 *pudIsDtbAckFinish,UINT32 *pudDtbAckRsl)
+UINT32 CmdkBttlTestSaAckRslGet(UINT64 uddSaVirAddr,
+							   E_CMDK_DTB_SA_CMD_TYPE eDtbSaCmdType,
+							   UINT32 *pudIsDtbAckFinish, UINT32 *pudDtbAckRsl)
 {
-    UINT32 udVal = 0;
-    UINT32 udDtbAckFinish = 0;
-
-    /*入参检查*/
-    //BTTL_PUB_ID_CHECK(eDtbSaCmdType, E_DTB_SA_CMD_LAST);
-    //BTTL_PUB_NULL_CHECK(pudIsDtbAckFinish);
-    //BTTL_PUB_NULL_CHECK(pudDtbAckRsl);
-
-    *pudIsDtbAckFinish = 0;  /* 默认置为响应未完成 */
-
-    udVal = *((UINT32 *)(uddSaVirAddr ));
-    udDtbAckFinish = PUB_BIT_FIELD_RIGHT_JUST_GET64(udVal,0,24);
-    *pudDtbAckRsl = PUB_BIT_FIELD_RIGHT_JUST_GET64(udVal,24,8);
-
-    if(E_DTB_SA_CMD_FLOW_DOWN == eDtbSaCmdType)
-    {
-        if(udDtbAckFinish == 0x5a5a5a)
-        {
-            *pudIsDtbAckFinish = 1;
-        }
-    }
-    else
-    {
-        if(udDtbAckFinish == 0x555555)
-        {
-            *pudIsDtbAckFinish = 1;
-        }
-    }
-
-    return 0;
-
+	UINT32 udVal = 0;
+	UINT32 udDtbAckFinish = 0;
+
+	/*入参检查*/
+	// BTTL_PUB_ID_CHECK(eDtbSaCmdType, E_DTB_SA_CMD_LAST);
+	// BTTL_PUB_NULL_CHECK(pudIsDtbAckFinish);
+	// BTTL_PUB_NULL_CHECK(pudDtbAckRsl);
+
+	*pudIsDtbAckFinish = 0; /* 默认置为响应未完成 */
+
+	udVal = *((UINT32 *)(uddSaVirAddr));
+	udDtbAckFinish = PUB_BIT_FIELD_RIGHT_JUST_GET64(udVal, 0, 24);
+	*pudDtbAckRsl = PUB_BIT_FIELD_RIGHT_JUST_GET64(udVal, 24, 8);
+
+	if (E_DTB_SA_CMD_FLOW_DOWN == eDtbSaCmdType) {
+		if (udDtbAckFinish == 0x5a5a5a) {
+			*pudIsDtbAckFinish = 1;
+		}
+	} else {
+		if (udDtbAckFinish == 0x555555) {
+			*pudIsDtbAckFinish = 1;
+		}
+	}
+
+	return 0;
 }
 
 /*参考NP的函数 dpp_dtb_user_info_set*/
-UINT32 CmdkBttlSecSaDownload(struct zxdh_en_device *en_dev, UINT32 udSecEngineId, T_QUEUE_DTB_REG *pt,UINT32 udQueIndex)
+UINT32 CmdkBttlSecSaDownload(struct zxdh_en_device *en_dev,
+							 UINT32 udSecEngineId, T_QUEUE_DTB_REG *pt,
+							 UINT32 udQueIndex)
 {
-    UINT32 udRet;
-    UINT32 udRegVal;
-    //UINT32 udQueIndex = 1;
-    UINT32 udEpldVfunNum = 0;
-    UINT32 udPcieDbiEn = 1;        /*1为dbi中断，0为match中断,NP这里是全局变量,暂时写死*/
-    UINT32 udEpid = 5;
-    UINT32 udVfuncNum = 0;
-    UINT32 udCfgMsixVector = 2;    /*以前host驱动写的是2,暂时写死*/
-    UINT32 udFuncNum = 2;
-    UINT32 udVfuncActive = 0;
-    UINT16 usVport = 0;
-
-    //BTTL_PUB_ID_CHECK(en_dev, CMDK_BTTL_PUB_CHIP_MAX);
-    //BTTL_PUB_ID_CHECK(udSecEngineId, HAL_SEC_MAX_ENGINE);
-    //BTTL_PUB_NULL_CHECK(pt);
-    PUB_CHECK_NULL_PTR_RET_ERR(en_dev);
-
-    usVport = en_dev->ops->get_vport(en_dev->parent);
-
-    //写sa的队列锁状态寄存器CFG_DTB_QUEUE_LOCK_STATE，共128个队列,理论上应该查询
-    //udRet = HalSecWrite(en_dev, udSecEngineId, REG_SEC_DTB_QUEUE_LOCK_STATE_0_3(0), PUB_BIT_SET(udLockMask,udQueIndex));
-
-
-    //暂时沟通是，只需要将epid配置为0，下表模块就会去riscv侧下表，暂时可以不配
-    udEpid = EPID(usVport) + 5;
-    udVfuncNum = VFUNC_NUM(usVport);
-    udFuncNum = FUNC_NUM(usVport);
-    udVfuncActive = VF_ACTIVE(usVport);
-
-    DH_LOG_INFO(MODULE_SEC, "udEpid:0x%x,udVfuncNum:0x%x\n",udEpid,udVfuncNum);
-    DH_LOG_INFO(MODULE_SEC, "udFuncNum:0x%x,udVfuncActive:0x%x\n",udFuncNum,udVfuncActive);
-
-    PUB_BIT_FIELD_SET64(udEpldVfunNum,udVfuncActive,0,1);
-    PUB_BIT_FIELD_SET64(udEpldVfunNum,udFuncNum,5,3);
-    PUB_BIT_FIELD_SET64(udEpldVfunNum,udCfgMsixVector,8,7);
-    PUB_BIT_FIELD_SET64(udEpldVfunNum,udVfuncNum,16,8);
-    PUB_BIT_FIELD_SET64(udEpldVfunNum,udEpid,24,4);
-    PUB_BIT_FIELD_SET64(udEpldVfunNum,udPcieDbiEn,31,1);
-
-    //return 0;
-    DH_LOG_INFO(MODULE_SEC, "udEpldVfunNum = 0x%x\n",udEpldVfunNum);
-    HalSecWrite(en_dev, udSecEngineId, REG_SEC_CFG_EPID_V_FUNC_NUM_0_127(udQueIndex), udEpldVfunNum);
-
-    //查询所申请队列剩余空间,如果队列剩余空间大于0则可入队；
-     udRegVal = HalSecRead(en_dev, udSecEngineId, REG_SEC_INFO_QUEUE_BUF_SPACE_LEFT_0_127(udQueIndex));
-     if(udRegVal < 2)
-     {
-         BTTL_PRINTF("queue:%u buf empty left:%u\n",udQueIndex,udRegVal);
-         return 1;
-     }
-     if(udRegVal > 0x20)
-     {
-         BTTL_PRINTF("queue:%u buf left:%u\n",udQueIndex,udRegVal);
-         return 1;
-     }
-
-    //先写DTB_ADDR[63:32],接着写DTB_ADDR[31:0],最后写usdtb_len(软件需严格遵守该顺序）
-    udRet = HalSecWrite(en_dev, udSecEngineId, REG_SEC_CFG_QUEUE_DTB_ADDR_H_0_127(udQueIndex), pt->DtbAddrH);
-
-    //DH_LOG_INFO(MODULE_SEC, "pt->DtbAddrH = 0x%x\n",pt->DtbAddrH);
-    udRet = HalSecWrite(en_dev, udSecEngineId, REG_SEC_CFG_QUEUE_DTB_ADDR_L_0_127(udQueIndex), pt->DtbAddrL);
-
-    //DH_LOG_INFO(MODULE_SEC, "pt->DtbAddrL = 0x%x\n",pt->DtbAddrL);
-    //DH_LOG_INFO(MODULE_SEC, "pt->DtbAddrVir = 0x%llx\n",HalBttlVpaToVa(en_dev,(UINT64)((UINT64)pt->DtbAddrH)<<32)+pt->DtbAddrL);
-    // CMD寄存器最后配
-    udRet = HalSecWrite(en_dev, udSecEngineId, REG_SEC_CFG_QUEUE_DTB_LEN_0_127(udQueIndex), pt->DtbCmd);
-
-    //DH_LOG_INFO(MODULE_SEC, "pt->DtbCmd = 0x%x\n",pt->DtbCmd);
-    return 0;
+	UINT32 udRet;
+	UINT32 udRegVal;
+	// UINT32 udQueIndex = 1;
+	UINT32 udEpldVfunNum = 0;
+	UINT32 udPcieDbiEn =
+			1; /*1为dbi中断，0为match中断,NP这里是全局变量,暂时写死*/
+	UINT32 udEpid = 5;
+	UINT32 udVfuncNum = 0;
+	UINT32 udCfgMsixVector = 2; /*以前host驱动写的是2,暂时写死*/
+	UINT32 udFuncNum = 2;
+	UINT32 udVfuncActive = 0;
+	UINT16 usVport = 0;
+
+	// BTTL_PUB_ID_CHECK(en_dev, CMDK_BTTL_PUB_CHIP_MAX);
+	// BTTL_PUB_ID_CHECK(udSecEngineId, HAL_SEC_MAX_ENGINE);
+	// BTTL_PUB_NULL_CHECK(pt);
+	PUB_CHECK_NULL_PTR_RET_ERR(en_dev);
+
+	usVport = en_dev->ops->get_vport(en_dev->parent);
+
+	//写sa的队列锁状态寄存器CFG_DTB_QUEUE_LOCK_STATE，共128个队列,理论上应该查询
+	// udRet = HalSecWrite(en_dev, udSecEngineId,
+	// REG_SEC_DTB_QUEUE_LOCK_STATE_0_3(0), PUB_BIT_SET(udLockMask,udQueIndex));
+
+	//暂时沟通是，只需要将epid配置为0，下表模块就会去riscv侧下表，暂时可以不配
+	udEpid = EPID(usVport) + 5;
+	udVfuncNum = VFUNC_NUM(usVport);
+	udFuncNum = FUNC_NUM(usVport);
+	udVfuncActive = VF_ACTIVE(usVport);
+
+	DH_LOG_INFO(MODULE_SEC, "udEpid:0x%x,udVfuncNum:0x%x\n", udEpid,
+				udVfuncNum);
+	DH_LOG_INFO(MODULE_SEC, "udFuncNum:0x%x,udVfuncActive:0x%x\n", udFuncNum,
+				udVfuncActive);
+
+	PUB_BIT_FIELD_SET64(udEpldVfunNum, udVfuncActive, 0, 1);
+	PUB_BIT_FIELD_SET64(udEpldVfunNum, udFuncNum, 5, 3);
+	PUB_BIT_FIELD_SET64(udEpldVfunNum, udCfgMsixVector, 8, 7);
+	PUB_BIT_FIELD_SET64(udEpldVfunNum, udVfuncNum, 16, 8);
+	PUB_BIT_FIELD_SET64(udEpldVfunNum, udEpid, 24, 4);
+	PUB_BIT_FIELD_SET64(udEpldVfunNum, udPcieDbiEn, 31, 1);
+
+	// return 0;
+	DH_LOG_INFO(MODULE_SEC, "udEpldVfunNum = 0x%x\n", udEpldVfunNum);
+	HalSecWrite(en_dev, udSecEngineId,
+				REG_SEC_CFG_EPID_V_FUNC_NUM_0_127(udQueIndex), udEpldVfunNum);
+
+	//查询所申请队列剩余空间,如果队列剩余空间大于0则可入队；
+	udRegVal = HalSecRead(en_dev, udSecEngineId,
+						  REG_SEC_INFO_QUEUE_BUF_SPACE_LEFT_0_127(udQueIndex));
+	if (udRegVal < 2) {
+		BTTL_PRINTF("queue:%u buf empty left:%u\n", udQueIndex, udRegVal);
+		return 1;
+	}
+	if (udRegVal > 0x20) {
+		BTTL_PRINTF("queue:%u buf left:%u\n", udQueIndex, udRegVal);
+		return 1;
+	}
+
+	//先写DTB_ADDR[63:32],接着写DTB_ADDR[31:0],最后写usdtb_len(软件需严格遵守该顺序）
+	udRet = HalSecWrite(en_dev, udSecEngineId,
+						REG_SEC_CFG_QUEUE_DTB_ADDR_H_0_127(udQueIndex),
+						pt->DtbAddrH);
+
+	// DH_LOG_INFO(MODULE_SEC, "pt->DtbAddrH = 0x%x\n",pt->DtbAddrH);
+	udRet = HalSecWrite(en_dev, udSecEngineId,
+						REG_SEC_CFG_QUEUE_DTB_ADDR_L_0_127(udQueIndex),
+						pt->DtbAddrL);
+
+	// DH_LOG_INFO(MODULE_SEC, "pt->DtbAddrL = 0x%x\n",pt->DtbAddrL);
+	// DH_LOG_INFO(MODULE_SEC, "pt->DtbAddrVir =
+	// 0x%llx\n",HalBttlVpaToVa(en_dev,(UINT64)((UINT64)pt->DtbAddrH)<<32)+pt->DtbAddrL);
+	// CMD寄存器最后配
+	udRet = HalSecWrite(en_dev, udSecEngineId,
+						REG_SEC_CFG_QUEUE_DTB_LEN_0_127(udQueIndex),
+						pt->DtbCmd);
+
+	// DH_LOG_INFO(MODULE_SEC, "pt->DtbCmd = 0x%x\n",pt->DtbCmd);
+	return 0;
 }
 
 /*
     sa下表模块测试
-    SA存放地址,第二套L2D uddSaL2DPhyAddr= 0x6201000000;理论上为68位，目前场景为64位
-    usdtb_len =30;
+    SA存放地址,第二套L2D uddSaL2DPhyAddr=
+   0x6201000000;理论上为68位，目前场景为64位 usdtb_len =30;
 */
-//E_SA_TYPE geSaType;
-
-UINT32 gudTestCnt = 0;
-UINT32 CmdkBttlTestSecDtbSaAdd(struct zxdh_en_device *en_dev,E_CMDK_DTB_SA_CMD_TYPE eDtbSaCmdType,E_SA_TYPE eSaType,UINT64 uddSaVirAddr,UINT32 udDtbSaIsIntEn,UINT32 udDtbLen,UINT32 udQueIndex)
+// E_SA_TYPE geSaType;
+
+UINT32 gudTestCnt;
+UINT32 CmdkBttlTestSecDtbSaAdd(struct zxdh_en_device *en_dev,
+							   E_CMDK_DTB_SA_CMD_TYPE eDtbSaCmdType,
+							   E_SA_TYPE eSaType, UINT64 uddSaVirAddr,
+							   UINT32 udDtbSaIsIntEn, UINT32 udDtbLen,
+							   UINT32 udQueIndex)
 {
-    /* int_en指示是否产生需要中断 第29位,cmd_type=0指示为流表下发命令，cmd_type=1指示为流表dump命令 第30位 一对sa表的大小为480字节，以16字节为单位*/
-    T_QUEUE_DTB_REG tDtbReg = {0};
-    UINT32 udDtbCmd = 0;
-    UINT64 uddSaPhaAddr = 0;
-    UINT32 udIsDtbAckFinish = 0;
-    UINT32 udDtbAckRsl = 0;
-    UINT32 udRet = 0;
-    int i = 0;
-
-
-    /*入参检查*/
-    //BTTL_PUB_ID_CHECK(en_dev, CMDK_BTTL_PUB_CHIP_MAX);
-    //BTTL_PUB_ID_CHECK(eDtbSaCmdType, E_DTB_SA_CMD_LAST);
-    PUB_CHECK_NULL_PTR_RET_ERR(en_dev);
-
-    uddSaPhaAddr = (UINT64)HalBttlVaToVpa(en_dev, uddSaVirAddr);
-    //BTTL_PUB_0_CHECK(uddSaPhaAddr);
-    DH_LOG_INFO(MODULE_SEC, "uddSaVirAddr:0x%llx,uddSaPhaAddr:0x%llx\n",uddSaVirAddr,uddSaPhaAddr);
-
-    //构造udDtbCmd
-    PUB_BIT_FIELD_SET64(udDtbCmd,udDtbLen>>4,0,10);
-    PUB_BIT_FIELD_SET64(udDtbCmd,eSaType,27,2);
-    PUB_BIT_FIELD_SET64(udDtbCmd,udDtbSaIsIntEn,29,1);
-    PUB_BIT_FIELD_SET64(udDtbCmd,eDtbSaCmdType,30,1);
-
-    tDtbReg.DtbAddrH = (UINT32)PUB_BIT_FIELD_RIGHT_JUST_GET64(uddSaPhaAddr,32,32);
-    tDtbReg.DtbAddrL = (UINT32)PUB_BIT_FIELD_RIGHT_JUST_GET64(uddSaPhaAddr,0,32);
-    tDtbReg.DtbCmd  = udDtbCmd;
-
-    /* 配置下表寄存器 */
-    for(i=0;i<gudDtbSaNum;i++)
-    {
-    //gudTestCnt++;
-    //(*(volatile UINT32*)(uddSaVirAddr + 16)) = PUB_NTOH32(gudTestCnt);
-        udRet = CmdkBttlSecSaDownload(en_dev,0,&tDtbReg,udQueIndex);
-        //PUB_CHECK_RET_VAL_RV(udRet);
-    }
-    /* 等待 */
-    msleep(1000);
-    // PubUsDelay(10); //等待多久需要微院确认
-
-    udRet = CmdkBttlTestSaAckRslGet(uddSaVirAddr,eDtbSaCmdType,&udIsDtbAckFinish,&udDtbAckRsl);
-    PUB_CHECK_RET_VAL_RV(udRet);
-
-    if((1 == udIsDtbAckFinish)&&(0xff == udDtbAckRsl))
-    {
-        return 0;
-    }
-    else
-    {
-        BTTL_PRINTF("CmdkBttlTestSa Dtb Ack is error!! udIsDtbAckFinish:%u,udDtbAckRsl:%u\n",udIsDtbAckFinish,udDtbAckRsl);
-        BttlPubDump((unsigned char *)uddSaVirAddr, 0x60);
-    return 1;
-    }
-
-    return 0;
+	/* int_en指示是否产生需要中断
+   * 第29位,cmd_type=0指示为流表下发命令，cmd_type=1指示为流表dump命令 第30位
+   * 一对sa表的大小为480字节，以16字节为单位*/
+	T_QUEUE_DTB_REG tDtbReg = { 0 };
+	UINT32 udDtbCmd = 0;
+	UINT64 uddSaPhaAddr = 0;
+	UINT32 udIsDtbAckFinish = 0;
+	UINT32 udDtbAckRsl = 0;
+	UINT32 udRet = 0;
+	int i = 0;
+
+	/*入参检查*/
+	// BTTL_PUB_ID_CHECK(en_dev, CMDK_BTTL_PUB_CHIP_MAX);
+	// BTTL_PUB_ID_CHECK(eDtbSaCmdType, E_DTB_SA_CMD_LAST);
+	PUB_CHECK_NULL_PTR_RET_ERR(en_dev);
+
+	uddSaPhaAddr = (UINT64)HalBttlVaToVpa(en_dev, uddSaVirAddr);
+	// BTTL_PUB_0_CHECK(uddSaPhaAddr);
+	DH_LOG_INFO(MODULE_SEC, "uddSaVirAddr:0x%llx,uddSaPhaAddr:0x%llx\n",
+				uddSaVirAddr, uddSaPhaAddr);
+
+	//构造udDtbCmd
+	PUB_BIT_FIELD_SET64(udDtbCmd, udDtbLen >> 4, 0, 10);
+	PUB_BIT_FIELD_SET64(udDtbCmd, eSaType, 27, 2);
+	PUB_BIT_FIELD_SET64(udDtbCmd, udDtbSaIsIntEn, 29, 1);
+	PUB_BIT_FIELD_SET64(udDtbCmd, eDtbSaCmdType, 30, 1);
+
+	tDtbReg.DtbAddrH =
+			(UINT32)PUB_BIT_FIELD_RIGHT_JUST_GET64(uddSaPhaAddr, 32, 32);
+	tDtbReg.DtbAddrL =
+			(UINT32)PUB_BIT_FIELD_RIGHT_JUST_GET64(uddSaPhaAddr, 0, 32);
+	tDtbReg.DtbCmd = udDtbCmd;
+
+	/* 配置下表寄存器 */
+	for (i = 0; i < gudDtbSaNum; i++) {
+		// gudTestCnt++;
+		//(*(volatile UINT32*)(uddSaVirAddr + 16)) = PUB_NTOH32(gudTestCnt);
+		udRet = CmdkBttlSecSaDownload(en_dev, 0, &tDtbReg, udQueIndex);
+		// PUB_CHECK_RET_VAL_RV(udRet);
+	}
+	/* 等待 */
+	msleep(1000);
+	// PubUsDelay(10); //等待多久需要微院确认
+
+	udRet = CmdkBttlTestSaAckRslGet(uddSaVirAddr, eDtbSaCmdType,
+									&udIsDtbAckFinish, &udDtbAckRsl);
+	PUB_CHECK_RET_VAL_RV(udRet);
+
+	if ((1 == udIsDtbAckFinish) && (0xff == udDtbAckRsl)) {
+		return 0;
+	} else {
+		BTTL_PRINTF("CmdkBttlTestSa Dtb Ack is error!! "
+					"udIsDtbAckFinish:%u,udDtbAckRsl:%u\n",
+					udIsDtbAckFinish, udDtbAckRsl);
+		BttlPubDump((unsigned char *)uddSaVirAddr, 0x60);
+		return 1;
+	}
+
+	return 0;
 }
 
 #if 1
 static int zxdh_ipsec_add_sa(struct xfrm_state *xs)
 {
-    struct xfrm_state_offload *xso = &xs->xso;
-    struct net_device *netdev = xso->dev;
-    struct zxdh_en_priv *en_priv = NULL;
-    //struct zxdh_en_device *en_dev = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    dma_addr_t dma_handle;
-    UINT32 dma_size = 0x1000;  //暂定4K,批量下表情况下需要更多
-
-    UINT64 uddDtbSaVirAddr = 0;
-    UINT32 udSaTblLen = 0;
-    int ret = 0;
-
-    en_priv = netdev_priv(netdev);
-    en_dev = &(en_priv->edev);
-
-    if(unlikely(en_dev->drs_sec_pri.SecVAddr == 0))
-    {
-        en_dev->drs_sec_pri.SecVAddr = (uint64_t)dma_alloc_coherent(netdev->dev.parent,dma_size,&dma_handle,GFP_KERNEL);
-        if(en_dev->drs_sec_pri.SecVAddr == 0)
-        {
-            DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_add_sa dma_alloc_coherent fail\n");
-            return -1;
-        }
-        en_dev->drs_sec_pri.SecPAddr = dma_handle;
-        en_dev->drs_sec_pri.SecMemSize = dma_size;
-    }
-    uddDtbSaVirAddr = en_dev->drs_sec_pri.SecVAddr;
-
-    DH_LOG_INFO(MODULE_SEC, "uddDtbSaVirAddr:0x%llx\n",uddDtbSaVirAddr);
-    //DH_LOG_INFO(MODULE_SEC, "xs:0x%llx\n",xs);
-
-    memset((void*)uddDtbSaVirAddr,0,1024);
-
-    //else if(1 == xs->xso.dir)
-    if(xso->flags & XFRM_OFFLOAD_INBOUND)
-    {
-        ret = zxdh_ipsec_dtb_in_sa_get(xs,(T_HAL_SA_DTB_HW_IN*)(uddDtbSaVirAddr+16));
-        if(ret != 0)
-        {
-            return 1;
-        }
-        BttlPubDump((unsigned char *)uddDtbSaVirAddr, 0x210);  //传入时加了16字节的回写空间
-
-        #if 1
-        udSaTblLen = 512 - 16;
-        CmdkBttlTestSecDtbSaAdd(en_dev,E_DTB_SA_CMD_FLOW_DOWN,E_SATYPE_IN,uddDtbSaVirAddr,0,udSaTblLen,2);
-
-        #endif
-    }
-    //if(2 == xs->xso.dir)
-    else
-    {
-        ret = zxdh_ipsec_dtb_out_sa_get(xs,(T_HAL_SA_DTB_HW_OUT*)(uddDtbSaVirAddr+16));
-        if(ret != 0)
-        {
-            return 1;
-        }
-        BttlPubDump((unsigned char *)uddDtbSaVirAddr, 0x110);  //传入时加了16字节的回写空间
-
-        #if 1
-        udSaTblLen = 256 - 16;
-        CmdkBttlTestSecDtbSaAdd(en_dev,E_DTB_SA_CMD_FLOW_DOWN,E_SATYPE_OUT,uddDtbSaVirAddr,0,udSaTblLen,2);
-        #endif
-    }
-
-    return 0;
+	struct xfrm_state_offload *xso = &xs->xso;
+	struct net_device *netdev = xso->dev;
+	struct zxdh_en_priv *en_priv = NULL;
+	// struct zxdh_en_device *en_dev = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	dma_addr_t dma_handle;
+	UINT32 dma_size = 0x1000; //暂定4K,批量下表情况下需要更多
+
+	UINT64 uddDtbSaVirAddr = 0;
+	UINT32 udSaTblLen = 0;
+	int ret = 0;
+
+	en_priv = netdev_priv(netdev);
+	en_dev = &(en_priv->edev);
+
+	if (unlikely(en_dev->drs_sec_pri.SecVAddr == 0)) {
+		en_dev->drs_sec_pri.SecVAddr = (uint64_t)dma_alloc_coherent(
+				netdev->dev.parent, dma_size, &dma_handle, GFP_KERNEL);
+		if (en_dev->drs_sec_pri.SecVAddr == 0) {
+			DH_LOG_INFO(MODULE_SEC,
+						"zxdh_ipsec_add_sa dma_alloc_coherent fail\n");
+			return -1;
+		}
+		en_dev->drs_sec_pri.SecPAddr = dma_handle;
+		en_dev->drs_sec_pri.SecMemSize = dma_size;
+	}
+	uddDtbSaVirAddr = en_dev->drs_sec_pri.SecVAddr;
+
+	DH_LOG_INFO(MODULE_SEC, "uddDtbSaVirAddr:0x%llx\n", uddDtbSaVirAddr);
+	// DH_LOG_INFO(MODULE_SEC, "xs:0x%llx\n",xs);
+
+	memset((void *)uddDtbSaVirAddr, 0, 1024);
+
+	// else if(1 == xs->xso.dir)
+	if (xso->flags & XFRM_OFFLOAD_INBOUND) {
+		ret = zxdh_ipsec_dtb_in_sa_get(
+				xs, (T_HAL_SA_DTB_HW_IN *)(uddDtbSaVirAddr + 16));
+		if (ret != 0) {
+			return 1;
+		}
+		BttlPubDump((unsigned char *)uddDtbSaVirAddr,
+					0x210); //传入时加了16字节的回写空间
+
+		udSaTblLen = 512 - 16;
+		CmdkBttlTestSecDtbSaAdd(en_dev, E_DTB_SA_CMD_FLOW_DOWN, E_SATYPE_IN,
+								uddDtbSaVirAddr, 0, udSaTblLen, 2);
+	}
+	// if(2 == xs->xso.dir)
+	else {
+		ret = zxdh_ipsec_dtb_out_sa_get(
+				xs, (T_HAL_SA_DTB_HW_OUT *)(uddDtbSaVirAddr + 16));
+		if (ret != 0) {
+			return 1;
+		}
+		BttlPubDump((unsigned char *)uddDtbSaVirAddr,
+					0x110); //传入时加了16字节的回写空间
+
+		udSaTblLen = 256 - 16;
+		CmdkBttlTestSecDtbSaAdd(en_dev, E_DTB_SA_CMD_FLOW_DOWN, E_SATYPE_OUT,
+								uddDtbSaVirAddr, 0, udSaTblLen, 2);
+	}
+
+	return 0;
 }
 
 void zxdh_ipsec_del_sa(struct xfrm_state *xs)
 {
-    DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_del_sa\n");
-    return;
+	DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_del_sa\n");
+	return;
 }
 
 bool zxdh_ipsec_offload_ok(struct sk_buff *skb, struct xfrm_state *xs)
 {
-    DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_offload_ok\n");
-    return true;
+	DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_offload_ok\n");
+	return true;
 }
 
-void zxdh_ipsec_state_advance_esn (struct xfrm_state *x)
+void zxdh_ipsec_state_advance_esn(struct xfrm_state *x)
 {
-    DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_state_advance_esn\n");
-    return;
+	DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_state_advance_esn\n");
+	return;
 }
-void zxdh_ipsec_state_update_curlft (struct xfrm_state *x)
+void zxdh_ipsec_state_update_curlft(struct xfrm_state *x)
 {
-    DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_state_update_curlft\n");
-    return ;
+	DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_state_update_curlft\n");
+	return;
 }
-int zxdh_ipsec_policy_add (struct xfrm_policy *x)
+int zxdh_ipsec_policy_add(struct xfrm_policy *x)
 {
-#if 1
-    int32_t ret = 0;
-    UINT8 aucSip[4] = {0xc8,0xfe,0x00,0x1};
-    UINT8 aucDip[4] = {0xc8,0xfe,0x00,0x2};
-    UINT8 aucSipMask[4] = {0xff,0xff,0x00,0x0};
-    UINT8 aucDipMask[4] = {0xff,0xff,0x00,0x0};
-    /*6.2的内核才有*/
-    //struct xfrm_dev_offload *xdo = &x->xdo;
-    //struct net_device *netdev = xdo->dev;
-    struct net_device *netdev = NULL; //低版本内核仅编译通过
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    DPP_PF_INFO_T pf_info = {0};
-
-    DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_policy_add\n");
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    /*np下表 inline sec模式 打开*/
-    ret = dpp_egr_port_attr_set(&pf_info,EGR_FLAG_INLINE_SEC_OFFLOAD,1);
-    if (ret != 0)
-    {
-        LOG_ERR("Failed to set port_attr EGR_FLAG_INLINE_SEC_OFFLOAD !\n");
-    }
-
-    /*配置np ipset加密表*/
-    ret = dpp_ipsec_enc_entry_add(&pf_info,0,aucSip,aucDip,aucSipMask,aucDipMask,1,0x80001);
-    if (ret != 0)
-    {
-        LOG_ERR("xfrm policy dpp_ipsec_enc_entry_add Failed!\n");
-    }
-#endif
-
-    return 0;
+	int32_t ret = 0;
+	UINT8 aucSip[4] = { 0xc8, 0xfe, 0x00, 0x1 };
+	UINT8 aucDip[4] = { 0xc8, 0xfe, 0x00, 0x2 };
+	UINT8 aucSipMask[4] = { 0xff, 0xff, 0x00, 0x0 };
+	UINT8 aucDipMask[4] = { 0xff, 0xff, 0x00, 0x0 };
+	/*6.2的内核才有*/
+	// struct xfrm_dev_offload *xdo = &x->xdo;
+	// struct net_device *netdev = xdo->dev;
+	struct net_device *netdev = NULL; //低版本内核仅编译通过
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_policy_add\n");
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	/*np下表 inline sec模式 打开*/
+	ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_INLINE_SEC_OFFLOAD, 1);
+	if (ret != 0) {
+		LOG_ERR("Failed to set port_attr EGR_FLAG_INLINE_SEC_OFFLOAD !\n");
+	}
+
+	/*配置np ipset加密表*/
+	ret = dpp_ipsec_enc_entry_add(&pf_info, 0, aucSip, aucDip, aucSipMask,
+								  aucDipMask, 1, 0x80001);
+	if (ret != 0) {
+		LOG_ERR("xfrm policy dpp_ipsec_enc_entry_add Failed!\n");
+	}
+
+	return 0;
 }
-void zxdh_ipsec_policy_delete (struct xfrm_policy *x)
+void zxdh_ipsec_policy_delete(struct xfrm_policy *x)
 {
-    DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_policy_delete\n");
-    return;
+	DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_policy_delete\n");
+	return;
 }
-void zxdh_ipsec_policy_free (struct xfrm_policy *x)
+void zxdh_ipsec_policy_free(struct xfrm_policy *x)
 {
-    DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_policy_free\n");
-    return;
+	DH_LOG_INFO(MODULE_SEC, "zxdh_ipsec_policy_free\n");
+	return;
 }
 
-const struct xfrmdev_ops zxdh_xfrmdev_ops =
-{
-    .xdo_dev_state_add = zxdh_ipsec_add_sa,
-    .xdo_dev_state_delete = zxdh_ipsec_del_sa,
-    .xdo_dev_offload_ok = zxdh_ipsec_offload_ok,
-    //.xdo_dev_state_advance_esn = zxdh_ipsec_state_advance_esn,
-    //.xdo_dev_state_update_curlft = zxdh_ipsec_state_update_curlft,
-    //.xdo_dev_policy_add = zxdh_ipsec_policy_add,
-    //.xdo_dev_policy_free = zxdh_ipsec_policy_free,
+const struct xfrmdev_ops zxdh_xfrmdev_ops = {
+	.xdo_dev_state_add = zxdh_ipsec_add_sa,
+	.xdo_dev_state_delete = zxdh_ipsec_del_sa,
+	.xdo_dev_offload_ok = zxdh_ipsec_offload_ok,
+	//.xdo_dev_state_advance_esn = zxdh_ipsec_state_advance_esn,
+	//.xdo_dev_state_update_curlft = zxdh_ipsec_state_update_curlft,
+	//.xdo_dev_policy_add = zxdh_ipsec_policy_add,
+	//.xdo_dev_policy_free = zxdh_ipsec_policy_free,
 };
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/drs_sec_dtb.h b/src/net/drivers/net/ethernet/dinghai/en_aux/drs_sec_dtb.h
old mode 100755
new mode 100644
index ed07b7ffca144df3c21b029bf7211f9a411162e2..346870bb8efc3976ca6aee6fe63b5e7d75598240
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/drs_sec_dtb.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/drs_sec_dtb.h
@@ -19,67 +19,62 @@
 #ifndef DRS_SEC_DTB_H
 #define DRS_SEC_DTB_H
 /*同步pub宏定义*/
-typedef void                VOID;
-typedef float               FLOAT;
-typedef double              DOUBLE;
-
-typedef signed char         INT8;
-typedef unsigned char       UINT8;
-
-typedef char                CHAR;
-
-
-typedef signed short        INT16;
-typedef unsigned short      UINT16;
-
-typedef signed int          INT32;
-typedef unsigned int        UINT32;
-
-
-typedef signed long long    INT64;
-typedef unsigned long long  UINT64;
-
-#define BITWIDTH1                     ((UINT32)0x00000001)
-#define BITWIDTH2                     ((UINT32)0x00000003)
-#define BITWIDTH3                     ((UINT32)0x00000007)
-#define BITWIDTH4                     ((UINT32)0x0000000f)
-#define BITWIDTH5                     ((UINT32)0x0000001f)
-#define BITWIDTH6                     ((UINT32)0x0000003f)
-#define BITWIDTH7                     ((UINT32)0x0000007f)
-#define BITWIDTH8                     ((UINT32)0x000000ff)
-#define BITWIDTH9                     ((UINT32)0x000001ff)
-#define BITWIDTH10                    ((UINT32)0x000003ff)
-#define BITWIDTH11                    ((UINT32)0x000007ff)
-#define BITWIDTH12                    ((UINT32)0x00000fff)
-#define BITWIDTH13                    ((UINT32)0x00001fff)
-#define BITWIDTH14                    ((UINT32)0x00003fff)
-#define BITWIDTH15                    ((UINT32)0x00007fff)
-#define BITWIDTH16                    ((UINT32)0x0000ffff)
-#define BITWIDTH17                    ((UINT32)0x0001ffff)
-#define BITWIDTH18                    ((UINT32)0x0003ffff)
-#define BITWIDTH19                    ((UINT32)0x0007ffff)
-#define BITWIDTH20                    ((UINT32)0x000fffff)
-#define BITWIDTH21                    ((UINT32)0x001fffff)
-#define BITWIDTH22                    ((UINT32)0x003fffff)
-#define BITWIDTH23                    ((UINT32)0x007fffff)
-#define BITWIDTH24                    ((UINT32)0x00ffffff)
-#define BITWIDTH25                    ((UINT32)0x01ffffff)
-#define BITWIDTH26                    ((UINT32)0x03ffffff)
-#define BITWIDTH27                    ((UINT32)0x07ffffff)
-#define BITWIDTH28                    ((UINT32)0x0fffffff)
-#define BITWIDTH29                    ((UINT32)0x1fffffff)
-#define BITWIDTH30                    ((UINT32)0x3fffffff)
-#define BITWIDTH31                    ((UINT32)0x7fffffff)
-#define BITWIDTH32                    ((UINT32)0xffffffff)
-
-
-
-#define PUB_OK                          (0)
-#define PUB_ERROR                       (0xffffffff)/*直接定义为0xffffffff*/
-
-#define BTTL_PRINTF(fmt, arg...)               DH_LOG_INFO(MODULE_SEC, fmt, ##arg)
-#define BTTL_PUB_PRINT_ERROR(fmt, arg...)      DH_LOG_ERR(MODULE_SEC, fmt, ##arg)
-
+typedef void VOID;
+typedef float FLOAT;
+typedef double DOUBLE;
+
+typedef signed char INT8;
+typedef unsigned char UINT8;
+
+typedef char CHAR;
+
+typedef signed short INT16;
+typedef unsigned short UINT16;
+
+typedef signed int INT32;
+typedef unsigned int UINT32;
+
+typedef signed long long INT64;
+typedef unsigned long long UINT64;
+
+#define BITWIDTH1 ((UINT32)0x00000001)
+#define BITWIDTH2 ((UINT32)0x00000003)
+#define BITWIDTH3 ((UINT32)0x00000007)
+#define BITWIDTH4 ((UINT32)0x0000000f)
+#define BITWIDTH5 ((UINT32)0x0000001f)
+#define BITWIDTH6 ((UINT32)0x0000003f)
+#define BITWIDTH7 ((UINT32)0x0000007f)
+#define BITWIDTH8 ((UINT32)0x000000ff)
+#define BITWIDTH9 ((UINT32)0x000001ff)
+#define BITWIDTH10 ((UINT32)0x000003ff)
+#define BITWIDTH11 ((UINT32)0x000007ff)
+#define BITWIDTH12 ((UINT32)0x00000fff)
+#define BITWIDTH13 ((UINT32)0x00001fff)
+#define BITWIDTH14 ((UINT32)0x00003fff)
+#define BITWIDTH15 ((UINT32)0x00007fff)
+#define BITWIDTH16 ((UINT32)0x0000ffff)
+#define BITWIDTH17 ((UINT32)0x0001ffff)
+#define BITWIDTH18 ((UINT32)0x0003ffff)
+#define BITWIDTH19 ((UINT32)0x0007ffff)
+#define BITWIDTH20 ((UINT32)0x000fffff)
+#define BITWIDTH21 ((UINT32)0x001fffff)
+#define BITWIDTH22 ((UINT32)0x003fffff)
+#define BITWIDTH23 ((UINT32)0x007fffff)
+#define BITWIDTH24 ((UINT32)0x00ffffff)
+#define BITWIDTH25 ((UINT32)0x01ffffff)
+#define BITWIDTH26 ((UINT32)0x03ffffff)
+#define BITWIDTH27 ((UINT32)0x07ffffff)
+#define BITWIDTH28 ((UINT32)0x0fffffff)
+#define BITWIDTH29 ((UINT32)0x1fffffff)
+#define BITWIDTH30 ((UINT32)0x3fffffff)
+#define BITWIDTH31 ((UINT32)0x7fffffff)
+#define BITWIDTH32 ((UINT32)0xffffffff)
+
+#define PUB_OK (0)
+#define PUB_ERROR (0xffffffff) /*直接定义为0xffffffff*/
+
+#define BTTL_PRINTF(fmt, arg...) DH_LOG_INFO(MODULE_SEC, fmt, ##arg)
+#define BTTL_PUB_PRINT_ERROR(fmt, arg...) DH_LOG_ERR(MODULE_SEC, fmt, ##arg)
 
 /* 寄存器单bit位操作 */
 
@@ -90,7 +85,7 @@ typedef unsigned long long  UINT64;
 #define PUB_BIT_CLEAR(reg, bit) ((reg) = ((reg) & (~(1u << (bit)))))
 
 /** 获取某bit的值 (0/1) */
-#define PUB_GET_BIT_VAL(reg, bit) (((reg)>> (bit)) & 1u)
+#define PUB_GET_BIT_VAL(reg, bit) (((reg) >> (bit)) & 1u)
 
 /** 判断某bit的值是否为1 */
 #define PUB_IS_BIT_SET(reg, pos) (((reg) & (1u << (pos))) != 0x0u)
@@ -99,439 +94,436 @@ typedef unsigned long long  UINT64;
 #define PUB_IS_BIT_CLEAR(reg, pos) (((reg) & (1u << (pos))) == 0x0u)
 
 /** 某bit位填写值val,其他bit不变 */
-#define PUB_BIT_INSR(reg, bit, val)                                       \
-    ((reg) = (((reg) & (~(1u << (bit)))) | (((val) & 1u) << (bit))))
-
+#define PUB_BIT_INSR(reg, bit, val) \
+	((reg) = (((reg) & (~(1u << (bit)))) | (((val)&1u) << (bit))))
 
 #define PUB_BIT_FIELD_MASK_GET64(bitoff, bitfieldlen) \
-((((UINT64)0x01 << (bitfieldlen)) - 1) << (bitoff))
+	((((UINT64)0x01 << (bitfieldlen)) - 1) << (bitoff))
 
 #define PUB_BIT_FIELD_GET64(val, bitoff, bitfieldlen) \
-((val) & PUB_BIT_FIELD_MASK_GET64(bitoff, bitfieldlen))
+	((val)&PUB_BIT_FIELD_MASK_GET64(bitoff, bitfieldlen))
 
-#define PUB_BIT_FIELD_SET64(var, val, bitoff, bitlen) \
-((var) = (((var) & (~ PUB_BIT_FIELD_MASK_GET64(bitoff, bitlen))) | (((UINT64)val) << (bitoff))))
+#define PUB_BIT_FIELD_SET64(var, val, bitoff, bitlen)                 \
+	((var) = (((var) & (~PUB_BIT_FIELD_MASK_GET64(bitoff, bitlen))) | \
+			  (((UINT64)val) << (bitoff))))
 
 #define PUB_BIT_FIELD_RIGHT_JUST_GET64(val, bitoff, bitfieldlen) \
-(((val) >> (bitoff)) & (((UINT64)0x01 << (bitfieldlen)) - 1))
+	(((val) >> (bitoff)) & (((UINT64)0x01 << (bitfieldlen)) - 1))
 
 /** 检查空指针，返回错误 */
-#define PUB_CHECK_NULL_PTR_RET_ERR(ptr)  \
-    do{\
-        if(NULL == ptr){\
-            DH_LOG_INFO(MODULE_SEC, "Null Ptr Err! Fuc:%s,Line:%d,File:%s\n", __FUNCTION__,__LINE__,__FILE__);\
-            return PUB_ERROR;\
-        }\
-    }while(0)
+#define PUB_CHECK_NULL_PTR_RET_ERR(ptr)                                       \
+	do {                                                                      \
+		if (NULL == ptr) {                                                    \
+			DH_LOG_INFO(MODULE_SEC, "Null Ptr Err! Fuc:%s,Line:%d,File:%s\n", \
+						__FUNCTION__, __LINE__, __FILE__);                    \
+			return PUB_ERROR;                                                 \
+		}                                                                     \
+	} while (0)
 
 /** 检查空指针，返回VOID */
-#define PUB_CHECK_NULL_PTR_RET_VOID(ptr)  \
-    do{\
-        if(NULL == ptr){\
-            DH_LOG_INFO(MODULE_SEC, "Null Ptr Err! Fuc:%s,Line:%d,File:%s\n", __FUNCTION__,__LINE__,__FILE__);\
-            return;\
-        }\
-    }while(0)
-
-#define PUB_CHECK_RET_VAL_RV(expr) \
-    do {    \
-        UINT32 _ret = (expr);    \
-        if (PUB_OK != _ret) \
-        {   \
-            DH_LOG_INFO(MODULE_SEC, "%s Error,Line:%d,Ret:0x%x\n", __FUNCTION__,__LINE__,_ret);   \
-            return _ret;    \
-        }   \
-    } while (0)
-
-#define BTTL_PUB_ID_CHECK(id, cmpid)  \
-    do{\
-        if(cmpid <= (id)){\
-            DH_LOG_INFO(MODULE_SEC, " ID %d <= %d check Err! Fuc:%s,Line:%d,File:%s\n", id, cmpid, __FUNCTION__,__LINE__,__FILE__);\
-            return 1;\
-        }\
-    }while(0)
-
-#define BTTL_PUB_0_CHECK(value)   \
-    do{\
-        if(0 == (value)){\
-            DH_LOG_INFO(MODULE_SEC, " value %x 0 check Err! Fuc:%s,Line:%d,File:%s\n", value, __FUNCTION__,__LINE__,__FILE__);\
-            return E_INVALID_VALUE;\
-        }\
-    }while(0)
+#define PUB_CHECK_NULL_PTR_RET_VOID(ptr)                                      \
+	do {                                                                      \
+		if (NULL == ptr) {                                                    \
+			DH_LOG_INFO(MODULE_SEC, "Null Ptr Err! Fuc:%s,Line:%d,File:%s\n", \
+						__FUNCTION__, __LINE__, __FILE__);                    \
+			return;                                                           \
+		}                                                                     \
+	} while (0)
+
+#define PUB_CHECK_RET_VAL_RV(expr)                                 \
+	do {                                                           \
+		UINT32 _ret = (expr);                                      \
+		if (PUB_OK != _ret) {                                      \
+			DH_LOG_INFO(MODULE_SEC, "%s Error,Line:%d,Ret:0x%x\n", \
+						__FUNCTION__, __LINE__, _ret);             \
+			return _ret;                                           \
+		}                                                          \
+	} while (0)
+
+#define BTTL_PUB_ID_CHECK(id, cmpid)                                        \
+	do {                                                                    \
+		if (cmpid <= (id)) {                                                \
+			DH_LOG_INFO(MODULE_SEC,                                         \
+						" ID %d <= %d check Err! Fuc:%s,Line:%d,File:%s\n", \
+						id, cmpid, __FUNCTION__, __LINE__, __FILE__);       \
+			return 1;                                                       \
+		}                                                                   \
+	} while (0)
+
+#define BTTL_PUB_0_CHECK(value)                                            \
+	do {                                                                   \
+		if (0 == (value)) {                                                \
+			DH_LOG_INFO(MODULE_SEC,                                        \
+						" value %x 0 check Err! Fuc:%s,Line:%d,File:%s\n", \
+						value, __FUNCTION__, __LINE__, __FILE__);          \
+			return E_INVALID_VALUE;                                        \
+		}                                                                  \
+	} while (0)
 
 /* 大小端操作 */
 /** 16位数据大小端转换 */
-#define PUB_SWAP16(x)  ((UINT16)((((x) >> 8) & 0xffu) | (((x) & 0xffu) << 8)))
+#define PUB_SWAP16(x) ((UINT16)((((x) >> 8) & 0xffu) | (((x)&0xffu) << 8)))
 /** 32位数据大小端转换 */
-#define PUB_SWAP32(x) \
-    ((UINT32)( \
-        (((UINT32)(x) & (UINT32)0x000000ffUL) << 24) | \
-        (((UINT32)(x) & (UINT32)0x0000ff00UL) <<  8) | \
-        (((UINT32)(x) & (UINT32)0x00ff0000UL) >>  8) | \
-        (((UINT32)(x) & (UINT32)0xff000000UL) >> 24) ))
+#define PUB_SWAP32(x)                                        \
+	((UINT32)((((UINT32)(x) & (UINT32)0x000000ffUL) << 24) | \
+			  (((UINT32)(x) & (UINT32)0x0000ff00UL) << 8) |  \
+			  (((UINT32)(x) & (UINT32)0x00ff0000UL) >> 8) |  \
+			  (((UINT32)(x) & (UINT32)0xff000000UL) >> 24)))
 /** 64位数据大小端转换 */
-#define PUB_SWAP64(x) \
-    ((UINT64)( \
-        (((UINT64)(x) & (UINT64)0x00000000000000ffUL) << 56) | \
-        (((UINT64)(x) & (UINT64)0x000000000000ff00UL) << 40) | \
-        (((UINT64)(x) & (UINT64)0x0000000000ff0000UL) << 24) | \
-        (((UINT64)(x) & (UINT64)0x00000000ff000000UL) << 8 ) | \
-        (((UINT64)(x) & (UINT64)0x000000ff00000000UL) >> 8 ) | \
-        (((UINT64)(x) & (UINT64)0x0000ff0000000000UL) >> 24) | \
-        (((UINT64)(x) & (UINT64)0x00ff000000000000UL) >> 40) | \
-        (((UINT64)(x) & (UINT64)0xff00000000000000UL) >> 56) ))
-
+#define PUB_SWAP64(x)                                                \
+	((UINT64)((((UINT64)(x) & (UINT64)0x00000000000000ffUL) << 56) | \
+			  (((UINT64)(x) & (UINT64)0x000000000000ff00UL) << 40) | \
+			  (((UINT64)(x) & (UINT64)0x0000000000ff0000UL) << 24) | \
+			  (((UINT64)(x) & (UINT64)0x00000000ff000000UL) << 8) |  \
+			  (((UINT64)(x) & (UINT64)0x000000ff00000000UL) >> 8) |  \
+			  (((UINT64)(x) & (UINT64)0x0000ff0000000000UL) >> 24) | \
+			  (((UINT64)(x) & (UINT64)0x00ff000000000000UL) >> 40) | \
+			  (((UINT64)(x) & (UINT64)0xff00000000000000UL) >> 56)))
 
 /* 已知数据的大小端，转换为网络序 */
-#define PUB_LE_TO_NET16(x)      PUB_SWAP16(x)   /**< 将小端数据转换为网络序 */
-#define PUB_LE_TO_NET32(x)      PUB_SWAP32(x)   /**< 将小端数据转换为网络序 */
-#define PUB_LE_TO_NET64(x)      PUB_SWAP64(x)   /**< 将小端数据转换为网络序 */
-#define PUB_DE_TO_NET16(x)      (x)             /**< 将大端数据转换为网络序 */
-#define PUB_DE_TO_NET32(x)      (x)             /**< 将大端数据转换为网络序 */
-#define PUB_DE_TO_NET64(x)      (x)             /**< 将大端数据转换为网络序 */
-
+#define PUB_LE_TO_NET16(x) PUB_SWAP16(x) /**< 将小端数据转换为网络序 */
+#define PUB_LE_TO_NET32(x) PUB_SWAP32(x) /**< 将小端数据转换为网络序 */
+#define PUB_LE_TO_NET64(x) PUB_SWAP64(x) /**< 将小端数据转换为网络序 */
+#define PUB_DE_TO_NET16(x) (x) /**< 将大端数据转换为网络序 */
+#define PUB_DE_TO_NET32(x) (x) /**< 将大端数据转换为网络序 */
+#define PUB_DE_TO_NET64(x) (x) /**< 将大端数据转换为网络序 */
 
 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 
-#define PUB_LE_TO_HOST16(x)     PUB_SWAP16(x)   /**< 小端16位数据转换为主机序 */
-#define PUB_LE_TO_HOST32(x)     PUB_SWAP32(x)   /**< 小端32位数据转换为主机序 */
-#define PUB_LE_TO_HOST64(x)     PUB_SWAP64(x)   /**< 小端64位数据转换为主机序 */
-#define PUB_DE_TO_HOST16(x)     (x)             /**< 大端16位数据转换为主机序 */
-#define PUB_DE_TO_HOST32(x)     (x)             /**< 大端32位数据转换为主机序 */
-#define PUB_DE_TO_HOST64(x)     (x)             /**< 大端64位数据转换为主机序 */
-#define PUB_HTON16(x)           (x)             /**< 16位数据主机序转换为网络序 */
-#define PUB_HTON32(x)           (x)             /**< 32位数据主机序转换为网络序 */
-#define PUB_HTON64(x)           (x)             /**< 64位数据主机序转换为网络序 */
-#define PUB_NTOH16(x)           (x)             /**< 16位数据网络序转换为主机序 */
-#define PUB_NTOH32(x)           (x)             /**< 32位数据网络序转换为主机序 */
-#define PUB_NTOH64(x)           (x)             /**< 64位数据网络序转换为主机序 */
-
+#define PUB_LE_TO_HOST16(x) PUB_SWAP16(x) /**< 小端16位数据转换为主机序 */
+#define PUB_LE_TO_HOST32(x) PUB_SWAP32(x) /**< 小端32位数据转换为主机序 */
+#define PUB_LE_TO_HOST64(x) PUB_SWAP64(x) /**< 小端64位数据转换为主机序 */
+#define PUB_DE_TO_HOST16(x) (x) /**< 大端16位数据转换为主机序 */
+#define PUB_DE_TO_HOST32(x) (x) /**< 大端32位数据转换为主机序 */
+#define PUB_DE_TO_HOST64(x) (x) /**< 大端64位数据转换为主机序 */
+#define PUB_HTON16(x) (x) /**< 16位数据主机序转换为网络序 */
+#define PUB_HTON32(x) (x) /**< 32位数据主机序转换为网络序 */
+#define PUB_HTON64(x) (x) /**< 64位数据主机序转换为网络序 */
+#define PUB_NTOH16(x) (x) /**< 16位数据网络序转换为主机序 */
+#define PUB_NTOH32(x) (x) /**< 32位数据网络序转换为主机序 */
+#define PUB_NTOH64(x) (x) /**< 64位数据网络序转换为主机序 */
 
 #else
-#define PUB_LE_TO_HOST16(x)     (x)
-#define PUB_LE_TO_HOST32(x)     (x)
-#define PUB_LE_TO_HOST64(x)     (x)
-#define PUB_DE_TO_HOST16(x)     PUB_SWAP16(x)
-#define PUB_DE_TO_HOST32(x)     PUB_SWAP32(x)
-#define PUB_DE_TO_HOST64(x)     PUB_SWAP64(x)
-#define PUB_HTON16(x)           PUB_SWAP16(x)
-#define PUB_HTON32(x)           PUB_SWAP32(x)
-#define PUB_HTON64(x)           PUB_SWAP64(x)
-#define PUB_NTOH16(x)           PUB_SWAP16(x)
-#define PUB_NTOH32(x)           PUB_SWAP32(x)
-#define PUB_NTOH64(x)           PUB_SWAP64(x)
-
+#define PUB_LE_TO_HOST16(x) (x)
+#define PUB_LE_TO_HOST32(x) (x)
+#define PUB_LE_TO_HOST64(x) (x)
+#define PUB_DE_TO_HOST16(x) PUB_SWAP16(x)
+#define PUB_DE_TO_HOST32(x) PUB_SWAP32(x)
+#define PUB_DE_TO_HOST64(x) PUB_SWAP64(x)
+#define PUB_HTON16(x) PUB_SWAP16(x)
+#define PUB_HTON32(x) PUB_SWAP32(x)
+#define PUB_HTON64(x) PUB_SWAP64(x)
+#define PUB_NTOH16(x) PUB_SWAP16(x)
+#define PUB_NTOH32(x) PUB_SWAP32(x)
+#define PUB_NTOH64(x) PUB_SWAP64(x)
 
 #endif
 
 /*因为SEC下表和NP下表硬件基本一样,这里同步NP关于EPID等定义*/
-#define VF_ACTIVE(VPORT)            ((VPORT & 0x0800) >> 11)
-#define EPID(VPORT)                 ((VPORT & 0x7000) >> 12)
-#define FUNC_NUM(VPORT)             ((VPORT & 0x0700) >> 8)
-#define VFUNC_NUM(VPORT)            ((VPORT & 0x00FF))
+#define VF_ACTIVE(VPORT) ((VPORT & 0x0800) >> 11)
+#define EPID(VPORT) ((VPORT & 0x7000) >> 12)
+#define FUNC_NUM(VPORT) ((VPORT & 0x0700) >> 8)
+#define VFUNC_NUM(VPORT) ((VPORT & 0x00FF))
 
-#define PF_VQM_VFID_OFFSET          (1152)
-#define IS_PF(VPORT)                (!VF_ACTIVE(VPORT))
-#define VQM_VFID(VPORT)             (IS_PF(VPORT) ? \
-                                    (PF_VQM_VFID_OFFSET + EPID(VPORT) * 8 + FUNC_NUM(VPORT)) : \
-                                    (EPID(VPORT) * 256 + VFUNC_NUM(VPORT)))
+#define PF_VQM_VFID_OFFSET (1152)
+#define IS_PF(VPORT) (!VF_ACTIVE(VPORT))
+#define VQM_VFID(VPORT)                                                        \
+	(IS_PF(VPORT) ? (PF_VQM_VFID_OFFSET + EPID(VPORT) * 8 + FUNC_NUM(VPORT)) : \
+					  (EPID(VPORT) * 256 + VFUNC_NUM(VPORT)))
 
-#define OWNER_PF_VQM_VFID(VPORT)    (PF_VQM_VFID_OFFSET + EPID(VPORT) * 8 + FUNC_NUM(VPORT))
-#define OWNER_PF_VPORT(VPORT)       (((EPID(VPORT)) << 12) | ((FUNC_NUM(VPORT)) << 8))
+#define OWNER_PF_VQM_VFID(VPORT) \
+	(PF_VQM_VFID_OFFSET + EPID(VPORT) * 8 + FUNC_NUM(VPORT))
+#define OWNER_PF_VPORT(VPORT) (((EPID(VPORT)) << 12) | ((FUNC_NUM(VPORT)) << 8))
 
-#define VQM_VFID_MAX_NUM            (2048)
+#define VQM_VFID_MAX_NUM (2048)
 
 /*vport格式
 15 |14 13 12 |     11    |10  9  8|7 6 5 4 3 2 1 0|
 rsv| ep_id   |func_active|func_num|    vfunc_num  |
 */
-#define VPORT_EPID_BT_START          (12)  /*EPID起始位*/
-#define VPORT_EPID_BT_LEN            (3)  /*EPID长度*/
-#define VPORT_FUNC_ACTIVE_BT_START   (11)  /*FUNC_ACTIVE起始位*/
-#define VPORT_FUNC_ACTIVE_BT_LEN     (1)  /*FUNC_ACTIVE长度*/
-#define VPORT_FUNC_NUM_BT_START      (8)  /*FUNC_NUM起始位*/
-#define VPORT_FUNC_NUM_BT_LEN        (3)  /*FUNC_NUM长度*/
-#define VPORT_VFUNC_NUM_BT_START     (0)  /*FUNC_NUM起始位*/
-#define VPORT_VFUNC_NUM_BT_LEN       (8)  /*FUNC_NUM长度*/
+#define VPORT_EPID_BT_START (12) /*EPID起始位*/
+#define VPORT_EPID_BT_LEN (3) /*EPID长度*/
+#define VPORT_FUNC_ACTIVE_BT_START (11) /*FUNC_ACTIVE起始位*/
+#define VPORT_FUNC_ACTIVE_BT_LEN (1) /*FUNC_ACTIVE长度*/
+#define VPORT_FUNC_NUM_BT_START (8) /*FUNC_NUM起始位*/
+#define VPORT_FUNC_NUM_BT_LEN (3) /*FUNC_NUM长度*/
+#define VPORT_VFUNC_NUM_BT_START (0) /*FUNC_NUM起始位*/
+#define VPORT_VFUNC_NUM_BT_LEN (8) /*FUNC_NUM长度*/
 
 /**
-* @name 通用寄存器操作宏
-* @brief 读寄存器宏定义
-* @{
-*/
-#define PUB_READ_REG8(addr)                 (*(volatile UINT8 *)(addr))   /**< 读8位寄存器 */
-#define PUB_READ_REG16(addr)                (*(volatile UINT16 *)(addr))  /**< 读16位寄存器 */
-#define PUB_READ_REG32(addr)                (*(volatile UINT32 *)(addr))  /**< 读32位寄存器 */
+ * @name 通用寄存器操作宏
+ * @brief 读寄存器宏定义
+ * @{
+ */
+#define PUB_READ_REG8(addr) (*(volatile UINT8 *)(addr)) /**< 读8位寄存器 */
+#define PUB_READ_REG16(addr) (*(volatile UINT16 *)(addr)) /**< 读16位寄存器 */
+#define PUB_READ_REG32(addr) (*(volatile UINT32 *)(addr)) /**< 读32位寄存器 */
 /** @} 通用寄存器操作宏 */
 
 /**
-* @name 通用寄存器操作宏
-* @brief 写寄存器宏定义
-* @{
-*/
-#define PUB_WRITE_REG8(addr, val_8)         (*(volatile UINT8 *)(addr) = val_8)    /**< 写8位寄存器 */
-#define PUB_WRITE_REG16(addr, val_16)       (*(volatile UINT16 *)(addr) = val_16)  /**< 写16位寄存器 */
-#define PUB_WRITE_REG32(addr, val_32)       (*(volatile UINT32 *)(addr) = val_32)  /**< 写32位寄存器 */
+ * @name 通用寄存器操作宏
+ * @brief 写寄存器宏定义
+ * @{
+ */
+#define PUB_WRITE_REG8(addr, val_8) \
+	(*(volatile UINT8 *)(addr) = val_8) /**< 写8位寄存器 */
+#define PUB_WRITE_REG16(addr, val_16) \
+	(*(volatile UINT16 *)(addr) = val_16) /**< 写16位寄存器 */
+#define PUB_WRITE_REG32(addr, val_32) \
+	(*(volatile UINT32 *)(addr) = val_32) /**< 写32位寄存器 */
 /** @} 通用寄存器操作宏 */
 
-
 /*寄存器偏移定义*/
-#define REG_SEC_IDX_OFFSET             (0x800000)        /* SEC内部基地址偏移 */
+#define REG_SEC_IDX_OFFSET (0x800000) /* SEC内部基地址偏移 */
 
-#define REG_SEC_TOP_DTB_OFFSET         (0)        /*host驱动 这里为0,因为就是从dtb开始映射的*/
+#define REG_SEC_TOP_DTB_OFFSET (0) /*host驱动 这里为0,因为就是从dtb开始映射的*/
 /* CFG_QUEUE_DTB_ADDR_H_0_127 虚机队列入队的高地址寄存器 n=0~127 */
-#define REG_SEC_CFG_QUEUE_DTB_ADDR_H_0_127(n)     (REG_SEC_TOP_DTB_OFFSET + 0x0000 + n*32)
+#define REG_SEC_CFG_QUEUE_DTB_ADDR_H_0_127(n) \
+	(REG_SEC_TOP_DTB_OFFSET + 0x0000 + n * 32)
 
 /* CFG_QUEUE_DTB_ADDR_L_0_127 虚机队列入队的低地址寄存器 n=0~127*/
-#define REG_SEC_CFG_QUEUE_DTB_ADDR_L_0_127(n)     (REG_SEC_TOP_DTB_OFFSET + 0x0004 + n*32)
+#define REG_SEC_CFG_QUEUE_DTB_ADDR_L_0_127(n) \
+	(REG_SEC_TOP_DTB_OFFSET + 0x0004 + n * 32)
 
 /* CFG_QUEUE_DTB_LEN_0_127 虚机队列入队的长度寄存器 n=0~127*/
-#define REG_SEC_CFG_QUEUE_DTB_LEN_0_127(n)        (REG_SEC_TOP_DTB_OFFSET + 0x0008 + n*32)
+#define REG_SEC_CFG_QUEUE_DTB_LEN_0_127(n) \
+	(REG_SEC_TOP_DTB_OFFSET + 0x0008 + n * 32)
 
 /* INFO_QUEUE_BUF_SPACE_LEFT_0_127 靠靠靠靠靠靠?n=0~127*/
-#define REG_SEC_INFO_QUEUE_BUF_SPACE_LEFT_0_127(n) (REG_SEC_TOP_DTB_OFFSET + 0x000C + n*32)
+#define REG_SEC_INFO_QUEUE_BUF_SPACE_LEFT_0_127(n) \
+	(REG_SEC_TOP_DTB_OFFSET + 0x000C + n * 32)
 
 /* CFG_EPID_V_FUNC_NUM_0_127 SOC虚机信息配置寄存器 n=0~127*/
-#define REG_SEC_CFG_EPID_V_FUNC_NUM_0_127(n)       (REG_SEC_TOP_DTB_OFFSET + 0x0010 + n*32)
-
-/* DTB_QUEUE_LOCK_STATE_0_3 队列锁状态寄存器,4个寄存器共128bit，对应队列0~127 n=0~3 */
-#define REG_SEC_DTB_QUEUE_LOCK_STATE_0_3(n)        (REG_SEC_TOP_DTB_OFFSET + 0x4080 + n*4)
-
-typedef enum
-{
-    e_SEC_IPSEC_TRANSPORT_MODE = 0,  /*传输模式*/
-    e_SEC_IPSEC_TUNNEL_MODE,        /*隧道模式*/
-    e_SEC_IPSEC_MODE_LAST,
+#define REG_SEC_CFG_EPID_V_FUNC_NUM_0_127(n) \
+	(REG_SEC_TOP_DTB_OFFSET + 0x0010 + n * 32)
+
+/* DTB_QUEUE_LOCK_STATE_0_3 队列锁状态寄存器,4个寄存器共128bit，对应队列0~127
+ * n=0~3 */
+#define REG_SEC_DTB_QUEUE_LOCK_STATE_0_3(n) \
+	(REG_SEC_TOP_DTB_OFFSET + 0x4080 + n * 4)
+
+typedef enum {
+	e_SEC_IPSEC_TRANSPORT_MODE = 0, /*传输模式*/
+	e_SEC_IPSEC_TUNNEL_MODE, /*隧道模式*/
+	e_SEC_IPSEC_MODE_LAST,
 } E_CMDK_SEC_IPSEC_MODE;
 
-typedef enum
-{
-    e_SEC_SA_DF_BYPASS_MODE = 0,        /*00 bypass DF bit*/
-    e_SEC_SA_DF_CLEAR_MODE,             /*01 clear*/
-    e_SEC_SA_DF_SET_MODE,               /*10 set*/
-    e_SEC_SA_DF_COPY_MODE,              /*11 copy*/
-    e_SEC_SA_DF_MODE_LAST,
+typedef enum {
+	e_SEC_SA_DF_BYPASS_MODE = 0, /*00 bypass DF bit*/
+	e_SEC_SA_DF_CLEAR_MODE, /*01 clear*/
+	e_SEC_SA_DF_SET_MODE, /*10 set*/
+	e_SEC_SA_DF_COPY_MODE, /*11 copy*/
+	e_SEC_SA_DF_MODE_LAST,
 } E_CMDK_SEC_SA_DF_MODE;
 
-typedef enum
-{
-    E_DTB_SA_CMD_FLOW_DOWN = 0,
-    E_DTB_SA_CMD_DUMP,
-    E_DTB_SA_CMD_LAST,
+typedef enum {
+	E_DTB_SA_CMD_FLOW_DOWN = 0,
+	E_DTB_SA_CMD_DUMP,
+	E_DTB_SA_CMD_LAST,
 } E_CMDK_DTB_SA_CMD_TYPE;
 
-typedef enum
-{
-    E_SATYPE_IN  = 1,
-    E_SATYPE_OUT ,
-    E_SATYPE_IN_AND_OUT = 3,
-}E_SA_TYPE;
-
-typedef enum
-{
-    E_INLINE_IN,
-    E_INLINE_OUT,
-    E_INLINE_IN_AND_OUT,
-}E_INLINE_TYPE;
-
-typedef enum
-{
-    e_SEC_ENCRYP_AH_MODE = 0,                       /*000 AH认证*/
-    e_SEC_ENCRYP_ESP_AUTH_MODE,                     /*001 ESP完整性*/
-    e_SEC_ENCRYP_ESP_ENCRYP_MODE,                   /*010 ESP加密*/
-    e_SEC_ENCRYP_ESP_AUTH_AND_ESP_ENCRYP_MODE,      /*011 ESP加密+ESP完整*/
-    e_SEC_ENCRYP_ESP_COMBINED_MODE,                /*100 ESP组合模式*/
-    e_SEC_ENCRYP_MODE_LAST,
+typedef enum {
+	E_SATYPE_IN = 1,
+	E_SATYPE_OUT,
+	E_SATYPE_IN_AND_OUT = 3,
+} E_SA_TYPE;
+
+typedef enum {
+	E_INLINE_IN,
+	E_INLINE_OUT,
+	E_INLINE_IN_AND_OUT,
+} E_INLINE_TYPE;
+
+typedef enum {
+	e_SEC_ENCRYP_AH_MODE = 0, /*000 AH认证*/
+	e_SEC_ENCRYP_ESP_AUTH_MODE, /*001 ESP完整性*/
+	e_SEC_ENCRYP_ESP_ENCRYP_MODE, /*010 ESP加密*/
+	e_SEC_ENCRYP_ESP_AUTH_AND_ESP_ENCRYP_MODE, /*011 ESP加密+ESP完整*/
+	e_SEC_ENCRYP_ESP_COMBINED_MODE, /*100 ESP组合模式*/
+	e_SEC_ENCRYP_MODE_LAST,
 } E_CMDK_SEC_ENCRYP_MODE;
 
-typedef enum
-{
-    e_SEC_SA_LIVETIME_NONE_TYPE = 0,             /*00 none*/
-    e_SEC_SA_LIVETIME_TIME_TYPE,                 /*01 生存时间*/
-    e_SEC_SA_LIVETIME_BYTE_TYPE,                 /*10 byte数*/
-    e_SEC_SA_LIVETIME_PKT_TYPE,                 /*11 pkt数(预留,目前不支持)*/
-    e_SEC_SA_LIVETIME_TYPE_LAST,
+typedef enum {
+	e_SEC_SA_LIVETIME_NONE_TYPE = 0, /*00 none*/
+	e_SEC_SA_LIVETIME_TIME_TYPE, /*01 生存时间*/
+	e_SEC_SA_LIVETIME_BYTE_TYPE, /*10 byte数*/
+	e_SEC_SA_LIVETIME_PKT_TYPE, /*11 pkt数(预留,目前不支持)*/
+	e_SEC_SA_LIVETIME_TYPE_LAST,
 } E_CMDK_LIVETIME_TYPES;
 
 #pragma pack(1)
-typedef struct IPV4_HEAD
-{
-    UINT8 ip_headlen_version;
-    UINT8 ip_tos;
-    UINT16 usTotallen;
-
-    UINT16 usIdentify;
-    UINT16 ip_fragoff;
-
-    UINT8 uclive_time;
-    UINT8 ucProtocal;
-    UINT16 usHeadChecksum;
-
-    UINT32  udSrcIpAddr;
-    UINT32  udDstIpAddr;
-}T_IPV4_HEAD;
-#pragma pack()
+typedef struct IPV4_HEAD {
+	UINT8 ip_headlen_version;
+	UINT8 ip_tos;
+	UINT16 usTotallen;
 
-typedef struct
-{
-   UINT32  DtbAddrH;  /*地址的高32位*/
-   UINT32  DtbAddrL;  /*地址的低32位,两个地址组成64位然后左移4位得到68位的真实地址*/
-   UINT32  DtbCmd;    /*研规上的DTB_LEN字段   */
-}T_QUEUE_DTB_REG;
-
-//SA下表模块使用的结构体
-typedef struct
-{
-  UINT32   udSPI;
-  UINT32   udSaId;
-  UINT16   usSaParam;
-  UINT8    ucCiperID;
-  UINT8    ucAuthID;
-  UINT8    ucCipherkeyLen;
-  UINT8    ucAuthkeyLen;
-  UINT16   usFrag_State;
-
-  UINT32   udESN;
-  UINT32   udSN;
-  UINT64   uddProcessedByteCnt;
-
-  UINT32   udSalt;
-  UINT32   udLifetimeSecMax;
-  UINT64   uddLifetimByteCntMax;
-
-  UINT8    ucProtocol;
-  UINT8    ucTOS;
-  UINT8    ucEsnFlag;
-  UINT8    ucIpType;
-  UINT32   udRSV0;
-  UINT32   udRSV1;
-  UINT32   udRSV2;
-
-  UINT32   udSrcAddress0;
-  UINT32   udSrcAddress1;
-  UINT32   udSrcAddress2;
-  UINT32   udSrcAddress3;
-
-  UINT32   udDstAddress0;
-  UINT32   udDstAddress1;
-  UINT32   udDstAddress2;
-  UINT32   udDstAddress3;
-
-  UINT8   aucSaCipherKey[32];
-  UINT8   aucSaAuthKey[128];
-}__attribute__((packed))T_HAL_SA_DTB_HW_OUT;
-
- typedef struct
-{
-
-  UINT32   udSrcAddress0;
-  UINT32   udSrcAddress1;
-  UINT32   udSrcAddress2;
-  UINT32   udSrcAddress3;
-
-  UINT32   udDstAddress0;
-  UINT32   udDstAddress1;
-  UINT32   udDstAddress2;
-  UINT32   udDstAddress3;
-
-  UINT32   udSPI;
-  UINT32   udSaId;
-  UINT16   usSaParam;
-  UINT8    ucCiperID;
-  UINT8    ucAuthID;
-  UINT8    ucCipherkeyLen;
-  UINT8    ucAuthkeyLen;
-  UINT16   usFrag_State;
-
-  UINT32   udSalt;
-  UINT32   udLifetimeSecMax;
-  UINT64   uddLifetimByteCntMax;
-
-  UINT8    ucProtocol;
-  UINT8    ucTOS;
-  UINT8    ucEsnFlag;
-  UINT8    ucIpType;
-  UINT16   usOutSaOffset;
-  UINT16   udRSV0;
-  UINT32   udOutSaId;
-  UINT32   udRSV1;
-
-  UINT8    aucBitmap[256];
-
-  UINT32   udAntiWindowHigh;
-  UINT32   udAntiWindowLow;
-  UINT64   uddProcessedByteCnt;
-
-  UINT8    aucSaCipherKey[32];
-  UINT8    aucSaAuthKey[128];
-}__attribute__((packed))T_HAL_SA_DTB_HW_IN;
-
-typedef enum
-{
-    e_HAL_IPSEC_CIPHER_NULL     = 0x00,
-    e_HAL_IPSEC_CIPHER_AES_CTR  = 0x11,
-    e_HAL_IPSEC_CIPHER_AES_CBC  = 0x12,
-    e_HAL_IPSEC_CIPHER_AES_ECB  = 0x13,
-    e_HAL_IPSEC_CIPHER_AES_GCM  = 0x14,
-    e_HAL_IPSEC_CIPHER_AES_CCM  = 0x15,
-    e_HAL_IPSEC_CIPHER_AES_GMAC = 0x16,
-    /* 新增SM4算法 */
-    e_HAL_IPSEC_CIPHER_SM4_CTR  = 0x17,
-    e_HAL_IPSEC_CIPHER_SM4_CBC  = 0x18,
-    e_HAL_IPSEC_CIPHER_SM4_ECB  = 0x19,
-    /* 新增XTS算法 */
-    e_HAL_IPSEC_CIPHER_AES_XTS  = 0x1a,
-    e_HAL_IPSEC_CIPHER_SM4_XTS  = 0x1b,
-
-    e_HAL_IPSEC_CIPHER_DES_CBC  = 0x31,
-    e_HAL_IPSEC_CIPHER_3DES_CBC = 0x32,
-    e_HAL_IPSEC_CIPHER_CHACHA   = 0x50,
-}E_HAL_SEC_IPSEC_CIPHER_ALG;
-
-typedef enum
-{
-    e_HAL_IPSEC_AUTH_NULL        = 0x00,
-
-    /* 新增 */
-    e_HAL_IPSEC_AUTH_AES_GMAC    = 0x16,      /* 1 */
-    e_HAL_IPSEC_AUTH_SM4_GMAC    = 0x1e,
-
-    e_HAL_IPSEC_AUTH_AES_CMAC32  = 0x22,      /* 3 */
-    e_HAL_IPSEC_AUTH_AES_CMAC96  = 0x23,
-    e_HAL_IPSEC_AUTH_AES_XCBCMAC = 0x21,
-    e_HAL_IPSEC_AUTH_AES_SHA1    = 0x41,      /* 6 */
-    e_HAL_IPSEC_AUTH_AES_SHA224  = 0x42,
-    e_HAL_IPSEC_AUTH_AES_SHA256  = 0x44,
-    e_HAL_IPSEC_AUTH_AES_SHA384  = 0x45,
-    e_HAL_IPSEC_AUTH_AES_SHA512  = 0x46,
-    e_HAL_IPSEC_AUTH_AES_MD5     = 0x43,
-    e_HAL_IPSEC_AUTH_SM3         = 0x47,
-}E_HAL_SEC_IPSEC_AUTH_ALG;
-
-typedef struct
-{
-    char alg_name[64];
-    char compat_name[64];
-    E_HAL_SEC_IPSEC_CIPHER_ALG e_zxdh_ealgo_id;
-}T_ZXDH_EALGO;
-
-typedef struct
-{
-    char alg_name[64];
-    char compat_name[64];
-    E_HAL_SEC_IPSEC_AUTH_ALG e_zxdh_auth_id;
-}T_ZXDH_ALGO;
+	UINT16 usIdentify;
+	UINT16 ip_fragoff;
 
+	UINT8 uclive_time;
+	UINT8 ucProtocal;
+	UINT16 usHeadChecksum;
+
+	UINT32 udSrcIpAddr;
+	UINT32 udDstIpAddr;
+} T_IPV4_HEAD;
+#pragma pack()
+
+typedef struct {
+	UINT32 DtbAddrH; /*地址的高32位*/
+	UINT32
+	DtbAddrL; /*地址的低32位,两个地址组成64位然后左移4位得到68位的真实地址*/
+	UINT32 DtbCmd; /*研规上的DTB_LEN字段   */
+} T_QUEUE_DTB_REG;
+
+// SA下表模块使用的结构体
+typedef struct {
+	UINT32 udSPI;
+	UINT32 udSaId;
+	UINT16 usSaParam;
+	UINT8 ucCiperID;
+	UINT8 ucAuthID;
+	UINT8 ucCipherkeyLen;
+	UINT8 ucAuthkeyLen;
+	UINT16 usFrag_State;
+
+	UINT32 udESN;
+	UINT32 udSN;
+	UINT64 uddProcessedByteCnt;
+
+	UINT32 udSalt;
+	UINT32 udLifetimeSecMax;
+	UINT64 uddLifetimByteCntMax;
+
+	UINT8 ucProtocol;
+	UINT8 ucTOS;
+	UINT8 ucEsnFlag;
+	UINT8 ucIpType;
+	UINT32 udRSV0;
+	UINT32 udRSV1;
+	UINT32 udRSV2;
+
+	UINT32 udSrcAddress0;
+	UINT32 udSrcAddress1;
+	UINT32 udSrcAddress2;
+	UINT32 udSrcAddress3;
+
+	UINT32 udDstAddress0;
+	UINT32 udDstAddress1;
+	UINT32 udDstAddress2;
+	UINT32 udDstAddress3;
+
+	UINT8 aucSaCipherKey[32];
+	UINT8 aucSaAuthKey[128];
+} __attribute__((packed)) T_HAL_SA_DTB_HW_OUT;
+
+typedef struct {
+	UINT32 udSrcAddress0;
+	UINT32 udSrcAddress1;
+	UINT32 udSrcAddress2;
+	UINT32 udSrcAddress3;
+
+	UINT32 udDstAddress0;
+	UINT32 udDstAddress1;
+	UINT32 udDstAddress2;
+	UINT32 udDstAddress3;
+
+	UINT32 udSPI;
+	UINT32 udSaId;
+	UINT16 usSaParam;
+	UINT8 ucCiperID;
+	UINT8 ucAuthID;
+	UINT8 ucCipherkeyLen;
+	UINT8 ucAuthkeyLen;
+	UINT16 usFrag_State;
+
+	UINT32 udSalt;
+	UINT32 udLifetimeSecMax;
+	UINT64 uddLifetimByteCntMax;
+
+	UINT8 ucProtocol;
+	UINT8 ucTOS;
+	UINT8 ucEsnFlag;
+	UINT8 ucIpType;
+	UINT16 usOutSaOffset;
+	UINT16 udRSV0;
+	UINT32 udOutSaId;
+	UINT32 udRSV1;
+
+	UINT8 aucBitmap[256];
+
+	UINT32 udAntiWindowHigh;
+	UINT32 udAntiWindowLow;
+	UINT64 uddProcessedByteCnt;
+
+	UINT8 aucSaCipherKey[32];
+	UINT8 aucSaAuthKey[128];
+} __attribute__((packed)) T_HAL_SA_DTB_HW_IN;
+
+typedef enum {
+	e_HAL_IPSEC_CIPHER_NULL = 0x00,
+	e_HAL_IPSEC_CIPHER_AES_CTR = 0x11,
+	e_HAL_IPSEC_CIPHER_AES_CBC = 0x12,
+	e_HAL_IPSEC_CIPHER_AES_ECB = 0x13,
+	e_HAL_IPSEC_CIPHER_AES_GCM = 0x14,
+	e_HAL_IPSEC_CIPHER_AES_CCM = 0x15,
+	e_HAL_IPSEC_CIPHER_AES_GMAC = 0x16,
+	/* 新增SM4算法 */
+	e_HAL_IPSEC_CIPHER_SM4_CTR = 0x17,
+	e_HAL_IPSEC_CIPHER_SM4_CBC = 0x18,
+	e_HAL_IPSEC_CIPHER_SM4_ECB = 0x19,
+	/* 新增XTS算法 */
+	e_HAL_IPSEC_CIPHER_AES_XTS = 0x1a,
+	e_HAL_IPSEC_CIPHER_SM4_XTS = 0x1b,
+
+	e_HAL_IPSEC_CIPHER_DES_CBC = 0x31,
+	e_HAL_IPSEC_CIPHER_3DES_CBC = 0x32,
+	e_HAL_IPSEC_CIPHER_CHACHA = 0x50,
+} E_HAL_SEC_IPSEC_CIPHER_ALG;
+
+typedef enum {
+	e_HAL_IPSEC_AUTH_NULL = 0x00,
+
+	/* 新增 */
+	e_HAL_IPSEC_AUTH_AES_GMAC = 0x16, /* 1 */
+	e_HAL_IPSEC_AUTH_SM4_GMAC = 0x1e,
+
+	e_HAL_IPSEC_AUTH_AES_CMAC32 = 0x22, /* 3 */
+	e_HAL_IPSEC_AUTH_AES_CMAC96 = 0x23,
+	e_HAL_IPSEC_AUTH_AES_XCBCMAC = 0x21,
+	e_HAL_IPSEC_AUTH_AES_SHA1 = 0x41, /* 6 */
+	e_HAL_IPSEC_AUTH_AES_SHA224 = 0x42,
+	e_HAL_IPSEC_AUTH_AES_SHA256 = 0x44,
+	e_HAL_IPSEC_AUTH_AES_SHA384 = 0x45,
+	e_HAL_IPSEC_AUTH_AES_SHA512 = 0x46,
+	e_HAL_IPSEC_AUTH_AES_MD5 = 0x43,
+	e_HAL_IPSEC_AUTH_SM3 = 0x47,
+} E_HAL_SEC_IPSEC_AUTH_ALG;
+
+typedef struct {
+	char alg_name[64];
+	char compat_name[64];
+	E_HAL_SEC_IPSEC_CIPHER_ALG e_zxdh_ealgo_id;
+} T_ZXDH_EALGO;
+
+typedef struct {
+	char alg_name[64];
+	char compat_name[64];
+	E_HAL_SEC_IPSEC_AUTH_ALG e_zxdh_auth_id;
+} T_ZXDH_ALGO;
 
 void BttlPubDump(unsigned char *ucBuf, UINT32 udLen);
-UINT32 CmdkBttlTestSecDtbSaAdd(struct zxdh_en_device *en_dev,E_CMDK_DTB_SA_CMD_TYPE eDtbSaCmdType,E_SA_TYPE eSaType,UINT64 uddSaVirAddr,UINT32 udDtbSaIsIntEn,UINT32 udDtbLen,UINT32 udQueIndex);
+UINT32 CmdkBttlTestSecDtbSaAdd(struct zxdh_en_device *en_dev,
+							   E_CMDK_DTB_SA_CMD_TYPE eDtbSaCmdType,
+							   E_SA_TYPE eSaType, UINT64 uddSaVirAddr,
+							   UINT32 udDtbSaIsIntEn, UINT32 udDtbLen,
+							   UINT32 udQueIndex);
 void zxdh_ipsec_del_sa(struct xfrm_state *xs);
 bool zxdh_ipsec_offload_ok(struct sk_buff *skb, struct xfrm_state *xs);
-void zxdh_ipsec_state_advance_esn (struct xfrm_state *x);
-void zxdh_ipsec_state_update_curlft (struct xfrm_state *x);
-int  zxdh_ipsec_policy_add (struct xfrm_policy *x);
-void zxdh_ipsec_policy_delete (struct xfrm_policy *x);
-void zxdh_ipsec_policy_free (struct xfrm_policy *x);
+void zxdh_ipsec_state_advance_esn(struct xfrm_state *x);
+void zxdh_ipsec_state_update_curlft(struct xfrm_state *x);
+int zxdh_ipsec_policy_add(struct xfrm_policy *x);
+void zxdh_ipsec_policy_delete(struct xfrm_policy *x);
+void zxdh_ipsec_policy_free(struct xfrm_policy *x);
 
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc.c b/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc.c
index 79f1a12ec783f00f0c2ecd130b59bbeb38ad5ff9..d438de57e91ad8c9d7202be1569598cbfc5ce0dc 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc.c
@@ -1,489 +1,476 @@
-/*****************************************************************************
-(C) 2023 ZTE Corporation. 版权所有.
-
-文件名      : en_1588_pkt_proc.c
-内容摘要    : 提供PTP数据包处理相关接口
-作者/日期   : Limin / 2023.10.12
-版本        : 1.0
-*****************************************************************************/
-
-#include "en_1588_pkt_proc.h"
-#include "en_ioctl.h"
-#include "queue.h"
-
-#define PTP_MESSAGE_HRD_LEN         34
-#define IPV6_HDR_LEN                40
-#define IPV6_PROT_OFFSET            6
-#define UDP_DEST_PORT_OFFSET        2
-#define VLAN_TPID                   0x8100
-
-/* pi头中pkt_type字段值 */
-#define PTP_EVENT_TYPE_NOSECURITY   2
-#define PTP_EVENT_TYPE_SECURITY     3
-#define PTP_GENERAL_TYPE            0
-#define PTP_TYPE_OFFSET             4
-/* 下行层四1588微码是否需要查询ipsec表 */
-#define PTP_L4_NEED_QUERY_IPSEC_TABLE   1
-#define PTP_TYPE_L4_SECURITY_OFFSET     3
-
-/* L3报文类型 */
-#define ETH_TYPE_PTP        0x88f7
-#define ETH_TYPE_IPV4       0x0800
-#define ETH_TYPE_IPV6       0x86dd
-
-/* L4报文类型 */
-#define ETH_TYPE_UDP        0x11
-#define ETH_TYPE_TCP        0x06
-
-#define UDP_HDR_LEN         0x08
-#define TCP_HDR_LEN         0x14
-
-/* 报文中关键字段的长度 */
-#define ETHER_TYPE_LEN      2
-#define ETHER_MAC_LEN       6
-#define L2_PKT_HDR_LEN      ((2 * ETHER_MAC_LEN) + ETHER_TYPE_LEN)
-
-#define IP_PROT_OFFSET      9 /* IP头中protocol字段的偏移 */
-
-#define PTP_MSG_ERROR_TYPE  0xff
-#define PTPHDR_CF_OFFSET    8
-
-#define VLAN_LEN            4
-
-extern int get_hw_timestamp(struct zxdh_en_device *en_dev, u32 *hwts);
-/* PTP报文类型和处理函数对应关系结构体 */
-typedef struct
-{
-    uint8_t type;
-    int32_t (*proc_func)(struct sk_buff *skb,               \
-                         struct zxdh_net_hdr *hdr,          \
-                         uint8_t *ptpHdr,                   \
-                         struct time_stamps *t5g,           \
-                         struct time_stamps *tsn,           \
-                         uint32_t *thw,                     \
-                         struct zxdh_en_device *en_dev);
-} MsgProc_t;
-
-typedef struct
-{
-    uint8_t type;
-    int32_t (*proc_func)(struct zxdh_net_hdr_rcv *hdr, \
-                         uint8_t *ptpHdr,                   \
-                         struct time_stamps *t5g,           \
-                         struct time_stamps *tsn,           \
-                         uint32_t *thw,                     \
-                         struct skb_shared_info *ptSkbSharedInfo,
-                         struct zxdh_en_device *en_dev);
-} MsgRcv_t;
-
-/* PTP报文类型和处理函数对应关系表 */
-MsgProc_t g_MsgProcTable[] =
-{
-    {PTP_MSG_TYPE_SYNC,                  pkt_proc_type_sync                 },
-    {PTP_MSG_TYPE_DELAY_REQ,             pkt_proc_type_delay_req            },
-    {PTP_MSG_TYPE_PDELAY_REQ,            pkt_proc_type_pdelay_req           },
-    {PTP_MSG_TYPE_PDELAY_RESP,           pkt_proc_type_pdelay_resp          },
-
-    {PTP_MSG_TYPE_FOLLOW_UP,             pkt_proc_type_follow_up            },
-    {PTP_MSG_TYPE_DELAY_RESP,            pkt_proc_type_delay_resp           },
-    {PTP_MSG_TYPE_PDELAY_RESP_FOLLOW_UP, pkt_proc_type_pdelay_resp_follow_up},
-    {PTP_MSG_TYPE_ANNOUNCE,              pkt_proc_type_announce             },
-    {PTP_MSG_TYPE_SIGNALING,             pkt_proc_type_signaling            },
-    {PTP_MSG_TYPE_MANAGEMENT,            pkt_proc_type_management           },
-
-    {PTP_MSG_ERROR_TYPE,                 NULL                               }
-};
-
-MsgRcv_t g_MsgRcvTable[] =
-{
-    {PTP_MSG_TYPE_SYNC,                  pkt_rcv_type_event                 },
-    {PTP_MSG_TYPE_DELAY_REQ,             pkt_rcv_type_event                 },
-    {PTP_MSG_TYPE_PDELAY_REQ,            pkt_rcv_type_event                 },
-    {PTP_MSG_TYPE_PDELAY_RESP,           pkt_rcv_type_event                 },
-
-    {PTP_MSG_TYPE_DELAY_RESP,            pkt_rcv_type_delay_resp            },
-
-    {PTP_MSG_ERROR_TYPE,                 NULL                               }
-};
-
-/* 判断是否为事件报文 */
-bool is_event_message(const uint8_t msg_type)
-{
-    if (msg_type <= PTP_MSG_TYPE_PDELAY_RESP)
-    {
-        return true;
-    }
-    return false;
-}
-
-/* 判断是否为普通报文 */
-bool is_general_message(const uint8_t msg_type)
-{
-    if ((PTP_MSG_TYPE_FOLLOW_UP <= msg_type) && (msg_type <= PTP_MSG_TYPE_MANAGEMENT))
-    {
-        return true;
-    }
-    return false;
-}
-
-/* p得到PTP报文头位置 */
-int32_t get_hdr_point(uint8_t *pData, uint8_t *piTs0ffset, uint8_t **ptpHdr)
-{
-    uint16_t    udp_dest_port_ptp   = 0;
-    uint16_t    offset              = 0;
-    uint16_t    temp_len            = 0;
-    uint16_t    eth_type_lay3       = ntohs(*((uint16_t*)(pData + (2 * ETHER_MAC_LEN))));   /* get Eth Type */
-    uint8_t     eth_type_lay4       = 0;
-    uint8_t     eth_type_lay4_ipv6  = 0;
-    uint16_t    eth_type_vlan_lay3  = ntohs(*((uint16_t*)(pData + (2 * ETHER_MAC_LEN) + VLAN_LEN)));
-
-    /* 计算PTP头的偏移 */
-    offset = L2_PKT_HDR_LEN;
-
-    if ((VLAN_TPID == eth_type_lay3) && (VLAN_TPID != eth_type_vlan_lay3)) /* 单vlan偏移 */
-    {
-        offset += VLAN_LEN;
-    }
-    else if ((VLAN_TPID == eth_type_lay3) && (VLAN_TPID == eth_type_vlan_lay3)) /* 双vlan偏移 */
-    {
-        offset += (VLAN_LEN * 2);
-    }
-
-    eth_type_lay3 = ntohs(*((uint16_t*)(pData + offset - ETHER_TYPE_LEN)));
-    eth_type_lay4 = *(pData + offset + IP_PROT_OFFSET);
-
-    eth_type_lay4_ipv6  = *(pData + offset + IPV6_PROT_OFFSET);
-
-    if ((ETH_TYPE_PTP != eth_type_lay3) && (ETH_TYPE_IPV4 != eth_type_lay3) && (ETH_TYPE_IPV6 != eth_type_lay3))
-    {
-        LOG_ERR("unknown L3 eth type: %d\n", eth_type_lay3);
-        return IS_NOT_PTP_MSG;
-    }
-
-    if (ETH_TYPE_IPV4 == eth_type_lay3)
-    {
-        /* IP首部第一字节: 版本(4b)+首部长度（4b），这里取低4位，长度是以4字节为单位 */
-        temp_len = *(pData + offset);
-        temp_len = (temp_len & 0x0f) * 4;
-        offset += temp_len;
-
-        /* L4类型PTP只有UDP */
-        if (ETH_TYPE_UDP == eth_type_lay4)
-        {
-            udp_dest_port_ptp = ntohs(*(uint16_t *)(pData + offset + UDP_DEST_PORT_OFFSET));
-            if ((udp_dest_port_ptp != 319) && (udp_dest_port_ptp != 320))
-            {
-                LOG_ERR("UDP destination port(%hd) is not 319 or 320!!\n", udp_dest_port_ptp);
-                return IS_NOT_PTP_MSG;
-            }
-            temp_len = UDP_HDR_LEN;
-            offset += temp_len;
-        }
-        else
-        {
-            LOG_ERR("eth_type_lay4 = %c, is not UDP!!!!!\n", eth_type_lay4);
-            return IS_NOT_PTP_MSG;
-        }
-    }
-    else if(ETH_TYPE_IPV6 == eth_type_lay3)
-    {
-        temp_len = IPV6_HDR_LEN;
-        offset += temp_len;
-
-        /* L4类型PTP只有UDP */
-        if (ETH_TYPE_UDP == eth_type_lay4_ipv6)
-        {
-            udp_dest_port_ptp = ntohs(*(uint16_t *)(pData + offset + UDP_DEST_PORT_OFFSET));
-            if ((udp_dest_port_ptp != 319) && (udp_dest_port_ptp != 320))
-            {
-                LOG_ERR("UDP destination port(%hd) is not 319 or 320!!\n", udp_dest_port_ptp);
-                return IS_NOT_PTP_MSG;
-            }
-            temp_len = UDP_HDR_LEN;
-            offset += temp_len;
-        }
-        else
-        {   LOG_ERR("eth_type_lay4_ipv6 = %c, is not UDP!!!!!!\n",eth_type_lay4_ipv6);
-            return IS_NOT_PTP_MSG;
-        }
-    }
-
-    *ptpHdr = pData + offset;
-
-    /* 赋值pd头的ts_offset字段 */
-    *piTs0ffset = offset;
-
-    return PTP_SUCCESS;
-}
-
-/* 从PTP报文头中解析出报文类型 */
-uint8_t get_msgtype_from_hrd(uint8_t *hrd, const uint8_t len)
-{
-    uint8_t msg_type = PTP_MSG_ERROR_TYPE;
-
-    CHECK_UNEQUAL_ERR(len, PTP_MESSAGE_HRD_LEN, -EFAULT, "error len %d!", len);
-
-    msg_type = hrd[0] & 0x0f;
-    if (is_event_message(msg_type) || is_general_message(msg_type))
-    {
-        return msg_type;
-    }
-
-    LOG_ERR("error message type %d", msg_type);
-    return PTP_MSG_ERROR_TYPE;
-}
-
-/* 调用PTP模块驱动接口，读取3个时间戳：两个80bit（T1，T2），一个32bit（T3） */
-#ifdef    PTP_DRIVER_INTERFACE_EN
-extern int get_pkt_timestamp(int32_t clock_no, struct zxdh_en_device *en_dev, struct time_stamps *ts, u32 *hwts);
-#endif /* PTP_DRIVER_INTERFACE_EN */
-
-int32_t get_tstamps_from_ptp(int32_t clock_no, struct time_stamps *t5g, struct time_stamps *tsn, uint32_t *thw, struct zxdh_en_device *en_dev)
-{  
-    uint32_t hwts                       = 0;
-    struct time_stamps ts[2]            = {};
-
-#ifdef  PTP_DRIVER_INTERFACE_EN
-    int32_t ret                         = 0;
-    ret = get_pkt_timestamp(clock_no, en_dev, ts, &hwts);//todo
-    if (unlikely(ret != 0))
-    {
-        LOG_ERR("netdev %s get tsn clock %d failed!, ret = %d", en_dev->netdev->name,clock_no,ret);
-        return -1;
-    }
-#endif /* PTP_DRIVER_INTERFACE_EN */
-
-    LOG_DEBUG("===GET-PTP===: hwts=%u", hwts);
-    LOG_DEBUG("===GET-PTP===: ts[0].s=%llu, ts[0].ns=%u", ts[0].s, ts[0].ns);
-    LOG_DEBUG("===GET-PTP===: ts[1].s=%llu, ts[1].ns=%u", ts[1].s, ts[1].ns);
-
-    *t5g = ts[1];
-    *tsn = ts[1];
-    *thw = hwts;
-
-    return 0;
-}
-#ifdef TIME_STAMP_1588
-/* 发送流程中的报文时间戳处理 */
-int32_t pkt_1588_proc_xmit(struct sk_buff *skb, struct zxdh_net_hdr *hdr, int32_t clock_no, struct zxdh_en_device *en_dev)
-{
-    struct time_stamps  ts_5g;              /* 5G时间戳，有效值80bit */
-    struct time_stamps  ts_tsn;             /* TSN时间戳，有效值80bit */
-    uint32_t            ts_thw      = 0;    /* 硬件当前时间戳，有效值32bit */
-    uint8_t             *pData      = NULL;
-    uint8_t             *ptpHdr     = NULL;
-    uint8_t             ret         = 0;
-    uint8_t             i           = 0;
-    uint8_t             cnt         = 0;
-    uint8_t             msg_type    = 0xff;
-    struct ptpHdr_t     *ptPtpHdr   = NULL;
-
-    memset(&ts_5g, 0, sizeof(struct time_stamps));
-    memset(&ts_tsn, 0, sizeof(struct time_stamps));
-
-    CHECK_EQUAL_ERR(skb, NULL, -EADDRNOTAVAIL, "skb is NULL!\n");
-    CHECK_EQUAL_ERR(hdr, NULL, -EADDRNOTAVAIL, "hdr is NULL!\n");
-
-    pData = skb->data;
-
-    /* 获得ptp报文头指针&赋值pd头ts_offset字段 */
-    ret = get_hdr_point(pData, &(hdr->ts_offset), &ptpHdr);
-    CHECK_EQUAL_ERR(ptpHdr, NULL, -EADDRNOTAVAIL, "get ptp hdr failed!\n");
-    CHECK_UNEQUAL_ERR(ret, 0, ret, "is not ptp msg or get hdr err!!\n");
-
-    ptPtpHdr = (struct ptpHdr_t *)ptpHdr;
-    char * phdr = (char *)ptPtpHdr;
-
-    /* 解析PTP报文类型 */
-    msg_type = get_msgtype_from_hrd(ptpHdr, PTP_MESSAGE_HRD_LEN);
-    CHECK_EQUAL_ERR(msg_type, PTP_MSG_ERROR_TYPE, -EFAULT, "unknow PTP msg type!\n");
-
-    /* 如果是事件报文，提取时间戳 */
-    if (is_event_message(msg_type))
-    {
-        ret = get_tstamps_from_ptp(clock_no, &ts_5g, &ts_tsn, &ts_thw, en_dev);
-        CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "get tstamps from ptp failed!\n");
-
-        /* ptp_type[2]的低bit2-4表示pkt_type,加密事件报文类型为2，非加密事件报文为3,   */
-        hdr->ptp_type[2] = (hdr->ptp_type[2] & 0x8F) + (PTP_EVENT_TYPE_NOSECURITY << PTP_TYPE_OFFSET);
-        if (0 != ((ptPtpHdr->flagField) & 0x0080))
-        {
-            hdr->ptp_type[2] = (hdr->ptp_type[2] & 0x8F) + (PTP_EVENT_TYPE_SECURITY << PTP_TYPE_OFFSET);
-        }
-    }
-    else
-    {
-        /* 普通报文类型为0 */
-        hdr->ptp_type[2] = (hdr->ptp_type[2] & 0x8F) + (PTP_GENERAL_TYPE << PTP_TYPE_OFFSET);
-    }
-    /* 层四1588报文,下行微码处理时，是否需要查ipsec表, 加密报文需要 */
-    LOG_INFO("ptPtpHdr->flagField: 0x%x\n", ptPtpHdr->flagField);
-    if (0 != ((ptPtpHdr->flagField) & 0x0080))
-    {
-        hdr->ptp_type[2] = (hdr->ptp_type[2] & 0xF7) + (PTP_L4_NEED_QUERY_IPSEC_TABLE << PTP_TYPE_L4_SECURITY_OFFSET);
-        LOG_INFO("hdr->ptp_type[2]: 0x%x\n", hdr->ptp_type[2]);
-    }
-    /* 层二发送方向的出端口需要这里指示 */
-    hdr->port = en_dev->phy_port;
-
-    /* 根据不同报文类型做不同处理 */
-    cnt = sizeof(g_MsgProcTable) / sizeof(MsgProc_t);
-    for (i = 0; i < cnt; i++)
-    {
-        if (g_MsgProcTable[i].type == msg_type)
-        {
-            if (likely(g_MsgProcTable[i].proc_func != NULL))
-            {
-                ret = g_MsgProcTable[i].proc_func(skb, hdr, ptpHdr, &ts_5g, &ts_tsn, &ts_thw, en_dev);
-            }
-        }
-    }
-
-    return ret;
-}
-#endif
-/* 接收流程中的报文时间戳处理 */
-int32_t pkt_1588_proc_rcv(struct sk_buff *skb, struct zxdh_net_hdr_rcv *hdr, int32_t clock_no, struct zxdh_en_device *en_dev)
-{
-    struct time_stamps      ts_5g;  /* 5G时间戳，有效值80bit */
-    struct time_stamps      ts_tsn; /* TSN时间戳，有效值80bit */
-    uint32_t    ts_thw      = 0;    /* 硬件当前时间戳，有效值32bit */
-    uint8_t     *pData      = NULL;
-    uint8_t     *ptpHdr     = NULL;
-    int32_t     ret         = 0;
-    uint8_t     i           = 0;
-    uint8_t     cnt         = 0;
-    uint8_t     msg_type    = 0xff;
-    uint8_t     piTsOffset  = 0;
-
-    memset(&ts_5g, 0, sizeof(struct time_stamps));
-    memset(&ts_tsn, 0, sizeof(struct time_stamps));
-
-    CHECK_EQUAL_ERR(skb, NULL, -EADDRNOTAVAIL, "skb is NULL!\n");
-    CHECK_EQUAL_ERR(hdr, NULL, -EADDRNOTAVAIL, "hdr is NULL!\n");
-
-    pData = skb->data;//TODO,大包data可能会填到非线性区，此处需要修改。
-
-    print_data((uint8_t *)hdr, sizeof(struct zxdh_net_hdr)+16); //todo
-    print_data(skb->data, skb->len);
-
-    /* 获得ptp报文头指针&赋值pi头ts_offset字段 */
-    ret = get_hdr_point(pData, &piTsOffset, &ptpHdr);
-    CHECK_EQUAL_ERR(ptpHdr, NULL, -EADDRNOTAVAIL, "get ptp hdr failed!\n");
-    CHECK_UNEQUAL_ERR(ret, 0, ret, "is not ptp msg or get hdr err!!\n");
-
-    /* 解析PTP报文类型 */
-    msg_type = get_msgtype_from_hrd(ptpHdr, PTP_MESSAGE_HRD_LEN);
-    CHECK_EQUAL_ERR(msg_type, PTP_MSG_ERROR_TYPE, -EFAULT, "unknow PTP msg type!\n");
-
-    /* 如果是事件报文，提取时间戳 */
-    if (is_event_message(msg_type))
-    {
-        ret = get_tstamps_from_ptp(clock_no, &ts_5g, &ts_tsn, &ts_thw, en_dev);
-        CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "get tstamps from ptp failed!\n");
-    }
-
-    /* 根据不同报文类型做不同处理 */
-    cnt = sizeof(g_MsgRcvTable) / sizeof(MsgRcv_t);
-    for (i = 0; i < cnt; i++)
-    {
-        if (g_MsgRcvTable[i].type == msg_type)
-        {
-            if (likely(g_MsgRcvTable[i].proc_func != NULL))
-            {
-                ret = g_MsgRcvTable[i].proc_func(hdr, ptpHdr, &ts_5g, &ts_tsn, &ts_thw, skb_shinfo(skb), en_dev);
-            }
-        }
-    }
-
-    return ret;
-}
-
-int32_t is_delay_statistics_pkt(uint8_t *pData)
-{
-    uint16_t    udp_dest_port   = 0;
-    uint16_t    offset              = 0;
-    uint16_t    temp_len            = 0;
-    uint16_t    eth_type_lay3       = ntohs(*((uint16_t*)(pData + (2 * ETHER_MAC_LEN))));   /* get Eth Type */
-    uint8_t     eth_type_lay4       = 0;
-    uint8_t     eth_type_lay4_ipv6  = 0;
-    uint16_t    eth_type_vlan_lay3  = ntohs(*((uint16_t*)(pData + (2 * ETHER_MAC_LEN) + VLAN_LEN)));
-
-    /* 计算PTP头的偏移 */
-    offset = L2_PKT_HDR_LEN;
-
-    if ((VLAN_TPID == eth_type_lay3) && (VLAN_TPID != eth_type_vlan_lay3)) /* 单vlan偏移 */
-    {
-        offset += VLAN_LEN;
-    }
-    else if ((VLAN_TPID == eth_type_lay3) && (VLAN_TPID == eth_type_vlan_lay3)) /* 双vlan偏移 */
-    {
-        offset += (VLAN_LEN * 2);
-    }
-
-    eth_type_lay3 = ntohs(*((uint16_t*)(pData + offset - ETHER_TYPE_LEN)));
-    eth_type_lay4 = *(pData + offset + IP_PROT_OFFSET);
-
-    eth_type_lay4_ipv6  = *(pData + offset + IPV6_PROT_OFFSET);
-
-    if (ETH_TYPE_IPV4 != eth_type_lay3)
-    {
-        // LOG_ERR("unknown L4 eth type: %d\n", eth_type_lay3);
-        return IS_NOT_STATISTICS_PKT;
-    }
-
-    if (ETH_TYPE_IPV4 == eth_type_lay3)
-    {
-        /* IP首部第一字节: 版本(4b)+首部长度（4b），这里取低4位，长度是以4字节为单位 */
-        temp_len = *(pData + offset);
-        temp_len = (temp_len & 0x0f) * 4;
-        offset += temp_len;
-
-        /* L4类型PTP只有UDP */
-        if (ETH_TYPE_UDP == eth_type_lay4)
-        {
-            udp_dest_port = ntohs(*(uint16_t *)(pData + offset + UDP_DEST_PORT_OFFSET));
-            if (udp_dest_port != 49184)
-            {
-                // LOG_ERR("UDP destination port(%hd) is not 49184!!\n", udp_dest_port);
-                return IS_NOT_STATISTICS_PKT;
-            }
-        }
-        else
-        {
-            // LOG_ERR("eth_type_lay4 = %c, is not UDP!!!!!\n", eth_type_lay4);
-            return IS_NOT_STATISTICS_PKT;
-        }
-    }
-
-    return PTP_SUCCESS;
-}
-
-/* delay统计报文发送流程中的时间戳处理 */
-int32_t pkt_delay_statistics_proc(struct sk_buff *skb, struct zxdh_net_hdr *hdr, struct zxdh_en_device *en_dev)
-{
-    uint8_t             *pData      = NULL;
-    uint8_t             ret         = 0;
-    uint32_t            ts_thw      = 0;
-
-    CHECK_EQUAL_ERR(skb, NULL, -EADDRNOTAVAIL, "skb is NULL!\n");
-    CHECK_EQUAL_ERR(hdr, NULL, -EADDRNOTAVAIL, "hdr is NULL!\n");
-
-    pData = skb->data;
-
-    /* 检查是否是delay统计报文: udp端口号：49184 */
-    if(IS_NOT_STATISTICS_PKT == is_delay_statistics_pkt(pData))
-    {
-        return DELAY_STATISTICS_FAILED;
-    }
-    /* 时延统计使能 */
-    hdr->pd_hdr.ol_flag |= htons(DELAY_STATISTICS_INSERT_EN_BIT);
-
-    ret = get_hw_timestamp(en_dev, &ts_thw);
-    CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "get_hw_timestamp failed!\n");
-
-    /*hw的时间戳，写到 PD头的5~8字节:高29位为ns位，低3bits位为小数ns位 */
-    *(uint32_t*)(&(hdr->pd_hdr.tag_idx)) = htonl(ts_thw << CPU_TX_DECIMAL_NS); /* 大端对齐 */
-
-    return ret;
-}
+/*****************************************************************************
+(C) 2023 ZTE Corporation. 版权所有.
+
+文件名      : en_1588_pkt_proc.c
+内容摘要    : 提供PTP数据包处理相关接口
+作者/日期   : Limin / 2023.10.12
+版本        : 1.0
+*****************************************************************************/
+
+#include "en_1588_pkt_proc.h"
+#include "en_ioctl.h"
+#include "queue.h"
+
+#define PTP_MESSAGE_HRD_LEN 34
+#define IPV6_HDR_LEN 40
+#define IPV6_PROT_OFFSET 6
+#define UDP_DEST_PORT_OFFSET 2
+#define VLAN_TPID 0x8100
+
+/* pi头中pkt_type字段值 */
+#define PTP_EVENT_TYPE_NOSECURITY 2
+#define PTP_EVENT_TYPE_SECURITY 3
+#define PTP_GENERAL_TYPE 0
+#define PTP_TYPE_OFFSET 4
+/* 下行层四1588微码是否需要查询ipsec表 */
+#define PTP_L4_NEED_QUERY_IPSEC_TABLE 1
+#define PTP_TYPE_L4_SECURITY_OFFSET 3
+
+/* L3报文类型 */
+#define ETH_TYPE_PTP 0x88f7
+#define ETH_TYPE_IPV4 0x0800
+#define ETH_TYPE_IPV6 0x86dd
+
+/* L4报文类型 */
+#define ETH_TYPE_UDP 0x11
+#define ETH_TYPE_TCP 0x06
+
+#define UDP_HDR_LEN 0x08
+#define TCP_HDR_LEN 0x14
+
+/* 报文中关键字段的长度 */
+#define ETHER_TYPE_LEN 2
+#define ETHER_MAC_LEN 6
+#define L2_PKT_HDR_LEN ((2 * ETHER_MAC_LEN) + ETHER_TYPE_LEN)
+
+#define IP_PROT_OFFSET 9 /* IP头中protocol字段的偏移 */
+
+#define PTP_MSG_ERROR_TYPE 0xff
+#define PTPHDR_CF_OFFSET 8
+
+#define VLAN_LEN 4
+
+extern int get_hw_timestamp(struct zxdh_en_device *en_dev, u32 *hwts);
+/* PTP报文类型和处理函数对应关系结构体 */
+typedef struct {
+	uint8_t type;
+	int32_t (*proc_func)(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+						 uint8_t *ptpHdr, struct time_stamps *t5g,
+						 struct time_stamps *tsn, uint32_t *thw,
+						 struct zxdh_en_device *en_dev);
+} MsgProc_t;
+
+typedef struct {
+	uint8_t type;
+	int32_t (*proc_func)(struct zxdh_net_hdr_rcv *hdr, uint8_t *ptpHdr,
+						 struct time_stamps *t5g, struct time_stamps *tsn,
+						 uint32_t *thw, struct skb_shared_info *ptSkbSharedInfo,
+						 struct zxdh_en_device *en_dev);
+} MsgRcv_t;
+
+/* PTP报文类型和处理函数对应关系表 */
+MsgProc_t g_MsgProcTable[] = {
+	{ PTP_MSG_TYPE_SYNC, pkt_proc_type_sync },
+	{ PTP_MSG_TYPE_DELAY_REQ, pkt_proc_type_delay_req },
+	{ PTP_MSG_TYPE_PDELAY_REQ, pkt_proc_type_pdelay_req },
+	{ PTP_MSG_TYPE_PDELAY_RESP, pkt_proc_type_pdelay_resp },
+
+	{ PTP_MSG_TYPE_FOLLOW_UP, pkt_proc_type_follow_up },
+	{ PTP_MSG_TYPE_DELAY_RESP, pkt_proc_type_delay_resp },
+	{ PTP_MSG_TYPE_PDELAY_RESP_FOLLOW_UP, pkt_proc_type_pdelay_resp_follow_up },
+	{ PTP_MSG_TYPE_ANNOUNCE, pkt_proc_type_announce },
+	{ PTP_MSG_TYPE_SIGNALING, pkt_proc_type_signaling },
+	{ PTP_MSG_TYPE_MANAGEMENT, pkt_proc_type_management },
+
+	{ PTP_MSG_ERROR_TYPE, NULL }
+};
+
+MsgRcv_t g_MsgRcvTable[] = { { PTP_MSG_TYPE_SYNC, pkt_rcv_type_event },
+							 { PTP_MSG_TYPE_DELAY_REQ, pkt_rcv_type_event },
+							 { PTP_MSG_TYPE_PDELAY_REQ, pkt_rcv_type_event },
+							 { PTP_MSG_TYPE_PDELAY_RESP, pkt_rcv_type_event },
+
+							 { PTP_MSG_TYPE_DELAY_RESP,
+							   pkt_rcv_type_delay_resp },
+
+							 { PTP_MSG_ERROR_TYPE, NULL } };
+
+/* 判断是否为事件报文 */
+bool is_event_message(const uint8_t msg_type)
+{
+	if (msg_type <= PTP_MSG_TYPE_PDELAY_RESP) {
+		return true;
+	}
+	return false;
+}
+
+/* 判断是否为普通报文 */
+bool is_general_message(const uint8_t msg_type)
+{
+	if ((PTP_MSG_TYPE_FOLLOW_UP <= msg_type) &&
+		(msg_type <= PTP_MSG_TYPE_MANAGEMENT)) {
+		return true;
+	}
+	return false;
+}
+
+/* p得到PTP报文头位置 */
+int32_t get_hdr_point(uint8_t *pData, uint8_t *piTs0ffset, uint8_t **ptpHdr)
+{
+	uint16_t udp_dest_port_ptp = 0;
+	uint16_t offset = 0;
+	uint16_t temp_len = 0;
+	uint16_t eth_type_lay3 = ntohs(
+			*((uint16_t *)(pData + (2 * ETHER_MAC_LEN)))); /* get Eth Type */
+	uint8_t eth_type_lay4 = 0;
+	uint8_t eth_type_lay4_ipv6 = 0;
+	uint16_t eth_type_vlan_lay3 =
+			ntohs(*((uint16_t *)(pData + (2 * ETHER_MAC_LEN) + VLAN_LEN)));
+
+	/* 计算PTP头的偏移 */
+	offset = L2_PKT_HDR_LEN;
+
+	if ((VLAN_TPID == eth_type_lay3) && (VLAN_TPID != eth_type_vlan_lay3)) {
+		/* 单vlan偏移 */
+		offset += VLAN_LEN;
+	} else if ((VLAN_TPID == eth_type_lay3) &&
+			   (VLAN_TPID == eth_type_vlan_lay3)) {
+		/* 双vlan偏移 */
+		offset += (VLAN_LEN * 2);
+	}
+
+	eth_type_lay3 = ntohs(*((uint16_t *)(pData + offset - ETHER_TYPE_LEN)));
+	eth_type_lay4 = *(pData + offset + IP_PROT_OFFSET);
+
+	eth_type_lay4_ipv6 = *(pData + offset + IPV6_PROT_OFFSET);
+
+	if ((ETH_TYPE_PTP != eth_type_lay3) && (ETH_TYPE_IPV4 != eth_type_lay3) &&
+		(ETH_TYPE_IPV6 != eth_type_lay3)) {
+		LOG_ERR("unknown L3 eth type: %d\n", eth_type_lay3);
+		return IS_NOT_PTP_MSG;
+	}
+
+	if (ETH_TYPE_IPV4 == eth_type_lay3) {
+		/* IP首部第一字节: 版本(4b)+首部长度（4b），这里取低4位，长度是以4字节为单位 */
+		temp_len = *(pData + offset);
+		temp_len = (temp_len & 0x0f) * 4;
+		offset += temp_len;
+
+		/* L4类型PTP只有UDP */
+		if (ETH_TYPE_UDP == eth_type_lay4) {
+			udp_dest_port_ptp =
+					ntohs(*(uint16_t *)(pData + offset + UDP_DEST_PORT_OFFSET));
+			if ((udp_dest_port_ptp != 319) && (udp_dest_port_ptp != 320)) {
+				LOG_ERR("UDP destination port(%hd) is not 319 or 320!!\n",
+						udp_dest_port_ptp);
+				return IS_NOT_PTP_MSG;
+			}
+			temp_len = UDP_HDR_LEN;
+			offset += temp_len;
+		} else {
+			LOG_ERR("eth_type_lay4 = %c, is not UDP!!!!!\n", eth_type_lay4);
+			return IS_NOT_PTP_MSG;
+		}
+	} else if (ETH_TYPE_IPV6 == eth_type_lay3) {
+		temp_len = IPV6_HDR_LEN;
+		offset += temp_len;
+
+		/* L4类型PTP只有UDP */
+		if (ETH_TYPE_UDP == eth_type_lay4_ipv6) {
+			udp_dest_port_ptp =
+					ntohs(*(uint16_t *)(pData + offset + UDP_DEST_PORT_OFFSET));
+			if ((udp_dest_port_ptp != 319) && (udp_dest_port_ptp != 320)) {
+				LOG_ERR("UDP destination port(%hd) is not 319 or 320!!\n",
+						udp_dest_port_ptp);
+				return IS_NOT_PTP_MSG;
+			}
+			temp_len = UDP_HDR_LEN;
+			offset += temp_len;
+		} else {
+			LOG_ERR("eth_type_lay4_ipv6 = %c, is not UDP!!!!!!\n",
+					eth_type_lay4_ipv6);
+			return IS_NOT_PTP_MSG;
+		}
+	}
+
+	*ptpHdr = pData + offset;
+
+	/* 赋值pd头的ts_offset字段 */
+	*piTs0ffset = offset;
+
+	return PTP_SUCCESS;
+}
+
+/* 从PTP报文头中解析出报文类型 */
+uint8_t get_msgtype_from_hrd(uint8_t *hrd, const uint8_t len)
+{
+	uint8_t msg_type = PTP_MSG_ERROR_TYPE;
+
+	CHECK_UNEQUAL_ERR(len, PTP_MESSAGE_HRD_LEN, -EFAULT, "error len %d!", len);
+
+	msg_type = hrd[0] & 0x0f;
+	if (is_event_message(msg_type) || is_general_message(msg_type)) {
+		return msg_type;
+	}
+
+	LOG_ERR("error message type %d", msg_type);
+	return PTP_MSG_ERROR_TYPE;
+}
+
+/* 调用PTP模块驱动接口，读取3个时间戳：两个80bit（T1，T2），一个32bit（T3） */
+#ifdef PTP_DRIVER_INTERFACE_EN
+extern int get_pkt_timestamp(int32_t clock_no, struct zxdh_en_device *en_dev,
+							 struct time_stamps *ts, u32 *hwts);
+#endif /* PTP_DRIVER_INTERFACE_EN */
+
+int32_t get_tstamps_from_ptp(int32_t clock_no, struct time_stamps *t5g,
+							 struct time_stamps *tsn, uint32_t *thw,
+							 struct zxdh_en_device *en_dev)
+{
+	uint32_t hwts = 0;
+	struct time_stamps ts[2] = {};
+
+#ifdef PTP_DRIVER_INTERFACE_EN
+	int32_t ret = 0;
+	ret = get_pkt_timestamp(clock_no, en_dev, ts, &hwts); // todo
+	if (unlikely(ret != 0)) {
+		LOG_ERR("netdev %s get tsn clock %d failed!, ret = %d",
+				en_dev->netdev->name, clock_no, ret);
+		return -1;
+	}
+#endif /* PTP_DRIVER_INTERFACE_EN */
+
+	LOG_DEBUG("===GET-PTP===: hwts=%u", hwts);
+	LOG_DEBUG("===GET-PTP===: ts[0].s=%llu, ts[0].ns=%u", ts[0].s, ts[0].ns);
+	LOG_DEBUG("===GET-PTP===: ts[1].s=%llu, ts[1].ns=%u", ts[1].s, ts[1].ns);
+
+	*t5g = ts[1];
+	*tsn = ts[1];
+	*thw = hwts;
+
+	return 0;
+}
+#ifdef TIME_STAMP_1588
+/* 发送流程中的报文时间戳处理 */
+int32_t pkt_1588_proc_xmit(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+						   int32_t clock_no, struct zxdh_en_device *en_dev)
+{
+	struct time_stamps ts_5g; /* 5G时间戳，有效值80bit */
+	struct time_stamps ts_tsn; /* TSN时间戳，有效值80bit */
+	uint32_t ts_thw = 0; /* 硬件当前时间戳，有效值32bit */
+	uint8_t *pData = NULL;
+	uint8_t *ptpHdr = NULL;
+	uint8_t ret = 0;
+	uint8_t i = 0;
+	uint8_t cnt = 0;
+	uint8_t msg_type = 0xff;
+	struct ptpHdr_t *ptPtpHdr = NULL;
+
+	memset(&ts_5g, 0, sizeof(struct time_stamps));
+	memset(&ts_tsn, 0, sizeof(struct time_stamps));
+
+	CHECK_EQUAL_ERR(skb, NULL, -EADDRNOTAVAIL, "skb is NULL!\n");
+	CHECK_EQUAL_ERR(hdr, NULL, -EADDRNOTAVAIL, "hdr is NULL!\n");
+
+	pData = skb->data;
+
+	/* 获得ptp报文头指针&赋值pd头ts_offset字段 */
+	ret = get_hdr_point(pData, &(hdr->ts_offset), &ptpHdr);
+	CHECK_EQUAL_ERR(ptpHdr, NULL, -EADDRNOTAVAIL, "get ptp hdr failed!\n");
+	CHECK_UNEQUAL_ERR(ret, 0, ret, "is not ptp msg or get hdr err!!\n");
+
+	ptPtpHdr = (struct ptpHdr_t *)ptpHdr;
+	char *phdr = (char *)ptPtpHdr;
+
+	/* 解析PTP报文类型 */
+	msg_type = get_msgtype_from_hrd(ptpHdr, PTP_MESSAGE_HRD_LEN);
+	CHECK_EQUAL_ERR(msg_type, PTP_MSG_ERROR_TYPE, -EFAULT,
+					"unknow PTP msg type!\n");
+
+	/* 如果是事件报文，提取时间戳 */
+	if (is_event_message(msg_type)) {
+		ret = get_tstamps_from_ptp(clock_no, &ts_5g, &ts_tsn, &ts_thw, en_dev);
+		CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "get tstamps from ptp failed!\n");
+
+		/* ptp_type[2]的低bit2-4表示pkt_type,加密事件报文类型为2，非加密事件报文为3,
+     */
+		hdr->ptp_type[2] = (hdr->ptp_type[2] & 0x8F) +
+						   (PTP_EVENT_TYPE_NOSECURITY << PTP_TYPE_OFFSET);
+		if (0 != ((ptPtpHdr->flagField) & 0x0080)) {
+			hdr->ptp_type[2] = (hdr->ptp_type[2] & 0x8F) +
+							   (PTP_EVENT_TYPE_SECURITY << PTP_TYPE_OFFSET);
+		}
+	} else {
+		/* 普通报文类型为0 */
+		hdr->ptp_type[2] = (hdr->ptp_type[2] & 0x8F) +
+						   (PTP_GENERAL_TYPE << PTP_TYPE_OFFSET);
+	}
+	/* 层四1588报文,下行微码处理时，是否需要查ipsec表, 加密报文需要 */
+	LOG_INFO("ptPtpHdr->flagField: 0x%x\n", ptPtpHdr->flagField);
+	if (0 != ((ptPtpHdr->flagField) & 0x0080)) {
+		hdr->ptp_type[2] =
+				(hdr->ptp_type[2] & 0xF7) +
+				(PTP_L4_NEED_QUERY_IPSEC_TABLE << PTP_TYPE_L4_SECURITY_OFFSET);
+		LOG_INFO("hdr->ptp_type[2]: 0x%x\n", hdr->ptp_type[2]);
+	}
+	/* 层二发送方向的出端口需要这里指示 */
+	hdr->port = en_dev->phy_port;
+
+	/* 根据不同报文类型做不同处理 */
+	cnt = sizeof(g_MsgProcTable) / sizeof(MsgProc_t);
+	for (i = 0; i < cnt; i++) {
+		if (g_MsgProcTable[i].type == msg_type) {
+			if (likely(g_MsgProcTable[i].proc_func != NULL)) {
+				ret = g_MsgProcTable[i].proc_func(skb, hdr, ptpHdr, &ts_5g,
+												  &ts_tsn, &ts_thw, en_dev);
+			}
+		}
+	}
+
+	return ret;
+}
+#endif
+/* 接收流程中的报文时间戳处理 */
+int32_t pkt_1588_proc_rcv(struct sk_buff *skb, struct zxdh_net_hdr_rcv *hdr,
+						  int32_t clock_no, struct zxdh_en_device *en_dev)
+{
+	struct time_stamps ts_5g; /* 5G时间戳，有效值80bit */
+	struct time_stamps ts_tsn; /* TSN时间戳，有效值80bit */
+	uint32_t ts_thw = 0; /* 硬件当前时间戳，有效值32bit */
+	uint8_t *pData = NULL;
+	uint8_t *ptpHdr = NULL;
+	int32_t ret = 0;
+	uint8_t i = 0;
+	uint8_t cnt = 0;
+	uint8_t msg_type = 0xff;
+	uint8_t piTsOffset = 0;
+
+	memset(&ts_5g, 0, sizeof(struct time_stamps));
+	memset(&ts_tsn, 0, sizeof(struct time_stamps));
+
+	CHECK_EQUAL_ERR(skb, NULL, -EADDRNOTAVAIL, "skb is NULL!\n");
+	CHECK_EQUAL_ERR(hdr, NULL, -EADDRNOTAVAIL, "hdr is NULL!\n");
+
+	pData = skb->data; // TODO,大包data可能会填到非线性区，此处需要修改。
+
+	print_data((uint8_t *)hdr, sizeof(struct zxdh_net_hdr) + 16); // todo
+	print_data(skb->data, skb->len);
+
+	/* 获得ptp报文头指针&赋值pi头ts_offset字段 */
+	ret = get_hdr_point(pData, &piTsOffset, &ptpHdr);
+	CHECK_EQUAL_ERR(ptpHdr, NULL, -EADDRNOTAVAIL, "get ptp hdr failed!\n");
+	CHECK_UNEQUAL_ERR(ret, 0, ret, "is not ptp msg or get hdr err!!\n");
+
+	/* 解析PTP报文类型 */
+	msg_type = get_msgtype_from_hrd(ptpHdr, PTP_MESSAGE_HRD_LEN);
+	CHECK_EQUAL_ERR(msg_type, PTP_MSG_ERROR_TYPE, -EFAULT,
+					"unknow PTP msg type!\n");
+
+	/* 如果是事件报文，提取时间戳 */
+	if (is_event_message(msg_type)) {
+		ret = get_tstamps_from_ptp(clock_no, &ts_5g, &ts_tsn, &ts_thw, en_dev);
+		CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "get tstamps from ptp failed!\n");
+	}
+
+	/* 根据不同报文类型做不同处理 */
+	cnt = sizeof(g_MsgRcvTable) / sizeof(MsgRcv_t);
+	for (i = 0; i < cnt; i++) {
+		if (g_MsgRcvTable[i].type == msg_type) {
+			if (likely(g_MsgRcvTable[i].proc_func != NULL)) {
+				ret = g_MsgRcvTable[i].proc_func(hdr, ptpHdr, &ts_5g, &ts_tsn,
+												 &ts_thw, skb_shinfo(skb),
+												 en_dev);
+			}
+		}
+	}
+
+	return ret;
+}
+
+int32_t is_delay_statistics_pkt(uint8_t *pData)
+{
+	uint16_t udp_dest_port = 0;
+	uint16_t offset = 0;
+	uint16_t temp_len = 0;
+	uint16_t eth_type_lay3 = ntohs(
+			*((uint16_t *)(pData + (2 * ETHER_MAC_LEN)))); /* get Eth Type */
+	uint8_t eth_type_lay4 = 0;
+	uint8_t eth_type_lay4_ipv6 = 0;
+	uint16_t eth_type_vlan_lay3 =
+			ntohs(*((uint16_t *)(pData + (2 * ETHER_MAC_LEN) + VLAN_LEN)));
+
+	/* 计算PTP头的偏移 */
+	offset = L2_PKT_HDR_LEN;
+
+	if ((VLAN_TPID == eth_type_lay3) && (VLAN_TPID != eth_type_vlan_lay3)) {
+		/* 单vlan偏移 */
+		offset += VLAN_LEN;
+	} else if ((VLAN_TPID == eth_type_lay3) &&
+			   (VLAN_TPID == eth_type_vlan_lay3)) {
+		/* 双vlan偏移 */
+		offset += (VLAN_LEN * 2);
+	}
+
+	eth_type_lay3 = ntohs(*((uint16_t *)(pData + offset - ETHER_TYPE_LEN)));
+	eth_type_lay4 = *(pData + offset + IP_PROT_OFFSET);
+
+	eth_type_lay4_ipv6 = *(pData + offset + IPV6_PROT_OFFSET);
+
+	if (ETH_TYPE_IPV4 != eth_type_lay3) {
+		// LOG_ERR("unknown L4 eth type: %d\n", eth_type_lay3);
+		return IS_NOT_STATISTICS_PKT;
+	}
+
+	if (ETH_TYPE_IPV4 == eth_type_lay3) {
+		/* IP首部第一字节: 版本(4b)+首部长度（4b），这里取低4位，长度是以4字节为单位
+     */
+		temp_len = *(pData + offset);
+		temp_len = (temp_len & 0x0f) * 4;
+		offset += temp_len;
+
+		/* L4类型PTP只有UDP */
+		if (ETH_TYPE_UDP == eth_type_lay4) {
+			udp_dest_port =
+					ntohs(*(uint16_t *)(pData + offset + UDP_DEST_PORT_OFFSET));
+			if (udp_dest_port != 49184) {
+				// LOG_ERR("UDP destination port(%hd) is not 49184!!\n", udp_dest_port);
+				return IS_NOT_STATISTICS_PKT;
+			}
+		} else {
+			// LOG_ERR("eth_type_lay4 = %c, is not UDP!!!!!\n", eth_type_lay4);
+			return IS_NOT_STATISTICS_PKT;
+		}
+	}
+
+	return PTP_SUCCESS;
+}
+
+/* delay统计报文发送流程中的时间戳处理 */
+int32_t pkt_delay_statistics_proc(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								  struct zxdh_en_device *en_dev)
+{
+	uint8_t *pData = NULL;
+	uint8_t ret = 0;
+	uint32_t ts_thw = 0;
+
+	CHECK_EQUAL_ERR(skb, NULL, -EADDRNOTAVAIL, "skb is NULL!\n");
+	CHECK_EQUAL_ERR(hdr, NULL, -EADDRNOTAVAIL, "hdr is NULL!\n");
+
+	pData = skb->data;
+
+	/* 检查是否是delay统计报文: udp端口号：49184 */
+	if (IS_NOT_STATISTICS_PKT == is_delay_statistics_pkt(pData)) {
+		return DELAY_STATISTICS_FAILED;
+	}
+	/* 时延统计使能 */
+	hdr->pd_hdr.ol_flag |= htons(DELAY_STATISTICS_INSERT_EN_BIT);
+
+	ret = get_hw_timestamp(en_dev, &ts_thw);
+	CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "get_hw_timestamp failed!\n");
+
+	/*hw的时间戳，写到 PD头的5~8字节:高29位为ns位，低3bits位为小数ns位 */
+	*(uint32_t *)(&(hdr->pd_hdr.tag_idx)) =
+			htonl(ts_thw << CPU_TX_DECIMAL_NS); /* 大端对齐 */
+
+	return ret;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc.h b/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc.h
index 63af6286aa6666417d2c836e5cf38d2b393a47f0..ac59029818c4fd603f0b3fe1771034d90621d548 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc.h
@@ -1,34 +1,38 @@
-/*****************************************************************************
-(C) 2023 ZTE Corporation. 版权所有.
-
-文件名      : en_1588_pkt_proc.h
-内容摘要    : 提供PTP数据包处理相关接口
-作者/日期   : Limin / 2023.10.12
-版本        : 1.0
-*****************************************************************************/
-
-#ifndef _EN_1588_PKT_PROC_H_
-#define _EN_1588_PKT_PROC_H_
-
-#ifdef __cplusplus
-    extern "C" {
-#endif /* __cplusplus */
-
-#include "en_1588_pkt_proc_func.h"
-
-#define PTP_SUCCESS 0
-#define PTP_FAILED (-1)
-#define IS_NOT_PTP_MSG 1
-#define IS_NOT_STATISTICS_PKT   1
-#define DELAY_STATISTICS_FAILED (-1)
-
-int32_t pkt_1588_proc_xmit(struct sk_buff *skb, struct zxdh_net_hdr *hdr, int32_t clock_no, struct zxdh_en_device *en_dev);
-int32_t pkt_1588_proc_rcv(struct sk_buff *skb, struct zxdh_net_hdr_rcv *hdr, int32_t clock_no, struct zxdh_en_device *en_dev);
-int32_t pi_1588_net_hdr_add(struct sk_buff *skb, struct zxdh_net_hdr *hdr, int32_t clock_no, struct zxdh_en_device *en_dev);
-int32_t pkt_delay_statistics_proc(struct sk_buff *skb, struct zxdh_net_hdr *hdr, struct zxdh_en_device *en_dev);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
+/*****************************************************************************
+(C) 2023 ZTE Corporation. 版权所有.
+
+文件名      : en_1588_pkt_proc.h
+内容摘要    : 提供PTP数据包处理相关接口
+作者/日期   : Limin / 2023.10.12
+版本        : 1.0
+*****************************************************************************/
+
+#ifndef _EN_1588_PKT_PROC_H_
+#define _EN_1588_PKT_PROC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "en_1588_pkt_proc_func.h"
+
+#define PTP_SUCCESS 0
+#define PTP_FAILED (-1)
+#define IS_NOT_PTP_MSG 1
+#define IS_NOT_STATISTICS_PKT 1
+#define DELAY_STATISTICS_FAILED (-1)
+
+int32_t pkt_1588_proc_xmit(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+						   int32_t clock_no, struct zxdh_en_device *en_dev);
+int32_t pkt_1588_proc_rcv(struct sk_buff *skb, struct zxdh_net_hdr_rcv *hdr,
+						  int32_t clock_no, struct zxdh_en_device *en_dev);
+int32_t pi_1588_net_hdr_add(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+							int32_t clock_no, struct zxdh_en_device *en_dev);
+int32_t pkt_delay_statistics_proc(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								  struct zxdh_en_device *en_dev);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
 #endif /* _EN_1588_PKT_PROC_H_ */
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc_func.c b/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc_func.c
index 53786dcf4c333d8ca82292d7ef5e69eb1ce6d30b..e698b80a59d23127911b2f0e5fdf6aa53b2ea083 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc_func.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc_func.c
@@ -1,673 +1,631 @@
-/*****************************************************************************
-(C) 2023 ZTE Corporation. 版权所有.
-
-文件名      : en_1588_pkt_proc_func.c
-内容摘要    : 不同数据类型包的处理接口实现
-作者/日期   : Limin / 2023.10.12
-版本        : 1.0
-*****************************************************************************/
-
-#include "en_1588_pkt_proc_func.h"
-#include "en_cmd.h"
-#include "en_ioctl.h"
-
-struct ptp_update_buff tGlobalPtpBuff = {0};
-
-uint64_t htonll(uint64_t u64_host)
-{
-    uint64_t u64_net = 0;
-    uint32_t u32_host_h = 0;
-    uint32_t u32_host_l = 0;
-
-    u32_host_l = u64_host & 0xffffffff;
-    u32_host_h = (u64_host >> 32) & 0xffffffff;
-
-    u64_net = htonl(u32_host_l);
-    u64_net = ( u64_net << 32 ) | htonl(u32_host_h);
-
-    return u64_net;
-}
-
-/**
-* @brief 计算两时间戳subtraction和minuend之差，并将差值赋值给*ptMinusRet
-* @param minuend 高48bit为s位，低32bit为ns位
-*/
-int32_t bits_80_minus(struct time_stamps subtraction, Bits80_t minuend, struct time_stamps *ptMinusRet)
-{
-    uint64_t    minusHigh48_s   = 0;
-    uint32_t    minusLow32_ns   = 0;
-
-    /* 取出80bits被减数的ns位值和s位值 */
-    memcpy((uint8_t *)(&minusHigh48_s), &minuend, S_SIZE);
-    memcpy(&minusLow32_ns, (uint8_t *)(&minuend) + S_SIZE, NS_SIZE);
-
-    /* minuend大端 */
-    minusHigh48_s = htonll(minusHigh48_s) >> 16;
-    minusLow32_ns = htonl(minusLow32_ns);
-
-    /* 如果减数值小于被减数值 */
-    if ((subtraction.s < minusHigh48_s) || ((subtraction.s == minusHigh48_s) && (subtraction.ns < minusLow32_ns)))
-    {
-        LOG_ERR("The difference between the two times is negative！！");
-        return PTP_RET_TIME_ERR;
-    }
-
-    if (subtraction.ns > minusLow32_ns)
-    {
-        ptMinusRet->ns = subtraction.ns - minusLow32_ns;    /* 赋值ns位 */
-        ptMinusRet->s  = subtraction.s - minusHigh48_s;     /* 赋值s位 */
-    }
-    else
-    {
-        ptMinusRet->ns = S_HOLD - (minusLow32_ns - subtraction.ns); /* 赋值ns位 */
-        ptMinusRet->s  = subtraction.s - minusHigh48_s - 1;         /* 赋值s位 */
-    }
-
-    return PTP_RET_SUCCESS;
-}
-
-int32_t pkt_proc_type_sync(struct sk_buff *skb,             \
-                         struct zxdh_net_hdr *hdr,          \
-                         uint8_t *ptpHdr,                   \
-                         struct time_stamps *t5g,           \
-                         struct time_stamps *tsn,           \
-                         uint32_t *thw,                     \
-                         struct zxdh_en_device *en_dev)
-{
-    struct SkbSharedHwtstamps_t         tShhwtstamps;
-    struct time_stamps                  tMinusRet;
-    struct skb_shared_hwtstamps         tHwtstamps5g;
-    struct skb_shared_hwtstamps         tHwtstampsTsn;
-    Bits80_t                            tTsi;
-    struct ptpHdr_t * ptPtpHdr          = NULL;
-    uint8_t         *pOriginTimeStamp   = NULL;
-    uint8_t         majorSdoId          = 0;
-    uint32_t        t5gNsBig            = 0;
-    uint64_t        t5gSBig             = 0;
-    uint32_t        tsnNsBig            = 0;
-    uint64_t        tsnSBig             = 0;
-#ifdef TIME_STAMP_1588
-    uint32_t        frequency           = 0;
-    uint64_t        cfAddedVal          = 0;
-    uint8_t         *tsiTlv             = NULL;
-    uint32_t        cpuTx_ns            = 0;
-    uint32_t        cpuTx_frac_ns       = 0;
-    uint64_t        cfNs                = 0;
-#endif
-
-    ptPtpHdr            = (struct ptpHdr_t *)ptpHdr;
-    majorSdoId          = ((ptPtpHdr->majorType) & 0xf0) >> 4;
-    pOriginTimeStamp    = ptpHdr + sizeof(struct ptpHdr_t);
-    t5gSBig             = (htonll(t5g->s)) >> 16;
-    t5gNsBig            = htonl(t5g->ns);
-    tsnSBig             = (htonll(tsn->s)) >> 16;
-    tsnNsBig            = htonl(tsn->ns);
-
-    memset(&tShhwtstamps, 0, sizeof(struct SkbSharedHwtstamps_t));
-    memset(&tHwtstamps5g, 0, sizeof(struct skb_shared_hwtstamps));
-    memset(&tHwtstampsTsn, 0, sizeof(struct skb_shared_hwtstamps));
-    memset(&tMinusRet, 0, sizeof(struct time_stamps));
-    memset(&tTsi, 0, sizeof(Bits80_t));
-#ifdef TIME_STAMP_1588
-    /* 解析PTP Header的majorSdoId字段，如果是0，表示PTP消息由1588使用 */
-    if (0 == majorSdoId)
-    {
-        /* 解析Flag字段低一字节bit1，如果为0，则是一步法,为1不做处理 */
-        if (0 == ((ptPtpHdr->flagField) & 0x0002))
-        {
-            memcpy(pOriginTimeStamp, &t5gSBig, S_SIZE);
-            memcpy(pOriginTimeStamp + S_SIZE, &t5gNsBig, NS_SIZE);
-        }
-    }
-    else if (1 == majorSdoId) /* 如果是1，表示PTP消息由802.1AS协议使用 */
-    {
-        /* 解析Flag字段低一字节bit1，如果为0，则是一步法 */
-        if (0 == ((ptPtpHdr->flagField) & 0x0002))
-        {
-            /* tsn时间戳放到Sync报文的originTimestamp字段 */
-            memcpy(pOriginTimeStamp, &tsnSBig, S_SIZE);
-            memcpy(pOriginTimeStamp + S_SIZE, &tsnNsBig, NS_SIZE);
-
-            if (0 != ((ptPtpHdr->flagField) & 0x8000)) /* 解析Flag字段高一字节bit7，如果为1，做如下处理，为0不做处理*/
-            {
-                frequency = *(uint32_t *)(ptpHdr + PTPHDR_FREQUENCY_OFFSET);
-                frequency = htonl(frequency);/* 频率比 */
-
-                memcpy(&tTsi, ptpHdr + PTPHDR_TSI_OFFSET, sizeof(Bits80_t));
-
-                bits_80_minus(*t5g, tTsi, &tMinusRet);
-
-                /* （*t5g-*tsi）*频率比 计算结果叠加到CF字段ns位，(不会出现CF字段ns位值溢出情况) */
-                cfAddedVal  = (tMinusRet.s * S_HOLD + tMinusRet.ns) * frequency;
-                memcpy(&cfNs, ptPtpHdr->correctionField, CF_NS_SIZE);
-                cfNs        = htonll(cfNs) >> 16;
-                cfNs        += cfAddedVal;
-                cfNs        = htonll(cfNs) >> 16;
-                memcpy(&(ptPtpHdr->correctionField[0]), &cfNs, CF_NS_SIZE);
-
-                /* flagField字段的高1字节bit7清0 */
-                ptPtpHdr->flagField = (ptPtpHdr->flagField) & 0x7f;
-
-                /* 清除20 byte tTsi TLV为0 */
-                tsiTlv = ptpHdr + PTPHDR_TSI_TLV_OFFSET;
-                memset(tsiTlv, 0, PTPHDR_TSI_TLV_LEN);
-
-                /* 把Header中的messageLength值减去20 */
-                ptPtpHdr->msglen = htons(ptPtpHdr->msglen);
-                ptPtpHdr->msglen -= PTPHDR_TSI_TLV_LEN;
-                ptPtpHdr->msglen = htons(ptPtpHdr->msglen);
-            }
-        }
-        else /* 如果为1，则是两步法 */
-        {
-            /* 解析Flag字段高一字节bit7，如果为1，做如下处理，为0不做处理 */
-            if (0 != ((ptPtpHdr->flagField) & 0x8000))
-            {
-                memcpy(&tTsi, ptpHdr + PTPHDR_TSI_OFFSET, sizeof(Bits80_t));
-
-                bits_80_minus(*t5g, tTsi, &tMinusRet);
-
-                /* （*t5g-*tsi）*频率比 计算结果叠加到CF字段ns位，(不会出现CF字段ns位值溢出情况) */
-                frequency = htonl(ptPtpHdr-> msgTypeSpecific);
-                cfAddedVal  = (tMinusRet.s * S_HOLD + tMinusRet.ns) * frequency;
-                memcpy(&cfNs, ptPtpHdr->correctionField, CF_NS_SIZE);
-                cfNs        = htonll(cfNs) >> 16;
-                cfNs        += cfAddedVal;
-                cfNs        = htonll(cfNs) >> 16;
-                memcpy(&(ptPtpHdr->correctionField[0]), &cfNs, CF_NS_SIZE);
-
-                /* 将messagetypespecific清0 */
-                memset(&(ptPtpHdr->msgTypeSpecific), 0, sizeof(uint32_t));
-
-                /* flagField字段的高1字节bit7清0 */
-                ptPtpHdr->flagField = (ptPtpHdr->flagField) & 0x7f;
-
-                /* 清除20 byte tTsi TLV为0 */
-                tsiTlv = ptpHdr + PTPHDR_TSI_TLV_OFFSET_TWO;
-                memset(tsiTlv, 0, PTPHDR_TSI_TLV_LEN);
-
-                /* 把Header中的messageLength值减去20 */
-                ptPtpHdr->msglen = htons(ptPtpHdr->msglen);
-                ptPtpHdr->msglen -= PTPHDR_TSI_TLV_LEN;
-                ptPtpHdr->msglen = htons(ptPtpHdr->msglen);
-            }
-        }
-    }
-
-    /*PTPM的32bit的时间戳，写到 PI头的cpu_tx字段:高29位为ns位，低3bits位为小数ns位 */
-    cpuTx_frac_ns   = (hdr->cpu_tx) & 0x07;
-    cpuTx_ns        = *thw << CPU_TX_DECIMAL_NS;
-    hdr->cpu_tx     = htonl(cpuTx_ns + cpuTx_frac_ns); /* 大端对齐 */
-
-    /* 两个80bit时间戳（T1，T2）放到socket的ERR_QUEUE中 */
-    tShhwtstamps.ts_5g_t    = *t5g;
-    tShhwtstamps.ts_tsn_t   = *tsn;
-    tHwtstamps5g.hwtstamp   = tShhwtstamps.ts_5g_t.ns + tShhwtstamps.ts_5g_t.s * S_HOLD;
-    tHwtstampsTsn.hwtstamp  = tShhwtstamps.ts_tsn_t.ns + tShhwtstamps.ts_tsn_t.s * S_HOLD;
-    skb_tstamp_tx(skb, &tHwtstamps5g);
-#ifdef CGEL_TSTAMP_2_PATCH_EN
-    skb_tstamp_tx_2(skb, &tHwtstampsTsn);
-#endif /* CGEL_TSTAMP_2_PATCH_EN */
-#endif
-    return PTP_RET_SUCCESS;
-}
-
-int32_t delay_and_pdelay_req_proc(struct sk_buff *skb,      \
-                                struct zxdh_net_hdr *hdr,   \
-                                struct time_stamps *t5g,    \
-                                struct time_stamps *tsn,    \
-                                uint32_t *thw)
-{
-#ifdef TIME_STAMP_1588
-    struct SkbSharedHwtstamps_t tShhwtstamps;
-    struct skb_shared_hwtstamps tHwtstamps5g;
-    struct skb_shared_hwtstamps tHwtstampsTsn;
-    uint32_t    cpuTx_ns        = 0;
-    uint32_t    cpuTx_frac_ns   = 0;
-
-    memset(&tShhwtstamps, 0, sizeof(struct SkbSharedHwtstamps_t));
-    memset(&tHwtstamps5g, 0, sizeof(struct skb_shared_hwtstamps));
-    memset(&tHwtstampsTsn, 0, sizeof(struct skb_shared_hwtstamps));
-    /*PTPM的32bit的时间戳，写到 PI头的cpu_tx字段:高29位为ns位，低3bits位为小数ns位 */
-    cpuTx_frac_ns   = (hdr->cpu_tx) & 0x07;
-    cpuTx_ns        = *thw << CPU_TX_DECIMAL_NS;
-    hdr->cpu_tx     = htonl(cpuTx_ns + cpuTx_frac_ns);
-
-    tShhwtstamps.ts_5g_t  = *t5g;
-    tShhwtstamps.ts_tsn_t = *tsn;
-
-    /* 2个80bit放到socket error queue中 */
-    tHwtstamps5g.hwtstamp  = tShhwtstamps.ts_5g_t.ns + tShhwtstamps.ts_5g_t.s * S_HOLD;
-    tHwtstampsTsn.hwtstamp = tShhwtstamps.ts_tsn_t.ns + tShhwtstamps.ts_tsn_t.s * S_HOLD;
-    skb_tstamp_tx(skb, &tHwtstamps5g);
-#ifdef CGEL_TSTAMP_2_PATCH_EN
-    skb_tstamp_tx_2(skb, &tHwtstampsTsn);
-#endif /* CGEL_TSTAMP_2_PATCH_EN */
-#endif
-    return PTP_RET_SUCCESS;
-}
-
-int32_t pkt_proc_type_delay_req(struct sk_buff *skb,               \
-                                struct zxdh_net_hdr *hdr,          \
-                                uint8_t *ptpHdr,                   \
-                                struct time_stamps *t5g,           \
-                                struct time_stamps *tsn,           \
-                                uint32_t *thw,                     \
-                                struct zxdh_en_device *en_dev)
-{
-    int32_t ret = 0;
-    ret = delay_and_pdelay_req_proc(skb, hdr, t5g, tsn, thw);
-    return ret;
-}
-
-int32_t pkt_proc_type_pdelay_req(struct sk_buff *skb,              \
-                                struct zxdh_net_hdr *hdr,          \
-                                uint8_t *ptpHdr,                   \
-                                struct time_stamps *t5g,           \
-                                struct time_stamps *tsn,           \
-                                uint32_t *thw,                     \
-                                struct zxdh_en_device *en_dev)
-{
-    int32_t ret = 0;
-    ret = delay_and_pdelay_req_proc(skb, hdr, t5g, tsn, thw);
-    return ret;
-}
-
-int32_t pkt_proc_type_pdelay_resp(struct sk_buff *skb,             \
-                                struct zxdh_net_hdr *hdr,          \
-                                uint8_t *ptpHdr,                   \
-                                struct time_stamps *t5g,           \
-                                struct time_stamps *tsn,           \
-                                uint32_t *thw,                     \
-                                struct zxdh_en_device *en_dev)
-{
-#ifdef TIME_STAMP_1588
-    Bits80_t                        tReqReceTs;
-    struct SkbSharedHwtstamps_t     tShhwtstamps;
-    struct skb_shared_hwtstamps     tHwtstamps5g;
-    struct skb_shared_hwtstamps     tHwtstampsTsn;
-    struct time_stamps              tMinusRet;
-    struct ptpHdr_t *ptPtpHdr       = NULL;
-    uint64_t        MinusVal        = 0;
-    uint32_t        cpuTx_ns        = 0;
-    uint32_t        cpuTx_frac_ns   = 0;
-    uint64_t        cfNs            = 0;
-
-    memset(&tReqReceTs, 0, sizeof(Bits80_t));
-    memset(&tShhwtstamps, 0, sizeof(struct SkbSharedHwtstamps_t));
-    memset(&tMinusRet, 0, sizeof(struct time_stamps));
-    memset(&tHwtstamps5g, 0, sizeof(struct skb_shared_hwtstamps));
-    memset(&tHwtstampsTsn, 0, sizeof(struct skb_shared_hwtstamps));
-    ptPtpHdr        = (struct ptpHdr_t *)ptpHdr;
-
-    /*PTPM的32bit的时间戳，写到 PI头的cpu_tx字段:高29位为ns位，低3bits位为小数ns位 */
-    cpuTx_frac_ns   = (hdr->cpu_tx) & 0x07;
-    cpuTx_ns        = *thw << CPU_TX_DECIMAL_NS;
-    hdr->cpu_tx     = htonl(cpuTx_ns + cpuTx_frac_ns);
-
-    /* 解析Header中flagField的低1字节的bit1，如果是0（一步法） */
-    if (0 == (ptPtpHdr->flagField & 0x0002))
-    {
-        /* 提取requestRecieptTimestamp */
-        tReqReceTs = *(Bits80_t *)(ptpHdr + sizeof(struct ptpHdr_t)); /* 记为T2 */
-
-        /* 将*tsn-T2的差值加到CorrectionField字段的高48bit ns位上 */
-        bits_80_minus(*tsn, tReqReceTs, &tMinusRet);
-        MinusVal = tMinusRet.ns + tMinusRet.s * S_HOLD;
-        memcpy(&cfNs, ptPtpHdr->correctionField, CF_NS_SIZE);
-        cfNs        = htonll(cfNs) >> 16;
-        cfNs        += MinusVal;
-        cfNs        = htonll(cfNs) >> 16;
-        memcpy(&(ptPtpHdr->correctionField[0]), &cfNs, CF_NS_SIZE);
-    }
-
-    tShhwtstamps.ts_5g_t  = *t5g;
-    tShhwtstamps.ts_tsn_t = *tsn;
-
-    /* 2个80bit放到socket error queue中 */
-    tHwtstamps5g.hwtstamp  = tShhwtstamps.ts_5g_t.ns + tShhwtstamps.ts_5g_t.s * S_HOLD;
-    tHwtstampsTsn.hwtstamp = tShhwtstamps.ts_tsn_t.ns + tShhwtstamps.ts_tsn_t.s * S_HOLD;
-    skb_tstamp_tx(skb, &tHwtstamps5g);
-#ifdef  CGEL_TSTAMP_2_PATCH_EN
-    skb_tstamp_tx_2(skb, &tHwtstampsTsn);
-#endif /* CGEL_TSTAMP_2_PATCH_EN */
-#endif
-    return PTP_RET_SUCCESS;
-}
-
-/* 接收方向的事件报文的时间戳处理函数：在1588驱动中对接收方向的事件报文的时间戳处理是一致的 */
-int32_t pkt_rcv_type_event(struct zxdh_net_hdr_rcv *hdr,                    \
-                            uint8_t *ptpHdr,                            \
-                            struct time_stamps *t5g,                    \
-                            struct time_stamps *tsn,                    \
-                            uint32_t *thw,                              \
-                            struct skb_shared_info *ptSkbSharedInfo,    \
-                            struct zxdh_en_device *en_dev)
-{
-#ifdef TIME_STAMP_1588
-    struct SkbSharedHwtstamps_t tShhwtstamps;
-    uint32_t    tsRx            = 0;
-    uint32_t    tsRx_ns         = 0;
-    uint32_t    tsRx_frac_ns    = 0;
-    int32_t     MinusRetThwCpu  = 0;
-    uint64_t    temp            = 0x20000000;
-    uint32_t    i               = 0;
-
-    memset(&tShhwtstamps, 0, sizeof(struct SkbSharedHwtstamps_t));
-    /* cpu_tx高29bits ns位，低3bits小数ns位 */
-    tsRx = htonl(hdr->rx_ts);
-
-    tsRx_frac_ns = tsRx & 0x07;
-    tsRx_ns = tsRx >> 3;
-    // LOG_DEBUG("hdr->rx_ts = %d, tsRx = %d, tsRx_ns = %d\n", hdr->rx_ts, tsRx, tsRx_ns);
-
-    if (tsRx_frac_ns > 4)
-    {
-        tsRx_ns += 1;
-    }
-    // LOG_DEBUG("thw = %d, tsRx_ns = %d\n", *thw, tsRx_ns);
-    MinusRetThwCpu = (*thw & 0x1fffffff) - tsRx_ns;
-
-    if(MinusRetThwCpu < 0)
-    {
-        MinusRetThwCpu += temp;
-    }
-
-    LOG_DEBUG("MinusRetThwCpu = %d\n", MinusRetThwCpu);
-
-    tShhwtstamps.ts_5g_t  = *t5g;
-    tShhwtstamps.ts_tsn_t = *tsn;
-
-    /* 更新两个80bits时间戳 */
-    if (tShhwtstamps.ts_5g_t.ns > MinusRetThwCpu)
-    {
-        tShhwtstamps.ts_5g_t.ns -= MinusRetThwCpu;
-    }
-    else
-    {
-        for (i = 1; i < tShhwtstamps.ts_5g_t.s + 1; i++)
-        {
-            temp = i * S_HOLD + tShhwtstamps.ts_5g_t.ns;
-
-            if (temp > MinusRetThwCpu)
-            {
-                tShhwtstamps.ts_5g_t.ns = temp - MinusRetThwCpu;
-                tShhwtstamps.ts_5g_t.s -= i;
-                break;
-            }
-        }
-        if (temp < MinusRetThwCpu)
-        {
-            LOG_ERR("ts_5g_t < MinusRetThwCpu!!!\n");
-        }
-    }
-
-    if (tShhwtstamps.ts_tsn_t.ns > MinusRetThwCpu)
-    {
-        tShhwtstamps.ts_tsn_t.ns -= MinusRetThwCpu;
-    }
-    else
-    {
-        for (i = 1; i < tShhwtstamps.ts_tsn_t.s + 1; i++)
-        {
-            temp = i * S_HOLD + tShhwtstamps.ts_tsn_t.ns;
-            if(temp > MinusRetThwCpu)
-            {
-                tShhwtstamps.ts_tsn_t.ns = temp - MinusRetThwCpu;
-                tShhwtstamps.ts_tsn_t.s -= i;
-                break;
-            }
-        }
-        if (temp < MinusRetThwCpu)
-        {
-            LOG_ERR("ts_tsn_t < MinusRetThwCpu!!!\n");
-        }
-    }
-
-    LOG_DEBUG("enter in pkt_rcv_type_event!!!!\n");
-    LOG_DEBUG("tShhwtstamps.ts_5g_t.s = %llu, tShhwtstamps.ts_5g_t.ns = %d\n", tShhwtstamps.ts_5g_t.s, tShhwtstamps.ts_5g_t.ns);
-    LOG_DEBUG("tShhwtstamps.ts_tsn_t.s = %llu, tShhwtstamps.ts_tsn_t.ns = %d\n", tShhwtstamps.ts_tsn_t.s, tShhwtstamps.ts_tsn_t.ns);
-
-    /* 2个80bit放到socket cmsg中。连同报文返回给应用 */
-    ptSkbSharedInfo->hwtstamps.hwtstamp = ktime_set(tShhwtstamps.ts_5g_t.s, tShhwtstamps.ts_5g_t.ns);
-#ifdef CGEL_TSTAMP_2_PATCH_EN
-    ptSkbSharedInfo->hwtstamps2.hwtstamp = ktime_set(tShhwtstamps.ts_tsn_t.s, tShhwtstamps.ts_tsn_t.ns);
-#endif /* CGEL_TSTAMP_2_PATCH_EN */
-#endif
-    return PTP_RET_SUCCESS;
-}
-
-/**
-* @fn read_ts_match_info
-* @brief 查询时间戳匹配信息，查询到匹配信息后更新cf字段和本地时间戳信息
-* @param msgType ptp事件报文类型
-* @return 返回值为0表示查询时间戳匹配信息成功
-*/
-int32_t read_ts_match_info(uint32_t msgType, uint8_t *ptpHdr)
-{
-    uint32_t            mssageType      = 0;
-    int32_t             cfNum           = 0;
-    uint32_t            srcPortIdFifo   = 0;
-    uint32_t            sequeIdFifo     = 0;
-    struct ptpHdr_t     *ptPtpHdr       = NULL;
-    uint32_t            matchInfo       = 0;
-    uint8_t             srcPortId       = 0;
-    uint64_t            cfVal           = 0;
-
-    ptPtpHdr = (struct ptpHdr_t *)ptpHdr;
-
-    CHECK_EQUAL_ERR(ptPtpHdr, NULL, -EADDRNOTAVAIL, "tPtpBuff is NULL\n");
-
-    srcPortId = *(uint8_t *)(ptPtpHdr->srcPortIdentity + SRCPORTID_LEN - 1); /* 只取srcPortIdentity最后一字节值 */
-
-    for (cfNum = 0; cfNum < tGlobalPtpBuff.cfCount; cfNum++)
-    {
-        matchInfo = tGlobalPtpBuff.ptpRegInfo[cfNum].matchInfo;
-        mssageType = (matchInfo >> MSGTYPE_OFFSET) & 0xf;
-        srcPortIdFifo = (matchInfo >> SRCPORTID_OFFSET) & 0xf;
-        sequeIdFifo = htons(matchInfo & 0xffff);
-
-        if((mssageType == msgType) &&              \
-           (srcPortIdFifo == (srcPortId & 0xf)) && \
-           (sequeIdFifo == ptPtpHdr->sequenceId))
-        {
-            LOG_DEBUG("read the match info successfully!!!\n");
-            LOG_DEBUG("mssageType: %u, srcPortIdFifo: %u, sequeIdFifo: %u\n", mssageType, srcPortIdFifo, sequeIdFifo);
-            memcpy(&cfVal, &(tGlobalPtpBuff.ptpRegInfo[cfNum].cfVal[0]), CF_SIZE);
-            cfVal = htonll(cfVal);
-            memcpy(&(ptPtpHdr->correctionField[0]), &cfVal, CF_SIZE);
-
-            /* 将匹配到的信息从本地buff去除 */
-            tGlobalPtpBuff.cfCount--;
-            if (cfNum == MAX_PTP_REG_INFO_NUM - 1)
-            {
-                memset(&(tGlobalPtpBuff.ptpRegInfo[cfNum]), 0, sizeof(struct ptp_reg_info));
-                return 0;
-            }
-            memcpy(&(tGlobalPtpBuff.ptpRegInfo[cfNum]), &(tGlobalPtpBuff.ptpRegInfo[cfNum + 1]), \
-                    (MAX_PTP_REG_INFO_NUM - cfNum - 1) * sizeof(struct ptp_reg_info));
-            memset(&(tGlobalPtpBuff.ptpRegInfo[MAX_PTP_REG_INFO_NUM - 1]), 0, sizeof(struct ptp_reg_info));
-
-            return 0;
-        }
-    }
-
-    return -1;
-}
-
-#ifdef  PTP_DRIVER_INTERFACE_EN
-extern int32_t get_event_ts_info(struct zxdh_en_device *en_dev, struct ptp_buff* p_tsInfo, int32_t mac_number);
-#endif /* PTP_DRIVER_INTERFACE_EN */
-
-/**
-* @fn general_encrypt_msg_proc
-* @brief 使用两步法，获取、存储和处理不同的ptp加密事件报文的时间戳信息
-* @param msgType ptp事件报文类型
-*/
-int32_t general_encrypt_msg_proc(uint32_t msgType, uint8_t *ptpHdr, struct zxdh_en_device *en_dev)
-{
-    int32_t             num             = 0;
-    int32_t             macNum          = 0;
-    int32_t             ret             = 0;
-    struct ptpHdr_t     *ptPtpHdr       = NULL;
-    struct ptp_buff     tempBuff;
-
-    memset(&tempBuff, 0, sizeof(struct ptp_buff));
-    ptPtpHdr = (struct ptpHdr_t *)ptpHdr;
-
-    /* 判断报文是否是加密报文 */
-    if (!(0x0080 == ((ptPtpHdr->flagField) & 0x0080)))
-    {
-        return ret;
-    }
-
-    macNum = zxdh_pf_macpcs_num_get(en_dev);
-    if (macNum < 0)
-    {
-        LOG_ERR("get mac num %d err, its value should is 0-2!\n", macNum);
-        return -1;
-    }
-
-    // LOG_INFO("ptp buff:\n ");
-    // print_data((uint8_t *)&tGlobalPtpBuff, sizeof(struct ptp_update_buff));
-
-    /* 1、从本地buff查询和处理时间戳匹配信息，并更新本地buff */
-    ret = read_ts_match_info(msgType, ptpHdr);
-
-    /* 2、从本地没匹配到信息，则读取FIFO中信息，将读取到的信息更新到本地，重新匹配 */
-    if (ret != 0)
-    {
-        // LOG_INFO("cannot read the matchInfo from the BUFF!---------------");
-
-    #ifdef  PTP_DRIVER_INTERFACE_EN
-        ret = get_event_ts_info(en_dev, &tempBuff, macNum);
-        CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "read FIFO form ptpDriver failed!!!");
-    #endif /* PTP_DRIVER_INTERFACE_EN */
-
-        /* 2.1 将读取到到的FIFO信息，添加到本地全局buff */
-        if (tempBuff.cfCount > 0)
-        {
-            if (tempBuff.cfCount + tGlobalPtpBuff.cfCount < MAX_PTP_REG_INFO_NUM)
-            {
-                memcpy(&(tGlobalPtpBuff.ptpRegInfo[tGlobalPtpBuff.cfCount]),
-                    tempBuff.ptpRegInfo, sizeof(struct ptp_reg_info) * tempBuff.cfCount);
-
-                tGlobalPtpBuff.cfCount += tempBuff.cfCount;
-                // LOG_INFO("tGlobalPtpBuff.cfCount: %u\n", tGlobalPtpBuff.cfCount);
-            }
-            else /* 当超过64组时间戳信息时 */
-            {
-                num = tempBuff.cfCount + tGlobalPtpBuff.cfCount - MAX_PTP_REG_INFO_NUM;
-
-                /* 丢弃掉最先存在本地的信息(此信息更大的概率匹配不上) */
-                memcpy(&(tGlobalPtpBuff.ptpRegInfo[0]), &(tGlobalPtpBuff.ptpRegInfo[num]),
-                        sizeof(struct ptp_reg_info) * (MAX_PTP_REG_INFO_NUM - num));
-                tGlobalPtpBuff.cfCount -= num;
-
-                /* 添加新的信息到本地 */
-                memcpy(&(tGlobalPtpBuff.ptpRegInfo[tGlobalPtpBuff.cfCount]),
-                    tempBuff.ptpRegInfo, sizeof(struct ptp_reg_info) * tempBuff.cfCount);
-                tGlobalPtpBuff.cfCount = MAX_PTP_REG_INFO_NUM;
-            }
-
-            /* 2.2 在更新后的本地全局buff查询和处理匹配信息，并更新本地buff*/
-            ret = read_ts_match_info(msgType, ptpHdr);
-            CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "cannot read the matchInfo from the local BUFF!");
-        }
-    }
-
-    // LOG_INFO("ptp buff:\n ");
-    // print_data((uint8_t *)&tGlobalPtpBuff, sizeof(struct ptp_update_buff));
-
-    return ret;
-}
-
-
-int32_t pkt_proc_type_follow_up(struct sk_buff *skb,               \
-                                struct zxdh_net_hdr *hdr,          \
-                                uint8_t *ptpHdr,                   \
-                                struct time_stamps *t5g,           \
-                                struct time_stamps *tsn,           \
-                                uint32_t *thw,                     \
-                                struct zxdh_en_device *en_dev)
-{
-    int32_t ret = 0;
-    ret = general_encrypt_msg_proc(PTP_MSG_TYPE_SYNC, ptpHdr, en_dev);
-
-    return ret;
-}
-
-int32_t pkt_proc_type_delay_resp(struct sk_buff *skb,              \
-                                struct zxdh_net_hdr *hdr,          \
-                                uint8_t *ptpHdr,                   \
-                                struct time_stamps *t5g,           \
-                                struct time_stamps *tsn,           \
-                                uint32_t *thw,                     \
-                                struct zxdh_en_device *en_dev)
-{
-    return 0;
-}
-
-int32_t pkt_rcv_type_delay_resp(struct zxdh_net_hdr_rcv *hdr,               \
-                            uint8_t *ptpHdr,                            \
-                            struct time_stamps *t5g,                    \
-                            struct time_stamps *tsn,                    \
-                            uint32_t *thw,                              \
-                            struct skb_shared_info *ptSkbSharedInfo,    \
-                            struct zxdh_en_device *en_dev)
-{
-    int32_t ret = 0;
-    ret = general_encrypt_msg_proc(PTP_MSG_TYPE_DELAY_REQ, ptpHdr, en_dev);
-
-    return ret;
-}
-
-int32_t pkt_proc_type_pdelay_resp_follow_up(struct sk_buff *skb,               \
-                                            struct zxdh_net_hdr *hdr,          \
-                                            uint8_t *ptpHdr,                   \
-                                            struct time_stamps *t5g,           \
-                                            struct time_stamps *tsn,           \
-                                            uint32_t *thw,                     \
-                                            struct zxdh_en_device *en_dev)
-{
-    int32_t ret = 0;
-    ret = general_encrypt_msg_proc(PTP_MSG_TYPE_PDELAY_RESP, ptpHdr, en_dev);
-
-    return ret;
-}
-
-int32_t pkt_proc_type_announce(struct sk_buff *skb,            \
-                            struct zxdh_net_hdr *hdr,          \
-                            uint8_t *ptpHdr,                   \
-                            struct time_stamps *t5g,           \
-                            struct time_stamps *tsn,           \
-                            uint32_t *thw,                     \
-                            struct zxdh_en_device *en_dev)
-{
-    /* 驱动不做处理 */
-    return 0;
-}
-
-int32_t pkt_proc_type_signaling(struct sk_buff *skb,               \
-                                struct zxdh_net_hdr *hdr,          \
-                                uint8_t *ptpHdr,                   \
-                                struct time_stamps *t5g,           \
-                                struct time_stamps *tsn,           \
-                                uint32_t *thw,                     \
-                                struct zxdh_en_device *en_dev)
-{
-    /* 驱动不做处理 */
-    return 0;
-}
-
-int32_t pkt_proc_type_management(struct sk_buff *skb,              \
-                                struct zxdh_net_hdr *hdr,          \
-                                uint8_t *ptpHdr,                   \
-                                struct time_stamps *t5g,           \
-                                struct time_stamps *tsn,           \
-                                uint32_t *thw,                     \
-                                struct zxdh_en_device *en_dev)
-{
-    /* 驱动不做处理 */
-    return 0;
-}
+/*****************************************************************************
+(C) 2023 ZTE Corporation. 版权所有.
+
+文件名      : en_1588_pkt_proc_func.c
+内容摘要    : 不同数据类型包的处理接口实现
+作者/日期   : Limin / 2023.10.12
+版本        : 1.0
+*****************************************************************************/
+
+#include "en_1588_pkt_proc_func.h"
+#include "en_cmd.h"
+#include "en_ioctl.h"
+
+struct ptp_update_buff tGlobalPtpBuff = { 0 };
+
+uint64_t htonll(uint64_t u64_host)
+{
+	uint64_t u64_net = 0;
+	uint32_t u32_host_h = 0;
+	uint32_t u32_host_l = 0;
+
+	u32_host_l = u64_host & 0xffffffff;
+	u32_host_h = (u64_host >> 32) & 0xffffffff;
+
+	u64_net = htonl(u32_host_l);
+	u64_net = (u64_net << 32) | htonl(u32_host_h);
+
+	return u64_net;
+}
+
+/**
+ * @brief 计算两时间戳subtraction和minuend之差，并将差值赋值给*ptMinusRet
+ * @param minuend 高48bit为s位，低32bit为ns位
+ */
+int32_t bits_80_minus(struct time_stamps subtraction, Bits80_t minuend,
+					  struct time_stamps *ptMinusRet)
+{
+	uint64_t minusHigh48_s = 0;
+	uint32_t minusLow32_ns = 0;
+
+	/* 取出80bits被减数的ns位值和s位值 */
+	memcpy((uint8_t *)(&minusHigh48_s), &minuend, S_SIZE);
+	memcpy(&minusLow32_ns, (uint8_t *)(&minuend) + S_SIZE, NS_SIZE);
+
+	/* minuend大端 */
+	minusHigh48_s = htonll(minusHigh48_s) >> 16;
+	minusLow32_ns = htonl(minusLow32_ns);
+
+	/* 如果减数值小于被减数值 */
+	if ((subtraction.s < minusHigh48_s) || ((subtraction.s == minusHigh48_s) &&
+											(subtraction.ns < minusLow32_ns))) {
+		LOG_ERR("The difference between the two times is negative！！");
+		return PTP_RET_TIME_ERR;
+	}
+
+	if (subtraction.ns > minusLow32_ns) {
+		ptMinusRet->ns = subtraction.ns - minusLow32_ns; /* 赋值ns位 */
+		ptMinusRet->s = subtraction.s - minusHigh48_s; /* 赋值s位 */
+	} else {
+		ptMinusRet->ns =
+				S_HOLD - (minusLow32_ns - subtraction.ns); /* 赋值ns位 */
+		ptMinusRet->s = subtraction.s - minusHigh48_s - 1; /* 赋值s位 */
+	}
+
+	return PTP_RET_SUCCESS;
+}
+
+int32_t pkt_proc_type_sync(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+						   uint8_t *ptpHdr, struct time_stamps *t5g,
+						   struct time_stamps *tsn, uint32_t *thw,
+						   struct zxdh_en_device *en_dev)
+{
+	struct SkbSharedHwtstamps_t tShhwtstamps;
+	struct time_stamps tMinusRet;
+	struct skb_shared_hwtstamps tHwtstamps5g;
+	struct skb_shared_hwtstamps tHwtstampsTsn;
+	Bits80_t tTsi;
+	struct ptpHdr_t *ptPtpHdr = NULL;
+	uint8_t *pOriginTimeStamp = NULL;
+	uint8_t majorSdoId = 0;
+	uint32_t t5gNsBig = 0;
+	uint64_t t5gSBig = 0;
+	uint32_t tsnNsBig = 0;
+	uint64_t tsnSBig = 0;
+#ifdef TIME_STAMP_1588
+	uint32_t frequency = 0;
+	uint64_t cfAddedVal = 0;
+	uint8_t *tsiTlv = NULL;
+	uint32_t cpuTx_ns = 0;
+	uint32_t cpuTx_frac_ns = 0;
+	uint64_t cfNs = 0;
+#endif
+
+	ptPtpHdr = (struct ptpHdr_t *)ptpHdr;
+	majorSdoId = ((ptPtpHdr->majorType) & 0xf0) >> 4;
+	pOriginTimeStamp = ptpHdr + sizeof(struct ptpHdr_t);
+	t5gSBig = (htonll(t5g->s)) >> 16;
+	t5gNsBig = htonl(t5g->ns);
+	tsnSBig = (htonll(tsn->s)) >> 16;
+	tsnNsBig = htonl(tsn->ns);
+
+	memset(&tShhwtstamps, 0, sizeof(struct SkbSharedHwtstamps_t));
+	memset(&tHwtstamps5g, 0, sizeof(struct skb_shared_hwtstamps));
+	memset(&tHwtstampsTsn, 0, sizeof(struct skb_shared_hwtstamps));
+	memset(&tMinusRet, 0, sizeof(struct time_stamps));
+	memset(&tTsi, 0, sizeof(Bits80_t));
+#ifdef TIME_STAMP_1588
+	/* 解析PTP Header的majorSdoId字段，如果是0，表示PTP消息由1588使用 */
+	if (0 == majorSdoId) {
+		/* 解析Flag字段低一字节bit1，如果为0，则是一步法,为1不做处理 */
+		if (0 == ((ptPtpHdr->flagField) & 0x0002)) {
+			memcpy(pOriginTimeStamp, &t5gSBig, S_SIZE);
+			memcpy(pOriginTimeStamp + S_SIZE, &t5gNsBig, NS_SIZE);
+		}
+		/* 如果是1，表示PTP消息由802.1AS协议使用 */
+	} else if (1 == majorSdoId) {
+		/* 解析Flag字段低一字节bit1，如果为0，则是一步法 */
+		if (0 == ((ptPtpHdr->flagField) & 0x0002)) {
+			/* tsn时间戳放到Sync报文的originTimestamp字段 */
+			memcpy(pOriginTimeStamp, &tsnSBig, S_SIZE);
+			memcpy(pOriginTimeStamp + S_SIZE, &tsnNsBig, NS_SIZE);
+
+			/* 解析Flag字段高一字节bit7，如果为1，做如下处理，为0不做处理*/
+			if (0 != ((ptPtpHdr->flagField) & 0x8000)) {
+				frequency = *(uint32_t *)(ptpHdr + PTPHDR_FREQUENCY_OFFSET);
+				frequency = htonl(frequency); /* 频率比 */
+
+				memcpy(&tTsi, ptpHdr + PTPHDR_TSI_OFFSET, sizeof(Bits80_t));
+
+				bits_80_minus(*t5g, tTsi, &tMinusRet);
+
+				/* （*t5g-*tsi）*频率比* 计算结果叠加到CF字段ns位，(不会出现CF字段ns位值溢出情况) */
+				cfAddedVal = (tMinusRet.s * S_HOLD + tMinusRet.ns) * frequency;
+				memcpy(&cfNs, ptPtpHdr->correctionField, CF_NS_SIZE);
+				cfNs = htonll(cfNs) >> 16;
+				cfNs += cfAddedVal;
+				cfNs = htonll(cfNs) >> 16;
+				memcpy(&(ptPtpHdr->correctionField[0]), &cfNs, CF_NS_SIZE);
+
+				/* flagField字段的高1字节bit7清0 */
+				ptPtpHdr->flagField = (ptPtpHdr->flagField) & 0x7f;
+
+				/* 清除20 byte tTsi TLV为0 */
+				tsiTlv = ptpHdr + PTPHDR_TSI_TLV_OFFSET;
+				memset(tsiTlv, 0, PTPHDR_TSI_TLV_LEN);
+
+				/* 把Header中的messageLength值减去20 */
+				ptPtpHdr->msglen = htons(ptPtpHdr->msglen);
+				ptPtpHdr->msglen -= PTPHDR_TSI_TLV_LEN;
+				ptPtpHdr->msglen = htons(ptPtpHdr->msglen);
+			}
+			/* 如果为1，则是两步法 */
+		} else {
+			/* 解析Flag字段高一字节bit7，如果为1，做如下处理，为0不做处理 */
+			if (0 != ((ptPtpHdr->flagField) & 0x8000)) {
+				memcpy(&tTsi, ptpHdr + PTPHDR_TSI_OFFSET, sizeof(Bits80_t));
+
+				bits_80_minus(*t5g, tTsi, &tMinusRet);
+
+				/* （*t5g-*tsi）*频率比* 计算结果叠加到CF字段ns位，(不会出现CF字段ns位值溢出情况) */
+				frequency = htonl(ptPtpHdr->msgTypeSpecific);
+				cfAddedVal = (tMinusRet.s * S_HOLD + tMinusRet.ns) * frequency;
+				memcpy(&cfNs, ptPtpHdr->correctionField, CF_NS_SIZE);
+				cfNs = htonll(cfNs) >> 16;
+				cfNs += cfAddedVal;
+				cfNs = htonll(cfNs) >> 16;
+				memcpy(&(ptPtpHdr->correctionField[0]), &cfNs, CF_NS_SIZE);
+
+				/* 将messagetypespecific清0 */
+				memset(&(ptPtpHdr->msgTypeSpecific), 0, sizeof(uint32_t));
+
+				/* flagField字段的高1字节bit7清0 */
+				ptPtpHdr->flagField = (ptPtpHdr->flagField) & 0x7f;
+
+				/* 清除20 byte tTsi TLV为0 */
+				tsiTlv = ptpHdr + PTPHDR_TSI_TLV_OFFSET_TWO;
+				memset(tsiTlv, 0, PTPHDR_TSI_TLV_LEN);
+
+				/* 把Header中的messageLength值减去20 */
+				ptPtpHdr->msglen = htons(ptPtpHdr->msglen);
+				ptPtpHdr->msglen -= PTPHDR_TSI_TLV_LEN;
+				ptPtpHdr->msglen = htons(ptPtpHdr->msglen);
+			}
+		}
+	}
+
+	/*PTPM的32bit的时间戳，写到 PI头的cpu_tx字段:高29位为ns位，低3bits位为小数ns位
+   */
+	cpuTx_frac_ns = (hdr->cpu_tx) & 0x07;
+	cpuTx_ns = *thw << CPU_TX_DECIMAL_NS;
+	hdr->cpu_tx = htonl(cpuTx_ns + cpuTx_frac_ns); /* 大端对齐 */
+
+	/* 两个80bit时间戳（T1，T2）放到socket的ERR_QUEUE中 */
+	tShhwtstamps.ts_5g_t = *t5g;
+	tShhwtstamps.ts_tsn_t = *tsn;
+	tHwtstamps5g.hwtstamp =
+			tShhwtstamps.ts_5g_t.ns + tShhwtstamps.ts_5g_t.s * S_HOLD;
+	tHwtstampsTsn.hwtstamp =
+			tShhwtstamps.ts_tsn_t.ns + tShhwtstamps.ts_tsn_t.s * S_HOLD;
+	skb_tstamp_tx(skb, &tHwtstamps5g);
+#ifdef CGEL_TSTAMP_2_PATCH_EN
+	skb_tstamp_tx_2(skb, &tHwtstampsTsn);
+#endif /* CGEL_TSTAMP_2_PATCH_EN */
+#endif
+	return PTP_RET_SUCCESS;
+}
+
+int32_t delay_and_pdelay_req_proc(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								  struct time_stamps *t5g,
+								  struct time_stamps *tsn, uint32_t *thw)
+{
+#ifdef TIME_STAMP_1588
+	struct SkbSharedHwtstamps_t tShhwtstamps;
+	struct skb_shared_hwtstamps tHwtstamps5g;
+	struct skb_shared_hwtstamps tHwtstampsTsn;
+	uint32_t cpuTx_ns = 0;
+	uint32_t cpuTx_frac_ns = 0;
+
+	memset(&tShhwtstamps, 0, sizeof(struct SkbSharedHwtstamps_t));
+	memset(&tHwtstamps5g, 0, sizeof(struct skb_shared_hwtstamps));
+	memset(&tHwtstampsTsn, 0, sizeof(struct skb_shared_hwtstamps));
+	/*PTPM的32bit的时间戳，写到 PI头的cpu_tx字段:高29位为ns位，低3bits位为小数ns位
+   */
+	cpuTx_frac_ns = (hdr->cpu_tx) & 0x07;
+	cpuTx_ns = *thw << CPU_TX_DECIMAL_NS;
+	hdr->cpu_tx = htonl(cpuTx_ns + cpuTx_frac_ns);
+
+	tShhwtstamps.ts_5g_t = *t5g;
+	tShhwtstamps.ts_tsn_t = *tsn;
+
+	/* 2个80bit放到socket error queue中 */
+	tHwtstamps5g.hwtstamp =
+			tShhwtstamps.ts_5g_t.ns + tShhwtstamps.ts_5g_t.s * S_HOLD;
+	tHwtstampsTsn.hwtstamp =
+			tShhwtstamps.ts_tsn_t.ns + tShhwtstamps.ts_tsn_t.s * S_HOLD;
+	skb_tstamp_tx(skb, &tHwtstamps5g);
+#ifdef CGEL_TSTAMP_2_PATCH_EN
+	skb_tstamp_tx_2(skb, &tHwtstampsTsn);
+#endif /* CGEL_TSTAMP_2_PATCH_EN */
+#endif
+	return PTP_RET_SUCCESS;
+}
+
+int32_t pkt_proc_type_delay_req(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								uint8_t *ptpHdr, struct time_stamps *t5g,
+								struct time_stamps *tsn, uint32_t *thw,
+								struct zxdh_en_device *en_dev)
+{
+	int32_t ret = 0;
+	ret = delay_and_pdelay_req_proc(skb, hdr, t5g, tsn, thw);
+	return ret;
+}
+
+int32_t pkt_proc_type_pdelay_req(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								 uint8_t *ptpHdr, struct time_stamps *t5g,
+								 struct time_stamps *tsn, uint32_t *thw,
+								 struct zxdh_en_device *en_dev)
+{
+	int32_t ret = 0;
+	ret = delay_and_pdelay_req_proc(skb, hdr, t5g, tsn, thw);
+	return ret;
+}
+
+int32_t pkt_proc_type_pdelay_resp(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								  uint8_t *ptpHdr, struct time_stamps *t5g,
+								  struct time_stamps *tsn, uint32_t *thw,
+								  struct zxdh_en_device *en_dev)
+{
+#ifdef TIME_STAMP_1588
+	Bits80_t tReqReceTs;
+	struct SkbSharedHwtstamps_t tShhwtstamps;
+	struct skb_shared_hwtstamps tHwtstamps5g;
+	struct skb_shared_hwtstamps tHwtstampsTsn;
+	struct time_stamps tMinusRet;
+	struct ptpHdr_t *ptPtpHdr = NULL;
+	uint64_t MinusVal = 0;
+	uint32_t cpuTx_ns = 0;
+	uint32_t cpuTx_frac_ns = 0;
+	uint64_t cfNs = 0;
+
+	memset(&tReqReceTs, 0, sizeof(Bits80_t));
+	memset(&tShhwtstamps, 0, sizeof(struct SkbSharedHwtstamps_t));
+	memset(&tMinusRet, 0, sizeof(struct time_stamps));
+	memset(&tHwtstamps5g, 0, sizeof(struct skb_shared_hwtstamps));
+	memset(&tHwtstampsTsn, 0, sizeof(struct skb_shared_hwtstamps));
+	ptPtpHdr = (struct ptpHdr_t *)ptpHdr;
+
+	/*PTPM的32bit的时间戳，写到 PI头的cpu_tx字段:高29位为ns位，低3bits位为小数ns位
+   */
+	cpuTx_frac_ns = (hdr->cpu_tx) & 0x07;
+	cpuTx_ns = *thw << CPU_TX_DECIMAL_NS;
+	hdr->cpu_tx = htonl(cpuTx_ns + cpuTx_frac_ns);
+
+	/* 解析Header中flagField的低1字节的bit1，如果是0（一步法） */
+	if (0 == (ptPtpHdr->flagField & 0x0002)) {
+		/* 提取requestRecieptTimestamp */
+		tReqReceTs =
+				*(Bits80_t *)(ptpHdr + sizeof(struct ptpHdr_t)); /* 记为T2 */
+
+		/* 将*tsn-T2的差值加到CorrectionField字段的高48bit ns位上 */
+		bits_80_minus(*tsn, tReqReceTs, &tMinusRet);
+		MinusVal = tMinusRet.ns + tMinusRet.s * S_HOLD;
+		memcpy(&cfNs, ptPtpHdr->correctionField, CF_NS_SIZE);
+		cfNs = htonll(cfNs) >> 16;
+		cfNs += MinusVal;
+		cfNs = htonll(cfNs) >> 16;
+		memcpy(&(ptPtpHdr->correctionField[0]), &cfNs, CF_NS_SIZE);
+	}
+
+	tShhwtstamps.ts_5g_t = *t5g;
+	tShhwtstamps.ts_tsn_t = *tsn;
+
+	/* 2个80bit放到socket error queue中 */
+	tHwtstamps5g.hwtstamp =
+			tShhwtstamps.ts_5g_t.ns + tShhwtstamps.ts_5g_t.s * S_HOLD;
+	tHwtstampsTsn.hwtstamp =
+			tShhwtstamps.ts_tsn_t.ns + tShhwtstamps.ts_tsn_t.s * S_HOLD;
+	skb_tstamp_tx(skb, &tHwtstamps5g);
+#ifdef CGEL_TSTAMP_2_PATCH_EN
+	skb_tstamp_tx_2(skb, &tHwtstampsTsn);
+#endif /* CGEL_TSTAMP_2_PATCH_EN */
+#endif
+	return PTP_RET_SUCCESS;
+}
+
+/* 接收方向的事件报文的时间戳处理函数：在1588驱动中对接收方向的事件报文的时间戳处理是一致的
+ */
+int32_t pkt_rcv_type_event(struct zxdh_net_hdr_rcv *hdr, uint8_t *ptpHdr,
+						   struct time_stamps *t5g, struct time_stamps *tsn,
+						   uint32_t *thw,
+						   struct skb_shared_info *ptSkbSharedInfo,
+						   struct zxdh_en_device *en_dev)
+{
+#ifdef TIME_STAMP_1588
+	struct SkbSharedHwtstamps_t tShhwtstamps;
+	uint32_t tsRx = 0;
+	uint32_t tsRx_ns = 0;
+	uint32_t tsRx_frac_ns = 0;
+	int32_t MinusRetThwCpu = 0;
+	uint64_t temp = 0x20000000;
+	uint32_t i = 0;
+
+	memset(&tShhwtstamps, 0, sizeof(struct SkbSharedHwtstamps_t));
+	/* cpu_tx高29bits ns位，低3bits小数ns位 */
+	tsRx = htonl(hdr->rx_ts);
+
+	tsRx_frac_ns = tsRx & 0x07;
+	tsRx_ns = tsRx >> 3;
+	// LOG_DEBUG("hdr->rx_ts = %d, tsRx = %d, tsRx_ns = %d\n", hdr->rx_ts, tsRx,
+	// tsRx_ns);
+
+	if (tsRx_frac_ns > 4) {
+		tsRx_ns += 1;
+	}
+	// LOG_DEBUG("thw = %d, tsRx_ns = %d\n", *thw, tsRx_ns);
+	MinusRetThwCpu = (*thw & 0x1fffffff) - tsRx_ns;
+
+	if (MinusRetThwCpu < 0) {
+		MinusRetThwCpu += temp;
+	}
+
+	LOG_DEBUG("MinusRetThwCpu = %d\n", MinusRetThwCpu);
+
+	tShhwtstamps.ts_5g_t = *t5g;
+	tShhwtstamps.ts_tsn_t = *tsn;
+
+	/* 更新两个80bits时间戳 */
+	if (tShhwtstamps.ts_5g_t.ns > MinusRetThwCpu) {
+		tShhwtstamps.ts_5g_t.ns -= MinusRetThwCpu;
+	} else {
+		for (i = 1; i < tShhwtstamps.ts_5g_t.s + 1; i++) {
+			temp = i * S_HOLD + tShhwtstamps.ts_5g_t.ns;
+
+			if (temp > MinusRetThwCpu) {
+				tShhwtstamps.ts_5g_t.ns = temp - MinusRetThwCpu;
+				tShhwtstamps.ts_5g_t.s -= i;
+				break;
+			}
+		}
+		if (temp < MinusRetThwCpu) {
+			LOG_ERR("ts_5g_t < MinusRetThwCpu!!!\n");
+		}
+	}
+
+	if (tShhwtstamps.ts_tsn_t.ns > MinusRetThwCpu) {
+		tShhwtstamps.ts_tsn_t.ns -= MinusRetThwCpu;
+	} else {
+		for (i = 1; i < tShhwtstamps.ts_tsn_t.s + 1; i++) {
+			temp = i * S_HOLD + tShhwtstamps.ts_tsn_t.ns;
+			if (temp > MinusRetThwCpu) {
+				tShhwtstamps.ts_tsn_t.ns = temp - MinusRetThwCpu;
+				tShhwtstamps.ts_tsn_t.s -= i;
+				break;
+			}
+		}
+		if (temp < MinusRetThwCpu) {
+			LOG_ERR("ts_tsn_t < MinusRetThwCpu!!!\n");
+		}
+	}
+
+	LOG_DEBUG("enter in pkt_rcv_type_event!!!!\n");
+	LOG_DEBUG("tShhwtstamps.ts_5g_t.s = %llu, tShhwtstamps.ts_5g_t.ns = %d\n",
+			  tShhwtstamps.ts_5g_t.s, tShhwtstamps.ts_5g_t.ns);
+	LOG_DEBUG("tShhwtstamps.ts_tsn_t.s = %llu, tShhwtstamps.ts_tsn_t.ns = %d\n",
+			  tShhwtstamps.ts_tsn_t.s, tShhwtstamps.ts_tsn_t.ns);
+
+	/* 2个80bit放到socket cmsg中。连同报文返回给应用 */
+	ptSkbSharedInfo->hwtstamps.hwtstamp =
+			ktime_set(tShhwtstamps.ts_5g_t.s, tShhwtstamps.ts_5g_t.ns);
+#ifdef CGEL_TSTAMP_2_PATCH_EN
+	ptSkbSharedInfo->hwtstamps2.hwtstamp =
+			ktime_set(tShhwtstamps.ts_tsn_t.s, tShhwtstamps.ts_tsn_t.ns);
+#endif /* CGEL_TSTAMP_2_PATCH_EN */
+#endif
+	return PTP_RET_SUCCESS;
+}
+
+/**
+ * @fn read_ts_match_info
+ * @brief 查询时间戳匹配信息，查询到匹配信息后更新cf字段和本地时间戳信息
+ * @param msgType ptp事件报文类型
+ * @return 返回值为0表示查询时间戳匹配信息成功
+ */
+int32_t read_ts_match_info(uint32_t msgType, uint8_t *ptpHdr)
+{
+	uint32_t mssageType = 0;
+	int32_t cfNum = 0;
+	uint32_t srcPortIdFifo = 0;
+	uint32_t sequeIdFifo = 0;
+	struct ptpHdr_t *ptPtpHdr = NULL;
+	uint32_t matchInfo = 0;
+	uint8_t srcPortId = 0;
+	uint64_t cfVal = 0;
+
+	ptPtpHdr = (struct ptpHdr_t *)ptpHdr;
+
+	CHECK_EQUAL_ERR(ptPtpHdr, NULL, -EADDRNOTAVAIL, "tPtpBuff is NULL\n");
+
+	srcPortId = *(uint8_t *)(ptPtpHdr->srcPortIdentity + SRCPORTID_LEN -
+							 1); /* 只取srcPortIdentity最后一字节值 */
+
+	for (cfNum = 0; cfNum < tGlobalPtpBuff.cfCount; cfNum++) {
+		matchInfo = tGlobalPtpBuff.ptpRegInfo[cfNum].matchInfo;
+		mssageType = (matchInfo >> MSGTYPE_OFFSET) & 0xf;
+		srcPortIdFifo = (matchInfo >> SRCPORTID_OFFSET) & 0xf;
+		sequeIdFifo = htons(matchInfo & 0xffff);
+
+		if ((mssageType == msgType) && (srcPortIdFifo == (srcPortId & 0xf)) &&
+			(sequeIdFifo == ptPtpHdr->sequenceId)) {
+			LOG_DEBUG("read the match info successfully!!!\n");
+			LOG_DEBUG("mssageType: %u, srcPortIdFifo: %u, sequeIdFifo: %u\n",
+					  mssageType, srcPortIdFifo, sequeIdFifo);
+			memcpy(&cfVal, &(tGlobalPtpBuff.ptpRegInfo[cfNum].cfVal[0]),
+				   CF_SIZE);
+			cfVal = htonll(cfVal);
+			memcpy(&(ptPtpHdr->correctionField[0]), &cfVal, CF_SIZE);
+
+			/* 将匹配到的信息从本地buff去除 */
+			memcpy(&(tGlobalPtpBuff.ptpRegInfo[cfNum]),
+				   &(tGlobalPtpBuff.ptpRegInfo[cfNum + 1]),
+				   (MAX_PTP_REG_INFO_NUM - cfNum) *
+						   sizeof(struct ptp_reg_info));
+			tGlobalPtpBuff.cfCount--;
+
+			return 0;
+		}
+	}
+
+	return -1;
+}
+
+#ifdef PTP_DRIVER_INTERFACE_EN
+extern int32_t get_event_ts_info(struct zxdh_en_device *en_dev,
+								 struct ptp_buff *p_tsInfo, int32_t mac_number);
+#endif /* PTP_DRIVER_INTERFACE_EN */
+
+/**
+ * @fn general_encrypt_msg_proc
+ * @brief 使用两步法，获取、存储和处理不同的ptp加密事件报文的时间戳信息
+ * @param msgType ptp事件报文类型
+ */
+int32_t general_encrypt_msg_proc(uint32_t msgType, uint8_t *ptpHdr,
+								 struct zxdh_en_device *en_dev)
+{
+	int32_t num = 0;
+	int32_t macNum = 0;
+	int32_t ret = 0;
+	struct ptpHdr_t *ptPtpHdr = NULL;
+	struct ptp_buff tempBuff;
+
+	memset(&tempBuff, 0, sizeof(struct ptp_buff));
+	ptPtpHdr = (struct ptpHdr_t *)ptpHdr;
+
+	/* 判断报文是否是加密报文 */
+	if (!(0x0080 == ((ptPtpHdr->flagField) & 0x0080))) {
+		return ret;
+	}
+
+	macNum = zxdh_pf_macpcs_num_get(en_dev);
+	if (macNum < 0) {
+		LOG_ERR("get mac num %d err, its value should is 0-2!\n", macNum);
+		return -1;
+	}
+
+	// LOG_INFO("ptp buff:\n ");
+	// print_data((uint8_t *)&tGlobalPtpBuff, sizeof(struct ptp_update_buff));
+
+	/* 1、从本地buff查询和处理时间戳匹配信息，并更新本地buff */
+	ret = read_ts_match_info(msgType, ptpHdr);
+
+	/* 2、从本地没匹配到信息，则读取FIFO中信息，将读取到的信息更新到本地，重新匹配
+   */
+	if (ret != 0) {
+		// LOG_INFO("cannot read the matchInfo from the BUFF!---------------");
+
+#ifdef PTP_DRIVER_INTERFACE_EN
+		ret = get_event_ts_info(en_dev, &tempBuff, macNum);
+		CHECK_UNEQUAL_ERR(ret, 0, -EFAULT,
+						  "read FIFO form ptpDriver failed!!!");
+#endif /* PTP_DRIVER_INTERFACE_EN */
+
+		/* 2.1 将读取到到的FIFO信息，添加到本地全局buff */
+		if (tempBuff.cfCount > 0) {
+			if (tempBuff.cfCount + tGlobalPtpBuff.cfCount <
+				MAX_PTP_REG_INFO_NUM) {
+				memcpy(&(tGlobalPtpBuff.ptpRegInfo[tGlobalPtpBuff.cfCount]),
+					   tempBuff.ptpRegInfo,
+					   sizeof(struct ptp_reg_info) * tempBuff.cfCount);
+
+				tGlobalPtpBuff.cfCount += tempBuff.cfCount;
+				// LOG_INFO("tGlobalPtpBuff.cfCount: %u\n", tGlobalPtpBuff.cfCount);
+				/* 当超过64组时间戳信息时 */
+			} else {
+				num = tempBuff.cfCount + tGlobalPtpBuff.cfCount -
+					  MAX_PTP_REG_INFO_NUM;
+
+				/* 丢弃掉最先存在本地的信息(此信息更大的概率匹配不上) */
+				memcpy(&(tGlobalPtpBuff.ptpRegInfo[0]),
+					   &(tGlobalPtpBuff.ptpRegInfo[num]),
+					   sizeof(struct ptp_reg_info) *
+							   (MAX_PTP_REG_INFO_NUM - num));
+				tGlobalPtpBuff.cfCount -= num;
+
+				/* 添加新的信息到本地 */
+				memcpy(&(tGlobalPtpBuff.ptpRegInfo[tGlobalPtpBuff.cfCount]),
+					   tempBuff.ptpRegInfo,
+					   sizeof(struct ptp_reg_info) * tempBuff.cfCount);
+				tGlobalPtpBuff.cfCount = MAX_PTP_REG_INFO_NUM;
+			}
+
+			/* 2.2 在更新后的本地全局buff查询和处理匹配信息，并更新本地buff*/
+			ret = read_ts_match_info(msgType, ptpHdr);
+			CHECK_UNEQUAL_ERR(ret, 0, -EFAULT,
+							  "cannot read the matchInfo from the local BUFF!");
+		}
+	}
+
+	// LOG_INFO("ptp buff:\n ");
+	// print_data((uint8_t *)&tGlobalPtpBuff, sizeof(struct ptp_update_buff));
+
+	return ret;
+}
+
+int32_t pkt_proc_type_follow_up(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								uint8_t *ptpHdr, struct time_stamps *t5g,
+								struct time_stamps *tsn, uint32_t *thw,
+								struct zxdh_en_device *en_dev)
+{
+	int32_t ret = 0;
+	ret = general_encrypt_msg_proc(PTP_MSG_TYPE_SYNC, ptpHdr, en_dev);
+
+	return ret;
+}
+
+int32_t pkt_proc_type_delay_resp(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								 uint8_t *ptpHdr, struct time_stamps *t5g,
+								 struct time_stamps *tsn, uint32_t *thw,
+								 struct zxdh_en_device *en_dev)
+{
+	return 0;
+}
+
+int32_t pkt_rcv_type_delay_resp(struct zxdh_net_hdr_rcv *hdr, uint8_t *ptpHdr,
+								struct time_stamps *t5g,
+								struct time_stamps *tsn, uint32_t *thw,
+								struct skb_shared_info *ptSkbSharedInfo,
+								struct zxdh_en_device *en_dev)
+{
+	int32_t ret = 0;
+	ret = general_encrypt_msg_proc(PTP_MSG_TYPE_DELAY_REQ, ptpHdr, en_dev);
+
+	return ret;
+}
+
+int32_t pkt_proc_type_pdelay_resp_follow_up(
+		struct sk_buff *skb, struct zxdh_net_hdr *hdr, uint8_t *ptpHdr,
+		struct time_stamps *t5g, struct time_stamps *tsn, uint32_t *thw,
+		struct zxdh_en_device *en_dev)
+{
+	int32_t ret = 0;
+	ret = general_encrypt_msg_proc(PTP_MSG_TYPE_PDELAY_RESP, ptpHdr, en_dev);
+
+	return ret;
+}
+
+int32_t pkt_proc_type_announce(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+							   uint8_t *ptpHdr, struct time_stamps *t5g,
+							   struct time_stamps *tsn, uint32_t *thw,
+							   struct zxdh_en_device *en_dev)
+{
+	/* 驱动不做处理 */
+	return 0;
+}
+
+int32_t pkt_proc_type_signaling(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								uint8_t *ptpHdr, struct time_stamps *t5g,
+								struct time_stamps *tsn, uint32_t *thw,
+								struct zxdh_en_device *en_dev)
+{
+	/* 驱动不做处理 */
+	return 0;
+}
+
+int32_t pkt_proc_type_management(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								 uint8_t *ptpHdr, struct time_stamps *t5g,
+								 struct time_stamps *tsn, uint32_t *thw,
+								 struct zxdh_en_device *en_dev)
+{
+	/* 驱动不做处理 */
+	return 0;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc_func.h b/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc_func.h
index 191a8877e804dd8fc54d4de6e87a6d92ed72098c..e2a444c7f9a36ee7cd82467394cad563a022138c 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc_func.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/en_1588_pkt_proc_func.h
@@ -1,233 +1,192 @@
-/*****************************************************************************
-(C) 2023 ZTE Corporation. 版权所有.
-
-文件名      : en_1588_pkt_proc_func.h
-内容摘要    : 不同数据类型包的处理接口实现
-作者/日期   : Limin / 2023.10.12
-版本        : 1.0
-*****************************************************************************/
-
-#ifndef _EN_1588_PKT_PROC_FUNC_H_
-#define _EN_1588_PKT_PROC_FUNC_H_
-
-#ifdef __cplusplus
-    extern "C" {
-#endif /* __cplusplus */
-
-#include "../en_aux.h"
-#include "queue.h"
-
-#define PTP_REG_INFO_NUM                32
-#define MAX_PTP_REG_INFO_NUM            64
-
-/* MAC FIFO相关定义 */
-#define MSGTYPE_OFFSET                  20
-#define SRCPORTID_OFFSET                16
-
-/* PTP报文时间戳处理函数返回值 */
-#define PTP_RET_SUCCESS                 0
-#define PTP_RET_TIME_ERR                (-1)
-
-/* CF字段ns位和s位长度 */
-#define CF_DECIMAL_NS_SIZE              2
-#define CF_NS_SIZE                      6
-#define CF_SIZE                         8
-
-/* PTP时间戳长度 */
-#define PTP_TS_5G_LEN                   10
-#define PTP_TS_TSN_LEN                  10
-#define PTP_REQRECE_TS_LEN              10
-
-/* PTP报文后缀相关字段偏移和长度 */
-#define PTPHDR_FREQUENCY_OFFSET         54
-#define PTPHDR_TSI_OFFSET               86
-#define PTPHDR_TSI_TLV_OFFSET           76
-#define PTPHDR_TSI_TLV_OFFSET_TWO       44
-#define PTPHDR_TSI_TLV_LEN              20
-#define ORIGINTIMESTAMP_LEN             10
-#define FOLLOWUP_TLV_LEN                32
-#define TSITLV_LEN                      20
-#define SRCPORTID_LEN                   10
-
-/* 80bit时间戳ns位和s位长度 */
-#define S_SIZE                          6           /* 高48位 */
-#define NS_SIZE                         4           /* 低32位 */
-#define S_HOLD                          1000000000L /* 进位阈值，即低32位达到1e9 */
-
-/* pi头中cpu_tx字段，高29位为ns位，低3位为小数ns位 */
-#define CPU_TX_DECIMAL_NS               3
-#define CPU_TX_NS                       29
-
-typedef struct
-{
-    uint8_t data[S_SIZE + NS_SIZE];
-} Bits80_t;
-
-struct time_stamps
-{
-    uint64_t s;
-    uint32_t ns;
-};
-
-struct SkbSharedHwtstamps_t
-{
-    struct time_stamps ts_5g_t;
-    struct time_stamps ts_tsn_t;
-};
-
-struct ptpHdr_t
-{
-    uint8_t     majorType;              /* 高4位为majorSdoId，低4位为msgType */
-    uint8_t     versionPTP;
-    uint16_t    msglen;
-    uint8_t     domainNumber;
-    uint8_t     minorSdoId;
-    uint16_t    flagField;
-    uint8_t     correctionField[CF_SIZE];     /* 高48位为ns位，低16字节为小数ns位 */
-    uint32_t    msgTypeSpecific;        /* 大端 */
-    uint8_t     srcPortIdentity[SRCPORTID_LEN];
-    uint16_t    sequenceId;
-    uint8_t     controlField;
-    uint8_t     logMsgInterval;
-} __attribute__((packed));
-
-
-struct ptp_reg_info
-{
-    uint32_t cfVal[2]; //High寄存器是ns位，Low寄存器的高16bit是ns位，低16bit是ns小数位
-    uint32_t matchInfo; //保存的内容是[bit23:0]:  {MessageType[23:20], sourcePortIdentity[19:16], sequenceId[15:0]}
-};
-
-struct ptp_buff
-{
-    uint32_t cfCount;
-    struct ptp_reg_info ptpRegInfo[PTP_REG_INFO_NUM];
-};
-
-struct ptp_update_buff
-{
-    uint32_t cfCount;
-    struct ptp_reg_info ptpRegInfo[MAX_PTP_REG_INFO_NUM];
-};
-
-/* PTP报文类型枚举 */
-enum
-{
-    /* event message types */
-    PTP_MSG_TYPE_SYNC = 0,
-    PTP_MSG_TYPE_DELAY_REQ,
-    PTP_MSG_TYPE_PDELAY_REQ,
-    PTP_MSG_TYPE_PDELAY_RESP,
-
-    /* general message types */
-    PTP_MSG_TYPE_FOLLOW_UP = 8,
-    PTP_MSG_TYPE_DELAY_RESP,
-    PTP_MSG_TYPE_PDELAY_RESP_FOLLOW_UP,
-    PTP_MSG_TYPE_ANNOUNCE,
-    PTP_MSG_TYPE_SIGNALING,
-    PTP_MSG_TYPE_MANAGEMENT
-};
-
-uint64_t htonll(uint64_t u64_host);
-
-int32_t pkt_proc_type_sync(struct sk_buff *skb,                         \
-                           struct zxdh_net_hdr *hdr,                    \
-                           uint8_t *ptpHdr,                             \
-                           struct time_stamps *t5g,                     \
-                           struct time_stamps *tsn,                     \
-                           uint32_t *thw,                               \
-                           struct zxdh_en_device *en_dev);
-
-int32_t pkt_proc_type_delay_req(struct sk_buff *skb,                    \
-                                struct zxdh_net_hdr *hdr,               \
-                                uint8_t *ptpHdr,                        \
-                                struct time_stamps *t5g,                \
-                                struct time_stamps *tsn,                \
-                                uint32_t *thw,                          \
-                                struct zxdh_en_device *en_dev);
-
-int32_t pkt_proc_type_pdelay_req(struct sk_buff *skb,                   \
-                                struct zxdh_net_hdr *hdr,               \
-                                uint8_t *ptpHdr,                        \
-                                struct time_stamps *t5g,                \
-                                struct time_stamps *tsn,                \
-                                uint32_t *thw,                          \
-                                struct zxdh_en_device *en_dev);
-
-int32_t pkt_proc_type_pdelay_resp(struct sk_buff *skb,                  \
-                                struct zxdh_net_hdr *hdr,               \
-                                uint8_t *ptpHdr,                        \
-                                struct time_stamps *t5g,                \
-                                struct time_stamps *tsn,                \
-                                uint32_t *thw,                          \
-                                struct zxdh_en_device *en_dev);
-
-int32_t pkt_proc_type_follow_up(struct sk_buff *skb,                    \
-                                struct zxdh_net_hdr *hdr,               \
-                                uint8_t *ptpHdr,                        \
-                                struct time_stamps *t5g,                \
-                                struct time_stamps *tsn,                \
-                                uint32_t *thw,                          \
-                                struct zxdh_en_device *en_dev);
-
-int32_t pkt_proc_type_delay_resp(struct sk_buff *skb,                   \
-                                struct zxdh_net_hdr *hdr,               \
-                                uint8_t *ptpHdr,                        \
-                                struct time_stamps *t5g,                \
-                                struct time_stamps *tsn,                \
-                                uint32_t *thw,                          \
-                                struct zxdh_en_device *en_dev);
-
-int32_t pkt_proc_type_pdelay_resp_follow_up(struct sk_buff *skb,        \
-                                            struct zxdh_net_hdr *hdr,   \
-                                            uint8_t *ptpHdr,            \
-                                            struct time_stamps *t5g,    \
-                                            struct time_stamps *tsn,    \
-                                            uint32_t *thw,              \
-                                            struct zxdh_en_device *en_dev);
-
-int32_t pkt_proc_type_announce(struct sk_buff *skb,                     \
-                            struct zxdh_net_hdr *hdr,                   \
-                            uint8_t *ptpHdr,                            \
-                            struct time_stamps *t5g,                    \
-                            struct time_stamps *tsn,                    \
-                            uint32_t *thw,                              \
-                            struct zxdh_en_device *en_dev);
-
-int32_t pkt_proc_type_signaling(struct sk_buff *skb,                    \
-                                struct zxdh_net_hdr *hdr,               \
-                                uint8_t *ptpHdr,                        \
-                                struct time_stamps *t5g,                \
-                                struct time_stamps *tsn,                \
-                                uint32_t *thw,                          \
-                                struct zxdh_en_device *en_dev);
-
-int32_t pkt_proc_type_management(struct sk_buff *skb,                   \
-                                struct zxdh_net_hdr *hdr,               \
-                                uint8_t *ptpHdr,                        \
-                                struct time_stamps *t5g,                \
-                                struct time_stamps *tsn,                \
-                                uint32_t *thw,                          \
-                                struct zxdh_en_device *en_dev);
-
-int32_t pkt_rcv_type_event(struct zxdh_net_hdr_rcv *hdr,                \
-                          uint8_t *ptpHdr,                              \
-                          struct time_stamps *t5g,                      \
-                          struct time_stamps *tsn,                      \
-                          uint32_t *thw,                                \
-                          struct skb_shared_info *ptSkbSharedInfo,
-                          struct zxdh_en_device *en_dev);
-
-int32_t pkt_rcv_type_delay_resp(struct zxdh_net_hdr_rcv *hdr,           \
-                            uint8_t *ptpHdr,                            \
-                            struct time_stamps *t5g,                    \
-                            struct time_stamps *tsn,                    \
-                            uint32_t *thw,                              \
-                            struct skb_shared_info *ptSkbSharedInfo,
-                            struct zxdh_en_device *en_dev);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
+/*****************************************************************************
+(C) 2023 ZTE Corporation. 版权所有.
+
+文件名      : en_1588_pkt_proc_func.h
+内容摘要    : 不同数据类型包的处理接口实现
+作者/日期   : Limin / 2023.10.12
+版本        : 1.0
+*****************************************************************************/
+
+#ifndef _EN_1588_PKT_PROC_FUNC_H_
+#define _EN_1588_PKT_PROC_FUNC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "../en_aux.h"
+#include "queue.h"
+
+#define PTP_REG_INFO_NUM 32
+#define MAX_PTP_REG_INFO_NUM 64
+
+/* MAC FIFO相关定义 */
+#define MSGTYPE_OFFSET 20
+#define SRCPORTID_OFFSET 16
+
+/* PTP报文时间戳处理函数返回值 */
+#define PTP_RET_SUCCESS 0
+#define PTP_RET_TIME_ERR (-1)
+
+/* CF字段ns位和s位长度 */
+#define CF_DECIMAL_NS_SIZE 2
+#define CF_NS_SIZE 6
+#define CF_SIZE 8
+
+/* PTP时间戳长度 */
+#define PTP_TS_5G_LEN 10
+#define PTP_TS_TSN_LEN 10
+#define PTP_REQRECE_TS_LEN 10
+
+/* PTP报文后缀相关字段偏移和长度 */
+#define PTPHDR_FREQUENCY_OFFSET 54
+#define PTPHDR_TSI_OFFSET 86
+#define PTPHDR_TSI_TLV_OFFSET 76
+#define PTPHDR_TSI_TLV_OFFSET_TWO 44
+#define PTPHDR_TSI_TLV_LEN 20
+#define ORIGINTIMESTAMP_LEN 10
+#define FOLLOWUP_TLV_LEN 32
+#define TSITLV_LEN 20
+#define SRCPORTID_LEN 10
+
+/* 80bit时间戳ns位和s位长度 */
+#define S_SIZE 6 /* 高48位 */
+#define NS_SIZE 4 /* 低32位 */
+#define S_HOLD 1000000000L /* 进位阈值，即低32位达到1e9 */
+
+/* pi头中cpu_tx字段，高29位为ns位，低3位为小数ns位 */
+#define CPU_TX_DECIMAL_NS 3
+#define CPU_TX_NS 29
+
+typedef struct {
+	uint8_t data[S_SIZE + NS_SIZE];
+} Bits80_t;
+
+struct time_stamps {
+	uint64_t s;
+	uint32_t ns;
+};
+
+struct SkbSharedHwtstamps_t {
+	struct time_stamps ts_5g_t;
+	struct time_stamps ts_tsn_t;
+};
+
+struct ptpHdr_t {
+	uint8_t majorType; /* 高4位为majorSdoId，低4位为msgType */
+	uint8_t versionPTP;
+	uint16_t msglen;
+	uint8_t domainNumber;
+	uint8_t minorSdoId;
+	uint16_t flagField;
+	uint8_t correctionField[CF_SIZE]; /* 高48位为ns位，低16字节为小数ns位 */
+	uint32_t msgTypeSpecific; /* 大端 */
+	uint8_t srcPortIdentity[SRCPORTID_LEN];
+	uint16_t sequenceId;
+	uint8_t controlField;
+	uint8_t logMsgInterval;
+} __attribute__((packed));
+
+struct ptp_reg_info {
+	uint32_t cfVal
+			[2]; // High寄存器是ns位，Low寄存器的高16bit是ns位，低16bit是ns小数位
+	uint32_t matchInfo; //保存的内容是[bit23:0]:  {MessageType[23:20],
+			// sourcePortIdentity[19:16], sequenceId[15:0]}
+};
+
+struct ptp_buff {
+	uint32_t cfCount;
+	struct ptp_reg_info ptpRegInfo[PTP_REG_INFO_NUM];
+};
+
+struct ptp_update_buff {
+	uint32_t cfCount;
+	struct ptp_reg_info ptpRegInfo[MAX_PTP_REG_INFO_NUM];
+};
+
+/* PTP报文类型枚举 */
+enum {
+	/* event message types */
+	PTP_MSG_TYPE_SYNC = 0,
+	PTP_MSG_TYPE_DELAY_REQ,
+	PTP_MSG_TYPE_PDELAY_REQ,
+	PTP_MSG_TYPE_PDELAY_RESP,
+
+	/* general message types */
+	PTP_MSG_TYPE_FOLLOW_UP = 8,
+	PTP_MSG_TYPE_DELAY_RESP,
+	PTP_MSG_TYPE_PDELAY_RESP_FOLLOW_UP,
+	PTP_MSG_TYPE_ANNOUNCE,
+	PTP_MSG_TYPE_SIGNALING,
+	PTP_MSG_TYPE_MANAGEMENT
+};
+
+uint64_t htonll(uint64_t u64_host);
+
+int32_t pkt_proc_type_sync(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+						   uint8_t *ptpHdr, struct time_stamps *t5g,
+						   struct time_stamps *tsn, uint32_t *thw,
+						   struct zxdh_en_device *en_dev);
+
+int32_t pkt_proc_type_delay_req(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								uint8_t *ptpHdr, struct time_stamps *t5g,
+								struct time_stamps *tsn, uint32_t *thw,
+								struct zxdh_en_device *en_dev);
+
+int32_t pkt_proc_type_pdelay_req(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								 uint8_t *ptpHdr, struct time_stamps *t5g,
+								 struct time_stamps *tsn, uint32_t *thw,
+								 struct zxdh_en_device *en_dev);
+
+int32_t pkt_proc_type_pdelay_resp(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								  uint8_t *ptpHdr, struct time_stamps *t5g,
+								  struct time_stamps *tsn, uint32_t *thw,
+								  struct zxdh_en_device *en_dev);
+
+int32_t pkt_proc_type_follow_up(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								uint8_t *ptpHdr, struct time_stamps *t5g,
+								struct time_stamps *tsn, uint32_t *thw,
+								struct zxdh_en_device *en_dev);
+
+int32_t pkt_proc_type_delay_resp(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								 uint8_t *ptpHdr, struct time_stamps *t5g,
+								 struct time_stamps *tsn, uint32_t *thw,
+								 struct zxdh_en_device *en_dev);
+
+int32_t pkt_proc_type_pdelay_resp_follow_up(
+		struct sk_buff *skb, struct zxdh_net_hdr *hdr, uint8_t *ptpHdr,
+		struct time_stamps *t5g, struct time_stamps *tsn, uint32_t *thw,
+		struct zxdh_en_device *en_dev);
+
+int32_t pkt_proc_type_announce(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+							   uint8_t *ptpHdr, struct time_stamps *t5g,
+							   struct time_stamps *tsn, uint32_t *thw,
+							   struct zxdh_en_device *en_dev);
+
+int32_t pkt_proc_type_signaling(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								uint8_t *ptpHdr, struct time_stamps *t5g,
+								struct time_stamps *tsn, uint32_t *thw,
+								struct zxdh_en_device *en_dev);
+
+int32_t pkt_proc_type_management(struct sk_buff *skb, struct zxdh_net_hdr *hdr,
+								 uint8_t *ptpHdr, struct time_stamps *t5g,
+								 struct time_stamps *tsn, uint32_t *thw,
+								 struct zxdh_en_device *en_dev);
+
+int32_t pkt_rcv_type_event(struct zxdh_net_hdr_rcv *hdr, uint8_t *ptpHdr,
+						   struct time_stamps *t5g, struct time_stamps *tsn,
+						   uint32_t *thw,
+						   struct skb_shared_info *ptSkbSharedInfo,
+						   struct zxdh_en_device *en_dev);
+
+int32_t pkt_rcv_type_delay_resp(struct zxdh_net_hdr_rcv *hdr, uint8_t *ptpHdr,
+								struct time_stamps *t5g,
+								struct time_stamps *tsn, uint32_t *thw,
+								struct skb_shared_info *ptSkbSharedInfo,
+								struct zxdh_en_device *en_dev);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
 #endif /* _EN_1588_PKT_PROC_FUNC_H_ */
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/en_cmd.c b/src/net/drivers/net/ethernet/dinghai/en_aux/en_cmd.c
index c80e40206f86aaac42f05e2336954172505fdeae..7d1f1e4f99b7c71d3bef5ac563aaada42ca65ddc 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/en_cmd.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/en_cmd.c
@@ -5,1556 +5,1454 @@
 #include <linux/device.h>
 #include <linux/pci.h>
 #include <xen/xen.h>
-
 #include <linux/dinghai/dh_cmd.h>
 #include "../en_aux.h"
 #include "../en_np/table/include/dpp_tbl_api.h"
 #include "../msg_common.h"
 #include "en_cmd.h"
 
-static int32_t get_common_table_msg(struct zxdh_en_device *en_dev, uint16_t pcie_id, uint8_t field, void *ack);
-static int32_t write_queue_index_to_message(struct zxdh_en_device *en_dev, uint32_t queue_nums,
-                                            uint32_t field, uint16_t *bytes, uint16_t *data)
+static int32_t get_common_table_msg(struct zxdh_en_device *en_dev,
+									uint16_t pcie_id, uint8_t field, void *ack);
+static int32_t write_queue_index_to_message(struct zxdh_en_device *en_dev,
+											uint32_t queue_nums, uint32_t field,
+											uint16_t *bytes, uint16_t *data)
 {
-    uint32_t ix = 0;
-    uint16_t old_queue_nums = 0;
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-
-    if (OP_CODE_DATA_CHAN == field)
-    {
-        *bytes = (uint16_t)((queue_nums + 1) * ZXDH_QS_PAIRS);
-        data[0] = (uint16_t)queue_nums;
-
-        for (ix = 0; ix < queue_nums; ix = ix + ZXDH_QS_PAIRS)
-        {
-            data[ix + 1] = en_dev->rq[ix / ZXDH_QS_PAIRS].vq->phy_index;
-            data[ix + 2] = en_dev->sq[ix / ZXDH_QS_PAIRS].vq->phy_index;
-        }
-
-        if (en_dev->ops->is_bond(en_dev->parent))
-        {
-            ret = get_common_table_msg(en_dev, en_dev->pcie_id, OP_CODE_DATA_CHAN, &msg);
-            if (ret != 0)
-            {
-                LOG_ERR("Failed to get data queue: %d\n", ret);
-                return ret;
-            }
-
-            old_queue_nums = msg.reps.cmn_vq_msg.queue_nums;
-            if (old_queue_nums == 0)
-            {
-                return 0;
-            }
-
-            if ((old_queue_nums + queue_nums) > 256)
-            {
-                LOG_ERR("Exceeded the maximum number of queues, old_queue_nums(%d)\n", old_queue_nums);
-                return -1;
-            }
-
-            *bytes = (uint16_t)((queue_nums + old_queue_nums + 1) * ZXDH_QS_PAIRS);
-            data[0] = (uint16_t)(queue_nums + old_queue_nums);
-            memcpy(data + queue_nums + 1, msg.reps.cmn_vq_msg.phy_qidx, old_queue_nums * ZXDH_QS_PAIRS);
-
-            for (ix = 1; ix <= (queue_nums + old_queue_nums); ix++)
-            {
-                LOG_INFO("vq phy_qid: %d ", data[ix]);
-            }
-        }
-    }
+	uint32_t ix = 0;
+	zxdh_reps_info reps = { 0 };
+	uint16_t old_queue_nums = 0;
+	int32_t ret = 0;
+
+	if (OP_CODE_DATA_CHAN == field) {
+		*bytes = (uint16_t)((queue_nums + 1) * ZXDH_QS_PAIRS);
+		data[0] = (uint16_t)queue_nums;
+
+		for (ix = 0; ix < queue_nums; ix = ix + ZXDH_QS_PAIRS) {
+			data[ix + 1] = en_dev->rq[ix / ZXDH_QS_PAIRS].vq->phy_index;
+			data[ix + 2] = en_dev->sq[ix / ZXDH_QS_PAIRS].vq->phy_index;
+		}
+
+		if (en_dev->ops->is_bond(en_dev->parent)) {
+			ret = get_common_table_msg(en_dev, en_dev->pcie_id,
+									   OP_CODE_DATA_CHAN, &reps);
+			if (ret != 0) {
+				LOG_ERR("Failed to get data queue: %d\n", ret);
+				return ret;
+			}
+
+			old_queue_nums = reps.cmn_vq_msg.queue_nums;
+			if (old_queue_nums == 0) {
+				return 0;
+			}
+
+			LOG_INFO("old queue nums %d: ", old_queue_nums);
+			for (ix = 0; ix < old_queue_nums; ix++) {
+				LOG_INFO("%d ", reps.cmn_vq_msg.phy_qidx[ix]);
+			}
+
+			if ((old_queue_nums + queue_nums) > 256) {
+				LOG_ERR("Exceeded the maximum number of queues, old_queue_nums(%d)\n",
+						old_queue_nums);
+				return -1;
+			}
+
+			*bytes = (uint16_t)((queue_nums + old_queue_nums + 1) *
+								ZXDH_QS_PAIRS);
+			data[0] = (uint16_t)(queue_nums + old_queue_nums);
+			memcpy(data + queue_nums + 1, reps.cmn_vq_msg.phy_qidx,
+				   old_queue_nums * ZXDH_QS_PAIRS);
+
+			for (ix = 1; ix <= (queue_nums + old_queue_nums); ix++) {
+				LOG_INFO("%d ", data[ix]);
+			}
+		}
+	}
 #ifdef ZXDH_MSGQ
-    else if (OP_CODE_MSGQ_CHAN == field)
-    {
-        *bytes = (uint16_t)(queue_nums * ZXDH_QS_PAIRS);
-        data[0] = en_dev->rq[en_dev->curr_queue_pairs].vq->phy_index;
-        data[1] = en_dev->sq[en_dev->curr_queue_pairs].vq->phy_index;
-    }
+	else if (OP_CODE_MSGQ_CHAN == field) {
+		*bytes = (uint16_t)(queue_nums * ZXDH_QS_PAIRS);
+		data[0] = en_dev->rq[en_dev->curr_queue_pairs].vq->phy_index;
+		data[1] = en_dev->sq[en_dev->curr_queue_pairs].vq->phy_index;
+	}
 #endif
 
-    return 0;
+	return 0;
 }
 
-static int32_t cmd_tbl_messgae_to_riscv_send(struct zxdh_en_device *en_dev, void *payload, uint32_t pld_len)
+static int32_t cmd_tbl_messgae_to_riscv_send(struct zxdh_en_device *en_dev,
+											 void *payload, uint32_t pld_len)
 {
-    int32_t ret = 0;
-    struct cmd_hdr_recv *hdr_recv;
-    struct cmd_tbl_ack cmd_tbl_ack = {0};
-
-    ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_TBL, payload, &cmd_tbl_ack, true);
-    if (0 != ret)
-    {
-        LOG_ERR("en_dev->ops->msg_send_cmd failed\n");
-        goto out;
-    }
-
-    hdr_recv =(struct cmd_hdr_recv*)&cmd_tbl_ack;
-    if (hdr_recv->check != OP_CODE_TBL_STAT)
-    {
-        LOG_ERR("tbl init message recv check failed\n");
-        ret = -1;
-    }
+	int32_t ret = 0;
+	struct cmd_hdr_recv *hdr_recv;
+	struct cmd_tbl_ack cmd_tbl_ack = { 0 };
+
+	ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_TBL, payload,
+									&cmd_tbl_ack, true);
+	if (0 != ret) {
+		LOG_ERR("en_dev->ops->msg_send_cmd failed\n");
+		goto out;
+	}
+
+	hdr_recv = (struct cmd_hdr_recv *)&cmd_tbl_ack;
+	if (hdr_recv->check != OP_CODE_TBL_STAT) {
+		LOG_ERR("tbl init message recv check failed\n");
+		ret = -1;
+	}
 out:
-    return ret;
+	return ret;
 }
 
-static int32_t cmd_common_tbl_init(struct zxdh_en_device *en_dev, uint32_t queue_nums, uint32_t field)
+static int32_t cmd_common_tbl_init(struct zxdh_en_device *en_dev,
+								   uint32_t queue_nums, uint32_t field)
 {
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-
-    if ((2 * ZXDH_MAX_PAIRS_NUM) < queue_nums)
-    {
-        LOG_ERR("queue pairs %u out of range\n", queue_nums);
-        return -ENOMEM;
-    }
-
-    msg.payload.hdr_to_cmn.field = field;
-    msg.payload.hdr_to_cmn.type = OP_CODE_WRITE;
-    msg.payload.hdr_to_cmn.pcie_id = en_dev->pcie_id;
-    ret = write_queue_index_to_message(en_dev, queue_nums, field, \
-                    &msg.payload.hdr_to_cmn.write_bytes, msg.payload.cmn_tbl_msg);
-    if (0 != ret)
-    {
-        LOG_ERR("write_queue_index_to_message failed, ret: %d\n", ret);
-        return ret;
-    }
-
-    // 执行message send
-    ret = cmd_tbl_messgae_to_riscv_send(en_dev, &msg, MSG_STRUCT_HD_LEN + msg.payload.hdr_to_cmn.write_bytes);
-    if (0 != ret)
-    {
-        LOG_ERR("zxdh_bar_chan_sync_msg_send failed, ret: %d\n", ret);
-    }
-
-    return ret;
+	int32_t ret = 0;
+	zxdh_msg_info msg = { 0 };
+
+	if ((2 * ZXDH_MAX_PAIRS_NUM) < queue_nums) {
+		LOG_ERR("queue pairs %u out of range\n", queue_nums);
+		return -ENOMEM;
+	}
+
+	msg.hdr_to_cmn.field = field;
+	msg.hdr_to_cmn.type = OP_CODE_WRITE;
+	msg.hdr_to_cmn.pcie_id = en_dev->pcie_id;
+	ret = write_queue_index_to_message(en_dev, queue_nums, field,
+									   &msg.hdr_to_cmn.write_bytes,
+									   msg.cmn_tbl_msg);
+	if (0 != ret) {
+		LOG_ERR("write_queue_index_to_message failed, ret: %d\n", ret);
+		return ret;
+	}
+
+	// 执行message send
+	ret = cmd_tbl_messgae_to_riscv_send(
+			en_dev, &msg, MSG_STRUCT_HD_LEN + msg.hdr_to_cmn.write_bytes);
+	if (0 != ret) {
+		LOG_ERR("zxdh_bar_chan_sync_msg_send failed, ret: %d\n", ret);
+	}
+
+	return ret;
 }
 
 int32_t zxdh_common_tbl_init(struct net_device *netdev)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t ret = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t ret = 0;
 
 #ifdef ZXDH_MSGQ
-    NEED_MSGQ(en_dev)
-    {
-        ret = cmd_common_tbl_init(en_dev, ZXDH_QS_PAIRS, OP_CODE_MSGQ_CHAN);
-        if (0 != ret)
-        {
-            LOG_ERR("field msgq message failed\n");
-            return -1;
-        }
-    }
+	if (en_dev->need_msgq) {
+		ret = cmd_common_tbl_init(en_dev, ZXDH_QS_PAIRS, OP_CODE_MSGQ_CHAN);
+		if (0 != ret) {
+			LOG_ERR("field msgq message failed\n");
+			return -1;
+		}
+	}
 #endif
 
-    ret = cmd_common_tbl_init(en_dev, en_dev->curr_queue_pairs * ZXDH_QS_PAIRS, OP_CODE_DATA_CHAN);
-    if (0 != ret)
-    {
-        LOG_ERR("field data message failed\n");
-        return -1;
-    }
+	ret = cmd_common_tbl_init(en_dev, en_dev->curr_queue_pairs * ZXDH_QS_PAIRS,
+							  OP_CODE_DATA_CHAN);
+	if (0 != ret) {
+		LOG_ERR("field data message failed\n");
+		return -1;
+	}
 
-    return 0;
+	return 0;
 }
 
-int32_t zxdh_send_command_to_specify(struct zxdh_en_device *en_dev, uint16_t module_id, void *msg, void *ack)
+int32_t zxdh_send_command_to_specify(struct zxdh_en_device *en_dev,
+									 uint16_t module_id, void *msg, void *ack)
 {
-    struct dh_core_dev *dh_dev = en_dev->parent;
+	struct dh_core_dev *dh_dev = en_dev->parent;
 
-    return en_dev->ops->msg_send_cmd(dh_dev, module_id, msg, ack, true);
+	return en_dev->ops->msg_send_cmd(dh_dev, module_id, msg, ack, true);
 }
 
-static int32_t get_common_table_msg(struct zxdh_en_device *en_dev, uint16_t pcie_id, \
-                                    uint8_t field, void *ack)
+static int32_t get_common_table_msg(struct zxdh_en_device *en_dev,
+									uint16_t pcie_id, uint8_t field, void *ack)
 {
-    union zxdh_msg msg = {0};
+	zxdh_msg_info msg = { 0 };
 
-    msg.payload.hdr_to_cmn.type = RISC_TYPE_READ;
-    msg.payload.hdr_to_cmn.field = field;
-    msg.payload.hdr_to_cmn.pcie_id = pcie_id;
-    msg.payload.hdr_to_cmn.write_bytes = 0;
+	msg.hdr_to_cmn.type = RISC_TYPE_READ;
+	msg.hdr_to_cmn.field = field;
+	msg.hdr_to_cmn.pcie_id = pcie_id;
+	msg.hdr_to_cmn.write_bytes = 0;
 
-    return zxdh_send_command_to_specify(en_dev, MODULE_TBL, &msg, ack);
+	return zxdh_send_command_to_specify(en_dev, MODULE_TBL, &msg, ack);
 }
 
 int32_t zxdh_hash_id_get(struct zxdh_en_device *en_dev)
 {
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-
-    ret = get_common_table_msg(en_dev, en_dev->pcie_id, RISC_FIELD_HASHID_CHANNEL, &msg);
-    if(ret != 0)
-    {
-        LOG_ERR("get own hash_id failed: %d\n", ret);
-        return ret;
-    }
-
-    en_dev->hash_search_idx = msg.reps.cmn_recv_msg.value;
-    LOG_DEBUG("hash_id: %u\n", en_dev->hash_search_idx);
-    if (en_dev->hash_search_idx > ZXDH_MAX_HASH_INDEX)
-    {
-        LOG_ERR("hash_id is invalid value: %u\n", en_dev->hash_search_idx);
-        return -EINVAL;
-    }
-    if (en_dev->hash_search_idx == ZXDH_MAX_HASH_INDEX) //TODO:if should be delete
-    {
-        en_dev->hash_search_idx = 1;
-    }
-
-    return ret;
+	int32_t ret = 0;
+	zxdh_reps_info reps = { 0 };
+
+	ret = get_common_table_msg(en_dev, en_dev->pcie_id,
+							   RISC_FIELD_HASHID_CHANNEL, &reps);
+	if (ret != 0) {
+		LOG_ERR("get own hash_id failed: %d\n", ret);
+		return ret;
+	}
+
+	en_dev->hash_search_idx = reps.cmn_recv_msg.value;
+	LOG_DEBUG("hash_id: %u\n", en_dev->hash_search_idx);
+	if (en_dev->hash_search_idx > ZXDH_MAX_HASH_INDEX) {
+		LOG_ERR("hash_id is invalid value: %u\n", en_dev->hash_search_idx);
+		return -EINVAL;
+	}
+	// TODO:if should be delete
+	if (en_dev->hash_search_idx == ZXDH_MAX_HASH_INDEX) {
+		en_dev->hash_search_idx = 1;
+	}
+
+	return ret;
 }
 
 int32_t zxdh_phyport_get(struct zxdh_en_device *en_dev)
 {
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-
-    ret = get_common_table_msg(en_dev, en_dev->pcie_id, RISC_FIELD_PHYPORT_CHANNEL, &msg);
-    if(ret != 0)
-    {
-        LOG_ERR("get own phyport failed: %d\n", ret);
-        return ret;
-    }
-
-    en_dev->phy_port = msg.reps.cmn_recv_msg.value;
-    if (en_dev->phy_port == INVALID_PHY_PORT)
-    {
-        LOG_ERR("get phy_port failed\n");
-        return -EINVAL;
-    }
-    en_dev->ops->set_pf_phy_port(en_dev->parent, en_dev->phy_port);
-    LOG_DEBUG("phy_port: %u\n", en_dev->phy_port);
-
-    return ret;
+	int32_t ret = 0;
+	zxdh_reps_info reps = { 0 };
+
+	ret = get_common_table_msg(en_dev, en_dev->pcie_id,
+							   RISC_FIELD_PHYPORT_CHANNEL, &reps);
+	if (ret != 0) {
+		LOG_ERR("get own phyport failed: %d\n", ret);
+		return ret;
+	}
+
+	en_dev->phy_port = reps.cmn_recv_msg.value;
+	if (en_dev->phy_port == INVALID_PHY_PORT) {
+		LOG_ERR("get phy_port failed\n");
+		return -EINVAL;
+	}
+	en_dev->ops->set_pf_phy_port(en_dev->parent, en_dev->phy_port);
+	LOG_DEBUG("phy_port: %u\n", en_dev->phy_port);
+
+	return ret;
 }
 
 int32_t zxdh_panel_id_get(struct zxdh_en_device *en_dev)
 {
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-
-    ret = get_common_table_msg(en_dev, en_dev->pcie_id, RISC_FIELD_PANEL_ID, &msg);
-    if(ret != 0)
-    {
-        LOG_ERR("get own phyport failed: %d\n", ret);
-        return ret;
-    }
-
-    en_dev->panel_id = msg.reps.cmn_recv_msg.value;
-    if (en_dev->panel_id > MAX_PANEL_ID)
-    {
-        LOG_ERR("get panel_id failed, panel_id: %u\n", en_dev->panel_id);
-        return -EINVAL;
-    }
-    LOG_DEBUG("panel_id: %u\n", en_dev->panel_id);
-
-    return ret;
+	int32_t ret = 0;
+	zxdh_reps_info reps = { 0 };
+
+	ret = get_common_table_msg(en_dev, en_dev->pcie_id, RISC_FIELD_PANEL_ID,
+							   &reps);
+	if (ret != 0) {
+		LOG_ERR("get own phyport failed: %d\n", ret);
+		return ret;
+	}
+
+	en_dev->panel_id = reps.cmn_recv_msg.value;
+	if (en_dev->panel_id > MAX_PANEL_ID) {
+		LOG_ERR("get panel_id failed, panel_id: %u\n", en_dev->panel_id);
+		return -EINVAL;
+	}
+	LOG_DEBUG("panel_id: %u\n", en_dev->panel_id);
+
+	return ret;
 }
 
 int32_t zxdh_pf_macpcs_num_get(struct zxdh_en_device *en_dev)
 {
-    int32_t phy_port = 0;
-    int32_t mac_num = 0; //0-2
-
-    phy_port = en_dev->phy_port;
-
-    if (phy_port < 4)
-    {
-        mac_num = 0;
-    }
-    else if (phy_port < 8)
-    {
-        mac_num = 1;
-    }
-    else if (phy_port < 10)
-    {
-        mac_num = 2;
-    }
-    else
-    {
-        LOG_ERR("phy_port(%d) err, not in 0-9!!\n", phy_port);
-        mac_num = -1;
-        return mac_num;
-    }
-
-    LOG_DEBUG("mac_num: %d\n", mac_num);
-    return mac_num;
+	int32_t phy_port = 0;
+	int32_t mac_num = 0; // 0-2
+
+	phy_port = en_dev->phy_port;
+
+	if (phy_port < 4) {
+		mac_num = 0;
+	} else if (phy_port < 8) {
+		mac_num = 1;
+	} else if (phy_port < 10) {
+		mac_num = 2;
+	} else {
+		LOG_ERR("phy_port(%d) err, not in 0-9!!\n", phy_port);
+		mac_num = -1;
+		return mac_num;
+	}
+
+	LOG_DEBUG("mac_num: %d\n", mac_num);
+	return mac_num;
 }
 
 int32_t zxdh_pf_link_state_get(struct zxdh_en_device *en_dev)
 {
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_LINK_INFO_GET;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_pf_link_state_get failed: %d\n", ret);
-        return ret;
-    }
-    en_dev->ops->set_pf_link_up(en_dev->parent, msg.reps.mac_set_msg.link_state);
-    LOG_INFO("link_up is %s\n", msg.reps.mac_set_msg.link_state ? "true" : "false");
-    if(msg.reps.mac_set_msg.link_state)
-    {
-        netif_carrier_on(en_dev->netdev);
-    }
-    else
-    {
-        netif_carrier_off(en_dev->netdev);
-    }
-    return ret;
+	int32_t ret = 0;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+
+	msg.hdr_to_agt.op_code = AGENT_MAC_LINK_INFO_GET;
+	msg.hdr_to_agt.phyport = en_dev->phy_port;
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
+	if (ret != 0) {
+		LOG_ERR("zxdh_pf_link_state_get failed: %d\n", ret);
+		return ret;
+	}
+	en_dev->ops->set_pf_link_up(en_dev->parent, reps.mac_set_msg.link_state);
+	LOG_INFO("link_up is %s\n", reps.mac_set_msg.link_state ? "true" : "false");
+	if (reps.mac_set_msg.link_state) {
+		netif_carrier_on(en_dev->netdev);
+	} else {
+		netif_carrier_off(en_dev->netdev);
+	}
+	return ret;
 }
 
-int32_t zxdh_lldp_enable_set(struct zxdh_en_device *en_dev,bool lldp_enable)
+int32_t zxdh_lldp_enable_set(struct zxdh_en_device *en_dev, bool lldp_enable)
 {
-    union zxdh_msg msg = {0};
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
 
-    msg.payload.hdr_to_agt.op_code = AGENT_DEBUG_LLDP_ENABLE_SET;
-    msg.payload.hdr_to_agt.port_id = en_dev->panel_id;
+	msg.hdr_to_agt.op_code = AGENT_DEBUG_LLDP_ENABLE_SET;
+	msg.hdr_to_agt.port_id = en_dev->panel_id;
 
-    if (en_dev->ops->is_bond(en_dev->parent))
-    {
-        msg.payload.hdr_to_agt.port_id = en_dev->pannel_id;
-    }
-    msg.payload.lldp_msg.lldp_enable = lldp_enable;
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		msg.hdr_to_agt.port_id = en_dev->pannel_id;
+	}
+	msg.lldp_msg.lldp_enable = lldp_enable;
 
-    return zxdh_send_command_to_specify(en_dev, MODULE_DEBUG, &msg, &msg);
+	return zxdh_send_command_to_specify(en_dev, MODULE_DEBUG, &msg, &reps);
 }
 
 int32_t zxdh_sshd_enable_set(struct zxdh_en_device *en_dev, bool sshd_enable)
 {
-    union zxdh_msg msg = {0};
-
-    if (sshd_enable)
-    {
-        msg.payload.hdr_to_agt.op_code = AGENT_SSHD_START;
-    }
-    else
-    {
-        msg.payload.hdr_to_agt.op_code = AGENT_SSHD_STOP;
-    }
-
-    LOG_INFO("event id is %d\n", MODULE_LOGIN_CTRL);
-    return zxdh_send_command_to_specify(en_dev, MODULE_LOGIN_CTRL, &msg, &msg);
-}
-
-int32_t zxdh_lldp_enable_get(struct zxdh_en_device *en_dev, uint32_t *lldp_enable)
-{
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
 
-    msg.payload.hdr_to_agt.op_code = AGENT_DEBUG_LLDP_ENABLE_GET;
-    msg.payload.hdr_to_agt.port_id = en_dev->panel_id;
+	if (sshd_enable) {
+		msg.hdr_to_agt.op_code = AGENT_SSHD_START;
+	} else {
+		msg.hdr_to_agt.op_code = AGENT_SSHD_STOP;
+	}
 
-    if (en_dev->ops->is_bond(en_dev->parent))
-    {
-        msg.payload.hdr_to_agt.port_id = en_dev->pannel_id;
-    }
-
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_DEBUG, &msg, &msg);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_lldp_enable_get failed: %d\n", ret);
-        return ret;
-    }
-
-    *lldp_enable = (uint32_t)(msg.reps.debug_lldp_msg.lldp_status);
-
-    return ret;
+	LOG_INFO("event id is %d\n", MODULE_LOGIN_CTRL);
+	return zxdh_send_command_to_specify(en_dev, MODULE_LOGIN_CTRL, &msg, &reps);
 }
 
-int32_t zxdh_riscv_os_type_get(struct zxdh_en_device *en_dev, uint8_t *is_zios)
+int32_t zxdh_lldp_enable_get(struct zxdh_en_device *en_dev,
+							 uint32_t *lldp_enable)
 {
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-    msg.payload.hdr_to_agt.op_code = AGENT_OS_TYPE_GET;
+	int32_t ret = 0;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+
+	msg.hdr_to_agt.op_code = AGENT_DEBUG_LLDP_ENABLE_GET;
+	msg.hdr_to_agt.port_id = en_dev->panel_id;
 
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_LOGIN_CTRL, &msg, &msg);
-    if (ret != 0)
-    {
-        LOG_ERR("get bus from riscv failed: %d\n", ret);
-        return ret;
-    }
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		msg.hdr_to_agt.port_id = en_dev->pannel_id;
+	}
 
-    *is_zios = msg.reps.os_type_msg.is_zios;
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_DEBUG, &msg, &reps);
+	if (ret != 0) {
+		LOG_ERR("zxdh_lldp_enable_get failed: %d\n", ret);
+		return ret;
+	}
 
-    return ret;
+	*lldp_enable = (uint32_t)(reps.debug_lldp_msg.lldp_status);
+
+	return ret;
 }
 
 int32_t zxdh_ep0_bus_get(struct zxdh_en_device *en_dev, uint8_t *bus_info)
 {
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
+	int32_t ret = 0;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
 
-    msg.payload.hdr_to_agt.op_code = AGENT_EP0_BUS_GET;
+	msg.hdr_to_agt.op_code = AGENT_EP0_BUS_GET;
 
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_LOGIN_CTRL, &msg, &msg);
-    if (ret != 0)
-    {
-        LOG_ERR("get bus from riscv failed: %d\n", ret);
-        return ret;
-    }
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_LOGIN_CTRL, &msg, &reps);
+	if (ret != 0) {
+		LOG_ERR("get bus from riscv failed: %d\n", ret);
+		return ret;
+	}
 
-    *bus_info = msg.reps.ep0_bus_msg.bus_info;
+	*bus_info = reps.ep0_bus_msg.bus_info;
 
-    return ret;
+	return ret;
 }
 
 int8_t zxdh_debug_ip_get(struct zxdh_en_device *en_dev, int8_t *ip)
 {
-    int32_t ret = 0;
-    uint8_t bus_info = 0;
-    int8_t ip_address[20] = {0};
-    int8_t bus_str[5]= {0};
+	int32_t ret = 0;
+	uint8_t bus_info = 0;
+	int8_t ip_address[20] = { 0 };
+	int8_t bus_str[5] = { 0 };
 
-    sprintf(ip_address, "26.20.5");
+	sprintf(ip_address, "26.20.5");
 
-    ret = zxdh_ep0_bus_get(en_dev, &bus_info);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_ep0_bus_get failed: %d\n", ret);
-        return ret;
-    }
+	ret = zxdh_ep0_bus_get(en_dev, &bus_info);
+	if (ret != 0) {
+		LOG_ERR("zxdh_ep0_bus_get failed: %d\n", ret);
+		return ret;
+	}
 
-    sprintf(bus_str, ".%d", bus_info);
-    strcat(ip_address, bus_str); /* 将bus号添加到IP地址字符串后面 */
-    strcpy(ip, ip_address);
+	sprintf(bus_str, ".%d", bus_info);
+	strcat(ip_address, bus_str); /* 将bus号添加到IP地址字符串后面 */
+	strcpy(ip, ip_address);
 
-    LOG_INFO("DEBUG IP is: %s\n", ip_address);
+	LOG_INFO("DEBUG IP is: %s\n", ip_address);
 
-    return ret;
+	return ret;
 }
 
 #define FLASH_OPEN_FW
-int32_t zxdh_en_firmware_version_get(struct zxdh_en_device *en_dev, uint8_t *fw_version, uint8_t *fw_version_len)
+int32_t zxdh_en_firmware_version_get(struct zxdh_en_device *en_dev,
+									 uint8_t *fw_version,
+									 uint8_t *fw_version_len)
 {
 #ifdef FLASH_OPEN_FW
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
+	int32_t ret = 0;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
 
-    msg.payload.hdr_to_agt.op_code = AGENT_FLASH_FIR_VERSION_GET;
+	msg.hdr_to_agt.op_code = AGENT_FLASH_FIR_VERSION_GET;
 
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_FLASH, &msg, &msg);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_send_command_to_specify failed: %d\n", ret);
-        return ret;
-    }
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_FLASH, &msg, &reps);
+	if (ret != 0) {
+		LOG_ERR("zxdh_send_command_to_specify failed: %d\n", ret);
+		return ret;
+	}
 
-    memcpy(fw_version, msg.reps.flash_msg.firmware_version, FW_VERSION_LEN);
-    *fw_version_len = FW_VERSION_LEN;
+	memcpy(fw_version, reps.flash_msg.firmware_version, FW_VERSION_LEN);
+	*fw_version_len = FW_VERSION_LEN;
 #else
-    uint8_t fw_version_test[] = "V2.24.10.01B4";
+	uint8_t fw_version_test[] = "V2.24.10.01B4";
 
-    memcpy(fw_version, fw_version_test, sizeof(fw_version_test));
-    *fw_version_len = sizeof(fw_version_test);
+	memcpy(fw_version, fw_version_test, sizeof(fw_version_test));
+	*fw_version_len = sizeof(fw_version_test);
 #endif
-    return 0;
+	return 0;
 }
 
 int32_t do_get_vport_stats(struct zxdh_en_device *en_dev, uint8_t np_mode,
-                           struct zxdh_en_vport_stats *vport_stats)
+						   struct zxdh_en_vport_stats *vport_stats)
 {
-    union zxdh_msg msg = {0};
-    uint64_t rx_broadcast_cnt = 0;
-    uint64_t tx_broadcast_cnt = 0;
-    uint64_t rx_mtu_drop_pkts_cnt = 0;
-    uint64_t tx_mtu_drop_pkts_cnt = 0;
-    uint64_t rx_mtu_drop_bytes_cnt = 0;
-    uint64_t tx_mtu_drop_bytes_cnt = 0;
-    uint64_t rx_plcr_drop_pkts_cnt = 0;
-    uint64_t tx_plcr_drop_pkts_cnt = 0;
-    uint64_t rx_plcr_drop_bytes_cnt = 0;
-    uint64_t tx_plcr_drop_bytes_cnt = 0;
-    uint32_t vf_id = GET_VFID(en_dev->vport);
-    int32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    msg.payload.hdr_to_agt.op_code = AGENT_VQM_DEVICE_STATS_GET;
-    msg.payload.hdr_to_agt.vf_id = vf_id;
-    err = zxdh_send_command_to_specify(en_dev, MODULE_VQM, &msg, &msg);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_vport_stats_get failed, err: %d\n", err);
-        return err;
-    }
-    memcpy(&(vport_stats->vqm_stats), &(msg.reps.stats_msg), sizeof(vport_stats->vqm_stats));
-
-    memset(&msg, 0, sizeof(union zxdh_msg));
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-    {
-        msg.payload.hdr.op_code = ZXDH_GET_NP_STATS;
-        msg.payload.hdr.vport = en_dev->vport;
-        msg.payload.hdr.vf_id = vf_id;
-        msg.payload.np_stats_get_msg.clear_mode = np_mode;
-        err = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
-        if(err != 0)
-        {
-            LOG_ERR("zxdh_send_command_to_pf failed: %d\n", err);
-            return err;
-        }
-        rx_broadcast_cnt = msg.reps.np_stats_msg.np_rx_broadcast;
-        tx_broadcast_cnt = msg.reps.np_stats_msg.np_tx_broadcast;
-        rx_mtu_drop_pkts_cnt = msg.reps.np_stats_msg.np_rx_mtu_drop_pkts;
-        tx_mtu_drop_pkts_cnt = msg.reps.np_stats_msg.np_tx_mtu_drop_pkts;
-        rx_mtu_drop_bytes_cnt = msg.reps.np_stats_msg.np_rx_mtu_drop_bytes;
-        tx_mtu_drop_bytes_cnt = msg.reps.np_stats_msg.np_tx_mtu_drop_bytes;
-        rx_plcr_drop_pkts_cnt = msg.reps.np_stats_msg.np_rx_plcr_drop_pkts;
-        tx_plcr_drop_pkts_cnt = msg.reps.np_stats_msg.np_tx_plcr_drop_pkts;
-        rx_plcr_drop_bytes_cnt = msg.reps.np_stats_msg.np_rx_plcr_drop_bytes;
-        tx_plcr_drop_bytes_cnt = msg.reps.np_stats_msg.np_tx_plcr_drop_bytes;
-    }
-    else
-    {
-        dpp_stat_port_bc_packet_rx_cnt_get(&pf_info, vf_id, np_mode, &rx_broadcast_cnt);
-        dpp_stat_port_bc_packet_tx_cnt_get(&pf_info, vf_id, np_mode, &tx_broadcast_cnt);
-        dpp_stat_MTU_packet_msg_rx_cnt_get(&pf_info, vf_id, np_mode, &rx_mtu_drop_bytes_cnt, &rx_mtu_drop_pkts_cnt);
-        dpp_stat_MTU_packet_msg_tx_cnt_get(&pf_info, vf_id, np_mode, &tx_mtu_drop_bytes_cnt, &tx_mtu_drop_pkts_cnt);
-        dpp_stat_plcr_packet_drop_rx_cnt_get(&pf_info, vf_id, np_mode, &rx_plcr_drop_bytes_cnt, &rx_plcr_drop_pkts_cnt);
-        dpp_stat_plcr_packet_drop_tx_cnt_get(&pf_info, vf_id, np_mode, &tx_plcr_drop_bytes_cnt, &tx_plcr_drop_pkts_cnt);
-    }
-    vport_stats->np_stats.rx_vport_broadcast_packets = rx_broadcast_cnt;
-    vport_stats->np_stats.tx_vport_broadcast_packets = tx_broadcast_cnt;
-    vport_stats->np_stats.rx_vport_mtu_drop_packets = rx_mtu_drop_pkts_cnt;
-    vport_stats->np_stats.tx_vport_mtu_drop_packets = tx_mtu_drop_pkts_cnt;
-    vport_stats->np_stats.rx_vport_mtu_drop_bytes = rx_mtu_drop_bytes_cnt;
-    vport_stats->np_stats.tx_vport_mtu_drop_bytes = tx_mtu_drop_bytes_cnt;
-    vport_stats->np_stats.rx_vport_plcr_drop_packets = rx_plcr_drop_pkts_cnt;
-    vport_stats->np_stats.tx_vport_plcr_drop_packets = tx_plcr_drop_pkts_cnt;
-    vport_stats->np_stats.rx_vport_plcr_drop_bytes = rx_plcr_drop_bytes_cnt;
-    vport_stats->np_stats.tx_vport_plcr_drop_bytes = tx_plcr_drop_bytes_cnt;
-
-    return err;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	uint64_t rx_broadcast_cnt = 0;
+	uint64_t tx_broadcast_cnt = 0;
+	uint64_t rx_mtu_drop_pkts_cnt = 0;
+	uint64_t tx_mtu_drop_pkts_cnt = 0;
+	uint64_t rx_mtu_drop_bytes_cnt = 0;
+	uint64_t tx_mtu_drop_bytes_cnt = 0;
+	uint64_t rx_plcr_drop_pkts_cnt = 0;
+	uint64_t tx_plcr_drop_pkts_cnt = 0;
+	uint64_t rx_plcr_drop_bytes_cnt = 0;
+	uint64_t tx_plcr_drop_bytes_cnt = 0;
+	uint32_t vf_id = GET_VFID(en_dev->vport);
+	int32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	msg.hdr_to_agt.op_code = AGENT_VQM_DEVICE_STATS_GET;
+	msg.hdr_to_agt.vf_id = vf_id;
+	err = zxdh_send_command_to_specify(en_dev, MODULE_VQM, &msg, &reps);
+	if (err != 0) {
+		LOG_ERR("zxdh_vport_stats_get failed, err: %d\n", err);
+		return err;
+	}
+	memcpy(&(vport_stats->vqm_stats), &(reps.stats_msg),
+		   sizeof(vport_stats->vqm_stats));
+
+	memset(&msg, 0, sizeof(zxdh_msg_info));
+	memset(&reps, 0, sizeof(zxdh_reps_info));
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		msg.hdr.op_code = ZXDH_GET_NP_STATS;
+		msg.hdr.vport = en_dev->vport;
+		msg.hdr.vf_id = vf_id;
+		msg.np_stats_get_msg.clear_mode = np_mode;
+		err = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF,
+										   &msg, &reps);
+		if (err != 0) {
+			LOG_ERR("zxdh_send_command_to_pf failed: %d\n", err);
+			return err;
+		}
+		rx_broadcast_cnt = reps.np_stats_msg.np_rx_broadcast;
+		tx_broadcast_cnt = reps.np_stats_msg.np_tx_broadcast;
+		rx_mtu_drop_pkts_cnt = reps.np_stats_msg.np_rx_mtu_drop_pkts;
+		tx_mtu_drop_pkts_cnt = reps.np_stats_msg.np_tx_mtu_drop_pkts;
+		rx_mtu_drop_bytes_cnt = reps.np_stats_msg.np_rx_mtu_drop_bytes;
+		tx_mtu_drop_bytes_cnt = reps.np_stats_msg.np_tx_mtu_drop_bytes;
+		rx_plcr_drop_pkts_cnt = reps.np_stats_msg.np_rx_plcr_drop_pkts;
+		tx_plcr_drop_pkts_cnt = reps.np_stats_msg.np_tx_plcr_drop_pkts;
+		rx_plcr_drop_bytes_cnt = reps.np_stats_msg.np_rx_plcr_drop_bytes;
+		tx_plcr_drop_bytes_cnt = reps.np_stats_msg.np_tx_plcr_drop_bytes;
+	} else {
+		dpp_stat_port_bc_packet_rx_cnt_get(&pf_info, vf_id, np_mode,
+										   &rx_broadcast_cnt);
+		dpp_stat_port_bc_packet_tx_cnt_get(&pf_info, vf_id, np_mode,
+										   &tx_broadcast_cnt);
+		dpp_stat_MTU_packet_msg_rx_cnt_get(&pf_info, vf_id, np_mode,
+										   &rx_mtu_drop_bytes_cnt,
+										   &rx_mtu_drop_pkts_cnt);
+		dpp_stat_MTU_packet_msg_tx_cnt_get(&pf_info, vf_id, np_mode,
+										   &tx_mtu_drop_bytes_cnt,
+										   &tx_mtu_drop_pkts_cnt);
+		dpp_stat_plcr_packet_drop_rx_cnt_get(&pf_info, vf_id, np_mode,
+											 &rx_plcr_drop_bytes_cnt,
+											 &rx_plcr_drop_pkts_cnt);
+		dpp_stat_plcr_packet_drop_tx_cnt_get(&pf_info, vf_id, np_mode,
+											 &tx_plcr_drop_bytes_cnt,
+											 &tx_plcr_drop_pkts_cnt);
+	}
+	vport_stats->np_stats.rx_vport_broadcast_packets = rx_broadcast_cnt;
+	vport_stats->np_stats.tx_vport_broadcast_packets = tx_broadcast_cnt;
+	vport_stats->np_stats.rx_vport_mtu_drop_packets = rx_mtu_drop_pkts_cnt;
+	vport_stats->np_stats.tx_vport_mtu_drop_packets = tx_mtu_drop_pkts_cnt;
+	vport_stats->np_stats.rx_vport_mtu_drop_bytes = rx_mtu_drop_bytes_cnt;
+	vport_stats->np_stats.tx_vport_mtu_drop_bytes = tx_mtu_drop_bytes_cnt;
+	vport_stats->np_stats.rx_vport_plcr_drop_packets = rx_plcr_drop_pkts_cnt;
+	vport_stats->np_stats.tx_vport_plcr_drop_packets = tx_plcr_drop_pkts_cnt;
+	vport_stats->np_stats.rx_vport_plcr_drop_bytes = rx_plcr_drop_bytes_cnt;
+	vport_stats->np_stats.tx_vport_plcr_drop_bytes = tx_plcr_drop_bytes_cnt;
+
+	return err;
 }
 
 int32_t zxdh_en_vport_pre_stats_get(struct zxdh_en_device *en_dev)
 {
-    int32_t err = 0;
-    struct zxdh_en_vport_stats *vport_stats = &en_dev->pre_stats;
-
-    err = do_get_vport_stats(en_dev, NP_GET_PKT_CNT, vport_stats);
-    if(err != 0)
-    {
-        LOG_ERR("zxdh_en_vport_pre_stat_get failed\n");
-    }
-    return err;
+	int32_t err = 0;
+	struct zxdh_en_vport_stats *vport_stats = &en_dev->pre_stats;
+
+	err = do_get_vport_stats(en_dev, NP_GET_PKT_CNT, vport_stats);
+	if (err != 0) {
+		LOG_ERR("zxdh_en_vport_pre_stat_get failed\n");
+	}
+	return err;
 }
 
 int32_t zxdh_vport_stats_get(struct zxdh_en_device *en_dev)
 {
-    int32_t err = 0;
-    struct zxdh_en_vport_stats *vport_stats = &en_dev->hw_stats.vport_stats;
-
-    err = do_get_vport_stats(en_dev, NP_GET_PKT_CNT, vport_stats);
-    if(err != 0)
-    {
-        LOG_ERR("zxdh_vport_stats_get failed\n");
-        return err;
-    }
-
-    vport_stats->vqm_stats.rx_vport_packets -= en_dev->pre_stats.vqm_stats.rx_vport_packets;
-    vport_stats->vqm_stats.tx_vport_packets -= en_dev->pre_stats.vqm_stats.tx_vport_packets;
-    vport_stats->vqm_stats.rx_vport_bytes -= en_dev->pre_stats.vqm_stats.rx_vport_bytes;
-    vport_stats->vqm_stats.tx_vport_bytes -= en_dev->pre_stats.vqm_stats.tx_vport_bytes;
-    vport_stats->vqm_stats.rx_vport_dropped -= en_dev->pre_stats.vqm_stats.rx_vport_dropped;
-    vport_stats->np_stats.rx_vport_broadcast_packets -= en_dev->pre_stats.np_stats.rx_vport_broadcast_packets;
-    vport_stats->np_stats.tx_vport_broadcast_packets -= en_dev->pre_stats.np_stats.tx_vport_broadcast_packets;
-    vport_stats->np_stats.rx_vport_mtu_drop_packets -= en_dev->pre_stats.np_stats.rx_vport_mtu_drop_packets;
-    vport_stats->np_stats.tx_vport_mtu_drop_packets -= en_dev->pre_stats.np_stats.tx_vport_mtu_drop_packets;
-    vport_stats->np_stats.rx_vport_mtu_drop_bytes -= en_dev->pre_stats.np_stats.rx_vport_mtu_drop_bytes;
-    vport_stats->np_stats.tx_vport_mtu_drop_bytes -= en_dev->pre_stats.np_stats.tx_vport_mtu_drop_bytes;
-    vport_stats->np_stats.rx_vport_plcr_drop_packets -= en_dev->pre_stats.np_stats.rx_vport_plcr_drop_packets;
-    vport_stats->np_stats.tx_vport_plcr_drop_packets -= en_dev->pre_stats.np_stats.tx_vport_plcr_drop_packets;
-    vport_stats->np_stats.rx_vport_plcr_drop_bytes -= en_dev->pre_stats.np_stats.rx_vport_plcr_drop_bytes;
-    vport_stats->np_stats.tx_vport_plcr_drop_bytes -= en_dev->pre_stats.np_stats.tx_vport_plcr_drop_bytes;
-    return err;
+	int32_t err = 0;
+	struct zxdh_en_vport_stats *vport_stats = &en_dev->hw_stats.vport_stats;
+
+	err = do_get_vport_stats(en_dev, NP_GET_PKT_CNT, vport_stats);
+	if (err != 0) {
+		LOG_ERR("zxdh_vport_stats_get failed\n");
+		return err;
+	}
+
+	vport_stats->vqm_stats.rx_vport_packets -=
+			en_dev->pre_stats.vqm_stats.rx_vport_packets;
+	vport_stats->vqm_stats.tx_vport_packets -=
+			en_dev->pre_stats.vqm_stats.tx_vport_packets;
+	vport_stats->vqm_stats.rx_vport_bytes -=
+			en_dev->pre_stats.vqm_stats.rx_vport_bytes;
+	vport_stats->vqm_stats.tx_vport_bytes -=
+			en_dev->pre_stats.vqm_stats.tx_vport_bytes;
+	vport_stats->vqm_stats.rx_vport_dropped -=
+			en_dev->pre_stats.vqm_stats.rx_vport_dropped;
+	vport_stats->np_stats.rx_vport_broadcast_packets -=
+			en_dev->pre_stats.np_stats.rx_vport_broadcast_packets;
+	vport_stats->np_stats.tx_vport_broadcast_packets -=
+			en_dev->pre_stats.np_stats.tx_vport_broadcast_packets;
+	vport_stats->np_stats.rx_vport_mtu_drop_packets -=
+			en_dev->pre_stats.np_stats.rx_vport_mtu_drop_packets;
+	vport_stats->np_stats.tx_vport_mtu_drop_packets -=
+			en_dev->pre_stats.np_stats.tx_vport_mtu_drop_packets;
+	vport_stats->np_stats.rx_vport_mtu_drop_bytes -=
+			en_dev->pre_stats.np_stats.rx_vport_mtu_drop_bytes;
+	vport_stats->np_stats.tx_vport_mtu_drop_bytes -=
+			en_dev->pre_stats.np_stats.tx_vport_mtu_drop_bytes;
+	vport_stats->np_stats.rx_vport_plcr_drop_packets -=
+			en_dev->pre_stats.np_stats.rx_vport_plcr_drop_packets;
+	vport_stats->np_stats.tx_vport_plcr_drop_packets -=
+			en_dev->pre_stats.np_stats.tx_vport_plcr_drop_packets;
+	vport_stats->np_stats.rx_vport_plcr_drop_bytes -=
+			en_dev->pre_stats.np_stats.rx_vport_plcr_drop_bytes;
+	vport_stats->np_stats.tx_vport_plcr_drop_bytes -=
+			en_dev->pre_stats.np_stats.tx_vport_plcr_drop_bytes;
+	return err;
 }
 
 int32_t zxdh_mac_stats_get(struct zxdh_en_device *en_dev)
 {
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_STATS_GET;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;
-    err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_mac_stats_get failed, err: %d\n", err);
-        return err;
-    }
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-    {
-        memset(&msg.reps.stats_msg, 0, sizeof(msg.reps.stats_msg));
-    }
-    memcpy(&(en_dev->hw_stats.phy_stats), &msg.reps.stats_msg, sizeof(en_dev->hw_stats.phy_stats));
-
-    return err;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	int32_t err = 0;
+
+	msg.hdr_to_agt.op_code = AGENT_MAC_STATS_GET;
+	msg.hdr_to_agt.phyport = en_dev->phy_port;
+	err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
+	if (err != 0) {
+		LOG_ERR("zxdh_mac_stats_get failed, err: %d\n", err);
+		return err;
+	}
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		memset(&reps.stats_msg, 0, sizeof(reps.stats_msg));
+	}
+	memcpy(&(en_dev->hw_stats.phy_stats), &reps.stats_msg,
+		   sizeof(en_dev->hw_stats.phy_stats));
+
+#if STATS_CLEAR_AFTER_READ
+	msg.hdr_to_agt.op_code = AGENT_MAC_STATS_CLEAR;
+	zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
+#endif
+
+	return err;
 }
 
 int32_t zxdh_mac_stats_clear(struct zxdh_en_device *en_dev)
 {
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_STATS_CLEAR;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;
-    err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_mac_stats_clear failed, err: %d\n", err);
-        return err;
-    }
-
-    return err;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	int32_t err = 0;
+
+	msg.hdr_to_agt.op_code = AGENT_MAC_STATS_CLEAR;
+	msg.hdr_to_agt.phyport = en_dev->phy_port;
+	err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
+	if (err != 0) {
+		LOG_ERR("zxdh_mac_stats_clear failed, err: %d\n", err);
+		return err;
+	}
+
+	return err;
 }
 
 int32_t zxdh_en_phyport_init(struct zxdh_en_device *en_dev)
 {
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-    struct link_info_struct link_info_val = {0};
-
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_PHYPORT_INIT;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;
-    if (en_dev->ops->is_upf(en_dev->parent))
-    {
-        msg.payload.hdr_to_agt.phyport = 0;
-        msg.payload.hdr_to_agt.is_upf = 1;
-        //TODO 确定upf设备link状态获取方案
-        en_dev->link_up = true;
-        en_dev->speed = SPEED_100000;
-        en_dev->ops->set_pf_link_up(en_dev->parent, en_dev->link_up);
-        netif_carrier_on(en_dev->netdev);
-    }
-
-    err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_send_command_to_riscv_mac failed, err: %d\n", err);
-        return err;
-    }
-
-    en_dev->supported_speed_modes = msg.reps.mac_set_msg.speed_modes;
-    en_dev->advertising_speed_modes = msg.reps.mac_set_msg.speed_modes;
-
-    link_info_val.speed = en_dev->speed;
-    link_info_val.autoneg_enable = en_dev->autoneg_enable;
-    link_info_val.supported_speed_modes = en_dev->supported_speed_modes;
-    link_info_val.advertising_speed_modes = en_dev->advertising_speed_modes;
-    link_info_val.duplex = en_dev->duplex;
-    en_dev->ops->update_pf_link_info(en_dev->parent, &link_info_val);
-
-    return err;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	int32_t err = 0;
+	struct link_info_struct link_info_val = { 0 };
+
+	msg.hdr_to_agt.op_code = AGENT_MAC_PHYPORT_INIT;
+	msg.hdr_to_agt.phyport = en_dev->phy_port;
+
+	err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
+	if (err != 0) {
+		LOG_ERR("zxdh_send_command_to_riscv_mac failed, err: %d\n", err);
+		return err;
+	}
+
+	en_dev->supported_speed_modes = reps.mac_set_msg.speed_modes;
+	en_dev->advertising_speed_modes = reps.mac_set_msg.speed_modes;
+
+	link_info_val.speed = en_dev->speed;
+	link_info_val.autoneg_enable = en_dev->autoneg_enable;
+	link_info_val.supported_speed_modes = en_dev->supported_speed_modes;
+	link_info_val.advertising_speed_modes = en_dev->advertising_speed_modes;
+	link_info_val.duplex = en_dev->duplex;
+	en_dev->ops->update_pf_link_info(en_dev->parent, &link_info_val);
+
+	return err;
 }
 
-int32_t zxdh_en_autoneg_set(struct zxdh_en_device *en_dev, uint8_t enable, uint32_t speed_modes)
+int32_t zxdh_en_autoneg_set(struct zxdh_en_device *en_dev, uint8_t enable,
+							uint32_t speed_modes)
 {
-    union zxdh_msg msg = {0};
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
 
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_AUTONEG_SET;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;
-    msg.payload.mac_set_msg.autoneg = enable;
-    msg.payload.mac_set_msg.speed_modes = speed_modes;
+	msg.hdr_to_agt.op_code = AGENT_MAC_AUTONEG_SET;
+	msg.hdr_to_agt.phyport = en_dev->phy_port;
+	msg.mac_set_msg.autoneg = enable;
+	msg.mac_set_msg.speed_modes = speed_modes;
 
-    return zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
+	return zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
 }
 
 int32_t zxdh_en_fec_mode_set(struct zxdh_en_device *en_dev, uint32_t fec_cfg)
 {
-    union zxdh_msg msg = {0};
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
 
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_FEC_MODE_SET;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;
-    msg.payload.mac_fec_mode_msg.fec_cfg = fec_cfg;
+	msg.hdr_to_agt.op_code = AGENT_MAC_FEC_MODE_SET;
+	msg.hdr_to_agt.phyport = en_dev->phy_port;
+	msg.mac_fec_mode_msg.fec_cfg = fec_cfg;
 
-    return zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
+	return zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
 }
 
-int32_t zxdh_en_fec_mode_get(struct zxdh_en_device *en_dev, uint32_t *fec_cap, uint32_t *fec_cfg, uint32_t *fec_active)
+int32_t zxdh_en_fec_mode_get(struct zxdh_en_device *en_dev, uint32_t *fec_cap,
+							 uint32_t *fec_cfg, uint32_t *fec_active)
 {
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_FEC_MODE_GET;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;
-
-    err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_send_command_to_riscv_mac failed, err: %d\n", err);
-        return err;
-    }
-
-    if(fec_cap)
-        *fec_cap = msg.reps.mac_fec_mode_msg.fec_cap;
-    if(fec_cfg)
-        *fec_cfg = msg.reps.mac_fec_mode_msg.fec_cfg;
-    if(fec_active)
-        *fec_active = msg.reps.mac_fec_mode_msg.fec_link;
-
-    return err;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	int32_t err = 0;
+
+	msg.hdr_to_agt.op_code = AGENT_MAC_FEC_MODE_GET;
+	msg.hdr_to_agt.phyport = en_dev->phy_port;
+
+	err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
+	if (err != 0) {
+		LOG_ERR("zxdh_send_command_to_riscv_mac failed, err: %d\n", err);
+		return err;
+	}
+
+	if (fec_cap)
+		*fec_cap = reps.mac_fec_mode_msg.fec_cap;
+	if (fec_cfg)
+		*fec_cfg = reps.mac_fec_mode_msg.fec_cfg;
+	if (fec_active)
+		*fec_active = reps.mac_fec_mode_msg.fec_link;
+
+	return err;
 }
 
 int32_t zxdh_en_fc_mode_set(struct zxdh_en_device *en_dev, uint32_t fc_mode)
 {
-    union zxdh_msg msg = {0};
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
 
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_FC_MODE_SET;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;
-    msg.payload.mac_fc_mode_msg.fc_mode = fc_mode;
+	msg.hdr_to_agt.op_code = AGENT_MAC_FC_MODE_SET;
+	msg.hdr_to_agt.phyport = en_dev->phy_port;
+	msg.mac_fc_mode_msg.fc_mode = fc_mode;
 
-    return zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
+	return zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
 }
 
 int32_t zxdh_en_fc_mode_get(struct zxdh_en_device *en_dev, uint32_t *fc_mode)
 {
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	int32_t err = 0;
 
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_FC_MODE_GET;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;
+	msg.hdr_to_agt.op_code = AGENT_MAC_FC_MODE_GET;
+	msg.hdr_to_agt.phyport = en_dev->phy_port;
 
-    err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_send_command_to_riscv_mac failed, err: %d\n", err);
-        return err;
-    }
+	err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
+	if (err != 0) {
+		LOG_ERR("zxdh_send_command_to_riscv_mac failed, err: %d\n", err);
+		return err;
+	}
 
-    if(fc_mode)
-        *fc_mode = msg.reps.mac_fc_mode_msg.fc_mode;
+	if (fc_mode)
+		*fc_mode = reps.mac_fc_mode_msg.fc_mode;
 
-    return err;
+	return err;
 }
 
-uint32_t zxdh_en_module_eeprom_read(struct zxdh_en_device *en_dev, struct zxdh_en_module_eeprom_param *query, uint8_t *data)
+uint32_t zxdh_en_module_eeprom_read(struct zxdh_en_device *en_dev,
+									struct zxdh_en_module_eeprom_param *query,
+									uint8_t *data)
 {
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_MODULE_EEPROM_READ;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;
-    msg.payload.module_eeprom_msg.i2c_addr = query->i2c_addr;
-    msg.payload.module_eeprom_msg.bank = query->bank;
-    msg.payload.module_eeprom_msg.page = query->page;
-    msg.payload.module_eeprom_msg.offset = query->offset;
-    msg.payload.module_eeprom_msg.length = query->length;
-
-    err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_send_command_to_riscv_mac failed, err: %d\n", err);
-        return 0;
-    }
-
-    if(data)
-        memcpy(data, msg.reps.module_eeprom_msg.data, msg.reps.module_eeprom_msg.length);
-
-    return msg.reps.module_eeprom_msg.length;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	int32_t err = 0;
+
+	msg.hdr_to_agt.op_code = AGENT_MAC_MODULE_EEPROM_READ;
+	msg.hdr_to_agt.phyport = en_dev->phy_port;
+	msg.module_eeprom_msg.i2c_addr = query->i2c_addr;
+	msg.module_eeprom_msg.bank = query->bank;
+	msg.module_eeprom_msg.page = query->page;
+	msg.module_eeprom_msg.offset = query->offset;
+	msg.module_eeprom_msg.length = query->length;
+
+	err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
+	if (err != 0) {
+		LOG_ERR("zxdh_send_command_to_riscv_mac failed, err: %d\n", err);
+		return 0;
+	}
+
+	if (data)
+		memcpy(data, reps.module_eeprom_msg.data,
+			   reps.module_eeprom_msg.length);
+
+	return reps.module_eeprom_msg.length;
 }
 
 int32_t zxdh_vf_1588_call_np_interface(struct zxdh_en_device *en_dev)
 {
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-
-    msg.payload.hdr.op_code = ZXDH_VF_1588_CALL_NP;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.hdr.pcie_id = en_dev->pcie_id;
-    msg.payload.vf_1588_call_np.vfid = VQM_VFID(msg.payload.hdr.vport);
-    msg.payload.vf_1588_call_np.call_np_interface_num = en_dev->vf_1588_call_np_num;
-    msg.payload.vf_1588_call_np.ptp_tc_enable_opt = en_dev->ptp_tc_enable_opt;
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
-    if(ret != 0)
-    {
-        LOG_ERR("zxdh_send_command_to_pf failed: %d\n", ret);
-        return ret;
-    }
-
-    return ret;
+	int32_t ret = 0;
+	zxdh_msg_info msg;
+	zxdh_reps_info ack;
+
+	msg.hdr.op_code = ZXDH_VF_1588_CALL_NP;
+	msg.hdr.vport = en_dev->vport;
+	msg.hdr.pcie_id = en_dev->pcie_id;
+	msg.vf_1588_call_np.vfid = VQM_VFID(msg.hdr.vport);
+	msg.vf_1588_call_np.call_np_interface_num = en_dev->vf_1588_call_np_num;
+	msg.vf_1588_call_np.ptp_tc_enable_opt = en_dev->ptp_tc_enable_opt;
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+									   &ack);
+	if (ret != 0) {
+		LOG_ERR("zxdh_send_command_to_pf failed: %d\n", ret);
+		return ret;
+	}
+
+	return ret;
 }
 
 int32_t zxdh_vf_port_create(struct zxdh_en_device *en_dev)
 {
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-    uint8_t link_up = 0;
-    bool is_upf = false;
-
-    if (en_dev->ops->is_upf(en_dev->parent))
-    {
-        is_upf = true;
-    }
-
-    msg.payload.hdr.op_code = ZXDH_VF_PORT_INIT;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.hdr.pcie_id = en_dev->pcie_id;
-    msg.payload.vf_init_msg.base_qid = en_dev->phy_index[0];
-    msg.payload.vf_init_msg.hash_search_idx = en_dev->hash_search_idx;
-    msg.payload.vf_init_msg.rss_enable = 1;
-    msg.payload.vf_init_msg.is_upf = is_upf;
-
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
-    if(ret != 0)
-    {
-        LOG_ERR("zxdh_send_command_to_pf failed: %d\n", ret);
-        return ret;
-    }
-
-    if (is_upf)
-    {
-        en_dev->link_up = msg.reps.vf_init_msg.link_up;
-    }
-    else
-    {
-        en_dev->ops->get_link_info_from_vqm(en_dev->parent, &link_up);
-        en_dev->link_up = link_up;
-        LOG_INFO("vf read link_up: %d from vqm\n", link_up);
-    }
-
-    ether_addr_copy(en_dev->netdev->dev_addr, msg.reps.vf_init_msg.mac_addr);
-    en_dev->speed = msg.reps.vf_init_msg.speed;
-    en_dev->autoneg_enable = msg.reps.vf_init_msg.autoneg_enable;
-    en_dev->supported_speed_modes = msg.reps.vf_init_msg.sup_link_modes;
-    en_dev->advertising_speed_modes = msg.reps.vf_init_msg.adv_link_modes;
-    en_dev->duplex = msg.reps.vf_init_msg.duplex;
-
-    if (!is_upf)
-    {
-        en_dev->phy_port = msg.reps.vf_init_msg.phy_port;
-        en_dev->ops->set_pf_phy_port(en_dev->parent, en_dev->phy_port);
-    }
-
-    if (en_dev->link_up)
-    {
-        en_dev->ops->set_pf_link_up(en_dev->parent, TRUE);
-        netif_carrier_on(en_dev->netdev);
-    }
-    else
-    {
-        en_dev->ops->set_pf_link_up(en_dev->parent, FALSE);
-        netif_carrier_off(en_dev->netdev);
-    }
-    return ret;
+	int32_t ret = 0;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack = { 0 };
+	uint8_t link_up = 0;
+
+	// dpp_np_init
+	msg.hdr.op_code = ZXDH_VF_PORT_INIT;
+	msg.hdr.vport = en_dev->vport;
+	msg.hdr.pcie_id = en_dev->pcie_id;
+	msg.vf_init_msg.base_qid = en_dev->phy_index[0];
+	msg.vf_init_msg.hash_search_idx = en_dev->hash_search_idx;
+	msg.vf_init_msg.rss_enable = 1;
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+									   &ack);
+	if (ret != 0) {
+		LOG_ERR("zxdh_send_command_to_pf failed: %d\n", ret);
+		return ret;
+	}
+	en_dev->ops->get_link_info_from_vqm(en_dev->parent, &link_up);
+
+	LOG_INFO("vf read link_up: %d from vqm\n", link_up);
+	en_dev->link_up = link_up;
+	ether_addr_copy(en_dev->netdev->dev_addr, ack.vf_init_msg.mac_addr);
+	en_dev->speed = ack.vf_init_msg.speed;
+	en_dev->autoneg_enable = ack.vf_init_msg.autoneg_enable;
+	en_dev->supported_speed_modes = ack.vf_init_msg.sup_link_modes;
+	en_dev->advertising_speed_modes = ack.vf_init_msg.adv_link_modes;
+	en_dev->duplex = ack.vf_init_msg.duplex;
+	en_dev->phy_port = ack.vf_init_msg.phy_port;
+
+	en_dev->ops->set_pf_phy_port(en_dev->parent, en_dev->phy_port);
+
+	if (link_up == 0) {
+		en_dev->ops->set_pf_link_up(en_dev->parent, FALSE);
+		netif_carrier_off(en_dev->netdev);
+	} else {
+		en_dev->ops->set_pf_link_up(en_dev->parent, TRUE);
+		netif_carrier_on(en_dev->netdev);
+	}
+	return ret;
 }
 
 int32_t zxdh_vf_port_delete(struct zxdh_en_device *en_dev)
 {
-    union zxdh_msg msg = {0};
-
-    //dpp_np_uninit
-    msg.payload.hdr.op_code = ZXDH_VF_PORT_UNINIT;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.hdr.pcie_id = en_dev->pcie_id;
-    return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
+	zxdh_msg_info msg;
+	zxdh_reps_info ack;
+
+	// dpp_np_uninit
+	msg.hdr.op_code = ZXDH_VF_PORT_UNINIT;
+	msg.hdr.vport = en_dev->vport;
+	msg.hdr.pcie_id = en_dev->pcie_id;
+	return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+										&ack);
 }
 
-int32_t zxdh_vf_dpp_add_mac(struct zxdh_en_device *en_dev, const uint8_t *dev_addr, uint8_t filter_flag)
+int32_t zxdh_vf_dpp_add_mac(struct zxdh_en_device *en_dev,
+							const uint8_t *dev_addr, uint8_t filter_flag)
 {
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-
-    msg.payload.hdr.op_code = ZXDH_MAC_ADD;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.hdr.pcie_id = en_dev->pcie_id;
-    msg.payload.mac_addr_set_msg.filter_flag = filter_flag;
-    memcpy(msg.payload.mac_addr_set_msg.mac_addr, dev_addr, en_dev->netdev->addr_len);
-
-    err = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
-    if (err != 0)
-    {
-        if (msg.reps.flag == ZXDH_REPS_BEOND_MAC)
-        {
-            return DPP_RC_TABLE_RANGE_INVALID;
-        }
-    }
-    return err;
-}
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack = { 0 };
 
-int32_t zxdh_vf_dpp_del_mac(struct zxdh_en_device *en_dev, const uint8_t *dev_addr, uint8_t filter_flag, bool mac_flag)
-{
-    union zxdh_msg msg = {0};
+	msg.hdr.op_code = ZXDH_MAC_ADD;
+	msg.hdr.vport = en_dev->vport;
+	msg.hdr.pcie_id = en_dev->pcie_id;
+	msg.mac_addr_set_msg.filter_flag = filter_flag;
+	memcpy(msg.mac_addr_set_msg.mac_addr, dev_addr, en_dev->netdev->addr_len);
 
-    msg.payload.hdr.op_code = ZXDH_MAC_DEL;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.hdr.pcie_id = en_dev->pcie_id;
-    msg.payload.mac_addr_set_msg.filter_flag = filter_flag;
-    msg.payload.mac_addr_set_msg.mac_flag = mac_flag;
-    memcpy(msg.payload.mac_addr_set_msg.mac_addr, dev_addr, en_dev->netdev->addr_len);
+	return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+										&ack);
+}
 
-    return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
+int32_t zxdh_vf_dpp_del_mac(struct zxdh_en_device *en_dev,
+							const uint8_t *dev_addr, uint8_t filter_flag,
+							bool mac_flag)
+{
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack = { 0 };
+
+	msg.hdr.op_code = ZXDH_MAC_DEL;
+	msg.hdr.vport = en_dev->vport;
+	msg.hdr.pcie_id = en_dev->pcie_id;
+	msg.mac_addr_set_msg.filter_flag = filter_flag;
+	msg.mac_addr_set_msg.mac_flag = mac_flag;
+	memcpy(msg.mac_addr_set_msg.mac_addr, dev_addr, en_dev->netdev->addr_len);
+
+	return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+										&ack);
 }
 
 int32_t zxdh_vf_rss_en_set(struct zxdh_en_device *en_dev, uint32_t enable)
 {
-    union zxdh_msg msg = {0};
-
-    msg.payload.hdr.op_code = ZXDH_RSS_EN_SET;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.hdr.pcie_id = en_dev->pcie_id;
-    msg.payload.rss_enable_msg.rss_enable = enable;
-    return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack = { 0 };
+
+	msg.hdr.op_code = ZXDH_RSS_EN_SET;
+	msg.hdr.vport = en_dev->vport;
+	msg.hdr.pcie_id = en_dev->pcie_id;
+	msg.rss_enable_msg.rss_enable = enable;
+	return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+										&ack);
 }
 
-int32_t zxdh_vf_dpp_add_ipv6_mac(struct zxdh_en_device *en_dev, const uint8_t *mac_addr)
+int32_t zxdh_vf_dpp_add_ipv6_mac(struct zxdh_en_device *en_dev,
+								 const uint8_t *dev_addr)
 {
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-
-    msg.payload.hdr.op_code = ZXDH_IPV6_MAC_ADD;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.hdr.pcie_id = en_dev->pcie_id;
-    memcpy(msg.payload.mac_addr_set_msg.mac_addr, mac_addr, en_dev->netdev->addr_len);
-    err = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
-    if ((err != 0) && (msg.reps.flag == ZXDH_REPS_BEOND_MAC))
-    {
-        LOG_ERR("Add Multicast MAC Address(%pM) Failed, Beyond Max MAC Num 32\n", mac_addr);
-        return DPP_RC_TABLE_RANGE_INVALID;
-    }
-    return err;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack = { 0 };
+	msg.hdr.op_code = ZXDH_IPV6_MAC_ADD;
+	msg.hdr.vport = en_dev->vport;
+	msg.hdr.pcie_id = en_dev->pcie_id;
+	memcpy(msg.ipv6_mac_addr_msg.mac_addr, dev_addr, en_dev->netdev->addr_len);
+
+	return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+										&ack);
 }
 
-int32_t zxdh_vf_dpp_del_ipv6_mac(struct zxdh_en_device *en_dev, const uint8_t *mac_addr)
+int32_t zxdh_vf_dpp_del_ipv6_mac(struct zxdh_en_device *en_dev,
+								 const uint8_t *dev_addr)
 {
-    union zxdh_msg msg = {0};
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack = { 0 };
 
-    msg.payload.hdr.op_code = ZXDH_IPV6_MAC_DEL;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.hdr.pcie_id = en_dev->pcie_id;
-    memcpy(msg.payload.mac_addr_set_msg.mac_addr, mac_addr, en_dev->netdev->addr_len);
+	msg.hdr.op_code = ZXDH_IPV6_MAC_DEL;
+	msg.hdr.vport = en_dev->vport;
+	msg.hdr.pcie_id = en_dev->pcie_id;
+	memcpy(msg.ipv6_mac_addr_msg.mac_addr, dev_addr, en_dev->netdev->addr_len);
 
-    return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
+	return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+										&ack);
 }
 
-int32_t zxdh_vf_egr_port_attr_set(struct zxdh_en_device *en_dev, uint32_t mode, uint32_t value, uint8_t fow)
+int32_t zxdh_vf_egr_port_attr_set(struct zxdh_en_device *en_dev, uint32_t mode,
+								  uint32_t value, uint8_t fow)
 {
-    union zxdh_msg msg = {0};
-
-    msg.payload.hdr.op_code = ZXDH_PORT_ATTRS_SET;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.hdr.pcie_id = en_dev->pcie_id;
-    msg.payload.port_attr_set_msg.mode = mode;
-    msg.payload.port_attr_set_msg.value = value;
-    msg.payload.port_attr_set_msg.allmulti_follow = fow;
-    return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack = { 0 };
+
+	msg.hdr.op_code = ZXDH_PORT_ATTRS_SET;
+	msg.hdr.vport = en_dev->vport;
+	msg.hdr.pcie_id = en_dev->pcie_id;
+	msg.port_attr_set_msg.mode = mode;
+	msg.port_attr_set_msg.value = value;
+	msg.port_attr_set_msg.allmulti_follow = fow;
+	return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+										&ack);
 }
 
-int32_t zxdh_vf_egr_port_attr_get(struct zxdh_en_device *en_dev, ZXDH_VPORT_T *port_attr_entry)
+int32_t zxdh_vf_egr_port_attr_get(struct zxdh_en_device *en_dev,
+								  ZXDH_VPORT_T *port_attr_entry)
 {
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-
-    msg.payload.hdr.op_code = ZXDH_PORT_ATTRS_GET;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.hdr.pcie_id = en_dev->pcie_id;
-    err = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
-    if (err != 0)
-    {
-        LOG_ERR("vf_egr_port_attr_get failed, err = %d\n", err);
-        return err;
-    }
-
-    memcpy(port_attr_entry, &msg.reps.port_attr_get_msg.port_attr_entry, sizeof(ZXDH_VPORT_T));
-    return err;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack = { 0 };
+	int32_t err = 0;
+
+	msg.hdr.op_code = ZXDH_PORT_ATTRS_GET;
+	msg.hdr.vport = en_dev->vport;
+	msg.hdr.pcie_id = en_dev->pcie_id;
+	err = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+									   &ack);
+	if (err != 0) {
+		LOG_ERR("vf_egr_port_attr_get failed, err = %d\n", err);
+		return err;
+	}
+
+	memcpy(port_attr_entry, &ack.port_attr_get_msg.port_attr_entry,
+		   sizeof(ZXDH_VPORT_T));
+	return err;
 }
 
-int32_t zxdh_vf_port_promisc_set(struct zxdh_en_device *en_dev, uint8_t mode, uint8_t value, uint8_t fow)
+int32_t zxdh_vf_port_promisc_set(struct zxdh_en_device *en_dev, uint8_t mode,
+								 uint8_t value, uint8_t fow)
 {
-    union zxdh_msg msg = {0};
-
-    msg.payload.hdr.op_code = ZXDH_PROMISC_SET;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.hdr.pcie_id = en_dev->pcie_id;
-    msg.payload.promisc_set_msg.mode = mode;
-    msg.payload.promisc_set_msg.value = value;
-    msg.payload.promisc_set_msg.mc_follow = fow;
-    return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
+	zxdh_msg_info msg;
+	zxdh_reps_info ack;
+
+	msg.hdr.op_code = ZXDH_PROMISC_SET;
+	msg.hdr.vport = en_dev->vport;
+	msg.hdr.pcie_id = en_dev->pcie_id;
+	msg.promisc_set_msg.mode = mode;
+	msg.promisc_set_msg.value = value;
+	msg.promisc_set_msg.mc_follow = fow;
+	return zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+										&ack);
 }
 
 int32_t zxdh_en_vport_create(struct zxdh_en_device *en_dev)
 {
-    DPP_PF_INFO_T pf_info = {0};
+	DPP_PF_INFO_T pf_info = { 0 };
 
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-    if (!en_dev->ops->if_init(en_dev->parent))
-    {
-        return 0;
-    }
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+	if (!en_dev->ops->if_init(en_dev->parent)) {
+		return 0;
+	}
 
-    return dpp_vport_create(&pf_info);
+	return dpp_vport_create(&pf_info);
 }
 
 int32_t zxdh_en_vport_delete(struct zxdh_en_device *en_dev)
 {
-    DPP_PF_INFO_T pf_info = {0};
+	DPP_PF_INFO_T pf_info = { 0 };
 
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-    if (!en_dev->ops->if_init(en_dev->parent))
-    {
-        return 0;
-    }
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+	if (!en_dev->ops->if_init(en_dev->parent)) {
+		return 0;
+	}
 
-    return dpp_vport_delete(&pf_info);
+	return dpp_vport_delete(&pf_info);
 }
 
 int32_t zxdh_pf_vport_create(struct zxdh_en_device *en_dev)
 {
-    int32_t ret = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    ret = zxdh_en_vport_create(en_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_en_vport_create failed: %d\n", ret);
-        return ret;
-    }
-
-    ret = dpp_vport_bond_pf(&pf_info);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_vport_bond_pf failed: %d\n", ret);
-        goto err_vport;
-    }
-
-    if (en_dev->ops->is_upf(en_dev->parent))
-    {
-        ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_LAG_ID, 0);
-        if (ret != 0)
-        {
-            LOG_ERR("dpp_egr_port_attr_set lag_id 0 failed: %d\n", ret);
-            goto err_vport;
-        }
-
-        ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_LAG_EN_OFF, 1);
-        if (ret != 0)
-        {
-            LOG_ERR("dpp_egr_port_attr_set bond_en 1 failed: %d\n", ret);
-            goto err_vport;
-        }
-    }
-    else
-    {
-        ret = dpp_panel_bond_vport(&pf_info, en_dev->phy_port);
-        if (ret != 0)
-        {
-            LOG_ERR("dpp_panel_bond_vport failed: %d\n", ret);
-            goto err_vport;
-        }
-    }
-
-    return ret;
+	int32_t ret = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	ret = zxdh_en_vport_create(en_dev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_en_vport_create failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = dpp_vport_bond_pf(&pf_info);
+	if (ret != 0) {
+		LOG_ERR("dpp_vport_bond_pf failed: %d\n", ret);
+		goto err_vport;
+	}
+
+	ret = dpp_panel_bond_vport(&pf_info, en_dev->phy_port);
+	if (ret != 0) {
+		LOG_ERR("dpp_panel_bond_vport failed: %d\n", ret);
+		goto err_vport;
+	}
+
+	return ret;
 
 err_vport:
-    zxdh_en_vport_delete(en_dev);
-    return ret;
+	zxdh_en_vport_delete(en_dev);
+	return ret;
 }
 
 int32_t zxdh_rxfh_set(struct zxdh_en_device *en_dev, uint32_t *queue_map)
 {
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (queue_map == NULL)
-    {
-        return -1;
-    }
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        err = dpp_rxfh_set(&pf_info, queue_map, ZXDH_INDIR_RQT_SIZE);
-        if (err != 0)
-        {
-            LOG_ERR("dpp_rxfh_set failed: %d\n", err);
-        }
-    }
-    else
-    {
-        msg.payload.hdr.op_code = ZXDH_RXFH_SET;
-        msg.payload.hdr.vport = en_dev->vport;
-        msg.payload.hdr.pcie_id = en_dev->pcie_id;
-        memcpy(msg.payload.rxfh_set_msg.queue_map, queue_map, ZXDH_INDIR_RQT_SIZE * sizeof(uint32_t));
-        err = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true);
-        if(err != 0)
-        {
-            LOG_ERR("zxdh_send_command_to_pf_np failed: %d\n", err);
-        }
-    }
-
-    return err;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack = { 0 };
+	int32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if (queue_map == NULL) {
+		return -1;
+	}
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		err = dpp_rxfh_set(&pf_info, queue_map, ZXDH_INDIR_RQT_SIZE);
+		if (err != 0) {
+			LOG_ERR("dpp_rxfh_set failed: %d\n", err);
+		}
+	} else {
+		msg.hdr.op_code = ZXDH_RXFH_SET;
+		msg.hdr.vport = en_dev->vport;
+		msg.hdr.pcie_id = en_dev->pcie_id;
+		memcpy(msg.rxfh_set_msg.queue_map, queue_map,
+			   ZXDH_INDIR_RQT_SIZE * sizeof(uint32_t));
+		err = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF,
+										&msg, &ack, true);
+		if (err != 0) {
+			LOG_ERR("zxdh_send_command_to_pf_np failed: %d\n", err);
+		}
+	}
+
+	return err;
 }
 
 void zxdh_rxfh_del(struct zxdh_en_device *en_dev)
 {
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (en_dev->ops->is_bond(en_dev->parent))
-    {
-        return;
-    }
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        dpp_rxfh_del(&pf_info);
-    }
-    else
-    {
-        msg.payload.hdr.op_code = ZXDH_RXFH_DEL;
-        msg.payload.hdr.vport = en_dev->vport;
-        msg.payload.hdr.pcie_id = en_dev->pcie_id;
-        err = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true);
-        if(err != 0)
-        {
-            LOG_ERR("zxdh_send_command_to_pf_np failed: %d\n", err);
-        }
-    }
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack = { 0 };
+	int32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		return;
+	}
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		dpp_rxfh_del(&pf_info);
+	} else {
+		msg.hdr.op_code = ZXDH_RXFH_DEL;
+		msg.hdr.vport = en_dev->vport;
+		msg.hdr.pcie_id = en_dev->pcie_id;
+		err = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF,
+										&msg, &ack, true);
+		if (err != 0) {
+			LOG_ERR("zxdh_send_command_to_pf_np failed: %d\n", err);
+		}
+	}
 }
 
 int32_t zxdh_ethtool_init(struct zxdh_en_device *en_dev)
 {
-    int32_t ret = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    ret = dpp_vport_rss_en_set(&pf_info, 1);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_vport_rss_en_set failed: %d\n", ret);
-        return ret;
-    }
-
-    ret = dpp_vport_hash_funcs_set(&pf_info, en_dev->hash_func);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_vport_hash_funcs_set failed: %d\n", ret);
-        return ret;
-    }
-
-    ret = dpp_rx_flow_hash_set(&pf_info, ZXDH_NET_RX_FLOW_HASH_SDFNT);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_rx_flow_hash_set failed: %d\n", ret);
-        return ret;
-    }
-
-    ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_PORT_BASE_QID, (uint16_t)en_dev->phy_index[0]);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set %d failed: %d\n", en_dev->phy_index[0], ret);
-        return ret;
-    }
-
-    ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IPV4_TCP_ASSEMBLE, 1);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set tcp assemble failed: %d\n", ret);
-        return ret;
-    }
-
-    ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IPV6_TCP_ASSEMBLE, 1);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set tcp assemble failed: %d\n", ret);
-        return ret;
-    }
-
-    ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IP_CHKSUM, 1);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set rx ip checksum failed: %d\n", ret);
-        return ret;
-    }
-
-    ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_TCP_UDP_CHKSUM, 1);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set rx l4 checksum failed: %d\n", ret);
-        return ret;
-    }
-
-    ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 1);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set accelerator offload failed: %d\n", ret);
-        return ret;
-    }
-
-    ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD, 1);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set vxlan outer ip checksum failed: %d\n", ret);
-        return ret;
-    }
-
-    ret = dpp_vport_vlan_filter_en_set(&pf_info, 0);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_vport_vlan_filter_en_set failed: %d\n", ret);
-        return ret;
-    }
-
-    ret = dpp_vlan_filter_init(&pf_info);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_vlan_filter_init failed: %d\n", ret);
-        return ret;
-    }
-
-    return ret;
+	int32_t ret = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	ret = dpp_vport_rss_en_set(&pf_info, 1);
+	if (ret != 0) {
+		LOG_ERR("dpp_vport_rss_en_set failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = dpp_vport_hash_funcs_set(&pf_info, en_dev->hash_func);
+	if (ret != 0) {
+		LOG_ERR("dpp_vport_hash_funcs_set failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = dpp_rx_flow_hash_set(&pf_info, ZXDH_NET_RX_FLOW_HASH_SDFNT);
+	if (ret != 0) {
+		LOG_ERR("zxdh_rx_flow_hash_set failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_PORT_BASE_QID,
+								(uint16_t)en_dev->phy_index[0]);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set %d failed: %d\n", en_dev->phy_index[0],
+				ret);
+		return ret;
+	}
+
+	ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IPV4_TCP_ASSEMBLE, 1);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set tcp assemble failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IPV6_TCP_ASSEMBLE, 1);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set tcp assemble failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_IP_CHKSUM, 1);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set rx ip checksum failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_TCP_UDP_CHKSUM, 1);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set rx l4 checksum failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 1);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set accelerator offload failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD,
+								1);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set vxlan outer ip checksum failed: %d\n",
+				ret);
+		return ret;
+	}
+
+	ret = dpp_vport_vlan_filter_en_set(&pf_info, 0);
+	if (ret != 0) {
+		LOG_ERR("dpp_vport_vlan_filter_en_set failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = dpp_vlan_filter_init(&pf_info);
+	if (ret != 0) {
+		LOG_ERR("dpp_vlan_filter_init failed: %d\n", ret);
+		return ret;
+	}
+
+	return ret;
 }
 
 int32_t zxdh_pf_flush_mac(struct zxdh_en_device *en_dev)
 {
-    int32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    /* 删除此转发域所有单播mac地址 */
-    err = dpp_unicast_all_mac_delete(&pf_info);
-    if (err != 0)
-    {
-        LOG_ERR("dpp_unicast_all_mac_delete failed\n");
-        return err;
-    }
-    LOG_INFO("dpp_unicast_all_mac_delete succeed\n");
-
-    /* 删除此转发域中所有组播mac地址 */
-    err = dpp_multicast_all_mac_delete(&pf_info);
-    if (err != 0)
-    {
-        LOG_ERR("dpp_multicast_all_mac_delete failed\n");
-        return err;
-    }
-    LOG_INFO("dpp_multicast_all_mac_delete succeed\n");
-
-    return err;
+	int32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	/* 删除此转发域所有单播mac地址 */
+	err = dpp_unicast_all_mac_delete(&pf_info);
+	if (err != 0) {
+		LOG_ERR("dpp_unicast_all_mac_delete failed\n");
+		return err;
+	}
+	LOG_INFO("dpp_unicast_all_mac_delete succeed\n");
+
+	/* 删除此转发域中所有组播mac地址 */
+	err = dpp_multicast_all_mac_delete(&pf_info);
+	if (err != 0) {
+		LOG_ERR("dpp_multicast_all_mac_delete failed\n");
+		return err;
+	}
+	LOG_INFO("dpp_multicast_all_mac_delete succeed\n");
+
+	return err;
 }
 
 int32_t zxdh_pf_flush_mac_online(struct zxdh_en_device *en_dev)
 {
-    int32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    /* 删除此转发域所有单播mac地址 */
-    err = dpp_unicast_all_mac_online_delete(&pf_info);
-    if (err != 0)
-    {
-        LOG_ERR("dpp_unicast_all_mac_online_delete failed:%d\n", err);
-        return err;
-    }
-
-    /* 删除此转发域中所有组播mac地址 */
-    err = dpp_multicast_all_mac_online_delete(&pf_info);
-    if (err != 0)
-    {
-        LOG_ERR("dpp_multicast_all_mac_online_delete failed:%d\n", err);
-        return err;
-    }
-
-    return err;
+	int32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	/* 删除此转发域所有单播mac地址 */
+	err = dpp_unicast_all_mac_online_delete(&pf_info);
+	if (err != 0) {
+		LOG_ERR("dpp_unicast_all_mac_online_delete failed:%d\n", err);
+		return err;
+	}
+
+	/* 删除此转发域中所有组播mac地址 */
+	err = dpp_multicast_all_mac_online_delete(&pf_info);
+	if (err != 0) {
+		LOG_ERR("dpp_multicast_all_mac_online_delete failed:%d\n", err);
+		return err;
+	}
+
+	return err;
 }
 
 int32_t zxdh_pf_port_delete(struct net_device *netdev)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t ret = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    if (en_dev == NULL)
-    {
-        return -1;
-    }
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-    dpp_vport_uc_promisc_set(&pf_info, 0);
-    dpp_vport_mc_promisc_set(&pf_info, 0);
-
-    /* pf删除所有配置到np的mac地址 */
-    if (!en_dev->ops->is_bond(en_dev->parent))
-    {
-        ret = zxdh_pf_flush_mac_online(en_dev);
-        if (ret != 0)
-        {
-            LOG_ERR("zxdh_pf_flush_mac_online failed: %d\n", ret);
-            return ret;
-        }
-    }
-
-    ret = zxdh_en_vport_delete(en_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_vport_delete failed: %d\n", ret);
-        return ret;
-    }
-
-    return ret;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t ret = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	if (en_dev == NULL) {
+		return -1;
+	}
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+	dpp_vport_uc_promisc_set(&pf_info, 0);
+	dpp_vport_mc_promisc_set(&pf_info, 0);
+
+	/* pf删除所有配置到np的mac地址 */
+	if (!en_dev->ops->is_bond(en_dev->parent)) {
+		ret = zxdh_pf_flush_mac_online(en_dev);
+		if (ret != 0) {
+			LOG_ERR("zxdh_pf_flush_mac_online failed: %d\n", ret);
+			return ret;
+		}
+	}
+
+	ret = zxdh_en_vport_delete(en_dev);
+	if (ret != 0) {
+		LOG_ERR("dpp_vport_delete failed: %d\n", ret);
+		return ret;
+	}
+
+	return ret;
 }
 
 int32_t zxdh_aux_alloc_pannel(struct zxdh_en_device *en_dev)
 {
-    int32_t ret = 0;
-    struct zxdh_pannle_port port;
+	int32_t ret = 0;
+	struct zxdh_pannle_port port;
 
-    ret = en_dev->ops->request_port(en_dev->parent, &port);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_aux_alloc_pannel failed \n");
-        goto out;
-    }
+	ret = en_dev->ops->request_port(en_dev->parent, &port);
+	if (ret != 0) {
+		LOG_ERR("zxdh_aux_alloc_pannel failed \n");
+		goto out;
+	}
 
-    en_dev->phy_port = port.phyport;
-    en_dev->pannel_id = port.pannel_id;
-    en_dev->link_check_bit = port.link_check_bit;
+	en_dev->phy_port = port.phyport;
+	en_dev->pannel_id = port.pannel_id;
+	en_dev->link_check_bit = port.link_check_bit;
 
-    LOG_INFO("bond pf: pannel %u, phyport %u check bit %u \n",
-        en_dev->pannel_id, en_dev->phy_port, en_dev->link_check_bit);
+	LOG_INFO("zxdh_aux_alloc_pannel pannel %u, phyport %u check bit %u \n",
+			 en_dev->pannel_id, en_dev->phy_port, en_dev->link_check_bit);
 
 out:
-    return ret;
+	return ret;
 }
 
-#if 0
-int32_t zxdh_aux_query_phyport(struct zxdh_en_device *en_dev)
-{
-    int32_t ret = 0;
-    struct aux_phyport_message recv = {0};
-    struct aux_phyport_message *recv_data = &recv;
-    zxdh_aux_phyport_msg msg = {0};
-    zxdh_aux_phyport_msg *payload = &msg;
-
-    payload->pcie_id = en_dev->pcie_id;
-    payload->pannel_id = en_dev->pannel_id;
-    payload->rsv = en_dev->pannel_id;
-
-    ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_PHYPORT_QUERY, payload, recv_data, true);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_aux_query_phyport send message failed \n");
-        goto out;
-    }
-
-    en_dev->phy_port = recv_data->phyport;
-
-out:
-    return ret;
-}
-#endif
 int32_t zxdh_pf_port_init(struct net_device *netdev)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    bool vepa = false;
-    int32_t ret = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    if (en_dev == NULL)
-    {
-        return -1;
-    }
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-#if 0
-    en_dev->ops->dpp_np_init(en_dev->parent, en_dev->vport);
-#endif
-
-    ret = zxdh_pf_vport_create(en_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_pf_vport_create failed: %d\n", ret);
-        return ret;
-    }
-
-    zxdh_mac_stats_clear(en_dev);
-
-    if (en_dev->ops->is_bond(en_dev->parent))
-    {
-        if (!en_dev->ops->if_init(en_dev->parent))
-        {
-            LOG_INFO("First net-device is init\n");
-            return 0;
-        }
-
-        /* 只将第一个网络设备的队列配置到vport属性表中 */
-        ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_PORT_BASE_QID, (uint16_t)en_dev->phy_index[0]);
-        if (ret != 0)
-        {
-            LOG_ERR("dpp_egr_port_attr_set %d failed: %d\n", en_dev->phy_index[0], ret);
-            goto err_vport;
-        }
-        return 0;
-    }
-
-    vepa = en_dev->ops->get_vepa(en_dev->parent);
-    ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VEPA_EN_OFF, (uint32_t)vepa);
-    if (ret != 0)
-    {
-        LOG_ERR("Failed to setup vport(0x%x) %s mode, ret: %d\n", en_dev->vport, vepa?"vepa":"veb", ret);
-        goto err_vport;
-    }
-    LOG_INFO("Initialize vport(0x%x) to %s mode\n", en_dev->vport, vepa?"vepa":"veb");
-
-    ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_HASH_SEARCH_INDEX, en_dev->hash_search_idx);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set hash_search_index %u failed: %d\n", en_dev->hash_search_idx, ret);
-        goto err_vport;
-    }
-
-    ret = zxdh_ethtool_init(en_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_ethtool_init failed: %d\n", ret);
-         return ret;
-    }
-
-    /* PF删除复位前配置到np的mac */
-    ret = zxdh_pf_flush_mac(en_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_pf_flush_mac failed: %d\n", ret);
-        goto err_vport;
-    }
-
-    ret = dpp_add_mac(&pf_info, netdev->dev_addr);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_add_mac failed: %d\n", ret);
-        goto err_vport;
-    }
-
-    dpp_vport_uc_promisc_set(&pf_info, 0);
-    dpp_vport_mc_promisc_set(&pf_info, 0);
-
-    return 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	bool vepa = false;
+	int32_t ret = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	if (en_dev == NULL) {
+		return -1;
+	}
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	en_dev->hash_func = ZXDH_FUNC_TOP;
+
+	ret = zxdh_pf_vport_create(en_dev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_pf_vport_create failed: %d\n", ret);
+		return ret;
+	}
+
+	zxdh_mac_stats_clear(en_dev);
+
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		if (!en_dev->ops->if_init(en_dev->parent)) {
+			LOG_INFO("First net-device is init\n");
+			return 0;
+		}
+
+		/* 只将第一个网络设备的队列配置到vport属性表中 */
+		ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_PORT_BASE_QID,
+									(uint16_t)en_dev->phy_index[0]);
+		if (ret != 0) {
+			LOG_ERR("dpp_egr_port_attr_set %d failed: %d\n",
+					en_dev->phy_index[0], ret);
+			goto err_vport;
+		}
+		return 0;
+	}
+
+	vepa = en_dev->ops->get_vepa(en_dev->parent);
+	ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VEPA_EN_OFF, (uint32_t)vepa);
+	if (ret != 0) {
+		LOG_ERR("Failed to setup vport(0x%x) %s mode, ret: %d\n", en_dev->vport,
+				vepa ? "vepa" : "veb", ret);
+		goto err_vport;
+	}
+	LOG_INFO("Initialize vport(0x%x) to %s mode\n", en_dev->vport,
+			 vepa ? "vepa" : "veb");
+
+	ret = dpp_egr_port_attr_set(&pf_info, EGR_FLAG_HASH_SEARCH_INDEX,
+								en_dev->hash_search_idx);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set hash_search_index %u failed: %d\n",
+				en_dev->hash_search_idx, ret);
+		goto err_vport;
+	}
+
+	ret = zxdh_ethtool_init(en_dev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_ethtool_init failed: %d\n", ret);
+		return ret;
+	}
+
+	/* PF删除复位前配置到np的mac */
+	ret = zxdh_pf_flush_mac(en_dev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_pf_flush_mac failed: %d\n", ret);
+		goto err_vport;
+	}
+
+	ret = dpp_add_mac(&pf_info, netdev->dev_addr);
+	if (ret != 0) {
+		LOG_ERR("dpp_add_mac failed: %d\n", ret);
+		goto err_vport;
+	}
+
+	dpp_vport_uc_promisc_set(&pf_info, 0);
+	dpp_vport_mc_promisc_set(&pf_info, 0);
+
+	return 0;
 
 err_vport:
-    zxdh_en_vport_delete(en_dev);
-    return ret;
+	zxdh_en_vport_delete(en_dev);
+	return ret;
 }
 
 int32_t zxdh_vf_get_mac(struct net_device *netdev)
 {
-    struct zxdh_en_priv *en_priv  = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct netdev_hw_addr *ha = NULL;
-    union zxdh_msg msg = {0};
-    uint8_t mac[6] = {0};
-    int32_t ret    = 0;
-    bool add_flag  = true;
-
-    msg.payload.hdr.op_code = ZXDH_MAC_GET;
-    msg.payload.hdr.vport = en_dev->vport;
-    msg.payload.hdr.pcie_id = en_dev->pcie_id;
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_send_command_to_pf failed: %d\n", ret);
-        return ret;
-    }
-
-    ether_addr_copy(mac, msg.reps.vf_mac_addr_get_msg.mac_addr);
-    LOG_INFO("zxdh_vf_get_mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-    if (is_zero_ether_addr(mac))
-    {
-        get_random_bytes(mac, 6);
-        mac[0] &= 0xfe;
-        LOG_INFO("vf set random mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-    }
-
-    list_for_each_entry(ha, &netdev->uc.list, list)
-    {
-        if (!memcmp(ha->addr, mac, netdev->addr_len))
-        {
-            add_flag = false;
-        }
-    }
-
-    if (add_flag)
-    {
-        ret = zxdh_vf_dpp_add_mac(en_dev, mac, UNFILTER_MAC);
-        if (ret != 0)
-        {
-            LOG_ERR("zxdh_vf_dpp_add_mac failed: %d\n", ret);
-            goto free_vport;
-        }
-    }
-
-    ether_addr_copy(netdev->dev_addr, mac);
-
-    return ret;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct netdev_hw_addr *ha = NULL;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack = { 0 };
+	uint8_t mac[6] = { 0 };
+	int32_t ret = 0;
+	bool add_flag = true;
+
+	msg.hdr.op_code = ZXDH_MAC_GET;
+	msg.hdr.vport = en_dev->vport;
+	msg.hdr.pcie_id = en_dev->pcie_id;
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg,
+									   &ack);
+	if (ret != 0) {
+		LOG_ERR("zxdh_send_command_to_pf failed: %d\n", ret);
+		return ret;
+	}
+
+	ether_addr_copy(mac, ack.vf_mac_addr_get_msg.mac_addr);
+	LOG_INFO("zxdh_vf_get_mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0], mac[1],
+			 mac[2], mac[3], mac[4], mac[5]);
+	if (is_zero_ether_addr(mac)) {
+		get_random_bytes(mac, 6);
+		mac[0] &= 0xfe;
+		LOG_INFO("vf set random mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0],
+				 mac[1], mac[2], mac[3], mac[4], mac[5]);
+	}
+
+	list_for_each_entry(ha, &netdev->uc.list, list) {
+		if (!memcmp(ha->addr, mac, netdev->addr_len)) {
+			add_flag = false;
+		}
+	}
+
+	if (add_flag) {
+		ret = zxdh_vf_dpp_add_mac(en_dev, mac, UNFILTER_MAC);
+		if (ret != 0) {
+			LOG_ERR("zxdh_vf_dpp_add_mac failed: %d\n", ret);
+			goto free_vport;
+		}
+	}
+
+	ether_addr_copy(netdev->dev_addr, mac);
+
+	return ret;
 free_vport:
-    zxdh_vf_port_delete(en_dev);
-    return ret;
+	zxdh_vf_port_delete(en_dev);
+	return ret;
 }
 
 int32_t zxdh_vf_dpp_port_init(struct net_device *netdev)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t ret = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t ret = 0;
 
-    ret = zxdh_vf_port_create(en_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_vf_port_create failed: %d\n", ret);
-    }
+	ret = zxdh_vf_port_create(en_dev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_vf_port_create failed: %d\n", ret);
+	}
 
-    return ret;
+	return ret;
 }
 
 void zxdh_vport_uninit(struct net_device *netdev)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t ret = 0;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        ret = zxdh_pf_port_delete(netdev);
-        if (ret != 0)
-        {
-            LOG_ERR("zxdh_pf_port_delete failed: %d\n", ret);
-        }
-    }
-    else
-    {
-        ret = zxdh_vf_port_delete(en_dev);
-        if (ret != 0)
-        {
-            LOG_ERR("zxdh_vf_port_delete failed: %d\n", ret);
-        }
-    }
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t ret = 0;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		ret = zxdh_pf_port_delete(netdev);
+		if (ret != 0) {
+			LOG_ERR("zxdh_pf_port_delete failed: %d\n", ret);
+		}
+	} else {
+		ret = zxdh_vf_port_delete(en_dev);
+		if (ret != 0) {
+			LOG_ERR("zxdh_vf_port_delete failed: %d\n", ret);
+		}
+	}
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/en_cmd.h b/src/net/drivers/net/ethernet/dinghai/en_aux/en_cmd.h
index 578b8dcc1267e6d56e6ac61a7f247145db1cbaec..4a48ad99e4362096db913f1b9ed03ccdf4f7bbc9 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/en_cmd.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/en_cmd.h
@@ -4,223 +4,217 @@
 #include <linux/ethtool.h>
 #include "../msg_common.h"
 
-#define ZXDH_QRES_TBL_LEN              (300)
-#define ZXDH_QS_PAIRS                   (2)
+#define ZXDH_QRES_TBL_LEN (300)
+#define ZXDH_QS_PAIRS (2)
 
-#define INVALID_PHY_PORT                    0xff
-#define ZXDH_MAX_HASH_INDEX                 6//TODO:should is 5
+#define STATS_CLEAR_AFTER_READ 0
+
+#define INVALID_PHY_PORT 0xff
+#define ZXDH_MAX_HASH_INDEX 6 // TODO:should is 5
 
 /* HASH_FUNC TYPE */
-#define ZXDH_FUNC_TOP                       0x04
-#define ZXDH_FUNC_XOR                       0x02
-#define ZXDH_FUNC_CRC32                     0x01
+#define ZXDH_FUNC_TOP 0x04
+#define ZXDH_FUNC_XOR 0x02
+#define ZXDH_FUNC_CRC32 0x01
 
 /* RX_NFC */
-#define ZXDH_NET_RX_FLOW_HASH_MV            4
-#define ZXDH_NET_RX_FLOW_HASH_SDT           2
-#define ZXDH_NET_RX_FLOW_HASH_SDFNT         1
+#define ZXDH_NET_RX_FLOW_HASH_MV 4
+#define ZXDH_NET_RX_FLOW_HASH_SDT 2
+#define ZXDH_NET_RX_FLOW_HASH_SDFNT 1
 
 /* RISCV OPCODE */
-#define RISC_TYPE_READ                  0
-#define RISC_FIELD_PANEL_ID             5
-#define RISC_FIELD_PHYPORT_CHANNEL      6
-#define RISC_FIELD_HASHID_CHANNEL       10
-#define RISC_SERVER_TIME                0xF0
-
-
-#define MAX_PANEL_ID                    8//TODO:should is 5
-
-enum riscv_op_code
-{
-    OP_CODE_WRITE     = 1,
-    OP_CODE_MSGQ_CHAN = 2,
-    OP_CODE_DATA_CHAN = 3,
-    OP_CODE_MAX,
+#define RISC_TYPE_READ 0
+#define RISC_FIELD_PANEL_ID 5
+#define RISC_FIELD_PHYPORT_CHANNEL 6
+#define RISC_FIELD_HASHID_CHANNEL 10
+#define RISC_SERVER_TIME 0xF0
+
+#define MAX_PANEL_ID 8 // TODO:should is 5
+
+enum riscv_op_code {
+	OP_CODE_WRITE = 1,
+	OP_CODE_MSGQ_CHAN = 2,
+	OP_CODE_DATA_CHAN = 3,
+	OP_CODE_MAX,
 };
 
-#define OP_CODE_TBL_STAT                (0xaa)
-#define MSG_STRUCT_HD_LEN               8
-
-struct queue_index_message
-{
-    uint8_t  type;
-    uint8_t  field;
-    uint16_t ep_bdf;
-    uint16_t write_bytes;
-    uint16_t rsv;
-    uint16_t write_data[0];
+#define OP_CODE_TBL_STAT (0xaa)
+#define MSG_STRUCT_HD_LEN 8
+
+struct queue_index_message {
+	uint8_t type;
+	uint8_t field;
+	uint16_t ep_bdf;
+	uint16_t write_bytes;
+	uint16_t rsv;
+	uint16_t write_data[0];
 } __attribute__((packed));
 
-struct cmd_hdr_recv
-{
-    uint8_t  check;
-    uint8_t  rsv;
-    uint16_t data_len_bytes;
+struct cmd_hdr_recv {
+	uint8_t check;
+	uint8_t rsv;
+	uint16_t data_len_bytes;
 };
 
-struct cmd_tbl_ack
-{
-    struct cmd_hdr_recv hdr;
-    uint8_t  phy_port;
-    uint8_t  rsv[3];
+struct cmd_tbl_ack {
+	struct cmd_hdr_recv hdr;
+	uint8_t phy_port;
+	uint8_t rsv[3];
 } __attribute__((packed));
 
-enum zxdh_msg_chan_opc
-{
-    ZXDH_VPORT_GET               = 4,
-    ZXDH_PHYPORT_GET             = 6,
+enum zxdh_msg_chan_opc {
+	ZXDH_VPORT_GET = 4,
+	ZXDH_PHYPORT_GET = 6,
 };
 
-struct zxdh_debug_msg
-{
-    uint8_t opcode;
-    uint8_t phyport;
-    bool lldp_enable;
+struct zxdh_debug_msg {
+	uint8_t opcode;
+	uint8_t phyport;
+	bool lldp_enable;
 } __attribute__((packed));
 
-struct zxdh_debug_rcv_msg
-{
-    uint8_t reps_states;
-    uint8_t lldp_enable;
+struct zxdh_debug_rcv_msg {
+	uint8_t reps_states;
+	uint8_t lldp_enable;
 } __attribute__((packed));
 
-enum zxdh_en_link_speed_bit_indices
-{
-    SPM_SPEED_1X_1G = 2,
-    SPM_SPEED_1X_10G = 5,
-    SPM_SPEED_1X_25G = 6,
-    SPM_SPEED_1X_50G = 7,
-    SPM_SPEED_2X_100G = 8,
-    SPM_SPEED_4X_40G = 9,
-    SPM_SPEED_4X_100G = 10,
+enum zxdh_en_link_speed_bit_indices {
+	SPM_SPEED_1X_1G = 2,
+	SPM_SPEED_1X_10G = 5,
+	SPM_SPEED_1X_25G = 6,
+	SPM_SPEED_1X_50G = 7,
+	SPM_SPEED_2X_100G = 8,
+	SPM_SPEED_4X_40G = 9,
+	SPM_SPEED_4X_100G = 10,
 };
 
-enum zxdh_en_fec_mode_bit_indices
-{
-    SPM_FEC_NONE = 0,
-    SPM_FEC_BASER = 1,
-    SPM_FEC_RS528 = 2,
-    SPM_FEC_RS544 = 3,
+enum zxdh_en_fec_mode_bit_indices {
+	SPM_FEC_NONE = 0,
+	SPM_FEC_BASER = 1,
+	SPM_FEC_RS528 = 2,
+	SPM_FEC_RS544 = 3,
 };
 
-enum zxdh_en_fc_mode_bit_indices
-{
-    SPM_FC_NONE = 0,
-    SPM_FC_PAUSE_RX = 1,
-    SPM_FC_PAUSE_TX = 2,
-    SPM_FC_PAUSE_FULL = 3,
-    SPM_FC_PFC_FULL = 4,
+enum zxdh_en_fc_mode_bit_indices {
+	SPM_FC_NONE = 0,
+	SPM_FC_PAUSE_RX = 1,
+	SPM_FC_PAUSE_TX = 2,
+	SPM_FC_PAUSE_FULL = 3,
+	SPM_FC_PFC_FULL = 4,
 };
 
-struct zxdh_en_module_eeprom_param
-{
-    uint8_t i2c_addr;
-    uint8_t bank;
-    uint8_t page;
-    uint8_t offset;
-    uint8_t length;
+struct zxdh_en_module_eeprom_param {
+	uint8_t i2c_addr;
+	uint8_t bank;
+	uint8_t page;
+	uint8_t offset;
+	uint8_t length;
 };
 
-#define SFF_I2C_ADDRESS_LOW	    (0x50)
-#define SFF_I2C_ADDRESS_HIGH    (0x51)
+#define SFF_I2C_ADDRESS_LOW (0x50)
+#define SFF_I2C_ADDRESS_HIGH (0x51)
 
 enum zxdh_module_id {
-    ZXDH_MODULE_ID_SFP              = 0x3,
-    ZXDH_MODULE_ID_QSFP             = 0xC,
-    ZXDH_MODULE_ID_QSFP_PLUS        = 0xD,
-    ZXDH_MODULE_ID_QSFP28           = 0x11,
-    ZXDH_MODULE_ID_QSFP_DD          = 0x18,
-    ZXDH_MODULE_ID_OSFP             = 0x19,
-    ZXDH_MODULE_ID_DSFP             = 0x1B,
+	ZXDH_MODULE_ID_SFP = 0x3,
+	ZXDH_MODULE_ID_QSFP = 0xC,
+	ZXDH_MODULE_ID_QSFP_PLUS = 0xD,
+	ZXDH_MODULE_ID_QSFP28 = 0x11,
+	ZXDH_MODULE_ID_QSFP_DD = 0x18,
+	ZXDH_MODULE_ID_OSFP = 0x19,
+	ZXDH_MODULE_ID_DSFP = 0x1B,
 };
 
-#define SPEED_MODES_TO_SPEED(speed_modes, speed)                                 \
-do                                                                               \
-{                                                                                \
-    if (((speed_modes) & BIT(SPM_SPEED_1X_1G)) == BIT(SPM_SPEED_1X_1G))          \
-    {                                                                            \
-        (speed) = SPEED_1000;                                                    \
-    }                                                                            \
-    else if (((speed_modes) & BIT(SPM_SPEED_1X_10G)) == BIT(SPM_SPEED_1X_10G))   \
-    {                                                                            \
-        (speed) = SPEED_10000;                                                   \
-    }                                                                            \
-    else if (((speed_modes) & BIT(SPM_SPEED_1X_25G)) == BIT(SPM_SPEED_1X_25G))   \
-    {                                                                            \
-        (speed) = SPEED_25000;                                                   \
-    }                                                                            \
-    else if (((speed_modes) & BIT(SPM_SPEED_4X_40G)) == BIT(SPM_SPEED_4X_40G))   \
-    {                                                                            \
-        (speed) = SPEED_40000;                                                   \
-    }                                                                            \
-    else if (((speed_modes) & BIT(SPM_SPEED_1X_50G)) == BIT(SPM_SPEED_1X_50G))   \
-    {                                                                            \
-        (speed) = SPEED_50000;                                                   \
-    }                                                                            \
-    else if (((speed_modes) & BIT(SPM_SPEED_2X_100G)) == BIT(SPM_SPEED_2X_100G)) \
-    {                                                                            \
-        (speed) = SPEED_100000;                                                  \
-    }                                                                            \
-    else if (((speed_modes) & BIT(SPM_SPEED_4X_100G)) == BIT(SPM_SPEED_4X_100G)) \
-    {                                                                            \
-        (speed) = SPEED_100000;                                                  \
-    }                                                                            \
-    else                                                                         \
-    {                                                                            \
-        (speed) = SPEED_UNKNOWN;                                                 \
-    }                                                                            \
-} while (0)
+#define SPEED_MODES_TO_SPEED(speed_modes, speed)                            \
+	do {                                                                    \
+		if (((speed_modes)&BIT(SPM_SPEED_1X_1G)) == BIT(SPM_SPEED_1X_1G)) { \
+			(speed) = SPEED_1000;                                           \
+		} else if (((speed_modes)&BIT(SPM_SPEED_1X_10G)) ==                 \
+				   BIT(SPM_SPEED_1X_10G)) {                                 \
+			(speed) = SPEED_10000;                                          \
+		} else if (((speed_modes)&BIT(SPM_SPEED_1X_25G)) ==                 \
+				   BIT(SPM_SPEED_1X_25G)) {                                 \
+			(speed) = SPEED_25000;                                          \
+		} else if (((speed_modes)&BIT(SPM_SPEED_4X_40G)) ==                 \
+				   BIT(SPM_SPEED_4X_40G)) {                                 \
+			(speed) = SPEED_40000;                                          \
+		} else if (((speed_modes)&BIT(SPM_SPEED_1X_50G)) ==                 \
+				   BIT(SPM_SPEED_1X_50G)) {                                 \
+			(speed) = SPEED_50000;                                          \
+		} else if (((speed_modes)&BIT(SPM_SPEED_2X_100G)) ==                \
+				   BIT(SPM_SPEED_2X_100G)) {                                \
+			(speed) = SPEED_100000;                                         \
+		} else if (((speed_modes)&BIT(SPM_SPEED_4X_100G)) ==                \
+				   BIT(SPM_SPEED_4X_100G)) {                                \
+			(speed) = SPEED_100000;                                         \
+		} else {                                                            \
+			(speed) = SPEED_UNKNOWN;                                        \
+		}                                                                   \
+	} while (0)
 
 #define GET_VFID(vport)                                                 \
-    (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) ?  \
-    (PF_VQM_VFID_OFFSET + EPID(vport) * 8 + FUNC_NUM(vport)) :          \
-    (EPID(vport) * 256 + VFUNC_NUM(vport))                              \
-
+	((en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) ? \
+			   (PF_VQM_VFID_OFFSET + EPID(vport) * 8 + FUNC_NUM(vport)) : \
+			   (EPID(vport) * 256 + VFUNC_NUM(vport)))
 
-#define NP_GET_PKT_CNT    0
-#define NP_CLEAR_PKT_CNT  1
+#define NP_GET_PKT_CNT 0
+#define NP_CLEAR_PKT_CNT 1
 
 struct zxdh_en_device;
 int32_t zxdh_common_tbl_init(struct net_device *netdev);
 int32_t zxdh_en_phyport_init(struct zxdh_en_device *en_dev);
-int32_t zxdh_en_autoneg_set(struct zxdh_en_device *en_dev, uint8_t enable, uint32_t speed_modes);
+int32_t zxdh_en_autoneg_set(struct zxdh_en_device *en_dev, uint8_t enable,
+							uint32_t speed_modes);
 int32_t zxdh_vport_stats_get(struct zxdh_en_device *en_dev);
 int32_t zxdh_en_vport_pre_stats_get(struct zxdh_en_device *en_dev);
 int32_t zxdh_mac_stats_get(struct zxdh_en_device *en_dev);
 int32_t zxdh_mac_stats_clear(struct zxdh_en_device *en_dev);
 int32_t zxdh_hash_id_get(struct zxdh_en_device *en_dev);
 int32_t zxdh_en_fec_mode_set(struct zxdh_en_device *en_dev, uint32_t fec_cfg);
-int32_t zxdh_en_fec_mode_get(struct zxdh_en_device *en_dev, uint32_t *fec_cap, uint32_t *fec_cfg, uint32_t *fec_active);
+int32_t zxdh_en_fec_mode_get(struct zxdh_en_device *en_dev, uint32_t *fec_cap,
+							 uint32_t *fec_cfg, uint32_t *fec_active);
 int32_t zxdh_en_fc_mode_set(struct zxdh_en_device *en_dev, uint32_t fc_mode);
 int32_t zxdh_en_fc_mode_get(struct zxdh_en_device *en_dev, uint32_t *fc_mode);
-uint32_t zxdh_en_module_eeprom_read(struct zxdh_en_device *en_dev, struct zxdh_en_module_eeprom_param *query, uint8_t *data);
+uint32_t zxdh_en_module_eeprom_read(struct zxdh_en_device *en_dev,
+									struct zxdh_en_module_eeprom_param *query,
+									uint8_t *data);
 int32_t zxdh_lldp_enable_set(struct zxdh_en_device *en_dev, bool lldp_enable);
 int32_t zxdh_sshd_enable_set(struct zxdh_en_device *en_dev, bool sshd_enable);
-int32_t zxdh_vf_dpp_add_mac(struct zxdh_en_device *en_dev, const uint8_t *dev_addr, uint8_t filter_flag);
-int32_t zxdh_vf_dpp_del_mac(struct zxdh_en_device *en_dev, const uint8_t *dev_addr, uint8_t filter_flag, bool mac_flag);
+int32_t zxdh_vf_dpp_add_mac(struct zxdh_en_device *en_dev,
+							const uint8_t *dev_addr, uint8_t filter_flag);
+int32_t zxdh_vf_dpp_del_mac(struct zxdh_en_device *en_dev,
+							const uint8_t *dev_addr, uint8_t filter_flag,
+							bool mac_flag);
 void zxdh_vport_uninit(struct net_device *netdev);
 int32_t zxdh_pf_port_init(struct net_device *netdev);
 int32_t zxdh_vf_dpp_port_init(struct net_device *netdev);
-int32_t zxdh_vf_egr_port_attr_set(struct zxdh_en_device *en_dev, uint32_t mode, uint32_t value, uint8_t fow);
-int32_t zxdh_vf_egr_port_attr_get(struct zxdh_en_device *en_dev, ZXDH_VPORT_T *port_attr_entry);
+int32_t zxdh_vf_egr_port_attr_set(struct zxdh_en_device *en_dev, uint32_t mode,
+								  uint32_t value, uint8_t fow);
+int32_t zxdh_vf_egr_port_attr_get(struct zxdh_en_device *en_dev,
+								  ZXDH_VPORT_T *port_attr_entry);
 int32_t zxdh_vf_rss_en_set(struct zxdh_en_device *en_dev, uint32_t enable);
-int32_t zxdh_num_channels_changed(struct zxdh_en_device *en_dev, uint16_t num_changed);
-int32_t zxdh_send_command_to_specify(struct zxdh_en_device *en_dev, uint16_t module_id, void *msg, void *ack);
+int32_t zxdh_num_channels_changed(struct zxdh_en_device *en_dev,
+								  uint16_t num_changed);
+int32_t zxdh_send_command_to_specify(struct zxdh_en_device *en_dev,
+									 uint16_t module_id, void *msg, void *ack);
 int32_t zxdh_pf_macpcs_num_get(struct zxdh_en_device *en_dev);
-int32_t zxdh_lldp_enable_get(struct zxdh_en_device *en_dev, uint32_t *lldp_enable);
+int32_t zxdh_lldp_enable_get(struct zxdh_en_device *en_dev,
+							 uint32_t *lldp_enable);
 int32_t zxdh_vf_get_mac(struct net_device *netdev);
 int32_t zxdh_rxfh_set(struct zxdh_en_device *en_dev, uint32_t *queue_map);
 void zxdh_rxfh_del(struct zxdh_en_device *en_dev);
 void zxdh_u32_array_print(uint32_t *array, uint16_t size);
-int32_t zxdh_en_firmware_version_get(struct zxdh_en_device *en_dev, uint8_t *fw_version, uint8_t *fw_version_len);
+int32_t zxdh_en_firmware_version_get(struct zxdh_en_device *en_dev,
+									 uint8_t *fw_version,
+									 uint8_t *fw_version_len);
 int32_t zxdh_panel_id_get(struct zxdh_en_device *en_dev);
-int32_t zxdh_vf_port_promisc_set(struct zxdh_en_device *en_dev, uint8_t mode, uint8_t value, uint8_t fow);
+int32_t zxdh_vf_port_promisc_set(struct zxdh_en_device *en_dev, uint8_t mode,
+								 uint8_t value, uint8_t fow);
 int32_t zxdh_phyport_get(struct zxdh_en_device *en_dev);
 int32_t zxdh_vf_1588_call_np_interface(struct zxdh_en_device *en_dev);
 int32_t zxdh_aux_alloc_pannel(struct zxdh_en_device *en_dev);
 int8_t zxdh_debug_ip_get(struct zxdh_en_device *en_dev, int8_t *ip);
-int32_t zxdh_riscv_os_type_get(struct zxdh_en_device *en_dev, uint8_t *is_zios);
-int32_t zxdh_vf_dpp_add_ipv6_mac(struct zxdh_en_device *en_dev, const uint8_t *mac_addr);
-int32_t zxdh_vf_dpp_del_ipv6_mac(struct zxdh_en_device *en_dev, const uint8_t *mac_addr);
-
-#endif  /* END __ZXDH_EN_COMMAND_H_ */
+int32_t zxdh_vf_dpp_add_ipv6_mac(struct zxdh_en_device *en_dev,
+								 const uint8_t *dev_addr);
+int32_t zxdh_vf_dpp_del_ipv6_mac(struct zxdh_en_device *en_dev,
+								 const uint8_t *dev_addr);
+#endif /* END __ZXDH_EN_COMMAND_H_ */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/en_ioctl.c b/src/net/drivers/net/ethernet/dinghai/en_aux/en_ioctl.c
index f8a48fbd412e0f8e1eb5bd8f8e1dd30a5c4f12ec..5596e6dbbc6eaf437594babdf0c0a8ab5478ffdc 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/en_ioctl.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/en_ioctl.c
@@ -7,1457 +7,1380 @@
 #include "../en_np/table/include/dpp_tbl_api.h"
 #include "../en_pf/msg_func.h"
 #include "../en_pf/eq.h"
-#include "../en_tsn/zxdh_tsn_ioctl.h"
 
-extern int32_t tod_device_set_bar_virtual_addr(uint64_t virtaddr, uint16_t pcieid);
+extern int32_t tod_device_set_bar_virtual_addr(uint64_t virtaddr);
 int32_t print_data(uint8_t *data, uint32_t len)
 {
-    int32_t i = 0;
-    uint32_t loopcnt = 0;
-    uint32_t last_line_len = 0;
-    uint32_t line_len = PKT_PRINT_LINE_LEN;
-    uint8_t last_line_data[PKT_PRINT_LINE_LEN] = {0};
-
-    if (len == 0)
-    {
-        return 0;
-    }
-    loopcnt = len / line_len;
-    last_line_len = len % line_len;
-
-    LOG_DEBUG("***************packet data[len: %d]***************\n", len);
-    for (i = 0; i < loopcnt; i++)
-    {
-        LOG_INFO("%.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x\n",                            \
-                 *(data + (line_len * i) + 0), *(data + (line_len * i) + 1), *(data + (line_len * i) + 2), *(data + (line_len * i) + 3),     \
-                 *(data + (line_len * i) + 4), *(data + (line_len * i) + 5), *(data + (line_len * i) + 6), *(data + (line_len * i) + 7),     \
-                 *(data + (line_len * i) + 8), *(data + (line_len * i) + 9), *(data + (line_len * i) + 10), *(data + (line_len * i) + 11),   \
-                 *(data + (line_len * i) + 12), *(data + (line_len * i) + 13), *(data + (line_len * i) + 14), *(data + (line_len * i) + 15));
-    }
-    if (last_line_len != 0)
-    {
-        memcpy(last_line_data, (data + (line_len * i)), last_line_len);
-        LOG_INFO("%.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x\n", \
-                 last_line_data[0], last_line_data[1], last_line_data[2], last_line_data[3],     \
-                 last_line_data[4], last_line_data[5], last_line_data[6], last_line_data[7],     \
-                 last_line_data[8], last_line_data[9], last_line_data[10], last_line_data[11],   \
-                 last_line_data[12], last_line_data[13], last_line_data[14], last_line_data[15]);
-    }
-    LOG_INFO("****************end packet data**************\n");
-
-    return 0;
+	int32_t i = 0;
+	uint32_t loopcnt = 0;
+	uint32_t last_line_len = 0;
+	uint32_t line_len = PKT_PRINT_LINE_LEN;
+	uint8_t last_line_data[PKT_PRINT_LINE_LEN] = { 0 };
+
+	if (len == 0) {
+		return 0;
+	}
+	loopcnt = len / line_len;
+	last_line_len = len % line_len;
+
+	LOG_DEBUG("***************packet data[len: %d]***************\n", len);
+	for (i = 0; i < loopcnt; i++) {
+		LOG_INFO(
+				"%.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x "
+				"%.2x %.2x %.2x\n",
+				*(data + (line_len * i) + 0), *(data + (line_len * i) + 1),
+				*(data + (line_len * i) + 2), *(data + (line_len * i) + 3),
+				*(data + (line_len * i) + 4), *(data + (line_len * i) + 5),
+				*(data + (line_len * i) + 6), *(data + (line_len * i) + 7),
+				*(data + (line_len * i) + 8), *(data + (line_len * i) + 9),
+				*(data + (line_len * i) + 10), *(data + (line_len * i) + 11),
+				*(data + (line_len * i) + 12), *(data + (line_len * i) + 13),
+				*(data + (line_len * i) + 14), *(data + (line_len * i) + 15));
+	}
+	if (last_line_len != 0) {
+		memcpy(last_line_data, (data + (line_len * i)), last_line_len);
+		LOG_INFO(
+				"%.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x %.2x "
+				"%.2x %.2x %.2x\n",
+				last_line_data[0], last_line_data[1], last_line_data[2],
+				last_line_data[3], last_line_data[4], last_line_data[5],
+				last_line_data[6], last_line_data[7], last_line_data[8],
+				last_line_data[9], last_line_data[10], last_line_data[11],
+				last_line_data[12], last_line_data[13], last_line_data[14],
+				last_line_data[15]);
+	}
+	LOG_INFO("****************end packet data**************\n");
+
+	return 0;
 }
 
 int32_t zxdh_read_reg_cmd(struct net_device *netdev, struct ifreq *ifr)
 {
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    struct zxdh_en_reg *reg = NULL;
-    uint32_t size = sizeof(struct zxdh_en_reg);
-    uint64_t base_addr = 0;
-    uint32_t num = 0;
-    int32_t err = 0;
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-
-    reg = kzalloc(size, GFP_KERNEL);
-    CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n");
-
-    if (copy_from_user(reg, ifr->ifr_ifru.ifru_data, size))
-    {
-        LOG_ERR("copy_from_user failed\n");
-        err = -EFAULT;
-        goto err_ret;
-    }
-
-    if ((reg->num == 0) || (reg->num > MAX_ACCESS_NUM))
-    {
-        LOG_ERR("transmit failed, reg->num=%u\n", reg->num);
-        err = -EFAULT;
-        goto err_ret;
-    }
-
-    base_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0);
-
-    for (num = 0; num < reg->num; num++)
-    {
-        reg->data[num] = readl((const volatile void *)(base_addr + (reg->offset & 0xfffffffc) + num * 4));
-    }
-
-    if (copy_to_user(ifr->ifr_ifru.ifru_data, reg,  size))
-    {
-        LOG_ERR("copy_to_user failed\n");
-        err = -EFAULT;
-    }
-
-err_ret:
-    kfree(reg);
-    return err;
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	struct zxdh_en_reg reg = { 0 };
+	uint64_t base_addr = 0;
+	uint32_t num = 0;
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+
+	if (copy_from_user(&reg, ifr->ifr_ifru.ifru_data, sizeof(reg))) {
+		LOG_ERR("copy_from_user failed\n");
+		return -EFAULT;
+	}
+
+	if ((reg.num == 0) || (reg.num > MAX_ACCESS_NUM)) {
+		LOG_ERR("transmit failed, reg.num=%u\n", reg.num);
+		return -EFAULT;
+	}
+
+	base_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0);
+
+	for (num = 0; num < reg.num; num++) {
+		reg.data[num] = readl(
+				(const volatile void *)(base_addr + (reg.offset & 0xfffffffc) +
+										num * 4));
+	}
+
+	if (copy_to_user(ifr->ifr_ifru.ifru_data, &reg, sizeof(reg))) {
+		LOG_ERR("copy_to_user failed\n");
+		return -EFAULT;
+	}
+
+	return 0;
 }
 
 int32_t zxdh_write_reg_cmd(struct net_device *netdev, struct ifreq *ifr)
 {
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    struct zxdh_en_reg *reg = NULL;
-    uint32_t size = sizeof(struct zxdh_en_reg);
-    uint64_t base_addr = 0;
-    uint32_t num = 0;
-    int32_t err = 0;
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-
-    reg = kzalloc(size, GFP_KERNEL);
-    CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n");
-
-    if (copy_from_user(reg, ifr->ifr_ifru.ifru_data, size))
-    {
-        LOG_ERR("copy_from_user failed\n");
-        err = -EFAULT;
-        goto err_ret;
-    }
-
-    if ((reg->num == 0) || (reg->num > MAX_ACCESS_NUM))
-    {
-        LOG_ERR("transmit failed, reg->num=%u\n", reg->num);
-        err = -EFAULT;
-        goto err_ret;
-    }
-
-    base_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0);
-
-    for (num = 0; num < reg->num; num++)
-    {
-        writel(reg->data[num], (volatile void *)(base_addr + (reg->offset & 0xfffffffc) + num * 4));
-    }
-
-err_ret:
-    kfree(reg);
-    return err;
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	struct zxdh_en_reg reg = { 0 };
+	uint64_t base_addr = 0;
+	uint32_t num = 0;
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+
+	if (copy_from_user(&reg, ifr->ifr_ifru.ifru_data, sizeof(reg))) {
+		LOG_ERR("copy_from_user failed\n");
+		return -EFAULT;
+	}
+
+	if ((reg.num == 0) || (reg.num > MAX_ACCESS_NUM)) {
+		LOG_ERR("transmit failed, reg.num=%u\n", reg.num);
+		return -EFAULT;
+	}
+
+	base_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0);
+
+	for (num = 0; num < reg.num; num++) {
+		writel(reg.data[num],
+			   (volatile void *)(base_addr + (reg.offset & 0xfffffffc) +
+								 num * 4));
+	}
+
+	return 0;
 }
 
 int32_t print_vring_info(struct virtqueue *vq, struct zxdh_en_reg *reg)
 {
-    struct vring_virtqueue *vvq = to_vvq(vq);
+	struct vring_virtqueue *vvq = to_vvq(vq);
 
-    if ((reg->num + reg->data[0]) > vvq->packed.vring.num)
-    {
-        LOG_ERR("the sum of desc_index %u and desc_num %u over desc depth %u, should be [0-%u]\n", \
-                 reg->num, reg->data[0], vvq->packed.vring.num, vvq->packed.vring.num - 1);
-        return -EINVAL;
-    }
+	if ((reg->num + reg->data[0]) > vvq->packed.vring.num) {
+		LOG_ERR("the sum of desc_index %u and desc_num %u over desc depth %u, "
+				"should be [0-%u]\n",
+				reg->num, reg->data[0], vvq->packed.vring.num,
+				vvq->packed.vring.num - 1);
+		return -EINVAL;
+	}
 
-    zxdh_print_vring_info(vq, reg->num, reg->num + reg->data[0]);
+	zxdh_print_vring_info(vq, reg->num, reg->num + reg->data[0]);
 
-    return 0;
+	return 0;
 }
 
 int32_t zxdh_get_vring_info(struct net_device *netdev, struct ifreq *ifr)
 {
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    struct zxdh_en_reg *reg = NULL;
-    uint32_t size = sizeof(struct zxdh_en_reg);
-    struct virtqueue *vq = NULL;
-    int32_t ret = 0;
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-
-    reg = kzalloc(size, GFP_KERNEL);
-    CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n");
-
-    if (copy_from_user(reg, ifr->ifr_ifru.ifru_data, size))
-    {
-        LOG_ERR("copy_from_user failed\n");
-        ret = -EFAULT;
-        goto err_ret;
-    }
-
-    if (reg->offset >= en_dev->max_queue_pairs)
-    {
-        LOG_ERR("the queue index %u over the curr_queue_pairs %u, should be [0-%u]\n", \
-                 reg->offset, en_dev->curr_queue_pairs, en_dev->curr_queue_pairs - 1);
-        ret = -EINVAL;
-        goto err_ret;
-    }
-
-    vq = en_dev->sq[reg->offset].vq;
-    LOG_INFO("******************************tx vring info****************************\n");
-    ret = print_vring_info(vq, reg);
-    if (ret != 0)
-    {
-        LOG_ERR("print tx vring info failed!\n");
-        ret = -EINVAL;
-        goto err_ret;
-    }
-
-    vq = en_dev->rq[reg->offset].vq;
-    LOG_INFO("******************************rx vring info****************************\n");
-    ret = print_vring_info(vq, reg);
-    if (ret != 0)
-    {
-        LOG_ERR("print rx vring info failed!\n");
-        ret = -EINVAL;
-    }
-
-err_ret:
-    kfree(reg);
-    return ret;
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	struct zxdh_en_reg reg = { 0 };
+	struct virtqueue *vq = NULL;
+	int32_t ret = 0;
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+
+	if (copy_from_user(&reg, ifr->ifr_ifru.ifru_data, sizeof(reg))) {
+		LOG_ERR("copy_from_user failed\n");
+		return -EFAULT;
+	}
+
+	if (reg.offset >= en_dev->max_queue_pairs) {
+		LOG_ERR("the queue index %u over the curr_queue_pairs %u, should be [0-%u]\n",
+				reg.offset, en_dev->curr_queue_pairs,
+				en_dev->curr_queue_pairs - 1);
+		return -EINVAL;
+	}
+
+	vq = en_dev->sq[reg.offset].vq;
+	LOG_INFO("******************************tx vring "
+			 "info****************************\n");
+	ret = print_vring_info(vq, &reg);
+	CHECK_UNEQUAL_ERR(ret, 0, -EINVAL, "print tx vring info failed!\n");
+
+	vq = en_dev->rq[reg.offset].vq;
+	LOG_INFO("******************************rx vring "
+			 "info****************************\n");
+	ret = print_vring_info(vq, &reg);
+	CHECK_UNEQUAL_ERR(ret, 0, -EINVAL, "print rx vring info failed!\n");
+
+	return 0;
 }
 
-int32_t zxdh_en_set_clock_no(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_set_clock_no(struct net_device *netdev, struct ifreq *ifr,
+							 struct zxdh_en_reg *reg)
 {
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
 
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
 
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
 
-    if (reg->num != 1)
-    {
-        LOG_ERR("Transmit failed[len = %d]!\n", reg->num);
-        goto err_ret;
-    }
+	if (reg->num != 1) {
+		LOG_ERR("Transmit failed[len = %d]!\n", reg->num);
+		goto err_ret;
+	}
 
-    en_dev->clock_no = reg->data[0];
-    LOG_INFO("en_dev %s clock_no = %d\n", en_dev->netdev->name, en_dev->clock_no);
+	en_dev->clock_no = reg->data[0];
+	LOG_INFO("en_dev %s clock_no = %d\n", en_dev->netdev->name,
+			 en_dev->clock_no);
 
-    reg->num = 0;
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        LOG_ERR("copy_to_user failed!\n");
-        goto err_ret;
-    }
+	reg->num = 0;
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		LOG_ERR("copy_to_user failed!\n");
+		goto err_ret;
+	}
 
-    return 0;
+	return 0;
 
 err_ret:
-    return -1;
+	return -1;
 }
 
 void copy_u32_to_u8(uint8_t *data_pkt, uint32_t *data, uint32_t pktlen)
 {
-    uint32_t i = 0;
+	uint32_t i = 0;
 
-    for (i = 0; i < pktlen; i++)
-    {
-        *data_pkt++ = data[i];
-    }
+	for (i = 0; i < pktlen; i++) {
+		*data_pkt++ = data[i];
+	}
 }
 
 int32_t zxdh_tx_file_pkts(struct zxdh_en_priv *en_priv, struct zxdh_en_reg *reg)
 {
-    int32_t total_sg = 0;
-    uint8_t *data_pkt = NULL;
-    struct scatterlist *sg = NULL;
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct send_queue *sq = en_dev->sq;
-    struct page *page = NULL;
-    struct data_packet pkt = {0};
-    uint16_t i = 0;
-    uint32_t len = 0;
-    void *ptr = NULL;
-    uint32_t last_buff_len = 0;
-    uint32_t pktLen = reg->num;
-    uint32_t buffLen = 4096;
-
-    while ((ptr = virtqueue_get_buf(sq->vq, &len)) != NULL)
-    {
-        LOG_ERR("virtqueue_get_buf() != NULL, ptr=0x%llx, len=0x%x\n", (uint64_t)ptr, len);
-    };
-
-    sg = sq->sg;
-    pkt.buf_size = 16 * PAGE_SIZE;
-    page = alloc_pages(GFP_KERNEL, 4);
-    if (unlikely(page == NULL))
-    {
-        LOG_ERR("page is null\n");
-        goto err;
-    }
-
-    pkt.buf = page_address(page);
-    if (unlikely(pkt.buf == NULL))
-    {
-        LOG_ERR("pkt.buf is null\n");
-        goto err1;
-    }
-    memset(pkt.buf, 0, pkt.buf_size);
-
-    data_pkt = (uint8_t*)pkt.buf;
-    copy_u32_to_u8(data_pkt, reg->data, pktLen);
-    print_data(data_pkt, (pktLen > PKT_PRINT_LEN_MAX) ? PKT_PRINT_LEN_MAX : pktLen);
-
-    total_sg = pktLen / buffLen;
-    last_buff_len = pktLen % buffLen;
-    if (last_buff_len != 0)
-    {
-        total_sg += 1;
-    }
-
-    sg_init_table(sg, total_sg);
-    for (i = 0; i < total_sg; i++)
-    {
-        if (i == (total_sg - 1))
-        {
-            sg_set_buf(&sg[i], data_pkt + (i * buffLen), ((last_buff_len != 0) ? last_buff_len : buffLen));
-        }
-        else
-        {
-            sg_set_buf(&sg[i], data_pkt + (i * buffLen), buffLen);
-        }
-    }
-
-    if (unlikely(virtqueue_add_outbuf(sq->vq, sg, total_sg, data_pkt, GFP_ATOMIC) != 0))
-    {
-        LOG_ERR("virtqueue_add_outbuf failure!\n");
-        goto err1;
-    }
-
-    if (virtqueue_kick_prepare_packed(sq->vq) && virtqueue_notify(sq->vq))
-    {
-        u64_stats_update_begin(&sq->stats.syncp);
-        sq->stats.kicks++;
-        u64_stats_update_end(&sq->stats.syncp);
-    }
-
-    en_dev->netdev->stats.tx_packets++;
-    en_dev->netdev->stats.tx_bytes += pktLen;
-    LOG_INFO("en_dev->netdev->stats.tx_packets=%ld, tx pktLen=%d\n", en_dev->netdev->stats.tx_packets, pktLen);
-
-    return 0;
+	int32_t total_sg = 0;
+	uint8_t *data_pkt = NULL;
+	struct scatterlist *sg = NULL;
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct send_queue *sq = en_dev->sq;
+	struct page *page = NULL;
+	struct data_packet pkt = { 0 };
+	uint16_t i = 0;
+	uint32_t len = 0;
+	void *ptr = NULL;
+	uint32_t last_buff_len = 0;
+	uint32_t pktLen = reg->num;
+	uint32_t buffLen = 4096;
+
+	while ((ptr = virtqueue_get_buf(sq->vq, &len)) != NULL) {
+		LOG_ERR("virtqueue_get_buf() != NULL, ptr=0x%llx, len=0x%x\n",
+				(uint64_t)ptr, len);
+	};
+
+	sg = sq->sg;
+	pkt.buf_size = 16 * PAGE_SIZE;
+	page = alloc_pages(GFP_KERNEL, 4);
+	if (unlikely(page == NULL)) {
+		LOG_ERR("page is null\n");
+		goto err;
+	}
+
+	pkt.buf = page_address(page);
+	if (unlikely(pkt.buf == NULL)) {
+		LOG_ERR("pkt.buf is null\n");
+		goto err1;
+	}
+	memset(pkt.buf, 0, pkt.buf_size);
+
+	data_pkt = (uint8_t *)pkt.buf;
+	copy_u32_to_u8(data_pkt, reg->data, pktLen);
+	print_data(data_pkt,
+			   (pktLen > PKT_PRINT_LEN_MAX) ? PKT_PRINT_LEN_MAX : pktLen);
+
+	total_sg = pktLen / buffLen;
+	last_buff_len = pktLen % buffLen;
+	if (last_buff_len != 0) {
+		total_sg += 1;
+	}
+
+	sg_init_table(sg, total_sg);
+	for (i = 0; i < total_sg; i++) {
+		if (i == (total_sg - 1)) {
+			sg_set_buf(&sg[i], data_pkt + (i * buffLen),
+					   ((last_buff_len != 0) ? last_buff_len : buffLen));
+		} else {
+			sg_set_buf(&sg[i], data_pkt + (i * buffLen), buffLen);
+		}
+	}
+
+	if (unlikely(virtqueue_add_outbuf(sq->vq, sg, total_sg, data_pkt,
+									  GFP_ATOMIC) != 0)) {
+		LOG_ERR("virtqueue_add_outbuf failure!\n");
+		goto err1;
+	}
+
+	if (virtqueue_kick_prepare_packed(sq->vq) && virtqueue_notify(sq->vq)) {
+		u64_stats_update_begin(&sq->stats.syncp);
+		sq->stats.kicks++;
+		u64_stats_update_end(&sq->stats.syncp);
+	}
+
+	en_dev->netdev->stats.tx_packets++;
+	en_dev->netdev->stats.tx_bytes += pktLen;
+	LOG_INFO("en_dev->netdev->stats.tx_packets=%ld, tx pktLen=%d\n",
+			 en_dev->netdev->stats.tx_packets, pktLen);
+
+	return 0;
 
 err1:
-    free_pages((uint64_t)pkt.buf, 4);
+	free_pages((uint64_t)pkt.buf, 4);
 err:
-    return -1;
+	return -1;
 }
 
 int32_t zxdh_send_file_pkt(struct net_device *netdev, struct ifreq *ifr)
 {
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_reg *reg = NULL;
-    uint32_t size = sizeof(struct zxdh_en_reg);
-    int32_t ret = 0;
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-
-    reg = kzalloc(size, GFP_KERNEL);
-    CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n");
-
-    if (copy_from_user(reg, ifr->ifr_ifru.ifru_data, size))
-    {
-        LOG_ERR("copy_from_user failed\n");
-        ret = -EFAULT;
-        goto err_ret;
-    }
-
-    if ((reg->num == 0) || (reg->num > MAX_ACCESS_NUM))
-    {
-        LOG_ERR("transmit failed, reg->num=%d\n", reg->num);
-        ret = -EFAULT;
-        goto err_ret;
-    }
-
-    ret = zxdh_tx_file_pkts(en_priv, reg);
-    if (unlikely(ret != 0))
-    {
-        LOG_ERR("transmit failed[ret = %d]!", ret);
-        ret = -1;
-        goto err_ret;
-    }
-
-    reg->num = 0;
-    if (copy_to_user(ifr->ifr_ifru.ifru_data, reg, size))
-    {
-        LOG_ERR("copy_to_user failed\n");
-        ret = -EFAULT;
-    }
-
-err_ret:
-    kfree(reg);
-    return ret;
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_reg reg = { 0 };
+	int32_t ret = 0;
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+
+	if (copy_from_user(&reg, ifr->ifr_ifru.ifru_data, sizeof(reg))) {
+		LOG_ERR("copy_from_user failed\n");
+		return -EFAULT;
+	}
+
+	if ((reg.num == 0) || (reg.num > MAX_ACCESS_NUM)) {
+		LOG_ERR("transmit failed, reg.num=%d\n", reg.num);
+		return -EFAULT;
+	}
+
+	ret = zxdh_tx_file_pkts(en_priv, &reg);
+	if (unlikely(ret != 0)) {
+		LOG_ERR("transmit failed[ret = %d]!", ret);
+		return -1;
+	}
+
+	reg.num = 0;
+	if (copy_to_user(ifr->ifr_ifru.ifru_data, &reg, sizeof(reg))) {
+		LOG_ERR("copy_to_user failed\n");
+		return -EFAULT;
+	}
+
+	return 0;
 }
 
-#ifdef  PTP_DRIVER_INTERFACE_EN
+#ifdef PTP_DRIVER_INTERFACE_EN
 /* ptp发送加密报文时，需要调用使能函数进行使能 */
-extern int32_t enable_write_ts_to_fifo(struct zxdh_en_device *en_dev, uint32_t enable, uint32_t mac_number);
-extern int32_t set_interrupt_capture_timer(struct zxdh_en_device *en_dev, uint32_t index);
-extern int32_t zxdh_set_pps_selection(struct zxdh_en_device *en_dev, uint32_t pps_type, uint32_t selection);
-extern int32_t zxdh_set_pd_detection(struct zxdh_en_device *en_dev, uint32_t pd_index, uint32_t pd_input1, uint32_t pd_input2);
-extern int32_t zxdh_get_pd_value(struct zxdh_en_device *en_dev, uint32_t pd_index, uint32_t *pd_result);
+extern int32_t enable_write_ts_to_fifo(struct zxdh_en_device *en_dev,
+									   uint32_t enable, uint32_t mac_number);
+extern int32_t set_interrupt_capture_timer(struct zxdh_en_device *en_dev,
+										   uint32_t index);
+extern int32_t zxdh_set_pps_selection(struct zxdh_en_device *en_dev,
+									  uint32_t pps_type, uint32_t selection);
+extern int32_t zxdh_set_pd_detection(struct zxdh_en_device *en_dev,
+									 uint32_t pd_index, uint32_t pd_input1,
+									 uint32_t pd_input2);
+extern int32_t zxdh_get_pd_value(struct zxdh_en_device *en_dev,
+								 uint32_t pd_index, uint32_t *pd_result);
 #endif /* PTP_DRIVER_INTERFACE_EN */
-int32_t zxdh_en_enable_ptp_encrypted_msg(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_enable_ptp_encrypted_msg(struct net_device *netdev,
+										 struct ifreq *ifr,
+										 struct zxdh_en_reg *reg)
 {
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    int32_t mac_num = 0; //0-2
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    uint32_t enable = 0;
-    int32_t ret = 0;
-
-    LOG_INFO("enter in zxdh_en_enable_ptp_encrypted_msg\n");
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-
-    mac_num = zxdh_pf_macpcs_num_get(en_dev);
-    if (mac_num < 0)
-    {
-        LOG_ERR("get mac num %d err, its value should is 0-2!\n", mac_num);
-        goto err_ret;
-    }
-
-    if (unlikely(copy_from_user(reg, ifr->ifr_ifru.ifru_data, reg_size)))
-    {
-        LOG_ERR("copy_from_user failed!\n");
-        goto err_ret;
-    }
-    if (reg->num != 1)
-    {
-        LOG_ERR("Transmit failed[len = %d]!\n", reg->num);
-        goto err_ret;
-    }
-
-    enable = reg->data[0];
-    if ((enable != 0) && (enable != 1))
-    {
-        LOG_ERR("Transmit failed[enable = %u]!\n", enable);
-        goto err_ret;
-    }
-
-    LOG_INFO("enable = %u\n", enable);
-
-#ifdef  PTP_DRIVER_INTERFACE_EN
-    /* 使能ptp加密报文发送接口 */
-    ret = enable_write_ts_to_fifo(en_dev, enable, mac_num);
-    CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "enable ptp encrypted msg failed!!\n");
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	int32_t mac_num = 0; // 0-2
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	uint32_t enable = 0;
+	int32_t ret = 0;
+
+	LOG_INFO("enter in zxdh_en_enable_ptp_encrypted_msg\n");
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+
+	mac_num = zxdh_pf_macpcs_num_get(en_dev);
+	if (mac_num < 0) {
+		LOG_ERR("get mac num %d err, its value should is 0-2!\n", mac_num);
+		goto err_ret;
+	}
+
+	if (unlikely(copy_from_user(reg, ifr->ifr_ifru.ifru_data, reg_size))) {
+		LOG_ERR("copy_from_user failed!\n");
+		goto err_ret;
+	}
+	if (reg->num != 1) {
+		LOG_ERR("Transmit failed[len = %d]!\n", reg->num);
+		goto err_ret;
+	}
+
+	enable = reg->data[0];
+	if ((enable != 0) && (enable != 1)) {
+		LOG_ERR("Transmit failed[enable = %u]!\n", enable);
+		goto err_ret;
+	}
+
+	LOG_INFO("enable = %u\n", enable);
+
+#ifdef PTP_DRIVER_INTERFACE_EN
+	/* 使能ptp加密报文发送接口 */
+	ret = enable_write_ts_to_fifo(en_dev, enable, mac_num);
+	CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "enable ptp encrypted msg failed!!\n");
 #endif /* PTP_DRIVER_INTERFACE_EN */
 
-    reg->num = 0;
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        LOG_ERR("copy_to_user failed!\n");
-        goto err_ret;
-    }
+	reg->num = 0;
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		LOG_ERR("copy_to_user failed!\n");
+		goto err_ret;
+	}
 
-    return ret;
+	return ret;
 
 err_ret:
-    return -1;
+	return -1;
 }
 
-int32_t zxdh_en_set_intr_capture_timer(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_set_intr_capture_timer(struct net_device *netdev,
+									   struct ifreq *ifr,
+									   struct zxdh_en_reg *reg)
 {
-    u_int32_t index;
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    int32_t ret = 0;
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-
-    if (reg->num != 1)
-    {
-        LOG_ERR("Transmit failed[len = %d]!", reg->num);
-        goto err_ret;
-    }
-
-    index = reg->data[0];
-    LOG_INFO("index = %d\n", index);
-    if (index > 4)
-    {
-        LOG_ERR("capture timer out of range!");
-        goto err_ret;
-    }
-#ifdef  PTP_DRIVER_INTERFACE_EN
-    ret = set_interrupt_capture_timer(en_dev, index);
-    CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "set interrupt capture timer failed!!\n");
+	u_int32_t index;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	int32_t ret = 0;
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+
+	if (reg->num != 1) {
+		LOG_ERR("Transmit failed[len = %d]!", reg->num);
+		goto err_ret;
+	}
+
+	index = reg->data[0];
+	LOG_INFO("index = %d\n", index);
+	if (index > 4) {
+		LOG_ERR("capture timer out of range!");
+		goto err_ret;
+	}
+#ifdef PTP_DRIVER_INTERFACE_EN
+	ret = set_interrupt_capture_timer(en_dev, index);
+	CHECK_UNEQUAL_ERR(ret, 0, -EFAULT,
+					  "set interrupt capture timer failed!!\n");
 #endif /* PTP_DRIVER_INTERFACE_EN */
 
-    reg->num = 0;
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        LOG_ERR("copy_to_user failed!!!\n");
-        goto err_ret;
-    }
+	reg->num = 0;
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		LOG_ERR("copy_to_user failed!!!\n");
+		goto err_ret;
+	}
 
-    return ret;
+	return ret;
 
 err_ret:
-    return -1;
-
+	return -1;
 }
 
-int32_t zxdh_en_set_pps_selection(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_set_pps_selection(struct net_device *netdev, struct ifreq *ifr,
+								  struct zxdh_en_reg *reg)
 {
-    uint32_t pps_type;
-    uint32_t selection;
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    int32_t ret = 0;
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-
-    if (reg->num != 2)
-    {
-        LOG_ERR("Transmit failed[len = %d]!", reg->num);
-        goto err_ret;
-    }
-
-    pps_type = reg->data[0];
-    selection = reg->data[1];
-    LOG_INFO("pps_type = %u, selection = %u\n", pps_type, selection);
-#ifdef  PTP_DRIVER_INTERFACE_EN
-    ret = zxdh_set_pps_selection(en_dev, pps_type, selection);
-    CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "set pps selection failed!!\n");
+	uint32_t pps_type;
+	uint32_t selection;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	int32_t ret = 0;
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+
+	if (reg->num != 2) {
+		LOG_ERR("Transmit failed[len = %d]!", reg->num);
+		goto err_ret;
+	}
+
+	pps_type = reg->data[0];
+	selection = reg->data[1];
+	LOG_INFO("pps_type = %u, selection = %u\n", pps_type, selection);
+#ifdef PTP_DRIVER_INTERFACE_EN
+	ret = zxdh_set_pps_selection(en_dev, pps_type, selection);
+	CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "set pps selection failed!!\n");
 #endif /* PTP_DRIVER_INTERFACE_EN */
 
-    reg->num = 0;
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        LOG_ERR("copy_to_user failed!!!\n");
-        goto err_ret;
-    }
+	reg->num = 0;
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		LOG_ERR("copy_to_user failed!!!\n");
+		goto err_ret;
+	}
 
-    return ret;
+	return ret;
 
 err_ret:
-    return -1;
+	return -1;
 }
 
-int32_t zxdh_en_set_phase_detection(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_set_phase_detection(struct net_device *netdev,
+									struct ifreq *ifr, struct zxdh_en_reg *reg)
 {
-    uint32_t pd_index;
-    uint32_t pd_input1;
-    uint32_t pd_input2;
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    int32_t ret = 0;
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-
-    if (reg->num != 3)
-    {
-        LOG_ERR("Transmit failed[len = %d]!", reg->num);
-        goto err_ret;
-    }
-
-    pd_index = reg->data[0];
-    pd_input1 = reg->data[1];
-    pd_input2 = reg->data[2];
-    LOG_INFO("pd_index = %u, pd_input1 = %u, pd_input2 = %u\n", pd_index, pd_input1, pd_input2);
-#ifdef  PTP_DRIVER_INTERFACE_EN
-    ret = zxdh_set_pd_detection(en_dev, pd_index, pd_input1, pd_input2);
-    CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "set pd detection failed!!\n");
+	uint32_t pd_index;
+	uint32_t pd_input1;
+	uint32_t pd_input2;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	int32_t ret = 0;
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+
+	if (reg->num != 3) {
+		LOG_ERR("Transmit failed[len = %d]!", reg->num);
+		goto err_ret;
+	}
+
+	pd_index = reg->data[0];
+	pd_input1 = reg->data[1];
+	pd_input2 = reg->data[2];
+	LOG_INFO("pd_index = %u, pd_input1 = %u, pd_input2 = %u\n", pd_index,
+			 pd_input1, pd_input2);
+#ifdef PTP_DRIVER_INTERFACE_EN
+	ret = zxdh_set_pd_detection(en_dev, pd_index, pd_input1, pd_input2);
+	CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "set pd detection failed!!\n");
 #endif /* PTP_DRIVER_INTERFACE_EN */
 
-    reg->num = 0;
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        LOG_ERR("copy_to_user failed!!!\n");
-        goto err_ret;
-    }
+	reg->num = 0;
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		LOG_ERR("copy_to_user failed!!!\n");
+		goto err_ret;
+	}
 
-    return ret;
+	return ret;
 
 err_ret:
-    return -1;
+	return -1;
 }
 
-int32_t zxdh_en_get_pd_value(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_get_pd_value(struct net_device *netdev, struct ifreq *ifr,
+							 struct zxdh_en_reg *reg)
 {
-    uint32_t pd_index;
-    uint32_t pd_result;
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    int32_t ret = 0;
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-
-    if (reg->num != 1)
-    {
-        LOG_ERR("Transmit failed[len = %d]!", reg->num);
-        goto err_ret;
-    }
-
-    pd_index = reg->data[0];
-    LOG_INFO("pd_index = %u\n", pd_index);
-#ifdef  PTP_DRIVER_INTERFACE_EN
-    ret = zxdh_get_pd_value(en_dev, pd_index, &pd_result);
-    CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "get pd value failed!!\n");
+	uint32_t pd_index;
+	uint32_t pd_result;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	int32_t ret = 0;
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+
+	if (reg->num != 1) {
+		LOG_ERR("Transmit failed[len = %d]!", reg->num);
+		goto err_ret;
+	}
+
+	pd_index = reg->data[0];
+	LOG_INFO("pd_index = %u\n", pd_index);
+#ifdef PTP_DRIVER_INTERFACE_EN
+	ret = zxdh_get_pd_value(en_dev, pd_index, &pd_result);
+	CHECK_UNEQUAL_ERR(ret, 0, -EFAULT, "get pd value failed!!\n");
 #endif /* PTP_DRIVER_INTERFACE_EN */
 
-    reg->num = 1;
-    reg->data[0] = pd_result;
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        LOG_ERR("copy_to_user failed!!!\n");
-        goto err_ret;
-    }
+	reg->num = 1;
+	reg->data[0] = pd_result;
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		LOG_ERR("copy_to_user failed!!!\n");
+		goto err_ret;
+	}
 
-    return ret;
+	return ret;
 
 err_ret:
-    return -1;
+	return -1;
 }
 
-int32_t zxdh_en_set_l2_ptp_port(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_set_l2_ptp_port(struct net_device *netdev, struct ifreq *ifr,
+								struct zxdh_en_reg *reg)
 {
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    int32_t ret = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    LOG_INFO("reg->num: %d", reg->num);
-    LOG_INFO("reg->offset: %d", reg->offset);
-    if (reg->num != 1)
-    {
-        LOG_ERR("Transmit failed[len = %d]!", reg->num);
-        goto err_ret;
-    }
-
-    en_dev->vf_1588_call_np_num = PTP_PORT_VFID_SET;
-    LOG_INFO("en_dev->vport: 0x%x, IS_PF(en_dev->vport): %d", en_dev->vport, IS_PF(en_dev->vport));
-    if (IS_PF(en_dev->vport))
-    {
-        ret = dpp_ptp_port_vfid_set(&pf_info, VQM_VFID(en_dev->vport));
-        if (ret != 0)
-        {
-            LOG_ERR("dpp_ptp_port_vfid_set failed!!!\n");
-            goto err_ret;
-        }
-    }
-    else
-    {
-        ret = zxdh_vf_1588_call_np_interface(en_dev);
-        if (ret != 0)
-        {
-            LOG_ERR("zxdh_vf_1588_call_np_interface failed!!!\n");
-            goto err_ret;
-        }
-    }
-
-    reg->num = 0;
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        LOG_ERR("copy_to_user failed!!!\n");
-        goto err_ret;
-    }
-    LOG_INFO("dpp_ptp_port_vfid_set success");
-
-    return ret;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	int32_t ret = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	LOG_INFO("reg->num: %d", reg->num);
+	LOG_INFO("reg->offset: %d", reg->offset);
+	if (reg->num != 1) {
+		LOG_ERR("Transmit failed[len = %d]!", reg->num);
+		goto err_ret;
+	}
+
+	en_dev->vf_1588_call_np_num = PTP_PORT_VFID_SET;
+	LOG_INFO("en_dev->vport: 0x%x, IS_PF(en_dev->vport): %d", en_dev->vport,
+			 IS_PF(en_dev->vport));
+	if (IS_PF(en_dev->vport)) {
+		ret = dpp_ptp_port_vfid_set(&pf_info, VQM_VFID(en_dev->vport));
+		if (ret != 0) {
+			LOG_ERR("dpp_ptp_port_vfid_set failed!!!\n");
+			goto err_ret;
+		}
+	} else {
+		ret = zxdh_vf_1588_call_np_interface(en_dev);
+		if (ret != 0) {
+			LOG_ERR("zxdh_vf_1588_call_np_interface failed!!!\n");
+			goto err_ret;
+		}
+	}
+
+	reg->num = 0;
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		LOG_ERR("copy_to_user failed!!!\n");
+		goto err_ret;
+	}
+	LOG_INFO("dpp_ptp_port_vfid_set success");
+
+	return ret;
 
 err_ret:
-    return -1;
+	return -1;
 }
 
-int32_t zxdh_en_set_ptp_tc_enable(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_set_ptp_tc_enable(struct net_device *netdev, struct ifreq *ifr,
+								  struct zxdh_en_reg *reg)
 {
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    int32_t ret = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    if (reg->num != 1)
-    {
-        LOG_ERR("Transmit failed[len = %d]!", reg->num);
-        goto err_ret;
-    }
-
-    en_dev->ptp_tc_enable_opt = reg->data[0];
-    LOG_INFO("en_dev->ptp_tc_enable_opt = %u\n", en_dev->ptp_tc_enable_opt);
-
-    en_dev->vf_1588_call_np_num = PTP_TC_ENABLE_SET;
-
-    if (IS_PF(en_dev->vport))
-    {
-        ret = dpp_ptp_tc_enable_set(&pf_info, en_dev->ptp_tc_enable_opt);
-        if (ret != 0)
-        {
-            LOG_ERR("dpp_ptp_tc_enable_set failed!!!\n");
-            goto err_ret;
-        }
-    }
-    else
-    {
-        ret = zxdh_vf_1588_call_np_interface(en_dev);
-        if (ret != 0)
-        {
-            LOG_ERR("zxdh_vf_1588_call_np_interface failed!!!\n");
-            goto err_ret;
-        }
-    }
-
-    reg->num = 0;
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        goto err_ret;
-    }
-
-    return ret;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	int32_t ret = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	if (reg->num != 1) {
+		LOG_ERR("Transmit failed[len = %d]!", reg->num);
+		goto err_ret;
+	}
+
+	en_dev->ptp_tc_enable_opt = reg->data[0];
+	LOG_INFO("en_dev->ptp_tc_enable_opt = %u\n", en_dev->ptp_tc_enable_opt);
+
+	en_dev->vf_1588_call_np_num = PTP_TC_ENABLE_SET;
+
+	if (IS_PF(en_dev->vport)) {
+		ret = dpp_ptp_tc_enable_set(&pf_info, en_dev->ptp_tc_enable_opt);
+		if (ret != 0) {
+			LOG_ERR("dpp_ptp_tc_enable_set failed!!!\n");
+			goto err_ret;
+		}
+	} else {
+		ret = zxdh_vf_1588_call_np_interface(en_dev);
+		if (ret != 0) {
+			LOG_ERR("zxdh_vf_1588_call_np_interface failed!!!\n");
+			goto err_ret;
+		}
+	}
+
+	reg->num = 0;
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		goto err_ret;
+	}
+
+	return ret;
 
 err_ret:
-    return -1;
+	return -1;
 }
 
-int32_t zxdh_en_set_synce_recovery_port(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_set_synce_recovery_port(struct net_device *netdev,
+										struct ifreq *ifr,
+										struct zxdh_en_reg *reg)
 {
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-
-    if (reg->num != 1)
-    {
-        LOG_ERR("Transmit failed[len = %d]!", reg->num);
-        goto err_ret;
-    }
-
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_RECOVERY_CLK_SET;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;
-    msg.payload.synce_clk_recovery_port.clk_speed = reg->data[0];
-    LOG_INFO("phyport = %u, clk_speed = %u\n", msg.payload.hdr_to_agt.phyport, msg.payload.synce_clk_recovery_port.clk_speed);
-    err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_en_set_synce_recovery_port failed, err: %d\n", err);
-        return err;
-    }
-
-    reg->num = 0;
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        goto err_ret;
-    }
-
-    return ret;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	int32_t ret = 0;
+
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	int32_t err = 0;
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+
+	if (reg->num != 1) {
+		LOG_ERR("Transmit failed[len = %d]!", reg->num);
+		goto err_ret;
+	}
+
+	msg.hdr_to_agt.op_code = AGENT_MAC_RECOVERY_CLK_SET;
+	msg.hdr_to_agt.phyport = en_dev->phy_port;
+	msg.synce_clk_recovery_port.clk_speed = reg->data[0];
+	LOG_INFO("phyport = %u, clk_speed = %u\n", msg.hdr_to_agt.phyport,
+			 msg.synce_clk_recovery_port.clk_speed);
+	err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
+	if (err != 0) {
+		LOG_ERR("zxdh_en_set_synce_recovery_port failed, err: %d\n", err);
+		return err;
+	}
+
+	reg->num = 0;
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		goto err_ret;
+	}
+
+	return ret;
 
 err_ret:
-    return -1;
+	return -1;
 }
 
-int32_t zxdh_en_get_synce_clk_stats(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_get_synce_clk_stats(struct net_device *netdev,
+									struct ifreq *ifr, struct zxdh_en_reg *reg)
 {
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-
-    if (reg->num != 1)
-    {
-        LOG_ERR("Transmit failed[len = %d]!", reg->num);
-        goto err_ret;
-    }
-
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_SYNCE_CLK_STATS_GET;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;
-    LOG_INFO("phyport = %u\n", msg.payload.hdr_to_agt.phyport);
-    err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_en_get_synce_clk_stats failed, err: %d\n", err);
-        return err;
-    }
-
-    reg->num = 1;
-    reg->data[0] = msg.reps.synce_clk_recovery_port.clk_stats;
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        goto err_ret;
-    }
-    LOG_INFO("num = %u, clk_stats: 0x%x\n", reg->num, reg->data[0]);
-
-    return ret;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	int32_t ret = 0;
+
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	int32_t err = 0;
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+
+	if (reg->num != 1) {
+		LOG_ERR("Transmit failed[len = %d]!", reg->num);
+		goto err_ret;
+	}
+
+	msg.hdr_to_agt.op_code = AGENT_MAC_SYNCE_CLK_STATS_GET;
+	msg.hdr_to_agt.phyport = en_dev->phy_port;
+	LOG_INFO("phyport = %u\n", msg.hdr_to_agt.phyport);
+	err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
+	if (err != 0) {
+		LOG_ERR("zxdh_en_get_synce_clk_stats failed, err: %d\n", err);
+		return err;
+	}
+
+	reg->num = 1;
+	reg->data[0] = reps.synce_clk_recovery_port.clk_stats;
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		goto err_ret;
+	}
+	LOG_INFO("num = %u, clk_stats: 0x%x\n", reg->num, reg->data[0]);
+
+	return ret;
 
 err_ret:
-    return -1;
+	return -1;
 }
 
-int32_t zxdh_en_set_spm_port_tstamp_enable(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_set_spm_port_tstamp_enable(struct net_device *netdev,
+										   struct ifreq *ifr,
+										   struct zxdh_en_reg *reg)
 {
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-
-    if (reg->num != 2)
-    {
-        LOG_ERR("Transmit failed[len = %d]!", reg->num);
-        goto err_ret;
-    }
-
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_PORT_TSTAMP_ENABLE_SET;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port; // 0~9
-    msg.payload.mac_tstamp_msg.tx_enable = reg->data[0];
-    msg.payload.mac_tstamp_msg.rx_enable = reg->data[1];
-    LOG_INFO("phyport = %u, tx_enable: %u, rx_enable: %u\n", msg.payload.hdr_to_agt.phyport, msg.payload.mac_tstamp_msg.tx_enable, msg.payload.mac_tstamp_msg.rx_enable);
-    err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_en_set_spm_port_tstamp_enable failed, err: %d\n", err);
-        return err;
-    }
-
-    reg->num = 0;
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        goto err_ret;
-    }
-
-    return ret;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	int32_t ret = 0;
+
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	int32_t err = 0;
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+
+	if (reg->num != 2) {
+		LOG_ERR("Transmit failed[len = %d]!", reg->num);
+		goto err_ret;
+	}
+
+	msg.hdr_to_agt.op_code = AGENT_MAC_PORT_TSTAMP_ENABLE_SET;
+	msg.hdr_to_agt.phyport = en_dev->phy_port; // 0~9
+	msg.mac_tstamp_msg.tx_enable = reg->data[0];
+	msg.mac_tstamp_msg.rx_enable = reg->data[1];
+	LOG_INFO("phyport = %u, tx_enable: %u, rx_enable: %u\n",
+			 msg.hdr_to_agt.phyport, msg.mac_tstamp_msg.tx_enable,
+			 msg.mac_tstamp_msg.rx_enable);
+	err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
+	if (err != 0) {
+		LOG_ERR("zxdh_en_set_spm_port_tstamp_enable failed, err: %d\n", err);
+		return err;
+	}
+
+	reg->num = 0;
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		goto err_ret;
+	}
+
+	return ret;
 
 err_ret:
-    return -1;
+	return -1;
 }
 
-int32_t zxdh_en_get_spm_port_tstamp_enable(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_get_spm_port_tstamp_enable(struct net_device *netdev,
+										   struct ifreq *ifr,
+										   struct zxdh_en_reg *reg)
 {
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_PORT_TSTAMP_ENABLE_GET;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port; // 0~9
-    LOG_INFO("phyport = %u\n", msg.payload.hdr_to_agt.phyport);
-    err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_en_get_spm_port_tstamp_enable failed, err: %d\n", err);
-        return err;
-    }
-
-    reg->num = 2;
-    reg->data[0] = msg.reps.mac_tstamp_msg.tx_enable;
-    reg->data[1] = msg.reps.mac_tstamp_msg.rx_enable;
-    LOG_INFO("tx_enable: %u, rx_enable: %u\n", msg.reps.mac_tstamp_msg.tx_enable, msg.reps.mac_tstamp_msg.rx_enable);
-
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        goto err_ret;
-    }
-
-    return ret;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	int32_t ret = 0;
+
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	int32_t err = 0;
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+
+	msg.hdr_to_agt.op_code = AGENT_MAC_PORT_TSTAMP_ENABLE_GET;
+	msg.hdr_to_agt.phyport = en_dev->phy_port; // 0~9
+	LOG_INFO("phyport = %u\n", msg.hdr_to_agt.phyport);
+	err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
+	if (err != 0) {
+		LOG_ERR("zxdh_en_get_spm_port_tstamp_enable failed, err: %d\n", err);
+		return err;
+	}
+
+	reg->num = 2;
+	reg->data[0] = reps.mac_tstamp_msg.tx_enable;
+	reg->data[1] = reps.mac_tstamp_msg.rx_enable;
+	LOG_INFO("tx_enable: %u, rx_enable: %u\n", reps.mac_tstamp_msg.tx_enable,
+			 reps.mac_tstamp_msg.rx_enable);
+
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		goto err_ret;
+	}
+
+	return ret;
 
 err_ret:
-    return -1;
+	return -1;
 }
 
-int32_t zxdh_en_set_spm_port_tstamp_mode(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_set_spm_port_tstamp_mode(struct net_device *netdev,
+										 struct ifreq *ifr,
+										 struct zxdh_en_reg *reg)
 {
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-
-    if (reg->num != 2)
-    {
-        LOG_ERR("Transmit failed[len = %d]!", reg->num);
-        goto err_ret;
-    }
-
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_PORT_TSTAMP_MODE_SET;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;// 0~9
-    msg.payload.mac_tstamp_msg.tx_mode = reg->data[0];
-    msg.payload.mac_tstamp_msg.rx_mode = reg->data[1];
-    LOG_INFO("phyport = %u, tx_mode: %u, rx_mode: %u\n", msg.payload.hdr_to_agt.phyport, msg.payload.mac_tstamp_msg.tx_mode, msg.payload.mac_tstamp_msg.rx_mode);
-    err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_en_set_spm_port_tstamp_mode failed, err: %d\n", err);
-        return err;
-    }
-
-    reg->num = 0;
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        goto err_ret;
-    }
-
-    return ret;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	int32_t ret = 0;
+
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	int32_t err = 0;
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+
+	if (reg->num != 2) {
+		LOG_ERR("Transmit failed[len = %d]!", reg->num);
+		goto err_ret;
+	}
+
+	msg.hdr_to_agt.op_code = AGENT_MAC_PORT_TSTAMP_MODE_SET;
+	msg.hdr_to_agt.phyport = en_dev->phy_port; // 0~9
+	msg.mac_tstamp_msg.tx_mode = reg->data[0];
+	msg.mac_tstamp_msg.rx_mode = reg->data[1];
+	LOG_INFO("phyport = %u, tx_mode: %u, rx_mode: %u\n", msg.hdr_to_agt.phyport,
+			 msg.mac_tstamp_msg.tx_mode, msg.mac_tstamp_msg.rx_mode);
+	err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
+	if (err != 0) {
+		LOG_ERR("zxdh_en_set_spm_port_tstamp_mode failed, err: %d\n", err);
+		return err;
+	}
+
+	reg->num = 0;
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		goto err_ret;
+	}
+
+	return ret;
 
 err_ret:
-    return -1;
+	return -1;
 }
 
-int32_t zxdh_en_get_spm_port_tstamp_mode(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_get_spm_port_tstamp_mode(struct net_device *netdev,
+										 struct ifreq *ifr,
+										 struct zxdh_en_reg *reg)
 {
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_PORT_TSTAMP_MODE_GET;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;// 0~9
-    LOG_INFO("phyport = %u\n", msg.payload.hdr_to_agt.phyport);
-    err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_en_get_spm_port_tstamp_mode failed, err: %d\n", err);
-        return err;
-    }
-
-    reg->num = 2;
-    reg->data[0] = msg.reps.mac_tstamp_msg.tx_mode;
-    reg->data[1] = msg.reps.mac_tstamp_msg.rx_mode;
-    LOG_INFO("tx_mode: %u, rx_mode: %u\n", msg.reps.mac_tstamp_msg.tx_mode, msg.reps.mac_tstamp_msg.rx_mode);
-
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        goto err_ret;
-    }
-
-    return 0;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	int32_t err = 0;
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+
+	msg.hdr_to_agt.op_code = AGENT_MAC_PORT_TSTAMP_MODE_GET;
+	msg.hdr_to_agt.phyport = en_dev->phy_port; // 0~9
+	LOG_INFO("phyport = %u\n", msg.hdr_to_agt.phyport);
+	err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
+	if (err != 0) {
+		LOG_ERR("zxdh_en_get_spm_port_tstamp_mode failed, err: %d\n", err);
+		return err;
+	}
+
+	reg->num = 2;
+	reg->data[0] = reps.mac_tstamp_msg.tx_mode;
+	reg->data[1] = reps.mac_tstamp_msg.rx_mode;
+	LOG_INFO("tx_mode: %u, rx_mode: %u\n", reps.mac_tstamp_msg.tx_mode,
+			 reps.mac_tstamp_msg.rx_mode);
+
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		goto err_ret;
+	}
+
+	return 0;
 
 err_ret:
-    return -1;
+	return -1;
 }
 
 /* 配置时延测量功能是否打开, 维测功能 */
-int32_t zxdh_en_set_delay_statistics_enable(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_set_delay_statistics_enable(struct net_device *netdev,
+											struct ifreq *ifr,
+											struct zxdh_en_reg *reg)
 {
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    int32_t ret = 0;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	int32_t ret = 0;
 
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
 
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
 
-    if (reg->num != 1)
-    {
-        LOG_ERR("Transmit failed[len = %d]!", reg->num);
-        goto err_ret;
-    }
+	if (reg->num != 1) {
+		LOG_ERR("Transmit failed[len = %d]!", reg->num);
+		goto err_ret;
+	}
 
-    en_dev->delay_statistics_enable = reg->data[0];
-    LOG_INFO("en_dev->delay_statistics_enable = %u\n", en_dev->delay_statistics_enable);
+	en_dev->delay_statistics_enable = reg->data[0];
+	LOG_INFO("en_dev->delay_statistics_enable = %u\n",
+			 en_dev->delay_statistics_enable);
 
-    reg->num = 0;
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        goto err_ret;
-    }
+	reg->num = 0;
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		goto err_ret;
+	}
 
-    return ret;
+	return ret;
 
 err_ret:
-    return -1;
+	return -1;
 }
 
-int32_t zxdh_en_get_delay_statistics_value(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_get_delay_statistics_value(struct net_device *netdev,
+										   struct ifreq *ifr,
+										   struct zxdh_en_reg *reg)
 {
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_PORT_DELAY_VALUE_GET;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;// 0~9
-    LOG_INFO("phyport = %u\n", msg.payload.hdr_to_agt.phyport);
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_en_get_delay_statistics_value failed, ret: %d\n", ret);
-        return ret;
-    }
-
-    reg->num = 4;
-    reg->data[0] = (uint32_t)(msg.reps.delay_statistics_val.min_delay & 0xffffffff);
-    reg->data[1] = (uint32_t)((msg.reps.delay_statistics_val.min_delay >> 32) & 0xffffffff);
-    reg->data[2] = (uint32_t)(msg.reps.delay_statistics_val.max_delay & 0xffffffff);
-    reg->data[3] = (uint32_t)((msg.reps.delay_statistics_val.max_delay >> 32) & 0xffffffff);
-    LOG_INFO("delay val: min_delay: %llu, max_delay: %llu\n", msg.reps.delay_statistics_val.min_delay, \
-        msg.reps.delay_statistics_val.max_delay);
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        goto err_ret;
-    }
-
-    return 0;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	int32_t ret = 0;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+
+	msg.hdr_to_agt.op_code = AGENT_MAC_PORT_DELAY_VALUE_GET;
+	msg.hdr_to_agt.phyport = en_dev->phy_port; // 0~9
+	LOG_INFO("phyport = %u\n", msg.hdr_to_agt.phyport);
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
+	if (ret != 0) {
+		LOG_ERR("zxdh_en_get_delay_statistics_value failed, ret: %d\n", ret);
+		return ret;
+	}
+
+	reg->num = 4;
+	reg->data[0] = (uint32_t)(reps.delay_statistics_val.min_delay & 0xffffffff);
+	reg->data[1] = (uint32_t)((reps.delay_statistics_val.min_delay >> 32) &
+							  0xffffffff);
+	reg->data[2] = (uint32_t)(reps.delay_statistics_val.max_delay & 0xffffffff);
+	reg->data[3] = (uint32_t)((reps.delay_statistics_val.max_delay >> 32) &
+							  0xffffffff);
+	LOG_INFO("delay val: min_delay: %llu, max_delay: %llu\n",
+			 reps.delay_statistics_val.min_delay,
+			 reps.delay_statistics_val.max_delay);
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		goto err_ret;
+	}
+
+	return 0;
 
 err_ret:
-    return -1;
+	return -1;
 }
 
-int32_t zxdh_en_clear_delay_statistics_value(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t zxdh_en_clear_delay_statistics_value(struct net_device *netdev,
+											 struct ifreq *ifr,
+											 struct zxdh_en_reg *reg)
 {
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
-    en_dev = &en_priv->edev;
-
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_PORT_DELAY_VALUE_CLR;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;// 0~9
-    LOG_INFO("phyport = %u\n", msg.payload.hdr_to_agt.phyport);
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_en_clear_delay_statistics_value failed, ret: %d\n", ret);
-        return ret;
-    }
-
-    reg->num = 0;
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        goto err_ret;
-    }
-
-    return 0;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	int32_t ret = 0;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_priv, NULL, -EADDRNOTAVAIL, "netdev priv is null!\n");
+	en_dev = &en_priv->edev;
+
+	msg.hdr_to_agt.op_code = AGENT_MAC_PORT_DELAY_VALUE_CLR;
+	msg.hdr_to_agt.phyport = en_dev->phy_port; // 0~9
+	LOG_INFO("phyport = %u\n", msg.hdr_to_agt.phyport);
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
+	if (ret != 0) {
+		LOG_ERR("zxdh_en_clear_delay_statistics_value failed, ret: %d\n", ret);
+		return ret;
+	}
+
+	reg->num = 0;
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		goto err_ret;
+	}
+
+	return 0;
 
 err_ret:
-    return -1;
+	return -1;
 }
 
-struct zxdh_en_ptp_ioctl_table ioctl_ptp_table[] =
-{
-    {PTP_SET_CLOCK_NO,               zxdh_en_set_clock_no},
-    {PTP_ENABLE_PTP_ENCRYPTED_MSG,   zxdh_en_enable_ptp_encrypted_msg},
-    {PTP_SET_INTR_CAPTURE_TIMER,     zxdh_en_set_intr_capture_timer},
-    {PTP_SET_PP1S_SELECTION,         zxdh_en_set_pps_selection},
-    {PTP_SET_PHASE_DETECTION,        zxdh_en_set_phase_detection},
-    {PTP_GET_PD_VALUE,               zxdh_en_get_pd_value},
-    {PTP_SET_L2PTP_PORT,             zxdh_en_set_l2_ptp_port},
-    {PTP_SET_PTP_EC_ENABLE,          zxdh_en_set_ptp_tc_enable},
-    {PTP_SET_SYNCE_CLK_PORT,         zxdh_en_set_synce_recovery_port},
-    {PTP_GET_SYNCE_CLK_STATS,        zxdh_en_get_synce_clk_stats},
-    {PTP_SET_SPM_PORT_TSTAMP_ENABLE,      zxdh_en_set_spm_port_tstamp_enable},
-    {PTP_GET_SPM_PORT_TSTAMP_ENABLE,      zxdh_en_get_spm_port_tstamp_enable},
-    {PTP_SET_SPM_PORT_TSTAMP_MODE,        zxdh_en_set_spm_port_tstamp_mode},
-    {PTP_GET_SPM_PORT_TSTAMP_MODE,        zxdh_en_get_spm_port_tstamp_mode},
-    {PTP_SET_DELAY_STATISTICS_ENABLE,     zxdh_en_set_delay_statistics_enable},
-    {PTP_GET_DELAY_STATISTICS_VALUE,      zxdh_en_get_delay_statistics_value},
-    {PTP_CLR_DELAY_STATISTICS_VALUE,      zxdh_en_clear_delay_statistics_value}
+struct zxdh_en_ptp_ioctl_table ioctl_ptp_table[] = {
+	{ PTP_SET_CLOCK_NO, zxdh_en_set_clock_no },
+	{ PTP_ENABLE_PTP_ENCRYPTED_MSG, zxdh_en_enable_ptp_encrypted_msg },
+	{ PTP_SET_INTR_CAPTURE_TIMER, zxdh_en_set_intr_capture_timer },
+	{ PTP_SET_PP1S_SELECTION, zxdh_en_set_pps_selection },
+	{ PTP_SET_PHASE_DETECTION, zxdh_en_set_phase_detection },
+	{ PTP_GET_PD_VALUE, zxdh_en_get_pd_value },
+	{ PTP_SET_L2PTP_PORT, zxdh_en_set_l2_ptp_port },
+	{ PTP_SET_PTP_EC_ENABLE, zxdh_en_set_ptp_tc_enable },
+	{ PTP_SET_SYNCE_CLK_PORT, zxdh_en_set_synce_recovery_port },
+	{ PTP_GET_SYNCE_CLK_STATS, zxdh_en_get_synce_clk_stats },
+	{ PTP_SET_SPM_PORT_TSTAMP_ENABLE, zxdh_en_set_spm_port_tstamp_enable },
+	{ PTP_GET_SPM_PORT_TSTAMP_ENABLE, zxdh_en_get_spm_port_tstamp_enable },
+	{ PTP_SET_SPM_PORT_TSTAMP_MODE, zxdh_en_set_spm_port_tstamp_mode },
+	{ PTP_GET_SPM_PORT_TSTAMP_MODE, zxdh_en_get_spm_port_tstamp_mode },
+	{ PTP_SET_DELAY_STATISTICS_ENABLE, zxdh_en_set_delay_statistics_enable },
+	{ PTP_GET_DELAY_STATISTICS_VALUE, zxdh_en_get_delay_statistics_value },
+	{ PTP_CLR_DELAY_STATISTICS_VALUE, zxdh_en_clear_delay_statistics_value }
 };
 
-int32_t ptp_table_match_func(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg)
+int32_t ptp_table_match_func(struct net_device *netdev, struct ifreq *ifr,
+							 struct zxdh_en_reg *reg)
 {
-    uint32_t i = 0;
-    uint32_t ret = 0;
-    uint32_t table_size = sizeof(ioctl_ptp_table) / sizeof(struct zxdh_en_ioctl_table);
-    for(i = 0; i < table_size; i++)
-    {
-        if((reg->offset == ioctl_ptp_table[i].cmd) && (ioctl_ptp_table[i].func != NULL))
-        {
-            ret = ioctl_ptp_table[i].func(netdev, ifr, reg);
-            break;
-        }
-    }
-    return ret;
+	uint32_t i = 0;
+	uint32_t ret = 0;
+	uint32_t table_size =
+			sizeof(ioctl_ptp_table) / sizeof(struct zxdh_en_ioctl_table);
+	for (i = 0; i < table_size; i++) {
+		if ((reg->offset == ioctl_ptp_table[i].cmd) &&
+			(ioctl_ptp_table[i].func != NULL)) {
+			ret = ioctl_ptp_table[i].func(netdev, ifr, reg);
+			break;
+		}
+	}
+	return ret;
 }
 
 int32_t zxdh_en_ptp_func(struct net_device *netdev, struct ifreq *ifr)
 {
-    struct zxdh_en_reg *reg = NULL;
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_reg *reg = NULL;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
 
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
 
-    reg = kzalloc(reg_size, GFP_KERNEL);
-    CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n");
+	reg = kzalloc(reg_size, GFP_KERNEL);
+	CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n");
 
-    if (unlikely(copy_from_user(reg, ifr->ifr_ifru.ifru_data, reg_size)))
-    {
-        LOG_ERR("copy_from_user failed!\n");
-        goto err_ret;
-    }
+	if (unlikely(copy_from_user(reg, ifr->ifr_ifru.ifru_data, reg_size))) {
+		LOG_ERR("copy_from_user failed!\n");
+		goto err_ret;
+	}
 
-    if(-1 == ptp_table_match_func(netdev, ifr, reg))
-    {
-        LOG_ERR("ptp_table_match_func failed!\n");
-        goto err_ret;
-    }
+	if (-1 == ptp_table_match_func(netdev, ifr, reg)) {
+		LOG_ERR("ptp_table_match_func failed!\n");
+		goto err_ret;
+	}
 
-    kfree(reg);
-    return 0;
+	kfree(reg);
+	return 0;
 
 err_ret:
-    kfree(reg);
-    return -1;
+	kfree(reg);
+	return -1;
 }
 
 int32_t zxdh_en_pps_func(struct net_device *netdev, struct ifreq *ifr)
 {
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-    struct dh_core_dev *dh_dev = NULL;
-    struct zxdh_pf_device *pf_dev = NULL;
-    struct dh_eq_table *table = NULL;
-    struct dh_pf_eq_table *table_priv = NULL;
-    uint64_t virtaddr = 0x0;
-    struct dh_irq *expps = NULL;
-    struct dh_irq *lopps = NULL;
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-
-    en_priv = netdev_priv(netdev);
-    en_dev = &en_priv->edev;
-    dh_dev = en_dev->parent->parent;
-    pf_dev = dh_core_priv(dh_dev);
-
-    table = &dh_dev->eq_table;
-    table_priv = table->priv;
-
-    LOG_ERR("pf_dev->pci_ioremap_addr[0]: 0x%llx\n", pf_dev->pci_ioremap_addr[0]);
-
-    virtaddr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET;
-    tod_device_set_bar_virtual_addr(virtaddr, pf_dev->pcie_id);
-
-    expps = table_priv->async_irq_tbl[3];
-    lopps = table_priv->async_irq_tbl[4];
-
-    msg.payload.msg_pps.pcieid = pf_dev->pcie_id;
-    msg.payload.msg_pps.extern_pps_vector = expps->index;
-    msg.payload.msg_pps.local_pps_vector = lopps->index;
-    err = zxdh_send_command_to_specify(en_dev, MODULE_PPS, &msg, &msg);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_en_pps_func failed, err: %d\n", err);
-        return err;
-    }
-
-    return 0;
+	struct zxdh_en_priv *en_priv = NULL;
+	struct zxdh_en_device *en_dev = NULL;
+	struct dh_core_dev *dh_dev = NULL;
+	struct zxdh_pf_device *pf_dev = NULL;
+	struct dh_eq_table *table = NULL;
+	struct dh_pf_eq_table *table_priv = NULL;
+	uint64_t virtaddr = 0x0;
+	struct dh_irq *expps = NULL;
+	struct dh_irq *lopps = NULL;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	int32_t err = 0;
+
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+
+	en_priv = netdev_priv(netdev);
+	en_dev = &en_priv->edev;
+	dh_dev = en_dev->parent->parent;
+	pf_dev = dh_core_priv(dh_dev);
+
+	table = &dh_dev->eq_table;
+	table_priv = table->priv;
+
+	LOG_ERR("pf_dev->pci_ioremap_addr[0]: 0x%llx\n",
+			pf_dev->pci_ioremap_addr[0]);
+
+	virtaddr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET;
+	tod_device_set_bar_virtual_addr(virtaddr);
+
+	expps = table_priv->async_irq_tbl[3];
+	lopps = table_priv->async_irq_tbl[4];
+
+	msg.msg_pps.pcieid = pf_dev->pcie_id;
+	msg.msg_pps.extern_pps_vector = expps->index;
+	msg.msg_pps.local_pps_vector = lopps->index;
+	err = zxdh_send_command_to_specify(en_dev, MODULE_PPS, &msg, &reps);
+	if (err != 0) {
+		LOG_ERR("zxdh_en_pps_func failed, err: %d\n", err);
+		return err;
+	}
+
+	return 0;
 }
 
 #ifdef ZXDH_MSGQ
 int32_t zxdh_msgq_msg_send(struct net_device *netdev, struct ifreq *ifr)
 {
-    struct zxdh_en_device *en_dev = NULL;
-    struct msgq_dev *msgq_dev = NULL;
-    struct zxdh_en_reg *reg = NULL;
-    struct msgq_pkt_info pkt_info = {0};
-    uint32_t size = sizeof(struct zxdh_en_reg);
-    struct reps_info reps = {0};
-    uint32_t loop_cnt = 0;
-    uint32_t i = 0;
-    int32_t err = -2;
-    uint64_t start_us = 0;
-    uint64_t end_us = 0;
-
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    en_dev = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_dev, NULL, -EADDRNOTAVAIL, "en_dev is null!\n");
-    msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
-    CHECK_EQUAL_ERR(msgq_dev, NULL, -EADDRNOTAVAIL, "msgq_dev is null!\n");
-
-    reg = kzalloc(size, GFP_KERNEL);
-    CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n");
-
-    if (unlikely(copy_from_user(reg, ifr->ifr_ifru.ifru_data, size)))
-    {
-        LOG_ERR("copy_from_user failed!\n");
-        goto err_ret;
-    }
-
-    pkt_info.event_id = MODULE_DEMO;
-    pkt_info.timeout_us = 500000;
-    pkt_info.len = reg->data[0] + PRIV_HEADER_LEN;
-    pkt_info.no_reps = (reg->data[1] == 0) ? false : true;
-    loop_cnt = reg->data[2];
-    if (loop_cnt == 0)
-    {
-        goto err_ret;
-    }
-
-    if (loop_cnt > 100000000)
-    {
-        loop_cnt = 100000000;
-    }
-
-    reps.len = 14000;
-    reps.addr = vmalloc(reps.len);
-    if (reps.addr == NULL)
-    {
-        LOG_ERR("vmalloc failed!\n");
-        goto err_ret;
-    }
-
-    LOG_DEBUG("len: %d, no_reps: %d, loop_cnt: %d\n", \
-        pkt_info.len, pkt_info.no_reps, loop_cnt);
-
-    start_us = jiffies_to_usecs(jiffies);
-    for (i = 0; i < loop_cnt; ++i)
-    {
-        pkt_info.addr = kzalloc(pkt_info.len, GFP_KERNEL);
-        if(pkt_info.addr == NULL)
-        {
-            err = -3;
-            break;
-        };
-        err = zxdh_msgq_send_cmd(msgq_dev, &pkt_info, &reps);
-    }
-
-    end_us = jiffies_to_usecs(jiffies);
-    if (i != 0)
-    {
-        LOG_DEBUG("exec_time: %lld us, single_time: %lld us\n", \
-                end_us- start_us, (end_us- start_us) / i);
-    }
-
-    reg->num = -err;
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, size)))
-    {
-        LOG_ERR("copy_to_user failed!\n");
-    }
-
-    if (pkt_info.is_async && !pkt_info.no_reps)
-    {
-        usleep_range(pkt_info.timeout_us, pkt_info.timeout_us + 100);
-    }
-
-    vfree(reps.addr);
+	struct zxdh_en_device *en_dev = NULL;
+	struct msgq_dev *msgq_dev = NULL;
+	struct zxdh_en_reg *reg = NULL;
+	struct msgq_pkt_info pkt_info = { 0 };
+	uint32_t size = sizeof(struct zxdh_en_reg);
+	struct reps_info reps = { 0 };
+	uint32_t loop_cnt = 0;
+	uint32_t i = 0;
+	int32_t err = -2;
+	uint64_t start_us = 0;
+	uint64_t end_us = 0;
+
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	en_dev = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_dev, NULL, -EADDRNOTAVAIL, "en_dev is null!\n");
+	msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
+	CHECK_EQUAL_ERR(msgq_dev, NULL, -EADDRNOTAVAIL, "msgq_dev is null!\n");
+
+	reg = kzalloc(size, GFP_KERNEL);
+	CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n");
+
+	if (unlikely(copy_from_user(reg, ifr->ifr_ifru.ifru_data, size))) {
+		LOG_ERR("copy_from_user failed!\n");
+		goto err_ret;
+	}
+
+	pkt_info.event_id = MODULE_DEMO;
+	pkt_info.timeout_us = 500000;
+	pkt_info.len = reg->data[0] + PRIV_HEADER_LEN;
+	pkt_info.no_reps = (reg->data[1] == 0) ? false : true;
+	loop_cnt = reg->data[2];
+	if (loop_cnt == 0) {
+		goto err_ret;
+	}
+
+	reps.len = 14000;
+	reps.addr = vmalloc(reps.len);
+	if (reps.addr == NULL) {
+		LOG_ERR("vmalloc failed!\n");
+		goto err_ret;
+	}
+
+	LOG_DEBUG("len: %d, no_reps: %d, loop_cnt: %d\n", pkt_info.len,
+			  pkt_info.no_reps, loop_cnt);
+
+	start_us = jiffies_to_usecs(jiffies);
+	for (i = 0; i < loop_cnt; ++i) {
+		pkt_info.addr = kzalloc(pkt_info.len, GFP_KERNEL);
+		if (pkt_info.addr == NULL) {
+			err = -3;
+			break;
+		};
+		err = zxdh_msgq_send_cmd(msgq_dev, &pkt_info, &reps);
+	}
+
+	end_us = jiffies_to_usecs(jiffies);
+	if (i != 0) {
+		LOG_DEBUG("exec_time: %lld us, single_time: %lld us\n",
+				  end_us - start_us, (end_us - start_us) / i);
+	}
+
+	reg->num = err;
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, size))) {
+		LOG_ERR("copy_to_user failed!\n");
+	}
+
+	if (pkt_info.is_async && !pkt_info.no_reps) {
+		usleep_range(pkt_info.timeout_us, pkt_info.timeout_us + 100);
+	}
+
+	vfree(reps.addr);
 err_ret:
-    kfree(reg);
-    return err;
+	kfree(reg);
+	return err;
 }
 
 int32_t zxdh_msgq_dev_config(struct net_device *netdev, struct ifreq *ifr)
 {
-    uint32_t reg_size = sizeof(struct zxdh_en_reg);
-    struct zxdh_en_device *en_dev = NULL;
-    struct msgq_dev *msgq_dev = NULL;
-    struct zxdh_en_reg *reg = NULL;
-
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-    en_dev = netdev_priv(netdev);
-    CHECK_EQUAL_ERR(en_dev, NULL, -EADDRNOTAVAIL, "en_dev is null!\n");
-    msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
-    CHECK_EQUAL_ERR(msgq_dev, NULL, -EADDRNOTAVAIL, "msgq_dev is null!\n");
-
-    reg = kzalloc(reg_size, GFP_KERNEL);
-    CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n");
-
-    if (unlikely(copy_from_user(reg, ifr->ifr_ifru.ifru_data, reg_size)))
-    {
-        LOG_ERR("copy_from_user failed!\n");
-        goto err_ret;
-    }
-
-    if (reg->data[1] == MSGQ_PRINT_STA)
-    {
-        LOG_DEBUG("msgq_rx_pkts: %lld\n", msgq_dev->rq_priv->stats.packets);
-        LOG_DEBUG("msgq_rx_kicks: %lld\n", msgq_dev->rq_priv->stats.kicks);
-        LOG_DEBUG("msgq_rx_bytes: %lld\n", msgq_dev->rq_priv->stats.bytes);
-        LOG_DEBUG("msgq_rx_drops: %lld\n", msgq_dev->rq_priv->stats.drops);
-        LOG_DEBUG("msgq_rx_errs: %lld\n", msgq_dev->rq_priv->stats.xdp_drops);
-
-        LOG_DEBUG("msgq_tx_pkts: %lld\n", msgq_dev->sq_priv->stats.packets);
-        LOG_DEBUG("msgq_tx_bytes: %lld\n", msgq_dev->sq_priv->stats.bytes);
-        LOG_DEBUG("msgq_tx_kicks: %lld\n", msgq_dev->sq_priv->stats.kicks);
-        LOG_DEBUG("msgq_tx_timeouts: %lld\n", msgq_dev->sq_priv->stats.tx_timeouts);
-        LOG_DEBUG("msgq_tx_errs: %lld\n", msgq_dev->sq_priv->stats.xdp_tx_drops);
-
-        kfree(reg);
-        return 0;
-    }
-
-    msgq_dev->loopback = (reg->data[0] != 0 ? true : false);
-    msgq_dev->print_flag = reg->data[1];
-    LOG_INFO("msgq_dev->print_flag = %d\n", msgq_dev->print_flag);
-    LOG_INFO("msgq_dev->loopback = %d\n", msgq_dev->loopback);
-
-    if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size)))
-    {
-        LOG_ERR("copy_to_user failed!\n");
-        goto err_ret;
-    }
-
-    kfree(reg);
-    return 0;
+	uint32_t reg_size = sizeof(struct zxdh_en_reg);
+	struct zxdh_en_device *en_dev = NULL;
+	struct msgq_dev *msgq_dev = NULL;
+	struct zxdh_en_reg *reg = NULL;
+
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+	en_dev = netdev_priv(netdev);
+	CHECK_EQUAL_ERR(en_dev, NULL, -EADDRNOTAVAIL, "en_dev is null!\n");
+	msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
+	CHECK_EQUAL_ERR(msgq_dev, NULL, -EADDRNOTAVAIL, "msgq_dev is null!\n");
+
+	reg = kzalloc(reg_size, GFP_KERNEL);
+	CHECK_EQUAL_ERR(reg, NULL, -EADDRNOTAVAIL, "reg is null!\n");
+
+	if (unlikely(copy_from_user(reg, ifr->ifr_ifru.ifru_data, reg_size))) {
+		LOG_ERR("copy_from_user failed!\n");
+		goto err_ret;
+	}
+
+	msgq_dev->loopback = (reg->data[0] != 0 ? true : false);
+	msgq_dev->print_flag = reg->data[1];
+	LOG_INFO("msgq_dev->print_flag = %d\n", msgq_dev->print_flag);
+	LOG_INFO("msgq_dev->loopback = %d\n", msgq_dev->loopback);
+
+	if (unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, reg, reg_size))) {
+		LOG_ERR("copy_to_user failed!\n");
+		goto err_ret;
+	}
+
+	kfree(reg);
+	return 0;
 
 err_ret:
-    kfree(reg);
-    return -1;
+	kfree(reg);
+	return -1;
 }
 #endif
 
-struct zxdh_en_ioctl_table ioctl_table[] =
-{
-    {SIOCGMIIREG,                               zxdh_read_reg_cmd},
-    {SIOCSMIIREG,                               zxdh_write_reg_cmd},
-    {SIOCDEVPRIVATE_VQ_INFO,                    zxdh_get_vring_info},
-    {SIOCDEVPRIVATE_SEND_FILE_PKT,              zxdh_send_file_pkt},
+struct zxdh_en_ioctl_table ioctl_table[] = {
+	{ SIOCGMIIREG, zxdh_read_reg_cmd },
+	{ SIOCSMIIREG, zxdh_write_reg_cmd },
+	{ SIOCDEVPRIVATE_VQ_INFO, zxdh_get_vring_info },
+	{ SIOCDEVPRIVATE_SEND_FILE_PKT, zxdh_send_file_pkt },
 #ifdef ZXDH_MSGQ
-    {SIOCDEVPRIVATE_MSGQ_SNED,                  zxdh_msgq_msg_send},
-    {SIOCDEVPRIVATE_MSGQ_CONFIG,                zxdh_msgq_dev_config},
+	{ SIOCDEVPRIVATE_MSGQ_SNED, zxdh_msgq_msg_send },
+	{ SIOCDEVPRIVATE_MSGQ_CONFIG, zxdh_msgq_dev_config },
 #endif
-    {SIOCDEVPRIVATE_PTP_FUNC,                   zxdh_en_ptp_func},
-    {SIOCDEVPRIVATE_PPS_FUNC,                   zxdh_en_pps_func},
-    {SIOCDEVPRIVATE_TSN_FUNC,                   zxdh_en_tsn_func},
-    {SIOCDEVPRIVATE_DH_TOOLS,                   zxdh_tools_ioctl_dispatcher},
+	{ SIOCDEVPRIVATE_PTP_FUNC, zxdh_en_ptp_func },
+	{ SIOCDEVPRIVATE_PPS_FUNC, zxdh_en_pps_func },
+	{ SIOCDEVPRIVATE_DH_TOOLS, zxdh_tools_ioctl_dispatcher },
 };
 
-int32_t ioctl_table_match_func(struct net_device *netdev, struct ifreq *ifr, int32_t cmd,
-                               struct zxdh_en_ioctl_table *func_table, uint32_t table_size)
+int32_t ioctl_table_match_func(struct net_device *netdev, struct ifreq *ifr,
+							   int32_t cmd,
+							   struct zxdh_en_ioctl_table *func_table,
+							   uint32_t table_size)
 {
-    int32_t ret = 0;
-    uint32_t i = 0;
-
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-    for (i = 0; i < table_size; i++)
-    {
-        if ((func_table[i].cmd == cmd) && (func_table[i].func != NULL))
-        {
-            ret = func_table[i].func(netdev, ifr);
-            break;
-        }
-    }
-
-    return ret;
+	int32_t ret = 0;
+	uint32_t i = 0;
+
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+	for (i = 0; i < table_size; i++) {
+		if ((func_table[i].cmd == cmd) && (func_table[i].func != NULL)) {
+			ret = func_table[i].func(netdev, ifr);
+			break;
+		}
+	}
+
+	return ret;
 }
 
 int32_t zxdh_en_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
 {
-    uint32_t table_size = sizeof(ioctl_table) / sizeof(struct zxdh_en_ioctl_table);
+	uint32_t table_size =
+			sizeof(ioctl_table) / sizeof(struct zxdh_en_ioctl_table);
 
-    return ioctl_table_match_func(netdev, ifr, cmd, ioctl_table, table_size);
+	return ioctl_table_match_func(netdev, ifr, cmd, ioctl_table, table_size);
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/en_ioctl.h b/src/net/drivers/net/ethernet/dinghai/en_aux/en_ioctl.h
index 1b2e5c478750bf7212ea3700785af553303e5017..9ecf2d1b0a75b13fb88ee6090e78955e5112ef22 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/en_ioctl.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/en_ioctl.h
@@ -7,33 +7,32 @@ extern "C" {
 
 #include "../en_aux.h"
 
-#define SIOCDEVPRIVATE_WRITE_MAC     (SIOCDEVPRIVATE + 1)
-#define SIOCDEVPRIVATE_VQ_INFO       (SIOCDEVPRIVATE + 2)
-#define SIOCDEVPRIVATE_MSGQ_SNED     (SIOCDEVPRIVATE + 3)
-#define SIOCDEVPRIVATE_MSGQ_CONFIG   (SIOCDEVPRIVATE + 4)
+#define SIOCDEVPRIVATE_WRITE_MAC (SIOCDEVPRIVATE + 1)
+#define SIOCDEVPRIVATE_VQ_INFO (SIOCDEVPRIVATE + 2)
+#define SIOCDEVPRIVATE_MSGQ_SNED (SIOCDEVPRIVATE + 3)
+#define SIOCDEVPRIVATE_MSGQ_CONFIG (SIOCDEVPRIVATE + 4)
 #define SIOCDEVPRIVATE_SEND_FILE_PKT (SIOCDEVPRIVATE + 6)
-#define SIOCDEVPRIVATE_PTP_FUNC      (SIOCDEVPRIVATE + 9)
-#define SIOCDEVPRIVATE_PPS_FUNC      (SIOCDEVPRIVATE + 10)
-#define SIOCDEVPRIVATE_TSN_FUNC      (SIOCDEVPRIVATE + 11)
-#define SIOCDEVPRIVATE_DH_TOOLS      (SIOCDEVPRIVATE + 13)
-
-#define PTP_SET_CLOCK_NO              (0)
-#define PTP_ENABLE_PTP_ENCRYPTED_MSG  (1)
-#define PTP_SET_INTR_CAPTURE_TIMER    (2)
-#define PTP_SET_PP1S_SELECTION        (3)
-#define PTP_SET_PHASE_DETECTION       (4)
-#define PTP_GET_PD_VALUE              (5)
-#define PTP_SET_L2PTP_PORT            (6)
-#define PTP_SET_PTP_EC_ENABLE         (7)
-#define PTP_SET_SYNCE_CLK_PORT        (8)
-#define PTP_GET_SYNCE_CLK_STATS       (9)
-#define PTP_SET_SPM_PORT_TSTAMP_ENABLE     (10)
-#define PTP_GET_SPM_PORT_TSTAMP_ENABLE     (11)
-#define PTP_SET_SPM_PORT_TSTAMP_MODE       (12)
-#define PTP_GET_SPM_PORT_TSTAMP_MODE       (13)
-#define PTP_SET_DELAY_STATISTICS_ENABLE    (14)
-#define PTP_GET_DELAY_STATISTICS_VALUE     (15)
-#define PTP_CLR_DELAY_STATISTICS_VALUE     (16)
+#define SIOCDEVPRIVATE_PTP_FUNC (SIOCDEVPRIVATE + 9)
+#define SIOCDEVPRIVATE_PPS_FUNC (SIOCDEVPRIVATE + 10)
+#define SIOCDEVPRIVATE_DH_TOOLS (SIOCDEVPRIVATE + 13)
+
+#define PTP_SET_CLOCK_NO (0)
+#define PTP_ENABLE_PTP_ENCRYPTED_MSG (1)
+#define PTP_SET_INTR_CAPTURE_TIMER (2)
+#define PTP_SET_PP1S_SELECTION (3)
+#define PTP_SET_PHASE_DETECTION (4)
+#define PTP_GET_PD_VALUE (5)
+#define PTP_SET_L2PTP_PORT (6)
+#define PTP_SET_PTP_EC_ENABLE (7)
+#define PTP_SET_SYNCE_CLK_PORT (8)
+#define PTP_GET_SYNCE_CLK_STATS (9)
+#define PTP_SET_SPM_PORT_TSTAMP_ENABLE (10)
+#define PTP_GET_SPM_PORT_TSTAMP_ENABLE (11)
+#define PTP_SET_SPM_PORT_TSTAMP_MODE (12)
+#define PTP_GET_SPM_PORT_TSTAMP_MODE (13)
+#define PTP_SET_DELAY_STATISTICS_ENABLE (14)
+#define PTP_GET_DELAY_STATISTICS_VALUE (15)
+#define PTP_CLR_DELAY_STATISTICS_VALUE (16)
 
 #define PI_HDR_MAX_NUM 128
 #define GET_LOW32 0x00000000ffffffff
@@ -42,52 +41,47 @@ extern "C" {
 #define PKT_PRINT_LINE_LEN 16
 #define PKT_PRINT_LEN_MAX (16 * 1024)
 
-#define CONFIG_RISC_PCS_LOOPB_OPCODE    13
-#define CONFIG_RISC_PCS_NORMAL_OPCODE   14
+#define CONFIG_RISC_PCS_LOOPB_OPCODE 13
+#define CONFIG_RISC_PCS_NORMAL_OPCODE 14
 
-#define MSG_MODULE_DEBUG_RISC   20
+#define MSG_MODULE_DEBUG_RISC 20
 
 #define MAX_ACCESS_NUM 500
-struct zxdh_en_reg
-{
-    uint32_t offset;
-    uint32_t num;
-    uint32_t data[MAX_ACCESS_NUM];
+struct zxdh_en_reg {
+	uint32_t offset;
+	uint32_t num;
+	uint32_t data[MAX_ACCESS_NUM];
 };
 
-struct risc_config_mac_msg
-{
-    uint8_t op_code;
-    uint8_t phyport;
-    uint8_t spm_speed;
-    uint8_t spm_fec;
-    uint8_t loop_enable;
+struct risc_config_mac_msg {
+	uint8_t op_code;
+	uint8_t phyport;
+	uint8_t spm_speed;
+	uint8_t spm_fec;
+	uint8_t loop_enable;
 };
 
-struct risc_config_userspace
-{
-    uint8_t op_code;
-    uint8_t arg_num;
-    uint8_t filestr_size;
-    uint8_t file[100];
+struct risc_config_userspace {
+	uint8_t op_code;
+	uint8_t arg_num;
+	uint8_t filestr_size;
+	uint8_t file[100];
 };
 
-struct data_packet
-{
-    void *buf;
-    uint32_t buf_size;
+struct data_packet {
+	void *buf;
+	uint32_t buf_size;
 };
 
-struct zxdh_en_ioctl_table
-{
-    int32_t cmd;
-    int32_t (*func)(struct net_device *netdev, struct ifreq *ifr);
+struct zxdh_en_ioctl_table {
+	int32_t cmd;
+	int32_t (*func)(struct net_device *netdev, struct ifreq *ifr);
 };
 
-struct zxdh_en_ptp_ioctl_table
-{
-    int32_t cmd;
-    int32_t (*func)(struct net_device *netdev, struct ifreq *ifr, struct zxdh_en_reg *reg);
+struct zxdh_en_ptp_ioctl_table {
+	int32_t cmd;
+	int32_t (*func)(struct net_device *netdev, struct ifreq *ifr,
+					struct zxdh_en_reg *reg);
 };
 
 int32_t print_data(uint8_t *data, uint32_t len);
@@ -98,4 +92,3 @@ int32_t zxdh_en_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
 #endif
 
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/eq.c b/src/net/drivers/net/ethernet/dinghai/en_aux/eq.c
index e63fb8dfffac94d17bc4704c22e6384d083d5d63..36fbc26990cb604d23e6379c21dcefdbf73c129b 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/eq.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/eq.c
@@ -3,331 +3,326 @@
 #include <linux/dinghai/dh_cmd.h>
 #include "eq.h"
 
-static int32_t dh_eq_async_link_info_int_bond_pf(struct notifier_block *nb, unsigned long action, void *data)
+static int32_t dh_eq_async_link_info_int_bond_pf(struct notifier_block *nb,
+												 unsigned long action,
+												 void *data)
 {
-    struct dh_eq_async *eq_link_info_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)eq_link_info_async->priv;
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint8_t link_up = 0;
-    uint8_t link_info = 0;
-    uint8_t bit_value = 0;
-
-    if (en_dev == NULL)
-    {
-        LOG_ERR("null ptr\n");
-        return -1;
-    }
-
-    if(!en_dev->ops->is_bond(en_dev->parent))
-    {
-        LOG_INFO("isn't bond_pf exit\n");
-        return 0;
-    }
-
-    //读取state寄存器中第en_dev->link_check_bit位的值
-    en_dev->ops->get_link_info_from_vqm(en_dev->parent, &link_info);
-    bit_value = (link_info >> en_dev->link_check_bit) & 0x01;
-    LOG_INFO("[aux level] netdev:%s read VQM[0x%x]: link_check_bit[%d]-bit_value[%d]\n", en_dev->netdev->name, link_info, en_dev->link_check_bit, bit_value);
-    link_up |= bit_value;
-
-    en_dev->link_up = link_up;
-    queue_work(en_priv->events->wq, &en_dev->link_info_irq_update_np_work);
-
-    if(link_up == 0)
-    {
-        netif_carrier_off(en_dev->netdev);
-        en_dev->speed = SPEED_UNKNOWN;
-        en_dev->duplex = DUPLEX_UNKNOWN;
-    }
-    else
-    {
-        netif_carrier_on(en_dev->netdev);
-        queue_work(en_priv->events->wq, &en_dev->link_info_irq_process_work);
-    }
-
-    return 0;
+	struct dh_eq_async *eq_link_info_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct zxdh_en_priv *en_priv =
+			(struct zxdh_en_priv *)eq_link_info_async->priv;
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint8_t link_up = 0;
+	uint8_t link_info = 0;
+	uint8_t bit_value = 0;
+
+	if (en_dev == NULL) {
+		LOG_ERR("null ptr\n");
+		return -1;
+	}
+
+	if (!en_dev->ops->is_bond(en_dev->parent)) {
+		LOG_INFO("isn't bond_pf exit\n");
+		return 0;
+	}
+
+	//读取state寄存器中第en_dev->link_check_bit位的值
+	en_dev->ops->get_link_info_from_vqm(en_dev->parent, &link_info);
+	bit_value = (link_info >> en_dev->link_check_bit) & 0x01;
+	LOG_INFO("[aux level] netdev:%s read VQM[0x%x]: "
+			 "link_check_bit[%d]-bit_value[%d]\n",
+			 en_dev->netdev->name, link_info, en_dev->link_check_bit,
+			 bit_value);
+	link_up |= bit_value;
+
+	en_dev->link_up = link_up;
+	queue_work(en_priv->events->wq, &en_dev->link_info_irq_update_np_work);
+
+	if (link_up == 0) {
+		netif_carrier_off(en_dev->netdev);
+		en_dev->speed = SPEED_UNKNOWN;
+		en_dev->duplex = DUPLEX_UNKNOWN;
+	} else {
+		netif_carrier_on(en_dev->netdev);
+		queue_work(en_priv->events->wq, &en_dev->link_info_irq_process_work);
+	}
+
+	return 0;
 }
 
-static int32_t dh_eq_async_link_info_int(struct notifier_block *nb, unsigned long action, void *data)
+static int32_t dh_eq_async_link_info_int(struct notifier_block *nb,
+										 unsigned long action, void *data)
 {
-    struct dh_eq_async *eq_link_info_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)eq_link_info_async->priv;
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint8_t link_up = 0;
-    uint8_t link_info = 0;
-    uint8_t phyport_val = 0;
-
-    //判断是否为bond_pf
-    if (en_dev == NULL)
-    {
-        LOG_ERR("null ptr\n");
-        return -1;
-    }
-
-    if(en_dev->ops->is_bond(en_dev->parent))
-    {
-        LOG_INFO("is bond_pf, exit\n");
-        return 0;
-    }
-
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF && (en_dev->device_id==0x8042))
-    {
-        //调用读取state后四位获取phoport、读取前四位，获取link_up信息
-        en_dev->ops->get_link_info_from_vqm(en_dev->parent, &link_info);
-        link_up = link_info & 0x0F;
-        phyport_val = (link_info >> 4) & 0x0F;
-        LOG_INFO("[bond_vf netdev %s] read VQM[0x%x]: phyport[0x%x] link_up[%d]\n", en_dev->netdev->name, link_info, phyport_val, link_up);
-        en_dev->phy_port = phyport_val;
-    }
-    else
-    {
-        en_dev->ops->get_link_info_from_vqm(en_dev->parent, &link_up);
-    }
-
-    en_dev->link_up = link_up;
-    queue_work(en_priv->events->wq, &en_dev->link_info_irq_update_np_work);
-    if(link_up == 0)
-    {
-        en_dev->ops->set_pf_link_up(en_dev->parent, FALSE);
-        netif_carrier_off(en_dev->netdev);
-        en_dev->speed = SPEED_UNKNOWN;
-        en_dev->duplex = DUPLEX_UNKNOWN;
-    }
-    else
-    {
-        en_dev->ops->set_pf_link_up(en_dev->parent, TRUE);
-        netif_carrier_on(en_dev->netdev);
-        queue_work(en_priv->events->wq, &en_dev->link_info_irq_process_work);
-    }
-
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        LOG_INFO("pf update all vf\n");
-        queue_work(en_priv->events->wq, &en_dev->link_info_irq_update_vf_work);
-    }
-    return 0;
+	struct dh_eq_async *eq_link_info_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct zxdh_en_priv *en_priv =
+			(struct zxdh_en_priv *)eq_link_info_async->priv;
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint8_t link_up = 0;
+	uint8_t link_info = 0;
+	uint8_t phyport_val = 0;
+
+	//判断是否为bond_pf
+	if (en_dev == NULL) {
+		LOG_ERR("null ptr\n");
+		return -1;
+	}
+
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		LOG_INFO("is bond_pf, exit\n");
+		return 0;
+	}
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF &&
+		(en_dev->device_id == 0x8042)) {
+		//调用读取state后四位获取phoport、读取前四位，获取link_up信息
+		en_dev->ops->get_link_info_from_vqm(en_dev->parent, &link_info);
+		link_up = link_info & 0x0F;
+		phyport_val = (link_info >> 4) & 0x0F;
+		LOG_INFO(
+				"[bond_vf netdev %s] read VQM[0x%x]: phyport[0x%x] link_up[%d]\n",
+				en_dev->netdev->name, link_info, phyport_val, link_up);
+		en_dev->phy_port = phyport_val;
+	} else {
+		en_dev->ops->get_link_info_from_vqm(en_dev->parent, &link_up);
+	}
+
+	en_dev->link_up = link_up;
+	queue_work(en_priv->events->wq, &en_dev->link_info_irq_update_np_work);
+	if (link_up == 0) {
+		en_dev->ops->set_pf_link_up(en_dev->parent, FALSE);
+		netif_carrier_off(en_dev->netdev);
+		en_dev->speed = SPEED_UNKNOWN;
+		en_dev->duplex = DUPLEX_UNKNOWN;
+	} else {
+		en_dev->ops->set_pf_link_up(en_dev->parent, TRUE);
+		netif_carrier_on(en_dev->netdev);
+		queue_work(en_priv->events->wq, &en_dev->link_info_irq_process_work);
+	}
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		LOG_INFO("pf update all vf\n");
+		queue_work(en_priv->events->wq, &en_dev->link_info_irq_update_vf_work);
+	}
+	return 0;
 }
 
-static int32_t dh_eq_async_riscv_int(struct notifier_block *nb, unsigned long action, void *data)
+static int32_t dh_eq_async_riscv_int(struct notifier_block *nb,
+									 unsigned long action, void *data)
 {
-    struct dh_eq_async * eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)eq_riscv_async->priv;
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct dh_eq_table *eq_table = &en_priv->eq_table;
-    struct dh_events *events = en_priv->events;
-    struct dh_event_nb *event_nb = NULL;
-    uint64_t virt_addr = 0;
-    int32_t event_type = 0;
-    uint16_t event_idx = 0;
-    uint16_t i = 0;
-
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-    {
-        return 0;
-    }
-
-    virt_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0) + ZXDH_BAR_MSG_OFFSET;
-    event_idx = zxdh_get_event_id(virt_addr, MSG_CHAN_END_RISC, MSG_CHAN_END_PF);
-    event_type = dh_eq_event_type_get(event_idx);
-    LOG_INFO("------------- event_idx: %d, event_type: %d------------\n", event_idx, event_type);
-
-    if(events == NULL)
-    {
-        LOG_ERR("riscv_irq trigger, events is null\n");
-        return 0;
-    }
-
-    for (i = 0; i < events->evt_num; i++)
-    {
-        event_nb = &events->notifiers[i];
-
-        if (event_type == event_nb->nb.event_type)
-        {
-            LOG_INFO("en_aux async riscv irq_handler called\n");
-            atomic_notifier_call_chain(&eq_table->nh[event_type], event_type, NULL);
-            return 0;
-        }
-    }
-
-    return 0;
+	struct dh_eq_async *eq_riscv_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)eq_riscv_async->priv;
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct dh_eq_table *eq_table = &en_priv->eq_table;
+	struct dh_events *events = en_priv->events;
+	struct dh_event_nb *event_nb = NULL;
+	uint64_t virt_addr = 0;
+	int32_t event_type = 0;
+	uint16_t event_idx = 0;
+	uint16_t i = 0;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		return 0;
+	}
+
+	virt_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0) +
+				ZXDH_BAR_MSG_OFFSET;
+	event_idx =
+			zxdh_get_event_id(virt_addr, MSG_CHAN_END_RISC, MSG_CHAN_END_PF);
+	event_type = dh_eq_event_type_get(event_idx);
+	LOG_INFO("------------- event_idx: %d, event_type: %d------------\n",
+			 event_idx, event_type);
+
+	if (events == NULL) {
+		LOG_ERR("riscv_irq trigger, events is null\n");
+		return 0;
+	}
+
+	for (i = 0; i < events->evt_num; i++) {
+		event_nb = &events->notifiers[i];
+
+		if (event_type == event_nb->nb.event_type) {
+			LOG_INFO("en_aux async riscv irq_handler called\n");
+			atomic_notifier_call_chain(&eq_table->nh[event_type], event_type,
+									   NULL);
+			return 0;
+		}
+	}
+
+	return 0;
 }
 
-static int32_t dh_eq_async_pf_int(struct notifier_block *nb, unsigned long action, void *data)
+static int32_t dh_eq_async_pf_int(struct notifier_block *nb,
+								  unsigned long action, void *data)
 {
-    struct dh_eq_async * eq_pf_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)eq_pf_async->priv;
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct dh_eq_table *eq_table = &en_priv->eq_table;
-    struct dh_events *events = en_priv->events;
-    struct dh_event_nb *event_nb = NULL;
-    uint64_t virt_addr = 0;
-    int32_t event_type = 0;
-    uint16_t event_idx = 0;
-    uint16_t i = 0;
-
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        return 0;
-    }
-
-    virt_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0) + ZXDH_BAR_MSG_OFFSET + ZXDH_BAR_PFVF_MSG_OFFSET;
-    event_idx = zxdh_get_event_id(virt_addr, MSG_CHAN_END_PF, MSG_CHAN_END_VF);
-    event_type = dh_eq_event_type_get(event_idx);
-    LOG_INFO("------------- event_idx: %d, event_type: %d------------\n", event_idx, event_type);
-
-    for (i = 0; i < events->evt_num; i++)
-    {
-        event_nb = &events->notifiers[i];
-
-        if (event_type == event_nb->nb.event_type)
-        {
-            LOG_INFO("en_aux async pf irq_handler called\n");
-            atomic_notifier_call_chain(&eq_table->nh[event_type], event_type, NULL);
-            return 0;
-        }
-    }
-
-    return 0;
+	struct dh_eq_async *eq_pf_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)eq_pf_async->priv;
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct dh_eq_table *eq_table = &en_priv->eq_table;
+	struct dh_events *events = en_priv->events;
+	struct dh_event_nb *event_nb = NULL;
+	uint64_t virt_addr = 0;
+	int32_t event_type = 0;
+	uint16_t event_idx = 0;
+	uint16_t i = 0;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		return 0;
+	}
+
+	virt_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0) +
+				ZXDH_BAR_MSG_OFFSET + ZXDH_BAR_PFVF_MSG_OFFSET;
+	event_idx = zxdh_get_event_id(virt_addr, MSG_CHAN_END_PF, MSG_CHAN_END_VF);
+	event_type = dh_eq_event_type_get(event_idx);
+	LOG_INFO("------------- event_idx: %d, event_type: %d------------\n",
+			 event_idx, event_type);
+
+	for (i = 0; i < events->evt_num; i++) {
+		event_nb = &events->notifiers[i];
+
+		if (event_type == event_nb->nb.event_type) {
+			LOG_INFO("en_aux async pf irq_handler called\n");
+			atomic_notifier_call_chain(&eq_table->nh[event_type], event_type,
+									   NULL);
+			return 0;
+		}
+	}
+
+	return 0;
 }
 
-struct dh_aux_async_eq_table
-{
-    char name[64];
-    notifier_fn_t async_int;
+struct dh_aux_async_eq_table {
+	char name[64];
+	notifier_fn_t async_int;
 };
 
-static struct dh_aux_async_eq_table dh_aux_async_eq_tbl[] =
-{
-    {"riscv", dh_eq_async_riscv_int},
-    {"pf", dh_eq_async_pf_int},
-    {"link_info", dh_eq_async_link_info_int},
-    {"link_info", dh_eq_async_link_info_int_bond_pf},
+static struct dh_aux_async_eq_table dh_aux_async_eq_tbl[] = {
+	{ "riscv", dh_eq_async_riscv_int },
+	{ "pf", dh_eq_async_pf_int },
+	{ "link_info", dh_eq_async_link_info_int },
+	{ "link_info", dh_eq_async_link_info_int_bond_pf },
 };
 
-static int32_t dh_aux_setup_async_eq(struct zxdh_en_priv *en_priv, \
-                            struct dh_eq_async *eq, const char *name, \
-                            notifier_fn_t call)
+static int32_t dh_aux_setup_async_eq(struct zxdh_en_priv *en_priv,
+									 struct dh_eq_async *eq, const char *name,
+									 notifier_fn_t call)
 {
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t err = 0;
-
-    spin_lock_init(&eq->lock);//unused
-    eq->priv = en_priv;
-    eq->irq_nb.notifier_call = call;
-    err = en_dev->ops->async_eq_enable(en_dev->parent, eq, name, true);
-    if (err != 0)
-    {
-        LOG_ERR("failed to enable %s EQ %d\n", name, err);
-    }
-
-    return err;
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t err = 0;
+
+	spin_lock_init(&eq->lock); // unused
+	eq->priv = en_priv;
+	eq->irq_nb.notifier_call = call;
+	err = en_dev->ops->async_eq_enable(en_dev->parent, eq, name, true);
+	if (err != 0) {
+		LOG_ERR("failed to enable %s EQ %d\n", name, err);
+	}
+
+	return err;
 }
 
-static void cleanup_async_eq(struct zxdh_en_priv *en_priv, struct dh_eq_async *eq, const char *name)
+static void cleanup_async_eq(struct zxdh_en_priv *en_priv,
+							 struct dh_eq_async *eq, const char *name)
 {
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t err = 0;
-
-    err = en_dev->ops->async_eq_enable(en_dev->parent, eq, name, false);
-    if (err != 0)
-    {
-        LOG_ERR("failed to disable %s EQ %d\n", name, err);
-    }
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t err = 0;
+
+	err = en_dev->ops->async_eq_enable(en_dev->parent, eq, name, false);
+	if (err != 0) {
+		LOG_ERR("failed to disable %s EQ %d\n", name, err);
+	}
 }
 
 static void destroy_async_eqs(struct zxdh_en_priv *en_priv)
 {
-    struct dh_eq_table *table = &en_priv->eq_table;
-    struct dh_aux_eq_table *table_priv = table->priv;
-    int32_t i = 0;
-
-    for (i = 0; i < ZXDH_AUX_ASYNC_EQ_NUM; ++i)
-    {
-        cleanup_async_eq(en_priv, &table_priv->async_eq_tbl[i], dh_aux_async_eq_tbl[i].name);
-    }
+	struct dh_eq_table *table = &en_priv->eq_table;
+	struct dh_aux_eq_table *table_priv = table->priv;
+	int32_t i = 0;
+
+	for (i = 0; i < ZXDH_AUX_ASYNC_EQ_NUM; ++i) {
+		cleanup_async_eq(en_priv, &table_priv->async_eq_tbl[i],
+						 dh_aux_async_eq_tbl[i].name);
+	}
 }
 
 void dh_aux_eq_table_destroy(struct zxdh_en_priv *en_priv)
 {
-    destroy_async_eqs(en_priv);
+	destroy_async_eqs(en_priv);
 }
 
 void dh_aux_eq_table_cleanup(struct zxdh_en_priv *en_priv)
 {
-    kvfree(en_priv->eq_table.priv);
+	kvfree(en_priv->eq_table.priv);
 }
 
 int32_t dh_aux_eq_table_init(struct zxdh_en_priv *en_priv)
 {
-    struct dh_eq_table *eq_table;
-    struct dh_aux_eq_table *table_priv = NULL;
-    int32_t err = 0;
-    uint32_t i = 0;
+	struct dh_eq_table *eq_table;
+	struct dh_aux_eq_table *table_priv = NULL;
+	int32_t err = 0;
+	uint32_t i = 0;
 
-    eq_table = &en_priv->eq_table;
+	eq_table = &en_priv->eq_table;
 
-    table_priv = kvzalloc(sizeof(*table_priv), GFP_KERNEL);
-    if (unlikely(table_priv == NULL))
-    {
-        LOG_ERR("dh_aux_eq_table kvzalloc failed\n");
-        err = -ENOMEM;
-        goto err_table_priv;
-    }
+	table_priv = kvzalloc(sizeof(*table_priv), GFP_KERNEL);
+	if (unlikely(table_priv == NULL)) {
+		err = -ENOMEM;
+		goto err_table_priv;
+	}
 
-    eq_table->priv = table_priv;
+	eq_table->priv = table_priv;
 
-    mutex_init(&eq_table->lock);
-    for (i = 0; i < DH_EVENT_TYPE_MAX; i++)
-    {
-        ATOMIC_INIT_NOTIFIER_HEAD(&eq_table->nh[i]);
-    }
+	mutex_init(&eq_table->lock);
+	for (i = 0; i < DH_EVENT_TYPE_MAX; i++) {
+		ATOMIC_INIT_NOTIFIER_HEAD(&eq_table->nh[i]);
+	}
 
-    eq_table->irq_table = NULL;
+	eq_table->irq_table = NULL;
 
-    return 0;
+	return 0;
 
 err_table_priv:
-    return err;
+	return err;
 }
 
 static int32_t create_async_eqs(struct zxdh_en_priv *en_priv)
 {
-    struct dh_eq_table *eq_table = &en_priv->eq_table;
-    struct dh_aux_eq_table *table_priv = eq_table->priv;
-    int32_t err = 0;
-    int32_t i = 0;
-    int32_t j = 0;
-
-    for (i = 0; i < ZXDH_AUX_ASYNC_EQ_NUM; ++i)
-    {
-        err = dh_aux_setup_async_eq(en_priv, &table_priv->async_eq_tbl[i], \
-                dh_aux_async_eq_tbl[i].name, dh_aux_async_eq_tbl[i].async_int);
-        if (err != 0)
-        {
-            LOG_ERR("Failed to setup aux_async_eq_tbl[%d]\n", i);
-            goto err_setup_async_eq;
-        }
-    }
-
-    return err;
+	struct dh_eq_table *eq_table = &en_priv->eq_table;
+	struct dh_aux_eq_table *table_priv = eq_table->priv;
+	int32_t err = 0;
+	int32_t i = 0;
+	int32_t j = 0;
+
+	for (i = 0; i < ZXDH_AUX_ASYNC_EQ_NUM; ++i) {
+		err = dh_aux_setup_async_eq(en_priv, &table_priv->async_eq_tbl[i],
+									dh_aux_async_eq_tbl[i].name,
+									dh_aux_async_eq_tbl[i].async_int);
+		if (err != 0) {
+			LOG_ERR("Failed to setup aux_async_eq_tbl[%d]\n", i);
+			goto err_setup_async_eq;
+		}
+	}
+
+	return err;
 
 err_setup_async_eq:
-    for (j = 0; j < i; ++j)
-    {
-        cleanup_async_eq(en_priv, &table_priv->async_eq_tbl[j], dh_aux_async_eq_tbl[j].name);
-    }
-    return err;
+	for (j = 0; j < i; ++j) {
+		cleanup_async_eq(en_priv, &table_priv->async_eq_tbl[j],
+						 dh_aux_async_eq_tbl[j].name);
+	}
+	return err;
 }
 
 int32_t dh_aux_eq_table_create(struct zxdh_en_priv *en_priv)
 {
-    int32_t err = 0;
+	int32_t err = 0;
 
-    err = create_async_eqs(en_priv);
-    if (err != 0)
-    {
-        LOG_ERR("Failed to create async EQs\n");
-    }
+	err = create_async_eqs(en_priv);
+	if (err != 0) {
+		LOG_ERR("Failed to create async EQs\n");
+	}
 
-    return err;
+	return err;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/eq.h b/src/net/drivers/net/ethernet/dinghai/en_aux/eq.h
index c9d24443b379b440491b742fbc0ec95e6d8e62d1..9c9c53502c681327e7b97153a31ba889e8b3ba11 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/eq.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/eq.h
@@ -9,7 +9,7 @@ extern "C" {
 
 #define ZXDH_AUX_ASYNC_EQ_NUM 4
 struct dh_aux_eq_table {
-    struct dh_eq_async async_eq_tbl[ZXDH_AUX_ASYNC_EQ_NUM];
+	struct dh_eq_async async_eq_tbl[ZXDH_AUX_ASYNC_EQ_NUM];
 };
 
 int32_t dh_aux_eq_table_init(struct zxdh_en_priv *en_priv);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/events.c b/src/net/drivers/net/ethernet/dinghai/en_aux/events.c
index 1dd5fee9cb51babb5b7a8d8e5672536a049d8bcf..db231f375afa3af9c6cfa29396dfeee3f8a6429e 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/events.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/events.c
@@ -1,824 +1,790 @@
-#include <linux/gfp.h>
-#include <linux/slab.h>
-#include <linux/notifier.h>
-#include <linux/dinghai/events.h>
-#include <linux/dinghai/dh_cmd.h>
-#include <linux/workqueue.h>
-#include <linux/kernel.h>
-#include "events.h"
-#include "en_cmd.h"
-#include "../msg_common.h"
-#include "../en_np/table/include/dpp_tbl_api.h"
-#include "../zxdh_tools/zxdh_tools_netlink.h"
-#include "dcbnl/en_dcbnl_api.h"
-#include "zxic_common.h"
-#include <linux/timer.h>
-#include <linux/rtc.h>
-#include <linux/if_ether.h>
-#include <linux/in6.h>
-#include <net/addrconf.h>
-#include <linux/if_vlan.h>       // 对于VLAN设备
-#include <linux/if_bonding.h>    // 对于bonding设备
-#include <net/bonding.h>
-
-static int32_t pf2vf_notifier(struct notifier_block *, unsigned long, void *);
-static int32_t riscv2aux_notifier(struct notifier_block *, unsigned long, void *);
-
-void rx_mode_set_handler(struct work_struct *work);
-
-static struct dh_nb aux_events[] = {
-    {.nb.notifier_call = pf2vf_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_PF_TO_VF},
-    {.nb.notifier_call = riscv2aux_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_RISCV_TO_AUX},
-};
-
-static int32_t do_pf_vf_inet6_update_mac_to_np(struct zxdh_en_device *en_dev, const struct in6_addr *ipv6_addr, unsigned long action)
-{
-    int32_t ret = 0;
-    struct in6_addr sol_addr={0};
-    uint8_t mcast_mac[ETH_ALEN];
-
-    // 打印IPv6地址，使用%pI6c格式化IPv6地址，确保正确显示
-    LOG_INFO("IPv6 address changed on interface %s, %s address: %pI6c\n",
-           en_dev->netdev->name, (action == 1) ? "add" : (action == 2) ? "del" : "unknown action with", ipv6_addr);
-    // Calculate the multicast MAC address from the IPv6 address
-    addrconf_addr_solict_mult(ipv6_addr, &sol_addr);
-    ipv6_eth_mc_map(&sol_addr, mcast_mac);
-    LOG_INFO("Multicast MAC Address: %pM\n", mcast_mac);
-
-    switch (action) {
-        case NETDEV_UP:
-        {
-            ret = zxdh_ip6mac_add(en_dev, ipv6_addr->s6_addr32, mcast_mac);
-            if (ret != 0)
-            {
-                LOG_ERR("zxdh_ip6mac_add failed");
-            }
-            break;
-        }
-        case NETDEV_DOWN:
-        {
-            ret = zxdh_ip6mac_del(en_dev, ipv6_addr->s6_addr32, mcast_mac);
-            if (ret != 0)
-            {
-                LOG_ERR("zxdh_ip6mac_del failed");
-            }
-            break;
-        }
-        default:
-            break;
-    }
-    return ret;
-}
-
-static int32_t do_bond_master_inet6_update_mac_to_np(struct net_device *notifier_dev, const struct in6_addr *ipv6_addr, struct zxdh_en_device *en_dev, unsigned long action)
-{
-    int32_t ret = 0;
-    struct list_head *iter = NULL;
-    struct slave *slave_dev = NULL;
-    struct bonding *bond = netdev_priv(notifier_dev);
-
-    // 遍历所有slave设备
-    if (!bond_has_slaves(bond))
-    {
-        LOG_INFO("Bond device %s don't have slave\n", notifier_dev->name);
-        return 0;
-    }
-
-    bond_for_each_slave(bond, slave_dev, iter)
-    {
-        if (strcmp(en_dev->netdev->name, slave_dev->dev->name) != 0)
-        {
-            continue;
-        }
-        LOG_INFO("Bond device %s have slave device: %s\n", notifier_dev->name, slave_dev->dev->name);
-        ret = do_pf_vf_inet6_update_mac_to_np(en_dev, ipv6_addr, action);
-        if (ret != 0)
-        {
-            return ret;
-        }
-    }
-    return 0;
-}
-
-static int32_t inet6_addr_change_notifier(struct notifier_block *nb, unsigned long action, void *data)
-{
-    struct inet6_ifaddr *ifa = NULL;
-    struct net_device *notifier_dev = NULL;  //触发事件的网络设备
-    struct zxdh_en_device *en_dev = container_of(nb, struct zxdh_en_device, ipv6_notifier);  //处理此回调函数的设备
-
-    if(data == NULL)
-    {
-        LOG_ERR("data is NULL");
-        return NOTIFY_OK;
-    }
-
-    ifa = (struct inet6_ifaddr *)data;
-    notifier_dev = ifa->idev->dev;
-
-    if (notifier_dev == NULL)
-    {
-        LOG_ERR("notifier_dev is NULL");
-        return NOTIFY_OK;
-    }
-
-    // 检查是否为vlan设备
-    if (is_vlan_dev(notifier_dev))
-        notifier_dev = vlan_dev_real_dev(notifier_dev);
-
-    // 检查是否为bond master设备
-    if (netif_is_bond_master(notifier_dev))
-        return do_bond_master_inet6_update_mac_to_np(notifier_dev, &ifa->addr, en_dev, action);
-
-    // 检查是否为自定义设备
-    if (strcmp(en_dev->netdev->name, notifier_dev->name) == 0)
-        return do_pf_vf_inet6_update_mac_to_np(en_dev, &ifa->addr, action);
-
-    return NOTIFY_OK;
-}
-
-static void vf_link_info_update_handler(struct work_struct *_work)
-{
-    struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device, vf_link_info_update_work);
-    union zxdh_msg msg = {0};
-    struct zxdh_vf_item *vf_item = NULL;
-    int32_t err = 0;
-    uint16_t vf_idx = 0;
-    struct pci_dev *pdev = NULL;
-    uint16_t num_vfs = 0;
-    bool pf_link_up = false;
-
-    ZXDH_AUX_INIT_COMP_CHECK(en_dev);
-    pf_link_up = en_dev->ops->get_pf_link_up(en_dev->parent);
-    pdev = en_dev->ops->get_pdev(en_dev->parent);
-    num_vfs = pci_num_vf(pdev);
-
-    msg.payload.hdr_vf.op_code = ZXDH_SET_VF_LINK_STATE;
-    msg.payload.link_state_msg.is_link_force_set = FALSE;
-
-    msg.payload.link_state_msg.link_up = pf_link_up;
-    msg.payload.link_state_msg.speed = en_dev->speed;
-    msg.payload.link_state_msg.autoneg_enable = en_dev->autoneg_enable;
-    msg.payload.link_state_msg.supported_speed_modes = en_dev->supported_speed_modes;
-    msg.payload.link_state_msg.advertising_speed_modes = en_dev->advertising_speed_modes;
-
-    for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
-    {
-        vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx);
-        msg.payload.hdr_vf.dst_pcie_id = FIND_VF_PCIE_ID(en_dev->pcie_id, vf_idx);
-        if(vf_item->is_probed)
-        {
-            msg.payload.link_state_msg.link_forced = vf_item->link_forced;
-            err = zxdh_send_command_to_specify(en_dev, MODULE_PF_BAR_MSG_TO_VF, &msg, &msg);
-            if (err != 0)
-            {
-                LOG_ERR("failed to update VF[%d]\n", vf_idx);
-            }
-        }
-    }
-}
-
-static void link_info_irq_update_vf_handler(struct work_struct *_work)
-{
-    struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device, link_info_irq_update_vf_work);
-    struct zxdh_vf_item *vf_item = NULL;
-    int32_t err = 0;
-    uint16_t vf_idx = 0;
-    struct pci_dev *pdev = NULL;
-    uint16_t num_vfs = 0;
-    bool pf_link_up = en_dev->ops->get_pf_link_up(en_dev->parent);
-    uint16_t func_no = 0;
-    uint16_t pf_no = FIND_PF_ID(en_dev->pcie_id);
-    union zxdh_msg msg = {0};
-
-    LOG_INFO("is called\n");
-    ZXDH_AUX_INIT_COMP_CHECK(en_dev);
-    msg.payload.hdr_to_agt.op_code = AGENT_DEV_STATUS_NOTIFY;
-    msg.payload.hdr_to_agt.pcie_id = en_dev->pcie_id;
-    pdev = en_dev->ops->get_pdev(en_dev->parent);
-    num_vfs = pci_num_vf(pdev);
-    for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
-    {
-        vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx);
-        if(vf_item->link_forced == FALSE && vf_item->is_probed)
-        {
-            func_no = GET_FUNC_NO(pf_no, vf_idx);
-            LOG_INFO("vf_idx:%d, func_no=0x%x\n",vf_idx,func_no);
-            msg.payload.pcie_msix_msg.func_no[msg.payload.pcie_msix_msg.num++] = func_no;
-            en_dev->ops->set_vf_link_info(en_dev->parent, vf_idx, pf_link_up ? 1 : 0);
-        }
-    }
-    LOG_INFO("msg.payload.pcie_msix_msg.num:%d\n",msg.payload.pcie_msix_msg.num);
-    if(msg.payload.pcie_msix_msg.num > 0)
-    {
-        err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-        if (err != 0)
-        {
-            LOG_ERR("failed to update VF link info\n");
-        }
-    }
-}
-
-static void link_info_irq_process_handler(struct work_struct *_work)
-{
-    struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device, link_info_irq_process_work);
-    int32_t ret = 0;
-    union zxdh_msg msg = {0};
-    struct link_info_struct link_info_val = {0};
-
-    ZXDH_AUX_INIT_COMP_CHECK(en_dev);
-
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_LINK_INFO_GET;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;
-    ret = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
-    if (ret != 0)
-    {
-        LOG_ERR("get speed and duplex from agent failed: %d\n", ret);
-        return;
-    }
-    en_dev->speed = msg.reps.mac_set_msg.speed;
-    en_dev->duplex = msg.reps.mac_set_msg.duplex;
-    LOG_DEBUG("netdev:%s, phy_port:0x%x, speed:%d, duplex:0x%x\n", en_dev->netdev->name, en_dev->phy_port, en_dev->speed, en_dev->duplex);
-
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        link_info_val.speed = en_dev->speed;
-        link_info_val.autoneg_enable = en_dev->autoneg_enable;
-        link_info_val.supported_speed_modes = en_dev->supported_speed_modes;
-        link_info_val.advertising_speed_modes = en_dev->advertising_speed_modes;
-        link_info_val.duplex = en_dev->duplex;
-
-        en_dev->ops->update_pf_link_info(en_dev->parent, &link_info_val);
-
-        //zxdh_port_th_update(en_dev);
-    }
-
-    return;
-}
-
-static void link_info_irq_update_np_work_handler(struct work_struct *_work)
-{
-    struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device, link_info_irq_update_np_work);
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    ZXDH_AUX_INIT_COMP_CHECK(en_dev);
-    if (!en_dev->ops->is_bond(en_dev->parent))
-    {
-        if (!netif_running(en_dev->netdev))
-        {
-            return;
-        }
-        if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-        {
-            zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_VPORT_IS_UP, en_dev->link_up, 0);
-        }
-        else
-        {
-            dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VPORT_IS_UP, en_dev->link_up);
-        }
-        return;
-    }
-
-    if (!en_dev->link_up)
-    {
-        dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_IS_UP, 0);
-    }
-    else
-    {
-        if (en_dev->netdev->flags & IFF_UP)
-        {
-            dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_IS_UP, 1);
-        }
-    }
-}
-
-static void en_aux_spoof_check(struct zxdh_en_device *en_dev)
-{
-    uint64_t ssvpc = 0;
-    uint16_t en_aux_pf_id = 0;
-    uint32_t ret = 0;
-    uint16_t num_vfs = 0;
-    struct pci_dev *pdev = NULL;
-    struct dh_core_dev *dh_dev = NULL;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    dh_dev = en_dev->parent;
-    pdev = en_dev->ops->get_pdev(dh_dev);
-    num_vfs = pci_num_vf(pdev);
-
-    if (!IS_PF(en_dev->vport))
-    {
-        return;
-    }
-    if (num_vfs == 0)
-    {
-        return;
-    }
-
-    en_aux_pf_id = DH_AUX_PF_ID_OFFSET(en_dev->vport);
-    // spoof static register clear to 0 after read
-    ret = dpp_stat_spoof_packet_drop_cnt_get(&pf_info, en_aux_pf_id, 1, &ssvpc);
-    if (ret != 0)
-    {
-        LOG_ERR("Failed to get spoof check dropped packets number.\n");
-        return;
-    }
-    if (!ssvpc)
-    {
-        return;
-    }
-    LOG_INFO("%llu Spoofed packets detected in EP%d, PF%d\n", ssvpc, EPID(en_dev->vport), FUNC_NUM(en_dev->vport));
-    return;
-}
-
-static void en_aux_service_task(struct work_struct *_work)
-{
-    struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device, service_task);
-
-    ZXDH_AUX_INIT_COMP_CHECK(en_dev);
-    en_aux_spoof_check(en_dev);
-}
-
-static void en_aux_service_timer(struct timer_list *t)
-{
-    unsigned long next_event_offset = HZ * 2;
-    struct zxdh_en_device *en_dev = from_timer(en_dev, t, service_timer);
-    struct zxdh_en_priv *en_priv = container_of(en_dev, struct zxdh_en_priv, edev);
-
-    /* Reset the timer */
-    mod_timer(&en_dev->service_timer, next_event_offset + jiffies);
-    queue_work(en_priv->events->wq, &en_dev->service_task);
-}
-
-static void en_aux_service_riscv_task(struct work_struct *_work)
-{
-    int32_t retval = 0;
-    union zxdh_msg msg = {0};
-
-    time64_t   time64;
-    struct rtc_time tm;
-    unsigned long next_event_offset = HZ * 259200;
-
-    struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device, service_riscv_task);
-
-    if (!IS_PF(en_dev->vport))
-    {
-        return;
-    }
-
-    msg.payload.hdr_to_cmn.pcie_id =  en_dev->pcie_id;;
-    msg.payload.hdr_to_cmn.write_bytes = 9;
-    msg.payload.hdr_to_cmn.type = RISC_SERVER_TIME;
-    msg.payload.hdr_to_cmn.field = 0;
-
-    time64 = ktime_get_real_seconds();
-    time64 += 28800;//CST比UST晚八个小时
-    rtc_time64_to_tm(time64, &tm);
-
-    msg.payload.time_cfg_msg.tmmng_type = 0xF0;
-    msg.payload.time_cfg_msg.dir = 0x2;
-    msg.payload.time_cfg_msg.year = tm.tm_year + 1900;
-    msg.payload.time_cfg_msg.month = tm.tm_mon + 1;
-    msg.payload.time_cfg_msg.day = tm.tm_mday;
-    msg.payload.time_cfg_msg.hour = tm.tm_hour;
-    msg.payload.time_cfg_msg.min = tm.tm_min;
-    msg.payload.time_cfg_msg.sec = tm.tm_sec;
-
-
-    LOG_INFO("send msg timer to riscv:%d-%d-%d %d:%d:%d\n", msg.payload.time_cfg_msg.year, msg.payload.time_cfg_msg.month, msg.payload.time_cfg_msg.day, msg.payload.time_cfg_msg.hour, msg.payload.time_cfg_msg.min, msg.payload.time_cfg_msg.sec);
-    ZXDH_AUX_INIT_COMP_CHECK(en_dev);
-
-    retval = zxdh_send_command_to_specify(en_dev, MODULE_PF_TIMER_TO_RISC_MSG, &msg, &msg);
-    if (retval != 0)
-    {
-        LOG_ERR("zxdh_send_command_to_riscv failed: %d\n", retval);
-    }
-
-    mod_timer(&en_dev->service_riscv_timer, next_event_offset + jiffies);
-}
-
-static void en_aux_service_riscv_timer(struct timer_list *t)
-{
-    unsigned long next_event_offset = HZ * 60;
-    struct zxdh_en_device *en_dev = from_timer(en_dev, t, service_riscv_timer);
-    struct zxdh_en_priv *en_priv = container_of(en_dev, struct zxdh_en_priv, edev);
-
-    /* Reset the timer */
-    mod_timer(&en_dev->service_riscv_timer, next_event_offset + jiffies);
-    queue_work(en_priv->events->wq, &en_dev->service_riscv_task);
-}
-
-static void pf2vf_msg_proc_work_handler(struct work_struct *_work)
-{
-    struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device, pf2vf_msg_proc_work);
-    uint64_t virt_addr = 0;
-
-    LOG_INFO("is called\n");
-    ZXDH_AUX_INIT_COMP_CHECK(en_dev);
-    virt_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0) + ZXDH_BAR_MSG_OFFSET + ZXDH_BAR_PFVF_MSG_OFFSET;
-    zxdh_bar_irq_recv(MSG_CHAN_END_PF, MSG_CHAN_END_VF, virt_addr, en_dev);
-}
-
-static int32_t pf2vf_notifier(struct notifier_block *nb, unsigned long type, void *data)
-{
-    struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
-    struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)event_nb->ctx;
-
-    LOG_INFO("is called\n");
-    queue_work(en_priv->events->wq, &en_priv->edev.pf2vf_msg_proc_work);
-
-    return NOTIFY_OK;
-}
-
-static void riscv2aux_msg_proc_work_handler(struct work_struct *_work)
-{
-    struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device, riscv2aux_msg_proc_work);
-    uint64_t virt_addr = 0;
-    uint16_t src = MSG_CHAN_END_RISC;
-    uint16_t dst = MSG_CHAN_END_PF;
-
-    LOG_INFO("is called\n");
-    ZXDH_AUX_INIT_COMP_CHECK(en_dev);
-    virt_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0) + ZXDH_BAR_MSG_OFFSET;
-    zxdh_bar_irq_recv(src, dst, virt_addr, en_dev);
-}
-
-static int32_t riscv2aux_notifier(struct notifier_block *nb, unsigned long type, void *data)
-{
-    struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
-    struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)event_nb->ctx;
-    LOG_INFO("is called\n");
-    queue_work(en_priv->events->wq, &en_priv->edev.riscv2aux_msg_proc_work);
-
-    return NOTIFY_OK;
-}
-
-void pf_notify_vf_reset_handler(struct work_struct *work)
-{
-    int32_t ret = 0;
-    struct zxdh_en_device *en_dev = container_of(work, struct zxdh_en_device, pf_notify_vf_reset_work);
-    struct net_device *netdev = en_dev->netdev;
-
-    LOG_INFO("pf_notify_vf_reset_handler is called\n");
-    ZXDH_AUX_INIT_COMP_CHECK(en_dev);
-    ret = zxdh_vf_get_mac(netdev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_vf_get_mac failed: %d\n", ret);
-    }
-}
-
-typedef uint32_t (*zxdh_pf_msg_func)(zxdh_msg_info *msg, zxdh_reps_info *reps, struct zxdh_en_device *en_dev);
-
-typedef struct
-{
-    zxdh_msg_op_code op_code;
-    uint8_t proc_name[ZXDH_MSG_TYPE_CNT_MAX];
-    zxdh_pf_msg_func msg_proc;
-} zxdh_pf_msg_proc;
-
-static uint32_t zxdh_set_vf_link_state(zxdh_msg_info *msg, zxdh_reps_info *reps, struct zxdh_en_device *en_dev)
-{
-    uint32_t ret = 0;
-    uint16_t vf_idx = msg->hdr_vf.dst_pcie_id & (0xff);
-
-    if(!msg->link_state_msg.is_link_force_set)
-    {
-        en_dev->speed = msg->link_state_msg.speed;
-        en_dev->autoneg_enable = msg->link_state_msg.autoneg_enable;
-        en_dev->supported_speed_modes = msg->link_state_msg.supported_speed_modes;
-        en_dev->advertising_speed_modes = msg->link_state_msg.advertising_speed_modes;
-        if(msg->link_state_msg.link_forced)
-        {
-            return 0;
-        }
-    }
-
-    en_dev->ops->set_pf_link_up(en_dev->parent, msg->link_state_msg.link_up);
-    if(en_dev->ops->get_pf_link_up(en_dev->parent))
-    {
-        netif_carrier_on(en_dev->netdev);
-    }
-    else
-    {
-        netif_carrier_off(en_dev->netdev);
-    }
-    LOG_INFO("[VF GET MSG FROM PF]--VF[%d] link_state[%s] update success!\n", vf_idx, en_dev->ops->get_pf_link_up(en_dev->parent)?"TRUE":"FALSE");
-    return ret;
-}
-
-static uint32_t zxdh_set_vf_reset(zxdh_msg_info *msg, zxdh_reps_info *reps, struct zxdh_en_device *en_dev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(en_dev->netdev);
-    queue_work(en_priv->events->wq, &en_priv->edev.pf_notify_vf_reset_work);
-    return 0;
-}
-
-static uint32_t zxdh_set_vf_vlan(zxdh_msg_info *msg, zxdh_reps_info *reps, struct zxdh_en_device *edev)
-{
-    uint32_t ret = 0;
-    /* update local var*/
-    edev->vlan_dev.vlan_id = msg->vf_vlan_msg.vlan_id;
-    edev->vlan_dev.qos = msg->vf_vlan_msg.qos;
-    edev->vlan_dev.protcol = msg->vf_vlan_msg.protocl;
-
-    return ret;
-}
-
-static uint32_t zxdh_pf_get_vf_queue(zxdh_msg_info *msg, zxdh_reps_info *reps, struct zxdh_en_device *edev)
-{
-    uint32_t ret = 0;
-    uint32_t vir_queue_start;
-    uint32_t vir_queue_num;
-    uint32_t queue_index;
-    uint32_t queue_num;
-    uint32_t max_queue_num = edev->curr_queue_pairs;
-
-    PLCR_LOG_INFO("vf's edev->vport     = 0x%x\n", edev->vport);
-    PLCR_LOG_INFO("vf's max_queue_num(pairs) = 0x%x\n", max_queue_num);
-    PLCR_LOG_INFO("edev->device_id = %x\n", edev->device_id);
-    PLCR_LOG_INFO("edev->rq[0].vq->phy_index = %x\n", edev->rq[0].vq->phy_index);
-    PLCR_LOG_INFO("edev->sq[0].vq->phy_index = %x\n", edev->sq[0].vq->phy_index);
-
-    vir_queue_start = msg->plcr_pf_get_vf_queue_info_msg.vir_queue_start;
-    vir_queue_num   = msg->plcr_pf_get_vf_queue_info_msg.vir_queue_num;
-
-    PLCR_LOG_INFO("vir_queue_start = 0x%x\n", vir_queue_start);
-    PLCR_LOG_INFO("vir_queue_num   = 0x%x\n", vir_queue_num);
-
-    if(max_queue_num > (vir_queue_num + vir_queue_num))
-    {
-        max_queue_num = vir_queue_num + vir_queue_num;
-    }
-
-    for(queue_index=vir_queue_start, queue_num = 0; queue_index<max_queue_num; queue_index++, queue_num++)
-    {
-        //get rx&tx queue info
-        reps->plcr_pf_get_vf_queue_info_rsp.phy_rxq[queue_num] = edev->rq[queue_num].vq->phy_index;
-        reps->plcr_pf_get_vf_queue_info_rsp.phy_txq[queue_num] = edev->sq[queue_num].vq->phy_index;
-    }
-
-    reps->plcr_pf_get_vf_queue_info_rsp.phy_queue_num = queue_num;
-
-    PLCR_LOG_INFO("queue_num   = 0x%x\n", queue_num);
-
-    return ret;
-}
-
-zxdh_pf_msg_proc pf_msg_proc[] =
-{
-    {ZXDH_SET_VF_LINK_STATE,      "set_vf_link_state",         zxdh_set_vf_link_state},
-    {ZXDH_SET_VF_RESET,           "set_vf_reset",              zxdh_set_vf_reset},
-    {ZXDH_PF_SET_VF_VLAN,         "pf_set_vf_vlan",            zxdh_set_vf_vlan},
-    {ZXDH_PF_GET_VF_QUEUE_INFO,   "pf_get_vf_queue_info",      zxdh_pf_get_vf_queue},
-};
-
-int32_t zxdh_vf_msg_recv_func(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev)
-{
-    zxdh_msg_info *msg = (zxdh_msg_info *)pay_load;
-    zxdh_reps_info *reps = (zxdh_reps_info *)reps_buffer;
-    struct zxdh_en_device *en_dev = (struct zxdh_en_device *)dev;
-    int32_t ret = 0;
-    int32_t i = 0;
-    int32_t num = 0;
-
-    LOG_INFO("is called\n");
-    if (len != sizeof(union zxdh_msg))
-    {
-        LOG_ERR("invalid data_len\n");
-        return -1;
-    }
-
-    if (en_dev == NULL)
-    {
-        LOG_ERR("dev is NULL\n");
-        return -1;
-    }
-
-    num = sizeof(pf_msg_proc)/sizeof(zxdh_pf_msg_proc);
-
-    for (i = 0; i < num; i++)
-    {
-        *reps_len = sizeof(union zxdh_msg);
-        if (pf_msg_proc[i].op_code == msg->hdr_vf.op_code)
-        {
-            LOG_INFO("%s is called", pf_msg_proc[i].proc_name);
-            ret = pf_msg_proc[i].msg_proc(msg, reps, en_dev);
-            if (ret != 0)
-            {
-                reps->flag = ZXDH_REPS_FAIL;
-                LOG_ERR("%s failed, ret: %d\n", pf_msg_proc[i].proc_name, ret);
-                return -1;
-            }
-            reps->flag = ZXDH_REPS_SUCC;
-            return 0;
-        }
-    }
-
-    LOG_ERR("invalid op_code: [%u]\n", msg->hdr_vf.op_code);
-    return -2;
-}
-
-int32_t dh_aux_ipv6_notifier_init(struct zxdh_en_priv *en_priv)
-{
-    int32_t ret = 0;
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    en_dev->ipv6_notifier.notifier_call = inet6_addr_change_notifier;
-    en_dev->ipv6_notifier.priority = 0;
-    ret = dh_inet6_addr_change_notifier_register(&(en_dev->ipv6_notifier));
-    if (ret)
-    {
-        LOG_ERR("Failed to register inet6addr_notifier, ret:%d\n",ret);
-        return ret;
-    }
-    LOG_INFO("netdev:%s ipv6_notifier_init success\n", en_dev->netdev->name);
-    return ret;
-}
-
-int32_t dh_aux_events_init(struct zxdh_en_priv *en_priv)
-{
-    struct dh_events *events = NULL;
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t i = 0;
-    int32_t ret = 0;
-    uint32_t evt_num = ARRAY_SIZE(aux_events);
-
-    if (!en_dev->ops->if_init(en_dev->parent))
-    {
-        evt_num -= 1;
-    }
-
-    events = kzalloc((sizeof(*events) + evt_num * sizeof(struct dh_event_nb)), GFP_KERNEL);
-    if (unlikely(events == NULL))
-    {
-        LOG_ERR("events kzalloc failed: %p\n", events);
-        ret = -ENOMEM;
-        goto err_events_kzalloc;
-    }
-
-    events->evt_num = evt_num;
-    events->dev = NULL;
-    en_priv->events = events;
-    events->wq = create_singlethread_workqueue("dh_aux_events");
-    if (!events->wq)
-    {
-        LOG_ERR("events->wq create_singlethread_workqueue failed: %p\n", events->wq);
-        ret = -ENOMEM;
-        goto err_create_wq;
-    }
-
-    INIT_WORK(&en_dev->vf_link_info_update_work, vf_link_info_update_handler);
-    INIT_WORK(&en_dev->link_info_irq_update_vf_work, link_info_irq_update_vf_handler);
-    INIT_WORK(&en_dev->link_info_irq_process_work, link_info_irq_process_handler);
-    INIT_WORK(&en_dev->link_info_irq_update_np_work, link_info_irq_update_np_work_handler);
-    INIT_WORK(&en_dev->rx_mode_set_work, rx_mode_set_handler);
-    INIT_WORK(&en_dev->pf2vf_msg_proc_work, pf2vf_msg_proc_work_handler);
-    INIT_WORK(&en_dev->pf_notify_vf_reset_work, pf_notify_vf_reset_handler);
-    INIT_WORK(&en_dev->service_task, en_aux_service_task);
-    INIT_WORK(&en_dev->service_riscv_task, en_aux_service_riscv_task);
-    INIT_WORK(&en_dev->riscv2aux_msg_proc_work, riscv2aux_msg_proc_work_handler);
-
-    timer_setup(&en_dev->service_timer, en_aux_service_timer, 0);
-    ret = mod_timer(&en_dev->service_timer, jiffies);
-    if (ret)
-    {
-        LOG_ERR("timer add failed\n");
-        goto err_mod_timer;
-    }
-
-    timer_setup(&en_dev->service_riscv_timer, en_aux_service_riscv_timer, 0);
-    ret = mod_timer(&en_dev->service_riscv_timer, jiffies);
-    if (ret)
-    {
-        LOG_ERR("timer add failed\n");
-        goto err_riscv_timer;
-    }
-
-    for (i = 0; i < evt_num; i++)
-    {
-        events->notifiers[i].nb = aux_events[i];
-        events->notifiers[i].ctx = en_priv;
-        dh_eq_notifier_register(&en_priv->eq_table, &events->notifiers[i].nb);
-    }
-
-    return ret;
-
-err_riscv_timer:
-    del_timer(&en_dev->service_riscv_timer);
-err_mod_timer:
-    del_timer(&en_dev->service_timer);
-    destroy_workqueue(events->wq);
-err_create_wq:
-    kfree(events);
-err_events_kzalloc:
-    return ret;
-}
-
-void dh_aux_events_uninit(struct zxdh_en_priv *en_priv)
-{
-    struct dh_events *events = en_priv->events;
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t i = 0;
-
-    for (i = events->evt_num - 1; i >= 0 ; i--)
-    {
-        dh_eq_notifier_unregister(&en_priv->eq_table, &events->notifiers[i].nb);
-    }
-
-    del_timer(&en_dev->service_timer);
-    del_timer(&en_dev->service_riscv_timer);
-    destroy_workqueue(en_priv->events->wq);
-    kfree(en_priv->events);
-
-    return;
-}
-
-static int32_t mgr_test_cnt(void *data, uint16_t len, void *reps, uint16_t *reps_len, void *dev)
-{
-    uint8_t *pay_load = (uint8_t *)data;
-    uint8_t *reps_buffer = (uint8_t *)reps;
-    uint16_t idx = 0;
-    uint16_t sum = 0;
-
-    if (reps_buffer == NULL)
-    {
-        return 0;
-    }
-
-    for (idx = 0; idx < len; idx++)
-    {
-        sum += pay_load[idx];
-    }
-
-    reps_buffer[0] = (uint8_t)sum;
-    reps_buffer[1] = (uint8_t)(sum >> 8);
-    *reps_len = 2;
-    return 0;
-}
-
-static int32_t msgq_test_func(void *data, uint16_t len, void *reps, uint16_t *reps_len, void *dev)
-{
-    if (reps == NULL)
-    {
-        return 0;
-    }
-
-    *reps_len = len;
-    return 0;
-}
-
-int32_t dh_aux_msg_recv_func_register(void)
-{
-    int32_t ret = 0;
-
-    ret = zxdh_bar_chan_msg_recv_register(MODULE_PF_BAR_MSG_TO_VF, zxdh_vf_msg_recv_func);
-    if (0 != ret)
-    {
-        LOG_ERR("event_id[%d] register failed: %d\n", MODULE_PF_BAR_MSG_TO_VF, ret);
-        return ret;
-    }
-
-    ret = zxdh_bar_chan_msg_recv_register(MODULE_DHTOOL, zxdh_tools_sendto_user_netlink);
-    if (0 != ret)
-    {
-        LOG_ERR("event_id[%d] register failed: %d\n", MODULE_DHTOOL, ret);
-        goto unregister_pf_to_vf;
-    }
-
-    ret = zxdh_bar_chan_msg_recv_register(MODULE_DEMO, mgr_test_cnt);
-    if (0 != ret)
-    {
-        LOG_ERR("event_id[%d] register failed: %d\n", MODULE_MSGQ, ret);
-        goto unregister_dhtool;
-    }
-
-    ret = zxdh_bar_chan_msg_recv_register(MODULE_MSGQ, msgq_test_func);
-    if (0 != ret)
-    {
-        LOG_ERR("event_id[%d] register failed: %d\n", MODULE_MSGQ, ret);
-        goto unregister_demo;
-    }
-
-    return ret;
-unregister_demo:
-    zxdh_bar_chan_msg_recv_unregister(MODULE_DEMO);
-unregister_dhtool:
-    zxdh_bar_chan_msg_recv_unregister(MODULE_DHTOOL);
-unregister_pf_to_vf:
-    zxdh_bar_chan_msg_recv_unregister(MODULE_PF_BAR_MSG_TO_VF);
-    return ret;
-}
-
-void dh_aux_msg_recv_func_unregister(void)
-{
-    zxdh_bar_chan_msg_recv_unregister(MODULE_MSGQ);
-    zxdh_bar_chan_msg_recv_unregister(MODULE_DEMO);
-    zxdh_bar_chan_msg_recv_unregister(MODULE_DHTOOL);
-    zxdh_bar_chan_msg_recv_unregister(MODULE_PF_BAR_MSG_TO_VF);
-    return;
-}
+#include <linux/gfp.h>
+#include <linux/slab.h>
+#include <linux/notifier.h>
+#include <linux/dinghai/events.h>
+#include <linux/dinghai/dh_cmd.h>
+#include <linux/workqueue.h>
+#include <linux/kernel.h>
+#include "events.h"
+#include "en_cmd.h"
+#include "../msg_common.h"
+#include "../en_np/table/include/dpp_tbl_api.h"
+#include "../zxdh_tools/zxdh_tools_netlink.h"
+#include "dcbnl/en_dcbnl_api.h"
+#include "zxic_common.h"
+#include <linux/timer.h>
+#include <linux/rtc.h>
+#include <linux/if_ether.h>
+#include <linux/in6.h>
+#include <net/addrconf.h>
+#include <linux/if_vlan.h>       // 对于VLAN设备
+#include <linux/if_bonding.h>    // 对于bonding设备
+#include <net/bonding.h>
+
+static int32_t pf2vf_notifier(struct notifier_block *, unsigned long, void *);
+static int32_t riscv2aux_notifier(struct notifier_block *, unsigned long,
+								  void *);
+
+void rx_mode_set_handler(struct work_struct *work);
+
+static struct dh_nb aux_events[] = {
+	{ .nb.notifier_call = pf2vf_notifier,
+	  .event_type = DH_EVENT_TYPE_NOTIFY_PF_TO_VF },
+	{ .nb.notifier_call = riscv2aux_notifier,
+	  .event_type = DH_EVENT_TYPE_NOTIFY_RISCV_TO_AUX },
+};
+
+static int32_t do_pf_vf_inet6_update_mac_to_np(struct zxdh_en_device *en_dev,
+											   const struct in6_addr *ipv6_addr,
+											   unsigned long action)
+{
+	int32_t ret = 0;
+	struct in6_addr sol_addr = { 0 };
+	uint8_t mcast_mac[ETH_ALEN];
+
+	// 打印IPv6地址，使用%pI6c格式化IPv6地址，确保正确显示
+	LOG_INFO("IPv6 address changed on interface %s, %s address: %pI6c\n",
+			 en_dev->netdev->name,
+			 (action == 1) ? "add" :
+			 (action == 2) ? "del" :
+							   "unknown action with",
+			 ipv6_addr);
+	// Calculate the multicast MAC address from the IPv6 address
+	addrconf_addr_solict_mult(ipv6_addr, &sol_addr);
+	LOG_INFO("Solicited-Node multicast address: %pI6\n", &sol_addr);
+	ipv6_eth_mc_map(&sol_addr, mcast_mac);
+	LOG_INFO("Multicast MAC Address: %pM\n", mcast_mac);
+
+	switch (action) {
+	case NETDEV_UP: {
+		ret = ipv6_multicast_mac_add(en_dev, en_dev->netdev, mcast_mac);
+		if (ret != 0) {
+			LOG_ERR("ipv6_multicast_mac_add failed");
+		}
+		break;
+	}
+	case NETDEV_DOWN: {
+		ret = ipv6_multicast_mac_del(en_dev, en_dev->netdev, mcast_mac);
+		if (ret != 0) {
+			LOG_ERR("ipv6_multicast_mac_del failed");
+		}
+		break;
+	}
+	default:
+		break;
+	}
+	return ret;
+}
+
+static int32_t do_bond_master_inet6_update_mac_to_np(
+		struct net_device *notifier_dev, const struct in6_addr *ipv6_addr,
+		struct zxdh_en_device *en_dev, unsigned long action)
+{
+	int32_t ret = 0;
+	struct list_head *iter = NULL;
+	struct slave *slave_dev = NULL;
+	struct bonding *bond = netdev_priv(notifier_dev);
+
+	// 遍历所有slave设备
+	if (bond_has_slaves(bond)) {
+		bond_for_each_slave(bond, slave_dev, iter) {
+			if (strcmp(en_dev->netdev->name, slave_dev->dev->name) != 0) {
+				continue;
+			}
+			LOG_INFO("Bond device %s has slave device: %s\n",
+					 notifier_dev->name, slave_dev->dev->name);
+			ret = do_pf_vf_inet6_update_mac_to_np(en_dev, ipv6_addr, action);
+			if (ret != 0) {
+				return ret;
+			}
+		}
+	}
+	return 0;
+}
+
+static int32_t inet6_addr_change_notifier(struct notifier_block *nb,
+										  unsigned long action, void *data)
+{
+	struct inet6_ifaddr *ifa = NULL;
+	struct net_device *notifier_dev = NULL; //触发事件的网络设备
+	struct net_device *vlan_real_dev = NULL; // vlan子接口底层设备
+	struct zxdh_en_device *en_dev = container_of(
+			nb, struct zxdh_en_device, ipv6_notifier); //处理此回调函数的设备
+
+	if (data == NULL) {
+		LOG_ERR("data is NULL");
+		return -1;
+	}
+
+	ifa = (struct inet6_ifaddr *)data;
+	notifier_dev = ifa->idev->dev;
+
+	if (notifier_dev == NULL) {
+		LOG_ERR("notifier_dev is NULL");
+		return -1;
+	}
+
+	// 检查是否为vlan设备
+	if (is_vlan_dev(notifier_dev))
+		notifier_dev = vlan_dev_real_dev(notifier_dev);
+
+	// 检查是否为bond master设备
+	if (netif_is_bond_master(notifier_dev)) {
+		return do_bond_master_inet6_update_mac_to_np(notifier_dev, &ifa->addr,
+													 en_dev, action);
+	}
+
+	// 检查是否为自定义设备
+	if (strcmp(en_dev->netdev->name, notifier_dev->name) == 0) {
+		return do_pf_vf_inet6_update_mac_to_np(en_dev, &ifa->addr, action);
+	}
+
+	return NOTIFY_OK;
+}
+
+static void vf_link_info_update_handler(struct work_struct *_work)
+{
+	struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device,
+												 vf_link_info_update_work);
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack = { 0 };
+	struct zxdh_vf_item *vf_item = NULL;
+	int32_t err = 0;
+	uint16_t vf_idx = 0;
+	struct pci_dev *pdev = NULL;
+	uint16_t num_vfs = 0;
+	bool pf_link_up = false;
+
+	ZXDH_AUX_INIT_COMP_CHECK(en_dev);
+	pf_link_up = en_dev->ops->get_pf_link_up(en_dev->parent);
+	pdev = en_dev->ops->get_pdev(en_dev->parent);
+	num_vfs = pci_num_vf(pdev);
+
+	msg.hdr_vf.op_code = ZXDH_SET_VF_LINK_STATE;
+	msg.link_state_msg.is_link_force_set = FALSE;
+
+	msg.link_state_msg.link_up = pf_link_up;
+	msg.link_state_msg.speed = en_dev->speed;
+	msg.link_state_msg.autoneg_enable = en_dev->autoneg_enable;
+	msg.link_state_msg.supported_speed_modes = en_dev->supported_speed_modes;
+	msg.link_state_msg.advertising_speed_modes =
+			en_dev->advertising_speed_modes;
+
+	for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) {
+		vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx);
+		msg.hdr_vf.dst_pcie_id = FIND_VF_PCIE_ID(en_dev->pcie_id, vf_idx);
+		if (vf_item->is_probed) {
+			msg.link_state_msg.link_forced = vf_item->link_forced;
+			err = zxdh_send_command_to_specify(en_dev, MODULE_PF_BAR_MSG_TO_VF,
+											   &msg, &ack);
+			if (err != 0) {
+				LOG_ERR("failed to update VF[%d]\n", vf_idx);
+			}
+		}
+	}
+}
+
+static void link_info_irq_update_vf_handler(struct work_struct *_work)
+{
+	struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device,
+												 link_info_irq_update_vf_work);
+	struct zxdh_vf_item *vf_item = NULL;
+	int32_t err = 0;
+	uint16_t vf_idx = 0;
+	struct pci_dev *pdev = NULL;
+	uint16_t num_vfs = 0;
+	bool pf_link_up = en_dev->ops->get_pf_link_up(en_dev->parent);
+	uint16_t func_no = 0;
+	uint16_t pf_no = FIND_PF_ID(en_dev->pcie_id);
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack = { 0 };
+
+	LOG_INFO("is called\n");
+	ZXDH_AUX_INIT_COMP_CHECK(en_dev);
+	msg.hdr_to_agt.op_code = AGENT_DEV_STATUS_NOTIFY;
+	msg.hdr_to_agt.pcie_id = en_dev->pcie_id;
+	pdev = en_dev->ops->get_pdev(en_dev->parent);
+	num_vfs = pci_num_vf(pdev);
+	for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) {
+		vf_item = en_dev->ops->get_vf_item(en_dev->parent, vf_idx);
+		if (vf_item->link_forced == FALSE && vf_item->is_probed) {
+			func_no = GET_FUNC_NO(pf_no, vf_idx);
+			LOG_INFO("vf_idx:%d, func_no=0x%x\n", vf_idx, func_no);
+			msg.pcie_msix_msg.func_no[msg.pcie_msix_msg.num++] = func_no;
+			en_dev->ops->set_vf_link_info(en_dev->parent, vf_idx,
+										  pf_link_up ? 1 : 0);
+		}
+	}
+	LOG_INFO("msg.pcie_msix_msg.num:%d\n", msg.pcie_msix_msg.num);
+	if (msg.pcie_msix_msg.num > 0) {
+		err = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &ack);
+		if (err != 0) {
+			LOG_ERR("failed to update VF link info\n");
+		}
+	}
+}
+
+static void link_info_irq_process_handler(struct work_struct *_work)
+{
+	struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device,
+												 link_info_irq_process_work);
+	int32_t ret = 0;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack = { 0 };
+	struct link_info_struct link_info_val = { 0 };
+
+	ZXDH_AUX_INIT_COMP_CHECK(en_dev);
+
+	msg.hdr_to_agt.op_code = AGENT_MAC_LINK_INFO_GET;
+	msg.hdr_to_agt.phyport = en_dev->phy_port;
+	ret = zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &ack);
+	if (ret != 0) {
+		LOG_ERR("get speed and duplex from agent failed: %d\n", ret);
+		return;
+	}
+	en_dev->speed = ack.mac_set_msg.speed;
+	en_dev->duplex = ack.mac_set_msg.duplex;
+	LOG_DEBUG("netdev:%s, phy_port:0x%x, speed:%d, duplex:0x%x\n",
+			  en_dev->netdev->name, en_dev->phy_port, en_dev->speed,
+			  en_dev->duplex);
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		link_info_val.speed = en_dev->speed;
+		link_info_val.autoneg_enable = en_dev->autoneg_enable;
+		link_info_val.supported_speed_modes = en_dev->supported_speed_modes;
+		link_info_val.advertising_speed_modes = en_dev->advertising_speed_modes;
+		link_info_val.duplex = en_dev->duplex;
+
+		en_dev->ops->update_pf_link_info(en_dev->parent, &link_info_val);
+
+		zxdh_port_th_update(en_dev);
+	}
+
+	return;
+}
+
+static void link_info_irq_update_np_work_handler(struct work_struct *_work)
+{
+	struct zxdh_en_device *en_dev = container_of(_work, struct zxdh_en_device,
+												 link_info_irq_update_np_work);
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	ZXDH_AUX_INIT_COMP_CHECK(en_dev);
+	if (!en_dev->ops->is_bond(en_dev->parent)) {
+		if (!netif_running(en_dev->netdev)) {
+			return;
+		}
+		if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+			zxdh_vf_egr_port_attr_set(en_dev, EGR_FLAG_VPORT_IS_UP,
+									  en_dev->link_up, 0);
+		} else {
+			dpp_egr_port_attr_set(&pf_info, EGR_FLAG_VPORT_IS_UP,
+								  en_dev->link_up);
+		}
+		return;
+	}
+
+	if (!en_dev->link_up) {
+		dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_IS_UP, 0);
+	} else {
+		if (en_dev->netdev->flags & IFF_UP) {
+			dpp_panel_attr_set(&pf_info, en_dev->phy_port, PANEL_FLAG_IS_UP, 1);
+		}
+	}
+}
+
+static void en_aux_spoof_check(struct zxdh_en_device *en_dev)
+{
+	uint64_t ssvpc = 0;
+	uint16_t en_aux_pf_id = 0;
+	uint32_t ret = 0;
+	uint16_t num_vfs = 0;
+	struct pci_dev *pdev = NULL;
+	struct dh_core_dev *dh_dev = NULL;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	dh_dev = en_dev->parent;
+	pdev = en_dev->ops->get_pdev(dh_dev);
+	num_vfs = pci_num_vf(pdev);
+
+	if (!IS_PF(en_dev->vport)) {
+		return;
+	}
+	if (num_vfs == 0) {
+		return;
+	}
+
+	en_aux_pf_id = DH_AUX_PF_ID_OFFSET(en_dev->vport);
+	// spoof static register clear to 0 after read
+	ret = dpp_stat_spoof_packet_drop_cnt_get(&pf_info, en_aux_pf_id, 1, &ssvpc);
+	if (ret != 0) {
+		LOG_ERR("Failed to get spoof check dropped packets number.\n");
+		return;
+	}
+	if (!ssvpc) {
+		return;
+	}
+	LOG_INFO("%llu Spoofed packets detected in EP%d, PF%d\n", ssvpc,
+			 EPID(en_dev->vport), FUNC_NUM(en_dev->vport));
+	return;
+}
+
+static void en_aux_service_task(struct work_struct *_work)
+{
+	struct zxdh_en_device *en_dev =
+			container_of(_work, struct zxdh_en_device, service_task);
+
+	ZXDH_AUX_INIT_COMP_CHECK(en_dev);
+	en_aux_spoof_check(en_dev);
+}
+
+static void en_aux_service_timer(struct timer_list *t)
+{
+	unsigned long next_event_offset = HZ * 360000;
+	struct zxdh_en_device *en_dev = from_timer(en_dev, t, service_timer);
+	struct zxdh_en_priv *en_priv =
+			container_of(en_dev, struct zxdh_en_priv, edev);
+
+	/* Reset the timer */
+	mod_timer(&en_dev->service_timer, next_event_offset + jiffies);
+	queue_work(en_priv->events->wq, &en_dev->service_task);
+}
+
+static void en_aux_service_riscv_task(struct work_struct *_work)
+{
+	int32_t retval = 0;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack;
+
+	time64_t time64;
+	struct rtc_time tm;
+	unsigned long next_event_offset = HZ * 259200;
+
+	struct zxdh_en_device *en_dev =
+			container_of(_work, struct zxdh_en_device, service_riscv_task);
+	LOG_INFO("is called en_aux_service_riscv_task\n");
+
+	if (!IS_PF(en_dev->vport)) {
+		return;
+	}
+
+	msg.hdr_to_cmn.pcie_id = en_dev->pcie_id;
+	;
+	msg.hdr_to_cmn.write_bytes = 9;
+	msg.hdr_to_cmn.type = RISC_SERVER_TIME;
+	msg.hdr_to_cmn.field = 0;
+
+	time64 = ktime_get_real_seconds();
+	time64 += 28800; // CST比UST晚八个小时
+	rtc_time64_to_tm(time64, &tm);
+
+	msg.time_cfg_msg.tmmng_type = 0xF0;
+	msg.time_cfg_msg.dir = 0x2;
+	msg.time_cfg_msg.year = tm.tm_year + 1900;
+	msg.time_cfg_msg.month = tm.tm_mon + 1;
+	msg.time_cfg_msg.day = tm.tm_mday;
+	msg.time_cfg_msg.hour = tm.tm_hour;
+	msg.time_cfg_msg.min = tm.tm_min;
+	msg.time_cfg_msg.sec = tm.tm_sec;
+
+	LOG_INFO("send msg timer to riscv:%d-%d-%d %d:%d:%d\n",
+			 msg.time_cfg_msg.year, msg.time_cfg_msg.month,
+			 msg.time_cfg_msg.day, msg.time_cfg_msg.hour, msg.time_cfg_msg.min,
+			 msg.time_cfg_msg.sec);
+	ZXDH_AUX_INIT_COMP_CHECK(en_dev);
+
+	retval = zxdh_send_command_to_specify(en_dev, MODULE_PF_TIMER_TO_RISC_MSG,
+										  &msg, &ack);
+	if (retval != 0) {
+		LOG_ERR("zxdh_send_command_to_riscv failed: %d\n", retval);
+	}
+
+	mod_timer(&en_dev->service_riscv_timer, next_event_offset + jiffies);
+}
+
+static void en_aux_service_riscv_timer(struct timer_list *t)
+{
+	unsigned long next_event_offset = HZ * 60;
+	struct zxdh_en_device *en_dev = from_timer(en_dev, t, service_riscv_timer);
+	struct zxdh_en_priv *en_priv =
+			container_of(en_dev, struct zxdh_en_priv, edev);
+	LOG_INFO("is called en_aux_service_riscv_timer\n");
+
+	/* Reset the timer */
+	mod_timer(&en_dev->service_riscv_timer, next_event_offset + jiffies);
+	queue_work(en_priv->events->wq, &en_dev->service_riscv_task);
+}
+
+static void pf2vf_msg_proc_work_handler(struct work_struct *_work)
+{
+	struct zxdh_en_device *en_dev =
+			container_of(_work, struct zxdh_en_device, pf2vf_msg_proc_work);
+	uint64_t virt_addr = 0;
+
+	LOG_INFO("is called\n");
+	ZXDH_AUX_INIT_COMP_CHECK(en_dev);
+	virt_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0) +
+				ZXDH_BAR_MSG_OFFSET + ZXDH_BAR_PFVF_MSG_OFFSET;
+	zxdh_bar_irq_recv(MSG_CHAN_END_PF, MSG_CHAN_END_VF, virt_addr, en_dev);
+}
+
+static int32_t pf2vf_notifier(struct notifier_block *nb, unsigned long type,
+							  void *data)
+{
+	struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
+	struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)event_nb->ctx;
+
+	LOG_INFO("is called\n");
+	queue_work(en_priv->events->wq, &en_priv->edev.pf2vf_msg_proc_work);
+
+	return NOTIFY_OK;
+}
+
+static void riscv2aux_msg_proc_work_handler(struct work_struct *_work)
+{
+	struct zxdh_en_device *en_dev =
+			container_of(_work, struct zxdh_en_device, riscv2aux_msg_proc_work);
+	uint64_t virt_addr = 0;
+	uint16_t src = MSG_CHAN_END_RISC;
+	uint16_t dst = MSG_CHAN_END_PF;
+
+	LOG_INFO("is called\n");
+	ZXDH_AUX_INIT_COMP_CHECK(en_dev);
+	virt_addr = en_dev->ops->get_bar_virt_addr(en_dev->parent, 0) +
+				ZXDH_BAR_MSG_OFFSET;
+	zxdh_bar_irq_recv(src, dst, virt_addr, en_dev);
+}
+
+static int32_t riscv2aux_notifier(struct notifier_block *nb, unsigned long type,
+								  void *data)
+{
+	struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
+	struct zxdh_en_priv *en_priv = (struct zxdh_en_priv *)event_nb->ctx;
+	LOG_INFO("is called\n");
+	queue_work(en_priv->events->wq, &en_priv->edev.riscv2aux_msg_proc_work);
+
+	return NOTIFY_OK;
+}
+
+void pf_notify_vf_reset_handler(struct work_struct *work)
+{
+	int32_t ret = 0;
+	struct zxdh_en_device *en_dev =
+			container_of(work, struct zxdh_en_device, pf_notify_vf_reset_work);
+	struct net_device *netdev = en_dev->netdev;
+
+	LOG_INFO("pf_notify_vf_reset_handler is called\n");
+	ZXDH_AUX_INIT_COMP_CHECK(en_dev);
+	ret = zxdh_vf_get_mac(netdev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_vf_get_mac failed: %d\n", ret);
+	}
+}
+
+typedef uint32_t (*zxdh_pf_msg_func)(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									 struct zxdh_en_device *en_dev);
+
+typedef struct {
+	zxdh_msg_op_code op_code;
+	uint8_t proc_name[ZXDH_MSG_TYPE_CNT_MAX];
+	zxdh_pf_msg_func msg_proc;
+} zxdh_pf_msg_proc;
+
+static uint32_t zxdh_set_vf_link_state(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									   struct zxdh_en_device *en_dev)
+{
+	uint32_t ret = 0;
+	uint16_t vf_idx = msg->hdr_vf.dst_pcie_id & (0xff);
+
+	if (!msg->link_state_msg.is_link_force_set) {
+		en_dev->speed = msg->link_state_msg.speed;
+		en_dev->autoneg_enable = msg->link_state_msg.autoneg_enable;
+		en_dev->supported_speed_modes =
+				msg->link_state_msg.supported_speed_modes;
+		en_dev->advertising_speed_modes =
+				msg->link_state_msg.advertising_speed_modes;
+		if (msg->link_state_msg.link_forced) {
+			return 0;
+		}
+	}
+
+	en_dev->ops->set_pf_link_up(en_dev->parent, msg->link_state_msg.link_up);
+	if (en_dev->ops->get_pf_link_up(en_dev->parent)) {
+		netif_carrier_on(en_dev->netdev);
+	} else {
+		netif_carrier_off(en_dev->netdev);
+	}
+	LOG_INFO("[VF GET MSG FROM PF]--VF[%d] link_state[%s] update success!\n",
+			 vf_idx,
+			 en_dev->ops->get_pf_link_up(en_dev->parent) ? "TRUE" : "FALSE");
+	return ret;
+}
+
+static uint32_t zxdh_set_vf_reset(zxdh_msg_info *msg, zxdh_reps_info *reps,
+								  struct zxdh_en_device *en_dev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(en_dev->netdev);
+	queue_work(en_priv->events->wq, &en_priv->edev.pf_notify_vf_reset_work);
+	return 0;
+}
+
+static uint32_t zxdh_set_vf_vlan(zxdh_msg_info *msg, zxdh_reps_info *reps,
+								 struct zxdh_en_device *edev)
+{
+	uint32_t ret = 0;
+	/* update local var*/
+	edev->vlan_dev.vlan_id = msg->vf_vlan_msg.vlan_id;
+	edev->vlan_dev.qos = msg->vf_vlan_msg.qos;
+	edev->vlan_dev.protcol = msg->vf_vlan_msg.protocl;
+
+	return ret;
+}
+
+zxdh_pf_msg_proc pf_msg_proc[] = {
+	{ ZXDH_SET_VF_LINK_STATE, "set_vf_link_state", zxdh_set_vf_link_state },
+	{ ZXDH_SET_VF_RESET, "set_vf_reset", zxdh_set_vf_reset },
+	{ ZXDH_PF_SET_VF_VLAN, "pf_set_vf_vlan", zxdh_set_vf_vlan },
+};
+
+int32_t zxdh_vf_msg_recv_func(void *pay_load, uint16_t len, void *reps_buffer,
+							  uint16_t *reps_len, void *dev)
+{
+	zxdh_msg_info *msg = (zxdh_msg_info *)pay_load;
+	zxdh_reps_info *reps = (zxdh_reps_info *)reps_buffer;
+	struct zxdh_en_device *en_dev = (struct zxdh_en_device *)dev;
+	int32_t ret = 0;
+	int32_t i = 0;
+	int32_t num = 0;
+
+	LOG_INFO("is called\n");
+	if (len != sizeof(zxdh_msg_info)) {
+		LOG_ERR("invalid data_len\n");
+		return -1;
+	}
+
+	if (en_dev == NULL) {
+		LOG_ERR("dev is NULL\n");
+		return -1;
+	}
+
+	num = sizeof(pf_msg_proc) / sizeof(zxdh_pf_msg_proc);
+
+	for (i = 0; i < num; i++) {
+		*reps_len = sizeof(zxdh_reps_info);
+		if (pf_msg_proc[i].op_code == msg->hdr_vf.op_code) {
+			LOG_INFO("%s is called", pf_msg_proc[i].proc_name);
+			ret = pf_msg_proc[i].msg_proc(msg, reps, en_dev);
+			if (ret != 0) {
+				reps->flag = ZXDH_REPS_FAIL;
+				LOG_ERR("%s failed, ret: %d\n", pf_msg_proc[i].proc_name, ret);
+				return -1;
+			}
+			reps->flag = ZXDH_REPS_SUCC;
+			return 0;
+		}
+	}
+
+	LOG_ERR("invalid op_code: [%u]\n", msg->hdr_vf.op_code);
+	return -2;
+}
+
+int32_t dh_aux_ipv6_notifier_init(struct zxdh_en_priv *en_priv)
+{
+	int32_t ret = 0;
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	en_dev->ipv6_notifier.notifier_call = inet6_addr_change_notifier;
+	en_dev->ipv6_notifier.priority = 0;
+	ret = dh_inet6_addr_change_notifier_register(&(en_dev->ipv6_notifier));
+	if (ret) {
+		LOG_ERR("Failed to register inet6addr_notifier, ret:%d\n", ret);
+		return ret;
+	}
+	LOG_INFO("netdev:%s ipv6_notifier_init success\n", en_dev->netdev->name);
+	return ret;
+}
+
+int32_t dh_aux_events_init(struct zxdh_en_priv *en_priv)
+{
+	struct dh_events *events = NULL;
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t i = 0;
+	int32_t ret = 0;
+	uint32_t evt_num = ARRAY_SIZE(aux_events);
+
+	if (!en_dev->ops->if_init(en_dev->parent)) {
+		evt_num -= 1;
+	}
+
+	events = kzalloc((sizeof(*events) + evt_num * sizeof(struct dh_event_nb)),
+					 GFP_KERNEL);
+	if (unlikely(events == NULL)) {
+		LOG_ERR("events kzalloc failed: %p\n", events);
+		ret = -ENOMEM;
+		goto err_events_kzalloc;
+	}
+
+	events->evt_num = evt_num;
+	events->dev = NULL;
+	en_priv->events = events;
+	events->wq = create_singlethread_workqueue("dh_aux_events");
+	if (!events->wq) {
+		LOG_ERR("events->wq create_singlethread_workqueue failed: %p\n",
+				events->wq);
+		ret = -ENOMEM;
+		goto err_create_wq;
+	}
+
+	INIT_WORK(&en_dev->vf_link_info_update_work, vf_link_info_update_handler);
+	INIT_WORK(&en_dev->link_info_irq_update_vf_work,
+			  link_info_irq_update_vf_handler);
+	INIT_WORK(&en_dev->link_info_irq_process_work,
+			  link_info_irq_process_handler);
+	INIT_WORK(&en_dev->link_info_irq_update_np_work,
+			  link_info_irq_update_np_work_handler);
+	INIT_WORK(&en_dev->rx_mode_set_work, rx_mode_set_handler);
+	INIT_WORK(&en_dev->pf2vf_msg_proc_work, pf2vf_msg_proc_work_handler);
+	INIT_WORK(&en_dev->pf_notify_vf_reset_work, pf_notify_vf_reset_handler);
+	INIT_WORK(&en_dev->service_task, en_aux_service_task);
+	INIT_WORK(&en_dev->service_riscv_task, en_aux_service_riscv_task);
+	INIT_WORK(&en_dev->riscv2aux_msg_proc_work,
+			  riscv2aux_msg_proc_work_handler);
+
+	timer_setup(&en_dev->service_timer, en_aux_service_timer, 0);
+	ret = mod_timer(&en_dev->service_timer, jiffies);
+	if (ret) {
+		LOG_ERR("timer add failed\n");
+		goto err_mod_timer;
+	}
+
+	timer_setup(&en_dev->service_riscv_timer, en_aux_service_riscv_timer, 0);
+	ret = mod_timer(&en_dev->service_riscv_timer, jiffies);
+	if (ret) {
+		LOG_ERR("timer add failed\n");
+		goto err_riscv_timer;
+	}
+
+	for (i = 0; i < evt_num; i++) {
+		events->notifiers[i].nb = aux_events[i];
+		events->notifiers[i].ctx = en_priv;
+		dh_eq_notifier_register(&en_priv->eq_table, &events->notifiers[i].nb);
+	}
+
+	return ret;
+
+err_riscv_timer:
+	del_timer(&en_dev->service_riscv_timer);
+err_mod_timer:
+	del_timer(&en_dev->service_timer);
+	destroy_workqueue(events->wq);
+err_create_wq:
+	kfree(events);
+err_events_kzalloc:
+	return ret;
+}
+
+void dh_aux_events_uninit(struct zxdh_en_priv *en_priv)
+{
+	struct dh_events *events = en_priv->events;
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t i = 0;
+
+	for (i = events->evt_num - 1; i >= 0; i--) {
+		dh_eq_notifier_unregister(&en_priv->eq_table, &events->notifiers[i].nb);
+	}
+
+	del_timer(&en_dev->service_timer);
+	del_timer(&en_dev->service_riscv_timer);
+	destroy_workqueue(en_priv->events->wq);
+	kfree(en_priv->events);
+
+	return;
+}
+
+static int32_t mgr_test_cnt(void *data, uint16_t len, void *reps,
+							uint16_t *reps_len, void *dev)
+{
+	uint8_t *pay_load = (uint8_t *)data;
+	uint8_t *reps_buffer = (uint8_t *)reps;
+	uint16_t idx = 0;
+	uint16_t sum = 0;
+
+	if (reps_buffer == NULL) {
+		return 0;
+	}
+
+	for (idx = 0; idx < len; idx++) {
+		sum += pay_load[idx];
+	}
+
+	reps_buffer[0] = (uint8_t)sum;
+	reps_buffer[1] = (uint8_t)(sum >> 8);
+	*reps_len = 2;
+	return 0;
+}
+
+static int32_t msgq_test_func(void *data, uint16_t len, void *reps,
+							  uint16_t *reps_len, void *dev)
+{
+	if (reps == NULL) {
+		return 0;
+	}
+
+	*reps_len = len;
+	return 0;
+}
+
+int32_t dh_aux_msg_recv_func_register(void)
+{
+	int32_t ret = 0;
+
+	ret = zxdh_bar_chan_msg_recv_register(MODULE_PF_BAR_MSG_TO_VF,
+										  zxdh_vf_msg_recv_func);
+	if (0 != ret) {
+		LOG_ERR("event_id[%d] register failed: %d\n", MODULE_PF_BAR_MSG_TO_VF,
+				ret);
+		return ret;
+	}
+
+	ret = zxdh_bar_chan_msg_recv_register(MODULE_DHTOOL,
+										  zxdh_tools_sendto_user_netlink);
+	if (0 != ret) {
+		LOG_ERR("event_id[%d] register failed: %d\n", MODULE_DHTOOL, ret);
+		goto unregister_pf_to_vf;
+	}
+
+	ret = zxdh_bar_chan_msg_recv_register(MODULE_DEMO, mgr_test_cnt);
+	if (0 != ret) {
+		LOG_ERR("event_id[%d] register failed: %d\n", MODULE_MSGQ, ret);
+		goto unregister_dhtool;
+	}
+
+	ret = zxdh_bar_chan_msg_recv_register(MODULE_MSGQ, msgq_test_func);
+	if (0 != ret) {
+		LOG_ERR("event_id[%d] register failed: %d\n", MODULE_MSGQ, ret);
+		goto unregister_demo;
+	}
+
+	return ret;
+unregister_demo:
+	zxdh_bar_chan_msg_recv_unregister(MODULE_DEMO);
+unregister_dhtool:
+	zxdh_bar_chan_msg_recv_unregister(MODULE_DHTOOL);
+unregister_pf_to_vf:
+	zxdh_bar_chan_msg_recv_unregister(MODULE_PF_BAR_MSG_TO_VF);
+	return ret;
+}
+
+void dh_aux_msg_recv_func_unregister(void)
+{
+	zxdh_bar_chan_msg_recv_unregister(MODULE_MSGQ);
+	zxdh_bar_chan_msg_recv_unregister(MODULE_DEMO);
+	zxdh_bar_chan_msg_recv_unregister(MODULE_DHTOOL);
+	zxdh_bar_chan_msg_recv_unregister(MODULE_PF_BAR_MSG_TO_VF);
+	return;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/events.h b/src/net/drivers/net/ethernet/dinghai/en_aux/events.h
index 57348563fc7fd104080c77901c5de53e6cddb0fc..58c44e83961d501b0e1b36c038879d6140436f05 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/events.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/events.h
@@ -1,24 +1,24 @@
-#ifndef __ZXDH_PF_EVENTS_H__
-#define __ZXDH_PF_EVENTS_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/driver.h>
-#include "en_aux.h"
-#include "../en_np/table/include/dpp_tbl_comm.h"
-
-#define DH_AUX_PF_ID_OFFSET(vport) (EPID(vport) * 8 + FUNC_NUM(vport))
-
-int32_t dh_aux_events_init(struct zxdh_en_priv *en_priv);
-void dh_aux_events_uninit(struct zxdh_en_priv *en_priv);
-int32_t dh_aux_msg_recv_func_register(void);
-void dh_aux_msg_recv_func_unregister(void);
-int32_t dh_aux_ipv6_notifier_init(struct zxdh_en_priv *en_priv);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef __ZXDH_PF_EVENTS_H__
+#define __ZXDH_PF_EVENTS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/driver.h>
+#include "en_aux.h"
+#include "../en_np/table/include/dpp_tbl_comm.h"
+
+#define DH_AUX_PF_ID_OFFSET(vport) (EPID(vport) * 8 + FUNC_NUM(vport))
+
+int32_t dh_aux_events_init(struct zxdh_en_priv *en_priv);
+void dh_aux_events_uninit(struct zxdh_en_priv *en_priv);
+int32_t dh_aux_msg_recv_func_register(void);
+void dh_aux_msg_recv_func_unregister(void);
+int32_t dh_aux_ipv6_notifier_init(struct zxdh_en_priv *en_priv);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/priv_queue.c b/src/net/drivers/net/ethernet/dinghai/en_aux/priv_queue.c
index e29058eedaff85426607fbce9190ec20fc08f919..76208ad3c8b234608bedb6548fafb49cedf2fa31 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/priv_queue.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/priv_queue.c
@@ -1,4 +1,3 @@
-
 #include <linux/dinghai/kcompat.h>
 #include <linux/interrupt.h>
 #include <linux/device.h>
@@ -7,806 +6,739 @@
 
 static void poll_timer_callback(struct timer_list *this_timer)
 {
-    struct msgq_dev *msgq_dev = from_timer(msgq_dev, this_timer, poll_timer);
-    struct msg_buff *this_msg_buff = NULL;
-    uint16_t i = 0;
-    uint32_t tx_timeouts = 0;
-
-    if (msgq_dev == NULL)
-    {
-        LOG_ERR("msgq_dev is NULL\n");
-        return;
-    }
-
-    for (i = 0; i < MSGQ_MAX_MSG_BUFF_NUM; ++i)
-    {
-        if (msgq_dev->free_cnt == 0)
-        {
-            msgq_dev->timer_in_use = false;
-            return;
-        }
-        this_msg_buff = &msgq_dev->msg_buff_ring[i];
-
-        if (!this_msg_buff->using || !this_msg_buff->need_free)
-        {
-            continue;
-        }
-
-        if (this_msg_buff->timeout_cnt == 0)
-        {
-            *(this_msg_buff->data_len) = 0;
-            this_msg_buff->data = NULL;
-            msgq_dev->free_cnt--;
-            tx_timeouts++;
-            LOG_ERR("msg[%d] get callback out of time\n", i);
-            this_msg_buff->using = false;
-            continue;
-        }
-        this_msg_buff->timeout_cnt--;
-    }
-
-    u64_stats_update_begin(&msgq_dev->sq_priv->stats.syncp);
-    msgq_dev->sq_priv->stats.tx_timeouts += tx_timeouts;
-    u64_stats_update_end(&msgq_dev->sq_priv->stats.syncp);
-
-    mod_timer(this_timer, jiffies + msecs_to_jiffies(TIMER_DELAY_US));
+	struct msgq_dev *msgq_dev = from_timer(msgq_dev, this_timer, poll_timer);
+	struct msg_buff *this_msg_buff = NULL;
+	uint16_t i = 0;
+	uint32_t tx_timeouts = 0;
+
+	if (msgq_dev == NULL) {
+		LOG_ERR("msgq_dev is NULL\n");
+		return;
+	}
+
+	for (i = 0; i < MSGQ_MAX_MSG_BUFF_NUM; ++i) {
+		if (msgq_dev->free_cnt == 0) {
+			msgq_dev->timer_in_use = false;
+			return;
+		}
+		this_msg_buff = &msgq_dev->msg_buff_ring[i];
+
+		if (!this_msg_buff->using || !this_msg_buff->need_free) {
+			continue;
+		}
+
+		if (this_msg_buff->timeout_cnt == 0) {
+			*(this_msg_buff->data_len) = 0;
+			this_msg_buff->data = NULL;
+			msgq_dev->free_cnt--;
+			tx_timeouts++;
+			LOG_ERR("msg[%d] get callback out of time\n", i);
+			this_msg_buff->using = false;
+			continue;
+		}
+		this_msg_buff->timeout_cnt--;
+	}
+
+	u64_stats_update_begin(&msgq_dev->sq_priv->stats.syncp);
+	msgq_dev->sq_priv->stats.tx_timeouts += tx_timeouts;
+	u64_stats_update_end(&msgq_dev->sq_priv->stats.syncp);
+
+	mod_timer(this_timer, jiffies + msecs_to_jiffies(TIMER_DELAY_US));
 }
 
-static uint32_t msgq_get_mergeable_buf_len(struct receive_queue *rq, struct ewma_pkt_len *avg_pkt_len)
+static uint32_t msgq_get_mergeable_buf_len(struct receive_queue *rq,
+										   struct ewma_pkt_len *avg_pkt_len)
 {
-    const size_t hdr_len = PRIV_HEADER_LEN;
-    uint32_t len = 0;
+	const size_t hdr_len = PRIV_HEADER_LEN;
+	uint32_t len = 0;
 
-    len = hdr_len + clamp_t(uint32_t, ewma_pkt_len_read(avg_pkt_len), rq->min_buf_len, PAGE_SIZE - hdr_len);
+	len = hdr_len + clamp_t(uint32_t, ewma_pkt_len_read(avg_pkt_len),
+							rq->min_buf_len, PAGE_SIZE - hdr_len);
 
-    return ALIGN(len, L1_CACHE_BYTES);
+	return ALIGN(len, L1_CACHE_BYTES);
 }
 
 static int32_t msgq_add_recvbuf_mergeable(struct receive_queue *rq, gfp_t gfp)
 {
-    struct page_frag *alloc_frag = &rq->alloc_frag;
-    char *buf = NULL;
-    void *ctx = NULL;
-    int32_t err = 0;
-    uint32_t len = 0;
-    uint32_t hole = 0;
-
-    len = msgq_get_mergeable_buf_len(rq, &rq->mrg_avg_pkt_len);
-    if (unlikely(!skb_page_frag_refill(len, alloc_frag, gfp)))
-    {
-        return -ENOMEM;
-    }
-
-    buf = (char *)page_address(alloc_frag->page) + alloc_frag->offset;
-    get_page(alloc_frag->page);
-    alloc_frag->offset += len;
-    hole = alloc_frag->size - alloc_frag->offset;
-    if (hole < len)
-    {
-        len += hole;
-        alloc_frag->offset += hole;
-    }
-
-    sg_init_one(rq->sg, buf, len);
-    ctx = (void *)(unsigned long)len;
-    err = virtqueue_add_inbuf_ctx(rq->vq, rq->sg, 1, buf, ctx, gfp);
-    if (err < 0)
-    {
-        put_page(virt_to_head_page(buf));
-    }
-
-    return err;
+	struct page_frag *alloc_frag = &rq->alloc_frag;
+	char *buf = NULL;
+	void *ctx = NULL;
+	int32_t err = 0;
+	uint32_t len = 0;
+	uint32_t hole = 0;
+
+	len = msgq_get_mergeable_buf_len(rq, &rq->mrg_avg_pkt_len);
+	if (unlikely(!skb_page_frag_refill(len, alloc_frag, gfp))) {
+		return -ENOMEM;
+	}
+
+	buf = (char *)page_address(alloc_frag->page) + alloc_frag->offset;
+	get_page(alloc_frag->page);
+	alloc_frag->offset += len;
+	hole = alloc_frag->size - alloc_frag->offset;
+	if (hole < len) {
+		len += hole;
+		alloc_frag->offset += hole;
+	}
+
+	sg_init_one(rq->sg, buf, len);
+	ctx = (void *)(unsigned long)len;
+	err = virtqueue_add_inbuf_ctx(rq->vq, rq->sg, 1, buf, ctx, gfp);
+	if (err < 0) {
+		put_page(virt_to_head_page(buf));
+	}
+
+	return err;
 }
 
 static bool msgq_try_fill_recv(struct receive_queue *rq, gfp_t gfp)
 {
-    int32_t err = 0;
-    bool oom = 0;
-    unsigned long flags = 0;
-
-    do
-    {
-        err = msgq_add_recvbuf_mergeable(rq, gfp);
-        oom = err == -ENOMEM;
-        if (err)
-        {
-            break;
-        }
-    } while (rq->vq->num_free);
-
-    if (virtqueue_kick_prepare_packed(rq->vq) && virtqueue_notify(rq->vq))
-    {
-        flags = u64_stats_update_begin_irqsave(&rq->stats.syncp);
-        rq->stats.kicks++;
-        u64_stats_update_end_irqrestore(&rq->stats.syncp, flags);
-    }
-
-    return !oom;
+	int32_t err = 0;
+	bool oom = 0;
+	unsigned long flags = 0;
+
+	do {
+		err = msgq_add_recvbuf_mergeable(rq, gfp);
+		oom = err == -ENOMEM;
+		if (err) {
+			break;
+		}
+	} while (rq->vq->num_free);
+
+	if (virtqueue_kick_prepare_packed(rq->vq) && virtqueue_notify(rq->vq)) {
+		flags = u64_stats_update_begin_irqsave(&rq->stats.syncp);
+		rq->stats.kicks++;
+		u64_stats_update_end_irqrestore(&rq->stats.syncp, flags);
+	}
+
+	return !oom;
 }
 
 uint32_t msgq_mergeable_min_buf_len(struct virtqueue *vq)
 {
-    const uint32_t hdr_len = PRIV_HEADER_LEN;
-    uint32_t rq_size = virtqueue_get_vring_size(vq);
-    uint32_t min_buf_len = DIV_ROUND_UP(BUFF_LEN, rq_size);
+	const uint32_t hdr_len = PRIV_HEADER_LEN;
+	uint32_t rq_size = virtqueue_get_vring_size(vq);
+	uint32_t min_buf_len = DIV_ROUND_UP(BUFF_LEN, rq_size);
 
-    return max(max(min_buf_len, hdr_len) - hdr_len, (uint32_t)GOOD_PACKET_LEN);
+	return max(max(min_buf_len, hdr_len) - hdr_len, (uint32_t)GOOD_PACKET_LEN);
 }
 
-static int32_t msgq_privq_init(struct msgq_dev *msgq_dev, struct net_device *netdev)
+static int32_t msgq_privq_init(struct msgq_dev *msgq_dev,
+							   struct net_device *netdev)
 {
-    struct receive_queue *rq = msgq_dev->rq_priv;
-    struct send_queue *sq = msgq_dev->sq_priv;
-
-    rq->pages = NULL;
-    rq->min_buf_len = msgq_mergeable_min_buf_len(rq->vq);
-    netif_napi_add(netdev, &rq->napi, zxdh_msgq_poll, NAPI_POLL_WEIGHT);
-    netif_tx_napi_add(netdev, &sq->napi, NULL, NAPI_POLL_WEIGHT);
-
-    sg_init_table(rq->sg, ARRAY_SIZE(rq->sg));
-    ewma_pkt_len_init(&rq->mrg_avg_pkt_len);
-    sg_init_table(sq->sg, ARRAY_SIZE(sq->sg));
-
-    u64_stats_init(&rq->stats.syncp);
-    u64_stats_init(&sq->stats.syncp);
-
-    if (!msgq_try_fill_recv(rq, GFP_KERNEL))
-    {
-        LOG_ERR("msgq_try_fill_recv failed\n");
-        ZXDH_FREE_PTR(msgq_dev);
-        return MSGQ_RET_ERR_CHANNEL_NOT_READY;
-    }
-
-    msgq_dev->msgq_enable = true;
-    virtnet_napi_enable(rq->vq, &rq->napi);
-    LOG_INFO("zxdh_msgq_init success\n");
-    return MSGQ_RET_OK;
+	struct receive_queue *rq = msgq_dev->rq_priv;
+	struct send_queue *sq = msgq_dev->sq_priv;
+
+	rq->pages = NULL;
+	rq->min_buf_len = msgq_mergeable_min_buf_len(rq->vq);
+	netif_napi_add(netdev, &rq->napi, zxdh_msgq_poll, NAPI_POLL_WEIGHT);
+	netif_tx_napi_add(netdev, &sq->napi, NULL, NAPI_POLL_WEIGHT);
+
+	sg_init_table(rq->sg, ARRAY_SIZE(rq->sg));
+	ewma_pkt_len_init(&rq->mrg_avg_pkt_len); //
+	sg_init_table(sq->sg, ARRAY_SIZE(sq->sg));
+
+	u64_stats_init(&rq->stats.syncp);
+	u64_stats_init(&sq->stats.syncp);
+
+	if (!msgq_try_fill_recv(rq, GFP_KERNEL)) {
+		LOG_ERR("msgq_try_fill_recv failed\n");
+		ZXDH_FREE_PTR(msgq_dev);
+		return MSGQ_RET_ERR_CHANNEL_NOT_READY;
+	}
+
+	msgq_dev->msgq_enable = true;
+	virtnet_napi_enable(rq->vq, &rq->napi);
+	LOG_INFO("zxdh_msgq_init success\n");
+	return MSGQ_RET_OK;
 }
 
 int32_t zxdh_msgq_init(struct zxdh_en_device *en_dev)
 {
-    struct msgq_dev *msgq_dev = NULL;
-    int32_t idx = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-    en_dev->msgq_dev = kzalloc(sizeof(struct msgq_dev), GFP_KERNEL);
-    ZXDH_CHECK_PTR_RETURN(en_dev->msgq_dev);
-
-    idx = en_dev->max_queue_pairs - ZXDH_PQ_PAIRS_NUM;
-    msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
-    msgq_dev->sq_priv = &en_dev->sq[idx];
-    msgq_dev->rq_priv = &en_dev->rq[idx];
-    msgq_dev->msgq_vfid = (uint16_t)VQM_VFID(en_dev->vport);
-    msgq_dev->msgq_rqid = (uint16_t)msgq_dev->rq_priv->vq->phy_index;
-
-    dpp_vport_create_by_vqm_vfid(&pf_info, RISCV_COMMON_VFID);
-    spin_lock_init(&msgq_dev->sn_lock);
-    spin_lock_init(&msgq_dev->tx_lock);
-    mutex_init(&msgq_dev->mlock);
-    timer_setup(&msgq_dev->poll_timer, poll_timer_callback, 0);
-
-    return msgq_privq_init(msgq_dev, en_dev->netdev);
+	struct msgq_dev *msgq_dev = NULL;
+	int32_t idx = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+	en_dev->msgq_dev = kzalloc(sizeof(struct msgq_dev), GFP_KERNEL);
+	ZXDH_CHECK_PTR_RETURN(en_dev->msgq_dev);
+
+	idx = en_dev->max_queue_pairs - ZXDH_PQ_PAIRS_NUM;
+	msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
+	msgq_dev->sq_priv = &en_dev->sq[idx];
+	msgq_dev->rq_priv = &en_dev->rq[idx];
+	msgq_dev->msgq_vfid = (uint16_t)VQM_VFID(en_dev->vport);
+	msgq_dev->msgq_rqid = (uint16_t)msgq_dev->rq_priv->vq->phy_index;
+
+	dpp_vport_create_by_vqm_vfid(&pf_info, RISCV_COMMON_VFID);
+	spin_lock_init(&msgq_dev->sn_lock);
+	spin_lock_init(&msgq_dev->tx_lock);
+	mutex_init(&msgq_dev->mlock);
+	timer_setup(&msgq_dev->poll_timer, poll_timer_callback, 0);
+
+	return msgq_privq_init(msgq_dev, en_dev->netdev);
 }
 
 void zxdh_msgq_exit(struct zxdh_en_device *en_dev)
 {
-    struct msgq_dev *msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
+	struct msgq_dev *msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
 
-    if (msgq_dev == NULL)
-    {
-        LOG_ERR("msgq_dev is null!\n");
-        return;
-    }
+	if (msgq_dev == NULL) {
+		LOG_ERR("msgq_dev is null!\n");
+		return;
+	}
 
-    msgq_dev->msgq_enable = false;
-    napi_disable(&msgq_dev->rq_priv->napi);
-    del_timer(&msgq_dev->poll_timer);
+	msgq_dev->msgq_enable = false;
+	napi_disable(&msgq_dev->rq_priv->napi);
+	del_timer(&msgq_dev->poll_timer);
 
-    ZXDH_FREE_PTR(msgq_dev);
-    LOG_INFO("zxdh_msg_chan_pkt remove success\n");
+	ZXDH_FREE_PTR(msgq_dev);
+	LOG_INFO("zxdh_msg_chan_pkt remove success\n");
 }
 
 void msgq_print_data(uint8_t *buf, uint32_t len, uint8_t flag)
 {
-    uint32_t print_len = 0;
-
-    if (flag == MSGQ_PRINT_HDR)
-    {
-        print_len = PRIV_HEADER_LEN;
-    }
-    else if (flag == MSGQ_PRINT_128B)
-    {
-        print_len = len > 128 ? 128 : len;
-    }
-    else if (flag == MSGQ_PRINT_ALL)
-    {
-        print_len = len;
-    }
-    print_data(buf, print_len);
+	uint32_t print_len = 0;
+
+	if (flag == MSGQ_PRINT_HDR) {
+		print_len = PRIV_HEADER_LEN;
+	} else if (flag == MSGQ_PRINT_128B) {
+		print_len = len > 128 ? 128 : len;
+	} else if (flag == MSGQ_PRINT_ALL) {
+		print_len = len;
+	}
+	print_data(buf, print_len);
 }
 
-static int32_t zxdh_msg_para_check(struct msgq_pkt_info *msg, struct reps_info *reps)
+static int32_t zxdh_msg_para_check(struct msgq_pkt_info *msg,
+								   struct reps_info *reps)
 {
-    ZXDH_CHECK_PTR_RETURN(msg);
-    ZXDH_CHECK_PTR_RETURN(msg->addr);
-
-    if ((msg->len == 0) || (msg->len > MSGQ_MAX_ADDR_LEN))
-    {
-        LOG_ERR("invalid data_len: %d\n", msg->len);
-        goto free_addr;
-    }
-
-    if (msg->event_id >= MSG_MODULE_NUM)
-    {
-        LOG_ERR("invalid event_id\n");
-        goto free_addr;
-    }
-
-    if (msg->no_reps)
-    {
-        return MSGQ_RET_OK;
-    }
-
-    ZXDH_CHECK_PTR_GOTO_ERR(reps, free_addr);
-    ZXDH_CHECK_PTR_GOTO_ERR(reps->addr, free_addr);
-    if (reps->len == 0)
-    {
-        LOG_ERR("invalid reps_len: %d\n", reps->len);
-        goto free_addr;
-    }
-
-    return MSGQ_RET_OK;
+	ZXDH_CHECK_PTR_RETURN(msg);
+	ZXDH_CHECK_PTR_RETURN(msg->addr);
+
+	if ((msg->len == 0) || (msg->len > MSGQ_MAX_ADDR_LEN)) {
+		LOG_ERR("invalid data_len: %d\n", msg->len);
+		goto free_addr;
+	}
+
+	if (msg->event_id >= MSG_MODULE_NUM) {
+		LOG_ERR("invalid event_id\n");
+		goto free_addr;
+	}
+
+	if (msg->no_reps) {
+		return MSGQ_RET_OK;
+	}
+
+	ZXDH_CHECK_PTR_GOTO_ERR(reps, free_addr);
+	ZXDH_CHECK_PTR_GOTO_ERR(reps->addr, free_addr);
+	if (reps->len == 0) {
+		LOG_ERR("invalid reps_len: %d\n", reps->len);
+		goto free_addr;
+	}
+
+	return MSGQ_RET_OK;
 free_addr:
-    ZXDH_FREE_PTR(msg->addr);
-    return MSGQ_RET_ERR_INVALID_PARA;
+	ZXDH_FREE_PTR(msg->addr);
+	return MSGQ_RET_ERR_INVALID_PARA;
 }
 
-static int32_t zxdh_sequence_num_get(struct msgq_dev *msgq_dev, uint16_t *sequence_num)
+static int32_t zxdh_sequence_num_get(struct msgq_dev *msgq_dev,
+									 uint16_t *sequence_num)
 {
-    uint16_t sn = 0;
-    uint16_t loop = 0;
-
-    spin_lock(&msgq_dev->sn_lock);
-    sn = msgq_dev->sequence_num;
-
-    for (loop = 0; loop < MSGQ_MAX_MSG_BUFF_NUM; loop++)
-    {
-        if (!msgq_dev->msg_buff_ring[sn].using)
-        {
-            *sequence_num = sn;
-            msgq_dev->msg_buff_ring[sn].using = true;
-            msgq_dev->msg_buff_ring[sn].valid = false;
-            msgq_dev->free_cnt++;
-            SEQUENCE_NUM_ADD(sn);
-            break;
-        }
-        SEQUENCE_NUM_ADD(sn);
-    }
-
-    msgq_dev->sequence_num = sn;
-    spin_unlock(&msgq_dev->sn_lock);
-
-    if (loop == MSGQ_MAX_MSG_BUFF_NUM)
-    {
-        return MSGQ_RET_ERR_CHAN_BUSY;
-    }
-
-    return MSGQ_RET_OK;
+	uint16_t sn = 0;
+	uint16_t loop = 0;
+
+	spin_lock(&msgq_dev->sn_lock);
+	sn = msgq_dev->sequence_num;
+
+	for (loop = 0; loop < MSGQ_MAX_MSG_BUFF_NUM; loop++) {
+		if (!msgq_dev->msg_buff_ring[sn].using) {
+			*sequence_num = sn;
+			msgq_dev->msg_buff_ring[sn].using = true;
+			msgq_dev->msg_buff_ring[sn].valid = false;
+			msgq_dev->free_cnt++;
+			SEQUENCE_NUM_ADD(sn);
+			break;
+		}
+		SEQUENCE_NUM_ADD(sn);
+	}
+
+	msgq_dev->sequence_num = sn;
+	spin_unlock(&msgq_dev->sn_lock);
+
+	if (loop == MSGQ_MAX_MSG_BUFF_NUM) {
+		return MSGQ_RET_ERR_CHAN_BUSY;
+	}
+
+	return MSGQ_RET_OK;
 }
 
-static int32_t page_send_cmd(struct send_queue *sq, uint8_t *buf, uint16_t buf_len, uint8_t print)
+static int32_t page_send_cmd(struct send_queue *sq, uint8_t *buf,
+							 uint16_t buf_len, uint8_t print)
 {
-    uint16_t i = 0;
-    int32_t err = 0;
-    uint16_t total_sg = 0;
-    uint16_t last_buff_len = 0;
-
-    if (print != 0)
-    {
-        LOG_DEBUG("send pkt start\n");
-        msgq_print_data(buf, buf_len, print);
-    }
-
-    total_sg = buf_len / BUFF_LEN;
-    last_buff_len = buf_len % BUFF_LEN;
-    if (last_buff_len != 0)
-    {
-        total_sg += 1;
-    }
-
-    sg_init_table(sq->sg, total_sg);
-    for (i = 0; i < total_sg; ++i)
-    {
-        if (i == (total_sg - 1))
-        {
-            sg_set_buf(&sq->sg[i], buf + (i * BUFF_LEN), ((last_buff_len != 0) ? (last_buff_len) : (BUFF_LEN)));
-        }
-        else
-        {
-            sg_set_buf(&sq->sg[i], buf + (i * BUFF_LEN), BUFF_LEN);
-        }
-    }
-
-    err = virtqueue_add_outbuf(sq->vq, sq->sg, total_sg, buf, GFP_ATOMIC);
-    ZXDH_CHECK_RET_GOTO_ERR(err, free_addr, "virtqueue_add_outbuf failed: %d\n", err);
-
-    if (virtqueue_kick_prepare_packed(sq->vq) && virtqueue_notify(sq->vq))
-    {
-        u64_stats_update_begin(&sq->stats.syncp);
-        sq->stats.kicks++;
-        u64_stats_update_end(&sq->stats.syncp);
-    }
-    return err;
+	uint16_t i = 0;
+	int32_t err = 0;
+	uint16_t total_sg = 0;
+	uint16_t last_buff_len = 0;
+
+	if (print != 0) {
+		LOG_DEBUG("send pkt start\n");
+		msgq_print_data(buf, buf_len, print);
+	}
+
+	total_sg = buf_len / BUFF_LEN;
+	last_buff_len = buf_len % BUFF_LEN;
+	if (last_buff_len != 0) {
+		total_sg += 1;
+	}
+
+	sg_init_table(sq->sg, total_sg);
+	for (i = 0; i < total_sg; ++i) {
+		if (i == (total_sg - 1)) {
+			sg_set_buf(&sq->sg[i], buf + (i * BUFF_LEN),
+					   ((last_buff_len != 0) ? (last_buff_len) : (BUFF_LEN)));
+		} else {
+			sg_set_buf(&sq->sg[i], buf + (i * BUFF_LEN), BUFF_LEN);
+		}
+	}
+
+	err = virtqueue_add_outbuf(sq->vq, sq->sg, total_sg, buf, GFP_ATOMIC);
+	ZXDH_CHECK_RET_GOTO_ERR(err, free_addr, "virtqueue_add_outbuf failed: %d\n",
+							err);
+
+	if (virtqueue_kick_prepare_packed(sq->vq) && virtqueue_notify(sq->vq)) {
+		u64_stats_update_begin(&sq->stats.syncp);
+		sq->stats.kicks++;
+		u64_stats_update_end(&sq->stats.syncp);
+	}
+	return err;
 
 free_addr:
-    return MSGQ_RET_ERR_VQ_BROKEN;
+	return MSGQ_RET_ERR_VQ_BROKEN;
 }
 
-static int32_t zxdh_msgq_pkt_send(struct msgq_dev *msgq_dev, \
-                struct msgq_pkt_info *pkt_info, uint16_t sn)
+static int32_t zxdh_msgq_pkt_send(struct msgq_dev *msgq_dev,
+								  struct msgq_pkt_info *pkt_info, uint16_t sn)
 {
-    struct priv_queues_net_hdr *hdr = (struct priv_queues_net_hdr *)pkt_info->addr;
-    void *buf = NULL;
-    uint32_t len = 0;
-
-    if (spin_trylock(&msgq_dev->tx_lock))
-    {
-        while ((buf = virtqueue_get_buf(msgq_dev->sq_priv->vq, &len)) != NULL)
-        {
-            ZXDH_FREE_PTR(buf);
-        };
-        spin_unlock(&msgq_dev->tx_lock);
-    }
-
-    memset(hdr, 0, PRIV_HEADER_LEN);
-    hdr->tx_port = TX_PORT_NP;
-    hdr->pd_len = PRIV_HEADER_LEN / 2;
-    hdr->pi_hdr.pi_type = DEFAULT_PI_TYPE;
-    hdr->pi_hdr.pkt_type = CONTROL_MSG_TYPE;
-    hdr->pi_hdr.vfid_dst = htons(RISCV_COMMON_VFID);
-    hdr->pi_hdr.qid_dst = htons(RISCV_COMMON_QID);
-    hdr->pi_hdr.vfid_src = htons(msgq_dev->msgq_vfid);
-    hdr->pi_hdr.qid_src = htons(msgq_dev->msgq_rqid);
-    hdr->pi_hdr.event_id = pkt_info->event_id;
-    hdr->pi_hdr.sequence_num = sn;
-    if (sn == NO_REPS_SEQUENCE_NUM)
-    {
-        hdr->pi_hdr.msg_type = NO_REPS_MSG;
-    }
-    if (msgq_dev->loopback)
-    {
-        hdr->pi_hdr.event_id = MODULE_MSGQ;
-        hdr->pi_hdr.vfid_dst = hdr->pi_hdr.vfid_src;
-        hdr->pi_hdr.qid_dst = hdr->pi_hdr.qid_src;
-    }
-
-    return page_send_cmd(msgq_dev->sq_priv, pkt_info->addr, \
-            pkt_info->len, msgq_dev->print_flag);
+	struct priv_queues_net_hdr *hdr =
+			(struct priv_queues_net_hdr *)pkt_info->addr;
+	void *buf = NULL;
+	uint32_t len = 0;
+
+	if (spin_trylock(&msgq_dev->tx_lock)) {
+		while ((buf = virtqueue_get_buf(msgq_dev->sq_priv->vq, &len)) != NULL) {
+			ZXDH_FREE_PTR(buf);
+		};
+		spin_unlock(&msgq_dev->tx_lock);
+	}
+
+	memset(hdr, 0, PRIV_HEADER_LEN);
+	hdr->tx_port = TX_PORT_NP;
+	hdr->pd_len = PRIV_HEADER_LEN / 2;
+	hdr->pi_hdr.pi_type = DEFAULT_PI_TYPE;
+	hdr->pi_hdr.pkt_type = CONTROL_MSG_TYPE;
+	hdr->pi_hdr.vfid_dst = htons(RISCV_COMMON_VFID);
+	hdr->pi_hdr.qid_dst = htons(RISCV_COMMON_QID);
+	hdr->pi_hdr.vfid_src = htons(msgq_dev->msgq_vfid);
+	hdr->pi_hdr.qid_src = htons(msgq_dev->msgq_rqid);
+	hdr->pi_hdr.event_id = pkt_info->event_id;
+	hdr->pi_hdr.sequence_num = sn;
+	if (sn == NO_REPS_SEQUENCE_NUM) {
+		hdr->pi_hdr.msg_type = NO_REPS_MSG;
+	}
+	if (msgq_dev->loopback) {
+		hdr->pi_hdr.event_id = MODULE_MSGQ;
+		hdr->pi_hdr.vfid_dst = hdr->pi_hdr.vfid_src;
+		hdr->pi_hdr.qid_dst = hdr->pi_hdr.qid_src;
+	}
+
+	return page_send_cmd(msgq_dev->sq_priv, pkt_info->addr, pkt_info->len,
+						 msgq_dev->print_flag);
 }
 
-int32_t zxdh_msgq_send_cmd(struct msgq_dev *msgq_dev, \
-            struct msgq_pkt_info *pkt_info, struct reps_info *reps)
+int32_t zxdh_msgq_send_cmd(struct msgq_dev *msgq_dev,
+						   struct msgq_pkt_info *pkt_info,
+						   struct reps_info *reps)
 {
-    uint16_t sn = NO_REPS_SEQUENCE_NUM;
-    uint16_t sync_poll_cnt = 0;
-    int32_t err = 0;
-    int32_t i = 0;
-    uint32_t tx_timeouts = 0;
-    uint32_t tx_errs = 0;
-
-    err = zxdh_msg_para_check(pkt_info, reps);
-    ZXDH_CHECK_RET_GOTO_ERR(err, tx_err, "zxdh_msg_para_check failed: %d\n", err);
-
-    ZXDH_CHECK_PTR_GOTO_ERR(msgq_dev, free_addr);
-    CHECK_CHANNEL_USABLE(msgq_dev, err, free_addr);
-
-    if (!pkt_info->no_reps)
-    {
-        err = zxdh_sequence_num_get(msgq_dev, &sn);
-        ZXDH_CHECK_RET_GOTO_ERR(err, free_addr, \
-            "zxdh_sequence_num_get failed: %d\n", err);
-    }
-
-    mutex_lock(&msgq_dev->mlock);
-    err = zxdh_msgq_pkt_send(msgq_dev, pkt_info, sn);
-    mutex_unlock(&msgq_dev->mlock);
-    ZXDH_CHECK_RET_GOTO_ERR(err, free_addr, "zxdh_msgq_pkt_send failed: %d\n", err);
-
-    if (pkt_info->no_reps)
-    {
-        return MSGQ_RET_OK;
-    }
-
-    msgq_dev->msg_buff_ring[sn].data = &reps->addr;
-    msgq_dev->msg_buff_ring[sn].data_len = &reps->len;
-    msgq_dev->msg_buff_ring[sn].timeout_cnt = pkt_info->timeout_us / TIMER_DELAY_US;
-    if (!pkt_info->is_async)
-    {
-        sync_poll_cnt = pkt_info->timeout_us / 10;
-        for (i = 0; i < sync_poll_cnt; ++i)
-        {
-            usleep_range(5, 10);
-            if (!msgq_dev->msg_buff_ring[sn].using &&
-                msgq_dev->msg_buff_ring[sn].valid)
-            {
-                return MSGQ_RET_OK;
-            }
-        }
-        err = MSGQ_RET_ERR_CALLBACK_OUT_OF_TIME;
-        goto free_sn;
-    }
-    else
-    {
-        msgq_dev->msg_buff_ring[sn].need_free = true;
-        if (!msgq_dev->timer_in_use)
-        {
-            mod_timer(&msgq_dev->poll_timer, jiffies + usecs_to_jiffies(TIMER_DELAY_US));
-            msgq_dev->timer_in_use = true;
-        }
-    }
-    return MSGQ_RET_OK;
+	uint16_t sn = NO_REPS_SEQUENCE_NUM;
+	uint16_t sync_poll_cnt = 0;
+	int32_t err = 0;
+	int32_t i = 0;
+	uint32_t tx_timeouts = 0;
+	uint32_t tx_errs = 0;
+
+	err = zxdh_msg_para_check(pkt_info, reps);
+	ZXDH_CHECK_RET_GOTO_ERR(err, tx_err, "zxdh_msg_para_check failed: %d\n",
+							err);
+
+	ZXDH_CHECK_PTR_GOTO_ERR(msgq_dev, free_addr);
+	CHECK_CHANNEL_USABLE(msgq_dev, err, free_addr);
+
+	if (!pkt_info->no_reps) {
+		err = zxdh_sequence_num_get(msgq_dev, &sn);
+		ZXDH_CHECK_RET_GOTO_ERR(err, free_addr,
+								"zxdh_sequence_num_get failed: %d\n", err);
+	}
+
+	mutex_lock(&msgq_dev->mlock);
+	err = zxdh_msgq_pkt_send(msgq_dev, pkt_info, sn);
+	mutex_unlock(&msgq_dev->mlock);
+	ZXDH_CHECK_RET_GOTO_ERR(err, free_addr, "zxdh_msgq_pkt_send failed: %d\n",
+							err);
+
+	if (pkt_info->no_reps) {
+		return MSGQ_RET_OK;
+	}
+
+	msgq_dev->msg_buff_ring[sn].data = &reps->addr;
+	msgq_dev->msg_buff_ring[sn].data_len = &reps->len;
+	msgq_dev->msg_buff_ring[sn].timeout_cnt =
+			pkt_info->timeout_us / TIMER_DELAY_US;
+	if (!pkt_info->is_async) {
+		sync_poll_cnt = pkt_info->timeout_us / 10;
+		for (i = 0; i < sync_poll_cnt; ++i) {
+			usleep_range(5, 10);
+			if (!msgq_dev->msg_buff_ring[sn].using &&
+				msgq_dev->msg_buff_ring[sn].valid) {
+				return MSGQ_RET_OK;
+			}
+		}
+		err = MSGQ_RET_ERR_CALLBACK_OUT_OF_TIME;
+		goto free_sn;
+	} else {
+		msgq_dev->msg_buff_ring[sn].need_free = true;
+		if (!msgq_dev->timer_in_use) {
+			mod_timer(&msgq_dev->poll_timer,
+					  jiffies + usecs_to_jiffies(TIMER_DELAY_US));
+			msgq_dev->timer_in_use = true;
+		}
+	}
+	return MSGQ_RET_OK;
 
 free_addr:
-    ZXDH_FREE_PTR(pkt_info->addr);
+	ZXDH_FREE_PTR(pkt_info->addr);
 tx_err:
-    tx_errs++;
+	tx_errs++;
 free_sn:
-    if ((sn != NO_REPS_SEQUENCE_NUM) && (sn < MSGQ_MAX_MSG_BUFF_NUM))
-    {
-        LOG_ERR("timeout, sn[%d] is free\n", sn);
-        msgq_dev->msg_buff_ring[sn].using = false;
-        tx_timeouts++;
-        msgq_dev->free_cnt--;
-    }
-    u64_stats_update_begin(&msgq_dev->sq_priv->stats.syncp);
-    msgq_dev->sq_priv->stats.xdp_tx_drops += tx_errs;
-    msgq_dev->sq_priv->stats.tx_timeouts += tx_timeouts;
-    u64_stats_update_end(&msgq_dev->sq_priv->stats.syncp);
-    return err;
+	if (sn != NO_REPS_SEQUENCE_NUM) {
+		LOG_ERR("timeout, sn[%d] is free\n", sn);
+		msgq_dev->msg_buff_ring[sn].using = false;
+		tx_timeouts++;
+		msgq_dev->free_cnt--;
+	}
+	u64_stats_update_begin(&msgq_dev->sq_priv->stats.syncp);
+	msgq_dev->sq_priv->stats.xdp_tx_drops += tx_errs;
+	msgq_dev->sq_priv->stats.tx_timeouts += tx_timeouts;
+	u64_stats_update_end(&msgq_dev->sq_priv->stats.syncp);
+	return err;
 }
 
 static void zxdh_swap_dst_and_src(uint16_t *dst, uint16_t *src)
 {
-    uint16_t temp = 0;
+	uint16_t temp = 0;
 
-    temp = *dst;
-    *dst = *src;
-    *src = temp;
+	temp = *dst;
+	*dst = *src;
+	*src = temp;
 }
 
 static int32_t zxdh_pi_header_check(struct pi_header *hdr)
 {
-    if (hdr->pi_type != DEFAULT_PI_TYPE)
-    {
-        LOG_ERR("INVALID_PI_TYPE: %d\n", hdr->pi_type);
-        return MSGQ_RET_ERR_CALLBACK_FAIL;
-    }
-
-    if (hdr->pkt_type != CONTROL_MSG_TYPE)
-    {
-        LOG_ERR("INVALID_PKT_TYPE: %d\n", hdr->pkt_type);
-        return MSGQ_RET_ERR_CALLBACK_FAIL;
-    }
-
-    if (hdr->msg_type > NO_REPS_MSG)
-    {
-        LOG_ERR("INVALID_MSG_TYPE: %d\n", hdr->msg_type);
-        return MSGQ_RET_ERR_CALLBACK_FAIL;
-    }
-
-    if (hdr->event_id >= MSG_MODULE_NUM)
-    {
-        LOG_ERR("INVALID_MSG_MODULE_ID: %d\n", hdr->event_id);
-        return MSGQ_RET_ERR_CALLBACK_FAIL;
-    }
-
-    if (hdr->err_code != MSGQ_RET_OK)
-    {
-        LOG_ERR("MSG_ERR_CODE: %d\n", hdr->err_code);
-        return MSGQ_RET_ERR_CALLBACK_FAIL;
-    }
-
-    return MSGQ_RET_OK;
+	if (hdr->pi_type != DEFAULT_PI_TYPE) {
+		LOG_ERR("INVALID_PI_TYPE: %d\n", hdr->pi_type);
+		return MSGQ_RET_ERR_CALLBACK_FAIL;
+	}
+
+	if (hdr->pkt_type != CONTROL_MSG_TYPE) {
+		LOG_ERR("INVALID_PKT_TYPE: %d\n", hdr->pkt_type);
+		return MSGQ_RET_ERR_CALLBACK_FAIL;
+	}
+
+	if (hdr->msg_type > NO_REPS_MSG) {
+		LOG_ERR("INVALID_MSG_TYPE: %d\n", hdr->msg_type);
+		return MSGQ_RET_ERR_CALLBACK_FAIL;
+	}
+
+	if (hdr->event_id >= MSG_MODULE_NUM) {
+		LOG_ERR("INVALID_MSG_MODULE_ID: %d\n", hdr->event_id);
+		return MSGQ_RET_ERR_CALLBACK_FAIL;
+	}
+
+	if (hdr->err_code != MSGQ_RET_OK) {
+		LOG_ERR("MSG_ERR_CODE: %d\n", hdr->err_code);
+		return MSGQ_RET_ERR_CALLBACK_FAIL;
+	}
+
+	return MSGQ_RET_OK;
 }
 
 static void rx_free_pages(struct msgq_dev *msgq_dev, void *buf, uint32_t len)
 {
-    if (msgq_dev->print_flag == MSGQ_PRINT_ALL)
-    {
-        print_data((uint8_t *)buf, len);
-        LOG_DEBUG("buf: 0x%llx refcnt: %d\n", (uint64_t)buf, \
-                        page_ref_count(virt_to_head_page(buf)));
-    }
-    put_page(virt_to_head_page(buf));
+	if (msgq_dev->print_flag == MSGQ_PRINT_ALL) {
+		print_data((uint8_t *)buf, len);
+		LOG_DEBUG("buf: 0x%llx refcnt: %d\n", (uint64_t)buf,
+				  page_ref_count(virt_to_head_page(buf)));
+	}
+	put_page(virt_to_head_page(buf));
 }
 
-static int32_t zxdh_response_msg_handle(struct msgq_dev *msgq_dev, \
-        struct virtnet_rq_stats *stats, uint16_t num_buf, void *buf, uint32_t len)
+static int32_t zxdh_response_msg_handle(struct msgq_dev *msgq_dev,
+										struct virtnet_rq_stats *stats,
+										uint16_t num_buf, void *buf,
+										uint32_t len)
 {
-    struct priv_queues_net_hdr *hdr = (struct priv_queues_net_hdr *)buf;
-    uint16_t sn = hdr->pi_hdr.sequence_num;
-    int32_t err = MSGQ_RET_OK;
-    struct msg_buff *tmp_buff = NULL;
-    uint32_t max_len = 0;
-    uint32_t pkt_len = 0;
-
-    if (sn >= MSGQ_MAX_MSG_BUFF_NUM)
-    {
-        LOG_ERR("INVALID_SEQUENCE_NUM: %d\n", sn);
-        err = MSGQ_RET_ERR;
-        goto put_page;
-    }
-
-    tmp_buff = &msgq_dev->msg_buff_ring[sn];
-    if (!tmp_buff->using)
-    {
-        LOG_ERR("buff[%d] is free\n", sn);
-        err = MSGQ_RET_ERR_CALLBACK_OUT_OF_TIME;
-        goto put_page;
-    }
-    ZXDH_CHECK_PTR_GOTO_ERR(*tmp_buff->data, put_page);
-
-    max_len = *(tmp_buff->data_len);
-    pkt_len = len - PRIV_HEADER_LEN;
-    if (pkt_len > max_len)
-    {
-        LOG_ERR("buf_len: %d > tmp_buff->data_len: %d\n", pkt_len, max_len);
-        err = MSGQ_RET_ERR_REPS_LEN_NOT_ENOUGH;
-        goto put_page;
-    }
-
-    memcpy(*tmp_buff->data, (uint8_t *)buf + PRIV_HEADER_LEN, pkt_len);
-    while (--num_buf != 0)
-    {
-        rx_free_pages(msgq_dev, buf, len);
-        buf = virtqueue_get_buf(msgq_dev->rq_priv->vq, &len);
-        if (unlikely(buf == NULL))
-        {
-            LOG_ERR("msgq rx error: %dth buffers missing\n", num_buf);
-            stats->drops++;
-            err = MSGQ_RET_ERR_RX_INVALID_NUM_BUF;
-            goto out;
-        }
-
-        if ((len + pkt_len) > max_len)
-        {
-            LOG_ERR("buf_len: %d > tmp_buff->data_len: %d\n", len + pkt_len, max_len);
-            err = MSGQ_RET_ERR_REPS_LEN_NOT_ENOUGH;
-            goto put_page;
-        }
-
-        stats->bytes += len;
-        memcpy((*tmp_buff->data) + pkt_len, buf, len);
-        pkt_len += len;
-    }
-    *(tmp_buff->data_len) = pkt_len;
-    tmp_buff->valid = true;
-    stats->xdp_drops--;
+	struct priv_queues_net_hdr *hdr = (struct priv_queues_net_hdr *)buf;
+	uint16_t sn = hdr->pi_hdr.sequence_num;
+	int32_t err = MSGQ_RET_OK;
+	struct msg_buff *tmp_buff = NULL;
+	uint32_t max_len = 0;
+	uint32_t pkt_len = 0;
+
+	if (sn >= MSGQ_MAX_MSG_BUFF_NUM) {
+		LOG_ERR("INVALID_SEQUENCE_NUM: %d\n", sn);
+		err = MSGQ_RET_ERR;
+		goto put_page;
+	}
+
+	tmp_buff = &msgq_dev->msg_buff_ring[sn];
+	if (!tmp_buff->using) {
+		LOG_ERR("buff[%d] is free\n", sn);
+		err = MSGQ_RET_ERR_CALLBACK_OUT_OF_TIME;
+		goto put_page;
+	}
+	ZXDH_CHECK_PTR_GOTO_ERR(*tmp_buff->data, put_page);
+
+	max_len = *(tmp_buff->data_len);
+	pkt_len = len - PRIV_HEADER_LEN;
+	if (pkt_len > max_len) {
+		LOG_ERR("buf_len: %d > tmp_buff->data_len: %d\n", pkt_len, max_len);
+		err = MSGQ_RET_ERR_REPS_LEN_NOT_ENOUGH;
+		goto put_page;
+	}
+
+	memcpy(*tmp_buff->data, (uint8_t *)buf + PRIV_HEADER_LEN, pkt_len);
+	while (--num_buf != 0) {
+		rx_free_pages(msgq_dev, buf, len);
+		buf = virtqueue_get_buf(msgq_dev->rq_priv->vq, &len);
+		if (unlikely(buf == NULL)) {
+			LOG_ERR("msgq rx error: %dth buffers missing\n", num_buf);
+			stats->drops++;
+			err = MSGQ_RET_ERR_RX_INVALID_NUM_BUF;
+			goto out;
+		}
+
+		if ((len + pkt_len) > max_len) {
+			LOG_ERR("buf_len: %d > tmp_buff->data_len: %d\n", len + pkt_len,
+					max_len);
+			err = MSGQ_RET_ERR_REPS_LEN_NOT_ENOUGH;
+			goto put_page;
+		}
+
+		stats->bytes += len;
+		memcpy((*tmp_buff->data) + pkt_len, buf, len);
+		pkt_len += len;
+	}
+	*(tmp_buff->data_len) = pkt_len;
+	tmp_buff->valid = true;
+	stats->xdp_drops--;
 
 put_page:
-    put_page(virt_to_head_page(buf));
+	put_page(virt_to_head_page(buf));
 out:
-    if (tmp_buff != NULL)
-    {
-        tmp_buff->using = false;
-        tmp_buff->data = NULL;
-        msgq_dev->free_cnt--;
-    }
-    return err;
+	tmp_buff->using = false;
+	msgq_dev->free_cnt--;
+	tmp_buff->data = NULL;
+	return err;
 }
 
-static int32_t zxdh_callback_msg_handle(struct zxdh_en_device *en_dev, \
-                                uint8_t *buf_addr, uint32_t buf_len)
+static int32_t zxdh_callback_msg_handle(struct zxdh_en_device *en_dev,
+										uint8_t *buf_addr, uint32_t buf_len)
 {
-    struct msgq_dev *msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
-    int32_t err = BAR_MSG_ERR_MODULE_NOEXIST;
-    uint8_t *reps_addr = NULL;
-    uint16_t reps_len = MAX_PACKET_LEN;
-    uint16_t hdr_len = PRIV_HEADER_LEN;
-    struct priv_queues_net_hdr *hdr = NULL;
-
-    hdr = (struct priv_queues_net_hdr *)buf_addr;
-    if (hdr->pi_hdr.msg_type == NO_REPS_MSG)
-    {
-        return call_msg_recv_func_tbl(hdr->pi_hdr.event_id, \
-        buf_addr + hdr_len, buf_len - hdr_len, NULL, 0, en_dev);
-    }
-
-    reps_addr = kzalloc(MSGQ_MAX_ADDR_LEN, GFP_ATOMIC);
-    ZXDH_CHECK_PTR_RETURN(reps_addr);
-    memcpy(reps_addr, buf_addr, hdr_len);
-    hdr = (struct priv_queues_net_hdr *)reps_addr;
-
-    if (hdr->pi_hdr.event_id < MSG_MODULE_NUM)
-    {
-        err = call_msg_recv_func_tbl(hdr->pi_hdr.event_id, \
-                buf_addr + hdr_len, buf_len - hdr_len, \
-                reps_addr + hdr_len, &reps_len, en_dev);
-        hdr->pi_hdr.msg_type = ACK_MSG;
-    }
-
-    if (err == BAR_MSG_ERR_MODULE_NOEXIST)
-    {
-        hdr->pi_hdr.err_code = ERR_CODE_EVENT_UNREGIST;
-    }
-    else if ((err != MSGQ_RET_OK) || (reps_len > MAX_PACKET_LEN))
-    {
-        LOG_ERR("get reps failed, reps_len:%d\n", reps_len);
-        hdr->pi_hdr.err_code = ERR_CODE_EVENT_FAIL;
-    }
-
-    zxdh_swap_dst_and_src(&hdr->pi_hdr.vfid_dst, &hdr->pi_hdr.vfid_src);
-    zxdh_swap_dst_and_src(&hdr->pi_hdr.qid_dst, &hdr->pi_hdr.qid_src);
-
-    return page_send_cmd(msgq_dev->sq_priv, \
-        reps_addr, reps_len + hdr_len, msgq_dev->print_flag);
+	struct msgq_dev *msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
+	int32_t err = MSGQ_RET_OK;
+	uint8_t *reps_addr = NULL;
+	uint16_t reps_len = MAX_PACKET_LEN;
+	uint16_t hdr_len = PRIV_HEADER_LEN;
+	struct priv_queues_net_hdr *hdr = NULL;
+
+	reps_addr = kzalloc(MSGQ_MAX_ADDR_LEN, GFP_ATOMIC);
+	ZXDH_CHECK_PTR_RETURN(reps_addr);
+	memcpy(reps_addr, buf_addr, hdr_len);
+	hdr = (struct priv_queues_net_hdr *)reps_addr;
+
+	if (hdr->pi_hdr.msg_type == NO_REPS_MSG) {
+		return call_msg_recv_func_tbl(hdr->pi_hdr.event_id, buf_addr + hdr_len,
+									  buf_len - hdr_len, NULL, 0, en_dev);
+	}
+
+	err = call_msg_recv_func_tbl(hdr->pi_hdr.event_id, buf_addr + hdr_len,
+								 buf_len - hdr_len, reps_addr + hdr_len,
+								 &reps_len, en_dev);
+	hdr->pi_hdr.msg_type = ACK_MSG;
+
+	if (err == BAR_MSG_ERR_MODULE_NOEXIST) {
+		hdr->pi_hdr.err_code = ERR_CODE_EVENT_UNREGIST;
+	} else if ((err != MSGQ_RET_OK) || (reps_len > MAX_PACKET_LEN)) {
+		LOG_ERR("get reps failed, reps_len:%d\n", reps_len);
+		hdr->pi_hdr.err_code = ERR_CODE_EVENT_FAIL;
+	}
+
+	zxdh_swap_dst_and_src(&hdr->pi_hdr.vfid_dst, &hdr->pi_hdr.vfid_src);
+	zxdh_swap_dst_and_src(&hdr->pi_hdr.qid_dst, &hdr->pi_hdr.qid_src);
+
+	return page_send_cmd(msgq_dev->sq_priv, reps_addr, reps_len + hdr_len,
+						 msgq_dev->print_flag);
 }
 
-static void msgq_receive_buf(struct zxdh_en_device *en_dev, struct receive_queue *rq,
-                 void *buf, uint32_t len, void **ctx, struct virtnet_rq_stats *stats)
+static void msgq_receive_buf(struct zxdh_en_device *en_dev,
+							 struct receive_queue *rq, void *buf, uint32_t len,
+							 void **ctx, struct virtnet_rq_stats *stats)
 {
-    struct net_device *netdev = en_dev->netdev;
-    struct priv_queues_net_hdr *hdr = (struct priv_queues_net_hdr *)buf;
-    uint16_t num_buf = vqm16_to_cpu(netdev, hdr->num_buffers);
-    struct msgq_dev *msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
-    int32_t err = MSGQ_RET_OK;
-    uint8_t *tmp_addr = NULL;
-    uint32_t tmp_addr_len = len;
-    bool free_tmp_addr = false;
-
-    if (msgq_dev->print_flag != 0)
-    {
-        LOG_DEBUG("receive pkt start, num_buf: %d\n", num_buf);
-        msgq_print_data((uint8_t *)buf, len, msgq_dev->print_flag);
-    }
-
-    stats->xdp_drops++;
-    err = zxdh_pi_header_check(&hdr->pi_hdr);
-    ZXDH_CHECK_RET_GOTO_ERR(err, free_pages, "invalid pi_header\n");
-
-    if (hdr->pi_hdr.msg_type == ACK_MSG)
-    {
-        err = zxdh_response_msg_handle(msgq_dev, stats, num_buf, buf, len);
-        goto free_addr;
-    }
-    else if (num_buf == 1)
-    {
-        err = zxdh_callback_msg_handle(en_dev, (uint8_t *)buf, len);
-    }
-    else
-    {
-        tmp_addr = kzalloc(MSGQ_MAX_ADDR_LEN, GFP_ATOMIC);
-        ZXDH_CHECK_PTR_GOTO_ERR(tmp_addr, free_pages);
-        memcpy(tmp_addr, buf, tmp_addr_len);
-        free_tmp_addr = true;
-        while (--num_buf != 0)
-        {
-            rx_free_pages(msgq_dev, buf, len);
-            buf = virtqueue_get_buf_ctx_packed(rq->vq, &len, ctx);
-            if (unlikely(buf == NULL))
-            {
-                LOG_ERR("msgq rx error: %dth buffers missing\n", num_buf);
-                stats->drops++;
-                goto free_addr;
-            }
-
-            memcpy(tmp_addr + tmp_addr_len, buf, len);
-            tmp_addr_len += len;
-        }
-        err = zxdh_callback_msg_handle(en_dev, tmp_addr, tmp_addr_len);
-    }
-    stats->xdp_drops--;
+	struct net_device *netdev = en_dev->netdev;
+	struct priv_queues_net_hdr *hdr = (struct priv_queues_net_hdr *)buf;
+	uint16_t num_buf = vqm16_to_cpu(netdev, hdr->num_buffers);
+	struct msgq_dev *msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
+	int32_t err = MSGQ_RET_OK;
+	uint8_t *tmp_addr = NULL;
+	uint32_t tmp_addr_len = len;
+	bool free_tmp_addr = false;
+
+	if (msgq_dev->print_flag != 0) {
+		LOG_DEBUG("receive pkt start, num_buf: %d\n", num_buf);
+		msgq_print_data((uint8_t *)buf, len, msgq_dev->print_flag);
+	}
+
+	stats->xdp_drops++;
+	err = zxdh_pi_header_check(&hdr->pi_hdr);
+	ZXDH_CHECK_RET_GOTO_ERR(err, free_pages, "invalid pi_header\n");
+
+	if (hdr->pi_hdr.msg_type == ACK_MSG) {
+		err = zxdh_response_msg_handle(msgq_dev, stats, num_buf, buf, len);
+		goto free_addr;
+	} else if (num_buf == 1) {
+		err = zxdh_callback_msg_handle(en_dev, (uint8_t *)buf, len);
+	} else {
+		tmp_addr = kzalloc(MSGQ_MAX_ADDR_LEN, GFP_ATOMIC);
+		ZXDH_CHECK_PTR_GOTO_ERR(tmp_addr, free_pages);
+		memcpy(tmp_addr, buf, tmp_addr_len);
+		free_tmp_addr = true;
+		while (--num_buf != 0) {
+			rx_free_pages(msgq_dev, buf, len);
+			buf = virtqueue_get_buf_ctx_packed(rq->vq, &len, ctx);
+			if (unlikely(buf == NULL)) {
+				LOG_ERR("msgq rx error: %dth buffers missing\n", num_buf);
+				stats->drops++;
+				goto free_addr;
+			}
+
+			memcpy(tmp_addr + tmp_addr_len, buf, len);
+			tmp_addr_len += len;
+		}
+		err = zxdh_callback_msg_handle(en_dev, tmp_addr, tmp_addr_len);
+	}
+	stats->xdp_drops--;
 
 free_pages:
-    put_page(virt_to_head_page(buf));
+	put_page(virt_to_head_page(buf));
 free_addr:
-    if (free_tmp_addr)
-    {
-        ZXDH_FREE_PTR(tmp_addr);
-    }
-    stats->bytes += tmp_addr_len;
-    return;
+	if (free_tmp_addr) {
+		ZXDH_FREE_PTR(tmp_addr);
+	}
+	stats->bytes += tmp_addr_len;
+	return;
 }
 
 static int32_t zxdh_msgq_receive(struct receive_queue *rq, int32_t budget)
 {
-    struct zxdh_en_device *en_dev = netdev_priv(rq->vq->vdev);
-    struct virtnet_rq_stats stats = {};
-    uint32_t len = 0;
-    void *buf = NULL;
-    int32_t i = 0;
-    void *ctx = NULL;
-    uint64_t *item = NULL;
-
-    while (stats.packets < budget && (buf = virtqueue_get_buf_ctx_packed(rq->vq, &len, &ctx)))
-    {
-        msgq_receive_buf(en_dev, rq, buf, len, &ctx, &stats);
-        stats.packets++;
-    }
-
-    if (rq->vq->num_free > min((uint32_t)budget, virtqueue_get_vring_size(rq->vq)) / 2)
-    {
-        if (!msgq_try_fill_recv(rq, GFP_ATOMIC))
-        {
-            LOG_ERR("msgq_try_fill_recv failed\n");
-        }
-    }
-
-    u64_stats_update_begin(&rq->stats.syncp);
-    for (i = 0; i < VIRTNET_RQ_STATS_LEN; i++)
-    {
-        size_t offset = virtnet_rq_stats_desc[i].offset;
-        item = (uint64_t *)((uint8_t *)&rq->stats + offset);
-        *item += *(uint64_t *)((uint8_t *)&stats + offset);
-    }
-    u64_stats_update_end(&rq->stats.syncp);
-
-    return stats.packets;
+	struct zxdh_en_device *en_dev = netdev_priv(rq->vq->vdev);
+	struct virtnet_rq_stats stats = {};
+	uint32_t len = 0;
+	void *buf = NULL;
+	int32_t i = 0;
+	void *ctx = NULL;
+	uint64_t *item = NULL;
+
+	while (stats.packets < budget &&
+		   (buf = virtqueue_get_buf_ctx_packed(rq->vq, &len, &ctx))) {
+		msgq_receive_buf(en_dev, rq, buf, len, &ctx, &stats);
+		stats.packets++;
+	}
+
+	if (rq->vq->num_free >
+		min((uint32_t)budget, virtqueue_get_vring_size(rq->vq)) / 2) {
+		if (!msgq_try_fill_recv(rq, GFP_ATOMIC)) {
+			LOG_ERR("msgq_try_fill_recv failed\n");
+		}
+	}
+
+	u64_stats_update_begin(&rq->stats.syncp);
+	for (i = 0; i < VIRTNET_RQ_STATS_LEN; i++) {
+		size_t offset = virtnet_rq_stats_desc[i].offset;
+		item = (uint64_t *)((uint8_t *)&rq->stats + offset);
+		*item += *(uint64_t *)((uint8_t *)&stats + offset);
+	}
+	u64_stats_update_end(&rq->stats.syncp);
+
+	return stats.packets;
 }
 
 static void free_old_xmit_bufs(struct net_device *netdev, struct send_queue *sq)
 {
-    uint32_t len = 0;
-    uint32_t packets = 0;
-    uint32_t bytes = 0;
-    void *buf = NULL;
-
-    while ((buf = virtqueue_get_buf(sq->vq, &len)) != NULL)
-    {
-        bytes += len;
-        packets++;
-        ZXDH_FREE_PTR(buf);
-    }
-
-    if (!packets)
-    {
-        return;
-    }
-
-    u64_stats_update_begin(&sq->stats.syncp);
-    sq->stats.bytes += bytes;
-    sq->stats.packets += packets;
-    u64_stats_update_end(&sq->stats.syncp);
+	uint32_t len = 0;
+	uint32_t packets = 0;
+	uint32_t bytes = 0;
+	void *buf = NULL;
+
+	while ((buf = virtqueue_get_buf(sq->vq, &len)) != NULL) {
+		bytes += len;
+		packets++;
+		ZXDH_FREE_PTR(buf);
+	}
+
+	if (!packets) {
+		return;
+	}
+
+	u64_stats_update_begin(&sq->stats.syncp);
+	sq->stats.bytes += bytes;
+	sq->stats.packets += packets;
+	u64_stats_update_end(&sq->stats.syncp);
 }
 
 static void msgq_poll_cleantx(struct receive_queue *rq)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(rq->vq->vdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct msgq_dev *msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
-    struct send_queue *sq = msgq_dev->sq_priv;
-
-    if (!sq->napi.weight)
-    {
-        return;
-    }
-
-    if (spin_trylock(&msgq_dev->tx_lock))
-    {
-        free_old_xmit_bufs(en_dev->netdev, sq);
-        spin_unlock(&msgq_dev->tx_lock);
-    }
+	struct zxdh_en_priv *en_priv = netdev_priv(rq->vq->vdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct msgq_dev *msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
+	struct send_queue *sq = msgq_dev->sq_priv;
+
+	if (!sq->napi.weight) {
+		return;
+	}
+
+	if (spin_trylock(&msgq_dev->tx_lock)) {
+		free_old_xmit_bufs(en_dev->netdev, sq);
+		spin_unlock(&msgq_dev->tx_lock);
+	}
 }
 
 int zxdh_msgq_poll(struct napi_struct *napi, int budget)
 {
-    struct receive_queue *rq = container_of(napi, struct receive_queue, napi);
-    struct zxdh_en_device *en_dev = netdev_priv(rq->vq->vdev);
-    struct msgq_dev *msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
-    uint32_t received = 0;
-
-    if (msgq_dev->msgq_enable)
-    {
-        msgq_poll_cleantx(rq);
-        received = zxdh_msgq_receive(rq, budget);
-    }
-
-    if (received < budget)
-    {
-        virtqueue_napi_complete(napi, rq->vq, received);
-    }
-
-    return received;
+	struct receive_queue *rq = container_of(napi, struct receive_queue, napi);
+	struct zxdh_en_device *en_dev = netdev_priv(rq->vq->vdev);
+	struct msgq_dev *msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
+	uint32_t received = 0;
+
+	if (msgq_dev->msgq_enable) {
+		msgq_poll_cleantx(rq);
+		received = zxdh_msgq_receive(rq, budget);
+	}
+
+	if (received < budget) {
+		virtqueue_napi_complete(napi, rq->vq, received);
+	}
+
+	return received;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/priv_queue.h b/src/net/drivers/net/ethernet/dinghai/en_aux/priv_queue.h
index 3ad57da3ae4cd953303a1a4c7aa12e23fa4e9797..e7d21748b323af69fe749d3cedf0067a6b7dfe37 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/priv_queue.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/priv_queue.h
@@ -12,210 +12,202 @@ extern "C" {
 #include <linux/scatterlist.h>
 #include "queue.h"
 #include "../en_aux.h"
-#include "../../dinghai/en_np/table/include/dpp_tbl_api.h"
 
 #define MSGQ_TEST 1
 
-#define MSGQ_RET_OK                          0
-#define MSGQ_RET_ERR                        (-1)
-#define MSGQ_RET_ERR_NULL_PTR               (-2)
-#define MSGQ_RET_ERR_INVALID_PARA           (-3)
-#define MSGQ_RET_ERR_CHANNEL_NOT_READY      (-5)
-#define MSGQ_RET_ERR_CHAN_BUSY              (-6)
-#define MSGQ_RET_ERR_VQ_BROKEN              (-7)
-#define MSGQ_RET_ERR_CALLBACK_OUT_OF_TIME   (-8)
-#define MSGQ_RET_ERR_CALLBACK_FAIL          (-9)
-#define MSGQ_RET_ERR_REPS_LEN_NOT_ENOUGH    (-10)
-#define MSGQ_RET_ERR_RX_INVALID_NUM_BUF     (-11)
-
-struct reps_info
-{
-    uint32_t len;
-    uint8_t *addr;
+#define MSGQ_RET_OK 0
+#define MSGQ_RET_ERR (-1)
+#define MSGQ_RET_ERR_NULL_PTR (-2)
+#define MSGQ_RET_ERR_INVALID_PARA (-3)
+#define MSGQ_RET_ERR_CHANNEL_NOT_READY (-5)
+#define MSGQ_RET_ERR_CHAN_BUSY (-6)
+#define MSGQ_RET_ERR_VQ_BROKEN (-7)
+#define MSGQ_RET_ERR_CALLBACK_OUT_OF_TIME (-8)
+#define MSGQ_RET_ERR_CALLBACK_FAIL (-9)
+#define MSGQ_RET_ERR_REPS_LEN_NOT_ENOUGH (-10)
+#define MSGQ_RET_ERR_RX_INVALID_NUM_BUF (-11)
+
+struct reps_info {
+	uint32_t len;
+	uint8_t *addr;
 };
 
-struct msgq_pkt_info
-{
-    uint32_t timeout_us;
-    uint16_t event_id;
-    bool is_async;
-    bool no_reps;
-    uint8_t msg_priority;
-    uint8_t rsv;
-    uint32_t len;
-    uint8_t *addr;
+struct msgq_pkt_info {
+	uint32_t timeout_us;
+	uint16_t event_id;
+	bool is_async;
+	bool no_reps;
+	uint8_t msg_priority;
+	uint8_t rsv;
+	uint32_t len;
+	uint8_t *addr;
 } __attribute__((packed));
 
 /* msg_chan_pkt Definitions */
-#define MAX_PACKET_LEN           (MSGQ_MAX_ADDR_LEN - PRIV_HEADER_LEN)
-#define MSGQ_MAX_ADDR_LEN         14000
-#define NO_REPS_SEQUENCE_NUM      0x8000
-
-#define TIMER_DELAY_US            100
-#define MSGQ_MAX_MSG_BUFF_NUM     1024
-#define BUFF_LEN                  4096
-
-#define PRIV_HEADER_LEN           sizeof(struct priv_queues_net_hdr)
-#define DEFAULT_PI_TYPE           0x00 /*NP*/
-#define CONTROL_MSG_TYPE          0x1f
-#define NEED_REPS_MSG             0x00
-#define ACK_MSG                   0x01
-#define NO_REPS_MSG               0x02
-
-#define RISCV_COMMON_VFID   (1192)
-#define RISCV_COMMON_QID    (4092)
-
-enum msgq_err_code
-{
-    ERR_CODE_INVALID_EVENTID = 1,
-    ERR_CODE_EVENT_UNREGIST,
-    ERR_CODE_INVALID_ACK,
-    ERR_CODE_EVENT_FAIL,
-    ERR_CODE_INVALID_REPS_LEN,
-    ERR_CODE_PEER_BROKEN,
+#define MAX_PACKET_LEN (MSGQ_MAX_ADDR_LEN - PRIV_HEADER_LEN)
+#define MSGQ_MAX_ADDR_LEN 14000
+#define NO_REPS_SEQUENCE_NUM 0x8000
+
+#define TIMER_DELAY_US 100
+#define MSGQ_MAX_MSG_BUFF_NUM 1024
+#define BUFF_LEN 4096
+
+#define PRIV_HEADER_LEN sizeof(struct priv_queues_net_hdr)
+#define DEFAULT_PI_TYPE 0x00 /*NP*/
+#define CONTROL_MSG_TYPE 0x1f
+#define NEED_REPS_MSG 0x00
+#define ACK_MSG 0x01
+#define NO_REPS_MSG 0x02
+
+#define RISCV_COMMON_VFID (1192)
+#define RISCV_COMMON_QID (4092)
+
+#define VF_ACTIVE(VPORT) ((VPORT & 0x0800) >> 11)
+#define EPID(VPORT) ((VPORT & 0x7000) >> 12)
+#define FUNC_NUM(VPORT) ((VPORT & 0x0700) >> 8)
+#define VFUNC_NUM(VPORT) ((VPORT & 0x00FF))
+
+#define PF_VQM_VFID_OFFSET (1152)
+#define IS_PF(VPORT) (!VF_ACTIVE(VPORT))
+#define VQM_VFID(VPORT)                                                        \
+	(IS_PF(VPORT) ? (PF_VQM_VFID_OFFSET + EPID(VPORT) * 8 + FUNC_NUM(VPORT)) : \
+					  (EPID(VPORT) * 256 + VFUNC_NUM(VPORT)))
+#define OWNER_PF_VQM_VFID(VPORT) \
+	(PF_VQM_VFID_OFFSET + EPID(VPORT) * 8 + FUNC_NUM(VPORT))
+
+enum msgq_err_code {
+	ERR_CODE_INVALID_EVENTID = 1,
+	ERR_CODE_EVENT_UNREGIST,
+	ERR_CODE_INVALID_ACK,
+	ERR_CODE_EVENT_FAIL,
+	ERR_CODE_INVALID_REPS_LEN,
+	ERR_CODE_PEER_BROKEN,
 };
 
-struct pi_header
-{
-    uint8_t pi_type;
-    uint8_t pkt_type;
-    uint16_t event_id;
-    uint16_t vfid_dst;
-    uint16_t qid_dst;
-    uint16_t vfid_src;
-    uint16_t qid_src;
-    uint16_t sequence_num;
-    uint8_t msg_priority;
-    uint8_t msg_type;
-    uint8_t err_code;
-    uint8_t rsv[3];
+struct pi_header {
+	uint8_t pi_type;
+	uint8_t pkt_type;
+	uint16_t event_id;
+	uint16_t vfid_dst;
+	uint16_t qid_dst;
+	uint16_t vfid_src;
+	uint16_t qid_src;
+	uint16_t sequence_num;
+	uint8_t msg_priority;
+	uint8_t msg_type;
+	uint8_t err_code;
+	uint8_t rsv[3];
 };
 
-struct msgq_pi_info
-{
-    uint16_t event_id;
-    uint16_t vfid_dst;
-    uint16_t qid_dst;
-    uint16_t vfid_src;
-    uint16_t qid_src;
-    uint16_t sequence_num;
+struct msgq_pi_info {
+	uint16_t event_id;
+	uint16_t vfid_dst;
+	uint16_t qid_dst;
+	uint16_t vfid_src;
+	uint16_t qid_src;
+	uint16_t sequence_num;
 } __attribute__((packed));
 
-struct priv_queues_net_hdr
-{
-    uint8_t tx_port;
-    uint8_t pd_len;
-    uint8_t num_buffers;
-    uint8_t rsv;
-    struct pi_header pi_hdr;
+struct priv_queues_net_hdr {
+	uint8_t tx_port;
+	uint8_t pd_len;
+	uint8_t num_buffers;
+	uint8_t rsv;
+	struct pi_header pi_hdr;
 };
 
-struct msg_buff
-{
-    bool using;
-    bool valid;
-    bool need_free;
-    uint32_t timeout_cnt;
-    uint8_t **data;
-    uint32_t *data_len;
+struct msg_buff {
+	bool using;
+	bool valid;
+	bool need_free;
+	uint32_t timeout_cnt;
+	uint8_t **data;
+	uint32_t *data_len;
 } __attribute__((packed));
 
-#define MSGQ_PRINT_HDR   1
-#define MSGQ_PRINT_128B  2
-#define MSGQ_PRINT_ALL   3
-#define MSGQ_PRINT_STA   4
-
-struct msgq_dev
-{
-    bool msgq_enable;
-    bool timer_in_use;
-    bool loopback;
-    uint8_t print_flag;
-    uint16_t sequence_num;
-    uint16_t free_cnt;
-    uint16_t msgq_vfid;
-    uint16_t msgq_rqid;
-    struct send_queue *sq_priv;
-    struct receive_queue *rq_priv;
-    struct mutex mlock;
-    struct spinlock sn_lock;
-    struct spinlock tx_lock;
-    struct msg_buff msg_buff_ring[MSGQ_MAX_MSG_BUFF_NUM];
-    struct timer_list poll_timer;
+#define MSGQ_PRINT_HDR 1
+#define MSGQ_PRINT_128B 2
+#define MSGQ_PRINT_ALL 3
+
+struct msgq_dev {
+	bool msgq_enable;
+	bool timer_in_use;
+	bool loopback;
+	uint8_t print_flag;
+	uint16_t sequence_num;
+	uint16_t free_cnt;
+	uint16_t msgq_vfid;
+	uint16_t msgq_rqid;
+	struct send_queue *sq_priv;
+	struct receive_queue *rq_priv;
+	struct mutex mlock;
+	struct spinlock sn_lock;
+	struct spinlock tx_lock;
+	struct msg_buff msg_buff_ring[MSGQ_MAX_MSG_BUFF_NUM];
+	struct timer_list poll_timer;
 } __attribute__((packed));
 
-#define CHECK_CHANNEL_USABLE(msgq, ret, err)     \
-do                                               \
-{                                                \
-    if (!(msgq)->msgq_enable)                    \
-    {                                            \
-        LOG_ERR("msgq unable\n");                \
-        ret = MSGQ_RET_ERR_CHANNEL_NOT_READY;    \
-        goto err;                                \
-    }                                            \
-} while (0)
-
-#define ZXDH_CHECK_RET_RETURN(ret, fmt, arg...)     \
-do                                                  \
-{                                                   \
-    if ((ret) != MSGQ_RET_OK)                       \
-    {                                               \
-        LOG_ERR(fmt, ##arg);                        \
-        return (ret);                               \
-    }                                               \
-} while (0)
-
-#define ZXDH_CHECK_RET_GOTO_ERR(ret, err, fmt, arg...)     \
-do                                                         \
-{                                                          \
-    if ((ret) != MSGQ_RET_OK)                              \
-    {                                                      \
-        LOG_ERR(fmt, ##arg);                               \
-        goto err;                                          \
-    }                                                      \
-} while (0)
-
-#define ZXDH_CHECK_PTR_RETURN(ptr)    \
-do                                    \
-{                                     \
-    if (unlikely((ptr) == NULL))      \
-    {                                 \
-        LOG_ERR("null pointer\n");    \
-        return MSGQ_RET_ERR_NULL_PTR; \
-    }                                 \
-} while (0)
-
-#define ZXDH_CHECK_PTR_GOTO_ERR(ptr, err)       \
-do                                              \
-{                                               \
-    if (unlikely((ptr) == NULL))                \
-    {                                           \
-        LOG_ERR("null pointer\n");              \
-        goto err;                               \
-    }                                           \
-} while (0)
-
-#define ZXDH_FREE_PTR(ptr)      \
-do                              \
-{                               \
-    if ((ptr) != NULL)          \
-    {                           \
-        kfree(ptr);             \
-        (ptr) = NULL;           \
-    }                           \
-} while (0)
-
-#define SEQUENCE_NUM_ADD(id)                \
-do                                          \
-{                                           \
-    (id)++;                                 \
-    (id) %= MSGQ_MAX_MSG_BUFF_NUM;               \
-} while (0)
+#define CHECK_CHANNEL_USABLE(msgq, ret, err)      \
+	do {                                          \
+		if (!(msgq)->msgq_enable) {               \
+			LOG_ERR("msgq unable\n");             \
+			ret = MSGQ_RET_ERR_CHANNEL_NOT_READY; \
+			goto err;                             \
+		}                                         \
+	} while (0)
+
+#define ZXDH_CHECK_RET_RETURN(ret, fmt, arg...) \
+	do {                                        \
+		if ((ret) != MSGQ_RET_OK) {             \
+			LOG_ERR(fmt, ##arg);                \
+			return ret;                         \
+		}                                       \
+	} while (0)
+
+#define ZXDH_CHECK_RET_GOTO_ERR(ret, err, fmt, arg...) \
+	do {                                               \
+		if ((ret) != MSGQ_RET_OK) {                    \
+			LOG_ERR(fmt, ##arg);                       \
+			goto err;                                  \
+		}                                              \
+	} while (0)
+
+#define ZXDH_CHECK_PTR_RETURN(ptr)        \
+	do {                                  \
+		if (unlikely((ptr) == NULL)) {    \
+			LOG_ERR("null pointer\n");    \
+			return MSGQ_RET_ERR_NULL_PTR; \
+		}                                 \
+	} while (0)
+
+#define ZXDH_CHECK_PTR_GOTO_ERR(ptr, err) \
+	do {                                  \
+		if (unlikely((ptr) == NULL)) {    \
+			LOG_ERR("null pointer\n");    \
+			goto err;                     \
+		}                                 \
+	} while (0)
+
+#define ZXDH_FREE_PTR(ptr)   \
+	do {                     \
+		if ((ptr) != NULL) { \
+			kfree(ptr);      \
+			(ptr) = NULL;    \
+		}                    \
+	} while (0)
+
+#define SEQUENCE_NUM_ADD(id)           \
+	do {                               \
+		(id)++;                        \
+		(id) %= MSGQ_MAX_MSG_BUFF_NUM; \
+	} while (0)
 
 int32_t zxdh_msgq_init(struct zxdh_en_device *en_dev);
 void zxdh_msgq_exit(struct zxdh_en_device *en_dev);
 int32_t print_data(uint8_t *data, uint32_t len);
-int32_t zxdh_msgq_send_cmd(struct msgq_dev *msgq_dev, struct msgq_pkt_info *pkt_info, struct reps_info *reps);
+int32_t zxdh_msgq_send_cmd(struct msgq_dev *msgq_dev,
+						   struct msgq_pkt_info *pkt_info,
+						   struct reps_info *reps);
 int zxdh_msgq_poll(struct napi_struct *napi, int budget);
 
 #ifdef __cplusplus
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/queue.c b/src/net/drivers/net/ethernet/dinghai/en_aux/queue.c
index 1493e6de85d5306d08e7fd50b3c34c2c7b9fcc7f..cfced6924ace79125b1e962079bdf78fbb3b5e9c 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/queue.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/queue.c
@@ -1,2913 +1,2714 @@
-#include <linux/dinghai/kcompat.h>
-#include <linux/netdevice.h>
-#include <linux/scatterlist.h>
-#include <linux/interrupt.h>
-#include <linux/device.h>
-#include <linux/pci.h>
-#include <xen/xen.h>
-#include "../en_aux.h"
-#include "queue.h"
-#ifdef TIME_STAMP_1588
-#include "en_1588_pkt_proc.h"
-#endif
-#ifdef ZXDH_MSGQ
-#include "priv_queue.h"
-#endif
-
-static uint32_t features_table[] =
-{
-    ZXDH_NET_F_MRG_RXBUF, ZXDH_NET_F_STATUS, ZXDH_NET_F_CTRL_VQ, ZXDH_NET_F_MQ, \
-    ZXDH_RING_F_INDIRECT_DESC, ZXDH_RING_F_EVENT_IDX, ZXDH_F_VERSION_1, ZXDH_F_RING_PACKED
-};
-
-void zxdh_print_vring_info(struct virtqueue *vq, uint32_t desc_index, uint32_t desc_num)
-{
-    struct vring_virtqueue *vvq = to_vvq(vq);
-    struct vring_packed_desc *desc = NULL;
-    uint32_t i = 0;
-
-    LOG_INFO("phy_index         : %d\n", vq->phy_index);
-    LOG_INFO("num free          : %d\n", vq->num_free);
-    LOG_INFO("vring address     : 0x%llx\n", (uint64_t)&vvq->packed.vring);
-    LOG_INFO("vring size        : %d\n", vvq->packed.vring.num);
-    LOG_INFO("last_used_idx     : %d\n", vvq->last_used_idx);
-    LOG_INFO("avail_wrap_counter: %d\n", vvq->packed.avail_wrap_counter);
-    LOG_INFO("used_wrap_counter : %d\n", vvq->packed.used_wrap_counter);
-    LOG_INFO("next_avail_idx    : %d\n", vvq->packed.next_avail_idx);
-    LOG_INFO("free head         : %d\n", vvq->free_head);
-    LOG_INFO("driver->flags     : 0x%x\n", vvq->packed.vring.driver->flags);
-    LOG_INFO("driver->off_wrap  : %d\n", vvq->packed.vring.driver->off_wrap);
-    LOG_INFO("device->flags     : 0x%x\n", vvq->packed.vring.device->flags);
-    LOG_INFO("device->off_wrap  : %d\n", vvq->packed.vring.device->off_wrap);
-    LOG_INFO("DESC[x]:\tDESC_ADDR\t[BUFFER_ADDR]\t\t[LEN]\t\t[ID]\t[FLAG]\n");
-
-    desc = vvq->packed.vring.desc;
-    for (i = desc_index; i < desc_num; i++)
-    {
-        LOG_INFO("DESC[%d] 0x%llx:\t0x%016llx\t0x%08x\t%8d\t0x%x\n", \
-                 i, (uint64_t)desc, desc->addr, desc->len, desc->id, desc->flags);
-        desc++;
-    }
-
-    return;
-}
-
-/* enable irq handlers */
-void zxdh_vp_enable_cbs(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t i = 0;
-
-    for (i = 0; i< en_dev->channels_num; i++)
-    {
-        en_dev->ops->switch_vqs_channel(en_dev->parent, i, 1);
-    }
-}
-
-/* disable irq handlers */
-void zxdh_vp_disable_cbs(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t i = 0;
-
-    for (i = 0; i< en_dev->channels_num; i++)
-    {
-        en_dev->ops->switch_vqs_channel(en_dev->parent, i, 0);
-    }
-}
-
-void zxdh_vp_reset(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    /* 0 status means a reset. */
-    en_dev->ops->set_status(en_dev->parent, 0);
-
-    /* After writing 0 to device_status, the driver MUST wait for a read of
-     * device_status to return 0 before reinitializing the device.
-     * This will flush out the status write, and flush in device writes,
-     * including MSI-X interrupts, if any.
-     */
-    LOG_INFO("vp reset: get_status start\n");
-    while (en_dev->ops->get_status(en_dev->parent) != 0)
-    {
-        msleep(1);
-    }
-    LOG_INFO("vp reset: get_status stop\n");
-
-    return;
-}
-
-void zxdh_add_status(struct net_device *netdev, uint32_t status)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint8_t dev_status = 0;
-
-    might_sleep();
-
-    dev_status = en_dev->ops->get_status(en_dev->parent);
-
-    en_dev->ops->set_status(en_dev->parent, (dev_status | status));
-
-    return;
-}
-
-bool zxdh_has_status(struct net_device *netdev, uint32_t sbit)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint8_t dev_status = 0;
-
-    dev_status = en_dev->ops->get_status(en_dev->parent);
-
-    return (dev_status & sbit);
-}
-
-void zxdh_pf_features_init(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t i = 0;
-    uint64_t features = 0;
-
-    en_dev->device_feature = en_dev->ops->get_features(en_dev->parent);
-    en_dev->device_feature |= BIT(34);
-    en_dev->driver_feature = 0;
-
-    for (i = 0; i < ARRAY_SIZE(features_table); i++)
-    {
-        features = features_table[i];
-        en_dev->driver_feature |= (1ULL << features);
-    }
-    en_dev->guest_feature = en_dev->device_feature & 0xfffffff5dfffffff;
-    LOG_INFO("device_feature: 0x%llx, guest_feature: 0x%llx\n", en_dev->device_feature, en_dev->guest_feature);
-    en_dev->ops->set_features(en_dev->parent, en_dev->guest_feature);
-
-    return;
-}
-
-bool zxdh_has_feature(struct net_device *netdev, uint32_t fbit)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    return en_dev->guest_feature & BIT_ULL(fbit);
-}
-
-int32_t vq2txq(struct virtqueue *vq)
-{
-    return (vq->index - 1) / 2;
-}
-
-int32_t txq2vq(int32_t txq)
-{
-    return txq * 2 + 1;
-}
-int32_t vq2rxq(struct virtqueue *vq)
-{
-    return vq->index / 2;
-}
-
-int32_t rxq2vq(int32_t rxq)
-{
-    return rxq * 2;
-}
-
-inline void vqm_mb(bool weak_barriers)
-{
-    if (weak_barriers)
-    {
-        virt_mb();
-    }
-    else
-    {
-        mb();
-    }
-}
-
-inline void vqm_rmb(bool weak_barriers)
-{
-    if (weak_barriers)
-    {
-        virt_rmb();
-    }
-    else
-    {
-        dma_rmb();
-    }
-}
-
-inline void vqm_wmb(bool weak_barriers)
-{
-    if (weak_barriers)
-    {
-        virt_wmb();
-    }
-    else
-    {
-        dma_wmb();
-    }
-}
-
-void vring_del_virtqueue(struct virtqueue *_vq)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(_vq->vdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct vring_virtqueue *vq = to_vvq(_vq);
-
-    spin_lock(&en_dev->vqs_list_lock);
-    list_del(&_vq->list);
-    spin_unlock(&en_dev->vqs_list_lock);
-
-    if (vq->we_own_ring)
-    {
-        vring_free_queue(vq->vq.vdev,
-                 vq->packed.ring_size_in_bytes,
-                 vq->packed.vring.desc,
-                 vq->packed.ring_dma_addr);
-
-        vring_free_queue(vq->vq.vdev,
-                 vq->packed.event_size_in_bytes,
-                 vq->packed.vring.driver,
-                 vq->packed.driver_event_dma_addr);
-
-        vring_free_queue(vq->vq.vdev,
-                 vq->packed.event_size_in_bytes,
-                 vq->packed.vring.device,
-                 vq->packed.device_event_dma_addr);
-
-        kfree(vq->packed.desc_state);
-        vq->packed.desc_state = NULL;
-        kfree(vq->packed.desc_extra);
-        vq->packed.desc_extra = NULL;
-    }
-
-    kfree(vq);
-    vq = NULL;
-}
-
-void del_vq(struct zxdh_pci_vq_info *info)
-{
-    struct virtqueue *vq = info->vq;
-    struct zxdh_en_priv *en_priv = netdev_priv(vq->vdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    en_dev->ops->vq_unbind_channel(en_dev->parent, vq->phy_index);
-
-    en_dev->ops->vp_modern_unmap_vq_notify(en_dev->parent, vq->priv);
-
-    vring_del_virtqueue(vq);
-}
-
-void vp_del_vq(struct virtqueue *vq)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(vq->vdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_pci_vq_info *info = en_dev->vqs[vq->index];
-    unsigned long flags;
-
-    spin_lock_irqsave(&en_dev->lock, flags);
-    list_del(&info->node);
-    spin_unlock_irqrestore(&en_dev->lock, flags);
-
-    del_vq(info);
-    kfree(info);
-    en_dev->vqs[vq->index] = NULL;
-}
-
-void vp_detach_vqs(void *para)
-{
-    struct net_device *netdev = para;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct virtqueue *vq;
-    struct virtqueue *n;
-
-    list_for_each_entry_safe(vq, n, &en_dev->vqs_list, list)
-    {
-        vp_del_vq(vq);
-    }
-}
-
-void vp_del_vqs(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    vp_detach_vqs(netdev);
-
-    kfree(en_dev->vqs);
-    en_dev->vqs = NULL;
-}
-
-/**
- * virtqueue_get_vring_size - return the size of the virtqueue's vring
- * @_vq: the struct virtqueue containing the vring of interest.
- *
- * Returns the size of the vring.  This is mainly used for boasting to
- * userspace.  Unlike other operations, this need not be serialized.
- */
-uint32_t virtqueue_get_vring_size(struct virtqueue *_vq)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-
-    return vq->packed.vring.num;
-}
-
-dma_addr_t virtqueue_get_desc_addr(struct virtqueue *_vq)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-
-    BUG_ON(!vq->we_own_ring);
-
-    return vq->packed.ring_dma_addr;
-}
-
-dma_addr_t virtqueue_get_avail_addr(struct virtqueue *_vq)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-
-    BUG_ON(!vq->we_own_ring);
-
-    return vq->packed.driver_event_dma_addr;
-}
-
-dma_addr_t virtqueue_get_used_addr(struct virtqueue *_vq)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-
-    BUG_ON(!vq->we_own_ring);
-
-    return vq->packed.device_event_dma_addr;
-}
-
-bool vqm_has_dma_quirk(struct net_device *netdev)
-{
-    /*
-     * Note the reverse polarity of the quirk feature (compared to most
-     * other features), this is for compatibility with legacy systems.
-     */
-    return !zxdh_has_feature(netdev, ZXDH_F_ACCESS_PLATFORM);
-}
-
-bool vring_use_dma_api(struct net_device *netdev)
-{
-    if (!vqm_has_dma_quirk(netdev))
-    {
-        return true;
-    }
-
-    /* Otherwise, we are left to guess. */
-    /*
-     * In theory, it's possible to have a buggy QEMU-supposed
-     * emulated Q35 IOMMU and Xen enabled at the same time.  On
-     * such a configuration, zxdh has never worked and will
-     * not work without an even larger kludge.  Instead, enable
-     * the DMA API if we're a Xen guest, which at least allows
-     * all of the sensible Xen configurations to work correctly.
-     */
-    if (xen_domain())
-    {
-        return true;
-    }
-
-    return false;
-}
-
-void vring_free_queue(struct net_device *netdev, size_t size, void *queue, dma_addr_t dma_handle)
-{
-    if (vring_use_dma_api(netdev))
-    {
-        dma_free_coherent(netdev->dev.parent, size, queue, dma_handle);
-    }
-    else
-    {
-        free_pages_exact(queue, PAGE_ALIGN(size));
-    }
-}
-
-void *vring_alloc_queue(struct net_device *netdev, size_t size, dma_addr_t *dma_handle, gfp_t flag)
-{
-    if (vring_use_dma_api(netdev))
-    {
-        return dma_alloc_coherent(netdev->dev.parent, size, dma_handle, flag);
-    }
-    else
-    {
-        void *queue = alloc_pages_exact(PAGE_ALIGN(size), flag);
-
-        if (queue)
-        {
-            phys_addr_t phys_addr = virt_to_phys(queue);
-            *dma_handle = (dma_addr_t)phys_addr;
-
-            /*
-             * Sanity check: make sure we dind't truncate
-             * the address.  The only arches I can find that
-             * have 64-bit phys_addr_t but 32-bit dma_addr_t
-             * are certain non-highmem MIPS and x86
-             * configurations, but these configurations
-             * should never allocate physical pages above 32
-             * bits, so this is fine.  Just in case, throw a
-             * warning and abort if we end up with an
-             * unrepresentable address.
-             */
-            if (WARN_ON_ONCE(*dma_handle != phys_addr))
-            {
-                free_pages_exact(queue, PAGE_ALIGN(size));
-                return NULL;
-            }
-        }
-        return queue;
-    }
-}
-
-struct vring_desc_extra *vring_alloc_desc_extra(struct vring_virtqueue *vq, uint32_t num)
-{
-    struct vring_desc_extra *desc_extra = NULL;
-    uint32_t i = 0;
-
-    desc_extra = kmalloc_array(num, sizeof(struct vring_desc_extra), GFP_KERNEL);
-    if (unlikely(desc_extra == NULL))
-    {
-        LOG_ERR("desc_extra kmalloc_array failed\n");
-        return NULL;
-    }
-
-    memset(desc_extra, 0, num * sizeof(struct vring_desc_extra));
-
-    for (i = 0; i < num - 1; i++)
-    {
-        desc_extra[i].next = i + 1;
-    }
-
-    return desc_extra;
-}
-
-struct virtqueue *vring_create_virtqueue_packed(uint32_t index,
-                                                uint32_t num,
-                                                uint32_t vring_align,
-                                                struct net_device *netdev,
-                                                bool weak_barriers,
-                                                bool may_reduce_num,
-                                                bool context,
-                                                bool (*notify)(struct virtqueue *),
-                                                void (*callback)(struct virtqueue *),
-                                                const char *name)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct vring_virtqueue *vq = NULL;
-    struct vring_packed_desc *ring = NULL;
-    struct vring_packed_desc_event *driver = NULL;
-    struct vring_packed_desc_event *device = NULL;
-    dma_addr_t ring_dma_addr;
-    dma_addr_t driver_event_dma_addr;
-    dma_addr_t device_event_dma_addr;
-    size_t ring_size_in_bytes;
-    size_t event_size_in_bytes;
-
-    ring_size_in_bytes = num * sizeof(struct vring_packed_desc);
-
-    ring = vring_alloc_queue(netdev, ring_size_in_bytes, &ring_dma_addr, GFP_KERNEL|__GFP_NOWARN|__GFP_ZERO);
-    if (unlikely(ring == NULL))
-    {
-        LOG_ERR("ring vring_alloc_queue failed\n");
-        goto err_ring;
-    }
-
-    event_size_in_bytes = sizeof(struct vring_packed_desc_event);
-
-    driver = vring_alloc_queue(netdev, event_size_in_bytes, &driver_event_dma_addr, GFP_KERNEL|__GFP_NOWARN|__GFP_ZERO);
-    if (unlikely(driver == NULL))
-    {
-        LOG_ERR("driver vring_alloc_queue failed\n");
-        goto err_driver;
-    }
-
-    device = vring_alloc_queue(netdev, event_size_in_bytes, &device_event_dma_addr, GFP_KERNEL|__GFP_NOWARN|__GFP_ZERO);
-    if (unlikely(device == NULL))
-    {
-        LOG_ERR("device vring_alloc_queue failed\n");
-        goto err_device;
-    }
-
-    vq = kmalloc(sizeof(*vq), GFP_KERNEL);
-    if (unlikely(vq == NULL))
-    {
-        LOG_ERR("vq kmalloc failed\n");
-        goto err_vq;
-    }
-
-    vq->vq.callback = callback;
-    vq->vq.vdev = netdev;
-    vq->vq.name = name;
-    vq->vq.num_free = num;
-    vq->vq.index = index;
-    vq->we_own_ring = true;
-    vq->notify = notify;
-    vq->weak_barriers = weak_barriers;
-    vq->broken = false;
-    vq->last_used_idx = 0;
-    vq->event_triggered = false;
-    vq->num_added = 0;
-    vq->packed_ring = true;
-    vq->use_dma_api = vring_use_dma_api(netdev);
-#ifdef DEBUG
-    vq->in_use = false;
-    vq->last_add_time_valid = false;
-#endif
-
-    vq->indirect = zxdh_has_feature(netdev, ZXDH_RING_F_INDIRECT_DESC) && !context;
-    vq->event = zxdh_has_feature(netdev, ZXDH_RING_F_EVENT_IDX);
-
-    if (zxdh_has_feature(netdev, ZXDH_F_ORDER_PLATFORM))
-    {
-        vq->weak_barriers = false;
-    }
-
-    vq->packed.ring_dma_addr = ring_dma_addr;
-    vq->packed.driver_event_dma_addr = driver_event_dma_addr;
-    vq->packed.device_event_dma_addr = device_event_dma_addr;
-
-    vq->packed.ring_size_in_bytes = ring_size_in_bytes;
-    vq->packed.event_size_in_bytes = event_size_in_bytes;
-
-    vq->packed.vring.num = num;
-    vq->packed.vring.desc = ring;
-    vq->packed.vring.driver = driver;
-    vq->packed.vring.device = device;
-
-    vq->packed.next_avail_idx = 0;
-    vq->packed.avail_wrap_counter = 1;
-    vq->packed.used_wrap_counter = 1;
-    vq->packed.event_flags_shadow = 0;
-    vq->packed.avail_used_flags = 1 << VRING_PACKED_DESC_F_AVAIL;
-
-    vq->packed.desc_state = kmalloc_array(num, sizeof(struct vring_desc_state_packed), GFP_KERNEL);
-    if (unlikely(vq->packed.desc_state == NULL))
-    {
-        LOG_ERR("vq->packed.desc_state kmalloc_array failed\n");
-        goto err_desc_state;
-    }
-
-    memset(vq->packed.desc_state, 0, num * sizeof(struct vring_desc_state_packed));
-
-    /* Put everything in free lists. */
-    vq->free_head = 0;
-
-    vq->packed.desc_extra = vring_alloc_desc_extra(vq, num);
-    if (unlikely(vq->packed.desc_extra == NULL))
-    {
-        LOG_ERR("vq->packed.desc_extra vring_alloc_desc_extra failed\n");
-        goto err_desc_extra;
-    }
-
-    /* No callback? Tell other side not to bother us. */
-    if (!callback)
-    {
-        vq->packed.event_flags_shadow = VRING_PACKED_EVENT_FLAG_DISABLE;
-        vq->packed.vring.driver->flags = cpu_to_le16(vq->packed.event_flags_shadow);
-    }
-
-    spin_lock(&en_dev->vqs_list_lock);
-    list_add_tail(&vq->vq.list, &en_dev->vqs_list);
-    spin_unlock(&en_dev->vqs_list_lock);
-
-    return &vq->vq;
-
-err_desc_extra:
-    kfree(vq->packed.desc_state);
-    vq->packed.desc_state = NULL;
-err_desc_state:
-    kfree(vq);
-    vq = NULL;
-err_vq:
-    vring_free_queue(netdev, event_size_in_bytes, device, device_event_dma_addr);
-err_device:
-    vring_free_queue(netdev, event_size_in_bytes, driver, driver_event_dma_addr);
-err_driver:
-    vring_free_queue(netdev, ring_size_in_bytes, ring, ring_dma_addr);
-err_ring:
-    return NULL;
-}
-
-/* the notify function used when creating a virt queue */
-bool vp_notify(struct virtqueue *vq)
-{
-    /* we write the queue's selector into the notification register to
-     * signal the other end */
-    iowrite16(vq->phy_index, (void __iomem *)vq->priv);
-
-    return true;
-}
-
-struct virtqueue *vp_setup_vq(struct net_device *netdev, unsigned index,
-                              void (*callback)(struct virtqueue *vq),
-                              const char *name, bool ctx, uint16_t channel_num)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_pci_vq_info *info = kmalloc(sizeof *info, GFP_KERNEL);
-    struct virtqueue *vq = NULL;
-    struct virtqueue *n = NULL;
-    unsigned long flags;
-    uint16_t num = 0;
-    int32_t err = 0;
-    struct dh_vq_handler vq_handler;
-
-    /* fill out our structure that represents an active queue */
-    if (unlikely(info == NULL))
-    {
-        LOG_ERR("info kmalloc failed\n");
-        return ERR_PTR(-ENOMEM);
-    }
-
-    /*if (index >= en_dev->ops->get_queue_num(en_dev->parent))
-    {
-        LOG_ERR("index over queue nums\n");
-        return ERR_PTR(-ENOENT);
-    }*/
-
-    /* Check if queue is either not available or already active. */
-    num = en_dev->ops->get_queue_size(en_dev->parent, en_dev->phy_index[index]);
-    // if (!num || zxdh_get_queue_enable(en_dev, en_dev->phy_index[index]))
-    // {
-    //     return ERR_PTR(-ENOENT);
-    // }
-    num = ZXDH_PF_MIN_DESC_NUM;
-
-    if (num & (num - 1))
-    {
-        LOG_ERR("bad queue size %u\n", num);
-        err = -ENOMEM;
-        goto out_info;
-    }
-
-    /* create the vring */
-    vq = vring_create_virtqueue_packed(index, num, SMP_CACHE_BYTES, en_dev->netdev,
-                                       true, true, ctx, vp_notify, callback, name);
-    if (vq == NULL)
-    {
-        LOG_ERR("create the vring failed\n");
-        err = -ENOMEM;
-        goto out_info;
-    }
-
-    /* activate the queue */
-    en_dev->ops->activate_phy_vq(en_dev->parent, en_dev->phy_index[index], virtqueue_get_vring_size(vq), virtqueue_get_desc_addr(vq), virtqueue_get_avail_addr(vq), virtqueue_get_used_addr(vq));
-
-    vq->priv = (void __force *)en_dev->ops->vp_modern_map_vq_notify(en_dev->parent, en_dev->phy_index[index], NULL);
-    if (!vq->priv)
-    {
-        LOG_ERR("vp_modern_map_vq_notify failed\n");
-        err = -ENOMEM;
-        goto err_map_notify;
-    }
-
-    vq->phy_index = en_dev->phy_index[index];
-    vq->index = index;
-    info->channel_num = channel_num;
-
-    memset(&vq_handler, 0, sizeof(struct dh_vq_handler));
-    vq_handler.callback = dh_eq_vqs_vring_int;
-    if (channel_num < (en_dev->ops->get_channels_num(en_dev->parent)))
-    {
-        err = en_dev->ops->vqs_channel_bind_handler(en_dev->parent, channel_num, &vq_handler);
-        if (err < 0)
-        {
-            LOG_ERR("vqs_channel_bind_handler failed: %d\n", err);
-            goto err_vqs_channel_bind_handler;
-        }
-    }
-
-    if (channel_num >= (en_dev->ops->get_channels_num(en_dev->parent)))
-    {
-        channel_num = en_dev->ops->get_channels_num(en_dev->parent) - 1;
-    }
-    err = en_dev->ops->vq_bind_channel(en_dev->parent, channel_num, en_dev->phy_index[index]);
-    if (err < 0)
-    {
-        LOG_ERR("vq_bind_channel failed: %d\n", err);
-        goto err_vq_bind_channel;
-    }
-
-    if (callback)
-    {
-        spin_lock_irqsave(&en_dev->lock, flags);
-        err = en_dev->ops->vqs_bind_eqs(en_dev->parent, channel_num, &info->node);
-        spin_unlock_irqrestore(&en_dev->lock, flags);
-        if (err < 0)
-        {
-            LOG_ERR("vqs_bind_eqs failed: %d\n", err);
-            goto err_vqs_bind_eqs;
-        }
-    }
-    else
-    {
-        INIT_LIST_HEAD(&info->node);
-    }
-
-    info->vq = vq;
-    en_dev->vqs[index] = info;
-    return vq;
-
-err_vqs_bind_eqs:
-    list_for_each_entry_safe(vq, n, &en_dev->vqs_list, list)
-    {
-        en_dev->ops->vq_unbind_channel(en_dev->parent, vq->phy_index);
-    }
-err_vq_bind_channel:
-    if (channel_num < (en_dev->ops->get_channels_num(en_dev->parent)))
-    {
-        en_dev->ops->vqs_channel_unbind_handler(en_dev->parent, channel_num);
-    }
-err_vqs_channel_bind_handler:
-    en_dev->ops->vp_modern_unmap_vq_notify(en_dev->parent, (void __iomem __force *)vq->priv);
-err_map_notify:
-    vring_del_virtqueue(vq);
-out_info:
-    kfree(info);
-    en_dev->vqs[index] = NULL;
-    return ERR_PTR(err);
-}
-
-uint32_t get_mergeable_buf_len(struct receive_queue *rq, struct ewma_pkt_len *avg_pkt_len, uint32_t room)
-{
-    const size_t hdr_len = sizeof(struct zxdh_net_hdr);
-    uint32_t len = 0;
-
-    if (room)
-    {
-        return PAGE_SIZE - room;
-    }
-
-    len = hdr_len + clamp_t(uint32_t, ewma_pkt_len_read(avg_pkt_len), rq->min_buf_len, PAGE_SIZE - hdr_len);
-
-    return ALIGN(len, L1_CACHE_BYTES);
-}
-
-/*
- * The DMA ops on various arches are rather gnarly right now, and
- * making all of the arch DMA ops work on the vring device itself
- * is a mess.  For now, we use the parent device for DMA ops.
- */
-static inline struct device *vring_dma_dev(const struct vring_virtqueue *vq)
-{
-    return vq->vq.vdev->dev.parent; //todo
-}
-
-/* Map one sg entry. */
-dma_addr_t vring_map_one_sg(const struct vring_virtqueue *vq, struct scatterlist *sg, enum dma_data_direction direction)
-{
-    if (!vq->use_dma_api)
-    {
-        return (dma_addr_t)sg_phys(sg);
-    }
-
-    /*
-     * We can't use dma_map_sg, because we don't use scatterlists in
-     * the way it expects (we don't guarantee that the scatterlist
-     * will exist for the lifetime of the mapping).
-     */
-    return dma_map_page(vring_dma_dev(vq), sg_page(sg), sg->offset, sg->length, direction);
-}
-
-dma_addr_t vring_map_single(const struct vring_virtqueue *vq,
-                            void *cpu_addr, size_t size,
-                            enum dma_data_direction direction)
-{
-    if (!vq->use_dma_api)
-    {
-        return (dma_addr_t)virt_to_phys(cpu_addr);
-    }
-
-    return dma_map_single(vring_dma_dev(vq), cpu_addr, size, direction);
-}
-
-int32_t vring_mapping_error(const struct vring_virtqueue *vq, dma_addr_t addr)
-{
-    if (!vq->use_dma_api)
-    {
-        return 0;
-    }
-
-    return dma_mapping_error(vring_dma_dev(vq), addr);
-}
-
-/*
- * Packed ring specific functions - *_packed().
- */
-void vring_unmap_state_packed(const struct vring_virtqueue *vq, struct vring_desc_extra *state)
-{
-    uint16_t flags = 0;
-
-    if (!vq->use_dma_api)
-    {
-        return;
-    }
-
-    flags = state->flags;
-    if (flags & VRING_DESC_F_INDIRECT)
-    {
-        dma_unmap_single(vring_dma_dev(vq),
-                         state->addr, state->len,
-                         (flags & VRING_DESC_F_WRITE) ?
-                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
-    }
-    else
-    {
-        dma_unmap_page(vring_dma_dev(vq),
-                       state->addr, state->len,
-                       (flags & VRING_DESC_F_WRITE) ?
-                       DMA_FROM_DEVICE : DMA_TO_DEVICE);
-    }
-}
-
-void vring_unmap_desc_packed(const struct vring_virtqueue *vq, struct vring_packed_desc *desc)
-{
-    uint16_t flags = 0;
-
-    if (!vq->use_dma_api)
-    {
-        return;
-    }
-
-    flags = le16_to_cpu(desc->flags);
-
-    if (flags & VRING_DESC_F_INDIRECT)
-    {
-        dma_unmap_single(vring_dma_dev(vq),
-                         le64_to_cpu(desc->addr),
-                         le32_to_cpu(desc->len),
-                         (flags & VRING_DESC_F_WRITE) ?
-                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
-    }
-    else
-    {
-        dma_unmap_page(vring_dma_dev(vq),
-                       le64_to_cpu(desc->addr),
-                       le32_to_cpu(desc->len),
-                       (flags & VRING_DESC_F_WRITE) ?
-                       DMA_FROM_DEVICE : DMA_TO_DEVICE);
-    }
-}
-
-void *mergeable_len_to_ctx(uint32_t truesize, uint32_t headroom)
-{
-    return (void *)(unsigned long)((headroom << MRG_CTX_HEADER_SHIFT) | truesize);
-}
-
-inline bool virtqueue_use_indirect(struct virtqueue *_vq, unsigned int total_sg)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-
-    /*
-     * If the host supports indirect descriptor tables, and we have multiple
-     * buffers, then go indirect. FIXME: tune this threshold
-     */
-    return (vq->indirect && total_sg > 1 && vq->vq.num_free);
-}
-
-struct vring_packed_desc *alloc_indirect_packed(unsigned int total_sg, gfp_t gfp)
-{
-    struct vring_packed_desc *desc = NULL;
-
-    /*
-     * We require lowmem mappings for the descriptors because
-     * otherwise virt_to_phys will give us bogus addresses in the
-     * virtqueue.
-     */
-    gfp &= ~__GFP_HIGHMEM;
-
-    desc = kmalloc_array(total_sg, sizeof(struct vring_packed_desc), gfp);
-
-    return desc;
-}
-
-int virtqueue_add_indirect_packed(struct vring_virtqueue *vq,
-                                  struct scatterlist *sgs[],
-                                  unsigned int total_sg,
-                                  unsigned int out_sgs,
-                                  unsigned int in_sgs,
-                                  void *data,
-                                  gfp_t gfp)
-{
-    struct vring_packed_desc *desc = NULL;
-    struct scatterlist *sg = NULL;
-    uint32_t i = 0;
-    uint32_t n = 0;
-    uint32_t err_idx = 0;
-    uint16_t head = 0;
-    uint16_t id = 0;
-    dma_addr_t addr;
-
-    head = vq->packed.next_avail_idx;
-    desc = alloc_indirect_packed(total_sg, gfp);
-    if (desc == NULL)
-    {
-        LOG_ERR("desc alloc_indirect_packed failed\n");
-        return -ENOMEM;
-    }
-
-    if (unlikely(vq->vq.num_free < 1))
-    {
-        LOG_DEBUG("can't add buf len 1 - avail = 0\n");
-        kfree(desc);
-        END_USE(vq);
-        return -ENOSPC;
-    }
-
-    i = 0;
-    id = vq->free_head;
-    BUG_ON(id == vq->packed.vring.num);
-
-    for (n = 0; n < out_sgs + in_sgs; n++)
-    {
-        for (sg = sgs[n]; sg; sg = sg_next(sg))
-        {
-            addr = vring_map_one_sg(vq, sg, n < out_sgs ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
-            if (vring_mapping_error(vq, addr))
-            {
-                LOG_ERR("vring_map_one_sg error\n");
-                goto unmap_release;
-            }
-
-            desc[i].flags = cpu_to_le16(n < out_sgs ? 0 : VRING_DESC_F_WRITE);
-            desc[i].addr = cpu_to_le64(addr);
-            desc[i].len = cpu_to_le32(sg->length);
-            i++;
-        }
-    }
-
-    /* Now that the indirect table is filled in, map it. */
-    addr = vring_map_single(vq, desc, total_sg * sizeof(struct vring_packed_desc), DMA_TO_DEVICE);
-    if (vring_mapping_error(vq, addr))
-    {
-        LOG_ERR("vring_map_single error\n");
-        goto unmap_release;
-    }
-
-    vq->packed.vring.desc[head].addr = cpu_to_le64(addr);
-    vq->packed.vring.desc[head].len = cpu_to_le32(total_sg * sizeof(struct vring_packed_desc));
-    vq->packed.vring.desc[head].id = cpu_to_le16(id);
-
-    if (vq->use_dma_api)
-    {
-        vq->packed.desc_extra[id].addr = addr;
-        vq->packed.desc_extra[id].len = total_sg * sizeof(struct vring_packed_desc);
-        vq->packed.desc_extra[id].flags = VRING_DESC_F_INDIRECT | vq->packed.avail_used_flags;
-    }
-
-    /*
-     * A driver MUST NOT make the first descriptor in the list
-     * available before all subsequent descriptors comprising
-     * the list are made available.
-     */
-    vqm_wmb(vq->weak_barriers);
-    vq->packed.vring.desc[head].flags = cpu_to_le16(VRING_DESC_F_INDIRECT | vq->packed.avail_used_flags);
-
-    /* We're using some buffers from the free list. */
-    vq->vq.num_free -= 1;
-
-    /* Update free pointer */
-    n = head + 1;
-    if (n >= vq->packed.vring.num)
-    {
-        n = 0;
-        vq->packed.avail_wrap_counter ^= 1;
-        vq->packed.avail_used_flags ^=
-                1 << VRING_PACKED_DESC_F_AVAIL |
-                1 << VRING_PACKED_DESC_F_USED;
-    }
-    vq->packed.next_avail_idx = n;
-    vq->free_head = vq->packed.desc_extra[id].next;
-
-    /* Store token and indirect buffer state. */
-    vq->packed.desc_state[id].num = 1;
-    vq->packed.desc_state[id].data = data;
-    vq->packed.desc_state[id].indir_desc = desc;
-    vq->packed.desc_state[id].last = id;
-
-    vq->num_added += 1;
-
-    //LOG_DEBUG("added buffer head %i to %p\n", head, vq);
-    END_USE(vq);
-
-    return 0;
-
-unmap_release:
-    err_idx = i;
-
-    for (i = 0; i < err_idx; i++)
-    {
-        vring_unmap_desc_packed(vq, &desc[i]);
-    }
-
-    kfree(desc);
-
-    END_USE(vq);
-    return -ENOMEM;
-}
-
-int32_t virtqueue_add_packed(struct virtqueue *_vq,
-                             struct scatterlist *sgs[],
-                             uint32_t total_sg,
-                             uint32_t out_sgs,
-                             uint32_t in_sgs,
-                             void *data,
-                             void *ctx,
-                             gfp_t gfp)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-    struct vring_packed_desc *desc = NULL;
-    struct scatterlist *sg = NULL;
-    uint32_t i = 0;
-    uint32_t n = 0;
-    uint32_t c = 0;
-    uint32_t descs_used = 0;
-    uint32_t err_idx = 0;
-    __le16 head_flags = 0;
-    __le16 flags = 0;
-    uint16_t head = 0;
-    uint16_t id = 0;
-    uint16_t prev = 0;
-    uint16_t curr = 0;
-    uint16_t avail_used_flags = 0;
-    int32_t err = 0;
-
-    START_USE(vq);
-
-    BUG_ON(data == NULL);
-    BUG_ON(ctx && vq->indirect);
-
-    if (unlikely(vq->broken))
-    {
-        LOG_ERR("vq->broken\n");
-        END_USE(vq);
-        return -EIO;
-    }
-
-    LAST_ADD_TIME_UPDATE(vq);
-
-    BUG_ON(total_sg == 0);
-
-    if (virtqueue_use_indirect(_vq, total_sg))
-    {
-        err = virtqueue_add_indirect_packed(vq, sgs, total_sg, out_sgs, in_sgs, data, gfp);
-        if (err != -ENOMEM)
-        {
-            END_USE(vq);
-            return err;
-        }
-        /* fall back on direct */
-    }
-
-    head = vq->packed.next_avail_idx;
-    avail_used_flags = vq->packed.avail_used_flags;
-
-    WARN_ON_ONCE(total_sg > vq->packed.vring.num && !vq->indirect);
-
-    desc = vq->packed.vring.desc;
-    i = head;
-    descs_used = total_sg;
-
-    if (unlikely(vq->vq.num_free < descs_used))
-    {
-        LOG_ERR("can't add buf len %i - avail = %i\n", descs_used, vq->vq.num_free);
-        END_USE(vq);
-        return -ENOSPC;
-    }
-
-    id = vq->free_head;
-    BUG_ON(id == vq->packed.vring.num);
-
-    curr = id;
-    c = 0;
-    for (n = 0; n < out_sgs + in_sgs; n++)
-    {
-        for (sg = sgs[n]; sg; sg = sg_next(sg))
-        {
-            dma_addr_t addr = vring_map_one_sg(vq, sg, n < out_sgs ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
-            if (vring_mapping_error(vq, addr))
-            {
-                LOG_ERR("vring_map_one_sg error\n");
-                goto unmap_release;
-            }
-
-            flags = cpu_to_le16(vq->packed.avail_used_flags |
-                    (++c == total_sg ? 0 : VRING_DESC_F_NEXT) |
-                    (n < out_sgs ? 0 : VRING_DESC_F_WRITE));
-
-            desc[i].addr = cpu_to_le64(addr);
-            desc[i].len = cpu_to_le32(sg->length);
-            desc[i].id = cpu_to_le16(id);
-
-            if (i == head)
-            {
-                head_flags = flags;
-            }
-            else
-            {
-                desc[i].flags = flags;
-            }
-
-            if (unlikely(vq->use_dma_api))
-            {
-                vq->packed.desc_extra[curr].addr = addr;
-                vq->packed.desc_extra[curr].len = sg->length;
-                vq->packed.desc_extra[curr].flags = le16_to_cpu(flags);
-            }
-            prev = curr;
-            curr = vq->packed.desc_extra[curr].next;
-
-            if ((unlikely(++i >= vq->packed.vring.num)))
-            {
-                i = 0;
-                vq->packed.avail_used_flags ^=
-                    1 << VRING_PACKED_DESC_F_AVAIL |
-                    1 << VRING_PACKED_DESC_F_USED;
-            }
-        }
-    }
-
-    if (i < head)
-    {
-        vq->packed.avail_wrap_counter ^= 1;
-    }
-
-    /* We're using some buffers from the free list. */
-    vq->vq.num_free -= descs_used;
-
-    /* Update free pointer */
-    vq->packed.next_avail_idx = i;
-    vq->free_head = curr;
-
-    /* Store token. */
-    vq->packed.desc_state[id].num = descs_used;
-    vq->packed.desc_state[id].data = data;
-    vq->packed.desc_state[id].indir_desc = ctx;
-    vq->packed.desc_state[id].last = prev;
-
-    /*
-     * A driver MUST NOT make the first descriptor in the list
-     * available before all subsequent descriptors comprising
-     * the list are made available.
-     */
-    vqm_wmb(vq->weak_barriers);
-    vq->packed.vring.desc[head].flags = head_flags;
-    vq->num_added += descs_used;
-
-    //LOG_INFO("added buffer head %i to %p\n", head, vq);
-    END_USE(vq);
-
-    return 0;
-
-unmap_release:
-    err_idx = i;
-    i = head;
-    curr = vq->free_head;
-
-    vq->packed.avail_used_flags = avail_used_flags;
-
-    for (n = 0; n < total_sg; n++)
-    {
-        if (i == err_idx)
-        {
-            break;
-        }
-
-        vring_unmap_state_packed(vq, &vq->packed.desc_extra[curr]);
-        curr = vq->packed.desc_extra[curr].next;
-        i++;
-        if (i >= vq->packed.vring.num)
-        {
-            i = 0;
-        }
-    }
-
-    END_USE(vq);
-    return -EIO;
-}
-
-/**
- * virtqueue_add_inbuf_ctx - expose input buffers to other end
- * @vq: the struct virtqueue we're talking about.
- * @sg: scatterlist (must be well-formed and terminated!)
- * @num: the number of entries in @sg writable by other side
- * @data: the token identifying the buffer.
- * @ctx: extra context for the token
- * @gfp: how to do memory allocations (if necessary).
- *
- * Caller must ensure we don't call this with other virtqueue operations
- * at the same time (except where noted).
- *
- * Returns zero or a negative error (ie. ENOSPC, ENOMEM, EIO).
- */
-int32_t virtqueue_add_inbuf_ctx(struct virtqueue *vq,
-                                struct scatterlist *sg, uint32_t num,
-                                void *data,
-                                void *ctx,
-                                gfp_t gfp)
-{
-    return virtqueue_add_packed(vq, &sg, num, 0, 1, data, ctx, gfp);
-}
-
-bool is_used_desc_packed(struct vring_virtqueue *vq, uint16_t idx, bool used_wrap_counter)
-{
-    bool avail = false;
-    bool used = false;
-    uint16_t flags = 0;
-
-    flags = le16_to_cpu(vq->packed.vring.desc[idx].flags);
-    avail = !!(flags & (1 << VRING_PACKED_DESC_F_AVAIL));
-    used = !!(flags & (1 << VRING_PACKED_DESC_F_USED));
-
-    return avail == used && used == used_wrap_counter;
-}
-
-bool virtqueue_poll_packed(struct virtqueue *_vq, uint16_t off_wrap)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-    bool wrap_counter = false;
-    uint16_t used_idx = 0;
-
-    wrap_counter = off_wrap >> VRING_PACKED_EVENT_F_WRAP_CTR;
-    used_idx = off_wrap & ~(1 << VRING_PACKED_EVENT_F_WRAP_CTR);
-
-    return is_used_desc_packed(vq, used_idx, wrap_counter);
-}
-
-/**
- * virtqueue_poll - query pending used buffers
- * @_vq: the struct virtqueue we're talking about.
- * @last_used_idx: virtqueue state (from call to virtqueue_enable_cb_prepare).
- *
- * Returns "true" if there are pending used buffers in the queue.
- *
- * This does not need to be serialized.
- */
-bool virtqueue_poll(struct virtqueue *_vq, unsigned last_used_idx)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-
-    if (unlikely(vq->broken))
-    {
-        LOG_ERR("vq->broken\n");
-        return false;
-    }
-
-    vqm_mb(vq->weak_barriers);
-    return virtqueue_poll_packed(_vq, last_used_idx);
-}
-
-unsigned virtqueue_enable_cb_prepare_packed(struct virtqueue *_vq)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-
-    START_USE(vq);
-
-    /*
-     * We optimistically turn back on interrupts, then check if there was
-     * more to do.
-     */
-    if (vq->event)
-    {
-        vq->packed.vring.driver->off_wrap =
-            cpu_to_le16(vq->last_used_idx | (vq->packed.used_wrap_counter << VRING_PACKED_EVENT_F_WRAP_CTR));
-        /*
-         * We need to update event offset and event wrap
-         * counter first before updating event flags.
-         */
-        vqm_wmb(vq->weak_barriers);
-    }
-
-    if (vq->packed.event_flags_shadow == VRING_PACKED_EVENT_FLAG_DISABLE)
-    {
-        vq->packed.event_flags_shadow = vq->event ?
-                VRING_PACKED_EVENT_FLAG_DESC :
-                VRING_PACKED_EVENT_FLAG_ENABLE;
-        vq->packed.vring.driver->flags = cpu_to_le16(vq->packed.event_flags_shadow);
-    }
-
-    END_USE(vq);
-    return vq->last_used_idx | ((uint16_t)vq->packed.used_wrap_counter << VRING_PACKED_EVENT_F_WRAP_CTR);
-}
-
-int32_t virtqueue_enable_cb_prepare(struct virtqueue *_vq)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-
-    if (vq->event_triggered)
-    {
-        vq->event_triggered = false;
-    }
-
-    return virtqueue_enable_cb_prepare_packed(_vq);
-}
-
-bool more_used_packed(struct vring_virtqueue *vq)
-{
-    return is_used_desc_packed(vq, vq->last_used_idx, vq->packed.used_wrap_counter);
-}
-
-void detach_buf_packed(struct vring_virtqueue *vq, uint32_t id, void **ctx)
-{
-    struct vring_desc_state_packed *state = NULL;
-    struct vring_packed_desc *desc = NULL;
-    uint32_t i = 0;
-    uint32_t curr = 0;
-
-    state = &vq->packed.desc_state[id];
-
-    /* Clear data ptr. */
-    state->data = NULL;
-
-    vq->packed.desc_extra[state->last].next = vq->free_head;
-    vq->free_head = id;
-    vq->vq.num_free += state->num;
-
-    if (unlikely(vq->use_dma_api))
-    {
-        curr = id;
-        for (i = 0; i < state->num; i++)
-        {
-            vring_unmap_state_packed(vq, &vq->packed.desc_extra[curr]);
-            curr = vq->packed.desc_extra[curr].next;
-        }
-    }
-
-    if (vq->indirect)
-    {
-        uint32_t len;
-
-        /* Free the indirect table, if any, now that it's unmapped. */
-        desc = state->indir_desc;
-        if (!desc)
-        {
-            return;
-        }
-
-        if (vq->use_dma_api)
-        {
-            len = vq->packed.desc_extra[id].len;
-            for (i = 0; i < len / sizeof(struct vring_packed_desc); i++)
-            {
-                vring_unmap_desc_packed(vq, &desc[i]);
-            }
-        }
-        kfree(desc);
-        state->indir_desc = NULL;
-    }
-    else if (ctx)
-    {
-        *ctx = state->indir_desc;
-    }
-}
-
-void *virtqueue_get_buf_ctx_packed(struct virtqueue *_vq, uint32_t *len, void **ctx)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-    uint16_t last_used = 0;
-    uint16_t id = 0;
-    void *ret = NULL;
-
-    START_USE(vq);
-
-    if (unlikely(vq->broken))
-    {
-        END_USE(vq);
-        return NULL;
-    }
-
-    if (!more_used_packed(vq))
-    {
-        //LOG_ERR("no more buffers in queue\n");
-        END_USE(vq);
-        return NULL;
-    }
-
-    /* Only get used elements after they have been exposed by host. */
-    vqm_rmb(vq->weak_barriers);
-
-    last_used = vq->last_used_idx;
-    id = le16_to_cpu(vq->packed.vring.desc[last_used].id);
-    *len = le32_to_cpu(vq->packed.vring.desc[last_used].len);
-
-    if (unlikely(id >= vq->packed.vring.num))
-    {
-        zxdh_print_vring_info(_vq, 0, vq->packed.vring.num);
-        BAD_RING(vq, "id %u out of range\n", id);
-        return NULL;
-    }
-    if (unlikely(!vq->packed.desc_state[id].data))
-    {
-        zxdh_print_vring_info(_vq, 0, vq->packed.vring.num);
-        BAD_RING(vq, "id %u is not a head!\n", id);
-        return NULL;
-    }
-
-    /* detach_buf_packed clears data, so grab it now. */
-    ret = vq->packed.desc_state[id].data;
-    detach_buf_packed(vq, id, ctx);
-
-    vq->last_used_idx += vq->packed.desc_state[id].num;
-    if (unlikely(vq->last_used_idx >= vq->packed.vring.num))
-    {
-        vq->last_used_idx -= vq->packed.vring.num;
-        vq->packed.used_wrap_counter ^= 1;
-    }
-
-    /*
-     * If we expect an interrupt for the next entry, tell host
-     * by writing event index and flush out the write before
-     * the read in the next get_buf call.
-     */
-    if (vq->packed.event_flags_shadow == VRING_PACKED_EVENT_FLAG_DESC)
-        vqm_store_mb(vq->weak_barriers,
-                &vq->packed.vring.driver->off_wrap,
-                cpu_to_le16(vq->last_used_idx |
-                    (vq->packed.used_wrap_counter <<
-                     VRING_PACKED_EVENT_F_WRAP_CTR)));
-
-    LAST_ADD_TIME_INVALID(vq);
-
-    END_USE(vq);
-    return ret;
-}
-
-void *virtqueue_get_buf(struct virtqueue *_vq, uint32_t *len)
-{
-    return virtqueue_get_buf_ctx_packed(_vq, len, NULL);
-}
-
-/*
- * private is used to chain pages for big packets, put the whole
- * most recent used list in the beginning for reuse
- */
-void give_pages(struct receive_queue *rq, struct page *page)
-{
-    struct page *end = NULL;
-
-    /* Find end of list, sew whole thing into vi->rq.pages. */
-    for (end = page; end->private; end = (struct page *)end->private);
-    end->private = (unsigned long)rq->pages;
-    rq->pages = page;
-}
-
-void free_old_xmit_skbs(struct net_device *netdev, struct send_queue *sq, bool in_napi)
-{
-    uint32_t len = 0;
-    uint32_t packets = 0;
-    uint32_t bytes = 0;
-    void *ptr = NULL;
-
-    while ((ptr = virtqueue_get_buf(sq->vq, &len)) != NULL)
-    {
-        struct sk_buff *skb = ptr;
-
-        //LOG_DEBUG("sent skb %p\n", skb);
-
-        bytes += skb->len;
-        napi_consume_skb(skb, in_napi);
-        packets++;
-    }
-
-    /* Avoid overhead when no packets have been processed
-     * happens when called speculatively from start_xmit.
-     */
-    if (!packets)
-    {
-        return;
-    }
-
-    u64_stats_update_begin(&sq->stats.syncp);
-    sq->stats.bytes += bytes;
-    sq->stats.packets += packets;
-    netdev->stats.tx_bytes += bytes;
-    netdev->stats.tx_packets += packets;
-    u64_stats_update_end(&sq->stats.syncp);
-}
-
-void virtqueue_disable_cb_packed(struct virtqueue *_vq)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-
-    if (vq->packed.event_flags_shadow != VRING_PACKED_EVENT_FLAG_DISABLE)
-    {
-        vq->packed.event_flags_shadow = VRING_PACKED_EVENT_FLAG_DISABLE;
-        vq->packed.vring.driver->flags = cpu_to_le16(vq->packed.event_flags_shadow);
-    }
-}
-
-/**
- * virtqueue_disable_cb - disable callbacks
- * @_vq: the struct virtqueue we're talking about.
- *
- * Note that this is not necessarily synchronous, hence unreliable and only
- * useful as an optimization.
- *
- * Unlike other operations, this need not be serialized.
- */
-void virtqueue_disable_cb(struct virtqueue *_vq)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-
-    /* If device triggered an event already it won't trigger one again:
-     * no need to disable.
-     */
-    if (vq->event_triggered)
-    {
-        return;
-    }
-
-    virtqueue_disable_cb_packed(_vq);
-}
-
-void virtqueue_napi_schedule(struct napi_struct *napi, struct virtqueue *vq)
-{
-    if (napi_schedule_prep(napi))
-    {
-        virtqueue_disable_cb(vq);
-        __napi_schedule(napi);
-    }
-}
-
-void virtnet_napi_enable(struct virtqueue *vq, struct napi_struct *napi)
-{
-    napi_enable(napi);
-
-    /* If all buffers were filled by other side before we napi_enabled, we
-     * won't get another interrupt, so process any outstanding packets now.
-     * Call local_bh_enable after to trigger softIRQ processing.
-     */
-    local_bh_disable();
-    virtqueue_napi_schedule(napi, vq);
-    local_bh_enable();
-}
-
-void virtnet_napi_tx_enable(struct net_device *netdev, struct virtqueue *vq, struct napi_struct *napi)
-{
-    if (!napi->weight)
-    {
-        return;
-    }
-
-    virtnet_napi_enable(vq, napi);
-
-    return;
-}
-
-void virtnet_napi_tx_disable(struct napi_struct *napi)
-{
-    if (napi->weight)
-    {
-        napi_disable(napi);
-    }
-}
-
-int virtnet_poll_tx(struct napi_struct *napi, int budget)
-{
-    struct send_queue *sq = container_of(napi, struct send_queue, napi);
-    struct zxdh_en_priv *en_priv = netdev_priv(sq->vq->vdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t index = vq2txq(sq->vq);
-    struct netdev_queue *txq = NULL;
-    int32_t opaque = 0;
-    bool done = false;
-
-    txq = netdev_get_tx_queue(en_dev->netdev, index);
-    __netif_tx_lock(txq, raw_smp_processor_id());
-    virtqueue_disable_cb(sq->vq);
-    free_old_xmit_skbs(en_dev->netdev, sq, true);
-
-    if (sq->vq->num_free >= 2 + MAX_SKB_FRAGS)
-    {
-        netif_tx_wake_queue(txq);
-    }
-
-    opaque = virtqueue_enable_cb_prepare(sq->vq);
-
-    done = napi_complete_done(napi, 0);
-
-    if (!done)
-    {
-        virtqueue_disable_cb(sq->vq);
-    }
-
-    __netif_tx_unlock(txq);
-
-    if (done)
-    {
-        if (unlikely(virtqueue_poll(sq->vq, opaque)))
-        {
-            if (napi_schedule_prep(napi))
-            {
-                __netif_tx_lock(txq, raw_smp_processor_id());
-                virtqueue_disable_cb(sq->vq);
-                __netif_tx_unlock(txq);
-                __napi_schedule(napi);
-            }
-        }
-    }
-
-    return 0;
-}
-
-bool virtqueue_enable_cb_delayed_packed(struct virtqueue *_vq)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-    uint16_t used_idx = 0;
-    uint16_t wrap_counter = 0;
-    uint16_t bufs = 0;
-
-    START_USE(vq);
-
-    /*
-     * We optimistically turn back on interrupts, then check if there was
-     * more to do.
-     */
-
-    if (vq->event)
-    {
-        /* TODO: tune this threshold */
-        bufs = (vq->packed.vring.num - vq->vq.num_free) * 3 / 4;
-        wrap_counter = vq->packed.used_wrap_counter;
-
-        used_idx = vq->last_used_idx + bufs;
-        if (used_idx >= vq->packed.vring.num)
-        {
-            used_idx -= vq->packed.vring.num;
-            wrap_counter ^= 1;
-        }
-
-        vq->packed.vring.driver->off_wrap = cpu_to_le16(used_idx |
-            (wrap_counter << VRING_PACKED_EVENT_F_WRAP_CTR));
-
-        /*
-         * We need to update event offset and event wrap
-         * counter first before updating event flags.
-         */
-        vqm_wmb(vq->weak_barriers);
-    }
-
-    if (vq->packed.event_flags_shadow == VRING_PACKED_EVENT_FLAG_DISABLE)
-    {
-        vq->packed.event_flags_shadow = vq->event ?
-                VRING_PACKED_EVENT_FLAG_DESC :
-                VRING_PACKED_EVENT_FLAG_ENABLE;
-        vq->packed.vring.driver->flags = cpu_to_le16(vq->packed.event_flags_shadow);
-    }
-
-    /*
-     * We need to update event suppression structure first
-     * before re-checking for more used buffers.
-     */
-    vqm_mb(vq->weak_barriers);
-
-    if (is_used_desc_packed(vq, vq->last_used_idx, vq->packed.used_wrap_counter))
-    {
-        END_USE(vq);
-        return false;
-    }
-
-    END_USE(vq);
-    return true;
-}
-uint16_t __vqm16_to_cpu(bool little_endian, __vqm16 val)
-{
-    if (little_endian)
-    {
-        return le16_to_cpu((__force __le16)val);
-    }
-    else
-    {
-        return be16_to_cpu((__force __be16)val);
-    }
-}
-
-static inline bool zxdh_legacy_is_little_endian(void)
-{
-#ifdef __LITTLE_ENDIAN
-    return true;
-#else
-    return false;
-#endif
-}
-
-bool zxdh_is_little_endian(struct net_device *dev)
-{
-    return zxdh_has_feature(dev, ZXDH_F_VERSION_1) || zxdh_legacy_is_little_endian();
-}
-
-/* Memory accessors */
-uint16_t vqm16_to_cpu(struct net_device *netdev, __vqm16 val)
-{
-    return __vqm16_to_cpu(zxdh_is_little_endian(netdev), val);
-}
-
-uint32_t mergeable_ctx_to_headroom(void *mrg_ctx)
-{
-    return (unsigned long)mrg_ctx >> MRG_CTX_HEADER_SHIFT;
-}
-
-uint32_t mergeable_ctx_to_truesize(void *mrg_ctx)
-{
-    return (unsigned long)mrg_ctx & ((1 << MRG_CTX_HEADER_SHIFT) - 1);
-}
-
-/**
- * virtqueue_enable_cb_delayed - restart callbacks after disable_cb.
- * @_vq: the struct virtqueue we're talking about.
- *
- * This re-enables callbacks but hints to the other side to delay
- * interrupts until most of the available buffers have been processed;
- * it returns "false" if there are many pending buffers in the queue,
- * to detect a possible race between the driver checking for more work,
- * and enabling callbacks.
- *
- * Caller must ensure we don't call this with other virtqueue
- * operations at the same time (except where noted).
- */
-bool virtqueue_enable_cb_delayed(struct virtqueue *_vq)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-
-    if (vq->event_triggered)
-    {
-        vq->event_triggered = false;
-    }
-
-    return virtqueue_enable_cb_delayed_packed(_vq);
-}
-
-void virtnet_poll_cleantx(struct receive_queue *rq)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(rq->vq->vdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t index = vq2rxq(rq->vq);
-    struct send_queue *sq = &en_dev->sq[index];
-    struct netdev_queue *txq = netdev_get_tx_queue(en_dev->netdev, index);
-
-    if (!sq->napi.weight)
-    {
-        return;
-    }
-
-    if (__netif_tx_trylock(txq))
-    {
-        do
-        {
-            virtqueue_disable_cb(sq->vq);
-            free_old_xmit_skbs(en_dev->netdev, sq, true);
-        } while (unlikely(!virtqueue_enable_cb_delayed(sq->vq)));
-
-        if (sq->vq->num_free >= 2 + MAX_SKB_FRAGS)
-        {
-            netif_tx_wake_queue(txq);
-        }
-
-        __netif_tx_unlock(txq);
-    }
-}
-
-inline struct zxdh_net_hdr *skb_vnet_hdr(struct sk_buff *skb)
-{
-    return (struct zxdh_net_hdr *)skb->cb;
-}
-
-/* Called from bottom half context */
-struct sk_buff *page_to_skb(struct zxdh_en_device *en_dev,
-                            struct receive_queue *rq,
-                            struct page *page, uint32_t offset,
-                            uint32_t len, uint32_t truesize,
-                            uint32_t metasize, uint32_t headroom)
-{
-    struct sk_buff *skb = NULL;
-    struct zxdh_net_hdr *hdr = NULL;
-    uint32_t copy = 0;
-    uint32_t hdr_len = 0;
-    struct page *page_to_free = NULL;
-    int32_t tailroom = 0;
-    int32_t shinfo_size = 0;
-    char *p = NULL;
-    char *hdr_p = NULL;
-    char *buf = NULL;
-    uint32_t hdr_len_tmp = 0;
-
-    p = page_address(page) + offset;
-    hdr_p = p;
-
-    hdr_len = (((struct zxdh_net_hdr *)hdr_p)->pd_len) * HDR_2B_UNIT;
-
-    /* If headroom is not 0, there is an offset between the beginning of the
-     * data and the allocated space, otherwise the data and the allocated
-     * space are aligned.
-     *
-     * Buffers with headroom use PAGE_SIZE as alloc size, see
-     * add_recvbuf_mergeable() + get_mergeable_buf_len()
-     */
-    truesize = headroom ? PAGE_SIZE : truesize;
-    tailroom = truesize - headroom;
-    buf = p - headroom;
-
-    len -= hdr_len;
-    offset += hdr_len;
-    p += hdr_len;
-    tailroom -= hdr_len + len;
-
-    shinfo_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
-
-    /* copy small packet so we can reuse these pages */
-    if (!NET_IP_ALIGN && len > GOOD_COPY_LEN && tailroom >= shinfo_size)
-    {
-        skb = build_skb(buf, truesize);
-        if (unlikely(!skb))
-        {
-            LOG_ERR("build_skb is null\n");
-            return NULL;
-        }
-
-        skb_reserve(skb, p - buf);
-        skb_put(skb, len);
-
-        page = (struct page *)page->private;
-        if (page)
-        {
-            give_pages(rq, page);
-        }
-        goto ok;
-    }
-
-    /* copy small packet so we can reuse these pages for small data */
-    skb = napi_alloc_skb(&rq->napi, GOOD_COPY_LEN);
-    if (unlikely(!skb))
-    {
-        LOG_ERR("napi_alloc_skb is null\n");
-        return NULL;
-    }
-
-    /* Copy all frame if it fits skb->head */
-    if (len <= skb_tailroom(skb))
-    {
-        copy = len;
-    }
-    else
-    {
-        copy = ETH_HLEN + metasize;
-    }
-    skb_put_data(skb, p, copy);
-
-    len -= copy;
-    offset += copy;
-
-    if (len)
-    {
-        skb_add_rx_frag(skb, 0, page, offset, len, truesize);
-    }
-    else
-    {
-        page_to_free = page;
-    }
-
-ok:
-    hdr = skb_vnet_hdr(skb);
-    hdr_len_tmp = hdr_len > 48 ? 48 : hdr_len; //todo
-    memcpy(hdr, hdr_p, hdr_len_tmp);
-    //memcpy(hdr, hdr_p, hdr_len);
-
-    if (page_to_free)
-    {
-        put_page(page_to_free);
-    }
-
-    if (metasize)
-    {
-        __skb_pull(skb, metasize);
-        skb_metadata_set(skb, metasize);
-    }
-
-    return skb;
-}
-/**
- * virtqueue_add_outbuf - expose output buffers to other end
- * @vq: the struct virtqueue we're talking about.
- * @sg: scatterlist (must be well-formed and terminated!)
- * @num: the number of entries in @sg readable by other side
- * @data: the token identifying the buffer.
- * @gfp: how to do memory allocations (if necessary).
- *
- * Caller must ensure we don't call this with other virtqueue operations
- * at the same time (except where noted).
- *
- * Returns zero or a negative error (ie. ENOSPC, ENOMEM, EIO).
- */
-int32_t virtqueue_add_outbuf(struct virtqueue *vq, struct scatterlist *sg, uint32_t num, void *data, gfp_t gfp)
-{
-    return virtqueue_add_packed(vq, &sg, num, 1, 0, data, NULL, gfp);
-}
-
-struct sk_buff *receive_mergeable(struct net_device *netdev,
-                                  struct zxdh_en_device *en_dev,
-                                  struct receive_queue *rq,
-                                  void *buf,
-                                  void *ctx,
-                                  uint32_t len,
-                                  struct virtnet_rq_stats *stats)
-{
-    struct zxdh_net_hdr *hdr = buf;
-    uint16_t num_buf = vqm16_to_cpu(netdev, hdr->num_buffers);
-    struct page *page = virt_to_head_page(buf);
-    int32_t offset = buf - page_address(page);
-    struct sk_buff *head_skb = NULL;
-    struct sk_buff *curr_skb = NULL;
-    uint32_t truesize = mergeable_ctx_to_truesize(ctx);
-    uint32_t headroom = mergeable_ctx_to_headroom(ctx);
-    uint32_t metasize = 0;
-
-    stats->bytes += (len - (hdr->pd_len * HDR_2B_UNIT));
-    netdev->stats.rx_bytes += (len - (hdr->pd_len * HDR_2B_UNIT));
-
-    if (unlikely(len > truesize))
-    {
-        LOG_ERR("%s: rx error: len %u exceeds truesize %lu\n", netdev->name, len, (unsigned long)ctx);
-        netdev->stats.rx_length_errors++;
-        netdev->stats.rx_errors++;
-        goto err_skb;
-    }
-
-    head_skb = page_to_skb(en_dev, rq, page, offset, len, truesize, metasize, headroom);
-    curr_skb = head_skb;
-
-    if (unlikely(!curr_skb))
-    {
-        LOG_ERR("page_to_skb is null\n");
-        goto err_skb;
-    }
-    while (--num_buf)
-    {
-        int32_t num_skb_frags;
-
-        buf = virtqueue_get_buf_ctx_packed(rq->vq, &len, &ctx);
-        if (unlikely(!buf))
-        {
-            LOG_ERR("%s: rx error: %d buffers out of %d missing\n", netdev->name, num_buf, vqm16_to_cpu(netdev, hdr->num_buffers));
-            netdev->stats.rx_length_errors++;
-            netdev->stats.rx_errors++;
-            goto err_buf;
-        }
-
-        stats->bytes += len;
-        netdev->stats.rx_bytes += len;
-        page = virt_to_head_page(buf);
-
-        truesize = mergeable_ctx_to_truesize(ctx);
-        if (unlikely(len > truesize))
-        {
-            LOG_ERR("%s: rx error: len %u exceeds truesize %lu\n", netdev->name, len, (unsigned long)ctx);
-            netdev->stats.rx_length_errors++;
-            netdev->stats.rx_errors++;
-            goto err_skb;
-        }
-
-        num_skb_frags = skb_shinfo(curr_skb)->nr_frags;
-        if (unlikely(num_skb_frags == MAX_SKB_FRAGS))
-        {
-            struct sk_buff *nskb = alloc_skb(0, GFP_ATOMIC);
-
-            if (unlikely(!nskb))
-            {
-                LOG_ERR("alloc_skb is null\n");
-                goto err_skb;
-            }
-            if (curr_skb == head_skb)
-            {
-                skb_shinfo(curr_skb)->frag_list = nskb;
-            }
-            else
-            {
-                curr_skb->next = nskb;
-            }
-            curr_skb = nskb;
-            head_skb->truesize += nskb->truesize;
-            num_skb_frags = 0;
-        }
-
-        if (curr_skb != head_skb)
-        {
-            head_skb->data_len += len;
-            head_skb->len += len;
-            head_skb->truesize += truesize;
-        }
-        offset = buf - page_address(page);
-
-        if (skb_can_coalesce(curr_skb, num_skb_frags, page, offset))
-        {
-            put_page(page);
-            skb_coalesce_rx_frag(curr_skb, num_skb_frags - 1, len, truesize);
-        }
-        else
-        {
-            skb_add_rx_frag(curr_skb, num_skb_frags, page, offset, len, truesize);
-        }
-    }
-
-    ewma_pkt_len_add(&rq->mrg_avg_pkt_len, head_skb->len);
-    return head_skb;
-
-err_skb:
-    put_page(page);
-    while (num_buf-- > 1)
-    {
-        buf = virtqueue_get_buf(rq->vq, &len);
-        if (unlikely(!buf))
-        {
-            LOG_ERR("%s: rx error: %d buffers missing\n", netdev->name, num_buf);
-            netdev->stats.rx_length_errors++;
-            netdev->stats.rx_errors++;
-            break;
-        }
-        stats->bytes += len;
-        page = virt_to_head_page(buf);
-        put_page(page);
-    }
-err_buf:
-    stats->drops++;
-    netdev->stats.rx_dropped++;
-    dev_kfree_skb(head_skb);
-    return NULL;
-}
-
-static bool is_dev_configed_vlan(struct zxdh_en_device *en_dev)
-{
-    return (en_dev->vlan_dev.vlan_id != 0);
-}
-
-void receive_buf(struct zxdh_en_device *en_dev, struct receive_queue *rq,
-                 void *buf, uint32_t len, void **ctx,
-                 struct virtnet_rq_stats *stats)
-{
-    bool vlan_striped, qinq_striped;
-    struct net_device *netdev = en_dev->netdev;
-    struct sk_buff *skb = NULL;
-    struct zxdh_net_hdr_rcv *hdr_rcv = (struct zxdh_net_hdr_rcv *)buf;
-
-#ifdef TIME_STAMP_1588
-    int32_t ret = 0;
-#endif
-
-    if (unlikely(len < (hdr_rcv->pd_len * HDR_2B_UNIT) + ETH_HLEN))
-    {
-        LOG_ERR("%s: short packet %i\n", netdev->name, len);
-        netdev->stats.rx_length_errors++;
-        netdev->stats.rx_errors++;
-
-        put_page(virt_to_head_page(buf));
-        return;
-    }
-
-    skb = receive_mergeable(netdev, en_dev, rq, buf, ctx, len, stats);
-
-    if (unlikely(!skb))
-    {
-        LOG_ERR("skb receive_mergeable null\n");
-        return;
-    }
-
-    /* rx packet contain the strip label & open rxvlan offloading*/
-    vlan_striped =  hdr_rcv->pd_hdr.flags & RX_VLAN_STRIPED_MASK && !is_dev_configed_vlan(en_dev);
-    qinq_striped =  hdr_rcv->pd_hdr.flags & RX_QINQ_STRIPED_MASK;
-    if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && (vlan_striped || qinq_striped))
-    {
-        u16 vid = htons(hdr_rcv->pd_hdr.striped_ctci) & RX_TPID_VLAN_ID_MASK;
-        __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
-    }
-
-    if ((netdev->features & NETIF_F_RXCSUM) && !(hdr_rcv->pi_hdr.error_code[1] & PI_HDR_L4_CHKSUM_ERROR_CODE)
-        && !(hdr_rcv->pi_hdr.error_code[0] & PI_HDR_L3_CHKSUM_ERROR_CODE) && !(hdr_rcv->pd_hdr.flags & OUTER_IP_CHKSUM_ERROT_CODE))
-    {
-        skb->ip_summed = CHECKSUM_UNNECESSARY;
-    }
-    else
-    {
-        skb->ip_summed = CHECKSUM_NONE;
-    }
-
-#ifdef TIME_STAMP_1588
-    ret = pkt_1588_proc_rcv(skb, hdr_rcv, en_dev->clock_no, en_dev);
-    if ((ret != PTP_SUCCESS) && (ret != IS_NOT_PTP_MSG))
-    {
-        LOG_ERR("pkt_1588_proc_rcv err!!!\n");
-        return;
-    }
-#endif
-
-    skb_record_rx_queue(skb, vq2rxq(rq->vq));
-    skb->protocol = eth_type_trans(skb, netdev);
-
-    //LOG_INFO("receiving skb proto 0x%04x len %i type %i\n", ntohs(skb->protocol), skb->len, skb->pkt_type);
-
-    napi_gro_receive(&rq->napi, skb);
-    return;
-}
-
-/**
- * virtqueue_notify - second half of split virtqueue_kick call.
- * @_vq: the struct virtqueue
- *
- * This does not need to be serialized.
- *
- * Returns false if host notify failed or queue is broken, otherwise true.
- */
-bool virtqueue_notify(struct virtqueue *_vq)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-
-    if (unlikely(vq->broken))
-    {
-        LOG_ERR("vq->broken\n");
-        return false;
-    }
-
-    /* Prod other side to tell it about changes. */
-    if (!vq->notify(_vq))
-    {
-        LOG_ERR("vq->notify(_vq) failed\n");
-        vq->broken = true;
-        return false;
-    }
-
-    return true;
-}
-
-int32_t add_recvbuf_mergeable(struct zxdh_en_device *en_dev, struct receive_queue *rq, gfp_t gfp)
-{
-    struct page_frag *alloc_frag = &rq->alloc_frag;
-    uint32_t headroom = 0;
-    uint32_t tailroom = 0;
-    uint32_t room = SKB_DATA_ALIGN(headroom + tailroom);
-    char *buf = NULL;
-    void *ctx = NULL;
-    int32_t err = 0;
-    uint32_t len = 0;
-    uint32_t hole = 0;
-
-    /* Extra tailroom is needed to satisfy XDP's assumption. This
-     * means rx frags coalescing won't work, but consider we've
-     * disabled GSO for XDP, it won't be a big issue.
-     */
-    len = get_mergeable_buf_len(rq, &rq->mrg_avg_pkt_len, room);
-    if (unlikely(!skb_page_frag_refill(len + room, alloc_frag, gfp)))
-    {
-        LOG_ERR("skb_page_frag_refill failed\n");
-        return -ENOMEM;
-    }
-
-    buf = (char *)page_address(alloc_frag->page) + alloc_frag->offset;
-    buf += headroom; /* advance address leaving hole at front of pkt */
-    get_page(alloc_frag->page);
-    alloc_frag->offset += len + room;
-    hole = alloc_frag->size - alloc_frag->offset;
-    if (hole < len + room)
-    {
-        /* To avoid internal fragmentation, if there is very likely not
-         * enough space for another buffer, add the remaining space to
-         * the current buffer.
-         */
-        len += hole;
-        alloc_frag->offset += hole;
-    }
-
-    sg_init_one(rq->sg, buf, len);
-    ctx = mergeable_len_to_ctx(len, headroom);
-    err = virtqueue_add_inbuf_ctx(rq->vq, rq->sg, 1, buf, ctx, gfp);
-    if (err < 0)
-    {
-        put_page(virt_to_head_page(buf));
-    }
-
-    return err;
-}
-
-/* Assuming a given event_idx value from the other side, if
- * we have just incremented index from old to new_idx,
- * should we trigger an event? */
-int32_t vring_need_event(__u16 event_idx, __u16 new_idx, __u16 old)
-{
-    /* Note: Xen has similar logic for notification hold-off
-     * in include/xen/interface/io/ring.h with req_event and req_prod
-     * corresponding to event_idx + 1 and new_idx respectively.
-     * Note also that req_event and req_prod in Xen start at 1,
-     * event indexes in custom queue start at 0. */
-    return (__u16)(new_idx - event_idx - 1) < (__u16)(new_idx - old);
-}
-
-bool virtqueue_kick_prepare_packed(struct virtqueue *_vq)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-    uint16_t new = 0;
-    uint16_t old = 0;
-    uint16_t off_wrap = 0;
-    uint16_t flags = 0;
-    uint16_t wrap_counter = 0;
-    uint16_t event_idx = 0;
-    bool needs_kick = false;
-    union
-    {
-        struct
-        {
-            __le16 off_wrap;
-            __le16 flags;
-        };
-        uint32_t u32;
-    } snapshot;
-
-    START_USE(vq);
-
-    /*
-     * We need to expose the new flags value before checking notification
-     * suppressions.
-     */
-    vqm_mb(vq->weak_barriers);
-
-    old = vq->packed.next_avail_idx - vq->num_added;
-    new = vq->packed.next_avail_idx;
-    vq->num_added = 0;
-
-    snapshot.u32 = *(uint32_t *)vq->packed.vring.device;
-    flags = le16_to_cpu(snapshot.flags);
-
-    LAST_ADD_TIME_CHECK(vq);
-    LAST_ADD_TIME_INVALID(vq);
-
-    if (flags != VRING_PACKED_EVENT_FLAG_DESC)
-    {
-        needs_kick = (flags != VRING_PACKED_EVENT_FLAG_DISABLE);
-        goto out;
-    }
-
-    off_wrap = le16_to_cpu(snapshot.off_wrap);
-
-    wrap_counter = off_wrap >> VRING_PACKED_EVENT_F_WRAP_CTR;
-    event_idx = off_wrap & ~(1 << VRING_PACKED_EVENT_F_WRAP_CTR);
-    if (wrap_counter != vq->packed.avail_wrap_counter)
-    {
-        event_idx -= vq->packed.vring.num;
-    }
-
-    needs_kick = vring_need_event(event_idx, new, old);
-out:
-    END_USE(vq);
-    return needs_kick;
-}
-
-/*
- * Returns false if we couldn't fill entirely (OOM).
- *
- * Normally run in the receive path, but can also be run from ndo_open
- * before we're receiving packets, or from refill_work which is
- * careful to disable receiving (using napi_disable).
- */
-bool try_fill_recv(struct net_device *netdev, struct receive_queue *rq, gfp_t gfp)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t err = 0;
-    bool oom = 0;
-    unsigned long flags = 0;
-
-    do
-    {
-        err = add_recvbuf_mergeable(en_dev, rq, gfp);
-        oom = err == -ENOMEM;
-        if (err)
-        {
-            break;
-        }
-    } while (rq->vq->num_free);
-
-    if (virtqueue_kick_prepare_packed(rq->vq) && virtqueue_notify(rq->vq))
-    {
-        flags = u64_stats_update_begin_irqsave(&rq->stats.syncp);
-        rq->stats.kicks++;
-        u64_stats_update_end_irqrestore(&rq->stats.syncp, flags);
-    }
-
-    return !oom;
-}
-
-int32_t virtnet_receive(struct receive_queue *rq, int32_t budget)
-{
-    struct net_device *netdev = rq->vq->vdev;
-    struct zxdh_en_priv *en_priv = netdev_priv(rq->vq->vdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct virtnet_rq_stats stats = {};
-    uint32_t len = 0;
-    void *buf = NULL;
-    int32_t i = 0;
-    void *ctx = NULL;
-
-    while (stats.packets < budget && (buf = virtqueue_get_buf_ctx_packed(rq->vq, &len, &ctx)))
-    {
-        receive_buf(en_dev, rq, buf, len, ctx, &stats);
-        stats.packets++;
-        netdev->stats.rx_packets++;
-    }
-
-    if (rq->vq->num_free > min((uint32_t)budget, virtqueue_get_vring_size(rq->vq)) / 2)
-    {
-        if (!try_fill_recv(rq->vq->vdev, rq, GFP_ATOMIC))
-        {
-            schedule_delayed_work(&en_dev->refill, 0);
-        }
-    }
-
-    u64_stats_update_begin(&rq->stats.syncp);
-    for (i = 0; i < VIRTNET_RQ_STATS_LEN; i++)
-    {
-        size_t offset = virtnet_rq_stats_desc[i].offset;
-        uint64_t *item;
-
-        item = (uint64_t *)((uint8_t *)&rq->stats + offset);
-        *item += *(uint64_t *)((uint8_t *)&stats + offset);
-    }
-    u64_stats_update_end(&rq->stats.syncp);
-
-    return stats.packets;
-}
-
-void virtqueue_napi_complete(struct napi_struct *napi, struct virtqueue *vq, int32_t processed)
-{
-    int32_t opaque = 0;
-
-    opaque = virtqueue_enable_cb_prepare(vq);
-    if (napi_complete_done(napi, processed))
-    {
-        if (unlikely(virtqueue_poll(vq, opaque)))
-        {
-            virtqueue_napi_schedule(napi, vq);
-        }
-    }
-    else
-    {
-        virtqueue_disable_cb(vq);
-    }
-}
-
-int virtnet_poll(struct napi_struct *napi, int budget)
-{
-    struct receive_queue *rq = container_of(napi, struct receive_queue, napi);
-    uint32_t received = 0;
-
-    virtnet_poll_cleantx(rq);
-
-    received = virtnet_receive(rq, budget);
-
-    /* Out of packets? */
-    if (received < budget)
-    {
-        virtqueue_napi_complete(napi, rq->vq, received);
-    }
-
-    return received;
-}
-
-int32_t virtnet_alloc_queues(struct zxdh_en_device *en_dev)
-{
-    int32_t i = 0;
-
-    en_dev->sq = kcalloc(en_dev->max_queue_pairs, sizeof(*en_dev->sq), GFP_KERNEL);
-    if (unlikely(en_dev->sq == NULL))
-    {
-        LOG_ERR("en_dev->sq kcalloc failed\n");
-        goto err_sq;
-    }
-
-    en_dev->rq = kcalloc(en_dev->max_queue_pairs, sizeof(*en_dev->rq), GFP_KERNEL);
-    if (unlikely(en_dev->rq == NULL))
-    {
-        LOG_ERR("en_dev->rq kcalloc failed\n");
-        goto err_rq;
-    }
-
-    INIT_DELAYED_WORK(&en_dev->refill, refill_work);
-
-    for (i = 0; i < en_dev->curr_queue_pairs; i++)
-    {
-        en_dev->rq[i].pages = NULL;
-        netif_napi_add(en_dev->netdev, &en_dev->rq[i].napi, virtnet_poll, NAPI_POLL_WEIGHT);
-        netif_tx_napi_add(en_dev->netdev, &en_dev->sq[i].napi, virtnet_poll_tx, NAPI_POLL_WEIGHT);
-
-        sg_init_table(en_dev->rq[i].sg, ARRAY_SIZE(en_dev->rq[i].sg));
-        ewma_pkt_len_init(&en_dev->rq[i].mrg_avg_pkt_len);
-        sg_init_table(en_dev->sq[i].sg, ARRAY_SIZE(en_dev->sq[i].sg));
-
-        u64_stats_init(&en_dev->rq[i].stats.syncp);
-        u64_stats_init(&en_dev->sq[i].stats.syncp);
-    }
-
-    return 0;
-
-err_rq:
-    kfree(en_dev->sq);
-    en_dev->sq = NULL;
-err_sq:
-    return -ENOMEM;
-}
-
-/**
- * virtqueue_set_affinity - setting affinity for a virtqueue
- * @vq: the virtqueue
- * @cpu_mask: the cpu no.
- *
- * Pay attention the function are best-effort: the affinity hint may not be set
- * due to config support, irq type and sharing.
- *
- */
-int32_t virtqueue_set_affinity(struct virtqueue *vq, const struct cpumask *cpu_mask)
-{
-    if (!vq->callback)
-    {
-        LOG_ERR("vq->callback is null\n");
-        return -EINVAL;
-    }
-
-    return 0;
-}
-
-void refill_work(struct work_struct *work)
-{
-    int32_t i = 0;
-    bool still_empty = false;
-    struct zxdh_en_device *en_dev = container_of(work, struct zxdh_en_device, refill.work);
-
-    for (i = 0; i < en_dev->curr_queue_pairs; i++)
-    {
-        struct receive_queue *rq = &en_dev->rq[i];
-
-        napi_disable(&rq->napi);
-        still_empty = !try_fill_recv(en_dev->netdev, rq, GFP_KERNEL);
-        virtnet_napi_enable(rq->vq, &rq->napi);
-
-        /* In theory, this can happen: if we don't get any buffers in
-         * we will *never* try to fill again.
-         */
-        if (still_empty)
-        {
-            schedule_delayed_work(&en_dev->refill, HZ/2);
-        }
-    }
-}
-
-int32_t dh_eq_vqs_vring_int(struct notifier_block *nb, unsigned long action, void *data)
-{
-    struct dh_eq_vq *eq_vq = container_of(nb, struct dh_eq_vq, irq_nb);
-    struct dh_eq_vqs *eq_vqs = container_of(eq_vq, struct dh_eq_vqs, vq_s);
-    struct list_head *item = NULL;
-    struct zxdh_pci_vq_info *info = NULL;
-    struct vring_virtqueue *vq = NULL;
-
-    list_for_each(item, &eq_vqs->vqs)
-    {
-        info = list_entry(item, struct zxdh_pci_vq_info, node);
-
-        vq = to_vvq(info->vq);
-        if (!more_used_packed(vq))
-        {
-            continue;
-        }
-
-        if (unlikely(vq->broken))
-        {
-            LOG_ERR("vq:%d is broken\n", info->vq->phy_index);
-            continue;
-        }
-
-        /* Just a hint for performance: so it's ok that this can be racy! */
-        if (vq->event)
-        {
-            vq->event_triggered = true;
-        }
-
-        if (vq->vq.callback)
-        {
-            vq->vq.callback(&vq->vq);
-        }
-    }
-
-    return 0;
-}
-
-static DEFINE_SPINLOCK(vp_find_lock);
-
-int32_t vp_find_vqs_msix(struct net_device *netdev, unsigned nvqs,
-                         struct virtqueue *vqs[], vq_callback_t *callbacks[],
-                         const char * const names[], const bool *ctx)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t err = 0;
-    uint16_t qidx = 0;
-    int32_t phy_index = -1;
-
-    en_dev->vqs = kcalloc(nvqs, sizeof(*en_dev->vqs), GFP_KERNEL);
-    if (unlikely(en_dev->vqs == NULL))
-    {
-        LOG_ERR("en_dev->vqs kcalloc failed\n");
-        return -ENOMEM;
-    }
-
-    spin_lock(&vp_find_lock);
-    for (qidx = 0; qidx < nvqs; ++qidx)
-    {
-        phy_index = en_dev->ops->get_phy_vq(en_dev->parent, qidx);
-        if(phy_index < 0)
-        {
-            LOG_ERR("get_phy_vq failed: %d\n", phy_index);
-            err = phy_index;
-            goto err;
-        }
-        en_dev->phy_index[qidx] = phy_index;
-
-        vqs[qidx] = vp_setup_vq(netdev, qidx, callbacks[qidx], names[qidx], ctx ? ctx[qidx] : false, qidx);
-        if (IS_ERR_OR_NULL(vqs[qidx]))
-        {
-            err = PTR_ERR(vqs[qidx]);
-            LOG_ERR("vp_setup_vq failed: %d\n", err);
-            goto err;
-        }
-
-        en_dev->ops->set_queue_enable(en_dev->parent, phy_index, true);
-    }
-    spin_unlock(&vp_find_lock);
-    return 0;
-
-err:
-    en_dev->ops->release_phy_vq(en_dev->parent, en_dev->phy_index, qidx+1);
-    spin_unlock(&vp_find_lock);
-    vp_del_vqs(netdev);
-    return err;
-}
-
-/* How large should a single buffer be so a queue full of these can fit at
- * least one full packet?
- * Logic below assumes the mergeable buffer header is used.
- */
-uint32_t mergeable_min_buf_len(struct zxdh_en_device *en_dev, struct virtqueue *vq)
-{
-    const uint32_t hdr_len = sizeof(struct zxdh_net_hdr);
-    uint32_t rq_size = virtqueue_get_vring_size(vq);
-    uint32_t packet_len = en_dev->netdev->max_mtu;
-    uint32_t buf_len = hdr_len + ETH_HLEN + VLAN_HLEN + packet_len;
-    uint32_t min_buf_len = DIV_ROUND_UP(buf_len, rq_size);
-
-    return max(max(min_buf_len, hdr_len) - hdr_len, (uint32_t)GOOD_PACKET_LEN);
-}
-
-void zxdh_en_recv_pkts(struct virtqueue *rvq)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(rvq->vdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct receive_queue *rq = &en_dev->rq[vq2rxq(rvq)];
-
-    virtqueue_napi_schedule(&rq->napi, rvq);
-}
-
-void zxdh_en_xmit_pkts(struct virtqueue *tvq)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(tvq->vdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct napi_struct *napi = &en_dev->sq[vq2txq(tvq)].napi;
-
-    /* Suppress further interrupts. */
-    virtqueue_disable_cb(tvq);
-
-    if (napi->weight)
-    {
-        virtqueue_napi_schedule(napi, tvq);
-    }
-    else
-    {
-        /* We were probably waiting for more output buffers. */
-        netif_wake_subqueue(en_dev->netdev, vq2txq(tvq));
-        en_dev->hw_stats.q_stats[vq2txq(tvq)].q_tx_wake++;
-    }
-}
-
-int32_t virtnet_find_vqs(struct zxdh_en_device *en_dev)
-{
-    vq_callback_t **callbacks = NULL;
-    struct virtqueue **vqs = NULL;
-    int32_t ret = -ENOMEM;
-    int32_t i = 0;
-    int32_t total_vqs = 0;
-    const char **names = NULL;
-    bool *ctx = NULL;
-
-    total_vqs = en_dev->max_queue_pairs * 2;
-
-    /* Allocate space for find_vqs parameters */
-    vqs = kcalloc(total_vqs, sizeof(*vqs), GFP_KERNEL);
-    if (unlikely(vqs == NULL))
-    {
-        LOG_ERR("vqs kcalloc failed\n");
-        goto err_vq;
-    }
-
-    callbacks = kmalloc_array(total_vqs, sizeof(*callbacks), GFP_KERNEL);
-    if (unlikely(callbacks == NULL))
-    {
-        LOG_ERR("callbacks kmalloc_array failed\n");
-        goto err_callback;
-    }
-
-    names = kmalloc_array(total_vqs, sizeof(*names), GFP_KERNEL);
-    if (unlikely(names == NULL))
-    {
-        LOG_ERR("names kmalloc_array failed\n");
-        goto err_names;
-    }
-
-    ctx = kcalloc(total_vqs, sizeof(*ctx), GFP_KERNEL);
-    if (unlikely(ctx == NULL))
-    {
-        LOG_ERR("ctx kmalloc failed\n");
-        goto err_ctx;
-    }
-
-    /* Allocate/initialize parameters for services send/receive virtqueues */
-    for (i = 0; i < en_dev->max_queue_pairs; i++)
-    {
-        callbacks[rxq2vq(i)] = zxdh_en_recv_pkts;
-        callbacks[txq2vq(i)] = zxdh_en_xmit_pkts;
-        sprintf(en_dev->rq[i].name, "input.%d", i);
-        sprintf(en_dev->sq[i].name, "output.%d", i);
-        names[rxq2vq(i)] = en_dev->rq[i].name;
-        names[txq2vq(i)] = en_dev->sq[i].name;
-        if (ctx)
-        {
-            ctx[rxq2vq(i)] = true;
-        }
-    }
-
-    ret = vp_find_vqs_msix(en_dev->netdev, total_vqs, vqs, callbacks, names, ctx);
-    if (ret)
-    {
-        LOG_ERR("vp_find_vqs_msix failed: %d\n", ret);
-        goto err_find;
-    }
-
-    for (i = 0; i < en_dev->max_queue_pairs; i++)
-    {
-        en_dev->rq[i].vq = vqs[rxq2vq(i)];
-        en_dev->rq[i].min_buf_len = mergeable_min_buf_len(en_dev, en_dev->rq[i].vq);
-        en_dev->sq[i].vq = vqs[txq2vq(i)];
-    }
-
-err_find:
-    kfree(ctx);
-    ctx = NULL;
-err_ctx:
-    kfree(names);
-    names = NULL;
-err_names:
-    kfree(callbacks);
-    callbacks = NULL;
-err_callback:
-    kfree(vqs);
-    vqs = NULL;
-err_vq:
-    return ret;
-}
-
-void virtnet_free_queues(struct zxdh_en_device *en_dev)
-{
-    int32_t i = 0;
-
-    for (i = 0; i < en_dev->max_queue_pairs; i++)
-    {
-        netif_napi_del(&en_dev->rq[i].napi);
-        netif_napi_del(&en_dev->sq[i].napi);
-    }
-
-    /* We called __netif_napi_del(),
-     * we need to respect an RCU grace period before freeing zxdev->rq
-     */
-    synchronize_net();
-
-    kfree(en_dev->rq);
-    kfree(en_dev->sq);
-}
-
-void *virtqueue_detach_unused_buf_packed(struct virtqueue *_vq)
-{
-    struct vring_virtqueue *vq = to_vvq(_vq);
-    uint32_t i = 0;
-    void *buf = NULL;
-
-    START_USE(vq);
-
-    for (i = 0; i < vq->packed.vring.num; i++)
-    {
-        if (!vq->packed.desc_state[i].data)
-        {
-            continue;
-        }
-
-        /* detach_buf clears data, so grab it now. */
-        buf = vq->packed.desc_state[i].data;
-        detach_buf_packed(vq, i, NULL);
-        END_USE(vq);
-        return buf;
-    }
-
-    /* That should have freed everything. */
-    BUG_ON(vq->vq.num_free != vq->packed.vring.num);
-
-    END_USE(vq);
-    return NULL;
-}
-
-void zxdh_free_unused_bufs(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct virtqueue *vq = NULL;
-    void *buf = NULL;
-    int32_t i = 0;
-
-    for (i = 0; i < en_dev->max_queue_pairs; i++)
-    {
-        vq = en_dev->sq[i].vq;
-        while ((buf = virtqueue_detach_unused_buf_packed(vq)) != NULL)
-        {
-#ifdef ZXDH_MSGQ
-            if (i == (en_dev->max_queue_pairs - 1))
-            {
-                NEED_MSGQ(en_dev)
-                {
-                    ZXDH_FREE_PTR(buf);
-                    continue;
-                }
-            }
-#endif
-            dev_kfree_skb(buf);
-        }
-    }
-
-    for (i = 0; i < en_dev->max_queue_pairs; i++)
-    {
-        vq = en_dev->rq[i].vq;
-        while ((buf = virtqueue_detach_unused_buf_packed(vq)) != NULL)
-        {
-            put_page(virt_to_head_page(buf));
-        }
-    }
-}
-
-struct page *get_a_page(struct receive_queue *rq, gfp_t gfp_mask)
-{
-    struct page *p = rq->pages;
-
-    if (p)
-    {
-        rq->pages = (struct page *)p->private;
-        /* clear private here, it is used to chain pages */
-        p->private = 0;
-    }
-    else
-    {
-        p = alloc_page(gfp_mask);
-    }
-    return p;
-}
-
-void _free_receive_bufs(struct zxdh_en_device *en_dev)
-{
-    int32_t i = 0;
-
-    for (i = 0; i < en_dev->max_queue_pairs; i++)
-    {
-        while (en_dev->rq[i].pages)
-        {
-            __free_pages(get_a_page(&en_dev->rq[i], GFP_KERNEL), 0);
-        }
-    }
-}
-
-void zxdh_free_receive_bufs(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    rtnl_lock();
-    _free_receive_bufs(en_dev);
-    rtnl_unlock();
-}
-
-void zxdh_free_receive_page_frags(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t i = 0;
-
-    for (i = 0; i < en_dev->max_queue_pairs; i++)
-    {
-        if (en_dev->rq[i].alloc_frag.page)
-        {
-            put_page(en_dev->rq[i].alloc_frag.page);
-        }
-    }
-}
-
-void zxdh_virtnet_del_vqs(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    vp_del_vqs(netdev);
-    en_dev->ops->vqs_unbind_eqs(en_dev->parent, (en_dev->max_queue_pairs * 2 - 1));
-    en_dev->ops->vqs_channel_unbind_handler(en_dev->parent, (en_dev->max_queue_pairs * 2 - 1));
-    virtnet_free_queues(en_dev);
-}
-
-void zxdh_vqs_uninit(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    zxdh_vp_reset(netdev);
-
-    cancel_delayed_work_sync(&en_dev->refill);
-    zxdh_free_unused_bufs(netdev);
-    zxdh_free_receive_bufs(netdev);
-    zxdh_free_receive_page_frags(netdev);
-    zxdh_virtnet_del_vqs(netdev);
-    en_dev->ops->release_phy_vq(en_dev->parent, en_dev->phy_index, en_dev->max_queue_pairs*2);
-}
-
-int32_t zxdh_vqs_init(struct net_device *netdev)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t ret = 0;
-
-    en_dev->hdr_len = sizeof(struct zxdh_net_hdr);
-    en_dev->any_header_sg = zxdh_has_feature(netdev, ZXDH_F_ANY_LAYOUT);
-    en_dev->netdev->needed_headroom = en_dev->hdr_len;
-    en_dev->max_queue_pairs = max_pairs;
-    memset(en_dev->phy_index, 0xFF, sizeof(en_dev->phy_index));
-
-    if (en_dev->ops->is_bond(en_dev->parent))
-    {
-        en_dev->max_queue_pairs = ZXDH_BOND_ETH_MQ_PAIRS_NUM;
-    }
-    en_dev->curr_queue_pairs = en_dev->max_queue_pairs;
-
-#ifdef ZXDH_MSGQ
-    IS_MSGQ_DEV(en_dev)
-    {
-        en_dev->need_msgq = true;
-        en_dev->max_queue_pairs += ZXDH_PQ_PAIRS_NUM;
-        LOG_INFO("max_queue_pairs: %d\n", en_dev->max_queue_pairs);
-    }
-#endif
-
-    INIT_LIST_HEAD(&en_dev->vqs_list);
-    spin_lock_init(&en_dev->vqs_list_lock);
-
-    INIT_LIST_HEAD(&en_dev->virtqueues);
-    spin_lock_init(&en_dev->lock);
-
-    /* Allocate services send & receive queues */
-    ret = virtnet_alloc_queues(en_dev);
-    if (ret)
-    {
-        LOG_ERR("virtnet_alloc_queues failed: %d\n", ret);
-        return ret;
-    }
-
-    ret = virtnet_find_vqs(en_dev);
-    if (ret)
-    {
-        LOG_ERR("virtnet_find_vqs failed: %d\n", ret);
-        goto err_find_vqs;
-    }
-
-    rtnl_lock();
-    netif_set_real_num_tx_queues(en_dev->netdev, en_dev->curr_queue_pairs);
-    rtnl_unlock();
-    rtnl_lock();
-    netif_set_real_num_rx_queues(en_dev->netdev, en_dev->curr_queue_pairs);
-    rtnl_unlock();
-
-    return 0;
-
-err_find_vqs:
-    virtnet_free_queues(en_dev);
-    return ret;
-}
+#include "queue.h"
+#include "../en_aux.h"
+#include <linux/device.h>
+#include <linux/dinghai/kcompat.h>
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include <linux/pci.h>
+#include <linux/scatterlist.h>
+#include <xen/xen.h>
+#ifdef TIME_STAMP_1588
+#include "en_1588_pkt_proc.h"
+#endif
+#ifdef ZXDH_MSGQ
+#include "priv_queue.h"
+#endif
+
+static uint32_t features_table[] = {
+	ZXDH_NET_F_MRG_RXBUF, ZXDH_NET_F_STATUS,		 ZXDH_NET_F_CTRL_VQ,
+	ZXDH_NET_F_MQ,		  ZXDH_RING_F_INDIRECT_DESC, ZXDH_RING_F_EVENT_IDX,
+	ZXDH_F_VERSION_1,	  ZXDH_F_RING_PACKED
+};
+
+void zxdh_print_vring_info(struct virtqueue *vq, uint32_t desc_index,
+						   uint32_t desc_num)
+{
+	struct vring_virtqueue *vvq = to_vvq(vq);
+	struct vring_packed_desc *desc = NULL;
+	uint32_t i = 0;
+
+	LOG_INFO("phy_index         : %d\n", vq->phy_index);
+	LOG_INFO("num free          : %d\n", vq->num_free);
+	LOG_INFO("vring address     : 0x%llx\n", (uint64_t)&vvq->packed.vring);
+	LOG_INFO("vring size        : %d\n", vvq->packed.vring.num);
+	LOG_INFO("last_used_idx     : %d\n", vvq->last_used_idx);
+	LOG_INFO("avail_wrap_counter: %d\n", vvq->packed.avail_wrap_counter);
+	LOG_INFO("used_wrap_counter : %d\n", vvq->packed.used_wrap_counter);
+	LOG_INFO("next_avail_idx    : %d\n", vvq->packed.next_avail_idx);
+	LOG_INFO("free head         : %d\n", vvq->free_head);
+	LOG_INFO("driver->flags     : 0x%x\n", vvq->packed.vring.driver->flags);
+	LOG_INFO("driver->off_wrap  : %d\n", vvq->packed.vring.driver->off_wrap);
+	LOG_INFO("device->flags     : 0x%x\n", vvq->packed.vring.device->flags);
+	LOG_INFO("device->off_wrap  : %d\n", vvq->packed.vring.device->off_wrap);
+	LOG_INFO("DESC[x]:\tDESC_ADDR\t[BUFFER_ADDR]\t\t[LEN]\t\t[ID]\t[FLAG]\n");
+
+	desc = vvq->packed.vring.desc;
+	for (i = desc_index; i < desc_num; i++) {
+		LOG_INFO("DESC[%d] 0x%llx:\t0x%016llx\t0x%08x\t%8d\t0x%x\n", i,
+				 (uint64_t)desc, desc->addr, desc->len, desc->id, desc->flags);
+		desc++;
+	}
+
+	return;
+}
+
+/* enable irq handlers */
+void zxdh_vp_enable_cbs(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t i = 0;
+
+	for (i = 0; i < en_dev->channels_num; i++) {
+		en_dev->ops->switch_vqs_channel(en_dev->parent, i, 1);
+	}
+}
+
+/* disable irq handlers */
+void zxdh_vp_disable_cbs(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t i = 0;
+
+	for (i = 0; i < en_dev->channels_num; i++) {
+		en_dev->ops->switch_vqs_channel(en_dev->parent, i, 0);
+	}
+}
+
+void zxdh_vp_reset(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	/* 0 status means a reset. */
+	en_dev->ops->set_status(en_dev->parent, 0);
+
+	/* After writing 0 to device_status, the driver MUST wait for a read of
+   * device_status to return 0 before reinitializing the device.
+   * This will flush out the status write, and flush in device writes,
+   * including MSI-X interrupts, if any.
+   */
+	while (en_dev->ops->get_status(en_dev->parent) != 0) {
+		msleep(1);
+	}
+
+	return;
+}
+
+void zxdh_add_status(struct net_device *netdev, uint32_t status)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint8_t dev_status = 0;
+
+	might_sleep();
+
+	dev_status = en_dev->ops->get_status(en_dev->parent);
+
+	en_dev->ops->set_status(en_dev->parent, (dev_status | status));
+
+	return;
+}
+
+bool zxdh_has_status(struct net_device *netdev, uint32_t sbit)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint8_t dev_status = 0;
+
+	dev_status = en_dev->ops->get_status(en_dev->parent);
+
+	return (dev_status & sbit);
+}
+
+void zxdh_pf_features_init(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t i = 0;
+	uint64_t features = 0;
+
+	en_dev->device_feature = en_dev->ops->get_features(en_dev->parent);
+	en_dev->device_feature |= BIT(34);
+	en_dev->driver_feature = 0;
+
+	for (i = 0; i < ARRAY_SIZE(features_table); i++) {
+		features = features_table[i];
+		en_dev->driver_feature |= (1ULL << features);
+	}
+	en_dev->guest_feature = en_dev->device_feature & 0xfffffff5dfffffff;
+	en_dev->ops->set_features(en_dev->parent, en_dev->guest_feature);
+
+	return;
+}
+
+bool zxdh_has_feature(struct net_device *netdev, uint32_t fbit)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	return en_dev->guest_feature & BIT_ULL(fbit);
+}
+
+int32_t vq2txq(struct virtqueue *vq)
+{
+	return (vq->index - 1) / 2;
+}
+
+int32_t txq2vq(int32_t txq)
+{
+	return txq * 2 + 1;
+}
+int32_t vq2rxq(struct virtqueue *vq)
+{
+	return vq->index / 2;
+}
+
+int32_t rxq2vq(int32_t rxq)
+{
+	return rxq * 2;
+}
+
+inline void vqm_mb(bool weak_barriers)
+{
+	if (weak_barriers) {
+		virt_mb();
+	} else {
+		mb();
+	}
+}
+
+inline void vqm_rmb(bool weak_barriers)
+{
+	if (weak_barriers) {
+		virt_rmb();
+	} else {
+		dma_rmb();
+	}
+}
+
+inline void vqm_wmb(bool weak_barriers)
+{
+	if (weak_barriers) {
+		virt_wmb();
+	} else {
+		dma_wmb();
+	}
+}
+
+void vring_del_virtqueue(struct virtqueue *_vq)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(_vq->vdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct vring_virtqueue *vq = to_vvq(_vq);
+
+	spin_lock(&en_dev->vqs_list_lock);
+	list_del(&_vq->list);
+	spin_unlock(&en_dev->vqs_list_lock);
+
+	if (vq->we_own_ring) {
+		vring_free_queue(vq->vq.vdev, vq->packed.ring_size_in_bytes,
+						 vq->packed.vring.desc, vq->packed.ring_dma_addr);
+
+		vring_free_queue(vq->vq.vdev, vq->packed.event_size_in_bytes,
+						 vq->packed.vring.driver,
+						 vq->packed.driver_event_dma_addr);
+
+		vring_free_queue(vq->vq.vdev, vq->packed.event_size_in_bytes,
+						 vq->packed.vring.device,
+						 vq->packed.device_event_dma_addr);
+
+		kfree(vq->packed.desc_state);
+		vq->packed.desc_state = NULL;
+		kfree(vq->packed.desc_extra);
+		vq->packed.desc_extra = NULL;
+	}
+
+	kfree(vq);
+	vq = NULL;
+}
+
+void del_vq(struct zxdh_pci_vq_info *info)
+{
+	struct virtqueue *vq = info->vq;
+	struct zxdh_en_priv *en_priv = netdev_priv(vq->vdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	en_dev->ops->vq_unbind_channel(en_dev->parent, vq->phy_index);
+
+	en_dev->ops->vp_modern_unmap_vq_notify(en_dev->parent, vq->priv);
+
+	vring_del_virtqueue(vq);
+}
+
+void vp_del_vq(struct virtqueue *vq)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(vq->vdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_pci_vq_info *info = en_dev->vqs[vq->index];
+	unsigned long flags;
+
+	spin_lock_irqsave(&en_dev->lock, flags);
+	list_del(&info->node);
+	spin_unlock_irqrestore(&en_dev->lock, flags);
+
+	del_vq(info);
+	kfree(info);
+	en_dev->vqs[vq->index] = NULL;
+}
+
+void vp_detach_vqs(void *para)
+{
+	struct net_device *netdev = para;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct virtqueue *vq;
+	struct virtqueue *n;
+
+	list_for_each_entry_safe(vq, n, &en_dev->vqs_list, list) {
+		vp_del_vq(vq);
+	}
+}
+
+void vp_del_vqs(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	vp_detach_vqs(netdev);
+
+	kfree(en_dev->vqs);
+	en_dev->vqs = NULL;
+}
+
+/**
+ * virtqueue_get_vring_size - return the size of the virtqueue's vring
+ * @_vq: the struct virtqueue containing the vring of interest.
+ *
+ * Returns the size of the vring.  This is mainly used for boasting to
+ * userspace.  Unlike other operations, this need not be serialized.
+ */
+uint32_t virtqueue_get_vring_size(struct virtqueue *_vq)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+
+	return vq->packed.vring.num;
+}
+
+dma_addr_t virtqueue_get_desc_addr(struct virtqueue *_vq)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+
+	BUG_ON(!vq->we_own_ring);
+
+	return vq->packed.ring_dma_addr;
+}
+
+dma_addr_t virtqueue_get_avail_addr(struct virtqueue *_vq)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+
+	BUG_ON(!vq->we_own_ring);
+
+	return vq->packed.driver_event_dma_addr;
+}
+
+dma_addr_t virtqueue_get_used_addr(struct virtqueue *_vq)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+
+	BUG_ON(!vq->we_own_ring);
+
+	return vq->packed.device_event_dma_addr;
+}
+
+bool vqm_has_dma_quirk(struct net_device *netdev)
+{
+	/*
+   * Note the reverse polarity of the quirk feature (compared to most
+   * other features), this is for compatibility with legacy systems.
+   */
+	return !zxdh_has_feature(netdev, ZXDH_F_ACCESS_PLATFORM);
+}
+
+bool vring_use_dma_api(struct net_device *netdev)
+{
+	if (!vqm_has_dma_quirk(netdev)) {
+		return true;
+	}
+
+	/* Otherwise, we are left to guess. */
+	/*
+   * In theory, it's possible to have a buggy QEMU-supposed
+   * emulated Q35 IOMMU and Xen enabled at the same time.  On
+   * such a configuration, zxdh has never worked and will
+   * not work without an even larger kludge.  Instead, enable
+   * the DMA API if we're a Xen guest, which at least allows
+   * all of the sensible Xen configurations to work correctly.
+   */
+	if (xen_domain()) {
+		return true;
+	}
+
+	return false;
+}
+
+void vring_free_queue(struct net_device *netdev, size_t size, void *queue,
+					  dma_addr_t dma_handle)
+{
+	if (vring_use_dma_api(netdev)) {
+		dma_free_coherent(netdev->dev.parent, size, queue, dma_handle);
+	} else {
+		free_pages_exact(queue, PAGE_ALIGN(size));
+	}
+}
+
+void *vring_alloc_queue(struct net_device *netdev, size_t size,
+						dma_addr_t *dma_handle, gfp_t flag)
+{
+	if (vring_use_dma_api(netdev)) {
+		return dma_alloc_coherent(netdev->dev.parent, size, dma_handle, flag);
+	} else {
+		void *queue = alloc_pages_exact(PAGE_ALIGN(size), flag);
+
+		if (queue) {
+			phys_addr_t phys_addr = virt_to_phys(queue);
+			*dma_handle = (dma_addr_t)phys_addr;
+
+			/*
+       * Sanity check: make sure we dind't truncate
+       * the address.  The only arches I can find that
+       * have 64-bit phys_addr_t but 32-bit dma_addr_t
+       * are certain non-highmem MIPS and x86
+       * configurations, but these configurations
+       * should never allocate physical pages above 32
+       * bits, so this is fine.  Just in case, throw a
+       * warning and abort if we end up with an
+       * unrepresentable address.
+       */
+			if (WARN_ON_ONCE(*dma_handle != phys_addr)) {
+				free_pages_exact(queue, PAGE_ALIGN(size));
+				return NULL;
+			}
+		}
+		return queue;
+	}
+}
+
+struct vring_desc_extra *vring_alloc_desc_extra(struct vring_virtqueue *vq,
+												uint32_t num)
+{
+	struct vring_desc_extra *desc_extra = NULL;
+	uint32_t i = 0;
+
+	desc_extra =
+			kmalloc_array(num, sizeof(struct vring_desc_extra), GFP_KERNEL);
+	if (unlikely(desc_extra == NULL)) {
+		return NULL;
+	}
+
+	memset(desc_extra, 0, num * sizeof(struct vring_desc_extra));
+
+	for (i = 0; i < num - 1; i++) {
+		desc_extra[i].next = i + 1;
+	}
+
+	return desc_extra;
+}
+
+struct virtqueue *vring_create_virtqueue_packed(
+		uint32_t index, uint32_t num, uint32_t vring_align,
+		struct net_device *netdev, bool weak_barriers, bool may_reduce_num,
+		bool context, bool (*notify)(struct virtqueue *),
+		void (*callback)(struct virtqueue *), const char *name)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct vring_virtqueue *vq = NULL;
+	struct vring_packed_desc *ring = NULL;
+	struct vring_packed_desc_event *driver = NULL;
+	struct vring_packed_desc_event *device = NULL;
+	dma_addr_t ring_dma_addr;
+	dma_addr_t driver_event_dma_addr;
+	dma_addr_t device_event_dma_addr;
+	size_t ring_size_in_bytes;
+	size_t event_size_in_bytes;
+
+	ring_size_in_bytes = num * sizeof(struct vring_packed_desc);
+
+	ring = vring_alloc_queue(netdev, ring_size_in_bytes, &ring_dma_addr,
+							 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
+	if (unlikely(ring == NULL)) {
+		goto err_ring;
+	}
+
+	event_size_in_bytes = sizeof(struct vring_packed_desc_event);
+
+	driver = vring_alloc_queue(netdev, event_size_in_bytes,
+							   &driver_event_dma_addr,
+							   GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
+	if (unlikely(driver == NULL)) {
+		goto err_driver;
+	}
+
+	device = vring_alloc_queue(netdev, event_size_in_bytes,
+							   &device_event_dma_addr,
+							   GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
+	if (unlikely(device == NULL)) {
+		goto err_device;
+	}
+
+	vq = kmalloc(sizeof(*vq), GFP_KERNEL);
+	if (unlikely(vq == NULL)) {
+		goto err_vq;
+	}
+
+	vq->vq.callback = callback;
+	vq->vq.vdev = netdev;
+	vq->vq.name = name;
+	vq->vq.num_free = num;
+	vq->vq.index = index;
+	vq->we_own_ring = true;
+	vq->notify = notify;
+	vq->weak_barriers = weak_barriers;
+	vq->broken = false;
+	vq->last_used_idx = 0;
+	vq->event_triggered = false;
+	vq->num_added = 0;
+	vq->packed_ring = true;
+	vq->use_dma_api = vring_use_dma_api(netdev);
+#ifdef DEBUG
+	vq->in_use = false;
+	vq->last_add_time_valid = false;
+#endif
+
+	vq->indirect = zxdh_has_feature(netdev, ZXDH_RING_F_INDIRECT_DESC) &&
+				   !context;
+	vq->event = zxdh_has_feature(netdev, ZXDH_RING_F_EVENT_IDX);
+
+	if (zxdh_has_feature(netdev, ZXDH_F_ORDER_PLATFORM)) {
+		vq->weak_barriers = false;
+	}
+
+	vq->packed.ring_dma_addr = ring_dma_addr;
+	vq->packed.driver_event_dma_addr = driver_event_dma_addr;
+	vq->packed.device_event_dma_addr = device_event_dma_addr;
+
+	vq->packed.ring_size_in_bytes = ring_size_in_bytes;
+	vq->packed.event_size_in_bytes = event_size_in_bytes;
+
+	vq->packed.vring.num = num;
+	vq->packed.vring.desc = ring;
+	vq->packed.vring.driver = driver;
+	vq->packed.vring.device = device;
+
+	vq->packed.next_avail_idx = 0;
+	vq->packed.avail_wrap_counter = 1;
+	vq->packed.used_wrap_counter = 1;
+	vq->packed.event_flags_shadow = 0;
+	vq->packed.avail_used_flags = 1 << VRING_PACKED_DESC_F_AVAIL;
+
+	vq->packed.desc_state = kmalloc_array(
+			num, sizeof(struct vring_desc_state_packed), GFP_KERNEL);
+	if (unlikely(vq->packed.desc_state == NULL)) {
+		LOG_ERR("vq->packed.desc_state kmalloc_array failed\n");
+		goto err_desc_state;
+	}
+
+	memset(vq->packed.desc_state, 0,
+		   num * sizeof(struct vring_desc_state_packed));
+
+	/* Put everything in free lists. */
+	vq->free_head = 0;
+
+	vq->packed.desc_extra = vring_alloc_desc_extra(vq, num);
+	if (unlikely(vq->packed.desc_extra == NULL)) {
+		LOG_ERR("vq->packed.desc_extra vring_alloc_desc_extra failed\n");
+		goto err_desc_extra;
+	}
+
+	/* No callback? Tell other side not to bother us. */
+	if (!callback) {
+		vq->packed.event_flags_shadow = VRING_PACKED_EVENT_FLAG_DISABLE;
+		vq->packed.vring.driver->flags =
+				cpu_to_le16(vq->packed.event_flags_shadow);
+	}
+
+	spin_lock(&en_dev->vqs_list_lock);
+	list_add_tail(&vq->vq.list, &en_dev->vqs_list);
+	spin_unlock(&en_dev->vqs_list_lock);
+
+	return &vq->vq;
+
+err_desc_extra:
+	kfree(vq->packed.desc_state);
+	vq->packed.desc_state = NULL;
+err_desc_state:
+	kfree(vq);
+	vq = NULL;
+err_vq:
+	vring_free_queue(netdev, event_size_in_bytes, device,
+					 device_event_dma_addr);
+err_device:
+	vring_free_queue(netdev, event_size_in_bytes, driver,
+					 driver_event_dma_addr);
+err_driver:
+	vring_free_queue(netdev, ring_size_in_bytes, ring, ring_dma_addr);
+err_ring:
+	return NULL;
+}
+
+/* the notify function used when creating a virt queue */
+bool vp_notify(struct virtqueue *vq)
+{
+	/* we write the queue's selector into the notification register to
+   * signal the other end */
+	iowrite16(vq->phy_index, (void __iomem *)vq->priv);
+
+	return true;
+}
+
+struct virtqueue *vp_setup_vq(struct net_device *netdev, unsigned index,
+							  void (*callback)(struct virtqueue *vq),
+							  const char *name, bool ctx, uint16_t channel_num)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_pci_vq_info *info = kmalloc(sizeof *info, GFP_KERNEL);
+	struct virtqueue *vq = NULL;
+	struct virtqueue *n = NULL;
+	unsigned long flags;
+	uint16_t num = 0;
+	int32_t err = 0;
+	struct dh_vq_handler vq_handler;
+
+	/* fill out our structure that represents an active queue */
+	if (unlikely(info == NULL)) {
+		LOG_ERR("info kmalloc failed\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/*if (index >= en_dev->ops->get_queue_num(en_dev->parent))
+  {
+      LOG_ERR("index over queue nums\n");
+      return ERR_PTR(-ENOENT);
+  }*/
+
+	/* Check if queue is either not available or already active. */
+	num = en_dev->ops->get_queue_size(en_dev->parent, en_dev->phy_index[index]);
+	// if (!num || zxdh_get_queue_enable(en_dev, en_dev->phy_index[index]))
+	// {
+	//     return ERR_PTR(-ENOENT);
+	// }
+	num = ZXDH_PF_MIN_DESC_NUM;
+
+	if (num & (num - 1)) {
+		LOG_ERR("bad queue size %u\n", num);
+		err = -ENOMEM;
+		goto out_info;
+	}
+
+	/* create the vring */
+	vq = vring_create_virtqueue_packed(index, num, SMP_CACHE_BYTES,
+									   en_dev->netdev, true, true, ctx,
+									   vp_notify, callback, name);
+	if (vq == NULL) {
+		LOG_ERR("create the vring failed\n");
+		err = -ENOMEM;
+		goto out_info;
+	}
+
+	/* activate the queue */
+	en_dev->ops->activate_phy_vq(en_dev->parent, en_dev->phy_index[index],
+								 virtqueue_get_vring_size(vq),
+								 virtqueue_get_desc_addr(vq),
+								 virtqueue_get_avail_addr(vq),
+								 virtqueue_get_used_addr(vq));
+
+	vq->priv = (void __force *)en_dev->ops->vp_modern_map_vq_notify(
+			en_dev->parent, en_dev->phy_index[index], NULL);
+	if (!vq->priv) {
+		err = -ENOMEM;
+		goto err_map_notify;
+	}
+
+	vq->phy_index = en_dev->phy_index[index];
+	vq->index = index;
+	info->channel_num = channel_num;
+
+	memset(&vq_handler, 0, sizeof(struct dh_vq_handler));
+	vq_handler.callback = dh_eq_vqs_vring_int;
+	if (channel_num < (en_dev->ops->get_channels_num(en_dev->parent))) {
+		err = en_dev->ops->vqs_channel_bind_handler(en_dev->parent, channel_num,
+													&vq_handler);
+		if (err < 0) {
+			LOG_ERR("vqs_channel_bind_handler failed: %d\n", err);
+			goto err_vqs_channel_bind_handler;
+		}
+	}
+
+	if (channel_num >= (en_dev->ops->get_channels_num(en_dev->parent))) {
+		channel_num = en_dev->ops->get_channels_num(en_dev->parent) - 1;
+	}
+	err = en_dev->ops->vq_bind_channel(en_dev->parent, channel_num,
+									   en_dev->phy_index[index]);
+	if (err < 0) {
+		LOG_ERR("vq_bind_channel failed: %d\n", err);
+		goto err_vq_bind_channel;
+	}
+
+	if (callback) {
+		spin_lock_irqsave(&en_dev->lock, flags);
+		err = en_dev->ops->vqs_bind_eqs(en_dev->parent, channel_num,
+										&info->node);
+		spin_unlock_irqrestore(&en_dev->lock, flags);
+		if (err < 0) {
+			LOG_ERR("vqs_bind_eqs failed: %d\n", err);
+			goto err_vqs_bind_eqs;
+		}
+	} else {
+		INIT_LIST_HEAD(&info->node);
+	}
+
+	info->vq = vq;
+	en_dev->vqs[index] = info;
+	return vq;
+
+err_vqs_bind_eqs:
+	list_for_each_entry_safe(vq, n, &en_dev->vqs_list, list) {
+		en_dev->ops->vq_unbind_channel(en_dev->parent, vq->phy_index);
+	}
+err_vq_bind_channel:
+	if (channel_num < (en_dev->ops->get_channels_num(en_dev->parent))) {
+		en_dev->ops->vqs_channel_unbind_handler(en_dev->parent, channel_num);
+	}
+err_vqs_channel_bind_handler:
+	en_dev->ops->vp_modern_unmap_vq_notify(en_dev->parent,
+										   (void __iomem __force *)vq->priv);
+err_map_notify:
+	vring_del_virtqueue(vq);
+out_info:
+	kfree(info);
+	en_dev->vqs[index] = NULL;
+	return ERR_PTR(err);
+}
+
+uint32_t get_mergeable_buf_len(struct receive_queue *rq,
+							   struct ewma_pkt_len *avg_pkt_len, uint32_t room)
+{
+	const size_t hdr_len = sizeof(struct zxdh_net_hdr);
+	uint32_t len = 0;
+
+	if (room) {
+		return PAGE_SIZE - room;
+	}
+
+	len = hdr_len + clamp_t(uint32_t, ewma_pkt_len_read(avg_pkt_len),
+							rq->min_buf_len, PAGE_SIZE - hdr_len);
+
+	return ALIGN(len, L1_CACHE_BYTES);
+}
+
+/*
+ * The DMA ops on various arches are rather gnarly right now, and
+ * making all of the arch DMA ops work on the vring device itself
+ * is a mess.  For now, we use the parent device for DMA ops.
+ */
+static inline struct device *vring_dma_dev(const struct vring_virtqueue *vq)
+{
+	return vq->vq.vdev->dev.parent; // todo
+}
+
+/* Map one sg entry. */
+dma_addr_t vring_map_one_sg(const struct vring_virtqueue *vq,
+							struct scatterlist *sg,
+							enum dma_data_direction direction)
+{
+	if (!vq->use_dma_api) {
+		return (dma_addr_t)sg_phys(sg);
+	}
+
+	/*
+   * We can't use dma_map_sg, because we don't use scatterlists in
+   * the way it expects (we don't guarantee that the scatterlist
+   * will exist for the lifetime of the mapping).
+   */
+	return dma_map_page(vring_dma_dev(vq), sg_page(sg), sg->offset, sg->length,
+						direction);
+}
+
+dma_addr_t vring_map_single(const struct vring_virtqueue *vq, void *cpu_addr,
+							size_t size, enum dma_data_direction direction)
+{
+	if (!vq->use_dma_api) {
+		return (dma_addr_t)virt_to_phys(cpu_addr);
+	}
+
+	return dma_map_single(vring_dma_dev(vq), cpu_addr, size, direction);
+}
+
+int32_t vring_mapping_error(const struct vring_virtqueue *vq, dma_addr_t addr)
+{
+	if (!vq->use_dma_api) {
+		return 0;
+	}
+
+	return dma_mapping_error(vring_dma_dev(vq), addr);
+}
+
+/*
+ * Packed ring specific functions - *_packed().
+ */
+void vring_unmap_state_packed(const struct vring_virtqueue *vq,
+							  struct vring_desc_extra *state)
+{
+	uint16_t flags = 0;
+
+	if (!vq->use_dma_api) {
+		return;
+	}
+
+	flags = state->flags;
+	if (flags & VRING_DESC_F_INDIRECT) {
+		dma_unmap_single(vring_dma_dev(vq), state->addr, state->len,
+						 (flags & VRING_DESC_F_WRITE) ? DMA_FROM_DEVICE :
+														  DMA_TO_DEVICE);
+	} else {
+		dma_unmap_page(vring_dma_dev(vq), state->addr, state->len,
+					   (flags & VRING_DESC_F_WRITE) ? DMA_FROM_DEVICE :
+														DMA_TO_DEVICE);
+	}
+}
+
+void vring_unmap_desc_packed(const struct vring_virtqueue *vq,
+							 struct vring_packed_desc *desc)
+{
+	uint16_t flags = 0;
+
+	if (!vq->use_dma_api) {
+		return;
+	}
+
+	flags = le16_to_cpu(desc->flags);
+
+	if (flags & VRING_DESC_F_INDIRECT) {
+		dma_unmap_single(vring_dma_dev(vq), le64_to_cpu(desc->addr),
+						 le32_to_cpu(desc->len),
+						 (flags & VRING_DESC_F_WRITE) ? DMA_FROM_DEVICE :
+														  DMA_TO_DEVICE);
+	} else {
+		dma_unmap_page(vring_dma_dev(vq), le64_to_cpu(desc->addr),
+					   le32_to_cpu(desc->len),
+					   (flags & VRING_DESC_F_WRITE) ? DMA_FROM_DEVICE :
+														DMA_TO_DEVICE);
+	}
+}
+
+void *mergeable_len_to_ctx(uint32_t truesize, uint32_t headroom)
+{
+	return (void *)(unsigned long)((headroom << MRG_CTX_HEADER_SHIFT) |
+								   truesize);
+}
+
+inline bool virtqueue_use_indirect(struct virtqueue *_vq, unsigned int total_sg)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+
+	/*
+   * If the host supports indirect descriptor tables, and we have multiple
+   * buffers, then go indirect. FIXME: tune this threshold
+   */
+	return (vq->indirect && total_sg > 1 && vq->vq.num_free);
+}
+
+struct vring_packed_desc *alloc_indirect_packed(unsigned int total_sg,
+												gfp_t gfp)
+{
+	struct vring_packed_desc *desc = NULL;
+
+	/*
+   * We require lowmem mappings for the descriptors because
+   * otherwise virt_to_phys will give us bogus addresses in the
+   * virtqueue.
+   */
+	gfp &= ~__GFP_HIGHMEM;
+
+	desc = kmalloc_array(total_sg, sizeof(struct vring_packed_desc), gfp);
+
+	return desc;
+}
+
+int virtqueue_add_indirect_packed(struct vring_virtqueue *vq,
+								  struct scatterlist *sgs[],
+								  unsigned int total_sg, unsigned int out_sgs,
+								  unsigned int in_sgs, void *data, gfp_t gfp)
+{
+	struct vring_packed_desc *desc = NULL;
+	struct scatterlist *sg = NULL;
+	uint32_t i = 0;
+	uint32_t n = 0;
+	uint32_t err_idx = 0;
+	uint16_t head = 0;
+	uint16_t id = 0;
+	dma_addr_t addr;
+
+	head = vq->packed.next_avail_idx;
+	desc = alloc_indirect_packed(total_sg, gfp);
+	if (desc == NULL) {
+		return -ENOMEM;
+	}
+
+	if (unlikely(vq->vq.num_free < 1)) {
+		LOG_DEBUG("can't add buf len 1 - avail = 0\n");
+		kfree(desc);
+		END_USE(vq);
+		return -ENOSPC;
+	}
+
+	i = 0;
+	id = vq->free_head;
+	BUG_ON(id == vq->packed.vring.num);
+
+	for (n = 0; n < out_sgs + in_sgs; n++) {
+		for (sg = sgs[n]; sg; sg = sg_next(sg)) {
+			addr = vring_map_one_sg(
+					vq, sg, n < out_sgs ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+			if (vring_mapping_error(vq, addr)) {
+				goto unmap_release;
+			}
+
+			desc[i].flags = cpu_to_le16(n < out_sgs ? 0 : VRING_DESC_F_WRITE);
+			desc[i].addr = cpu_to_le64(addr);
+			desc[i].len = cpu_to_le32(sg->length);
+			i++;
+		}
+	}
+
+	/* Now that the indirect table is filled in, map it. */
+	addr = vring_map_single(vq, desc,
+							total_sg * sizeof(struct vring_packed_desc),
+							DMA_TO_DEVICE);
+	if (vring_mapping_error(vq, addr)) {
+		goto unmap_release;
+	}
+
+	vq->packed.vring.desc[head].addr = cpu_to_le64(addr);
+	vq->packed.vring.desc[head].len =
+			cpu_to_le32(total_sg * sizeof(struct vring_packed_desc));
+	vq->packed.vring.desc[head].id = cpu_to_le16(id);
+
+	if (vq->use_dma_api) {
+		vq->packed.desc_extra[id].addr = addr;
+		vq->packed.desc_extra[id].len =
+				total_sg * sizeof(struct vring_packed_desc);
+		vq->packed.desc_extra[id].flags = VRING_DESC_F_INDIRECT |
+										  vq->packed.avail_used_flags;
+	}
+
+	/*
+   * A driver MUST NOT make the first descriptor in the list
+   * available before all subsequent descriptors comprising
+   * the list are made available.
+   */
+	vqm_wmb(vq->weak_barriers);
+	vq->packed.vring.desc[head].flags =
+			cpu_to_le16(VRING_DESC_F_INDIRECT | vq->packed.avail_used_flags);
+
+	/* We're using some buffers from the free list. */
+	vq->vq.num_free -= 1;
+
+	/* Update free pointer */
+	n = head + 1;
+	if (n >= vq->packed.vring.num) {
+		n = 0;
+		vq->packed.avail_wrap_counter ^= 1;
+		vq->packed.avail_used_flags ^= 1 << VRING_PACKED_DESC_F_AVAIL |
+									   1 << VRING_PACKED_DESC_F_USED;
+	}
+	vq->packed.next_avail_idx = n;
+	vq->free_head = vq->packed.desc_extra[id].next;
+
+	/* Store token and indirect buffer state. */
+	vq->packed.desc_state[id].num = 1;
+	vq->packed.desc_state[id].data = data;
+	vq->packed.desc_state[id].indir_desc = desc;
+	vq->packed.desc_state[id].last = id;
+
+	vq->num_added += 1;
+
+	LOG_DEBUG("added buffer head %i to %p\n", head, vq);
+	END_USE(vq);
+
+	return 0;
+
+unmap_release:
+	err_idx = i;
+
+	for (i = 0; i < err_idx; i++) {
+		vring_unmap_desc_packed(vq, &desc[i]);
+	}
+
+	kfree(desc);
+
+	END_USE(vq);
+	return -ENOMEM;
+}
+
+int32_t virtqueue_add_packed(struct virtqueue *_vq, struct scatterlist *sgs[],
+							 uint32_t total_sg, uint32_t out_sgs,
+							 uint32_t in_sgs, void *data, void *ctx, gfp_t gfp)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+	struct vring_packed_desc *desc = NULL;
+	struct scatterlist *sg = NULL;
+	uint32_t i = 0;
+	uint32_t n = 0;
+	uint32_t c = 0;
+	uint32_t descs_used = 0;
+	uint32_t err_idx = 0;
+	__le16 head_flags = 0;
+	__le16 flags = 0;
+	uint16_t head = 0;
+	uint16_t id = 0;
+	uint16_t prev = 0;
+	uint16_t curr = 0;
+	uint16_t avail_used_flags = 0;
+	int32_t err = 0;
+
+	START_USE(vq);
+
+	BUG_ON(data == NULL);
+	BUG_ON(ctx && vq->indirect);
+
+	if (unlikely(vq->broken)) {
+		END_USE(vq);
+		return -EIO;
+	}
+
+	LAST_ADD_TIME_UPDATE(vq);
+
+	BUG_ON(total_sg == 0);
+
+	if (virtqueue_use_indirect(_vq, total_sg)) {
+		err = virtqueue_add_indirect_packed(vq, sgs, total_sg, out_sgs, in_sgs,
+											data, gfp);
+		if (err != -ENOMEM) {
+			END_USE(vq);
+			return err;
+		}
+		/* fall back on direct */
+	}
+
+	head = vq->packed.next_avail_idx;
+	avail_used_flags = vq->packed.avail_used_flags;
+
+	WARN_ON_ONCE(total_sg > vq->packed.vring.num && !vq->indirect);
+
+	desc = vq->packed.vring.desc;
+	i = head;
+	descs_used = total_sg;
+
+	if (unlikely(vq->vq.num_free < descs_used)) {
+		LOG_ERR("can't add buf len %i - avail = %i\n", descs_used,
+				vq->vq.num_free);
+		END_USE(vq);
+		return -ENOSPC;
+	}
+
+	id = vq->free_head;
+	BUG_ON(id == vq->packed.vring.num);
+
+	curr = id;
+	c = 0;
+	for (n = 0; n < out_sgs + in_sgs; n++) {
+		for (sg = sgs[n]; sg; sg = sg_next(sg)) {
+			dma_addr_t addr = vring_map_one_sg(
+					vq, sg, n < out_sgs ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+			if (vring_mapping_error(vq, addr)) {
+				goto unmap_release;
+			}
+
+			flags = cpu_to_le16(vq->packed.avail_used_flags |
+								(++c == total_sg ? 0 : VRING_DESC_F_NEXT) |
+								(n < out_sgs ? 0 : VRING_DESC_F_WRITE));
+
+			desc[i].addr = cpu_to_le64(addr);
+			desc[i].len = cpu_to_le32(sg->length);
+			desc[i].id = cpu_to_le16(id);
+
+			if (i == head) {
+				head_flags = flags;
+			} else {
+				desc[i].flags = flags;
+			}
+
+			if (unlikely(vq->use_dma_api)) {
+				vq->packed.desc_extra[curr].addr = addr;
+				vq->packed.desc_extra[curr].len = sg->length;
+				vq->packed.desc_extra[curr].flags = le16_to_cpu(flags);
+			}
+			prev = curr;
+			curr = vq->packed.desc_extra[curr].next;
+
+			if ((unlikely(++i >= vq->packed.vring.num))) {
+				i = 0;
+				vq->packed.avail_used_flags ^= 1 << VRING_PACKED_DESC_F_AVAIL |
+											   1 << VRING_PACKED_DESC_F_USED;
+			}
+		}
+	}
+
+	if (i < head) {
+		vq->packed.avail_wrap_counter ^= 1;
+	}
+
+	/* We're using some buffers from the free list. */
+	vq->vq.num_free -= descs_used;
+
+	/* Update free pointer */
+	vq->packed.next_avail_idx = i;
+	vq->free_head = curr;
+
+	/* Store token. */
+	vq->packed.desc_state[id].num = descs_used;
+	vq->packed.desc_state[id].data = data;
+	vq->packed.desc_state[id].indir_desc = ctx;
+	vq->packed.desc_state[id].last = prev;
+
+	/*
+   * A driver MUST NOT make the first descriptor in the list
+   * available before all subsequent descriptors comprising
+   * the list are made available.
+   */
+	vqm_wmb(vq->weak_barriers);
+	vq->packed.vring.desc[head].flags = head_flags;
+	vq->num_added += descs_used;
+
+	// LOG_INFO("added buffer head %i to %p\n", head, vq);
+	END_USE(vq);
+
+	return 0;
+
+unmap_release:
+	err_idx = i;
+	i = head;
+	curr = vq->free_head;
+
+	vq->packed.avail_used_flags = avail_used_flags;
+
+	for (n = 0; n < total_sg; n++) {
+		if (i == err_idx) {
+			break;
+		}
+
+		vring_unmap_state_packed(vq, &vq->packed.desc_extra[curr]);
+		curr = vq->packed.desc_extra[curr].next;
+		i++;
+		if (i >= vq->packed.vring.num) {
+			i = 0;
+		}
+	}
+
+	END_USE(vq);
+	return -EIO;
+}
+
+/**
+ * virtqueue_add_inbuf_ctx - expose input buffers to other end
+ * @vq: the struct virtqueue we're talking about.
+ * @sg: scatterlist (must be well-formed and terminated!)
+ * @num: the number of entries in @sg writable by other side
+ * @data: the token identifying the buffer.
+ * @ctx: extra context for the token
+ * @gfp: how to do memory allocations (if necessary).
+ *
+ * Caller must ensure we don't call this with other virtqueue operations
+ * at the same time (except where noted).
+ *
+ * Returns zero or a negative error (ie. ENOSPC, ENOMEM, EIO).
+ */
+int32_t virtqueue_add_inbuf_ctx(struct virtqueue *vq, struct scatterlist *sg,
+								uint32_t num, void *data, void *ctx, gfp_t gfp)
+{
+	return virtqueue_add_packed(vq, &sg, num, 0, 1, data, ctx, gfp);
+}
+
+bool is_used_desc_packed(struct vring_virtqueue *vq, uint16_t idx,
+						 bool used_wrap_counter)
+{
+	bool avail = false;
+	bool used = false;
+	uint16_t flags = 0;
+
+	flags = le16_to_cpu(vq->packed.vring.desc[idx].flags);
+	avail = !!(flags & (1 << VRING_PACKED_DESC_F_AVAIL));
+	used = !!(flags & (1 << VRING_PACKED_DESC_F_USED));
+
+	return avail == used && used == used_wrap_counter;
+}
+
+bool virtqueue_poll_packed(struct virtqueue *_vq, uint16_t off_wrap)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+	bool wrap_counter = false;
+	uint16_t used_idx = 0;
+
+	wrap_counter = off_wrap >> VRING_PACKED_EVENT_F_WRAP_CTR;
+	used_idx = off_wrap & ~(1 << VRING_PACKED_EVENT_F_WRAP_CTR);
+
+	return is_used_desc_packed(vq, used_idx, wrap_counter);
+}
+
+/**
+ * virtqueue_poll - query pending used buffers
+ * @_vq: the struct virtqueue we're talking about.
+ * @last_used_idx: virtqueue state (from call to virtqueue_enable_cb_prepare).
+ *
+ * Returns "true" if there are pending used buffers in the queue.
+ *
+ * This does not need to be serialized.
+ */
+bool virtqueue_poll(struct virtqueue *_vq, unsigned last_used_idx)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+
+	if (unlikely(vq->broken)) {
+		return false;
+	}
+
+	vqm_mb(vq->weak_barriers);
+	return virtqueue_poll_packed(_vq, last_used_idx);
+}
+
+unsigned virtqueue_enable_cb_prepare_packed(struct virtqueue *_vq)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+
+	START_USE(vq);
+
+	/*
+   * We optimistically turn back on interrupts, then check if there was
+   * more to do.
+   */
+	if (vq->event) {
+		vq->packed.vring.driver->off_wrap = cpu_to_le16(
+				vq->last_used_idx | (vq->packed.used_wrap_counter
+									 << VRING_PACKED_EVENT_F_WRAP_CTR));
+		/*
+     * We need to update event offset and event wrap
+     * counter first before updating event flags.
+     */
+		vqm_wmb(vq->weak_barriers);
+	}
+
+	if (vq->packed.event_flags_shadow == VRING_PACKED_EVENT_FLAG_DISABLE) {
+		vq->packed.event_flags_shadow = vq->event ?
+												  VRING_PACKED_EVENT_FLAG_DESC :
+												  VRING_PACKED_EVENT_FLAG_ENABLE;
+		vq->packed.vring.driver->flags =
+				cpu_to_le16(vq->packed.event_flags_shadow);
+	}
+
+	END_USE(vq);
+	return vq->last_used_idx | ((uint16_t)vq->packed.used_wrap_counter
+								<< VRING_PACKED_EVENT_F_WRAP_CTR);
+}
+
+int32_t virtqueue_enable_cb_prepare(struct virtqueue *_vq)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+
+	if (vq->event_triggered) {
+		vq->event_triggered = false;
+	}
+
+	return virtqueue_enable_cb_prepare_packed(_vq);
+}
+
+bool more_used_packed(struct vring_virtqueue *vq)
+{
+	return is_used_desc_packed(vq, vq->last_used_idx,
+							   vq->packed.used_wrap_counter);
+}
+
+void detach_buf_packed(struct vring_virtqueue *vq, uint32_t id, void **ctx)
+{
+	struct vring_desc_state_packed *state = NULL;
+	struct vring_packed_desc *desc = NULL;
+	uint32_t i = 0;
+	uint32_t curr = 0;
+
+	state = &vq->packed.desc_state[id];
+
+	/* Clear data ptr. */
+	state->data = NULL;
+
+	vq->packed.desc_extra[state->last].next = vq->free_head;
+	vq->free_head = id;
+	vq->vq.num_free += state->num;
+
+	if (unlikely(vq->use_dma_api)) {
+		curr = id;
+		for (i = 0; i < state->num; i++) {
+			vring_unmap_state_packed(vq, &vq->packed.desc_extra[curr]);
+			curr = vq->packed.desc_extra[curr].next;
+		}
+	}
+
+	if (vq->indirect) {
+		uint32_t len;
+
+		/* Free the indirect table, if any, now that it's unmapped. */
+		desc = state->indir_desc;
+		if (!desc) {
+			return;
+		}
+
+		if (vq->use_dma_api) {
+			len = vq->packed.desc_extra[id].len;
+			for (i = 0; i < len / sizeof(struct vring_packed_desc); i++) {
+				vring_unmap_desc_packed(vq, &desc[i]);
+			}
+		}
+		kfree(desc);
+		state->indir_desc = NULL;
+	} else if (ctx) {
+		*ctx = state->indir_desc;
+	}
+}
+
+void *virtqueue_get_buf_ctx_packed(struct virtqueue *_vq, uint32_t *len,
+								   void **ctx)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+	uint16_t last_used = 0;
+	uint16_t id = 0;
+	void *ret = NULL;
+
+	START_USE(vq);
+
+	if (unlikely(vq->broken)) {
+		END_USE(vq);
+		return NULL;
+	}
+
+	if (!more_used_packed(vq)) {
+		// LOG_ERR("no more buffers in queue\n");
+		END_USE(vq);
+		return NULL;
+	}
+
+	/* Only get used elements after they have been exposed by host. */
+	vqm_rmb(vq->weak_barriers);
+
+	last_used = vq->last_used_idx;
+	id = le16_to_cpu(vq->packed.vring.desc[last_used].id);
+	*len = le32_to_cpu(vq->packed.vring.desc[last_used].len);
+
+	if (unlikely(id >= vq->packed.vring.num)) {
+		zxdh_print_vring_info(_vq, 0, vq->packed.vring.num);
+		BAD_RING(vq, "id %u out of range\n", id);
+		return NULL;
+	}
+	if (unlikely(!vq->packed.desc_state[id].data)) {
+		zxdh_print_vring_info(_vq, 0, vq->packed.vring.num);
+		BAD_RING(vq, "id %u is not a head!\n", id);
+		return NULL;
+	}
+
+	/* detach_buf_packed clears data, so grab it now. */
+	ret = vq->packed.desc_state[id].data;
+	detach_buf_packed(vq, id, ctx);
+
+	vq->last_used_idx += vq->packed.desc_state[id].num;
+	if (unlikely(vq->last_used_idx >= vq->packed.vring.num)) {
+		vq->last_used_idx -= vq->packed.vring.num;
+		vq->packed.used_wrap_counter ^= 1;
+	}
+
+	/*
+   * If we expect an interrupt for the next entry, tell host
+   * by writing event index and flush out the write before
+   * the read in the next get_buf call.
+   */
+	if (vq->packed.event_flags_shadow == VRING_PACKED_EVENT_FLAG_DESC)
+		vqm_store_mb(vq->weak_barriers, &vq->packed.vring.driver->off_wrap,
+					 cpu_to_le16(vq->last_used_idx |
+								 (vq->packed.used_wrap_counter
+								  << VRING_PACKED_EVENT_F_WRAP_CTR)));
+
+	LAST_ADD_TIME_INVALID(vq);
+
+	END_USE(vq);
+	return ret;
+}
+
+void *virtqueue_get_buf(struct virtqueue *_vq, uint32_t *len)
+{
+	return virtqueue_get_buf_ctx_packed(_vq, len, NULL);
+}
+
+/*
+ * private is used to chain pages for big packets, put the whole
+ * most recent used list in the beginning for reuse
+ */
+void give_pages(struct receive_queue *rq, struct page *page)
+{
+	struct page *end = NULL;
+
+	/* Find end of list, sew whole thing into vi->rq.pages. */
+	for (end = page; end->private; end = (struct page *)end->private)
+		;
+	end->private = (unsigned long)rq->pages;
+	rq->pages = page;
+}
+
+void free_old_xmit_skbs(struct net_device *netdev, struct send_queue *sq,
+						bool in_napi)
+{
+	uint32_t len = 0;
+	uint32_t packets = 0;
+	uint32_t bytes = 0;
+	void *ptr = NULL;
+
+	while ((ptr = virtqueue_get_buf(sq->vq, &len)) != NULL) {
+		struct sk_buff *skb = ptr;
+
+		// LOG_DEBUG("sent skb %p\n", skb);
+
+		bytes += skb->len;
+		napi_consume_skb(skb, in_napi);
+		packets++;
+	}
+
+	/* Avoid overhead when no packets have been processed
+   * happens when called speculatively from start_xmit.
+   */
+	if (!packets) {
+		return;
+	}
+
+	u64_stats_update_begin(&sq->stats.syncp);
+	sq->stats.bytes += bytes;
+	sq->stats.packets += packets;
+	netdev->stats.tx_bytes += bytes;
+	netdev->stats.tx_packets += packets;
+	u64_stats_update_end(&sq->stats.syncp);
+}
+
+void virtqueue_disable_cb_packed(struct virtqueue *_vq)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+
+	if (vq->packed.event_flags_shadow != VRING_PACKED_EVENT_FLAG_DISABLE) {
+		vq->packed.event_flags_shadow = VRING_PACKED_EVENT_FLAG_DISABLE;
+		vq->packed.vring.driver->flags =
+				cpu_to_le16(vq->packed.event_flags_shadow);
+	}
+}
+
+/**
+ * virtqueue_disable_cb - disable callbacks
+ * @_vq: the struct virtqueue we're talking about.
+ *
+ * Note that this is not necessarily synchronous, hence unreliable and only
+ * useful as an optimization.
+ *
+ * Unlike other operations, this need not be serialized.
+ */
+void virtqueue_disable_cb(struct virtqueue *_vq)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+
+	/* If device triggered an event already it won't trigger one again:
+   * no need to disable.
+   */
+	if (vq->event_triggered) {
+		return;
+	}
+
+	virtqueue_disable_cb_packed(_vq);
+}
+
+void virtqueue_napi_schedule(struct napi_struct *napi, struct virtqueue *vq)
+{
+	if (napi_schedule_prep(napi)) {
+		virtqueue_disable_cb(vq);
+		__napi_schedule(napi);
+	}
+}
+
+void virtnet_napi_enable(struct virtqueue *vq, struct napi_struct *napi)
+{
+	napi_enable(napi);
+
+	/* If all buffers were filled by other side before we napi_enabled, we
+   * won't get another interrupt, so process any outstanding packets now.
+   * Call local_bh_enable after to trigger softIRQ processing.
+   */
+	local_bh_disable();
+	virtqueue_napi_schedule(napi, vq);
+	local_bh_enable();
+}
+
+void virtnet_napi_tx_enable(struct net_device *netdev, struct virtqueue *vq,
+							struct napi_struct *napi)
+{
+	if (!napi->weight) {
+		return;
+	}
+
+	virtnet_napi_enable(vq, napi);
+
+	return;
+}
+
+void virtnet_napi_tx_disable(struct napi_struct *napi)
+{
+	if (napi->weight) {
+		napi_disable(napi);
+	}
+}
+
+int virtnet_poll_tx(struct napi_struct *napi, int budget)
+{
+	struct send_queue *sq = container_of(napi, struct send_queue, napi);
+	struct zxdh_en_priv *en_priv = netdev_priv(sq->vq->vdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t index = vq2txq(sq->vq);
+	struct netdev_queue *txq = NULL;
+	int32_t opaque = 0;
+	bool done = false;
+
+	txq = netdev_get_tx_queue(en_dev->netdev, index);
+	__netif_tx_lock(txq, raw_smp_processor_id());
+	virtqueue_disable_cb(sq->vq);
+	free_old_xmit_skbs(en_dev->netdev, sq, true);
+
+	if (sq->vq->num_free >= 2 + MAX_SKB_FRAGS) {
+		netif_tx_wake_queue(txq);
+	}
+
+	opaque = virtqueue_enable_cb_prepare(sq->vq);
+
+	done = napi_complete_done(napi, 0);
+
+	if (!done) {
+		virtqueue_disable_cb(sq->vq);
+	}
+
+	__netif_tx_unlock(txq);
+
+	if (done) {
+		if (unlikely(virtqueue_poll(sq->vq, opaque))) {
+			if (napi_schedule_prep(napi)) {
+				__netif_tx_lock(txq, raw_smp_processor_id());
+				virtqueue_disable_cb(sq->vq);
+				__netif_tx_unlock(txq);
+				__napi_schedule(napi);
+			}
+		}
+	}
+
+	return 0;
+}
+
+bool virtqueue_enable_cb_delayed_packed(struct virtqueue *_vq)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+	uint16_t used_idx = 0;
+	uint16_t wrap_counter = 0;
+	uint16_t bufs = 0;
+
+	START_USE(vq);
+
+	/*
+   * We optimistically turn back on interrupts, then check if there was
+   * more to do.
+   */
+
+	if (vq->event) {
+		/* TODO: tune this threshold */
+		bufs = (vq->packed.vring.num - vq->vq.num_free) * 3 / 4;
+		wrap_counter = vq->packed.used_wrap_counter;
+
+		used_idx = vq->last_used_idx + bufs;
+		if (used_idx >= vq->packed.vring.num) {
+			used_idx -= vq->packed.vring.num;
+			wrap_counter ^= 1;
+		}
+
+		vq->packed.vring.driver->off_wrap = cpu_to_le16(
+				used_idx | (wrap_counter << VRING_PACKED_EVENT_F_WRAP_CTR));
+
+		/*
+     * We need to update event offset and event wrap
+     * counter first before updating event flags.
+     */
+		vqm_wmb(vq->weak_barriers);
+	}
+
+	if (vq->packed.event_flags_shadow == VRING_PACKED_EVENT_FLAG_DISABLE) {
+		vq->packed.event_flags_shadow = vq->event ?
+												  VRING_PACKED_EVENT_FLAG_DESC :
+												  VRING_PACKED_EVENT_FLAG_ENABLE;
+		vq->packed.vring.driver->flags =
+				cpu_to_le16(vq->packed.event_flags_shadow);
+	}
+
+	/*
+   * We need to update event suppression structure first
+   * before re-checking for more used buffers.
+   */
+	vqm_mb(vq->weak_barriers);
+
+	if (is_used_desc_packed(vq, vq->last_used_idx,
+							vq->packed.used_wrap_counter)) {
+		END_USE(vq);
+		return false;
+	}
+
+	END_USE(vq);
+	return true;
+}
+uint16_t __vqm16_to_cpu(bool little_endian, __vqm16 val)
+{
+	if (little_endian) {
+		return le16_to_cpu((__force __le16)val);
+	} else {
+		return be16_to_cpu((__force __be16)val);
+	}
+}
+
+static inline bool zxdh_legacy_is_little_endian(void)
+{
+#ifdef __LITTLE_ENDIAN
+	return true;
+#else
+	return false;
+#endif
+}
+
+bool zxdh_is_little_endian(struct net_device *dev)
+{
+	return zxdh_has_feature(dev, ZXDH_F_VERSION_1) ||
+		   zxdh_legacy_is_little_endian();
+}
+
+/* Memory accessors */
+uint16_t vqm16_to_cpu(struct net_device *netdev, __vqm16 val)
+{
+	return __vqm16_to_cpu(zxdh_is_little_endian(netdev), val);
+}
+
+uint32_t mergeable_ctx_to_headroom(void *mrg_ctx)
+{
+	return (unsigned long)mrg_ctx >> MRG_CTX_HEADER_SHIFT;
+}
+
+uint32_t mergeable_ctx_to_truesize(void *mrg_ctx)
+{
+	return (unsigned long)mrg_ctx & ((1 << MRG_CTX_HEADER_SHIFT) - 1);
+}
+
+/**
+ * virtqueue_enable_cb_delayed - restart callbacks after disable_cb.
+ * @_vq: the struct virtqueue we're talking about.
+ *
+ * This re-enables callbacks but hints to the other side to delay
+ * interrupts until most of the available buffers have been processed;
+ * it returns "false" if there are many pending buffers in the queue,
+ * to detect a possible race between the driver checking for more work,
+ * and enabling callbacks.
+ *
+ * Caller must ensure we don't call this with other virtqueue
+ * operations at the same time (except where noted).
+ */
+bool virtqueue_enable_cb_delayed(struct virtqueue *_vq)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+
+	if (vq->event_triggered) {
+		vq->event_triggered = false;
+	}
+
+	return virtqueue_enable_cb_delayed_packed(_vq);
+}
+
+void virtnet_poll_cleantx(struct receive_queue *rq)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(rq->vq->vdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t index = vq2rxq(rq->vq);
+	struct send_queue *sq = &en_dev->sq[index];
+	struct netdev_queue *txq = netdev_get_tx_queue(en_dev->netdev, index);
+
+	if (!sq->napi.weight) {
+		return;
+	}
+
+	if (__netif_tx_trylock(txq)) {
+		do {
+			virtqueue_disable_cb(sq->vq);
+			free_old_xmit_skbs(en_dev->netdev, sq, true);
+		} while (unlikely(!virtqueue_enable_cb_delayed(sq->vq)));
+
+		if (sq->vq->num_free >= 2 + MAX_SKB_FRAGS) {
+			netif_tx_wake_queue(txq);
+		}
+
+		__netif_tx_unlock(txq);
+	}
+}
+
+inline struct zxdh_net_hdr *skb_vnet_hdr(struct sk_buff *skb)
+{
+	return (struct zxdh_net_hdr *)skb->cb;
+}
+
+/* Called from bottom half context */
+struct sk_buff *page_to_skb(struct zxdh_en_device *en_dev,
+							struct receive_queue *rq, struct page *page,
+							uint32_t offset, uint32_t len, uint32_t truesize,
+							uint32_t metasize, uint32_t headroom)
+{
+	struct sk_buff *skb = NULL;
+	struct zxdh_net_hdr *hdr = NULL;
+	uint32_t copy = 0;
+	uint32_t hdr_len = 0;
+	struct page *page_to_free = NULL;
+	int32_t tailroom = 0;
+	int32_t shinfo_size = 0;
+	char *p = NULL;
+	char *hdr_p = NULL;
+	char *buf = NULL;
+	uint32_t hdr_len_tmp = 0;
+
+	p = page_address(page) + offset;
+	hdr_p = p;
+
+	hdr_len = (((struct zxdh_net_hdr *)hdr_p)->pd_len) * HDR_2B_UNIT;
+
+	/* If headroom is not 0, there is an offset between the beginning of the
+   * data and the allocated space, otherwise the data and the allocated
+   * space are aligned.
+   *
+   * Buffers with headroom use PAGE_SIZE as alloc size, see
+   * add_recvbuf_mergeable() + get_mergeable_buf_len()
+   */
+	truesize = headroom ? PAGE_SIZE : truesize;
+	tailroom = truesize - headroom;
+	buf = p - headroom;
+
+	len -= hdr_len;
+	offset += hdr_len;
+	p += hdr_len;
+	tailroom -= hdr_len + len;
+
+	shinfo_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
+
+	/* copy small packet so we can reuse these pages */
+	if (!NET_IP_ALIGN && len > GOOD_COPY_LEN && tailroom >= shinfo_size) {
+		skb = build_skb(buf, truesize);
+		if (unlikely(!skb)) {
+			return NULL;
+		}
+
+		skb_reserve(skb, p - buf);
+		skb_put(skb, len);
+
+		page = (struct page *)page->private;
+		if (page) {
+			give_pages(rq, page);
+		}
+		goto ok;
+	}
+
+	/* copy small packet so we can reuse these pages for small data */
+	skb = napi_alloc_skb(&rq->napi, GOOD_COPY_LEN);
+	if (unlikely(!skb)) {
+		return NULL;
+	}
+
+	/* Copy all frame if it fits skb->head */
+	if (len <= skb_tailroom(skb)) {
+		copy = len;
+	} else {
+		copy = ETH_HLEN + metasize;
+	}
+	skb_put_data(skb, p, copy);
+
+	len -= copy;
+	offset += copy;
+
+	if (len) {
+		skb_add_rx_frag(skb, 0, page, offset, len, truesize);
+	} else {
+		page_to_free = page;
+	}
+
+ok:
+	hdr = skb_vnet_hdr(skb);
+	hdr_len_tmp = hdr_len > 48 ? 48 : hdr_len; // todo
+	memcpy(hdr, hdr_p, hdr_len_tmp);
+	// memcpy(hdr, hdr_p, hdr_len);
+
+	if (page_to_free) {
+		put_page(page_to_free);
+	}
+
+	if (metasize) {
+		__skb_pull(skb, metasize);
+		skb_metadata_set(skb, metasize);
+	}
+
+	return skb;
+}
+/**
+ * virtqueue_add_outbuf - expose output buffers to other end
+ * @vq: the struct virtqueue we're talking about.
+ * @sg: scatterlist (must be well-formed and terminated!)
+ * @num: the number of entries in @sg readable by other side
+ * @data: the token identifying the buffer.
+ * @gfp: how to do memory allocations (if necessary).
+ *
+ * Caller must ensure we don't call this with other virtqueue operations
+ * at the same time (except where noted).
+ *
+ * Returns zero or a negative error (ie. ENOSPC, ENOMEM, EIO).
+ */
+int32_t virtqueue_add_outbuf(struct virtqueue *vq, struct scatterlist *sg,
+							 uint32_t num, void *data, gfp_t gfp)
+{
+	return virtqueue_add_packed(vq, &sg, num, 1, 0, data, NULL, gfp);
+}
+
+struct sk_buff *receive_mergeable(struct net_device *netdev,
+								  struct zxdh_en_device *en_dev,
+								  struct receive_queue *rq, void *buf,
+								  void *ctx, uint32_t len,
+								  struct virtnet_rq_stats *stats)
+{
+	struct zxdh_net_hdr *hdr = buf;
+	uint16_t num_buf = vqm16_to_cpu(netdev, hdr->num_buffers);
+	struct page *page = virt_to_head_page(buf);
+	int32_t offset = buf - page_address(page);
+	struct sk_buff *head_skb = NULL;
+	struct sk_buff *curr_skb = NULL;
+	uint32_t truesize = mergeable_ctx_to_truesize(ctx);
+	uint32_t headroom = mergeable_ctx_to_headroom(ctx);
+	uint32_t metasize = 0;
+
+	stats->bytes += (len - (hdr->pd_len * HDR_2B_UNIT));
+	netdev->stats.rx_bytes += (len - (hdr->pd_len * HDR_2B_UNIT));
+
+	if (unlikely(len > truesize)) {
+		LOG_ERR("%s: rx error: len %u exceeds truesize %lu\n", netdev->name,
+				len, (unsigned long)ctx);
+		netdev->stats.rx_length_errors++;
+		netdev->stats.rx_errors++;
+		goto err_skb;
+	}
+
+	head_skb = page_to_skb(en_dev, rq, page, offset, len, truesize, metasize,
+						   headroom);
+	curr_skb = head_skb;
+
+	if (unlikely(!curr_skb)) {
+		goto err_skb;
+	}
+	while (--num_buf) {
+		int32_t num_skb_frags;
+
+		buf = virtqueue_get_buf_ctx_packed(rq->vq, &len, &ctx);
+		if (unlikely(!buf)) {
+			LOG_ERR("%s: rx error: %d buffers out of %d missing\n",
+					netdev->name, num_buf,
+					vqm16_to_cpu(netdev, hdr->num_buffers));
+			netdev->stats.rx_length_errors++;
+			netdev->stats.rx_errors++;
+			goto err_buf;
+		}
+
+		stats->bytes += len;
+		netdev->stats.rx_bytes += len;
+		page = virt_to_head_page(buf);
+
+		truesize = mergeable_ctx_to_truesize(ctx);
+		if (unlikely(len > truesize)) {
+			LOG_ERR("%s: rx error: len %u exceeds truesize %lu\n", netdev->name,
+					len, (unsigned long)ctx);
+			netdev->stats.rx_length_errors++;
+			netdev->stats.rx_errors++;
+			goto err_skb;
+		}
+
+		num_skb_frags = skb_shinfo(curr_skb)->nr_frags;
+		if (unlikely(num_skb_frags == MAX_SKB_FRAGS)) {
+			struct sk_buff *nskb = alloc_skb(0, GFP_ATOMIC);
+
+			if (unlikely(!nskb)) {
+				goto err_skb;
+			}
+			if (curr_skb == head_skb) {
+				skb_shinfo(curr_skb)->frag_list = nskb;
+			} else {
+				curr_skb->next = nskb;
+			}
+			curr_skb = nskb;
+			head_skb->truesize += nskb->truesize;
+			num_skb_frags = 0;
+		}
+
+		if (curr_skb != head_skb) {
+			head_skb->data_len += len;
+			head_skb->len += len;
+			head_skb->truesize += truesize;
+		}
+		offset = buf - page_address(page);
+
+		if (skb_can_coalesce(curr_skb, num_skb_frags, page, offset)) {
+			put_page(page);
+			skb_coalesce_rx_frag(curr_skb, num_skb_frags - 1, len, truesize);
+		} else {
+			skb_add_rx_frag(curr_skb, num_skb_frags, page, offset, len,
+							truesize);
+		}
+	}
+
+	ewma_pkt_len_add(&rq->mrg_avg_pkt_len, head_skb->len);
+	return head_skb;
+
+err_skb:
+	put_page(page);
+	while (num_buf-- > 1) {
+		buf = virtqueue_get_buf(rq->vq, &len);
+		if (unlikely(!buf)) {
+			LOG_ERR("%s: rx error: %d buffers missing\n", netdev->name,
+					num_buf);
+			netdev->stats.rx_length_errors++;
+			netdev->stats.rx_errors++;
+			break;
+		}
+		stats->bytes += len;
+		page = virt_to_head_page(buf);
+		put_page(page);
+	}
+err_buf:
+	stats->drops++;
+	netdev->stats.rx_dropped++;
+	dev_kfree_skb(head_skb);
+	return NULL;
+}
+
+void receive_buf(struct zxdh_en_device *en_dev, struct receive_queue *rq,
+				 void *buf, uint32_t len, void **ctx,
+				 struct virtnet_rq_stats *stats)
+{
+	struct net_device *netdev = en_dev->netdev;
+	struct sk_buff *skb = NULL;
+	struct zxdh_net_hdr_rcv *hdr_rcv = (struct zxdh_net_hdr_rcv *)buf;
+
+#ifdef TIME_STAMP_1588
+	int32_t ret = 0;
+#endif
+
+	if (unlikely(len < (hdr_rcv->pd_len * HDR_2B_UNIT) + ETH_HLEN)) {
+		LOG_ERR("%s: short packet %i\n", netdev->name, len);
+		netdev->stats.rx_length_errors++;
+		netdev->stats.rx_errors++;
+
+		put_page(virt_to_head_page(buf));
+		return;
+	}
+
+	skb = receive_mergeable(netdev, en_dev, rq, buf, ctx, len, stats);
+
+	if (unlikely(!skb)) {
+		return;
+	}
+
+	/* rx packet contain the strip label & open rxvlan offloading*/
+	if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
+		hdr_rcv->pd_hdr.flags & (1 << 4)) {
+		u16 vid = htons(hdr_rcv->pd_hdr.striped_ctci) & 0xfff;
+		LOG_DEBUG("recived packtes vlan stripped, vlan-id: %d\n", vid);
+		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
+	}
+
+	if ((netdev->features & NETIF_F_RXCSUM) &&
+		!(hdr_rcv->pi_hdr.error_code[0] & PI_HDR_L4_CHKSUM_ERROR_CODE) &&
+		!(hdr_rcv->pi_hdr.error_code[1] & PI_HDR_L3_CHKSUM_ERROR_CODE) &&
+		!(hdr_rcv->pd_hdr.flags & OUTER_IP_CHKSUM_ERROT_CODE)) {
+		skb->ip_summed = CHECKSUM_UNNECESSARY;
+	} else {
+		skb->ip_summed = CHECKSUM_NONE;
+	}
+
+#ifdef TIME_STAMP_1588
+	ret = pkt_1588_proc_rcv(skb, hdr_rcv, en_dev->clock_no, en_dev);
+	if ((ret != PTP_SUCCESS) && (ret != IS_NOT_PTP_MSG)) {
+		LOG_ERR("pkt_1588_proc_rcv err!!!\n");
+		return;
+	}
+#endif
+
+	skb_record_rx_queue(skb, vq2rxq(rq->vq));
+	skb->protocol = eth_type_trans(skb, netdev);
+
+	// LOG_INFO("receiving skb proto 0x%04x len %i type %i\n",
+	// ntohs(skb->protocol), skb->len, skb->pkt_type);
+
+	napi_gro_receive(&rq->napi, skb);
+	return;
+}
+
+/**
+ * virtqueue_notify - second half of split virtqueue_kick call.
+ * @_vq: the struct virtqueue
+ *
+ * This does not need to be serialized.
+ *
+ * Returns false if host notify failed or queue is broken, otherwise true.
+ */
+bool virtqueue_notify(struct virtqueue *_vq)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+
+	if (unlikely(vq->broken)) {
+		return false;
+	}
+
+	/* Prod other side to tell it about changes. */
+	if (!vq->notify(_vq)) {
+		vq->broken = true;
+		return false;
+	}
+
+	return true;
+}
+
+int32_t add_recvbuf_mergeable(struct zxdh_en_device *en_dev,
+							  struct receive_queue *rq, gfp_t gfp)
+{
+	struct page_frag *alloc_frag = &rq->alloc_frag;
+	uint32_t headroom = 0;
+	uint32_t tailroom = 0;
+	uint32_t room = SKB_DATA_ALIGN(headroom + tailroom);
+	char *buf = NULL;
+	void *ctx = NULL;
+	int32_t err = 0;
+	uint32_t len = 0;
+	uint32_t hole = 0;
+
+	/* Extra tailroom is needed to satisfy XDP's assumption. This
+   * means rx frags coalescing won't work, but consider we've
+   * disabled GSO for XDP, it won't be a big issue.
+   */
+	len = get_mergeable_buf_len(rq, &rq->mrg_avg_pkt_len, room);
+	if (unlikely(!skb_page_frag_refill(len + room, alloc_frag, gfp))) {
+		return -ENOMEM;
+	}
+
+	buf = (char *)page_address(alloc_frag->page) + alloc_frag->offset;
+	buf += headroom; /* advance address leaving hole at front of pkt */
+	get_page(alloc_frag->page);
+	alloc_frag->offset += len + room;
+	hole = alloc_frag->size - alloc_frag->offset;
+	if (hole < len + room) {
+		/* To avoid internal fragmentation, if there is very likely not
+     * enough space for another buffer, add the remaining space to
+     * the current buffer.
+     */
+		len += hole;
+		alloc_frag->offset += hole;
+	}
+
+	sg_init_one(rq->sg, buf, len);
+	ctx = mergeable_len_to_ctx(len, headroom);
+	err = virtqueue_add_inbuf_ctx(rq->vq, rq->sg, 1, buf, ctx, gfp);
+	if (err < 0) {
+		put_page(virt_to_head_page(buf));
+	}
+
+	return err;
+}
+
+/* Assuming a given event_idx value from the other side, if
+ * we have just incremented index from old to new_idx,
+ * should we trigger an event? */
+int32_t vring_need_event(__u16 event_idx, __u16 new_idx, __u16 old)
+{
+	/* Note: Xen has similar logic for notification hold-off
+   * in include/xen/interface/io/ring.h with req_event and req_prod
+   * corresponding to event_idx + 1 and new_idx respectively.
+   * Note also that req_event and req_prod in Xen start at 1,
+   * event indexes in custom queue start at 0. */
+	return (__u16)(new_idx - event_idx - 1) < (__u16)(new_idx - old);
+}
+
+bool virtqueue_kick_prepare_packed(struct virtqueue *_vq)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+	uint16_t new = 0;
+	uint16_t old = 0;
+	uint16_t off_wrap = 0;
+	uint16_t flags = 0;
+	uint16_t wrap_counter = 0;
+	uint16_t event_idx = 0;
+	bool needs_kick = false;
+	union {
+		struct {
+			__le16 off_wrap;
+			__le16 flags;
+		};
+		uint32_t u32;
+	} snapshot;
+
+	START_USE(vq);
+
+	/*
+   * We need to expose the new flags value before checking notification
+   * suppressions.
+   */
+	vqm_mb(vq->weak_barriers);
+
+	old = vq->packed.next_avail_idx - vq->num_added;
+	new = vq->packed.next_avail_idx;
+	vq->num_added = 0;
+
+	snapshot.u32 = *(uint32_t *)vq->packed.vring.device;
+	flags = le16_to_cpu(snapshot.flags);
+
+	LAST_ADD_TIME_CHECK(vq);
+	LAST_ADD_TIME_INVALID(vq);
+
+	if (flags != VRING_PACKED_EVENT_FLAG_DESC) {
+		needs_kick = (flags != VRING_PACKED_EVENT_FLAG_DISABLE);
+		goto out;
+	}
+
+	off_wrap = le16_to_cpu(snapshot.off_wrap);
+
+	wrap_counter = off_wrap >> VRING_PACKED_EVENT_F_WRAP_CTR;
+	event_idx = off_wrap & ~(1 << VRING_PACKED_EVENT_F_WRAP_CTR);
+	if (wrap_counter != vq->packed.avail_wrap_counter) {
+		event_idx -= vq->packed.vring.num;
+	}
+
+	needs_kick = vring_need_event(event_idx, new, old);
+out:
+	END_USE(vq);
+	return needs_kick;
+}
+
+/*
+ * Returns false if we couldn't fill entirely (OOM).
+ *
+ * Normally run in the receive path, but can also be run from ndo_open
+ * before we're receiving packets, or from refill_work which is
+ * careful to disable receiving (using napi_disable).
+ */
+bool try_fill_recv(struct net_device *netdev, struct receive_queue *rq,
+				   gfp_t gfp)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t err = 0;
+	bool oom = 0;
+	unsigned long flags = 0;
+
+	do {
+		err = add_recvbuf_mergeable(en_dev, rq, gfp);
+		oom = err == -ENOMEM;
+		if (err) {
+			break;
+		}
+	} while (rq->vq->num_free);
+
+	if (virtqueue_kick_prepare_packed(rq->vq) && virtqueue_notify(rq->vq)) {
+		flags = u64_stats_update_begin_irqsave(&rq->stats.syncp);
+		rq->stats.kicks++;
+		u64_stats_update_end_irqrestore(&rq->stats.syncp, flags);
+	}
+
+	return !oom;
+}
+
+int32_t virtnet_receive(struct receive_queue *rq, int32_t budget)
+{
+	struct net_device *netdev = rq->vq->vdev;
+	struct zxdh_en_priv *en_priv = netdev_priv(rq->vq->vdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct virtnet_rq_stats stats = {};
+	uint32_t len = 0;
+	void *buf = NULL;
+	int32_t i = 0;
+	void *ctx = NULL;
+
+	while (stats.packets < budget &&
+		   (buf = virtqueue_get_buf_ctx_packed(rq->vq, &len, &ctx))) {
+		receive_buf(en_dev, rq, buf, len, ctx, &stats);
+		stats.packets++;
+		netdev->stats.rx_packets++;
+	}
+
+	if (rq->vq->num_free >
+		min((uint32_t)budget, virtqueue_get_vring_size(rq->vq)) / 2) {
+		if (!try_fill_recv(rq->vq->vdev, rq, GFP_ATOMIC)) {
+			schedule_delayed_work(&en_dev->refill, 0);
+		}
+	}
+
+	u64_stats_update_begin(&rq->stats.syncp);
+	for (i = 0; i < VIRTNET_RQ_STATS_LEN; i++) {
+		size_t offset = virtnet_rq_stats_desc[i].offset;
+		uint64_t *item;
+
+		item = (uint64_t *)((uint8_t *)&rq->stats + offset);
+		*item += *(uint64_t *)((uint8_t *)&stats + offset);
+	}
+	u64_stats_update_end(&rq->stats.syncp);
+
+	return stats.packets;
+}
+
+void virtqueue_napi_complete(struct napi_struct *napi, struct virtqueue *vq,
+							 int32_t processed)
+{
+	int32_t opaque = 0;
+
+	opaque = virtqueue_enable_cb_prepare(vq);
+	if (napi_complete_done(napi, processed)) {
+		if (unlikely(virtqueue_poll(vq, opaque))) {
+			virtqueue_napi_schedule(napi, vq);
+		}
+	} else {
+		virtqueue_disable_cb(vq);
+	}
+}
+
+int virtnet_poll(struct napi_struct *napi, int budget)
+{
+	struct receive_queue *rq = container_of(napi, struct receive_queue, napi);
+	uint32_t received = 0;
+
+	virtnet_poll_cleantx(rq);
+
+	received = virtnet_receive(rq, budget);
+
+	/* Out of packets? */
+	if (received < budget) {
+		virtqueue_napi_complete(napi, rq->vq, received);
+	}
+
+	return received;
+}
+
+int32_t virtnet_alloc_queues(struct zxdh_en_device *en_dev)
+{
+	int32_t i = 0;
+
+	en_dev->sq =
+			kcalloc(en_dev->max_queue_pairs, sizeof(*en_dev->sq), GFP_KERNEL);
+	if (unlikely(en_dev->sq == NULL)) {
+		LOG_ERR("vi->sq kcalloc failed\n");
+		goto err_sq;
+	}
+
+	en_dev->rq =
+			kcalloc(en_dev->max_queue_pairs, sizeof(*en_dev->rq), GFP_KERNEL);
+	if (unlikely(en_dev->rq == NULL)) {
+		LOG_ERR("vi->rq kcalloc failed\n");
+		goto err_rq;
+	}
+
+	INIT_DELAYED_WORK(&en_dev->refill, refill_work);
+
+	for (i = 0; i < en_dev->curr_queue_pairs; i++) {
+		en_dev->rq[i].pages = NULL;
+		netif_napi_add(en_dev->netdev, &en_dev->rq[i].napi, virtnet_poll,
+					   NAPI_POLL_WEIGHT);
+		netif_tx_napi_add(en_dev->netdev, &en_dev->sq[i].napi, virtnet_poll_tx,
+						  NAPI_POLL_WEIGHT);
+
+		sg_init_table(en_dev->rq[i].sg, ARRAY_SIZE(en_dev->rq[i].sg));
+		ewma_pkt_len_init(&en_dev->rq[i].mrg_avg_pkt_len);
+		sg_init_table(en_dev->sq[i].sg, ARRAY_SIZE(en_dev->sq[i].sg));
+
+		u64_stats_init(&en_dev->rq[i].stats.syncp);
+		u64_stats_init(&en_dev->sq[i].stats.syncp);
+	}
+
+	return 0;
+
+err_rq:
+	kfree(en_dev->sq);
+	en_dev->sq = NULL;
+err_sq:
+	return -ENOMEM;
+}
+
+/**
+ * virtqueue_set_affinity - setting affinity for a virtqueue
+ * @vq: the virtqueue
+ * @cpu_mask: the cpu no.
+ *
+ * Pay attention the function are best-effort: the affinity hint may not be set
+ * due to config support, irq type and sharing.
+ *
+ */
+int32_t virtqueue_set_affinity(struct virtqueue *vq,
+							   const struct cpumask *cpu_mask)
+{
+	if (!vq->callback) {
+		LOG_ERR("vq->callback is null\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void refill_work(struct work_struct *work)
+{
+	int32_t i = 0;
+	bool still_empty = false;
+	struct zxdh_en_device *en_dev =
+			container_of(work, struct zxdh_en_device, refill.work);
+
+	for (i = 0; i < en_dev->curr_queue_pairs; i++) {
+		struct receive_queue *rq = &en_dev->rq[i];
+
+		napi_disable(&rq->napi);
+		still_empty = !try_fill_recv(en_dev->netdev, rq, GFP_KERNEL);
+		virtnet_napi_enable(rq->vq, &rq->napi);
+
+		/* In theory, this can happen: if we don't get any buffers in
+     * we will *never* try to fill again.
+     */
+		if (still_empty) {
+			schedule_delayed_work(&en_dev->refill, HZ / 2);
+		}
+	}
+}
+
+int32_t dh_eq_vqs_vring_int(struct notifier_block *nb, unsigned long action,
+							void *data)
+{
+	struct dh_eq_vq *eq_vq = container_of(nb, struct dh_eq_vq, irq_nb);
+	struct dh_eq_vqs *eq_vqs = container_of(eq_vq, struct dh_eq_vqs, vq_s);
+	struct list_head *item = NULL;
+	struct zxdh_pci_vq_info *info = NULL;
+	struct vring_virtqueue *vq = NULL;
+
+	list_for_each(item, &eq_vqs->vqs) {
+		info = list_entry(item, struct zxdh_pci_vq_info, node);
+
+		vq = to_vvq(info->vq);
+		if (!more_used_packed(vq)) {
+			continue;
+		}
+
+		if (unlikely(vq->broken)) {
+			LOG_ERR("vq:%d is broken\n", info->vq->phy_index);
+			continue;
+		}
+
+		/* Just a hint for performance: so it's ok that this can be racy! */
+		if (vq->event) {
+			vq->event_triggered = true;
+		}
+
+		if (vq->vq.callback) {
+			vq->vq.callback(&vq->vq);
+		}
+	}
+
+	return 0;
+}
+
+static DEFINE_SPINLOCK(vp_find_lock);
+
+int32_t vp_find_vqs_msix(struct net_device *netdev, unsigned nvqs,
+						 struct virtqueue *vqs[], vq_callback_t *callbacks[],
+						 const char *const names[], const bool *ctx)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t err = 0;
+	uint16_t qidx = 0;
+	int32_t phy_index = -1;
+
+	en_dev->vqs = kcalloc(nvqs, sizeof(*en_dev->vqs), GFP_KERNEL);
+	if (unlikely(en_dev->vqs == NULL)) {
+		LOG_ERR("zxdev->vqs kcalloc failed\n");
+		return -ENOMEM;
+	}
+
+	spin_lock(&vp_find_lock);
+	for (qidx = 0; qidx < nvqs; ++qidx) {
+		phy_index = en_dev->ops->get_phy_vq(en_dev->parent, qidx);
+		if (phy_index < 0) {
+			LOG_ERR("get_phy_vq failed: %d\n", phy_index);
+			err = phy_index;
+			goto err;
+		}
+		en_dev->phy_index[qidx] = phy_index;
+
+		vqs[qidx] = vp_setup_vq(netdev, qidx, callbacks[qidx], names[qidx],
+								ctx ? ctx[qidx] : false, qidx);
+		if (IS_ERR_OR_NULL(vqs[qidx])) {
+			err = PTR_ERR(vqs[qidx]);
+			LOG_ERR("vp_setup_vq failed: %d\n", err);
+			goto err;
+		}
+
+		en_dev->ops->set_queue_enable(en_dev->parent, phy_index, true);
+	}
+	spin_unlock(&vp_find_lock);
+	return 0;
+
+err:
+	en_dev->ops->release_phy_vq(en_dev->parent, en_dev->phy_index, qidx + 1);
+	spin_unlock(&vp_find_lock);
+	vp_del_vqs(netdev);
+	return err;
+}
+
+/* How large should a single buffer be so a queue full of these can fit at
+ * least one full packet?
+ * Logic below assumes the mergeable buffer header is used.
+ */
+uint32_t mergeable_min_buf_len(struct zxdh_en_device *en_dev,
+							   struct virtqueue *vq)
+{
+	const uint32_t hdr_len = sizeof(struct zxdh_net_hdr);
+	uint32_t rq_size = virtqueue_get_vring_size(vq);
+	uint32_t packet_len = en_dev->netdev->max_mtu;
+	uint32_t buf_len = hdr_len + ETH_HLEN + VLAN_HLEN + packet_len;
+	uint32_t min_buf_len = DIV_ROUND_UP(buf_len, rq_size);
+
+	return max(max(min_buf_len, hdr_len) - hdr_len, (uint32_t)GOOD_PACKET_LEN);
+}
+
+void zxdh_en_recv_pkts(struct virtqueue *rvq)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(rvq->vdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct receive_queue *rq = &en_dev->rq[vq2rxq(rvq)];
+
+	virtqueue_napi_schedule(&rq->napi, rvq);
+}
+
+void zxdh_en_xmit_pkts(struct virtqueue *tvq)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(tvq->vdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct napi_struct *napi = &en_dev->sq[vq2txq(tvq)].napi;
+
+	/* Suppress further interrupts. */
+	virtqueue_disable_cb(tvq);
+
+	if (napi->weight) {
+		virtqueue_napi_schedule(napi, tvq);
+	} else {
+		/* We were probably waiting for more output buffers. */
+		netif_wake_subqueue(en_dev->netdev, vq2txq(tvq));
+		en_dev->hw_stats.q_stats[vq2txq(tvq)].q_tx_wake++;
+	}
+}
+
+int32_t virtnet_find_vqs(struct zxdh_en_device *en_dev)
+{
+	vq_callback_t **callbacks = NULL;
+	struct virtqueue **vqs = NULL;
+	int32_t ret = -ENOMEM;
+	int32_t i = 0;
+	int32_t total_vqs = 0;
+	const char **names = NULL;
+	bool *ctx = NULL;
+
+	total_vqs = en_dev->max_queue_pairs * 2;
+
+	/* Allocate space for find_vqs parameters */
+	vqs = kcalloc(total_vqs, sizeof(*vqs), GFP_KERNEL);
+	if (unlikely(vqs == NULL)) {
+		LOG_ERR("vqs kcalloc failed\n");
+		goto err_vq;
+	}
+
+	callbacks = kmalloc_array(total_vqs, sizeof(*callbacks), GFP_KERNEL);
+	if (unlikely(callbacks == NULL)) {
+		LOG_ERR("callbacks kmalloc_array failed\n");
+		goto err_callback;
+	}
+
+	names = kmalloc_array(total_vqs, sizeof(*names), GFP_KERNEL);
+	if (unlikely(names == NULL)) {
+		LOG_ERR("names kmalloc_array failed\n");
+		goto err_names;
+	}
+
+	ctx = kcalloc(total_vqs, sizeof(*ctx), GFP_KERNEL);
+	if (unlikely(ctx == NULL)) {
+		LOG_ERR("ctx kmalloc failed\n");
+		goto err_ctx;
+	}
+
+	/* Allocate/initialize parameters for services send/receive virtqueues */
+	for (i = 0; i < en_dev->max_queue_pairs; i++) {
+		callbacks[rxq2vq(i)] = zxdh_en_recv_pkts;
+		callbacks[txq2vq(i)] = zxdh_en_xmit_pkts;
+		sprintf(en_dev->rq[i].name, "input.%d", i);
+		sprintf(en_dev->sq[i].name, "output.%d", i);
+		names[rxq2vq(i)] = en_dev->rq[i].name;
+		names[txq2vq(i)] = en_dev->sq[i].name;
+		if (ctx) {
+			ctx[rxq2vq(i)] = true;
+		}
+	}
+
+	ret = vp_find_vqs_msix(en_dev->netdev, total_vqs, vqs, callbacks, names,
+						   ctx);
+	if (ret) {
+		LOG_ERR("vp_find_vqs_msix failed: %d\n", ret);
+		goto err_find;
+	}
+
+	for (i = 0; i < en_dev->max_queue_pairs; i++) {
+		en_dev->rq[i].vq = vqs[rxq2vq(i)];
+		en_dev->rq[i].min_buf_len =
+				mergeable_min_buf_len(en_dev, en_dev->rq[i].vq);
+		en_dev->sq[i].vq = vqs[txq2vq(i)];
+	}
+
+err_find:
+	kfree(ctx);
+	ctx = NULL;
+err_ctx:
+	kfree(names);
+	names = NULL;
+err_names:
+	kfree(callbacks);
+	callbacks = NULL;
+err_callback:
+	kfree(vqs);
+	vqs = NULL;
+err_vq:
+	return ret;
+}
+
+void virtnet_free_queues(struct zxdh_en_device *en_dev)
+{
+	int32_t i = 0;
+
+	for (i = 0; i < en_dev->max_queue_pairs; i++) {
+		netif_napi_del(&en_dev->rq[i].napi);
+		netif_napi_del(&en_dev->sq[i].napi);
+	}
+
+	/* We called __netif_napi_del(),
+   * we need to respect an RCU grace period before freeing zxdev->rq
+   */
+	synchronize_net();
+
+	kfree(en_dev->rq);
+	kfree(en_dev->sq);
+}
+
+void *virtqueue_detach_unused_buf_packed(struct virtqueue *_vq)
+{
+	struct vring_virtqueue *vq = to_vvq(_vq);
+	uint32_t i = 0;
+	void *buf = NULL;
+
+	START_USE(vq);
+
+	for (i = 0; i < vq->packed.vring.num; i++) {
+		if (!vq->packed.desc_state[i].data) {
+			continue;
+		}
+
+		/* detach_buf clears data, so grab it now. */
+		buf = vq->packed.desc_state[i].data;
+		detach_buf_packed(vq, i, NULL);
+		END_USE(vq);
+		return buf;
+	}
+
+	/* That should have freed everything. */
+	BUG_ON(vq->vq.num_free != vq->packed.vring.num);
+
+	END_USE(vq);
+	return NULL;
+}
+
+void zxdh_free_unused_bufs(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct virtqueue *vq = NULL;
+	void *buf = NULL;
+	int32_t i = 0;
+
+	for (i = 0; i < en_dev->max_queue_pairs; i++) {
+		vq = en_dev->sq[i].vq;
+		while ((buf = virtqueue_detach_unused_buf_packed(vq)) != NULL) {
+#ifdef ZXDH_MSGQ
+			if (i == (en_dev->max_queue_pairs - 1)) {
+				if (en_dev->need_msgq) {
+					ZXDH_FREE_PTR(buf);
+					continue;
+				}
+			}
+#endif
+			dev_kfree_skb(buf);
+		}
+	}
+
+	for (i = 0; i < en_dev->max_queue_pairs; i++) {
+		vq = en_dev->rq[i].vq;
+		while ((buf = virtqueue_detach_unused_buf_packed(vq)) != NULL) {
+			put_page(virt_to_head_page(buf));
+		}
+	}
+}
+
+struct page *get_a_page(struct receive_queue *rq, gfp_t gfp_mask)
+{
+	struct page *p = rq->pages;
+
+	if (p) {
+		rq->pages = (struct page *)p->private;
+		/* clear private here, it is used to chain pages */
+		p->private = 0;
+	} else {
+		p = alloc_page(gfp_mask);
+	}
+	return p;
+}
+
+void _free_receive_bufs(struct zxdh_en_device *en_dev)
+{
+	int32_t i = 0;
+
+	for (i = 0; i < en_dev->max_queue_pairs; i++) {
+		while (en_dev->rq[i].pages) {
+			__free_pages(get_a_page(&en_dev->rq[i], GFP_KERNEL), 0);
+		}
+	}
+}
+
+void zxdh_free_receive_bufs(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	rtnl_lock();
+	_free_receive_bufs(en_dev);
+	rtnl_unlock();
+}
+
+void zxdh_free_receive_page_frags(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t i = 0;
+
+	for (i = 0; i < en_dev->max_queue_pairs; i++) {
+		if (en_dev->rq[i].alloc_frag.page) {
+			put_page(en_dev->rq[i].alloc_frag.page);
+		}
+	}
+}
+
+void zxdh_virtnet_del_vqs(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	vp_del_vqs(netdev);
+	en_dev->ops->vqs_unbind_eqs(en_dev->parent,
+								(en_dev->max_queue_pairs * 2 - 1));
+	en_dev->ops->vqs_channel_unbind_handler(en_dev->parent,
+											(en_dev->max_queue_pairs * 2 - 1));
+	virtnet_free_queues(en_dev);
+}
+
+void zxdh_vqs_uninit(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	zxdh_vp_reset(netdev);
+
+	cancel_delayed_work_sync(&en_dev->refill);
+	zxdh_free_unused_bufs(netdev);
+	zxdh_free_receive_bufs(netdev);
+	zxdh_free_receive_page_frags(netdev);
+	zxdh_virtnet_del_vqs(netdev);
+	en_dev->ops->release_phy_vq(en_dev->parent, en_dev->phy_index,
+								en_dev->max_queue_pairs * 2);
+}
+
+int32_t zxdh_vqs_init(struct net_device *netdev)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t ret = 0;
+
+	en_dev->hdr_len = sizeof(struct zxdh_net_hdr);
+	en_dev->any_header_sg = zxdh_has_feature(netdev, ZXDH_F_ANY_LAYOUT);
+	en_dev->netdev->needed_headroom = en_dev->hdr_len;
+	en_dev->max_queue_pairs = max_pairs;
+	memset(en_dev->phy_index, 0xFF, sizeof(en_dev->phy_index));
+
+	if (en_dev->ops->is_bond(en_dev->parent)) {
+		en_dev->max_queue_pairs = ZXDH_BOND_ETH_MQ_PAIRS_NUM;
+	}
+	en_dev->curr_queue_pairs = en_dev->max_queue_pairs;
+
+#ifdef ZXDH_MSGQ
+	if ((en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) &&
+			((!en_dev->ops->is_bond(en_dev->parent)) ||
+			 (en_dev->ops->is_bond(en_dev->parent) &&
+			  en_dev->ops->if_init(en_dev->parent)))) {
+		en_dev->need_msgq = true;
+		en_dev->max_queue_pairs += ZXDH_PQ_PAIRS_NUM;
+		LOG_INFO("max_queue_pairs: %d\n", en_dev->max_queue_pairs);
+	}
+#endif
+
+	INIT_LIST_HEAD(&en_dev->vqs_list);
+	spin_lock_init(&en_dev->vqs_list_lock);
+
+	INIT_LIST_HEAD(&en_dev->virtqueues);
+	spin_lock_init(&en_dev->lock);
+
+	/* Allocate services send & receive queues */
+	ret = virtnet_alloc_queues(en_dev);
+	if (ret) {
+		LOG_ERR("virtnet_alloc_queues failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = virtnet_find_vqs(en_dev);
+	if (ret) {
+		LOG_ERR("virtnet_find_vqs failed: %d\n", ret);
+		goto err_find_vqs;
+	}
+
+	rtnl_lock();
+	netif_set_real_num_tx_queues(en_dev->netdev, en_dev->curr_queue_pairs);
+	rtnl_unlock();
+	rtnl_lock();
+	netif_set_real_num_rx_queues(en_dev->netdev, en_dev->curr_queue_pairs);
+	rtnl_unlock();
+
+	return 0;
+
+err_find_vqs:
+	virtnet_free_queues(en_dev);
+	return ret;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_aux/queue.h b/src/net/drivers/net/ethernet/dinghai/en_aux/queue.h
index 0c370d71c6c75f5917d015f8c2d2fd9be43f4a0f..77a72bc00caa79885da91644eafb5de47532c607 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_aux/queue.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_aux/queue.h
@@ -1,830 +1,792 @@
-#ifndef __ZXDH_QUEUE_H__
-#define __ZXDH_QUEUE_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/netdevice.h>
-#include <linux/filter.h>
-#include <linux/average.h>
-#include <linux/mm_types_task.h>
-#include <linux/bpf.h>
-#include <linux/bpf_trace.h>
-#include <net/xdp.h>
-#include <linux/printk.h>
-#include <linux/dinghai/queue.h>
-#include <linux/dinghai/kcompat.h>
-
-/*========================================================
- * 是否走1588处理流程（1588pd头宏开关）:
- *     在提交代码时候这里注释掉，在使用1588功能时需要打开。
- *=========================================================*/
-// #define TIME_STAMP_1588
-
-/*========================================================
- * 是否打开依赖PTP驱动的接口调用代码:
- *     在提交代码时候这里注释掉，在实际调试时需要打开。
- *=========================================================*/
-#define PTP_DRIVER_INTERFACE_EN
-
-/**========================================================
- *  是否打开依赖os时间戳补丁接口的代码:
- *      在提交代码时候这里注释掉，在实际调试时需要打开。
- *=========================================================*/
-/* #define CGEL_TSTAMP_2_PATCH_EN TODO 补丁不可用*/
-
-/* 判断两个值是否相等，相等表示出错，打印信息后返回指定值 */
-#define CHECK_EQUAL_ERR(a, b, c, fmt, arg...)   \
-do {                                            \
-    if (unlikely(a == b))                       \
-    {                                           \
-        LOG_ERR(fmt, ##arg);                    \
-        return c;                               \
-    }                                           \
-} while(0)
-
-/* 判断两个值是否不等，不等表示出错，打印信息后返回指定值 */
-#define CHECK_UNEQUAL_ERR(a, b, c, fmt, arg...) \
-do {                                            \
-    if (unlikely(a != b))                       \
-    {                                           \
-        LOG_ERR(fmt, ##arg);                    \
-        return c;                               \
-    }                                           \
-} while(0)
-
-#define ZXDH_MQ_PAIRS_NUM 8
-#define ZXDH_PQ_PAIRS_NUM 1
-#define ZXDH_MAX_PAIRS_NUM 128
-#define ZXDH_BOND_ETH_MQ_PAIRS_NUM 1
-#define ZXDH_MAX_QUEUES_NUM 4096
-#define ZXDH_PF_MAX_BAR_VAL 0x5
-#define ZXDH_PF_BAR0 0
-#define ZXDH_PF_MAX_DESC_NUM (32 * 1024)
-#define ZXDH_PF_MIN_DESC_NUM 1024
-#define ZXDH_INDIR_RQT_SIZE 256
-#define ZXDH_NET_HASH_KEY_SIZE 40
-
-#define VQM_HOST_BAR_OFFSET 0x0
-#define PHY_VQ_REG_OFFSET 0x5000
-#define LOCK_VQ_REG_OFFSET 0x90
-#define ZXDH_PHY_REG_BITS 32
-#define ZXDH_PF_LOCK_ENABLE_MASK 0x1
-#define ZXDH_PF_RELEASE_LOCK_VAL 0
-#define ZXDH_PF_GET_PHY_INDEX_DONE 1
-#define ZXDH_PF_GET_PHY_INDEX_BIT 1
-#define ZXDH_PF_WAIT_COUNT 2048
-#define ZXDH_PF_DELAY_US 10
-#define ZXDH_PF_RQ_TYPE 0
-#define ZXDH_PF_TQ_TYPE 1
-#define ZXDH_PF_POWER_INDEX2 2
-
-#define MSG_PAYLOAD_FIX_FIELD 8
-#define MSG_CHAN_PF_MODULE_ID 0
-#define MSG_PAYLOAD_TYPE_WRITE 1
-#define MSG_PAYLOAD_FIELD_MSG_CHL 2
-#define MSG_PAYLOAD_FIELD_DATA_CHL 3
-#define MSG_PAYLOAD_MSG_CHL_SLEN 4
-#define MSG_RECV_BUF_LEN 6
-
-#define ZXDH_MAC_NUM 6
-#define ZXDH_MAX_MTU 14000
-#define ZXDH_DEFAULT_MTU 1500
-
-/* The feature bitmap for zxdh net */
-#define ZXDH_NET_F_MRG_RXBUF             15   /* Host can merge receive buffers. */
-#define ZXDH_NET_F_STATUS                16   /* net_config.status available */
-#define ZXDH_NET_F_CTRL_VQ               17   /* Control channel available */
-#define ZXDH_NET_F_MQ                    22   /* Device supports Receive Flow Steering */
-#define ZXDH_F_ANY_LAYOUT                27   /* Can the device handle any descriptor layout? */
-#define ZXDH_RING_F_INDIRECT_DESC        28   /* We support indirect buffer descriptors */
-
-/* The Guest publishes the used index for which it expects an interrupt
- * at the end of the avail ring. Host should ignore the avail->flags field. */
-/* The Host publishes the avail index for which it expects a kick
- * at the end of the used ring. Guest should ignore the used->flags field. */
-#define ZXDH_RING_F_EVENT_IDX            29
-
-#define ZXDH_F_VERSION_1                 32   /* v1.0 compliant */
-
-/*
- * If clear - device has the platform DMA (e.g. IOMMU) bypass quirk feature.
- * If set - use platform DMA tools to access the memory.
- *
- * Note the reverse polarity (compared to most other features),
- * this is for compatibility with legacy systems.
- */
-#define ZXDH_F_ACCESS_PLATFORM           33
-
-/* This feature indicates support for the packed virtqueue layout. */
-#define ZXDH_F_RING_PACKED               34
-
-/*
- * This feature indicates that memory accesses by the driver and the
- * device are ordered in a way described by the platform.
- */
-#define ZXDH_F_ORDER_PLATFORM            36
-
-/* This marks a buffer as continuing via the next field. */
-#define VRING_DESC_F_NEXT                1
-/* This marks a buffer as write-only (otherwise read-only). */
-#define VRING_DESC_F_WRITE               2
-/* This means the buffer contains a list of buffer descriptors. */
-#define VRING_DESC_F_INDIRECT            4
-
-/*
- * Mark a descriptor as available or used in packed ring.
- * Notice: they are defined as shifts instead of shifted values.
- */
-#define VRING_PACKED_DESC_F_AVAIL        7
-#define VRING_PACKED_DESC_F_USED         15
-
-/* The Host uses this in used->flags to advise the Guest: don't kick me when
- * you add a buffer.  It's unreliable, so it's simply an optimization.  Guest
- * will still kick if it's out of buffers. */
-#define VRING_USED_F_NO_NOTIFY           1
-/* The Guest uses this in avail->flags to advise the Host: don't interrupt me
- * when you consume a buffer.  It's unreliable, so it's simply an
- * optimization.  */
-#define VRING_AVAIL_F_NO_INTERRUPT       1
-
-/* Enable events in packed ring. */
-#define VRING_PACKED_EVENT_FLAG_ENABLE   0x0
-/* Disable events in packed ring. */
-#define VRING_PACKED_EVENT_FLAG_DISABLE  0x1
-/*
- * Enable events for a specific descriptor in packed ring.
- * (as specified by Descriptor Ring Change Event Offset/Wrap Counter).
- * Only valid if ZXDH_RING_F_EVENT_IDX has been negotiated.
- */
-#define VRING_PACKED_EVENT_FLAG_DESC     0x2
-
-/*
- * Wrap counter bit shift in event suppression structure
- * of packed ring.
- */
-#define VRING_PACKED_EVENT_F_WRAP_CTR    15
-
-/* Alignment requirements for vring elements */
-#define VRING_AVAIL_ALIGN_SIZE 2
-#define VRING_USED_ALIGN_SIZE  4
-#define VRING_DESC_ALIGN_SIZE  16
-
-#define MRG_CTX_HEADER_SHIFT 22
-
-
-/* FIXME: MTU in config. */
-#define GOOD_PACKET_LEN (ETH_HLEN + VLAN_HLEN + ETH_DATA_LEN)
-#define GOOD_COPY_LEN   128
-
-
-#define TX_PORT_NP 0x00
-#define TX_PORT_DRS 0x01
-#define TX_PORT_DTP 0x02
-#define HDR_2B_UNIT 2
-#define ENABLE_PI_FLAG_32B 0x1
-#define DISABLE_PI_FIELD_PARSE 0x80
-#define IPV4_TYPE 0x0
-#define IPV6_TYPE 0x1
-#define NOT_IP_TYPE 0x2
-#define PKT_SRC_NP 0x0
-#define PKT_SRC_CPU 0x1
-#define PCODE_IP 0x1
-#define PCODE_TCP 0x2
-#define PCODE_UDP 0x3
-#define INVALID_ETH_PORT_ID 0xff
-#define ETH_MTU_4B_UNIT 4
-#define IP_FRG_CSUM_FLAG 0x8000
-#define NOT_IP_FRG_CSUM_FLAG 0x6000
-#define TCP_FRG_CSUM_FLAG 0x24
-#define NOT_TCP_FRG_CSUM_FLAG 0x30
-#define HDR_2B_UNIT 2
-
-#define HDR_BUFFER_LEN 100
-#define IP_BASE_HLEN 20
-#define IPV6_BASE_HLEN 40
-#define TCP_BASE_HLEN 20
-
-#define OUTER_IP_CHECKSUM_OFFSET    (12)
-#define INNER_IP_CHECKSUM_OFFSET    (15)
-#define INNER_L4_CHECKSUM_OFFSET    (2)
-#define PI_HDR_L3_CHKSUM_ERROR_CODE (0xff)
-#define PI_HDR_L4_CHKSUM_ERROR_CODE (0xff)
-#define OUTER_IP_CHKSUM_ERROT_CODE  (0x20)
-
-#define RX_VLAN_STRIPED_MASK        (1 << 4)
-#define RX_QINQ_STRIPED_MASK        (1 << 14)
-#define RX_TPID_VLAN_ID_MASK        (0xfff)
-
-/* PD header offload flags */
-#define PANELID_EN (1 << 15)
-
-/* PD header sk_prio */
-#define ZXDH_DCBNL_SET_SK_PRIO(sk_prio)   ((0x7 & sk_prio) << 8)
-
-/*
- * __vqm{16,32,64} have the following meaning:
- * - __u{16,32,64} for zxdh devices in legacy mode, accessed in native endian
- * - __le{16,32,64} for standard-compliant zxdh devices
- */
-typedef __u16 __bitwise __vqm16;
-typedef __u32 __bitwise __vqm32;
-typedef __u64 __bitwise __vqm64;
-
-
-/* Constants for MSI-X */
-/* Use first vector for configuration changes, second and the rest for
- * virtqueues Thus, we need at least 2 vectors for MSI. */
-enum
-{
-    VP_MSIX_CONFIG_VECTOR = 0,
-    VP_MSIX_VQ_VECTOR = 1,
-};
-
-
-struct vring_packed_desc_event
-{
-    /* Descriptor Ring Change Event Offset/Wrap Counter. */
-    __le16 off_wrap;
-    /* Descriptor Ring Change Event Flags. */
-    __le16 flags;
-};
-
-struct vring_packed_desc
-{
-    /* Buffer Address. */
-    __le64 addr;
-    /* Buffer Length. */
-    __le32 len;
-    /* Buffer ID. */
-    __le16 id;
-    /* The flags depending on descriptor type. */
-    __le16 flags;
-};
-
-struct vring_desc_state_packed
-{
-    void *data;         /* Data for callback. */
-    struct vring_packed_desc *indir_desc; /* Indirect descriptor, if any. */
-    uint16_t num;            /* Descriptor list length. */
-    uint16_t last;           /* The last desc state in a list. */
-};
-
-struct vring_desc_extra
-{
-    dma_addr_t addr;    /* Buffer DMA addr. */
-    uint32_t len;            /* Buffer length. */
-    uint16_t flags;          /* Descriptor flags. */
-    uint16_t next;           /* The next desc state in a list. */
-};
-
-union pkt_type_t
-{
-    uint8_t pkt_type;
-    struct
-    {
-        uint8_t pkt_code:5;
-        uint8_t pkt_src:1;
-        uint8_t ip_type:2;
-    }type_ctx;
-}__attribute__((packed));
-
-struct pi_net_hdr
-{
-    uint8_t bttl_pi_len;
-    union pkt_type_t pt;
-    uint16_t vlan_id;
-    uint32_t ipv6_exp_flags;
-    uint16_t hdr_l3_offset;
-    uint16_t hdr_l4_offset;
-    uint8_t eth_port_id;
-    uint8_t pkt_action_flag2;
-    uint16_t pkt_action_flag1;
-    uint8_t sa_index[8];
-    uint8_t error_code[2];
-    uint8_t rsv[6];
-}__attribute__((packed));
-
-struct pd_net_hdr_tx
-{
-#define TXCAP_STAG_INSERT_EN_BIT      (1 << 14)
-#define TXCAP_CTAG_INSERT_EN_BIT      (1 << 13)
-#define DELAY_STATISTICS_INSERT_EN_BIT      (1 << 7)
-    uint16_t ol_flag;
-    uint8_t rsv;
-    uint8_t panel_id;
-    uint8_t tag_idx;
-    uint8_t tag_data;
-    uint16_t vfid;
-    struct {
-        uint16_t tpid;
-        uint16_t tci;
-    } svlan;
-    struct {
-        uint16_t tpid;
-        uint16_t tci;
-    } cvlan;
-}__attribute__((packed));
-
-
-struct pd_net_hdr_rx
-{
-#define RX_PD_HEAD_VLAN_STRIP_BIT      (1 << 28)
-    uint32_t flags;
-    uint32_t rss_hash;
-    uint32_t fd;
-    uint16_t striped_stci;
-    uint16_t striped_ctci;
-    uint8_t tag_idx;
-    uint8_t tag_data;
-    uint16_t src_port;
-    uint16_t outer_pkt_type;
-    uint16_t inner_pkt_type;
-}__attribute__((packed));
-
-/* zxdh net header */
-struct zxdh_net_hdr
-{
-    uint8_t tx_port; //bit7:2 rsv; bit1:0 00:np, 01:DRS, 10:DTP
-    uint8_t pd_len; //bit7 rsv; bit6:0 L2报文前的描述符长度，以2B为单位
-    uint8_t num_buffers; //表示接收方向num buffers字段
-    uint8_t rsv; //保留
-
-    struct pi_net_hdr pi_hdr;
-    struct pd_net_hdr_tx pd_hdr;
-}__attribute__((packed));
-
-struct zxdh_net_1588_hdr
-{
-    uint8_t tx_port; //bit7:2 rsv; bit1:0 00:np, 01:DRS, 10:DTP
-    uint8_t pd_len; //bit7 rsv; bit6:0 L2报文前的描述符长度，以2B为单位
-    uint8_t num_buffers; //表示接收方向num buffers字段
-    uint8_t rsv; //保留
-
-    struct pi_net_hdr pi_hdr;
-    struct pd_net_hdr_tx pd_hdr;
-
-    uint8_t ptp_type[3]; /* 低bit0-16预留，bit17-19 pkt_type, bit23 ptp_udp */
-    uint8_t ts_offset;
-    uint32_t cpu_tx;
-    uint8_t port; /* egress_port/ingress_port, L4报文此字段无用 */
-    uint8_t rsv1[4];
-    uint8_t sec_1588_key[3];
-}__attribute__((packed));
-
-struct zxdh_net_hdr_rcv
-{
-    uint8_t tx_port; //bit7:2 rsv; bit1:0 00:np, 01:DRS, 10:DTP
-    uint8_t pd_len; //bit7 rsv; bit6:0 L2报文前的描述符长度，以2B为单位
-    uint8_t num_buffers; //表示接收方向num buffers字段
-    uint8_t rsv; //保留
-
-    struct pi_net_hdr pi_hdr;
-    struct pd_net_hdr_rx pd_hdr;
-}__attribute__((packed));
-
-struct zxdh_net_1588_hdr_rcv
-{
-    uint8_t tx_port; //bit7:2 rsv; bit1:0 00:np, 01:DRS, 10:DTP
-    uint8_t pd_len; //bit7 rsv; bit6:0 L2报文前的描述符长度，以2B为单位
-    uint8_t num_buffers; //表示接收方向num buffers字段
-    uint8_t rsv; //保留
-
-    struct pi_net_hdr pi_hdr;
-    struct pd_net_hdr_rx pd_hdr;
-
-    uint8_t egress_port;
-    uint8_t ptp_type[2]; /* 低bit0-8预留，bit9-11 pkt_type, bit 12-14预留，bit15 ptp_udp */
-    uint8_t ts_offset;
-    uint32_t rx_ts;
-}__attribute__((packed));
-
-#ifdef DEBUG
-/* For development, we want to crash whenever the ring is screwed. */
-#define BAD_RING(_vq, fmt, args...)                \
-    do {                            \
-        LOG_ERR("%s:"fmt, (_vq)->vq.name, ##args);    \
-        BUG();                        \
-    } while (0)
-/* Caller is supposed to guarantee no reentry. */
-#define START_USE(_vq)                        \
-    do {                            \
-        if ((_vq)->in_use)                \
-            panic("%s:in_use = %i\n",        \
-                  (_vq)->vq.name, (_vq)->in_use);    \
-        (_vq)->in_use = __LINE__;            \
-    } while (0)
-#define END_USE(_vq) \
-    do { BUG_ON(!(_vq)->in_use); (_vq)->in_use = 0; } while(0)
-#define LAST_ADD_TIME_UPDATE(_vq)                \
-    do {                            \
-        ktime_t now = ktime_get();            \
-                                \
-        /* No kick or get, with .1 second between?  Warn. */ \
-        if ((_vq)->last_add_time_valid)            \
-            WARN_ON(ktime_to_ms(ktime_sub(now,    \
-                (_vq)->last_add_time)) > 100);    \
-        (_vq)->last_add_time = now;            \
-        (_vq)->last_add_time_valid = true;        \
-    } while (0)
-#define LAST_ADD_TIME_CHECK(_vq)                \
-    do {                            \
-        if ((_vq)->last_add_time_valid) {        \
-            WARN_ON(ktime_to_ms(ktime_sub(ktime_get(), \
-                      (_vq)->last_add_time)) > 100); \
-        }                        \
-    } while (0)
-#define LAST_ADD_TIME_INVALID(_vq)                \
-    ((_vq)->last_add_time_valid = false)
-#else
-#define BAD_RING(_vq, fmt, args...)                \
-    do {                            \
-        LOG_ERR("%s:"fmt, (_vq)->vq.name, ##args);    \
-        (_vq)->broken = true;                \
-    } while (0)
-#define START_USE(vq)
-#define END_USE(vq)
-#define LAST_ADD_TIME_UPDATE(vq)
-#define LAST_ADD_TIME_CHECK(vq)
-#define LAST_ADD_TIME_INVALID(vq)
-#endif
-
-
-#define vqm_store_mb(weak_barriers, p, v) \
-do { \
-    if (weak_barriers) { \
-        virt_store_mb(*p, v); \
-    } else { \
-        WRITE_ONCE(*p, v); \
-        mb(); \
-    } \
-} while (0) \
-
-
-/* This is the PCI capability header: */
-struct zxdh_pci_cap
-{
-    __u8 cap_vndr;        /* Generic PCI field: PCI_CAP_ID_VNDR */
-    __u8 cap_next;        /* Generic PCI field: next ptr. */
-    __u8 cap_len;         /* Generic PCI field: capability length */
-    __u8 cfg_type;        /* Identifies the structure. */
-    __u8 bar;             /* Where to find it. */
-    __u8 id;              /* Multiple capabilities of the same type */
-    __u8 padding[2];      /* Pad to full dword. */
-    __le32 offset;        /* Offset within bar. */
-    __le32 length;        /* Length of the structure, in bytes. */
-};
-
-struct zxdh_pci_notify_cap
-{
-    struct zxdh_pci_cap cap;
-    __le32 notify_off_multiplier; /* Multiplier for queue_notify_off. */
-};
-
-struct virtqueue
-{
-    struct list_head list;
-    void (*callback)(struct virtqueue *vq);
-    const char *name;
-    struct net_device *vdev;
-    uint32_t index;
-    uint32_t phy_index;
-    uint32_t num_free;
-    void *priv;
-};
-
-/* custom queue ring descriptors: 16 bytes. These can chain together via "next". */
-struct vring_desc
-{
-    /* Address (guest-physical). */
-    uint64_t addr;
-    /* Length. */
-    uint32_t len;
-    /* The flags as indicated above. */
-    uint16_t flags;
-    /* We chain unused descriptors via this, too */
-    uint16_t next;
-};
-
-struct vring_avail
-{
-    uint16_t flags;
-    uint16_t idx;
-    uint16_t ring[];
-};
-
-/* u32 is used here for ids for padding reasons. */
-struct vring_used_elem
-{
-    /* Index of start of used descriptor chain. */
-    uint32_t id;
-    /* Total length of the descriptor chain which was used (written to) */
-    uint32_t len;
-};
-
-typedef struct vring_used_elem __attribute__((aligned(VRING_USED_ALIGN_SIZE)))
-    vring_used_elem_t;
-
-struct vring_used
-{
-    uint16_t flags;
-    uint16_t idx;
-    vring_used_elem_t ring[];
-};
-
-typedef struct vring_desc __attribute__((aligned(VRING_DESC_ALIGN_SIZE)))
-    vring_desc_t;
-typedef struct vring_avail __attribute__((aligned(VRING_AVAIL_ALIGN_SIZE)))
-    vring_avail_t;
-typedef struct vring_used __attribute__((aligned(VRING_USED_ALIGN_SIZE)))
-    vring_used_t;
-
-struct vring
-{
-    uint32_t num;
-
-    vring_desc_t *desc;
-
-    vring_avail_t *avail;
-
-    vring_used_t *used;
-};
-
-struct vring_virtqueue
-{
-    struct virtqueue vq;
-
-    /* Is this a packed ring? */
-    bool packed_ring;
-
-    /* Is DMA API used? */
-    bool use_dma_api;
-
-    /* Can we use weak barriers? */
-    bool weak_barriers;
-
-    /* Other side has made a mess, don't try any more. */
-    bool broken;
-
-    /* Host supports indirect buffers */
-    bool indirect;
-
-    /* Host publishes avail event idx */
-    bool event;
-
-    /* Head of free buffer list. */
-    uint32_t free_head;
-    /* Number we've added since last sync. */
-    uint32_t num_added;
-
-    /* Last used index we've seen. */
-    uint16_t last_used_idx;
-
-    /* Hint for event idx: already triggered no need to disable. */
-    bool event_triggered;
-
-    /* Available for packed ring */
-    struct
-    {
-        /* Actual memory layout for this queue. */
-        struct
-        {
-            uint32_t num;
-            struct vring_packed_desc *desc;
-            struct vring_packed_desc_event *driver;
-            struct vring_packed_desc_event *device;
-        } vring;
-
-        /* Driver ring wrap counter. */
-        bool avail_wrap_counter;
-
-        /* Device ring wrap counter. */
-        bool used_wrap_counter;
-
-        /* Avail used flags. */
-        uint16_t avail_used_flags;
-
-        /* Index of the next avail descriptor. */
-        uint16_t next_avail_idx;
-
-        /*
-         * Last written value to driver->flags in
-         * guest byte order.
-         */
-        uint16_t event_flags_shadow;
-
-        /* Per-descriptor state. */
-        struct vring_desc_state_packed *desc_state;
-        struct vring_desc_extra *desc_extra;
-
-        /* DMA address and size information */
-        dma_addr_t ring_dma_addr;
-        dma_addr_t driver_event_dma_addr;
-        dma_addr_t device_event_dma_addr;
-        size_t ring_size_in_bytes;
-        size_t event_size_in_bytes;
-    } packed;
-
-    /* How to notify other side. FIXME: commonalize hcalls! */
-    bool (*notify)(struct virtqueue *vq);
-
-    /* DMA, allocation, and size information */
-    bool we_own_ring;
-
-#ifdef DEBUG
-    /* They're supposed to lock for us. */
-    uint32_t in_use;
-
-    /* Figure out if their kicks are too delayed. */
-    bool last_add_time_valid;
-    ktime_t last_add_time;
-#endif
-};
-
-struct zxdh_pci_vq_info
-{
-    /* the actual virtqueue */
-    struct virtqueue *vq;
-
-    /* the list node for the virtqueues list */
-    struct list_head node;
-
-    /* channel num map 1-1 to vector*/
-    unsigned channel_num;
-};
-
-struct virtnet_stat_desc
-{
-    char desc[ETH_GSTRING_LEN];
-    size_t offset;
-};
-
-struct virtnet_sq_stats
-{
-    struct u64_stats_sync syncp;
-    uint64_t packets;
-    uint64_t bytes;
-    uint64_t xdp_tx;
-    uint64_t xdp_tx_drops;
-    uint64_t kicks;
-    uint64_t tx_timeouts;
-};
-
-struct virtnet_rq_stats
-{
-    struct u64_stats_sync syncp;
-    uint64_t packets;
-    uint64_t bytes;
-    uint64_t drops;
-    uint64_t xdp_packets;
-    uint64_t xdp_tx;
-    uint64_t xdp_redirects;
-    uint64_t xdp_drops;
-    uint64_t kicks;
-};
-#define VIRTNET_SQ_STAT(m)    offsetof(struct virtnet_sq_stats, m)
-#define VIRTNET_RQ_STAT(m)    offsetof(struct virtnet_rq_stats, m)
-
-static const struct virtnet_stat_desc virtnet_sq_stats_desc[] =
-{
-    { "packets",        VIRTNET_SQ_STAT(packets) },
-    { "bytes",          VIRTNET_SQ_STAT(bytes) },
-    { "xdp_tx",         VIRTNET_SQ_STAT(xdp_tx) },
-    { "xdp_tx_drops",   VIRTNET_SQ_STAT(xdp_tx_drops) },
-    { "kicks",          VIRTNET_SQ_STAT(kicks) },
-    { "tx_timeouts",    VIRTNET_SQ_STAT(tx_timeouts) },
-};
-
-static const struct virtnet_stat_desc virtnet_rq_stats_desc[] =
-{
-    { "packets",        VIRTNET_RQ_STAT(packets) },
-    { "bytes",          VIRTNET_RQ_STAT(bytes) },
-    { "drops",          VIRTNET_RQ_STAT(drops) },
-    { "xdp_packets",    VIRTNET_RQ_STAT(xdp_packets) },
-    { "xdp_tx",         VIRTNET_RQ_STAT(xdp_tx) },
-    { "xdp_redirects",  VIRTNET_RQ_STAT(xdp_redirects) },
-    { "xdp_drops",      VIRTNET_RQ_STAT(xdp_drops) },
-    { "kicks",          VIRTNET_RQ_STAT(kicks) },
-};
-
-#define VIRTNET_SQ_STATS_LEN    ARRAY_SIZE(virtnet_sq_stats_desc)
-#define VIRTNET_RQ_STATS_LEN    ARRAY_SIZE(virtnet_rq_stats_desc)
-
-/* RX packet size EWMA. The average packet size is used to determine the packet
- * buffer size when refilling RX rings. As the entire RX ring may be refilled
- * at once, the weight is chosen so that the EWMA will be insensitive to short-
- * term, transient changes in packet size.
- */
-DECLARE_EWMA(pkt_len, 0, 64)
-
-
-/* Internal representation of a send virtqueue */
-struct send_queue
-{
-    /* Virtqueue associated with this send _queue */
-    struct virtqueue *vq;
-
-    /* TX: fragments + linear part + custom queue header */
-    struct scatterlist sg[MAX_SKB_FRAGS + 2];
-
-    /* Name of the send queue: output.$index */
-    char name[40];
-
-    struct virtnet_sq_stats stats;
-
-    struct napi_struct napi;
-
-    uint8_t hdr_buf[HDR_BUFFER_LEN];
-};
-
-/* Internal representation of a receive virtqueue */
-struct receive_queue
-{
-    /* Virtqueue associated with this receive_queue */
-    struct virtqueue *vq;
-
-    struct napi_struct napi;
-
-    struct bpf_prog __rcu *xdp_prog;
-
-    struct virtnet_rq_stats stats;
-
-    /* Chain pages by the private ptr. */
-    struct page *pages;
-
-    /* Average packet length for mergeable receive buffers. */
-    struct ewma_pkt_len mrg_avg_pkt_len; //todo
-
-    /* Page frag for packet buffer allocation. */
-    struct page_frag alloc_frag;
-
-    /* RX: fragments + linear part + custom queue header */
-    struct scatterlist sg[MAX_SKB_FRAGS + 2];
-
-    /* Min single buffer size for mergeable buffers case. */
-    uint32_t min_buf_len;
-
-    /* Name of this receive queue: input.$index */
-    char name[40];
-
-    struct xdp_rxq_info xdp_rxq;
-};
-
-#define to_vvq(_vq) container_of(_vq, struct vring_virtqueue, vq)
-
-typedef void vq_callback_t(struct virtqueue *);
-
-
-void zxdh_print_vring_info(struct virtqueue *vq, uint32_t desc_index, uint32_t desc_num);
-void virtnet_napi_enable(struct virtqueue *vq, struct napi_struct *napi);
-void virtnet_napi_tx_enable(struct net_device *netdev, struct virtqueue *vq, struct napi_struct *napi);
-void virtnet_napi_tx_disable(struct napi_struct *napi);
-void refill_work(struct work_struct *work);
-int virtnet_poll(struct napi_struct *napi, int budget);
-int virtnet_poll_tx(struct napi_struct *napi, int budget);
-int32_t txq2vq(int32_t txq);
-int32_t rxq2vq(int32_t rxq);
-uint16_t vqm16_to_cpu(struct net_device *netdev, __vqm16 val);
-uint8_t vp_get_status(struct net_device *netdev);
-void vp_set_status(struct net_device *netdev, uint8_t status);
-void vp_set_reset_status(struct net_device *netdev, uint8_t status);
-void zxdh_add_status(struct net_device *netdev, uint32_t status);
-void zxdh_vp_enable_cbs(struct net_device *netdev);
-void zxdh_vp_disable_cbs(struct net_device *netdev);
-void zxdh_vp_reset(struct net_device *netdev);
-void vring_free_queue(struct net_device *netdev, size_t size, void *queue, dma_addr_t dma_handle);
-netdev_tx_t start_xmit(struct sk_buff *skb, struct net_device *netdev);
-bool try_fill_recv(struct net_device *netdev, struct receive_queue *rq, gfp_t gfp);
-inline struct zxdh_net_hdr *skb_vnet_hdr(struct sk_buff *skb);
-int32_t virtqueue_add_outbuf(struct virtqueue *vq, struct scatterlist *sg, uint32_t num, void *data, gfp_t gfp);
-void virtqueue_disable_cb(struct virtqueue *_vq);
-void free_old_xmit_skbs(struct net_device *netdev, struct send_queue *sq, bool in_napi);
-bool virtqueue_enable_cb_delayed(struct virtqueue *_vq);
-bool virtqueue_kick_prepare_packed(struct virtqueue *_vq);
-bool virtqueue_notify(struct virtqueue *_vq);
-void zxdh_pf_features_init(struct net_device *netdev);
-bool zxdh_has_feature(struct net_device *netdev, uint32_t fbit);
-bool zxdh_has_status(struct net_device *netdev, uint32_t sbit);
-void zxdh_free_unused_bufs(struct net_device *netdev);
-void zxdh_free_receive_bufs(struct net_device *netdev);
-void zxdh_free_receive_page_frags(struct net_device *netdev);
-void zxdh_virtnet_del_vqs(struct net_device *netdev);
-void zxdh_vqs_uninit(struct net_device *netdev);
-int32_t zxdh_vqs_init(struct net_device *netdev);
-int32_t dh_eq_vqs_vring_int(struct notifier_block *nb, unsigned long action, void *data);
-int32_t vq2rxq(struct virtqueue *vq);
-void *virtqueue_get_buf(struct virtqueue *_vq, uint32_t *len);
-void *virtqueue_get_buf_ctx_packed(struct virtqueue *_vq, uint32_t *len, void **ctx);
-uint32_t virtqueue_get_vring_size(struct virtqueue *_vq);
-void virtqueue_napi_complete(struct napi_struct *napi, struct virtqueue *vq, int32_t processed);
-int32_t virtqueue_add_inbuf_ctx(struct virtqueue *vq,
-                                struct scatterlist *sg, uint32_t num,
-                                void *data,
-                                void *ctx,
-                                gfp_t gfp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef __ZXDH_QUEUE_H__
+#define __ZXDH_QUEUE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/netdevice.h>
+#include <linux/filter.h>
+#include <linux/average.h>
+#include <linux/mm_types_task.h>
+#include <linux/bpf.h>
+#include <linux/bpf_trace.h>
+#include <net/xdp.h>
+#include <linux/printk.h>
+#include <linux/dinghai/queue.h>
+#include <linux/dinghai/kcompat.h>
+
+/*========================================================
+ * 是否走1588处理流程（1588pd头宏开关）:
+ *     在提交代码时候这里注释掉，在使用1588功能时需要打开。
+ *=========================================================*/
+// #define TIME_STAMP_1588
+
+/*========================================================
+ * 是否打开依赖PTP驱动的接口调用代码:
+ *     在提交代码时候这里注释掉，在实际调试时需要打开。
+ *=========================================================*/
+#define PTP_DRIVER_INTERFACE_EN
+
+/**========================================================
+ *  是否打开依赖os时间戳补丁接口的代码:
+ *      在提交代码时候这里注释掉，在实际调试时需要打开。
+ *=========================================================*/
+/* #define CGEL_TSTAMP_2_PATCH_EN TODO 补丁不可用*/
+
+/* 判断两个值是否相等，相等表示出错，打印信息后返回指定值 */
+#define CHECK_EQUAL_ERR(a, b, c, fmt, arg...) \
+	do {                                      \
+		if (unlikely(a == b)) {               \
+			LOG_ERR(fmt, ##arg);              \
+			return c;                         \
+		}                                     \
+	} while (0)
+
+/* 判断两个值是否不等，不等表示出错，打印信息后返回指定值 */
+#define CHECK_UNEQUAL_ERR(a, b, c, fmt, arg...) \
+	do {                                        \
+		if (unlikely(a != b)) {                 \
+			LOG_ERR(fmt, ##arg);                \
+			return c;                           \
+		}                                       \
+	} while (0)
+
+#define ZXDH_MQ_PAIRS_NUM 8
+#define ZXDH_PQ_PAIRS_NUM 1
+#define ZXDH_MAX_PAIRS_NUM 128
+#define ZXDH_BOND_ETH_MQ_PAIRS_NUM 1
+#define ZXDH_MAX_QUEUES_NUM 4096
+#define ZXDH_PF_MAX_BAR_VAL 0x5
+#define ZXDH_PF_BAR0 0
+#define ZXDH_PF_MAX_DESC_NUM (32 * 1024)
+#define ZXDH_PF_MIN_DESC_NUM 1024
+#define ZXDH_INDIR_RQT_SIZE 256
+#define ZXDH_NET_HASH_KEY_SIZE 40
+
+#define VQM_HOST_BAR_OFFSET 0x0
+#define PHY_VQ_REG_OFFSET 0x5000
+#define LOCK_VQ_REG_OFFSET 0x90
+#define ZXDH_PHY_REG_BITS 32
+#define ZXDH_PF_LOCK_ENABLE_MASK 0x1
+#define ZXDH_PF_RELEASE_LOCK_VAL 0
+#define ZXDH_PF_GET_PHY_INDEX_DONE 1
+#define ZXDH_PF_GET_PHY_INDEX_BIT 1
+#define ZXDH_PF_WAIT_COUNT 2048
+#define ZXDH_PF_DELAY_US 10
+#define ZXDH_PF_RQ_TYPE 0
+#define ZXDH_PF_TQ_TYPE 1
+#define ZXDH_PF_POWER_INDEX2 2
+
+#define MSG_PAYLOAD_FIX_FIELD 8
+#define MSG_CHAN_PF_MODULE_ID 0
+#define MSG_PAYLOAD_TYPE_WRITE 1
+#define MSG_PAYLOAD_FIELD_MSG_CHL 2
+#define MSG_PAYLOAD_FIELD_DATA_CHL 3
+#define MSG_PAYLOAD_MSG_CHL_SLEN 4
+#define MSG_RECV_BUF_LEN 6
+
+#define ZXDH_MAC_NUM 6
+#define ZXDH_MAX_MTU 14000
+#define ZXDH_DEFAULT_MTU 1500
+
+/* The feature bitmap for zxdh net */
+#define ZXDH_NET_F_MRG_RXBUF 15 /* Host can merge receive buffers. */
+#define ZXDH_NET_F_STATUS 16 /* net_config.status available */
+#define ZXDH_NET_F_CTRL_VQ 17 /* Control channel available */
+#define ZXDH_NET_F_MQ 22 /* Device supports Receive Flow Steering */
+#define ZXDH_F_ANY_LAYOUT \
+	27 /* Can the device handle any descriptor layout?                           \
+      */
+#define ZXDH_RING_F_INDIRECT_DESC \
+	28 /* We support indirect buffer descriptors */
+
+/* The Guest publishes the used index for which it expects an interrupt
+ * at the end of the avail ring. Host should ignore the avail->flags field. */
+/* The Host publishes the avail index for which it expects a kick
+ * at the end of the used ring. Guest should ignore the used->flags field. */
+#define ZXDH_RING_F_EVENT_IDX 29
+
+#define ZXDH_F_VERSION_1 32 /* v1.0 compliant */
+
+/*
+ * If clear - device has the platform DMA (e.g. IOMMU) bypass quirk feature.
+ * If set - use platform DMA tools to access the memory.
+ *
+ * Note the reverse polarity (compared to most other features),
+ * this is for compatibility with legacy systems.
+ */
+#define ZXDH_F_ACCESS_PLATFORM 33
+
+/* This feature indicates support for the packed virtqueue layout. */
+#define ZXDH_F_RING_PACKED 34
+
+/*
+ * This feature indicates that memory accesses by the driver and the
+ * device are ordered in a way described by the platform.
+ */
+#define ZXDH_F_ORDER_PLATFORM 36
+
+/* This marks a buffer as continuing via the next field. */
+#define VRING_DESC_F_NEXT 1
+/* This marks a buffer as write-only (otherwise read-only). */
+#define VRING_DESC_F_WRITE 2
+/* This means the buffer contains a list of buffer descriptors. */
+#define VRING_DESC_F_INDIRECT 4
+
+/*
+ * Mark a descriptor as available or used in packed ring.
+ * Notice: they are defined as shifts instead of shifted values.
+ */
+#define VRING_PACKED_DESC_F_AVAIL 7
+#define VRING_PACKED_DESC_F_USED 15
+
+/* The Host uses this in used->flags to advise the Guest: don't kick me when
+ * you add a buffer.  It's unreliable, so it's simply an optimization.  Guest
+ * will still kick if it's out of buffers. */
+#define VRING_USED_F_NO_NOTIFY 1
+/* The Guest uses this in avail->flags to advise the Host: don't interrupt me
+ * when you consume a buffer.  It's unreliable, so it's simply an
+ * optimization.  */
+#define VRING_AVAIL_F_NO_INTERRUPT 1
+
+/* Enable events in packed ring. */
+#define VRING_PACKED_EVENT_FLAG_ENABLE 0x0
+/* Disable events in packed ring. */
+#define VRING_PACKED_EVENT_FLAG_DISABLE 0x1
+/*
+ * Enable events for a specific descriptor in packed ring.
+ * (as specified by Descriptor Ring Change Event Offset/Wrap Counter).
+ * Only valid if ZXDH_RING_F_EVENT_IDX has been negotiated.
+ */
+#define VRING_PACKED_EVENT_FLAG_DESC 0x2
+
+/*
+ * Wrap counter bit shift in event suppression structure
+ * of packed ring.
+ */
+#define VRING_PACKED_EVENT_F_WRAP_CTR 15
+
+/* Alignment requirements for vring elements */
+#define VRING_AVAIL_ALIGN_SIZE 2
+#define VRING_USED_ALIGN_SIZE 4
+#define VRING_DESC_ALIGN_SIZE 16
+
+#define MRG_CTX_HEADER_SHIFT 22
+
+/* FIXME: MTU in config. */
+#define GOOD_PACKET_LEN (ETH_HLEN + VLAN_HLEN + ETH_DATA_LEN)
+#define GOOD_COPY_LEN 128
+
+#define TX_PORT_NP 0x00
+#define TX_PORT_DRS 0x01
+#define TX_PORT_DTP 0x02
+#define HDR_2B_UNIT 2
+#define ENABLE_PI_FLAG_32B 0x1
+#define DISABLE_PI_FIELD_PARSE 0x80
+#define IPV4_TYPE 0x0
+#define IPV6_TYPE 0x1
+#define NOT_IP_TYPE 0x2
+#define PKT_SRC_NP 0x0
+#define PKT_SRC_CPU 0x1
+#define PCODE_IP 0x1
+#define PCODE_TCP 0x2
+#define PCODE_UDP 0x3
+#define INVALID_ETH_PORT_ID 0xff
+#define ETH_MTU_4B_UNIT 4
+#define IP_FRG_CSUM_FLAG 0x8000
+#define NOT_IP_FRG_CSUM_FLAG 0x6000
+#define TCP_FRG_CSUM_FLAG 0x24
+#define NOT_TCP_FRG_CSUM_FLAG 0x30
+#define HDR_2B_UNIT 2
+
+#define HDR_BUFFER_LEN 100
+#define IP_BASE_HLEN 20
+#define IPV6_BASE_HLEN 40
+#define TCP_BASE_HLEN 20
+
+#define OUTER_IP_CHECKSUM_OFFSET (12)
+#define INNER_IP_CHECKSUM_OFFSET (15)
+#define INNER_L4_CHECKSUM_OFFSET (2)
+#define PI_HDR_L3_CHKSUM_ERROR_CODE (0x1)
+#define PI_HDR_L4_CHKSUM_ERROR_CODE (0x60)
+#define OUTER_IP_CHKSUM_ERROT_CODE (0x20)
+
+/* PD header offload flags */
+#define PANELID_EN (1 << 15)
+
+/* PD header sk_prio */
+#define ZXDH_DCBNL_SET_SK_PRIO(sk_prio) ((0x7 & sk_prio) << 8)
+
+/*
+ * __vqm{16,32,64} have the following meaning:
+ * - __u{16,32,64} for zxdh devices in legacy mode, accessed in native endian
+ * - __le{16,32,64} for standard-compliant zxdh devices
+ */
+typedef __u16 __bitwise __vqm16;
+typedef __u32 __bitwise __vqm32;
+typedef __u64 __bitwise __vqm64;
+
+/* Constants for MSI-X */
+/* Use first vector for configuration changes, second and the rest for
+ * virtqueues Thus, we need at least 2 vectors for MSI. */
+enum {
+	VP_MSIX_CONFIG_VECTOR = 0,
+	VP_MSIX_VQ_VECTOR = 1,
+};
+
+struct vring_packed_desc_event {
+	/* Descriptor Ring Change Event Offset/Wrap Counter. */
+	__le16 off_wrap;
+	/* Descriptor Ring Change Event Flags. */
+	__le16 flags;
+};
+
+struct vring_packed_desc {
+	/* Buffer Address. */
+	__le64 addr;
+	/* Buffer Length. */
+	__le32 len;
+	/* Buffer ID. */
+	__le16 id;
+	/* The flags depending on descriptor type. */
+	__le16 flags;
+};
+
+struct vring_desc_state_packed {
+	void *data; /* Data for callback. */
+	struct vring_packed_desc *indir_desc; /* Indirect descriptor, if any. */
+	uint16_t num; /* Descriptor list length. */
+	uint16_t last; /* The last desc state in a list. */
+};
+
+struct vring_desc_extra {
+	dma_addr_t addr; /* Buffer DMA addr. */
+	uint32_t len; /* Buffer length. */
+	uint16_t flags; /* Descriptor flags. */
+	uint16_t next; /* The next desc state in a list. */
+};
+
+union pkt_type_t {
+	uint8_t pkt_type;
+	struct {
+		uint8_t pkt_code : 5;
+		uint8_t pkt_src : 1;
+		uint8_t ip_type : 2;
+	} type_ctx;
+} __attribute__((packed));
+
+struct pi_net_hdr {
+	uint8_t bttl_pi_len;
+	union pkt_type_t pt;
+	uint16_t vlan_id;
+	uint32_t ipv6_exp_flags;
+	uint16_t hdr_l3_offset;
+	uint16_t hdr_l4_offset;
+	uint8_t eth_port_id;
+	uint8_t pkt_action_flag2;
+	uint16_t pkt_action_flag1;
+	uint8_t sa_index[8];
+	uint8_t error_code[2];
+	uint8_t rsv[6];
+} __attribute__((packed));
+
+struct pd_net_hdr_tx {
+#define TXCAP_STAG_INSERT_EN_BIT (1 << 14)
+#define TXCAP_CTAG_INSERT_EN_BIT (1 << 13)
+#define DELAY_STATISTICS_INSERT_EN_BIT (1 << 7)
+	uint16_t ol_flag;
+	uint8_t rsv;
+	uint8_t panel_id;
+	uint8_t tag_idx;
+	uint8_t tag_data;
+	uint16_t vfid;
+	struct {
+		uint16_t tpid;
+		uint16_t tci;
+	} svlan;
+	struct {
+		uint16_t tpid;
+		uint16_t tci;
+	} cvlan;
+} __attribute__((packed));
+
+struct pd_net_hdr_rx {
+#define RX_PD_HEAD_VLAN_STRIP_BIT (1 << 28)
+	uint32_t flags;
+	uint32_t rss_hash;
+	uint32_t fd;
+	uint16_t striped_stci;
+	uint16_t striped_ctci;
+	uint8_t tag_idx;
+	uint8_t tag_data;
+	uint16_t src_port;
+	uint16_t outer_pkt_type;
+	uint16_t inner_pkt_type;
+} __attribute__((packed));
+
+/* zxdh net header */
+struct zxdh_net_hdr {
+	uint8_t tx_port; // bit7:2 rsv; bit1:0 00:np, 01:DRS, 10:DTP
+	uint8_t pd_len; // bit7 rsv; bit6:0 L2报文前的描述符长度，以2B为单位
+	uint8_t num_buffers; //表示接收方向num buffers字段
+	uint8_t rsv; //保留
+
+	struct pi_net_hdr pi_hdr;
+	struct pd_net_hdr_tx pd_hdr;
+} __attribute__((packed));
+
+struct zxdh_net_1588_hdr {
+	uint8_t tx_port; // bit7:2 rsv; bit1:0 00:np, 01:DRS, 10:DTP
+	uint8_t pd_len; // bit7 rsv; bit6:0 L2报文前的描述符长度，以2B为单位
+	uint8_t num_buffers; //表示接收方向num buffers字段
+	uint8_t rsv; //保留
+
+	struct pi_net_hdr pi_hdr;
+	struct pd_net_hdr_tx pd_hdr;
+
+	uint8_t ptp_type[3]; /* 低bit0-16预留，bit17-19 pkt_type, bit23 ptp_udp */
+	uint8_t ts_offset;
+	uint32_t cpu_tx;
+	uint8_t port; /* egress_port/ingress_port, L4报文此字段无用 */
+	uint8_t rsv1[4];
+	uint8_t sec_1588_key[3];
+} __attribute__((packed));
+
+struct zxdh_net_hdr_rcv {
+	uint8_t tx_port; // bit7:2 rsv; bit1:0 00:np, 01:DRS, 10:DTP
+	uint8_t pd_len; // bit7 rsv; bit6:0 L2报文前的描述符长度，以2B为单位
+	uint8_t num_buffers; //表示接收方向num buffers字段
+	uint8_t rsv; //保留
+
+	struct pi_net_hdr pi_hdr;
+	struct pd_net_hdr_rx pd_hdr;
+} __attribute__((packed));
+
+struct zxdh_net_1588_hdr_rcv {
+	uint8_t tx_port; // bit7:2 rsv; bit1:0 00:np, 01:DRS, 10:DTP
+	uint8_t pd_len; // bit7 rsv; bit6:0 L2报文前的描述符长度，以2B为单位
+	uint8_t num_buffers; //表示接收方向num buffers字段
+	uint8_t rsv; //保留
+
+	struct pi_net_hdr pi_hdr;
+	struct pd_net_hdr_rx pd_hdr;
+
+	uint8_t egress_port;
+	/* 低bit0-8预留，bit9-11 pkt_type, bit 12-14预留，bit15 ptp_udp */
+	uint8_t ptp_type[2];
+	uint8_t ts_offset;
+	uint32_t rx_ts;
+} __attribute__((packed));
+
+#ifdef DEBUG
+/* For development, we want to crash whenever the ring is screwed. */
+#define BAD_RING(_vq, fmt, args...)                 \
+	do {                                            \
+		LOG_ERR("%s:" fmt, (_vq)->vq.name, ##args); \
+		BUG();                                      \
+	} while (0)
+/* Caller is supposed to guarantee no reentry. */
+#define START_USE(_vq)                                                \
+	do {                                                              \
+		if ((_vq)->in_use)                                            \
+			panic("%s:in_use = %i\n", (_vq)->vq.name, (_vq)->in_use); \
+		(_vq)->in_use = __LINE__;                                     \
+	} while (0)
+#define END_USE(_vq)            \
+	do {                        \
+		BUG_ON(!(_vq)->in_use); \
+		(_vq)->in_use = 0;      \
+	} while (0)
+#define LAST_ADD_TIME_UPDATE(_vq)                                             \
+	do {                                                                      \
+		ktime_t now = ktime_get();                                            \
+		/* No kick or get, with .1 second between?  Warn. */                  \
+		if ((_vq)->last_add_time_valid)                                       \
+			WARN_ON(ktime_to_ms(ktime_sub(now, (_vq)->last_add_time)) > 100); \
+		(_vq)->last_add_time = now;                                           \
+		(_vq)->last_add_time_valid = true;                                    \
+	} while (0)
+#define LAST_ADD_TIME_CHECK(_vq)                                         \
+	do {                                                                 \
+		if ((_vq)->last_add_time_valid) {                                \
+			WARN_ON(ktime_to_ms(ktime_sub(ktime_get(),                   \
+										  (_vq)->last_add_time)) > 100); \
+		}                                                                \
+	} while (0)
+#define LAST_ADD_TIME_INVALID(_vq) ((_vq)->last_add_time_valid = false)
+#else
+#define BAD_RING(_vq, fmt, args...)                 \
+	do {                                            \
+		LOG_ERR("%s:" fmt, (_vq)->vq.name, ##args); \
+		(_vq)->broken = true;                       \
+	} while (0)
+#define START_USE(vq)
+#define END_USE(vq)
+#define LAST_ADD_TIME_UPDATE(vq)
+#define LAST_ADD_TIME_CHECK(vq)
+#define LAST_ADD_TIME_INVALID(vq)
+#endif
+
+#define vqm_store_mb(weak_barriers, p, v) \
+	do {                                  \
+		if (weak_barriers) {              \
+			virt_store_mb(*p, v);         \
+		} else {                          \
+			WRITE_ONCE(*p, v);            \
+			mb();                         \
+		}                                 \
+	} while (0)
+
+/* This is the PCI capability header: */
+struct zxdh_pci_cap {
+	__u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */
+	__u8 cap_next; /* Generic PCI field: next ptr. */
+	__u8 cap_len; /* Generic PCI field: capability length */
+	__u8 cfg_type; /* Identifies the structure. */
+	__u8 bar; /* Where to find it. */
+	__u8 id; /* Multiple capabilities of the same type */
+	__u8 padding[2]; /* Pad to full dword. */
+	__le32 offset; /* Offset within bar. */
+	__le32 length; /* Length of the structure, in bytes. */
+};
+
+struct zxdh_pci_notify_cap {
+	struct zxdh_pci_cap cap;
+	__le32 notify_off_multiplier; /* Multiplier for queue_notify_off. */
+};
+
+struct virtqueue {
+	struct list_head list;
+	void (*callback)(struct virtqueue *vq);
+	const char *name;
+	struct net_device *vdev;
+	uint32_t index;
+	uint32_t phy_index;
+	uint32_t num_free;
+	void *priv;
+};
+
+/* custom queue ring descriptors: 16 bytes. These can chain together via "next".
+ */
+struct vring_desc {
+	/* Address (guest-physical). */
+	uint64_t addr;
+	/* Length. */
+	uint32_t len;
+	/* The flags as indicated above. */
+	uint16_t flags;
+	/* We chain unused descriptors via this, too */
+	uint16_t next;
+};
+
+struct vring_avail {
+	uint16_t flags;
+	uint16_t idx;
+	uint16_t ring[];
+};
+
+/* u32 is used here for ids for padding reasons. */
+struct vring_used_elem {
+	/* Index of start of used descriptor chain. */
+	uint32_t id;
+	/* Total length of the descriptor chain which was used (written to) */
+	uint32_t len;
+};
+
+typedef struct vring_used_elem __attribute__((aligned(VRING_USED_ALIGN_SIZE)))
+vring_used_elem_t;
+
+struct vring_used {
+	uint16_t flags;
+	uint16_t idx;
+	vring_used_elem_t ring[];
+};
+
+typedef struct vring_desc __attribute__((aligned(VRING_DESC_ALIGN_SIZE)))
+vring_desc_t;
+typedef struct vring_avail __attribute__((aligned(VRING_AVAIL_ALIGN_SIZE)))
+vring_avail_t;
+typedef struct vring_used __attribute__((aligned(VRING_USED_ALIGN_SIZE)))
+vring_used_t;
+
+struct vring {
+	uint32_t num;
+
+	vring_desc_t *desc;
+
+	vring_avail_t *avail;
+
+	vring_used_t *used;
+};
+
+struct vring_virtqueue {
+	struct virtqueue vq;
+
+	/* Is this a packed ring? */
+	bool packed_ring;
+
+	/* Is DMA API used? */
+	bool use_dma_api;
+
+	/* Can we use weak barriers? */
+	bool weak_barriers;
+
+	/* Other side has made a mess, don't try any more. */
+	bool broken;
+
+	/* Host supports indirect buffers */
+	bool indirect;
+
+	/* Host publishes avail event idx */
+	bool event;
+
+	/* Head of free buffer list. */
+	uint32_t free_head;
+	/* Number we've added since last sync. */
+	uint32_t num_added;
+
+	/* Last used index we've seen. */
+	uint16_t last_used_idx;
+
+	/* Hint for event idx: already triggered no need to disable. */
+	bool event_triggered;
+
+	/* Available for packed ring */
+	struct {
+		/* Actual memory layout for this queue. */
+		struct {
+			uint32_t num;
+			struct vring_packed_desc *desc;
+			struct vring_packed_desc_event *driver;
+			struct vring_packed_desc_event *device;
+		} vring;
+
+		/* Driver ring wrap counter. */
+		bool avail_wrap_counter;
+
+		/* Device ring wrap counter. */
+		bool used_wrap_counter;
+
+		/* Avail used flags. */
+		uint16_t avail_used_flags;
+
+		/* Index of the next avail descriptor. */
+		uint16_t next_avail_idx;
+
+		/*
+     * Last written value to driver->flags in
+     * guest byte order.
+     */
+		uint16_t event_flags_shadow;
+
+		/* Per-descriptor state. */
+		struct vring_desc_state_packed *desc_state;
+		struct vring_desc_extra *desc_extra;
+
+		/* DMA address and size information */
+		dma_addr_t ring_dma_addr;
+		dma_addr_t driver_event_dma_addr;
+		dma_addr_t device_event_dma_addr;
+		size_t ring_size_in_bytes;
+		size_t event_size_in_bytes;
+	} packed;
+
+	/* How to notify other side. FIXME: commonalize hcalls! */
+	bool (*notify)(struct virtqueue *vq);
+
+	/* DMA, allocation, and size information */
+	bool we_own_ring;
+
+#ifdef DEBUG
+	/* They're supposed to lock for us. */
+	uint32_t in_use;
+
+	/* Figure out if their kicks are too delayed. */
+	bool last_add_time_valid;
+	ktime_t last_add_time;
+#endif
+};
+
+struct zxdh_pci_vq_info {
+	/* the actual virtqueue */
+	struct virtqueue *vq;
+
+	/* the list node for the virtqueues list */
+	struct list_head node;
+
+	/* channel num map 1-1 to vector*/
+	unsigned channel_num;
+};
+
+struct virtnet_stat_desc {
+	char desc[ETH_GSTRING_LEN];
+	size_t offset;
+};
+
+struct virtnet_sq_stats {
+	struct u64_stats_sync syncp;
+	uint64_t packets;
+	uint64_t bytes;
+	uint64_t xdp_tx;
+	uint64_t xdp_tx_drops;
+	uint64_t kicks;
+	uint64_t tx_timeouts;
+};
+
+struct virtnet_rq_stats {
+	struct u64_stats_sync syncp;
+	uint64_t packets;
+	uint64_t bytes;
+	uint64_t drops;
+	uint64_t xdp_packets;
+	uint64_t xdp_tx;
+	uint64_t xdp_redirects;
+	uint64_t xdp_drops;
+	uint64_t kicks;
+};
+#define VIRTNET_SQ_STAT(m) offsetof(struct virtnet_sq_stats, m)
+#define VIRTNET_RQ_STAT(m) offsetof(struct virtnet_rq_stats, m)
+
+static const struct virtnet_stat_desc virtnet_sq_stats_desc[] = {
+	{ "packets", VIRTNET_SQ_STAT(packets) },
+	{ "bytes", VIRTNET_SQ_STAT(bytes) },
+	{ "xdp_tx", VIRTNET_SQ_STAT(xdp_tx) },
+	{ "xdp_tx_drops", VIRTNET_SQ_STAT(xdp_tx_drops) },
+	{ "kicks", VIRTNET_SQ_STAT(kicks) },
+	{ "tx_timeouts", VIRTNET_SQ_STAT(tx_timeouts) },
+};
+
+static const struct virtnet_stat_desc virtnet_rq_stats_desc[] = {
+	{ "packets", VIRTNET_RQ_STAT(packets) },
+	{ "bytes", VIRTNET_RQ_STAT(bytes) },
+	{ "drops", VIRTNET_RQ_STAT(drops) },
+	{ "xdp_packets", VIRTNET_RQ_STAT(xdp_packets) },
+	{ "xdp_tx", VIRTNET_RQ_STAT(xdp_tx) },
+	{ "xdp_redirects", VIRTNET_RQ_STAT(xdp_redirects) },
+	{ "xdp_drops", VIRTNET_RQ_STAT(xdp_drops) },
+	{ "kicks", VIRTNET_RQ_STAT(kicks) },
+};
+
+#define VIRTNET_SQ_STATS_LEN ARRAY_SIZE(virtnet_sq_stats_desc)
+#define VIRTNET_RQ_STATS_LEN ARRAY_SIZE(virtnet_rq_stats_desc)
+
+/* RX packet size EWMA. The average packet size is used to determine the packet
+ * buffer size when refilling RX rings. As the entire RX ring may be refilled
+ * at once, the weight is chosen so that the EWMA will be insensitive to short-
+ * term, transient changes in packet size.
+ */
+DECLARE_EWMA(pkt_len, 0, 64)
+
+/* Internal representation of a send virtqueue */
+struct send_queue {
+	/* Virtqueue associated with this send _queue */
+	struct virtqueue *vq;
+
+	/* TX: fragments + linear part + custom queue header */
+	struct scatterlist sg[MAX_SKB_FRAGS + 2];
+
+	/* Name of the send queue: output.$index */
+	char name[40];
+
+	struct virtnet_sq_stats stats;
+
+	struct napi_struct napi;
+
+	uint8_t hdr_buf[HDR_BUFFER_LEN];
+};
+
+/* Internal representation of a receive virtqueue */
+struct receive_queue {
+	/* Virtqueue associated with this receive_queue */
+	struct virtqueue *vq;
+
+	struct napi_struct napi;
+
+	struct bpf_prog __rcu *xdp_prog;
+
+	struct virtnet_rq_stats stats;
+
+	/* Chain pages by the private ptr. */
+	struct page *pages;
+
+	/* Average packet length for mergeable receive buffers. */
+	struct ewma_pkt_len mrg_avg_pkt_len; // todo
+
+	/* Page frag for packet buffer allocation. */
+	struct page_frag alloc_frag;
+
+	/* RX: fragments + linear part + custom queue header */
+	struct scatterlist sg[MAX_SKB_FRAGS + 2];
+
+	/* Min single buffer size for mergeable buffers case. */
+	uint32_t min_buf_len;
+
+	/* Name of this receive queue: input.$index */
+	char name[40];
+
+	struct xdp_rxq_info xdp_rxq;
+};
+
+#define to_vvq(_vq) container_of(_vq, struct vring_virtqueue, vq)
+
+typedef void vq_callback_t(struct virtqueue *);
+
+void zxdh_print_vring_info(struct virtqueue *vq, uint32_t desc_index,
+						   uint32_t desc_num);
+void virtnet_napi_enable(struct virtqueue *vq, struct napi_struct *napi);
+void virtnet_napi_tx_enable(struct net_device *netdev, struct virtqueue *vq,
+							struct napi_struct *napi);
+void virtnet_napi_tx_disable(struct napi_struct *napi);
+void refill_work(struct work_struct *work);
+int virtnet_poll(struct napi_struct *napi, int budget);
+int virtnet_poll_tx(struct napi_struct *napi, int budget);
+int32_t txq2vq(int32_t txq);
+int32_t rxq2vq(int32_t rxq);
+uint16_t vqm16_to_cpu(struct net_device *netdev, __vqm16 val);
+uint8_t vp_get_status(struct net_device *netdev);
+void vp_set_status(struct net_device *netdev, uint8_t status);
+void vp_set_reset_status(struct net_device *netdev, uint8_t status);
+void zxdh_add_status(struct net_device *netdev, uint32_t status);
+void zxdh_vp_enable_cbs(struct net_device *netdev);
+void zxdh_vp_disable_cbs(struct net_device *netdev);
+void zxdh_vp_reset(struct net_device *netdev);
+void vring_free_queue(struct net_device *netdev, size_t size, void *queue,
+					  dma_addr_t dma_handle);
+netdev_tx_t start_xmit(struct sk_buff *skb, struct net_device *netdev);
+bool try_fill_recv(struct net_device *netdev, struct receive_queue *rq,
+				   gfp_t gfp);
+inline struct zxdh_net_hdr *skb_vnet_hdr(struct sk_buff *skb);
+int32_t virtqueue_add_outbuf(struct virtqueue *vq, struct scatterlist *sg,
+							 uint32_t num, void *data, gfp_t gfp);
+void virtqueue_disable_cb(struct virtqueue *_vq);
+void free_old_xmit_skbs(struct net_device *netdev, struct send_queue *sq,
+						bool in_napi);
+bool virtqueue_enable_cb_delayed(struct virtqueue *_vq);
+bool virtqueue_kick_prepare_packed(struct virtqueue *_vq);
+bool virtqueue_notify(struct virtqueue *_vq);
+void zxdh_pf_features_init(struct net_device *netdev);
+bool zxdh_has_feature(struct net_device *netdev, uint32_t fbit);
+bool zxdh_has_status(struct net_device *netdev, uint32_t sbit);
+void zxdh_free_unused_bufs(struct net_device *netdev);
+void zxdh_free_receive_bufs(struct net_device *netdev);
+void zxdh_free_receive_page_frags(struct net_device *netdev);
+void zxdh_virtnet_del_vqs(struct net_device *netdev);
+void zxdh_vqs_uninit(struct net_device *netdev);
+int32_t zxdh_vqs_init(struct net_device *netdev);
+int32_t dh_eq_vqs_vring_int(struct notifier_block *nb, unsigned long action,
+							void *data);
+int32_t vq2rxq(struct virtqueue *vq);
+void *virtqueue_get_buf(struct virtqueue *_vq, uint32_t *len);
+void *virtqueue_get_buf_ctx_packed(struct virtqueue *_vq, uint32_t *len,
+								   void **ctx);
+uint32_t virtqueue_get_vring_size(struct virtqueue *_vq);
+void virtqueue_napi_complete(struct napi_struct *napi, struct virtqueue *vq,
+							 int32_t processed);
+int32_t virtqueue_add_inbuf_ctx(struct virtqueue *vq, struct scatterlist *sg,
+								uint32_t num, void *data, void *ctx, gfp_t gfp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_ethtool/ethtool.c b/src/net/drivers/net/ethernet/dinghai/en_ethtool/ethtool.c
index 3794403df3383bac7aa3c0158f1b80aa4edc00ea..2ce0f226f1ec22aa731e18d3550295d178f883d4 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_ethtool/ethtool.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_ethtool/ethtool.c
@@ -22,1363 +22,1316 @@ MODULE_LICENSE("Dual BSD/GPL");
 #define MAX_DRV_VERSION_LEN 32
 #define PCI_BUS(PCI_BDF) ((PCI_BDF >> 8) & 0xff)
 
-#define ZXDH_EN_LINK_MODE_ADD(ks, name, sup)                             \
-do                                                                       \
-{                                                                        \
-    if (sup)                                                             \
-    {                                                                    \
-        ethtool_link_ksettings_add_link_mode((ks), supported, name);     \
-    }                                                                    \
-    else                                                                 \
-    {                                                                    \
-        ethtool_link_ksettings_add_link_mode((ks), advertising, name);   \
-    }                                                                    \
-} while (0)
-
-#define ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, bit, sup)              \
-    sup ? ((en_dev->supported_speed_modes) & BIT(bit)) == BIT(bit) : \
-    ((en_dev->advertising_speed_modes) & BIT(bit)) == BIT(bit)
-
-#define GET_FEC_LINK_FLAG  (0)
-#define GET_FEC_CFG_FLAG   (1)
-#define GET_FEC_CAP_FLAG   (2)
-
-static const uint32_t fec_2_ethtool_fecparam[] =
-{
-    [SPM_FEC_NONE] = ETHTOOL_FEC_OFF,
-    [SPM_FEC_BASER] = ETHTOOL_FEC_BASER,
-    [SPM_FEC_RS528] = ETHTOOL_FEC_RS,
-    [SPM_FEC_RS544] = ETHTOOL_FEC_RS,
+#define ZXDH_EN_LINK_MODE_ADD(ks, name, sup)                               \
+	do {                                                                   \
+		if (sup) {                                                         \
+			ethtool_link_ksettings_add_link_mode((ks), supported, name);   \
+		} else {                                                           \
+			ethtool_link_ksettings_add_link_mode((ks), advertising, name); \
+		}                                                                  \
+	} while (0)
+
+#define ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, bit, sup)               \
+	(sup ? ((en_dev->supported_speed_modes) & BIT(bit)) == BIT(bit) : \
+			 ((en_dev->advertising_speed_modes) & BIT(bit)) == BIT(bit))
+
+#define GET_FEC_LINK_FLAG (0)
+#define GET_FEC_CFG_FLAG (1)
+#define GET_FEC_CAP_FLAG (2)
+
+static const uint32_t fec_2_ethtool_fecparam[] = {
+	[SPM_FEC_NONE] = ETHTOOL_FEC_OFF,
+	[SPM_FEC_BASER] = ETHTOOL_FEC_BASER,
+	[SPM_FEC_RS528] = ETHTOOL_FEC_RS,
+	[SPM_FEC_RS544] = ETHTOOL_FEC_RS,
 };
 
-static uint32_t zxdh_en_fec_to_ethtool_fecparam(uint32_t fec_mode, uint32_t flag)
+static uint32_t zxdh_en_fec_to_ethtool_fecparam(uint32_t fec_mode,
+												uint32_t flag)
 {
-    int32_t i;
-    uint32_t fecparam_cap = 0;
+	int32_t i;
+	uint32_t fecparam_cap = 0;
 
-    if(!fec_mode)
-    {
-        if(flag == GET_FEC_LINK_FLAG)
-            return ETHTOOL_FEC_NONE;
-        else if(flag == GET_FEC_CFG_FLAG)
-            return ETHTOOL_FEC_AUTO;
-    }
+	if (!fec_mode) {
+		if (flag == GET_FEC_LINK_FLAG)
+			return ETHTOOL_FEC_NONE;
+		else if (flag == GET_FEC_CFG_FLAG)
+			return ETHTOOL_FEC_AUTO;
+	}
 
-    for(i = 0; i < ARRAY_SIZE(fec_2_ethtool_fecparam); i++)
-    {
-        if(fec_mode & BIT(i))
-        {
-            fecparam_cap |= fec_2_ethtool_fecparam[i];
-        }
-    }
+	for (i = 0; i < ARRAY_SIZE(fec_2_ethtool_fecparam); i++) {
+		if (fec_mode & BIT(i)) {
+			fecparam_cap |= fec_2_ethtool_fecparam[i];
+		}
+	}
 
-    if(flag == GET_FEC_CAP_FLAG)
-        fecparam_cap |= ETHTOOL_FEC_AUTO;
+	if (flag == GET_FEC_CAP_FLAG)
+		fecparam_cap |= ETHTOOL_FEC_AUTO;
 
-    return fecparam_cap;
+	return fecparam_cap;
 }
 
 static void zxdh_en_fec_to_link_ksettings(uint32_t fec_mode,
-                                          struct ethtool_link_ksettings *ks,
-                                          bool sup)
+										  struct ethtool_link_ksettings *ks,
+										  bool sup)
 {
-    if(fec_mode & BIT(SPM_FEC_NONE))
-        ZXDH_EN_LINK_MODE_ADD(ks, FEC_NONE, sup);
-    if(fec_mode & BIT(SPM_FEC_BASER))
-        ZXDH_EN_LINK_MODE_ADD(ks, FEC_BASER, sup);
-    if(fec_mode & BIT(SPM_FEC_RS528) ||
-       fec_mode & BIT(SPM_FEC_RS544))
-        ZXDH_EN_LINK_MODE_ADD(ks, FEC_RS, sup);
+	if (fec_mode & BIT(SPM_FEC_NONE))
+		ZXDH_EN_LINK_MODE_ADD(ks, FEC_NONE, sup);
+	if (fec_mode & BIT(SPM_FEC_BASER))
+		ZXDH_EN_LINK_MODE_ADD(ks, FEC_BASER, sup);
+	if (fec_mode & BIT(SPM_FEC_RS528) || fec_mode & BIT(SPM_FEC_RS544))
+		ZXDH_EN_LINK_MODE_ADD(ks, FEC_RS, sup);
 }
 
 static void zxdh_en_fec_link_ksettings_get(struct zxdh_en_device *en_dev,
-                                              struct ethtool_link_ksettings *ks)
+										   struct ethtool_link_ksettings *ks)
 {
-    int32_t ret;
-    uint32_t fec_cap;
-    uint32_t fec_active;
+	int32_t ret;
+	uint32_t fec_cap;
+	uint32_t fec_active;
 
-    ret = zxdh_en_fec_mode_get(en_dev, &fec_cap, NULL, &fec_active);
-    if(ret)
-    {
-        LOG_ERR("zxdh_en_fec_mode_get failed!\n");
-        return;
-    }
-    //LOG_INFO("fec_cap=0x%x, fec_active=0x%x\n", fec_cap, fec_active);
+	ret = zxdh_en_fec_mode_get(en_dev, &fec_cap, NULL, &fec_active);
+	if (ret) {
+		LOG_ERR("zxdh_en_fec_mode_get failed!\n");
+		return;
+	}
+	// LOG_INFO("fec_cap=0x%x, fec_active=0x%x\n", fec_cap, fec_active);
 
-    zxdh_en_fec_to_link_ksettings(fec_cap, ks, true);
-    zxdh_en_fec_to_link_ksettings(fec_active, ks, false);
+	zxdh_en_fec_to_link_ksettings(fec_cap, ks, true);
+	zxdh_en_fec_to_link_ksettings(fec_active, ks, false);
 
-    return;
+	return;
 }
 
 static void zxdh_en_pause_link_ksettings_get(struct zxdh_en_device *en_dev,
-                                             struct ethtool_link_ksettings *ks)
-{
-    int32_t err;
-    uint32_t fc_mode;
-
-    err = zxdh_en_fc_mode_get(en_dev, &fc_mode);
-    if(err != 0)
-    {
-        LOG_ERR("zxdh_en_fc_mode_get failed!\n");
-        return;
-    }
-
-    ZXDH_EN_LINK_MODE_ADD(ks, Pause, true);
-
-    if(fc_mode == BIT(SPM_FC_PAUSE_FULL))
-        ZXDH_EN_LINK_MODE_ADD(ks, Pause, false);
-    else if(fc_mode == BIT(SPM_FC_PAUSE_RX) || fc_mode == BIT(SPM_FC_PAUSE_TX))
-        ZXDH_EN_LINK_MODE_ADD(ks, Asym_Pause, false);
-
-    return;
-}
-
-static void zxdh_en_phytype_to_ethtool(struct zxdh_en_device *en_dev, struct ethtool_link_ksettings *ks, bool sup)
-{
-    //0x20000020020
-    if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_1X_1G, sup))
-    {
-        ZXDH_EN_LINK_MODE_ADD(ks, 1000baseT_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 1000baseKX_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 1000baseX_Full, sup);
-    }
-
-    //0x5C0000081000
-    if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_1X_10G, sup))
-    {
-        ZXDH_EN_LINK_MODE_ADD(ks, 10000baseT_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 10000baseKR_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 10000baseCR_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 10000baseSR_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 10000baseLR_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 10000baseER_Full, sup);
-    }
-
-    //0x380000000
-    if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_1X_25G, sup))
-    {
-        ZXDH_EN_LINK_MODE_ADD(ks, 25000baseCR_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 25000baseKR_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 25000baseSR_Full, sup);
-    }
-
-    //0x10C00000000
-    if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_1X_50G, sup))
-    {
-        ZXDH_EN_LINK_MODE_ADD(ks, 50000baseCR2_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 50000baseKR2_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 50000baseSR2_Full, sup);
-    }
-
-    //0x7800000
-    if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_4X_40G, sup))
-    {
-        ZXDH_EN_LINK_MODE_ADD(ks, 40000baseKR4_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 40000baseCR4_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 40000baseSR4_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 40000baseLR4_Full, sup);
-    }
-
-    //0xF000000000
-    if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_4X_100G, sup))
-    {
-        ZXDH_EN_LINK_MODE_ADD(ks, 100000baseKR4_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 100000baseSR4_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 100000baseCR4_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 100000baseLR4_ER4_Full, sup);
-    }
-
-    //0x1E00000000000000
-    if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_2X_100G, sup))
-    {
-        ZXDH_EN_LINK_MODE_ADD(ks, 100000baseKR2_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 100000baseSR2_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 100000baseCR2_Full, sup);
-        ZXDH_EN_LINK_MODE_ADD(ks, 100000baseLR2_ER2_FR2_Full, sup);
-    }
-
-    return;
-}
-
-static void zxdh_en_ethtool_to_phytype(struct ethtool_link_ksettings *ks, uint32_t *speed_modes)
-{
-    if (ethtool_link_ksettings_test_link_mode(ks, advertising, 1000baseT_Full))
-    {
-        *speed_modes |= BIT(SPM_SPEED_1X_1G);
-    }
-
-    if (ethtool_link_ksettings_test_link_mode(ks, advertising, 10000baseT_Full))
-    {
-        *speed_modes |= BIT(SPM_SPEED_1X_10G);
-    }
-
-    if (ethtool_link_ksettings_test_link_mode(ks, advertising, 25000baseCR_Full))
-    {
-        *speed_modes |= BIT(SPM_SPEED_1X_25G);
-    }
-
-    if (ethtool_link_ksettings_test_link_mode(ks, advertising, 50000baseCR2_Full))
-    {
-        *speed_modes |= BIT(SPM_SPEED_1X_50G);
-    }
-
-    if (ethtool_link_ksettings_test_link_mode(ks, advertising, 40000baseKR4_Full))
-    {
-        *speed_modes |= BIT(SPM_SPEED_4X_40G);
-    }
-
-    if (ethtool_link_ksettings_test_link_mode(ks, advertising, 100000baseKR4_Full))
-    {
-        *speed_modes |= BIT(SPM_SPEED_4X_100G);
-    }
-
-    if (ethtool_link_ksettings_test_link_mode(ks, advertising, 100000baseKR2_Full))
-    {
-        *speed_modes |= BIT(SPM_SPEED_2X_100G);
-    }
-
-    return;
-}
-
-static int32_t zxdh_en_speed_to_speed_modes(uint32_t speed, uint32_t *speed_modes, uint32_t sup_modes)
-{
-    switch (speed)
-    {
-        case SPEED_1000:
-        {
-            *speed_modes |= BIT(SPM_SPEED_1X_1G);
-            break;
-        }
-        case SPEED_10000:
-        {
-            *speed_modes |= BIT(SPM_SPEED_1X_10G);
-            break;
-        }
-        case SPEED_25000:
-        {
-            *speed_modes |= BIT(SPM_SPEED_1X_25G);
-            break;
-        }
-        case SPEED_40000:
-        {
-            *speed_modes |= BIT(SPM_SPEED_4X_40G);
-            break;
-        }
-        case SPEED_50000:
-        {
-            *speed_modes |= BIT(SPM_SPEED_1X_50G);
-            break;
-        }
-        case SPEED_100000:
-        {
-            *speed_modes |= BIT(SPM_SPEED_2X_100G);
-            *speed_modes |= BIT(SPM_SPEED_4X_100G);
-            break;
-        }
-        default:
-        {
-            return -EINVAL;
-        }
-    }
-
-    *speed_modes &= sup_modes;
-    if (*speed_modes == 0)
-    {
-        return -EINVAL;
-    }
-
-    return 0;
+											 struct ethtool_link_ksettings *ks)
+{
+	int32_t err;
+	uint32_t fc_mode;
+
+	err = zxdh_en_fc_mode_get(en_dev, &fc_mode);
+	if (err != 0) {
+		LOG_ERR("zxdh_en_fc_mode_get failed!\n");
+		return;
+	}
+
+	ZXDH_EN_LINK_MODE_ADD(ks, Pause, true);
+
+	if (fc_mode == BIT(SPM_FC_PAUSE_FULL))
+		ZXDH_EN_LINK_MODE_ADD(ks, Pause, false);
+	else if (fc_mode == BIT(SPM_FC_PAUSE_RX) || fc_mode == BIT(SPM_FC_PAUSE_TX))
+		ZXDH_EN_LINK_MODE_ADD(ks, Asym_Pause, false);
+
+	return;
+}
+
+static void zxdh_en_phytype_to_ethtool(struct zxdh_en_device *en_dev,
+									   struct ethtool_link_ksettings *ks,
+									   bool sup)
+{
+	// 0x20000020020
+	if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_1X_1G, sup)) {
+		ZXDH_EN_LINK_MODE_ADD(ks, 1000baseT_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 1000baseKX_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 1000baseX_Full, sup);
+	}
+
+	// 0x5C0000081000
+	if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_1X_10G, sup)) {
+		ZXDH_EN_LINK_MODE_ADD(ks, 10000baseT_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 10000baseKR_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 10000baseCR_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 10000baseSR_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 10000baseLR_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 10000baseER_Full, sup);
+	}
+
+	// 0x380000000
+	if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_1X_25G, sup)) {
+		ZXDH_EN_LINK_MODE_ADD(ks, 25000baseCR_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 25000baseKR_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 25000baseSR_Full, sup);
+	}
+
+	// 0x10C00000000
+	if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_1X_50G, sup)) {
+		ZXDH_EN_LINK_MODE_ADD(ks, 50000baseCR2_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 50000baseKR2_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 50000baseSR2_Full, sup);
+	}
+
+	// 0x7800000
+	if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_4X_40G, sup)) {
+		ZXDH_EN_LINK_MODE_ADD(ks, 40000baseKR4_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 40000baseCR4_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 40000baseSR4_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 40000baseLR4_Full, sup);
+	}
+
+	// 0xF000000000
+	if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_4X_100G, sup)) {
+		ZXDH_EN_LINK_MODE_ADD(ks, 100000baseKR4_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 100000baseSR4_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 100000baseCR4_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 100000baseLR4_ER4_Full, sup);
+	}
+
+	// 0x1E00000000000000
+	if (ZXDH_EN_SPEED_MODE_TO_ETHTOOL(en_dev, SPM_SPEED_2X_100G, sup)) {
+		ZXDH_EN_LINK_MODE_ADD(ks, 100000baseKR2_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 100000baseSR2_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 100000baseCR2_Full, sup);
+		ZXDH_EN_LINK_MODE_ADD(ks, 100000baseLR2_ER2_FR2_Full, sup);
+	}
+
+	return;
+}
+
+static void zxdh_en_ethtool_to_phytype(struct ethtool_link_ksettings *ks,
+									   uint32_t *speed_modes)
+{
+	if (ethtool_link_ksettings_test_link_mode(ks, advertising,
+											  1000baseT_Full)) {
+		*speed_modes |= BIT(SPM_SPEED_1X_1G);
+	}
+
+	if (ethtool_link_ksettings_test_link_mode(ks, advertising,
+											  10000baseT_Full)) {
+		*speed_modes |= BIT(SPM_SPEED_1X_10G);
+	}
+
+	if (ethtool_link_ksettings_test_link_mode(ks, advertising,
+											  25000baseCR_Full)) {
+		*speed_modes |= BIT(SPM_SPEED_1X_25G);
+	}
+
+	if (ethtool_link_ksettings_test_link_mode(ks, advertising,
+											  50000baseCR2_Full)) {
+		*speed_modes |= BIT(SPM_SPEED_1X_50G);
+	}
+
+	if (ethtool_link_ksettings_test_link_mode(ks, advertising,
+											  40000baseKR4_Full)) {
+		*speed_modes |= BIT(SPM_SPEED_4X_40G);
+	}
+
+	if (ethtool_link_ksettings_test_link_mode(ks, advertising,
+											  100000baseKR4_Full)) {
+		*speed_modes |= BIT(SPM_SPEED_4X_100G);
+	}
+
+	if (ethtool_link_ksettings_test_link_mode(ks, advertising,
+											  100000baseKR2_Full)) {
+		*speed_modes |= BIT(SPM_SPEED_2X_100G);
+	}
+
+	return;
+}
+
+static int32_t zxdh_en_speed_to_speed_modes(uint32_t speed,
+											uint32_t *speed_modes,
+											uint32_t sup_modes)
+{
+	switch (speed) {
+	case SPEED_1000: {
+		*speed_modes |= BIT(SPM_SPEED_1X_1G);
+		break;
+	}
+	case SPEED_10000: {
+		*speed_modes |= BIT(SPM_SPEED_1X_10G);
+		break;
+	}
+	case SPEED_25000: {
+		*speed_modes |= BIT(SPM_SPEED_1X_25G);
+		break;
+	}
+	case SPEED_40000: {
+		*speed_modes |= BIT(SPM_SPEED_4X_40G);
+		break;
+	}
+	case SPEED_50000: {
+		*speed_modes |= BIT(SPM_SPEED_1X_50G);
+		break;
+	}
+	case SPEED_100000: {
+		*speed_modes |= BIT(SPM_SPEED_2X_100G);
+		*speed_modes |= BIT(SPM_SPEED_4X_100G);
+		break;
+	}
+	default: {
+		return -EINVAL;
+	}
+	}
+
+	*speed_modes &= sup_modes;
+	if (*speed_modes == 0) {
+		return -EINVAL;
+	}
+
+	return 0;
 }
 
 static int32_t zxdh_en_get_link_ksettings(struct net_device *netdev,
-                                struct ethtool_link_ksettings *ks)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    ethtool_link_ksettings_zero_link_mode(ks, supported);
-    ethtool_link_ksettings_zero_link_mode(ks, advertising);
-
-    ks->base.port = PORT_FIBRE;
-    ks->base.autoneg = en_dev->autoneg_enable;
-    ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE);
-    ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
-
-    if (en_dev->autoneg_enable == AUTONEG_ENABLE)
-    {
-        ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
-    }
-
-    ks->base.speed = en_dev->speed;
-    if ((!netif_running(netdev)) || (!netif_carrier_ok(netdev)))
-    {
-        ks->base.speed = SPEED_UNKNOWN;
-    }
-    ks->base.duplex = ks->base.speed == SPEED_UNKNOWN ? DUPLEX_UNKNOWN : DUPLEX_FULL;
-
-    zxdh_en_phytype_to_ethtool(en_dev, ks, true);
-    zxdh_en_phytype_to_ethtool(en_dev, ks, false);
-
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        zxdh_en_fec_link_ksettings_get(en_dev, ks);
-        zxdh_en_pause_link_ksettings_get(en_dev, ks);
-    }
-
-    return 0;
-}
-
-static int32_t zxdh_en_set_link_ksettings(struct net_device *netdev,
-                                    const struct ethtool_link_ksettings *ks)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct ethtool_link_ksettings safe_ks;
-    uint32_t advertising_link_modes = 0;
-    uint32_t off_speed_modes = 0;
-    uint32_t on_speed_modes = 0;
-    int32_t err = 0;
-
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-    {
-        return 0;
-    }
-    if (ks->base.duplex == DUPLEX_HALF)
-    {
-        return -ENAVAIL;
-    }
-
-    memset(&safe_ks, 0, sizeof(safe_ks));
-    ethtool_link_ksettings_zero_link_mode(&safe_ks, supported);
-    ethtool_link_ksettings_zero_link_mode(&safe_ks, advertising);
-
-    if (ks->base.autoneg == AUTONEG_DISABLE)
-    {
-        err = zxdh_en_speed_to_speed_modes(ks->base.speed, &off_speed_modes,
-                                        en_dev->supported_speed_modes);
-        LOG_DEBUG("set speed: %d, off_speed_modes: 0x%x\n", ks->base.speed, off_speed_modes);
-        if (err != 0)
-        {
-            LOG_ERR("zxdh_en_speed_to_speed_mode failed: %d\n", err);
-            return -EOPNOTSUPP;
-        }
-
-        advertising_link_modes = off_speed_modes;
-    }
-    else
-    {
-        zxdh_en_phytype_to_ethtool(en_dev, &safe_ks, true);
-        if (!bitmap_intersects(ks->link_modes.advertising,
-                    safe_ks.link_modes.supported, __ETHTOOL_LINK_MODE_MASK_NBITS))
-        {
-            LOG_ERR("link_mode not supported\n");
-            return -EOPNOTSUPP;
-        }
-
-        bitmap_and(safe_ks.link_modes.advertising, ks->link_modes.advertising,
-                    safe_ks.link_modes.supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
-        zxdh_en_ethtool_to_phytype(&safe_ks, &on_speed_modes);
-        LOG_DEBUG("on_speed_modes: 0x%x\n", on_speed_modes);
-        advertising_link_modes = on_speed_modes;
-    }
-
-    if ((advertising_link_modes == en_dev->advertising_speed_modes) &&
-        (ks->base.autoneg == en_dev->autoneg_enable))
-    {
-        LOG_DEBUG("nothing changed\n");
-        return 0;
-    }
-
-    safe_ks.base.speed = en_dev->speed;
-    en_dev->speed = SPEED_UNKNOWN;
-    LOG_INFO("autoneg %d, link_modes: 0x%x\n", ks->base.autoneg, advertising_link_modes);
-    err = zxdh_en_autoneg_set(en_dev, ks->base.autoneg, advertising_link_modes);
-    if (err != 0)
-    {
-        en_dev->speed = safe_ks.base.speed;
-        LOG_ERR("zxdh_en_autoneg_set failed: %d\n", err);
-        return err;
-    }
-    else
-    {
-        en_dev->autoneg_enable = ks->base.autoneg;
-        en_dev->advertising_speed_modes = advertising_link_modes;
-        en_dev->link_up = false;
-        netif_carrier_off(netdev);
-        en_dev->ops->set_pf_link_up(en_dev->parent, FALSE); //TODO:是否需要更新pf信息？
-        queue_work(en_priv->events->wq, &en_priv->edev.vf_link_info_update_work);
-        queue_work(en_priv->events->wq, &en_priv->edev.link_info_irq_update_np_work);
-    }
-
-    return err;
+										  struct ethtool_link_ksettings *ks)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	ethtool_link_ksettings_zero_link_mode(ks, supported);
+	ethtool_link_ksettings_zero_link_mode(ks, advertising);
+
+	ks->base.port = PORT_FIBRE;
+	ks->base.autoneg = en_dev->autoneg_enable;
+	ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE);
+	ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
+
+	if (en_dev->autoneg_enable == AUTONEG_ENABLE) {
+		ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
+	}
+
+	ks->base.speed = en_dev->speed;
+	if ((!netif_running(netdev)) || (!netif_carrier_ok(netdev))) {
+		ks->base.speed = SPEED_UNKNOWN;
+	}
+	ks->base.duplex = ks->base.speed == SPEED_UNKNOWN ? DUPLEX_UNKNOWN :
+														  DUPLEX_FULL;
+
+	zxdh_en_phytype_to_ethtool(en_dev, ks, true);
+	zxdh_en_phytype_to_ethtool(en_dev, ks, false);
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		zxdh_en_fec_link_ksettings_get(en_dev, ks);
+		zxdh_en_pause_link_ksettings_get(en_dev, ks);
+	}
+
+	return 0;
+}
+
+static int32_t
+zxdh_en_set_link_ksettings(struct net_device *netdev,
+						   const struct ethtool_link_ksettings *ks)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct ethtool_link_ksettings safe_ks;
+	uint32_t advertising_link_modes = 0;
+	uint32_t off_speed_modes = 0;
+	uint32_t on_speed_modes = 0;
+	int32_t err = 0;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		return 0;
+	}
+	if (ks->base.duplex == DUPLEX_HALF) {
+		return -ENAVAIL;
+	}
+
+	memset(&safe_ks, 0, sizeof(safe_ks));
+	ethtool_link_ksettings_zero_link_mode(&safe_ks, supported);
+	ethtool_link_ksettings_zero_link_mode(&safe_ks, advertising);
+
+	if (ks->base.autoneg == AUTONEG_DISABLE) {
+		err = zxdh_en_speed_to_speed_modes(ks->base.speed, &off_speed_modes,
+										   en_dev->supported_speed_modes);
+		LOG_DEBUG("set speed: %d, off_speed_modes: 0x%x\n", ks->base.speed,
+				  off_speed_modes);
+		if (err != 0) {
+			LOG_ERR("zxdh_en_speed_to_speed_mode failed: %d\n", err);
+			return -EOPNOTSUPP;
+		}
+
+		advertising_link_modes = off_speed_modes;
+	} else {
+		zxdh_en_phytype_to_ethtool(en_dev, &safe_ks, true);
+		if (!bitmap_intersects(ks->link_modes.advertising,
+							   safe_ks.link_modes.supported,
+							   __ETHTOOL_LINK_MODE_MASK_NBITS)) {
+			LOG_ERR("link_mode not supported\n");
+			return -EOPNOTSUPP;
+		}
+
+		bitmap_and(safe_ks.link_modes.advertising, ks->link_modes.advertising,
+				   safe_ks.link_modes.supported,
+				   __ETHTOOL_LINK_MODE_MASK_NBITS);
+		zxdh_en_ethtool_to_phytype(&safe_ks, &on_speed_modes);
+		LOG_DEBUG("on_speed_modes: 0x%x\n", on_speed_modes);
+		advertising_link_modes = on_speed_modes;
+	}
+
+	if ((advertising_link_modes == en_dev->advertising_speed_modes) &&
+		(ks->base.autoneg == en_dev->autoneg_enable)) {
+		LOG_DEBUG("nothing changed\n");
+		return 0;
+	}
+
+	safe_ks.base.speed = en_dev->speed;
+	en_dev->speed = SPEED_UNKNOWN;
+	LOG_INFO("autoneg %d, link_modes: 0x%x\n", ks->base.autoneg,
+			 advertising_link_modes);
+	err = zxdh_en_autoneg_set(en_dev, ks->base.autoneg, advertising_link_modes);
+	if (err != 0) {
+		en_dev->speed = safe_ks.base.speed;
+		LOG_ERR("zxdh_en_autoneg_set failed: %d\n", err);
+		return err;
+	} else {
+		en_dev->autoneg_enable = ks->base.autoneg;
+		en_dev->advertising_speed_modes = advertising_link_modes;
+		en_dev->link_up = false;
+		netif_carrier_off(netdev);
+		en_dev->ops->set_pf_link_up(en_dev->parent,
+									FALSE); // TODO:是否需要更新pf信息？
+		queue_work(en_priv->events->wq,
+				   &en_priv->edev.vf_link_info_update_work);
+		queue_work(en_priv->events->wq,
+				   &en_priv->edev.link_info_irq_update_np_work);
+	}
+
+	return err;
 }
 
 static uint32_t zxdh_en_get_link(struct net_device *netdev)
 {
-    return netif_carrier_ok(netdev) ? 1 : 0;
+	return netif_carrier_ok(netdev) ? 1 : 0;
 }
 
 static int zxdh_en_get_eeprom_len(struct net_device *netdev)
 {
-    return 0;
+	return 0;
 }
 
-static int zxdh_en_get_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom, u8 *bytes)
+static int zxdh_en_get_eeprom(struct net_device *netdev,
+							  struct ethtool_eeprom *eeprom, u8 *bytes)
 {
-    return 0;
+	return 0;
 }
 
-static int zxdh_en_set_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom, u8 *bytes)
+static int zxdh_en_set_eeprom(struct net_device *netdev,
+							  struct ethtool_eeprom *eeprom, u8 *bytes)
 {
-    return 0;
+	return 0;
 }
 
-static void zxdh_en_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
+static void zxdh_en_get_ringparam(struct net_device *netdev,
+								  struct ethtool_ringparam *ring)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
 
-    ring->rx_max_pending = ZXDH_PF_MAX_DESC_NUM;
-    ring->tx_max_pending = ZXDH_PF_MAX_DESC_NUM;
-    ring->rx_pending = en_dev->ops->get_queue_size(en_dev->parent, en_dev->phy_index[0]);
-    ring->tx_pending = en_dev->ops->get_queue_size(en_dev->parent, en_dev->phy_index[1]);
+	ring->rx_max_pending = ZXDH_PF_MAX_DESC_NUM;
+	ring->tx_max_pending = ZXDH_PF_MAX_DESC_NUM;
+	ring->rx_pending =
+			en_dev->ops->get_queue_size(en_dev->parent, en_dev->phy_index[0]);
+	ring->tx_pending =
+			en_dev->ops->get_queue_size(en_dev->parent, en_dev->phy_index[1]);
 
-    return;
+	return;
 }
 
-static int zxdh_en_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
-{
-    LOG_ERR("not supported\n");
-    return -1;
-}
-
-static void zxdh_en_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
-{
-    int32_t err;
-    uint32_t fc_mode;
-    struct zxdh_en_device *en_dev = netdev_priv(netdev);
-
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-    {
-        return;
-    }
-
-    err = zxdh_en_fc_mode_get(en_dev, &fc_mode);
-    if(err != 0)
-    {
-        LOG_ERR("zxdh_en_fc_mode_get failed!\n");
-        return;
-    }
-
-    pause->autoneg = 0;
-
-    switch(fc_mode)
-    {
-        case BIT(SPM_FC_PAUSE_FULL):
-        {
-            pause->rx_pause = 1;
-            pause->tx_pause = 1;
-            break;
-        }
-        case BIT(SPM_FC_PAUSE_RX):
-        {
-            pause->rx_pause = 1;
-            pause->tx_pause = 0;
-            break;
-        }
-        case BIT(SPM_FC_PAUSE_TX):
-        {
-            pause->rx_pause = 0;
-            pause->tx_pause = 1;
-            break;
-        }
-        default:
-        {
-            pause->rx_pause = 0;
-            pause->tx_pause = 0;
-            break;
-        }
-    }
-
-    return;
-}
-
-static int32_t zxdh_en_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
-{
-    int32_t err;
-    uint32_t fc_mode_cur;
-    uint32_t fc_mode_cfg;
-    struct zxdh_en_device *en_dev = netdev_priv(netdev);
-
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-    {
-        return -EOPNOTSUPP;
-    }
-
-    if(pause->autoneg)
-    {
-        LOG_ERR("not support pause autoneg!\n");
-        return -EOPNOTSUPP;
-    }
-
-    err = zxdh_en_fc_mode_get(en_dev, &fc_mode_cur);
-    if(err != 0)
-    {
-        LOG_ERR("zxdh_en_fc_mode_get failed!\n");
-        return err;
-    }
-
-    if((pause->rx_pause || pause->tx_pause) && (fc_mode_cur == BIT(SPM_FC_PFC_FULL)))
-    {
-        LOG_ERR("warning, ethtool cfg pause on, this will lead to pfc off!\n");
-    }
-
-    if(pause->rx_pause && pause->tx_pause)
-    {
-        fc_mode_cfg = BIT(SPM_FC_PAUSE_FULL);
-    }
-    else if(pause->rx_pause)
-    {
-        fc_mode_cfg = BIT(SPM_FC_PAUSE_RX);
-    }
-    else if(pause->tx_pause)
-    {
-        fc_mode_cfg = BIT(SPM_FC_PAUSE_TX);
-    }
-    else
-    {
-        if(fc_mode_cur == BIT(SPM_FC_PFC_FULL))
-            fc_mode_cfg = BIT(SPM_FC_PFC_FULL);
-        else
-            fc_mode_cfg = BIT(SPM_FC_NONE);
-    }
-
-    if(fc_mode_cfg != fc_mode_cur)
-    {
-        err = zxdh_en_fc_mode_set(en_dev, fc_mode_cfg);
-        if(err != 0)
-        {
-            LOG_ERR("zxdh_en_fc_mode_set failed!\n");
-            return err;
-        }
-    }
-
-    return 0;
-}
-
-static int32_t zxdh_en_get_fecparam(struct net_device *netdev, struct ethtool_fecparam *fecparam)
-{
-    int32_t err;
-    uint32_t fec_cfg;
-    uint32_t fec_active;
-    struct zxdh_en_device *en_dev = netdev_priv(netdev);
-
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-    {
-        return -EOPNOTSUPP;
-    }
-
-    err = zxdh_en_fec_mode_get(en_dev, NULL, &fec_cfg, &fec_active);
-    if(err != 0)
-    {
-        LOG_ERR("zxdh_en_fec_mode_get failed!\n");
-        return err;
-    }
-
-    fecparam->fec = zxdh_en_fec_to_ethtool_fecparam(fec_cfg, GET_FEC_CFG_FLAG);
-    fecparam->active_fec = zxdh_en_fec_to_ethtool_fecparam(fec_active, GET_FEC_LINK_FLAG);
-
-    //LOG_INFO("fec_cfg=0x%x, fecparam->fec=0x%x, fec_active=0x%x, fecparam->active_fec=0x%x\n",
-    //          fec_cfg, fecparam->fec, fec_active, fecparam->active_fec);
-
-    return 0;
-}
-
-static int32_t zxdh_en_set_fecparam(struct net_device *netdev, struct ethtool_fecparam *fecparam)
-{
-    int32_t i;
-    int32_t err;
-    uint32_t fec_cap;
-    uint32_t fec_cfg = 0;
-    uint32_t fecparam_cap;
-    struct zxdh_en_device *en_dev = netdev_priv(netdev);
-
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-    {
-        return -EOPNOTSUPP;
-    }
-
-    err = zxdh_en_fec_mode_get(en_dev, &fec_cap, NULL, NULL);
-    if(err != 0)
-    {
-        LOG_ERR("zxdh_en_fec_mode_get failed!\n");
-        return err;
-    }
-    fecparam_cap = zxdh_en_fec_to_ethtool_fecparam(fec_cap, GET_FEC_CAP_FLAG);
-
-    if((fecparam->fec | fecparam_cap) != fecparam_cap)
-    {
-        LOG_ERR("fecparam->fec 0x%x unsupport !\n", fecparam->fec);
-        return -EOPNOTSUPP;
-    }
-
-    for(i = 0; i < ARRAY_SIZE(fec_2_ethtool_fecparam); i++)
-    {
-        if(fecparam->fec == fec_2_ethtool_fecparam[i])
-        {
-            fec_cfg |= BIT(i);
-        }
-    }
-
-    if(!fec_cfg && (fecparam->fec != ETHTOOL_FEC_AUTO))
-    {
-        LOG_ERR("fecparam->fec 0x%x unsupport !\n", fecparam->fec);
-        return -EOPNOTSUPP;
-    }
-
-    //LOG_INFO("fecparam_cap=0x%x, fec_cap=0x%x, fecparam->fec=0x%x, fec_cfg=0x%x\n",
-    //          fecparam_cap, fec_cap, fecparam->fec, fec_cfg);
-
-    err = zxdh_en_fec_mode_set(en_dev, fec_cfg);
-    if(err != 0)
-    {
-        LOG_ERR("zxdh_en_fec_mode_set failed!\n");
-        return err;
-    }
-
-    return 0;
-}
-
-static int32_t zxdh_en_get_module_info(struct net_device *netdev, struct ethtool_modinfo *modinfo)
-{
-    uint32_t read_bytes;
-    uint8_t data[2] = {0};
-    struct zxdh_en_module_eeprom_param query = {0};
-    struct zxdh_en_device *en_dev = netdev_priv(netdev);
-
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-    {
-        return -EOPNOTSUPP;
-    }
-
-    query.i2c_addr = SFF_I2C_ADDRESS_LOW;
-    query.page = 0;
-    query.offset = 0;
-    query.length = 2;
-    read_bytes = zxdh_en_module_eeprom_read(en_dev, &query, data);
-    if(read_bytes != query.length)
-    {
-        LOG_ERR("zxdh_en_module_eeprom_read failed!\n");
-        return -EIO;
-    }
-
-    switch(data[0])
-    {
-        case ZXDH_MODULE_ID_SFP:
-            modinfo->type       = ETH_MODULE_SFF_8472;
-            modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
-            break;
-        case ZXDH_MODULE_ID_QSFP:
-            modinfo->type       = ETH_MODULE_SFF_8436;
-            modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
-            break;
-        case ZXDH_MODULE_ID_QSFP_PLUS:
-        case ZXDH_MODULE_ID_QSFP28:
-            if(data[1] < 3)
-            {
-                modinfo->type       = ETH_MODULE_SFF_8436;
-                modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
-            }
-            else
-            {
-                modinfo->type       = ETH_MODULE_SFF_8636;
-                modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
-            }
-            break;
-        default:
-            LOG_ERR("can not recognize module identifier 0x%x!\n", data[0]);
-            return -EINVAL;
-    }
-
-    return 0;
-}
-
-static int32_t zxdh_en_get_module_eeprom(struct net_device *netdev, struct ethtool_eeprom *ee, u8 *data)
-{
-    struct zxdh_en_module_eeprom_param query = {0};
-    struct zxdh_en_device *en_dev = netdev_priv(netdev);
-    uint32_t offset = ee->offset;
-    uint32_t length = ee->len;
-    uint8_t identifier;
-    uint32_t offset_boundary = 0;
-    uint32_t total_read_bytes = 0;
-    uint32_t read_bytes = 0;
-
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-    {
-        return -EOPNOTSUPP;
-    }
-
-    //LOG_INFO("offset %u, len %u\n", ee->offset, ee->len);
-
-    if(!ee->len)
-        return -EINVAL;
-
-    memset(data, 0, ee->len);
-
-    query.i2c_addr = SFF_I2C_ADDRESS_LOW;
-    query.bank = 0;
-    query.page = 0;
-    query.offset = 0;
-    query.length = 1;
-    read_bytes = zxdh_en_module_eeprom_read(en_dev, &query, &identifier);
-    if(read_bytes != query.length)
-    {
-        LOG_ERR("zxdh_en_module_eeprom_read failed!\n");
-        return -EIO;
-    }
-
-    while(total_read_bytes < ee->len)
-    {
-        if(identifier == ZXDH_MODULE_ID_SFP)
-        {
-            if(offset < 256)
-            {
-                query.i2c_addr = SFF_I2C_ADDRESS_LOW;
-                query.page = 0;
-                query.offset = offset;
-            }
-            else
-            {
-                query.i2c_addr = SFF_I2C_ADDRESS_HIGH;
-                query.page = 0;
-                query.offset = offset - 256;
-            }
-            offset_boundary = (query.offset < 128) ? 128 : 256;
-            query.length = ((query.offset + length) > offset_boundary) ? (offset_boundary - query.offset) : length;
-        }
-        else if(identifier == ZXDH_MODULE_ID_QSFP ||
-                identifier == ZXDH_MODULE_ID_QSFP_PLUS ||
-                identifier == ZXDH_MODULE_ID_QSFP28)
-        {
-            query.i2c_addr = SFF_I2C_ADDRESS_LOW;
-            if(offset < 256)
-            {
-                query.page = 0;
-                query.offset = offset;
-            }
-            else
-            {
-                query.page = (offset - 256) / 128 + 1;
-                query.offset = offset - 128 * query.page;
-            }
-            offset_boundary = (query.offset < 128) ? 128 : 256;
-            query.length = ((query.offset + length) > offset_boundary) ? (offset_boundary - query.offset) : length;
-        }
-        else
-        {
-            LOG_ERR("can not recognize module identifier 0x%x!\n", identifier);
-            return -EINVAL;
-        }
-
-        read_bytes = zxdh_en_module_eeprom_read(en_dev, &query, data + total_read_bytes);
-        if(read_bytes != query.length)
-        {
-            LOG_ERR("zxdh_en_module_eeprom_read failed!\n");
-            return -EIO;
-        }
-
-        total_read_bytes += read_bytes;
-        offset += read_bytes;
-        length -= read_bytes;
-    }
-
-    return 0;
+static int zxdh_en_set_ringparam(struct net_device *netdev,
+								 struct ethtool_ringparam *ring)
+{
+	LOG_ERR("not supported\n");
+	return -1;
+}
+
+static void zxdh_en_get_pauseparam(struct net_device *netdev,
+								   struct ethtool_pauseparam *pause)
+{
+	int32_t err;
+	uint32_t fc_mode;
+	struct zxdh_en_device *en_dev = netdev_priv(netdev);
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		return;
+	}
+
+	err = zxdh_en_fc_mode_get(en_dev, &fc_mode);
+	if (err != 0) {
+		LOG_ERR("zxdh_en_fc_mode_get failed!\n");
+		return;
+	}
+
+	pause->autoneg = 0;
+
+	switch (fc_mode) {
+	case BIT(SPM_FC_PAUSE_FULL): {
+		pause->rx_pause = 1;
+		pause->tx_pause = 1;
+		break;
+	}
+	case BIT(SPM_FC_PAUSE_RX): {
+		pause->rx_pause = 1;
+		pause->tx_pause = 0;
+		break;
+	}
+	case BIT(SPM_FC_PAUSE_TX): {
+		pause->rx_pause = 0;
+		pause->tx_pause = 1;
+		break;
+	}
+	default: {
+		pause->rx_pause = 0;
+		pause->tx_pause = 0;
+		break;
+	}
+	}
+
+	return;
+}
+
+static int32_t zxdh_en_set_pauseparam(struct net_device *netdev,
+									  struct ethtool_pauseparam *pause)
+{
+	int32_t err;
+	uint32_t fc_mode_cur;
+	uint32_t fc_mode_cfg;
+	struct zxdh_en_device *en_dev = netdev_priv(netdev);
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		return -EOPNOTSUPP;
+	}
+
+	if (pause->autoneg) {
+		LOG_ERR("not support pause autoneg!\n");
+		return -EOPNOTSUPP;
+	}
+
+	err = zxdh_en_fc_mode_get(en_dev, &fc_mode_cur);
+	if (err != 0) {
+		LOG_ERR("zxdh_en_fc_mode_get failed!\n");
+		return err;
+	}
+
+	if ((pause->rx_pause || pause->tx_pause) &&
+		(fc_mode_cur == BIT(SPM_FC_PFC_FULL))) {
+		LOG_ERR("warning, ethtool cfg pause on, this will lead to pfc off!\n");
+	}
+
+	if (pause->rx_pause && pause->tx_pause) {
+		fc_mode_cfg = BIT(SPM_FC_PAUSE_FULL);
+	} else if (pause->rx_pause) {
+		fc_mode_cfg = BIT(SPM_FC_PAUSE_RX);
+	} else if (pause->tx_pause) {
+		fc_mode_cfg = BIT(SPM_FC_PAUSE_TX);
+	} else {
+		if (fc_mode_cur == BIT(SPM_FC_PFC_FULL))
+			fc_mode_cfg = BIT(SPM_FC_PFC_FULL);
+		else
+			fc_mode_cfg = BIT(SPM_FC_NONE);
+	}
+
+	if (fc_mode_cfg != fc_mode_cur) {
+		err = zxdh_en_fc_mode_set(en_dev, fc_mode_cfg);
+		if (err != 0) {
+			LOG_ERR("zxdh_en_fc_mode_set failed!\n");
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+static int32_t zxdh_en_get_fecparam(struct net_device *netdev,
+									struct ethtool_fecparam *fecparam)
+{
+	int32_t err;
+	uint32_t fec_cfg;
+	uint32_t fec_active;
+	struct zxdh_en_device *en_dev = netdev_priv(netdev);
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		return -EOPNOTSUPP;
+	}
+
+	err = zxdh_en_fec_mode_get(en_dev, NULL, &fec_cfg, &fec_active);
+	if (err != 0) {
+		LOG_ERR("zxdh_en_fec_mode_get failed!\n");
+		return err;
+	}
+
+	fecparam->fec = zxdh_en_fec_to_ethtool_fecparam(fec_cfg, GET_FEC_CFG_FLAG);
+	fecparam->active_fec =
+			zxdh_en_fec_to_ethtool_fecparam(fec_active, GET_FEC_LINK_FLAG);
+
+	// LOG_INFO("fec_cfg=0x%x, fecparam->fec=0x%x, fec_active=0x%x,
+	// fecparam->active_fec=0x%x\n",
+	//          fec_cfg, fecparam->fec, fec_active, fecparam->active_fec);
+
+	return 0;
+}
+
+static int32_t zxdh_en_set_fecparam(struct net_device *netdev,
+									struct ethtool_fecparam *fecparam)
+{
+	int32_t i;
+	int32_t err;
+	uint32_t fec_cap;
+	uint32_t fec_cfg = 0;
+	uint32_t fecparam_cap;
+	struct zxdh_en_device *en_dev = netdev_priv(netdev);
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		return -EOPNOTSUPP;
+	}
+
+	err = zxdh_en_fec_mode_get(en_dev, &fec_cap, NULL, NULL);
+	if (err != 0) {
+		LOG_ERR("zxdh_en_fec_mode_get failed!\n");
+		return err;
+	}
+	fecparam_cap = zxdh_en_fec_to_ethtool_fecparam(fec_cap, GET_FEC_CAP_FLAG);
+
+	if ((fecparam->fec | fecparam_cap) != fecparam_cap) {
+		LOG_ERR("fecparam->fec 0x%x unsupport !\n", fecparam->fec);
+		return -EOPNOTSUPP;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(fec_2_ethtool_fecparam); i++) {
+		if (fecparam->fec == fec_2_ethtool_fecparam[i]) {
+			fec_cfg |= BIT(i);
+		}
+	}
+
+	if (!fec_cfg && (fecparam->fec != ETHTOOL_FEC_AUTO)) {
+		LOG_ERR("fecparam->fec 0x%x unsupport !\n", fecparam->fec);
+		return -EOPNOTSUPP;
+	}
+
+	// LOG_INFO("fecparam_cap=0x%x, fec_cap=0x%x, fecparam->fec=0x%x,
+	// fec_cfg=0x%x\n",
+	//          fecparam_cap, fec_cap, fecparam->fec, fec_cfg);
+
+	err = zxdh_en_fec_mode_set(en_dev, fec_cfg);
+	if (err != 0) {
+		LOG_ERR("zxdh_en_fec_mode_set failed!\n");
+		return err;
+	}
+
+	return 0;
+}
+
+static int32_t zxdh_en_get_module_info(struct net_device *netdev,
+									   struct ethtool_modinfo *modinfo)
+{
+	uint32_t read_bytes;
+	uint8_t data[2] = { 0 };
+	struct zxdh_en_module_eeprom_param query = { 0 };
+	struct zxdh_en_device *en_dev = netdev_priv(netdev);
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		return -EOPNOTSUPP;
+	}
+
+	query.i2c_addr = SFF_I2C_ADDRESS_LOW;
+	query.page = 0;
+	query.offset = 0;
+	query.length = 2;
+	read_bytes = zxdh_en_module_eeprom_read(en_dev, &query, data);
+	if (read_bytes != query.length) {
+		LOG_ERR("zxdh_en_module_eeprom_read failed!\n");
+		return -EIO;
+	}
+
+	switch (data[0]) {
+	case ZXDH_MODULE_ID_SFP:
+		modinfo->type = ETH_MODULE_SFF_8472;
+		modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
+		break;
+	case ZXDH_MODULE_ID_QSFP:
+		modinfo->type = ETH_MODULE_SFF_8436;
+		modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
+		break;
+	case ZXDH_MODULE_ID_QSFP_PLUS:
+	case ZXDH_MODULE_ID_QSFP28:
+		if (data[1] < 3) {
+			modinfo->type = ETH_MODULE_SFF_8436;
+			modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
+		} else {
+			modinfo->type = ETH_MODULE_SFF_8636;
+			modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
+		}
+		break;
+	default:
+		LOG_ERR("can not recognize module identifier 0x%x!\n", data[0]);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int32_t zxdh_en_get_module_eeprom(struct net_device *netdev,
+										 struct ethtool_eeprom *ee, u8 *data)
+{
+	struct zxdh_en_module_eeprom_param query = { 0 };
+	struct zxdh_en_device *en_dev = netdev_priv(netdev);
+	uint32_t offset = ee->offset;
+	uint32_t length = ee->len;
+	uint8_t identifier;
+	uint32_t offset_boundary = 0;
+	uint32_t total_read_bytes = 0;
+	uint32_t read_bytes = 0;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		return -EOPNOTSUPP;
+	}
+
+	// LOG_INFO("offset %u, len %u\n", ee->offset, ee->len);
+
+	if (!ee->len)
+		return -EINVAL;
+
+	memset(data, 0, ee->len);
+
+	query.i2c_addr = SFF_I2C_ADDRESS_LOW;
+	query.bank = 0;
+	query.page = 0;
+	query.offset = 0;
+	query.length = 1;
+	read_bytes = zxdh_en_module_eeprom_read(en_dev, &query, &identifier);
+	if (read_bytes != query.length) {
+		LOG_ERR("zxdh_en_module_eeprom_read failed!\n");
+		return -EIO;
+	}
+
+	while (total_read_bytes < ee->len) {
+		if (identifier == ZXDH_MODULE_ID_SFP) {
+			if (offset < 256) {
+				query.i2c_addr = SFF_I2C_ADDRESS_LOW;
+				query.page = 0;
+				query.offset = offset;
+			} else {
+				query.i2c_addr = SFF_I2C_ADDRESS_HIGH;
+				query.page = 0;
+				query.offset = offset - 256;
+			}
+			offset_boundary = (query.offset < 128) ? 128 : 256;
+			query.length = ((query.offset + length) > offset_boundary) ?
+									 (offset_boundary - query.offset) :
+									 length;
+		} else if (identifier == ZXDH_MODULE_ID_QSFP ||
+				   identifier == ZXDH_MODULE_ID_QSFP_PLUS ||
+				   identifier == ZXDH_MODULE_ID_QSFP28) {
+			query.i2c_addr = SFF_I2C_ADDRESS_LOW;
+			if (offset < 256) {
+				query.page = 0;
+				query.offset = offset;
+			} else {
+				query.page = (offset - 256) / 128 + 1;
+				query.offset = offset - 128 * query.page;
+			}
+			offset_boundary = (query.offset < 128) ? 128 : 256;
+			query.length = ((query.offset + length) > offset_boundary) ?
+									 (offset_boundary - query.offset) :
+									 length;
+		} else {
+			LOG_ERR("can not recognize module identifier 0x%x!\n", identifier);
+			return -EINVAL;
+		}
+
+		read_bytes = zxdh_en_module_eeprom_read(en_dev, &query,
+												data + total_read_bytes);
+		if (read_bytes != query.length) {
+			LOG_ERR("zxdh_en_module_eeprom_read failed!\n");
+			return -EIO;
+		}
+
+		total_read_bytes += read_bytes;
+		offset += read_bytes;
+		length -= read_bytes;
+	}
+
+	return 0;
 }
 
 #ifdef HAVE_ETHTOOL_GET_MODULE_EEPROM_BY_PAGE
-static int32_t zxdh_en_get_module_eeprom_by_page(struct net_device *netdev,
-                                                 const struct ethtool_module_eeprom *page_data,
-                                                 struct netlink_ext_ack *extack)
+static int32_t
+zxdh_en_get_module_eeprom_by_page(struct net_device *netdev,
+								  const struct ethtool_module_eeprom *page_data,
+								  struct netlink_ext_ack *extack)
 {
-    struct zxdh_en_module_eeprom_param query = {0};
-    struct zxdh_en_device *en_dev = netdev_priv(netdev);
-    uint32_t read_bytes = 0;
+	struct zxdh_en_module_eeprom_param query = { 0 };
+	struct zxdh_en_device *en_dev = netdev_priv(netdev);
+	uint32_t read_bytes = 0;
 
-    if(en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF)
-    {
-        return -EOPNOTSUPP;
-    }
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		return -EOPNOTSUPP;
+	}
 
-    //LOG_INFO("offset %u, length %u, page %u, bank %u, i2c_address %u\n",
-    //          page_data->offset, page_data->length, page_data->page, page_data->bank, page_data->i2c_address);
+	// LOG_INFO("offset %u, length %u, page %u, bank %u, i2c_address %u\n",
+	//          page_data->offset, page_data->length, page_data->page,
+	//          page_data->bank, page_data->i2c_address);
 
-    if(!page_data->length)
-        return -EINVAL;
+	if (!page_data->length)
+		return -EINVAL;
 
-    memset(page_data->data, 0, page_data->length);
+	memset(page_data->data, 0, page_data->length);
 
-    query.i2c_addr = page_data->i2c_address;
-    query.bank = page_data->bank;
-    query.page = page_data->page;
-    query.offset = page_data->offset;
-    query.length = page_data->length;
-    read_bytes = zxdh_en_module_eeprom_read(en_dev, &query, page_data->data);
-    if(read_bytes != query.length)
-    {
-        LOG_ERR("zxdh_en_module_eeprom_read failed!\n");
-        return -EIO;
-    }
+	query.i2c_addr = page_data->i2c_address;
+	query.bank = page_data->bank;
+	query.page = page_data->page;
+	query.offset = page_data->offset;
+	query.length = page_data->length;
+	read_bytes = zxdh_en_module_eeprom_read(en_dev, &query, page_data->data);
+	if (read_bytes != query.length) {
+		LOG_ERR("zxdh_en_module_eeprom_read failed!\n");
+		return -EIO;
+	}
 
-    return read_bytes;
+	return read_bytes;
 }
 #endif
 
-static void zxdh_en_diag_test(struct net_device *netdev, struct ethtool_test *eth_test, u64 *data)
+static void zxdh_en_diag_test(struct net_device *netdev,
+							  struct ethtool_test *eth_test, u64 *data)
 {
-
 }
 
 static int32_t zxdh_lldp_enable_proc(struct net_device *netdev, bool enable)
 {
-    int32_t ret = 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	int32_t ret = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
 
-    ret = zxdh_lldp_enable_set(&en_priv->edev, enable);
-    if (0 != ret)
-    {
-        LOG_ERR("%s lldp failed!\n", enable ? "enable" : "disable");
-        return ret;
-    }
+	ret = zxdh_lldp_enable_set(&en_priv->edev, enable);
+	if (0 != ret) {
+		LOG_ERR("%s lldp failed!\n", enable ? "enable" : "disable");
+		return ret;
+	}
 
-    return ret;
+	return ret;
 }
 
 static int32_t zxdh_sshd_enable_proc(struct net_device *netdev, bool enable)
 {
-    int32_t ret = 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	int32_t ret = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
 
-    ret = zxdh_sshd_enable_set(&en_priv->edev, enable);
-    if (0 != ret)
-    {
-        LOG_ERR("%s riscv sshd failed!\n", enable ? "enable" : "disable");
-        return ret;
-    }
+	ret = zxdh_sshd_enable_set(&en_priv->edev, enable);
+	if (0 != ret) {
+		LOG_ERR("%s riscv sshd failed!\n", enable ? "enable" : "disable");
+		return ret;
+	}
 
-    return ret;
+	return ret;
 }
 
 typedef int32_t (*zxdh_pflag_handler)(struct net_device *netdev, bool enable);
 
-struct flag_desc
-{
-    uint8_t name[ETH_GSTRING_LEN];
-    uint32_t bitno;
-    zxdh_pflag_handler handler;
+struct flag_desc {
+	uint8_t name[ETH_GSTRING_LEN];
+	uint32_t bitno;
+	zxdh_pflag_handler handler;
 };
 
-#define ZXDH_PRIV_DESC(_name, _bitno, _handler) \
-{                                               \
-    .name = _name,                              \
-    .bitno = _bitno,                            \
-    .handler = _handler,                        \
-}
-
-static const struct flag_desc zxdh_gstrings_priv_flags[] =
-{
-    ZXDH_PRIV_DESC("enable_lldp", ZXDH_PFLAG_ENABLE_LLDP, zxdh_lldp_enable_proc),
-    ZXDH_PRIV_DESC("enable_sshd", ZXDH_PFLAG_ENABLE_SSHD, zxdh_sshd_enable_proc),
-    ZXDH_PRIV_DESC("debug_ip", ZXDH_PFLAG_IP, NULL),
+#define ZXDH_PRIV_DESC(_name, _bitno, _handler)              \
+	{                                                        \
+		.name = _name, .bitno = _bitno, .handler = _handler, \
+	}
+
+static const struct flag_desc zxdh_gstrings_priv_flags[] = {
+	ZXDH_PRIV_DESC("enable_lldp", ZXDH_PFLAG_ENABLE_LLDP,
+				   zxdh_lldp_enable_proc),
+	ZXDH_PRIV_DESC("enable_sshd", ZXDH_PFLAG_ENABLE_SSHD,
+				   zxdh_sshd_enable_proc),
+	ZXDH_PRIV_DESC("debug_ip", ZXDH_PFLAG_IP, NULL),
 };
 
 #define ZXDH_PRIV_FALG_ARRAY_SIZE ARRAY_SIZE(zxdh_gstrings_priv_flags)
 
-static void zxdh_en_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint16_t i = 0;
-    int8_t ip[20] = {0};
-    uint8_t is_zios = 0;
-    int32_t ret = 0;
-
-    switch (stringset)
-    {
-        case ETH_SS_STATS:
-        {
-            snprintf(data, ETH_GSTRING_LEN, "rx_packets");//get stat from netdev->stats
-            ZXDH_ADD_STRING(data, "tx_packets");
-            ZXDH_ADD_STRING(data, "rx_bytes");
-            ZXDH_ADD_STRING(data, "tx_bytes");
-            ZXDH_ADD_STRING(data, "tx_queue_wake");
-            ZXDH_ADD_STRING(data, "tx_queue_stopped");
-            ZXDH_ADD_STRING(data, "tx_queue_dropped");
-
-            ZXDH_ADD_STRING(data, "rx_vport_packets");//get stat from np & vqm
-            ZXDH_ADD_STRING(data, "tx_vport_packets");
-            ZXDH_ADD_STRING(data, "rx_vport_bytes");
-            ZXDH_ADD_STRING(data, "tx_vport_bytes");
-            ZXDH_ADD_STRING(data, "rx_vport_dropped");
-            ZXDH_ADD_STRING(data, "rx_vport_broadcast_packets");
-            ZXDH_ADD_STRING(data, "tx_vport_broadcast_packets");
-            ZXDH_ADD_STRING(data, "rx_vport_mtu_drop_packets");
-            ZXDH_ADD_STRING(data, "tx_vport_mtu_drop_packets");
-            ZXDH_ADD_STRING(data, "rx_vport_mtu_drop_bytes");
-            ZXDH_ADD_STRING(data, "tx_vport_mtu_drop_bytes");
-            ZXDH_ADD_STRING(data, "rx_vport_plcr_drop_packets");
-            ZXDH_ADD_STRING(data, "tx_vport_plcr_drop_packets");
-            ZXDH_ADD_STRING(data, "rx_vport_plcr_drop_bytes");
-            ZXDH_ADD_STRING(data, "tx_vport_plcr_drop_bytes");
-
-            ZXDH_ADD_STRING(data, "rx_packets_phy");//get stat from mac
-            ZXDH_ADD_STRING(data, "tx_packets_phy");
-            ZXDH_ADD_STRING(data, "rx_bytes_phy");
-            ZXDH_ADD_STRING(data, "tx_bytes_phy");
-            ZXDH_ADD_STRING(data, "rx_errors_phy");
-            ZXDH_ADD_STRING(data, "tx_errors_phy");
-            ZXDH_ADD_STRING(data, "rx_drop_phy");
-            ZXDH_ADD_STRING(data, "tx_drop_phy");
-            ZXDH_ADD_STRING(data, "rx_multicast_phy");
-            ZXDH_ADD_STRING(data, "tx_multicast_phy");
-            ZXDH_ADD_STRING(data, "rx_broadcast_phy");
-            ZXDH_ADD_STRING(data, "tx_broadcast_phy");
-            ZXDH_ADD_STRING(data, "rx_size_64_phy");
-            ZXDH_ADD_STRING(data, "rx_size_65_127");
-            ZXDH_ADD_STRING(data, "rx_size_128_255");
-            ZXDH_ADD_STRING(data, "rx_size_256_511");
-            ZXDH_ADD_STRING(data, "rx_size_512_1023");
-            ZXDH_ADD_STRING(data, "rx_size_1024_1518");
-            ZXDH_ADD_STRING(data, "rx_size_1519_mru");
-            ZXDH_ADD_STRING(data, "rx_pause");
-            ZXDH_ADD_STRING(data, "tx_pause");
-
-            for (i = 0; i < en_dev->curr_queue_pairs; i++)
-            {
-                ZXDH_ADD_QUEUE_STRING(data, "rx_pkts", i);
-                ZXDH_ADD_QUEUE_STRING(data, "tx_pkts", i);
-                ZXDH_ADD_QUEUE_STRING(data, "rx_bytes", i);
-                ZXDH_ADD_QUEUE_STRING(data, "tx_bytes", i);
-                ZXDH_ADD_QUEUE_STRING(data, "tx_stopped", i);
-                ZXDH_ADD_QUEUE_STRING(data, "tx_wake", i);
-                ZXDH_ADD_QUEUE_STRING(data, "tx_dropped", i);
-            }
-            break;
-        }
-        case ETH_SS_PRIV_FLAGS:
-        {
-            for (i = 0; i < ZXDH_NUM_PFLAGS; i++)
-            {
-                strncpy(data + i * ETH_GSTRING_LEN, zxdh_gstrings_priv_flags[i].name, ETH_GSTRING_LEN);
-            }
-
-            /* 获取riscv的os类型 */
-            ret = zxdh_riscv_os_type_get(en_dev, &is_zios);
-            if (ret != 0)
-            {
-                LOG_ERR("zxdh_riscv_os_type_get failed");
-                break;
-            }
-
-            /* 修改登录方式 */
-            if (is_zios == ZIOS_TYPE)
-            {
-                strncpy(data + ZXDH_PFLAG_ENABLE_SSHD * ETH_GSTRING_LEN, "enable_telnetd", ETH_GSTRING_LEN);
-            }
-
-            /* 获取debug口的ip地址*/
-            ret = zxdh_debug_ip_get(en_dev, ip);
-            if (ret != 0)
-            {
-                LOG_ERR("ip get failed");
-                break;
-            }
-            strncpy(data + ZXDH_PFLAG_IP * ETH_GSTRING_LEN, ip, ETH_GSTRING_LEN);
-            break;
-        }
-        default:
-        {
-            LOG_ERR("invalid para\n");
-            break;
-        }
-    }
-
-    return;
+static void zxdh_en_get_strings(struct net_device *netdev, u32 stringset,
+								u8 *data)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint16_t i = 0;
+	int8_t ip[20] = { 0 };
+	int32_t ret = 0;
+
+	switch (stringset) {
+	case ETH_SS_STATS: {
+		snprintf(data, ETH_GSTRING_LEN, "rx_packets"); // get stat from
+				// netdev->stats
+		ZXDH_ADD_STRING(data, "tx_packets");
+		ZXDH_ADD_STRING(data, "rx_bytes");
+		ZXDH_ADD_STRING(data, "tx_bytes");
+		ZXDH_ADD_STRING(data, "tx_queue_wake");
+		ZXDH_ADD_STRING(data, "tx_queue_stopped");
+		ZXDH_ADD_STRING(data, "tx_queue_dropped");
+
+		ZXDH_ADD_STRING(data, "rx_vport_packets"); // get stat from np & vqm
+		ZXDH_ADD_STRING(data, "tx_vport_packets");
+		ZXDH_ADD_STRING(data, "rx_vport_bytes");
+		ZXDH_ADD_STRING(data, "tx_vport_bytes");
+		ZXDH_ADD_STRING(data, "rx_vport_dropped");
+		ZXDH_ADD_STRING(data, "rx_vport_broadcast_packets");
+		ZXDH_ADD_STRING(data, "tx_vport_broadcast_packets");
+		ZXDH_ADD_STRING(data, "rx_vport_mtu_drop_packets");
+		ZXDH_ADD_STRING(data, "tx_vport_mtu_drop_packets");
+		ZXDH_ADD_STRING(data, "rx_vport_mtu_drop_bytes");
+		ZXDH_ADD_STRING(data, "tx_vport_mtu_drop_bytes");
+		ZXDH_ADD_STRING(data, "rx_vport_plcr_drop_packets");
+		ZXDH_ADD_STRING(data, "tx_vport_plcr_drop_packets");
+		ZXDH_ADD_STRING(data, "rx_vport_plcr_drop_bytes");
+		ZXDH_ADD_STRING(data, "tx_vport_plcr_drop_bytes");
+
+		ZXDH_ADD_STRING(data, "rx_packets_phy"); // get stat from mac
+		ZXDH_ADD_STRING(data, "tx_packets_phy");
+		ZXDH_ADD_STRING(data, "rx_bytes_phy");
+		ZXDH_ADD_STRING(data, "tx_bytes_phy");
+		ZXDH_ADD_STRING(data, "rx_errors_phy");
+		ZXDH_ADD_STRING(data, "tx_errors_phy");
+		ZXDH_ADD_STRING(data, "rx_drop_phy");
+		ZXDH_ADD_STRING(data, "tx_drop_phy");
+		ZXDH_ADD_STRING(data, "rx_multicast_phy");
+		ZXDH_ADD_STRING(data, "tx_multicast_phy");
+		ZXDH_ADD_STRING(data, "rx_broadcast_phy");
+		ZXDH_ADD_STRING(data, "tx_broadcast_phy");
+		ZXDH_ADD_STRING(data, "rx_size_64_phy");
+		ZXDH_ADD_STRING(data, "rx_size_65_127");
+		ZXDH_ADD_STRING(data, "rx_size_128_255");
+		ZXDH_ADD_STRING(data, "rx_size_256_511");
+		ZXDH_ADD_STRING(data, "rx_size_512_1023");
+		ZXDH_ADD_STRING(data, "rx_size_1024_1518");
+		ZXDH_ADD_STRING(data, "rx_size_1519_mru");
+
+		for (i = 0; i < en_dev->curr_queue_pairs; i++) {
+			ZXDH_ADD_QUEUE_STRING(data, "rx_pkts", i);
+			ZXDH_ADD_QUEUE_STRING(data, "tx_pkts", i);
+			ZXDH_ADD_QUEUE_STRING(data, "rx_bytes", i);
+			ZXDH_ADD_QUEUE_STRING(data, "tx_bytes", i);
+			ZXDH_ADD_QUEUE_STRING(data, "tx_stopped", i);
+			ZXDH_ADD_QUEUE_STRING(data, "tx_wake", i);
+			ZXDH_ADD_QUEUE_STRING(data, "tx_dropped", i);
+		}
+		break;
+	}
+	case ETH_SS_PRIV_FLAGS: {
+		for (i = 0; i < ZXDH_NUM_PFLAGS; i++) {
+			strncpy(data + i * ETH_GSTRING_LEN,
+					zxdh_gstrings_priv_flags[i].name, ETH_GSTRING_LEN);
+		}
+		/* 获取debug的ip地址*/
+		ret = zxdh_debug_ip_get(en_dev, ip);
+		if (ret != 0) {
+			LOG_ERR("ip get failed");
+			break;
+		}
+		strncpy(data + 2 * ETH_GSTRING_LEN, ip, ETH_GSTRING_LEN);
+		break;
+	}
+	default: {
+		LOG_ERR("invalid para\n");
+		break;
+	}
+	}
+
+	return;
 }
 
 static int32_t zxdh_handle_pflag(struct net_device *netdev,
-                                uint32_t wanted_flags,
-                                enum zxdh_priv_flag flag)
+								 uint32_t wanted_flags,
+								 enum zxdh_priv_flag flag)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    bool enable = !!(wanted_flags & BIT(flag));
-    uint32_t changes = wanted_flags ^ en_priv->edev.pflags;
-    int32_t err = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	bool enable = !!(wanted_flags & BIT(flag));
+	uint32_t changes = wanted_flags ^ en_priv->edev.pflags;
+	int32_t err = 0;
 
-    /* 判断设置的值是否改变&改变的位是否为flag位 */
-    if (!(changes & BIT(flag)))
-    {
-        return 0;
-    }
+	/* 判断设置的值是否改变&改变的位是否为flag位 */
+	if (!(changes & BIT(flag))) {
+		return 0;
+	}
 
-    if (flag == ZXDH_PFLAG_IP)
-    {
-        LOG_INFO("debug ip can not be changed");
-        return 0;
-    }
+	if (flag == ZXDH_PFLAG_IP) {
+		LOG_INFO("debug ip can not be changed");
+		return 0;
+	}
 
-    err = zxdh_gstrings_priv_flags[flag].handler(netdev, enable);
-    if (0 != err)
-    {
-        LOG_ERR("%s private flag '%s' failed err %d\n", \
-               enable ? "Enable" : "Disable", zxdh_gstrings_priv_flags[flag].name, err);
-        return err;
-    }
+	err = zxdh_gstrings_priv_flags[flag].handler(netdev, enable);
+	if (0 != err) {
+		LOG_ERR("%s private flag '%s' failed err %d\n",
+				enable ? "Enable" : "Disable",
+				zxdh_gstrings_priv_flags[flag].name, err);
+		return err;
+	}
 
-    ZXDH_SET_PFLAG(en_priv->edev.pflags, flag, enable);
+	ZXDH_SET_PFLAG(en_priv->edev.pflags, flag, enable);
 
-    if (flag == ZXDH_PFLAG_ENABLE_SSHD) /* 同步debug的ip状态*/
-    {
-        ZXDH_SET_PFLAG(en_priv->edev.pflags, ZXDH_PFLAG_IP, enable);
-    }
-    return 0;
+	/* 同步debug的ip状态*/
+	if (flag == ZXDH_PFLAG_ENABLE_SSHD) {
+		ZXDH_SET_PFLAG(en_priv->edev.pflags, ZXDH_PFLAG_IP, enable);
+	}
+	return 0;
 }
 
-
-static int32_t zxdh_en_set_priv_flags(struct net_device *netdev, uint32_t pflags)
+static int32_t zxdh_en_set_priv_flags(struct net_device *netdev,
+									  uint32_t pflags)
 {
-    enum zxdh_priv_flag pflag = 0;
-    int32_t err = 0;
+	enum zxdh_priv_flag pflag = 0;
+	int32_t err = 0;
 
-    for (pflag = 0; pflag < ZXDH_NUM_PFLAGS; pflag++)
-    {
-        err = zxdh_handle_pflag(netdev, pflags, pflag);
-        if (0 != err)
-        {
-            break;
-        }
-    }
+	for (pflag = 0; pflag < ZXDH_NUM_PFLAGS; pflag++) {
+		err = zxdh_handle_pflag(netdev, pflags, pflag);
+		if (0 != err) {
+			break;
+		}
+	}
 
-    return err;
+	return err;
 }
 
 static uint32_t zxdh_en_get_priv_flags(struct net_device *netdev)
 {
-    int32_t ret = 0;
-    uint32_t flag_lldp = 0;
-    uint32_t lldp_mask = 0;
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	int32_t ret = 0;
+	uint32_t flag_lldp = 0;
+	uint32_t lldp_mask = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
 
-    ret = zxdh_lldp_enable_get(&en_priv->edev, &flag_lldp);
-    if ((ret != 0) && (flag_lldp != 0) && (flag_lldp != 1))
-    {
-        LOG_ERR("zxdh_lldp_enable_get err, ret(%d), flag_lldp(%u).\n", ret, flag_lldp);
-        return en_priv->edev.pflags;
-    }
+	ret = zxdh_lldp_enable_get(&en_priv->edev, &flag_lldp);
+	if ((ret != 0) && (flag_lldp != 0) && (flag_lldp != 1)) {
+		LOG_ERR("zxdh_lldp_enable_get err, ret(%d), flag_lldp(%u).\n", ret,
+				flag_lldp);
+		return en_priv->edev.pflags;
+	}
 
-    flag_lldp = flag_lldp << ZXDH_PFLAG_ENABLE_LLDP;
+	flag_lldp = flag_lldp << ZXDH_PFLAG_ENABLE_LLDP;
 
-    lldp_mask = 0xFFFFFFFF ^ BIT(ZXDH_PFLAG_ENABLE_LLDP);
-    en_priv->edev.pflags = (en_priv->edev.pflags & lldp_mask) | flag_lldp;
+	lldp_mask = 0xFFFFFFFF ^ BIT(ZXDH_PFLAG_ENABLE_LLDP);
+	en_priv->edev.pflags = (en_priv->edev.pflags & lldp_mask) | flag_lldp;
 
-    return en_priv->edev.pflags;
+	return en_priv->edev.pflags;
 }
 
 static int zxdh_en_get_regs_len(struct net_device *netdev)
 {
 #define ZXDH_REGS_LEN (128 * 1024)
-    return ZXDH_REGS_LEN * sizeof(uint32_t);
+	return ZXDH_REGS_LEN * sizeof(uint32_t);
 }
 
-static void zxdh_en_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
+static void zxdh_en_get_regs(struct net_device *netdev,
+							 struct ethtool_regs *regs, void *p)
 {
-
 }
 
-static void zxdh_en_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
+static void zxdh_en_get_wol(struct net_device *netdev,
+							struct ethtool_wolinfo *wol)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
 
-    wol->supported = en_dev->wol_support;
-    if (wol->supported == 0)
-    {
-        return;
-    }
-    wol->wolopts = en_dev->wolopts;
+	wol->supported = en_dev->wol_support;
+	if (wol->supported == 0) {
+		return;
+	}
+	wol->wolopts = en_dev->wolopts;
 }
 
-static int zxdh_en_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
+static int zxdh_en_set_wol(struct net_device *netdev,
+						   struct ethtool_wolinfo *wol)
 {
-    return 0;
+	return 0;
 }
 
 static uint32_t zxdh_en_get_msglevel(struct net_device *netdev)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
 
-    return en_dev->msglevel;
+	return en_dev->msglevel;
 }
 
 static void zxdh_en_set_msglevel(struct net_device *netdev, uint32_t data)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    en_dev->msglevel = data;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	en_dev->msglevel = data;
 }
 
 static int zxdh_en_nway_reset(struct net_device *netdev)
 {
-    return 0;
+	return 0;
 }
 
 #ifdef HAVE_ETHTOOL_SET_PHYS_ID
-static int zxdh_en_set_phys_id(struct net_device *netdev, enum ethtool_phys_id_state state)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    union zxdh_msg msg = {0};
-
-    switch (state)
-    {
-        case ETHTOOL_ID_ACTIVE:
-        {
-            msg.payload.mac_set_msg.blink_enable = 1;
-            break;
-        }
-        case ETHTOOL_ID_INACTIVE:
-        {
-            msg.payload.mac_set_msg.blink_enable = 0;
-            break;
-        }
-        default:
-            return -EOPNOTSUPP;
-    }
-    msg.payload.hdr_to_agt.op_code = AGENT_MAC_LED_BLINK;
-    msg.payload.hdr_to_agt.phyport = en_dev->phy_port;
-    LOG_DEBUG("send phyport %d, blink_enable=%d\n", en_dev->phy_port, msg.payload.mac_set_msg.blink_enable);
-
-    return zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &msg);
+static int zxdh_en_set_phys_id(struct net_device *netdev,
+							   enum ethtool_phys_id_state state)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+
+	switch (state) {
+	case ETHTOOL_ID_ACTIVE: {
+		msg.mac_set_msg.blink_enable = 1;
+		break;
+	}
+	case ETHTOOL_ID_INACTIVE: {
+		msg.mac_set_msg.blink_enable = 0;
+		break;
+	}
+	default:
+		return -EOPNOTSUPP;
+	}
+	msg.hdr_to_agt.op_code = AGENT_MAC_LED_BLINK;
+	msg.hdr_to_agt.phyport = en_dev->phy_port;
+	LOG_DEBUG("send phyport %d, blink_enable=%d\n", en_dev->phy_port,
+			  msg.mac_set_msg.blink_enable);
+
+	return zxdh_send_command_to_specify(en_dev, MODULE_MAC, &msg, &reps);
 }
 #else
 static int zxdh_en_phys_id(struct net_device *netdev, u32 data)
 {
-    return 0;
+	return 0;
 }
 #endif /* HAVE_ETHTOOL_SET_PHYS_ID */
 
 int32_t zxdh_en_self_test_num(void)
 {
-    return 0;
+	return 0;
 }
 
 #ifdef HAVE_ETHTOOL_GET_SSET_COUNT
 static int32_t zxdh_en_get_sset_count(struct net_device *netdev, int sset)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-
-    switch (sset)
-    {
-        case ETH_SS_STATS:
-        {
-            return ZXDH_NET_PF_STATS_NUM(en_dev);
-        }
-        case ETH_SS_PRIV_FLAGS:
-        {
-            return ZXDH_NUM_PFLAGS;
-        }
-        case ETH_SS_TEST:
-        {
-            return zxdh_en_self_test_num();
-        }
-        default:
-        {
-            return -EOPNOTSUPP;
-        }
-    }
-
-    return 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+
+	switch (sset) {
+	case ETH_SS_STATS: {
+		return ZXDH_NET_PF_STATS_NUM(en_dev);
+	}
+	case ETH_SS_PRIV_FLAGS: {
+		return ZXDH_NUM_PFLAGS;
+	}
+	case ETH_SS_TEST: {
+		return zxdh_en_self_test_num();
+	}
+	default: {
+		return -EOPNOTSUPP;
+	}
+	}
+
+	return 0;
 }
 #endif
 
-static void zxdh_en_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
+static void zxdh_en_get_drvinfo(struct net_device *netdev,
+								struct ethtool_drvinfo *drvinfo)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t ret = 0;
-    uint8_t drv_name_len = 0;
-    uint8_t drv_version[MAX_DRV_VERSION_LEN] = {0};
-    uint8_t drv_version_len = 0;
-    uint16_t vport = 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t ret = 0;
+	uint8_t drv_name_len = 0;
+	uint8_t drv_version[MAX_DRV_VERSION_LEN] = { 0 };
+	uint8_t drv_version_len = 0;
+	uint16_t vport = 0;
 
-    ret = en_dev->ops->get_pf_drv_msg(en_dev->parent, drv_version, &drv_version_len);
-    if (drv_version_len > MAX_DRV_NAME_LEN)
-    {
-        LOG_ERR("drv_version_len(%hhu) greater than %u", drv_version_len, MAX_DRV_NAME_LEN);
-        drv_version_len = MAX_DRV_NAME_LEN;
-    }
+	ret = en_dev->ops->get_pf_drv_msg(en_dev->parent, drv_version,
+									  &drv_version_len);
+	if (drv_version_len > MAX_DRV_NAME_LEN) {
+		LOG_ERR("drv_version_len(%hhu) greater than %u", drv_version_len,
+				MAX_DRV_NAME_LEN);
+		drv_version_len = MAX_DRV_NAME_LEN;
+	}
 
-    vport = en_dev->vport;
-    drv_name_len = sizeof(DRV_NAME(vport));
-    if (drv_name_len > MAX_DRV_NAME_LEN)
-    {
-        LOG_ERR("drv_name_len(%hhu) greater than %u", drv_name_len, MAX_DRV_NAME_LEN);
-        drv_name_len = MAX_DRV_NAME_LEN;
-    }
+	vport = en_dev->vport;
+	drv_name_len = sizeof(DRV_NAME(vport));
+	if (drv_name_len > MAX_DRV_NAME_LEN) {
+		LOG_ERR("drv_name_len(%hhu) greater than %u", drv_name_len,
+				MAX_DRV_NAME_LEN);
+		drv_name_len = MAX_DRV_NAME_LEN;
+	}
 
-    memcpy(drvinfo->driver, DRV_NAME(vport), drv_name_len);
-    memcpy(drvinfo->version, drv_version, drv_version_len);
+	memcpy(drvinfo->driver, DRV_NAME(vport), drv_name_len);
+	memcpy(drvinfo->version, drv_version, drv_version_len);
 
-    strlcpy(drvinfo->bus_info, dev_name(en_dev->parent->parent->device), sizeof(drvinfo->bus_info));
+	strlcpy(drvinfo->bus_info, dev_name(en_dev->parent->parent->device),
+			sizeof(drvinfo->bus_info));
 
-    drvinfo->n_priv_flags = ZXDH_NUM_PFLAGS;
-    drvinfo->n_stats = ZXDH_NET_PF_STATS_NUM(en_dev);
-    drvinfo->eedump_len = zxdh_en_get_eeprom_len(netdev);
-    drvinfo->regdump_len = zxdh_en_get_regs_len(netdev);
-    drvinfo->testinfo_len = zxdh_en_self_test_num();
+	drvinfo->n_priv_flags = ZXDH_NUM_PFLAGS;
+	drvinfo->n_stats = ZXDH_NET_PF_STATS_NUM(en_dev);
+	drvinfo->eedump_len = zxdh_en_get_eeprom_len(netdev);
+	drvinfo->regdump_len = zxdh_en_get_regs_len(netdev);
+	drvinfo->testinfo_len = zxdh_en_self_test_num();
 
-    memcpy(drvinfo->fw_version, en_dev->fw_version, en_dev->fw_version_len);
+	memcpy(drvinfo->fw_version, en_dev->fw_version, en_dev->fw_version_len);
 }
 
 int32_t zxdh_stats_update(struct zxdh_en_device *en_dev)
 {
-    uint16_t i = 0;
-    int32_t ret = 0;
-
-    ret = zxdh_vport_stats_get(en_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_mac_stats_get failed, ret: %d\n", ret);
-        return -1;
-    }
+	uint16_t i = 0;
+	int32_t ret = 0;
 
-    ret = zxdh_mac_stats_get(en_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_mac_stats_get failed, ret: %d\n", ret);
-        return -1;
-    }
-
-    memset(&en_dev->hw_stats.netdev_stats, 0, sizeof(en_dev->hw_stats.netdev_stats));
-    for (i = 0; i < en_dev->curr_queue_pairs; i++)
-    {
-        /* queue software statistics */
-        en_dev->hw_stats.q_stats[i].q_rx_pkts = en_dev->rq[i].stats.packets;
-        en_dev->hw_stats.q_stats[i].q_tx_pkts = en_dev->sq[i].stats.packets;
-        en_dev->hw_stats.q_stats[i].q_rx_bytes = en_dev->rq[i].stats.bytes;
-        en_dev->hw_stats.q_stats[i].q_tx_bytes = en_dev->sq[i].stats.bytes;
+#if STATS_CLEAR_AFTER_READ
+	memset(&en_dev->hw_stats, 0, sizeof(struct zxdh_en_hw_stats));
+#endif
 
-        en_dev->hw_stats.netdev_stats.rx_packets += en_dev->rq[i].stats.packets;
-        en_dev->hw_stats.netdev_stats.tx_packets += en_dev->sq[i].stats.packets;
-        en_dev->hw_stats.netdev_stats.rx_bytes += en_dev->rq[i].stats.bytes;
-        en_dev->hw_stats.netdev_stats.tx_bytes += en_dev->sq[i].stats.bytes;
-        en_dev->hw_stats.netdev_stats.tx_queue_wake += en_dev->hw_stats.q_stats[i].q_tx_wake;
-        en_dev->hw_stats.netdev_stats.tx_queue_stopped += en_dev->hw_stats.q_stats[i].q_tx_stopped;
-        en_dev->hw_stats.netdev_stats.tx_queue_dropped += en_dev->hw_stats.q_stats[i].q_tx_dropped;
-    }
+	ret = zxdh_vport_stats_get(en_dev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_mac_stats_get failed, ret: %d\n", ret);
+		return -1;
+	}
+
+	ret = zxdh_mac_stats_get(en_dev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_mac_stats_get failed, ret: %d\n", ret);
+		return -1;
+	}
+
+	memset(&en_dev->hw_stats.netdev_stats, 0,
+		   sizeof(en_dev->hw_stats.netdev_stats));
+	for (i = 0; i < en_dev->curr_queue_pairs; i++) {
+		/* queue software statistics */
+		en_dev->hw_stats.q_stats[i].q_rx_pkts = en_dev->rq[i].stats.packets;
+		en_dev->hw_stats.q_stats[i].q_tx_pkts = en_dev->sq[i].stats.packets;
+		en_dev->hw_stats.q_stats[i].q_rx_bytes = en_dev->rq[i].stats.bytes;
+		en_dev->hw_stats.q_stats[i].q_tx_bytes = en_dev->sq[i].stats.bytes;
+
+		en_dev->hw_stats.netdev_stats.rx_packets += en_dev->rq[i].stats.packets;
+		en_dev->hw_stats.netdev_stats.tx_packets += en_dev->sq[i].stats.packets;
+		en_dev->hw_stats.netdev_stats.rx_bytes += en_dev->rq[i].stats.bytes;
+		en_dev->hw_stats.netdev_stats.tx_bytes += en_dev->sq[i].stats.bytes;
+		en_dev->hw_stats.netdev_stats.tx_queue_wake +=
+				en_dev->hw_stats.q_stats[i].q_tx_wake;
+		en_dev->hw_stats.netdev_stats.tx_queue_stopped +=
+				en_dev->hw_stats.q_stats[i].q_tx_stopped;
+		en_dev->hw_stats.netdev_stats.tx_queue_dropped +=
+				en_dev->hw_stats.q_stats[i].q_tx_dropped;
+
+		/* below stats increased when queue event occur
+    en_dev->hw_stats.q_stats[i].q_tx_stopped
+    en_dev->hw_stats.q_stats[i].q_tx_wake
+    en_dev->hw_stats.q_stats[i].q_tx_dropped */
+
+#if STATS_CLEAR_AFTER_READ
+		memset(&en_dev->sq[i].stats, 0, sizeof(struct virtnet_sq_stats));
+		memset(&en_dev->rq[i].stats, 0, sizeof(struct virtnet_rq_stats));
+#endif
+	}
+
+#ifdef ZXDH_MSGQ
+	if (en_dev->need_msgq) {
+		LOG_DEBUG("msgq_rx_pkts: %lld\n", en_dev->rq[i].stats.packets);
+		LOG_DEBUG("msgq_rx_kicks: %lld\n", en_dev->rq[i].stats.kicks);
+		LOG_DEBUG("msgq_rx_bytes: %lld\n", en_dev->rq[i].stats.bytes);
+		LOG_DEBUG("msgq_rx_drops: %lld\n", en_dev->rq[i].stats.drops);
+		LOG_DEBUG("msgq_rx_errs: %lld\n", en_dev->rq[i].stats.xdp_drops);
+
+		LOG_DEBUG("msgq_tx_pkts: %lld\n", en_dev->sq[i].stats.packets);
+		LOG_DEBUG("msgq_tx_bytes: %lld\n", en_dev->sq[i].stats.bytes);
+		LOG_DEBUG("msgq_tx_kicks: %lld\n", en_dev->sq[i].stats.kicks);
+		LOG_DEBUG("msgq_tx_timeouts: %lld\n", en_dev->sq[i].stats.tx_timeouts);
+		LOG_DEBUG("msgq_tx_errs: %lld\n", en_dev->sq[i].stats.xdp_tx_drops);
+	}
+#endif
 
-    return ret;
+	return ret;
 }
 
-static void zxdh_en_get_ethtool_stats(struct net_device *netdev, struct ethtool_stats *stats, u64 *data)
+static void zxdh_en_get_ethtool_stats(struct net_device *netdev,
+									  struct ethtool_stats *stats, u64 *data)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    uint32_t offset = ZXDH_NETDEV_STATS_NUM + ZXDH_MAC_STATS_NUM + ZXDH_VPORT_STATS_NUM;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t offset =
+			ZXDH_NETDEV_STATS_NUM + ZXDH_MAC_STATS_NUM + ZXDH_VPORT_STATS_NUM;
 
-    zxdh_stats_update(en_dev);
-    memcpy(data, &en_dev->hw_stats, ZXDH_NET_PF_STATS_NUM(en_dev) * sizeof(uint64_t));
-    memcpy(data + offset, en_dev->hw_stats.q_stats, (en_dev->curr_queue_pairs * ZXDH_QUEUE_STATS_NUM) * sizeof(uint64_t));
+	zxdh_stats_update(en_dev);
+	memcpy(data, &en_dev->hw_stats,
+		   ZXDH_NET_PF_STATS_NUM(en_dev) * sizeof(uint64_t));
+	memcpy(data + offset, en_dev->hw_stats.q_stats,
+		   (en_dev->curr_queue_pairs * ZXDH_QUEUE_STATS_NUM) *
+				   sizeof(uint64_t));
 
-    return;
+	return;
 }
 
-static int zxdh_en_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ec)
+static int zxdh_en_get_coalesce(struct net_device *netdev,
+								struct ethtool_coalesce *ec)
 {
-    return 0;
+	return 0;
 }
 
-static int zxdh_en_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ec)
+static int zxdh_en_set_coalesce(struct net_device *netdev,
+								struct ethtool_coalesce *ec)
 {
-    return 0;
+	return 0;
 }
 
-static int zxdh_en_get_ts_info(struct net_device *netdev, struct ethtool_ts_info *info)
+static int zxdh_en_get_ts_info(struct net_device *netdev,
+							   struct ethtool_ts_info *info)
 {
-    return 0;
+	return 0;
 }
 
 #ifdef CONFIG_PM_RUNTIME
 static int zxdh_en_ethtool_begin(struct net_device *netdev)
 {
-    return 0;
+	return 0;
 }
 
 static void zxdh_en_ethtool_complete(struct net_device *netdev)
 {
-
 }
 #endif
 
 #ifndef HAVE_NDO_SET_FEATURES
 static int zxdh_en_get_rx_csum(struct net_device *netdev)
 {
-    return 0;
+	return 0;
 }
 
 static int zxdh_en_set_rx_csum(struct net_device *netdev, u32 data)
 {
-    return 0;
+	return 0;
 }
 
 static int zxdh_en_set_tx_csum(struct net_device *netdev, u32 data)
 {
-    return 0;
+	return 0;
 }
 
 #ifdef NETIF_F_TSO
 static int zxdh_en_set_tso(struct net_device *netdev, u32 data)
 {
-    return 0;
+	return 0;
 }
 #endif /* NETIF_F_TSO */
 
 #ifdef ETHTOOL_GFLAGS
 static int zxdh_en_set_flags(struct net_device *netdev, u32 data)
 {
-    return 0;
+	return 0;
 }
 #endif /* ETHTOOL_GFLAGS */
 #endif /* HAVE_NDO_SET_FEATURES */
 
 static int zxdh_en_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
 {
-    return 0;
+	return 0;
 }
 
 static int zxdh_en_set_eee(struct net_device *netdev, struct ethtool_eee *edata)
 {
-    return 0;
+	return 0;
 }
 #ifdef ETHTOOL_GRXFHINDIR
 #ifdef HAVE_ETHTOOL_GRXFHINDIR_SIZE
 static u32 zxdh_en_get_rxfh_indir_size(struct net_device *netdev)
 {
-    return ZXDH_INDIR_RQT_SIZE;
+	return ZXDH_INDIR_RQT_SIZE;
 }
 
 static u32 zxdh_en_get_rxfh_key_size(struct net_device *netdev)
 {
-    return ZXDH_NET_HASH_KEY_SIZE;
+	return ZXDH_NET_HASH_KEY_SIZE;
 }
 
 #if (defined(ETHTOOL_GRSSH) && !defined(HAVE_ETHTOOL_GSRSSH))
 #ifdef HAVE_RXFH_HASHFUNC
-static int zxdh_en_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc)
+static int zxdh_en_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
+							u8 *hfunc)
 #else
 static int zxdh_en_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key)
 #endif /* HAVE_RXFH_HASHFUNC */
@@ -1386,612 +1339,572 @@ static int zxdh_en_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key)
 static int zxdh_en_get_rxfh_indir(struct net_device *netdev, u32 *indir)
 #endif /* HAVE_ETHTOOL_GSRSSH */
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    union zxdh_msg msg = {0};
-    int32_t ret = 0;
-    uint8_t func = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    LOG_INFO("zxdh_en_get_rxfh start\n");
-    if (indir != NULL)
-    {
-        memcpy(indir, en_dev->indir_rqt, sizeof(uint32_t) * ZXDH_INDIR_RQT_SIZE);
-    }
-
-    if (key != NULL)
-    {
-        LOG_INFO("get key is called\n");
-        if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-        {
-            ret = dpp_thash_key_get(&pf_info, key, ZXDH_NET_HASH_KEY_SIZE);
-        }
-        else
-        {
-            msg.payload.hdr.op_code = ZXDH_THASH_KEY_GET;
-            msg.payload.hdr.vport = en_dev->vport;
-            msg.payload.hdr.pcie_id = en_dev->pcie_id;
-            ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true);
-            if (ret == 0)
-            {
-                memcpy(key, msg.reps.thash_key_set_msg.key_map, ZXDH_NET_HASH_KEY_SIZE);
-            }
-        }
-    }
-
-    if (hfunc != NULL)
-    {
-        func = en_dev->hash_func;
-        switch (func)
-        {
-            case ZXDH_FUNC_TOP:
-            {
-                *hfunc = ETH_RSS_HASH_TOP;
-                break;
-            }
-            case ZXDH_FUNC_XOR:
-            {
-                *hfunc = ETH_RSS_HASH_XOR;
-                break;
-            }
-            case ZXDH_FUNC_CRC32:
-            {
-                *hfunc = ETH_RSS_HASH_CRC32;
-                break;
-            }
-            default:
-            {
-                return -EOPNOTSUPP;
-            }
-        }
-    }
-
-    return ret;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	int32_t ret = 0;
+	uint8_t func = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	LOG_INFO("zxdh_en_get_rxfh start\n");
+	if (indir != NULL) {
+		memcpy(indir, en_dev->indir_rqt,
+			   sizeof(uint32_t) * ZXDH_INDIR_RQT_SIZE);
+	}
+
+	if (key != NULL) {
+		LOG_INFO("get key is called\n");
+		if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+			ret = dpp_thash_key_get(&pf_info, key, ZXDH_NET_HASH_KEY_SIZE);
+		} else {
+			msg.hdr.op_code = ZXDH_THASH_KEY_GET;
+			msg.hdr.vport = en_dev->vport;
+			msg.hdr.pcie_id = en_dev->pcie_id;
+			ret = en_dev->ops->msg_send_cmd(
+					en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &reps, true);
+			if (ret == 0) {
+				memcpy(key, reps.thash_key_set_msg.key_map,
+					   ZXDH_NET_HASH_KEY_SIZE);
+			}
+		}
+	}
+
+	if (hfunc != NULL) {
+		func = en_dev->hash_func;
+		switch (func) {
+		case ZXDH_FUNC_TOP: {
+			*hfunc = ETH_RSS_HASH_TOP;
+			break;
+		}
+		case ZXDH_FUNC_XOR: {
+			*hfunc = ETH_RSS_HASH_XOR;
+			break;
+		}
+		case ZXDH_FUNC_CRC32: {
+			*hfunc = ETH_RSS_HASH_CRC32;
+			break;
+		}
+		default: {
+			return -EOPNOTSUPP;
+		}
+		}
+	}
+
+	return ret;
 }
 #else
-static int zxdh_en_get_rxfh_indir(struct net_device *netdev, struct ethtool_rxfh_indir *indir)
+static int zxdh_en_get_rxfh_indir(struct net_device *netdev,
+								  struct ethtool_rxfh_indir *indir)
 {
-    return 0;
+	return 0;
 }
 #endif /* HAVE_ETHTOOL_GRXFHINDIR_SIZE */
 #endif /* ETHTOOL_GRXFHINDIR */
 
-static int32_t zxdh_indir_to_queue_map(struct zxdh_en_device *en_dev, const uint32_t *indir)
-{
-    uint32_t *queue_map = NULL;
-    int32_t err = 0;
-    uint16_t i = 0;
-    uint16_t j = 0;
-
-    queue_map = kzalloc(ZXDH_INDIR_RQT_SIZE * sizeof(uint32_t), GFP_KERNEL);
-    if (queue_map == NULL)
-    {
-        LOG_ERR("queue_map is NULL\n");
-        return -ENOMEM;
-    }
-    for (i = 0; i < ZXDH_INDIR_RQT_SIZE; i++)
-    {
-        j = indir[i];
-        queue_map[i] = en_dev->phy_index[2 * j];
-    }
-    err = zxdh_rxfh_set(en_dev, queue_map);
-    kfree(queue_map);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_rxfh_set failed: %d\n", err);
-        return err;
-    }
-
-    memcpy(en_dev->indir_rqt, indir, ZXDH_INDIR_RQT_SIZE * sizeof(uint32_t));
-
-    return err;
+static int32_t zxdh_indir_to_queue_map(struct zxdh_en_device *en_dev,
+									   const uint32_t *indir)
+{
+	uint32_t *queue_map = NULL;
+	int32_t err = 0;
+	uint16_t i = 0;
+	uint16_t j = 0;
+
+	queue_map = kzalloc(ZXDH_INDIR_RQT_SIZE * sizeof(uint32_t), GFP_KERNEL);
+	if (queue_map == NULL) {
+		LOG_ERR("queue_map is NULL\n");
+		return -ENOMEM;
+	}
+	for (i = 0; i < ZXDH_INDIR_RQT_SIZE; i++) {
+		j = indir[i];
+		queue_map[i] = en_dev->phy_index[2 * j];
+	}
+	err = zxdh_rxfh_set(en_dev, queue_map);
+	kfree(queue_map);
+	if (err != 0) {
+		LOG_ERR("zxdh_rxfh_set failed: %d\n", err);
+		return err;
+	}
+
+	memcpy(en_dev->indir_rqt, indir, ZXDH_INDIR_RQT_SIZE * sizeof(uint32_t));
+
+	return err;
 }
 
 #ifdef HAVE_ETHTOOL_GRXFHINDIR_SIZE
 #if (defined(ETHTOOL_GRSSH) && !defined(HAVE_ETHTOOL_GSRSSH))
 #ifdef HAVE_RXFH_HASHFUNC
-static int zxdh_en_set_rxfh(struct net_device *netdev, const u32 *indir, const u8 *key, const u8 hfunc)
+static int zxdh_en_set_rxfh(struct net_device *netdev, const u32 *indir,
+							const u8 *key, const u8 hfunc)
 #else
-static int zxdh_en_set_rxfh(struct net_device *netdev, const u32 *indir, const u8 *key)
+static int zxdh_en_set_rxfh(struct net_device *netdev, const u32 *indir,
+							const u8 *key)
 #endif /* HAVE_RXFH_HASHFUNC */
 #else
 static int zxdh_en_set_rxfh_indir(struct net_device *netdev, const u32 *indir)
 #endif /* HAVE_ETHTOOL_GSRSSH */
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    union zxdh_msg msg = {0};
-    int32_t ret = 0;
-    uint8_t func = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    LOG_INFO("zxdh_en_set_rxfh_indir start\n");
-    switch (hfunc)
-    {
-        case ETH_RSS_HASH_NO_CHANGE:
-        {
-            break;
-        }
-        case ETH_RSS_HASH_TOP:
-        {
-            func = ZXDH_FUNC_TOP;
-            break;
-        }
-        case ETH_RSS_HASH_XOR:
-        {
-            func = ZXDH_FUNC_XOR;
-            break;
-        }
-        case ETH_RSS_HASH_CRC32:
-        {
-            func = ZXDH_FUNC_CRC32;
-            break;
-        }
-        default:
-        {
-            return -EOPNOTSUPP;
-        }
-    }
-
-    if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && (func != en_dev->hash_func))
-    {
-        LOG_DEBUG("func: %u\n", func);
-        if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-        {
-            ret = dpp_vport_hash_funcs_set(&pf_info, func);
-        }
-        else
-        {
-            msg.payload.hdr.op_code = ZXDH_HASH_FUNC_SET;
-            msg.payload.hdr.vport = en_dev->vport;
-            msg.payload.hdr.pcie_id = en_dev->pcie_id;
-            msg.payload.hfunc_set_msg.func = func;
-            ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true);
-        }
-        if (ret != 0)
-        {
-            LOG_ERR("hunc set failed: %d", ret);
-            return ret;
-        }
-        en_dev->hash_func = func;
-    }
-
-    if (indir != NULL)
-    {
-        LOG_DEBUG("set indir is called\n");
-        ret = zxdh_indir_to_queue_map(en_dev, indir);
-        if (ret != 0)
-        {
-            LOG_ERR("indir set failed: %d", ret);
-            return ret;
-        }
-    }
-
-    if (key != NULL)
-    {
-        LOG_DEBUG("set thash key is called\n");
-        if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-        {
-            ret = dpp_thash_key_set(&pf_info, (uint8_t *)key, ZXDH_NET_HASH_KEY_SIZE);
-        }
-        else
-        {
-            memset(&msg, 0, sizeof(union zxdh_msg));
-            msg.payload.hdr.op_code = ZXDH_THASH_KEY_SET;
-            msg.payload.hdr.vport = en_dev->vport;
-            msg.payload.hdr.pcie_id = en_dev->pcie_id;
-            memcpy(msg.payload.thash_key_set_msg.key_map, key, ZXDH_NET_HASH_KEY_SIZE);
-            ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true);
-        }
-    }
-
-    return ret;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	int32_t ret = 0;
+	uint8_t func = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	LOG_INFO("zxdh_en_set_rxfh_indir start\n");
+	switch (hfunc) {
+	case ETH_RSS_HASH_NO_CHANGE: {
+		break;
+	}
+	case ETH_RSS_HASH_TOP: {
+		func = ZXDH_FUNC_TOP;
+		break;
+	}
+	case ETH_RSS_HASH_XOR: {
+		func = ZXDH_FUNC_XOR;
+		break;
+	}
+	case ETH_RSS_HASH_CRC32: {
+		func = ZXDH_FUNC_CRC32;
+		break;
+	}
+	default: {
+		return -EOPNOTSUPP;
+	}
+	}
+
+	if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && (func != en_dev->hash_func)) {
+		LOG_DEBUG("func: %u\n", func);
+		if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+			ret = dpp_vport_hash_funcs_set(&pf_info, func);
+		} else {
+			msg.hdr.op_code = ZXDH_HASH_FUNC_SET;
+			msg.hdr.vport = en_dev->vport;
+			msg.hdr.pcie_id = en_dev->pcie_id;
+			msg.hfunc_set_msg.func = func;
+			ret = en_dev->ops->msg_send_cmd(
+					en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &reps, true);
+		}
+		if (ret != 0) {
+			LOG_ERR("hunc set failed: %d", ret);
+			return ret;
+		}
+		en_dev->hash_func = func;
+	}
+
+	if (indir != NULL) {
+		LOG_DEBUG("set indir is called\n");
+		ret = zxdh_indir_to_queue_map(en_dev, indir);
+		if (ret != 0) {
+			LOG_ERR("indir set failed: %d", ret);
+			return ret;
+		}
+	}
+
+	if (key != NULL) {
+		LOG_DEBUG("set thash key is called\n");
+		if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+			ret = dpp_thash_key_set(&pf_info, (uint8_t *)key,
+									ZXDH_NET_HASH_KEY_SIZE);
+		} else {
+			memset(&msg, 0, sizeof(zxdh_msg_info));
+			msg.hdr.op_code = ZXDH_THASH_KEY_SET;
+			msg.hdr.vport = en_dev->vport;
+			msg.hdr.pcie_id = en_dev->pcie_id;
+			memcpy(msg.thash_key_set_msg.key_map, key, ZXDH_NET_HASH_KEY_SIZE);
+			ret = en_dev->ops->msg_send_cmd(
+					en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &reps, true);
+		}
+	}
+
+	return ret;
 }
 #else
-static int zxdh_en_set_rxfh_indir(struct net_device *netdev, struct ethtool_cmd *ecmd)
+static int zxdh_en_set_rxfh_indir(struct net_device *netdev,
+								  struct ethtool_cmd *ecmd)
 {
-    return 0;
+	return 0;
 }
 #endif
 #ifdef ETHTOOL_GCHANNELS
-static void zxdh_en_get_channels(struct net_device *netdev, struct ethtool_channels *ch)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    union zxdh_msg msg = {0};
-    int32_t err = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    ch->max_combined = max_pairs;
-    ch->combined_count = en_dev->curr_queue_pairs;
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        err = dpp_rxfh_get(&pf_info, msg.payload.rxfh_set_msg.queue_map, ZXDH_INDIR_RQT_SIZE);
-        if (err != 0)
-        {
-            LOG_ERR("dpp_rxfh_get failed: %d\n", err);
-            return;
-        }
-
-        LOG_DEBUG("*******pf_queue_map*******\n");
-        zxdh_u32_array_print(msg.payload.rxfh_set_msg.queue_map, ZXDH_INDIR_RQT_SIZE);
-    }
-    else
-    {
-        msg.payload.hdr.op_code = ZXDH_RXFH_GET;
-        msg.payload.hdr.vport = en_dev->vport;
-        msg.payload.hdr.pcie_id = en_dev->pcie_id;
-        err = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true);
-        if (err != 0)
-        {
-            LOG_ERR("dpp_rxfh_get failed: %d\n", err);
-            return;
-        }
-
-        LOG_DEBUG("*******vf_queue_map*******\n");
-        zxdh_u32_array_print(msg.reps.rxfh_get_msg.queue_map, ZXDH_INDIR_RQT_SIZE);
-    }
+static void zxdh_en_get_channels(struct net_device *netdev,
+								 struct ethtool_channels *ch)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	zxdh_msg_info msg = { 0 };
+	int32_t err = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	ch->max_combined = max_pairs;
+	ch->combined_count = en_dev->curr_queue_pairs;
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		err = dpp_rxfh_get(&pf_info, msg.rxfh_set_msg.queue_map,
+						   ZXDH_INDIR_RQT_SIZE);
+		if (err != 0) {
+			LOG_ERR("dpp_rxfh_get failed: %d\n", err);
+			return;
+		}
+
+		LOG_DEBUG("*******pf_queue_map*******\n");
+		zxdh_u32_array_print(msg.rxfh_set_msg.queue_map, ZXDH_INDIR_RQT_SIZE);
+	} else {
+		msg.hdr.op_code = ZXDH_RXFH_GET;
+		msg.hdr.vport = en_dev->vport;
+		msg.hdr.pcie_id = en_dev->pcie_id;
+		err = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF,
+										&msg, &msg, true);
+		if (err != 0) {
+			LOG_ERR("dpp_rxfh_get failed: %d\n", err);
+			return;
+		}
+	}
 }
 #endif /* ETHTOOL_GCHANNELS */
 
-int32_t zxdh_num_channels_changed(struct zxdh_en_device *en_dev, uint16_t num_changed)
+int32_t zxdh_num_channels_changed(struct zxdh_en_device *en_dev,
+								  uint16_t num_changed)
 {
-    uint32_t indir[ZXDH_INDIR_RQT_SIZE] = {0};
-    int32_t err = 0;
-    uint16_t i = 0;
+	uint32_t indir[ZXDH_INDIR_RQT_SIZE] = { 0 };
+	int32_t err = 0;
+	uint16_t i = 0;
 
-    if (!netif_is_rxfh_configured(en_dev->netdev))
-    {
-        LOG_INFO("indir_is_default\n");
-        for (i = 0; i < ZXDH_INDIR_RQT_SIZE; ++i)
-        {
-            indir[i] = i % num_changed;
-        }
+	LOG_DEBUG("num_changed: %d\n", num_changed);
+	if (!netif_is_rxfh_configured(en_dev->netdev)) {
+		LOG_INFO("indir_is_default\n");
+		for (i = 0; i < ZXDH_INDIR_RQT_SIZE; ++i) {
+			indir[i] = i % num_changed;
+		}
 
-        err = zxdh_indir_to_queue_map(en_dev, indir);
-        if (err != 0)
-        {
-            LOG_ERR("zxdh_indir_to_queue_map failed: %d\n", err);
-            return err;
-        }
-    }
+		err = zxdh_indir_to_queue_map(en_dev, indir);
+		if (err != 0) {
+			LOG_ERR("zxdh_indir_to_queue_map failed: %d\n", err);
+			return err;
+		}
+	}
 
-    en_dev->curr_queue_pairs = num_changed;
+	en_dev->curr_queue_pairs = num_changed;
 
-    return err;
+	return err;
 }
 
 #ifdef ETHTOOL_SCHANNELS
-static int zxdh_en_set_channels(struct net_device *netdev, struct ethtool_channels *ch)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    int32_t ret = 0;
-
-    LOG_INFO("zxdh_en_set_channels start\n");
-    /* verify that the number of channels does not invalidate any current
-     * flow director rules
-     */
-    //TODO
-
-    /* We don't support separate rx/tx channels.
-     * We don't allow setting 'other' channels.
-     */
-    if (ch->rx_count || ch->tx_count || ch->other_count)
-    {
-        LOG_ERR("not supported\n");
-        return -EINVAL;
-    }
-
-    if ((ch->combined_count > max_pairs) || (ch->combined_count == 0))
-    {
-        LOG_ERR("invalid para\n");
-        return -EINVAL;
-    }
-
-    if (ch->combined_count == en_dev->curr_queue_pairs)
-    {
-        return 0;
-    }
-
-    ret = zxdh_num_channels_changed(en_dev, ch->combined_count);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_num_channels_changed failed: %d\n", ret);
-        return -1;
-    }
-
-    netif_set_real_num_tx_queues(netdev, en_dev->curr_queue_pairs);
-    netif_set_real_num_rx_queues(netdev, en_dev->curr_queue_pairs);
-
-    return 0;
+static int zxdh_en_set_channels(struct net_device *netdev,
+								struct ethtool_channels *ch)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t ret = 0;
+
+	LOG_INFO("zxdh_en_set_channels start\n");
+	/* verify that the number of channels does not invalidate any current
+   * flow director rules
+   */
+	// TODO
+
+	/* We don't support separate rx/tx channels.
+   * We don't allow setting 'other' channels.
+   */
+	if (ch->rx_count || ch->tx_count || ch->other_count) {
+		LOG_ERR("not supported\n");
+		return -EINVAL;
+	}
+
+	if ((ch->combined_count > max_pairs) || (ch->combined_count == 0)) {
+		LOG_ERR("invalid para\n");
+		return -EINVAL;
+	}
+
+	if (ch->combined_count == en_dev->curr_queue_pairs) {
+		return 0;
+	}
+
+	ret = zxdh_num_channels_changed(en_dev, ch->combined_count);
+	if (ret != 0) {
+		LOG_ERR("zxdh_num_channels_changed failed: %d\n", ret);
+		return -1;
+	}
+
+	netif_set_real_num_tx_queues(netdev, en_dev->curr_queue_pairs);
+	netif_set_real_num_rx_queues(netdev, en_dev->curr_queue_pairs);
+
+	return 0;
 }
 #endif
 
-static int zxdh_en_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
+static int zxdh_en_get_rxnfc(struct net_device *netdev,
+							 struct ethtool_rxnfc *cmd,
 #ifdef HAVE_ETHTOOL_GET_RXNFC_VOID_RULE_LOCS
-                             void *rule_locs)
+							 void *rule_locs)
 #else
-                             u32 *rule_locs)
+							 u32 *rule_locs)
 #endif
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    union zxdh_msg msg = {0};
-    uint32_t hash_mode = 0;
-    int32_t ret = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    LOG_INFO("zxdh_en_get_rxnfc start\n");
-    if (cmd->cmd == ETHTOOL_GRXRINGS)
-    {
-        cmd->data = en_dev->curr_queue_pairs;
-        return 0;
-    }
-
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        ret = dpp_rx_flow_hash_get(&pf_info, &hash_mode);
-    }
-    else
-    {
-        msg.payload.hdr.op_code = ZXDH_RX_FLOW_HASH_GET;
-        msg.payload.hdr.vport = en_dev->vport;
-        msg.payload.hdr.pcie_id = en_dev->pcie_id;
-        ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true);
-        hash_mode = msg.reps.rx_flow_hash_set_msg.hash_mode;
-    }
-    if (ret != 0)
-    {
-        return ret;
-    }
-
-    LOG_DEBUG("hash_mode: %u\n", hash_mode);
-    switch (hash_mode)
-    {
-        case ZXDH_NET_RX_FLOW_HASH_MV:
-        {
-            cmd->data = RXH_L2DA + RXH_VLAN;
-            break;
-        }
-        case ZXDH_NET_RX_FLOW_HASH_SDT:
-        {
-            cmd->data = RXH_L3_PROTO + RXH_IP_SRC + RXH_IP_DST;
-            break;
-        }
-        case ZXDH_NET_RX_FLOW_HASH_SDFNT:
-        {
-            cmd->data = RXH_L3_PROTO + RXH_IP_SRC + RXH_IP_DST + RXH_L4_B_0_1 + RXH_L4_B_2_3;
-            break;
-        }
-        default:
-        {
-            LOG_ERR("invalid hash_mode\n");
-            return -1;
-        }
-    }
-
-    return 0;
-}
-
-static int zxdh_en_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
-{
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    union zxdh_msg msg = {0};
-    uint32_t hash_mode = 0;
-    int32_t ret = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = en_dev->slot_id;
-    pf_info.vport = en_dev->vport;
-
-    LOG_INFO("zxdh_en_set_rxnfc start\n");
-    switch (cmd->data)
-    {
-        /* input parameter mv */
-        case (RXH_L2DA + RXH_VLAN):
-        {
-            hash_mode = ZXDH_NET_RX_FLOW_HASH_MV;
-            break;
-        }
-        /* input parameter sdt */
-        case (RXH_L3_PROTO + RXH_IP_SRC + RXH_IP_DST):
-        {
-            hash_mode = ZXDH_NET_RX_FLOW_HASH_SDT;
-            break;
-        }
-        /* input parameter sdfnt  */
-        case (RXH_L3_PROTO + RXH_IP_SRC + RXH_IP_DST + RXH_L4_B_0_1 + RXH_L4_B_2_3):
-        {
-            hash_mode = ZXDH_NET_RX_FLOW_HASH_SDFNT;
-            break;
-        }
-        default:
-        {
-            LOG_ERR("invalid para, support mv, sdt, sdfnt\n");
-            return -EOPNOTSUPP;
-        }
-    }
-
-    LOG_DEBUG("hash_mode: %u\n", hash_mode);
-    if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF)
-    {
-        ret = dpp_rx_flow_hash_set(&pf_info, hash_mode);
-    }
-    else
-    {
-        msg.payload.hdr.op_code = ZXDH_RX_FLOW_HASH_SET;
-        msg.payload.hdr.vport = en_dev->vport;
-        msg.payload.hdr.pcie_id = en_dev->pcie_id;
-        msg.payload.rx_flow_hash_set_msg.hash_mode = hash_mode;
-        ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true);
-    }
-
-    return ret;
-}
-
-static const struct ethtool_ops zxdh_en_ethtool_ops =
-{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	uint32_t hash_mode = 0;
+	int32_t ret = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	LOG_INFO("zxdh_en_get_rxnfc start\n");
+	if (cmd->cmd == ETHTOOL_GRXRINGS) {
+		cmd->data = en_dev->curr_queue_pairs;
+		return 0;
+	}
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		ret = dpp_rx_flow_hash_get(&pf_info, &hash_mode);
+	} else {
+		msg.hdr.op_code = ZXDH_RX_FLOW_HASH_GET;
+		msg.hdr.vport = en_dev->vport;
+		msg.hdr.pcie_id = en_dev->pcie_id;
+		ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF,
+										&msg, &reps, true);
+		hash_mode = reps.rx_flow_hash_set_msg.hash_mode;
+	}
+	if (ret != 0) {
+		return ret;
+	}
+
+	LOG_DEBUG("hash_mode: %u\n", hash_mode);
+	switch (hash_mode) {
+	case ZXDH_NET_RX_FLOW_HASH_MV: {
+		cmd->data = RXH_L2DA + RXH_VLAN;
+		break;
+	}
+	case ZXDH_NET_RX_FLOW_HASH_SDT: {
+		cmd->data = RXH_L3_PROTO + RXH_IP_SRC + RXH_IP_DST;
+		break;
+	}
+	case ZXDH_NET_RX_FLOW_HASH_SDFNT: {
+		cmd->data = RXH_L3_PROTO + RXH_IP_SRC + RXH_IP_DST + RXH_L4_B_0_1 +
+					RXH_L4_B_2_3;
+		break;
+	}
+	default: {
+		LOG_ERR("invalid hash_mode\n");
+		return -1;
+	}
+	}
+
+	return 0;
+}
+
+static int zxdh_en_set_rxnfc(struct net_device *netdev,
+							 struct ethtool_rxnfc *cmd)
+{
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	uint32_t hash_mode = 0;
+	int32_t ret = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	LOG_INFO("zxdh_en_set_rxnfc start\n");
+	switch (cmd->data) {
+	/* input parameter mv */
+	case (RXH_L2DA + RXH_VLAN): {
+		hash_mode = ZXDH_NET_RX_FLOW_HASH_MV;
+		break;
+	}
+	/* input parameter sdt */
+	case (RXH_L3_PROTO + RXH_IP_SRC + RXH_IP_DST): {
+		hash_mode = ZXDH_NET_RX_FLOW_HASH_SDT;
+		break;
+	}
+	/* input parameter sdfnt  */
+	case (RXH_L3_PROTO + RXH_IP_SRC + RXH_IP_DST + RXH_L4_B_0_1 +
+		  RXH_L4_B_2_3): {
+		hash_mode = ZXDH_NET_RX_FLOW_HASH_SDFNT;
+		break;
+	}
+	default: {
+		LOG_ERR("invalid para, support mv, sdt, sdfnt\n");
+		return -EOPNOTSUPP;
+	}
+	}
+
+	LOG_DEBUG("hash_mode: %u\n", hash_mode);
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		ret = dpp_rx_flow_hash_set(&pf_info, hash_mode);
+	} else {
+		msg.hdr.op_code = ZXDH_RX_FLOW_HASH_SET;
+		msg.hdr.vport = en_dev->vport;
+		msg.hdr.pcie_id = en_dev->pcie_id;
+		msg.rx_flow_hash_set_msg.hash_mode = hash_mode;
+		ret = en_dev->ops->msg_send_cmd(en_dev->parent, MODULE_VF_BAR_MSG_TO_PF,
+										&msg, &reps, true);
+	}
+
+	return ret;
+}
+
+static const struct ethtool_ops zxdh_en_ethtool_ops = {
 #ifdef HAVE_ETHTOOL_COALESCE_PARAMS_SUPPORT
-    .supported_coalesce_params = ETHTOOL_COALESCE_MAX_FRAMES, //ETHTOOL_COALESCE_USECS,
+	.supported_coalesce_params =
+			ETHTOOL_COALESCE_MAX_FRAMES, // ETHTOOL_COALESCE_USECS,
 #endif
-    .get_drvinfo = zxdh_en_get_drvinfo,
-    .get_link_ksettings = zxdh_en_get_link_ksettings,
-    .set_link_ksettings = zxdh_en_set_link_ksettings,
-    .get_regs_len = zxdh_en_get_regs_len,
-    .get_regs = zxdh_en_get_regs,
-    .get_wol = zxdh_en_get_wol,
-    .set_wol = zxdh_en_set_wol,
-    .get_msglevel = zxdh_en_get_msglevel,
-    .set_msglevel = zxdh_en_set_msglevel,
-    .nway_reset = zxdh_en_nway_reset,
-    .get_link = zxdh_en_get_link,
-    .get_eeprom_len = zxdh_en_get_eeprom_len,
-    .get_eeprom = zxdh_en_get_eeprom,
-    .set_eeprom = zxdh_en_set_eeprom,
-    .get_ringparam = zxdh_en_get_ringparam,
-    .set_ringparam = zxdh_en_set_ringparam,
-    .get_pauseparam = zxdh_en_get_pauseparam,
-    .set_pauseparam = zxdh_en_set_pauseparam,
-    .get_fecparam = zxdh_en_get_fecparam,
-    .set_fecparam = zxdh_en_set_fecparam,
-    .get_module_info   = zxdh_en_get_module_info,
-    .get_module_eeprom = zxdh_en_get_module_eeprom,
+	.get_drvinfo = zxdh_en_get_drvinfo,
+	.get_link_ksettings = zxdh_en_get_link_ksettings,
+	.set_link_ksettings = zxdh_en_set_link_ksettings,
+	.get_regs_len = zxdh_en_get_regs_len,
+	.get_regs = zxdh_en_get_regs,
+	.get_wol = zxdh_en_get_wol,
+	.set_wol = zxdh_en_set_wol,
+	.get_msglevel = zxdh_en_get_msglevel,
+	.set_msglevel = zxdh_en_set_msglevel,
+	.nway_reset = zxdh_en_nway_reset,
+	.get_link = zxdh_en_get_link,
+	.get_eeprom_len = zxdh_en_get_eeprom_len,
+	.get_eeprom = zxdh_en_get_eeprom,
+	.set_eeprom = zxdh_en_set_eeprom,
+	.get_ringparam = zxdh_en_get_ringparam,
+	.set_ringparam = zxdh_en_set_ringparam,
+	.get_pauseparam = zxdh_en_get_pauseparam,
+	.set_pauseparam = zxdh_en_set_pauseparam,
+	.get_fecparam = zxdh_en_get_fecparam,
+	.set_fecparam = zxdh_en_set_fecparam,
+	.get_module_info = zxdh_en_get_module_info,
+	.get_module_eeprom = zxdh_en_get_module_eeprom,
 #ifdef HAVE_ETHTOOL_GET_MODULE_EEPROM_BY_PAGE
-    .get_module_eeprom_by_page = zxdh_en_get_module_eeprom_by_page,
+	.get_module_eeprom_by_page = zxdh_en_get_module_eeprom_by_page,
 #endif
-    .self_test = zxdh_en_diag_test,
-    .get_strings = zxdh_en_get_strings,
-    .get_priv_flags = zxdh_en_get_priv_flags,
-    .set_priv_flags = zxdh_en_set_priv_flags,
+	.self_test = zxdh_en_diag_test,
+	.get_strings = zxdh_en_get_strings,
+	.get_priv_flags = zxdh_en_get_priv_flags,
+	.set_priv_flags = zxdh_en_set_priv_flags,
 #ifndef HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT
 #ifdef HAVE_ETHTOOL_SET_PHYS_ID
-    .set_phys_id = zxdh_en_set_phys_id,
+	.set_phys_id = zxdh_en_set_phys_id,
 #else
-    .phys_id = zxdh_en_phys_id,
+	.phys_id = zxdh_en_phys_id,
 #endif /* HAVE_ETHTOOL_SET_PHYS_ID */
 #endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */
 
 #ifdef HAVE_ETHTOOL_GET_SSET_COUNT
-    .get_sset_count = zxdh_en_get_sset_count,
+	.get_sset_count = zxdh_en_get_sset_count,
 #else
-    .get_stats_count = zxdh_en_get_stats_count,
-    .self_test_count = zxdh_en_diag_test_count,
+	.get_stats_count = zxdh_en_get_stats_count,
+	.self_test_count = zxdh_en_diag_test_count,
 #endif
-    .get_ethtool_stats = zxdh_en_get_ethtool_stats,
+	.get_ethtool_stats = zxdh_en_get_ethtool_stats,
 
 #ifdef HAVE_ETHTOOL_GET_PERM_ADDR
-    .get_perm_addr = ethtool_op_get_perm_addr,
+	.get_perm_addr = ethtool_op_get_perm_addr,
 #endif
-    .get_coalesce = zxdh_en_get_coalesce,
-    .set_coalesce = zxdh_en_set_coalesce,
+	.get_coalesce = zxdh_en_get_coalesce,
+	.set_coalesce = zxdh_en_set_coalesce,
 #ifndef HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT
 #ifdef HAVE_ETHTOOL_GET_TS_INFO
-    .get_ts_info = zxdh_en_get_ts_info,
+	.get_ts_info = zxdh_en_get_ts_info,
 #endif /* HAVE_ETHTOOL_GET_TS_INFO */
 #endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */
 #ifdef CONFIG_PM_RUNTIME
-    .begin = zxdh_en_ethtool_begin,
-    .complete = zxdh_en_ethtool_complete,
+	.begin = zxdh_en_ethtool_begin,
+	.complete = zxdh_en_ethtool_complete,
 #endif /* CONFIG_PM_RUNTIME */
 #ifndef HAVE_NDO_SET_FEATURES
-    .get_rx_csum = zxdh_en_get_rx_csum,
-    .set_rx_csum = zxdh_en_set_rx_csum,
-    .get_tx_csum = ethtool_op_get_tx_csum,
-    .set_tx_csum = zxdh_en_set_tx_csum,
-    .get_sg = ethtool_op_get_sg,
-    .set_sg = ethtool_op_set_sg,
+	.get_rx_csum = zxdh_en_get_rx_csum,
+	.set_rx_csum = zxdh_en_set_rx_csum,
+	.get_tx_csum = ethtool_op_get_tx_csum,
+	.set_tx_csum = zxdh_en_set_tx_csum,
+	.get_sg = ethtool_op_get_sg,
+	.set_sg = ethtool_op_set_sg,
 #ifdef NETIF_F_TSO
-    .get_tso = ethtool_op_get_tso,
-    .set_tso = zxdh_en_set_tso,
+	.get_tso = ethtool_op_get_tso,
+	.set_tso = zxdh_en_set_tso,
 #endif
 #ifdef ETHTOOL_GFLAGS
-    .get_flags = ethtool_op_get_flags,
-    .set_flags = zxdh_en_set_flags,
+	.get_flags = ethtool_op_get_flags,
+	.set_flags = zxdh_en_set_flags,
 #endif /* ETHTOOL_GFLAGS */
 #endif /* HAVE_NDO_SET_FEATURES */
 #ifdef ETHTOOL_GADV_COAL
-    .get_advcoal = zxdh_en_get_adv_coal,
-    .set_advcoal = zxdh_en_set_dmac_coal,
+	.get_advcoal = zxdh_en_get_adv_coal,
+	.set_advcoal = zxdh_en_set_dmac_coal,
 #endif /* ETHTOOL_GADV_COAL */
 #ifndef HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT
 #ifdef ETHTOOL_GEEE
-    .get_eee = zxdh_en_get_eee,
+	.get_eee = zxdh_en_get_eee,
 #endif
 #ifdef ETHTOOL_SEEE
-    .set_eee = zxdh_en_set_eee,
+	.set_eee = zxdh_en_set_eee,
 #endif
 #ifdef ETHTOOL_GRXFHINDIR
 #ifdef HAVE_ETHTOOL_GRXFHINDIR_SIZE
-    .get_rxfh_indir_size = zxdh_en_get_rxfh_indir_size,
-    .get_rxfh_key_size = zxdh_en_get_rxfh_key_size,
+	.get_rxfh_indir_size = zxdh_en_get_rxfh_indir_size,
+	.get_rxfh_key_size = zxdh_en_get_rxfh_key_size,
 #endif /* HAVE_ETHTOOL_GRSFHINDIR_SIZE */
 #if (defined(ETHTOOL_GRSSH) && !defined(HAVE_ETHTOOL_GSRSSH))
-    .get_rxfh = zxdh_en_get_rxfh,
+	.get_rxfh = zxdh_en_get_rxfh,
 #else
-    .get_rxfh_indir = zxdh_en_get_rxfh_indir,
+	.get_rxfh_indir = zxdh_en_get_rxfh_indir,
 #endif /* HAVE_ETHTOOL_GSRSSH */
 #endif /* ETHTOOL_GRXFHINDIR */
 #ifdef ETHTOOL_SRXFHINDIR
 #if (defined(ETHTOOL_GRSSH) && !defined(HAVE_ETHTOOL_GSRSSH))
-    .set_rxfh = zxdh_en_set_rxfh,
+	.set_rxfh = zxdh_en_set_rxfh,
 #else
-    .set_rxfh_indir = zxdh_en_set_rxfh_indir,
+	.set_rxfh_indir = zxdh_en_set_rxfh_indir,
 #endif /* HAVE_ETHTOOL_GSRSSH */
 #endif /* ETHTOOL_SRXFHINDIR */
 #ifdef ETHTOOL_GCHANNELS
-    .get_channels = zxdh_en_get_channels,
+	.get_channels = zxdh_en_get_channels,
 #endif /* ETHTOOL_GCHANNELS */
 #ifdef ETHTOOL_SCHANNELS
-    .set_channels = zxdh_en_set_channels,
+	.set_channels = zxdh_en_set_channels,
 #endif /* ETHTOOL_SCHANNELS */
 #endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */
 #ifdef ETHTOOL_GRXFH
-    .get_rxnfc = zxdh_en_get_rxnfc,
-    .set_rxnfc = zxdh_en_set_rxnfc,
+	.get_rxnfc = zxdh_en_get_rxnfc,
+	.set_rxnfc = zxdh_en_set_rxnfc,
 #endif
 };
 
 #ifdef HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT
-static const struct ethtool_ops_ext zxdh_en_ethtool_ops_ext =
-{
-    .size = sizeof(struct ethtool_ops_ext),
-    .get_ts_info = zxdh_en_get_ts_info,
-    .set_phys_id = zxdh_en_set_phys_id,
-    .get_eee = zxdh_en_get_eee,
-    .set_eee = zxdh_en_set_eee,
+static const struct ethtool_ops_ext zxdh_en_ethtool_ops_ext = {
+	.size = sizeof(struct ethtool_ops_ext),
+	.get_ts_info = zxdh_en_get_ts_info,
+	.set_phys_id = zxdh_en_set_phys_id,
+	.get_eee = zxdh_en_get_eee,
+	.set_eee = zxdh_en_set_eee,
 #ifdef HAVE_ETHTOOL_GRXFHINDIR_SIZE
-    .get_rxfh_indir_size = zxdh_en_get_rxfh_indir_size,
+	.get_rxfh_indir_size = zxdh_en_get_rxfh_indir_size,
 #endif /* HAVE_ETHTOOL_GRSFHINDIR_SIZE */
-    .get_rxfh_indir = zxdh_en_get_rxfh_indir,
-    .set_rxfh_indir = zxdh_en_set_rxfh_indir,
-    .get_channels = zxdh_en_get_channels,
-    .set_channels = zxdh_en_set_channels,
+	.get_rxfh_indir = zxdh_en_get_rxfh_indir,
+	.set_rxfh_indir = zxdh_en_set_rxfh_indir,
+	.get_channels = zxdh_en_get_channels,
+	.set_channels = zxdh_en_set_channels,
 };
 
 void zxdh_en_set_ethtool_ops_ext(struct net_device *netdev)
 {
-    netdev->ethtool_ops = &zxdh_en_ethtool_ops;
-    set_ethtool_ops_ext(netdev, &zxdh_en_ethtool_ops_ext);
+	netdev->ethtool_ops = &zxdh_en_ethtool_ops;
+	set_ethtool_ops_ext(netdev, &zxdh_en_ethtool_ops_ext);
 }
 #else
 void zxdh_en_set_ethtool_ops(struct net_device *netdev)
 {
-    netdev->ethtool_ops = &zxdh_en_ethtool_ops;
+	netdev->ethtool_ops = &zxdh_en_ethtool_ops;
 }
 #endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_ethtool/ethtool.h b/src/net/drivers/net/ethernet/dinghai/en_ethtool/ethtool.h
index fb8fb3de7f2b804d33321814b0f089673ce24697..55964963b3b3e74eb4ba4208f0a24faffaa257c0 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_ethtool/ethtool.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_ethtool/ethtool.h
@@ -8,49 +8,45 @@ extern "C" {
 #include <linux/dinghai/kcompat.h>
 #include <linux/netdevice.h>
 
-enum zxdh_priv_flag
-{
-    ZXDH_PFLAG_ENABLE_LLDP,
-    ZXDH_PFLAG_ENABLE_SSHD,
-    ZXDH_PFLAG_IP=2,
-    ZXDH_NUM_PFLAGS, /* Keep last */
+enum zxdh_priv_flag {
+	ZXDH_PFLAG_ENABLE_LLDP,
+	ZXDH_PFLAG_ENABLE_SSHD,
+	ZXDH_PFLAG_IP = 2,
+	ZXDH_NUM_PFLAGS, /* Keep last */
 };
 
-#define ZXDH_SET_PFLAG(pflags, flag, enable)    \
-    do                                          \
-    {                                           \
-        if (enable)                             \
-        {                                       \
-            pflags |= BIT(flag);                \
-        }                                       \
-        else                                    \
-        {                                       \
-            pflags &= ~(BIT(flag));             \
-        }                                       \
-    } while (0)
-
-#define ZXDH_ADD_STRING(data, str)                              \
-do                                                              \
-{                                                               \
-    data += ETH_GSTRING_LEN;                                    \
-    snprintf(data, ETH_GSTRING_LEN, str);                       \
-} while (0)
-
-#define ZXDH_ADD_QUEUE_STRING(data, str, i)                     \
-do                                                              \
-{                                                               \
-    data += ETH_GSTRING_LEN;                                    \
-    snprintf(data, ETH_GSTRING_LEN, "queue[%u]_%s", i, str);    \
-} while (0)
-
-#define ZXDH_NETDEV_STATS_NUM           (sizeof(struct zxdh_en_netdev_stats) / sizeof(uint64_t))
-#define ZXDH_VPORT_STATS_NUM            (sizeof(struct zxdh_en_vport_stats) / sizeof(uint64_t))
-#define ZXDH_MAC_STATS_NUM              (sizeof(struct zxdh_en_phy_stats) / sizeof(uint64_t))
-#define ZXDH_QUEUE_STATS_NUM            (sizeof(struct zxdh_en_queue_stats) / sizeof(uint64_t))
-
-#define ZXDH_NET_PF_STATS_NUM(en_dev)                                              \
-            (ZXDH_NETDEV_STATS_NUM + ZXDH_MAC_STATS_NUM + ZXDH_VPORT_STATS_NUM +   \
-            en_dev->curr_queue_pairs * ZXDH_QUEUE_STATS_NUM)
+#define ZXDH_SET_PFLAG(pflags, flag, enable) \
+	do {                                     \
+		if (enable) {                        \
+			pflags |= BIT(flag);             \
+		} else {                             \
+			pflags &= ~(BIT(flag));          \
+		}                                    \
+	} while (0)
+
+#define ZXDH_ADD_STRING(data, str)            \
+	do {                                      \
+		data += ETH_GSTRING_LEN;              \
+		snprintf(data, ETH_GSTRING_LEN, str); \
+	} while (0)
+
+#define ZXDH_ADD_QUEUE_STRING(data, str, i)                      \
+	do {                                                         \
+		data += ETH_GSTRING_LEN;                                 \
+		snprintf(data, ETH_GSTRING_LEN, "queue[%u]_%s", i, str); \
+	} while (0)
+
+#define ZXDH_NETDEV_STATS_NUM \
+	(sizeof(struct zxdh_en_netdev_stats) / sizeof(uint64_t))
+#define ZXDH_VPORT_STATS_NUM \
+	(sizeof(struct zxdh_en_vport_stats) / sizeof(uint64_t))
+#define ZXDH_MAC_STATS_NUM (sizeof(struct zxdh_en_phy_stats) / sizeof(uint64_t))
+#define ZXDH_QUEUE_STATS_NUM \
+	(sizeof(struct zxdh_en_queue_stats) / sizeof(uint64_t))
+
+#define ZXDH_NET_PF_STATS_NUM(en_dev)                                    \
+	(ZXDH_NETDEV_STATS_NUM + ZXDH_MAC_STATS_NUM + ZXDH_VPORT_STATS_NUM + \
+	 en_dev->curr_queue_pairs * ZXDH_QUEUE_STATS_NUM)
 
 #define ZXDH_GET_PFLAG(pflags, flag) (!!(pflags & (BIT(flag))))
 
@@ -60,7 +56,6 @@ void zxdh_en_set_ethtool_ops_ext(struct net_device *netdev);
 void zxdh_en_set_ethtool_ops(struct net_device *netdev);
 #endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */
 
-#define ZIOS_TYPE 0XAA
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf.c b/src/net/drivers/net/ethernet/dinghai/en_mpf.c
old mode 100755
new mode 100644
index 1b65f40c549a9b4370c0de95a698cc3f44924369..1ca4722119e72131795e34b6da1aabb41f966b7d
--- a/src/net/drivers/net/ethernet/dinghai/en_mpf.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_mpf.c
@@ -1,301 +1,296 @@
-#include <linux/module.h>
-#include <linux/kmod.h>
-#include <linux/pci.h>
-#include <linux/dinghai/helper.h>
-#include <linux/dinghai/devlink.h>
-#include <linux/dinghai/dinghai_irq.h>
-#include <linux/dinghai/eq.h>
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/kcompat.h>
-#include "./en_mpf/events.h"
-#include "./en_mpf/eq.h"
-#include "./en_mpf/irq.h"
-#include "en_mpf.h"
-#include "en_mpf/cfg_sf.h"
-
-MODULE_LICENSE("Dual BSD/GPL");
-
-uint32_t dh_debug_mask;
-module_param_named(debug_mask, dh_debug_mask, uint, 0644);
-MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
-
-extern struct devlink_ops dh_mpf_devlink_ops;
-extern struct dh_core_devlink_ops dh_mpf_core_devlink_ops;
-
-int32_t dh_mpf_pci_init(struct dh_core_dev *dev)
-{
-    int32_t ret = 0;
-    struct dh_en_mpf_dev *mpf_dev = NULL;
-
-    pci_set_drvdata(dev->pdev, dev);
-
-    ret = pci_enable_device(dev->pdev);
-    if (ret != 0)
-    {
-        dev_err(dev->device, "pci_enable_device failed: %d\n", ret);
-        return -ENOMEM;
-    }
-
-    ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(64));
-    if (ret != 0)
-    {
-        ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(32));
-        if (ret != 0)
-        {
-            dev_err(dev->device, "dma_set_mask_and_coherent failed: %d\n", ret);
-            goto err_pci;
-        }
-    }
-
-    ret = pci_request_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM), "dh-mpf");
-    if (ret != 0)
-    {
-        dev_err(dev->device, "pci_request_selected_regions failed: %d\n", ret);
-        goto err_pci;
-    }
-
-    pci_enable_pcie_error_reporting(dev->pdev);
-    pci_set_master(dev->pdev);
-    ret = pci_save_state(dev->pdev);
-    if (ret != 0)
-    {
-        dev_err(dev->device, "pci_save_state failed: %d\n", ret);
-        goto err_pci_save_state;
-    }
-
-    mpf_dev = dh_core_priv(dev);
-    mpf_dev->pci_ioremap_addr = (uint64_t)ioremap(pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0));
-    LOG_INFO("pci_ioremap_addr=0x%llx, ioremap(0x%llx, 0x%llx)\n", mpf_dev->pci_ioremap_addr, pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0));
-    if (mpf_dev->pci_ioremap_addr == 0)
-    {
-        ret = -1;
-        LOG_ERR("ioremap(0x%llx, 0x%llx) failed\n", pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0));
-        goto err_pci_save_state;
-    }
-
-    return 0;
-
-err_pci_save_state:
-    pci_disable_pcie_error_reporting(dev->pdev);
-    pci_release_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM));
-err_pci:
-    pci_disable_device(dev->pdev);
-    return ret;
-}
-
-static const struct pci_device_id dh_mpf_pci_table[] = {
-   { PCI_DEVICE(ZXDH_MPF_VENDOR_ID, ZXDH_MPF_DEVICE_ID), 0 },
-   { 0, }
-};
-
-MODULE_DEVICE_TABLE(pci, dh_mpf_pci_table);
-
-void dh_mpf_pci_close(struct dh_core_dev *dev)
-{
-    struct dh_en_mpf_dev *mpf_dev = NULL;
-
-    mpf_dev = dh_core_priv(dev);
-    iounmap((void *)mpf_dev->pci_ioremap_addr);
-    pci_disable_pcie_error_reporting(dev->pdev);
-    pci_release_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM));
-    pci_disable_device(dev->pdev);
-
-    return;
-}
-
-static int32_t dh_mpf_probe(struct pci_dev *pdev, const struct pci_device_id *id)
-{
-    struct dh_core_dev *dh_dev = NULL;
-    struct devlink *devlink    = NULL;
-    int32_t err                = 0;
-
-    LOG_INFO("mpf driver start to probe\n");
-
-    devlink = zxdh_devlink_alloc(&pdev->dev, &dh_mpf_devlink_ops, sizeof(struct dh_en_mpf_dev));
-    if (devlink == NULL)
-    {
-        dev_err(&pdev->dev, "devlink alloc failed\n");
-        return -ENOMEM;
-    }
-
-    dh_dev = devlink_priv(devlink);
-    dh_dev->device = &pdev->dev;
-    dh_dev->pdev = pdev;
-    dh_dev->devlink_ops = &dh_mpf_core_devlink_ops;
-
-    err = dh_mpf_pci_init(dh_dev);
-    if (err != 0)
-    {
-        dev_err(&pdev->dev, "dh_mpf_pci_init failed: %d\n", err);
-        goto err_devlink_cleanup;
-    }
-
-    err = dh_mpf_irq_table_init(dh_dev);
-    if (err != 0)
-    {
-        dh_err(dh_dev, "Failed to alloc IRQs\n");
-        goto err_pci;
-    }
-
-    err = dh_mpf_eq_table_init(dh_dev);
-    if (err != 0)
-    {
-        dh_err(dh_dev, "Failed to alloc IRQs\n");
-        goto err_eq_table_init;
-    }
-
-    err = dh_mpf_irq_table_create(dh_dev);
-    if (err != 0)
-    {
-        dh_err(dh_dev, "Failed to alloc IRQs\n");
-        goto err_irq_table_create;
-    }
-
-    err = dh_mpf_eq_table_create(dh_dev);
-    if (err != 0)
-    {
-        dh_err(dh_dev, "Failed to alloc EQs\n");
-        goto err_eq_table_create;
-    }
-
-    err = dh_mpf_events_init(dh_dev);
-    if (err != 0)
-    {
-        dh_err(dh_dev, "failed to initialize events\n");
-        goto err_events_init_cleanup;
-    }
-
-#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
-    zxdh_devlink_register(devlink);
-#else
-    zxdh_devlink_register(devlink, &pdev->dev);
-#endif
-
-    LOG_INFO("mpf driver probe completed\n");
-    return 0;
-
-err_events_init_cleanup:
-    dh_mpf_eq_table_destroy(dh_dev);
-err_eq_table_create:
-    dh_mpf_irq_table_destroy(dh_dev);
-err_irq_table_create:
-    dh_eq_table_cleanup(dh_dev);
-err_eq_table_init:
-    dh_irq_table_cleanup(dh_dev);
-err_pci:
-    dh_mpf_pci_close(dh_dev);
-err_devlink_cleanup:
-    zxdh_devlink_free(devlink);
-    return err;
-}
-
-static void dh_mpf_remove(struct pci_dev *pdev)
-{
-    struct dh_core_dev *dh_dev = pci_get_drvdata(pdev);
-    struct devlink *devlink = priv_to_devlink(dh_dev);
-    LOG_INFO("mpf driver start to remove");
-
-    zxdh_devlink_unregister(devlink);
-    dh_mpf_events_uninit(dh_dev);
-    dh_mpf_eq_table_destroy(dh_dev);
-    dh_mpf_irq_table_destroy(dh_dev);
-    dh_eq_table_cleanup(dh_dev);
-    dh_irq_table_cleanup(dh_dev);
-    dh_mpf_pci_close(dh_dev);
-    zxdh_devlink_free(devlink);
-
-    pci_set_drvdata(pdev, NULL);
-    LOG_INFO("mpf driver remove completed\n");
-}
-
-static int32_t dh_mpf_suspend(struct pci_dev *pdev, pm_message_t state)
-{
-
-    return 0;
-}
-
-static int32_t dh_mpf_resume(struct pci_dev *pdev)
-{
-
-    return 0;
-}
-
-static void dh_mpf_shutdown(struct pci_dev *pdev)
-{
-    dh_mpf_remove(pdev);
-}
-
-static pci_ers_result_t dh_pci_err_detected(struct pci_dev *pdev,
-                                            pci_channel_state_t state)
-{
-    return PCI_ERS_RESULT_NONE;
-}
-
-static pci_ers_result_t dh_mpf_pci_slot_reset(struct pci_dev *pdev)
-{
-    return PCI_ERS_RESULT_NONE;
-}
-
-static void dh_mpf_pci_resume(struct pci_dev *pdev)
-{
-
-}
-
-static const struct pci_error_handlers dh_mpf_err_handler = {
-    .error_detected = dh_pci_err_detected,
-    .slot_reset     = dh_mpf_pci_slot_reset,
-    .resume         = dh_mpf_pci_resume
-};
-
-static struct pci_driver dh_mpf_driver = {
-    .name           = KBUILD_MODNAME,
-    .id_table       = dh_mpf_pci_table,
-    .probe          = dh_mpf_probe,
-    .remove         = dh_mpf_remove,
-    .suspend        = dh_mpf_suspend,
-    .resume         = dh_mpf_resume,
-    .shutdown       = dh_mpf_shutdown,
-    .err_handler    = &dh_mpf_err_handler,
-};
-
-static int32_t __init init(void)
-{
-    int32_t err = 0;
-
-    err = pci_register_driver(&dh_mpf_driver);
-    if (err != 0)
-    {
-        LOG_ERR("pci_register_driver failed: %d\n", err);
-        return err;
-    }
-
-#ifdef CONFIG_ZXDH_SF
-    err = zxdh_mpf_sf_driver_register();
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_en_sf_driver_register failed: %d\n", err);
-        goto err_sf;
-    }
-#endif
-
-    LOG_INFO("zxdh_mpf driver init success\n");
-
-    return 0;
-
-err_sf:
-    pci_unregister_driver(&dh_mpf_driver);
-    return err;
-}
-
-static void __exit cleanup(void)
-{
-#ifdef CONFIG_ZXDH_SF
-    zxdh_mpf_sf_driver_uregister();
-#endif
-    pci_unregister_driver(&dh_mpf_driver);
-
-    LOG_INFO("zxdh_mpf driver remove success\n");
-}
-
-module_init(init);
-module_exit(cleanup);
+#include <linux/module.h>
+#include <linux/kmod.h>
+#include <linux/pci.h>
+#include <linux/dinghai/helper.h>
+#include <linux/dinghai/devlink.h>
+#include <linux/dinghai/dinghai_irq.h>
+#include <linux/dinghai/eq.h>
+#include <linux/dinghai/driver.h>
+#include <linux/dinghai/kcompat.h>
+#include "./en_mpf/events.h"
+#include "./en_mpf/eq.h"
+#include "./en_mpf/irq.h"
+#include "en_mpf.h"
+#include "en_mpf/cfg_sf.h"
+
+MODULE_LICENSE("Dual BSD/GPL");
+
+uint32_t dh_debug_mask;
+module_param_named(debug_mask, dh_debug_mask, uint, 0644);
+MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec "
+							 "time, 3 = both. Default=0");
+
+extern struct devlink_ops dh_mpf_devlink_ops;
+extern struct dh_core_devlink_ops dh_mpf_core_devlink_ops;
+
+int32_t dh_mpf_pci_init(struct dh_core_dev *dev)
+{
+	int32_t ret = 0;
+	struct dh_en_mpf_dev *mpf_dev = NULL;
+
+	pci_set_drvdata(dev->pdev, dev);
+
+	ret = pci_enable_device(dev->pdev);
+	if (ret != 0) {
+		dev_err(dev->device, "pci_enable_device failed: %d\n", ret);
+		return -ENOMEM;
+	}
+
+	ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(64));
+	if (ret != 0) {
+		ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(32));
+		if (ret != 0) {
+			dev_err(dev->device, "dma_set_mask_and_coherent failed: %d\n", ret);
+			goto err_pci;
+		}
+	}
+
+	ret = pci_request_selected_regions(
+			dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM), "dh-mpf");
+	if (ret != 0) {
+		dev_err(dev->device, "pci_request_selected_regions failed: %d\n", ret);
+		goto err_pci;
+	}
+
+	pci_enable_pcie_error_reporting(dev->pdev);
+	pci_set_master(dev->pdev);
+	ret = pci_save_state(dev->pdev);
+	if (ret != 0) {
+		dev_err(dev->device, "pci_save_state failed: %d\n", ret);
+		goto err_pci_save_state;
+	}
+
+	mpf_dev = dh_core_priv(dev);
+	mpf_dev->pci_ioremap_addr = (uint64_t)ioremap(
+			pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0));
+	LOG_INFO("pci_ioremap_addr=0x%llx, ioremap(0x%llx, 0x%llx)\n",
+			 mpf_dev->pci_ioremap_addr, pci_resource_start(dev->pdev, 0),
+			 pci_resource_len(dev->pdev, 0));
+	if (mpf_dev->pci_ioremap_addr == 0) {
+		ret = -1;
+		LOG_ERR("ioremap(0x%llx, 0x%llx) failed\n",
+				pci_resource_start(dev->pdev, 0),
+				pci_resource_len(dev->pdev, 0));
+		goto err_pci_save_state;
+	}
+
+	return 0;
+
+err_pci_save_state:
+	pci_disable_pcie_error_reporting(dev->pdev);
+	pci_release_selected_regions(dev->pdev,
+								 pci_select_bars(dev->pdev, IORESOURCE_MEM));
+err_pci:
+	pci_disable_device(dev->pdev);
+	return ret;
+}
+
+static const struct pci_device_id dh_mpf_pci_table[] = {
+	{ PCI_DEVICE(ZXDH_MPF_VENDOR_ID, ZXDH_MPF_DEVICE_ID), 0 },
+	{
+			0,
+	}
+};
+
+MODULE_DEVICE_TABLE(pci, dh_mpf_pci_table);
+
+void dh_mpf_pci_close(struct dh_core_dev *dev)
+{
+	struct dh_en_mpf_dev *mpf_dev = NULL;
+
+	mpf_dev = dh_core_priv(dev);
+	iounmap((void *)mpf_dev->pci_ioremap_addr);
+	pci_disable_pcie_error_reporting(dev->pdev);
+	pci_release_selected_regions(dev->pdev,
+								 pci_select_bars(dev->pdev, IORESOURCE_MEM));
+	pci_disable_device(dev->pdev);
+
+	return;
+}
+
+static int32_t dh_mpf_probe(struct pci_dev *pdev,
+							const struct pci_device_id *id)
+{
+	struct dh_core_dev *dh_dev = NULL;
+	struct devlink *devlink = NULL;
+	int32_t err = 0;
+
+	LOG_INFO("mpf driver start to probe\n");
+
+	devlink = zxdh_devlink_alloc(&pdev->dev, &dh_mpf_devlink_ops,
+								 sizeof(struct dh_en_mpf_dev));
+	if (devlink == NULL) {
+		dev_err(&pdev->dev, "devlink alloc failed\n");
+		return -ENOMEM;
+	}
+
+	dh_dev = devlink_priv(devlink);
+	dh_dev->device = &pdev->dev;
+	dh_dev->pdev = pdev;
+	dh_dev->devlink_ops = &dh_mpf_core_devlink_ops;
+
+	err = dh_mpf_pci_init(dh_dev);
+	if (err != 0) {
+		dev_err(&pdev->dev, "dh_mpf_pci_init failed: %d\n", err);
+		goto err_devlink_cleanup;
+	}
+
+	err = dh_mpf_irq_table_init(dh_dev);
+	if (err != 0) {
+		dh_err(dh_dev, "Failed to alloc IRQs\n");
+		goto err_pci;
+	}
+
+	err = dh_mpf_eq_table_init(dh_dev);
+	if (err != 0) {
+		dh_err(dh_dev, "Failed to alloc IRQs\n");
+		goto err_eq_table_init;
+	}
+
+	err = dh_mpf_irq_table_create(dh_dev);
+	if (err != 0) {
+		dh_err(dh_dev, "Failed to alloc IRQs\n");
+		goto err_irq_table_create;
+	}
+
+	err = dh_mpf_eq_table_create(dh_dev);
+	if (err != 0) {
+		dh_err(dh_dev, "Failed to alloc EQs\n");
+		goto err_eq_table_create;
+	}
+
+	err = dh_mpf_events_init(dh_dev);
+	if (err != 0) {
+		dh_err(dh_dev, "failed to initialize events\n");
+		goto err_events_init_cleanup;
+	}
+
+#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
+	zxdh_devlink_register(devlink);
+#else
+	zxdh_devlink_register(devlink, &pdev->dev);
+#endif
+
+	LOG_INFO("mpf driver probe completed\n");
+	return 0;
+
+err_events_init_cleanup:
+	dh_mpf_eq_table_destroy(dh_dev);
+err_eq_table_create:
+	dh_mpf_irq_table_destroy(dh_dev);
+err_irq_table_create:
+	dh_eq_table_cleanup(dh_dev);
+err_eq_table_init:
+	dh_irq_table_cleanup(dh_dev);
+err_pci:
+	dh_mpf_pci_close(dh_dev);
+err_devlink_cleanup:
+	zxdh_devlink_free(devlink);
+	return err;
+}
+
+static void dh_mpf_remove(struct pci_dev *pdev)
+{
+	struct dh_core_dev *dh_dev = pci_get_drvdata(pdev);
+	struct devlink *devlink = priv_to_devlink(dh_dev);
+	LOG_INFO("mpf driver start to remove");
+
+	zxdh_devlink_unregister(devlink);
+	dh_mpf_events_uninit(dh_dev);
+	dh_mpf_eq_table_destroy(dh_dev);
+	dh_mpf_irq_table_destroy(dh_dev);
+	dh_eq_table_cleanup(dh_dev);
+	dh_irq_table_cleanup(dh_dev);
+	dh_mpf_pci_close(dh_dev);
+	zxdh_devlink_free(devlink);
+
+	pci_set_drvdata(pdev, NULL);
+	LOG_INFO("mpf driver remove completed\n");
+}
+
+static int32_t dh_mpf_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+	return 0;
+}
+
+static int32_t dh_mpf_resume(struct pci_dev *pdev)
+{
+	return 0;
+}
+
+static void dh_mpf_shutdown(struct pci_dev *pdev)
+{
+	dh_mpf_remove(pdev);
+}
+
+static pci_ers_result_t dh_pci_err_detected(struct pci_dev *pdev,
+											pci_channel_state_t state)
+{
+	return PCI_ERS_RESULT_NONE;
+}
+
+static pci_ers_result_t dh_mpf_pci_slot_reset(struct pci_dev *pdev)
+{
+	return PCI_ERS_RESULT_NONE;
+}
+
+static void dh_mpf_pci_resume(struct pci_dev *pdev)
+{
+}
+
+static const struct pci_error_handlers dh_mpf_err_handler = {
+	.error_detected = dh_pci_err_detected,
+	.slot_reset = dh_mpf_pci_slot_reset,
+	.resume = dh_mpf_pci_resume
+};
+
+static struct pci_driver dh_mpf_driver = {
+	.name = KBUILD_MODNAME,
+	.id_table = dh_mpf_pci_table,
+	.probe = dh_mpf_probe,
+	.remove = dh_mpf_remove,
+	.suspend = dh_mpf_suspend,
+	.resume = dh_mpf_resume,
+	.shutdown = dh_mpf_shutdown,
+	.err_handler = &dh_mpf_err_handler,
+};
+
+static int32_t __init init(void)
+{
+	int32_t err = 0;
+
+	err = pci_register_driver(&dh_mpf_driver);
+	if (err != 0) {
+		LOG_ERR("pci_register_driver failed: %d\n", err);
+		return err;
+	}
+
+#ifdef CONFIG_ZXDH_SF
+	err = zxdh_mpf_sf_driver_register();
+	if (err != 0) {
+		LOG_ERR("zxdh_en_sf_driver_register failed: %d\n", err);
+		goto err_sf;
+	}
+#endif
+
+	LOG_INFO("zxdh_mpf driver init success\n");
+
+	return 0;
+
+err_sf:
+	pci_unregister_driver(&dh_mpf_driver);
+	return err;
+}
+
+static void __exit cleanup(void)
+{
+#ifdef CONFIG_ZXDH_SF
+	zxdh_mpf_sf_driver_uregister();
+#endif
+	pci_unregister_driver(&dh_mpf_driver);
+
+	LOG_INFO("zxdh_mpf driver remove success\n");
+}
+
+module_init(init);
+module_exit(cleanup);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf.h b/src/net/drivers/net/ethernet/dinghai/en_mpf.h
old mode 100755
new mode 100644
index cd1ee3c5d84d46908b795da7d1af8935094909eb..54e571128271d171df8be4deedad37f2be02b350
--- a/src/net/drivers/net/ethernet/dinghai/en_mpf.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_mpf.h
@@ -1,32 +1,32 @@
-#ifndef __ZXDH_EN_MPF_H__
-#define __ZXDH_EN_MPF_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/workqueue.h>
-#include <linux/dinghai/driver.h>
-
-#define ZXDH_MPF_VENDOR_ID 0x1111
-#define ZXDH_MPF_DEVICE_ID 0x1041
-
-#define ZXDH_BAR1_CHAN_OFFSET               0x2000//0x7801000
-#define ZXDH_BAR2_CHAN_OFFSET               0x3000//0x7802000
-
-struct dh_en_mpf_dev {
-    uint16_t ep_bdf;
-    uint16_t pcie_id;
-    uint16_t vport;
-
-    uint64_t pci_ioremap_addr;
-
-    struct work_struct dh_np_sdk_from_risc;
-    struct work_struct dh_np_sdk_from_pf;
-};
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef __ZXDH_EN_MPF_H__
+#define __ZXDH_EN_MPF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/workqueue.h>
+#include <linux/dinghai/driver.h>
+
+#define ZXDH_MPF_VENDOR_ID 0x1111
+#define ZXDH_MPF_DEVICE_ID 0x1041
+
+#define ZXDH_BAR1_CHAN_OFFSET 0x2000 // 0x7801000
+#define ZXDH_BAR2_CHAN_OFFSET 0x3000 // 0x7802000
+
+struct dh_en_mpf_dev {
+	uint16_t ep_bdf;
+	uint16_t pcie_id;
+	uint16_t vport;
+
+	uint64_t pci_ioremap_addr;
+
+	struct work_struct dh_np_sdk_from_risc;
+	struct work_struct dh_np_sdk_from_pf;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* __ZXDH_EN_MPF_H__ */
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/cfg_sf.c b/src/net/drivers/net/ethernet/dinghai/en_mpf/cfg_sf.c
old mode 100755
new mode 100644
index 1ddde92cff9a89f235e46bb414d04130f98168e3..14901598da1d76235c01c8786fdea49cb1000502
--- a/src/net/drivers/net/ethernet/dinghai/en_mpf/cfg_sf.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/cfg_sf.c
@@ -1,54 +1,64 @@
-#include <linux/kernel.h>
-#include <linux/dinghai/auxiliary_bus.h>
-#include <linux/dinghai/driver.h>
-
-#include "cfg_sf.h"
-
-static int32_t zxdh_cfg_resume(struct zxdh_auxiliary_device *adev)
-{
-    return 0;
-}
-
-static int32_t zxdh_cfg_suspend(struct zxdh_auxiliary_device *adev, pm_message_t state)
-{
-    return 0;
-}
-
-static int32_t zxdh_cfg_probe(struct zxdh_auxiliary_device *adev,
-                              const struct zxdh_auxiliary_device_id *id)
-{
-    struct cfg_sf_dev * __attribute__((unused)) cfg_sf_dev = container_of(adev, struct cfg_sf_dev, adev);
-
-    return 0;
-}
-
-static int32_t zxdh_cfg_remove(struct zxdh_auxiliary_device *adev)
-{
-    return 0;
-}
-
-static const struct zxdh_auxiliary_device_id zxdh_cfg_id_table[] = {
-    { .name = ZXDH_EN_SF_NAME ".mpf_cfg", },
-    {},
-};
-
-//MODULE_DEVICE_TABLE(auxiliary_zxdh_id_table, zxdh_cfg_id_table);
-
-static struct zxdh_auxiliary_driver zxdh_cfg_driver = {
-    .name     = "mpf_cfg",
-    .probe    = zxdh_cfg_probe,
-    .remove   = zxdh_cfg_remove,
-    .suspend  = zxdh_cfg_suspend,
-    .resume   = zxdh_cfg_resume,
-    .id_table = zxdh_cfg_id_table,
-};
-
-int32_t zxdh_mpf_sf_driver_register(void)
-{
-    return zxdh_auxiliary_driver_register(&zxdh_cfg_driver);;
-}
-
-void zxdh_mpf_sf_driver_uregister(void)
-{
-    zxdh_auxiliary_driver_unregister(&zxdh_cfg_driver);;
-}
+#include <linux/kernel.h>
+#ifdef AUX_BUS_NO_SUPPORT
+#include <linux/dinghai/auxiliary_bus.h>
+#else
+#include <linux/auxiliary_bus.h>
+#endif
+#include <linux/dinghai/driver.h>
+
+#include "cfg_sf.h"
+
+static int32_t zxdh_cfg_resume(struct auxiliary_device *adev)
+{
+	return 0;
+}
+
+static int32_t zxdh_cfg_suspend(struct auxiliary_device *adev,
+								pm_message_t state)
+{
+	return 0;
+}
+
+static int32_t zxdh_cfg_probe(struct auxiliary_device *adev,
+							  const struct auxiliary_device_id *id)
+{
+	struct cfg_sf_dev *__attribute__((unused))
+	cfg_sf_dev = container_of(adev, struct cfg_sf_dev, adev);
+
+	return 0;
+}
+
+static int32_t zxdh_cfg_remove(struct auxiliary_device *adev)
+{
+	return 0;
+}
+
+static const struct auxiliary_device_id zxdh_cfg_id_table[] = {
+	{
+			.name = ZXDH_EN_SF_NAME ".mpf_cfg",
+	},
+	{},
+};
+
+// MODULE_DEVICE_TABLE(auxiliary_zxdh_id_table, zxdh_cfg_id_table);
+
+static struct auxiliary_driver zxdh_cfg_driver = {
+	.name = "mpf_cfg",
+	.probe = zxdh_cfg_probe,
+	.remove = zxdh_cfg_remove,
+	.suspend = zxdh_cfg_suspend,
+	.resume = zxdh_cfg_resume,
+	.id_table = zxdh_cfg_id_table,
+};
+
+int32_t zxdh_mpf_sf_driver_register(void)
+{
+	return auxiliary_driver_register(&zxdh_cfg_driver);
+	;
+}
+
+void zxdh_mpf_sf_driver_uregister(void)
+{
+	auxiliary_driver_unregister(&zxdh_cfg_driver);
+	;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/cfg_sf.h b/src/net/drivers/net/ethernet/dinghai/en_mpf/cfg_sf.h
old mode 100755
new mode 100644
index ec0fdd081cedd95474b33d6fe96020044977270a..2d25fe42e856669e62f2e1a0ed5f0aad6618834b
--- a/src/net/drivers/net/ethernet/dinghai/en_mpf/cfg_sf.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/cfg_sf.h
@@ -1,30 +1,31 @@
-#ifndef __ZXDH_MPF_CFG_SF_H__
-#define __ZXDH_MPF_CFG_SF_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/auxiliary_bus.h>
-#include <linux/dinghai/driver.h>
-
-struct cfg_sf_ops {
-
-};
-
-struct cfg_sf_dev {
-    struct zxdh_auxiliary_device adev;
-    struct dh_core_dev *dh_dev;
-    struct cfg_sf_ops *ops;
-};
-
-int32_t zxdh_mpf_sf_driver_register(void);
-void zxdh_mpf_sf_driver_uregister(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
+#ifndef __ZXDH_MPF_CFG_SF_H__
+#define __ZXDH_MPF_CFG_SF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef AUX_BUS_NO_SUPPORT
+#include <linux/dinghai/auxiliary_bus.h>
+#else
+#include <linux/auxiliary_bus.h>
+#endif
+#include <linux/dinghai/driver.h>
+
+struct cfg_sf_ops {
+};
+
+struct cfg_sf_dev {
+	struct auxiliary_device adev;
+	struct dh_core_dev *dh_dev;
+	struct cfg_sf_ops *ops;
+};
+
+int32_t zxdh_mpf_sf_driver_register(void);
+void zxdh_mpf_sf_driver_uregister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/devlink.c b/src/net/drivers/net/ethernet/dinghai/en_mpf/devlink.c
old mode 100755
new mode 100644
index e89a752f121155b5a7f48b8bb2474eb209a61bca..9fdaebdbd4d2c0b11d8eb4f46f1bcb9deb5f81aa
--- a/src/net/drivers/net/ethernet/dinghai/en_mpf/devlink.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/devlink.c
@@ -1,130 +1,124 @@
-#include <linux/dinghai/driver.h>
-#include <net/devlink.h>
-#include "devlink.h"
-
-struct devlink_ops dh_mpf_devlink_ops = {
-
-};
-
-enum {
-    DH_MPF_PARAMS_MAX,
-};
-
-static int32_t __attribute__((unused)) sample_check(struct dh_core_dev *dev)
-{
-    return 1;
-}
-
-enum dh_mpf_devlink_param_id {
-    DH_MPF_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
-    DH_MPF_DEVLINK_PARAM_ID_SAMPLE,
-};
-
-
-static int32_t dh_devlink_sample_set(struct devlink *devlink, uint32_t id,
-                              struct devlink_param_gset_ctx *ctx)
-{
-    struct dh_core_dev * __attribute__((unused)) dev = devlink_priv(devlink);
-
-    return 0;
-}
-
-static int32_t dh_devlink_sample_get(struct devlink *devlink, uint32_t id,
-                              struct devlink_param_gset_ctx *ctx)
-{
-    struct dh_core_dev * __attribute__((unused)) dev = devlink_priv(devlink);
-
-    return 0;
-}
-
-#ifdef HAVE_DEVLINK_PARAM_REGISTER
-static const struct devlink_params {
-    const char *name;
-    int32_t (*check)(struct dh_core_dev *dev);
-    struct devlink_param param;
-} devlink_params[] = {
-    [DH_MPF_PARAMS_MAX] = { .name = "sample",
-                            .check = &sample_check,
-                            .param = DEVLINK_PARAM_DRIVER(DH_MPF_DEVLINK_PARAM_ID_SAMPLE,
-                                                          "sample", DEVLINK_PARAM_TYPE_BOOL,
-                                                          BIT(DEVLINK_PARAM_CMODE_RUNTIME),dh_devlink_sample_get,
-                                                          dh_devlink_sample_set,
-                                                          NULL),
-                          }
-};
-
-static int32_t params_register(struct devlink *devlink)
-{
-    int32_t i = 0;
-    int32_t err = 0;
-    struct dh_core_dev *dh_dev = devlink_priv(devlink);
-
-    for (i = 0; i < ARRAY_SIZE(devlink_params); i++)
-    {
-        if(devlink_params[i].check(dh_dev))
-        {
-            err = devlink_param_register(devlink, &devlink_params[i].param);
-            if (err)
-            {
-               goto rollback;
-            }
-        }
-    }
-
-    return 0;
-
-rollback:
-    if (i == 0)
-    {
-        return err;
-    }
-
-    for (; i > 0; i--)
-    {
-        devlink_param_unregister(devlink, &devlink_params[i].param);
-    }
-
-    return err;
-}
-
-static int32_t params_unregister(struct devlink *devlink)
-{
-    int32_t i = 0;
-
-    for (i = 0; i < ARRAY_SIZE(devlink_params); i++)
-    {
-        devlink_param_unregister(devlink, &devlink_params[i].param);
-    }
-
-    return 0;
-}
-#else 
-static struct devlink_param devlink_params [] = {
-    [DH_MPF_PARAMS_MAX] = DEVLINK_PARAM_DRIVER(DH_MPF_DEVLINK_PARAM_ID_SAMPLE,
-                                                          "sample", DEVLINK_PARAM_TYPE_BOOL,
-                                                          BIT(DEVLINK_PARAM_CMODE_RUNTIME),dh_devlink_sample_get,
-                                                          dh_devlink_sample_set,
-                                                          NULL),
-};
-
-static int32_t params_register(struct devlink *devlink)
-{
-    struct dh_core_dev * __attribute__((unused)) dh_dev = devlink_priv(devlink);
-    int32_t err = 0;
-
-    err = devlink_params_register(devlink, devlink_params, ARRAY_SIZE(devlink_params));
-
-    return err;
-}
-static int32_t params_unregister(struct devlink *devlink)
-{
-    devlink_params_unregister(devlink, devlink_params, ARRAY_SIZE(devlink_params));
-
-    return 0;
-}
-#endif
-
-struct dh_core_devlink_ops dh_mpf_core_devlink_ops = {
-    .params_register   =  params_register,
-    .params_unregister =  params_unregister
-};
+#include <linux/dinghai/driver.h>
+#include <net/devlink.h>
+#include "devlink.h"
+
+struct devlink_ops dh_mpf_devlink_ops = {
+
+};
+
+enum {
+	DH_MPF_PARAMS_MAX,
+};
+
+static int32_t __attribute__((unused)) sample_check(struct dh_core_dev *dev)
+{
+	return 1;
+}
+
+enum dh_mpf_devlink_param_id {
+	DH_MPF_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
+	DH_MPF_DEVLINK_PARAM_ID_SAMPLE,
+};
+
+static int32_t dh_devlink_sample_set(struct devlink *devlink, uint32_t id,
+									 struct devlink_param_gset_ctx *ctx)
+{
+	struct dh_core_dev *__attribute__((unused)) dev = devlink_priv(devlink);
+
+	return 0;
+}
+
+static int32_t dh_devlink_sample_get(struct devlink *devlink, uint32_t id,
+									 struct devlink_param_gset_ctx *ctx)
+{
+	struct dh_core_dev *__attribute__((unused)) dev = devlink_priv(devlink);
+
+	return 0;
+}
+
+#ifdef HAVE_DEVLINK_PARAM_REGISTER
+static const struct devlink_params {
+	const char *name;
+	int32_t (*check)(struct dh_core_dev *dev);
+	struct devlink_param param;
+} devlink_params[] = { [DH_MPF_PARAMS_MAX] = {
+							   .name = "sample",
+							   .check = &sample_check,
+							   .param = DEVLINK_PARAM_DRIVER(
+									   DH_MPF_DEVLINK_PARAM_ID_SAMPLE, "sample",
+									   DEVLINK_PARAM_TYPE_BOOL,
+									   BIT(DEVLINK_PARAM_CMODE_RUNTIME),
+									   dh_devlink_sample_get,
+									   dh_devlink_sample_set, NULL),
+					   } };
+
+static int32_t params_register(struct devlink *devlink)
+{
+	int32_t i = 0;
+	int32_t err = 0;
+	struct dh_core_dev *dh_dev = devlink_priv(devlink);
+
+	for (i = 0; i < ARRAY_SIZE(devlink_params); i++) {
+		if (devlink_params[i].check(dh_dev)) {
+			err = devlink_param_register(devlink, &devlink_params[i].param);
+			if (err) {
+				goto rollback;
+			}
+		}
+	}
+
+	return 0;
+
+rollback:
+	if (i == 0) {
+		return err;
+	}
+
+	for (; i > 0; i--) {
+		devlink_param_unregister(devlink, &devlink_params[i].param);
+	}
+
+	return err;
+}
+
+static int32_t params_unregister(struct devlink *devlink)
+{
+	int32_t i = 0;
+
+	for (i = 0; i < ARRAY_SIZE(devlink_params); i++) {
+		devlink_param_unregister(devlink, &devlink_params[i].param);
+	}
+
+	return 0;
+}
+#else
+static struct devlink_param devlink_params[] = {
+	[DH_MPF_PARAMS_MAX] = DEVLINK_PARAM_DRIVER(
+			DH_MPF_DEVLINK_PARAM_ID_SAMPLE, "sample", DEVLINK_PARAM_TYPE_BOOL,
+			BIT(DEVLINK_PARAM_CMODE_RUNTIME), dh_devlink_sample_get,
+			dh_devlink_sample_set, NULL),
+};
+
+static int32_t params_register(struct devlink *devlink)
+{
+	struct dh_core_dev *__attribute__((unused)) dh_dev = devlink_priv(devlink);
+	int32_t err = 0;
+
+	err = devlink_params_register(devlink, devlink_params,
+								  ARRAY_SIZE(devlink_params));
+
+	return err;
+}
+static int32_t params_unregister(struct devlink *devlink)
+{
+	devlink_params_unregister(devlink, devlink_params,
+							  ARRAY_SIZE(devlink_params));
+
+	return 0;
+}
+#endif
+
+struct dh_core_devlink_ops dh_mpf_core_devlink_ops = {
+	.params_register = params_register,
+	.params_unregister = params_unregister
+};
diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/devlink.h b/src/net/drivers/net/ethernet/dinghai/en_mpf/devlink.h
old mode 100755
new mode 100644
index a45fd1009d0f0a86da48b4a7acc40eaad9b9fa2e..7dea3be9aad73e4359eaf6eea720c2fcf773a933
--- a/src/net/drivers/net/ethernet/dinghai/en_mpf/devlink.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/devlink.h
@@ -1,16 +1,14 @@
-#ifndef __ZXDH_MPF_DEVLINK_H__
-#define __ZXDH_MPF_DEVLINK_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/devlink.h>
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef __ZXDH_MPF_DEVLINK_H__
+#define __ZXDH_MPF_DEVLINK_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/devlink.h>
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/eq.c b/src/net/drivers/net/ethernet/dinghai/en_mpf/eq.c
old mode 100755
new mode 100644
index 0d8b612a27c455bc3128823d500205deda2e886e..c6ed8d90328d60ae5f78beb84391e9c65b105cb4
--- a/src/net/drivers/net/ethernet/dinghai/en_mpf/eq.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/eq.c
@@ -1,235 +1,236 @@
-#include <linux/dinghai/eq.h>
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/dh_cmd.h>
-#include <linux/dinghai/helper.h>
-#include "irq.h"
-#include "eq.h"
-#include "../en_mpf.h"
-
-struct dh_mpf_eq_table {
-    struct dh_irq      **comp_irqs;
-    struct dh_irq      *async_risc_irq;
-    struct dh_irq      *async_pf_irq;
-    struct dh_eq_async async_risc_eq;
-    struct dh_eq_async async_pf_eq;
-};
-
-static int32_t create_async_eqs(struct dh_core_dev *dev);
-
-static int32_t __attribute__((unused)) create_eq_map(struct dh_eq_param *param)
-{
-    int32_t err = 0;
-
-    /* inform device*/
-    return err;
-}
-
-int32_t dh_mpf_eq_table_init(struct dh_core_dev *dev)
-{
-    struct dh_eq_table *eq_table;
-    struct dh_mpf_eq_table *table_priv = NULL;
-    int32_t err                        = 0;
-
-    eq_table = &dev->eq_table;
-
-    table_priv = kvzalloc(sizeof(*table_priv), GFP_KERNEL);  
-    if (unlikely(table_priv == NULL))
-    {
-        err = -ENOMEM;
-        goto err_table_priv;
-    }
-
-    dh_eq_table_init(dev, table_priv);
-
-    return 0;
-
-err_table_priv:
-    kvfree(eq_table);
-    return err;
-}
-
-/*todo*/
-int32_t dh_eq_get_comp_eqs(struct dh_core_dev *dev)
-{
-    return 0;
-}
-
-static int32_t create_comp_eqs(struct dh_core_dev *dev)
-{
-    return 0;
-}
-
-static int32_t destroy_async_eq(struct dh_core_dev *dev)
-{
-    struct dh_eq_table *eq_table = &dev->eq_table;
-
-    mutex_lock(&eq_table->lock);
-    /*unmap inform device*/
-    mutex_unlock(&eq_table->lock);
-
-    return 0;
-}
-
-static void cleanup_async_eq(struct dh_core_dev *dev,
-                             struct dh_eq_async *eq, const char *name)
-{
-    dh_eq_disable(dev, &eq->core, &eq->irq_nb);
-}
-
-static void destroy_async_eqs(struct dh_core_dev *dev)
-{
-    struct dh_eq_table *table          = &dev->eq_table;
-    struct dh_mpf_eq_table *table_priv = table->priv;
-
-    cleanup_async_eq(dev, &table_priv->async_risc_eq, "riscv");
-    cleanup_async_eq(dev, &table_priv->async_pf_eq, "pf");
-    destroy_async_eq(dev);
-    dh_irqs_release_vectors(&table_priv->async_risc_irq, 1);
-    dh_irqs_release_vectors(&table_priv->async_pf_irq, 1);
-}
-
-void destroy_comp_eqs(struct dh_core_dev *dev)
-{
-
-}
-
-void dh_mpf_eq_table_destroy(struct dh_core_dev *dev)
-{
-    destroy_comp_eqs(dev);
-    destroy_async_eqs(dev);
-}
-
-int32_t dh_mpf_eq_table_create(struct dh_core_dev *dev)
-{
-    int32_t err                  = 0;
-
-    err = create_async_eqs(dev);
-    if (err != 0)
-    {
-        dh_err(dev, "Failed to create async EQs\n");
-        goto err_async_eqs;
-    }
-
-    err = create_comp_eqs(dev);
-    if (err != 0)
-    {
-        dh_err(dev, "Failed to create completion EQs\n");
-        goto err_comp_eqs;
-    }
-
-    return 0;
-
-err_comp_eqs:
-    destroy_async_eqs(dev);
-err_async_eqs:
-    return err;
-}
-
-/*create eventq*/
-static int32_t create_async_eq(struct dh_core_dev *dev, struct dh_irq *risc, struct dh_irq *pf)
-{
-    struct dh_eq_table *eq_table = &dev->eq_table;
-    struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dev);
-    struct msix_para in = {0};
-    int32_t err = 0;
-
-    in.vector_risc = risc->index;
-    in.vector_pfvf = pf->index;
-    in.vector_mpf = 0xff;
-    in.driver_type = MSG_CHAN_END_PF;//TODO
-    in.pdev = dev->pdev;
-    in.virt_addr = mpf_dev->pci_ioremap_addr + ZXDH_BAR1_CHAN_OFFSET;
-
-    mutex_lock(&eq_table->lock);
-
-    err = zxdh_bar_enable_chan(&in, &mpf_dev->vport);
-
-    mutex_unlock(&eq_table->lock);
-
-    return err;
-}
-
-static int32_t dh_eq_async_riscv_int(struct notifier_block *nb, unsigned long action, void *data)
-{
-    struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
-    struct dh_eq_table *eq_table = &dev->eq_table;
-
-    atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF], DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF, NULL);
-
-    return 0;
-}
-
-static int32_t dh_eq_async_mpf_int(struct notifier_block *nb, unsigned long action, void *data)
-{
-    struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
-    struct dh_eq_table *eq_table = &dev->eq_table;
-
-    atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_PF_TO_MPF], DH_EVENT_TYPE_NOTIFY_PF_TO_MPF, NULL);
-
-    return 0;
-}
-
-static int32_t create_async_eqs(struct dh_core_dev *dev)
-{
-    struct dh_eq_table *table          = &dev->eq_table;
-    struct dh_mpf_eq_table *table_priv = table->priv;
-    struct dh_eq_param param           = {};
-    int32_t err                        = 0;
-
-    dh_dbg(dev, "start\r\n");
-    table_priv->async_risc_irq = dh_mpf_async_irq_request(dev);
-    if (IS_ERR_OR_NULL(table_priv->async_risc_irq))
-    {
-        dh_err(dev, "Failed to get async_risc_irq\n");
-        return PTR_ERR(table_priv->async_risc_irq);
-    }
-
-    table_priv->async_pf_irq = dh_mpf_async_irq_request(dev);
-    if (IS_ERR_OR_NULL(table_priv->async_pf_irq))
-    {
-        err = PTR_ERR(table_priv->async_pf_irq);
-        dh_err(dev, "Failed to get async_pf_irq\n");
-        goto err_irq_request;
-    }
-
-    err = create_async_eq(dev, table_priv->async_risc_irq, table_priv->async_pf_irq);
-    if (err != 0)
-    {
-        dh_err(dev, "Failed to create async_eq\n");
-        goto err_create_async_eq;
-    }
-
-    param = (struct dh_eq_param) {
-        .irq = table_priv->async_risc_irq,
-        .nent = 10,
-        .event_type = DH_EVENT_QUEUE_TYPE_RISCV /* used for inform dpu */
-    };
-    err = setup_async_eq(dev, &table_priv->async_risc_eq, &param, dh_eq_async_riscv_int, "riscv", dev);
-    if (err != 0)
-    {
-        dh_err(dev, "Failed to setup async_risc_eq\n");
-        goto err_setup_async_eq;
-    }
-
-    param.irq = table_priv->async_pf_irq,
-    err = setup_async_eq(dev, &table_priv->async_pf_eq, &param, dh_eq_async_mpf_int, "pf", dev);
-    if (err != 0)
-    {
-        dh_err(dev, "Failed to setup async_pf_eq\n");
-        goto cleanup_async_eq;
-    }
-
-    return 0;
-
-cleanup_async_eq:
-    cleanup_async_eq(dev, &table_priv->async_risc_eq, "riscv");
-err_setup_async_eq:
-    destroy_async_eq(dev);
-err_create_async_eq:
-    dh_irqs_release_vectors(&table_priv->async_pf_irq, 1);
-err_irq_request:
-    dh_irqs_release_vectors(&table_priv->async_risc_irq, 1);
-    return err;
+#include <linux/dinghai/eq.h>
+#include <linux/dinghai/driver.h>
+#include <linux/dinghai/dh_cmd.h>
+#include <linux/dinghai/helper.h>
+#include "irq.h"
+#include "eq.h"
+#include "../en_mpf.h"
+
+struct dh_mpf_eq_table {
+	struct dh_irq **comp_irqs;
+	struct dh_irq *async_risc_irq;
+	struct dh_irq *async_pf_irq;
+	struct dh_eq_async async_risc_eq;
+	struct dh_eq_async async_pf_eq;
+};
+
+static int32_t create_async_eqs(struct dh_core_dev *dev);
+
+static int32_t __attribute__((unused)) create_eq_map(struct dh_eq_param *param)
+{
+	int32_t err = 0;
+
+	/* inform device*/
+	return err;
+}
+
+int32_t dh_mpf_eq_table_init(struct dh_core_dev *dev)
+{
+	struct dh_eq_table *eq_table;
+	struct dh_mpf_eq_table *table_priv = NULL;
+	int32_t err = 0;
+
+	eq_table = &dev->eq_table;
+
+	table_priv = kvzalloc(sizeof(*table_priv), GFP_KERNEL);
+	if (unlikely(table_priv == NULL)) {
+		err = -ENOMEM;
+		goto err_table_priv;
+	}
+
+	dh_eq_table_init(dev, table_priv);
+
+	return 0;
+
+err_table_priv:
+	kvfree(eq_table);
+	return err;
+}
+
+/*todo*/
+int32_t dh_eq_get_comp_eqs(struct dh_core_dev *dev)
+{
+	return 0;
+}
+
+static int32_t create_comp_eqs(struct dh_core_dev *dev)
+{
+	return 0;
+}
+
+static int32_t destroy_async_eq(struct dh_core_dev *dev)
+{
+	struct dh_eq_table *eq_table = &dev->eq_table;
+
+	mutex_lock(&eq_table->lock);
+	/*unmap inform device*/
+	mutex_unlock(&eq_table->lock);
+
+	return 0;
+}
+
+static void cleanup_async_eq(struct dh_core_dev *dev, struct dh_eq_async *eq,
+							 const char *name)
+{
+	dh_eq_disable(dev, &eq->core, &eq->irq_nb);
+}
+
+static void destroy_async_eqs(struct dh_core_dev *dev)
+{
+	struct dh_eq_table *table = &dev->eq_table;
+	struct dh_mpf_eq_table *table_priv = table->priv;
+
+	cleanup_async_eq(dev, &table_priv->async_risc_eq, "riscv");
+	cleanup_async_eq(dev, &table_priv->async_pf_eq, "pf");
+	destroy_async_eq(dev);
+	dh_irqs_release_vectors(&table_priv->async_risc_irq, 1);
+	dh_irqs_release_vectors(&table_priv->async_pf_irq, 1);
+}
+
+void destroy_comp_eqs(struct dh_core_dev *dev)
+{
+}
+
+void dh_mpf_eq_table_destroy(struct dh_core_dev *dev)
+{
+	destroy_comp_eqs(dev);
+	destroy_async_eqs(dev);
+}
+
+int32_t dh_mpf_eq_table_create(struct dh_core_dev *dev)
+{
+	int32_t err = 0;
+
+	err = create_async_eqs(dev);
+	if (err != 0) {
+		dh_err(dev, "Failed to create async EQs\n");
+		goto err_async_eqs;
+	}
+
+	err = create_comp_eqs(dev);
+	if (err != 0) {
+		dh_err(dev, "Failed to create completion EQs\n");
+		goto err_comp_eqs;
+	}
+
+	return 0;
+
+err_comp_eqs:
+	destroy_async_eqs(dev);
+err_async_eqs:
+	return err;
+}
+
+/*create eventq*/
+static int32_t create_async_eq(struct dh_core_dev *dev, struct dh_irq *risc,
+							   struct dh_irq *pf)
+{
+	struct dh_eq_table *eq_table = &dev->eq_table;
+	struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dev);
+	struct msix_para in = { 0 };
+	int32_t err = 0;
+
+	in.vector_risc = risc->index;
+	in.vector_pfvf = pf->index;
+	in.vector_mpf = 0xff;
+	in.driver_type = MSG_CHAN_END_PF; // TODO
+	in.pdev = dev->pdev;
+	in.virt_addr = mpf_dev->pci_ioremap_addr + ZXDH_BAR1_CHAN_OFFSET;
+
+	mutex_lock(&eq_table->lock);
+
+	err = zxdh_bar_enable_chan(&in, &mpf_dev->vport);
+
+	mutex_unlock(&eq_table->lock);
+
+	return err;
+}
+
+static int32_t dh_eq_async_riscv_int(struct notifier_block *nb,
+									 unsigned long action, void *data)
+{
+	struct dh_eq_async *eq_riscv_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
+	struct dh_eq_table *eq_table = &dev->eq_table;
+
+	atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF],
+							   DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF, NULL);
+
+	return 0;
+}
+
+static int32_t dh_eq_async_mpf_int(struct notifier_block *nb,
+								   unsigned long action, void *data)
+{
+	struct dh_eq_async *eq_riscv_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
+	struct dh_eq_table *eq_table = &dev->eq_table;
+
+	atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_PF_TO_MPF],
+							   DH_EVENT_TYPE_NOTIFY_PF_TO_MPF, NULL);
+
+	return 0;
+}
+
+static int32_t create_async_eqs(struct dh_core_dev *dev)
+{
+	struct dh_eq_table *table = &dev->eq_table;
+	struct dh_mpf_eq_table *table_priv = table->priv;
+	struct dh_eq_param param = {};
+	int32_t err = 0;
+
+	dh_dbg(dev, "start\r\n");
+	table_priv->async_risc_irq = dh_mpf_async_irq_request(dev);
+	if (IS_ERR_OR_NULL(table_priv->async_risc_irq)) {
+		dh_err(dev, "Failed to get async_risc_irq\n");
+		return PTR_ERR(table_priv->async_risc_irq);
+	}
+
+	table_priv->async_pf_irq = dh_mpf_async_irq_request(dev);
+	if (IS_ERR_OR_NULL(table_priv->async_pf_irq)) {
+		err = PTR_ERR(table_priv->async_pf_irq);
+		dh_err(dev, "Failed to get async_pf_irq\n");
+		goto err_irq_request;
+	}
+
+	err = create_async_eq(dev, table_priv->async_risc_irq,
+						  table_priv->async_pf_irq);
+	if (err != 0) {
+		dh_err(dev, "Failed to create async_eq\n");
+		goto err_create_async_eq;
+	}
+
+	param = (struct dh_eq_param){
+		.irq = table_priv->async_risc_irq,
+		.nent = 10,
+		.event_type = DH_EVENT_QUEUE_TYPE_RISCV /* used for inform dpu */
+	};
+	err = setup_async_eq(dev, &table_priv->async_risc_eq, &param,
+						 dh_eq_async_riscv_int, "riscv", dev);
+	if (err != 0) {
+		dh_err(dev, "Failed to setup async_risc_eq\n");
+		goto err_setup_async_eq;
+	}
+
+	param.irq = table_priv->async_pf_irq,
+	err = setup_async_eq(dev, &table_priv->async_pf_eq, &param,
+						 dh_eq_async_mpf_int, "pf", dev);
+	if (err != 0) {
+		dh_err(dev, "Failed to setup async_pf_eq\n");
+		goto cleanup_async_eq;
+	}
+
+	return 0;
+
+cleanup_async_eq:
+	cleanup_async_eq(dev, &table_priv->async_risc_eq, "riscv");
+err_setup_async_eq:
+	destroy_async_eq(dev);
+err_create_async_eq:
+	dh_irqs_release_vectors(&table_priv->async_pf_irq, 1);
+err_irq_request:
+	dh_irqs_release_vectors(&table_priv->async_risc_irq, 1);
+	return err;
 }
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/eq.h b/src/net/drivers/net/ethernet/dinghai/en_mpf/eq.h
old mode 100755
new mode 100644
index 4aaaaaee6b4c6426214c934fa70b0d9f56254c91..e962267a1ae63c17db0f671bdcedfe720c39818b
--- a/src/net/drivers/net/ethernet/dinghai/en_mpf/eq.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/eq.h
@@ -1,19 +1,19 @@
-#ifndef __ZXDH_MPF_EQ_H__
-#define __ZXDH_MPF_EQ_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/driver.h>
-
-int32_t dh_mpf_eq_table_init(struct dh_core_dev *dev);
-
-int32_t dh_mpf_eq_table_create(struct dh_core_dev *dev);
-void dh_mpf_eq_table_destroy(struct dh_core_dev *dev);
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef __ZXDH_MPF_EQ_H__
+#define __ZXDH_MPF_EQ_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/driver.h>
+
+int32_t dh_mpf_eq_table_init(struct dh_core_dev *dev);
+
+int32_t dh_mpf_eq_table_create(struct dh_core_dev *dev);
+void dh_mpf_eq_table_destroy(struct dh_core_dev *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/events.c b/src/net/drivers/net/ethernet/dinghai/en_mpf/events.c
old mode 100755
new mode 100644
index 35aaf52711e8d6f2e741aad09a0d8ec5081412f7..d0d701329777398a9d2ba12a26a9c5a9897d71c9
--- a/src/net/drivers/net/ethernet/dinghai/en_mpf/events.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/events.c
@@ -1,132 +1,140 @@
-#include <linux/gfp.h>
-#include <linux/slab.h>
-#include <linux/dinghai/driver.h>
-#include <linux/notifier.h>
-#include <linux/dinghai/events.h>
-#include <linux/dinghai/dh_cmd.h>
-#include <linux/workqueue.h>
-#include <linux/kernel.h>
-#include "events.h"
-#include "../en_mpf.h"
-
-static int32_t riscv_notifier(struct notifier_block *nb, unsigned long type, void *data);
-static int32_t pf_notifier(struct notifier_block *nb, unsigned long type, void *data);
-
-static struct dh_nb mpf_events[] = {
-    {.nb.notifier_call = riscv_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF},
-    {.nb.notifier_call = pf_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_PF_TO_MPF}
-};
-
-static int32_t riscv_notifier(struct notifier_block *nb, unsigned long type, void *data)
-{
-    struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
-    struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
-    struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
-
-    zxdh_events_work_enqueue(dh_dev, &mpf_dev->dh_np_sdk_from_risc);
-
-    return NOTIFY_OK;
-}
-
-static int32_t pf_notifier(struct notifier_block *nb, unsigned long type, void *data)
-{
-    struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
-    struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
-    struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
-
-    zxdh_events_work_enqueue(dh_dev, &mpf_dev->dh_np_sdk_from_pf);
-
-    return NOTIFY_OK;
-}
-
-void np_sdk_handler_from_risc(struct work_struct *p_work)
-{
-    struct dh_en_mpf_dev *mpf_dev = container_of(p_work, struct dh_en_mpf_dev, dh_np_sdk_from_risc);
-
-    LOG_INFO("is called\n");
-    zxdh_bar_irq_recv(MSG_CHAN_END_RISC, MSG_CHAN_END_MPF, mpf_dev->pci_ioremap_addr + ZXDH_BAR1_CHAN_OFFSET, NULL);
-    return;
-}
-
-void np_sdk_handler_from_pf(struct work_struct *p_work)
-{
-    struct dh_en_mpf_dev *mpf_dev = container_of(p_work, struct dh_en_mpf_dev, dh_np_sdk_from_pf);
-
-    LOG_INFO("is called\n");
-    zxdh_bar_irq_recv(MSG_CHAN_END_PF, MSG_CHAN_END_MPF, mpf_dev->pci_ioremap_addr + ZXDH_BAR2_CHAN_OFFSET, NULL);
-    return;
-}
-
-void zxdh_events_start(struct dh_core_dev *dev)
-{
-    struct dh_events *events = dev->events;
-    int32_t i;
-    int32_t err;
-
-    for (i = 0; i < ARRAY_SIZE(mpf_events); i++)
-    {
-        events->notifiers[i].nb = mpf_events[i];
-        events->notifiers[i].ctx = dev;
-        err = dh_eq_notifier_register(&dev->eq_table, &events->notifiers[i].nb);
-        if (err != 0)
-        {
-            LOG_ERR("i: %d, err: %d.\n", i, err);
-        }
-    }
-}
-
-int32_t dh_mpf_events_init(struct dh_core_dev *dev)
-{
-    struct dh_events *events = NULL;
-    struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dev);
-    int32_t ret = 0;
-
-    events = kzalloc((sizeof(*events) + ARRAY_SIZE(mpf_events) * sizeof(struct dh_event_nb)), GFP_KERNEL);
-    if (unlikely(events == NULL))
-    {
-        LOG_ERR("events kzalloc failed: %p\n", events);
-        ret = -ENOMEM;
-        goto err_events_kzalloc;
-    }
-
-    events->evt_num = ARRAY_SIZE(mpf_events);
-    events->dev = dev;
-    dev->events = events;
-    events->wq = create_singlethread_workqueue("dh_mpf_events");
-    if (!events->wq)
-    {
-        LOG_ERR("events->wq create_singlethread_workqueue failed: %p\n", events->wq);
-        ret = -ENOMEM;
-        goto err_create_wq;
-    }
-
-    INIT_WORK(&mpf_dev->dh_np_sdk_from_risc, np_sdk_handler_from_risc);
-    INIT_WORK(&mpf_dev->dh_np_sdk_from_pf, np_sdk_handler_from_pf);
-
-    zxdh_events_start(dev);
-
-    return 0;
-
-err_create_wq:
-    kfree(events);
-err_events_kzalloc:
-    return ret;
-}
-
-void dh_events_stop(struct dh_core_dev *dev)
-{
-    struct dh_events *events = dev->events;
-    int32_t i = 0;
-
-    for (i = ARRAY_SIZE(mpf_events) - 1; i >= 0 ; i--)
-    {
-        dh_eq_notifier_unregister(&dev->eq_table, &events->notifiers[i].nb);
-    }
-
-    zxdh_events_cleanup(dev);
-}
-
-void dh_mpf_events_uninit(struct dh_core_dev *dev)
-{
-    return dh_events_stop(dev);
+#include <linux/gfp.h>
+#include <linux/slab.h>
+#include <linux/dinghai/driver.h>
+#include <linux/notifier.h>
+#include <linux/dinghai/events.h>
+#include <linux/dinghai/dh_cmd.h>
+#include <linux/workqueue.h>
+#include <linux/kernel.h>
+#include "events.h"
+#include "../en_mpf.h"
+
+static int32_t riscv_notifier(struct notifier_block *nb, unsigned long type,
+							  void *data);
+static int32_t pf_notifier(struct notifier_block *nb, unsigned long type,
+						   void *data);
+
+static struct dh_nb mpf_events[] = {
+	{ .nb.notifier_call = riscv_notifier,
+	  .event_type = DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF },
+	{ .nb.notifier_call = pf_notifier,
+	  .event_type = DH_EVENT_TYPE_NOTIFY_PF_TO_MPF }
+};
+
+static int32_t riscv_notifier(struct notifier_block *nb, unsigned long type,
+							  void *data)
+{
+	struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
+	struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
+	struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
+
+	zxdh_events_work_enqueue(dh_dev, &mpf_dev->dh_np_sdk_from_risc);
+
+	return NOTIFY_OK;
+}
+
+static int32_t pf_notifier(struct notifier_block *nb, unsigned long type,
+						   void *data)
+{
+	struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
+	struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
+	struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
+
+	zxdh_events_work_enqueue(dh_dev, &mpf_dev->dh_np_sdk_from_pf);
+
+	return NOTIFY_OK;
+}
+
+void np_sdk_handler_from_risc(struct work_struct *p_work)
+{
+	struct dh_en_mpf_dev *mpf_dev =
+			container_of(p_work, struct dh_en_mpf_dev, dh_np_sdk_from_risc);
+
+	LOG_INFO("is called\n");
+	zxdh_bar_irq_recv(MSG_CHAN_END_RISC, MSG_CHAN_END_MPF,
+					  mpf_dev->pci_ioremap_addr + ZXDH_BAR1_CHAN_OFFSET, NULL);
+	return;
+}
+
+void np_sdk_handler_from_pf(struct work_struct *p_work)
+{
+	struct dh_en_mpf_dev *mpf_dev =
+			container_of(p_work, struct dh_en_mpf_dev, dh_np_sdk_from_pf);
+
+	LOG_INFO("is called\n");
+	zxdh_bar_irq_recv(MSG_CHAN_END_PF, MSG_CHAN_END_MPF,
+					  mpf_dev->pci_ioremap_addr + ZXDH_BAR2_CHAN_OFFSET, NULL);
+	return;
+}
+
+void zxdh_events_start(struct dh_core_dev *dev)
+{
+	struct dh_events *events = dev->events;
+	int32_t i;
+	int32_t err;
+
+	for (i = 0; i < ARRAY_SIZE(mpf_events); i++) {
+		events->notifiers[i].nb = mpf_events[i];
+		events->notifiers[i].ctx = dev;
+		err = dh_eq_notifier_register(&dev->eq_table, &events->notifiers[i].nb);
+		if (err != 0) {
+			LOG_ERR("i: %d, err: %d.\n", i, err);
+		}
+	}
+}
+
+int32_t dh_mpf_events_init(struct dh_core_dev *dev)
+{
+	struct dh_events *events = NULL;
+	struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dev);
+	int32_t ret = 0;
+
+	events = kzalloc((sizeof(*events) +
+					  ARRAY_SIZE(mpf_events) * sizeof(struct dh_event_nb)),
+					 GFP_KERNEL);
+	if (unlikely(events == NULL)) {
+		LOG_ERR("events kzalloc failed: %p\n", events);
+		ret = -ENOMEM;
+		goto err_events_kzalloc;
+	}
+
+	events->evt_num = ARRAY_SIZE(mpf_events);
+	events->dev = dev;
+	dev->events = events;
+	events->wq = create_singlethread_workqueue("dh_mpf_events");
+	if (!events->wq) {
+		LOG_ERR("events->wq create_singlethread_workqueue failed: %p\n",
+				events->wq);
+		ret = -ENOMEM;
+		goto err_create_wq;
+	}
+
+	INIT_WORK(&mpf_dev->dh_np_sdk_from_risc, np_sdk_handler_from_risc);
+	INIT_WORK(&mpf_dev->dh_np_sdk_from_pf, np_sdk_handler_from_pf);
+
+	zxdh_events_start(dev);
+
+	return 0;
+
+err_create_wq:
+	kfree(events);
+err_events_kzalloc:
+	return ret;
+}
+
+void dh_events_stop(struct dh_core_dev *dev)
+{
+	struct dh_events *events = dev->events;
+	int32_t i = 0;
+
+	for (i = ARRAY_SIZE(mpf_events) - 1; i >= 0; i--) {
+		dh_eq_notifier_unregister(&dev->eq_table, &events->notifiers[i].nb);
+	}
+
+	zxdh_events_cleanup(dev);
+}
+
+void dh_mpf_events_uninit(struct dh_core_dev *dev)
+{
+	return dh_events_stop(dev);
 }
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/events.h b/src/net/drivers/net/ethernet/dinghai/en_mpf/events.h
old mode 100755
new mode 100644
index 496097e7ffdb0a06d04c5c47e5bcb07f1000ada0..20496792f5c710c2027f36d1150d9599a1383a56
--- a/src/net/drivers/net/ethernet/dinghai/en_mpf/events.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/events.h
@@ -1,18 +1,18 @@
-#ifndef __ZXDH_MPF_EVENTS_H__
-#define __ZXDH_MPF_EVENTS_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/driver.h>
-
-int32_t dh_mpf_events_init(struct dh_core_dev *dev);
-void dh_mpf_events_uninit(struct dh_core_dev *dev);
-void zxdh_events_start(struct dh_core_dev *dev);
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef __ZXDH_MPF_EVENTS_H__
+#define __ZXDH_MPF_EVENTS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/driver.h>
+
+int32_t dh_mpf_events_init(struct dh_core_dev *dev);
+void dh_mpf_events_uninit(struct dh_core_dev *dev);
+void zxdh_events_start(struct dh_core_dev *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/irq.c b/src/net/drivers/net/ethernet/dinghai/en_mpf/irq.c
old mode 100755
new mode 100644
index a1ccaab8ea0a35c5e1e5a95d670dd9e8730187e8..aa036edb2658f821ab5df28c033f3555367547f3
--- a/src/net/drivers/net/ethernet/dinghai/en_mpf/irq.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/irq.c
@@ -1,171 +1,164 @@
-#include <linux/pci.h>
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/helper.h>
-#include "irq.h"
-
-#define ZXDH_MPF_ASYNC_IRQ_MIN_COMP 0
-#define ZXDH_MPF_ASYNC_IRQ_MAX_COMP 1
-
-#define ZXDH_MPF_COMP_IRQ_MIN_COMP 0
-#define ZXDH_MPF_COMP_IRQ_MAX_COMP 1
-
-#ifndef CONFIG_DINGHAI_ZF_MPF
-#define ZXDH_MPF_ASYNC_IRQ_NUM 2
-#else
-#define ZXDH_MPF_ASYNC_IRQ_NUM 6
-#endif
-
-struct dh_mpf_irq_table {
-    struct dh_irq_pool *mpf_comp_pool;
-    struct dh_irq_pool *mpf_async_pool;
-};
-
-struct dh_irq_range {
-    int32_t start;
-    int32_t size;
-};
-
-static struct dh_irq_range zxdh_get_mpf_range(struct dh_core_dev *dev)
-{
-    struct dh_irq_range tmp = {
-        .start = 0,
-        .size = ZXDH_MPF_ASYNC_IRQ_NUM
-    };
-
-    return tmp;
-}
-static struct dh_irq_range zxdh_get_comp_mpf_range(struct dh_core_dev *dev)
-{
-    struct dh_irq_range tmp = {
-        .start = ZXDH_MPF_ASYNC_IRQ_NUM + 1,
-        .size = ZXDH_MPF_ASYNC_IRQ_NUM + 1
-    };
-
-    return tmp;
-}
-
-static int32_t irq_pools_init(struct dh_core_dev *dev)
-{
-    struct dh_irq_table *table              = &dev->irq_table;
-    int32_t err                             = 0;
-    struct dh_irq_range irq_range;
-    struct dh_mpf_irq_table * mpf_irq_table = table->priv;
-
-    /* init mpf_pool */
-    irq_range = zxdh_get_mpf_range(dev);
-
-    mpf_irq_table->mpf_async_pool = irq_pool_alloc(dev, irq_range.start, irq_range.size, "zxdh_mpf_msg",
-                                                   ZXDH_MPF_ASYNC_IRQ_MIN_COMP,
-                                                   ZXDH_MPF_ASYNC_IRQ_MAX_COMP);
-    if (IS_ERR_OR_NULL(mpf_irq_table->mpf_async_pool))
-    {
-        return PTR_ERR(mpf_irq_table->mpf_async_pool);
-    }
-
-    /* init sf_comp_pool */
-    irq_range = zxdh_get_comp_mpf_range(dev);
-
-    mpf_irq_table->mpf_comp_pool = irq_pool_alloc(dev, irq_range.start,
-                                                  irq_range.size, "zxdh_mpf_comp",
-                                                  ZXDH_MPF_COMP_IRQ_MIN_COMP,
-                                                  ZXDH_MPF_COMP_IRQ_MAX_COMP);
-    if (IS_ERR_OR_NULL(mpf_irq_table->mpf_comp_pool))
-    {
-        err = PTR_ERR(mpf_irq_table->mpf_comp_pool);
-        goto err_mpf_comp;
-    }
-
-    mpf_irq_table->mpf_comp_pool->irqs_per_cpu = kcalloc(nr_cpu_ids, sizeof(u16), GFP_KERNEL);
-    if (unlikely(mpf_irq_table->mpf_comp_pool->irqs_per_cpu == NULL))
-    {
-        err = -ENOMEM;
-        goto err_irqs_per_cpu;
-    }
-
-    return 0;
-
-err_irqs_per_cpu:
-    irq_pool_free(mpf_irq_table->mpf_comp_pool);
-err_mpf_comp:
-    irq_pool_free(mpf_irq_table->mpf_async_pool);
-    return err;
-}
-
-static void irq_pools_destroy(struct dh_irq_table *table)
-{
-    struct dh_mpf_irq_table *mpf_irq_table = (struct dh_mpf_irq_table *)table->priv;
-
-    irq_pool_free(mpf_irq_table->mpf_comp_pool);
-    irq_pool_free(mpf_irq_table->mpf_async_pool);
-}
-
-/*todo*/
-static int32_t zxdh_get_total_vec(struct dh_core_dev *dev)
-{
-    return ZXDH_MPF_ASYNC_IRQ_NUM;
-}
-
-int32_t dh_mpf_irq_table_create(struct dh_core_dev *dev)
-{
-    int32_t total_vec = 0;
-    int32_t err       = 0;
-
-    total_vec = zxdh_get_total_vec(dev);
-
-    total_vec = pci_alloc_irq_vectors(dev->pdev, total_vec, total_vec, PCI_IRQ_MSIX);
-    if (total_vec < 0)
-    {
-        dh_err(dev, "pci_alloc_irq_vectors failed: %d\n", total_vec);
-        return total_vec;
-    }
-
-    err = irq_pools_init(dev);
-    if (err != 0)
-    {
-        pci_free_irq_vectors(dev->pdev);
-    }
-
-    return err;
-}
-
-void dh_mpf_irq_table_destroy(struct dh_core_dev *dev)
-{
-    struct dh_irq_table *table = &dev->irq_table;
-
-    /* There are cases where IRQs still will be in used when we reaching
-     * to here. Hence, making sure all the irqs are released.
-     */
-    irq_pools_destroy(table);
-    pci_free_irq_vectors(dev->pdev);
-}
-
-struct dh_irq *dh_mpf_async_irq_request(struct dh_core_dev *dev)
-{
-    struct dh_irq_table *table             = &dev->irq_table;
-    struct dh_mpf_irq_table *mpf_irq_table = (struct dh_mpf_irq_table *)table->priv;
-
-    struct dh_irq *irq = zxdh_get_irq_of_pool(dev, mpf_irq_table->mpf_async_pool);
-    if (IS_ERR_OR_NULL(irq))
-        dh_err(dev, "irq=0x%llx\r\n", (unsigned long long)irq);
-    dh_dbg(dev, "end\r\n");
-    return irq;
-}
-
-/* irq_table API */
-int32_t dh_mpf_irq_table_init(struct dh_core_dev *dev)
-{
-    struct dh_irq_table *irq_table;
-    struct dh_mpf_irq_table * mpf_irq_table = NULL;
-
-    irq_table = &dev->irq_table;
-
-    mpf_irq_table = kvzalloc(sizeof(*mpf_irq_table), GFP_KERNEL);
-    if (unlikely(mpf_irq_table == NULL))
-    {
-        return -ENOMEM;
-    }
-
-    irq_table->priv = mpf_irq_table;
-
-    return 0;
-}
+#include <linux/pci.h>
+#include <linux/dinghai/driver.h>
+#include <linux/dinghai/helper.h>
+#include "irq.h"
+
+#define ZXDH_MPF_ASYNC_IRQ_MIN_COMP 0
+#define ZXDH_MPF_ASYNC_IRQ_MAX_COMP 1
+
+#define ZXDH_MPF_COMP_IRQ_MIN_COMP 0
+#define ZXDH_MPF_COMP_IRQ_MAX_COMP 1
+
+#ifndef CONFIG_DINGHAI_ZF_MPF
+#define ZXDH_MPF_ASYNC_IRQ_NUM 2
+#else
+#define ZXDH_MPF_ASYNC_IRQ_NUM 6
+#endif
+
+struct dh_mpf_irq_table {
+	struct dh_irq_pool *mpf_comp_pool;
+	struct dh_irq_pool *mpf_async_pool;
+};
+
+struct dh_irq_range {
+	int32_t start;
+	int32_t size;
+};
+
+static struct dh_irq_range zxdh_get_mpf_range(struct dh_core_dev *dev)
+{
+	struct dh_irq_range tmp = { .start = 0, .size = ZXDH_MPF_ASYNC_IRQ_NUM };
+
+	return tmp;
+}
+static struct dh_irq_range zxdh_get_comp_mpf_range(struct dh_core_dev *dev)
+{
+	struct dh_irq_range tmp = { .start = ZXDH_MPF_ASYNC_IRQ_NUM + 1,
+								.size = ZXDH_MPF_ASYNC_IRQ_NUM + 1 };
+
+	return tmp;
+}
+
+static int32_t irq_pools_init(struct dh_core_dev *dev)
+{
+	struct dh_irq_table *table = &dev->irq_table;
+	int32_t err = 0;
+	struct dh_irq_range irq_range;
+	struct dh_mpf_irq_table *mpf_irq_table = table->priv;
+
+	/* init mpf_pool */
+	irq_range = zxdh_get_mpf_range(dev);
+
+	mpf_irq_table->mpf_async_pool = irq_pool_alloc(
+			dev, irq_range.start, irq_range.size, "zxdh_mpf_msg",
+			ZXDH_MPF_ASYNC_IRQ_MIN_COMP, ZXDH_MPF_ASYNC_IRQ_MAX_COMP);
+	if (IS_ERR_OR_NULL(mpf_irq_table->mpf_async_pool)) {
+		return PTR_ERR(mpf_irq_table->mpf_async_pool);
+	}
+
+	/* init sf_comp_pool */
+	irq_range = zxdh_get_comp_mpf_range(dev);
+
+	mpf_irq_table->mpf_comp_pool = irq_pool_alloc(
+			dev, irq_range.start, irq_range.size, "zxdh_mpf_comp",
+			ZXDH_MPF_COMP_IRQ_MIN_COMP, ZXDH_MPF_COMP_IRQ_MAX_COMP);
+	if (IS_ERR_OR_NULL(mpf_irq_table->mpf_comp_pool)) {
+		err = PTR_ERR(mpf_irq_table->mpf_comp_pool);
+		goto err_mpf_comp;
+	}
+
+	mpf_irq_table->mpf_comp_pool->irqs_per_cpu =
+			kcalloc(nr_cpu_ids, sizeof(u16), GFP_KERNEL);
+	if (unlikely(mpf_irq_table->mpf_comp_pool->irqs_per_cpu == NULL)) {
+		err = -ENOMEM;
+		goto err_irqs_per_cpu;
+	}
+
+	return 0;
+
+err_irqs_per_cpu:
+	irq_pool_free(mpf_irq_table->mpf_comp_pool);
+err_mpf_comp:
+	irq_pool_free(mpf_irq_table->mpf_async_pool);
+	return err;
+}
+
+static void irq_pools_destroy(struct dh_irq_table *table)
+{
+	struct dh_mpf_irq_table *mpf_irq_table =
+			(struct dh_mpf_irq_table *)table->priv;
+
+	irq_pool_free(mpf_irq_table->mpf_comp_pool);
+	irq_pool_free(mpf_irq_table->mpf_async_pool);
+}
+
+/*todo*/
+static int32_t zxdh_get_total_vec(struct dh_core_dev *dev)
+{
+	return ZXDH_MPF_ASYNC_IRQ_NUM;
+}
+
+int32_t dh_mpf_irq_table_create(struct dh_core_dev *dev)
+{
+	int32_t total_vec = 0;
+	int32_t err = 0;
+
+	total_vec = zxdh_get_total_vec(dev);
+
+	total_vec = pci_alloc_irq_vectors(dev->pdev, total_vec, total_vec,
+									  PCI_IRQ_MSIX);
+	if (total_vec < 0) {
+		dh_err(dev, "pci_alloc_irq_vectors failed: %d\n", total_vec);
+		return total_vec;
+	}
+
+	err = irq_pools_init(dev);
+	if (err != 0) {
+		pci_free_irq_vectors(dev->pdev);
+	}
+
+	return err;
+}
+
+void dh_mpf_irq_table_destroy(struct dh_core_dev *dev)
+{
+	struct dh_irq_table *table = &dev->irq_table;
+
+	/* There are cases where IRQs still will be in used when we reaching
+   * to here. Hence, making sure all the irqs are released.
+   */
+	irq_pools_destroy(table);
+	pci_free_irq_vectors(dev->pdev);
+}
+
+struct dh_irq *dh_mpf_async_irq_request(struct dh_core_dev *dev)
+{
+	struct dh_irq_table *table = &dev->irq_table;
+	struct dh_mpf_irq_table *mpf_irq_table =
+			(struct dh_mpf_irq_table *)table->priv;
+
+	struct dh_irq *irq =
+			zxdh_get_irq_of_pool(dev, mpf_irq_table->mpf_async_pool);
+	if (IS_ERR_OR_NULL(irq))
+		dh_err(dev, "irq=0x%llx\r\n", (unsigned long long)irq);
+	dh_dbg(dev, "end\r\n");
+	return irq;
+}
+
+/* irq_table API */
+int32_t dh_mpf_irq_table_init(struct dh_core_dev *dev)
+{
+	struct dh_irq_table *irq_table;
+	struct dh_mpf_irq_table *mpf_irq_table = NULL;
+
+	irq_table = &dev->irq_table;
+
+	mpf_irq_table = kvzalloc(sizeof(*mpf_irq_table), GFP_KERNEL);
+	if (unlikely(mpf_irq_table == NULL)) {
+		return -ENOMEM;
+	}
+
+	irq_table->priv = mpf_irq_table;
+
+	return 0;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/irq.h b/src/net/drivers/net/ethernet/dinghai/en_mpf/irq.h
old mode 100755
new mode 100644
index 8cb582b9168b255279fba43cf8f9935f723b452f..c3a1f0d8823c450baec678d54ca2f85a668dcdc7
--- a/src/net/drivers/net/ethernet/dinghai/en_mpf/irq.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_mpf/irq.h
@@ -1,20 +1,20 @@
-#ifndef __ZXDH_MPF_IRQ_H__
-#define __ZXDH_MPF_IRQ_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/dinghai_irq.h>
-#include <linux/dinghai/driver.h>
-
-struct dh_irq *dh_mpf_async_irq_request(struct dh_core_dev *dev);
-void dh_mpf_irq_table_destroy(struct dh_core_dev *dev);
-int32_t dh_mpf_irq_table_create(struct dh_core_dev *dev);
-int32_t dh_mpf_irq_table_init(struct dh_core_dev *dev);
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef __ZXDH_MPF_IRQ_H__
+#define __ZXDH_MPF_IRQ_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/dinghai_irq.h>
+#include <linux/dinghai/driver.h>
+
+struct dh_irq *dh_mpf_async_irq_request(struct dh_core_dev *dev);
+void dh_mpf_irq_table_destroy(struct dh_core_dev *dev);
+int32_t dh_mpf_irq_table_create(struct dh_core_dev *dev);
+int32_t dh_mpf_irq_table_init(struct dh_core_dev *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_mpf/tc.c b/src/net/drivers/net/ethernet/dinghai/en_mpf/tc.c
old mode 100755
new mode 100644
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/agent/include/dpp_agent_channel.h b/src/net/drivers/net/ethernet/dinghai/en_np/agent/include/dpp_agent_channel.h
index 5bc1759e2e725fb06534b45921a44e74038399df..0dcf64093ea06f057922ce3373e8334dad74117d 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/agent/include/dpp_agent_channel.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/agent/include/dpp_agent_channel.h
@@ -5,154 +5,179 @@
 #include "dpp_dev.h"
 #include "dpp_type_api.h"
 
-#define BUFFER_LEN_MAX     (256)
-#define REG_REPS_LEN       (8)
-#define CHANNEL_REPS_LEN   (4)
-#define NP_AGENT_ID        (16)
-#define MSG_REP_OFFSET     (4)
-#define MSG_REP_VALID      (0Xff)
+#define BUFFER_LEN_MAX (256)
+#define REG_REPS_LEN (8)
+#define CHANNEL_REPS_LEN (4)
+#define NP_AGENT_ID (16)
+#define MSG_REP_OFFSET (4)
+#define MSG_REP_VALID (0Xff)
 #define MSG_REP_LEN_OFFSET (1)
 #define SCHE_RSP_LEN (2)
-#define SCHE_REQ_VALID      (0Xffff)
+#define SCHE_REQ_VALID (0Xffff)
 #define PROFILEID_REQ_VALID (0Xffff)
-#define EPID_LEVEL         (4)
+#define EPID_LEVEL (4)
 
 #pragma pack(1)
 
-typedef enum dpp_agent_msg_type
-{
-    DPP_REG_MSG = 0,
-    DPP_DTB_MSG,
-    DPP_TM_MSG,
-    DPP_PLCR_MSG,
-    DPP_TLB_MSG,
-    DPP_FLR_MSG,
-    DPP_RESET_MSG,
-    DPP_MSG_MAX
+typedef enum dpp_agent_msg_type {
+	DPP_REG_MSG = 0,
+	DPP_DTB_MSG,
+	DPP_TM_MSG,
+	DPP_PLCR_MSG,
+	DPP_TLB_MSG,
+	DPP_FLR_MSG,
+	DPP_RESET_MSG,
+	DPP_MSG_MAX
 } MSG_TYPE_E;
 
-typedef enum dpp_agent_msg_oper
-{
-    DPP_WR = 0,
-    DPP_RD,
-    DPP_WR_RD_MAX
+typedef enum dpp_agent_msg_oper {
+	DPP_WR = 0,
+	DPP_RD,
+	DPP_WR_RD_MAX
 } MSG_OPER_E;
 
-typedef enum dpp_msg_dtb_oper
-{
-    QUEUE_REQUEST = 0,
-    QUEUE_RELEASE = 1,
+typedef enum dpp_msg_dtb_oper {
+	QUEUE_REQUEST = 0,
+	QUEUE_RELEASE = 1,
 } MSG_DTB_OPER_E;
 
-typedef enum dpp_msg_tm_oper
-{
-    SEID_REQUEST = 0,
-    SEID_RELEASE = 1,
-    SEID_QUERY = 2
+typedef enum dpp_msg_tm_oper {
+	SEID_REQUEST = 0,
+	SEID_RELEASE = 1,
+	SEID_QUERY = 2
 } MSG_TM_OPER_E;
 
-typedef enum dpp_msg_plcr_oper
-{
-    PROFILEID_REQUEST = 0,
-    PROFILEID_RELEASE = 1,
+typedef enum dpp_msg_plcr_oper {
+	PROFILEID_REQUEST = 0,
+	PROFILEID_RELEASE = 1,
 } MSG_PLCR_OPER_E;
-typedef enum dpp_cosq_sche_type
-{
-    FQ_SCHE = 0,
-    FQ2_SCHE = 1,
-    FQ4_SCHE = 2,
-    FQ8_SCHE = 3,
-    SP_SCHE = 4,
-    WFQ_SCHE = 5,
-    WFQ2_SCHE = 6,
-    WFQ4_SCHE = 7,
-    WFQ8_SCHE = 8,
-    FLOW_SCHE = 9,
-    SCHE_TYPE = 10
+typedef enum dpp_cosq_sche_type {
+	FQ_SCHE = 0,
+	FQ2_SCHE = 1,
+	FQ4_SCHE = 2,
+	FQ8_SCHE = 3,
+	SP_SCHE = 4,
+	WFQ_SCHE = 5,
+	WFQ2_SCHE = 6,
+	WFQ4_SCHE = 7,
+	WFQ8_SCHE = 8,
+	FLOW_SCHE = 9,
+	SCHE_TYPE = 10
 } DPP_COSQ_SCHE_TYPE;
 
-typedef enum dpp_agent_msg_csflag
-{
-    DPP_CS_ADDR_FLAG = 0,
-    DPP_CS_REGNO_FLAG,
-    DPP_CS_FLAG_MAX
+typedef enum dpp_agent_msg_csflag {
+	DPP_CS_ADDR_FLAG = 0,
+	DPP_CS_REGNO_FLAG,
+	DPP_CS_FLAG_MAX
 } MSG_CSFLAG_E;
 
-typedef struct dpp_agent_channel_reg_msg
-{
-    ZXIC_UINT8 devId;
-    ZXIC_UINT8 type;
-    ZXIC_UINT8 subtype;
-    ZXIC_UINT8 oper;
-    ZXIC_UINT32 reg_no;
-    ZXIC_UINT32 addr;
-    ZXIC_UINT32 val_len;
-    ZXIC_UINT32 val[32];
+typedef struct dpp_agent_channel_reg_msg {
+	ZXIC_UINT8 devId;
+	ZXIC_UINT8 type;
+	ZXIC_UINT8 subtype;
+	ZXIC_UINT8 oper;
+	ZXIC_UINT32 reg_no;
+	ZXIC_UINT32 addr;
+	ZXIC_UINT32 val_len;
+	ZXIC_UINT32 val[32];
 } DPP_AGENT_CHANNEL_REG_MSG_T;
 
-typedef struct dpp_agent_channel_dtb_msg
-{
-    ZXIC_UINT8 devId;
-    ZXIC_UINT8 type;
-    ZXIC_UINT8 oper;
-    ZXIC_UINT8 rsv;
-    ZXIC_UINT8 name[32];
-    ZXIC_UINT32 vport;
-    ZXIC_UINT32 queue_id;
+typedef struct dpp_agent_channel_dtb_msg {
+	ZXIC_UINT8 devId;
+	ZXIC_UINT8 type;
+	ZXIC_UINT8 oper;
+	ZXIC_UINT8 rsv;
+	ZXIC_UINT8 name[32];
+	ZXIC_UINT32 vport;
+	ZXIC_UINT32 queue_id;
 } DPP_AGENT_CHANNEL_DTB_MSG_T;
-typedef struct dpp_agent_channel_tm_msg
-{
-    ZXIC_UINT8 devId;
-    ZXIC_UINT8 type;
-    ZXIC_UINT8 oper;
-    ZXIC_UINT8  num;
-    ZXIC_UINT32 port;
-    ZXIC_UINT32 vport;
-    ZXIC_UINT32 sche_level;
-    ZXIC_UINT32 sche_type;
-    ZXIC_UINT32 se_id;
+typedef struct dpp_agent_channel_tm_msg {
+	ZXIC_UINT8 devId;
+	ZXIC_UINT8 type;
+	ZXIC_UINT8 oper;
+	ZXIC_UINT8 num;
+	ZXIC_UINT32 port;
+	ZXIC_UINT32 vport;
+	ZXIC_UINT32 sche_level;
+	ZXIC_UINT32 sche_type;
+	ZXIC_UINT32 se_id;
 } DPP_AGENT_CHANNEL_TM_MSG_T;
-typedef struct dpp_agent_channel_plcr_msg
-{
-    ZXIC_UINT8 devId;
-    ZXIC_UINT8 type;
-    ZXIC_UINT8 oper;
-    ZXIC_UINT8 rsv;
-    ZXIC_UINT32 vport;
-    ZXIC_UINT32 car_type;
-    ZXIC_UINT32 profile_id;
+typedef struct dpp_agent_channel_plcr_msg {
+	ZXIC_UINT8 devId;
+	ZXIC_UINT8 type;
+	ZXIC_UINT8 oper;
+	ZXIC_UINT8 rsv;
+	ZXIC_UINT32 vport;
+	ZXIC_UINT32 car_type;
+	ZXIC_UINT32 profile_id;
 } DPP_AGENT_CHANNEL_PLCR_MSG_T;
-typedef struct dpp_agent_channel_msg
-{
-    ZXIC_UINT32 msg_len;
-    ZXIC_VOID *msg;
+typedef struct dpp_agent_channel_msg {
+	ZXIC_UINT32 msg_len;
+	ZXIC_VOID *msg;
 } DPP_AGENT_CHANNEL_MSG_T;
 
 #pragma pack()
 
 DPP_STATUS dpp_agent_channel_init(ZXIC_VOID);
 DPP_STATUS dpp_agent_channel_exit(ZXIC_VOID);
-DPP_STATUS dpp_agent_channel_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_MSG_T *pMsg,
-                                                            ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len);
-DPP_STATUS dpp_agent_channel_reg_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_REG_MSG_T *pMsg,
-                                                            ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len);
-DPP_STATUS dpp_agent_channel_reg_write(DPP_DEV_T *dev, ZXIC_UINT32 reg_type, ZXIC_UINT32 reg_no,
-                                        ZXIC_UINT32 reg_width, ZXIC_UINT32 addr, ZXIC_UINT32 *pData);
-DPP_STATUS dpp_agent_channel_reg_read(DPP_DEV_T *dev, ZXIC_UINT32 reg_type, ZXIC_UINT32 reg_no,
-                                        ZXIC_UINT32 reg_width, ZXIC_UINT32 addr, ZXIC_UINT32 *pData);
-DPP_STATUS dpp_agent_channel_dtb_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_DTB_MSG_T *pMsg,
-                                                            ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len);
-DPP_STATUS dpp_agent_channel_dtb_queue_request(DPP_DEV_T *dev, ZXIC_CONST ZXIC_UINT8 *p_name, ZXIC_UINT32 vport_info, ZXIC_UINT32 *p_queue_id);
-DPP_STATUS dpp_agent_channel_dtb_queue_release(DPP_DEV_T *dev, ZXIC_CONST ZXIC_UINT8 *p_name, ZXIC_UINT32 queue_id);
-
-DPP_STATUS dpp_agent_channel_tm_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_TM_MSG_T *pMsg, ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len);
-DPP_STATUS dpp_agent_channel_tm_seid_request(DPP_DEV_T *dev, ZXIC_UINT32 port, ZXIC_UINT32 vport, ZXIC_UINT32 sche_level, ZXIC_UINT32 sche_type, ZXIC_UINT32 num, ZXIC_UINT32 *p_se_id);
-DPP_STATUS dpp_agent_channel_tm_seid_release(DPP_DEV_T *dev, ZXIC_UINT32 port, ZXIC_UINT32 vport, ZXIC_UINT32 sche_level, ZXIC_UINT32 sche_type, ZXIC_UINT32 num, ZXIC_UINT32 se_id);
-
-DPP_STATUS dpp_agent_channel_tm_base_node_get(DPP_DEV_T *dev, ZXIC_UINT32 port, ZXIC_UINT32 vport, ZXIC_UINT32 *p_se_id);
-
-DPP_STATUS dpp_agent_channel_plcr_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_PLCR_MSG_T *pMsg, ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len);
-DPP_STATUS dpp_agent_channel_plcr_profileid_request(DPP_DEV_T *dev, ZXIC_UINT32 vport, ZXIC_UINT32 car_type, ZXIC_UINT32 *p_profileid);
-DPP_STATUS dpp_agent_channel_plcr_profileid_release(DPP_DEV_T *dev, ZXIC_UINT32 vport, ZXIC_UINT32 car_type, ZXIC_UINT32 profileid);
+DPP_STATUS dpp_agent_channel_sync_send(DPP_DEV_T *dev,
+									   DPP_AGENT_CHANNEL_MSG_T *pMsg,
+									   ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len);
+DPP_STATUS dpp_agent_channel_reg_sync_send(DPP_DEV_T *dev,
+										   DPP_AGENT_CHANNEL_REG_MSG_T *pMsg,
+										   ZXIC_UINT32 *pData,
+										   ZXIC_UINT32 rep_len);
+DPP_STATUS dpp_agent_channel_reg_write(DPP_DEV_T *dev, ZXIC_UINT32 reg_type,
+									   ZXIC_UINT32 reg_no,
+									   ZXIC_UINT32 reg_width, ZXIC_UINT32 addr,
+									   ZXIC_UINT32 *pData);
+DPP_STATUS dpp_agent_channel_reg_read(DPP_DEV_T *dev, ZXIC_UINT32 reg_type,
+									  ZXIC_UINT32 reg_no, ZXIC_UINT32 reg_width,
+									  ZXIC_UINT32 addr, ZXIC_UINT32 *pData);
+DPP_STATUS dpp_agent_channel_dtb_sync_send(DPP_DEV_T *dev,
+										   DPP_AGENT_CHANNEL_DTB_MSG_T *pMsg,
+										   ZXIC_UINT32 *pData,
+										   ZXIC_UINT32 rep_len);
+DPP_STATUS dpp_agent_channel_dtb_queue_request(DPP_DEV_T *dev,
+											   ZXIC_UINT8 *p_name,
+											   ZXIC_UINT32 vport_info,
+											   ZXIC_UINT32 *p_queue_id);
+DPP_STATUS dpp_agent_channel_dtb_queue_release(DPP_DEV_T *dev,
+											   ZXIC_UINT8 *pName,
+											   ZXIC_UINT32 queueId);
+
+DPP_STATUS dpp_agent_channel_tm_sync_send(DPP_DEV_T *dev,
+										  DPP_AGENT_CHANNEL_TM_MSG_T *pMsg,
+										  ZXIC_UINT32 *pData,
+										  ZXIC_UINT32 rep_len);
+DPP_STATUS dpp_agent_channel_tm_seid_request(DPP_DEV_T *dev, ZXIC_UINT32 port,
+											 ZXIC_UINT32 vport,
+											 ZXIC_UINT32 sche_level,
+											 ZXIC_UINT32 sche_type,
+											 ZXIC_UINT32 num,
+											 ZXIC_UINT32 *p_se_id);
+DPP_STATUS dpp_agent_channel_tm_seid_release(DPP_DEV_T *dev, ZXIC_UINT32 port,
+											 ZXIC_UINT32 vport,
+											 ZXIC_UINT32 sche_level,
+											 ZXIC_UINT32 sche_type,
+											 ZXIC_UINT32 num,
+											 ZXIC_UINT32 se_id);
+
+DPP_STATUS dpp_agent_channel_tm_base_node_get(DPP_DEV_T *dev, ZXIC_UINT32 port,
+											  ZXIC_UINT32 vport,
+											  ZXIC_UINT32 *p_se_id);
+
+DPP_STATUS dpp_agent_channel_plcr_sync_send(DPP_DEV_T *dev,
+											DPP_AGENT_CHANNEL_PLCR_MSG_T *pMsg,
+											ZXIC_UINT32 *pData,
+											ZXIC_UINT32 rep_len);
+DPP_STATUS dpp_agent_channel_plcr_profileid_request(DPP_DEV_T *dev,
+													ZXIC_UINT32 vport,
+													ZXIC_UINT32 car_type,
+													ZXIC_UINT32 *p_profileid);
+DPP_STATUS dpp_agent_channel_plcr_profileid_release(DPP_DEV_T *dev,
+													ZXIC_UINT32 vport,
+													ZXIC_UINT32 car_type,
+													ZXIC_UINT32 profileid);
 
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/agent/source/dpp_agent_channel.c b/src/net/drivers/net/ethernet/dinghai/en_np/agent/source/dpp_agent_channel.c
index e280cb73e8ba612bd9cf1a13a5e1ae8734e5b2ad..29a6dac658e94a194f97ae88abc9387eb143362e 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/agent/source/dpp_agent_channel.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/agent/source/dpp_agent_channel.c
@@ -2,475 +2,526 @@
 #include "dh_cmd.h"
 #include "dpp_dev.h"
 
-DPP_STATUS dpp_agent_channel_init()
+DPP_STATUS dpp_agent_channel_init(ZXIC_VOID)
 {
-    // zxdh_bar_msg_chan_init();
-    return DPP_OK;
+	// zxdh_bar_msg_chan_init();
+	return DPP_OK;
 }
 
-DPP_STATUS dpp_agent_channel_exit()
+DPP_STATUS dpp_agent_channel_exit(ZXIC_VOID)
 {
-    // zxdh_bar_msg_chan_remove();
-    return DPP_OK;
+	// zxdh_bar_msg_chan_remove();
+	return DPP_OK;
 }
 
-DPP_STATUS dpp_agent_channel_reg_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_REG_MSG_T *pMsg,
-                                                        ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len)
+DPP_STATUS dpp_agent_channel_reg_sync_send(DPP_DEV_T *dev,
+										   DPP_AGENT_CHANNEL_REG_MSG_T *pMsg,
+										   ZXIC_UINT32 *pData,
+										   ZXIC_UINT32 rep_len)
 {
-    DPP_STATUS ret = DPP_OK;
-    DPP_AGENT_CHANNEL_MSG_T agentMsg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(pMsg);
-
-    agentMsg.msg                     = (ZXIC_VOID *)pMsg;
-    agentMsg.msg_len                 = sizeof(DPP_AGENT_CHANNEL_REG_MSG_T);
-
-    ret = dpp_agent_channel_sync_send(dev, &agentMsg, pData, rep_len);
-    if (DPP_OK != ret)
-    {
-        ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed\n", __FUNCTION__);
-        return DPP_ERR;
-    }
-
-    ret = *pData;
-    if (DPP_OK != ret)
-    {
-        ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed in buffer\n", __FUNCTION__);
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
+	DPP_STATUS ret = DPP_OK;
+	DPP_AGENT_CHANNEL_MSG_T agentMsg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(pMsg);
+
+	agentMsg.msg = (ZXIC_VOID *)pMsg;
+	agentMsg.msg_len = sizeof(DPP_AGENT_CHANNEL_REG_MSG_T);
+
+	ret = dpp_agent_channel_sync_send(dev, &agentMsg, pData, rep_len);
+	if (DPP_OK != ret) {
+		ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed\n",
+							  __FUNCTION__);
+		return DPP_ERR;
+	}
+
+	ret = *pData;
+	if (DPP_OK != ret) {
+		ZXIC_COMM_TRACE_ERROR(
+				"%s: dpp_agent_channel_sync_send failed in buffer\n",
+				__FUNCTION__);
+		return DPP_ERR;
+	}
+
+	return DPP_OK;
 }
 
-DPP_STATUS dpp_agent_channel_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_MSG_T *pMsg,
-                                                        ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len)
+DPP_STATUS dpp_agent_channel_sync_send(DPP_DEV_T *dev,
+									   DPP_AGENT_CHANNEL_MSG_T *pMsg,
+									   ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len)
 {
-    DPP_STATUS ret            = DPP_OK;
-    ZXIC_UINT8 *reply_ptr     = NULL;
-    ZXIC_UINT16 reply_msg_len = 0;
-    ZXIC_UINT32 *recv_buffer  = NULL;
+	DPP_STATUS ret = DPP_OK;
+	ZXIC_UINT8 *reply_ptr = NULL;
+	ZXIC_UINT16 reply_msg_len = 0;
+	ZXIC_UINT32 *recv_buffer = NULL;
 
-    struct zxdh_pci_bar_msg in          = {0};
-    struct zxdh_msg_recviver_mem result = {0};
+	struct zxdh_pci_bar_msg in = { 0 };
+	struct zxdh_msg_recviver_mem result = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(pMsg);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(pMsg);
 
-    recv_buffer = (ZXIC_UINT32 *)kmalloc(rep_len + CHANNEL_REPS_LEN, GFP_KERNEL);
-    ZXIC_COMM_CHECK_POINT(recv_buffer);
-    ZXIC_COMM_MEMSET(recv_buffer, 0, rep_len + CHANNEL_REPS_LEN);
+	recv_buffer =
+			(ZXIC_UINT32 *)kmalloc(rep_len + CHANNEL_REPS_LEN, GFP_KERNEL);
+	ZXIC_COMM_CHECK_POINT(recv_buffer);
+	ZXIC_COMM_MEMSET(recv_buffer, 0, rep_len + CHANNEL_REPS_LEN);
 
-    in.virt_addr    = DEV_PCIE_MSG_ADDR(dev);
-    in.payload_addr = pMsg->msg;
-    in.payload_len  = pMsg->msg_len;
-    in.src          = MSG_CHAN_END_PF;
-    in.dst          = MSG_CHAN_END_RISC;
-    in.event_id     = NP_AGENT_ID;
-    in.src_pcieid   = DEV_PCIE_ID(dev);
+	in.virt_addr = DEV_PCIE_MSG_ADDR(dev);
+	in.payload_addr = pMsg->msg;
+	in.payload_len = pMsg->msg_len;
+	in.src = MSG_CHAN_END_PF;
+	in.dst = MSG_CHAN_END_RISC;
+	in.event_id = NP_AGENT_ID;
+	in.src_pcieid = DEV_PCIE_ID(dev);
 
-    result.buffer_len  = rep_len + CHANNEL_REPS_LEN;
-    result.recv_buffer = recv_buffer;
+	result.buffer_len = rep_len + CHANNEL_REPS_LEN;
+	result.recv_buffer = recv_buffer;
 
-    ZXIC_COMM_TRACE_DEBUG("%s: in.virt_addr 0x%llx.\n", __FUNCTION__, in.virt_addr);
+	ZXIC_COMM_TRACE_DEBUG("%s: in.virt_addr 0x%llx.\n", __FUNCTION__,
+						  in.virt_addr);
 
-    ret = zxdh_bar_chan_sync_msg_send(&in, &result);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "zxdh_bar_chan_sync_msg_send", recv_buffer);
+	ret = zxdh_bar_chan_sync_msg_send(&in, &result);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "zxdh_bar_chan_sync_msg_send",
+								   recv_buffer);
 
-    reply_ptr = (ZXIC_UINT8 *)(result.recv_buffer);
-    if (MSG_REP_VALID == *reply_ptr)
-    {
-        reply_msg_len = *(ZXIC_UINT16 *)(reply_ptr + MSG_REP_LEN_OFFSET);
-        memcpy(pData, reply_ptr + MSG_REP_OFFSET, ((reply_msg_len > rep_len) ? rep_len : reply_msg_len));
+	reply_ptr = (ZXIC_UINT8 *)(result.recv_buffer);
+	if (MSG_REP_VALID == *reply_ptr) {
+		reply_msg_len = *(ZXIC_UINT16 *)(reply_ptr + MSG_REP_LEN_OFFSET);
+		memcpy(pData, reply_ptr + MSG_REP_OFFSET,
+			   ((reply_msg_len > rep_len) ? rep_len : reply_msg_len));
 
-        kfree(recv_buffer);
-        return DPP_OK;
-    }
+		kfree(recv_buffer);
+		return DPP_OK;
+	}
 
-    kfree(recv_buffer);
+	kfree(recv_buffer);
 
-    ZXIC_COMM_TRACE_ERROR("%s: zxdh_bar_chan_sync_msg_send failed.\n", __FUNCTION__);
+	ZXIC_COMM_TRACE_ERROR("%s: zxdh_bar_chan_sync_msg_send failed.\n",
+						  __FUNCTION__);
 
-    return DPP_ERR;
+	return DPP_ERR;
 }
 
-DPP_STATUS dpp_agent_channel_reg_write(DPP_DEV_T *dev, ZXIC_UINT32 reg_type, ZXIC_UINT32 reg_no,
-                                            ZXIC_UINT32 reg_width, ZXIC_UINT32 addr, ZXIC_UINT32 *pData)
+DPP_STATUS dpp_agent_channel_reg_write(DPP_DEV_T *dev, ZXIC_UINT32 reg_type,
+									   ZXIC_UINT32 reg_no,
+									   ZXIC_UINT32 reg_width, ZXIC_UINT32 addr,
+									   ZXIC_UINT32 *pData)
 {
-    DPP_STATUS ret          = 0;
-    ZXIC_UINT32 resp_len    = 0;
-    ZXIC_UINT8 *resp_buffer = NULL;
+	DPP_STATUS ret = 0;
+	ZXIC_UINT32 resp_len = 0;
+	ZXIC_UINT8 *resp_buffer = NULL;
 
-    DPP_AGENT_CHANNEL_REG_MSG_T msgcfg = {0};
+	DPP_AGENT_CHANNEL_REG_MSG_T msgcfg = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(pData);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(pData);
 
-    msgcfg.devId                       = 0;
-    msgcfg.type                        = DPP_REG_MSG;
-    msgcfg.subtype                     = reg_type;
-    msgcfg.oper                        = DPP_WR;
-    msgcfg.reg_no                      = reg_no;
-    msgcfg.addr                        = addr;
-    msgcfg.val_len                     = reg_width / 4;
-    memcpy(msgcfg.val, pData, reg_width);
+	msgcfg.devId = 0;
+	msgcfg.type = DPP_REG_MSG;
+	msgcfg.subtype = reg_type;
+	msgcfg.oper = DPP_WR;
+	msgcfg.reg_no = reg_no;
+	msgcfg.addr = addr;
+	msgcfg.val_len = reg_width / 4;
+	memcpy(msgcfg.val, pData, reg_width);
 
-    resp_len    = reg_width + 4;
-    resp_buffer = (ZXIC_UINT8 *)kmalloc(resp_len, GFP_KERNEL);
-    ZXIC_COMM_CHECK_POINT(resp_buffer);
+	resp_len = reg_width + 4;
+	resp_buffer = (ZXIC_UINT8 *)kmalloc(resp_len, GFP_KERNEL);
+	ZXIC_COMM_CHECK_POINT(resp_buffer);
 
-    memset(resp_buffer, 0, resp_len);
+	memset(resp_buffer, 0, resp_len);
 
-    ret = dpp_agent_channel_reg_sync_send(dev, &msgcfg, (ZXIC_UINT32 *)resp_buffer, resp_len);
+	ret = dpp_agent_channel_reg_sync_send(dev, &msgcfg,
+										  (ZXIC_UINT32 *)resp_buffer, resp_len);
 
-    if (DPP_OK != ret)
-    {
-        ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_reg_sync_send failed\n", __FUNCTION__);
-        kfree(resp_buffer);
-        return DPP_ERR;
-    }
+	if (DPP_OK != ret) {
+		ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_reg_sync_send failed\n",
+							  __FUNCTION__);
+		kfree(resp_buffer);
+		return DPP_ERR;
+	}
 
-    if (DPP_OK != *((ZXIC_UINT32 *)resp_buffer))
-    {
-        ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_reg_sync_send failed in buffer\n", __FUNCTION__);
-        kfree(resp_buffer);
-        return DPP_ERR;
-    }
+	if (DPP_OK != *((ZXIC_UINT32 *)resp_buffer)) {
+		ZXIC_COMM_TRACE_ERROR(
+				"%s: dpp_agent_channel_reg_sync_send failed in buffer\n",
+				__FUNCTION__);
+		kfree(resp_buffer);
+		return DPP_ERR;
+	}
 
-    memcpy(pData, resp_buffer + 4, reg_width);
+	memcpy(pData, resp_buffer + 4, reg_width);
 
-    kfree(resp_buffer);
+	kfree(resp_buffer);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-DPP_STATUS dpp_agent_channel_reg_read(DPP_DEV_T *dev, ZXIC_UINT32 reg_type, ZXIC_UINT32 reg_no, ZXIC_UINT32 reg_width, ZXIC_UINT32 addr,
-                                      ZXIC_UINT32 *pData)
+DPP_STATUS dpp_agent_channel_reg_read(DPP_DEV_T *dev, ZXIC_UINT32 reg_type,
+									  ZXIC_UINT32 reg_no, ZXIC_UINT32 reg_width,
+									  ZXIC_UINT32 addr, ZXIC_UINT32 *pData)
 {
-    DPP_STATUS ret          = 0;
-    ZXIC_UINT32 resp_len    = 0;
-    ZXIC_UINT8 *resp_buffer = NULL;
+	DPP_STATUS ret = 0;
+	ZXIC_UINT32 resp_len = 0;
+	ZXIC_UINT8 *resp_buffer = NULL;
 
-    DPP_AGENT_CHANNEL_REG_MSG_T msgcfg = {0};
+	DPP_AGENT_CHANNEL_REG_MSG_T msgcfg = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(pData);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(pData);
 
-    msgcfg.devId                       = 0;
-    msgcfg.type                        = DPP_REG_MSG;
-    msgcfg.subtype                     = reg_type;
-    msgcfg.oper                        = DPP_RD;
-    msgcfg.reg_no                      = reg_no;
-    msgcfg.addr                        = addr;
-    msgcfg.val_len                     = reg_width / 4;
+	msgcfg.devId = 0;
+	msgcfg.type = DPP_REG_MSG;
+	msgcfg.subtype = reg_type;
+	msgcfg.oper = DPP_RD;
+	msgcfg.reg_no = reg_no;
+	msgcfg.addr = addr;
+	msgcfg.val_len = reg_width / 4;
 
-    resp_len    = reg_width + 4;
-    resp_buffer = (ZXIC_UINT8 *)kmalloc(resp_len, GFP_KERNEL);
-    ZXIC_COMM_CHECK_POINT(resp_buffer);
+	resp_len = reg_width + 4;
+	resp_buffer = (ZXIC_UINT8 *)kmalloc(resp_len, GFP_KERNEL);
+	ZXIC_COMM_CHECK_POINT(resp_buffer);
 
-    memset(resp_buffer, 0, resp_len);
+	memset(resp_buffer, 0, resp_len);
 
-    ret = dpp_agent_channel_reg_sync_send(dev, &msgcfg, (ZXIC_UINT32 *)resp_buffer, resp_len);
+	ret = dpp_agent_channel_reg_sync_send(dev, &msgcfg,
+										  (ZXIC_UINT32 *)resp_buffer, resp_len);
 
-    if (DPP_OK != ret)
-    {
-        ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_reg_sync_send failed\n", __FUNCTION__);
-        kfree(resp_buffer);
-        return DPP_ERR;
-    }
+	if (DPP_OK != ret) {
+		ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_reg_sync_send failed\n",
+							  __FUNCTION__);
+		kfree(resp_buffer);
+		return DPP_ERR;
+	}
 
-    if (DPP_OK != *((ZXIC_UINT32 *)resp_buffer))
-    {
-        ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_reg_sync_send failed in buffer\n", __FUNCTION__);
-        kfree(resp_buffer);
-        return DPP_ERR;
-    }
+	if (DPP_OK != *((ZXIC_UINT32 *)resp_buffer)) {
+		ZXIC_COMM_TRACE_ERROR(
+				"%s: dpp_agent_channel_reg_sync_send failed in buffer\n",
+				__FUNCTION__);
+		kfree(resp_buffer);
+		return DPP_ERR;
+	}
 
-    memcpy(pData, resp_buffer + 4, reg_width);
+	memcpy(pData, resp_buffer + 4, reg_width);
 
-    kfree(resp_buffer);
+	kfree(resp_buffer);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-DPP_STATUS dpp_agent_channel_dtb_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_DTB_MSG_T *pMsg, ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len)
+DPP_STATUS dpp_agent_channel_dtb_sync_send(DPP_DEV_T *dev,
+										   DPP_AGENT_CHANNEL_DTB_MSG_T *pMsg,
+										   ZXIC_UINT32 *pData,
+										   ZXIC_UINT32 rep_len)
 {
-    DPP_STATUS ret = DPP_OK;
+	DPP_STATUS ret = DPP_OK;
 
-    DPP_AGENT_CHANNEL_MSG_T agentMsg = {0};
+	DPP_AGENT_CHANNEL_MSG_T agentMsg = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(pMsg);
-    ZXIC_COMM_CHECK_POINT(pData);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(pMsg);
+	ZXIC_COMM_CHECK_POINT(pData);
 
-    agentMsg.msg                     = (ZXIC_VOID *)pMsg;
-    agentMsg.msg_len                 = sizeof(DPP_AGENT_CHANNEL_DTB_MSG_T);
+	agentMsg.msg = (ZXIC_VOID *)pMsg;
+	agentMsg.msg_len = sizeof(DPP_AGENT_CHANNEL_DTB_MSG_T);
 
-    ret = dpp_agent_channel_sync_send(dev, &agentMsg, pData, rep_len);
-    if (DPP_OK != ret)
-    {
-        ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed\n", __FUNCTION__);
-        return DPP_ERR;
-    }
+	ret = dpp_agent_channel_sync_send(dev, &agentMsg, pData, rep_len);
+	if (DPP_OK != ret) {
+		ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed\n",
+							  __FUNCTION__);
+		return DPP_ERR;
+	}
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-DPP_STATUS dpp_agent_channel_dtb_queue_request(DPP_DEV_T *dev, ZXIC_CONST ZXIC_UINT8 *p_name, ZXIC_UINT32 vport_info, ZXIC_UINT32 *p_queue_id)
+DPP_STATUS dpp_agent_channel_dtb_queue_request(DPP_DEV_T *dev,
+											   ZXIC_UINT8 *p_name,
+											   ZXIC_UINT32 vport_info,
+											   ZXIC_UINT32 *p_queue_id)
 {
-    DPP_STATUS ret          = DPP_OK;
-    ZXIC_UINT32 rsp_buff[2] = {0};
-    ZXIC_UINT32 msg_result  = 0;
-    ZXIC_UINT32 queue_id    = 0;
+	DPP_STATUS ret = DPP_OK;
+	ZXIC_UINT32 rsp_buff[2] = { 0 };
+	ZXIC_UINT32 msg_result = 0;
+	ZXIC_UINT32 queue_id = 0;
 
-    DPP_AGENT_CHANNEL_DTB_MSG_T msgcfg = {0};
+	DPP_AGENT_CHANNEL_DTB_MSG_T msgcfg = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(dev);
 
-    msgcfg.devId = DEV_ID(dev);
-    msgcfg.type  = DPP_DTB_MSG;
-    msgcfg.oper  = QUEUE_REQUEST;
-    ZXIC_COMM_MEMCPY(msgcfg.name, p_name, ZXIC_COMM_STRLEN(p_name));
-    msgcfg.vport = vport_info;
+	msgcfg.devId = DEV_ID(dev);
+	msgcfg.type = DPP_DTB_MSG;
+	msgcfg.oper = QUEUE_REQUEST;
+	ZXIC_COMM_MEMCPY(msgcfg.name, p_name, ZXIC_COMM_STRLEN(p_name));
+	msgcfg.vport = vport_info;
 
-    ZXIC_COMM_TRACE_INFO("%s: msgcfg.name = %s.\n", __FUNCTION__, msgcfg.name);
+	ZXIC_COMM_TRACE_INFO("%s: msgcfg.name = %s.\n", __FUNCTION__, msgcfg.name);
 
-    ret = dpp_agent_channel_dtb_sync_send(dev, &msgcfg, rsp_buff, ZXIC_SIZEOF(rsp_buff));
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_dtb_sync_send");
+	ret = dpp_agent_channel_dtb_sync_send(dev, &msgcfg, rsp_buff,
+										  ZXIC_SIZEOF(rsp_buff));
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_dtb_sync_send");
 
-    msg_result = rsp_buff[0];
-    queue_id   = rsp_buff[1];
+	msg_result = rsp_buff[0];
+	queue_id = rsp_buff[1];
 
-    ZXIC_COMM_TRACE_INFO("%s: msg_result: %d.\n", __FUNCTION__, msg_result);
-    ZXIC_COMM_TRACE_INFO("%s: queue_id: %d.\n", __FUNCTION__, queue_id);
+	ZXIC_COMM_TRACE_INFO("%s: msg_result: %d.\n", __FUNCTION__, msg_result);
+	ZXIC_COMM_TRACE_INFO("%s: queue_id: %d.\n", __FUNCTION__, queue_id);
 
-    *p_queue_id = queue_id;
+	*p_queue_id = queue_id;
 
-    return msg_result;
+	return msg_result;
 }
 
-DPP_STATUS dpp_agent_channel_dtb_queue_release(DPP_DEV_T *dev, ZXIC_CONST ZXIC_UINT8 *p_name, ZXIC_UINT32 queue_id)
+DPP_STATUS dpp_agent_channel_dtb_queue_release(DPP_DEV_T *dev,
+											   ZXIC_UINT8 *p_name,
+											   ZXIC_UINT32 queue_id)
 {
-    DPP_STATUS ret          = DPP_OK;
-    ZXIC_UINT32 msg_result  = 0;
-    ZXIC_UINT32 rsp_buff[2] = {0};
+	DPP_STATUS ret = DPP_OK;
+	ZXIC_UINT32 msg_result = 0;
+	ZXIC_UINT32 rsp_buff[2] = { 0 };
 
-    DPP_AGENT_CHANNEL_DTB_MSG_T msgcfg = {0};
+	DPP_AGENT_CHANNEL_DTB_MSG_T msgcfg = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(dev);
 
-    msgcfg.devId    = DEV_ID(dev);
-    msgcfg.type     = DPP_DTB_MSG;
-    msgcfg.oper     = QUEUE_RELEASE;
-    msgcfg.queue_id = queue_id;
-    ZXIC_COMM_MEMCPY(msgcfg.name, p_name, ZXIC_COMM_STRLEN(p_name));
+	msgcfg.devId = DEV_ID(dev);
+	msgcfg.type = DPP_DTB_MSG;
+	msgcfg.oper = QUEUE_RELEASE;
+	msgcfg.queue_id = queue_id;
+	ZXIC_COMM_MEMCPY(msgcfg.name, p_name, ZXIC_COMM_STRLEN(p_name));
 
-    ZXIC_COMM_TRACE_INFO("%s: msgcfg.name = %s.\n", __FUNCTION__, msgcfg.name);
+	ZXIC_COMM_TRACE_INFO("%s: msgcfg.name = %s.\n", __FUNCTION__, msgcfg.name);
 
-    ret = dpp_agent_channel_dtb_sync_send(dev, &msgcfg, rsp_buff, ZXIC_SIZEOF(rsp_buff));
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_dtb_sync_send");
+	ret = dpp_agent_channel_dtb_sync_send(dev, &msgcfg, rsp_buff,
+										  ZXIC_SIZEOF(rsp_buff));
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_dtb_sync_send");
 
-    msg_result = rsp_buff[0];
-    ZXIC_COMM_TRACE_INFO("%s: msg_result: %d.\n", __FUNCTION__, msg_result);
+	msg_result = rsp_buff[0];
+	ZXIC_COMM_TRACE_INFO("%s: msg_result: %d.\n", __FUNCTION__, msg_result);
 
-    return msg_result;
+	return msg_result;
 }
 
-DPP_STATUS dpp_agent_channel_tm_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_TM_MSG_T *pMsg, ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len)
+DPP_STATUS dpp_agent_channel_tm_sync_send(DPP_DEV_T *dev,
+										  DPP_AGENT_CHANNEL_TM_MSG_T *pMsg,
+										  ZXIC_UINT32 *pData,
+										  ZXIC_UINT32 rep_len)
 {
-    DPP_STATUS ret = DPP_OK;
-    DPP_AGENT_CHANNEL_MSG_T agentMsg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(pMsg);
-    ZXIC_COMM_CHECK_POINT(pData);
-
-    agentMsg.msg                     = (ZXIC_VOID *)pMsg;
-    agentMsg.msg_len                 = sizeof(DPP_AGENT_CHANNEL_TM_MSG_T);
-
-    ret = dpp_agent_channel_sync_send(dev, &agentMsg, pData, rep_len);
-    
-    if (DPP_OK != ret)
-    {
-        ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed\n", __FUNCTION__);
-        return DPP_ERR;
-    }
-
-    // ret = *(ZXIC_UINT8 *)pData;
-    // if (DPP_OK != ret)
-    // {
-    //     ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_tm_sync_send failed in buffer\n", __FUNCTION__);
-    //     return DPP_ERR;
-    // }
-
-    return DPP_OK;
+	DPP_STATUS ret = DPP_OK;
+	DPP_AGENT_CHANNEL_MSG_T agentMsg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(pMsg);
+	ZXIC_COMM_CHECK_POINT(pData);
+
+	agentMsg.msg = (ZXIC_VOID *)pMsg;
+	agentMsg.msg_len = sizeof(DPP_AGENT_CHANNEL_TM_MSG_T);
+
+	ret = dpp_agent_channel_sync_send(dev, &agentMsg, pData, rep_len);
+
+	if (DPP_OK != ret) {
+		ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed\n",
+							  __FUNCTION__);
+		return DPP_ERR;
+	}
+
+	// ret = *(ZXIC_UINT8 *)pData;
+	// if (DPP_OK != ret)
+	// {
+	//     ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_tm_sync_send failed in buffer\n", __FUNCTION__);
+	//     return DPP_ERR;
+	// }
+
+	return DPP_OK;
 }
 
-DPP_STATUS dpp_agent_channel_tm_seid_request(DPP_DEV_T *dev, ZXIC_UINT32 port, ZXIC_UINT32 vport, ZXIC_UINT32 sche_level, ZXIC_UINT32 sche_type, ZXIC_UINT32 num, ZXIC_UINT32 *p_se_id)
+DPP_STATUS dpp_agent_channel_tm_seid_request(DPP_DEV_T *dev, ZXIC_UINT32 port,
+											 ZXIC_UINT32 vport,
+											 ZXIC_UINT32 sche_level,
+											 ZXIC_UINT32 sche_type,
+											 ZXIC_UINT32 num,
+											 ZXIC_UINT32 *p_se_id)
 {
-    DPP_STATUS ret = DPP_OK;
-    ZXIC_UINT32 resp_buffer[2] = {0};
+	DPP_STATUS ret = DPP_OK;
+	ZXIC_UINT32 resp_buffer[2] = { 0 };
 
-    DPP_AGENT_CHANNEL_TM_MSG_T msgcfg = {0};
+	DPP_AGENT_CHANNEL_TM_MSG_T msgcfg = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_se_id);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_se_id);
 
-    msgcfg.devId = 0;
-    msgcfg.type = DPP_TM_MSG;
-    msgcfg.oper = SEID_REQUEST;
-    msgcfg.port = port;
-    msgcfg.vport = vport;
-    msgcfg.sche_level = sche_level;
-    msgcfg.sche_type = sche_type;
-    msgcfg.num = num;
-    msgcfg.se_id = SCHE_REQ_VALID;
+	msgcfg.devId = 0;
+	msgcfg.type = DPP_TM_MSG;
+	msgcfg.oper = SEID_REQUEST;
+	msgcfg.port = port;
+	msgcfg.vport = vport;
+	msgcfg.sche_level = sche_level;
+	msgcfg.sche_type = sche_type;
+	msgcfg.num = num;
+	msgcfg.se_id = SCHE_REQ_VALID;
 
-    if (FLOW_SCHE != sche_type)
-    {
-        msgcfg.num = 1;
-    }
+	if (FLOW_SCHE != sche_type) {
+		msgcfg.num = 1;
+	}
 
-    ret = dpp_agent_channel_tm_sync_send(dev, &msgcfg, resp_buffer, sizeof(resp_buffer));
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_tm_sync_send");
+	ret = dpp_agent_channel_tm_sync_send(dev, &msgcfg, resp_buffer,
+										 sizeof(resp_buffer));
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_tm_sync_send");
 
-    memcpy(p_se_id, resp_buffer, sizeof(ZXIC_UINT32)*SCHE_RSP_LEN);
+	memcpy(p_se_id, resp_buffer, sizeof(ZXIC_UINT32) * SCHE_RSP_LEN);
 
-    return ret;
+	return ret;
 }
 
-DPP_STATUS dpp_agent_channel_tm_seid_release(DPP_DEV_T *dev, ZXIC_UINT32 port, ZXIC_UINT32 vport, ZXIC_UINT32 sche_level, ZXIC_UINT32 sche_type, ZXIC_UINT32 num, ZXIC_UINT32 se_id)
+DPP_STATUS dpp_agent_channel_tm_seid_release(DPP_DEV_T *dev, ZXIC_UINT32 port,
+											 ZXIC_UINT32 vport,
+											 ZXIC_UINT32 sche_level,
+											 ZXIC_UINT32 sche_type,
+											 ZXIC_UINT32 num, ZXIC_UINT32 se_id)
 {
-    DPP_STATUS ret = DPP_OK;
-    ZXIC_UINT32 resp_buffer[2] = {0};
+	DPP_STATUS ret = DPP_OK;
+	ZXIC_UINT32 resp_buffer[2] = { 0 };
 
-    DPP_AGENT_CHANNEL_TM_MSG_T msgcfg = {0};
+	DPP_AGENT_CHANNEL_TM_MSG_T msgcfg = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(dev);
 
-    msgcfg.devId = 0;
-    msgcfg.type = DPP_TM_MSG;
-    msgcfg.oper = SEID_RELEASE;
-    msgcfg.port = port;
-    msgcfg.vport = vport;
-    msgcfg.sche_level = sche_level;
-    msgcfg.sche_type = sche_type;
-    msgcfg.num = num;
-    msgcfg.se_id = se_id;
+	msgcfg.devId = 0;
+	msgcfg.type = DPP_TM_MSG;
+	msgcfg.oper = SEID_RELEASE;
+	msgcfg.port = port;
+	msgcfg.vport = vport;
+	msgcfg.sche_level = sche_level;
+	msgcfg.sche_type = sche_type;
+	msgcfg.num = num;
+	msgcfg.se_id = se_id;
 
-    if (FLOW_SCHE != sche_type)
-    {
-        msgcfg.num = 1;
-    }
+	if (FLOW_SCHE != sche_type) {
+		msgcfg.num = 1;
+	}
 
-    ret = dpp_agent_channel_tm_sync_send(dev, &msgcfg, resp_buffer, sizeof(resp_buffer));
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_tm_sync_send");
+	ret = dpp_agent_channel_tm_sync_send(dev, &msgcfg, resp_buffer,
+										 sizeof(resp_buffer));
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_tm_sync_send");
 
-    ret = *(ZXIC_UINT8*)resp_buffer;
+	ret = *(ZXIC_UINT8 *)resp_buffer;
 
-    return ret;
+	return ret;
 }
 
-DPP_STATUS dpp_agent_channel_tm_base_node_get(DPP_DEV_T *dev, ZXIC_UINT32 port, ZXIC_UINT32 vport, ZXIC_UINT32 *p_se_id)
+DPP_STATUS dpp_agent_channel_tm_base_node_get(DPP_DEV_T *dev, ZXIC_UINT32 port,
+											  ZXIC_UINT32 vport,
+											  ZXIC_UINT32 *p_se_id)
 {
-    DPP_STATUS ret = DPP_OK;
-    ZXIC_UINT32 resp_buffer[2] = {0};
+	DPP_STATUS ret = DPP_OK;
+	ZXIC_UINT32 resp_buffer[2] = { 0 };
 
-    DPP_AGENT_CHANNEL_TM_MSG_T msgcfg = {0};
+	DPP_AGENT_CHANNEL_TM_MSG_T msgcfg = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_se_id);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_se_id);
 
-    msgcfg.devId = 0;
-    msgcfg.type = DPP_TM_MSG;
-    msgcfg.oper = SEID_QUERY;
-    msgcfg.port = port;
-    msgcfg.vport = vport;
-    msgcfg.sche_level = EPID_LEVEL;
-    msgcfg.sche_type = WFQ_SCHE;
-    msgcfg.num = 1;
-    msgcfg.se_id = SCHE_REQ_VALID;
+	msgcfg.devId = 0;
+	msgcfg.type = DPP_TM_MSG;
+	msgcfg.oper = SEID_QUERY;
+	msgcfg.port = port;
+	msgcfg.vport = vport;
+	msgcfg.sche_level = EPID_LEVEL;
+	msgcfg.sche_type = WFQ_SCHE;
+	msgcfg.num = 1;
+	msgcfg.se_id = SCHE_REQ_VALID;
 
-    ret = dpp_agent_channel_tm_sync_send(dev, &msgcfg, resp_buffer, sizeof(resp_buffer));
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_tm_sync_send");
+	ret = dpp_agent_channel_tm_sync_send(dev, &msgcfg, resp_buffer,
+										 sizeof(resp_buffer));
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_tm_sync_send");
 
-    memcpy(p_se_id, resp_buffer, sizeof(ZXIC_UINT32)*SCHE_RSP_LEN);
+	memcpy(p_se_id, resp_buffer, sizeof(ZXIC_UINT32) * SCHE_RSP_LEN);
 
-    return ret;
+	return ret;
 }
 
-DPP_STATUS dpp_agent_channel_plcr_sync_send(DPP_DEV_T *dev, DPP_AGENT_CHANNEL_PLCR_MSG_T *pMsg, ZXIC_UINT32 *pData, ZXIC_UINT32 rep_len)
+DPP_STATUS dpp_agent_channel_plcr_sync_send(DPP_DEV_T *dev,
+											DPP_AGENT_CHANNEL_PLCR_MSG_T *pMsg,
+											ZXIC_UINT32 *pData,
+											ZXIC_UINT32 rep_len)
 {
-    DPP_STATUS ret = DPP_OK;
-    DPP_AGENT_CHANNEL_MSG_T agentMsg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(pMsg);
-
-    agentMsg.msg = (ZXIC_VOID *)pMsg;
-    agentMsg.msg_len = sizeof(DPP_AGENT_CHANNEL_PLCR_MSG_T);
-
-    ret = dpp_agent_channel_sync_send(dev, &agentMsg, pData, rep_len);
-    if (DPP_OK != ret)
-    {
-        ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed\n", __FUNCTION__);
-        return DPP_ERR;
-    }
-
-    // ret = *(ZXIC_UINT8*)pData;
-    // if (DPP_OK != ret)
-    // {
-    //     ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed in buffer\n", __FUNCTION__);
-    //     return DPP_ERR;
-    // }
-
-    return DPP_OK;
+	DPP_STATUS ret = DPP_OK;
+	DPP_AGENT_CHANNEL_MSG_T agentMsg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(pMsg);
+
+	agentMsg.msg = (ZXIC_VOID *)pMsg;
+	agentMsg.msg_len = sizeof(DPP_AGENT_CHANNEL_PLCR_MSG_T);
+
+	ret = dpp_agent_channel_sync_send(dev, &agentMsg, pData, rep_len);
+	if (DPP_OK != ret) {
+		ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed\n",
+							  __FUNCTION__);
+		return DPP_ERR;
+	}
+
+	// ret = *(ZXIC_UINT8*)pData;
+	// if (DPP_OK != ret)
+	// {
+	//     ZXIC_COMM_TRACE_ERROR("%s: dpp_agent_channel_sync_send failed in buffer\n", __FUNCTION__);
+	//     return DPP_ERR;
+	// }
+
+	return DPP_OK;
 }
 
-DPP_STATUS dpp_agent_channel_plcr_profileid_request(DPP_DEV_T *dev, ZXIC_UINT32 vport, ZXIC_UINT32 car_type, ZXIC_UINT32 *p_profileid)
+DPP_STATUS dpp_agent_channel_plcr_profileid_request(DPP_DEV_T *dev,
+													ZXIC_UINT32 vport,
+													ZXIC_UINT32 car_type,
+													ZXIC_UINT32 *p_profileid)
 {
-    DPP_STATUS ret = DPP_OK;
-    ZXIC_UINT32 resp_buffer[2] = {0};
+	DPP_STATUS ret = DPP_OK;
+	ZXIC_UINT32 resp_buffer[2] = { 0 };
+
+	DPP_AGENT_CHANNEL_PLCR_MSG_T msgcfg = { 0 };
 
-    DPP_AGENT_CHANNEL_PLCR_MSG_T msgcfg = {0};
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_profileid);
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_profileid);
+	msgcfg.devId = 0;
+	msgcfg.type = DPP_PLCR_MSG;
+	msgcfg.oper = PROFILEID_REQUEST;
+	msgcfg.vport = vport;
+	msgcfg.car_type = car_type;
+	msgcfg.profile_id = PROFILEID_REQ_VALID;
 
-    msgcfg.devId = 0;
-    msgcfg.type = DPP_PLCR_MSG;
-    msgcfg.oper = PROFILEID_REQUEST;
-    msgcfg.vport = vport;
-    msgcfg.car_type = car_type;
-    msgcfg.profile_id = PROFILEID_REQ_VALID;
-    
-    ret = dpp_agent_channel_plcr_sync_send(dev, &msgcfg, resp_buffer, sizeof(resp_buffer));
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_plcr_sync_send");
+	ret = dpp_agent_channel_plcr_sync_send(dev, &msgcfg, resp_buffer,
+										   sizeof(resp_buffer));
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_plcr_sync_send");
 
-    memcpy(p_profileid, resp_buffer, sizeof(ZXIC_UINT32)*SCHE_RSP_LEN);
+	memcpy(p_profileid, resp_buffer, sizeof(ZXIC_UINT32) * SCHE_RSP_LEN);
 
-    return ret;
+	return ret;
 }
 
-DPP_STATUS dpp_agent_channel_plcr_profileid_release(DPP_DEV_T *dev, ZXIC_UINT32 vport, ZXIC_UINT32 car_type, ZXIC_UINT32 profileid)
+DPP_STATUS dpp_agent_channel_plcr_profileid_release(DPP_DEV_T *dev,
+													ZXIC_UINT32 vport,
+													ZXIC_UINT32 car_type,
+													ZXIC_UINT32 profileid)
 {
-    DPP_STATUS ret = DPP_OK;
-    ZXIC_UINT32 resp_buffer[2] = {0};
+	DPP_STATUS ret = DPP_OK;
+	ZXIC_UINT32 resp_buffer[2] = { 0 };
 
-    DPP_AGENT_CHANNEL_PLCR_MSG_T msgcfg = {0};
+	DPP_AGENT_CHANNEL_PLCR_MSG_T msgcfg = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(dev);
 
-    msgcfg.devId = 0;
-    msgcfg.type = DPP_PLCR_MSG;
-    msgcfg.oper = PROFILEID_RELEASE;
-    msgcfg.vport = vport;
-    msgcfg.profile_id = profileid;
+	msgcfg.devId = 0;
+	msgcfg.type = DPP_PLCR_MSG;
+	msgcfg.oper = PROFILEID_RELEASE;
+	msgcfg.vport = vport;
+	msgcfg.profile_id = profileid;
 
-    ret = dpp_agent_channel_plcr_sync_send(dev, &msgcfg, resp_buffer, sizeof(resp_buffer));
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_plcr_sync_send");
+	ret = dpp_agent_channel_plcr_sync_send(dev, &msgcfg, resp_buffer,
+										   sizeof(resp_buffer));
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(ret, "dpp_agent_channel_plcr_sync_send");
 
-    ret = *(ZXIC_UINT8*)resp_buffer;
+	ret = *(ZXIC_UINT8 *)resp_buffer;
 
-    return ret;
+	return ret;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/cmd/include/dpp_cmd_init.h b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/include/dpp_cmd_init.h
index 1f3e6bfc4b1b4b148698b3fd993e4f725c35ce6e..2afb2e2fd5369293a3feadb918f718b826a273ec 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/cmd/include/dpp_cmd_init.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/include/dpp_cmd_init.h
@@ -1,14 +1,14 @@
-//generate function cmdlist from symbol file
+// generate function cmdlist from symbol file
 
 #ifndef DPP_CMD_INIT_H
 #define DPP_CMD_INIT_H
 
 #include "zxic_common.h"
 
-#define MSG_ID_MSG_DPP_CMD_SHELL    ((ZXIC_UINT32)(100))
+#define MSG_ID_MSG_DPP_CMD_SHELL ((ZXIC_UINT32)(100))
 typedef struct {
-    ZXIC_UINT32 msgId;
-    ZXIC_UINT8 command[256];
+	ZXIC_UINT32 msgId;
+	ZXIC_UINT8 command[256];
 } T_MSG_CMD_SHELL;
 
 ZXIC_UINT32 dpp_cmd_init(ZXIC_VOID);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/cmd/include/dpp_cmd_shell.h b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/include/dpp_cmd_shell.h
index a12705a160d42c141aa55870da0571b729036fe4..7ced706cf4709eca737dacc673761c6cfb19737c 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/cmd/include/dpp_cmd_shell.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/include/dpp_cmd_shell.h
@@ -1,4 +1,4 @@
-//generate function cmdlist from symbol file
+// generate function cmdlist from symbol file
 
 #ifndef DPP_CMD_SHELL_H
 #define DPP_CMD_SHELL_H
@@ -7,43 +7,56 @@
 #include "dpp_dtb.h"
 #include "dpp_tbl_diag.h"
 
-typedef struct
-{
-    ZXIC_CHAR *name;
-    ZXIC_CHAR *doc;
-    ZXIC_VOID *func;
+typedef struct {
+	ZXIC_CHAR *name;
+	ZXIC_CHAR *doc;
+	ZXIC_VOID *func;
 } DPP_COMMAND;
 
 ZXIC_UINT32 dpp_cmd_help(ZXIC_VOID);
 
 DPP_COMMAND dpp_commands[] = {
-    { "dpp_cmd_help", "none", dpp_cmd_help},
-    { "zxic_comm_set_print_level", "debug_level", zxic_comm_set_print_level },
-    { "zxic_comm_set_print_en", "enable", zxic_comm_set_print_en },
-    { "diag_dpp_vport_mac_add", "slot vport mac0...5", diag_dpp_vport_mac_add },
-    { "diag_dpp_vport_mac_del", "slot vport mac0...5", diag_dpp_vport_mac_del },
-    { "diag_dpp_vport_mac_prt", "slot vport", diag_dpp_vport_mac_prt },
-    { "diag_dpp_vport_mc_mac_add", "slot vport mac0...5", diag_dpp_vport_mc_mac_add },
-    { "diag_dpp_vport_mc_mac_del", "slot vport mac0...5", diag_dpp_vport_mc_mac_del },
-    { "diag_dpp_vport_mc_mac_prt", "slot vport", diag_dpp_vport_mc_mac_prt },
-    { "diag_dpp_vport_table_set", "slot vport attr value", diag_dpp_vport_table_set },
-    { "diag_dpp_vport_table_prt", "slot vport", diag_dpp_vport_table_prt },
-    { "diag_dpp_vport_panel_table_set", "slot vport panel_id attr value", diag_dpp_vport_panel_table_set },
-    { "diag_dpp_vport_panel_table_prt", "slot vport panel_id", diag_dpp_vport_panel_table_prt },
-    { "diag_dpp_vport_bc_table_set", "slot vport enable", diag_dpp_vport_bc_table_set },
-    { "diag_dpp_vport_bc_table_prt", "slot vport", diag_dpp_vport_bc_table_prt },
-    { "diag_dpp_vport_uc_promisc_table_set", "slot vport enable", diag_dpp_vport_uc_promisc_table_set },
-    { "diag_dpp_vport_uc_promisc_table_prt", "slot vport", diag_dpp_vport_uc_promisc_table_prt },
-    { "diag_dpp_vport_mc_promisc_table_set", "slot vport enable", diag_dpp_vport_mc_promisc_table_set },
-    { "diag_dpp_vport_mc_promisc_table_prt", "slot vport", diag_dpp_vport_mc_promisc_table_prt },
-    { "dpp_dtb_prt_disable", "none", dpp_dtb_prt_disable },
-    { "dpp_dtb_prt_enable", "none", dpp_dtb_prt_enable },
-    { "dpp_dtb_debug_fun_enable", "none", dpp_dtb_debug_fun_enable },
-    { "dpp_dtb_debug_fun_disable", "none", dpp_dtb_debug_fun_disable },
-    { "dpp_dtb_soft_perf_test_set", "value", dpp_dtb_soft_perf_test_set },
-    { "dpp_dtb_hardware_perf_test_set", "value", dpp_dtb_hardware_perf_test_set },
-    { "dpp_dtb_down_table_overtime_set", "times_s", dpp_dtb_down_table_overtime_set },
-    { "dpp_dtb_dump_table_overtime_set", "times_s", dpp_dtb_dump_table_overtime_set },
+	{ "dpp_cmd_help", "none", dpp_cmd_help },
+	{ "zxic_comm_set_print_level", "debug_level", zxic_comm_set_print_level },
+	{ "zxic_comm_set_print_en", "enable", zxic_comm_set_print_en },
+	{ "diag_dpp_vport_mac_add", "slot vport mac0...5", diag_dpp_vport_mac_add },
+	{ "diag_dpp_vport_mac_del", "slot vport mac0...5", diag_dpp_vport_mac_del },
+	{ "diag_dpp_vport_mac_prt", "slot vport", diag_dpp_vport_mac_prt },
+	{ "diag_dpp_vport_mc_mac_add", "slot vport mac0...5",
+	  diag_dpp_vport_mc_mac_add },
+	{ "diag_dpp_vport_mc_mac_del", "slot vport mac0...5",
+	  diag_dpp_vport_mc_mac_del },
+	{ "diag_dpp_vport_mc_mac_prt", "slot vport", diag_dpp_vport_mc_mac_prt },
+	{ "diag_dpp_vport_table_set", "slot vport attr value",
+	  diag_dpp_vport_table_set },
+	{ "diag_dpp_vport_table_prt", "slot vport", diag_dpp_vport_table_prt },
+	{ "diag_dpp_vport_panel_table_set", "slot vport panel_id attr value",
+	  diag_dpp_vport_panel_table_set },
+	{ "diag_dpp_vport_panel_table_prt", "slot vport panel_id",
+	  diag_dpp_vport_panel_table_prt },
+	{ "diag_dpp_vport_bc_table_set", "slot vport enable",
+	  diag_dpp_vport_bc_table_set },
+	{ "diag_dpp_vport_bc_table_prt", "slot vport",
+	  diag_dpp_vport_bc_table_prt },
+	{ "diag_dpp_vport_uc_promisc_table_set", "slot vport enable",
+	  diag_dpp_vport_uc_promisc_table_set },
+	{ "diag_dpp_vport_uc_promisc_table_prt", "slot vport",
+	  diag_dpp_vport_uc_promisc_table_prt },
+	{ "diag_dpp_vport_mc_promisc_table_set", "slot vport enable",
+	  diag_dpp_vport_mc_promisc_table_set },
+	{ "diag_dpp_vport_mc_promisc_table_prt", "slot vport",
+	  diag_dpp_vport_mc_promisc_table_prt },
+	{ "dpp_dtb_prt_disable", "none", dpp_dtb_prt_disable },
+	{ "dpp_dtb_prt_enable", "none", dpp_dtb_prt_enable },
+	{ "dpp_dtb_debug_fun_enable", "none", dpp_dtb_debug_fun_enable },
+	{ "dpp_dtb_debug_fun_disable", "none", dpp_dtb_debug_fun_disable },
+	{ "dpp_dtb_soft_perf_test_set", "value", dpp_dtb_soft_perf_test_set },
+	{ "dpp_dtb_hardware_perf_test_set", "value",
+	  dpp_dtb_hardware_perf_test_set },
+	{ "dpp_dtb_down_table_overtime_set", "times_s",
+	  dpp_dtb_down_table_overtime_set },
+	{ "dpp_dtb_dump_table_overtime_set", "times_s",
+	  dpp_dtb_dump_table_overtime_set },
 };
 
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/dpp_cmd_init.c b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/dpp_cmd_init.c
index 4e9ac09783779b6e5b4a899cabcaae1d64270f4f..9c92764827b1ec2f9135a9d4c382e614d8ee398b 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/dpp_cmd_init.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/dpp_cmd_init.c
@@ -2,32 +2,34 @@
 #include "dpp_netlink.h"
 #include "dpp_cmd_init.h"
 
-extern ZXIC_CHAR* dpp_cmd_trim(ZXIC_CHAR* line);
-extern ZXIC_UINT32 dpp_cmd_exec(ZXIC_CHAR* line);
+extern ZXIC_CHAR *dpp_cmd_trim(ZXIC_CHAR *line);
+extern ZXIC_UINT32 dpp_cmd_exec(ZXIC_CHAR *line);
 
-ZXIC_UINT32 dpp_cmd_msg_proc(ZXIC_VOID *msg_body, ZXIC_UINT32 msg_len, ZXIC_VOID **resp, ZXIC_UINT32 *reps_len)
+ZXIC_UINT32 dpp_cmd_msg_proc(ZXIC_VOID *msg_body, ZXIC_UINT32 msg_len,
+							 ZXIC_VOID **resp, ZXIC_UINT32 *reps_len)
 {
-    ZXIC_CHAR *line = NULL;
-    T_MSG_CMD_SHELL *msg = (T_MSG_CMD_SHELL*)(msg_body);
+	ZXIC_CHAR *line = NULL;
+	T_MSG_CMD_SHELL *msg = (T_MSG_CMD_SHELL *)(msg_body);
 
-    ZXIC_COMM_CHECK_POINT(msg);
+	ZXIC_COMM_CHECK_POINT(msg);
 
-    line = dpp_cmd_trim(msg->command);
-    ZXIC_COMM_CHECK_POINT(line);
+	line = dpp_cmd_trim(msg->command);
+	ZXIC_COMM_CHECK_POINT(line);
 
-    if (*line)
-    {
-        ZXIC_COMM_PRINT("---------------------------------------------------\n");
-        dpp_cmd_exec(line);
-        ZXIC_COMM_PRINT("---------------------------------------------------\n");
-    }
+	if (*line) {
+		ZXIC_COMM_PRINT(
+				"\n---------------------------------------------------\n");
+		dpp_cmd_exec(line);
+		ZXIC_COMM_PRINT(
+				"\n---------------------------------------------------\n");
+	}
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_cmd_init(ZXIC_VOID)
 {
-    dpp_netlink_regist_msg_proc_fun(MSG_ID_MSG_DPP_CMD_SHELL, dpp_cmd_msg_proc);
+	dpp_netlink_regist_msg_proc_fun(MSG_ID_MSG_DPP_CMD_SHELL, dpp_cmd_msg_proc);
 
-    return DPP_OK;
+	return DPP_OK;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/dpp_cmd_shell.c b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/dpp_cmd_shell.c
index f96bf02ff94f5b6d89592fa3067f6c6f1e3f2dd0..59ee6317fc36622b1be35c98c1ab8399428d9936 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/dpp_cmd_shell.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/cmd/source/dpp_cmd_shell.c
@@ -3,294 +3,294 @@
 #include "dpp_cmd_shell.h"
 
 #ifndef whitespace
-#define whitespace(c)       (((c) == ' ') || ((c) == '\t'))
+#define whitespace(c) (((c) == ' ') || ((c) == '\t'))
 #endif
 
 #define DPP_CMD_ARG_NUM_MAX (15)
 
 ZXIC_UINT32 dpp_cmd_help(ZXIC_VOID)
 {
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 list_index = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 list_index = 0;
 
-    list_index = sizeof(dpp_commands) / sizeof(dpp_commands[0]);
+	list_index = sizeof(dpp_commands) / sizeof(dpp_commands[0]);
 
-    for (i = 0; i < list_index; i++)
-    {
-        ZXIC_COMM_PRINT("%-40s | %s\n", dpp_commands[i].name, dpp_commands[i].doc);
-    }
+	for (i = 0; i < list_index; i++) {
+		ZXIC_COMM_PRINT("%-40s | %s\n", dpp_commands[i].name,
+						dpp_commands[i].doc);
+	}
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_cmd_atoi(ZXIC_CHAR* str)
+ZXIC_UINT32 dpp_cmd_atoi(ZXIC_CHAR *str)
 {
-    ZXIC_UINT32 n = 0;
-    ZXIC_SINT32 rc = 0;
-
-    if(str == NULL)
-    {
-       return 0x0;
-    }
-
-    if((str[0] == '0') && (str[1] == 'x'))
-    {
-        rc = sscanf(str, "0x%x", &n);
-    }
-    else if((str[0] == '0') && (str[1] == 'X'))
-    {
-        rc = sscanf(str, "0X%x", &n);
-    }
-    else
-    {
-        rc = sscanf(str, "%u", &n);
-    }
-
-    if (rc < 0)
-    {
-        return 0;
-    }
-
-    return n;
+	ZXIC_UINT32 rc = 0;
+
+	if (str == NULL) {
+		return 0x0;
+	}
+
+	if (str[0] == '0' && str[1] == 'x') {
+		sscanf(str, "0x%x", &rc);
+	} else if (str[0] == '0' && str[1] == 'X') {
+		sscanf(str, "0X%x", &rc);
+	} else {
+		sscanf(str, "%u", &rc);
+	}
+
+	return rc;
 }
 
-DPP_COMMAND* dpp_cmd_find(ZXIC_CHAR* name)
+DPP_COMMAND *dpp_cmd_find(ZXIC_CHAR *name)
 {
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 list_index = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 list_index = 0;
 
-    list_index = sizeof(dpp_commands) / sizeof(dpp_commands[0]);
+	list_index = sizeof(dpp_commands) / sizeof(dpp_commands[0]);
 
-    for (i = 0; i < list_index; i++)
-    {
-        if (strcmp(name, dpp_commands[i].name) == 0)
-        {
-            return (&dpp_commands[i]);
-        }
-    }
+	for (i = 0; i < list_index; i++) {
+		if (strcmp(name, dpp_commands[i].name) == 0) {
+			return ((DPP_COMMAND *)(&dpp_commands[i]));
+		}
+	}
 
-    return ((DPP_COMMAND *)NULL);
+	return ((DPP_COMMAND *)NULL);
 }
 
-ZXIC_UINT32 dpp_cmd_strtok(ZXIC_CHAR *str, ZXIC_CHAR** arg_v, ZXIC_UINT32* arg_num)
+ZXIC_UINT32 dpp_cmd_strtok(ZXIC_CHAR *str, ZXIC_CHAR **arg_v,
+						   ZXIC_UINT32 *arg_num)
 {
-    ZXIC_CHAR* p_tok = NULL;
-    ZXIC_CONST ZXIC_CHAR* delim = " ();\t";
-    ZXIC_UINT32 i = 0;
+	ZXIC_CHAR *p_tok = NULL;
+	ZXIC_CHAR *delim = " ();\t";
+	ZXIC_UINT32 i = 0;
 
-    ZXIC_COMM_CHECK_POINT(str);
-    ZXIC_COMM_CHECK_POINT(arg_v);
-    ZXIC_COMM_CHECK_POINT(arg_num);
+	ZXIC_COMM_CHECK_POINT(str);
+	ZXIC_COMM_CHECK_POINT(arg_v);
+	ZXIC_COMM_CHECK_POINT(arg_num);
 
-    ZXIC_COMM_MEMSET(arg_v, 0, DPP_CMD_ARG_NUM_MAX * sizeof(ZXIC_CHAR*));
+	ZXIC_COMM_MEMSET(arg_v, 0, DPP_CMD_ARG_NUM_MAX * sizeof(ZXIC_CHAR *));
 
-    p_tok = strsep(&str, delim);
-    ZXIC_COMM_CHECK_POINT(p_tok);
+	p_tok = strsep(&str, delim);
+	ZXIC_COMM_CHECK_POINT(p_tok);
 
-    arg_v[0] = p_tok;
+	arg_v[0] = p_tok;
 
-    i = 1;
-    while (p_tok && (i < DPP_CMD_ARG_NUM_MAX))
-    {
-        p_tok = strsep(&str, delim);
-        if (p_tok == NULL)
-        {
-            break;
-        }
-        arg_v[i++] = p_tok;
-    }
+	i = 1;
+	while (p_tok && i < DPP_CMD_ARG_NUM_MAX) {
+		p_tok = strsep(&str, delim);
+		if (p_tok == NULL) {
+			break;
+		}
+		arg_v[i++] = p_tok;
+	}
 
-    *arg_num = i;
+	*arg_num = i;
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-ZXIC_CHAR* dpp_cmd_trim(ZXIC_CHAR* line)
+ZXIC_CHAR *dpp_cmd_trim(ZXIC_CHAR *line)
 {
-    ZXIC_CHAR* s;
-    ZXIC_CHAR* t;
+	ZXIC_CHAR *s;
+	ZXIC_CHAR *t;
 
-    ZXIC_COMM_CHECK_POINT_RETURN_NULL(line);
+	ZXIC_COMM_CHECK_POINT_RETURN_NULL(line);
 
-    for (s = line; whitespace(*s); s++)
-    ;
+	for (s = line; whitespace(*s); s++)
+		;
 
-    if (*s == 0)
-    {
-        return (s);
-    }
+	if (*s == 0) {
+		return ((ZXIC_CHAR *)s);
+	}
 
-    t = s + strlen(s) - 1;
-    while ((t > s) && whitespace(*t))
-    t--;
-    *++t = '\0';
+	t = s + strlen(s) - 1;
+	while (t > s && whitespace(*t))
+		t--;
+	*++t = '\0';
 
-    return s;
+	return s;
 }
 
-ZXIC_UINT32 dpp_cmd_exec(ZXIC_CHAR* line)
+ZXIC_UINT32 dpp_cmd_exec(ZXIC_CHAR *line)
 {
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 rc = DPP_OK;
-    ZXIC_UINT32 arg_num = 0;
-    ZXIC_UINT32 len = 0;
-    ZXIC_CHAR* word = 0;
-    ZXIC_CHAR* arg_v[DPP_CMD_ARG_NUM_MAX] = {0};
-    DPP_COMMAND* command = NULL;
-
-    ZXIC_UINT32 (*func0)(ZXIC_VOID);
-    ZXIC_UINT32 (*func1)(ZXIC_UINT32);
-    ZXIC_UINT32 (*func2)(ZXIC_UINT32, ZXIC_UINT32);
-    ZXIC_UINT32 (*func3)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32);
-    ZXIC_UINT32 (*func4)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32);
-    ZXIC_UINT32 (*func5)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32);
-    ZXIC_UINT32 (*func6)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32);
-    ZXIC_UINT32 (*func7)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32);
-    ZXIC_UINT32 (*func8)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32);
-    ZXIC_UINT32 (*func9)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32);
-    ZXIC_UINT32 (*func10)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32);
-    ZXIC_UINT32 (*func11)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32,
-                          ZXIC_UINT32);
-    ZXIC_UINT32 (*func12)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32,
-                          ZXIC_UINT32, ZXIC_UINT32);
-
-    ZXIC_COMM_CHECK_POINT(line);
-
-    len = ZXIC_COMM_STRLEN(line);
-    if(0 == len)
-    {
-        ZXIC_COMM_PRINT("%s: len is 0.\n", __FUNCTION__);
-        return DPP_OK;
-    }
-
-    i = 0;
-    while(line[i % (len + 1)] && whitespace(line[i % (len + 1)]))
-    {
-        i++;
-    }
-    word = line + i;
-
-    while(line[i % (len + 1)] && !whitespace(line[i % (len + 1)]))
-    {
-        i++;
-    }
-
-    if(line[i % (len + 1)])
-    {
-        line[i++] = '\0';
-    }
-
-    command = dpp_cmd_find(word);
-    ZXIC_COMM_CHECK_POINT(command);
-    ZXIC_COMM_CHECK_POINT(command->func);
-
-    while(whitespace(line[i % (len + 1)]))
-    {
-        i++;
-    }
-
-    word = line + i;
-
-    rc = dpp_cmd_strtok(word, arg_v, &arg_num);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_cmd_strtok");
-    ZXIC_COMM_CHECK_INDEX(arg_num, 0, DPP_CMD_ARG_NUM_MAX);
-
-    switch (arg_num)
-    {
-        case 0:
-        {
-            func0 = command->func;
-            ((*(func0)) ());
-            break;
-        }
-        case 1:
-        {
-            func1 = command->func;
-            ((*(func1)) (dpp_cmd_atoi(arg_v[0])));
-            break;
-        }
-        case 2:
-        {
-            func2 = command->func;
-            ((*(func2)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1])));
-            break;
-        }
-        case 3:
-        {
-            func3 = command->func;
-            ((*(func3)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2])));
-            break;
-        }
-        case 4:
-        {
-            func4 = command->func;
-            ((*(func4)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3])));
-            break;
-        }
-        case 5:
-        {
-            func5 = command->func;
-            ((*(func5)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]), dpp_cmd_atoi(arg_v[4])));
-            break;
-        }
-        case 6:
-        {
-            func6 = command->func;
-            ((*(func6)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]), dpp_cmd_atoi(arg_v[4]),
-                                dpp_cmd_atoi(arg_v[5])));
-            break;
-        }
-        case 7:
-        {
-            func7 = command->func;
-            ((*(func7)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]), dpp_cmd_atoi(arg_v[4]),
-                                 dpp_cmd_atoi(arg_v[5]), dpp_cmd_atoi(arg_v[6])));
-            break;
-        }
-        case 8:
-        {
-            func8 = command->func;
-            ((*(func8)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]), dpp_cmd_atoi(arg_v[4]),
-                                 dpp_cmd_atoi(arg_v[5]), dpp_cmd_atoi(arg_v[6]), dpp_cmd_atoi(arg_v[7])));
-            break;
-        }
-        case 9:
-        {
-            func9 = command->func;
-            ((*(func9)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]), dpp_cmd_atoi(arg_v[4]),
-                                 dpp_cmd_atoi(arg_v[5]), dpp_cmd_atoi(arg_v[6]), dpp_cmd_atoi(arg_v[7]), dpp_cmd_atoi(arg_v[8])));
-            break;
-        }
-        case 10:
-        {
-            func10 = command->func;
-            ((*(func10)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]), dpp_cmd_atoi(arg_v[4]),
-                                 dpp_cmd_atoi(arg_v[5]), dpp_cmd_atoi(arg_v[6]), dpp_cmd_atoi(arg_v[7]), dpp_cmd_atoi(arg_v[8]), dpp_cmd_atoi(arg_v[9])));
-            break;
-        }
-        case 11:
-        {
-            func11 = command->func;
-            ((*(func11)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]), dpp_cmd_atoi(arg_v[4]),
-                                 dpp_cmd_atoi(arg_v[5]), dpp_cmd_atoi(arg_v[6]), dpp_cmd_atoi(arg_v[7]), dpp_cmd_atoi(arg_v[8]), dpp_cmd_atoi(arg_v[9]),
-                                 dpp_cmd_atoi(arg_v[10])));
-            break;
-        }
-        case 12:
-        {
-            func12 = command->func;
-            ((*(func12)) (dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]), dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]), dpp_cmd_atoi(arg_v[4]),
-                                 dpp_cmd_atoi(arg_v[5]), dpp_cmd_atoi(arg_v[6]), dpp_cmd_atoi(arg_v[7]), dpp_cmd_atoi(arg_v[8]), dpp_cmd_atoi(arg_v[9]),
-                                 dpp_cmd_atoi(arg_v[10]),dpp_cmd_atoi(arg_v[11])));
-            break;
-        }
-        default:
-        {
-            ZXIC_COMM_PRINT("%s: err [arg_num:%d] oversize.\n", __FUNCTION__, arg_num);
-            break;
-        }
-        
-    }
-  
-    return DPP_OK;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 arg_num = 0;
+	ZXIC_UINT32 len = 0;
+	ZXIC_CHAR *word = 0;
+	ZXIC_CHAR *arg_v[DPP_CMD_ARG_NUM_MAX] = { 0 };
+	DPP_COMMAND *command = NULL;
+
+	ZXIC_UINT32 (*func0)(ZXIC_VOID);
+	ZXIC_UINT32 (*func1)(ZXIC_UINT32);
+	ZXIC_UINT32 (*func2)(ZXIC_UINT32, ZXIC_UINT32);
+	ZXIC_UINT32 (*func3)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32);
+	ZXIC_UINT32 (*func4)(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32);
+	ZXIC_UINT32(*func5)
+	(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32);
+	ZXIC_UINT32(*func6)
+	(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32,
+	 ZXIC_UINT32);
+	ZXIC_UINT32(*func7)
+	(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32,
+	 ZXIC_UINT32, ZXIC_UINT32);
+	ZXIC_UINT32(*func8)
+	(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32,
+	 ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32);
+	ZXIC_UINT32(*func9)
+	(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32,
+	 ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32);
+	ZXIC_UINT32(*func10)
+	(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32,
+	 ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32);
+	ZXIC_UINT32(*func11)
+	(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32,
+	 ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32,
+	 ZXIC_UINT32);
+	ZXIC_UINT32(*func12)
+	(ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32,
+	 ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32, ZXIC_UINT32,
+	 ZXIC_UINT32, ZXIC_UINT32);
+
+	ZXIC_COMM_CHECK_POINT(line);
+
+	len = ZXIC_COMM_STRLEN(line);
+	if (0 == len) {
+		ZXIC_COMM_PRINT("%s: len is 0.\n", __FUNCTION__);
+		return DPP_OK;
+	}
+
+	i = 0;
+	while (line[i % (len + 1)] && whitespace(line[i % (len + 1)])) {
+		i++;
+	}
+	word = line + i;
+
+	while (line[i % (len + 1)] && !whitespace(line[i % (len + 1)])) {
+		i++;
+	}
+
+	if (line[i % (len + 1)]) {
+		line[i++] = '\0';
+	}
+
+	command = dpp_cmd_find(word);
+	ZXIC_COMM_CHECK_POINT(command);
+	ZXIC_COMM_CHECK_POINT(command->func);
+
+	while (whitespace(line[i % (len + 1)])) {
+		i++;
+	}
+
+	word = line + i;
+
+	rc = dpp_cmd_strtok(word, arg_v, &arg_num);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_cmd_strtok");
+	ZXIC_COMM_CHECK_INDEX(arg_num, 0, DPP_CMD_ARG_NUM_MAX);
+
+	switch (arg_num) {
+	case 0: {
+		func0 = command->func;
+		((*(func0))());
+		break;
+	}
+	case 1: {
+		func1 = command->func;
+		((*(func1))(dpp_cmd_atoi(arg_v[0])));
+		break;
+	}
+	case 2: {
+		func2 = command->func;
+		((*(func2))(dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1])));
+		break;
+	}
+	case 3: {
+		func3 = command->func;
+		((*(func3))(dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]),
+					dpp_cmd_atoi(arg_v[2])));
+		break;
+	}
+	case 4: {
+		func4 = command->func;
+		((*(func4))(dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]),
+					dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3])));
+		break;
+	}
+	case 5: {
+		func5 = command->func;
+		((*(func5))(dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]),
+					dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]),
+					dpp_cmd_atoi(arg_v[4])));
+		break;
+	}
+	case 6: {
+		func6 = command->func;
+		((*(func6))(dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]),
+					dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]),
+					dpp_cmd_atoi(arg_v[4]), dpp_cmd_atoi(arg_v[5])));
+		break;
+	}
+	case 7: {
+		func7 = command->func;
+		((*(func7))(dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]),
+					dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]),
+					dpp_cmd_atoi(arg_v[4]), dpp_cmd_atoi(arg_v[5]),
+					dpp_cmd_atoi(arg_v[6])));
+		break;
+	}
+	case 8: {
+		func8 = command->func;
+		((*(func8))(dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]),
+					dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]),
+					dpp_cmd_atoi(arg_v[4]), dpp_cmd_atoi(arg_v[5]),
+					dpp_cmd_atoi(arg_v[6]), dpp_cmd_atoi(arg_v[7])));
+		break;
+	}
+	case 9: {
+		func9 = command->func;
+		((*(func9))(dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]),
+					dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]),
+					dpp_cmd_atoi(arg_v[4]), dpp_cmd_atoi(arg_v[5]),
+					dpp_cmd_atoi(arg_v[6]), dpp_cmd_atoi(arg_v[7]),
+					dpp_cmd_atoi(arg_v[8])));
+		break;
+	}
+	case 10: {
+		func10 = command->func;
+		((*(func10))(dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]),
+					 dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]),
+					 dpp_cmd_atoi(arg_v[4]), dpp_cmd_atoi(arg_v[5]),
+					 dpp_cmd_atoi(arg_v[6]), dpp_cmd_atoi(arg_v[7]),
+					 dpp_cmd_atoi(arg_v[8]), dpp_cmd_atoi(arg_v[9])));
+		break;
+	}
+	case 11: {
+		func11 = command->func;
+		((*(func11))(dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]),
+					 dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]),
+					 dpp_cmd_atoi(arg_v[4]), dpp_cmd_atoi(arg_v[5]),
+					 dpp_cmd_atoi(arg_v[6]), dpp_cmd_atoi(arg_v[7]),
+					 dpp_cmd_atoi(arg_v[8]), dpp_cmd_atoi(arg_v[9]),
+					 dpp_cmd_atoi(arg_v[10])));
+		break;
+	}
+	case 12: {
+		func12 = command->func;
+		((*(func12))(dpp_cmd_atoi(arg_v[0]), dpp_cmd_atoi(arg_v[1]),
+					 dpp_cmd_atoi(arg_v[2]), dpp_cmd_atoi(arg_v[3]),
+					 dpp_cmd_atoi(arg_v[4]), dpp_cmd_atoi(arg_v[5]),
+					 dpp_cmd_atoi(arg_v[6]), dpp_cmd_atoi(arg_v[7]),
+					 dpp_cmd_atoi(arg_v[8]), dpp_cmd_atoi(arg_v[9]),
+					 dpp_cmd_atoi(arg_v[10]), dpp_cmd_atoi(arg_v[11])));
+		break;
+	}
+	default: {
+		ZXIC_COMM_PRINT("%s: err [arg_num:%d] oversize.\n", __FUNCTION__,
+						arg_num);
+		break;
+	}
+	}
+
+	return DPP_OK;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_avl_tree.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_avl_tree.h
index a4c829cf8d6e24bfa3712bc070e37a7fdcc7e2fa..11572c8497338fcf55c66b767904d50c0962d94e 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_avl_tree.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_avl_tree.h
@@ -1,97 +1,88 @@
-/*********************************************************************
- * 版权所有 (C)2012, 深圳市中兴通讯股份有限公司。
- *
- * 文件名称：zxic_avl_tree.h
- * 文件标识：
- * 内容摘要：//  本文件从pfe_index 移植过来
- * 其它说明：// 其它内容的说明
- * 当前版本：
- * 作    者：
- * 完成日期：
- *
- * 修    改: 蒋文明10124041 2012.04.26移植到NSE项目
- ********************************************************************/
-#ifndef __ZXIC_COMM_AVL_TREE_H__
-#define __ZXIC_COMM_AVL_TREE_H__
-
-
-/* Since the trees are balanced, their heignse will never be large. */
-#define avl_maxheight    41 /* why this? a small exercise */
-#define heightoftree(tree)  ((tree) == NULL ? 0 : (tree)->avl_height)
-
-struct _ZXIC_AVL_CFG;
-struct _ZXIC_AVL_NODE;
-
-#define ZXIC_LIST_ENTRY(ptr, type, member) \
-    ((type *)((ZXIC_UINT8 *)(ptr)-(((unsigned long)(&((type *)64)->member)) - 64)))
-
-#define ZXIC_GET_AVL_KEY_ADDR(p_avl_cfg,key_index) \
-                  ((p_avl_cfg->p_key_base)+(p_avl_cfg->key_len*(key_index)));
-
-typedef ZXIC_SINT32 (*ZXIC_KEY_CMP_FUNC)(void *p_new_key, void *p_old_key, ZXIC_UINT32 key_len);
-
-typedef struct _ZXIC_AVL_NODE
-{
-    void                   *p_key;
-    //void                   *p_owner;      /*the owner of this node*/
-    ZXIC_UINT32                  result;       /*该节点的索引*/
-    ZXIC_SINT32                 avl_height;
-    struct _ZXIC_AVL_NODE   *p_avl_left;
-    struct _ZXIC_AVL_NODE   *p_avl_right;
-    D_NODE                  avl_node_list;/*the data is owner*/
-} ZXIC_AVL_NODE;
-
-typedef struct _ZXIC_AVL_CFG
-{
-
-    ZXIC_AVL_NODE         *p_root;
-    ZXIC_UINT32                avl_node_num;          /*avl 中已使用节点的数目*/
-    D_HEAD                avl_node_list_head;    /*avl 线索化节点的头节点*/
-    ZXIC_UINT32                key_len;
-    ZXIC_UINT32                item_num;
-    ZXIC_KEY_CMP_FUNC      avl_cmp_func;
-    ZXIC_UINT8                 *p_key_base;
-    ZXIC_AVL_NODE         *p_avl_node_base;
-    ZXIC_LISTSTACK_MANGER *p_avl_node_liststack;
-
-    ZXIC_UINT32                is_dynamic;            /*是否支持avl 的节点动态生成，1:支持;0:不支持*/    
-    ZXIC_UINT32                is_init;
-
-} ZXIC_AVL_CFG;
-
-
-
-ZXIC_RTN32 zxic_comm_avl_init(ZXIC_AVL_CFG*        p_avl_cfg, /* avl配置*/
-                              ZXIC_UINT32          item_num,    /* 插入键值的数目,如果为0表示动态申请节点*/
-                              ZXIC_UINT32          key_length,  /* 插入键值的长度，以字节为单位*/
-                              ZXIC_KEY_CMP_FUNC    avl_cmp_func);   /* 键值比较函数,使用默认比较函数可以为NULL,
-                                                                       如果按整型比较，需要用户提供比较函数*/
-ZXIC_RTN32 zxic_comm_avl_insert(ZXIC_AVL_CFG*   p_avl_cfg,
-                                void*           p_new_key,
-                                ZXIC_UINT32*    p_index);
-
-ZXIC_RTN32 zxic_comm_avl_remove(ZXIC_AVL_CFG*  p_avl_cfg,
-                                void*          p_delete_key,
-                                void*          p_out);
-
-ZXIC_RTN32 zxic_comm_avl_find(ZXIC_AVL_CFG*   p_avl_cfg,
-                              void*           p_find_key,
-                              void*           p_out);
-
-ZXIC_RTN32 zxic_comm_avl_destroy(ZXIC_AVL_CFG*  p_avl_cfg );
-
-
-
-
-ZXIC_UINT32 ic_comm_avl_get_node_num(ZXIC_AVL_CFG* p_avl_cfg);
-ZXIC_UINT32 ic_comm_avl_is_none(ZXIC_AVL_CFG* p_avl_cfg);
-ZXIC_RTN32 ic_comm_avl_get_1st_key(ZXIC_AVL_CFG*  p_avl_cfg, void *p_key_out);
-ZXIC_RTN32 ic_comm_avl_get_last_key(ZXIC_AVL_CFG*  p_avl_cfg, void *p_key_out);
-ZXIC_RTN32 ic_comm_avl_get_1st_node(ZXIC_AVL_CFG*  p_avl_cfg, ZXIC_AVL_NODE** p_node_out);
-ZXIC_RTN32 ic_comm_avl_get_last_node(ZXIC_AVL_CFG*  p_avl_cfg, ZXIC_AVL_NODE** p_node_out);
-
-ZXIC_RTN32 zxic_comm_avl_show_info(ZXIC_AVL_CFG*  p_avl_cfg);
-
-#endif/*__ZXIC_AVL_TREE_H__*/
-
-
+/*********************************************************************
+ * 版权所有 (C)2012, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：zxic_avl_tree.h
+ * 文件标识：
+ * 内容摘要：//  本文件从pfe_index 移植过来
+ * 其它说明：// 其它内容的说明
+ * 当前版本：
+ * 作    者：
+ * 完成日期：
+ *
+ * 修    改: 蒋文明10124041 2012.04.26移植到NSE项目
+ ********************************************************************/
+#ifndef __ZXIC_COMM_AVL_TREE_H__
+#define __ZXIC_COMM_AVL_TREE_H__
+
+/* Since the trees are balanced, their heignse will never be large. */
+#define avl_maxheight 41 /* why this? a small exercise */
+#define heightoftree(tree) ((tree) == NULL ? 0 : (tree)->avl_height)
+
+struct _ZXIC_AVL_CFG;
+struct _ZXIC_AVL_NODE;
+
+#define ZXIC_LIST_ENTRY(ptr, type, member) \
+	((type *)((ZXIC_UINT8 *)(ptr) -        \
+			  (((unsigned long)(&((type *)64)->member)) - 64)))
+
+#define ZXIC_GET_AVL_KEY_ADDR(p_avl_cfg, key_index) \
+	((p_avl_cfg->p_key_base) + (p_avl_cfg->key_len * (key_index)));
+
+typedef ZXIC_SINT32 (*ZXIC_KEY_CMP_FUNC)(void *p_new_key, void *p_old_key,
+										 ZXIC_UINT32 key_len);
+
+typedef struct _ZXIC_AVL_NODE {
+	void *p_key;
+	// void                   *p_owner;      /*the owner of this node*/
+	ZXIC_UINT32 result; /*该节点的索引*/
+	ZXIC_SINT32 avl_height;
+	struct _ZXIC_AVL_NODE *p_avl_left;
+	struct _ZXIC_AVL_NODE *p_avl_right;
+	D_NODE avl_node_list; /*the data is owner*/
+} ZXIC_AVL_NODE;
+
+typedef struct _ZXIC_AVL_CFG {
+	ZXIC_AVL_NODE *p_root;
+	ZXIC_UINT32 avl_node_num; /*avl 中已使用节点的数目*/
+	D_HEAD avl_node_list_head; /*avl 线索化节点的头节点*/
+	ZXIC_UINT32 key_len;
+	ZXIC_UINT32 item_num;
+	ZXIC_KEY_CMP_FUNC avl_cmp_func;
+	ZXIC_UINT8 *p_key_base;
+	ZXIC_AVL_NODE *p_avl_node_base;
+	ZXIC_LISTSTACK_MANGER *p_avl_node_liststack;
+
+	ZXIC_UINT32 is_dynamic; /*是否支持avl 的节点动态生成，1:支持;0:不支持*/
+	ZXIC_UINT32 is_init;
+
+} ZXIC_AVL_CFG;
+
+ZXIC_RTN32 zxic_comm_avl_init(
+		ZXIC_AVL_CFG * p_avl_cfg, /* avl配置*/
+		ZXIC_UINT32 item_num, /* 插入键值的数目,如果为0表示动态申请节点*/
+		ZXIC_UINT32 key_length, /* 插入键值的长度，以字节为单位*/
+		ZXIC_KEY_CMP_FUNC
+		avl_cmp_func); /* 键值比较函数,使用默认比较函数可以为NULL,如果按整型比较，需要用户提供比较函数*/
+ZXIC_RTN32 zxic_comm_avl_insert(ZXIC_AVL_CFG *p_avl_cfg, void *p_new_key,
+								ZXIC_UINT32 *p_index);
+
+ZXIC_RTN32 zxic_comm_avl_remove(ZXIC_AVL_CFG *p_avl_cfg, void *p_delete_key,
+								void *p_out);
+
+ZXIC_RTN32 zxic_comm_avl_find(ZXIC_AVL_CFG *p_avl_cfg, void *p_find_key,
+							  void *p_out);
+
+ZXIC_RTN32 zxic_comm_avl_destroy(ZXIC_AVL_CFG *p_avl_cfg);
+
+ZXIC_UINT32 ic_comm_avl_get_node_num(ZXIC_AVL_CFG *p_avl_cfg);
+ZXIC_UINT32 ic_comm_avl_is_none(ZXIC_AVL_CFG *p_avl_cfg);
+ZXIC_RTN32 ic_comm_avl_get_1st_key(ZXIC_AVL_CFG *p_avl_cfg, void *p_key_out);
+ZXIC_RTN32 ic_comm_avl_get_last_key(ZXIC_AVL_CFG *p_avl_cfg, void *p_key_out);
+ZXIC_RTN32 ic_comm_avl_get_1st_node(ZXIC_AVL_CFG *p_avl_cfg,
+									ZXIC_AVL_NODE **p_node_out);
+ZXIC_RTN32 ic_comm_avl_get_last_node(ZXIC_AVL_CFG *p_avl_cfg,
+									 ZXIC_AVL_NODE **p_node_out);
+
+ZXIC_RTN32 zxic_comm_avl_show_info(ZXIC_AVL_CFG *p_avl_cfg);
+
+#endif /*__ZXIC_AVL_TREE_H__*/
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_double_link.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_double_link.h
index 2b6afbdd6b98a214e43cb85db2593f192d79b5e4..c95272bf8afa1c1bea567db3e818722fe5274607 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_double_link.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_double_link.h
@@ -1,109 +1,108 @@
-/*****************************************************************************
- * 版权所有 (C)2008-2010, 深圳市中兴通讯股份有限公司。
- * 
- * 文件名称：    zxic_comm_double_link.h
- * 文件标识：    
- * 内容摘要：    双链表实现
- * 其它说明： 
- * 当前版本：    V1.00.10
- * 作           者：   
- * 完成日期：    2012年2月14日
- * 当前责任人-1：ChenWei188471
- * 当前责任人-2：
- * 历史责任人-3: 
- *
- * 修改记录：   
- * 修改日期：   版 本 号   修 改 人     修改内容 
- 1    20120214               V1.00.10       ChenWei188471  创建
- 2      
- *****************************************************************************/
-
-#ifndef _ZXIC_COMM_DOUBLE_LINK_H
-#define _ZXIC_COMM_DOUBLE_LINK_H
-#define TEST_NUMBER (255)
-
-
-
-
-/**************************************************************************
- *                        double_link api                                  *
- **************************************************************************/
-typedef struct _d_node
-{
-    void *data;
-    struct _d_node *prev;
-    struct _d_node *next;
-}D_NODE;
-
-typedef struct _d_head
-{
-    ZXIC_UINT32  used;
-    ZXIC_UINT32  maxnum;
-    D_NODE *p_next;
-    D_NODE *p_prev;
-}D_HEAD;
-
-typedef ZXIC_SINT32 (*CMP_FUNC)(D_NODE* data1,D_NODE* data2,void* );
-
-typedef ZXIC_RTN32 (*fun_free)(void *);
-
-ZXIC_RTN32  zxic_comm_double_link_insert_1st (D_NODE *newnode,  D_HEAD *head);
-ZXIC_RTN32  zxic_comm_double_link_insert_aft (D_NODE *newnode,  D_NODE *oldnode,D_HEAD*head);
-ZXIC_RTN32  zxic_comm_double_link_insert_pre (D_NODE *newnode,  D_NODE *oldnode,D_HEAD*head);
-ZXIC_RTN32  zxic_comm_double_link_insert_last(D_NODE *newnode,  D_HEAD *head);
-ZXIC_RTN32  zxic_comm_double_link_merge_list (D_HEAD *d_list,   D_HEAD *s_list);
-
-ZXIC_RTN32  zxic_comm_double_link_insert_sort(D_NODE *newnode,  D_HEAD *head,  CMP_FUNC fuc,void*);
-
-ZXIC_RTN32  zxic_comm_double_link_search     (D_NODE *data,     D_HEAD *head);
-ZXIC_RTN32  zxic_comm_double_link_del        (D_NODE *data,     D_HEAD *head);
-ZXIC_RTN32  zxic_comm_double_link_init       (ZXIC_UINT32 elmemtnum, D_HEAD *head);
-ZXIC_RTN32  zxic_comm_double_link_insert_merge(D_NODE *p_newnode,D_HEAD *p_head,ZXIC_UINT32 is_head);
-
-/*fun指向的是释放dnode指向的空间，如果没有，可以传NULL*/
-ZXIC_RTN32  zxic_comm_dlink_release(D_HEAD *p_head,fun_free fun);
-ZXIC_SINT32 zxic_comm_double_link_default_cmp_fuc(D_NODE* p_data1,D_NODE* p_data2,void*);
-
-ZXIC_RTN32 zxic_comm_double_link_del_pos(D_HEAD *p_head,void* cmp_data,fun_free fun);
-ZXIC_RTN32 zxic_comm_double_link_insert_cmp(D_HEAD *p_head, void* cmp_data, ZXIC_UINT32 *is_same);
-
-#define INIT_D_NODE(ptr,pdata) \
-    do{\
-        (ptr)->data = pdata;\
-        (ptr)->prev = NULL;\
-        (ptr)->next = NULL;\
-    }while(0)
-
-
-/*add by lius
-将0转 换成(TYPE*)，结构以内存空间首地址0作为起始地址，则成员地址为偏移地址；*/
-#define MEM_OFF(type,member) \
-    (ZXIC_COMM_PTR_TO_VAL(&(((type*)0)->member)))
-
-/*根据当前双链表的指针，找到本节点的指针*/
-#define STRUCT_ENTRY_POINT(ptr, type, member) \
-    ((type *)(ZXIC_COMM_PTR_TO_VAL(ptr)-MEM_OFF(type,member)))
-
-/* 不依据0，找结构体首地址 */
-#define MEM_OFF_NOT_NULL(type,member) \
-    (ZXIC_COMM_PTR_TO_VAL(&(((type*)4)->member)) - ZXIC_COMM_PTR_TO_VAL(((type*)4)))
-
-/* 为了消除原STRUCT_ENTRY_POINT中“直接解引用 NULL”的coverity */
-#define GET_STRUCT_ENTRY_POINT(ptr, type, member) \
-    ((type *)(ZXIC_COMM_PTR_TO_VAL(ptr)-MEM_OFF_NOT_NULL(type,member)))
-
-#define DLINK_IS_FULL(p_dlink) \
-    ((p_dlink)->used == (p_dlink)->maxnum)
-
-
-ZXIC_RTN32 zxic_comm_double_link_sort   (D_HEAD *p_head,  CMP_FUNC cmp_fuc);
-ZXIC_RTN32 zxic_comm_double_link_swap   (D_NODE *p_pre,   D_NODE *p_next);
-ZXIC_RTN32 zxic_comm_double_link_test   (ZXIC_VOID );
-ZXIC_RTN32 zxic_comm_double_link_print  (D_HEAD *p_head);
-ZXIC_RTN32 zxic_comm_double_link_del_by_data(D_HEAD *p_head,ZXIC_VOID* cmp_data,fun_free fun);
-ZXIC_RTN32 zxic_comm_double_link_del_by_info(D_HEAD *p_head, void* cmp_data, CMP_FUNC cmp_fuc, ZXIC_UINT32 *p_deled_num);
-
-
-
-#endif 
-
+/*****************************************************************************
+ * 版权所有 (C)2008-2010, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：    zxic_comm_double_link.h
+ * 文件标识：
+ * 内容摘要：    双链表实现
+ * 其它说明：
+ * 当前版本：    V1.00.10
+ * 作           者：
+ * 完成日期：    2012年2月14日
+ * 当前责任人-1：ChenWei188471
+ * 当前责任人-2：
+ * 历史责任人-3:
+ *
+ * 修改记录：
+ * 修改日期：   版 本 号   修 改 人     修改内容
+ 1    20120214               V1.00.10       ChenWei188471  创建
+ 2
+ *****************************************************************************/
+
+#ifndef _ZXIC_COMM_DOUBLE_LINK_H
+#define _ZXIC_COMM_DOUBLE_LINK_H
+#define TEST_NUMBER (255)
+
+/**************************************************************************
+ *                        double_link api                                  *
+ **************************************************************************/
+typedef struct _d_node {
+	void *data;
+	struct _d_node *prev;
+	struct _d_node *next;
+} D_NODE;
+
+typedef struct _d_head {
+	ZXIC_UINT32 used;
+	ZXIC_UINT32 maxnum;
+	D_NODE *p_next;
+	D_NODE *p_prev;
+} D_HEAD;
+
+typedef ZXIC_SINT32 (*CMP_FUNC)(D_NODE *data1, D_NODE *data2, void *);
+
+typedef ZXIC_RTN32 (*fun_free)(void *);
+
+ZXIC_RTN32 zxic_comm_double_link_insert_1st(D_NODE *newnode, D_HEAD *head);
+ZXIC_RTN32 zxic_comm_double_link_insert_aft(D_NODE *newnode, D_NODE *oldnode,
+											D_HEAD *head);
+ZXIC_RTN32 zxic_comm_double_link_insert_pre(D_NODE *newnode, D_NODE *oldnode,
+											D_HEAD *head);
+ZXIC_RTN32 zxic_comm_double_link_insert_last(D_NODE *newnode, D_HEAD *head);
+ZXIC_RTN32 zxic_comm_double_link_merge_list(D_HEAD *d_list, D_HEAD *s_list);
+
+ZXIC_RTN32 zxic_comm_double_link_insert_sort(D_NODE *newnode, D_HEAD *head,
+											 CMP_FUNC fuc, void *);
+
+ZXIC_RTN32 zxic_comm_double_link_search(D_NODE *data, D_HEAD *head);
+ZXIC_RTN32 zxic_comm_double_link_del(D_NODE *data, D_HEAD *head);
+ZXIC_RTN32 zxic_comm_double_link_init(ZXIC_UINT32 elmemtnum, D_HEAD *head);
+ZXIC_RTN32 zxic_comm_double_link_insert_merge(D_NODE *p_newnode, D_HEAD *p_head,
+											  ZXIC_UINT32 is_head);
+
+/*fun指向的是释放dnode指向的空间，如果没有，可以传NULL*/
+ZXIC_RTN32 zxic_comm_dlink_release(D_HEAD *p_head, fun_free fun);
+ZXIC_SINT32 zxic_comm_double_link_default_cmp_fuc(D_NODE *p_data1,
+												  D_NODE *p_data2, void *);
+
+ZXIC_RTN32 zxic_comm_double_link_del_pos(D_HEAD *p_head, void *cmp_data,
+										 fun_free fun);
+ZXIC_RTN32 zxic_comm_double_link_insert_cmp(D_HEAD *p_head, void *cmp_data,
+											ZXIC_UINT32 *is_same);
+
+#define INIT_D_NODE(ptr, pdata) \
+	do {                        \
+		(ptr)->data = pdata;    \
+		(ptr)->prev = NULL;     \
+		(ptr)->next = NULL;     \
+	} while (0)
+
+/*add by lius
+将0转 换成(TYPE*)，结构以内存空间首地址0作为起始地址，则成员地址为偏移地址；*/
+#define MEM_OFF(type, member) (ZXIC_COMM_PTR_TO_VAL(&(((type *)0)->member)))
+
+/*根据当前双链表的指针，找到本节点的指针*/
+#define STRUCT_ENTRY_POINT(ptr, type, member) \
+	((type *)(ZXIC_COMM_PTR_TO_VAL(ptr) - MEM_OFF(type, member)))
+
+/* 不依据0，找结构体首地址 */
+#define MEM_OFF_NOT_NULL(type, member)              \
+	(ZXIC_COMM_PTR_TO_VAL(&(((type *)4)->member)) - \
+	 ZXIC_COMM_PTR_TO_VAL(((type *)4)))
+
+/* 为了消除原STRUCT_ENTRY_POINT中“直接解引用 NULL”的coverity */
+#define GET_STRUCT_ENTRY_POINT(ptr, type, member) \
+	((type *)(ZXIC_COMM_PTR_TO_VAL(ptr) - MEM_OFF_NOT_NULL(type, member)))
+
+#define DLINK_IS_FULL(p_dlink) ((p_dlink)->used == (p_dlink)->maxnum)
+
+ZXIC_RTN32 zxic_comm_double_link_sort(D_HEAD *p_head, CMP_FUNC cmp_fuc);
+ZXIC_RTN32 zxic_comm_double_link_swap(D_NODE *p_pre, D_NODE *p_next);
+ZXIC_RTN32 zxic_comm_double_link_test(ZXIC_VOID);
+ZXIC_RTN32 zxic_comm_double_link_print(D_HEAD *p_head);
+ZXIC_RTN32 zxic_comm_double_link_del_by_data(D_HEAD *p_head,
+											 ZXIC_VOID *cmp_data, fun_free fun);
+ZXIC_RTN32 zxic_comm_double_link_del_by_info(D_HEAD *p_head, void *cmp_data,
+											 CMP_FUNC cmp_fuc,
+											 ZXIC_UINT32 *p_deled_num);
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_doublelink_index.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_doublelink_index.h
index c966195c72a702ca1a94304d07d05363fa5481f1..4f7e52efe7743896809397f961c2eaae74f7e71e 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_doublelink_index.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_doublelink_index.h
@@ -1,166 +1,147 @@
-/*****************************************************************************
- * 版权所有 (C)2008-2010, 深圳市中兴通讯股份有限公司。
- * 
- * 文件名称：zxic_doublelink_index.h
- * 文件标识：
- * 内容摘要：zxic_doublelink_index.c 的头文件， 这里定义了.c文件需要用到的数据结构，
-             并且申明了提供外部模块调用的接口函数
- * 其它说明： 其它内容的说明
- * 当前版本：
- * 作    者：HuangHe(170389)   Z T E 中兴
- * 完成日期：2009-02-16
- * 当前责任人-1：HuangHe   Z T E 中兴
- * 当前责任人-2： 
- * 历史责任人-3: 
- * 
- * 修改记录： 
- * 修改日期：   版 本 号   修 改 人     修改内容 
- 1 yyyymmdd       V*.*     姓名工号 
- 2  
-  *****************************************************************************/
-#ifndef __ZXIC_COMM_DOUBLELINK_INDEX_H__
-#define __ZXIC_COMM_DOUBLELINK_INDEX_H__
-
-/**************************  include head files  *****************************/
-
-/**************************  type define  *****************************/
-#define DOUBLELINK_CHECKSUM                   ((ZXIC_UINT32)(0xAABBBAAB))   
-
-
-/**************************  const variables  **************************/
-#define DOUBLELINK_INVALID_PREVIOUS                     (0x0)
-#define DOUBLELINK_INVALID_NEXT                         (0x0)
-#define DOUBLELINK_USED_FLAG                            ((ZXIC_UINT32)(0xffffffff))
-#define DOUBLELINK_LASTEST_ELEMENT                      ((ZXIC_UINT32)(0x0ffffffe))
-
-/**************************************************************************
- *                        double_link_index api                           *
- **************************************************************************/
-
-/**
- * NAME: DLINK_NODE
- *
- * DESCRIPTION: Structure Node the information of the doublelink.
- **/
-typedef struct
-{
-    ZXIC_UINT32 dw_next_node; /*后一个节点*/
-    ZXIC_UINT32 dw_pre_node;  /*前一个节点*/
-    ZXIC_UINT32 dw_self_node; /*当前一个节点*/
-    
-}DLINK_NODE;
-
-/**
- * NAME: FTMCOMM_DOUBLELINK_MANGER
- *
- * DESCRIPTION: Structure containing the information required by the
- * implementation of the doublelink.
-**/
- 
-typedef struct _FtmComm_DoubleLink_Manager
-{
-    /*
-     * p_array is a pointer to the array of elements used to track which
-     * indexes have been allocated.
-     */
-    DLINK_NODE *p_array;
-
-    /*
-     * numElements is the number of indexes managed by this instance of the
-     * index_pool.
-     */
-    ZXIC_UINT32   capacity;
-
-    /*
-     * currFreeElement stores a free element for where to alloc next free element.
-     * This helps prevent looping over a large sections of the array each time
-     * a new index is allocated.
-     */
-    ZXIC_UINT32   free_num;
-
-    ZXIC_UINT32   used_num;
-
-    ZXIC_UINT32   first_used;
-
-    ZXIC_UINT32   last_used;
-
-    ZXIC_UINT32   first_free;
-
-    ZXIC_UINT32   last_free;
-    /*
-     * offset is an adjustment value, allowing the caller to prevent certain
-     * indexes from being allocated.  This value is only meaningful to the
-     * client, and does not affect how the indexes are managed within the
-     * doublelink.
-     */
-    ZXIC_UINT32   offset;
-
-    ZXIC_UINT32   check_sum; /*用来检查传入的地址是否是双链表管理结构地址*/
-
-}ZXIC_DOUBLELINK_MANGER;
-
-
-ZXIC_RTN32 zxic_comm_dlink_manage_create(ZXIC_UINT32                     dw_element_num,       
-                                   ZXIC_UINT32                     dw_offset, 
-                                   ZXIC_DOUBLELINK_MANGER **p_dlink);
-
-
-ZXIC_RTN32 zxic_comm_dlink_alloc        (ZXIC_DOUBLELINK_MANGER  *p_dlink, 
-                                   ZXIC_UINT32                     *index);
-
-
-ZXIC_RTN32 zxic_comm_dlink_free         (ZXIC_DOUBLELINK_MANGER *p_dlink,
-                                   ZXIC_UINT32                     index);
-
-
-ZXIC_RTN32 zxic_comm_dlink_get_next     (ZXIC_DOUBLELINK_MANGER *p_dlink,
-                                   ZXIC_UINT32                     dw_index,
-                                   ZXIC_UINT32                    *p_next_index);
-
-
-ZXIC_RTN32 zxic_comm_dlink_manage_clear (ZXIC_DOUBLELINK_MANGER *p_dlink);
-
-
-ZXIC_RTN32 zxic_comm_dlink_get_previous (ZXIC_DOUBLELINK_MANGER *p_dlink,
-                                   ZXIC_UINT32                     dw_index,
-                                   ZXIC_UINT32                    *p_pre_index);
-
-ZXIC_RTN32 zxic_comm_dlink_is_used      (ZXIC_DOUBLELINK_MANGER *p_dlink,
-                                   ZXIC_UINT32                     dw_index, 
-                                   ZXIC_UINT8                      *p_is_used);
-
-
-ZXIC_RTN32 zxic_comm_dlink_first_free   (ZXIC_DOUBLELINK_MANGER *p_dlink,
-                                   ZXIC_UINT32                    *p_index);
-
-
-ZXIC_RTN32 zxic_comm_dlink_first_used   (ZXIC_DOUBLELINK_MANGER *p_dlink, 
-                                   ZXIC_UINT32                    *p_index);
-
-
-
-ZXIC_RTN32 zxic_comm_dlink_manage_reset        (ZXIC_DOUBLELINK_MANGER *p_dlink);
-
-ZXIC_RTN32 zxic_comm_dlink_get_curr_info      (ZXIC_DOUBLELINK_MANGER  *p_dlink, 
-                                         ZXIC_UINT32                     *p_free_num, 
-                                         ZXIC_UINT32                     *p_curr_free_index);
-
-ZXIC_RTN32 zxic_comm_dlink_last_used          (ZXIC_DOUBLELINK_MANGER  *p_dlink, 
-                                         ZXIC_UINT32                     *p_index);
-
-ZXIC_RTN32 zxic_comm_dlink_used_num           (ZXIC_DOUBLELINK_MANGER  *p_dlink,
-                                         ZXIC_UINT32                     *p_num);
-
-ZXIC_RTN32 zxic_comm_dlink_show_node_info     (ZXIC_DOUBLELINK_MANGER  *p_dlink,
-                                         ZXIC_UINT32                      dw_node_index);
-
-ZXIC_RTN32 zxic_comm_dlink_show_current_status(ZXIC_DOUBLELINK_MANGER  *p_dlink);
-
-
-ZXIC_RTN32 zxic_comm_dlink_self_test(ZXIC_VOID);
-
-
-
-#endif
-
-
+/*****************************************************************************
+ * 版权所有 (C)2008-2010, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：zxic_doublelink_index.h
+ * 文件标识：
+ * 内容摘要：zxic_doublelink_index.c 的头文件， 这里定义了.c文件需要用到的数据结构，
+ * 并且申明了提供外部模块调用的接口函数
+ * 其它说明： 其它内容的说明
+ * 当前版本：
+ * 作    者：HuangHe(170389)   Z T E 中兴
+ * 完成日期：2009-02-16
+ * 当前责任人-1：HuangHe   Z T E 中兴
+ * 当前责任人-2：
+ * 历史责任人-3:
+ *
+ * 修改记录：
+ * 修改日期：   版 本 号   修 改 人     修改内容
+ 1 yyyymmdd       V*.*     姓名工号
+ 2
+  *****************************************************************************/
+#ifndef __ZXIC_COMM_DOUBLELINK_INDEX_H__
+#define __ZXIC_COMM_DOUBLELINK_INDEX_H__
+
+/**************************  include head files  *****************************/
+
+/**************************  type define  *****************************/
+#define DOUBLELINK_CHECKSUM ((ZXIC_UINT32)(0xAABBBAAB))
+
+/**************************  const variables  **************************/
+#define DOUBLELINK_INVALID_PREVIOUS (0x0)
+#define DOUBLELINK_INVALID_NEXT (0x0)
+#define DOUBLELINK_USED_FLAG ((ZXIC_UINT32)(0xffffffff))
+#define DOUBLELINK_LASTEST_ELEMENT ((ZXIC_UINT32)(0x0ffffffe))
+
+/**************************************************************************
+ *                        double_link_index api                           *
+ **************************************************************************/
+
+/**
+ * NAME: DLINK_NODE
+ *
+ * DESCRIPTION: Structure Node the information of the doublelink.
+ **/
+typedef struct {
+	ZXIC_UINT32 dw_next_node; /*后一个节点*/
+	ZXIC_UINT32 dw_pre_node; /*前一个节点*/
+	ZXIC_UINT32 dw_self_node; /*当前一个节点*/
+
+} DLINK_NODE;
+
+/**
+ * NAME: FTMCOMM_DOUBLELINK_MANGER
+ *
+ * DESCRIPTION: Structure containing the information required by the
+ * implementation of the doublelink.
+ **/
+
+typedef struct _FtmComm_DoubleLink_Manager {
+	/*
+     * p_array is a pointer to the array of elements used to track which
+     * indexes have been allocated.
+     */
+	DLINK_NODE *p_array;
+
+	/*
+     * numElements is the number of indexes managed by this instance of the
+     * index_pool.
+     */
+	ZXIC_UINT32 capacity;
+
+	/*
+     * currFreeElement stores a free element for where to alloc next free element.
+     * This helps prevent looping over a large sections of the array each time
+     * a new index is allocated.
+     */
+	ZXIC_UINT32 free_num;
+
+	ZXIC_UINT32 used_num;
+
+	ZXIC_UINT32 first_used;
+
+	ZXIC_UINT32 last_used;
+
+	ZXIC_UINT32 first_free;
+
+	ZXIC_UINT32 last_free;
+	/*
+     * offset is an adjustment value, allowing the caller to prevent certain
+     * indexes from being allocated.  This value is only meaningful to the
+     * client, and does not affect how the indexes are managed within the
+     * doublelink.
+     */
+	ZXIC_UINT32 offset;
+
+	ZXIC_UINT32 check_sum; /*用来检查传入的地址是否是双链表管理结构地址*/
+
+} ZXIC_DOUBLELINK_MANGER;
+
+ZXIC_RTN32 zxic_comm_dlink_manage_create(ZXIC_UINT32 dw_element_num,
+										 ZXIC_UINT32 dw_offset,
+										 ZXIC_DOUBLELINK_MANGER **p_dlink);
+
+ZXIC_RTN32 zxic_comm_dlink_alloc(ZXIC_DOUBLELINK_MANGER *p_dlink,
+								 ZXIC_UINT32 *index);
+
+ZXIC_RTN32 zxic_comm_dlink_free(ZXIC_DOUBLELINK_MANGER *p_dlink,
+								ZXIC_UINT32 index);
+
+ZXIC_RTN32 zxic_comm_dlink_get_next(ZXIC_DOUBLELINK_MANGER *p_dlink,
+									ZXIC_UINT32 dw_index,
+									ZXIC_UINT32 *p_next_index);
+
+ZXIC_RTN32 zxic_comm_dlink_manage_clear(ZXIC_DOUBLELINK_MANGER *p_dlink);
+
+ZXIC_RTN32 zxic_comm_dlink_get_previous(ZXIC_DOUBLELINK_MANGER *p_dlink,
+										ZXIC_UINT32 dw_index,
+										ZXIC_UINT32 *p_pre_index);
+
+ZXIC_RTN32 zxic_comm_dlink_is_used(ZXIC_DOUBLELINK_MANGER *p_dlink,
+								   ZXIC_UINT32 dw_index, ZXIC_UINT8 *p_is_used);
+
+ZXIC_RTN32 zxic_comm_dlink_first_free(ZXIC_DOUBLELINK_MANGER *p_dlink,
+									  ZXIC_UINT32 *p_index);
+
+ZXIC_RTN32 zxic_comm_dlink_first_used(ZXIC_DOUBLELINK_MANGER *p_dlink,
+									  ZXIC_UINT32 *p_index);
+
+ZXIC_RTN32 zxic_comm_dlink_manage_reset(ZXIC_DOUBLELINK_MANGER *p_dlink);
+
+ZXIC_RTN32 zxic_comm_dlink_get_curr_info(ZXIC_DOUBLELINK_MANGER *p_dlink,
+										 ZXIC_UINT32 *p_free_num,
+										 ZXIC_UINT32 *p_curr_free_index);
+
+ZXIC_RTN32 zxic_comm_dlink_last_used(ZXIC_DOUBLELINK_MANGER *p_dlink,
+									 ZXIC_UINT32 *p_index);
+
+ZXIC_RTN32 zxic_comm_dlink_used_num(ZXIC_DOUBLELINK_MANGER *p_dlink,
+									ZXIC_UINT32 *p_num);
+
+ZXIC_RTN32 zxic_comm_dlink_show_node_info(ZXIC_DOUBLELINK_MANGER *p_dlink,
+										  ZXIC_UINT32 dw_node_index);
+
+ZXIC_RTN32 zxic_comm_dlink_show_current_status(ZXIC_DOUBLELINK_MANGER *p_dlink);
+
+ZXIC_RTN32 zxic_comm_dlink_self_test(ZXIC_VOID);
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_ctrl.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_ctrl.h
index 9b887af51591ffe52333bae8dff67671dd570067..799453fdce4503398750a5e806078fda5e405e5b 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_ctrl.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_ctrl.h
@@ -1,77 +1,83 @@
-/*********************************************************************
-* 版权所有 (C)2001, 深圳市中兴通讯股份有限公司。
-*
-* 文件名称：
-* 文件标识：
-* 内容摘要:
-* 其它说明:
-*
-*
-* 当前版本：
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT   : 100% 
-* 作    者： 
-* 完成日期：2010-10-29
-********************************************************************/
-#ifndef _ZXIC_COMM_INDEX_CONTROLLER_H_
-#define _ZXIC_COMM_INDEX_CONTROLLER_H_
-
-//#include "zxic_common.h"
-//#include "zxic_comm_rb_tree.h"
-//#include "zxic_comm_double_link.h"
-
-
-#define ZXIC_INDEX_EXPAND_MAX_NUM   (900)
-#define INDEX_KEY_LENGTH           (4)
-typedef struct zxic_index_ctrl_cfg 
-{
-
-    ZXIC_UINT32                   index_cursor_current    ;
-    ZXIC_UINT32                   index_cursor_last       ;
-    ZXIC_UINT32                   index_cursor_max_cur    ;
-    ZXIC_UINT32                   index_ctrl_is_init      ;
-    ZXIC_UINT32*                  p_index_buf             ;
-
-    ZXIC_RB_CFG               index_ctrl_rb_tree      ;
-    ZXIC_RB_CFG               rcd_ctrl_rb_tree        ;
-    
-    D_HEAD                  *p_index_ctrl_link       ;
-}ZXIC_INDEX_CTRL_CFG;
-
-typedef struct _zxic_index_api_params
-{
-    ZXIC_UINT32 zxic_expand_num            ;    /*the expand num of this item  */
-    ZXIC_UINT32 zxic_opera_mode            ;    /*0:add;1:del;2:sch            */
-    ZXIC_UINT32 zxic_rsp_isexit            ;    /*the rsp of whether is exit   */
-    ZXIC_UINT32 *p_zxic_out_index          ;    /*the address of response      */ 
-    ZXIC_VOID   *p_zxic_data               ;    /*the data of inserting in tcam*/
-  
-} ZXIC_INDEX_API_PARAMS;
-
-typedef enum functionNo     /* 接口提供的表操作类型 */                                                           
-{
-    INDEX_CTRL_ADD,
-    INDEX_CTRL_ADD_FROM_LAST,
-    INDEX_CTRL_DEL,
-    INDEX_CTRL_SEARCH,   
-    INDEX_CTRL_UNDEFINED
-}FUNCTION_NO;
-
-
-
-
-ZXIC_RTN32 zxic_comm_indexctrl_get_free_index(ZXIC_INDEX_CTRL_CFG *p_table_info,ZXIC_UINT32 func_type,ZXIC_UINT32 *p_free_index_num);
-ZXIC_RTN32 zxic_comm_indexctrl_add_from_last(ZXIC_INDEX_CTRL_CFG *p_table_info,ZXIC_VOID *data,ZXIC_UINT32 expand_num,ZXIC_UINT32 *out_index);
-ZXIC_RTN32 zxic_comm_indexctrl_sch(ZXIC_INDEX_CTRL_CFG *p_table_info,ZXIC_VOID *data,ZXIC_UINT32 *p_is_exit,ZXIC_UINT32 *out_index);
-ZXIC_RTN32 zxic_comm_indexctrl_extcommand(ZXIC_INDEX_API_PARAMS *p_zxic_api_params,ZXIC_INDEX_CTRL_CFG *p_table_info) ;
-ZXIC_RTN32 zxic_comm_indexctrl_add(ZXIC_INDEX_CTRL_CFG *p_table_info,ZXIC_VOID *data,ZXIC_UINT32 expand_num,ZXIC_UINT32 *out_index);
-ZXIC_RTN32 zxic_comm_indexctrl_init(ZXIC_INDEX_CTRL_CFG *p_table_info,ZXIC_UINT32 index_max_num,ZXIC_UINT32 table_key_len);
-ZXIC_RTN32 zxic_comm_indexctrl_getindex_from_last(ZXIC_INDEX_CTRL_CFG *p_table_info,ZXIC_UINT32 *p_index_out);
-ZXIC_RTN32 zxic_comm_indexctrl_del(ZXIC_INDEX_CTRL_CFG *p_table_info,ZXIC_VOID *data,ZXIC_UINT32 *out_index);
-ZXIC_RTN32 zxic_comm_indexctrl_getindex(ZXIC_INDEX_CTRL_CFG *p_table_info,ZXIC_UINT32 *p_index_out);
-ZXIC_SINT32    zxic_comm_indexctrl_cmp_key(ZXIC_VOID *new_key, ZXIC_VOID *old_key,ZXIC_UINT32 key_len);
-
-
-#endif
-
-
+/*********************************************************************
+ * 版权所有 (C)2001, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：
+ * 文件标识：
+ * 内容摘要:
+ * 其它说明:
+ *
+ *
+ * 当前版本：
+ * DEPARTMENT: ASIC_FPGA_R&D_Dept
+ * MANUAL_PERCENT   : 100%
+ * 作    者：
+ * 完成日期：2010-10-29
+ ********************************************************************/
+#ifndef _ZXIC_COMM_INDEX_CONTROLLER_H_
+#define _ZXIC_COMM_INDEX_CONTROLLER_H_
+
+//#include "zxic_common.h"
+//#include "zxic_comm_rb_tree.h"
+//#include "zxic_comm_double_link.h"
+
+#define ZXIC_INDEX_EXPAND_MAX_NUM (900)
+#define INDEX_KEY_LENGTH (4)
+typedef struct zxic_index_ctrl_cfg {
+	ZXIC_UINT32 index_cursor_current;
+	ZXIC_UINT32 index_cursor_last;
+	ZXIC_UINT32 index_cursor_max_cur;
+	ZXIC_UINT32 index_ctrl_is_init;
+	ZXIC_UINT32 *p_index_buf;
+
+	ZXIC_RB_CFG index_ctrl_rb_tree;
+	ZXIC_RB_CFG rcd_ctrl_rb_tree;
+
+	D_HEAD *p_index_ctrl_link;
+} ZXIC_INDEX_CTRL_CFG;
+
+typedef struct _zxic_index_api_params {
+	ZXIC_UINT32 zxic_expand_num; /*the expand num of this item  */
+	ZXIC_UINT32 zxic_opera_mode; /*0:add;1:del;2:sch            */
+	ZXIC_UINT32 zxic_rsp_isexit; /*the rsp of whether is exit   */
+	ZXIC_UINT32 *p_zxic_out_index; /*the address of response      */
+	ZXIC_VOID *p_zxic_data; /*the data of inserting in tcam*/
+
+} ZXIC_INDEX_API_PARAMS;
+
+typedef enum functionNo /* 接口提供的表操作类型 */
+{ INDEX_CTRL_ADD,
+  INDEX_CTRL_ADD_FROM_LAST,
+  INDEX_CTRL_DEL,
+  INDEX_CTRL_SEARCH,
+  INDEX_CTRL_UNDEFINED } FUNCTION_NO;
+
+ZXIC_RTN32 zxic_comm_indexctrl_get_free_index(ZXIC_INDEX_CTRL_CFG *p_table_info,
+											  ZXIC_UINT32 func_type,
+											  ZXIC_UINT32 *p_free_index_num);
+ZXIC_RTN32 zxic_comm_indexctrl_add_from_last(ZXIC_INDEX_CTRL_CFG *p_table_info,
+											 ZXIC_VOID *data,
+											 ZXIC_UINT32 expand_num,
+											 ZXIC_UINT32 *out_index);
+ZXIC_RTN32 zxic_comm_indexctrl_sch(ZXIC_INDEX_CTRL_CFG *p_table_info,
+								   ZXIC_VOID *data, ZXIC_UINT32 *p_is_exit,
+								   ZXIC_UINT32 *out_index);
+ZXIC_RTN32
+zxic_comm_indexctrl_extcommand(ZXIC_INDEX_API_PARAMS *p_zxic_api_params,
+							   ZXIC_INDEX_CTRL_CFG *p_table_info);
+ZXIC_RTN32 zxic_comm_indexctrl_add(ZXIC_INDEX_CTRL_CFG *p_table_info,
+								   ZXIC_VOID *data, ZXIC_UINT32 expand_num,
+								   ZXIC_UINT32 *out_index);
+ZXIC_RTN32 zxic_comm_indexctrl_init(ZXIC_INDEX_CTRL_CFG *p_table_info,
+									ZXIC_UINT32 index_max_num,
+									ZXIC_UINT32 table_key_len);
+ZXIC_RTN32
+zxic_comm_indexctrl_getindex_from_last(ZXIC_INDEX_CTRL_CFG *p_table_info,
+									   ZXIC_UINT32 *p_index_out);
+ZXIC_RTN32 zxic_comm_indexctrl_del(ZXIC_INDEX_CTRL_CFG *p_table_info,
+								   ZXIC_VOID *data, ZXIC_UINT32 *out_index);
+ZXIC_RTN32 zxic_comm_indexctrl_getindex(ZXIC_INDEX_CTRL_CFG *p_table_info,
+										ZXIC_UINT32 *p_index_out);
+ZXIC_SINT32 zxic_comm_indexctrl_cmp_key(ZXIC_VOID *new_key, ZXIC_VOID *old_key,
+										ZXIC_UINT32 key_len);
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_fill.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_fill.h
index 3dcf520ef26ac5945bcf85dd566f13edc2cab300..fc26ff990e9e215d4310c001a3603519b38e47fd 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_fill.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_fill.h
@@ -1,69 +1,74 @@
-/*****************************************************************************
- * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。
- * 
- * 文件名称：   zxic_index_fill.h
- * 文件标识：    
- * 内容摘要：  索引空位填充源代码头文件
- * 其它说明：   
- * 当前版本：    
- * 作    者：    ChenWei10088471
- * 完成日期：   
- * 当前责任人-1：
- * 当前责任人-2：
- *
- * DEPARTMENT       : ASIC_FPGA_R&D_Dept
- * MANUAL_PERCENT   : 100% 
- *****************************************************************************/
-
-#ifndef _ZXIC_COMM_INDEX_FILL_H
-#define _ZXIC_COMM_INDEX_FILL_H
-
-
-typedef ZXIC_RTN32 (*INDEXFILL_SWAP_FUNC)(ZXIC_UINT32 old_index,ZXIC_UINT32 new_index,ZXIC_VOID *p_cfg);
-
-
-typedef struct
-{
-    ZXIC_RB_TN    rb_node;
-    ZXIC_UINT32       position;
-    ZXIC_UINT32       usednum;
-}INDEX_FILL_NODE;
-
-typedef struct
-{
-    ZXIC_RB_CFG           fill_rb;
-    ZXIC_UINT32               index_num;  
-    INDEX_FILL_NODE      *fill_node;
-    INDEXFILL_SWAP_FUNC  swap_fun;
-    ZXIC_UINT32               total_used;
-}INDEX_FILL_CFG;
-
-ZXIC_RTN32 ic_comm_node_data_free(void *p_data);
-
-
-ZXIC_RTN32 zxic_comm_indexfill_init(INDEX_FILL_CFG *p_fill_cfg,
-                              ZXIC_UINT32 index_num,
-                              ZXIC_KEY_CMP_FUNC p_cmp_fun,
-                              INDEXFILL_SWAP_FUNC p_swap_fun,
-                              ZXIC_UINT32 key_len);
-
-ZXIC_RTN32 zxic_comm_indexfill_free(INDEX_FILL_CFG *p_fill_cfg,
-                              ZXIC_UINT32 free_index,
-                              ZXIC_VOID* p_rb_key,
-                              ZXIC_UINT32 *out_index);
-
-ZXIC_RTN32 zxic_comm_indexfill_destroy(INDEX_FILL_CFG *p_fill_cfg);
-
-ZXIC_RTN32 zxic_comm_indexfill_store(INDEX_FILL_CFG *p_fill_cfg, ZXIC_UINT32 *p_size, ZXIC_UINT8 **p_data_buff);
-
-ZXIC_RTN32 zxic_comm_indexfill_show_all_position(INDEX_FILL_CFG *p_fill_cfg);
-ZXIC_RTN32 zxic_comm_indexfill_clear(INDEX_FILL_CFG *p_fill_cfg);
-
-#define    ICMINF_GET_NODE_LASTPOS(p_inf_node) \
-    ((p_inf_node)->position + (p_inf_node)->usednum -1)
-
-#define    ICMINF_GET_NODE_FSTPOS(p_inf_node) \
-    ((p_inf_node)->position)
-
-#endif
-
+/*****************************************************************************
+ * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：   zxic_index_fill.h
+ * 文件标识：
+ * 内容摘要：  索引空位填充源代码头文件
+ * 其它说明：
+ * 当前版本：
+ * 作    者：    ChenWei10088471
+ * 完成日期：
+ * 当前责任人-1：
+ * 当前责任人-2：
+ *
+ * DEPARTMENT       : ASIC_FPGA_R&D_Dept
+ * MANUAL_PERCENT   : 100%
+ *****************************************************************************/
+
+#ifndef _ZXIC_COMM_INDEX_FILL_H
+#define _ZXIC_COMM_INDEX_FILL_H
+
+typedef ZXIC_RTN32 (*INDEXFILL_SWAP_FUNC)(ZXIC_UINT32 old_index,
+										  ZXIC_UINT32 new_index,
+										  ZXIC_VOID *p_cfg);
+
+typedef struct {
+	ZXIC_RB_TN rb_node;
+	ZXIC_UINT32 position;
+	ZXIC_UINT32 usednum;
+} INDEX_FILL_NODE;
+
+typedef struct {
+	ZXIC_RB_CFG fill_rb;
+	ZXIC_UINT32 index_num;
+	INDEX_FILL_NODE *fill_node;
+	INDEXFILL_SWAP_FUNC swap_fun;
+	ZXIC_UINT32 total_used;
+} INDEX_FILL_CFG;
+
+ZXIC_RTN32 ic_comm_node_data_free(void *p_data);
+
+ZXIC_RTN32 zxic_comm_indexfill_init(INDEX_FILL_CFG *p_fill_cfg,
+									ZXIC_UINT32 index_num,
+									ZXIC_KEY_CMP_FUNC p_cmp_fun,
+									INDEXFILL_SWAP_FUNC p_swap_fun,
+									ZXIC_UINT32 key_len);
+
+ZXIC_RTN32 zxic_comm_indexfill_alloc(INDEX_FILL_CFG *p_fill_cfg,
+									 ZXIC_UINT32 *out_index,
+									 ZXIC_VOID *p_rb_key);
+
+ZXIC_RTN32 zxic_comm_indexfill_free(INDEX_FILL_CFG *p_fill_cfg,
+									ZXIC_UINT32 free_index, ZXIC_VOID *p_rb_key,
+									ZXIC_UINT32 *out_index);
+
+ZXIC_RTN32 zxic_comm_indexfill_destroy(INDEX_FILL_CFG *p_fill_cfg);
+
+ZXIC_RTN32 zxic_comm_indexfill_store(INDEX_FILL_CFG *p_fill_cfg,
+									 ZXIC_UINT32 *p_size,
+									 ZXIC_UINT8 **p_data_buff);
+ZXIC_RTN32 zxic_comm_indexfill_recovery(INDEX_FILL_CFG *p_fill_cfg,
+										ZXIC_UINT32 size,
+										ZXIC_UINT8 *p_data_buff,
+										ZXIC_KEY_CMP_FUNC p_cmp_fun,
+										INDEXFILL_SWAP_FUNC p_swap_fun);
+
+ZXIC_RTN32 zxic_comm_indexfill_show_all_position(INDEX_FILL_CFG *p_fill_cfg);
+ZXIC_RTN32 zxic_comm_indexfill_clear(INDEX_FILL_CFG *p_fill_cfg);
+
+#define ICMINF_GET_NODE_LASTPOS(p_inf_node) \
+	((p_inf_node)->position + (p_inf_node)->usednum - 1)
+
+#define ICMINF_GET_NODE_FSTPOS(p_inf_node) ((p_inf_node)->position)
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_fill_type.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_fill_type.h
index ae4f64a1f569034b59b1e664e80b2323b42ef3cc..22773c2075bb9fc93282c1bd7fd6f46181a6e690 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_fill_type.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_fill_type.h
@@ -1,96 +1,88 @@
-/*****************************************************************************
- * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。
- * 
- * 文件名称：   zxic_index_fill.h
- * 文件标识：    
- * 内容摘要：  索引空位填充源代码头文件
- * 其它说明：   
- * 当前版本：    
- * 作    者：    ChenWei10088471
- * 完成日期：   
- * 当前责任人-1：
- * 当前责任人-2：
- *
- * DEPARTMENT       : ASIC_FPGA_R&D_Dept
- * MANUAL_PERCENT   : 100% 
- *****************************************************************************/
-
-#ifndef _ZXIC_COMM_INDEX_FILL_TYPE_H
-#define _ZXIC_COMM_INDEX_FILL_TYPE_H
-
-typedef ZXIC_RTN32 (*INDEXFILL_TYPE_SWAP_FUNC)(ZXIC_UINT32 old_index,ZXIC_UINT32 new_index,ZXIC_VOID *p_cfg);
-
-typedef struct
-{
-    ZXIC_UINT32 is_used;    /* 0空闲，1已分配 */
-    ZXIC_UINT32 prio;
-}INDEX_FILL_TYPE_INDEX_STATUS;  /* is_used==0时，不关心prio */
-
-typedef struct
-{
-    ZXIC_RB_TN prio_rb_node;                /* prio_rb_tree中的节点 */
-    ZXIC_RB_CFG idx_rb_cfg;                 /* 以index为key，详细记录每个prio的每个index信息 */
-    ZXIC_UINT32 prio;                       /* prio值*/
-}INDEX_FILL_TYPE_PRIO_NODE;
-
-typedef struct {
-    ZXIC_UINT32 prio;
-} SSP4_INDEX_FILL_TYPE_PRIO_RB_KEY;         /* prio红黑树的key */
-
-typedef struct
-{
-    ZXIC_RB_CFG prio_rb;    /* 每type的prio红黑树，以prio为key */
-    D_HEAD mv_list_head;    /* 同type的移位链表 */
-    ZXIC_VOID *p_cfg;       /* type相关的其他参数定义，外部自行定义 */
-}INDEX_FILL_TYPE_MNG_CFG;
-
-typedef struct
-{
-    ZXIC_UINT32                     index_num;                        /* 本池的索引数量 */
-    ZXIC_UINT32                     total_used;                       /* 本池已使用的索引数量 */
-    ZXIC_UINT32                     prio_max;                       /* 最大优先级范围 */
-    ZXIC_UINT32                     global_max_num;                       /* 全局最大数量*/
-    INDEX_FILL_TYPE_INDEX_STATUS    *p_idx_status;               /* 全局索引池状态位记录数组指针 */
-    INDEXFILL_TYPE_SWAP_FUNC        swap_fun;                         /* 向前或者向后挤压时的移位操作函数 */
-}INDEX_FILL_TYPE_INDEX_POOL_CFG; /* 多种type共享的索引池 */
-
-
-
-ZXIC_UINT32 zxic_comm_indexfill_type_idx_status_get(INDEX_FILL_TYPE_INDEX_STATUS *index_status, 
-                                                    ZXIC_UINT32 index, 
-                                                    ZXIC_UINT32 *used_status_flag, 
-                                                    ZXIC_UINT32 *used_status_prio);
-
-
-ZXIC_UINT32 zxic_comm_indexfill_type_idx_status_set(INDEX_FILL_TYPE_INDEX_STATUS *index_status, 
-                                                    ZXIC_UINT32 index, 
-                                                    ZXIC_UINT32 prio, 
-                                                    ZXIC_UINT32 used_flag);
-
-ZXIC_RTN32 zxic_comm_indexfill_type_init(INDEX_FILL_TYPE_INDEX_POOL_CFG *p_fill_type_index_pool_cfg, 
-                                            ZXIC_UINT32 index_num, 
-                                            ZXIC_UINT32 prio_max, 
-                                            ZXIC_UINT32 global_max_num,
-                                            INDEXFILL_TYPE_SWAP_FUNC p_swap_fun);
-
-ZXIC_RTN32 zxic_comm_indexfill_type_rb_init(INDEX_FILL_TYPE_MNG_CFG *p_fill_type_mng_cfg);
-
-/* 多张type共享的索引记录 */
-/* 每种type，一个prio红黑树管理结构，一个prio+index红黑树管理结构 */
-ZXIC_RTN32 zxic_comm_indexfill_type_alloc(INDEX_FILL_TYPE_INDEX_POOL_CFG *p_fill_type_index_pool_cfg, 
-                                          INDEX_FILL_TYPE_MNG_CFG *p_fill_type_mng_cfg, 
-                                          ZXIC_UINT32 prio,
-                                          ZXIC_UINT32 *out_index);
-/* 多张type共享的索引记录 */
-/* 每种type，一个prio红黑树管理结构，一个prio+index红黑树管理结构 */
-ZXIC_RTN32 zxic_comm_indexfill_type_free(INDEX_FILL_TYPE_INDEX_POOL_CFG *p_fill_type_index_pool_cfg, 
-                                          INDEX_FILL_TYPE_MNG_CFG *p_fill_type_mng_cfg, 
-                                          ZXIC_UINT32 free_index, 
-                                          ZXIC_UINT32 *out_index);
-
-ZXIC_RTN32 zxic_comm_indexfill_type_show_all_position(INDEX_FILL_TYPE_INDEX_POOL_CFG *p_fill_type_index_pool_cfg, 
-                                                        INDEX_FILL_TYPE_MNG_CFG *p_fill_type_mng_cfg);
-
-
-#endif
-
+/*****************************************************************************
+ * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：   zxic_index_fill.h
+ * 文件标识：
+ * 内容摘要：  索引空位填充源代码头文件
+ * 其它说明：
+ * 当前版本：
+ * 作    者：    ChenWei10088471
+ * 完成日期：
+ * 当前责任人-1：
+ * 当前责任人-2：
+ *
+ * DEPARTMENT       : ASIC_FPGA_R&D_Dept
+ * MANUAL_PERCENT   : 100%
+ *****************************************************************************/
+
+#ifndef _ZXIC_COMM_INDEX_FILL_TYPE_H
+#define _ZXIC_COMM_INDEX_FILL_TYPE_H
+
+typedef ZXIC_RTN32 (*INDEXFILL_TYPE_SWAP_FUNC)(ZXIC_UINT32 old_index,
+											   ZXIC_UINT32 new_index,
+											   ZXIC_VOID *p_cfg);
+
+typedef struct {
+	ZXIC_UINT32 is_used; /* 0空闲，1已分配 */
+	ZXIC_UINT32 prio;
+} INDEX_FILL_TYPE_INDEX_STATUS; /* is_used==0时，不关心prio */
+
+typedef struct {
+	ZXIC_RB_TN prio_rb_node; /* prio_rb_tree中的节点 */
+	ZXIC_RB_CFG idx_rb_cfg; /* 以index为key，详细记录每个prio的每个index信息 */
+	ZXIC_UINT32 prio; /* prio值*/
+} INDEX_FILL_TYPE_PRIO_NODE;
+
+typedef struct {
+	ZXIC_UINT32 prio;
+} SSP4_INDEX_FILL_TYPE_PRIO_RB_KEY; /* prio红黑树的key */
+
+typedef struct {
+	ZXIC_RB_CFG prio_rb; /* 每type的prio红黑树，以prio为key */
+	D_HEAD mv_list_head; /* 同type的移位链表 */
+	ZXIC_VOID *p_cfg; /* type相关的其他参数定义，外部自行定义 */
+} INDEX_FILL_TYPE_MNG_CFG;
+
+typedef struct {
+	ZXIC_UINT32 index_num; /* 本池的索引数量 */
+	ZXIC_UINT32 total_used; /* 本池已使用的索引数量 */
+	ZXIC_UINT32 prio_max; /* 最大优先级范围 */
+	ZXIC_UINT32 global_max_num; /* 全局最大数量*/
+	INDEX_FILL_TYPE_INDEX_STATUS *p_idx_status; /* 全局索引池状态位记录数组指针 */
+	INDEXFILL_TYPE_SWAP_FUNC swap_fun; /* 向前或者向后挤压时的移位操作函数 */
+} INDEX_FILL_TYPE_INDEX_POOL_CFG; /* 多种type共享的索引池 */
+
+ZXIC_UINT32 zxic_comm_indexfill_type_idx_status_get(
+		INDEX_FILL_TYPE_INDEX_STATUS *index_status, ZXIC_UINT32 index,
+		ZXIC_UINT32 *used_status_flag, ZXIC_UINT32 *used_status_prio);
+
+ZXIC_UINT32 zxic_comm_indexfill_type_idx_status_set(
+		INDEX_FILL_TYPE_INDEX_STATUS *index_status, ZXIC_UINT32 index,
+		ZXIC_UINT32 prio, ZXIC_UINT32 used_flag);
+
+ZXIC_RTN32 zxic_comm_indexfill_type_init(
+		INDEX_FILL_TYPE_INDEX_POOL_CFG * p_fill_type_index_pool_cfg,
+		ZXIC_UINT32 index_num, ZXIC_UINT32 prio_max, ZXIC_UINT32 global_max_num,
+		INDEXFILL_TYPE_SWAP_FUNC p_swap_fun);
+
+ZXIC_RTN32
+zxic_comm_indexfill_type_rb_init(INDEX_FILL_TYPE_MNG_CFG *p_fill_type_mng_cfg);
+
+/* 多张type共享的索引记录 */
+/* 每种type，一个prio红黑树管理结构，一个prio+index红黑树管理结构 */
+ZXIC_RTN32 zxic_comm_indexfill_type_alloc(
+		INDEX_FILL_TYPE_INDEX_POOL_CFG * p_fill_type_index_pool_cfg,
+		INDEX_FILL_TYPE_MNG_CFG *p_fill_type_mng_cfg, ZXIC_UINT32 prio,
+		ZXIC_UINT32 *out_index);
+/* 多张type共享的索引记录 */
+/* 每种type，一个prio红黑树管理结构，一个prio+index红黑树管理结构 */
+ZXIC_RTN32 zxic_comm_indexfill_type_free(
+		INDEX_FILL_TYPE_INDEX_POOL_CFG * p_fill_type_index_pool_cfg,
+		INDEX_FILL_TYPE_MNG_CFG *p_fill_type_mng_cfg, ZXIC_UINT32 free_index,
+		ZXIC_UINT32 *out_index);
+
+ZXIC_RTN32 zxic_comm_indexfill_type_show_all_position(
+		INDEX_FILL_TYPE_INDEX_POOL_CFG * p_fill_type_index_pool_cfg,
+		INDEX_FILL_TYPE_MNG_CFG *p_fill_type_mng_cfg);
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_reserve.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_reserve.h
index 3a6e8ac462f131a381b446e1267546cc1ccdb6fd..0ab8459fe8037e0c7e609d2c7c8765c01fddff7d 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_reserve.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_index_reserve.h
@@ -1,78 +1,78 @@
-/*****************************************************************************
- * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。
- * 
- * 文件名称：   zxic_index_reserve.h
- * 文件标识：    
- * 内容摘要：   索引预留算法源代码头文件
- * 其它说明：   
- * 当前版本：    
- * 作    者：    ChenWei10088471
- * 完成日期：   
- * 当前责任人-1：
- * 当前责任人-2：
- *
- * DEPARTMENT       : ASIC_FPGA_R&D_Dept
- * MANUAL_PERCENT   : 100% 
- *****************************************************************************/
-#ifndef _ZXIC_COMM_INDEX_RESERVE_H
-#define _ZXIC_COMM_INDEX_RESERVE_H
-
-#define  CMP_MODE_LOW   (0)
-#define  CMP_MODE_HIGH  (1)
-typedef ZXIC_UINT32 (*SWAP_FUNC)(ZXIC_UINT32 old_index,ZXIC_UINT32 new_index);
-typedef ZXIC_UINT32 (*LOCAL_SWAP_FUNC)(ZXIC_VOID *p_cfg,ZXIC_UINT32 old_index,ZXIC_UINT32 new_index);
-
-typedef struct
-{
-    ZXIC_UINT32 head_curr;
-    ZXIC_UINT32 tail_curr;
-}INDEX_CURR;
-
-typedef struct
-{
-    ZXIC_UINT32 old_handle;
-    ZXIC_UINT32 new_handle;
-}INR_SWAP_NODE;
-
-typedef struct _index_res_cfg
-{
-    ZXIC_UINT32          total_num;
-    ZXIC_UINT32          space_num;
-    ZXIC_UINT32*         index_prop;
-    ZXIC_RB_CFG*     index_usedrb;
-    ZXIC_RB_CFG*     index_freerb;
-    ZXIC_RB_TN*      index_node;
-    SWAP_FUNC       swap_fun;
-    LOCAL_SWAP_FUNC local_fun;
-    INDEX_CURR*     index_curr;
-    D_HEAD          swap_list;
-    ZXIC_UINT32          total_used;    
-    ZXIC_UINT32           is_init;
-    ZXIC_UINT32     indexres_id;
-}INDEX_RES_CFG;
-ZXIC_VOID zxic_comm_rb_tn_relation_clear(ZXIC_RB_TN *rb_tn_node);
-
-ZXIC_RTN32 zxic_comm_indexres_init(INDEX_RES_CFG *p_indexres_cfg,  /*配置句柄*/
-                             ZXIC_UINT32         arg_total_num,   /*索引总数*/
-                             ZXIC_UINT32         arg_space_num,   /*空间总数*/
-                             ZXIC_UINT32*        arg_index_prop,  /*空间大小，若用户提供，则按用户提供的进行空间分配，否则平均分配所有空间*/
-                             SWAP_FUNC      p_swap_fun,
-                             LOCAL_SWAP_FUNC local_fun);     /*重排函数，注册则调用，否则不调*/
-
-ZXIC_RTN32 zxic_comm_indexres_alloc(INDEX_RES_CFG *p_indexres_cfg, /*配置句柄*/
-                                 ZXIC_UINT32         space_val,   /*空间序列*/
-                                 ZXIC_UINT32         *out_index); /*出参，分配的索引*/
-
-ZXIC_RTN32 zxic_comm_indexres_free(INDEX_RES_CFG *p_indexres_cfg,
-                             ZXIC_UINT32         space_val,
-                             ZXIC_UINT32         free_index);
-
-ZXIC_RTN32 zxic_comm_indexres_destory(INDEX_RES_CFG *p_indexres_cfg);
-
-ZXIC_RTN32 zxic_comm_indexres_reset(INDEX_RES_CFG *p_indexres_cfg);
-
-ZXIC_RTN32 zxic_comm_indexres_showinfo(INDEX_RES_CFG *p_indexres_cfg);/*重置整个索引空间，恢复到最初的配置状态，注意，此时所有的索引都需要在未使用状态*/
-
-
-#endif
-
+/*****************************************************************************
+ * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：   zxic_index_reserve.h
+ * 文件标识：
+ * 内容摘要：   索引预留算法源代码头文件
+ * 其它说明：
+ * 当前版本：
+ * 作    者：    ChenWei10088471
+ * 完成日期：
+ * 当前责任人-1：
+ * 当前责任人-2：
+ *
+ * DEPARTMENT       : ASIC_FPGA_R&D_Dept
+ * MANUAL_PERCENT   : 100%
+ *****************************************************************************/
+#ifndef _ZXIC_COMM_INDEX_RESERVE_H
+#define _ZXIC_COMM_INDEX_RESERVE_H
+
+#define CMP_MODE_LOW (0)
+#define CMP_MODE_HIGH (1)
+typedef ZXIC_UINT32 (*SWAP_FUNC)(ZXIC_UINT32 old_index, ZXIC_UINT32 new_index);
+typedef ZXIC_UINT32 (*LOCAL_SWAP_FUNC)(ZXIC_VOID *p_cfg, ZXIC_UINT32 old_index,
+									   ZXIC_UINT32 new_index);
+
+typedef struct {
+	ZXIC_UINT32 head_curr;
+	ZXIC_UINT32 tail_curr;
+} INDEX_CURR;
+
+typedef struct {
+	ZXIC_UINT32 old_handle;
+	ZXIC_UINT32 new_handle;
+} INR_SWAP_NODE;
+
+typedef struct _index_res_cfg {
+	ZXIC_UINT32 total_num;
+	ZXIC_UINT32 space_num;
+	ZXIC_UINT32 *index_prop;
+	ZXIC_RB_CFG *index_usedrb;
+	ZXIC_RB_CFG *index_freerb;
+	ZXIC_RB_TN *index_node;
+	SWAP_FUNC swap_fun;
+	LOCAL_SWAP_FUNC local_fun;
+	INDEX_CURR *index_curr;
+	D_HEAD swap_list;
+	ZXIC_UINT32 total_used;
+	ZXIC_UINT32 is_init;
+	ZXIC_UINT32 indexres_id;
+} INDEX_RES_CFG;
+ZXIC_VOID zxic_comm_rb_tn_relation_clear(ZXIC_RB_TN *rb_tn_node);
+
+ZXIC_RTN32 zxic_comm_indexres_init(
+		INDEX_RES_CFG * p_indexres_cfg, /*配置句柄*/
+		ZXIC_UINT32 arg_total_num, /*索引总数*/
+		ZXIC_UINT32 arg_space_num, /*空间总数*/
+		ZXIC_UINT32 *arg_index_prop, /*空间大小，若用户提供，则按用户提供的进行空间分配，否则平均分配所有空间*/
+		SWAP_FUNC p_swap_fun,
+		LOCAL_SWAP_FUNC local_fun); /*重排函数，注册则调用，否则不调*/
+
+ZXIC_RTN32
+zxic_comm_indexres_alloc(INDEX_RES_CFG *p_indexres_cfg, /*配置句柄*/
+						 ZXIC_UINT32 space_val, /*空间序列*/
+						 ZXIC_UINT32 *out_index); /*出参，分配的索引*/
+
+ZXIC_RTN32 zxic_comm_indexres_free(INDEX_RES_CFG *p_indexres_cfg,
+								   ZXIC_UINT32 space_val,
+								   ZXIC_UINT32 free_index);
+
+ZXIC_RTN32 zxic_comm_indexres_destory(INDEX_RES_CFG *p_indexres_cfg);
+
+ZXIC_RTN32 zxic_comm_indexres_reset(INDEX_RES_CFG *p_indexres_cfg);
+
+ZXIC_RTN32 zxic_comm_indexres_showinfo(
+		INDEX_RES_CFG *
+				p_indexres_cfg); /*重置整个索引空间，恢复到最初的配置状态，注意，此时所有的索引都需要在未使用状态*/
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_liststack.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_liststack.h
index cac0dda324a8b2b686371277b899c31197ec4c91..f71f9675cf1ae1628a1ce541932c15284b50d957 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_liststack.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_liststack.h
@@ -1,95 +1,88 @@
-/*****************************************************************************
- * 版权所有 (C)2001-2005, 深圳市中兴通讯股份有限公司。
- * 
- * 文件名称：   Rtm_ListStack.h
- * 文件标识：    
- * 内容摘要：   链表栈管理头文件
- * 其它说明：   释放的元素放到队头
- * 当前版本：    ZXR10 V2.6
- * 作    者：    郑纪伟
- * 完成日期：    2006-9-27 10:34
- * 当前责任人-1：
- * 当前责任人-2：
- *
- * 修改记录1：   
- *    修改日期：2006-9-27 10:34
- *    版 本 号：ZXR10 V2.6
- *    修 改 人：郑纪伟
- *    修改内容：创建 
- * 
- *修改记录2：
- *    修改文件名称：ftmcomm_liststack.h
- *    修改日期：2008-10-16 15:14
- *    版 本 号：ZXR10 V2.6
- *    修 改 人：HuangHe 170389
- *    修改内容：移植到T8000项目使用 
- *修改记录3：
- *    修改文件名称：zxic_liststack.h
- *    修改日期：2012-03-15 15:14
- *    版 本 号：ZXR10 V2.6
- *    修 改 人：JiangWenming 12010401
- *    修改内容：移植到NSE项目使用 
- * 
- *****************************************************************************/
-#ifndef __ZXIC_COMM_LIST_STACK_H__
-#define __ZXIC_COMM_LIST_STACK_H__
-
-
-/**************************************************************************
- *                            宏定义                                      *
- **************************************************************************/
-
-#define LISTSTACK_MAX_ELEMENT  ((ZXIC_UINT32)(0x0ffffffe))
-#define LISTSTACK_INVALID_INDEX     (0)
-#define ALLOC_NUMBER                (0x3)
-/**************************************************************************
- *                        liststack api                                   *
- **************************************************************************/
-
-typedef struct _s_freelink
-{
-    ZXIC_UINT32 index;
-    ZXIC_UINT32 next;
-}ZXIC_COMM_FREELINK;
-
-
-typedef struct _s_List_Stack_Manager
-{
-  ZXIC_COMM_FREELINK  *p_array;
-
-  ZXIC_UINT32 capacity;
-
-  ZXIC_UINT32 p_head;
-
-  ZXIC_UINT32 free_num;
-  ZXIC_UINT32 used_num;
-
-}ZXIC_LISTSTACK_MANGER;
-
-/*
-**zxic_comm_liststack_creat:
-*/
-
-ZXIC_RTN32 zxic_comm_liststack_creat  (ZXIC_UINT32                  element_num, 
-                                 ZXIC_LISTSTACK_MANGER  **p_list);
-
-/*
-**NOTE:index allocated from 0:
-*/
-ZXIC_RTN32 zxic_comm_liststack_alloc  (ZXIC_LISTSTACK_MANGER   *p_list,
-                                 ZXIC_UINT32                 *index);
-ZXIC_RTN32 zxic_comm_liststack_free   (ZXIC_LISTSTACK_MANGER*   p_list,
-                                 ZXIC_UINT32                  index);
-ZXIC_RTN32 zxic_comm_liststack_destroy(ZXIC_LISTSTACK_MANGER*   p_list);
-ZXIC_RTN32 zxic_comm_liststack_alloc_spec_index(ZXIC_LISTSTACK_MANGER* p_list, ZXIC_UINT32 index);
-
-ZXIC_RTN32 zxic_comm_liststack_show_used(ZXIC_LISTSTACK_MANGER* p_list, ZXIC_UINT32 line_number );
-ZXIC_RTN32 zxic_comm_liststack_show_free (ZXIC_LISTSTACK_MANGER* p_list, ZXIC_UINT32 line_number );
-
-
-
-#endif /* end "_FTMCOMM_LIST_STACK_H" */
-
-
-
-
+/*****************************************************************************
+ * 版权所有 (C)2001-2005, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：   Rtm_ListStack.h
+ * 文件标识：
+ * 内容摘要：   链表栈管理头文件
+ * 其它说明：   释放的元素放到队头
+ * 当前版本：    ZXR10 V2.6
+ * 作    者：    郑纪伟
+ * 完成日期：    2006-9-27 10:34
+ * 当前责任人-1：
+ * 当前责任人-2：
+ *
+ * 修改记录1：
+ *    修改日期：2006-9-27 10:34
+ *    版 本 号：ZXR10 V2.6
+ *    修 改 人：郑纪伟
+ *    修改内容：创建
+ *
+ *修改记录2：
+ *    修改文件名称：ftmcomm_liststack.h
+ *    修改日期：2008-10-16 15:14
+ *    版 本 号：ZXR10 V2.6
+ *    修 改 人：HuangHe 170389
+ *    修改内容：移植到T8000项目使用
+ *修改记录3：
+ *    修改文件名称：zxic_liststack.h
+ *    修改日期：2012-03-15 15:14
+ *    版 本 号：ZXR10 V2.6
+ *    修 改 人：JiangWenming 12010401
+ *    修改内容：移植到NSE项目使用
+ *
+ *****************************************************************************/
+#ifndef __ZXIC_COMM_LIST_STACK_H__
+#define __ZXIC_COMM_LIST_STACK_H__
+
+/**************************************************************************
+ *                            宏定义                                      *
+ **************************************************************************/
+
+#define LISTSTACK_MAX_ELEMENT ((ZXIC_UINT32)(0x0ffffffe))
+#define LISTSTACK_INVALID_INDEX (0)
+#define ALLOC_NUMBER (0x3)
+/**************************************************************************
+ *                        liststack api                                   *
+ **************************************************************************/
+
+typedef struct _s_freelink {
+	ZXIC_UINT32 index;
+	ZXIC_UINT32 next;
+} ZXIC_COMM_FREELINK;
+
+typedef struct _s_List_Stack_Manager {
+	ZXIC_COMM_FREELINK *p_array;
+
+	ZXIC_UINT32 capacity;
+
+	ZXIC_UINT32 p_head;
+
+	ZXIC_UINT32 free_num;
+	ZXIC_UINT32 used_num;
+
+} ZXIC_LISTSTACK_MANGER;
+
+/*
+**zxic_comm_liststack_creat:
+*/
+
+ZXIC_RTN32 zxic_comm_liststack_creat(ZXIC_UINT32 element_num,
+									 ZXIC_LISTSTACK_MANGER **p_list);
+
+/*
+**NOTE:index allocated from 0:
+*/
+ZXIC_RTN32 zxic_comm_liststack_alloc(ZXIC_LISTSTACK_MANGER *p_list,
+									 ZXIC_UINT32 *index);
+ZXIC_RTN32 zxic_comm_liststack_free(ZXIC_LISTSTACK_MANGER *p_list,
+									ZXIC_UINT32 index);
+ZXIC_RTN32 zxic_comm_liststack_destroy(ZXIC_LISTSTACK_MANGER *p_list);
+ZXIC_RTN32 zxic_comm_liststack_alloc_spec_index(ZXIC_LISTSTACK_MANGER *p_list,
+												ZXIC_UINT32 index);
+
+ZXIC_RTN32 zxic_comm_liststack_show_used(ZXIC_LISTSTACK_MANGER *p_list,
+										 ZXIC_UINT32 line_number);
+ZXIC_RTN32 zxic_comm_liststack_show_free(ZXIC_LISTSTACK_MANGER *p_list,
+										 ZXIC_UINT32 line_number);
+
+#endif /* end "_FTMCOMM_LIST_STACK_H" */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_rb_tree.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_rb_tree.h
index cc3787cefc3cbb56c2675669bf1d0c28baa09ef9..fc397f563aff2a06543c90050226f46712881e98 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_rb_tree.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_rb_tree.h
@@ -1,128 +1,116 @@
-/*****************************************************************************
- * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。
- * 
- * 文件名称：   zxic_comm_rb_tree.h
- * 文件标识：    
- * 内容摘要：   
- * 其它说明：   
- * 当前版本：    
- * 作    者：    ChenWei10088471
- * 完成日期：   
- * 当前责任人-1：
- * 当前责任人-2：
- *
- * DEPARTMENT       : ASIC_FPGA_R&D_Dept
- * MANUAL_PERCENT   : 100% 
- *****************************************************************************/
-
-#ifndef _ZXIC_COMM_RB_TREE_H
-#define _ZXIC_COMM_RB_TREE_H
-
-#include "zxic_comm_double_link.h"
-#include "zxic_comm_liststack.h"
-
-#define   ZXIC_RBT_RED          (0x1)
-#define   ZXIC_RBT_BLACK        (0x2)
-#define   ZXIC_RBT_MAX_DEPTH    (128)
-
-typedef ZXIC_SINT32  (*ZXIC_RB_CMPFUN)(ZXIC_VOID *p_new,ZXIC_VOID *p_old,ZXIC_UINT32 keysize);
-
-
-typedef struct _rb_tn
-{
-    ZXIC_VOID     *p_key;
-    ZXIC_UINT32    color_lsv;       /*last 2 bits indicate color, bit2-31 if dynamic=0 indicate list val*/
-    struct    _rb_tn   *p_left;
-    struct    _rb_tn   *p_right;
-    struct    _rb_tn   *p_parent;
-    D_NODE    tn_ln;
-}ZXIC_RB_TN;
-
-typedef struct _rb_cfg
-{
-    ZXIC_UINT32                 key_size;
-    ZXIC_UINT32                 is_dynamic;  /* 1 - customer manage memory;0 - alloc all memory*/
-    ZXIC_RB_TN             *p_root;      /* rb tree root node */
-    D_HEAD                 tn_list;
-    ZXIC_RB_CMPFUN          p_cmpfun;
-    ZXIC_LISTSTACK_MANGER   *p_lsm;      /* list stack manage*/
-    ZXIC_UINT8                   *p_keybase;
-    ZXIC_RB_TN              *p_tnbase;
-    ZXIC_UINT32             is_init;
-}ZXIC_RB_CFG;
-
-
-
-#define GET_TN_COLOR(p_tn) \
-           ((p_tn == NULL) ? ZXIC_RBT_BLACK :(p_tn)->color_lsv & 0x3)
-           
-#define SET_TN_COLOR(p_tn,color) \
-    do{\
-        (p_tn)->color_lsv  &= 0xfffffffc;\
-        (p_tn)->color_lsv  |= (color & 0x3);\
-    }while(0)
-   
-
-           
-#define GET_TN_LSV(p_tn)   \
-        ((p_tn)->color_lsv >> 2 )
-
-#define SET_TN_LSV(p_tn,list_val) \
-    do{\
-        (p_tn)->color_lsv &= 0x3;\
-        (p_tn)->color_lsv |= ((list_val) << 2); \
-    }while(0)
-
-
-/*init the rb node ,be careful init_color is red*/
-#define INIT_RBT_TN(p_tn,p_newkey) \
-    do{\
-        (p_tn)->p_key    = p_newkey; \
-        (p_tn)->color_lsv= 0; \
-        (p_tn)->p_left   = NULL; \
-        (p_tn)->p_right  = NULL; \
-        (p_tn)->p_parent = NULL; \
-        INIT_D_NODE(&((p_tn)->tn_ln),(p_tn));\
-    }while(0)
-
-ZXIC_RTN32 zxic_comm_rb_init(ZXIC_RB_CFG *p_rb_cfg,
-                       ZXIC_UINT32      total_num,
-                       ZXIC_UINT32      key_size,
-                       ZXIC_RB_CMPFUN cmpfun);
-
-
-ZXIC_RTN32 zxic_comm_rb_insert(ZXIC_RB_CFG *p_rb_cfg,
-                         ZXIC_VOID       *p_key,
-                         ZXIC_VOID       *out_val);
-
-ZXIC_RTN32 zxic_comm_rb_delete(ZXIC_RB_CFG *p_rb_cfg,
-                         ZXIC_VOID       *p_key,
-                         ZXIC_VOID       *out_val);
-
-ZXIC_RTN32 zxic_comm_rb_search(ZXIC_RB_CFG *p_rb_cfg,
-                         ZXIC_VOID       *p_key,
-                         ZXIC_VOID       *out_val);
-
-ZXIC_RTN32 zxic_comm_rb_destroy(ZXIC_RB_CFG *p_rb_cfg);
-
-ZXIC_RB_TN *zxic_comm_rb_get_1st_tn(ZXIC_RB_CFG *p_rb_cfg);
-
-ZXIC_RB_TN *zxic_comm_rb_get_last_tn(ZXIC_RB_CFG *p_rb_cfg);
-
-ZXIC_RTN32 zxic_comm_rb_get_1st_key(ZXIC_RB_CFG* p_rb_cfg, ZXIC_VOID *p_key_out);
-
-ZXIC_RTN32 zxic_comm_rb_get_last_key(ZXIC_RB_CFG*  p_rb_cfg, ZXIC_VOID *p_key_out);
-
-ZXIC_RTN32 zxic_comm_rb_insert_spec_index(ZXIC_RB_CFG *p_rb_cfg, ZXIC_VOID *p_key, ZXIC_UINT32 in_idx);
-
-
-#define ZXIC_RBT_RC_BASE               (0x1000)
-
-#define ZXIC_RBT_RC_UPDATE             (ZXIC_RBT_RC_BASE | 0x1)
-#define ZXIC_RBT_RC_SRHFAIL            (ZXIC_RBT_RC_BASE | 0x2)
-#define ZXIC_RBT_RC_FULL               (ZXIC_RBT_RC_BASE | 0x3)
-#define ZXIC_RBT_ISEMPTY_ERR           (ZXIC_RBT_RC_BASE | 0x4)
-#define ZXIC_RBT_PARA_INVALID          (ZXIC_RBT_RC_BASE | 0x5)
-
-#endif
-
+/*****************************************************************************
+ * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：   zxic_comm_rb_tree.h
+ * 文件标识：
+ * 内容摘要：
+ * 其它说明：
+ * 当前版本：
+ * 作    者：    ChenWei10088471
+ * 完成日期：
+ * 当前责任人-1：
+ * 当前责任人-2：
+ *
+ * DEPARTMENT       : ASIC_FPGA_R&D_Dept
+ * MANUAL_PERCENT   : 100%
+ *****************************************************************************/
+
+#ifndef _ZXIC_COMM_RB_TREE_H
+#define _ZXIC_COMM_RB_TREE_H
+
+#include "zxic_comm_double_link.h"
+#include "zxic_comm_liststack.h"
+
+#define ZXIC_RBT_RED (0x1)
+#define ZXIC_RBT_BLACK (0x2)
+#define ZXIC_RBT_MAX_DEPTH (128)
+
+typedef ZXIC_SINT32 (*ZXIC_RB_CMPFUN)(ZXIC_VOID *p_new, ZXIC_VOID *p_old,
+									  ZXIC_UINT32 keysize);
+
+typedef struct _rb_tn {
+	ZXIC_VOID *p_key;
+	ZXIC_UINT32
+	color_lsv; /*last 2 bits indicate color, bit2-31 if dynamic=0 indicate list val*/
+	struct _rb_tn *p_left;
+	struct _rb_tn *p_right;
+	struct _rb_tn *p_parent;
+	D_NODE tn_ln;
+} ZXIC_RB_TN;
+
+typedef struct _rb_cfg {
+	ZXIC_UINT32 key_size;
+	ZXIC_UINT32 is_dynamic; /* 1 - customer manage memory;0 - alloc all memory*/
+	ZXIC_RB_TN *p_root; /* rb tree root node */
+	D_HEAD tn_list;
+	ZXIC_RB_CMPFUN p_cmpfun;
+	ZXIC_LISTSTACK_MANGER *p_lsm; /* list stack manage*/
+	ZXIC_UINT8 *p_keybase;
+	ZXIC_RB_TN *p_tnbase;
+	ZXIC_UINT32 is_init;
+} ZXIC_RB_CFG;
+
+#define GET_TN_COLOR(p_tn) \
+	((p_tn == NULL) ? ZXIC_RBT_BLACK : (p_tn)->color_lsv & 0x3)
+
+#define SET_TN_COLOR(p_tn, color)           \
+	do {                                    \
+		(p_tn)->color_lsv &= 0xfffffffc;    \
+		(p_tn)->color_lsv |= (color & 0x3); \
+	} while (0)
+
+#define GET_TN_LSV(p_tn) ((p_tn)->color_lsv >> 2)
+
+#define SET_TN_LSV(p_tn, list_val)              \
+	do {                                        \
+		(p_tn)->color_lsv &= 0x3;               \
+		(p_tn)->color_lsv |= ((list_val) << 2); \
+	} while (0)
+
+/*init the rb node ,be careful init_color is red*/
+#define INIT_RBT_TN(p_tn, p_newkey)            \
+	do {                                       \
+		(p_tn)->p_key = p_newkey;              \
+		(p_tn)->color_lsv = 0;                 \
+		(p_tn)->p_left = NULL;                 \
+		(p_tn)->p_right = NULL;                \
+		(p_tn)->p_parent = NULL;               \
+		INIT_D_NODE(&((p_tn)->tn_ln), (p_tn)); \
+	} while (0)
+
+ZXIC_RTN32 zxic_comm_rb_init(ZXIC_RB_CFG *p_rb_cfg, ZXIC_UINT32 total_num,
+							 ZXIC_UINT32 key_size, ZXIC_RB_CMPFUN cmpfun);
+
+ZXIC_RTN32 zxic_comm_rb_insert(ZXIC_RB_CFG *p_rb_cfg, ZXIC_VOID *p_key,
+							   ZXIC_VOID *out_val);
+
+ZXIC_RTN32 zxic_comm_rb_delete(ZXIC_RB_CFG *p_rb_cfg, ZXIC_VOID *p_key,
+							   ZXIC_VOID *out_val);
+
+ZXIC_RTN32 zxic_comm_rb_search(ZXIC_RB_CFG *p_rb_cfg, ZXIC_VOID *p_key,
+							   ZXIC_VOID *out_val);
+
+ZXIC_RTN32 zxic_comm_rb_destroy(ZXIC_RB_CFG *p_rb_cfg);
+
+ZXIC_RB_TN *zxic_comm_rb_get_1st_tn(ZXIC_RB_CFG *p_rb_cfg);
+
+ZXIC_RB_TN *zxic_comm_rb_get_last_tn(ZXIC_RB_CFG *p_rb_cfg);
+
+ZXIC_RTN32 zxic_comm_rb_get_1st_key(ZXIC_RB_CFG *p_rb_cfg,
+									ZXIC_VOID *p_key_out);
+
+ZXIC_RTN32 zxic_comm_rb_get_last_key(ZXIC_RB_CFG *p_rb_cfg,
+									 ZXIC_VOID *p_key_out);
+
+ZXIC_RTN32 zxic_comm_rb_insert_spec_index(ZXIC_RB_CFG *p_rb_cfg,
+										  ZXIC_VOID *p_key, ZXIC_UINT32 in_idx);
+
+#define ZXIC_RBT_RC_BASE (0x1000)
+
+#define ZXIC_RBT_RC_UPDATE (ZXIC_RBT_RC_BASE | 0x1)
+#define ZXIC_RBT_RC_SRHFAIL (ZXIC_RBT_RC_BASE | 0x2)
+#define ZXIC_RBT_RC_FULL (ZXIC_RBT_RC_BASE | 0x3)
+#define ZXIC_RBT_ISEMPTY_ERR (ZXIC_RBT_RC_BASE | 0x4)
+#define ZXIC_RBT_PARA_INVALID (ZXIC_RBT_RC_BASE | 0x5)
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_socket.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_socket.h
index aff6ef34aa78ee48261ac36a2163e2785f6e173d..de84252ae6767144db4cc4be9983e0d3c4b04f9f 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_socket.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_socket.h
@@ -1,157 +1,139 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : zxic_comm_socket.h
-* 文件标识 : 
-* 内容摘要 : 
-* 其它说明 : 
-* 当前版本 : 
-* 作    者 : 王春雷
-* 完成日期 : 2014/02/08
-* DEPARTMENT: ASIC_FPGA_R&D_Dept 
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* 版 本 号:  
-* 修 改 人:  
-* 修改内容:  
-***************************************************************/
-
-#ifndef _ZXIC_COMM_SOCKET_H_
-#define _ZXIC_COMM_SOCKET_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef ZXIC_OS_WIN
-#include <winsock.h>
-typedef SOCKET                 ZXIC_SOCKET;
-
-#else
-#include <linux/socket.h>
-#include <linux/in.h>
-#include <linux/inet.h>
-#include <linux/tcp.h>
-typedef ZXIC_SINT32            ZXIC_SOCKET;
-#endif
-
-typedef struct sockaddr        SOCKADDR;
-typedef struct sockaddr_in     SOCKADDR_IN;
-
-
-#define ZXIC_SOCK_VALID             (0)
-#define ZXIC_SOCK_INVALID           (-1)
-#define ZXIC_SOCK_NUM_MAX           (16)
-
-#define ZXIC_SOCK_INADDR_ANY        (0x00000000)
-#define ZXIC_SOCK_INADDR_LOOPBACK   (0x7f000001)
-#define ZXIC_SOCK_INADDR_BROADCAST  (0xffffffff)
-#define ZXIC_SOCK_INADDR_NONE       (0xffffffff)
-
-/* socket domain */
-#define ZXIC_SOCK_AF_INET           AF_INET     /* internetwork: UDP, TCP, etc. */
-#define ZXIC_SOCK_AF_INET6          AF_INET6    /* Internetwork Version 6 */
-
-/* socket type */
-#define ZXIC_SOCK_STREAM            SOCK_STREAM     /* stream socket */
-#define ZXIC_SOCK_DGRAM             SOCK_DGRAM      /* datagram socket */
-#define ZXIC_SOCK_RAW               SOCK_RAW        /* raw-protocol interface */
-#define ZXIC_SOCK_RDM               SOCK_RDM        /* reliably-delivered message */
-#define ZXIC_SOCK_SEQPACKET         SOCK_SEQPACKET  /* sequenced packet stream */
-
-/* socket protocol */
-#define ZXIC_SOCK_IPPROTO_IP        IPPROTO_IP   /* dummy for IP */
-#define ZXIC_SOCK_IPPROTO_TCP       IPPROTO_TCP  /* tcp */
-#define ZXIC_SOCK_IPPROTO_UDP       IPPROTO_UDP  /* user datagram protocol */
-
-/* socket level */
-#define ZXIC_SOCK_SOL_SOCKET        SOL_SOCKET   /* options for socket level */
-
-/* socket OptName */
-#define ZXIC_SOCK_SO_DEBUG          SO_DEBUG          /* turn on debugging info recording */
-#define ZXIC_SOCK_SO_ACCEPTCONN     SO_ACCEPTCONN     /* socket has had listen() */
-#define ZXIC_SOCK_SO_REUSEADDR      SO_REUSEADDR      /* allow local address reuse */
-#define ZXIC_SOCK_SO_KEEPALIVE      SO_KEEPALIVE      /* keep connections alive */
-#define ZXIC_SOCK_SO_DONTROUTE      SO_DONTROUTE      /* just use interface addresses */
-#define ZXIC_SOCK_SO_BROADCAST      SO_BROADCAST      /* permit sending of broadcast msgs */
-#define ZXIC_SOCK_SO_USELOOPBACK    SO_USELOOPBACK    /* bypass hardware when possible */
-#define ZXIC_SOCK_SO_LINGER         SO_LINGER         /* linger on close if data present */
-#define ZXIC_SOCK_SO_OOBINLINE      SO_OOBINLINE      /* leave received OOB data in line */
-#define ZXIC_SOCK_SO_SNDBUF         SO_SNDBUF         /* send buffer size */
-#define ZXIC_SOCK_SO_RCVBUF         SO_RCVBUF         /* receive buffer size */
-#define ZXIC_SOCK_SO_SNDLOWAT       SO_SNDLOWAT       /* send low-water mark */
-#define ZXIC_SOCK_SO_RCVLOWAT       SO_RCVLOWAT       /* receive low-water mark */
-#define ZXIC_SOCK_SO_SNDTIMEO       SO_SNDTIMEO       /* send timeout */
-#define ZXIC_SOCK_SO_RCVTIMEO       SO_RCVTIMEO       /* receive timeout */
-#define ZXIC_SOCK_SO_ERROR          SO_ERROR          /* get error status and clear */
-#define ZXIC_SOCK_SO_TYPE           SO_TYPE           /* get socket type */
-
-
-#define ZXIC_TCP_OP_NODELAY         TCP_NODELAY
-
-typedef struct zxic_comm_sock_addr_t
-{
-    ZXIC_UINT32  family;
-    ZXIC_UINT32  port;
-    ZXIC_UINT32   addr;
-}ZXIC_SOCK_ADDR_T;
-
-typedef struct zxic_comm_sock_mgr_t
-{
-    ZXIC_UINT32     is_init;
-    ZXIC_UINT32     count;
-    ZXIC_SOCKET     socks[ZXIC_SOCK_NUM_MAX];
-    ZXIC_UINT8      sock_vld[ZXIC_SOCK_NUM_MAX];
-    ZXIC_MUTEX_T    mutex;
-}ZXIC_SOCK_MGR_T;
-
-/* API */
-ZXIC_RTN32 zxic_comm_sock_init(ZXIC_VOID);
-ZXIC_RTN32 zxic_comm_sock_service_start(ZXIC_VOID);
-ZXIC_RTN32 zxic_comm_sock_service_close(ZXIC_VOID);
-ZXIC_RTN32 zxic_comm_sock_create(ZXIC_SOCKET  *p_socket, 
-                            ZXIC_SINT32     domain, 
-                            ZXIC_SINT32     type, 
-                            ZXIC_SINT32     protocol);
-
-ZXIC_RTN32 zxic_comm_sock_set_opt(ZXIC_SOCKET  sock, 
-                             ZXIC_SINT32     level,
-                             ZXIC_SINT32     opt_name,
-                             ZXIC_VOID        *p_opt_val,
-                             ZXIC_UINT32     opt_len);
-
-ZXIC_RTN32 zxic_comm_sock_get_opt(ZXIC_SOCKET  sock, 
-                             ZXIC_SINT32     level,
-                             ZXIC_SINT32     opt_name,
-                             ZXIC_VOID        *p_opt_val,
-                             ZXIC_UINT32     *p_opt_len);
-
-ZXIC_RTN32 zxic_comm_sock_bind_listen(ZXIC_SOCKET       sock,
-                                 ZXIC_SOCK_ADDR_T  *p_sock_addr);
-
-ZXIC_RTN32 zxic_comm_sock_accpet(ZXIC_SOCKET       listen_sock,
-                            ZXIC_SOCKET       *p_cnnt_sock,
-                            ZXIC_SOCK_ADDR_T  *p_sock_addr);
-
-ZXIC_RTN32 zxic_comm_sock_connect(ZXIC_SOCKET       sock,
-                             ZXIC_SOCK_ADDR_T  *p_sock_addr);
-
-ZXIC_SINT32 zxic_comm_sock_send(ZXIC_SOCKET  sock,
-                           ZXIC_CHAR        *p_buf,
-                           ZXIC_SINT32     len,
-                           ZXIC_SINT32     flag);
-
-ZXIC_SINT32 zxic_comm_sock_recv(ZXIC_SOCKET  sock,
-                           ZXIC_CHAR        *p_buf,
-                           ZXIC_SINT32     len,
-                           ZXIC_SINT32     flag);
-
-ZXIC_RTN32 zxic_comm_sock_close(ZXIC_SOCKET sock);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : zxic_comm_socket.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2014/02/08
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#ifndef _ZXIC_COMM_SOCKET_H_
+#define _ZXIC_COMM_SOCKET_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/socket.h>
+#include <linux/in.h>
+#include <linux/inet.h>
+#include <linux/tcp.h>
+typedef ZXIC_SINT32 ZXIC_SOCKET;
+
+typedef struct sockaddr SOCKADDR;
+typedef struct sockaddr_in SOCKADDR_IN;
+
+#define ZXIC_SOCK_VALID (0)
+#define ZXIC_SOCK_INVALID (-1)
+#define ZXIC_SOCK_NUM_MAX (16)
+
+#define ZXIC_SOCK_INADDR_ANY (0x00000000)
+#define ZXIC_SOCK_INADDR_LOOPBACK (0x7f000001)
+#define ZXIC_SOCK_INADDR_BROADCAST (0xffffffff)
+#define ZXIC_SOCK_INADDR_NONE (0xffffffff)
+
+/* socket domain */
+#define ZXIC_SOCK_AF_INET AF_INET /* internetwork: UDP, TCP, etc. */
+#define ZXIC_SOCK_AF_INET6 AF_INET6 /* Internetwork Version 6 */
+
+/* socket type */
+#define ZXIC_SOCK_STREAM SOCK_STREAM /* stream socket */
+#define ZXIC_SOCK_DGRAM SOCK_DGRAM /* datagram socket */
+#define ZXIC_SOCK_RAW SOCK_RAW /* raw-protocol interface */
+#define ZXIC_SOCK_RDM SOCK_RDM /* reliably-delivered message */
+#define ZXIC_SOCK_SEQPACKET SOCK_SEQPACKET /* sequenced packet stream */
+
+/* socket protocol */
+#define ZXIC_SOCK_IPPROTO_IP IPPROTO_IP /* dummy for IP */
+#define ZXIC_SOCK_IPPROTO_TCP IPPROTO_TCP /* tcp */
+#define ZXIC_SOCK_IPPROTO_UDP IPPROTO_UDP /* user datagram protocol */
+
+/* socket level */
+#define ZXIC_SOCK_SOL_SOCKET SOL_SOCKET /* options for socket level */
+
+/* socket OptName */
+#define ZXIC_SOCK_SO_DEBUG SO_DEBUG /* turn on debugging info recording */
+#define ZXIC_SOCK_SO_ACCEPTCONN SO_ACCEPTCONN /* socket has had listen() */
+#define ZXIC_SOCK_SO_REUSEADDR SO_REUSEADDR /* allow local address reuse */
+#define ZXIC_SOCK_SO_KEEPALIVE SO_KEEPALIVE /* keep connections alive */
+#define ZXIC_SOCK_SO_DONTROUTE SO_DONTROUTE /* just use interface addresses */
+#define ZXIC_SOCK_SO_BROADCAST \
+	SO_BROADCAST /* permit sending of broadcast msgs */
+#define ZXIC_SOCK_SO_USELOOPBACK \
+	SO_USELOOPBACK /* bypass hardware when possible */
+#define ZXIC_SOCK_SO_LINGER SO_LINGER /* linger on close if data present */
+#define ZXIC_SOCK_SO_OOBINLINE \
+	SO_OOBINLINE /* leave received OOB data in line */
+#define ZXIC_SOCK_SO_SNDBUF SO_SNDBUF /* send buffer size */
+#define ZXIC_SOCK_SO_RCVBUF SO_RCVBUF /* receive buffer size */
+#define ZXIC_SOCK_SO_SNDLOWAT SO_SNDLOWAT /* send low-water mark */
+#define ZXIC_SOCK_SO_RCVLOWAT SO_RCVLOWAT /* receive low-water mark */
+#define ZXIC_SOCK_SO_SNDTIMEO SO_SNDTIMEO /* send timeout */
+#define ZXIC_SOCK_SO_RCVTIMEO SO_RCVTIMEO /* receive timeout */
+#define ZXIC_SOCK_SO_ERROR SO_ERROR /* get error status and clear */
+#define ZXIC_SOCK_SO_TYPE SO_TYPE /* get socket type */
+
+#define ZXIC_TCP_OP_NODELAY TCP_NODELAY
+
+typedef struct zxic_comm_sock_addr_t {
+	ZXIC_UINT32 family;
+	ZXIC_UINT32 port;
+	ZXIC_UINT32 addr;
+} ZXIC_SOCK_ADDR_T;
+
+typedef struct zxic_comm_sock_mgr_t {
+	ZXIC_UINT32 is_init;
+	ZXIC_UINT32 count;
+	ZXIC_SOCKET socks[ZXIC_SOCK_NUM_MAX];
+	ZXIC_UINT8 sock_vld[ZXIC_SOCK_NUM_MAX];
+	ZXIC_MUTEX_T mutex;
+} ZXIC_SOCK_MGR_T;
+
+/* API */
+ZXIC_RTN32 zxic_comm_sock_init(ZXIC_VOID);
+ZXIC_RTN32 zxic_comm_sock_service_start(ZXIC_VOID);
+ZXIC_RTN32 zxic_comm_sock_service_close(ZXIC_VOID);
+ZXIC_RTN32 zxic_comm_sock_create(ZXIC_SOCKET *p_socket, ZXIC_SINT32 domain,
+								 ZXIC_SINT32 type, ZXIC_SINT32 protocol);
+
+ZXIC_RTN32 zxic_comm_sock_set_opt(ZXIC_SOCKET sock, ZXIC_SINT32 level,
+								  ZXIC_SINT32 opt_name, ZXIC_VOID *p_opt_val,
+								  ZXIC_UINT32 opt_len);
+
+ZXIC_RTN32 zxic_comm_sock_get_opt(ZXIC_SOCKET sock, ZXIC_SINT32 level,
+								  ZXIC_SINT32 opt_name, ZXIC_VOID *p_opt_val,
+								  ZXIC_UINT32 *p_opt_len);
+
+ZXIC_RTN32 zxic_comm_sock_bind_listen(ZXIC_SOCKET sock,
+									  ZXIC_SOCK_ADDR_T *p_sock_addr);
+
+ZXIC_RTN32 zxic_comm_sock_accpet(ZXIC_SOCKET listen_sock,
+								 ZXIC_SOCKET *p_cnnt_sock,
+								 ZXIC_SOCK_ADDR_T *p_sock_addr);
+
+ZXIC_RTN32 zxic_comm_sock_connect(ZXIC_SOCKET sock,
+								  ZXIC_SOCK_ADDR_T *p_sock_addr);
+
+ZXIC_SINT32 zxic_comm_sock_send(ZXIC_SOCKET sock, ZXIC_CHAR *p_buf,
+								ZXIC_SINT32 len, ZXIC_SINT32 flag);
+
+ZXIC_SINT32 zxic_comm_sock_recv(ZXIC_SOCKET sock, ZXIC_CHAR *p_buf,
+								ZXIC_SINT32 len, ZXIC_SINT32 flag);
+
+ZXIC_RTN32 zxic_comm_sock_close(ZXIC_SOCKET sock);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_thread.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_thread.h
index f07d090c82c1f17b39e3a669e2d6385c5cc95a36..82f1fa13bf39b777a69322ca220d5a09902d4e89 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_thread.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_comm_thread.h
@@ -1,95 +1,84 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : zxic_comm_thread.h
-* 文件标识 : 
-* 内容摘要 : 
-* 其它说明 : 
-* 当前版本 : 
-* 作    者 : 王春雷
-* 完成日期 : 2014/02/08
-* DEPARTMENT: ASIC_FPGA_R&D_Dept 
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* 版 本 号:  
-* 修 改 人:  
-* 修改内容:  
-***************************************************************/
-
-#ifndef _ZXIC_COMM_THREAD_H_
-#define _ZXIC_COMM_THREAD_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef ZXIC_OS_LINUX
-#include <linux/sched.h>
-#include <linux/limits.h>
-#endif
-
-#define THREAD_NAME_MAX                 (64)
-#define ZXIC_THREAD_TIME_INFINITE       (0xFFFFFFFF)  /* Infinite timeout */
-
-typedef ZXIC_VOID* (*ZXIC_THREAD_FUNC) (ZXIC_VOID*);
-
-/* Thread ID */
-typedef struct zxic_comm_thread_id_t
-{
-#ifdef ZXIC_OS_WIN
-    HANDLE  id;
-#else
-    //pthread_t id;
-    int id;
-#endif
-}ZXIC_THREAD_ID_T;
-
-/* Thread CreateFlag */
-#define ZXIC_THREAD_FLAG_DETACH             (1 << 0)
-#define ZXIC_THREAD_FLAG_EXPLICIT_SCHED     (1 << 1)
-
-typedef struct zxic_comm_thread_info_t
-{
-    ZXIC_CHAR         name[THREAD_NAME_MAX];  /* 线程名   */
-    ZXIC_UINT32       priority;               /* 优先级   */
-    ZXIC_UINT32       stack_size;             /* 初始栈大小，以字节为单位 */
-    ZXIC_UINT32       create_flag;            /* 线程标志 */
-    ZXIC_THREAD_ID_T  id;                     /* 线程ID   */
-    ZXIC_THREAD_FUNC  thread_func;            /* 线程函数 */
-    ZXIC_VOID*        p_arg;                  /* 线程入参 */
-    ZXIC_UINT32       is_valid;               /* 是否有效 */
-}ZXIC_THREAD_INFO_T;
-
-/* API */
-ZXIC_RTN32 zxic_comm_thread_info_init(ZXIC_VOID);
-ZXIC_RTN32 zxic_comm_thread_info_add(ZXIC_THREAD_ID_T*     p_thread_id,
-                                     ZXIC_CONST ZXIC_CHAR* p_name,
-                                     ZXIC_UINT32           priority,
-                                     ZXIC_UINT32           stack_size,
-                                     ZXIC_UINT32           create_flag,
-                                     ZXIC_THREAD_FUNC      p_thread_func,
-                                     ZXIC_VOID*            p_arg,
-                                     ZXIC_UINT32*          p_info_index);
-ZXIC_RTN32 zxic_comm_thread_info_del(ZXIC_THREAD_ID_T *p_thread_id);
-ZXIC_RTN32 zxic_comm_thread_info_print(ZXIC_VOID);
-
-ZXIC_RTN32 zxic_comm_thread_create(ZXIC_CONST ZXIC_CHAR *p_name, 
-                              ZXIC_UINT32            priority,
-                              ZXIC_UINT32            stack_size,
-                              ZXIC_UINT32            create_flag,
-                              ZXIC_THREAD_FUNC       thread_func,
-                              ZXIC_VOID              *p_arg,
-                              ZXIC_THREAD_ID_T       *p_thread_id);
-
-ZXIC_RTN32 zxic_comm_thread_exit(ZXIC_VOID);
-ZXIC_RTN32 zxic_comm_thread_wait(ZXIC_THREAD_ID_T  *p_thread_id, ZXIC_DWORD wait_time);
-ZXIC_RTN32 zxic_comm_thread_close_handle(ZXIC_THREAD_ID_T *p_thread_id);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif
-
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : zxic_comm_thread.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2014/02/08
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#ifndef _ZXIC_COMM_THREAD_H_
+#define _ZXIC_COMM_THREAD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef ZXIC_OS_LINUX
+#include <linux/sched.h>
+#include <linux/limits.h>
+#endif
+
+#define THREAD_NAME_MAX (64)
+#define ZXIC_THREAD_TIME_INFINITE (0xFFFFFFFF) /* Infinite timeout */
+
+typedef ZXIC_VOID *(*ZXIC_THREAD_FUNC)(ZXIC_VOID *);
+
+/* Thread ID */
+typedef struct zxic_comm_thread_id_t {
+	int id;
+} ZXIC_THREAD_ID_T;
+
+/* Thread CreateFlag */
+#define ZXIC_THREAD_FLAG_DETACH (1 << 0)
+#define ZXIC_THREAD_FLAG_EXPLICIT_SCHED (1 << 1)
+
+typedef struct zxic_comm_thread_info_t {
+	ZXIC_CHAR name[THREAD_NAME_MAX]; /* 线程名   */
+	ZXIC_UINT32 priority; /* 优先级   */
+	ZXIC_UINT32 stack_size; /* 初始栈大小，以字节为单位 */
+	ZXIC_UINT32 create_flag; /* 线程标志 */
+	ZXIC_THREAD_ID_T id; /* 线程ID   */
+	ZXIC_THREAD_FUNC thread_func; /* 线程函数 */
+	ZXIC_VOID *p_arg; /* 线程入参 */
+	ZXIC_UINT32 is_valid; /* 是否有效 */
+} ZXIC_THREAD_INFO_T;
+
+/* API */
+ZXIC_RTN32 zxic_comm_thread_info_init(ZXIC_VOID);
+ZXIC_RTN32
+zxic_comm_thread_info_add(ZXIC_THREAD_ID_T *p_thread_id,
+						  ZXIC_CONST ZXIC_CHAR *p_name, ZXIC_UINT32 priority,
+						  ZXIC_UINT32 stack_size, ZXIC_UINT32 create_flag,
+						  ZXIC_THREAD_FUNC p_thread_func, ZXIC_VOID *p_arg,
+						  ZXIC_UINT32 *p_info_index);
+ZXIC_RTN32 zxic_comm_thread_info_del(ZXIC_THREAD_ID_T *p_thread_id);
+ZXIC_RTN32 zxic_comm_thread_info_print(ZXIC_VOID);
+
+ZXIC_RTN32 zxic_comm_thread_create(ZXIC_CONST ZXIC_CHAR *p_name,
+								   ZXIC_UINT32 priority, ZXIC_UINT32 stack_size,
+								   ZXIC_UINT32 create_flag,
+								   ZXIC_THREAD_FUNC thread_func,
+								   ZXIC_VOID *p_arg,
+								   ZXIC_THREAD_ID_T *p_thread_id);
+
+ZXIC_RTN32 zxic_comm_thread_exit(ZXIC_VOID);
+ZXIC_RTN32 zxic_comm_thread_wait(ZXIC_THREAD_ID_T *p_thread_id,
+								 ZXIC_DWORD wait_time);
+ZXIC_RTN32 zxic_comm_thread_close_handle(ZXIC_THREAD_ID_T *p_thread_id);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_common.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_common.h
index 59ea70641b14f54c678532d8a0ca531bf769fd63..f29e8881eaff764b97e8e0e8efb9f48b2cac1595 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_common.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_common.h
@@ -1,2674 +1,3104 @@
-/**************************************************************
-* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司
-* 文件名称      :       zxic_common.h
-* 文件标识      :
-* 内容摘要      :       大部分的项目,只需要感知这一个头文件即可,
-                    其包括了变量定义/打印/日志/参数校验/互斥锁/bit流拼接等常用定义和功能
-* 其它说明      :       编译宏：ZXIC_OS_WIN/ZXIC_RELEASE/MACRO_CPU64
-* 当前版本      :
-* 作    者    :
-* 完成日期      :       2020/07/20
-* DEPARTMENT:       有线开发四部-系统软件团队
-* MANUAL_PERCENT:   100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-#ifndef __ZXIC_COMMON_H__
-#define __ZXIC_COMMON_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-编译宏说明
-ZXIC_OS_WIN :若不导入该宏,则默认为 ZXIC_OS_LINUX
-ZXIC_RELEASE:若不导入该宏,则默认为 ZXIC_DEBUG
-MACRO_CPU64 :若不导入该宏,则默认为32位操作系统
-*/
-
-#include "zxic_private_top.h"
-#include "zxic_private.h"
-//#include <ctype.h>
-//#include <stdlib.h>
-//#include <stdio.h>
-#include <linux/stddef.h>
-#include <linux/string.h>
-//#include <errno.h>
-//#include <assert.h>
-#include <stdarg.h>
-//#include <math.h>
-#include <linux/stat.h>
-//#include <stdint.h>
-
-#ifdef ZXIC_OS_WIN              /* 编译宏导入 */
-#include <Windows.h>
-#include <time.h>
-#include <direct.h>
-#include <io.h>
-#pragma warning (disable:4996)
-#else
-#include <linux/unistd.h>
-#include <linux/types.h>
-#include <linux/socket.h>
-//#include <select.h>
-#include <linux/time.h>
-#include <linux/wait.h>
-#include <linux/kthread.h>
-#include <linux/fcntl.h>
-#include <linux/semaphore.h>
-#include <linux/slab.h>
-#include <linux/fs.h>
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/printk.h>
-#include <linux/dma-mapping.h>
-#endif
-
-#if ZXIC_REAL("数据类型定义")
-/* 无符号整数 */
-#define ZXIC_UINT8              unsigned char
-#define ZXIC_UINT16             unsigned short
-
-#ifndef ZXIC_UINT32
-#define ZXIC_UINT32             unsigned int
-#endif
-
-#ifndef ZXIC_UINT64
-#define ZXIC_UINT64             unsigned long long
-#endif
-#define ZXIC_DWORD              unsigned long      /* 慎用,注意:WIN系统:32bits       LINUX系统:64bits */
-#define ZXIC_SIZE_T             size_t             /* 32位系统:uint32 64位系统:uint64 */
-
-/* 有符号整数 */
-#define ZXIC_CHAR               char               /* char默认为unsigned还是signed取决于编译器,定义字符可用 */
-#define ZXIC_SINT8              signed char
-#define ZXIC_SINT16             signed short
-
-#ifndef ZXIC_SINT32
-#define ZXIC_SINT32             signed int
-#endif
-
-#ifndef ZXIC_SINT64
-#define ZXIC_SINT64             signed long long  
-#endif
-
-#define ZXIC_SDWORD             long
-
-/* 浮点数 */
-//#define ZXIC_FLOAT              float
-//#define ZXIC_DOUBLE             double
-//#define ZXIC_LDOUBLE            long double
-#define ZXIC_FLOAT              int
-#define ZXIC_DOUBLE             long
-#define ZXIC_LDOUBLE            long long
-
-/* 文件类型 */
-typedef struct file             ZXIC_FILE;
-
-/*  */
-#define ZXIC_VOL                volatile
-#define ZXIC_VOID               void
-#define ZXIC_CONST              const
-#define ZXIC_RTN32              ZXIC_UINT32
-
-#ifdef MACRO_CPU64              /* 64位系统编译宏导入,慎重修改 */
-#define ZXIC_ADDR_T             ZXIC_UINT64
-#define ZXIC_SIZEOF(x)          (sizeof(x) & 0xFFFFFFFFU)  /* 在64位环境下，sizeof的长度是64b */
-#define ZXIC_SIZEOF_T(x)        ((ZXIC_UINT32)(sizeof(x) & 0xFFFFFFFF))
-
-#else
-#define ZXIC_ADDR_T             ZXIC_UINT32
-#define ZXIC_SIZEOF(x)          (sizeof(x))
-#define ZXIC_SIZEOF_T(x)        (sizeof(x))
-#endif
-
-/* 特殊变量 */
-#define ZXIC_NULL               (0)
-#define ZXIC_OK                 (0U)               /* 后面加U,防止32位系统64位系统常量的默认长度不一致 */
-#define ZXIC_ERR                (1U)
-#define ZXIC_TRUE               (1U)
-#define ZXIC_FALSE              (0U)
-#define ZXIC_UINT8_MAX          (0xFFU)
-#define ZXIC_UINT32_MAX         (0xFFFFFFFFU)
-#define ZXIC_ULONG_MAX          (0xFFFFFFFFFFFFFFFFUL)
-#define ZXIC_SINT_MAX           (0x7FFFFFFF)
-#define ZXIC_SINT_MIN           (-ZXIC_SINT_MAX - 1)
-
-
-#define ZXIC_UINT64_MASK        (0xFFFFFFFFFFFFFFFFULL)
-#define ZXIC_UINT32_MASK        (0xFFFFFFFFU)
-#define ZXIC_UINT16_MASK        (0xFFFFU)
-#define ZXIC_UINT8_MASK         (0xFFU)
-#endif  /* END 数据类型定义 */
-
-#if ZXIC_REAL("宏函数定义")
-#define ZXIC_COMM_MEMCMP             ic_comm_memcmp
-#define ZXIC_COMM_MEMSET             memset
-#define ZXIC_COMM_MEMMOVE            memmove
-#define ZXIC_COMM_MEMSET_S           ic_comm_memset_s
-#define ZXIC_COMM_MEMCPY             ic_comm_memcpy
-#define ZXIC_COMM_MEMCPY_S           ic_comm_memcpy_s
-#define ZXIC_COMM_STRLEN             strlen
-#define ZXIC_COMM_STRNLEN            strnlen
-#define ZXIC_COMM_STRNLEN_S          ic_comm_strnlen_s
-#define ZXIC_COMM_STRCPY             strcpy
-#define ZXIC_COMM_STRCPY_S           ic_comm_strcpy_s
-#define ZXIC_COMM_STRNCPY            strncpy
-#define ZXIC_COMM_STRNCPY_S          ic_comm_strncpy_s
-#define ZXIC_COMM_STRCMP             strcmp
-#define ZXIC_COMM_STRNCMP            ic_comm_strncmp
-#define ZXIC_COMM_STRTOK             strtok
-#define ZXIC_COMM_STRTOK_S           ic_comm_strtok_s
-#define ZXIC_COMM_STRCAT_S           ic_comm_strcat_s
-#define ZXIC_COMM_STRNCAT_S          ic_comm_strncat_s
-
-//#define ZXIC_COMM_FOPEN              fopen
-#define ZXIC_COMM_FOPEN              filp_open
-//#define ZXIC_COMM_FCLOSE             fclose
-#define ZXIC_COMM_FCLOSE(a)          filp_close(a,NULL)
-#define ZXIC_COMM_FGETS              fgets
-#define ZXIC_COMM_FPUTS              fputs
-#define ZXIC_COMM_FREAD              fread
-
-// #define ZXIC_COMM_FPRINTF            fprintf
-// #define ZXIC_COMM_FPRINTF(a,b,c)     printk(b,c)      
-#define ZXIC_COMM_SSCANF             ic_comm_sscanf
-#define ZXIC_COMM_FSCANF             (void)fscanf
-#define ZXIC_COMM_SNPRINTF_S         ic_comm_snprintf_s
-#define ZXIC_COMM_VSNPRINTF_S        ic_comm_vsnprintf_s
-
-#define ZXIC_COMM_TIME               time
-#define ZXIC_COMM_ATOI               atoi
-
-#ifdef ZXIC_OS_WIN
-#define ZXIC_COMM_ACCESS             _access
-#define ZXIC_COMM_SNPRINTF           _snprintf
-#define ZXIC_COMM_VSNPRINTF          _vsnprintf
-#define ZXIC_COMM_GETPID             _getpid
-#else
-#define ZXIC_COMM_ACCESS              kern_path
-/*#define ZXIC_COMM_SNPRINTF           snprintf*/
-#define ZXIC_COMM_SNPRINTF(a,b,c...)    __snprintf_chk(a,b,0,b,c)
-#define ZXIC_COMM_VSNPRINTF          vsnprintf
-#define ZXIC_COMM_GETPID             getpid
-#endif
-
-#ifdef MACRO_CPU64                   /* 64位系统编译宏导入,慎重修改 */
-#define ZXIC_COMM_PTR_TO_VAL(p)      ((ZXIC_UINT64)(p))
-#define ZXIC_COMM_VAL_TO_PTR(v)      ((ZXIC_VOID *)((ZXIC_UINT64)(v)))
-#define ZXIC_SSIZE_T   ZXIC_SINT64
-#else
-#define ZXIC_COMM_PTR_TO_VAL(p)      ((ZXIC_UINT32)(p))
-#define ZXIC_COMM_VAL_TO_PTR(v)      ((ZXIC_VOID *)(long)((ZXIC_UINT32)(v)))
-#define ZXIC_SSIZE_T   ZXIC_SINT32
-
-#endif
-
-#ifdef ZXIC_OS_WIN
-#define ZXIC_COMM_STRCASECMP        stricmp
-#else
-#define ZXIC_COMM_STRCASECMP        strcasecmp
-#endif
-
-#define ZXIC_COMM_FFLUSH            (ZXIC_VOID)fflush
-#define ZXIC_COMM_SPRINTF           (ZXIC_VOID)sprintf
-
-
-
-#ifdef ZXIC_RELEASE                   /* 编译宏控制,默认编译为DEBUG版本 */
-#define ZXIC_COMM_ASSERT(x)
-#else
-    #ifdef ZXIC_FOR_FUZZER
-        #define ZXIC_COMM_ASSERT(x)
-    #else
-        #define ZXIC_COMM_ASSERT(x)
-    #endif
-#endif
-
-#endif  /* END 宏函数定义 */
-
-#define ZXIC_COMM_MEMORY_MAX_B_SIZE (200 * 1024 * 1024) /* 200M */
-#define ZXIC_COMM_STRNLEN_MAX           (0xffffffff)
-
-#if ZXIC_REAL("打印-print")
-#if ZXIC_REAL("开关")
-ZXIC_VOID  zxic_comm_set_print_en   (ZXIC_UINT32 enable);
-ZXIC_RTN32 zxic_comm_get_print_en   (ZXIC_VOID);
-ZXIC_VOID  zxic_comm_set_print_level(ZXIC_TRACE_LEVEL debug_level);
-ZXIC_RTN32 zxic_comm_get_print_level(ZXIC_VOID);
-#endif
-#if ZXIC_REAL("功能")
-ZXIC_VOID ZXIC_COMM_PRINT(ZXIC_CONST ZXIC_CHAR *format, ...);
-ZXIC_VOID ZXIC_COMM_TRACE_ERROR(ZXIC_CONST ZXIC_CHAR *format, ...);
-ZXIC_VOID ZXIC_COMM_TRACE_INFO(ZXIC_CONST ZXIC_CHAR *format, ...);
-ZXIC_VOID ZXIC_COMM_TRACE_DEBUG(ZXIC_CONST ZXIC_CHAR *format, ...);
-ZXIC_VOID ZXIC_COMM_TRACE_ALL(ZXIC_CONST ZXIC_CHAR *format, ...);
-
-ZXIC_VOID ZXIC_COMM_TRACE_DEV_ERROR(ZXIC_UINT32 dev_id, ZXIC_CONST ZXIC_CHAR *format, ...);
-ZXIC_VOID ZXIC_COMM_TRACE_DEV_INFO(ZXIC_UINT32 dev_id, ZXIC_CONST ZXIC_CHAR *format, ...);
-ZXIC_VOID ZXIC_COMM_TRACE_DEV_DEBUG(ZXIC_UINT32 dev_id,ZXIC_CONST ZXIC_CHAR *format, ...);
-ZXIC_VOID ZXIC_COMM_TRACE_DEV_ALL(ZXIC_UINT32 dev_id, ZXIC_CONST ZXIC_CHAR *format, ...);
-
-ZXIC_VOID ZXIC_COMM_DBGCNT64_PRINT       (ZXIC_CONST ZXIC_CHAR * name, ZXIC_UINT64 value);
-ZXIC_VOID ZXIC_COMM_DBGCNT32_PRINT       (ZXIC_CONST ZXIC_CHAR * name, ZXIC_UINT32 value);
-ZXIC_VOID ZXIC_COMM_DBGCNT32_PAR_PRINT   (ZXIC_CONST ZXIC_CHAR * name, ZXIC_UINT32 parm, ZXIC_UINT32 value);
-
-#endif
-#endif
-
-#if ZXIC_REAL("互斥锁")
-ZXIC_RTN32 zxic_comm_mutex_create (ZXIC_MUTEX_T *p_mutex);
-ZXIC_RTN32 zxic_comm_mutex_lock   (ZXIC_MUTEX_T *p_mutex);
-ZXIC_RTN32 zxic_comm_mutex_unlock (ZXIC_MUTEX_T *p_mutex);
-ZXIC_RTN32 zxic_comm_mutex_destroy(ZXIC_MUTEX_T *p_mutex);
-#endif
-
-#if ZXIC_REAL("信号量")
-ZXIC_RTN32 zxic_comm_sem_create(ZXIC_SEM_T *p_sem, ZXIC_SINT32 share, ZXIC_SINT32 IniCount, ZXIC_SINT32 MaxCount);
-ZXIC_RTN32 zxic_comm_sem_release(ZXIC_SEM_T *p_sem);
-ZXIC_RTN32 zxic_comm_sem_wait(ZXIC_SEM_T *p_sem);
-#endif
-
-#if ZXIC_REAL("参数检查")
-
-#if ZXIC_REAL("NO DEV_ID & ASSERT")
-#define ZXIC_COMM_CHECK_RC(rc,becall)\
-    do{\
-        if(ZXIC_OK != rc)\
-        {\
-           ZXIC_COMM_TRACE_ERROR("\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-           ZXIC_COMM_ASSERT(0);\
-           return rc;\
-        }\
-    }while(0)
-             
-#define ZXIC_COMM_CHECK_RC_MEMORY_FREE(rc, becall, ptr)\
-    do{\
-         if (ZXIC_OK != rc)\
-         {\
-            ZXIC_COMM_TRACE_ERROR("\n ZXICP  %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\
-            ZXIC_COMM_FREE(ptr);\
-            ZXIC_COMM_ASSERT(0);\
-            return rc;\
-         }\
-    } while(0)
-
-#define ZXIC_COMM_CHECK_POINT(point)\
-    do{\
-       if(ZXIC_NULL == (point))\
-       {\
-          ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-          ZXIC_COMM_ASSERT(0);\
-          return ZXIC_PAR_CHK_POINT_NULL;\
-       }\
-    }while(0)
-    
-#define ZXIC_COMM_CHECK_POINT_MEMORY_FREE(point, ptr)\
-   do{\
-      if(ZXIC_NULL == (point))\
-      {\
-         ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-         ZXIC_COMM_FREE(ptr);\
-         ZXIC_COMM_ASSERT(0);\
-         return ZXIC_PAR_CHK_POINT_NULL;\
-      }\
-   }while(0)
-#define ZXIC_COMM_CHECK_POINT_EMEMORY_FREE2PTR(point, ptr0, ptr1)\
-   do{\
-      if(ZXIC_NULL == (point))\
-      {\
-         ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-         ZXIC_COMM_FREE(ptr0);\
-         ZXIC_COMM_FREE(ptr1);\
-         ZXIC_COMM_ASSERT(0);\
-         return ZXIC_PAR_CHK_POINT_NULL;\
-      }\
-   }while(0)
-#define ZXIC_COMM_CHECK_POINT_RETURN_NULL(point)\
-    do{\
-       if(ZXIC_NULL == (point))\
-       {\
-          ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-          ZXIC_COMM_ASSERT(0);\
-          return ZXIC_NULL;\
-       }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_INDEX(val,min,max)\
-    do{\
-        if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-        else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_RANGE;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_EQUAL(val,equal)\
-    do{\
-        if(val == equal)\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [equal=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, equal, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_EQUAL_RETURN_OK(val,equal)\
-    do{\
-        if(val == equal)\
-        {\
-            return ZXIC_OK;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_NOT_EQUAL(val,equal)\
-    do{\
-        if(val != equal)\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [equal=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, equal, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_UPPER(val,max)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)    
-#define ZXIC_COMM_CHECK_INDEX_LOWER(val,min)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_BOTH(val,min,max)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_UPPER_MEMORY_FREE(val,max,ptr)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0) 
-#define ZXIC_COMM_CHECK_INDEX_LOWER_MEMORY_FREE(val,min,ptr)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_BOTH_MEMORY_FREE(val,min,max,ptr)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_MEMORY_FREE(val0,val1,ptr)\
-    do{\
-        if((ZXIC_UINT32_MAX - (val0)) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)  
-
-#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(val0,val1)\
-    do{\
-        if((ZXIC_UINT32_MAX - (val0)) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)  
-
-
-#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_64(val0,val1)\
-do{\
-    if((ZXIC_ULONG_MAX - (val0)) < (val1))\
-    {\
-        ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-        ZXIC_COMM_ASSERT(0);\
-        return ZXIC_PAR_CHK_INVALID_INDEX;\
-    }\
-}while(0)  
-
-#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_UNLOCK(val0, val1, mutex)\
-    do{\
-        if((ZXIC_UINT32_MAX - (val0)) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            if(0 != zxic_comm_mutex_unlock(mutex))\
-            {\
-                ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-            }\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(val0,val1)\
-    do{\
-        if((val0) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_64(val0,val1)\
-do{\
-    if((val0) < (val1))\
-    {\
-        ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-        ZXIC_COMM_ASSERT(0);\
-        return ZXIC_PAR_CHK_INVALID_INDEX;\
-    }\
-}while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_UNLOCK(val0, val1, mutex)\
-do{\
-if((val0) < (val1))\
-{\
-    ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-    if(0 != zxic_comm_mutex_unlock(mutex))\
-    {\
-        ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-    }\
-    ZXIC_COMM_ASSERT(0);\
-    return ZXIC_PAR_CHK_INVALID_INDEX;\
-}\
-}while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW(val0,val1)\
-do{\
-    if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\
-    {\
-        ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-        ZXIC_COMM_ASSERT(0);\
-        return ZXIC_PAR_CHK_INVALID_INDEX;\
-    }\
-}while(0)  
-#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_64(val0,val1)\
-do{\
-    if(((val0) > 0) && ((ZXIC_ULONG_MAX / (val0)) < (val1)))\
-    {\
-        ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-        ZXIC_COMM_ASSERT(0);\
-        return ZXIC_PAR_CHK_INVALID_INDEX;\
-    }\
-}while(0)  
-
-#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_UNLOCK(val0, val1, mutex)\
-do{\
-  if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\
-  {\
-      ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-      if(0 != zxic_comm_mutex_unlock(mutex))\
-      {\
-          ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-      }\
-      ZXIC_COMM_ASSERT(0);\
-      return ZXIC_PAR_CHK_INVALID_INDEX;\
-  }\
-}while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_RETURN_NULL(val,min,max)\
-    do{\
-        if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_NULL;\
-        }\
-        else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_NULL;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_RC_UNLOCK(rc, becall, mutex)\
-    do{\
-       if(ZXIC_OK != rc)\
-       {\
-          ZXIC_COMM_TRACE_ERROR("\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-          if(0 != zxic_comm_mutex_unlock(mutex))\
-          {   \
-              ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-          }   \
-          ZXIC_COMM_ASSERT(0);\
-          return rc;\
-       }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_RC_CLOSE_FP(rc, becall, fp)\
-    do{\
-        if(ZXIC_OK != rc)\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-            if(ZXIC_COMM_FCLOSE(fp))\
-            {\
-                ZXIC_COMM_TRACE_ERROR("\n ZXIC  %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\
-            }\
-            ZXIC_COMM_ASSERT(0);\
-            return rc;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_POINT_CLOSE_FP(point, fp)\
-    do{\
-      if(NULL == (point))\
-      {\
-          ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-          if (ZXIC_COMM_FCLOSE(fp))\
-          {\
-              ZXIC_COMM_TRACE_ERROR("\n ZXIC  %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\
-          }\
-          ZXIC_COMM_ASSERT(0);\
-          return ZXIC_PAR_CHK_POINT_NULL;\
-      }\
-    }while(0)\
-
-          
-#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_RETURN(val0, val1)\
-          do{\
-              if((0xFFFFFFFF - (val0)) < (val1))\
-              {\
-                  ZXIC_COMM_TRACE_ERROR("ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-                  return;\
-              }\
-          }while(0)
-          
-#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_RETURN(val0, val1)\
-          do{\
-              if(val0 < val1)\
-              {\
-                  ZXIC_COMM_TRACE_ERROR("ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-                  return;\
-              }\
-          }while(0)
-          
-#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_CLOSE_FP_NO_ASSERT(dev_id, val0, val1, fp)\
-              do{\
-                  if((0xFFFFFFFF - (val0)) < (val1))\
-                  {\
-                     ZXIC_COMM_TRACE_DEV_ERROR(dev_id,  "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-                      if (ZXIC_COMM_FCLOSE(fp))\
-                      {\
-                          ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ICM  %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\
-                      }\
-                     return ZXIC_PAR_CHK_INVALID_INDEX;\
-                  }\
-              }while(0)
-          
-#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_CLOSE_FP_NO_ASSERT(dev_id, val0, val1, fp)\
-                      do{\
-                          if((val0 > 0) && ((0xFFFFFFFF / (val0)) < (val1)))\
-                          {\
-                              ZXIC_COMM_TRACE_DEV_ERROR(dev_id,  "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-                              if (ZXIC_COMM_FCLOSE(fp))\
-                              {\
-                                  ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ICM  %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\
-                              }\
-                              return ZXIC_PAR_CHK_INVALID_INDEX;\
-                          }\
-                      }while(0)
-
-#endif
-
-#if ZXIC_REAL("NO DEV_ID & NO ASSERT")
-#define ZXIC_COMM_CHECK_RC_NO_ASSERT(rc,becall)\
-    do{\
-        if(ZXIC_OK != rc)\
-        {\
-           ZXIC_COMM_TRACE_ERROR("\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-           return rc;\
-        }\
-      }while(0)
-
-#define ZXIC_COMM_CHECK_RC_NO_ASSERT_UNLOCK(rc, becall, mutex)\
-    do{\
-        if(ZXIC_OK != rc)\
-        {\
-           ZXIC_COMM_TRACE_ERROR("\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-           if(0 != zxic_comm_mutex_unlock(mutex))\
-           {   \
-               ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-           }   \
-           return rc;\
-        }\
-      }while(0)
-
-#define ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, becall, ptr)\
-  do{\
-       if (ZXIC_OK != rc)\
-       {\
-          ZXIC_COMM_TRACE_ERROR("\n ZXICP  %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\
-          ZXIC_COMM_FREE(ptr);\
-          return rc;\
-       }\
-  }while(0)
-
-#define ZXIC_COMM_CHECK_RC_MEMORY_FREE2PTR_NO_ASSERT(rc, becall, ptr1, ptr2)\
-    do{\
-          if (ZXIC_OK != rc)\
-          {\
-              ZXIC_COMM_TRACE_ERROR("\n ZXICP  %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\
-              ZXIC_COMM_FREE(ptr1);\
-              ZXIC_COMM_FREE(ptr2);\
-              return rc;\
-          }\
-      }while(0)
-
-#define ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, becall, ptr1, ptr2, ptr3)\
-    do{\
-          if (ZXIC_OK != rc)\
-          {\
-              ZXIC_COMM_TRACE_ERROR("\n ZXICP  %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\
-              ZXIC_COMM_FREE(ptr1);\
-              ZXIC_COMM_FREE(ptr2);\
-              ZXIC_COMM_FREE(ptr3);\
-              return rc;\
-          }\
-      }while(0)
-
-#define ZXIC_COMM_CHECK_POINT_NO_ASSERT(point)\
-    do{\
-         if(ZXIC_NULL == (point))\
-         {\
-            ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-            return ZXIC_PAR_CHK_POINT_NULL;\
-         }\
-     }while(0)
-
-#define ZXIC_COMM_CHECK_POINT_CLOSE_FP_NO_ASSERT(point, fp)\
-     do{\
-       if(NULL == (point))\
-       {\
-           ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-           if (ZXIC_COMM_FCLOSE(fp))\
-           {\
-               ZXIC_COMM_TRACE_ERROR("\n ZXIC  %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\
-           }\
-           return ZXIC_PAR_CHK_POINT_NULL;\
-       }\
-     }while(0)
-
-#define ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(point,ptr)\
-    do{\
-         if(ZXIC_NULL == (point))\
-         {\
-            ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            return ZXIC_PAR_CHK_POINT_NULL;\
-         }\
-     }while(0)
-
-#define ZXIC_COMM_CHECK_POINT_MEMORY_FREE2PTR_NO_ASSERT(point, ptr1, ptr2)\
-    do{\
-          if(ZXIC_NULL == (point))\
-          {\
-              ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-              ZXIC_COMM_FREE(ptr1);\
-              ZXIC_COMM_FREE(ptr2);\
-              return ZXIC_PAR_CHK_POINT_NULL;\
-          }\
-      }while(0)
-
-#define ZXIC_COMM_CHECK_POINT_MEMORY_FREE3PTR_NO_ASSERT(point, ptr1, ptr2, ptr3)\
-    do{\
-          if(ZXIC_NULL == (point))\
-          {\
-              ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-              ZXIC_COMM_FREE(ptr1);\
-              ZXIC_COMM_FREE(ptr2);\
-              ZXIC_COMM_FREE(ptr3);\
-              return ZXIC_PAR_CHK_POINT_NULL;\
-          }\
-      }while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_NO_ASSERT(val,min,max)\
-   do{\
-       if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\
-       {\
-           ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-           return ZXIC_PAR_CHK_INVALID_INDEX;\
-       }\
-       else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\
-       {\
-           ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-           return ZXIC_PAR_CHK_INVALID_RANGE;\
-       }\
-   }while (0)
-
-#define ZXIC_COMM_CHECK_INDEX_NO_ASSERT_UNLOCK(val, min, max, mutex)\
-   do{\
-       if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\
-       {\
-           ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-           if(0 != zxic_comm_mutex_unlock(mutex))\
-           {   \
-               ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-           }   \
-           return ZXIC_PAR_CHK_INVALID_INDEX;\
-       }\
-       else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\
-       {\
-           ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-           if(0 != zxic_comm_mutex_unlock(mutex))\
-           {   \
-               ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-           }   \
-           return ZXIC_PAR_CHK_INVALID_RANGE;\
-       }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_UPPER_NO_ASSERT(val, max)\
-   do{\
-       if((val) > (max))\
-       {\
-           ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-           return ZXIC_PAR_CHK_INVALID_INDEX;\
-       }\
-   }while(0)    
-
-#define ZXIC_COMM_CHECK_INDEX_UPPER_NO_ASSERT_UNLOCK(val, max, mutex)\
-  do{\
-      if((val) > (max))\
-      {\
-          ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-          if(0 != zxic_comm_mutex_unlock(mutex))\
-          {   \
-              ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-          }   \
-          return ZXIC_PAR_CHK_INVALID_INDEX;\
-      }\
-  }while(0)   
-#define ZXIC_COMM_CHECK_INDEX_UPPER_MEMORY_FREE_NO_ASSERT(val, max, ptr)\
- do{\
-     if((val) > (max))\
-     {\
-         ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-         ZXIC_COMM_FREE(ptr);\
-         return ZXIC_PAR_CHK_INVALID_INDEX;\
-     }\
- }while(0) 
-
-#define ZXIC_COMM_CHECK_INDEX_LOWER_NO_ASSERT(val,min)\
-   do{\
-       if((val) < (min))\
-       {\
-           ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-           return ZXIC_PAR_CHK_INVALID_INDEX;\
-       }\
-   }while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_LOWER_NO_ASSERT_UNLOCK(val, min, mutex)\
-  do{\
-      if((val) < (min))\
-      {\
-          ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-          if(0 != zxic_comm_mutex_unlock(mutex))\
-          {   \
-              ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-          }   \
-          return ZXIC_PAR_CHK_INVALID_INDEX;\
-      }\
-  }while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_LOWER_MEMORY_FREE_NO_ASSERT(val,min,ptr)\
-   do{\
-       if((val) < (min))\
-       {\
-           ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-           ZXIC_COMM_FREE(ptr);\
-           return ZXIC_PAR_CHK_INVALID_INDEX;\
-       }\
-   }while(0)       
-#define ZXIC_COMM_CHECK_INDEX_BOTH_NO_ASSERT(val, min, max)\
-   do{\
-       if(((val) < (min)) || ((val) > (max)))\
-       {\
-           ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-           return ZXIC_PAR_CHK_INVALID_INDEX;\
-       }\
-   }while(0) 
-
-#define ZXIC_COMM_CHECK_INDEX_BOTH_NO_ASSERT_UNLOCK(val, min, max, mutex)\
-  do{\
-      if(((val) < (min)) || ((val) > (max)))\
-      {\
-          ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-          if(0 != zxic_comm_mutex_unlock(mutex))\
-          {   \
-              ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-          }   \
-          return ZXIC_PAR_CHK_INVALID_INDEX;\
-      }\
-  }while(0) 
-#define ZXIC_COMM_CHECK_INDEX_BOTH_MEMORY_FREE_NO_ASSERT(val, min, max, ptr)\
-   do{\
-       if(((val) < (min)) || ((val) > (max)))\
-       {\
-           ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-           ZXIC_COMM_FREE(ptr);\
-           return ZXIC_PAR_CHK_INVALID_INDEX;\
-       }\
-   }while(0)       
-#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(val0, val1)\
-      do{\
-          if((ZXIC_UINT32_MAX - (val0)) < (val1))\
-          {\
-              ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-              return ZXIC_PAR_CHK_INVALID_INDEX;\
-          }\
-      }while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_64_NO_ASSERT(val0,val1)\
-      do{\
-          if((ZXIC_ULONG_MAX - (val0)) < (val1))\
-          {\
-              ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-              return ZXIC_PAR_CHK_INVALID_INDEX;\
-          }\
-      }while(0)  
-
-#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT_UNLOCK(val0, val1, mutex)\
-do{\
-    if((ZXIC_UINT32_MAX - (val0)) < (val1))\
-    {\
-        ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-        if(0 != zxic_comm_mutex_unlock(mutex))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-        }\
-        return ZXIC_PAR_CHK_INVALID_INDEX;\
-    }\
-}while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_ASSERT(val0, val1)\
-       do{\
-          if((val0) < (val1))\
-          {\
-              ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-              return ZXIC_PAR_CHK_INVALID_INDEX;\
-          }\
-       }while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_ASSERT_UNLOCK(val0, val1, mutex)\
- do{\
-    if((val0) < (val1))\
-    {\
-        ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-        if(0 != zxic_comm_mutex_unlock(mutex))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-        }\
-        return ZXIC_PAR_CHK_INVALID_INDEX;\
-    }\
- }while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(val0, val1)\
-       do{\
-           if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\
-           {\
-              ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-              return ZXIC_PAR_CHK_INVALID_INDEX;\
-           }\
-       }while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT_UNLOCK(val0, val1, mutex)\
-      do{\
-          if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\
-          {\
-             ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-              if(0 != zxic_comm_mutex_unlock(mutex))\
-              {\
-                  ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-              }\
-             return ZXIC_PAR_CHK_INVALID_INDEX;\
-          }\
-      }while(0)
-#define ZXIC_COMM_CHECK_INDEX_RETURN_VOID_NO_ASSERT(val,min,max)\
-  do{\
-      if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\
-      {\
-          ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-          return ;\
-      }\
-      else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\
-      {\
-          ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-          return ;\
-      }\
-  }while (0)
-
-#define ZXIC_COMM_CHECK_INDEX_RETURN_NULL_NO_ASSERT(val,min,max)\
-       do{\
-           if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\
-           {\
-               ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-               return ZXIC_NULL;\
-           }\
-           else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\
-           {\
-               ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-               return ZXIC_NULL;\
-           }\
-       }while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_CLOSE_FP_NO_ASSERT(val,min,max,fp)\
-    do{\
-        if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            if (ZXIC_COMM_FCLOSE(fp))\
-            {\
-                ZXIC_COMM_TRACE_ERROR("\n ZXIC  %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\
-            }\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-        else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            if (ZXIC_COMM_FCLOSE(fp))\
-            {\
-                ZXIC_COMM_TRACE_ERROR("\n ZXIC  %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\
-            }\
-            return ZXIC_PAR_CHK_INVALID_RANGE;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_MEMORY_FREE_NO_ASSERT(val,min,max,ptr)\
-    do{\
-          if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\
-          {\
-              ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-              ZXIC_COMM_FREE(ptr);\
-              return ZXIC_PAR_CHK_INVALID_INDEX;\
-          }\
-          else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\
-          {\
-              ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-              ZXIC_COMM_FREE(ptr);\
-              return ZXIC_PAR_CHK_INVALID_RANGE;\
-          }\
-      }while(0)
-#define ZXIC_COMM_CHECK_INDEX_MEMORY_FREE2PTR_NO_ASSERT(val, min, max, ptr1, ptr2)\
-    do{\
-          if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\
-          {\
-              ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-              ZXIC_COMM_FREE(ptr1);\
-              ZXIC_COMM_FREE(ptr2);\
-              return ZXIC_PAR_CHK_INVALID_INDEX;\
-          }\
-          else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\
-          {\
-              ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-              ZXIC_COMM_FREE(ptr1);\
-              ZXIC_COMM_FREE(ptr2);\
-              return ZXIC_PAR_CHK_INVALID_RANGE;\
-          }\
-      }while(0)
-#define ZXIC_COMM_CHECK_INDEX_MEMORY_FREE3PTR_NO_ASSERT(val, min, max, ptr1, ptr2, ptr3)\
-    do{\
-          if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\
-          {\
-              ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-              ZXIC_COMM_FREE(ptr1);\
-              ZXIC_COMM_FREE(ptr2);\
-              ZXIC_COMM_FREE(ptr3);\
-              return ZXIC_PAR_CHK_INVALID_INDEX;\
-          }\
-          else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\
-          {\
-              ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-              ZXIC_COMM_FREE(ptr1);\
-              ZXIC_COMM_FREE(ptr2);\
-              ZXIC_COMM_FREE(ptr3);\
-              return ZXIC_PAR_CHK_INVALID_RANGE;\
-          }\
-      }while(0)
-
-#endif
-
-#if ZXIC_REAL("DEV_ID & ASSERT")
-
-#define ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, becall)\
-   do{\
-       if(ZXIC_OK != rc)\
-       {\
-          ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-          ZXIC_COMM_ASSERT(0);\
-          return rc;\
-       }\
-   }while(0)
-#define ZXIC_COMM_CHECK_DEV_RC_NULL(dev_id,rc,becall)\
-       do{\
-           if(ZXIC_OK != rc)\
-           {\
-               ZXIC_COMM_TRACE_ERROR("\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-               ZXIC_COMM_ASSERT(0);\
-               return NULL;\
-           }\
-       }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_RC_UNLOCK(dev_id,rc, becall, mutex)\
-    do{\
-         if(ZXIC_OK != rc)\
-         {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-            if(0 != zxic_comm_mutex_unlock(mutex))\
-            {   \
-                ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-            }   \
-            ZXIC_COMM_ASSERT(0);\
-            return rc;\
-         }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_RC_CLOSE_FP(dev_id, rc, becall, fp)\
-    do{\
-        if(ZXIC_OK != rc)\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-            if(ZXIC_COMM_FCLOSE(fp))\
-            {\
-                ZXIC_COMM_TRACE_ERROR("\n ZXIC  %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\
-            }\
-            ZXIC_COMM_ASSERT(0);\
-            return rc;\
-        }\
-    }while(0)
-                
-#define ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE(dev_id, rc, becall, ptr)\
-    do{\
-         if (ZXIC_OK != rc)\
-         {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXICP  %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\
-            ZXIC_COMM_FREE(ptr);\
-            ZXIC_COMM_ASSERT(0);\
-            return rc;\
-         }\
-    } while (0)
-
-#define ZXIC_COMM_CHECK_DEV_POINT(dev_id, point)\
-    do{\
-         if(NULL == (point))\
-         {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_POINT_NULL;\
-         }\
-     }while(0)
-#define ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE(dev_id, point, ptr)\
-   do{\
-      if(ZXIC_NULL == (point))\
-      {\
-         ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-         ZXIC_COMM_FREE(ptr);\
-         ZXIC_COMM_ASSERT(0);\
-         return ZXIC_PAR_CHK_POINT_NULL;\
-      }\
-   }while(0)
-#define ZXIC_COMM_CHECK_DEV_POINT_EMEMORY_FREE2PTR(dev_id, point, ptr0, ptr1)\
-   do{\
-      if(ZXIC_NULL == (point))\
-      {\
-         ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-         ZXIC_COMM_FREE(ptr0);\
-         ZXIC_COMM_FREE(ptr1);\
-         ZXIC_COMM_ASSERT(0);\
-         return ZXIC_PAR_CHK_POINT_NULL;\
-      }\
-   }while(0)     
-#define ZXIC_COMM_CHECK_DEV_POINT_RETURN_NULL(dev_id,point)\
-        do{\
-             if(NULL == (point))\
-             {\
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-                ZXIC_COMM_ASSERT(0);\
-                return ZXIC_NULL;\
-             }\
-         }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_POINT_UNLOCK(dev_id,point,mutex)\
-    do{\
-         if(NULL == (point))\
-         {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-            if(0 != zxic_comm_mutex_unlock(mutex))\
-            {   \
-                ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-            }   \
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_POINT_NULL;\
-         }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_POINT_CLOSE_FP(dev_id, point, fp)\
-    do{\
-        if(NULL == (point))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-            if (ZXIC_COMM_FCLOSE(fp))\
-            {\
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXIC  %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\
-            }\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_POINT_NULL;\
-        }\
-    }while(0)\
-
-#define ZXIC_COMM_CHECK_DEV_INDEX(dev_id,val,min,max)\
-    do{\
-        if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_dev_index_check(dev_id, val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-        else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_dev_index_check(dev_id, val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_RANGE;\
-        }\
-     }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER(dev_id,val,max)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)    
-#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER(dev_id,val,min)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH(dev_id,val,min,max)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_MEMORY_FREE(dev_id,val,max,ptr)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)    
-#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_MEMORY_FREE(dev_id,val,min,ptr)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_MEMORY_FREE(dev_id,val,min,max,ptr)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_RETURN_NULL(dev_id,val,min,max)\
-    do{\
-        if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_NULL;\
-        }\
-        else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_NULL;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_ID(dev_id)\
-    do{\
-        if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(dev_id, 0, zxic_comm_channel_max_get() - 1))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, dev_id, 0, zxic_comm_channel_max_get() - 1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-        else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(dev_id, 0, zxic_comm_channel_max_get() - 1))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, dev_id, 0, zxic_comm_channel_max_get() - 1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_RANGE;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW(dev_id,val0,val1)\
-    do{\
-        if((ZXIC_UINT32_MAX - (val0)) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-        
-#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64(dev_id,val0,val1)\
-    do{\
-        if((ZXIC_ULONG_MAX - (val0)) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-        
-#define ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW(dev_id, val0, val1)\
-    do{\
-        if((val0) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)  
-        
-#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW(dev_id,val0,val1)\
-    do{\
-        if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)  
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_64(dev_id, val0, val1)\
-        do{\
-            if(((val0) > 0) && ((0xFFFFFFFFFFFFFFFF / (val0)) < (val1)))\
-            {\
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-                ZXIC_COMM_ASSERT(0);\
-                return ZXIC_PAR_CHK_INVALID_INDEX;\
-            }\
-        }while(0) 
-
-
-#endif
-
-#if ZXIC_REAL("DEV_ID & NO ASSERT")
-#define ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id,rc,becall)\
-    do{\
-        if(ZXIC_OK != rc)\
-        {\
-           ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-           return rc;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(dev_id,rc, becall, mutex)\
-    do{\
-         if(ZXIC_OK != rc)\
-         {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-            if(0 != zxic_comm_mutex_unlock(mutex))\
-            {   \
-                ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-            }   \
-            return rc;\
-         }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_RC_CLOSE_FP_NO_ASSERT(dev_id, rc, becall, fp)\
-    do{\
-        if(ZXIC_OK != rc)\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-            if (ZXIC_COMM_FCLOSE(fp))\
-            {\
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXIC  %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\
-            }\
-            return rc;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE_NO_ASSERT(dev_id, rc, becall, ptr)\
-do{\
-     if (ZXIC_OK != rc)\
-     {\
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXICP  %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\
-        ZXIC_COMM_FREE(ptr);\
-        return rc;\
-     }\
-} while (0)
-#define ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE2PTR_NO_ASSERT(dev_id, rc, becall, ptr1, ptr2)\
-do{\
-     if (ZXIC_OK != rc)\
-     {\
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXICP  %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\
-        ZXIC_COMM_FREE(ptr1);\
-        ZXIC_COMM_FREE(ptr2);\
-        return rc;\
-     }\
-} while (0)
-#define ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE3PTR_NO_ASSERT(dev_id, rc, becall, ptr1, ptr2, ptr3)\
-do{\
-     if (ZXIC_OK != rc)\
-     {\
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXICP  %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\
-        ZXIC_COMM_FREE(ptr1);\
-        ZXIC_COMM_FREE(ptr2);\
-        ZXIC_COMM_FREE(ptr3);\
-        return rc;\
-     }\
-} while (0)
-
-#define ZXIC_COMM_CHECK_DEV_POINT_NO_ASSERT(dev_id,point)\
-    do{\
-         if(NULL == (point))\
-         {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-            return ZXIC_PAR_CHK_POINT_NULL;\
-         }\
-     }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_POINT_RETURN_NULL_NO_ASSERT(dev_id,point)\
-     do{\
-        if(ZXIC_NULL == (point))\
-        {\
-           ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-           return ZXIC_NULL;\
-        }\
-     }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_POINT_CLOSE_FP_NO_ASSERT(dev_id, point, fp)\
-    do{\
-        if(NULL == (point))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-            if (ZXIC_COMM_FCLOSE(fp))\
-            {\
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ZXIC  %s:%d !-- %s close file Fail!\n",__FILE__,__LINE__,__FUNCTION__);\
-            }\
-            return ZXIC_PAR_CHK_POINT_NULL;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE_NO_ASSERT(dev_id,point,ptr)\
-    do{\
-         if(ZXIC_NULL == (point))\
-         {\
-            ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            return ZXIC_PAR_CHK_POINT_NULL;\
-         }\
-     }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE2PTR_NO_ASSERT(dev_id, point, ptr1, ptr2)\
-    do{\
-          if(ZXIC_NULL == (point))\
-          {\
-              ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-              ZXIC_COMM_FREE(ptr1);\
-              ZXIC_COMM_FREE(ptr2);\
-              return ZXIC_PAR_CHK_POINT_NULL;\
-          }\
-      }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE3PTR_NO_ASSERT(dev_id, point, ptr1, ptr2, ptr3)\
-    do{\
-          if(ZXIC_NULL == (point))\
-          {\
-              ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-              ZXIC_COMM_FREE(ptr1);\
-              ZXIC_COMM_FREE(ptr2);\
-              ZXIC_COMM_FREE(ptr3);\
-              return ZXIC_PAR_CHK_POINT_NULL;\
-          }\
-      }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id,val,min,max)\
-    do{\
-        if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_dev_index_check(dev_id, val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-        else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_dev_index_check(dev_id, val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            return ZXIC_PAR_CHK_INVALID_RANGE;\
-        }\
-     }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT_UNLOCK(dev_id, val, min, max, mutex)\
-    do{\
-        if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_dev_index_check(dev_id, val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            if(0 != zxic_comm_mutex_unlock(mutex))\
-            {   \
-                ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-            }   \
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-        else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_dev_index_check(dev_id, val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            if(0 != zxic_comm_mutex_unlock(mutex))\
-            {   \
-                ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-            }   \
-            return ZXIC_PAR_CHK_INVALID_RANGE;\
-        }\
-     }while(0)
-  
-#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_NO_ASSERT(dev_id,val,max)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)    
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_NO_ASSERT_UNLOCK(dev_id, val, max, mutex)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-            if(0 != zxic_comm_mutex_unlock(mutex))\
-            {   \
-                ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-            }   \
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)  
-#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_MEMORY_FREE_NO_ASSERT(dev_id,val,max,ptr)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)   
-
-        
-#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_NO_ASSERT(dev_id,val,min)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_NO_ASSERT_UNLOCK(dev_id, val, min, mutex)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-            if(0 != zxic_comm_mutex_unlock(mutex))\
-            {   \
-                ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-            }   \
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_MEMORY_FREE_NO_ASSERT(dev_id,val,min,ptr)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-
-        
-#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_NO_ASSERT(dev_id,val,min,max)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_NO_ASSERT_UNLOCK(dev_id, val, min, max, mutex)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            if(0 != zxic_comm_mutex_unlock(mutex))\
-            {   \
-                ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-            }   \
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_MEMORY_FREE_NO_ASSERT(dev_id,val,min,max,ptr)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_RETURN_NULL_NO_ASSERT(dev_id,val,min,max)\
-    do{\
-        if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            return ZXIC_NULL;\
-        }\
-        else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            return ZXIC_NULL;\
-        }\
-    }while(0)
-
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id,val,min,max,ptr)\
-    do{\
-        if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_dev_index_check(dev_id, val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-        else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_dev_index_check(dev_id, val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            return ZXIC_PAR_CHK_INVALID_RANGE;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE2PTR_NO_ASSERT(dev_id, val, min, max, ptr1, ptr2)\
-    do{\
-        if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_dev_index_check(dev_id, val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr1);\
-            ZXIC_COMM_FREE(ptr2);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-        else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_dev_index_check(dev_id, val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr1);\
-            ZXIC_COMM_FREE(ptr2);\
-            return ZXIC_PAR_CHK_INVALID_RANGE;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE3PTR_NO_ASSERT(dev_id, val, min, max, ptr1, ptr2, ptr3)\
-    do{\
-        if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_dev_index_check(dev_id, val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr1);\
-            ZXIC_COMM_FREE(ptr2);\
-            ZXIC_COMM_FREE(ptr3);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-        else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_dev_index_check(dev_id, val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr1);\
-            ZXIC_COMM_FREE(ptr2);\
-            ZXIC_COMM_FREE(ptr3);\
-            return ZXIC_PAR_CHK_INVALID_RANGE;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_ID_NO_ASSERT(dev_id)\
-    do{\
-        if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(dev_id, 0, zxic_comm_channel_max_get() - 1))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, dev_id, 0, zxic_comm_channel_max_get() - 1, __FUNCTION__);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-        else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(dev_id, 0, zxic_comm_channel_max_get() - 1))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, dev_id, 0, zxic_comm_channel_max_get() - 1, __FUNCTION__);\
-            return ZXIC_PAR_CHK_INVALID_RANGE;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_ID_RETURN_NULL_NO_ASSERT(dev_id)\
-    do{\
-        if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(dev_id, 0, zxic_comm_channel_max_get() - 1))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, dev_id, 0, zxic_comm_channel_max_get() - 1, __FUNCTION__);\
-            return ZXIC_NULL;\
-        }\
-        else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(dev_id, 0, zxic_comm_channel_max_get() - 1))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, dev_id, 0, zxic_comm_channel_max_get() - 1, __FUNCTION__);\
-            return ZXIC_NULL;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, val0, val1)\
-    do{\
-        if((val0) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)  
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT_UNLOCK(dev_id, val0, val1, mutex)\
-    do{\
-        if((val0) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            if(0 != zxic_comm_mutex_unlock(mutex))\
-            {\
-                ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-            }\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)  
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id,val0,val1)\
-    do{\
-        if((ZXIC_UINT32_MAX - (val0)) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT_UNLOCK(dev_id,val0,val1,mutex)\
-    do{\
-        if((ZXIC_UINT32_MAX - (val0)) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            if(0 != zxic_comm_mutex_unlock(mutex))\
-            {\
-                ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-            }\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64_NO_ASSERT(dev_id,val0,val1)\
-    do{\
-        if((ZXIC_ULONG_MAX - (val0)) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id,val0,val1)\
-    do{\
-        if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)  
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT_UNLOCK(dev_id,val0,val1,mutex)\
-    do{\
-        if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            if(0 != zxic_comm_mutex_unlock(mutex))\
-            {\
-                ZXIC_COMM_TRACE_ERROR("File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", __FILE__, __FUNCTION__, __LINE__);\
-            }\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_64_NO_ASSERT(dev_id,val0,val1)\
-    do{\
-        if(((val0) > 0) && ((ZXIC_ULONG_MAX/ (val0)) < (val1)))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            return ZXIC_PAR_CHK_INVALID_INDEX;\
-        }\
-    }while(0)  
-
-#endif
-#if ZXIC_REAL("return no code")
-#define ZXIC_COMM_CHECK_RC_RETURN_NONE(rc,becall)\
-    do{\
-        if(ZXIC_OK != rc)\
-        {\
-           ZXIC_COMM_TRACE_ERROR("\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-           ZXIC_COMM_ASSERT(0);\
-           return;\
-        }\
-    }while(0)
-
-/* 不带返回值,用于VOID类型函数 */
-#define ZXIC_COMM_CHECK_POINT_RETURN_NONE(point)\
-    do{\
-       if(ZXIC_NULL == (point))\
-       {\
-          ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-          ZXIC_COMM_ASSERT(0);\
-          return;\
-       }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_RETURN_NONE(val0,val1)\
-    do{\
-        if((ZXIC_UINT32_MAX - (val0)) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)  
-#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_RETURN_NONE(val0,val1)\
-    do{\
-        if((val0) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_RETURN_NONE(val0,val1)\
-    do{\
-        if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_UPPER_RETURN_NONE(val,max)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_LOWER_RETURN_NONE(val,min)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)    
-#define ZXIC_COMM_CHECK_INDEX_BOTH_RETURN_NONE(val,min,max)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)              
-#define ZXIC_COMM_CHECK_INDEX_UPPER_MEMORY_FREE_RETURN_NONE(val,max,ptr)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_LOWER_MEMORY_FREE_RETURN_NONE(val,min,ptr)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)    
-#define ZXIC_COMM_CHECK_INDEX_BOTH_MEMORY_FREE_RETURN_NONE(val,min,max,ptr)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0) 
-
-#define ZXIC_COMM_CHECK_DEV_RC_RETURN_NONE(dev_id, rc, becall)\
-    do{\
-        if(ZXIC_OK != rc)\
-        {\
-           ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-           ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_POINT_RETURN_NONE(dev_id,point)\
-  do{\
-       if(NULL == (point))\
-       {\
-          ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-          ZXIC_COMM_ASSERT(0);\
-          return;\
-       }\
-   }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_RETURN_NONE(dev_id,val,max)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)      
-#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_RETURN_NONE(dev_id,val,min)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_RETURN_NONE(dev_id,val,min,max)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_MEMORY_FREE_RETURN_NONE(dev_id,val,max,ptr)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)      
-#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_MEMORY_FREE_RETURN_NONE(dev_id,val,min,ptr)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_MEMORY_FREE_RETURN_NONE(dev_id,val,min,max,ptr)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)    
-#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_RETURN_NONE(dev_id,val0,val1)\
-    do{\
-        if((ZXIC_UINT32_MAX - (val0)) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)
-        
-#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64_RETURN_NONE(dev_id,val0,val1)\
-    do{\
-        if((ZXIC_ULONG_MAX - (val0)) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)
-        
-#define ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_RETURN_NONE(dev_id, val0, val1)\
-    do{\
-        if((val0) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)  
-        
-#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_RETURN_NONE(dev_id,val0,val1)\
-    do{\
-        if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return;\
-        }\
-    }while(0)     
-#endif
-
-#if ZXIC_REAL("return no code & no assert")
-#define ZXIC_COMM_CHECK_RC_RETURN_NONE_NO_ASSERT(rc,becall)\
-    do{\
-        if(ZXIC_OK != rc)\
-        {\
-           ZXIC_COMM_TRACE_ERROR("\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-           return;\
-        }\
-    }while(0)
-
-/* 不带返回值,用于VOID类型函数 */
-#define ZXIC_COMM_CHECK_POINT_RETURN_NONE_NO_ASSERT(point)\
-    do{\
-       if(ZXIC_NULL == (point))\
-       {\
-          ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-          return;\
-       }\
-    }while(0) 
-#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_RETURN_NONE_NO_ASSERT(val0,val1)\
-    do{\
-        if((ZXIC_UINT32_MAX - (val0)) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            return;\
-        }\
-    }while(0)  
-#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_RETURN_NONE_NO_ASSERT(val0,val1)\
-    do{\
-        if((val0) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            return;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_RETURN_NONE_NO_ASSERT(val0,val1)\
-    do{\
-        if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            return;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_UPPER_RETURN_NONE_NO_ASSERT(val,max)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-            return;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_LOWER_RETURN_NONE_NO_ASSERT(val,min)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-            return;\
-        }\
-    }while(0)    
-#define ZXIC_COMM_CHECK_INDEX_BOTH_RETURN_NONE_NO_ASSERT(val,min,max)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            return;\
-        }\
-    }while(0)              
-#define ZXIC_COMM_CHECK_INDEX_UPPER_MEMORY_FREE_RETURN_NONE_NO_ASSERT(val,max,ptr)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            return;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_LOWER_MEMORY_FREE_RETURN_NONE_NO_ASSERT(val,min,ptr)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            return;\
-        }\
-    }while(0)    
-#define ZXIC_COMM_CHECK_INDEX_BOTH_MEMORY_FREE_RETURN_NONE_NO_ASSERT(val,min,max,ptr)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            return;\
-        }\
-    }while(0) 
-
-#define ZXIC_COMM_CHECK_DEV_RC_RETURN_NONE_NO_ASSERT(dev_id, rc, becall)\
-    do{\
-        if(ZXIC_OK != rc)\
-        {\
-           ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-            return;\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_POINT_RETURN_NONE_NO_ASSERT(dev_id,point)\
-  do{\
-       if(NULL == (point))\
-       {\
-          ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-          return;\
-       }\
-   }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_RETURN_NONE_NO_ASSERT(dev_id,val,max)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-            return;\
-        }\
-    }while(0)      
-#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_RETURN_NONE_NO_ASSERT(dev_id,val,min)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-            return;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_RETURN_NONE_NO_ASSERT(dev_id,val,min,max)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            return;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_MEMORY_FREE_RETURN_NONE_NO_ASSERT(dev_id,val,max,ptr)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            return;\
-        }\
-    }while(0)      
-#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_MEMORY_FREE_RETURN_NONE_NO_ASSERT(dev_id,val,min,ptr)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            return;\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_MEMORY_FREE_RETURN_NONE_NO_ASSERT(dev_id,val,min,max,ptr)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-            ZXIC_COMM_FREE(ptr);\
-            return;\
-        }\
-    }while(0)    
-#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_RETURN_NONE_NO_ASSERT(dev_id,val0,val1)\
-    do{\
-        if((ZXIC_UINT32_MAX - (val0)) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            return;\
-        }\
-    }while(0)
-        
-#define ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_RETURN_NONE_NO_ASSERT(dev_id, val0, val1)\
-    do{\
-        if((val0) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            return;\
-        }\
-    }while(0)  
-        
-#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_RETURN_NONE_NO_ASSERT(dev_id,val0,val1)\
-    do{\
-        if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            return;\
-        }\
-    }while(0)     
-#endif
-
-#if ZXIC_REAL("no return")
-#define ZXIC_COMM_CHECK_RC_NONE(rc,becall)\
-    do{\
-        if(ZXIC_OK != rc)\
-        {\
-           ZXIC_COMM_TRACE_ERROR("\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-           ZXIC_COMM_ASSERT(0);\
-        }\
-    }while(0)
-
-/* 不带返回值,用于VOID类型函数 */
-#define ZXIC_COMM_CHECK_POINT_NONE(point)\
-    do{\
-       if(ZXIC_NULL == (point))\
-       {\
-          ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-          ZXIC_COMM_ASSERT(0);\
-       }\
-    }while(0)
-
-/* 不带返回值,用于VOID类型函数 */
-#define ZXIC_COMM_CHECK_INDEX_NONE(val,min,max)\
-    do{\
-        if (ZXIC_OK != zxic_comm_index_check(val, min, max));\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_UPPER_NONE(val,max)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-        }\
-    }while(0)  
-#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NONE(val0,val1)\
-    do{\
-        if((ZXIC_UINT32_MAX - (val0)) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-        }\
-    }while(0)  
-#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NONE(val0,val1)\
-    do{\
-        if((val0) < (val1))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NONE(val0,val1)\
-    do{\
-        if(((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1)))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val0, val1, __FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_LOWER_NONE(val,min)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_INDEX_BOTH_NONE(val,min,max)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-        }\
-    }while(0)              
-
-#define ZXIC_COMM_CHECK_DEV_RC_NONE(dev_id, rc, becall)\
-    do{\
-        if(ZXIC_OK != rc)\
-        {\
-           ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,becall);\
-           ZXIC_COMM_ASSERT(0);\
-        }\
-    }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_POINT_NONE(dev_id,point)\
-  do{\
-       if(NULL == (point))\
-       {\
-          ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);\
-          ZXIC_COMM_ASSERT(0);\
-       }\
-   }while(0)
-
-#define ZXIC_COMM_CHECK_DEV_INDEX_NONE(dev_id,val,min,max)\
-    do{\
-        if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_dev_index_check(dev_id, val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-        }\
-        else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_dev_index_check(dev_id, val, min, max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-        }\
-     }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_NONE(dev_id,val,max)\
-    do{\
-        if((val) > (max))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, max, __FUNCTION__);\
-        }\
-    }while(0)      
-#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_NONE(dev_id,val,min)\
-    do{\
-        if((val) < (min))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, __FUNCTION__);\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_NONE(dev_id,val,min,max)\
-    do{\
-        if(((val) < (min)) || ((val) > (max)))\
-        {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);\
-        }\
-    }while(0)
-#define ZXIC_COMM_CHECK_DEV_RC_INT(dev_id,check_rc,rc,becall)\
-   do{\
-       if(check_rc < 0)\
-       {\
-          ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM  %s:%d [ErrorCode:0x%x] [rc:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,check_rc, rc,__FUNCTION__,becall);\
-          ZXIC_COMM_ASSERT(0);\
-          return rc;\
-       }\
-   }while(0)
-
-#endif
-#if ZXIC_REAL("no print")
-#define ZXIC_COMM_CHECK_RC_NO_PRINT(rc,error_code)\
-do{\
-    if(ZXIC_OK != rc)\
-    {\
-       ZXIC_COMM_ASSERT(0);\
-       return error_code;\
-    }\
-}while(0)
-#define ZXIC_COMM_CHECK_RC_UNLOCK_NO_PRINT(rc, p_mutex, error_code)\
-do{\
-    if(ZXIC_OK != rc)\
-    {\
-       (ZXIC_VOID)zxic_comm_mutex_unlock(p_mutex);\
-       ZXIC_COMM_ASSERT(0);\
-       return error_code;\
-    }\
-}while(0)
-
-#define ZXIC_COMM_CHECK_POINT_NO_PRINT(point)\
-do{\
-   if(ZXIC_NULL == (point))\
-   {\
-      ZXIC_COMM_ASSERT(0);\
-      return ZXIC_PAR_CHK_POINT_NULL;\
-   }\
-}while(0)
-#define ZXIC_COMM_CHECK_POINT_NO_PRINT_UNLOCK(point,p_mutex)\
-do{\
-   if(ZXIC_NULL == (point))\
-   {\
-      (ZXIC_VOID)zxic_comm_mutex_unlock(p_mutex);\
-      ZXIC_COMM_ASSERT(0);\
-      return ZXIC_PAR_CHK_POINT_NULL;\
-   }\
-}while(0)
-
-#define ZXIC_COMM_CHECK_RC_POINT_NO_PRINT(point,rc)\
-   do{\
-      if(ZXIC_NULL == (point))\
-      {\
-         ZXIC_COMM_ASSERT(0);\
-         return rc;\
-      }\
-   }while(0)
-
-#define ZXIC_COMM_CHECK_INDEX_NO_PRINT_UNLOCK(val,min,max,p_mutex)\
-do{\
-    if(ZXIC_PAR_CHK_INVALID_INDEX == zxic_comm_index_check(val, min, max))\
-    {\
-        (ZXIC_VOID)zxic_comm_mutex_unlock(p_mutex);\
-        ZXIC_COMM_ASSERT(0);\
-        return ZXIC_PAR_CHK_INVALID_INDEX;\
-    }\
-    else if(ZXIC_PAR_CHK_INVALID_RANGE == zxic_comm_index_check(val, min, max))\
-    {\
-        (ZXIC_VOID)zxic_comm_mutex_unlock(p_mutex);\
-        ZXIC_COMM_ASSERT(0);\
-        return ZXIC_PAR_CHK_INVALID_RANGE;\
-    }\
-}while(0)
-#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_PRINT_UNLOCK(val0, val1, mutex)\
- do{\
-    if((val0) < (val1))\
-    {\
-        if(0 != zxic_comm_mutex_unlock(mutex))\
-        {\
-            ZXIC_COMM_ASSERT(0);\
-            return ZXIC_PAR_CHK_INVALID_PARA;\
-        }\
-        ZXIC_COMM_ASSERT(0);\
-        return ZXIC_PAR_CHK_INVALID_INDEX;\
-    }\
- }while(0)
-
-#endif
-#endif /* ZXIC_REAL("参数检查") */
-
-
-//#ifdef ZXIC_FOR_LLT
-#if ZXIC_REAL("UT_TEST")
-#define ZXIC_CHECK_DEV_UT_RC(dev_id, rc, val, becall)\
-    do{\
-        if (val != rc)\
-        {\
-           ZXIC_COMM_PRINT("\n ZXICP %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\
-           zxic_comm_ut_detail_trace_dev_error(dev_id, "\n ZXICP %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", __FILE__, __LINE__, rc, __FUNCTION__, becall);\
-           return ZXIC_E_LLT_CHECK;\
-        }\
-    } while (0)
-#endif
-
-#if ZXIC_REAL("字节序")
-/* DWORD变量字节序转换 */
-#define ZXIC_COMM_CONVERT32(dw_data) \
-                                        ((((dw_data)&0xff)<<24)|(((dw_data)&0xff00)<<8)\
-                                        |(((dw_data)&0xff0000)>>8)|(((dw_data)&0xff000000)>>24))
-/* WORD变量字节序转换 */
-#define ZXIC_COMM_CONVERT16(w_data) \
-                                        ((((w_data)&0xff)<<8)|(((w_data)&0xff00)>>8))
-
-/* WORD变量字节序转换 */
-#define ZXIC_COMM_CONVERT32_16b(w_data) \
-                                        ((((w_data)&0xffff)<<16)|(((w_data)&0xffff0000)>>16))
-
-ZXIC_VOID  zxic_comm_swap_en_set(ZXIC_UINT32 enable);
-ZXIC_RTN32 zxic_comm_swap_en_get(ZXIC_VOID);
-ZXIC_RTN32 zxic_comm_is_big_endian(ZXIC_VOID);
-ZXIC_RTN32 zxic_comm_endian_prt(ZXIC_VOID);
-ZXIC_VOID  zxic_comm_swap(ZXIC_UINT8 *p_uc_data, ZXIC_UINT32 dw_byte_len);
-ZXIC_VOID  zxic_comm_swap_16b(ZXIC_UINT8 *p_uc_data, ZXIC_UINT32 dw_byte_len);
-ZXIC_UINT64 ZXIC_COMM_COUNTER64_BUILD(ZXIC_UINT32 hi, ZXIC_UINT32 lo);
-#endif
-
-#if ZXIC_REAL("内存")
-ZXIC_UINT32 zxic_comm_get_malloc_num(ZXIC_VOID);
-ZXIC_UINT32 zxic_comm_get_malloc_size(ZXIC_VOID);
-ZXIC_VOID   zxic_clr_malloc_num(ZXIC_VOID);
-
-#define ZXIC_COMM_FREE(p_data) \
-do{\
-    ic_comm_free_record();\
-    kfree(p_data);\
-    p_data = ZXIC_NULL; \
-}while(0)
-
-#define ZXIC_COMM_MALLOC(size)  ic_comm_malloc_memory(size)
-
-#define ZXIC_COMM_ALLOC_MEMORY(ptr,size) \
-    do{\
-        (ptr) = ZXIC_COMM_MALLOC(size);\
-        ZXIC_COMM_CHECK_POINT(ptr);\
-        ZXIC_COMM_MEMSET((ptr),0,size);\
-    }while(0)
-#define ZXIC_COMM_ALLOC_MEMORY_DEV(dev_id,ptr,size) \
-    do{\
-        (ptr) = ZXIC_COMM_MALLOC(size);\
-        ZXIC_COMM_CHECK_DEV_POINT(dev_id,ptr);\
-        ZXIC_COMM_MEMSET((ptr),0,size);\
-    }while(0)
-
-
-#endif
-
-#if ZXIC_REAL("延时")
-// ZXIC_VOID zxic_comm_sleep(ZXIC_UINT32 milliseconds);
-ZXIC_VOID zxic_comm_msleep(ZXIC_UINT32 millisecond);
-ZXIC_VOID zxic_comm_udelay(ZXIC_UINT32 microseconds);
-ZXIC_VOID zxic_comm_delay(ZXIC_UINT32 milliseconds);
-ZXIC_DOUBLE zxic_comm_get_ticks_s(ZXIC_VOID);
-ZXIC_DOUBLE zxic_comm_get_ticks_ms(ZXIC_VOID);
-ZXIC_DOUBLE zxic_get_ticks_uses(ZXIC_VOID);
-#endif
-
-#if ZXIC_REAL("bit操作")
-
-/* ZXIC_UINT32 写某几bit的值 */
-#define ZXIC_COMM_MASK_BIT(intType,_bitNum_)\
-    (( intType )( 0x1U << (_bitNum_) ))
-
-#define ZXIC_COMM_GET_BIT_MASK( _intType_, _bitQnt_ )\
-    ( (_intType_)( ( (_bitQnt_) < 32 ) \
-      ? ( (_intType_) ZXIC_COMM_MASK_BIT( _intType_ , ( (_bitQnt_) & 0x1F ) ) - 1 ) \
-      : ((_intType_)(0xffffffff)) ) )
-
-#define ZXIC_COMM_UINT32_WRITE_BITS( _uiDst_, _uiSrc_, _uiStartPos_, _uiLen_ )\
-do{\
-    ( _uiDst_ ) = ( ( _uiDst_ ) & ~( ZXIC_COMM_GET_BIT_MASK( ZXIC_UINT32 , ( _uiLen_ ) ) << ( _uiStartPos_ ) ) ) |\
-                ( ( ( _uiSrc_ ) & ZXIC_COMM_GET_BIT_MASK( ZXIC_UINT32 , ( _uiLen_ ) ) ) << ( _uiStartPos_ ) );\
-}while(0)
-
-#define ZXIC_COMM_UINT32_WRITE_BITS_ZERO(_uiDst_, _uiStartPos_, _uiLen_ )\
-do{\
-    ( _uiDst_ ) = ( ( _uiDst_ ) & ~( ZXIC_COMM_GET_BIT_MASK( ZXIC_UINT32 , ( _uiLen_ ) ) << ( _uiStartPos_ ) ) );\
-}while(0)
-
-#define ZXIC_COMM_UINT32_GET_BITS(_uiDst_ ,_uiSrc_, _uiStartPos_, _uiLen_)\
-do{\
-    ( _uiDst_ ) =( ( (_uiSrc_) >> (_uiStartPos_) ) & \
-                ( ZXIC_COMM_GET_BIT_MASK( ZXIC_UINT32 , (_uiLen_) ) ) );\
-  }while(0)
-
-#define ZXIC_COMM_UINT32_GET_RETURN_BITS(_uiSrc_, _uiStartPos_, _uiLen_)\
-    ( ( (_uiSrc_) >> (_uiStartPos_) ) & \
-                ( ZXIC_COMM_GET_BIT_MASK( ZXIC_UINT32 , (_uiLen_) ) ) )\
-
-/* ZXIC_UINT64 写某几bit的值 */
-#define ZXIC_COMM_MASK_BIT_64(intType,_bitNum_)\
-    (( intType )( 0x1ULL << (_bitNum_) ))
-
-#define ZXIC_COMM_GET_64_BIT_MASK( _intType_, _bitQnt_ )\
-    ( (_intType_)( ( (_bitQnt_) < 64 ) \
-      ? ( (_intType_) ZXIC_COMM_MASK_BIT_64( _intType_ , ( (_bitQnt_) & 0x3F ) ) - 1 ) \
-      : ((_intType_)(0xFFFFFFFFFFFFFFFFULL)) ) )
-
-#define ZXIC_COMM_UINT64_WRITE_BITS( _uiDst_, _uiSrc_, _uiStartPos_, _uiLen_ )\
-do{\
-    ( _uiDst_ ) = ( ( _uiDst_ ) & ~( ZXIC_COMM_GET_64_BIT_MASK( ZXIC_UINT64 , ( _uiLen_ ) ) << ( _uiStartPos_ ) ) ) |\
-                ( ( ( _uiSrc_ ) & ZXIC_COMM_GET_64_BIT_MASK( ZXIC_UINT64 , ( _uiLen_ ) ) ) << ( _uiStartPos_ ) );\
-}while(0)
-
-/* Base type for declarations */
-#define ZXIC_COMM_BITDCL        ZXIC_UINT32
-#define ZXIC_COMM_BITWID        (32)
-
-/* (internal) Number of ZXICP_BITDCLs needed to contain _max bits */
-#define NPE_BITDCLSIZE(_max)    (((_max) + ZXIC_COMM_BITWID - 1) / ZXIC_COMM_BITWID)
-
-/* Size for giving to malloc and memset to handle _max bits */
-#define ZXIC_COMM_BITALLOCSIZE(_max) (NPE_BITDCLSIZE(_max) * sizeof (ZXIC_COMM_BITDCL))
-
-
-/* (internal) Generic operation macro on bit array _a, with bit _b */
-#define NPE_BITOP(_a, _b, _op)  (((_a)[(_b) / ZXIC_COMM_BITWID]) _op (1U << ((_b) % ZXIC_COMM_BITWID)))
-
-/* Specific operations */
-#define ZXIC_COMM_BITGET(_a, _b)    NPE_BITOP(_a, _b, &)
-#define ZXIC_COMM_BITSET(_a, _b)    NPE_BITOP(_a, _b, |=)
-#define ZXIC_COMM_BITCLR(_a, _b)    NPE_BITOP(_a, _b, &= ~)
-
-
-ZXIC_RTN32 zxic_comm_bit_count(ZXIC_UINT32 data);
-ZXIC_RTN32 zxic_comm_read_bits(ZXIC_UINT8 * p_base, ZXIC_UINT32 base_size_bit, ZXIC_UINT32 * p_data, ZXIC_UINT32 start_bit, ZXIC_UINT32 end_bit);
-ZXIC_RTN32 zxic_comm_write_bits(ZXIC_UINT8 * p_base, ZXIC_UINT32 base_size_bit, ZXIC_UINT32 data, ZXIC_UINT32 start_bit, ZXIC_UINT32 end_bit);
-ZXIC_RTN32 zxic_comm_write_bits_ex(ZXIC_UINT8 * p_base, ZXIC_UINT32 base_size_bit, ZXIC_UINT32 data, ZXIC_UINT32 msb_start_pos, ZXIC_UINT32 len);
-ZXIC_RTN32 zxic_comm_read_bits_ex(ZXIC_UINT8 * p_base, ZXIC_UINT32 base_size_bit, ZXIC_UINT32 * p_data, ZXIC_UINT32 msb_start_pos, ZXIC_UINT32 len);
-ZXIC_RTN32 zxic_comm_write_bits_op(ZXIC_UINT8* p_src_dat, ZXIC_UINT32 src_size_bit, ZXIC_UINT32 input_data, ZXIC_UINT32 start_bit, ZXIC_UINT32 end_bit);
-ZXIC_RTN32 zxic_comm_read_bits_op(ZXIC_UINT8*  p_src_dat, ZXIC_UINT32  src_size_bit, ZXIC_UINT32* p_out_data, ZXIC_UINT32  start_bit, ZXIC_UINT32  end_bit);
-#endif
-
-#if ZXIC_REAL("算数运算")
-ZXIC_UINT64 zxic_comm_get_gcd (ZXIC_UINT64 a, ZXIC_UINT64 b);
-ZXIC_RTN32 zxic_comm_multi_big_integer(ZXIC_CONST ZXIC_CHAR* num1,ZXIC_CONST ZXIC_CHAR* num2,ZXIC_CHAR* str_num);
-ZXIC_RTN32 zxic_comm_div_big_integer(ZXIC_CONST ZXIC_CHAR *num1,ZXIC_CONST ZXIC_CHAR *num2,ZXIC_UINT32 *quo_val);
-ZXIC_SINT32 zxic_comm_sub_stract(ZXIC_SINT32 *p1,ZXIC_SINT32 *p2,ZXIC_SINT32 len1,ZXIC_SINT32 len2 );
-ZXIC_SINT32 zxic_comm_cmpm_calc(ZXIC_UINT64 cm_cal, ZXIC_UINT64 pm_cal, ZXIC_UINT32* cm, ZXIC_UINT32* pm);
-ZXIC_VOID zxic_comm_pm_cm_cal(ZXIC_UINT64  cm_y, ZXIC_UINT64  pm_y, ZXIC_UINT32* cm, ZXIC_UINT32* pm);
-#endif
-
-#if ZXIC_REAL("字符串")
-ZXIC_RTN32 zxic_comm_strcasecmp(ZXIC_CHAR *str1, ZXIC_CHAR* str2);
-ZXIC_UINT8 zxic_comm_char_to_hex(ZXIC_UINT8 c);
-ZXIC_DWORD zxic_comm_ipaddr_to_dword(ZXIC_CONST ZXIC_CHAR *p_addr);
-ZXIC_RTN32 zxic_comm_char_to_number(ZXIC_CHAR a, ZXIC_CHAR b, ZXIC_UINT8 *number);
-ZXIC_CHAR *zxic_comm_strlower(ZXIC_CHAR *str);
-ZXIC_RTN32 ic_comm_check_str_size(ZXIC_CHAR* str);
-ZXIC_SIZE_T ic_comm_getAbsValue(ZXIC_UINT8* dest, ZXIC_CONST ZXIC_UINT8* src);
-ZXIC_VOID ic_comm_memset_s(void* dest, ZXIC_SIZE_T dmax, ZXIC_UINT8 c, ZXIC_SIZE_T n);
-ZXIC_SINT32 ic_comm_memcmp(void* str1, const void* str2, ZXIC_SIZE_T n);
-ZXIC_SINT32 ic_comm_strncmp(const ZXIC_CHAR* str1, const ZXIC_CHAR* str2, ZXIC_SIZE_T n);
-
-
-#endif
-
-#if ZXIC_REAL("dma内存分配")
-#define ZXIC_DMA_PHY_ADDR dma_addr_t
-ZXIC_RTN32 zxic_comm_dma_mem_malloc(ZXIC_ADDR_T *vir_addr,ZXIC_ADDR_T *phy_addr,ZXIC_UINT32 dma_size);
-ZXIC_RTN32 zxic_comm_dma_mem_free(ZXIC_ADDR_T vir_addr,ZXIC_ADDR_T phy_addr,ZXIC_UINT32 dma_size);
-#endif
-
-#if ZXIC_REAL("OTHER")
-#define MIN_VAL(x,y)                   ((x)<=(y) ? (x) : (y))
-#define MAX_VAL(x,y)                   ((x)<=(y) ? (y) : (x))
-#define ZXIC_COMM_DM_TO_X(d, m)        ((d) & ~(m))
-#define ZXIC_COMM_DM_TO_Y(d, m)        (~(d) & ~(m))
-#define ZXIC_COMM_XY_TO_MASK(x, y)     (~(x) & ~(y))
-#define ZXIC_COMM_XY_TO_DATA(x, y)     (x)             /* valid only when mask is 0 */
-#define ZXIC_RD_CNT_MAX                 (50)
-
-/* 新增常用数据掩码 */
-#define ZXIC_COMM_WORD64_MASK         (0xFFFFFFFFFFFFFFFFULL)
-#define ZXIC_COMM_WORD32_MASK         (0xFFFFFFFFU)
-#define ZXIC_COMM_WORD16_MASK         (0xFFFFU)
-#define ZXIC_COMM_BYTE_MASK           (0xFFU)
-
-ZXIC_RTN32 ZXIC_COMM_GET_MASK_VALUE(ZXIC_UINT32 total, ZXIC_UINT32 masklen);
-ZXIC_UINT32 zxic_comm_random(ZXIC_VOID);
-ZXIC_VOID zxic_comm_channel_max_set(ZXIC_UINT32 dev_max);
-
-ZXIC_RTN32 zxic_comm_channel_max_get(ZXIC_VOID);
-
-ZXIC_VOID zxic_comm_dbgcnt64_select_print(const ZXIC_CHAR * name, ZXIC_UINT64 value, ZXIC_UINT32 prt_mode);
-
-ZXIC_VOID zxic_comm_dbgcnt64_select_par_print(const ZXIC_CHAR * name, ZXIC_UINT32 parm, ZXIC_UINT64 value, ZXIC_UINT32 prt_mode);
-
-ZXIC_VOID zxic_comm_dbgcnt32_select_print(const ZXIC_CHAR * name, ZXIC_UINT32 value, ZXIC_UINT32 prt_mode);
-
-ZXIC_VOID zxic_comm_dbgcnt32_select_par_print(const ZXIC_CHAR * name, ZXIC_UINT32 parm, ZXIC_UINT32 value, ZXIC_UINT32 prt_mode);
-
-#define ZXIC_COMM_CHECK_ADD_CNT(x,y) (((0xffffffff - (x)) < (y)) ? ((y) - (0xffffffff - (x)) - 1) : ((x) + (y)))
-#define ZXIC_COMM_CHECK_ADD_CNT_WORD64(x,y) (((0xffffffffffffffff - (x)) < (y)) ? ((y) - (0xffffffffffffffff - (x)) - 1) : ((x) + (y)))
-#endif
-
-#if ZXIC_REAL("UT_TEST")
-
-ZXIC_VOID zxic_comm_ut_detail_info_trace(const ZXIC_CHAR *format, ...);
-
-ZXIC_VOID zxic_comm_ut_result_info_trace(const ZXIC_CHAR *format, ...);
-
-ZXIC_VOID zxic_comm_ut_detail_trace_error(const ZXIC_CHAR *format, ...);
-
-ZXIC_VOID zxic_comm_ut_detail_trace_dev_error(ZXIC_UINT32 dev_id, const ZXIC_CHAR *format, ...);
-
-#endif
-
-
-
-
-#if ZXIC_REAL("头文件")
-#include "zxic_comm_double_link.h"
-#include "zxic_comm_doublelink_index.h"
-#include "zxic_comm_liststack.h"
-#include "zxic_comm_avl_tree.h"
-#include "zxic_comm_rb_tree.h"
-#include "zxic_comm_index_ctrl.h"
-#include "zxic_comm_index_reserve.h"
-#include "zxic_comm_index_fill.h"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end __ZXIC_COMMON_H__ */
-
+/**************************************************************
+* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司
+* 文件名称      :       zxic_common.h
+* 文件标识      :
+* 内容摘要      :       大部分的项目,只需要感知这一个头文件即可,
+* 其包括了变量定义/打印/日志/参数校验/互斥锁/bit流拼接等常用定义和功能
+* 其它说明      :       编译宏：ZXIC_OS_WIN/ZXIC_RELEASE/MACRO_CPU64
+* 当前版本      :
+* 作    者    :
+* 完成日期      :       2020/07/20
+* DEPARTMENT:       有线开发四部-系统软件团队
+* MANUAL_PERCENT:   100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#ifndef __ZXIC_COMMON_H__
+#define __ZXIC_COMMON_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+    编译宏说明
+    ZXIC_OS_WIN :若不导入该宏,则默认为 ZXIC_OS_LINUX
+    ZXIC_RELEASE:若不导入该宏,则默认为 ZXIC_DEBUG
+    MACRO_CPU64 :若不导入该宏,则默认为32位操作系统
+    */
+
+#include "zxic_private_top.h"
+#include "zxic_private.h"
+//#include <ctype.h>
+//#include <stdlib.h>
+//#include <stdio.h>
+#include <linux/stddef.h>
+#include <linux/string.h>
+//#include <errno.h>
+//#include <assert.h>
+#include <stdarg.h>
+//#include <math.h>
+#include <linux/stat.h>
+//#include <stdint.h>
+
+#include <linux/unistd.h>
+#include <linux/types.h>
+#include <linux/socket.h>
+//#include <select.h>
+#include <linux/time.h>
+#include <linux/wait.h>
+#include <linux/kthread.h>
+#include <linux/fcntl.h>
+#include <linux/semaphore.h>
+#include <linux/slab.h>
+#include <linux/fs.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/printk.h>
+#include <linux/dma-mapping.h>
+
+#if ZXIC_REAL("数据类型定义")
+/* 无符号整数 */
+#define ZXIC_UINT8 unsigned char
+#define ZXIC_UINT16 unsigned short
+
+#ifndef ZXIC_UINT32
+#define ZXIC_UINT32 unsigned int
+#endif
+
+#ifndef ZXIC_UINT64
+#define ZXIC_UINT64 unsigned long long
+#endif
+#define ZXIC_DWORD \
+	unsigned long /* 慎用,注意:WIN系统:32bits       LINUX系统:64bits */
+#define ZXIC_SIZE_T size_t /* 32位系统:uint32 64位系统:uint64 */
+
+/* 有符号整数 */
+#define ZXIC_CHAR \
+	char /* char默认为unsigned还是signed取决于编译器,定义字符可用 */
+#define ZXIC_SINT8 signed char
+#define ZXIC_SINT16 signed short
+
+#ifndef ZXIC_SINT32
+#define ZXIC_SINT32 signed int
+#endif
+
+#ifndef ZXIC_SINT64
+#define ZXIC_SINT64 signed long long
+#endif
+
+#define ZXIC_SDWORD long
+
+/* 浮点数 */
+//#define ZXIC_FLOAT              float
+//#define ZXIC_DOUBLE             double
+//#define ZXIC_LDOUBLE            long double
+#define ZXIC_FLOAT int
+#define ZXIC_DOUBLE long
+#define ZXIC_LDOUBLE long long
+
+/* 文件类型 */
+typedef struct file ZXIC_FILE;
+
+/*  */
+#define ZXIC_VOL volatile
+#define ZXIC_VOID void
+#define ZXIC_CONST const
+#define ZXIC_RTN32 ZXIC_UINT32
+
+#ifdef MACRO_CPU64 /* 64位系统编译宏导入,慎重修改 */
+#define ZXIC_ADDR_T ZXIC_UINT64
+#define ZXIC_SIZEOF(x) \
+	(sizeof(x) & 0xFFFFFFFFU) /* 在64位环境下，sizeof的长度是64b */
+#define ZXIC_SIZEOF_T(x) ((ZXIC_UINT32)(sizeof(x) & 0xFFFFFFFF))
+
+#else
+#define ZXIC_ADDR_T ZXIC_UINT32
+#define ZXIC_SIZEOF(x) (sizeof(x))
+#define ZXIC_SIZEOF_T(x) (sizeof(x))
+#endif
+
+/* 特殊变量 */
+#define ZXIC_NULL (0)
+#define ZXIC_OK (0U) /* 后面加U,防止32位系统64位系统常量的默认长度不一致 */
+#define ZXIC_ERR (1U)
+#define ZXIC_TRUE (1U)
+#define ZXIC_FALSE (0U)
+#define ZXIC_UINT8_MAX (0xFFU)
+#define ZXIC_UINT32_MAX (0xFFFFFFFFU)
+#define ZXIC_ULONG_MAX (0xFFFFFFFFFFFFFFFFUL)
+#define ZXIC_SINT_MAX (0x7FFFFFFF)
+#define ZXIC_SINT_MIN (-ZXIC_SINT_MAX - 1)
+
+#define ZXIC_UINT64_MASK (0xFFFFFFFFFFFFFFFFULL)
+#define ZXIC_UINT32_MASK (0xFFFFFFFFU)
+#define ZXIC_UINT16_MASK (0xFFFFU)
+#define ZXIC_UINT8_MASK (0xFFU)
+#endif /* END 数据类型定义 */
+
+#if ZXIC_REAL("宏函数定义")
+#define ZXIC_COMM_MEMCMP ic_comm_memcmp
+#define ZXIC_COMM_MEMSET memset
+#define ZXIC_COMM_MEMMOVE memmove
+#define ZXIC_COMM_MEMSET_S ic_comm_memset_s
+#define ZXIC_COMM_MEMCPY ic_comm_memcpy
+#define ZXIC_COMM_MEMCPY_S ic_comm_memcpy_s
+#define ZXIC_COMM_STRLEN strlen
+#define ZXIC_COMM_STRNLEN strnlen
+#define ZXIC_COMM_STRNLEN_S ic_comm_strnlen_s
+#define ZXIC_COMM_STRCPY strcpy
+#define ZXIC_COMM_STRCPY_S ic_comm_strcpy_s
+#define ZXIC_COMM_STRNCPY strncpy
+#define ZXIC_COMM_STRNCPY_S ic_comm_strncpy_s
+#define ZXIC_COMM_STRCMP strcmp
+#define ZXIC_COMM_STRNCMP ic_comm_strncmp
+#define ZXIC_COMM_STRTOK strtok
+#define ZXIC_COMM_STRTOK_S ic_comm_strtok_s
+#define ZXIC_COMM_STRCAT_S ic_comm_strcat_s
+#define ZXIC_COMM_STRNCAT_S ic_comm_strncat_s
+
+//#define ZXIC_COMM_FOPEN              fopen
+#define ZXIC_COMM_FOPEN filp_open
+//#define ZXIC_COMM_FCLOSE             fclose
+#define ZXIC_COMM_FCLOSE(a) filp_close(a, NULL)
+#define ZXIC_COMM_FGETS fgets
+#define ZXIC_COMM_FPUTS fputs
+#define ZXIC_COMM_FREAD fread
+
+// #define ZXIC_COMM_FPRINTF            fprintf
+// #define ZXIC_COMM_FPRINTF(a,b,c)     printk(b,c)
+#define ZXIC_COMM_SSCANF ic_comm_sscanf
+#define ZXIC_COMM_FSCANF ((void)fscanf)
+#define ZXIC_COMM_SNPRINTF_S ic_comm_snprintf_s
+#define ZXIC_COMM_VSNPRINTF_S ic_comm_vsnprintf_s
+
+#define ZXIC_COMM_TIME time
+#define ZXIC_COMM_ATOI atoi
+
+#define ZXIC_COMM_ACCESS kern_path
+/*#define ZXIC_COMM_SNPRINTF           snprintf*/
+#define ZXIC_COMM_SNPRINTF(a, b, c...) __snprintf_chk(a, b, 0, b, c)
+#define ZXIC_COMM_VSNPRINTF vsnprintf
+#define ZXIC_COMM_GETPID getpid
+
+#ifdef MACRO_CPU64 /* 64位系统编译宏导入,慎重修改 */
+#define ZXIC_COMM_PTR_TO_VAL(p) ((ZXIC_UINT64)(p))
+#define ZXIC_COMM_VAL_TO_PTR(v) ((ZXIC_VOID *)((ZXIC_UINT64)(v)))
+#define ZXIC_SSIZE_T ZXIC_SINT64
+#else
+#define ZXIC_COMM_PTR_TO_VAL(p) ((ZXIC_UINT32)(p))
+#define ZXIC_COMM_VAL_TO_PTR(v) ((ZXIC_VOID *)(long)((ZXIC_UINT32)(v)))
+#define ZXIC_SSIZE_T ZXIC_SINT32
+
+#endif
+
+#define ZXIC_COMM_STRCASECMP strcasecmp
+
+#define ZXIC_COMM_FFLUSH ((ZXIC_VOID) fflush)
+#define ZXIC_COMM_SPRINTF ((ZXIC_VOID) sprintf)
+
+#define ZXIC_COMM_ASSERT(x)
+
+#endif /* END 宏函数定义 */
+
+#define ZXIC_COMM_MEMORY_MAX_B_SIZE (200 * 1024 * 1024) /* 200M */
+#define ZXIC_COMM_STRNLEN_MAX (0xffffffff)
+
+#if ZXIC_REAL("打印-print")
+#if ZXIC_REAL("开关")
+ZXIC_VOID zxic_comm_set_print_en(ZXIC_UINT32 enable);
+ZXIC_RTN32 zxic_comm_get_print_en(ZXIC_VOID);
+ZXIC_VOID zxic_comm_set_print_level(ZXIC_TRACE_LEVEL debug_level);
+ZXIC_RTN32 zxic_comm_get_print_level(ZXIC_VOID);
+#endif
+#if ZXIC_REAL("功能")
+ZXIC_VOID ZXIC_COMM_PRINT(ZXIC_CONST ZXIC_CHAR *format, ...);
+ZXIC_VOID ZXIC_COMM_TRACE_ERROR(ZXIC_CONST ZXIC_CHAR *format, ...);
+ZXIC_VOID ZXIC_COMM_TRACE_INFO(ZXIC_CONST ZXIC_CHAR *format, ...);
+ZXIC_VOID ZXIC_COMM_TRACE_DEBUG(ZXIC_CONST ZXIC_CHAR *format, ...);
+ZXIC_VOID ZXIC_COMM_TRACE_ALL(ZXIC_CONST ZXIC_CHAR *format, ...);
+
+ZXIC_VOID ZXIC_COMM_TRACE_DEV_ERROR(ZXIC_UINT32 dev_id,
+									ZXIC_CONST ZXIC_CHAR *format, ...);
+ZXIC_VOID ZXIC_COMM_TRACE_DEV_INFO(ZXIC_UINT32 dev_id,
+								   ZXIC_CONST ZXIC_CHAR *format, ...);
+ZXIC_VOID ZXIC_COMM_TRACE_DEV_DEBUG(ZXIC_UINT32 dev_id,
+									ZXIC_CONST ZXIC_CHAR *format, ...);
+ZXIC_VOID ZXIC_COMM_TRACE_DEV_ALL(ZXIC_UINT32 dev_id,
+								  ZXIC_CONST ZXIC_CHAR *format, ...);
+
+ZXIC_VOID ZXIC_COMM_DBGCNT64_PRINT(ZXIC_CONST ZXIC_CHAR *name,
+								   ZXIC_UINT64 value);
+ZXIC_VOID ZXIC_COMM_DBGCNT32_PRINT(ZXIC_CONST ZXIC_CHAR *name,
+								   ZXIC_UINT32 value);
+ZXIC_VOID ZXIC_COMM_DBGCNT32_PAR_PRINT(ZXIC_CONST ZXIC_CHAR *name,
+									   ZXIC_UINT32 parm, ZXIC_UINT32 value);
+
+#endif
+#endif
+
+#if ZXIC_REAL("互斥锁")
+ZXIC_RTN32 zxic_comm_mutex_create(ZXIC_MUTEX_T *p_mutex);
+ZXIC_RTN32 zxic_comm_mutex_lock(ZXIC_MUTEX_T *p_mutex);
+ZXIC_RTN32 zxic_comm_mutex_unlock(ZXIC_MUTEX_T *p_mutex);
+ZXIC_RTN32 zxic_comm_mutex_destroy(ZXIC_MUTEX_T *p_mutex);
+#endif
+
+#if ZXIC_REAL("信号量")
+ZXIC_RTN32 zxic_comm_sem_create(ZXIC_SEM_T * p_sem, ZXIC_SINT32 share,
+								ZXIC_SINT32 IniCount, ZXIC_SINT32 MaxCount);
+ZXIC_RTN32 zxic_comm_sem_release(ZXIC_SEM_T *p_sem);
+ZXIC_RTN32 zxic_comm_sem_wait(ZXIC_SEM_T *p_sem);
+#endif
+
+#if ZXIC_REAL("参数检查")
+
+#if ZXIC_REAL("NO DEV_ID & ASSERT")
+#define ZXIC_COMM_CHECK_RC(rc, becall)                                        \
+	do {                                                                      \
+		if (ZXIC_OK != rc) {                                                  \
+			ZXIC_COMM_TRACE_ERROR(                                            \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);            \
+			ZXIC_COMM_ASSERT(0);                                              \
+			return rc;                                                        \
+		}                                                                     \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_RC_MEMORY_FREE(rc, becall, ptr)                     \
+	do {                                                                    \
+		if (ZXIC_OK != rc) {                                                \
+			ZXIC_COMM_TRACE_ERROR(                                          \
+					"\n ZXICP  %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);          \
+			ZXIC_COMM_FREE(ptr);                                            \
+			ZXIC_COMM_ASSERT(0);                                            \
+			return rc;                                                      \
+		}                                                                   \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_POINT(point)                                      \
+	do {                                                                  \
+		if (ZXIC_NULL == (point)) {                                       \
+			ZXIC_COMM_TRACE_ERROR(                                        \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			ZXIC_COMM_ASSERT(0);                                          \
+			return ZXIC_PAR_CHK_POINT_NULL;                               \
+		}                                                                 \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_POINT_MEMORY_FREE(point, ptr)                     \
+	do {                                                                  \
+		if (ZXIC_NULL == (point)) {                                       \
+			ZXIC_COMM_TRACE_ERROR(                                        \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			ZXIC_COMM_FREE(ptr);                                          \
+			ZXIC_COMM_ASSERT(0);                                          \
+			return ZXIC_PAR_CHK_POINT_NULL;                               \
+		}                                                                 \
+	} while (0)
+#define ZXIC_COMM_CHECK_POINT_EMEMORY_FREE2PTR(point, ptr0, ptr1)         \
+	do {                                                                  \
+		if (ZXIC_NULL == (point)) {                                       \
+			ZXIC_COMM_TRACE_ERROR(                                        \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			ZXIC_COMM_FREE(ptr0);                                         \
+			ZXIC_COMM_FREE(ptr1);                                         \
+			ZXIC_COMM_ASSERT(0);                                          \
+			return ZXIC_PAR_CHK_POINT_NULL;                               \
+		}                                                                 \
+	} while (0)
+#define ZXIC_COMM_CHECK_POINT_RETURN_NULL(point)                          \
+	do {                                                                  \
+		if (ZXIC_NULL == (point)) {                                       \
+			ZXIC_COMM_TRACE_ERROR(                                        \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			ZXIC_COMM_ASSERT(0);                                          \
+			return ZXIC_NULL;                                             \
+		}                                                                 \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX(val, min, max)                                                      \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_index_check(val, min, max)) {                                               \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_index_check(val, min, max)) {                                        \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_RANGE;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_EQUAL(val, equal)                                            \
+	do {                                                                                   \
+		if (val == equal) {                                                                \
+			ZXIC_COMM_TRACE_ERROR(                                                         \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [equal=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, equal, __FUNCTION__);                         \
+			ZXIC_COMM_ASSERT(0);                                                           \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                             \
+		}                                                                                  \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_EQUAL_RETURN_OK(val, equal) \
+	do {                                                  \
+		if (val == equal) {                               \
+			return ZXIC_OK;                               \
+		}                                                 \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_NOT_EQUAL(val, equal)                                        \
+	do {                                                                                   \
+		if (val != equal) {                                                                \
+			ZXIC_COMM_TRACE_ERROR(                                                         \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [equal=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, equal, __FUNCTION__);                         \
+			ZXIC_COMM_ASSERT(0);                                                           \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                             \
+		}                                                                                  \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_UPPER(val, max)                                            \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+			ZXIC_COMM_ASSERT(0);                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                           \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_LOWER(val, min)                                            \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+			ZXIC_COMM_ASSERT(0);                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                           \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_BOTH(val, min, max)                                                 \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_UPPER_MEMORY_FREE(val, max, ptr)                           \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+			ZXIC_COMM_FREE(ptr);                                                         \
+			ZXIC_COMM_ASSERT(0);                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                           \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_LOWER_MEMORY_FREE(val, min, ptr)                           \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+			ZXIC_COMM_FREE(ptr);                                                         \
+			ZXIC_COMM_ASSERT(0);                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                           \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_BOTH_MEMORY_FREE(val, min, max, ptr)                                \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr);                                                                  \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_MEMORY_FREE(val0, val1, ptr)                        \
+	do {                                                                                       \
+		if ((ZXIC_UINT32_MAX - (val0)) < (val1)) {                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr);                                                               \
+			ZXIC_COMM_ASSERT(0);                                                               \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                 \
+		}                                                                                      \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(val0, val1)                                         \
+	do {                                                                                       \
+		if ((ZXIC_UINT32_MAX - (val0)) < (val1)) {                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                               \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                 \
+		}                                                                                      \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_64(val0, val1)                                                \
+	do {                                                                                                 \
+		if ((ZXIC_ULONG_MAX - (val0)) < (val1)) {                                                        \
+			ZXIC_COMM_TRACE_ERROR(                                                                       \
+					"\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                                       \
+			ZXIC_COMM_ASSERT(0);                                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                           \
+		}                                                                                                \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_UNLOCK(val0, val1, mutex)                              \
+	do {                                                                                          \
+		if ((ZXIC_UINT32_MAX - (val0)) < (val1)) {                                                \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n",    \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                                \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(val0, val1)                                         \
+	do {                                                                                       \
+		if ((val0) < (val1)) {                                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                               \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                 \
+		}                                                                                      \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_64(val0, val1)                                                \
+	do {                                                                                                 \
+		if ((val0) < (val1)) {                                                                           \
+			ZXIC_COMM_TRACE_ERROR(                                                                       \
+					"\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                                       \
+			ZXIC_COMM_ASSERT(0);                                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                           \
+		}                                                                                                \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_UNLOCK(val0, val1, mutex)                              \
+	do {                                                                                          \
+		if ((val0) < (val1)) {                                                                    \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n",    \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                                \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW(val0, val1)                                         \
+	do {                                                                                       \
+		if (((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1))) {                           \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                               \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                 \
+		}                                                                                      \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_64(val0, val1)                                                \
+	do {                                                                                                 \
+		if (((val0) > 0) && ((ZXIC_ULONG_MAX / (val0)) < (val1))) {                                      \
+			ZXIC_COMM_TRACE_ERROR(                                                                       \
+					"\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                                       \
+			ZXIC_COMM_ASSERT(0);                                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                           \
+		}                                                                                                \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_UNLOCK(val0, val1, mutex)                              \
+	do {                                                                                          \
+		if (((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1))) {                              \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n",    \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                                \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_RETURN_NULL(val, min, max)                                          \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_index_check(val, min, max)) {                                               \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_NULL;                                                                     \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_index_check(val, min, max)) {                                        \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_NULL;                                                                     \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_RC_UNLOCK(rc, becall, mutex)                                              \
+	do {                                                                                          \
+		if (ZXIC_OK != rc) {                                                                      \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",                     \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);                                \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return rc;                                                                            \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_RC_CLOSE_FP(rc, becall, fp)                           \
+	do {                                                                      \
+		if (ZXIC_OK != rc) {                                                  \
+			ZXIC_COMM_TRACE_ERROR(                                            \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);            \
+			if (ZXIC_COMM_FCLOSE(fp)) {                                       \
+				ZXIC_COMM_TRACE_ERROR(                                        \
+						"\n ZXIC  %s:%d !-- %s close file Fail!\n", __FILE__, \
+						__LINE__, __FUNCTION__);                              \
+			}                                                                 \
+			ZXIC_COMM_ASSERT(0);                                              \
+			return rc;                                                        \
+		}                                                                     \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_POINT_CLOSE_FP(point, fp)                             \
+	do {                                                                      \
+		if (NULL == (point)) {                                                \
+			ZXIC_COMM_TRACE_ERROR(                                            \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",     \
+					__FILE__, __LINE__, __FUNCTION__);                        \
+			if (ZXIC_COMM_FCLOSE(fp)) {                                       \
+				ZXIC_COMM_TRACE_ERROR(                                        \
+						"\n ZXIC  %s:%d !-- %s close file Fail!\n", __FILE__, \
+						__LINE__, __FUNCTION__);                              \
+			}                                                                 \
+			ZXIC_COMM_ASSERT(0);                                              \
+			return ZXIC_PAR_CHK_POINT_NULL;                                   \
+		}                                                                     \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_RETURN(val0, val1)                                   \
+	do {                                                                                        \
+		if ((0xFFFFFFFF - (val0)) < (val1)) {                                                   \
+			ZXIC_COMM_TRACE_ERROR(                                                              \
+					"ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                              \
+			return;                                                                             \
+		}                                                                                       \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_RETURN(val0, val1)                                   \
+	do {                                                                                        \
+		if (val0 < val1) {                                                                      \
+			ZXIC_COMM_TRACE_ERROR(                                                              \
+					"ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                              \
+			return;                                                                             \
+		}                                                                                       \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_CLOSE_FP_NO_ASSERT(                              \
+		dev_id, val0, val1, fp)                                                                 \
+	do {                                                                                        \
+		if ((0xFFFFFFFF - (val0)) < (val1)) {                                                   \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                          \
+					dev_id,                                                                     \
+					"ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                              \
+			if (ZXIC_COMM_FCLOSE(fp)) {                                                         \
+				ZXIC_COMM_TRACE_DEV_ERROR(                                                      \
+						dev_id, "\n ICM  %s:%d !-- %s close file Fail!\n",                      \
+						__FILE__, __LINE__, __FUNCTION__);                                      \
+			}                                                                                   \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                  \
+		}                                                                                       \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_CLOSE_FP_NO_ASSERT(                              \
+		dev_id, val0, val1, fp)                                                                 \
+	do {                                                                                        \
+		if ((val0 > 0) && ((0xFFFFFFFF / (val0)) < (val1))) {                                   \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                          \
+					dev_id,                                                                     \
+					"ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                              \
+			if (ZXIC_COMM_FCLOSE(fp)) {                                                         \
+				ZXIC_COMM_TRACE_DEV_ERROR(                                                      \
+						dev_id, "\n ICM  %s:%d !-- %s close file Fail!\n",                      \
+						__FILE__, __LINE__, __FUNCTION__);                                      \
+			}                                                                                   \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                  \
+		}                                                                                       \
+	} while (0)
+
+#endif
+
+#if ZXIC_REAL("NO DEV_ID & NO ASSERT")
+#define ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, becall)                              \
+	do {                                                                      \
+		if (ZXIC_OK != rc) {                                                  \
+			ZXIC_COMM_TRACE_ERROR(                                            \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);            \
+			return rc;                                                        \
+		}                                                                     \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_RC_NO_ASSERT_UNLOCK(rc, becall, mutex)                                    \
+	do {                                                                                          \
+		if (ZXIC_OK != rc) {                                                                      \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",                     \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);                                \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return rc;                                                                            \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, becall, ptr)           \
+	do {                                                                    \
+		if (ZXIC_OK != rc) {                                                \
+			ZXIC_COMM_TRACE_ERROR(                                          \
+					"\n ZXICP  %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);          \
+			ZXIC_COMM_FREE(ptr);                                            \
+			return rc;                                                      \
+		}                                                                   \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_RC_MEMORY_FREE2PTR_NO_ASSERT(rc, becall, ptr1, ptr2) \
+	do {                                                                     \
+		if (ZXIC_OK != rc) {                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                           \
+					"\n ZXICP  %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n",  \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);           \
+			ZXIC_COMM_FREE(ptr1);                                            \
+			ZXIC_COMM_FREE(ptr2);                                            \
+			return rc;                                                       \
+		}                                                                    \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, becall, ptr1, ptr2, \
+													 ptr3)                   \
+	do {                                                                     \
+		if (ZXIC_OK != rc) {                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                           \
+					"\n ZXICP  %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n",  \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);           \
+			ZXIC_COMM_FREE(ptr1);                                            \
+			ZXIC_COMM_FREE(ptr2);                                            \
+			ZXIC_COMM_FREE(ptr3);                                            \
+			return rc;                                                       \
+		}                                                                    \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_POINT_NO_ASSERT(point)                            \
+	do {                                                                  \
+		if (ZXIC_NULL == (point)) {                                       \
+			ZXIC_COMM_TRACE_ERROR(                                        \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			return ZXIC_PAR_CHK_POINT_NULL;                               \
+		}                                                                 \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_POINT_CLOSE_FP_NO_ASSERT(point, fp)                   \
+	do {                                                                      \
+		if (NULL == (point)) {                                                \
+			ZXIC_COMM_TRACE_ERROR(                                            \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",     \
+					__FILE__, __LINE__, __FUNCTION__);                        \
+			if (ZXIC_COMM_FCLOSE(fp)) {                                       \
+				ZXIC_COMM_TRACE_ERROR(                                        \
+						"\n ZXIC  %s:%d !-- %s close file Fail!\n", __FILE__, \
+						__LINE__, __FUNCTION__);                              \
+			}                                                                 \
+			return ZXIC_PAR_CHK_POINT_NULL;                                   \
+		}                                                                     \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(point, ptr)           \
+	do {                                                                  \
+		if (ZXIC_NULL == (point)) {                                       \
+			ZXIC_COMM_TRACE_ERROR(                                        \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			ZXIC_COMM_FREE(ptr);                                          \
+			return ZXIC_PAR_CHK_POINT_NULL;                               \
+		}                                                                 \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_POINT_MEMORY_FREE2PTR_NO_ASSERT(point, ptr1, ptr2) \
+	do {                                                                   \
+		if (ZXIC_NULL == (point)) {                                        \
+			ZXIC_COMM_TRACE_ERROR(                                         \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",  \
+					__FILE__, __LINE__, __FUNCTION__);                     \
+			ZXIC_COMM_FREE(ptr1);                                          \
+			ZXIC_COMM_FREE(ptr2);                                          \
+			return ZXIC_PAR_CHK_POINT_NULL;                                \
+		}                                                                  \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_POINT_MEMORY_FREE3PTR_NO_ASSERT(point, ptr1, ptr2, \
+														ptr3)              \
+	do {                                                                   \
+		if (ZXIC_NULL == (point)) {                                        \
+			ZXIC_COMM_TRACE_ERROR(                                         \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",  \
+					__FILE__, __LINE__, __FUNCTION__);                     \
+			ZXIC_COMM_FREE(ptr1);                                          \
+			ZXIC_COMM_FREE(ptr2);                                          \
+			ZXIC_COMM_FREE(ptr3);                                          \
+			return ZXIC_PAR_CHK_POINT_NULL;                                \
+		}                                                                  \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_NO_ASSERT(val, min, max)                                            \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_index_check(val, min, max)) {                                               \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_index_check(val, min, max)) {                                        \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			return ZXIC_PAR_CHK_INVALID_RANGE;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_NO_ASSERT_UNLOCK(val, min, max, mutex)                              \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_index_check(val, min, max)) {                                               \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_index_check(val, min, max)) {                                        \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_RANGE;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_UPPER_NO_ASSERT(val, max)                                  \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                           \
+		}                                                                                \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_UPPER_NO_ASSERT_UNLOCK(val, max, mutex)                             \
+	do {                                                                                          \
+		if ((val) > (max)) {                                                                      \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n",          \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                                  \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_UPPER_MEMORY_FREE_NO_ASSERT(val, max, ptr)                 \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+			ZXIC_COMM_FREE(ptr);                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                           \
+		}                                                                                \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_LOWER_NO_ASSERT(val, min)                                  \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                           \
+		}                                                                                \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_LOWER_NO_ASSERT_UNLOCK(val, min, mutex)                             \
+	do {                                                                                          \
+		if ((val) < (min)) {                                                                      \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n",          \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                                  \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_LOWER_MEMORY_FREE_NO_ASSERT(val, min, ptr)                 \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+			ZXIC_COMM_FREE(ptr);                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                           \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_BOTH_NO_ASSERT(val, min, max)                                       \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_BOTH_NO_ASSERT_UNLOCK(val, min, max, mutex)                         \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_BOTH_MEMORY_FREE_NO_ASSERT(val, min, max, ptr)                      \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(val0, val1)                               \
+	do {                                                                                       \
+		if ((ZXIC_UINT32_MAX - (val0)) < (val1)) {                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                 \
+		}                                                                                      \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_64_NO_ASSERT(val0, val1)                            \
+	do {                                                                                       \
+		if ((ZXIC_ULONG_MAX - (val0)) < (val1)) {                                              \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                 \
+		}                                                                                      \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT_UNLOCK(val0, val1, mutex)                    \
+	do {                                                                                          \
+		if ((ZXIC_UINT32_MAX - (val0)) < (val1)) {                                                \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n",    \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                                \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_ASSERT(val0, val1)                               \
+	do {                                                                                       \
+		if ((val0) < (val1)) {                                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                 \
+		}                                                                                      \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_ASSERT_UNLOCK(val0, val1, mutex)                    \
+	do {                                                                                          \
+		if ((val0) < (val1)) {                                                                    \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n",    \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                                \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(val0, val1)                               \
+	do {                                                                                       \
+		if (((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1))) {                           \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                 \
+		}                                                                                      \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT_UNLOCK(val0, val1, mutex)                    \
+	do {                                                                                          \
+		if (((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1))) {                              \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n",    \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                                \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_RETURN_VOID_NO_ASSERT(val, min, max)                                \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_index_check(val, min, max)) {                                               \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			return;                                                                               \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_index_check(val, min, max)) {                                        \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			return;                                                                               \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_RETURN_NULL_NO_ASSERT(val, min, max)                                \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_index_check(val, min, max)) {                                               \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			return ZXIC_NULL;                                                                     \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_index_check(val, min, max)) {                                        \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			return ZXIC_NULL;                                                                     \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_CLOSE_FP_NO_ASSERT(val, min, max, fp)                               \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_index_check(val, min, max)) {                                               \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			if (ZXIC_COMM_FCLOSE(fp)) {                                                           \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"\n ZXIC  %s:%d !-- %s close file Fail!\n", __FILE__,                     \
+						__LINE__, __FUNCTION__);                                                  \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_index_check(val, min, max)) {                                        \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			if (ZXIC_COMM_FCLOSE(fp)) {                                                           \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"\n ZXIC  %s:%d !-- %s close file Fail!\n", __FILE__,                     \
+						__LINE__, __FUNCTION__);                                                  \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_RANGE;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_MEMORY_FREE_NO_ASSERT(val, min, max, ptr)                           \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_index_check(val, min, max)) {                                               \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_index_check(val, min, max)) {                                        \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_RANGE;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_MEMORY_FREE2PTR_NO_ASSERT(val, min, max, ptr1,                      \
+														ptr2)                                     \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_index_check(val, min, max)) {                                               \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr1);                                                                 \
+			ZXIC_COMM_FREE(ptr2);                                                                 \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_index_check(val, min, max)) {                                        \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr1);                                                                 \
+			ZXIC_COMM_FREE(ptr2);                                                                 \
+			return ZXIC_PAR_CHK_INVALID_RANGE;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_MEMORY_FREE3PTR_NO_ASSERT(val, min, max, ptr1,                      \
+														ptr2, ptr3)                               \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_index_check(val, min, max)) {                                               \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr1);                                                                 \
+			ZXIC_COMM_FREE(ptr2);                                                                 \
+			ZXIC_COMM_FREE(ptr3);                                                                 \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_index_check(val, min, max)) {                                        \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr1);                                                                 \
+			ZXIC_COMM_FREE(ptr2);                                                                 \
+			ZXIC_COMM_FREE(ptr3);                                                                 \
+			return ZXIC_PAR_CHK_INVALID_RANGE;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#endif
+
+#if ZXIC_REAL("DEV_ID & ASSERT")
+
+#define ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, becall)                            \
+	do {                                                                      \
+		if (ZXIC_OK != rc) {                                                  \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                        \
+					dev_id,                                                   \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);            \
+			ZXIC_COMM_ASSERT(0);                                              \
+			return rc;                                                        \
+		}                                                                     \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_RC_NULL(dev_id, rc, becall)                       \
+	do {                                                                      \
+		if (ZXIC_OK != rc) {                                                  \
+			ZXIC_COMM_TRACE_ERROR(                                            \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);            \
+			ZXIC_COMM_ASSERT(0);                                              \
+			return NULL;                                                      \
+		}                                                                     \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, becall, mutex)                                  \
+	do {                                                                                          \
+		if (ZXIC_OK != rc) {                                                                      \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",                     \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);                                \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return rc;                                                                            \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_RC_CLOSE_FP(dev_id, rc, becall, fp)               \
+	do {                                                                      \
+		if (ZXIC_OK != rc) {                                                  \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                        \
+					dev_id,                                                   \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);            \
+			if (ZXIC_COMM_FCLOSE(fp)) {                                       \
+				ZXIC_COMM_TRACE_ERROR(                                        \
+						"\n ZXIC  %s:%d !-- %s close file Fail!\n", __FILE__, \
+						__LINE__, __FUNCTION__);                              \
+			}                                                                 \
+			ZXIC_COMM_ASSERT(0);                                              \
+			return rc;                                                        \
+		}                                                                     \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE(dev_id, rc, becall, ptr)         \
+	do {                                                                    \
+		if (ZXIC_OK != rc) {                                                \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                      \
+					dev_id,                                                 \
+					"\n ZXICP  %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);          \
+			ZXIC_COMM_FREE(ptr);                                            \
+			ZXIC_COMM_ASSERT(0);                                            \
+			return rc;                                                      \
+		}                                                                   \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_POINT(dev_id, point)                          \
+	do {                                                                  \
+		if (NULL == (point)) {                                            \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                    \
+					dev_id,                                               \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			ZXIC_COMM_ASSERT(0);                                          \
+			return ZXIC_PAR_CHK_POINT_NULL;                               \
+		}                                                                 \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE(dev_id, point, ptr)         \
+	do {                                                                  \
+		if (ZXIC_NULL == (point)) {                                       \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                    \
+					dev_id,                                               \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			ZXIC_COMM_FREE(ptr);                                          \
+			ZXIC_COMM_ASSERT(0);                                          \
+			return ZXIC_PAR_CHK_POINT_NULL;                               \
+		}                                                                 \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_POINT_EMEMORY_FREE2PTR(dev_id, point, ptr0, ptr1) \
+	do {                                                                      \
+		if (ZXIC_NULL == (point)) {                                           \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                        \
+					dev_id,                                                   \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",     \
+					__FILE__, __LINE__, __FUNCTION__);                        \
+			ZXIC_COMM_FREE(ptr0);                                             \
+			ZXIC_COMM_FREE(ptr1);                                             \
+			ZXIC_COMM_ASSERT(0);                                              \
+			return ZXIC_PAR_CHK_POINT_NULL;                                   \
+		}                                                                     \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_POINT_RETURN_NULL(dev_id, point)              \
+	do {                                                                  \
+		if (NULL == (point)) {                                            \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                    \
+					dev_id,                                               \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			ZXIC_COMM_ASSERT(0);                                          \
+			return ZXIC_NULL;                                             \
+		}                                                                 \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_POINT_UNLOCK(dev_id, point, mutex)                                    \
+	do {                                                                                          \
+		if (NULL == (point)) {                                                                    \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",                         \
+					__FILE__, __LINE__, __FUNCTION__);                                            \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_PAR_CHK_POINT_NULL;                                                       \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_POINT_CLOSE_FP(dev_id, point, fp)               \
+	do {                                                                    \
+		if (NULL == (point)) {                                              \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                      \
+					dev_id,                                                 \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",   \
+					__FILE__, __LINE__, __FUNCTION__);                      \
+			if (ZXIC_COMM_FCLOSE(fp)) {                                     \
+				ZXIC_COMM_TRACE_DEV_ERROR(                                  \
+						dev_id, "\n ZXIC  %s:%d !-- %s close file Fail!\n", \
+						__FILE__, __LINE__, __FUNCTION__);                  \
+			}                                                               \
+			ZXIC_COMM_ASSERT(0);                                            \
+			return ZXIC_PAR_CHK_POINT_NULL;                                 \
+		}                                                                   \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX(dev_id, val, min, max)                                          \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_dev_index_check(dev_id, val, min, max)) {                                   \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_dev_index_check(dev_id, val, min, max)) {                            \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_RANGE;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER(dev_id, val, max)                                \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+			ZXIC_COMM_ASSERT(0);                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                           \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER(dev_id, val, min)                                \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+			ZXIC_COMM_ASSERT(0);                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                           \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH(dev_id, val, min, max)                                     \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_MEMORY_FREE(dev_id, val, max, ptr)               \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+			ZXIC_COMM_FREE(ptr);                                                         \
+			ZXIC_COMM_ASSERT(0);                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                           \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_MEMORY_FREE(dev_id, val, min, ptr)               \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+			ZXIC_COMM_FREE(ptr);                                                         \
+			ZXIC_COMM_ASSERT(0);                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                           \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_MEMORY_FREE(dev_id, val, min, max, ptr)                    \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr);                                                                  \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_RETURN_NULL(dev_id, val, min, max)                              \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_index_check(val, min, max)) {                                               \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_NULL;                                                                     \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_index_check(val, min, max)) {                                        \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_NULL;                                                                     \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_ID(dev_id)                                                            \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_index_check(dev_id, 0,                                                      \
+								  zxic_comm_channel_max_get() - 1)) {                             \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, dev_id, 0,                                                \
+					zxic_comm_channel_max_get() - 1, __FUNCTION__);                               \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_index_check(dev_id, 0,                                               \
+										 zxic_comm_channel_max_get() - 1)) {                      \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, dev_id, 0,                                                \
+					zxic_comm_channel_max_get() - 1, __FUNCTION__);                               \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_RANGE;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW(dev_id, val0, val1)                             \
+	do {                                                                                       \
+		if ((ZXIC_UINT32_MAX - (val0)) < (val1)) {                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                         \
+					dev_id,                                                                    \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                               \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                 \
+		}                                                                                      \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64(dev_id, val0, val1)                                    \
+	do {                                                                                                 \
+		if ((ZXIC_ULONG_MAX - (val0)) < (val1)) {                                                        \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                                   \
+					dev_id,                                                                              \
+					"\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                                       \
+			ZXIC_COMM_ASSERT(0);                                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                           \
+		}                                                                                                \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW(dev_id, val0, val1)                             \
+	do {                                                                                       \
+		if ((val0) < (val1)) {                                                                 \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                         \
+					dev_id,                                                                    \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                               \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                 \
+		}                                                                                      \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW(dev_id, val0, val1)                             \
+	do {                                                                                       \
+		if (((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1))) {                           \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                         \
+					dev_id,                                                                    \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                               \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                 \
+		}                                                                                      \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_64(dev_id, val0, val1)                                    \
+	do {                                                                                                 \
+		if (((val0) > 0) && ((0xFFFFFFFFFFFFFFFF / (val0)) < (val1))) {                                  \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                                   \
+					dev_id,                                                                              \
+					"\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                                       \
+			ZXIC_COMM_ASSERT(0);                                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                           \
+		}                                                                                                \
+	} while (0)
+
+#endif
+
+#if ZXIC_REAL("DEV_ID & NO ASSERT")
+#define ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, becall)                  \
+	do {                                                                      \
+		if (ZXIC_OK != rc) {                                                  \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                        \
+					dev_id,                                                   \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);            \
+			return rc;                                                        \
+		}                                                                     \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(dev_id, rc, becall, mutex)                        \
+	do {                                                                                          \
+		if (ZXIC_OK != rc) {                                                                      \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",                     \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);                                \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return rc;                                                                            \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_RC_CLOSE_FP_NO_ASSERT(dev_id, rc, becall, fp)     \
+	do {                                                                      \
+		if (ZXIC_OK != rc) {                                                  \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                        \
+					dev_id,                                                   \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);            \
+			if (ZXIC_COMM_FCLOSE(fp)) {                                       \
+				ZXIC_COMM_TRACE_DEV_ERROR(                                    \
+						dev_id, "\n ZXIC  %s:%d !-- %s close file Fail!\n",   \
+						__FILE__, __LINE__, __FUNCTION__);                    \
+			}                                                                 \
+			return rc;                                                        \
+		}                                                                     \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE_NO_ASSERT(dev_id, rc, becall, ptr) \
+	do {                                                                      \
+		if (ZXIC_OK != rc) {                                                  \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                        \
+					dev_id,                                                   \
+					"\n ZXICP  %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n",   \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);            \
+			ZXIC_COMM_FREE(ptr);                                              \
+			return rc;                                                        \
+		}                                                                     \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE2PTR_NO_ASSERT(dev_id, rc, becall, \
+														 ptr1, ptr2)         \
+	do {                                                                     \
+		if (ZXIC_OK != rc) {                                                 \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                       \
+					dev_id,                                                  \
+					"\n ZXICP  %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n",  \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);           \
+			ZXIC_COMM_FREE(ptr1);                                            \
+			ZXIC_COMM_FREE(ptr2);                                            \
+			return rc;                                                       \
+		}                                                                    \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE3PTR_NO_ASSERT(dev_id, rc, becall, \
+														 ptr1, ptr2, ptr3)   \
+	do {                                                                     \
+		if (ZXIC_OK != rc) {                                                 \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                       \
+					dev_id,                                                  \
+					"\n ZXICP  %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n",  \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);           \
+			ZXIC_COMM_FREE(ptr1);                                            \
+			ZXIC_COMM_FREE(ptr2);                                            \
+			ZXIC_COMM_FREE(ptr3);                                            \
+			return rc;                                                       \
+		}                                                                    \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_POINT_NO_ASSERT(dev_id, point)                \
+	do {                                                                  \
+		if (NULL == (point)) {                                            \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                    \
+					dev_id,                                               \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			return ZXIC_PAR_CHK_POINT_NULL;                               \
+		}                                                                 \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_POINT_RETURN_NULL_NO_ASSERT(dev_id, point)    \
+	do {                                                                  \
+		if (ZXIC_NULL == (point)) {                                       \
+			ZXIC_COMM_TRACE_ERROR(                                        \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			return ZXIC_NULL;                                             \
+		}                                                                 \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_POINT_CLOSE_FP_NO_ASSERT(dev_id, point, fp)     \
+	do {                                                                    \
+		if (NULL == (point)) {                                              \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                      \
+					dev_id,                                                 \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",   \
+					__FILE__, __LINE__, __FUNCTION__);                      \
+			if (ZXIC_COMM_FCLOSE(fp)) {                                     \
+				ZXIC_COMM_TRACE_DEV_ERROR(                                  \
+						dev_id, "\n ZXIC  %s:%d !-- %s close file Fail!\n", \
+						__FILE__, __LINE__, __FUNCTION__);                  \
+			}                                                               \
+			return ZXIC_PAR_CHK_POINT_NULL;                                 \
+		}                                                                   \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE_NO_ASSERT(dev_id, point, ptr) \
+	do {                                                                    \
+		if (ZXIC_NULL == (point)) {                                         \
+			ZXIC_COMM_TRACE_ERROR(                                          \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",   \
+					__FILE__, __LINE__, __FUNCTION__);                      \
+			ZXIC_COMM_FREE(ptr);                                            \
+			return ZXIC_PAR_CHK_POINT_NULL;                                 \
+		}                                                                   \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE2PTR_NO_ASSERT(dev_id, point, \
+															ptr1, ptr2)    \
+	do {                                                                   \
+		if (ZXIC_NULL == (point)) {                                        \
+			ZXIC_COMM_TRACE_ERROR(                                         \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",  \
+					__FILE__, __LINE__, __FUNCTION__);                     \
+			ZXIC_COMM_FREE(ptr1);                                          \
+			ZXIC_COMM_FREE(ptr2);                                          \
+			return ZXIC_PAR_CHK_POINT_NULL;                                \
+		}                                                                  \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE3PTR_NO_ASSERT(dev_id, point,    \
+															ptr1, ptr2, ptr3) \
+	do {                                                                      \
+		if (ZXIC_NULL == (point)) {                                           \
+			ZXIC_COMM_TRACE_ERROR(                                            \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",     \
+					__FILE__, __LINE__, __FUNCTION__);                        \
+			ZXIC_COMM_FREE(ptr1);                                             \
+			ZXIC_COMM_FREE(ptr2);                                             \
+			ZXIC_COMM_FREE(ptr3);                                             \
+			return ZXIC_PAR_CHK_POINT_NULL;                                   \
+		}                                                                     \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, val, min, max)                                \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_dev_index_check(dev_id, val, min, max)) {                                   \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_dev_index_check(dev_id, val, min, max)) {                            \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			return ZXIC_PAR_CHK_INVALID_RANGE;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT_UNLOCK(dev_id, val, min, max,                         \
+												   mutex)                                         \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_dev_index_check(dev_id, val, min, max)) {                                   \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_dev_index_check(dev_id, val, min, max)) {                            \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_RANGE;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_NO_ASSERT(dev_id, val, max)                      \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                           \
+		}                                                                                \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_NO_ASSERT_UNLOCK(dev_id, val, max,                        \
+														 mutex)                                   \
+	do {                                                                                          \
+		if ((val) > (max)) {                                                                      \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n",          \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                                  \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_MEMORY_FREE_NO_ASSERT(dev_id, val,               \
+															  max, ptr)                  \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+			ZXIC_COMM_FREE(ptr);                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                           \
+		}                                                                                \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_NO_ASSERT(dev_id, val, min)                      \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                           \
+		}                                                                                \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_NO_ASSERT_UNLOCK(dev_id, val, min,                        \
+														 mutex)                                   \
+	do {                                                                                          \
+		if ((val) < (min)) {                                                                      \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n",          \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                                  \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_MEMORY_FREE_NO_ASSERT(dev_id, val,               \
+															  min, ptr)                  \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+			ZXIC_COMM_FREE(ptr);                                                         \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                           \
+		}                                                                                \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_NO_ASSERT(dev_id, val, min, max)                           \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_NO_ASSERT_UNLOCK(dev_id, val, min, max,                    \
+														mutex)                                    \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_MEMORY_FREE_NO_ASSERT(dev_id, val, min,                    \
+															 max, ptr)                            \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_RETURN_NULL_NO_ASSERT(dev_id, val, min, max)                    \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_index_check(val, min, max)) {                                               \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			return ZXIC_NULL;                                                                     \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_index_check(val, min, max)) {                                        \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			return ZXIC_NULL;                                                                     \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, val, min, max,                    \
+														ptr)                                      \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_dev_index_check(dev_id, val, min, max)) {                                   \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_dev_index_check(dev_id, val, min, max)) {                            \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr);                                                                  \
+			return ZXIC_PAR_CHK_INVALID_RANGE;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE2PTR_NO_ASSERT(dev_id, val, min,                     \
+															max, ptr1, ptr2)                      \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_dev_index_check(dev_id, val, min, max)) {                                   \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr1);                                                                 \
+			ZXIC_COMM_FREE(ptr2);                                                                 \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_dev_index_check(dev_id, val, min, max)) {                            \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr1);                                                                 \
+			ZXIC_COMM_FREE(ptr2);                                                                 \
+			return ZXIC_PAR_CHK_INVALID_RANGE;                                                    \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE3PTR_NO_ASSERT(                                      \
+		dev_id, val, min, max, ptr1, ptr2, ptr3)                                                  \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_dev_index_check(dev_id, val, min, max)) {                                   \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr1);                                                                 \
+			ZXIC_COMM_FREE(ptr2);                                                                 \
+			ZXIC_COMM_FREE(ptr3);                                                                 \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_dev_index_check(dev_id, val, min, max)) {                            \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr1);                                                                 \
+			ZXIC_COMM_FREE(ptr2);                                                                 \
+			ZXIC_COMM_FREE(ptr3);                                                                 \
+			return ZXIC_PAR_CHK_INVALID_RANGE;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_ID_NO_ASSERT(dev_id)                                                  \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_index_check(dev_id, 0,                                                      \
+								  zxic_comm_channel_max_get() - 1)) {                             \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, dev_id, 0,                                                \
+					zxic_comm_channel_max_get() - 1, __FUNCTION__);                               \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_index_check(dev_id, 0,                                               \
+										 zxic_comm_channel_max_get() - 1)) {                      \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, dev_id, 0,                                                \
+					zxic_comm_channel_max_get() - 1, __FUNCTION__);                               \
+			return ZXIC_PAR_CHK_INVALID_RANGE;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_ID_RETURN_NULL_NO_ASSERT(dev_id)                                      \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_index_check(dev_id, 0,                                                      \
+								  zxic_comm_channel_max_get() - 1)) {                             \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, dev_id, 0,                                                \
+					zxic_comm_channel_max_get() - 1, __FUNCTION__);                               \
+			return ZXIC_NULL;                                                                     \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_index_check(dev_id, 0,                                               \
+										 zxic_comm_channel_max_get() - 1)) {                      \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, dev_id, 0,                                                \
+					zxic_comm_channel_max_get() - 1, __FUNCTION__);                               \
+			return ZXIC_NULL;                                                                     \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, val0, val1)                   \
+	do {                                                                                       \
+		if ((val0) < (val1)) {                                                                 \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                         \
+					dev_id,                                                                    \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                 \
+		}                                                                                      \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT_UNLOCK(dev_id, val0,                     \
+																val1, mutex)                      \
+	do {                                                                                          \
+		if ((val0) < (val1)) {                                                                    \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n",    \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                                \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, val0, val1)                   \
+	do {                                                                                       \
+		if ((ZXIC_UINT32_MAX - (val0)) < (val1)) {                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                         \
+					dev_id,                                                                    \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                 \
+		}                                                                                      \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT_UNLOCK(dev_id, val0,                     \
+																val1, mutex)                      \
+	do {                                                                                          \
+		if ((ZXIC_UINT32_MAX - (val0)) < (val1)) {                                                \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n",    \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                                \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64_NO_ASSERT(dev_id, val0,                                \
+															val1)                                        \
+	do {                                                                                                 \
+		if ((ZXIC_ULONG_MAX - (val0)) < (val1)) {                                                        \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                                   \
+					dev_id,                                                                              \
+					"\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                                       \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                           \
+		}                                                                                                \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, val0, val1)                   \
+	do {                                                                                       \
+		if (((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1))) {                           \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                         \
+					dev_id,                                                                    \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                 \
+		}                                                                                      \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT_UNLOCK(dev_id, val0,                     \
+																val1, mutex)                      \
+	do {                                                                                          \
+		if (((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1))) {                              \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n",    \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                                \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                                             \
+				ZXIC_COMM_TRACE_ERROR(                                                            \
+						"File: [%s],Function:[%s],Line:%u mutex unlock failed!-->Return ERROR\n", \
+						__FILE__, __FUNCTION__, __LINE__);                                        \
+			}                                                                                     \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                    \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_64_NO_ASSERT(dev_id, val0,                      \
+															val1)                              \
+	do {                                                                                       \
+		if (((val0) > 0) && ((ZXIC_ULONG_MAX / (val0)) < (val1))) {                            \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                         \
+					dev_id,                                                                    \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                                 \
+		}                                                                                      \
+	} while (0)
+
+#endif
+#if ZXIC_REAL("return no code")
+#define ZXIC_COMM_CHECK_RC_RETURN_NONE(rc, becall)                            \
+	do {                                                                      \
+		if (ZXIC_OK != rc) {                                                  \
+			ZXIC_COMM_TRACE_ERROR(                                            \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);            \
+			ZXIC_COMM_ASSERT(0);                                              \
+			return;                                                           \
+		}                                                                     \
+	} while (0)
+
+/* 不带返回值,用于VOID类型函数 */
+#define ZXIC_COMM_CHECK_POINT_RETURN_NONE(point)                          \
+	do {                                                                  \
+		if (ZXIC_NULL == (point)) {                                       \
+			ZXIC_COMM_TRACE_ERROR(                                        \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			ZXIC_COMM_ASSERT(0);                                          \
+			return;                                                       \
+		}                                                                 \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_RETURN_NONE(val0, val1)                             \
+	do {                                                                                       \
+		if ((ZXIC_UINT32_MAX - (val0)) < (val1)) {                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                               \
+			return;                                                                            \
+		}                                                                                      \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_RETURN_NONE(val0, val1)                             \
+	do {                                                                                       \
+		if ((val0) < (val1)) {                                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                               \
+			return;                                                                            \
+		}                                                                                      \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_RETURN_NONE(val0, val1)                             \
+	do {                                                                                       \
+		if (((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1))) {                           \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                               \
+			return;                                                                            \
+		}                                                                                      \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_UPPER_RETURN_NONE(val, max)                                \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+			ZXIC_COMM_ASSERT(0);                                                         \
+			return;                                                                      \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_LOWER_RETURN_NONE(val, min)                                \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+			ZXIC_COMM_ASSERT(0);                                                         \
+			return;                                                                      \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_BOTH_RETURN_NONE(val, min, max)                                     \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return;                                                                               \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_UPPER_MEMORY_FREE_RETURN_NONE(val, max, ptr)               \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+			ZXIC_COMM_FREE(ptr);                                                         \
+			ZXIC_COMM_ASSERT(0);                                                         \
+			return;                                                                      \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_LOWER_MEMORY_FREE_RETURN_NONE(val, min, ptr)               \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+			ZXIC_COMM_FREE(ptr);                                                         \
+			ZXIC_COMM_ASSERT(0);                                                         \
+			return;                                                                      \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_BOTH_MEMORY_FREE_RETURN_NONE(val, min, max, ptr)                    \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr);                                                                  \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return;                                                                               \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_RC_RETURN_NONE(dev_id, rc, becall)                \
+	do {                                                                      \
+		if (ZXIC_OK != rc) {                                                  \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                        \
+					dev_id,                                                   \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);            \
+			ZXIC_COMM_ASSERT(0);                                              \
+			return;                                                           \
+		}                                                                     \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_POINT_RETURN_NONE(dev_id, point)              \
+	do {                                                                  \
+		if (NULL == (point)) {                                            \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                    \
+					dev_id,                                               \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			ZXIC_COMM_ASSERT(0);                                          \
+			return;                                                       \
+		}                                                                 \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_RETURN_NONE(dev_id, val, max)                    \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+			ZXIC_COMM_ASSERT(0);                                                         \
+			return;                                                                      \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_RETURN_NONE(dev_id, val, min)                    \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+			ZXIC_COMM_ASSERT(0);                                                         \
+			return;                                                                      \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_RETURN_NONE(dev_id, val, min, max)                         \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return;                                                                               \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_MEMORY_FREE_RETURN_NONE(dev_id, val,             \
+																max, ptr)                \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+			ZXIC_COMM_FREE(ptr);                                                         \
+			ZXIC_COMM_ASSERT(0);                                                         \
+			return;                                                                      \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_MEMORY_FREE_RETURN_NONE(dev_id, val,             \
+																min, ptr)                \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+			ZXIC_COMM_FREE(ptr);                                                         \
+			ZXIC_COMM_ASSERT(0);                                                         \
+			return;                                                                      \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_MEMORY_FREE_RETURN_NONE(dev_id, val,                       \
+															   min, max, ptr)                     \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr);                                                                  \
+			ZXIC_COMM_ASSERT(0);                                                                  \
+			return;                                                                               \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_RETURN_NONE(dev_id, val0, val1)                 \
+	do {                                                                                       \
+		if ((ZXIC_UINT32_MAX - (val0)) < (val1)) {                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                         \
+					dev_id,                                                                    \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                               \
+			return;                                                                            \
+		}                                                                                      \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64_RETURN_NONE(dev_id, val0,                              \
+															  val1)                                      \
+	do {                                                                                                 \
+		if ((ZXIC_ULONG_MAX - (val0)) < (val1)) {                                                        \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                                   \
+					dev_id,                                                                              \
+					"\n %s:%d[Error:VALUE[val0=0x%016llx] INVALID] [val1=0x%016llx] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                                       \
+			ZXIC_COMM_ASSERT(0);                                                                         \
+			return;                                                                                      \
+		}                                                                                                \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_RETURN_NONE(dev_id, val0, val1)                 \
+	do {                                                                                       \
+		if ((val0) < (val1)) {                                                                 \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                         \
+					dev_id,                                                                    \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                               \
+			return;                                                                            \
+		}                                                                                      \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_RETURN_NONE(dev_id, val0, val1)                 \
+	do {                                                                                       \
+		if (((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1))) {                           \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                         \
+					dev_id,                                                                    \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                               \
+			return;                                                                            \
+		}                                                                                      \
+	} while (0)
+#endif
+
+#if ZXIC_REAL("return no code & no assert")
+#define ZXIC_COMM_CHECK_RC_RETURN_NONE_NO_ASSERT(rc, becall)                  \
+	do {                                                                      \
+		if (ZXIC_OK != rc) {                                                  \
+			ZXIC_COMM_TRACE_ERROR(                                            \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);            \
+			return;                                                           \
+		}                                                                     \
+	} while (0)
+
+/* 不带返回值,用于VOID类型函数 */
+#define ZXIC_COMM_CHECK_POINT_RETURN_NONE_NO_ASSERT(point)                \
+	do {                                                                  \
+		if (ZXIC_NULL == (point)) {                                       \
+			ZXIC_COMM_TRACE_ERROR(                                        \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			return;                                                       \
+		}                                                                 \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_RETURN_NONE_NO_ASSERT(val0, val1)                   \
+	do {                                                                                       \
+		if ((ZXIC_UINT32_MAX - (val0)) < (val1)) {                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			return;                                                                            \
+		}                                                                                      \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_RETURN_NONE_NO_ASSERT(val0, val1)                   \
+	do {                                                                                       \
+		if ((val0) < (val1)) {                                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			return;                                                                            \
+		}                                                                                      \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_RETURN_NONE_NO_ASSERT(val0, val1)                   \
+	do {                                                                                       \
+		if (((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1))) {                           \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			return;                                                                            \
+		}                                                                                      \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_UPPER_RETURN_NONE_NO_ASSERT(val, max)                      \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+			return;                                                                      \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_LOWER_RETURN_NONE_NO_ASSERT(val, min)                      \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+			return;                                                                      \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_BOTH_RETURN_NONE_NO_ASSERT(val, min, max)                           \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			return;                                                                               \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_UPPER_MEMORY_FREE_RETURN_NONE_NO_ASSERT(                   \
+		val, max, ptr)                                                                   \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+			ZXIC_COMM_FREE(ptr);                                                         \
+			return;                                                                      \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_LOWER_MEMORY_FREE_RETURN_NONE_NO_ASSERT(                   \
+		val, min, ptr)                                                                   \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+			ZXIC_COMM_FREE(ptr);                                                         \
+			return;                                                                      \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_BOTH_MEMORY_FREE_RETURN_NONE_NO_ASSERT(val, min,                    \
+																	 max, ptr)                    \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr);                                                                  \
+			return;                                                                               \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_RC_RETURN_NONE_NO_ASSERT(dev_id, rc, becall)      \
+	do {                                                                      \
+		if (ZXIC_OK != rc) {                                                  \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                        \
+					dev_id,                                                   \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);            \
+			return;                                                           \
+		}                                                                     \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_POINT_RETURN_NONE_NO_ASSERT(dev_id, point)    \
+	do {                                                                  \
+		if (NULL == (point)) {                                            \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                    \
+					dev_id,                                               \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			return;                                                       \
+		}                                                                 \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_RETURN_NONE_NO_ASSERT(dev_id, val,               \
+															  max)                       \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+			return;                                                                      \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_RETURN_NONE_NO_ASSERT(dev_id, val,               \
+															  min)                       \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+			return;                                                                      \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_RETURN_NONE_NO_ASSERT(dev_id, val, min,                    \
+															 max)                                 \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			return;                                                                               \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_MEMORY_FREE_RETURN_NONE_NO_ASSERT(               \
+		dev_id, val, max, ptr)                                                           \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+			ZXIC_COMM_FREE(ptr);                                                         \
+			return;                                                                      \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_MEMORY_FREE_RETURN_NONE_NO_ASSERT(               \
+		dev_id, val, min, ptr)                                                           \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+			ZXIC_COMM_FREE(ptr);                                                         \
+			return;                                                                      \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_MEMORY_FREE_RETURN_NONE_NO_ASSERT(                         \
+		dev_id, val, min, max, ptr)                                                               \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+			ZXIC_COMM_FREE(ptr);                                                                  \
+			return;                                                                               \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_RETURN_NONE_NO_ASSERT(                          \
+		dev_id, val0, val1)                                                                    \
+	do {                                                                                       \
+		if ((ZXIC_UINT32_MAX - (val0)) < (val1)) {                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                         \
+					dev_id,                                                                    \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			return;                                                                            \
+		}                                                                                      \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_RETURN_NONE_NO_ASSERT(                          \
+		dev_id, val0, val1)                                                                    \
+	do {                                                                                       \
+		if ((val0) < (val1)) {                                                                 \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                         \
+					dev_id,                                                                    \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			return;                                                                            \
+		}                                                                                      \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_RETURN_NONE_NO_ASSERT(                          \
+		dev_id, val0, val1)                                                                    \
+	do {                                                                                       \
+		if (((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1))) {                           \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                         \
+					dev_id,                                                                    \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			return;                                                                            \
+		}                                                                                      \
+	} while (0)
+#endif
+
+#if ZXIC_REAL("no return")
+#define ZXIC_COMM_CHECK_RC_NONE(rc, becall)                                   \
+	do {                                                                      \
+		if (ZXIC_OK != rc) {                                                  \
+			ZXIC_COMM_TRACE_ERROR(                                            \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);            \
+			ZXIC_COMM_ASSERT(0);                                              \
+		}                                                                     \
+	} while (0)
+
+/* 不带返回值,用于VOID类型函数 */
+#define ZXIC_COMM_CHECK_POINT_NONE(point)                                 \
+	do {                                                                  \
+		if (ZXIC_NULL == (point)) {                                       \
+			ZXIC_COMM_TRACE_ERROR(                                        \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			ZXIC_COMM_ASSERT(0);                                          \
+		}                                                                 \
+	} while (0)
+
+/* 不带返回值,用于VOID类型函数 */
+#define ZXIC_COMM_CHECK_INDEX_NONE(val, min, max)                                                 \
+	do {                                                                                          \
+		if (ZXIC_OK != zxic_comm_index_check(val, min, max))                                      \
+			;                                                                                     \
+		{                                                                                         \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_UPPER_NONE(val, max)                                       \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NONE(val0, val1)                                    \
+	do {                                                                                       \
+		if ((ZXIC_UINT32_MAX - (val0)) < (val1)) {                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                               \
+		}                                                                                      \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NONE(val0, val1)                                    \
+	do {                                                                                       \
+		if ((val0) < (val1)) {                                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                               \
+		}                                                                                      \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NONE(val0, val1)                                    \
+	do {                                                                                       \
+		if (((val0) > 0) && ((ZXIC_UINT32_MAX / (val0)) < (val1))) {                           \
+			ZXIC_COMM_TRACE_ERROR(                                                             \
+					"\n %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val0, val1, __FUNCTION__);                             \
+			ZXIC_COMM_ASSERT(0);                                                               \
+		}                                                                                      \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_LOWER_NONE(val, min)                                       \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_BOTH_NONE(val, min, max)                                            \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_ERROR(                                                                \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+		}                                                                                         \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_RC_NONE(dev_id, rc, becall)                       \
+	do {                                                                      \
+		if (ZXIC_OK != rc) {                                                  \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                        \
+					dev_id,                                                   \
+					"\n ZXIC  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);            \
+			ZXIC_COMM_ASSERT(0);                                              \
+		}                                                                     \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_POINT_NONE(dev_id, point)                     \
+	do {                                                                  \
+		if (NULL == (point)) {                                            \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                    \
+					dev_id,                                               \
+					"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, __FUNCTION__);                    \
+			ZXIC_COMM_ASSERT(0);                                          \
+		}                                                                 \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_DEV_INDEX_NONE(dev_id, val, min, max)                                     \
+	do {                                                                                          \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                                                         \
+			zxic_comm_dev_index_check(dev_id, val, min, max)) {                                   \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                                                  \
+				   zxic_comm_dev_index_check(dev_id, val, min, max)) {                            \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_UPPER_NONE(dev_id, val, max)                           \
+	do {                                                                                 \
+		if ((val) > (max)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, max, __FUNCTION__);                         \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_LOWER_NONE(dev_id, val, min)                           \
+	do {                                                                                 \
+		if ((val) < (min)) {                                                             \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                   \
+					dev_id,                                                              \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, __FUNCTION__);                         \
+		}                                                                                \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_INDEX_BOTH_NONE(dev_id, val, min, max)                                \
+	do {                                                                                          \
+		if (((val) < (min)) || ((val) > (max))) {                                                 \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                            \
+					dev_id,                                                                       \
+					"\n %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", \
+					__FILE__, __LINE__, val, min, max, __FUNCTION__);                             \
+		}                                                                                         \
+	} while (0)
+#define ZXIC_COMM_CHECK_DEV_RC_INT(dev_id, check_rc, rc, becall)                       \
+	do {                                                                               \
+		if (check_rc < 0) {                                                            \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                                 \
+					dev_id,                                                            \
+					"\n ICM  %s:%d [ErrorCode:0x%x] [rc:0x%x] !-- %s Call %s Fail!\n", \
+					__FILE__, __LINE__, check_rc, rc, __FUNCTION__, becall);           \
+			ZXIC_COMM_ASSERT(0);                                                       \
+			return rc;                                                                 \
+		}                                                                              \
+	} while (0)
+
+#endif
+#if ZXIC_REAL("no print")
+#define ZXIC_COMM_CHECK_RC_NO_PRINT(rc, error_code) \
+	do {                                            \
+		if (ZXIC_OK != rc) {                        \
+			ZXIC_COMM_ASSERT(0);                    \
+			return error_code;                      \
+		}                                           \
+	} while (0)
+#define ZXIC_COMM_CHECK_RC_UNLOCK_NO_PRINT(rc, p_mutex, error_code) \
+	do {                                                            \
+		if (ZXIC_OK != rc) {                                        \
+			(ZXIC_VOID) zxic_comm_mutex_unlock(p_mutex);            \
+			ZXIC_COMM_ASSERT(0);                                    \
+			return error_code;                                      \
+		}                                                           \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_POINT_NO_PRINT(point) \
+	do {                                      \
+		if (ZXIC_NULL == (point)) {           \
+			ZXIC_COMM_ASSERT(0);              \
+			return ZXIC_PAR_CHK_POINT_NULL;   \
+		}                                     \
+	} while (0)
+#define ZXIC_COMM_CHECK_POINT_NO_PRINT_UNLOCK(point, p_mutex) \
+	do {                                                      \
+		if (ZXIC_NULL == (point)) {                           \
+			(ZXIC_VOID) zxic_comm_mutex_unlock(p_mutex);      \
+			ZXIC_COMM_ASSERT(0);                              \
+			return ZXIC_PAR_CHK_POINT_NULL;                   \
+		}                                                     \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_RC_POINT_NO_PRINT(point, rc) \
+	do {                                             \
+		if (ZXIC_NULL == (point)) {                  \
+			ZXIC_COMM_ASSERT(0);                     \
+			return rc;                               \
+		}                                            \
+	} while (0)
+
+#define ZXIC_COMM_CHECK_INDEX_NO_PRINT_UNLOCK(val, min, max, p_mutex) \
+	do {                                                              \
+		if (ZXIC_PAR_CHK_INVALID_INDEX ==                             \
+			zxic_comm_index_check(val, min, max)) {                   \
+			(ZXIC_VOID) zxic_comm_mutex_unlock(p_mutex);              \
+			ZXIC_COMM_ASSERT(0);                                      \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                        \
+		} else if (ZXIC_PAR_CHK_INVALID_RANGE ==                      \
+				   zxic_comm_index_check(val, min, max)) {            \
+			(ZXIC_VOID) zxic_comm_mutex_unlock(p_mutex);              \
+			ZXIC_COMM_ASSERT(0);                                      \
+			return ZXIC_PAR_CHK_INVALID_RANGE;                        \
+		}                                                             \
+	} while (0)
+#define ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_PRINT_UNLOCK(val0, val1, mutex) \
+	do {                                                                      \
+		if ((val0) < (val1)) {                                                \
+			if (0 != zxic_comm_mutex_unlock(mutex)) {                         \
+				ZXIC_COMM_ASSERT(0);                                          \
+				return ZXIC_PAR_CHK_INVALID_PARA;                             \
+			}                                                                 \
+			ZXIC_COMM_ASSERT(0);                                              \
+			return ZXIC_PAR_CHK_INVALID_INDEX;                                \
+		}                                                                     \
+	} while (0)
+
+#endif
+#endif /* ZXIC_REAL("参数检查") */
+
+//#ifdef ZXIC_FOR_LLT
+#if ZXIC_REAL("UT_TEST")
+#define ZXIC_CHECK_DEV_UT_RC(dev_id, rc, val, becall)                      \
+	do {                                                                   \
+		if (val != rc) {                                                   \
+			ZXIC_COMM_PRINT(                                               \
+					"\n ZXICP %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);         \
+			zxic_comm_ut_detail_trace_dev_error(                           \
+					dev_id,                                                \
+					"\n ZXICP %s:%d [ErrorCode:0x%x], %s Call %s Fail!\n", \
+					__FILE__, __LINE__, rc, __FUNCTION__, becall);         \
+			return ZXIC_E_LLT_CHECK;                                       \
+		}                                                                  \
+	} while (0)
+#endif
+
+#if ZXIC_REAL("字节序")
+/* DWORD变量字节序转换 */
+#define ZXIC_COMM_CONVERT32(dw_data)                    \
+	(((dw_data)&0xff) << 24 | ((dw_data)&0xff00) << 8 | \
+	 ((dw_data)&0xff0000) >> 8 | ((dw_data)&0xff000000) >> 24)
+/* WORD变量字节序转换 */
+#define ZXIC_COMM_CONVERT16(w_data) \
+	(((w_data)&0xff) << 8 | ((w_data)&0xff00) >> 8)
+
+/* WORD变量字节序转换 */
+#define ZXIC_COMM_CONVERT32_16b(w_data) \
+	(((w_data)&0xffff) << 16 | ((w_data)&0xffff0000) >> 16)
+
+ZXIC_VOID zxic_comm_swap_en_set(ZXIC_UINT32 enable);
+ZXIC_RTN32 zxic_comm_swap_en_get(ZXIC_VOID);
+ZXIC_RTN32 zxic_comm_is_big_endian(ZXIC_VOID);
+ZXIC_RTN32 zxic_comm_endian_prt(ZXIC_VOID);
+ZXIC_VOID zxic_comm_swap(ZXIC_UINT8 *p_uc_data, ZXIC_UINT32 dw_byte_len);
+ZXIC_VOID zxic_comm_swap_16b(ZXIC_UINT8 *p_uc_data, ZXIC_UINT32 dw_byte_len);
+ZXIC_UINT64 ZXIC_COMM_COUNTER64_BUILD(ZXIC_UINT32 hi, ZXIC_UINT32 lo);
+#endif
+
+#if ZXIC_REAL("内存")
+ZXIC_UINT32 zxic_comm_get_malloc_num(ZXIC_VOID);
+ZXIC_UINT32 zxic_comm_get_malloc_size(ZXIC_VOID);
+ZXIC_VOID zxic_clr_malloc_num(ZXIC_VOID);
+
+#define ZXIC_COMM_FREE(p_data) \
+	do {                       \
+		ic_comm_free_record(); \
+		kfree(p_data);         \
+		p_data = ZXIC_NULL;    \
+	} while (0)
+
+#define ZXIC_COMM_MALLOC(size) ic_comm_malloc_memory(size)
+
+#define ZXIC_COMM_ALLOC_MEMORY(ptr, size) \
+	do {                                  \
+		(ptr) = ZXIC_COMM_MALLOC(size);   \
+		ZXIC_COMM_CHECK_POINT(ptr);       \
+		ZXIC_COMM_MEMSET((ptr), 0, size); \
+	} while (0)
+#define ZXIC_COMM_ALLOC_MEMORY_DEV(dev_id, ptr, size) \
+	do {                                              \
+		(ptr) = ZXIC_COMM_MALLOC(size);               \
+		ZXIC_COMM_CHECK_DEV_POINT(dev_id, ptr);       \
+		ZXIC_COMM_MEMSET((ptr), 0, size);             \
+	} while (0)
+
+#endif
+
+#if ZXIC_REAL("延时")
+// ZXIC_VOID zxic_comm_sleep(ZXIC_UINT32 milliseconds);
+ZXIC_VOID zxic_comm_msleep(ZXIC_UINT32 millisecond);
+ZXIC_VOID zxic_comm_delay(ZXIC_UINT32 milliseconds);
+ZXIC_DOUBLE zxic_comm_get_ticks_s(ZXIC_VOID);
+ZXIC_DOUBLE zxic_comm_get_ticks_ms(ZXIC_VOID);
+ZXIC_DOUBLE zxic_get_ticks_uses(ZXIC_VOID);
+#endif
+
+#if ZXIC_REAL("bit操作")
+
+/* ZXIC_UINT32 写某几bit的值 */
+#define ZXIC_COMM_MASK_BIT(intType, _bitNum_) ((intType)(0x1U << (_bitNum_)))
+
+#define ZXIC_COMM_GET_BIT_MASK(_intType_, _bitQnt_)                           \
+	((_intType_)(((_bitQnt_) < 32) ? ((_intType_)ZXIC_COMM_MASK_BIT(          \
+											  _intType_, ((_bitQnt_)&0x1F)) - \
+									  1) :                                    \
+									   ((_intType_)(0xffffffff))))
+
+#define ZXIC_COMM_UINT32_WRITE_BITS(_uiDst_, _uiSrc_, _uiStartPos_, _uiLen_)  \
+	do {                                                                      \
+		(_uiDst_) =                                                           \
+				((_uiDst_) & ~(ZXIC_COMM_GET_BIT_MASK(ZXIC_UINT32, (_uiLen_)) \
+							   << (_uiStartPos_))) |                          \
+				(((_uiSrc_)&ZXIC_COMM_GET_BIT_MASK(ZXIC_UINT32, (_uiLen_)))   \
+				 << (_uiStartPos_));                                          \
+	} while (0)
+
+#define ZXIC_COMM_UINT32_WRITE_BITS_ZERO(_uiDst_, _uiStartPos_, _uiLen_)      \
+	do {                                                                      \
+		(_uiDst_) =                                                           \
+				((_uiDst_) & ~(ZXIC_COMM_GET_BIT_MASK(ZXIC_UINT32, (_uiLen_)) \
+							   << (_uiStartPos_)));                           \
+	} while (0)
+
+#define ZXIC_COMM_UINT32_GET_BITS(_uiDst_, _uiSrc_, _uiStartPos_, _uiLen_) \
+	do {                                                                   \
+		(_uiDst_) = (((_uiSrc_) >> (_uiStartPos_)) &                       \
+					 (ZXIC_COMM_GET_BIT_MASK(ZXIC_UINT32, (_uiLen_))));    \
+	} while (0)
+
+#define ZXIC_COMM_UINT32_GET_RETURN_BITS(_uiSrc_, _uiStartPos_, _uiLen_) \
+	(((_uiSrc_) >> (_uiStartPos_)) &                                     \
+	 (ZXIC_COMM_GET_BIT_MASK(ZXIC_UINT32, (_uiLen_))))
+
+/* ZXIC_UINT64 写某几bit的值 */
+#define ZXIC_COMM_MASK_BIT_64(intType, _bitNum_) \
+	((intType)(0x1ULL << (_bitNum_)))
+
+#define ZXIC_COMM_GET_64_BIT_MASK(_intType_, _bitQnt_)                        \
+	((_intType_)(((_bitQnt_) < 64) ? ((_intType_)ZXIC_COMM_MASK_BIT_64(       \
+											  _intType_, ((_bitQnt_)&0x3F)) - \
+									  1) :                                    \
+									   ((_intType_)(0xFFFFFFFFFFFFFFFFULL))))
+
+#define ZXIC_COMM_UINT64_WRITE_BITS(_uiDst_, _uiSrc_, _uiStartPos_, _uiLen_)   \
+	do {                                                                       \
+		(_uiDst_) =                                                            \
+				((_uiDst_) &                                                   \
+				 ~(ZXIC_COMM_GET_64_BIT_MASK(ZXIC_UINT64, (_uiLen_))           \
+				   << (_uiStartPos_))) |                                       \
+				(((_uiSrc_)&ZXIC_COMM_GET_64_BIT_MASK(ZXIC_UINT64, (_uiLen_))) \
+				 << (_uiStartPos_));                                           \
+	} while (0)
+
+/* Base type for declarations */
+#define ZXIC_COMM_BITDCL ZXIC_UINT32
+#define ZXIC_COMM_BITWID (32)
+
+/* (internal) Number of ZXICP_BITDCLs needed to contain _max bits */
+#define NPE_BITDCLSIZE(_max) \
+	(((_max) + ZXIC_COMM_BITWID - 1) / ZXIC_COMM_BITWID)
+
+/* Size for giving to malloc and memset to handle _max bits */
+#define ZXIC_COMM_BITALLOCSIZE(_max) \
+	(NPE_BITDCLSIZE(_max) * sizeof(ZXIC_COMM_BITDCL))
+
+/* (internal) Generic operation macro on bit array _a, with bit _b */
+#define NPE_BITOP(_a, _b, _op) \
+	(((_a)[(_b) / ZXIC_COMM_BITWID]) _op(1U << ((_b) % ZXIC_COMM_BITWID)))
+
+/* Specific operations */
+#define ZXIC_COMM_BITGET(_a, _b) NPE_BITOP(_a, _b, &)
+#define ZXIC_COMM_BITSET(_a, _b) NPE_BITOP(_a, _b, |=)
+#define ZXIC_COMM_BITCLR(_a, _b) NPE_BITOP(_a, _b, &= ~)
+
+ZXIC_RTN32 zxic_comm_bit_count(ZXIC_UINT32 data);
+ZXIC_RTN32 zxic_comm_read_bits(ZXIC_UINT8 *p_base, ZXIC_UINT32 base_size_bit,
+							   ZXIC_UINT32 *p_data, ZXIC_UINT32 start_bit,
+							   ZXIC_UINT32 end_bit);
+ZXIC_RTN32 zxic_comm_write_bits(ZXIC_UINT8 *p_base, ZXIC_UINT32 base_size_bit,
+								ZXIC_UINT32 data, ZXIC_UINT32 start_bit,
+								ZXIC_UINT32 end_bit);
+ZXIC_RTN32 zxic_comm_write_bits_ex(ZXIC_UINT8 *p_base,
+								   ZXIC_UINT32 base_size_bit, ZXIC_UINT32 data,
+								   ZXIC_UINT32 msb_start_pos, ZXIC_UINT32 len);
+ZXIC_RTN32 zxic_comm_read_bits_ex(ZXIC_UINT8 *p_base, ZXIC_UINT32 base_size_bit,
+								  ZXIC_UINT32 *p_data,
+								  ZXIC_UINT32 msb_start_pos, ZXIC_UINT32 len);
+ZXIC_RTN32 zxic_comm_write_bits_op(ZXIC_UINT8 *p_src_dat,
+								   ZXIC_UINT32 src_size_bit,
+								   ZXIC_UINT32 input_data,
+								   ZXIC_UINT32 start_bit, ZXIC_UINT32 end_bit);
+ZXIC_RTN32 zxic_comm_read_bits_op(ZXIC_UINT8 *p_src_dat,
+								  ZXIC_UINT32 src_size_bit,
+								  ZXIC_UINT32 *p_out_data,
+								  ZXIC_UINT32 start_bit, ZXIC_UINT32 end_bit);
+#endif
+
+#if ZXIC_REAL("算数运算")
+ZXIC_UINT64 zxic_comm_get_gcd(ZXIC_UINT64 a, ZXIC_UINT64 b);
+ZXIC_RTN32 zxic_comm_multi_big_integer(ZXIC_CONST ZXIC_CHAR *num1,
+									   ZXIC_CONST ZXIC_CHAR *num2,
+									   ZXIC_CHAR *str_num);
+ZXIC_RTN32 zxic_comm_div_big_integer(ZXIC_CONST ZXIC_CHAR *num1,
+									 ZXIC_CONST ZXIC_CHAR *num2,
+									 ZXIC_UINT32 *quo_val);
+ZXIC_SINT32 zxic_comm_sub_stract(ZXIC_SINT32 *p1, ZXIC_SINT32 *p2,
+								 ZXIC_SINT32 len1, ZXIC_SINT32 len2);
+ZXIC_SINT32 zxic_comm_cmpm_calc(ZXIC_UINT64 cm_cal, ZXIC_UINT64 pm_cal,
+								ZXIC_UINT32 *cm, ZXIC_UINT32 *pm);
+ZXIC_VOID zxic_comm_pm_cm_cal(ZXIC_UINT64 cm_y, ZXIC_UINT64 pm_y,
+							  ZXIC_UINT32 *cm, ZXIC_UINT32 *pm);
+#endif
+
+#if ZXIC_REAL("字符串")
+ZXIC_RTN32 zxic_comm_strcasecmp(ZXIC_CHAR *str1, ZXIC_CHAR *str2);
+ZXIC_UINT8 zxic_comm_char_to_hex(ZXIC_UINT8 c);
+ZXIC_DWORD zxic_comm_ipaddr_to_dword(ZXIC_CONST ZXIC_CHAR *p_addr);
+ZXIC_RTN32 zxic_comm_char_to_number(ZXIC_CHAR a, ZXIC_CHAR b,
+									ZXIC_UINT8 *number);
+ZXIC_CHAR *zxic_comm_strlower(ZXIC_CHAR *str);
+ZXIC_RTN32 ic_comm_check_str_size(ZXIC_CHAR *str);
+ZXIC_SIZE_T ic_comm_getAbsValue(ZXIC_UINT8 *dest, ZXIC_CONST ZXIC_UINT8 *src);
+ZXIC_VOID ic_comm_memset_s(void *dest, ZXIC_SIZE_T dmax, ZXIC_UINT8 c,
+						   ZXIC_SIZE_T n);
+ZXIC_SINT32 ic_comm_memcmp(void *str1, const void *str2, ZXIC_SIZE_T n);
+ZXIC_SINT32 ic_comm_strncmp(const ZXIC_CHAR *str1, const ZXIC_CHAR *str2,
+							ZXIC_SIZE_T n);
+
+#endif
+
+#if ZXIC_REAL("dma内存分配")
+#define ZXIC_DMA_PHY_ADDR dma_addr_t
+ZXIC_RTN32 zxic_comm_dma_mem_malloc(ZXIC_ADDR_T * vir_addr,
+									ZXIC_ADDR_T * phy_addr,
+									ZXIC_UINT32 dma_size);
+ZXIC_RTN32 zxic_comm_dma_mem_free(ZXIC_ADDR_T vir_addr, ZXIC_ADDR_T phy_addr,
+								  ZXIC_UINT32 dma_size);
+#endif
+
+#if ZXIC_REAL("OTHER")
+#define MIN_VAL(x, y) ((x) <= (y) ? (x) : (y))
+#define MAX_VAL(x, y) ((x) <= (y) ? (y) : (x))
+#define ZXIC_COMM_DM_TO_X(d, m) ((d) & ~(m))
+#define ZXIC_COMM_DM_TO_Y(d, m) (~(d) & ~(m))
+#define ZXIC_COMM_XY_TO_MASK(x, y) (~(x) & ~(y))
+#define ZXIC_COMM_XY_TO_DATA(x, y) (x) /* valid only when mask is 0 */
+#define ZXIC_RD_CNT_MAX (50)
+
+/* 新增常用数据掩码 */
+#define ZXIC_COMM_WORD64_MASK (0xFFFFFFFFFFFFFFFFULL)
+#define ZXIC_COMM_WORD32_MASK (0xFFFFFFFFU)
+#define ZXIC_COMM_WORD16_MASK (0xFFFFU)
+#define ZXIC_COMM_BYTE_MASK (0xFFU)
+
+ZXIC_RTN32 ZXIC_COMM_GET_MASK_VALUE(ZXIC_UINT32 total, ZXIC_UINT32 masklen);
+ZXIC_UINT32 zxic_comm_random(ZXIC_VOID);
+ZXIC_VOID zxic_comm_channel_max_set(ZXIC_UINT32 dev_max);
+
+ZXIC_RTN32 zxic_comm_channel_max_get(ZXIC_VOID);
+
+ZXIC_VOID zxic_comm_dbgcnt64_select_print(const ZXIC_CHAR *name,
+										  ZXIC_UINT64 value,
+										  ZXIC_UINT32 prt_mode);
+
+ZXIC_VOID zxic_comm_dbgcnt64_select_par_print(const ZXIC_CHAR *name,
+											  ZXIC_UINT32 parm,
+											  ZXIC_UINT64 value,
+											  ZXIC_UINT32 prt_mode);
+
+ZXIC_VOID zxic_comm_dbgcnt32_select_print(const ZXIC_CHAR *name,
+										  ZXIC_UINT32 value,
+										  ZXIC_UINT32 prt_mode);
+
+ZXIC_VOID zxic_comm_dbgcnt32_select_par_print(const ZXIC_CHAR *name,
+											  ZXIC_UINT32 parm,
+											  ZXIC_UINT32 value,
+											  ZXIC_UINT32 prt_mode);
+
+#define ZXIC_COMM_CHECK_ADD_CNT(x, y) \
+	(((0xffffffff - (x)) < (y)) ? ((y) - (0xffffffff - (x)) - 1) : ((x) + (y)))
+#define ZXIC_COMM_CHECK_ADD_CNT_WORD64(x, y)          \
+	(((0xffffffffffffffff - (x)) < (y)) ?             \
+			   ((y) - (0xffffffffffffffff - (x)) - 1) : \
+			   ((x) + (y)))
+#endif
+
+#if ZXIC_REAL("UT_TEST")
+
+ZXIC_VOID zxic_comm_ut_detail_info_trace(const ZXIC_CHAR *format, ...);
+
+ZXIC_VOID zxic_comm_ut_result_info_trace(const ZXIC_CHAR *format, ...);
+
+ZXIC_VOID zxic_comm_ut_detail_trace_error(const ZXIC_CHAR *format, ...);
+
+ZXIC_VOID zxic_comm_ut_detail_trace_dev_error(ZXIC_UINT32 dev_id,
+											  const ZXIC_CHAR *format, ...);
+
+#endif
+
+#if ZXIC_REAL("头文件")
+#include "zxic_comm_double_link.h"
+#include "zxic_comm_doublelink_index.h"
+#include "zxic_comm_liststack.h"
+#include "zxic_comm_avl_tree.h"
+#include "zxic_comm_rb_tree.h"
+#include "zxic_comm_index_ctrl.h"
+#include "zxic_comm_index_reserve.h"
+#include "zxic_comm_index_fill.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end __ZXIC_COMMON_H__ */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_private.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_private.h
index 76a4e7ad4171b3acafc5be27de3b0c1506371875..514fc3a503d9a9f2e523eca1faccc09dd27bdfdd 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_private.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_private.h
@@ -1,117 +1,103 @@
-/**************************************************************
-* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司
-* 文件名称      :
-* 文件标识      :
-* 内容摘要      :   集合几个文件用到的定义，不对外部开放
-* 其它说明      :
-* 当前版本      :
-* 作    者      :
-* 完成日期      : 2020/07/20
-* DEPARTMENT: 有线开发四部-系统软件团队
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-#ifndef __ZXIC_PRIVATE_H__
-#define __ZXIC_PRIVATE_H__
-
-#if ZXIC_REAL("日志相关")
-#include <linux/mutex.h>
-#include <linux/semaphore.h>
-#include <linux/fs.h>
-#define ZXIC_TRACE_LOG_FILE_GZ_MAX_CNT  (50) /* 最大压缩后日志文件数 */
-
-typedef struct zxic_log_file_info
-{
-    char       fname[50];
-    struct file       *p_log_fp;
-    unsigned int     f_size;    /* 日志文件大小上限，以字节为单位 */
-}ZXIC_LOG_FILE_INFO;
-
-
-#endif /* ZXIC_REAL("日志相关") */
-
-#if ZXIC_REAL("打印相关")
- typedef enum
- {
-     ZXIC_TRACE_PRINT       = 0,
-     ZXIC_TRACE_ERROR_PRINT = 1,
-     ZXIC_TRACE_INFO_PRINT     ,
-     ZXIC_TRACE_DEBUG_PRINT    ,
-     ZXIC_TRACE_ALL_PRINT      ,
-     ZXIC_TRACE_INVALID_PRINT
- } ZXIC_TRACE_LEVEL;
-
- typedef enum zxic_log_file_type_e
- {
-     ZXIC_LOG_SDK       = 0,  /*SDK日常配置记录*/
-     ZXIC_LOG_INIT      = 1,  /*初始化日志记录*/
-     ZXIC_LOG_LIF       = 2,  /*LIF日志记录*/
-     ZXIC_LOG_SERDES    = 3,  /*SERDES日志记录*/
-     ZXIC_LOG_SE_ERAM   = 4,  /*SE ERAM日志记录*/
-     ZXIC_LOG_SE_HBM    = 5,  /*SE HBM日志记录*/ 
-     ZXIC_LOG_SE_OTHER  = 6,  /*SE other （se 部分模块）日志记录*/
-     ZXIC_LOG_REG       = 7,  /*寄存器和打桩信息日志记录，特殊使用*/
-     ZXIC_LOG_DEBUG     = 8,  /*打印，诊断计数打印等日志记录*/
-     ZXIC_LOG_DUMP      = 9,  /*捞数据日志记录，特殊使用*/
-     ZXIC_LOG_SE_LPM_SAMPLE_V4    = 10,  /*SE LPM_V4样本打印记录*/
-     ZXIC_LOG_SE_LPM_SAMPLE_V6    = 11,  /*SE LPM_V4样本打印记录*/
-     ZXIC_LOG_UT_DETAIL     = 12,  /* ut check 失败信息 */
-     ZXIC_LOG_UT_RESULT     = 13,  /* utcheck 统计信息 */
-     ZXIC_LOG_SE_HASH   = 14,  /*SE HASH日志记录*/
-     ZXIC_LOG_SE_ACL    = 15,  /*SE ACL日志记录*/
-     ZXIC_LOG_SLT       = 16,  /*SLT 日志记录*/
-     ZXIC_LOG_SDS_COMM  = 17,  /*SERDES COMM 库日志记录 */
-     ZXIC_LOG_THREAD    = 31,  /*多线程log打印,注意多线程占用了31b~26b*/
-     ZXIC_LOG_MAX,
- } ZXIC_LOG_FILE_TYPE_E;
-
-#define ZXIC_THREAD_ID_NUM_MAX      (2048)
-
-#define ZXIC_MALLOC_MAX_B_SIZE (0xC800000U) /* 200M */
-
-#endif /* ZXIC_REAL("打印相关") */
-
-#if ZXIC_REAL("互斥锁相关")
-typedef struct zxic_mutex_t
-{
-#ifdef ZXIC_OS_WIN
-    HANDLE          mutex;
-#else
-    struct mutex mutex;
-#endif
-}ZXIC_MUTEX_T;
-#endif
-
-#if ZXIC_REAL("信号量相关")
-typedef struct zxic_sem_t
-{
-    #ifdef ZXIC_OS_WIN
-    HANDLE          sem;
-    #else
-    struct semaphore sem;
-    #endif
-}ZXIC_SEM_T;
-#endif
-
-void *ic_comm_sdk_print_regist(void);
-unsigned int ic_comm_callback_print_get(void* pExcCall);
-unsigned int ic_comm_callback_err_log_get(void* pExcCall);
-void ic_comm_set_os_callback(ZXIC_OS_CALLBACK *p_os_cb);
-void ic_comm_malloc_record(unsigned int size);
-void ic_comm_free_record(void);
-/***********************************************************/
-/** 从path_name所指的目录中查找符合参数的执行文件，找到后便执行该文件，
-    然后将第二个参数argv传给该欲执行的文件,请参照execv用法,异常时候返回-1
-* @return
-* @remark  无
-* @see
-* @author  pj      @date  2020/03/30
-************************************************************/
-int zxic_system(const char *path_name, char *const argv[]);
-
-#endif /* end  __ZXIC_COMMON_TOP_H__ */
+/**************************************************************
+* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司
+* 文件名称      :
+* 文件标识      :
+* 内容摘要      :   集合几个文件用到的定义，不对外部开放
+* 其它说明      :
+* 当前版本      :
+* 作    者      :
+* 完成日期      : 2020/07/20
+* DEPARTMENT: 有线开发四部-系统软件团队
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#ifndef __ZXIC_PRIVATE_H__
+#define __ZXIC_PRIVATE_H__
+
+#if ZXIC_REAL("日志相关")
+#include <linux/mutex.h>
+#include <linux/semaphore.h>
+#include <linux/fs.h>
+#define ZXIC_TRACE_LOG_FILE_GZ_MAX_CNT (50) /* 最大压缩后日志文件数 */
+
+typedef struct zxic_log_file_info {
+	char fname[50];
+	struct file *p_log_fp;
+	unsigned int f_size; /* 日志文件大小上限，以字节为单位 */
+} ZXIC_LOG_FILE_INFO;
+
+#endif /* ZXIC_REAL("日志相关") */
+
+#if ZXIC_REAL("打印相关")
+typedef enum {
+	ZXIC_TRACE_PRINT = 0,
+	ZXIC_TRACE_ERROR_PRINT = 1,
+	ZXIC_TRACE_INFO_PRINT,
+	ZXIC_TRACE_DEBUG_PRINT,
+	ZXIC_TRACE_ALL_PRINT,
+	ZXIC_TRACE_INVALID_PRINT
+} ZXIC_TRACE_LEVEL;
+
+typedef enum zxic_log_file_type_e {
+	ZXIC_LOG_SDK = 0, /*SDK日常配置记录*/
+	ZXIC_LOG_INIT = 1, /*初始化日志记录*/
+	ZXIC_LOG_LIF = 2, /*LIF日志记录*/
+	ZXIC_LOG_SERDES = 3, /*SERDES日志记录*/
+	ZXIC_LOG_SE_ERAM = 4, /*SE ERAM日志记录*/
+	ZXIC_LOG_SE_HBM = 5, /*SE HBM日志记录*/
+	ZXIC_LOG_SE_OTHER = 6, /*SE other （se 部分模块）日志记录*/
+	ZXIC_LOG_REG = 7, /*寄存器和打桩信息日志记录，特殊使用*/
+	ZXIC_LOG_DEBUG = 8, /*打印，诊断计数打印等日志记录*/
+	ZXIC_LOG_DUMP = 9, /*捞数据日志记录，特殊使用*/
+	ZXIC_LOG_SE_LPM_SAMPLE_V4 = 10, /*SE LPM_V4样本打印记录*/
+	ZXIC_LOG_SE_LPM_SAMPLE_V6 = 11, /*SE LPM_V4样本打印记录*/
+	ZXIC_LOG_UT_DETAIL = 12, /* ut check 失败信息 */
+	ZXIC_LOG_UT_RESULT = 13, /* utcheck 统计信息 */
+	ZXIC_LOG_SE_HASH = 14, /*SE HASH日志记录*/
+	ZXIC_LOG_SE_ACL = 15, /*SE ACL日志记录*/
+	ZXIC_LOG_SLT = 16, /*SLT 日志记录*/
+	ZXIC_LOG_SDS_COMM = 17, /*SERDES COMM 库日志记录 */
+	ZXIC_LOG_THREAD = 31, /*多线程log打印,注意多线程占用了31b~26b*/
+	ZXIC_LOG_MAX,
+} ZXIC_LOG_FILE_TYPE_E;
+
+#define ZXIC_THREAD_ID_NUM_MAX (2048)
+
+#define ZXIC_MALLOC_MAX_B_SIZE (0xC800000U) /* 200M */
+
+#endif /* ZXIC_REAL("打印相关") */
+
+#if ZXIC_REAL("互斥锁相关")
+typedef struct zxic_mutex_t {
+	struct mutex mutex;
+} ZXIC_MUTEX_T;
+#endif
+
+#if ZXIC_REAL("信号量相关")
+typedef struct zxic_sem_t {
+	struct semaphore sem;
+} ZXIC_SEM_T;
+#endif
+
+void *ic_comm_sdk_print_regist(void);
+unsigned int ic_comm_callback_print_get(void *pExcCall);
+unsigned int ic_comm_callback_err_log_get(void *pExcCall);
+void ic_comm_set_os_callback(ZXIC_OS_CALLBACK *p_os_cb);
+void ic_comm_malloc_record(unsigned int size);
+void ic_comm_free_record(void);
+/***********************************************************/
+/** 从path_name所指的目录中查找符合参数的执行文件，找到后便执行该文件，
+    然后将第二个参数argv传给该欲执行的文件,请参照execv用法,异常时候返回-1
+* @return
+* @remark  无
+* @see
+* @author  pj      @date  2020/03/30
+************************************************************/
+int zxic_system(const char *path_name, char *const argv[]);
+
+#endif /* end  __ZXIC_COMMON_TOP_H__ */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_private_top.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_private_top.h
index 19515187a3407344ed990ec1ad50b494f5f79a2a..56a4426374dd032ce734513203f29febca87d065 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_private_top.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_private_top.h
@@ -1,194 +1,198 @@
-/**************************************************************
-* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司
-* 文件名称      : zxic_comm_top.h
-* 文件标识      :
-* 内容摘要      :提供少许 common.h 开头就要用到的宏
-* 其它说明      : 项目线不需要感知
-* 当前版本      :
-* 作    者      :
-* 完成日期      : 2020/07/20
-* DEPARTMENT: 有线开发四部-系统软件团队
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-#ifndef __ZXIC_PRIVATE_TOP_H__
-#define __ZXIC_PRIVATE_TOP_H__
-
-//#include <ctype.h>
-//#include <stdlib.h>
-//#include <stdio.h>
-#include <linux/stddef.h>
-#include <linux/string.h>
-//#include <errno.h>
-//#include <assert.h>
-#include <stdarg.h>
-//#include <math.h>
-#include <linux/stat.h>
-#include <linux/semaphore.h>
-
-#define ZXIC_REAL(x)        (1U)    /* 用于#if 对同一类的代码进行  分段    */
-#define ZXIC_NOREAL(x)      (0U)    /* 用于#if   对同一类的代码进行  分段    */
-
-#ifndef ZXIC_OS_WIN                 /* 操作系统类型导入,编译宏控制 */
-#define ZXIC_OS_LINUX               /* 默认为LINUX操作系统 */
-#endif
-
-#if ZXIC_REAL("内存")
-typedef void* (*ZXIC_OS_MEM_MALLOC)(unsigned int mem_size);
-typedef void  (*ZXIC_OS_MEM_FREE)(void *p_free);
-
-typedef struct _zxic_os_callback
-{
-    ZXIC_OS_MEM_MALLOC p_mem_malloc;
-    ZXIC_OS_MEM_FREE   p_mem_free;
-} ZXIC_OS_CALLBACK;
-#endif
-
-#if ZXIC_REAL("大小端")
-/*大小端序专用*/
-typedef union zxic_endian_u
-{
-    unsigned int     a;
-    unsigned char    b;
-} ZXIC_ENDIAN_U;
-#endif
-
-#if ZXIC_REAL("异常返回值宏定义")
-#define ZXIC_RC_BASE                            (0x1000U)
-
-/* bit_stream */
-#define ZXIC_BIT_STREAM_BASE                    (ZXIC_RC_BASE            | 0x100)
-#define ZXIC_BIT_STREAM_INDEX_ERR               (ZXIC_BIT_STREAM_BASE    | 0x001)
-#define ZXIC_BIT_STREAM_DATA_TOO_BIG            (ZXIC_BIT_STREAM_BASE    | 0x002)
- 
-/* parameter check */
-#define ZXIC_PARAMETER_CHK_BASE                 (ZXIC_RC_BASE            | 0x200)
-#define ZXIC_PAR_CHK_POINT_NULL                 (ZXIC_PARAMETER_CHK_BASE | 0x001)
-#define ZXIC_PAR_CHK_ARGIN_ZERO                 (ZXIC_PARAMETER_CHK_BASE | 0x002)
-#define ZXIC_PAR_CHK_ARGIN_OVERFLOW             (ZXIC_PARAMETER_CHK_BASE | 0x003)
-#define ZXIC_PAR_CHK_ARGIN_ERROR                (ZXIC_PARAMETER_CHK_BASE | 0x004)
-#define ZXIC_PAR_CHK_INVALID_INDEX              (ZXIC_PARAMETER_CHK_BASE | 0x005)
-#define ZXIC_PAR_CHK_INVALID_RANGE              (ZXIC_PARAMETER_CHK_BASE | 0x006)
-#define ZXIC_PAR_CHK_INVALID_DEV_ID             (ZXIC_PARAMETER_CHK_BASE | 0x007)
-#define ZXIC_PAR_CHK_INVALID_PARA               (ZXIC_PARAMETER_CHK_BASE | 0x008)
-
-/* mutex lock */
-#define ZXIC_MUTEX_LOCK_BASE                    (ZXIC_RC_BASE            | 0x300)
-#define ZXIC_MUTEX_LOCK_INIT_FAIL               (ZXIC_MUTEX_LOCK_BASE    | 0x001)
-#define ZXIC_MUTEX_LOCK_LOCK_FAIL               (ZXIC_MUTEX_LOCK_BASE    | 0x002)
-#define ZXIC_MUTEX_LOCK_ULOCK_FAIL              (ZXIC_MUTEX_LOCK_BASE    | 0X003)
-#define ZXIC_MUTEX_LOCK_DESTROY_FAIL            (ZXIC_MUTEX_LOCK_BASE    | 0X004)
-
-/* thread */
-#define ZXIC_THREAD_BASE                        (ZXIC_RC_BASE            | 0x400)
-#define ZXIC_THREAD_INFO_ADD_FAIL               (ZXIC_THREAD_BASE        | 0x001)
-#define ZXIC_THREAD_CREATE_FAIL                 (ZXIC_THREAD_BASE        | 0x002)
-
-/* socket */
-#define ZXIC_SOCKET_BASE                        (ZXIC_RC_BASE            | 0x400)
-#define ZXIC_SOKET_SERVICE_START_FAIL           (ZXIC_THREAD_BASE        | 0x001)
-#define ZXIC_SOKET_SERVICE_CLOSE_FAIL           (ZXIC_THREAD_BASE        | 0x002)
-#define ZXIC_SOKET_SET_PARA_FAIL                (ZXIC_THREAD_BASE        | 0x003)
-#define ZXIC_SOKET_CREATE_FAIL                  (ZXIC_THREAD_BASE        | 0x004)
-#define ZXIC_SOKET_BIND_LISTEN_FAIL             (ZXIC_THREAD_BASE        | 0x005)
-#define ZXIC_SOKET_CONNECT_FAIL                 (ZXIC_THREAD_BASE        | 0x006)
-#define ZXIC_SOKET_CLOSE_FAIL                   (ZXIC_THREAD_BASE        | 0x007)
-#define ZXIC_SOKET_GET_PARA_FAIL                (ZXIC_THREAD_BASE        | 0x008)
-
-
-/* double link */
-#define ZXIC_DOUBLE_LINK_BASE                   (ZXIC_RC_BASE            | 0x500)
-#define ZXIC_DOUBLE_LINK_ELEMENT_NUM_ERR        (ZXIC_DOUBLE_LINK_BASE   | 0x001)
-#define ZXIC_DOUBLE_LINK_MALLOC_FAIL            (ZXIC_DOUBLE_LINK_BASE   | 0x002)
-#define ZXIC_DOUBLE_LINK_POINT_NULL             (ZXIC_DOUBLE_LINK_BASE   | 0x003)
-#define ZXIC_DOUBLE_LINK_CHK_SUM_ERR            (ZXIC_DOUBLE_LINK_BASE   | 0x004)
-#define ZXIC_DOUBLE_LINK_NO_EXIST_FREENODE      (ZXIC_DOUBLE_LINK_BASE   | 0x005)
-#define ZXIC_DOUBLE_LINK_FREE_INDX_INVALID      (ZXIC_DOUBLE_LINK_BASE   | 0x006)
-#define ZXIC_DOUBLE_LINK_NO_EXIST_PRENODE       (ZXIC_DOUBLE_LINK_BASE   | 0x007)
-#define ZXIC_DOUBLE_LINK_INPUT_INDX_INVALID     (ZXIC_DOUBLE_LINK_BASE   | 0x008)
-#define ZXIC_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR   (ZXIC_DOUBLE_LINK_BASE   | 0x009)
-
-
-/* index ctrl */
-#define ZXIC_INDEX_CTRL_BASE                    (ZXIC_RC_BASE            | 0x600)
-#define ZXIC_INDEX_CTRL_TREE_FULL               (ZXIC_INDEX_CTRL_BASE    | 0x001)
-#define ZXIC_INDEX_CTRL_SAME_RECORD             (ZXIC_INDEX_CTRL_BASE    | 0x002)
-#define ZXIC_INDEX_CTRL_OPER_MODE_ERR           (ZXIC_INDEX_CTRL_BASE    | 0x003)
-
-/* index reverse */
-#define ZXIC_INDEX_RSV_BASE                      (ZXIC_RC_BASE           | 0x700)
-#define ZXIC_INDEX_RESERVE_GET_INDX_FAIL         (ZXIC_INDEX_RSV_BASE    | 0x001)
-#define ZXIC_INDEX_RESERVE_BORROW_HIG_FAIL       (ZXIC_INDEX_RSV_BASE    | 0x002)
-#define ZXIC_INDEX_RESERVE_BORROW_LOW_FAIL       (ZXIC_INDEX_RSV_BASE    | 0x003)
-#define ZXIC_INDEX_RESERVE_ALLOCI_INDX_FAIL      (ZXIC_INDEX_RSV_BASE    | 0x004)
-#define ZXIC_INDEX_RESERVE_FREE_INDX_FAIL        (ZXIC_INDEX_RSV_BASE    | 0x005)
-#define ZXIC_INDEX_RESERVE_RESET_INDX_FAIL       (ZXIC_INDEX_RSV_BASE    | 0x006)
-
-/* list stack */
-#define ZXIC_LIST_STACK_BASE                     (ZXIC_RC_BASE            | 0x800)
-#define ZXIC_LIST_STACK_ELEMENT_NUM_ERR          (ZXIC_LIST_STACK_BASE    | 0x001)
-#define ZXIC_LIST_STACK_POINT_NULL               (ZXIC_LIST_STACK_BASE    | 0x002)
-#define ZXIC_LIST_STACK_ALLOC_MEMORY_FAIL        (ZXIC_LIST_STACK_BASE    | 0x003)
-#define ZXIC_LIST_STACK_ISEMPTY_ERR              (ZXIC_LIST_STACK_BASE    | 0x004)
-#define ZXIC_LIST_STACK_FREE_INDEX_INVALID       (ZXIC_LIST_STACK_BASE    | 0x005)
-#define ZXIC_LIST_STACK_ALLOC_INDEX_INVALID      (ZXIC_LIST_STACK_BASE    | 0x006)
-#define ZXIC_LIST_STACK_ALLOC_INDEX_USED         (ZXIC_LIST_STACK_BASE    | 0x007)
-
-/* avl tree */
-#define ZXIC_AVL_TREE_BASE                       (ZXIC_RC_BASE            | 0x900)
-#define ZXIC_AVL_TREE_INVALID_INDEX              (ZXIC_AVL_TREE_BASE      | 0x001)
-#define ZXIC_AVL_TREE_SORT_INIT_INPUT_PARA_ERR   (ZXIC_AVL_TREE_BASE      | 0x002)
-#define ZXIC_AVL_TREE_SORT_ISEMPTY_ERR           (ZXIC_AVL_TREE_BASE      | 0x003)
-#define ZXIC_AVL_TREE_SORT_INSERT_SAME_KEY       (ZXIC_AVL_TREE_BASE      | 0x004)
-#define ZXIC_AVL_TREE_SORT_IS_FULL               (ZXIC_AVL_TREE_BASE      | 0x005)
-#define ZXIC_AVL_TREE_KEY_SIZE_ERR               (ZXIC_AVL_TREE_BASE      | 0x006)
-
-/* index fill */
-#define ZXIC_INDEX_FILL_BASE                     (ZXIC_RC_BASE            | 0xA00)
-#define ZXIC_INDEX_FILL_FULL                     (ZXIC_INDEX_FILL_BASE    | 0x001)
-#define ZXIC_INDEX_DEL_FAIL                      (ZXIC_INDEX_FILL_BASE    | 0x002)
-
-#define ZXIC_COMM_LOG_BASE                       (ZXIC_RC_BASE            | 0xB00)
-#define ZXIC_COMM_LOG_MUTEX_CREATE_FAIL          (ZXIC_COMM_LOG_BASE      | 0x001)
-#define ZXIC_COMM_LOG_MUTEX_LOCK_FAIL            (ZXIC_COMM_LOG_BASE      | 0x002)
-#define ZXIC_COMM_LOG_FILE_RENAME_FAIL           (ZXIC_COMM_LOG_BASE      | 0x003)
-#define ZXIC_COMM_LOG_FILE_DELETE_FAIL           (ZXIC_COMM_LOG_BASE      | 0x004)
-
-/* index fill type */
-#define ZXIC_INDEX_FILL_TYPE_BASE                (ZXIC_RC_BASE                  | 0xC00)
-#define ZXIC_INDEX_FILL_TYPE_FULL                (ZXIC_INDEX_FILL_TYPE_BASE     | 0x001)
-#define ZXIC_INDEX_DEL_TYPE_FAIL                 (ZXIC_INDEX_FILL_TYPE_BASE     | 0x002)
-
-#define ZXIC_COMM_C_INVALID_PARAM                (ZXIC_COMM_LOG_BASE | 0x005)
-
-#define ZXIC_E_LLT_CHECK                  (25) 
-#define ZXIC_E_LLT_ASSERT                 (26) 
-
-#endif  /* END 返回值宏定义 */
-
-#if ZXIC_REAL("")
-signed int  ic_comm_snprintf_s(char *buffer, size_t sizeofbuf, size_t count, const char *format, ...);
-signed int ic_comm_vsnprintf_s(char *buffer, size_t sizeofbuf, size_t count, const char *format, va_list ap);
-signed int ic_comm_sscanf(const char * src, const char * format, ...);
-char *ic_comm_strcpy_s( char *pcDst, size_t dwMaxSize, const char *pcSrc);
-char *ic_comm_strncpy_s( char *pcDst, size_t dwMaxSize, const char *pcSrc, size_t dwCount );
-unsigned int ic_comm_memcpy(void* dest, const void* src, size_t n);
-unsigned int ic_comm_memcpy_s(void* dest, size_t dest_len, const void* src, size_t n);
-char *ic_comm_strcat_s( char *pcDst, size_t dwMaxSize, const char *pcSrc );
-char *ic_comm_strncat_s( char *pcDst, size_t dwMaxSize, const char *pcSrc, size_t dwCount );
-size_t ic_comm_strnlen_s( const char  *str, size_t MaxCount);
-char* ic_comm_strtok_s(char* string_org, const char* demial, char** context);
-ZXIC_OS_CALLBACK* zxic_comm_get_os_callback(void);
-void* ic_comm_malloc_memory(unsigned int size);
-void ic_comm_free_record(void);
-unsigned int zxic_comm_index_check(unsigned int val, unsigned int min, unsigned int max);
-unsigned int zxic_comm_dev_index_check(unsigned int dev_id, unsigned int val, unsigned int min, unsigned int max);
-unsigned int zxic_comm_index_check(unsigned int val, unsigned int min, unsigned int max);
-#endif
-
-#endif /* end  __ZXIC_COMMON_TOP_H__ */
+/**************************************************************
+* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司
+* 文件名称      : zxic_comm_top.h
+* 文件标识      :
+* 内容摘要      :提供少许 common.h 开头就要用到的宏
+* 其它说明      : 项目线不需要感知
+* 当前版本      :
+* 作    者      :
+* 完成日期      : 2020/07/20
+* DEPARTMENT: 有线开发四部-系统软件团队
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#ifndef __ZXIC_PRIVATE_TOP_H__
+#define __ZXIC_PRIVATE_TOP_H__
+
+//#include <ctype.h>
+//#include <stdlib.h>
+//#include <stdio.h>
+#include <linux/stddef.h>
+#include <linux/string.h>
+//#include <errno.h>
+//#include <assert.h>
+#include <stdarg.h>
+//#include <math.h>
+#include <linux/stat.h>
+#include <linux/semaphore.h>
+
+#define ZXIC_REAL(x) (1U) /* 用于#if 对同一类的代码进行  分段    */
+#define ZXIC_NOREAL(x) (0U) /* 用于#if   对同一类的代码进行  分段    */
+
+#ifndef ZXIC_OS_WIN /* 操作系统类型导入,编译宏控制 */
+#define ZXIC_OS_LINUX /* 默认为LINUX操作系统 */
+#endif
+
+#if ZXIC_REAL("内存")
+typedef void *(*ZXIC_OS_MEM_MALLOC)(unsigned int mem_size);
+typedef void (*ZXIC_OS_MEM_FREE)(void *p_free);
+
+typedef struct _zxic_os_callback {
+	ZXIC_OS_MEM_MALLOC p_mem_malloc;
+	ZXIC_OS_MEM_FREE p_mem_free;
+} ZXIC_OS_CALLBACK;
+#endif
+
+#if ZXIC_REAL("大小端")
+/*大小端序专用*/
+typedef union zxic_endian_u {
+	unsigned int a;
+	unsigned char b;
+} ZXIC_ENDIAN_U;
+#endif
+
+#if ZXIC_REAL("异常返回值宏定义")
+#define ZXIC_RC_BASE (0x1000U)
+
+/* bit_stream */
+#define ZXIC_BIT_STREAM_BASE (ZXIC_RC_BASE | 0x100)
+#define ZXIC_BIT_STREAM_INDEX_ERR (ZXIC_BIT_STREAM_BASE | 0x001)
+#define ZXIC_BIT_STREAM_DATA_TOO_BIG (ZXIC_BIT_STREAM_BASE | 0x002)
+
+/* parameter check */
+#define ZXIC_PARAMETER_CHK_BASE (ZXIC_RC_BASE | 0x200)
+#define ZXIC_PAR_CHK_POINT_NULL (ZXIC_PARAMETER_CHK_BASE | 0x001)
+#define ZXIC_PAR_CHK_ARGIN_ZERO (ZXIC_PARAMETER_CHK_BASE | 0x002)
+#define ZXIC_PAR_CHK_ARGIN_OVERFLOW (ZXIC_PARAMETER_CHK_BASE | 0x003)
+#define ZXIC_PAR_CHK_ARGIN_ERROR (ZXIC_PARAMETER_CHK_BASE | 0x004)
+#define ZXIC_PAR_CHK_INVALID_INDEX (ZXIC_PARAMETER_CHK_BASE | 0x005)
+#define ZXIC_PAR_CHK_INVALID_RANGE (ZXIC_PARAMETER_CHK_BASE | 0x006)
+#define ZXIC_PAR_CHK_INVALID_DEV_ID (ZXIC_PARAMETER_CHK_BASE | 0x007)
+#define ZXIC_PAR_CHK_INVALID_PARA (ZXIC_PARAMETER_CHK_BASE | 0x008)
+
+/* mutex lock */
+#define ZXIC_MUTEX_LOCK_BASE (ZXIC_RC_BASE | 0x300)
+#define ZXIC_MUTEX_LOCK_INIT_FAIL (ZXIC_MUTEX_LOCK_BASE | 0x001)
+#define ZXIC_MUTEX_LOCK_LOCK_FAIL (ZXIC_MUTEX_LOCK_BASE | 0x002)
+#define ZXIC_MUTEX_LOCK_ULOCK_FAIL (ZXIC_MUTEX_LOCK_BASE | 0X003)
+#define ZXIC_MUTEX_LOCK_DESTROY_FAIL (ZXIC_MUTEX_LOCK_BASE | 0X004)
+
+/* thread */
+#define ZXIC_THREAD_BASE (ZXIC_RC_BASE | 0x400)
+#define ZXIC_THREAD_INFO_ADD_FAIL (ZXIC_THREAD_BASE | 0x001)
+#define ZXIC_THREAD_CREATE_FAIL (ZXIC_THREAD_BASE | 0x002)
+
+/* socket */
+#define ZXIC_SOCKET_BASE (ZXIC_RC_BASE | 0x400)
+#define ZXIC_SOKET_SERVICE_START_FAIL (ZXIC_THREAD_BASE | 0x001)
+#define ZXIC_SOKET_SERVICE_CLOSE_FAIL (ZXIC_THREAD_BASE | 0x002)
+#define ZXIC_SOKET_SET_PARA_FAIL (ZXIC_THREAD_BASE | 0x003)
+#define ZXIC_SOKET_CREATE_FAIL (ZXIC_THREAD_BASE | 0x004)
+#define ZXIC_SOKET_BIND_LISTEN_FAIL (ZXIC_THREAD_BASE | 0x005)
+#define ZXIC_SOKET_CONNECT_FAIL (ZXIC_THREAD_BASE | 0x006)
+#define ZXIC_SOKET_CLOSE_FAIL (ZXIC_THREAD_BASE | 0x007)
+#define ZXIC_SOKET_GET_PARA_FAIL (ZXIC_THREAD_BASE | 0x008)
+
+/* double link */
+#define ZXIC_DOUBLE_LINK_BASE (ZXIC_RC_BASE | 0x500)
+#define ZXIC_DOUBLE_LINK_ELEMENT_NUM_ERR (ZXIC_DOUBLE_LINK_BASE | 0x001)
+#define ZXIC_DOUBLE_LINK_MALLOC_FAIL (ZXIC_DOUBLE_LINK_BASE | 0x002)
+#define ZXIC_DOUBLE_LINK_POINT_NULL (ZXIC_DOUBLE_LINK_BASE | 0x003)
+#define ZXIC_DOUBLE_LINK_CHK_SUM_ERR (ZXIC_DOUBLE_LINK_BASE | 0x004)
+#define ZXIC_DOUBLE_LINK_NO_EXIST_FREENODE (ZXIC_DOUBLE_LINK_BASE | 0x005)
+#define ZXIC_DOUBLE_LINK_FREE_INDX_INVALID (ZXIC_DOUBLE_LINK_BASE | 0x006)
+#define ZXIC_DOUBLE_LINK_NO_EXIST_PRENODE (ZXIC_DOUBLE_LINK_BASE | 0x007)
+#define ZXIC_DOUBLE_LINK_INPUT_INDX_INVALID (ZXIC_DOUBLE_LINK_BASE | 0x008)
+#define ZXIC_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR (ZXIC_DOUBLE_LINK_BASE | 0x009)
+
+/* index ctrl */
+#define ZXIC_INDEX_CTRL_BASE (ZXIC_RC_BASE | 0x600)
+#define ZXIC_INDEX_CTRL_TREE_FULL (ZXIC_INDEX_CTRL_BASE | 0x001)
+#define ZXIC_INDEX_CTRL_SAME_RECORD (ZXIC_INDEX_CTRL_BASE | 0x002)
+#define ZXIC_INDEX_CTRL_OPER_MODE_ERR (ZXIC_INDEX_CTRL_BASE | 0x003)
+
+/* index reverse */
+#define ZXIC_INDEX_RSV_BASE (ZXIC_RC_BASE | 0x700)
+#define ZXIC_INDEX_RESERVE_GET_INDX_FAIL (ZXIC_INDEX_RSV_BASE | 0x001)
+#define ZXIC_INDEX_RESERVE_BORROW_HIG_FAIL (ZXIC_INDEX_RSV_BASE | 0x002)
+#define ZXIC_INDEX_RESERVE_BORROW_LOW_FAIL (ZXIC_INDEX_RSV_BASE | 0x003)
+#define ZXIC_INDEX_RESERVE_ALLOCI_INDX_FAIL (ZXIC_INDEX_RSV_BASE | 0x004)
+#define ZXIC_INDEX_RESERVE_FREE_INDX_FAIL (ZXIC_INDEX_RSV_BASE | 0x005)
+#define ZXIC_INDEX_RESERVE_RESET_INDX_FAIL (ZXIC_INDEX_RSV_BASE | 0x006)
+
+/* list stack */
+#define ZXIC_LIST_STACK_BASE (ZXIC_RC_BASE | 0x800)
+#define ZXIC_LIST_STACK_ELEMENT_NUM_ERR (ZXIC_LIST_STACK_BASE | 0x001)
+#define ZXIC_LIST_STACK_POINT_NULL (ZXIC_LIST_STACK_BASE | 0x002)
+#define ZXIC_LIST_STACK_ALLOC_MEMORY_FAIL (ZXIC_LIST_STACK_BASE | 0x003)
+#define ZXIC_LIST_STACK_ISEMPTY_ERR (ZXIC_LIST_STACK_BASE | 0x004)
+#define ZXIC_LIST_STACK_FREE_INDEX_INVALID (ZXIC_LIST_STACK_BASE | 0x005)
+#define ZXIC_LIST_STACK_ALLOC_INDEX_INVALID (ZXIC_LIST_STACK_BASE | 0x006)
+#define ZXIC_LIST_STACK_ALLOC_INDEX_USED (ZXIC_LIST_STACK_BASE | 0x007)
+
+/* avl tree */
+#define ZXIC_AVL_TREE_BASE (ZXIC_RC_BASE | 0x900)
+#define ZXIC_AVL_TREE_INVALID_INDEX (ZXIC_AVL_TREE_BASE | 0x001)
+#define ZXIC_AVL_TREE_SORT_INIT_INPUT_PARA_ERR (ZXIC_AVL_TREE_BASE | 0x002)
+#define ZXIC_AVL_TREE_SORT_ISEMPTY_ERR (ZXIC_AVL_TREE_BASE | 0x003)
+#define ZXIC_AVL_TREE_SORT_INSERT_SAME_KEY (ZXIC_AVL_TREE_BASE | 0x004)
+#define ZXIC_AVL_TREE_SORT_IS_FULL (ZXIC_AVL_TREE_BASE | 0x005)
+#define ZXIC_AVL_TREE_KEY_SIZE_ERR (ZXIC_AVL_TREE_BASE | 0x006)
+
+/* index fill */
+#define ZXIC_INDEX_FILL_BASE (ZXIC_RC_BASE | 0xA00)
+#define ZXIC_INDEX_FILL_FULL (ZXIC_INDEX_FILL_BASE | 0x001)
+#define ZXIC_INDEX_DEL_FAIL (ZXIC_INDEX_FILL_BASE | 0x002)
+
+#define ZXIC_COMM_LOG_BASE (ZXIC_RC_BASE | 0xB00)
+#define ZXIC_COMM_LOG_MUTEX_CREATE_FAIL (ZXIC_COMM_LOG_BASE | 0x001)
+#define ZXIC_COMM_LOG_MUTEX_LOCK_FAIL (ZXIC_COMM_LOG_BASE | 0x002)
+#define ZXIC_COMM_LOG_FILE_RENAME_FAIL (ZXIC_COMM_LOG_BASE | 0x003)
+#define ZXIC_COMM_LOG_FILE_DELETE_FAIL (ZXIC_COMM_LOG_BASE | 0x004)
+
+/* index fill type */
+#define ZXIC_INDEX_FILL_TYPE_BASE (ZXIC_RC_BASE | 0xC00)
+#define ZXIC_INDEX_FILL_TYPE_FULL (ZXIC_INDEX_FILL_TYPE_BASE | 0x001)
+#define ZXIC_INDEX_DEL_TYPE_FAIL (ZXIC_INDEX_FILL_TYPE_BASE | 0x002)
+
+#define ZXIC_COMM_C_INVALID_PARAM (ZXIC_COMM_LOG_BASE | 0x005)
+
+#define ZXIC_E_LLT_CHECK (25)
+#define ZXIC_E_LLT_ASSERT (26)
+
+#endif /* END 返回值宏定义 */
+
+#if ZXIC_REAL("")
+signed int ic_comm_snprintf_s(char *buffer, size_t sizeofbuf, size_t count,
+							  const char *format, ...);
+signed int ic_comm_vsnprintf_s(char *buffer, size_t sizeofbuf, size_t count,
+							   const char *format, va_list ap);
+signed int ic_comm_sscanf(const char *src, const char *format, ...);
+char *ic_comm_strcpy_s(char *pcDst, size_t dwMaxSize, const char *pcSrc);
+char *ic_comm_strncpy_s(char *pcDst, size_t dwMaxSize, const char *pcSrc,
+						size_t dwCount);
+unsigned int ic_comm_memcpy(void *dest, const void *src, size_t n);
+unsigned int ic_comm_memcpy_s(void *dest, size_t dest_len, const void *src,
+							  size_t n);
+char *ic_comm_strcat_s(char *pcDst, size_t dwMaxSize, const char *pcSrc);
+char *ic_comm_strncat_s(char *pcDst, size_t dwMaxSize, const char *pcSrc,
+						size_t dwCount);
+size_t ic_comm_strnlen_s(const char *str, size_t MaxCount);
+char *ic_comm_strtok_s(char *string_org, const char *demial, char **context);
+ZXIC_OS_CALLBACK *zxic_comm_get_os_callback(void);
+void *ic_comm_malloc_memory(unsigned int size);
+void ic_comm_free_record(void);
+unsigned int zxic_comm_index_check(unsigned int val, unsigned int min,
+								   unsigned int max);
+unsigned int zxic_comm_dev_index_check(unsigned int dev_id, unsigned int val,
+									   unsigned int min, unsigned int max);
+unsigned int zxic_comm_index_check(unsigned int val, unsigned int min,
+								   unsigned int max);
+#endif
+
+#endif /* end  __ZXIC_COMMON_TOP_H__ */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_slt.h b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_slt.h
index d23ebccccb041da553f5511bca4c2c14d6a8b84f..8b33892926d2dd715fdfbe07a4fc95d42cd5fce6 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_slt.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/include/zxic_slt.h
@@ -1,751 +1,781 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : zxic_slt.h
-* 文件标识 : 
-* 内容摘要 : 
-* 其它说明 : 
-* 当前版本 : 
-* 作    者 : PJ
-* 完成日期 : 2022/03/26
-* DEPARTMENT: ASIC_FPGA_R&D_Dept 
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* 版 本 号:  
-* 修 改 人:  
-* 修改内容:  
-***************************************************************/
-
-#ifndef __ZXIC_SLT_H__
-#define __ZXIC_SLT_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-#define ZXIC_SLT_CASE_PASS                        (0U)
-#define ZXIC_SLT_CASE_FAILURE                     (1U)
-
-#define ZXIC_SLT_ERR_INFO_LEN                     (255U)
-#define ZXIC_SLT_CASE_MAX_NUM                     (255U)
-#define ZXIC_SLT_DEV_ID_MAX_NUM                   (4U)
-#define ZXIC_SLT_CHIP_ID_LEN                      (3U)
-
-/* 封装类型，不同产品含义不同，暂时定义最大支持5个*/
-#define ZXIC_SLT_MAX_ENCAP                        (5U)
-
-
-/* BIN_CODE 编码*/
-#define ZXIC_SLT_BIN_CODE_PASS                    ZXIC_SLT_CASE_PASS
-#define ZXIC_SLT_BIN_CODE_SERDES_FAIL             (1U)/* sredes类检测*/
-#define ZXIC_SLT_BIN_CODE_FLOW_FAIL               (2U)/* pvt类检测 FLOW通流类*/
-#define ZXIC_SLT_BIN_CODE_RAM_FAIL                (3U)/* RAM类检测*/
-#define ZXIC_SLT_BIN_CODE_HBM_DDR_FAIL            (4U)/* hbm类检测*/
-#define ZXIC_SLT_BIN_CODE_OTHER_FAIL              (5U)/* PLL EFUSE PCIE RISCV */
-#define ZXIC_SLT_BIN_CODE_MIX_FAIL                (6U)/* 上述多种类型的混合*/
-
-
-
-
-/* 测试用例全集case_no定义*/
-typedef enum zxic_slt_case_no_e
-{
-    ZXIC_SLT_CASE_PLL_LOCK_STATUS_CHECK       = (0x08U),
-    /* efuse锁定相关测试用例 */
-    ZXIC_SLT_CASE_EFUSE_CHECK                 = (0x09U),
-
-
-
-
-    /* serdes用例编号范围0x10~0x7f*/
-    /* lifx(LIF0 LIF1 LIF2)接口serdes prbs相关测试用例  0x10~0x2f*/
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_1G         = (0x10U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_3G         = (0x11U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_5G         = (0x12U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_6G         = (0x13U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_9G         = (0x14U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_10G        = (0x15U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_12G        = (0x16U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_15G        = (0x17U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_20G        = (0x18U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_25G        = (0x19U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_26G        = (0x1aU),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_27G        = (0x1bU),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_28G        = (0x1cU),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_30G        = (0x1dU),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_50G        = (0x1fU),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_51G        = (0x20U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_53G        = (0x21U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_55G        = (0x22U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_56G        = (0x23U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_57G        = (0x24U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_98G        = (0x25U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_106G       = (0x26U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_111G       = (0x27U),
-    ZXIC_SLT_CASE_SERDES_LIFX_PRBS_112G       = (0x28U),
-
-
-    /* lifc接口serdes相关测试用例 0x30~0x37*/
-    ZXIC_SLT_CASE_SERDES_LIFC_PRBS_1G         = (0x30U),
-    ZXIC_SLT_CASE_SERDES_LIFC_PRBS_10G        = (0x31U),
-    ZXIC_SLT_CASE_SERDES_LIFC_PRBS_25G        = (0x32U),
-    ZXIC_SLT_CASE_SERDES_LIFC_PRBS_53G        = (0x33U),
-
-    /* lifc eth 接口发包测试相关测试用例 0x38~0x3f*/
-    ZXIC_SLT_CASE_PORT_LIFC_SD_1G            = (0x38U),
-    ZXIC_SLT_CASE_PORT_LIFC_SD_10G           = (0x39U),
-    ZXIC_SLT_CASE_PORT_LIFC_SD_25G           = (0x3aU),
-    ZXIC_SLT_CASE_PORT_LIFC_SD_53G           = (0x3bU),
-
-    /* 外部查找的interlaken-la接口*/
-    ZXIC_SLT_CASE_SERDES_INTERLAKEN_LA       = (0x3fU),
-
-
-    /* lif0 eth 接口发包测试相关测试用例 0x40~0x5f*/
-    ZXIC_SLT_CASE_PORT_LIFO_SD_1G         = (0x40U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_5G         = (0x41U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_10G        = (0x42U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_12G        = (0x43U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_25G        = (0x44U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_26G        = (0x45U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_51G        = (0x46U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_53G        = (0x47U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_106G       = (0x48U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_112G       = (0x49U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_20G        = (0x4AU),
-
-
-    /* lif0 intlk接口发包测试相关测试用例 0x60~0x6f*/
-    ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_3G     =  (0x60U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_6G     =  (0x61U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_10G    =  (0x62U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_12G    =  (0x63U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_25G    =  (0x64U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_28G    =  (0x65U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_30G    =  (0x66U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_50G    =  (0x67U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_51G    =  (0x68U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_53G    =  (0x69U),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_56G    =  (0x6aU),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_106G   =  (0x6bU),
-    ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_112G   =  (0x6cU),
-
-
-    /* 交换侧lif1 FEC测试相关测试用例 0x70~0x7f*/
-    ZXIC_SLT_CASE_SERDES_LIF1_FEC_25G        = (0x70U),
-    ZXIC_SLT_CASE_SERDES_LIF1_FEC_26G        = (0x71U),
-    ZXIC_SLT_CASE_SERDES_LIF1_FEC_28G        = (0x72U),
-    ZXIC_SLT_CASE_SERDES_LIF1_FEC_50G        = (0x73U),
-    ZXIC_SLT_CASE_SERDES_LIF1_FEC_53G        = (0x74U),
-    ZXIC_SLT_CASE_SERDES_LIF1_FEC_56G        = (0x75U),
-    ZXIC_SLT_CASE_SERDES_LIF1_FEC_98G        = (0x76U),
-    ZXIC_SLT_CASE_SERDES_LIF1_FEC_106G       = (0x77U),
-    ZXIC_SLT_CASE_SERDES_LIF1_FEC_112G       = (0x78U),
-
-
-
-
-    /*片内ram用例编号范围0x80~0x87*/
-    /* CPU可读写寄存器测试用例 */
-    ZXIC_SLT_CASE_REG_CPU_W_R                      =  (0x80U),
-    /* CPU可读写ram测试用例 */
-    ZXIC_SLT_CASE_RAM_CPU_W_R                      =  (0x81U),
-    /* RAM表项读写测试(微码)*/
-    ZXIC_SLT_CASE_RAM_MC_W_R                       =  (0x82U),
-   /* RAM表项读写测试 memtest86(微码)*/
-    ZXIC_SLT_CASE_RAM_MC_MEMTEST86                 =  (0x83U),
-
-
-
-
-    /* HBM/DDR用例编号范围 0x90~0x9f*/
-    /*mbist测试*/
-    ZXIC_SLT_CASE_HBM_DDR_CTRL_BIST                =  (0x90U),
-    /* HBM/DDR表项CPU读写测试*/
-    ZXIC_SLT_CASE_HBM_DDR_CPU_W_R                  =  (0x91U),
-    /* HBM/DDR表项读写测试(微码)*/
-    ZXIC_SLT_CASE_HBM_DDR_MC_W_R                   =  (0x92U),
-    /* HBM/DDR表项读写测试 memtest86(微码)*/
-    ZXIC_SLT_CASE_HBM_DDR_MC_MEMTEST86             =  (0x93U),
-    /* HBM/DDR TM覆盖测试*/
-    ZXIC_SLT_CASE_HBM_DDR_TM_TEST                  =  (0x94U),
-
-
-
-
-
-    /* 发流测试和全业务PVT测试用例编号范围 0xa0~0xaf*/
-    /* 数据路径测试用例 */
-    ZXIC_SLT_CASE_PKT_FLOW_NOM                      =  (0xA0U),
-    /* OAM发包测试用例 */
-    ZXIC_SLT_CASE_OAM_SEND_PKT                      =  (0xA1U),
-    /* se查表全集测试 */
-    ZXIC_SLT_CASE_PKT_FLOW_SE_FULL                  =  (0xA2U),
-    /* tm全队列测试用例 */
-    ZXIC_SLT_CASE_PKT_FLOW_TM_FULL                  =  (0xA3U),
-    /* LIFC口测试用例 */
-    ZXIC_SLT_CASE_PKT_FLOW_LIFC                     =  (0xA4U),
-
-    /* 芯片PVT 功耗、温度和电压测试用例 */
-    ZXIC_SLT_CASE_PVT_EXCEED_POWER_TEST             =  (0xA8U),
-    ZXIC_SLT_CASE_PVT_EXCEED_TEM_VOLT_TEST          =  (0xA9U),
-    ZXIC_SLT_CASE_PVT_EXCEED_HBM_TEMPER_TEST        =  (0xAaU),
-
-
-
-
-
-    /* 其他测试用例编号范围0xb0~0xff*/
-    /* 调压测试*/
-    ZXIC_SLT_CASE_VOLT_TEST                         =  (0xB0U),
-    /* 时钟频偏测试 */
-    ZXIC_SLT_CASE_CLK_TEST                          =  (0xB1U),
-
-    /* PCIE压力测试 */
-    ZXIC_SLT_CASE_PCIE_W_R_TEST                     =  (0xB2U),
-    /* 下述两个测试用例必须放在最后执行 */
-    /* PCIE建链测试 */
-    ZXIC_SLT_CASE_PCIE_TEST                         =  (0xB3U),
-    /* RISCV测试用例 */
-    ZXIC_SLT_CASE_RISCV_W_R_TEST                     =  (0xB4U),
-
-    ZXIC_SLT_CASE_MAX,
-} ZXIC_SLT_CASE_NO_E;
-
-
-#if ZXIC_REAL("ERR_CODE")
-#define ZXIC_SLT_RC_BASE                              (0x100U)
-
-
- #define ZXIC_SLT_TEST_CASE_FNC_POINT_NULL            (ZXIC_SLT_RC_BASE | 0x1)  
- #define ZXIC_SLT_CASE_PLL_LOCK_STATUS_CHECK_FAIL     (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PLL_LOCK_STATUS_CHECK)  
- #define ZXIC_SLT_CASE_EFUSE_CHECK_FAIL               (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_EFUSE_CHECK)  
- 
- /* lifx*/                                            
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_1G_FAIL        (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_1G)  
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_3G_FAIL        (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_3G)  
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_5G_FAIL        (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_5G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_6G_FAIL        (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_6G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_9G_FAIL        (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_9G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_10G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_10G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_12G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_12G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_15G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_15G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_20G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_20G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_25G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_25G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_26G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_26G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_27G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_27G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_28G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_28G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_30G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_30G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_50G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_50G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_51G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_51G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_53G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_53G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_55G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_55G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_56G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_56G)  
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_57G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_57G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_98G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_98G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_106G_FAIL      (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_106G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_111G_FAIL      (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_111G)     
- #define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_112G_FAIL      (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_112G)     
-     
- /* lifc*/                                            
- #define ZXIC_SLT_CASE_SERDES_LIFC_PRBS_1G_FAIL        (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFC_PRBS_1G)   
- #define ZXIC_SLT_CASE_SERDES_LIFC_PRBS_10G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFC_PRBS_10G)     
- #define ZXIC_SLT_CASE_SERDES_LIFC_PRBS_25G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFC_PRBS_25G)     
- #define ZXIC_SLT_CASE_SERDES_LIFC_PRBS_53G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFC_PRBS_53G)     
-   
- /* lifc */                                           
- #define ZXIC_SLT_CASE_PORT_LIFC_SD_1G_FAIL            (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFC_SD_1G )  
- #define ZXIC_SLT_CASE_PORT_LIFC_SD_10G_FAIL           (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFC_SD_10G)  
- #define ZXIC_SLT_CASE_PORT_LIFC_SD_25G_FAIL           (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFC_SD_25G)   
- #define ZXIC_SLT_CASE_PORT_LIFC_SD_53G_FAIL           (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFC_SD_53G)  
-    
- /* lif0 ETH*/                                        
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_1G_FAIL           (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_1G)  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_5G_FAIL           (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_5G)  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_10G_FAIL          (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_10G)  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_12G_FAIL          (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_12G)  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_25G_FAIL          (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_25G)  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_26G_FAIL          (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_26G)  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_51G_FAIL          (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_51G)   
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_53G_FAIL          (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_53G)   
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_106G_FAIL         (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_106G)   
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_112G_FAIL         (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_112G) 
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_20G_FAIL          (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_20G)   
-    
- /* lif0 intlk*/                                      
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_3G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_3G  )  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_6G_FAIL       (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_6G  )  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_10G_FAIL      (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_10G )    
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_12G_FAIL      (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_12G )  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_25G_FAIL      (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_25G )  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_28G_FAIL      (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_28G )  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_30G_FAIL      (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_30G )  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_50G_FAIL      (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_50G )  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_51G_FAIL      (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_51G )  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_53G_FAIL      (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_53G )  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_56G_FAIL      (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_56G )  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_106G_FAIL     (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_106G)  
- #define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_112G_FAIL     (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_112G )  
-
-
-/* lif1*/                                              
-#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_25G_FAIL   (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_25G)  
-#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_26G_FAIL   (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_26G)    
-#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_28G_FAIL   (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_28G)   
-#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_50G_FAIL   (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_50G) 
-#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_53G_FAIL   (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_53G)   
-#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_56G_FAIL   (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_56G)
-#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_98G_FAIL   (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_98G)  
-#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_106G_FAIL  (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_106G)   
-#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_112G_FAIL  (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_112G) 
-
-/* 外部查找的interlaken-la接口*/
-#define ZXIC_SLT_CASE_SERDES_INTELAKEN_LA_FAIL   (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_INTELAKEN_LA) 
-
- 
- /*片内ram读写测试*/                                   
- #define ZXIC_SLT_CASE_RAM_CPU_W_R_FAIL               (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_RAM_CPU_W_R )  
- #define ZXIC_SLT_CASE_REG_CPU_W_R_FAIL               (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_REG_CPU_W_R  )  
- #define ZXIC_SLT_CASE_RAM_MC_W_R_FAIL                (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_RAM_MC_W_R  )  
- #define ZXIC_SLT_CASE_RAM_MC_MEMTEST86_FAIL          (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_RAM_MC_MEMTEST86 )  
-
- /* HBM/DDR */
- #define ZXIC_SLT_CASE_HBM_DDR_CTRL_BIST_FAIL         (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_HBM_DDR_CTRL_BIST    )  
- #define ZXIC_SLT_CASE_HBM_DDR_MC_W_R_FAIL            (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_HBM_DDR_MC_W_R       )  
- #define ZXIC_SLT_CASE_HBM_DDR_MC_MEMTEST86_FAIL      (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_HBM_DDR_MC_MEMTEST86 )  
- #define ZXIC_SLT_CASE_HBM_DDR_CPU_W_R_FAIL           (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_HBM_DDR_CPU_W_R )  
- #define ZXIC_SLT_CASE_HBM_DDR_TM_TEST_FAIL           (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_HBM_DDR_TM_TEST      )  
-
-
- /* 发流测试和全业务PVT测试*/
- #define ZXIC_SLT_CASE_PKT_FLOW_NOM_FAIL               (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PKT_FLOW_NOM              )  
- #define ZXIC_SLT_CASE_OAM_SEND_PKT_FAIL               (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_OAM_SEND_PKT              )  
- #define ZXIC_SLT_CASE_PKT_FLOW_SE_FULL_FAIL           (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PKT_FLOW_SE_FULL          )  
- #define ZXIC_SLT_CASE_PKT_FLOW_TM_FULL_FAIL           (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PKT_FLOW_TM_FULL          )   
- #define ZXIC_SLT_CASE_PKT_FLOW_LIFC_FAIL              (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PKT_FLOW_LIFC  )
-
- #define ZXIC_SLT_CASE_PVT_EXCEED_POWER_TEST_FAIL      (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PVT_EXCEED_POWER_TEST     )  
- #define ZXIC_SLT_CASE_PVT_EXCEED_TEM_VOLT_TEST_FAIL   (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PVT_EXCEED_TEM_VOLT_TEST  )  
- #define ZXIC_SLT_CASE_PVT_EXCEED_HBM_TEMPER_TEST_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PVT_EXCEED_HBM_TEMPER_TEST)  
-
-
- #define ZXIC_SLT_CASE_PCIE_TEST_FAIL                  (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PCIE_TEST    )  
- #define ZXIC_SLT_CASE_PCIE_W_R_TEST_FAIL              (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PCIE_W_R_TEST    )  
- #define ZXIC_SLT_CASE_RISCV_W_R_TEST_FAIL              (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_RISCV_W_R_TEST)  
- #define ZXIC_SLT_CASE_VOLT_TEST_FAIL                  (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_VOLT_TEST    )  
- #define ZXIC_SLT_CASE_CLK_TEST_FAIL                   (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_CLK_TEST)  
-
-#endif 
-
-
-typedef struct zxic_slt_err_info_mng_t
-{
-    ZXIC_UINT32         err_code;      /*参见ERR_CODE定义*/
-    const ZXIC_CHAR *   err_info;
-} ZXIC_SLT_ERR_INFO_MNG_T;
-
-
-typedef struct zxic_slt_init_ctrl_t
-{
-    ZXIC_ADDR_T pcie_vir_baddr;               /**<  @brief PCIe映射虚拟基地址*/
-    ZXIC_ADDR_T riscv_vir_baddr;               /**<  @brief RISCV映射虚拟基地址 */
-    ZXIC_ADDR_T dma_vir_baddr;                /**<  @brief DMA映射虚拟地址*/
-    ZXIC_ADDR_T dma_phy_baddr;                /**<  @brief DMA内存物理地址*/
-}ZXIC_SLT_INIT_CTRL_T;
-
-
-typedef struct zxic_slt_case_para_t
-
-{
-    ZXIC_UINT32 chip_id[ZXIC_SLT_CHIP_ID_LEN];      /* 返回对应芯片ID */
-    ZXIC_UINT32 case_num;                           /* 返回执行SLT 用例数 */
-    ZXIC_UINT32 case_no[ZXIC_SLT_CASE_MAX_NUM];     /* 返回执行SLT 用例编号列表 */
-    ZXIC_UINT32 case_result[ZXIC_SLT_CASE_MAX_NUM]; /* 返回执行SLT 用例对应结果，成功返回值或错误码 */
-    ZXIC_UINT32 bin_code;                           /* 返回 SLT 执行分BIN码 */	
-    ZXIC_DOUBLE temp;                               /* 返回 SLT 用例测试前初始温度 */
-    ZXIC_DOUBLE volt;                               /* 返回 SLT 用例测试前核电压 */
-
-} ZXIC_SLT_CASE_PARA_T;
-
-
-
-/*case 函数标准定义*/
-typedef ZXIC_RTN32 (*ZXIC_SLT_INST_CASE_FN)(ZXIC_UINT32 device_id);
-
-typedef struct zxic_slt_case_mng_t
-{
-    const ZXIC_CHAR *        case_name;     /*用例名称*/
-    ZXIC_UINT32              case_no;       /*参见ZXIC_SLT_CASE_NO_E定义*/
-    ZXIC_SLT_INST_CASE_FN    inst_case_fn; /*单个case函数指针*/
-} ZXIC_SLT_CASE_MNG_T;
-
-
-
-/* 功耗类型定义*/
-typedef enum zxic_slt_power_type_t
-{
-    ZXIC_SLT_POWER_VCC_SSP4_CORE                =  (0x0U),
-    ZXIC_SLT_POWER_VCC0V75_SSP4_SERDES_DVDD     =  (0x1U),
-    ZXIC_SLT_POWER_VCC0V75_SSP4_SERDES_AVDDL    =  (0x2U),
-    ZXIC_SLT_POWER_VCC1V2_SSP4_SERDES_AVDDH     =  (0x3U),
-    ZXIC_SLT_POWER_VCC1V2_SSP4_HBM_VDDQ         =  (0x4U),
-
-    ZXIC_SLT_POWER_VCC0V75_SSP4_AVDD            =  (0x5U),
-    ZXIC_SLT_POWER_VCC1V2_SSP4_AVDD             =  (0x6U),
-    ZXIC_SLT_POWER_VCC1V2_SSP4_GPIO_DVDD        =  (0x7U),
-    ZXIC_SLT_POWER_VCC2V5_SSP4_VPP              =  (0x8U),
-
-    ZXIC_SLT_POWER_TYPE_MAX,
-
-}ZXIC_SLT_POWER_TYPE_T;
-
-typedef struct zxic_slt_power_t
-{
-
-   ZXIC_DOUBLE volt;   /* 电压值 */
-   ZXIC_DOUBLE cur;    /* 电流值 */
-   ZXIC_UINT32 type;   /* 功耗编码，参见ZXIC_SLT_POWER_TYPE_T定义 */
-}ZXIC_SLT_POWER_T;
-
-typedef struct zxic_slt_power_para_t
-{
-   ZXIC_SLT_POWER_T *p_para;
-   ZXIC_UINT32 num;  /* 有效功耗个数 */
-}ZXIC_SLT_POWER_PARA_T;
-
-
-
-/* 电压类型定义*/
-typedef enum zxic_slt_volt_type_t
-{
-    ZXIC_SLT_VOLT_VCC_SSP4_CORE                =  (0x0U),
-    ZXIC_SLT_VOLT_VCC0V75_SSP4_SERDES_DVDD     =  (0x1U),
-    ZXIC_SLT_VOLT_VCC0V75_SSP4_SERDES_AVDDL    =  (0x2U),
-    ZXIC_SLT_VOLT_VCC1V2_SSP4_SERDES_AVDDH     =  (0x3U),
-    ZXIC_SLT_VOLT_VCC1V2_SSP4_HBM_VDDQ         =  (0x4U),
-    
-    ZXIC_SLT_VOLT_TYPE_MAX,
-
-}ZXIC_SLT_VOLT_TYPE_T;
-
-typedef struct zxic_slt_volt_t
-{
-
-   ZXIC_UINT32 percent;   /* 调压上下浮动值，百分比*100,例如上调1%，传入数值1*/
-   ZXIC_UINT32 flag;      /* 正偏：0   负偏：1 */
-   ZXIC_UINT32 vol_type;  /* 电压类型，参见ZXIC_SLT_VOLT_TYPE_T定义 */
-}ZXIC_SLT_VOLT_T;
-
-typedef struct zxic_slt_volt_para_t
-{
-   ZXIC_SLT_VOLT_T *p_para;
-   ZXIC_UINT32 num;  /* 有效调压个数 */
-}ZXIC_SLT_VOLT_PARA_T;
-
-
-
-/* 时钟类型定义*/
-typedef enum zxic_slt_clk_type_t
-{
-    ZXIC_SLT_CLK_AU5327_A          =  (0x0U),/*SSP4 SOCKET 单板AU5327#1 HOST_100M*/
-    ZXIC_SLT_CLK_AU5327_B          =  (0x1U),/*SSP4 SOCKET 单板AU5327#1 PLL_SYS_CLK/SERDES 156.25M*/
-    ZXIC_SLT_CLK_AU5327_C          =  (0x2U),/*SSP4 SOCKET 单板AU5327#1 PLL_LOCAL_CLK  156.25M*/
-    ZXIC_SLT_CLK_AU5327_D          =  (0x3U),/*SSP4 SOCKET 单板AU5327#1 PLL_TS_CLK 125M*/
-    
-    ZXIC_SLT_CLK_TYPE_MAX,
-
-
-}ZXIC_SLT_CLK_TYPE_T;
-
-typedef struct zxic_slt_clk_t
-{
-
-   ZXIC_UINT32 value;     /* 时钟拉偏值，单位HZ(PPM),1PPM = 1HZ（1MHZ=1000KHZ=1000000HZ）*/
-   ZXIC_UINT32 flag;      /* 正偏：0   负偏：1 */
-   ZXIC_UINT32 clk_type;  /* 时钟类型，参见ZXIC_SLT_CLK_TYPE_T定义 */
-}ZXIC_SLT_CLK_T;
-
-typedef struct zxic_slt_clk_para_t
-{
-   ZXIC_SLT_CLK_T *p_para;
-   ZXIC_UINT32 num;  /* 有效拉偏时钟个数 */
-}ZXIC_SLT_CLK_PARA_T;
-
-
-
-#if ZXIC_REAL("define_for_bsp")
-/***********************************************************/
-/** 功耗获取函数
-* @param   ZXIC_SLT_CASE_GETPOWER_FN   
-* @param   device_id   
-* @param   p_para   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  PJ      @date  2022/04/28
-************************************************************/
-typedef ZXIC_RTN32 (*ZXIC_SLT_CASE_GETPOWER_FN)(ZXIC_UINT32 device_id, ZXIC_SLT_POWER_PARA_T *p_para);
-
-
-/***********************************************************/
-/** riscv测试函数
-* @param   ZXIC_SLT_CASE_RISCV_FN   
-* @param   device_id   
-* @param   reg_addr   寄存器地址
-* @param   wr_data   写入寄存器的值
-* @param   rd_data   期望从寄存器中读出的值
-*
-* @return  
-* @remark  无
-* @see     
-* @author  PJ      @date  2022/04/28
-************************************************************/
-typedef ZXIC_RTN32 (*ZXIC_SLT_CASE_RISCV_FN)(ZXIC_UINT32 device_id, ZXIC_UINT32 reg_addr, ZXIC_UINT32 wr_data, ZXIC_UINT32 rd_data);
-
-
-/***********************************************************/
-/** PCIE测试函数
-* @param   ZXIC_SLT_CASE_PCIE_FN   
-* @param   device_id   
-* @param   times  pcie建链测试次数  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  PJ      @date  2022/04/28
-************************************************************/
-typedef ZXIC_RTN32 (*ZXIC_SLT_CASE_PCIE_FN)(ZXIC_UINT32 device_id, ZXIC_UINT32 times);
-
-
-/***********************************************************/
-/** 调电压函数
-* @param   ZXIC_SLT_CASE_ADJUST_VOLT_FN   
-* @param   device_id   
-* @param   p_para   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  PJ      @date  2022/04/28
-************************************************************/
-typedef ZXIC_RTN32 (*ZXIC_SLT_CASE_ADJUST_VOLT_FN)(ZXIC_UINT32 device_id,ZXIC_SLT_VOLT_PARA_T *p_para);
-
-
-/***********************************************************/
-/** 调时钟函数
-* @param   ZXIC_SLT_CASE_ADJUST_CLK_FN   
-* @param   device_id   
-* @param   p_para   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  PJ      @date  2022/04/28
-************************************************************/
-typedef ZXIC_RTN32 (*ZXIC_SLT_CASE_ADJUST_CLK_FN)(ZXIC_UINT32 device_id,ZXIC_SLT_CLK_PARA_T *p_para);
-
-
-/*BSP回调函数定义*/
-typedef struct zxic_slt_bsp_register_fn_t
-{
-    ZXIC_SLT_CASE_GETPOWER_FN        zxic_slt_power_fn;        
-    ZXIC_SLT_CASE_RISCV_FN            zxic_slt_riscv_fn;          
-    ZXIC_SLT_CASE_PCIE_FN            zxic_slt_pcie_fn;         
-    ZXIC_SLT_CASE_ADJUST_VOLT_FN     zxic_slt_volt_fn;         
-    ZXIC_SLT_CASE_ADJUST_CLK_FN      zxic_slt_clk_fn;          
-
-} ZXIC_SLT_BSP_REGISTER_FN_T;
-
-#endif
-
-#if ZXIC_REAL("define_for_sdk")
-/***********************************************************/
-/** 初始化函数
-* @param   ZXIC_SLT_INIT_FN   
-* @param   device_id   
-* @param   chip_type  用于区分不同封装类型  
-* @param   p_init_ctrl   参见ZXIC_SLT_INIT_CTRL_T定义
-*
-* @return  
-* @remark  无
-* @see     
-* @author  PJ      @date  2022/04/22
-************************************************************/
-typedef ZXIC_RTN32 (*ZXIC_SLT_INIT_FN)(ZXIC_UINT32 device_id,ZXIC_UINT32 chip_type,ZXIC_SLT_INIT_CTRL_T *p_init_ctrl);
-
-
-
-
-/* Chip_ID 组成结构说明：
-** Chip_ID = efuse里面的wafer批次号+wafer片号+x坐标+Y坐标组合而成
-** wafer批次号: 48bit lot_id5~0
-** wafer片号:   5bit  wafer_no
-** x坐标:		8bit  x_addr
-** Y坐标:		8bit  y_addr
-** chip_id2 = lot_id5[7:3]
-** chip_id1 = lot_id5[2:0] + lot_id4 + lot_id3 + lot_id2 + lot_id1[7:3]
-** chip_id0 = lot_id1[2:0] + lot_id0 + wafer_no[4:0] + x_addr + y_addr*/
-
-/***********************************************************/
-/** 执行测试用例之前的预处理函数,用来获取chip_id,温度，电压信息
-* @param   ZXIC_SLT_PRE_FN   
-* @param   device_id   
-* @param   chip_type  用于区分不同封装类型 
-* @param   p_chip_id   返回芯片的chip_id信息(参见上述格式说明）
-* @param   p_temp  返回 SLT 用例测试前初始温度 
-* @param   p_volt  返回 SLT 用例测试前核电压 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  PJ      @date  2022/03/29
-************************************************************/
-typedef ZXIC_RTN32 (*ZXIC_SLT_PRE_FN)(ZXIC_UINT32 device_id,ZXIC_UINT32 chip_type,ZXIC_UINT32 *p_chip_id, ZXIC_DOUBLE *p_temp,ZXIC_DOUBLE *p_volt);
-
-/***********************************************************/
-/** 用例执行函数
-* @param   ZXIC_SLT_ALL_CASE_FN   
-* @param   device_id   
-* @param   chip_type  用于区分不同封装类型 
-* @param   p_case_num  返回执行SLT 用例数 
-* @param   p_case_no   返回执行SLT 用例编号列表
-* @param   p_case_result   返回执行SLT 用例对应结果，成功返回值或错误码
-*
-* @return  
-* @remark  无
-* @see     
-* @author  PJ      @date  2022/03/29
-************************************************************/
-typedef ZXIC_RTN32 (*ZXIC_SLT_ALL_CASE_FN)(ZXIC_UINT32 device_id,ZXIC_UINT32 chip_type,ZXIC_UINT32 *p_case_num,ZXIC_UINT32 *p_case_no,ZXIC_UINT32 *p_case_result);
-
-/*SDK回调函数定义*/
-typedef struct zxic_slt_register_fn_t
-{
-    ZXIC_SLT_INIT_FN           zxic_slt_init_fn;         /* 初始化函数 */
-    ZXIC_SLT_PRE_FN            zxic_slt_pre_fn;          /* 预处理函数 */
-    ZXIC_SLT_ALL_CASE_FN       zxic_slt_all_case_fn;     /* 用例执行函数*/
-    
-} ZXIC_SLT_REGISTER_FN_T;
-
-#endif
-
-
-
-#if ZXIC_REAL("fn for sdk")
-/***********************************************************/
-/** 回调功能注册函数，不区分芯片ID，仅注册一次即可，提供给SDK设置
-* @return
-* @remark  无
-* @see
-* @author  PJ      @date  2020/05/03
-************************************************************/
-ZXIC_RTN32 zxic_slt_register_fn_set(ZXIC_SLT_REGISTER_FN_T *pExcCall);
-
-/***********************************************************/
-/** 获取POWER函数
-* @param   pExcCall
-*
-* @return
-* @remark  无
-* @see
-* @author  PJ      @date  2020/05/03
-************************************************************/
-ZXIC_RTN32 zxic_slt_callback_getpower(ZXIC_VOID *pExcCall);
-
-/***********************************************************/
-/** 获取MODI函数
-* @param   pExcCall
-*
-* @return
-* @remark  无
-* @see
-* @author  PJ      @date  2020/05/03
-************************************************************/
-ZXIC_RTN32 zxic_slt_callback_riscv(ZXIC_VOID *pExcCall);
-
-/***********************************************************/
-/** 获PCIE函数
-* @param   pExcCall
-*
-* @return
-* @remark  无
-* @see
-* @author  PJ      @date  2020/05/03
-************************************************************/
-ZXIC_RTN32 zxic_slt_callback_pcie(ZXIC_VOID *pExcCall);
-
-/***********************************************************/
-/** 获取VOLT函数
-* @param   pExcCall
-*
-* @return
-* @remark  无
-* @see
-* @author  PJ      @date  2020/05/03
-************************************************************/
-ZXIC_RTN32 zxic_slt_callback_adjust_volt(ZXIC_VOID *pExcCall);
-
-/***********************************************************/
-/** 获取CLK函数
-* @param   pExcCall
-*
-* @return
-* @remark  无
-* @see
-* @author  PJ      @date  2020/05/03
-************************************************************/
-ZXIC_RTN32 zxic_slt_callback_adjust_clk(ZXIC_VOID *pExcCall);
-
-
-#endif
-
-
-#if ZXIC_REAL("fn for bsp")
-
-/***********************************************************/
-/** 回调功能注册函数，不区分芯片ID，仅注册一次即可，提供给SDK设置
-* @return
-* @remark  无
-* @see
-* @author  PJ      @date  2020/05/03
-************************************************************/
-ZXIC_RTN32 zxic_slt_bsp_register_fn_set(ZXIC_SLT_BSP_REGISTER_FN_T *pExcCall);
-
-
-/***********************************************************/
-/** 设置是否删除log标记,提供给BSP调用
-* @return
-* @remark  无
-* @see
-* @author  PJ      @date  2020/05/03
-************************************************************/
-ZXIC_VOID zxic_slt_log_rm_flag_set(ZXIC_UINT32 log_rm_flag);
-
-
-/***********************************************************/
-/** 执行SDK SLT 所有用例测试,提供给BSP调用
-* @param   dev_id   
-* @param   chip_type   芯片封装类型 
-* @param   p_init_ctrl  详细参见ZXIC_SLT_INIT_CTRL_T说明
-* @param   p_case_para  详细参见ZXIC_SLT_CASE_PARA_T说明
-*
-* @return  
-* @remark  无
-* @see     
-* @author  PJ      @date  2022/03/29
-************************************************************/
-ZXIC_RTN32 zxic_slt_all_case_test(ZXIC_UINT32 dev_id,ZXIC_UINT32 chip_type, ZXIC_SLT_INIT_CTRL_T *p_init_ctrl,ZXIC_SLT_CASE_PARA_T *p_case_para);
-
-#endif
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end __ZXIC_SLT_H__ */
-
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : zxic_slt.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : PJ
+* 完成日期 : 2022/03/26
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#ifndef __ZXIC_SLT_H__
+#define __ZXIC_SLT_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ZXIC_SLT_CASE_PASS (0U)
+#define ZXIC_SLT_CASE_FAILURE (1U)
+
+#define ZXIC_SLT_ERR_INFO_LEN (255U)
+#define ZXIC_SLT_CASE_MAX_NUM (255U)
+#define ZXIC_SLT_DEV_ID_MAX_NUM (4U)
+#define ZXIC_SLT_CHIP_ID_LEN (3U)
+
+/* 封装类型，不同产品含义不同，暂时定义最大支持5个*/
+#define ZXIC_SLT_MAX_ENCAP (5U)
+
+/* BIN_CODE 编码*/
+#define ZXIC_SLT_BIN_CODE_PASS ZXIC_SLT_CASE_PASS
+#define ZXIC_SLT_BIN_CODE_SERDES_FAIL (1U) /* sredes类检测*/
+#define ZXIC_SLT_BIN_CODE_FLOW_FAIL (2U) /* pvt类检测 FLOW通流类*/
+#define ZXIC_SLT_BIN_CODE_RAM_FAIL (3U) /* RAM类检测*/
+#define ZXIC_SLT_BIN_CODE_HBM_DDR_FAIL (4U) /* hbm类检测*/
+#define ZXIC_SLT_BIN_CODE_OTHER_FAIL (5U) /* PLL EFUSE PCIE RISCV */
+#define ZXIC_SLT_BIN_CODE_MIX_FAIL (6U) /* 上述多种类型的混合*/
+
+/* 测试用例全集case_no定义*/
+typedef enum zxic_slt_case_no_e {
+	ZXIC_SLT_CASE_PLL_LOCK_STATUS_CHECK = (0x08U),
+	/* efuse锁定相关测试用例 */
+	ZXIC_SLT_CASE_EFUSE_CHECK = (0x09U),
+
+	/* serdes用例编号范围0x10~0x7f*/
+	/* lifx(LIF0 LIF1 LIF2)接口serdes prbs相关测试用例  0x10~0x2f*/
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_1G = (0x10U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_3G = (0x11U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_5G = (0x12U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_6G = (0x13U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_9G = (0x14U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_10G = (0x15U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_12G = (0x16U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_15G = (0x17U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_20G = (0x18U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_25G = (0x19U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_26G = (0x1aU),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_27G = (0x1bU),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_28G = (0x1cU),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_30G = (0x1dU),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_50G = (0x1fU),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_51G = (0x20U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_53G = (0x21U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_55G = (0x22U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_56G = (0x23U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_57G = (0x24U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_98G = (0x25U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_106G = (0x26U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_111G = (0x27U),
+	ZXIC_SLT_CASE_SERDES_LIFX_PRBS_112G = (0x28U),
+
+	/* lifc接口serdes相关测试用例 0x30~0x37*/
+	ZXIC_SLT_CASE_SERDES_LIFC_PRBS_1G = (0x30U),
+	ZXIC_SLT_CASE_SERDES_LIFC_PRBS_10G = (0x31U),
+	ZXIC_SLT_CASE_SERDES_LIFC_PRBS_25G = (0x32U),
+	ZXIC_SLT_CASE_SERDES_LIFC_PRBS_53G = (0x33U),
+
+	/* lifc eth 接口发包测试相关测试用例 0x38~0x3f*/
+	ZXIC_SLT_CASE_PORT_LIFC_SD_1G = (0x38U),
+	ZXIC_SLT_CASE_PORT_LIFC_SD_10G = (0x39U),
+	ZXIC_SLT_CASE_PORT_LIFC_SD_25G = (0x3aU),
+	ZXIC_SLT_CASE_PORT_LIFC_SD_53G = (0x3bU),
+
+	/* 外部查找的interlaken-la接口*/
+	ZXIC_SLT_CASE_SERDES_INTERLAKEN_LA = (0x3fU),
+
+	/* lif0 eth 接口发包测试相关测试用例 0x40~0x5f*/
+	ZXIC_SLT_CASE_PORT_LIFO_SD_1G = (0x40U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_5G = (0x41U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_10G = (0x42U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_12G = (0x43U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_25G = (0x44U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_26G = (0x45U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_51G = (0x46U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_53G = (0x47U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_106G = (0x48U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_112G = (0x49U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_20G = (0x4AU),
+
+	/* lif0 intlk接口发包测试相关测试用例 0x60~0x6f*/
+	ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_3G = (0x60U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_6G = (0x61U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_10G = (0x62U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_12G = (0x63U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_25G = (0x64U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_28G = (0x65U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_30G = (0x66U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_50G = (0x67U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_51G = (0x68U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_53G = (0x69U),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_56G = (0x6aU),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_106G = (0x6bU),
+	ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_112G = (0x6cU),
+
+	/* 交换侧lif1 FEC测试相关测试用例 0x70~0x7f*/
+	ZXIC_SLT_CASE_SERDES_LIF1_FEC_25G = (0x70U),
+	ZXIC_SLT_CASE_SERDES_LIF1_FEC_26G = (0x71U),
+	ZXIC_SLT_CASE_SERDES_LIF1_FEC_28G = (0x72U),
+	ZXIC_SLT_CASE_SERDES_LIF1_FEC_50G = (0x73U),
+	ZXIC_SLT_CASE_SERDES_LIF1_FEC_53G = (0x74U),
+	ZXIC_SLT_CASE_SERDES_LIF1_FEC_56G = (0x75U),
+	ZXIC_SLT_CASE_SERDES_LIF1_FEC_98G = (0x76U),
+	ZXIC_SLT_CASE_SERDES_LIF1_FEC_106G = (0x77U),
+	ZXIC_SLT_CASE_SERDES_LIF1_FEC_112G = (0x78U),
+
+	/*片内ram用例编号范围0x80~0x87*/
+	/* CPU可读写寄存器测试用例 */
+	ZXIC_SLT_CASE_REG_CPU_W_R = (0x80U),
+	/* CPU可读写ram测试用例 */
+	ZXIC_SLT_CASE_RAM_CPU_W_R = (0x81U),
+	/* RAM表项读写测试(微码)*/
+	ZXIC_SLT_CASE_RAM_MC_W_R = (0x82U),
+	/* RAM表项读写测试 memtest86(微码)*/
+	ZXIC_SLT_CASE_RAM_MC_MEMTEST86 = (0x83U),
+
+	/* HBM/DDR用例编号范围 0x90~0x9f*/
+	/*mbist测试*/
+	ZXIC_SLT_CASE_HBM_DDR_CTRL_BIST = (0x90U),
+	/* HBM/DDR表项CPU读写测试*/
+	ZXIC_SLT_CASE_HBM_DDR_CPU_W_R = (0x91U),
+	/* HBM/DDR表项读写测试(微码)*/
+	ZXIC_SLT_CASE_HBM_DDR_MC_W_R = (0x92U),
+	/* HBM/DDR表项读写测试 memtest86(微码)*/
+	ZXIC_SLT_CASE_HBM_DDR_MC_MEMTEST86 = (0x93U),
+	/* HBM/DDR TM覆盖测试*/
+	ZXIC_SLT_CASE_HBM_DDR_TM_TEST = (0x94U),
+
+	/* 发流测试和全业务PVT测试用例编号范围 0xa0~0xaf*/
+	/* 数据路径测试用例 */
+	ZXIC_SLT_CASE_PKT_FLOW_NOM = (0xA0U),
+	/* OAM发包测试用例 */
+	ZXIC_SLT_CASE_OAM_SEND_PKT = (0xA1U),
+	/* se查表全集测试 */
+	ZXIC_SLT_CASE_PKT_FLOW_SE_FULL = (0xA2U),
+	/* tm全队列测试用例 */
+	ZXIC_SLT_CASE_PKT_FLOW_TM_FULL = (0xA3U),
+	/* LIFC口测试用例 */
+	ZXIC_SLT_CASE_PKT_FLOW_LIFC = (0xA4U),
+
+	/* 芯片PVT 功耗、温度和电压测试用例 */
+	ZXIC_SLT_CASE_PVT_EXCEED_POWER_TEST = (0xA8U),
+	ZXIC_SLT_CASE_PVT_EXCEED_TEM_VOLT_TEST = (0xA9U),
+	ZXIC_SLT_CASE_PVT_EXCEED_HBM_TEMPER_TEST = (0xAaU),
+
+	/* 其他测试用例编号范围0xb0~0xff*/
+	/* 调压测试*/
+	ZXIC_SLT_CASE_VOLT_TEST = (0xB0U),
+	/* 时钟频偏测试 */
+	ZXIC_SLT_CASE_CLK_TEST = (0xB1U),
+
+	/* PCIE压力测试 */
+	ZXIC_SLT_CASE_PCIE_W_R_TEST = (0xB2U),
+	/* 下述两个测试用例必须放在最后执行 */
+	/* PCIE建链测试 */
+	ZXIC_SLT_CASE_PCIE_TEST = (0xB3U),
+	/* RISCV测试用例 */
+	ZXIC_SLT_CASE_RISCV_W_R_TEST = (0xB4U),
+
+	ZXIC_SLT_CASE_MAX,
+} ZXIC_SLT_CASE_NO_E;
+
+#if ZXIC_REAL("ERR_CODE")
+#define ZXIC_SLT_RC_BASE (0x100U)
+
+#define ZXIC_SLT_TEST_CASE_FNC_POINT_NULL (ZXIC_SLT_RC_BASE | 0x1)
+#define ZXIC_SLT_CASE_PLL_LOCK_STATUS_CHECK_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PLL_LOCK_STATUS_CHECK)
+#define ZXIC_SLT_CASE_EFUSE_CHECK_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_EFUSE_CHECK)
+
+/* lifx*/
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_1G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_1G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_3G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_3G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_5G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_5G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_6G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_6G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_9G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_9G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_10G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_10G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_12G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_12G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_15G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_15G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_20G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_20G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_25G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_25G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_26G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_26G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_27G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_27G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_28G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_28G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_30G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_30G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_50G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_50G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_51G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_51G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_53G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_53G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_55G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_55G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_56G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_56G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_57G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_57G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_98G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_98G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_106G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_106G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_111G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_111G)
+#define ZXIC_SLT_CASE_SERDES_LIFX_PRBS_112G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFX_PRBS_112G)
+
+/* lifc*/
+#define ZXIC_SLT_CASE_SERDES_LIFC_PRBS_1G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFC_PRBS_1G)
+#define ZXIC_SLT_CASE_SERDES_LIFC_PRBS_10G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFC_PRBS_10G)
+#define ZXIC_SLT_CASE_SERDES_LIFC_PRBS_25G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFC_PRBS_25G)
+#define ZXIC_SLT_CASE_SERDES_LIFC_PRBS_53G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIFC_PRBS_53G)
+
+/* lifc */
+#define ZXIC_SLT_CASE_PORT_LIFC_SD_1G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFC_SD_1G)
+#define ZXIC_SLT_CASE_PORT_LIFC_SD_10G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFC_SD_10G)
+#define ZXIC_SLT_CASE_PORT_LIFC_SD_25G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFC_SD_25G)
+#define ZXIC_SLT_CASE_PORT_LIFC_SD_53G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFC_SD_53G)
+
+/* lif0 ETH*/
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_1G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_1G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_5G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_5G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_10G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_10G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_12G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_12G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_25G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_25G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_26G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_26G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_51G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_51G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_53G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_53G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_106G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_106G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_112G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_112G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_20G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_20G)
+
+/* lif0 intlk*/
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_3G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_3G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_6G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_6G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_10G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_10G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_12G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_12G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_25G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_25G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_28G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_28G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_30G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_30G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_50G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_50G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_51G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_51G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_53G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_53G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_56G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_56G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_106G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_106G)
+#define ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_112G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PORT_LIFO_SD_ILK_112G)
+
+/* lif1*/
+#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_25G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_25G)
+#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_26G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_26G)
+#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_28G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_28G)
+#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_50G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_50G)
+#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_53G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_53G)
+#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_56G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_56G)
+#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_98G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_98G)
+#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_106G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_106G)
+#define ZXIC_SLT_CASE_SERDES_LIF1_FEC_112G_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_LIF1_FEC_112G)
+
+/* 外部查找的interlaken-la接口*/
+#define ZXIC_SLT_CASE_SERDES_INTELAKEN_LA_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_SERDES_INTELAKEN_LA)
+
+/*片内ram读写测试*/
+#define ZXIC_SLT_CASE_RAM_CPU_W_R_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_RAM_CPU_W_R)
+#define ZXIC_SLT_CASE_REG_CPU_W_R_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_REG_CPU_W_R)
+#define ZXIC_SLT_CASE_RAM_MC_W_R_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_RAM_MC_W_R)
+#define ZXIC_SLT_CASE_RAM_MC_MEMTEST86_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_RAM_MC_MEMTEST86)
+
+/* HBM/DDR */
+#define ZXIC_SLT_CASE_HBM_DDR_CTRL_BIST_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_HBM_DDR_CTRL_BIST)
+#define ZXIC_SLT_CASE_HBM_DDR_MC_W_R_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_HBM_DDR_MC_W_R)
+#define ZXIC_SLT_CASE_HBM_DDR_MC_MEMTEST86_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_HBM_DDR_MC_MEMTEST86)
+#define ZXIC_SLT_CASE_HBM_DDR_CPU_W_R_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_HBM_DDR_CPU_W_R)
+#define ZXIC_SLT_CASE_HBM_DDR_TM_TEST_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_HBM_DDR_TM_TEST)
+
+/* 发流测试和全业务PVT测试*/
+#define ZXIC_SLT_CASE_PKT_FLOW_NOM_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PKT_FLOW_NOM)
+#define ZXIC_SLT_CASE_OAM_SEND_PKT_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_OAM_SEND_PKT)
+#define ZXIC_SLT_CASE_PKT_FLOW_SE_FULL_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PKT_FLOW_SE_FULL)
+#define ZXIC_SLT_CASE_PKT_FLOW_TM_FULL_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PKT_FLOW_TM_FULL)
+#define ZXIC_SLT_CASE_PKT_FLOW_LIFC_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PKT_FLOW_LIFC)
+
+#define ZXIC_SLT_CASE_PVT_EXCEED_POWER_TEST_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PVT_EXCEED_POWER_TEST)
+#define ZXIC_SLT_CASE_PVT_EXCEED_TEM_VOLT_TEST_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PVT_EXCEED_TEM_VOLT_TEST)
+#define ZXIC_SLT_CASE_PVT_EXCEED_HBM_TEMPER_TEST_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PVT_EXCEED_HBM_TEMPER_TEST)
+
+#define ZXIC_SLT_CASE_PCIE_TEST_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PCIE_TEST)
+#define ZXIC_SLT_CASE_PCIE_W_R_TEST_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_PCIE_W_R_TEST)
+#define ZXIC_SLT_CASE_RISCV_W_R_TEST_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_RISCV_W_R_TEST)
+#define ZXIC_SLT_CASE_VOLT_TEST_FAIL \
+	(ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_VOLT_TEST)
+#define ZXIC_SLT_CASE_CLK_TEST_FAIL (ZXIC_SLT_RC_BASE | ZXIC_SLT_CASE_CLK_TEST)
+
+#endif
+
+typedef struct zxic_slt_err_info_mng_t {
+	ZXIC_UINT32 err_code; /*参见ERR_CODE定义*/
+	const ZXIC_CHAR *err_info;
+} ZXIC_SLT_ERR_INFO_MNG_T;
+
+typedef struct zxic_slt_init_ctrl_t {
+	ZXIC_ADDR_T pcie_vir_baddr; /**<  @brief PCIe映射虚拟基地址*/
+	ZXIC_ADDR_T riscv_vir_baddr; /**<  @brief RISCV映射虚拟基地址 */
+	ZXIC_ADDR_T dma_vir_baddr; /**<  @brief DMA映射虚拟地址*/
+	ZXIC_ADDR_T dma_phy_baddr; /**<  @brief DMA内存物理地址*/
+} ZXIC_SLT_INIT_CTRL_T;
+
+typedef struct zxic_slt_case_para_t
+
+{
+	ZXIC_UINT32 chip_id[ZXIC_SLT_CHIP_ID_LEN]; /* 返回对应芯片ID */
+	ZXIC_UINT32 case_num; /* 返回执行SLT 用例数 */
+	ZXIC_UINT32 case_no[ZXIC_SLT_CASE_MAX_NUM]; /* 返回执行SLT 用例编号列表 */
+	ZXIC_UINT32 case_result
+			[ZXIC_SLT_CASE_MAX_NUM]; /* 返回执行SLT 用例对应结果，成功返回值或错误码 */
+	ZXIC_UINT32 bin_code; /* 返回 SLT 执行分BIN码 */
+	ZXIC_DOUBLE temp; /* 返回 SLT 用例测试前初始温度 */
+	ZXIC_DOUBLE volt; /* 返回 SLT 用例测试前核电压 */
+
+} ZXIC_SLT_CASE_PARA_T;
+
+/*case 函数标准定义*/
+typedef ZXIC_RTN32 (*ZXIC_SLT_INST_CASE_FN)(ZXIC_UINT32 device_id);
+
+typedef struct zxic_slt_case_mng_t {
+	const ZXIC_CHAR *case_name; /*用例名称*/
+	ZXIC_UINT32 case_no; /*参见ZXIC_SLT_CASE_NO_E定义*/
+	ZXIC_SLT_INST_CASE_FN inst_case_fn; /*单个case函数指针*/
+} ZXIC_SLT_CASE_MNG_T;
+
+/* 功耗类型定义*/
+typedef enum zxic_slt_power_type_t {
+	ZXIC_SLT_POWER_VCC_SSP4_CORE = (0x0U),
+	ZXIC_SLT_POWER_VCC0V75_SSP4_SERDES_DVDD = (0x1U),
+	ZXIC_SLT_POWER_VCC0V75_SSP4_SERDES_AVDDL = (0x2U),
+	ZXIC_SLT_POWER_VCC1V2_SSP4_SERDES_AVDDH = (0x3U),
+	ZXIC_SLT_POWER_VCC1V2_SSP4_HBM_VDDQ = (0x4U),
+
+	ZXIC_SLT_POWER_VCC0V75_SSP4_AVDD = (0x5U),
+	ZXIC_SLT_POWER_VCC1V2_SSP4_AVDD = (0x6U),
+	ZXIC_SLT_POWER_VCC1V2_SSP4_GPIO_DVDD = (0x7U),
+	ZXIC_SLT_POWER_VCC2V5_SSP4_VPP = (0x8U),
+
+	ZXIC_SLT_POWER_TYPE_MAX,
+
+} ZXIC_SLT_POWER_TYPE_T;
+
+typedef struct zxic_slt_power_t {
+	ZXIC_DOUBLE volt; /* 电压值 */
+	ZXIC_DOUBLE cur; /* 电流值 */
+	ZXIC_UINT32 type; /* 功耗编码，参见ZXIC_SLT_POWER_TYPE_T定义 */
+} ZXIC_SLT_POWER_T;
+
+typedef struct zxic_slt_power_para_t {
+	ZXIC_SLT_POWER_T *p_para;
+	ZXIC_UINT32 num; /* 有效功耗个数 */
+} ZXIC_SLT_POWER_PARA_T;
+
+/* 电压类型定义*/
+typedef enum zxic_slt_volt_type_t {
+	ZXIC_SLT_VOLT_VCC_SSP4_CORE = (0x0U),
+	ZXIC_SLT_VOLT_VCC0V75_SSP4_SERDES_DVDD = (0x1U),
+	ZXIC_SLT_VOLT_VCC0V75_SSP4_SERDES_AVDDL = (0x2U),
+	ZXIC_SLT_VOLT_VCC1V2_SSP4_SERDES_AVDDH = (0x3U),
+	ZXIC_SLT_VOLT_VCC1V2_SSP4_HBM_VDDQ = (0x4U),
+
+	ZXIC_SLT_VOLT_TYPE_MAX,
+
+} ZXIC_SLT_VOLT_TYPE_T;
+
+typedef struct zxic_slt_volt_t {
+	ZXIC_UINT32 percent; /* 调压上下浮动值，百分比*100,例如上调1%，传入数值1*/
+	ZXIC_UINT32 flag; /* 正偏：0   负偏：1 */
+	ZXIC_UINT32 vol_type; /* 电压类型，参见ZXIC_SLT_VOLT_TYPE_T定义 */
+} ZXIC_SLT_VOLT_T;
+
+typedef struct zxic_slt_volt_para_t {
+	ZXIC_SLT_VOLT_T *p_para;
+	ZXIC_UINT32 num; /* 有效调压个数 */
+} ZXIC_SLT_VOLT_PARA_T;
+
+/* 时钟类型定义*/
+typedef enum zxic_slt_clk_type_t {
+	ZXIC_SLT_CLK_AU5327_A = (0x0U), /*SSP4 SOCKET 单板AU5327#1 HOST_100M*/
+	ZXIC_SLT_CLK_AU5327_B =
+			(0x1U), /*SSP4 SOCKET 单板AU5327#1 PLL_SYS_CLK/SERDES 156.25M*/
+	ZXIC_SLT_CLK_AU5327_C =
+			(0x2U), /*SSP4 SOCKET 单板AU5327#1 PLL_LOCAL_CLK  156.25M*/
+	ZXIC_SLT_CLK_AU5327_D = (0x3U), /*SSP4 SOCKET 单板AU5327#1 PLL_TS_CLK 125M*/
+
+	ZXIC_SLT_CLK_TYPE_MAX,
+
+} ZXIC_SLT_CLK_TYPE_T;
+
+typedef struct zxic_slt_clk_t {
+	ZXIC_UINT32
+	value; /* 时钟拉偏值，单位HZ(PPM),1PPM = 1HZ（1MHZ=1000KHZ=1000000HZ）*/
+	ZXIC_UINT32 flag; /* 正偏：0   负偏：1 */
+	ZXIC_UINT32 clk_type; /* 时钟类型，参见ZXIC_SLT_CLK_TYPE_T定义 */
+} ZXIC_SLT_CLK_T;
+
+typedef struct zxic_slt_clk_para_t {
+	ZXIC_SLT_CLK_T *p_para;
+	ZXIC_UINT32 num; /* 有效拉偏时钟个数 */
+} ZXIC_SLT_CLK_PARA_T;
+
+#if ZXIC_REAL("define_for_bsp")
+/***********************************************************/
+/** 功耗获取函数
+     * @param   ZXIC_SLT_CASE_GETPOWER_FN
+     * @param   device_id
+     * @param   p_para
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2022/04/28
+     ************************************************************/
+typedef ZXIC_RTN32 (*ZXIC_SLT_CASE_GETPOWER_FN)(ZXIC_UINT32 device_id,
+												ZXIC_SLT_POWER_PARA_T * p_para);
+
+/***********************************************************/
+/** riscv测试函数
+     * @param   ZXIC_SLT_CASE_RISCV_FN
+     * @param   device_id
+     * @param   reg_addr   寄存器地址
+     * @param   wr_data   写入寄存器的值
+     * @param   rd_data   期望从寄存器中读出的值
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2022/04/28
+     ************************************************************/
+typedef ZXIC_RTN32 (*ZXIC_SLT_CASE_RISCV_FN)(ZXIC_UINT32 device_id,
+											 ZXIC_UINT32 reg_addr,
+											 ZXIC_UINT32 wr_data,
+											 ZXIC_UINT32 rd_data);
+
+/***********************************************************/
+/** PCIE测试函数
+     * @param   ZXIC_SLT_CASE_PCIE_FN
+     * @param   device_id
+     * @param   times  pcie建链测试次数
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2022/04/28
+     ************************************************************/
+typedef ZXIC_RTN32 (*ZXIC_SLT_CASE_PCIE_FN)(ZXIC_UINT32 device_id,
+											ZXIC_UINT32 times);
+
+/***********************************************************/
+/** 调电压函数
+     * @param   ZXIC_SLT_CASE_ADJUST_VOLT_FN
+     * @param   device_id
+     * @param   p_para
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2022/04/28
+     ************************************************************/
+typedef ZXIC_RTN32 (*ZXIC_SLT_CASE_ADJUST_VOLT_FN)(
+		ZXIC_UINT32 device_id, ZXIC_SLT_VOLT_PARA_T *p_para);
+
+/***********************************************************/
+/** 调时钟函数
+     * @param   ZXIC_SLT_CASE_ADJUST_CLK_FN
+     * @param   device_id
+     * @param   p_para
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2022/04/28
+     ************************************************************/
+typedef ZXIC_RTN32 (*ZXIC_SLT_CASE_ADJUST_CLK_FN)(ZXIC_UINT32 device_id,
+												  ZXIC_SLT_CLK_PARA_T *p_para);
+
+/*BSP回调函数定义*/
+typedef struct zxic_slt_bsp_register_fn_t {
+	ZXIC_SLT_CASE_GETPOWER_FN zxic_slt_power_fn;
+	ZXIC_SLT_CASE_RISCV_FN zxic_slt_riscv_fn;
+	ZXIC_SLT_CASE_PCIE_FN zxic_slt_pcie_fn;
+	ZXIC_SLT_CASE_ADJUST_VOLT_FN zxic_slt_volt_fn;
+	ZXIC_SLT_CASE_ADJUST_CLK_FN zxic_slt_clk_fn;
+
+} ZXIC_SLT_BSP_REGISTER_FN_T;
+
+#endif
+
+#if ZXIC_REAL("define_for_sdk")
+/***********************************************************/
+/** 初始化函数
+     * @param   ZXIC_SLT_INIT_FN
+     * @param   device_id
+     * @param   chip_type  用于区分不同封装类型
+     * @param   p_init_ctrl   参见ZXIC_SLT_INIT_CTRL_T定义
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2022/04/22
+     ************************************************************/
+typedef ZXIC_RTN32 (*ZXIC_SLT_INIT_FN)(ZXIC_UINT32 device_id,
+									   ZXIC_UINT32 chip_type,
+									   ZXIC_SLT_INIT_CTRL_T * p_init_ctrl);
+
+/* Chip_ID 组成结构说明：
+    ** Chip_ID = efuse里面的wafer批次号+wafer片号+x坐标+Y坐标组合而成
+    ** wafer批次号: 48bit lot_id5~0
+    ** wafer片号:   5bit  wafer_no
+    ** x坐标:		8bit  x_addr
+    ** Y坐标:		8bit  y_addr
+    ** chip_id2 = lot_id5[7:3]
+    ** chip_id1 = lot_id5[2:0] + lot_id4 + lot_id3 + lot_id2 + lot_id1[7:3]
+    ** chip_id0 = lot_id1[2:0] + lot_id0 + wafer_no[4:0] + x_addr + y_addr*/
+
+/***********************************************************/
+/** 执行测试用例之前的预处理函数,用来获取chip_id,温度，电压信息
+     * @param   ZXIC_SLT_PRE_FN
+     * @param   device_id
+     * @param   chip_type  用于区分不同封装类型
+     * @param   p_chip_id   返回芯片的chip_id信息(参见上述格式说明）
+     * @param   p_temp  返回 SLT 用例测试前初始温度
+     * @param   p_volt  返回 SLT 用例测试前核电压
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2022/03/29
+     ************************************************************/
+typedef ZXIC_RTN32 (*ZXIC_SLT_PRE_FN)(ZXIC_UINT32 device_id,
+									  ZXIC_UINT32 chip_type,
+									  ZXIC_UINT32 *p_chip_id,
+									  ZXIC_DOUBLE *p_temp, ZXIC_DOUBLE *p_volt);
+
+/***********************************************************/
+/** 用例执行函数
+     * @param   ZXIC_SLT_ALL_CASE_FN
+     * @param   device_id
+     * @param   chip_type  用于区分不同封装类型
+     * @param   p_case_num  返回执行SLT 用例数
+     * @param   p_case_no   返回执行SLT 用例编号列表
+     * @param   p_case_result   返回执行SLT 用例对应结果，成功返回值或错误码
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2022/03/29
+     ************************************************************/
+typedef ZXIC_RTN32 (*ZXIC_SLT_ALL_CASE_FN)(ZXIC_UINT32 device_id,
+										   ZXIC_UINT32 chip_type,
+										   ZXIC_UINT32 *p_case_num,
+										   ZXIC_UINT32 *p_case_no,
+										   ZXIC_UINT32 *p_case_result);
+
+/*SDK回调函数定义*/
+typedef struct zxic_slt_register_fn_t {
+	ZXIC_SLT_INIT_FN zxic_slt_init_fn; /* 初始化函数 */
+	ZXIC_SLT_PRE_FN zxic_slt_pre_fn; /* 预处理函数 */
+	ZXIC_SLT_ALL_CASE_FN zxic_slt_all_case_fn; /* 用例执行函数*/
+
+} ZXIC_SLT_REGISTER_FN_T;
+
+#endif
+
+#if ZXIC_REAL("fn for sdk")
+/***********************************************************/
+/** 回调功能注册函数，不区分芯片ID，仅注册一次即可，提供给SDK设置
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2020/05/03
+     ************************************************************/
+ZXIC_RTN32 zxic_slt_register_fn_set(ZXIC_SLT_REGISTER_FN_T * pExcCall);
+
+/***********************************************************/
+/** 获取POWER函数
+     * @param   pExcCall
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2020/05/03
+     ************************************************************/
+ZXIC_RTN32 zxic_slt_callback_getpower(ZXIC_VOID *pExcCall);
+
+/***********************************************************/
+/** 获取MODI函数
+     * @param   pExcCall
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2020/05/03
+     ************************************************************/
+ZXIC_RTN32 zxic_slt_callback_riscv(ZXIC_VOID *pExcCall);
+
+/***********************************************************/
+/** 获PCIE函数
+     * @param   pExcCall
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2020/05/03
+     ************************************************************/
+ZXIC_RTN32 zxic_slt_callback_pcie(ZXIC_VOID *pExcCall);
+
+/***********************************************************/
+/** 获取VOLT函数
+     * @param   pExcCall
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2020/05/03
+     ************************************************************/
+ZXIC_RTN32 zxic_slt_callback_adjust_volt(ZXIC_VOID *pExcCall);
+
+/***********************************************************/
+/** 获取CLK函数
+     * @param   pExcCall
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2020/05/03
+     ************************************************************/
+ZXIC_RTN32 zxic_slt_callback_adjust_clk(ZXIC_VOID *pExcCall);
+
+#endif
+
+#if ZXIC_REAL("fn for bsp")
+
+/***********************************************************/
+/** 回调功能注册函数，不区分芯片ID，仅注册一次即可，提供给SDK设置
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2020/05/03
+     ************************************************************/
+ZXIC_RTN32 zxic_slt_bsp_register_fn_set(ZXIC_SLT_BSP_REGISTER_FN_T * pExcCall);
+
+/***********************************************************/
+/** 设置是否删除log标记,提供给BSP调用
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2020/05/03
+     ************************************************************/
+ZXIC_VOID zxic_slt_log_rm_flag_set(ZXIC_UINT32 log_rm_flag);
+
+/***********************************************************/
+/** 执行SDK SLT 所有用例测试,提供给BSP调用
+     * @param   dev_id
+     * @param   chip_type   芯片封装类型
+     * @param   p_init_ctrl  详细参见ZXIC_SLT_INIT_CTRL_T说明
+     * @param   p_case_para  详细参见ZXIC_SLT_CASE_PARA_T说明
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  PJ      @date  2022/03/29
+     ************************************************************/
+ZXIC_RTN32 zxic_slt_all_case_test(ZXIC_UINT32 dev_id, ZXIC_UINT32 chip_type,
+								  ZXIC_SLT_INIT_CTRL_T *p_init_ctrl,
+								  ZXIC_SLT_CASE_PARA_T *p_case_para);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end __ZXIC_SLT_H__ */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_double_link.c b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_double_link.c
index 9a36d06e4faa7a7742bea20565f0f7f165f9e6fe..f00bc2bcdd1cac4279572c8f182030726de61c46 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_double_link.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_double_link.c
@@ -1,605 +1,541 @@
-/*****************************************************************************
- * 版权所有 (C)2008-2010, 深圳市中兴通讯股份有限公司。
- *
- * 文件名称：    zxic_comm_double_link.c
- * 文件标识：
- * 内容摘要：    双链表实现
- * 其它说明：
- * 当前版本：    V1.00.10
- * 作    者：
- * 完成日期：    2012年2月14日
- * 当前责任人-1：ChenWei188471
- * 当前责任人-2：
- * 历史责任人-3:
- *
- * 修改记录：
- * 修改日期：   版 本 号   修 改 人     修改内容
- 1    20120214               V1.00.10       ChenWei188471  创建
- 2
- *****************************************************************************/
-
-#include "zxic_common.h"
-#include "zxic_comm_double_link.h"
-
-/*当前节点都插在头节点之后,新插入的节点永远在第一个*/
-ZXIC_RTN32 zxic_comm_double_link_insert_1st(D_NODE *p_newnode,D_HEAD *p_head)
-{
-    ZXIC_COMM_CHECK_POINT(p_newnode);
-    ZXIC_COMM_CHECK_POINT(p_head);
-
-    ZXIC_COMM_CHECK_INDEX((p_head->used+1), 1, p_head->maxnum);
-
-    ZXIC_COMM_ASSERT(!(!p_head->p_next&& p_head->p_prev));
-    ZXIC_COMM_ASSERT(!(p_head->p_next && !p_head->p_prev));
-
-    p_newnode->next = p_head->p_next;
-    p_newnode->prev = NULL;/*新节点前驱为NULL*/
-
-    if(p_head->p_next)
-    {
-        p_head->p_next->prev = p_newnode;
-    }
-    else
-    {
-        p_head->p_prev = p_newnode;
-    }
-
-    p_head->p_next = p_newnode;
-    p_head->used++;
-
-
-    return ZXIC_OK;
-}
-
-/*目的是配合sort函数实现相同节点无需重复写入*/
-ZXIC_RTN32 zxic_comm_double_link_insert_cmp(D_HEAD *p_head, void* cmp_data, ZXIC_UINT32 *is_same)
-{
-    D_NODE *p_dn = 0;
-
-    *is_same = 0;
-
-    p_dn = p_head->p_next;
-
-    while(p_dn)
-    {
-        if(*(ZXIC_UINT32*)cmp_data == *(ZXIC_UINT32*)p_dn->data)
-        {
-            *is_same = 1;
-
-            break;
-        }
-
-        p_dn = p_dn->next;
-    }
-
-    return ZXIC_OK;
-}
-
-ZXIC_RTN32 zxic_comm_double_link_insert_merge(D_NODE *p_newnode,D_HEAD *p_head,ZXIC_UINT32 is_head)
-{
-    D_NODE *p_dn = 0;
-    ZXIC_UINT32  is_same = 0;
-
-    p_dn = p_head->p_next;
-
-    while(p_dn)
-    {
-        if(p_dn->data == p_newnode->data)
-        {
-            is_same = 1;
-            break;
-        }
-
-        p_dn = p_dn->next;
-    }
-
-    if(! is_same )
-    {
-        if (is_head)
-        {
-            return zxic_comm_double_link_insert_1st(p_newnode, p_head);
-        }
-        else
-        {
-            return zxic_comm_double_link_insert_last(p_newnode, p_head);
-        }
-    }
-
-    return ZXIC_OK;
-
-}
-
-/* 在OLD节点之后插入 */
-ZXIC_RTN32  zxic_comm_double_link_insert_aft(D_NODE *p_newnode,D_NODE *p_oldnode,D_HEAD*p_head)
-{
-
-
-    ZXIC_COMM_CHECK_POINT(p_newnode);
-    ZXIC_COMM_CHECK_POINT(p_oldnode);
-    ZXIC_COMM_CHECK_POINT(p_head);
-
-    ZXIC_COMM_CHECK_INDEX((p_head->used+1), 1, p_head->maxnum);
-
-    ZXIC_COMM_ASSERT(!(!p_head->p_next&& p_head->p_prev));
-    ZXIC_COMM_ASSERT(!(p_head->p_next && !p_head->p_prev));
-
-    p_newnode->next = p_oldnode->next;
-    p_newnode->prev = p_oldnode;
-
-    if(p_oldnode->next)
-    {
-        p_oldnode->next->prev = p_newnode;
-    }
-    else
-    {
-        p_head->p_prev = p_newnode;
-    }
-
-    p_oldnode->next = p_newnode;
-    p_head->used++;
-
-    return ZXIC_OK;
-}
-
-/* 在OLD节点前插入 */
-ZXIC_RTN32 zxic_comm_double_link_insert_pre(D_NODE *p_newnode,D_NODE *p_oldnode,D_HEAD*p_head)
-{
-
-    ZXIC_COMM_CHECK_POINT(p_newnode);
-    ZXIC_COMM_CHECK_POINT(p_oldnode);
-    ZXIC_COMM_CHECK_POINT(p_head);
-
-    ZXIC_COMM_CHECK_INDEX((p_head->used+1), 1, p_head->maxnum);
-
-    ZXIC_COMM_ASSERT(!(!p_head->p_next&& p_head->p_prev));
-    ZXIC_COMM_ASSERT(!(p_head->p_next && !p_head->p_prev));
-
-    p_newnode->next = p_oldnode;
-    p_newnode->prev = p_oldnode->prev;
-
-    if(p_oldnode->prev)
-    {
-        p_oldnode->prev->next = p_newnode;
-    }
-    else
-    {
-        p_head->p_next = p_newnode;
-    }
-
-    p_oldnode->prev = p_newnode;
-    p_head->used++;
-
-    return ZXIC_OK;
-}
-ZXIC_RTN32 zxic_comm_double_link_insert_last(D_NODE *p_newnode,D_HEAD* p_head)
-{
-    D_NODE *p_dnode = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_newnode);
-    ZXIC_COMM_CHECK_POINT(p_head);
-
-    ZXIC_COMM_CHECK_INDEX((p_head->used+1), 1, p_head->maxnum);
-
-    ZXIC_COMM_ASSERT(!(!p_head->p_next&& p_head->p_prev));
-    ZXIC_COMM_ASSERT(!(p_head->p_next && !p_head->p_prev));
-
-
-    p_dnode = p_head->p_prev;
-
-
-    if(!p_dnode)
-    {
-        p_head->p_next  = p_newnode;
-        p_head->p_prev  = p_newnode;
-        p_newnode->next = NULL;
-        p_newnode->prev = NULL;
-    }
-    else
-    {
-        p_newnode->prev = p_dnode;
-        p_newnode->next = NULL;
-        p_head->p_prev  = p_newnode;
-        p_dnode->next   = p_newnode;
-    }
-
-    p_head->used++;
-
-    return ZXIC_OK;
-}
-ZXIC_RTN32  zxic_comm_double_link_del(D_NODE *delnode,D_HEAD *p_head)
-{
-    D_NODE *next = NULL;
-    D_NODE *pre  = NULL;
-
-    ZXIC_COMM_CHECK_POINT(delnode);
-    ZXIC_COMM_CHECK_POINT(p_head);
-
-    ZXIC_COMM_CHECK_INDEX(p_head->used, 1, p_head->maxnum);
-
-    next = delnode->next;
-    pre  = delnode->prev;
-
-    if(next)
-    {
-        next->prev = delnode->prev;
-    }
-    else
-    {
-        p_head->p_prev= delnode->prev;
-    }
-
-    if(pre)
-    {
-        pre->next = delnode->next;
-    }
-    else
-    {
-        p_head->p_next = delnode->next;
-    }
-
-    p_head->used--;
-    delnode->next = NULL;
-    delnode->prev = NULL;
-    return ZXIC_OK;
-}
-
-
-ZXIC_RTN32 zxic_comm_double_link_init(ZXIC_UINT32 elmemtnum,D_HEAD *p_head)
-{
-    ZXIC_UINT32 err_code = 0;
-
-
-    ZXIC_COMM_CHECK_POINT(p_head);
-
-    if(elmemtnum == 0 )
-    {
-        err_code = ZXIC_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR;
-        ZXIC_COMM_TRACE_ERROR("\nError:[0x%x] zxic_doule_link_init Element Num Err !",err_code);
-        return err_code;
-    }
-
-    p_head->maxnum   = elmemtnum;
-    p_head->used     = 0;
-    p_head->p_next   = NULL;
-    p_head->p_prev   = NULL;
-
-    return ZXIC_OK;
-}
-
-ZXIC_RTN32 zxic_comm_dlink_release(D_HEAD *p_head,fun_free fun)
-{
-    ZXIC_UINT32 rc = 0;
-    D_NODE *p_node = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_head);
-
-    while(p_head->used)
-    {
-        p_node = p_head->p_next;
-
-        if(NULL != fun)
-        {
-            rc = fun(p_node->data);
-            ZXIC_COMM_CHECK_RC(rc, "fun");
-        }
-
-        rc = zxic_comm_double_link_del(p_node,p_head);
-        ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_del");
-
-        ZXIC_COMM_FREE(p_node);
-    }
-
-    return ZXIC_OK;
-}
-/*connetc the s_list to d_list */
-
-ZXIC_RTN32 zxic_comm_double_link_merge_list(D_HEAD *d_list,D_HEAD *s_list)
-{
-    if(d_list->p_prev)
-    {
-        d_list->p_prev->next  = s_list->p_next;
-    }
-    else
-    {
-        ZXIC_COMM_ASSERT(!d_list->p_next);
-        d_list->p_next = s_list->p_next;
-    }
-
-    if(s_list->p_next)
-    {
-        ZXIC_COMM_ASSERT(s_list->p_prev);
-        s_list->p_next->prev = d_list->p_prev;
-        d_list->p_prev       = s_list->p_prev;
-    }
-
-    d_list->used         += s_list->used;
-
-    return ZXIC_OK;
-}
-/*********************************************************************
- * 函数名称：zxic_comm_double_link_insert_sort
- * 功能描述:
- * 函数功能简介
- *            插入排序，
- * 输入参数：
- * 输出参数：
- * 返 回 值：ZXIC_RTN32
- * 全局变量：
- * 注    释：
-============================================================
- * 修改记录:
- * 修改日期      版本号      修改人   修改内容
-============================================================
- * 2012-03-19             jiangwenming
-
- ******************************************************************/
-ZXIC_RTN32 zxic_comm_double_link_insert_sort(D_NODE *p_newnode,D_HEAD *p_head,CMP_FUNC cmp_fuc,void* cmp_data)
-{
-    D_NODE*    pre_node = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_head);
-    ZXIC_COMM_CHECK_POINT(p_newnode);
-
-    if(NULL == cmp_fuc )
-    {
-        cmp_fuc = zxic_comm_double_link_default_cmp_fuc;
-    }
-
-    ZXIC_COMM_CHECK_INDEX((p_head->used+1), 1, p_head->maxnum);
-
-    /*此时表中的数据，已经排序了，再插入时，只需从表头开始比较，然后插入适当位置*/
-    if( 0 == p_head->used )
-    {
-        return zxic_comm_double_link_insert_1st(p_newnode,p_head);
-    }
-    else
-    {
-        pre_node = p_head->p_next;
-
-        while(NULL!=pre_node)
-        {
-            /*新节点的键值小于等于当前的键值*/
-            if(cmp_fuc(p_newnode,pre_node,cmp_data) <= 0)
-            {
-                 return zxic_comm_double_link_insert_pre(p_newnode,pre_node,p_head);
-            }
-            else
-            {
-                pre_node = pre_node->next;
-            }
-        }
-
-        /*循环结束后，说明插入的节点大于链表中的所有节点，需要在尾部插入*/
-        return zxic_comm_double_link_insert_last(p_newnode,p_head);
-    }
-}
-
-
-/*********************************************************************
- * 函数名称：zxic_comm_double_link_del_pos
- * 功能描述:
- * 函数功能简介
- *           根据node中指定的信息删除节点
- * 输入参数：
- * 输出参数：
- * 返 回 值：ZXIC_RTN32
- * 全局变量：
- * 注    释： 根据指定的信息，可能会删除多个
-============================================================
- * 修改记录:
- * 修改日期      版本号      修改人   修改内容
-============================================================
- * 2020-11-11            徐晨曦
-
- ******************************************************************/
-ZXIC_RTN32 zxic_comm_double_link_del_by_info(D_HEAD *p_head, void* cmp_data, CMP_FUNC cmp_fuc, ZXIC_UINT32 *p_deled_num)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 is_same = 0;
-
-    D_NODE *p;
-    D_NODE *p_cur_node = ZXIC_NULL;
-
-    if(NULL == cmp_fuc )
-    {
-        cmp_fuc = zxic_comm_double_link_default_cmp_fuc;
-    }
-
-    p = p_head->p_next;
-
-    while(p)
-    {
-        /*新节点的键值等于当前的键值*/
-        if(cmp_fuc(cmp_data, p,cmp_data) == 0)
-        {
-            rc = zxic_comm_double_link_del(p, p_head);
-            ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_del");
-
-            p_cur_node = p;
-            p = p->next;
-
-            ZXIC_COMM_FREE(p_cur_node);
-            is_same ++;
-            continue;
-        }
-
-        p = p->next;
-    }
-
-    if(0 == is_same)
-    {
-        return ZXIC_ERR;
-    }
-
-    *p_deled_num = is_same;
-
-    ZXIC_COMM_TRACE_DEBUG(" DOUBLE LINK DEL NUM %d \n", is_same);
-
-    return ZXIC_OK;
-}
-
-/*********************************************************************
- * 函数名称：zxic_comm_double_link_del_pos
- * 功能描述:
- * 函数功能简介
- *            删除指定位置的数据
- * 输入参数：
- * 输出参数：
- * 返 回 值：ZXIC_RTN32
- * 全局变量：
- * 注    释：
-============================================================
- * 修改记录:
- * 修改日期      版本号      修改人   修改内容
-============================================================
- * 2012-03-19             jiangwenming
-
- ******************************************************************/
-ZXIC_RTN32 zxic_comm_double_link_del_pos(D_HEAD *p_head,void* cmp_data,fun_free fun)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 is_same = 0;
-
-    D_NODE *p;
-
-    p = p_head->p_next;
-
-    while(p)
-    {
-        if(*(ZXIC_UINT32*)cmp_data == *(ZXIC_UINT32*)p->data)
-        {
-            is_same = 1;
-
-            break;
-        }
-
-        p = p->next;
-    }
-
-    if(is_same)
-    {
-        rc = zxic_comm_double_link_del(p, p_head);
-        ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_del");
-
-        if(NULL != fun)
-        {
-            rc = fun(p->data);
-            ZXIC_COMM_CHECK_RC(rc, "fun");
-        }
-
-        ZXIC_COMM_FREE(p);
-    }
-
-    return ZXIC_OK;
-}
-
-/*********************************************************************
- * 函数名称：zxic_comm_double_link_swap
- * 功能描述:
- * 函数功能简介
- *            交换链表中的两个节点
- * 输入参数：
- * 输出参数：
- * 返 回 值：ZXIC_RTN32
- * 全局变量：
- * 注    释：
-============================================================
- * 修改记录:
- * 修改日期      版本号      修改人   修改内容
-============================================================
- * 2012-03-19             jiangwenming
-
- ******************************************************************/
-ZXIC_RTN32 zxic_comm_double_link_print(D_HEAD *p_head)
-{
-
-    D_NODE *p_pre   = NULL;
-    D_NODE *p_next  = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_head);
-    /*正向打印*/
-    p_next = p_head->p_next;
-    ZXIC_COMM_PRINT("*************sequ order***********\n");
-
-    while(p_next)
-    {
-        ZXIC_COMM_PRINT("==>%d",*(ZXIC_UINT32*)(p_next->data));
-        p_next=p_next->next;
-    }
-
-    /*反向打印*/
-    ZXIC_COMM_PRINT("\n\n*************reverve order***********\n");
-    p_pre=p_head->p_prev;
-
-    while(p_pre != NULL)
-    {
-        ZXIC_COMM_PRINT("==>%d",*(ZXIC_UINT32*)(p_pre->data));
-        p_pre   = p_pre->prev;
-    }
-
-    return ZXIC_OK;
-
-}
-
-ZXIC_SINT32 zxic_comm_double_link_default_cmp_fuc(D_NODE* p_data1,D_NODE* p_data2,void* p_data)
-{
-    ZXIC_UINT32 data1= *(ZXIC_UINT32*)p_data1->data;
-    ZXIC_UINT32 data2= *(ZXIC_UINT32*)p_data2->data;
-
-    if(data1>data2)
-    {
-        return 1;
-    }
-    else if(data1==data2)
-    {
-        return 0;
-    }
-    else
-    {
-        return -1;
-    }
-}
-
-ZXIC_RTN32 zxic_comm_double_link_del_by_data(D_HEAD *p_head,ZXIC_VOID* cmp_data,fun_free fun)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 is_same = 0;
-
-    D_NODE *p;
-
-    p = p_head->p_next;
-
-    while(p)
-    {
-        if(cmp_data == p->data)
-        {
-            is_same = 1;
-
-            break;
-        }
-        p = p->next;
-    }
-
-    if(is_same)
-    {
-        rc = zxic_comm_double_link_del(p,p_head);
-        ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_del");
-        if(NULL != fun)
-        {
-            rc = fun(p->data);
-            ZXIC_COMM_CHECK_RC(rc, "fun");
-        }
-
-        ZXIC_COMM_FREE(p);
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_ERROR("\nError:data not exist. FUNCTION : %s!\n", __FUNCTION__);
-    }
-
-    return ZXIC_OK;
-}
-
-
-
-
+/*****************************************************************************
+ * 版权所有 (C)2008-2010, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：    zxic_comm_double_link.c
+ * 文件标识：
+ * 内容摘要：    双链表实现
+ * 其它说明：
+ * 当前版本：    V1.00.10
+ * 作    者：
+ * 完成日期：    2012年2月14日
+ * 当前责任人-1：ChenWei188471
+ * 当前责任人-2：
+ * 历史责任人-3:
+ *
+ * 修改记录：
+ * 修改日期：   版 本 号   修 改 人     修改内容
+ 1    20120214               V1.00.10       ChenWei188471  创建
+ 2
+ *****************************************************************************/
+
+#include "zxic_common.h"
+#include "zxic_comm_double_link.h"
+
+/*当前节点都插在头节点之后,新插入的节点永远在第一个*/
+ZXIC_RTN32 zxic_comm_double_link_insert_1st(D_NODE *p_newnode, D_HEAD *p_head)
+{
+	ZXIC_COMM_CHECK_POINT(p_newnode);
+	ZXIC_COMM_CHECK_POINT(p_head);
+
+	ZXIC_COMM_CHECK_INDEX((p_head->used + 1), 1, p_head->maxnum);
+
+	ZXIC_COMM_ASSERT(!(!p_head->p_next && p_head->p_prev));
+	ZXIC_COMM_ASSERT(!(p_head->p_next && !p_head->p_prev));
+
+	p_newnode->next = p_head->p_next;
+	p_newnode->prev = NULL; /*新节点前驱为NULL*/
+
+	if (p_head->p_next) {
+		p_head->p_next->prev = p_newnode;
+	} else {
+		p_head->p_prev = p_newnode;
+	}
+
+	p_head->p_next = p_newnode;
+	p_head->used++;
+
+	return ZXIC_OK;
+}
+
+/*目的是配合sort函数实现相同节点无需重复写入*/
+ZXIC_RTN32 zxic_comm_double_link_insert_cmp(D_HEAD *p_head, void *cmp_data,
+											ZXIC_UINT32 *is_same)
+{
+	D_NODE *p_dn = 0;
+
+	*is_same = 0;
+
+	p_dn = p_head->p_next;
+
+	while (p_dn) {
+		if (*(ZXIC_UINT32 *)cmp_data == *(ZXIC_UINT32 *)p_dn->data) {
+			*is_same = 1;
+
+			break;
+		}
+
+		p_dn = p_dn->next;
+	}
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_double_link_insert_merge(D_NODE *p_newnode, D_HEAD *p_head,
+											  ZXIC_UINT32 is_head)
+{
+	D_NODE *p_dn = 0;
+	ZXIC_UINT32 is_same = 0;
+
+	p_dn = p_head->p_next;
+
+	while (p_dn) {
+		if (p_dn->data == p_newnode->data) {
+			is_same = 1;
+			break;
+		}
+
+		p_dn = p_dn->next;
+	}
+
+	if (!is_same) {
+		if (is_head) {
+			return zxic_comm_double_link_insert_1st(p_newnode, p_head);
+		} else {
+			return zxic_comm_double_link_insert_last(p_newnode, p_head);
+		}
+	}
+
+	return ZXIC_OK;
+}
+
+/* 在OLD节点之后插入 */
+ZXIC_RTN32 zxic_comm_double_link_insert_aft(D_NODE *p_newnode,
+											D_NODE *p_oldnode, D_HEAD *p_head)
+{
+	ZXIC_COMM_CHECK_POINT(p_newnode);
+	ZXIC_COMM_CHECK_POINT(p_oldnode);
+	ZXIC_COMM_CHECK_POINT(p_head);
+
+	ZXIC_COMM_CHECK_INDEX((p_head->used + 1), 1, p_head->maxnum);
+
+	ZXIC_COMM_ASSERT(!(!p_head->p_next && p_head->p_prev));
+	ZXIC_COMM_ASSERT(!(p_head->p_next && !p_head->p_prev));
+
+	p_newnode->next = p_oldnode->next;
+	p_newnode->prev = p_oldnode;
+
+	if (p_oldnode->next) {
+		p_oldnode->next->prev = p_newnode;
+	} else {
+		p_head->p_prev = p_newnode;
+	}
+
+	p_oldnode->next = p_newnode;
+	p_head->used++;
+
+	return ZXIC_OK;
+}
+
+/* 在OLD节点前插入 */
+ZXIC_RTN32 zxic_comm_double_link_insert_pre(D_NODE *p_newnode,
+											D_NODE *p_oldnode, D_HEAD *p_head)
+{
+	ZXIC_COMM_CHECK_POINT(p_newnode);
+	ZXIC_COMM_CHECK_POINT(p_oldnode);
+	ZXIC_COMM_CHECK_POINT(p_head);
+
+	ZXIC_COMM_CHECK_INDEX((p_head->used + 1), 1, p_head->maxnum);
+
+	ZXIC_COMM_ASSERT(!(!p_head->p_next && p_head->p_prev));
+	ZXIC_COMM_ASSERT(!(p_head->p_next && !p_head->p_prev));
+
+	p_newnode->next = p_oldnode;
+	p_newnode->prev = p_oldnode->prev;
+
+	if (p_oldnode->prev) {
+		p_oldnode->prev->next = p_newnode;
+	} else {
+		p_head->p_next = p_newnode;
+	}
+
+	p_oldnode->prev = p_newnode;
+	p_head->used++;
+
+	return ZXIC_OK;
+}
+ZXIC_RTN32 zxic_comm_double_link_insert_last(D_NODE *p_newnode, D_HEAD *p_head)
+{
+	D_NODE *p_dnode = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_newnode);
+	ZXIC_COMM_CHECK_POINT(p_head);
+
+	ZXIC_COMM_CHECK_INDEX((p_head->used + 1), 1, p_head->maxnum);
+
+	ZXIC_COMM_ASSERT(!(!p_head->p_next && p_head->p_prev));
+	ZXIC_COMM_ASSERT(!(p_head->p_next && !p_head->p_prev));
+
+	p_dnode = p_head->p_prev;
+
+	if (!p_dnode) {
+		p_head->p_next = p_newnode;
+		p_head->p_prev = p_newnode;
+		p_newnode->next = NULL;
+		p_newnode->prev = NULL;
+	} else {
+		p_newnode->prev = p_dnode;
+		p_newnode->next = NULL;
+		p_head->p_prev = p_newnode;
+		p_dnode->next = p_newnode;
+	}
+
+	p_head->used++;
+
+	return ZXIC_OK;
+}
+ZXIC_RTN32 zxic_comm_double_link_del(D_NODE *delnode, D_HEAD *p_head)
+{
+	D_NODE *next = NULL;
+	D_NODE *pre = NULL;
+
+	ZXIC_COMM_CHECK_POINT(delnode);
+	ZXIC_COMM_CHECK_POINT(p_head);
+
+	ZXIC_COMM_CHECK_INDEX(p_head->used, 1, p_head->maxnum);
+
+	next = delnode->next;
+	pre = delnode->prev;
+
+	if (next) {
+		next->prev = delnode->prev;
+	} else {
+		p_head->p_prev = delnode->prev;
+	}
+
+	if (pre) {
+		pre->next = delnode->next;
+	} else {
+		p_head->p_next = delnode->next;
+	}
+
+	p_head->used--;
+	delnode->next = NULL;
+	delnode->prev = NULL;
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_double_link_init(ZXIC_UINT32 elmemtnum, D_HEAD *p_head)
+{
+	ZXIC_UINT32 err_code = 0;
+
+	ZXIC_COMM_CHECK_POINT(p_head);
+
+	if (elmemtnum == 0) {
+		err_code = ZXIC_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR;
+		ZXIC_COMM_TRACE_ERROR(
+				"\nError:[0x%x] zxic_doule_link_init Element Num Err !",
+				err_code);
+		return err_code;
+	}
+
+	p_head->maxnum = elmemtnum;
+	p_head->used = 0;
+	p_head->p_next = NULL;
+	p_head->p_prev = NULL;
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_dlink_release(D_HEAD *p_head, fun_free fun)
+{
+	ZXIC_UINT32 rc = 0;
+	D_NODE *p_node = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_head);
+
+	while (p_head->used) {
+		p_node = p_head->p_next;
+
+		if (NULL != fun) {
+			rc = fun(p_node->data);
+			ZXIC_COMM_CHECK_RC(rc, "fun");
+		}
+
+		rc = zxic_comm_double_link_del(p_node, p_head);
+		ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_del");
+
+		ZXIC_COMM_FREE(p_node);
+	}
+
+	return ZXIC_OK;
+}
+/*connetc the s_list to d_list */
+
+ZXIC_RTN32 zxic_comm_double_link_merge_list(D_HEAD *d_list, D_HEAD *s_list)
+{
+	if (d_list->p_prev) {
+		d_list->p_prev->next = s_list->p_next;
+	} else {
+		ZXIC_COMM_ASSERT(!d_list->p_next);
+		d_list->p_next = s_list->p_next;
+	}
+
+	if (s_list->p_next) {
+		ZXIC_COMM_ASSERT(s_list->p_prev);
+		s_list->p_next->prev = d_list->p_prev;
+		d_list->p_prev = s_list->p_prev;
+	}
+
+	d_list->used += s_list->used;
+
+	return ZXIC_OK;
+}
+/*********************************************************************
+ * 函数名称：zxic_comm_double_link_insert_sort
+ * 功能描述:
+ * 函数功能简介
+ *            插入排序，
+ * 输入参数：
+ * 输出参数：
+ * 返 回 值：ZXIC_RTN32
+ * 全局变量：
+ * 注    释：
+============================================================
+ * 修改记录:
+ * 修改日期      版本号      修改人   修改内容
+============================================================
+ * 2012-03-19             jiangwenming
+
+ ******************************************************************/
+ZXIC_RTN32 zxic_comm_double_link_insert_sort(D_NODE *p_newnode, D_HEAD *p_head,
+											 CMP_FUNC cmp_fuc, void *cmp_data)
+{
+	D_NODE *pre_node = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_head);
+	ZXIC_COMM_CHECK_POINT(p_newnode);
+
+	if (NULL == cmp_fuc) {
+		cmp_fuc = zxic_comm_double_link_default_cmp_fuc;
+	}
+
+	ZXIC_COMM_CHECK_INDEX((p_head->used + 1), 1, p_head->maxnum);
+
+	/*此时表中的数据，已经排序了，再插入时，只需从表头开始比较，然后插入适当位置*/
+	if (0 == p_head->used) {
+		return zxic_comm_double_link_insert_1st(p_newnode, p_head);
+	} else {
+		pre_node = p_head->p_next;
+
+		while (NULL != pre_node) {
+			/*新节点的键值小于等于当前的键值*/
+			if (cmp_fuc(p_newnode, pre_node, cmp_data) <= 0) {
+				return zxic_comm_double_link_insert_pre(p_newnode, pre_node,
+														p_head);
+			} else {
+				pre_node = pre_node->next;
+			}
+		}
+
+		/*循环结束后，说明插入的节点大于链表中的所有节点，需要在尾部插入*/
+		return zxic_comm_double_link_insert_last(p_newnode, p_head);
+	}
+}
+
+/*********************************************************************
+ * 函数名称：zxic_comm_double_link_del_pos
+ * 功能描述:
+ * 函数功能简介
+ *           根据node中指定的信息删除节点
+ * 输入参数：
+ * 输出参数：
+ * 返 回 值：ZXIC_RTN32
+ * 全局变量：
+ * 注    释： 根据指定的信息，可能会删除多个
+============================================================
+ * 修改记录:
+ * 修改日期      版本号      修改人   修改内容
+============================================================
+ * 2020-11-11            徐晨曦
+
+ ******************************************************************/
+ZXIC_RTN32 zxic_comm_double_link_del_by_info(D_HEAD *p_head, void *cmp_data,
+											 CMP_FUNC cmp_fuc,
+											 ZXIC_UINT32 *p_deled_num)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 is_same = 0;
+
+	D_NODE *p;
+	D_NODE *p_cur_node = ZXIC_NULL;
+
+	if (NULL == cmp_fuc) {
+		cmp_fuc = zxic_comm_double_link_default_cmp_fuc;
+	}
+
+	p = p_head->p_next;
+
+	while (p) {
+		/*新节点的键值等于当前的键值*/
+		if (cmp_fuc(cmp_data, p, cmp_data) == 0) {
+			rc = zxic_comm_double_link_del(p, p_head);
+			ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_del");
+
+			p_cur_node = p;
+			p = p->next;
+
+			ZXIC_COMM_FREE(p_cur_node);
+			is_same++;
+			continue;
+		}
+
+		p = p->next;
+	}
+
+	if (0 == is_same) {
+		return ZXIC_ERR;
+	}
+
+	*p_deled_num = is_same;
+
+	ZXIC_COMM_TRACE_DEBUG(" DOUBLE LINK DEL NUM %d \n", is_same);
+
+	return ZXIC_OK;
+}
+
+/*********************************************************************
+ * 函数名称：zxic_comm_double_link_del_pos
+ * 功能描述:
+ * 函数功能简介
+ *            删除指定位置的数据
+ * 输入参数：
+ * 输出参数：
+ * 返 回 值：ZXIC_RTN32
+ * 全局变量：
+ * 注    释：
+============================================================
+ * 修改记录:
+ * 修改日期      版本号      修改人   修改内容
+============================================================
+ * 2012-03-19             jiangwenming
+
+ ******************************************************************/
+ZXIC_RTN32 zxic_comm_double_link_del_pos(D_HEAD *p_head, void *cmp_data,
+										 fun_free fun)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 is_same = 0;
+
+	D_NODE *p;
+
+	p = p_head->p_next;
+
+	while (p) {
+		if (*(ZXIC_UINT32 *)cmp_data == *(ZXIC_UINT32 *)p->data) {
+			is_same = 1;
+
+			break;
+		}
+
+		p = p->next;
+	}
+
+	if (is_same) {
+		rc = zxic_comm_double_link_del(p, p_head);
+		ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_del");
+
+		if (NULL != fun) {
+			rc = fun(p->data);
+			ZXIC_COMM_CHECK_RC(rc, "fun");
+		}
+
+		ZXIC_COMM_FREE(p);
+	}
+
+	return ZXIC_OK;
+}
+
+/*********************************************************************
+ * 函数名称：zxic_comm_double_link_swap
+ * 功能描述:
+ * 函数功能简介
+ *            交换链表中的两个节点
+ * 输入参数：
+ * 输出参数：
+ * 返 回 值：ZXIC_RTN32
+ * 全局变量：
+ * 注    释：
+============================================================
+ * 修改记录:
+ * 修改日期      版本号      修改人   修改内容
+============================================================
+ * 2012-03-19             jiangwenming
+
+ ******************************************************************/
+ZXIC_RTN32 zxic_comm_double_link_print(D_HEAD *p_head)
+{
+	D_NODE *p_pre = NULL;
+	D_NODE *p_next = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_head);
+	/*正向打印*/
+	p_next = p_head->p_next;
+	ZXIC_COMM_PRINT("*************sequ order***********\n");
+
+	while (p_next) {
+		ZXIC_COMM_PRINT("==>%d", *(ZXIC_UINT32 *)(p_next->data));
+		p_next = p_next->next;
+	}
+
+	/*反向打印*/
+	ZXIC_COMM_PRINT("\n\n*************reverve order***********\n");
+	p_pre = p_head->p_prev;
+
+	while (p_pre != NULL) {
+		ZXIC_COMM_PRINT("==>%d", *(ZXIC_UINT32 *)(p_pre->data));
+		p_pre = p_pre->prev;
+	}
+
+	return ZXIC_OK;
+}
+
+ZXIC_SINT32 zxic_comm_double_link_default_cmp_fuc(D_NODE *p_data1,
+												  D_NODE *p_data2, void *p_data)
+{
+	ZXIC_UINT32 data1 = *(ZXIC_UINT32 *)p_data1->data;
+	ZXIC_UINT32 data2 = *(ZXIC_UINT32 *)p_data2->data;
+
+	if (data1 > data2) {
+		return 1;
+	} else if (data1 == data2) {
+		return 0;
+	} else {
+		return -1;
+	}
+}
+
+ZXIC_RTN32 zxic_comm_double_link_del_by_data(D_HEAD *p_head,
+											 ZXIC_VOID *cmp_data, fun_free fun)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 is_same = 0;
+
+	D_NODE *p;
+
+	p = p_head->p_next;
+
+	while (p) {
+		if (cmp_data == p->data) {
+			is_same = 1;
+
+			break;
+		}
+		p = p->next;
+	}
+
+	if (is_same) {
+		rc = zxic_comm_double_link_del(p, p_head);
+		ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_del");
+		if (NULL != fun) {
+			rc = fun(p->data);
+			ZXIC_COMM_CHECK_RC(rc, "fun");
+		}
+
+		ZXIC_COMM_FREE(p);
+	} else {
+		ZXIC_COMM_TRACE_ERROR("\nError:data not exist. FUNCTION : %s!\n",
+							  __FUNCTION__);
+	}
+
+	return ZXIC_OK;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_index_fill.c b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_index_fill.c
index c3d1da4fce5f2456ed128810966b352a3709a471..5d6c25ae952cca7c720a518ade2630fdbbdc9e57 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_index_fill.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_index_fill.c
@@ -1,420 +1,724 @@
-/*****************************************************************************
- * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。
- * 
- * 文件名称：   zxic_index_fill.c
- * 文件标识：    
- * 内容摘要：   索引空位填充源代码头文件
- * 其它说明：   
- * 当前版本：    
- * 作    者：    ChenWei10088471
- * 完成日期：   
- * 当前责任人-1：
- * 当前责任人-2：
- *
- * DEPARTMENT       : ASIC_FPGA_R&D_Dept
- * MANUAL_PERCENT   : 100% 
- *****************************************************************************/
-#include "zxic_common.h"
-#include "zxic_comm_index_fill.h"
-#include "zxic_comm_double_link.h"
-
-/***********************************************************/
-/** 释放数据节点
-* @param   p_data
-*
-* @return
-* @remark  无
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-ZXIC_RTN32 ic_comm_node_data_free(void *p_data)
-{
-    ZXIC_COMM_CHECK_POINT(p_data);
-    ZXIC_COMM_FREE(p_data);
-
-    return ZXIC_OK;
-}
-
-ZXIC_RTN32 zxic_comm_indexfill_init(INDEX_FILL_CFG *p_fill_cfg,ZXIC_UINT32 index_num,ZXIC_KEY_CMP_FUNC p_cmp_fun,INDEXFILL_SWAP_FUNC p_swap_fun,ZXIC_UINT32 key_len)
-{
-    ZXIC_UINT32   rtn = 0;
-    
-    p_fill_cfg->index_num = index_num;
-    p_fill_cfg->total_used = 0;
-    p_fill_cfg->swap_fun   = p_swap_fun;
-
-    rtn = zxic_comm_rb_init(&p_fill_cfg->fill_rb,0,key_len,p_cmp_fun);
-    ZXIC_COMM_CHECK_RC(rtn,"zxic_comm_rb_init");
-    
-    return ZXIC_OK;
-}
-/* 前向挤压 */
-ZXIC_RTN32 zxic_comm_indexfill_handle_position_right(INDEX_FILL_CFG *p_fill_cfg,INDEX_FILL_NODE* p_start,INDEX_FILL_NODE* p_end)
-{
-    ZXIC_UINT32   rtn       = 0;
-
-    INDEX_FILL_NODE *p_cur_node = p_start;
-    INDEX_FILL_NODE *p_nxt_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(p_cur_node->rb_node.tn_ln.next,ZXIC_RB_TN,tn_ln);
-    INDEX_FILL_NODE *p_pre_node = NULL;
-
-    while(p_cur_node != p_end)
-    {
-        if(ICMINF_GET_NODE_LASTPOS(p_cur_node) + 1 < ICMINF_GET_NODE_FSTPOS(p_nxt_node))
-        {
-            break;
-        }
-        else
-        {
-            p_cur_node = p_nxt_node;
-            
-            if(p_cur_node->rb_node.tn_ln.next)
-            {
-                p_nxt_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(p_cur_node->rb_node.tn_ln.next,ZXIC_RB_TN,tn_ln);
-            }
-        }
-    }
-
-    ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(p_fill_cfg->index_num, 1);
-    if(p_cur_node == p_end && p_fill_cfg->index_num - 1 == ICMINF_GET_NODE_LASTPOS(p_end))
-    {
-        return ZXIC_INDEX_FILL_FULL;
-    }
-    
-    p_pre_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(p_cur_node->rb_node.tn_ln.prev,ZXIC_RB_TN,tn_ln);
-
-    while(p_cur_node != p_start)
-    {
-        if(p_fill_cfg->swap_fun)
-        {
-            rtn = p_fill_cfg->swap_fun(ICMINF_GET_NODE_FSTPOS(p_cur_node),ICMINF_GET_NODE_LASTPOS(p_cur_node) + 1,p_fill_cfg);
-        }
-
-        ICMINF_GET_NODE_FSTPOS(p_cur_node) = ICMINF_GET_NODE_FSTPOS(p_cur_node) + 1;
-
-        p_cur_node = p_pre_node;
-
-        if(p_cur_node->rb_node.tn_ln.prev)
-        {
-            p_pre_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(p_cur_node->rb_node.tn_ln.prev,ZXIC_RB_TN,tn_ln);
-        }        
-    }
-
-    if(p_fill_cfg->swap_fun)
-    {
-        rtn = p_fill_cfg->swap_fun(ICMINF_GET_NODE_FSTPOS(p_start),ICMINF_GET_NODE_LASTPOS(p_start)+1,p_fill_cfg);
-    }
-
-    ICMINF_GET_NODE_FSTPOS(p_start) =  ICMINF_GET_NODE_FSTPOS(p_start) + 1;
-    
-    return rtn;
-}
-/* 后向挤压 */
-ZXIC_RTN32 zxic_comm_indexfill_handle_position_left(INDEX_FILL_CFG *p_fill_cfg,INDEX_FILL_NODE* p_start,INDEX_FILL_NODE* p_end)
-{
-    ZXIC_UINT32   rtn       = 0;
-
-    INDEX_FILL_NODE *p_cur_node = p_start;
-    INDEX_FILL_NODE *p_nxt_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(p_cur_node->rb_node.tn_ln.prev,ZXIC_RB_TN,tn_ln);
-    INDEX_FILL_NODE *p_pre_node = NULL;
-
-    while(p_cur_node != p_end)
-    {
-        ZXIC_COMM_CHECK_POINT(p_nxt_node);
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(p_nxt_node->position, p_nxt_node->usednum);
-        ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW((p_nxt_node->position + p_nxt_node->usednum), 1);
-        
-        if(ICMINF_GET_NODE_FSTPOS(p_cur_node) -1 > ICMINF_GET_NODE_LASTPOS(p_nxt_node))
-        {
-            break;
-        }
-        else
-        {
-            p_cur_node = p_nxt_node;
-            
-            if(p_cur_node->rb_node.tn_ln.prev)
-            {
-                p_nxt_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(p_cur_node->rb_node.tn_ln.prev,ZXIC_RB_TN,tn_ln);
-            }
-        }
-    }
-
-    if(p_cur_node == p_end && 0 == ICMINF_GET_NODE_FSTPOS(p_end))
-    {
-        return ZXIC_INDEX_FILL_FULL;
-    }
-
-    p_pre_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(p_cur_node->rb_node.tn_ln.next,ZXIC_RB_TN,tn_ln);
-
-    while(p_cur_node != p_start)
-    {
-        if(p_fill_cfg->swap_fun)/*将最后一个移动到本节点第一个*/
-        {
-            rtn = p_fill_cfg->swap_fun(ICMINF_GET_NODE_LASTPOS(p_cur_node),ICMINF_GET_NODE_FSTPOS(p_cur_node)-1,p_fill_cfg);
-
-        }
-
-        ICMINF_GET_NODE_FSTPOS(p_cur_node) = ICMINF_GET_NODE_FSTPOS(p_cur_node)-1;
-        
-        p_cur_node = p_pre_node;
-
-        if(p_cur_node->rb_node.tn_ln.next)
-        {
-            p_pre_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(p_cur_node->rb_node.tn_ln.next,ZXIC_RB_TN,tn_ln);
-        }        
-    }
-    
-    if(p_fill_cfg->swap_fun)
-    {
-        rtn = p_fill_cfg->swap_fun(ICMINF_GET_NODE_LASTPOS(p_start),ICMINF_GET_NODE_FSTPOS(p_start)-1,p_fill_cfg);
-    }    
-
-    ICMINF_GET_NODE_FSTPOS(p_start) = ICMINF_GET_NODE_FSTPOS(p_start) -1;
-    
-    return rtn;
-}
-
-ZXIC_RTN32 zxic_comm_indexfill_free(INDEX_FILL_CFG *p_fill_cfg,ZXIC_UINT32 free_index,ZXIC_VOID* p_rb_key,ZXIC_UINT32 *out_index)
-{
-    ZXIC_UINT32   rtn       = 0;
-    ZXIC_RB_TN       *p_rb_out   = NULL;
-    INDEX_FILL_NODE *p_inf_node = NULL;
-
-    rtn = zxic_comm_rb_search(&p_fill_cfg->fill_rb, p_rb_key, &p_rb_out);
-
-    if ((!p_rb_out)||(rtn!=ZXIC_OK) )
-    {
-        ZXIC_COMM_TRACE_ERROR("\n srh fail ,the key is not exist");
-        return ZXIC_INDEX_DEL_FAIL;
-    }
-
-    p_inf_node = (INDEX_FILL_NODE *)p_rb_out;
-    
-    ZXIC_COMM_ASSERT(p_inf_node->usednum);
-
-    ZXIC_COMM_CHECK_INDEX(free_index,ICMINF_GET_NODE_FSTPOS(p_inf_node),ICMINF_GET_NODE_LASTPOS(p_inf_node));
-
-     *out_index = free_index;
-    
-    if(free_index == ICMINF_GET_NODE_FSTPOS(p_inf_node))
-    {
-        p_inf_node->position++;
-    }
-    else if(free_index != ICMINF_GET_NODE_LASTPOS(p_inf_node))
-    {
-       *out_index = ICMINF_GET_NODE_FSTPOS(p_inf_node);
-
-       if(p_fill_cfg->swap_fun)
-       {
-            p_fill_cfg->swap_fun(ICMINF_GET_NODE_FSTPOS(p_inf_node), free_index, p_fill_cfg);
-       }
-
-       p_inf_node->position++;
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEBUG("\n Free the last position,do nothing \n");
-    }
-
-    p_inf_node->usednum--;
-    
-    if(p_inf_node->usednum == 0)
-    {
-        rtn = zxic_comm_rb_delete(&p_fill_cfg->fill_rb,p_rb_key,&p_rb_out);
-        ZXIC_COMM_CHECK_RC(rtn,"zxic_comm_rb_delete"); 
-
-        if(!p_rb_out)
-        {
-            ZXIC_COMM_TRACE_ERROR("\n srh fail ,the key is not exist");
-            return ZXIC_INDEX_DEL_FAIL;
-        }
-
-        ZXIC_COMM_FREE(p_inf_node->rb_node.p_key);
-
-        ZXIC_COMM_FREE(p_inf_node); 
-    }
-    else
-    {
-        /*ICMINF_GET_NODE_FSTPOS(p_inf_node) = ICMINF_GET_NODE_FSTPOS(p_inf_node)-1;*/
-    }
-
-    ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(p_fill_cfg->total_used, 1);
-    p_fill_cfg->total_used--;
-    
-    return ZXIC_OK;
-}
-
-ZXIC_RTN32 zxic_comm_indexfill_destroy(INDEX_FILL_CFG *p_fill_cfg)
-{
-    ZXIC_UINT32 rtn = 0;
-
-    rtn = zxic_comm_dlink_release(&p_fill_cfg->fill_rb.tn_list,ic_comm_node_data_free);
-    ZXIC_COMM_CHECK_RC(rtn,"zxic_comm_dlink_release");
-
-    ZXIC_COMM_MEMSET(p_fill_cfg,0,ZXIC_SIZEOF(INDEX_FILL_CFG));
-    
-    return ZXIC_OK;
-}
-
-ZXIC_RTN32 zxic_comm_indexfill_show_all_position(INDEX_FILL_CFG *p_fill_cfg)
-{
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    D_NODE       *p_node     = NULL;
-    INDEX_FILL_NODE *p_inf_node = NULL;
-
-    p_node = p_fill_cfg->fill_rb.tn_list.p_next;
-
-    ZXIC_COMM_PRINT("\n *************************Used Position*************************\n");
-
-    while(p_node)
-    {
-        ZXIC_COMM_PRINT("\n ==== Num [%d ] ==== :",i); 
-        
-        p_inf_node = (INDEX_FILL_NODE *)(STRUCT_ENTRY_POINT(p_node,ZXIC_RB_TN,tn_ln));
-        
-        for(j = 0 ;j < p_inf_node->usednum;j++)
-        {            
-            ZXIC_COMM_PRINT(" %d ",ICMINF_GET_NODE_FSTPOS(p_inf_node)+ j);
-
-            if (j != 0 && j % 8 == 0)
-            {
-                ZXIC_COMM_PRINT("\n                   ");
-            }
-        }        
-
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(i, 1);
-        i++;
-        
-        p_node = p_node->next; 
-    }
-
-    ZXIC_COMM_PRINT("\n*******End*******\n");
-
-    return ZXIC_OK;
-    
-}
-
-ZXIC_RTN32 zxic_comm_indexfill_store(INDEX_FILL_CFG *p_fill_cfg, ZXIC_UINT32 *p_size, ZXIC_UINT8 **p_data_buff)
-{
-    ZXIC_UINT32   rtn       = 0;
-    ZXIC_UINT32   i         = 0;
-    ZXIC_UINT32   used_node_num      = 0;
-    ZXIC_UINT32   rb_node_size       = 0;
-    ZXIC_UINT32   max_index_num      = 0;  
-    ZXIC_UINT32   buff_offset        = 0;
-    ZXIC_UINT32   tmp_val            = 0;
-    D_NODE          *p_node     = NULL;
-    INDEX_FILL_NODE *p_inf_node = NULL;
-    ZXIC_UINT8 *p_item_buff           = NULL;
-    ZXIC_UINT32 item_buff_offset     = 0;
-    /*
-    |   used_node_num  |  rb_node_size | max_index_num  |//head
-    | node_start_index | node_used_num | rb_key ... ... |//item
-    */
-    
-    ZXIC_COMM_CHECK_POINT(p_fill_cfg);
-    ZXIC_COMM_CHECK_POINT(p_size);
-    //item size
-    rb_node_size = p_fill_cfg->fill_rb.key_size + 8;/*sizeof(ZXIC_UINT32) + sizeof(ZXIC_UINT32);*/
-    max_index_num = p_fill_cfg->index_num;
-    
-    p_node = p_fill_cfg->fill_rb.tn_list.p_next;
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(used_node_num, 1);
-    while(p_node)
-    {
-        //p_inf_node = (INDEX_FILL_NODE *)(STRUCT_ENTRY_POINT(p_node,ZXIC_RB_TN,tn_ln));
-        used_node_num++;
-        p_node = p_node->next; 
-    }
-    tmp_val = ZXIC_SIZEOF(ZXIC_UINT32) * 3;
-    ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW(rb_node_size, used_node_num);
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(tmp_val, rb_node_size * used_node_num);    
-    *p_size = tmp_val + rb_node_size * used_node_num;
-    
-    *p_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(*p_size);
-    ZXIC_COMM_CHECK_POINT(*p_data_buff);
-    ZXIC_COMM_MEMSET(*p_data_buff, 0, *p_size);
-    
-    buff_offset = 0;
-    
-    ZXIC_COMM_MEMCPY_S(*p_data_buff + buff_offset, ZXIC_SIZEOF(ZXIC_UINT32), &used_node_num, ZXIC_SIZEOF(ZXIC_UINT32));
-    buff_offset += ZXIC_SIZEOF(ZXIC_UINT32);
-    ZXIC_COMM_MEMCPY_S(*p_data_buff + buff_offset, ZXIC_SIZEOF(ZXIC_UINT32), &rb_node_size, ZXIC_SIZEOF(ZXIC_UINT32));
-    buff_offset += ZXIC_SIZEOF(ZXIC_UINT32);
-    ZXIC_COMM_MEMCPY_S(*p_data_buff + buff_offset, ZXIC_SIZEOF(ZXIC_UINT32), &max_index_num, ZXIC_SIZEOF(ZXIC_UINT32));
-    buff_offset += ZXIC_SIZEOF(ZXIC_UINT32);
-
-    p_item_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(rb_node_size);
-    ZXIC_COMM_CHECK_POINT(p_item_buff);
-    ZXIC_COMM_MEMSET(p_item_buff, 0, rb_node_size);
-    
-    for(i = 0; i < used_node_num; i++)
-    {
-        if(0 == i)
-        {
-            p_node = p_fill_cfg->fill_rb.tn_list.p_next;
-            ZXIC_COMM_CHECK_POINT_MEMORY_FREE(p_node, p_item_buff);
-        }
-        else
-        {
-            p_node = p_node->next;
-            ZXIC_COMM_CHECK_POINT_MEMORY_FREE(p_node, p_item_buff);
-        }
-        item_buff_offset = 0;
-        
-        p_inf_node = (INDEX_FILL_NODE *)(STRUCT_ENTRY_POINT(p_node,ZXIC_RB_TN,tn_ln));
-
-        ZXIC_COMM_MEMCPY_S(p_item_buff + item_buff_offset, ZXIC_SIZEOF(ZXIC_UINT32), &(p_inf_node->position), ZXIC_SIZEOF(ZXIC_UINT32));
-        item_buff_offset += ZXIC_SIZEOF(ZXIC_UINT32);
-        ZXIC_COMM_MEMCPY_S(p_item_buff + item_buff_offset, ZXIC_SIZEOF(ZXIC_UINT32), &(p_inf_node->usednum), ZXIC_SIZEOF(ZXIC_UINT32));
-        item_buff_offset += ZXIC_SIZEOF(ZXIC_UINT32);
-        ZXIC_COMM_MEMCPY_S(p_item_buff + item_buff_offset, p_fill_cfg->fill_rb.key_size, p_inf_node->rb_node.p_key, p_fill_cfg->fill_rb.key_size);
-
-        ZXIC_COMM_MEMCPY_S(*p_data_buff + buff_offset, rb_node_size, p_item_buff, rb_node_size);
-
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_MEMORY_FREE(buff_offset, rb_node_size, p_item_buff);
-        buff_offset += rb_node_size;
-    }
-
-    ZXIC_COMM_ASSERT(buff_offset == *p_size);
-    
-    ZXIC_COMM_FREE(p_item_buff);
-    
-    return rtn;
-}
-
-ZXIC_RTN32 zxic_comm_indexfill_clear(INDEX_FILL_CFG *p_fill_cfg)
-{
-    ZXIC_UINT32 rtn = 0;
-    ZXIC_UINT32 key_len = p_fill_cfg->fill_rb.key_size;
-    ZXIC_KEY_CMP_FUNC p_cmp_fun = p_fill_cfg->fill_rb.p_cmpfun;
-    INDEX_FILL_NODE *fill_node;
-    D_NODE *p_curnode = NULL;
-    void *cur_data;
-    p_curnode = p_fill_cfg->fill_rb.tn_list.p_next;
-    
-    while(p_curnode)
-    {
-        cur_data = p_curnode->data;
-        p_curnode = p_curnode->next;
-        fill_node = cur_data;
-        ZXIC_COMM_FREE(fill_node->rb_node.p_key);
-        ZXIC_COMM_FREE(fill_node);
-        
-    }
-    
-    rtn = zxic_comm_rb_destroy(&p_fill_cfg->fill_rb);
-    ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_destroy");
-
-    rtn = zxic_comm_rb_init(&p_fill_cfg->fill_rb, 0, key_len, p_cmp_fun);
-    ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_init");
-
-    
-    p_fill_cfg->total_used = 0;
-
-
-    return ZXIC_OK;
-}
-
-
+/*****************************************************************************
+ * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：   zxic_index_fill.c
+ * 文件标识：
+ * 内容摘要：   索引空位填充源代码头文件
+ * 其它说明：
+ * 当前版本：
+ * 作    者：    ChenWei10088471
+ * 完成日期：
+ * 当前责任人-1：
+ * 当前责任人-2：
+ *
+ * DEPARTMENT       : ASIC_FPGA_R&D_Dept
+ * MANUAL_PERCENT   : 100%
+ *****************************************************************************/
+#include "zxic_common.h"
+#include "zxic_comm_index_fill.h"
+#include "zxic_comm_double_link.h"
+
+/***********************************************************/
+/** 释放数据节点
+ * @param   p_data
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  ChenWei10088471      @date  2014/02/07
+ ************************************************************/
+ZXIC_RTN32 ic_comm_node_data_free(void *p_data)
+{
+	ZXIC_COMM_CHECK_POINT(p_data);
+	ZXIC_COMM_FREE(p_data);
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_indexfill_init(INDEX_FILL_CFG *p_fill_cfg,
+									ZXIC_UINT32 index_num,
+									ZXIC_KEY_CMP_FUNC p_cmp_fun,
+									INDEXFILL_SWAP_FUNC p_swap_fun,
+									ZXIC_UINT32 key_len)
+{
+	ZXIC_UINT32 rtn = 0;
+
+	p_fill_cfg->index_num = index_num;
+	p_fill_cfg->total_used = 0;
+	p_fill_cfg->swap_fun = p_swap_fun;
+
+	rtn = zxic_comm_rb_init(&p_fill_cfg->fill_rb, 0, key_len, p_cmp_fun);
+	ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_init");
+
+	return ZXIC_OK;
+}
+/* 前向挤压 */
+ZXIC_RTN32 zxic_comm_indexfill_handle_position_right(INDEX_FILL_CFG *p_fill_cfg,
+													 INDEX_FILL_NODE *p_start,
+													 INDEX_FILL_NODE *p_end)
+{
+	ZXIC_UINT32 rtn = 0;
+
+	INDEX_FILL_NODE *p_cur_node = p_start;
+	INDEX_FILL_NODE *p_nxt_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(
+			p_cur_node->rb_node.tn_ln.next, ZXIC_RB_TN, tn_ln);
+	INDEX_FILL_NODE *p_pre_node = NULL;
+
+	while (p_cur_node != p_end) {
+		if (ICMINF_GET_NODE_LASTPOS(p_cur_node) + 1 <
+			ICMINF_GET_NODE_FSTPOS(p_nxt_node)) {
+			break;
+		} else {
+			p_cur_node = p_nxt_node;
+
+			if (p_cur_node->rb_node.tn_ln.next) {
+				p_nxt_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(
+						p_cur_node->rb_node.tn_ln.next, ZXIC_RB_TN, tn_ln);
+			}
+		}
+	}
+
+	ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(p_fill_cfg->index_num, 1);
+	if (p_cur_node == p_end &&
+		p_fill_cfg->index_num - 1 == ICMINF_GET_NODE_LASTPOS(p_end)) {
+		return ZXIC_INDEX_FILL_FULL;
+	}
+
+	p_pre_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(
+			p_cur_node->rb_node.tn_ln.prev, ZXIC_RB_TN, tn_ln);
+
+	while (p_cur_node != p_start) {
+		if (p_fill_cfg->swap_fun) {
+			rtn = p_fill_cfg->swap_fun(ICMINF_GET_NODE_FSTPOS(p_cur_node),
+									   ICMINF_GET_NODE_LASTPOS(p_cur_node) + 1,
+									   p_fill_cfg);
+		}
+
+		ICMINF_GET_NODE_FSTPOS(p_cur_node) =
+				ICMINF_GET_NODE_FSTPOS(p_cur_node) + 1;
+
+		p_cur_node = p_pre_node;
+
+		if (p_cur_node->rb_node.tn_ln.prev) {
+			p_pre_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(
+					p_cur_node->rb_node.tn_ln.prev, ZXIC_RB_TN, tn_ln);
+		}
+	}
+
+	if (p_fill_cfg->swap_fun) {
+		rtn = p_fill_cfg->swap_fun(ICMINF_GET_NODE_FSTPOS(p_start),
+								   ICMINF_GET_NODE_LASTPOS(p_start) + 1,
+								   p_fill_cfg);
+	}
+
+	ICMINF_GET_NODE_FSTPOS(p_start) = ICMINF_GET_NODE_FSTPOS(p_start) + 1;
+
+	return rtn;
+}
+/* 后向挤压 */
+ZXIC_RTN32 zxic_comm_indexfill_handle_position_left(INDEX_FILL_CFG *p_fill_cfg,
+													INDEX_FILL_NODE *p_start,
+													INDEX_FILL_NODE *p_end)
+{
+	ZXIC_UINT32 rtn = 0;
+
+	INDEX_FILL_NODE *p_cur_node = p_start;
+	INDEX_FILL_NODE *p_nxt_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(
+			p_cur_node->rb_node.tn_ln.prev, ZXIC_RB_TN, tn_ln);
+	INDEX_FILL_NODE *p_pre_node = NULL;
+
+	while (p_cur_node != p_end) {
+		ZXIC_COMM_CHECK_POINT(p_nxt_node);
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(p_nxt_node->position,
+										   p_nxt_node->usednum);
+		ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(
+				(p_nxt_node->position + p_nxt_node->usednum), 1);
+
+		if (ICMINF_GET_NODE_FSTPOS(p_cur_node) - 1 >
+			ICMINF_GET_NODE_LASTPOS(p_nxt_node)) {
+			break;
+		} else {
+			p_cur_node = p_nxt_node;
+
+			if (p_cur_node->rb_node.tn_ln.prev) {
+				p_nxt_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(
+						p_cur_node->rb_node.tn_ln.prev, ZXIC_RB_TN, tn_ln);
+			}
+		}
+	}
+
+	if (p_cur_node == p_end && 0 == ICMINF_GET_NODE_FSTPOS(p_end)) {
+		return ZXIC_INDEX_FILL_FULL;
+	}
+
+	p_pre_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(
+			p_cur_node->rb_node.tn_ln.next, ZXIC_RB_TN, tn_ln);
+
+	while (p_cur_node != p_start) {
+		if (p_fill_cfg->swap_fun) { /*将最后一个移动到本节点第一个*/
+			rtn = p_fill_cfg->swap_fun(ICMINF_GET_NODE_LASTPOS(p_cur_node),
+									   ICMINF_GET_NODE_FSTPOS(p_cur_node) - 1,
+									   p_fill_cfg);
+		}
+
+		ICMINF_GET_NODE_FSTPOS(p_cur_node) =
+				ICMINF_GET_NODE_FSTPOS(p_cur_node) - 1;
+
+		p_cur_node = p_pre_node;
+
+		if (p_cur_node->rb_node.tn_ln.next) {
+			p_pre_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(
+					p_cur_node->rb_node.tn_ln.next, ZXIC_RB_TN, tn_ln);
+		}
+	}
+
+	if (p_fill_cfg->swap_fun) {
+		rtn = p_fill_cfg->swap_fun(ICMINF_GET_NODE_LASTPOS(p_start),
+								   ICMINF_GET_NODE_FSTPOS(p_start) - 1,
+								   p_fill_cfg);
+	}
+
+	ICMINF_GET_NODE_FSTPOS(p_start) = ICMINF_GET_NODE_FSTPOS(p_start) - 1;
+
+	return rtn;
+}
+
+ZXIC_RTN32 zxic_comm_indexfill_alloc(INDEX_FILL_CFG *p_fill_cfg,
+									 ZXIC_UINT32 *out_index,
+									 ZXIC_VOID *p_rb_key) /*acl_info*/
+{
+	ZXIC_UINT32 rtn = 0;
+	ZXIC_RB_TN *rb_index = NULL;
+	INDEX_FILL_NODE *p_fill_node = NULL;
+	INDEX_FILL_NODE *p_nxt_node = NULL;
+	INDEX_FILL_NODE *p_pre_node = NULL;
+	INDEX_FILL_NODE *p_start_node = NULL;
+	INDEX_FILL_NODE *p_end_node = NULL;
+	ZXIC_RB_TN *p_rb_find = NULL;
+	ZXIC_UINT8 *p_key = NULL;
+	ZXIC_UINT32 is_head_mdy = 0; /*是否需修改头指针*/
+
+	ZXIC_COMM_CHECK_POINT(p_fill_cfg);
+	ZXIC_COMM_CHECK_POINT(out_index);
+	ZXIC_COMM_CHECK_POINT(p_rb_key);
+
+	if (p_fill_cfg->index_num == p_fill_cfg->total_used) {
+		ZXIC_COMM_TRACE_INFO("\n , index fill is full !");
+		return ZXIC_INDEX_FILL_FULL;
+	}
+
+	if (p_fill_cfg->fill_rb.tn_list.p_next) {
+		p_start_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(
+				p_fill_cfg->fill_rb.tn_list.p_next, ZXIC_RB_TN, tn_ln);
+	}
+
+	if (p_fill_cfg->fill_rb.tn_list.p_prev) {
+		p_end_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(
+				p_fill_cfg->fill_rb.tn_list.p_prev, ZXIC_RB_TN, tn_ln);
+	}
+
+	p_fill_node =
+			(INDEX_FILL_NODE *)ZXIC_COMM_MALLOC(ZXIC_SIZEOF(INDEX_FILL_NODE));
+	ZXIC_COMM_CHECK_POINT(p_fill_node);
+	ZXIC_COMM_MEMSET(p_fill_node, 0, ZXIC_SIZEOF(INDEX_FILL_NODE));
+
+	p_key = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(p_fill_cfg->fill_rb.key_size);
+
+	if (NULL == p_key) {
+		ZXIC_COMM_FREE(p_fill_node);
+		ZXIC_COMM_TRACE_ERROR(
+				"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", __FILE__,
+				__LINE__, __FUNCTION__);
+		return ZXIC_PAR_CHK_POINT_NULL;
+	}
+
+	ZXIC_COMM_MEMSET(p_key, 0, p_fill_cfg->fill_rb.key_size);
+
+	ZXIC_COMM_MEMCPY_S(p_key, p_fill_cfg->fill_rb.key_size, p_rb_key,
+					   p_fill_cfg->fill_rb.key_size);
+	p_fill_node->rb_node.p_key = p_key;
+
+	rtn = zxic_comm_rb_insert(&p_fill_cfg->fill_rb, p_fill_node, &rb_index);
+
+	if (rtn == ZXIC_RBT_RC_UPDATE) {
+		ZXIC_COMM_TRACE_DEBUG("\n %s, same key ,add used one!", __FUNCTION__);
+
+		rtn = zxic_comm_rb_search(&p_fill_cfg->fill_rb, p_rb_key, &p_rb_find);
+		ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_search");
+
+		ZXIC_COMM_CHECK_POINT(p_rb_find);
+
+		ZXIC_COMM_FREE(p_fill_node->rb_node.p_key);
+
+		ZXIC_COMM_FREE(p_fill_node);
+
+		p_fill_node = (INDEX_FILL_NODE *)p_rb_find;
+	} else {
+		ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_insert");
+	}
+
+	if (p_fill_node->rb_node.tn_ln.next) {
+		p_nxt_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(
+				p_fill_node->rb_node.tn_ln.next, ZXIC_RB_TN, tn_ln);
+	}
+
+	if (p_fill_node->rb_node.tn_ln.prev) {
+		p_pre_node = (INDEX_FILL_NODE *)STRUCT_ENTRY_POINT(
+				p_fill_node->rb_node.tn_ln.prev, ZXIC_RB_TN, tn_ln);
+	}
+
+	if (!p_nxt_node) { /*无后继节点，则作为最后一个节点插入，无需重排*/
+		if (!p_pre_node) {
+			if (p_fill_node->usednum == 0) {
+				*out_index = 0;
+			} else if (ICMINF_GET_NODE_LASTPOS(p_fill_node) ==
+					   p_fill_cfg->index_num - 1) {
+				*out_index = ICMINF_GET_NODE_FSTPOS(p_fill_node) - 1;
+				is_head_mdy = 1;
+			} else {
+				*out_index = ICMINF_GET_NODE_LASTPOS(p_fill_node) + 1;
+			}
+		} else if (p_end_node &&
+				   (ICMINF_GET_NODE_LASTPOS(p_end_node) !=
+					p_fill_cfg->index_num - 1)){ /*xjw mod for KW_0411 #725*/
+			*out_index = ICMINF_GET_NODE_LASTPOS(p_end_node) + 1;
+		} else {
+			if (p_end_node && p_start_node) {
+				rtn = zxic_comm_indexfill_handle_position_left(
+						p_fill_cfg, p_end_node, p_start_node);
+				ZXIC_COMM_CHECK_RC(rtn,
+								   "zxic_comm_indexfill_handle_position_left");
+
+				*out_index = ICMINF_GET_NODE_LASTPOS(p_end_node) + 1;
+			}
+		}
+	} else if (!p_pre_node) {
+		if (p_fill_node->usednum == 0) {
+			if (ICMINF_GET_NODE_FSTPOS(p_nxt_node) != 0) {
+				*out_index = ICMINF_GET_NODE_FSTPOS(p_nxt_node) - 1;
+			} else {
+				if (p_end_node) {
+					rtn = zxic_comm_indexfill_handle_position_right(
+							p_fill_cfg, p_nxt_node, p_end_node);
+					ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_indexfill_handle_position_right");
+
+					*out_index = ICMINF_GET_NODE_FSTPOS(p_nxt_node) - 1;
+				}
+			}
+		} else {
+			if (p_start_node && (ICMINF_GET_NODE_FSTPOS(p_start_node) != 0)) {
+				*out_index = ICMINF_GET_NODE_FSTPOS(p_start_node) - 1;
+			} else {
+				if (p_start_node && p_end_node) {
+					rtn = zxic_comm_indexfill_handle_position_right(
+							p_fill_cfg, p_start_node, p_end_node);
+					ZXIC_COMM_CHECK_RC(
+							rtn, "zxic_comm_indexfill_handle_position_right");
+
+					*out_index = ICMINF_GET_NODE_FSTPOS(p_start_node) - 1;
+				}
+			}
+
+			is_head_mdy = 1;
+		}
+	} else {
+		if (ICMINF_GET_NODE_FSTPOS(p_nxt_node) -
+					ICMINF_GET_NODE_LASTPOS(p_pre_node) >
+			1 + p_fill_node->usednum) {
+			if (p_fill_node->usednum == 0) {
+				*out_index = ICMINF_GET_NODE_FSTPOS(p_nxt_node) - 1;
+			} else if (ICMINF_GET_NODE_LASTPOS(p_fill_node) + 1 ==
+					   ICMINF_GET_NODE_FSTPOS(p_nxt_node)) {
+				*out_index = ICMINF_GET_NODE_FSTPOS(p_fill_node) - 1;
+
+				is_head_mdy = 1;
+			} else {
+				*out_index = ICMINF_GET_NODE_LASTPOS(p_fill_node) + 1;
+			}
+		} else {
+			if (p_end_node) {
+				rtn = zxic_comm_indexfill_handle_position_right(
+						p_fill_cfg, p_nxt_node, p_end_node);
+
+				if (rtn == ZXIC_OK) {
+					*out_index = ICMINF_GET_NODE_FSTPOS(p_nxt_node) - 1;
+				} else {
+					if (p_start_node != NULL) {
+						rtn = zxic_comm_indexfill_handle_position_left(
+								p_fill_cfg, p_pre_node, p_start_node);
+						ZXIC_COMM_CHECK_RC(
+								rtn, "zxic_comm_indexfill_handle_position");
+
+						*out_index = ICMINF_GET_NODE_LASTPOS(p_pre_node) + 1;
+
+						is_head_mdy = 1;
+					}
+				}
+			}
+		}
+	}
+
+	if (is_head_mdy || p_fill_node->usednum == 0) {
+		p_fill_node->position = *out_index;
+	}
+
+	p_fill_node->usednum++;
+
+	p_fill_cfg->total_used++;
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_indexfill_free(INDEX_FILL_CFG *p_fill_cfg,
+									ZXIC_UINT32 free_index, ZXIC_VOID *p_rb_key,
+									ZXIC_UINT32 *out_index)
+{
+	ZXIC_UINT32 rtn = 0;
+	ZXIC_RB_TN *p_rb_out = NULL;
+	INDEX_FILL_NODE *p_inf_node = NULL;
+
+	rtn = zxic_comm_rb_search(&p_fill_cfg->fill_rb, p_rb_key, &p_rb_out);
+
+	if ((!p_rb_out) || (rtn != ZXIC_OK)) {
+		ZXIC_COMM_TRACE_ERROR("\n srh fail ,the key is not exist");
+		return ZXIC_INDEX_DEL_FAIL;
+	}
+
+	p_inf_node = (INDEX_FILL_NODE *)p_rb_out;
+
+	ZXIC_COMM_ASSERT(p_inf_node->usednum);
+
+	ZXIC_COMM_CHECK_INDEX(free_index, ICMINF_GET_NODE_FSTPOS(p_inf_node),
+						  ICMINF_GET_NODE_LASTPOS(p_inf_node));
+
+	*out_index = free_index;
+
+	if (free_index == ICMINF_GET_NODE_FSTPOS(p_inf_node)) {
+		p_inf_node->position++;
+	} else if (free_index != ICMINF_GET_NODE_LASTPOS(p_inf_node)) {
+		*out_index = ICMINF_GET_NODE_FSTPOS(p_inf_node);
+
+		if (p_fill_cfg->swap_fun) {
+			p_fill_cfg->swap_fun(ICMINF_GET_NODE_FSTPOS(p_inf_node), free_index,
+								 p_fill_cfg);
+		}
+
+		p_inf_node->position++;
+	} else {
+		ZXIC_COMM_TRACE_DEBUG("\n Free the last position,do nothing \n");
+	}
+
+	p_inf_node->usednum--;
+
+	if (p_inf_node->usednum == 0) {
+		rtn = zxic_comm_rb_delete(&p_fill_cfg->fill_rb, p_rb_key, &p_rb_out);
+		ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_delete");
+
+		if (!p_rb_out) {
+			ZXIC_COMM_TRACE_ERROR("\n srh fail ,the key is not exist");
+			return ZXIC_INDEX_DEL_FAIL;
+		}
+
+		ZXIC_COMM_FREE(p_inf_node->rb_node.p_key);
+
+		ZXIC_COMM_FREE(p_inf_node);
+	} else {
+		/*ICMINF_GET_NODE_FSTPOS(p_inf_node) = ICMINF_GET_NODE_FSTPOS(p_inf_node)-1;*/
+	}
+
+	ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(p_fill_cfg->total_used, 1);
+	p_fill_cfg->total_used--;
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_indexfill_destroy(INDEX_FILL_CFG *p_fill_cfg)
+{
+	ZXIC_UINT32 rtn = 0;
+
+	rtn = zxic_comm_dlink_release(&p_fill_cfg->fill_rb.tn_list,
+								  ic_comm_node_data_free);
+	ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_dlink_release");
+
+	ZXIC_COMM_MEMSET(p_fill_cfg, 0, ZXIC_SIZEOF(INDEX_FILL_CFG));
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_indexfill_show_all_position(INDEX_FILL_CFG *p_fill_cfg)
+{
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 j = 0;
+	D_NODE *p_node = NULL;
+	INDEX_FILL_NODE *p_inf_node = NULL;
+
+	p_node = p_fill_cfg->fill_rb.tn_list.p_next;
+
+	ZXIC_COMM_PRINT(
+			"\n *************************Used Position*************************\n");
+
+	while (p_node) {
+		ZXIC_COMM_PRINT("\n ==== Num [%d ] ==== :", i);
+
+		p_inf_node = (INDEX_FILL_NODE *)(STRUCT_ENTRY_POINT(p_node, ZXIC_RB_TN,
+															tn_ln));
+
+		for (j = 0; j < p_inf_node->usednum; j++) {
+			ZXIC_COMM_PRINT(" %d ", ICMINF_GET_NODE_FSTPOS(p_inf_node) + j);
+
+			if (j != 0 && j % 8 == 0) {
+				ZXIC_COMM_PRINT("\n                   ");
+			}
+		}
+
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(i, 1);
+		i++;
+
+		p_node = p_node->next;
+	}
+
+	ZXIC_COMM_PRINT("\n*******End*******\n");
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_indexfill_insert(INDEX_FILL_CFG *p_fill_cfg,
+									  ZXIC_UINT32 first_index, ZXIC_UINT32 num,
+									  ZXIC_VOID *p_rb_key)
+{
+	ZXIC_UINT32 rtn = 0;
+	ZXIC_RB_TN *rb_index = NULL;
+	// ZXIC_UINT32   i         = 0;
+	INDEX_FILL_NODE *p_fill_node = NULL;
+	ZXIC_UINT8 *p_key = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_fill_cfg);
+	if (p_fill_cfg->index_num == p_fill_cfg->total_used) {
+		ZXIC_COMM_TRACE_INFO("\n , index fill is full !");
+		return ZXIC_INDEX_FILL_FULL;
+	}
+
+	p_fill_node =
+			(INDEX_FILL_NODE *)ZXIC_COMM_MALLOC(ZXIC_SIZEOF(INDEX_FILL_NODE));
+	ZXIC_COMM_CHECK_POINT(p_fill_node);
+	ZXIC_COMM_MEMSET(p_fill_node, 0, ZXIC_SIZEOF(INDEX_FILL_NODE));
+
+	p_key = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(p_fill_cfg->fill_rb.key_size);
+	ZXIC_COMM_CHECK_POINT_MEMORY_FREE(p_key, p_fill_node);
+	ZXIC_COMM_MEMSET(p_key, 0, p_fill_cfg->fill_rb.key_size);
+
+	ZXIC_COMM_MEMCPY_S(p_key, p_fill_cfg->fill_rb.key_size, p_rb_key,
+					   p_fill_cfg->fill_rb.key_size);
+	p_fill_node->rb_node.p_key = p_key;
+
+	ZXIC_COMM_PRINT("zxic_comm_rb_insert begin\n");
+	rtn = zxic_comm_rb_insert(&p_fill_cfg->fill_rb, p_fill_node, &rb_index);
+	if (ZXIC_OK != rtn) {
+		ZXIC_COMM_PRINT("Call zxic_comm_rb_insert Error!!!\n");
+		return rtn;
+	}
+
+	ICMINF_GET_NODE_FSTPOS(p_fill_node) = first_index;
+
+	ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(p_fill_cfg->total_used, num);
+	p_fill_node->usednum = num;
+	p_fill_cfg->total_used += num;
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_indexfill_store(INDEX_FILL_CFG *p_fill_cfg,
+									 ZXIC_UINT32 *p_size,
+									 ZXIC_UINT8 **p_data_buff)
+{
+	ZXIC_UINT32 rtn = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 used_node_num = 0;
+	ZXIC_UINT32 rb_node_size = 0;
+	ZXIC_UINT32 max_index_num = 0;
+	ZXIC_UINT32 buff_offset = 0;
+	ZXIC_UINT32 tmp_val = 0;
+	D_NODE *p_node = NULL;
+	INDEX_FILL_NODE *p_inf_node = NULL;
+	ZXIC_UINT8 *p_item_buff = NULL;
+	ZXIC_UINT32 item_buff_offset = 0;
+	/*
+    |   used_node_num  |  rb_node_size | max_index_num  |//head
+    | node_start_index | node_used_num | rb_key ... ... |//item
+    */
+
+	ZXIC_COMM_CHECK_POINT(p_fill_cfg);
+	ZXIC_COMM_CHECK_POINT(p_size);
+	// item size
+	rb_node_size = p_fill_cfg->fill_rb.key_size +
+				   8; /*sizeof(ZXIC_UINT32) + sizeof(ZXIC_UINT32);*/
+	max_index_num = p_fill_cfg->index_num;
+
+	p_node = p_fill_cfg->fill_rb.tn_list.p_next;
+
+	ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(used_node_num, 1);
+	while (p_node) {
+		// p_inf_node = (INDEX_FILL_NODE *)(STRUCT_ENTRY_POINT(p_node,ZXIC_RB_TN,tn_ln));
+		used_node_num++;
+		p_node = p_node->next;
+	}
+	tmp_val = ZXIC_SIZEOF(ZXIC_UINT32) * 3;
+	ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW(rb_node_size, used_node_num);
+	ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(tmp_val, rb_node_size * used_node_num);
+	*p_size = tmp_val + rb_node_size * used_node_num;
+
+	*p_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(*p_size);
+	ZXIC_COMM_CHECK_POINT(*p_data_buff);
+	ZXIC_COMM_MEMSET(*p_data_buff, 0, *p_size);
+
+	buff_offset = 0;
+
+	ZXIC_COMM_MEMCPY_S(*p_data_buff + buff_offset, ZXIC_SIZEOF(ZXIC_UINT32),
+					   &used_node_num, ZXIC_SIZEOF(ZXIC_UINT32));
+	buff_offset += ZXIC_SIZEOF(ZXIC_UINT32);
+	ZXIC_COMM_MEMCPY_S(*p_data_buff + buff_offset, ZXIC_SIZEOF(ZXIC_UINT32),
+					   &rb_node_size, ZXIC_SIZEOF(ZXIC_UINT32));
+	buff_offset += ZXIC_SIZEOF(ZXIC_UINT32);
+	ZXIC_COMM_MEMCPY_S(*p_data_buff + buff_offset, ZXIC_SIZEOF(ZXIC_UINT32),
+					   &max_index_num, ZXIC_SIZEOF(ZXIC_UINT32));
+	buff_offset += ZXIC_SIZEOF(ZXIC_UINT32);
+
+	p_item_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(rb_node_size);
+	ZXIC_COMM_CHECK_POINT(p_item_buff);
+	ZXIC_COMM_MEMSET(p_item_buff, 0, rb_node_size);
+
+	for (i = 0; i < used_node_num; i++) {
+		if (0 == i) {
+			p_node = p_fill_cfg->fill_rb.tn_list.p_next;
+			ZXIC_COMM_CHECK_POINT_MEMORY_FREE(p_node, p_item_buff);
+		} else {
+			p_node = p_node->next;
+			ZXIC_COMM_CHECK_POINT_MEMORY_FREE(p_node, p_item_buff);
+		}
+		item_buff_offset = 0;
+
+		p_inf_node = (INDEX_FILL_NODE *)(STRUCT_ENTRY_POINT(p_node, ZXIC_RB_TN,
+															tn_ln));
+
+		ZXIC_COMM_MEMCPY_S(p_item_buff + item_buff_offset,
+						   ZXIC_SIZEOF(ZXIC_UINT32), &(p_inf_node->position),
+						   ZXIC_SIZEOF(ZXIC_UINT32));
+		item_buff_offset += ZXIC_SIZEOF(ZXIC_UINT32);
+		ZXIC_COMM_MEMCPY_S(p_item_buff + item_buff_offset,
+						   ZXIC_SIZEOF(ZXIC_UINT32), &(p_inf_node->usednum),
+						   ZXIC_SIZEOF(ZXIC_UINT32));
+		item_buff_offset += ZXIC_SIZEOF(ZXIC_UINT32);
+		ZXIC_COMM_MEMCPY_S(p_item_buff + item_buff_offset,
+						   p_fill_cfg->fill_rb.key_size,
+						   p_inf_node->rb_node.p_key,
+						   p_fill_cfg->fill_rb.key_size);
+
+		ZXIC_COMM_MEMCPY_S(*p_data_buff + buff_offset, rb_node_size,
+						   p_item_buff, rb_node_size);
+
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_MEMORY_FREE(
+				buff_offset, rb_node_size, p_item_buff);
+		buff_offset += rb_node_size;
+	}
+
+	ZXIC_COMM_ASSERT(buff_offset == *p_size);
+
+	ZXIC_COMM_FREE(p_item_buff);
+
+	return rtn;
+}
+
+ZXIC_RTN32 zxic_comm_indexfill_recovery(INDEX_FILL_CFG *p_fill_cfg,
+										ZXIC_UINT32 size,
+										ZXIC_UINT8 *p_data_buff,
+										ZXIC_KEY_CMP_FUNC p_cmp_fun,
+										INDEXFILL_SWAP_FUNC p_swap_fun)
+{
+	ZXIC_UINT32 rtn = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 buff_offset = 0;
+	ZXIC_UINT32 used_node_num = 0;
+	ZXIC_UINT32 rb_node_size = 0;
+	ZXIC_UINT32 max_index_num = 0;
+	ZXIC_UINT32 start_index = 0;
+	ZXIC_UINT32 used_num = 0;
+	ZXIC_UINT8 *p_key = NULL;
+	ZXIC_UINT32 key_size = 0;
+	ZXIC_UINT32 tmp_val = 0;
+	ZXIC_COMM_CHECK_POINT(p_fill_cfg);
+	ZXIC_COMM_CHECK_POINT(p_data_buff);
+
+	ZXIC_COMM_MEMCPY_S(&used_node_num, ZXIC_SIZEOF(ZXIC_UINT32),
+					   p_data_buff + buff_offset, ZXIC_SIZEOF(ZXIC_UINT32));
+	buff_offset += ZXIC_SIZEOF(ZXIC_UINT32);
+	ZXIC_COMM_MEMCPY_S(&rb_node_size, ZXIC_SIZEOF(ZXIC_UINT32),
+					   p_data_buff + buff_offset, ZXIC_SIZEOF(ZXIC_UINT32));
+	buff_offset += ZXIC_SIZEOF(ZXIC_UINT32);
+	ZXIC_COMM_MEMCPY_S(&max_index_num, ZXIC_SIZEOF(ZXIC_UINT32),
+					   p_data_buff + buff_offset, ZXIC_SIZEOF(ZXIC_UINT32));
+	buff_offset += ZXIC_SIZEOF(ZXIC_UINT32);
+
+	ZXIC_COMM_TRACE_DEBUG("used_node_num   : 0x%08x\n", used_node_num);
+	ZXIC_COMM_TRACE_DEBUG("rb_node_size    : 0x%08x\n", rb_node_size);
+	ZXIC_COMM_TRACE_DEBUG("max_index_num   : 0x%08x\n", max_index_num);
+
+	tmp_val = ZXIC_SIZEOF(ZXIC_UINT32) * 2;
+	ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(rb_node_size, tmp_val);
+	key_size = rb_node_size - tmp_val;
+
+	rtn = zxic_comm_indexfill_init(p_fill_cfg, max_index_num, p_cmp_fun,
+								   p_swap_fun, key_size);
+	ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_indexfill_init");
+
+	p_key = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(key_size);
+	ZXIC_COMM_CHECK_POINT(p_key);
+	ZXIC_COMM_MEMSET(p_key, 0, key_size);
+
+	ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(buff_offset, rb_node_size);
+	for (i = 0; i < used_node_num; i++, buff_offset += rb_node_size) {
+		ZXIC_COMM_MEMCPY_S(&start_index, ZXIC_SIZEOF(ZXIC_UINT32),
+						   p_data_buff + buff_offset, ZXIC_SIZEOF(ZXIC_UINT32));
+		ZXIC_COMM_MEMCPY_S(&used_num, ZXIC_SIZEOF(ZXIC_UINT32),
+						   p_data_buff + buff_offset + ZXIC_SIZEOF(ZXIC_UINT32),
+						   ZXIC_SIZEOF(ZXIC_UINT32));
+		ZXIC_COMM_MEMCPY_S(p_key, key_size,
+						   p_data_buff + buff_offset +
+								   ZXIC_SIZEOF(ZXIC_UINT32) * 2,
+						   key_size);
+		rtn = zxic_comm_indexfill_insert(p_fill_cfg, start_index, used_num,
+										 p_key);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE(rtn, "zxic_comm_indexfill_insert",
+									   p_key);
+	}
+
+	ZXIC_COMM_FREE(p_key);
+	return rtn;
+}
+ZXIC_RTN32 zxic_comm_indexfill_clear(INDEX_FILL_CFG *p_fill_cfg)
+{
+	ZXIC_UINT32 rtn = 0;
+	ZXIC_UINT32 key_len = p_fill_cfg->fill_rb.key_size;
+	ZXIC_KEY_CMP_FUNC p_cmp_fun = p_fill_cfg->fill_rb.p_cmpfun;
+	INDEX_FILL_NODE *fill_node;
+	D_NODE *p_curnode = NULL;
+	void *cur_data;
+	p_curnode = p_fill_cfg->fill_rb.tn_list.p_next;
+
+	while (p_curnode) {
+		cur_data = p_curnode->data;
+		p_curnode = p_curnode->next;
+		fill_node = cur_data;
+		ZXIC_COMM_FREE(fill_node->rb_node.p_key);
+		ZXIC_COMM_FREE(fill_node);
+	}
+
+	rtn = zxic_comm_rb_destroy(&p_fill_cfg->fill_rb);
+	ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_destroy");
+
+	rtn = zxic_comm_rb_init(&p_fill_cfg->fill_rb, 0, key_len, p_cmp_fun);
+	ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_init");
+
+	p_fill_cfg->total_used = 0;
+
+	return ZXIC_OK;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_liststack.c b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_liststack.c
index ae40a07660129505df03b90e70c5aacf112ff17f..1fff18db3d312f5af7ca40eaa5a954eacd1976be 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_liststack.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_liststack.c
@@ -1,431 +1,384 @@
-/*****************************************************************************
- * 版权所有 (C)2001-2006, 深圳市中兴通讯股份有限公司。
- * 
- * 文件名称：   Rtm_ListStack.c
- * 文件标识：    
- * 内容摘要：   链表栈管理文件
- 
- * 其它说明：   链表栈的管理方式，后进先出,释放的元素挂到队头
-               
- * 当前版本：    ZXR10 V2.6
- * 作    者：    郑纪伟
- * 完成日期：    2006-9-27 10:34
- * 当前责任人-1：
- * 当前责任人-2：
- *
- * 修改记录1：   
- *    修改日期：2006-9-27 10:34
- *    版 本 号：ZXR10 V2.6
- *    修 改 人：郑纪伟
- *    修改内容：创建 
- *
- * 修改记录2：
- *    文件名称：ftmcomm_liststack.c
- *    修改日期：2008-10-16 15:08
- *    版 本 号：ZXR10 V2.6
- *    修 改 人：HuangHe 170389
- *    修改内容：移植到T8000项目使用 
- *
- *修改记录3：
- *    修改文件名称：zxic_liststack.c
- *    修改日期：2012-03-15 15:14
- *    版 本 号：ZXR10 V2.6
- *    修 改 人：JiangWenming 12010401
- *    修改内容：移植到NSE项目使用 
- *
- *****************************************************************************/
-#include "zxic_common.h"
-
-
-ZXIC_RTN32 zxic_comm_liststack_creat(ZXIC_UINT32 element_num, ZXIC_LISTSTACK_MANGER** p_list)
-{
-    ZXIC_LISTSTACK_MANGER* p_local_list = NULL;
-    ZXIC_UINT32 dw_list_size = 0;
-    ZXIC_UINT32 dw_manage_size = 0;
-    ZXIC_UINT32 dw_actual_element_num = 0; 
-    ZXIC_UINT32 i = 0;
-    
-    /*611002174859 zj068187 检查双重指针*/
-    if (NULL == p_list)
-    {
-        ZXIC_COMM_PRINT("\n p_list is NULL!\n");
-        return ZXIC_LIST_STACK_POINT_NULL;
-        
-    }     
-    if(element_num <= 0)
-    {
-        *p_list = NULL;
-        ZXIC_COMM_PRINT( "\n FtmComm_ListStackCreat_dwElementNum <=0"); 
-        return ZXIC_LIST_STACK_ELEMENT_NUM_ERR;
-        
-    }
-
-    if(element_num>LISTSTACK_MAX_ELEMENT-1)
-    {
-        dw_actual_element_num = LISTSTACK_MAX_ELEMENT;
-    }
-    else
-    {
-        dw_actual_element_num = element_num + 1; /*10124041 index from 0*/
-    }
-     
-
-
-    dw_list_size = (dw_actual_element_num * ZXIC_SIZEOF(ZXIC_COMM_FREELINK))&0xffffffff;
-    dw_manage_size = (ZXIC_SIZEOF(ZXIC_LISTSTACK_MANGER) + dw_list_size)&0xffffffff;
-
-    p_local_list = (ZXIC_LISTSTACK_MANGER*)ZXIC_COMM_MALLOC(dw_manage_size);
-     
-    if(p_local_list == NULL)
-    {
-        *p_list = NULL;
-        ZXIC_COMM_PRINT( "\n zxic_comm_liststack_creat Fail \n");
-        return ZXIC_LIST_STACK_ALLOC_MEMORY_FAIL;
-        
-    }
-
-    ZXIC_COMM_MEMSET(p_local_list,0,dw_manage_size);
-
-    p_local_list->p_array = (ZXIC_COMM_FREELINK*)((ZXIC_UINT8 *)p_local_list+ZXIC_SIZEOF(ZXIC_LISTSTACK_MANGER));
-
-    p_local_list->capacity = dw_actual_element_num;
-    p_local_list->free_num = dw_actual_element_num - 1; /* for index = 0 is reserved */
-    p_local_list->used_num = 0;
-
-    for(i=1; i<(dw_actual_element_num-1); i++)
-    {
-        p_local_list->p_array[i].index = i;
-        p_local_list->p_array[i].next = i+1;
-    }
-
-    p_local_list->p_array[0].index = 0;
-    p_local_list->p_array[0].next =  0;
-
-    p_local_list->p_array[dw_actual_element_num-1].index = dw_actual_element_num-1;
-    p_local_list->p_array[dw_actual_element_num-1].next = 0xffffffff;
-
-    p_local_list->p_head = p_local_list->p_array[1].index;
-     
-    *p_list = p_local_list; 
-
-    return ZXIC_OK;
-
-}
-
-
-ZXIC_RTN32 zxic_comm_liststack_alloc  (ZXIC_LISTSTACK_MANGER* p_list,ZXIC_UINT32 *p_index)
-{
-    ZXIC_UINT32 dw_alloc_index = 0;
-    ZXIC_UINT32 dw_next_free = 0;
-
-    if(p_list == NULL)
-    {
-        *p_index = LISTSTACK_INVALID_INDEX;        
-         ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc! ERROR LINE:%d\n ",__LINE__);
-         return ZXIC_LIST_STACK_POINT_NULL;
-        
-    }
-
-    if((p_list->p_head) == LISTSTACK_INVALID_INDEX)
-    {
-        *p_index = LISTSTACK_INVALID_INDEX;
-        
-        /*ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc is full!  LINE:%d\n ",__LINE__);*/
-         return ZXIC_LIST_STACK_ISEMPTY_ERR;
-      
-    }
-
-    dw_alloc_index = p_list->p_head;
-
-    dw_next_free = p_list->p_array[dw_alloc_index].next;
-    p_list->p_array[dw_alloc_index].next = LISTSTACK_INVALID_INDEX;
-    
-    if(dw_next_free != 0xffffffff) /* ZXIC_UINT32 - 1 为0xffffffff*/
-    {
-        p_list->p_head = p_list->p_array[dw_next_free].index;
-    }
-    else
-    {
-        p_list->p_head = LISTSTACK_INVALID_INDEX;
-    }
-
-    *p_index = dw_alloc_index - 1; /*减1是为了使索引从0开始分配*/
-
-    p_list->free_num--;
-    p_list->used_num++;
-
-    /*分配一个条目后，判断队列是否变为空，若变为空，则头指向无效索引*/
-    if((p_list->free_num == 0) || (p_list->used_num == (p_list->capacity-1)))
-    {
-        /*ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc! ERROR LINE:%d\n ",__LINE__);*/
-        p_list->p_head = LISTSTACK_INVALID_INDEX;
-    }
-    
-    return ZXIC_OK;    
-
-}
-
-ZXIC_RTN32 zxic_comm_liststack_free   (ZXIC_LISTSTACK_MANGER* p_list,ZXIC_UINT32 index)
-{
-    ZXIC_UINT32     dw_free_index = 0;
-    ZXIC_UINT32     dw_prev_free  = 0;
-    ZXIC_UINT32     dw_index      = 0;
-    
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(index, 1);
-    dw_index      = index + 1; /*加1是为了使索引从0开始分配*/
-
-    if(p_list == NULL)
-    {        
-        
-        ZXIC_COMM_PRINT("\n zxic_comm_liststack_free is null! LINE:%d\n ",__LINE__);
-        return ZXIC_LIST_STACK_POINT_NULL;
-    }
-
-    
-        
-    if (dw_index >= p_list->capacity)
-    {
-        
-        ZXIC_COMM_PRINT("\n zxic_comm_liststack_free is null! LINE:%d\n ",__LINE__);
-        return ZXIC_LIST_STACK_FREE_INDEX_INVALID;
-        
-    }
-
-    if(p_list->p_array[dw_index].next != LISTSTACK_INVALID_INDEX)
-    {
-        return ZXIC_OK;
-    }
-    
-    dw_free_index = dw_index;
-    dw_prev_free = p_list->p_head;
-
-    if(dw_prev_free != 0)
-    {
-        p_list->p_array[dw_free_index].next =  p_list->p_array[dw_prev_free].index;
-    }
-    else
-    {
-        p_list->p_array[dw_free_index].next = 0xffffffff;
-    }
-
-    /* 释放的元素挂到队头*/
-    p_list->p_head = p_list->p_array[dw_free_index].index;
-
-    p_list->free_num++;
-    p_list->used_num--;
-
-    return ZXIC_OK;
-
-}
-
-ZXIC_RTN32 zxic_comm_liststack_alloc_spec_index(ZXIC_LISTSTACK_MANGER* p_list, ZXIC_UINT32 index)
-{
-    ZXIC_UINT32 dw_free_index = 0;  
-    ZXIC_UINT32 dw_index      = 0;
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(index, 1);
-    dw_index = index + 1; //加1是为了使索引从0开始分配    
-    if(p_list == NULL)
-    {       
-         ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc_spec_index: address is full! ERROR LINE:%d\n ",__LINE__);
-         return ZXIC_LIST_STACK_POINT_NULL;
-    }
-
-    if((p_list->p_head) == LISTSTACK_INVALID_INDEX)
-    {
-         //ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc is full!  LINE:%d\n ",__LINE__);
-         return ZXIC_LIST_STACK_ISEMPTY_ERR;
-      
-    }
-
-    if(dw_index >= p_list->capacity)
-    {
-        ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc_spec_index: input invalid index! LINE:%d\n ",__LINE__);
-        return ZXIC_LIST_STACK_ALLOC_INDEX_INVALID;
-    }
-
-    if(p_list->p_array[dw_index].next == LISTSTACK_INVALID_INDEX)
-    {
-        ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc_spec_index: index is used, not alloc again! LINE:%d\n ",__LINE__);
-        return ZXIC_LIST_STACK_ALLOC_INDEX_USED;
-    }
-    else
-    {
-        if(p_list->p_head == dw_index)
-        {
-            if(p_list->p_array[dw_index].next != 0xffffffff)
-            {
-                p_list->p_head = p_list->p_array[dw_index].next;
-            }
-            else
-            {
-                p_list->p_head = LISTSTACK_INVALID_INDEX;
-            }
-        }
-        else
-        {
-            dw_free_index = p_list->p_head;
-            while(p_list->p_array[dw_free_index].next != 0xffffffff)
-            {
-                if(p_list->p_array[dw_free_index].next == dw_index)
-                {
-                    p_list->p_array[dw_free_index].next = p_list->p_array[dw_index].next;
-                    break;
-                }
-                dw_free_index = p_list->p_array[dw_free_index].next;
-            }
-        }
-
-        p_list->p_array[dw_index].next = LISTSTACK_INVALID_INDEX;
-        p_list->free_num--;
-        p_list->used_num++;
-    }
-
-    /*分配一个条目后，判断队列是否变为空，若变为空，则头指向无效索引*/
-    if((p_list->free_num == 0) || (p_list->used_num == (p_list->capacity-1)))
-    {
-        //ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc! ERROR LINE:%d\n ",__LINE__);
-        p_list->p_head = LISTSTACK_INVALID_INDEX;
-    }
-    
-    return ZXIC_OK;    
-
-}
-
-
-ZXIC_RTN32 zxic_comm_liststack_destroy(ZXIC_LISTSTACK_MANGER* p_list)
-{    
-    if(p_list == NULL)
-    {              
-        ZXIC_COMM_PRINT("\n zxic_comm_liststack_destroy! LINE:%d\n ",__LINE__);
-        return ZXIC_LIST_STACK_POINT_NULL;        
-    }
-    ZXIC_COMM_FREE(p_list);
-
-    return ZXIC_OK;
-
-}
-
-ZXIC_RTN32 zxic_comm_liststack_showlist_info (ZXIC_LISTSTACK_MANGER* p_list)
-{
-    ZXIC_COMM_PRINT( "\n\t List:     0x%p",      (void*)p_list   );
-    ZXIC_COMM_PRINT( "\n\t Array:    0x%p",      (void*)p_list->p_array  );
-    ZXIC_COMM_PRINT( "\n\t capacity: 0x%x",      p_list->capacity );
-    ZXIC_COMM_PRINT( "\n\t p_head:   0x%x",      p_list->p_head   );
-    ZXIC_COMM_PRINT( "\n\t free_num: 0x%x",      p_list->free_num );
-    ZXIC_COMM_PRINT( "\n\t used_num: 0x%x\n",    p_list->used_num );
-    
-    return 0;
-}
-
-ZXIC_RTN32 zxic_comm_liststack_show_used(ZXIC_LISTSTACK_MANGER* p_list, ZXIC_UINT32 line_number )
-{
-    ZXIC_RTN32 rc = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 used_number = 0;
-    ZXIC_UINT32 dw_index = 0;
-    ZXIC_UINT32 dw_last_free_idx = 0;
-
-    if(p_list == NULL)
-    {
-        ZXIC_COMM_PRINT ( "\n Please Input Param!" );
-        return 0;
-    }
-
-    if ( line_number == 0 )
-    {
-        line_number = 32;
-    }
-
-    rc = zxic_comm_liststack_showlist_info ( p_list );
-    ZXIC_COMM_CHECK_RC(rc, "zxic_comm_liststack_showlist_info");
-    ZXIC_COMM_PRINT ( "\n" );
-
-    /*611002175032 zj068187 begin*/
-    if(LISTSTACK_INVALID_INDEX == p_list->p_head)
-    {
-        ZXIC_COMM_PRINT("\n The index are all used!\n");
-    }
-    
-    dw_index = p_list->p_head;
-    ZXIC_COMM_CHECK_INDEX_UPPER(dw_index, (p_list->capacity - 1));
-    while(LISTSTACK_INVALID_INDEX != p_list->p_array[dw_index].next)
-    { 
-        dw_index = p_list->p_array[dw_index].next;
-        ZXIC_COMM_CHECK_INDEX_UPPER(dw_index, (p_list->capacity - 1));      
-    }
-
-    dw_last_free_idx = p_list->p_array[dw_index].index;
-    /*611002175032 zj068187 end*/
-
-      for ( i = 1; i < p_list->capacity; i++ )
-      {
-            /*611002175032 zj068187 modify*/
-            if((LISTSTACK_INVALID_INDEX == p_list->p_array[i].next)
-                &&(dw_last_free_idx != p_list->p_array[i].index))
-            {
-                  ZXIC_COMM_PRINT ( " 0x%x", i );
-                  used_number++;
-
-                  if ( ( used_number % line_number ) == 0 )
-                  {
-                        ZXIC_COMM_PRINT ( "\n" );
-                  }
-            }
-      }
-
-      ZXIC_COMM_PRINT ( "\n used_number: 0x%x", used_number );
-
-      return ZXIC_OK;
-}
-
-ZXIC_RTN32 zxic_comm_liststack_show_free (ZXIC_LISTSTACK_MANGER* p_list, ZXIC_UINT32 line_number )
-{
-      ZXIC_RTN32 rc = 0;
-      ZXIC_UINT32 i = 0;
-      ZXIC_UINT32 index = 0;
-      ZXIC_UINT32 free_number = 0;
-
-      if(p_list == NULL)
-      {
-            ZXIC_COMM_PRINT ( "\n Please Input Param!" );
-            return 0;
-      }
-
-      if ( line_number == 0 )
-      {
-            line_number = 32;
-      }
-
-      rc = zxic_comm_liststack_showlist_info ( p_list );
-      ZXIC_COMM_CHECK_RC(rc, "zxic_comm_liststack_showlist_info");
-      ZXIC_COMM_PRINT ( "\n" );
-
-      index = p_list->p_head;
-
-      for ( i = p_list->capacity - 1; i != 0; i-- )
-      {
-            if ( index != LISTSTACK_INVALID_INDEX )
-            {
-                  ZXIC_COMM_PRINT ( " 0x%x", index );
-                  free_number++;
-
-                  index = p_list->p_array[index].next;
-
-                  if ( ( free_number % line_number ) == 0 )
-                  {
-                        ZXIC_COMM_PRINT ( "\n" );
-                  }
-            }
-            else
-            {
-                  break;
-            }
-      }
-
-      ZXIC_COMM_PRINT ( "\n free_number: 0x%x", free_number );
-
-      return ZXIC_OK;
-}
-
-
+/*****************************************************************************
+ * 版权所有 (C)2001-2006, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：   Rtm_ListStack.c
+ * 文件标识：
+ * 内容摘要：   链表栈管理文件
+
+ * 其它说明：   链表栈的管理方式，后进先出,释放的元素挂到队头
+
+ * 当前版本：    ZXR10 V2.6
+ * 作    者：    郑纪伟
+ * 完成日期：    2006-9-27 10:34
+ * 当前责任人-1：
+ * 当前责任人-2：
+ *
+ * 修改记录1：
+ *    修改日期：2006-9-27 10:34
+ *    版 本 号：ZXR10 V2.6
+ *    修 改 人：郑纪伟
+ *    修改内容：创建
+ *
+ * 修改记录2：
+ *    文件名称：ftmcomm_liststack.c
+ *    修改日期：2008-10-16 15:08
+ *    版 本 号：ZXR10 V2.6
+ *    修 改 人：HuangHe 170389
+ *    修改内容：移植到T8000项目使用
+ *
+ *修改记录3：
+ *    修改文件名称：zxic_liststack.c
+ *    修改日期：2012-03-15 15:14
+ *    版 本 号：ZXR10 V2.6
+ *    修 改 人：JiangWenming 12010401
+ *    修改内容：移植到NSE项目使用
+ *
+ *****************************************************************************/
+#include "zxic_common.h"
+
+ZXIC_RTN32 zxic_comm_liststack_creat(ZXIC_UINT32 element_num,
+									 ZXIC_LISTSTACK_MANGER **p_list)
+{
+	ZXIC_LISTSTACK_MANGER *p_local_list = NULL;
+	ZXIC_UINT32 dw_list_size = 0;
+	ZXIC_UINT32 dw_manage_size = 0;
+	ZXIC_UINT32 dw_actual_element_num = 0;
+	ZXIC_UINT32 i = 0;
+
+	/*611002174859 zj068187 检查双重指针*/
+	if (NULL == p_list) {
+		ZXIC_COMM_PRINT("\n p_list is NULL!\n");
+		return ZXIC_LIST_STACK_POINT_NULL;
+	}
+	if (element_num <= 0) {
+		*p_list = NULL;
+		ZXIC_COMM_PRINT("\n FtmComm_ListStackCreat_dwElementNum <=0");
+		return ZXIC_LIST_STACK_ELEMENT_NUM_ERR;
+	}
+
+	if (element_num > LISTSTACK_MAX_ELEMENT - 1) {
+		dw_actual_element_num = LISTSTACK_MAX_ELEMENT;
+	} else {
+		dw_actual_element_num = element_num + 1; /*10124041 index from 0*/
+	}
+
+	dw_list_size = (dw_actual_element_num * ZXIC_SIZEOF(ZXIC_COMM_FREELINK)) &
+				   0xffffffff;
+	dw_manage_size = (ZXIC_SIZEOF(ZXIC_LISTSTACK_MANGER) + dw_list_size) &
+					 0xffffffff;
+
+	p_local_list = (ZXIC_LISTSTACK_MANGER *)ZXIC_COMM_MALLOC(dw_manage_size);
+
+	if (p_local_list == NULL) {
+		*p_list = NULL;
+		ZXIC_COMM_PRINT("\n zxic_comm_liststack_creat Fail \n");
+		return ZXIC_LIST_STACK_ALLOC_MEMORY_FAIL;
+	}
+
+	ZXIC_COMM_MEMSET(p_local_list, 0, dw_manage_size);
+
+	p_local_list->p_array =
+			(ZXIC_COMM_FREELINK *)((ZXIC_UINT8 *)p_local_list +
+								   ZXIC_SIZEOF(ZXIC_LISTSTACK_MANGER));
+
+	p_local_list->capacity = dw_actual_element_num;
+	p_local_list->free_num =
+			dw_actual_element_num - 1; /* for index = 0 is reserved */
+	p_local_list->used_num = 0;
+
+	for (i = 1; i < (dw_actual_element_num - 1); i++) {
+		p_local_list->p_array[i].index = i;
+		p_local_list->p_array[i].next = i + 1;
+	}
+
+	p_local_list->p_array[0].index = 0;
+	p_local_list->p_array[0].next = 0;
+
+	p_local_list->p_array[dw_actual_element_num - 1].index =
+			dw_actual_element_num - 1;
+	p_local_list->p_array[dw_actual_element_num - 1].next = 0xffffffff;
+
+	p_local_list->p_head = p_local_list->p_array[1].index;
+
+	*p_list = p_local_list;
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_liststack_alloc(ZXIC_LISTSTACK_MANGER *p_list,
+									 ZXIC_UINT32 *p_index)
+{
+	ZXIC_UINT32 dw_alloc_index = 0;
+	ZXIC_UINT32 dw_next_free = 0;
+
+	if (p_list == NULL) {
+		*p_index = LISTSTACK_INVALID_INDEX;
+		ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc! ERROR LINE:%d\n ",
+						__LINE__);
+		return ZXIC_LIST_STACK_POINT_NULL;
+	}
+
+	if ((p_list->p_head) == LISTSTACK_INVALID_INDEX) {
+		*p_index = LISTSTACK_INVALID_INDEX;
+
+		/*ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc is full!  LINE:%d\n ",__LINE__);*/
+		return ZXIC_LIST_STACK_ISEMPTY_ERR;
+	}
+
+	dw_alloc_index = p_list->p_head;
+
+	dw_next_free = p_list->p_array[dw_alloc_index].next;
+	p_list->p_array[dw_alloc_index].next = LISTSTACK_INVALID_INDEX;
+
+	if (dw_next_free != 0xffffffff) { /* ZXIC_UINT32 - 1 为0xffffffff*/
+		p_list->p_head = p_list->p_array[dw_next_free].index;
+	} else {
+		p_list->p_head = LISTSTACK_INVALID_INDEX;
+	}
+
+	*p_index = dw_alloc_index - 1; /*减1是为了使索引从0开始分配*/
+
+	p_list->free_num--;
+	p_list->used_num++;
+
+	/*分配一个条目后，判断队列是否变为空，若变为空，则头指向无效索引*/
+	if ((p_list->free_num == 0) ||
+		(p_list->used_num == (p_list->capacity - 1))) {
+		/*ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc! ERROR LINE:%d\n ",__LINE__);*/
+		p_list->p_head = LISTSTACK_INVALID_INDEX;
+	}
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_liststack_free(ZXIC_LISTSTACK_MANGER *p_list,
+									ZXIC_UINT32 index)
+{
+	ZXIC_UINT32 dw_free_index = 0;
+	ZXIC_UINT32 dw_prev_free = 0;
+	ZXIC_UINT32 dw_index = 0;
+
+	ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(index, 1);
+	dw_index = index + 1; /*加1是为了使索引从0开始分配*/
+
+	if (p_list == NULL) {
+		ZXIC_COMM_PRINT("\n zxic_comm_liststack_free is null! LINE:%d\n ",
+						__LINE__);
+		return ZXIC_LIST_STACK_POINT_NULL;
+	}
+
+	if (dw_index >= p_list->capacity) {
+		ZXIC_COMM_PRINT("\n zxic_comm_liststack_free is null! LINE:%d\n ",
+						__LINE__);
+		return ZXIC_LIST_STACK_FREE_INDEX_INVALID;
+	}
+
+	if (p_list->p_array[dw_index].next != LISTSTACK_INVALID_INDEX) {
+		return ZXIC_OK;
+	}
+
+	dw_free_index = dw_index;
+	dw_prev_free = p_list->p_head;
+
+	if (dw_prev_free != 0) {
+		p_list->p_array[dw_free_index].next =
+				p_list->p_array[dw_prev_free].index;
+	} else {
+		p_list->p_array[dw_free_index].next = 0xffffffff;
+	}
+
+	/* 释放的元素挂到队头*/
+	p_list->p_head = p_list->p_array[dw_free_index].index;
+
+	p_list->free_num++;
+	p_list->used_num--;
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_liststack_alloc_spec_index(ZXIC_LISTSTACK_MANGER *p_list,
+												ZXIC_UINT32 index)
+{
+	ZXIC_UINT32 dw_free_index = 0;
+	ZXIC_UINT32 dw_index = 0;
+
+	ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(index, 1);
+	dw_index = index + 1; //加1是为了使索引从0开始分配
+	if (p_list == NULL) {
+		ZXIC_COMM_PRINT(
+				"\n zxic_comm_liststack_alloc_spec_index: address is full! ERROR LINE:%d\n ",
+				__LINE__);
+		return ZXIC_LIST_STACK_POINT_NULL;
+	}
+
+	if ((p_list->p_head) == LISTSTACK_INVALID_INDEX) {
+		// ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc is full!  LINE:%d\n ",__LINE__);
+		return ZXIC_LIST_STACK_ISEMPTY_ERR;
+	}
+
+	if (dw_index >= p_list->capacity) {
+		ZXIC_COMM_PRINT(
+				"\n zxic_comm_liststack_alloc_spec_index: input invalid index! LINE:%d\n ",
+				__LINE__);
+		return ZXIC_LIST_STACK_ALLOC_INDEX_INVALID;
+	}
+
+	if (p_list->p_array[dw_index].next == LISTSTACK_INVALID_INDEX) {
+		ZXIC_COMM_PRINT(
+				"\n zxic_comm_liststack_alloc_spec_index: index is used, not alloc again! LINE:%d\n ",
+				__LINE__);
+		return ZXIC_LIST_STACK_ALLOC_INDEX_USED;
+	} else {
+		if (p_list->p_head == dw_index) {
+			if (p_list->p_array[dw_index].next != 0xffffffff) {
+				p_list->p_head = p_list->p_array[dw_index].next;
+			} else {
+				p_list->p_head = LISTSTACK_INVALID_INDEX;
+			}
+		} else {
+			dw_free_index = p_list->p_head;
+			while (p_list->p_array[dw_free_index].next != 0xffffffff) {
+				if (p_list->p_array[dw_free_index].next == dw_index) {
+					p_list->p_array[dw_free_index].next =
+							p_list->p_array[dw_index].next;
+					break;
+				}
+				dw_free_index = p_list->p_array[dw_free_index].next;
+			}
+		}
+
+		p_list->p_array[dw_index].next = LISTSTACK_INVALID_INDEX;
+		p_list->free_num--;
+		p_list->used_num++;
+	}
+
+	/*分配一个条目后，判断队列是否变为空，若变为空，则头指向无效索引*/
+	if ((p_list->free_num == 0) ||
+		(p_list->used_num == (p_list->capacity - 1))) {
+		// ZXIC_COMM_PRINT("\n zxic_comm_liststack_alloc! ERROR LINE:%d\n ",__LINE__);
+		p_list->p_head = LISTSTACK_INVALID_INDEX;
+	}
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_liststack_destroy(ZXIC_LISTSTACK_MANGER *p_list)
+{
+	if (p_list == NULL) {
+		ZXIC_COMM_PRINT("\n zxic_comm_liststack_destroy! LINE:%d\n ", __LINE__);
+		return ZXIC_LIST_STACK_POINT_NULL;
+	}
+	ZXIC_COMM_FREE(p_list);
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_liststack_showlist_info(ZXIC_LISTSTACK_MANGER *p_list)
+{
+	ZXIC_COMM_PRINT("\n\t List:     0x%p", (void *)p_list);
+	ZXIC_COMM_PRINT("\n\t Array:    0x%p", (void *)p_list->p_array);
+	ZXIC_COMM_PRINT("\n\t capacity: 0x%x", p_list->capacity);
+	ZXIC_COMM_PRINT("\n\t p_head:   0x%x", p_list->p_head);
+	ZXIC_COMM_PRINT("\n\t free_num: 0x%x", p_list->free_num);
+	ZXIC_COMM_PRINT("\n\t used_num: 0x%x\n", p_list->used_num);
+
+	return 0;
+}
+
+ZXIC_RTN32 zxic_comm_liststack_show_used(ZXIC_LISTSTACK_MANGER *p_list,
+										 ZXIC_UINT32 line_number)
+{
+	ZXIC_RTN32 rc = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 used_number = 0;
+	ZXIC_UINT32 dw_index = 0;
+	ZXIC_UINT32 dw_last_free_idx = 0;
+
+	if (p_list == NULL) {
+		ZXIC_COMM_PRINT("\n Please Input Param!");
+		return 0;
+	}
+
+	if (line_number == 0) {
+		line_number = 32;
+	}
+
+	rc = zxic_comm_liststack_showlist_info(p_list);
+	ZXIC_COMM_CHECK_RC(rc, "zxic_comm_liststack_showlist_info");
+	ZXIC_COMM_PRINT("\n");
+
+	/*611002175032 zj068187 begin*/
+	if (LISTSTACK_INVALID_INDEX == p_list->p_head) {
+		ZXIC_COMM_PRINT("\n The index are all used!\n");
+	}
+
+	dw_index = p_list->p_head;
+	ZXIC_COMM_CHECK_INDEX_UPPER(dw_index, (p_list->capacity - 1));
+	while (LISTSTACK_INVALID_INDEX != p_list->p_array[dw_index].next) {
+		dw_index = p_list->p_array[dw_index].next;
+		ZXIC_COMM_CHECK_INDEX_UPPER(dw_index, (p_list->capacity - 1));
+	}
+
+	dw_last_free_idx = p_list->p_array[dw_index].index;
+	/*611002175032 zj068187 end*/
+
+	for (i = 1; i < p_list->capacity; i++) {
+		/*611002175032 zj068187 modify*/
+		if ((LISTSTACK_INVALID_INDEX == p_list->p_array[i].next) &&
+			(dw_last_free_idx != p_list->p_array[i].index)) {
+			ZXIC_COMM_PRINT(" 0x%x", i);
+			used_number++;
+
+			if ((used_number % line_number) == 0) {
+				ZXIC_COMM_PRINT("\n");
+			}
+		}
+	}
+
+	ZXIC_COMM_PRINT("\n used_number: 0x%x", used_number);
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_liststack_show_free(ZXIC_LISTSTACK_MANGER *p_list,
+										 ZXIC_UINT32 line_number)
+{
+	ZXIC_RTN32 rc = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 free_number = 0;
+
+	if (p_list == NULL) {
+		ZXIC_COMM_PRINT("\n Please Input Param!");
+		return 0;
+	}
+
+	if (line_number == 0) {
+		line_number = 32;
+	}
+
+	rc = zxic_comm_liststack_showlist_info(p_list);
+	ZXIC_COMM_CHECK_RC(rc, "zxic_comm_liststack_showlist_info");
+	ZXIC_COMM_PRINT("\n");
+
+	index = p_list->p_head;
+
+	for (i = p_list->capacity - 1; i != 0; i--) {
+		if (index != LISTSTACK_INVALID_INDEX) {
+			ZXIC_COMM_PRINT(" 0x%x", index);
+			free_number++;
+
+			index = p_list->p_array[index].next;
+
+			if ((free_number % line_number) == 0) {
+				ZXIC_COMM_PRINT("\n");
+			}
+		} else {
+			break;
+		}
+	}
+
+	ZXIC_COMM_PRINT("\n free_number: 0x%x", free_number);
+
+	return ZXIC_OK;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_mutex_lock.c b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_mutex_lock.c
index 91529d77eac4b817c9dd68bd61aed7881776267d..c2a0b405a3b22a6715a66b2ccee54bba1def6f99 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_mutex_lock.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_mutex_lock.c
@@ -1,179 +1,100 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : zxic_sal.c
-* 文件标识 : 
-* 内容摘要 : 
-* 其它说明 : 
-* 当前版本 : 
-* 作    者 : 王春雷
-* 完成日期 : 2014/02/07
-* DEPARTMENT: ASIC_FPGA_R&D_Dept 
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* 版 本 号:  
-* 修 改 人:  
-* 修改内容:  
-***************************************************************/
-
-#include "zxic_common.h"
-#include "zxic_private.h"
-
-#ifdef ZXIC_OS_WIN
-#define ZXIC_MUTEX_WAITTIME_MAX       (INFINITE)  /* 互斥锁最大等待时间 */
-#else
-#define ZXIC_MUTEX_WAITTIME_MAX       (5000)  /* 互斥锁最大等待时间:5000ms */
-#endif
-
-/***********************************************************/
-/** 初始化互斥量
-* @param   p_mutex 互斥量   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  王春雷      @date  2014/02/07
-************************************************************/
-ZXIC_RTN32 zxic_comm_mutex_create(ZXIC_MUTEX_T *p_mutex)
-{
-    // ZXIC_SINT32 rc = 0;
-    
-    ZXIC_COMM_CHECK_POINT(p_mutex);
-    
-#ifdef ZXIC_OS_WIN
-    p_mutex->mutex = CreateMutex(ZXIC_NULL, ZXIC_FALSE, ZXIC_NULL);
-    if(p_mutex->mutex == 0)
-    {
-        ZXIC_COMM_TRACE_ERROR("\nErrCode[ 0x%x ]: Create mutex failed.", ZXIC_MUTEX_LOCK_INIT_FAIL);
-        return ZXIC_MUTEX_LOCK_INIT_FAIL;
-    }
-#else
-    /*rc = pthread_mutex_init(&p_mutex->mutex, NULL);
-    if(rc != 0)
-    {
-        ZXIC_COMM_TRACE_ERROR("\nErrCode[ 0x%x ]: Create mutex failed", ZXIC_MUTEX_LOCK_INIT_FAIL);
-        return ZXIC_MUTEX_LOCK_INIT_FAIL;
-    }*/
-    mutex_init(&p_mutex->mutex);
-#endif
-
-    return ZXIC_OK;
-}
-
-/***********************************************************/
-/** 互斥量加锁
-* @param   p_mutex   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  王春雷      @date  2014/02/07
-************************************************************/
-ZXIC_RTN32 zxic_comm_mutex_lock(ZXIC_MUTEX_T *p_mutex)
-{
-    ZXIC_SINT32 rc = 0; 
-#ifndef ZXIC_FOR_FUZZER    
-    ZXIC_COMM_CHECK_POINT(p_mutex);
-    
-    #ifdef ZXIC_OS_WIN
-        switch(WaitForSingleObject(p_mutex->mutex, ZXIC_MUTEX_WAITTIME_MAX))
-        {
-            case (WAIT_OBJECT_0):
-            {
-                /* wait mutex success. */
-                break;
-            }
-            default:
-            {
-                ZXIC_COMM_TRACE_ERROR("\nErrCode[ 0x%x ]: WaitForSingleObject failed.", ZXIC_MUTEX_LOCK_LOCK_FAIL);
-                ZXIC_COMM_ASSERT(0);
-                return ZXIC_MUTEX_LOCK_LOCK_FAIL;
-            }
-        }
-    #else
-        /*rc = pthread_mutex_lock(&p_mutex->mutex);
-        if(rc != 0)
-        {
-            ZXIC_COMM_TRACE_ERROR("\nErrCode[ 0x%x ]: Get mutex lock fail.", ZXIC_MUTEX_LOCK_LOCK_FAIL);
-            //ZXIC_COMM_ASSERT(0);
-            //return ZXIC_MUTEX_LOCK_LOCK_FAIL;
-            return rc;
-        }*/
-        mutex_lock(&p_mutex->mutex);
-    #endif
-#endif
-
-    return rc;
-}
-
-/***********************************************************/
-/** 互斥量解锁
-* @param   p_mutex   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  王春雷      @date  2014/02/07
-************************************************************/
-ZXIC_RTN32 zxic_comm_mutex_unlock(ZXIC_MUTEX_T *p_mutex)
-{
-    ZXIC_SINT32 rc = 0; 
-#ifndef ZXIC_FOR_FUZZER 
-
-    ZXIC_COMM_CHECK_POINT(p_mutex);
-        
-    #ifdef ZXIC_OS_WIN
-        if(!ReleaseMutex(p_mutex->mutex))
-        {
-            ZXIC_COMM_TRACE_ERROR("\nErrCode[ 0x%x ]: ReleaseMutex failed.", ZXIC_MUTEX_LOCK_ULOCK_FAIL);
-            return ZXIC_MUTEX_LOCK_ULOCK_FAIL;
-        }
-    #else
-        /*rc = pthread_mutex_unlock(&p_mutex->mutex);
-        if(rc != 0)
-        {
-            ZXIC_COMM_TRACE_ERROR("\nErrCode[ 0x%x ]: Release mutex lock fail.", ZXIC_MUTEX_LOCK_ULOCK_FAIL);
-            return ZXIC_MUTEX_LOCK_ULOCK_FAIL;
-        }*/
-        mutex_unlock(&p_mutex->mutex);
-    #endif
-#endif
-
-    return rc;
-}
-
-/***********************************************************/
-/** 销毁互斥量
-* @param   p_mutex   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  王春雷      @date  2014/02/07
-************************************************************/
-ZXIC_RTN32 zxic_comm_mutex_destroy(ZXIC_MUTEX_T *p_mutex)
-{
-    // ZXIC_SINT32 rc = 0;
-    
-    ZXIC_COMM_CHECK_POINT(p_mutex);
-    
-#ifdef ZXIC_OS_WIN
-    if(p_mutex->mutex == 0)
-    {
-        ZXIC_COMM_TRACE_ERROR("\nErrCode[ 0x%x ]: Destroy mutex failed.", ZXIC_MUTEX_LOCK_DESTROY_FAIL);
-        return ZXIC_MUTEX_LOCK_DESTROY_FAIL;
-    }
-    CloseHandle(p_mutex->mutex);
-#else
-    /*rc = pthread_mutex_destroy(&p_mutex->mutex);
-    if(rc != 0)
-    {
-        ZXIC_COMM_TRACE_ERROR("\nErrCode[ 0x%x ]: Destroy mutex fail", ZXIC_MUTEX_LOCK_DESTROY_FAIL);
-        return ZXIC_MUTEX_LOCK_DESTROY_FAIL;
-    }*/
-    mutex_destroy(&p_mutex->mutex);
-#endif
-
-    return ZXIC_OK;
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : zxic_sal.c
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2014/02/07
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#include "zxic_common.h"
+#include "zxic_private.h"
+
+#define ZXIC_MUTEX_WAITTIME_MAX (5000) /* 互斥锁最大等待时间:5000ms */
+
+/***********************************************************/
+/** 初始化互斥量
+ * @param   p_mutex 互斥量
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/02/07
+ ************************************************************/
+ZXIC_RTN32 zxic_comm_mutex_create(ZXIC_MUTEX_T *p_mutex)
+{
+	// ZXIC_SINT32 rc = 0;
+
+	ZXIC_COMM_CHECK_POINT(p_mutex);
+
+	mutex_init(&p_mutex->mutex);
+
+	return ZXIC_OK;
+}
+
+/***********************************************************/
+/** 互斥量加锁
+ * @param   p_mutex
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/02/07
+ ************************************************************/
+ZXIC_RTN32 zxic_comm_mutex_lock(ZXIC_MUTEX_T *p_mutex)
+{
+	ZXIC_SINT32 rc = 0;
+
+	ZXIC_COMM_CHECK_POINT(p_mutex);
+	mutex_lock(&p_mutex->mutex);
+
+	return rc;
+}
+
+/***********************************************************/
+/** 互斥量解锁
+ * @param   p_mutex
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/02/07
+ ************************************************************/
+ZXIC_RTN32 zxic_comm_mutex_unlock(ZXIC_MUTEX_T *p_mutex)
+{
+	ZXIC_SINT32 rc = 0;
+
+	ZXIC_COMM_CHECK_POINT(p_mutex);
+	mutex_unlock(&p_mutex->mutex);
+
+	return rc;
+}
+
+/***********************************************************/
+/** 销毁互斥量
+ * @param   p_mutex
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/02/07
+ ************************************************************/
+ZXIC_RTN32 zxic_comm_mutex_destroy(ZXIC_MUTEX_T *p_mutex)
+{
+	// ZXIC_SINT32 rc = 0;
+
+	ZXIC_COMM_CHECK_POINT(p_mutex);
+	mutex_destroy(&p_mutex->mutex);
+
+	return ZXIC_OK;
 }
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_print.c b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_print.c
index 64a6f7437ebae9639bf0cc65bb367f9cf8e63360..2000bd6041b39d77724e33302f21829e6c23e83b 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_print.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_print.c
@@ -1,446 +1,457 @@
-/**************************************************************
-* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司
-* 文件名称 : zxic_comm_print.c
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者   : xuchenxi_10235594
-* 完成日期 : 2020/07/20
-* DEPARTMENT: 有线开发四部-系统软件团队
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-#include "zxic_common.h"
-#include "zxic_private.h"
-#include "log.h"
-
-#if ZXIC_REAL("全局变量定义")
-ZXIC_UINT32  g_zxic_print_level        = ZXIC_TRACE_ERROR_PRINT;    /*打印级别,默认为INFO*/
-ZXIC_UINT32  g_zxic_print_en           = 1;                         /*界面打印控制开关*/
-#endif
-
-#if ZXIC_REAL("开关")
-/***********************************************************/
-/** 设置打印开关，决定ZXIC_COMM_PRINT等调试打印函数是否输出到屏幕
-* @param   enable  0-不打印到屏幕，1-打印到屏幕
-*
-* @return
-* @remark  无
-* @see
-* @author  zhaisyu      @date  2018/10/25
-************************************************************/
-ZXIC_VOID zxic_comm_set_print_en(ZXIC_UINT32 enable)
-{
-    g_zxic_print_en = enable;
-}
-
-ZXIC_RTN32 zxic_comm_get_print_en(ZXIC_VOID)
-{
-    return g_zxic_print_en;
-}
-
-/***********************************************************/
-/** 设置Debug打印级别
-* @param   debug_level 0打印级别最低，4打印级别最高，即打印的东西最多
-*
-* @return
-* @remark  无
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-ZXIC_VOID zxic_comm_set_print_level(ZXIC_UINT32 debug_level)
-{
-    g_zxic_print_level = debug_level;
-}
-
-/***********************************************************/
-/** 获取Debug打印级别
-* @param   ZXIC_VOID
-*
-* @return
-* @remark  无
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-ZXIC_RTN32 zxic_comm_get_print_level(ZXIC_VOID)
-{
-    return g_zxic_print_level;
-}
-
-#endif
-
-#if ZXIC_REAL("打印函数")
-ZXIC_VOID ZXIC_COMM_PRINT(ZXIC_CONST ZXIC_CHAR *format, ...)
-{
-    va_list   ap;
-    ZXIC_CHAR szBuffer[1024];
-
-    ZXIC_COMM_ASSERT(format);
-
-    va_start(ap, format);
-    {
-        ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), ZXIC_SIZEOF(szBuffer), format, ap);
-        if (g_zxic_print_en)
-        {
-            DH_LOG_INFO(MODULE_NP, "%s", szBuffer);
-        }
-    }
-    va_end(ap);
-}
-
-/***********************************************************/
-/** Error信息打印函数
-* @param   format
-*
-* @return
-* @remark  无
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-ZXIC_VOID ZXIC_COMM_TRACE_ERROR(ZXIC_CONST ZXIC_CHAR *format, ...)
-{
-    va_list   ap;
-    ZXIC_CHAR szBuffer[1024];
-
-    ZXIC_COMM_ASSERT(format);
-
-    if (zxic_comm_get_print_level() == 0 || zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT)
-    {
-        return;
-    }
-
-    va_start(ap, format);
-    {
-        ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), 1024, format, ap);
-        if (zxic_comm_get_print_en())
-        {
-            DH_LOG_ERR(MODULE_NP, "%s", szBuffer);
-        }
-    }
-    va_end(ap);
-}
-
-/***********************************************************/
-/** Info信息打印函数
-* @param   format
-*
-* @return
-* @remark  无
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-ZXIC_VOID ZXIC_COMM_TRACE_INFO(ZXIC_CONST ZXIC_CHAR *format, ...)
-{
-    va_list   ap;
-    ZXIC_CHAR szBuffer[1024];
-
-    ZXIC_COMM_ASSERT(format);
-
-    if (zxic_comm_get_print_level() == 0 || zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT)
-    {
-        return;
-    }
-
-    if (zxic_comm_get_print_level() >= ZXIC_TRACE_INFO_PRINT)
-    {
-        va_start(ap, format);
-        {
-            ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), 1024, format, ap);
-            if (zxic_comm_get_print_en())
-            {
-                DH_LOG_INFO(MODULE_NP, "%s", szBuffer);
-            }
-        }
-        va_end(ap);
-    }
-}
-
-/***********************************************************/
-/** Debug信息打印函数
-* @param   format
-*
-* @return
-* @remark  无
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-ZXIC_VOID ZXIC_COMM_TRACE_DEBUG(ZXIC_CONST ZXIC_CHAR *format, ...)
-{
-    va_list   ap;
-    ZXIC_CHAR szBuffer[1024];
-
-    ZXIC_COMM_ASSERT(format);
-
-    if (zxic_comm_get_print_level() == 0 || zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT)
-    {
-        return;
-    }
-
-    if (zxic_comm_get_print_level() >= ZXIC_TRACE_DEBUG_PRINT)
-    {
-        va_start(ap, format);
-        {
-            ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), 1024, format, ap);
-            if (zxic_comm_get_print_en())
-            {
-                DH_LOG_DEBUG(MODULE_NP, "%s", szBuffer);
-            }
-        }
-        va_end(ap);
-    }
-}
-
-/***********************************************************/
-/** 所有调试信息打印函数
-* @param   format
-*
-* @return
-* @remark  无
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-ZXIC_VOID ZXIC_COMM_TRACE_ALL(ZXIC_CONST ZXIC_CHAR *format, ...)
-{
-    va_list   ap;
-    ZXIC_CHAR szBuffer[1024];
-
-    ZXIC_COMM_ASSERT(format);
-
-    if (zxic_comm_get_print_level() == 0 || zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT)
-    {
-        return;
-    }
-
-    if (zxic_comm_get_print_level() >= ZXIC_TRACE_ALL_PRINT)
-    {
-        va_start(ap, format);
-        {
-            ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), 1024, format, ap);
-            if (zxic_comm_get_print_en())
-            {
-                DH_LOG_DEBUG(MODULE_NP, "%s", szBuffer);
-            }
-        }
-        va_end(ap);
-    }
-}
-
-/***********************************************************/
-/** 支持多芯片的Error信息打印函数
-*   打印级别为1及以上时执行打印
-* @param   dev_id
-* @param   format
-*
-* @return
-* @remark  无
-* @see
-* @author  xcx                  @date  2020/07/20
-************************************************************/
-ZXIC_VOID ZXIC_COMM_TRACE_DEV_ERROR(ZXIC_UINT32 dev_id, ZXIC_CONST ZXIC_CHAR *format, ...)
-{
-    va_list   ap;
-    ZXIC_CHAR szBuffer[768 - 32] = {0};
-    ZXIC_CHAR devBuffer[1024]    = {0};
-
-    ZXIC_COMM_ASSERT(format);
-
-    if (zxic_comm_get_print_level() == 0 || zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT || dev_id > 3)
-    {
-        return;
-    }
-
-    if (zxic_comm_get_print_level() >= ZXIC_TRACE_ERROR_PRINT)
-    {
-        ZXIC_COMM_SNPRINTF_S(devBuffer, ZXIC_SIZEOF(devBuffer), ZXIC_SIZEOF(devBuffer), "Dev_id[%u]_ERROR: ", dev_id);
-
-        va_start(ap, format);
-        {
-            ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), ZXIC_SIZEOF(szBuffer), format, ap);
-            ZXIC_COMM_STRNCAT_S(devBuffer, 1024, szBuffer, ZXIC_COMM_STRNLEN_S(szBuffer, ZXIC_SIZEOF(szBuffer)));
-
-            if (zxic_comm_get_print_en())
-            {
-                DH_LOG_ERR(MODULE_NP, "%s", devBuffer);
-            }
-        }
-        va_end(ap);
-    }
-}
-
-/***********************************************************/
-/** 支持多芯片的Info信息打印函数
-*   打印级别为2及以上时执行打印
-* @param   dev_id
-* @param   format
-*
-* @return
-* @remark  无
-* @see
-* @author  wcl                  @date  2018/09/08
-************************************************************/
-ZXIC_VOID ZXIC_COMM_TRACE_DEV_INFO(ZXIC_UINT32 dev_id, ZXIC_CONST ZXIC_CHAR *format, ...)
-{
-    va_list   ap;
-    ZXIC_CHAR szBuffer[768 - 32] = {0};
-    ZXIC_CHAR devBuffer[1024]    = {0};
-
-    ZXIC_COMM_ASSERT(format);
-
-    if (zxic_comm_get_print_level() == 0 || zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT || dev_id > 3)
-    {
-        return;
-    }
-
-    if (zxic_comm_get_print_level() >= ZXIC_TRACE_INFO_PRINT)
-    {
-        ZXIC_COMM_SNPRINTF_S(devBuffer, ZXIC_SIZEOF(devBuffer), ZXIC_SIZEOF(devBuffer), "Dev_id[%u]_INFO: ", dev_id);
-
-        va_start(ap, format);
-        {
-            ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), ZXIC_SIZEOF(szBuffer), format, ap);
-            ZXIC_COMM_STRNCAT_S(devBuffer, 1024, szBuffer, ZXIC_COMM_STRNLEN_S(szBuffer, ZXIC_SIZEOF(szBuffer)));
-
-            if (zxic_comm_get_print_en())
-            {
-                DH_LOG_INFO(MODULE_NP, "%s", devBuffer);
-            }
-        }
-        va_end(ap);
-    }
-}
-
-/***********************************************************/
-/** 支持多芯片的Debug信息打印函数
-* @param   dev_id
-* @param   format
-*
-* @return
-* @remark  无
-* @see
-* @author  wcl                  @date  2018/09/08
-************************************************************/
-ZXIC_VOID ZXIC_COMM_TRACE_DEV_DEBUG(ZXIC_UINT32 dev_id,ZXIC_CONST ZXIC_CHAR *format, ...)
-{
-    va_list   ap;
-    ZXIC_CHAR szBuffer[768 - 32] = {0};
-    ZXIC_CHAR devBuffer[1024]    = {0};
-
-    ZXIC_COMM_ASSERT(format);
-
-    if (zxic_comm_get_print_level() == 0 || zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT || dev_id > 3)
-    {
-        return;
-    }
-
-    if (zxic_comm_get_print_level() >= ZXIC_TRACE_DEBUG_PRINT)
-    {
-        ZXIC_COMM_SNPRINTF_S(devBuffer, ZXIC_SIZEOF(devBuffer), ZXIC_SIZEOF(devBuffer), "Dev_id[%u]_DEBUG: ", dev_id);
-
-        va_start(ap, format);
-        {
-            ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), ZXIC_SIZEOF(szBuffer), format, ap);
-            ZXIC_COMM_STRNCAT_S(devBuffer, 1024, szBuffer, ZXIC_COMM_STRNLEN_S(szBuffer, ZXIC_SIZEOF(szBuffer)));
-
-            if (zxic_comm_get_print_en())
-            {
-                DH_LOG_DEBUG(MODULE_NP, "%s", devBuffer);
-            }
-        }
-        va_end(ap);
-    }
-}
-
-/***********************************************************/
-/** 支持多芯片的所有调试信息打印函数
-* @param   dev_id
-* @param   format
-*
-* @return
-* @remark  无
-* @see
-* @author  wcl                  @date  2018/09/08
-************************************************************/
-ZXIC_VOID ZXIC_COMM_TRACE_DEV_ALL(ZXIC_UINT32 dev_id, ZXIC_CONST ZXIC_CHAR *format, ...)
-{
-    va_list   ap;
-    ZXIC_CHAR szBuffer[768 - 32] = {0};
-    ZXIC_CHAR devBuffer[1024]    = {0};
-
-    ZXIC_COMM_ASSERT(format);
-
-    if (zxic_comm_get_print_level() == 0 || zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT || dev_id > 3)
-    {
-        return;
-    }
-
-    if (zxic_comm_get_print_level() >= ZXIC_TRACE_ALL_PRINT)
-    {
-        ZXIC_COMM_SNPRINTF_S(devBuffer, ZXIC_SIZEOF(devBuffer), ZXIC_SIZEOF(devBuffer), "Dev_id[%u]_ALL:", dev_id);
-
-        va_start(ap, format);
-        {
-            ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), ZXIC_SIZEOF(szBuffer), format, ap);
-            ZXIC_COMM_STRNCAT_S(devBuffer, 1024, szBuffer, ZXIC_COMM_STRNLEN_S(szBuffer, ZXIC_SIZEOF(szBuffer)));
-
-            if (zxic_comm_get_print_en())
-            {
-                DH_LOG_DEBUG(MODULE_NP, "%s", devBuffer);
-            }
-        }
-        va_end(ap);
-    }
-}
-#endif
-
-#if ZXIC_REAL("")
-
-ZXIC_VOID ZXIC_COMM_DBGCNT64_PRINT(ZXIC_CONST ZXIC_CHAR * name, ZXIC_UINT64 value)
-{
-    ZXIC_CHAR temp_buff[50] = {0};
-
-    if (-1 == ZXIC_COMM_SNPRINTF_S(temp_buff, 50, 50, "0x%016llx", value))
-    {
-        return;
-    }
-
-    ZXIC_COMM_PRINT("%-50s  : %18s\n", name, temp_buff);
-}
-
-ZXIC_VOID ZXIC_COMM_DBGCNT32_PRINT(ZXIC_CONST ZXIC_CHAR * name, ZXIC_UINT32 value)
-{
-    ZXIC_CHAR temp_buff[50] = {0};
-
-    if (-1 == ZXIC_COMM_SNPRINTF_S(temp_buff, 50, 50, "0x%08x", value))
-    {
-        return;
-    }
-
-    ZXIC_COMM_PRINT("%-50s  : %18s\n", name, temp_buff);
-}
-
-/** 双参数打印 */
-ZXIC_VOID ZXIC_COMM_DBGCNT32_PAR_PRINT(ZXIC_CONST ZXIC_CHAR * name, ZXIC_UINT32 parm, ZXIC_UINT32 value)
-{
-    ZXIC_CHAR temp_buff[50] = {0};
-    ZXIC_CHAR vlaue_buff[18] = {0};
-
-    if (-1 == ZXIC_COMM_SNPRINTF_S(temp_buff, 50, 50, name, parm))
-    {
-        return;
-    }
-
-    if (-1 == ZXIC_COMM_SNPRINTF_S(vlaue_buff, 18, 18, "0x%08x", value))
-    {
-        return;
-    }
-
-    ZXIC_COMM_PRINT("%-50s  : %18s\n", temp_buff, vlaue_buff);
-}
-
+/**************************************************************
+* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司
+* 文件名称 : zxic_comm_print.c
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者   : xuchenxi_10235594
+* 完成日期 : 2020/07/20
+* DEPARTMENT: 有线开发四部-系统软件团队
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#include "zxic_common.h"
+#include "zxic_private.h"
+#include "log.h"
+
+#if ZXIC_REAL("全局变量定义")
+ZXIC_UINT32 g_zxic_print_level = ZXIC_TRACE_ERROR_PRINT; /*打印级别,默认为INFO*/
+ZXIC_UINT32 g_zxic_print_en = 1; /*界面打印控制开关*/
+#endif
+
+#if ZXIC_REAL("开关")
+/***********************************************************/
+/** 设置打印开关，决定ZXIC_COMM_PRINT等调试打印函数是否输出到屏幕
+ * @param   enable  0-不打印到屏幕，1-打印到屏幕
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zhaisyu      @date  2018/10/25
+ ************************************************************/
+ZXIC_VOID zxic_comm_set_print_en(ZXIC_UINT32 enable)
+{
+	g_zxic_print_en = enable;
+}
+
+ZXIC_RTN32 zxic_comm_get_print_en(ZXIC_VOID)
+{
+	return g_zxic_print_en;
+}
+
+/***********************************************************/
+/** 设置Debug打印级别
+ * @param   debug_level 0打印级别最低，4打印级别最高，即打印的东西最多
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  ChenWei10088471      @date  2014/02/07
+ ************************************************************/
+ZXIC_VOID zxic_comm_set_print_level(ZXIC_UINT32 debug_level)
+{
+	g_zxic_print_level = debug_level;
+}
+
+/***********************************************************/
+/** 获取Debug打印级别
+ * @param   ZXIC_VOID
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  ChenWei10088471      @date  2014/02/07
+ ************************************************************/
+ZXIC_RTN32 zxic_comm_get_print_level(ZXIC_VOID)
+{
+	return g_zxic_print_level;
+}
+
+#endif
+
+#if ZXIC_REAL("打印函数")
+ZXIC_VOID ZXIC_COMM_PRINT(ZXIC_CONST ZXIC_CHAR *format, ...)
+{
+	va_list ap;
+	ZXIC_CHAR szBuffer[1024];
+
+	ZXIC_COMM_ASSERT(format);
+
+	va_start(ap, format);
+	{
+		ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer),
+							  ZXIC_SIZEOF(szBuffer), format, ap);
+		if (g_zxic_print_en) {
+			DH_LOG_INFO(MODULE_NP, "%s", szBuffer);
+		}
+	}
+	va_end(ap);
+}
+
+/***********************************************************/
+/** Error信息打印函数
+ * @param   format
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  ChenWei10088471      @date  2014/02/07
+ ************************************************************/
+ZXIC_VOID ZXIC_COMM_TRACE_ERROR(ZXIC_CONST ZXIC_CHAR *format, ...)
+{
+	va_list ap;
+	ZXIC_CHAR szBuffer[1024];
+
+	ZXIC_COMM_ASSERT(format);
+
+	if (zxic_comm_get_print_level() == 0 ||
+		zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT) {
+		return;
+	}
+
+	va_start(ap, format);
+	{
+		ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), 1024, format,
+							  ap);
+		if (zxic_comm_get_print_en()) {
+			DH_LOG_ERR(MODULE_NP, "%s", szBuffer);
+		}
+	}
+	va_end(ap);
+}
+
+/***********************************************************/
+/** Info信息打印函数
+ * @param   format
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  ChenWei10088471      @date  2014/02/07
+ ************************************************************/
+ZXIC_VOID ZXIC_COMM_TRACE_INFO(ZXIC_CONST ZXIC_CHAR *format, ...)
+{
+	va_list ap;
+	ZXIC_CHAR szBuffer[1024];
+
+	ZXIC_COMM_ASSERT(format);
+
+	if (zxic_comm_get_print_level() == 0 ||
+		zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT) {
+		return;
+	}
+
+	if (zxic_comm_get_print_level() >= ZXIC_TRACE_INFO_PRINT) {
+		va_start(ap, format);
+		{
+			ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), 1024, format,
+								  ap);
+			if (zxic_comm_get_print_en()) {
+				DH_LOG_INFO(MODULE_NP, "%s", szBuffer);
+			}
+		}
+		va_end(ap);
+	}
+}
+
+/***********************************************************/
+/** Debug信息打印函数
+ * @param   format
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  ChenWei10088471      @date  2014/02/07
+ ************************************************************/
+ZXIC_VOID ZXIC_COMM_TRACE_DEBUG(ZXIC_CONST ZXIC_CHAR *format, ...)
+{
+	va_list ap;
+	ZXIC_CHAR szBuffer[1024];
+
+	ZXIC_COMM_ASSERT(format);
+
+	if (zxic_comm_get_print_level() == 0 ||
+		zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT) {
+		return;
+	}
+
+	if (zxic_comm_get_print_level() >= ZXIC_TRACE_DEBUG_PRINT) {
+		va_start(ap, format);
+		{
+			ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), 1024, format,
+								  ap);
+			if (zxic_comm_get_print_en()) {
+				DH_LOG_DEBUG(MODULE_NP, "%s", szBuffer);
+			}
+		}
+		va_end(ap);
+	}
+}
+
+/***********************************************************/
+/** 所有调试信息打印函数
+ * @param   format
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  ChenWei10088471      @date  2014/02/07
+ ************************************************************/
+ZXIC_VOID ZXIC_COMM_TRACE_ALL(ZXIC_CONST ZXIC_CHAR *format, ...)
+{
+	va_list ap;
+	ZXIC_CHAR szBuffer[1024];
+
+	ZXIC_COMM_ASSERT(format);
+
+	if (zxic_comm_get_print_level() == 0 ||
+		zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT) {
+		return;
+	}
+
+	if (zxic_comm_get_print_level() >= ZXIC_TRACE_ALL_PRINT) {
+		va_start(ap, format);
+		{
+			ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer), 1024, format,
+								  ap);
+			if (zxic_comm_get_print_en()) {
+				DH_LOG_DEBUG(MODULE_NP, "%s", szBuffer);
+			}
+		}
+		va_end(ap);
+	}
+}
+
+/***********************************************************/
+/** 支持多芯片的Error信息打印函数
+ *   打印级别为1及以上时执行打印
+ * @param   dev_id
+ * @param   format
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  xcx                  @date  2020/07/20
+ ************************************************************/
+ZXIC_VOID ZXIC_COMM_TRACE_DEV_ERROR(ZXIC_UINT32 dev_id,
+									ZXIC_CONST ZXIC_CHAR *format, ...)
+{
+	va_list ap;
+	ZXIC_CHAR szBuffer[768 - 32] = { 0 };
+	ZXIC_CHAR devBuffer[1024] = { 0 };
+
+	ZXIC_COMM_ASSERT(format);
+
+	if (zxic_comm_get_print_level() == 0 ||
+		zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT || dev_id > 3) {
+		return;
+	}
+
+	if (zxic_comm_get_print_level() >= ZXIC_TRACE_ERROR_PRINT) {
+		ZXIC_COMM_SNPRINTF_S(devBuffer, ZXIC_SIZEOF(devBuffer),
+							 ZXIC_SIZEOF(devBuffer),
+							 "Dev_id[%u]_ERROR: ", dev_id);
+
+		va_start(ap, format);
+		{
+			ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer),
+								  ZXIC_SIZEOF(szBuffer), format, ap);
+			ZXIC_COMM_STRNCAT_S(devBuffer, 1024, szBuffer,
+								ZXIC_COMM_STRNLEN_S(szBuffer,
+													ZXIC_SIZEOF(szBuffer)));
+
+			if (zxic_comm_get_print_en()) {
+				DH_LOG_ERR(MODULE_NP, "%s", devBuffer);
+			}
+		}
+		va_end(ap);
+	}
+}
+
+/***********************************************************/
+/** 支持多芯片的Info信息打印函数
+ *   打印级别为2及以上时执行打印
+ * @param   dev_id
+ * @param   format
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wcl                  @date  2018/09/08
+ ************************************************************/
+ZXIC_VOID ZXIC_COMM_TRACE_DEV_INFO(ZXIC_UINT32 dev_id,
+								   ZXIC_CONST ZXIC_CHAR *format, ...)
+{
+	va_list ap;
+	ZXIC_CHAR szBuffer[768 - 32] = { 0 };
+	ZXIC_CHAR devBuffer[1024] = { 0 };
+
+	ZXIC_COMM_ASSERT(format);
+
+	if (zxic_comm_get_print_level() == 0 ||
+		zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT || dev_id > 3) {
+		return;
+	}
+
+	if (zxic_comm_get_print_level() >= ZXIC_TRACE_INFO_PRINT) {
+		ZXIC_COMM_SNPRINTF_S(devBuffer, ZXIC_SIZEOF(devBuffer),
+							 ZXIC_SIZEOF(devBuffer),
+							 "Dev_id[%u]_INFO: ", dev_id);
+
+		va_start(ap, format);
+		{
+			ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer),
+								  ZXIC_SIZEOF(szBuffer), format, ap);
+			ZXIC_COMM_STRNCAT_S(devBuffer, 1024, szBuffer,
+								ZXIC_COMM_STRNLEN_S(szBuffer,
+													ZXIC_SIZEOF(szBuffer)));
+
+			if (zxic_comm_get_print_en()) {
+				DH_LOG_INFO(MODULE_NP, "%s", devBuffer);
+			}
+		}
+		va_end(ap);
+	}
+}
+
+/***********************************************************/
+/** 支持多芯片的Debug信息打印函数
+ * @param   dev_id
+ * @param   format
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wcl                  @date  2018/09/08
+ ************************************************************/
+ZXIC_VOID ZXIC_COMM_TRACE_DEV_DEBUG(ZXIC_UINT32 dev_id,
+									ZXIC_CONST ZXIC_CHAR *format, ...)
+{
+	va_list ap;
+	ZXIC_CHAR szBuffer[768 - 32] = { 0 };
+	ZXIC_CHAR devBuffer[1024] = { 0 };
+
+	ZXIC_COMM_ASSERT(format);
+
+	if (zxic_comm_get_print_level() == 0 ||
+		zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT || dev_id > 3) {
+		return;
+	}
+
+	if (zxic_comm_get_print_level() >= ZXIC_TRACE_DEBUG_PRINT) {
+		ZXIC_COMM_SNPRINTF_S(devBuffer, ZXIC_SIZEOF(devBuffer),
+							 ZXIC_SIZEOF(devBuffer),
+							 "Dev_id[%u]_DEBUG: ", dev_id);
+
+		va_start(ap, format);
+		{
+			ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer),
+								  ZXIC_SIZEOF(szBuffer), format, ap);
+			ZXIC_COMM_STRNCAT_S(devBuffer, 1024, szBuffer,
+								ZXIC_COMM_STRNLEN_S(szBuffer,
+													ZXIC_SIZEOF(szBuffer)));
+
+			if (zxic_comm_get_print_en()) {
+				DH_LOG_DEBUG(MODULE_NP, "%s", devBuffer);
+			}
+		}
+		va_end(ap);
+	}
+}
+
+/***********************************************************/
+/** 支持多芯片的所有调试信息打印函数
+ * @param   dev_id
+ * @param   format
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wcl                  @date  2018/09/08
+ ************************************************************/
+ZXIC_VOID ZXIC_COMM_TRACE_DEV_ALL(ZXIC_UINT32 dev_id,
+								  ZXIC_CONST ZXIC_CHAR *format, ...)
+{
+	va_list ap;
+	ZXIC_CHAR szBuffer[768 - 32] = { 0 };
+	ZXIC_CHAR devBuffer[1024] = { 0 };
+
+	ZXIC_COMM_ASSERT(format);
+
+	if (zxic_comm_get_print_level() == 0 ||
+		zxic_comm_get_print_level() >= ZXIC_TRACE_INVALID_PRINT || dev_id > 3) {
+		return;
+	}
+
+	if (zxic_comm_get_print_level() >= ZXIC_TRACE_ALL_PRINT) {
+		ZXIC_COMM_SNPRINTF_S(devBuffer, ZXIC_SIZEOF(devBuffer),
+							 ZXIC_SIZEOF(devBuffer), "Dev_id[%u]_ALL:", dev_id);
+
+		va_start(ap, format);
+		{
+			ZXIC_COMM_VSNPRINTF_S(szBuffer, ZXIC_SIZEOF(szBuffer),
+								  ZXIC_SIZEOF(szBuffer), format, ap);
+			ZXIC_COMM_STRNCAT_S(devBuffer, 1024, szBuffer,
+								ZXIC_COMM_STRNLEN_S(szBuffer,
+													ZXIC_SIZEOF(szBuffer)));
+
+			if (zxic_comm_get_print_en()) {
+				DH_LOG_DEBUG(MODULE_NP, "%s", devBuffer);
+			}
+		}
+		va_end(ap);
+	}
+}
+#endif
+
+#if ZXIC_REAL("")
+
+ZXIC_VOID ZXIC_COMM_DBGCNT64_PRINT(ZXIC_CONST ZXIC_CHAR *name,
+								   ZXIC_UINT64 value)
+{
+	ZXIC_CHAR temp_buff[50] = { 0 };
+
+	if (-1 == ZXIC_COMM_SNPRINTF_S(temp_buff, 50, 50, "0x%016llx", value)) {
+		return;
+	}
+
+	ZXIC_COMM_PRINT("%-50s  : %18s\n", name, temp_buff);
+}
+
+ZXIC_VOID ZXIC_COMM_DBGCNT32_PRINT(ZXIC_CONST ZXIC_CHAR *name,
+								   ZXIC_UINT32 value)
+{
+	ZXIC_CHAR temp_buff[50] = { 0 };
+
+	if (-1 == ZXIC_COMM_SNPRINTF_S(temp_buff, 50, 50, "0x%08x", value)) {
+		return;
+	}
+
+	ZXIC_COMM_PRINT("%-50s  : %18s\n", name, temp_buff);
+}
+
+/** 双参数打印 */
+ZXIC_VOID ZXIC_COMM_DBGCNT32_PAR_PRINT(ZXIC_CONST ZXIC_CHAR *name,
+									   ZXIC_UINT32 parm, ZXIC_UINT32 value)
+{
+	ZXIC_CHAR temp_buff[50] = { 0 };
+	ZXIC_CHAR vlaue_buff[18] = { 0 };
+
+	if (-1 == ZXIC_COMM_SNPRINTF_S(temp_buff, 50, 50, name, parm)) {
+		return;
+	}
+
+	if (-1 == ZXIC_COMM_SNPRINTF_S(vlaue_buff, 18, 18, "0x%08x", value)) {
+		return;
+	}
+
+	ZXIC_COMM_PRINT("%-50s  : %18s\n", temp_buff, vlaue_buff);
+}
+
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_rb_tree.c b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_rb_tree.c
index 5ae63c9de9a4e478f00e6f222f33254f3cffea71..c8ae21dac18641781a0f4731fbb4f488c42f56a4 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_rb_tree.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_comm_rb_tree.c
@@ -1,1059 +1,930 @@
-/*****************************************************************************
- * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。
- *
- * 文件名称：   zxic_comm_rb_tree.c
- * 文件标识：
- * 内容摘要：
- * 其它说明：
- * 当前版本：
- * 作    者：    ChenWei10088471
- * 完成日期：
- * 当前责任人-1：
- * 当前责任人-2：
- *
- * DEPARTMENT       : ASIC_FPGA_R&D_Dept
- * MANUAL_PERCENT   : 100%
- *****************************************************************************/
-#include "zxic_common.h"
-#include "zxic_comm_rb_tree.h"
-#include "zxic_comm_double_link.h"
-
-ZXIC_SINT32 zxic_comm_rb_def_cmp(ZXIC_VOID *p_new, ZXIC_VOID *p_old, ZXIC_UINT32 key_size)
-{
-    return ZXIC_COMM_MEMCMP(p_new, p_old, key_size);
-}
-
-ZXIC_RTN32 zxic_comm_rb_init(ZXIC_RB_CFG *p_rb_cfg,
-                        ZXIC_UINT32      total_num,
-                        ZXIC_UINT32      key_size,
-                        ZXIC_RB_CMPFUN cmpfun )
-{
-    ZXIC_UINT32      rtn  = ZXIC_OK;
-    ZXIC_UINT32      malloc_size = 0;
-    ZXIC_UINT32      memset_size = 0;
-
-    ZXIC_COMM_CHECK_POINT(p_rb_cfg);
-    if (p_rb_cfg->is_init)
-    {
-        ZXIC_COMM_TRACE_ERROR("\n zxic_comm_rb_init already init!");
-        return ZXIC_OK;
-    }
-
-    p_rb_cfg->key_size =  key_size;
-    p_rb_cfg->p_root   =  NULL;
-
-    if (cmpfun)
-    {
-        p_rb_cfg->p_cmpfun =  cmpfun;
-    }
-    else
-    {
-        p_rb_cfg->p_cmpfun = zxic_comm_rb_def_cmp;
-    }
-
-    if (total_num)
-    {
-        p_rb_cfg->is_dynamic = 0;
-
-        rtn = zxic_comm_double_link_init(total_num, &p_rb_cfg->tn_list);
-        ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_init");
-
-        rtn = zxic_comm_liststack_creat(total_num, &p_rb_cfg->p_lsm);
-        ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_liststack_creat");
-
-        p_rb_cfg->p_keybase = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(total_num * p_rb_cfg->key_size);
-        ZXIC_COMM_CHECK_POINT(p_rb_cfg->p_keybase);
-        memset_size = total_num * p_rb_cfg->key_size;
-        ZXIC_COMM_MEMSET(p_rb_cfg->p_keybase, 0, memset_size);
-        
-        malloc_size = (ZXIC_SIZEOF(ZXIC_RB_TN) * total_num) & ZXIC_UINT32_MASK;
-
-        p_rb_cfg->p_tnbase  = (ZXIC_RB_TN*)ZXIC_COMM_MALLOC(malloc_size);
-        ZXIC_COMM_CHECK_POINT(p_rb_cfg->p_tnbase);
-        ZXIC_COMM_MEMSET(p_rb_cfg->p_tnbase, 0, total_num * ZXIC_SIZEOF(ZXIC_RB_TN));
-    }
-    else /*totalnum = 0 indicate that customer manage the memory*/
-    {
-        p_rb_cfg->is_dynamic = 1;
-
-        rtn = zxic_comm_double_link_init(0xFFFFFFFF, &p_rb_cfg->tn_list);
-        ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_init");
-    }
-    p_rb_cfg->is_init = 1;
-
-    return ZXIC_OK;
-}
-
-ZXIC_RTN32 zxic_comm_rb_destroy(ZXIC_RB_CFG *p_rb_cfg)
-{
-    ZXIC_UINT32       rtn     = 0;
-
-    ZXIC_COMM_CHECK_POINT(p_rb_cfg);
-    /*静态才使用*/
-    if (0 == p_rb_cfg->is_dynamic)
-    {
-        zxic_comm_liststack_destroy(p_rb_cfg->p_lsm);    
-    }
-    if (NULL != p_rb_cfg->p_keybase)
-    {
-        ZXIC_COMM_FREE(p_rb_cfg->p_keybase);
-        p_rb_cfg->p_keybase = NULL;
-    }
-
-    if (NULL != p_rb_cfg->p_tnbase)
-    {
-        ZXIC_COMM_FREE(p_rb_cfg->p_tnbase);
-        p_rb_cfg->p_tnbase = NULL;
-    }
-
-    ZXIC_COMM_MEMSET(p_rb_cfg, 0, ZXIC_SIZEOF(ZXIC_RB_CFG));
-
-    return rtn;
-}
-
-ZXIC_VOID zxic_comm_rb_swich_color(ZXIC_RB_TN  *p_tn1, ZXIC_RB_TN *p_tn2)
-{
-    ZXIC_UINT32 color1, color2;
-
-    ZXIC_COMM_CHECK_POINT_NONE(p_tn1);
-    ZXIC_COMM_CHECK_POINT_NONE(p_tn2);
-
-    color1 = GET_TN_COLOR(p_tn1);
-    color2 = GET_TN_COLOR(p_tn2);
-
-    SET_TN_COLOR(p_tn1, color2);
-    SET_TN_COLOR(p_tn2, color1);
-
-    return;
-}
-
-
-ZXIC_RB_TN* zxic_comm_rb_get_brotn(ZXIC_RB_TN  *p_cur_tn)
-{
-    ZXIC_COMM_CHECK_POINT_RETURN_NULL(p_cur_tn);
-    ZXIC_COMM_CHECK_POINT_RETURN_NULL(p_cur_tn->p_parent);
-
-    return (p_cur_tn->p_parent->p_left == p_cur_tn) ? p_cur_tn->p_parent->p_right : p_cur_tn->p_parent->p_left;
-}
-
-
-ZXIC_RTN32 zxic_comm_rb_handle_ins(ZXIC_RB_CFG *p_rb_cfg,
-                              ZXIC_RB_TN  ***stack_tn,
-                              ZXIC_UINT32      stack_top)
-{
-    ZXIC_RB_TN  **pp_cur_tn        = NULL;
-    ZXIC_RB_TN  *p_cur_tn          = NULL;
-    ZXIC_RB_TN  **pp_tmp_tn        = NULL;
-    ZXIC_RB_TN  *p_tmp_tn          = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_rb_cfg);
-    ZXIC_COMM_CHECK_POINT(stack_tn);
-
-    while (stack_top > 0)
-    {
-        pp_cur_tn = stack_tn[stack_top];
-        p_cur_tn  = *pp_cur_tn;
-
-        if (!p_cur_tn->p_parent) /*root must be black*/
-        {
-            SET_TN_COLOR(p_cur_tn, ZXIC_RBT_BLACK);
-            break;
-        }
-        else if (GET_TN_COLOR(p_cur_tn->p_parent) == ZXIC_RBT_RED)
-        {
-            ZXIC_RB_TN *p_unc_tn = zxic_comm_rb_get_brotn(p_cur_tn->p_parent);
-
-            ZXIC_COMM_ASSERT(p_cur_tn->p_parent == *stack_tn[stack_top - 1]);
-
-            if (GET_TN_COLOR(p_unc_tn) == ZXIC_RBT_RED) /*unc is red,so we change the black of parent and unc*/
-            {
-                ZXIC_COMM_ASSERT(p_unc_tn);
-                SET_TN_COLOR(p_cur_tn->p_parent, ZXIC_RBT_BLACK);
-                SET_TN_COLOR(p_unc_tn, ZXIC_RBT_BLACK);
-
-                ZXIC_COMM_ASSERT(p_cur_tn->p_parent->p_parent == *stack_tn[stack_top - 2]);
-
-                SET_TN_COLOR(p_cur_tn->p_parent->p_parent, ZXIC_RBT_RED);
-                stack_top -= 2;
-            }
-            else /*we need shift ,p_cur_tn->parent->parent*/
-            {
-                ZXIC_RB_TN *p_bro_tn = NULL;
-
-                pp_tmp_tn = stack_tn[stack_top - 2];
-                p_tmp_tn  = *pp_tmp_tn;
-
-
-                if (p_cur_tn->p_parent == p_tmp_tn->p_left && p_cur_tn == p_cur_tn->p_parent->p_left)
-                {
-                    *pp_tmp_tn = p_cur_tn->p_parent;
-
-                    p_bro_tn  = zxic_comm_rb_get_brotn(p_cur_tn);
-                    p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent;
-
-                    p_tmp_tn->p_left   = p_bro_tn;
-                    p_tmp_tn->p_parent = p_cur_tn->p_parent;
-                    p_cur_tn->p_parent->p_right = p_tmp_tn;
-
-                    if (p_bro_tn)
-                    {
-                        p_bro_tn->p_parent  = p_tmp_tn;
-                    }
-
-                    zxic_comm_rb_swich_color(*pp_tmp_tn, p_tmp_tn);
-                }
-                else if (p_cur_tn->p_parent == p_tmp_tn->p_left && p_cur_tn == p_cur_tn->p_parent->p_right)
-                {
-                    *pp_tmp_tn = p_cur_tn;
-
-                    p_cur_tn->p_parent->p_right = p_cur_tn->p_left;
-
-                    if (p_cur_tn->p_left)
-                    {
-                        p_cur_tn->p_left->p_parent = p_cur_tn->p_parent;
-                    }
-
-                    p_cur_tn->p_parent->p_parent = p_cur_tn;
-                    p_tmp_tn->p_left = p_cur_tn->p_right;
-
-                    if (p_cur_tn->p_right)
-                    {
-                        p_cur_tn->p_right->p_parent = p_tmp_tn;
-                    }
-
-                    p_cur_tn->p_left = p_cur_tn->p_parent;
-                    p_cur_tn->p_right = p_tmp_tn;
-
-                    p_cur_tn->p_parent = p_tmp_tn->p_parent;
-                    p_tmp_tn->p_parent = p_cur_tn;
-
-                    zxic_comm_rb_swich_color(*pp_tmp_tn, p_tmp_tn);
-                }
-                else if (p_cur_tn->p_parent == p_tmp_tn->p_right && p_cur_tn == p_cur_tn->p_parent->p_right)
-                {
-                    *pp_tmp_tn = p_cur_tn->p_parent;
-                    p_bro_tn  = zxic_comm_rb_get_brotn(p_cur_tn);
-
-                    p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent;
-
-                    p_tmp_tn->p_right = p_cur_tn->p_parent->p_left;
-                    p_tmp_tn->p_parent = p_cur_tn->p_parent;
-                    p_cur_tn->p_parent->p_left = p_tmp_tn;
-
-                    if (p_bro_tn)
-                    {
-                        p_bro_tn->p_parent  = p_tmp_tn;
-                    }
-
-                    zxic_comm_rb_swich_color(*pp_tmp_tn, p_tmp_tn);
-                }
-                else
-                {
-                    *pp_tmp_tn = p_cur_tn;
-                    p_cur_tn->p_parent->p_left = p_cur_tn->p_right;
-
-                    if (p_cur_tn->p_right)
-                    {
-                        p_cur_tn->p_right->p_parent = p_cur_tn->p_parent;
-                    }
-
-                    p_cur_tn->p_parent->p_parent = p_cur_tn;
-                    p_tmp_tn->p_right = p_cur_tn->p_left;
-
-                    if (p_cur_tn->p_left)
-                    {
-                        p_cur_tn->p_left->p_parent = p_tmp_tn;
-                    }
-
-                    p_cur_tn->p_right = p_cur_tn->p_parent;
-                    p_cur_tn->p_left = p_tmp_tn;
-
-                    p_cur_tn->p_parent = p_tmp_tn->p_parent;
-                    p_tmp_tn->p_parent = p_cur_tn;
-
-                    zxic_comm_rb_swich_color(*pp_tmp_tn, p_tmp_tn);
-
-                }
-
-                /*change color*/
-
-                /* SET_TN_COLOR(p_cur_tn->p_parent,ZXIC_RBT_BLACK);
-                SET_TN_COLOR(p_tmp_tn,ZXIC_RBT_RED); */
-                break;
-            }
-        }
-        else /*parent is black ,nothing to do ,end*/
-        {
-            break;
-        }
-    }
-
-    return ZXIC_OK;
-}
-
-
-ZXIC_RTN32 zxic_comm_rb_insert(ZXIC_RB_CFG *p_rb_cfg,
-                         ZXIC_VOID       *p_key,
-                         ZXIC_VOID       *out_val)
-{
-    ZXIC_UINT32     rtn            = 0;
-    ZXIC_UINT32     stack_top      = 1;
-    ZXIC_SINT32    cmprtn         = 0;
-    ZXIC_UINT32     lsm_out        = 0;
-
-    ZXIC_RB_TN  **stack_tn[ZXIC_RBT_MAX_DEPTH] = {0};
-    //ZXIC_RB_TN  **pp_tmp_tn     = NULL;
-    ZXIC_RB_TN  *p_cur_tn      = NULL;
-    ZXIC_RB_TN  *p_pre_tn      = NULL;
-    ZXIC_RB_TN **pp_cur_tn     = NULL;
-    ZXIC_VOID       *p_cur_key     = NULL;
-    ZXIC_RB_TN  *p_ins_tn      = p_key;
-
-    ZXIC_COMM_CHECK_POINT(p_rb_cfg);
-    ZXIC_COMM_CHECK_POINT(p_key);
-
-    p_cur_key = p_rb_cfg->is_dynamic ? ((ZXIC_RB_TN*)p_key)->p_key : p_key;
-
-    pp_cur_tn = &p_rb_cfg->p_root;
-
-    for (;;)
-    {
-        p_cur_tn = *pp_cur_tn;
-
-        if (!p_cur_tn) /*find the insert position*/
-        {
-            if (p_rb_cfg->is_dynamic == 0)
-            {
-                rtn = zxic_comm_liststack_alloc(p_rb_cfg->p_lsm, &lsm_out);
-
-                if (rtn == ZXIC_LIST_STACK_ISEMPTY_ERR)
-                {
-                    return ZXIC_RBT_RC_FULL;
-                }
-
-                ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_liststack_alloc");
-
-                p_ins_tn = p_rb_cfg->p_tnbase + lsm_out;
-
-                ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW( p_rb_cfg->key_size, lsm_out);
-                INIT_RBT_TN(p_ins_tn, p_rb_cfg->key_size * lsm_out + p_rb_cfg->p_keybase);
-
-                ZXIC_COMM_MEMCPY_S(p_ins_tn->p_key, p_rb_cfg->key_size, p_key, p_rb_cfg->key_size);
-
-                SET_TN_LSV(p_ins_tn, lsm_out);
-
-                if (out_val)
-                {
-                    *((ZXIC_UINT32*)out_val) = lsm_out;
-                }
-            }
-            else
-            {
-                INIT_D_NODE(&p_ins_tn->tn_ln, p_ins_tn);
-            }
-
-            /*all insert tn color set to red*/
-            SET_TN_COLOR(p_ins_tn, ZXIC_RBT_RED);
-
-            /*insert list*/
-            if (cmprtn < 0)
-            {
-                rtn = zxic_comm_double_link_insert_pre(&p_ins_tn->tn_ln, &p_pre_tn->tn_ln, &p_rb_cfg->tn_list);
-                ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_pre");
-            }
-            else if (cmprtn > 0)
-            {
-                rtn = zxic_comm_double_link_insert_aft(&p_ins_tn->tn_ln, &p_pre_tn->tn_ln, &p_rb_cfg->tn_list);
-                ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_aft");
-            }
-            else
-            {
-                /*first insert*/
-                ZXIC_COMM_ASSERT(!p_pre_tn);
-
-                rtn = zxic_comm_double_link_insert_1st(&p_ins_tn->tn_ln, &p_rb_cfg->tn_list);
-                ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_1st");
-            }
-
-            /*get out loop */
-            break;
-        }
-
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(stack_top, 1);
-        stack_tn[stack_top++] =  pp_cur_tn;
-        p_pre_tn = p_cur_tn;
-        cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size);
-
-        if (cmprtn > 0)
-        {
-            pp_cur_tn = &p_cur_tn->p_right;
-        }
-        else if (cmprtn < 0)
-        {
-            pp_cur_tn = &p_cur_tn->p_left;
-        }
-        else
-        {
-            ZXIC_COMM_TRACE_ALL("info ,rb_key is same \n");
-
-            if (p_rb_cfg->is_dynamic)
-            {
-                if (out_val)
-                {
-                    *((ZXIC_RB_TN**)out_val) = p_cur_tn;
-                }
-            }
-            else
-            {
-                if (out_val)
-                {
-                    *((ZXIC_UINT32*)out_val) = GET_TN_LSV(p_cur_tn);
-                }
-            }
-
-            return ZXIC_RBT_RC_UPDATE;
-        }
-    }
-
-    /*handle parenet ptr*/
-    //pp_tmp_tn  = stack_tn[stack_top - 1];
-
-    /*p_ins_tn->p_parent = stack_top != 1 ? *pp_tmp_tn : NULL;*/
-    p_ins_tn->p_parent = (stack_top != 1) ? *stack_tn[stack_top - 1] : NULL;
-
-    stack_tn[stack_top] = pp_cur_tn;
-
-    *pp_cur_tn = p_ins_tn;
-
-    rtn = zxic_comm_rb_handle_ins(p_rb_cfg, stack_tn, stack_top);
-    ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_handle_ins");
-
-    /* 新插入时也返回 */
-    if (p_rb_cfg->is_dynamic)
-    {
-        if (out_val)
-        {
-            *((ZXIC_RB_TN**)out_val) = p_ins_tn;
-        }
-    }
-
-    return ZXIC_OK;
-}
-
-
-
-ZXIC_RTN32 zxic_comm_rb_handle_del(ZXIC_RB_CFG *p_rb_cfg,
-                             ZXIC_RB_TN***stack_tn,
-                             ZXIC_UINT32   stack_top)
-{
-    ZXIC_RB_TN  **pp_cur_tn        = NULL;
-    ZXIC_RB_TN  *p_cur_tn          = NULL;
-    ZXIC_RB_TN  *p_tmp_tn          = NULL;
-    ZXIC_RB_TN  *p_unc_tn          = NULL;
-    ZXIC_RB_TN  *p_par_tn          = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_rb_cfg);
-    ZXIC_COMM_CHECK_POINT(stack_tn);
-
-    while (stack_top > 1 )
-    {
-        pp_cur_tn =  stack_tn[stack_top];
-        p_cur_tn  = *pp_cur_tn;
-
-        p_par_tn  = *stack_tn[stack_top - 1];
-
-        if (p_cur_tn && p_cur_tn->p_parent)
-        {
-            p_unc_tn  = zxic_comm_rb_get_brotn(p_cur_tn);
-        }
-        else if (p_cur_tn && !p_cur_tn->p_parent)
-        {
-            ZXIC_COMM_ASSERT(p_par_tn == p_cur_tn->p_parent);
-
-            SET_TN_COLOR(p_cur_tn, ZXIC_RBT_BLACK);
-
-            break;
-        }
-        else
-        {
-            ZXIC_COMM_ASSERT(!p_cur_tn);
-
-            if (p_par_tn)
-            {
-                p_unc_tn = p_par_tn->p_left ? p_par_tn->p_left : p_par_tn->p_right;
-            }
-            else
-            {
-                break;
-            }
-        }
-
-        if (p_unc_tn)
-        {
-            ZXIC_COMM_ASSERT(p_unc_tn->p_parent == p_par_tn);
-        }
-
-        if (GET_TN_COLOR(p_unc_tn) == ZXIC_RBT_RED) /*shift */
-        {
-            ZXIC_COMM_CHECK_INDEX_BOTH(stack_top, 1, (ZXIC_RBT_MAX_DEPTH - 2));
-            if (p_unc_tn == p_par_tn->p_left) /*shift right */
-            {
-                *stack_tn[stack_top - 1] = p_unc_tn;
-                p_unc_tn->p_parent = p_par_tn->p_parent;
-                p_par_tn->p_left = p_unc_tn->p_right;
-
-                if (p_unc_tn->p_right)
-                {
-                    p_unc_tn->p_right->p_parent = p_par_tn;
-                }
-
-                p_par_tn->p_parent = p_unc_tn;
-                p_unc_tn->p_right = p_par_tn;
-
-                stack_tn[stack_top++] = &p_unc_tn->p_right;
-                ZXIC_COMM_CHECK_INDEX_UPPER(stack_top, (ZXIC_RBT_MAX_DEPTH - 1));
-                stack_tn[stack_top]   = &p_par_tn->p_right;
-            }
-            else /*shift left*/
-            {
-                ZXIC_COMM_ASSERT(p_unc_tn == p_par_tn->p_right);
-                *stack_tn[stack_top - 1] = p_unc_tn;
-                p_unc_tn->p_parent = p_par_tn->p_parent;
-                p_par_tn->p_right = p_unc_tn->p_left;
-
-                if (p_unc_tn->p_left)
-                {
-                    p_unc_tn->p_left->p_parent = p_par_tn;
-                }
-
-                p_par_tn->p_parent = p_unc_tn;
-                p_unc_tn->p_left  = p_par_tn;
-
-                stack_tn[stack_top++] = &p_unc_tn->p_left;
-                ZXIC_COMM_CHECK_INDEX_UPPER(stack_top, (ZXIC_RBT_MAX_DEPTH - 1));
-                stack_tn[stack_top]   = &p_par_tn->p_left;
-            }
-
-            zxic_comm_rb_swich_color(p_unc_tn, p_par_tn);
-        }
-        else if (!p_unc_tn)
-        {
-            /*this branch will never run ,consider too much*/
-            ZXIC_COMM_ASSERT(0);
-            ZXIC_COMM_ASSERT(GET_TN_COLOR(p_par_tn) ==  ZXIC_RBT_RED);
-
-            SET_TN_COLOR(p_par_tn, ZXIC_RBT_BLACK);
-
-            break;
-        }
-        else
-        {
-            if (GET_TN_COLOR(p_unc_tn->p_left) == ZXIC_RBT_BLACK && GET_TN_COLOR(p_unc_tn->p_right) == ZXIC_RBT_BLACK)
-            {
-                if (GET_TN_COLOR(p_unc_tn->p_parent) == ZXIC_RBT_BLACK)
-                {
-                    SET_TN_COLOR(p_unc_tn, ZXIC_RBT_RED);
-                    stack_top--;
-                }
-                else
-                {
-                    ZXIC_COMM_ASSERT(GET_TN_COLOR(p_unc_tn->p_parent) == ZXIC_RBT_RED);
-
-                    zxic_comm_rb_swich_color(p_unc_tn->p_parent, p_unc_tn);
-
-                    break;
-                }
-            }
-            else if (p_unc_tn == p_par_tn->p_right)
-            {
-                if (GET_TN_COLOR(p_unc_tn->p_right) == ZXIC_RBT_RED) /*shift left*/
-                {
-                    *stack_tn[stack_top - 1] = p_unc_tn;
-                    p_unc_tn->p_parent = p_par_tn->p_parent;
-                    p_par_tn->p_right = p_unc_tn->p_left;
-
-                    if (p_unc_tn->p_left)
-                    {
-                        p_unc_tn->p_left->p_parent = p_par_tn;
-                    }
-
-                    p_par_tn->p_parent = p_unc_tn;
-                    p_unc_tn->p_left  = p_par_tn;
-
-                    zxic_comm_rb_swich_color(p_unc_tn, p_par_tn);
-
-                    SET_TN_COLOR(p_unc_tn->p_right, ZXIC_RBT_BLACK);
-
-                    break;
-                }
-                else
-                {
-                    ZXIC_COMM_ASSERT(GET_TN_COLOR(p_unc_tn->p_left) == ZXIC_RBT_RED);
-
-                    p_tmp_tn = p_unc_tn->p_left;
-
-                    p_par_tn->p_right  = p_tmp_tn;
-                    p_tmp_tn->p_parent = p_par_tn;
-                    p_unc_tn->p_left  = p_tmp_tn->p_right;
-
-                    if (p_tmp_tn->p_right)
-                    {
-                        p_tmp_tn->p_right->p_parent = p_unc_tn;
-                    }
-
-                    p_tmp_tn->p_right = p_unc_tn;
-                    p_unc_tn->p_parent = p_tmp_tn;
-
-                    zxic_comm_rb_swich_color(p_tmp_tn, p_unc_tn);
-                }
-            }
-            else
-            {
-                ZXIC_COMM_ASSERT(p_unc_tn == p_par_tn->p_left);
-
-                if (GET_TN_COLOR(p_unc_tn->p_left) == ZXIC_RBT_RED) /*shift right*/
-                {
-                    *stack_tn[stack_top - 1] = p_unc_tn;
-                    p_unc_tn->p_parent = p_par_tn->p_parent;
-                    p_par_tn->p_left  = p_unc_tn->p_right;
-
-                    if (p_unc_tn->p_right)
-                    {
-                        p_unc_tn->p_right->p_parent = p_par_tn;
-                    }
-
-                    p_par_tn->p_parent = p_unc_tn;
-                    p_unc_tn->p_right = p_par_tn;
-
-                    zxic_comm_rb_swich_color(p_unc_tn, p_par_tn);
-
-                    SET_TN_COLOR(p_unc_tn->p_left, ZXIC_RBT_BLACK);
-                    break;
-                }
-                else
-                {
-                    ZXIC_COMM_ASSERT(GET_TN_COLOR(p_unc_tn->p_right) == ZXIC_RBT_RED);
-
-                    p_tmp_tn = p_unc_tn->p_right;
-
-                    p_par_tn->p_left  = p_tmp_tn;
-                    p_tmp_tn->p_parent = p_par_tn;
-                    p_unc_tn->p_right  = p_tmp_tn->p_left;
-
-                    if (p_tmp_tn->p_left)
-                    {
-                        p_tmp_tn->p_left->p_parent = p_unc_tn;
-                    }
-
-                    p_tmp_tn->p_left = p_unc_tn;
-                    p_unc_tn->p_parent = p_tmp_tn;
-
-                    zxic_comm_rb_swich_color(p_tmp_tn, p_unc_tn);
-                }
-            }
-        }
-    }
-
-    return ZXIC_OK;
-}
-
-ZXIC_RTN32 zxic_comm_rb_delete(ZXIC_RB_CFG *p_rb_cfg,
-                         ZXIC_VOID       *p_key,
-                         ZXIC_VOID       *out_val)
-{
-    ZXIC_UINT32     rtn            = 0;
-    ZXIC_UINT32     stack_top      = 1;
-    ZXIC_SINT32    cmprtn         = 0;
-    ZXIC_UINT32     rsv_stack      = 0;
-    ZXIC_UINT32     del_is_red     = 0;
-
-    ZXIC_RB_TN  **stack_tn[ZXIC_RBT_MAX_DEPTH] = {0};
-    ZXIC_RB_TN  *p_cur_tn      = NULL;
-    ZXIC_RB_TN **pp_cur_tn     = NULL;
-    ZXIC_VOID       *p_cur_key     = NULL;
-    ZXIC_RB_TN  *p_rsv_tn      = NULL;
-    ZXIC_RB_TN  *p_del_tn      = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_rb_cfg);
-    ZXIC_COMM_CHECK_POINT(out_val);
-
-    p_cur_key = p_key;
-
-    pp_cur_tn = &p_rb_cfg->p_root;
-
-    for (;;)
-    {
-        p_cur_tn = *pp_cur_tn;
-
-        if (!p_cur_tn)
-        {
-            /*ZXIC_COMM_TRACE_ERROR("\n error ,the key is not exist !");*/
-            return ZXIC_RBT_RC_SRHFAIL;
-        }
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(stack_top, 1);
-        stack_tn[stack_top++] = pp_cur_tn;
-
-        cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size);
-
-        if (cmprtn > 0)
-        {
-            pp_cur_tn = &p_cur_tn->p_right;
-        }
-        else if (cmprtn < 0)
-        {
-            pp_cur_tn = &p_cur_tn->p_left;
-        }
-        else
-        {
-            ZXIC_COMM_TRACE_ALL(" find the key!\n");
-
-            break;
-        }
-    }
-    ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(stack_top, 1);
-    rsv_stack =  stack_top - 1; /*save stack pos*/
-    p_rsv_tn  =  p_cur_tn;
-
-    pp_cur_tn = &p_cur_tn->p_right;
-    p_cur_tn  = *pp_cur_tn;
-
-    if (p_cur_tn)
-    {
-    
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(stack_top, 1);
-        stack_tn[stack_top++] = pp_cur_tn;
-
-        pp_cur_tn = &p_cur_tn->p_left;
-        p_cur_tn  = *pp_cur_tn;
-
-        while (p_cur_tn)
-        {
-            ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(stack_top, 1);        
-            stack_tn[stack_top++] = pp_cur_tn;
-            pp_cur_tn = &p_cur_tn->p_left;
-            p_cur_tn  = *pp_cur_tn;
-        }
-
-        /*get the del tn*/
-        ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(stack_top, 1);        
-        p_del_tn = *stack_tn[stack_top - 1];
-
-        /*set tn is left child to cur place*/
-        *stack_tn[stack_top - 1] = p_del_tn->p_right;
-
-        if (p_del_tn->p_right)
-        {
-            p_del_tn->p_right->p_parent =  p_del_tn->p_parent;
-        }
-
-        /*rsv the del tn info for delete*/
-        if (GET_TN_COLOR(p_del_tn) == ZXIC_RBT_RED)
-        {
-            del_is_red = 1;
-        }
-
-        /*replace the delete val*/
-        ZXIC_COMM_CHECK_INDEX_UPPER(rsv_stack, (ZXIC_RBT_MAX_DEPTH - 2));
-        *stack_tn[rsv_stack]   = p_del_tn;
-
-        stack_tn[rsv_stack + 1]  = &p_del_tn->p_right;
-
-        SET_TN_COLOR(p_del_tn, GET_TN_COLOR(p_rsv_tn));
-        p_del_tn->p_parent = p_rsv_tn->p_parent;
-
-        p_del_tn->p_left   = p_rsv_tn->p_left;
-
-        if (p_rsv_tn->p_left)
-        {
-            p_rsv_tn->p_left->p_parent = p_del_tn;
-        }
-
-        p_del_tn->p_right  = p_rsv_tn->p_right;
-
-        if (p_rsv_tn->p_right)
-        {
-            p_rsv_tn->p_right->p_parent = p_del_tn;
-        }
-    }
-    else
-    {
-        if (GET_TN_COLOR(p_rsv_tn) == ZXIC_RBT_RED)
-        {
-            del_is_red = 1;
-        }
-        
-        ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(stack_top, 1); 
-        *stack_tn[stack_top - 1] = p_rsv_tn->p_left;
-
-        if (p_rsv_tn->p_left)
-        {
-            p_rsv_tn->p_left->p_parent = p_rsv_tn->p_parent;
-        }
-    }
-
-    ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(stack_top, 1);
-    stack_top--;
-    ZXIC_COMM_CHECK_INDEX_UPPER(stack_top, (ZXIC_RBT_MAX_DEPTH - 1));
-    if (GET_TN_COLOR(*stack_tn[stack_top]) == ZXIC_RBT_RED)
-    {
-        SET_TN_COLOR(*stack_tn[stack_top], ZXIC_RBT_BLACK);
-    }
-    else if (!del_is_red) /*del node is red ,do nothing*/
-    {
-        rtn = zxic_comm_rb_handle_del(p_rb_cfg, stack_tn, stack_top);
-        ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_handle_del");
-    }
-
-    /*clear the node from the list */
-    rtn = zxic_comm_double_link_del(&p_rsv_tn->tn_ln, &p_rb_cfg->tn_list);
-    ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_del");
-
-    if (p_rb_cfg->is_dynamic)
-    {
-        *(ZXIC_RB_TN**)out_val = p_rsv_tn;
-    }
-    else
-    {
-        rtn = zxic_comm_liststack_free(p_rb_cfg->p_lsm, GET_TN_LSV(p_rsv_tn));
-        ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_liststack_free");
-
-        *(ZXIC_UINT32*)out_val = GET_TN_LSV(p_rsv_tn);
-
-        ZXIC_COMM_MEMSET(p_rsv_tn->p_key, 0, p_rb_cfg->key_size);
-        ZXIC_COMM_MEMSET(p_rsv_tn, 0, ZXIC_SIZEOF(ZXIC_RB_TN));
-    }
-
-    return ZXIC_OK;
-}
-
-/* 注意此处传入的p_key和insert时候传入的p_key不是同一个东西 */
-ZXIC_RTN32 zxic_comm_rb_search(ZXIC_RB_CFG *p_rb_cfg,
-                         ZXIC_VOID       *p_key,
-                         ZXIC_VOID       *out_val)
-{
-    ZXIC_SINT32    cmprtn   = 0;
-    ZXIC_RB_TN *p_cur_tn = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_rb_cfg);
-    ZXIC_COMM_CHECK_POINT(p_key);
-    ZXIC_COMM_CHECK_POINT(out_val);
-
-    p_cur_tn = p_rb_cfg->p_root;
-
-    while (p_cur_tn)
-    {
-        cmprtn = p_rb_cfg->p_cmpfun(p_key, p_cur_tn->p_key, p_rb_cfg->key_size);
-
-        if (cmprtn > 0)
-        {
-            p_cur_tn = p_cur_tn->p_right;
-        }
-        else if (cmprtn < 0)
-        {
-            p_cur_tn = p_cur_tn->p_left;
-        }
-        else
-        {
-            break;
-        }
-    }
-
-    if (!p_cur_tn)
-    {
-        ZXIC_COMM_TRACE_ALL("rb srh fail \n");
-        return ZXIC_RBT_RC_SRHFAIL;
-    }
-
-    if (p_rb_cfg->is_dynamic)
-    {
-        *(ZXIC_RB_TN**)out_val = p_cur_tn;
-    }
-    else
-    {
-        *(ZXIC_UINT32*)out_val = GET_TN_LSV(p_cur_tn);
-    }
-
-    return ZXIC_OK;
-}
-
-ZXIC_SINT32 zxic_comm_rb_is_none(ZXIC_RB_CFG*  p_rb_cfg)
-{
-    ZXIC_COMM_CHECK_POINT(p_rb_cfg);
-
-    if (0 == p_rb_cfg->tn_list.used)
-    {
-        return 1;
-    }
-    else
-    {
-        return 0;
-    }
-}
-
-ZXIC_RB_TN *zxic_comm_rb_get_1st_tn(ZXIC_RB_CFG *p_rb_cfg)
-{
-    ZXIC_COMM_CHECK_POINT_RETURN_NULL(p_rb_cfg);
-
-    return (p_rb_cfg->p_root) ? p_rb_cfg->tn_list.p_next->data : NULL;
-}
-
-ZXIC_RTN32 zxic_comm_rb_get_1st_key(ZXIC_RB_CFG* p_rb_cfg, ZXIC_VOID *p_key_out)
-{
-    D_NODE    *rb_list_node  = NULL;
-    ZXIC_RB_TN *p_rb_node     = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_rb_cfg);
-    ZXIC_COMM_CHECK_POINT(p_key_out);
-
-    if (zxic_comm_rb_is_none(p_rb_cfg))
-    {
-        return ZXIC_RBT_ISEMPTY_ERR;
-    }
-
-    rb_list_node = p_rb_cfg->tn_list.p_next;
-    ZXIC_COMM_CHECK_POINT(rb_list_node);
-
-    p_rb_node = (ZXIC_RB_TN *)rb_list_node->data;
-    ZXIC_COMM_CHECK_POINT(p_rb_node);
-
-    ZXIC_COMM_MEMCPY_S(p_key_out, p_rb_cfg->key_size, p_rb_node->p_key, p_rb_cfg->key_size);
-
-    return ZXIC_OK;
-}
-
-ZXIC_RB_TN *zxic_comm_rb_get_last_tn(ZXIC_RB_CFG *p_rb_cfg)
-{
-    ZXIC_COMM_CHECK_POINT_RETURN_NULL(p_rb_cfg);
-
-    return (p_rb_cfg->p_root) ? p_rb_cfg->tn_list.p_prev->data : NULL;
-}
-
-ZXIC_RTN32 zxic_comm_rb_get_last_key(ZXIC_RB_CFG*  p_rb_cfg, ZXIC_VOID *p_key_out)
-{
-    D_NODE        *p_rb_list_node      = NULL;
-    ZXIC_RB_TN     *p_rb_node           = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_rb_cfg);
-
-    if (zxic_comm_rb_is_none(p_rb_cfg))
-    {
-        return ZXIC_RBT_ISEMPTY_ERR;
-    }
-
-    p_rb_list_node = p_rb_cfg->tn_list.p_prev;
-
-    p_rb_node = (ZXIC_RB_TN *)p_rb_list_node->data;
-    ZXIC_COMM_MEMCPY_S(p_key_out, p_rb_cfg->key_size, p_rb_node->p_key, p_rb_cfg->key_size);
-
-    return ZXIC_OK;
-}
-
-/* 不支持动态内存分配模式, 此函数仅用于CPU软复位 */
-ZXIC_RTN32 zxic_comm_rb_insert_spec_index(ZXIC_RB_CFG *p_rb_cfg, ZXIC_VOID *p_key, ZXIC_UINT32 in_idx)
-{
-    ZXIC_UINT32     rtn            = 0;
-    ZXIC_UINT32     stack_top      = 1;
-    ZXIC_SINT32    cmprtn         = 0;
-
-    ZXIC_RB_TN  **stack_tn[ZXIC_RBT_MAX_DEPTH] = {0};
-    //ZXIC_RB_TN  **pp_tmp_tn     = NULL;
-    ZXIC_RB_TN  *p_cur_tn      = NULL;
-    ZXIC_RB_TN  *p_pre_tn      = NULL;
-    ZXIC_RB_TN **pp_cur_tn     = NULL;
-    ZXIC_VOID       *p_cur_key     = NULL;
-    ZXIC_RB_TN  *p_ins_tn      = p_key;
-
-    ZXIC_COMM_CHECK_POINT(p_rb_cfg);
-    ZXIC_COMM_CHECK_POINT(p_key);
-
-    if (p_rb_cfg->is_dynamic)
-    {
-        ZXIC_COMM_PRINT("zxic_comm_rb_insert_spec_index: dynamic mode is not support ! Error");
-        return ZXIC_RBT_PARA_INVALID;
-    }
-
-    p_cur_key = p_key;
-
-    pp_cur_tn = &p_rb_cfg->p_root;
-
-    for (;;)
-    {
-        p_cur_tn = *pp_cur_tn;
-
-        if (!p_cur_tn) /*find the insert position*/
-        {
-            rtn = zxic_comm_liststack_alloc_spec_index(p_rb_cfg->p_lsm, in_idx);
-            ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_liststack_alloc_spec_index");
-
-            p_ins_tn = p_rb_cfg->p_tnbase + in_idx;
-
-            ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW(p_rb_cfg->key_size, in_idx);
-            INIT_RBT_TN(p_ins_tn, p_rb_cfg->key_size * in_idx + p_rb_cfg->p_keybase);
-
-            ZXIC_COMM_MEMCPY_S(p_ins_tn->p_key, p_rb_cfg->key_size, p_key, p_rb_cfg->key_size);
-
-            SET_TN_LSV(p_ins_tn, in_idx);
-
-            /*all insert tn color set to red*/
-            SET_TN_COLOR(p_ins_tn, ZXIC_RBT_RED);
-
-            /*insert list*/
-            if (cmprtn < 0)
-            {
-                rtn = zxic_comm_double_link_insert_pre(&p_ins_tn->tn_ln, &p_pre_tn->tn_ln, &p_rb_cfg->tn_list);
-                ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_pre");
-            }
-            else if (cmprtn > 0)
-            {
-                rtn = zxic_comm_double_link_insert_aft(&p_ins_tn->tn_ln, &p_pre_tn->tn_ln, &p_rb_cfg->tn_list);
-                ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_aft");
-            }
-            else
-            {
-                /*first insert*/
-                ZXIC_COMM_ASSERT(!p_pre_tn);
-
-                rtn = zxic_comm_double_link_insert_1st(&p_ins_tn->tn_ln, &p_rb_cfg->tn_list);
-                ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_1st");
-            }
-
-            /*get out loop */
-            break;
-        }
-
-        
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(stack_top, 1);
-        stack_tn[stack_top++] =  pp_cur_tn;
-        p_pre_tn = p_cur_tn;
-        cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size);
-
-        if (cmprtn > 0)
-        {
-            pp_cur_tn = &p_cur_tn->p_right;
-        }
-        else if (cmprtn < 0)
-        {
-            pp_cur_tn = &p_cur_tn->p_left;
-        }
-        else
-        {
-            ZXIC_COMM_TRACE_ALL("info ,rb_key is same \n");
-
-            return ZXIC_RBT_RC_UPDATE;
-        }
-    }
-
-    /*handle parenet ptr*/
-    p_ins_tn->p_parent = (stack_top != 1) ? *stack_tn[stack_top - 1] : NULL;
-
-    stack_tn[stack_top] = pp_cur_tn;
-
-    *pp_cur_tn = p_ins_tn;
-
-    rtn = zxic_comm_rb_handle_ins(p_rb_cfg, stack_tn, stack_top);
-    ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_handle_ins");
-
-    return ZXIC_OK;
-}
-
-
+/*****************************************************************************
+ * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：   zxic_comm_rb_tree.c
+ * 文件标识：
+ * 内容摘要：
+ * 其它说明：
+ * 当前版本：
+ * 作    者：    ChenWei10088471
+ * 完成日期：
+ * 当前责任人-1：
+ * 当前责任人-2：
+ *
+ * DEPARTMENT       : ASIC_FPGA_R&D_Dept
+ * MANUAL_PERCENT   : 100%
+ *****************************************************************************/
+#include "zxic_common.h"
+#include "zxic_comm_rb_tree.h"
+#include "zxic_comm_double_link.h"
+
+ZXIC_SINT32 zxic_comm_rb_def_cmp(ZXIC_VOID *p_new, ZXIC_VOID *p_old,
+								 ZXIC_UINT32 key_size)
+{
+	return ZXIC_COMM_MEMCMP(p_new, p_old, key_size);
+}
+
+ZXIC_RTN32 zxic_comm_rb_init(ZXIC_RB_CFG *p_rb_cfg, ZXIC_UINT32 total_num,
+							 ZXIC_UINT32 key_size, ZXIC_RB_CMPFUN cmpfun)
+{
+	ZXIC_UINT32 rtn = ZXIC_OK;
+	ZXIC_UINT32 malloc_size = 0;
+	ZXIC_UINT32 memset_size = 0;
+
+	ZXIC_COMM_CHECK_POINT(p_rb_cfg);
+	if (p_rb_cfg->is_init) {
+		ZXIC_COMM_TRACE_ERROR("\n zxic_comm_rb_init already init!");
+		return ZXIC_OK;
+	}
+
+	p_rb_cfg->key_size = key_size;
+	p_rb_cfg->p_root = NULL;
+
+	if (cmpfun) {
+		p_rb_cfg->p_cmpfun = cmpfun;
+	} else {
+		p_rb_cfg->p_cmpfun = zxic_comm_rb_def_cmp;
+	}
+
+	if (total_num) {
+		p_rb_cfg->is_dynamic = 0;
+
+		rtn = zxic_comm_double_link_init(total_num, &p_rb_cfg->tn_list);
+		ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_init");
+
+		rtn = zxic_comm_liststack_creat(total_num, &p_rb_cfg->p_lsm);
+		ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_liststack_creat");
+
+		p_rb_cfg->p_keybase =
+				(ZXIC_UINT8 *)ZXIC_COMM_MALLOC(total_num * p_rb_cfg->key_size);
+		ZXIC_COMM_CHECK_POINT(p_rb_cfg->p_keybase);
+		memset_size = total_num * p_rb_cfg->key_size;
+		ZXIC_COMM_MEMSET(p_rb_cfg->p_keybase, 0, memset_size);
+
+		malloc_size = (ZXIC_SIZEOF(ZXIC_RB_TN) * total_num) & ZXIC_UINT32_MASK;
+
+		p_rb_cfg->p_tnbase = (ZXIC_RB_TN *)ZXIC_COMM_MALLOC(malloc_size);
+		ZXIC_COMM_CHECK_POINT(p_rb_cfg->p_tnbase);
+		ZXIC_COMM_MEMSET(p_rb_cfg->p_tnbase, 0,
+						 total_num * ZXIC_SIZEOF(ZXIC_RB_TN));
+	} else {/*totalnum = 0 indicate that customer manage the memory*/
+		p_rb_cfg->is_dynamic = 1;
+
+		rtn = zxic_comm_double_link_init(0xFFFFFFFF, &p_rb_cfg->tn_list);
+		ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_init");
+	}
+	p_rb_cfg->is_init = 1;
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_rb_destroy(ZXIC_RB_CFG *p_rb_cfg)
+{
+	ZXIC_UINT32 rtn = 0;
+
+	ZXIC_COMM_CHECK_POINT(p_rb_cfg);
+	/*静态才使用*/
+	if (0 == p_rb_cfg->is_dynamic) {
+		zxic_comm_liststack_destroy(p_rb_cfg->p_lsm);
+	}
+	if (NULL != p_rb_cfg->p_keybase) {
+		ZXIC_COMM_FREE(p_rb_cfg->p_keybase);
+		p_rb_cfg->p_keybase = NULL;
+	}
+
+	if (NULL != p_rb_cfg->p_tnbase) {
+		ZXIC_COMM_FREE(p_rb_cfg->p_tnbase);
+		p_rb_cfg->p_tnbase = NULL;
+	}
+
+	ZXIC_COMM_MEMSET(p_rb_cfg, 0, ZXIC_SIZEOF(ZXIC_RB_CFG));
+
+	return rtn;
+}
+
+ZXIC_VOID zxic_comm_rb_swich_color(ZXIC_RB_TN *p_tn1, ZXIC_RB_TN *p_tn2)
+{
+	ZXIC_UINT32 color1, color2;
+
+	ZXIC_COMM_CHECK_POINT_NONE(p_tn1);
+	ZXIC_COMM_CHECK_POINT_NONE(p_tn2);
+
+	color1 = GET_TN_COLOR(p_tn1);
+	color2 = GET_TN_COLOR(p_tn2);
+
+	SET_TN_COLOR(p_tn1, color2);
+	SET_TN_COLOR(p_tn2, color1);
+
+	return;
+}
+
+ZXIC_RB_TN *zxic_comm_rb_get_brotn(ZXIC_RB_TN *p_cur_tn)
+{
+	ZXIC_COMM_CHECK_POINT_RETURN_NULL(p_cur_tn);
+	ZXIC_COMM_CHECK_POINT_RETURN_NULL(p_cur_tn->p_parent);
+
+	return (p_cur_tn->p_parent->p_left == p_cur_tn) ?
+					 p_cur_tn->p_parent->p_right :
+					 p_cur_tn->p_parent->p_left;
+}
+
+ZXIC_RTN32 zxic_comm_rb_handle_ins(ZXIC_RB_CFG *p_rb_cfg,
+								   ZXIC_RB_TN ***stack_tn,
+								   ZXIC_UINT32 stack_top)
+{
+	ZXIC_RB_TN **pp_cur_tn = NULL;
+	ZXIC_RB_TN *p_cur_tn = NULL;
+	ZXIC_RB_TN **pp_tmp_tn = NULL;
+	ZXIC_RB_TN *p_tmp_tn = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_rb_cfg);
+	ZXIC_COMM_CHECK_POINT(stack_tn);
+
+	while (stack_top > 0) {
+		pp_cur_tn = stack_tn[stack_top];
+		p_cur_tn = *pp_cur_tn;
+
+		if (!p_cur_tn->p_parent) { /*root must be black*/
+			SET_TN_COLOR(p_cur_tn, ZXIC_RBT_BLACK);
+			break;
+		} else if (GET_TN_COLOR(p_cur_tn->p_parent) == ZXIC_RBT_RED) {
+			ZXIC_RB_TN *p_unc_tn = zxic_comm_rb_get_brotn(p_cur_tn->p_parent);
+
+			ZXIC_COMM_ASSERT(p_cur_tn->p_parent == *stack_tn[stack_top - 1]);
+
+			if (GET_TN_COLOR(p_unc_tn) ==
+				ZXIC_RBT_RED) { /*unc is red,so we change the black of parent and unc*/
+				ZXIC_COMM_ASSERT(p_unc_tn);
+				SET_TN_COLOR(p_cur_tn->p_parent, ZXIC_RBT_BLACK);
+				SET_TN_COLOR(p_unc_tn, ZXIC_RBT_BLACK);
+
+				ZXIC_COMM_ASSERT(p_cur_tn->p_parent->p_parent ==
+								 *stack_tn[stack_top - 2]);
+
+				SET_TN_COLOR(p_cur_tn->p_parent->p_parent, ZXIC_RBT_RED);
+				stack_top -= 2;
+			} else {/*we need shift ,p_cur_tn->parent->parent*/
+				ZXIC_RB_TN *p_bro_tn = NULL;
+
+				pp_tmp_tn = stack_tn[stack_top - 2];
+				p_tmp_tn = *pp_tmp_tn;
+
+				if (p_cur_tn->p_parent == p_tmp_tn->p_left &&
+					p_cur_tn == p_cur_tn->p_parent->p_left) {
+					*pp_tmp_tn = p_cur_tn->p_parent;
+
+					p_bro_tn = zxic_comm_rb_get_brotn(p_cur_tn);
+					p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent;
+
+					p_tmp_tn->p_left = p_bro_tn;
+					p_tmp_tn->p_parent = p_cur_tn->p_parent;
+					p_cur_tn->p_parent->p_right = p_tmp_tn;
+
+					if (p_bro_tn) {
+						p_bro_tn->p_parent = p_tmp_tn;
+					}
+
+					zxic_comm_rb_swich_color(*pp_tmp_tn, p_tmp_tn);
+				} else if (p_cur_tn->p_parent == p_tmp_tn->p_left &&
+						   p_cur_tn == p_cur_tn->p_parent->p_right) {
+					*pp_tmp_tn = p_cur_tn;
+
+					p_cur_tn->p_parent->p_right = p_cur_tn->p_left;
+
+					if (p_cur_tn->p_left) {
+						p_cur_tn->p_left->p_parent = p_cur_tn->p_parent;
+					}
+
+					p_cur_tn->p_parent->p_parent = p_cur_tn;
+					p_tmp_tn->p_left = p_cur_tn->p_right;
+
+					if (p_cur_tn->p_right) {
+						p_cur_tn->p_right->p_parent = p_tmp_tn;
+					}
+
+					p_cur_tn->p_left = p_cur_tn->p_parent;
+					p_cur_tn->p_right = p_tmp_tn;
+
+					p_cur_tn->p_parent = p_tmp_tn->p_parent;
+					p_tmp_tn->p_parent = p_cur_tn;
+
+					zxic_comm_rb_swich_color(*pp_tmp_tn, p_tmp_tn);
+				} else if (p_cur_tn->p_parent == p_tmp_tn->p_right &&
+						   p_cur_tn == p_cur_tn->p_parent->p_right) {
+					*pp_tmp_tn = p_cur_tn->p_parent;
+					p_bro_tn = zxic_comm_rb_get_brotn(p_cur_tn);
+
+					p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent;
+
+					p_tmp_tn->p_right = p_cur_tn->p_parent->p_left;
+					p_tmp_tn->p_parent = p_cur_tn->p_parent;
+					p_cur_tn->p_parent->p_left = p_tmp_tn;
+
+					if (p_bro_tn) {
+						p_bro_tn->p_parent = p_tmp_tn;
+					}
+
+					zxic_comm_rb_swich_color(*pp_tmp_tn, p_tmp_tn);
+				} else {
+					*pp_tmp_tn = p_cur_tn;
+					p_cur_tn->p_parent->p_left = p_cur_tn->p_right;
+
+					if (p_cur_tn->p_right) {
+						p_cur_tn->p_right->p_parent = p_cur_tn->p_parent;
+					}
+
+					p_cur_tn->p_parent->p_parent = p_cur_tn;
+					p_tmp_tn->p_right = p_cur_tn->p_left;
+
+					if (p_cur_tn->p_left) {
+						p_cur_tn->p_left->p_parent = p_tmp_tn;
+					}
+
+					p_cur_tn->p_right = p_cur_tn->p_parent;
+					p_cur_tn->p_left = p_tmp_tn;
+
+					p_cur_tn->p_parent = p_tmp_tn->p_parent;
+					p_tmp_tn->p_parent = p_cur_tn;
+
+					zxic_comm_rb_swich_color(*pp_tmp_tn, p_tmp_tn);
+				}
+				break;
+			}
+		} else { /*parent is black ,nothing to do ,end*/
+			break;
+		}
+	}
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_rb_insert(ZXIC_RB_CFG *p_rb_cfg, ZXIC_VOID *p_key,
+							   ZXIC_VOID *out_val)
+{
+	ZXIC_UINT32 rtn = 0;
+	ZXIC_UINT32 stack_top = 1;
+	ZXIC_SINT32 cmprtn = 0;
+	ZXIC_UINT32 lsm_out = 0;
+
+	ZXIC_RB_TN **stack_tn[ZXIC_RBT_MAX_DEPTH] = { 0 };
+	// ZXIC_RB_TN  **pp_tmp_tn     = NULL;
+	ZXIC_RB_TN *p_cur_tn = NULL;
+	ZXIC_RB_TN *p_pre_tn = NULL;
+	ZXIC_RB_TN **pp_cur_tn = NULL;
+	ZXIC_VOID *p_cur_key = NULL;
+	ZXIC_RB_TN *p_ins_tn = p_key;
+
+	ZXIC_COMM_CHECK_POINT(p_rb_cfg);
+	ZXIC_COMM_CHECK_POINT(p_key);
+
+	p_cur_key = p_rb_cfg->is_dynamic ? ((ZXIC_RB_TN *)p_key)->p_key : p_key;
+
+	pp_cur_tn = &p_rb_cfg->p_root;
+
+	for (;;) {
+		p_cur_tn = *pp_cur_tn;
+
+		if (!p_cur_tn) { /*find the insert position*/
+			if (p_rb_cfg->is_dynamic == 0) {
+				rtn = zxic_comm_liststack_alloc(p_rb_cfg->p_lsm, &lsm_out);
+
+				if (rtn == ZXIC_LIST_STACK_ISEMPTY_ERR) {
+					return ZXIC_RBT_RC_FULL;
+				}
+
+				ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_liststack_alloc");
+
+				p_ins_tn = p_rb_cfg->p_tnbase + lsm_out;
+
+				ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW(p_rb_cfg->key_size, lsm_out);
+				INIT_RBT_TN(p_ins_tn,
+							p_rb_cfg->key_size * lsm_out + p_rb_cfg->p_keybase);
+
+				ZXIC_COMM_MEMCPY_S(p_ins_tn->p_key, p_rb_cfg->key_size, p_key,
+								   p_rb_cfg->key_size);
+
+				SET_TN_LSV(p_ins_tn, lsm_out);
+
+				if (out_val) {
+					*((ZXIC_UINT32 *)out_val) = lsm_out;
+				}
+			} else {
+				INIT_D_NODE(&p_ins_tn->tn_ln, p_ins_tn);
+			}
+
+			/*all insert tn color set to red*/
+			SET_TN_COLOR(p_ins_tn, ZXIC_RBT_RED);
+
+			/*insert list*/
+			if (cmprtn < 0) {
+				rtn = zxic_comm_double_link_insert_pre(
+						&p_ins_tn->tn_ln, &p_pre_tn->tn_ln, &p_rb_cfg->tn_list);
+				ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_pre");
+			} else if (cmprtn > 0) {
+				rtn = zxic_comm_double_link_insert_aft(
+						&p_ins_tn->tn_ln, &p_pre_tn->tn_ln, &p_rb_cfg->tn_list);
+				ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_aft");
+			} else {
+				/*first insert*/
+				ZXIC_COMM_ASSERT(!p_pre_tn);
+
+				rtn = zxic_comm_double_link_insert_1st(&p_ins_tn->tn_ln,
+													   &p_rb_cfg->tn_list);
+				ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_1st");
+			}
+
+			/*get out loop */
+			break;
+		}
+
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(stack_top, 1);
+		stack_tn[stack_top++] = pp_cur_tn;
+		p_pre_tn = p_cur_tn;
+		cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key,
+									p_rb_cfg->key_size);
+
+		if (cmprtn > 0) {
+			pp_cur_tn = &p_cur_tn->p_right;
+		} else if (cmprtn < 0) {
+			pp_cur_tn = &p_cur_tn->p_left;
+		} else {
+			ZXIC_COMM_TRACE_ALL("info ,rb_key is same \n");
+
+			if (p_rb_cfg->is_dynamic) {
+				if (out_val) {
+					*((ZXIC_RB_TN **)out_val) = p_cur_tn;
+				}
+			} else {
+				if (out_val) {
+					*((ZXIC_UINT32 *)out_val) = GET_TN_LSV(p_cur_tn);
+				}
+			}
+
+			return ZXIC_RBT_RC_UPDATE;
+		}
+	}
+
+	/*handle parenet ptr*/
+	// pp_tmp_tn  = stack_tn[stack_top - 1];
+
+	/*p_ins_tn->p_parent = stack_top != 1 ? *pp_tmp_tn : NULL;*/
+	p_ins_tn->p_parent = (stack_top != 1) ? *stack_tn[stack_top - 1] : NULL;
+
+	stack_tn[stack_top] = pp_cur_tn;
+
+	*pp_cur_tn = p_ins_tn;
+
+	rtn = zxic_comm_rb_handle_ins(p_rb_cfg, stack_tn, stack_top);
+	ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_handle_ins");
+
+	/* 新插入时也返回 */
+	if (p_rb_cfg->is_dynamic) {
+		if (out_val) {
+			*((ZXIC_RB_TN **)out_val) = p_ins_tn;
+		}
+	}
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_rb_handle_del(ZXIC_RB_CFG *p_rb_cfg,
+								   ZXIC_RB_TN ***stack_tn,
+								   ZXIC_UINT32 stack_top)
+{
+	ZXIC_RB_TN **pp_cur_tn = NULL;
+	ZXIC_RB_TN *p_cur_tn = NULL;
+	ZXIC_RB_TN *p_tmp_tn = NULL;
+	ZXIC_RB_TN *p_unc_tn = NULL;
+	ZXIC_RB_TN *p_par_tn = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_rb_cfg);
+	ZXIC_COMM_CHECK_POINT(stack_tn);
+
+	while (stack_top > 1) {
+		pp_cur_tn = stack_tn[stack_top];
+		p_cur_tn = *pp_cur_tn;
+
+		p_par_tn = *stack_tn[stack_top - 1];
+
+		if (p_cur_tn && p_cur_tn->p_parent) {
+			p_unc_tn = zxic_comm_rb_get_brotn(p_cur_tn);
+		} else if (p_cur_tn && !p_cur_tn->p_parent) {
+			ZXIC_COMM_ASSERT(p_par_tn == p_cur_tn->p_parent);
+
+			SET_TN_COLOR(p_cur_tn, ZXIC_RBT_BLACK);
+
+			break;
+		} else {
+			ZXIC_COMM_ASSERT(!p_cur_tn);
+
+			if (p_par_tn) {
+				p_unc_tn = p_par_tn->p_left ? p_par_tn->p_left :
+												p_par_tn->p_right;
+			} else {
+				break;
+			}
+		}
+
+		if (p_unc_tn) {
+			ZXIC_COMM_ASSERT(p_unc_tn->p_parent == p_par_tn);
+		}
+
+		if (GET_TN_COLOR(p_unc_tn) == ZXIC_RBT_RED) { /*shift */
+			ZXIC_COMM_CHECK_INDEX_BOTH(stack_top, 1, (ZXIC_RBT_MAX_DEPTH - 2));
+			if (p_unc_tn == p_par_tn->p_left) { /*shift right */
+				*stack_tn[stack_top - 1] = p_unc_tn;
+				p_unc_tn->p_parent = p_par_tn->p_parent;
+				p_par_tn->p_left = p_unc_tn->p_right;
+
+				if (p_unc_tn->p_right) {
+					p_unc_tn->p_right->p_parent = p_par_tn;
+				}
+
+				p_par_tn->p_parent = p_unc_tn;
+				p_unc_tn->p_right = p_par_tn;
+
+				stack_tn[stack_top++] = &p_unc_tn->p_right;
+				ZXIC_COMM_CHECK_INDEX_UPPER(stack_top,
+											(ZXIC_RBT_MAX_DEPTH - 1));
+				stack_tn[stack_top] = &p_par_tn->p_right;
+			} else {/*shift left*/
+				ZXIC_COMM_ASSERT(p_unc_tn == p_par_tn->p_right);
+				*stack_tn[stack_top - 1] = p_unc_tn;
+				p_unc_tn->p_parent = p_par_tn->p_parent;
+				p_par_tn->p_right = p_unc_tn->p_left;
+
+				if (p_unc_tn->p_left) {
+					p_unc_tn->p_left->p_parent = p_par_tn;
+				}
+
+				p_par_tn->p_parent = p_unc_tn;
+				p_unc_tn->p_left = p_par_tn;
+
+				stack_tn[stack_top++] = &p_unc_tn->p_left;
+				ZXIC_COMM_CHECK_INDEX_UPPER(stack_top,
+											(ZXIC_RBT_MAX_DEPTH - 1));
+				stack_tn[stack_top] = &p_par_tn->p_left;
+			}
+
+			zxic_comm_rb_swich_color(p_unc_tn, p_par_tn);
+		} else if (!p_unc_tn) {
+			/*this branch will never run ,consider too much*/
+			ZXIC_COMM_ASSERT(0);
+			ZXIC_COMM_ASSERT(GET_TN_COLOR(p_par_tn) == ZXIC_RBT_RED);
+
+			SET_TN_COLOR(p_par_tn, ZXIC_RBT_BLACK);
+
+			break;
+		} else {
+			if (GET_TN_COLOR(p_unc_tn->p_left) == ZXIC_RBT_BLACK &&
+				GET_TN_COLOR(p_unc_tn->p_right) == ZXIC_RBT_BLACK) {
+				if (GET_TN_COLOR(p_unc_tn->p_parent) == ZXIC_RBT_BLACK) {
+					SET_TN_COLOR(p_unc_tn, ZXIC_RBT_RED);
+					stack_top--;
+				} else {
+					ZXIC_COMM_ASSERT(GET_TN_COLOR(p_unc_tn->p_parent) ==
+									 ZXIC_RBT_RED);
+
+					zxic_comm_rb_swich_color(p_unc_tn->p_parent, p_unc_tn);
+
+					break;
+				}
+			} else if (p_unc_tn == p_par_tn->p_right) {
+				if (GET_TN_COLOR(p_unc_tn->p_right) ==
+					ZXIC_RBT_RED) {/*shift left*/
+					*stack_tn[stack_top - 1] = p_unc_tn;
+					p_unc_tn->p_parent = p_par_tn->p_parent;
+					p_par_tn->p_right = p_unc_tn->p_left;
+
+					if (p_unc_tn->p_left) {
+						p_unc_tn->p_left->p_parent = p_par_tn;
+					}
+
+					p_par_tn->p_parent = p_unc_tn;
+					p_unc_tn->p_left = p_par_tn;
+
+					zxic_comm_rb_swich_color(p_unc_tn, p_par_tn);
+
+					SET_TN_COLOR(p_unc_tn->p_right, ZXIC_RBT_BLACK);
+
+					break;
+				} else {
+					ZXIC_COMM_ASSERT(GET_TN_COLOR(p_unc_tn->p_left) ==
+									 ZXIC_RBT_RED);
+
+					p_tmp_tn = p_unc_tn->p_left;
+
+					p_par_tn->p_right = p_tmp_tn;
+					p_tmp_tn->p_parent = p_par_tn;
+					p_unc_tn->p_left = p_tmp_tn->p_right;
+
+					if (p_tmp_tn->p_right) {
+						p_tmp_tn->p_right->p_parent = p_unc_tn;
+					}
+
+					p_tmp_tn->p_right = p_unc_tn;
+					p_unc_tn->p_parent = p_tmp_tn;
+
+					zxic_comm_rb_swich_color(p_tmp_tn, p_unc_tn);
+				}
+			} else {
+				ZXIC_COMM_ASSERT(p_unc_tn == p_par_tn->p_left);
+
+				if (GET_TN_COLOR(p_unc_tn->p_left) ==
+					ZXIC_RBT_RED) {/*shift right*/
+					*stack_tn[stack_top - 1] = p_unc_tn;
+					p_unc_tn->p_parent = p_par_tn->p_parent;
+					p_par_tn->p_left = p_unc_tn->p_right;
+
+					if (p_unc_tn->p_right) {
+						p_unc_tn->p_right->p_parent = p_par_tn;
+					}
+
+					p_par_tn->p_parent = p_unc_tn;
+					p_unc_tn->p_right = p_par_tn;
+
+					zxic_comm_rb_swich_color(p_unc_tn, p_par_tn);
+
+					SET_TN_COLOR(p_unc_tn->p_left, ZXIC_RBT_BLACK);
+					break;
+				} else {
+					ZXIC_COMM_ASSERT(GET_TN_COLOR(p_unc_tn->p_right) ==
+									 ZXIC_RBT_RED);
+
+					p_tmp_tn = p_unc_tn->p_right;
+
+					p_par_tn->p_left = p_tmp_tn;
+					p_tmp_tn->p_parent = p_par_tn;
+					p_unc_tn->p_right = p_tmp_tn->p_left;
+
+					if (p_tmp_tn->p_left) {
+						p_tmp_tn->p_left->p_parent = p_unc_tn;
+					}
+
+					p_tmp_tn->p_left = p_unc_tn;
+					p_unc_tn->p_parent = p_tmp_tn;
+
+					zxic_comm_rb_swich_color(p_tmp_tn, p_unc_tn);
+				}
+			}
+		}
+	}
+
+	return ZXIC_OK;
+}
+
+ZXIC_RTN32 zxic_comm_rb_delete(ZXIC_RB_CFG *p_rb_cfg, ZXIC_VOID *p_key,
+							   ZXIC_VOID *out_val)
+{
+	ZXIC_UINT32 rtn = 0;
+	ZXIC_UINT32 stack_top = 1;
+	ZXIC_SINT32 cmprtn = 0;
+	ZXIC_UINT32 rsv_stack = 0;
+	ZXIC_UINT32 del_is_red = 0;
+
+	ZXIC_RB_TN **stack_tn[ZXIC_RBT_MAX_DEPTH] = { 0 };
+	ZXIC_RB_TN *p_cur_tn = NULL;
+	ZXIC_RB_TN **pp_cur_tn = NULL;
+	ZXIC_VOID *p_cur_key = NULL;
+	ZXIC_RB_TN *p_rsv_tn = NULL;
+	ZXIC_RB_TN *p_del_tn = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_rb_cfg);
+	ZXIC_COMM_CHECK_POINT(out_val);
+
+	p_cur_key = p_key;
+
+	pp_cur_tn = &p_rb_cfg->p_root;
+
+	for (;;) {
+		p_cur_tn = *pp_cur_tn;
+
+		if (!p_cur_tn) {
+			/*ZXIC_COMM_TRACE_ERROR("\n error ,the key is not exist !");*/
+			return ZXIC_RBT_RC_SRHFAIL;
+		}
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(stack_top, 1);
+		stack_tn[stack_top++] = pp_cur_tn;
+
+		cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key,
+									p_rb_cfg->key_size);
+
+		if (cmprtn > 0) {
+			pp_cur_tn = &p_cur_tn->p_right;
+		} else if (cmprtn < 0) {
+			pp_cur_tn = &p_cur_tn->p_left;
+		} else {
+			ZXIC_COMM_TRACE_ALL(" find the key!\n");
+
+			break;
+		}
+	}
+	ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(stack_top, 1);
+	rsv_stack = stack_top - 1; /*save stack pos*/
+	p_rsv_tn = p_cur_tn;
+
+	pp_cur_tn = &p_cur_tn->p_right;
+	p_cur_tn = *pp_cur_tn;
+
+	if (p_cur_tn) {
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(stack_top, 1);
+		stack_tn[stack_top++] = pp_cur_tn;
+
+		pp_cur_tn = &p_cur_tn->p_left;
+		p_cur_tn = *pp_cur_tn;
+
+		while (p_cur_tn) {
+			ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(stack_top, 1);
+			stack_tn[stack_top++] = pp_cur_tn;
+			pp_cur_tn = &p_cur_tn->p_left;
+			p_cur_tn = *pp_cur_tn;
+		}
+
+		/*get the del tn*/
+		ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(stack_top, 1);
+		p_del_tn = *stack_tn[stack_top - 1];
+
+		/*set tn is left child to cur place*/
+		*stack_tn[stack_top - 1] = p_del_tn->p_right;
+
+		if (p_del_tn->p_right) {
+			p_del_tn->p_right->p_parent = p_del_tn->p_parent;
+		}
+
+		/*rsv the del tn info for delete*/
+		if (GET_TN_COLOR(p_del_tn) == ZXIC_RBT_RED) {
+			del_is_red = 1;
+		}
+
+		/*replace the delete val*/
+		ZXIC_COMM_CHECK_INDEX_UPPER(rsv_stack, (ZXIC_RBT_MAX_DEPTH - 2));
+		*stack_tn[rsv_stack] = p_del_tn;
+
+		stack_tn[rsv_stack + 1] = &p_del_tn->p_right;
+
+		SET_TN_COLOR(p_del_tn, GET_TN_COLOR(p_rsv_tn));
+		p_del_tn->p_parent = p_rsv_tn->p_parent;
+
+		p_del_tn->p_left = p_rsv_tn->p_left;
+
+		if (p_rsv_tn->p_left) {
+			p_rsv_tn->p_left->p_parent = p_del_tn;
+		}
+
+		p_del_tn->p_right = p_rsv_tn->p_right;
+
+		if (p_rsv_tn->p_right) {
+			p_rsv_tn->p_right->p_parent = p_del_tn;
+		}
+	} else {
+		if (GET_TN_COLOR(p_rsv_tn) == ZXIC_RBT_RED) {
+			del_is_red = 1;
+		}
+
+		ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(stack_top, 1);
+		*stack_tn[stack_top - 1] = p_rsv_tn->p_left;
+
+		if (p_rsv_tn->p_left) {
+			p_rsv_tn->p_left->p_parent = p_rsv_tn->p_parent;
+		}
+	}
+
+	ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(stack_top, 1);
+	stack_top--;
+	ZXIC_COMM_CHECK_INDEX_UPPER(stack_top, (ZXIC_RBT_MAX_DEPTH - 1));
+	if (GET_TN_COLOR(*stack_tn[stack_top]) == ZXIC_RBT_RED) {
+		SET_TN_COLOR(*stack_tn[stack_top], ZXIC_RBT_BLACK);
+	} else if (!del_is_red) { /*del node is red ,do nothing*/
+		rtn = zxic_comm_rb_handle_del(p_rb_cfg, stack_tn, stack_top);
+		ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_handle_del");
+	}
+
+	/*clear the node from the list */
+	rtn = zxic_comm_double_link_del(&p_rsv_tn->tn_ln, &p_rb_cfg->tn_list);
+	ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_del");
+
+	if (p_rb_cfg->is_dynamic) {
+		*(ZXIC_RB_TN **)out_val = p_rsv_tn;
+	} else {
+		rtn = zxic_comm_liststack_free(p_rb_cfg->p_lsm, GET_TN_LSV(p_rsv_tn));
+		ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_liststack_free");
+
+		*(ZXIC_UINT32 *)out_val = GET_TN_LSV(p_rsv_tn);
+
+		ZXIC_COMM_MEMSET(p_rsv_tn->p_key, 0, p_rb_cfg->key_size);
+		ZXIC_COMM_MEMSET(p_rsv_tn, 0, ZXIC_SIZEOF(ZXIC_RB_TN));
+	}
+
+	return ZXIC_OK;
+}
+
+/* 注意此处传入的p_key和insert时候传入的p_key不是同一个东西 */
+ZXIC_RTN32 zxic_comm_rb_search(ZXIC_RB_CFG *p_rb_cfg, ZXIC_VOID *p_key,
+							   ZXIC_VOID *out_val)
+{
+	ZXIC_SINT32 cmprtn = 0;
+	ZXIC_RB_TN *p_cur_tn = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_rb_cfg);
+	ZXIC_COMM_CHECK_POINT(p_key);
+	ZXIC_COMM_CHECK_POINT(out_val);
+
+	p_cur_tn = p_rb_cfg->p_root;
+
+	while (p_cur_tn) {
+		cmprtn = p_rb_cfg->p_cmpfun(p_key, p_cur_tn->p_key, p_rb_cfg->key_size);
+
+		if (cmprtn > 0) {
+			p_cur_tn = p_cur_tn->p_right;
+		} else if (cmprtn < 0) {
+			p_cur_tn = p_cur_tn->p_left;
+		} else {
+			break;
+		}
+	}
+
+	if (!p_cur_tn) {
+		ZXIC_COMM_TRACE_ALL("rb srh fail \n");
+		return ZXIC_RBT_RC_SRHFAIL;
+	}
+
+	if (p_rb_cfg->is_dynamic) {
+		*(ZXIC_RB_TN **)out_val = p_cur_tn;
+	} else {
+		*(ZXIC_UINT32 *)out_val = GET_TN_LSV(p_cur_tn);
+	}
+
+	return ZXIC_OK;
+}
+
+ZXIC_SINT32 zxic_comm_rb_is_none(ZXIC_RB_CFG *p_rb_cfg)
+{
+	ZXIC_COMM_CHECK_POINT(p_rb_cfg);
+
+	if (0 == p_rb_cfg->tn_list.used) {
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+ZXIC_RB_TN *zxic_comm_rb_get_1st_tn(ZXIC_RB_CFG *p_rb_cfg)
+{
+	ZXIC_COMM_CHECK_POINT_RETURN_NULL(p_rb_cfg);
+
+	return (p_rb_cfg->p_root) ? p_rb_cfg->tn_list.p_next->data : NULL;
+}
+
+ZXIC_RTN32 zxic_comm_rb_get_1st_key(ZXIC_RB_CFG *p_rb_cfg, ZXIC_VOID *p_key_out)
+{
+	D_NODE *rb_list_node = NULL;
+	ZXIC_RB_TN *p_rb_node = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_rb_cfg);
+	ZXIC_COMM_CHECK_POINT(p_key_out);
+
+	if (zxic_comm_rb_is_none(p_rb_cfg)) {
+		return ZXIC_RBT_ISEMPTY_ERR;
+	}
+
+	rb_list_node = p_rb_cfg->tn_list.p_next;
+	ZXIC_COMM_CHECK_POINT(rb_list_node);
+
+	p_rb_node = (ZXIC_RB_TN *)rb_list_node->data;
+	ZXIC_COMM_CHECK_POINT(p_rb_node);
+
+	ZXIC_COMM_MEMCPY_S(p_key_out, p_rb_cfg->key_size, p_rb_node->p_key,
+					   p_rb_cfg->key_size);
+
+	return ZXIC_OK;
+}
+
+ZXIC_RB_TN *zxic_comm_rb_get_last_tn(ZXIC_RB_CFG *p_rb_cfg)
+{
+	ZXIC_COMM_CHECK_POINT_RETURN_NULL(p_rb_cfg);
+
+	return (p_rb_cfg->p_root) ? p_rb_cfg->tn_list.p_prev->data : NULL;
+}
+
+ZXIC_RTN32 zxic_comm_rb_get_last_key(ZXIC_RB_CFG *p_rb_cfg,
+									 ZXIC_VOID *p_key_out)
+{
+	D_NODE *p_rb_list_node = NULL;
+	ZXIC_RB_TN *p_rb_node = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_rb_cfg);
+
+	if (zxic_comm_rb_is_none(p_rb_cfg)) {
+		return ZXIC_RBT_ISEMPTY_ERR;
+	}
+
+	p_rb_list_node = p_rb_cfg->tn_list.p_prev;
+
+	p_rb_node = (ZXIC_RB_TN *)p_rb_list_node->data;
+	ZXIC_COMM_MEMCPY_S(p_key_out, p_rb_cfg->key_size, p_rb_node->p_key,
+					   p_rb_cfg->key_size);
+
+	return ZXIC_OK;
+}
+
+/* 不支持动态内存分配模式, 此函数仅用于CPU软复位 */
+ZXIC_RTN32 zxic_comm_rb_insert_spec_index(ZXIC_RB_CFG *p_rb_cfg,
+										  ZXIC_VOID *p_key, ZXIC_UINT32 in_idx)
+{
+	ZXIC_UINT32 rtn = 0;
+	ZXIC_UINT32 stack_top = 1;
+	ZXIC_SINT32 cmprtn = 0;
+
+	ZXIC_RB_TN **stack_tn[ZXIC_RBT_MAX_DEPTH] = { 0 };
+	// ZXIC_RB_TN  **pp_tmp_tn     = NULL;
+	ZXIC_RB_TN *p_cur_tn = NULL;
+	ZXIC_RB_TN *p_pre_tn = NULL;
+	ZXIC_RB_TN **pp_cur_tn = NULL;
+	ZXIC_VOID *p_cur_key = NULL;
+	ZXIC_RB_TN *p_ins_tn = p_key;
+
+	ZXIC_COMM_CHECK_POINT(p_rb_cfg);
+	ZXIC_COMM_CHECK_POINT(p_key);
+
+	if (p_rb_cfg->is_dynamic) {
+		ZXIC_COMM_PRINT(
+				"zxic_comm_rb_insert_spec_index: dynamic mode is not support ! Error");
+		return ZXIC_RBT_PARA_INVALID;
+	}
+
+	p_cur_key = p_key;
+
+	pp_cur_tn = &p_rb_cfg->p_root;
+
+	for (;;) {
+		p_cur_tn = *pp_cur_tn;
+
+		if (!p_cur_tn) {/*find the insert position*/
+			rtn = zxic_comm_liststack_alloc_spec_index(p_rb_cfg->p_lsm, in_idx);
+			ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_liststack_alloc_spec_index");
+
+			p_ins_tn = p_rb_cfg->p_tnbase + in_idx;
+
+			ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW(p_rb_cfg->key_size, in_idx);
+			INIT_RBT_TN(p_ins_tn,
+						p_rb_cfg->key_size * in_idx + p_rb_cfg->p_keybase);
+
+			ZXIC_COMM_MEMCPY_S(p_ins_tn->p_key, p_rb_cfg->key_size, p_key,
+							   p_rb_cfg->key_size);
+
+			SET_TN_LSV(p_ins_tn, in_idx);
+
+			/*all insert tn color set to red*/
+			SET_TN_COLOR(p_ins_tn, ZXIC_RBT_RED);
+
+			/*insert list*/
+			if (cmprtn < 0) {
+				rtn = zxic_comm_double_link_insert_pre(
+						&p_ins_tn->tn_ln, &p_pre_tn->tn_ln, &p_rb_cfg->tn_list);
+				ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_pre");
+			} else if (cmprtn > 0) {
+				rtn = zxic_comm_double_link_insert_aft(
+						&p_ins_tn->tn_ln, &p_pre_tn->tn_ln, &p_rb_cfg->tn_list);
+				ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_aft");
+			} else {
+				/*first insert*/
+				ZXIC_COMM_ASSERT(!p_pre_tn);
+
+				rtn = zxic_comm_double_link_insert_1st(&p_ins_tn->tn_ln,
+													   &p_rb_cfg->tn_list);
+				ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_double_link_insert_1st");
+			}
+
+			/*get out loop */
+			break;
+		}
+
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(stack_top, 1);
+		stack_tn[stack_top++] = pp_cur_tn;
+		p_pre_tn = p_cur_tn;
+		cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key,
+									p_rb_cfg->key_size);
+
+		if (cmprtn > 0) {
+			pp_cur_tn = &p_cur_tn->p_right;
+		} else if (cmprtn < 0) {
+			pp_cur_tn = &p_cur_tn->p_left;
+		} else {
+			ZXIC_COMM_TRACE_ALL("info ,rb_key is same \n");
+
+			return ZXIC_RBT_RC_UPDATE;
+		}
+	}
+
+	/*handle parenet ptr*/
+	p_ins_tn->p_parent = (stack_top != 1) ? *stack_tn[stack_top - 1] : NULL;
+
+	stack_tn[stack_top] = pp_cur_tn;
+
+	*pp_cur_tn = p_ins_tn;
+
+	rtn = zxic_comm_rb_handle_ins(p_rb_cfg, stack_tn, stack_top);
+	ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_rb_handle_ins");
+
+	return ZXIC_OK;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_common.c b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_common.c
index 89306a2a32f5c995d90fae0dc5b176b870710b6a..d54daf6ea8593fe419cf9a81483099c025ab5cfd 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_common.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_common.c
@@ -1,1009 +1,924 @@
-/**************************************************************
-* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司
-* 文件名称 :        zxic_common.c
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者   :    xuchenxi_10235594
-* 完成日期 :        2020/07/20
-* DEPARTMENT:   有线开发四部-系统软件团队
-* MANUAL_PERCENT: 0%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-#include "zxic_common.h"
-
-#if ZXIC_REAL("全局变量")
-ZXIC_UINT32      g_zxic_malloc_num         = 0;
-ZXIC_UINT32      g_zxic_malloc_size        = 0;     /* 单位字节 */
-ZXIC_UINT32      g_zxic_byte_swap_en       = 1;
-ZXIC_UINT32      g_zxic_comm_channel_max   = 4;
-#endif
-
-#if ZXIC_REAL("内存")
-/***********************************************************/
-/** 释放内存
-* @param   p_data
-*
-* @return
-* @remark  无
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-ZXIC_VOID ic_comm_free_record(void)
-{
-    if (g_zxic_malloc_num > 0)
-    {
-        g_zxic_malloc_num--;
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_ERROR("Note:g_zxicp_malloc_num is zero now\n");
-    }
-}
-
-/***********************************************************/
-/** 分配内存
-* @param   size
-*
-* @return
-* @remark  无
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-ZXIC_VOID* ic_comm_malloc_memory(ZXIC_UINT32 size)
-{
-    /* 独立安全测评 限定申请内存的大小 */
-    if(size > ZXIC_MALLOC_MAX_B_SIZE)
-    {
-        ZXIC_COMM_TRACE_ERROR("malloc size err, size more than 200M \n");
-        return ZXIC_NULL;
-    }
-    if (g_zxic_malloc_num < ZXIC_UINT32_MAX)
-    {
-        g_zxic_malloc_num++;
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_ERROR("Note:g_zxicp_malloc_num is maxvalue now, reset 0\n");
-        g_zxic_malloc_num = 0;
-    }
-
-    if (g_zxic_malloc_size < (ZXIC_UINT32_MAX - size))
-    {
-        g_zxic_malloc_size += size;
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_INFO("Note:g_zxic_malloc_size[0x%x] and size[0x%x] sum is over maxvalue now, reset 0\n", g_zxic_malloc_size, size);
-        g_zxic_malloc_size = 0;
-    }
-    return kmalloc(size,GFP_KERNEL); 
-}
-#endif /* 内存 */
-
-#if ZXIC_REAL("延时")
-/***********************************************************/
-/** 毫秒级延时
-* @param   milliseconds
-*
-* @return
-* @remark  无
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-// ZXIC_VOID zxic_comm_sleep(ZXIC_UINT32 milliseconds)
-// {
-//     /* 打桩测试不需要延时       modify by zhangjintao 2022.01.21 */
-// #ifndef ZXIC_FOR_LLT
-// #ifdef ZXIC_OS_WIN
-//     Sleep(milliseconds);
-// #else
-//     ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NONE((ZXIC_UINT32)milliseconds, 1000);
-
-//     msleep(milliseconds);
-// #endif
-// #endif
-// }
-
-/***********************************************************/
-/** 微秒级延时,互坼锁中使用
-* @param   milliseconds
-*
-* @return
-* @remark  
-* @see
-* @author  fyl      @date  2020/04/09
-************************************************************/
-ZXIC_VOID zxic_comm_udelay(ZXIC_UINT32 microseconds)
-{
-#ifndef ZXIC_FOR_LLT
-
-    ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NONE(microseconds, 1);
-
-    udelay(microseconds);
-#endif
-}
-
-/***********************************************************/
-/** 毫秒级延时,互坼锁中使用
-* @param   milliseconds
-*
-* @return
-* @remark  无
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-ZXIC_VOID zxic_comm_delay(ZXIC_UINT32 milliseconds)
-{
-#ifndef ZXIC_FOR_LLT
-    // ZXIC_UINT32 i = 0;
-
-    ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NONE(milliseconds, 1);
-    // while (--milliseconds != 0)
-    // {
-    //     for (i = 0; i < 600; i++);
-    // }
-    mdelay(milliseconds);
-#endif
-}
-
-/***********************************************************/
-/** LINUX  :毫秒级延时
-    WINDOWS:毫秒级延时
-* @param   millisecond
-*
-* @return
-* @remark  无
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-ZXIC_VOID zxic_comm_msleep(ZXIC_UINT32 millisecond)
-{
-#ifndef ZXIC_FOR_LLT
-#ifdef ZXIC_OS_WIN
-    Sleep(millisecond);
-#else
-    msleep(millisecond);
-#endif
-#endif
-}
-
-/***********************************************************/
-/**获取时间函数，毫秒
-* @param   total
-* @param   masklen
-*
-* @return
-* @remark  无
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-ZXIC_DOUBLE zxic_comm_get_ticks_ms()
-{
-#ifdef ZXIC_OS_WIN
-    return (ZXIC_FLOAT)GetTickCount();
-#else
-    struct timespec64 tv = {0};
-    get_timespec64(&tv, ZXIC_NULL);
-    return (ZXIC_DOUBLE)1000 * tv.tv_sec + (ZXIC_DOUBLE)tv.tv_nsec / 1000;
-#endif
-}
-#endif
-
-#if ZXIC_REAL("字节序")
-/***********************************************************/
-/** 判断CPU的大小端字节序
-* @param   ZXIC_VOID
-*
-* @return  0-小端；1-大端
-* @remark  无
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-ZXIC_RTN32 zxic_comm_is_big_endian(ZXIC_VOID)
-{
-    ZXIC_ENDIAN_U c_data;
-
-    c_data.a = 1;
-
-    if (c_data.b == 1)
-    {
-        return 0;
-    }
-    else
-    {
-        return 1;
-    }
-}
-
-/***********************************************************/
-/** 字节序转换，以4字节为单位进行转序
-* @param   p_uc_data
-* @param   dw_byte_len
-*
-* @return
-* @remark  无
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-ZXIC_VOID zxic_comm_swap(ZXIC_UINT8 *p_uc_data, ZXIC_UINT32 dw_byte_len)
-{
-    ZXIC_UINT32      dw_byte_num    = 0;
-    ZXIC_UINT8       uc_byte_mode   = 0;
-    ZXIC_UINT32       uc_is_big_flag = 0;
-    ZXIC_UINT32      i              = 0;
-    ZXIC_UINT16     *p_w_tmp        = ZXIC_NULL;
-    ZXIC_UINT32     *p_dw_tmp       = ZXIC_NULL;
-
-    if (g_zxic_byte_swap_en)
-    {
-
-        p_dw_tmp = (ZXIC_UINT32 *)(p_uc_data);
-
-        uc_is_big_flag = zxic_comm_is_big_endian();
-
-        if (uc_is_big_flag)
-        {
-            return;
-        }
-        else
-        {
-            dw_byte_num  = dw_byte_len >> 2;
-            uc_byte_mode = dw_byte_len % 4 & 0xff;
-
-            for (i = 0; i < dw_byte_num; i++)
-            {
-                (*p_dw_tmp) = ZXIC_COMM_CONVERT32(*p_dw_tmp);
-                p_dw_tmp++;
-            }
-
-            if (uc_byte_mode > 1)
-            {
-                p_w_tmp = (ZXIC_UINT16 *)(p_dw_tmp);
-                (*p_w_tmp) = ZXIC_COMM_CONVERT16(*p_w_tmp);
-            }
-        }
-    }
-
-    return;
-}
-
-/***********************************************************/
-/** WORD32拼装成WORD64
-* @param   hi   高32bit
-* @param   lo   低32bit
-*
-* @return  WORD64
-* @remark  无
-* @see
-* @author  pj      @date  2019/10/22
-************************************************************/
-ZXIC_UINT64 ZXIC_COMM_COUNTER64_BUILD(ZXIC_UINT32 hi, ZXIC_UINT32 lo)
-{
-    ZXIC_UINT64 value = hi;
-
-    value = value << 32;
-    value = value | lo;
-
-    return value;
-}
-#endif
-
-#if ZXIC_REAL("bit操作")
-/***********************************************************/
-/** 将数据写入缓存区的指定bit位置，一次只能写入32bit的数据
-    p_base的低字节存放数据的低比特，高字节存放数据的高比特。
-* @param   p_base 数据缓存区指针
-* @param   base_size_bit 缓存总的bit位宽
-* @param   data 数据, 比特顺序左低右高，小端比特序
-* @param   start_bit 起始bit位置(必须小于结束bit位置)
-* @param   end_bit 结束bit位置
-*
-* @return
-* @remark  exp:
-                ZXIC_UINT8 data0[4] = {0x22, 0x44, 0x66, 0x88};
-                zxic_comm_write_bits(data0, 32, 0xAABBCC, 0,23);
-                ZXIC_COMM_PRINT("0x%02X %02X %02X %02X \n", data0[0], data0[1], data0[2], data0[3]);
-                输出:0xAA BB CC 88
-
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-ZXIC_RTN32 zxic_comm_write_bits(ZXIC_UINT8 * p_base, 
-                           ZXIC_UINT32 base_size_bit, 
-                           ZXIC_UINT32 data, 
-                           ZXIC_UINT32 start_bit, 
-                           ZXIC_UINT32 end_bit)
-{
-    ZXIC_UINT32   len               =  0;
-    ZXIC_UINT32   start_byte_index  =  0;
-    ZXIC_UINT32   end_byte_index    =  0;
-    ZXIC_UINT8     mask_value        =  0;
-    ZXIC_UINT32   byte_num          =  0;
-    ZXIC_UINT32   buffer_size       =  0;
-
-    if (0 != (base_size_bit % 8))
-    {
-        ZXIC_COMM_TRACE_ERROR("\n buffer must be:%d", __LINE__);
-        //assert(0);
-        return ZXIC_BIT_STREAM_INDEX_ERR;
-    }
-
-    if (start_bit > end_bit)
-    {
-        ZXIC_COMM_TRACE_ERROR("\nend_bit cannot be less than start_bit:%d", __LINE__);
-        //assert(0);
-        return ZXIC_BIT_STREAM_INDEX_ERR;
-    }
-
-    if (base_size_bit < end_bit)
-    {
-        ZXIC_COMM_TRACE_ERROR("\nend_bit exceeds the base_size!line:%d,base_size_bit:%d end_bit:%d",
-                             __LINE__, base_size_bit, end_bit);
-        //assert(0);
-        return ZXIC_BIT_STREAM_INDEX_ERR;
-    }
-
-    ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(end_bit, start_bit);
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(end_bit - start_bit, 1);
-
-    len = end_bit - start_bit + 1;
-    buffer_size = base_size_bit / 8;
-
-    /*寄存器位宽需要时2的次方，如不是，需要累加到最近的2的次方*/
-    /*用于解决KW检查中zxic_comm_write_bits_ex出现的内存泄漏错误*/
-    ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(buffer_size, 1);
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(buffer_size, 1);
-
-    while (0 != (buffer_size & (buffer_size - 1)))
-    {
-        buffer_size += 1;
-    }
-
-    if (buffer_size != base_size_bit / 8)
-    {
-        ZXIC_COMM_TRACE_ALL("\n buffer size[0x%x] is not 2^n: add up to [0x%x]", base_size_bit / 8, buffer_size);
-    }
-
-
-
-    /*一次只能写32bit*/
-    ZXIC_COMM_CHECK_INDEX(len, 1, 32);
-
-    if (data > (ZXIC_UINT32)(0xffffffff >> (32 - len)))
-    {
-        ZXIC_COMM_PRINT("\nValue is too big to write in the bit field!:%d,data:%x,len:%x",
-                  __LINE__, data, (ZXIC_UINT32)(0xffffffff >> (32 - len)));
-        return ZXIC_BIT_STREAM_DATA_TOO_BIG;
-    }
-
-    end_byte_index     = (end_bit    >> 3);
-    start_byte_index   = (start_bit  >> 3);
-
-    if (start_byte_index == end_byte_index)
-    {
-        mask_value  = ((0xFE << (7 - (start_bit & 7))) & 0xff);
-        mask_value |= (((1 << (7 - (end_bit  & 7))) - 1)& 0xff);
-        p_base[end_byte_index] &= mask_value;
-        p_base[end_byte_index] |= (((data << (7 - (end_bit & 7)))) & 0xff);
-        return ZXIC_OK;
-    }
-
-    if (7 != (end_bit & 7))
-    {
-        mask_value = ((0x7f >> (end_bit  & 7)) & 0xff);
-        p_base[end_byte_index] &= mask_value;
-        p_base[end_byte_index] |= ((data << (7 - (end_bit & 7))) & 0xff);
-        end_byte_index--;
-        data >>= 1 + (end_bit  & 7);
-    }
-
-    for (byte_num = end_byte_index; byte_num > start_byte_index; byte_num--)
-    {
-        /* critical */
-        p_base[byte_num & (buffer_size - 1)] = data & 0xff;
-        data >>= 8;
-    }
-
-    mask_value        = ((0xFE << (7 - (start_bit  & 7))) & 0xff);
-    p_base[byte_num] &= mask_value;
-    p_base[byte_num] |= data;
-
-    return ZXIC_OK;
-}
-
-/***********************************************************/
-/** 从缓存区中读取指定bit位置的数据，一次最多只能读32bit
-* @param   p_base 数据缓存区指针
-* @param   base_size_bit 缓存区总的bit位宽
-* @param   p_data 返回数据的指针
-* @param   start_bit 起始bit位置(必须小于结束bit位置)
-* @param   end_bit 结束bit位置
-*
-* @return
-* @remark  exp:
-            ZXIC_UINT8  data0[4] = {0x22, 0x44, 0x66, 0x88};
-            ZXIC_UINT32 test_a = 0;
-            zxic_comm_read_bits(data0, 32, &test_a, 0, 23);
-            输出: test_a = 0x224466
-* @see
-* @author  ChenWei10088471      @date  2014/02/07
-************************************************************/
-ZXIC_RTN32 zxic_comm_read_bits(ZXIC_UINT8* p_base, 
-                          ZXIC_UINT32 base_size_bit, 
-                          ZXIC_UINT32* p_data, 
-                          ZXIC_UINT32 start_bit, 
-                          ZXIC_UINT32 end_bit)
-{
-    ZXIC_UINT32   len               =  0;
-    ZXIC_UINT32   start_byte_index  =  0;
-    ZXIC_UINT32   end_byte_index    =  0;
-    ZXIC_UINT32   byte_num          =  0;
-    ZXIC_UINT32   buffer_size       =  0;
-
-    if (0 != (base_size_bit % 8))
-    {
-        ZXIC_COMM_TRACE_ERROR("\n buffer must be:%d", __LINE__);
-        return ZXIC_BIT_STREAM_INDEX_ERR;
-    }
-
-    if (start_bit > end_bit)
-    {
-        ZXIC_COMM_TRACE_ERROR("\nend_bit cannot be less than start_bit:%d", __LINE__);
-        return ZXIC_BIT_STREAM_INDEX_ERR;
-    }
-
-    if (base_size_bit < end_bit)
-    {
-        ZXIC_COMM_TRACE_ERROR("\nend_bit exceeds the base_size:%d,end_bit:%d", __LINE__, end_bit);
-        return ZXIC_BIT_STREAM_INDEX_ERR;
-    }
-
-    len = end_bit - start_bit + 1;
-    buffer_size = base_size_bit / 8;
-
-    /*寄存器位宽需要时2的次方，如不是，需要累加到最近的2的次方*/
-    /*用于解决KW检查中zxic_comm_read_bits_ex出现的内存泄漏错误*/
-    ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(buffer_size, 1);
-
-    while (0 != (buffer_size & (buffer_size - 1)))
-    {
-        buffer_size += 1;
-    }
-
-    if (buffer_size != base_size_bit / 8)
-    {
-        ZXIC_COMM_TRACE_ALL("\n buffer size[0x%x] is not 2^n: add up to [0x%x]", base_size_bit / 8, buffer_size);
-    }
-
-    /*先将返回的数据清零*/
-    *p_data = 0;
-
-    /*一次最多只能读32bit*/
-    ZXIC_COMM_CHECK_INDEX(len, 1, 32);
-
-    end_byte_index     = (end_bit    >> 3);
-    start_byte_index   = (start_bit  >> 3);
-
-    if (start_byte_index == end_byte_index)
-    {
-        *p_data = (ZXIC_UINT32)(((p_base[start_byte_index] >> (7U - (end_bit & 7))) & (0xff >> (8U - len))) & 0xff);
-        return ZXIC_OK;
-    }
-
-    if (start_bit & 7)
-    {
-        *p_data = (p_base[start_byte_index] & (0xff >> (start_bit & 7))) & ZXIC_UINT8_MASK;
-        start_byte_index++;
-    }
-
-    for (byte_num = start_byte_index; byte_num < end_byte_index; byte_num++)
-    {
-        *p_data <<= 8;
-        
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(*p_data, p_base[byte_num]);      
-        *p_data  += p_base[byte_num];
-    }
-
-    *p_data <<= 1 + (end_bit & 7);
-    /* critical */
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(*p_data, (((p_base[byte_num & (buffer_size - 1)] & (0xff << (7 - (end_bit  & 7)))) >> (7 - (end_bit  & 7))) & 0xff));
-    *p_data  += ((p_base[byte_num & (buffer_size - 1)] & (0xff << (7 - (end_bit  & 7)))) >> (7 - (end_bit  & 7))) & 0xff;
-
-    return ZXIC_OK;
-}
-
-/***********************************************************/
-/** 比特流拼装，比特流的形式为: p_base的低字节存放
-    数据的高比特，高字节存放数据的低比特。
-* @param   p_base
-* @param   base_size_bit
-* @param   data           数据, 比特顺序左高右低，大端比特序
-* @param   msb_start_pos  数据最高比特的位置
-* @param   len            数据长度
-*
-* @return
-* @remark  exp:
-                ZXIC_UINT8 data0[4] = {0x22, 0x44, 0x66, 0x88};
-                zxic_comm_write_bits_ex(data0, 32, 0x123456, 23,24);
-                ZXIC_COMM_PRINT("0x%02X %02X %02X %02X \n", data0[0], data0[1], data0[2], data0[3]);
-                输出：0x22 12 34 56
-
-* @see
-* @author  王春雷      @date  2014/03/08
-************************************************************/
-ZXIC_RTN32 zxic_comm_write_bits_ex(ZXIC_UINT8 * p_base, 
-                              ZXIC_UINT32 base_size_bit, 
-                              ZXIC_UINT32 data, 
-                              ZXIC_UINT32 msb_start_pos, 
-                              ZXIC_UINT32 len)
-{
-    ZXIC_RTN32 rtn = ZXIC_OK;
-    ZXIC_COMM_CHECK_POINT(p_base);
-
-    ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(base_size_bit, 1);
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(base_size_bit - 1, msb_start_pos);
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(base_size_bit - 1 - msb_start_pos, len);
-    ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(base_size_bit - 1 - msb_start_pos + len, 1);
-
-    rtn = zxic_comm_write_bits(p_base,
-                         base_size_bit,
-                         data,
-                         (base_size_bit - 1 - msb_start_pos),
-                         (base_size_bit - 1 - msb_start_pos + len - 1));
-
-    return rtn;
-}
-
-/***********************************************************/
-/** 从比特流中读取数据，比特流的形式为: p_base的低字节存放
-    数据的高比特，高字节存放数据的低比特。
-* @param   p_base
-* @param   base_size_bit
-* @param   p_data
-* @param   msb_start_pos
-* @param   len
-*
-* @return
-* @remark  exp:
-                ZXIC_UINT8 data0[4] = {0x22, 0x44, 0x66, 0x88};
-                zxic_comm_read_bits_ex(data0, 32, &test_a, 23, 24);
-                ZXIC_COMM_PRINT("0test_a = 0x%x \n", test_a);
-                输出: 0test_a = 0x446688
-                
-* @see
-* @author  王春雷      @date  2014/03/08
-************************************************************/
-ZXIC_RTN32 zxic_comm_read_bits_ex(ZXIC_UINT8 * p_base, 
-                             ZXIC_UINT32 base_size_bit, 
-                             ZXIC_UINT32 * p_data, 
-                             ZXIC_UINT32 msb_start_pos, 
-                             ZXIC_UINT32 len)
-{
-    ZXIC_RTN32 rtn = ZXIC_OK;
-    ZXIC_COMM_CHECK_POINT(p_base);
-    ZXIC_COMM_CHECK_POINT(p_data);
-
-    ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(base_size_bit, 1);
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(base_size_bit - 1, msb_start_pos);
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(base_size_bit - 1 - msb_start_pos, len);
-    ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(base_size_bit - 1 - msb_start_pos + len, 1);
-
-    rtn = zxic_comm_read_bits(p_base,
-                        base_size_bit,
-                        p_data,
-                        (base_size_bit - 1 - msb_start_pos),
-                        (base_size_bit - 1 - msb_start_pos + len - 1));
-    return rtn;
-}
-#endif /*  */
-
-#if ZXIC_REAL("字符串")
-/***********************************************************/
-/** 
-* @param   buffer   目标字符串
-* @param   sizeofbuf  sizeofbuffer
-* @param   count  要拷贝字节数
-* @param   format
-*
-* @return  待拷贝的实际字符串长度
-* @remark  snprintf
-* @see     
-* @author  sj      @date  2020/12/09
-************************************************************/
-ZXIC_SINT32 ic_comm_snprintf_s(ZXIC_CHAR *buffer, ZXIC_SIZE_T sizeofbuf, ZXIC_SIZE_T count, const ZXIC_CHAR *format, ...)
-{
-    va_list ap;
-    ZXIC_SINT32 ret = -1;
-    
-    if ((ZXIC_NULL == buffer)||(ZXIC_NULL == format))
-    { 
-        ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);
-        return ret;
-    }
-    if (!count)
-    {    
-        ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:count err], FUNCTION : %s!\n", __FILE__, __LINE__, __FUNCTION__);       
-        return ret;
-    }
-    va_start(ap, format);
-    ret = ZXIC_COMM_VSNPRINTF_S(buffer, sizeofbuf, count, format, ap);  
-    va_end(ap);
-    
-    if (ret == -1)
-    {
-        ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:snprintf_s err], FUNCTION : %s!\n", __FILE__, __LINE__, __FUNCTION__);
-    }    
-    return ret;
-}
-/***********************************************************/
-/** 
-* @param   buffer   目标字符串
-* @param   sizeofbuf  sizeofbuffer
-* @param   count  要拷贝字节数
-* @param   format
-*
-* @return  待拷贝的实际字符串长度
-* @remark  vsnprintf
-* @see     
-* @author  sj      @date  2020/12/09
-************************************************************/
-ZXIC_SINT32 ic_comm_vsnprintf_s(ZXIC_CHAR *buffer, ZXIC_SIZE_T sizeofbuf, ZXIC_SIZE_T count, const ZXIC_CHAR *format, va_list ap)
-{
-    ZXIC_SINT32 ret = -1;
-    
-    if ((ZXIC_NULL == buffer)||(ZXIC_NULL == format))
-    { 
-        ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);
-        return ret;
-    }
-    if (!count)
-    {    
-        ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:count err], FUNCTION : %s!\n", __FILE__, __LINE__, __FUNCTION__);       
-        return ret;
-    }
-    if (count < sizeofbuf)
-    {
-        sizeofbuf = count;
-    }  
-#ifdef ZXIC_OS_WIN
-    ret = _vsnprintf(buffer, sizeofbuf, format, ap);
-#else
-    ret = vsnprintf(buffer, sizeofbuf, format, ap);
-#endif
-    if (ret == -1)
-    {
-        ZXIC_COMM_TRACE_ERROR("\n ZXIC %s:%d[Error:vsnprintf err], FUNCTION : %s!\n", __FILE__, __LINE__, __FUNCTION__);
-    }  
-    return ret;
-}
-
-/***********************************************************/
-/** 
-* @param   pcDst 　　 目的地址
-* @param   dwMaxSize　目的长度
-* @param   pcSrc 　　 源地址
-* @param   dwCount　  要复制的最大字符数
-*
-* @return  
-* @remark  将源地址的字符拷贝到目的字符数组;
-* @see     
-* @author  
-************************************************************/
-ZXIC_CHAR *ic_comm_strncpy_s( ZXIC_CHAR *pcDst, size_t dwMaxSize, ZXIC_CONST ZXIC_CHAR *pcSrc, size_t dwCount )
-{
-    size_t  dwIndex = 1, dwCopyNum = dwCount;
-    ZXIC_CHAR   *pcResult = pcDst;
-
-    ZXIC_COMM_CHECK_RC_POINT_NO_PRINT(pcDst, pcResult);
-    ZXIC_COMM_CHECK_RC_POINT_NO_PRINT(pcSrc, pcResult);
-
-    if (( dwMaxSize <= 1 ) || (dwMaxSize > ZXIC_COMM_MEMORY_MAX_B_SIZE) || ( dwCount == 0 ) )
-    {
-        return pcResult;
-    }
-
-    /* 计算拷贝的字符长度，不含结束符 */
-    if ( dwCount >= dwMaxSize )
-    {
-        dwCopyNum = dwMaxSize - 1;
-    }
-
-    if (ic_comm_getAbsValue((unsigned ZXIC_CHAR*)pcDst, (ZXIC_CONST ZXIC_UINT8*)pcSrc) < dwCopyNum)
-    {
-        return pcResult;
-    }
-
-    while ( '\0' != ( *pcDst++ = *pcSrc++ ) )
-    {
-        /* 判断拷贝字符数是否等于dwCopyNum，等于就退出 */
-        /* 由于判断放在循环体内，进行判断前已经拷贝了一次，所以i初试值为1 */
-        if ( dwIndex++ >= dwCopyNum )
-        {
-            *pcDst = '\0';
-
-            return pcResult;
-        }
-    }
-
-    /* 本处的处理是为了保持和库函数中的解释一致，对于源串长度小于dwCopyNum，剩余部分全部填0 */
-    while ( dwIndex++ <= dwCopyNum )
-    {
-        *pcDst++ = '\0';
-    }
-
-    return pcResult;
-}
-
-ZXIC_SIZE_T ic_comm_getAbsValue(ZXIC_UINT8* dest, ZXIC_CONST ZXIC_UINT8* src)
-{
-    return dest > src ? (dest - src) : (src - dest);
-}
-/***********************************************************/
-/** 
-* @param   dest 　　目的地址
-* @param   src 　源地址
-* @param   n　　 要复制的长度
-*
-* @return  
-* @remark  从源地址拷贝若干字节的长度到目的内存处
-* @see     
-* @author  
-************************************************************/
-ZXIC_RTN32 ic_comm_memcpy(ZXIC_VOID* dest, ZXIC_CONST ZXIC_VOID* src, size_t n)
-{
-    ZXIC_COMM_CHECK_POINT(dest);
-    ZXIC_COMM_CHECK_POINT(src);
-    
-    /* memcpy 的大小限制在200M */
-    if(n > 200 * 1024 * 1024)
-    {
-        return ZXIC_PAR_CHK_INVALID_PARA;
-    }
-
-    if (ic_comm_getAbsValue((ZXIC_UINT8*)dest, (ZXIC_CONST ZXIC_UINT8*)src) < n)
-    {
-        return ZXIC_ERR;
-    }
-#ifdef ZXIC_OS_WIN
-    memcpy(dest, src, n);
-#else
-    //__memcpy_chk(dest, src, n, n);
-    memcpy(dest,src,n);
-#endif
-    return ZXIC_OK;
-}
-/***********************************************************/
-/** 
-* @param   dest 　　目的地址
-* @param   dest_len　目的长度
-* @param   src 　源地址
-* @param   n　　 要复制的长度
-*
-* @return  
-* @remark  从源地址拷贝若干字节的长度到目的内存处,增加源目的长度之间的检查
-* @see     
-* @author  
-************************************************************/
-ZXIC_RTN32 ic_comm_memcpy_s(ZXIC_VOID* dest, size_t dest_len, const void* src, size_t n)
-{
-    ZXIC_COMM_CHECK_POINT(dest);
-    ZXIC_COMM_CHECK_POINT(src);
-
-    /* memcpy 的大小限制在200M */
-    if(n > 200 * 1024 * 1024)
-    {
-        return ZXIC_PAR_CHK_INVALID_PARA;
-    }
-
-    if (ic_comm_getAbsValue((ZXIC_UINT8 *)dest, (ZXIC_CONST ZXIC_UINT8*)src) < n)
-    {
-        return ZXIC_PAR_CHK_ARGIN_ERROR;
-    }
-#ifdef ZXIC_OS_WIN
-    if (dest_len < n)
-    {
-        return ZXIC_ERR;
-    }
-    memcpy(dest, src, n);
-#else
-    //__memcpy_chk(dest, src, n, dest_len);
-    memcpy(dest, src, n);
-#endif
-    return ZXIC_OK;
-}
-
-/***********************************************************/
-/** 
-* @param   pcDst 　　 目的地址
-* @param   dwMaxSize　目的长度
-* @param   pcSrc 　　 源地址
-* @param   dwCount 　 待连接的字符数
-*
-* @return  
-* @remark  字符串连接函数，将pcSrc的dwCount字符复制到pcDst的字符串后，覆盖"\0";
-* @see     
-* @author  
-************************************************************/
-ZXIC_CHAR *ic_comm_strncat_s( ZXIC_CHAR *pcDst, size_t dwMaxSize, ZXIC_CONST ZXIC_CHAR *pcSrc, size_t dwCount )
-{
-    ZXIC_SIZE_T  dwIndex = 1, dwCopyNum = 0;
-    ZXIC_CHAR   *pcResult = pcDst;
-
-    ZXIC_COMM_CHECK_RC_POINT_NO_PRINT(pcDst, pcResult);
-    ZXIC_COMM_CHECK_RC_POINT_NO_PRINT(pcSrc, pcResult);
-
-    if (( dwMaxSize == 0 ) || (dwMaxSize > ZXIC_COMM_MEMORY_MAX_B_SIZE) || ( dwCount == 0 ) )
-    {
-        return pcResult;
-    }
-
-    /* 计算目的串的长度 */
-    while ( ( *pcDst++ != '\0' ) && ( ++dwCopyNum < dwMaxSize ) )
-    {
-    }
-
-    if ( dwCopyNum >= dwMaxSize )
-    {
-        return pcResult;
-    }
-
-    dwCopyNum = dwMaxSize - dwCopyNum;  /* 计算剩余的缓冲区长度 */
-
-    /* 计算拷贝的字符长度，不含结束符 */
-    if ( dwCount >= dwCopyNum )
-    {
-        dwCopyNum = dwCopyNum - 1;
-    }
-    else
-    {
-        dwCopyNum = dwCount;
-    }
-
-    if (dwCopyNum == 0) /* 宋志强 修正pcDst 空间刚好满导致内存越界的问题 */
-    {
-        return pcResult;
-    }
-
-    pcDst --;
-
-    if (ic_comm_getAbsValue((unsigned ZXIC_CHAR*)pcDst, (const unsigned ZXIC_CHAR*)pcSrc) < dwCopyNum)
-    {
-        return pcResult;
-    }
-
-    while ( '\0' != ( *pcDst++ = *pcSrc++ ) )
-    {
-        /* 判断拷贝字符数是否等于dwCopyNum，等于就退出 */
-        /* 由于判断放在循环体内，进行判断前已经拷贝了一次，所以i初试值为1 */
-        if ( dwIndex++ >= dwCopyNum )
-        {
-            *pcDst = '\0';
-
-            return pcResult;
-        }
-    }
-
-    /* 本处的处理是为了保持和库函数中的解释一致，对于源串长度小于dwCopyNum，剩余部分全部填0 */
-    while ( dwIndex++ <= dwCopyNum )
-    {
-        *pcDst++ = '\0';
-    }
-
-    return pcResult;
-}
-
-/***********************************************************/
-/** 
-* @param   str 　　字符串首地址
-* @param   MaxCount　可返回的最大长度,若计算的长度大于该长度，则返回MaxCount；
-*
-* @return  
-* @remark  计算字符串的长度
-* @see     
-* @author  
-************************************************************/
-ZXIC_SIZE_T ic_comm_strnlen_s( const ZXIC_CHAR *str, ZXIC_SIZE_T MaxCount)
-{
-    return (str == 0)? 0: ZXIC_COMM_STRNLEN(str, MaxCount);
-}
-
-ZXIC_VOID ic_comm_memset_s(void* dest, ZXIC_SIZE_T dmax, ZXIC_UINT8 c, ZXIC_SIZE_T n)
-{
-    if ((ZXIC_NULL == dest) || (dmax > ZXIC_COMM_MEMORY_MAX_B_SIZE) || (0 == n) || (n > dmax))
-    {
-        ZXIC_COMM_TRACE_ERROR("zxic_memset_s para err:ptr is null or size err.\n");
-        return;
-    }
-    memset(dest, c, n);
-}
-
-ZXIC_SINT32 ic_comm_memcmp(void* str1, const void* str2, ZXIC_SIZE_T n)
-{
-    if ((ZXIC_NULL == str1) || (ZXIC_NULL == str2)|| (n > ZXIC_COMM_MEMORY_MAX_B_SIZE) || (0 == n))
-    {   
-        ZXIC_COMM_TRACE_ERROR("zxic_memcmp para err:ptr is null or size more than 200M.\n");
-        return 0x7fffffff;
-    }
-    return memcmp(str1, str2, n);
-}
-#endif
-
-ZXIC_RTN32 zxic_comm_random()
-{
-
-#ifdef ZXIC_OS_WIN
-    /* return RtlGenRandom(); Modify by wcl, 20200424, Windows版本编译失败,先改回rand */
-    return rand();
-#else
-    ZXIC_UINT8 buff[4] = {0};
-    ZXIC_UINT32 ticks = 0;
-    ZXIC_UINT32 random_d = 0;
-    struct timespec64 tv;
-    ZXIC_UINT32 result_len = 0;
-    struct file *fd = NULL;
-    loff_t pos = 0;
-
-    //fd =  open("/dev/urandom", O_RDONLY);
-    fd = filp_open("/dev/urandom",O_RDONLY,0);
-
-    if(NULL==fd)
-    {
-        get_timespec64(&tv, ZXIC_NULL);
-        ticks = ((tv.tv_sec & ZXIC_UINT32_MAX) + (tv.tv_nsec & ZXIC_UINT32_MAX)) & ZXIC_UINT32_MAX;
-        random_d = ticks;
-    }
-    else if ((result_len = (kernel_read(fd, buff, ZXIC_SIZEOF(buff),&pos) & 0xFFFFFFFF)) != ZXIC_SIZEOF(buff))
-    {
-        get_timespec64(&tv, ZXIC_NULL);
-        ticks = ((tv.tv_sec & ZXIC_UINT32_MAX) + (tv.tv_nsec & ZXIC_UINT32_MAX)) & ZXIC_UINT32_MAX;
-        random_d = ticks;
-        filp_close(fd,NULL);
-    }
-    else
-    {
-        random_d = (((buff[0] << 24) & 0xff000000) | 
-                    ((buff[1] << 16) & 0x00ff0000) | 
-                    ((buff[2] << 8)  & 0x0000ff00) | 
-                     (buff[3] & 0x000000ff));        
-        filp_close(fd,NULL);
-    }
-
-    return random_d;
-#endif
-
-}
-
-/***********************************************************/
-/** 设置最大通道数
-* @param   dev_max      设置的最大设备数
-*
-* @return
-* @remark  无
-* @see
-* @author  lihk      @date  2021/03/31
-************************************************************/
-ZXIC_VOID zxic_comm_channel_max_set(ZXIC_UINT32 dev_max)
-{
-    g_zxic_comm_channel_max = dev_max;
-}
-
-/***********************************************************/
-/** 获取最大通道数
-* @param
-*
-* @return
-* @remark  无
-* @see
-* @author  lihk      @date  2021/03/31
-************************************************************/
-ZXIC_RTN32 zxic_comm_channel_max_get(ZXIC_VOID)
-{
-    return g_zxic_comm_channel_max;
-}
+/**************************************************************
+* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司
+* 文件名称 :        zxic_common.c
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者   :    xuchenxi_10235594
+* 完成日期 :        2020/07/20
+* DEPARTMENT:   有线开发四部-系统软件团队
+* MANUAL_PERCENT: 0%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#include "zxic_common.h"
+
+#if ZXIC_REAL("全局变量")
+ZXIC_UINT32 g_zxic_malloc_num;
+ZXIC_UINT32 g_zxic_malloc_size; /* 单位字节 */
+ZXIC_UINT32 g_zxic_byte_swap_en = 1;
+ZXIC_UINT32 g_zxic_comm_channel_max = 4;
+#endif
+
+#if ZXIC_REAL("内存")
+/***********************************************************/
+/** 释放内存
+ * @param   p_data
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  ChenWei10088471      @date  2014/02/07
+ ************************************************************/
+ZXIC_VOID ic_comm_free_record(void)
+{
+	if (g_zxic_malloc_num > 0) {
+		g_zxic_malloc_num--;
+	} else {
+		ZXIC_COMM_TRACE_ERROR("Note:g_zxicp_malloc_num is zero now\n");
+	}
+}
+
+/***********************************************************/
+/** 分配内存
+ * @param   size
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  ChenWei10088471      @date  2014/02/07
+ ************************************************************/
+ZXIC_VOID *ic_comm_malloc_memory(ZXIC_UINT32 size)
+{
+	/* 独立安全测评 限定申请内存的大小 */
+	if (size > ZXIC_MALLOC_MAX_B_SIZE) {
+		ZXIC_COMM_TRACE_ERROR("malloc size err, size more than 200M \n");
+		return ZXIC_NULL;
+	}
+	if (g_zxic_malloc_num < ZXIC_UINT32_MAX) {
+		g_zxic_malloc_num++;
+	} else {
+		ZXIC_COMM_TRACE_ERROR(
+				"Note:g_zxicp_malloc_num is maxvalue now, reset 0\n");
+		g_zxic_malloc_num = 0;
+	}
+
+	if (g_zxic_malloc_size < (ZXIC_UINT32_MAX - size)) {
+		g_zxic_malloc_size += size;
+	} else {
+		ZXIC_COMM_TRACE_INFO(
+				"Note:g_zxic_malloc_size[0x%x] and size[0x%x] sum is over maxvalue now, reset 0\n",
+				g_zxic_malloc_size, size);
+		g_zxic_malloc_size = 0;
+	}
+	return kmalloc(size, GFP_KERNEL);
+}
+#endif /* 内存 */
+
+#if ZXIC_REAL("延时")
+/***********************************************************/
+/** 毫秒级延时
+ * @param   milliseconds
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  ChenWei10088471      @date  2014/02/07
+ ************************************************************/
+// ZXIC_VOID zxic_comm_sleep(ZXIC_UINT32 milliseconds)
+// {
+//     /* 打桩测试不需要延时       modify by zhangjintao 2022.01.21 */
+// #ifndef ZXIC_FOR_LLT
+// #ifdef ZXIC_OS_WIN
+//     Sleep(milliseconds);
+// #else
+//     ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NONE((ZXIC_UINT32)milliseconds, 1000);
+
+//     msleep(milliseconds);
+// #endif
+// #endif
+// }
+
+/***********************************************************/
+/** 毫秒级延时,互坼锁中使用
+ * @param   milliseconds
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  ChenWei10088471      @date  2014/02/07
+ ************************************************************/
+ZXIC_VOID zxic_comm_delay(ZXIC_UINT32 milliseconds)
+{
+#ifndef ZXIC_FOR_LLT
+	// ZXIC_UINT32 i = 0;
+
+	ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NONE(milliseconds, 1);
+	// while (--milliseconds != 0)
+	// {
+	//     for (i = 0; i < 600; i++);
+	// }
+	mdelay(milliseconds);
+#endif
+}
+
+/***********************************************************/
+/** LINUX  :毫秒级延时
+    WINDOWS:毫秒级延时
+* @param   millisecond
+*
+* @return
+* @remark  无
+* @see
+* @author  ChenWei10088471      @date  2014/02/07
+************************************************************/
+ZXIC_VOID zxic_comm_msleep(ZXIC_UINT32 millisecond)
+{
+	msleep(millisecond);
+}
+
+/***********************************************************/
+/**获取时间函数，毫秒
+ * @param   total
+ * @param   masklen
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  ChenWei10088471      @date  2014/02/07
+ ************************************************************/
+ZXIC_DOUBLE zxic_comm_get_ticks_ms(ZXIC_VOID)
+{
+	struct timespec64 tv = { 0 };
+	get_timespec64(&tv, ZXIC_NULL);
+	return (ZXIC_DOUBLE)1000 * tv.tv_sec + (ZXIC_DOUBLE)tv.tv_nsec / 1000;
+}
+#endif
+
+#if ZXIC_REAL("字节序")
+/***********************************************************/
+/** 判断CPU的大小端字节序
+ * @param   ZXIC_VOID
+ *
+ * @return  0-小端；1-大端
+ * @remark  无
+ * @see
+ * @author  ChenWei10088471      @date  2014/02/07
+ ************************************************************/
+ZXIC_RTN32 zxic_comm_is_big_endian(ZXIC_VOID)
+{
+	ZXIC_ENDIAN_U c_data;
+
+	c_data.a = 1;
+
+	if (c_data.b == 1) {
+		return 0;
+	} else {
+		return 1;
+	}
+}
+
+/***********************************************************/
+/** 字节序转换，以4字节为单位进行转序
+ * @param   p_uc_data
+ * @param   dw_byte_len
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  ChenWei10088471      @date  2014/02/07
+ ************************************************************/
+ZXIC_VOID zxic_comm_swap(ZXIC_UINT8 *p_uc_data, ZXIC_UINT32 dw_byte_len)
+{
+	ZXIC_UINT32 dw_byte_num = 0;
+	ZXIC_UINT8 uc_byte_mode = 0;
+	ZXIC_UINT32 uc_is_big_flag = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT16 *p_w_tmp = ZXIC_NULL;
+	ZXIC_UINT32 *p_dw_tmp = ZXIC_NULL;
+
+	if (g_zxic_byte_swap_en) {
+		p_dw_tmp = (ZXIC_UINT32 *)(p_uc_data);
+
+		uc_is_big_flag = zxic_comm_is_big_endian();
+
+		if (uc_is_big_flag) {
+			return;
+		} else {
+			dw_byte_num = dw_byte_len >> 2;
+			uc_byte_mode = dw_byte_len % 4 & 0xff;
+
+			for (i = 0; i < dw_byte_num; i++) {
+				(*p_dw_tmp) = ZXIC_COMM_CONVERT32(*p_dw_tmp);
+				p_dw_tmp++;
+			}
+
+			if (uc_byte_mode > 1) {
+				p_w_tmp = (ZXIC_UINT16 *)(p_dw_tmp);
+				(*p_w_tmp) = ZXIC_COMM_CONVERT16(*p_w_tmp);
+			}
+		}
+	}
+
+	return;
+}
+
+/***********************************************************/
+/** WORD32拼装成WORD64
+ * @param   hi   高32bit
+ * @param   lo   低32bit
+ *
+ * @return  WORD64
+ * @remark  无
+ * @see
+ * @author  pj      @date  2019/10/22
+ ************************************************************/
+ZXIC_UINT64 ZXIC_COMM_COUNTER64_BUILD(ZXIC_UINT32 hi, ZXIC_UINT32 lo)
+{
+	ZXIC_UINT64 value = hi;
+
+	value = value << 32;
+	value = value | lo;
+
+	return value;
+}
+#endif
+
+#if ZXIC_REAL("bit操作")
+/***********************************************************/
+/** 将数据写入缓存区的指定bit位置，一次只能写入32bit的数据
+    p_base的低字节存放数据的低比特，高字节存放数据的高比特。
+* @param   p_base 数据缓存区指针
+* @param   base_size_bit 缓存总的bit位宽
+* @param   data 数据, 比特顺序左低右高，小端比特序
+* @param   start_bit 起始bit位置(必须小于结束bit位置)
+* @param   end_bit 结束bit位置
+*
+* @return
+* @remark  exp:
+	ZXIC_UINT8 data0[4] = {0x22, 0x44, 0x66, 0x88};
+	zxic_comm_write_bits(data0, 32, 0xAABBCC, 0,23);
+	ZXIC_COMM_PRINT("0x%02X %02X %02X %02X \n", data0[0], data0[1], data0[2], data0[3]);
+	输出:0xAA BB CC 88
+
+* @see
+* @author  ChenWei10088471      @date  2014/02/07
+************************************************************/
+ZXIC_RTN32 zxic_comm_write_bits(ZXIC_UINT8 *p_base, ZXIC_UINT32 base_size_bit,
+								ZXIC_UINT32 data, ZXIC_UINT32 start_bit,
+								ZXIC_UINT32 end_bit)
+{
+	ZXIC_UINT32 len = 0;
+	ZXIC_UINT32 start_byte_index = 0;
+	ZXIC_UINT32 end_byte_index = 0;
+	ZXIC_UINT8 mask_value = 0;
+	ZXIC_UINT32 byte_num = 0;
+	ZXIC_UINT32 buffer_size = 0;
+
+	if (0 != (base_size_bit % 8)) {
+		ZXIC_COMM_TRACE_ERROR("\n buffer must be:%d", __LINE__);
+		// assert(0);
+		return ZXIC_BIT_STREAM_INDEX_ERR;
+	}
+
+	if (start_bit > end_bit) {
+		ZXIC_COMM_TRACE_ERROR("\nend_bit cannot be less than start_bit:%d",
+							  __LINE__);
+		// assert(0);
+		return ZXIC_BIT_STREAM_INDEX_ERR;
+	}
+
+	if (base_size_bit < end_bit) {
+		ZXIC_COMM_TRACE_ERROR(
+				"\nend_bit exceeds the base_size!line:%d,base_size_bit:%d end_bit:%d",
+				__LINE__, base_size_bit, end_bit);
+		// assert(0);
+		return ZXIC_BIT_STREAM_INDEX_ERR;
+	}
+
+	ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(end_bit, start_bit);
+	ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(end_bit - start_bit, 1);
+
+	len = end_bit - start_bit + 1;
+	buffer_size = base_size_bit / 8;
+
+	/*寄存器位宽需要时2的次方，如不是，需要累加到最近的2的次方*/
+	/*用于解决KW检查中zxic_comm_write_bits_ex出现的内存泄漏错误*/
+	ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(buffer_size, 1);
+	ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(buffer_size, 1);
+
+	while (0 != (buffer_size & (buffer_size - 1))) {
+		buffer_size += 1;
+	}
+
+	if (buffer_size != base_size_bit / 8) {
+		ZXIC_COMM_TRACE_ALL("\n buffer size[0x%x] is not 2^n: add up to [0x%x]",
+							base_size_bit / 8, buffer_size);
+	}
+
+	/*一次只能写32bit*/
+	ZXIC_COMM_CHECK_INDEX(len, 1, 32);
+
+	if (data > (ZXIC_UINT32)(0xffffffff >> (32 - len))) {
+		ZXIC_COMM_PRINT(
+				"\nValue is too big to write in the bit field!:%d,data:%x,len:%x",
+				__LINE__, data, (ZXIC_UINT32)(0xffffffff >> (32 - len)));
+		return ZXIC_BIT_STREAM_DATA_TOO_BIG;
+	}
+
+	end_byte_index = (end_bit >> 3);
+	start_byte_index = (start_bit >> 3);
+
+	if (start_byte_index == end_byte_index) {
+		mask_value = ((0xFE << (7 - (start_bit & 7))) & 0xff);
+		mask_value |= (((1 << (7 - (end_bit & 7))) - 1) & 0xff);
+		p_base[end_byte_index] &= mask_value;
+		p_base[end_byte_index] |= (((data << (7 - (end_bit & 7)))) & 0xff);
+		return ZXIC_OK;
+	}
+
+	if (7 != (end_bit & 7)) {
+		mask_value = ((0x7f >> (end_bit & 7)) & 0xff);
+		p_base[end_byte_index] &= mask_value;
+		p_base[end_byte_index] |= ((data << (7 - (end_bit & 7))) & 0xff);
+		end_byte_index--;
+		data >>= 1 + (end_bit & 7);
+	}
+
+	for (byte_num = end_byte_index; byte_num > start_byte_index; byte_num--) {
+		/* critical */
+		p_base[byte_num & (buffer_size - 1)] = data & 0xff;
+		data >>= 8;
+	}
+
+	mask_value = ((0xFE << (7 - (start_bit & 7))) & 0xff);
+	p_base[byte_num] &= mask_value;
+	p_base[byte_num] |= data;
+
+	return ZXIC_OK;
+}
+
+/***********************************************************/
+/** 从缓存区中读取指定bit位置的数据，一次最多只能读32bit
+* @param   p_base 数据缓存区指针
+* @param   base_size_bit 缓存区总的bit位宽
+* @param   p_data 返回数据的指针
+* @param   start_bit 起始bit位置(必须小于结束bit位置)
+* @param   end_bit 结束bit位置
+*
+* @return
+* @remark  exp:
+	ZXIC_UINT8  data0[4] = {0x22, 0x44, 0x66, 0x88};
+	ZXIC_UINT32 test_a = 0;
+	zxic_comm_read_bits(data0, 32, &test_a, 0, 23);
+	输出: test_a = 0x224466
+* @see
+* @author  ChenWei10088471      @date  2014/02/07
+************************************************************/
+ZXIC_RTN32 zxic_comm_read_bits(ZXIC_UINT8 *p_base, ZXIC_UINT32 base_size_bit,
+							   ZXIC_UINT32 *p_data, ZXIC_UINT32 start_bit,
+							   ZXIC_UINT32 end_bit)
+{
+	ZXIC_UINT32 len = 0;
+	ZXIC_UINT32 start_byte_index = 0;
+	ZXIC_UINT32 end_byte_index = 0;
+	ZXIC_UINT32 byte_num = 0;
+	ZXIC_UINT32 buffer_size = 0;
+
+	if (0 != (base_size_bit % 8)) {
+		ZXIC_COMM_TRACE_ERROR("\n buffer must be:%d", __LINE__);
+		return ZXIC_BIT_STREAM_INDEX_ERR;
+	}
+
+	if (start_bit > end_bit) {
+		ZXIC_COMM_TRACE_ERROR("\nend_bit cannot be less than start_bit:%d",
+							  __LINE__);
+		return ZXIC_BIT_STREAM_INDEX_ERR;
+	}
+
+	if (base_size_bit < end_bit) {
+		ZXIC_COMM_TRACE_ERROR("\nend_bit exceeds the base_size:%d,end_bit:%d",
+							  __LINE__, end_bit);
+		return ZXIC_BIT_STREAM_INDEX_ERR;
+	}
+
+	len = end_bit - start_bit + 1;
+	buffer_size = base_size_bit / 8;
+
+	/*寄存器位宽需要时2的次方，如不是，需要累加到最近的2的次方*/
+	/*用于解决KW检查中zxic_comm_read_bits_ex出现的内存泄漏错误*/
+	ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(buffer_size, 1);
+
+	while (0 != (buffer_size & (buffer_size - 1))) {
+		buffer_size += 1;
+	}
+
+	if (buffer_size != base_size_bit / 8) {
+		ZXIC_COMM_TRACE_ALL("\n buffer size[0x%x] is not 2^n: add up to [0x%x]",
+							base_size_bit / 8, buffer_size);
+	}
+
+	/*先将返回的数据清零*/
+	*p_data = 0;
+
+	/*一次最多只能读32bit*/
+	ZXIC_COMM_CHECK_INDEX(len, 1, 32);
+
+	end_byte_index = (end_bit >> 3);
+	start_byte_index = (start_bit >> 3);
+
+	if (start_byte_index == end_byte_index) {
+		*p_data = (ZXIC_UINT32)(
+				((p_base[start_byte_index] >> (7U - (end_bit & 7))) &
+				 (0xff >> (8U - len))) &
+				0xff);
+		return ZXIC_OK;
+	}
+
+	if (start_bit & 7) {
+		*p_data = (p_base[start_byte_index] & (0xff >> (start_bit & 7))) &
+				  ZXIC_UINT8_MASK;
+		start_byte_index++;
+	}
+
+	for (byte_num = start_byte_index; byte_num < end_byte_index; byte_num++) {
+		*p_data <<= 8;
+
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(*p_data, p_base[byte_num]);
+		*p_data += p_base[byte_num];
+	}
+
+	*p_data <<= 1 + (end_bit & 7);
+	/* critical */
+	ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(*p_data,
+									   (((p_base[byte_num & (buffer_size - 1)] &
+										  (0xff << (7 - (end_bit & 7)))) >>
+										 (7 - (end_bit & 7))) &
+										0xff));
+	*p_data += ((p_base[byte_num & (buffer_size - 1)] &
+				 (0xff << (7 - (end_bit & 7)))) >>
+				(7 - (end_bit & 7))) &
+			   0xff;
+
+	return ZXIC_OK;
+}
+
+/***********************************************************/
+/** 比特流拼装，比特流的形式为: p_base的低字节存放
+    数据的高比特，高字节存放数据的低比特。
+* @param   p_base
+* @param   base_size_bit
+* @param   data           数据, 比特顺序左高右低，大端比特序
+* @param   msb_start_pos  数据最高比特的位置
+* @param   len            数据长度
+*
+* @return
+* @remark  exp:
+	ZXIC_UINT8 data0[4] = {0x22, 0x44, 0x66, 0x88};
+	zxic_comm_write_bits_ex(data0, 32, 0x123456, 23,24);
+	ZXIC_COMM_PRINT("0x%02X %02X %02X %02X \n", data0[0], data0[1], data0[2], data0[3]);
+	输出：0x22 12 34 56
+
+* @see
+* @author  王春雷      @date  2014/03/08
+************************************************************/
+ZXIC_RTN32 zxic_comm_write_bits_ex(ZXIC_UINT8 *p_base,
+								   ZXIC_UINT32 base_size_bit, ZXIC_UINT32 data,
+								   ZXIC_UINT32 msb_start_pos, ZXIC_UINT32 len)
+{
+	ZXIC_RTN32 rtn = ZXIC_OK;
+	ZXIC_COMM_CHECK_POINT(p_base);
+
+	ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(base_size_bit, 1);
+	ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(base_size_bit - 1, msb_start_pos);
+	ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(base_size_bit - 1 - msb_start_pos, len);
+	ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(base_size_bit - 1 - msb_start_pos + len,
+									   1);
+
+	rtn = zxic_comm_write_bits(p_base, base_size_bit, data,
+							   (base_size_bit - 1 - msb_start_pos),
+							   (base_size_bit - 1 - msb_start_pos + len - 1));
+
+	return rtn;
+}
+
+/***********************************************************/
+/** 从比特流中读取数据，比特流的形式为: p_base的低字节存放
+    数据的高比特，高字节存放数据的低比特。
+* @param   p_base
+* @param   base_size_bit
+* @param   p_data
+* @param   msb_start_pos
+* @param   len
+*
+* @return
+* @remark  exp:
+	ZXIC_UINT8 data0[4] = {0x22, 0x44, 0x66, 0x88};
+	zxic_comm_read_bits_ex(data0, 32, &test_a, 23, 24);
+	ZXIC_COMM_PRINT("0test_a = 0x%x \n", test_a);
+	输出: 0test_a = 0x446688
+
+* @see
+* @author  王春雷      @date  2014/03/08
+************************************************************/
+ZXIC_RTN32 zxic_comm_read_bits_ex(ZXIC_UINT8 *p_base, ZXIC_UINT32 base_size_bit,
+								  ZXIC_UINT32 *p_data,
+								  ZXIC_UINT32 msb_start_pos, ZXIC_UINT32 len)
+{
+	ZXIC_RTN32 rtn = ZXIC_OK;
+	ZXIC_COMM_CHECK_POINT(p_base);
+	ZXIC_COMM_CHECK_POINT(p_data);
+
+	ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(base_size_bit, 1);
+	ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(base_size_bit - 1, msb_start_pos);
+	ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW(base_size_bit - 1 - msb_start_pos, len);
+	ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(base_size_bit - 1 - msb_start_pos + len,
+									   1);
+
+	rtn = zxic_comm_read_bits(p_base, base_size_bit, p_data,
+							  (base_size_bit - 1 - msb_start_pos),
+							  (base_size_bit - 1 - msb_start_pos + len - 1));
+	return rtn;
+}
+#endif /*  */
+
+#if ZXIC_REAL("字符串")
+/***********************************************************/
+/**
+ * @param   buffer   目标字符串
+ * @param   sizeofbuf  sizeofbuffer
+ * @param   count  要拷贝字节数
+ * @param   format
+ *
+ * @return  待拷贝的实际字符串长度
+ * @remark  snprintf
+ * @see
+ * @author  sj      @date  2020/12/09
+ ************************************************************/
+ZXIC_SINT32 ic_comm_snprintf_s(ZXIC_CHAR *buffer, ZXIC_SIZE_T sizeofbuf,
+							   ZXIC_SIZE_T count, const ZXIC_CHAR *format, ...)
+{
+	va_list ap;
+	ZXIC_SINT32 ret = -1;
+
+	if ((ZXIC_NULL == buffer) || (ZXIC_NULL == format)) {
+		ZXIC_COMM_TRACE_ERROR(
+				"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", __FILE__,
+				__LINE__, __FUNCTION__);
+		return ret;
+	}
+	if (!count) {
+		ZXIC_COMM_TRACE_ERROR(
+				"\n ZXIC %s:%d[Error:count err], FUNCTION : %s!\n", __FILE__,
+				__LINE__, __FUNCTION__);
+		return ret;
+	}
+	va_start(ap, format);
+	ret = ZXIC_COMM_VSNPRINTF_S(buffer, sizeofbuf, count, format, ap);
+	va_end(ap);
+
+	if (ret == -1) {
+		ZXIC_COMM_TRACE_ERROR(
+				"\n ZXIC %s:%d[Error:snprintf_s err], FUNCTION : %s!\n",
+				__FILE__, __LINE__, __FUNCTION__);
+	}
+	return ret;
+}
+/***********************************************************/
+/**
+ * @param   buffer   目标字符串
+ * @param   sizeofbuf  sizeofbuffer
+ * @param   count  要拷贝字节数
+ * @param   format
+ *
+ * @return  待拷贝的实际字符串长度
+ * @remark  vsnprintf
+ * @see
+ * @author  sj      @date  2020/12/09
+ ************************************************************/
+ZXIC_SINT32 ic_comm_vsnprintf_s(ZXIC_CHAR *buffer, ZXIC_SIZE_T sizeofbuf,
+								ZXIC_SIZE_T count, const ZXIC_CHAR *format,
+								va_list ap)
+{
+	ZXIC_SINT32 ret = -1;
+
+	if ((ZXIC_NULL == buffer) || (ZXIC_NULL == format)) {
+		ZXIC_COMM_TRACE_ERROR(
+				"\n ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", __FILE__,
+				__LINE__, __FUNCTION__);
+		return ret;
+	}
+	if (!count) {
+		ZXIC_COMM_TRACE_ERROR(
+				"\n ZXIC %s:%d[Error:count err], FUNCTION : %s!\n", __FILE__,
+				__LINE__, __FUNCTION__);
+		return ret;
+	}
+	if (count < sizeofbuf) {
+		sizeofbuf = count;
+	}
+	ret = vsnprintf(buffer, sizeofbuf, format, ap);
+	if (ret == -1) {
+		ZXIC_COMM_TRACE_ERROR(
+				"\n ZXIC %s:%d[Error:vsnprintf err], FUNCTION : %s!\n",
+				__FILE__, __LINE__, __FUNCTION__);
+	}
+	return ret;
+}
+
+/***********************************************************/
+/**
+ * @param   pcDst 　　 目的地址
+ * @param   dwMaxSize　目的长度
+ * @param   pcSrc 　　 源地址
+ * @param   dwCount　  要复制的最大字符数
+ *
+ * @return
+ * @remark  将源地址的字符拷贝到目的字符数组;
+ * @see
+ * @author
+ ************************************************************/
+ZXIC_CHAR *ic_comm_strncpy_s(ZXIC_CHAR *pcDst, size_t dwMaxSize,
+							 ZXIC_CONST ZXIC_CHAR *pcSrc, size_t dwCount)
+{
+	size_t dwIndex = 1, dwCopyNum = dwCount;
+	ZXIC_CHAR *pcResult = pcDst;
+
+	ZXIC_COMM_CHECK_RC_POINT_NO_PRINT(pcDst, pcResult);
+	ZXIC_COMM_CHECK_RC_POINT_NO_PRINT(pcSrc, pcResult);
+
+	if ((dwMaxSize <= 1) || (dwMaxSize > ZXIC_COMM_MEMORY_MAX_B_SIZE) ||
+		(dwCount == 0)) {
+		return pcResult;
+	}
+
+	/* 计算拷贝的字符长度，不含结束符 */
+	if (dwCount >= dwMaxSize) {
+		dwCopyNum = dwMaxSize - 1;
+	}
+
+	if (ic_comm_getAbsValue((unsigned ZXIC_CHAR *)pcDst,
+							(ZXIC_CONST ZXIC_UINT8 *)pcSrc) < dwCopyNum) {
+		return pcResult;
+	}
+
+	while ('\0' != (*pcDst++ = *pcSrc++)) {
+		/* 判断拷贝字符数是否等于dwCopyNum，等于就退出 */
+		/* 由于判断放在循环体内，进行判断前已经拷贝了一次，所以i初试值为1 */
+		if (dwIndex++ >= dwCopyNum) {
+			*pcDst = '\0';
+
+			return pcResult;
+		}
+	}
+
+	/* 本处的处理是为了保持和库函数中的解释一致，对于源串长度小于dwCopyNum，剩余部分全部填0 */
+	while (dwIndex++ <= dwCopyNum) {
+		*pcDst++ = '\0';
+	}
+
+	return pcResult;
+}
+
+ZXIC_SIZE_T ic_comm_getAbsValue(ZXIC_UINT8 *dest, ZXIC_CONST ZXIC_UINT8 *src)
+{
+	return dest > src ? (dest - src) : (src - dest);
+}
+/***********************************************************/
+/**
+ * @param   dest 　　目的地址
+ * @param   src 　源地址
+ * @param   n　　 要复制的长度
+ *
+ * @return
+ * @remark  从源地址拷贝若干字节的长度到目的内存处
+ * @see
+ * @author
+ ************************************************************/
+ZXIC_RTN32 ic_comm_memcpy(ZXIC_VOID *dest, ZXIC_CONST ZXIC_VOID *src, size_t n)
+{
+	ZXIC_COMM_CHECK_POINT(dest);
+	ZXIC_COMM_CHECK_POINT(src);
+
+	/* memcpy 的大小限制在200M */
+	if (n > 200 * 1024 * 1024) {
+		return ZXIC_PAR_CHK_INVALID_PARA;
+	}
+
+	if (ic_comm_getAbsValue((ZXIC_UINT8 *)dest, (ZXIC_CONST ZXIC_UINT8 *)src) <
+		n) {
+		return ZXIC_ERR;
+	}
+	memcpy(dest, src, n);
+	return ZXIC_OK;
+}
+/***********************************************************/
+/**
+ * @param   dest 　　目的地址
+ * @param   dest_len　目的长度
+ * @param   src 　源地址
+ * @param   n　　 要复制的长度
+ *
+ * @return
+ * @remark  从源地址拷贝若干字节的长度到目的内存处,增加源目的长度之间的检查
+ * @see
+ * @author
+ ************************************************************/
+ZXIC_RTN32 ic_comm_memcpy_s(ZXIC_VOID *dest, size_t dest_len, const void *src,
+							size_t n)
+{
+	ZXIC_COMM_CHECK_POINT(dest);
+	ZXIC_COMM_CHECK_POINT(src);
+
+	/* memcpy 的大小限制在200M */
+	if (n > 200 * 1024 * 1024) {
+		return ZXIC_PAR_CHK_INVALID_PARA;
+	}
+
+	if (ic_comm_getAbsValue((ZXIC_UINT8 *)dest, (ZXIC_CONST ZXIC_UINT8 *)src) <
+		n) {
+		return ZXIC_PAR_CHK_ARGIN_ERROR;
+	}
+	memcpy(dest, src, n);
+	return ZXIC_OK;
+}
+
+/***********************************************************/
+/**
+ * @param   pcDst 　　 目的地址
+ * @param   dwMaxSize　目的长度
+ * @param   pcSrc 　　 源地址
+ * @param   dwCount 　 待连接的字符数
+ *
+ * @return
+ * @remark  字符串连接函数，将pcSrc的dwCount字符复制到pcDst的字符串后，覆盖"\0";
+ * @see
+ * @author
+ ************************************************************/
+ZXIC_CHAR *ic_comm_strncat_s(ZXIC_CHAR *pcDst, size_t dwMaxSize,
+							 ZXIC_CONST ZXIC_CHAR *pcSrc, size_t dwCount)
+{
+	ZXIC_SIZE_T dwIndex = 1, dwCopyNum = 0;
+	ZXIC_CHAR *pcResult = pcDst;
+
+	ZXIC_COMM_CHECK_RC_POINT_NO_PRINT(pcDst, pcResult);
+	ZXIC_COMM_CHECK_RC_POINT_NO_PRINT(pcSrc, pcResult);
+
+	if ((dwMaxSize == 0) || (dwMaxSize > ZXIC_COMM_MEMORY_MAX_B_SIZE) ||
+		(dwCount == 0)) {
+		return pcResult;
+	}
+
+	/* 计算目的串的长度 */
+	while ((*pcDst++ != '\0') && (++dwCopyNum < dwMaxSize)) {
+	}
+
+	if (dwCopyNum >= dwMaxSize) {
+		return pcResult;
+	}
+
+	dwCopyNum = dwMaxSize - dwCopyNum; /* 计算剩余的缓冲区长度 */
+
+	/* 计算拷贝的字符长度，不含结束符 */
+	if (dwCount >= dwCopyNum) {
+		dwCopyNum = dwCopyNum - 1;
+	} else {
+		dwCopyNum = dwCount;
+	}
+
+	if (dwCopyNum == 0) {/* 宋志强 修正pcDst 空间刚好满导致内存越界的问题 */
+		return pcResult;
+	}
+
+	pcDst--;
+
+	if (ic_comm_getAbsValue((unsigned ZXIC_CHAR *)pcDst,
+							(const unsigned ZXIC_CHAR *)pcSrc) < dwCopyNum) {
+		return pcResult;
+	}
+
+	while ('\0' != (*pcDst++ = *pcSrc++)) {
+		/* 判断拷贝字符数是否等于dwCopyNum，等于就退出 */
+		/* 由于判断放在循环体内，进行判断前已经拷贝了一次，所以i初试值为1 */
+		if (dwIndex++ >= dwCopyNum) {
+			*pcDst = '\0';
+
+			return pcResult;
+		}
+	}
+
+	/* 本处的处理是为了保持和库函数中的解释一致，对于源串长度小于dwCopyNum，剩余部分全部填0 */
+	while (dwIndex++ <= dwCopyNum) {
+		*pcDst++ = '\0';
+	}
+
+	return pcResult;
+}
+
+/***********************************************************/
+/**
+ * @param   str 　　字符串首地址
+ * @param   MaxCount　可返回的最大长度,若计算的长度大于该长度，则返回MaxCount；
+ *
+ * @return
+ * @remark  计算字符串的长度
+ * @see
+ * @author
+ ************************************************************/
+ZXIC_SIZE_T ic_comm_strnlen_s(const ZXIC_CHAR *str, ZXIC_SIZE_T MaxCount)
+{
+	return (str == 0) ? 0 : ZXIC_COMM_STRNLEN(str, MaxCount);
+}
+
+ZXIC_VOID ic_comm_memset_s(void *dest, ZXIC_SIZE_T dmax, ZXIC_UINT8 c,
+						   ZXIC_SIZE_T n)
+{
+	if ((ZXIC_NULL == dest) || (dmax > ZXIC_COMM_MEMORY_MAX_B_SIZE) ||
+		(0 == n) || (n > dmax)) {
+		ZXIC_COMM_TRACE_ERROR(
+				"zxic_memset_s para err:ptr is null or size err.\n");
+		return;
+	}
+	memset(dest, c, n);
+}
+
+ZXIC_SINT32 ic_comm_memcmp(void *str1, const void *str2, ZXIC_SIZE_T n)
+{
+	if ((ZXIC_NULL == str1) || (ZXIC_NULL == str2) ||
+		(n > ZXIC_COMM_MEMORY_MAX_B_SIZE) || (0 == n)) {
+		ZXIC_COMM_TRACE_ERROR(
+				"zxic_memcmp para err:ptr is null or size more than 200M.\n");
+		return 0x7fffffff;
+	}
+	return memcmp(str1, str2, n);
+}
+#endif
+
+ZXIC_RTN32 zxic_comm_random(ZXIC_VOID)
+{
+	ZXIC_UINT8 buff[4] = { 0 };
+	ZXIC_UINT32 ticks = 0;
+	ZXIC_UINT32 random_d = 0;
+	struct timespec64 tv;
+	struct file *fd = NULL;
+	loff_t pos = 0;
+
+	// fd =  open("/dev/urandom", O_RDONLY);
+	fd = filp_open("/dev/urandom", O_RDONLY, 0);
+
+	if (NULL == fd) {
+		get_timespec64(&tv, ZXIC_NULL);
+		ticks = ((tv.tv_sec & ZXIC_UINT32_MAX) +
+				 (tv.tv_nsec & ZXIC_UINT32_MAX)) &
+				ZXIC_UINT32_MAX;
+		random_d = ticks;
+	} else if (((kernel_read(fd, buff, ZXIC_SIZEOF(buff), &pos) &
+							  0xFFFFFFFF)) != ZXIC_SIZEOF(buff)) {
+		get_timespec64(&tv, ZXIC_NULL);
+		ticks = ((tv.tv_sec & ZXIC_UINT32_MAX) +
+				 (tv.tv_nsec & ZXIC_UINT32_MAX)) &
+				ZXIC_UINT32_MAX;
+		random_d = ticks;
+		filp_close(fd, NULL);
+	} else {
+		random_d = (((buff[0] << 24) & 0xff000000) |
+					((buff[1] << 16) & 0x00ff0000) |
+					((buff[2] << 8) & 0x0000ff00) | (buff[3] & 0x000000ff));
+		filp_close(fd, NULL);
+	}
+
+	return random_d;
+}
+
+/***********************************************************/
+/** 设置最大通道数
+ * @param   dev_max      设置的最大设备数
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  lihk      @date  2021/03/31
+ ************************************************************/
+ZXIC_VOID zxic_comm_channel_max_set(ZXIC_UINT32 dev_max)
+{
+	g_zxic_comm_channel_max = dev_max;
+}
+
+/***********************************************************/
+/** 获取最大通道数
+ * @param
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  lihk      @date  2021/03/31
+ ************************************************************/
+ZXIC_RTN32 zxic_comm_channel_max_get(ZXIC_VOID)
+{
+	return g_zxic_comm_channel_max;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_private_top.c b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_private_top.c
index 8e5d260137d1e239bc17f702e1afad0f762844dc..2d0a48140fd9ddf1c9da0b624a4a08b080bb7fa6 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_private_top.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/comm/source/zxic_private_top.c
@@ -1,148 +1,116 @@
-/**************************************************************
-* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司
-* 文件名称 : zxic_common.c
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者   : xuchenxi_10235594
-* 完成日期 : 2020/07/20
-* DEPARTMENT: 有线开发四部-系统软件团队
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-#include "zxic_private_top.h"
-#include "zxic_common.h"
-#include <linux/ctype.h>
-//#include <stdlib.h>
-//#include <stdio.h>
-#include <linux/stddef.h>
-#include <linux/string.h>
-#include <linux/errno.h>
-//#include <assert.h>
-//#include <linux/stdarg.h>
-//#include <linux/math.h>
-#include <linux/stat.h>
-
-#ifdef ZXIC_OS_WIN
-#include <Windows.h>
-#include <time.h>
-#include <direct.h>
-#include <io.h>
-#pragma warning (disable:4996)
-#else
-//#include <unistd.h>
-#include <linux/types.h>
-#include <linux/socket.h>
-#include <linux/selection.h>
-#include <linux/time.h>
-#include <linux/wait.h>
-#include <linux/kthread.h>
-#include <linux/fcntl.h>
-#endif 
-
-#if ZXIC_REAL("参数检查函数定义")
-/***********************************************************/
-/**
-* @param   val
-* @param   min
-* @param   max
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2019/07/13
-************************************************************/
-ZXIC_RTN32 zxic_comm_index_check(ZXIC_UINT32 val, ZXIC_UINT32 min, ZXIC_UINT32 max)
-{
-    if (min <= max)
-    {
-        if (0 == min)
-        {
-            if ((val) > (max))
-            {
-                return ZXIC_PAR_CHK_INVALID_INDEX;
-            }
-        }
-        else
-        {
-            if ((val) < (min) || (val) > (max))
-            {
-                return ZXIC_PAR_CHK_INVALID_INDEX;
-            }
-        }
-    }
-    else
-    {
-        return ZXIC_PAR_CHK_INVALID_RANGE;
-    }
-
-    return ZXIC_OK;
-}
-
-/***********************************************************/
-/**
-* @param   dev_id
-* @param   val
-* @param   min
-* @param   max
-*
-* @return
-* @remark  无
-* @see
-* @author  PJ      @date  2019/07/13
-************************************************************/
-ZXIC_RTN32 zxic_comm_dev_index_check(ZXIC_UINT32 dev_id, 
-                                     ZXIC_UINT32 val, 
-                                     ZXIC_UINT32 min, 
-                                     ZXIC_UINT32 max)
-{
-    if (min <= max)
-    {
-        if (0 == min)
-        {
-            if ((val) > (max))
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ZXIC %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);
-                return ZXIC_PAR_CHK_INVALID_INDEX;
-            }
-        }
-        else
-        {
-            if ((val) < (min) || (val) > (max))
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ZXIC %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);
-                return ZXIC_PAR_CHK_INVALID_INDEX;
-            }
-        }
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ZXIC %s:%d[Error:RANGE INVALID] [val=0x%x,min=0x%x,max=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, val, min, max, __FUNCTION__);
-        return ZXIC_PAR_CHK_INVALID_RANGE;
-    }
-
-    return ZXIC_OK;
-}
-
-#endif
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+/**************************************************************
+* 版权所有 (C)2013-2020, 深圳市中兴通讯股份有限公司
+* 文件名称 : zxic_common.c
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者   : xuchenxi_10235594
+* 完成日期 : 2020/07/20
+* DEPARTMENT: 有线开发四部-系统软件团队
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#include "zxic_private_top.h"
+#include "zxic_common.h"
+#include <linux/ctype.h>
+//#include <stdlib.h>
+//#include <stdio.h>
+#include <linux/stddef.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+//#include <assert.h>
+//#include <linux/stdarg.h>
+//#include <linux/math.h>
+#include <linux/stat.h>
+//#include <unistd.h>
+#include <linux/types.h>
+#include <linux/socket.h>
+#include <linux/selection.h>
+#include <linux/time.h>
+#include <linux/wait.h>
+#include <linux/kthread.h>
+#include <linux/fcntl.h>
+
+#if ZXIC_REAL("参数检查函数定义")
+/***********************************************************/
+/**
+ * @param   val
+ * @param   min
+ * @param   max
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XXX      @date  2019/07/13
+ ************************************************************/
+ZXIC_RTN32 zxic_comm_index_check(ZXIC_UINT32 val, ZXIC_UINT32 min,
+								 ZXIC_UINT32 max)
+{
+	if (min <= max) {
+		if (0 == min) {
+			if ((val) > (max)) {
+				return ZXIC_PAR_CHK_INVALID_INDEX;
+			}
+		} else {
+			if ((val) < (min) || (val) > (max)) {
+				return ZXIC_PAR_CHK_INVALID_INDEX;
+			}
+		}
+	} else {
+		return ZXIC_PAR_CHK_INVALID_RANGE;
+	}
+
+	return ZXIC_OK;
+}
+
+/***********************************************************/
+/**
+ * @param   dev_id
+ * @param   val
+ * @param   min
+ * @param   max
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  PJ      @date  2019/07/13
+ ************************************************************/
+ZXIC_RTN32 zxic_comm_dev_index_check(ZXIC_UINT32 dev_id, ZXIC_UINT32 val,
+									 ZXIC_UINT32 min, ZXIC_UINT32 max)
+{
+	if (min <= max) {
+		if (0 == min) {
+			if ((val) > (max)) {
+				ZXIC_COMM_TRACE_DEV_ERROR(
+						dev_id,
+						"ZXIC %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n",
+						__FILE__, __LINE__, val, min, max, __FUNCTION__);
+				return ZXIC_PAR_CHK_INVALID_INDEX;
+			}
+		} else {
+			if ((val) < (min) || (val) > (max)) {
+				ZXIC_COMM_TRACE_DEV_ERROR(
+						dev_id,
+						"ZXIC %s:%d[Error:VALUE[0x%x] INVALID] [min=0x%x,max=0x%x] ! FUNCTION :%s !\n",
+						__FILE__, __LINE__, val, min, max, __FUNCTION__);
+				return ZXIC_PAR_CHK_INVALID_INDEX;
+			}
+		}
+	} else {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id,
+				"ZXIC %s:%d[Error:RANGE INVALID] [val=0x%x,min=0x%x,max=0x%x] ! FUNCTION :%s !\n",
+				__FILE__, __LINE__, val, min, max, __FUNCTION__);
+		return ZXIC_PAR_CHK_INVALID_RANGE;
+	}
+
+	return ZXIC_OK;
+}
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/dpp_kshell b/src/net/drivers/net/ethernet/dinghai/en_np/dpp_kshell
old mode 100755
new mode 100644
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_acl.h b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_acl.h
index 340d346172e2bb5dba8546d5070c952d155479f1..1a21c95ce6f9481f8be60f173715a49794de5199 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_acl.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_acl.h
@@ -24,60 +24,57 @@
 #include "dpp_apt_se_api.h"
 
 /* etcam级联地址划分 */
-#define ZXDH_FD_AS_ERAM_BAADDR              (ZXIC_UINT32)(0x38000)
-#define ZXDH_FD_AS_ERAM_DEPTH               (ZXIC_UINT32)(2048)
+#define ZXDH_FD_AS_ERAM_BAADDR ((ZXIC_UINT32)(0x38000))
+#define ZXDH_FD_AS_ERAM_DEPTH ((ZXIC_UINT32)(2048))
 
-#define ZXDH_IPSEC_ENC_AS_ERAM_BAADDR       (ZXIC_UINT32)(0x38B00)
-#define ZXDH_IPSEC_ENC_AS_ERAM_DEPTH        (ZXIC_UINT32)(1024)
+#define ZXDH_IPSEC_ENC_AS_ERAM_BAADDR ((ZXIC_UINT32)(0x38B00))
+#define ZXDH_IPSEC_ENC_AS_ERAM_DEPTH ((ZXIC_UINT32)(1024))
 
 /* etcam表项 0~7 */
-#define ZXDH_ACL_FD_CFG_ID                  (ZXIC_UINT32)(0)
-#define ZXDH_ACL_TBL_ID1                    (ZXIC_UINT32)(1)
-#define ZXDH_ACL_TBL_ID2                    (ZXIC_UINT32)(2)
-#define ZXDH_ACL_TBL_ID3                    (ZXIC_UINT32)(3)
-#define ZXDH_ACL_TBL_ID4                    (ZXIC_UINT32)(4)
-#define ZXDH_ACL_TBL_ID5                    (ZXIC_UINT32)(5)
-#define ZXDH_ACL_TBL_ID6                    (ZXIC_UINT32)(6)
-#define ZXDH_ACL_TBL_ID7                    (ZXIC_UINT32)(7)
+#define ZXDH_ACL_FD_CFG_ID ((ZXIC_UINT32)(0))
+#define ZXDH_ACL_TBL_ID1 ((ZXIC_UINT32)(1))
+#define ZXDH_ACL_TBL_ID2 ((ZXIC_UINT32)(2))
+#define ZXDH_ACL_TBL_ID3 ((ZXIC_UINT32)(3))
+#define ZXDH_ACL_TBL_ID4 ((ZXIC_UINT32)(4))
+#define ZXDH_ACL_TBL_ID5 ((ZXIC_UINT32)(5))
+#define ZXDH_ACL_TBL_ID6 ((ZXIC_UINT32)(6))
+#define ZXDH_ACL_TBL_ID7 ((ZXIC_UINT32)(7))
 
-typedef struct zxdh_ipsec_enc_key
-{
-    ZXIC_UINT8  dip[16];
-    ZXIC_UINT8  sip[16];
-    ZXIC_UINT32 rsv2;
-    ZXIC_UINT32 rsv1;
-}ZXDH_IPSEC_ENC_KEY;
+typedef struct zxdh_ipsec_enc_key {
+	ZXIC_UINT8 dip[16];
+	ZXIC_UINT8 sip[16];
+	ZXIC_UINT32 rsv2;
+	ZXIC_UINT32 rsv1;
+} ZXDH_IPSEC_ENC_KEY;
 
-typedef struct zxdh_ipsec_enc_mask
-{
-    ZXIC_UINT8  dip[16];
-    ZXIC_UINT8  sip[16];
-    ZXIC_UINT32 rsv2;
-    ZXIC_UINT32 rsv1;
-}ZXDH_IPSEC_ENC_MASK;
+typedef struct zxdh_ipsec_enc_mask {
+	ZXIC_UINT8 dip[16];
+	ZXIC_UINT8 sip[16];
+	ZXIC_UINT32 rsv2;
+	ZXIC_UINT32 rsv1;
+} ZXDH_IPSEC_ENC_MASK;
 
-typedef struct zxdh_ipsec_enc_entry
-{
-    ZXIC_UINT32 sa_id;
-    ZXIC_UINT32 rsv;
-    ZXIC_UINT32 hit_flag;
-}ZXDH_IPSEC_ENC_ENTRY;
+typedef struct zxdh_ipsec_enc_entry {
+	ZXIC_UINT32 sa_id;
+	ZXIC_UINT32 rsv;
+	ZXIC_UINT32 hit_flag;
+} ZXDH_IPSEC_ENC_ENTRY;
 
-typedef struct zxdh_ipsec_enc_t
-{
-    ZXIC_UINT32 index;
-    ZXDH_IPSEC_ENC_KEY key;
-    ZXDH_IPSEC_ENC_MASK mask;
-    ZXDH_IPSEC_ENC_ENTRY entry;
+typedef struct zxdh_ipsec_enc_t {
+	ZXIC_UINT32 index;
+	ZXDH_IPSEC_ENC_KEY key;
+	ZXDH_IPSEC_ENC_MASK mask;
+	ZXDH_IPSEC_ENC_ENTRY entry;
 } ZXDH_IPSEC_ENC_T;
 
-ZXIC_UINT32 dpp_apt_set_ipsec_enc_data(ZXIC_VOID *pData,DPP_ACL_ENTRY_EX_T *aclEntry);
-ZXIC_UINT32 dpp_apt_get_ipsec_enc_data(ZXIC_VOID *pData,DPP_ACL_ENTRY_EX_T *aclEntry);
+ZXIC_UINT32 dpp_apt_set_ipsec_enc_data(ZXIC_VOID *pData,
+									   DPP_ACL_ENTRY_EX_T *aclEntry);
+ZXIC_UINT32 dpp_apt_get_ipsec_enc_data(ZXIC_VOID *pData,
+									   DPP_ACL_ENTRY_EX_T *aclEntry);
 
-typedef struct dpp_acl_init_t
-{
-    ZXIC_UINT32 tbl_num; 
-    DPP_APT_ACL_TABLE_T *acl;
+typedef struct dpp_acl_init_t {
+	ZXIC_UINT32 tbl_num;
+	DPP_APT_ACL_TABLE_T *acl;
 } DPP_ACL_INIT_T;
 
 extern DPP_ACL_INIT_T g_aclTable;
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_eram.h b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_eram.h
index 5b3f0586e1ac20950e24c2ec5e89914d50f74eeb..cc9ad2a59e0ff7e0be20902dbfd169d500f9e377 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_eram.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_eram.h
@@ -23,197 +23,186 @@
 #include "zxic_common.h"
 #include "dpp_apt_se_api.h"
 
-#define ZXDH_VXLAN_ERAM_BAADDR              ((ZXIC_UINT32)(0x8000))
-#define ZXDH_VXLAN_ERAM_DEPTH               ((ZXIC_UINT32)(2))
+#define ZXDH_VXLAN_ERAM_BAADDR ((ZXIC_UINT32)(0x8000))
+#define ZXDH_VXLAN_ERAM_DEPTH ((ZXIC_UINT32)(2))
 
-#define ZXDH_VPORT_ATTR_ERAM_BAADDR         ((ZXIC_UINT32)(0x8001))
-#define ZXDH_VPORT_ATTR_ERAM_DEPTH          ((ZXIC_UINT32)(1280))
+#define ZXDH_VPORT_ATTR_ERAM_BAADDR ((ZXIC_UINT32)(0x8001))
+#define ZXDH_VPORT_ATTR_ERAM_DEPTH ((ZXIC_UINT32)(1280))
 
-#define ZXDH_PANEL_PORT_ATTR_ERAM_BAADDR    ((ZXIC_UINT32)(0x87F9))
-#define ZXDH_PANEL_PORT_ATTR_ERAM_DEPTH     ((ZXIC_UINT32)(16))
+#define ZXDH_PANEL_PORT_ATTR_ERAM_BAADDR ((ZXIC_UINT32)(0x87F9))
+#define ZXDH_PANEL_PORT_ATTR_ERAM_DEPTH ((ZXIC_UINT32)(16))
 
-#define ZXDH_RSS_TO_VQID_ERAM_BAADDR        ((ZXIC_UINT32)(0x8809))
-#define ZXDH_RSS_TO_VQID_ERAM_DEPTH         ((ZXIC_UINT32)(38144))
+#define ZXDH_RSS_TO_VQID_ERAM_BAADDR ((ZXIC_UINT32)(0x8809))
+#define ZXDH_RSS_TO_VQID_ERAM_DEPTH ((ZXIC_UINT32)(38144))
 
-#define ZXDH_VLAN_FILTER_ERAM_BAADDR        ((ZXIC_UINT32)(0x11D09))
-#define ZXDH_VLAN_FILTER_ERAM_DEPTH         ((ZXIC_UINT32)(71680))
+#define ZXDH_VLAN_FILTER_ERAM_BAADDR ((ZXIC_UINT32)(0x11D09))
+#define ZXDH_VLAN_FILTER_ERAM_DEPTH ((ZXIC_UINT32)(71680))
 
-#define ZXDH_LAG_ERAM_BAADDR                ((ZXIC_UINT32)(0x23509))
-#define ZXDH_LAG_ERAM_DEPTH                 ((ZXIC_UINT32)(8))
+#define ZXDH_LAG_ERAM_BAADDR ((ZXIC_UINT32)(0x23509))
+#define ZXDH_LAG_ERAM_DEPTH ((ZXIC_UINT32)(8))
 
-#define ZXDH_BC_ERAM_BAADDR                 ((ZXIC_UINT32)(0x2350D))
-#define ZXDH_BC_ERAM_DEPTH                  ((ZXIC_UINT32)(256))
+#define ZXDH_BC_ERAM_BAADDR ((ZXIC_UINT32)(0x2350D))
+#define ZXDH_BC_ERAM_DEPTH ((ZXIC_UINT32)(256))
 
-#define ZXDH_STAT_PPU_ERAM_BAADDR           ((ZXIC_UINT32)(0x68000))
-#define ZXDH_STAT_PPU_ERAM_DEPTH            ((ZXIC_UINT32)(0x1C000)) // 此数值以64bit为单位
+#define ZXDH_STAT_PPU_ERAM_BAADDR ((ZXIC_UINT32)(0x68000))
+#define ZXDH_STAT_PPU_ERAM_DEPTH ((ZXIC_UINT32)(0x1C000)) // 此数值以64bit为单位
 
-#define ZXDH_DSCP_TO_UP_ERAM_BAADDR         ((ZXIC_UINT32)(0x2370D))
-#define ZXDH_DSCP_TO_UP_ERAM_DEPTH          ((ZXIC_UINT32)(1024))
+#define ZXDH_DSCP_TO_UP_ERAM_BAADDR ((ZXIC_UINT32)(0x2370D))
+#define ZXDH_DSCP_TO_UP_ERAM_DEPTH ((ZXIC_UINT32)(1024))
 
-#define ZXDH_UP_TO_TC_ERAM_BAADDR           ((ZXIC_UINT32)(0x2390D))
-#define ZXDH_UP_TO_TC_ERAM_DEPTH            ((ZXIC_UINT32)(128))
+#define ZXDH_UP_TO_TC_ERAM_BAADDR ((ZXIC_UINT32)(0x2390D))
+#define ZXDH_UP_TO_TC_ERAM_DEPTH ((ZXIC_UINT32)(128))
 
-#define ZXDH_VHCA_ERAM_BAADDR               ((ZXIC_UINT32)(0x40000))
-#define ZXDH_VHCA_ERAM_DEPTH                ((ZXIC_UINT32)(0x800))
+#define ZXDH_VHCA_ERAM_BAADDR ((ZXIC_UINT32)(0x40000))
+#define ZXDH_VHCA_ERAM_DEPTH ((ZXIC_UINT32)(0x800))
 
-#define ZXDH_UC_PROMISC_ERAM_BAADDR         ((ZXIC_UINT32)(0x2398E))
-#define ZXDH_UC_PROMISC_ERAM_DEPTH          ((ZXIC_UINT32)(256))
+#define ZXDH_UC_PROMISC_ERAM_BAADDR ((ZXIC_UINT32)(0x2398E))
+#define ZXDH_UC_PROMISC_ERAM_DEPTH ((ZXIC_UINT32)(256))
 
-#define ZXDH_MC_PROMISC_ERAM_BAADDR         ((ZXIC_UINT32)(0x23A8E))
-#define ZXDH_MC_PROMISC_ERAM_DEPTH          ((ZXIC_UINT32)(256))
+#define ZXDH_MC_PROMISC_ERAM_BAADDR ((ZXIC_UINT32)(0x23A8E))
+#define ZXDH_MC_PROMISC_ERAM_DEPTH ((ZXIC_UINT32)(256))
 
-typedef struct zxdh_vxlan_t
-{
-    ZXIC_UINT64 port : 16;
-    ZXIC_UINT64 rsv : 47;
-    ZXIC_UINT64 hit_flag : 1;
+typedef struct zxdh_vxlan_t {
+	ZXIC_UINT64 port : 16;
+	ZXIC_UINT64 rsv : 47;
+	ZXIC_UINT64 hit_flag : 1;
 } ZXDH_VXLAN_T;
 
-typedef struct zxdh_vport_t
-{
-    ZXIC_UINT32 tpid/* : 16; */;
-    ZXIC_UINT32 vhca/* : 10; */;
-    ZXIC_UINT32 uplink_port/* : 6; */;
-
-    ZXIC_UINT32 rss_hash_factor/* : 8; */;
-    ZXIC_UINT32 hash_alg/* : 4; */;
-    ZXIC_UINT32 panel_id/* : 4; */;
-
-    ZXIC_UINT32 lag_id/* : 3; */;
-    ZXIC_UINT32 pf_vqm_vfid/* : 11; */;
-    ZXIC_UINT32 rsv3/* : 2; */;
-
-    ZXIC_UINT32 mtu/* : 16; */;
-
-    ZXIC_UINT32 port_base_qid/* : 12; */;
-    ZXIC_UINT32 hash_search_index/* : 3; */;
-    ZXIC_UINT32 rsv1/* : 1; */;
-    
-    ZXIC_UINT32 tm_enable/* : 1; */;
-    ZXIC_UINT32 ingress_meter_enable/* : 1; */;
-    ZXIC_UINT32 egress_meter_enable/* : 1; */;
-    ZXIC_UINT32 ingress_meter_mode/* : 1; */;
-    ZXIC_UINT32 egress_meter_mode/* : 1; */;
-    ZXIC_UINT32 fd_enable/* : 1; */;
-    ZXIC_UINT32 vepa_enable/* : 1; */;
-    ZXIC_UINT32 spoof_check_enable/* : 1; */;
-
-    ZXIC_UINT32 inline_sec_offload/* : 1; */;
-    ZXIC_UINT32 ovs_enable/* : 1; */;
-    ZXIC_UINT32 lag_enable/* : 1; */;
-    ZXIC_UINT32 is_passthrough/* : 1; */;
-    ZXIC_UINT32 is_vf/* : 1; */;
-    ZXIC_UINT32 virtion_version/* : 2; */;
-    ZXIC_UINT32 virtio_enable/* : 1; */;
-    
-    ZXIC_UINT32 accelerator_offload_flag/* : 1; */;
-    ZXIC_UINT32 lro_offload/* : 1; */;
-    ZXIC_UINT32 ip_fragment_offload/* : 1; */;
-    ZXIC_UINT32 tcp_udp_checksum_offload/* : 1; */;
-    ZXIC_UINT32 ip_checksum_offload/* : 1; */;
-    ZXIC_UINT32 outer_ip_checksum_offload/* : 1; */;
-    ZXIC_UINT32 is_up/* : 1; */;
-    ZXIC_UINT32 allmulticast_enable/* : 1; */;
-
-    ZXIC_UINT32 hw_bond_enable/* : 1; */;
-    ZXIC_UINT32 rdma_offload_enable/* : 1; */;
-    ZXIC_UINT32 vlan_filter_enable/* : 1; */;
-    ZXIC_UINT32 vlan_strip_offload/* : 1; */;
-    ZXIC_UINT32 qinq_vlan_strip_offload/* : 1; */;
-    ZXIC_UINT32 rss_enable/* : 1; */;
-    ZXIC_UINT32 mtu_offload_enable/* : 1; */;
-    ZXIC_UINT32 hit_flag/*: 1; */;
+typedef struct zxdh_vport_t {
+	ZXIC_UINT32 tpid /* : 16; */;
+	ZXIC_UINT32 vhca /* : 10; */;
+	ZXIC_UINT32 uplink_port /* : 6; */;
+
+	ZXIC_UINT32 rss_hash_factor /* : 8; */;
+	ZXIC_UINT32 hash_alg /* : 4; */;
+	ZXIC_UINT32 panel_id /* : 4; */;
+
+	ZXIC_UINT32 lag_id /* : 3; */;
+	ZXIC_UINT32 pf_vqm_vfid /* : 11; */;
+	ZXIC_UINT32 rsv3 /* : 2; */;
+
+	ZXIC_UINT32 mtu /* : 16; */;
+
+	ZXIC_UINT32 port_base_qid /* : 12; */;
+	ZXIC_UINT32 hash_search_index /* : 3; */;
+	ZXIC_UINT32 rsv1 /* : 1; */;
+
+	ZXIC_UINT32 tm_enable /* : 1; */;
+	ZXIC_UINT32 ingress_meter_enable /* : 1; */;
+	ZXIC_UINT32 egress_meter_enable /* : 1; */;
+	ZXIC_UINT32 ingress_meter_mode /* : 1; */;
+	ZXIC_UINT32 egress_meter_mode /* : 1; */;
+	ZXIC_UINT32 fd_enable /* : 1; */;
+	ZXIC_UINT32 vepa_enable /* : 1; */;
+	ZXIC_UINT32 spoof_check_enable /* : 1; */;
+
+	ZXIC_UINT32 inline_sec_offload /* : 1; */;
+	ZXIC_UINT32 ovs_enable /* : 1; */;
+	ZXIC_UINT32 lag_enable /* : 1; */;
+	ZXIC_UINT32 is_passthrough /* : 1; */;
+	ZXIC_UINT32 is_vf /* : 1; */;
+	ZXIC_UINT32 virtion_version /* : 2; */;
+	ZXIC_UINT32 virtio_enable /* : 1; */;
+
+	ZXIC_UINT32 accelerator_offload_flag /* : 1; */;
+	ZXIC_UINT32 lro_offload /* : 1; */;
+	ZXIC_UINT32 ip_fragment_offload /* : 1; */;
+	ZXIC_UINT32 tcp_udp_checksum_offload /* : 1; */;
+	ZXIC_UINT32 ip_checksum_offload /* : 1; */;
+	ZXIC_UINT32 outer_ip_checksum_offload /* : 1; */;
+	ZXIC_UINT32 is_up /* : 1; */;
+	ZXIC_UINT32 allmulticast_enable /* : 1; */;
+
+	ZXIC_UINT32 hw_bond_enable /* : 1; */;
+	ZXIC_UINT32 rdma_offload_enable /* : 1; */;
+	ZXIC_UINT32 vlan_filter_enable /* : 1; */;
+	ZXIC_UINT32 vlan_strip_offload /* : 1; */;
+	ZXIC_UINT32 qinq_vlan_strip_offload /* : 1; */;
+	ZXIC_UINT32 rss_enable /* : 1; */;
+	ZXIC_UINT32 mtu_offload_enable /* : 1; */;
+	ZXIC_UINT32 hit_flag /*: 1; */;
 } ZXDH_VPORT_T;
 
-typedef struct zxdh_panel_port_t
-{
-    ZXIC_UINT32 rsv7                /* : 16; */;
-    ZXIC_UINT32 ovs_pf_vfid         /* : 11; */;
-    ZXIC_UINT32 rsv6                /* : 5; */;
-    ZXIC_UINT32 pf_memport_qid      /* : 12; */;
-    ZXIC_UINT32 rsv5                /* : 4; */;
-    ZXIC_UINT32 bond_pf_vqm_vfid    /* : 11; */;
-    ZXIC_UINT32 rsv4                /* : 2; */;
-    ZXIC_UINT32 is_up               /* : 1; */;
-    ZXIC_UINT32 bond_link_up        /* : 1; */;
-    ZXIC_UINT32 hw_bond_enable      /* : 1; */;
-    ZXIC_UINT32 mtu                 /* : 16; */;
-    ZXIC_UINT32 mtu_offload_enable  /* : 1; */;
-    ZXIC_UINT32 rsv3                /* : 3; */;
-    ZXIC_UINT32 tm_base_queue       /* : 12; */;
-    ZXIC_UINT32 ptp_port_vfid       /* : 11; */;
-    ZXIC_UINT32 rsv2                /* : 5; */;
-    ZXIC_UINT32 pf_vqm_vfid         /* : 11 */;
-    ZXIC_UINT32 tm_shape_enable     /* : 1; */;
-    ZXIC_UINT32 ptp_tc_enable       /* : 2; */;
-    ZXIC_UINT32 trust_mode          /* : 1; */;
-    ZXIC_UINT32 hit_flag            /* : 1; */;
+typedef struct zxdh_panel_port_t {
+	ZXIC_UINT32 rsv7 /* : 16; */;
+	ZXIC_UINT32 ovs_pf_vfid /* : 11; */;
+	ZXIC_UINT32 rsv6 /* : 5; */;
+	ZXIC_UINT32 pf_memport_qid /* : 12; */;
+	ZXIC_UINT32 rsv5 /* : 4; */;
+	ZXIC_UINT32 bond_pf_vqm_vfid /* : 11; */;
+	ZXIC_UINT32 rsv4 /* : 2; */;
+	ZXIC_UINT32 is_up /* : 1; */;
+	ZXIC_UINT32 bond_link_up /* : 1; */;
+	ZXIC_UINT32 hw_bond_enable /* : 1; */;
+	ZXIC_UINT32 mtu /* : 16; */;
+	ZXIC_UINT32 mtu_offload_enable /* : 1; */;
+	ZXIC_UINT32 rsv3 /* : 3; */;
+	ZXIC_UINT32 tm_base_queue /* : 12; */;
+	ZXIC_UINT32 ptp_port_vfid /* : 11; */;
+	ZXIC_UINT32 rsv2 /* : 5; */;
+	ZXIC_UINT32 pf_vqm_vfid /* : 11 */;
+	ZXIC_UINT32 tm_shape_enable /* : 1; */;
+	ZXIC_UINT32 ptp_tc_enable /* : 2; */;
+	ZXIC_UINT32 trust_mode /* : 1; */;
+	ZXIC_UINT32 hit_flag /* : 1; */;
 } ZXDH_PANEL_PORT_T;
 
-typedef struct zxdh_dscp_to_up_t
-{
-    ZXIC_UINT32 rsv2                /* : 32; */;
-    ZXIC_UINT32 up                  /* : 3; */;
-    ZXIC_UINT32 rsv1                /* : 28; */;
-    ZXIC_UINT32 hit_flag            /* : 1;  */;
+typedef struct zxdh_dscp_to_up_t {
+	ZXIC_UINT32 rsv2 /* : 32; */;
+	ZXIC_UINT32 up /* : 3; */;
+	ZXIC_UINT32 rsv1 /* : 28; */;
+	ZXIC_UINT32 hit_flag /* : 1;  */;
 } ZXDH_DSCP_TO_UP_T;
 
-typedef struct zxdh_up_to_tc_t
-{
-    ZXIC_UINT32 rsv2                /* : 32; */;
-    ZXIC_UINT32 tc                  /* : 3; */;
-    ZXIC_UINT32 rsv1                /* : 28; */;
-    ZXIC_UINT32 hit_flag            /* : 1;  */;
+typedef struct zxdh_up_to_tc_t {
+	ZXIC_UINT32 rsv2 /* : 32; */;
+	ZXIC_UINT32 tc /* : 3; */;
+	ZXIC_UINT32 rsv1 /* : 28; */;
+	ZXIC_UINT32 hit_flag /* : 1;  */;
 } ZXDH_UP_TO_TC_T;
 
-typedef struct zxdh_rss_to_vqid_t
-{
-    ZXIC_UINT32 vqm_qid[8];
-    ZXIC_UINT32 hit_flag;
+typedef struct zxdh_rss_to_vqid_t {
+	ZXIC_UINT32 vqm_qid[8];
+	ZXIC_UINT32 hit_flag;
 } ZXDH_RSS_TO_VQID_T;
 
-typedef struct zxdh_vlan_filter_t
-{
-    ZXIC_UINT8 vport_bitmap[15];
-    ZXIC_UINT8 rsv : 7;
-    ZXIC_UINT8 hit_flag : 1;
+typedef struct zxdh_vlan_filter_t {
+	ZXIC_UINT8 vport_bitmap[15];
+	ZXIC_UINT8 rsv : 7;
+	ZXIC_UINT8 hit_flag : 1;
 
 } ZXDH_VLAN_FILTER_T;
 
-typedef struct zxdh_lag_t
-{
-    ZXIC_UINT32 member_bitmap;
-    ZXIC_UINT32 rsv2;
-    ZXIC_UINT32 hash_factor;
-    ZXIC_UINT32 bond_mode;
-    ZXIC_UINT32 member_num;
-    ZXIC_UINT32 rsv1;
-    ZXIC_UINT32 hit_flag;
+typedef struct zxdh_lag_t {
+	ZXIC_UINT32 member_bitmap;
+	ZXIC_UINT32 rsv2;
+	ZXIC_UINT32 hash_factor;
+	ZXIC_UINT32 bond_mode;
+	ZXIC_UINT32 member_num;
+	ZXIC_UINT32 rsv1;
+	ZXIC_UINT32 hit_flag;
 } ZXDH_LAG_T;
 
-typedef struct zxdh_bc_t
-{
-    ZXIC_UINT64 bc_bitmap;
-    ZXIC_UINT32 rsv2;
-    ZXIC_UINT32 rsv1;
-    ZXIC_UINT32 hit_flag;
+typedef struct zxdh_bc_t {
+	ZXIC_UINT64 bc_bitmap;
+	ZXIC_UINT32 rsv2;
+	ZXIC_UINT32 rsv1;
+	ZXIC_UINT32 hit_flag;
 } ZXDH_BC_T;
 
-typedef struct zxdh_promisc_t
-{
-    ZXIC_UINT64 bitmap;
-    ZXIC_UINT32 rsv2;
-    ZXIC_UINT32 rsv1;
-    ZXIC_UINT32 pf_enable;
-    ZXIC_UINT32 hit_flag;
+typedef struct zxdh_promisc_t {
+	ZXIC_UINT64 bitmap;
+	ZXIC_UINT32 rsv2;
+	ZXIC_UINT32 rsv1;
+	ZXIC_UINT32 pf_enable;
+	ZXIC_UINT32 hit_flag;
 } ZXDH_PROMISC_T;
 
-typedef struct zxdh_vhca_t
-{
-    ZXIC_UINT32 rsv2;
-    ZXIC_UINT32 vqm_vfid;
-    ZXIC_UINT32 rsv1;
-    ZXIC_UINT32 valid;
+typedef struct zxdh_vhca_t {
+	ZXIC_UINT32 rsv2;
+	ZXIC_UINT32 vqm_vfid;
+	ZXIC_UINT32 rsv1;
+	ZXIC_UINT32 valid;
 } ZXDH_VHCA_T;
 
 /*************eram call back ****************/
@@ -250,11 +239,9 @@ ZXIC_UINT32 dpp_apt_get_promisc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]);
 ZXIC_UINT32 dpp_apt_set_vhca_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]);
 ZXIC_UINT32 dpp_apt_get_vhca_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4]);
 
-
-typedef struct dpp_eram_init_t
-{
-    ZXIC_UINT32 tbl_num;
-    DPP_APT_ERAM_TABLE_T *eram;
+typedef struct dpp_eram_init_t {
+	ZXIC_UINT32 tbl_num;
+	DPP_APT_ERAM_TABLE_T *eram;
 } DPP_ERAM_INIT_T;
 
 extern DPP_ERAM_INIT_T g_eRamTable;
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_hash.h b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_hash.h
index 8b30f8fcc474e068231f81e34807100992dc8d70..636f84953a85a328dcd052ab4bb2bf1239bb866c 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_hash.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_hash.h
@@ -22,55 +22,50 @@
 #include "zxic_common.h"
 #include "dpp_apt_se_api.h"
 
-#define ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR  (ZXIC_UINT32)(0x0) /* L2转发表保活标志表 */
+#define ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR \
+	((ZXIC_UINT32)(0x0)) /* L2转发表保活标志表 */
 
 /* hash-function for hash tbl */
-#define ZXDH_HASH_FUNC0                     (ZXIC_UINT8)(0)
-#define ZXDH_HASH_FUNC1                     (ZXIC_UINT8)(1)
-#define ZXDH_HASH_FUNC2                     (ZXIC_UINT8)(2)
-#define ZXDH_HASH_FUNC3                     (ZXIC_UINT8)(3)
+#define ZXDH_HASH_FUNC0 ((ZXIC_UINT8)(0))
+#define ZXDH_HASH_FUNC1 ((ZXIC_UINT8)(1))
+#define ZXDH_HASH_FUNC2 ((ZXIC_UINT8)(2))
+#define ZXDH_HASH_FUNC3 ((ZXIC_UINT8)(3))
 
 /* L2 forward */
-typedef struct zxdh_l2_fwd_key
-{
-    ZXIC_UINT8  dmac_addr[6];  /**<  @brief key */
-    ZXIC_UINT16 rsv            /* : 16; */;
+typedef struct zxdh_l2_fwd_key {
+	ZXIC_UINT8 dmac_addr[6]; /**<  @brief key */
+	ZXIC_UINT16 rsv /* : 16; */;
 } ZXDH_L2_FWD_KEY;
 
-typedef struct zxdh_l2_fwd_entry
-{
-    ZXIC_UINT32 vqm_vfid   /* : 11;*/;
-    ZXIC_UINT32 rsv        /* : 20; */;
-    ZXIC_UINT32 hit_flag   /* : 1; */;
-}ZXDH_L2_FWD_ENTRY;
-
-typedef struct zxdh_l2_fwd_t
-{
-    ZXDH_L2_FWD_KEY key;
-    ZXDH_L2_FWD_ENTRY entry;
+typedef struct zxdh_l2_fwd_entry {
+	ZXIC_UINT32 vqm_vfid /* : 11;*/;
+	ZXIC_UINT32 rsv /* : 20; */;
+	ZXIC_UINT32 hit_flag /* : 1; */;
+} ZXDH_L2_FWD_ENTRY;
+
+typedef struct zxdh_l2_fwd_t {
+	ZXDH_L2_FWD_KEY key;
+	ZXDH_L2_FWD_ENTRY entry;
 } ZXDH_L2_ENTRY_T;
 
 /* multicast */
-typedef struct zxdh_mc_key
-{
-    ZXIC_UINT8  mc_mac[6];
-    ZXIC_UINT32 group_id;
-    ZXIC_UINT32 rsv;
-}ZXDH_MC_KEY;
-
-typedef struct zxdh_mc_entry
-{
-    ZXIC_UINT64 mc_bitmap;
-    ZXIC_UINT32 rsv2;
-    ZXIC_UINT32 rsv1;
-    ZXIC_UINT32 mc_pf_enable;
-    ZXIC_UINT32 hit_flag;
-}ZXDH_MC_ENTRY;
-
-typedef struct zxdh_mc_t
-{
-    ZXDH_MC_KEY key;
-    ZXDH_MC_ENTRY entry;
+typedef struct zxdh_mc_key {
+	ZXIC_UINT8 mc_mac[6];
+	ZXIC_UINT32 group_id;
+	ZXIC_UINT32 rsv;
+} ZXDH_MC_KEY;
+
+typedef struct zxdh_mc_entry {
+	ZXIC_UINT64 mc_bitmap;
+	ZXIC_UINT32 rsv2;
+	ZXIC_UINT32 rsv1;
+	ZXIC_UINT32 mc_pf_enable;
+	ZXIC_UINT32 hit_flag;
+} ZXDH_MC_ENTRY;
+
+typedef struct zxdh_mc_t {
+	ZXDH_MC_KEY key;
+	ZXDH_MC_ENTRY entry;
 } ZXDH_MC_T;
 
 ZXIC_UINT32 dpp_apt_set_l2entry_data(ZXIC_VOID *pData, DPP_HASH_ENTRY *pEntry);
@@ -79,19 +74,24 @@ ZXIC_UINT32 dpp_apt_get_l2entry_data(ZXIC_VOID *pData, DPP_HASH_ENTRY *pEntry);
 ZXIC_UINT32 dpp_apt_set_mc_data(ZXIC_VOID *pData, DPP_HASH_ENTRY *pEntry);
 ZXIC_UINT32 dpp_apt_get_mc_data(ZXIC_VOID *pData, DPP_HASH_ENTRY *pEntry);
 
-typedef struct dpp_hash_init_t
-{   
-    ZXIC_UINT32 func_num; 
-    DPP_APT_HASH_FUNC_RES_T *func;
-    ZXIC_UINT32 bulk_num;
-    DPP_APT_HASH_BULK_RES_T *bulk;
-    ZXIC_UINT32 ser_num;
-    DPP_APT_HASH_TABLE_T  *ser;
+typedef struct dpp_hash_init_t {
+	ZXIC_UINT32 func_num;
+	DPP_APT_HASH_FUNC_RES_T *func;
+	ZXIC_UINT32 bulk_num;
+	DPP_APT_HASH_BULK_RES_T *bulk;
+	ZXIC_UINT32 ser_num;
+	DPP_APT_HASH_TABLE_T *ser;
 } DPP_HASH_INIT_T;
 
 extern DPP_HASH_INIT_T g_hashTable;
 
-DPP_STATUS dpp_apt_dtb_hash_table_unicast_mac_dump(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 sdt_no, ZXDH_L2_ENTRY_T *pHashDataArr, ZXIC_UINT32 *p_entry_num);
-DPP_STATUS dpp_apt_dtb_hash_table_multicast_mac_dump(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 sdt_no, ZXDH_MC_T *pHashDataArr, ZXIC_UINT32 *p_entry_num);
+DPP_STATUS dpp_apt_dtb_hash_table_unicast_mac_dump(
+		DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 sdt_no,
+		ZXDH_L2_ENTRY_T *pHashDataArr, ZXIC_UINT32 *p_entry_num);
+DPP_STATUS dpp_apt_dtb_hash_table_multicast_mac_dump(DPP_DEV_T *dev,
+													 ZXIC_UINT32 queue_id,
+													 ZXIC_UINT32 sdt_no,
+													 ZXDH_MC_T *pHashDataArr,
+													 ZXIC_UINT32 *p_entry_num);
 
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_init.h b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_init.h
index 57da29add7929f9216c977df840a573124266173..c814f69cb9f6be1322733f3548b1cfd33851610c 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_init.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_init.h
@@ -30,4 +30,3 @@ DPP_STATUS dpp_flow_uninit(ZXIC_UINT32 dev_id);
 DPP_STATUS dpp_flow_data_all_flush(DPP_DEV_T *dev, ZXIC_UINT32 queue_id);
 
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_sdt.h b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_sdt.h
index 4c8ca496eed8b063bcade22a67986f3847b707d2..11c48312faeea85244ab1178ffb4f1d8e76eac27 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_sdt.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/include/dpp_drv_sdt.h
@@ -23,40 +23,40 @@
 
 /*************SDT配置***************************/
 /* eram直接表 */
-#define ZXDH_SDT_VXLAN_ATTR_TABLE           (ZXIC_UINT32)(0)
-#define ZXDH_SDT_VPORT_ATTR_TABLE           (ZXIC_UINT32)(1)
-#define ZXDH_SDT_PANEL_PORT_ATTR_TABLE      (ZXIC_UINT32)(2)
-#define ZXDH_SDT_RSS_TO_VQID_TABLE          (ZXIC_UINT32)(3)
-#define ZXDH_SDT_VLAN_FILTER_TABLE          (ZXIC_UINT32)(4)
-#define ZXDH_SDT_LAG_TABLE                  (ZXIC_UINT32)(5)
-#define ZXDH_SDT_BC_TABLE                   (ZXIC_UINT32)(6)
-#define ZXDH_SDT_DSCP_TO_UP_TABLE           (ZXIC_UINT32)(7)
-#define ZXDH_SDT_UP_TO_TC_TABLE             (ZXIC_UINT32)(8)
-#define ZXDH_SDT_VHCA_TABLE                 (ZXIC_UINT32)(50)
-#define ZXDH_SDT_UC_PROMISC_TABLE           (ZXIC_UINT32)(10)
-#define ZXDH_SDT_MC_PROMISC_TABLE           (ZXIC_UINT32)(11)
+#define ZXDH_SDT_VXLAN_ATTR_TABLE ((ZXIC_UINT32)(0))
+#define ZXDH_SDT_VPORT_ATTR_TABLE ((ZXIC_UINT32)(1))
+#define ZXDH_SDT_PANEL_PORT_ATTR_TABLE ((ZXIC_UINT32)(2))
+#define ZXDH_SDT_RSS_TO_VQID_TABLE ((ZXIC_UINT32)(3))
+#define ZXDH_SDT_VLAN_FILTER_TABLE ((ZXIC_UINT32)(4))
+#define ZXDH_SDT_LAG_TABLE ((ZXIC_UINT32)(5))
+#define ZXDH_SDT_BC_TABLE ((ZXIC_UINT32)(6))
+#define ZXDH_SDT_DSCP_TO_UP_TABLE ((ZXIC_UINT32)(7))
+#define ZXDH_SDT_UP_TO_TC_TABLE ((ZXIC_UINT32)(8))
+#define ZXDH_SDT_VHCA_TABLE ((ZXIC_UINT32)(50))
+#define ZXDH_SDT_UC_PROMISC_TABLE ((ZXIC_UINT32)(10))
+#define ZXDH_SDT_MC_PROMISC_TABLE ((ZXIC_UINT32)(11))
 
 /* hash表 */
-#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0    (ZXIC_UINT32)(64)
-#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT1    (ZXIC_UINT32)(65)
-#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT2    (ZXIC_UINT32)(66)
-#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT3    (ZXIC_UINT32)(67)
-#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT4    (ZXIC_UINT32)(68)
-#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT5    (ZXIC_UINT32)(69)
-
-#define ZXDH_SDT_MC_TABLE_PHYPORT0          (ZXIC_UINT32)(76)
-#define ZXDH_SDT_MC_TABLE_PHYPORT1          (ZXIC_UINT32)(77)
-#define ZXDH_SDT_MC_TABLE_PHYPORT2          (ZXIC_UINT32)(78)
-#define ZXDH_SDT_MC_TABLE_PHYPORT3          (ZXIC_UINT32)(79)
-#define ZXDH_SDT_MC_TABLE_PHYPORT4          (ZXIC_UINT32)(80)
-#define ZXDH_SDT_MC_TABLE_PHYPORT5          (ZXIC_UINT32)(81)
+#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 ((ZXIC_UINT32)(64))
+#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT1 ((ZXIC_UINT32)(65))
+#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT2 ((ZXIC_UINT32)(66))
+#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT3 ((ZXIC_UINT32)(67))
+#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT4 ((ZXIC_UINT32)(68))
+#define ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT5 ((ZXIC_UINT32)(69))
+
+#define ZXDH_SDT_MC_TABLE_PHYPORT0 ((ZXIC_UINT32)(76))
+#define ZXDH_SDT_MC_TABLE_PHYPORT1 ((ZXIC_UINT32)(77))
+#define ZXDH_SDT_MC_TABLE_PHYPORT2 ((ZXIC_UINT32)(78))
+#define ZXDH_SDT_MC_TABLE_PHYPORT3 ((ZXIC_UINT32)(79))
+#define ZXDH_SDT_MC_TABLE_PHYPORT4 ((ZXIC_UINT32)(80))
+#define ZXDH_SDT_MC_TABLE_PHYPORT5 ((ZXIC_UINT32)(81))
 
 /* etcam表 */
-#define ZXDH_SDT_FD_CFG_TABLE               (ZXIC_UINT32)(130)
-#define ZXDH_SDT_IPSEC_ENC_TABLE            (ZXIC_UINT32)(131)
+#define ZXDH_SDT_FD_CFG_TABLE ((ZXIC_UINT32)(130))
+#define ZXDH_SDT_IPSEC_ENC_TABLE ((ZXIC_UINT32)(131))
 
 /* 抓包使能 */
-#define ZXDH_SDT_CLUTH_DISABLE              (ZXIC_UINT32)(0)
-#define ZXDH_SDT_CLUTH_ENABLE               (ZXIC_UINT32)(1)
+#define ZXDH_SDT_CLUTH_DISABLE ((ZXIC_UINT32)(0))
+#define ZXDH_SDT_CLUTH_ENABLE ((ZXIC_UINT32)(1))
 
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_acl.c b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_acl.c
index a0f1354a89c037eb0b0fddeec2b9f3689c7d3bfa..c40d6b00ed6d5c92c7cb5485edd5b2768f7210b7 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_acl.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_acl.c
@@ -4,159 +4,175 @@
 #include "dpp_drv_sdt.h"
 #include "dpp_drv_acl.h"
 
-static DPP_APT_ACL_TABLE_T g_aclSdtTable[] =
-{
-    {
-        ZXDH_SDT_FD_CFG_TABLE,
-        { // sdt表
-            DPP_SDT_TBLT_eTCAM,           /** <@brief 查找表项类型 DPP_SDT_TABLE_TYPE_E */
-            0,                            /** <@brief etcam通道 */
-            DPP_ACL_KEY_640b,             /** <@brief etcam键值长度 DPP_ACL_KEY_MODE_E */
-            ZXDH_ACL_TBL_ID2,             /** <@brief etcam表项号 */
-            DPP_ETCAM_NO_AS_RSP_MODE_32,  /** <@brief handle模式返回位宽,非级联 0:默认32bit */
-            1,                            /** <@brief 级联eram使能 */
-            ZXDH_FD_AS_ERAM_BAADDR,       /** <@brief 级联eram基地址 */
-            DPP_ACL_AS_MODE_128b,         /** <@brief 级联返回位宽 DPP_ACL_AS_MODE_E */
-            ZXDH_FD_AS_ERAM_DEPTH,        /** <@brief 表项深度，越界检查 */
-            0,                            /** <@brief 抓包使能 */
-        },
-        { // res表
-            DPP_ACL_PRI_SPECIFY,          /** <@brief pri_mode */
-            2048,                         /** <@brief entry_num */
-            4,                            /** <@brief block_num */
-            {2,3,4,5,0,0,0,0},            /** <@brief block_index */
-        },
-        NULL,                             /** <@brief 结构体转换为码流 */
-        NULL,                             /** <@brief 码流转换为结构体 */
-    },  
-    {
-        ZXDH_SDT_IPSEC_ENC_TABLE,
-        { // sdt表
-            DPP_SDT_TBLT_eTCAM,             /** <@brief 查找表项类型 DPP_SDT_TABLE_TYPE_E */
-            0,                              /** <@brief etcam通道 */
-            DPP_ACL_KEY_320b,               /** <@brief etcam键值长度 DPP_ACL_KEY_MODE_E */
-            ZXDH_ACL_TBL_ID3,               /** <@brief etcam表项号 */
-            DPP_ETCAM_NO_AS_RSP_MODE_32,    /** <@brief handle模式返回位宽,非级联 0:默认32bit */
-            1,                              /** <@brief 级联eram使能 */
-            ZXDH_IPSEC_ENC_AS_ERAM_BAADDR,  /** <@brief 级联eram基地址 */
-            DPP_ACL_AS_MODE_64b,            /** <@brief 级联返回位宽 DPP_ACL_AS_MODE_E */
-            ZXDH_IPSEC_ENC_AS_ERAM_DEPTH,   /** <@brief 表项深度，越界检查 */
-            0,                              /** <@brief 抓包使能 */
-        },
-        { // res表
-            DPP_ACL_PRI_SPECIFY,          /** <@brief pri_mode */
-            256,                          /** <@brief entry_num */
-            1,                            /** <@brief block_num */
-            {6,0,0,0,0,0,0,0},            /** <@brief block_index */
-        },
-        dpp_apt_set_ipsec_enc_data,       /** <@brief 结构体转换为码流 */
-        dpp_apt_get_ipsec_enc_data,       /** <@brief 码流转换为结构体 */
-    },  
+static DPP_APT_ACL_TABLE_T g_aclSdtTable[] = {
+	{
+			ZXDH_SDT_FD_CFG_TABLE,
+			{
+					// sdt表
+					DPP_SDT_TBLT_eTCAM, /** <@brief 查找表项类型 DPP_SDT_TABLE_TYPE_E */
+					0, /** <@brief etcam通道 */
+					DPP_ACL_KEY_640b, /** <@brief etcam键值长度 DPP_ACL_KEY_MODE_E */
+					ZXDH_ACL_TBL_ID2, /** <@brief etcam表项号 */
+					DPP_ETCAM_NO_AS_RSP_MODE_32, /** <@brief handle模式返回位宽,非级联 0:默认32bit */
+					1, /** <@brief 级联eram使能 */
+					ZXDH_FD_AS_ERAM_BAADDR, /** <@brief 级联eram基地址 */
+					DPP_ACL_AS_MODE_128b, /** <@brief 级联返回位宽 DPP_ACL_AS_MODE_E */
+					ZXDH_FD_AS_ERAM_DEPTH, /** <@brief 表项深度，越界检查 */
+					0, /** <@brief 抓包使能 */
+			},
+			{
+					// res表
+					DPP_ACL_PRI_SPECIFY, /** <@brief pri_mode */
+					2048, /** <@brief entry_num */
+					4, /** <@brief block_num */
+					{ 2, 3, 4, 5, 0, 0, 0, 0 }, /** <@brief block_index */
+			},
+			NULL, /** <@brief 结构体转换为码流 */
+			NULL, /** <@brief 码流转换为结构体 */
+	},
+	{
+			ZXDH_SDT_IPSEC_ENC_TABLE,
+			{
+					// sdt表
+					DPP_SDT_TBLT_eTCAM, /** <@brief 查找表项类型 DPP_SDT_TABLE_TYPE_E */
+					0, /** <@brief etcam通道 */
+					DPP_ACL_KEY_320b, /** <@brief etcam键值长度 DPP_ACL_KEY_MODE_E */
+					ZXDH_ACL_TBL_ID3, /** <@brief etcam表项号 */
+					DPP_ETCAM_NO_AS_RSP_MODE_32, /** <@brief handle模式返回位宽,非级联 0:默认32bit */
+					1, /** <@brief 级联eram使能 */
+					ZXDH_IPSEC_ENC_AS_ERAM_BAADDR, /** <@brief 级联eram基地址 */
+					DPP_ACL_AS_MODE_64b, /** <@brief 级联返回位宽 DPP_ACL_AS_MODE_E */
+					ZXDH_IPSEC_ENC_AS_ERAM_DEPTH, /** <@brief 表项深度，越界检查 */
+					0, /** <@brief 抓包使能 */
+			},
+			{
+					// res表
+					DPP_ACL_PRI_SPECIFY, /** <@brief pri_mode */
+					256, /** <@brief entry_num */
+					1, /** <@brief block_num */
+					{ 6, 0, 0, 0, 0, 0, 0, 0 }, /** <@brief block_index */
+			},
+			dpp_apt_set_ipsec_enc_data, /** <@brief 结构体转换为码流 */
+			dpp_apt_get_ipsec_enc_data, /** <@brief 码流转换为结构体 */
+	},
 };
 
-ZXIC_UINT32 dpp_apt_set_ipsec_enc_data(ZXIC_VOID *pData, DPP_ACL_ENTRY_EX_T *aclEntry)
+ZXIC_UINT32 dpp_apt_set_ipsec_enc_data(ZXIC_VOID *pData,
+									   DPP_ACL_ENTRY_EX_T *aclEntry)
 {
-    ZXIC_UINT32 key_data = 0;
-    ZXIC_UINT32 key_mask = 0;
-    ZXIC_UINT32 rst = 0;
-
-    ZXDH_IPSEC_ENC_T *ipsec_enc_table = pData;
-
-    ZXIC_COMM_CHECK_POINT(aclEntry);
-    ZXIC_COMM_CHECK_POINT(ipsec_enc_table);
-
-    aclEntry->pri = ipsec_enc_table->index;
-
-    if(aclEntry->key_data)
-    {
-        ZXIC_COMM_UINT32_WRITE_BITS(key_data, ipsec_enc_table->key.rsv1, 0, 32);
-        zxic_comm_swap((ZXIC_UINT8 *)&key_data, sizeof(ZXIC_UINT32));
-        ZXIC_COMM_MEMCPY(aclEntry->key_data, &key_data, sizeof(ZXIC_UINT32));
-
-        ZXIC_COMM_UINT32_WRITE_BITS(key_data, ipsec_enc_table->key.rsv2, 0, 32);
-        zxic_comm_swap((ZXIC_UINT8 *)&key_data, sizeof(ZXIC_UINT32));
-        ZXIC_COMM_MEMCPY(aclEntry->key_data + 4, &key_data, sizeof(ZXIC_UINT32));
-
-        ZXIC_COMM_MEMCPY(aclEntry->key_data + 8, ipsec_enc_table->key.sip, 16);
-        ZXIC_COMM_MEMCPY(aclEntry->key_data + 24, ipsec_enc_table->key.dip, 16);
-    }
-
-    if(aclEntry->key_mask)
-    {
-        ZXIC_COMM_UINT32_WRITE_BITS(key_mask, ipsec_enc_table->mask.rsv1, 0, 32);
-        zxic_comm_swap((ZXIC_UINT8 *)&key_mask, sizeof(ZXIC_UINT32));
-        ZXIC_COMM_MEMCPY(aclEntry->key_mask, &key_mask, sizeof(ZXIC_UINT32));
-
-        ZXIC_COMM_UINT32_WRITE_BITS(key_mask, ipsec_enc_table->mask.rsv2, 0, 32);
-        zxic_comm_swap((ZXIC_UINT8 *)&key_mask, sizeof(ZXIC_UINT32));
-        ZXIC_COMM_MEMCPY(aclEntry->key_mask + 4, &key_mask, sizeof(ZXIC_UINT32));
-
-        ZXIC_COMM_MEMCPY(aclEntry->key_mask + 8, ipsec_enc_table->mask.sip, 16);
-        ZXIC_COMM_MEMCPY(aclEntry->key_mask + 24, ipsec_enc_table->mask.dip, 16);
-    }
-
-    if(aclEntry->p_as_rslt)
-    {
-        ZXIC_COMM_UINT32_WRITE_BITS(rst, ipsec_enc_table->entry.hit_flag, 31, 1);
-        ZXIC_COMM_UINT32_WRITE_BITS(rst, ipsec_enc_table->entry.rsv, 0, 31);
-        zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32));
-        ZXIC_COMM_MEMCPY(aclEntry->p_as_rslt, &rst, sizeof(ZXIC_UINT32));
-
-        ZXIC_COMM_UINT32_WRITE_BITS(rst, ipsec_enc_table->entry.sa_id, 0, 32);
-        zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32));
-        ZXIC_COMM_MEMCPY(aclEntry->p_as_rslt + 4, &rst, sizeof(ZXIC_UINT32));
-    }
-
-    return DPP_OK;
+	ZXIC_UINT32 key_data = 0;
+	ZXIC_UINT32 key_mask = 0;
+	ZXIC_UINT32 rst = 0;
+
+	ZXDH_IPSEC_ENC_T *ipsec_enc_table = pData;
+
+	ZXIC_COMM_CHECK_POINT(aclEntry);
+	ZXIC_COMM_CHECK_POINT(ipsec_enc_table);
+
+	aclEntry->pri = ipsec_enc_table->index;
+
+	if (aclEntry->key_data) {
+		ZXIC_COMM_UINT32_WRITE_BITS(key_data, ipsec_enc_table->key.rsv1, 0, 32);
+		zxic_comm_swap((ZXIC_UINT8 *)&key_data, sizeof(ZXIC_UINT32));
+		ZXIC_COMM_MEMCPY(aclEntry->key_data, &key_data, sizeof(ZXIC_UINT32));
+
+		ZXIC_COMM_UINT32_WRITE_BITS(key_data, ipsec_enc_table->key.rsv2, 0, 32);
+		zxic_comm_swap((ZXIC_UINT8 *)&key_data, sizeof(ZXIC_UINT32));
+		ZXIC_COMM_MEMCPY(aclEntry->key_data + 4, &key_data,
+						 sizeof(ZXIC_UINT32));
+
+		ZXIC_COMM_MEMCPY(aclEntry->key_data + 8, ipsec_enc_table->key.sip, 16);
+		ZXIC_COMM_MEMCPY(aclEntry->key_data + 24, ipsec_enc_table->key.dip, 16);
+	}
+
+	if (aclEntry->key_mask) {
+		ZXIC_COMM_UINT32_WRITE_BITS(key_mask, ipsec_enc_table->mask.rsv1, 0,
+									32);
+		zxic_comm_swap((ZXIC_UINT8 *)&key_mask, sizeof(ZXIC_UINT32));
+		ZXIC_COMM_MEMCPY(aclEntry->key_mask, &key_mask, sizeof(ZXIC_UINT32));
+
+		ZXIC_COMM_UINT32_WRITE_BITS(key_mask, ipsec_enc_table->mask.rsv2, 0,
+									32);
+		zxic_comm_swap((ZXIC_UINT8 *)&key_mask, sizeof(ZXIC_UINT32));
+		ZXIC_COMM_MEMCPY(aclEntry->key_mask + 4, &key_mask,
+						 sizeof(ZXIC_UINT32));
+
+		ZXIC_COMM_MEMCPY(aclEntry->key_mask + 8, ipsec_enc_table->mask.sip, 16);
+		ZXIC_COMM_MEMCPY(aclEntry->key_mask + 24, ipsec_enc_table->mask.dip,
+						 16);
+	}
+
+	if (aclEntry->p_as_rslt) {
+		ZXIC_COMM_UINT32_WRITE_BITS(rst, ipsec_enc_table->entry.hit_flag, 31,
+									1);
+		ZXIC_COMM_UINT32_WRITE_BITS(rst, ipsec_enc_table->entry.rsv, 0, 31);
+		zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32));
+		ZXIC_COMM_MEMCPY(aclEntry->p_as_rslt, &rst, sizeof(ZXIC_UINT32));
+
+		ZXIC_COMM_UINT32_WRITE_BITS(rst, ipsec_enc_table->entry.sa_id, 0, 32);
+		zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32));
+		ZXIC_COMM_MEMCPY(aclEntry->p_as_rslt + 4, &rst, sizeof(ZXIC_UINT32));
+	}
+
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_apt_get_ipsec_enc_data(ZXIC_VOID *pData, DPP_ACL_ENTRY_EX_T *aclEntry)
-{  
-    ZXDH_IPSEC_ENC_T *ipsec_enc_table = pData;
-
-    ZXIC_COMM_CHECK_POINT(aclEntry);
-    ZXIC_COMM_CHECK_POINT(ipsec_enc_table);
-
-    ipsec_enc_table->index = aclEntry->pri;
-
-    if(aclEntry->key_data)
-    {
-        zxic_comm_swap(aclEntry->key_data, sizeof(ZXIC_UINT32));
-        ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->key.rsv1, *(ZXIC_UINT32 *)(aclEntry->key_data), 0, 32);
-
-        zxic_comm_swap(aclEntry->key_data + 4, sizeof(ZXIC_UINT32));
-        ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->key.rsv2, *(ZXIC_UINT32 *)(aclEntry->key_data + 4), 0, 32);
-
-        ZXIC_COMM_MEMCPY(ipsec_enc_table->key.sip, aclEntry->key_data + 8, 16);
-        ZXIC_COMM_MEMCPY(ipsec_enc_table->key.dip, aclEntry->key_data + 24, 16);
-    }
-
-    if(aclEntry->key_mask)
-    {
-        zxic_comm_swap(aclEntry->key_mask, sizeof(ZXIC_UINT32));
-        ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->mask.rsv1, *(ZXIC_UINT32 *)(aclEntry->key_mask), 0, 32);
-
-        zxic_comm_swap(aclEntry->key_mask + 4, sizeof(ZXIC_UINT32));
-        ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->mask.rsv2, *(ZXIC_UINT32 *)(aclEntry->key_mask + 4), 0, 32);
-
-        ZXIC_COMM_MEMCPY(ipsec_enc_table->mask.sip, aclEntry->key_mask + 8, 16);
-        ZXIC_COMM_MEMCPY(ipsec_enc_table->mask.dip, aclEntry->key_mask + 24, 16);
-    }
-
-    if(aclEntry->p_as_rslt)
-    {
-        zxic_comm_swap(aclEntry->p_as_rslt, sizeof(ZXIC_UINT32));
-        ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->entry.hit_flag, *(ZXIC_UINT32 *)(aclEntry->p_as_rslt), 31, 1);
-        ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->entry.rsv, *(ZXIC_UINT32 *)(aclEntry->p_as_rslt), 0, 31);
-
-        zxic_comm_swap(aclEntry->p_as_rslt + 4, sizeof(ZXIC_UINT32));
-        ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->entry.sa_id, *(ZXIC_UINT32 *)(aclEntry->p_as_rslt + 4), 0, 32);
-    }
-
-    return DPP_OK;
+ZXIC_UINT32 dpp_apt_get_ipsec_enc_data(ZXIC_VOID *pData,
+									   DPP_ACL_ENTRY_EX_T *aclEntry)
+{
+	ZXDH_IPSEC_ENC_T *ipsec_enc_table = pData;
+
+	ZXIC_COMM_CHECK_POINT(aclEntry);
+	ZXIC_COMM_CHECK_POINT(ipsec_enc_table);
+
+	ipsec_enc_table->index = aclEntry->pri;
+
+	if (aclEntry->key_data) {
+		zxic_comm_swap(aclEntry->key_data, sizeof(ZXIC_UINT32));
+		ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->key.rsv1,
+								  *(ZXIC_UINT32 *)(aclEntry->key_data), 0, 32);
+
+		zxic_comm_swap(aclEntry->key_data + 4, sizeof(ZXIC_UINT32));
+		ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->key.rsv2,
+								  *(ZXIC_UINT32 *)(aclEntry->key_data + 4), 0,
+								  32);
+
+		ZXIC_COMM_MEMCPY(ipsec_enc_table->key.sip, aclEntry->key_data + 8, 16);
+		ZXIC_COMM_MEMCPY(ipsec_enc_table->key.dip, aclEntry->key_data + 24, 16);
+	}
+
+	if (aclEntry->key_mask) {
+		zxic_comm_swap(aclEntry->key_mask, sizeof(ZXIC_UINT32));
+		ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->mask.rsv1,
+								  *(ZXIC_UINT32 *)(aclEntry->key_mask), 0, 32);
+
+		zxic_comm_swap(aclEntry->key_mask + 4, sizeof(ZXIC_UINT32));
+		ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->mask.rsv2,
+								  *(ZXIC_UINT32 *)(aclEntry->key_mask + 4), 0,
+								  32);
+
+		ZXIC_COMM_MEMCPY(ipsec_enc_table->mask.sip, aclEntry->key_mask + 8, 16);
+		ZXIC_COMM_MEMCPY(ipsec_enc_table->mask.dip, aclEntry->key_mask + 24,
+						 16);
+	}
+
+	if (aclEntry->p_as_rslt) {
+		zxic_comm_swap(aclEntry->p_as_rslt, sizeof(ZXIC_UINT32));
+		ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->entry.hit_flag,
+								  *(ZXIC_UINT32 *)(aclEntry->p_as_rslt), 31, 1);
+		ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->entry.rsv,
+								  *(ZXIC_UINT32 *)(aclEntry->p_as_rslt), 0, 31);
+
+		zxic_comm_swap(aclEntry->p_as_rslt + 4, sizeof(ZXIC_UINT32));
+		ZXIC_COMM_UINT32_GET_BITS(ipsec_enc_table->entry.sa_id,
+								  *(ZXIC_UINT32 *)(aclEntry->p_as_rslt + 4), 0,
+								  32);
+	}
+
+	return DPP_OK;
 }
 
 DPP_ACL_INIT_T g_aclTable = {
-    .tbl_num = sizeof(g_aclSdtTable) / sizeof(DPP_APT_ACL_TABLE_T),
-    .acl = g_aclSdtTable,
+	.tbl_num = sizeof(g_aclSdtTable) / sizeof(DPP_APT_ACL_TABLE_T),
+	.acl = g_aclSdtTable,
 };
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_eram.c b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_eram.c
index 22eeb50e5673551cad77af5f65d22cad1fe6e5c5..14fc95186fc89587567556103151bf8cfc570873 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_eram.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_eram.c
@@ -3,673 +3,629 @@
 #include "dpp_drv_sdt.h"
 #include "dpp_drv_eram.h"
 
-static DPP_APT_ERAM_TABLE_T g_eRamSdtTable[] =
-{
-    {
-        ZXDH_SDT_VXLAN_ATTR_TABLE,
-        {
-            DPP_SDT_TBLT_eRAM,                  /** <@brief 查找表项类型 */
-            ERAM128_TBL_64b,                    /** <@brief eRam返回位宽 */
-            ZXDH_VXLAN_ERAM_BAADDR,             /** <@brief eRam表项基地址，128bit为单位 */
-            ZXDH_VXLAN_ERAM_DEPTH,              /** <@brief 表项深度，作为越界检查使用 */
-            ZXDH_SDT_CLUTH_DISABLE              /** <@brief 抓包使能 */
-        },
-        ERAM128_OPR_64b,                        /**  操作位宽 */
-        RD_MODE_HOLD,                           /**  所有表项都为：RD_MODE_HOLD */
-        dpp_apt_set_vxlan_data,
-        dpp_apt_get_vxlan_data
-    },
-    {
-        ZXDH_SDT_VPORT_ATTR_TABLE,
-        {
-            DPP_SDT_TBLT_eRAM,
-            ERAM128_TBL_128b,
-            ZXDH_VPORT_ATTR_ERAM_BAADDR,
-            ZXDH_VPORT_ATTR_ERAM_DEPTH,
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        ERAM128_OPR_128b,
-        RD_MODE_HOLD,
-        dpp_apt_set_vport_data,
-        dpp_apt_get_vport_data
-    },
-    {
-        ZXDH_SDT_PANEL_PORT_ATTR_TABLE,
-        {
-            DPP_SDT_TBLT_eRAM,
-            ERAM128_TBL_128b,
-            ZXDH_PANEL_PORT_ATTR_ERAM_BAADDR,
-            ZXDH_PANEL_PORT_ATTR_ERAM_DEPTH,
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        ERAM128_OPR_128b,
-        RD_MODE_HOLD,
-        dpp_apt_set_panel_port_data,
-        dpp_apt_get_panel_port_data
-    },
-    {
-        ZXDH_SDT_RSS_TO_VQID_TABLE,
-        {
-            DPP_SDT_TBLT_eRAM,
-            ERAM128_TBL_128b,
-            ZXDH_RSS_TO_VQID_ERAM_BAADDR,
-            ZXDH_RSS_TO_VQID_ERAM_DEPTH,
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        ERAM128_OPR_128b,
-        RD_MODE_HOLD,
-        dpp_apt_set_rss_to_vqid_data,
-        dpp_apt_get_rss_to_vqid_data
-    },
-    {
-        ZXDH_SDT_VLAN_FILTER_TABLE,
-        {
-            DPP_SDT_TBLT_eRAM,
-            ERAM128_TBL_128b,
-            ZXDH_VLAN_FILTER_ERAM_BAADDR,
-            ZXDH_VLAN_FILTER_ERAM_DEPTH,
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        ERAM128_OPR_128b,
-        RD_MODE_HOLD,
-        dpp_apt_set_vlan_filter_data,
-        dpp_apt_get_vlan_filter_data
-    },
-    {
-        ZXDH_SDT_LAG_TABLE,
-        {
-            DPP_SDT_TBLT_eRAM,
-            ERAM128_TBL_64b,
-            ZXDH_LAG_ERAM_BAADDR,
-            ZXDH_LAG_ERAM_DEPTH,
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        ERAM128_OPR_64b,
-        RD_MODE_HOLD,
-        dpp_apt_set_lag_data,
-        dpp_apt_get_lag_data
-    },
-    {
-        ZXDH_SDT_BC_TABLE,
-        {
-            DPP_SDT_TBLT_eRAM,
-            ERAM128_TBL_128b,
-            ZXDH_BC_ERAM_BAADDR,
-            ZXDH_BC_ERAM_DEPTH,
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        ERAM128_OPR_128b,
-        RD_MODE_HOLD,
-        dpp_apt_set_bc_data,
-        dpp_apt_get_bc_data
-    },
-    {
-        ZXDH_SDT_DSCP_TO_UP_TABLE,
-        {
-            DPP_SDT_TBLT_eRAM,
-            ERAM128_TBL_64b,
-            ZXDH_DSCP_TO_UP_ERAM_BAADDR,
-            ZXDH_DSCP_TO_UP_ERAM_DEPTH,
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        ERAM128_OPR_64b,
-        RD_MODE_HOLD,
-        dpp_apt_set_dscp_to_up_data,
-        dpp_apt_get_dscp_to_up_data
-    },
-    {
-        ZXDH_SDT_UP_TO_TC_TABLE,
-        {
-            DPP_SDT_TBLT_eRAM,
-            ERAM128_TBL_64b,
-            ZXDH_UP_TO_TC_ERAM_BAADDR,
-            ZXDH_UP_TO_TC_ERAM_DEPTH,
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        ERAM128_OPR_64b,
-        RD_MODE_HOLD,
-        dpp_apt_set_up_to_tc_data,
-        dpp_apt_get_up_to_tc_data
-    },
-    {
-        ZXDH_SDT_VHCA_TABLE,
-        {
-            DPP_SDT_TBLT_eRAM,
-            ERAM128_TBL_64b,
-            ZXDH_VHCA_ERAM_BAADDR,
-            ZXDH_VHCA_ERAM_DEPTH,
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        ERAM128_OPR_64b,
-        RD_MODE_HOLD,
-        dpp_apt_set_vhca_data,
-        dpp_apt_get_vhca_data
-    },
-    {
-        ZXDH_SDT_UC_PROMISC_TABLE,
-        {
-            DPP_SDT_TBLT_eRAM,
-            ERAM128_TBL_128b,
-            ZXDH_UC_PROMISC_ERAM_BAADDR,
-            ZXDH_UC_PROMISC_ERAM_DEPTH,
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        ERAM128_OPR_128b,
-        RD_MODE_HOLD,
-        dpp_apt_set_promisc_data,
-        dpp_apt_get_promisc_data
-    },
-    {
-        ZXDH_SDT_MC_PROMISC_TABLE,
-        {
-            DPP_SDT_TBLT_eRAM,
-            ERAM128_TBL_128b,
-            ZXDH_MC_PROMISC_ERAM_BAADDR,
-            ZXDH_MC_PROMISC_ERAM_DEPTH,
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        ERAM128_OPR_128b,
-        RD_MODE_HOLD,
-        dpp_apt_set_promisc_data,
-        dpp_apt_get_promisc_data
-    },
+static DPP_APT_ERAM_TABLE_T g_eRamSdtTable[] = {
+	{ ZXDH_SDT_VXLAN_ATTR_TABLE,
+	  {
+			  DPP_SDT_TBLT_eRAM, /** <@brief 查找表项类型 */
+			  ERAM128_TBL_64b, /** <@brief eRam返回位宽 */
+			  ZXDH_VXLAN_ERAM_BAADDR, /** <@brief eRam表项基地址，128bit为单位 */
+			  ZXDH_VXLAN_ERAM_DEPTH, /** <@brief 表项深度，作为越界检查使用 */
+			  ZXDH_SDT_CLUTH_DISABLE /** <@brief 抓包使能 */
+	  },
+	  ERAM128_OPR_64b, /**  操作位宽 */
+	  RD_MODE_HOLD, /**  所有表项都为：RD_MODE_HOLD */
+	  dpp_apt_set_vxlan_data,
+	  dpp_apt_get_vxlan_data },
+	{ ZXDH_SDT_VPORT_ATTR_TABLE,
+	  { DPP_SDT_TBLT_eRAM, ERAM128_TBL_128b, ZXDH_VPORT_ATTR_ERAM_BAADDR,
+		ZXDH_VPORT_ATTR_ERAM_DEPTH, ZXDH_SDT_CLUTH_DISABLE },
+	  ERAM128_OPR_128b,
+	  RD_MODE_HOLD,
+	  dpp_apt_set_vport_data,
+	  dpp_apt_get_vport_data },
+	{ ZXDH_SDT_PANEL_PORT_ATTR_TABLE,
+	  { DPP_SDT_TBLT_eRAM, ERAM128_TBL_128b, ZXDH_PANEL_PORT_ATTR_ERAM_BAADDR,
+		ZXDH_PANEL_PORT_ATTR_ERAM_DEPTH, ZXDH_SDT_CLUTH_DISABLE },
+	  ERAM128_OPR_128b,
+	  RD_MODE_HOLD,
+	  dpp_apt_set_panel_port_data,
+	  dpp_apt_get_panel_port_data },
+	{ ZXDH_SDT_RSS_TO_VQID_TABLE,
+	  { DPP_SDT_TBLT_eRAM, ERAM128_TBL_128b, ZXDH_RSS_TO_VQID_ERAM_BAADDR,
+		ZXDH_RSS_TO_VQID_ERAM_DEPTH, ZXDH_SDT_CLUTH_DISABLE },
+	  ERAM128_OPR_128b,
+	  RD_MODE_HOLD,
+	  dpp_apt_set_rss_to_vqid_data,
+	  dpp_apt_get_rss_to_vqid_data },
+	{ ZXDH_SDT_VLAN_FILTER_TABLE,
+	  { DPP_SDT_TBLT_eRAM, ERAM128_TBL_128b, ZXDH_VLAN_FILTER_ERAM_BAADDR,
+		ZXDH_VLAN_FILTER_ERAM_DEPTH, ZXDH_SDT_CLUTH_DISABLE },
+	  ERAM128_OPR_128b,
+	  RD_MODE_HOLD,
+	  dpp_apt_set_vlan_filter_data,
+	  dpp_apt_get_vlan_filter_data },
+	{ ZXDH_SDT_LAG_TABLE,
+	  { DPP_SDT_TBLT_eRAM, ERAM128_TBL_64b, ZXDH_LAG_ERAM_BAADDR,
+		ZXDH_LAG_ERAM_DEPTH, ZXDH_SDT_CLUTH_DISABLE },
+	  ERAM128_OPR_64b,
+	  RD_MODE_HOLD,
+	  dpp_apt_set_lag_data,
+	  dpp_apt_get_lag_data },
+	{ ZXDH_SDT_BC_TABLE,
+	  { DPP_SDT_TBLT_eRAM, ERAM128_TBL_128b, ZXDH_BC_ERAM_BAADDR,
+		ZXDH_BC_ERAM_DEPTH, ZXDH_SDT_CLUTH_DISABLE },
+	  ERAM128_OPR_128b,
+	  RD_MODE_HOLD,
+	  dpp_apt_set_bc_data,
+	  dpp_apt_get_bc_data },
+	{ ZXDH_SDT_DSCP_TO_UP_TABLE,
+	  { DPP_SDT_TBLT_eRAM, ERAM128_TBL_64b, ZXDH_DSCP_TO_UP_ERAM_BAADDR,
+		ZXDH_DSCP_TO_UP_ERAM_DEPTH, ZXDH_SDT_CLUTH_DISABLE },
+	  ERAM128_OPR_64b,
+	  RD_MODE_HOLD,
+	  dpp_apt_set_dscp_to_up_data,
+	  dpp_apt_get_dscp_to_up_data },
+	{ ZXDH_SDT_UP_TO_TC_TABLE,
+	  { DPP_SDT_TBLT_eRAM, ERAM128_TBL_64b, ZXDH_UP_TO_TC_ERAM_BAADDR,
+		ZXDH_UP_TO_TC_ERAM_DEPTH, ZXDH_SDT_CLUTH_DISABLE },
+	  ERAM128_OPR_64b,
+	  RD_MODE_HOLD,
+	  dpp_apt_set_up_to_tc_data,
+	  dpp_apt_get_up_to_tc_data },
+	{ ZXDH_SDT_VHCA_TABLE,
+	  { DPP_SDT_TBLT_eRAM, ERAM128_TBL_64b, ZXDH_VHCA_ERAM_BAADDR,
+		ZXDH_VHCA_ERAM_DEPTH, ZXDH_SDT_CLUTH_DISABLE },
+	  ERAM128_OPR_64b,
+	  RD_MODE_HOLD,
+	  dpp_apt_set_vhca_data,
+	  dpp_apt_get_vhca_data },
+	{ ZXDH_SDT_UC_PROMISC_TABLE,
+	  { DPP_SDT_TBLT_eRAM, ERAM128_TBL_128b, ZXDH_UC_PROMISC_ERAM_BAADDR,
+		ZXDH_UC_PROMISC_ERAM_DEPTH, ZXDH_SDT_CLUTH_DISABLE },
+	  ERAM128_OPR_128b,
+	  RD_MODE_HOLD,
+	  dpp_apt_set_promisc_data,
+	  dpp_apt_get_promisc_data },
+	{ ZXDH_SDT_MC_PROMISC_TABLE,
+	  { DPP_SDT_TBLT_eRAM, ERAM128_TBL_128b, ZXDH_MC_PROMISC_ERAM_BAADDR,
+		ZXDH_MC_PROMISC_ERAM_DEPTH, ZXDH_SDT_CLUTH_DISABLE },
+	  ERAM128_OPR_128b,
+	  RD_MODE_HOLD,
+	  dpp_apt_set_promisc_data,
+	  dpp_apt_get_promisc_data },
 };
 
 DPP_ERAM_INIT_T g_eRamTable = {
-    .tbl_num = sizeof(g_eRamSdtTable) / sizeof(DPP_APT_ERAM_TABLE_T),
-    .eram = g_eRamSdtTable,
+	.tbl_num = sizeof(g_eRamSdtTable) / sizeof(DPP_APT_ERAM_TABLE_T),
+	.eram = g_eRamSdtTable,
 };
 
-ZXIC_UINT32 dpp_apt_set_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4], ZXIC_UINT32 size)
+ZXIC_UINT32 dpp_apt_set_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4],
+							 ZXIC_UINT32 size)
 {
-    if (pData == NULL)
-    {
-        return DPP_ERR;
-    }
-    memcpy(buff, pData, size);
-    return DPP_OK;
+	if (pData == NULL) {
+		return DPP_ERR;
+	}
+	memcpy(buff, pData, size);
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_apt_get_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4],ZXIC_UINT32 size)
+ZXIC_UINT32 dpp_apt_get_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4],
+							 ZXIC_UINT32 size)
 {
-    if (pData == NULL)
-    {
-        return DPP_ERR;
-    }
-    memcpy(pData, buff, size);    
-    return DPP_OK;
+	if (pData == NULL) {
+		return DPP_ERR;
+	}
+	memcpy(pData, buff, size);
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_set_vxlan_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    return dpp_apt_set_data(pData, buff, sizeof(ZXDH_VXLAN_T));
+	return dpp_apt_set_data(pData, buff, sizeof(ZXDH_VXLAN_T));
 }
 
 ZXIC_UINT32 dpp_apt_get_vxlan_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    return dpp_apt_get_data(pData, buff, sizeof(ZXDH_VXLAN_T)); 
+	return dpp_apt_get_data(pData, buff, sizeof(ZXDH_VXLAN_T));
 }
 
 ZXIC_UINT32 dpp_apt_set_vport_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXDH_VPORT_T *port_attr = (ZXDH_VPORT_T *)pData;
-
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->hit_flag, 31, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->mtu_offload_enable, 30, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->rss_enable, 29, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->qinq_vlan_strip_offload, 28, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->vlan_strip_offload, 27, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->vlan_filter_enable, 26, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->rdma_offload_enable, 25, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->hw_bond_enable, 24, 1);
-
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->allmulticast_enable, 23, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->is_up, 22, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->outer_ip_checksum_offload, 21, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->ip_checksum_offload, 20, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->tcp_udp_checksum_offload, 19, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->ip_fragment_offload, 18, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->lro_offload, 17, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->accelerator_offload_flag, 16, 1);
-
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->virtio_enable, 15, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->virtion_version, 13, 2);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->is_vf, 12, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->is_passthrough, 11, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->lag_enable, 10, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->ovs_enable, 9, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->inline_sec_offload, 8, 1);
-
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->spoof_check_enable, 7, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->vepa_enable, 6, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->fd_enable, 5, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->egress_meter_mode, 4, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->ingress_meter_mode, 3, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->egress_meter_enable, 2, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->ingress_meter_enable, 1, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->tm_enable, 0, 1);
-
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], port_attr->rsv1, 31, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], port_attr->hash_search_index, 28, 3);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], port_attr->port_base_qid, 16, 12);
-
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], port_attr->mtu, 0, 16);
-
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->rsv3, 30, 2);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->pf_vqm_vfid, 19, 11);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->lag_id, 16, 3);
-
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->panel_id, 12, 4);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->hash_alg, 8, 4);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->rss_hash_factor, 0, 8);
-
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[3], port_attr->uplink_port, 26, 6);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[3], port_attr->vhca, 16, 10);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[3], port_attr->tpid, 0, 16);
-
-
-    return DPP_OK;
+	ZXDH_VPORT_T *port_attr = (ZXDH_VPORT_T *)pData;
+
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->hit_flag, 31, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->mtu_offload_enable, 30, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->rss_enable, 29, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->qinq_vlan_strip_offload, 28,
+								1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->vlan_strip_offload, 27, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->vlan_filter_enable, 26, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->rdma_offload_enable, 25, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->hw_bond_enable, 24, 1);
+
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->allmulticast_enable, 23, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->is_up, 22, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->outer_ip_checksum_offload,
+								21, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->ip_checksum_offload, 20, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->tcp_udp_checksum_offload,
+								19, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->ip_fragment_offload, 18, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->lro_offload, 17, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->accelerator_offload_flag,
+								16, 1);
+
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->virtio_enable, 15, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->virtion_version, 13, 2);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->is_vf, 12, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->is_passthrough, 11, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->lag_enable, 10, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->ovs_enable, 9, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->inline_sec_offload, 8, 1);
+
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->spoof_check_enable, 7, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->vepa_enable, 6, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->fd_enable, 5, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->egress_meter_mode, 4, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->ingress_meter_mode, 3, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->egress_meter_enable, 2, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->ingress_meter_enable, 1, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], port_attr->tm_enable, 0, 1);
+
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], port_attr->rsv1, 31, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], port_attr->hash_search_index, 28, 3);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], port_attr->port_base_qid, 16, 12);
+
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], port_attr->mtu, 0, 16);
+
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->rsv3, 30, 2);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->pf_vqm_vfid, 19, 11);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->lag_id, 16, 3);
+
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->panel_id, 12, 4);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->hash_alg, 8, 4);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], port_attr->rss_hash_factor, 0, 8);
+
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[3], port_attr->uplink_port, 26, 6);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[3], port_attr->vhca, 16, 10);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[3], port_attr->tpid, 0, 16);
+
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_get_vport_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXDH_VPORT_T *port_attr = (ZXDH_VPORT_T *)pData;
-
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->hit_flag, buff[0], 31, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->mtu_offload_enable, buff[0], 30, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->rss_enable, buff[0], 29, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->qinq_vlan_strip_offload, buff[0], 28, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->vlan_strip_offload, buff[0], 27, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->vlan_filter_enable, buff[0], 26, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->rdma_offload_enable, buff[0], 25, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->hw_bond_enable, buff[0], 24, 1);
-
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->allmulticast_enable, buff[0], 23, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->is_up, buff[0], 22, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->outer_ip_checksum_offload, buff[0], 21, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->ip_checksum_offload, buff[0], 20, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->tcp_udp_checksum_offload, buff[0], 19, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->ip_fragment_offload, buff[0], 18, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->lro_offload, buff[0], 17, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->accelerator_offload_flag, buff[0], 16, 1);
-
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->virtio_enable, buff[0], 15, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->virtion_version, buff[0], 13, 2);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->is_vf, buff[0], 12, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->is_passthrough, buff[0], 11, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->lag_enable, buff[0], 10, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->ovs_enable, buff[0], 9, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->inline_sec_offload, buff[0], 8, 1);
-
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->spoof_check_enable, buff[0], 7, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->vepa_enable, buff[0], 6, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->fd_enable, buff[0], 5, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->egress_meter_mode, buff[0], 4, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->ingress_meter_mode, buff[0], 3, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->egress_meter_enable, buff[0], 2, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->ingress_meter_enable, buff[0], 1, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->tm_enable, buff[0], 0, 1);
-
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->rsv1, buff[1], 31, 1);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->hash_search_index, buff[1], 28, 3);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->port_base_qid, buff[1], 16, 12);
-
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->mtu, buff[1], 0, 16);
-
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->rsv3, buff[2], 30, 2);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->pf_vqm_vfid, buff[2], 19, 11);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->lag_id, buff[2], 16, 3);
-
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->panel_id, buff[2], 12, 4);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->hash_alg, buff[2], 8, 4);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->rss_hash_factor, buff[2], 0, 8);
-
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->uplink_port, buff[3], 26, 6);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->vhca, buff[3], 16, 10);
-    ZXIC_COMM_UINT32_GET_BITS(port_attr->tpid, buff[3], 0, 16);
-
-    return DPP_OK;
-
+	ZXDH_VPORT_T *port_attr = (ZXDH_VPORT_T *)pData;
+
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->hit_flag, buff[0], 31, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->mtu_offload_enable, buff[0], 30, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->rss_enable, buff[0], 29, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->qinq_vlan_strip_offload, buff[0], 28,
+							  1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->vlan_strip_offload, buff[0], 27, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->vlan_filter_enable, buff[0], 26, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->rdma_offload_enable, buff[0], 25, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->hw_bond_enable, buff[0], 24, 1);
+
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->allmulticast_enable, buff[0], 23, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->is_up, buff[0], 22, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->outer_ip_checksum_offload, buff[0], 21,
+							  1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->ip_checksum_offload, buff[0], 20, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->tcp_udp_checksum_offload, buff[0], 19,
+							  1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->ip_fragment_offload, buff[0], 18, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->lro_offload, buff[0], 17, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->accelerator_offload_flag, buff[0], 16,
+							  1);
+
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->virtio_enable, buff[0], 15, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->virtion_version, buff[0], 13, 2);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->is_vf, buff[0], 12, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->is_passthrough, buff[0], 11, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->lag_enable, buff[0], 10, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->ovs_enable, buff[0], 9, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->inline_sec_offload, buff[0], 8, 1);
+
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->spoof_check_enable, buff[0], 7, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->vepa_enable, buff[0], 6, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->fd_enable, buff[0], 5, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->egress_meter_mode, buff[0], 4, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->ingress_meter_mode, buff[0], 3, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->egress_meter_enable, buff[0], 2, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->ingress_meter_enable, buff[0], 1, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->tm_enable, buff[0], 0, 1);
+
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->rsv1, buff[1], 31, 1);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->hash_search_index, buff[1], 28, 3);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->port_base_qid, buff[1], 16, 12);
+
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->mtu, buff[1], 0, 16);
+
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->rsv3, buff[2], 30, 2);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->pf_vqm_vfid, buff[2], 19, 11);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->lag_id, buff[2], 16, 3);
+
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->panel_id, buff[2], 12, 4);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->hash_alg, buff[2], 8, 4);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->rss_hash_factor, buff[2], 0, 8);
+
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->uplink_port, buff[3], 26, 6);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->vhca, buff[3], 16, 10);
+	ZXIC_COMM_UINT32_GET_BITS(port_attr->tpid, buff[3], 0, 16);
+
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_set_panel_port_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXDH_PANEL_PORT_T* attr = (ZXDH_PANEL_PORT_T*)pData;
-
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->hit_flag, 31, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->trust_mode, 30, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->ptp_tc_enable, 28, 2);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->tm_shape_enable, 27, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->pf_vqm_vfid, 16, 11);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->rsv2, 11, 5);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->ptp_port_vfid, 0, 11);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->tm_base_queue, 20, 12);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->rsv3, 17, 3);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->mtu_offload_enable, 16, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->mtu, 0, 16);
-
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->hw_bond_enable, 31, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->bond_link_up, 30, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->is_up, 29, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->rsv4, 27, 2);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->bond_pf_vqm_vfid, 16, 11);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->rsv5, 12, 4);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->pf_memport_qid, 0, 12);
-
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[3], attr->rsv6, 27, 5);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[3], attr->ovs_pf_vfid, 16, 11);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[3], attr->rsv7, 0, 16);
-
-    return DPP_OK;
+	ZXDH_PANEL_PORT_T *attr = (ZXDH_PANEL_PORT_T *)pData;
+
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->hit_flag, 31, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->trust_mode, 30, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->ptp_tc_enable, 28, 2);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->tm_shape_enable, 27, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->pf_vqm_vfid, 16, 11);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->rsv2, 11, 5);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->ptp_port_vfid, 0, 11);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->tm_base_queue, 20, 12);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->rsv3, 17, 3);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->mtu_offload_enable, 16, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->mtu, 0, 16);
+
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->hw_bond_enable, 31, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->bond_link_up, 30, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->is_up, 29, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->rsv4, 27, 2);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->bond_pf_vqm_vfid, 16, 11);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->rsv5, 12, 4);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->pf_memport_qid, 0, 12);
+
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[3], attr->rsv6, 27, 5);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[3], attr->ovs_pf_vfid, 16, 11);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[3], attr->rsv7, 0, 16);
+
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_get_panel_port_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXDH_PANEL_PORT_T* attr = (ZXDH_PANEL_PORT_T*)pData;
-
-    ZXIC_COMM_UINT32_GET_BITS(attr->hit_flag, buff[0], 31, 1);
-    ZXIC_COMM_UINT32_GET_BITS(attr->trust_mode, buff[0], 30, 1);
-    ZXIC_COMM_UINT32_GET_BITS(attr->ptp_tc_enable, buff[0], 28, 2);
-    ZXIC_COMM_UINT32_GET_BITS(attr->tm_shape_enable, buff[0], 27, 1);
-    ZXIC_COMM_UINT32_GET_BITS(attr->pf_vqm_vfid, buff[0], 16, 11);
-    ZXIC_COMM_UINT32_GET_BITS(attr->rsv2, buff[0], 11, 5);
-    ZXIC_COMM_UINT32_GET_BITS(attr->ptp_port_vfid, buff[0], 0, 11);
-    ZXIC_COMM_UINT32_GET_BITS(attr->tm_base_queue, buff[1], 20, 12);
-    ZXIC_COMM_UINT32_GET_BITS(attr->rsv3, buff[1], 17, 3);
-    ZXIC_COMM_UINT32_GET_BITS(attr->mtu_offload_enable, buff[1], 16, 1);
-    ZXIC_COMM_UINT32_GET_BITS(attr->mtu, buff[1], 0, 16);
-
-    ZXIC_COMM_UINT32_GET_BITS(attr->hw_bond_enable, buff[2], 31, 1);
-    ZXIC_COMM_UINT32_GET_BITS(attr->bond_link_up, buff[2], 30, 1);
-    ZXIC_COMM_UINT32_GET_BITS(attr->is_up, buff[2], 29, 1);
-    ZXIC_COMM_UINT32_GET_BITS(attr->rsv4, buff[2], 27, 2);
-    ZXIC_COMM_UINT32_GET_BITS(attr->bond_pf_vqm_vfid, buff[2], 16, 11);
-    ZXIC_COMM_UINT32_GET_BITS(attr->rsv5, buff[2], 12, 4);
-    ZXIC_COMM_UINT32_GET_BITS(attr->pf_memport_qid, buff[2], 0, 12);
-
-    ZXIC_COMM_UINT32_GET_BITS(attr->rsv6, buff[3], 27, 5);
-    ZXIC_COMM_UINT32_GET_BITS(attr->ovs_pf_vfid, buff[3], 16, 11);
-    ZXIC_COMM_UINT32_GET_BITS(attr->rsv7, buff[3], 0, 16);
-
-    return DPP_OK;
+	ZXDH_PANEL_PORT_T *attr = (ZXDH_PANEL_PORT_T *)pData;
+
+	ZXIC_COMM_UINT32_GET_BITS(attr->hit_flag, buff[0], 31, 1);
+	ZXIC_COMM_UINT32_GET_BITS(attr->trust_mode, buff[0], 30, 1);
+	ZXIC_COMM_UINT32_GET_BITS(attr->ptp_tc_enable, buff[0], 28, 2);
+	ZXIC_COMM_UINT32_GET_BITS(attr->tm_shape_enable, buff[0], 27, 1);
+	ZXIC_COMM_UINT32_GET_BITS(attr->pf_vqm_vfid, buff[0], 16, 11);
+	ZXIC_COMM_UINT32_GET_BITS(attr->rsv2, buff[0], 11, 5);
+	ZXIC_COMM_UINT32_GET_BITS(attr->ptp_port_vfid, buff[0], 0, 11);
+	ZXIC_COMM_UINT32_GET_BITS(attr->tm_base_queue, buff[1], 20, 12);
+	ZXIC_COMM_UINT32_GET_BITS(attr->rsv3, buff[1], 17, 3);
+	ZXIC_COMM_UINT32_GET_BITS(attr->mtu_offload_enable, buff[1], 16, 1);
+	ZXIC_COMM_UINT32_GET_BITS(attr->mtu, buff[1], 0, 16);
+
+	ZXIC_COMM_UINT32_GET_BITS(attr->hw_bond_enable, buff[2], 31, 1);
+	ZXIC_COMM_UINT32_GET_BITS(attr->bond_link_up, buff[2], 30, 1);
+	ZXIC_COMM_UINT32_GET_BITS(attr->is_up, buff[2], 29, 1);
+	ZXIC_COMM_UINT32_GET_BITS(attr->rsv4, buff[2], 27, 2);
+	ZXIC_COMM_UINT32_GET_BITS(attr->bond_pf_vqm_vfid, buff[2], 16, 11);
+	ZXIC_COMM_UINT32_GET_BITS(attr->rsv5, buff[2], 12, 4);
+	ZXIC_COMM_UINT32_GET_BITS(attr->pf_memport_qid, buff[2], 0, 12);
+
+	ZXIC_COMM_UINT32_GET_BITS(attr->rsv6, buff[3], 27, 5);
+	ZXIC_COMM_UINT32_GET_BITS(attr->ovs_pf_vfid, buff[3], 16, 11);
+	ZXIC_COMM_UINT32_GET_BITS(attr->rsv7, buff[3], 0, 16);
+
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_set_dscp_to_up_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXDH_DSCP_TO_UP_T* attr = (ZXDH_DSCP_TO_UP_T*)pData;
+	ZXDH_DSCP_TO_UP_T *attr = (ZXDH_DSCP_TO_UP_T *)pData;
 
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->hit_flag, 31, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->rsv1, 3, 28);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->up, 0, 3);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->hit_flag, 31, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->rsv1, 3, 28);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->up, 0, 3);
 
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->rsv2, 0, 32);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->rsv2, 0, 32);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_get_dscp_to_up_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXDH_DSCP_TO_UP_T* attr = (ZXDH_DSCP_TO_UP_T*)pData;
+	ZXDH_DSCP_TO_UP_T *attr = (ZXDH_DSCP_TO_UP_T *)pData;
+
+	ZXIC_COMM_UINT32_GET_BITS(attr->hit_flag, buff[0], 31, 1);
+	ZXIC_COMM_UINT32_GET_BITS(attr->rsv1, buff[0], 3, 28);
+	ZXIC_COMM_UINT32_GET_BITS(attr->up, buff[0], 0, 3);
 
-    ZXIC_COMM_UINT32_GET_BITS(attr->hit_flag, buff[0], 31, 1);
-    ZXIC_COMM_UINT32_GET_BITS(attr->rsv1, buff[0], 3, 28);
-    ZXIC_COMM_UINT32_GET_BITS(attr->up, buff[0], 0, 3);
+	ZXIC_COMM_UINT32_GET_BITS(attr->rsv2, buff[1], 0, 32);
 
-    ZXIC_COMM_UINT32_GET_BITS(attr->rsv2, buff[1], 0, 32);
-    
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_set_up_to_tc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXDH_UP_TO_TC_T* attr = (ZXDH_UP_TO_TC_T*)pData;
+	ZXDH_UP_TO_TC_T *attr = (ZXDH_UP_TO_TC_T *)pData;
 
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->hit_flag, 31, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->rsv1, 3, 28);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->tc, 0, 3);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->hit_flag, 31, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->rsv1, 3, 28);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->tc, 0, 3);
 
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->rsv2, 0, 32);
-   
-    return DPP_OK;
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->rsv2, 0, 32);
+
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_get_up_to_tc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXDH_UP_TO_TC_T* attr = (ZXDH_UP_TO_TC_T*)pData;
+	ZXDH_UP_TO_TC_T *attr = (ZXDH_UP_TO_TC_T *)pData;
+
+	ZXIC_COMM_UINT32_GET_BITS(attr->hit_flag, buff[0], 31, 1);
+	ZXIC_COMM_UINT32_GET_BITS(attr->rsv1, buff[0], 3, 28);
+	ZXIC_COMM_UINT32_GET_BITS(attr->tc, buff[0], 0, 3);
 
-    ZXIC_COMM_UINT32_GET_BITS(attr->hit_flag, buff[0], 31, 1);
-    ZXIC_COMM_UINT32_GET_BITS(attr->rsv1, buff[0], 3, 28);
-    ZXIC_COMM_UINT32_GET_BITS(attr->tc, buff[0], 0, 3);
+	ZXIC_COMM_UINT32_GET_BITS(attr->rsv2, buff[1], 0, 32);
 
-    ZXIC_COMM_UINT32_GET_BITS(attr->rsv2, buff[1], 0, 32);
-    
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_set_rss_to_vqid_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXDH_RSS_TO_VQID_T *attr = (ZXDH_RSS_TO_VQID_T*)pData;
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->hit_flag, 31, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->vqm_qid[0], 16, 15);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->vqm_qid[1], 0, 16);
+	ZXDH_RSS_TO_VQID_T *attr = (ZXDH_RSS_TO_VQID_T *)pData;
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->hit_flag, 31, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->vqm_qid[0], 16, 15);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], attr->vqm_qid[1], 0, 16);
 
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->vqm_qid[2], 16, 16);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->vqm_qid[3], 0, 16);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->vqm_qid[2], 16, 16);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], attr->vqm_qid[3], 0, 16);
 
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->vqm_qid[4], 16, 16);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->vqm_qid[5], 0, 16);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->vqm_qid[4], 16, 16);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], attr->vqm_qid[5], 0, 16);
 
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[3], attr->vqm_qid[6], 16, 16);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[3], attr->vqm_qid[7], 0, 16);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[3], attr->vqm_qid[6], 16, 16);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[3], attr->vqm_qid[7], 0, 16);
 
-    return DPP_OK; 
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_get_rss_to_vqid_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXDH_RSS_TO_VQID_T *attr = (ZXDH_RSS_TO_VQID_T*)pData;
+	ZXDH_RSS_TO_VQID_T *attr = (ZXDH_RSS_TO_VQID_T *)pData;
 
-    ZXIC_COMM_UINT32_GET_BITS(attr->hit_flag, buff[0], 31, 1);
-    ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[0], buff[0], 16, 15);
-    ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[1], buff[0], 0, 16);
+	ZXIC_COMM_UINT32_GET_BITS(attr->hit_flag, buff[0], 31, 1);
+	ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[0], buff[0], 16, 15);
+	ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[1], buff[0], 0, 16);
 
-    ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[2], buff[1],16, 16);
-    ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[3], buff[1], 0, 16);
+	ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[2], buff[1], 16, 16);
+	ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[3], buff[1], 0, 16);
 
-    ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[4], buff[2], 16, 16);
-    ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[5], buff[2], 0, 16);
+	ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[4], buff[2], 16, 16);
+	ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[5], buff[2], 0, 16);
 
-    ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[6], buff[3], 16, 16);
-    ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[7], buff[3], 0, 16);
+	ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[6], buff[3], 16, 16);
+	ZXIC_COMM_UINT32_GET_BITS(attr->vqm_qid[7], buff[3], 0, 16);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_set_vlan_filter_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXDH_VLAN_FILTER_T *vlan_filter_table = (ZXDH_VLAN_FILTER_T *)pData;
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vlan_filter_table->hit_flag, 31, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vlan_filter_table->rsv, 24, 7);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vlan_filter_table->vport_bitmap[0], 16, 8);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vlan_filter_table->vport_bitmap[1], 8, 8);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vlan_filter_table->vport_bitmap[2], 0, 8);
-
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], vlan_filter_table->vport_bitmap[3], 24, 8);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], vlan_filter_table->vport_bitmap[4], 16, 8);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], vlan_filter_table->vport_bitmap[5], 8, 8);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], vlan_filter_table->vport_bitmap[6], 0, 8);
-
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], vlan_filter_table->vport_bitmap[7], 24, 8);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], vlan_filter_table->vport_bitmap[8], 16, 8);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], vlan_filter_table->vport_bitmap[9], 8, 8);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], vlan_filter_table->vport_bitmap[10], 0, 8);
-
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[3], vlan_filter_table->vport_bitmap[11], 24, 8);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[3], vlan_filter_table->vport_bitmap[12], 16, 8);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[3], vlan_filter_table->vport_bitmap[13], 8, 8);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[3], vlan_filter_table->vport_bitmap[14], 0, 8);
-    return DPP_OK;
+	ZXDH_VLAN_FILTER_T *vlan_filter_table = (ZXDH_VLAN_FILTER_T *)pData;
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vlan_filter_table->hit_flag, 31, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vlan_filter_table->rsv, 24, 7);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vlan_filter_table->vport_bitmap[0], 16,
+								8);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vlan_filter_table->vport_bitmap[1], 8,
+								8);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vlan_filter_table->vport_bitmap[2], 0,
+								8);
+
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], vlan_filter_table->vport_bitmap[3], 24,
+								8);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], vlan_filter_table->vport_bitmap[4], 16,
+								8);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], vlan_filter_table->vport_bitmap[5], 8,
+								8);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], vlan_filter_table->vport_bitmap[6], 0,
+								8);
+
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], vlan_filter_table->vport_bitmap[7], 24,
+								8);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], vlan_filter_table->vport_bitmap[8], 16,
+								8);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], vlan_filter_table->vport_bitmap[9], 8,
+								8);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], vlan_filter_table->vport_bitmap[10], 0,
+								8);
+
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[3], vlan_filter_table->vport_bitmap[11],
+								24, 8);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[3], vlan_filter_table->vport_bitmap[12],
+								16, 8);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[3], vlan_filter_table->vport_bitmap[13], 8,
+								8);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[3], vlan_filter_table->vport_bitmap[14], 0,
+								8);
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_get_vlan_filter_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXDH_VLAN_FILTER_T *vlan_filter_table = (ZXDH_VLAN_FILTER_T *)pData;
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->hit_flag, buff[0], 31, 1);
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->rsv, buff[0], 24, 7);
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[0], buff[0], 16, 8);
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[1], buff[0], 8, 8);
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[2], buff[0], 0, 8);
-
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[3], buff[1], 24, 8);
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[4], buff[1], 16, 8);
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[5], buff[1], 8, 8);
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[6], buff[1], 0, 8);
-
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[7], buff[2], 24, 8);
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[8], buff[2], 16, 8);
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[9], buff[2], 8, 8);
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[10], buff[2], 0, 8);
-
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[11], buff[3], 24, 8);
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[12], buff[3], 16, 8);
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[13], buff[3], 8, 8);
-    ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[14], buff[3], 0, 8);
-    return DPP_OK;
+	ZXDH_VLAN_FILTER_T *vlan_filter_table = (ZXDH_VLAN_FILTER_T *)pData;
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->hit_flag, buff[0], 31, 1);
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->rsv, buff[0], 24, 7);
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[0], buff[0], 16,
+							  8);
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[1], buff[0], 8,
+							  8);
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[2], buff[0], 0,
+							  8);
+
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[3], buff[1], 24,
+							  8);
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[4], buff[1], 16,
+							  8);
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[5], buff[1], 8,
+							  8);
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[6], buff[1], 0,
+							  8);
+
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[7], buff[2], 24,
+							  8);
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[8], buff[2], 16,
+							  8);
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[9], buff[2], 8,
+							  8);
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[10], buff[2], 0,
+							  8);
+
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[11], buff[3], 24,
+							  8);
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[12], buff[3], 16,
+							  8);
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[13], buff[3], 8,
+							  8);
+	ZXIC_COMM_UINT32_GET_BITS(vlan_filter_table->vport_bitmap[14], buff[3], 0,
+							  8);
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_set_lag_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXDH_LAG_T *lag_entry = (ZXDH_LAG_T *)pData;
+	ZXDH_LAG_T *lag_entry = (ZXDH_LAG_T *)pData;
 
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->hit_flag, 31, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->rsv1, 27, 4);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->member_num, 24, 3);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->bond_mode, 16, 8);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->hash_factor, 8, 8);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->rsv2, 0, 8);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->hit_flag, 31, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->rsv1, 27, 4);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->member_num, 24, 3);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->bond_mode, 16, 8);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->hash_factor, 8, 8);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], lag_entry->rsv2, 0, 8);
 
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], lag_entry->rsv2, 16, 16);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], lag_entry->member_bitmap, 0, 16);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], lag_entry->rsv2, 16, 16);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], lag_entry->member_bitmap, 0, 16);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_get_lag_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXDH_LAG_T *lag_entry = (ZXDH_LAG_T *)pData;
+	ZXDH_LAG_T *lag_entry = (ZXDH_LAG_T *)pData;
 
-    ZXIC_COMM_UINT32_GET_BITS(lag_entry->hit_flag, buff[0], 31, 1);
-    ZXIC_COMM_UINT32_GET_BITS(lag_entry->rsv1, buff[0], 27, 4);
-    ZXIC_COMM_UINT32_GET_BITS(lag_entry->member_num, buff[0], 24, 3);
-    ZXIC_COMM_UINT32_GET_BITS(lag_entry->bond_mode, buff[0], 16, 8);
-    ZXIC_COMM_UINT32_GET_BITS(lag_entry->hash_factor, buff[0], 8, 8);
-    ZXIC_COMM_UINT32_GET_BITS(lag_entry->rsv2, buff[0], 0, 8);
+	ZXIC_COMM_UINT32_GET_BITS(lag_entry->hit_flag, buff[0], 31, 1);
+	ZXIC_COMM_UINT32_GET_BITS(lag_entry->rsv1, buff[0], 27, 4);
+	ZXIC_COMM_UINT32_GET_BITS(lag_entry->member_num, buff[0], 24, 3);
+	ZXIC_COMM_UINT32_GET_BITS(lag_entry->bond_mode, buff[0], 16, 8);
+	ZXIC_COMM_UINT32_GET_BITS(lag_entry->hash_factor, buff[0], 8, 8);
+	ZXIC_COMM_UINT32_GET_BITS(lag_entry->rsv2, buff[0], 0, 8);
 
-    ZXIC_COMM_UINT32_GET_BITS(lag_entry->rsv2, buff[1], 16, 16);
-    ZXIC_COMM_UINT32_GET_BITS(lag_entry->member_bitmap, buff[1], 0, 16);
+	ZXIC_COMM_UINT32_GET_BITS(lag_entry->rsv2, buff[1], 16, 16);
+	ZXIC_COMM_UINT32_GET_BITS(lag_entry->member_bitmap, buff[1], 0, 16);
 
-    return DPP_OK; 
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_set_bc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXIC_UINT32 bc_bitmap = 0;
-    ZXDH_BC_T *bc_entry = (ZXDH_BC_T *)pData;
+	ZXIC_UINT32 bc_bitmap = 0;
+	ZXDH_BC_T *bc_entry = (ZXDH_BC_T *)pData;
 
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], bc_entry->hit_flag, 31, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], bc_entry->rsv1, 0, 31);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], bc_entry->hit_flag, 31, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], bc_entry->rsv1, 0, 31);
 
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], bc_entry->rsv2, 0, 32);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], bc_entry->rsv2, 0, 32);
 
-    bc_bitmap = bc_entry->bc_bitmap >> 32;
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], bc_bitmap, 0, 32);
+	bc_bitmap = bc_entry->bc_bitmap >> 32;
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], bc_bitmap, 0, 32);
 
-    bc_bitmap = bc_entry->bc_bitmap;
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[3], bc_bitmap, 0, 32);
+	bc_bitmap = bc_entry->bc_bitmap;
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[3], bc_bitmap, 0, 32);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_get_bc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXIC_UINT32 bc_bitmap = 0;
-    ZXDH_BC_T *bc_entry = (ZXDH_BC_T *)pData;
+	ZXIC_UINT32 bc_bitmap = 0;
+	ZXDH_BC_T *bc_entry = (ZXDH_BC_T *)pData;
 
-    ZXIC_COMM_UINT32_GET_BITS(bc_entry->hit_flag, buff[0], 31, 1);
-    ZXIC_COMM_UINT32_GET_BITS(bc_entry->rsv1, buff[0], 0, 31);
+	ZXIC_COMM_UINT32_GET_BITS(bc_entry->hit_flag, buff[0], 31, 1);
+	ZXIC_COMM_UINT32_GET_BITS(bc_entry->rsv1, buff[0], 0, 31);
 
-    ZXIC_COMM_UINT32_GET_BITS(bc_entry->rsv2, buff[1], 0, 32);
+	ZXIC_COMM_UINT32_GET_BITS(bc_entry->rsv2, buff[1], 0, 32);
 
-    ZXIC_COMM_UINT32_GET_BITS(bc_bitmap, buff[2], 0, 32);
-    bc_entry->bc_bitmap = (((ZXIC_UINT64)bc_bitmap) << 32);
+	ZXIC_COMM_UINT32_GET_BITS(bc_bitmap, buff[2], 0, 32);
+	bc_entry->bc_bitmap = (((ZXIC_UINT64)bc_bitmap) << 32);
 
-    ZXIC_COMM_UINT32_GET_BITS(bc_bitmap, buff[3], 0, 32);
-    bc_entry->bc_bitmap |= bc_bitmap;
+	ZXIC_COMM_UINT32_GET_BITS(bc_bitmap, buff[3], 0, 32);
+	bc_entry->bc_bitmap |= bc_bitmap;
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_set_promisc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXIC_UINT32 bitmap = 0;
-    ZXDH_PROMISC_T *promisc_entry = (ZXDH_PROMISC_T *)pData;
+	ZXIC_UINT32 bitmap = 0;
+	ZXDH_PROMISC_T *promisc_entry = (ZXDH_PROMISC_T *)pData;
 
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], promisc_entry->hit_flag, 31, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], promisc_entry->pf_enable, 30, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], promisc_entry->rsv1, 0, 30);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], promisc_entry->hit_flag, 31, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], promisc_entry->pf_enable, 30, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], promisc_entry->rsv1, 0, 30);
 
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], promisc_entry->rsv2, 0, 32);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], promisc_entry->rsv2, 0, 32);
 
-    bitmap = promisc_entry->bitmap >> 32;
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[2], bitmap, 0, 32);
+	bitmap = promisc_entry->bitmap >> 32;
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[2], bitmap, 0, 32);
 
-    bitmap = promisc_entry->bitmap;
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[3], bitmap, 0, 32);
+	bitmap = promisc_entry->bitmap;
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[3], bitmap, 0, 32);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_get_promisc_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXIC_UINT32 bitmap = 0;
-    ZXDH_PROMISC_T *promisc_entry = (ZXDH_PROMISC_T *)pData;
+	ZXIC_UINT32 bitmap = 0;
+	ZXDH_PROMISC_T *promisc_entry = (ZXDH_PROMISC_T *)pData;
 
-    ZXIC_COMM_UINT32_GET_BITS(promisc_entry->hit_flag, buff[0], 31, 1);
-    ZXIC_COMM_UINT32_GET_BITS(promisc_entry->pf_enable, buff[0], 30, 1);
-    ZXIC_COMM_UINT32_GET_BITS(promisc_entry->rsv1, buff[0], 0, 30);
+	ZXIC_COMM_UINT32_GET_BITS(promisc_entry->hit_flag, buff[0], 31, 1);
+	ZXIC_COMM_UINT32_GET_BITS(promisc_entry->pf_enable, buff[0], 30, 1);
+	ZXIC_COMM_UINT32_GET_BITS(promisc_entry->rsv1, buff[0], 0, 30);
 
-    ZXIC_COMM_UINT32_GET_BITS(promisc_entry->rsv2, buff[1], 0, 32);
+	ZXIC_COMM_UINT32_GET_BITS(promisc_entry->rsv2, buff[1], 0, 32);
 
-    ZXIC_COMM_UINT32_GET_BITS(bitmap, buff[2], 0, 32);
-    promisc_entry->bitmap = (((ZXIC_UINT64)bitmap) << 32);
+	ZXIC_COMM_UINT32_GET_BITS(bitmap, buff[2], 0, 32);
+	promisc_entry->bitmap = (((ZXIC_UINT64)bitmap) << 32);
 
-    ZXIC_COMM_UINT32_GET_BITS(bitmap, buff[3], 0, 32);
-    promisc_entry->bitmap |= bitmap;
+	ZXIC_COMM_UINT32_GET_BITS(bitmap, buff[3], 0, 32);
+	promisc_entry->bitmap |= bitmap;
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_set_vhca_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXDH_VHCA_T *vhca_entry = (ZXDH_VHCA_T *)pData;
+	ZXDH_VHCA_T *vhca_entry = (ZXDH_VHCA_T *)pData;
 
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vhca_entry->valid, 31, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vhca_entry->rsv1, 11, 20);
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vhca_entry->vqm_vfid, 0, 11);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vhca_entry->valid, 31, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vhca_entry->rsv1, 11, 20);
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[0], vhca_entry->vqm_vfid, 0, 11);
 
-    ZXIC_COMM_UINT32_WRITE_BITS(buff[1], vhca_entry->rsv2, 0, 32);
-    return DPP_OK;
+	ZXIC_COMM_UINT32_WRITE_BITS(buff[1], vhca_entry->rsv2, 0, 32);
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_get_vhca_data(ZXIC_VOID *pData, ZXIC_UINT32 buff[4])
 {
-    ZXDH_VHCA_T *vhca_entry = (ZXDH_VHCA_T *)pData;
+	ZXDH_VHCA_T *vhca_entry = (ZXDH_VHCA_T *)pData;
 
-    ZXIC_COMM_UINT32_GET_BITS(vhca_entry->valid, buff[0], 31, 1);
-    ZXIC_COMM_UINT32_GET_BITS(vhca_entry->rsv1, buff[0], 11, 20);
-    ZXIC_COMM_UINT32_GET_BITS(vhca_entry->vqm_vfid, buff[0], 0, 11);
+	ZXIC_COMM_UINT32_GET_BITS(vhca_entry->valid, buff[0], 31, 1);
+	ZXIC_COMM_UINT32_GET_BITS(vhca_entry->rsv1, buff[0], 11, 20);
+	ZXIC_COMM_UINT32_GET_BITS(vhca_entry->vqm_vfid, buff[0], 0, 11);
 
-    ZXIC_COMM_UINT32_GET_BITS(vhca_entry->rsv2, buff[1], 0, 32);
+	ZXIC_COMM_UINT32_GET_BITS(vhca_entry->rsv2, buff[1], 0, 32);
 
-    return DPP_OK; 
+	return DPP_OK;
 }
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_hash.c b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_hash.c
index 84d731930b9d215406aa1e36ead57ee4a9f48ef1..fae6898004ddf4421cc7cec0d8a86cf12910f4e3 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_hash.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_hash.c
@@ -8,581 +8,497 @@
 #include "dpp_drv_hash.h"
 #include "dpp_kernel_init.h"
 
-static DPP_APT_HASH_TABLE_T g_hashSdtTable[] =
-{
-    {
-        ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0,
-        {
-            DPP_SDT_TBLT_HASH,
-            ZXDH_HASH_FUNC0,     
-            HASH_KEY_128b,
-            8,                 // rsv(16) + mac(48)
-            0,
-            0,
-            0,
-            ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR,
-            DPP_SDT_RSP_32b,   // hit-flag(1) + rsv(20) + VQM_VFID(11)
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        0,
-        dpp_apt_set_l2entry_data,
-        dpp_apt_get_l2entry_data
-    },
-    {
-        ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT1,
-        {
-            DPP_SDT_TBLT_HASH,
-            ZXDH_HASH_FUNC0,     
-            HASH_KEY_128b,
-            8,                 // rsv(16) + mac(48)
-            1,
-            0,
-            0,
-            ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR,
-            DPP_SDT_RSP_32b,   // hit-flag(1) + rsv(20) + VQM_VFID(11)
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        0,
-        dpp_apt_set_l2entry_data,
-        dpp_apt_get_l2entry_data
-    },
-    {
-        ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT2,
-        {
-            DPP_SDT_TBLT_HASH,
-            ZXDH_HASH_FUNC0,     
-            HASH_KEY_128b,
-            8,                 // rsv(16) + mac(48)
-            2,
-            0,
-            0,
-            ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR,
-            DPP_SDT_RSP_32b,   // hit-flag(1) + rsv(20) + VQM_VFID(11)
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        0,
-        dpp_apt_set_l2entry_data,
-        dpp_apt_get_l2entry_data
-    },
-    {
-        ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT3,
-        {
-            DPP_SDT_TBLT_HASH,
-            ZXDH_HASH_FUNC0,     
-            HASH_KEY_128b,
-            8,                 // rsv(16) + mac(48)
-            3,
-            0,
-            0,
-            ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR,
-            DPP_SDT_RSP_32b,   // hit-flag(1) + rsv(20) + VQM_VFID(11)
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        0,
-        dpp_apt_set_l2entry_data,
-        dpp_apt_get_l2entry_data
-    },
-    {
-        ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT4,
-        {
-            DPP_SDT_TBLT_HASH,
-            ZXDH_HASH_FUNC0,     
-            HASH_KEY_128b,
-            8,                 // rsv(16) + mac(48)
-            4,
-            0,
-            0,
-            ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR,
-            DPP_SDT_RSP_32b,   // hit-flag(1) + rsv(20) + VQM_VFID(11)
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        0,
-        dpp_apt_set_l2entry_data,
-        dpp_apt_get_l2entry_data
-    },
-    {
-        ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT5,
-        {
-            DPP_SDT_TBLT_HASH,
-            ZXDH_HASH_FUNC0,     
-            HASH_KEY_128b,
-            8,                 // rsv(16) + mac(48)
-            5,
-            0,
-            0,
-            ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR,
-            DPP_SDT_RSP_32b,   // hit-flag(1) + rsv(20) + VQM_VFID(11)
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        0,
-        dpp_apt_set_l2entry_data,
-        dpp_apt_get_l2entry_data
-    },
-    {
-        ZXDH_SDT_MC_TABLE_PHYPORT0,
-        {
-            DPP_SDT_TBLT_HASH,
-            ZXDH_HASH_FUNC0,
-            HASH_KEY_256b,
-            8,                      // rsv(14) + vf_group_id(2) + MC_MAC(48)
-            12,
-            0,
-            0,
-            0,
-            DPP_SDT_RSP_128b,       // hit_flag(1) + rsv(63) + MC_BITMAP(64)
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        0,
-        dpp_apt_set_mc_data,
-        dpp_apt_get_mc_data
-    },
-    {
-        ZXDH_SDT_MC_TABLE_PHYPORT1,
-        {
-            DPP_SDT_TBLT_HASH,
-            ZXDH_HASH_FUNC0,
-            HASH_KEY_256b,
-            8,                      // rsv(14) + vf_group_id(2) + MC_MAC(48)
-            13,
-            0,
-            0,
-            0,
-            DPP_SDT_RSP_128b,       // hit_flag(1) + rsv(63) + MC_BITMAP(64)
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        0,
-        dpp_apt_set_mc_data,
-        dpp_apt_get_mc_data
-    },
-    {
-        ZXDH_SDT_MC_TABLE_PHYPORT2,
-        {
-            DPP_SDT_TBLT_HASH,
-            ZXDH_HASH_FUNC0,
-            HASH_KEY_256b,
-            8,                      // rsv(14) + vf_group_id(2) + MC_MAC(48)
-            14,
-            0,
-            0,
-            0,
-            DPP_SDT_RSP_128b,       // hit_flag(1) + rsv(63) + MC_BITMAP(64)
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        0,
-        dpp_apt_set_mc_data,
-        dpp_apt_get_mc_data
-    },
-    {
-        ZXDH_SDT_MC_TABLE_PHYPORT3,
-        {
-            DPP_SDT_TBLT_HASH,
-            ZXDH_HASH_FUNC0,
-            HASH_KEY_256b,
-            8,                      // rsv(14) + vf_group_id(2) + MC_MAC(48)
-            15,
-            0,
-            0,
-            0,
-            DPP_SDT_RSP_128b,       // hit_flag(1) + rsv(63) + MC_BITMAP(64)
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        0,
-        dpp_apt_set_mc_data,
-        dpp_apt_get_mc_data
-    },
-    {
-        ZXDH_SDT_MC_TABLE_PHYPORT4,
-        {
-            DPP_SDT_TBLT_HASH,
-            ZXDH_HASH_FUNC0,
-            HASH_KEY_256b,
-            8,                      // rsv(14) + vf_group_id(2) + MC_MAC(48)
-            16,
-            0,
-            0,
-            0,
-            DPP_SDT_RSP_128b,       // hit_flag(1) + rsv(63) + MC_BITMAP(64)
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        0,
-        dpp_apt_set_mc_data,
-        dpp_apt_get_mc_data
-    },
-    {
-        ZXDH_SDT_MC_TABLE_PHYPORT5,
-        {
-            DPP_SDT_TBLT_HASH,
-            ZXDH_HASH_FUNC0,
-            HASH_KEY_256b,
-            8,                      // rsv(14) + vf_group_id(2) + MC_MAC(48)
-            17,
-            0,
-            0,
-            0,
-            DPP_SDT_RSP_128b,       // hit_flag(1) + rsv(63) + MC_BITMAP(64)
-            ZXDH_SDT_CLUTH_DISABLE
-        },
-        0,
-        dpp_apt_set_mc_data,
-        dpp_apt_get_mc_data
-    }
+static DPP_APT_HASH_TABLE_T g_hashSdtTable[] = {
+	{ ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0,
+	  { DPP_SDT_TBLT_HASH, ZXDH_HASH_FUNC0, HASH_KEY_128b,
+		8, // rsv(16) + mac(48)
+		0, 0, 0, ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR,
+		DPP_SDT_RSP_32b, // hit-flag(1) + rsv(20) + VQM_VFID(11)
+		ZXDH_SDT_CLUTH_DISABLE },
+	  0,
+	  dpp_apt_set_l2entry_data,
+	  dpp_apt_get_l2entry_data },
+	{ ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT1,
+	  { DPP_SDT_TBLT_HASH, ZXDH_HASH_FUNC0, HASH_KEY_128b,
+		8, // rsv(16) + mac(48)
+		1, 0, 0, ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR,
+		DPP_SDT_RSP_32b, // hit-flag(1) + rsv(20) + VQM_VFID(11)
+		ZXDH_SDT_CLUTH_DISABLE },
+	  0,
+	  dpp_apt_set_l2entry_data,
+	  dpp_apt_get_l2entry_data },
+	{ ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT2,
+	  { DPP_SDT_TBLT_HASH, ZXDH_HASH_FUNC0, HASH_KEY_128b,
+		8, // rsv(16) + mac(48)
+		2, 0, 0, ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR,
+		DPP_SDT_RSP_32b, // hit-flag(1) + rsv(20) + VQM_VFID(11)
+		ZXDH_SDT_CLUTH_DISABLE },
+	  0,
+	  dpp_apt_set_l2entry_data,
+	  dpp_apt_get_l2entry_data },
+	{ ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT3,
+	  { DPP_SDT_TBLT_HASH, ZXDH_HASH_FUNC0, HASH_KEY_128b,
+		8, // rsv(16) + mac(48)
+		3, 0, 0, ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR,
+		DPP_SDT_RSP_32b, // hit-flag(1) + rsv(20) + VQM_VFID(11)
+		ZXDH_SDT_CLUTH_DISABLE },
+	  0,
+	  dpp_apt_set_l2entry_data,
+	  dpp_apt_get_l2entry_data },
+	{ ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT4,
+	  { DPP_SDT_TBLT_HASH, ZXDH_HASH_FUNC0, HASH_KEY_128b,
+		8, // rsv(16) + mac(48)
+		4, 0, 0, ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR,
+		DPP_SDT_RSP_32b, // hit-flag(1) + rsv(20) + VQM_VFID(11)
+		ZXDH_SDT_CLUTH_DISABLE },
+	  0,
+	  dpp_apt_set_l2entry_data,
+	  dpp_apt_get_l2entry_data },
+	{ ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT5,
+	  { DPP_SDT_TBLT_HASH, ZXDH_HASH_FUNC0, HASH_KEY_128b,
+		8, // rsv(16) + mac(48)
+		5, 0, 0, ZXDH_L2ENTRY_KEEPALIVE_ERAM_BAADDR,
+		DPP_SDT_RSP_32b, // hit-flag(1) + rsv(20) + VQM_VFID(11)
+		ZXDH_SDT_CLUTH_DISABLE },
+	  0,
+	  dpp_apt_set_l2entry_data,
+	  dpp_apt_get_l2entry_data },
+	{ ZXDH_SDT_MC_TABLE_PHYPORT0,
+	  { DPP_SDT_TBLT_HASH, ZXDH_HASH_FUNC0, HASH_KEY_256b,
+		8, // rsv(14) + vf_group_id(2) + MC_MAC(48)
+		12, 0, 0, 0,
+		DPP_SDT_RSP_128b, // hit_flag(1) + rsv(63) + MC_BITMAP(64)
+		ZXDH_SDT_CLUTH_DISABLE },
+	  0,
+	  dpp_apt_set_mc_data,
+	  dpp_apt_get_mc_data },
+	{ ZXDH_SDT_MC_TABLE_PHYPORT1,
+	  { DPP_SDT_TBLT_HASH, ZXDH_HASH_FUNC0, HASH_KEY_256b,
+		8, // rsv(14) + vf_group_id(2) + MC_MAC(48)
+		13, 0, 0, 0,
+		DPP_SDT_RSP_128b, // hit_flag(1) + rsv(63) + MC_BITMAP(64)
+		ZXDH_SDT_CLUTH_DISABLE },
+	  0,
+	  dpp_apt_set_mc_data,
+	  dpp_apt_get_mc_data },
+	{ ZXDH_SDT_MC_TABLE_PHYPORT2,
+	  { DPP_SDT_TBLT_HASH, ZXDH_HASH_FUNC0, HASH_KEY_256b,
+		8, // rsv(14) + vf_group_id(2) + MC_MAC(48)
+		14, 0, 0, 0,
+		DPP_SDT_RSP_128b, // hit_flag(1) + rsv(63) + MC_BITMAP(64)
+		ZXDH_SDT_CLUTH_DISABLE },
+	  0,
+	  dpp_apt_set_mc_data,
+	  dpp_apt_get_mc_data },
+	{ ZXDH_SDT_MC_TABLE_PHYPORT3,
+	  { DPP_SDT_TBLT_HASH, ZXDH_HASH_FUNC0, HASH_KEY_256b,
+		8, // rsv(14) + vf_group_id(2) + MC_MAC(48)
+		15, 0, 0, 0,
+		DPP_SDT_RSP_128b, // hit_flag(1) + rsv(63) + MC_BITMAP(64)
+		ZXDH_SDT_CLUTH_DISABLE },
+	  0,
+	  dpp_apt_set_mc_data,
+	  dpp_apt_get_mc_data },
+	{ ZXDH_SDT_MC_TABLE_PHYPORT4,
+	  { DPP_SDT_TBLT_HASH, ZXDH_HASH_FUNC0, HASH_KEY_256b,
+		8, // rsv(14) + vf_group_id(2) + MC_MAC(48)
+		16, 0, 0, 0,
+		DPP_SDT_RSP_128b, // hit_flag(1) + rsv(63) + MC_BITMAP(64)
+		ZXDH_SDT_CLUTH_DISABLE },
+	  0,
+	  dpp_apt_set_mc_data,
+	  dpp_apt_get_mc_data },
+	{ ZXDH_SDT_MC_TABLE_PHYPORT5,
+	  { DPP_SDT_TBLT_HASH, ZXDH_HASH_FUNC0, HASH_KEY_256b,
+		8, // rsv(14) + vf_group_id(2) + MC_MAC(48)
+		17, 0, 0, 0,
+		DPP_SDT_RSP_128b, // hit_flag(1) + rsv(63) + MC_BITMAP(64)
+		ZXDH_SDT_CLUTH_DISABLE },
+	  0,
+	  dpp_apt_set_mc_data,
+	  dpp_apt_get_mc_data }
 };
 
 DPP_APT_HASH_FUNC_RES_T func_res[] = {
-    /*func_id | zblk_num | zblk_bitmap | ddr_dis*/
-    {0,         10,        0x000003FF,   1},        /*混合，zblock0~zblock9*/
+	/*func_id | zblk_num | zblk_bitmap | ddr_dis*/
+	{ 0, 10, 0x000003FF, 1 }, /*混合，zblock0~zblock9*/
 };
 
 DPP_APT_HASH_BULK_RES_T bulk_res[] = {
-    /*funcid, bulkid, zcell_num, zreg_num, ddr_baddr, ddr_item_num, ddr_width_mode, ddr_crc_sel, ddr_ecc_en*/
-    {0,       0,      19,        19,       0,         0,            DDR_WIDTH_512b, 0,           0},
-    {0,       1,      10,        10,       0,         0,            DDR_WIDTH_512b, 0,           0},
-    {0,       2,      0,         0,        0,         0,            DDR_WIDTH_512b, 0,           0},
-    {0,       3,      2,         2,        0,         0,            DDR_WIDTH_512b, 0,           0},
-    {0,       4,      2,         2,        0,         0,            DDR_WIDTH_512b, 0,           0},
-    {0,       5,      3,         3,        0,         0,            DDR_WIDTH_512b, 0,           0},
-    {0,       6,      2,         2,        0,         0,            DDR_WIDTH_512b, 0,           0},
-    {0,       7,      2,         2,        0,         0,            DDR_WIDTH_512b, 0,           0},
+	/*funcid, bulkid, zcell_num, zreg_num, ddr_baddr, ddr_item_num, ddr_width_mode, ddr_crc_sel, ddr_ecc_en*/
+	{ 0, 0, 19, 19, 0, 0, DDR_WIDTH_512b, 0, 0 },
+	{ 0, 1, 10, 10, 0, 0, DDR_WIDTH_512b, 0, 0 },
+	{ 0, 2, 0, 0, 0, 0, DDR_WIDTH_512b, 0, 0 },
+	{ 0, 3, 2, 2, 0, 0, DDR_WIDTH_512b, 0, 0 },
+	{ 0, 4, 2, 2, 0, 0, DDR_WIDTH_512b, 0, 0 },
+	{ 0, 5, 3, 3, 0, 0, DDR_WIDTH_512b, 0, 0 },
+	{ 0, 6, 2, 2, 0, 0, DDR_WIDTH_512b, 0, 0 },
+	{ 0, 7, 2, 2, 0, 0, DDR_WIDTH_512b, 0, 0 },
 };
 
 DPP_HASH_INIT_T g_hashTable = {
-    .func_num = sizeof(func_res) / sizeof(DPP_APT_HASH_FUNC_RES_T), 
-    .func = func_res,
-    .bulk_num = sizeof(bulk_res) / sizeof(DPP_APT_HASH_BULK_RES_T),
-    .bulk = bulk_res,
-    .ser_num = sizeof(g_hashSdtTable) / sizeof(DPP_APT_HASH_TABLE_T),
-    .ser = g_hashSdtTable,
+	.func_num = sizeof(func_res) / sizeof(DPP_APT_HASH_FUNC_RES_T),
+	.func = func_res,
+	.bulk_num = sizeof(bulk_res) / sizeof(DPP_APT_HASH_BULK_RES_T),
+	.bulk = bulk_res,
+	.ser_num = sizeof(g_hashSdtTable) / sizeof(DPP_APT_HASH_TABLE_T),
+	.ser = g_hashSdtTable,
 };
 
 ZXIC_UINT32 dpp_apt_set_l2entry_data(ZXIC_VOID *pData, DPP_HASH_ENTRY *pEntry)
 {
-    ZXIC_UINT32 key = 0;
-    ZXIC_UINT32 rst = 0;
-    ZXDH_L2_ENTRY_T *pL2Entry = NULL;
+	ZXIC_UINT32 key = 0;
+	ZXIC_UINT32 rst = 0;
+	ZXDH_L2_ENTRY_T *pL2Entry = NULL;
+
+	ZXIC_COMM_CHECK_POINT(pData);
+	ZXIC_COMM_CHECK_POINT(pEntry);
+	ZXIC_COMM_CHECK_POINT(pEntry->p_key);
+	ZXIC_COMM_CHECK_POINT(pEntry->p_rst);
 
-    ZXIC_COMM_CHECK_POINT(pData);
-    ZXIC_COMM_CHECK_POINT(pEntry);
-    ZXIC_COMM_CHECK_POINT(pEntry->p_key);
-    ZXIC_COMM_CHECK_POINT(pEntry->p_rst);
+	pL2Entry = (ZXDH_L2_ENTRY_T *)pData;
+	ZXIC_COMM_UINT32_WRITE_BITS(key, pL2Entry->key.rsv, 16, 16);
 
-    pL2Entry = (ZXDH_L2_ENTRY_T *)pData;
-    ZXIC_COMM_UINT32_WRITE_BITS(key, pL2Entry->key.rsv, 16, 16);
+	zxic_comm_swap((ZXIC_UINT8 *)&key, sizeof(ZXIC_UINT32));
+	ZXIC_COMM_MEMCPY(pEntry->p_key + 1, &key, sizeof(ZXIC_UINT32));
 
-    zxic_comm_swap((ZXIC_UINT8 *)&key,sizeof(ZXIC_UINT32));
-    ZXIC_COMM_MEMCPY(pEntry->p_key+1,&key,sizeof(ZXIC_UINT32));
+	ZXIC_COMM_MEMCPY(pEntry->p_key + 3, pL2Entry->key.dmac_addr, 6);
 
-    ZXIC_COMM_MEMCPY(pEntry->p_key + 3, pL2Entry->key.dmac_addr, 6);
-            
-    ZXIC_COMM_UINT32_WRITE_BITS(rst, pL2Entry->entry.hit_flag, 31, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(rst, pL2Entry->entry.rsv, 11, 20);
-    ZXIC_COMM_UINT32_WRITE_BITS(rst, pL2Entry->entry.vqm_vfid, 0, 11);
+	ZXIC_COMM_UINT32_WRITE_BITS(rst, pL2Entry->entry.hit_flag, 31, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(rst, pL2Entry->entry.rsv, 11, 20);
+	ZXIC_COMM_UINT32_WRITE_BITS(rst, pL2Entry->entry.vqm_vfid, 0, 11);
 
-    zxic_comm_swap((ZXIC_UINT8 *)&rst,sizeof(ZXIC_UINT32));
-    ZXIC_COMM_MEMCPY(pEntry->p_rst,&rst,sizeof(ZXIC_UINT32)); 
+	zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32));
+	ZXIC_COMM_MEMCPY(pEntry->p_rst, &rst, sizeof(ZXIC_UINT32));
 
-    return DPP_OK; 
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_get_l2entry_data(ZXIC_VOID *pData, DPP_HASH_ENTRY *pEntry)
-{  
-    ZXDH_L2_ENTRY_T *pL2Entry = NULL;
+{
+	ZXDH_L2_ENTRY_T *pL2Entry = NULL;
 
-    ZXIC_UINT32 key = 0;
+	ZXIC_UINT32 key = 0;
 
-    ZXIC_COMM_CHECK_POINT(pData);
-    ZXIC_COMM_CHECK_POINT(pEntry);
-    ZXIC_COMM_CHECK_POINT(pEntry->p_rst);
+	ZXIC_COMM_CHECK_POINT(pData);
+	ZXIC_COMM_CHECK_POINT(pEntry);
+	ZXIC_COMM_CHECK_POINT(pEntry->p_rst);
 
-    pL2Entry = (ZXDH_L2_ENTRY_T *)pData;
+	pL2Entry = (ZXDH_L2_ENTRY_T *)pData;
 
-    key = *(ZXIC_UINT32 *)(pEntry->p_key + 1);
-    zxic_comm_swap((ZXIC_UINT8 *)&key,sizeof(ZXIC_UINT32));
-    ZXIC_COMM_UINT32_GET_BITS(pL2Entry->key.rsv, key, 16, 16);
+	key = *(ZXIC_UINT32 *)(pEntry->p_key + 1);
+	zxic_comm_swap((ZXIC_UINT8 *)&key, sizeof(ZXIC_UINT32));
+	ZXIC_COMM_UINT32_GET_BITS(pL2Entry->key.rsv, key, 16, 16);
 
-    ZXIC_COMM_MEMCPY(pL2Entry->key.dmac_addr, pEntry->p_key + 3, 6);
+	ZXIC_COMM_MEMCPY(pL2Entry->key.dmac_addr, pEntry->p_key + 3, 6);
 
-    zxic_comm_swap(pEntry->p_rst, sizeof(ZXIC_UINT32));
-    ZXIC_COMM_UINT32_GET_BITS(pL2Entry->entry.hit_flag, *(ZXIC_UINT32 *)pEntry->p_rst, 31, 1);
-    ZXIC_COMM_UINT32_GET_BITS(pL2Entry->entry.rsv, *(ZXIC_UINT32 *)pEntry->p_rst, 11, 20);
-    ZXIC_COMM_UINT32_GET_BITS(pL2Entry->entry.vqm_vfid, *(ZXIC_UINT32 *)pEntry->p_rst, 0, 11);
+	zxic_comm_swap(pEntry->p_rst, sizeof(ZXIC_UINT32));
+	ZXIC_COMM_UINT32_GET_BITS(pL2Entry->entry.hit_flag,
+							  *(ZXIC_UINT32 *)pEntry->p_rst, 31, 1);
+	ZXIC_COMM_UINT32_GET_BITS(pL2Entry->entry.rsv,
+							  *(ZXIC_UINT32 *)pEntry->p_rst, 11, 20);
+	ZXIC_COMM_UINT32_GET_BITS(pL2Entry->entry.vqm_vfid,
+							  *(ZXIC_UINT32 *)pEntry->p_rst, 0, 11);
 
-    return DPP_OK;   
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_set_mc_data(ZXIC_VOID *pData, DPP_HASH_ENTRY *pEntry)
 {
-    ZXIC_UINT32 key = 0;
-    ZXIC_UINT32 rst = 0;
+	ZXIC_UINT32 key = 0;
+	ZXIC_UINT32 rst = 0;
+
+	ZXDH_MC_T *mc_table = NULL;
 
-    ZXDH_MC_T *mc_table = NULL;
+	ZXIC_COMM_CHECK_POINT(pData);
+	ZXIC_COMM_CHECK_POINT(pEntry);
+	ZXIC_COMM_CHECK_POINT(pEntry->p_key);
+	ZXIC_COMM_CHECK_POINT(pEntry->p_rst);
 
-    ZXIC_COMM_CHECK_POINT(pData);
-    ZXIC_COMM_CHECK_POINT(pEntry);
-    ZXIC_COMM_CHECK_POINT(pEntry->p_key);
-    ZXIC_COMM_CHECK_POINT(pEntry->p_rst);
+	mc_table = (ZXDH_MC_T *)pData;
 
-    mc_table = (ZXDH_MC_T *)pData;
+	ZXIC_COMM_UINT32_WRITE_BITS(key, mc_table->key.rsv, 18, 14);
+	ZXIC_COMM_UINT32_WRITE_BITS(key, mc_table->key.group_id, 16, 2);
 
-    ZXIC_COMM_UINT32_WRITE_BITS(key, mc_table->key.rsv, 18, 14);
-    ZXIC_COMM_UINT32_WRITE_BITS(key, mc_table->key.group_id, 16, 2);
+	zxic_comm_swap((ZXIC_UINT8 *)&key, sizeof(ZXIC_UINT32));
+	ZXIC_COMM_MEMCPY(pEntry->p_key + 1, &key, sizeof(ZXIC_UINT32));
 
-    zxic_comm_swap((ZXIC_UINT8 *)&key, sizeof(ZXIC_UINT32));
-    ZXIC_COMM_MEMCPY(pEntry->p_key + 1, &key, sizeof(ZXIC_UINT32));
+	ZXIC_COMM_MEMCPY(pEntry->p_key + 3, mc_table->key.mc_mac, 6);
 
-    ZXIC_COMM_MEMCPY(pEntry->p_key + 3, mc_table->key.mc_mac, 6);
+	ZXIC_COMM_UINT32_WRITE_BITS(rst, mc_table->entry.hit_flag, 31, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(rst, mc_table->entry.mc_pf_enable, 30, 1);
+	ZXIC_COMM_UINT32_WRITE_BITS(rst, mc_table->entry.rsv1, 0, 30);
+	zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32));
+	ZXIC_COMM_MEMCPY(pEntry->p_rst, &rst, sizeof(ZXIC_UINT32));
 
-    ZXIC_COMM_UINT32_WRITE_BITS(rst, mc_table->entry.hit_flag, 31, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(rst, mc_table->entry.mc_pf_enable, 30, 1);
-    ZXIC_COMM_UINT32_WRITE_BITS(rst, mc_table->entry.rsv1, 0, 30);
-    zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32));
-    ZXIC_COMM_MEMCPY(pEntry->p_rst, &rst, sizeof(ZXIC_UINT32));
+	ZXIC_COMM_UINT32_WRITE_BITS(rst, mc_table->entry.rsv2, 0, 32);
+	zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32));
+	ZXIC_COMM_MEMCPY(pEntry->p_rst + 4, &rst, sizeof(ZXIC_UINT32));
 
-    ZXIC_COMM_UINT32_WRITE_BITS(rst, mc_table->entry.rsv2, 0, 32);
-    zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32));
-    ZXIC_COMM_MEMCPY(pEntry->p_rst + 4, &rst, sizeof(ZXIC_UINT32));
-    
-    rst = mc_table->entry.mc_bitmap >> 32;
-    zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32));
-    ZXIC_COMM_MEMCPY(pEntry->p_rst + 8, &rst, sizeof(ZXIC_UINT32));
+	rst = mc_table->entry.mc_bitmap >> 32;
+	zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32));
+	ZXIC_COMM_MEMCPY(pEntry->p_rst + 8, &rst, sizeof(ZXIC_UINT32));
 
-    rst = mc_table->entry.mc_bitmap;
-    zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32));
-    ZXIC_COMM_MEMCPY(pEntry->p_rst + 12, &rst, sizeof(ZXIC_UINT32));
+	rst = mc_table->entry.mc_bitmap;
+	zxic_comm_swap((ZXIC_UINT8 *)&rst, sizeof(ZXIC_UINT32));
+	ZXIC_COMM_MEMCPY(pEntry->p_rst + 12, &rst, sizeof(ZXIC_UINT32));
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_apt_get_mc_data(ZXIC_VOID *pData, DPP_HASH_ENTRY *pEntry)
 {
-    ZXIC_UINT32 key = 0;
-    ZXIC_UINT32 rst = 0;
+	ZXIC_UINT32 key = 0;
+	ZXIC_UINT32 rst = 0;
 
-    ZXDH_MC_T *mc_table = NULL;
+	ZXDH_MC_T *mc_table = NULL;
 
-    ZXIC_COMM_CHECK_POINT(pData);
-    ZXIC_COMM_CHECK_POINT(pEntry);
-    ZXIC_COMM_CHECK_POINT(pEntry->p_key);
-    ZXIC_COMM_CHECK_POINT(pEntry->p_rst);
+	ZXIC_COMM_CHECK_POINT(pData);
+	ZXIC_COMM_CHECK_POINT(pEntry);
+	ZXIC_COMM_CHECK_POINT(pEntry->p_key);
+	ZXIC_COMM_CHECK_POINT(pEntry->p_rst);
 
-    mc_table = (ZXDH_MC_T *)pData;
+	mc_table = (ZXDH_MC_T *)pData;
 
-    key = *(ZXIC_UINT32 *)(pEntry->p_key + 1);
-    zxic_comm_swap((ZXIC_UINT8 *)&key, sizeof(ZXIC_UINT32));
-    ZXIC_COMM_UINT32_GET_BITS(mc_table->key.rsv, key, 18, 14);
-    ZXIC_COMM_UINT32_GET_BITS(mc_table->key.group_id, key, 16, 2);
+	key = *(ZXIC_UINT32 *)(pEntry->p_key + 1);
+	zxic_comm_swap((ZXIC_UINT8 *)&key, sizeof(ZXIC_UINT32));
+	ZXIC_COMM_UINT32_GET_BITS(mc_table->key.rsv, key, 18, 14);
+	ZXIC_COMM_UINT32_GET_BITS(mc_table->key.group_id, key, 16, 2);
 
-    ZXIC_COMM_MEMCPY(mc_table->key.mc_mac, pEntry->p_key + 3, 6);
+	ZXIC_COMM_MEMCPY(mc_table->key.mc_mac, pEntry->p_key + 3, 6);
 
-    zxic_comm_swap(pEntry->p_rst, sizeof(ZXIC_UINT32));
-    ZXIC_COMM_UINT32_GET_BITS(mc_table->entry.hit_flag, *(ZXIC_UINT32 *)pEntry->p_rst, 31, 1);
-    ZXIC_COMM_UINT32_GET_BITS(mc_table->entry.mc_pf_enable, *(ZXIC_UINT32 *)pEntry->p_rst, 30, 1);
-    ZXIC_COMM_UINT32_GET_BITS(mc_table->entry.rsv1, *(ZXIC_UINT32 *)pEntry->p_rst, 0, 30);
+	zxic_comm_swap(pEntry->p_rst, sizeof(ZXIC_UINT32));
+	ZXIC_COMM_UINT32_GET_BITS(mc_table->entry.hit_flag,
+							  *(ZXIC_UINT32 *)pEntry->p_rst, 31, 1);
+	ZXIC_COMM_UINT32_GET_BITS(mc_table->entry.mc_pf_enable,
+							  *(ZXIC_UINT32 *)pEntry->p_rst, 30, 1);
+	ZXIC_COMM_UINT32_GET_BITS(mc_table->entry.rsv1,
+							  *(ZXIC_UINT32 *)pEntry->p_rst, 0, 30);
 
-    zxic_comm_swap(pEntry->p_rst + 4, sizeof(ZXIC_UINT32));
-    ZXIC_COMM_UINT32_GET_BITS(mc_table->entry.rsv2, *(ZXIC_UINT32 *)(pEntry->p_rst + 4), 0, 32);
+	zxic_comm_swap(pEntry->p_rst + 4, sizeof(ZXIC_UINT32));
+	ZXIC_COMM_UINT32_GET_BITS(mc_table->entry.rsv2,
+							  *(ZXIC_UINT32 *)(pEntry->p_rst + 4), 0, 32);
 
-    zxic_comm_swap(pEntry->p_rst + 8, sizeof(ZXIC_UINT32));
-    ZXIC_COMM_UINT32_GET_BITS(rst, *(ZXIC_UINT32 *)(pEntry->p_rst + 8), 0, 32);
-    mc_table->entry.mc_bitmap = (((ZXIC_UINT64)rst) << 32);
+	zxic_comm_swap(pEntry->p_rst + 8, sizeof(ZXIC_UINT32));
+	ZXIC_COMM_UINT32_GET_BITS(rst, *(ZXIC_UINT32 *)(pEntry->p_rst + 8), 0, 32);
+	mc_table->entry.mc_bitmap = (((ZXIC_UINT64)rst) << 32);
 
-    zxic_comm_swap(pEntry->p_rst + 12, sizeof(ZXIC_UINT32));
-    ZXIC_COMM_UINT32_GET_BITS(rst, *(ZXIC_UINT32 *)(pEntry->p_rst + 12), 24, 8);
-    mc_table->entry.mc_bitmap |= rst;
+	zxic_comm_swap(pEntry->p_rst + 12, sizeof(ZXIC_UINT32));
+	ZXIC_COMM_UINT32_GET_BITS(rst, *(ZXIC_UINT32 *)(pEntry->p_rst + 12), 24, 8);
+	mc_table->entry.mc_bitmap |= rst;
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-DPP_STATUS dpp_apt_dtb_hash_table_unicast_mac_dump(DPP_DEV_T *dev, 
-                                                   ZXIC_UINT32 queue_id, 
-                                                   ZXIC_UINT32 sdt_no, 
-                                                   ZXDH_L2_ENTRY_T *pHashDataArr, 
-                                                   ZXIC_UINT32 *p_entry_num)
+DPP_STATUS dpp_apt_dtb_hash_table_unicast_mac_dump(
+		DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 sdt_no,
+		ZXDH_L2_ENTRY_T *pHashDataArr, ZXIC_UINT32 *p_entry_num)
 {
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 max_item_num = DTB_DUMP_UNICAST_MAC_DUMP_NUM;
-    ZXIC_UINT32 index = 0; 
-    ZXIC_UINT32 entryNum = 0;
-    ZXIC_UINT8* pDumpData = NULL;
-    ZXIC_UINT8 *pKey = NULL;
-    ZXIC_UINT8 *pRst = NULL;
-
-    ZXIC_UINT32 dma_size  = 0;
-    ZXIC_UINT64 dma_phy_addr = 0;
-    ZXIC_UINT64 dma_vir_addr = 0;
-
-    DPP_HASH_ENTRY *p_dump_hash_entry = NULL;
-    DPP_HASH_ENTRY *p_temp_entry = NULL;
-    DPP_SDTTBL_HASH_T sdt_hash_info = {0};  /*SDT内容*/
-    SE_APT_CALLBACK_T *pAptCallback = NULL;
-    ZXDH_L2_ENTRY_T *p_l2_mac_entry = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(pHashDataArr);
-    ZXIC_COMM_CHECK_POINT(p_entry_num);
-
-    //从sdt_no中获取SDT配置
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
-
-    pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback);
-
-    //分配空间
-    pDumpData = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * sizeof(DPP_HASH_ENTRY));
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(pDumpData);
-    pKey = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_KEY_MAX);
-    ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(pKey, pDumpData);
-    pRst = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_RST_MAX);
-    ZXIC_COMM_CHECK_POINT_MEMORY_FREE2PTR_NO_ASSERT(pRst, pKey, pDumpData);
-
-    ZXIC_COMM_MEMSET(pDumpData, 0x0, max_item_num * sizeof(DPP_HASH_ENTRY));
-    ZXIC_COMM_MEMSET(pKey, 0x0, max_item_num * HASH_KEY_MAX);
-    ZXIC_COMM_MEMSET(pRst, 0x0, max_item_num * HASH_RST_MAX);
-
-    p_dump_hash_entry = (DPP_HASH_ENTRY *)pDumpData;
-    for(index = 0; index < max_item_num; index++)
-    {
-        p_temp_entry = p_dump_hash_entry + index;
-        p_temp_entry->p_key = pKey + index * HASH_KEY_MAX;
-        p_temp_entry->p_rst = pRst + index * HASH_RST_MAX;
-    }
-
-    rc = dtb_sdt_dump_dma_alloc(dev, DTB_SDT_DUMP_SIZE, &dma_phy_addr, &dma_vir_addr);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, "dtb_sdt_dump_dma_alloc", pRst, pKey, pDumpData);
-
-    rc = dpp_dtb_dump_sdt_addr_set(dev, queue_id, sdt_no, dma_phy_addr, dma_vir_addr, DTB_SDT_DUMP_SIZE);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, "dpp_dtb_dump_sdt_addr_set", pRst, pKey, pDumpData);
-
-    rc = dpp_dtb_hash_table_only_zcam_dump(dev, queue_id, sdt_no, pDumpData, &entryNum);
-    
-    dpp_dtb_dump_sdt_addr_get(dev, queue_id, sdt_no, &dma_phy_addr, &dma_vir_addr, &dma_size);
-    dtb_sdt_dump_dma_release(dev, dma_size, dma_phy_addr, dma_vir_addr);
-    dpp_dtb_dump_sdt_addr_clear(dev, queue_id, sdt_no);
-    
-    if(rc != DPP_OK)
-    {
-        ZXIC_COMM_FREE(pKey);
-        ZXIC_COMM_FREE(pRst);
-        ZXIC_COMM_FREE(pDumpData);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_table_only_zcam_dump");
-    }
-
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_hash_table_only_zcam_dump unicast entry_num: %d\n", entryNum);
-
-    for(index = 0; index < entryNum; index++)
-    {
-        p_temp_entry = p_dump_hash_entry + index;
-        p_l2_mac_entry = pHashDataArr + index;
-        // //打印数据
-        dpp_dtb_data_print(p_temp_entry->p_key, DPP_GET_ACTU_KEY_BY_SIZE(sdt_hash_info.key_size) + 1);
-        dpp_dtb_data_print(p_temp_entry->p_rst, 4 * (0x1 << sdt_hash_info.rsp_mode));
-
-        rc = pAptCallback->se_func_info.hashFunc.hash_get_func(p_l2_mac_entry, p_temp_entry);
-        ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE3PTR_NO_ASSERT(DEV_ID(dev), rc, "hash_set_func", pRst, pKey, pDumpData);
-    }
-
-    *p_entry_num = entryNum;
-
-    ZXIC_COMM_FREE(pKey);
-    ZXIC_COMM_FREE(pRst);
-    ZXIC_COMM_FREE(pDumpData);
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 max_item_num = DTB_DUMP_UNICAST_MAC_DUMP_NUM;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 entryNum = 0;
+	ZXIC_UINT8 *pDumpData = NULL;
+	ZXIC_UINT8 *pKey = NULL;
+	ZXIC_UINT8 *pRst = NULL;
+
+	ZXIC_UINT32 dma_size = 0;
+	ZXIC_UINT64 dma_phy_addr = 0;
+	ZXIC_UINT64 dma_vir_addr = 0;
+
+	DPP_HASH_ENTRY *p_dump_hash_entry = NULL;
+	DPP_HASH_ENTRY *p_temp_entry = NULL;
+	DPP_SDTTBL_HASH_T sdt_hash_info = { 0 }; /*SDT内容*/
+	SE_APT_CALLBACK_T *pAptCallback = NULL;
+	ZXDH_L2_ENTRY_T *p_l2_mac_entry = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(pHashDataArr);
+	ZXIC_COMM_CHECK_POINT(p_entry_num);
+
+	//从sdt_no中获取SDT配置
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
+
+	pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback);
+
+	//分配空间
+	pDumpData = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num *
+											   sizeof(DPP_HASH_ENTRY));
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(pDumpData);
+	pKey = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_KEY_MAX);
+	ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(pKey, pDumpData);
+	pRst = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_RST_MAX);
+	ZXIC_COMM_CHECK_POINT_MEMORY_FREE2PTR_NO_ASSERT(pRst, pKey, pDumpData);
+
+	ZXIC_COMM_MEMSET(pDumpData, 0x0, max_item_num * sizeof(DPP_HASH_ENTRY));
+	ZXIC_COMM_MEMSET(pKey, 0x0, max_item_num * HASH_KEY_MAX);
+	ZXIC_COMM_MEMSET(pRst, 0x0, max_item_num * HASH_RST_MAX);
+
+	p_dump_hash_entry = (DPP_HASH_ENTRY *)pDumpData;
+	for (index = 0; index < max_item_num; index++) {
+		p_temp_entry = p_dump_hash_entry + index;
+		p_temp_entry->p_key = pKey + index * HASH_KEY_MAX;
+		p_temp_entry->p_rst = pRst + index * HASH_RST_MAX;
+	}
+
+	rc = dtb_sdt_dump_dma_alloc(dev, DTB_SDT_DUMP_SIZE, &dma_phy_addr,
+								&dma_vir_addr);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, "dtb_sdt_dump_dma_alloc",
+												 pRst, pKey, pDumpData);
+
+	rc = dpp_dtb_dump_sdt_addr_set(dev, queue_id, sdt_no, dma_phy_addr,
+								   dma_vir_addr, DTB_SDT_DUMP_SIZE);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(
+			rc, "dpp_dtb_dump_sdt_addr_set", pRst, pKey, pDumpData);
+
+	rc = dpp_dtb_hash_table_only_zcam_dump(dev, queue_id, sdt_no, pDumpData,
+										   &entryNum);
+
+	dpp_dtb_dump_sdt_addr_get(dev, queue_id, sdt_no, &dma_phy_addr,
+							  &dma_vir_addr, &dma_size);
+	dtb_sdt_dump_dma_release(dev, dma_size, dma_phy_addr, dma_vir_addr);
+	dpp_dtb_dump_sdt_addr_clear(dev, queue_id, sdt_no);
+
+	if (rc != DPP_OK) {
+		ZXIC_COMM_FREE(pKey);
+		ZXIC_COMM_FREE(pRst);
+		ZXIC_COMM_FREE(pDumpData);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_table_only_zcam_dump");
+	}
+
+	ZXIC_COMM_TRACE_INFO(
+			"dpp_dtb_hash_table_only_zcam_dump unicast entry_num: %d\n",
+			entryNum);
+
+	for (index = 0; index < entryNum; index++) {
+		p_temp_entry = p_dump_hash_entry + index;
+		p_l2_mac_entry = pHashDataArr + index;
+		// //打印数据
+		dpp_dtb_data_print(p_temp_entry->p_key,
+						   DPP_GET_ACTU_KEY_BY_SIZE(sdt_hash_info.key_size) +
+								   1);
+		dpp_dtb_data_print(p_temp_entry->p_rst,
+						   4 * (0x1 << sdt_hash_info.rsp_mode));
+
+		rc = pAptCallback->se_func_info.hashFunc.hash_get_func(p_l2_mac_entry,
+															   p_temp_entry);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "hash_set_func");
+	}
+
+	*p_entry_num = entryNum;
+
+	ZXIC_COMM_FREE(pKey);
+	ZXIC_COMM_FREE(pRst);
+	ZXIC_COMM_FREE(pDumpData);
+
+	return DPP_OK;
 }
 
-DPP_STATUS dpp_apt_dtb_hash_table_multicast_mac_dump(DPP_DEV_T *dev, 
-                                            ZXIC_UINT32 queue_id, 
-                                            ZXIC_UINT32 sdt_no, 
-                                            ZXDH_MC_T *pHashDataArr, 
-                                            ZXIC_UINT32 *p_entry_num)
+DPP_STATUS dpp_apt_dtb_hash_table_multicast_mac_dump(DPP_DEV_T *dev,
+													 ZXIC_UINT32 queue_id,
+													 ZXIC_UINT32 sdt_no,
+													 ZXDH_MC_T *pHashDataArr,
+													 ZXIC_UINT32 *p_entry_num)
 {
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 max_item_num = DTB_DUMP_MULTICAST_MAC_DUMP_NUM;
-    ZXIC_UINT32 index = 0; 
-    ZXIC_UINT32 entryNum = 0;
-    ZXIC_UINT8* pDumpData = NULL;
-    ZXIC_UINT8 *pKey = NULL;
-    ZXIC_UINT8 *pRst = NULL;
-
-    ZXIC_UINT32 dma_size  = 0;
-    ZXIC_UINT64 dma_phy_addr = 0;
-    ZXIC_UINT64 dma_vir_addr = 0;
-
-    DPP_HASH_ENTRY *p_dump_hash_entry = NULL;
-    DPP_HASH_ENTRY *p_temp_entry = NULL;
-    DPP_SDTTBL_HASH_T sdt_hash_info = {0};  /*SDT内容*/
-    SE_APT_CALLBACK_T *pAptCallback = NULL;
-    ZXDH_MC_T *p_multicast_mac_data = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(pHashDataArr);
-    ZXIC_COMM_CHECK_POINT(p_entry_num);
-
-    //从sdt_no中获取SDT配置
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
-
-    pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback);
-
-    //分配空间
-    pDumpData = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * sizeof(DPP_HASH_ENTRY));
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(pDumpData);
-    pKey = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_KEY_MAX);
-    ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(pKey, pDumpData);
-    pRst = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_RST_MAX);
-    ZXIC_COMM_CHECK_POINT_MEMORY_FREE2PTR_NO_ASSERT(pRst, pKey, pDumpData);
-
-    ZXIC_COMM_MEMSET(pDumpData, 0x0, max_item_num * sizeof(DPP_HASH_ENTRY));
-    ZXIC_COMM_MEMSET(pKey, 0x0, max_item_num * HASH_KEY_MAX);
-    ZXIC_COMM_MEMSET(pRst, 0x0, max_item_num * HASH_RST_MAX);
-
-    p_dump_hash_entry = (DPP_HASH_ENTRY *)pDumpData;
-    for(index = 0; index < max_item_num; index++)
-    {
-        p_temp_entry = p_dump_hash_entry + index;
-        p_temp_entry->p_key = pKey + index * HASH_KEY_MAX;
-        p_temp_entry->p_rst = pRst + index * HASH_RST_MAX;
-    }
-
-    rc = dtb_sdt_dump_dma_alloc(dev, DTB_SDT_DUMP_SIZE, &dma_phy_addr, &dma_vir_addr);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, "dtb_sdt_dump_dma_alloc", pRst, pKey, pDumpData);
-
-    rc = dpp_dtb_dump_sdt_addr_set(dev, queue_id, sdt_no, dma_phy_addr, dma_vir_addr, DTB_SDT_DUMP_SIZE);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, "dpp_dtb_dump_sdt_addr_set", pRst, pKey, pDumpData);
-
-    rc = dpp_dtb_hash_table_only_zcam_dump(dev, queue_id, sdt_no, pDumpData, &entryNum);
-    
-    dpp_dtb_dump_sdt_addr_get(dev, queue_id, sdt_no, &dma_phy_addr, &dma_vir_addr, &dma_size);
-    dtb_sdt_dump_dma_release(dev, dma_size, dma_phy_addr, dma_vir_addr);
-    dpp_dtb_dump_sdt_addr_clear(dev, queue_id, sdt_no);
-    
-    if(rc != DPP_OK)
-    {
-        ZXIC_COMM_FREE(pKey);
-        ZXIC_COMM_FREE(pRst);
-        ZXIC_COMM_FREE(pDumpData);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_table_only_zcam_dump");
-    }
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_hash_table_only_zcam_dump multicast entry_num: %d\n", entryNum);
-
-    for(index = 0; index < entryNum; index++)
-    {
-        p_temp_entry = p_dump_hash_entry + index;
-        p_multicast_mac_data = pHashDataArr + index;
-        // //打印数据
-        dpp_dtb_data_print(p_temp_entry->p_key, DPP_GET_ACTU_KEY_BY_SIZE(sdt_hash_info.key_size) + 1);
-        dpp_dtb_data_print(p_temp_entry->p_rst, 4 * (0x1 << sdt_hash_info.rsp_mode));
-
-        rc = pAptCallback->se_func_info.hashFunc.hash_get_func(p_multicast_mac_data, p_temp_entry);
-        ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE3PTR_NO_ASSERT(DEV_ID(dev), rc, "hash_get_func", pRst, pKey, pDumpData);
-    }
-
-    *p_entry_num = entryNum;
-
-    ZXIC_COMM_FREE(pKey);
-    ZXIC_COMM_FREE(pRst);
-    ZXIC_COMM_FREE(pDumpData);
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 max_item_num = DTB_DUMP_MULTICAST_MAC_DUMP_NUM;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 entryNum = 0;
+	ZXIC_UINT8 *pDumpData = NULL;
+	ZXIC_UINT8 *pKey = NULL;
+	ZXIC_UINT8 *pRst = NULL;
+
+	ZXIC_UINT32 dma_size = 0;
+	ZXIC_UINT64 dma_phy_addr = 0;
+	ZXIC_UINT64 dma_vir_addr = 0;
+
+	DPP_HASH_ENTRY *p_dump_hash_entry = NULL;
+	DPP_HASH_ENTRY *p_temp_entry = NULL;
+	DPP_SDTTBL_HASH_T sdt_hash_info = { 0 }; /*SDT内容*/
+	SE_APT_CALLBACK_T *pAptCallback = NULL;
+	ZXDH_MC_T *p_multicast_mac_data = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(pHashDataArr);
+	ZXIC_COMM_CHECK_POINT(p_entry_num);
+
+	//从sdt_no中获取SDT配置
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
+
+	pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback);
+
+	//分配空间
+	pDumpData = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num *
+											   sizeof(DPP_HASH_ENTRY));
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(pDumpData);
+	pKey = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_KEY_MAX);
+	ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(pKey, pDumpData);
+	pRst = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_RST_MAX);
+	ZXIC_COMM_CHECK_POINT_MEMORY_FREE2PTR_NO_ASSERT(pRst, pKey, pDumpData);
+
+	ZXIC_COMM_MEMSET(pDumpData, 0x0, max_item_num * sizeof(DPP_HASH_ENTRY));
+	ZXIC_COMM_MEMSET(pKey, 0x0, max_item_num * HASH_KEY_MAX);
+	ZXIC_COMM_MEMSET(pRst, 0x0, max_item_num * HASH_RST_MAX);
+
+	p_dump_hash_entry = (DPP_HASH_ENTRY *)pDumpData;
+	for (index = 0; index < max_item_num; index++) {
+		p_temp_entry = p_dump_hash_entry + index;
+		p_temp_entry->p_key = pKey + index * HASH_KEY_MAX;
+		p_temp_entry->p_rst = pRst + index * HASH_RST_MAX;
+	}
+
+	rc = dtb_sdt_dump_dma_alloc(dev, DTB_SDT_DUMP_SIZE, &dma_phy_addr,
+								&dma_vir_addr);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, "dtb_sdt_dump_dma_alloc",
+												 pRst, pKey, pDumpData);
+
+	rc = dpp_dtb_dump_sdt_addr_set(dev, queue_id, sdt_no, dma_phy_addr,
+								   dma_vir_addr, DTB_SDT_DUMP_SIZE);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(
+			rc, "dpp_dtb_dump_sdt_addr_set", pRst, pKey, pDumpData);
+
+	rc = dpp_dtb_hash_table_only_zcam_dump(dev, queue_id, sdt_no, pDumpData,
+										   &entryNum);
+
+	dpp_dtb_dump_sdt_addr_get(dev, queue_id, sdt_no, &dma_phy_addr,
+							  &dma_vir_addr, &dma_size);
+	dtb_sdt_dump_dma_release(dev, dma_size, dma_phy_addr, dma_vir_addr);
+	dpp_dtb_dump_sdt_addr_clear(dev, queue_id, sdt_no);
+
+	if (rc != DPP_OK) {
+		ZXIC_COMM_FREE(pKey);
+		ZXIC_COMM_FREE(pRst);
+		ZXIC_COMM_FREE(pDumpData);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_table_only_zcam_dump");
+	}
+	ZXIC_COMM_TRACE_INFO(
+			"dpp_dtb_hash_table_only_zcam_dump multicast entry_num: %d\n",
+			entryNum);
+
+	for (index = 0; index < entryNum; index++) {
+		p_temp_entry = p_dump_hash_entry + index;
+		p_multicast_mac_data = pHashDataArr + index;
+		// //打印数据
+		dpp_dtb_data_print(p_temp_entry->p_key,
+						   DPP_GET_ACTU_KEY_BY_SIZE(sdt_hash_info.key_size) +
+								   1);
+		dpp_dtb_data_print(p_temp_entry->p_rst,
+						   4 * (0x1 << sdt_hash_info.rsp_mode));
+
+		rc = pAptCallback->se_func_info.hashFunc.hash_get_func(
+				p_multicast_mac_data, p_temp_entry);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "hash_set_func");
+	}
+
+	*p_entry_num = entryNum;
+
+	ZXIC_COMM_FREE(pKey);
+	ZXIC_COMM_FREE(pRst);
+	ZXIC_COMM_FREE(pDumpData);
+
+	return DPP_OK;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_init.c b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_init.c
index af3057df7b621340bdc47b2e51d8988ffcadb7e2..1bb2854a6678c6d3fd909d712bbcbc9dd5f1aef5 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_init.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/driver/source/dpp_drv_init.c
@@ -7,109 +7,110 @@
 #include "dpp_hash.h"
 #include "dpp_apt_se.h"
 
-#define DPP_FLOW_INIT_START       ((ZXIC_UINT32)(0))
-#define DPP_FLOW_INIT_SUCCESS     ((ZXIC_UINT32)(1))
-
-#define DPP_FLOW_INIT_STATUS_CHECK()\
-    do{\
-        if(DPP_FLOW_INIT_SUCCESS != dpp_flow_init_status)\
-        {\
-           return DPP_OK;\
-        }\
-    }while(0)
-
-#define DPP_FLOW_INIT_SUCCESS_STATUS_CHECK()\
-    do{\
-        if(DPP_FLOW_INIT_SUCCESS == dpp_flow_init_status)\
-        {\
-           return DPP_OK;\
-        }\
-    }while(0)
+#define DPP_FLOW_INIT_START ((ZXIC_UINT32)(0))
+#define DPP_FLOW_INIT_SUCCESS ((ZXIC_UINT32)(1))
+
+#define DPP_FLOW_INIT_STATUS_CHECK()                         \
+	do {                                                     \
+		if (DPP_FLOW_INIT_SUCCESS != dpp_flow_init_status) { \
+			return DPP_OK;                                   \
+		}                                                    \
+	} while (0)
+
+#define DPP_FLOW_INIT_SUCCESS_STATUS_CHECK()                 \
+	do {                                                     \
+		if (DPP_FLOW_INIT_SUCCESS == dpp_flow_init_status) { \
+			return DPP_OK;                                   \
+		}                                                    \
+	} while (0)
 
 ZXIC_UINT32 dpp_flow_init_status = DPP_FLOW_INIT_START;
 
 DPP_STATUS dpp_flow_init_status_set(ZXIC_UINT32 status)
 {
-    ZXIC_COMM_CHECK_INDEX(status, DPP_FLOW_INIT_START, DPP_FLOW_INIT_SUCCESS);
+	ZXIC_COMM_CHECK_INDEX(status, DPP_FLOW_INIT_START, DPP_FLOW_INIT_SUCCESS);
 
-    dpp_flow_init_status = status;
+	dpp_flow_init_status = status;
 
-    return DPP_OK; 
+	return DPP_OK;
 }
 
 DPP_STATUS dpp_flow_init(DPP_DEV_T *dev)
 {
 	DPP_STATUS rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    DPP_FLOW_INIT_SUCCESS_STATUS_CHECK();
+	ZXIC_COMM_CHECK_POINT(dev);
+	DPP_FLOW_INIT_SUCCESS_STATUS_CHECK();
 
-    ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__);
+	ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__);
 
-    // hash init
-    rc = dpp_apt_hash_global_res_init(dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_hash_global_res_init");
+	// hash init
+	rc = dpp_apt_hash_global_res_init(dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_hash_global_res_init");
 
-    rc = dpp_apt_hash_func_res_init(DEV_ID(dev), g_hashTable.func_num, g_hashTable.func);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_hash_func_res_init");
+	rc = dpp_apt_hash_func_res_init(DEV_ID(dev), g_hashTable.func_num,
+									g_hashTable.func);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_hash_func_res_init");
 
-    rc = dpp_apt_hash_bulk_res_init(DEV_ID(dev), g_hashTable.bulk_num, g_hashTable.bulk);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_hash_bulk_res_init");
+	rc = dpp_apt_hash_bulk_res_init(DEV_ID(dev), g_hashTable.bulk_num,
+									g_hashTable.bulk);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_hash_bulk_res_init");
 
-    // tbl-res must be initialized after fun-res and buld-res
-    rc = dpp_apt_hash_tbl_res_init(dev, g_hashTable.ser_num, g_hashTable.ser);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_hash_tbl_res_init");
+	// tbl-res must be initialized after fun-res and buld-res
+	rc = dpp_apt_hash_tbl_res_init(dev, g_hashTable.ser_num, g_hashTable.ser);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_hash_tbl_res_init");
 
-    // eram init
-    rc = dpp_apt_eram_res_init(dev, g_eRamTable.tbl_num, g_eRamTable.eram);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_eram_res_init");
+	// eram init
+	rc = dpp_apt_eram_res_init(dev, g_eRamTable.tbl_num, g_eRamTable.eram);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_eram_res_init");
 
-    // init acl
-    rc = dpp_apt_acl_res_init(dev, g_aclTable.tbl_num, g_aclTable.acl);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_acl_res_init");
+	// init acl
+	rc = dpp_apt_acl_res_init(dev, g_aclTable.tbl_num, g_aclTable.acl);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_acl_res_init");
 
 #ifdef DPP_FLOW_HW_INIT
-    rc = dpp_stat_ppu_eram_baddr_set(dev, ZXDH_STAT_PPU_ERAM_BAADDR);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_ppu_eram_baddr_set");
+	rc = dpp_stat_ppu_eram_baddr_set(dev, ZXDH_STAT_PPU_ERAM_BAADDR);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_ppu_eram_baddr_set");
 
-    rc = dpp_stat_ppu_eram_depth_set(dev, (ZXDH_STAT_PPU_ERAM_DEPTH / 2)); //表项深度以128bit为单位
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_ppu_eram_depth_set");
+	rc = dpp_stat_ppu_eram_depth_set(
+			dev, (ZXDH_STAT_PPU_ERAM_DEPTH / 2)); //表项深度以128bit为单位
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_ppu_eram_depth_set");
 #endif
 
-    rc = dpp_flow_init_status_set(DPP_FLOW_INIT_SUCCESS);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_flow_init_status_set");
+	rc = dpp_flow_init_status_set(DPP_FLOW_INIT_SUCCESS);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_flow_init_status_set");
 
-    ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__);
+	ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 DPP_STATUS dpp_flow_uninit(ZXIC_UINT32 dev_id)
 {
-    DPP_STATUS rc = DPP_OK;
+	DPP_STATUS rc = DPP_OK;
 
-    DPP_FLOW_INIT_STATUS_CHECK();
+	DPP_FLOW_INIT_STATUS_CHECK();
 
-    ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__);
+	ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__);
 
-    rc = dpp_hash_soft_uninstall(dev_id);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_hash_soft_uninstall");
+	rc = dpp_hash_soft_uninstall(dev_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_hash_soft_uninstall");
 
-    rc = dpp_acl_res_destroy(dev_id);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_acl_res_destroy");
+	rc = dpp_acl_res_destroy(dev_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_acl_res_destroy");
 
-    ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__);
+	ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 DPP_STATUS dpp_flow_data_all_flush(DPP_DEV_T *dev, ZXIC_UINT32 queue_id)
 {
-    DPP_STATUS rc = DPP_OK;
+	DPP_STATUS rc = DPP_OK;
 
-    rc = dpp_apt_hash_func_flush_hardware_all(dev, g_hashTable.func_num, g_hashTable.func, queue_id);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_apt_hash_func_flush_hardware");
+	rc = dpp_apt_hash_func_flush_hardware_all(dev, g_hashTable.func_num,
+											  g_hashTable.func, queue_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_apt_hash_func_flush_hardware");
 
-    return rc;
+	return rc;
 }
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/fc/include/dpp_drv_fc.h b/src/net/drivers/net/ethernet/dinghai/en_np/fc/include/dpp_drv_fc.h
index fd156074905db1af01a9b77344c41905e94661c1..3f72477df70f137fd5141cf7b137fb76a7006e99 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/fc/include/dpp_drv_fc.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/fc/include/dpp_drv_fc.h
@@ -1,65 +1,61 @@
-#ifndef  _DPP_DRV_FC_H_
-#define  _DPP_DRV_FC_H_
-
-#include "zxic_common.h"
-#include "dpp_pbu.h"
-#include "dpp_pbu_api.h"
-#include "dpp_drv_qos.h"
-
-/***********************************************************/
-/**对外接口  配置基于vport的端口指针阈值
-* @param   vport_id--vport号
-* @param   port_id   端口号
-* @param   p_para   端口阈值
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_port_th_set(DPP_PF_INFO_T* pf_info,
-                           ZXIC_UINT32 port_id,
-                           DPP_PBU_PORT_TH_PARA_T *p_para);
-
-/***********************************************************/
-/** 读取端口的阈值
-* @param   vport_id--vport号
-* @param   port_id   端口号
-* @param   p_para   端口阈值
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_port_th_get(DPP_PF_INFO_T* pf_info,
-                           ZXIC_UINT32 port_id,
-                           DPP_PBU_PORT_TH_PARA_T *p_para);
-
-/***********************************************************/
-/**对外接口  配置基于vport的端口指定端口按cos优先级起pfc流控的优先级流控指针阈值
-* @param   vport_id--vport号
-* @param   port_id   端口号
-* @param   p_para   cos阈值，要求高优先级的阈值不小于低优先级的阈值
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_port_cos_th_set(DPP_PF_INFO_T* pf_info,
-                               ZXIC_UINT32 port_id,
-                               DPP_PBU_PORT_COS_TH_PARA_T *p_para);
-
-/***********************************************************/
-/** 读取指定端口中各cos的优先级流控指针阈值，仅对lif0的48个通道有效
-* @param   vport_id--vport号
-* @param   port_id   端口号
-* @param   p_para   cos阈值，要求高优先级的阈值不小于低优先级的阈值
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_port_cos_th_get(DPP_PF_INFO_T* pf_info,
-                                   ZXIC_UINT32 port_id,
-                                   DPP_PBU_PORT_COS_TH_PARA_T *p_para);
-
-#endif
+#ifndef _DPP_DRV_FC_H_
+#define _DPP_DRV_FC_H_
+
+#include "zxic_common.h"
+#include "dpp_pbu.h"
+#include "dpp_pbu_api.h"
+#include "dpp_drv_qos.h"
+
+/***********************************************************/
+/**对外接口  配置基于vport的端口指针阈值
+ * @param   vport_id--vport号
+ * @param   port_id   端口号
+ * @param   p_para   端口阈值
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_port_th_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 port_id,
+						   DPP_PBU_PORT_TH_PARA_T *p_para);
+
+/***********************************************************/
+/** 读取端口的阈值
+ * @param   vport_id--vport号
+ * @param   port_id   端口号
+ * @param   p_para   端口阈值
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_port_th_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 port_id,
+						   DPP_PBU_PORT_TH_PARA_T *p_para);
+
+/***********************************************************/
+/**对外接口  配置基于vport的端口指定端口按cos优先级起pfc流控的优先级流控指针阈值
+ * @param   vport_id--vport号
+ * @param   port_id   端口号
+ * @param   p_para   cos阈值，要求高优先级的阈值不小于低优先级的阈值
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_port_cos_th_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 port_id,
+							   DPP_PBU_PORT_COS_TH_PARA_T *p_para);
+
+/***********************************************************/
+/** 读取指定端口中各cos的优先级流控指针阈值，仅对lif0的48个通道有效
+ * @param   vport_id--vport号
+ * @param   port_id   端口号
+ * @param   p_para   cos阈值，要求高优先级的阈值不小于低优先级的阈值
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_port_cos_th_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 port_id,
+							   DPP_PBU_PORT_COS_TH_PARA_T *p_para);
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/fc/source/dpp_drv_fc.c b/src/net/drivers/net/ethernet/dinghai/en_np/fc/source/dpp_drv_fc.c
old mode 100755
new mode 100644
index 31b10b3e421d42e1f428b7996e12d198e43afb28..13049048c415ca24ddd6baa875249f48888a3f35
--- a/src/net/drivers/net/ethernet/dinghai/en_np/fc/source/dpp_drv_fc.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/fc/source/dpp_drv_fc.c
@@ -1,138 +1,137 @@
-#include "dpp_drv_fc.h"
-
-/***********************************************************/
-/**对外接口  配置基于vport的端口指针阈值
-* @param   vport_id--vport号
-* @param   port_id   端口号
-* @param   p_para   端口阈值
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_port_th_set(DPP_PF_INFO_T* pf_info,
-                           ZXIC_UINT32 port_id,
-                           DPP_PBU_PORT_TH_PARA_T *p_para)
-{
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
-
-    ZXIC_COMM_CHECK_POINT(pf_info);
-
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-
-    ret = dpp_pbu_port_th_set(&dev, port_id, p_para);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_pbu_port_th_set");
-
-    return ret;
-}
-EXPORT_SYMBOL(dpp_port_th_set);
-
-/***********************************************************/
-/** 读取端口的阈值
-* @param   vport_id--vport号
-* @param   port_id   端口号
-* @param   p_para   端口阈值
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_port_th_get(DPP_PF_INFO_T* pf_info,
-                           ZXIC_UINT32 port_id,
-                           DPP_PBU_PORT_TH_PARA_T *p_para)
-{
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
-
-    ZXIC_COMM_CHECK_POINT(pf_info);
-
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-
-    ret = dpp_pbu_port_th_get(&dev, port_id, p_para);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_pbu_port_th_get");
-
-    return ret;
-}
-EXPORT_SYMBOL(dpp_port_th_get);
-
-/***********************************************************/
-/**对外接口  配置基于vport的端口指定端口按cos优先级起pfc流控的优先级流控指针阈值
-* @param   vport_id--vport号
-* @param   port_id   端口号
-* @param   p_para   cos阈值，要求高优先级的阈值不小于低优先级的阈值
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_port_cos_th_set(DPP_PF_INFO_T* pf_info,
-                               ZXIC_UINT32 port_id,
-                               DPP_PBU_PORT_COS_TH_PARA_T *p_para)
-{
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
-
-    ZXIC_COMM_CHECK_POINT(pf_info);
-
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-
-    ret = dpp_pbu_port_cos_th_set(&dev, port_id, p_para);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_pbu_port_cos_th_set");
-
-    return ret;
-}
-EXPORT_SYMBOL(dpp_port_cos_th_set);
-
-/***********************************************************/
-/** 读取指定端口中各cos的优先级流控指针阈值，仅对lif0的48个通道有效
-* @param   vport_id--vport号
-* @param   port_id   端口号
-* @param   p_para   cos阈值，要求高优先级的阈值不小于低优先级的阈值
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_port_cos_th_get(DPP_PF_INFO_T* pf_info,
-                               ZXIC_UINT32 port_id,
-                               DPP_PBU_PORT_COS_TH_PARA_T *p_para)
-{
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
-
-    ZXIC_COMM_CHECK_POINT(pf_info);
-
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-
-    ret = dpp_pbu_port_cos_th_get(&dev, port_id, p_para);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_pbu_port_cos_th_get");
-
-    return ret;
-}
-EXPORT_SYMBOL(dpp_port_cos_th_get);
-
+#include "dpp_drv_fc.h"
+
+/***********************************************************/
+/**对外接口  配置基于vport的端口指针阈值
+ * @param   vport_id--vport号
+ * @param   port_id   端口号
+ * @param   p_para   端口阈值
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_port_th_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 port_id,
+						   DPP_PBU_PORT_TH_PARA_T *p_para)
+{
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(pf_info);
+
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
+
+	ret = dpp_pbu_port_th_set(&dev, port_id, p_para);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_pbu_port_th_set");
+
+	return ret;
+}
+EXPORT_SYMBOL(dpp_port_th_set);
+
+/***********************************************************/
+/** 读取端口的阈值
+ * @param   vport_id--vport号
+ * @param   port_id   端口号
+ * @param   p_para   端口阈值
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_port_th_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 port_id,
+						   DPP_PBU_PORT_TH_PARA_T *p_para)
+{
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(pf_info);
+
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
+
+	ret = dpp_pbu_port_th_get(&dev, port_id, p_para);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_pbu_port_th_get");
+
+	return ret;
+}
+EXPORT_SYMBOL(dpp_port_th_get);
+
+/***********************************************************/
+/**对外接口  配置基于vport的端口指定端口按cos优先级起pfc流控的优先级流控指针阈值
+ * @param   vport_id--vport号
+ * @param   port_id   端口号
+ * @param   p_para   cos阈值，要求高优先级的阈值不小于低优先级的阈值
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_port_cos_th_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 port_id,
+							   DPP_PBU_PORT_COS_TH_PARA_T *p_para)
+{
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(pf_info);
+
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
+
+	ret = dpp_pbu_port_cos_th_set(&dev, port_id, p_para);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_pbu_port_cos_th_set");
+
+	return ret;
+}
+EXPORT_SYMBOL(dpp_port_cos_th_set);
+
+/***********************************************************/
+/** 读取指定端口中各cos的优先级流控指针阈值，仅对lif0的48个通道有效
+ * @param   vport_id--vport号
+ * @param   port_id   端口号
+ * @param   p_para   cos阈值，要求高优先级的阈值不小于低优先级的阈值
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_port_cos_th_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 port_id,
+							   DPP_PBU_PORT_COS_TH_PARA_T *p_para)
+{
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(pf_info);
+
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
+
+	ret = dpp_pbu_port_cos_th_get(&dev, port_id, p_para);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_pbu_port_cos_th_get");
+
+	return ret;
+}
+EXPORT_SYMBOL(dpp_port_cos_th_get);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/init/include/dpp_np_init.h b/src/net/drivers/net/ethernet/dinghai/en_np/init/include/dpp_np_init.h
index 25f7eec4fffcd49809c99e0e001768e531e71f57..815f19ec64784f6c0bf78e4bb30c700065c4d888 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/init/include/dpp_np_init.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/init/include/dpp_np_init.h
@@ -1,11 +1,11 @@
-#ifndef _DPP_NP_INIT_H_
-#define _DPP_NP_INIT_H_
-
-#include <linux/pci.h>
-#include "zxic_common.h"
-#include "dpp_dev.h"
-
-ZXIC_UINT32 dpp_vport_register(DPP_PF_INFO_T* pf_info, struct pci_dev *p_dev);
-ZXIC_UINT32 dpp_vport_unregister(DPP_PF_INFO_T* pf_info);
-
-#endif
+#ifndef _DPP_NP_INIT_H_
+#define _DPP_MP_INIT_H_
+
+#include <linux/pci.h>
+#include "zxic_common.h"
+#include "dpp_dev.h"
+
+ZXIC_UINT32 dpp_vport_register(DPP_PF_INFO_T *pf_info, struct pci_dev *p_dev);
+ZXIC_UINT32 dpp_vport_unregister(DPP_PF_INFO_T *pf_info);
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/init/source/dpp_np_init.c b/src/net/drivers/net/ethernet/dinghai/en_np/init/source/dpp_np_init.c
index 4c47e5fe350d29bc67d600567a4918cc5a4395cc..170c074732e95ff53c7846cf63e37496d4706f7b 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/init/source/dpp_np_init.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/init/source/dpp_np_init.c
@@ -14,153 +14,153 @@
 #include "dpp_hash.h"
 #include "dpp_sdt_mgr.h"
 
-ZXIC_UINT32 dpp_vport_register(DPP_PF_INFO_T* pf_info, struct pci_dev *p_dev)
+ZXIC_UINT32 dpp_vport_register(DPP_PF_INFO_T *pf_info, struct pci_dev *p_dev)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(p_dev);
-    ZXIC_COMM_CHECK_INDEX_EQUAL_RETURN_OK(IS_PF(pf_info->vport), 0);
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(p_dev);
+	ZXIC_COMM_CHECK_INDEX_EQUAL_RETURN_OK(IS_PF(pf_info->vport), 0);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x register start.\n", __FUNCTION__,
-                                                   pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x register start.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport);
 
-    rc = dpp_dev_pcie_channel_add(dev_id, pf_info, p_dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_pcie_channel_add");
+	rc = dpp_dev_pcie_channel_add(dev_id, pf_info, p_dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_pcie_channel_add");
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_init(&dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_init");
+	rc = dpp_dtb_init(&dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_init");
 
 #ifdef DPP_FLOW_HW_INIT
-    rc = dpp_flow_init(&dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_flow_init");
+	rc = dpp_flow_init(&dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_flow_init");
 #endif
 
-    rc = dpp_apt_dtb_res_init(&dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_res_init");
+	rc = dpp_apt_dtb_res_init(&dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_res_init");
 
-    rc = dpp_vport_mgr_init(pf_info);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mgr_init");
+	rc = dpp_vport_mgr_init(pf_info);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mgr_init");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x register success.\n", __FUNCTION__,
-                                                     pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x register success.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_register);
 
-ZXIC_UINT32 dpp_vport_unregister(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_vport_unregister(DPP_PF_INFO_T *pf_info)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_INDEX_EQUAL_RETURN_OK(IS_PF(pf_info->vport), 0);
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_INDEX_EQUAL_RETURN_OK(IS_PF(pf_info->vport), 0);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x unregister start.\n", __FUNCTION__,
-                                                     pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x unregister start.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_dtb_queue_release(&dev, "pf", queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_release");
+	rc = dpp_dtb_queue_release(&dev, "pf", queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_release");
 
-    rc = dpp_dtb_queue_dma_mem_release(&dev, queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_dma_mem_release");
+	rc = dpp_dtb_queue_dma_mem_release(&dev, queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_dma_mem_release");
 
-    rc = dpp_dev_pcie_channel_del(dev_id, pf_info);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_pcie_channel_del");
+	rc = dpp_dev_pcie_channel_del(dev_id, pf_info);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_pcie_channel_del");
 
-    rc = dpp_vport_mgr_release(pf_info);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mgr_release");
+	rc = dpp_vport_mgr_release(pf_info);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mgr_release");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x unregister success.\n", __FUNCTION__,
-                                                       pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x unregister success.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_unregister);
 
 static DPP_SYS_INIT_CTRL_T g_np_sys_init = {
-    .device_type = DPP_DEV_TYPE_CHIP,
-    .flags       = DPP_DEV_ACCESS_TYPE_PCIE << 0,
+	.device_type = DPP_DEV_TYPE_CHIP,
+	.flags = DPP_DEV_ACCESS_TYPE_PCIE << 0,
 };
 
 static int __init dpp_np_init(void)
 {
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
 #ifndef DPP_FLOW_HW_INIT
-    DPP_DEV_T dev = {dev_id, {0, 0, 0, 0, 0}};
+	DPP_DEV_T dev = { dev_id, { 0, 0, 0, 0, 0 } };
 #endif
 
-    ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__);
+	ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__);
 
-    rc = dpp_init(dev_id, &g_np_sys_init);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_init");
+	rc = dpp_init(dev_id, &g_np_sys_init);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_init");
 
 #ifndef DPP_FLOW_HW_INIT
-    rc = dpp_flow_init(&dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_flow_init");
+	rc = dpp_flow_init(&dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_flow_init");
 #endif
 
-    rc = dpp_agent_channel_init();
-    ZXIC_COMM_CHECK_RC(rc, "dpp_agent_channel_init");
+	rc = dpp_agent_channel_init();
+	ZXIC_COMM_CHECK_RC(rc, "dpp_agent_channel_init");
 
-    rc = dpp_netlink_init();
-    ZXIC_COMM_CHECK_RC(rc, "dpp_netlink_init");
+	rc = dpp_netlink_init();
+	ZXIC_COMM_CHECK_RC(rc, "dpp_netlink_init");
 
-    rc = dpp_cmd_init();
-    ZXIC_COMM_CHECK_RC(rc, "dpp_cmd_init");
+	rc = dpp_cmd_init();
+	ZXIC_COMM_CHECK_RC(rc, "dpp_cmd_init");
 
-    ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__);
+	ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 dpp_np_online_uninstall(void)
 {
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    rc = dpp_flow_uninit(dev_id);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_flow_uninit");
+	rc = dpp_flow_uninit(dev_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_flow_uninit");
 
-    rc = dpp_dtb_mgr_destory_all();
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_mgr_destory");
+	rc = dpp_dtb_mgr_destory_all();
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_mgr_destory");
 
-    rc = dpp_sdt_mgr_destroy(dev_id);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_sdt_mgr_destroy");
+	rc = dpp_sdt_mgr_destroy(dev_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_sdt_mgr_destroy");
 
-    rc = dpp_dev_del(dev_id);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dev_del");
+	rc = dpp_dev_del(dev_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dev_del");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 static void __exit dpp_np_exit(void)
 {
-    ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__);
+	ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__);
 
-    dpp_netlink_exit();
-    dpp_agent_channel_exit();
-    dpp_np_online_uninstall();
+	dpp_netlink_exit();
+	dpp_agent_channel_exit();
+	dpp_np_online_uninstall();
 
-    ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__);
+	ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__);
 }
 
 module_init(dpp_np_init);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/netlink/source/dpp_netlink.c b/src/net/drivers/net/ethernet/dinghai/en_np/netlink/source/dpp_netlink.c
index 78f77e44f0ce2e279eb44fdd8b89737fc13563a5..3a60695d2d48fd9a903a976958b03ab488de7336 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/netlink/source/dpp_netlink.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/netlink/source/dpp_netlink.c
@@ -12,194 +12,185 @@
 #include <asm/types.h>
 #include "dpp_netlink.h"
 
-#define DPP_NETLINK_PROTOCOL    ((ZXIC_UINT32)(29))
-#define DPP_NETLINK_GROUP_ID    ((ZXIC_UINT32)(1))
-#define DPP_NETLINK_MAX_PROC    ((ZXIC_UINT32)(2048))
+#define DPP_NETLINK_PROTOCOL ((ZXIC_UINT32)(29))
+#define DPP_NETLINK_GROUP_ID ((ZXIC_UINT32)(1))
+#define DPP_NETLINK_MAX_PROC ((ZXIC_UINT32)(2048))
 
-typedef DPP_STATUS (*DPP_NETLINK_PROC_PTR)(ZXIC_VOID *msg_body, ZXIC_UINT32 msg_len, ZXIC_VOID **resp, ZXIC_UINT32 *reps_len);
+typedef DPP_STATUS (*DPP_NETLINK_PROC_PTR)(ZXIC_VOID *msg_body,
+										   ZXIC_UINT32 msg_len,
+										   ZXIC_VOID **resp,
+										   ZXIC_UINT32 *reps_len);
 
 static struct sock *dpp_netlink_sk;
-static DPP_NETLINK_PROC_PTR dpp_netlink_proc_ptr[DPP_NETLINK_MAX_PROC] = {0};
+static DPP_NETLINK_PROC_PTR dpp_netlink_proc_ptr[DPP_NETLINK_MAX_PROC] = { 0 };
 
 static DPP_STATUS dpp_netlink_send_ack_msg(ZXIC_VOID *data, ZXIC_UINT32 len)
 {
-    struct sk_buff *skb  = NULL;
-    struct nlmsghdr *nlh = NULL;
-    ZXIC_SINT32 rtn = DPP_OK;
-
-    if (data == NULL)
-    {
-        ZXIC_COMM_PRINT("%s: data invalid.\n", __FUNCTION__);
-        return DPP_ERR;
-    }
-
-    skb = alloc_skb(NLMSG_SPACE(len), GFP_KERNEL);
-    if (skb == NULL)
-    {
-        ZXIC_COMM_PRINT("%s: alloc_skb failed.\n", __FUNCTION__);
-        return DPP_ERR;
-    }
-
-    nlh = nlmsg_put(skb, 0, 0, 0, len, 0);
-    if (nlh == NULL)
-    {
-        ZXIC_COMM_PRINT("%s: nlmsg_put failed.\n", __FUNCTION__);
-        return DPP_ERR;
-    }
-
-    nlh->nlmsg_flags = NLM_F_ACK;
-    memcpy(NLMSG_DATA(nlh), data, len);
-
-    rtn = nlmsg_multicast(dpp_netlink_sk, skb, 0, DPP_NETLINK_GROUP_ID, 0);
-    if (rtn < 0)
-    {
-        ZXIC_COMM_PRINT("%s: nlmsg_multicast failed, rtn %d.\n", __FUNCTION__, rtn);
-        return DPP_ERR;
-    }
-    return DPP_OK;
+	struct sk_buff *skb = NULL;
+	struct nlmsghdr *nlh = NULL;
+	ZXIC_UINT32 rtn = DPP_OK;
+
+	if (data == NULL) {
+		ZXIC_COMM_PRINT("%s: data invalid.\n", __FUNCTION__);
+		return DPP_ERR;
+	}
+
+	skb = alloc_skb(NLMSG_SPACE(len), GFP_KERNEL);
+	if (skb == NULL) {
+		ZXIC_COMM_PRINT("%s: alloc_skb failed.\n", __FUNCTION__);
+		return DPP_ERR;
+	}
+
+	nlh = nlmsg_put(skb, 0, 0, 0, len, 0);
+	if (nlh == NULL) {
+		ZXIC_COMM_PRINT("%s: nlmsg_put failed.\n", __FUNCTION__);
+		return DPP_ERR;
+	}
+
+	nlh->nlmsg_flags = NLM_F_ACK;
+	memcpy(NLMSG_DATA(nlh), data, len);
+
+	rtn = nlmsg_multicast(dpp_netlink_sk, skb, 0, DPP_NETLINK_GROUP_ID, 0);
+	if (rtn < 0) {
+		ZXIC_COMM_PRINT("%s: nlmsg_multicast failed, rtn %d.\n", __FUNCTION__,
+						rtn);
+		return DPP_ERR;
+	}
+	return DPP_OK;
 }
 
-static DPP_STATUS dpp_netlink_dispach_msg(struct nlmsghdr *nlh)
+static DPP_STATUS dpp_netlink_dispach_msg(const struct nlmsghdr *nlh)
 {
-    ZXIC_UINT8 *data     = NULL;
-    ZXIC_UINT32 id       = 0;
-    ZXIC_UINT32 len      = 0;
-    ZXIC_UINT8 *req      = NULL;
-    ZXIC_VOID *resp      = NULL;
-    ZXIC_UINT32 resp_len = 0;
-    ZXIC_UINT32 rtn      = DPP_OK;
-
-    DPP_NETLINK_PROC_PTR ptr = NULL;
-
-    if (nlh == NULL)
-    {
-        ZXIC_COMM_PRINT("%s: nlh invalid.\n", __FUNCTION__);
-        return DPP_ERR;
-    }
-
-    id  = *(ZXIC_UINT32 *)NLMSG_DATA(nlh);
-    len = nlh->nlmsg_len - NLMSG_HDRLEN;
-    req = (ZXIC_UINT8 *)NLMSG_DATA(nlh);
-    if (id > (DPP_NETLINK_MAX_PROC - 1))
-    {
-        ZXIC_COMM_PRINT("%s: id %u invalid.\n", __FUNCTION__, id);
-        return DPP_ERR;
-    }
-
-    ptr = dpp_netlink_proc_ptr[id];
-    if (ptr == NULL)
-    {
-        ZXIC_COMM_PRINT("%s: ptr invalid.\n", __FUNCTION__);
-        return DPP_ERR;
-    }
-
-    rtn = ptr(req, len, &resp, &resp_len);
-    if (rtn != DPP_OK)
-    {
-        kfree(resp);
-        ZXIC_COMM_PRINT("%s: proc id %u failed.\n", __FUNCTION__, id);
-        return rtn;
-    }
-
-    data = (ZXIC_UINT8 *)kmalloc(NLMSG_ALIGN(resp_len) + sizeof(ZXIC_UINT32), GFP_KERNEL);
-    if (data == NULL)
-    {
-        kfree(resp);
-        ZXIC_COMM_PRINT("%s: kmalloc failed.\n", __FUNCTION__);
-        return DPP_ERR;
-    }
-    memcpy(data, &rtn, sizeof(ZXIC_UINT32));
-
-    if (resp != NULL)
-    {
-        memcpy(data + sizeof(ZXIC_UINT32), resp, resp_len);
-    }
-
-    dpp_netlink_send_ack_msg(data, NLMSG_ALIGN(resp_len) + sizeof(ZXIC_UINT32));
-
-    kfree(data);
-    kfree(resp);
-
-    return DPP_OK;
+	ZXIC_UINT8 *data = NULL;
+	ZXIC_UINT32 id = 0;
+	ZXIC_UINT32 len = 0;
+	ZXIC_UINT8 *req = NULL;
+	ZXIC_VOID *resp = NULL;
+	ZXIC_UINT32 resp_len = 0;
+	ZXIC_UINT32 rtn = DPP_OK;
+
+	DPP_NETLINK_PROC_PTR ptr = NULL;
+
+	if (nlh == NULL) {
+		ZXIC_COMM_PRINT("%s: nlh invalid.\n", __FUNCTION__);
+		return DPP_ERR;
+	}
+
+	id = *(ZXIC_UINT32 *)NLMSG_DATA(nlh);
+	len = nlh->nlmsg_len - NLMSG_HDRLEN;
+	req = (ZXIC_UINT8 *)NLMSG_DATA(nlh);
+	if (id > (DPP_NETLINK_MAX_PROC - 1)) {
+		ZXIC_COMM_PRINT("%s: id %u invalid.\n", __FUNCTION__, id);
+		return DPP_ERR;
+	}
+
+	ptr = dpp_netlink_proc_ptr[id];
+	if (ptr == NULL) {
+		ZXIC_COMM_PRINT("%s: ptr invalid.\n", __FUNCTION__);
+		return DPP_ERR;
+	}
+
+	rtn = ptr(req, len, &resp, &resp_len);
+	if (rtn != DPP_OK) {
+		kfree(resp);
+		ZXIC_COMM_PRINT("%s: proc id %u failed.\n", __FUNCTION__, id);
+		return rtn;
+	}
+
+	data = (ZXIC_UINT8 *)kmalloc(NLMSG_ALIGN(resp_len) + sizeof(ZXIC_UINT32),
+								 GFP_KERNEL);
+	if (data == NULL) {
+		kfree(resp);
+		ZXIC_COMM_PRINT("%s: kmalloc failed.\n", __FUNCTION__);
+		return DPP_ERR;
+	}
+	memcpy(data, &rtn, sizeof(ZXIC_UINT32));
+
+	if (resp != NULL) {
+		memcpy(data + sizeof(ZXIC_UINT32), resp, resp_len);
+	}
+
+	dpp_netlink_send_ack_msg(data, NLMSG_ALIGN(resp_len) + sizeof(ZXIC_UINT32));
+
+	kfree(data);
+	kfree(resp);
+
+	return DPP_OK;
 }
 
 static ZXIC_VOID dpp_netlink_recv_msg(struct sk_buff *__skb)
 {
-    struct sk_buff *skb;
-    struct nlmsghdr *nlh;
-    ZXIC_UINT32 rtn = DPP_ERR;
-
-    skb = skb_get(__skb);
-    if (skb == NULL)
-    {
-        ZXIC_COMM_PRINT("%s: get skb failed.\n", __FUNCTION__);
-        return;
-    }
-
-    nlh = nlmsg_hdr(skb);
-    if ((nlh == NULL) || !NLMSG_OK(nlh, skb->len))
-    {
-        kfree_skb(skb);
-        ZXIC_COMM_PRINT("%s: skb format invalid.\n", __FUNCTION__);
-        return;
-    }
-
-    if ((nlh->nlmsg_flags & NLM_F_REQUEST) != 0)
-    {
-        if (dpp_netlink_dispach_msg(nlh) != DPP_OK)
-        {
-            dpp_netlink_send_ack_msg((ZXIC_UINT8 *)&rtn, sizeof(ZXIC_UINT32));
-            ZXIC_COMM_PRINT("%s: dpp_netlink_dispach_msg failed.\n", __FUNCTION__);
-        }
-        kfree_skb(skb);
-        return;
-    }
-
-    kfree_skb(skb);
-    ZXIC_COMM_PRINT("%s: nlmsg_flags 0x%04x invalid.\n", __FUNCTION__, nlh->nlmsg_flags);
-    return;
+	struct sk_buff *skb;
+	struct nlmsghdr *nlh;
+	ZXIC_UINT32 rtn = DPP_ERR;
+
+	skb = skb_get(__skb);
+	if (skb == NULL) {
+		ZXIC_COMM_PRINT("%s: get skb failed.\n", __FUNCTION__);
+		return;
+	}
+
+	nlh = nlmsg_hdr(skb);
+	if ((nlh == NULL) || !NLMSG_OK(nlh, skb->len)) {
+		kfree_skb(skb);
+		ZXIC_COMM_PRINT("%s: skb format invalid.\n", __FUNCTION__);
+		return;
+	}
+
+	if ((nlh->nlmsg_flags & NLM_F_REQUEST) != 0) {
+		if (dpp_netlink_dispach_msg(nlh) != DPP_OK) {
+			kfree_skb(skb);
+			dpp_netlink_send_ack_msg((ZXIC_UINT8 *)&rtn, sizeof(ZXIC_UINT32));
+			ZXIC_COMM_PRINT("%s: dpp_netlink_dispach_msg failed.\n",
+							__FUNCTION__);
+		}
+		return;
+	}
+
+	kfree_skb(skb);
+	ZXIC_COMM_PRINT("%s: nlmsg_flags 0x%04x invalid.\n", __FUNCTION__,
+					nlh->nlmsg_flags);
+	return;
 }
 
 DPP_STATUS dpp_netlink_regist_msg_proc_fun(ZXIC_UINT32 id, ZXIC_VOID *ptr)
 {
-    if (ptr == NULL)
-    {
-        ZXIC_COMM_PRINT("%s: ptr invalid.\n", __FUNCTION__);
-        return DPP_ERR;
-    }
-    if (id > (DPP_NETLINK_MAX_PROC - 1))
-    {
-        ZXIC_COMM_PRINT("%s: id %u invalid.\n", __FUNCTION__, id);
-        return DPP_ERR;
-    }
-    dpp_netlink_proc_ptr[id] = ptr;
-    return DPP_OK;
+	if (ptr == NULL) {
+		ZXIC_COMM_PRINT("%s: ptr invalid.\n", __FUNCTION__);
+		return DPP_ERR;
+	}
+	if (id > (DPP_NETLINK_MAX_PROC - 1)) {
+		ZXIC_COMM_PRINT("%s: id %u invalid.\n", __FUNCTION__, id);
+		return DPP_ERR;
+	}
+	dpp_netlink_proc_ptr[id] = ptr;
+	return DPP_OK;
 }
 
 ZXIC_SINT32 dpp_netlink_init(ZXIC_VOID)
 {
-    struct netlink_kernel_cfg cfg = {
-        .input = dpp_netlink_recv_msg,
-    };
+	struct netlink_kernel_cfg cfg = {
+		.input = dpp_netlink_recv_msg,
+	};
 
-    ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__);
+	ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__);
 
-    // dpp_netlink_sk = netlink_kernel_create(get_net_ns_by_pid(1), DPP_NETLINK_PROTOCOL, &cfg);
-    dpp_netlink_sk = netlink_kernel_create(&init_net, DPP_NETLINK_PROTOCOL, &cfg);
-    if (!dpp_netlink_sk)
-    {
-        ZXIC_COMM_PRINT("%s: create socket failed.\n", __FUNCTION__);
-        return DPP_ERR;
-    }
+	// dpp_netlink_sk = netlink_kernel_create(get_net_ns_by_pid(1), DPP_NETLINK_PROTOCOL, &cfg);
+	dpp_netlink_sk =
+			netlink_kernel_create(&init_net, DPP_NETLINK_PROTOCOL, &cfg);
+	if (!dpp_netlink_sk) {
+		ZXIC_COMM_PRINT("%s: create socket failed.\n", __FUNCTION__);
+		return DPP_ERR;
+	}
 
-    ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__);
+	ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_VOID dpp_netlink_exit(ZXIC_VOID)
 {
-    ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__);
-    netlink_kernel_release(dpp_netlink_sk);
-    ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__);
+	ZXIC_COMM_PRINT("[%s] start.\n", __FUNCTION__);
+	netlink_kernel_release(dpp_netlink_sk);
+	ZXIC_COMM_PRINT("[%s] success.\n", __FUNCTION__);
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/qos/include/dpp_drv_qos.h b/src/net/drivers/net/ethernet/dinghai/en_np/qos/include/dpp_drv_qos.h
index 8916bb0e4e540789aa4b0e0a9c5282da9177d23d..aeceb1eabb63c371ed96ff92ca6e4ec79c4a5ae3 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/qos/include/dpp_drv_qos.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/qos/include/dpp_drv_qos.h
@@ -1,30 +1,30 @@
 /**************************************************************
 * TM调度器资源分配如下
-* FQ 
+* FQ
 *fq_num:  1280 : 0, 1, 2 ... 0x4ff
-*fq2_num: 1024 : 0x500, 0x502, 0x504 ... 0xcfe 
-*fq4_num: 1024 : 0xd00, 0xd04, 0xd08 ... 0x1cfc 
+*fq2_num: 1024 : 0x500, 0x502, 0x504 ... 0xcfe
+*fq4_num: 1024 : 0xd00, 0xd04, 0xd08 ... 0x1cfc
 *fq8_num: 1120 : 0x1d00, 0x1d08, 0x1d10 ... 0x3ff8
 * SP-WFQ
-*sp_num: 128 : 0x4000, 0x4001, 0x4002 ... 0x407f 
-*wfq_num: 2048 : 0x4080, 0x4081, 0x4082 ... 0x487f 
-*wfq2_num: 256 : 0x4880, 0x4882, 0x4884 ... 0x4a7e 
-*wfq4_num: 256 : 0x4a80, 0x4a84, 0x4a88 ... 0x4e7c 
-*wfq8_num: 688 : 0x4e80, 0x4e88, 0x4e90 ... 0x63f8 
+*sp_num: 128 : 0x4000, 0x4001, 0x4002 ... 0x407f
+*wfq_num: 2048 : 0x4080, 0x4081, 0x4082 ... 0x487f
+*wfq2_num: 256 : 0x4880, 0x4882, 0x4884 ... 0x4a7e
+*wfq4_num: 256 : 0x4a80, 0x4a84, 0x4a88 ... 0x4e7c
+*wfq8_num: 688 : 0x4e80, 0x4e88, 0x4e90 ... 0x63f8
 *
 *队列资源分配如下
 *flow id 0~0xf 预留 0队列用于MR复制队列， 0x10~0xfff 通用队列
 
 * PLCR profileid资源分配如下
-* 一级CAR 
-* flowid:32K, profileid:512 
-* 一级CAR 
-* flowid:4K, profileid:128 
-* 一级CAR 
-* flowid:1K, profileid:32 
+* 一级CAR
+* flowid:32K, profileid:512
+* 一级CAR
+* flowid:4K, profileid:128
+* 一级CAR
+* flowid:1K, profileid:32
 ***************************************************************/
-#ifndef  _DPP_DRV_QOS_H_
-#define  _DPP_DRV_QOS_H_
+#ifndef _DPP_DRV_QOS_H_
+#define _DPP_DRV_QOS_H_
 
 #include "zxic_common.h"
 #include "dpp_tm.h"
@@ -36,44 +36,61 @@
 /******************************************************************************
  *                                宏定义                                *
  *****************************************************************************/
-#define  DPP_VPORT_NUM_MAX  (0x7fff)
-#define  DPP_CRDT_LEVEL_MAX (7)
-#define  DPP_SCHE_TYPE_MAX  (10)
+#define DPP_VPORT_NUM_MAX (0x7fff)
+#define DPP_CRDT_LEVEL_MAX (7)
+#define DPP_SCHE_TYPE_MAX (10)
 
-#define  DPP_TM_PORT_WIDTH   (56)
-#define  DPP_TM_VPORT_WIDTH  (32)
-#define  DPP_TM_LEVEL_WIDTH  (28)
-#define  DPP_TM_TYPE_WIDTH   (24)
+#define DPP_TM_PORT_WIDTH (56)
+#define DPP_TM_VPORT_WIDTH (32)
+#define DPP_TM_LEVEL_WIDTH (28)
+#define DPP_TM_TYPE_WIDTH (24)
 
-#define  G_SCH_ID_LEN (8)
+#define G_SCH_ID_LEN (8)
 
-#define  CAR_TYPE_MAX (4)
+#define CAR_TYPE_MAX (4)
 
-#define  G_PROFILE_ID_LEN (8)
+#define G_PROFILE_ID_LEN (8)
 
 /* Get Real port */
-#define DPP_TM_CRDT_PP_PORT_GET(_gsch_id, _pp_port)  \
-    ((_pp_port) = ((_gsch_id >> DPP_TM_PORT_WIDTH) & 0xffff))
+#define DPP_TM_CRDT_PP_PORT_GET(_gsch_id, _pp_port) \
+	((_pp_port) = ((_gsch_id >> DPP_TM_PORT_WIDTH) & 0xffff))
 
 /* Get Real vport */
-#define DPP_TM_CRDT_VPORT_GET(_gsch_id, _vport)  \
-    ((_vport) = ((_gsch_id >> DPP_TM_VPORT_WIDTH) & 0xffff))
+#define DPP_TM_CRDT_VPORT_GET(_gsch_id, _vport) \
+	((_vport) = ((_gsch_id >> DPP_TM_VPORT_WIDTH) & 0xffff))
 
 /* Get Real level */
-#define DPP_TM_CRDT_LEVEL_GET(_gsch_id,_sche_level)  \
-    ((_sche_level) = ((_gsch_id >> DPP_TM_LEVEL_WIDTH) & 0xf))
+#define DPP_TM_CRDT_LEVEL_GET(_gsch_id, _sche_level) \
+	((_sche_level) = ((_gsch_id >> DPP_TM_LEVEL_WIDTH) & 0xf))
 
 /* Get Real type */
-#define DPP_TM_CRDT_TYPE_GET(_gsch_id,_sche_type)  \
-    ((_sche_type) = ((_gsch_id >> DPP_TM_TYPE_WIDTH) & 0xf))
+#define DPP_TM_CRDT_TYPE_GET(_gsch_id, _sche_type) \
+	((_sche_type) = ((_gsch_id >> DPP_TM_TYPE_WIDTH) & 0xf))
 
 /* Get Real se_id */
-#define DPP_TM_CRDT_SE_ID_GET(_gsch_id,_se_id)  \
-    ((_se_id) = ((_gsch_id & 0xffff)))
+#define DPP_TM_CRDT_SE_ID_GET(_gsch_id, _se_id) \
+	((_se_id) = ((_gsch_id & 0xffff)))
 
 /* Get Real profile */
-#define DPP_CAR_PROFILE_ID_GET(_profile_id,_profileid)  \
-    ((_profileid) = ((_profile_id & 0xffff)))
+#define DPP_CAR_PROFILE_ID_GET(_profile_id, _profileid) \
+	((_profileid) = ((_profile_id & 0xffff)))
+
+#define VF_ACTIVE(VPORT) ((VPORT & 0x0800) >> 11)
+#define EPID(VPORT) ((VPORT & 0x7000) >> 12)
+#define FUNC_NUM(VPORT) ((VPORT & 0x0700) >> 8)
+#define VFUNC_NUM(VPORT) ((VPORT & 0x00FF))
+
+#define PF_VQM_VFID_OFFSET (1152)
+#define IS_PF(VPORT) (!VF_ACTIVE(VPORT))
+#define VQM_VFID(VPORT)                                                        \
+	(IS_PF(VPORT) ? (PF_VQM_VFID_OFFSET + EPID(VPORT) * 8 + FUNC_NUM(VPORT)) : \
+					  (EPID(VPORT) * 256 + VFUNC_NUM(VPORT)))
+
+#define OWNER_PF_VQM_VFID(VPORT) \
+	(PF_VQM_VFID_OFFSET + EPID(VPORT) * 8 + FUNC_NUM(VPORT))
+#define OWNER_PF_VPORT(VPORT) (((EPID(VPORT)) << 12) | ((FUNC_NUM(VPORT)) << 8))
+
+#define VQM_VFID_MAX_NUM (2048)
 
 /******************************************************************************
  *                                类型定义                               *
@@ -84,485 +101,437 @@
  *****************************************************************************/
 /***********************************************************/
 /**对外接口  TM资源申请
-* @param   vport_id--vport号
-* @param   pp_port--端口0~9 
-* @param   numq--申请id个数 1
-* @param   level--挂接层级
-* @param   flags--se_id类型
-* @param   gsch_id--调度单元号
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_cosq_gsch_id_add(DPP_PF_INFO_T* pf_info, 
-                                ZXIC_UINT32 pp_port,
-                                ZXIC_UINT32 numq, 
-                                ZXIC_UINT32 level, 
-                                ZXIC_UINT32 flags, 
-                                ZXIC_UINT64 *p_gsch_id);
+ * @param   vport_id--vport号
+ * @param   pp_port--端口0~9
+ * @param   numq--申请id个数 1
+ * @param   level--挂接层级
+ * @param   flags--se_id类型
+ * @param   gsch_id--调度单元号
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_cosq_gsch_id_add(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 pp_port,
+								ZXIC_UINT32 numq, ZXIC_UINT32 level,
+								ZXIC_UINT32 flags, ZXIC_UINT64 *p_gsch_id);
 
 /***********************************************************/
 /**对外接口  TM资源释放
-* @param   vport_id--vport号
-* @param   pp_port--端口0~9 
-* @param   gsch_id--调度单元号
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_cosq_gsch_id_delete(DPP_PF_INFO_T* pf_info, 
-                                   ZXIC_UINT32 pp_port, 
-                                   ZXIC_UINT64 gsch_id);
+ * @param   vport_id--vport号
+ * @param   pp_port--端口0~9
+ * @param   gsch_id--调度单元号
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_cosq_gsch_id_delete(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 pp_port,
+								   ZXIC_UINT64 gsch_id);
 
 /***********************************************************/
 /**对外接口  读取TM根节点
-* @param   vport_id--vport号
-* @param   pp_port--端口0~9 
-* @param   gsch_id--调度单元号
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_sch_base_node_get(DPP_PF_INFO_T* pf_info,
-                                 ZXIC_UINT32 pp_port, 
-                                 ZXIC_UINT64 *gsch_id);
+ * @param   vport_id--vport号
+ * @param   pp_port--端口0~9
+ * @param   gsch_id--调度单元号
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_sch_base_node_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 pp_port,
+								 ZXIC_UINT64 *gsch_id);
 
 /***********************************************************/
 /**对外接口  配置se->pp->dev挂接关系
-* @param   vport_id--vport号
-* @param   se_id--调度器号
-* @param   pp_id-端口号
-* @param   weight-权重1
-* @param   sp_mapping-优先级0-7
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_crdt_se_pp_link_set(DPP_PF_INFO_T* pf_info, 
-                                   ZXIC_UINT32 se_id, 
-                                   ZXIC_UINT32 pp_id, 
-                                   ZXIC_UINT32 weight, 
-                                   ZXIC_UINT32 sp_mapping);
+ * @param   vport_id--vport号
+ * @param   se_id--调度器号
+ * @param   pp_id-端口号
+ * @param   weight-权重1
+ * @param   sp_mapping-优先级0-7
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_crdt_se_pp_link_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 se_id,
+								   ZXIC_UINT32 pp_id, ZXIC_UINT32 weight,
+								   ZXIC_UINT32 sp_mapping);
 
 /***********************************************************/
 /**对外接口  配置se->se层次化挂接关系
-* @param   vport_id--vport号
-* @param   se_id--调度器号
-* @param   se_linkid--上级调度器号
-* @param   se_weight -权重
-* @param   se_sp-优先级0-7
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_crdt_se_link_set(DPP_PF_INFO_T* pf_info, 
-                                ZXIC_UINT32 se_id, 
-                                ZXIC_UINT32 se_linkid, 
-                                ZXIC_UINT32 se_weight, 
-                                ZXIC_UINT32 se_sp);
+ * @param   vport_id--vport号
+ * @param   se_id--调度器号
+ * @param   se_linkid--上级调度器号
+ * @param   se_weight -权重
+ * @param   se_sp-优先级0-7
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_crdt_se_link_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 se_id,
+								ZXIC_UINT32 se_linkid, ZXIC_UINT32 se_weight,
+								ZXIC_UINT32 se_sp);
 
 /***********************************************************/
 /**对外接口  配置flow级流队列挂接关系
-* @param   vport_id--vport号
-* @param   flow_id--0~4095
-* @param   c_linkid--c桶se_id
-* @param   c_weight--c桶权重
-* @param   c_sp--c桶优先级
-* @param   mode--0-单桶 1-双桶
-* @param   e_linkid--e桶se_id
-* @param   e_weight--e桶权重
-* @param   e_sp--e桶优先级
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_crdt_flow_link_set(DPP_PF_INFO_T* pf_info,
-                                  ZXIC_UINT32 flow_id,
-                                  ZXIC_UINT32 c_linkid,
-                                  ZXIC_UINT32 c_weight,
-                                  ZXIC_UINT32 c_sp,
-                                  ZXIC_UINT32 mode,
-                                  ZXIC_UINT32 e_linkid,
-                                  ZXIC_UINT32 e_weight,
-                                  ZXIC_UINT32 e_sp);
+ * @param   vport_id--vport号
+ * @param   flow_id--0~4095
+ * @param   c_linkid--c桶se_id
+ * @param   c_weight--c桶权重
+ * @param   c_sp--c桶优先级
+ * @param   mode--0-单桶 1-双桶
+ * @param   e_linkid--e桶se_id
+ * @param   e_weight--e桶权重
+ * @param   e_sp--e桶优先级
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_crdt_flow_link_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 flow_id,
+								  ZXIC_UINT32 c_linkid, ZXIC_UINT32 c_weight,
+								  ZXIC_UINT32 c_sp, ZXIC_UINT32 mode,
+								  ZXIC_UINT32 e_linkid, ZXIC_UINT32 e_weight,
+								  ZXIC_UINT32 e_sp);
 
 /***********************************************************/
 /**对外接口  删除flow级流队列挂接关系
-* @param   vport_id--vport号
-* @param   id_s--起始flowid
-* @param   id_e--终止flowid
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_crdt_del_flow_link_set(DPP_PF_INFO_T* pf_info,
-                                      ZXIC_UINT32  id_s,
-                                      ZXIC_UINT32  id_e);
+ * @param   vport_id--vport号
+ * @param   id_s--起始flowid
+ * @param   id_e--终止flowid
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_crdt_del_flow_link_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 id_s,
+									  ZXIC_UINT32 id_e);
 
 /***********************************************************/
 /**对外接口  删除调度器挂接关系
-* @param   vport_id--vport号
-* @param   id_s--起始seid
-* @param   id_e--终止seid
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_crdt_del_se_link_set(DPP_PF_INFO_T* pf_info,
-                                    ZXIC_UINT32  id_s,
-                                    ZXIC_UINT32  id_e);
+ * @param   vport_id--vport号
+ * @param   id_s--起始seid
+ * @param   id_e--终止seid
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_crdt_del_se_link_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 id_s,
+									ZXIC_UINT32 id_e);
 
 /***********************************************************/
 /**对外接口  配置端口级整形
-* @param   vport_id--vport号
-* @param   pp_port--端口0~9
-* @param   cir   单位Kb
-* @param   cbs   单位KB
-* @param   c_en   c桶使能
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_port_shape_set(DPP_PF_INFO_T* pf_info,
-                              ZXIC_UINT32 pp_port,
-                              ZXIC_UINT32 cir,
-                              ZXIC_UINT32 cbs,
-                              ZXIC_UINT32 c_en);
+ * @param   vport_id--vport号
+ * @param   pp_port--端口0~9
+ * @param   cir   单位Kb
+ * @param   cbs   单位KB
+ * @param   c_en   c桶使能
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_port_shape_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 pp_port,
+							  ZXIC_UINT32 cir, ZXIC_UINT32 cbs,
+							  ZXIC_UINT32 c_en);
 
 /***********************************************************/
 /**对外接口  读取端口级整形
-* @param   vport_id--vport号
-* @param   pp_port--端口0~9
-* @param   p_para   整形信息:cir/cbs/en
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_port_shape_get(DPP_PF_INFO_T* pf_info,
-                              ZXIC_UINT32 pp_port,
-                              DPP_TM_SHAPE_PP_PARA_T *p_para);
+ * @param   vport_id--vport号
+ * @param   pp_port--端口0~9
+ * @param   p_para   整形信息:cir/cbs/en
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_port_shape_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 pp_port,
+							  DPP_TM_SHAPE_PP_PARA_T *p_para);
 
 /***********************************************************/
 /**对外接口  配置调度器整形
-* @param   vport_id  vport号
-* @param   se_id     调度器编号号
-* @param   pir       pir总速率，单位Kb，范围同cir
-* @param   pbs       pbs总桶深，单位KB，范围同cbs
-* @param   db_en     整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效
-* @param   cir       调度器cir速率，单位Kb
-* @param   cbs       调度器cbs桶深，单位KB
-*                    注：cbs=0 表示关闭整形,即不限速
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_se_shape_set(DPP_PF_INFO_T* pf_info,
-                            ZXIC_UINT32 se_id,
-                            ZXIC_UINT32 pir,
-                            ZXIC_UINT32 pbs,
-                            ZXIC_UINT32 db_en,
-                            ZXIC_UINT32 cir,
-                            ZXIC_UINT32 cbs);
+ * @param   vport_id  vport号
+ * @param   se_id     调度器编号号
+ * @param   pir       pir总速率，单位Kb，范围同cir
+ * @param   pbs       pbs总桶深，单位KB，范围同cbs
+ * @param   db_en     整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效
+ * @param   cir       调度器cir速率，单位Kb
+ * @param   cbs       调度器cbs桶深，单位KB
+ *                    注：cbs=0 表示关闭整形,即不限速
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_se_shape_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 se_id,
+							ZXIC_UINT32 pir, ZXIC_UINT32 pbs, ZXIC_UINT32 db_en,
+							ZXIC_UINT32 cir, ZXIC_UINT32 cbs);
 
 /***********************************************************/
 /**对外接口  配置flow整形
-* @param   vport_id  vport号
-* @param   flow_id   流队列号
-* @param   cir       cir速率，单位Kb
-* @param   cbs       cbs桶深，单位KB
-*                     注：cbs=0 表示关闭整形,即不限速
-* @param   db_en     双桶整形使能，0-单桶，1-双桶
-* @param   eir       eir速率，单位Kb
-* @param   ebs       ebs桶深，单位KB
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_flow_shape_set(DPP_PF_INFO_T* pf_info,
-                              ZXIC_UINT32 flow_id,
-                              ZXIC_UINT32 cir,
-                              ZXIC_UINT32 cbs,
-                              ZXIC_UINT32 db_en,
-                              ZXIC_UINT32 eir,
-                              ZXIC_UINT32 ebs);
+ * @param   vport_id  vport号
+ * @param   flow_id   流队列号
+ * @param   cir       cir速率，单位Kb
+ * @param   cbs       cbs桶深，单位KB
+ *                     注：cbs=0 表示关闭整形,即不限速
+ * @param   db_en     双桶整形使能，0-单桶，1-双桶
+ * @param   eir       eir速率，单位Kb
+ * @param   ebs       ebs桶深，单位KB
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_flow_shape_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 flow_id,
+							  ZXIC_UINT32 cir, ZXIC_UINT32 cbs,
+							  ZXIC_UINT32 db_en, ZXIC_UINT32 eir,
+							  ZXIC_UINT32 ebs);
 
 /***********************************************************/
 /**对外接口  配置流队列挂接到端口号
-* @param   vport_id  vport号
-* @param   flow_id    流队列号
-* @param   port      端口0~9      
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_flow_map_port_set(DPP_PF_INFO_T* pf_info,
-                                 ZXIC_UINT32  flow_id,
-                                 ZXIC_UINT32  port);
+ * @param   vport_id  vport号
+ * @param   flow_id    流队列号
+ * @param   port      端口0~9
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_flow_map_port_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 flow_id,
+								 ZXIC_UINT32 port);
 
 /***********************************************************/
 /**对外接口  读取流队列挂接的端口号
-* @param   vport_id  vport号
-* @param   flowid    流队列号
-* @param   port      端口0~9      
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_flow_map_port_get(DPP_PF_INFO_T* pf_info,
-                                 ZXIC_UINT32  flow_id,
-                                 ZXIC_UINT32  *p_port);
+ * @param   vport_id  vport号
+ * @param   flowid    流队列号
+ * @param   port      端口0~9
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_flow_map_port_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 flow_id,
+								 ZXIC_UINT32 *p_port);
 
 /***********************************************************/
 /**对外接口  配置TD门限值
-* @param   vport_id  vport号
-* @param   flow_id   流队列号
-* @param   td_th     配置的丢弃门限值      
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_flow_td_th_set(DPP_PF_INFO_T* pf_info,
-                              ZXIC_UINT32  flow_id,
-                              ZXIC_UINT32  td_th);
+ * @param   vport_id  vport号
+ * @param   flow_id   流队列号
+ * @param   td_th     配置的丢弃门限值
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_flow_td_th_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 flow_id,
+							  ZXIC_UINT32 td_th);
 
 /***********************************************************/
 /**对外接口  读取TD门限值
-* @param   vport_id  vport号
-* @param   flow_id   流队列号
-* @param   p_td_th   配置的丢弃门限值      
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_flow_td_th_get(DPP_PF_INFO_T* pf_info,
-                              ZXIC_UINT32  flow_id,
-                              ZXIC_UINT32  *p_td_th);
+ * @param   vport_id  vport号
+ * @param   flow_id   流队列号
+ * @param   p_td_th   配置的丢弃门限值
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_flow_td_th_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 flow_id,
+							  ZXIC_UINT32 *p_td_th);
 
 /***********************************************************/
 /**对外接口  设置block值
-* @param   vport_id  vport号
-* @param   size   配置block值      
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_blk_size_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 size);
+ * @param   vport_id  vport号
+ * @param   size   配置block值
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_blk_size_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 size);
 
 /***********************************************************/
 /**对外接口  配置全局pfc使能状态
-* @param   vport_id  vport号
-* @param   pfc_en    使能开关    
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_qmu_pfc_en_set(DPP_PF_INFO_T* pf_info, 
-                              ZXIC_UINT32 pfc_en);
+ * @param   vport_id  vport号
+ * @param   pfc_en    使能开关
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_qmu_pfc_en_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 pfc_en);
 
 /***********************************************************/
 /**对外接口  读取全局pfc使能状态
-* @param   vport_id  vport号
-* @param   p_pfc_en    使能开关    
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_qmu_pfc_en_get(DPP_PF_INFO_T* pf_info, 
-                              ZXIC_UINT32 *p_pfc_en);
+ * @param   vport_id  vport号
+ * @param   p_pfc_en    使能开关
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_qmu_pfc_en_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 *p_pfc_en);
 
 /***********************************************************/
 /**对外接口  配置物理端口pfc使能状态
-* @param   vport_id  vport号
-* @param   port_id    端口0~9
-* @param   port_en    使能开关   
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_qmu_port_pfc_set(DPP_PF_INFO_T* pf_info, 
-                                ZXIC_UINT32 port_id,
-                                ZXIC_UINT32 port_en);
+ * @param   vport_id  vport号
+ * @param   port_id    端口0~9
+ * @param   port_en    使能开关
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_qmu_port_pfc_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 port_id,
+								ZXIC_UINT32 port_en);
 
 /***********************************************************/
 /**对外接口  读取物理端口pfc使能状态
-* @param   vport_id  vport号
-* @param   port_id    端口0~9
-* @param   p_port_en  使能开关    
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_qmu_port_pfc_get(DPP_PF_INFO_T* pf_info, 
-                                ZXIC_UINT32 port_id,
-                                ZXIC_UINT32 *p_port_en);
-
+ * @param   vport_id  vport号
+ * @param   port_id    端口0~9
+ * @param   p_port_en  使能开关
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_qmu_port_pfc_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 port_id,
+								ZXIC_UINT32 *p_port_en);
 
 /***********************************************************/
 /**对外接口  申请profile_id资源
-* @param   vport_id    vport号
-* @param   numq        申请id个数 1
-* @param   flags       car类型
-* @param   profile_id  限速模版号   
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_car_profile_id_add(DPP_PF_INFO_T* pf_info,
-                                  ZXIC_UINT32 flags,
-                                  ZXIC_UINT64 *profile_id);
+ * @param   vport_id    vport号
+ * @param   numq        申请id个数 1
+ * @param   flags       car类型
+ * @param   profile_id  限速模版号
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_car_profile_id_add(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 flags,
+								  ZXIC_UINT64 *profile_id);
 
 /***********************************************************/
 /**对外接口  释放profile_id资源
-* @param   vport_id    vport号
-* @param   flags       car类型
-* @param   profile_id  限速模版号  
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_car_profile_id_delete(DPP_PF_INFO_T* pf_info, 
-                                     ZXIC_UINT32 flags, 
-                                     ZXIC_UINT64 profile_id);
+ * @param   vport_id    vport号
+ * @param   flags       car类型
+ * @param   profile_id  限速模版号
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_car_profile_id_delete(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 flags,
+									 ZXIC_UINT64 profile_id);
 
 /***********************************************************/
 /**对外接口 配置flow_id和profile_id的绑定关系，并配置限速模板使能
-* @param   vport_id     vport号
-* @param   car_type     car模式
-* @param   flow_id      队列号
-* @param   drop_flag    丢弃标志
-* @param   plcr_en      限速使能
-* @param   profile_id   模板编号
-*
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_car_queue_cfg_set(DPP_PF_INFO_T* pf_info,
-                                 ZXIC_UINT32 car_type,
-                                 ZXIC_UINT32 flow_id,
-                                 ZXIC_UINT32 drop_flag,
-                                 ZXIC_UINT32 plcr_en,
-                                 ZXIC_UINT32 profile_id);
+ * @param   vport_id     vport号
+ * @param   car_type     car模式
+ * @param   flow_id      队列号
+ * @param   drop_flag    丢弃标志
+ * @param   plcr_en      限速使能
+ * @param   profile_id   模板编号
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_car_queue_cfg_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 car_type,
+								 ZXIC_UINT32 flow_id, ZXIC_UINT32 drop_flag,
+								 ZXIC_UINT32 plcr_en, ZXIC_UINT32 profile_id);
 
 /***********************************************************/
 /**对外接口 查询flow_id和profile_id的绑定关系
-* @param   vport_id     vport号
-* @param   car_type     car模式
-* @param   flow_id      队列号
-* @param   p_drop_flag    丢弃标志
-* @param   p_plcr_en      限速使能
-* @param   p_profile_id   模板编号
-*
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_car_queue_cfg_get(DPP_PF_INFO_T* pf_info,
-                                 ZXIC_UINT32 car_type,
-                                 ZXIC_UINT32 flow_id,
-                                 ZXIC_UINT32 *p_drop_flag,
-                                 ZXIC_UINT32 *p_plcr_en,
-                                 ZXIC_UINT32 *p_profile_id);
+ * @param   vport_id     vport号
+ * @param   car_type     car模式
+ * @param   flow_id      队列号
+ * @param   p_drop_flag    丢弃标志
+ * @param   p_plcr_en      限速使能
+ * @param   p_profile_id   模板编号
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_car_queue_cfg_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 car_type,
+								 ZXIC_UINT32 flow_id, ZXIC_UINT32 *p_drop_flag,
+								 ZXIC_UINT32 *p_plcr_en,
+								 ZXIC_UINT32 *p_profile_id);
 
 /***********************************************************/
 /**对外接口 配置profile_id限速模版
-* @param   vport_id     vport号      
-* @param   car_type     car模式
-* @param   pkt_sign     限速模式0-字节;1-包
-* @param   profile_id   模板编号
-* @param   p_car_profile_cfg   限速参数
-*
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_car_profile_cfg_set(DPP_PF_INFO_T* pf_info,
-                                   ZXIC_UINT32 car_type,
-                                   ZXIC_UINT32 pkt_sign,
-                                   ZXIC_UINT32 profile_id,
-                                   ZXIC_VOID* p_car_profile_cfg);
+ * @param   vport_id     vport号
+ * @param   car_type     car模式
+ * @param   pkt_sign     限速模式0-字节;1-包
+ * @param   profile_id   模板编号
+ * @param   p_car_profile_cfg   限速参数
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_car_profile_cfg_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 car_type,
+								   ZXIC_UINT32 pkt_sign, ZXIC_UINT32 profile_id,
+								   ZXIC_VOID *p_car_profile_cfg);
 
 /***********************************************************/
 /**对外接口 查询profile_id限速模版参数
-* @param   vport_id     vport号      
-* @param   car_type     car模式
-* @param   pkt_sign     限速模式0-字节;1-包
-* @param   profile_id   模板编号
-* @param   p_car_profile_cfg   限速参数
-*
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_car_profile_cfg_get(DPP_PF_INFO_T* pf_info,
-                                   ZXIC_UINT32 car_type,
-                                   ZXIC_UINT32 pkt_sign,
-                                   ZXIC_UINT32 profile_id,
-                                   ZXIC_VOID* p_car_profile_cfg);
+ * @param   vport_id     vport号
+ * @param   car_type     car模式
+ * @param   pkt_sign     限速模式0-字节;1-包
+ * @param   profile_id   模板编号
+ * @param   p_car_profile_cfg   限速参数
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_car_profile_cfg_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 car_type,
+								   ZXIC_UINT32 pkt_sign, ZXIC_UINT32 profile_id,
+								   ZXIC_VOID *p_car_profile_cfg);
 
 /***********************************************************/
 /**对外接口 配置队列映射关系
-* @param   dev_id       设备号
-* @param   car_type     car模式类型，参见STAT_CAR_TYPE_E
-* @param   flow_id      队列号
-* @param   map_flow_id  映射队列号
-* @param   map_sp       映射sp
-*
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_car_queue_map_set(DPP_PF_INFO_T* pf_info,
-                                 ZXIC_UINT32 car_type,
-                                 ZXIC_UINT32 flow_id,
-                                 ZXIC_UINT32 map_flow_id,
-                                 ZXIC_UINT32 map_sp);
+ * @param   dev_id       设备号
+ * @param   car_type     car模式类型，参见STAT_CAR_TYPE_E
+ * @param   flow_id      队列号
+ * @param   map_flow_id  映射队列号
+ * @param   map_sp       映射sp
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_car_queue_map_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 car_type,
+								 ZXIC_UINT32 flow_id, ZXIC_UINT32 map_flow_id,
+								 ZXIC_UINT32 map_sp);
 
 /***********************************************************/
 /**对外接口 配置队列映射关系
-* @param   dev_id       设备号
-* @param   car_type     car模式类型，参见STAT_CAR_TYPE_E
-* @param   flow_id      队列号
-* @param   map_flow_id  映射队列号
-* @param   map_sp       映射sp
-*
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_car_queue_map_get(DPP_PF_INFO_T* pf_info,
-                                 ZXIC_UINT32 car_type,
-                                 ZXIC_UINT32 flow_id,
-                                 ZXIC_UINT32 *p_map_flow_id,
-                                 ZXIC_UINT32 *p_map_sp);
+ * @param   dev_id       设备号
+ * @param   car_type     car模式类型，参见STAT_CAR_TYPE_E
+ * @param   flow_id      队列号
+ * @param   map_flow_id  映射队列号
+ * @param   map_sp       映射sp
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_car_queue_map_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 car_type,
+								 ZXIC_UINT32 flow_id,
+								 ZXIC_UINT32 *p_map_flow_id,
+								 ZXIC_UINT32 *p_map_sp);
 
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/qos/source/dpp_drv_qos.c b/src/net/drivers/net/ethernet/dinghai/en_np/qos/source/dpp_drv_qos.c
index 3ee97d6a605e0989b1c7ff9894256e3ea73fad86..043a281d4557a9ef5fe4aac311e23cd2fc3d1b84 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/qos/source/dpp_drv_qos.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/qos/source/dpp_drv_qos.c
@@ -26,50 +26,56 @@
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_cosq_gsch_id_add(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 pp_port, ZXIC_UINT32 numq, ZXIC_UINT32 level,
-                                ZXIC_UINT32 flags, ZXIC_UINT64 *p_gsch_id)
+DPP_STATUS dpp_cosq_gsch_id_add(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 pp_port,
+								ZXIC_UINT32 numq, ZXIC_UINT32 level,
+								ZXIC_UINT32 flags, ZXIC_UINT64 *p_gsch_id)
 {
-    DPP_STATUS ret         = DPP_OK;
-    DPP_DEV_T dev          = {0};
-    ZXIC_UINT32 dev_id     = 0;
-    ZXIC_UINT32 num        = 0;
-    ZXIC_UINT32 *gsch_id = ZXIC_NULL;
-    ZXIC_UINT32 gsch_id_h = 0;
-    ZXIC_UINT32 gsch_id_l = 0;
-    ZXIC_UINT64 temp_id    = 0;
-
-    ZXIC_COMM_CHECK_POINT(pf_info);
-
-    gsch_id = (ZXIC_UINT32 *)kmalloc(G_SCH_ID_LEN, GFP_KERNEL);
-    ZXIC_COMM_CHECK_POINT(gsch_id);
-
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_dev_get", gsch_id);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX, gsch_id);
-    ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, pp_port, 0, DPP_TM_PP_NUM - 1, gsch_id);
-    ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, level, 0, DPP_CRDT_LEVEL_MAX, gsch_id);
-    ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, flags, 0, DPP_SCHE_TYPE_MAX, gsch_id);
-    num = ((flags == FLOW_SCHE) ? numq : 1);
-
-    ret = dpp_agent_channel_tm_seid_request(&dev, pp_port, pf_info->vport, level, flags, num, gsch_id);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_agent_channel_tm_seid_request", gsch_id);
-
-    gsch_id_h = *(gsch_id + 1);
-    gsch_id_l = *gsch_id;
-
-    temp_id = ((ZXIC_UINT64)gsch_id_h) << 32 | ((ZXIC_UINT64)gsch_id_l);
-
-    if (DPP_OK != (ZXIC_UINT32)(temp_id >> 56))
-    {
-        kfree(gsch_id);
-        return DPP_ERR;
-    }
-
-    *p_gsch_id = temp_id;
-    kfree(gsch_id);
-
-    return DPP_OK;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 num = 0;
+	ZXIC_UINT32 *gsch_id = ZXIC_NULL;
+	ZXIC_UINT32 gsch_id_h = 0;
+	ZXIC_UINT32 gsch_id_l = 0;
+	ZXIC_UINT64 temp_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(pf_info);
+
+	gsch_id = (ZXIC_UINT32 *)kmalloc(G_SCH_ID_LEN, GFP_KERNEL);
+	ZXIC_COMM_CHECK_POINT(gsch_id);
+
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_dev_get", gsch_id);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, pf_info->vport, 0,
+													DPP_VPORT_NUM_MAX, gsch_id);
+	ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, pp_port, 0,
+													DPP_TM_PP_NUM - 1, gsch_id);
+	ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(
+			dev_id, level, 0, DPP_CRDT_LEVEL_MAX, gsch_id);
+	ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, flags, 0,
+													DPP_SCHE_TYPE_MAX, gsch_id);
+	num = ((flags == FLOW_SCHE) ? numq : 1);
+
+	ret = dpp_agent_channel_tm_seid_request(&dev, pp_port, pf_info->vport,
+											level, flags, num, gsch_id);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_agent_channel_tm_seid_request",
+								   gsch_id);
+
+	gsch_id_h = *(gsch_id + 1);
+	gsch_id_l = *gsch_id;
+
+	temp_id = ((ZXIC_UINT64)gsch_id_h) << 32 | ((ZXIC_UINT64)gsch_id_l);
+
+	if (DPP_OK != (ZXIC_UINT32)(temp_id >> 56)) {
+		kfree(gsch_id);
+		return DPP_ERR;
+	}
+
+	*p_gsch_id = temp_id;
+	kfree(gsch_id);
+
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_cosq_gsch_id_add);
 
@@ -83,37 +89,39 @@ EXPORT_SYMBOL(dpp_cosq_gsch_id_add);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_cosq_gsch_id_delete(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 pp_port, ZXIC_UINT64 gsch_id)
+DPP_STATUS dpp_cosq_gsch_id_delete(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 pp_port,
+								   ZXIC_UINT64 gsch_id)
 {
-    DPP_STATUS ret         = DPP_OK;
-    DPP_DEV_T dev          = {0};
-    ZXIC_UINT32 dev_id     = 0;
-    ZXIC_UINT32 sche_level = 0;
-    ZXIC_UINT32 sche_type  = 0;
-    ZXIC_UINT32 num        = 1;
-    ZXIC_UINT32 se_id      = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 sche_level = 0;
+	ZXIC_UINT32 sche_type = 0;
+	ZXIC_UINT32 num = 1;
+	ZXIC_UINT32 se_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pp_port, 0, DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pp_port, 0, DPP_TM_PP_NUM - 1);
 
-    DPP_TM_CRDT_LEVEL_GET(gsch_id, sche_level);
-    DPP_TM_CRDT_TYPE_GET(gsch_id, sche_type);
-    DPP_TM_CRDT_SE_ID_GET(gsch_id, se_id);
+	DPP_TM_CRDT_LEVEL_GET(gsch_id, sche_level);
+	DPP_TM_CRDT_TYPE_GET(gsch_id, sche_type);
+	DPP_TM_CRDT_SE_ID_GET(gsch_id, se_id);
 
-    ret = dpp_agent_channel_tm_seid_release(&dev, pp_port, pf_info->vport, sche_level, sche_type, num, se_id);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_agent_channel_tm_seid_release");
+	ret = dpp_agent_channel_tm_seid_release(&dev, pp_port, pf_info->vport,
+											sche_level, sche_type, num, se_id);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_agent_channel_tm_seid_release");
 
-    // if (DPP_OK != ret)
-    // {
-    //     return DPP_ERR;
-    // }
+	if (DPP_OK != ret) {
+		return DPP_ERR;
+	}
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_cosq_gsch_id_delete);
 
@@ -127,44 +135,48 @@ EXPORT_SYMBOL(dpp_cosq_gsch_id_delete);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_sch_base_node_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 pp_port, ZXIC_UINT64 *p_gsch_id)
+DPP_STATUS dpp_sch_base_node_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 pp_port,
+								 ZXIC_UINT64 *p_gsch_id)
 {
-    DPP_STATUS ret         = DPP_OK;
-    DPP_DEV_T dev          = {0};
-    ZXIC_UINT32 dev_id     = 0;
-    ZXIC_UINT32 *gsch_id = ZXIC_NULL;
-    ZXIC_UINT32 gsch_id_h = 0;
-    ZXIC_UINT32 gsch_id_l = 0;
-    ZXIC_UINT64 temp_id    = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 *gsch_id = ZXIC_NULL;
+	ZXIC_UINT32 gsch_id_h = 0;
+	ZXIC_UINT32 gsch_id_l = 0;
+	ZXIC_UINT64 temp_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    gsch_id = (ZXIC_UINT32 *)kmalloc(G_SCH_ID_LEN, GFP_KERNEL);
-    ZXIC_COMM_CHECK_POINT(gsch_id);
+	gsch_id = (ZXIC_UINT32 *)kmalloc(G_SCH_ID_LEN, GFP_KERNEL);
+	ZXIC_COMM_CHECK_POINT(gsch_id);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_dev_get", gsch_id);
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_dev_get", gsch_id);
 
-    ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX, gsch_id);
-    ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, pp_port, 0, DPP_TM_PP_NUM - 1, gsch_id);
+	ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, pf_info->vport, 0,
+													DPP_VPORT_NUM_MAX, gsch_id);
+	ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, pp_port, 0,
+													DPP_TM_PP_NUM - 1, gsch_id);
 
-    ret = dpp_agent_channel_tm_base_node_get(&dev, pp_port, pf_info->vport, gsch_id);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_agent_channel_tm_base_node_get", gsch_id);
+	ret = dpp_agent_channel_tm_base_node_get(&dev, pp_port, pf_info->vport,
+											 gsch_id);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_agent_channel_tm_base_node_get",
+								   gsch_id);
 
-    gsch_id_h = *(gsch_id + 1);
-    gsch_id_l = *gsch_id;
+	gsch_id_h = *(gsch_id + 1);
+	gsch_id_l = *gsch_id;
 
-    temp_id = ((ZXIC_UINT64)gsch_id_h) << 32 | ((ZXIC_UINT64)gsch_id_l);
-    if (DPP_OK != (ZXIC_UINT32)(temp_id >> 56))
-    {
-        kfree(gsch_id);
-        return DPP_ERR;
-    }
+	temp_id = ((ZXIC_UINT64)gsch_id_h) << 32 | ((ZXIC_UINT64)gsch_id_l);
+	if (DPP_OK != (ZXIC_UINT32)(temp_id >> 56)) {
+		kfree(gsch_id);
+		return DPP_ERR;
+	}
 
-    *p_gsch_id = temp_id;
-    kfree(gsch_id);
+	*p_gsch_id = temp_id;
+	kfree(gsch_id);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_sch_base_node_get);
 
@@ -180,28 +192,33 @@ EXPORT_SYMBOL(dpp_sch_base_node_get);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_crdt_se_pp_link_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 se_id, ZXIC_UINT32 pp_id, ZXIC_UINT32 weight,
-                                   ZXIC_UINT32 sp_mapping)
+DPP_STATUS dpp_crdt_se_pp_link_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 se_id,
+								   ZXIC_UINT32 pp_id, ZXIC_UINT32 weight,
+								   ZXIC_UINT32 sp_mapping)
 {
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pp_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, weight, 0, DPP_TM_SCH_WEIGHT_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sp_mapping, DPP_TM_SCH_SP_0, DPP_TM_SCH_SP_8);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_id, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pp_id, 0, DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, weight, 0,
+										DPP_TM_SCH_WEIGHT_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sp_mapping, DPP_TM_SCH_SP_0,
+										DPP_TM_SCH_SP_8);
 
-    ret = dpp_tm_crdt_se_pp_link_set(&dev, se_id, pp_id, weight, sp_mapping);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_crdt_se_pp_link_set");
+	ret = dpp_tm_crdt_se_pp_link_set(&dev, se_id, pp_id, weight, sp_mapping);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_crdt_se_pp_link_set");
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_crdt_se_pp_link_set);
 
@@ -217,28 +234,34 @@ EXPORT_SYMBOL(dpp_crdt_se_pp_link_set);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_crdt_se_link_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 se_id, ZXIC_UINT32 se_linkid, ZXIC_UINT32 se_weight,
-                                ZXIC_UINT32 se_sp)
+DPP_STATUS dpp_crdt_se_link_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 se_id,
+								ZXIC_UINT32 se_linkid, ZXIC_UINT32 se_weight,
+								ZXIC_UINT32 se_sp)
 {
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
-
-    ZXIC_COMM_CHECK_POINT(pf_info);
-
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_linkid, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_weight, 0, DPP_TM_SCH_WEIGHT_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_sp, DPP_TM_SCH_SP_0, DPP_TM_SCH_SP_8);
-
-    ret = dpp_tm_crdt_se_link_set(&dev, se_id, se_linkid, se_weight, se_sp);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_crdt_se_link_set");
-
-    return ret;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(pf_info);
+
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_id, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_linkid, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_weight, 0,
+										DPP_TM_SCH_WEIGHT_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_sp, DPP_TM_SCH_SP_0,
+										DPP_TM_SCH_SP_8);
+
+	ret = dpp_tm_crdt_se_link_set(&dev, se_id, se_linkid, se_weight, se_sp);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_crdt_se_link_set");
+
+	return ret;
 }
 EXPORT_SYMBOL(dpp_crdt_se_link_set);
 
@@ -258,25 +281,29 @@ EXPORT_SYMBOL(dpp_crdt_se_link_set);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_crdt_flow_link_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 flow_id, ZXIC_UINT32 c_linkid, ZXIC_UINT32 c_weight,
-                                  ZXIC_UINT32 c_sp, ZXIC_UINT32 mode, ZXIC_UINT32 e_linkid, ZXIC_UINT32 e_weight,
-                                  ZXIC_UINT32 e_sp)
+DPP_STATUS dpp_crdt_flow_link_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 flow_id,
+								  ZXIC_UINT32 c_linkid, ZXIC_UINT32 c_weight,
+								  ZXIC_UINT32 c_sp, ZXIC_UINT32 mode,
+								  ZXIC_UINT32 e_linkid, ZXIC_UINT32 e_weight,
+								  ZXIC_UINT32 e_sp)
 {
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
 
-    ret = dpp_tm_crdt_flow_link_set(&dev, flow_id, c_linkid, c_weight, c_sp, mode, e_linkid, e_weight, e_sp);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_crdt_flow_link_set");
+	ret = dpp_tm_crdt_flow_link_set(&dev, flow_id, c_linkid, c_weight, c_sp,
+									mode, e_linkid, e_weight, e_sp);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_crdt_flow_link_set");
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_crdt_flow_link_set);
 
@@ -290,25 +317,27 @@ EXPORT_SYMBOL(dpp_crdt_flow_link_set);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_crdt_del_flow_link_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 id_s, ZXIC_UINT32 id_e)
+DPP_STATUS dpp_crdt_del_flow_link_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 id_s,
+									  ZXIC_UINT32 id_e)
 {
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id_s, 0, DPP_ETM_CRDT_NUM);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id_e, 0, DPP_ETM_CRDT_NUM);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id_s, 0, DPP_ETM_CRDT_NUM);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id_e, 0, DPP_ETM_CRDT_NUM);
 
-    ret = dpp_tm_crdt_del_flow_link_set(&dev, id_s, id_e);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_crdt_del_flow_link_set");
+	ret = dpp_tm_crdt_del_flow_link_set(&dev, id_s, id_e);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_crdt_del_flow_link_set");
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_crdt_del_flow_link_set);
 
@@ -322,25 +351,27 @@ EXPORT_SYMBOL(dpp_crdt_del_flow_link_set);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_crdt_del_se_link_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 id_s, ZXIC_UINT32 id_e)
+DPP_STATUS dpp_crdt_del_se_link_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 id_s,
+									ZXIC_UINT32 id_e)
 {
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id_s, 0, DPP_ETM_FQSPWFQ_NUM);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id_e, 0, DPP_ETM_FQSPWFQ_NUM);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id_s, 0, DPP_ETM_FQSPWFQ_NUM);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id_e, 0, DPP_ETM_FQSPWFQ_NUM);
 
-    ret = dpp_tm_crdt_del_se_link_set(&dev, id_s, id_e);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_crdt_del_se_link_set");
+	ret = dpp_tm_crdt_del_se_link_set(&dev, id_s, id_e);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_crdt_del_se_link_set");
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_crdt_del_se_link_set);
 
@@ -356,26 +387,28 @@ EXPORT_SYMBOL(dpp_crdt_del_se_link_set);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_port_shape_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 pp_port, ZXIC_UINT32 cir, ZXIC_UINT32 cbs,
-                              ZXIC_UINT32 c_en)
+DPP_STATUS dpp_port_shape_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 pp_port,
+							  ZXIC_UINT32 cir, ZXIC_UINT32 cbs,
+							  ZXIC_UINT32 c_en)
 {
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pp_port, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, c_en, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pp_port, 0, DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, c_en, 0, 1);
 
-    ret = dpp_tm_shape_pp_para_wr(&dev, pp_port, cir, cbs, c_en);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_shape_pp_para_wr");
+	ret = dpp_tm_shape_pp_para_wr(&dev, pp_port, cir, cbs, c_en);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_shape_pp_para_wr");
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_port_shape_set);
 
@@ -389,29 +422,31 @@ EXPORT_SYMBOL(dpp_port_shape_set);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_port_shape_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 pp_port, DPP_TM_SHAPE_PP_PARA_T *p_para)
+DPP_STATUS dpp_port_shape_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 pp_port,
+							  DPP_TM_SHAPE_PP_PARA_T *p_para)
 {
-    DPP_STATUS ret                      = DPP_OK;
-    DPP_DEV_T dev                       = {0};
-    ZXIC_UINT32 dev_id                  = 0;
-    DPP_TM_SHAPE_PP_PARA_T pp_shap_para = {0};
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
+	DPP_TM_SHAPE_PP_PARA_T pp_shap_para = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pp_port, 0, DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pp_port, 0, DPP_TM_PP_NUM - 1);
 
-    ret = dpp_tm_shape_pp_para_get(&dev, pp_port, &pp_shap_para);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_shape_pp_para_get");
+	ret = dpp_tm_shape_pp_para_get(&dev, pp_port, &pp_shap_para);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_shape_pp_para_get");
 
-    p_para->c_en = pp_shap_para.c_en;
-    p_para->cir  = pp_shap_para.cir;
-    p_para->cbs  = pp_shap_para.cbs;
+	p_para->c_en = pp_shap_para.c_en;
+	p_para->cir = pp_shap_para.cir;
+	p_para->cbs = pp_shap_para.cbs;
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_port_shape_get);
 
@@ -430,24 +465,26 @@ EXPORT_SYMBOL(dpp_port_shape_get);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_se_shape_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 se_id, ZXIC_UINT32 pir, ZXIC_UINT32 pbs,
-                            ZXIC_UINT32 db_en, ZXIC_UINT32 cir, ZXIC_UINT32 cbs)
+DPP_STATUS dpp_se_shape_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 se_id,
+							ZXIC_UINT32 pir, ZXIC_UINT32 pbs, ZXIC_UINT32 db_en,
+							ZXIC_UINT32 cir, ZXIC_UINT32 cbs)
 {
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
 
-    ret = dpp_tm_shape_se_para_set(&dev, se_id, pir, pbs, db_en, cir, cbs);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_shape_se_para_set");
+	ret = dpp_tm_shape_se_para_set(&dev, se_id, pir, pbs, db_en, cir, cbs);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_shape_se_para_set");
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_se_shape_set);
 
@@ -466,24 +503,27 @@ EXPORT_SYMBOL(dpp_se_shape_set);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_flow_shape_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 flow_id, ZXIC_UINT32 cir, ZXIC_UINT32 cbs,
-                              ZXIC_UINT32 db_en, ZXIC_UINT32 eir, ZXIC_UINT32 ebs)
+DPP_STATUS dpp_flow_shape_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 flow_id,
+							  ZXIC_UINT32 cir, ZXIC_UINT32 cbs,
+							  ZXIC_UINT32 db_en, ZXIC_UINT32 eir,
+							  ZXIC_UINT32 ebs)
 {
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
 
-    ret = dpp_tm_shape_flow_para_set(&dev, flow_id, cir, cbs, db_en, eir, ebs);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_shape_flow_para_set");
+	ret = dpp_tm_shape_flow_para_set(&dev, flow_id, cir, cbs, db_en, eir, ebs);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_shape_flow_para_set");
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_flow_shape_set);
 
@@ -497,23 +537,25 @@ EXPORT_SYMBOL(dpp_flow_shape_set);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_flow_map_port_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 flow_id, ZXIC_UINT32 port)
+DPP_STATUS dpp_flow_map_port_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 flow_id,
+								 ZXIC_UINT32 port)
 {
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
 
-    ret = dpp_tm_cgavd_q_map_pp_set(&dev, flow_id, port);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_cgavd_q_map_pp_set");
+	ret = dpp_tm_cgavd_q_map_pp_set(&dev, flow_id, port);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_cgavd_q_map_pp_set");
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_flow_map_port_set);
 
@@ -527,26 +569,28 @@ EXPORT_SYMBOL(dpp_flow_map_port_set);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_flow_map_port_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 flow_id, ZXIC_UINT32 *p_port)
+DPP_STATUS dpp_flow_map_port_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 flow_id,
+								 ZXIC_UINT32 *p_port)
 {
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 pp_id  = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 pp_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
 
-    ret = dpp_tm_cgavd_q_map_pp_get(&dev, flow_id, &pp_id);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_cgavd_q_map_pp_get");
+	ret = dpp_tm_cgavd_q_map_pp_get(&dev, flow_id, &pp_id);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_cgavd_q_map_pp_get");
 
-    *p_port = pp_id;
+	*p_port = pp_id;
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_flow_map_port_get);
 
@@ -560,23 +604,25 @@ EXPORT_SYMBOL(dpp_flow_map_port_get);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_flow_td_th_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 flow_id, ZXIC_UINT32 td_th)
+DPP_STATUS dpp_flow_td_th_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 flow_id,
+							  ZXIC_UINT32 td_th)
 {
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
 
-    ret = dpp_tm_cgavd_td_th_set(&dev, QUEUE_LEVEL, flow_id, td_th);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_cgavd_td_th_set");
+	ret = dpp_tm_cgavd_td_th_set(&dev, QUEUE_LEVEL, flow_id, td_th);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_cgavd_td_th_set");
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_flow_td_th_set);
 
@@ -590,54 +636,57 @@ EXPORT_SYMBOL(dpp_flow_td_th_set);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_flow_td_th_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 flow_id, ZXIC_UINT32 *p_td_th)
+DPP_STATUS dpp_flow_td_th_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 flow_id,
+							  ZXIC_UINT32 *p_td_th)
 {
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 td_th  = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 td_th = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
 
-    ret = dpp_tm_cgavd_td_th_get(&dev, QUEUE_LEVEL, flow_id, &td_th);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_cgavd_td_th_get");
+	ret = dpp_tm_cgavd_td_th_get(&dev, QUEUE_LEVEL, flow_id, &td_th);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_cgavd_td_th_get");
 
-    *p_td_th = td_th;
+	*p_td_th = td_th;
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_flow_td_th_get);
 
 /***********************************************************/
 /**对外接口  设置block值
-* @param   vport_id  vport号
-* @param   size   配置block值      
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_blk_size_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 size)
+ * @param   vport_id  vport号
+ * @param   size   配置block值
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_blk_size_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 size)
 {
-    DPP_STATUS ret  = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ret = dpp_tm_cfgmt_blk_size_set(&dev, size);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, ret, "dpp_tm_cfgmt_blk_size_set");
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ret = dpp_tm_cfgmt_blk_size_set(&dev, size);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, ret, "dpp_tm_cfgmt_blk_size_set");
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_blk_size_set);
 
@@ -650,24 +699,25 @@ EXPORT_SYMBOL(dpp_blk_size_set);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_qmu_pfc_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 pfc_en)
+DPP_STATUS dpp_qmu_pfc_en_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 pfc_en)
 {
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pfc_en, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pfc_en, 0, 1);
 
-    ret = dpp_tm_qmu_pfc_en_set(&dev, pfc_en);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_qmu_pfc_en_set");
+	ret = dpp_tm_qmu_pfc_en_set(&dev, pfc_en);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_qmu_pfc_en_set");
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_qmu_pfc_en_set);
 
@@ -680,27 +730,28 @@ EXPORT_SYMBOL(dpp_qmu_pfc_en_set);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_qmu_pfc_en_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *p_pfc_en)
+DPP_STATUS dpp_qmu_pfc_en_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 *p_pfc_en)
 {
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 pfc_en = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 pfc_en = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pfc_en, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pfc_en, 0, 1);
 
-    ret = dpp_tm_qmu_pfc_en_get(&dev, &pfc_en);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_qmu_pfc_en_set");
+	ret = dpp_tm_qmu_pfc_en_get(&dev, &pfc_en);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_qmu_pfc_en_set");
 
-    *p_pfc_en = pfc_en;
+	*p_pfc_en = pfc_en;
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_qmu_pfc_en_get);
 
@@ -714,25 +765,27 @@ EXPORT_SYMBOL(dpp_qmu_pfc_en_get);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_qmu_port_pfc_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port_id, ZXIC_UINT32 port_en)
+DPP_STATUS dpp_qmu_port_pfc_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 port_id,
+								ZXIC_UINT32 port_en)
 {
-    DPP_STATUS ret     = DPP_OK;
-    DPP_DEV_T dev      = {0};
-    ZXIC_UINT32 dev_id = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_en, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_en, 0, 1);
 
-    ret = dpp_tm_qmu_port_pfc_make_set(&dev, port_id, port_en);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_qmu_port_pfc_make_set");
+	ret = dpp_tm_qmu_port_pfc_make_set(&dev, port_id, port_en);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_qmu_port_pfc_make_set");
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_qmu_port_pfc_set);
 
@@ -746,355 +799,360 @@ EXPORT_SYMBOL(dpp_qmu_port_pfc_set);
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_qmu_port_pfc_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port_id, ZXIC_UINT32 *p_port_en)
+DPP_STATUS dpp_qmu_port_pfc_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 port_id,
+								ZXIC_UINT32 *p_port_en)
 {
-    DPP_STATUS ret      = DPP_OK;
-    DPP_DEV_T dev       = {0};
-    ZXIC_UINT32 dev_id  = 0;
-    ZXIC_UINT32 port_en = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 port_en = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1);
 
-    ret = dpp_tm_qmu_port_pfc_make_get(&dev, port_id, &port_en);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_tm_qmu_port_pfc_make_get");
+	ret = dpp_tm_qmu_port_pfc_make_get(&dev, port_id, &port_en);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_tm_qmu_port_pfc_make_get");
 
-    *p_port_en = port_en;
+	*p_port_en = port_en;
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_qmu_port_pfc_get);
 
-
 /***********************************************************/
 /**对外接口  申请profile_id资源
-* @param   vport_id    vport号
-* @param   flags       car类型
-* @param   p_profile_id  限速模版号   
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_car_profile_id_add(DPP_PF_INFO_T* pf_info,
-                                  ZXIC_UINT32 flags,
-                                  ZXIC_UINT64 *p_profile_id)
+ * @param   vport_id    vport号
+ * @param   flags       car类型
+ * @param   p_profile_id  限速模版号
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_car_profile_id_add(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 flags,
+								  ZXIC_UINT64 *p_profile_id)
 {
-    DPP_STATUS ret         = DPP_OK;
-    DPP_DEV_T dev          = {0};
-    ZXIC_UINT32 dev_id     = 0;
-    ZXIC_UINT32 *profile_id = ZXIC_NULL;
-    ZXIC_UINT32 profile_id_h = 0;
-    ZXIC_UINT32 profile_id_l = 0;
-    ZXIC_UINT64 temp_profile_id    = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 *profile_id = ZXIC_NULL;
+	ZXIC_UINT32 profile_id_h = 0;
+	ZXIC_UINT32 profile_id_l = 0;
+	ZXIC_UINT64 temp_profile_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    profile_id = (ZXIC_UINT32 *)kmalloc(G_PROFILE_ID_LEN, GFP_KERNEL);
-    ZXIC_COMM_CHECK_POINT(profile_id);
+	profile_id = (ZXIC_UINT32 *)kmalloc(G_PROFILE_ID_LEN, GFP_KERNEL);
+	ZXIC_COMM_CHECK_POINT(profile_id);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_dev_get", profile_id);
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_dev_get", profile_id);
 
-    ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX, profile_id);
-    ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, flags, 0, CAR_TYPE_MAX, profile_id);
+	ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(
+			dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX, profile_id);
+	ZXIC_COMM_CHECK_DEV_INDEX_MEMORY_FREE_NO_ASSERT(dev_id, flags, 0,
+													CAR_TYPE_MAX, profile_id);
 
-    ret = dpp_agent_channel_plcr_profileid_request(&dev, pf_info->vport, flags, profile_id);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE(ret, "dpp_agent_channel_plcr_profileid_request", profile_id);
+	ret = dpp_agent_channel_plcr_profileid_request(&dev, pf_info->vport, flags,
+												   profile_id);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE(
+			ret, "dpp_agent_channel_plcr_profileid_request", profile_id);
 
-    profile_id_h = *(profile_id + 1);
-    profile_id_l = *profile_id;
+	profile_id_h = *(profile_id + 1);
+	profile_id_l = *profile_id;
 
-    temp_profile_id = ((ZXIC_UINT64)profile_id_l) << 32 | ((ZXIC_UINT64)profile_id_h);
+	temp_profile_id = ((ZXIC_UINT64)profile_id_l) << 32 |
+					  ((ZXIC_UINT64)profile_id_h);
 
-    if (DPP_OK != (ZXIC_UINT32)(temp_profile_id >> 56))
-    {
-        kfree(profile_id);
-        return DPP_ERR;
-    }
+	if (DPP_OK != (ZXIC_UINT32)(temp_profile_id >> 56)) {
+		kfree(profile_id);
+		return DPP_ERR;
+	}
 
-    *p_profile_id = temp_profile_id;
-    kfree(profile_id);
+	*p_profile_id = temp_profile_id;
+	kfree(profile_id);
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_car_profile_id_add);
 
 /***********************************************************/
 /**对外接口  释放profile_id资源
-* @param   vport_id    vport号
-* @param   flags       car类型
-* @param   profile_id  限速模版号  
+ * @param   vport_id    vport号
+ * @param   flags       car类型
+ * @param   profile_id  限速模版号
  * @return
  * @remark  无
  * @see
  * @author  sun      @date  2023/11/17
  ************************************************************/
-DPP_STATUS dpp_car_profile_id_delete(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 flags, ZXIC_UINT64 profile_id)
+DPP_STATUS dpp_car_profile_id_delete(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 flags,
+									 ZXIC_UINT64 profile_id)
 {
-    DPP_STATUS ret         = DPP_OK;
-    DPP_DEV_T dev          = {0};
-    ZXIC_UINT32 dev_id     = 0;
-    ZXIC_UINT32 profileid     = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 profileid = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    DPP_CAR_PROFILE_ID_GET(profile_id, profileid);
+	DPP_CAR_PROFILE_ID_GET(profile_id, profileid);
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, flags, 0, CAR_TYPE_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, flags, 0, CAR_TYPE_MAX);
 
-    ret = dpp_agent_channel_plcr_profileid_release(&dev, pf_info->vport, flags, profileid);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_agent_channel_plcr_profileid_release");
+	ret = dpp_agent_channel_plcr_profileid_release(&dev, pf_info->vport, flags,
+												   profileid);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_agent_channel_plcr_profileid_release");
 
-    // if (DPP_OK != ret)
-    // {
-    //     return DPP_ERR;
-    // }
+	if (DPP_OK != ret) {
+		return DPP_ERR;
+	}
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_car_profile_id_delete);
 
 /***********************************************************/
 /**对外接口 配置flow_id和profile_id的绑定关系，并配置限速模板使能
-* @param   vport_id     vport号
-* @param   car_type     car模式
-* @param   flow_id      队列号
-* @param   drop_flag    丢弃标志
-* @param   plcr_en      限速使能
-* @param   profile_id   模板编号
-*
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_car_queue_cfg_set(DPP_PF_INFO_T* pf_info,
-                                 ZXIC_UINT32 car_type,
-                                 ZXIC_UINT32 flow_id,
-                                 ZXIC_UINT32 drop_flag,
-                                 ZXIC_UINT32 plcr_en,
-                                 ZXIC_UINT32 profile_id)
+ * @param   vport_id     vport号
+ * @param   car_type     car模式
+ * @param   flow_id      队列号
+ * @param   drop_flag    丢弃标志
+ * @param   plcr_en      限速使能
+ * @param   profile_id   模板编号
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_car_queue_cfg_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 car_type,
+								 ZXIC_UINT32 flow_id, ZXIC_UINT32 drop_flag,
+								 ZXIC_UINT32 plcr_en, ZXIC_UINT32 profile_id)
 {
-    DPP_STATUS ret         = DPP_OK;
-    DPP_DEV_T dev          = {0};
-    ZXIC_UINT32 dev_id     = 0;
-
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ret = dpp_stat_car_queue_cfg_set(&dev, car_type, flow_id, drop_flag, plcr_en, profile_id);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_queue_cfg_set");
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
 
-    return ret;
+	ret = dpp_stat_car_queue_cfg_set(&dev, car_type, flow_id, drop_flag,
+									 plcr_en, profile_id);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_queue_cfg_set");
 
+	return ret;
 }
 EXPORT_SYMBOL(dpp_car_queue_cfg_set);
 
 /***********************************************************/
 /**对外接口 查询flow_id和profile_id的绑定关系
-* @param   vport_id     vport号
-* @param   car_type     car模式
-* @param   flow_id      队列号
-* @param   p_drop_flag    丢弃标志
-* @param   p_plcr_en      限速使能
-* @param   p_profile_id   模板编号
-*
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_car_queue_cfg_get(DPP_PF_INFO_T* pf_info,
-                                 ZXIC_UINT32 car_type,
-                                 ZXIC_UINT32 flow_id,
-                                 ZXIC_UINT32 *p_drop_flag,
-                                 ZXIC_UINT32 *p_plcr_en,
-                                 ZXIC_UINT32 *p_profile_id)
+ * @param   vport_id     vport号
+ * @param   car_type     car模式
+ * @param   flow_id      队列号
+ * @param   p_drop_flag    丢弃标志
+ * @param   p_plcr_en      限速使能
+ * @param   p_profile_id   模板编号
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_car_queue_cfg_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 car_type,
+								 ZXIC_UINT32 flow_id, ZXIC_UINT32 *p_drop_flag,
+								 ZXIC_UINT32 *p_plcr_en,
+								 ZXIC_UINT32 *p_profile_id)
 {
-    DPP_STATUS ret         = DPP_OK;
-    DPP_DEV_T dev          = {0};
-    ZXIC_UINT32 dev_id     = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_CHECK_DEV_POINT(0, p_drop_flag);
-    ZXIC_COMM_CHECK_DEV_POINT(0, p_plcr_en);
-    ZXIC_COMM_CHECK_DEV_POINT(0, p_profile_id);
+	ZXIC_COMM_CHECK_DEV_POINT(0, p_drop_flag);
+	ZXIC_COMM_CHECK_DEV_POINT(0, p_plcr_en);
+	ZXIC_COMM_CHECK_DEV_POINT(0, p_profile_id);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
 
-    ret = dpp_stat_car_queue_cfg_get(&dev, car_type, flow_id, p_drop_flag, p_plcr_en, p_profile_id);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_queue_cfg_get");
+	ret = dpp_stat_car_queue_cfg_get(&dev, car_type, flow_id, p_drop_flag,
+									 p_plcr_en, p_profile_id);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_queue_cfg_get");
 
-    return ret;
+	return ret;
 }
 EXPORT_SYMBOL(dpp_car_queue_cfg_get);
 
 /***********************************************************/
 /**对外接口 配置profile_id限速模版
-* @param   dev_id      
-* @param   car_type   
-* @param   pkt_sign   
-* @param   profile_id   
-* @param   p_car_profile_cfg   
-*
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_car_profile_cfg_set(DPP_PF_INFO_T* pf_info,
-                                   ZXIC_UINT32 car_type,
-                                   ZXIC_UINT32 pkt_sign,
-                                   ZXIC_UINT32 profile_id,
-                                   ZXIC_VOID* p_car_profile_cfg)
+ * @param   dev_id
+ * @param   car_type
+ * @param   pkt_sign
+ * @param   profile_id
+ * @param   p_car_profile_cfg
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_car_profile_cfg_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 car_type,
+								   ZXIC_UINT32 pkt_sign, ZXIC_UINT32 profile_id,
+								   ZXIC_VOID *p_car_profile_cfg)
 {
-    DPP_STATUS ret         = DPP_OK;
-    DPP_DEV_T dev          = {0};
-    ZXIC_UINT32 dev_id     = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_profile_cfg);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_profile_cfg);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
 
-    ret = dpp_stat_car_profile_cfg_set(&dev, car_type, pkt_sign, profile_id, p_car_profile_cfg);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_queue_cfg_set");
+	ret = dpp_stat_car_profile_cfg_set(&dev, car_type, pkt_sign, profile_id,
+									   p_car_profile_cfg);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_queue_cfg_set");
 
-    return ret;   
+	return ret;
 }
 EXPORT_SYMBOL(dpp_car_profile_cfg_set);
 
 /***********************************************************/
 /**对外接口 查询profile_id限速模版参数
-* @param   vport_id     vport号      
-* @param   car_type     car模式
-* @param   pkt_sign     限速模式0-字节;1-包
-* @param   profile_id   模板编号
-* @param   p_car_profile_cfg   限速参数
-*
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_car_profile_cfg_get(DPP_PF_INFO_T* pf_info,
-                                   ZXIC_UINT32 car_type,
-                                   ZXIC_UINT32 pkt_sign,
-                                   ZXIC_UINT32 profile_id,
-                                   ZXIC_VOID* p_car_profile_cfg)
+ * @param   vport_id     vport号
+ * @param   car_type     car模式
+ * @param   pkt_sign     限速模式0-字节;1-包
+ * @param   profile_id   模板编号
+ * @param   p_car_profile_cfg   限速参数
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_car_profile_cfg_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 car_type,
+								   ZXIC_UINT32 pkt_sign, ZXIC_UINT32 profile_id,
+								   ZXIC_VOID *p_car_profile_cfg)
 {
-    DPP_STATUS ret         = DPP_OK;
-    DPP_DEV_T dev          = {0};
-    ZXIC_UINT32 dev_id     = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_profile_cfg);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_profile_cfg);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
 
-    ret = dpp_stat_car_profile_cfg_get(&dev, car_type, pkt_sign, profile_id, p_car_profile_cfg);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_profile_cfg_get");
+	ret = dpp_stat_car_profile_cfg_get(&dev, car_type, pkt_sign, profile_id,
+									   p_car_profile_cfg);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_profile_cfg_get");
 
-    return ret;      
+	return ret;
 }
 EXPORT_SYMBOL(dpp_car_profile_cfg_get);
 
 /***********************************************************/
 /**对外接口 配置队列映射关系
-* @param   dev_id       设备号
-* @param   car_type     car模式类型，参见STAT_CAR_TYPE_E
-* @param   flow_id      队列号
-* @param   map_flow_id  映射队列号
-* @param   map_sp       映射sp
-*
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_car_queue_map_set(DPP_PF_INFO_T* pf_info,
-                                 ZXIC_UINT32 car_type,
-                                 ZXIC_UINT32 flow_id,
-                                 ZXIC_UINT32 map_flow_id,
-                                 ZXIC_UINT32 map_sp)
+ * @param   dev_id       设备号
+ * @param   car_type     car模式类型，参见STAT_CAR_TYPE_E
+ * @param   flow_id      队列号
+ * @param   map_flow_id  映射队列号
+ * @param   map_sp       映射sp
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_car_queue_map_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 car_type,
+								 ZXIC_UINT32 flow_id, ZXIC_UINT32 map_flow_id,
+								 ZXIC_UINT32 map_sp)
 {
-    DPP_STATUS ret         = DPP_OK;
-    DPP_DEV_T dev          = {0};
-    ZXIC_UINT32 dev_id     = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
 
-    ret = dpp_stat_car_queue_map_set(&dev, car_type, flow_id, map_flow_id, map_sp);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_queue_map_set");
+	ret = dpp_stat_car_queue_map_set(&dev, car_type, flow_id, map_flow_id,
+									 map_sp);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_queue_map_set");
 
-    return ret;  
+	return ret;
 }
 EXPORT_SYMBOL(dpp_car_queue_map_set);
 
 /***********************************************************/
 /**对外接口 配置队列映射关系
-* @param   dev_id       设备号
-* @param   car_type     car模式类型，参见STAT_CAR_TYPE_E
-* @param   flow_id      队列号
-* @param   map_flow_id  映射队列号
-* @param   map_sp       映射sp
-*
-* @return
-* @remark  无
-* @see
-* @author  sun      @date  2023/11/17
-************************************************************/
-DPP_STATUS dpp_car_queue_map_get(DPP_PF_INFO_T* pf_info,
-                                 ZXIC_UINT32 car_type,
-                                 ZXIC_UINT32 flow_id,
-                                 ZXIC_UINT32 *p_map_flow_id,
-                                 ZXIC_UINT32 *p_map_sp)
+ * @param   dev_id       设备号
+ * @param   car_type     car模式类型，参见STAT_CAR_TYPE_E
+ * @param   flow_id      队列号
+ * @param   map_flow_id  映射队列号
+ * @param   map_sp       映射sp
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/11/17
+ ************************************************************/
+DPP_STATUS dpp_car_queue_map_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 car_type,
+								 ZXIC_UINT32 flow_id,
+								 ZXIC_UINT32 *p_map_flow_id,
+								 ZXIC_UINT32 *p_map_sp)
 {
-    DPP_STATUS ret         = DPP_OK;
-    DPP_DEV_T dev          = {0};
-    ZXIC_UINT32 dev_id     = 0;
+	DPP_STATUS ret = DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ret = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
+	ret = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_dev_get");
 
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_map_flow_id);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_map_sp);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0, DPP_VPORT_NUM_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_map_flow_id);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_map_sp);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pf_info->vport, 0,
+										DPP_VPORT_NUM_MAX);
 
-    ret = dpp_stat_car_queue_map_get(&dev, car_type, flow_id, p_map_flow_id, p_map_sp);
-    ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_queue_map_get");
+	ret = dpp_stat_car_queue_map_get(&dev, car_type, flow_id, p_map_flow_id,
+									 p_map_sp);
+	ZXIC_COMM_CHECK_RC(ret, "dpp_stat_car_queue_map_get");
 
-    return ret;  
+	return ret;
 }
 EXPORT_SYMBOL(dpp_car_queue_map_get);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_apt_se_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_apt_se_api.h
index 8094f4a0aef5370bc5a9097daaca8e307dce9728..9356a671d50405b4e615aec85f3d8f76d12537ae 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_apt_se_api.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_apt_se_api.h
@@ -1,19 +1,19 @@
 /**************************************************************
 * 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
 * 文件名称 : dpp_apt_se_api.h
-* 文件标识 : 
+* 文件标识 :
 * 内容摘要 : SE适配业务接口数据结构和函数声明
-* 其它说明 : 
-* 当前版本 : 
+* 其它说明 :
+* 当前版本 :
 * 作    者 : chenqin00181032
 * 完成日期 : 2022/02/22
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* 版 本 号:  
-* 修 改 人:  
-* 修改内容:  
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
 ***************************************************************/
 
 #ifndef _DPP_APT_SE_API_H_
@@ -28,87 +28,99 @@
 #include "dpp_se.h"
 #endif
 
-
 #if ZXIC_REAL("data struct define")
-typedef ZXIC_UINT32 (*DPP_APT_ACL_ENTRY_SET_FUNC)(ZXIC_VOID *pData,DPP_ACL_ENTRY_EX_T *aclEntry);
-typedef ZXIC_UINT32 (*DPP_APT_ACL_ENTRY_GET_FUNC)(ZXIC_VOID *pData,DPP_ACL_ENTRY_EX_T *aclEntry);
-
-typedef ZXIC_UINT32 (*DPP_APT_ERAM_SET_FUNC)(ZXIC_VOID *pData,ZXIC_UINT32 buf[4]);
-typedef ZXIC_UINT32 (*DPP_APT_ERAM_GET_FUNC)(ZXIC_VOID *pData,ZXIC_UINT32 buf[4]);
-
-typedef ZXIC_UINT32 (*DPP_APT_HASH_ENTRY_SET_FUNC)(ZXIC_VOID *pData,DPP_HASH_ENTRY *pEntry);
-typedef ZXIC_UINT32 (*DPP_APT_HASH_ENTRY_GET_FUNC)(ZXIC_VOID *pData,DPP_HASH_ENTRY *pEntry);
-
-typedef ZXIC_UINT32 (*DPP_APT_LPM_ENTRY_SET_FUNC)(ZXIC_VOID *pData,ZXIC_VOID *pEntry);
-typedef ZXIC_UINT32 (*DPP_APT_LPM_ENTRY_GET_FUNC)(ZXIC_VOID *pData,ZXIC_VOID *pEntry);
-
-typedef ZXIC_UINT32 (*DPP_APT_DDR_SET_FUNC)(ZXIC_VOID *pData,ZXIC_UINT32 buf[DPP_DIR_TBL_BUF_MAX_NUM]);
-typedef ZXIC_UINT32 (*DPP_APT_DDR_GET_FUNC)(ZXIC_VOID *pData,ZXIC_UINT32 buf[DPP_DIR_TBL_BUF_MAX_NUM]);
-
-typedef struct dpp_apt_eram_table_t
-{
-    ZXIC_UINT32 sdtNo;          /** <@brief sdt no 0~255 */
-    DPP_SDTTBL_ERAM_T eRamSdt; /** <@brief eRam属性*/
-    ZXIC_UINT32 opr_mode;     /**cpu读写位宽模式DPP_ERAM128_OPR_MODE_E 0:128b 1:64b 2:1b 3:32b <@*/
-    ZXIC_UINT32 rd_mode;      /*读清模式DPP_ERAM128_RD_CLR_MODE_E，0:正常读 1:读清模式*/
-    DPP_APT_ERAM_SET_FUNC  eram_set_func;   /** <@brief 结构体转换为码流 */
-    DPP_APT_ERAM_GET_FUNC  eram_get_func;   /** <@brief 码流转换为结构体 */
+typedef ZXIC_UINT32 (*DPP_APT_ACL_ENTRY_SET_FUNC)(ZXIC_VOID *pData,
+												  DPP_ACL_ENTRY_EX_T *aclEntry);
+typedef ZXIC_UINT32 (*DPP_APT_ACL_ENTRY_GET_FUNC)(ZXIC_VOID *pData,
+												  DPP_ACL_ENTRY_EX_T *aclEntry);
+
+typedef ZXIC_UINT32 (*DPP_APT_ERAM_SET_FUNC)(ZXIC_VOID *pData,
+											 ZXIC_UINT32 buf[4]);
+typedef ZXIC_UINT32 (*DPP_APT_ERAM_GET_FUNC)(ZXIC_VOID *pData,
+											 ZXIC_UINT32 buf[4]);
+
+typedef ZXIC_UINT32 (*DPP_APT_HASH_ENTRY_SET_FUNC)(ZXIC_VOID *pData,
+												   DPP_HASH_ENTRY *pEntry);
+typedef ZXIC_UINT32 (*DPP_APT_HASH_ENTRY_GET_FUNC)(ZXIC_VOID *pData,
+												   DPP_HASH_ENTRY *pEntry);
+
+typedef ZXIC_UINT32 (*DPP_APT_LPM_ENTRY_SET_FUNC)(ZXIC_VOID *pData,
+												  ZXIC_VOID *pEntry);
+typedef ZXIC_UINT32 (*DPP_APT_LPM_ENTRY_GET_FUNC)(ZXIC_VOID *pData,
+												  ZXIC_VOID *pEntry);
+
+typedef ZXIC_UINT32 (*DPP_APT_DDR_SET_FUNC)(
+		ZXIC_VOID *pData, ZXIC_UINT32 buf[DPP_DIR_TBL_BUF_MAX_NUM]);
+typedef ZXIC_UINT32 (*DPP_APT_DDR_GET_FUNC)(
+		ZXIC_VOID *pData, ZXIC_UINT32 buf[DPP_DIR_TBL_BUF_MAX_NUM]);
+
+typedef struct dpp_apt_eram_table_t {
+	ZXIC_UINT32 sdtNo; /** <@brief sdt no 0~255 */
+	DPP_SDTTBL_ERAM_T eRamSdt; /** <@brief eRam属性*/
+	ZXIC_UINT32
+	opr_mode; /**cpu读写位宽模式DPP_ERAM128_OPR_MODE_E 0:128b 1:64b 2:1b 3:32b <@*/
+	ZXIC_UINT32
+	rd_mode; /*读清模式DPP_ERAM128_RD_CLR_MODE_E，0:正常读 1:读清模式*/
+	DPP_APT_ERAM_SET_FUNC eram_set_func; /** <@brief 结构体转换为码流 */
+	DPP_APT_ERAM_GET_FUNC eram_get_func; /** <@brief 码流转换为结构体 */
 } DPP_APT_ERAM_TABLE_T;
 
-typedef struct dpp_apt_ddr_table_t
-{
-    ZXIC_UINT32 sdtNo;          /** <@brief sdt no 0~255 */
-    DPP_SDTTBL_DDR3_T eDdrSdt;  /** <@brief DDR属性*/
-    ZXIC_UINT32 ddr_table_depth;/** <@brief DDR表项深度，单位与读写模式一致*/
-    DPP_APT_DDR_SET_FUNC  ddr_set_func;     /** <@brief 结构体转换为码流 */
-    DPP_APT_DDR_GET_FUNC  ddr_get_func;     /** <@brief 码流转换为结构体 */
+typedef struct dpp_apt_ddr_table_t {
+	ZXIC_UINT32 sdtNo; /** <@brief sdt no 0~255 */
+	DPP_SDTTBL_DDR3_T eDdrSdt; /** <@brief DDR属性*/
+	ZXIC_UINT32 ddr_table_depth; /** <@brief DDR表项深度，单位与读写模式一致*/
+	DPP_APT_DDR_SET_FUNC ddr_set_func; /** <@brief 结构体转换为码流 */
+	DPP_APT_DDR_GET_FUNC ddr_get_func; /** <@brief 码流转换为结构体 */
 } DPP_APT_DDR_TABLE_T;
 
-typedef struct dpp_apt_acl_res_t
-{
-    ZXIC_UINT32 pri_mode;      /** <@brief1：显式优先级，2：隐式优先级，以条目下发顺序作为优先级，3：用户指定每个条目在tcam中的存放索引*/
-    ZXIC_UINT32 entry_num;      /** <@brief 可配置的条目数*/
-    ZXIC_UINT32 block_num;      /** <@brief  最大8个 */
-    ZXIC_UINT32 block_index[DPP_ETCAM_BLOCK_NUM]; /** <@brief  0~7 */
+typedef struct dpp_apt_acl_res_t {
+	ZXIC_UINT32
+	pri_mode; /** <@brief1：显式优先级，2：隐式优先级，以条目下发顺序作为优先级，3：用户指定每个条目在tcam中的存放索引*/
+	ZXIC_UINT32 entry_num; /** <@brief 可配置的条目数*/
+	ZXIC_UINT32 block_num; /** <@brief  最大8个 */
+	ZXIC_UINT32 block_index[DPP_ETCAM_BLOCK_NUM]; /** <@brief  0~7 */
 } DPP_APT_ACL_RES_T;
 
-typedef struct dpp_apt_acl_table_t
-{
-    ZXIC_UINT32 sdtNo;          /** <@brief sdt no 0~255 */
-    DPP_SDTTBL_ETCAM_T aclSdt;  /** <@brief acl属性*/
-    DPP_APT_ACL_RES_T aclRes;   /** <@brief acl资源*/
-    DPP_APT_ACL_ENTRY_SET_FUNC  acl_set_func;  /** <@brief 结构体转换为码流 */
-    DPP_APT_ACL_ENTRY_GET_FUNC  acl_get_func;  /** <@brief 码流转换为结构体 */
+typedef struct dpp_apt_acl_table_t {
+	ZXIC_UINT32 sdtNo; /** <@brief sdt no 0~255 */
+	DPP_SDTTBL_ETCAM_T aclSdt; /** <@brief acl属性*/
+	DPP_APT_ACL_RES_T aclRes; /** <@brief acl资源*/
+	DPP_APT_ACL_ENTRY_SET_FUNC acl_set_func; /** <@brief 结构体转换为码流 */
+	DPP_APT_ACL_ENTRY_GET_FUNC acl_get_func; /** <@brief 码流转换为结构体 */
 } DPP_APT_ACL_TABLE_T;
 
-typedef struct dpp_apt_hash_table_t
-{
-    ZXIC_UINT32 sdtNo;          /** <@brief sdt no 0~255 */
-    DPP_SDTTBL_HASH_T hashSdt;  /** <@brief hash sdt属性*/
-    ZXIC_UINT32 tbl_flag;       /**<  @brief 业务表初始化标记（bit0：老化保活置位使能，bit1：硬件学习使能，bit2：微码写表使能）*/
-    DPP_APT_HASH_ENTRY_SET_FUNC hash_set_func;  /** <@brief 结构体转换为码流,转换时预留一个字节，从第1字节开始填充 */
-    DPP_APT_HASH_ENTRY_GET_FUNC hash_get_func;  /** <@brief 码流转换为结构体 */
+typedef struct dpp_apt_hash_table_t {
+	ZXIC_UINT32 sdtNo; /** <@brief sdt no 0~255 */
+	DPP_SDTTBL_HASH_T hashSdt; /** <@brief hash sdt属性*/
+	ZXIC_UINT32
+	tbl_flag; /**<  @brief 业务表初始化标记（bit0：老化保活置位使能，bit1：硬件学习使能，bit2：微码写表使能）*/
+	DPP_APT_HASH_ENTRY_SET_FUNC
+	hash_set_func; /** <@brief 结构体转换为码流,转换时预留一个字节，从第1字节开始填充 */
+	DPP_APT_HASH_ENTRY_GET_FUNC hash_get_func; /** <@brief 码流转换为结构体 */
 } DPP_APT_HASH_TABLE_T;
 
-typedef struct dpp_apt_hash_func_res_t
-{
-   ZXIC_UINT32 func_id;        /**<  @brief hash引擎id 0~3*/
-   ZXIC_UINT32 zblk_num;       /**<  @brief 0~32*/
-   ZXIC_UINT32 zblk_bitmap;    /**<  @brief 置1的bit位表示分配的block编号 */
-   ZXIC_UINT32 ddr_dis;        /** <@brief 0:混合模式，1：纯片内模式*/
+typedef struct dpp_apt_hash_func_res_t {
+	ZXIC_UINT32 func_id; /**<  @brief hash引擎id 0~3*/
+	ZXIC_UINT32 zblk_num; /**<  @brief 0~32*/
+	ZXIC_UINT32 zblk_bitmap; /**<  @brief 置1的bit位表示分配的block编号 */
+	ZXIC_UINT32 ddr_dis; /** <@brief 0:混合模式，1：纯片内模式*/
 } DPP_APT_HASH_FUNC_RES_T;
 
-typedef struct dpp_apt_hash_bulk_res_t
-{
-    ZXIC_UINT32 func_id;                     /**<  @brief 0~3*/
-    ZXIC_UINT32 bulk_id;                     /**<  @brief 0~7*/
-    ZXIC_UINT32 zcell_num;                   /**<  @brief 0~128*/
-    ZXIC_UINT32 zreg_num;                    /**<  @brief 0~128*/
-    ZXIC_UINT32 ddr_baddr;                   /**<  @brief 分配给hash的DDR空间的硬件基地址,单位2k*256bit*/
-    ZXIC_UINT32 ddr_item_num;                /**<  @brief 分配给hash的DDR空间单元数目，以256bit为一个单元（根据分配的基地址和单元数目确定分配的DDR空间大小）*/
-    DPP_HASH_DDR_WIDTH_MODE ddr_width_mode;  /**<  @brief 分配给hash的DDR空间物理存储位宽模式，0:无效值，1:256bit 2:512bit*/
-    ZXIC_UINT32 ddr_crc_sel;                 /**<  @brief 选择一个DDR CRC多项式，取值范围0~3,0~3分别对应一个CRC多项式*/
-    ZXIC_UINT32 ddr_ecc_en;                  /**<  @brief DDR ECC使能: 0-不使能，1-使能*/
+typedef struct dpp_apt_hash_bulk_res_t {
+	ZXIC_UINT32 func_id; /**<  @brief 0~3*/
+	ZXIC_UINT32 bulk_id; /**<  @brief 0~7*/
+	ZXIC_UINT32 zcell_num; /**<  @brief 0~128*/
+	ZXIC_UINT32 zreg_num; /**<  @brief 0~128*/
+	ZXIC_UINT32
+	ddr_baddr; /**<  @brief 分配给hash的DDR空间的硬件基地址,单位2k*256bit*/
+	ZXIC_UINT32
+	ddr_item_num; /**<  @brief
+	分配给hash的DDR空间单元数目，以256bit为一个单元（根据分配的基地址和单元数目确定分配的DDR空间大小）*/
+	DPP_HASH_DDR_WIDTH_MODE
+	ddr_width_mode; /**<  @brief 分配给hash的DDR空间物理存储位宽模式，0:无效值，1:256bit 2:512bit*/
+	ZXIC_UINT32
+	ddr_crc_sel; /**<  @brief 选择一个DDR CRC多项式，取值范围0~3,0~3分别对应一个CRC多项式*/
+	ZXIC_UINT32 ddr_ecc_en; /**<  @brief DDR ECC使能: 0-不使能，1-使能*/
 } DPP_APT_HASH_BULK_RES_T;
 
 #define DTB_DUMP_UNICAST_MAC_DUMP_NUM (32 * 257)
@@ -119,184 +131,198 @@ typedef struct dpp_apt_hash_bulk_res_t
 
 /***********************************************************/
 /** eram表资源初始化
-* @param   dev_id  设备号 
-* @param   tbl_num  需初始化的eram表个数
-* @param   pEramTbl  eram资源信息，包括SDT配置信息，直接表读取位宽和结构体码流转换回调函数
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_eram_res_init(DPP_DEV_T *dev,ZXIC_UINT32 tbl_num,DPP_APT_ERAM_TABLE_T *pEramTbl);
+ * @param   dev_id  设备号
+ * @param   tbl_num  需初始化的eram表个数
+ * @param   pEramTbl  eram资源信息，包括SDT配置信息，直接表读取位宽和结构体码流转换回调函数
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_eram_res_init(DPP_DEV_T *dev, ZXIC_UINT32 tbl_num,
+								 DPP_APT_ERAM_TABLE_T *pEramTbl);
 
 /***********************************************************/
 /** DDR表资源初始化
-* @param   dev_id  设备号 
-* @param   tbl_num  需初始化的DDR表个数
-* @param   pDdrTbl  ddr资源信息，包括SDT配置信息，直接表读取位宽和结构体码流转换回调函数
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/07/26
-************************************************************/
-DPP_STATUS dpp_apt_ddr_res_init(DPP_DEV_T *dev,ZXIC_UINT32 tbl_num,DPP_APT_DDR_TABLE_T *pDdrTbl);
+ * @param   dev_id  设备号
+ * @param   tbl_num  需初始化的DDR表个数
+ * @param   pDdrTbl  ddr资源信息，包括SDT配置信息，直接表读取位宽和结构体码流转换回调函数
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/07/26
+ ************************************************************/
+DPP_STATUS dpp_apt_ddr_res_init(DPP_DEV_T *dev, ZXIC_UINT32 tbl_num,
+								DPP_APT_DDR_TABLE_T *pDdrTbl);
 
 /***********************************************************/
 /** acl资源初始化
-* @param   dev_id  设备号 
-* @param   tbl_num     etcam对应的sdt表个数
-* @param   pAclTblRes  acl表资源信息，包括SDT配置信息，acl资源(条目数，存放方式和占用的block)和结构体码流转换回调函数
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_acl_res_init(DPP_DEV_T *dev,ZXIC_UINT32 tbl_num,DPP_APT_ACL_TABLE_T *pAclTblRes);
+ * @param   dev_id  设备号
+ * @param   tbl_num     etcam对应的sdt表个数
+ * @param   pAclTblRes  acl表资源信息，包括SDT配置信息，acl资源(条目数，存放方式和占用的block)和结构体码流转换回调函数
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_acl_res_init(DPP_DEV_T *dev, ZXIC_UINT32 tbl_num,
+								DPP_APT_ACL_TABLE_T *pAclTblRes);
 
 /***********************************************************/
 /** hash表全局资源初始化
-* @param   dev_id  设备号 
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
+ * @param   dev_id  设备号
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
 DPP_STATUS dpp_apt_hash_global_res_init(DPP_DEV_T *dev);
 
 /***********************************************************/
 /** hash引擎初始化
-* @param   dev_id  设备号 
-* @param   func_num     需初始化的hash引擎个数 1~4
-* @param   pHashFuncRes  每个hash引擎分配的zblock个数和编号，以及分配模式(混合模式或者纯片内模式)
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_hash_func_res_init(ZXIC_UINT32 dev_id,ZXIC_UINT32 func_num,DPP_APT_HASH_FUNC_RES_T *pHashFuncRes);
+ * @param   dev_id  设备号
+ * @param   func_num     需初始化的hash引擎个数 1~4
+ * @param   pHashFuncRes  每个hash引擎分配的zblock个数和编号，以及分配模式(混合模式或者纯片内模式)
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_hash_func_res_init(ZXIC_UINT32 dev_id, ZXIC_UINT32 func_num,
+									  DPP_APT_HASH_FUNC_RES_T *pHashFuncRes);
 
 /***********************************************************/
 /** hash引擎初始化(删除硬件数据)
-* @param   dev_id  设备号 
-* @param   func_num     需初始化的hash引擎个数 1~4
-* @param   pHashFuncRes  每个hash引擎分配的zblock个数和编号，以及分配模式(混合模式或者纯片内模式)
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_hash_func_flush_hardware_all(DPP_DEV_T *dev, 
-                                            ZXIC_UINT32 func_num, 
-                                            DPP_APT_HASH_FUNC_RES_T *pHashFuncRes, 
-                                            ZXIC_UINT32 queue_id);
+ * @param   dev_id  设备号
+ * @param   func_num     需初始化的hash引擎个数 1~4
+ * @param   pHashFuncRes  每个hash引擎分配的zblock个数和编号，以及分配模式(混合模式或者纯片内模式)
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS
+dpp_apt_hash_func_flush_hardware_all(DPP_DEV_T *dev, ZXIC_UINT32 func_num,
+									 DPP_APT_HASH_FUNC_RES_T *pHashFuncRes,
+									 ZXIC_UINT32 queue_id);
 
 /***********************************************************/
 /** hash引擎bulk空间初始化
-* @param   dev_id  设备号 
-* @param   bulk_num     需初始化的bulk表个数 1~32
-* @param   pBulkRes  zcell和zreg资源占用信息，如果是混合模式，需进行DDR资源分配
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_hash_bulk_res_init(ZXIC_UINT32 dev_id,ZXIC_UINT32 bulk_num,DPP_APT_HASH_BULK_RES_T *pBulkRes);
+ * @param   dev_id  设备号
+ * @param   bulk_num     需初始化的bulk表个数 1~32
+ * @param   pBulkRes  zcell和zreg资源占用信息，如果是混合模式，需进行DDR资源分配
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_hash_bulk_res_init(ZXIC_UINT32 dev_id, ZXIC_UINT32 bulk_num,
+									  DPP_APT_HASH_BULK_RES_T *pBulkRes);
 
 /***********************************************************/
 /** hash业务表属性初始化
-* @param   dev_id  设备号 
-* @param   tbl_num     需初始化的业务表表个数 1~128
-* @param   pHashTbl  sdt配置信息，初始化标记和业务结构体码流转换函数
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_hash_tbl_res_init(DPP_DEV_T *dev,ZXIC_UINT32 tbl_num,DPP_APT_HASH_TABLE_T *pHashTbl);
+ * @param   dev_id  设备号
+ * @param   tbl_num     需初始化的业务表表个数 1~128
+ * @param   pHashTbl  sdt配置信息，初始化标记和业务结构体码流转换函数
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_hash_tbl_res_init(DPP_DEV_T *dev, ZXIC_UINT32 tbl_num,
+									 DPP_APT_HASH_TABLE_T *pHashTbl);
 
 /***********************************************************/
 /** dtb eram表项插入/更新
-* @param   dev_id  设备号 
-* @param   sdt_no  SDT号 0~255
-* @param   index   条目index，索引范围随wrt_mode模式不同
-* @param   pData   插入表项内容，由业务确定
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_dtb_eram_insert(DPP_DEV_T *dev,ZXIC_UINT32 queue_id,ZXIC_UINT32 sdt_no,ZXIC_UINT32 index,void *pData);
+ * @param   dev_id  设备号
+ * @param   sdt_no  SDT号 0~255
+ * @param   index   条目index，索引范围随wrt_mode模式不同
+ * @param   pData   插入表项内容，由业务确定
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_dtb_eram_insert(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								   ZXIC_UINT32 sdt_no, ZXIC_UINT32 index,
+								   void *pData);
 
 /***********************************************************/
 /** eram表项数据获取,从软件缓存中获取
-* @param   dev_id  设备号 
-* @param   sdt_no  SDT号 0~255
-* @param   index   条目index，索引范围随wrt_mode模式不同
-* @param   pData   出参，返回业务表项内容
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_dtb_eram_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 sdt_no, ZXIC_UINT32 index, void *pData);
+ * @param   dev_id  设备号
+ * @param   sdt_no  SDT号 0~255
+ * @param   index   条目index，索引范围随wrt_mode模式不同
+ * @param   pData   出参，返回业务表项内容
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_dtb_eram_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								ZXIC_UINT32 sdt_no, ZXIC_UINT32 index,
+								void *pData);
 
 /***********************************************************/
 /** eram表项删除,软件维护删除
-* @param   dev_id  设备号 
-* @param   sdt_no  SDT号 0~255
-* @param   index   条目index，索引范围随wrt_mode模式不同
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_dtb_eram_clear(DPP_DEV_T *dev,ZXIC_UINT32 queue_id,ZXIC_UINT32 sdt_no,ZXIC_UINT32 index);
+ * @param   dev_id  设备号
+ * @param   sdt_no  SDT号 0~255
+ * @param   index   条目index，索引范围随wrt_mode模式不同
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_dtb_eram_clear(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								  ZXIC_UINT32 sdt_no, ZXIC_UINT32 index);
 
 /***********************************************************/
 /** dtb hash表项插入/更新
-* @param   dev_id  设备号 
-* @param   sdt_no  sdt号 0~255
-* @param   pData   插入hash表项信息,由业务确定
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_dtb_hash_insert(DPP_DEV_T *dev,ZXIC_UINT32 queue_id,ZXIC_UINT32 sdt_no,void *pData);
+ * @param   dev_id  设备号
+ * @param   sdt_no  sdt号 0~255
+ * @param   pData   插入hash表项信息,由业务确定
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_dtb_hash_insert(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								   ZXIC_UINT32 sdt_no, void *pData);
 
 /***********************************************************/
 /** dtb hash表项删除
-* @param   dev_id  设备号 
-* @param   sdt_no  sdt号 0~255
-* @param   pData   删除hash表项信息,由业务传入
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_dtb_hash_delete(DPP_DEV_T *dev,ZXIC_UINT32 queue_id,ZXIC_UINT32 sdt_no,void *pData);
+ * @param   dev_id  设备号
+ * @param   sdt_no  sdt号 0~255
+ * @param   pData   删除hash表项信息,由业务传入
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_dtb_hash_delete(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								   ZXIC_UINT32 sdt_no, void *pData);
 
 /***********************************************************/
 /** acl表项插入/更新
-* @param   dev_id  设备号 
-* @param   sdt_no  sdt号 0~255
-* @param   pData   业务插入表项内容，具体结构体由业务确定(结构体的第一个字段必须为index)，SDK不感知
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_dtb_acl_entry_insert(DPP_DEV_T *dev,ZXIC_UINT32 queue_id, ZXIC_UINT32 sdt_no, void *pData);
+ * @param   dev_id  设备号
+ * @param   sdt_no  sdt号 0~255
+ * @param   pData   业务插入表项内容，具体结构体由业务确定(结构体的第一个字段必须为index)，SDK不感知
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_dtb_acl_entry_insert(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+										ZXIC_UINT32 sdt_no, void *pData);
 
 /***********************************************************/
 /** 释放sdt资源以及适配资源
-* @param   dev_id      设备号
-* @param   sdt_no      sdt号
-* @return  
-* @remark  无
-* @see
-* @author  cq      @date  2023/11/09
-************************************************************/
+ * @param   dev_id      设备号
+ * @param   sdt_no      sdt号
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/11/09
+ ************************************************************/
 DPP_STATUS dpp_apt_sdt_res_deinit(DPP_DEV_T *dev, ZXIC_UINT32 sdt_no);
 #endif
 
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_dtb_table_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_dtb_table_api.h
index 3bcc5c450dd721b0500d9e5747e3b84470d3a243..907591fb143806502803ee7f46cfefc4de175b6d 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_dtb_table_api.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_dtb_table_api.h
@@ -2,209 +2,193 @@
 #define _DPP_DTB_TABLE_API_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
 #include "dpp_dev.h"
 #include "zxic_common.h"
 
-#define DPP_DTB_DUMP_ZCAM_TYPE  (ZXIC_UINT32)(0)
-#define DPP_DTB_DUMP_DDR_TYPE   (ZXIC_UINT32)(1)
-
-typedef struct dpp_dtb_user_entry_t
-{
-    ZXIC_UINT32 sdt_no;        /*流表sdt号*/
-    ZXIC_VOID* p_entry_data;   /*该流表的数据，数据结构见各表的结构体定义*/
-}DPP_DTB_USER_ENTRY_T;
-
-typedef struct dpp_dtb_eram_entry_info_t
-{
-    ZXIC_UINT32 index;      /*条目index，根据wrt_mode模式为单位的的index，支持1/64/128bit */
-    ZXIC_UINT32 *p_data;    /*写入的表项信息 */
-}DPP_DTB_ERAM_ENTRY_INFO_T;
-
-typedef struct dpp_dtb_ddr_entry_info_t
-{
-    ZXIC_UINT32 index;      /*条目index，根据wrt_mode模式定义的index，支持128/256/384/512bit*/
-    ZXIC_UINT32 *p_data;    /*写入的表项信息*/
-}DPP_DTB_DDR_ENTRY_INFO_T;
-
-typedef struct dpp_dtb_hash_entry_info_t
-{
-    ZXIC_UINT8 *p_actu_key;     /*实际的键值，对于一种表来说键值长度是固定的，在初始化时，会通过dpp_hash_tbl_id_info_init进行配置*/
-    ZXIC_UINT8 *p_rst;          /*hash表结果 result的长度由当前业务结果位宽决定*/
-}DPP_DTB_HASH_ENTRY_INFO_T;
-
-typedef struct dpp_dtb_acl_entry_info_t
-{
-    ZXIC_UINT32   handle;     /*条目索引*/
-    ZXIC_UINT8    *key_data;  /*键值data部分 按mode的长度，支持640bit/320bit/160bit/80bit*/
-    ZXIC_UINT8    *key_mask;  /*键值mask部分 长度与data相同*/
-    ZXIC_UINT8    *p_as_rslt; /*关联结果，仅使能关联查找情况有效 支持1/64/128bit*/
-}DPP_DTB_ACL_ENTRY_INFO_T;
-
-typedef struct dpp_dtb_dump_index_t
-{
-    ZXIC_UINT32 index;      /*index*/
-    ZXIC_UINT32 index_type;  /*index类型 */
-}DPP_DTB_DUMP_INDEX_T;
-
-typedef struct dtb_queue_dma_addr_info
-{
-  ZXIC_UINT32 slot_id;         /*np所在的槽位号*/ 
-  ZXIC_UINT32 queue_id;        /*队列号*/
-  ZXIC_UINT32 dma_size;        /*该队列申请的dma大小*/
-  ZXIC_UINT64 dma_phy_addr;    /* dma 物理地址*/
-  ZXIC_UINT64 dma_vir_addr;    /* dma 内核虚拟地址*/
-}DTB_QUEUE_DMA_ADDR_INFO;
+#define DPP_DTB_DUMP_ZCAM_TYPE ((ZXIC_UINT32)(0))
+#define DPP_DTB_DUMP_DDR_TYPE ((ZXIC_UINT32)(1))
+
+typedef struct dpp_dtb_user_entry_t {
+	ZXIC_UINT32 sdt_no; /*流表sdt号*/
+	ZXIC_VOID *p_entry_data; /*该流表的数据，数据结构见各表的结构体定义*/
+} DPP_DTB_USER_ENTRY_T;
+
+typedef struct dpp_dtb_eram_entry_info_t {
+	ZXIC_UINT32
+	index; /*条目index，根据wrt_mode模式为单位的的index，支持1/64/128bit */
+	ZXIC_UINT32 *p_data; /*写入的表项信息 */
+} DPP_DTB_ERAM_ENTRY_INFO_T;
+
+typedef struct dpp_dtb_ddr_entry_info_t {
+	ZXIC_UINT32
+	index; /*条目index，根据wrt_mode模式定义的index，支持128/256/384/512bit*/
+	ZXIC_UINT32 *p_data; /*写入的表项信息*/
+} DPP_DTB_DDR_ENTRY_INFO_T;
+
+typedef struct dpp_dtb_hash_entry_info_t {
+	ZXIC_UINT8 *
+			p_actu_key; /*实际的键值，对于一种表来说键值长度是固定的，在初始化时，会通过dpp_hash_tbl_id_info_init进行配置*/
+	ZXIC_UINT8 *p_rst; /*hash表结果 result的长度由当前业务结果位宽决定*/
+} DPP_DTB_HASH_ENTRY_INFO_T;
+
+typedef struct dpp_dtb_acl_entry_info_t {
+	ZXIC_UINT32 handle; /*条目索引*/
+	ZXIC_UINT8 *
+			key_data; /*键值data部分 按mode的长度，支持640bit/320bit/160bit/80bit*/
+	ZXIC_UINT8 *key_mask; /*键值mask部分 长度与data相同*/
+	ZXIC_UINT8 *p_as_rslt; /*关联结果，仅使能关联查找情况有效 支持1/64/128bit*/
+} DPP_DTB_ACL_ENTRY_INFO_T;
+
+typedef struct dpp_dtb_dump_index_t {
+	ZXIC_UINT32 index; /*index*/
+	ZXIC_UINT32 index_type; /*index类型 */
+} DPP_DTB_DUMP_INDEX_T;
+
+typedef struct dtb_queue_dma_addr_info {
+	ZXIC_UINT32 slot_id; /*np所在的槽位号*/
+	ZXIC_UINT32 queue_id; /*队列号*/
+	ZXIC_UINT32 dma_size; /*该队列申请的dma大小*/
+	ZXIC_UINT64 dma_phy_addr; /* dma 物理地址*/
+	ZXIC_UINT64 dma_vir_addr; /* dma 内核虚拟地址*/
+} DTB_QUEUE_DMA_ADDR_INFO;
 
 /*dump地址信息获取*/
-ZXIC_UINT32 dpp_dtb_dump_sdt_addr_get(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 queue_id,  
-                                      ZXIC_UINT32 sdt_no, 
-                                      ZXIC_UINT64 *phy_addr, 
-                                      ZXIC_UINT64 *vir_addr, 
-                                      ZXIC_UINT32 *size);
+ZXIC_UINT32 dpp_dtb_dump_sdt_addr_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									  ZXIC_UINT32 sdt_no, ZXIC_UINT64 *phy_addr,
+									  ZXIC_UINT64 *vir_addr, ZXIC_UINT32 *size);
 
 /***********************************************************/
 /** DTB通道申请
-* @param   devId       NP设备号
-* @param   pName       申请DTB通道的唯一设备名(最大32字符)
-* @param   pQueueId    申请到的DTB通道编号
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_requst(DPP_DEV_T *dev, ZXIC_CONST ZXIC_UINT8* pName, 
-                                 ZXIC_UINT16 vPort, 
-                                 ZXIC_UINT32 *pQueueId);
+     * @param   devId       NP设备号
+     * @param   pName       申请DTB通道的唯一设备名(最大32字符)
+     * @param   pQueueId    申请到的DTB通道编号
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2023/07/03
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_requst(DPP_DEV_T *dev, ZXIC_UINT8 *pName,
+								 ZXIC_UINT16 vPort, ZXIC_UINT32 *pQueueId);
 
 /***********************************************************/
 /** DTB通道释放
-* @param   devId       NP设备号
-* @param   pName       要释放DTB通道的唯一设备名(最大32字符)
-* @param   pQueueId    要释放的DTB通道编号
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_release(DPP_DEV_T *dev, ZXIC_CONST ZXIC_UINT8* pName, 
-                                  ZXIC_UINT32 queueId);
+     * @param   devId       NP设备号
+     * @param   pName       要释放DTB通道的唯一设备名(最大32字符)
+     * @param   pQueueId    要释放的DTB通道编号
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2023/07/03
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_release(DPP_DEV_T *dev, ZXIC_UINT8 *pName,
+								  ZXIC_UINT32 queueId);
 
 /***********************************************************/
 /** DTB通道用户信息配置
-* @param   devId      NP设备号
-* @param   queueId    DTB通道编号
-* @param   vPort      vport信息
-* @param   vector     中断号
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/
-ZXIC_UINT32 dpp_dtb_user_info_set(DPP_DEV_T *dev,
-                                  ZXIC_UINT32 queueId, 
-                                  ZXIC_UINT16 vPort, 
-                                  ZXIC_UINT32 vector);
+     * @param   devId      NP设备号
+     * @param   queueId    DTB通道编号
+     * @param   vPort      vport信息
+     * @param   vector     中断号
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2023/07/03
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_user_info_set(DPP_DEV_T *dev, ZXIC_UINT32 queueId,
+								  ZXIC_UINT16 vPort, ZXIC_UINT32 vector);
 
 /***********************************************************/
 /** DTB通道下表空间地址设置,空间大小[32*(16+16*1024)B]
-* @param   devId      NP设备号
-* @param   queueId    DTB通道编号
-* @param   phyAddr    物理地址
-* @param   virAddr    虚拟地址
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/
+     * @param   devId      NP设备号
+     * @param   queueId    DTB通道编号
+     * @param   phyAddr    物理地址
+     * @param   virAddr    虚拟地址
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2023/07/03
+     ************************************************************/
 ZXIC_UINT32 dpp_dtb_queue_down_table_addr_set(DPP_DEV_T *dev,
-                                              ZXIC_UINT32 queueId, 
-                                              ZXIC_UINT64 phyAddr, 
-                                              ZXIC_UINT64 virAddr);
+											  ZXIC_UINT32 queueId,
+											  ZXIC_UINT64 phyAddr,
+											  ZXIC_UINT64 virAddr);
 
 /***********************************************************/
 /** DTB通道dump空间地址设置,空间大小[32*(16+16*1024)B]
-* @param   devId      NP设备号
-* @param   pName      要释放DTB通道的设备名
-* @param   phyAddr    物理地址
-* @param   virAddr    虚拟地址
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/
+     * @param   devId      NP设备号
+     * @param   pName      要释放DTB通道的设备名
+     * @param   phyAddr    物理地址
+     * @param   virAddr    虚拟地址
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2023/07/03
+     ************************************************************/
 ZXIC_UINT32 dpp_dtb_queue_dump_table_addr_set(DPP_DEV_T *dev,
-                                              ZXIC_UINT32 queueId, 
-                                              ZXIC_UINT64 phyAddr, 
-                                              ZXIC_UINT64 virAddr);
+											  ZXIC_UINT32 queueId,
+											  ZXIC_UINT64 phyAddr,
+											  ZXIC_UINT64 virAddr);
 
 /***********************************************************/
 /** 大批量dump一个流表使用的地址空间配置
-* @param   devId       NP设备号
-* @param   queueId     DTB队列编号
-* @param   sdtNo       流表std号
-* @param   phyAddr     物理地址
-* @param   virAddr     虚拟地址
-* @param   size        (最大64MB)
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/
-ZXIC_UINT32 dpp_dtb_dump_sdt_addr_set(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 queueId,  
-                                      ZXIC_UINT32 sdtNo, 
-                                      ZXIC_UINT64 phyAddr, 
-                                      ZXIC_UINT64 virAddr, 
-                                      ZXIC_UINT32 size);
+     * @param   devId       NP设备号
+     * @param   queueId     DTB队列编号
+     * @param   sdtNo       流表std号
+     * @param   phyAddr     物理地址
+     * @param   virAddr     虚拟地址
+     * @param   size        (最大64MB)
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2023/07/03
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_dump_sdt_addr_set(DPP_DEV_T *dev, ZXIC_UINT32 queueId,
+									  ZXIC_UINT32 sdtNo, ZXIC_UINT64 phyAddr,
+									  ZXIC_UINT64 virAddr, ZXIC_UINT32 size);
 
 /***********************************************************/
 /** 清除大批量dump一个流表使用的地址空间配置
-* @param   devId        NP设备号
-* @param   queueId      DTB队列编号
-* @param   sdtNo        流表std号
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/
-ZXIC_UINT32 dpp_dtb_dump_sdt_addr_clear(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 queueId, 
-                                        ZXIC_UINT32 sdtNo);
+     * @param   devId        NP设备号
+     * @param   queueId      DTB队列编号
+     * @param   sdtNo        流表std号
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2023/07/03
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_dump_sdt_addr_clear(DPP_DEV_T *dev, ZXIC_UINT32 queueId,
+										ZXIC_UINT32 sdtNo);
 
 /***********************************************************/
 /** 释放当前sdt下的所有流表(硬件方式)
-* (适用于进程启动后，仅配置流表资源，软件未配置流表，但需要删除硬件上已配置流表的场景) 
-* @param   dev_id  设备号 
-* @param   queue_id  队列号
-* @param   sdt_no  sdt号 
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/12/04
-************************************************************/
-DPP_STATUS dpp_dtb_hash_offline_delete(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 queue_id,
-                                        ZXIC_UINT32 sdt_no);
-
+     * (适用于进程启动后，仅配置流表资源，软件未配置流表，但需要删除硬件上已配置流表的场景)
+     * @param   dev_id  设备号
+     * @param   queue_id  队列号
+     * @param   sdt_no  sdt号
+     * @return
+     * @remark  无
+     * @see
+     * @author  cq      @date  2023/12/04
+     ************************************************************/
+DPP_STATUS dpp_dtb_hash_offline_delete(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									   ZXIC_UINT32 sdt_no);
 
 /***********************************************************/
 /** 释放当前sdt下的所有流表(硬件方式)
-* (适用于进程正常退出前删除表项，软件上有存储表项)
-* @param   dev_id  设备号 
-* @param   queue_id  队列号
-* @param   sdt_no  sdt号 
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/12/04
-************************************************************/
-DPP_STATUS dpp_dtb_hash_online_delete(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 queue_id,
-                                        ZXIC_UINT32 sdt_no);
+     * (适用于进程正常退出前删除表项，软件上有存储表项)
+     * @param   dev_id  设备号
+     * @param   queue_id  队列号
+     * @param   sdt_no  sdt号
+     * @return
+     * @remark  无
+     * @see
+     * @author  cq      @date  2023/12/04
+     ************************************************************/
+DPP_STATUS dpp_dtb_hash_online_delete(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									  ZXIC_UINT32 sdt_no);
 
 #ifdef __cplusplus
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_pbu_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_pbu_api.h
index f5586055c30d5f7dc41810ce58e08d12ce3732df..40df36ae021e7df3dc19f647cda8a0aa76cbd901 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_pbu_api.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_pbu_api.h
@@ -1,145 +1,90 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_pbu_api.h
-* 文件标识 : pbu模块对外数据类型定义和接口函数声明
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : djf
-* 完成日期 : 2015/02/04
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-
-#ifndef  _DPP_PBU_API_H_
-#define _DPP_PBU_API_H_
-
-#include "dpp_module.h"
-
-#if ZXIC_REAL("data struct define")
-typedef struct dpp_pbu_mc_cos_para_t
-{
-    ZXIC_UINT32 mc_cos_th[8];   /**<  @brief cos0~7的mc指针阈值*/
-    ZXIC_UINT32 mc_cos_mode[8]; /**<  @brief cos0~7的mc指针溢出处理模式*/
-} DPP_PBU_MC_COS_PARA_T;
-
-
-typedef struct dpp_pbu_port_th_para_t
-{
-    ZXIC_UINT32 lif_th; /**<  @brief lif阈值*/
-    ZXIC_UINT32 lif_prv; /**<  @brief lif私有阈值*/
-    ZXIC_UINT32 idma_prv; /**<  @brief idma私有阈值*/
-    ZXIC_UINT32 idma_th_cos0; /**<  @brief idma cos0指针阈值*/
-    ZXIC_UINT32 idma_th_cos1; /**<  @brief idma cos1指针阈值*/
-    ZXIC_UINT32 idma_th_cos2; /**<  @brief idma cos2指针阈值*/
-    ZXIC_UINT32 idma_th_cos3; /**<  @brief idma cos3指针阈值*/
-    ZXIC_UINT32 idma_th_cos4; /**<  @brief idma cos4指针阈值*/
-    ZXIC_UINT32 idma_th_cos5; /**<  @brief idma cos5指针阈值*/
-    ZXIC_UINT32 idma_th_cos6; /**<  @brief idma cos6指针阈值*/
-    ZXIC_UINT32 idma_th_cos7; /**<  @brief idma cos7指针阈值*/
-} DPP_PBU_PORT_TH_PARA_T;
-
-typedef struct dpp_pbu_port_cos_th_para_t
-{
-    ZXIC_UINT32 cos_th[8];  /**< @brief 各cos对应的阈值，要求高优先级的阈值不小于低优先级的阈值 */
-} DPP_PBU_PORT_COS_TH_PARA_T;
-
-
-typedef struct dpp_pbu_global_th_t
-{
-    ZXIC_UINT32 idma_public_th;/**<  @brief idma总的共有指针*/
-    ZXIC_UINT32 lif_public_th;/**<  @brief lif总的共有指针*/
-    ZXIC_UINT32 idma_total_th;/**<  @brief idma总的指针阈值，最大支持16384*/
-    ZXIC_UINT32 lif_total_th;/**<  @brief lif总的指针阈值，最大支持16384*/
-    ZXIC_UINT32 mc_total_th;/**<  @brief 组播总的指针阈值*/
-} DPP_PBU_GLOBAL_TH_T;
-
-
-
-
-
-
-#endif//struct
-
-
-#if ZXIC_REAL("function declaration")
-#if 0
-/***********************************************************/
-/** 全局公共使用指针阈值总体配置
-* @param   dev_id  芯片ID 0~3
-* @param   p_global_th   参见DPP_PBU_GLOBAL_TH_T详细定义
-*
-* @return
-* @remark  无
-* @see
-* @author  pj      @date  2019/12/04
-************************************************************/
-DPP_STATUS dpp_pbu_global_th_set(ZXIC_UINT32 dev_id,
-                                 DPP_PBU_GLOBAL_TH_T *p_global_th);
-
-#endif
-/***********************************************************/
-/** 配置基于端口的指针阈值
-* @param   dev_id   设备编号
-* @param   port_id   端口号
-* @param   p_para   端口阈值
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/07/09
-************************************************************/
-DPP_STATUS dpp_pbu_port_th_set(DPP_DEV_T *dev,
-                               ZXIC_UINT32 port_id,
-                               DPP_PBU_PORT_TH_PARA_T *p_para);
-
-/***********************************************************/
-/** 配置指定端口按cos优先级起pfc流控的优先级流控指针阈值，仅对lif0的48个通道有效
-* @param   dev_id   设备编号
-* @param   port_id   端口号
-* @param   p_para   cos阈值，要求高优先级的阈值不小于低优先级的阈值
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/07/09
-************************************************************/
-DPP_STATUS dpp_pbu_port_cos_th_set(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 port_id,
-                                   DPP_PBU_PORT_COS_TH_PARA_T *p_para);
-
-#if 0
-/***********************************************************/
-/** pbu初始化函数
-* @param   dev_id   设备编号
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/07/09
-************************************************************/
-DPP_STATUS dpp_pbu_init(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** 配置基于cos的mc复制指针阈值和mc指针溢出处理模式
-* @param   dev_id   设备编号
-* @param   p_para   cos0~7的mc指针阈值和mc指针溢出处理模式 0-wait 1-disc
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/14
-************************************************************/
-DPP_STATUS dpp_pbu_mc_cos_para_set(ZXIC_UINT32 dev_id,
-                                   DPP_PBU_MC_COS_PARA_T *p_para);
-#endif
-#endif//function
-#endif
-
-
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_pbu_api.h
+* 文件标识 : pbu模块对外数据类型定义和接口函数声明
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : djf
+* 完成日期 : 2015/02/04
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#ifndef _DPP_PBU_API_H_
+#define _DPP_PBU_API_H_
+
+#include "dpp_module.h"
+
+#if ZXIC_REAL("data struct define")
+typedef struct dpp_pbu_mc_cos_para_t {
+	ZXIC_UINT32 mc_cos_th[8]; /**<  @brief cos0~7的mc指针阈值*/
+	ZXIC_UINT32 mc_cos_mode[8]; /**<  @brief cos0~7的mc指针溢出处理模式*/
+} DPP_PBU_MC_COS_PARA_T;
+
+typedef struct dpp_pbu_port_th_para_t {
+	ZXIC_UINT32 lif_th; /**<  @brief lif阈值*/
+	ZXIC_UINT32 lif_prv; /**<  @brief lif私有阈值*/
+	ZXIC_UINT32 idma_prv; /**<  @brief idma私有阈值*/
+	ZXIC_UINT32 idma_th_cos0; /**<  @brief idma cos0指针阈值*/
+	ZXIC_UINT32 idma_th_cos1; /**<  @brief idma cos1指针阈值*/
+	ZXIC_UINT32 idma_th_cos2; /**<  @brief idma cos2指针阈值*/
+	ZXIC_UINT32 idma_th_cos3; /**<  @brief idma cos3指针阈值*/
+	ZXIC_UINT32 idma_th_cos4; /**<  @brief idma cos4指针阈值*/
+	ZXIC_UINT32 idma_th_cos5; /**<  @brief idma cos5指针阈值*/
+	ZXIC_UINT32 idma_th_cos6; /**<  @brief idma cos6指针阈值*/
+	ZXIC_UINT32 idma_th_cos7; /**<  @brief idma cos7指针阈值*/
+} DPP_PBU_PORT_TH_PARA_T;
+
+typedef struct dpp_pbu_port_cos_th_para_t {
+	ZXIC_UINT32 cos_th
+			[8]; /**< @brief 各cos对应的阈值，要求高优先级的阈值不小于低优先级的阈值 */
+} DPP_PBU_PORT_COS_TH_PARA_T;
+
+typedef struct dpp_pbu_global_th_t {
+	ZXIC_UINT32 idma_public_th; /**<  @brief idma总的共有指针*/
+	ZXIC_UINT32 lif_public_th; /**<  @brief lif总的共有指针*/
+	ZXIC_UINT32 idma_total_th; /**<  @brief idma总的指针阈值，最大支持16384*/
+	ZXIC_UINT32 lif_total_th; /**<  @brief lif总的指针阈值，最大支持16384*/
+	ZXIC_UINT32 mc_total_th; /**<  @brief 组播总的指针阈值*/
+} DPP_PBU_GLOBAL_TH_T;
+
+#endif // struct
+
+#if ZXIC_REAL("function declaration")
+/***********************************************************/
+/** 配置基于端口的指针阈值
+ * @param   dev_id   设备编号
+ * @param   port_id   端口号
+ * @param   p_para   端口阈值
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/07/09
+ ************************************************************/
+DPP_STATUS dpp_pbu_port_th_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+							   DPP_PBU_PORT_TH_PARA_T *p_para);
+
+/***********************************************************/
+/** 配置指定端口按cos优先级起pfc流控的优先级流控指针阈值，仅对lif0的48个通道有效
+ * @param   dev_id   设备编号
+ * @param   port_id   端口号
+ * @param   p_para   cos阈值，要求高优先级的阈值不小于低优先级的阈值
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/07/09
+ ************************************************************/
+DPP_STATUS dpp_pbu_port_cos_th_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+								   DPP_PBU_PORT_COS_TH_PARA_T *p_para);
+
+#endif // function
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_ppu_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_ppu_api.h
old mode 100755
new mode 100644
index 45f587534b9dc9240999c831b96c8ce80b776c93..829f4bc5822fc59c0d762c9d95fc649a37d13619
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_ppu_api.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_ppu_api.h
@@ -1,393 +1,594 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_ppu_api.h
-* 文件标识 : 
-* 内容摘要 : PPU模块对外数据结构和函数声明
-* 其它说明 : 
-* 当前版本 : 
-* 作    者 : wcl
-* 完成日期 : 2015/02/13
-* DEPARTMENT: ASIC_FPGA_R&D_Dept 
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* 版 本 号:  
-* 修 改 人:  
-* 修改内容:  
-***************************************************************/
-
-#ifndef _DPP_PPU_API_H_
-#define _DPP_PPU_API_H_
-
-
-#if ZXIC_REAL("header file")
-#include "dpp_module.h"
-
-#endif
-
-#if ZXIC_REAL("data struct define")
-
-/** mcode version time */
-typedef struct dpp_version_t
-{
-    /*对应微码伪指令 version = expr_a.expr_b.expr_c*/
-    ZXIC_UINT32 version_a; /**<  @brief expr_a*/
-    ZXIC_UINT32 version_b; /**<  @brief expr_b*/
-    ZXIC_UINT32 version_c; /**<  @brief xpr_c*/
-
-    /*对应微码编译版本的时间 年/月/日/小时*/
-    ZXIC_UINT32 year;
-    ZXIC_UINT32 month;
-    ZXIC_UINT32 day;
-    ZXIC_UINT32 hour;
-}DPP_VERSION_T;
-
-/**  SDT表数据*/
-typedef struct dpp_sdt_tbl_data_t
-{
-    ZXIC_UINT32 data_high32; /**<  @brief SDT表数据高32bit*/
-    ZXIC_UINT32 data_low32;  /**<  @brief SDT表数据低32bit*/
-}DPP_SDT_TBL_DATA_T;
-
-#endif
-
-#if ZXIC_REAL("interrupt data struct define")
-/**  PPU 指令RAM ECC错误中断原因*/
-typedef struct dpp_ppu_ram_parity_err_t
-{
-    ZXIC_UINT32 instrmem2_bank3_parity_err; /**<  @brief 指令RAM instrmem2 BANK3 parity 错误*/
-    ZXIC_UINT32 instrmem2_bank2_parity_err; /**<  @brief 指令RAM instrmem2 BANK2 parity 错误*/
-    ZXIC_UINT32 instrmem2_bank1_parity_err; /**<  @brief 指令RAM instrmem2 BANK1 parity 错误*/
-    ZXIC_UINT32 instrmem2_bank0_parity_err; /**<  @brief 指令RAM instrmem2 BANK0 parity 错误*/
-    ZXIC_UINT32 instrmem1_bank3_parity_err; /**<  @brief 指令RAM instrmem1 BANK3 parity 错误*/
-    ZXIC_UINT32 instrmem1_bank2_parity_err; /**<  @brief 指令RAM instrmem1 BANK2 parity 错误*/
-    ZXIC_UINT32 instrmem1_bank1_parity_err; /**<  @brief 指令RAM instrmem1 BANK1 parity 错误*/
-    ZXIC_UINT32 instrmem1_bank0_parity_err; /**<  @brief 指令RAM instrmem1 BANK0 parity 错误*/
-    ZXIC_UINT32 instrmem0_bank3_parity_err; /**<  @brief 指令RAM instrmem0 BANK3 parity 错误*/
-    ZXIC_UINT32 instrmem0_bank2_parity_err; /**<  @brief 指令RAM instrmem0 BANK2 parity 错误*/
-    ZXIC_UINT32 instrmem0_bank1_parity_err; /**<  @brief 指令RAM instrmem0 BANK1 parity 错误*/
-    ZXIC_UINT32 instrmem0_bank0_parity_err; /**<  @brief 指令RAM instrmem0 BANK0 parity 错误*/
-}DPP_PPU_RAM_PARITY_ERR_T;
-
-/**  PPU ME指令RAM ECC错误中断原因*/
-typedef struct dpp_ppu_me_interrupt_t
-{
-    ZXIC_UINT32 me7_interrupt_mask ;     /**<  @brief me7core的中断掩码*/
-    ZXIC_UINT32 me6_interrupt_mask ;     /**<  @brief me6core的中断掩码*/
-    ZXIC_UINT32 me5_interrupt_mask ;     /**<  @brief me5core的中断掩码*/
-    ZXIC_UINT32 me4_interrupt_mask ;     /**<  @brief me4core的中断掩码*/
-    ZXIC_UINT32 me3_interrupt_mask ;     /**<  @brief me3core的中断掩码*/
-    ZXIC_UINT32 me2_interrupt_mask ;     /**<  @brief me2core的中断掩码*/
-    ZXIC_UINT32 me1_interrupt_mask ;     /**<  @brief me1core的中断掩码*/
-    ZXIC_UINT32 me0_interrupt_mask ;     /**<  @brief me0core的中断掩码*/
-
-}DPP_PPU_ME_INTERRUPT_T;
-
-/**  cluster mex的错误中断原因*/
-typedef struct dpp_ppu_cluster_600m_mex_fifo_int_t
-{
-    ZXIC_UINT32 ppu_se_ikey_afifo_underflow;       /**<  @brief se片内表key fifo读空中断*/
-    ZXIC_UINT32 ppu_se_ekey_afifo_underflow;       /**<  @brief se片外表key fifo读空中断*/
-    ZXIC_UINT32 ppu_sta_key_afifo_underflow;       /**<  @brief 统计计数key fifo读空中断*/
-    ZXIC_UINT32 ppu_cluster_mf_in_overflow;        /**<  @brief metafram接收 fifo满写中断*/
-    ZXIC_UINT32 ppu_ese_rsp_afifo_overflow;        /**<  @brief se片外表 rsp fifo满写中断*/
-    ZXIC_UINT32 ppu_ise_rsp_afifo_overflow;        /**<  @brief se片内表 rsp fifo满写中断*/
-    ZXIC_UINT32 ppu_sta_rsp_afifo_overflow;        /**<  @brief 统计计数 rsp fifo满写中断*/
-}DPP_PPU_CLUSTER_600M_MEX_FIFO_INT_T;
-
-/**  cluster mex的错误中断原因*/
-typedef struct dpp_ppu_cluster_1200m_mex_fifo_int_t
-{
-    ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_overflow_flag;              /**<  @brief ppu_se_key_afifo_32x54_wrapper满写中断掩码*/
-    ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_overflow_flag;             /**<  @brief ppu_se_key_afifo_32x665_wrapper满写中断掩码*/
-    ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_overflow_flag;            /**<  @brief ppu_sta_key_afifo_32x110_wrapper满写中断掩码*/
-    ZXIC_UINT32 ppu_cluster_mf_in_afifo_16x2048_wrapper_underflow_flag;    /**<  @brief ppu_cluster_mf_in_afifo_32x2048_wrapper读空中断掩码*/
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_flag;     /**<  @brief ppu_pbu_mcode_pf_rsp_fifo满写中断掩码*/
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_flag;    /**<  @brief ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper读空中断掩码*/
-    ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_flag;        /**<  @brief ppu_coprocess_rsp_fifo_32x77_wrapper满写中断掩码*/
-    ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_flag;       /**<  @brief ppu_coprocess_rsp_fifo_32x77_wrapper读空中断掩码*/
-    ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_flag;  /**<  @brief ppu_coprocess_rsp_fwft_fifo_128x78_wrapper满写中断掩码*/
-    ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_flag; /**<  @brief ppu_coprocess_rsp_fwft_fifo_128x78_wrapper读空中断掩码*/
-    ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_flag;        /**<  @brief ppu_ese_rsp_afifo_64x271_wrapper_u0满写中断掩码*/
-    
-    ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_overflow_flag;                     /**<  @brief ese_rsp_ram_free_ptr_u0满写中断掩码*/
-    ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_underflow_flag;                    /**<  @brief ese_rsp_ram_free_ptr_u0读空中断掩码*/
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag;  /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0满写中断掩码*/
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0读空中断掩码*/
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag;  /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1满写中断掩码*/
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1读空中断掩码*/
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag;  /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2满写中断掩码*/
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2读空中断掩码*/
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag;  /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3满写中断标记*/
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3读空中断标记*/
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag;  /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4满写中断标记*/
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4读空中断标记*/
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag;  /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5满写中断标记*/
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5读空中断标记*/
-    ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_flag;        /**<  @brief ppu_ise_rsp_afifo_64x143_wrapper_u0读空中断标记*/
-    ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_overflow_flag;                     /**<  @brief ise_rsp_ram_free_ptr_u0满写中断标记  */
-    ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_underflow_flag;                    /**<  @brief ise_rsp_ram_free_ptr_u0读空中断标记*/
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag;  /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0满写中断标记*/
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0读空中断标记*/
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag;  /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1满写中断标记*/
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1读空中断标记*/
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag;  /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2满写中断标记*/
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2读空中断标记*/
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag;  /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3满写中断标记*/
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3读空中断标记*/
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag;  /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4满写中断标记*/
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4读空中断标记*/
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag;  /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5满写中断标记*/
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5读空中断标记*/
-    ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_underflow_flag;            /**<  @brief ppu_sta_rsp_afifo_64x79_wrapper读空中断标记*/
-    ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_flag;        /**<  @brief ppu_sta_rsp_fwft_fifo_128x79_wrapper满写中断标记*/
-    ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_flag;       /**<  @brief ppu_sta_rsp_fwft_fifo_128x79_wrapper读空中断标记*/
-}DPP_PPU_CLUSTER_1200M_MEX_FIFO_INT_T;
-
-typedef struct dpp_ppu_ppu_ram_err_t
-{
-    ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_parity_err_flag;             /**<  @brief dup_freeptr_fwft_fifo_128x7_wrapper_u0_parity_err中断标记*/
-    ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_parity_err_flag;       /**<  @brief free_global_num_fwft_fifo_8192x13_wrapper_u0_parity_err中断标记*/
-    ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_parity_err_flag;                    /**<  @brief ppu_mccnt_fifo_32x15_wrapper_u0_parity_err中断标记*/
-    ZXIC_UINT32 ppu_reorder_link_table_ram_1r1w_8192x13_wrapper_u1_parity_err_flag; /**<  @brief ppu_reorder_link_table_ram_1r1w_8192x13_wrapper_u1_parity_err中断标记*/
-    ZXIC_UINT32 ppu_reorder_link_table_ram_1r1w_8192x13_wrapper_u0_parity_err_flag; /**<  @brief ppu_reorder_link_table_ram_1r1w_8192x13_wrapper_u0_parity_err中断标记*/
-}DPP_PPU_PPU_RAM_ERR_T;
-
-typedef struct dpp_ppu_cls_ram_err_600m_t
-{
-    ZXIC_UINT32 ppu_sdt_table_ram_2rw_256x64_wrapper_parity_errb_flag; /**<  @brief ppu_sdt_table_ram_2rw_256x64_wrapper_parity_errb中断标记*/
-    ZXIC_UINT32 ppu_sdt_table_ram_2rw_256x64_wrapper_parity_erra_flag; /**<  @brief ppu_sdt_table_ram_2rw_256x64_wrapper_parity_errba中断标记*/
-}DPP_PPU_CLS_RAM_ERR_600M_T;
-
-/**  cluster mex的错误中断原因*/
-typedef struct dpp_ppu_cluster_me_fifo_int_t
-{
-    ZXIC_UINT32 me_except_refetch_pc_overflow_flag;  /**<  @brief me_except_refetch_pc满写中断标记*/
-    ZXIC_UINT32 me_except_refetch_pc_underflow_flag; /**<  @brief me_except_refetch_pc读空中断标记*/
-    
-    ZXIC_UINT32 me_free_pkt_q_overflow_flag;         /**<  @brief me_free_pkt_q满写中断状态*/
-    ZXIC_UINT32 me_free_pkt_q_underflow_flag;        /**<  @brief me_free_pkt_q读空中断状态*/
-    ZXIC_UINT32 me_free_thread_q_overflow_flag;      /**<  @brief me_free_thread_q满写中断状态*/
-    ZXIC_UINT32 me_free_thread_q_underflow_flag;     /**<  @brief me_free_thread_q读空中断状态*/
-    ZXIC_UINT32 me_pkt_in_overflow_flag;             /**<  @brief me_pkt_in_满写中断状态*/  
-    ZXIC_UINT32 me_pkt_in_underflow_flag;            /**<  @brief me_pkt_in_读空中断状态*/ 
-    ZXIC_UINT32 me_rdy_q_overflow_flag;              /**<  @brief me_rdy_q满写中断状态*/ 
-    ZXIC_UINT32 me_rdy_q_underflow_flag;             /**<  @brief me_rdy_q读空中断状态*/
-    ZXIC_UINT32 me_pkt_out_q_overflow_flag;          /**<  @brief me_pkt_out_q满写中断状态*/
-    ZXIC_UINT32 me_pkt_out_q_underflow_flag;         /**<  @brief me_pkt_out_q读空中断状态*/
-    ZXIC_UINT32 me_continue_q_overflow_flag;         /**<  @brief me_continue_q满写中断状态*/
-    ZXIC_UINT32 me_continue_q_underflow_flag;        /**<  @brief me_continue_q读空中断状态*/
-    ZXIC_UINT32 me_esrh_q_overflow_flag;             /**<  @brief me_esrh_q满写中断状态*/ 
-    ZXIC_UINT32 me_esrh_q_underflow_flag;            /**<  @brief me_esrh_q读空中断状态*/
-    ZXIC_UINT32 me_isrh_q_overflow_flag;             /**<  @brief me_isrh_q满写中断状态*/
-    ZXIC_UINT32 me_isrh_q_underflow_flag;            /**<  @brief me_isrh_q读空中断状态*/  
-    ZXIC_UINT32 me_cache_miss_q_overflow_flag;       /**<  @brief me_cache_miss_q满写中断状态*/
-    ZXIC_UINT32 me_cache_miss_q_underflow_flag;      /**<  @brief me_cache_miss_q读空中断状态*/ 
-    ZXIC_UINT32 me_base_q_u0_overflow_flag;          /**<  @brief me_base_q_u0满写中断状态*/
-    ZXIC_UINT32 me_base_q_u0_underflow_flag;         /**<  @brief me_base_q_u0读空中断状态*/
-    ZXIC_UINT32 me_base_q_u1_overflow_flag;          /**<  @brief me_base_q_u1满写中断状态*/ 
-    ZXIC_UINT32 me_base_q_u1_underflow_flag;         /**<  @brief me_base_q_u1读空中断状态*/
-    ZXIC_UINT32 me_base_q_u2_overflow_flag;          /**<  @brief me_base_q_u2满写中断状态*/ 
-    ZXIC_UINT32 me_base_q_u2_underflow_flag;         /**<  @brief me_base_q_u2读空中断状态*/
-    ZXIC_UINT32 me_base_q_u3_overflow_flag;          /**<  @brief me_base_q_u3满写中断状态*/ 
-    ZXIC_UINT32 me_base_q_u3_underflow_flag;         /**<  @brief me_base_q_u3读空中断状态*/
-    ZXIC_UINT32 me_reg_pc_q_overflow_flag;           /**<  @brief me_reg_pc_q满写中断状态*/
-    ZXIC_UINT32 me_reg_pc_q_underflow_flag;          /**<  @brief me_reg_pc_q读空中断状态*/
-    ZXIC_UINT32 me_branch_q_overflow_flag;           /**<  @brief me_branch_q满写中断状态*/
-    ZXIC_UINT32 me_branch_q_underflow_flag;          /**<  @brief me_branch_q读空中断状态*/
-    ZXIC_UINT32 me_pkt_base_q_overflow_flag;         /**<  @brief me_pkt_base_q满写中断状态*/
-    ZXIC_UINT32 me_pkt_base_q_underflow_flag;        /**<  @brief me_pkt_base_q读空中断状态*/
-}DPP_PPU_CLUSTER_ME_FIFO_INT_T;
-
-
-typedef struct dpp_ppu_ppu_isu_ppu_demux_fifo_int_t
-{
-    ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_flag;  /**<  @brief isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow中断标记*/
-    ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_flag; /**<  @brief isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow中断标记*/
-    ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_overflow_flag;            /**<  @brief isu_in_fifo_64x81_wrapper_u0_overflow中断标记*/
-    ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_underflow_flag;           /**<  @brief isu_in_fifo_64x81_wrapper_u0_underflow中断标记*/
-}DPP_PPU_PPU_ISU_PPU_DEMUX_FIFO_INT_T;
-
-typedef struct dpp_ppu_ppu_ppu_multicast_fifo_int_t
-{
-    ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_overflow_flag;        /**<  @brief pf_req_fwft_fifo_16x36_wrapper_u0_overflow中断标记*/
-    ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_underflow_flag;       /**<  @brief pf_req_fwft_fifo_16x36_wrapper_u0_underflow中断标记*/
-    ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_flag;        /**<  @brief pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow中断标记*/
-    ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_flag;       /**<  @brief pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow中断标记*/
-    ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_overflow_flag;      /**<  @brief dup_para_fwft_fifo_16x35_wrapper_u0_overflow中断标记*/
-    ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_underflow_flag;     /**<  @brief dup_para_fwft_fifo_16x35_wrapper_u0_underflow中断标记*/
-    ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_flag;     /**<  @brief se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow中断标记*/
-    ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_flag;    /**<  @brief se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow中断标记*/
-    ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_overflow_flag;       /**<  @brief sa_para_fwft_fifo_64x17_wrapper_u0_overflow中断标记*/
-    ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_underflow_flag;      /**<  @brief sa_para_fwft_fifo_64x17_wrapper_u0_underflow中断标记*/
-    ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_overflow_flag;           /**<  @brief group_id_fifo_64x16_wrapper_u0_overflow中断标记*/
-    ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_underflow_flag;          /**<  @brief group_id_fifo_64x16_wrapper_u0_underflow中断标记*/
-    ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_flag;  /**<  @brief isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow中断标记*/
-    ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_flag; /**<  @brief isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow中断标记*/
-    ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_flag;   /**<  @brief dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow中断标记*/
-    ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_flag;  /**<  @brief dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow中断标记*/
-    ZXIC_UINT32 car_flag_fifo_32x1_wrapper_overflow_flag;               /**<  @brief car_flag_fifo_32x1_wrapper_overflow中断标记*/
-    ZXIC_UINT32 car_flag_fifo_32x1_wrapper_underflow_flag;              /**<  @brief car_flag_fifo_32x1_wrapper_underflow中断标记*/
-}DPP_PPU_PPU_PPU_MULTICAST_FIFO_INT_T;
-
-typedef struct dpp_ppu_ppu_ppu_in_schedule_fifo_int_t
-{
-    ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_flag;  /**<  @brief free_global_num_fwft_fifo_8192x13_满写中断标记*/
-    ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_flag; /**<  @brief free_global_num_fwft_fifo_8192x13_空读中断标记*/
-    ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_overflow_flag;                 /**<  @brief mc_mf_fifo_16x2048_满写中断标记*/
-    ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_underflow_flag;                /**<  @brief mc_mf_fifo_16x2048_空读中断标记*/
-    ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_overflow_flag;                 /**<  @brief uc_mf_fifo_96x2048_满写中断标记*/
-    ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_underflow_flag;                /**<  @brief uc_mf_fifo_96x2048_空读中断标记*/
-}DPP_PPU_PPU_PPU_IN_SCHEDULE_FIFO_INT_T;
-
-typedef struct dpp_ppu_ppu_ppu_mf_out_fifo_int_t
-{
-    ZXIC_UINT32 ppu_cluster5_mf_out_afifo_16x2048_wrapper_overflow_flag;  /**<  @brief cluster5发送描述符fifo满写中断标记*/
-    ZXIC_UINT32 ppu_cluster5_mf_out_afifo_16x2048_wrapper_underflow_flag; /**<  @brief cluster5发送描述符fifo空读中断标记*/
-    ZXIC_UINT32 ppu_cluster4_mf_out_afifo_16x2048_wrapper_overflow_flag;  /**<  @brief cluster4发送描述符fifo满写中断标记*/
-    ZXIC_UINT32 ppu_cluster4_mf_out_afifo_16x2048_wrapper_underflow_flag; /**<  @brief cluster4发送描述符fifo空读中断标记*/
-    ZXIC_UINT32 ppu_cluster3_mf_out_afifo_16x2048_wrapper_overflow_flag;  /**<  @brief cluster3发送描述符fifo满写中断标记*/
-    ZXIC_UINT32 ppu_cluster3_mf_out_afifo_16x2048_wrapper_underflow_flag; /**<  @brief cluster3发送描述符fifo空读中断标记*/
-    ZXIC_UINT32 ppu_cluster2_mf_out_afifo_16x2048_wrapper_overflow_flag;  /**<  @brief cluster2发送描述符fifo满写中断标记*/
-    ZXIC_UINT32 ppu_cluster2_mf_out_afifo_16x2048_wrapper_underflow_flag; /**<  @brief cluster2发送描述符fifo空读中断标记*/
-    ZXIC_UINT32 ppu_cluster1_mf_out_afifo_16x2048_wrapper_overflow_flag;  /**<  @brief cluster1发送描述符fifo满写中断标记*/
-    ZXIC_UINT32 ppu_cluster1_mf_out_afifo_16x2048_wrapper_underflow_flag; /**<  @brief cluster1发送描述符fifo空读中断标记*/
-    ZXIC_UINT32 ppu_cluster0_mf_out_afifo_16x2048_wrapper_overflow_flag;  /**<  @brief cluster0发送描述符fifo满写中断标记*/
-    ZXIC_UINT32 ppu_cluster0_mf_out_afifo_16x2048_wrapper_underflow_flag; /**<  @brief cluster0发送描述符fifo空读中断标记*/
-}DPP_PPU_PPU_PPU_MF_OUT_FIFO_INT_T;
-
-typedef struct dpp_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_int_t
-{
-    ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;  /**<  @brief cluster5指针预取fifo满写中断标记*/
-    ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;  /**<  @brief cluster4指针预取fifo满写中断标记*/
-    ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;  /**<  @brief cluster3指针预取fifo满写中断标记*/
-    ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;  /**<  @brief cluster2指针预取fifo满写中断标记*/
-    ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;  /**<  @brief cluster1指针预取fifo满写中断标记*/
-    ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;  /**<  @brief cluster0指针预取fifo满写中断标记*/
-    ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**<  @brief cluster5指针预取fifo空读中断标记*/
-    ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**<  @brief cluster4指针预取fifo空读中断标记*/
-    ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**<  @brief cluster3指针预取fifo空读中断标记*/
-    ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**<  @brief cluster2指针预取fifo空读中断标记*/
-    ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**<  @brief cluster1指针预取fifo空读中断标记*/
-    ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**<  @brief cluster0指针预取fifo空读中断标记*/
-}DPP_PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INT_T;
-
-typedef struct dpp_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_int_t
-{
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_flag; /**<  @brief ppu微码申请指针返回fifo空读中断标记*/
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_flag;   /**<  @brief ppu微码申请指针返回fifo满写中断标记*/
-}DPP_PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INT_T;
-
-typedef struct dpp_ppu_ppu_ppu_mccnt_fifo_int_t
-{
-    ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_overflow_flag;       /**<  @brief ppu_mccnt_fifo_32x15_wrapper_u0_overflow中断标记*/
-    ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_underflow_flag;      /**<  @brief ppu_mccnt_fifo_32x15_wrapper_u0_underflow中断标记*/
-    ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_flag;   /**<  @brief ppu_wb_data_fifo_32x2048_wrapper_u0_overflow中断标记*/
-    ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_flag;  /**<  @brief ppu_wb_data_fifo_32x2048_wrapper_u0_underflow中断标记*/
-    ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_overflow_flag;        /**<  @brief mccnt_rsp_fifo_32x1_wrapper_u0_overflow中断标记*/
-    ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_underflow_flag;       /**<  @brief mccnt_rsp_fifo_32x1_wrapper_u0_underflow中断标记*/
-}DPP_PPU_PPU_PPU_MCCNT_FIFO_INT_T;
-
-typedef struct dpp_ppu_ppu_coprocessor_fifo_int_t
-{
-    ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_flag;   /**<  @brief 协处理random_mod参数fifo错误满写中断标记*/
-    ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_flag;  /**<  @brief 协处理random_mod参数fifo错误空读中断标记*/
-
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_flag;    /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_flag;   /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_overflow_flag;          /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_underflow_flag;         /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_overflow_flag;          /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_underflow_flag;         /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_overflow_flag;          /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_underflow_flag;         /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_flag;    /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_flag;   /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_overflow_flag;          /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_underflow_flag;         /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_flag;    /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_flag;   /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_flag;    /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_flag;   /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flag;      /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flag;     /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;   /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;  /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flag;         /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flag;        /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;  /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flag;        /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flag;       /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;   /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;  /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flag;         /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flag;        /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;  /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
-
-    ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flag;        /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flag;       /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;   /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;  /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flag;         /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flag;        /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;  /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flag;        /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flag;       /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;   /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;  /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flag;         /**<  @brief fifo错误中断标记*/  
-    ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flag;        /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;  /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flag;        /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flag;       /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;   /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;  /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flag;         /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flag;        /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;  /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flag;        /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flag;       /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;   /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;  /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flag;         /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flag;        /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;  /**<  @brief fifo错误中断标记*/
-    ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
-}DPP_PPU_PPU_COPROCESSOR_FIFO_INT_T;
-
-
-typedef struct dpp_ppu_ppu_cos_meter_cfg_t
-{
-    ZXIC_UINT32 cbs;           /**<  @brief 0~7队列CBS配置*/
-    ZXIC_UINT32 pbs;           /**<  @brief 0~7队列PBS配置*/
-    ZXIC_UINT32 green_action;  /**<  @brief 0~7队列绿色报文动作配置，关闭CAR使能的时候，需要同时将该动作置为1*/
-    ZXIC_UINT32 yellow_action; /**<  @brief 0~7队列黄色报文动作配置*/
-    ZXIC_UINT32 red_action;    /**<  @brief 0~7队列红色报文动作配置*/
-    ZXIC_UINT32 cir;           /**<  @brief 0~7队列CIR配置，单位Mpps，0x24a对应600Mpps，按照线性变化*/  
-    ZXIC_UINT32 pir;           /**<  @brief 0~7队列PIR配置，单位Mpps，0x24a对应600Mpps，按照线性变化*/
-    ZXIC_UINT32 car_en;        /**<  @brief 0~7队列CAR使能配置*/
-}DPP_PPU_PPU_COS_METER_CFG_T;
-
-#endif
-
-/***********************************************************/
-/** 配置SDT表
-* @param   dev_id   设备号，范围0~3
-* @param   cluster_id  me cluster编号，范围0~7
-* @param   index       地址，即sdt表号，范围0~255
-* @param   p_sdt_data  sdt表数据
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/03/18
-************************************************************/
-DPP_STATUS dpp_ppu_sdt_tbl_write(DPP_DEV_T *dev, ZXIC_UINT32 cluster_id, ZXIC_UINT32 index, DPP_SDT_TBL_DATA_T *p_sdt_data);
-
-#endif /* dpp_ppu_api.h */
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_ppu_api.h
+* 文件标识 :
+* 内容摘要 : PPU模块对外数据结构和函数声明
+* 其它说明 :
+* 当前版本 :
+* 作    者 : wcl
+* 完成日期 : 2015/02/13
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#ifndef _DPP_PPU_API_H_
+#define _DPP_PPU_API_H_
+
+#if ZXIC_REAL("header file")
+#include "dpp_module.h"
+
+#endif
+
+#if ZXIC_REAL("data struct define")
+
+/** mcode version time */
+typedef struct dpp_version_t {
+	/*对应微码伪指令 version = expr_a.expr_b.expr_c*/
+	ZXIC_UINT32 version_a; /**<  @brief expr_a*/
+	ZXIC_UINT32 version_b; /**<  @brief expr_b*/
+	ZXIC_UINT32 version_c; /**<  @brief xpr_c*/
+
+	/*对应微码编译版本的时间 年/月/日/小时*/
+	ZXIC_UINT32 year;
+	ZXIC_UINT32 month;
+	ZXIC_UINT32 day;
+	ZXIC_UINT32 hour;
+} DPP_VERSION_T;
+
+/**  SDT表数据*/
+typedef struct dpp_sdt_tbl_data_t {
+	ZXIC_UINT32 data_high32; /**<  @brief SDT表数据高32bit*/
+	ZXIC_UINT32 data_low32; /**<  @brief SDT表数据低32bit*/
+} DPP_SDT_TBL_DATA_T;
+
+#endif
+
+#if ZXIC_REAL("interrupt data struct define")
+/**  PPU 指令RAM ECC错误中断原因*/
+typedef struct dpp_ppu_ram_parity_err_t {
+	ZXIC_UINT32
+	instrmem2_bank3_parity_err; /**<  @brief 指令RAM instrmem2 BANK3 parity 错误*/
+	ZXIC_UINT32
+	instrmem2_bank2_parity_err; /**<  @brief 指令RAM instrmem2 BANK2 parity 错误*/
+	ZXIC_UINT32
+	instrmem2_bank1_parity_err; /**<  @brief 指令RAM instrmem2 BANK1 parity 错误*/
+	ZXIC_UINT32
+	instrmem2_bank0_parity_err; /**<  @brief 指令RAM instrmem2 BANK0 parity 错误*/
+	ZXIC_UINT32
+	instrmem1_bank3_parity_err; /**<  @brief 指令RAM instrmem1 BANK3 parity 错误*/
+	ZXIC_UINT32
+	instrmem1_bank2_parity_err; /**<  @brief 指令RAM instrmem1 BANK2 parity 错误*/
+	ZXIC_UINT32
+	instrmem1_bank1_parity_err; /**<  @brief 指令RAM instrmem1 BANK1 parity 错误*/
+	ZXIC_UINT32
+	instrmem1_bank0_parity_err; /**<  @brief 指令RAM instrmem1 BANK0 parity 错误*/
+	ZXIC_UINT32
+	instrmem0_bank3_parity_err; /**<  @brief 指令RAM instrmem0 BANK3 parity 错误*/
+	ZXIC_UINT32
+	instrmem0_bank2_parity_err; /**<  @brief 指令RAM instrmem0 BANK2 parity 错误*/
+	ZXIC_UINT32
+	instrmem0_bank1_parity_err; /**<  @brief 指令RAM instrmem0 BANK1 parity 错误*/
+	ZXIC_UINT32
+	instrmem0_bank0_parity_err; /**<  @brief 指令RAM instrmem0 BANK0 parity 错误*/
+} DPP_PPU_RAM_PARITY_ERR_T;
+
+/**  PPU ME指令RAM ECC错误中断原因*/
+typedef struct dpp_ppu_me_interrupt_t {
+	ZXIC_UINT32 me7_interrupt_mask; /**<  @brief me7core的中断掩码*/
+	ZXIC_UINT32 me6_interrupt_mask; /**<  @brief me6core的中断掩码*/
+	ZXIC_UINT32 me5_interrupt_mask; /**<  @brief me5core的中断掩码*/
+	ZXIC_UINT32 me4_interrupt_mask; /**<  @brief me4core的中断掩码*/
+	ZXIC_UINT32 me3_interrupt_mask; /**<  @brief me3core的中断掩码*/
+	ZXIC_UINT32 me2_interrupt_mask; /**<  @brief me2core的中断掩码*/
+	ZXIC_UINT32 me1_interrupt_mask; /**<  @brief me1core的中断掩码*/
+	ZXIC_UINT32 me0_interrupt_mask; /**<  @brief me0core的中断掩码*/
+
+} DPP_PPU_ME_INTERRUPT_T;
+
+/**  cluster mex的错误中断原因*/
+typedef struct dpp_ppu_cluster_600m_mex_fifo_int_t {
+	ZXIC_UINT32
+	ppu_se_ikey_afifo_underflow; /**<  @brief se片内表key fifo读空中断*/
+	ZXIC_UINT32
+	ppu_se_ekey_afifo_underflow; /**<  @brief se片外表key fifo读空中断*/
+	ZXIC_UINT32
+	ppu_sta_key_afifo_underflow; /**<  @brief 统计计数key fifo读空中断*/
+	ZXIC_UINT32
+	ppu_cluster_mf_in_overflow; /**<  @brief metafram接收 fifo满写中断*/
+	ZXIC_UINT32
+	ppu_ese_rsp_afifo_overflow; /**<  @brief se片外表 rsp fifo满写中断*/
+	ZXIC_UINT32
+	ppu_ise_rsp_afifo_overflow; /**<  @brief se片内表 rsp fifo满写中断*/
+	ZXIC_UINT32
+	ppu_sta_rsp_afifo_overflow; /**<  @brief 统计计数 rsp fifo满写中断*/
+} DPP_PPU_CLUSTER_600M_MEX_FIFO_INT_T;
+
+/**  cluster mex的错误中断原因*/
+typedef struct dpp_ppu_cluster_1200m_mex_fifo_int_t {
+	ZXIC_UINT32
+	ppu_se_key_afifo_32x54_wrapper_overflow_flag; /**<  @brief ppu_se_key_afifo_32x54_wrapper满写中断掩码*/
+	ZXIC_UINT32
+	ppu_se_key_afifo_32x665_wrapper_overflow_flag; /**<  @brief ppu_se_key_afifo_32x665_wrapper满写中断掩码*/
+	ZXIC_UINT32
+	ppu_sta_key_afifo_32x110_wrapper_overflow_flag; /**<  @brief ppu_sta_key_afifo_32x110_wrapper满写中断掩码*/
+	ZXIC_UINT32
+	ppu_cluster_mf_in_afifo_16x2048_wrapper_underflow_flag; /**<  @brief ppu_cluster_mf_in_afifo_32x2048_wrapper读空中断掩码*/
+	ZXIC_UINT32
+	ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_flag; /**<  @brief ppu_pbu_mcode_pf_rsp_fifo满写中断掩码*/
+	ZXIC_UINT32
+	ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_flag; /**<  @brief ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper读空中断掩码*/
+	ZXIC_UINT32
+	ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_flag; /**<  @brief ppu_coprocess_rsp_fifo_32x77_wrapper满写中断掩码*/
+	ZXIC_UINT32
+	ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_flag; /**<  @brief ppu_coprocess_rsp_fifo_32x77_wrapper读空中断掩码*/
+	ZXIC_UINT32
+	ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_flag; /**<  @brief ppu_coprocess_rsp_fwft_fifo_128x78_wrapper满写中断掩码*/
+	ZXIC_UINT32
+	ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_flag; /**<  @brief ppu_coprocess_rsp_fwft_fifo_128x78_wrapper读空中断掩码*/
+	ZXIC_UINT32
+	ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_flag; /**<  @brief ppu_ese_rsp_afifo_64x271_wrapper_u0满写中断掩码*/
+
+	ZXIC_UINT32
+	ese_rsp_ram_free_ptr_u0_overflow_flag; /**<  @brief ese_rsp_ram_free_ptr_u0满写中断掩码*/
+	ZXIC_UINT32
+	ese_rsp_ram_free_ptr_u0_underflow_flag; /**<  @brief ese_rsp_ram_free_ptr_u0读空中断掩码*/
+	ZXIC_UINT32
+	ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0满写中断掩码*/
+	ZXIC_UINT32
+	ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0读空中断掩码*/
+	ZXIC_UINT32
+	ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1满写中断掩码*/
+	ZXIC_UINT32
+	ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1读空中断掩码*/
+	ZXIC_UINT32
+	ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2满写中断掩码*/
+	ZXIC_UINT32
+	ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2读空中断掩码*/
+	ZXIC_UINT32
+	ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3满写中断标记*/
+	ZXIC_UINT32
+	ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3读空中断标记*/
+	ZXIC_UINT32
+	ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4满写中断标记*/
+	ZXIC_UINT32
+	ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4读空中断标记*/
+	ZXIC_UINT32
+	ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5满写中断标记*/
+	ZXIC_UINT32
+	ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag; /**<  @brief ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5读空中断标记*/
+	ZXIC_UINT32
+	ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_flag; /**<  @brief ppu_ise_rsp_afifo_64x143_wrapper_u0读空中断标记*/
+	ZXIC_UINT32
+	ise_rsp_ram_free_ptr_u0_overflow_flag; /**<  @brief ise_rsp_ram_free_ptr_u0满写中断标记  */
+	ZXIC_UINT32
+	ise_rsp_ram_free_ptr_u0_underflow_flag; /**<  @brief ise_rsp_ram_free_ptr_u0读空中断标记*/
+	ZXIC_UINT32
+	ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0满写中断标记*/
+	ZXIC_UINT32
+	ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0读空中断标记*/
+	ZXIC_UINT32
+	ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1满写中断标记*/
+	ZXIC_UINT32
+	ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1读空中断标记*/
+	ZXIC_UINT32
+	ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2满写中断标记*/
+	ZXIC_UINT32
+	ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2读空中断标记*/
+	ZXIC_UINT32
+	ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3满写中断标记*/
+	ZXIC_UINT32
+	ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3读空中断标记*/
+	ZXIC_UINT32
+	ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4满写中断标记*/
+	ZXIC_UINT32
+	ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4读空中断标记*/
+	ZXIC_UINT32
+	ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5满写中断标记*/
+	ZXIC_UINT32
+	ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag; /**<  @brief ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5读空中断标记*/
+	ZXIC_UINT32
+	ppu_sta_rsp_afifo_64x79_wrapper_underflow_flag; /**<  @brief ppu_sta_rsp_afifo_64x79_wrapper读空中断标记*/
+	ZXIC_UINT32
+	ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_flag; /**<  @brief ppu_sta_rsp_fwft_fifo_128x79_wrapper满写中断标记*/
+	ZXIC_UINT32
+	ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_flag; /**<  @brief ppu_sta_rsp_fwft_fifo_128x79_wrapper读空中断标记*/
+} DPP_PPU_CLUSTER_1200M_MEX_FIFO_INT_T;
+
+typedef struct dpp_ppu_ppu_ram_err_t {
+	ZXIC_UINT32
+	dup_freeptr_fwft_fifo_128x7_wrapper_u0_parity_err_flag; /**<  @brief dup_freeptr_fwft_fifo_128x7_wrapper_u0_parity_err中断标记*/
+	ZXIC_UINT32
+	free_global_num_fwft_fifo_8192x13_wrapper_u0_parity_err_flag; /**<  @brief free_global_num_fwft_fifo_8192x13_wrapper_u0_parity_err中断标记*/
+	ZXIC_UINT32
+	ppu_mccnt_fifo_32x15_wrapper_u0_parity_err_flag; /**<  @brief ppu_mccnt_fifo_32x15_wrapper_u0_parity_err中断标记*/
+	ZXIC_UINT32
+	ppu_reorder_link_table_ram_1r1w_8192x13_wrapper_u1_parity_err_flag; /**<  @brief ppu_reorder_link_table_ram_1r1w_8192x13_wrapper_u1_parity_err中断标记*/
+	ZXIC_UINT32
+	ppu_reorder_link_table_ram_1r1w_8192x13_wrapper_u0_parity_err_flag; /**<  @brief ppu_reorder_link_table_ram_1r1w_8192x13_wrapper_u0_parity_err中断标记*/
+} DPP_PPU_PPU_RAM_ERR_T;
+
+typedef struct dpp_ppu_cls_ram_err_600m_t {
+	ZXIC_UINT32
+	ppu_sdt_table_ram_2rw_256x64_wrapper_parity_errb_flag; /**<  @brief ppu_sdt_table_ram_2rw_256x64_wrapper_parity_errb中断标记*/
+	ZXIC_UINT32
+	ppu_sdt_table_ram_2rw_256x64_wrapper_parity_erra_flag; /**<  @brief ppu_sdt_table_ram_2rw_256x64_wrapper_parity_errba中断标记*/
+} DPP_PPU_CLS_RAM_ERR_600M_T;
+
+/**  cluster mex的错误中断原因*/
+typedef struct dpp_ppu_cluster_me_fifo_int_t {
+	ZXIC_UINT32
+	me_except_refetch_pc_overflow_flag; /**<  @brief me_except_refetch_pc满写中断标记*/
+	ZXIC_UINT32
+	me_except_refetch_pc_underflow_flag; /**<  @brief me_except_refetch_pc读空中断标记*/
+
+	ZXIC_UINT32
+	me_free_pkt_q_overflow_flag; /**<  @brief me_free_pkt_q满写中断状态*/
+	ZXIC_UINT32
+	me_free_pkt_q_underflow_flag; /**<  @brief me_free_pkt_q读空中断状态*/
+	ZXIC_UINT32
+	me_free_thread_q_overflow_flag; /**<  @brief me_free_thread_q满写中断状态*/
+	ZXIC_UINT32
+	me_free_thread_q_underflow_flag; /**<  @brief me_free_thread_q读空中断状态*/
+	ZXIC_UINT32 me_pkt_in_overflow_flag; /**<  @brief me_pkt_in_满写中断状态*/
+	ZXIC_UINT32 me_pkt_in_underflow_flag; /**<  @brief me_pkt_in_读空中断状态*/
+	ZXIC_UINT32 me_rdy_q_overflow_flag; /**<  @brief me_rdy_q满写中断状态*/
+	ZXIC_UINT32 me_rdy_q_underflow_flag; /**<  @brief me_rdy_q读空中断状态*/
+	ZXIC_UINT32
+	me_pkt_out_q_overflow_flag; /**<  @brief me_pkt_out_q满写中断状态*/
+	ZXIC_UINT32
+	me_pkt_out_q_underflow_flag; /**<  @brief me_pkt_out_q读空中断状态*/
+	ZXIC_UINT32
+	me_continue_q_overflow_flag; /**<  @brief me_continue_q满写中断状态*/
+	ZXIC_UINT32
+	me_continue_q_underflow_flag; /**<  @brief me_continue_q读空中断状态*/
+	ZXIC_UINT32 me_esrh_q_overflow_flag; /**<  @brief me_esrh_q满写中断状态*/
+	ZXIC_UINT32 me_esrh_q_underflow_flag; /**<  @brief me_esrh_q读空中断状态*/
+	ZXIC_UINT32 me_isrh_q_overflow_flag; /**<  @brief me_isrh_q满写中断状态*/
+	ZXIC_UINT32 me_isrh_q_underflow_flag; /**<  @brief me_isrh_q读空中断状态*/
+	ZXIC_UINT32
+	me_cache_miss_q_overflow_flag; /**<  @brief me_cache_miss_q满写中断状态*/
+	ZXIC_UINT32
+	me_cache_miss_q_underflow_flag; /**<  @brief me_cache_miss_q读空中断状态*/
+	ZXIC_UINT32
+	me_base_q_u0_overflow_flag; /**<  @brief me_base_q_u0满写中断状态*/
+	ZXIC_UINT32
+	me_base_q_u0_underflow_flag; /**<  @brief me_base_q_u0读空中断状态*/
+	ZXIC_UINT32
+	me_base_q_u1_overflow_flag; /**<  @brief me_base_q_u1满写中断状态*/
+	ZXIC_UINT32
+	me_base_q_u1_underflow_flag; /**<  @brief me_base_q_u1读空中断状态*/
+	ZXIC_UINT32
+	me_base_q_u2_overflow_flag; /**<  @brief me_base_q_u2满写中断状态*/
+	ZXIC_UINT32
+	me_base_q_u2_underflow_flag; /**<  @brief me_base_q_u2读空中断状态*/
+	ZXIC_UINT32
+	me_base_q_u3_overflow_flag; /**<  @brief me_base_q_u3满写中断状态*/
+	ZXIC_UINT32
+	me_base_q_u3_underflow_flag; /**<  @brief me_base_q_u3读空中断状态*/
+	ZXIC_UINT32 me_reg_pc_q_overflow_flag; /**<  @brief me_reg_pc_q满写中断状态*/
+	ZXIC_UINT32 me_reg_pc_q_underflow_flag; /**<  @brief me_reg_pc_q读空中断状态*/
+	ZXIC_UINT32 me_branch_q_overflow_flag; /**<  @brief me_branch_q满写中断状态*/
+	ZXIC_UINT32 me_branch_q_underflow_flag; /**<  @brief me_branch_q读空中断状态*/
+	ZXIC_UINT32
+	me_pkt_base_q_overflow_flag; /**<  @brief me_pkt_base_q满写中断状态*/
+	ZXIC_UINT32
+	me_pkt_base_q_underflow_flag; /**<  @brief me_pkt_base_q读空中断状态*/
+} DPP_PPU_CLUSTER_ME_FIFO_INT_T;
+
+typedef struct dpp_ppu_ppu_isu_ppu_demux_fifo_int_t {
+	ZXIC_UINT32
+	isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_flag; /**<  @brief isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow中断标记*/
+	ZXIC_UINT32
+	isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_flag; /**<  @brief isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow中断标记*/
+	ZXIC_UINT32
+	isu_in_fifo_64x81_wrapper_u0_overflow_flag; /**<  @brief isu_in_fifo_64x81_wrapper_u0_overflow中断标记*/
+	ZXIC_UINT32
+	isu_in_fifo_64x81_wrapper_u0_underflow_flag; /**<  @brief isu_in_fifo_64x81_wrapper_u0_underflow中断标记*/
+} DPP_PPU_PPU_ISU_PPU_DEMUX_FIFO_INT_T;
+
+typedef struct dpp_ppu_ppu_ppu_multicast_fifo_int_t {
+	ZXIC_UINT32
+	pf_req_fwft_fifo_16x36_wrapper_u0_overflow_flag; /**<  @brief pf_req_fwft_fifo_16x36_wrapper_u0_overflow中断标记*/
+	ZXIC_UINT32
+	pf_req_fwft_fifo_16x36_wrapper_u0_underflow_flag; /**<  @brief pf_req_fwft_fifo_16x36_wrapper_u0_underflow中断标记*/
+	ZXIC_UINT32
+	pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_flag; /**<  @brief pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow中断标记*/
+	ZXIC_UINT32
+	pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_flag; /**<  @brief pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow中断标记*/
+	ZXIC_UINT32
+	dup_para_fwft_fifo_16x35_wrapper_u0_overflow_flag; /**<  @brief dup_para_fwft_fifo_16x35_wrapper_u0_overflow中断标记*/
+	ZXIC_UINT32
+	dup_para_fwft_fifo_16x35_wrapper_u0_underflow_flag; /**<  @brief dup_para_fwft_fifo_16x35_wrapper_u0_underflow中断标记*/
+	ZXIC_UINT32
+	se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_flag; /**<  @brief se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow中断标记*/
+	ZXIC_UINT32
+	se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_flag; /**<  @brief se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow中断标记*/
+	ZXIC_UINT32
+	sa_para_fwft_fifo_64x17_wrapper_u0_overflow_flag; /**<  @brief sa_para_fwft_fifo_64x17_wrapper_u0_overflow中断标记*/
+	ZXIC_UINT32
+	sa_para_fwft_fifo_64x17_wrapper_u0_underflow_flag; /**<  @brief sa_para_fwft_fifo_64x17_wrapper_u0_underflow中断标记*/
+	ZXIC_UINT32
+	group_id_fifo_64x16_wrapper_u0_overflow_flag; /**<  @brief group_id_fifo_64x16_wrapper_u0_overflow中断标记*/
+	ZXIC_UINT32
+	group_id_fifo_64x16_wrapper_u0_underflow_flag; /**<  @brief group_id_fifo_64x16_wrapper_u0_underflow中断标记*/
+	ZXIC_UINT32
+	isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_flag; /**<  @brief isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow中断标记*/
+	ZXIC_UINT32
+	isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_flag; /**<  @brief isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow中断标记*/
+	ZXIC_UINT32
+	dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_flag; /**<  @brief dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow中断标记*/
+	ZXIC_UINT32
+	dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_flag; /**<  @brief dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow中断标记*/
+	ZXIC_UINT32
+	car_flag_fifo_32x1_wrapper_overflow_flag; /**<  @brief car_flag_fifo_32x1_wrapper_overflow中断标记*/
+	ZXIC_UINT32
+	car_flag_fifo_32x1_wrapper_underflow_flag; /**<  @brief car_flag_fifo_32x1_wrapper_underflow中断标记*/
+} DPP_PPU_PPU_PPU_MULTICAST_FIFO_INT_T;
+
+typedef struct dpp_ppu_ppu_ppu_in_schedule_fifo_int_t {
+	ZXIC_UINT32
+	free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_flag; /**<  @brief free_global_num_fwft_fifo_8192x13_满写中断标记*/
+	ZXIC_UINT32
+	free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_flag; /**<  @brief free_global_num_fwft_fifo_8192x13_空读中断标记*/
+	ZXIC_UINT32
+	mc_mf_fifo_16x2048_wrapper_u0_overflow_flag; /**<  @brief mc_mf_fifo_16x2048_满写中断标记*/
+	ZXIC_UINT32
+	mc_mf_fifo_16x2048_wrapper_u0_underflow_flag; /**<  @brief mc_mf_fifo_16x2048_空读中断标记*/
+	ZXIC_UINT32
+	uc_mf_fifo_96x2048_wrapper_u0_overflow_flag; /**<  @brief uc_mf_fifo_96x2048_满写中断标记*/
+	ZXIC_UINT32
+	uc_mf_fifo_96x2048_wrapper_u0_underflow_flag; /**<  @brief uc_mf_fifo_96x2048_空读中断标记*/
+} DPP_PPU_PPU_PPU_IN_SCHEDULE_FIFO_INT_T;
+
+typedef struct dpp_ppu_ppu_ppu_mf_out_fifo_int_t {
+	ZXIC_UINT32
+	ppu_cluster5_mf_out_afifo_16x2048_wrapper_overflow_flag; /**<  @brief cluster5发送描述符fifo满写中断标记*/
+	ZXIC_UINT32
+	ppu_cluster5_mf_out_afifo_16x2048_wrapper_underflow_flag; /**<  @brief cluster5发送描述符fifo空读中断标记*/
+	ZXIC_UINT32
+	ppu_cluster4_mf_out_afifo_16x2048_wrapper_overflow_flag; /**<  @brief cluster4发送描述符fifo满写中断标记*/
+	ZXIC_UINT32
+	ppu_cluster4_mf_out_afifo_16x2048_wrapper_underflow_flag; /**<  @brief cluster4发送描述符fifo空读中断标记*/
+	ZXIC_UINT32
+	ppu_cluster3_mf_out_afifo_16x2048_wrapper_overflow_flag; /**<  @brief cluster3发送描述符fifo满写中断标记*/
+	ZXIC_UINT32
+	ppu_cluster3_mf_out_afifo_16x2048_wrapper_underflow_flag; /**<  @brief cluster3发送描述符fifo空读中断标记*/
+	ZXIC_UINT32
+	ppu_cluster2_mf_out_afifo_16x2048_wrapper_overflow_flag; /**<  @brief cluster2发送描述符fifo满写中断标记*/
+	ZXIC_UINT32
+	ppu_cluster2_mf_out_afifo_16x2048_wrapper_underflow_flag; /**<  @brief cluster2发送描述符fifo空读中断标记*/
+	ZXIC_UINT32
+	ppu_cluster1_mf_out_afifo_16x2048_wrapper_overflow_flag; /**<  @brief cluster1发送描述符fifo满写中断标记*/
+	ZXIC_UINT32
+	ppu_cluster1_mf_out_afifo_16x2048_wrapper_underflow_flag; /**<  @brief cluster1发送描述符fifo空读中断标记*/
+	ZXIC_UINT32
+	ppu_cluster0_mf_out_afifo_16x2048_wrapper_overflow_flag; /**<  @brief cluster0发送描述符fifo满写中断标记*/
+	ZXIC_UINT32
+	ppu_cluster0_mf_out_afifo_16x2048_wrapper_underflow_flag; /**<  @brief cluster0发送描述符fifo空读中断标记*/
+} DPP_PPU_PPU_PPU_MF_OUT_FIFO_INT_T;
+
+typedef struct dpp_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_int_t {
+	ZXIC_UINT32
+	ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; /**<  @brief cluster5指针预取fifo满写中断标记*/
+	ZXIC_UINT32
+	ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; /**<  @brief cluster4指针预取fifo满写中断标记*/
+	ZXIC_UINT32
+	ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; /**<  @brief cluster3指针预取fifo满写中断标记*/
+	ZXIC_UINT32
+	ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; /**<  @brief cluster2指针预取fifo满写中断标记*/
+	ZXIC_UINT32
+	ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; /**<  @brief cluster1指针预取fifo满写中断标记*/
+	ZXIC_UINT32
+	ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag; /**<  @brief cluster0指针预取fifo满写中断标记*/
+	ZXIC_UINT32
+	ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**<  @brief cluster5指针预取fifo空读中断标记*/
+	ZXIC_UINT32
+	ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**<  @brief cluster4指针预取fifo空读中断标记*/
+	ZXIC_UINT32
+	ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**<  @brief cluster3指针预取fifo空读中断标记*/
+	ZXIC_UINT32
+	ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**<  @brief cluster2指针预取fifo空读中断标记*/
+	ZXIC_UINT32
+	ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**<  @brief cluster1指针预取fifo空读中断标记*/
+	ZXIC_UINT32
+	ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag; /**<  @brief cluster0指针预取fifo空读中断标记*/
+} DPP_PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INT_T;
+
+typedef struct dpp_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_int_t {
+	ZXIC_UINT32
+	ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_flag; /**<  @brief ppu微码申请指针返回fifo空读中断标记*/
+	ZXIC_UINT32
+	ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_flag; /**<  @brief ppu微码申请指针返回fifo满写中断标记*/
+} DPP_PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INT_T;
+
+typedef struct dpp_ppu_ppu_ppu_mccnt_fifo_int_t {
+	ZXIC_UINT32
+	ppu_mccnt_fifo_32x15_wrapper_u0_overflow_flag; /**<  @brief ppu_mccnt_fifo_32x15_wrapper_u0_overflow中断标记*/
+	ZXIC_UINT32
+	ppu_mccnt_fifo_32x15_wrapper_u0_underflow_flag; /**<  @brief ppu_mccnt_fifo_32x15_wrapper_u0_underflow中断标记*/
+	ZXIC_UINT32
+	ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_flag; /**<  @brief ppu_wb_data_fifo_32x2048_wrapper_u0_overflow中断标记*/
+	ZXIC_UINT32
+	ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_flag; /**<  @brief ppu_wb_data_fifo_32x2048_wrapper_u0_underflow中断标记*/
+	ZXIC_UINT32
+	mccnt_rsp_fifo_32x1_wrapper_u0_overflow_flag; /**<  @brief mccnt_rsp_fifo_32x1_wrapper_u0_overflow中断标记*/
+	ZXIC_UINT32
+	mccnt_rsp_fifo_32x1_wrapper_u0_underflow_flag; /**<  @brief mccnt_rsp_fifo_32x1_wrapper_u0_underflow中断标记*/
+} DPP_PPU_PPU_PPU_MCCNT_FIFO_INT_T;
+
+typedef struct dpp_ppu_ppu_coprocessor_fifo_int_t {
+	ZXIC_UINT32
+	ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_flag; /**<  @brief 协处理random_mod参数fifo错误满写中断标记*/
+	ZXIC_UINT32
+	ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_flag; /**<  @brief 协处理random_mod参数fifo错误空读中断标记*/
+
+	ZXIC_UINT32
+	ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	ppu_cop_delay_fifo_48x16_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	ppu_cop_delay_fifo_48x16_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	ppu_cop_delay_fifo_16x48_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	ppu_cop_delay_fifo_16x48_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	ppu_cop_delay_fifo_16x32_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	ppu_cop_delay_fifo_16x32_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	ppu_cop_delay_fifo_16x16_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	ppu_cop_delay_fifo_16x16_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+
+	ZXIC_UINT32
+	mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag; /**<  @brief fifo错误中断标记*/
+	ZXIC_UINT32
+	mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag; /**<  @brief fifo错误中断标记*/
+} DPP_PPU_PPU_COPROCESSOR_FIFO_INT_T;
+
+typedef struct dpp_ppu_ppu_cos_meter_cfg_t {
+	ZXIC_UINT32 cbs; /**<  @brief 0~7队列CBS配置*/
+	ZXIC_UINT32 pbs; /**<  @brief 0~7队列PBS配置*/
+	ZXIC_UINT32
+	green_action; /**<  @brief 0~7队列绿色报文动作配置，关闭CAR使能的时候，需要同时将该动作置为1*/
+	ZXIC_UINT32 yellow_action; /**<  @brief 0~7队列黄色报文动作配置*/
+	ZXIC_UINT32 red_action; /**<  @brief 0~7队列红色报文动作配置*/
+	ZXIC_UINT32
+	cir; /**<  @brief 0~7队列CIR配置，单位Mpps，0x24a对应600Mpps，按照线性变化*/
+	ZXIC_UINT32
+	pir; /**<  @brief 0~7队列PIR配置，单位Mpps，0x24a对应600Mpps，按照线性变化*/
+	ZXIC_UINT32 car_en; /**<  @brief 0~7队列CAR使能配置*/
+} DPP_PPU_PPU_COS_METER_CFG_T;
+
+#endif
+
+/***********************************************************/
+/** 配置SDT表
+ * @param   dev_id   设备号，范围0~3
+ * @param   cluster_id  me cluster编号，范围0~7
+ * @param   index       地址，即sdt表号，范围0~255
+ * @param   p_sdt_data  sdt表数据
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/03/18
+ ************************************************************/
+DPP_STATUS dpp_ppu_sdt_tbl_write(DPP_DEV_T *dev, ZXIC_UINT32 cluster_id,
+								 ZXIC_UINT32 index,
+								 DPP_SDT_TBL_DATA_T * p_sdt_data);
+
+#endif /* dpp_ppu_api.h */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_reg_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_reg_api.h
old mode 100755
new mode 100644
index b87c69ed7fbc357a8af47b4b2955c1b31c135d1c..ea2555cb1a5fc86d3f71eabfc2553e0bf1a20e1e
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_reg_api.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_reg_api.h
@@ -1,183 +1,191 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_reg.h
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : wcl
-* 完成日期 : 2014/02/12
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-
-#ifndef _DPP_REG_API_H_
-#define _DPP_REG_API_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "dpp_dev.h"
-#include "dpp_reg_struct.h"
-
-/**  所有上层模块不需要直接使用该全局变量*/
-extern  DPP_REG_T g_dpp_reg_info[];
-
-/**  public*/
-#define DPP_REG(no)              (g_dpp_reg_info[no])
-#define DPP_REG_NAME(no)         ((DPP_REG(no)).reg_name)
-#define DPP_REG_NO(no)           ((DPP_REG(no)).reg_no)
-#define DPP_REG_MODULE_NO(no)    ((DPP_REG(no)).module_no)
-#define DPP_REG_FLAGS(no)        ((DPP_REG(no)).flags)
-#define DPP_REG_TYPE(no)         ((DPP_REG(no)).array_type)
-#define DPP_REG_ADDR(no)         ((DPP_REG(no)).addr)
-#define DPP_REG_WIDTH(no)        ((DPP_REG(no)).width)
-#define DPP_REG_M_SIZE(no)       ((DPP_REG(no)).m_size)
-#define DPP_REG_N_SIZE(no)       ((DPP_REG(no)).n_size)
-#define DPP_REG_M_STEP(no)       ((DPP_REG(no)).m_step)
-#define DPP_REG_N_STEP(no)       ((DPP_REG(no)).n_step)
-#define DPP_REG_FIELD_NUM(no)    ((DPP_REG(no)).field_num)
-#define DPP_REG_FIELD_NAME(no, field_no)    (((DPP_REG(no)).p_fields+field_no)->p_name)
-
-typedef enum dpp_bar_4k_e
-{
-   BAR_4K_DTB = 0,  /**<  @brief 0*/
-   BAR_4K_ETCAM,    /**<  @brief 1*/
-   BAR_4K_CLS0,     /**<  @brief 2*/
-   BAR_4K_CLS1,     /**<  @brief 3*/
-   BAR_4K_CLS2,     /**<  @brief 4*/
-   BAR_4K_CLS3,     /**<  @brief 5*/
-   BAR_4K_CLS4,     /**<  @brief 6*/
-   BAR_4K_CLS5,     /**<  @brief 7*/
-   BAR_4K_SE,       /**<  @brief 8*/
-   BAR_4K_SMMU1,    /**<  @brief 9*/
-   BAR_4K_MAX           
-} DPP_BAR_4K_E;
-
-typedef struct
-{ 
-    ZXIC_UINT32 reg_module;      /*DPP_MODULE_E*/
-    ZXIC_UINT32 index_4k;        /*BAR NP空间映射4K相对索引*/
-    ZXIC_UINT32 addr_offset;     /*寄存器偏移，用于计算BAR映射空间位置*/
-}DPP_REG_OFFSET_ADDR;
-
-/***********************************************************/
-/** 获取寄存器属性
-* @param   reg_no  寄存器编号
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/04/17
-************************************************************/
-DPP_REG_T* dpp_reg_info_get(ZXIC_UINT32 reg_no);
-
-/***********************************************************/
-/** 通用寄存器写函数
-* @param   dev_id  设备号，支持多芯片
-* @param   reg_no 寄存器编号
-* @param   m_offset 二元寄存器的m偏移
-* @param   n_offset 一元寄存器或二元寄存器的n偏移
-* @param   p_data 数据指针
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/02/12
-************************************************************/
-DPP_STATUS dpp_reg_write(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset, ZXIC_VOID *p_data);
-
-/***********************************************************/
-/** 通用寄存器读函数
-* @param   dev_id 设备号，支持多芯片
-* @param   reg_no 寄存器编号
-* @param   m_offset 二元寄存器的m偏移
-* @param   n_offset 一元寄存器或二元寄存器的n偏移
-* @param   p_data 数据指针
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/02/12
-************************************************************/
-DPP_STATUS dpp_reg_read(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset, ZXIC_VOID *p_data);
-
-/***********************************************************/
-/** 根据寄存器编号获得寄存器芯片内绝对地址
-* @param   reg_no
-* @param   m_offset
-* @param   n_offset
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/03/19
-************************************************************/
-ZXIC_UINT32 dpp_reg_get_reg_addr(ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset);
-
-/***********************************************************/
-/** 通过寄存器编号配置寄存器，仅适用于32bit位宽
-    的常规寄存器
-* @param   dev_id  设备号
-* @param   reg_no     寄存器编号
-* @param   m_offset   二元寄存器的m偏移
-* @param   n_offset   一元寄存器或二元寄存器的n偏移
-* @param   data       数据，32bit
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/01/21
-************************************************************/
-DPP_STATUS dpp_reg_write32(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 data);
-
-/***********************************************************/
-/** 通过寄存器编号读取寄存器的值，仅适用于32bit位宽的常规寄存器
-* @param   dev_id   设备号
-* @param   reg_no   寄存器编号
-* @param   m_offset   二元寄存器的m偏移
-* @param   n_offset   一元寄存器或二元寄存器的n偏移
-* @param   p_data   出参，返回读取寄存器数值
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  石金锋      @date  2015/03/09
-************************************************************/
-DPP_STATUS dpp_reg_read32(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset, ZXIC_UINT32 *p_data);
-/***********************************************************/
-/** 判断是否为4K寄存器
-* @param   reg_module
-*
-* @return  
-* @remark  无
-* @see
-* @author  cq      @date  2023/11/29
-************************************************************/
-BOOLEAN dpp_4k_reg(ZXIC_UINT32 reg_module);
-/***********************************************************/
-/** 获取NP对应模块的映射地址偏移(riscv或者非4K寄存器不做转换，host根据映射情况做转换)
-* @param   dev_id
-* @param   reg_module
-* @param   flags  标志位，DPP_REG_FLAG_INDIRECT DPP_REG_FLAG_DIRECT
-* @param   addr
-*
-* @return  映射地址
-* @remark  无
-* @see
-* @author  cq      @date  2023/11/29
-************************************************************/
-ZXIC_UINT32 dpp_reg_addr_convert(ZXIC_UINT32 dev_id, ZXIC_UINT32 reg_module,ZXIC_UINT32 flags, ZXIC_UINT32 addr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_reg.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : wcl
+* 完成日期 : 2014/02/12
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#ifndef _DPP_REG_API_H_
+#define _DPP_REG_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dpp_dev.h"
+#include "dpp_reg_struct.h"
+
+/**  所有上层模块不需要直接使用该全局变量*/
+extern DPP_REG_T g_dpp_reg_info[];
+
+/**  public*/
+#define DPP_REG(no) (g_dpp_reg_info[no])
+#define DPP_REG_NAME(no) ((DPP_REG(no)).reg_name)
+#define DPP_REG_NO(no) ((DPP_REG(no)).reg_no)
+#define DPP_REG_MODULE_NO(no) ((DPP_REG(no)).module_no)
+#define DPP_REG_FLAGS(no) ((DPP_REG(no)).flags)
+#define DPP_REG_TYPE(no) ((DPP_REG(no)).array_type)
+#define DPP_REG_ADDR(no) ((DPP_REG(no)).addr)
+#define DPP_REG_WIDTH(no) ((DPP_REG(no)).width)
+#define DPP_REG_M_SIZE(no) ((DPP_REG(no)).m_size)
+#define DPP_REG_N_SIZE(no) ((DPP_REG(no)).n_size)
+#define DPP_REG_M_STEP(no) ((DPP_REG(no)).m_step)
+#define DPP_REG_N_STEP(no) ((DPP_REG(no)).n_step)
+#define DPP_REG_FIELD_NUM(no) ((DPP_REG(no)).field_num)
+#define DPP_REG_FIELD_NAME(no, field_no) \
+	(((DPP_REG(no)).p_fields + field_no)->p_name)
+
+typedef enum dpp_bar_4k_e {
+	BAR_4K_DTB = 0, /**<  @brief 0*/
+	BAR_4K_ETCAM, /**<  @brief 1*/
+	BAR_4K_CLS0, /**<  @brief 2*/
+	BAR_4K_CLS1, /**<  @brief 3*/
+	BAR_4K_CLS2, /**<  @brief 4*/
+	BAR_4K_CLS3, /**<  @brief 5*/
+	BAR_4K_CLS4, /**<  @brief 6*/
+	BAR_4K_CLS5, /**<  @brief 7*/
+	BAR_4K_SE, /**<  @brief 8*/
+	BAR_4K_SMMU1, /**<  @brief 9*/
+	BAR_4K_MAX
+} DPP_BAR_4K_E;
+
+typedef struct {
+	ZXIC_UINT32 reg_module; /*DPP_MODULE_E*/
+	ZXIC_UINT32 index_4k; /*BAR NP空间映射4K相对索引*/
+	ZXIC_UINT32 addr_offset; /*寄存器偏移，用于计算BAR映射空间位置*/
+} DPP_REG_OFFSET_ADDR;
+
+/***********************************************************/
+/** 获取寄存器属性
+     * @param   reg_no  寄存器编号
+     *
+     * @return  DPP_OK-成功，DPP_ERR-失败
+     * @remark  无
+     * @see
+     * @author  王春雷      @date  2014/04/17
+     ************************************************************/
+DPP_REG_T *dpp_reg_info_get(ZXIC_UINT32 reg_no);
+
+/***********************************************************/
+/** 通用寄存器写函数
+     * @param   dev_id  设备号，支持多芯片
+     * @param   reg_no 寄存器编号
+     * @param   m_offset 二元寄存器的m偏移
+     * @param   n_offset 一元寄存器或二元寄存器的n偏移
+     * @param   p_data 数据指针
+     *
+     * @return  DPP_OK-成功，DPP_ERR-失败
+     * @remark  无
+     * @see
+     * @author  王春雷      @date  2014/02/12
+     ************************************************************/
+DPP_STATUS dpp_reg_write(DPP_DEV_T *dev, ZXIC_UINT32 reg_no,
+						 ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset,
+						 ZXIC_VOID *p_data);
+
+/***********************************************************/
+/** 通用寄存器读函数
+     * @param   dev_id 设备号，支持多芯片
+     * @param   reg_no 寄存器编号
+     * @param   m_offset 二元寄存器的m偏移
+     * @param   n_offset 一元寄存器或二元寄存器的n偏移
+     * @param   p_data 数据指针
+     *
+     * @return  DPP_OK-成功，DPP_ERR-失败
+     * @remark  无
+     * @see
+     * @author  王春雷      @date  2014/02/12
+     ************************************************************/
+DPP_STATUS dpp_reg_read(DPP_DEV_T *dev, ZXIC_UINT32 reg_no,
+						ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset,
+						ZXIC_VOID *p_data);
+
+/***********************************************************/
+/** 根据寄存器编号获得寄存器芯片内绝对地址
+     * @param   reg_no
+     * @param   m_offset
+     * @param   n_offset
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  王春雷      @date  2014/03/19
+     ************************************************************/
+ZXIC_UINT32 dpp_reg_get_reg_addr(ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset,
+								 ZXIC_UINT32 n_offset);
+
+/***********************************************************/
+/** 通过寄存器编号配置寄存器，仅适用于32bit位宽
+     的常规寄存器
+    * @param   dev_id  设备号
+    * @param   reg_no     寄存器编号
+    * @param   m_offset   二元寄存器的m偏移
+    * @param   n_offset   一元寄存器或二元寄存器的n偏移
+    * @param   data       数据，32bit
+    *
+    * @return  DPP_OK-成功，DPP_ERR-失败
+    * @remark  无
+    * @see
+    * @author  王春雷      @date  2015/01/21
+    ************************************************************/
+DPP_STATUS dpp_reg_write32(DPP_DEV_T *dev, ZXIC_UINT32 reg_no,
+						   ZXIC_UINT32 data);
+
+/***********************************************************/
+/** 通过寄存器编号读取寄存器的值，仅适用于32bit位宽的常规寄存器
+     * @param   dev_id   设备号
+     * @param   reg_no   寄存器编号
+     * @param   m_offset   二元寄存器的m偏移
+     * @param   n_offset   一元寄存器或二元寄存器的n偏移
+     * @param   p_data   出参，返回读取寄存器数值
+     *
+     * @return  DPP_OK-成功，DPP_ERR-失败
+     * @remark  无
+     * @see
+     * @author  石金锋      @date  2015/03/09
+     ************************************************************/
+DPP_STATUS dpp_reg_read32(DPP_DEV_T *dev, ZXIC_UINT32 reg_no,
+						  ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset,
+						  ZXIC_UINT32 *p_data);
+/***********************************************************/
+/** 判断是否为4K寄存器
+     * @param   reg_module
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  cq      @date  2023/11/29
+     ************************************************************/
+BOOLEAN dpp_4k_reg(ZXIC_UINT32 reg_module);
+/***********************************************************/
+/** 获取NP对应模块的映射地址偏移(riscv或者非4K寄存器不做转换，host根据映射情况做转换)
+     * @param   dev_id
+     * @param   reg_module
+     * @param   flags  标志位，DPP_REG_FLAG_INDIRECT DPP_REG_FLAG_DIRECT
+     * @param   addr
+     *
+     * @return  映射地址
+     * @remark  无
+     * @see
+     * @author  cq      @date  2023/11/29
+     ************************************************************/
+ZXIC_UINT32 dpp_reg_addr_convert(ZXIC_UINT32 dev_id, ZXIC_UINT32 reg_module,
+								 ZXIC_UINT32 flags, ZXIC_UINT32 addr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_se_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_se_api.h
old mode 100755
new mode 100644
index db5715cc01ca771d7cf479a79447af5308f384ed..e0a8adc4a7c4e8699378c15c25f0da383604fb6a
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_se_api.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_se_api.h
@@ -1,1386 +1,1400 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_se_api.h
-* 文件标识 : se模块对外数据类型定义和接口函数声明
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : wcl
-* 完成日期 : 2015/01/30
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-#ifndef _DPP_SE_API_H_
-#define _DPP_SE_API_H_
-
-#if ZXIC_REAL("header file")
- #include "dpp_type_api.h"  /* xcx_0619 */
-#endif
-
-#if ZXIC_REAL("data struct define")
-
-/** DPP+ 所有eram block 大小都变为2M  ~深度是16K */
-#define SE_SMMU0_ERAM_BLOCK_NUM            (32)
-#define SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK   (0x4000)
-#define SE_SMMU0_ERAM_ADDR_NUM_TOTAL       (SE_SMMU0_ERAM_BLOCK_NUM * SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK)
-
-#define DPP_DDR4_PER_BANK_BADDR_SETP       (0x800)/* 8G X16 */
-#define DPP_DDR4_BANK_NUM                  (64)
-#define DPP_DDR4_PER_BANK_BADDR_CONV(ddr4_phy_type) \
-    (DPP_DDR4_PER_BANK_BADDR_SETP*(4U>>ddr4_phy_type))
-
-/*普通上送上送类型*/
-typedef enum dpp_dma_ecc_en_e
-{
-    DMA_ECC_DISABLE  = 0,
-    DMA_ECC_ENABLE   = 1,
-} DPP_DMA_ECC_EN_E;
-
-/**  eRam表读请模式 */
-typedef enum dpp_eram128_rd_clr_mode_e
-{
-    RD_MODE_HOLD     = 0,  /**<  @brief 正常读，读完数据不清空   */
-    RD_MODE_CLEAR    = 1,  /**<  @brief 读清模式，返回eram中的值 */
-} DPP_ERAM128_RD_CLR_MODE_E;
-
-/**  eRam表cpu读写位宽模式*/
-typedef enum dpp_eram128_opr_mode_e
-{
-    ERAM128_OPR_128b = 0,  /**<  @brief 128bit模式读写eRam, 支持128bit读清模式*/
-    ERAM128_OPR_64b  = 1,  /**<  @brief 64bit模式读写eRam,  支持64bit  读清模式*/
-    ERAM128_OPR_1b   = 2,  /**<  @brief 1bit模式读写eRam,   不支持1bit  读清模式*/
-    ERAM128_OPR_32b  = 3   /**<  @brief 32bit模式读eRam,    不能用于写，支持32bit 读清模式*/
-} DPP_ERAM128_OPR_MODE_E;
-
-/**  eRam直接表位宽模式,也可用于eRam做结果表时的位宽  */
-typedef enum dpp_eram128_tbl_mode_e
-{
-    ERAM128_TBL_1b   = 0,  /**<  @brief 1bit   eRam片内直接表  */
-    ERAM128_TBL_32b  = 1,  /**<  @brief 32bit  eRam片内直接表  */
-    ERAM128_TBL_64b  = 2,  /**<  @brief 64bit  eRam片内直接表  */
-    ERAM128_TBL_128b = 3,  /**<  @brief 128bit eRam片内直接表  */
-    ERAM128_TBL_2b   = 4,  /**<  @brief 2bit   eRam片内直接表  */
-    ERAM128_TBL_4b   = 5,  /**<  @brief 4bit   eRam片内直接表  */
-    ERAM128_TBL_8b   = 6,  /**<  @brief 8bit   eRam片内直接表  */
-    ERAM128_TBL_16b  = 7   /**<  @brief 16bit  eRam片内直接表  */
-} DPP_ERAM128_TBL_MODE_E;
-
-/**  eRam查表通道*/
-typedef enum smmu0_empty_type_e
-{
-    SMMU0_EMPTY_CLS0 = 0,  /**<  @brief PPU cluster0通道*/
-    SMMU0_EMPTY_CLS1 = 1,  /**<  @brief PPU cluster1通道*/
-    SMMU0_EMPTY_CLS2 = 2,  /**<  @brief PPU cluster2通道*/
-    SMMU0_EMPTY_CLS3 = 3,  /**<  @brief PPU cluster3通道*/
-    SMMU0_EMPTY_CLS4 = 4,  /**<  @brief PPU cluster4通道*/
-    SMMU0_EMPTY_CLS5 = 5,  /**<  @brief PPU cluster5通道*/
-    SMMU0_EMPTY_CLS6 = 6,  /**<  @brief PPU cluster6通道*/
-    SMMU0_EMPTY_CLS7 = 7,  /**<  @brief PPU cluster7通道*/
-    SMMU0_EMPTY_MCAST = 8, /**<  @brief 组播复制表通道*/
-    SMMU0_EMPTY_ODMA  = 9, /**<  @brief ODMA保序计数通道*/
-} SMMU0_EMPTY_TYPE_E;
-
-/**  组播报文类型*/
-typedef enum smmu0_mcast_tbl_type_e
-{
-    MCAST_TDM = 0,         /**<  @brief TDM组播报文*/
-    MCAST_DATA = 1,        /**<  @brief 数据组播报文*/
-
-    MCAST_INVALID,         /**<  @brief 无效值 */
-} SMMU0_MCAST_TBL_TYPE_E;
-
-/** 调试计数读清模式 */
-typedef enum se_dbg_cnt_read_mode_e
-{
-    SE_DBG_CNT_READ_UNCLR = 0,  /**<  @brief 非读清模式 */
-    SE_DBG_CNT_READ_CLR,        /**<  @brief 读清模式 */
-} SE_DBG_CNT_READ_MODE_E;
-
-/** 调试计数溢出模式 */
-typedef enum se_dbg_cnt_overflow_mode_e
-{
-    SE_DBG_CNT_OVERFLOW_UNREVERSE = 0,  /**<  @brief 溢出保持 */
-    SE_DBG_CNT_OVERFLOW_REVERSE,        /**<  @brief 溢出翻转 */
-} SE_DBG_CNT_OVERFLOW_MODE_E;
-
-/**  DDR颗粒类型*/
-typedef enum se_ddr_phy_cfg_type_e
-{
-    DPP_SE_DDR_PHY_32G_16 = 0,  /**<  @brief DDR颗粒每组32G容量,x16颗粒*/
-    DPP_SE_DDR_PHY_16G_16,      /**<  @brief DDR颗粒每组16G容量,x16颗粒*/
-    DPP_SE_DDR_PHY_8G_16,       /**<  @brief DDR颗粒每组8G容量,x16颗粒*/
-    DPP_SE_DDR_PHY_4G_16,       /**<  @brief DDR颗粒每组4G容量,x16颗粒*/
-    DPP_SE_DDR_PHY_32G_8,       /**<  @brief DDR颗粒每组32G容量,x8颗粒*/
-    DPP_SE_DDR_PHY_16G_8,       /**<  @brief DDR颗粒每组16G容量,x8颗粒*/
-    DPP_SE_DDR_PHY_8G_8,        /**<  @brief DDR颗粒每组8G容量,x8颗粒*/
-    DPP_SE_DDR_PHY_4G_8,        /**<  @brief DDR颗粒每组4G容量,x8颗粒*/
-    DPP_SE_DDR_PHY_MAX,
-} SE_DDR_PHY_CFG_TYPE_E;
-
-/**  DDR表写数据位宽模式*/
-typedef enum smmu1_ddr_wrt_mode_e
-{
-    SMMU1_DDR_WRT_128b = 0,  /**<  @brief 128bit模式写DDR*/
-    SMMU1_DDR_WRT_256b = 1,  /**<  @brief 256bit模式写DDR*/
-    SMMU1_DDR_WRT_384b = 2,  /**<  @brief 384bit模式写DDR*/
-    SMMU1_DDR_WRT_512b = 3,  /**<  @brief 512bit模式写DDR*/
-} SMMU1_DDR_WRT_MODE_E;
-
-/** DDR表的共享模式 */
-typedef enum smmu1_ddr_share_mode_e
-{
-    SMMU1_DDR_SHARE_NO_SHARE    = 0,    /**<  @brief SE 占用整个DDR*/
-    SMMU1_DDR_SHARE_1_2         = 1,    /**<  @brief SE 占用1/2 DDR*/
-    SMMU1_DDR_SHARE_1_4         = 2,    /**<  @brief SE 占用1/4 DDR*/
-    SMMU1_DDR_SHARE_1_8         = 3,    /**<  @brief SE 占用1/8 DDR*/
-    SMMU1_DDR_SHARE_MAX
-} SMMU1_DDR_SHARE_MODE_E;
-
-/** 占用smmu1的表类型 */
-typedef enum smmu1_ddr_tbl_type_e
-{
-    SMMU1_DDR_TBL_TYPE_DIR_TBL         = 0,    /**<  @brief 片外直接表 */
-    SMMU1_DDR_TBL_TYPE_HASH_TBL        = 1,    /**<  @brief HASH占用表 */
-    SMMU1_DDR_TBL_TYPE_LPM_TBL         = 2,    /**<  @brief LPM 占用表  */
-    SMMU1_DDR_TBL_TYPE_OAM_TBL         = 3,    /**<  @brief OAM 占用表  */
-    SMMU1_DDR_TBL_TYPE_FTM_TBL         = 4,    /**<  @brief FTM 占用表  */
-    SMMU1_DDR_TBL_TYPE_ETM_TBL         = 5,    /**<  @brief ETM 占用表  */
-    SMMU1_DDR_TBL_TYPE_MAX
-} SMMU1_DDR_TBL_TYPE_E;
-
-typedef enum cmmu_rd_mode_e
-{
-    CMMU_RD_MODE_29_35  = 0,
-    CMMU_RD_MODE_32     = 1,
-    CMMU_RD_MODE_64     = 2,
-    CMMU_RD_MODE_128    = 3,
-    CMMU_RD_MODE_MAX,
-} CMMU_RD_OPR_MODE_E;
-
-/**  CMMU读请模式 */
-typedef enum cmmu_rd_clr_mode_e
-{
-    CMMU_RD_CLR_MODE_UNCLR     = 0,  /**<  @brief 正常读，读完数据不清空   */
-    CMMU_RD_CLR_MODE_CLR       = 1,  /**<  @brief 读清模式*/
-    CMMU_RD_CLR_MODE_MAX,
-} CMMU_RD_CLR_MODE_E;
-
-/**  DDR表读数据位宽模式*/
-typedef enum smmu1_ddr_srh_mode_e
-{
-    SMMU1_DDR_SRH_128b  = 0, /**<  @brief 访问DDR，以128bit模式返回数据*/
-    SMMU1_DDR_SRH_256b,      /**<  @brief 访问DDR，以256bit模式返回数据*/
-    SMMU1_DDR_SRH_512b,      /**<  @brief 访问DDR，以512bit模式返回数据*/
-    SMMU1_DDR_SRH_MAX
-} SMMU1_DDR_SRH_MODE_E;
-
-/**  DDR地址映射参数*/
-typedef struct se_ddr_addr_map_info_t
-{
-    ZXIC_UINT32 is_inited;            /**<  @brief 用于检测此结构体是否已经经过初始化 0xAA-已经初始化 其他值-未初始化 */
-    ZXIC_UINT32 ddr_phy_type;         /**<  @brief DDR颗粒类型 0-32G,x16颗粒,1-16G,x16颗粒,2-8G,x16颗粒 */
-    ZXIC_UINT32 se_use_bank_num;      /**<  @brief SE使用的bank数目 */
-    ZXIC_UINT32 bank_used_sate[64];   /**<  @brief 表示64个bank的使用状态 0-不存在 1-SE使用 2-PUB使用 3-FTM使用 4-ETM使用  */
-} SE_DDR_ADDR_MAP_INFO_T;
-
-/**  se从ppu接收的查表请求排空状态*/
-typedef struct dpp_se_ept_flag_t
-{
-    ZXIC_UINT32 ppu5_ept_flag; /**<  @brief se从ppu通道5接收的查表请求排空状态*/
-    ZXIC_UINT32 ppu4_ept_flag; /**<  @brief se从ppu通道4接收的查表请求排空状态*/
-    ZXIC_UINT32 ppu3_ept_flag; /**<  @brief se从ppu通道3接收的查表请求排空状态*/
-    ZXIC_UINT32 ppu2_ept_flag; /**<  @brief se从ppu通道2接收的查表请求排空状态*/
-    ZXIC_UINT32 ppu1_ept_flag; /**<  @brief se从ppu通道1接收的查表请求排空状态*/
-    ZXIC_UINT32 ppu0_ept_flag; /**<  @brief se从ppu通道0接收的查表请求排空状态*/
-} DPP_SE_EPT_FLAG_T;
-
-/**  smmu0(eRam)各通道查表请求排空状态*/
-typedef struct dpp_smmu0_ept_flag_t
-{
-    ZXIC_UINT32 ept_flag8; /**<  @brief odam请求排空状态*/
-    ZXIC_UINT32 ept_flag7; /**<  @brief odam tdm请求排空状态*/
-    ZXIC_UINT32 ept_flag6; /**<  @brief sa组播份数表请求排空状态*/
-    ZXIC_UINT32 ept_flag5; /**<  @brief ppu通道5查表请求排空状态*/
-    ZXIC_UINT32 ept_flag4; /**<  @brief ppu通道4查表请求排空状态*/
-    ZXIC_UINT32 ept_flag3; /**<  @brief ppu通道3查表请求排空状态*/
-    ZXIC_UINT32 ept_flag2; /**<  @brief ppu通道2查表请求排空状态*/
-    ZXIC_UINT32 ept_flag1; /**<  @brief ppu通道1查表请求排空状态*/
-    ZXIC_UINT32 ept_flag0; /**<  @brief ppu通道0查表请求排空状态*/
-} DPP_SMMU0_EPT_FLAG_T;
-
-/**  SMMU0保序FIFO写满读空中断原因*/
-typedef struct dpp_se_smmu0_int0_t
-{
-    ZXIC_UINT32 dma_ordfifo;    /**<  @brief DMA保序fifo 写满读空标志*/
-    ZXIC_UINT32 odma_ordfifo;   /**<  @brief ODMA保序fifo 写满读空标志*/
-    ZXIC_UINT32 mcast_ordfifo;  /**<  @brief MCAST保序fifo 写满读空标志*/
-} DPP_SE_SMMU0_INT0_T;
-
-/* 数据组播报文类型 */
-typedef struct data_mcast_t_
-{
-    ZXIC_UINT8   valid;             /**< @brief valid 表示是否可用 */
-    ZXIC_UINT8   rsv;               /**< @brief rsv   保留位，字节对齐使用,勿需关心 */
-    ZXIC_UINT16 mc_cnt;            /**< @brief mc_cnt 16bit */
-} DATA_MCAST_T;
-
-/* TDM 组播报文类型 */
-typedef struct tdm_mcast_t_
-{
-    ZXIC_UINT8   valid;             /**< @brief valid 表示是否可用 */
-    ZXIC_UINT8   rsv;               /**< @brief rsv   保留位，字节对齐使用，勿需关心 */
-    ZXIC_UINT8   bitmap[6];         /**< @brief bitmap[0]是最高位，bitmap[2]是最低位 */
-} TDM_MCAST_T;
-
-#endif
-
-#if ZXIC_REAL("eTcam data struct define")
-
-#endif
-
-#if ZXIC_REAL("interrupt data struct define")
-/** SMMU0 中断状态 */
-typedef struct dpp_se_smmu0_int_t
-{
-    ZXIC_UINT32 smmu0_int0;
-    ZXIC_UINT32 smmu0_int1;
-    ZXIC_UINT32 smmu0_int2;
-    ZXIC_UINT32 smmu0_int3;
-    ZXIC_UINT32 smmu0_int4;
-    ZXIC_UINT32 smmu0_int5;
-    ZXIC_UINT32 smmu0_int6;
-    ZXIC_UINT32 smmu0_int7;
-    ZXIC_UINT32 smmu0_int8;
-    ZXIC_UINT32 smmu0_int9;
-    ZXIC_UINT32 smmu0_int10;
-    ZXIC_UINT32 smmu0_int11;
-    ZXIC_UINT32 smmu0_int12;
-    ZXIC_UINT32 smmu0_int13;
-    ZXIC_UINT32 smmu0_int14;
-    ZXIC_UINT32 smmu0_int15;
-    ZXIC_UINT32 smmu0_int16;
-    ZXIC_UINT32 smmu0_int17;
-    ZXIC_UINT32 smmu0_int18;
-    ZXIC_UINT32 smmu0_int19;
-    ZXIC_UINT32 smmu0_int20;
-    ZXIC_UINT32 smmu0_int21;
-    ZXIC_UINT32 smmu0_int22;
-    ZXIC_UINT32 smmu0_int23;
-    ZXIC_UINT32 smmu0_int24;
-    ZXIC_UINT32 smmu0_int25;
-    ZXIC_UINT32 smmu0_int26;
-    ZXIC_UINT32 smmu0_int27;
-    ZXIC_UINT32 smmu0_int28;
-    ZXIC_UINT32 smmu0_int29;
-    ZXIC_UINT32 smmu0_int30;
-    ZXIC_UINT32 smmu0_int31;
-    ZXIC_UINT32 smmu0_int32;
-    ZXIC_UINT32 smmu0_int33;
-    ZXIC_UINT32 smmu0_int34;
-    ZXIC_UINT32 smmu0_int35;
-    ZXIC_UINT32 smmu0_int36;
-    ZXIC_UINT32 smmu0_int37;
-    ZXIC_UINT32 smmu0_int38;
-
-}DPP_SE_SMMU0_INT_T;
-
-/** SMMU0 模块总的中断状态 */
-typedef struct dpp_smmu0_brief_int_t
-{
-    ZXIC_UINT32 smmu0_int14_unmask_flag;
-    ZXIC_UINT32 smmu0_int13_unmask_flag;
-    ZXIC_UINT32 smmu0_int12_unmask_flag;
-    ZXIC_UINT32 smmu0_int11_unmask_flag;
-    ZXIC_UINT32 smmu0_int10_unmask_flag;
-    ZXIC_UINT32 smmu0_int9_unmask_flag;
-    ZXIC_UINT32 smmu0_int8_unmask_flag;
-    ZXIC_UINT32 smmu0_int7_unmask_flag;
-    ZXIC_UINT32 smmu0_int6_unmask_flag;
-    ZXIC_UINT32 smmu0_int5_unmask_flag;
-    ZXIC_UINT32 smmu0_int4_unmask_flag;
-    ZXIC_UINT32 smmu0_int3_unmask_flag;
-    ZXIC_UINT32 smmu0_int2_unmask_flag;
-    ZXIC_UINT32 smmu0_int1_unmask_flag;
-    ZXIC_UINT32 smmu0_int0_unmask_flag;
-} DPP_SMMU0_BRIEF_INT_T;
-
-/** SE 模块总的中断状态 */
-typedef struct dpp_se_int_status_t
-{
-    ZXIC_UINT32 as_int_unmask_flag;      /**< @brief 级联查找模块（AS）总中断状态 */
-    ZXIC_UINT32 kschd_int_unmask_flag;   /**< @brief 键值调度模块（KSCHD）总中断状态 */
-    ZXIC_UINT32 rschd_int_unmask_flag;   /**< @brief 返回调度模块（RSCHD）总中断状态 */
-    ZXIC_UINT32 smmu1_int_unmask_flag;  /**< @brief SMMU1 中断总中断状态 */
-    ZXIC_UINT32 cmmu_int_unmask_flag;    /**< @brief CMMU  总中断状态 */
-    ZXIC_UINT32 parser_int_unmask_flag;  /**< @brief 解析模块（parse）总中断状态 */
-} DPP_SE_INT_STATUS_T;
-
-/** se解析模块中断状态 */
-typedef struct dpp_se_parser_int_t
-{
-    ZXIC_UINT32 parser_int_en;
-    ZXIC_UINT32 parser_int_mask;
-    ZXIC_UINT32 parser_int_status;
-} DPP_SE_PARSER_INT_T;
-
-/** key调度模块(KSCHD)中断状态 */
-typedef struct dpp_se_kschd_int_t
-{
-    ZXIC_UINT32 kschd_int_0;
-    ZXIC_UINT32 kschd_int_1;
-    ZXIC_UINT32 kschd_int_2;
-    ZXIC_UINT32 kschd_int_3;
-    ZXIC_UINT32 kschd_int_4;
-} DPP_SE_KSCHD_INT_T;
-
-/** rsp调度模块(RSCHD)中断状态 */
-typedef struct dpp_se_rschd_int_t
-{
-    ZXIC_UINT32 port0_int;
-    ZXIC_UINT32 port1_int;
-} DPP_SE_RSCHD_INT_T;
-
-/**  关联查找(AS)模块的中断原因*/
-typedef struct dpp_se_as_int_t
-{
-    ZXIC_UINT32 as_int_0;
-    ZXIC_UINT32 as_int_1;
-    ZXIC_UINT32 as_int_2;
-} DPP_SE_AS_INT_T;
-
-/** cmmu 模块中断*/
-typedef struct dpp_se_cmmu_int_t
-{
-    ZXIC_UINT32 cmmu_int12;
-    ZXIC_UINT32 cmmu_int11;
-    ZXIC_UINT32 cmmu_int10;
-    ZXIC_UINT32 cmmu_int9;
-    ZXIC_UINT32 cmmu_int8;
-    ZXIC_UINT32 cmmu_int7;
-    ZXIC_UINT32 cmmu_int6;
-    ZXIC_UINT32 cmmu_int5;
-    ZXIC_UINT32 cmmu_int4;
-    ZXIC_UINT32 cmmu_int3;
-    ZXIC_UINT32 cmmu_int2;
-    ZXIC_UINT32 cmmu_int1;
-    ZXIC_UINT32 cmmu_int0;
-} DPP_SE_CMMU_INT_T;
-
-/** ALG 模块中断*/
-typedef struct dpp_se_alg_int_t
-{
-    ZXIC_UINT32 wr_rsp_fifo_ovfl_int;              /**< @brief 写返回缓存ptr fifo 溢出中断上报 */
-    ZXIC_UINT32 init_rd_cft_int;                /**< @brief 初始化过程中出现读命令，冲突中断 */
-    ZXIC_UINT32 schd_lpm_fifo_parity_err_int;     /**< @brief 调度lpm缓存FIFO奇偶校验错误上报 */
-    ZXIC_UINT32 schd_hash3_fifo_parity_err_int;    /**< @brief 调度hash3缓存FIFO奇偶校验错误上报 */
-    ZXIC_UINT32 schd_hash2_fifo_parity_err_int;    /**< @brief 调度hash2缓存FIFO奇偶校验错误上报 */
-    ZXIC_UINT32 schd_hash1_fifo_parity_err_int;    /**< @brief 调度hash1缓存FIFO奇偶校验错误上报 */
-    ZXIC_UINT32 schd_hash0_fifo_parity_err_int;    /**< @brief 调度hash0缓存FIFO奇偶校验错误上报 */
-    ZXIC_UINT32 schd_learn_fifo_parity_err_int;    /**< @brief 调度学习缓存FIFO奇偶校验错误上报 */
-    ZXIC_UINT32 schd_lpm_fifo_ovfl_int;            /**< @brief 调度lpm键值缓存FIFO溢出中断上报 */
-    ZXIC_UINT32 schd_hash3_fifo_ovfl_int;          /**< @brief 调度hash3键值缓存FIFO溢出中断上报 */
-    ZXIC_UINT32 schd_hash2_fifo_unfl_int;          /**< @brief 调度hash2键值缓存FIFO溢出中断上报 */
-    ZXIC_UINT32 schd_hash1_fifo_ovfl_int;          /**< @brief 调度hash1键值缓存FIFO溢出中断上报 */
-    ZXIC_UINT32 schd_hash0_fifo_ovfl_int;          /**< @brief 调度hash0键值缓存FIFO溢出中断上报 */
-    ZXIC_UINT32 schd_learn_fifo_ovfl_int;          /**< @brief 调度学习命令缓存FIFO溢出中断上报 */
-
-    ZXIC_UINT32 zblk31_parity_int;           /**< @brief zblock31  parity 中断 */
-    ZXIC_UINT32 zblk30_parity_int;           /**< @brief zblock30  parity 中断 */
-    ZXIC_UINT32 zblk29_parity_int;           /**< @brief zblock29  parity 中断 */
-    ZXIC_UINT32 zblk28_parity_int;           /**< @brief zblock28  parity 中断 */
-    ZXIC_UINT32 zblk27_parity_int;           /**< @brief zblock27  parity 中断 */
-    ZXIC_UINT32 zblk26_parity_int;           /**< @brief zblock26  parity 中断 */
-    ZXIC_UINT32 zblk25_parity_int;           /**< @brief zblock25  parity 中断 */
-    ZXIC_UINT32 zblk24_parity_int;           /**< @brief zblock24  parity 中断 */
-    ZXIC_UINT32 zblk23_parity_int;           /**< @brief zblock23  parity 中断 */
-    ZXIC_UINT32 zblk22_parity_int;           /**< @brief zblock22  parity 中断 */
-    ZXIC_UINT32 zblk21_parity_int;           /**< @brief zblock21  parity 中断 */
-    ZXIC_UINT32 zblk20_parity_int;           /**< @brief zblock20  parity 中断 */
-    ZXIC_UINT32 zblk19_parity_int;           /**< @brief zblock19  parity 中断 */
-    ZXIC_UINT32 zblk18_parity_int;           /**< @brief zblock18  parity 中断 */
-    ZXIC_UINT32 zblk17_parity_int;           /**< @brief zblock17  parity 中断 */
-    ZXIC_UINT32 zblk16_parity_int;           /**< @brief zblock16  parity 中断 */
-    ZXIC_UINT32 zblk15_parity_int;           /**< @brief zblock15  parity 中断 */
-    ZXIC_UINT32 zblk14_parity_int;           /**< @brief zblock14  parity 中断 */
-    ZXIC_UINT32 zblk13_parity_int;           /**< @brief zblock13  parity 中断 */
-    ZXIC_UINT32 zblk12_parity_int;           /**< @brief zblock12  parity 中断 */
-    ZXIC_UINT32 zblk11_parity_int;           /**< @brief zblock11  parity 中断 */
-    ZXIC_UINT32 zblk10_parity_int;           /**< @brief zblock10  parity 中断 */
-    ZXIC_UINT32 zblk9_parity_int;            /**< @brief zblock9   parity 中断 */
-    ZXIC_UINT32 zblk8_parity_int;            /**< @brief zblock8   parity 中断 */
-    ZXIC_UINT32 zblk7_parity_int;            /**< @brief zblock7   parity 中断 */
-    ZXIC_UINT32 zblk6_parity_int;            /**< @brief zblock6   parity 中断 */
-    ZXIC_UINT32 zblk5_parity_int;            /**< @brief zblock5   parity 中断 */
-    ZXIC_UINT32 zblk4_parity_int;            /**< @brief zblock4   parity 中断 */
-    ZXIC_UINT32 zblk3_parity_int;            /**< @brief zblock3   parity 中断 */
-    ZXIC_UINT32 zblk2_parity_int;            /**< @brief zblock2   parity 中断 */
-    ZXIC_UINT32 zblk1_parity_int;            /**< @brief zblock1   parity 中断 */
-    ZXIC_UINT32 zblk0_parity_int;            /**< @brief zblock0   parity 中断 */
-
-    ZXIC_UINT32 zcam_hash_p0_err_int;                 /**< @brief hash0 ZCAM查找出错中断 */
-    ZXIC_UINT32 hash0_agree_int_fifo_ovf_int;         /**< @brief hash0 汇聚fifo 片内通道溢出中断 */
-    ZXIC_UINT32 hash0_agree_ext_fifo_ovf_int;         /**< @brief hash0 汇聚fifo 片外通道parity中断 */
-    ZXIC_UINT32 hash0_agree_ext_fifo_parity_err_int;  /**< @brief hash0 汇聚fifo 片外通道溢出中断*/
-    ZXIC_UINT32 hash0_agree_int_fifo_parity_err_int;  /**< @brief hash0 汇聚fifo 片内通道parity中断 */
-    ZXIC_UINT32 hash0_key_fifo_ovfl_int;              /**< @brief hash0 片外键值缓存FIFO 溢出中断 */
-    ZXIC_UINT32 hash0_sreq_fifo_ovfl_int;             /**< @brief hash0 片外读地址缓存FIFO溢出中断 */
-    ZXIC_UINT32 hash0_key_fifo_parity_err_int;        /**< @brief hash0 片外键值缓存FIFO parity err中断 */
-
-    ZXIC_UINT32 zcam_hash_p1_err_int;                 /**< @brief hash1 ZCAM查找出错中断 */
-    ZXIC_UINT32 hash1_agree_int_fifo_ovf_int;         /**< @brief hash1 汇聚fifo 片内通道溢出中断 */
-    ZXIC_UINT32 hash1_agree_ext_fifo_ovf_int;         /**< @brief hash1 汇聚fifo 片外通道parity中断 */
-    ZXIC_UINT32 hash1_agree_ext_fifo_parity_err_int;  /**< @brief hash1 汇聚fifo 片外通道溢出中断*/
-    ZXIC_UINT32 hash1_agree_int_fifo_parity_err_int;  /**< @brief hash1 汇聚fifo 片内通道parity中断 */
-    ZXIC_UINT32 hash1_key_fifo_ovfl_int;              /**< @brief hash1 片外键值缓存FIFO 溢出中断 */
-    ZXIC_UINT32 hash1_sreq_fifo_ovfl_int;             /**< @brief hash1 片外读地址缓存FIFO溢出中断 */
-    ZXIC_UINT32 hash1_key_fifo_parity_err_int;        /**< @brief hash1 片外键值缓存FIFO parity err中断 */
-
-    ZXIC_UINT32 zcam_hash_p2_err_int;                 /**< @brief hash2 ZCAM查找出错中断 */
-    ZXIC_UINT32 hash2_agree_int_fifo_ovf_int;         /**< @brief hash2 汇聚fifo 片内通道溢出中断 */
-    ZXIC_UINT32 hash2_agree_ext_fifo_ovf_int;         /**< @brief hash2 汇聚fifo 片外通道parity中断 */
-    ZXIC_UINT32 hash2_agree_ext_fifo_parity_err_int;  /**< @brief hash2 汇聚fifo 片外通道溢出中断*/
-    ZXIC_UINT32 hash2_agree_int_fifo_parity_err_int;  /**< @brief hash2 汇聚fifo 片内通道parity中断 */
-    ZXIC_UINT32 hash2_key_fifo_ovfl_int;              /**< @brief hash2 片外键值缓存FIFO 溢出中断 */
-    ZXIC_UINT32 hash2_sreq_fifo_ovfl_int;             /**< @brief hash2 片外读地址缓存FIFO溢出中断 */
-    ZXIC_UINT32 hash2_key_fifo_parity_err_int;        /**< @brief hash2 片外键值缓存FIFO parity err中断 */
-
-    ZXIC_UINT32 zcam_hash_p3_err_int;                 /**< @brief hash3 ZCAM查找出错中断 */
-    ZXIC_UINT32 hash3_agree_int_fifo_ovf_int;         /**< @brief hash3 汇聚fifo 片内通道溢出中断 */
-    ZXIC_UINT32 hash3_agree_ext_fifo_ovf_int;         /**< @brief hash3 汇聚fifo 片外通道parity中断 */
-    ZXIC_UINT32 hash3_agree_ext_fifo_parity_err_int;  /**< @brief hash3 汇聚fifo 片外通道溢出中断*/
-    ZXIC_UINT32 hash3_agree_int_fifo_parity_err_int;  /**< @brief hash3 汇聚fifo 片内通道parity中断 */
-    ZXIC_UINT32 hash3_key_fifo_ovfl_int;              /**< @brief hash3 片外键值缓存FIFO 溢出中断 */
-    ZXIC_UINT32 hash3_sreq_fifo_ovfl_int;             /**< @brief hash3 片外读地址缓存FIFO溢出中断 */
-    ZXIC_UINT32 hash3_key_fifo_parity_err_int;        /**< @brief hash3 片外键值缓存FIFO parity err中断 */
-
-    ZXIC_UINT32 zcam_lpm_err_int;                     /**< @brief lpm ZCAM查找出错中断 */
-    ZXIC_UINT32 lpm_as_int_rsp_fifo_ovfl_int;         /**< @brief lpm as 片内查找结果缓存FIFO溢出中断 */
-    ZXIC_UINT32 lpm_as_req_fifo_ovfl_int;             /**< @brief lpm as 查找ddr 地址 FIFO溢出中断 */
-    ZXIC_UINT32 lpm_ext_ddr_rsp_fifo_parity_int;      /**< @brief lpm ext ddr rsp FIFO parity中断 */
-    ZXIC_UINT32 lpm_ext_v6_key_parity_int;            /**< @brief lpm ext v6 key FIFO parity中断 */
-    ZXIC_UINT32 lpm_ext_v4_key_parity_int;            /**< @brief lpm ext v4 key FIFO parity中断 */
-    ZXIC_UINT32 lpm_ext_addr_fifo_ovfl_int;           /**< @brief lpm ext ddr3 地址溢出中断 */
-    ZXIC_UINT32 lpm_ext_v4_fifo_ovfl_int;             /**< @brief lpm ext v4 key溢出中断 */
-    ZXIC_UINT32 lpm_ext_v6_fifo_ovfl_int;             /**< @brief lpm ext v6 key溢出中断 */
-    ZXIC_UINT32 lpm_ext_ddr_rsp_ovf_int;              /**< @brief lpm ext ddr返回缓存fifo溢出中断 */
-} DPP_SE_ALG_INT_T;
-
-/** ALG 模块对外总中断*/
-typedef struct dpp_se_alg_brief_int_t
-{
-    ZXIC_UINT32 schd_int_unmask_flag;        /**<@brief alg模块调度状态 */
-    ZXIC_UINT32 zblk_parity_int_unmask_flag; /**<@brief alg模块zblock奇偶校验中断 */
-    ZXIC_UINT32 hash0_int_unmask_flag;       /**<@brief alg模块hash0中断状态 */
-    ZXIC_UINT32 hash1_int_unmask_flag;       /**<@brief alg模块hash1中断状态 */
-    ZXIC_UINT32 hash2_int_unmask_flag;       /**<@brief alg模块hash2中断状态 */
-    ZXIC_UINT32 hash3_int_unmask_flag;       /**<@brief alg模块hash3中断状态 */
-    ZXIC_UINT32 lpm_int_unmask_flag;         /**<@brief alg模块lpm中断状态 */
-} DPP_SE_ALG_BRIEF_INT_T;
-
-/** SMMU1 中断 */
-typedef struct dpp_se_smmu1_int_t
-{
-    ZXIC_UINT32 smmu1_int0;
-    ZXIC_UINT32 smmu1_int1;
-    ZXIC_UINT32 smmu1_int2;
-    ZXIC_UINT32 smmu1_int3;
-    ZXIC_UINT32 smmu1_int4;
-    ZXIC_UINT32 smmu1_int5;
-    ZXIC_UINT32 smmu1_int6;
-    ZXIC_UINT32 smmu1_int7;
-    ZXIC_UINT32 smmu1_int8;
-    ZXIC_UINT32 smmu1_int9;
-    ZXIC_UINT32 smmu1_int10;
-    ZXIC_UINT32 smmu1_int11;
-    ZXIC_UINT32 smmu1_int12;
-    ZXIC_UINT32 smmu1_int13;
-    ZXIC_UINT32 smmu1_int14;
-    ZXIC_UINT32 smmu1_int15;
-    ZXIC_UINT32 smmu1_int16;
-    ZXIC_UINT32 smmu1_int17;
-} DPP_SE_SMMU1_INT_T;
-
-typedef struct dpp_etcam_intr_t
-{
-    ZXIC_UINT32 etcam_int_33;
-    ZXIC_UINT32 etcam_int_32;
-    ZXIC_UINT32 etcam_int_31;
-    ZXIC_UINT32 etcam_int_30;
-    ZXIC_UINT32 etcam_int_29;
-    ZXIC_UINT32 etcam_int_28;
-    ZXIC_UINT32 etcam_int_27;
-    ZXIC_UINT32 etcam_int_26;
-    ZXIC_UINT32 etcam_int_25;
-    ZXIC_UINT32 etcam_int_24;
-    ZXIC_UINT32 etcam_int_23;
-    ZXIC_UINT32 etcam_int_22;
-    ZXIC_UINT32 etcam_int_21;
-    ZXIC_UINT32 etcam_int_20;
-    ZXIC_UINT32 etcam_int_19;
-    ZXIC_UINT32 etcam_int_18;
-    ZXIC_UINT32 etcam_int_17;
-    ZXIC_UINT32 etcam_int_16;
-    ZXIC_UINT32 etcam_int_15;
-    ZXIC_UINT32 etcam_int_14;
-    ZXIC_UINT32 etcam_int_13;
-    ZXIC_UINT32 etcam_int_12;
-    ZXIC_UINT32 etcam_int_11;
-    ZXIC_UINT32 etcam_int_10;
-    ZXIC_UINT32 etcam_int_9;
-    ZXIC_UINT32 etcam_int_8;
-    ZXIC_UINT32 etcam_int_7;
-    ZXIC_UINT32 etcam_int_6;
-    ZXIC_UINT32 etcam_int_5;
-    ZXIC_UINT32 etcam_int_4;
-    ZXIC_UINT32 etcam_int_3;
-    ZXIC_UINT32 etcam_int_2;
-    ZXIC_UINT32 etcam_int_1;
-    ZXIC_UINT32 etcam_int_0;
-} DPP_ETCAM_INTR_T;
-
-typedef struct dpp_se_stat_int_t
-{
-    ZXIC_UINT32 stat_int0;
-    ZXIC_UINT32 stat_int1;
-    ZXIC_UINT32 stat_int2;
-    ZXIC_UINT32 stat_int3;
-    ZXIC_UINT32 stat_int4;
-    ZXIC_UINT32 stat_int5;
-} DPP_SE_STAT_INT_T;
-
-#endif
-
-#if ZXIC_REAL("macro function define")
-
-#endif
-
-#if ZXIC_REAL("function declaration")
-/***********************************************************/
-/** 读eRam
-* @param   dev_id       设备号
-* @param   base_addr    基地址，以128bit为单位
-* @param   index        条目索引,支持128、64、32和1bit的索引值
-* @param   rd_mode      读eRam模式, 取值参照ERAM128_OPR_MODE_E定义，读清模式下不支持1bit模式
-* @param   rd_clr_mode  eRam读清模式, 取值参照ERAM128_RD_CLR_MODE_E定义
-* @param   p_data       返回数据缓存的指针
-*
-* @return
-* @remark  无
-* @see
-* @author  wcl      @date  2015/01/30
-************************************************************/
-DPP_STATUS dpp_se_smmu0_ind_read(DPP_DEV_T *dev, ZXIC_UINT32 base_addr, ZXIC_UINT32 index, ZXIC_UINT32 rd_mode, ZXIC_UINT32 rd_clr_mode, ZXIC_UINT32 *p_data);
-
-#endif
-
-#if ZXIC_REAL("Hash & LPM data struct and function")
-
-/** lpm&hash算法模块硬件读写函数指针类型 */
-typedef DPP_STATUS (*WRITE32_FUN)(ZXIC_UINT32 dev_id, ZXIC_UINT32 addr, ZXIC_UINT32 write_data);
-typedef DPP_STATUS (*READ32_FUN) (ZXIC_UINT32 dev_id, ZXIC_UINT32 addr, ZXIC_UINT32 *read_data);
-
-/**  前缀匹配路由关联结果表写硬件函数指针类型*/
-typedef DPP_STATUS (*LPM_AS_RSLT_WRT_FUNCTION)(ZXIC_UINT32 dev_id, ZXIC_UINT32 as_type, ZXIC_UINT32 tbl_id, ZXIC_UINT32 index, ZXIC_UINT8 *p_data);
-
-#define     SE_ZGRP_NUM         (4)
-#define     SE_ZBLK_NUM         (32)
-#define     SE_ZCELL_NUM        (4)
-#define     SE_ZCELL_TOTAL_NUM  (SE_ZBLK_NUM * SE_ZCELL_NUM)
-#define     SE_ZREG_NUM         (4)
-#define     SE_RAM_DEPTH        (512)
-#define     MAX_FUN_NUM         (8)
-#define     SE_ALG_BANK_NUM     (29)
-
-#define LPM_THREAD_HW_WRITE_EN             (0)      /* ??????????????? */
-#if LPM_THREAD_HW_WRITE_EN
-#define ROUTE_DEV_CHANNEL_MAX              (4)      /* ?????? NPE_DEV_CHANNEL_MAX ??????? */
-#define MAX_ITEM_INFO_BAK_NUM              (0x100)  
-#endif
-/*
-*    zcell/zreg 基本存储单元的配置信息,512bit为单位，
-*    zcell包含512个基本存储单元，zreg包含4个基本存储单元，
-*    每个单元可以存储1个512bit条目、2个256bit条目或4个128bit条目，
-*    本结构体不感知内部存储条目的位宽，hash中键值中的key_type可以
-*    可以获取表项的位宽信息
-*/
-typedef struct se_item_cfg
-{
-    D_HEAD  item_list;      /** 基本存储单元双链表头节点，可以存放放在本单元内的具体表项条目*/
-    ZXIC_UINT32  item_index;     /** 基本存储单元所处的索引值 */
-    ZXIC_UINT32  hw_addr;        /** 基本存储单元物理的地址 */
-    ZXIC_UINT32  bulk_id;
-    ZXIC_UINT32  item_type;      /** 基本存储单元的存储类型，包括片外或片内，参见SE_ITEM_TYPE */
-    ZXIC_UINT8    wrt_mask;       /** 基本存储单元写入的掩码，4bit，每bit表示待写入的128bit位置 */
-    ZXIC_UINT8    valid;          /** 基本存储单元是否被占用，0-未被占用，1-被占用 */
-    ZXIC_UINT8    pad[2];
-} SE_ITEM_CFG;
-
-/**  zcell属性标志*/
-#define DPP_ZCELL_FLAG_IS_MONO       (1) /**<  @brief ZCELL是否被独占: 0-未被独占，1-已经被独占*/
-
-/**  zcell属性标志*/
-#define DPP_ZREG_FLAG_IS_MONO        (1) /**<  @brief ZREG是否被独占:  0-未被独占，1-已经被独占*/
-
-/* zcell 的配置信息*/
-typedef struct se_zcell_cfg
-{
-    ZXIC_UINT8            flag;           /* zcell属性标志，各比特的含义见上面DPP_ZCELL_FLAG_MODE等的定义 */
-    ZXIC_UINT32          bulk_id;        /* zcell所属空间ID  */
-    ZXIC_UINT32          zcell_idx;      /* zcell 的索引值, 高6bit为zblock的索引     */
-    ZXIC_UINT16          mask_len;       /* 掩码长度 */
-    ZXIC_UINT8            is_used;        /* 本zcell是否被占用*/
-    ZXIC_UINT8            is_share;       /* 是否共享block中的zcell*/
-    ZXIC_UINT32          item_used;
-    SE_ITEM_CFG     item_info[SE_RAM_DEPTH];    /* 本zcell的基本存储单元配置*/
-
-    D_NODE          zcell_dn;       /* 双链表节点，初始化其data指针指向SE_ZCELL_CFG实例自身，然后插入双链表中*/
-    ZXIC_AVL_NODE    zcell_avl;      /* 本hash程序未使用， 平衡二叉树节点*/
-} SE_ZCELL_CFG;
-/* zreg 的配置信息*/
-typedef struct se_zreg_cfg
-{
-    ZXIC_UINT8            flag;           /* z属性标志，各比特的含义见上面DPP_ZCELL_FLAG_MODE等的定义 */
-    ZXIC_UINT8            pad[3];
-    ZXIC_UINT32          bulk_id;        /* zcell所属空间ID  */
-    SE_ITEM_CFG     item_info;     /* zreg 存储的表条目配置*/
-} SE_ZREG_CFG;
-/* zblock 的配置信息*/
-typedef struct se_zblk_cfg
-{
-    ZXIC_UINT32          zblk_idx;   /* 统一编址，范围0~31 */
-    ZXIC_UINT16          is_used;    /* 本zblock 是否被占用 */
-    ZXIC_UINT16          zcell_bm;   /* 本hash程序未使用 */
-    ZXIC_UINT16          hash_arg;   /* hash crc算法的因子 */
-    ZXIC_UINT16          pad;
-
-    SE_ZCELL_CFG    zcell_info[SE_ZCELL_NUM];   /* 本block的4个zcell配置 */
-    SE_ZREG_CFG     zreg_info[SE_ZREG_NUM];     /* 本block的4个zreg配置*/
-
-    D_NODE          zblk_dn;                    /* 指向本实例的双链表节点 */
-
-} SE_ZBLK_CFG;
-/* alg表类型配置，包括4路hash引擎和v4 和 v6 lpm表项*/
-typedef struct func_id_info
-{
-    ZXIC_VOID *fun_ptr;
-    ZXIC_UINT8  fun_type;             /* 业务类型 参见 SE_FUN_TYPE */
-    ZXIC_UINT8  fun_id;
-    ZXIC_UINT8  is_used;
-    ZXIC_UINT8  pad;
-} FUNC_ID_INFO;
-
-typedef struct ddr_mem
-{
-    ZXIC_UINT32     total_num;
-    ZXIC_UINT32     base_addr;
-    ZXIC_UINT32     base_addr_offset;
-    ZXIC_UINT32     ecc_en;
-    ZXIC_UINT32     bank_num;
-    ZXIC_UINT32     bank_info[SE_ALG_BANK_NUM];
-    ZXIC_UINT32     share_type;  /* DDR bank共享模式 */
-    ZXIC_UINT32     item_used;
-    ZXIC_LISTSTACK_MANGER *p_ddr_mng;
-} DDR_MEM;
-
-typedef struct share_ram
-{
-    ZXIC_UINT32    zblk_array[SE_ZBLK_NUM];
-    D_HEAD    zblk_list;
-    D_HEAD    zcell_free_list;
-    ZXIC_UINT32    def_route_num;
-
-    ZXIC_RB_CFG       def_rb;
-    struct def_route_info  *p_dr_info;
-
-    DDR_MEM   ddr4_info;
-    DDR_MEM   ddr6_info;
-} SHARE_RAM;
-
-/**  算法模块管理数据结构，用户仅需创建实例变量，然后将指针传给初始化函数dpp_se_init()和dpp_se_client_init()即可，不需要单独赋值成员变量*/
-typedef struct dpp_se_cfg
-{
-    SE_ZBLK_CFG        zblk_info[SE_ZBLK_NUM];
-
-    FUNC_ID_INFO       fun_info[MAX_FUN_NUM];
-
-    SHARE_RAM          route_shareram;
-    ZXIC_UINT32             reg_base;
-
-    WRITE32_FUN        p_write32_fun;
-    READ32_FUN         p_read32_fun;
-
-    ZXIC_UINT32             lpm_flags;
-
-    ZXIC_VOID               *p_client;
-
-    DPP_DEV_T               *dev;
-    ZXIC_UINT32             dev_id;
-
-    LPM_AS_RSLT_WRT_FUNCTION p_as_rslt_wrt_fun;           /* dpp_se_lpm_as_rslt_write */
-
-#if LPM_THREAD_HW_WRITE_EN
-    // ZXIC_UINT32  mutex_location;                     /* dpp_route_cfg ?? cache mutex???????????route mode */
-    ZXIC_MUTEX_T cache_index_mutex[MAX_ITEM_INFO_BAK_NUM];         /* cache每个节点锁 */
-    ZXIC_UINT32  thread_hw_write_is_create;          /* ??????????????? ???????? add by lining for thread_hw_write */
-    ZXIC_LISTSTACK_MANGER *p_thread_liststack_mng;
-#endif
-
-} DPP_SE_CFG;
-
-/**  hash物理存储位宽类型*/
-typedef enum dpp_hash_ddr_width_mode
-{
-    DDR_WIDTH_INVALID = 0,
-    DDR_WIDTH_256b,          /**<  @brief 256bit位宽模式*/
-    DDR_WIDTH_512b,          /**<  @brief 512bit位宽模式*/
-} DPP_HASH_DDR_WIDTH_MODE;
-
-/**  hash条目类型*/
-typedef enum dpp_hash_key_type
-{
-    HASH_KEY_INVALID = 0, /**<  @brief 无效类型*/
-    HASH_KEY_128b,        /**<  @brief 128bit位宽类型*/
-    HASH_KEY_256b,        /**<  @brief 256bit位宽类型*/
-    HASH_KEY_512b,        /**<  @brief 512bit位宽类型*/
-} DPP_HASH_KEY_TYPE;
-
-/**  hash ddr resource cfg info*/
-typedef struct dpp_hash_ddr_resc_cfg_t
-{
-    ZXIC_UINT32 ddr_width_mode; /**<  @brief 分配给hash的DDR空间物理存储位宽模式，取值参考DPP_HASH_DDR_WIDTH_MODE的定义*/
-    ZXIC_UINT32 ddr_crc_sel;                     /**<  @brief 选择一个DDR CRC多项式，取值范围0~3,0~3分别对应一个CRC多项式*/
-    ZXIC_UINT32 ddr_item_num;                    /**<  @brief 分配给hash的DDR空间单元数目，以256bit为一个单元*/
-    ZXIC_UINT32 ddr_baddr;                       /**<  @brief 分配给hash的DDR空间的硬件基地址,以2k*256bit为单位*/
-    ZXIC_UINT32 ddr_ecc_en;                      /**<  @brief DDR ECC使能: 0-不使能，1-使能*/
-} DPP_HASH_DDR_RESC_CFG_T;
-
-/** hash search mode */
-typedef enum dpp_hash_srh_mode
-{
-    HASH_SRH_MODE_SOFT = 1,  /**<  @brief 查软件 */
-    HASH_SRH_MODE_HDW  = 2,  /**<  @brief 查硬件 */
-} DPP_HASH_SRH_MODE;
-
-/** hash tbl_flag */
-#define HASH_TBL_FLAG_AGE             (1<<0)  /**<  @brief 老化保活置位使能: 0-不使能；1-使能*/
-#define HASH_TBL_FLAG_LEARN           (1<<1)  /**<  @brief 硬件学习使能: 0-不使能；1-使能*/
-#define HASH_TBL_FLAG_MC_WRT          (1<<2)  /**<  @brief 微码写表使能: 0-不使能，1-使能 */
-
-/**  hash条目*/
-typedef struct dpp_hash_entry
-{
-    ZXIC_UINT8 *p_key; /**<  @brief 键值，格式详见各操作函数的说明*/
-    ZXIC_UINT8 *p_rst; /**<  @brief 结果*/
-} DPP_HASH_ENTRY;
-
-
-/**  前缀路由业务初始化标志*/
-#define LPM_FLAG_RT_HANDLE_START       (0)  /**<  @brief 是否使能级联结果表查找: 0-不使能，1-使能*/
-#define LPM_FLAG_RT_HANDLE_WIDTH       (1)
-#define LPM4_FLAG_DDR_EN_START         (1)  /**<  @brief 是否使能ipv4片外查找模式: 0-不使能，1-使能 */
-#define LPM4_FLAG_DDR_EN_WIDTH         (1)
-#define LPM6_FLAG_DDR_EN_START         (2)  /**<  @brief 是否使能ipv6片外查找模式: 0-不使能，1-使能 */
-#define LPM6_FLAG_DDR_EN_WIDTH         (1)
-#define LPM4_FLAG_DDR_SEL_START        (3)  /**<  @brief 是否为ipv4非线速模式: 0-线速，1-非线速 */
-#define LPM4_FLAG_DDR_SEL_WIDTH        (1)
-#define LPM6_FLAG_DDR_SEL_START        (4)  /**<  @brief 是否为ipv6非线速模式: 0-线速，1-非线速 */
-#define LPM6_FLAG_DDR_SEL_WIDTH        (1)
-#define LPM_FLAG_AS_MODE_START         (5)  /**<  @brief 级联结果表模式: 1-级联DDR，0-级联eRam  */
-#define LPM_FLAG_AS_MODE_WIDTH         (1)
-
-/**  前缀匹配路由级联DDR结果表返回位宽模式*/
-typedef enum dpp_route_as_rsp_len_e
-{
-    DPP_ROUTE_AS_128b  = 0,  /**<  @brief 返回128bit模式*/
-    DPP_ROUTE_AS_256b  = 1,  /**<  @brief 返回256bit模式*/
-    DPP_ROUTE_AS_384b  = 2,  /**<  @brief 返回384bit模式*/
-    DPP_ROUTE_AS_512b  = 3   /**<  @brief 返回512bit模式*/
-} DPP_ROUTE_AS_RSP_LEN_E;
-
-/**  前缀匹配路由业务ID*/
-typedef enum dpp_route_id_e
-{
-    DPP_ROUTE_V4_ID = 4, /**<  @brief route ipv4 ID*/
-    DPP_ROUTE_V6_ID = 5, /**<  @brief route ipv6 ID*/
-} DPP_ROUTE_ID_E;
-
-/**  前缀匹配路由业务模式*/
-typedef enum dpp_route_mode_e
-{
-    DPP_ROUTE_MODE_IPV4 = 1UL, /**<  @brief ipv4路由模式*/
-    DPP_ROUTE_MODE_IPV6        /**<  @brief ipv6路由模式*/
-} DPP_ROUTE_MODE_E;
-
-/**  前缀匹配路由DDR空间占用模式*/
-typedef enum dpp_route_ddr_use_mode_e
-{
-    DPP_ROUTE_DDR_USE_MINOR   = 1, /**<  @brief DDR使用量较少*/
-    DPP_ROUTE_DDR_USE_MIDDLE  = 2, /**<  @brief DDR使用量中等*/
-    DPP_ROUTE_DDR_USE_MAJOR   = 3, /**<  @brief DDR使用量较多*/
-} DPP_ROUTE_DDR_USE_MODE_E;
-
-/**  前缀匹配路由调试查找模式*/
-typedef enum dpp_route_srh_mode_e
-{
-    DPP_ROUTE_SRH_MODE_LP    = 1, /**<  @brief 前缀匹配查找模式*/
-    DPP_ROUTE_SRH_MODE_EQUAL = 2, /**<  @brief 精确匹配查找模式*/
-} DPP_ROUTE_SRH_MODE_E;
-
-/**  前缀匹配路由硬件资源 */
-typedef struct dpp_route_resource_t
-{
-    ZXIC_UINT32 zblk_num;          /**<  @brief LPM ipv4和ipv6共享的zblock数目*/
-    ZXIC_UINT32 *zblk_idx;         /**<  @brief LPM ipv4和ipv6共享的zblock编号数组*/
-    ZXIC_UINT32 ddr4_item_num;     /**<  @brief 分配给ipv4前缀查找的ddr存储条目数，以256bit为单位*/
-    ZXIC_UINT32 ddr4_baddr;        /**<  @brief 分配给ipv4前缀查找的ddr存储空间的基地址，以4K*128bit为单位*/
-    ZXIC_UINT32 ddr4_base_offset;  /**<  @brief ipv4前缀查找相对于片外ddr存储空间基地址的偏移量，以256bit为单位*/
-    ZXIC_UINT32 ddr4_ecc_en;       /**<  @brief 固定配为1，分配给ipv4前缀查找的ddr存储空间的ECC校验使能标志*/
-    ZXIC_UINT32 ddr4_bank_num;     /**<  @brief ipv4前缀查找的ddr存储空间bank复制份数 */
-    ZXIC_UINT32 *ddr4_bank_info;   /**<  @brief ipv4前缀查找的ddr存储空间bank号，数组传入，支持离散分配*/
-    ZXIC_UINT32 ddr4_share_type;   /**<  @brief ipv4前缀查找的ddr存储空间bank共享模式，参见SMMU1_DDR_SHARE_MODE_E*/
-    ZXIC_UINT32 ddr6_item_num;     /**<  @brief 分配给ipv6前缀查找的ddr存储条目数，以256bit为单位*/
-    ZXIC_UINT32 ddr6_baddr;        /**<  @brief 分配给ipv6前缀查找的ddr存储空间的基地址，以4K*128bit为单位*/
-    ZXIC_UINT32 ddr6_base_offset;  /**<  @brief ipv6前缀查找相对于片外ddr存储空间基地址的偏移量，以256bit为单位*/
-    ZXIC_UINT32 ddr6_ecc_en;       /**<  @brief 固定配为1，分配给ipv4前缀查找的ddr存储空间的ECC校验使能标志*/
-    ZXIC_UINT32 ddr6_bank_num;     /**<  @brief ipv6前缀查找的ddr存储空间bank复制份数 */
-    ZXIC_UINT32 *ddr6_bank_info;   /**<  @brief ipv6前缀查找的ddr存储空间bank号，数组传入，支持离散分配*/
-    ZXIC_UINT32 ddr6_share_type;   /**<  @brief ipv6前缀查找的ddr存储空间bank共享模式，参见SMMU1_DDR_SHARE_MODE_E*/
-} DPP_ROUTE_RESOURCE_T;
-
-/**  前缀匹配路由级联片内eRam结果表属性 */
-typedef struct dpp_route_as_eram_t
-{
-    ZXIC_UINT32 baddr;     /**<  @brief LPM级联eRam结果基地址*/
-    ZXIC_UINT32 rsp_mode;  /**<  @brief LPM级联eRam结果位宽模式，取值参照ERAM128_TBL_MODE_E的定义*/
-} DPP_ROUTE_AS_ERAM_T;
-
-/**  前缀匹配路由级联片外DDR结果表属性 */
-typedef struct dpp_route_as_ddr_t
-{
-    ZXIC_UINT32 baddr;        /**<  @brief 分配给级联ddr结果表空间的基地址，以4K*128bit为单位*/
-    ZXIC_UINT32 rsp_len;      /**<  @brief LPM级联DDR结果位宽模式，取值参照DPP_ROUTE_AS_RSP_LEN_E的定义*/
-    ZXIC_UINT32 ecc_en;       /**<  @brief 级联结果表DDR空间ECC校验使能标志: 0-不使能，1-使能*/
-} DPP_ROUTE_AS_DDR_T;
-
-typedef union dpp_route_as_rslttbl_u
-{
-    DPP_ROUTE_AS_ERAM_T as_eram_cfg;  /**<  @brief LPM级联eRam结果表空间属性*/
-    DPP_ROUTE_AS_DDR_T  as_ddr_cfg;   /**<  @brief LPM级联DDR结果表空间属性*/
-} DPP_ROUTE_AS_RSLTTBL_U;
-
-/**  前缀匹配IPv4键值*/
-typedef struct dpp_route_ipv4_key_t
-{
-    ZXIC_UINT32     vpnid;          /**<  @brief vpnid，16bit*/
-    ZXIC_UINT32     mask_len;       /**<  @brief IP地址的掩码长度，最小为0(表示默认路由)，最大为32*/
-    ZXIC_UINT32     ipv4_addr;      /**<  @brief IP地址，32bit*/
-} DPP_ROUTE_IPV4_KEY_T;
-
-/**  前缀匹配IPv4单个路由条目*/
-typedef struct dpp_route_entry_ipv4_t
-{
-    DPP_ROUTE_IPV4_KEY_T route_key; /**<  @brief 键值*/
-    ZXIC_UINT32         route_handle;    /**<  @brief 键值匹配后，继续查转发结果表的索引*/
-    ZXIC_UINT8           *p_as_rslt;      /**<  @brief 转发结果，仅在使能lpm关联结果查找的情况下有效 */
-} DPP_ROUTE_ENTRY_IPV4_T;
-
-/**  前缀匹配IPv6键值*/
-typedef struct dpp_route_ipv6_key_t
-{
-    ZXIC_UINT32    vpnid;      /**<  @brief vpnid，16bit*/
-    ZXIC_UINT32    mask_len;   /**<  @brief IP地址的掩码长度，最小为0(表示默认路由)，最大为128*/
-    ZXIC_UINT32    ipaddr[4];  /**<  @brief IP地址，128bit*/
-} DPP_ROUTE_IPV6_KEY_T;
-
-/**  前缀匹配IPv6单个路由条目*/
-typedef struct dpp_route_entry_ipv6_t
-{
-    DPP_ROUTE_IPV6_KEY_T route_key;  /**<  @brief 键值*/
-    ZXIC_UINT32         route_handle;     /**<  @brief 键值匹配后，继续查转发结果表的索引*/
-    ZXIC_UINT8           *p_as_rslt;       /**<  @brief 转发结果，仅在使能lpm关联结果查找的情况下有效 */
-} DPP_ROUTE_ENTRY_IPV6_T;
-
-/* 在HASH进行初始化的时候，需要存储的参数 */
-typedef struct dpp_hash_soft_reset_stor_dat
-{
-    /* 参照dpp_hash_init()的参数 */
-    ZXIC_UINT32 ddr_dis_flag[4];     /**<  @brief 4个HASH引擎是否DISABLE DDR标志 */
-    ZXIC_UINT32 zblk_num[4];         /**<  @brief 4个HASH引擎使用的zblk数量 */
-    ZXIC_UINT32 *zblk_idx_start[4];  /**<  @brief 4个HASH引擎使用的起始zblk index */
-
-    /* 参照dpp_hash_bulk_init()的参数 */
-    ZXIC_UINT32 ddr_item_num[4][8];  /**<  @brief 每个bulk空间存放的ddr item数 */
-    ZXIC_UINT32 ddr_base_addr[4];    /**<  @brief 每个hash引擎基地址 */
-    ZXIC_UINT32 ddr_bank_cp[4];      /**<  @brief 每个hash引擎bank copy数量 */
-    ZXIC_UINT32 ddr_ecc_en[4];       /**<  @brief ddr是否开启ecc使能 */
-
-    /*     ZXIC_UINT32 ddr_width_mode[4]; */       /**<  @brief ddr存储位宽 */
-    /*     ZXIC_UINT32 ddr_crc_sel[4];  */      /**<  @brief ddr多项式选择 */
-    /*     ZXIC_UINT32 ddr_share_type[4]; */       /**<  @brief ddr 共享类型 */
-
-    ZXIC_UINT32 hash_id_valid;       /** HASH引擎是否已经初始化标志 */
-} DPP_HASH_SOFT_RESET_STOR_DAT;
-
-
-
-/***********************************************************/
-/** 初始化算法管理数据结构，不包含用户自定义的数据指针
-* @param   p_se_cfg  算法管理数据结构指针
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wcl      @date  2015/05/20
-************************************************************/
-DPP_STATUS  dpp_se_init(DPP_DEV_T *dev, DPP_SE_CFG *p_se_cfg);
-
-/***********************************************************/
-/** 初始化算法管理数据结构用户自定义的数据指针，当前仅用于传入设备号的值
-* @param   p_se_cfg  算法管理数据结构指针
-* @param   p_client  用户自定义的数据指针
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wcl      @date  2015/05/20
-************************************************************/
-DPP_STATUS dpp_se_client_init(DPP_SE_CFG *p_se_cfg, ZXIC_VOID *p_client);
-
-/***********************************************************/
-/** 单个hash引擎初始化
-* @param   p_se_cfg      算法模块公共管理数据结构指针
-* @param   fun_id         hash引擎号
-* @param   zblk_num      分配给此hash引擎的zblock数目
-* @param   zblk_idx      分配给此hash引擎的zblock编号
-* @param   ddr_dis       DDR关闭位，0-不关闭片外DDR, 1-关闭片外DDR
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wcl      @date  2015/05/15
-************************************************************/
-DPP_STATUS dpp_hash_init(DPP_SE_CFG *p_se_cfg,
-                         ZXIC_UINT32     fun_id,
-                         ZXIC_UINT32     zblk_num,
-                         ZXIC_UINT32     *zblk_idx,
-                         ZXIC_UINT32     ddr_dis);
-
-/***********************************************************/
-/** 初始化单个hash引擎内的某个业务表，此接口支持为该业务表分配独占的zcell。
-*     必须先初始化hash引擎，再初始化业务表。
-* @param   p_se_cfg        算法模块公共管理数据结构指针
-* @param   fun_id         hash引擎号
-* @param   bulk_id         每个Hash引擎资源划分的空间ID号
-* @param   p_ddr_resc_cfg  分配给hash引擎此资源空间的ddr资源属性
-* @param   zcell_num       分配给hash引擎此资源空间的zcell数量
-* @param   zreg_num        分配给hash引擎此资源空间的zreg数量
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wcl      @date  2015/05/15
-************************************************************/
-DPP_STATUS dpp_hash_bulk_init(DPP_SE_CFG *p_se_cfg,
-                              ZXIC_UINT32     fun_id,
-                              ZXIC_UINT32     bulk_id,
-                              DPP_HASH_DDR_RESC_CFG_T *p_ddr_resc_cfg,
-                              ZXIC_UINT32     zcell_num,
-                              ZXIC_UINT32     zreg_num);
-
-/***********************************************************/
-/** 初始化单个hash引擎内的某个业务表，此接口支持为该业务表分配独占的zcell。
-*   必须先初始化hash引擎，如果是片内+片外模式还必须先初始化dpp_hash_ddr_bulk_init，
-*   再初始化业务表。
-* @param   p_se_cfg    算法模块公共管理数据结构指针
-* @param   fun_id      hash引擎号
-* @param   tbl_id          业务表
-* @param   tbl_flag        初始化标记, bitmap的形式使用，如:HASH_TBL_FLAG_AGE等
-* @param   key_type        hash条目类型，取值参照DPP_HASH_KEY_TYPE的定义
-* @param   actu_key_size   业务键值有效长度: 8bit*N，N=1~48
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wcl      @date  2015/05/15
-************************************************************/
-DPP_STATUS dpp_hash_tbl_id_info_init(DPP_SE_CFG *p_se_cfg,
-                                     ZXIC_UINT32  fun_id,
-                                     ZXIC_UINT32  tbl_id,
-                                     ZXIC_UINT32  tbl_flag,
-                                     ZXIC_UINT32  key_type,
-                                     ZXIC_UINT32  actu_key_size);
-
-#endif
-
-#if ZXIC_REAL("eTcam data struct and function")
-typedef DPP_STATUS (*ACL_AS_RSLT_WRT_FUNCTION)(ZXIC_UINT32 dev_id, ZXIC_UINT32 base_addr, ZXIC_UINT32 index, ZXIC_UINT32 as_mode, ZXIC_UINT8 *p_data);
-#define DPP_ACL_TBL_ID_NUM      (8U)
-#define DPP_ACL_ETCAM_ID_NUM    (1U)
-#define DPP_ACL_BLOCK_NUM       (8U)
-
-/**  eTcam条目位宽模式*/
-typedef enum dpp_etcam_entry_mode_e
-{
-    DPP_ETCAM_KEY_640b = 0,
-    DPP_ETCAM_KEY_320b = 1,
-    DPP_ETCAM_KEY_160b = 2,
-    DPP_ETCAM_KEY_80b  = 3,
-    DPP_ETCAM_KEY_INVALID,
-} DPP_ETCAM_ENTRY_MODE_E;
-
-/**  eTcam操作类型*/
-typedef enum dpp_etcam_opr_type_e
-{
-    DPP_ETCAM_OPR_DM = 0,  /**<  @brief data & mask类型*/
-    DPP_ETCAM_OPR_XY = 1,  /**<  @brief X & Y类型*/
-} DPP_ETCAM_OPR_TYPE_E;
-
-/**  eTcam条目格式*/
-typedef struct dpp_etcam_entry_t
-{
-    ZXIC_UINT32 mode;     /**<  @brief 条目位宽模式: 2'b00-640bit,2'b01-320bit,2'b10-160bit,2'b11-80bit*/
-    ZXIC_UINT8   *p_data;  /**<  @brief 键值*/
-    ZXIC_UINT8   *p_mask;  /**<  @brief 掩码*/
-} DPP_ETCAM_ENTRY_T;
-
-/**  ACL键值位宽模式*/
-typedef enum dpp_acl_key_mode_e
-{
-    DPP_ACL_KEY_640b = 0, /**<  @brief 640bit键值位宽*/
-    DPP_ACL_KEY_320b,     /**<  @brief 320bit键值位宽*/
-    DPP_ACL_KEY_160b,     /**<  @brief 160bit键值位宽*/
-    DPP_ACL_KEY_80b,      /**<  @brief 80bit键值位宽*/
-    DPP_ACL_KEY_INVALID,
-} DPP_ACL_KEY_MODE_E;
-
-/**  ACL关联查找结果表位宽模式*/
-typedef enum dpp_acl_as_mode_e
-{
-    DPP_ACL_AS_MODE_16b  = 0,
-    DPP_ACL_AS_MODE_32b  = 1,
-    DPP_ACL_AS_MODE_64b  = 2,  /**<  @brief 64bit结果位宽*/
-    DPP_ACL_AS_MODE_128b = 3,  /**<  @brief 128bit结果位宽*/
-    DPP_ACL_AS_MODE_INVALID,
-} DPP_ACL_AS_MODE_E;
-
-/**  ACL调试查找模式*/
-typedef enum dpp_acl_srh_mode_e
-{
-    DPP_ACL_SRH_SOFT     = 0, /**<  @brief 查软件*/
-    DPP_ACL_SRH_HARDWARE = 1, /**<  @brief 查硬件*/
-} DPP_ACL_SRH_MODE_E;
-
-/**  ACL条目*/
-typedef struct dpp_acl_entry_t
-{
-    ZXIC_UINT32  handle;     /**<  @brief 条目索引*/
-    ZXIC_UINT8    *key_data;  /**<  @brief 键值data部分*/
-    ZXIC_UINT8    *key_mask;  /**<  @brief 键值mask部分: 0为关心，1为不关心*/
-    ZXIC_UINT8    *p_as_rslt; /**<  @brief 关联结果，仅使能关联查找情况有效*/
-} DPP_ACL_ENTRY_T;
-
-typedef struct dpp_acl_block_info_t
-{
-    ZXIC_UINT32 is_used;
-    ZXIC_UINT32 tbl_id;
-    ZXIC_UINT32 idx_base;
-} DPP_ACL_BLOCK_INFO_T;
-
-typedef struct dpp_acl_etcamid_cfg_t
-{
-    ZXIC_UINT32 is_valid;
-    ZXIC_UINT32 as_enable;     /* eTcam自动关联eRam结果表使能: 0-不使能，1-使能 */
-    ZXIC_UINT32 as_idx_offset; /* 关联结果表基地址偏移，以128bit为单位 */
-    ZXIC_UINT32 as_eRam_base;  /* eTcam自动关联的eRam block的基地址，以128bit为单位 */
-    D_HEAD tbl_list;
-} DPP_ACL_ETCAMID_CFG_T;
-
-typedef struct dpp_acl_key_info_t
-{
-    ZXIC_UINT32 handle;
-    ZXIC_UINT32 pri;
-    ZXIC_UINT8   key[0];  /* data+mask */
-} DPP_ACL_KEY_INFO_T;
-
-/**  ACL初始化使能标志*/
-#define DPP_ACL_FLAG_ETCAM0_EN        (1<<0) /**<  @brief 开启eTcam端口0: 0-不开启，1-开启.*/
-#define DPP_ACL_FLAG_ETCAM0_AS        (1<<2) /**<  @brief 开启eTcam端口0的关联结果查找: 0-不开启，1-开启.*/
-//#define DPP_ACL_FLAG_ETCAM1_AS        (1<<3) /**<  @brief 开启eTcam端口1的关联结果查找: 0-不开启，1-开启.*/
-
-typedef DPP_STATUS (*ACL_TBL_AS_DDR_WR_FUN)(ZXIC_UINT32 dev_id, ZXIC_UINT32 tbl_type, ZXIC_UINT32 tbl_id, ZXIC_UINT32 dir_tbl_share_type, ZXIC_UINT32 dir_tbl_base_addr, ZXIC_UINT32 ecc_en, ZXIC_UINT32 index, ZXIC_UINT32 as_mode, ZXIC_UINT8 *p_data);
-typedef DPP_STATUS (*ACL_TBL_AS_DDR_RD_FUN)(ZXIC_UINT32 dev_id, ZXIC_UINT32 base_addr, ZXIC_UINT32 index, ZXIC_UINT32 as_mode, ZXIC_UINT8 *p_data);
-
-/**  */
-typedef struct dpp_acl_tbl_cfg_t
-{
-    ZXIC_UINT32 tbl_type;
-    ZXIC_UINT32 table_id;
-    ZXIC_UINT8   is_as_ddr;
-    ZXIC_UINT8   ddr_bankcp_info;
-    ZXIC_UINT32 dir_tbl_share_type;
-    ZXIC_UINT8   ddr_ecc_en;
-    ZXIC_UINT32 pri_mode;
-    ZXIC_UINT32 key_mode;
-    ZXIC_UINT32 entry_num;
-    ZXIC_UINT32 block_num;
-    ZXIC_UINT32 *block_array;
-    ZXIC_UINT32 is_used;
-    ZXIC_UINT32 as_mode;
-    ZXIC_UINT32 as_idx_base;
-    ZXIC_UINT32 as_enable;           /* eTcam自动关联eRam结果表使能: 0-不使能，1-使能 */
-    ZXIC_UINT32 as_eRam_base;        /* eTcam自动关联的eRam block的基地址，以128bit为单位 */
-    ZXIC_UINT32 ddr_baddr;
-    ZXIC_UINT32 idx_offset; /* 相对于ddr_baddr的基地址的索引偏移，以as_mode对应的数据位宽为单位 */
-    ACL_TBL_AS_DDR_WR_FUN p_as_ddr_wr_fun;
-    ACL_TBL_AS_DDR_RD_FUN p_as_ddr_rd_fun;
-    D_NODE         entry_dn;
-    INDEX_FILL_CFG index_mng;
-    ZXIC_RB_CFG     acl_rb;
-    DPP_ACL_KEY_INFO_T  **acl_key_buff;
-    ZXIC_UINT8  *as_rslt_buff;
-} DPP_ACL_TBL_CFG_T;
-
-/**  ACL公共管理数据结构*/
-typedef struct dpp_acl_cfg_t
-{
-    ZXIC_VOID    *p_client;
-    DPP_DEV_T    *dev;
-    ZXIC_UINT32  dev_id;
-    ZXIC_UINT32  flags;
-    ACL_AS_RSLT_WRT_FUNCTION  p_as_rslt_write_fun;
-    ACL_AS_RSLT_WRT_FUNCTION  p_as_rslt_read_fun;
-    DPP_ACL_BLOCK_INFO_T      acl_blocks[DPP_ACL_BLOCK_NUM];
-    DPP_ACL_ETCAMID_CFG_T     acl_etcamids;
-    DPP_ACL_TBL_CFG_T         acl_tbls[DPP_ACL_TBL_ID_NUM];
-} DPP_ACL_CFG_T;
-
-/**<  @brief ACL公共管理数据结构*/
-typedef struct dpp_acl_cfg_ex_t
-{
-    ZXIC_VOID    *p_client;
-    DPP_DEV_T    *dev;
-    ZXIC_UINT32  dev_id;
-    ZXIC_UINT32  flags;
-    ACL_AS_RSLT_WRT_FUNCTION  p_as_rslt_write_fun;
-    ACL_AS_RSLT_WRT_FUNCTION  p_as_rslt_read_fun;
-    DPP_ACL_BLOCK_INFO_T      acl_blocks[DPP_ACL_BLOCK_NUM];
-    DPP_ACL_ETCAMID_CFG_T     acl_etcamids;
-    DPP_ACL_TBL_CFG_T         acl_tbls[DPP_ACL_TBL_ID_NUM];
-}DPP_ACL_CFG_EX_T;
-
-/**  acl优先级模式*/
-typedef enum dpp_acl_pri_mode_e
-{
-    DPP_ACL_PRI_EXPLICIT = 1, /**<  @brief 显示优先级*/
-    DPP_ACL_PRI_IMPLICIT,     /**<  @brief 隐式优先级，以条目下发顺序作为优先级*/
-    DPP_ACL_PRI_SPECIFY,      /**<  @brief 用户指定每个条目的在tcam中的存放索引*/
-    DPP_ACL_PRI_INVALID,
-} DPP_ACL_PRI_MODE_E;
-
-/**  */
-typedef struct dpp_acl_entry_ex_t
-{
-    ZXIC_UINT32  idx_val;   /**<  @brief 一次插入单个acl条目时有效，返回单个索引*/
-    D_HEAD  idx_list;  /**<  @brief 一次插入多个acl条目时有效，返回多个索引*/
-    ZXIC_UINT32  pri;       /* PRI_EXPLICIT: pri is priority, PRI_IMPLICIT: pri is invalid, PRI_SPECIFY: pri is handle */
-    ZXIC_UINT8    *key_data;
-    ZXIC_UINT8    *key_mask;
-    ZXIC_UINT8    *p_as_rslt;
-} DPP_ACL_ENTRY_EX_T;
-
-/***********************************************************/
-/** eTcam模块初始化
-* @param   dev_id 设备号
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wcl      @date  2015/07/24
-************************************************************/
-DPP_STATUS dpp_etcam_init(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/**
-* @param   p_acl_cfg   ACL公共管理数据结构指针
-* @param   p_client   用户自定义的数据指针
-* @param   flags
-* @param   p_as_wrt_fun   关联结果写硬件表回调函数指针
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yxh      @date  2017/12/15
-************************************************************/
-DPP_STATUS dpp_acl_cfg_init_ex(DPP_DEV_T *dev,
-                               DPP_ACL_CFG_EX_T *p_acl_cfg,
-                               ZXIC_VOID *p_client,
-                               ZXIC_UINT32 flags,
-                               ACL_AS_RSLT_WRT_FUNCTION p_as_wrt_fun);
-
-/***********************************************************/
-/** acl业务表初始化，注意分配给一个table的多个block_idx
-    必须按从小到大的顺序给定。支持多个优先级模式，暂不对外开放。
-* @param   p_acl_cfg   ACL公共管理数据结构指针
-* @param   table_id   业务表号
-* @param   as_enable   是否使能关联结果查找，0-不使能，1-使能
-* @param   entry_num   最大条目数
-* @param   pri_mode   ACL优先级模式
-* @param   key_mode   ACL键值位宽模式, 取值参照DPP_ACL_KEY_MODE_E的定义
-* @param   as_mode   ACL关联查找结果表位宽模式
-* @param   as_baddr   基地址
-* @param   block_num   分配给当前业务表号的block数目
-* @param   p_block_idx   分配给当前业务表号的block编号数组
-*
-* @return
-* @remark  无
-* @see
-* @author  wcl      @date  2014/12/23
-************************************************************/
-DPP_STATUS dpp_acl_tbl_init_ex(DPP_ACL_CFG_EX_T *p_acl_cfg,
-                               ZXIC_UINT32 table_id,
-                               ZXIC_UINT32 as_enable,
-                               ZXIC_UINT32 entry_num,
-                               DPP_ACL_PRI_MODE_E pri_mode,
-                               ZXIC_UINT32 key_mode,
-                               DPP_ACL_AS_MODE_E  as_mode,
-                               ZXIC_UINT32 as_baddr,
-                               ZXIC_UINT32 block_num,
-                               ZXIC_UINT32 *p_block_idx);
-DPP_STATUS dpp_acl_res_destroy(ZXIC_UINT32 dev_id);
-
-#endif
-
-#if ZXIC_REAL("SDT data struct and function")
-/** SDT属性中的表类型 */
-typedef enum dpp_sdt_table_type_e
-{
-    DPP_SDT_TBLT_INVALID = 0, /**<  @brief 无效类型*/
-    DPP_SDT_TBLT_eRAM    = 1, /**<  @brief eRAM直接表类型*/
-    DPP_SDT_TBLT_DDR3    = 2, /**<  @brief DDR3直接表类型*/
-    DPP_SDT_TBLT_HASH    = 3, /**<  @brief Hash表类型*/
-    DPP_SDT_TBLT_LPM     = 4, /**<  @brief LPM表类型*/
-    DPP_SDT_TBLT_eTCAM   = 5, /**<  @brief 片内Tcam表类型*/
-    DPP_SDT_TBLT_PORTTBL = 6, /**<  @brief 物理端口属性表*/
-    DPP_SDT_TBLT_MAX     = 7,
-} DPP_SDT_TABLE_TYPE_E;
-
-/**  返回位宽模式*/
-typedef enum dpp_sdt_rsp_mode_e
-{
-    DPP_SDT_RSP_32b  = 0, /**  返回32bit位宽表结果*/
-    DPP_SDT_RSP_64b  = 1, /**  返回64bit位宽表结果*/
-    DPP_SDT_RSP_128b = 2, /**  返回128bit位宽表结果*/
-    DPP_SDT_RSP_256b = 3, /**  返回256bit位宽表结果*/
-} DPP_SDT_RSP_MODE_E;
-
-/**  eRam直接表SDT属性*/
-typedef struct dpp_sdt_tbl_eram_t
-{
-    ZXIC_UINT32 table_type;          /** <@brief 查找表项类型 */
-    ZXIC_UINT32 eram_mode;           /** <@brief eRam返回位宽 */
-    ZXIC_UINT32 eram_base_addr;      /** <@brief eRam表项基地址，128bit为单位 */
-    ZXIC_UINT32 eram_table_depth;    /** <@brief 表项深度，作为越界检查使用   */
-    ZXIC_UINT32 eram_clutch_en;      /** <@brief 抓包使能 */
-} DPP_SDTTBL_ERAM_T;
-
-/**  DDR3直接表SDT属性*/
-typedef struct dpp_sdt_tbl_ddr3_t
-{
-    ZXIC_UINT32 table_type;           /** <@brief 查找表项类型   */
-    ZXIC_UINT32 ddr3_base_addr;       /** <@brief ddr 基地址     */
-    ZXIC_UINT32 ddr3_share_type;      /** <@brief ddr 共享类型   */
-    ZXIC_UINT32 ddr3_rw_len;          /** <@brief 表项返回/写入位宽 */
-    ZXIC_UINT32 ddr3_sdt_num;         /** <@brief SDT表号/复制信息ram的表号 */
-    ZXIC_UINT32 ddr3_ecc_en;          /** <@brief ecc使能        */
-    ZXIC_UINT32 ddr3_clutch_en;       /** <@brief 抓包使能       */
-} DPP_SDTTBL_DDR3_T;
-
-/**  HASH表SDT属性*/
-typedef struct dpp_sdt_tbl_hash_t
-{
-    ZXIC_UINT32 table_type;          /** <@brief 查找表项类型       */
-    ZXIC_UINT32 hash_id;             /** <@brief 访问hash的引擎     */
-    ZXIC_UINT32 hash_table_width;    /** <@brief hash 表项存储位宽  */
-    ZXIC_UINT32 key_size;            /** <@brief hash 键值长度      */
-    ZXIC_UINT32 hash_table_id;       /** <@brief hash 逻辑表号      */
-    ZXIC_UINT32 learn_en;            /** <@brief 硬件学习使能       */
-    ZXIC_UINT32 keep_alive;          /** <@brief 保活标志使能       */
-    ZXIC_UINT32 keep_alive_baddr;     /** <@brief 保活标志基地址     */
-    ZXIC_UINT32 rsp_mode;            /** <@brief 表项返回数据位宽   */
-    ZXIC_UINT32 hash_clutch_en;      /** <@brief 抓包使能           */
-} DPP_SDTTBL_HASH_T;
-
-/**  LPM表SDT属性*/
-typedef struct dpp_sdt_tbl_lpm_t
-{
-    ZXIC_UINT32 table_type;          /** <@brief 查找表项类型       */
-    ZXIC_UINT32 lpm_v46_id;          /** <@brief ipv4/ipv6标志      */
-    ZXIC_UINT32 rsp_mode;            /** <@brief 表项返回数据位宽   */
-    ZXIC_UINT32 lpm_table_depth;     /** <@brief 表项深度，越界检查 */
-    ZXIC_UINT32 lpm_clutch_en;       /** <@brief 抓包使能           */
-} DPP_SDTTBL_LPM_T;
-
-/**  eTCAM表SDT属性*/
-typedef struct dpp_sdt_tbl_etcam_t
-{
-    ZXIC_UINT32 table_type;          /** <@brief 查找表项类型       */
-    ZXIC_UINT32 etcam_id;            /** <@brief etcam通道         */
-    ZXIC_UINT32 etcam_key_mode;      /** <@brief etcam键值长度      */
-    ZXIC_UINT32 etcam_table_id;      /** <@brief etcam表项号        */
-    ZXIC_UINT32 no_as_rsp_mode;      /** <@brief handle模式返回位宽 */
-    ZXIC_UINT32 as_en;               /** <@brief 级联eram使能       */
-    ZXIC_UINT32 as_eram_baddr;       /** <@brief 级联eram基地址     */
-    ZXIC_UINT32 as_rsp_mode;         /** <@brief 级联返回位宽       */
-    ZXIC_UINT32 etcam_table_depth;   /** <@brief 表项深度，越界检查 */
-    ZXIC_UINT32 etcam_clutch_en;     /** <@brief 抓包使能           */
-} DPP_SDTTBL_ETCAM_T;
-
-/**  物理端口属性表SDT属性*/
-typedef struct dpp_sdt_tbl_porttbl_t
-{
-    ZXIC_UINT32 table_type;          /** <@brief 查找表项类型       */
-    ZXIC_UINT32 porttbl_clutch_en;   /** <@brief 抓包使能           */
-} DPP_SDTTBL_PORTTBL_T;
-
-/***********************************************************/
-/** 初始化SDT表配置管理
-* @param   dev_num       设备数目
-* @param   dev_id_array  设备dev_id数组
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wcl      @date  2015/07/13
-************************************************************/
-DPP_STATUS dpp_sdt_init(ZXIC_UINT32 dev_num, ZXIC_UINT32 *dev_id_array);
-
-/***********************************************************/
-/** 写SDT属性表条目到硬件表，同时向8个cluster写入
-* @param   dev_id      设备号
-* @param   sdt_no      业务表对应的sdt号
-* @param   table_type  SDT属性中的表类型，取值参考DPP_SDT_TABLE_TYPE_E的定义(仅添加操作时有效)
-* @param   p_sdt_info  写入的SDT属性(仅添加操作时有效)。由table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n
-*                      DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR3_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、\n
-*                      DPP_SDTTBL_ETCAM_T、DPP_SDTTBL_XTCAM_T、DPP_SDTTBL_PORTTBL_T。
-* @param   opr_type    操作类型: 0-添加条目，1-删除条目.
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wcl      @date  2015/07/11
-************************************************************/
-DPP_STATUS dpp_sdt_tbl_write(DPP_DEV_T *dev,
-                             ZXIC_UINT32 sdt_no,
-                             ZXIC_UINT32 table_type,
-                             ZXIC_VOID *p_sdt_info,
-                             ZXIC_UINT32 opr_type);
-                             
-#endif
-
-#endif /*dpp_se_api.h*/
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_se_api.h
+* 文件标识 : se模块对外数据类型定义和接口函数声明
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : wcl
+* 完成日期 : 2015/01/30
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#ifndef _DPP_SE_API_H_
+#define _DPP_SE_API_H_
+
+#if ZXIC_REAL("header file")
+#include "dpp_type_api.h" /* xcx_0619 */
+#endif
+
+#if ZXIC_REAL("data struct define")
+
+/** DPP+ 所有eram block 大小都变为2M  ~深度是16K */
+#define SE_SMMU0_ERAM_BLOCK_NUM (32)
+#define SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK (0x4000)
+#define SE_SMMU0_ERAM_ADDR_NUM_TOTAL \
+	(SE_SMMU0_ERAM_BLOCK_NUM * SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK)
+
+#define DPP_DDR4_PER_BANK_BADDR_SETP (0x800) /* 8G X16 */
+#define DPP_DDR4_BANK_NUM (64)
+#define DPP_DDR4_PER_BANK_BADDR_CONV(ddr4_phy_type) \
+	(DPP_DDR4_PER_BANK_BADDR_SETP * (4U >> ddr4_phy_type))
+
+/*普通上送上送类型*/
+typedef enum dpp_dma_ecc_en_e {
+	DMA_ECC_DISABLE = 0,
+	DMA_ECC_ENABLE = 1,
+} DPP_DMA_ECC_EN_E;
+
+/**  eRam表读请模式 */
+typedef enum dpp_eram128_rd_clr_mode_e {
+	RD_MODE_HOLD = 0, /**<  @brief 正常读，读完数据不清空   */
+	RD_MODE_CLEAR = 1, /**<  @brief 读清模式，返回eram中的值 */
+} DPP_ERAM128_RD_CLR_MODE_E;
+
+/**  eRam表cpu读写位宽模式*/
+typedef enum dpp_eram128_opr_mode_e {
+	ERAM128_OPR_128b = 0, /**<  @brief 128bit模式读写eRam, 支持128bit读清模式*/
+	ERAM128_OPR_64b = 1, /**<  @brief 64bit模式读写eRam,  支持64bit  读清模式*/
+	ERAM128_OPR_1b = 2, /**<  @brief 1bit模式读写eRam,   不支持1bit  读清模式*/
+	ERAM128_OPR_32b =
+			3 /**<  @brief 32bit模式读eRam,    不能用于写，支持32bit 读清模式*/
+} DPP_ERAM128_OPR_MODE_E;
+
+/**  eRam直接表位宽模式,也可用于eRam做结果表时的位宽  */
+typedef enum dpp_eram128_tbl_mode_e {
+	ERAM128_TBL_1b = 0, /**<  @brief 1bit   eRam片内直接表  */
+	ERAM128_TBL_32b = 1, /**<  @brief 32bit  eRam片内直接表  */
+	ERAM128_TBL_64b = 2, /**<  @brief 64bit  eRam片内直接表  */
+	ERAM128_TBL_128b = 3, /**<  @brief 128bit eRam片内直接表  */
+	ERAM128_TBL_2b = 4, /**<  @brief 2bit   eRam片内直接表  */
+	ERAM128_TBL_4b = 5, /**<  @brief 4bit   eRam片内直接表  */
+	ERAM128_TBL_8b = 6, /**<  @brief 8bit   eRam片内直接表  */
+	ERAM128_TBL_16b = 7 /**<  @brief 16bit  eRam片内直接表  */
+} DPP_ERAM128_TBL_MODE_E;
+
+/**  eRam查表通道*/
+typedef enum smmu0_empty_type_e {
+	SMMU0_EMPTY_CLS0 = 0, /**<  @brief PPU cluster0通道*/
+	SMMU0_EMPTY_CLS1 = 1, /**<  @brief PPU cluster1通道*/
+	SMMU0_EMPTY_CLS2 = 2, /**<  @brief PPU cluster2通道*/
+	SMMU0_EMPTY_CLS3 = 3, /**<  @brief PPU cluster3通道*/
+	SMMU0_EMPTY_CLS4 = 4, /**<  @brief PPU cluster4通道*/
+	SMMU0_EMPTY_CLS5 = 5, /**<  @brief PPU cluster5通道*/
+	SMMU0_EMPTY_CLS6 = 6, /**<  @brief PPU cluster6通道*/
+	SMMU0_EMPTY_CLS7 = 7, /**<  @brief PPU cluster7通道*/
+	SMMU0_EMPTY_MCAST = 8, /**<  @brief 组播复制表通道*/
+	SMMU0_EMPTY_ODMA = 9, /**<  @brief ODMA保序计数通道*/
+} SMMU0_EMPTY_TYPE_E;
+
+/**  组播报文类型*/
+typedef enum smmu0_mcast_tbl_type_e {
+	MCAST_TDM = 0, /**<  @brief TDM组播报文*/
+	MCAST_DATA = 1, /**<  @brief 数据组播报文*/
+
+	MCAST_INVALID, /**<  @brief 无效值 */
+} SMMU0_MCAST_TBL_TYPE_E;
+
+/** 调试计数读清模式 */
+typedef enum se_dbg_cnt_read_mode_e {
+	SE_DBG_CNT_READ_UNCLR = 0, /**<  @brief 非读清模式 */
+	SE_DBG_CNT_READ_CLR, /**<  @brief 读清模式 */
+} SE_DBG_CNT_READ_MODE_E;
+
+/** 调试计数溢出模式 */
+typedef enum se_dbg_cnt_overflow_mode_e {
+	SE_DBG_CNT_OVERFLOW_UNREVERSE = 0, /**<  @brief 溢出保持 */
+	SE_DBG_CNT_OVERFLOW_REVERSE, /**<  @brief 溢出翻转 */
+} SE_DBG_CNT_OVERFLOW_MODE_E;
+
+/**  DDR颗粒类型*/
+typedef enum se_ddr_phy_cfg_type_e {
+	DPP_SE_DDR_PHY_32G_16 = 0, /**<  @brief DDR颗粒每组32G容量,x16颗粒*/
+	DPP_SE_DDR_PHY_16G_16, /**<  @brief DDR颗粒每组16G容量,x16颗粒*/
+	DPP_SE_DDR_PHY_8G_16, /**<  @brief DDR颗粒每组8G容量,x16颗粒*/
+	DPP_SE_DDR_PHY_4G_16, /**<  @brief DDR颗粒每组4G容量,x16颗粒*/
+	DPP_SE_DDR_PHY_32G_8, /**<  @brief DDR颗粒每组32G容量,x8颗粒*/
+	DPP_SE_DDR_PHY_16G_8, /**<  @brief DDR颗粒每组16G容量,x8颗粒*/
+	DPP_SE_DDR_PHY_8G_8, /**<  @brief DDR颗粒每组8G容量,x8颗粒*/
+	DPP_SE_DDR_PHY_4G_8, /**<  @brief DDR颗粒每组4G容量,x8颗粒*/
+	DPP_SE_DDR_PHY_MAX,
+} SE_DDR_PHY_CFG_TYPE_E;
+
+/**  DDR表写数据位宽模式*/
+typedef enum smmu1_ddr_wrt_mode_e {
+	SMMU1_DDR_WRT_128b = 0, /**<  @brief 128bit模式写DDR*/
+	SMMU1_DDR_WRT_256b = 1, /**<  @brief 256bit模式写DDR*/
+	SMMU1_DDR_WRT_384b = 2, /**<  @brief 384bit模式写DDR*/
+	SMMU1_DDR_WRT_512b = 3, /**<  @brief 512bit模式写DDR*/
+} SMMU1_DDR_WRT_MODE_E;
+
+/** DDR表的共享模式 */
+typedef enum smmu1_ddr_share_mode_e {
+	SMMU1_DDR_SHARE_NO_SHARE = 0, /**<  @brief SE 占用整个DDR*/
+	SMMU1_DDR_SHARE_1_2 = 1, /**<  @brief SE 占用1/2 DDR*/
+	SMMU1_DDR_SHARE_1_4 = 2, /**<  @brief SE 占用1/4 DDR*/
+	SMMU1_DDR_SHARE_1_8 = 3, /**<  @brief SE 占用1/8 DDR*/
+	SMMU1_DDR_SHARE_MAX
+} SMMU1_DDR_SHARE_MODE_E;
+
+/** 占用smmu1的表类型 */
+typedef enum smmu1_ddr_tbl_type_e {
+	SMMU1_DDR_TBL_TYPE_DIR_TBL = 0, /**<  @brief 片外直接表 */
+	SMMU1_DDR_TBL_TYPE_HASH_TBL = 1, /**<  @brief HASH占用表 */
+	SMMU1_DDR_TBL_TYPE_LPM_TBL = 2, /**<  @brief LPM 占用表  */
+	SMMU1_DDR_TBL_TYPE_OAM_TBL = 3, /**<  @brief OAM 占用表  */
+	SMMU1_DDR_TBL_TYPE_FTM_TBL = 4, /**<  @brief FTM 占用表  */
+	SMMU1_DDR_TBL_TYPE_ETM_TBL = 5, /**<  @brief ETM 占用表  */
+	SMMU1_DDR_TBL_TYPE_MAX
+} SMMU1_DDR_TBL_TYPE_E;
+
+typedef enum cmmu_rd_mode_e {
+	CMMU_RD_MODE_29_35 = 0,
+	CMMU_RD_MODE_32 = 1,
+	CMMU_RD_MODE_64 = 2,
+	CMMU_RD_MODE_128 = 3,
+	CMMU_RD_MODE_MAX,
+} CMMU_RD_OPR_MODE_E;
+
+/**  CMMU读请模式 */
+typedef enum cmmu_rd_clr_mode_e {
+	CMMU_RD_CLR_MODE_UNCLR = 0, /**<  @brief 正常读，读完数据不清空   */
+	CMMU_RD_CLR_MODE_CLR = 1, /**<  @brief 读清模式*/
+	CMMU_RD_CLR_MODE_MAX,
+} CMMU_RD_CLR_MODE_E;
+
+/**  DDR表读数据位宽模式*/
+typedef enum smmu1_ddr_srh_mode_e {
+	SMMU1_DDR_SRH_128b = 0, /**<  @brief 访问DDR，以128bit模式返回数据*/
+	SMMU1_DDR_SRH_256b, /**<  @brief 访问DDR，以256bit模式返回数据*/
+	SMMU1_DDR_SRH_512b, /**<  @brief 访问DDR，以512bit模式返回数据*/
+	SMMU1_DDR_SRH_MAX
+} SMMU1_DDR_SRH_MODE_E;
+
+/**  DDR地址映射参数*/
+typedef struct se_ddr_addr_map_info_t {
+	ZXIC_UINT32
+	is_inited; /**<  @brief 用于检测此结构体是否已经经过初始化 0xAA-已经初始化 其他值-未初始化 */
+	ZXIC_UINT32
+	ddr_phy_type; /**<  @brief DDR颗粒类型 0-32G,x16颗粒,1-16G,x16颗粒,2-8G,x16颗粒 */
+	ZXIC_UINT32 se_use_bank_num; /**<  @brief SE使用的bank数目 */
+	ZXIC_UINT32
+	bank_used_sate
+			[64]; /**<  @brief 表示64个bank的使用状态 0-不存在 1-SE使用 2-PUB使用 3-FTM使用 4-ETM使用  */
+} SE_DDR_ADDR_MAP_INFO_T;
+
+/**  se从ppu接收的查表请求排空状态*/
+typedef struct dpp_se_ept_flag_t {
+	ZXIC_UINT32 ppu5_ept_flag; /**<  @brief se从ppu通道5接收的查表请求排空状态*/
+	ZXIC_UINT32 ppu4_ept_flag; /**<  @brief se从ppu通道4接收的查表请求排空状态*/
+	ZXIC_UINT32 ppu3_ept_flag; /**<  @brief se从ppu通道3接收的查表请求排空状态*/
+	ZXIC_UINT32 ppu2_ept_flag; /**<  @brief se从ppu通道2接收的查表请求排空状态*/
+	ZXIC_UINT32 ppu1_ept_flag; /**<  @brief se从ppu通道1接收的查表请求排空状态*/
+	ZXIC_UINT32 ppu0_ept_flag; /**<  @brief se从ppu通道0接收的查表请求排空状态*/
+} DPP_SE_EPT_FLAG_T;
+
+/**  smmu0(eRam)各通道查表请求排空状态*/
+typedef struct dpp_smmu0_ept_flag_t {
+	ZXIC_UINT32 ept_flag8; /**<  @brief odam请求排空状态*/
+	ZXIC_UINT32 ept_flag7; /**<  @brief odam tdm请求排空状态*/
+	ZXIC_UINT32 ept_flag6; /**<  @brief sa组播份数表请求排空状态*/
+	ZXIC_UINT32 ept_flag5; /**<  @brief ppu通道5查表请求排空状态*/
+	ZXIC_UINT32 ept_flag4; /**<  @brief ppu通道4查表请求排空状态*/
+	ZXIC_UINT32 ept_flag3; /**<  @brief ppu通道3查表请求排空状态*/
+	ZXIC_UINT32 ept_flag2; /**<  @brief ppu通道2查表请求排空状态*/
+	ZXIC_UINT32 ept_flag1; /**<  @brief ppu通道1查表请求排空状态*/
+	ZXIC_UINT32 ept_flag0; /**<  @brief ppu通道0查表请求排空状态*/
+} DPP_SMMU0_EPT_FLAG_T;
+
+/**  SMMU0保序FIFO写满读空中断原因*/
+typedef struct dpp_se_smmu0_int0_t {
+	ZXIC_UINT32 dma_ordfifo; /**<  @brief DMA保序fifo 写满读空标志*/
+	ZXIC_UINT32 odma_ordfifo; /**<  @brief ODMA保序fifo 写满读空标志*/
+	ZXIC_UINT32 mcast_ordfifo; /**<  @brief MCAST保序fifo 写满读空标志*/
+} DPP_SE_SMMU0_INT0_T;
+
+/* 数据组播报文类型 */
+typedef struct data_mcast_t_ {
+	ZXIC_UINT8 valid; /**< @brief valid 表示是否可用 */
+	ZXIC_UINT8 rsv; /**< @brief rsv   保留位，字节对齐使用,勿需关心 */
+	ZXIC_UINT16 mc_cnt; /**< @brief mc_cnt 16bit */
+} DATA_MCAST_T;
+
+/* TDM 组播报文类型 */
+typedef struct tdm_mcast_t_ {
+	ZXIC_UINT8 valid; /**< @brief valid 表示是否可用 */
+	ZXIC_UINT8 rsv; /**< @brief rsv   保留位，字节对齐使用，勿需关心 */
+	ZXIC_UINT8 bitmap[6]; /**< @brief bitmap[0]是最高位，bitmap[2]是最低位 */
+} TDM_MCAST_T;
+
+#endif
+
+#if ZXIC_REAL("eTcam data struct define")
+
+#endif
+
+#if ZXIC_REAL("interrupt data struct define")
+/** SMMU0 中断状态 */
+typedef struct dpp_se_smmu0_int_t {
+	ZXIC_UINT32 smmu0_int0;
+	ZXIC_UINT32 smmu0_int1;
+	ZXIC_UINT32 smmu0_int2;
+	ZXIC_UINT32 smmu0_int3;
+	ZXIC_UINT32 smmu0_int4;
+	ZXIC_UINT32 smmu0_int5;
+	ZXIC_UINT32 smmu0_int6;
+	ZXIC_UINT32 smmu0_int7;
+	ZXIC_UINT32 smmu0_int8;
+	ZXIC_UINT32 smmu0_int9;
+	ZXIC_UINT32 smmu0_int10;
+	ZXIC_UINT32 smmu0_int11;
+	ZXIC_UINT32 smmu0_int12;
+	ZXIC_UINT32 smmu0_int13;
+	ZXIC_UINT32 smmu0_int14;
+	ZXIC_UINT32 smmu0_int15;
+	ZXIC_UINT32 smmu0_int16;
+	ZXIC_UINT32 smmu0_int17;
+	ZXIC_UINT32 smmu0_int18;
+	ZXIC_UINT32 smmu0_int19;
+	ZXIC_UINT32 smmu0_int20;
+	ZXIC_UINT32 smmu0_int21;
+	ZXIC_UINT32 smmu0_int22;
+	ZXIC_UINT32 smmu0_int23;
+	ZXIC_UINT32 smmu0_int24;
+	ZXIC_UINT32 smmu0_int25;
+	ZXIC_UINT32 smmu0_int26;
+	ZXIC_UINT32 smmu0_int27;
+	ZXIC_UINT32 smmu0_int28;
+	ZXIC_UINT32 smmu0_int29;
+	ZXIC_UINT32 smmu0_int30;
+	ZXIC_UINT32 smmu0_int31;
+	ZXIC_UINT32 smmu0_int32;
+	ZXIC_UINT32 smmu0_int33;
+	ZXIC_UINT32 smmu0_int34;
+	ZXIC_UINT32 smmu0_int35;
+	ZXIC_UINT32 smmu0_int36;
+	ZXIC_UINT32 smmu0_int37;
+	ZXIC_UINT32 smmu0_int38;
+
+} DPP_SE_SMMU0_INT_T;
+
+/** SMMU0 模块总的中断状态 */
+typedef struct dpp_smmu0_brief_int_t {
+	ZXIC_UINT32 smmu0_int14_unmask_flag;
+	ZXIC_UINT32 smmu0_int13_unmask_flag;
+	ZXIC_UINT32 smmu0_int12_unmask_flag;
+	ZXIC_UINT32 smmu0_int11_unmask_flag;
+	ZXIC_UINT32 smmu0_int10_unmask_flag;
+	ZXIC_UINT32 smmu0_int9_unmask_flag;
+	ZXIC_UINT32 smmu0_int8_unmask_flag;
+	ZXIC_UINT32 smmu0_int7_unmask_flag;
+	ZXIC_UINT32 smmu0_int6_unmask_flag;
+	ZXIC_UINT32 smmu0_int5_unmask_flag;
+	ZXIC_UINT32 smmu0_int4_unmask_flag;
+	ZXIC_UINT32 smmu0_int3_unmask_flag;
+	ZXIC_UINT32 smmu0_int2_unmask_flag;
+	ZXIC_UINT32 smmu0_int1_unmask_flag;
+	ZXIC_UINT32 smmu0_int0_unmask_flag;
+} DPP_SMMU0_BRIEF_INT_T;
+
+/** SE 模块总的中断状态 */
+typedef struct dpp_se_int_status_t {
+	ZXIC_UINT32 as_int_unmask_flag; /**< @brief 级联查找模块（AS）总中断状态 */
+	ZXIC_UINT32
+	kschd_int_unmask_flag; /**< @brief 键值调度模块（KSCHD）总中断状态 */
+	ZXIC_UINT32
+	rschd_int_unmask_flag; /**< @brief 返回调度模块（RSCHD）总中断状态 */
+	ZXIC_UINT32 smmu1_int_unmask_flag; /**< @brief SMMU1 中断总中断状态 */
+	ZXIC_UINT32 cmmu_int_unmask_flag; /**< @brief CMMU  总中断状态 */
+	ZXIC_UINT32 parser_int_unmask_flag; /**< @brief 解析模块（parse）总中断状态 */
+} DPP_SE_INT_STATUS_T;
+
+/** se解析模块中断状态 */
+typedef struct dpp_se_parser_int_t {
+	ZXIC_UINT32 parser_int_en;
+	ZXIC_UINT32 parser_int_mask;
+	ZXIC_UINT32 parser_int_status;
+} DPP_SE_PARSER_INT_T;
+
+/** key调度模块(KSCHD)中断状态 */
+typedef struct dpp_se_kschd_int_t {
+	ZXIC_UINT32 kschd_int_0;
+	ZXIC_UINT32 kschd_int_1;
+	ZXIC_UINT32 kschd_int_2;
+	ZXIC_UINT32 kschd_int_3;
+	ZXIC_UINT32 kschd_int_4;
+} DPP_SE_KSCHD_INT_T;
+
+/** rsp调度模块(RSCHD)中断状态 */
+typedef struct dpp_se_rschd_int_t {
+	ZXIC_UINT32 port0_int;
+	ZXIC_UINT32 port1_int;
+} DPP_SE_RSCHD_INT_T;
+
+/**  关联查找(AS)模块的中断原因*/
+typedef struct dpp_se_as_int_t {
+	ZXIC_UINT32 as_int_0;
+	ZXIC_UINT32 as_int_1;
+	ZXIC_UINT32 as_int_2;
+} DPP_SE_AS_INT_T;
+
+/** cmmu 模块中断*/
+typedef struct dpp_se_cmmu_int_t {
+	ZXIC_UINT32 cmmu_int12;
+	ZXIC_UINT32 cmmu_int11;
+	ZXIC_UINT32 cmmu_int10;
+	ZXIC_UINT32 cmmu_int9;
+	ZXIC_UINT32 cmmu_int8;
+	ZXIC_UINT32 cmmu_int7;
+	ZXIC_UINT32 cmmu_int6;
+	ZXIC_UINT32 cmmu_int5;
+	ZXIC_UINT32 cmmu_int4;
+	ZXIC_UINT32 cmmu_int3;
+	ZXIC_UINT32 cmmu_int2;
+	ZXIC_UINT32 cmmu_int1;
+	ZXIC_UINT32 cmmu_int0;
+} DPP_SE_CMMU_INT_T;
+
+/** ALG 模块中断*/
+typedef struct dpp_se_alg_int_t {
+	ZXIC_UINT32
+	wr_rsp_fifo_ovfl_int; /**< @brief 写返回缓存ptr fifo 溢出中断上报 */
+	ZXIC_UINT32 init_rd_cft_int; /**< @brief 初始化过程中出现读命令，冲突中断 */
+	ZXIC_UINT32
+	schd_lpm_fifo_parity_err_int; /**< @brief 调度lpm缓存FIFO奇偶校验错误上报 */
+	ZXIC_UINT32
+	schd_hash3_fifo_parity_err_int; /**< @brief 调度hash3缓存FIFO奇偶校验错误上报 */
+	ZXIC_UINT32
+	schd_hash2_fifo_parity_err_int; /**< @brief 调度hash2缓存FIFO奇偶校验错误上报 */
+	ZXIC_UINT32
+	schd_hash1_fifo_parity_err_int; /**< @brief 调度hash1缓存FIFO奇偶校验错误上报 */
+	ZXIC_UINT32
+	schd_hash0_fifo_parity_err_int; /**< @brief 调度hash0缓存FIFO奇偶校验错误上报 */
+	ZXIC_UINT32
+	schd_learn_fifo_parity_err_int; /**< @brief 调度学习缓存FIFO奇偶校验错误上报 */
+	ZXIC_UINT32
+	schd_lpm_fifo_ovfl_int; /**< @brief 调度lpm键值缓存FIFO溢出中断上报 */
+	ZXIC_UINT32
+	schd_hash3_fifo_ovfl_int; /**< @brief 调度hash3键值缓存FIFO溢出中断上报 */
+	ZXIC_UINT32
+	schd_hash2_fifo_unfl_int; /**< @brief 调度hash2键值缓存FIFO溢出中断上报 */
+	ZXIC_UINT32
+	schd_hash1_fifo_ovfl_int; /**< @brief 调度hash1键值缓存FIFO溢出中断上报 */
+	ZXIC_UINT32
+	schd_hash0_fifo_ovfl_int; /**< @brief 调度hash0键值缓存FIFO溢出中断上报 */
+	ZXIC_UINT32
+	schd_learn_fifo_ovfl_int; /**< @brief 调度学习命令缓存FIFO溢出中断上报 */
+
+	ZXIC_UINT32 zblk31_parity_int; /**< @brief zblock31  parity 中断 */
+	ZXIC_UINT32 zblk30_parity_int; /**< @brief zblock30  parity 中断 */
+	ZXIC_UINT32 zblk29_parity_int; /**< @brief zblock29  parity 中断 */
+	ZXIC_UINT32 zblk28_parity_int; /**< @brief zblock28  parity 中断 */
+	ZXIC_UINT32 zblk27_parity_int; /**< @brief zblock27  parity 中断 */
+	ZXIC_UINT32 zblk26_parity_int; /**< @brief zblock26  parity 中断 */
+	ZXIC_UINT32 zblk25_parity_int; /**< @brief zblock25  parity 中断 */
+	ZXIC_UINT32 zblk24_parity_int; /**< @brief zblock24  parity 中断 */
+	ZXIC_UINT32 zblk23_parity_int; /**< @brief zblock23  parity 中断 */
+	ZXIC_UINT32 zblk22_parity_int; /**< @brief zblock22  parity 中断 */
+	ZXIC_UINT32 zblk21_parity_int; /**< @brief zblock21  parity 中断 */
+	ZXIC_UINT32 zblk20_parity_int; /**< @brief zblock20  parity 中断 */
+	ZXIC_UINT32 zblk19_parity_int; /**< @brief zblock19  parity 中断 */
+	ZXIC_UINT32 zblk18_parity_int; /**< @brief zblock18  parity 中断 */
+	ZXIC_UINT32 zblk17_parity_int; /**< @brief zblock17  parity 中断 */
+	ZXIC_UINT32 zblk16_parity_int; /**< @brief zblock16  parity 中断 */
+	ZXIC_UINT32 zblk15_parity_int; /**< @brief zblock15  parity 中断 */
+	ZXIC_UINT32 zblk14_parity_int; /**< @brief zblock14  parity 中断 */
+	ZXIC_UINT32 zblk13_parity_int; /**< @brief zblock13  parity 中断 */
+	ZXIC_UINT32 zblk12_parity_int; /**< @brief zblock12  parity 中断 */
+	ZXIC_UINT32 zblk11_parity_int; /**< @brief zblock11  parity 中断 */
+	ZXIC_UINT32 zblk10_parity_int; /**< @brief zblock10  parity 中断 */
+	ZXIC_UINT32 zblk9_parity_int; /**< @brief zblock9   parity 中断 */
+	ZXIC_UINT32 zblk8_parity_int; /**< @brief zblock8   parity 中断 */
+	ZXIC_UINT32 zblk7_parity_int; /**< @brief zblock7   parity 中断 */
+	ZXIC_UINT32 zblk6_parity_int; /**< @brief zblock6   parity 中断 */
+	ZXIC_UINT32 zblk5_parity_int; /**< @brief zblock5   parity 中断 */
+	ZXIC_UINT32 zblk4_parity_int; /**< @brief zblock4   parity 中断 */
+	ZXIC_UINT32 zblk3_parity_int; /**< @brief zblock3   parity 中断 */
+	ZXIC_UINT32 zblk2_parity_int; /**< @brief zblock2   parity 中断 */
+	ZXIC_UINT32 zblk1_parity_int; /**< @brief zblock1   parity 中断 */
+	ZXIC_UINT32 zblk0_parity_int; /**< @brief zblock0   parity 中断 */
+
+	ZXIC_UINT32 zcam_hash_p0_err_int; /**< @brief hash0 ZCAM查找出错中断 */
+	ZXIC_UINT32
+	hash0_agree_int_fifo_ovf_int; /**< @brief hash0 汇聚fifo 片内通道溢出中断 */
+	ZXIC_UINT32
+	hash0_agree_ext_fifo_ovf_int; /**< @brief hash0 汇聚fifo 片外通道parity中断 */
+	ZXIC_UINT32
+	hash0_agree_ext_fifo_parity_err_int; /**< @brief hash0 汇聚fifo 片外通道溢出中断*/
+	ZXIC_UINT32
+	hash0_agree_int_fifo_parity_err_int; /**< @brief hash0 汇聚fifo 片内通道parity中断 */
+	ZXIC_UINT32
+	hash0_key_fifo_ovfl_int; /**< @brief hash0 片外键值缓存FIFO 溢出中断 */
+	ZXIC_UINT32
+	hash0_sreq_fifo_ovfl_int; /**< @brief hash0 片外读地址缓存FIFO溢出中断 */
+	ZXIC_UINT32
+	hash0_key_fifo_parity_err_int; /**< @brief hash0 片外键值缓存FIFO parity err中断 */
+
+	ZXIC_UINT32 zcam_hash_p1_err_int; /**< @brief hash1 ZCAM查找出错中断 */
+	ZXIC_UINT32
+	hash1_agree_int_fifo_ovf_int; /**< @brief hash1 汇聚fifo 片内通道溢出中断 */
+	ZXIC_UINT32
+	hash1_agree_ext_fifo_ovf_int; /**< @brief hash1 汇聚fifo 片外通道parity中断 */
+	ZXIC_UINT32
+	hash1_agree_ext_fifo_parity_err_int; /**< @brief hash1 汇聚fifo 片外通道溢出中断*/
+	ZXIC_UINT32
+	hash1_agree_int_fifo_parity_err_int; /**< @brief hash1 汇聚fifo 片内通道parity中断 */
+	ZXIC_UINT32
+	hash1_key_fifo_ovfl_int; /**< @brief hash1 片外键值缓存FIFO 溢出中断 */
+	ZXIC_UINT32
+	hash1_sreq_fifo_ovfl_int; /**< @brief hash1 片外读地址缓存FIFO溢出中断 */
+	ZXIC_UINT32
+	hash1_key_fifo_parity_err_int; /**< @brief hash1 片外键值缓存FIFO parity err中断 */
+
+	ZXIC_UINT32 zcam_hash_p2_err_int; /**< @brief hash2 ZCAM查找出错中断 */
+	ZXIC_UINT32
+	hash2_agree_int_fifo_ovf_int; /**< @brief hash2 汇聚fifo 片内通道溢出中断 */
+	ZXIC_UINT32
+	hash2_agree_ext_fifo_ovf_int; /**< @brief hash2 汇聚fifo 片外通道parity中断 */
+	ZXIC_UINT32
+	hash2_agree_ext_fifo_parity_err_int; /**< @brief hash2 汇聚fifo 片外通道溢出中断*/
+	ZXIC_UINT32
+	hash2_agree_int_fifo_parity_err_int; /**< @brief hash2 汇聚fifo 片内通道parity中断 */
+	ZXIC_UINT32
+	hash2_key_fifo_ovfl_int; /**< @brief hash2 片外键值缓存FIFO 溢出中断 */
+	ZXIC_UINT32
+	hash2_sreq_fifo_ovfl_int; /**< @brief hash2 片外读地址缓存FIFO溢出中断 */
+	ZXIC_UINT32
+	hash2_key_fifo_parity_err_int; /**< @brief hash2 片外键值缓存FIFO parity err中断 */
+
+	ZXIC_UINT32 zcam_hash_p3_err_int; /**< @brief hash3 ZCAM查找出错中断 */
+	ZXIC_UINT32
+	hash3_agree_int_fifo_ovf_int; /**< @brief hash3 汇聚fifo 片内通道溢出中断 */
+	ZXIC_UINT32
+	hash3_agree_ext_fifo_ovf_int; /**< @brief hash3 汇聚fifo 片外通道parity中断 */
+	ZXIC_UINT32
+	hash3_agree_ext_fifo_parity_err_int; /**< @brief hash3 汇聚fifo 片外通道溢出中断*/
+	ZXIC_UINT32
+	hash3_agree_int_fifo_parity_err_int; /**< @brief hash3 汇聚fifo 片内通道parity中断 */
+	ZXIC_UINT32
+	hash3_key_fifo_ovfl_int; /**< @brief hash3 片外键值缓存FIFO 溢出中断 */
+	ZXIC_UINT32
+	hash3_sreq_fifo_ovfl_int; /**< @brief hash3 片外读地址缓存FIFO溢出中断 */
+	ZXIC_UINT32
+	hash3_key_fifo_parity_err_int; /**< @brief hash3 片外键值缓存FIFO parity err中断 */
+
+	ZXIC_UINT32 zcam_lpm_err_int; /**< @brief lpm ZCAM查找出错中断 */
+	ZXIC_UINT32
+	lpm_as_int_rsp_fifo_ovfl_int; /**< @brief lpm as 片内查找结果缓存FIFO溢出中断 */
+	ZXIC_UINT32
+	lpm_as_req_fifo_ovfl_int; /**< @brief lpm as 查找ddr 地址 FIFO溢出中断 */
+	ZXIC_UINT32
+	lpm_ext_ddr_rsp_fifo_parity_int; /**< @brief lpm ext ddr rsp FIFO parity中断 */
+	ZXIC_UINT32
+	lpm_ext_v6_key_parity_int; /**< @brief lpm ext v6 key FIFO parity中断 */
+	ZXIC_UINT32
+	lpm_ext_v4_key_parity_int; /**< @brief lpm ext v4 key FIFO parity中断 */
+	ZXIC_UINT32
+	lpm_ext_addr_fifo_ovfl_int; /**< @brief lpm ext ddr3 地址溢出中断 */
+	ZXIC_UINT32 lpm_ext_v4_fifo_ovfl_int; /**< @brief lpm ext v4 key溢出中断 */
+	ZXIC_UINT32 lpm_ext_v6_fifo_ovfl_int; /**< @brief lpm ext v6 key溢出中断 */
+	ZXIC_UINT32
+	lpm_ext_ddr_rsp_ovf_int; /**< @brief lpm ext ddr返回缓存fifo溢出中断 */
+} DPP_SE_ALG_INT_T;
+
+/** ALG 模块对外总中断*/
+typedef struct dpp_se_alg_brief_int_t {
+	ZXIC_UINT32 schd_int_unmask_flag; /**<@brief alg模块调度状态 */
+	ZXIC_UINT32
+	zblk_parity_int_unmask_flag; /**<@brief alg模块zblock奇偶校验中断 */
+	ZXIC_UINT32 hash0_int_unmask_flag; /**<@brief alg模块hash0中断状态 */
+	ZXIC_UINT32 hash1_int_unmask_flag; /**<@brief alg模块hash1中断状态 */
+	ZXIC_UINT32 hash2_int_unmask_flag; /**<@brief alg模块hash2中断状态 */
+	ZXIC_UINT32 hash3_int_unmask_flag; /**<@brief alg模块hash3中断状态 */
+	ZXIC_UINT32 lpm_int_unmask_flag; /**<@brief alg模块lpm中断状态 */
+} DPP_SE_ALG_BRIEF_INT_T;
+
+/** SMMU1 中断 */
+typedef struct dpp_se_smmu1_int_t {
+	ZXIC_UINT32 smmu1_int0;
+	ZXIC_UINT32 smmu1_int1;
+	ZXIC_UINT32 smmu1_int2;
+	ZXIC_UINT32 smmu1_int3;
+	ZXIC_UINT32 smmu1_int4;
+	ZXIC_UINT32 smmu1_int5;
+	ZXIC_UINT32 smmu1_int6;
+	ZXIC_UINT32 smmu1_int7;
+	ZXIC_UINT32 smmu1_int8;
+	ZXIC_UINT32 smmu1_int9;
+	ZXIC_UINT32 smmu1_int10;
+	ZXIC_UINT32 smmu1_int11;
+	ZXIC_UINT32 smmu1_int12;
+	ZXIC_UINT32 smmu1_int13;
+	ZXIC_UINT32 smmu1_int14;
+	ZXIC_UINT32 smmu1_int15;
+	ZXIC_UINT32 smmu1_int16;
+	ZXIC_UINT32 smmu1_int17;
+} DPP_SE_SMMU1_INT_T;
+
+typedef struct dpp_etcam_intr_t {
+	ZXIC_UINT32 etcam_int_33;
+	ZXIC_UINT32 etcam_int_32;
+	ZXIC_UINT32 etcam_int_31;
+	ZXIC_UINT32 etcam_int_30;
+	ZXIC_UINT32 etcam_int_29;
+	ZXIC_UINT32 etcam_int_28;
+	ZXIC_UINT32 etcam_int_27;
+	ZXIC_UINT32 etcam_int_26;
+	ZXIC_UINT32 etcam_int_25;
+	ZXIC_UINT32 etcam_int_24;
+	ZXIC_UINT32 etcam_int_23;
+	ZXIC_UINT32 etcam_int_22;
+	ZXIC_UINT32 etcam_int_21;
+	ZXIC_UINT32 etcam_int_20;
+	ZXIC_UINT32 etcam_int_19;
+	ZXIC_UINT32 etcam_int_18;
+	ZXIC_UINT32 etcam_int_17;
+	ZXIC_UINT32 etcam_int_16;
+	ZXIC_UINT32 etcam_int_15;
+	ZXIC_UINT32 etcam_int_14;
+	ZXIC_UINT32 etcam_int_13;
+	ZXIC_UINT32 etcam_int_12;
+	ZXIC_UINT32 etcam_int_11;
+	ZXIC_UINT32 etcam_int_10;
+	ZXIC_UINT32 etcam_int_9;
+	ZXIC_UINT32 etcam_int_8;
+	ZXIC_UINT32 etcam_int_7;
+	ZXIC_UINT32 etcam_int_6;
+	ZXIC_UINT32 etcam_int_5;
+	ZXIC_UINT32 etcam_int_4;
+	ZXIC_UINT32 etcam_int_3;
+	ZXIC_UINT32 etcam_int_2;
+	ZXIC_UINT32 etcam_int_1;
+	ZXIC_UINT32 etcam_int_0;
+} DPP_ETCAM_INTR_T;
+
+typedef struct dpp_se_stat_int_t {
+	ZXIC_UINT32 stat_int0;
+	ZXIC_UINT32 stat_int1;
+	ZXIC_UINT32 stat_int2;
+	ZXIC_UINT32 stat_int3;
+	ZXIC_UINT32 stat_int4;
+	ZXIC_UINT32 stat_int5;
+} DPP_SE_STAT_INT_T;
+
+#endif
+
+#if ZXIC_REAL("macro function define")
+
+#endif
+
+#if ZXIC_REAL("function declaration")
+/***********************************************************/
+/** 读eRam
+ * @param   dev_id       设备号
+ * @param   base_addr    基地址，以128bit为单位
+ * @param   index        条目索引,支持128、64、32和1bit的索引值
+ * @param   rd_mode      读eRam模式, 取值参照ERAM128_OPR_MODE_E定义，读清模式下不支持1bit模式
+ * @param   rd_clr_mode  eRam读清模式, 取值参照ERAM128_RD_CLR_MODE_E定义
+ * @param   p_data       返回数据缓存的指针
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/01/30
+ ************************************************************/
+DPP_STATUS dpp_se_smmu0_ind_read(DPP_DEV_T *dev, ZXIC_UINT32 base_addr,
+								 ZXIC_UINT32 index, ZXIC_UINT32 rd_mode,
+								 ZXIC_UINT32 rd_clr_mode, ZXIC_UINT32 *p_data);
+
+#endif
+
+#if ZXIC_REAL("Hash & LPM data struct and function")
+
+/** lpm&hash算法模块硬件读写函数指针类型 */
+typedef DPP_STATUS (*WRITE32_FUN)(ZXIC_UINT32 dev_id, ZXIC_UINT32 addr,
+								  ZXIC_UINT32 write_data);
+typedef DPP_STATUS (*READ32_FUN)(ZXIC_UINT32 dev_id, ZXIC_UINT32 addr,
+								 ZXIC_UINT32 *read_data);
+
+/**  前缀匹配路由关联结果表写硬件函数指针类型*/
+typedef DPP_STATUS (*LPM_AS_RSLT_WRT_FUNCTION)(ZXIC_UINT32 dev_id,
+											   ZXIC_UINT32 as_type,
+											   ZXIC_UINT32 tbl_id,
+											   ZXIC_UINT32 index,
+											   ZXIC_UINT8 *p_data);
+
+#define SE_ZGRP_NUM (4)
+#define SE_ZBLK_NUM (32)
+#define SE_ZCELL_NUM (4)
+#define SE_ZCELL_TOTAL_NUM (SE_ZBLK_NUM * SE_ZCELL_NUM)
+#define SE_ZREG_NUM (4)
+#define SE_RAM_DEPTH (512)
+#define MAX_FUN_NUM (8)
+#define SE_ALG_BANK_NUM (29)
+
+/*
+ *    zcell/zreg 基本存储单元的配置信息,512bit为单位，
+ *    zcell包含512个基本存储单元，zreg包含4个基本存储单元，
+ *    每个单元可以存储1个512bit条目、2个256bit条目或4个128bit条目，
+ *    本结构体不感知内部存储条目的位宽，hash中键值中的key_type可以
+ *    可以获取表项的位宽信息
+ */
+typedef struct se_item_cfg {
+	D_HEAD item_list; /** 基本存储单元双链表头节点，可以存放放在本单元内的具体表项条目*/
+	ZXIC_UINT32 item_index; /** 基本存储单元所处的索引值 */
+	ZXIC_UINT32 hw_addr; /** 基本存储单元物理的地址 */
+	ZXIC_UINT32 bulk_id;
+	ZXIC_UINT32
+	item_type; /** 基本存储单元的存储类型，包括片外或片内，参见SE_ITEM_TYPE */
+	ZXIC_UINT8
+	wrt_mask; /** 基本存储单元写入的掩码，4bit，每bit表示待写入的128bit位置 */
+	ZXIC_UINT8 valid; /** 基本存储单元是否被占用，0-未被占用，1-被占用 */
+	ZXIC_UINT8 pad[2];
+} SE_ITEM_CFG;
+
+/**  zcell属性标志*/
+#define DPP_ZCELL_FLAG_IS_MONO \
+	(1) /**<  @brief ZCELL是否被独占: 0-未被独占，1-已经被独占*/
+
+/**  zcell属性标志*/
+#define DPP_ZREG_FLAG_IS_MONO \
+	(1) /**<  @brief ZREG是否被独占:  0-未被独占，1-已经被独占*/
+
+/* zcell 的配置信息*/
+typedef struct se_zcell_cfg {
+	ZXIC_UINT8
+	flag; /* zcell属性标志，各比特的含义见上面DPP_ZCELL_FLAG_MODE等的定义 */
+	ZXIC_UINT32 bulk_id; /* zcell所属空间ID  */
+	ZXIC_UINT32 zcell_idx; /* zcell 的索引值, 高6bit为zblock的索引     */
+	ZXIC_UINT16 mask_len; /* 掩码长度 */
+	ZXIC_UINT8 is_used; /* 本zcell是否被占用*/
+	ZXIC_UINT8 is_share; /* 是否共享block中的zcell*/
+	ZXIC_UINT32 item_used;
+	SE_ITEM_CFG item_info[SE_RAM_DEPTH]; /* 本zcell的基本存储单元配置*/
+
+	D_NODE zcell_dn; /* 双链表节点，初始化其data指针指向SE_ZCELL_CFG实例自身，然后插入双链表中*/
+	ZXIC_AVL_NODE zcell_avl; /* 本hash程序未使用， 平衡二叉树节点*/
+} SE_ZCELL_CFG;
+/* zreg 的配置信息*/
+typedef struct se_zreg_cfg {
+	ZXIC_UINT8
+	flag; /* z属性标志，各比特的含义见上面DPP_ZCELL_FLAG_MODE等的定义 */
+	ZXIC_UINT8 pad[3];
+	ZXIC_UINT32 bulk_id; /* zcell所属空间ID  */
+	SE_ITEM_CFG item_info; /* zreg 存储的表条目配置*/
+} SE_ZREG_CFG;
+/* zblock 的配置信息*/
+typedef struct se_zblk_cfg {
+	ZXIC_UINT32 zblk_idx; /* 统一编址，范围0~31 */
+	ZXIC_UINT16 is_used; /* 本zblock 是否被占用 */
+	ZXIC_UINT16 zcell_bm; /* 本hash程序未使用 */
+	ZXIC_UINT16 hash_arg; /* hash crc算法的因子 */
+	ZXIC_UINT16 pad;
+
+	SE_ZCELL_CFG zcell_info[SE_ZCELL_NUM]; /* 本block的4个zcell配置 */
+	SE_ZREG_CFG zreg_info[SE_ZREG_NUM]; /* 本block的4个zreg配置*/
+
+	D_NODE zblk_dn; /* 指向本实例的双链表节点 */
+
+} SE_ZBLK_CFG;
+/* alg表类型配置，包括4路hash引擎和v4 和 v6 lpm表项*/
+typedef struct func_id_info {
+	ZXIC_VOID *fun_ptr;
+	ZXIC_UINT8 fun_type; /* 业务类型 参见 SE_FUN_TYPE */
+	ZXIC_UINT8 fun_id;
+	ZXIC_UINT8 is_used;
+	ZXIC_UINT8 pad;
+} FUNC_ID_INFO;
+
+typedef struct ddr_mem {
+	ZXIC_UINT32 total_num;
+	ZXIC_UINT32 base_addr;
+	ZXIC_UINT32 base_addr_offset;
+	ZXIC_UINT32 ecc_en;
+	ZXIC_UINT32 bank_num;
+	ZXIC_UINT32 bank_info[SE_ALG_BANK_NUM];
+	ZXIC_UINT32 share_type; /* DDR bank共享模式 */
+	ZXIC_UINT32 item_used;
+	ZXIC_LISTSTACK_MANGER *p_ddr_mng;
+} DDR_MEM;
+
+typedef struct share_ram {
+	ZXIC_UINT32 zblk_array[SE_ZBLK_NUM];
+	D_HEAD zblk_list;
+	D_HEAD zcell_free_list;
+	ZXIC_UINT32 def_route_num;
+
+	ZXIC_RB_CFG def_rb;
+	struct def_route_info *p_dr_info;
+
+	DDR_MEM ddr4_info;
+	DDR_MEM ddr6_info;
+} SHARE_RAM;
+
+/**
+ * 算法模块管理数据结构，用户仅需创建实例变量，然后将指针传给初始化函数dpp_se_init()和dpp_se_client_init()即可，不需要单独赋值成员变量*/
+typedef struct dpp_se_cfg {
+	SE_ZBLK_CFG zblk_info[SE_ZBLK_NUM];
+
+	FUNC_ID_INFO fun_info[MAX_FUN_NUM];
+
+	SHARE_RAM route_shareram;
+	ZXIC_UINT32 reg_base;
+
+	WRITE32_FUN p_write32_fun;
+	READ32_FUN p_read32_fun;
+
+	ZXIC_UINT32 lpm_flags;
+
+	ZXIC_VOID *p_client;
+
+	DPP_DEV_T *dev;
+	ZXIC_UINT32 dev_id;
+
+	LPM_AS_RSLT_WRT_FUNCTION p_as_rslt_wrt_fun; /* dpp_se_lpm_as_rslt_write */
+} DPP_SE_CFG;
+
+/**  hash物理存储位宽类型*/
+typedef enum dpp_hash_ddr_width_mode {
+	DDR_WIDTH_INVALID = 0,
+	DDR_WIDTH_256b, /**<  @brief 256bit位宽模式*/
+	DDR_WIDTH_512b, /**<  @brief 512bit位宽模式*/
+} DPP_HASH_DDR_WIDTH_MODE;
+
+/**  hash条目类型*/
+typedef enum dpp_hash_key_type {
+	HASH_KEY_INVALID = 0, /**<  @brief 无效类型*/
+	HASH_KEY_128b, /**<  @brief 128bit位宽类型*/
+	HASH_KEY_256b, /**<  @brief 256bit位宽类型*/
+	HASH_KEY_512b, /**<  @brief 512bit位宽类型*/
+} DPP_HASH_KEY_TYPE;
+
+/**  hash ddr resource cfg info*/
+typedef struct dpp_hash_ddr_resc_cfg_t {
+	ZXIC_UINT32
+	ddr_width_mode; /**<  @brief 分配给hash的DDR空间物理存储位宽模式，取值参考DPP_HASH_DDR_WIDTH_MODE的定义*/
+	ZXIC_UINT32
+	ddr_crc_sel; /**<  @brief 选择一个DDR CRC多项式，取值范围0~3,0~3分别对应一个CRC多项式*/
+	ZXIC_UINT32
+	ddr_item_num; /**<  @brief 分配给hash的DDR空间单元数目，以256bit为一个单元*/
+	ZXIC_UINT32
+	ddr_baddr; /**<  @brief 分配给hash的DDR空间的硬件基地址,以2k*256bit为单位*/
+	ZXIC_UINT32 ddr_ecc_en; /**<  @brief DDR ECC使能: 0-不使能，1-使能*/
+} DPP_HASH_DDR_RESC_CFG_T;
+
+/** hash search mode */
+typedef enum dpp_hash_srh_mode {
+	HASH_SRH_MODE_SOFT = 1, /**<  @brief 查软件 */
+	HASH_SRH_MODE_HDW = 2, /**<  @brief 查硬件 */
+} DPP_HASH_SRH_MODE;
+
+/** hash tbl_flag */
+#define HASH_TBL_FLAG_AGE \
+	(1 << 0) /**<  @brief 老化保活置位使能: 0-不使能；1-使能*/
+#define HASH_TBL_FLAG_LEARN \
+	(1 << 1) /**<  @brief 硬件学习使能: 0-不使能；1-使能*/
+#define HASH_TBL_FLAG_MC_WRT \
+	(1 << 2) /**<  @brief 微码写表使能: 0-不使能，1-使能 */
+
+/**  hash条目*/
+typedef struct dpp_hash_entry {
+	ZXIC_UINT8 *p_key; /**<  @brief 键值，格式详见各操作函数的说明*/
+	ZXIC_UINT8 *p_rst; /**<  @brief 结果*/
+} DPP_HASH_ENTRY;
+
+/**  前缀路由业务初始化标志*/
+#define LPM_FLAG_RT_HANDLE_START \
+	(0) /**<  @brief 是否使能级联结果表查找: 0-不使能，1-使能*/
+#define LPM_FLAG_RT_HANDLE_WIDTH (1)
+#define LPM4_FLAG_DDR_EN_START \
+	(1) /**<  @brief 是否使能ipv4片外查找模式: 0-不使能，1-使能 */
+#define LPM4_FLAG_DDR_EN_WIDTH (1)
+#define LPM6_FLAG_DDR_EN_START \
+	(2) /**<  @brief 是否使能ipv6片外查找模式: 0-不使能，1-使能 */
+#define LPM6_FLAG_DDR_EN_WIDTH (1)
+#define LPM4_FLAG_DDR_SEL_START \
+	(3) /**<  @brief 是否为ipv4非线速模式: 0-线速，1-非线速 */
+#define LPM4_FLAG_DDR_SEL_WIDTH (1)
+#define LPM6_FLAG_DDR_SEL_START \
+	(4) /**<  @brief 是否为ipv6非线速模式: 0-线速，1-非线速 */
+#define LPM6_FLAG_DDR_SEL_WIDTH (1)
+#define LPM_FLAG_AS_MODE_START \
+	(5) /**<  @brief 级联结果表模式: 1-级联DDR，0-级联eRam  */
+#define LPM_FLAG_AS_MODE_WIDTH (1)
+
+/**  前缀匹配路由级联DDR结果表返回位宽模式*/
+typedef enum dpp_route_as_rsp_len_e {
+	DPP_ROUTE_AS_128b = 0, /**<  @brief 返回128bit模式*/
+	DPP_ROUTE_AS_256b = 1, /**<  @brief 返回256bit模式*/
+	DPP_ROUTE_AS_384b = 2, /**<  @brief 返回384bit模式*/
+	DPP_ROUTE_AS_512b = 3 /**<  @brief 返回512bit模式*/
+} DPP_ROUTE_AS_RSP_LEN_E;
+
+/**  前缀匹配路由业务ID*/
+typedef enum dpp_route_id_e {
+	DPP_ROUTE_V4_ID = 4, /**<  @brief route ipv4 ID*/
+	DPP_ROUTE_V6_ID = 5, /**<  @brief route ipv6 ID*/
+} DPP_ROUTE_ID_E;
+
+/**  前缀匹配路由业务模式*/
+typedef enum dpp_route_mode_e {
+	DPP_ROUTE_MODE_IPV4 = 1UL, /**<  @brief ipv4路由模式*/
+	DPP_ROUTE_MODE_IPV6 /**<  @brief ipv6路由模式*/
+} DPP_ROUTE_MODE_E;
+
+/**  前缀匹配路由DDR空间占用模式*/
+typedef enum dpp_route_ddr_use_mode_e {
+	DPP_ROUTE_DDR_USE_MINOR = 1, /**<  @brief DDR使用量较少*/
+	DPP_ROUTE_DDR_USE_MIDDLE = 2, /**<  @brief DDR使用量中等*/
+	DPP_ROUTE_DDR_USE_MAJOR = 3, /**<  @brief DDR使用量较多*/
+} DPP_ROUTE_DDR_USE_MODE_E;
+
+/**  前缀匹配路由调试查找模式*/
+typedef enum dpp_route_srh_mode_e {
+	DPP_ROUTE_SRH_MODE_LP = 1, /**<  @brief 前缀匹配查找模式*/
+	DPP_ROUTE_SRH_MODE_EQUAL = 2, /**<  @brief 精确匹配查找模式*/
+} DPP_ROUTE_SRH_MODE_E;
+
+/**  前缀匹配路由硬件资源 */
+typedef struct dpp_route_resource_t {
+	ZXIC_UINT32 zblk_num; /**<  @brief LPM ipv4和ipv6共享的zblock数目*/
+	ZXIC_UINT32 *zblk_idx; /**<  @brief LPM ipv4和ipv6共享的zblock编号数组*/
+	ZXIC_UINT32
+	ddr4_item_num; /**<  @brief 分配给ipv4前缀查找的ddr存储条目数，以256bit为单位*/
+	ZXIC_UINT32
+	ddr4_baddr; /**<  @brief 分配给ipv4前缀查找的ddr存储空间的基地址，以4K*128bit为单位*/
+	ZXIC_UINT32
+	ddr4_base_offset; /**<  @brief ipv4前缀查找相对于片外ddr存储空间基地址的偏移量，以256bit为单位*/
+	ZXIC_UINT32
+	ddr4_ecc_en; /**<  @brief 固定配为1，分配给ipv4前缀查找的ddr存储空间的ECC校验使能标志*/
+	ZXIC_UINT32
+	ddr4_bank_num; /**<  @brief ipv4前缀查找的ddr存储空间bank复制份数 */
+	ZXIC_UINT32 *
+			ddr4_bank_info; /**<  @brief ipv4前缀查找的ddr存储空间bank号，数组传入，支持离散分配*/
+	ZXIC_UINT32
+	ddr4_share_type; /**<  @brief ipv4前缀查找的ddr存储空间bank共享模式，参见SMMU1_DDR_SHARE_MODE_E*/
+	ZXIC_UINT32
+	ddr6_item_num; /**<  @brief 分配给ipv6前缀查找的ddr存储条目数，以256bit为单位*/
+	ZXIC_UINT32
+	ddr6_baddr; /**<  @brief 分配给ipv6前缀查找的ddr存储空间的基地址，以4K*128bit为单位*/
+	ZXIC_UINT32
+	ddr6_base_offset; /**<  @brief ipv6前缀查找相对于片外ddr存储空间基地址的偏移量，以256bit为单位*/
+	ZXIC_UINT32
+	ddr6_ecc_en; /**<  @brief 固定配为1，分配给ipv4前缀查找的ddr存储空间的ECC校验使能标志*/
+	ZXIC_UINT32
+	ddr6_bank_num; /**<  @brief ipv6前缀查找的ddr存储空间bank复制份数 */
+	ZXIC_UINT32 *
+			ddr6_bank_info; /**<  @brief ipv6前缀查找的ddr存储空间bank号，数组传入，支持离散分配*/
+	ZXIC_UINT32
+	ddr6_share_type; /**<  @brief ipv6前缀查找的ddr存储空间bank共享模式，参见SMMU1_DDR_SHARE_MODE_E*/
+} DPP_ROUTE_RESOURCE_T;
+
+/**  前缀匹配路由级联片内eRam结果表属性 */
+typedef struct dpp_route_as_eram_t {
+	ZXIC_UINT32 baddr; /**<  @brief LPM级联eRam结果基地址*/
+	ZXIC_UINT32
+	rsp_mode; /**<  @brief LPM级联eRam结果位宽模式，取值参照ERAM128_TBL_MODE_E的定义*/
+} DPP_ROUTE_AS_ERAM_T;
+
+/**  前缀匹配路由级联片外DDR结果表属性 */
+typedef struct dpp_route_as_ddr_t {
+	ZXIC_UINT32
+	baddr; /**<  @brief 分配给级联ddr结果表空间的基地址，以4K*128bit为单位*/
+	ZXIC_UINT32
+	rsp_len; /**<  @brief LPM级联DDR结果位宽模式，取值参照DPP_ROUTE_AS_RSP_LEN_E的定义*/
+	ZXIC_UINT32
+	ecc_en; /**<  @brief 级联结果表DDR空间ECC校验使能标志: 0-不使能，1-使能*/
+} DPP_ROUTE_AS_DDR_T;
+
+typedef union dpp_route_as_rslttbl_u {
+	DPP_ROUTE_AS_ERAM_T as_eram_cfg; /**<  @brief LPM级联eRam结果表空间属性*/
+	DPP_ROUTE_AS_DDR_T as_ddr_cfg; /**<  @brief LPM级联DDR结果表空间属性*/
+} DPP_ROUTE_AS_RSLTTBL_U;
+
+/**  前缀匹配IPv4键值*/
+typedef struct dpp_route_ipv4_key_t {
+	ZXIC_UINT32 vpnid; /**<  @brief vpnid，16bit*/
+	ZXIC_UINT32
+	mask_len; /**<  @brief IP地址的掩码长度，最小为0(表示默认路由)，最大为32*/
+	ZXIC_UINT32 ipv4_addr; /**<  @brief IP地址，32bit*/
+} DPP_ROUTE_IPV4_KEY_T;
+
+/**  前缀匹配IPv4单个路由条目*/
+typedef struct dpp_route_entry_ipv4_t {
+	DPP_ROUTE_IPV4_KEY_T route_key; /**<  @brief 键值*/
+	ZXIC_UINT32 route_handle; /**<  @brief 键值匹配后，继续查转发结果表的索引*/
+	ZXIC_UINT8 *
+			p_as_rslt; /**<  @brief 转发结果，仅在使能lpm关联结果查找的情况下有效 */
+} DPP_ROUTE_ENTRY_IPV4_T;
+
+/**  前缀匹配IPv6键值*/
+typedef struct dpp_route_ipv6_key_t {
+	ZXIC_UINT32 vpnid; /**<  @brief vpnid，16bit*/
+	ZXIC_UINT32
+	mask_len; /**<  @brief IP地址的掩码长度，最小为0(表示默认路由)，最大为128*/
+	ZXIC_UINT32 ipaddr[4]; /**<  @brief IP地址，128bit*/
+} DPP_ROUTE_IPV6_KEY_T;
+
+/**  前缀匹配IPv6单个路由条目*/
+typedef struct dpp_route_entry_ipv6_t {
+	DPP_ROUTE_IPV6_KEY_T route_key; /**<  @brief 键值*/
+	ZXIC_UINT32 route_handle; /**<  @brief 键值匹配后，继续查转发结果表的索引*/
+	ZXIC_UINT8 *
+			p_as_rslt; /**<  @brief 转发结果，仅在使能lpm关联结果查找的情况下有效 */
+} DPP_ROUTE_ENTRY_IPV6_T;
+
+/* 在HASH进行初始化的时候，需要存储的参数 */
+typedef struct dpp_hash_soft_reset_stor_dat {
+	/* 参照dpp_hash_init()的参数 */
+	ZXIC_UINT32 ddr_dis_flag[4]; /**<  @brief 4个HASH引擎是否DISABLE DDR标志 */
+	ZXIC_UINT32 zblk_num[4]; /**<  @brief 4个HASH引擎使用的zblk数量 */
+	ZXIC_UINT32
+	*zblk_idx_start[4]; /**<  @brief 4个HASH引擎使用的起始zblk index */
+
+	/* 参照dpp_hash_bulk_init()的参数 */
+	ZXIC_UINT32 ddr_item_num[4][8]; /**<  @brief 每个bulk空间存放的ddr item数 */
+	ZXIC_UINT32 ddr_base_addr[4]; /**<  @brief 每个hash引擎基地址 */
+	ZXIC_UINT32 ddr_bank_cp[4]; /**<  @brief 每个hash引擎bank copy数量 */
+	ZXIC_UINT32 ddr_ecc_en[4]; /**<  @brief ddr是否开启ecc使能 */
+
+	/*     ZXIC_UINT32 ddr_width_mode[4]; */ /**<  @brief ddr存储位宽 */
+	/*     ZXIC_UINT32 ddr_crc_sel[4];  */ /**<  @brief ddr多项式选择 */
+	/*     ZXIC_UINT32 ddr_share_type[4]; */ /**<  @brief ddr 共享类型 */
+
+	ZXIC_UINT32 hash_id_valid; /** HASH引擎是否已经初始化标志 */
+} DPP_HASH_SOFT_RESET_STOR_DAT;
+
+/***********************************************************/
+/** 初始化算法管理数据结构，不包含用户自定义的数据指针
+ * @param   p_se_cfg  算法管理数据结构指针
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/05/20
+ ************************************************************/
+DPP_STATUS dpp_se_init(DPP_DEV_T *dev, DPP_SE_CFG *p_se_cfg);
+
+/***********************************************************/
+/** 初始化算法管理数据结构用户自定义的数据指针，当前仅用于传入设备号的值
+ * @param   p_se_cfg  算法管理数据结构指针
+ * @param   p_client  用户自定义的数据指针
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/05/20
+ ************************************************************/
+DPP_STATUS dpp_se_client_init(DPP_SE_CFG *p_se_cfg, ZXIC_VOID *p_client);
+
+/***********************************************************/
+/** 单个hash引擎初始化
+ * @param   p_se_cfg      算法模块公共管理数据结构指针
+ * @param   fun_id         hash引擎号
+ * @param   zblk_num      分配给此hash引擎的zblock数目
+ * @param   zblk_idx      分配给此hash引擎的zblock编号
+ * @param   ddr_dis       DDR关闭位，0-不关闭片外DDR, 1-关闭片外DDR
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/05/15
+ ************************************************************/
+DPP_STATUS dpp_hash_init(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id,
+						 ZXIC_UINT32 zblk_num, ZXIC_UINT32 *zblk_idx,
+						 ZXIC_UINT32 ddr_dis);
+
+/***********************************************************/
+/** 初始化单个hash引擎内的某个业务表，此接口支持为该业务表分配独占的zcell。
+ *     必须先初始化hash引擎，再初始化业务表。
+ * @param   p_se_cfg        算法模块公共管理数据结构指针
+ * @param   fun_id         hash引擎号
+ * @param   bulk_id         每个Hash引擎资源划分的空间ID号
+ * @param   p_ddr_resc_cfg  分配给hash引擎此资源空间的ddr资源属性
+ * @param   zcell_num       分配给hash引擎此资源空间的zcell数量
+ * @param   zreg_num        分配给hash引擎此资源空间的zreg数量
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/05/15
+ ************************************************************/
+DPP_STATUS dpp_hash_bulk_init(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id,
+							  ZXIC_UINT32 bulk_id,
+							  DPP_HASH_DDR_RESC_CFG_T *p_ddr_resc_cfg,
+							  ZXIC_UINT32 zcell_num, ZXIC_UINT32 zreg_num);
+
+/***********************************************************/
+/** 初始化单个hash引擎内的某个业务表，此接口支持为该业务表分配独占的zcell。
+ *   必须先初始化hash引擎，如果是片内+片外模式还必须先初始化dpp_hash_ddr_bulk_init，
+ *   再初始化业务表。
+ * @param   p_se_cfg    算法模块公共管理数据结构指针
+ * @param   fun_id      hash引擎号
+ * @param   tbl_id          业务表
+ * @param   tbl_flag        初始化标记, bitmap的形式使用，如:HASH_TBL_FLAG_AGE等
+ * @param   key_type        hash条目类型，取值参照DPP_HASH_KEY_TYPE的定义
+ * @param   actu_key_size   业务键值有效长度: 8bit*N，N=1~48
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/05/15
+ ************************************************************/
+DPP_STATUS dpp_hash_tbl_id_info_init(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id,
+									 ZXIC_UINT32 tbl_id, ZXIC_UINT32 tbl_flag,
+									 ZXIC_UINT32 key_type,
+									 ZXIC_UINT32 actu_key_size);
+
+#endif
+
+#if ZXIC_REAL("eTcam data struct and function")
+typedef DPP_STATUS (*ACL_AS_RSLT_WRT_FUNCTION)(ZXIC_UINT32 dev_id,
+											   ZXIC_UINT32 base_addr,
+											   ZXIC_UINT32 index,
+											   ZXIC_UINT32 as_mode,
+											   ZXIC_UINT8 *p_data);
+#define DPP_ACL_TBL_ID_NUM (8U)
+#define DPP_ACL_ETCAM_ID_NUM (1U)
+#define DPP_ACL_BLOCK_NUM (8U)
+
+/**  eTcam条目位宽模式*/
+typedef enum dpp_etcam_entry_mode_e {
+	DPP_ETCAM_KEY_640b = 0,
+	DPP_ETCAM_KEY_320b = 1,
+	DPP_ETCAM_KEY_160b = 2,
+	DPP_ETCAM_KEY_80b = 3,
+	DPP_ETCAM_KEY_INVALID,
+} DPP_ETCAM_ENTRY_MODE_E;
+
+/**  eTcam操作类型*/
+typedef enum dpp_etcam_opr_type_e {
+	DPP_ETCAM_OPR_DM = 0, /**<  @brief data & mask类型*/
+	DPP_ETCAM_OPR_XY = 1, /**<  @brief X & Y类型*/
+} DPP_ETCAM_OPR_TYPE_E;
+
+/**  eTcam条目格式*/
+typedef struct dpp_etcam_entry_t {
+	ZXIC_UINT32
+	mode; /**<  @brief 条目位宽模式: 2'b00-640bit,2'b01-320bit,2'b10-160bit,2'b11-80bit*/
+	ZXIC_UINT8 *p_data; /**<  @brief 键值*/
+	ZXIC_UINT8 *p_mask; /**<  @brief 掩码*/
+} DPP_ETCAM_ENTRY_T;
+
+/**  ACL键值位宽模式*/
+typedef enum dpp_acl_key_mode_e {
+	DPP_ACL_KEY_640b = 0, /**<  @brief 640bit键值位宽*/
+	DPP_ACL_KEY_320b, /**<  @brief 320bit键值位宽*/
+	DPP_ACL_KEY_160b, /**<  @brief 160bit键值位宽*/
+	DPP_ACL_KEY_80b, /**<  @brief 80bit键值位宽*/
+	DPP_ACL_KEY_INVALID,
+} DPP_ACL_KEY_MODE_E;
+
+/**  ACL关联查找结果表位宽模式*/
+typedef enum dpp_acl_as_mode_e {
+	DPP_ACL_AS_MODE_16b = 0,
+	DPP_ACL_AS_MODE_32b = 1,
+	DPP_ACL_AS_MODE_64b = 2, /**<  @brief 64bit结果位宽*/
+	DPP_ACL_AS_MODE_128b = 3, /**<  @brief 128bit结果位宽*/
+	DPP_ACL_AS_MODE_INVALID,
+} DPP_ACL_AS_MODE_E;
+
+/**  ACL调试查找模式*/
+typedef enum dpp_acl_srh_mode_e {
+	DPP_ACL_SRH_SOFT = 0, /**<  @brief 查软件*/
+	DPP_ACL_SRH_HARDWARE = 1, /**<  @brief 查硬件*/
+} DPP_ACL_SRH_MODE_E;
+
+/**  ACL条目*/
+typedef struct dpp_acl_entry_t {
+	ZXIC_UINT32 handle; /**<  @brief 条目索引*/
+	ZXIC_UINT8 *key_data; /**<  @brief 键值data部分*/
+	ZXIC_UINT8 *key_mask; /**<  @brief 键值mask部分: 0为关心，1为不关心*/
+	ZXIC_UINT8 *p_as_rslt; /**<  @brief 关联结果，仅使能关联查找情况有效*/
+} DPP_ACL_ENTRY_T;
+
+typedef struct dpp_acl_block_info_t {
+	ZXIC_UINT32 is_used;
+	ZXIC_UINT32 tbl_id;
+	ZXIC_UINT32 idx_base;
+} DPP_ACL_BLOCK_INFO_T;
+
+typedef struct dpp_acl_etcamid_cfg_t {
+	ZXIC_UINT32 is_valid;
+	ZXIC_UINT32 as_enable; /* eTcam自动关联eRam结果表使能: 0-不使能，1-使能 */
+	ZXIC_UINT32 as_idx_offset; /* 关联结果表基地址偏移，以128bit为单位 */
+	ZXIC_UINT32
+	as_eRam_base; /* eTcam自动关联的eRam block的基地址，以128bit为单位 */
+	D_HEAD tbl_list;
+} DPP_ACL_ETCAMID_CFG_T;
+
+typedef struct dpp_acl_key_info_t {
+	ZXIC_UINT32 handle;
+	ZXIC_UINT32 pri;
+	ZXIC_UINT8 key[0]; /* data+mask */
+} DPP_ACL_KEY_INFO_T;
+
+/**  ACL初始化使能标志*/
+#define DPP_ACL_FLAG_ETCAM0_EN \
+	(1 << 0) /**<  @brief 开启eTcam端口0: 0-不开启，1-开启.*/
+#define DPP_ACL_FLAG_ETCAM0_AS \
+	(1 << 2) /**<  @brief 开启eTcam端口0的关联结果查找: 0-不开启，1-开启.*/
+//#define DPP_ACL_FLAG_ETCAM1_AS        (1<<3) /**<  @brief 开启eTcam端口1的关联结果查找: 0-不开启，1-开启.*/
+
+typedef DPP_STATUS (*ACL_TBL_AS_DDR_WR_FUN)(
+		ZXIC_UINT32 dev_id, ZXIC_UINT32 tbl_type, ZXIC_UINT32 tbl_id,
+		ZXIC_UINT32 dir_tbl_share_type, ZXIC_UINT32 dir_tbl_base_addr,
+		ZXIC_UINT32 ecc_en, ZXIC_UINT32 index, ZXIC_UINT32 as_mode,
+		ZXIC_UINT8 *p_data);
+typedef DPP_STATUS (*ACL_TBL_AS_DDR_RD_FUN)(ZXIC_UINT32 dev_id,
+											ZXIC_UINT32 base_addr,
+											ZXIC_UINT32 index,
+											ZXIC_UINT32 as_mode,
+											ZXIC_UINT8 *p_data);
+
+/**  */
+typedef struct dpp_acl_tbl_cfg_t {
+	ZXIC_UINT32 tbl_type;
+	ZXIC_UINT32 table_id;
+	ZXIC_UINT8 is_as_ddr;
+	ZXIC_UINT8 ddr_bankcp_info;
+	ZXIC_UINT32 dir_tbl_share_type;
+	ZXIC_UINT8 ddr_ecc_en;
+	ZXIC_UINT32 pri_mode;
+	ZXIC_UINT32 key_mode;
+	ZXIC_UINT32 entry_num;
+	ZXIC_UINT32 block_num;
+	ZXIC_UINT32 *block_array;
+	ZXIC_UINT32 is_used;
+	ZXIC_UINT32 as_mode;
+	ZXIC_UINT32 as_idx_base;
+	ZXIC_UINT32 as_enable; /* eTcam自动关联eRam结果表使能: 0-不使能，1-使能 */
+	ZXIC_UINT32
+	as_eRam_base; /* eTcam自动关联的eRam block的基地址，以128bit为单位 */
+	ZXIC_UINT32 ddr_baddr;
+	ZXIC_UINT32
+	idx_offset; /* 相对于ddr_baddr的基地址的索引偏移，以as_mode对应的数据位宽为单位 */
+	ACL_TBL_AS_DDR_WR_FUN p_as_ddr_wr_fun;
+	ACL_TBL_AS_DDR_RD_FUN p_as_ddr_rd_fun;
+	D_NODE entry_dn;
+	INDEX_FILL_CFG index_mng;
+	ZXIC_RB_CFG acl_rb;
+	DPP_ACL_KEY_INFO_T **acl_key_buff;
+	ZXIC_UINT8 *as_rslt_buff;
+} DPP_ACL_TBL_CFG_T;
+
+/**  ACL公共管理数据结构*/
+typedef struct dpp_acl_cfg_t {
+	ZXIC_VOID *p_client;
+	DPP_DEV_T *dev;
+	ZXIC_UINT32 dev_id;
+	ZXIC_UINT32 flags;
+	ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_write_fun;
+	ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_read_fun;
+	DPP_ACL_BLOCK_INFO_T acl_blocks[DPP_ACL_BLOCK_NUM];
+	DPP_ACL_ETCAMID_CFG_T acl_etcamids;
+	DPP_ACL_TBL_CFG_T acl_tbls[DPP_ACL_TBL_ID_NUM];
+} DPP_ACL_CFG_T;
+
+/**<  @brief ACL公共管理数据结构*/
+typedef struct dpp_acl_cfg_ex_t {
+	ZXIC_VOID *p_client;
+	DPP_DEV_T *dev;
+	ZXIC_UINT32 dev_id;
+	ZXIC_UINT32 flags;
+	ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_write_fun;
+	ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_read_fun;
+	DPP_ACL_BLOCK_INFO_T acl_blocks[DPP_ACL_BLOCK_NUM];
+	DPP_ACL_ETCAMID_CFG_T acl_etcamids;
+	DPP_ACL_TBL_CFG_T acl_tbls[DPP_ACL_TBL_ID_NUM];
+} DPP_ACL_CFG_EX_T;
+
+/**  acl优先级模式*/
+typedef enum dpp_acl_pri_mode_e {
+	DPP_ACL_PRI_EXPLICIT = 1, /**<  @brief 显示优先级*/
+	DPP_ACL_PRI_IMPLICIT, /**<  @brief 隐式优先级，以条目下发顺序作为优先级*/
+	DPP_ACL_PRI_SPECIFY, /**<  @brief 用户指定每个条目的在tcam中的存放索引*/
+	DPP_ACL_PRI_INVALID,
+} DPP_ACL_PRI_MODE_E;
+
+/**  */
+typedef struct dpp_acl_entry_ex_t {
+	ZXIC_UINT32 idx_val; /**<  @brief 一次插入单个acl条目时有效，返回单个索引*/
+	D_HEAD idx_list; /**<  @brief 一次插入多个acl条目时有效，返回多个索引*/
+	ZXIC_UINT32
+	pri; /* PRI_EXPLICIT: pri is priority, PRI_IMPLICIT: pri is invalid, PRI_SPECIFY: pri is handle */
+	ZXIC_UINT8 *key_data;
+	ZXIC_UINT8 *key_mask;
+	ZXIC_UINT8 *p_as_rslt;
+} DPP_ACL_ENTRY_EX_T;
+
+/***********************************************************/
+/** eTcam模块初始化
+ * @param   dev_id 设备号
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/07/24
+ ************************************************************/
+DPP_STATUS dpp_etcam_init(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/**
+ * @param   p_acl_cfg   ACL公共管理数据结构指针
+ * @param   p_client   用户自定义的数据指针
+ * @param   flags
+ * @param   p_as_wrt_fun   关联结果写硬件表回调函数指针
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yxh      @date  2017/12/15
+ ************************************************************/
+DPP_STATUS dpp_acl_cfg_init_ex(DPP_DEV_T *dev, DPP_ACL_CFG_EX_T *p_acl_cfg,
+							   ZXIC_VOID *p_client, ZXIC_UINT32 flags,
+							   ACL_AS_RSLT_WRT_FUNCTION p_as_wrt_fun);
+
+/***********************************************************/
+/** acl业务表初始化，注意分配给一个table的多个block_idx
+    必须按从小到大的顺序给定。支持多个优先级模式，暂不对外开放。
+* @param   p_acl_cfg   ACL公共管理数据结构指针
+* @param   table_id   业务表号
+* @param   as_enable   是否使能关联结果查找，0-不使能，1-使能
+* @param   entry_num   最大条目数
+* @param   pri_mode   ACL优先级模式
+* @param   key_mode   ACL键值位宽模式, 取值参照DPP_ACL_KEY_MODE_E的定义
+* @param   as_mode   ACL关联查找结果表位宽模式
+* @param   as_baddr   基地址
+* @param   block_num   分配给当前业务表号的block数目
+* @param   p_block_idx   分配给当前业务表号的block编号数组
+*
+* @return
+* @remark  无
+* @see
+* @author  wcl      @date  2014/12/23
+************************************************************/
+DPP_STATUS dpp_acl_tbl_init_ex(DPP_ACL_CFG_EX_T *p_acl_cfg,
+							   ZXIC_UINT32 table_id, ZXIC_UINT32 as_enable,
+							   ZXIC_UINT32 entry_num,
+							   DPP_ACL_PRI_MODE_E pri_mode,
+							   ZXIC_UINT32 key_mode, DPP_ACL_AS_MODE_E as_mode,
+							   ZXIC_UINT32 as_baddr, ZXIC_UINT32 block_num,
+							   ZXIC_UINT32 *p_block_idx);
+DPP_STATUS dpp_acl_res_destroy(ZXIC_UINT32 dev_id);
+
+#endif
+
+#if ZXIC_REAL("SDT data struct and function")
+/** SDT属性中的表类型 */
+typedef enum dpp_sdt_table_type_e {
+	DPP_SDT_TBLT_INVALID = 0, /**<  @brief 无效类型*/
+	DPP_SDT_TBLT_eRAM = 1, /**<  @brief eRAM直接表类型*/
+	DPP_SDT_TBLT_DDR3 = 2, /**<  @brief DDR3直接表类型*/
+	DPP_SDT_TBLT_HASH = 3, /**<  @brief Hash表类型*/
+	DPP_SDT_TBLT_LPM = 4, /**<  @brief LPM表类型*/
+	DPP_SDT_TBLT_eTCAM = 5, /**<  @brief 片内Tcam表类型*/
+	DPP_SDT_TBLT_PORTTBL = 6, /**<  @brief 物理端口属性表*/
+	DPP_SDT_TBLT_MAX = 7,
+} DPP_SDT_TABLE_TYPE_E;
+
+/**  返回位宽模式*/
+typedef enum dpp_sdt_rsp_mode_e {
+	DPP_SDT_RSP_32b = 0, /**  返回32bit位宽表结果*/
+	DPP_SDT_RSP_64b = 1, /**  返回64bit位宽表结果*/
+	DPP_SDT_RSP_128b = 2, /**  返回128bit位宽表结果*/
+	DPP_SDT_RSP_256b = 3, /**  返回256bit位宽表结果*/
+} DPP_SDT_RSP_MODE_E;
+
+/**  eRam直接表SDT属性*/
+typedef struct dpp_sdt_tbl_eram_t {
+	ZXIC_UINT32 table_type; /** <@brief 查找表项类型 */
+	ZXIC_UINT32 eram_mode; /** <@brief eRam返回位宽 */
+	ZXIC_UINT32 eram_base_addr; /** <@brief eRam表项基地址，128bit为单位 */
+	ZXIC_UINT32 eram_table_depth; /** <@brief 表项深度，作为越界检查使用   */
+	ZXIC_UINT32 eram_clutch_en; /** <@brief 抓包使能 */
+} DPP_SDTTBL_ERAM_T;
+
+/**  DDR3直接表SDT属性*/
+typedef struct dpp_sdt_tbl_ddr3_t {
+	ZXIC_UINT32 table_type; /** <@brief 查找表项类型   */
+	ZXIC_UINT32 ddr3_base_addr; /** <@brief ddr 基地址     */
+	ZXIC_UINT32 ddr3_share_type; /** <@brief ddr 共享类型   */
+	ZXIC_UINT32 ddr3_rw_len; /** <@brief 表项返回/写入位宽 */
+	ZXIC_UINT32 ddr3_sdt_num; /** <@brief SDT表号/复制信息ram的表号 */
+	ZXIC_UINT32 ddr3_ecc_en; /** <@brief ecc使能        */
+	ZXIC_UINT32 ddr3_clutch_en; /** <@brief 抓包使能       */
+} DPP_SDTTBL_DDR3_T;
+
+/**  HASH表SDT属性*/
+typedef struct dpp_sdt_tbl_hash_t {
+	ZXIC_UINT32 table_type; /** <@brief 查找表项类型       */
+	ZXIC_UINT32 hash_id; /** <@brief 访问hash的引擎     */
+	ZXIC_UINT32 hash_table_width; /** <@brief hash 表项存储位宽  */
+	ZXIC_UINT32 key_size; /** <@brief hash 键值长度      */
+	ZXIC_UINT32 hash_table_id; /** <@brief hash 逻辑表号      */
+	ZXIC_UINT32 learn_en; /** <@brief 硬件学习使能       */
+	ZXIC_UINT32 keep_alive; /** <@brief 保活标志使能       */
+	ZXIC_UINT32 keep_alive_baddr; /** <@brief 保活标志基地址     */
+	ZXIC_UINT32 rsp_mode; /** <@brief 表项返回数据位宽   */
+	ZXIC_UINT32 hash_clutch_en; /** <@brief 抓包使能           */
+} DPP_SDTTBL_HASH_T;
+
+/**  LPM表SDT属性*/
+typedef struct dpp_sdt_tbl_lpm_t {
+	ZXIC_UINT32 table_type; /** <@brief 查找表项类型       */
+	ZXIC_UINT32 lpm_v46_id; /** <@brief ipv4/ipv6标志      */
+	ZXIC_UINT32 rsp_mode; /** <@brief 表项返回数据位宽   */
+	ZXIC_UINT32 lpm_table_depth; /** <@brief 表项深度，越界检查 */
+	ZXIC_UINT32 lpm_clutch_en; /** <@brief 抓包使能           */
+} DPP_SDTTBL_LPM_T;
+
+/**  eTCAM表SDT属性*/
+typedef struct dpp_sdt_tbl_etcam_t {
+	ZXIC_UINT32 table_type; /** <@brief 查找表项类型       */
+	ZXIC_UINT32 etcam_id; /** <@brief etcam通道         */
+	ZXIC_UINT32 etcam_key_mode; /** <@brief etcam键值长度      */
+	ZXIC_UINT32 etcam_table_id; /** <@brief etcam表项号        */
+	ZXIC_UINT32 no_as_rsp_mode; /** <@brief handle模式返回位宽 */
+	ZXIC_UINT32 as_en; /** <@brief 级联eram使能       */
+	ZXIC_UINT32 as_eram_baddr; /** <@brief 级联eram基地址     */
+	ZXIC_UINT32 as_rsp_mode; /** <@brief 级联返回位宽       */
+	ZXIC_UINT32 etcam_table_depth; /** <@brief 表项深度，越界检查 */
+	ZXIC_UINT32 etcam_clutch_en; /** <@brief 抓包使能           */
+} DPP_SDTTBL_ETCAM_T;
+
+/**  物理端口属性表SDT属性*/
+typedef struct dpp_sdt_tbl_porttbl_t {
+	ZXIC_UINT32 table_type; /** <@brief 查找表项类型       */
+	ZXIC_UINT32 porttbl_clutch_en; /** <@brief 抓包使能           */
+} DPP_SDTTBL_PORTTBL_T;
+
+/***********************************************************/
+/** 初始化SDT表配置管理
+ * @param   dev_num       设备数目
+ * @param   dev_id_array  设备dev_id数组
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/07/13
+ ************************************************************/
+DPP_STATUS dpp_sdt_init(ZXIC_UINT32 dev_num, ZXIC_UINT32 *dev_id_array);
+
+/***********************************************************/
+/** 写SDT属性表条目到硬件表，同时向8个cluster写入
+ * @param   dev_id      设备号
+ * @param   sdt_no      业务表对应的sdt号
+ * @param   table_type  SDT属性中的表类型，取值参考DPP_SDT_TABLE_TYPE_E的定义(仅添加操作时有效)
+ * @param   p_sdt_info  写入的SDT属性(仅添加操作时有效)。由table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n
+ *                      DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR3_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、\n
+ *                      DPP_SDTTBL_ETCAM_T、DPP_SDTTBL_XTCAM_T、DPP_SDTTBL_PORTTBL_T。
+ * @param   opr_type    操作类型: 0-添加条目，1-删除条目.
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/07/11
+ ************************************************************/
+DPP_STATUS dpp_sdt_tbl_write(DPP_DEV_T *dev, ZXIC_UINT32 sdt_no,
+							 ZXIC_UINT32 table_type, ZXIC_VOID *p_sdt_info,
+							 ZXIC_UINT32 opr_type);
+
+#endif
+
+#endif /*dpp_se_api.h*/
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_stat_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_stat_api.h
old mode 100755
new mode 100644
index 57377578eaebb351a7ee70dd8b9e049b7d53aa09..d45809fdf0eed50b6e7497fd9ca87d5558623d08
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_stat_api.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_stat_api.h
@@ -1,533 +1,511 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_stat_api.h
-* 文件标识 : stat计数模块对外数据类型定义和接口函数声明
-* 内容摘要 : 
-* 其它说明 : 
-* 当前版本 : 
-* 作    者 : xjw
-* 完成日期 : 2015/02/09
-* DEPARTMENT: ASIC_FPGA_R&D_Dept 
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* 版 本 号:  
-* 修 改 人:  
-* 修改内容:  
-***************************************************************/
-
-#ifndef _DPP_STAT_API_H_
-#define _DPP_STAT_API_H_
-
-
-#if ZXIC_REAL("header file")
-
-#include "dpp_dev.h"
-
-#endif
-
-#if ZXIC_REAL("data struct define")
-/**  STAT模块TM模式*/
-typedef enum stat_tm_mode_e
-{
-    STAT_TM_MODE_ETM = 0,        /**< @brief 上行TM */
-    STAT_TM_MODE_FTM = 1,        /**< @brief 下行TM */
-    STAT_TM_MODE_MAX
-}STAT_TM_MODE_E;
-
-/** TM统计端口选择 */
-typedef enum stat_tm_port_mode_e
-{
-    STAT_TM_PORT_MODE_0_1 = 0,      /**< @brief 端口0~1 */
-    STAT_TM_PORT_MODE_2_3 = 1,      /**< @brief 端口2~3 */
-    STAT_TM_PORT_MODE_MAX,
-}STAT_TM_PORT_MODE_E;
-
-/**TM统计计数模式选择  */
-typedef enum stat_tm_cnt_mode_e
-{
-    STAT_TM_CNT_MODE_MIX = 0,        /**< @brief 混合模式 */
-    STAT_TM_CNT_MODE_INNER = 1,      /**< @brief 内部模式 */
-    STAT_TM_CNT_MODE_MAX
-}STAT_TM_CNT_MODE_E;
-
-/* TM计数器类型，共支持20种  */
-typedef enum tm_stat_type_e {
-
-    TM_STAT_ENQUE_PKT                   = 0,  /**<  @brief 入队包计数*/
-    TM_STAT_ENQUE_VALID_PKT             = 1,  /**<  @brief 入队VALID包计数*/      
-    TM_STAT_ENQUE_DROP_PKT              = 2,  /**<  @brief 入队丢弃包计数*/      
-    TM_STAT_ENQUE_TD_PKT                = 3,  /**<  @brief 入队TD包计数*/      
-    TM_STAT_ENQUE_WRED_PKT              = 4,  /**<  @brief 入队WRED包计数*/      
-    TM_STAT_ENQUE_DP0_PKT               = 5,  /**<  @brief 入队DP0包计数*/      
-    TM_STAT_ENQUE_DP1_PKT               = 6,  /**<  @brief 入队DP1包计数*/     
-    TM_STAT_ENQUE_DP2_PKT               = 7,  /**<  @brief 入队DP2包计数*/     
-    TM_STAT_ENQUE_DP3_PKT               = 8,  /**<  @brief 入队DP3包计数*/      
-    TM_STAT_ENQUE_DP4_PKT               = 9,  /**<  @brief 入队DP4包计数*/      
-    TM_STAT_ENQUE_DP5_PKT               = 10, /**<  @brief 入队DP5包计数*/       
-    TM_STAT_ENQUE_DP6_PKT               = 11, /**<  @brief 入队DP6包计数*/    
-    TM_STAT_ENQUE_DP7_PKT               = 12, /**<  @brief 入队DP7包计数*/     
-    TM_STAT_ENQUE_BLOCK_PKT             = 13, /**<  @brief 入队BLOCK包计数*/     
-    TM_STAT_ENQUE_DISABLE_PKT           = 14, /**<  @brief 入队DISABLE包计数*/   
-    TM_STAT_DEQUE_PKT                   = 15, /**<  @brief 出队包计数*/
-    TM_STAT_DEQUE_VALID_PKT             = 16, /**<  @brief 出队VALID包计数*/
-    TM_STAT_DEQUE_DISCARD_PKT           = 17, /**<  @brief 出队DISCARD包计数*/
-    TM_STAT_DEQUE_CLEAR_PKT             = 18, /**<  @brief 出队CLEAR包计数*/   
-    TM_STAT_DEQUE_AGE_PKT               = 19, /**<  @brief 出队AGE包计数*/
-    TM_STAT_TYPE_UNEN                   = 20, /**<  @brief 不使能的时候，需配置成这个*/
-    TM_STAT_TYPE_MAX
-} TM_STAT_TYPE_E;
-
-/** car的监管类型 */
-typedef enum stat_car_type_e
-{
-    STAT_CAR_A_TYPE  = 0,      /**<  @brief A级CAR*/
-    STAT_CAR_B_TYPE,         /**<  @brief B级CAR*/
-    STAT_CAR_C_TYPE,         /**<  @brief C级CAR*/
-    STAT_CAR_MAX_TYPE
-}STAT_CAR_TYPE_E;
-
-/** car监管队列配置*/
-typedef struct stat_car_queue_cfg_t
-{
-    ZXIC_UINT32 queue_id;        /**<  @brief 队列号*/
-    ZXIC_UINT32 plcr_en;         /**<  @brief CAR使能*/
-    ZXIC_UINT32 drop_flag;       /**<  @brief 丢弃标记*/
-    ZXIC_VOID * profile_cfg;     /**< @brief carA的包模式时，结构体类型是DPP_STAT_CAR_PKT_PROFILE_CFG_T，其余模式组合时，结构体类型DPP_STAT_CAR_PROFILE_CFG_T*/    
-}STAT_CAR_QUEUE_CFG_T;
-
-/**  stat模块计数模式设置*/
-typedef struct stat_count_cfg_t
-{
-    ZXIC_UINT32 rd_mode;       /**< @brief 0:计数器在CPU读的下一拍自动清理,1:不自动清零*/
-    ZXIC_UINT32 overflow_mode; /**< @brief 0:计数器达到最大值后，一直保持最大值,1:计数器累积到最高1bit为1，最高1bit始终为1，而其余为继续计数*/
-}STAT_COUNT_CFG_T;
-
-/** stat 的smmu1属性 */
-typedef struct dpp_stat_smmu1_cfg_t
-{
-    ZXIC_UINT32 baddr;         /**<  @brief 基地址*/
-}DPP_STAT_SMMU1_CFG_T;
-
-/** stat模块公共配置 */
-typedef struct dpp_stat_comm_cfg_t
-{
-    DPP_STAT_SMMU1_CFG_T stat_smmu1_cfg[DPP_DEV_CHANNEL_MAX];   /**<  @brief stat 的smmu1属性*/
-    ZXIC_UINT32 is_init[DPP_DEV_CHANNEL_MAX];                        /**<  @brief 初始化选择*/
-}DPP_STAT_COMM_CFG_T;
-
-/** stat模块tm统计配置 */
-typedef struct dpp_stat_tm_cfg_t
-{
-    ZXIC_UINT32 tm_en;                          /**<  @brief TM统计使能 */
-    ZXIC_UINT32 mov_en;                         /**<  @brief 搬移使能*/
-    ZXIC_UINT32 eram_en;                        /**<  @brief 片内计数使能*/
-    ZXIC_UINT32 ftm_pkt_en;                     /**<  @brief ftm包计数使能*/
-    ZXIC_UINT32 etm_pkt_en;                     /**<  @brief etm包计数使能*/
-    ZXIC_UINT32 ftm_port_type[4];               /**<  @brief ftm包计数端口类型选择 参考 TM_STAT_TYPE_E */
-    ZXIC_UINT32 etm_port_type[4];               /**<  @brief etm包计数端口类型选择 参考 TM_STAT_TYPE_E */
-    ZXIC_UINT32 etm_start_queue_id;             /**<  @brief etm起始队列号*/
-    ZXIC_UINT32 etm_queue_depth_mode;           /**<  @brief etm队列深度*/
-    DPP_STAT_SMMU1_CFG_T ftm_smmu1_cfg;    /**<  @brief ftm统计的smmu1属性*/
-    DPP_STAT_SMMU1_CFG_T etm_smmu1_cfg;    /**<  @brief etm统计的smmu1属性*/
-    ZXIC_UINT32 is_init[DPP_DEV_CHANNEL_MAX];   /**<  @brief 初始化选择*/
-}DPP_STAT_TM_CFG_T;
-
-/** TM 统计计数信息 */
-typedef struct dpp_stat_tm_cnt_t
-{
-    ZXIC_UINT32 tm_cnt_en;               /**<  @brief tm计数使能*/
-    ZXIC_UINT32 tm_mode;                 /**<  @brief TM统计模式:0-ftm, 1-etm*/
-    ZXIC_UINT32 tm_flow_id;              /**<  @brief TM统计流号*/
-    ZXIC_UINT32 tm_stat_type;            /**<  @brief TM统计端口类型*/
-    ZXIC_UINT32 is_tm_byte_en;           /**<  @brief TM统计字节计数使能*/
-    ZXIC_UINT32 is_eram_en;              /**<  @brief TM统计片内计数使能*/
-    ZXIC_UINT64 tm_cnt;                  /**<  @brief TM计数结果*/
-}DPP_STAT_TM_CNT_T;
-
-/** STAT 中断状态  */
-typedef struct dpp_stat_brief_int_t
-{
-    ZXIC_UINT32 etcam_int;               /**< @brief etcam模块中断 */
-    ZXIC_UINT32 stat_sch_int;            /**< @brief stat sch剩余部分的中断状态 */
-}DPP_STAT_BRIEF_INT_T;
-
-/** STAT fifo中断状态选择  */
-typedef struct dpp_stat_sch_intr_t
-{
-    ZXIC_UINT32 hardware_rsv;            /**< @brief 系统保留，用户无需关心*/
-    ZXIC_UINT32 oam0_ord_fifo_int;       /**< @brief oam0保序模块中断*/
-    ZXIC_UINT32 oam2_ord_fifo_int;       /**< @brief oam2保序模块中断*/
-    ZXIC_UINT32 oam3_ord_fifo_int;       /**< @brief oam3保序模块中断*/
-    ZXIC_UINT32 ddr_sch_fifo_int;        /**< @brief ddr调度中断*/
-    ZXIC_UINT32 plcr_sch_fifo_int;       /**< @brief plcr调度中断*/
-    ZXIC_UINT32 stat_schd_fifo_int;      /**< @brief stat模块key调度中断*/
-    ZXIC_UINT32 stat_rschd_fifo_int;     /**< @brief stat模块rsp调度中断*/
-}DPP_STAT_SCH_INTR_T;
-
-/*stat 计数类型*/
-typedef enum stat_cnt_mode_e
-{
-    STAT_64_MODE  = 0,         /**<  @brief 64bit位宽模式*/
-    STAT_128_MODE = 1,         /**<  @brief 128bit位宽模式*/
-    STAT_MAX_MODE,
-}STAT_CNT_MODE_E;
-
-/**DPP STAT读清模式选择  */
-typedef enum stat_rd_clr_mode_e
-{
-    STAT_RD_CLR_MODE_UNCLR = 0,  /**<  @brief 不读请*/
-    STAT_RD_CLR_MODE_CLR   = 1,  /**<  @brief 读清*/
-    STAT_RD_CLR_MODE_MAX,
-}STAT_RD_CLR_MODE_E;
-
-/* car 优先级 */
-typedef enum dpp_car_priority_e
-{
-    DPP_CAR_PRI0 = 0,        /**<  @brief CAR优先级0配置*/
-    DPP_CAR_PRI1 = 1,        /**<  @brief CAR优先级1配置*/
-    DPP_CAR_PRI2 = 2,        /**<  @brief CAR优先级2配置*/
-    DPP_CAR_PRI3 = 3,        /**<  @brief CAR优先级3配置*/
-    DPP_CAR_PRI4 = 4,        /**<  @brief CAR优先级4配置*/
-    DPP_CAR_PRI5 = 5,        /**<  @brief CAR优先级5配置*/
-    DPP_CAR_PRI6 = 6,        /**<  @brief CAR优先级6配置*/
-    DPP_CAR_PRI7 = 7,        /**<  @brief CAR优先级7配置*/
-    DPP_CAR_PRI_MAX 
-}DPP_CAR_PRIORITY_E;
-
-/** car 监管模板参数设置的参数 */
-typedef struct dpp_stat_car_profile_cfg_t
-{
-    ZXIC_UINT32 profile_id;                        /**<  @brief car模板号*/
-    ZXIC_UINT32 pkt_sign;                          /**<  @brief 包限速选择标志*/
-    ZXIC_UINT32 cd;                                /**<  @brief CD算法标志/令牌桶算法标志 0:srtcm 1:trtcm 2:MEF10.1*/
-    ZXIC_UINT32 cf;                                /**<  @brief CF溢出耦合标志，0:不溢出，1:溢出*/
-    ZXIC_UINT32 cm;                                /**<  @brief CM色盲/色敏标志，0:色盲模式，1:色敏模式 */
-    ZXIC_UINT32 cir;                               /**<  @brief C令牌桶添加速率(0~X, X Gbps/64kbps),最小值为64Kbps，步长为64Kbps*/
-    ZXIC_UINT32 cbs;                               /**<  @brief C桶桶深(XM),配置范围为0~XMByte-1，步长为1Byte*/
-    ZXIC_UINT32 eir;                               /**<  @brief E令牌桶添加速率(0~X, XGbps/64kbps),最小值为64Kbps，步长为64Kbps*/
-    ZXIC_UINT32 ebs;                               /**<  @brief E桶桶深(XM),配置范围为0~XMByte-1，步长为1Byte*/
-    ZXIC_UINT32 random_disc_e;                     /**<  @brief 仅carB、carC支持 */
-    ZXIC_UINT32 random_disc_c;                     /**<  @brief 仅carB、carC支持 */
-    ZXIC_UINT32 c_pri[DPP_CAR_PRI_MAX];            /**<  @brief 仅pri 1~7是有效值*/
-    ZXIC_UINT32 e_green_pri[DPP_CAR_PRI_MAX];      /**<  @brief 仅pri 1~7是有效值*/
-    ZXIC_UINT32 e_yellow_pri[DPP_CAR_PRI_MAX];
-}DPP_STAT_CAR_PROFILE_CFG_T;
-
-/* car 独占smmu0的模式 */
-typedef enum dpp_car_smmu0_mono_mode_e
-{
-    CAR_SMMU0_MONO_MODE_NONE = 0,             /**<  @brief CAR不独占smmu0*/
-    CAR_SMMU0_MONO_MODE_1    = 1,             /**<  @brief CAR独占1片smmu0*/
-    CAR_SMMU0_MONO_MODE_2    = 2,             /**<  @brief CAR独占2片smmu0*/
-    CAR_SMMU0_MONO_MODE_MAX
-}DPP_CAR_SMMU0_MONO_MODE_E;
-
-/* TM统计的读清模式 */
-typedef enum stat_tm_clr_mode_e
-{
-    STAT_TM_CLR_MODE_UNCLR = 0,         /**<  @brief  TM统计不读请*/
-    STAT_TM_CLR_MODE_CLR   = 1,           /**<  @brief  TM统计读请*/
-    STAT_TM_CLR_MODE_MAX,
-}STAT_TM_CLR_MODE_E;
-
-/** car A 队列设置的参数 */
-typedef struct dpp_stat_car_a_queue_cfg_t
-{
-    ZXIC_UINT32 flow_id;
-    ZXIC_UINT32 drop_flag;
-    ZXIC_UINT32 plcr_en;
-    ZXIC_UINT32 profile_id;
-    ZXIC_UINT64 tq;
-    ZXIC_UINT32 ted;
-    ZXIC_UINT32 tcd;
-    ZXIC_UINT32 tei;
-    ZXIC_UINT32 tci;
-}DPP_STAT_CAR_A_QUEUE_CFG_T;
-
-#endif
-
-#if ZXIC_REAL("macro function define")
-
-#endif
-
-
-#if ZXIC_REAL("function declaration")
-/***********************************************************/
-/** stat公共配置初始化
-* @param   dev_id   
-* @param   p_dpp_stat_comm_cfg   
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/07/14
-************************************************************/
-DPP_STATUS dpp_stat_comm_init(ZXIC_UINT32 dev_id, DPP_STAT_COMM_CFG_T * p_dpp_stat_comm_cfg);
-
-/***********************************************************/
-/** 设置ppu统计 ERAM基地址
-* @param   dev_id           设备号 
-* @param   ppu_eram_baddr   ppu统计eRam基地址,128bit为单位
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/03/31
-************************************************************/
-DPP_STATUS dpp_stat_ppu_eram_baddr_set(DPP_DEV_T *dev, ZXIC_UINT32 ppu_eram_baddr);
-
-/***********************************************************/
-/** 设置ppu统计片内深度
-* @param   dev_id           设备号
-* @param   ppu_eram_depth   ppu统计片内深度
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/03/31
-************************************************************/
-DPP_STATUS dpp_stat_ppu_eram_depth_set(DPP_DEV_T *dev, ZXIC_UINT32 ppu_eram_depth);
-
-/***********************************************************/
-/** 设置ppu统计 DDR基地址
-* @param   dev_id          设备号 
-* @param   ppu_ddr_baddr   ppu统计DDR基地址
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/03/31
-************************************************************/
-DPP_STATUS dpp_stat_ppu_ddr_baddr_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ppu_ddr_baddr);
-
-/***********************************************************/
-/** TM配置初始化
-* @param   dev_id   
-* @param   p_stat_tm_cfg   
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/08/03
-************************************************************/
-DPP_STATUS dpp_stat_tm_init(ZXIC_UINT32 dev_id, DPP_STAT_TM_CFG_T *p_stat_tm_cfg);
-
-/***********************************************************/
-/** 配置Etm 统计类型
-* @param   dev_id               设备号
-* @param   etm_port0_type       统计类型0
-* @param   etm_port1_type       统计类型1
-* @param   etm_port2_type       统计类型2
-* @param   etm_port3_type       统计类型3
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/03/31
-************************************************************/
-DPP_STATUS dpp_stat_etm_port_type_set(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 etm_port0_type,
-                                      ZXIC_UINT32 etm_port1_type,
-                                      ZXIC_UINT32 etm_port2_type,
-                                      ZXIC_UINT32 etm_port3_type);
-
-/***********************************************************/
-/** 配置Ftm 统计类型
-* @param   dev_id               设备号
-* @param   ftm_port0_type       统计类型0
-* @param   ftm_port1_type       统计类型1
-* @param   ftm_port2_type       统计类型2
-* @param   ftm_port3_type       统计类型3
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/03/31
-************************************************************/
-DPP_STATUS dpp_stat_ftm_port_type_set(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 ftm_port0_type,
-                                      ZXIC_UINT32 ftm_port1_type,
-                                      ZXIC_UINT32 ftm_port2_type,
-                                      ZXIC_UINT32 ftm_port3_type);
-
-
-
-/***********************************************************/
-/** car硬件初始化
-* @param   dev_id        设备号
-* @param   car_type      car编号
-* @param   car_type      car模式，参见STAT_CAR_TYPE_E
-* @param   car_mono_mode car独占mono模式
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/04/27
-************************************************************/
-DPP_STATUS dpp_stat_car_hardware_init(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 car_type,
-                                      ZXIC_UINT32 car_mono_mode);
-
-/***********************************************************/
-/** 配置car的层级模式
-* @param   dev_id      
-* @param   mode   2 - 三级car, 第一级支持16K
-*                 1 - 两级car, 第一级扩展为17K
-*                 0 - 一级car, 第一级扩展为21K
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/09/28
-************************************************************/
-DPP_STATUS dpp_stat_car_en_mode_set(DPP_DEV_T *dev, ZXIC_UINT32 mode);
-
-/***********************************************************/
-/** car A 字节限速监管模板设定
-* @param   dev_id               设备               car号
-* @param   profile_id           监管模板号
-* @param   p_cara_profile_cfg   监管模板配置
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_cara_profile_cfg_set(DPP_DEV_T *dev,
-                                         ZXIC_UINT32 profile_id,
-                                         DPP_STAT_CAR_PROFILE_CFG_T* p_cara_profile_cfg);
-
-/***********************************************************/
-/** 获取car A的流设置
-* @param   dev_id               设备               car编号
-* @param   flow_id              流号
-* @param   p_cara_queue_cfg     car A流配置信息
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_cara_queue_cfg_get(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 flow_id,
-                                       DPP_STAT_CAR_A_QUEUE_CFG_T* p_cara_queue_cfg);
-
-/***********************************************************/
-/** car A的流设置
-* @param   dev_id           设备           car编号
-* @param   flow_id          流号
-* @param   drop_flag        丢弃标志
-* @param   plcr_en          监管使能
-* @param   profile_id       监管模板号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_cara_queue_cfg_set(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 flow_id,
-                                       ZXIC_UINT32 drop_flag,
-                                       ZXIC_UINT32 plcr_en,
-                                       ZXIC_UINT32 profile_id);
-
-/***********************************************************/
-/** stat模块常用函数列表
-* @param   dev_id   
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see     
-* @author  刘硕10181552      @date  2016/02/03
-************************************************************/
-DPP_STATUS dpp_stat_help(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** stat 模块上电初始化
-* @param   dev_id   
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2017/07/20
-************************************************************/
-DPP_STATUS dpp_stat_module_init(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** ppu stat读统计结果配置
-* @param   dev_id           设备号
-* @param   rd_mode          读取位宽模式，参见STAT_CNT_MODE_E，0-64bit，1-128bit
-* @param   index            索引，具体位宽参见rd_mode
-* @param   p_data           出参，读取的数据
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  xhj      @date  2018/02/01
-************************************************************/
-DPP_STATUS dpp_stat_ppu_cnt_set(ZXIC_UINT32 dev_id,
-                                STAT_CNT_MODE_E rd_mode,
-                                ZXIC_UINT32 index,
-                                ZXIC_UINT32 *p_data);
-
-/***********************************************************/
-/** ppu计数值获取
-* @param   dev_id           设备号
-* @param   rd_mode          读取位宽模式，参见STAT_CNT_MODE_E，0-64bit，1-128bit
-* @param   index            索引，具体位宽参见rd_mode
-* @param   clr_mode         读清模式，参见STAT_RD_CLR_MODE_E，0-不读清，1-读清
-* @param   p_data           出参，读取的数据
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/07/11
-************************************************************/
-DPP_STATUS dpp_stat_ppu_cnt_get(DPP_DEV_T *dev,
-                                STAT_CNT_MODE_E rd_mode,
-                                ZXIC_UINT32 index,
-                                ZXIC_UINT32 clr_mode,
-                                ZXIC_UINT32 *p_data);
-
-/***********************************************************/
-/** TM计数值获取
-* @param   dev_id               设备号 
-* @param   tm_mode              tm模式，0-ftm，1-etm 参见STAT_TM_MODE_E
-* @param   only_pkt_num_en      全包模式使能
-* @param   port_mode            端口位置模式，参见STAT_TM_PORT_MODE_E
-* @param   cnt_mode             计数模式，0-片内计数，1-混合计数
-* @param   clr_mode             读清模式，0-非读清，1-读清
-* @param   index                索引值
-* @param   p_data               数据
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/07/19
-************************************************************/
-DPP_STATUS dpp_stat_tm_cnt_get(ZXIC_UINT32 dev_id,
-                               ZXIC_UINT32 tm_mode,
-                               ZXIC_UINT32 only_pkt_num_en,
-                               ZXIC_UINT32 port_mode,
-                               ZXIC_UINT32 cnt_mode,
-                               ZXIC_UINT32 clr_mode,
-                               ZXIC_UINT32 index,
-                               ZXIC_UINT32 *p_data);
-
-/***********************************************************/
-/** CMMU配置信息、ppu stat 统计计数配置打印
-* @param    dev_id
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark   无
-* @see
-* @author   刘硕10181552      @date  2016/01/20
-************************************************************/
-DPP_STATUS diag_dpp_stat_ppu_cfg_prt(ZXIC_UINT32 dev_id);
-
-#endif
-#endif /*dpp_stat_api.h*/
-
-
-
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_stat_api.h
+* 文件标识 : stat计数模块对外数据类型定义和接口函数声明
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : xjw
+* 完成日期 : 2015/02/09
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#ifndef _DPP_STAT_API_H_
+#define _DPP_STAT_API_H_
+
+#if ZXIC_REAL("header file")
+
+#include "dpp_dev.h"
+
+#endif
+
+#if ZXIC_REAL("data struct define")
+/**  STAT模块TM模式*/
+typedef enum stat_tm_mode_e {
+	STAT_TM_MODE_ETM = 0, /**< @brief 上行TM */
+	STAT_TM_MODE_FTM = 1, /**< @brief 下行TM */
+	STAT_TM_MODE_MAX
+} STAT_TM_MODE_E;
+
+/** TM统计端口选择 */
+typedef enum stat_tm_port_mode_e {
+	STAT_TM_PORT_MODE_0_1 = 0, /**< @brief 端口0~1 */
+	STAT_TM_PORT_MODE_2_3 = 1, /**< @brief 端口2~3 */
+	STAT_TM_PORT_MODE_MAX,
+} STAT_TM_PORT_MODE_E;
+
+/**TM统计计数模式选择  */
+typedef enum stat_tm_cnt_mode_e {
+	STAT_TM_CNT_MODE_MIX = 0, /**< @brief 混合模式 */
+	STAT_TM_CNT_MODE_INNER = 1, /**< @brief 内部模式 */
+	STAT_TM_CNT_MODE_MAX
+} STAT_TM_CNT_MODE_E;
+
+/* TM计数器类型，共支持20种  */
+typedef enum tm_stat_type_e {
+
+	TM_STAT_ENQUE_PKT = 0, /**<  @brief 入队包计数*/
+	TM_STAT_ENQUE_VALID_PKT = 1, /**<  @brief 入队VALID包计数*/
+	TM_STAT_ENQUE_DROP_PKT = 2, /**<  @brief 入队丢弃包计数*/
+	TM_STAT_ENQUE_TD_PKT = 3, /**<  @brief 入队TD包计数*/
+	TM_STAT_ENQUE_WRED_PKT = 4, /**<  @brief 入队WRED包计数*/
+	TM_STAT_ENQUE_DP0_PKT = 5, /**<  @brief 入队DP0包计数*/
+	TM_STAT_ENQUE_DP1_PKT = 6, /**<  @brief 入队DP1包计数*/
+	TM_STAT_ENQUE_DP2_PKT = 7, /**<  @brief 入队DP2包计数*/
+	TM_STAT_ENQUE_DP3_PKT = 8, /**<  @brief 入队DP3包计数*/
+	TM_STAT_ENQUE_DP4_PKT = 9, /**<  @brief 入队DP4包计数*/
+	TM_STAT_ENQUE_DP5_PKT = 10, /**<  @brief 入队DP5包计数*/
+	TM_STAT_ENQUE_DP6_PKT = 11, /**<  @brief 入队DP6包计数*/
+	TM_STAT_ENQUE_DP7_PKT = 12, /**<  @brief 入队DP7包计数*/
+	TM_STAT_ENQUE_BLOCK_PKT = 13, /**<  @brief 入队BLOCK包计数*/
+	TM_STAT_ENQUE_DISABLE_PKT = 14, /**<  @brief 入队DISABLE包计数*/
+	TM_STAT_DEQUE_PKT = 15, /**<  @brief 出队包计数*/
+	TM_STAT_DEQUE_VALID_PKT = 16, /**<  @brief 出队VALID包计数*/
+	TM_STAT_DEQUE_DISCARD_PKT = 17, /**<  @brief 出队DISCARD包计数*/
+	TM_STAT_DEQUE_CLEAR_PKT = 18, /**<  @brief 出队CLEAR包计数*/
+	TM_STAT_DEQUE_AGE_PKT = 19, /**<  @brief 出队AGE包计数*/
+	TM_STAT_TYPE_UNEN = 20, /**<  @brief 不使能的时候，需配置成这个*/
+	TM_STAT_TYPE_MAX
+} TM_STAT_TYPE_E;
+
+/** car的监管类型 */
+typedef enum stat_car_type_e {
+	STAT_CAR_A_TYPE = 0, /**<  @brief A级CAR*/
+	STAT_CAR_B_TYPE, /**<  @brief B级CAR*/
+	STAT_CAR_C_TYPE, /**<  @brief C级CAR*/
+	STAT_CAR_MAX_TYPE
+} STAT_CAR_TYPE_E;
+
+/** car监管队列配置*/
+typedef struct stat_car_queue_cfg_t {
+	ZXIC_UINT32 queue_id; /**<  @brief 队列号*/
+	ZXIC_UINT32 plcr_en; /**<  @brief CAR使能*/
+	ZXIC_UINT32 drop_flag; /**<  @brief 丢弃标记*/
+	ZXIC_VOID *profile_cfg; /**< @brief carA的包模式时，结构体类型是DPP_STAT_CAR_PKT_PROFILE_CFG_T，其余模式组合时，结构体类型DPP_STAT_CAR_PROFILE_CFG_T*/
+} STAT_CAR_QUEUE_CFG_T;
+
+/**  stat模块计数模式设置*/
+typedef struct stat_count_cfg_t {
+	ZXIC_UINT32
+	rd_mode; /**< @brief 0:计数器在CPU读的下一拍自动清理,1:不自动清零*/
+	ZXIC_UINT32
+	overflow_mode; /**< @brief 0:计数器达到最大值后，一直保持最大值,1:计数器累积到最高1bit为1，最高1bit始终为1，而其余为继续计数*/
+} STAT_COUNT_CFG_T;
+
+/** stat 的smmu1属性 */
+typedef struct dpp_stat_smmu1_cfg_t {
+	ZXIC_UINT32 baddr; /**<  @brief 基地址*/
+} DPP_STAT_SMMU1_CFG_T;
+
+/** stat模块公共配置 */
+typedef struct dpp_stat_comm_cfg_t {
+	DPP_STAT_SMMU1_CFG_T
+	stat_smmu1_cfg[DPP_DEV_CHANNEL_MAX]; /**<  @brief stat 的smmu1属性*/
+	ZXIC_UINT32 is_init[DPP_DEV_CHANNEL_MAX]; /**<  @brief 初始化选择*/
+} DPP_STAT_COMM_CFG_T;
+
+/** stat模块tm统计配置 */
+typedef struct dpp_stat_tm_cfg_t {
+	ZXIC_UINT32 tm_en; /**<  @brief TM统计使能 */
+	ZXIC_UINT32 mov_en; /**<  @brief 搬移使能*/
+	ZXIC_UINT32 eram_en; /**<  @brief 片内计数使能*/
+	ZXIC_UINT32 ftm_pkt_en; /**<  @brief ftm包计数使能*/
+	ZXIC_UINT32 etm_pkt_en; /**<  @brief etm包计数使能*/
+	ZXIC_UINT32 ftm_port_type
+			[4]; /**<  @brief ftm包计数端口类型选择 参考 TM_STAT_TYPE_E */
+	ZXIC_UINT32 etm_port_type
+			[4]; /**<  @brief etm包计数端口类型选择 参考 TM_STAT_TYPE_E */
+	ZXIC_UINT32 etm_start_queue_id; /**<  @brief etm起始队列号*/
+	ZXIC_UINT32 etm_queue_depth_mode; /**<  @brief etm队列深度*/
+	DPP_STAT_SMMU1_CFG_T ftm_smmu1_cfg; /**<  @brief ftm统计的smmu1属性*/
+	DPP_STAT_SMMU1_CFG_T etm_smmu1_cfg; /**<  @brief etm统计的smmu1属性*/
+	ZXIC_UINT32 is_init[DPP_DEV_CHANNEL_MAX]; /**<  @brief 初始化选择*/
+} DPP_STAT_TM_CFG_T;
+
+/** TM 统计计数信息 */
+typedef struct dpp_stat_tm_cnt_t {
+	ZXIC_UINT32 tm_cnt_en; /**<  @brief tm计数使能*/
+	ZXIC_UINT32 tm_mode; /**<  @brief TM统计模式:0-ftm, 1-etm*/
+	ZXIC_UINT32 tm_flow_id; /**<  @brief TM统计流号*/
+	ZXIC_UINT32 tm_stat_type; /**<  @brief TM统计端口类型*/
+	ZXIC_UINT32 is_tm_byte_en; /**<  @brief TM统计字节计数使能*/
+	ZXIC_UINT32 is_eram_en; /**<  @brief TM统计片内计数使能*/
+	ZXIC_UINT64 tm_cnt; /**<  @brief TM计数结果*/
+} DPP_STAT_TM_CNT_T;
+
+/** STAT 中断状态  */
+typedef struct dpp_stat_brief_int_t {
+	ZXIC_UINT32 etcam_int; /**< @brief etcam模块中断 */
+	ZXIC_UINT32 stat_sch_int; /**< @brief stat sch剩余部分的中断状态 */
+} DPP_STAT_BRIEF_INT_T;
+
+/** STAT fifo中断状态选择  */
+typedef struct dpp_stat_sch_intr_t {
+	ZXIC_UINT32 hardware_rsv; /**< @brief 系统保留，用户无需关心*/
+	ZXIC_UINT32 oam0_ord_fifo_int; /**< @brief oam0保序模块中断*/
+	ZXIC_UINT32 oam2_ord_fifo_int; /**< @brief oam2保序模块中断*/
+	ZXIC_UINT32 oam3_ord_fifo_int; /**< @brief oam3保序模块中断*/
+	ZXIC_UINT32 ddr_sch_fifo_int; /**< @brief ddr调度中断*/
+	ZXIC_UINT32 plcr_sch_fifo_int; /**< @brief plcr调度中断*/
+	ZXIC_UINT32 stat_schd_fifo_int; /**< @brief stat模块key调度中断*/
+	ZXIC_UINT32 stat_rschd_fifo_int; /**< @brief stat模块rsp调度中断*/
+} DPP_STAT_SCH_INTR_T;
+
+/*stat 计数类型*/
+typedef enum stat_cnt_mode_e {
+	STAT_64_MODE = 0, /**<  @brief 64bit位宽模式*/
+	STAT_128_MODE = 1, /**<  @brief 128bit位宽模式*/
+	STAT_MAX_MODE,
+} STAT_CNT_MODE_E;
+
+/**DPP STAT读清模式选择  */
+typedef enum stat_rd_clr_mode_e {
+	STAT_RD_CLR_MODE_UNCLR = 0, /**<  @brief 不读请*/
+	STAT_RD_CLR_MODE_CLR = 1, /**<  @brief 读清*/
+	STAT_RD_CLR_MODE_MAX,
+} STAT_RD_CLR_MODE_E;
+
+/* car 优先级 */
+typedef enum dpp_car_priority_e {
+	DPP_CAR_PRI0 = 0, /**<  @brief CAR优先级0配置*/
+	DPP_CAR_PRI1 = 1, /**<  @brief CAR优先级1配置*/
+	DPP_CAR_PRI2 = 2, /**<  @brief CAR优先级2配置*/
+	DPP_CAR_PRI3 = 3, /**<  @brief CAR优先级3配置*/
+	DPP_CAR_PRI4 = 4, /**<  @brief CAR优先级4配置*/
+	DPP_CAR_PRI5 = 5, /**<  @brief CAR优先级5配置*/
+	DPP_CAR_PRI6 = 6, /**<  @brief CAR优先级6配置*/
+	DPP_CAR_PRI7 = 7, /**<  @brief CAR优先级7配置*/
+	DPP_CAR_PRI_MAX
+} DPP_CAR_PRIORITY_E;
+
+/** car 监管模板参数设置的参数 */
+typedef struct dpp_stat_car_profile_cfg_t {
+	ZXIC_UINT32 profile_id; /**<  @brief car模板号*/
+	ZXIC_UINT32 pkt_sign; /**<  @brief 包限速选择标志*/
+	ZXIC_UINT32
+	cd; /**<  @brief CD算法标志/令牌桶算法标志 0:srtcm 1:trtcm 2:MEF10.1*/
+	ZXIC_UINT32 cf; /**<  @brief CF溢出耦合标志，0:不溢出，1:溢出*/
+	ZXIC_UINT32 cm; /**<  @brief CM色盲/色敏标志，0:色盲模式，1:色敏模式 */
+	ZXIC_UINT32
+	cir; /**<  @brief C令牌桶添加速率(0~X, X Gbps/64kbps),最小值为64Kbps，步长为64Kbps*/
+	ZXIC_UINT32 cbs; /**<  @brief C桶桶深(XM),配置范围为0~XMByte-1，步长为1Byte*/
+	ZXIC_UINT32
+	eir; /**<  @brief E令牌桶添加速率(0~X, XGbps/64kbps),最小值为64Kbps，步长为64Kbps*/
+	ZXIC_UINT32 ebs; /**<  @brief E桶桶深(XM),配置范围为0~XMByte-1，步长为1Byte*/
+	ZXIC_UINT32 random_disc_e; /**<  @brief 仅carB、carC支持 */
+	ZXIC_UINT32 random_disc_c; /**<  @brief 仅carB、carC支持 */
+	ZXIC_UINT32 c_pri[DPP_CAR_PRI_MAX]; /**<  @brief 仅pri 1~7是有效值*/
+	ZXIC_UINT32 e_green_pri[DPP_CAR_PRI_MAX]; /**<  @brief 仅pri 1~7是有效值*/
+	ZXIC_UINT32 e_yellow_pri[DPP_CAR_PRI_MAX];
+} DPP_STAT_CAR_PROFILE_CFG_T;
+
+/* car 独占smmu0的模式 */
+typedef enum dpp_car_smmu0_mono_mode_e {
+	CAR_SMMU0_MONO_MODE_NONE = 0, /**<  @brief CAR不独占smmu0*/
+	CAR_SMMU0_MONO_MODE_1 = 1, /**<  @brief CAR独占1片smmu0*/
+	CAR_SMMU0_MONO_MODE_2 = 2, /**<  @brief CAR独占2片smmu0*/
+	CAR_SMMU0_MONO_MODE_MAX
+} DPP_CAR_SMMU0_MONO_MODE_E;
+
+/* TM统计的读清模式 */
+typedef enum stat_tm_clr_mode_e {
+	STAT_TM_CLR_MODE_UNCLR = 0, /**<  @brief  TM统计不读请*/
+	STAT_TM_CLR_MODE_CLR = 1, /**<  @brief  TM统计读请*/
+	STAT_TM_CLR_MODE_MAX,
+} STAT_TM_CLR_MODE_E;
+
+/** car A 队列设置的参数 */
+typedef struct dpp_stat_car_a_queue_cfg_t {
+	ZXIC_UINT32 flow_id;
+	ZXIC_UINT32 drop_flag;
+	ZXIC_UINT32 plcr_en;
+	ZXIC_UINT32 profile_id;
+	ZXIC_UINT64 tq;
+	ZXIC_UINT32 ted;
+	ZXIC_UINT32 tcd;
+	ZXIC_UINT32 tei;
+	ZXIC_UINT32 tci;
+} DPP_STAT_CAR_A_QUEUE_CFG_T;
+
+#endif
+
+#if ZXIC_REAL("macro function define")
+
+#endif
+
+#if ZXIC_REAL("function declaration")
+/***********************************************************/
+/** stat公共配置初始化
+ * @param   dev_id
+ * @param   p_dpp_stat_comm_cfg
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/07/14
+ ************************************************************/
+DPP_STATUS dpp_stat_comm_init(ZXIC_UINT32 dev_id,
+							  DPP_STAT_COMM_CFG_T * p_dpp_stat_comm_cfg);
+
+/***********************************************************/
+/** 设置ppu统计 ERAM基地址
+ * @param   dev_id           设备号
+ * @param   ppu_eram_baddr   ppu统计eRam基地址,128bit为单位
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/03/31
+ ************************************************************/
+DPP_STATUS dpp_stat_ppu_eram_baddr_set(DPP_DEV_T *dev,
+									   ZXIC_UINT32 ppu_eram_baddr);
+
+/***********************************************************/
+/** 设置ppu统计片内深度
+ * @param   dev_id           设备号
+ * @param   ppu_eram_depth   ppu统计片内深度
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/03/31
+ ************************************************************/
+DPP_STATUS dpp_stat_ppu_eram_depth_set(DPP_DEV_T *dev,
+									   ZXIC_UINT32 ppu_eram_depth);
+
+/***********************************************************/
+/** 设置ppu统计 DDR基地址
+ * @param   dev_id          设备号
+ * @param   ppu_ddr_baddr   ppu统计DDR基地址
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/03/31
+ ************************************************************/
+DPP_STATUS dpp_stat_ppu_ddr_baddr_set(ZXIC_UINT32 dev_id,
+									  ZXIC_UINT32 ppu_ddr_baddr);
+
+/***********************************************************/
+/** TM配置初始化
+ * @param   dev_id
+ * @param   p_stat_tm_cfg
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/08/03
+ ************************************************************/
+DPP_STATUS dpp_stat_tm_init(ZXIC_UINT32 dev_id,
+							DPP_STAT_TM_CFG_T *p_stat_tm_cfg);
+
+/***********************************************************/
+/** 配置Etm 统计类型
+ * @param   dev_id               设备号
+ * @param   etm_port0_type       统计类型0
+ * @param   etm_port1_type       统计类型1
+ * @param   etm_port2_type       统计类型2
+ * @param   etm_port3_type       统计类型3
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/03/31
+ ************************************************************/
+DPP_STATUS dpp_stat_etm_port_type_set(ZXIC_UINT32 dev_id,
+									  ZXIC_UINT32 etm_port0_type,
+									  ZXIC_UINT32 etm_port1_type,
+									  ZXIC_UINT32 etm_port2_type,
+									  ZXIC_UINT32 etm_port3_type);
+
+/***********************************************************/
+/** 配置Ftm 统计类型
+ * @param   dev_id               设备号
+ * @param   ftm_port0_type       统计类型0
+ * @param   ftm_port1_type       统计类型1
+ * @param   ftm_port2_type       统计类型2
+ * @param   ftm_port3_type       统计类型3
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/03/31
+ ************************************************************/
+DPP_STATUS dpp_stat_ftm_port_type_set(ZXIC_UINT32 dev_id,
+									  ZXIC_UINT32 ftm_port0_type,
+									  ZXIC_UINT32 ftm_port1_type,
+									  ZXIC_UINT32 ftm_port2_type,
+									  ZXIC_UINT32 ftm_port3_type);
+
+/***********************************************************/
+/** car硬件初始化
+ * @param   dev_id        设备号
+ * @param   car_type      car编号
+ * @param   car_type      car模式，参见STAT_CAR_TYPE_E
+ * @param   car_mono_mode car独占mono模式
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/27
+ ************************************************************/
+DPP_STATUS dpp_stat_car_hardware_init(ZXIC_UINT32 dev_id, ZXIC_UINT32 car_type,
+									  ZXIC_UINT32 car_mono_mode);
+
+/***********************************************************/
+/** 配置car的层级模式
+ * @param   dev_id
+ * @param   mode   2 - 三级car, 第一级支持16K
+ *                 1 - 两级car, 第一级扩展为17K
+ *                 0 - 一级car, 第一级扩展为21K
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/09/28
+ ************************************************************/
+DPP_STATUS dpp_stat_car_en_mode_set(DPP_DEV_T *dev, ZXIC_UINT32 mode);
+
+/***********************************************************/
+/** car A 字节限速监管模板设定
+ * @param   dev_id               设备               car号
+ * @param   profile_id           监管模板号
+ * @param   p_cara_profile_cfg   监管模板配置
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS
+dpp_stat_cara_profile_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+							  DPP_STAT_CAR_PROFILE_CFG_T *p_cara_profile_cfg);
+
+/***********************************************************/
+/** 获取car A的流设置
+ * @param   dev_id               设备               car编号
+ * @param   flow_id              流号
+ * @param   p_cara_queue_cfg     car A流配置信息
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS
+dpp_stat_cara_queue_cfg_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+							DPP_STAT_CAR_A_QUEUE_CFG_T *p_cara_queue_cfg);
+
+/***********************************************************/
+/** car A的流设置
+ * @param   dev_id           设备           car编号
+ * @param   flow_id          流号
+ * @param   drop_flag        丢弃标志
+ * @param   plcr_en          监管使能
+ * @param   profile_id       监管模板号
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS dpp_stat_cara_queue_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									   ZXIC_UINT32 drop_flag,
+									   ZXIC_UINT32 plcr_en,
+									   ZXIC_UINT32 profile_id);
+
+/***********************************************************/
+/** stat模块常用函数列表
+ * @param   dev_id
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  刘硕10181552      @date  2016/02/03
+ ************************************************************/
+DPP_STATUS dpp_stat_help(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** stat 模块上电初始化
+ * @param   dev_id
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2017/07/20
+ ************************************************************/
+DPP_STATUS dpp_stat_module_init(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** ppu stat读统计结果配置
+ * @param   dev_id           设备号
+ * @param   rd_mode          读取位宽模式，参见STAT_CNT_MODE_E，0-64bit，1-128bit
+ * @param   index            索引，具体位宽参见rd_mode
+ * @param   p_data           出参，读取的数据
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xhj      @date  2018/02/01
+ ************************************************************/
+DPP_STATUS dpp_stat_ppu_cnt_set(ZXIC_UINT32 dev_id, STAT_CNT_MODE_E rd_mode,
+								ZXIC_UINT32 index, ZXIC_UINT32 *p_data);
+
+/***********************************************************/
+/** ppu计数值获取
+ * @param   dev_id           设备号
+ * @param   rd_mode          读取位宽模式，参见STAT_CNT_MODE_E，0-64bit，1-128bit
+ * @param   index            索引，具体位宽参见rd_mode
+ * @param   clr_mode         读清模式，参见STAT_RD_CLR_MODE_E，0-不读清，1-读清
+ * @param   p_data           出参，读取的数据
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/07/11
+ ************************************************************/
+DPP_STATUS dpp_stat_ppu_cnt_get(DPP_DEV_T *dev, STAT_CNT_MODE_E rd_mode,
+								ZXIC_UINT32 index, ZXIC_UINT32 clr_mode,
+								ZXIC_UINT32 *p_data);
+
+/***********************************************************/
+/** TM计数值获取
+ * @param   dev_id               设备号
+ * @param   tm_mode              tm模式，0-ftm，1-etm 参见STAT_TM_MODE_E
+ * @param   only_pkt_num_en      全包模式使能
+ * @param   port_mode            端口位置模式，参见STAT_TM_PORT_MODE_E
+ * @param   cnt_mode             计数模式，0-片内计数，1-混合计数
+ * @param   clr_mode             读清模式，0-非读清，1-读清
+ * @param   index                索引值
+ * @param   p_data               数据
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/07/19
+ ************************************************************/
+DPP_STATUS dpp_stat_tm_cnt_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 tm_mode,
+							   ZXIC_UINT32 only_pkt_num_en,
+							   ZXIC_UINT32 port_mode, ZXIC_UINT32 cnt_mode,
+							   ZXIC_UINT32 clr_mode, ZXIC_UINT32 index,
+							   ZXIC_UINT32 *p_data);
+
+/***********************************************************/
+/** CMMU配置信息、ppu stat 统计计数配置打印
+ * @param    dev_id
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark   无
+ * @see
+ * @author   刘硕10181552      @date  2016/01/20
+ ************************************************************/
+DPP_STATUS diag_dpp_stat_ppu_cfg_prt(ZXIC_UINT32 dev_id);
+
+#endif
+#endif /*dpp_stat_api.h*/
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_tm_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_tm_api.h
old mode 100755
new mode 100644
index 9da623f0b2cdc9968461e5059f3b20e9f0042ae4..d277cbe5d54add38bf5a7495cb6c41cac362c2c4
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_tm_api.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_tm_api.h
@@ -1,1209 +1,1130 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_tm_api.h
-* 文件标识 : tm模块对外数据类型定义和接口函数声明
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : djf
-* 完成日期 : 2015/02/04
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-#ifndef  _DPP_TM_API_H_
-#define  _DPP_TM_API_H_
-
-
-#if ZXIC_REAL("header file")
-#include "dpp_module.h"
-#endif
-
-#if ZXIC_REAL("macro")
-#define DPP_TM_SA_NUM   (128)
-#define DPP_TM_PP_NUM   (64)/**< @brief TM内部逻辑端口数 */
-#define DPP_ETM_Q_NUM   (9216)/**< @ETM qmu支持9K物理队列 */
-#define DPP_FTM_Q_NUM   (2048)/**< @FTM qmu支持2k队列 */
-#define DPP_ETM_CRDT_NUM     (0x47FF)  /*etm 支持的crdt流队列逻辑编号cir+eir=18K */
-#define DPP_FTM_CRDT_NUM     (0xFFF)   /*ftm 支持的crdt流队列逻辑编号cir+eir=4K */
-#define DPP_ETM_MID_SE_NUM   (6144)/**< @ETM中间级共享0x17FF调度单元 */
-#define DPP_FTM_MID_SE_NUM   (512)/**< @FTM 中间级共享0x1FF调度单元 */
-#define DPP_ETM_MID_WFQFQ_NUM   (8 * 6144)/**< @brief 中间级共享8 * 6144调度器 */
-#define DPP_FTM_MID_WFQFQ_NUM   (8 * 512)/**< @brief 中间级共享8 * 512调度器 */
-
-
-#define DPP_ETM_WFQSP_OFFSET    (0x4000)  /*etm sp-wfq调度器相对于fq调度器编号偏移*/
-#define DPP_ETM_FQ_NUM          (16*1024) /*etm fq调度器个数*/
-#define DPP_ETM_WFQSP_NUM       (9*1024)  /*etm sp8和wfq调度器个数*/
-#define DPP_ETM_FQSPWFQ_NUM     (25*1024) /*etm fq-sp-wfq调度器总个数*/
-#define DPP_FTM_WFQSP_NUM       (1920+64)    /*ftm sp8和wfq调度器个数+64个端口*/
-#define DPP_ETM_SCH_DEL_NUM     (0xABFF)  /*etm-crdt要删除的流和调度器编号*/
-#define DPP_FTM_SCH_DEL_NUM     (0x177F)  /*ftm-crdt要删除的流和调度器编号*/
-
-#define DPP_TM_INVALID_PORT     (0xFFFF)  /* 定义crdt无效端口号,用于判定crdt挂接状态 */
-#define DPP_FTM_DELETED_LINK_ID (0x7FF)   /**定义ftm已被删除的link_id**/
-#define DPP_ETM_DELETED_LINK_ID (0x7FFF)  /**定义etm已被删除的link_id**/
-
-
-
-/* ftm/etm调度器往端口级挂接link_id偏移 */
-#define DPP_FTM_PORT_LINKID_BASE   (0x780)
-#define DPP_ETM_PORT_LINKID_BASE   (0x7F80)
-/**SHAP模块se_id编号基址(非从0开始)**/
-#define DPP_FTM_SHAP_SEID_BASE   (0x1000)
-#define DPP_ETM_SHAP_SEID_BASE   (0x4800)
-
-
-
-/**< @brief TD */
-#define DPP_TM_Q_TD_TH_MAX   (8192)/**< @brief Kbyte */
-#define DPP_TM_PP_TD_TH_MAX   (8192)/**< @brief Kbyte */
-#define DPP_TM_SYS_TD_TH_MAX   (8192)/**< @brief Kbyte */
-
-#define DPP_TM_Q_AVG_Q_LEN_MAX   (8192)/**< @brief Kbyte */
-#define DPP_TM_PP_AVG_Q_LEN_MAX   (8192)/**< @brief Kbyte */
-#define DPP_TM_SYS_AVG_Q_LEN_MAX   (8192)/**< @brief Kbyte */
-
-/**< @brief WRED */
-#define DPP_TM_Q_WRED_NUM   (32)/**< @brief 队列级WRED组数 */
-#define DPP_TM_Q_WRED_TH_MAX   (8192)/**< @brief Kbyte */
-#define DPP_TM_Q_WRED_MAX_TH_MAX   (8192)/**< @brief Kbyte */
-#define DPP_TM_Q_WRED_MIN_TH_MAX   (8192)/**< @brief Kbyte */
-#define DPP_TM_Q_WRED_MAX_CFG_PARA   (0xffffffff)
-
-#define DPP_TM_PP_WRED_NUM   (8)/**< @brief 端口级WRED组数 */
-#define DPP_TM_PP_WRED_TH_MAX   (8192)/**< @brief Kbyte */
-#define DPP_TM_PP_WRED_MAX_TH_MAX   (8192)/**< @brief Kbyte */
-#define DPP_TM_PP_WRED_MIN_TH_MAX   (8192)/**< @brief Kbyte */
-#define DPP_TM_PP_WRED_MAX_CFG_PARA   (0xffffffff)
-
-/**< @brief GRED */
-#define DPP_TM_SYS_GRED_TH_MAX   (8192)/**< @brief Kbyte */
-#define DPP_TM_SYS_GRED_MAX_TH_MAX   (8192)/**< @brief Kbyte */
-#define DPP_TM_SYS_GRED_MIN_TH_MAX   (8192)/**< @brief Kbyte */
-#define DPP_TM_SYS_GRED_MID_TH_MAX   (8192)/**< @brief Kbyte */
-
-#define DPP_TM_DP_NUM   (8)/**< @brief DP曲线数 */
-#define DPP_TM_RED_P_MIN   (1)
-#define DPP_TM_RED_P_MAX   (100)
-#define DPP_TM_CGAVD_WEIGHT_MAX   (15)
-#define DPP_TM_CGAVD_MOVE_PROFILE_NUM   (16)
-
-
-#define DPP_TM_SCH_WEIGHT_INVALID   (0) /**< @brief WFQ权重，FQ时weight是无效的 */
-#define DPP_TM_SCH_WEIGHT_MIN   (1)
-#define DPP_TM_SCH_WEIGHT_MAX   (511)
-#define DPP_TM_SCH_SP_NUM   (8)
-
-#define DPP_ETM_MID_SHAPE_PROFILE_NUM   (512)/**< ETM中间级整形策略数 */
-#define DPP_FTM_MID_SHAPE_PROFILE_NUM   (64)/**< FTM中间级整形策略数 */
-#define DPP_ETM_FLOW_SHAPE_PROFILE_NUM   (512)/**< ETM 流级整形策略数 */
-#define DPP_FTM_FLOW_SHAPE_PROFILE_NUM   (128)/**< FTM 流级整形策略数 */
-
-#define DPP_TM_SHAPE_CIR_MIN   (0)                  /**< @brief kbps */
-#define DPP_TM_SHAPE_CIR_MAX   (800 * 1000 * 1000)   /**< @brief kbps:用户可配最大整形 */
-#define DPP_TM_SHAPE_CBS_MIN   (0)                   /**< @brief kbyte */
-#define DPP_TM_SHAPE_CBS_MAX   (128 * 1024)             /**< @brief kbyte:用户可配最大桶深 128M */
-
-
-/**< CBS写入寄存器最大值为0x7FF */
-#define DPP_TM_SHAPE_CBS_REG_MIN   (0)                   /**< @brief kbyte */
-#define DPP_TM_SHAPE_CBS_REG_MAX   (0x7FF)                /**< @brief kbyte */
-
-#define DPP_TM_SYS_HZ   (1000*1000*1000)  /* 系统主频1000MHz */
-
-#define DPP_TM_TC_NUM (8)
-
-#endif
-
-
-#if ZXIC_REAL("data struct define")
-/**< @brief 内置TM工作模式 */
-typedef enum dpp_tm_work_mode_e
-{
-    DPP_TM_WORK_MODE_TM = 0,
-    DPP_TM_WORK_MODE_SA,
-    DPP_TM_WORK_MODE_INVALID
-} DPP_TM_WORK_MODE_E;
-
-/**< @brief QMU工作模式 */
-typedef enum dpp_tm_qmu_work_mode_e
-{
-    DPP_TM_QMU_WORK_MODE_2M = 0, /**< @brief 2M节点工作模式 */
-    DPP_TM_QMU_WORK_MODE_4M, /**< @brief 4M节点工作模式 */
-    DPP_TM_QMU_WORK_MODE_INVALID
-} DPP_TM_QMU_WORK_MODE_E;
-
-/**< @brief QMU DDR随机模式 */
-typedef enum dpp_tm_qmu_ddr_random_mode_e
-{
-    DPP_TM_QMU_DDR_NOT_RANDOM = 0, /**< @brief DDR不随机模式 */
-    DPP_TM_QMU_DDR_RANDOM, /**< @brief DDR随机模式 */
-    DPP_TM_QMU_DDR_RANDOM_MODE_INVALID
-} DPP_TM_QMU_DDR_RANDOM_MODE_E;
-
-/**< @brief 计数模式寄存器 */
-typedef struct dpp_tm_cnt_mode_t
-{
-
-    ZXIC_UINT32 fc_count_mode; /**< @brief 计数流控模式 */
-    ZXIC_UINT32 count_rd_mode; /**< @brief 计数读模式 */
-    ZXIC_UINT32 count_overflow_mode; /**< @brief 计数溢出模式  */
-} DPP_TM_CNT_MODE_T;
-
-/**< @brief 中断信息 */
-typedef struct dpp_tm_int_t
-{
-
-    ZXIC_UINT32 shap_int;
-    ZXIC_UINT32 crdt_int;
-    ZXIC_UINT32 mmu_int;
-    ZXIC_UINT32 qmu_int;
-    ZXIC_UINT32 cgavd_int;
-    ZXIC_UINT32 olif_int;
-    ZXIC_UINT32 cfgmt_int;
-} DPP_TM_INT_T;
-
-
-/**< @brief 拥塞避免层次 */
-typedef enum dpp_tm_cgavd_level_e
-{
-    QUEUE_LEVEL = 0, /**< @brief 流队列级 */
-    PP_LEVEL,        /**< @brief 端口级 */
-    SYS_LEVEL,       /**< @brief 系统级 */
-    SA_LEVEL,        /**< @brief SA队列不可达拥塞避免 */
-    INVALID_LEVEL
-} DPP_TM_CGAVD_LEVEL_E;
-
-/**< @brief dp选取值 */
-typedef enum dpp_tm_cgavd_dp_sel_e
-{
-    DP_SEL_DP = 0, /**< @brief 选tm头中dp字段作为cgavd的dp */
-    DP_SEL_TC,        /**< @brief 选tm头中tc字段作为cgavd的dp */
-    DP_SEL_PKT_LEN,       /**< @brief 选tm头中pkt[2:0]字段作为cgavd的dp */
-    INVALID_DP
-} DPP_TM_CGAVD_DP_SEL_E;
-
-/**< @brief 拥塞避免模式 */
-typedef enum dpp_tm_cgavd_method_e
-{
-    TD_METHOD = 0, /**< @brief TD模式 */
-    WRED_GRED_METHOD, /**< @brief 流级和端口级为WRED模式，系统级为GRED模式 */
-    INVALID_METHOD
-} DPP_TM_CGAVD_METHOD_E;
-
-/**< @brief WRED DP曲线配置参数 */
-typedef struct dpp_tm_wred_dp_line_para_t
-{
-    ZXIC_UINT32 max_th; /**< @brief 平均队列深度上限阈值 */
-    ZXIC_UINT32 min_th; /**< @brief 平均队列深度下限阈值 */
-    ZXIC_UINT32 max_p; /**< @brief 最大丢弃概率 */
-    ZXIC_UINT32 weight; /**< @brief 平均队列深度计算权重 */
-    ZXIC_UINT32 q_len_th; /**< @brief 队列深度阈值 */
-} DPP_TM_WRED_DP_LINE_PARA_T;
-
-/**< @brief GRED DP曲线配置参数 */
-typedef struct dpp_tm_gred_dp_line_para_t
-{
-    ZXIC_UINT32 max_th; /**< @brief 第2段平均队列深度上限阈值 */
-    ZXIC_UINT32 mid_th; /**< @brief 第1段平均队列深度上限阈值 */
-    ZXIC_UINT32 min_th; /**< @brief 第1段平均队列深度下限阈值 */
-    ZXIC_UINT32 max_p; /**< @brief 最大丢弃概率 */
-    ZXIC_UINT32 weight; /**< @brief 平均队列深度计算权重 */
-    ZXIC_UINT32 q_len_th; /**< @brief 队列深度阈值 */
-} DPP_TM_GRED_DP_LINE_PARA_T;
-
-/**< @brief CRDT调度层次 */
-typedef enum dpp_tm_sch_level_e
-{
-    DPP_TM_SCH_LEVEL_Q = 1,
-    DPP_TM_SCH_LEVEL_VC = 2,
-    DPP_TM_SCH_LEVEL_VCG = 3,
-    DPP_TM_SCH_LEVEL_VP = 4,
-    DPP_TM_SCH_LEVEL_PP = 5,
-    DPP_TM_SCH_LEVEL_INVALID
-} DPP_TM_SCH_LEVEL_E;
-
-/**< @brief SP_ID */
-typedef enum dpp_tm_sch_sp_e
-{
-    DPP_TM_SCH_SP_0 = 0,
-    DPP_TM_SCH_SP_1 = 1,
-    DPP_TM_SCH_SP_2 = 2,
-    DPP_TM_SCH_SP_3 = 3,
-    DPP_TM_SCH_SP_4 = 4,
-    DPP_TM_SCH_SP_5 = 5,
-    DPP_TM_SCH_SP_6 = 6,
-    DPP_TM_SCH_SP_7 = 7,
-    DPP_TM_SCH_SP_8 = 8,
-    DPP_TM_SCH_SP_INVALID
-} DPP_TM_SCH_SP_E;
-
-/**< @brief 调度单元挂接参数 */
-typedef struct dpp_tm_sch_para_t
-{
-    ZXIC_UINT32 level_id;                    /**< @brief 当前为中间级时，vc:0 vcg:1 vp:2 para_get已加2供调用*/
-    DPP_TM_SCH_LEVEL_E se_last_level;   /**< @brief 挂接到的上级层次 */
-    ZXIC_UINT32 se_id;                       /**< @brief 挂接到的上级调度单元ID */
-    DPP_TM_SCH_SP_E c_sp_id;            /**< @brief C桶挂接到的SPID,SP0~SP7 */
-    DPP_TM_SCH_SP_E e_sp_id;            /**< @brief E桶挂接到的SPID,SP0~SP7 */
-    ZXIC_UINT32 sp_relay;                    /**< @brief 队列优先级传递标志,FLOW级时表示FLOW_WORK_MODE */
-    ZXIC_UINT32 c_sp_weight;                 /**< @brief C桶挂接到的调度器是WFQ的话，WFQ的权重 */
-    ZXIC_UINT32 e_sp_weight;                 /**< @brief E桶挂接到的调度器是WFQ的话，WFQ的权重 */
-} DPP_TM_SCH_PARA_T;
-
-/**< @brief 调度器参数 */
-typedef struct dpp_tm_wfqfq_t
-{
-    ZXIC_UINT32 wfqfq_id[8];     /**< @brief 本级调度单元下挂接的8个调度器ID，FQ/WFQ，由ID号区分 */
-} DPP_TM_WFQFQ_T;
-
-/**< @brief 流队列挂接参数 */
-typedef struct dpp_tm_sch_flow_para_t
-{
-    ZXIC_UINT32 c_linkid;            /**< @brief c桶要挂接到的上级调度器id */
-    ZXIC_UINT32 c_weight;            /**< @brief c桶挂接到上级调度器的权重[1~511] */
-    ZXIC_UINT32 c_sp;                /**< @brief c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 */
-    ZXIC_UINT32 mode;                /**< @brief 挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可 */
-    ZXIC_UINT32 e_linkid;            /**< @brief e桶要挂接到的上级调度器id */
-    ZXIC_UINT32 e_weight;            /**< @brief e桶挂接到上级调度器的权重[1~511] */
-    ZXIC_UINT32 e_sp;                /**< @brief e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低 */
-} DPP_TM_SCH_FLOW_PARA_T;
-
-/**< @brief 调度单元挂接参数:非优先级传递 */
-typedef struct dpp_tm_sch_se_para_t
-{
-    ZXIC_UINT32  se_linkid;             /**< @brief 要挂接到的上级调度器id */
-    ZXIC_UINT32  cp_token_en;           /**< @brief 调度器cp双桶使能开关，仅fq8/wfq8支持 */
-    ZXIC_UINT32  se_weight;             /**< @brief 挂接到上级调度器的权重[1~511] */
-    ZXIC_UINT32  se_sp;                  /**< @brief 挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 */
-} DPP_TM_SCH_SE_PARA_T;
-
-/**< @brief 调度单元挂接参数:优先级传递开启 */
-typedef struct dpp_tm_sch_se_para_insw_t
-{
-    ZXIC_UINT32  se_linkid;             /**< @brief  要挂接到的上级调度器id */
-    ZXIC_UINT32  cp_token_en;           /**< @brief 调度器cp双桶使能开关，仅fq8/wfq8支持 */
-    ZXIC_UINT32  se_sp;                  /**< @brief 挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 */
-    ZXIC_UINT32  se_weight[8];             /**< @brief WFQ8中各调度器权重值[1~511]，若是WFQ2/4 只取前面对应值，后面无效 */
-} DPP_TM_SCH_SE_PARA_INSW_T;
-
-typedef enum dpp_tm_sch_port_linkid_t
-{
-    DPP_TM_PP_LINKID_PORT0 = 0x7F80,
-    DPP_TM_PP_LINKID_PORT1 = 0x7F81,
-    DPP_TM_PP_LINKID_PORT2 = 0x7F82,
-    DPP_TM_PP_LINKID_PORT3 = 0x7F83,
-    DPP_TM_PP_LINKID_PORT4 = 0x7F84,
-    DPP_TM_PP_LINKID_PORT5 = 0x7F85,
-    DPP_TM_PP_LINKID_PORT6 = 0x7F86,
-    DPP_TM_PP_LINKID_PORT7 = 0x7F87,
-    DPP_TM_PP_LINKID_PORT8 = 0x7F88,
-    DPP_TM_PP_LINKID_PORT9 = 0x7F89,
-    DPP_TM_PP_LINKID_PORT10 = 0x7F8A,
-    DPP_TM_PP_LINKID_PORT11 = 0x7F8B,
-    DPP_TM_PP_LINKID_PORT12 = 0x7F8C,
-    DPP_TM_PP_LINKID_PORT13 = 0x7F8D,
-    DPP_TM_PP_LINKID_PORT14 = 0x7F8E,
-    DPP_TM_PP_LINKID_PORT15 = 0x7F8F,
-    DPP_TM_PP_LINKID_PORT16 = 0x7F90,
-    DPP_TM_PP_LINKID_PORT17 = 0x7F91,
-    DPP_TM_PP_LINKID_PORT18 = 0x7F92,
-    DPP_TM_PP_LINKID_PORT19 = 0x7F93,
-    DPP_TM_PP_LINKID_PORT20 = 0x7F94,
-    DPP_TM_PP_LINKID_PORT21 = 0x7F95,
-    DPP_TM_PP_LINKID_PORT22 = 0x7F96,
-    DPP_TM_PP_LINKID_PORT23 = 0x7F97,
-    DPP_TM_PP_LINKID_PORT24 = 0x7F98,
-    DPP_TM_PP_LINKID_PORT25 = 0x7F99,
-    DPP_TM_PP_LINKID_PORT26 = 0x7F9A,
-    DPP_TM_PP_LINKID_PORT27 = 0x7F9B,
-    DPP_TM_PP_LINKID_PORT28 = 0x7F9C,
-    DPP_TM_PP_LINKID_PORT29 = 0x7F9D,
-    DPP_TM_PP_LINKID_PORT30 = 0x7F9E,
-    DPP_TM_PP_LINKID_PORT31 = 0x7F9F,
-    DPP_TM_PP_LINKID_PORT32 = 0x7FA0,
-    DPP_TM_PP_LINKID_PORT33 = 0x7FA1,
-    DPP_TM_PP_LINKID_PORT34 = 0x7FA2,
-    DPP_TM_PP_LINKID_PORT35 = 0x7FA3,
-    DPP_TM_PP_LINKID_PORT36 = 0x7FA4,
-    DPP_TM_PP_LINKID_PORT37 = 0x7FA5,
-    DPP_TM_PP_LINKID_PORT38 = 0x7FA6,
-    DPP_TM_PP_LINKID_PORT39 = 0x7FA7,
-    DPP_TM_PP_LINKID_PORT40 = 0x7FA8,
-    DPP_TM_PP_LINKID_PORT41 = 0x7FA9,
-    DPP_TM_PP_LINKID_PORT42 = 0x7FAA,
-    DPP_TM_PP_LINKID_PORT43 = 0x7FAB,
-    DPP_TM_PP_LINKID_PORT44 = 0x7FAC,
-    DPP_TM_PP_LINKID_PORT45 = 0x7FAD,
-    DPP_TM_PP_LINKID_PORT46 = 0x7FAE,
-    DPP_TM_PP_LINKID_PORT47 = 0x7FAF,
-    DPP_TM_PP_LINKID_PORT48 = 0x7FB0,
-    DPP_TM_PP_LINKID_PORT49 = 0x7FB1,
-    DPP_TM_PP_LINKID_PORT50 = 0x7FB2,
-    DPP_TM_PP_LINKID_PORT51 = 0x7FB3,
-    DPP_TM_PP_LINKID_PORT52 = 0x7FB4,
-    DPP_TM_PP_LINKID_PORT53 = 0x7FB5,
-    DPP_TM_PP_LINKID_PORT54 = 0x7FB6,
-    DPP_TM_PP_LINKID_PORT55 = 0x7FB7,
-    DPP_TM_PP_LINKID_PORT56 = 0x7FB8,
-    DPP_TM_PP_LINKID_PORT57 = 0x7FB9,
-    DPP_TM_PP_LINKID_PORT58 = 0x7FBA,
-    DPP_TM_PP_LINKID_PORT59 = 0x7FBB,
-    DPP_TM_PP_LINKID_PORT60 = 0x7FBC,
-    DPP_TM_PP_LINKID_PORT61 = 0x7FBD,
-    DPP_TM_PP_LINKID_PORT62 = 0x7FBE,
-    DPP_TM_PP_LINKID_PORT63 = 0x7FBF,
-    DPP_TM_PP_LINKID_INVALID
-} DPP_TM_SCH_PORT_LINKID_T;
-typedef enum dpp_tm_shape_flag_e
-{
-    DPP_TM_SHAPE_FLAG_CIR = 0,
-    DPP_TM_SHAPE_FLAG_EIR = 1,
-    DPP_TM_SHAPE_FLAG_INVALID
-} DPP_TM_SHAPE_FLAG_E;
-
-/**< @brief 整形令牌桶模式 */
-typedef enum dpp_tm_shape_mode_e
-{
-    DPP_TM_SINGLE_MIX_BUCKET = 0,       /**< @brief 单桶/组合流 */
-    DPP_TM_DUAL_BUCKET = 1,       /**< @brief 双桶 */
-    DPP_TM_DUAL_PIPE = 2,      /**< @brief 被双桶 */
-    DPP_TM_SHAPE_MODE_INVALID
-} DPP_TM_SHAPE_MODE_E;
-
-/**< @brief 整形profile参数 */
-typedef struct dpp_tm_shape_profile_t
-{
-    ZXIC_UINT32 cir;
-    ZXIC_UINT32 cbs;
-    ZXIC_UINT32 eir;
-    ZXIC_UINT32 ebs;
-} DPP_TM_SHAPE_PROFILE_T;
-
-/**< @brief 端口级整形参数 */
-typedef struct dpp_tm_shape_pp_para_t
-{
-    ZXIC_UINT32 cir;
-    ZXIC_UINT32 cbs;
-    ZXIC_UINT32 c_en;
-} DPP_TM_SHAPE_PP_PARA_T;
-
-/**< @brief 调度单元整形参数 */
-typedef struct dpp_tm_shape_para_t
-{
-    ZXIC_UINT32 class_id;      /**< @brief 当前中间级所属层次，vc:1 vcg:2 vp:3 */
-    ZXIC_UINT32 profile_id;
-    ZXIC_UINT32 c_en;
-    ZXIC_UINT32 e_en;
-    DPP_TM_SHAPE_MODE_E mode;
-} DPP_TM_SHAPE_PARA_T;
-
-/**< @brief 整形参数 */
-typedef struct dpp_tm_shape_t
-{
-    ZXIC_UINT32 mid_level;      /**< @brief 当前中间级所属层次，vc:1 vcg:2 vp:3 */
-    ZXIC_UINT32 cir;
-    ZXIC_UINT32 cbs;
-    ZXIC_UINT32 eir;
-    ZXIC_UINT32 ebs;
-    ZXIC_UINT32 c_en;
-    ZXIC_UINT32 e_en;
-    ZXIC_UINT32 mode;
-} DPP_TM_SHAPE_T;
-
-typedef struct dpp_tm_shape_para
-{
-    ZXIC_UINT32 shape_cir;
-    ZXIC_UINT32 shape_cbs;
-    ZXIC_UINT32 shape_num;
-} DPP_TM_SHAPE_PARA_TABLE;
-
-
-/**< @brief TM初始化参数 */
-typedef struct dpp_tm_init_para_t
-{
-    DPP_TM_WORK_MODE_E tm_sa_mode;     /**< @brief TM或SA模式 */
-    DPP_TM_QMU_WORK_MODE_E qmu_mode;   /**< @brief QMU 2M或4M节点模式 */
-    ZXIC_UINT32 case_num;                   /**< @brief 四组QMU初始化场景编号为1-4;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8.*/
-    DPP_TM_QMU_DDR_RANDOM_MODE_E ddr_random_mode;   /**< @brief ddr随机模式 */
-    ZXIC_UINT32 block_size;                              /**< @brief block模式，128/256/512/1024 */
-    ZXIC_UINT32 local_sa_id;                             /**< @brief SA模式时，本地sa_id*/
-} DPP_TM_INIT_PARA_T;
-
-
-/* TM ASIC初始化信息配置 */
-typedef struct dpp_tm_asic_init_info_t
-{
-    ZXIC_UINT32 blk_size;       /**< @brief qmu配置的block大小 256B/512B[default]/1024B */
-    ZXIC_UINT32 case_num;       /**< @brief 四组QMU初始化场景编号为1-4;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8. */
-    ZXIC_UINT32 imem_omem;      /**< @brief 0:片内外混合; 1:纯片内;2:纯片外 */
-    ZXIC_UINT32 mode;           /**< @brief TM工作模式 0:TM模式; 1:SA模式 */
-} DPP_TM_ASIC_INIT_INFO_T;
-
-#endif
-
-#if ZXIC_REAL("function declaration")
-
-
-
-/***********************************************************/
-/** 读取block长度模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_size   block长度模式，256/512/1024
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_blk_size_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_size);
-
-
-/***********************************************************/
-/** 配置内置TM的工作模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   mode   配置的值，0-TM模式，1-SA模式
-*ETM仅工作在TM模式，FTM可以工作TM或SA模式
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_sa_work_mode_set(DPP_DEV_T *dev, DPP_TM_WORK_MODE_E mode);
-
-
-/***********************************************************/
-/**  配置各级搬移功能使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级
-* @param   en   使能标记，0-不使能，1-使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-#ifdef ETM_REAL
-DPP_STATUS dpp_tm_cgavd_move_en_set(ZXIC_UINT32 dev_id,
-                                    DPP_TM_CGAVD_LEVEL_E level,
-                                    ZXIC_UINT32 en);
-
-/***********************************************************/
-/** 配置各级搬移门限
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号，系统级时，id参数无效
-* @param   value   端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B；
-                   流级时为搬移profile_id,0~15
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_move_th_set(ZXIC_UINT32 dev_id,
-                                    DPP_TM_CGAVD_LEVEL_E level,
-                                    ZXIC_UINT32 id,
-                                    ZXIC_UINT32 value);
-
-/***********************************************************/
-/**  配置flow级的搬移策略
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   move_profile  flow级的搬移门限分组索引,0~15
-* @param   th  flow级的搬移门限，单位为KB；
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_flow_move_profile_set(ZXIC_UINT32 dev_id,
-                                              ZXIC_UINT32 move_profile,
-                                              ZXIC_UINT32 th);
-#endif
-
-/***********************************************************/
-/**  配置端口共享的搬移门限
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   th  端口共享的搬移门限，单位为NPPU存包的单位，256B；
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_port_share_th_set(ZXIC_UINT32 dev_id,
-                                           ZXIC_UINT32 th);
-
-/***********************************************************/
-/**  配置各级拥塞避免功能使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级
-* @param   en   使能标记，0-不使能，1-使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_en_set(DPP_DEV_T *dev,
-                               DPP_TM_CGAVD_LEVEL_E level,
-                               ZXIC_UINT32 en);
-
-/***********************************************************/
-/** 配置拥塞避免算法
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号，系统级时，id参数无效
-* @param   method  配置的拥塞避免算法，0:TD，1:WRED/GRED
-*          配置TD算法时，先配TD阈值，再配置TD算法
-*          配置WRED算法时,先配置流级或端口级的平均队列深度，再配置WRED算法
-*          配置GRED算法时，先配置系统级的平均队列深度，在配置成GRED算法
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark
-* @see
-* @author  taq      @date  2015/04/14
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_method_set(DPP_DEV_T *dev,
-                                   DPP_TM_CGAVD_LEVEL_E level,
-                                   ZXIC_UINT32 id,
-                                   DPP_TM_CGAVD_METHOD_E method);
-
-/***********************************************************/
-/** 配置TD拥塞避免模式下的丢弃门限值
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号，系统级时，id参数无效
-* @param   td_th   配置的丢弃门限值，用户配置门限值单位为Kbyte，需要转化为Block单位写入寄存器
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_td_th_set(DPP_DEV_T *dev,
-                                  DPP_TM_CGAVD_LEVEL_E level,
-                                  ZXIC_UINT32 id,
-                                  ZXIC_UINT32 td_th);
-
-/***********************************************************/
-/** 配置指定端口或队列绑定的WRED GROUP ID
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   id   队列号或端口号
-* @param   wred_id   配置的WRED GROUP ID
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_wred_id_set(ZXIC_UINT32 dev_id,
-                                    DPP_TM_CGAVD_LEVEL_E level,
-                                    ZXIC_UINT32 id,
-                                    ZXIC_UINT32 wred_id);
-
-/***********************************************************/
-/** 配置TM模式下流队列挂接的端口号；SA模式下流队列映射的目的芯片ID
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   q_id   队列号
-* @param   pp_id   配置的端口号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_q_map_pp_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 q_id,
-                                     ZXIC_UINT32 pp_id);
-
-/***********************************************************/
-/** 配置TM模式tc到flow的映射
-* @param   dev_id 设备编号
-* @param   tc_id   itmd tc优先级（0~7）
-* @param   flow_id 映射的flowid号 （0~4095）
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/07/04
-************************************************************/
-DPP_STATUS dpp_tm_tc_map_flow_set(DPP_DEV_T *dev,
-                                  ZXIC_UINT32 tc_id,
-                                  ZXIC_UINT32 flow_id);                                     
-
-/***********************************************************/
-/** 配置指定端口或队列是否支持动态门限机制
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   id   队列号或端口号
-* @param   en   配置的值，0-不支持动态门限机制，1-支持动态门限机制
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_dyn_th_en_set(DPP_DEV_T *dev,
-                                      DPP_TM_CGAVD_LEVEL_E level,
-                                      ZXIC_UINT32 id,
-                                      ZXIC_UINT32 en);
-
-/***********************************************************/
-/**  配置强制片内或片外
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en      1:使能
-* @param   mode   1 :omem 强制片外  0:imem 强制片内
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2017/10/14
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_imem_omem_set(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 en,
-                                      ZXIC_UINT32 mode);
-
-
-/***********************************************************/
-/** 读取QMU队列授权价值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_credit_value   授权价值，默认值是400Byte
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy     @date  2016/04/14
-************************************************************/
-DPP_STATUS dpp_tm_qmu_credit_value_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_credit_value);
-
-/******************************************************************************
-*包老化配置
-* @param: dev_id: 设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-*           aging_en: 包老化使能：1表示包老化功能使能；0表示包老化功能关闭。
-*           aging_interval: 普通老化两次的间隔配置
-*           aging_step_interval: 普通老化的老化时间的步进配置值
-*           aging_start_qnum: 老化起始队列
-*           aging_end_qnum: 老化结束队列
-*           aging_req_aful_th: 普通老化FIFO的将满阈值
-*           aging_pkt_num: 一次老化的包个数
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/05/10
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pkt_aging_set(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 aging_en,
-                                    ZXIC_UINT32 aging_interval,
-                                    ZXIC_UINT32 aging_step_interval,
-                                    ZXIC_UINT32 aging_start_qnum,
-                                    ZXIC_UINT32 aging_end_qnum,
-                                    ZXIC_UINT32 aging_pkt_num,
-                                    ZXIC_UINT32 aging_req_aful_th);
-
-/******************************************************************************
-*配置老化一个包的时间，一次老化一个包，老化队列范围为可配
-* @param: dev_id: 设备索引编号
-* @param    tm_type   0: etm; 1: ftm;
-*           aging_en: 包老化使能：1表示包老化功能使能；0表示包老化功能关闭。
-*           aging_time: 老化一个包的时间，单位ms
-            aging_que_start:老化起始队列
-            aging_que_start:老化终止队列
-老化时间=2*aging_interval*step_interval*q_num
-aging_interval = (aging_time * 600000) / (2 * 1 * DPP_TM_Q_NUM);
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb     @date  2020/12/08
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pkt_age_time_set(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 aging_en,
-                                       ZXIC_UINT32 aging_time,
-                                       ZXIC_UINT32 aging_que_start,
-                                       ZXIC_UINT32 aging_que_end);
-
-
-/***********************************************************/
-/** 分配etm调度器资源：fq/fq2/fq4/fq8 个数，(共16K= 16384)
-* @param   dev_id   设备编号
-* @param   fq_num   FQ调度器个数，须是8的倍数
-* @param   fq2_num  FQ2调度器个数，须是4的倍数
-* @param   fq4_num  FQ4调度器个数，须是2的倍数
-* @param   fq8_num  FQ8调度器个数
-*          调度器总数不能超过：16K= 16384
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/26
-************************************************************/
-DPP_STATUS dpp_etm_crdt_fq_set(DPP_DEV_T *dev,
-                               ZXIC_UINT32 fq_num,
-                               ZXIC_UINT32 fq2_num,
-                               ZXIC_UINT32 fq4_num,
-                               ZXIC_UINT32 fq8_num);
-
-/***********************************************************/
-/** 分配TM调度器资源：sp/wfq/wfq2/wfq4/wfq8 个数，（etm共9K=9216,ftm共1920个）
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sp_num   SP调度器个数，须是8的倍数
-* @param   wfq_num  WFQ调度器个数，须是8的倍数
-* @param   wfq2_num  WFQ2调度器个数，须是4的倍数
-* @param   wfq4_num  WFQ4调度器个数，须是2的倍数
-* @param   wfq8_num  WFQ8调度器个数
-*          调度器总数不能超过：ETM= 9216; FTM= 1920
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/26
-************************************************************/
-DPP_STATUS dpp_tm_crdt_wfqsp_set(DPP_DEV_T *dev,
-                                 ZXIC_UINT32 sp_num,
-                                 ZXIC_UINT32 wfq_num,
-                                 ZXIC_UINT32 wfq2_num,
-                                 ZXIC_UINT32 wfq4_num,
-                                 ZXIC_UINT32 wfq8_num);
-
-/***********************************************************/
-/** 配置flow级流队列的挂接关系(flow到上级调度器的挂接)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id   流队列号
-* @param   c_linkid  c桶要挂接到的上级调度器id
-* @param   c_weight  c桶挂接到上级调度器的权重[1~511]
-* @param   c_sp      c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
-* @param   mode      挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可
-* @param   e_linkid  e桶要挂接到的上级调度器id
-* @param   e_weight  e桶挂接到上级调度器的权重[1~511]
-* @param   e_sp      e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_flow_link_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 flow_id,
-                                     ZXIC_UINT32 c_linkid,
-                                     ZXIC_UINT32 c_weight,
-                                     ZXIC_UINT32 c_sp,
-                                     ZXIC_UINT32 mode,
-                                     ZXIC_UINT32 e_linkid,
-                                     ZXIC_UINT32 e_weight,
-                                     ZXIC_UINT32 e_sp);
-
-/***********************************************************/
-/** 配置调度器层次化QOS的挂接关系:非优先级传递
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   se_id      本级调度器id
-* @param   se_linkid  要挂接到的上级调度器id
-* @param   se_weight  挂接到上级调度器的权重[1~511]
-* @param   se_sp      挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
-* @param   se_insw    优先级传递使能：0-关 1-开. 该参数不传递直接配0
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_link_set(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 se_id,
-                                   ZXIC_UINT32 se_linkid,
-                                   ZXIC_UINT32 se_weight,
-                                   ZXIC_UINT32 se_sp);
-
-/***********************************************************/
-/** 配置调度器层次化QOS的挂接关系:优先级传递
-* @param   dev_id       设备编号
-* @param   tm_type      0-ETM,1-FTM
-* @param   se_id        本级调度器id
-* @param   se_linkid    要挂接到的上级调度器id
-* @param   se_weight    WFQ2/4/8中各调度器权重值[1~511]，取相等的值
-* @param   se_sp        挂接到上级调度器的sp优先级,有效值[0-7],共8级，优先级依次降低
-* @param   se_insw      优先级传递使能：0-关 1-开. 该参数不传递直接配1
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_link_insw_set(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 se_id,
-                                        ZXIC_UINT32 se_linkid,
-                                        ZXIC_UINT32 se_weight,
-                                        ZXIC_UINT32 se_sp);
-
-/***********************************************************/
-/** 配置调度器层次化QOS的挂接关系:优先级传递,单个调度器挂接
-* @param   dev_id       设备编号
-* @param   tm_type      0-ETM,1-FTM
-* @param   se_id        本级调度器id
-* @param   se_linkid    要挂接到的上级调度器id
-* @param   se_weight    WFQ8中对应调度器权重值[1~511]
-* @param   se_sp        挂接到上级调度器的sp优先级,有效值[0-7],共8级，优先级依次降低
-* @param   se_insw      优先级传递使能：0-关 1-开. 该参数不传递直接配1
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_link_insw_single_set(DPP_DEV_T *dev,
-                                               ZXIC_UINT32 se_id,
-                                               ZXIC_UINT32 se_linkid,
-                                               ZXIC_UINT32 se_weight,
-                                               ZXIC_UINT32 se_sp);
-
-/***********************************************************/
-/** 删除流挂接关系
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   id_s      要删除的流号或调度器起始id
-* @param   id_e      要删除的流号或调度器终止id
-*             ETM范围:0--0x47FF; FTM范围:0-0xFFF
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_del_flow_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id_s, ZXIC_UINT32 id_e);
-
-/***********************************************************/
-/** 删除调度器挂接关系(调度器编号从0开始)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   se_id_s   要删除的起始调度器id
-* @param   se_id_e   要删除的终止调度器id
-*          ETM范围:0--0x63FF; FTM范围:0-0x77F
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_del_se_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id_s, ZXIC_UINT32 id_e);
-
-/***********************************************************/
-/** 配置se->pp->dev挂接关系
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   se_id   往端口挂接的调度器id
-* @param   pp_id   [0-63]
-* @param   weight  [1-511]
-* @param   sp_mapping   0~7
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/3/4
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_pp_link_set(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 se_id,
-                                      ZXIC_UINT32 pp_id,
-                                      ZXIC_UINT32 weight,
-                                      ZXIC_UINT32 sp_mapping);
-
-/***********************************************************/
-/**
-* @param   dev_id   设备编号
-* @param   tm_type  0-ETM,1-FTM
-* @param   que_id   queue id
-* @param   en       1:过滤E桶队列CRS状态为SLOW的入链请求；0:E桶队列CRS SLOW正常入链；
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2019/05/08
-************************************************************/
-DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_set(DPP_DEV_T *dev, ZXIC_UINT32 que_id, ZXIC_UINT32 en);
-
-
-/***********************************************************/
-/** 清除整形表格里面的值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/16
-************************************************************/
-DPP_STATUS dpp_tm_clr_shape_para(DPP_DEV_T *dev);
-
-/***********************************************************/
-/** 配置流队列双桶整形使能及模式
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   db_en     双桶整形使能
-* @param   mode      0:c+e模式，1:c+p模式
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_flow_db_en_set(DPP_DEV_T *dev, ZXIC_UINT32 db_en, ZXIC_UINT32 mode);
-
-/***********************************************************/
-/** 配置流级整形参数
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id   流队列号 ETM:0-9215,FTM:0-2047
-* @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
-* @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
-*                    注：cbs=0 表示关闭整形,即不限速
-* @param   db_en     双桶整形使能，0-单桶，1-双桶
-* @param   eir       eir速率，单位Kb，范围同cir
-* @param   ebs       ebs桶深，单位Kb，范围同cbs
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_flow_para_set(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 flow_id,
-                                      ZXIC_UINT32 cir,
-                                      ZXIC_UINT32 cbs,
-                                      ZXIC_UINT32 db_en,
-                                      ZXIC_UINT32 eir,
-                                      ZXIC_UINT32 ebs);
-
-
-/***********************************************************/
-/** tm配置调度器整形参数
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   se_id     调度器编号号 ETM:0x4800-0xABFF,FTM:0x1000-0x177F
-* @param   pir       pir总速率，单位Kb，范围同cir
-* @param   pbs       pbs总桶深，单位Kb，范围同cbs
-* @param   db_en     整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效
-* @param   cir       [0-3]调度器cir速率，单位Kb，范围[64Kb - 160Gb]
-* @param   cbs       [0-3]调度器cbs桶深，单位KB，范围[1KB - 64M]
-*                    注：cbs=0 表示关闭整形,即不限速
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_se_para_set(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 se_id,
-                                    ZXIC_UINT32 pir,
-                                    ZXIC_UINT32 pbs,
-                                    ZXIC_UINT32 db_en,
-                                    ZXIC_UINT32 cir,
-                                    ZXIC_UINT32 cbs);
-
-
-/***********************************************************/
-/** 写入端口级整形信息
-* @param   tm_type   0-ETM,1-FTM
-* @param   port_id   端口号0-63
-* @param   cir
-* @param   cbs
-* @param   c_en   c桶使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/03
-************************************************************/
-DPP_STATUS dpp_tm_shape_pp_para_wr(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 port_id,
-                                   ZXIC_UINT32 cir,
-                                   ZXIC_UINT32 cbs,
-                                   ZXIC_UINT32 c_en);
-
-/***********************************************************/
-/** 配置端口级整形参数  更改整形转换公式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   port_id   端口号
-* @param   p_para   整形信息:CIR/CBS/EN
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/04/15
-************************************************************/
-DPP_STATUS dpp_tm_shape_pp_para_set(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 port_id,
-                                    const DPP_TM_SHAPE_PP_PARA_T *p_para);
-
-/***********************************************************/
-/** 配置轮转扫描使能和扫描速率
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   scan_en   轮转扫描使能。0：关闭，1：开启
-* @param   scan_rate   轮转扫描速率，配置扫描周期不得少于256个周期
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/10
-************************************************************/
-DPP_STATUS dpp_tm_qmu_scan_rate_set(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 scan_en,
-                                    ZXIC_UINT32 scan_rate);
-
-/***********************************************************/
-/** 配置CMD_SW分端口(qmu出端口)整形速率和使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   shape_cir 整形值，单位Mbps，范围[0-160000]
-* @param   shape_cbs 桶深， 单位B，范围[0-0x1EE00]
-* @param   shape_en   整形使能
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author   whuashan   2020-3-17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_egress_shape_set(ZXIC_UINT32 dev_id,
-                                       ZXIC_UINT32 port_id,
-                                       ZXIC_UINT32 shape_cir,
-                                       ZXIC_UINT32 shape_cbs,
-                                       ZXIC_UINT32 shape_en);
-
-
-/***********************************************************/
-/** 配置WRED丢弃曲线对应的参数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   wred_id   队列级共支持16个WRED组0-15，端口级支持8组0-7
-* @param   dp   共支持8个dp，取值0-7
-* @param   p_para   配置的WRED组参数值，包含以下五个参数
-           max_th  平均队列深度上限阈值
-           min_th  平均队列深度下限阈值
-           max_p  最大丢弃概率
-           weight   平均队列深度计算权重
-           q_len_th 队列深度阈值
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  taq     @date  2015/04/20
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_wred_dp_line_para_set(ZXIC_UINT32 dev_id,
-                                              DPP_TM_CGAVD_LEVEL_E level,
-                                              ZXIC_UINT32 wred_id,
-                                              ZXIC_UINT32 dp,
-                                              DPP_TM_WRED_DP_LINE_PARA_T *p_para);
-
-
-/***********************************************************/
-/** 配置各级WRED丢弃曲线对应的参数
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   wred_id   队列级共支持16个WRED组0-15，端口级支持8组0-7
-* @param   dp   共支持8个dp，取值0-7
-* @param   max_th  平均队列深度上限阈值
-* @param   min_th  平均队列深度下限阈值
-* @param   max_p  最大丢弃概率
-* @param   weight   平均队列深度计算权重
-* @param   q_len_th   队列深度阈值
-* @param   flag   忽略乘法里的当前包长和最大包长比标志位:1为忽略
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy     @date  2015/11/9
-************************************************************/
-DPP_STATUS dpp_tm_wred_dp_line_para_flag_wr(ZXIC_UINT32 dev_id,
-                                            ZXIC_UINT32 level,
-                                            ZXIC_UINT32 wred_id,
-                                            ZXIC_UINT32 dp,
-                                            ZXIC_UINT32 max_th,
-                                            ZXIC_UINT32 min_th,
-                                            ZXIC_UINT32 max_p,
-                                            ZXIC_UINT32 weight,
-                                            ZXIC_UINT32 q_len_th,
-                                            ZXIC_UINT32 flag);
-
-/***********************************************************/
-/** 配置CPU设置的报文长度是否参与计算丢弃概率的使能
-* @param   tm_type   0-ETM,1-FTM
-* @param   flag   忽略乘法里的当前包长和最大包长比标志位:1为忽略
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy    @date  2015/11/9
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_wred_pke_len_calc_sign_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 flag);
-
-
-/***********************************************************/
-/** TMMU TM纯片内模式配置
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   imem_en   1纯片内
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  说明：高有效，表示使能打开，TMMU不会再发起对MMU的读写操作，用户需要保证Cache PD全部命中。
-* @see
-* @author  wush      @date  2017/10/14
-************************************************************/
-DPP_STATUS dpp_tm_tmmu_imem_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 imem_en);
-
-/***********************************************************/
-/** TMMU 强制DDR RDY配置
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   ddr_force_rdy   1、如果bit【0】配置为1，则QMU看到的DDR0 RDY一直为1。
-                           2、bit【0】代表DDR0，bit【7】代表DDR7。
-                           3、纯片内模式需要配置为8'hff，排除DDR干扰。
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark
-* @see
-* @author  wush      @date  2017/10/14
-************************************************************/
-DPP_STATUS dpp_tm_tmmu_ddr_force_rdy_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_force_rdy);
-
-/***********************************************************/
-/** 写一片连续的TM寄存器
-* @param   module_id 区分TM子模块
-* @param   first_addr   起始寄存器的地址
-* @param   reg_num   总共读取的寄存器数
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/26
-************************************************************/
-DPP_STATUS dpp_tm_wr_more_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 first_addr, ZXIC_UINT32 first_data, ZXIC_UINT32 data_step, ZXIC_UINT32 reg_num);
-
-/***********************************************************/
-/** 打印tm诊断常用函数信息
-*
-* @return
-* @remark  无
-* @see
-* @author  张明月      @date  2015/10/21
-************************************************************/
-DPP_STATUS dpp_tm_help(ZXIC_UINT32 dev_id);
-
-/***********TM CPU软复位接口 End*************/
-
-
-#endif/***function declaration***/
-
-#endif/****_DPP_TM_H_****/
-
-
-
-
-
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_tm_api.h
+* 文件标识 : tm模块对外数据类型定义和接口函数声明
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : djf
+* 完成日期 : 2015/02/04
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#ifndef _DPP_TM_API_H_
+#define _DPP_TM_API_H_
+
+#if ZXIC_REAL("header file")
+#include "dpp_module.h"
+#endif
+
+#if ZXIC_REAL("macro")
+#define DPP_TM_SA_NUM (128)
+#define DPP_TM_PP_NUM (64) /**< @brief TM内部逻辑端口数 */
+#define DPP_ETM_Q_NUM (9216) /**< @ETM qmu支持9K物理队列 */
+#define DPP_FTM_Q_NUM (2048) /**< @FTM qmu支持2k队列 */
+#define DPP_ETM_CRDT_NUM (0x47FF) /*etm 支持的crdt流队列逻辑编号cir+eir=18K */
+#define DPP_FTM_CRDT_NUM (0xFFF) /*ftm 支持的crdt流队列逻辑编号cir+eir=4K */
+#define DPP_ETM_MID_SE_NUM (6144) /**< @ETM中间级共享0x17FF调度单元 */
+#define DPP_FTM_MID_SE_NUM (512) /**< @FTM 中间级共享0x1FF调度单元 */
+#define DPP_ETM_MID_WFQFQ_NUM (8 * 6144) /**< @brief 中间级共享8 * 6144调度器 */
+#define DPP_FTM_MID_WFQFQ_NUM (8 * 512) /**< @brief 中间级共享8 * 512调度器 */
+
+#define DPP_ETM_WFQSP_OFFSET (0x4000) /*etm sp-wfq调度器相对于fq调度器编号偏移*/
+#define DPP_ETM_FQ_NUM (16 * 1024) /*etm fq调度器个数*/
+#define DPP_ETM_WFQSP_NUM (9 * 1024) /*etm sp8和wfq调度器个数*/
+#define DPP_ETM_FQSPWFQ_NUM (25 * 1024) /*etm fq-sp-wfq调度器总个数*/
+#define DPP_FTM_WFQSP_NUM (1920 + 64) /*ftm sp8和wfq调度器个数+64个端口*/
+#define DPP_ETM_SCH_DEL_NUM (0xABFF) /*etm-crdt要删除的流和调度器编号*/
+#define DPP_FTM_SCH_DEL_NUM (0x177F) /*ftm-crdt要删除的流和调度器编号*/
+
+#define DPP_TM_INVALID_PORT \
+	(0xFFFF) /* 定义crdt无效端口号,用于判定crdt挂接状态 */
+#define DPP_FTM_DELETED_LINK_ID (0x7FF) /**定义ftm已被删除的link_id**/
+#define DPP_ETM_DELETED_LINK_ID (0x7FFF) /**定义etm已被删除的link_id**/
+
+/* ftm/etm调度器往端口级挂接link_id偏移 */
+#define DPP_FTM_PORT_LINKID_BASE (0x780)
+#define DPP_ETM_PORT_LINKID_BASE (0x7F80)
+/**SHAP模块se_id编号基址(非从0开始)**/
+#define DPP_FTM_SHAP_SEID_BASE (0x1000)
+#define DPP_ETM_SHAP_SEID_BASE (0x4800)
+
+/**< @brief TD */
+#define DPP_TM_Q_TD_TH_MAX (8192) /**< @brief Kbyte */
+#define DPP_TM_PP_TD_TH_MAX (8192) /**< @brief Kbyte */
+#define DPP_TM_SYS_TD_TH_MAX (8192) /**< @brief Kbyte */
+
+#define DPP_TM_Q_AVG_Q_LEN_MAX (8192) /**< @brief Kbyte */
+#define DPP_TM_PP_AVG_Q_LEN_MAX (8192) /**< @brief Kbyte */
+#define DPP_TM_SYS_AVG_Q_LEN_MAX (8192) /**< @brief Kbyte */
+
+/**< @brief WRED */
+#define DPP_TM_Q_WRED_NUM (32) /**< @brief 队列级WRED组数 */
+#define DPP_TM_Q_WRED_TH_MAX (8192) /**< @brief Kbyte */
+#define DPP_TM_Q_WRED_MAX_TH_MAX (8192) /**< @brief Kbyte */
+#define DPP_TM_Q_WRED_MIN_TH_MAX (8192) /**< @brief Kbyte */
+#define DPP_TM_Q_WRED_MAX_CFG_PARA (0xffffffff)
+
+#define DPP_TM_PP_WRED_NUM (8) /**< @brief 端口级WRED组数 */
+#define DPP_TM_PP_WRED_TH_MAX (8192) /**< @brief Kbyte */
+#define DPP_TM_PP_WRED_MAX_TH_MAX (8192) /**< @brief Kbyte */
+#define DPP_TM_PP_WRED_MIN_TH_MAX (8192) /**< @brief Kbyte */
+#define DPP_TM_PP_WRED_MAX_CFG_PARA (0xffffffff)
+
+/**< @brief GRED */
+#define DPP_TM_SYS_GRED_TH_MAX (8192) /**< @brief Kbyte */
+#define DPP_TM_SYS_GRED_MAX_TH_MAX (8192) /**< @brief Kbyte */
+#define DPP_TM_SYS_GRED_MIN_TH_MAX (8192) /**< @brief Kbyte */
+#define DPP_TM_SYS_GRED_MID_TH_MAX (8192) /**< @brief Kbyte */
+
+#define DPP_TM_DP_NUM (8) /**< @brief DP曲线数 */
+#define DPP_TM_RED_P_MIN (1)
+#define DPP_TM_RED_P_MAX (100)
+#define DPP_TM_CGAVD_WEIGHT_MAX (15)
+#define DPP_TM_CGAVD_MOVE_PROFILE_NUM (16)
+
+#define DPP_TM_SCH_WEIGHT_INVALID (0) /**< @brief WFQ权重，FQ时weight是无效的 */
+#define DPP_TM_SCH_WEIGHT_MIN (1)
+#define DPP_TM_SCH_WEIGHT_MAX (511)
+#define DPP_TM_SCH_SP_NUM (8)
+
+#define DPP_ETM_MID_SHAPE_PROFILE_NUM (512) /**< ETM中间级整形策略数 */
+#define DPP_FTM_MID_SHAPE_PROFILE_NUM (64) /**< FTM中间级整形策略数 */
+#define DPP_ETM_FLOW_SHAPE_PROFILE_NUM (512) /**< ETM 流级整形策略数 */
+#define DPP_FTM_FLOW_SHAPE_PROFILE_NUM (128) /**< FTM 流级整形策略数 */
+
+#define DPP_TM_SHAPE_CIR_MIN (0) /**< @brief kbps */
+#define DPP_TM_SHAPE_CIR_MAX \
+	(800 * 1000 * 1000) /**< @brief kbps:用户可配最大整形 */
+#define DPP_TM_SHAPE_CBS_MIN (0) /**< @brief kbyte */
+#define DPP_TM_SHAPE_CBS_MAX \
+	(128 * 1024) /**< @brief kbyte:用户可配最大桶深 128M */
+
+/**< CBS写入寄存器最大值为0x7FF */
+#define DPP_TM_SHAPE_CBS_REG_MIN (0) /**< @brief kbyte */
+#define DPP_TM_SHAPE_CBS_REG_MAX (0x7FF) /**< @brief kbyte */
+
+#define DPP_TM_SYS_HZ (1000 * 1000 * 1000) /* 系统主频1000MHz */
+
+#define DPP_TM_TC_NUM (8)
+
+#endif
+
+#if ZXIC_REAL("data struct define")
+/**< @brief 内置TM工作模式 */
+typedef enum dpp_tm_work_mode_e {
+	DPP_TM_WORK_MODE_TM = 0,
+	DPP_TM_WORK_MODE_SA,
+	DPP_TM_WORK_MODE_INVALID
+} DPP_TM_WORK_MODE_E;
+
+/**< @brief QMU工作模式 */
+typedef enum dpp_tm_qmu_work_mode_e {
+	DPP_TM_QMU_WORK_MODE_2M = 0, /**< @brief 2M节点工作模式 */
+	DPP_TM_QMU_WORK_MODE_4M, /**< @brief 4M节点工作模式 */
+	DPP_TM_QMU_WORK_MODE_INVALID
+} DPP_TM_QMU_WORK_MODE_E;
+
+/**< @brief QMU DDR随机模式 */
+typedef enum dpp_tm_qmu_ddr_random_mode_e {
+	DPP_TM_QMU_DDR_NOT_RANDOM = 0, /**< @brief DDR不随机模式 */
+	DPP_TM_QMU_DDR_RANDOM, /**< @brief DDR随机模式 */
+	DPP_TM_QMU_DDR_RANDOM_MODE_INVALID
+} DPP_TM_QMU_DDR_RANDOM_MODE_E;
+
+/**< @brief 计数模式寄存器 */
+typedef struct dpp_tm_cnt_mode_t {
+	ZXIC_UINT32 fc_count_mode; /**< @brief 计数流控模式 */
+	ZXIC_UINT32 count_rd_mode; /**< @brief 计数读模式 */
+	ZXIC_UINT32 count_overflow_mode; /**< @brief 计数溢出模式  */
+} DPP_TM_CNT_MODE_T;
+
+/**< @brief 中断信息 */
+typedef struct dpp_tm_int_t {
+	ZXIC_UINT32 shap_int;
+	ZXIC_UINT32 crdt_int;
+	ZXIC_UINT32 mmu_int;
+	ZXIC_UINT32 qmu_int;
+	ZXIC_UINT32 cgavd_int;
+	ZXIC_UINT32 olif_int;
+	ZXIC_UINT32 cfgmt_int;
+} DPP_TM_INT_T;
+
+/**< @brief 拥塞避免层次 */
+typedef enum dpp_tm_cgavd_level_e {
+	QUEUE_LEVEL = 0, /**< @brief 流队列级 */
+	PP_LEVEL, /**< @brief 端口级 */
+	SYS_LEVEL, /**< @brief 系统级 */
+	SA_LEVEL, /**< @brief SA队列不可达拥塞避免 */
+	INVALID_LEVEL
+} DPP_TM_CGAVD_LEVEL_E;
+
+/**< @brief dp选取值 */
+typedef enum dpp_tm_cgavd_dp_sel_e {
+	DP_SEL_DP = 0, /**< @brief 选tm头中dp字段作为cgavd的dp */
+	DP_SEL_TC, /**< @brief 选tm头中tc字段作为cgavd的dp */
+	DP_SEL_PKT_LEN, /**< @brief 选tm头中pkt[2:0]字段作为cgavd的dp */
+	INVALID_DP
+} DPP_TM_CGAVD_DP_SEL_E;
+
+/**< @brief 拥塞避免模式 */
+typedef enum dpp_tm_cgavd_method_e {
+	TD_METHOD = 0, /**< @brief TD模式 */
+	WRED_GRED_METHOD, /**< @brief 流级和端口级为WRED模式，系统级为GRED模式 */
+	INVALID_METHOD
+} DPP_TM_CGAVD_METHOD_E;
+
+/**< @brief WRED DP曲线配置参数 */
+typedef struct dpp_tm_wred_dp_line_para_t {
+	ZXIC_UINT32 max_th; /**< @brief 平均队列深度上限阈值 */
+	ZXIC_UINT32 min_th; /**< @brief 平均队列深度下限阈值 */
+	ZXIC_UINT32 max_p; /**< @brief 最大丢弃概率 */
+	ZXIC_UINT32 weight; /**< @brief 平均队列深度计算权重 */
+	ZXIC_UINT32 q_len_th; /**< @brief 队列深度阈值 */
+} DPP_TM_WRED_DP_LINE_PARA_T;
+
+/**< @brief GRED DP曲线配置参数 */
+typedef struct dpp_tm_gred_dp_line_para_t {
+	ZXIC_UINT32 max_th; /**< @brief 第2段平均队列深度上限阈值 */
+	ZXIC_UINT32 mid_th; /**< @brief 第1段平均队列深度上限阈值 */
+	ZXIC_UINT32 min_th; /**< @brief 第1段平均队列深度下限阈值 */
+	ZXIC_UINT32 max_p; /**< @brief 最大丢弃概率 */
+	ZXIC_UINT32 weight; /**< @brief 平均队列深度计算权重 */
+	ZXIC_UINT32 q_len_th; /**< @brief 队列深度阈值 */
+} DPP_TM_GRED_DP_LINE_PARA_T;
+
+/**< @brief CRDT调度层次 */
+typedef enum dpp_tm_sch_level_e {
+	DPP_TM_SCH_LEVEL_Q = 1,
+	DPP_TM_SCH_LEVEL_VC = 2,
+	DPP_TM_SCH_LEVEL_VCG = 3,
+	DPP_TM_SCH_LEVEL_VP = 4,
+	DPP_TM_SCH_LEVEL_PP = 5,
+	DPP_TM_SCH_LEVEL_INVALID
+} DPP_TM_SCH_LEVEL_E;
+
+/**< @brief SP_ID */
+typedef enum dpp_tm_sch_sp_e {
+	DPP_TM_SCH_SP_0 = 0,
+	DPP_TM_SCH_SP_1 = 1,
+	DPP_TM_SCH_SP_2 = 2,
+	DPP_TM_SCH_SP_3 = 3,
+	DPP_TM_SCH_SP_4 = 4,
+	DPP_TM_SCH_SP_5 = 5,
+	DPP_TM_SCH_SP_6 = 6,
+	DPP_TM_SCH_SP_7 = 7,
+	DPP_TM_SCH_SP_8 = 8,
+	DPP_TM_SCH_SP_INVALID
+} DPP_TM_SCH_SP_E;
+
+/**< @brief 调度单元挂接参数 */
+typedef struct dpp_tm_sch_para_t {
+	ZXIC_UINT32
+	level_id; /**< @brief 当前为中间级时，vc:0 vcg:1 vp:2 para_get已加2供调用*/
+	DPP_TM_SCH_LEVEL_E se_last_level; /**< @brief 挂接到的上级层次 */
+	ZXIC_UINT32 se_id; /**< @brief 挂接到的上级调度单元ID */
+	DPP_TM_SCH_SP_E c_sp_id; /**< @brief C桶挂接到的SPID,SP0~SP7 */
+	DPP_TM_SCH_SP_E e_sp_id; /**< @brief E桶挂接到的SPID,SP0~SP7 */
+	ZXIC_UINT32
+	sp_relay; /**< @brief 队列优先级传递标志,FLOW级时表示FLOW_WORK_MODE */
+	ZXIC_UINT32 c_sp_weight; /**< @brief C桶挂接到的调度器是WFQ的话，WFQ的权重 */
+	ZXIC_UINT32 e_sp_weight; /**< @brief E桶挂接到的调度器是WFQ的话，WFQ的权重 */
+} DPP_TM_SCH_PARA_T;
+
+/**< @brief 调度器参数 */
+typedef struct dpp_tm_wfqfq_t {
+	ZXIC_UINT32 wfqfq_id
+			[8]; /**< @brief 本级调度单元下挂接的8个调度器ID，FQ/WFQ，由ID号区分 */
+} DPP_TM_WFQFQ_T;
+
+/**< @brief 流队列挂接参数 */
+typedef struct dpp_tm_sch_flow_para_t {
+	ZXIC_UINT32 c_linkid; /**< @brief c桶要挂接到的上级调度器id */
+	ZXIC_UINT32 c_weight; /**< @brief c桶挂接到上级调度器的权重[1~511] */
+	ZXIC_UINT32
+	c_sp; /**< @brief c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 */
+	ZXIC_UINT32
+	mode; /**< @brief 挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可 */
+	ZXIC_UINT32 e_linkid; /**< @brief e桶要挂接到的上级调度器id */
+	ZXIC_UINT32 e_weight; /**< @brief e桶挂接到上级调度器的权重[1~511] */
+	ZXIC_UINT32
+	e_sp; /**< @brief e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低 */
+} DPP_TM_SCH_FLOW_PARA_T;
+
+/**< @brief 调度单元挂接参数:非优先级传递 */
+typedef struct dpp_tm_sch_se_para_t {
+	ZXIC_UINT32 se_linkid; /**< @brief 要挂接到的上级调度器id */
+	ZXIC_UINT32 cp_token_en; /**< @brief 调度器cp双桶使能开关，仅fq8/wfq8支持 */
+	ZXIC_UINT32 se_weight; /**< @brief 挂接到上级调度器的权重[1~511] */
+	ZXIC_UINT32
+	se_sp; /**< @brief 挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 */
+} DPP_TM_SCH_SE_PARA_T;
+
+/**< @brief 调度单元挂接参数:优先级传递开启 */
+typedef struct dpp_tm_sch_se_para_insw_t {
+	ZXIC_UINT32 se_linkid; /**< @brief  要挂接到的上级调度器id */
+	ZXIC_UINT32 cp_token_en; /**< @brief 调度器cp双桶使能开关，仅fq8/wfq8支持 */
+	ZXIC_UINT32
+	se_sp; /**< @brief 挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低 */
+	ZXIC_UINT32 se_weight
+			[8]; /**< @brief WFQ8中各调度器权重值[1~511]，若是WFQ2/4 只取前面对应值，后面无效 */
+} DPP_TM_SCH_SE_PARA_INSW_T;
+
+typedef enum dpp_tm_sch_port_linkid_t {
+	DPP_TM_PP_LINKID_PORT0 = 0x7F80,
+	DPP_TM_PP_LINKID_PORT1 = 0x7F81,
+	DPP_TM_PP_LINKID_PORT2 = 0x7F82,
+	DPP_TM_PP_LINKID_PORT3 = 0x7F83,
+	DPP_TM_PP_LINKID_PORT4 = 0x7F84,
+	DPP_TM_PP_LINKID_PORT5 = 0x7F85,
+	DPP_TM_PP_LINKID_PORT6 = 0x7F86,
+	DPP_TM_PP_LINKID_PORT7 = 0x7F87,
+	DPP_TM_PP_LINKID_PORT8 = 0x7F88,
+	DPP_TM_PP_LINKID_PORT9 = 0x7F89,
+	DPP_TM_PP_LINKID_PORT10 = 0x7F8A,
+	DPP_TM_PP_LINKID_PORT11 = 0x7F8B,
+	DPP_TM_PP_LINKID_PORT12 = 0x7F8C,
+	DPP_TM_PP_LINKID_PORT13 = 0x7F8D,
+	DPP_TM_PP_LINKID_PORT14 = 0x7F8E,
+	DPP_TM_PP_LINKID_PORT15 = 0x7F8F,
+	DPP_TM_PP_LINKID_PORT16 = 0x7F90,
+	DPP_TM_PP_LINKID_PORT17 = 0x7F91,
+	DPP_TM_PP_LINKID_PORT18 = 0x7F92,
+	DPP_TM_PP_LINKID_PORT19 = 0x7F93,
+	DPP_TM_PP_LINKID_PORT20 = 0x7F94,
+	DPP_TM_PP_LINKID_PORT21 = 0x7F95,
+	DPP_TM_PP_LINKID_PORT22 = 0x7F96,
+	DPP_TM_PP_LINKID_PORT23 = 0x7F97,
+	DPP_TM_PP_LINKID_PORT24 = 0x7F98,
+	DPP_TM_PP_LINKID_PORT25 = 0x7F99,
+	DPP_TM_PP_LINKID_PORT26 = 0x7F9A,
+	DPP_TM_PP_LINKID_PORT27 = 0x7F9B,
+	DPP_TM_PP_LINKID_PORT28 = 0x7F9C,
+	DPP_TM_PP_LINKID_PORT29 = 0x7F9D,
+	DPP_TM_PP_LINKID_PORT30 = 0x7F9E,
+	DPP_TM_PP_LINKID_PORT31 = 0x7F9F,
+	DPP_TM_PP_LINKID_PORT32 = 0x7FA0,
+	DPP_TM_PP_LINKID_PORT33 = 0x7FA1,
+	DPP_TM_PP_LINKID_PORT34 = 0x7FA2,
+	DPP_TM_PP_LINKID_PORT35 = 0x7FA3,
+	DPP_TM_PP_LINKID_PORT36 = 0x7FA4,
+	DPP_TM_PP_LINKID_PORT37 = 0x7FA5,
+	DPP_TM_PP_LINKID_PORT38 = 0x7FA6,
+	DPP_TM_PP_LINKID_PORT39 = 0x7FA7,
+	DPP_TM_PP_LINKID_PORT40 = 0x7FA8,
+	DPP_TM_PP_LINKID_PORT41 = 0x7FA9,
+	DPP_TM_PP_LINKID_PORT42 = 0x7FAA,
+	DPP_TM_PP_LINKID_PORT43 = 0x7FAB,
+	DPP_TM_PP_LINKID_PORT44 = 0x7FAC,
+	DPP_TM_PP_LINKID_PORT45 = 0x7FAD,
+	DPP_TM_PP_LINKID_PORT46 = 0x7FAE,
+	DPP_TM_PP_LINKID_PORT47 = 0x7FAF,
+	DPP_TM_PP_LINKID_PORT48 = 0x7FB0,
+	DPP_TM_PP_LINKID_PORT49 = 0x7FB1,
+	DPP_TM_PP_LINKID_PORT50 = 0x7FB2,
+	DPP_TM_PP_LINKID_PORT51 = 0x7FB3,
+	DPP_TM_PP_LINKID_PORT52 = 0x7FB4,
+	DPP_TM_PP_LINKID_PORT53 = 0x7FB5,
+	DPP_TM_PP_LINKID_PORT54 = 0x7FB6,
+	DPP_TM_PP_LINKID_PORT55 = 0x7FB7,
+	DPP_TM_PP_LINKID_PORT56 = 0x7FB8,
+	DPP_TM_PP_LINKID_PORT57 = 0x7FB9,
+	DPP_TM_PP_LINKID_PORT58 = 0x7FBA,
+	DPP_TM_PP_LINKID_PORT59 = 0x7FBB,
+	DPP_TM_PP_LINKID_PORT60 = 0x7FBC,
+	DPP_TM_PP_LINKID_PORT61 = 0x7FBD,
+	DPP_TM_PP_LINKID_PORT62 = 0x7FBE,
+	DPP_TM_PP_LINKID_PORT63 = 0x7FBF,
+	DPP_TM_PP_LINKID_INVALID
+} DPP_TM_SCH_PORT_LINKID_T;
+typedef enum dpp_tm_shape_flag_e {
+	DPP_TM_SHAPE_FLAG_CIR = 0,
+	DPP_TM_SHAPE_FLAG_EIR = 1,
+	DPP_TM_SHAPE_FLAG_INVALID
+} DPP_TM_SHAPE_FLAG_E;
+
+/**< @brief 整形令牌桶模式 */
+typedef enum dpp_tm_shape_mode_e {
+	DPP_TM_SINGLE_MIX_BUCKET = 0, /**< @brief 单桶/组合流 */
+	DPP_TM_DUAL_BUCKET = 1, /**< @brief 双桶 */
+	DPP_TM_DUAL_PIPE = 2, /**< @brief 被双桶 */
+	DPP_TM_SHAPE_MODE_INVALID
+} DPP_TM_SHAPE_MODE_E;
+
+/**< @brief 整形profile参数 */
+typedef struct dpp_tm_shape_profile_t {
+	ZXIC_UINT32 cir;
+	ZXIC_UINT32 cbs;
+	ZXIC_UINT32 eir;
+	ZXIC_UINT32 ebs;
+} DPP_TM_SHAPE_PROFILE_T;
+
+/**< @brief 端口级整形参数 */
+typedef struct dpp_tm_shape_pp_para_t {
+	ZXIC_UINT32 cir;
+	ZXIC_UINT32 cbs;
+	ZXIC_UINT32 c_en;
+} DPP_TM_SHAPE_PP_PARA_T;
+
+/**< @brief 调度单元整形参数 */
+typedef struct dpp_tm_shape_para_t {
+	ZXIC_UINT32 class_id; /**< @brief 当前中间级所属层次，vc:1 vcg:2 vp:3 */
+	ZXIC_UINT32 profile_id;
+	ZXIC_UINT32 c_en;
+	ZXIC_UINT32 e_en;
+	DPP_TM_SHAPE_MODE_E mode;
+} DPP_TM_SHAPE_PARA_T;
+
+/**< @brief 整形参数 */
+typedef struct dpp_tm_shape_t {
+	ZXIC_UINT32 mid_level; /**< @brief 当前中间级所属层次，vc:1 vcg:2 vp:3 */
+	ZXIC_UINT32 cir;
+	ZXIC_UINT32 cbs;
+	ZXIC_UINT32 eir;
+	ZXIC_UINT32 ebs;
+	ZXIC_UINT32 c_en;
+	ZXIC_UINT32 e_en;
+	ZXIC_UINT32 mode;
+} DPP_TM_SHAPE_T;
+
+typedef struct dpp_tm_shape_para {
+	ZXIC_UINT32 shape_cir;
+	ZXIC_UINT32 shape_cbs;
+	ZXIC_UINT32 shape_num;
+} DPP_TM_SHAPE_PARA_TABLE;
+
+/**< @brief TM初始化参数 */
+typedef struct dpp_tm_init_para_t {
+	DPP_TM_WORK_MODE_E tm_sa_mode; /**< @brief TM或SA模式 */
+	DPP_TM_QMU_WORK_MODE_E qmu_mode; /**< @brief QMU 2M或4M节点模式 */
+	ZXIC_UINT32
+	case_num; /**< @brief 四组QMU初始化场景编号为1-4;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8.*/
+	DPP_TM_QMU_DDR_RANDOM_MODE_E ddr_random_mode; /**< @brief ddr随机模式 */
+	ZXIC_UINT32 block_size; /**< @brief block模式，128/256/512/1024 */
+	ZXIC_UINT32 local_sa_id; /**< @brief SA模式时，本地sa_id*/
+} DPP_TM_INIT_PARA_T;
+
+/* TM ASIC初始化信息配置 */
+typedef struct dpp_tm_asic_init_info_t {
+	ZXIC_UINT32
+	blk_size; /**< @brief qmu配置的block大小 256B/512B[default]/1024B */
+	ZXIC_UINT32
+	case_num; /**< @brief 四组QMU初始化场景编号为1-4;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8. */
+	ZXIC_UINT32 imem_omem; /**< @brief 0:片内外混合; 1:纯片内;2:纯片外 */
+	ZXIC_UINT32 mode; /**< @brief TM工作模式 0:TM模式; 1:SA模式 */
+} DPP_TM_ASIC_INIT_INFO_T;
+
+#endif
+
+#if ZXIC_REAL("function declaration")
+
+/***********************************************************/
+/** 读取block长度模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_size   block长度模式，256/512/1024
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/04/09
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_blk_size_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_size);
+
+/***********************************************************/
+/** 配置内置TM的工作模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   mode   配置的值，0-TM模式，1-SA模式
+ *ETM仅工作在TM模式，FTM可以工作TM或SA模式
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/25
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_sa_work_mode_set(DPP_DEV_T *dev,
+										 DPP_TM_WORK_MODE_E mode);
+
+/***********************************************************/
+/**  配置各级搬移功能使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级
+ * @param   en   使能标记，0-不使能，1-使能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2016/10/18
+ ************************************************************/
+#ifdef ETM_REAL
+DPP_STATUS dpp_tm_cgavd_move_en_set(ZXIC_UINT32 dev_id,
+									DPP_TM_CGAVD_LEVEL_E level, ZXIC_UINT32 en);
+
+/***********************************************************/
+/** 配置各级搬移门限
+* @param   dev_id 设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+* @param   id   队列号或端口号，系统级时，id参数无效
+* @param   value   端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B；
+* 流级时为搬移profile_id,0~15
+*
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  djf      @date  2016/10/18
+************************************************************/
+DPP_STATUS dpp_tm_cgavd_move_th_set(ZXIC_UINT32 dev_id,
+									DPP_TM_CGAVD_LEVEL_E level, ZXIC_UINT32 id,
+									ZXIC_UINT32 value);
+
+/***********************************************************/
+/**  配置flow级的搬移策略
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   move_profile  flow级的搬移门限分组索引,0~15
+ * @param   th  flow级的搬移门限，单位为KB；
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2016/10/18
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_flow_move_profile_set(ZXIC_UINT32 dev_id,
+											  ZXIC_UINT32 move_profile,
+											  ZXIC_UINT32 th);
+#endif
+
+/***********************************************************/
+/**  配置端口共享的搬移门限
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   th  端口共享的搬移门限，单位为NPPU存包的单位，256B；
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2016/10/18
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_port_share_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 th);
+
+/***********************************************************/
+/**  配置各级拥塞避免功能使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级
+ * @param   en   使能标记，0-不使能，1-使能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_en_set(DPP_DEV_T *dev, DPP_TM_CGAVD_LEVEL_E level,
+							   ZXIC_UINT32 en);
+
+/***********************************************************/
+/** 配置拥塞避免算法
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   id   队列号或端口号，系统级时，id参数无效
+ * @param   method  配置的拥塞避免算法，0:TD，1:WRED/GRED
+ *          配置TD算法时，先配TD阈值，再配置TD算法
+ *          配置WRED算法时,先配置流级或端口级的平均队列深度，再配置WRED算法
+ *          配置GRED算法时，先配置系统级的平均队列深度，在配置成GRED算法
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark
+ * @see
+ * @author  taq      @date  2015/04/14
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_method_set(DPP_DEV_T *dev, DPP_TM_CGAVD_LEVEL_E level,
+								   ZXIC_UINT32 id,
+								   DPP_TM_CGAVD_METHOD_E method);
+
+/***********************************************************/
+/** 配置TD拥塞避免模式下的丢弃门限值
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   id   队列号或端口号，系统级时，id参数无效
+ * @param   td_th   配置的丢弃门限值，用户配置门限值单位为Kbyte，需要转化为Block单位写入寄存器
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_td_th_set(DPP_DEV_T *dev, DPP_TM_CGAVD_LEVEL_E level,
+								  ZXIC_UINT32 id, ZXIC_UINT32 td_th);
+
+/***********************************************************/
+/** 配置指定端口或队列绑定的WRED GROUP ID
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   WRED支持层次号，0:队列级，1:端口级
+ * @param   id   队列号或端口号
+ * @param   wred_id   配置的WRED GROUP ID
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_wred_id_set(ZXIC_UINT32 dev_id,
+									DPP_TM_CGAVD_LEVEL_E level, ZXIC_UINT32 id,
+									ZXIC_UINT32 wred_id);
+
+/***********************************************************/
+/** 配置TM模式下流队列挂接的端口号；SA模式下流队列映射的目的芯片ID
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   q_id   队列号
+ * @param   pp_id   配置的端口号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/18
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_q_map_pp_set(DPP_DEV_T *dev, ZXIC_UINT32 q_id,
+									 ZXIC_UINT32 pp_id);
+
+/***********************************************************/
+/** 配置TM模式tc到flow的映射
+ * @param   dev_id 设备编号
+ * @param   tc_id   itmd tc优先级（0~7）
+ * @param   flow_id 映射的flowid号 （0~4095）
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/07/04
+ ************************************************************/
+DPP_STATUS dpp_tm_tc_map_flow_set(DPP_DEV_T *dev, ZXIC_UINT32 tc_id,
+								  ZXIC_UINT32 flow_id);
+
+/***********************************************************/
+/** 配置指定端口或队列是否支持动态门限机制
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   WRED支持层次号，0:队列级，1:端口级
+ * @param   id   队列号或端口号
+ * @param   en   配置的值，0-不支持动态门限机制，1-支持动态门限机制
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_dyn_th_en_set(DPP_DEV_T *dev,
+									  DPP_TM_CGAVD_LEVEL_E level,
+									  ZXIC_UINT32 id, ZXIC_UINT32 en);
+
+/***********************************************************/
+/**  配置强制片内或片外
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   en      1:使能
+ * @param   mode   1 :omem 强制片外  0:imem 强制片内
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wush      @date  2017/10/14
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_imem_omem_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en,
+									  ZXIC_UINT32 mode);
+
+/***********************************************************/
+/** 读取QMU队列授权价值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_credit_value   授权价值，默认值是400Byte
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy     @date  2016/04/14
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_credit_value_get(DPP_DEV_T *dev,
+									   ZXIC_UINT32 *p_credit_value);
+
+/******************************************************************************
+ *包老化配置
+ * @param: dev_id: 设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ *           aging_en: 包老化使能：1表示包老化功能使能；0表示包老化功能关闭。
+ *           aging_interval: 普通老化两次的间隔配置
+ *           aging_step_interval: 普通老化的老化时间的步进配置值
+ *           aging_start_qnum: 老化起始队列
+ *           aging_end_qnum: 老化结束队列
+ *           aging_req_aful_th: 普通老化FIFO的将满阈值
+ *           aging_pkt_num: 一次老化的包个数
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/05/10
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_pkt_aging_set(DPP_DEV_T *dev, ZXIC_UINT32 aging_en,
+									ZXIC_UINT32 aging_interval,
+									ZXIC_UINT32 aging_step_interval,
+									ZXIC_UINT32 aging_start_qnum,
+									ZXIC_UINT32 aging_end_qnum,
+									ZXIC_UINT32 aging_pkt_num,
+									ZXIC_UINT32 aging_req_aful_th);
+
+/******************************************************************************
+*配置老化一个包的时间，一次老化一个包，老化队列范围为可配
+* @param: dev_id: 设备索引编号
+* @param    tm_type   0: etm; 1: ftm;
+*           aging_en: 包老化使能：1表示包老化功能使能；0表示包老化功能关闭。
+*           aging_time: 老化一个包的时间，单位ms
+*           aging_que_start:老化起始队列
+*           aging_que_start:老化终止队列
+老化时间=2*aging_interval*step_interval*q_num
+aging_interval = (aging_time * 600000) / (2 * 1 * DPP_TM_Q_NUM);
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  xuhb     @date  2020/12/08
+************************************************************/
+DPP_STATUS dpp_tm_qmu_pkt_age_time_set(DPP_DEV_T *dev, ZXIC_UINT32 aging_en,
+									   ZXIC_UINT32 aging_time,
+									   ZXIC_UINT32 aging_que_start,
+									   ZXIC_UINT32 aging_que_end);
+
+/***********************************************************/
+/** 分配etm调度器资源：fq/fq2/fq4/fq8 个数，(共16K= 16384)
+ * @param   dev_id   设备编号
+ * @param   fq_num   FQ调度器个数，须是8的倍数
+ * @param   fq2_num  FQ2调度器个数，须是4的倍数
+ * @param   fq4_num  FQ4调度器个数，须是2的倍数
+ * @param   fq8_num  FQ8调度器个数
+ *          调度器总数不能超过：16K= 16384
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/26
+ ************************************************************/
+DPP_STATUS dpp_etm_crdt_fq_set(DPP_DEV_T *dev, ZXIC_UINT32 fq_num,
+							   ZXIC_UINT32 fq2_num, ZXIC_UINT32 fq4_num,
+							   ZXIC_UINT32 fq8_num);
+
+/***********************************************************/
+/** 分配TM调度器资源：sp/wfq/wfq2/wfq4/wfq8 个数，（etm共9K=9216,ftm共1920个）
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   sp_num   SP调度器个数，须是8的倍数
+ * @param   wfq_num  WFQ调度器个数，须是8的倍数
+ * @param   wfq2_num  WFQ2调度器个数，须是4的倍数
+ * @param   wfq4_num  WFQ4调度器个数，须是2的倍数
+ * @param   wfq8_num  WFQ8调度器个数
+ *          调度器总数不能超过：ETM= 9216; FTM= 1920
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/26
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_wfqsp_set(DPP_DEV_T *dev, ZXIC_UINT32 sp_num,
+								 ZXIC_UINT32 wfq_num, ZXIC_UINT32 wfq2_num,
+								 ZXIC_UINT32 wfq4_num, ZXIC_UINT32 wfq8_num);
+
+/***********************************************************/
+/** 配置flow级流队列的挂接关系(flow到上级调度器的挂接)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flow_id   流队列号
+ * @param   c_linkid  c桶要挂接到的上级调度器id
+ * @param   c_weight  c桶挂接到上级调度器的权重[1~511]
+ * @param   c_sp      c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
+ * @param   mode      挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可
+ * @param   e_linkid  e桶要挂接到的上级调度器id
+ * @param   e_weight  e桶挂接到上级调度器的权重[1~511]
+ * @param   e_sp      e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_flow_link_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									 ZXIC_UINT32 c_linkid, ZXIC_UINT32 c_weight,
+									 ZXIC_UINT32 c_sp, ZXIC_UINT32 mode,
+									 ZXIC_UINT32 e_linkid, ZXIC_UINT32 e_weight,
+									 ZXIC_UINT32 e_sp);
+
+/***********************************************************/
+/** 配置调度器层次化QOS的挂接关系:非优先级传递
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   se_id      本级调度器id
+ * @param   se_linkid  要挂接到的上级调度器id
+ * @param   se_weight  挂接到上级调度器的权重[1~511]
+ * @param   se_sp      挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
+ * @param   se_insw    优先级传递使能：0-关 1-开. 该参数不传递直接配0
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_se_link_set(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+								   ZXIC_UINT32 se_linkid, ZXIC_UINT32 se_weight,
+								   ZXIC_UINT32 se_sp);
+
+/***********************************************************/
+/** 配置调度器层次化QOS的挂接关系:优先级传递
+ * @param   dev_id       设备编号
+ * @param   tm_type      0-ETM,1-FTM
+ * @param   se_id        本级调度器id
+ * @param   se_linkid    要挂接到的上级调度器id
+ * @param   se_weight    WFQ2/4/8中各调度器权重值[1~511]，取相等的值
+ * @param   se_sp        挂接到上级调度器的sp优先级,有效值[0-7],共8级，优先级依次降低
+ * @param   se_insw      优先级传递使能：0-关 1-开. 该参数不传递直接配1
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_se_link_insw_set(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+										ZXIC_UINT32 se_linkid,
+										ZXIC_UINT32 se_weight,
+										ZXIC_UINT32 se_sp);
+
+/***********************************************************/
+/** 配置调度器层次化QOS的挂接关系:优先级传递,单个调度器挂接
+ * @param   dev_id       设备编号
+ * @param   tm_type      0-ETM,1-FTM
+ * @param   se_id        本级调度器id
+ * @param   se_linkid    要挂接到的上级调度器id
+ * @param   se_weight    WFQ8中对应调度器权重值[1~511]
+ * @param   se_sp        挂接到上级调度器的sp优先级,有效值[0-7],共8级，优先级依次降低
+ * @param   se_insw      优先级传递使能：0-关 1-开. 该参数不传递直接配1
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_se_link_insw_single_set(DPP_DEV_T *dev,
+											   ZXIC_UINT32 se_id,
+											   ZXIC_UINT32 se_linkid,
+											   ZXIC_UINT32 se_weight,
+											   ZXIC_UINT32 se_sp);
+
+/***********************************************************/
+/** 删除流挂接关系
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   id_s      要删除的流号或调度器起始id
+ * @param   id_e      要删除的流号或调度器终止id
+ *             ETM范围:0--0x47FF; FTM范围:0-0xFFF
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_del_flow_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id_s,
+										 ZXIC_UINT32 id_e);
+
+/***********************************************************/
+/** 删除调度器挂接关系(调度器编号从0开始)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   se_id_s   要删除的起始调度器id
+ * @param   se_id_e   要删除的终止调度器id
+ *          ETM范围:0--0x63FF; FTM范围:0-0x77F
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_del_se_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id_s,
+									   ZXIC_UINT32 id_e);
+
+/***********************************************************/
+/** 配置se->pp->dev挂接关系
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   se_id   往端口挂接的调度器id
+ * @param   pp_id   [0-63]
+ * @param   weight  [1-511]
+ * @param   sp_mapping   0~7
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/3/4
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_se_pp_link_set(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+									  ZXIC_UINT32 pp_id, ZXIC_UINT32 weight,
+									  ZXIC_UINT32 sp_mapping);
+
+/***********************************************************/
+/**
+ * @param   dev_id   设备编号
+ * @param   tm_type  0-ETM,1-FTM
+ * @param   que_id   queue id
+ * @param   en       1:过滤E桶队列CRS状态为SLOW的入链请求；0:E桶队列CRS SLOW正常入链；
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XXX      @date  2019/05/08
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_set(DPP_DEV_T *dev, ZXIC_UINT32 que_id,
+											 ZXIC_UINT32 en);
+
+/***********************************************************/
+/** 清除整形表格里面的值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/07/16
+ ************************************************************/
+DPP_STATUS dpp_tm_clr_shape_para(DPP_DEV_T *dev);
+
+/***********************************************************/
+/** 配置流队列双桶整形使能及模式
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   db_en     双桶整形使能
+ * @param   mode      0:c+e模式，1:c+p模式
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_flow_db_en_set(DPP_DEV_T *dev, ZXIC_UINT32 db_en,
+									   ZXIC_UINT32 mode);
+
+/***********************************************************/
+/** 配置流级整形参数
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flow_id   流队列号 ETM:0-9215,FTM:0-2047
+ * @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
+ * @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
+ *                    注：cbs=0 表示关闭整形,即不限速
+ * @param   db_en     双桶整形使能，0-单桶，1-双桶
+ * @param   eir       eir速率，单位Kb，范围同cir
+ * @param   ebs       ebs桶深，单位Kb，范围同cbs
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_flow_para_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									  ZXIC_UINT32 cir, ZXIC_UINT32 cbs,
+									  ZXIC_UINT32 db_en, ZXIC_UINT32 eir,
+									  ZXIC_UINT32 ebs);
+
+/***********************************************************/
+/** tm配置调度器整形参数
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   se_id     调度器编号号 ETM:0x4800-0xABFF,FTM:0x1000-0x177F
+ * @param   pir       pir总速率，单位Kb，范围同cir
+ * @param   pbs       pbs总桶深，单位Kb，范围同cbs
+ * @param   db_en     整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效
+ * @param   cir       [0-3]调度器cir速率，单位Kb，范围[64Kb - 160Gb]
+ * @param   cbs       [0-3]调度器cbs桶深，单位KB，范围[1KB - 64M]
+ *                    注：cbs=0 表示关闭整形,即不限速
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_se_para_set(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+									ZXIC_UINT32 pir, ZXIC_UINT32 pbs,
+									ZXIC_UINT32 db_en, ZXIC_UINT32 cir,
+									ZXIC_UINT32 cbs);
+
+/***********************************************************/
+/** 写入端口级整形信息
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   port_id   端口号0-63
+ * @param   cir
+ * @param   cbs
+ * @param   c_en   c桶使能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/03/03
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_pp_para_wr(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+								   ZXIC_UINT32 cir, ZXIC_UINT32 cbs,
+								   ZXIC_UINT32 c_en);
+
+/***********************************************************/
+/** 配置端口级整形参数  更改整形转换公式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   port_id   端口号
+ * @param   p_para   整形信息:CIR/CBS/EN
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/04/15
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_pp_para_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+									const DPP_TM_SHAPE_PP_PARA_T *p_para);
+
+/***********************************************************/
+/** 配置轮转扫描使能和扫描速率
+ * @param   dev_id   设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   scan_en   轮转扫描使能。0：关闭，1：开启
+ * @param   scan_rate   轮转扫描速率，配置扫描周期不得少于256个周期
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/10
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_scan_rate_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 scan_en,
+									ZXIC_UINT32 scan_rate);
+
+/***********************************************************/
+/** 配置CMD_SW分端口(qmu出端口)整形速率和使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   shape_cir 整形值，单位Mbps，范围[0-160000]
+ * @param   shape_cbs 桶深， 单位B，范围[0-0x1EE00]
+ * @param   shape_en   整形使能
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author   whuashan   2020-3-17
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_egress_shape_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 port_id,
+									   ZXIC_UINT32 shape_cir,
+									   ZXIC_UINT32 shape_cbs,
+									   ZXIC_UINT32 shape_en);
+
+/***********************************************************/
+/** 配置WRED丢弃曲线对应的参数
+* @param   dev_id   设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @param   level   WRED支持层次号，0:队列级，1:端口级
+* @param   wred_id   队列级共支持16个WRED组0-15，端口级支持8组0-7
+* @param   dp   共支持8个dp，取值0-7
+* @param   p_para   配置的WRED组参数值，包含以下五个参数
+	max_th  平均队列深度上限阈值
+	min_th  平均队列深度下限阈值
+	max_p  最大丢弃概率
+	weight   平均队列深度计算权重
+	q_len_th 队列深度阈值
+*
+* @return  DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  taq     @date  2015/04/20
+************************************************************/
+DPP_STATUS dpp_tm_cgavd_wred_dp_line_para_set(
+		ZXIC_UINT32 dev_id, DPP_TM_CGAVD_LEVEL_E level, ZXIC_UINT32 wred_id,
+		ZXIC_UINT32 dp, DPP_TM_WRED_DP_LINE_PARA_T *p_para);
+
+/***********************************************************/
+/** 配置各级WRED丢弃曲线对应的参数
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   WRED支持层次号，0:队列级，1:端口级
+ * @param   wred_id   队列级共支持16个WRED组0-15，端口级支持8组0-7
+ * @param   dp   共支持8个dp，取值0-7
+ * @param   max_th  平均队列深度上限阈值
+ * @param   min_th  平均队列深度下限阈值
+ * @param   max_p  最大丢弃概率
+ * @param   weight   平均队列深度计算权重
+ * @param   q_len_th   队列深度阈值
+ * @param   flag   忽略乘法里的当前包长和最大包长比标志位:1为忽略
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy     @date  2015/11/9
+ ************************************************************/
+DPP_STATUS
+dpp_tm_wred_dp_line_para_flag_wr(ZXIC_UINT32 dev_id, ZXIC_UINT32 level,
+								 ZXIC_UINT32 wred_id, ZXIC_UINT32 dp,
+								 ZXIC_UINT32 max_th, ZXIC_UINT32 min_th,
+								 ZXIC_UINT32 max_p, ZXIC_UINT32 weight,
+								 ZXIC_UINT32 q_len_th, ZXIC_UINT32 flag);
+
+/***********************************************************/
+/** 配置CPU设置的报文长度是否参与计算丢弃概率的使能
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flag   忽略乘法里的当前包长和最大包长比标志位:1为忽略
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy    @date  2015/11/9
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_wred_pke_len_calc_sign_set(ZXIC_UINT32 dev_id,
+												   ZXIC_UINT32 flag);
+
+/***********************************************************/
+/** TMMU TM纯片内模式配置
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   imem_en   1纯片内
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  说明：高有效，表示使能打开，TMMU不会再发起对MMU的读写操作，用户需要保证Cache PD全部命中。
+ * @see
+ * @author  wush      @date  2017/10/14
+ ************************************************************/
+DPP_STATUS dpp_tm_tmmu_imem_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 imem_en);
+
+/***********************************************************/
+/** TMMU 强制DDR RDY配置
+* @param   dev_id   设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @param   ddr_force_rdy   1、如果bit【0】配置为1，则QMU看到的DDR0 RDY一直为1。
+*                          2、bit【0】代表DDR0，bit【7】代表DDR7。
+*                          3、纯片内模式需要配置为8'hff，排除DDR干扰。
+*
+* @return  DPP_OK-成功，DPP_ERR-失败
+* @remark
+* @see
+* @author  wush      @date  2017/10/14
+************************************************************/
+DPP_STATUS dpp_tm_tmmu_ddr_force_rdy_set(ZXIC_UINT32 dev_id,
+										 ZXIC_UINT32 ddr_force_rdy);
+
+/***********************************************************/
+/** 写一片连续的TM寄存器
+ * @param   module_id 区分TM子模块
+ * @param   first_addr   起始寄存器的地址
+ * @param   reg_num   总共读取的寄存器数
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/07/26
+ ************************************************************/
+DPP_STATUS dpp_tm_wr_more_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id,
+							  ZXIC_UINT32 first_addr, ZXIC_UINT32 first_data,
+							  ZXIC_UINT32 data_step, ZXIC_UINT32 reg_num);
+
+/***********************************************************/
+/** 打印tm诊断常用函数信息
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  张明月      @date  2015/10/21
+ ************************************************************/
+DPP_STATUS dpp_tm_help(ZXIC_UINT32 dev_id);
+
+/***********TM CPU软复位接口 End*************/
+
+#endif /***function declaration***/
+
+#endif /****_DPP_TM_H_****/
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_type_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_type_api.h
old mode 100755
new mode 100644
index 5b988e8a8b2facec2776f1f52847fde8122e1047..f979d3ef8ce198b62c4bfe55f8cd9c8469f5dc4b
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_type_api.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/api/dpp_type_api.h
@@ -24,54 +24,42 @@
 extern "C" {
 #endif
 
-
 //#define DPP_FOR_IDE      /* IDE仿真器Driver编译控制宏，通过VC工具导入，不允许手动更改此行 */
-//#define DPP_FOR_LLT      /* DPP 打桩控制宏，通过Makefile编译脚本导入，不允许手动更改此行 "make ssp4_test_64 DPPLLT=1"*/
-
+//#define DPP_FOR_LLT      /* DPP 打桩控制宏，通过Makefile编译脚本导入，不允许手动更改此行 "make ssp4_test_64
+//DPPLLT=1"*/
 
 #ifndef DPP_FOR_LLT
 /* write hardware enable */
-#define     DPP_HW_OPR_EN       (1)
+#define DPP_HW_OPR_EN (1)
 #else
 /* write hardware disable */
-#define     DPP_HW_OPR_EN       (1)
+#define DPP_HW_OPR_EN (1)
 #endif
 
 #ifndef DPP_FOR_LLT
-    #ifndef DPP_FOR_RISCV
-        #ifndef DPP_FOR_PCIE
-        /* dev VPCI enalbe */
-            #define     DPP_DEV_VPCI_EN     (1)
-        #else
-            #define     DPP_DEV_VPCI_EN     (0)
-        #endif
-    #else
-        #define     DPP_DEV_VPCI_EN     (0)
-    #endif
+#ifndef DPP_FOR_RISCV
+#ifndef DPP_FOR_PCIE
+/* dev VPCI enalbe */
+#define DPP_DEV_VPCI_EN (1)
 #else
-    #define     DPP_DEV_VPCI_EN     (0)
+#define DPP_DEV_VPCI_EN (0)
+#endif
+#else
+#define DPP_DEV_VPCI_EN (0)
+#endif
+#else
+#define DPP_DEV_VPCI_EN (0)
 #endif
-
 
 /* CPU软复位调试时开启 */
-#define     DPP_CPU_SOFT_RESET  (0)
+#define DPP_CPU_SOFT_RESET (0)
 
-#if defined(ZXIC_OS_WIN)
-#define DPP_OS_WIN32
-#elif defined(ZXIC_OS_LINUX)
 #define DPP_OS_LINUX
-#endif
-
-
-#ifdef ZXIC_OS_WIN
-#define SDT_FILE_PATH         "..\\tools\\midware\\table_info.txt"
-#else
-#define SDT_FILE_PATH         "table_info.txt"
-#endif
 
+#define SDT_FILE_PATH "table_info.txt"
 
 #ifndef BOOL
-#define BOOL   int
+#define BOOL int
 #endif
 
 #ifndef BOOLEAN
@@ -79,337 +67,333 @@ extern "C" {
 #endif
 
 #ifndef DPP_STATUS
-#define DPP_STATUS               ZXIC_UINT32
+#define DPP_STATUS ZXIC_UINT32
 #endif
 
 #ifndef DPP_OK
-#define DPP_OK                   (0)
+#define DPP_OK (0)
 #endif
 
 #ifndef DPP_ERR
-#define DPP_ERR                  (1)
+#define DPP_ERR (1)
 #endif
 
+#define DPP_RD_CNT_MAX (100) /* 最大读完成状态次数 */
 
-#define DPP_RD_CNT_MAX        (100)     /* 最大读完成状态次数 */
-
-#define DPP_PRT_BIT_LEN_1     (1)
-#define DPP_PRT_BIT_LEN_2     (2)
-#define DPP_PRT_BIT_LEN_8     (8)
-#define DPP_PRT_BIT_LEN_16    (16)
-#define DPP_PRT_BIT_LEN_32    (32)
-
+#define DPP_PRT_BIT_LEN_1 (1)
+#define DPP_PRT_BIT_LEN_2 (2)
+#define DPP_PRT_BIT_LEN_8 (8)
+#define DPP_PRT_BIT_LEN_16 (16)
+#define DPP_PRT_BIT_LEN_32 (32)
 
 /* agent module error code */
-#define DPP_RC_AGENT_BASE                (0x100)
-#define DPP_RC_AGENT_INVALID_PARAMS      (DPP_RC_AGENT_BASE | 0x0)
-#define DPP_RC_AGENT_INVALID_RANGES      (DPP_RC_AGENT_BASE | 0x1)
-#define DPP_RC_AGENT_CALL_FUN_FAIL       (DPP_RC_AGENT_BASE | 0x2)
-#define DPP_RC_AGENT_GET_POINTER_FAIL    (DPP_RC_AGENT_BASE | 0x3)
-#define DPP_RC_AGENT_SEND_MSG_FAIL       (DPP_RC_AGENT_BASE | 0x4)
-#define DPP_RC_AGENT_MSG_TYPE_INVALID    (DPP_RC_AGENT_BASE | 0x5)
+#define DPP_RC_AGENT_BASE (0x100)
+#define DPP_RC_AGENT_INVALID_PARAMS (DPP_RC_AGENT_BASE | 0x0)
+#define DPP_RC_AGENT_INVALID_RANGES (DPP_RC_AGENT_BASE | 0x1)
+#define DPP_RC_AGENT_CALL_FUN_FAIL (DPP_RC_AGENT_BASE | 0x2)
+#define DPP_RC_AGENT_GET_POINTER_FAIL (DPP_RC_AGENT_BASE | 0x3)
+#define DPP_RC_AGENT_SEND_MSG_FAIL (DPP_RC_AGENT_BASE | 0x4)
+#define DPP_RC_AGENT_MSG_TYPE_INVALID (DPP_RC_AGENT_BASE | 0x5)
 
 /* common module error code */
-#define DPP_RC_COMMON_BASE               (0x200)
-#define DPP_RC_COMMON_INVALID_PARAMS     (DPP_RC_COMMON_BASE | 0x0)
-#define DPP_RC_COMMON_INVALID_RANGES     (DPP_RC_COMMON_BASE | 0x1)
-#define DPP_RC_COMMON_CALL_FUN_FAIL      (DPP_RC_COMMON_BASE | 0x2)
-#define DPP_RC_COMMON_GET_POINTER_FAIL   (DPP_RC_COMMON_BASE | 0x3)
-#define DPP_RC_COMMON_SEND_MSG_FAIL      (DPP_RC_COMMON_BASE | 0x4)
-#define DPP_RC_COMMON_MSG_TYPE_INVALID   (DPP_RC_COMMON_BASE | 0x5)
+#define DPP_RC_COMMON_BASE (0x200)
+#define DPP_RC_COMMON_INVALID_PARAMS (DPP_RC_COMMON_BASE | 0x0)
+#define DPP_RC_COMMON_INVALID_RANGES (DPP_RC_COMMON_BASE | 0x1)
+#define DPP_RC_COMMON_CALL_FUN_FAIL (DPP_RC_COMMON_BASE | 0x2)
+#define DPP_RC_COMMON_GET_POINTER_FAIL (DPP_RC_COMMON_BASE | 0x3)
+#define DPP_RC_COMMON_SEND_MSG_FAIL (DPP_RC_COMMON_BASE | 0x4)
+#define DPP_RC_COMMON_MSG_TYPE_INVALID (DPP_RC_COMMON_BASE | 0x5)
 #define DPP_RC_COMMON_MEMCPY_S_INVALID_PTR (DPP_RC_COMMON_BASE | 0x6)
 #define DPP_RC_COMMON_MEMCPY_S_MEM_OVERLAP (DPP_RC_COMMON_BASE | 0x7)
-#define DPP_RC_COMMON_CLOSE_FAIL         (DPP_RC_COMMON_BASE | 0x8)
+#define DPP_RC_COMMON_CLOSE_FAIL (DPP_RC_COMMON_BASE | 0x8)
 
 /* config module error code */
-#define DPP_RC_CONFIG_BASE               (0x300)
-#define DPP_RC_CONFIG_PARA_INVALID       (DPP_RC_CONFIG_BASE | 0x0)
-#define DPP_RC_CONFIG_MSG_TYPE_INVALID   (DPP_RC_CONFIG_BASE | 0x1)
-#define DPP_RC_CONFIG_MEM_NO_INVALID     (DPP_RC_CONFIG_BASE | 0x2)
+#define DPP_RC_CONFIG_BASE (0x300)
+#define DPP_RC_CONFIG_PARA_INVALID (DPP_RC_CONFIG_BASE | 0x0)
+#define DPP_RC_CONFIG_MSG_TYPE_INVALID (DPP_RC_CONFIG_BASE | 0x1)
+#define DPP_RC_CONFIG_MEM_NO_INVALID (DPP_RC_CONFIG_BASE | 0x2)
 
 /* debug module error code */
-#define DPP_RC_DBG_BASE                  (0x400)
-#define DPP_RC_DBG_INVALID_PARAMS        (DPP_RC_DBG_BASE | 0x0)
-#define DPP_RC_DBG_INVALID_RANGES        (DPP_RC_DBG_BASE | 0x1)
-#define DPP_RC_DBG_CALL_FUN_FAIL         (DPP_RC_DBG_BASE | 0x2)
-#define DPP_RC_DBG_GET_POINTER_FAIL      (DPP_RC_DBG_BASE | 0x3)
-#define DPP_RC_DBG_SEND_MSG_FAIL         (DPP_RC_DBG_BASE | 0x4)
-#define DPP_RC_DBG_MEM_NOT_ALLOC         (DPP_RC_DBG_BASE | 0x5)
+#define DPP_RC_DBG_BASE (0x400)
+#define DPP_RC_DBG_INVALID_PARAMS (DPP_RC_DBG_BASE | 0x0)
+#define DPP_RC_DBG_INVALID_RANGES (DPP_RC_DBG_BASE | 0x1)
+#define DPP_RC_DBG_CALL_FUN_FAIL (DPP_RC_DBG_BASE | 0x2)
+#define DPP_RC_DBG_GET_POINTER_FAIL (DPP_RC_DBG_BASE | 0x3)
+#define DPP_RC_DBG_SEND_MSG_FAIL (DPP_RC_DBG_BASE | 0x4)
+#define DPP_RC_DBG_MEM_NOT_ALLOC (DPP_RC_DBG_BASE | 0x5)
 
 /* download module error code */
-#define DPP_RC_LOAD_BASE                 (0x500)
-#define DPP_RC_LOAD_INVALID_PARAMS       (DPP_RC_LOAD_BASE | 0x0)
-#define DPP_RC_LOAD_INVALID_RANGES       (DPP_RC_LOAD_BASE | 0x1)
-#define DPP_RC_LOAD_CALL_FUN_FAIL        (DPP_RC_LOAD_BASE | 0x2)
-#define DPP_RC_LOAD_GET_POINTER_FAIL     (DPP_RC_LOAD_BASE | 0x3)
-#define DPP_RC_LOAD_MSG_SEND_FAIL        (DPP_RC_LOAD_BASE | 0x4)
-#define DPP_RC_LOAD_MSG_TYPE_INVALID     (DPP_RC_LOAD_BASE | 0x5)
-#define DPP_RC_LOAD_DEV_NOT_EXIST        (DPP_RC_LOAD_BASE | 0x6)
+#define DPP_RC_LOAD_BASE (0x500)
+#define DPP_RC_LOAD_INVALID_PARAMS (DPP_RC_LOAD_BASE | 0x0)
+#define DPP_RC_LOAD_INVALID_RANGES (DPP_RC_LOAD_BASE | 0x1)
+#define DPP_RC_LOAD_CALL_FUN_FAIL (DPP_RC_LOAD_BASE | 0x2)
+#define DPP_RC_LOAD_GET_POINTER_FAIL (DPP_RC_LOAD_BASE | 0x3)
+#define DPP_RC_LOAD_MSG_SEND_FAIL (DPP_RC_LOAD_BASE | 0x4)
+#define DPP_RC_LOAD_MSG_TYPE_INVALID (DPP_RC_LOAD_BASE | 0x5)
+#define DPP_RC_LOAD_DEV_NOT_EXIST (DPP_RC_LOAD_BASE | 0x6)
 
 /* device module error code */
-#define DPP_RC_DEV_BASE                  (0x600)
-#define DPP_RC_DEV_PARA_INVALID          (DPP_RC_DEV_BASE | 0x0)
-#define DPP_RC_DEV_RANGE_INVALID         (DPP_RC_DEV_BASE | 0x1)
-#define DPP_RC_DEV_CALL_FUNC_FAIL        (DPP_RC_DEV_BASE | 0x2)
-#define DPP_RC_DEV_TYPE_INVALID          (DPP_RC_DEV_BASE | 0x3)
-#define DPP_RC_DEV_CONNECT_FAIL          (DPP_RC_DEV_BASE | 0x4)
-#define DPP_RC_DEV_MSG_INVALID           (DPP_RC_DEV_BASE | 0x5)
-#define DPP_RC_DEV_NOT_EXIST             (DPP_RC_DEV_BASE | 0x6)
-#define DPP_RC_DEV_MGR_NOT_INIT          (DPP_RC_DEV_BASE | 0x7)
-#define DPP_RC_DEV_CFG_NOT_INIT          (DPP_RC_DEV_BASE | 0x8)
+#define DPP_RC_DEV_BASE (0x600)
+#define DPP_RC_DEV_PARA_INVALID (DPP_RC_DEV_BASE | 0x0)
+#define DPP_RC_DEV_RANGE_INVALID (DPP_RC_DEV_BASE | 0x1)
+#define DPP_RC_DEV_CALL_FUNC_FAIL (DPP_RC_DEV_BASE | 0x2)
+#define DPP_RC_DEV_TYPE_INVALID (DPP_RC_DEV_BASE | 0x3)
+#define DPP_RC_DEV_CONNECT_FAIL (DPP_RC_DEV_BASE | 0x4)
+#define DPP_RC_DEV_MSG_INVALID (DPP_RC_DEV_BASE | 0x5)
+#define DPP_RC_DEV_NOT_EXIST (DPP_RC_DEV_BASE | 0x6)
+#define DPP_RC_DEV_MGR_NOT_INIT (DPP_RC_DEV_BASE | 0x7)
+#define DPP_RC_DEV_CFG_NOT_INIT (DPP_RC_DEV_BASE | 0x8)
 
 /* env(xOS) module error code */
-#define DPP_RC_ENV_BASE                  (0x700)
-#define DPP_RC_ENV_PARA_INVALID          (DPP_RC_ENV_BASE | 0x0)
-#define DPP_RC_ENV_RANGE_INVALID         (DPP_RC_ENV_BASE | 0x1)
-#define DPP_RC_ENV_CALL_FUNC_FAIL        (DPP_RC_ENV_BASE | 0x2)
-#define DPP_RC_ENV_SOCKET_FAIL           (DPP_RC_ENV_BASE | 0x3)
-#define DPP_RC_ENV_SOCKET_FULL           (DPP_RC_ENV_BASE | 0x4)
-#define DPP_RC_ENV_THREAD_FAIL           (DPP_RC_ENV_BASE | 0x5)
-#define DPP_RC_ENV_NOT_INIT              (DPP_RC_ENV_BASE | 0x6)
-#define DPP_RC_ENV_TABLE_FULL            (DPP_RC_ENV_BASE | 0x7)
-#define DPP_RC_ENV_MUTEX_FAIL            (DPP_RC_ENV_BASE | 0x8)
-#define DPP_RC_ENV_SOCKET_NOT_EXIST      (DPP_RC_ENV_BASE | 0x9)
+#define DPP_RC_ENV_BASE (0x700)
+#define DPP_RC_ENV_PARA_INVALID (DPP_RC_ENV_BASE | 0x0)
+#define DPP_RC_ENV_RANGE_INVALID (DPP_RC_ENV_BASE | 0x1)
+#define DPP_RC_ENV_CALL_FUNC_FAIL (DPP_RC_ENV_BASE | 0x2)
+#define DPP_RC_ENV_SOCKET_FAIL (DPP_RC_ENV_BASE | 0x3)
+#define DPP_RC_ENV_SOCKET_FULL (DPP_RC_ENV_BASE | 0x4)
+#define DPP_RC_ENV_THREAD_FAIL (DPP_RC_ENV_BASE | 0x5)
+#define DPP_RC_ENV_NOT_INIT (DPP_RC_ENV_BASE | 0x6)
+#define DPP_RC_ENV_TABLE_FULL (DPP_RC_ENV_BASE | 0x7)
+#define DPP_RC_ENV_MUTEX_FAIL (DPP_RC_ENV_BASE | 0x8)
+#define DPP_RC_ENV_SOCKET_NOT_EXIST (DPP_RC_ENV_BASE | 0x9)
 
 /* table module error code */
-#define DPP_RC_TABLE_BASE                (0x800)
-#define DPP_RC_TABLE_PARA_INVALID        (DPP_RC_TABLE_BASE | 0x0)
-#define DPP_RC_TABLE_RANGE_INVALID       (DPP_RC_TABLE_BASE | 0x1)
-#define DPP_RC_TABLE_CALL_FUNC_FAIL      (DPP_RC_TABLE_BASE | 0x2)
-#define DPP_RC_TABLE_SDT_MSG_INVALID     (DPP_RC_TABLE_BASE | 0x3)
-#define DPP_RC_TABLE_SDT_MGR_INVALID     (DPP_RC_TABLE_BASE | 0x4)
-#define DPP_RC_TABLE_IF_VALUE_FAIL       (DPP_RC_TABLE_BASE | 0x5)
-
+#define DPP_RC_TABLE_BASE (0x800)
+#define DPP_RC_TABLE_PARA_INVALID (DPP_RC_TABLE_BASE | 0x0)
+#define DPP_RC_TABLE_RANGE_INVALID (DPP_RC_TABLE_BASE | 0x1)
+#define DPP_RC_TABLE_CALL_FUNC_FAIL (DPP_RC_TABLE_BASE | 0x2)
+#define DPP_RC_TABLE_SDT_MSG_INVALID (DPP_RC_TABLE_BASE | 0x3)
+#define DPP_RC_TABLE_SDT_MGR_INVALID (DPP_RC_TABLE_BASE | 0x4)
+#define DPP_RC_TABLE_IF_VALUE_FAIL (DPP_RC_TABLE_BASE | 0x5)
 
 /* stat module error code */
-#define DPP_RC_STAT_BASE                 (0x900)
-#define DPP_RC_STAT_INIT_ERR             (DPP_RC_STAT_BASE | 0x1)
-#define DPP_RC_STAT_TM_INIT_ERR          (DPP_RC_STAT_BASE | 0x2)
-#define DPP_RC_STAT_TM_DIS_EN            (DPP_RC_STAT_BASE | 0x3)
-#define DPP_RC_STAT_TM_TYPE_ERR          (DPP_RC_STAT_BASE | 0xe)   /* TM 计数类型错误*/
-#define DPP_RC_STAT_TM_DEPTH_ERR         (DPP_RC_STAT_BASE | 0xf)   /* TM 计数深度错误*/
+#define DPP_RC_STAT_BASE (0x900)
+#define DPP_RC_STAT_INIT_ERR (DPP_RC_STAT_BASE | 0x1)
+#define DPP_RC_STAT_TM_INIT_ERR (DPP_RC_STAT_BASE | 0x2)
+#define DPP_RC_STAT_TM_DIS_EN (DPP_RC_STAT_BASE | 0x3)
+#define DPP_RC_STAT_TM_TYPE_ERR (DPP_RC_STAT_BASE | 0xe) /* TM 计数类型错误*/
+#define DPP_RC_STAT_TM_DEPTH_ERR (DPP_RC_STAT_BASE | 0xf) /* TM 计数深度错误*/
 
 /* appl module error code */
-#define DPP_RC_APPL_BASE                 (0xa00)
-#define DPP_RC_APPL_PARA_INVALID         (DPP_RC_APPL_BASE | 0x0)
-#define DPP_RC_APPL_RANGE_INVALID        (DPP_RC_APPL_BASE | 0x1)
-#define DPP_RC_APPL_CALL_FUNC_FAIL       (DPP_RC_APPL_BASE | 0x2)
+#define DPP_RC_APPL_BASE (0xa00)
+#define DPP_RC_APPL_PARA_INVALID (DPP_RC_APPL_BASE | 0x0)
+#define DPP_RC_APPL_RANGE_INVALID (DPP_RC_APPL_BASE | 0x1)
+#define DPP_RC_APPL_CALL_FUNC_FAIL (DPP_RC_APPL_BASE | 0x2)
 
 /* reg module error code */
-#define DPP_RC_MODULE_BASE               (0xb00)
-#define DPP_RC_MODULE_PARA_INVALID       (DPP_RC_MODULE_BASE | 0x0)
-#define DPP_RC_MODULE_RANGE_INVALID      (DPP_RC_MODULE_BASE | 0x1)
-#define DPP_RC_MODULE_CALL_FUNC_FAIL     (DPP_RC_MODULE_BASE | 0x2)
-#define DPP_RC_MODULE_ENUM_TYPE_FAIL     (DPP_RC_MODULE_BASE | 0x3)
-#define DPP_RC_MODULE_BCDR_WR_FAIL       (DPP_RC_MODULE_BASE | 0x4)
+#define DPP_RC_MODULE_BASE (0xb00)
+#define DPP_RC_MODULE_PARA_INVALID (DPP_RC_MODULE_BASE | 0x0)
+#define DPP_RC_MODULE_RANGE_INVALID (DPP_RC_MODULE_BASE | 0x1)
+#define DPP_RC_MODULE_CALL_FUNC_FAIL (DPP_RC_MODULE_BASE | 0x2)
+#define DPP_RC_MODULE_ENUM_TYPE_FAIL (DPP_RC_MODULE_BASE | 0x3)
+#define DPP_RC_MODULE_BCDR_WR_FAIL (DPP_RC_MODULE_BASE | 0x4)
 
 /* reg module error code */
-#define DPP_RC_REG_BASE                  (0xc00)
-#define DPP_RC_REG_PARA_INVALID          (DPP_RC_REG_BASE | 0x0)
-#define DPP_RC_REG_RANGE_INVALID         (DPP_RC_REG_BASE | 0x1)
-#define DPP_RC_REG_CALL_FUNC_FAIL        (DPP_RC_REG_BASE | 0x2)
-#define DPP_RC_REG_FIELD_OVERFLOW        (DPP_RC_REG_BASE | 0x3)
+#define DPP_RC_REG_BASE (0xc00)
+#define DPP_RC_REG_PARA_INVALID (DPP_RC_REG_BASE | 0x0)
+#define DPP_RC_REG_RANGE_INVALID (DPP_RC_REG_BASE | 0x1)
+#define DPP_RC_REG_CALL_FUNC_FAIL (DPP_RC_REG_BASE | 0x2)
+#define DPP_RC_REG_FIELD_OVERFLOW (DPP_RC_REG_BASE | 0x3)
 
 /* DTB module error code */
-#define DPP_RC_DTB_BASE                     (0xd00)
-#define DPP_RC_DTB_MGR_EXIST                (DPP_RC_DTB_BASE | 0x0)
-#define DPP_RC_DTB_MGR_NOT_EXIST            (DPP_RC_DTB_BASE | 0x1)
-#define DPP_RC_DTB_QUEUE_RES_EMPTY          (DPP_RC_DTB_BASE | 0x2)
-#define DPP_RC_DTB_QUEUE_BUFF_SIZE_ERR      (DPP_RC_DTB_BASE | 0x3)
-#define DPP_RC_DTB_QUEUE_ITEM_HW_EMPTY      (DPP_RC_DTB_BASE | 0x4)
-#define DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY      (DPP_RC_DTB_BASE | 0x5)
-#define DPP_RC_DTB_TAB_UP_BUFF_EMPTY        (DPP_RC_DTB_BASE | 0x6)
-#define DPP_RC_DTB_TAB_DOWN_BUFF_EMPTY      (DPP_RC_DTB_BASE | 0x7)
-#define DPP_RC_DTB_TAB_UP_TRANS_ERR         (DPP_RC_DTB_BASE | 0x8)
-#define DPP_RC_DTB_TAB_DOWN_TRANS_ERR       (DPP_RC_DTB_BASE | 0x9)
-#define DPP_RC_DTB_QUEUE_IS_WORKING         (DPP_RC_DTB_BASE | 0xa)
-#define DPP_RC_DTB_QUEUE_IS_NOT_INIT        (DPP_RC_DTB_BASE | 0xb)
-#define DPP_RC_DTB_MEMORY_ALLOC_ERR         (DPP_RC_DTB_BASE | 0xc)
-#define DPP_RC_DTB_PARA_INVALID             (DPP_RC_DTB_BASE | 0xd)
-#define DPP_RC_DMA_RANGE_INVALID            (DPP_RC_DTB_BASE | 0xe)
-#define DPP_RC_DMA_RCV_DATA_EMPTY           (DPP_RC_DTB_BASE | 0xf)
-#define DPP_RC_DTB_LPM_INSERT_FAIL          (DPP_RC_DTB_BASE | 0x10)
-#define DPP_RC_DTB_LPM_DELETE_FAIL          (DPP_RC_DTB_BASE | 0x11)
-#define DPP_RC_DTB_DOWN_LEN_INVALID         (DPP_RC_DTB_BASE | 0x12)
-#define DPP_RC_DTB_DOWN_HASH_CONFLICT       (DPP_RC_DTB_BASE | 0x13)   //3347
-#define DPP_RC_DTB_QUEUE_NOT_ALLOC          (DPP_RC_DTB_BASE | 0x14) 
-#define DPP_RC_DTB_QUEUE_NAME_ERROR         (DPP_RC_DTB_BASE | 0x15) 
-#define DPP_RC_DTB_DUMP_SIZE_SMALL          (DPP_RC_DTB_BASE | 0x16) 
-#define DPP_RC_DTB_SEARCH_VPORT_QUEUE_ZERO  (DPP_RC_DTB_BASE | 0x17) 
-#define DPP_RC_DTB_QUEUE_NOT_ENABLE         (DPP_RC_DTB_BASE | 0x18)
-#define DPP_RC_DTB_OPEN_DEBUG_MODE          (DPP_RC_DTB_BASE | 0x19)
-#define DPP_RC_DTB_OVER_TIME                (DPP_RC_DTB_BASE | 0x1a)   //3354
+#define DPP_RC_DTB_BASE (0xd00)
+#define DPP_RC_DTB_MGR_EXIST (DPP_RC_DTB_BASE | 0x0)
+#define DPP_RC_DTB_MGR_NOT_EXIST (DPP_RC_DTB_BASE | 0x1)
+#define DPP_RC_DTB_QUEUE_RES_EMPTY (DPP_RC_DTB_BASE | 0x2)
+#define DPP_RC_DTB_QUEUE_BUFF_SIZE_ERR (DPP_RC_DTB_BASE | 0x3)
+#define DPP_RC_DTB_QUEUE_ITEM_HW_EMPTY (DPP_RC_DTB_BASE | 0x4)
+#define DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY (DPP_RC_DTB_BASE | 0x5)
+#define DPP_RC_DTB_TAB_UP_BUFF_EMPTY (DPP_RC_DTB_BASE | 0x6)
+#define DPP_RC_DTB_TAB_DOWN_BUFF_EMPTY (DPP_RC_DTB_BASE | 0x7)
+#define DPP_RC_DTB_TAB_UP_TRANS_ERR (DPP_RC_DTB_BASE | 0x8)
+#define DPP_RC_DTB_TAB_DOWN_TRANS_ERR (DPP_RC_DTB_BASE | 0x9)
+#define DPP_RC_DTB_QUEUE_IS_WORKING (DPP_RC_DTB_BASE | 0xa)
+#define DPP_RC_DTB_QUEUE_IS_NOT_INIT (DPP_RC_DTB_BASE | 0xb)
+#define DPP_RC_DTB_MEMORY_ALLOC_ERR (DPP_RC_DTB_BASE | 0xc)
+#define DPP_RC_DTB_PARA_INVALID (DPP_RC_DTB_BASE | 0xd)
+#define DPP_RC_DMA_RANGE_INVALID (DPP_RC_DTB_BASE | 0xe)
+#define DPP_RC_DMA_RCV_DATA_EMPTY (DPP_RC_DTB_BASE | 0xf)
+#define DPP_RC_DTB_LPM_INSERT_FAIL (DPP_RC_DTB_BASE | 0x10)
+#define DPP_RC_DTB_LPM_DELETE_FAIL (DPP_RC_DTB_BASE | 0x11)
+#define DPP_RC_DTB_DOWN_LEN_INVALID (DPP_RC_DTB_BASE | 0x12)
+#define DPP_RC_DTB_DOWN_HASH_CONFLICT (DPP_RC_DTB_BASE | 0x13)
+#define DPP_RC_DTB_QUEUE_NOT_ALLOC (DPP_RC_DTB_BASE | 0x14)
+#define DPP_RC_DTB_QUEUE_NAME_ERROR (DPP_RC_DTB_BASE | 0x15)
+#define DPP_RC_DTB_DUMP_SIZE_SMALL (DPP_RC_DTB_BASE | 0x16)
+#define DPP_RC_DTB_SEARCH_VPORT_QUEUE_ZERO (DPP_RC_DTB_BASE | 0x17)
+#define DPP_RC_DTB_QUEUE_NOT_ENABLE (DPP_RC_DTB_BASE | 0x18)
+#define DPP_RC_DTB_OPEN_DEBUG_MODE (DPP_RC_DTB_BASE | 0x19)
 
 /* lif module error code */
-#define DPP_RC_LIF_BASE                  (0xe00)
-#define DPP_RC_LIF_PARA_INVALID             (DPP_RC_LIF_BASE | 0x0)
-#define DPP_RC_LIF_RANGE_INVALID            (DPP_RC_LIF_BASE | 0x1)
-#define DPP_RC_LIF_CALL_FUNC_FAIL           (DPP_RC_LIF_BASE | 0x2)
-#define DPP_RC_LIF_OPER_MODE_ERR            (DPP_RC_LIF_BASE | 0x3)
-#define DPP_RC_SERDES_ARRAY_OVERFLOW        (DPP_RC_LIF_BASE | 0x4)
-#define DPP_RC_RCV_PLL_LOCK_TIMEOUT         (DPP_RC_LIF_BASE | 0x5)
-#define DPP_RC_LIF_TIMEOUT                  (DPP_RC_LIF_BASE | 0x7)
-#define DPP_RC_LIF_NO_PORT                  (DPP_RC_LIF_BASE | 0x8)
-#define DPP_RC_BCDR_PARA_ERR                (DPP_RC_LIF_BASE | 0x9)
-#define DPP_RC_LIF_NOT_SUPPORT              (DPP_RC_LIF_BASE | 0xa)
+#define DPP_RC_LIF_BASE (0xe00)
+#define DPP_RC_LIF_PARA_INVALID (DPP_RC_LIF_BASE | 0x0)
+#define DPP_RC_LIF_RANGE_INVALID (DPP_RC_LIF_BASE | 0x1)
+#define DPP_RC_LIF_CALL_FUNC_FAIL (DPP_RC_LIF_BASE | 0x2)
+#define DPP_RC_LIF_OPER_MODE_ERR (DPP_RC_LIF_BASE | 0x3)
+#define DPP_RC_SERDES_ARRAY_OVERFLOW (DPP_RC_LIF_BASE | 0x4)
+#define DPP_RC_RCV_PLL_LOCK_TIMEOUT (DPP_RC_LIF_BASE | 0x5)
+#define DPP_RC_LIF_TIMEOUT (DPP_RC_LIF_BASE | 0x7)
+#define DPP_RC_LIF_NO_PORT (DPP_RC_LIF_BASE | 0x8)
+#define DPP_RC_BCDR_PARA_ERR (DPP_RC_LIF_BASE | 0x9)
+#define DPP_RC_LIF_NOT_SUPPORT (DPP_RC_LIF_BASE | 0xa)
 
 /* ddr module error code */
-#define DPP_RC_DDR_BASE                  (0x1000)
-#define DPP_RC_DDR_TIME_OUT          (DPP_RC_DDR_BASE | 0x0)
-#define DPP_RC_DDR_TRAIN_FAIL        (DPP_RC_DDR_BASE | 0x1)
-#define DPP_RC_DDR_TYPE_ERR          (DPP_RC_DDR_BASE | 0x2)
-#define DPP_RC_DDR_LOGCHK_ERR        (DPP_RC_DDR_BASE | 0x3)
-#define DPP_RC_DDR_PARA_ERR          (DPP_RC_DDR_BASE | 0x4)
-#define DPP_RC_DDR_DAMAGED           (DPP_RC_DDR_BASE | 0x5)
-#define DPP_RC_DDR_DISABLE           (DPP_RC_DDR_BASE | 0x6)
-#define DPP_RC_DDR_ARRAY_OVERFLOW    (DPP_RC_DDR_BASE | 0x7)
-#define DPP_RC_DDR_INVAL_TRAIN_MODE  (DPP_RC_DDR_BASE | 0x8)
-#define DPP_RC_DDR_INVAL_VREF_MODE   (DPP_RC_DDR_BASE | 0x9)
-#define DPP_RC_DDR_INTR_ERR          (DPP_RC_DDR_BASE | 0xa)
-#define DPP_RC_DDR_BIST_FAIL         (DPP_RC_DDR_BASE | 0xb)
-#define DPP_RC_DDR_SOFTCHK_FAIL      (DPP_RC_DDR_BASE | 0xb)
-#define DPP_RC_DDR_PLL_LOCK_TIMEOUT  (DPP_RC_DDR_BASE | 0x0)
+#define DPP_RC_DDR_BASE (0x1000)
+#define DPP_RC_DDR_TIME_OUT (DPP_RC_DDR_BASE | 0x0)
+#define DPP_RC_DDR_TRAIN_FAIL (DPP_RC_DDR_BASE | 0x1)
+#define DPP_RC_DDR_TYPE_ERR (DPP_RC_DDR_BASE | 0x2)
+#define DPP_RC_DDR_LOGCHK_ERR (DPP_RC_DDR_BASE | 0x3)
+#define DPP_RC_DDR_PARA_ERR (DPP_RC_DDR_BASE | 0x4)
+#define DPP_RC_DDR_DAMAGED (DPP_RC_DDR_BASE | 0x5)
+#define DPP_RC_DDR_DISABLE (DPP_RC_DDR_BASE | 0x6)
+#define DPP_RC_DDR_ARRAY_OVERFLOW (DPP_RC_DDR_BASE | 0x7)
+#define DPP_RC_DDR_INVAL_TRAIN_MODE (DPP_RC_DDR_BASE | 0x8)
+#define DPP_RC_DDR_INVAL_VREF_MODE (DPP_RC_DDR_BASE | 0x9)
+#define DPP_RC_DDR_INTR_ERR (DPP_RC_DDR_BASE | 0xa)
+#define DPP_RC_DDR_BIST_FAIL (DPP_RC_DDR_BASE | 0xb)
+#define DPP_RC_DDR_SOFTCHK_FAIL (DPP_RC_DDR_BASE | 0xb)
+#define DPP_RC_DDR_PLL_LOCK_TIMEOUT (DPP_RC_DDR_BASE | 0x0)
 
 /* tlb module error code */
-#define DPP_RC_TLB_BASE               (0x2000)
-#define DPP_RC_TLB_MGR_EXIST          (DPP_RC_TLB_BASE | 0x0)
-#define DPP_RC_TLB_MGR_NOT_EXIST      (DPP_RC_TLB_BASE | 0x1)
+#define DPP_RC_TLB_BASE (0x2000)
+#define DPP_RC_TLB_MGR_EXIST (DPP_RC_TLB_BASE | 0x0)
+#define DPP_RC_TLB_MGR_NOT_EXIST (DPP_RC_TLB_BASE | 0x1)
 
 /* se alg error code */
-#define DPP_SE_RC_BASE            (0x50000)
-#define DPP_SE_RC_ZBLK_FULL          (DPP_SE_RC_CFG_BASE | 0x1)
-#define DPP_SE_RC_FUN_INVALID        (DPP_SE_RC_CFG_BASE | 0x2)
-#define DPP_SE_RC_PARA_INVALID       (DPP_SE_RC_CFG_BASE | 0x3)
-
-#define DPP_SE_RC_CFG_BASE        (DPP_SE_RC_BASE | 0x1000)
-#define DPP_SE_RC_ACL_BASE        (DPP_SE_RC_BASE | 0x2000)
-#define DPP_SE_RC_LPM_BASE        (DPP_SE_RC_BASE | 0x3000)
-#define DPP_LPM_TBL_INVALID       (DPP_SE_RC_LPM_BASE | 0x01)
-#define DPP_LPM_MODE_INVALID      (DPP_SE_RC_LPM_BASE | 0x02)
-#define DPP_LPM_FUNID_INVALID     (DPP_SE_RC_LPM_BASE | 0x03)
-#define DPP_LPM_RAM_FULL          (DPP_SE_RC_LPM_BASE | 0x04)
-#define DPP_LPM_UPDATE            (DPP_SE_RC_LPM_BASE | 0x05)
-#define DPP_LPM_SRHFAIL           (DPP_SE_RC_LPM_BASE | 0x06)
-#define DPP_LPM_KEY_INVALID       (DPP_SE_RC_LPM_BASE | 0x07)
-#define DPP_LPM_DEF_REG_FULL      (DPP_SE_RC_LPM_BASE | 0x08) /*16组默认路由寄存器插满*/
-#define DPP_LPM_DEF_REG_NO_HIT    (DPP_SE_RC_LPM_BASE | 0x09) /*16组默认路由寄存器未匹配删除条目*/
-#define DPP_LPM_DEF_REG_UPDATE    (DPP_SE_RC_LPM_BASE | 0x0A)
-#define DPP_LPM_DIV_GO_ON         (DPP_SE_RC_LPM_BASE | 0x0B)
-#define DPP_LPM_DDR_FULL          (DPP_SE_RC_LPM_BASE | 0x0C)
-#define DPP_LPM_DDR_PARA_INVALID  (DPP_SE_RC_LPM_BASE | 0x0D)
-
-#define DPP_SE_RC_HASH_BASE       (DPP_SE_RC_BASE | 0x4000)
-#define DPP_HASH_RC_INVALID_FUNCINFO          (DPP_SE_RC_HASH_BASE | 0x1)
-#define DPP_HASH_RC_INVALID_ZBLCK             (DPP_SE_RC_HASH_BASE | 0x2)
-#define DPP_HASH_RC_INVALID_ZCELL             (DPP_SE_RC_HASH_BASE | 0x3)
-#define DPP_HASH_RC_INVALID_KEY               (DPP_SE_RC_HASH_BASE | 0x4)
-#define DPP_HASH_RC_INVALID_TBL_ID_INFO       (DPP_SE_RC_HASH_BASE | 0x5)
-#define DPP_HASH_RC_RB_TREE_FULL              (DPP_SE_RC_HASH_BASE | 0x6)
-#define DPP_HASH_RC_INVALID_KEY_TYPE          (DPP_SE_RC_HASH_BASE | 0x7)
-#define DPP_HASH_RC_ADD_UPDATE                (DPP_SE_RC_HASH_BASE | 0x8)
-#define DPP_HASH_RC_DEL_SRHFAIL               (DPP_SE_RC_HASH_BASE | 0x9)
-#define DPP_HASH_RC_ITEM_FULL                 (DPP_SE_RC_HASH_BASE | 0xa)
-#define DPP_HASH_RC_INVALID_DDR_WIDTH_MODE    (DPP_SE_RC_HASH_BASE | 0xb)
-#define DPP_HASH_RC_INVALID_PARA              (DPP_SE_RC_HASH_BASE | 0xc)
-#define DPP_HASH_RC_TBL_FULL                  (DPP_SE_RC_HASH_BASE | 0xd)
-#define DPP_HASH_RC_SRH_FAIL                  (DPP_SE_RC_HASH_BASE | 0xe)
-#define DPP_HASH_RC_MATCH_ITEM_FAIL           (DPP_SE_RC_HASH_BASE | 0xf)
-#define DPP_HASH_RC_DDR_WIDTH_MODE_ERR        (DPP_SE_RC_HASH_BASE | 0x10)
-#define DPP_HASH_RC_INVALID_ITEM_TYPE         (DPP_SE_RC_HASH_BASE | 0x11)
-#define DPP_HASH_RC_REPEAT_INIT               (DPP_SE_RC_HASH_BASE | 0x12)
-
-#define DPP_SE_RC_ETCAM_BASE       (DPP_SE_RC_BASE | 0x5000)
-#define DPP_ETCAM_RC_TBL_INVALID              (DPP_SE_RC_ETCAM_BASE | 0x1)
-#define DPP_ETCAM_RC_TBL_OVERFLOW             (DPP_SE_RC_ETCAM_BASE | 0x2)
-
-#define DPP_ACL_RC_BASE          (0x60000)
-#define DPP_ACL_RC_INVALID_TBLID       (DPP_ACL_RC_BASE | 0x0)
-#define DPP_ACL_RC_INVALID_BLOCKNUM    (DPP_ACL_RC_BASE | 0x1)
-#define DPP_ACL_RC_INVALID_BLOCKID     (DPP_ACL_RC_BASE | 0x2)
-#define DPP_ACL_RC_TBL_NOT_INIT        (DPP_ACL_RC_BASE | 0x3)
-#define DPP_ACL_RC_ETCAMID_NOT_INIT    (DPP_ACL_RC_BASE | 0x4)
-#define DPP_ACL_RC_AS_ERAM_NOT_ENOUGH  (DPP_ACL_RC_BASE | 0x5)
-#define DPP_ACL_RC_RB_TREE_FULL        (DPP_ACL_RC_BASE | 0x6)
-#define DPP_ACL_RC_TABLE_FULL          (DPP_ACL_RC_BASE | 0x7)
-#define DPP_ACL_RC_INVALID_PARA        (DPP_ACL_RC_BASE | 0x8)
-#define DPP_ACL_RC_DEL_SRHFAIL         (DPP_ACL_RC_BASE | 0x9)
-#define DPP_ACL_RC_TABLE_UPDATE        (DPP_ACL_RC_BASE | 0xa)
-#define DPP_ACL_RC_SRH_FAIL            (DPP_ACL_RC_BASE | 0xb)
-
-#define DPP_SE_RC_CAR_BASE       (0x1100)
-#define DPP_RC_CAR_TIME_OUT           (DPP_SE_RC_CAR_BASE | 0x1)
-#define DPP_RC_CAR_QUEUE_OUTRANGE     (DPP_SE_RC_CAR_BASE | 0x2)
-#define DPP_RC_CAR_RB_TREE_FULL       (DPP_SE_RC_CAR_BASE | 0x3)
-#define DPP_RC_CAR_RB_TREE_UPDATE     (DPP_SE_RC_CAR_BASE | 0x4)
-#define DPP_RC_CAR_RB_TREE_DEL_FAIL   (DPP_SE_RC_CAR_BASE | 0x5)
-#define DPP_RC_CAR_RB_TREE_SRH_FAIL   (DPP_SE_RC_CAR_BASE | 0x6)
-#define DPP_RC_CAR_RB_TREE_GET_FAIL   (DPP_SE_RC_CAR_BASE | 0x7)
-#define DPP_RC_CAR_INIT_FAIL          (DPP_SE_RC_CAR_BASE | 0x8)
-#define DPP_RC_CAR_UN_INIT            (DPP_SE_RC_CAR_BASE | 0x9)
-#define DPP_RC_CAR_PROFILE_UNSET      (DPP_SE_RC_CAR_BASE | 0xa)
+#define DPP_SE_RC_BASE (0x50000)
+#define DPP_SE_RC_ZBLK_FULL (DPP_SE_RC_CFG_BASE | 0x1)
+#define DPP_SE_RC_FUN_INVALID (DPP_SE_RC_CFG_BASE | 0x2)
+#define DPP_SE_RC_PARA_INVALID (DPP_SE_RC_CFG_BASE | 0x3)
+
+#define DPP_SE_RC_CFG_BASE (DPP_SE_RC_BASE | 0x1000)
+#define DPP_SE_RC_ACL_BASE (DPP_SE_RC_BASE | 0x2000)
+#define DPP_SE_RC_LPM_BASE (DPP_SE_RC_BASE | 0x3000)
+#define DPP_LPM_TBL_INVALID (DPP_SE_RC_LPM_BASE | 0x01)
+#define DPP_LPM_MODE_INVALID (DPP_SE_RC_LPM_BASE | 0x02)
+#define DPP_LPM_FUNID_INVALID (DPP_SE_RC_LPM_BASE | 0x03)
+#define DPP_LPM_RAM_FULL (DPP_SE_RC_LPM_BASE | 0x04)
+#define DPP_LPM_UPDATE (DPP_SE_RC_LPM_BASE | 0x05)
+#define DPP_LPM_SRHFAIL (DPP_SE_RC_LPM_BASE | 0x06)
+#define DPP_LPM_KEY_INVALID (DPP_SE_RC_LPM_BASE | 0x07)
+#define DPP_LPM_DEF_REG_FULL \
+	(DPP_SE_RC_LPM_BASE | 0x08) /*16组默认路由寄存器插满*/
+#define DPP_LPM_DEF_REG_NO_HIT \
+	(DPP_SE_RC_LPM_BASE | 0x09) /*16组默认路由寄存器未匹配删除条目*/
+#define DPP_LPM_DEF_REG_UPDATE (DPP_SE_RC_LPM_BASE | 0x0A)
+#define DPP_LPM_DIV_GO_ON (DPP_SE_RC_LPM_BASE | 0x0B)
+#define DPP_LPM_DDR_FULL (DPP_SE_RC_LPM_BASE | 0x0C)
+#define DPP_LPM_DDR_PARA_INVALID (DPP_SE_RC_LPM_BASE | 0x0D)
+
+#define DPP_SE_RC_HASH_BASE (DPP_SE_RC_BASE | 0x4000)
+#define DPP_HASH_RC_INVALID_FUNCINFO (DPP_SE_RC_HASH_BASE | 0x1)
+#define DPP_HASH_RC_INVALID_ZBLCK (DPP_SE_RC_HASH_BASE | 0x2)
+#define DPP_HASH_RC_INVALID_ZCELL (DPP_SE_RC_HASH_BASE | 0x3)
+#define DPP_HASH_RC_INVALID_KEY (DPP_SE_RC_HASH_BASE | 0x4)
+#define DPP_HASH_RC_INVALID_TBL_ID_INFO (DPP_SE_RC_HASH_BASE | 0x5)
+#define DPP_HASH_RC_RB_TREE_FULL (DPP_SE_RC_HASH_BASE | 0x6)
+#define DPP_HASH_RC_INVALID_KEY_TYPE (DPP_SE_RC_HASH_BASE | 0x7)
+#define DPP_HASH_RC_ADD_UPDATE (DPP_SE_RC_HASH_BASE | 0x8)
+#define DPP_HASH_RC_DEL_SRHFAIL (DPP_SE_RC_HASH_BASE | 0x9)
+#define DPP_HASH_RC_ITEM_FULL (DPP_SE_RC_HASH_BASE | 0xa)
+#define DPP_HASH_RC_INVALID_DDR_WIDTH_MODE (DPP_SE_RC_HASH_BASE | 0xb)
+#define DPP_HASH_RC_INVALID_PARA (DPP_SE_RC_HASH_BASE | 0xc)
+#define DPP_HASH_RC_TBL_FULL (DPP_SE_RC_HASH_BASE | 0xd)
+#define DPP_HASH_RC_SRH_FAIL (DPP_SE_RC_HASH_BASE | 0xe)
+#define DPP_HASH_RC_MATCH_ITEM_FAIL (DPP_SE_RC_HASH_BASE | 0xf)
+#define DPP_HASH_RC_DDR_WIDTH_MODE_ERR (DPP_SE_RC_HASH_BASE | 0x10)
+#define DPP_HASH_RC_INVALID_ITEM_TYPE (DPP_SE_RC_HASH_BASE | 0x11)
+#define DPP_HASH_RC_REPEAT_INIT (DPP_SE_RC_HASH_BASE | 0x12)
+
+#define DPP_SE_RC_ETCAM_BASE (DPP_SE_RC_BASE | 0x5000)
+#define DPP_ETCAM_RC_TBL_INVALID (DPP_SE_RC_ETCAM_BASE | 0x1)
+#define DPP_ETCAM_RC_TBL_OVERFLOW (DPP_SE_RC_ETCAM_BASE | 0x2)
+
+#define DPP_ACL_RC_BASE (0x60000)
+#define DPP_ACL_RC_INVALID_TBLID (DPP_ACL_RC_BASE | 0x0)
+#define DPP_ACL_RC_INVALID_BLOCKNUM (DPP_ACL_RC_BASE | 0x1)
+#define DPP_ACL_RC_INVALID_BLOCKID (DPP_ACL_RC_BASE | 0x2)
+#define DPP_ACL_RC_TBL_NOT_INIT (DPP_ACL_RC_BASE | 0x3)
+#define DPP_ACL_RC_ETCAMID_NOT_INIT (DPP_ACL_RC_BASE | 0x4)
+#define DPP_ACL_RC_AS_ERAM_NOT_ENOUGH (DPP_ACL_RC_BASE | 0x5)
+#define DPP_ACL_RC_RB_TREE_FULL (DPP_ACL_RC_BASE | 0x6)
+#define DPP_ACL_RC_TABLE_FULL (DPP_ACL_RC_BASE | 0x7)
+#define DPP_ACL_RC_INVALID_PARA (DPP_ACL_RC_BASE | 0x8)
+#define DPP_ACL_RC_DEL_SRHFAIL (DPP_ACL_RC_BASE | 0x9)
+#define DPP_ACL_RC_TABLE_UPDATE (DPP_ACL_RC_BASE | 0xa)
+#define DPP_ACL_RC_SRH_FAIL (DPP_ACL_RC_BASE | 0xb)
+
+#define DPP_SE_RC_CAR_BASE (0x1100)
+#define DPP_RC_CAR_TIME_OUT (DPP_SE_RC_CAR_BASE | 0x1)
+#define DPP_RC_CAR_QUEUE_OUTRANGE (DPP_SE_RC_CAR_BASE | 0x2)
+#define DPP_RC_CAR_RB_TREE_FULL (DPP_SE_RC_CAR_BASE | 0x3)
+#define DPP_RC_CAR_RB_TREE_UPDATE (DPP_SE_RC_CAR_BASE | 0x4)
+#define DPP_RC_CAR_RB_TREE_DEL_FAIL (DPP_SE_RC_CAR_BASE | 0x5)
+#define DPP_RC_CAR_RB_TREE_SRH_FAIL (DPP_SE_RC_CAR_BASE | 0x6)
+#define DPP_RC_CAR_RB_TREE_GET_FAIL (DPP_SE_RC_CAR_BASE | 0x7)
+#define DPP_RC_CAR_INIT_FAIL (DPP_SE_RC_CAR_BASE | 0x8)
+#define DPP_RC_CAR_UN_INIT (DPP_SE_RC_CAR_BASE | 0x9)
+#define DPP_RC_CAR_PROFILE_UNSET (DPP_SE_RC_CAR_BASE | 0xa)
 #define DPP_RC_CAR_LISTSTACK_MNG_FULL (DPP_SE_RC_CAR_BASE | 0xb)
 
-
 /*system critical item check error code*/
-#define DPP_SYSTEM_CHECK_RC_BASE          (0x70000)
-#define DPP_SYSTEM_CHECK_CRM_RC_BASE         (DPP_SYSTEM_CHECK_RC_BASE | 0x1000)
-#define DPP_SYSTEM_CHECK_LIF0_RC_BASE         (DPP_SYSTEM_CHECK_RC_BASE | 0x2000)
-#define DPP_SYSTEM_CHECK_PKTRX_RC_BASE         (DPP_SYSTEM_CHECK_RC_BASE | 0x3000)
-#define DPP_SYSTEM_CHECK_PBU_RC_BASE         (DPP_SYSTEM_CHECK_RC_BASE | 0x4000)
-#define DPP_SYSTEM_CHECK_PPU_RC_BASE         (DPP_SYSTEM_CHECK_RC_BASE | 0x5000)
-#define DPP_SYSTEM_CHECK_ODMA_RC_BASE         (DPP_SYSTEM_CHECK_RC_BASE | 0x6000)
-#define DPP_SYSTEM_CHECK_CFG_RC_BASE         (DPP_SYSTEM_CHECK_RC_BASE | 0x7000)
-#define DPP_SYSTEM_CHECK_TM_RC_BASE         (DPP_SYSTEM_CHECK_RC_BASE | 0x8000)
-#define DPP_SYSTEM_CHECK_TM_READY_RC_BASE         (DPP_SYSTEM_CHECK_RC_BASE | 0x100)
-#define DPP_SYSTEM_CHECK_TM_SAIP_RC_BASE         (DPP_SYSTEM_CHECK_RC_BASE | 0x200)
-#define DPP_SYSTEM_CHECK_TM_ILIF_RC_BASE         (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x300)
-#define DPP_SYSTEM_CHECK_TM_OLIF_RC_BASE         (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x400)
-#define DPP_SYSTEM_CHECK_TM_TMMU_RC_BASE         (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x500)
-#define DPP_SYSTEM_CHECK_TM_SHAPE_RC_BASE         (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x600)
-#define DPP_SYSTEM_CHECK_TM_CRDT_RC_BASE         (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x700)
-#define DPP_SYSTEM_CHECK_TM_CGAVD_RC_BASE         (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x800)
-#define DPP_SYSTEM_CHECK_TM_QMU_RC_BASE          (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x900)
+#define DPP_SYSTEM_CHECK_RC_BASE (0x70000)
+#define DPP_SYSTEM_CHECK_CRM_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x1000)
+#define DPP_SYSTEM_CHECK_LIF0_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x2000)
+#define DPP_SYSTEM_CHECK_PKTRX_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x3000)
+#define DPP_SYSTEM_CHECK_PBU_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x4000)
+#define DPP_SYSTEM_CHECK_PPU_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x5000)
+#define DPP_SYSTEM_CHECK_ODMA_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x6000)
+#define DPP_SYSTEM_CHECK_CFG_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x7000)
+#define DPP_SYSTEM_CHECK_TM_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x8000)
+#define DPP_SYSTEM_CHECK_TM_READY_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x100)
+#define DPP_SYSTEM_CHECK_TM_SAIP_RC_BASE (DPP_SYSTEM_CHECK_RC_BASE | 0x200)
+#define DPP_SYSTEM_CHECK_TM_ILIF_RC_BASE (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x300)
+#define DPP_SYSTEM_CHECK_TM_OLIF_RC_BASE (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x400)
+#define DPP_SYSTEM_CHECK_TM_TMMU_RC_BASE (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x500)
+#define DPP_SYSTEM_CHECK_TM_SHAPE_RC_BASE (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x600)
+#define DPP_SYSTEM_CHECK_TM_CRDT_RC_BASE (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x700)
+#define DPP_SYSTEM_CHECK_TM_CGAVD_RC_BASE (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x800)
+#define DPP_SYSTEM_CHECK_TM_QMU_RC_BASE (DPP_SYSTEM_CHECK_TM_RC_BASE | 0x900)
 
 /*system critical item check error code*/
-#define DPP_SERDES_CHECK_RC_BASE          (0x80000)
-#define DPP_SERDES_CHECK_PLL_BASE          (DPP_SERDES_CHECK_RC_BASE | 0x1000)
-#define DPP_SERDES_CHECK_PLL_A_BASE          (DPP_SERDES_CHECK_PLL_BASE | 0x100)
-#define DPP_SERDES_CHECK_PLL_B_BASE          (DPP_SERDES_CHECK_PLL_BASE | 0x200)
-#define DPP_SERDES_CHECK_PHYREADY_BASE     (DPP_SERDES_CHECK_RC_BASE | 0x2000)
-#define DPP_SERDES_CHECK_TX_PHYREADY_BASE    (DPP_SERDES_CHECK_PHYREADY_BASE | 0x100)
-#define DPP_SERDES_CHECK_RX_PHYREADY_BASE    (DPP_SERDES_CHECK_PHYREADY_BASE | 0x200)
-#define DPP_SERDES_CHECK_BERTOK_BASE     (DPP_SERDES_CHECK_RC_BASE | 0x3000)
+#define DPP_SERDES_CHECK_RC_BASE (0x80000)
+#define DPP_SERDES_CHECK_PLL_BASE (DPP_SERDES_CHECK_RC_BASE | 0x1000)
+#define DPP_SERDES_CHECK_PLL_A_BASE (DPP_SERDES_CHECK_PLL_BASE | 0x100)
+#define DPP_SERDES_CHECK_PLL_B_BASE (DPP_SERDES_CHECK_PLL_BASE | 0x200)
+#define DPP_SERDES_CHECK_PHYREADY_BASE (DPP_SERDES_CHECK_RC_BASE | 0x2000)
+#define DPP_SERDES_CHECK_TX_PHYREADY_BASE \
+	(DPP_SERDES_CHECK_PHYREADY_BASE | 0x100)
+#define DPP_SERDES_CHECK_RX_PHYREADY_BASE \
+	(DPP_SERDES_CHECK_PHYREADY_BASE | 0x200)
+#define DPP_SERDES_CHECK_BERTOK_BASE (DPP_SERDES_CHECK_RC_BASE | 0x3000)
 
 /*TM RAM检测项返回错误码定义*/
-#define DPP_TM_CHECK_RC_BASE          (0x100000)
-#define DPP_TM_CHECK_RAM_RC_BASE          (DPP_TM_CHECK_RC_BASE|0x100000)
-#define DPP_RC_TM_CRDT_INS_BUSY              (DPP_TM_CHECK_RC_BASE|0x100)
+#define DPP_TM_CHECK_RC_BASE (0x100000)
+#define DPP_TM_CHECK_RAM_RC_BASE (DPP_TM_CHECK_RC_BASE | 0x100000)
+#define DPP_RC_TM_CRDT_INS_BUSY (DPP_TM_CHECK_RC_BASE | 0x100)
 
 /*SAIP RAM检测项返回错误码定义*/
-#define DPP_SA_CHECK_RC_BASE          (0x110000)
-#define DPP_SA_CHECK_RAM_RC_BASE          (DPP_SA_CHECK_RC_BASE|0x110000)
+#define DPP_SA_CHECK_RC_BASE (0x110000)
+#define DPP_SA_CHECK_RAM_RC_BASE (DPP_SA_CHECK_RC_BASE | 0x110000)
 
 /*soft reset check error code*/
-#define DPP_SOFT_RESET_CHECK_BASE          (0x1300)
-#define DPP_SOFT_RESET_CHECK_WR_FAIL         (DPP_SOFT_RESET_CHECK_BASE | 0x0)
-#define DPP_SOFT_RESET_CHECK_RD_FAIL         (DPP_SOFT_RESET_CHECK_BASE | 0x1)
-#define DPP_SOFT_RESET_CHECK_WR_SIZE_ERR     (DPP_SOFT_RESET_CHECK_BASE | 0x2)
-#define DPP_SOFT_RESET_CHECK_RD_SIZE_ERR     (DPP_SOFT_RESET_CHECK_BASE | 0x3)
-#define DPP_SOFT_RESET_CHECK_BACKUP_ERR      (DPP_SOFT_RESET_CHECK_BASE | 0x4)
-
-//add by yinxh at 2018-1-15
-//soft interrupt check error code
-#define DPP_SOFT_INT_CHECK_BASE               (0x1400)
-#define DPP_SOFT_INT_CHECK_INVALID            (DPP_SOFT_INT_CHECK_BASE | 0x0)
-#define DPP_SOFT_INT_CHECK_NOT_INIT           (DPP_SOFT_INT_CHECK_BASE | 0x1)
-#define DPP_SOFT_INT_CHECK_SRH_FAIL           (DPP_SOFT_INT_CHECK_BASE | 0x2)
-#define DPP_SOFT_INT_CHECK_RB_TREE_FULL       (DPP_SOFT_INT_CHECK_BASE | 0x3)
-
+#define DPP_SOFT_RESET_CHECK_BASE (0x1300)
+#define DPP_SOFT_RESET_CHECK_WR_FAIL (DPP_SOFT_RESET_CHECK_BASE | 0x0)
+#define DPP_SOFT_RESET_CHECK_RD_FAIL (DPP_SOFT_RESET_CHECK_BASE | 0x1)
+#define DPP_SOFT_RESET_CHECK_WR_SIZE_ERR (DPP_SOFT_RESET_CHECK_BASE | 0x2)
+#define DPP_SOFT_RESET_CHECK_RD_SIZE_ERR (DPP_SOFT_RESET_CHECK_BASE | 0x3)
+#define DPP_SOFT_RESET_CHECK_BACKUP_ERR (DPP_SOFT_RESET_CHECK_BASE | 0x4)
+
+// add by yinxh at 2018-1-15
+// soft interrupt check error code
+#define DPP_SOFT_INT_CHECK_BASE (0x1400)
+#define DPP_SOFT_INT_CHECK_INVALID (DPP_SOFT_INT_CHECK_BASE | 0x0)
+#define DPP_SOFT_INT_CHECK_NOT_INIT (DPP_SOFT_INT_CHECK_BASE | 0x1)
+#define DPP_SOFT_INT_CHECK_SRH_FAIL (DPP_SOFT_INT_CHECK_BASE | 0x2)
+#define DPP_SOFT_INT_CHECK_RB_TREE_FULL (DPP_SOFT_INT_CHECK_BASE | 0x3)
 
 #ifdef __cplusplus
 }
 #endif
 
 #endif
-
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/chip/dpp_dev.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/chip/dpp_dev.h
old mode 100755
new mode 100644
index 7dd9990ad6fa4aedd4311ec2e08aa15a25c6aa8d..3924acee5c7cb846826557efad6df4b1a8e761ba
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/chip/dpp_dev.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/chip/dpp_dev.h
@@ -1,223 +1,228 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_dev.h
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : 王春雷
-* 完成日期 : 2014/02/10
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1: 代码规范性修改
-* 修改日期:  2014/02/10
-* 版 本 号:
-* 修 改 人:  丁金凤
-* 修改内容:
-***************************************************************/
-
-#ifndef _DPP_DEV_H_
-#define _DPP_DEV_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/pci.h>
-#include "zxic_common.h"
-#include "dpp_type_api.h"
-
-#define DPP_KEYSIG_DEBUG           (1)
-#define DPP_DEV_CHANNEL_MAX        (2)  /* 最多支持6个芯片 */
-#define DPP_DEV_PPU_CLS_MAX        (6)  /* 芯片支持4级cluster */
-#define DPP_DEV_PPU_INSTR_REG_NUM  (3)  /* 芯片支持4级cluster 共2个指令空间*/
-
-#define DPP_DEV_ME_MAX             (8)  /* 每级cluster支持8个me */
-#define DPP_DEV_SDT_ID_MAX         (256U)
-#define DPP_DTB_QUEUE_MAX          (128)
-
-#define DPP_CHIP_DPP               (0x279221)
-
-#define X86_ADDR_2_ARRCH64(X86_ADDR) (((X86_ADDR & (~0xFFFF)) << 4) | (X86_ADDR & 0xFFFF))
-
-#define DPP_PCIE_SLOT_MAX          (256)
-#define DPP_PCIE_CHANNEL_MAX       (128)
-#define DPP_PCIE_CHANNEL_ID(VPORT) (((VPORT & 0x7000) | (VPORT & 0x0700)) >> 8)
-
-#define DEV_ID(DEV)                (((DPP_DEV_T *)(DEV))->device_id)
-#define DEV_PCIE_SLOT(DEV)         (((DPP_DEV_T *)(DEV))->pcie_channel.slot)
-#define DEV_PCIE_VPORT(DEV)        (((DPP_DEV_T *)(DEV))->pcie_channel.vport)
-#define DEV_PCIE_DEV(DEV)          (((DPP_DEV_T *)(DEV))->pcie_channel.device)
-#define DEV_PCIE_ADDR(DEV)         (((DPP_DEV_T *)(DEV))->pcie_channel.base_addr)
-#define DEV_PCIE_OFFSET_ADDR(DEV)  (((DPP_DEV_T *)(DEV))->pcie_channel.offset_addr)
-#define DEV_PCIE_ID(DEV)           (((DPP_DEV_T *)(DEV))->pcie_channel.pcie_id)
-#define DEV_PCIE_MUTEX(DEV)        (((DPP_DEV_T *)(DEV))->pcie_channel.oper_mutex)
-
-#define DEV_PCIE_MSG_OFFSET_ADDR   (0x2000)
-#define DEV_PCIE_MSG_ADDR(DEV)     (DEV_PCIE_ADDR(DEV) + DEV_PCIE_MSG_OFFSET_ADDR)
-#define DEV_PCIE_REG_ADDR(DEV)     (DEV_PCIE_ADDR(DEV) + DEV_PCIE_OFFSET_ADDR(DEV) - SYS_NP_BASE_ADDR1)
-
-typedef struct dpp_pf_info_t
-{
-    ZXIC_UINT16 slot;
-    ZXIC_UINT16 vport;
-} DPP_PF_INFO_T;
-
-typedef struct dpp_pcie_channel_t
-{
-    ZXIC_UINT16 slot;
-    ZXIC_UINT16 vport;
-    ZXIC_UINT16 pcie_id;
-    ZXIC_ADDR_T base_addr;
-    ZXIC_ADDR_T offset_addr;
-    struct pci_dev* device;
-    ZXIC_MUTEX_T*   oper_mutex;
-} DPP_PCIE_CHANNEL_T;
-
-typedef struct dpp_dev_t
-{
-    ZXIC_UINT32 device_id;
-    DPP_PCIE_CHANNEL_T pcie_channel;
-} DPP_DEV_T;
-
-/**  底层设备硬件读写接口指针*/
-typedef DPP_STATUS (*DPP_DEV_WRITE_FUNC)(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data);
-typedef DPP_STATUS (*DPP_DEV_READ_FUNC)(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data);
-typedef DPP_STATUS (*DPP_ACCESS_SWITCH_FUNC)(ZXIC_UINT32 dev_id, ZXIC_UINT32 access_type);
-
-/**  设备访问类型*/
-typedef enum dpp_dev_access_type_e
-{
-    DPP_DEV_ACCESS_TYPE_PCIE = 0, /**<  @brief PCIe访问*/
-    DPP_DEV_ACCESS_TYPE_RISCV = 1, /**<  @brief RISCV访问*/
-} DPP_DEV_ACCESS_TYPE_E;
-
-/**  设备类型*/
-typedef enum dpp_dev_type_e
-{
-    DPP_DEV_TYPE_SIM  = 0,  /**<  @brief 仿真器设备*/
-    DPP_DEV_TYPE_VCS  = 1,  /**<  @brief VCS设备*/
-    DPP_DEV_TYPE_CHIP = 2,  /**<  @brief asci芯片设备*/
-    DPP_DEV_TYPE_FPGA = 3,  /**<  @brief fpga设备*/
-    DPP_DEV_TYPE_PCIE_ACC = 4,
-    DPP_DEV_TYPE_INVALID,
-} DPP_DEV_TYPE_E;
-
-/**  设备版本*/
-typedef enum dpp_chip_version_e
-{
-    DPP_CHIP_VERSION_DPP   = 0U,  /**<  @brief DPP */
-    DPP_CHIP_VERSION_DPP_P = 1U,  /**<  @brief DPP+ */
-    DPP_CHIP_VERSION_INVALID,
-} DPP_CHIP_VERSION_E;
-
-/**  互斥锁类型*/
-typedef enum dpp_dev_mutex_type_e
-{
-    DPP_DEV_MUTEX_T_REG   = 0,  /**<  @brief 寄存器操作互斥锁       */
-    DPP_DEV_MUTEX_T_OAM   = 1,  /**<  @brief OAM模块操作互斥锁      */
-    DPP_DEV_MUTEX_T_ETM   = 2,  /**<  @brief ETM模块操作互斥锁       */
-    DPP_DEV_MUTEX_T_DDR   = 4,  /**<  @brief DDR模块操作互斥锁      */
-    DPP_DEV_MUTEX_T_IND   = 5,  /**<  @brief RAM间接读写操作互斥锁  */
-    DPP_DEV_MUTEX_T_ETCAM = 6,  /**<  @brief ETCAM间接读写操作互斥锁*/
-    DPP_DEV_MUTEX_T_MMU   = 7,  /**<  @brief MMU间接读写操作互斥锁  */
-    DPP_DEV_MUTEX_T_CAR0  = 8,  /**<  @brief CAR0模块操作互斥锁     */
-    DPP_DEV_MUTEX_T_ALG       = 9, /**<  @brief ALG间接读写操作互斥锁  */
-    DPP_DEV_MUTEX_T_NPPU      = 10, /**<  @brief nppu间接读写操作互斥锁  */
-    DPP_DEV_MUTEX_T_SMMU0     = 11, /**<  @brief smmu0 模块操作互斥锁  */
-    DPP_DEV_MUTEX_T_SMMU1     = 12, /**<  @brief smmu1 模块操作互斥锁  */
-    DPP_DEV_MUTEX_T_ETM_2ND   = 13, /**<  @brief ETM模块二层间接表操作互斥锁 */
-    DPP_DEV_MUTEX_T_LPM       = 14, /**<  @brief LPM模块操作互斥锁 */
-    DPP_DEV_MUTEX_T_CRM_TEMP  = 15, /**<  @brief 温度获取操作互斥锁 */
-    DPP_DEV_MUTEX_T_SIM       = 16, /**<  @brief 仿真器socket通信操作互斥锁 */
-    DPP_DEV_MUTEX_T_DTB       = 17, /**<  @brief DTB队列操作互斥锁 */
-    DPP_DEV_MUTEX_T_MAX
-} DPP_DEV_MUTEX_TYPE_E;
-
-typedef enum module_init_e
-{
-    MODULE_INIT_NPPU = 0,  /**<  @brief 01:pktrx  0x2:pbu  0x4:odma*/
-    MODULE_INIT_PPU,
-    MODULE_INIT_SE,    /**<  @brief corresponding bits indicacte SE submodule, 0:smmu0 1:smmu1 2:alg 3:as 4:etcam 5:stat 6:reg_fifo 31:SE_init_done*/
-    MODULE_INIT_ETM,   /**<  @brief bit31:tm  bit0:olif  bit1:cgavd  bit2:tmmu  bit3:shap  bit4:crdt  bit5:qmu */
-    MODULE_INIT_DLB,   
-    MODULE_INIT_TRPG,   
-    MODULE_INIT_TSN,   
-    MODULE_INIT_MAX
-} MODULE_INIT_E;
-
-typedef struct dpp_dev_cfg_t
-{
-    ZXIC_UINT32 device_id;           /* 设备号 */
-    DPP_DEV_TYPE_E dev_type;    /* 设备类型: 0-SIM, 1-VCS, 2-CHIP(ASIC), 3-FPGA. */
-    ZXIC_UINT32 chip_ver;            /* 设备类型: 0-DPP, 1-DPP+ */
-    ZXIC_UINT32 access_type;         /* 访问类型: 0-PCIe, 1-RISCV. */
-    ZXIC_ADDR_T pcie_addr;           /* PCIe映射地址 */
-    ZXIC_ADDR_T riscv_addr;           /* RISCV映射地址 */
-    ZXIC_ADDR_T dma_vir_addr;        /* DMA空间映射地址 */
-    ZXIC_ADDR_T dma_phy_addr;        /* 芯片地址相对偏移 */
-    ZXIC_UINT32 init_flags[MODULE_INIT_MAX];
-    DPP_DEV_WRITE_FUNC p_pcie_write_fun;  /**  PCIe硬件写回调函数 */
-    DPP_DEV_READ_FUNC  p_pcie_read_fun;   /**  PCIe硬件读回调函数 */
-    DPP_DEV_WRITE_FUNC p_riscv_write_fun;  /**  RISCV硬件写回调函数 */
-    DPP_DEV_READ_FUNC  p_riscv_read_fun;   /**  RISCV硬件读回调函数 */  
-    ZXIC_MUTEX_T    reg_opr_mutex;     /**  寄存器操作互斥量 */
-    ZXIC_MUTEX_T    oam_mutex;         /**  OAM硬件操作互斥锁  */
-    ZXIC_MUTEX_T    etm_mutex;         /**  ETM硬件操作互斥锁   */
-    ZXIC_MUTEX_T    ddr_mutex;         /**  DDR硬件操作互斥锁  */
-    ZXIC_MUTEX_T    ind_mutex;         /**  RAM间接操作互斥锁  */
-    ZXIC_MUTEX_T    etcam_mutex;       /**  ETCAM硬件操作互斥锁 */
-    ZXIC_MUTEX_T    car0_mutex;        /**  CAR0硬件操作互斥锁 */
-    ZXIC_MUTEX_T    alg_mutex;         /**  alg硬件操作互斥锁*/
-    ZXIC_MUTEX_T    nppu_mutex;        /**  nppu硬件操作互斥锁*/
-    ZXIC_MUTEX_T    smmu0_mutex;         /**  smmu0 硬件操作互斥锁*/
-    ZXIC_MUTEX_T    smmu1_mutex;         /**  smmu1 硬件操作互斥锁*/
-    ZXIC_MUTEX_T    etm_2nd_mutex;       /**  ETM 二层间接表 硬件操作互斥锁*/
-    ZXIC_MUTEX_T    lpm_mutex;           /**  lpm配置 操作互斥锁*/
-    ZXIC_MUTEX_T    crm_temp_mutex;      /**  温度获取 操作互斥锁*/
-    ZXIC_MUTEX_T    sim_mutex;           /**  仿真器socket通信 操作互斥锁*/
-    ZXIC_MUTEX_T    dtb_mutex;           /** DTB操作互斥锁*/
-    ZXIC_MUTEX_T    dtb_queue_mutex[DPP_DTB_QUEUE_MAX];   /* DTB模块队列操作互斥锁 */
-    DPP_PCIE_CHANNEL_T pcie_channel[DPP_PCIE_SLOT_MAX][DPP_PCIE_CHANNEL_MAX];
-} DPP_DEV_CFG_T;
-
-typedef struct dpp_dev_mngr_t
-{
-    ZXIC_UINT32         device_num;  /* 设备数目 */
-    ZXIC_UINT32         is_init;
-    DPP_DEV_CFG_T  *p_dev_array[DPP_DEV_CHANNEL_MAX];
-} DPP_DEV_MGR_T;
-
-DPP_STATUS dpp_dev_init(ZXIC_VOID);
-DPP_STATUS dpp_dev_add(ZXIC_UINT32  dev_id,
-                       DPP_DEV_TYPE_E dev_type,
-                       DPP_DEV_ACCESS_TYPE_E  access_type,
-                       ZXIC_ADDR_T  pcie_addr,
-                       ZXIC_ADDR_T  riscv_addr,
-                       ZXIC_ADDR_T  dma_vir_addr,
-                       ZXIC_ADDR_T  dma_phy_addr,
-                       DPP_DEV_WRITE_FUNC p_pcie_write_fun,
-                       DPP_DEV_READ_FUNC  p_pcie_read_fun,
-                       DPP_DEV_WRITE_FUNC p_riscv_write_fun,
-                       DPP_DEV_READ_FUNC  p_riscv_read_fun);
-DPP_STATUS dpp_dev_del(ZXIC_UINT32 dev_id);
-DPP_STATUS dpp_dev_get(ZXIC_UINT32 dev_id, DPP_PF_INFO_T* pf_info, DPP_DEV_T *dev);
-DPP_STATUS dpp_dev_pcie_channel_add(ZXIC_UINT32 dev_id, DPP_PF_INFO_T* pf_info, struct pci_dev* p_dev);
-DPP_STATUS dpp_dev_pcie_channel_del(ZXIC_UINT32 dev_id, DPP_PF_INFO_T* pf_info);
-ZXIC_UINT32 dpp_dev_get_dev_type(ZXIC_UINT32 dev_id);
-ZXIC_UINT32 dpp_dev_chip_version_get(ZXIC_UINT32 dev_id);
-DPP_STATUS dpp_dev_init_flag_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 flag);
-DPP_STATUS dpp_dev_init_flag_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 *p_flag);
-DPP_STATUS dpp_dev_opr_mutex_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 type, ZXIC_MUTEX_T **p_mutex_out);
-DPP_STATUS dpp_dev_dtb_opr_mutex_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 type, ZXIC_UINT32 index, ZXIC_MUTEX_T **p_mutex_out);
-DPP_STATUS dpp_dev_pcie_default_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data);
-DPP_STATUS dpp_dev_pcie_default_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data);
-DPP_STATUS dpp_dev_write_channel(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data);
-DPP_STATUS dpp_dev_read_channel(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_dev.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2014/02/10
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1: 代码规范性修改
+* 修改日期:  2014/02/10
+* 版 本 号:
+* 修 改 人:  丁金凤
+* 修改内容:
+***************************************************************/
+
+#ifndef _DPP_DEV_H_
+#define _DPP_DEV_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/pci.h>
+#include "zxic_common.h"
+#include "dpp_type_api.h"
+
+#define DPP_KEYSIG_DEBUG (1)
+#define DPP_DEV_CHANNEL_MAX (2) /* 最多支持6个芯片 */
+#define DPP_DEV_PPU_CLS_MAX (6) /* 芯片支持4级cluster */
+#define DPP_DEV_PPU_INSTR_REG_NUM (3) /* 芯片支持4级cluster 共2个指令空间*/
+
+#define DPP_DEV_ME_MAX (8) /* 每级cluster支持8个me */
+#define DPP_DEV_SDT_ID_MAX (256U)
+#define DPP_DTB_QUEUE_MAX (128)
+
+#define DPP_CHIP_DPP (0x279221)
+
+#define X86_ADDR_2_ARRCH64(X86_ADDR) \
+	(((X86_ADDR & (~0xFFFF)) << 4) | (X86_ADDR & 0xFFFF))
+
+#define DPP_PCIE_SLOT_MAX (256)
+#define DPP_PCIE_CHANNEL_MAX (128)
+#define DPP_PCIE_CHANNEL_ID(VPORT) (((VPORT & 0x7000) | (VPORT & 0x0700)) >> 8)
+
+#define DEV_ID(DEV) (((DPP_DEV_T *)(DEV))->device_id)
+#define DEV_PCIE_SLOT(DEV) (((DPP_DEV_T *)(DEV))->pcie_channel.slot)
+#define DEV_PCIE_VPORT(DEV) (((DPP_DEV_T *)(DEV))->pcie_channel.vport)
+#define DEV_PCIE_DEV(DEV) (((DPP_DEV_T *)(DEV))->pcie_channel.device)
+#define DEV_PCIE_ADDR(DEV) (((DPP_DEV_T *)(DEV))->pcie_channel.base_addr)
+#define DEV_PCIE_OFFSET_ADDR(DEV) \
+	(((DPP_DEV_T *)(DEV))->pcie_channel.offset_addr)
+#define DEV_PCIE_ID(DEV) (((DPP_DEV_T *)(DEV))->pcie_channel.pcie_id)
+#define DEV_PCIE_MUTEX(DEV) (((DPP_DEV_T *)(DEV))->pcie_channel.oper_mutex)
+
+#define DEV_PCIE_MSG_OFFSET_ADDR (0x2000)
+#define DEV_PCIE_MSG_ADDR(DEV) (DEV_PCIE_ADDR(DEV) + DEV_PCIE_MSG_OFFSET_ADDR)
+#define DEV_PCIE_REG_ADDR(DEV) \
+	(DEV_PCIE_ADDR(DEV) + DEV_PCIE_OFFSET_ADDR(DEV) - SYS_NP_BASE_ADDR1)
+
+typedef struct dpp_pf_info_t {
+	ZXIC_UINT16 slot;
+	ZXIC_UINT16 vport;
+} DPP_PF_INFO_T;
+
+typedef struct dpp_pcie_channel_t {
+	ZXIC_UINT16 slot;
+	ZXIC_UINT16 vport;
+	ZXIC_UINT16 pcie_id;
+	ZXIC_ADDR_T base_addr;
+	ZXIC_ADDR_T offset_addr;
+	struct pci_dev *device;
+	ZXIC_MUTEX_T *oper_mutex;
+} DPP_PCIE_CHANNEL_T;
+
+typedef struct dpp_dev_t {
+	ZXIC_UINT32 device_id;
+	DPP_PCIE_CHANNEL_T pcie_channel;
+} DPP_DEV_T;
+
+/**  底层设备硬件读写接口指针*/
+typedef DPP_STATUS (*DPP_DEV_WRITE_FUNC)(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+										 ZXIC_UINT32 size, ZXIC_UINT32 *p_data);
+typedef DPP_STATUS (*DPP_DEV_READ_FUNC)(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+										ZXIC_UINT32 size, ZXIC_UINT32 *p_data);
+typedef DPP_STATUS (*DPP_ACCESS_SWITCH_FUNC)(ZXIC_UINT32 dev_id,
+											 ZXIC_UINT32 access_type);
+
+/**  设备访问类型*/
+typedef enum dpp_dev_access_type_e {
+	DPP_DEV_ACCESS_TYPE_PCIE = 0, /**<  @brief PCIe访问*/
+	DPP_DEV_ACCESS_TYPE_RISCV = 1, /**<  @brief RISCV访问*/
+} DPP_DEV_ACCESS_TYPE_E;
+
+/**  设备类型*/
+typedef enum dpp_dev_type_e {
+	DPP_DEV_TYPE_SIM = 0, /**<  @brief 仿真器设备*/
+	DPP_DEV_TYPE_VCS = 1, /**<  @brief VCS设备*/
+	DPP_DEV_TYPE_CHIP = 2, /**<  @brief asci芯片设备*/
+	DPP_DEV_TYPE_FPGA = 3, /**<  @brief fpga设备*/
+	DPP_DEV_TYPE_PCIE_ACC = 4,
+	DPP_DEV_TYPE_INVALID,
+} DPP_DEV_TYPE_E;
+
+/**  设备版本*/
+typedef enum dpp_chip_version_e {
+	DPP_CHIP_VERSION_DPP = 0U, /**<  @brief DPP */
+	DPP_CHIP_VERSION_DPP_P = 1U, /**<  @brief DPP+ */
+	DPP_CHIP_VERSION_INVALID,
+} DPP_CHIP_VERSION_E;
+
+/**  互斥锁类型*/
+typedef enum dpp_dev_mutex_type_e {
+	DPP_DEV_MUTEX_T_REG = 0, /**<  @brief 寄存器操作互斥锁       */
+	DPP_DEV_MUTEX_T_OAM = 1, /**<  @brief OAM模块操作互斥锁      */
+	DPP_DEV_MUTEX_T_ETM = 2, /**<  @brief ETM模块操作互斥锁       */
+	DPP_DEV_MUTEX_T_DDR = 4, /**<  @brief DDR模块操作互斥锁      */
+	DPP_DEV_MUTEX_T_IND = 5, /**<  @brief RAM间接读写操作互斥锁  */
+	DPP_DEV_MUTEX_T_ETCAM = 6, /**<  @brief ETCAM间接读写操作互斥锁*/
+	DPP_DEV_MUTEX_T_MMU = 7, /**<  @brief MMU间接读写操作互斥锁  */
+	DPP_DEV_MUTEX_T_CAR0 = 8, /**<  @brief CAR0模块操作互斥锁     */
+	DPP_DEV_MUTEX_T_ALG = 9, /**<  @brief ALG间接读写操作互斥锁  */
+	DPP_DEV_MUTEX_T_NPPU = 10, /**<  @brief nppu间接读写操作互斥锁  */
+	DPP_DEV_MUTEX_T_SMMU0 = 11, /**<  @brief smmu0 模块操作互斥锁  */
+	DPP_DEV_MUTEX_T_SMMU1 = 12, /**<  @brief smmu1 模块操作互斥锁  */
+	DPP_DEV_MUTEX_T_ETM_2ND = 13, /**<  @brief ETM模块二层间接表操作互斥锁 */
+	DPP_DEV_MUTEX_T_LPM = 14, /**<  @brief LPM模块操作互斥锁 */
+	DPP_DEV_MUTEX_T_CRM_TEMP = 15, /**<  @brief 温度获取操作互斥锁 */
+	DPP_DEV_MUTEX_T_SIM = 16, /**<  @brief 仿真器socket通信操作互斥锁 */
+	DPP_DEV_MUTEX_T_DTB = 17, /**<  @brief DTB队列操作互斥锁 */
+	DPP_DEV_MUTEX_T_MAX
+} DPP_DEV_MUTEX_TYPE_E;
+
+typedef enum module_init_e {
+	MODULE_INIT_NPPU = 0, /**<  @brief 01:pktrx  0x2:pbu  0x4:odma*/
+	MODULE_INIT_PPU,
+	MODULE_INIT_SE, /**<  @brief corresponding bits indicacte SE submodule, 0:smmu0 1:smmu1 2:alg 3:as 4:etcam
+	5:stat 6:reg_fifo 31:SE_init_done*/
+	MODULE_INIT_ETM, /**<  @brief bit31:tm  bit0:olif  bit1:cgavd  bit2:tmmu  bit3:shap  bit4:crdt  bit5:qmu */
+	MODULE_INIT_DLB,
+	MODULE_INIT_TRPG,
+	MODULE_INIT_TSN,
+	MODULE_INIT_MAX
+} MODULE_INIT_E;
+
+typedef struct dpp_dev_cfg_t {
+	ZXIC_UINT32 device_id; /* 设备号 */
+	DPP_DEV_TYPE_E dev_type; /* 设备类型: 0-SIM, 1-VCS, 2-CHIP(ASIC), 3-FPGA. */
+	ZXIC_UINT32 chip_ver; /* 设备类型: 0-DPP, 1-DPP+ */
+	ZXIC_UINT32 access_type; /* 访问类型: 0-PCIe, 1-RISCV. */
+	ZXIC_ADDR_T pcie_addr; /* PCIe映射地址 */
+	ZXIC_ADDR_T riscv_addr; /* RISCV映射地址 */
+	ZXIC_ADDR_T dma_vir_addr; /* DMA空间映射地址 */
+	ZXIC_ADDR_T dma_phy_addr; /* 芯片地址相对偏移 */
+	ZXIC_UINT32 init_flags[MODULE_INIT_MAX];
+	DPP_DEV_WRITE_FUNC p_pcie_write_fun; /**  PCIe硬件写回调函数 */
+	DPP_DEV_READ_FUNC p_pcie_read_fun; /**  PCIe硬件读回调函数 */
+	DPP_DEV_WRITE_FUNC p_riscv_write_fun; /**  RISCV硬件写回调函数 */
+	DPP_DEV_READ_FUNC p_riscv_read_fun; /**  RISCV硬件读回调函数 */
+	ZXIC_MUTEX_T reg_opr_mutex; /**  寄存器操作互斥量 */
+	ZXIC_MUTEX_T oam_mutex; /**  OAM硬件操作互斥锁  */
+	ZXIC_MUTEX_T etm_mutex; /**  ETM硬件操作互斥锁   */
+	ZXIC_MUTEX_T ddr_mutex; /**  DDR硬件操作互斥锁  */
+	ZXIC_MUTEX_T ind_mutex; /**  RAM间接操作互斥锁  */
+	ZXIC_MUTEX_T etcam_mutex; /**  ETCAM硬件操作互斥锁 */
+	ZXIC_MUTEX_T car0_mutex; /**  CAR0硬件操作互斥锁 */
+	ZXIC_MUTEX_T alg_mutex; /**  alg硬件操作互斥锁*/
+	ZXIC_MUTEX_T nppu_mutex; /**  nppu硬件操作互斥锁*/
+	ZXIC_MUTEX_T smmu0_mutex; /**  smmu0 硬件操作互斥锁*/
+	ZXIC_MUTEX_T smmu1_mutex; /**  smmu1 硬件操作互斥锁*/
+	ZXIC_MUTEX_T etm_2nd_mutex; /**  ETM 二层间接表 硬件操作互斥锁*/
+	ZXIC_MUTEX_T lpm_mutex; /**  lpm配置 操作互斥锁*/
+	ZXIC_MUTEX_T crm_temp_mutex; /**  温度获取 操作互斥锁*/
+	ZXIC_MUTEX_T sim_mutex; /**  仿真器socket通信 操作互斥锁*/
+	ZXIC_MUTEX_T dtb_mutex; /** DTB操作互斥锁*/
+	ZXIC_MUTEX_T dtb_queue_mutex[DPP_DTB_QUEUE_MAX]; /* DTB模块队列操作互斥锁 */
+	DPP_PCIE_CHANNEL_T pcie_channel[DPP_PCIE_SLOT_MAX][DPP_PCIE_CHANNEL_MAX];
+} DPP_DEV_CFG_T;
+
+typedef struct dpp_dev_mngr_t {
+	ZXIC_UINT32 device_num; /* 设备数目 */
+	ZXIC_UINT32 is_init;
+	DPP_DEV_CFG_T * p_dev_array[DPP_DEV_CHANNEL_MAX];
+} DPP_DEV_MGR_T;
+
+DPP_STATUS dpp_dev_init(ZXIC_VOID);
+DPP_STATUS dpp_dev_add(ZXIC_UINT32 dev_id, DPP_DEV_TYPE_E dev_type,
+					   DPP_DEV_ACCESS_TYPE_E access_type, ZXIC_ADDR_T pcie_addr,
+					   ZXIC_ADDR_T riscv_addr, ZXIC_ADDR_T dma_vir_addr,
+					   ZXIC_ADDR_T dma_phy_addr,
+					   DPP_DEV_WRITE_FUNC p_pcie_write_fun,
+					   DPP_DEV_READ_FUNC p_pcie_read_fun,
+					   DPP_DEV_WRITE_FUNC p_riscv_write_fun,
+					   DPP_DEV_READ_FUNC p_riscv_read_fun);
+DPP_STATUS dpp_dev_del(ZXIC_UINT32 dev_id);
+DPP_STATUS dpp_dev_get(ZXIC_UINT32 dev_id, DPP_PF_INFO_T *pf_info,
+					   DPP_DEV_T *dev);
+DPP_STATUS dpp_dev_pcie_channel_add(ZXIC_UINT32 dev_id, DPP_PF_INFO_T *pf_info,
+									struct pci_dev *p_dev);
+DPP_STATUS dpp_dev_pcie_channel_del(ZXIC_UINT32 dev_id, DPP_PF_INFO_T *pf_info);
+ZXIC_UINT32 dpp_dev_get_dev_type(ZXIC_UINT32 dev_id);
+ZXIC_UINT32 dpp_dev_chip_version_get(ZXIC_UINT32 dev_id);
+DPP_STATUS dpp_dev_init_flag_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id,
+								 ZXIC_UINT32 flag);
+DPP_STATUS dpp_dev_init_flag_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id,
+								 ZXIC_UINT32 *p_flag);
+DPP_STATUS dpp_dev_opr_mutex_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 type,
+								 ZXIC_MUTEX_T **p_mutex_out);
+DPP_STATUS dpp_dev_dtb_opr_mutex_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 type,
+									 ZXIC_UINT32 index,
+									 ZXIC_MUTEX_T **p_mutex_out);
+DPP_STATUS dpp_dev_pcie_default_write(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+									  ZXIC_UINT32 size, ZXIC_UINT32 *p_data);
+DPP_STATUS dpp_dev_pcie_default_read(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+									 ZXIC_UINT32 size, ZXIC_UINT32 *p_data);
+DPP_STATUS dpp_dev_write_channel(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+								 ZXIC_UINT32 size, ZXIC_UINT32 *p_data);
+DPP_STATUS dpp_dev_read_channel(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+								ZXIC_UINT32 size, ZXIC_UINT32 *p_data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/chip/dpp_init.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/chip/dpp_init.h
old mode 100755
new mode 100644
index c959437be7d868b7cce618fbc96baf074559156b..34f92a97727377045e82c0af840eeeab4bb1ef70
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/chip/dpp_init.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/chip/dpp_init.h
@@ -1,66 +1,79 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_init.h
-* 文件标识 :
-* 内容摘要 : 芯片初始化头文件
-* 其它说明 :
-* 当前版本 :
-* 作    者 : wcl
-* 完成日期 : 2015/03/17
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-#ifndef _DPP_INIT_H_
-#define _DPP_INIT_H_
-
-/**  系统初始化标志*/
-#define DPP_INIT_FLAG_ACCESS_TYPE      (1<<0)  /**<  @brief 访问模式: 0-PCRISCV1-MDIO*/
-#define DPP_INIT_FLAG_SERDES_DOWN_TP   (1<<1)  /**<  @brief serdes加载方式:  0-组播，1-单播*/
-#define DPP_INIT_FLAG_DDR_BACKDOOR     (1<<2)  /**<  @brief DDR3校准:  0-校准，1-不校准*/
-#define DPP_INIT_FLAG_SA_MODE          (1<<3)  /**<  @brief SA工作模式: 0-内置sa，1-非SA模式*/
-#define DPP_INIT_FLAG_SA_MESH          (1<<4)  /**<  @brief SA mesh模式: 0-非mesh，1-mesh*/
-#define DPP_INIT_FLAG_SA_SERDES_MODE   (1<<5)  /**<  @brief SA serdes编码方式: 0-64B/66B; 1-8B/10B */
-#define DPP_INIT_FLAG_INT_DEST_MODE    (1<<6)  /**<  @brief 中断上报方式: 0-PCIe; 1-LocalBus(管脚)*/
-#define DPP_INIT_FLAG_LIF0_MODE        (1<<7)  /**<  @brief 0: PON模式 1: QSGMII模式*/
-#define DPP_INIT_FLAG_DMA_ENABLE       (1<<8)  /**<  @brief DMA使能:  0-使能，1-不使能*/
-#define DPP_INIT_FLAG_TM_IMEM_FLAG     (1<<9)  /**<  @brief TM片内外模式:  0-片外，1-片内*/
-
-/**  dpp sdk系统初始化控制结构*/
-typedef struct dpp_sys_init_ctrl_t
-{
-    DPP_DEV_TYPE_E device_type;         /**<  @brief 设备类型，取值参考DPP_DEV_TYPE_E的定义*/
-    ZXIC_UINT32 flags;                       /**<  @brief 初始化标志，按bitmap使用，*/
-    ZXIC_UINT32 sa_id;                       /**<  @brief 内置sa模式下，sa的ID，范围0~127*/
-    ZXIC_UINT32 case_num;                    /**<  @brief TM四组QMU初始化场景编号为1-8;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8.*/
-    ZXIC_UINT32 lif0_port_type;              /**<  @brief LIF0是PON口模式下，lif0的PON端口类型，详见DPP_LIF0_PON_TYPE_E */
-    ZXIC_UINT32 lif1_port_type;              /**<  @brief 非内置SA模式下，lif1的端口类型，详见DPP_LIF1_PORT_MODE_E */
-    ZXIC_ADDR_T pcie_vir_baddr;              /**<  @brief PCIe映射虚拟基地址*/
-    ZXIC_ADDR_T riscv_vir_baddr;              /**<  @brief RISCV映射虚拟基地址 */
-    ZXIC_ADDR_T dma_vir_baddr;               /**<  @brief DMA映射虚拟地址*/
-    ZXIC_ADDR_T dma_phy_baddr;               /**<  @brief DMA内存物理地址*/
-    DPP_DEV_WRITE_FUNC pcie_write_fun;  /**<  @brief PCIe硬件写回调函数 */
-    DPP_DEV_READ_FUNC  pcie_read_fun;   /**<  @brief PCIe硬件读回调函数*/
-    DPP_DEV_WRITE_FUNC riscv_write_fun;  /**<  @brief RISCV硬件写回调函数 */
-    DPP_DEV_READ_FUNC  riscv_read_fun;   /**<  @brief RISCV硬件读回调函数*/
-    DPP_ACCESS_SWITCH_FUNC access_switch_fun; /**<  @brief PCIe/RISCV切换回调函数*/
-} DPP_SYS_INIT_CTRL_T;
-
-/***********************************************************/
-/** 芯片上电初始，完整版本
-* @param   dev_id    设备号
-* @param   p_init_ctrl  系统初始化控制数据结构，由用户完成实例化和成员赋值
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wcl      @date  2015/03/26
-************************************************************/
-DPP_STATUS dpp_init(ZXIC_UINT32 dev_id, DPP_SYS_INIT_CTRL_T *p_init_ctrl);
-
-#endif /* dpp_init.h */
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_init.h
+* 文件标识 :
+* 内容摘要 : 芯片初始化头文件
+* 其它说明 :
+* 当前版本 :
+* 作    者 : wcl
+* 完成日期 : 2015/03/17
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#ifndef _DPP_INIT_H_
+#define _DPP_INIT_H_
+
+/**  系统初始化标志*/
+#define DPP_INIT_FLAG_ACCESS_TYPE \
+	(1 << 0) /**<  @brief 访问模式: 0-PCRISCV1-MDIO*/
+#define DPP_INIT_FLAG_SERDES_DOWN_TP \
+	(1 << 1) /**<  @brief serdes加载方式:  0-组播，1-单播*/
+#define DPP_INIT_FLAG_DDR_BACKDOOR \
+	(1 << 2) /**<  @brief DDR3校准:  0-校准，1-不校准*/
+#define DPP_INIT_FLAG_SA_MODE \
+	(1 << 3) /**<  @brief SA工作模式: 0-内置sa，1-非SA模式*/
+#define DPP_INIT_FLAG_SA_MESH \
+	(1 << 4) /**<  @brief SA mesh模式: 0-非mesh，1-mesh*/
+#define DPP_INIT_FLAG_SA_SERDES_MODE \
+	(1 << 5) /**<  @brief SA serdes编码方式: 0-64B/66B; 1-8B/10B */
+#define DPP_INIT_FLAG_INT_DEST_MODE \
+	(1 << 6) /**<  @brief 中断上报方式: 0-PCIe; 1-LocalBus(管脚)*/
+#define DPP_INIT_FLAG_LIF0_MODE (1 << 7) /**<  @brief 0: PON模式 1: QSGMII模式*/
+#define DPP_INIT_FLAG_DMA_ENABLE \
+	(1 << 8) /**<  @brief DMA使能:  0-使能，1-不使能*/
+#define DPP_INIT_FLAG_TM_IMEM_FLAG \
+	(1 << 9) /**<  @brief TM片内外模式:  0-片外，1-片内*/
+
+/**  dpp sdk系统初始化控制结构*/
+typedef struct dpp_sys_init_ctrl_t {
+	DPP_DEV_TYPE_E
+	device_type; /**<  @brief 设备类型，取值参考DPP_DEV_TYPE_E的定义*/
+	ZXIC_UINT32 flags; /**<  @brief 初始化标志，按bitmap使用，*/
+	ZXIC_UINT32 sa_id; /**<  @brief 内置sa模式下，sa的ID，范围0~127*/
+	ZXIC_UINT32
+	case_num; /**<  @brief TM四组QMU初始化场景编号为1-8;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8.*/
+	ZXIC_UINT32
+	lif0_port_type; /**<  @brief LIF0是PON口模式下，lif0的PON端口类型，详见DPP_LIF0_PON_TYPE_E */
+	ZXIC_UINT32
+	lif1_port_type; /**<  @brief 非内置SA模式下，lif1的端口类型，详见DPP_LIF1_PORT_MODE_E */
+	ZXIC_ADDR_T pcie_vir_baddr; /**<  @brief PCIe映射虚拟基地址*/
+	ZXIC_ADDR_T riscv_vir_baddr; /**<  @brief RISCV映射虚拟基地址 */
+	ZXIC_ADDR_T dma_vir_baddr; /**<  @brief DMA映射虚拟地址*/
+	ZXIC_ADDR_T dma_phy_baddr; /**<  @brief DMA内存物理地址*/
+	DPP_DEV_WRITE_FUNC pcie_write_fun; /**<  @brief PCIe硬件写回调函数 */
+	DPP_DEV_READ_FUNC pcie_read_fun; /**<  @brief PCIe硬件读回调函数*/
+	DPP_DEV_WRITE_FUNC riscv_write_fun; /**<  @brief RISCV硬件写回调函数 */
+	DPP_DEV_READ_FUNC riscv_read_fun; /**<  @brief RISCV硬件读回调函数*/
+	DPP_ACCESS_SWITCH_FUNC
+	access_switch_fun; /**<  @brief PCIe/RISCV切换回调函数*/
+} DPP_SYS_INIT_CTRL_T;
+
+/***********************************************************/
+/** 芯片上电初始，完整版本
+ * @param   dev_id    设备号
+ * @param   p_init_ctrl  系统初始化控制数据结构，由用户完成实例化和成员赋值
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/03/26
+ ************************************************************/
+DPP_STATUS dpp_init(ZXIC_UINT32 dev_id, DPP_SYS_INIT_CTRL_T *p_init_ctrl);
+
+#endif /* dpp_init.h */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/init/dpp_kernel_init.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/init/dpp_kernel_init.h
index c989094f19babd26a9666f87b10399f2c68e4279..47b15db755b94712d815b95f21c246acdb946493 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/init/dpp_kernel_init.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/init/dpp_kernel_init.h
@@ -1,19 +1,19 @@
-#ifndef _DPP_KERNEL_INIT_H_
-#define _DPP_KERNEL_INIT_H_
-
-#include "zxic_common.h"
-#include "dpp_dtb_table_api.h"
-
-ZXIC_SINT32 dpp_dtb_queue_dma_mem_alloc(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 size);
-ZXIC_SINT32 dpp_dtb_queue_dma_mem_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, DTB_QUEUE_DMA_ADDR_INFO *dmaAddrInfo);
-ZXIC_SINT32 dpp_dtb_queue_dma_mem_release(DPP_DEV_T *dev, ZXIC_UINT32 queue_id);
-ZXIC_SINT32 dtb_sdt_dump_dma_alloc(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 dma_size, 
-                                   ZXIC_UINT64 * p_dma_phy_addr, 
-                                   ZXIC_UINT64 * p_dma_vir_addr);
-
-ZXIC_SINT32 dtb_sdt_dump_dma_release(DPP_DEV_T *dev,
-                            ZXIC_UINT32 dma_size, 
-                            ZXIC_UINT64 dma_phy_addr, 
-                            ZXIC_UINT64 dma_vir_addr);
-#endif
+#ifndef _DPP_KERNEL_INIT_H_
+#define _DPP_KERNEL_INIT_H_
+
+#include "zxic_common.h"
+#include "dpp_dtb_table_api.h"
+
+ZXIC_SINT32 dpp_dtb_queue_dma_mem_alloc(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+										ZXIC_UINT32 size);
+ZXIC_SINT32 dpp_dtb_queue_dma_mem_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									  DTB_QUEUE_DMA_ADDR_INFO *dmaAddrInfo);
+ZXIC_SINT32 dpp_dtb_queue_dma_mem_release(DPP_DEV_T *dev, ZXIC_UINT32 queue_id);
+ZXIC_SINT32 dtb_sdt_dump_dma_alloc(DPP_DEV_T *dev, ZXIC_UINT32 dma_size,
+								   ZXIC_UINT64 *p_dma_phy_addr,
+								   ZXIC_UINT64 *p_dma_vir_addr);
+
+ZXIC_SINT32 dtb_sdt_dump_dma_release(DPP_DEV_T *dev, ZXIC_UINT32 dma_size,
+									 ZXIC_UINT64 dma_phy_addr,
+									 ZXIC_UINT64 dma_vir_addr);
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/dma/dpp_dtb.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/dma/dpp_dtb.h
old mode 100755
new mode 100644
index e40be249e8076aa7ababf35e0fb5208fdd028c3a..bf5eb6c2d327c957117e76890ae437afffcb7d15
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/dma/dpp_dtb.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/dma/dpp_dtb.h
@@ -1,696 +1,697 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_dtb.h
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : zab
-* 完成日期 : 2022/08/26
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-#ifndef _DPP_DTB_H_
-#define _DPP_DTB_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "dpp_dtb_cfg.h"
-
-#define DPP_DTB_QUEUE_ITEM_NUM_MAX              (32)
-
-#define DPP_DTB_ITEM_ACK_SIZE                   (16)
-#define DPP_DTB_ITEM_BUFF_SIZE                  (16 * 1024)
-#define DPP_DTB_ITEM_SIZE                       (16 + 16 * 1024)
-#define DPP_DTB_TAB_UP_SIZE                     ((16 + 16 * 1024) * 32)
-#define DPP_DTB_TAB_DOWN_SIZE                   ((16 + 16 * 1024) * 32)
-
-#define DPP_DTB_TAB_UP_ACK_VLD_MASK             (0x555555)
-#define DPP_DTB_TAB_DOWN_ACK_VLD_MASK           (0x5a5a5a)
-#define DPP_DTB_TAB_ACK_IS_USING_MASK           (0x11111100)
-#define DPP_DTB_TAB_ACK_UNUSED_MASK             (0x0)
-#define DPP_DTB_TAB_ACK_SUCCESS_MASK            (0xff)
-#define DPP_DTB_TAB_ACK_FAILED_MASK             (0x1)
-#define DPP_DTB_TAB_ACK_CHECK_VALUE             (0x12345678)
-
-#define DPP_DTB_TAB_ACK_VLD_SHIFT               (104)
-#define DPP_DTB_TAB_ACK_STATUS_SHIFT            (96)
-
-#define DPP_DTB_TAB_UP_PHY_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX)     \
-        (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.start_phy_addr + INDEX * p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.item_size)
-#define DPP_DTB_TAB_UP_USER_PHY_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX)     \
-        (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].phy_addr)
-#define DPP_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX)     \
-        (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag)
-#define DPP_DTB_TAB_UP_USER_ADDR_FLAG_SET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX, VAL)     \
-        do {\
-            p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag = VAL;\
-        }while(0)
-#define DPP_DTB_TAB_DOWN_PHY_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX)   \
-        (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_down.start_phy_addr + INDEX * p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_down.item_size)
-#define DPP_DTB_TAB_UP_VIR_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX)     \
-        (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.start_vir_addr + INDEX * p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.item_size)
-#define DPP_DTB_TAB_UP_USER_VIR_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX)     \
-            (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].vir_addr)
-#define DPP_DTB_TAB_DOWN_VIR_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX)   \
-        (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_down.start_vir_addr + INDEX * p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_down.item_size)
-#define DPP_DTB_TAB_UP_WR_INDEX_GET(SLOT_ID, DEV_ID, QUEUE_ID)       \
-        (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.wr_index)
-#define DPP_DTB_TAB_UP_RD_INDEX_GET(SLOT_ID, DEV_ID, QUEUE_ID)       \
-        (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.rd_index)
-#define DPP_DTB_TAB_DOWN_WR_INDEX_GET(SLOT_ID, DEV_ID, QUEUE_ID)       \
-        (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_down.wr_index)
-#define DPP_DTB_TAB_DOWN_RD_INDEX_GET(SLOT_ID, DEV_ID, QUEUE_ID)       \
-        (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_down.rd_index)
-#define DPP_DTB_TAB_UP_DATA_LEN_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX)       \
-        (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.data_len[INDEX])
-#define DPP_DTB_QUEUE_INIT_FLAG_GET(SLOT_ID, DEV_ID, QUEUE_ID)       \
-        (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].init_flag)
-#define DPP_DTB_QUEUE_VPORT_GET(SLOT_ID, DEV_ID, QUEUE_ID)       \
-        (p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].vport)
-
-#define DPP_BDRING_ITEM_SIZE                (16)
-
-#define DPP_UP_MAC_BD_ITEM_NUM              (0XFF)
-
-#define DPP_BD_ITEM_NUM_MAX                 (0XFF)
-#define DPP_UP_BD_BUFF_SIZE_MAX             (4 * 1024)
-
-#define DPP_UP_MAC_BD_ITEM_SIZE             ((DPP_UP_MAC_BD_ITEM_NUM + 1) * DPP_BDRING_ITEM_SIZE)
-#define DPP_UP_MAC_BUFF_SIZE                (16 * 1024)
-#define DPP_UP_MAC_BD_BUFF_SIZE             (DPP_UP_MAC_BD_ITEM_NUM * DPP_UP_MAC_BUFF_SIZE)
-#define DPP_UP_MAC_BD_TOTAL_SIZE            (DPP_UP_MAC_BD_ITEM_SIZE + DPP_UP_MAC_BD_BUFF_SIZE)
-#define DPP_DMA_BUFF_SIZE                   (4*1024*1024)
-
-#define DPP_DMA_BD_VLD_MSK                  (0x80000000)
-#define DPP_DMA_BD_DATA_LEN_MSK             (0x7FF)
-
-#define DPP_EP_ID_MAX                       (16)
-
-#define DPP_DTB_LEN_MIN                     (1)
-#define DPP_DTB_DOWN_LEN                    (0x3FF)
-
-#define DPP_DMA_HASH_KEY_OFFSET             (6)
-#define DPP_DMA_HASH_ITEM_MAX               (64)
-#define DPP_DMA_HASH_KEY_RST                (DPP_DMA_HASH_ITEM_MAX-DPP_DMA_HASH_KEY_OFFSET)
-
-#define DPP_DMA_SENDTYPE_START_BIT          (23)
-#define DPP_DMA_SENDTYPE_BIT_NUM            (2)
-#define DPP_DMA_VALID_START_BIT             (23)
-#define DPP_DMA_VALID_BIT_NUM               (1)
-#define DPP_DMA_HASHID_START_BIT            (21)
-#define DPP_DMA_HASHID_BIT_NUM              (2)
-#define DPP_DMA_TBLID_START_BIT             (16)
-#define DPP_DMA_TBLID_BIT_NUM               (2)
-
-typedef struct dpp_dtb_queue_cfg_t
-{
-    ZXIC_ADDR_T up_start_phy_addr;
-    ZXIC_ADDR_T up_start_vir_addr;
-    ZXIC_ADDR_T down_start_phy_addr;
-    ZXIC_ADDR_T down_start_vir_addr;
-    
-    ZXIC_UINT32 up_item_size;
-    ZXIC_UINT32 down_item_size;
-}DPP_DTB_QUEUE_CFG_T;
-
-typedef struct dpp_dtb_tab_up_user_addr_t
-{
-    ZXIC_UINT32 user_flag;
-    
-    ZXIC_ADDR_T phy_addr;
-    ZXIC_ADDR_T vir_addr;
-}DPP_DTB_TAB_UP_USER_ADDR_T;
-
-typedef struct dpp_dtb_tab_up_info_t
-{
-    ZXIC_ADDR_T start_phy_addr;
-    ZXIC_ADDR_T start_vir_addr;
-    ZXIC_UINT32 item_size;
-
-    ZXIC_UINT32 wr_index;
-    ZXIC_UINT32 rd_index;
-
-    ZXIC_UINT32 data_len[DPP_DTB_QUEUE_ITEM_NUM_MAX];
-    DPP_DTB_TAB_UP_USER_ADDR_T user_addr[DPP_DTB_QUEUE_ITEM_NUM_MAX];
-}DPP_DTB_TAB_UP_INFO_T;
-
-typedef struct dpp_dtb_tab_down_info_t
-{
-    ZXIC_ADDR_T start_phy_addr;
-    ZXIC_ADDR_T start_vir_addr;
-    ZXIC_UINT32 item_size;
-
-    ZXIC_UINT32 wr_index;
-    ZXIC_UINT32 rd_index;
-}DPP_DTB_TAB_DOWN_INFO_T;
-
-typedef struct dpp_dtb_queue_info_t
-{
-    ZXIC_UINT32 init_flag;
-    ZXIC_UINT32 slot_id;
-    ZXIC_UINT32 vport;
-    ZXIC_UINT32 vector;
-    
-    DPP_DTB_TAB_UP_INFO_T tab_up;
-    DPP_DTB_TAB_DOWN_INFO_T tab_down;
-}DPP_DTB_QUEUE_INFO_T;
-
-typedef struct dpp_dtb_mgr_t
-{  
-    DPP_DTB_QUEUE_INFO_T queue_info[DPP_DTB_QUEUE_NUM_MAX];
-} DPP_DTB_MGR_T;
-
-typedef enum dpp_dtb_dir_type_e
-{
-    DPP_DTB_DIR_DOWN_TYPE    = 0, 
-    DPP_DTB_DIR_UP_TYPE    = 1,        
-    DPP_DTB_DIR_TYPE_MAX,
-} DPP_DTB_DIR_TYPE_E;
-
-
-typedef enum dpp_dtb_tab_up_user_addr_type_e
-{
-    DPP_DTB_TAB_UP_NOUSER_ADDR_TYPE     = 0, 
-    DPP_DTB_TAB_UP_USER_ADDR_TYPE       = 1,        
-    DPP_DTB_TAB_UP_USER_ADDR_TYPE_MAX,
-} DPP_DTB_TAB_UP_USER_ADDR_TYPE_E;
-
-typedef enum dpp_dma_send_type_e
-{
-    DMA_LEARN_HASH  = 0,
-    DMA_DEL_HASH    = 1,
-    DMA_UPDATE_HASH = 2,
-    DMA_ADD_HASH    = 3,
-    DMA_SEND_TYPE_MAX
-}DPP_DMA_SEND_TYPE_E;
-
-/* 单个通道BD表管理结构体 */
-typedef struct dpp_dma_bd_t
-{
-    ZXIC_ADDR_T bd_phy_addr;    /* BD表物理地址 */
-    ZXIC_ADDR_T bd_vir_addr;    /* BD表进程空间虚拟地址 */
-    ZXIC_ADDR_T buff_phy_addr;  /* BD表指向的BUFF物理地址 */
-    ZXIC_ADDR_T buff_vir_addr;  /* BD表指向的BUFF进程空间虚拟地址 */
-    ZXIC_UINT32 bd_index;       /* BD表当前使用index */
-} DPP_DMA_BD_T;
-
-/* 单个设备BD表管理结构体 */
-typedef struct dpp_dma_mgr_t
-{
-    ZXIC_UINT32 init;
-    ZXIC_UINT32 endian_flag;    /* DMA数据通道大小端，0-小端，1-大端 */
-    DPP_DMA_BD_T up_mac;
-} DPP_DMA_MGR_T;
-
-/**使能dtb调试函数*/
-ZXIC_UINT32 dpp_dtb_debug_fun_enable(ZXIC_VOID);
-
-/**去使能dtb调试函数*/
-ZXIC_UINT32 dpp_dtb_debug_fun_disable(ZXIC_VOID);
-
-/**获取dtb调试函数*/
-ZXIC_UINT32 dpp_dtb_debug_fun_get(ZXIC_VOID);
-
-/**使能dtb打印函数*/
-ZXIC_UINT32 dpp_dtb_prt_enable(ZXIC_VOID);
-
-/**去使能dtb打印函数*/
-ZXIC_UINT32 dpp_dtb_prt_disable(ZXIC_VOID);
-
-/**获取dtb打印函数*/
-ZXIC_UINT32 dpp_dtb_prt_get(ZXIC_VOID);
-
-ZXIC_UINT32 dpp_dtb_soft_perf_test_set(ZXIC_UINT32 value);
-
-ZXIC_UINT32 dpp_dtb_soft_perf_test_get(ZXIC_VOID);
-
-ZXIC_UINT32 dpp_dtb_hardware_perf_test_set(ZXIC_UINT32 value);
-
-ZXIC_UINT32 dpp_dtb_hardware_perf_test_get(ZXIC_VOID);
-
-ZXIC_UINT32 dpp_dtb_down_table_overtime_set(ZXIC_UINT32 times_s);
-ZXIC_UINT32 dpp_dtb_down_table_overtime_get(ZXIC_VOID);
-
-ZXIC_UINT32 dpp_dtb_dump_table_overtime_set(ZXIC_UINT32 times_s);
-ZXIC_UINT32 dpp_dtb_dump_table_overtime_get(ZXIC_VOID);
-
-#if ZXIC_REAL("MGR")
-/***********************************************************/
-/** 创建DTB的管理结构
-* @param   dev_id       设备号，支持多芯片  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_mgr_create(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** 注销DTB的管理结构
-* @param   dev_id       设备号，支持多芯片   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_mgr_destory_all(ZXIC_VOID);
-ZXIC_UINT32 dpp_dtb_mgr_destory(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** 重置DTB管理结构
-* @param   dev_id       设备号，支持多芯片   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_mgr_reset(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** 获取DMA管理结构
-* @param   dev_id               设备号，支持多芯片
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-DPP_DTB_MGR_T *dpp_dtb_mgr_get(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id);
-#endif
-
-#if ZXIC_REAL("ACK_RW")
-/***********************************************************/
-/** 读取BD表条目信息
-* @param   dev_id       芯片的id号  
-* @param   queue_id     队列号,范围0-127
-* @param   dir_flag     方向,1-上送表项,0-下发表项    
-* @param   index        条目索引,范围0-31 
-* @param   pos          一个item里面的4个32位，pos对应的是第几个ZXICP_WORD32，
-*                       取值为0，1，2，3      
-* @param   p_data       读取的数据,大端格式  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2019/11/2
-************************************************************/
-ZXIC_UINT32 dpp_dtb_item_ack_rd(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 dir_flag,
-                    ZXIC_UINT32 index, 
-                    ZXIC_UINT32 pos,
-                    ZXIC_UINT32 *p_data);
-
-/***********************************************************/
-/** 向BD表条目指定位置写入值
-* @param   dev_id       芯片的id号  
-* @param   queue_id     队列号,范围0-127
-* @param   dir_flag     方向,1-上送表项,0-下发表项  
-* @param   index        条目索引,范围0-31 
-* @param   pos          一个item里面的4个32位，pos对应的是第几个ZXICP_WORD32，
-*                       取值为0，1，2，3      
-* @param   data         读取的数据,大端格式 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2019/11/2
-************************************************************/
-ZXIC_UINT32 dpp_dtb_item_ack_wr(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 dir_flag,
-                    ZXIC_UINT32 index, 
-                    ZXIC_UINT32 pos,
-                    ZXIC_UINT32 data);
-#endif
-
-#if ZXIC_REAL("BUFF_RW")
-/***********************************************************/
-/** 读取dtb条目指向BUFF的数据
-* @param   dev_id       芯片的id号  
-* @param   queue_id     队列号,范围0-127
-* @param   dir_flag     方向,1-上送表项,0-下发表项  
-* @param   index        条目索引,范围0-31 
-* @param   pos          相对BUFF起始地址的偏移,单位32bit;      
-* @param   p_data       读取的数据,大端格式 
-* @param   len          读取数据长度,单位32bit; 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2019/11/2
-************************************************************/
-ZXIC_UINT32 dpp_dtb_item_buff_rd(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 dir_flag,
-                    ZXIC_UINT32 index, 
-                    ZXIC_UINT32 pos,
-                    ZXIC_UINT32 len,
-                    ZXIC_UINT32 *p_data);
-
-/***********************************************************/
-/** 向BD表条目指向的BUFF指定位置写入值
-* @param   dev_id       芯片的id号  
-* @param   queue_id     队列号,范围0-127
-* @param   dir_flag     方向,1-上送表项,0-下发表项  
-* @param   index        条目索引,范围0-31   
-* @param   pos          相对BUFF起始地址的偏移,单位32bit;       
-* @param   p_data       读取的数据,大端格式 
-* @param   len          写入数据长度,单位32bit; 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2019/11/2
-************************************************************/
-ZXIC_UINT32 dpp_dtb_item_buff_wr(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 dir_flag,
-                    ZXIC_UINT32 index, 
-                    ZXIC_UINT32 pos,
-                    ZXIC_UINT32 len,
-                    ZXIC_UINT32 *p_data);
-#endif
-
-#if ZXIC_REAL("API")
-/***********************************************************/
-/** 配置下发配置数据信息
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列号，范围0-31 
-* @param   int_flag             中断标志，0-无，1-有 
-* @param   data_len             数据长度，单位32bit;
-* @param   p_data               待下发数据 
-* @param   p_item_index         返回使用的条目编号 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_down_info_set(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 int_flag,
-                    ZXIC_UINT32 data_len,
-                    ZXIC_UINT32 *p_data,
-                    ZXIC_UINT32 *p_item_index);
-
-/***********************************************************/
-/** 一个元素down成功状态检查
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列号，范围0-31 
-* @param   element_id           条目编号 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_down_success_status_check(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 element_id);
-
-/***********************************************************/
-/** dump队列空闲条目获取
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列号，范围0-31 
-* @param   p_item_index         返回使用的条目编号 
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_up_free_item_get(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 *p_item_index);
-
-/***********************************************************/
-/** 获取dump指定条目物理地址
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列编号,范围:0-127  
-* @param   item_index           条目编号,范围0-31  
-* @param   p_phy_haddr          物理地址高32bit  
-* @param   p_phy_laddr          物理地址低32bit  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_up_item_addr_get(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 item_index,
-                    ZXIC_UINT32 *p_phy_haddr,
-                    ZXIC_UINT32 *p_phy_laddr);
-
-/***********************************************************/
-/** 获取指定dump条目一定地址偏移的物理地址
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列编号,范围:0-127  
-* @param   item_index           条目编号,范围0-31  
-* @param   p_phy_haddr          物理地址高32bit  
-* @param   p_phy_laddr          物理地址低32bit  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_up_item_offset_addr_get(DPP_DEV_T *dev,
-                                                ZXIC_UINT32 queue_id,
-                                                ZXIC_UINT32 item_index,
-                                                ZXIC_UINT32 addr_offset,
-                                                ZXIC_UINT32 *p_phy_haddr,
-                                                ZXIC_UINT32 *p_phy_laddr);
-
-/***********************************************************/
-/** 设置dump指定条目空间地址，用于用户自定义空间传输
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列编号,范围:0-127  
-* @param   item_index           条目编号,范围0-31  
-* @param   phy_haddr            物理地址高  
-* @param   vir_laddr            虚拟地址低  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_up_item_user_addr_set(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 item_index,
-                    ZXIC_ADDR_T phy_addr,
-                    ZXIC_ADDR_T vir_addr);                
-
-/***********************************************************/
-/** 清除用户dump指定条目空间地址
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列编号,范围:0-127  
-* @param   item_index           条目编号,范围0-31   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_up_item_user_addr_clr(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 item_index);
-
-/***********************************************************/
-/** dump配置描述符信息设置
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列号，范围0-31 
-* @param   item_index           返回使用的条目编号 
-* @param   int_flag             中断标志，0-无，1-有 
-* @param   data_len             数据长度，单位32bit;
-* @param   desc_len             描述符长度，单位32bit;
-* @param   p_desc_data          待下发描述符 
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_up_info_set(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 item_index,
-                    ZXIC_UINT32 int_flag,
-                    ZXIC_UINT32 data_len,
-                    ZXIC_UINT32 desc_len,
-                    ZXIC_UINT32 *p_desc_data);
-
-/***********************************************************/
-/** 一个元素dump成功状态检查
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列号，范围0-31 
-* @param   element_id           条目编号 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_up_success_status_check(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 element_id);
-
-/***********************************************************/
-/** 获取dump数据
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列号，范围0-31 
-* @param   item_index           数据对应的的条目编号 
-* @param   data_len             数据长度，单位32bit; 
-* @param   p_data               dump数据 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_up_data_get(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 item_index,
-                    ZXIC_UINT32 data_len,
-                    ZXIC_UINT32 *p_data);
-
-/***********************************************************/
-/** dtb初始化
-* @param   dev_id       设备号，支持多芯片   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2022/08/30
-************************************************************/
-ZXIC_UINT32 dpp_dtb_init(DPP_DEV_T *dev);
-
-/***********************************************************/
-/** dtb队列down初始化
-* @param   dev_id           设备号，支持多芯片 
-* @param   queue_id         队列号
-* @param   p_queue_cfg      队列配置参数，具体见DPP_DTB_QUEUE_CFG_T结构体类型
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_down_init(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    DPP_DTB_QUEUE_CFG_T *p_queue_cfg);
-
-/***********************************************************/
-/** dtb队列dump初始化
-* @param   dev_id           设备号，支持多芯片 
-* @param   queue_id         队列号
-* @param   p_queue_cfg      队列配置参数，具体见DPP_DTB_QUEUE_CFG_T结构体类型
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_dump_init(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    DPP_DTB_QUEUE_CFG_T *p_queue_cfg);
-
-/***********************************************************/
-/** dtb队列down 空间地址配置
-* @param   channelId    dtb通道号 
-* @param   phyAddr      down物理地址
-* @param   virAddr      down虚拟地址
-* @param   size         空间大小
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_down_channel_addr_set(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 channelId, 
-                                          ZXIC_UINT64 phyAddr, 
-                                          ZXIC_UINT64 virAddr, 
-                                          ZXIC_UINT32 size);
-
-/***********************************************************/
-/** dtb队列dump 空间地址配置
-* @param   channelId    dtb通道号 
-* @param   phyAddr      dump物理地址
-* @param   virAddr      dump虚拟地址
-* @param   size         空间大小
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_dump_channel_addr_set(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 channelId, 
-                                          ZXIC_UINT64 phyAddr, 
-                                          ZXIC_UINT64 virAddr, 
-                                          ZXIC_UINT32 size);
-
-/***********************************************************/
-/** 释放队列资源
-* @param   dev_id           设备号，支持多芯片  
-* @param   queue_id         分配到的队列号;
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_id_free(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id);
-
-/***********************************************************/
-/** 根据vport查找相应的队列号
-* @param   dev_id       设备号，支持多芯片   
-* @param   vport        vport信息
-* @param   p_queue_arr 找到到队列数组
-* @param   p_num          找到的队列个数
-* @return  
-* @remark  无
-* @see     
-* @author  cbb      @date  2023/09/13
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_id_search_by_vport(DPP_DEV_T *dev,
-                                             ZXIC_UINT32 *p_queue_arr,
-                                             ZXIC_UINT32 *p_num);
-
-/***********************************************************/
-/** 根据vport查找相应的队列号
-* @param   dev_id       设备号，支持多芯片
-* @param   vport        vport信息
-* @param   p_queue_arr 找到到队列数组
-* @param   p_num          找到的队列个数
-* @return  
-* @remark  无
-* @see     
-* @author  cbb      @date  2023/09/13
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_id_get(ZXIC_UINT32 dev_id, DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *queue);
-
-#endif
-
-#if ZXIC_REAL("DMA")
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_dtb.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : zab
+* 完成日期 : 2022/08/26
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#ifndef _DPP_DTB_H_
+#define _DPP_DTB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dpp_dtb_cfg.h"
+
+#define DPP_DTB_QUEUE_ITEM_NUM_MAX (32)
+
+#define DPP_DTB_ITEM_ACK_SIZE (16)
+#define DPP_DTB_ITEM_BUFF_SIZE (16 * 1024)
+#define DPP_DTB_ITEM_SIZE (16 + 16 * 1024)
+#define DPP_DTB_TAB_UP_SIZE ((16 + 16 * 1024) * 32)
+#define DPP_DTB_TAB_DOWN_SIZE ((16 + 16 * 1024) * 32)
+
+#define DPP_DTB_TAB_UP_ACK_VLD_MASK (0x555555)
+#define DPP_DTB_TAB_DOWN_ACK_VLD_MASK (0x5a5a5a)
+#define DPP_DTB_TAB_ACK_IS_USING_MASK (0x11111100)
+#define DPP_DTB_TAB_ACK_UNUSED_MASK (0x0)
+#define DPP_DTB_TAB_ACK_SUCCESS_MASK (0xff)
+#define DPP_DTB_TAB_ACK_FAILED_MASK (0x1)
+#define DPP_DTB_TAB_ACK_CHECK_VALUE (0x12345678)
+
+#define DPP_DTB_TAB_ACK_VLD_SHIFT (104)
+#define DPP_DTB_TAB_ACK_STATUS_SHIFT (96)
+
+#define DPP_DTB_TAB_UP_PHY_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX) \
+	(p_dpp_dtb_mgr[SLOT_ID][DEV_ID]                                   \
+			 ->queue_info[QUEUE_ID]                                   \
+			 .tab_up.start_phy_addr +                                 \
+	 INDEX * p_dpp_dtb_mgr[SLOT_ID][DEV_ID]                           \
+					 ->queue_info[QUEUE_ID]                           \
+					 .tab_up.item_size)
+#define DPP_DTB_TAB_UP_USER_PHY_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX) \
+	(p_dpp_dtb_mgr[SLOT_ID][DEV_ID]                                        \
+			 ->queue_info[QUEUE_ID]                                        \
+			 .tab_up.user_addr[INDEX]                                      \
+			 .phy_addr)
+#define DPP_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(SLOT_ID, DEV_ID, QUEUE_ID, \
+											  INDEX)                     \
+	(p_dpp_dtb_mgr[SLOT_ID][DEV_ID]                                      \
+			 ->queue_info[QUEUE_ID]                                      \
+			 .tab_up.user_addr[INDEX]                                    \
+			 .user_flag)
+#define DPP_DTB_TAB_UP_USER_ADDR_FLAG_SET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX, \
+										  VAL)                              \
+	do {                                                                    \
+		p_dpp_dtb_mgr[SLOT_ID][DEV_ID]                                      \
+				->queue_info[QUEUE_ID]                                      \
+				.tab_up.user_addr[INDEX]                                    \
+				.user_flag = VAL;                                           \
+	} while (0)
+#define DPP_DTB_TAB_DOWN_PHY_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX) \
+	(p_dpp_dtb_mgr[SLOT_ID][DEV_ID]                                     \
+			 ->queue_info[QUEUE_ID]                                     \
+			 .tab_down.start_phy_addr +                                 \
+	 INDEX * p_dpp_dtb_mgr[SLOT_ID][DEV_ID]                             \
+					 ->queue_info[QUEUE_ID]                             \
+					 .tab_down.item_size)
+#define DPP_DTB_TAB_UP_VIR_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX) \
+	(p_dpp_dtb_mgr[SLOT_ID][DEV_ID]                                   \
+			 ->queue_info[QUEUE_ID]                                   \
+			 .tab_up.start_vir_addr +                                 \
+	 INDEX * p_dpp_dtb_mgr[SLOT_ID][DEV_ID]                           \
+					 ->queue_info[QUEUE_ID]                           \
+					 .tab_up.item_size)
+#define DPP_DTB_TAB_UP_USER_VIR_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX) \
+	(p_dpp_dtb_mgr[SLOT_ID][DEV_ID]                                        \
+			 ->queue_info[QUEUE_ID]                                        \
+			 .tab_up.user_addr[INDEX]                                      \
+			 .vir_addr)
+#define DPP_DTB_TAB_DOWN_VIR_ADDR_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX) \
+	(p_dpp_dtb_mgr[SLOT_ID][DEV_ID]                                     \
+			 ->queue_info[QUEUE_ID]                                     \
+			 .tab_down.start_vir_addr +                                 \
+	 INDEX * p_dpp_dtb_mgr[SLOT_ID][DEV_ID]                             \
+					 ->queue_info[QUEUE_ID]                             \
+					 .tab_down.item_size)
+#define DPP_DTB_TAB_UP_WR_INDEX_GET(SLOT_ID, DEV_ID, QUEUE_ID) \
+	(p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.wr_index)
+#define DPP_DTB_TAB_UP_RD_INDEX_GET(SLOT_ID, DEV_ID, QUEUE_ID) \
+	(p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_up.rd_index)
+#define DPP_DTB_TAB_DOWN_WR_INDEX_GET(SLOT_ID, DEV_ID, QUEUE_ID) \
+	(p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_down.wr_index)
+#define DPP_DTB_TAB_DOWN_RD_INDEX_GET(SLOT_ID, DEV_ID, QUEUE_ID) \
+	(p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].tab_down.rd_index)
+#define DPP_DTB_TAB_UP_DATA_LEN_GET(SLOT_ID, DEV_ID, QUEUE_ID, INDEX) \
+	(p_dpp_dtb_mgr[SLOT_ID][DEV_ID]                                   \
+			 ->queue_info[QUEUE_ID]                                   \
+			 .tab_up.data_len[INDEX])
+#define DPP_DTB_QUEUE_INIT_FLAG_GET(SLOT_ID, DEV_ID, QUEUE_ID) \
+	(p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].init_flag)
+#define DPP_DTB_QUEUE_VPORT_GET(SLOT_ID, DEV_ID, QUEUE_ID) \
+	(p_dpp_dtb_mgr[SLOT_ID][DEV_ID]->queue_info[QUEUE_ID].vport)
+
+#define DPP_BDRING_ITEM_SIZE (16)
+
+#define DPP_UP_MAC_BD_ITEM_NUM (0XFF)
+
+#define DPP_BD_ITEM_NUM_MAX (0XFF)
+#define DPP_UP_BD_BUFF_SIZE_MAX (4 * 1024)
+
+#define DPP_UP_MAC_BD_ITEM_SIZE \
+	((DPP_UP_MAC_BD_ITEM_NUM + 1) * DPP_BDRING_ITEM_SIZE)
+#define DPP_UP_MAC_BUFF_SIZE (16 * 1024)
+#define DPP_UP_MAC_BD_BUFF_SIZE (DPP_UP_MAC_BD_ITEM_NUM * DPP_UP_MAC_BUFF_SIZE)
+#define DPP_UP_MAC_BD_TOTAL_SIZE \
+	(DPP_UP_MAC_BD_ITEM_SIZE + DPP_UP_MAC_BD_BUFF_SIZE)
+#define DPP_DMA_BUFF_SIZE (4 * 1024 * 1024)
+
+#define DPP_DMA_BD_VLD_MSK (0x80000000)
+#define DPP_DMA_BD_DATA_LEN_MSK (0x7FF)
+
+#define DPP_EP_ID_MAX (16)
+
+#define DPP_DTB_LEN_MIN (1)
+#define DPP_DTB_DOWN_LEN (0x3FF)
+
+#define DPP_DMA_HASH_KEY_OFFSET (6)
+#define DPP_DMA_HASH_ITEM_MAX (64)
+#define DPP_DMA_HASH_KEY_RST (DPP_DMA_HASH_ITEM_MAX - DPP_DMA_HASH_KEY_OFFSET)
+
+#define DPP_DMA_SENDTYPE_START_BIT (23)
+#define DPP_DMA_SENDTYPE_BIT_NUM (2)
+#define DPP_DMA_VALID_START_BIT (23)
+#define DPP_DMA_VALID_BIT_NUM (1)
+#define DPP_DMA_HASHID_START_BIT (21)
+#define DPP_DMA_HASHID_BIT_NUM (2)
+#define DPP_DMA_TBLID_START_BIT (16)
+#define DPP_DMA_TBLID_BIT_NUM (2)
+
+typedef struct dpp_dtb_queue_cfg_t {
+	ZXIC_ADDR_T up_start_phy_addr;
+	ZXIC_ADDR_T up_start_vir_addr;
+	ZXIC_ADDR_T down_start_phy_addr;
+	ZXIC_ADDR_T down_start_vir_addr;
+
+	ZXIC_UINT32 up_item_size;
+	ZXIC_UINT32 down_item_size;
+} DPP_DTB_QUEUE_CFG_T;
+
+typedef struct dpp_dtb_tab_up_user_addr_t {
+	ZXIC_UINT32 user_flag;
+
+	ZXIC_ADDR_T phy_addr;
+	ZXIC_ADDR_T vir_addr;
+} DPP_DTB_TAB_UP_USER_ADDR_T;
+
+typedef struct dpp_dtb_tab_up_info_t {
+	ZXIC_ADDR_T start_phy_addr;
+	ZXIC_ADDR_T start_vir_addr;
+	ZXIC_UINT32 item_size;
+
+	ZXIC_UINT32 wr_index;
+	ZXIC_UINT32 rd_index;
+
+	ZXIC_UINT32 data_len[DPP_DTB_QUEUE_ITEM_NUM_MAX];
+	DPP_DTB_TAB_UP_USER_ADDR_T user_addr[DPP_DTB_QUEUE_ITEM_NUM_MAX];
+} DPP_DTB_TAB_UP_INFO_T;
+
+typedef struct dpp_dtb_tab_down_info_t {
+	ZXIC_ADDR_T start_phy_addr;
+	ZXIC_ADDR_T start_vir_addr;
+	ZXIC_UINT32 item_size;
+
+	ZXIC_UINT32 wr_index;
+	ZXIC_UINT32 rd_index;
+} DPP_DTB_TAB_DOWN_INFO_T;
+
+typedef struct dpp_dtb_queue_info_t {
+	ZXIC_UINT32 init_flag;
+	ZXIC_UINT32 slot_id;
+	ZXIC_UINT32 vport;
+	ZXIC_UINT32 vector;
+
+	DPP_DTB_TAB_UP_INFO_T tab_up;
+	DPP_DTB_TAB_DOWN_INFO_T tab_down;
+} DPP_DTB_QUEUE_INFO_T;
+
+typedef struct dpp_dtb_mgr_t {
+	DPP_DTB_QUEUE_INFO_T queue_info[DPP_DTB_QUEUE_NUM_MAX];
+} DPP_DTB_MGR_T;
+
+typedef enum dpp_dtb_dir_type_e {
+	DPP_DTB_DIR_DOWN_TYPE = 0,
+	DPP_DTB_DIR_UP_TYPE = 1,
+	DPP_DTB_DIR_TYPE_MAX,
+} DPP_DTB_DIR_TYPE_E;
+
+typedef enum dpp_dtb_tab_up_user_addr_type_e {
+	DPP_DTB_TAB_UP_NOUSER_ADDR_TYPE = 0,
+	DPP_DTB_TAB_UP_USER_ADDR_TYPE = 1,
+	DPP_DTB_TAB_UP_USER_ADDR_TYPE_MAX,
+} DPP_DTB_TAB_UP_USER_ADDR_TYPE_E;
+
+typedef enum dpp_dma_send_type_e {
+	DMA_LEARN_HASH = 0,
+	DMA_DEL_HASH = 1,
+	DMA_UPDATE_HASH = 2,
+	DMA_ADD_HASH = 3,
+	DMA_SEND_TYPE_MAX
+} DPP_DMA_SEND_TYPE_E;
+
+/* 单个通道BD表管理结构体 */
+typedef struct dpp_dma_bd_t {
+	ZXIC_ADDR_T bd_phy_addr; /* BD表物理地址 */
+	ZXIC_ADDR_T bd_vir_addr; /* BD表进程空间虚拟地址 */
+	ZXIC_ADDR_T buff_phy_addr; /* BD表指向的BUFF物理地址 */
+	ZXIC_ADDR_T buff_vir_addr; /* BD表指向的BUFF进程空间虚拟地址 */
+	ZXIC_UINT32 bd_index; /* BD表当前使用index */
+} DPP_DMA_BD_T;
+
+/* 单个设备BD表管理结构体 */
+typedef struct dpp_dma_mgr_t {
+	ZXIC_UINT32 init;
+	ZXIC_UINT32 endian_flag; /* DMA数据通道大小端，0-小端，1-大端 */
+	DPP_DMA_BD_T up_mac;
+} DPP_DMA_MGR_T;
+
+/**使能dtb调试函数*/
+ZXIC_UINT32 dpp_dtb_debug_fun_enable(ZXIC_VOID);
+
+/**去使能dtb调试函数*/
+ZXIC_UINT32 dpp_dtb_debug_fun_disable(ZXIC_VOID);
+
+/**获取dtb调试函数*/
+ZXIC_UINT32 dpp_dtb_debug_fun_get(ZXIC_VOID);
+
+/**使能dtb打印函数*/
+ZXIC_UINT32 dpp_dtb_prt_enable(ZXIC_VOID);
+
+/**去使能dtb打印函数*/
+ZXIC_UINT32 dpp_dtb_prt_disable(ZXIC_VOID);
+
+/**获取dtb打印函数*/
+ZXIC_UINT32 dpp_dtb_prt_get(ZXIC_VOID);
+
+ZXIC_UINT32 dpp_dtb_soft_perf_test_set(ZXIC_UINT32 value);
+
+ZXIC_UINT32 dpp_dtb_soft_perf_test_get(ZXIC_VOID);
+
+ZXIC_UINT32 dpp_dtb_hardware_perf_test_set(ZXIC_UINT32 value);
+
+ZXIC_UINT32 dpp_dtb_hardware_perf_test_get(ZXIC_VOID);
+
+ZXIC_UINT32 dpp_dtb_down_table_overtime_set(ZXIC_UINT32 times_s);
+ZXIC_UINT32 dpp_dtb_down_table_overtime_get(ZXIC_VOID);
+
+ZXIC_UINT32 dpp_dtb_dump_table_overtime_set(ZXIC_UINT32 times_s);
+ZXIC_UINT32 dpp_dtb_dump_table_overtime_get(ZXIC_VOID);
+
+#if ZXIC_REAL("MGR")
+/***********************************************************/
+/** 创建DTB的管理结构
+     * @param   dev_id       设备号，支持多芯片
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_mgr_create(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 注销DTB的管理结构
+     * @param   dev_id       设备号，支持多芯片
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_mgr_destory_all(ZXIC_VOID);
+ZXIC_UINT32 dpp_dtb_mgr_destory(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 重置DTB管理结构
+     * @param   dev_id       设备号，支持多芯片
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_mgr_reset(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 获取DMA管理结构
+     * @param   dev_id               设备号，支持多芯片
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+DPP_DTB_MGR_T *dpp_dtb_mgr_get(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id);
+#endif
+
+#if ZXIC_REAL("ACK_RW")
+/***********************************************************/
+/** 读取BD表条目信息
+     * @param   dev_id       芯片的id号
+     * @param   queue_id     队列号,范围0-127
+     * @param   dir_flag     方向,1-上送表项,0-下发表项
+     * @param   index        条目索引,范围0-31
+     * @param   pos          一个item里面的4个32位，pos对应的是第几个ZXICP_WORD32，
+     *                       取值为0，1，2，3
+     * @param   p_data       读取的数据,大端格式
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2019/11/2
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_item_ack_rd(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								ZXIC_UINT32 dir_flag, ZXIC_UINT32 index,
+								ZXIC_UINT32 pos, ZXIC_UINT32 *p_data);
+
+/***********************************************************/
+/** 向BD表条目指定位置写入值
+     * @param   dev_id       芯片的id号
+     * @param   queue_id     队列号,范围0-127
+     * @param   dir_flag     方向,1-上送表项,0-下发表项
+     * @param   index        条目索引,范围0-31
+     * @param   pos          一个item里面的4个32位，pos对应的是第几个ZXICP_WORD32，
+     *                       取值为0，1，2，3
+     * @param   data         读取的数据,大端格式
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2019/11/2
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_item_ack_wr(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								ZXIC_UINT32 dir_flag, ZXIC_UINT32 index,
+								ZXIC_UINT32 pos, ZXIC_UINT32 data);
+#endif
+
+#if ZXIC_REAL("BUFF_RW")
+/***********************************************************/
+/** 读取dtb条目指向BUFF的数据
+     * @param   dev_id       芯片的id号
+     * @param   queue_id     队列号,范围0-127
+     * @param   dir_flag     方向,1-上送表项,0-下发表项
+     * @param   index        条目索引,范围0-31
+     * @param   pos          相对BUFF起始地址的偏移,单位32bit;
+     * @param   p_data       读取的数据,大端格式
+     * @param   len          读取数据长度,单位32bit;
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2019/11/2
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_item_buff_rd(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								 ZXIC_UINT32 dir_flag, ZXIC_UINT32 index,
+								 ZXIC_UINT32 pos, ZXIC_UINT32 len,
+								 ZXIC_UINT32 *p_data);
+
+/***********************************************************/
+/** 向BD表条目指向的BUFF指定位置写入值
+     * @param   dev_id       芯片的id号
+     * @param   queue_id     队列号,范围0-127
+     * @param   dir_flag     方向,1-上送表项,0-下发表项
+     * @param   index        条目索引,范围0-31
+     * @param   pos          相对BUFF起始地址的偏移,单位32bit;
+     * @param   p_data       读取的数据,大端格式
+     * @param   len          写入数据长度,单位32bit;
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2019/11/2
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_item_buff_wr(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								 ZXIC_UINT32 dir_flag, ZXIC_UINT32 index,
+								 ZXIC_UINT32 pos, ZXIC_UINT32 len,
+								 ZXIC_UINT32 *p_data);
+#endif
+
+#if ZXIC_REAL("API")
+/***********************************************************/
+/** 配置下发配置数据信息
+     * @param   dev_id               设备号，支持多芯片
+     * @param   queue_id             队列号，范围0-31
+     * @param   int_flag             中断标志，0-无，1-有
+     * @param   data_len             数据长度，单位32bit;
+     * @param   p_data               待下发数据
+     * @param   p_item_index         返回使用的条目编号
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_down_info_set(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									  ZXIC_UINT32 int_flag,
+									  ZXIC_UINT32 data_len, ZXIC_UINT32 *p_data,
+									  ZXIC_UINT32 *p_item_index);
+
+/***********************************************************/
+/** 一个元素down成功状态检查
+     * @param   dev_id               设备号，支持多芯片
+     * @param   queue_id             队列号，范围0-31
+     * @param   element_id           条目编号
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_down_success_status_check(DPP_DEV_T *dev,
+												  ZXIC_UINT32 queue_id,
+												  ZXIC_UINT32 element_id);
+
+/***********************************************************/
+/** dump队列空闲条目获取
+     * @param   dev_id               设备号，支持多芯片
+     * @param   queue_id             队列号，范围0-31
+     * @param   p_item_index         返回使用的条目编号
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_up_free_item_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+										 ZXIC_UINT32 *p_item_index);
+
+/***********************************************************/
+/** 获取dump指定条目物理地址
+     * @param   dev_id               设备号，支持多芯片
+     * @param   queue_id             队列编号,范围:0-127
+     * @param   item_index           条目编号,范围0-31
+     * @param   p_phy_haddr          物理地址高32bit
+     * @param   p_phy_laddr          物理地址低32bit
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_up_item_addr_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+										 ZXIC_UINT32 item_index,
+										 ZXIC_UINT32 *p_phy_haddr,
+										 ZXIC_UINT32 *p_phy_laddr);
+
+/***********************************************************/
+/** 获取指定dump条目一定地址偏移的物理地址
+     * @param   dev_id               设备号，支持多芯片
+     * @param   queue_id             队列编号,范围:0-127
+     * @param   item_index           条目编号,范围0-31
+     * @param   p_phy_haddr          物理地址高32bit
+     * @param   p_phy_laddr          物理地址低32bit
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_up_item_offset_addr_get(DPP_DEV_T *dev,
+												ZXIC_UINT32 queue_id,
+												ZXIC_UINT32 item_index,
+												ZXIC_UINT32 addr_offset,
+												ZXIC_UINT32 *p_phy_haddr,
+												ZXIC_UINT32 *p_phy_laddr);
+
+/***********************************************************/
+/** 设置dump指定条目空间地址，用于用户自定义空间传输
+     * @param   dev_id               设备号，支持多芯片
+     * @param   queue_id             队列编号,范围:0-127
+     * @param   item_index           条目编号,范围0-31
+     * @param   phy_haddr            物理地址高
+     * @param   vir_laddr            虚拟地址低
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_up_item_user_addr_set(DPP_DEV_T *dev,
+											  ZXIC_UINT32 queue_id,
+											  ZXIC_UINT32 item_index,
+											  ZXIC_ADDR_T phy_addr,
+											  ZXIC_ADDR_T vir_addr);
+
+/***********************************************************/
+/** 清除用户dump指定条目空间地址
+     * @param   dev_id               设备号，支持多芯片
+     * @param   queue_id             队列编号,范围:0-127
+     * @param   item_index           条目编号,范围0-31
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_up_item_user_addr_clr(DPP_DEV_T *dev,
+											  ZXIC_UINT32 queue_id,
+											  ZXIC_UINT32 item_index);
+
+/***********************************************************/
+/** dump配置描述符信息设置
+     * @param   dev_id               设备号，支持多芯片
+     * @param   queue_id             队列号，范围0-31
+     * @param   item_index           返回使用的条目编号
+     * @param   int_flag             中断标志，0-无，1-有
+     * @param   data_len             数据长度，单位32bit;
+     * @param   desc_len             描述符长度，单位32bit;
+     * @param   p_desc_data          待下发描述符
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_up_info_set(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									ZXIC_UINT32 item_index,
+									ZXIC_UINT32 int_flag, ZXIC_UINT32 data_len,
+									ZXIC_UINT32 desc_len,
+									ZXIC_UINT32 *p_desc_data);
+
+/***********************************************************/
+/** 一个元素dump成功状态检查
+     * @param   dev_id               设备号，支持多芯片
+     * @param   queue_id             队列号，范围0-31
+     * @param   element_id           条目编号
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_up_success_status_check(DPP_DEV_T *dev,
+												ZXIC_UINT32 queue_id,
+												ZXIC_UINT32 element_id);
+
+/***********************************************************/
+/** 获取dump数据
+     * @param   dev_id               设备号，支持多芯片
+     * @param   queue_id             队列号，范围0-31
+     * @param   item_index           数据对应的的条目编号
+     * @param   data_len             数据长度，单位32bit;
+     * @param   p_data               dump数据
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_up_data_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									ZXIC_UINT32 item_index,
+									ZXIC_UINT32 data_len, ZXIC_UINT32 *p_data);
+
+/***********************************************************/
+/** dtb初始化
+     * @param   dev_id       设备号，支持多芯片
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2022/08/30
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_init(DPP_DEV_T *dev);
+
+/***********************************************************/
+/** dtb队列down初始化
+     * @param   dev_id           设备号，支持多芯片
+     * @param   queue_id         队列号
+     * @param   p_queue_cfg      队列配置参数，具体见DPP_DTB_QUEUE_CFG_T结构体类型
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_down_init(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									DPP_DTB_QUEUE_CFG_T *p_queue_cfg);
+
+/***********************************************************/
+/** dtb队列dump初始化
+     * @param   dev_id           设备号，支持多芯片
+     * @param   queue_id         队列号
+     * @param   p_queue_cfg      队列配置参数，具体见DPP_DTB_QUEUE_CFG_T结构体类型
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_dump_init(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									DPP_DTB_QUEUE_CFG_T *p_queue_cfg);
+
+/***********************************************************/
+/** dtb队列down 空间地址配置
+     * @param   channelId    dtb通道号
+     * @param   phyAddr      down物理地址
+     * @param   virAddr      down虚拟地址
+     * @param   size         空间大小
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_down_channel_addr_set(DPP_DEV_T *dev, ZXIC_UINT32 channelId,
+										  ZXIC_UINT64 phyAddr,
+										  ZXIC_UINT64 virAddr,
+										  ZXIC_UINT32 size);
+
+/***********************************************************/
+/** dtb队列dump 空间地址配置
+     * @param   channelId    dtb通道号
+     * @param   phyAddr      dump物理地址
+     * @param   virAddr      dump虚拟地址
+     * @param   size         空间大小
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_dump_channel_addr_set(DPP_DEV_T *dev, ZXIC_UINT32 channelId,
+										  ZXIC_UINT64 phyAddr,
+										  ZXIC_UINT64 virAddr,
+										  ZXIC_UINT32 size);
+
+/***********************************************************/
+/** 释放队列资源
+     * @param   dev_id           设备号，支持多芯片
+     * @param   queue_id         分配到的队列号;
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2021/02/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_id_free(DPP_DEV_T *dev, ZXIC_UINT32 queue_id);
+
+/***********************************************************/
+/** 根据vport查找相应的队列号
+     * @param   dev_id       设备号，支持多芯片
+     * @param   vport        vport信息
+     * @param   p_queue_arr 找到到队列数组
+     * @param   p_num          找到的队列个数
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2023/09/13
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_id_search_by_vport(DPP_DEV_T *dev,
+											 ZXIC_UINT32 *p_queue_arr,
+											 ZXIC_UINT32 *p_num);
+
+/***********************************************************/
+/** 根据vport查找相应的队列号
+     * @param   dev_id       设备号，支持多芯片
+     * @param   vport        vport信息
+     * @param   p_queue_arr 找到到队列数组
+     * @param   p_num          找到的队列个数
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2023/09/13
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_id_get(ZXIC_UINT32 dev_id, DPP_PF_INFO_T *pf_info,
+								 ZXIC_UINT32 *queue);
+
+#endif
+
+#if ZXIC_REAL("DMA")
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/dma/dpp_dtb_cfg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/dma/dpp_dtb_cfg.h
old mode 100755
new mode 100644
index 08fdd244d51e828ad700e2e8398bf73d10116a0e..ea83873664dcf15deab3e2baf728108dd0e4ed80
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/dma/dpp_dtb_cfg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/dma/dpp_dtb_cfg.h
@@ -1,439 +1,192 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_dtb_cfg.h
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : zab
-* 完成日期 : 2022/08/23
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-#ifndef _DPP_DTB_CFG_H_
-#define _DPP_DTB_CFG_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "dpp_dev.h"
-
-#define DPP_DEV_SLOT_MAX                   (256)
-#define DPP_DTB_QUEUE_NUM_MAX              (128)
-#define DPP_DTB_TRAF_CTRL_RAM_SIZE         (256)
-#define DPP_DTB_TRAF_CTRL_RAM_5_SIZE       (64)
-#define DPP_DTB_DUMP_PD_RAM_SIZE           (2048)
-#define DPP_DTB_RD_CTRL_RAM_SIZE           (4096)
-#define DPP_DTB_RD_TABLE_RAM_SIZE          (8192)
-#define DPP_DTB_CMD_MAN_RAM_SIZE           (16384)
-
-/*vport格式
-15 |14 13 12 |     11    |10  9  8|7 6 5 4 3 2 1 0|
-rsv| ep_id   |func_active|func_num|    vfunc_num  |
-*/
-#define VPORT_EPID_BT_START          (12)  /*EPID起始位*/
-#define VPORT_EPID_BT_LEN            (3)  /*EPID长度*/
-#define VPORT_FUNC_ACTIVE_BT_START   (11)  /*FUNC_ACTIVE起始位*/
-#define VPORT_FUNC_ACTIVE_BT_LEN     (1)  /*FUNC_ACTIVE长度*/
-#define VPORT_FUNC_NUM_BT_START      (8)  /*FUNC_NUM起始位*/
-#define VPORT_FUNC_NUM_BT_LEN        (3)  /*FUNC_NUM长度*/
-#define VPORT_VFUNC_NUM_BT_START     (0)  /*FUNC_NUM起始位*/
-#define VPORT_VFUNC_NUM_BT_LEN       (8)  /*FUNC_NUM长度*/
-
-typedef struct dpp_dtb_queue_item_info_t
-{
-    ZXIC_UINT32 cmd_vld;
-    ZXIC_UINT32 cmd_type;
-    ZXIC_UINT32 int_en;
-    ZXIC_UINT32 data_len;
-    ZXIC_UINT32 data_laddr;
-    ZXIC_UINT32 data_hddr;
-} DPP_DTB_QUEUE_ITEM_INFO_T;
-
-typedef struct dpp_dtb_queue_vm_info_t
-{
-    ZXIC_UINT32 dbi_en;
-    ZXIC_UINT32 queue_en;
-    ZXIC_UINT32 epid;
-    ZXIC_UINT32 vfunc_num;
-    ZXIC_UINT32 vector;
-    ZXIC_UINT32 func_num;
-    ZXIC_UINT32 vfunc_active;
-} DPP_DTB_QUEUE_VM_INFO_T;
-
-#if ZXIC_REAL("DTB_CFG")
-/***********************************************************/
-/** DTB队列元素信息配置
-* @param   dev_id           芯片id
-* @param   queue_id         队列ID，范围0-127
-* @param   p_item_info      队列元素配置信息
-*
-* @return
-* @remark  无
-* @see
-* @author  zab      @date  2018/08/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_item_info_set(DPP_DEV_T *dev, 
-                        ZXIC_UINT32 queue_id,
-                        DPP_DTB_QUEUE_ITEM_INFO_T *p_item_info);
-
-/***********************************************************/
-/** 获取DTB队列中剩余未使用的条目数量
-* @param   dev_id               芯片id
-* @param   queue_id             队列ID，范围0-127
-* @param   p_item_num           剩余未使用条目数量
-*
-* @return
-* @remark  无
-* @see
-* @author  zab      @date  2018/08/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_unused_item_num_get(DPP_DEV_T *dev,
-                        ZXIC_UINT32 queue_id,
-                        ZXIC_UINT32 *p_item_num);
-
-/***********************************************************/
-/** 配置队列VM相关信息
-* @param   dev_id               芯片id
-* @param   queue_id             队列ID，范围0-127
-* @param   p_vm_info            VM配置信息
-*
-* @return
-* @remark  无
-* @see
-* @author  zab      @date  2018/08/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_vm_info_set(DPP_DEV_T *dev,
-                        ZXIC_UINT32 queue_id,
-                        DPP_DTB_QUEUE_VM_INFO_T *p_vm_info);
-
-
-/***********************************************************/
-/** 获取队列VM配置信息
-* @param   dev_id               оƬid
-* @param   queue_id             队列ID，范围0-127
-* @param   p_vm_info            VM配置信息
-*
-* @return
-* @remark  无
-* @see
-* @author  zab      @date  2018/08/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_vm_info_get(DPP_DEV_T *dev,
-                        ZXIC_UINT32 queue_id,
-                        DPP_DTB_QUEUE_VM_INFO_T *p_vm_info);
-
-/***********************************************************/
-/** 配置队列使能
-* @param   dev_id               芯片id
-* @param   queue_id             队列ID，范围0-127
-* @param   enable               1:队列使能,0:队列去使能
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/09/27
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_enable_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 queue_id,
-                                     ZXIC_UINT32 enable);
-
-/***********************************************************/
-/** 获取队列使能状态
-* @param   dev_id               芯片id
-* @param   queue_id             队列ID，范围0-127
-* @param   enable               1:队列使能,0:队列去使能
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/09/27
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_enable_get(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 queue_id,
-                                     ZXIC_UINT32 *enable);
-
-
-/***********************************************************/
-/** 配置 dtb 完成中断事件状态
-* @param   dev_id               芯片id
-* @param   queue_id             队列ID，范围0-127
-* @param   state                中断事件状态，1-发生中断，0-无中断发生
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/12
-************************************************************/
-ZXIC_UINT32 dpp_dtb_finish_interrupt_event_state_set(DPP_DEV_T *dev,
-                        ZXIC_UINT32 queue_id,
-                        ZXIC_UINT32 state);
-
-
-/***********************************************************/
-/** 清除 dtb 完成中断事件状态
-* @param   dev_id               芯片id
-* @param   queue_id             队列ID，范围0-127
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/12
-************************************************************/
-ZXIC_UINT32 dpp_dtb_finish_interrupt_event_state_clr(DPP_DEV_T *dev,
-                                                    ZXIC_UINT32 queue_id);
-
-ZXIC_UINT32 dpp_dtb_debug_mode_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_debug_mode);
-
-ZXIC_UINT32 dpp_dtb_mode_is_debug(DPP_DEV_T *dev); 
-
-/***********************************************************/
-/** 读取axi 最近一次读表相关信息
-* @param   dev_id           芯片id
-* @param   p_last_rd_table_addr_h      axim最近一次读表高地址
-* @param   p_last_rd_table_addr_l      axim最近一次读表低地址
-* @param   p_last_rd_table_len         axim最近一次读表长度
-* @param   p_last_rd_table_user        axim最近一次读表USER信号
-* @param   p_last_rd_table_onload_cnt  axim最近一次读表在线计数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_last_rd_table_info_get(DPP_DEV_T *dev, 
-                                               ZXIC_UINT32 *p_last_rd_table_addr_h,
-                                               ZXIC_UINT32 *p_last_rd_table_addr_l,
-                                               ZXIC_UINT32 *p_last_rd_table_len,
-                                               ZXIC_UINT32 *p_last_rd_table_user,
-                                               ZXIC_UINT32 *p_last_rd_table_onload_cnt
-                                               );
-
-/***********************************************************/
-/** 读表通道错误次数统计
-* @param   dev_id           芯片id
-* @param   p_axi_rd_table_resp_err_cnt      读表通道返回错误次数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_rd_table_resp_err_cnt_get(DPP_DEV_T *dev, 
-                                                  ZXIC_UINT32 *p_axi_rd_table_resp_err_cnt
-                                                  ); 
-
-/***********************************************************/
-/** 读取axi 最近一次读PD相关信息
-* @param   dev_id           芯片id
-* @param   p_last_rd_pd_addr_h      axim最近一次读PD高地址
-* @param   p_last_rd_pd_addr_l      axim最近一次读PD低地址
-* @param   p_last_rd_pd_len         axim最近一次读PD长度
-* @param   p_last_rd_pd_user        axim最近一次读PD USER信号
-* @param   p_last_rd_pd_onload_cnt  axim最近一次读PD在线计数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_last_rd_pd_info_get(DPP_DEV_T *dev, 
-                                            ZXIC_UINT32 *p_last_rd_pd_addr_h,
-                                            ZXIC_UINT32 *p_last_rd_pd_addr_l,
-                                            ZXIC_UINT32 *p_last_rd_pd_len,
-                                            ZXIC_UINT32 *p_last_rd_pd_user,
-                                            ZXIC_UINT32 *p_last_rd_pd_onload_cnt
-                                            );
-
-/***********************************************************/
-/** 读PD通道错误次数统计
-* @param   dev_id           芯片id
-* @param   p_axi_rd_pd_resp_err_cnt      读PD通道返回错误次数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_rd_pd_resp_err_cnt_get(DPP_DEV_T *dev,
-                                               ZXIC_UINT32 *p_axi_rd_pd_resp_err_cnt
-                                                ); 
-
-/***********************************************************/
-/** 读取axim 最近一次写控制相关信息
-* @param   dev_id           芯片id
-* @param   p_last_wr_ctrl_addr_h      axim最近一次写控制高地址
-* @param   p_last_wr_ctrl_addr_l      axim最近一次写控制低地址
-* @param   p_last_wr_ctrl_len         axim最近一次写控制长度
-* @param   p_last_wr_ctrl_user        axim最近一次写控制 USER信号
-* @param   p_last_wr_ctrl_onload_cnt  axim最近一次写控制在线计数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_last_wr_ctrl_info_get(DPP_DEV_T *dev, 
-                                              ZXIC_UINT32 *p_last_wr_ctrl_addr_h,
-                                              ZXIC_UINT32 *p_last_wr_ctrl_addr_l,
-                                              ZXIC_UINT32 *p_last_wr_ctrl_len,
-                                              ZXIC_UINT32 *p_last_wr_ctrl_user,
-                                              ZXIC_UINT32 *p_last_wr_ctrl_onload_cnt
-                                             );
-
-/***********************************************************/
-/** 获取写控制通道错误次数统计
-* @param   dev_id           芯片id
-* @param   p_axi_wr_ctrl_resp_err_cnt      写控制通道返回错误次数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_wr_ctrl_resp_err_cnt_get(DPP_DEV_T *dev,
-                                                ZXIC_UINT32 *p_axi_wr_ctrl_resp_err_cnt
-                                                );                                              
-
-/***********************************************************/
-/** 读取axim 最近一次写DDR相关信息
-* @param   dev_id           芯片id
-* @param   p_last_wr_ddr_addr_h      axim最近一次写控制高地址
-* @param   p_last_wr_ddr_addr_l      axim最近一次写控制低地址
-* @param   p_last_wr_ddr_len         axim最近一次写控制长度
-* @param   p_last_wr_ddr_user        axim最近一次写控制 USER信号
-* @param   p_last_wr_ddr_onload_cnt  axim最近一次写控制在线计数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_last_wr_ddr_info_get(DPP_DEV_T *dev,
-                                            ZXIC_UINT32 *p_last_wr_ddr_addr_h,
-                                            ZXIC_UINT32 *p_last_wr_ddr_addr_l,
-                                            ZXIC_UINT32 *p_last_wr_ddr_len,
-                                            ZXIC_UINT32 *p_last_wr_ddr_user,
-                                            ZXIC_UINT32 *p_last_wr_ddr_onload_cnt
-                                            ) ;
-
-/***********************************************************/
-/** 获取写DDR通道错误次数统计
-* @param   dev_id           芯片id
-* @param   p_axi_wr_ddr_resp_err_cnt      写DDR通道返回错误次数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_wr_ddr_resp_err_cnt_get(DPP_DEV_T *dev,
-                                                ZXIC_UINT32 *p_axi_wr_ddr_resp_err_cnt
-                                                ) ;  
-
-/***********************************************************/
-/** 读取axim 最近一次写完成相关信息
-* @param   dev_id           芯片id
-* @param   p_last_wr_fin_addr_h      axim最近一次写控制高地址
-* @param   p_last_wr_fin_addr_l      axim最近一次写控制低地址
-* @param   p_last_wr_fin_len         axim最近一次写控制长度
-* @param   p_last_wr_fin_user        axim最近一次写控制 USER信号
-* @param   p_last_wr_fin_onload_cnt  axim最近一次写控制在线计数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_last_wr_fin_info_get(DPP_DEV_T *dev, 
-                                             ZXIC_UINT32 *p_last_wr_fin_addr_h,
-                                             ZXIC_UINT32 *p_last_wr_fin_addr_l,
-                                             ZXIC_UINT32 *p_last_wr_fin_len,
-                                             ZXIC_UINT32 *p_last_wr_fin_user,
-                                             ZXIC_UINT32 *p_last_wr_fin_onload_cnt
-                                            ) ; 
-
-/***********************************************************/
-/** 获取写完成通道错误次数统计
-* @param   dev_id           芯片id
-* @param   p_axi_wr_fin_resp_err_cnt      写完成通道返回错误次数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_wr_fin_resp_err_cnt_get(DPP_DEV_T *dev,
-                                                ZXIC_UINT32 *p_axi_wr_fin_resp_err_cnt
-                                                ) ; 
-
-/***********************************************************/
-/** 读取 DTB 各通道状态机
-* @param   dev_id           芯片id
-* @param   p_wr_ctrl_state_info     写控制状态机
-* @param   p_rd_table_state_info    读表状态机
-* @param   p_rd_pd_state_info       读描述符数据状态机
-* @param   p_wr_ddr_state_info      写数据到ddr的状态机
-* @param   p_wr_fin_state_info      写结束标志的状态机
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_state_info_get(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 *p_wr_ctrl_state_info,
-                                   ZXIC_UINT32 *p_rd_table_state_info,
-                                   ZXIC_UINT32 *p_rd_pd_state_info,
-                                   ZXIC_UINT32 *p_wr_ddr_state_info,
-                                   ZXIC_UINT32 *p_dump_cmd_state_info
-                                   ); 
-                                                                                                                                                                                                                      
-/***********************************************************/
-/** 各通道错误统计打印
-* @param   dev_id       芯片的id号  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  cbb      @date  2022/11/11
-************************************************************/
-ZXIC_UINT32 diag_dpp_dtb_channels_axi_resp_err_cnt_prt(DPP_DEV_T *dev);
-
-/***********************************************************/
-/** AXIM最近一次操作信息记录打印
-* @param   dev_id       芯片的id号  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  cbb      @date  2022/11/11
-************************************************************/
-ZXIC_UINT32 diag_dpp_dtb_axi_last_operate_info_prt(DPP_DEV_T *dev);
-
-/***********************************************************/
-/** DTB 各通道状态机信息获取
-* @param   dev_id       芯片的id号  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  cbb      @date  2022/11/11
-************************************************************/
-ZXIC_UINT32 diag_dpp_dtb_channels_state_info_prt(DPP_DEV_T *dev);
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_dtb_cfg.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : zab
+* 完成日期 : 2022/08/23
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#ifndef _DPP_DTB_CFG_H_
+#define _DPP_DTB_CFG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dpp_dev.h"
+
+#define DPP_DEV_SLOT_MAX (256)
+#define DPP_DTB_QUEUE_NUM_MAX (128)
+#define DPP_DTB_TRAF_CTRL_RAM_SIZE (256)
+#define DPP_DTB_TRAF_CTRL_RAM_5_SIZE (64)
+#define DPP_DTB_DUMP_PD_RAM_SIZE (2048)
+#define DPP_DTB_RD_CTRL_RAM_SIZE (4096)
+#define DPP_DTB_RD_TABLE_RAM_SIZE (8192)
+#define DPP_DTB_CMD_MAN_RAM_SIZE (16384)
+
+/*vport格式
+15 |14 13 12 |     11    |10  9  8|7 6 5 4 3 2 1 0|
+rsv| ep_id   |func_active|func_num|    vfunc_num  |
+*/
+#define VPORT_EPID_BT_START (12) /*EPID起始位*/
+#define VPORT_EPID_BT_LEN (3) /*EPID长度*/
+#define VPORT_FUNC_ACTIVE_BT_START (11) /*FUNC_ACTIVE起始位*/
+#define VPORT_FUNC_ACTIVE_BT_LEN (1) /*FUNC_ACTIVE长度*/
+#define VPORT_FUNC_NUM_BT_START (8) /*FUNC_NUM起始位*/
+#define VPORT_FUNC_NUM_BT_LEN (3) /*FUNC_NUM长度*/
+#define VPORT_VFUNC_NUM_BT_START (0) /*FUNC_NUM起始位*/
+#define VPORT_VFUNC_NUM_BT_LEN (8) /*FUNC_NUM长度*/
+
+typedef struct dpp_dtb_queue_item_info_t {
+	ZXIC_UINT32 cmd_vld;
+	ZXIC_UINT32 cmd_type;
+	ZXIC_UINT32 int_en;
+	ZXIC_UINT32 data_len;
+	ZXIC_UINT32 data_laddr;
+	ZXIC_UINT32 data_hddr;
+} DPP_DTB_QUEUE_ITEM_INFO_T;
+
+typedef struct dpp_dtb_queue_vm_info_t {
+	ZXIC_UINT32 dbi_en;
+	ZXIC_UINT32 queue_en;
+	ZXIC_UINT32 epid;
+	ZXIC_UINT32 vfunc_num;
+	ZXIC_UINT32 vector;
+	ZXIC_UINT32 func_num;
+	ZXIC_UINT32 vfunc_active;
+} DPP_DTB_QUEUE_VM_INFO_T;
+
+#if ZXIC_REAL("DTB_CFG")
+/***********************************************************/
+/** DTB队列元素信息配置
+     * @param   dev_id           芯片id
+     * @param   queue_id         队列ID，范围0-127
+     * @param   p_item_info      队列元素配置信息
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2018/08/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_item_info_set(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+										DPP_DTB_QUEUE_ITEM_INFO_T * p_item_info);
+
+/***********************************************************/
+/** 获取DTB队列中剩余未使用的条目数量
+     * @param   dev_id               芯片id
+     * @param   queue_id             队列ID，范围0-127
+     * @param   p_item_num           剩余未使用条目数量
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2018/08/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_unused_item_num_get(DPP_DEV_T *dev,
+											  ZXIC_UINT32 queue_id,
+											  ZXIC_UINT32 *p_item_num);
+
+/***********************************************************/
+/** 配置队列VM相关信息
+     * @param   dev_id               芯片id
+     * @param   queue_id             队列ID，范围0-127
+     * @param   p_vm_info            VM配置信息
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2018/08/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_vm_info_set(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									  DPP_DTB_QUEUE_VM_INFO_T *p_vm_info);
+
+/***********************************************************/
+/** 获取队列VM配置信息
+     * @param   dev_id               оƬid
+     * @param   queue_id             队列ID，范围0-127
+     * @param   p_vm_info            VM配置信息
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  zab      @date  2018/08/23
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_vm_info_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									  DPP_DTB_QUEUE_VM_INFO_T *p_vm_info);
+
+/***********************************************************/
+/** 配置队列使能
+     * @param   dev_id               芯片id
+     * @param   queue_id             队列ID，范围0-127
+     * @param   enable               1:队列使能,0:队列去使能
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2023/09/27
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_enable_set(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									 ZXIC_UINT32 enable);
+
+/***********************************************************/
+/** 获取队列使能状态
+     * @param   dev_id               芯片id
+     * @param   queue_id             队列ID，范围0-127
+     * @param   enable               1:队列使能,0:队列去使能
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2023/09/27
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_enable_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									 ZXIC_UINT32 *enable);
+
+/***********************************************************/
+/** 配置 dtb 完成中断事件状态
+     * @param   dev_id               芯片id
+     * @param   queue_id             队列ID，范围0-127
+     * @param   state                中断事件状态，1-发生中断，0-无中断发生
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2022/11/12
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_finish_interrupt_event_state_set(DPP_DEV_T *dev,
+													 ZXIC_UINT32 queue_id,
+													 ZXIC_UINT32 state);
+
+/***********************************************************/
+/** 清除 dtb 完成中断事件状态
+     * @param   dev_id               芯片id
+     * @param   queue_id             队列ID，范围0-127
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2022/11/12
+     ************************************************************/
+ZXIC_UINT32 dpp_dtb_finish_interrupt_event_state_clr(DPP_DEV_T *dev,
+													 ZXIC_UINT32 queue_id);
+
+ZXIC_UINT32 dpp_dtb_debug_mode_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_debug_mode);
+
+ZXIC_UINT32 dpp_dtb_mode_is_debug(DPP_DEV_T *dev);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/nppu/dpp_pbu.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/nppu/dpp_pbu.h
index e2d3fc0f607433b2298fe420d86f63a1a49422fa..5642b5b617f0926e392c7048663384c8419d9398 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/nppu/dpp_pbu.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/nppu/dpp_pbu.h
@@ -1,458 +1,185 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_pbu.h
-* 文件标识 : 
-* 内容摘要 : 
-* 其它说明 : 
-* 当前版本 : 
-* 作    者 : djf
-* 完成日期 : 2014/04/14
-* DEPARTMENT: ASIC_FPGA_R&D_Dept 
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* 版 本 号:  
-* 修 改 人:  
-* 修改内容:  
-***************************************************************/
-#ifndef  _DPP_PBU_H_
-#define  _DPP_PBU_H_
-
-#include "dpp_nppu_reg.h"
-#include "dpp_pbu_api.h"
-
-#if ZXIC_REAL("macro")
-/******************************************************************************
- *                             START: 宏定义                              *
- *****************************************************************************/
-#define DPP_PBU_IND_CMD_WRT_FLAG     (0)
-#define DPP_PBU_IND_CMD_RD_FLAG        (1)
-
-#define PBU_FILE_PATH ("sa500t_pbu_output.txt")
-#define PBU_FILE_PATH_RAM ("sa500t_pbu_output_ram.txt")
-
-#define DPP_PBU_PORT_NUM         (119)           /** 物理端口号个数(0-128) */ 
-#define DPP_PBU_PORT_TH_MAX      (16380)         /** IDMA指针阈值最大值 */
-
-#define DPP_PBU_LIF0_PORT_NUM    (48)            /** lif0 48个通道对应的物理端口号个数(0-47)  */ 
-#define DPP_PBU_LIF1_PORT_NUM    (56)            /** lif1 8个通道对应的物理端口号个数(48~55)  */ 
-#define DPP_PBU_TM_LOOP_PORT_NUM    (113)            /** TM还回通道113  */ 
-
-
-#define DPP_PBU_COS_NUM          (8)             /** COS个数*/
-#define DPP_PBU_ALL_FTM_LINK_TH_NUM          (6)             /** COS个数*/
-#define DPP_PBU_IDMA_MAX_TH      (16380)         /** IDMA指针阈值最大值 */
-#define DPP_PBU_LIF_MAX_TH       (16384)         /** LIF指针阈值最大值 */
-#define DPP_PBU_MC_MAX_TH        (16380)         /** 组播指针阈值最大值 */
-#define DPP_PBU_PORT_COS_MAX_TH  (16380)         /** 单个端口指针阈值最大值 */
-#define DPP_PBU_MC_MAX_DIFF_TH   (255)           /** 组播指针申请逻辑复制和微码复制直接的阈值差最大值 */ 
-#define DPP_PBU_MC_MIN_DIFF_TH   (5)             /** 组播指针申请逻辑复制和微码复制直接的阈值差最小值 */
-#define DPP_PBU_CAP_DATA_MODE_MIN   (0)          /** PBU抓包数据模式最小值 */ 
-#define DPP_PBU_CAP_DATA_MODE_MAX   (12)         /** PBU抓包数据模式最大值 */ 
-
-#define DPP_PBU_CAP_FILTER_ADDR         (0x185)
-#define DPP_PBU_CAP_PKT_NUM      (64)            /** 抓包的最大分片个数 */
-
-/******************************************************************************
- *                              END: 宏定义                               *
- *****************************************************************************/ 
-#endif
-
-
-#if ZXIC_REAL("struct")
-
-
-typedef enum npe_pbu_ptr_rotate_e{
-    DPP_PBU_TOTAL_PTR_ROTATE = 0X1, /**<  @brief 全局指针翻转*/
-    DPP_PBU_MC_PTR_ROTATE    = 0X2,    /**<  @brief 组播指针翻转*/    
-    DPP_PBU_PORT_PTR_ROTATE  = 0X4,  /**<  @brief 端口指针翻转*/
- 
-}DPP_PBU_PTR_ROTATE_E;
-
-
-/******************************************************************************
- *                            START: 类型定义                             *
- *****************************************************************************/  
-typedef struct dpp_pbu_cnt_para_t
-{
-    ZXIC_UINT32 total_cnt;  /* 总指针计数 */
-    ZXIC_UINT32 idma_pub_cnt;  /* idma共享指针计数 */
-    ZXIC_UINT32 lif_pub_cnt;  /* lif共享指针计数 */
-    ZXIC_UINT32 mc_total_cnt;  /* mc总指针计数 */
-} DPP_PBU_CNT_PARA_T;
-/*
-typedef struct dpp_pbu_module_fc_rdy_t
-{
-    ZXIC_UINT32 pbu_oam_send_fc_rdy;
-    ZXIC_UINT32 pbu_lif_ctrl_rdy;
-    ZXIC_UINT32 pbu_odma_fc_rdy;
-    ZXIC_UINT32 pbu_tm_fc_rdy;
-    ZXIC_UINT32 pbu_idma_cos_rdy;
-}DPP_PBU_MODULE_FC_RDY_T;
-*/
-
-typedef struct dpp_mf_info_t
-{
-    ZXIC_CHAR* name;
-    ZXIC_UINT32 start_bit;
-    ZXIC_UINT32 end_bit;
-}DPP_MF_INFO_T;
-
-
-typedef enum dpp_pbu_ind_mem_id_e
-{
-    DPP_PBU_IDMATH_RAM= 0,          /**< @brief 端口阈值RAM，可读可写 */
-    DPP_PBU_MACTH_RAM = 1,          /**< @brief 端口COS阈值RAM，可读可写 */
-    DPP_PBU_CFG_IND_MEM_ID_INVALID = 2,      /**< @brief PBU CFG模块使用的内部表的个数 */
-} DPP_PBU_CFG_IND_MEM_ID_E;
-
-typedef enum dpp_pbu_stat_ind_mem_id_e
-{
-    DPP_PBU_PORT_CNT = 1,           /**< @brief 端口的指针计数，只读 */
-    DPP_PBU_STAT = 2,               /**< @brief PBU调试计数，只读 */
-    DPP_PBU_IFB_CFG = 3,            /**< @brief IFB中192字节报文，只读 */
-    DPP_PBU_CAPTURE_CFG = 4,        /**< @brief 报文抓包 可读可写 */
-    DPP_PBU_PORT_PUB_CNT = 5,
-    DPP_PBU_IND_MEM_ID_INVALID = 6,     /**< @brief PBU模块使用的内部表的个数*/
-} DPP_PBU_STAT_IND_MEM_ID_E;
-
-typedef enum dpp_idma_stat_ind_mem_id_e
-{
-    DPP_IDMA_STAT_RAM = 0,        
-    DPP_IDMA_DEBUG_RAM = 1,             
-    DPP_IDMA_IND_MEM_ID_INVALID = 2,     /**< @brief IDMA模块使用的内部表的个数*/
-} DPP_IDMA_STAT_IND_MEM_ID_E;
-
-typedef enum dpp_pbu_other_cnt_id_e
-{
-    DPP_PBU_IDMA_PTR_REQ_CNT  = 0,          /**< @brief idma指针申请计数，含无效申请 */
-    DPP_PBU_IDMA_RFD_WR_CNT   = 1,          /**< @brief idma写RFD计数 */
-    DPP_PBU_IDMA_IFB_WR1_CNT  = 2,          /**< @brief idma写ifb高64字节计数 */
-    DPP_PBU_IDMA_IFB_WR2_CNT  = 3,          /**< @brief idma写ifb低128字节计数 */
-    DPP_PBU_PPU_IFB_RD_CNT    = 4,          /**< @brief ppu读ifb申请计数 */
-    DPP_PBU_IFB_PPU_RDRSP_CNT = 5,          /**< @brief ifb返回给ppu包头计数 */
-    DPP_PBU_ODMA_RECY_PTR_CNT = 6,          /**< @brief odma指针回收个数 */
-    DPP_PBU_PPU_PF_REQ0_CNT   = 7,          /**< @brief ppu微码复制申请指针计数 */
-    DPP_PBU_PBU_PF_RSP0_CNT   = 8,          /**< @brief pbu返回微码复制申请指针计数 */
-    DPP_PBU_PPU_PF_REQ1_CNT   = 9,          /**< @brief ppu逻辑复制申请指针计数 */
-    DPP_PBU_PBU_PF_RSP1_CNT   = 10,         /**< @brief pbu返回逻辑复制申请指针计数 */
-    DPP_PBU_PPU_USE_PTR_CNT   = 11,         /**< @brief idma有效申请指针计数 */
-    DPP_PBU_PPU_WRBK_CNT      = 12,         /**< @brief ppu回写计数 */
-    DPP_PBU_PPU_REORDER_RSP_CNT  = 13,      /**< @brief pbu返回ppu回写参数计数 */
-    DPP_PBU_SE_PBU_KEY_VLD_CNT   = 14,      /**< @brief 深度解析请求计数 */
-    DPP_PBU_PBU_SE_RSP_VLD_CNT   = 15,      /**< @brief 深度解析返回计数 */
-    DPP_PBU_ODMA_IFB_RD1_CNT     = 16,      /**< @brief odma读ifb接口1读请求计数 */
-    DPP_PBU_ODMA_IFB_RD2_CNT     = 17,      /**< @brief odma读ifb接口2读请求计数 */
-    DPP_PBU_IDMA_O_ISU_PKT_CNT   = 18,      /**< @brief idma输出报文总计数 */
-    DPP_PBU_IDMA_O_ISU_EPKT_CNT  = 19,      /**< @brief idma输出带error标记的报文总计数 */
-    DPP_PBU_IDMA_DISPKT_CNT      = 20,      /**< @brief idma丢弃报文总数 */
-    DPP_PBU_OTHER_CNT_ID_INVALID,           /**< @brief PBU模块other计数的个数*/
-} DPP_PBU_OTHER_CNT_ID_E;
-
-
-typedef struct dpp_pbu_port_ptr_cnt_t
-{
-    ZXIC_UINT32 peak_port_cnt; /**< @brief 端口指针峰值 */
-    ZXIC_UINT32 current_port_cnt;/**< @brief 端口指针占用 */
-} DPP_PBU_PORT_PTR_CNT_T;
-
-typedef struct dpp_pbu_ifb_data_t
-{
-    ZXIC_UINT32 pbu_ifb_data[64];/**< @brief ifb数据 */
-} DPP_PBU_IFB_DATA_T;
-
-
-typedef struct dpp_pbu_all_ftm_link_th_t
-{
-    ZXIC_UINT32 total_congest_th[7];   /**<  @brief 拥塞阈值*/
-} DPP_PBU_ALL_FTM_LINK_TH_T;
-
-typedef struct
-{
-    ZXIC_UINT32 pbu_lif_group0_pfc_rdy[12];
-} DPP_PBU_LIF_GROUP_PFC_RDY;
-
-
-
-/******************************************************************************
- *                             END: 类型定义                              *
- *****************************************************************************/ 
-#endif
-
-#if 1
-/******************************************************************************
- *                            START: 函数声明                             *
- *****************************************************************************/
-#if 0
-DPP_STATUS dpp_pbu_idma_public_th_set(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 th);
-DPP_STATUS dpp_pbu_idma_public_th_get(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 *p_th);
-DPP_STATUS dpp_pbu_lif_public_th_set(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 th);
-DPP_STATUS dpp_pbu_lif_public_th_get(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 *p_th);
-DPP_STATUS dpp_pbu_idma_total_th_set(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 th);
-DPP_STATUS dpp_pbu_idma_total_th_get(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 *p_th);
-DPP_STATUS dpp_pbu_lif_total_th_set(ZXIC_UINT32 dev_id,
-                                        ZXIC_UINT32 th);
-DPP_STATUS dpp_pbu_lif_total_th_get(ZXIC_UINT32 dev_id,
-                                        ZXIC_UINT32 *p_th);
-DPP_STATUS dpp_pbu_mc_total_th_set(ZXIC_UINT32 dev_id,
-                                       ZXIC_UINT32 th);
-DPP_STATUS dpp_pbu_mc_total_th_get(ZXIC_UINT32 dev_id,
-                                       ZXIC_UINT32 *p_th);
-
-DPP_STATUS dpp_pbu_mc_cos_para_get(ZXIC_UINT32 dev_id,
-                                       DPP_PBU_MC_COS_PARA_T *p_para);
-DPP_STATUS dpp_pbu_sa_ip_en_set(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 en);
-DPP_STATUS dpp_pbu_sa_ip_en_get(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 *p_en);
-DPP_STATUS dpp_pbu_cnt_ovfl_mode_set(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 mode);
-DPP_STATUS dpp_pbu_cnt_ovfl_mode_get(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 *p_mode);
-DPP_STATUS dpp_pbu_cnt_rdclr_mode_set(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 mode);
-DPP_STATUS dpp_pbu_cnt_rdclr_mode_get(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 *p_mode);
-DPP_STATUS dpp_pbu_mc_diff_th_set(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 th);
-DPP_STATUS dpp_pbu_mc_diff_th_get(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 *p_th);
-DPP_STATUS dpp_pbu_peak_port_cnt_clr_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 port_no, ZXIC_UINT32 peak_port_cnt_clr);
-DPP_STATUS dpp_pbu_peak_port_cnt_clr_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 port_no, ZXIC_UINT32* p_peak_port_cnt_clr);
-DPP_STATUS dpp_pbu_all_ftm_crdt_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 port_no, DPP_NPPU_PBU_CFG_ALL_FTM_CRDT_TH_T* p_all_ftm_crdt_th);
-DPP_STATUS dpp_pbu_all_ftm_crdt_th_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 port_no, DPP_NPPU_PBU_CFG_ALL_FTM_CRDT_TH_T* p_all_ftm_crdt_th);
-DPP_STATUS dpp_pbu_all_ftm_link_th_set(ZXIC_UINT32 dev_id,
-                                       DPP_PBU_ALL_FTM_LINK_TH_T *p_para);
-DPP_STATUS dpp_pbu_all_ftm_link_th_get(ZXIC_UINT32 dev_id,
-                                       DPP_PBU_ALL_FTM_LINK_TH_T *p_para);
-DPP_STATUS dpp_pbu_ftm_total_congest_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 total_congest_th);
-DPP_STATUS dpp_pbu_ftm_total_congest_th_get(ZXIC_UINT32 dev_id, ZXIC_UINT32* total_congest_th);
-DPP_STATUS dpp_pbu_crdt_mode_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crdt_mode);
-DPP_STATUS dpp_pbu_crdt_mode_get(ZXIC_UINT32 dev_id, ZXIC_UINT32* p_crdt_mode);
-DPP_STATUS dpp_pbu_ind_reg_mode_status_check(ZXIC_UINT32 dev_id, ZXIC_UINT32 sub_module_ind_status_reg, ZXIC_UINT32 sleep_time);
-DPP_STATUS dpp_pbu_ind_cmd_reg_set(ZXIC_UINT32 dev_id,
-                                       ZXIC_UINT32 mem_addr,
-                                       ZXIC_UINT32 mem_id,
-                                       ZXIC_UINT32 wrt_rd_flag);
-DPP_STATUS dpp_pbu_ind_data_reg_set(ZXIC_UINT32 dev_id,
-                                        ZXIC_UINT32 len,
-                                        ZXIC_UINT32 *p_data,
-                                        ZXIC_UINT32 data_reg_base);
-DPP_STATUS dpp_pbu_ind_data_reg_get(ZXIC_UINT32 dev_id,
-                                        ZXIC_UINT32 len,
-                                        ZXIC_UINT32 *p_data,
-                                        ZXIC_UINT32 data_reg_base);
-DPP_STATUS dpp_pbu_cfg_ind_wrt(ZXIC_UINT32 dev_id,
-                               ZXIC_UINT32 mem_addr,
-                               DPP_PBU_CFG_IND_MEM_ID_E mem_id,
-                               ZXIC_UINT32 len,
-                               ZXIC_UINT32 *p_data);
-DPP_STATUS dpp_pbu_cfg_ind_rd(ZXIC_UINT32 dev_id,
-                              ZXIC_UINT32 mem_addr,
-                              DPP_PBU_CFG_IND_MEM_ID_E mem_id,
-                              ZXIC_UINT32 len,
-                              ZXIC_UINT32 *p_data);
-#endif                              
-DPP_STATUS dpp_pbu_port_th_get(DPP_DEV_T *dev,
-                               ZXIC_UINT32 port_id,
-                               DPP_PBU_PORT_TH_PARA_T *p_para);
-DPP_STATUS dpp_pbu_port_cos_th_get(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 port_id,
-                                   DPP_PBU_PORT_COS_TH_PARA_T *p_para);
-#if 0
-DPP_STATUS dpp_pbu_cnt_clr_all(ZXIC_UINT32 dev_id);
-DPP_STATUS dpp_pbu_int_flag_prt(ZXIC_UINT32 dev_id);
-DPP_STATUS dpp_pbu_stat_cnt_para_get(ZXIC_UINT32 dev_id,
-                                     DPP_PBU_CNT_PARA_T *p_para);
-DPP_STATUS dpp_pbu_stat_thram_init_done_check(ZXIC_UINT32 dev_id,
-                                              ZXIC_UINT32 *p_rdy);
-DPP_STATUS dpp_pbu_stat_fptr_init_done_check(ZXIC_UINT32 dev_id,
-                                             ZXIC_UINT32 *p_rdy);
-DPP_STATUS dpp_pbu_fc_rdy_get(ZXIC_UINT32 dev_id,
-                              DPP_NPPU_PBU_STAT_PBU_FC_RDY_T* p_pbu_module_fc);
-DPP_STATUS dpp_pbu_lif_fc_rdy_get(ZXIC_UINT32 dev_id,
-                              DPP_NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY0_T* p_pbu_group0_rdy0);
-DPP_STATUS dpp_pbu_lif_pfc_rdy_get(ZXIC_UINT32 dev_id, DPP_PBU_LIF_GROUP_PFC_RDY *p_lif_group0_pfc_rdy);   
-DPP_STATUS dpp_pbu_pktrx_mr_pfc_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_pbu_pktrx_mr_pfc);                                    
-DPP_STATUS dpp_pbu_stat_reg_mode_status_check(ZXIC_UINT32 dev_id, ZXIC_UINT32 sub_module_ind_status_reg, ZXIC_UINT32 sleep_time);
-DPP_STATUS dpp_pbu_stat_ind_cmd_reg_set(ZXIC_UINT32 dev_id,
-                                        ZXIC_UINT32 mem_addr,
-                                        ZXIC_UINT32 mem_id,
-                                        ZXIC_UINT32 wrt_rd_flag);
-DPP_STATUS dpp_pbu_stat_ind_data_reg_set(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 len,
-                                         ZXIC_UINT32 *p_data);
-DPP_STATUS dpp_pbu_stat_ind_data_reg_get(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 len,
-                                         ZXIC_UINT32 *p_data);
-DPP_STATUS dpp_pbu_stat_ind_wrt(ZXIC_UINT32 dev_id,
-                                ZXIC_UINT32 mem_addr,
-                                DPP_PBU_STAT_IND_MEM_ID_E mem_id,
-                                ZXIC_UINT32 len,
-                                ZXIC_UINT32 *p_data);
-DPP_STATUS dpp_pbu_stat_ind_rd(ZXIC_UINT32 dev_id,
-                               ZXIC_UINT32 mem_addr,
-                               DPP_PBU_STAT_IND_MEM_ID_E mem_id,
-                               ZXIC_UINT32 len,
-                               ZXIC_UINT32 *p_data);
-DPP_STATUS dpp_pbu_stat_port_ptr_cnt_get(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 port_id,
-                                         DPP_PBU_PORT_PTR_CNT_T *p_port_ptr_cnt);
-DPP_STATUS dpp_pbu_stat_ifb_req_vld_cnt_get(ZXIC_UINT32 dev_id,
-                                            ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_stat_ifb_rsp_vld_cnt_get(ZXIC_UINT32 dev_id,
-                                            ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_stat_odma_recy_ptr_cnt_get(ZXIC_UINT32 dev_id,
-                                              ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_stat_mcode_pf_req_cnt_get(ZXIC_UINT32 dev_id,
-                                             ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_stat_mcode_pf_rsp_cnt_get(ZXIC_UINT32 dev_id,
-                                             ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_stat_logic_pf_req_cnt_get(ZXIC_UINT32 dev_id,
-                                             ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_stat_logic_pf_rsp_cnt_get(ZXIC_UINT32 dev_id,
-                                             ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_stat_ppu_use_ptr_pulse_cnt_get(ZXIC_UINT32 dev_id,
-                                                  ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_stat_ppu_wb_vld_cnt_get(ZXIC_UINT32 dev_id,
-                                           ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_stat_ppu_reorder_para_cnt_get(ZXIC_UINT32 dev_id,
-                                                 ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_stat_se_dpi_key_vld_cnt_get(ZXIC_UINT32 dev_id,
-                                               ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_stat_se_dpi_rsp_vld_cnt_get(ZXIC_UINT32 dev_id,
-                                               ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_stat_odma_ifb_rd1_cnt_get(ZXIC_UINT32 dev_id,
-                                             ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_stat_odma_ifb_rd2_cnt_get(ZXIC_UINT32 dev_id,
-                                             ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_stat_mcode_pf_no_rsp_cnt_get(ZXIC_UINT32 dev_id,
-                                                ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_stat_logic_pf_no_rsp_cnt_get(ZXIC_UINT32 dev_id,
-                                                ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_stat_ifb_data_get(ZXIC_UINT32 dev_id,
-                                     DPP_PBU_IFB_DATA_T *p_data);
-DPP_STATUS dpp_pbu_stat_port_public_ptr_cnt_get(ZXIC_UINT32 dev_id,
-                                                ZXIC_UINT32 port_no,
-                                                ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_idma_cfg_cnt_ovfl_mode_set(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 mode);
-DPP_STATUS dpp_idma_cfg_cnt_ovfl_mode_get(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 *p_mode);
-DPP_STATUS dpp_idma_cfg_cnt_rdclr_mode_set(ZXIC_UINT32 dev_id,
-                                           ZXIC_UINT32 mode);
-DPP_STATUS dpp_idma_cfg_cnt_rdclr_mode_get(ZXIC_UINT32 dev_id,
-                                           ZXIC_UINT32 *p_mode);
-DPP_STATUS dpp_idma_stat_ind_reg_mode_status_check(ZXIC_UINT32 dev_id, ZXIC_UINT32 sub_module_ind_status_reg, ZXIC_UINT32 sleep_time);
-DPP_STATUS dpp_idma_stat_ind_cmd_reg_set(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 mem_addr,
-                                         ZXIC_UINT32 mem_id,
-                                         ZXIC_UINT32 wrt_rd_flag);
-DPP_STATUS dpp_idma_stat_ind_data_reg_set(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 *p_data);
-DPP_STATUS dpp_idma_stat_ind_data_reg_get(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 *p_data);
-DPP_STATUS dpp_idma_stat_ind_wrt(ZXIC_UINT32 dev_id,
-                                 ZXIC_UINT32 mem_addr,
-                                 DPP_IDMA_STAT_IND_MEM_ID_E mem_id,
-                                 ZXIC_UINT32 *p_data);
-DPP_STATUS dpp_idma_stat_ind_rd(ZXIC_UINT32 dev_id,
-                                ZXIC_UINT32 mem_addr,
-                                DPP_IDMA_STAT_IND_MEM_ID_E mem_id,
-                                ZXIC_UINT32 *p_data);
-DPP_STATUS dpp_idma_stat_to_isu_total_cnt_get(ZXIC_UINT32 dev_id,
-                                              ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_idma_stat_to_isu_err_total_cnt_get(ZXIC_UINT32 dev_id,
-                                                  ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_idma_stat_disc_total_cnt_get(ZXIC_UINT32 dev_id,
-                                            ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_idma_stat_port_to_isu_cnt_get(ZXIC_UINT32 dev_id,
-                                             ZXIC_UINT32 port_no,
-                                             ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_idma_stat_port_to_isu_err_cnt_get(ZXIC_UINT32 dev_id,
-                                                 ZXIC_UINT32 port_no,
-                                                 ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_idma_stat_port_disc_cnt_get(ZXIC_UINT32 dev_id,
-                                           ZXIC_UINT32 port_no,
-                                           ZXIC_UINT32 *p_cnt);
-DPP_STATUS dpp_pbu_cap_data_mode_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 mod_data);
-DPP_STATUS dpp_pbu_pkt_capture_start(ZXIC_UINT32 dev_id, ZXIC_UINT32 pkt_num);
-DPP_STATUS dpp_pbu_pkt_capture_stop(ZXIC_UINT32 dev_id);
-DPP_STATUS dpp_pbu_pkt_capture_mode_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 mode);
-DPP_STATUS dpp_pbu_pkt_capture_cnt(ZXIC_UINT32 dev_id, ZXIC_UINT32* pkt_num);
-DPP_STATUS dpp_pbu_pkt_capture_dbg_print(ZXIC_UINT32 dev_id);
-DPP_STATUS dpp_pbu_pkt_capture_cnt_print(ZXIC_UINT32 dev_id);
-DPP_STATUS dpp_pbu_pkt_capture_print_one(ZXIC_UINT32 dev_id, ZXIC_UINT32 pkt_no);
-DPP_STATUS dpp_pbu_pkt_capture_print(ZXIC_UINT32 dev_id,
-                                     ZXIC_UINT32 pkt_start_no,
-                                     ZXIC_UINT32 pkt_end_no);
-DPP_STATUS dpp_pbu_pkt_capture_print_all(ZXIC_UINT32 dev_id);
-DPP_STATUS dpp_pbu_pkt_capture_filter_set_bit(ZXIC_UINT32 dev_id,
-                                              ZXIC_UINT32 bit_no,
-                                              ZXIC_UINT32 filter_mode
-                                             );
-DPP_STATUS dpp_pbu_pkt_capture_filter_set(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 bit_start_no,
-                                          ZXIC_UINT32 bit_end_no,
-                                          ZXIC_UINT32 filter_mode);
-DPP_STATUS dpp_pbu_pkt_capture_filter_mask_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 start, ZXIC_UINT32 end, ZXIC_UINT32 mask, ZXIC_UINT32 data);
-DPP_STATUS dpp_pbu_pkt_capture_filter_pkt_mask_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 start, ZXIC_UINT32 end, ZXIC_UINT32 mask, ZXIC_UINT32 data);
-DPP_STATUS dpp_pbu_pkt_capture_filter_sport_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 port);
-DPP_STATUS dpp_pbu_pkt_capture_filter_dport_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 port);
-DPP_STATUS dpp_pbu_pkt_capture_filter_clr_bit(ZXIC_UINT32 dev_id,
-                                              ZXIC_UINT32 bit_no);
-DPP_STATUS dpp_pbu_pkt_capture_filter_clr(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 bit_start_no,
-                                          ZXIC_UINT32 bit_end_no);
-DPP_STATUS dpp_pbu_pkt_capture_filter_clr_all(ZXIC_UINT32 dev_id);
-/***********************************************************/
-/** 抓包报文分片打印by mf bit
-* @param   dev_id    芯片ID
-* @param   pkt_no    要打印的分片号
-*
-* @return
-* @remark  无
-* @see
-* @author  czd      @date  2015/04/29
-************************************************************/
-DPP_STATUS dpp_pbu_pkt_capture_print_one_mf_by_bit(ZXIC_UINT32 dev_id, ZXIC_UINT32 pkt_no);
-
-DPP_STATUS dpp_pbu_glb_mgr_get(ZXIC_UINT32 dev_id,
-                               ZXIC_UINT32 *p_flag,
-                               ZXIC_UINT32 *p_size,
-                               ZXIC_UINT8 **pp_data_buff);
-DPP_STATUS dpp_pbu_glb_mgr_set(ZXIC_UINT32 dev_id,
-                               ZXIC_UINT32 size,
-                               ZXIC_UINT8 *p_data_buff);
-DPP_STATUS dpp_pbu_glb_size_get(ZXIC_UINT32 dev_id,
-                                ZXIC_UINT32 *p_size);
-
-ZXIC_UINT32 sim_soc_mf_field_print(ZXIC_UINT8 *pkt_buff);
-
-
-DPP_STATUS dpp_pbu_pkt_capture_print_mf_by_bit(ZXIC_UINT32 dev_id,
-                                     ZXIC_UINT32 pkt_start_no,
-                                     ZXIC_UINT32 pkt_end_no);
-DPP_STATUS dpp_pbu_pkt_capture_print_one_simple_mf_by_bit(ZXIC_UINT32 dev_id, ZXIC_UINT32 pkt_no);
-
-DPP_STATUS dpp_pbu_pkt_capture_print_all_mf_by_bit(ZXIC_UINT32 dev_id);
-
-#endif
-
-/******************************************************************************
- *                             END: 函数声明                              *
- *****************************************************************************/
-#endif
-
-#endif /* _DPP_PBU_H_ */
-/* 必须有个空行，否则可能编不过 */
-
-
-
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_pbu.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : djf
+* 完成日期 : 2014/04/14
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#ifndef _DPP_PBU_H_
+#define _DPP_PBU_H_
+
+#include "dpp_nppu_reg.h"
+#include "dpp_pbu_api.h"
+
+#if ZXIC_REAL("macro")
+/******************************************************************************
+ *                             START: 宏定义                              *
+ *****************************************************************************/
+#define DPP_PBU_IND_CMD_WRT_FLAG (0)
+#define DPP_PBU_IND_CMD_RD_FLAG (1)
+
+#define PBU_FILE_PATH ("sa500t_pbu_output.txt")
+#define PBU_FILE_PATH_RAM ("sa500t_pbu_output_ram.txt")
+
+#define DPP_PBU_PORT_NUM (119) /** 物理端口号个数(0-128) */
+#define DPP_PBU_PORT_TH_MAX (16380) /** IDMA指针阈值最大值 */
+
+#define DPP_PBU_LIF0_PORT_NUM \
+	(48) /** lif0 48个通道对应的物理端口号个数(0-47)  */
+#define DPP_PBU_LIF1_PORT_NUM \
+	(56) /** lif1 8个通道对应的物理端口号个数(48~55)  */
+#define DPP_PBU_TM_LOOP_PORT_NUM (113) /** TM还回通道113  */
+
+#define DPP_PBU_COS_NUM (8) /** COS个数*/
+#define DPP_PBU_ALL_FTM_LINK_TH_NUM (6) /** COS个数*/
+#define DPP_PBU_IDMA_MAX_TH (16380) /** IDMA指针阈值最大值 */
+#define DPP_PBU_LIF_MAX_TH (16384) /** LIF指针阈值最大值 */
+#define DPP_PBU_MC_MAX_TH (16380) /** 组播指针阈值最大值 */
+#define DPP_PBU_PORT_COS_MAX_TH (16380) /** 单个端口指针阈值最大值 */
+#define DPP_PBU_MC_MAX_DIFF_TH \
+	(255) /** 组播指针申请逻辑复制和微码复制直接的阈值差最大值 */
+#define DPP_PBU_MC_MIN_DIFF_TH \
+	(5) /** 组播指针申请逻辑复制和微码复制直接的阈值差最小值 */
+#define DPP_PBU_CAP_DATA_MODE_MIN (0) /** PBU抓包数据模式最小值 */
+#define DPP_PBU_CAP_DATA_MODE_MAX (12) /** PBU抓包数据模式最大值 */
+
+#define DPP_PBU_CAP_FILTER_ADDR (0x185)
+#define DPP_PBU_CAP_PKT_NUM (64) /** 抓包的最大分片个数 */
+
+/******************************************************************************
+ *                              END: 宏定义                               *
+ *****************************************************************************/
+#endif
+
+#if ZXIC_REAL("struct")
+
+typedef enum npe_pbu_ptr_rotate_e {
+	DPP_PBU_TOTAL_PTR_ROTATE = 0X1, /**<  @brief 全局指针翻转*/
+	DPP_PBU_MC_PTR_ROTATE = 0X2, /**<  @brief 组播指针翻转*/
+	DPP_PBU_PORT_PTR_ROTATE = 0X4, /**<  @brief 端口指针翻转*/
+
+} DPP_PBU_PTR_ROTATE_E;
+
+/******************************************************************************
+ *                            START: 类型定义                             *
+ *****************************************************************************/
+typedef struct dpp_pbu_cnt_para_t {
+	ZXIC_UINT32 total_cnt; /* 总指针计数 */
+	ZXIC_UINT32 idma_pub_cnt; /* idma共享指针计数 */
+	ZXIC_UINT32 lif_pub_cnt; /* lif共享指针计数 */
+	ZXIC_UINT32 mc_total_cnt; /* mc总指针计数 */
+} DPP_PBU_CNT_PARA_T;
+/*
+typedef struct dpp_pbu_module_fc_rdy_t
+{
+    ZXIC_UINT32 pbu_oam_send_fc_rdy;
+    ZXIC_UINT32 pbu_lif_ctrl_rdy;
+    ZXIC_UINT32 pbu_odma_fc_rdy;
+    ZXIC_UINT32 pbu_tm_fc_rdy;
+    ZXIC_UINT32 pbu_idma_cos_rdy;
+}DPP_PBU_MODULE_FC_RDY_T;
+*/
+
+typedef struct dpp_mf_info_t {
+	ZXIC_CHAR *name;
+	ZXIC_UINT32 start_bit;
+	ZXIC_UINT32 end_bit;
+} DPP_MF_INFO_T;
+
+typedef enum dpp_pbu_ind_mem_id_e {
+	DPP_PBU_IDMATH_RAM = 0, /**< @brief 端口阈值RAM，可读可写 */
+	DPP_PBU_MACTH_RAM = 1, /**< @brief 端口COS阈值RAM，可读可写 */
+	DPP_PBU_CFG_IND_MEM_ID_INVALID =
+			2, /**< @brief PBU CFG模块使用的内部表的个数 */
+} DPP_PBU_CFG_IND_MEM_ID_E;
+
+typedef enum dpp_pbu_stat_ind_mem_id_e {
+	DPP_PBU_PORT_CNT = 1, /**< @brief 端口的指针计数，只读 */
+	DPP_PBU_STAT = 2, /**< @brief PBU调试计数，只读 */
+	DPP_PBU_IFB_CFG = 3, /**< @brief IFB中192字节报文，只读 */
+	DPP_PBU_CAPTURE_CFG = 4, /**< @brief 报文抓包 可读可写 */
+	DPP_PBU_PORT_PUB_CNT = 5,
+	DPP_PBU_IND_MEM_ID_INVALID = 6, /**< @brief PBU模块使用的内部表的个数*/
+} DPP_PBU_STAT_IND_MEM_ID_E;
+
+typedef enum dpp_idma_stat_ind_mem_id_e {
+	DPP_IDMA_STAT_RAM = 0,
+	DPP_IDMA_DEBUG_RAM = 1,
+	DPP_IDMA_IND_MEM_ID_INVALID = 2, /**< @brief IDMA模块使用的内部表的个数*/
+} DPP_IDMA_STAT_IND_MEM_ID_E;
+
+typedef enum dpp_pbu_other_cnt_id_e {
+	DPP_PBU_IDMA_PTR_REQ_CNT = 0, /**< @brief idma指针申请计数，含无效申请 */
+	DPP_PBU_IDMA_RFD_WR_CNT = 1, /**< @brief idma写RFD计数 */
+	DPP_PBU_IDMA_IFB_WR1_CNT = 2, /**< @brief idma写ifb高64字节计数 */
+	DPP_PBU_IDMA_IFB_WR2_CNT = 3, /**< @brief idma写ifb低128字节计数 */
+	DPP_PBU_PPU_IFB_RD_CNT = 4, /**< @brief ppu读ifb申请计数 */
+	DPP_PBU_IFB_PPU_RDRSP_CNT = 5, /**< @brief ifb返回给ppu包头计数 */
+	DPP_PBU_ODMA_RECY_PTR_CNT = 6, /**< @brief odma指针回收个数 */
+	DPP_PBU_PPU_PF_REQ0_CNT = 7, /**< @brief ppu微码复制申请指针计数 */
+	DPP_PBU_PBU_PF_RSP0_CNT = 8, /**< @brief pbu返回微码复制申请指针计数 */
+	DPP_PBU_PPU_PF_REQ1_CNT = 9, /**< @brief ppu逻辑复制申请指针计数 */
+	DPP_PBU_PBU_PF_RSP1_CNT = 10, /**< @brief pbu返回逻辑复制申请指针计数 */
+	DPP_PBU_PPU_USE_PTR_CNT = 11, /**< @brief idma有效申请指针计数 */
+	DPP_PBU_PPU_WRBK_CNT = 12, /**< @brief ppu回写计数 */
+	DPP_PBU_PPU_REORDER_RSP_CNT = 13, /**< @brief pbu返回ppu回写参数计数 */
+	DPP_PBU_SE_PBU_KEY_VLD_CNT = 14, /**< @brief 深度解析请求计数 */
+	DPP_PBU_PBU_SE_RSP_VLD_CNT = 15, /**< @brief 深度解析返回计数 */
+	DPP_PBU_ODMA_IFB_RD1_CNT = 16, /**< @brief odma读ifb接口1读请求计数 */
+	DPP_PBU_ODMA_IFB_RD2_CNT = 17, /**< @brief odma读ifb接口2读请求计数 */
+	DPP_PBU_IDMA_O_ISU_PKT_CNT = 18, /**< @brief idma输出报文总计数 */
+	DPP_PBU_IDMA_O_ISU_EPKT_CNT =
+			19, /**< @brief idma输出带error标记的报文总计数 */
+	DPP_PBU_IDMA_DISPKT_CNT = 20, /**< @brief idma丢弃报文总数 */
+	DPP_PBU_OTHER_CNT_ID_INVALID, /**< @brief PBU模块other计数的个数*/
+} DPP_PBU_OTHER_CNT_ID_E;
+
+typedef struct dpp_pbu_port_ptr_cnt_t {
+	ZXIC_UINT32 peak_port_cnt; /**< @brief 端口指针峰值 */
+	ZXIC_UINT32 current_port_cnt; /**< @brief 端口指针占用 */
+} DPP_PBU_PORT_PTR_CNT_T;
+
+typedef struct dpp_pbu_ifb_data_t {
+	ZXIC_UINT32 pbu_ifb_data[64]; /**< @brief ifb数据 */
+} DPP_PBU_IFB_DATA_T;
+
+typedef struct dpp_pbu_all_ftm_link_th_t {
+	ZXIC_UINT32 total_congest_th[7]; /**<  @brief 拥塞阈值*/
+} DPP_PBU_ALL_FTM_LINK_TH_T;
+
+typedef struct {
+	ZXIC_UINT32 pbu_lif_group0_pfc_rdy[12];
+} DPP_PBU_LIF_GROUP_PFC_RDY;
+
+/******************************************************************************
+ *                             END: 类型定义                              *
+ *****************************************************************************/
+#endif
+
+#if 1
+/******************************************************************************
+ *                            START: 函数声明                             *
+ *****************************************************************************/
+DPP_STATUS dpp_pbu_port_th_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+							   DPP_PBU_PORT_TH_PARA_T *p_para);
+DPP_STATUS dpp_pbu_port_cos_th_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+								   DPP_PBU_PORT_COS_TH_PARA_T *p_para);
+
+/******************************************************************************
+ *                             END: 函数声明                              *
+ *****************************************************************************/
+#endif
+
+#endif /* _DPP_PBU_H_ */
+/* 必须有个空行，否则可能编不过 */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/ppu/dpp_ppu.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/ppu/dpp_ppu.h
old mode 100755
new mode 100644
index 3a0798906e92a6a68732873fa80a0bf51b463ca2..bbfd77ef0fc80ba57484adccf317321d655e6644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/ppu/dpp_ppu.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/ppu/dpp_ppu.h
@@ -1,104 +1,110 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_ppu.h
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : 王春雷
-* 完成日期 : 2014/03/18
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-
-#ifndef _DPP_PPU_H_
-#define _DPP_PPU_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "dpp_module.h"
-#include "dpp_ppu_api.h"
-#include "dpp_ppu_reg.h"
-#include "zxic_comm_thread.h"
-
-#define PPU_CLS_ME_NUM         (8)
-#define PPU_INSTR_MEM_NUM      (3)    /*ppu中的微码指令空间数量 2个cluster 共用一个指令空间*/
-#define PPU_INSTR_REG_NUM      (4)    /*ppu中指令空间中的数据寄存器数目*/
-#define PPU_INSTR_NUM_MAX      (32*1024)    /* xjw mod at 18.6.2 from 16k to 32k */
-#define PPU_SDT_IDX_MIN        (0)
-#define PPU_SDT_IDX_MAX        (255)
-#define PPU_DUP_IDX_MIN        (0)
-#define PPU_DUP_IDX_MAX        (63)
-#define PPU_INSTR_COL_MAX      (4)
-
-/**  ME指令调试中断*/
-#define PPU_ME0_INT_BT_START   (0)
-#define PPU_ME0_INT_BT_LEN     (1)
-#define PPU_ME1_INT_BT_START   (1)
-#define PPU_ME1_INT_BT_LEN     (1)
-#define PPU_ME2_INT_BT_START   (2)
-#define PPU_ME2_INT_BT_LEN     (1)
-#define PPU_ME3_INT_BT_START   (3)
-#define PPU_ME3_INT_BT_LEN     (1)
-#define PPU_ME4_INT_BT_START   (4)
-#define PPU_ME4_INT_BT_LEN     (1)
-#define PPU_ME5_INT_BT_START   (5)
-#define PPU_ME5_INT_BT_LEN     (1)
-#define PPU_ME6_INT_BT_START   (6)
-#define PPU_ME6_INT_BT_LEN     (1)
-#define PPU_ME7_INT_BT_START   (7)
-#define PPU_ME7_INT_BT_LEN     (1)
-
-#define DPP_FPGA_MAX_FLOWTCAM_NUM (32)
-#define DPP_PPU_CLS_0_BIT_MAP  (1<<0) /*bit0 = 1 代表cluster0 启动*/
-#define DPP_PPU_CLS_1_BIT_MAP  (1<<1) /*bit1 = 1 代表cluster1 启动*/
-#define DPP_PPU_CLS_2_BIT_MAP  (1<<2) /*bit2 = 1 代表cluster2 启动*/
-#define DPP_PPU_CLS_3_BIT_MAP  (1<<3) /*bit3 = 1 代表cluster3 启动*/
-#define DPP_PPU_CLS_4_BIT_MAP  (1<<4) /*bit4 = 1 代表cluster4 启动*/
-#define DPP_PPU_CLS_5_BIT_MAP  (1<<5) /*bit5 = 1 代表cluster5 启动*/
-
-#define DPP_PPU_CLS_ALL_START  (0x3F) /*打开所有cluster*/
-
-/*该结构在ppu初始化的时候生成 全局不可修改*/
-typedef struct dpp_ppu_cls_bitmap_t
-{
-    ZXIC_UINT32 cls_use[DPP_PPU_CLUSTER_NUM]; /*记录配置生效的 cluster 由bitmap解析获得*/
-    ZXIC_UINT32 instr_mem[PPU_INSTR_MEM_NUM]; /*记录配置生效的 指令空间索引号, 每两个cluster 共享一个指令空间*/
-} DPP_PPU_CLS_BITMAP_T;
-
-typedef struct dpp_ppu_ppu_cop_thash_rsk_t
-{
-    ZXIC_UINT32 rsk_319_288;
-    ZXIC_UINT32 rsk_287_256;
-    ZXIC_UINT32 rsk_255_224;
-    ZXIC_UINT32 rsk_223_192;
-    ZXIC_UINT32 rsk_191_160;
-    ZXIC_UINT32 rsk_159_128;
-    ZXIC_UINT32 rsk_127_096;
-    ZXIC_UINT32 rsk_095_064;
-    ZXIC_UINT32 rsk_063_032;
-    ZXIC_UINT32 rsk_031_000;
-
-} DPP_PPU_PPU_COP_THASH_RSK_T;
-
-ZXIC_UINT32 dpp_ppu_cls_use_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 cluster_id, ZXIC_UINT32 flag);
-ZXIC_UINT32 dpp_ppu_cls_use_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 cluster_id);
-ZXIC_UINT32 dpp_ppu_instr_mem_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 mem_id, ZXIC_UINT32 flag);
-ZXIC_UINT32 dpp_ppu_parse_cls_bitmap(ZXIC_UINT32 dev_id, ZXIC_UINT32 bitmap);
-
-DPP_STATUS dpp_ppu_ppu_cop_thash_rsk_set(DPP_DEV_T *dev, DPP_PPU_PPU_COP_THASH_RSK_T *p_para);
-DPP_STATUS dpp_ppu_ppu_cop_thash_rsk_get(DPP_DEV_T *dev, DPP_PPU_PPU_COP_THASH_RSK_T *p_ppu_cop_thash_rsk);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_ppu.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2014/03/18
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#ifndef _DPP_PPU_H_
+#define _DPP_PPU_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dpp_module.h"
+#include "dpp_ppu_api.h"
+#include "dpp_ppu_reg.h"
+#include "zxic_comm_thread.h"
+
+#define PPU_CLS_ME_NUM (8)
+#define PPU_INSTR_MEM_NUM \
+	(3) /*ppu中的微码指令空间数量 2个cluster 共用一个指令空间*/
+#define PPU_INSTR_REG_NUM (4) /*ppu中指令空间中的数据寄存器数目*/
+#define PPU_INSTR_NUM_MAX (32 * 1024) /* xjw mod at 18.6.2 from 16k to 32k */
+#define PPU_SDT_IDX_MIN (0)
+#define PPU_SDT_IDX_MAX (255)
+#define PPU_DUP_IDX_MIN (0)
+#define PPU_DUP_IDX_MAX (63)
+#define PPU_INSTR_COL_MAX (4)
+
+/**  ME指令调试中断*/
+#define PPU_ME0_INT_BT_START (0)
+#define PPU_ME0_INT_BT_LEN (1)
+#define PPU_ME1_INT_BT_START (1)
+#define PPU_ME1_INT_BT_LEN (1)
+#define PPU_ME2_INT_BT_START (2)
+#define PPU_ME2_INT_BT_LEN (1)
+#define PPU_ME3_INT_BT_START (3)
+#define PPU_ME3_INT_BT_LEN (1)
+#define PPU_ME4_INT_BT_START (4)
+#define PPU_ME4_INT_BT_LEN (1)
+#define PPU_ME5_INT_BT_START (5)
+#define PPU_ME5_INT_BT_LEN (1)
+#define PPU_ME6_INT_BT_START (6)
+#define PPU_ME6_INT_BT_LEN (1)
+#define PPU_ME7_INT_BT_START (7)
+#define PPU_ME7_INT_BT_LEN (1)
+
+#define DPP_FPGA_MAX_FLOWTCAM_NUM (32)
+#define DPP_PPU_CLS_0_BIT_MAP (1 << 0) /*bit0 = 1 代表cluster0 启动*/
+#define DPP_PPU_CLS_1_BIT_MAP (1 << 1) /*bit1 = 1 代表cluster1 启动*/
+#define DPP_PPU_CLS_2_BIT_MAP (1 << 2) /*bit2 = 1 代表cluster2 启动*/
+#define DPP_PPU_CLS_3_BIT_MAP (1 << 3) /*bit3 = 1 代表cluster3 启动*/
+#define DPP_PPU_CLS_4_BIT_MAP (1 << 4) /*bit4 = 1 代表cluster4 启动*/
+#define DPP_PPU_CLS_5_BIT_MAP (1 << 5) /*bit5 = 1 代表cluster5 启动*/
+
+#define DPP_PPU_CLS_ALL_START (0x3F) /*打开所有cluster*/
+
+/*该结构在ppu初始化的时候生成 全局不可修改*/
+typedef struct dpp_ppu_cls_bitmap_t {
+	ZXIC_UINT32 cls_use
+			[DPP_PPU_CLUSTER_NUM]; /*记录配置生效的 cluster 由bitmap解析获得*/
+	ZXIC_UINT32 instr_mem
+			[PPU_INSTR_MEM_NUM]; /*记录配置生效的 指令空间索引号, 每两个cluster 共享一个指令空间*/
+} DPP_PPU_CLS_BITMAP_T;
+
+typedef struct dpp_ppu_ppu_cop_thash_rsk_t {
+	ZXIC_UINT32 rsk_319_288;
+	ZXIC_UINT32 rsk_287_256;
+	ZXIC_UINT32 rsk_255_224;
+	ZXIC_UINT32 rsk_223_192;
+	ZXIC_UINT32 rsk_191_160;
+	ZXIC_UINT32 rsk_159_128;
+	ZXIC_UINT32 rsk_127_096;
+	ZXIC_UINT32 rsk_095_064;
+	ZXIC_UINT32 rsk_063_032;
+	ZXIC_UINT32 rsk_031_000;
+
+} DPP_PPU_PPU_COP_THASH_RSK_T;
+
+ZXIC_UINT32 dpp_ppu_cls_use_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 cluster_id,
+								ZXIC_UINT32 flag);
+ZXIC_UINT32 dpp_ppu_cls_use_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 cluster_id);
+ZXIC_UINT32 dpp_ppu_instr_mem_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 mem_id,
+								  ZXIC_UINT32 flag);
+ZXIC_UINT32 dpp_ppu_parse_cls_bitmap(ZXIC_UINT32 dev_id, ZXIC_UINT32 bitmap);
+
+DPP_STATUS dpp_ppu_ppu_cop_thash_rsk_set(DPP_DEV_T *dev,
+										 DPP_PPU_PPU_COP_THASH_RSK_T *p_para);
+DPP_STATUS
+dpp_ppu_ppu_cop_thash_rsk_get(DPP_DEV_T *dev,
+							  DPP_PPU_PPU_COP_THASH_RSK_T *p_ppu_cop_thash_rsk);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_apt_se.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_apt_se.h
old mode 100755
new mode 100644
index cf5947033c744557e59edd981a1715dfeea3d521..04dadb77061ec9e6b70b0be432e99ed19bc57549
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_apt_se.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_apt_se.h
@@ -1,111 +1,110 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_apt_se.h
-* 文件标识 : 
-* 内容摘要 : SE适配业务接口数据结构和函数声明
-* 其它说明 : 
-* 当前版本 : 
-* 作    者 : chenqin00181032
-* 完成日期 : 2022/02/22
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* 版 本 号:  
-* 修 改 人:  
-* 修改内容:  
-***************************************************************/
-
-#ifndef _DPP_APT_SE_H_
-#define _DPP_APT_SE_H_
-
-#include "dpp_apt_se_api.h"
-
-#define SDT_OPER_ADD (ZXIC_UINT32)(0)
-#define SDT_OPER_DEL (ZXIC_UINT32)(1)
-
-#define SDT_DDR_RW_128BIT  (ZXIC_UINT32)(0)
-#define SDT_DDR_RW_256BIT  (ZXIC_UINT32)(1)
-#define SDT_DDR_RW_512BIT  (ZXIC_UINT32)(2)
-
-#define DDR_128BIT_BYTE    (ZXIC_UINT32)(16)
-
-#define ERAM_ENTRY_SOFT_MAX (ZXIC_UINT32)(16)   /*eram最大位宽128bit*/
-#define HASH_ENTRY_SOFT_MAX (ZXIC_UINT32)(64)   /*hash最大位宽512bit*/
-#define ACL_ENTRY_SOFT_MAX  (ZXIC_UINT32)(160)  /*acl最大位宽640bit key+640bit mask*/
-
-typedef struct se_apt_eram_func_t
-{
-    ZXIC_UINT32 opr_mode;     /**cpu读写位宽模式DPP_ERAM128_OPR_MODE_E 0:128b 1:64b 2:1b 3:32b <@*/
-    ZXIC_UINT32 rd_mode;      /*读清模式DPP_ERAM128_RD_CLR_MODE_E，0:正常读 1:读清模式*/
-    DPP_APT_ERAM_SET_FUNC  eram_set_func;
-    DPP_APT_ERAM_GET_FUNC  eram_get_func;
-}SE_APT_ERAM_FUNC_T;
-
-typedef struct se_apt_ddr_func_t
-{
-    ZXIC_UINT32 ddr_tbl_depth;     /*ddr表项深度，单位与ddr读写模式一致*/
-    DPP_APT_DDR_SET_FUNC  ddr_set_func;
-    DPP_APT_DDR_GET_FUNC  ddr_get_func;
-}SE_APT_DDR_FUNC_T;
-
-typedef struct se_apt_acl_func_t
-{
-    DPP_APT_ACL_ENTRY_SET_FUNC  acl_set_func;
-    DPP_APT_ACL_ENTRY_GET_FUNC  acl_get_func;
-}SE_APT_ACL_FUNC_T;
-
-typedef struct se_apt_hash_func_t
-{
-    DPP_APT_HASH_ENTRY_SET_FUNC  hash_set_func;
-    DPP_APT_HASH_ENTRY_GET_FUNC  hash_get_func;
-}SE_APT_HASH_FUNC_T;
-
-typedef struct se_apt_lpm_func_t
-{
-    DPP_APT_LPM_ENTRY_SET_FUNC  lpm_set_func;
-    DPP_APT_LPM_ENTRY_GET_FUNC  lpm_get_func;
-}SE_APT_LPM_FUNC_T;
-typedef struct se_apt_callback_t
-{
-    ZXIC_UINT32 sdtNo;          /** <@brief sdt no 0~255 */
-    ZXIC_UINT32 table_type;     /** <@brief 查找表项类型 */
-
-    union
-    {
-        SE_APT_ERAM_FUNC_T eramFunc;
-        SE_APT_DDR_FUNC_T  ddrFunc;
-        SE_APT_ACL_FUNC_T  aclFunc;
-        SE_APT_HASH_FUNC_T hashFunc;
-        SE_APT_LPM_FUNC_T  lpmFunc;
-    }se_func_info;
-}SE_APT_CALLBACK_T;
-
-typedef struct se_apt_eram_soft_t
-{
-    ZXIC_UINT32 index;
-    ZXIC_UINT32  buff[ERAM_ENTRY_SOFT_MAX/4];
-}SE_APT_ERAM_SOFT_T;
-
-typedef struct se_apt_eram_hash_t
-{
-    ZXIC_UINT32 index;
-    ZXIC_UINT8  aucData[HASH_ENTRY_SOFT_MAX];
-}SE_APT_HASH_SOFT_T;
-
-typedef struct se_apt_eram_acl_t
-{
-    ZXIC_UINT32 index;
-    ZXIC_UINT8  aucData[ACL_ENTRY_SOFT_MAX];
-}SE_APT_ACL_SOFT_T;
-
-ZXIC_SINT32 dpp_apt_table_key_cmp(void *p_new_key, void *p_old_key, ZXIC_UINT32 key_len);
-SE_APT_CALLBACK_T *dpp_apt_get_func(ZXIC_UINT32 dev_id,ZXIC_UINT32 sdt_no);
-DPP_STATUS dpp_apt_set_callback(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, ZXIC_UINT32 table_type,ZXIC_VOID *pData);
-DPP_STATUS dpp_apt_sw_list_insert(ZXIC_RB_CFG *rb_cfg,void *pData,ZXIC_UINT32 len);
-DPP_STATUS dpp_apt_sw_list_search(ZXIC_RB_CFG *rb_cfg,void *pData,ZXIC_UINT32 len);
-DPP_STATUS dpp_apt_sw_list_delete(ZXIC_RB_CFG *rb_cfg,void *pData,ZXIC_UINT32 len);
-DPP_STATUS dpp_apt_get_zblock_index(ZXIC_UINT32 zblock_bitmap,ZXIC_UINT32 *zblk_idx);
-DPP_STATUS dpp_apt_dtb_res_init(DPP_DEV_T *dev);
-DPP_STATUS dpp_apt_se_callback_init(ZXIC_UINT32 dev_id);
-#endif
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_apt_se.h
+* 文件标识 :
+* 内容摘要 : SE适配业务接口数据结构和函数声明
+* 其它说明 :
+* 当前版本 :
+* 作    者 : chenqin00181032
+* 完成日期 : 2022/02/22
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#ifndef _DPP_APT_SE_H_
+#define _DPP_APT_SE_H_
+
+#include "dpp_apt_se_api.h"
+
+#define SDT_OPER_ADD ((ZXIC_UINT32)(0))
+#define SDT_OPER_DEL ((ZXIC_UINT32)(1))
+
+#define SDT_DDR_RW_128BIT ((ZXIC_UINT32)(0))
+#define SDT_DDR_RW_256BIT ((ZXIC_UINT32)(1))
+#define SDT_DDR_RW_512BIT ((ZXIC_UINT32)(2))
+
+#define DDR_128BIT_BYTE ((ZXIC_UINT32)(16))
+
+#define ERAM_ENTRY_SOFT_MAX ((ZXIC_UINT32)(16)) /*eram最大位宽128bit*/
+#define HASH_ENTRY_SOFT_MAX ((ZXIC_UINT32)(64)) /*hash最大位宽512bit*/
+#define ACL_ENTRY_SOFT_MAX \
+	((ZXIC_UINT32)(160)) /*acl最大位宽640bit key+640bit mask*/
+
+typedef struct se_apt_eram_func_t {
+	ZXIC_UINT32
+	opr_mode; /**cpu读写位宽模式DPP_ERAM128_OPR_MODE_E 0:128b 1:64b 2:1b 3:32b <@*/
+	ZXIC_UINT32
+	rd_mode; /*读清模式DPP_ERAM128_RD_CLR_MODE_E，0:正常读 1:读清模式*/
+	DPP_APT_ERAM_SET_FUNC eram_set_func;
+	DPP_APT_ERAM_GET_FUNC eram_get_func;
+} SE_APT_ERAM_FUNC_T;
+
+typedef struct se_apt_ddr_func_t {
+	ZXIC_UINT32 ddr_tbl_depth; /*ddr表项深度，单位与ddr读写模式一致*/
+	DPP_APT_DDR_SET_FUNC ddr_set_func;
+	DPP_APT_DDR_GET_FUNC ddr_get_func;
+} SE_APT_DDR_FUNC_T;
+
+typedef struct se_apt_acl_func_t {
+	DPP_APT_ACL_ENTRY_SET_FUNC acl_set_func;
+	DPP_APT_ACL_ENTRY_GET_FUNC acl_get_func;
+} SE_APT_ACL_FUNC_T;
+
+typedef struct se_apt_hash_func_t {
+	DPP_APT_HASH_ENTRY_SET_FUNC hash_set_func;
+	DPP_APT_HASH_ENTRY_GET_FUNC hash_get_func;
+} SE_APT_HASH_FUNC_T;
+
+typedef struct se_apt_lpm_func_t {
+	DPP_APT_LPM_ENTRY_SET_FUNC lpm_set_func;
+	DPP_APT_LPM_ENTRY_GET_FUNC lpm_get_func;
+} SE_APT_LPM_FUNC_T;
+typedef struct se_apt_callback_t {
+	ZXIC_UINT32 sdtNo; /** <@brief sdt no 0~255 */
+	ZXIC_UINT32 table_type; /** <@brief 查找表项类型 */
+
+	union {
+		SE_APT_ERAM_FUNC_T eramFunc;
+		SE_APT_DDR_FUNC_T ddrFunc;
+		SE_APT_ACL_FUNC_T aclFunc;
+		SE_APT_HASH_FUNC_T hashFunc;
+		SE_APT_LPM_FUNC_T lpmFunc;
+	} se_func_info;
+} SE_APT_CALLBACK_T;
+
+typedef struct se_apt_eram_soft_t {
+	ZXIC_UINT32 index;
+	ZXIC_UINT32 buff[ERAM_ENTRY_SOFT_MAX / 4];
+} SE_APT_ERAM_SOFT_T;
+
+typedef struct se_apt_eram_hash_t {
+	ZXIC_UINT32 index;
+	ZXIC_UINT8 aucData[HASH_ENTRY_SOFT_MAX];
+} SE_APT_HASH_SOFT_T;
+
+typedef struct se_apt_eram_acl_t {
+	ZXIC_UINT32 index;
+	ZXIC_UINT8 aucData[ACL_ENTRY_SOFT_MAX];
+} SE_APT_ACL_SOFT_T;
+
+ZXIC_SINT32 dpp_apt_table_key_cmp(void *p_new_key, void *p_old_key,
+								  ZXIC_UINT32 key_len);
+SE_APT_CALLBACK_T *dpp_apt_get_func(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no);
+DPP_STATUS dpp_apt_set_callback(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no,
+								ZXIC_UINT32 table_type, ZXIC_VOID *pData);
+DPP_STATUS dpp_apt_sw_list_insert(ZXIC_RB_CFG *rb_cfg, void *pData,
+								  ZXIC_UINT32 len);
+DPP_STATUS dpp_apt_sw_list_search(ZXIC_RB_CFG *rb_cfg, void *pData,
+								  ZXIC_UINT32 len);
+DPP_STATUS dpp_apt_sw_list_delete(ZXIC_RB_CFG *rb_cfg, void *pData,
+								  ZXIC_UINT32 len);
+DPP_STATUS dpp_apt_get_zblock_index(ZXIC_UINT32 zblock_bitmap,
+									ZXIC_UINT32 *zblk_idx);
+DPP_STATUS dpp_apt_dtb_res_init(DPP_DEV_T *dev);
+DPP_STATUS dpp_apt_se_callback_init(ZXIC_UINT32 dev_id);
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_etcam.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_etcam.h
old mode 100755
new mode 100644
index 588b8156083ad5e862c04fd133301f705ccf2a22..d83d0ae13698b71796b5b17f7f3f8b6052a54ed0
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_etcam.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_etcam.h
@@ -1,157 +1,156 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_etcam.h
-* 文件标识 : 
-* 内容摘要 : 
-* 其它说明 : 
-* 当前版本 : 
-* 作    者 : 王春雷
-* 完成日期 : 2014/04/03
-* DEPARTMENT: ASIC_FPGA_R&D_Dept 
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* 版 本 号:  
-* 修 改 人:  
-* 修改内容:  
-***************************************************************/
-
-#ifndef _DPP_ETCAM_H_
-#define _DPP_ETCAM_H_
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-#define DPP_ETCAM_BLOCK_NUM           (8)   /* eTcam中Block的数目 16:dpp+的etcam block 数目 */
-#define DPP_ETCAM_TBLID_NUM           (8)    /* eTcam支持的业务表号 */
-#define DPP_ETCAM_RAM_NUM             (8)    /* Block内部RAM的个数 */
-#define DPP_ETCAM_RAM_WIDTH           (80U)   /* Block内部单个RAM的宽度，比特为单位 */
-
-#ifdef DPP_FPGA_TEST_BAORD_SA500FT
-#define DPP_ETCAM_RAM_DEPTH           (16U)   /* Block内部单个RAM的深度 */
-#else
-#define DPP_ETCAM_RAM_DEPTH           (512U)  /* Block内部单个RAM的深度 */
-#endif
-
-#define DPP_ETCAM_WR_MASK_MAX         (((ZXIC_UINT32)1<<DPP_ETCAM_RAM_NUM)-1)/*255*/
-#define DPP_ETCAM_WIDTH_MIN           (DPP_ETCAM_RAM_WIDTH)                     /* eTcam最小数据位宽，比特为单位 */
-#define DPP_ETCAM_WIDTH_MAX           (DPP_ETCAM_RAM_NUM * DPP_ETCAM_RAM_WIDTH) /* eTcam最大数据位宽，比特为单位 */
-
-#define DPP_ETCAM_DEFAULT_MIN         (0)
-#define DPP_ETCAM_ONE_BIT_MAX         (1)
-
-#define DPP_ETCAM_PORT_NUM            (1)
-
-typedef enum dpp_etcam_data_type_e
-{
-    DPP_ETCAM_DTYPE_MASK = 0,
-    DPP_ETCAM_DTYPE_DATA = 1,
-}DPP_ETCAM_DATA_TYPE_E;
-
-/** etcam 条目vld信息  */
-typedef struct dpp_etcam_entry_vld_t
-{
-    ZXIC_UINT8 vld;           /** <@brief 标示每个条目的使用状态，每bit为指示当前条目是否被占用 */
-    ZXIC_UINT8 rsv[3];        /** <@brief 数据对齐，勿需关心 */
-}DPP_ETCAM_ENTRY_VLD_T;
-
-/* error code */
-#define DPP_STAT_ETCAM_RC_BASE         (0x6000)
-#define DPP_ETCAM_RC_INVALID_PARA      (DPP_STAT_ETCAM_RC_BASE | 0x0)
-
-/* macro function */
-#define DPP_ETCAM_ENTRY_SIZE_GET(entry_mode) \
-    (((ZXIC_UINT32)DPP_ETCAM_RAM_WIDTH << (3 - entry_mode)) / 8)
-
-/* api */
-DPP_STATUS dpp_etcam_dm_to_xy(DPP_ETCAM_ENTRY_T *p_dm, DPP_ETCAM_ENTRY_T *p_xy, ZXIC_UINT32 len);
-
-DPP_STATUS dpp_etcam_xy_to_dm(DPP_ETCAM_ENTRY_T *p_dm, DPP_ETCAM_ENTRY_T *p_xy, ZXIC_UINT32 len);
-
-DPP_STATUS dpp_etcam_block_tbl_id_set(DPP_DEV_T *dev, ZXIC_UINT32 block_idx, ZXIC_UINT32 tbl_id);
-
-DPP_STATUS dpp_etcam_block_tbl_id_get(DPP_DEV_T *dev, ZXIC_UINT32 block_idx, ZXIC_UINT32 *p_tbl_id);
-
-DPP_STATUS dpp_etcam_block_baddr_set(DPP_DEV_T *dev, ZXIC_UINT32 block_idx, ZXIC_UINT32 base_addr);
-
-DPP_STATUS dpp_etcam_block_baddr_get(DPP_DEV_T *dev, ZXIC_UINT32 block_idx, ZXIC_UINT32 *p_base_addr);
-
-DPP_STATUS dpp_etcam_cpu_afull_get(DPP_DEV_T *dev, ZXIC_UINT32 block_idx, ZXIC_UINT32 *p_cpu_afull);
-
-DPP_STATUS dpp_etcam_ind_cmd_set(DPP_DEV_T *dev,
-                                 ZXIC_UINT32 addr,
-                                 ZXIC_UINT32 block_idx,
-                                 ZXIC_UINT32 data_or_mask,
-                                 ZXIC_UINT32 wr_mask,
-                                 ZXIC_UINT32 opr_type,
-                                 ZXIC_UINT32 tacm_reg_flag,
-                                 ZXIC_UINT32 row_mask_flag,
-                                 ZXIC_UINT32 vben,
-                                 ZXIC_UINT32 vbit);
-
-/***********************************************************/
-/** 添加eTcam表条目
-* @param   dev_id     设备号
-* @param   addr       每个block中的ram地址，位宽为8*80bit
-* @param   block_idx  block编号，范围0~15
-* @param   wr_mask    写表掩码，共8bit，每bit控制ram中对应位置的80bit数据是否有效
-* @param   p_entry    条目数据，data和mask
-*
-* @return
-* @remark  无
-* @see
-* @author  wcl      @date  2014/04/03
-************************************************************/
-DPP_STATUS dpp_etcam_entry_add(DPP_DEV_T *dev,
-                               ZXIC_UINT32 addr,
-                               ZXIC_UINT32 block_idx,
-                               ZXIC_UINT32 wr_mask,
-                               ZXIC_UINT32 opr_type,
-                               DPP_ETCAM_ENTRY_T *p_entry);
-
-/***********************************************************/
-/** 删除eTcam表项条目
-* @param   dev_id     设备号
-* @param   addr       每个block中的ram地址，位宽为8*80bit
-* @param   block_idx  block的编号，范围0~15
-* @param   wr_mask    写表掩码，共8bit，每bit控制ram中对应位置的80bit数据是否有效
-*
-* @return
-* @remark  无
-* @see
-* @author  wcl      @date  2014/04/03
-************************************************************/
-DPP_STATUS dpp_etcam_entry_del(DPP_DEV_T *dev,
-                               ZXIC_UINT32 addr,
-                               ZXIC_UINT32 block_idx,
-                               ZXIC_UINT32 wr_mask);
-
-ZXIC_UINT32 dpp_etcam_entry_cmp(DPP_ETCAM_ENTRY_T *p_entry_dm, DPP_ETCAM_ENTRY_T *p_entry_xy);
-
-ZXIC_UINT32 dpp_etcam_ind_data_reg_opr_mask_get(ZXIC_UINT32 mask);
-
-#if ZXIC_REAL("调试计数")
-
-typedef struct dpp_etcam_port_cnt
-{
-    ZXIC_UINT32 as_etcam_req_cnt;
-    ZXIC_UINT32 etcam_as_index_cnt;
-    ZXIC_UINT32 etcam_not_hit_cnt;
-}DPP_ETCAM_PORT_CNT_T;
-
-typedef struct dpp_etcam_dbg_cnt
-{
-    DPP_ETCAM_PORT_CNT_T dpp_etcam_port_cnt[DPP_ETCAM_PORT_NUM];
-    ZXIC_UINT32 table_id_not_match_cnt;
-    ZXIC_UINT32 table_id_clash01_cnt;
-}DPP_ETCAM_DBG_CNT_T;
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_etcam.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2014/04/03
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#ifndef _DPP_ETCAM_H_
+#define _DPP_ETCAM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DPP_ETCAM_BLOCK_NUM \
+	(8) /* eTcam中Block的数目 16:dpp+的etcam block 数目 */
+#define DPP_ETCAM_TBLID_NUM (8) /* eTcam支持的业务表号 */
+#define DPP_ETCAM_RAM_NUM (8) /* Block内部RAM的个数 */
+#define DPP_ETCAM_RAM_WIDTH (80U) /* Block内部单个RAM的宽度，比特为单位 */
+
+#define DPP_ETCAM_RAM_DEPTH (512U) /* Block内部单个RAM的深度 */
+
+#define DPP_ETCAM_WR_MASK_MAX \
+	(((ZXIC_UINT32)1 << DPP_ETCAM_RAM_NUM) - 1) /*255*/
+#define DPP_ETCAM_WIDTH_MIN \
+	(DPP_ETCAM_RAM_WIDTH) /* eTcam最小数据位宽，比特为单位 */
+#define DPP_ETCAM_WIDTH_MAX \
+	(DPP_ETCAM_RAM_NUM *    \
+	 DPP_ETCAM_RAM_WIDTH) /* eTcam最大数据位宽，比特为单位 */
+
+#define DPP_ETCAM_DEFAULT_MIN (0)
+#define DPP_ETCAM_ONE_BIT_MAX (1)
+
+#define DPP_ETCAM_PORT_NUM (1)
+
+typedef enum dpp_etcam_data_type_e {
+	DPP_ETCAM_DTYPE_MASK = 0,
+	DPP_ETCAM_DTYPE_DATA = 1,
+} DPP_ETCAM_DATA_TYPE_E;
+
+/** etcam 条目vld信息  */
+typedef struct dpp_etcam_entry_vld_t {
+	ZXIC_UINT8
+	vld; /** <@brief 标示每个条目的使用状态，每bit为指示当前条目是否被占用 */
+	ZXIC_UINT8 rsv[3]; /** <@brief 数据对齐，勿需关心 */
+} DPP_ETCAM_ENTRY_VLD_T;
+
+/* error code */
+#define DPP_STAT_ETCAM_RC_BASE (0x6000)
+#define DPP_ETCAM_RC_INVALID_PARA (DPP_STAT_ETCAM_RC_BASE | 0x0)
+
+/* macro function */
+#define DPP_ETCAM_ENTRY_SIZE_GET(entry_mode) \
+	(((ZXIC_UINT32)DPP_ETCAM_RAM_WIDTH << (3 - entry_mode)) / 8)
+
+/* api */
+DPP_STATUS dpp_etcam_dm_to_xy(DPP_ETCAM_ENTRY_T *p_dm, DPP_ETCAM_ENTRY_T *p_xy,
+							  ZXIC_UINT32 len);
+
+DPP_STATUS dpp_etcam_xy_to_dm(DPP_ETCAM_ENTRY_T *p_dm, DPP_ETCAM_ENTRY_T *p_xy,
+							  ZXIC_UINT32 len);
+
+DPP_STATUS dpp_etcam_block_tbl_id_set(DPP_DEV_T *dev, ZXIC_UINT32 block_idx,
+									  ZXIC_UINT32 tbl_id);
+
+DPP_STATUS dpp_etcam_block_tbl_id_get(DPP_DEV_T *dev, ZXIC_UINT32 block_idx,
+									  ZXIC_UINT32 *p_tbl_id);
+
+DPP_STATUS dpp_etcam_block_baddr_set(DPP_DEV_T *dev, ZXIC_UINT32 block_idx,
+									 ZXIC_UINT32 base_addr);
+
+DPP_STATUS dpp_etcam_block_baddr_get(DPP_DEV_T *dev, ZXIC_UINT32 block_idx,
+									 ZXIC_UINT32 *p_base_addr);
+
+DPP_STATUS dpp_etcam_cpu_afull_get(DPP_DEV_T *dev, ZXIC_UINT32 block_idx,
+								   ZXIC_UINT32 *p_cpu_afull);
+
+DPP_STATUS dpp_etcam_ind_cmd_set(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+								 ZXIC_UINT32 block_idx,
+								 ZXIC_UINT32 data_or_mask, ZXIC_UINT32 wr_mask,
+								 ZXIC_UINT32 opr_type,
+								 ZXIC_UINT32 tacm_reg_flag,
+								 ZXIC_UINT32 row_mask_flag, ZXIC_UINT32 vben,
+								 ZXIC_UINT32 vbit);
+
+/***********************************************************/
+/** 添加eTcam表条目
+     * @param   dev_id     设备号
+     * @param   addr       每个block中的ram地址，位宽为8*80bit
+     * @param   block_idx  block编号，范围0~15
+     * @param   wr_mask    写表掩码，共8bit，每bit控制ram中对应位置的80bit数据是否有效
+     * @param   p_entry    条目数据，data和mask
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  wcl      @date  2014/04/03
+     ************************************************************/
+DPP_STATUS dpp_etcam_entry_add(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+							   ZXIC_UINT32 block_idx, ZXIC_UINT32 wr_mask,
+							   ZXIC_UINT32 opr_type,
+							   DPP_ETCAM_ENTRY_T *p_entry);
+
+/***********************************************************/
+/** 删除eTcam表项条目
+     * @param   dev_id     设备号
+     * @param   addr       每个block中的ram地址，位宽为8*80bit
+     * @param   block_idx  block的编号，范围0~15
+     * @param   wr_mask    写表掩码，共8bit，每bit控制ram中对应位置的80bit数据是否有效
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  wcl      @date  2014/04/03
+     ************************************************************/
+DPP_STATUS dpp_etcam_entry_del(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+							   ZXIC_UINT32 block_idx, ZXIC_UINT32 wr_mask);
+
+ZXIC_UINT32 dpp_etcam_entry_cmp(DPP_ETCAM_ENTRY_T *p_entry_dm,
+								DPP_ETCAM_ENTRY_T *p_entry_xy);
+
+ZXIC_UINT32 dpp_etcam_ind_data_reg_opr_mask_get(ZXIC_UINT32 mask);
+
+#if ZXIC_REAL("调试计数")
+
+typedef struct dpp_etcam_port_cnt {
+	ZXIC_UINT32 as_etcam_req_cnt;
+	ZXIC_UINT32 etcam_as_index_cnt;
+	ZXIC_UINT32 etcam_not_hit_cnt;
+} DPP_ETCAM_PORT_CNT_T;
+
+typedef struct dpp_etcam_dbg_cnt {
+	DPP_ETCAM_PORT_CNT_T dpp_etcam_port_cnt[DPP_ETCAM_PORT_NUM];
+	ZXIC_UINT32 table_id_not_match_cnt;
+	ZXIC_UINT32 table_id_clash01_cnt;
+} DPP_ETCAM_DBG_CNT_T;
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_se.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_se.h
old mode 100755
new mode 100644
index 133b1e7651ee0a74cc1bcb66de1ed90d829c34b8..e39e2f1c47bbcdad0fc9ffede05b5e475ff3c364
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_se.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_se.h
@@ -1,821 +1,771 @@
-/**************************************************************
-* 版权所�? (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_se.h
-* 文件标识 : 
-* 内容摘要 : 
-* 其它说明 : 
-* 当前版本 : 
-* �?    �? : 王春�?
-* 完成日期 : 2014/03/11
-* DEPARTMENT: ASIC_FPGA_R&D_Dept 
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* �? �? �?:  
-* �? �? �?:  
-* 修改内容:  
-***************************************************************/
-
-#ifndef _DPP_SE_H_
-#define _DPP_SE_H_
-
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-
-#include "dpp_se_api.h"
-
-#define DPP_HASH_ID_MIN         (0)
-#define DPP_HASH_ID_MAX         (3)
-#define DPP_HASH_ID_NUM         (4)
-
-#define HASH_BULK_ID_MIN        (0)
-#define HASH_BULK_ID_MAX        (7)
-#define HASH_BULK_NUM           (8)    /* 每个Hash引擎存储资源划分的块�? */
-
-#define CRC_POLY_SEL_MIN        (0)
-#define CRC_POLY_SEL_MAX        (3)
-
-#define DPP_LPM_ID_MIN          (4)
-#define DPP_LPM_ID_MAX          (5)
-#define DPP_LPM_ID_NUM          (2)
-
-#define DPP_ETCAM_ID_MIN        (0)
-#define DPP_ETCAM_ID_MAX        (0)
-#define DPP_ETCAM_ID_NUM        (1)
-
-#define DPP_AGE_TBL_ID_MIN      (0)
-#define DPP_AGE_TBL_ID_MAX      (15)
-
-#define DPP_SMMU1_DDR_GRP_NUM               (1)
-
-//#define DPP_SMMU1_DIR_TBL_BANK_MAX          (15)
-#define DPP_SMMU1_DIR_TBL_INDEX_MAX         (255)
-//#define DPP_SMMU1_UN_DIR_TBL_BANK_MAX       (29)
-
-#define DPP_SMMU1_HASH_TBL_INDEX_BASE       (1)
-#define DPP_SMMU1_HASH_TBL_INDEX_MAX        (31)
-#define DPP_SMMU1_LPM_TBL_INDEX_BASE        (33)
-#define DPP_SMMU1_LPM_TBL_INDEX_MAX         (3)
-#define DPP_SMMU1_OAM_TBL_INDEX_BASE        (37)
-#define DPP_SMMU1_FTM_TBL_INDEX_BASE        (38)
-#define DPP_SMMU1_ETM_TBL_INDEX_BASE        (39)
-#define DPP_SMMU1_DIR_TBL_INDEX_BASE        (40)
-
-
-#define DPP_SMMU1_SINGLE_BNAK_MAX_ADDR      ((1<<25) - 1)
-#define DPP_SMMU1_SINGLE_BANK_MAX_BADDR     (DPP_SMMU1_SINGLE_BNAK_MAX_ADDR >> 12)
-#define DPP_SMMU1_TOTAL_BANK_NUM            (8)
-#define DPP_SMMU1_TOTAL_MAX_ADDR            (0xffffffff)
-#define DPP_SMMU1_TOTAL_MAX_BADDR           (DPP_SMMU1_TOTAL_MAX_ADDR >> 12)
-#define DPP_SMMU1_BADDR_MASK                (0x7ffff800)
-#define DPP_SMMU1_DDR_GROUP_NUM             (1)
-#define DPP_SMMU1_BANK_COPY_MAX_NUM         (16)
-#define DPP_SMMU1_READ_REG_MAX_NUM          (16)
-#define DPP_DIR_TBL_BUF_MAX_NUM             (DPP_SMMU1_READ_REG_MAX_NUM)
-
-/*hash ext crc cfg*/
-#define HASH_ECC_EN_BT_START          (2)
-#define HASH_ECC_EN_BT_WIDTH          (1)
-#define HASH_BANK_COPY_BT_START       (3)
-#define HASH_BANK_COPY_BT_WIDTH       (3)
-#define HASH_BASE_ADDR_BT_START       (6)
-#define HASH_BASE_ADDR_BT_WIDTH       (15)
-/*hash learn  tbl cfg*/
-#define LEARN_HASH_TBL_BT_START       (0)
-#define LEARN_HASH_TBL_BT_WIDTH       (19)
-
-#define DPP_SMMU0_MCAST_TBL_MAX_GROUP       (0xffff)
-
-#define DPP_SMMU0_CAR0_MONO_POS             (0)
-#define DPP_SMMU0_CAR0_MONO_LEN             (1)
-#define DPP_SMMU0_CAR0_EN_POS               (1)
-#define DPP_SMMU0_CAR0_EN_LEN               (1)
-#define DPP_SMMU0_CAR1_MONO_POS             (2)
-#define DPP_SMMU0_CAR1_MONO_LEN             (1)
-#define DPP_SMMU0_CAR1_EN_POS               (3)
-#define DPP_SMMU0_CAR1_EN_LEN               (1)
-
-#define DPP_SMMU0_LPM_AS_TBL_ID_MAX         (7)
-#define DPP_SMMU0_LPM_AS_TBL_ID_NUM         (8)
-
-#define DPP_SMMU0_MCAST_DATA_VLD_POS        (16)
-#define DPP_SMMU0_MCAST_DATA_VLD_LEN        (1)
-#define DPP_SMMU0_MCAST_CNT_POS             (0)
-#define DPP_SMMU0_MCAST_CNT_LEN             (16)
-
-#define DPP_SMMU0_INDIER_RDWR_OFFSET_NUM    (4)
-#define DPP_SMMU0_READ_REG_MAX_NUM          (4)
-
-/**  SMMU0 调度 fifo ecc 使能标志 */
-#define DPP_SMMU0_PPU_FIFO_POS               (12)
-#define DPP_SMMU0_PPU_FIFO_LEN               (8)
-#define DPP_SMMU0_STAT_FIFO_POS              (11)
-#define DPP_SMMU0_STAT_FIFO_LEN              (1)
-#define DPP_SMMU0_DMA_FIFO_POS               (10)
-#define DPP_SMMU0_DMA_FIFO_LEN               (1)
-#define DPP_SMMU0_ODMA_FIFO_POS              (6)
-#define DPP_SMMU0_ODMA_FIFO_LEN              (4)
-#define DPP_SMMU0_MCAST_FIFO_POS             (5)
-#define DPP_SMMU0_MCAST_FIFO_LEN             (1)
-#define DPP_SMMU0_ETCAM_FIFO_POS             (1)
-#define DPP_SMMU0_ETCAM_FIFO_LEN             (4)
-#define DPP_SMMU0_LPM_FIFO_POS               (0)
-#define DPP_SMMU0_LPM_FIFO_LEN               (1)
-
-#define DPP_SMMU0_CTRL_ECC_CFG_POS           (0)
-#define DPP_SMMU0_CTRL_ECC_CFG_LEN           (3)
-
-#define DPP_SMMU0_RSCHD_RAM_POS              (0)
-#define DPP_SMMU0_RSCHD_RAM_LEN              (1)
-
-#define DPP_SMMU0_ERAM_ECC_CFG_POS           (0)
-#define DPP_SMMU0_ERAM_ECC_CFG_LEN           (24)
-
-#define DPP_SMMU0_WR_ARB_ECC_CFG_POS         (0)
-#define DPP_SMMU0_WR_ARB_ECC_CFG_LEN         (1)
-
-/* smmu0 int0 reg bit define */
-#define SMMU0_INT0_DMA_ORDFIFO_START        (0)
-#define SMMU0_INT0_DMA_ORDFIFO_LEN          (1)
-#define SMMU0_INT0_ODMA_ORDFIFO_START       (1)
-#define SMMU0_INT0_ODMA_ORDFIFO_LEN         (1)
-#define SMMU0_INT0_MCAST_ORDFIFO_START      (2)
-#define SMMU0_INT0_MCAST_ORDFIFO_LEN        (1)
-
-#define DPP_ERAM128_BADDR_MASK              (0x3FFFF80)/* modified for dpp+ 25bit 2018-09-27*/
-
-#define DPP_SE_SMMU1_MAX_BADDR_NO_SHARE     ((1<<20)-1)
-#define DPP_SE_SMMU1_MAX_BADDR_SHARE        ((1<<13)-1)
-#define DPP_SE_SMMU1_MAX_ADDR               ((1<<30)-1)
-
-#define DPP_SE_SMMU1_BANK_NUM_POS           (16)
-#define DPP_SE_SMMU1_BANK_NUM_LEN           (5)
-
-#define DPP_SE_SMMU1_SHARE_TYPE_POS         (21)
-#define DPP_SE_SMMU1_SHARE_TYPE_LEN         (2)
-
-#define DPP_SE_SMMU1_RR_STATE_POS           (0)
-#define DPP_SE_SMMU1_RR_STATE_LEN           (15)
-
-#define DPP_SE_CFG_PPU_INFO_POS             (0)
-#define DPP_SE_CFG_PPU_INFO_LEN             (12)
-
-#define DPP_SE_CFG_DPI_FLAG_POS             (12)
-#define DPP_SE_CFG_DPI_FLAG_LEN             (1)
-
-#define DPP_SE_CFG_WR_FLAG_POS              (13)
-#define DPP_SE_CFG_WR_FLAG_LEN              (1)
-
-
-/** 中断相关 */
-#define DPP_SE_ALG_SCHD_INT_NUM             (14)
-#define DPP_SE_ALG_ZBLK_ECC_INT_NUM         (32)
-#define DPP_SE_ALG_HASH0_INT_NUM            (8)
-#define DPP_SE_ALG_HASH1_INT_NUM            (8)
-#define DPP_SE_ALG_HASH2_INT_NUM            (8)
-#define DPP_SE_ALG_HASH3_INT_NUM            (8)
-#define DPP_SE_ALG_LPM_INT_NUM              (10)
-
-#define DPP_SMMU0_CLS_NUM                   (6)
-#define DPP_SMMU0_STAT_NUM                  (10)
-#define DPP_SMMU0_AS_ETCAM_NUM              (DPP_ETCAM_ID_NUM)
-#define DPP_SMMU0_PLCR_NUM                  (1)
-#define DPP_SMMU0_ERAM_BLOCK_NUM            (32)
-
-#define DPP_SMMU1_SCH_CNT                   (4)/*sch 调度次数 完成6->4调度*/
-//#define DPP_SMMU1_GRP_CNT                   (DPP_SMMU1_DDR_GRP_NUM)
-#define DPP_SMMU1_GRP_CNT                   (8) /*与reg n_size保持一�?*/
-#define DPP_SMMU1_DIR_CHANNEL_CNT           (4)
-
-#define DPP_PARSE_MEX_CHANNEL_NUM           (6)
-#define DPP_PARSE_KSCHD_CHANNEL_NUM         (6)
-#define DPP_RSCHD_PPU_CHANNEL_NUM           (6)
-
-typedef enum smmu1_stat_type_e
-{
-    STAT_TYPE_PPU     = 0,
-    STAT_TYPE_OAM     = 1,
-    STAT_TYPE_MAX,
-}SMMU1_STAT_TYPE_E;
-
-typedef enum alg_lpm_type_e
-{
-    ALG_LPM_V4    = 1,
-    ALG_LPM_V6    = 2,
-    ALG_LPM_V4_AS = 3,
-    ALG_LPM_V6_AS = 4,
-    ALG_LPM_MAX
-}ALG_LPM_TYPE_E;
-
-typedef enum se_ddr_bank_info_e
-{
-    SE_DDR_BKINFO_LPM4    = 0,
-    SE_DDR_BKINFO_LPM6    = 1,
-    SE_DDR_BKINFO_LPM4_AS = 2,
-    SE_DDR_BKINFO_LPM6_AS = 3,
-}SE_DDR_BANK_INFO_E;
-
-typedef enum alg_zblk_serv_type_e
-{
-    ALG_ZBLK_SERV_LPM = 0,
-    ALG_ZBLK_SERV_HASH,
-}ALG_ZBLK_SERV_TYPE_E;
-
-typedef enum cmmu_ddr3_bank_enable_e
-{
-    CMMU_DDR3_BANK_DISABLE = 0,
-    CMMU_DDR3_BANK_ENABLE,
-}CMMU_DDR3_BANK_ENABLE_E;
-
-/** TM统计读片外位�? */
-typedef enum stat_tm_rd_ddr_mode_e
-{
-    STAT_TM_RD_DDR_MODE_128 = 0,
-    STAT_TM_RD_DDR_MODE_256 = 1,
-    STAT_TM_RD_DDR_MODE_512 = 2,
-    STAT_TM_RD_DDR_MODE_MAX,
-}STAT_TM_RD_DDR_MODE_E;
-
-typedef enum stat_tm_rd_clr_mode_e
-{
-    STAT_TM_RD_CLR_MODE_UNCLR     = 0,  /**<  @brief 正常读，读完数据不清�?   */
-    STAT_TM_RD_CLR_MODE_CLR       = 1,  /**<  @brief 读清模式*/
-    STAT_TM_RD_CLR_MODE_MAX,
-}STAT_TM_RD_CLR_MODE_E;
-
-typedef enum se_ddr_map_flag_e
-{
-    VIR_TO_PHY_FLAG       = 0,  /**<  @brief 虚拟地址/bank到物理地址/bank的映�?   */
-    PHY_TO_VIR_FLAG       = 1,  /**<  @brief 物理地址/bank到虚拟地址/bank的映�?   */
-}SE_DDR_MAP_FLAG_E;
-
-/**  module se*/
-typedef enum module_init_se_e
-{
-    MODULE_INIT_SE_SMMU0 = 0,
-    MODULE_INIT_SE_SMMU1,
-    MODULE_INIT_SE_ALG,
-    MODULE_INIT_SE_AS,
-    MODULE_INIT_SE_ETCAM,
-    MODULE_INIT_SE_STAT,
-    MODULE_INIT_SE_FIFO,
-    MODULE_INIT_SE_MAX
-} MODULE_INIT_SE_E;
-
-typedef struct smmu1_kschd_hash_ddr_cfg_t
-{
-    ZXIC_UINT32 baddr;
-    ZXIC_UINT32 crcen;
-    ZXIC_UINT32 mode;
-}SMMU1_KSCHD_HASH_DDR_CFG_T;
-
-typedef struct smmu1_kschd_lpm_ddr_cfg_t
-{
-    ZXIC_UINT32 baddr;
-    ZXIC_UINT32 bankcopy;
-    ZXIC_UINT32 crcen;
-    ZXIC_UINT32 flag;  /* 0-256, 1-384 */
-    ZXIC_UINT32 as_baddr;
-    ZXIC_UINT32 as_bankcopy;
-    ZXIC_UINT32 as_crcen;
-    ZXIC_UINT32 as_mode;
-}SMMU1_KSCHD_LPM_DDR_CFG_T;
-
-typedef struct dpp_lpm_as_eram_info_t
-{
-    ZXIC_UINT32 as_baddr;
-    ZXIC_UINT32 as_mode;
-}DPP_LPM_AS_ERAM_INFO_T;
-
-typedef struct dpp_lpm_res_info_t
-{
-    DPP_LPM_AS_ERAM_INFO_T as_eram_info[DPP_SMMU0_LPM_AS_TBL_ID_NUM];
-    ZXIC_UINT32 v4_ddr_baddr;
-    ZXIC_UINT32 v4_as_ddr_baddr;
-    ZXIC_UINT32 v4_as_rsp_len;
-    ZXIC_UINT32 v6_ddr_baddr;
-    ZXIC_UINT32 v6_as_ddr_baddr;
-    ZXIC_UINT32 v6_as_rsp_len;
-}DPP_LPM_RES_INFO_T;
-
-/*--------------------------------------------------------调试打印计数--------------------------------------------------------*/
-
-/*smmu0 调试打印计数 开�?*/
-typedef struct dpp_smmu0_dbg_cnt_t
-{
-    ZXIC_UINT32 smmu0_rcv_as_age_req_cnt;
-    ZXIC_UINT32 smmu0_rcv_parse_req_cnt;
-    ZXIC_UINT32 smmu0_cpu_ind_rd_rsp_cnt;
-    ZXIC_UINT32 smmu0_cpu_ind_rd_req_cnt;
-    ZXIC_UINT32 smmu0_cpu_ind_wr_req_cnt;
-    
-    ZXIC_UINT32 smmu0_to_plcr_rsp_cnt[DPP_SMMU0_PLCR_NUM];
-    ZXIC_UINT32 smmu0_rcv_plcr_req_cnt[DPP_SMMU0_PLCR_NUM];
-    
-    ZXIC_UINT32 smmu0_to_lpm_as_rsp_cnt;
-    ZXIC_UINT32 smmu0_rcv_lpm_as_req_cnt;
-    
-    ZXIC_UINT32 smmu0_to_as_etacm_rsp_cnt[DPP_SMMU0_AS_ETCAM_NUM];/* 与fc是反�? */
-    ZXIC_UINT32 smmu0_rcv_as_etacm_req_cnt[DPP_SMMU0_AS_ETCAM_NUM];
-
-    ZXIC_UINT32 smmu0_to_ppu_mc_rsp_cnt;
-    ZXIC_UINT32 smmu0_rcv_ppu_mc_req_cnt;
-    ZXIC_UINT32 smmu0_to_odma_tdm_mc_rsp_cnt;
-    ZXIC_UINT32 smmu0_rcv_odma_tdm_mc_req_cnt;
-    ZXIC_UINT32 smmu0_to_odma_rsp_cnt;
-    ZXIC_UINT32 smmu0_rcv_odma_req_cnt;
-    ZXIC_UINT32 smmu0_to_dma_rsp_cnt;
-    ZXIC_UINT32 smmu0_rcv_dma_req_cnt;
-    
-    ZXIC_UINT32 smmu0_to_stat_rsp_cnt[DPP_SMMU0_STAT_NUM];
-    ZXIC_UINT32 smmu0_rcv_stat_req_cnt[DPP_SMMU0_STAT_NUM];
-    ZXIC_UINT32 smmu0_to_ppu_rsp_cnt[DPP_SMMU0_CLS_NUM];
-    ZXIC_UINT32 smmu0_rcv_ppu_req_cnt[DPP_SMMU0_CLS_NUM];
-
-    ZXIC_UINT32 smmu0_rcv_ftm_stat_req0_cnt;
-    ZXIC_UINT32 smmu0_rcv_ftm_stat_req1_cnt;
-    ZXIC_UINT32 smmu0_rcv_etm_stat_req0_cnt;
-    ZXIC_UINT32 smmu0_rcv_etm_stat_req1_cnt;
-
-    ZXIC_UINT32 smmu0_block_rd_cnt[DPP_SMMU0_ERAM_BLOCK_NUM];
-    ZXIC_UINT32 smmu0_block_wr_cnt[DPP_SMMU0_ERAM_BLOCK_NUM];
-
-}DPP_SMMU0_DBG_CNT_T;
-
-typedef struct dpp_smmu0_dbg_fc_cnt_t
-{
-    ZXIC_UINT32 smmu0_to_as_age_req_fc_cnt;
-    ZXIC_UINT32 smmu0_to_parse_req_fc_cnt;
-    ZXIC_UINT32 smmu0_rcv_wr_arb_cpu_fc_cnt;
-    ZXIC_UINT32 smmu0_to_as_lpm_req_fc_cnt;
-    ZXIC_UINT32 smmu0_rcv_as_lpm_rsp_fc_cnt;
-    ZXIC_UINT32 smmu0_to_as_etacm_req_fc_cnt[DPP_SMMU0_AS_ETCAM_NUM];
-    ZXIC_UINT32 smmu0_rcv_as_etacm_rsp_fc_cnt[DPP_SMMU0_AS_ETCAM_NUM];
-    ZXIC_UINT32 smmu0_to_ppu_mc_req_fc_cnt;
-    ZXIC_UINT32 smmu0_rcv_ppu_mc_rsp_fc_cnt;
-    ZXIC_UINT32 smmu0_rcv_odma_tdm_mc_rsp_fc_cnt;
-    ZXIC_UINT32 smmu0_to_odma_tdm_mc_req_fc_cnt;
-    ZXIC_UINT32 smmu0_to_odma_req_fc_cnt;
-    ZXIC_UINT32 smmu0_to_dma_req_fc_cnt;
-    ZXIC_UINT32 smmu0_to_stat_req_fc_cnt[DPP_SMMU0_STAT_NUM];
-    ZXIC_UINT32 smmu0_rcv_stat_rsp_fc_cnt[DPP_SMMU0_STAT_NUM];
-    ZXIC_UINT32 smmu0_to_ppu_req_fc_cnt[DPP_SMMU0_CLS_NUM];
-    ZXIC_UINT32 smmu0_rcv_ppu_rsp_fc_cnt[DPP_SMMU0_CLS_NUM];
-}DPP_SMMU0_DBG_FC_CNT_T;
-/*smmu0 调试打印计数 结束*/
-
-/*smmu1 计数�?*/
-typedef struct dpp_smmu1_dbg_cnt_t
-{
-    ZXIC_UINT32 ctrl_to_cash_fc_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 cash_to_ctrl_req_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 rschd_to_cache_fc_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 cash_to_cache_rsp_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 cash_to_ctrl_fc_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 ctrl_to_cash_rsp_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 kschd_to_cache_req_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 cache_to_kschd_fc_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 dma_to_smmu1_rd_req_cnt;
-    ZXIC_UINT32 oam_to_kschd_req_cnt;
-    ZXIC_UINT32 oam_rr_state_rsp_cnt;
-    ZXIC_UINT32 oam_clash_info_cnt;
-    ZXIC_UINT32 oam_to_rr_req_cnt;
-    ZXIC_UINT32 lpm_as_to_kschd_req_cnt;
-    ZXIC_UINT32 lpm_as_rr_state_rsp_cnt;
-    ZXIC_UINT32 lpm_as_clash_info_cnt;
-    ZXIC_UINT32 lpm_as_to_rr_req_cnt;
-    ZXIC_UINT32 lpm_to_kschd_req_cnt;
-    ZXIC_UINT32 lpm_rr_state_rsp_cnt;
-    ZXIC_UINT32 lpm_clash_info_cnt;
-    ZXIC_UINT32 lpm_to_rr_req_cnt;
-    ZXIC_UINT32 hash_to_kschd_req_cnt[DPP_HASH_ID_NUM];
-    ZXIC_UINT32 hash_rr_state_rsp_cnt[DPP_HASH_ID_NUM];
-    ZXIC_UINT32 hash_clash_info_cnt[DPP_HASH_ID_NUM];
-    ZXIC_UINT32 hash_to_rr_req_cnt[DPP_HASH_ID_NUM];
-    ZXIC_UINT32 dir_to_kschd_req_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
-    ZXIC_UINT32 dir_clash_info_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
-    ZXIC_UINT32 dir_tbl_wr_req_cnt;
-    ZXIC_UINT32 warbi_to_dir_tbl_warbi_fc_cnt;
-    ZXIC_UINT32 dir_to_bank_rr_req_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
-    ZXIC_UINT32 kschd_to_dir_fc_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
-    ZXIC_UINT32 dir_rr_state_rsp_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
-    ZXIC_UINT32 wr_done_to_warbi_fc_cnt;
-    ZXIC_UINT32 wr_done_ptr_req_cnt;
-    ZXIC_UINT32 ctrl_to_warbi_fc_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 warbi_to_ctrl_wr_req_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 warbi_to_cash_wr_req_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 warbi_to_cpu_wr_fc_cnt;
-    ZXIC_UINT32 cpu_wr_req_cnt;
-    ZXIC_UINT32 ctrl_to_cpu_rd_rsp_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 cpu_to_ctrl_rd_req_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 cpu_rd_dir_tbl_rsp_cnt;
-    ZXIC_UINT32 cpu_to_dir_tbl_rd_wr_req_cnt;
-    ZXIC_UINT32 smmu1_to_mmu_rsp_fc_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 mmu_to_smmu1_rd_rsp_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 mmu_to_smmu1_rd_fc_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 smmu1_to_mmu_rd_req_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 mmu_to_smmu1_wr_fc_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 smmu1_to_mmu_wr_req_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 se_to_smmu1_wr_rsp_fc_cnt;
-    ZXIC_UINT32 smmu1_to_se_wr_rsp_cnt;
-    ZXIC_UINT32 ddr_wr_rsp_cnt[DPP_SMMU1_GRP_CNT];
-    ZXIC_UINT32 smmu1_to_as_fc_cnt;
-    ZXIC_UINT32 as_to_smmu1_wr_req_cnt;
-    ZXIC_UINT32 smmu1_to_se_parser_fc_cnt;
-    ZXIC_UINT32 se_parser_to_smmu1_req_cnt;/* 微码写ddr直接�? */
-    ZXIC_UINT32 smmu1_to_etm_wr_fc_cnt;
-    ZXIC_UINT32 etm_wr_req_cnt;
-    ZXIC_UINT32 smmu1_to_ftm_wr_fc_cnt;
-    ZXIC_UINT32 ftm_wr_req_cnt;
-    ZXIC_UINT32 smmu1_to_state_wr_fc_cnt;
-    ZXIC_UINT32 state_wr_req_cnt;
-    ZXIC_UINT32 se_to_dma_rsp_cnt;
-    ZXIC_UINT32 se_to_dma_fc_cnt;
-    ZXIC_UINT32 oam_to_smmu1_fc_cnt;
-    ZXIC_UINT32 smmu1_to_oam_rsp_cnt;
-    ZXIC_UINT32 smmu1_to_oam_fc_cnt;
-    ZXIC_UINT32 oam_to_smmu1_req_cnt;
-    ZXIC_UINT32 smmu1_to_etm_rsp_cnt;
-    ZXIC_UINT32 smmu1_to_ftm_rsp_cnt;
-    ZXIC_UINT32 smmu1_to_etm_fc_cnt;
-    ZXIC_UINT32 etm_to_smmu1_req_cnt;
-    ZXIC_UINT32 smmu1_to_ftm_fc_cnt;
-    ZXIC_UINT32 ftm_to_smmu1_req_cnt;
-    ZXIC_UINT32 smmu1_to_stat_rsp_cnt;
-    ZXIC_UINT32 smmu1_to_stat_fc_cnt;
-    ZXIC_UINT32 stat_to_smmu1_req_cnt;   /* cmmu */
-    ZXIC_UINT32 lpm_as_to_smmu1_fc_cnt;
-    ZXIC_UINT32 lpm_to_smmu1_fc_cnt;
-    ZXIC_UINT32 smmu1_to_lpm_as_rsp_cnt;
-    ZXIC_UINT32 smmu1_to_lpm_rsp_cnt;
-    ZXIC_UINT32 smmu1_to_lpm_as_fc_cnt;
-    ZXIC_UINT32 smmu1_to_lpm_fc_cnt;
-    ZXIC_UINT32 lpm_as_to_smmu1_req_cnt;
-    ZXIC_UINT32 lpm_to_smmu1_req_cnt;
-    ZXIC_UINT32 hash_to_smmu1_fc_cnt[DPP_HASH_ID_NUM];
-    ZXIC_UINT32 smmu1_to_hash_rsp_cnt[DPP_HASH_ID_NUM];
-    ZXIC_UINT32 smmu1_to_hash_fc_cnt[DPP_HASH_ID_NUM];
-    ZXIC_UINT32 hash_to_smmu1_cnt[DPP_HASH_ID_NUM];
-    ZXIC_UINT32 se_to_smmu1_dir_rsp_fc_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
-    ZXIC_UINT32 smmu1_to_se_dir_rsp_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
-    ZXIC_UINT32 smmu1_to_se_dir_fc_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
-    ZXIC_UINT32 se_to_smmu1_dir_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
-    ZXIC_UINT32 cache_to_rschd_rsp_cnt[DPP_SMMU1_GRP_CNT];
-}DPP_SMMU1_DBG_CNT_T;
-
-/*parser 计数�?*/
-typedef struct se_parser_dbg_cnt_t
-{
-    ZXIC_UINT32 mex_req_cnt[DPP_PARSE_MEX_CHANNEL_NUM];
-    ZXIC_UINT32 kschd_req_cnt[DPP_PARSE_KSCHD_CHANNEL_NUM];
-    ZXIC_UINT32 kschd_parser_fc_cnt[DPP_PARSE_KSCHD_CHANNEL_NUM];
-    ZXIC_UINT32 se_ppu_mex_fc_cnt[DPP_PARSE_MEX_CHANNEL_NUM];
-    ZXIC_UINT32 smmu0_marc_fc_cnt;
-    ZXIC_UINT32 smmu0_marc_key_cnt;
-    ZXIC_UINT32 smmu1_key_cnt;
-    ZXIC_UINT32 smmu1_parser_fc_cnt;
-    ZXIC_UINT32 marc_tab_type_err_mex_cnt[DPP_PARSE_MEX_CHANNEL_NUM];
-    ZXIC_UINT32 eram_fulladdr_drop_cnt;
-}SE_PARSER_DBG_CNT_T;
-
-/*kschd 计数�?*/
-typedef struct se_kschd_dbg_cnt_t
-{
-    ZXIC_UINT32 parser_kschd_key_cnt[DPP_PARSE_KSCHD_CHANNEL_NUM];
-    ZXIC_UINT32 kschd_smmu1_key_cnt[DPP_SMMU1_SCH_CNT];
-    ZXIC_UINT32 kschd_to_as_hash0_key_cnt;
-    ZXIC_UINT32 kschd_to_as_hash1_key_cnt;
-    ZXIC_UINT32 kschd_to_as_hash2_key_cnt;
-    ZXIC_UINT32 kschd_to_as_hash3_key_cnt;
-    ZXIC_UINT32 kschd_to_as_lpm_key_cnt;
-    ZXIC_UINT32 kschd_to_as_etacm0_key_cnt;
-    ZXIC_UINT32 kschd_to_as_etacm1_key_cnt;
-    ZXIC_UINT32 kschd_to_as_pbu_key_cnt;
-    ZXIC_UINT32 kschd_to_parser_fc_cnt[DPP_PARSE_KSCHD_CHANNEL_NUM];
-    ZXIC_UINT32 smmu1_kschd_fc_cnt[DPP_SMMU1_SCH_CNT];
-    ZXIC_UINT32 kschd_rcv_as_hash0_fc_cnt;
-    ZXIC_UINT32 kschd_rcv_as_hash1_fc_cnt;
-    ZXIC_UINT32 kschd_rcv_as_hash2_fc_cnt;
-    ZXIC_UINT32 kschd_rcv_as_hash3_fc_cnt;
-    ZXIC_UINT32 kschd_rcv_as_lpm_fc_cnt;
-    ZXIC_UINT32 kschd_rcv_as_etacm0_fc_cnt;
-    ZXIC_UINT32 kschd_rcv_as_etacm1_fc_cnt;
-    ZXIC_UINT32 kschd_rcv_as_pbu_fc_cnt;
-}SE_KSCHD_DBG_CNT_T;
-
-/*rschd 计数�?*/
-typedef struct se_rschd_dbg_cnt_t
-{
-    ZXIC_UINT32 se_ppu_mex_rsp_cnt[DPP_RSCHD_PPU_CHANNEL_NUM];
-    ZXIC_UINT32 rschd_rcv_as_hash0_rsp_cnt;
-    ZXIC_UINT32 rschd_rcv_as_hash1_rsp_cnt;
-    ZXIC_UINT32 rschd_rcv_as_hash2_rsp_cnt;
-    ZXIC_UINT32 rschd_rcv_as_hash3_rsp_cnt;
-    ZXIC_UINT32 rschd_rcv_as_lpm_rsp_cnt;
-    ZXIC_UINT32 rschd_rcv_as_etacm0_rsp_cnt;
-    ZXIC_UINT32 rschd_rcv_as_etacm1_rsp_cnt;
-    ZXIC_UINT32 rschd_rcv_as_pbu_rsp_cnt;
-    ZXIC_UINT32 smmu1_rschd_rsp_cnt[DPP_SMMU1_SCH_CNT];
-    ZXIC_UINT32 ppu_se_mex_fc_cnt[DPP_RSCHD_PPU_CHANNEL_NUM];
-    ZXIC_UINT32 rschd_to_as_hash0_fc_cnt;
-    ZXIC_UINT32 rschd_to_as_hash1_fc_cnt;
-    ZXIC_UINT32 rschd_to_as_hash2_fc_cnt;
-    ZXIC_UINT32 rschd_to_as_hash3_fc_cnt;
-    ZXIC_UINT32 rschd_to_as_lpm_fc_cnt;
-    ZXIC_UINT32 rschd_to_as_etacm0_fc_cnt;
-    ZXIC_UINT32 rschd_to_as_etacm1_fc_cnt;
-    ZXIC_UINT32 rschd_to_as_pbu_fc_cnt;
-    ZXIC_UINT32 rschd_smmu1_rdy_cnt[DPP_SMMU1_SCH_CNT];
-    ZXIC_UINT32 rschd_rcv_smmu0_wr_done_cnt;
-    ZXIC_UINT32 rschd_to_smmu0_wr_done_fc_cnt;
-    ZXIC_UINT32 rschd_rcv_smmu1_wr_done_cnt;
-    ZXIC_UINT32 rschd_to_smmu1_wr_done_fc_cnt;
-    ZXIC_UINT32 rschd_rcv_alg_wr_done_cnt;
-    ZXIC_UINT32 rschd_to_alg_wr_done_fc_cnt;
-}SE_RSCHD_DBG_CNT_T;
-
-/*cmmu 计数�?*/
-typedef struct se_cmmu_dbg_cnt_t
-{
-    ZXIC_UINT32 stat_cmmu_req_cnt;
-    ZXIC_UINT32 cmmu_stat_fc_cnt;
-    ZXIC_UINT32 smmu1_cmmu_wr_fc_cnt;
-    ZXIC_UINT32 smmu1_cmmu_rd_fc_cnt;
-}SE_CMMU_DBG_CNT_T;
-/*cmmu req计数�? 结束*/
-
-/*se_as模块 计数�?*/
-typedef struct se_as_dbg_cnt_t
-{
-    ZXIC_UINT32 hash_wr_req_cnt[DPP_HASH_ID_NUM];
-    ZXIC_UINT32 smmu0_etcam_fc_cnt[DPP_ETCAM_ID_NUM];
-    ZXIC_UINT32 etcam_smmu0_req_cnt[DPP_ETCAM_ID_NUM];
-    ZXIC_UINT32 smmu0_etcam_rsp_cnt[DPP_ETCAM_ID_NUM];
-    ZXIC_UINT32 as_hla_hash_key_cnt[DPP_HASH_ID_NUM];
-    ZXIC_UINT32 as_hla_lpm_key_cnt;
-    ZXIC_UINT32 alg_as_hash_rsp_cnt[DPP_HASH_ID_NUM];
-    ZXIC_UINT32 alg_as_hash_smf_rsp_cnt[DPP_HASH_ID_NUM];/* 命中计数 */
-    ZXIC_UINT32 alg_as_lpm_rsp_cnt;
-    ZXIC_UINT32 alg_as_lpm_smf_rsp_cnt;/* 命中计数 */
-    ZXIC_UINT32 as_pbu_key_cnt;
-    ZXIC_UINT32 pbu_se_dpi_rsp_dat_cnt;
-    ZXIC_UINT32 as_etcam_ctrl_req_cnt[DPP_ETCAM_ID_NUM];
-    ZXIC_UINT32 etcam_ctrl_as_index_cnt[DPP_ETCAM_ID_NUM];/* 有效返回计数 */
-    ZXIC_UINT32 etcam_ctrl_as_hit_cnt[DPP_ETCAM_ID_NUM];
-    ZXIC_UINT32 as_smmu0_req_cnt;
-    ZXIC_UINT32 learn_hla_wr_cnt;/* 硬件学习 */
-    ZXIC_UINT32 as_smmu1_req_cnt;
-    ZXIC_UINT32 se_cfg_mac_dat_cnt;/* 到DMA计数 */
-    ZXIC_UINT32 alg_as_hash_fc_cnt[DPP_HASH_ID_NUM];
-    ZXIC_UINT32 alg_as_lpm_fc_cnt;
-    ZXIC_UINT32 as_alg_hash_fc_cnt[DPP_HASH_ID_NUM];
-    ZXIC_UINT32 as_alg_lpm_fc_cnt;
-    ZXIC_UINT32 as_pbu_fc_cnt;
-    ZXIC_UINT32 pbu_se_dpi_key_fc_cnt;
-    ZXIC_UINT32 as_etcam_ctrl_fc_cnt[DPP_ETCAM_ID_NUM];
-    ZXIC_UINT32 etcam_ctrl_as_fc_cnt[DPP_ETCAM_ID_NUM];
-    ZXIC_UINT32 smmu0_as_mac_age_fc_cnt;
-    ZXIC_UINT32 alg_learn_fc_cnt;
-    ZXIC_UINT32 smmu1_as_fc_cnt;
-    ZXIC_UINT32 cfg_se_mac_fc_cnt;
-}SE_AS_DBG_CNT_T;
-
-
-/* hash 是否响应dma流控使能*/
-typedef enum se_as_hash_dma_fc_en_e
-{
-    HASH_EN_DMA_FC     = 0,
-    HASH_UN_EN_DMA_FC  = 1,
-}SE_AS_HASH_DMA_FC_EN_E;
-/*se_as模块 计数�? 结束*/
-
-/**  alg模块调试计数*/
-typedef struct se_alg_dbg_cnt_t
-{
-    ZXIC_UINT32 hash_key_cnt[4];
-    ZXIC_UINT32 hash_rsp_cnt[4];
-    ZXIC_UINT32 hash_hit_cnt[4];
-    ZXIC_UINT32 hash_space_vld_cnt[4];
-    ZXIC_UINT32 hash_ddr3_req_vld_cnt[4];
-    ZXIC_UINT32 hash_ddr3_rsp_vld_cnt[4];
-
-    ZXIC_UINT32 lpm_key_cnt;
-    ZXIC_UINT32 lpm_rsp_cnt;
-    ZXIC_UINT32 lpm_hit_cnt;
-    ZXIC_UINT32 lpm_key_ddr3_req_vld_cnt; /**<  @brief LPM_SMMU1_P4口用于键�?*/
-    ZXIC_UINT32 lpm_key_ddr3_rsp_vld_cnt; /**<  @brief LPM_SMMU1_P4口用于键�?*/
-    ZXIC_UINT32 lpm_as_ddr3_req_vld_cnt;  /**<  @brief LPM_SMMU1_P5口用于关联结�?*/
-    ZXIC_UINT32 lpm_as_ddr3_rsp_vld_cnt;  /**<  @brief LPM_SMMU1_P5口用于关联结�?*/
-}SE_ALG_DBG_CNT_T;
-
-typedef struct se_alg_dbg_excp_cnt_t
-{
-    ZXIC_UINT32 schd_learn_fifo_int_cnt;
-    ZXIC_UINT32 schd_hash_fifo_int_cnt[4];
-    ZXIC_UINT32 schd_lpm_fifo_int_cnt;
-    ZXIC_UINT32 schd_learn_fifo_parity_err_cnt;
-    ZXIC_UINT32 schd_hash_fifo_parity_err_cnt[4];
-    ZXIC_UINT32 schd_lpm_fifo_parity_err_cnt;
-    ZXIC_UINT32 rd_init_cft_cnt;                 /**<  @brief 初始化过程中出现的CPU读命令冲突计�?*/
-    ZXIC_UINT32 zblk_ecc_err_cnt[32];            /**<  @brief 32个zblock的ecc错误计数*/
-    ZXIC_UINT32 zcam_hash_parity_err_cnt[4];     /**<  @brief 4个hash业务口的parity错误计数*/
-    ZXIC_UINT32 zcam_lpm_err_cnt;                /**<  @brief LPM业务口错误计�?*/
-
-    ZXIC_UINT32 hash_sreq_fifo_parity_err_cnt[4];
-    ZXIC_UINT32 hash_sreq_fifo_int_cnt[4];
-    ZXIC_UINT32 hash_key_fifo_int_cnt[4];
-    ZXIC_UINT32 hash_int_rsp_fifo_parity_err_cnt[4];
-    ZXIC_UINT32 hash_ext_rsp_fifo_parity_err_cnt[4];
-    ZXIC_UINT32 hash_ext_rsp_fifo_int_cnt[4];
-    ZXIC_UINT32 hash_int_rsp_fifo_int_cnt[4];
-
-    ZXIC_UINT32 lpm_ext_rsp_fifo_int_cnt;
-    ZXIC_UINT32 lpm_ext_v6_fifo_int_cnt;
-    ZXIC_UINT32 lpm_ext_v4_fifo_int_cnt;
-    ZXIC_UINT32 lpm_ext_addr_fifo_int_cnt;
-    ZXIC_UINT32 lpm_ext_v4_fifo_parity_err_cnt;
-    ZXIC_UINT32 lpm_ext_v6_fifo_parity_err_cnt;
-    ZXIC_UINT32 lpm_ext_rsp_fifo_parity_err_cnt;
-    ZXIC_UINT32 lpm_as_req_fifo_int_cnt;
-    ZXIC_UINT32 lpm_as_int_rsp_fifo_int_cnt;
-}SE_ALG_DBG_EXCP_CNT_T;
-
-
-#define LPM_HW_DAT_BUFF_SIZE_MAX (16 * 1024)
-typedef enum {
-    LPM_DAT_WR_TYPE_DMA     = 1UL,
-    LPM_DAT_WR_TYPE_REG     = 2UL,
-}LPM_DAT_WR_TYPE;
-
-typedef enum {
-    LPM_DAT_ZECLL     = 1UL,
-    LPM_DAT_ZREG      = 2UL,
-    LPM_DAT_DDR       = 3UL,  
-    LPM_DAT_DDR_RST   = 4UL,        
-    LPM_DAT_ERAM_RST  = 5UL, 
-    LPM_DAT_TYPE_MAX, 
-}ROUTE_DAT_TYPE;
-
-typedef struct _lpm_hw_dat_ddr
-{
-    ZXIC_UINT32         dat_type;     /* ROUTE_DAT_TYPE :LPM_DAT_DDR/LPM_DAT_DDR_RST */
-    ZXIC_UINT32         v4v6_flag;    /* ALG_LPM_TYPE_E */
-    ZXIC_UINT32         lpm_wr_vld;   /* 0-WR 1-RD */
-    ZXIC_UINT32         tbl_id;       /* 对应复制通道 */    
-    ZXIC_UINT32         base_addr;    /* 19b */
-    ZXIC_UINT32         index;        /* by rw_len */
-    ZXIC_UINT32         ecc_en;   
-    ZXIC_UINT32         rw_len;       /* SMMU1_DDR_WRT_MODE_E */
-    ZXIC_UINT8          data[512/8];  /* 左对�? */   
-}ROUTE_HW_DAT_DDR;
-
-typedef struct _lpm_hw_dat_zcam
-{
-    ZXIC_UINT32         dat_type;       /* ROUTE_DAT_TYPE :LPM_DAT_ZREG/LPM_DAT_ZECLL */
-    ZXIC_UINT32         ram_reg_flag;   /* 0-reg 1-cell */
-    ZXIC_UINT32         rw_addr;        /* by 512b */
-    ZXIC_UINT8          data[512/8];    /* 左对�? */  
-}ROUTE_HW_DAT_ZCAM;
-
-typedef struct _lpm_hw_dat_eram
-{
-    ZXIC_UINT32         dat_type;   /* ROUTE_DAT_TYPE :LPM_DAT_ERAM_RST */
-    ZXIC_UINT32         base_addr;  /* by 128b */
-    ZXIC_UINT32         index;      /* by rw_len*/
-    ZXIC_UINT32         rw_len;     /* DPP_ERAM128_TBL_MODE_E */
-    ZXIC_UINT8          data[128/8];/* 左对�? */      
-}ROUTE_HW_DAT_ERAM;
-
-typedef struct ppu_stat_cfg_t
-{
-    ZXIC_UINT32 eram_baddr;           /*片内统计基地址，单位128bit*/
-    ZXIC_UINT32 eram_depth;           /*片内深度，单位128bit*/
-    ZXIC_UINT32 ddr_base_addr;            /*片外统计基地址(PPU和OAM的片外计数共用此基地址)，单位2k*256bit*/
-    ZXIC_UINT32 ppu_addr_offset;      /*PPU统计偏移地址,单位128bit*/
-}PPU_STAT_CFG_T;
-
-/***********************************************************/
-/** dpp hash的smmu1属性设�?
-* @param   dev_id       设备�?
-* @param   hash_id      hash引擎�?
-* @param   tbl_id       hash表号
-* @param   ecc_en       ecc使能
-* @param   baddr        ddr基地址
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  �?
-* @see     
-* @author  ls      @date  2016/04/12
-************************************************************/
-DPP_STATUS dpp_se_smmu1_hash_tbl_cfg_set(DPP_DEV_T *dev,
-                                         ZXIC_UINT32 hash_id,
-                                         ZXIC_UINT32 tbl_id,
-                                         ZXIC_UINT32 ecc_en,
-                                         ZXIC_UINT32 baddr);
-
-/** 获取hash算法访问DDR空间的属性，从软件获取(待优化)
-* @param   dev_id    设备号
-* @param   hash_id      hash引擎号
-* @param   bulk_id      Hash引擎存储资源划分块数的ID号
-* @param   p_ecc_en     使能ECC校验
-* @param   p_base_addr  DDR空间基地址
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  tf      @date  2016/06/15
-************************************************************/
-DPP_STATUS dpp_se_smmu1_hash_tbl_soft_cfg_get(DPP_DEV_T *dev,
-                                              ZXIC_UINT32 hash_id,
-                                              ZXIC_UINT32 bulk_id,
-                                              ZXIC_UINT32 *p_ecc_en,
-                                              ZXIC_UINT32 *p_base_addr);
-
-DPP_STATUS dpp_se_zblk_serv_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 zblk_idx, ZXIC_UINT32 serv_sel, ZXIC_UINT32 hash_id, ZXIC_UINT32 enable);
-
-DPP_STATUS dpp_se_zcell_mono_cfg_set(DPP_DEV_T *dev, 
-                                     ZXIC_UINT32 zblk_idx, 
-                                     ZXIC_UINT32 zcell0_tbl_id, 
-                                     ZXIC_UINT32 zcell0_mono_flag, 
-                                     ZXIC_UINT32 zcell1_tbl_id,
-                                     ZXIC_UINT32 zcell1_mono_flag,
-                                     ZXIC_UINT32 zcell2_tbl_id,
-                                     ZXIC_UINT32 zcell2_mono_flag,
-                                     ZXIC_UINT32 zcell3_tbl_id,
-                                     ZXIC_UINT32 zcell3_mono_flag);
-
-DPP_STATUS dpp_se_zcell_mono_cfg_get(DPP_DEV_T *dev, 
-                                     ZXIC_UINT32 zblk_idx, 
-                                     ZXIC_UINT32 *zcell0_tbl_id, 
-                                     ZXIC_UINT32 *zcell0_mono_flag, 
-                                     ZXIC_UINT32 *zcell1_tbl_id,
-                                     ZXIC_UINT32 *zcell1_mono_flag,
-                                     ZXIC_UINT32 *zcell2_tbl_id,
-                                     ZXIC_UINT32 *zcell2_mono_flag,
-                                     ZXIC_UINT32 *zcell3_tbl_id,
-                                     ZXIC_UINT32 *zcell3_mono_flag);
-
-DPP_STATUS dpp_se_zreg_mono_cfg_set(DPP_DEV_T *dev,           
-                                    ZXIC_UINT32 zblk_idx,            
-                                    ZXIC_UINT32 zreg0_tbl_id,        
-                                    ZXIC_UINT32 zreg0_mono_flag,     
-                                    ZXIC_UINT32 zreg1_tbl_id,        
-                                    ZXIC_UINT32 zreg1_mono_flag,     
-                                    ZXIC_UINT32 zreg2_tbl_id,        
-                                    ZXIC_UINT32 zreg2_mono_flag,     
-                                    ZXIC_UINT32 zreg3_tbl_id,        
-                                    ZXIC_UINT32 zreg3_mono_flag);
-
-DPP_STATUS dpp_se_zreg_mono_cfg_get(DPP_DEV_T *dev, 
-                                     ZXIC_UINT32 zblk_idx, 
-                                     ZXIC_UINT32 *zreg0_tbl_id, 
-                                     ZXIC_UINT32 *zreg0_mono_flag, 
-                                     ZXIC_UINT32 *zreg1_tbl_id,
-                                     ZXIC_UINT32 *zreg1_mono_flag,
-                                     ZXIC_UINT32 *zreg2_tbl_id,
-                                     ZXIC_UINT32 *zreg2_mono_flag,
-                                     ZXIC_UINT32 *zreg3_tbl_id,
-                                     ZXIC_UINT32 *zreg3_mono_flag);
-DPP_STATUS dpp_se_hash_zcam_mono_flags_set(DPP_DEV_T *dev, 
-                                           ZXIC_UINT32 hash0_mono_flag, 
-                                           ZXIC_UINT32 hash1_mono_flag, 
-                                           ZXIC_UINT32 hash2_mono_flag,
-                                           ZXIC_UINT32 hash3_mono_flag);
-
-DPP_STATUS dpp_se_hash_zcam_mono_flags_get(DPP_DEV_T *dev, 
-                                           ZXIC_UINT32 *hash0_mono_flag, 
-                                           ZXIC_UINT32 *hash1_mono_flag, 
-                                           ZXIC_UINT32 *hash2_mono_flag,
-                                           ZXIC_UINT32 *hash3_mono_flag);
-
-DPP_STATUS dpp_se_hash_ext_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 hash_id, ZXIC_UINT32 ext_mode, ZXIC_UINT32 flag);
-DPP_STATUS dpp_se_hash_ext_cfg_get(DPP_DEV_T *dev, ZXIC_UINT32 hash_id, ZXIC_UINT32 *p_content_type, ZXIC_UINT32 *p_flag);
-DPP_STATUS dpp_se_hash_tbl_depth_set(DPP_DEV_T *dev, 
-                                     ZXIC_UINT32 hash_id, 
-                                     ZXIC_UINT32 hash_tbl0_depth,          
-                                     ZXIC_UINT32 hash_tbl1_depth,          
-                                     ZXIC_UINT32 hash_tbl2_depth,          
-                                     ZXIC_UINT32 hash_tbl3_depth,          
-                                     ZXIC_UINT32 hash_tbl4_depth,      
-                                     ZXIC_UINT32 hash_tbl5_depth,      
-                                     ZXIC_UINT32 hash_tbl6_depth,      
-                                     ZXIC_UINT32 hash_tbl7_depth);
-DPP_STATUS dpp_se_hash_tbl_depth_get(DPP_DEV_T *dev, 
-                                     ZXIC_UINT32 hash_id, 
-                                     ZXIC_UINT32 *hash_tbl0_depth,          
-                                     ZXIC_UINT32 *hash_tbl1_depth,          
-                                     ZXIC_UINT32 *hash_tbl2_depth,          
-                                     ZXIC_UINT32 *hash_tbl3_depth,          
-                                     ZXIC_UINT32 *hash_tbl4_depth,      
-                                     ZXIC_UINT32 *hash_tbl5_depth,      
-                                     ZXIC_UINT32 *hash_tbl6_depth,      
-                                     ZXIC_UINT32 *hash_tbl7_depth);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/**************************************************************
+* 版权所�? (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_se.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* �?    �? : 王春�?
+* 完成日期 : 2014/03/11
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* �? �? �?:
+* �? �? �?:
+* 修改内容:
+***************************************************************/
+
+#ifndef _DPP_SE_H_
+#define _DPP_SE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dpp_se_api.h"
+
+#define DPP_HASH_ID_MIN (0)
+#define DPP_HASH_ID_MAX (3)
+#define DPP_HASH_ID_NUM (4)
+
+#define HASH_BULK_ID_MIN (0)
+#define HASH_BULK_ID_MAX (7)
+#define HASH_BULK_NUM (8) /* 每个Hash引擎存储资源划分的块�? */
+
+#define CRC_POLY_SEL_MIN (0)
+#define CRC_POLY_SEL_MAX (3)
+
+#define DPP_LPM_ID_MIN (4)
+#define DPP_LPM_ID_MAX (5)
+#define DPP_LPM_ID_NUM (2)
+
+#define DPP_ETCAM_ID_MIN (0)
+#define DPP_ETCAM_ID_MAX (0)
+#define DPP_ETCAM_ID_NUM (1)
+
+#define DPP_AGE_TBL_ID_MIN (0)
+#define DPP_AGE_TBL_ID_MAX (15)
+
+#define DPP_SMMU1_DDR_GRP_NUM (1)
+
+//#define DPP_SMMU1_DIR_TBL_BANK_MAX          (15)
+#define DPP_SMMU1_DIR_TBL_INDEX_MAX (255)
+//#define DPP_SMMU1_UN_DIR_TBL_BANK_MAX       (29)
+
+#define DPP_SMMU1_HASH_TBL_INDEX_BASE (1)
+#define DPP_SMMU1_HASH_TBL_INDEX_MAX (31)
+#define DPP_SMMU1_LPM_TBL_INDEX_BASE (33)
+#define DPP_SMMU1_LPM_TBL_INDEX_MAX (3)
+#define DPP_SMMU1_OAM_TBL_INDEX_BASE (37)
+#define DPP_SMMU1_FTM_TBL_INDEX_BASE (38)
+#define DPP_SMMU1_ETM_TBL_INDEX_BASE (39)
+#define DPP_SMMU1_DIR_TBL_INDEX_BASE (40)
+
+#define DPP_SMMU1_SINGLE_BNAK_MAX_ADDR ((1 << 25) - 1)
+#define DPP_SMMU1_SINGLE_BANK_MAX_BADDR (DPP_SMMU1_SINGLE_BNAK_MAX_ADDR >> 12)
+#define DPP_SMMU1_TOTAL_BANK_NUM (8)
+#define DPP_SMMU1_TOTAL_MAX_ADDR (0xffffffff)
+#define DPP_SMMU1_TOTAL_MAX_BADDR (DPP_SMMU1_TOTAL_MAX_ADDR >> 12)
+#define DPP_SMMU1_BADDR_MASK (0x7ffff800)
+#define DPP_SMMU1_DDR_GROUP_NUM (1)
+#define DPP_SMMU1_BANK_COPY_MAX_NUM (16)
+#define DPP_SMMU1_READ_REG_MAX_NUM (16)
+#define DPP_DIR_TBL_BUF_MAX_NUM (DPP_SMMU1_READ_REG_MAX_NUM)
+
+/*hash ext crc cfg*/
+#define HASH_ECC_EN_BT_START (2)
+#define HASH_ECC_EN_BT_WIDTH (1)
+#define HASH_BANK_COPY_BT_START (3)
+#define HASH_BANK_COPY_BT_WIDTH (3)
+#define HASH_BASE_ADDR_BT_START (6)
+#define HASH_BASE_ADDR_BT_WIDTH (15)
+/*hash learn  tbl cfg*/
+#define LEARN_HASH_TBL_BT_START (0)
+#define LEARN_HASH_TBL_BT_WIDTH (19)
+
+#define DPP_SMMU0_MCAST_TBL_MAX_GROUP (0xffff)
+
+#define DPP_SMMU0_CAR0_MONO_POS (0)
+#define DPP_SMMU0_CAR0_MONO_LEN (1)
+#define DPP_SMMU0_CAR0_EN_POS (1)
+#define DPP_SMMU0_CAR0_EN_LEN (1)
+#define DPP_SMMU0_CAR1_MONO_POS (2)
+#define DPP_SMMU0_CAR1_MONO_LEN (1)
+#define DPP_SMMU0_CAR1_EN_POS (3)
+#define DPP_SMMU0_CAR1_EN_LEN (1)
+
+#define DPP_SMMU0_LPM_AS_TBL_ID_MAX (7)
+#define DPP_SMMU0_LPM_AS_TBL_ID_NUM (8)
+
+#define DPP_SMMU0_MCAST_DATA_VLD_POS (16)
+#define DPP_SMMU0_MCAST_DATA_VLD_LEN (1)
+#define DPP_SMMU0_MCAST_CNT_POS (0)
+#define DPP_SMMU0_MCAST_CNT_LEN (16)
+
+#define DPP_SMMU0_INDIER_RDWR_OFFSET_NUM (4)
+#define DPP_SMMU0_READ_REG_MAX_NUM (4)
+
+/**  SMMU0 调度 fifo ecc 使能标志 */
+#define DPP_SMMU0_PPU_FIFO_POS (12)
+#define DPP_SMMU0_PPU_FIFO_LEN (8)
+#define DPP_SMMU0_STAT_FIFO_POS (11)
+#define DPP_SMMU0_STAT_FIFO_LEN (1)
+#define DPP_SMMU0_DMA_FIFO_POS (10)
+#define DPP_SMMU0_DMA_FIFO_LEN (1)
+#define DPP_SMMU0_ODMA_FIFO_POS (6)
+#define DPP_SMMU0_ODMA_FIFO_LEN (4)
+#define DPP_SMMU0_MCAST_FIFO_POS (5)
+#define DPP_SMMU0_MCAST_FIFO_LEN (1)
+#define DPP_SMMU0_ETCAM_FIFO_POS (1)
+#define DPP_SMMU0_ETCAM_FIFO_LEN (4)
+#define DPP_SMMU0_LPM_FIFO_POS (0)
+#define DPP_SMMU0_LPM_FIFO_LEN (1)
+
+#define DPP_SMMU0_CTRL_ECC_CFG_POS (0)
+#define DPP_SMMU0_CTRL_ECC_CFG_LEN (3)
+
+#define DPP_SMMU0_RSCHD_RAM_POS (0)
+#define DPP_SMMU0_RSCHD_RAM_LEN (1)
+
+#define DPP_SMMU0_ERAM_ECC_CFG_POS (0)
+#define DPP_SMMU0_ERAM_ECC_CFG_LEN (24)
+
+#define DPP_SMMU0_WR_ARB_ECC_CFG_POS (0)
+#define DPP_SMMU0_WR_ARB_ECC_CFG_LEN (1)
+
+/* smmu0 int0 reg bit define */
+#define SMMU0_INT0_DMA_ORDFIFO_START (0)
+#define SMMU0_INT0_DMA_ORDFIFO_LEN (1)
+#define SMMU0_INT0_ODMA_ORDFIFO_START (1)
+#define SMMU0_INT0_ODMA_ORDFIFO_LEN (1)
+#define SMMU0_INT0_MCAST_ORDFIFO_START (2)
+#define SMMU0_INT0_MCAST_ORDFIFO_LEN (1)
+
+#define DPP_ERAM128_BADDR_MASK \
+	(0x3FFFF80) /* modified for dpp+ 25bit 2018-09-27*/
+
+#define DPP_SE_SMMU1_MAX_BADDR_NO_SHARE ((1 << 20) - 1)
+#define DPP_SE_SMMU1_MAX_BADDR_SHARE ((1 << 13) - 1)
+#define DPP_SE_SMMU1_MAX_ADDR ((1 << 30) - 1)
+
+#define DPP_SE_SMMU1_BANK_NUM_POS (16)
+#define DPP_SE_SMMU1_BANK_NUM_LEN (5)
+
+#define DPP_SE_SMMU1_SHARE_TYPE_POS (21)
+#define DPP_SE_SMMU1_SHARE_TYPE_LEN (2)
+
+#define DPP_SE_SMMU1_RR_STATE_POS (0)
+#define DPP_SE_SMMU1_RR_STATE_LEN (15)
+
+#define DPP_SE_CFG_PPU_INFO_POS (0)
+#define DPP_SE_CFG_PPU_INFO_LEN (12)
+
+#define DPP_SE_CFG_DPI_FLAG_POS (12)
+#define DPP_SE_CFG_DPI_FLAG_LEN (1)
+
+#define DPP_SE_CFG_WR_FLAG_POS (13)
+#define DPP_SE_CFG_WR_FLAG_LEN (1)
+
+/** 中断相关 */
+#define DPP_SE_ALG_SCHD_INT_NUM (14)
+#define DPP_SE_ALG_ZBLK_ECC_INT_NUM (32)
+#define DPP_SE_ALG_HASH0_INT_NUM (8)
+#define DPP_SE_ALG_HASH1_INT_NUM (8)
+#define DPP_SE_ALG_HASH2_INT_NUM (8)
+#define DPP_SE_ALG_HASH3_INT_NUM (8)
+#define DPP_SE_ALG_LPM_INT_NUM (10)
+
+#define DPP_SMMU0_CLS_NUM (6)
+#define DPP_SMMU0_STAT_NUM (10)
+#define DPP_SMMU0_AS_ETCAM_NUM (DPP_ETCAM_ID_NUM)
+#define DPP_SMMU0_PLCR_NUM (1)
+#define DPP_SMMU0_ERAM_BLOCK_NUM (32)
+
+#define DPP_SMMU1_SCH_CNT (4) /*sch 调度次数 完成6->4调度*/
+//#define DPP_SMMU1_GRP_CNT                   (DPP_SMMU1_DDR_GRP_NUM)
+#define DPP_SMMU1_GRP_CNT (8) /*与reg n_size保持一�?*/
+#define DPP_SMMU1_DIR_CHANNEL_CNT (4)
+
+#define DPP_PARSE_MEX_CHANNEL_NUM (6)
+#define DPP_PARSE_KSCHD_CHANNEL_NUM (6)
+#define DPP_RSCHD_PPU_CHANNEL_NUM (6)
+
+typedef enum smmu1_stat_type_e {
+	STAT_TYPE_PPU = 0,
+	STAT_TYPE_OAM = 1,
+	STAT_TYPE_MAX,
+} SMMU1_STAT_TYPE_E;
+
+typedef enum alg_lpm_type_e {
+	ALG_LPM_V4 = 1,
+	ALG_LPM_V6 = 2,
+	ALG_LPM_V4_AS = 3,
+	ALG_LPM_V6_AS = 4,
+	ALG_LPM_MAX
+} ALG_LPM_TYPE_E;
+
+typedef enum se_ddr_bank_info_e {
+	SE_DDR_BKINFO_LPM4 = 0,
+	SE_DDR_BKINFO_LPM6 = 1,
+	SE_DDR_BKINFO_LPM4_AS = 2,
+	SE_DDR_BKINFO_LPM6_AS = 3,
+} SE_DDR_BANK_INFO_E;
+
+typedef enum alg_zblk_serv_type_e {
+	ALG_ZBLK_SERV_LPM = 0,
+	ALG_ZBLK_SERV_HASH,
+} ALG_ZBLK_SERV_TYPE_E;
+
+typedef enum cmmu_ddr3_bank_enable_e {
+	CMMU_DDR3_BANK_DISABLE = 0,
+	CMMU_DDR3_BANK_ENABLE,
+} CMMU_DDR3_BANK_ENABLE_E;
+
+/** TM统计读片外位�? */
+typedef enum stat_tm_rd_ddr_mode_e {
+	STAT_TM_RD_DDR_MODE_128 = 0,
+	STAT_TM_RD_DDR_MODE_256 = 1,
+	STAT_TM_RD_DDR_MODE_512 = 2,
+	STAT_TM_RD_DDR_MODE_MAX,
+} STAT_TM_RD_DDR_MODE_E;
+
+typedef enum stat_tm_rd_clr_mode_e {
+	STAT_TM_RD_CLR_MODE_UNCLR = 0, /**<  @brief 正常读，读完数据不清�?   */
+	STAT_TM_RD_CLR_MODE_CLR = 1, /**<  @brief 读清模式*/
+	STAT_TM_RD_CLR_MODE_MAX,
+} STAT_TM_RD_CLR_MODE_E;
+
+typedef enum se_ddr_map_flag_e {
+	VIR_TO_PHY_FLAG = 0, /**<  @brief 虚拟地址/bank到物理地址/bank的映�?   */
+	PHY_TO_VIR_FLAG = 1, /**<  @brief 物理地址/bank到虚拟地址/bank的映�?   */
+} SE_DDR_MAP_FLAG_E;
+
+/**  module se*/
+typedef enum module_init_se_e {
+	MODULE_INIT_SE_SMMU0 = 0,
+	MODULE_INIT_SE_SMMU1,
+	MODULE_INIT_SE_ALG,
+	MODULE_INIT_SE_AS,
+	MODULE_INIT_SE_ETCAM,
+	MODULE_INIT_SE_STAT,
+	MODULE_INIT_SE_FIFO,
+	MODULE_INIT_SE_MAX
+} MODULE_INIT_SE_E;
+
+typedef struct smmu1_kschd_hash_ddr_cfg_t {
+	ZXIC_UINT32 baddr;
+	ZXIC_UINT32 crcen;
+	ZXIC_UINT32 mode;
+} SMMU1_KSCHD_HASH_DDR_CFG_T;
+
+typedef struct smmu1_kschd_lpm_ddr_cfg_t {
+	ZXIC_UINT32 baddr;
+	ZXIC_UINT32 bankcopy;
+	ZXIC_UINT32 crcen;
+	ZXIC_UINT32 flag; /* 0-256, 1-384 */
+	ZXIC_UINT32 as_baddr;
+	ZXIC_UINT32 as_bankcopy;
+	ZXIC_UINT32 as_crcen;
+	ZXIC_UINT32 as_mode;
+} SMMU1_KSCHD_LPM_DDR_CFG_T;
+
+typedef struct dpp_lpm_as_eram_info_t {
+	ZXIC_UINT32 as_baddr;
+	ZXIC_UINT32 as_mode;
+} DPP_LPM_AS_ERAM_INFO_T;
+
+typedef struct dpp_lpm_res_info_t {
+	DPP_LPM_AS_ERAM_INFO_T as_eram_info[DPP_SMMU0_LPM_AS_TBL_ID_NUM];
+	ZXIC_UINT32 v4_ddr_baddr;
+	ZXIC_UINT32 v4_as_ddr_baddr;
+	ZXIC_UINT32 v4_as_rsp_len;
+	ZXIC_UINT32 v6_ddr_baddr;
+	ZXIC_UINT32 v6_as_ddr_baddr;
+	ZXIC_UINT32 v6_as_rsp_len;
+} DPP_LPM_RES_INFO_T;
+
+/*--------------------------------------------------------调试打印计数--------------------------------------------------------*/
+
+/*smmu0 调试打印计数 开�?*/
+typedef struct dpp_smmu0_dbg_cnt_t {
+	ZXIC_UINT32 smmu0_rcv_as_age_req_cnt;
+	ZXIC_UINT32 smmu0_rcv_parse_req_cnt;
+	ZXIC_UINT32 smmu0_cpu_ind_rd_rsp_cnt;
+	ZXIC_UINT32 smmu0_cpu_ind_rd_req_cnt;
+	ZXIC_UINT32 smmu0_cpu_ind_wr_req_cnt;
+
+	ZXIC_UINT32 smmu0_to_plcr_rsp_cnt[DPP_SMMU0_PLCR_NUM];
+	ZXIC_UINT32 smmu0_rcv_plcr_req_cnt[DPP_SMMU0_PLCR_NUM];
+
+	ZXIC_UINT32 smmu0_to_lpm_as_rsp_cnt;
+	ZXIC_UINT32 smmu0_rcv_lpm_as_req_cnt;
+
+	ZXIC_UINT32
+	smmu0_to_as_etacm_rsp_cnt[DPP_SMMU0_AS_ETCAM_NUM]; /* 与fc是反�? */
+	ZXIC_UINT32 smmu0_rcv_as_etacm_req_cnt[DPP_SMMU0_AS_ETCAM_NUM];
+
+	ZXIC_UINT32 smmu0_to_ppu_mc_rsp_cnt;
+	ZXIC_UINT32 smmu0_rcv_ppu_mc_req_cnt;
+	ZXIC_UINT32 smmu0_to_odma_tdm_mc_rsp_cnt;
+	ZXIC_UINT32 smmu0_rcv_odma_tdm_mc_req_cnt;
+	ZXIC_UINT32 smmu0_to_odma_rsp_cnt;
+	ZXIC_UINT32 smmu0_rcv_odma_req_cnt;
+	ZXIC_UINT32 smmu0_to_dma_rsp_cnt;
+	ZXIC_UINT32 smmu0_rcv_dma_req_cnt;
+
+	ZXIC_UINT32 smmu0_to_stat_rsp_cnt[DPP_SMMU0_STAT_NUM];
+	ZXIC_UINT32 smmu0_rcv_stat_req_cnt[DPP_SMMU0_STAT_NUM];
+	ZXIC_UINT32 smmu0_to_ppu_rsp_cnt[DPP_SMMU0_CLS_NUM];
+	ZXIC_UINT32 smmu0_rcv_ppu_req_cnt[DPP_SMMU0_CLS_NUM];
+
+	ZXIC_UINT32 smmu0_rcv_ftm_stat_req0_cnt;
+	ZXIC_UINT32 smmu0_rcv_ftm_stat_req1_cnt;
+	ZXIC_UINT32 smmu0_rcv_etm_stat_req0_cnt;
+	ZXIC_UINT32 smmu0_rcv_etm_stat_req1_cnt;
+
+	ZXIC_UINT32 smmu0_block_rd_cnt[DPP_SMMU0_ERAM_BLOCK_NUM];
+	ZXIC_UINT32 smmu0_block_wr_cnt[DPP_SMMU0_ERAM_BLOCK_NUM];
+
+} DPP_SMMU0_DBG_CNT_T;
+
+typedef struct dpp_smmu0_dbg_fc_cnt_t {
+	ZXIC_UINT32 smmu0_to_as_age_req_fc_cnt;
+	ZXIC_UINT32 smmu0_to_parse_req_fc_cnt;
+	ZXIC_UINT32 smmu0_rcv_wr_arb_cpu_fc_cnt;
+	ZXIC_UINT32 smmu0_to_as_lpm_req_fc_cnt;
+	ZXIC_UINT32 smmu0_rcv_as_lpm_rsp_fc_cnt;
+	ZXIC_UINT32 smmu0_to_as_etacm_req_fc_cnt[DPP_SMMU0_AS_ETCAM_NUM];
+	ZXIC_UINT32 smmu0_rcv_as_etacm_rsp_fc_cnt[DPP_SMMU0_AS_ETCAM_NUM];
+	ZXIC_UINT32 smmu0_to_ppu_mc_req_fc_cnt;
+	ZXIC_UINT32 smmu0_rcv_ppu_mc_rsp_fc_cnt;
+	ZXIC_UINT32 smmu0_rcv_odma_tdm_mc_rsp_fc_cnt;
+	ZXIC_UINT32 smmu0_to_odma_tdm_mc_req_fc_cnt;
+	ZXIC_UINT32 smmu0_to_odma_req_fc_cnt;
+	ZXIC_UINT32 smmu0_to_dma_req_fc_cnt;
+	ZXIC_UINT32 smmu0_to_stat_req_fc_cnt[DPP_SMMU0_STAT_NUM];
+	ZXIC_UINT32 smmu0_rcv_stat_rsp_fc_cnt[DPP_SMMU0_STAT_NUM];
+	ZXIC_UINT32 smmu0_to_ppu_req_fc_cnt[DPP_SMMU0_CLS_NUM];
+	ZXIC_UINT32 smmu0_rcv_ppu_rsp_fc_cnt[DPP_SMMU0_CLS_NUM];
+} DPP_SMMU0_DBG_FC_CNT_T;
+/*smmu0 调试打印计数 结束*/
+
+/*smmu1 计数�?*/
+typedef struct dpp_smmu1_dbg_cnt_t {
+	ZXIC_UINT32 ctrl_to_cash_fc_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 cash_to_ctrl_req_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 rschd_to_cache_fc_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 cash_to_cache_rsp_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 cash_to_ctrl_fc_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 ctrl_to_cash_rsp_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 kschd_to_cache_req_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 cache_to_kschd_fc_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 dma_to_smmu1_rd_req_cnt;
+	ZXIC_UINT32 oam_to_kschd_req_cnt;
+	ZXIC_UINT32 oam_rr_state_rsp_cnt;
+	ZXIC_UINT32 oam_clash_info_cnt;
+	ZXIC_UINT32 oam_to_rr_req_cnt;
+	ZXIC_UINT32 lpm_as_to_kschd_req_cnt;
+	ZXIC_UINT32 lpm_as_rr_state_rsp_cnt;
+	ZXIC_UINT32 lpm_as_clash_info_cnt;
+	ZXIC_UINT32 lpm_as_to_rr_req_cnt;
+	ZXIC_UINT32 lpm_to_kschd_req_cnt;
+	ZXIC_UINT32 lpm_rr_state_rsp_cnt;
+	ZXIC_UINT32 lpm_clash_info_cnt;
+	ZXIC_UINT32 lpm_to_rr_req_cnt;
+	ZXIC_UINT32 hash_to_kschd_req_cnt[DPP_HASH_ID_NUM];
+	ZXIC_UINT32 hash_rr_state_rsp_cnt[DPP_HASH_ID_NUM];
+	ZXIC_UINT32 hash_clash_info_cnt[DPP_HASH_ID_NUM];
+	ZXIC_UINT32 hash_to_rr_req_cnt[DPP_HASH_ID_NUM];
+	ZXIC_UINT32 dir_to_kschd_req_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
+	ZXIC_UINT32 dir_clash_info_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
+	ZXIC_UINT32 dir_tbl_wr_req_cnt;
+	ZXIC_UINT32 warbi_to_dir_tbl_warbi_fc_cnt;
+	ZXIC_UINT32 dir_to_bank_rr_req_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
+	ZXIC_UINT32 kschd_to_dir_fc_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
+	ZXIC_UINT32 dir_rr_state_rsp_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
+	ZXIC_UINT32 wr_done_to_warbi_fc_cnt;
+	ZXIC_UINT32 wr_done_ptr_req_cnt;
+	ZXIC_UINT32 ctrl_to_warbi_fc_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 warbi_to_ctrl_wr_req_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 warbi_to_cash_wr_req_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 warbi_to_cpu_wr_fc_cnt;
+	ZXIC_UINT32 cpu_wr_req_cnt;
+	ZXIC_UINT32 ctrl_to_cpu_rd_rsp_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 cpu_to_ctrl_rd_req_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 cpu_rd_dir_tbl_rsp_cnt;
+	ZXIC_UINT32 cpu_to_dir_tbl_rd_wr_req_cnt;
+	ZXIC_UINT32 smmu1_to_mmu_rsp_fc_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 mmu_to_smmu1_rd_rsp_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 mmu_to_smmu1_rd_fc_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 smmu1_to_mmu_rd_req_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 mmu_to_smmu1_wr_fc_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 smmu1_to_mmu_wr_req_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 se_to_smmu1_wr_rsp_fc_cnt;
+	ZXIC_UINT32 smmu1_to_se_wr_rsp_cnt;
+	ZXIC_UINT32 ddr_wr_rsp_cnt[DPP_SMMU1_GRP_CNT];
+	ZXIC_UINT32 smmu1_to_as_fc_cnt;
+	ZXIC_UINT32 as_to_smmu1_wr_req_cnt;
+	ZXIC_UINT32 smmu1_to_se_parser_fc_cnt;
+	ZXIC_UINT32 se_parser_to_smmu1_req_cnt; /* 微码写ddr直接�? */
+	ZXIC_UINT32 smmu1_to_etm_wr_fc_cnt;
+	ZXIC_UINT32 etm_wr_req_cnt;
+	ZXIC_UINT32 smmu1_to_ftm_wr_fc_cnt;
+	ZXIC_UINT32 ftm_wr_req_cnt;
+	ZXIC_UINT32 smmu1_to_state_wr_fc_cnt;
+	ZXIC_UINT32 state_wr_req_cnt;
+	ZXIC_UINT32 se_to_dma_rsp_cnt;
+	ZXIC_UINT32 se_to_dma_fc_cnt;
+	ZXIC_UINT32 oam_to_smmu1_fc_cnt;
+	ZXIC_UINT32 smmu1_to_oam_rsp_cnt;
+	ZXIC_UINT32 smmu1_to_oam_fc_cnt;
+	ZXIC_UINT32 oam_to_smmu1_req_cnt;
+	ZXIC_UINT32 smmu1_to_etm_rsp_cnt;
+	ZXIC_UINT32 smmu1_to_ftm_rsp_cnt;
+	ZXIC_UINT32 smmu1_to_etm_fc_cnt;
+	ZXIC_UINT32 etm_to_smmu1_req_cnt;
+	ZXIC_UINT32 smmu1_to_ftm_fc_cnt;
+	ZXIC_UINT32 ftm_to_smmu1_req_cnt;
+	ZXIC_UINT32 smmu1_to_stat_rsp_cnt;
+	ZXIC_UINT32 smmu1_to_stat_fc_cnt;
+	ZXIC_UINT32 stat_to_smmu1_req_cnt; /* cmmu */
+	ZXIC_UINT32 lpm_as_to_smmu1_fc_cnt;
+	ZXIC_UINT32 lpm_to_smmu1_fc_cnt;
+	ZXIC_UINT32 smmu1_to_lpm_as_rsp_cnt;
+	ZXIC_UINT32 smmu1_to_lpm_rsp_cnt;
+	ZXIC_UINT32 smmu1_to_lpm_as_fc_cnt;
+	ZXIC_UINT32 smmu1_to_lpm_fc_cnt;
+	ZXIC_UINT32 lpm_as_to_smmu1_req_cnt;
+	ZXIC_UINT32 lpm_to_smmu1_req_cnt;
+	ZXIC_UINT32 hash_to_smmu1_fc_cnt[DPP_HASH_ID_NUM];
+	ZXIC_UINT32 smmu1_to_hash_rsp_cnt[DPP_HASH_ID_NUM];
+	ZXIC_UINT32 smmu1_to_hash_fc_cnt[DPP_HASH_ID_NUM];
+	ZXIC_UINT32 hash_to_smmu1_cnt[DPP_HASH_ID_NUM];
+	ZXIC_UINT32 se_to_smmu1_dir_rsp_fc_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
+	ZXIC_UINT32 smmu1_to_se_dir_rsp_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
+	ZXIC_UINT32 smmu1_to_se_dir_fc_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
+	ZXIC_UINT32 se_to_smmu1_dir_cnt[DPP_SMMU1_DIR_CHANNEL_CNT];
+	ZXIC_UINT32 cache_to_rschd_rsp_cnt[DPP_SMMU1_GRP_CNT];
+} DPP_SMMU1_DBG_CNT_T;
+
+/*parser 计数�?*/
+typedef struct se_parser_dbg_cnt_t {
+	ZXIC_UINT32 mex_req_cnt[DPP_PARSE_MEX_CHANNEL_NUM];
+	ZXIC_UINT32 kschd_req_cnt[DPP_PARSE_KSCHD_CHANNEL_NUM];
+	ZXIC_UINT32 kschd_parser_fc_cnt[DPP_PARSE_KSCHD_CHANNEL_NUM];
+	ZXIC_UINT32 se_ppu_mex_fc_cnt[DPP_PARSE_MEX_CHANNEL_NUM];
+	ZXIC_UINT32 smmu0_marc_fc_cnt;
+	ZXIC_UINT32 smmu0_marc_key_cnt;
+	ZXIC_UINT32 smmu1_key_cnt;
+	ZXIC_UINT32 smmu1_parser_fc_cnt;
+	ZXIC_UINT32 marc_tab_type_err_mex_cnt[DPP_PARSE_MEX_CHANNEL_NUM];
+	ZXIC_UINT32 eram_fulladdr_drop_cnt;
+} SE_PARSER_DBG_CNT_T;
+
+/*kschd 计数�?*/
+typedef struct se_kschd_dbg_cnt_t {
+	ZXIC_UINT32 parser_kschd_key_cnt[DPP_PARSE_KSCHD_CHANNEL_NUM];
+	ZXIC_UINT32 kschd_smmu1_key_cnt[DPP_SMMU1_SCH_CNT];
+	ZXIC_UINT32 kschd_to_as_hash0_key_cnt;
+	ZXIC_UINT32 kschd_to_as_hash1_key_cnt;
+	ZXIC_UINT32 kschd_to_as_hash2_key_cnt;
+	ZXIC_UINT32 kschd_to_as_hash3_key_cnt;
+	ZXIC_UINT32 kschd_to_as_lpm_key_cnt;
+	ZXIC_UINT32 kschd_to_as_etacm0_key_cnt;
+	ZXIC_UINT32 kschd_to_as_etacm1_key_cnt;
+	ZXIC_UINT32 kschd_to_as_pbu_key_cnt;
+	ZXIC_UINT32 kschd_to_parser_fc_cnt[DPP_PARSE_KSCHD_CHANNEL_NUM];
+	ZXIC_UINT32 smmu1_kschd_fc_cnt[DPP_SMMU1_SCH_CNT];
+	ZXIC_UINT32 kschd_rcv_as_hash0_fc_cnt;
+	ZXIC_UINT32 kschd_rcv_as_hash1_fc_cnt;
+	ZXIC_UINT32 kschd_rcv_as_hash2_fc_cnt;
+	ZXIC_UINT32 kschd_rcv_as_hash3_fc_cnt;
+	ZXIC_UINT32 kschd_rcv_as_lpm_fc_cnt;
+	ZXIC_UINT32 kschd_rcv_as_etacm0_fc_cnt;
+	ZXIC_UINT32 kschd_rcv_as_etacm1_fc_cnt;
+	ZXIC_UINT32 kschd_rcv_as_pbu_fc_cnt;
+} SE_KSCHD_DBG_CNT_T;
+
+/*rschd 计数�?*/
+typedef struct se_rschd_dbg_cnt_t {
+	ZXIC_UINT32 se_ppu_mex_rsp_cnt[DPP_RSCHD_PPU_CHANNEL_NUM];
+	ZXIC_UINT32 rschd_rcv_as_hash0_rsp_cnt;
+	ZXIC_UINT32 rschd_rcv_as_hash1_rsp_cnt;
+	ZXIC_UINT32 rschd_rcv_as_hash2_rsp_cnt;
+	ZXIC_UINT32 rschd_rcv_as_hash3_rsp_cnt;
+	ZXIC_UINT32 rschd_rcv_as_lpm_rsp_cnt;
+	ZXIC_UINT32 rschd_rcv_as_etacm0_rsp_cnt;
+	ZXIC_UINT32 rschd_rcv_as_etacm1_rsp_cnt;
+	ZXIC_UINT32 rschd_rcv_as_pbu_rsp_cnt;
+	ZXIC_UINT32 smmu1_rschd_rsp_cnt[DPP_SMMU1_SCH_CNT];
+	ZXIC_UINT32 ppu_se_mex_fc_cnt[DPP_RSCHD_PPU_CHANNEL_NUM];
+	ZXIC_UINT32 rschd_to_as_hash0_fc_cnt;
+	ZXIC_UINT32 rschd_to_as_hash1_fc_cnt;
+	ZXIC_UINT32 rschd_to_as_hash2_fc_cnt;
+	ZXIC_UINT32 rschd_to_as_hash3_fc_cnt;
+	ZXIC_UINT32 rschd_to_as_lpm_fc_cnt;
+	ZXIC_UINT32 rschd_to_as_etacm0_fc_cnt;
+	ZXIC_UINT32 rschd_to_as_etacm1_fc_cnt;
+	ZXIC_UINT32 rschd_to_as_pbu_fc_cnt;
+	ZXIC_UINT32 rschd_smmu1_rdy_cnt[DPP_SMMU1_SCH_CNT];
+	ZXIC_UINT32 rschd_rcv_smmu0_wr_done_cnt;
+	ZXIC_UINT32 rschd_to_smmu0_wr_done_fc_cnt;
+	ZXIC_UINT32 rschd_rcv_smmu1_wr_done_cnt;
+	ZXIC_UINT32 rschd_to_smmu1_wr_done_fc_cnt;
+	ZXIC_UINT32 rschd_rcv_alg_wr_done_cnt;
+	ZXIC_UINT32 rschd_to_alg_wr_done_fc_cnt;
+} SE_RSCHD_DBG_CNT_T;
+
+/*cmmu 计数�?*/
+typedef struct se_cmmu_dbg_cnt_t {
+	ZXIC_UINT32 stat_cmmu_req_cnt;
+	ZXIC_UINT32 cmmu_stat_fc_cnt;
+	ZXIC_UINT32 smmu1_cmmu_wr_fc_cnt;
+	ZXIC_UINT32 smmu1_cmmu_rd_fc_cnt;
+} SE_CMMU_DBG_CNT_T;
+/*cmmu req计数�? 结束*/
+
+/*se_as模块 计数�?*/
+typedef struct se_as_dbg_cnt_t {
+	ZXIC_UINT32 hash_wr_req_cnt[DPP_HASH_ID_NUM];
+	ZXIC_UINT32 smmu0_etcam_fc_cnt[DPP_ETCAM_ID_NUM];
+	ZXIC_UINT32 etcam_smmu0_req_cnt[DPP_ETCAM_ID_NUM];
+	ZXIC_UINT32 smmu0_etcam_rsp_cnt[DPP_ETCAM_ID_NUM];
+	ZXIC_UINT32 as_hla_hash_key_cnt[DPP_HASH_ID_NUM];
+	ZXIC_UINT32 as_hla_lpm_key_cnt;
+	ZXIC_UINT32 alg_as_hash_rsp_cnt[DPP_HASH_ID_NUM];
+	ZXIC_UINT32 alg_as_hash_smf_rsp_cnt[DPP_HASH_ID_NUM]; /* 命中计数 */
+	ZXIC_UINT32 alg_as_lpm_rsp_cnt;
+	ZXIC_UINT32 alg_as_lpm_smf_rsp_cnt; /* 命中计数 */
+	ZXIC_UINT32 as_pbu_key_cnt;
+	ZXIC_UINT32 pbu_se_dpi_rsp_dat_cnt;
+	ZXIC_UINT32 as_etcam_ctrl_req_cnt[DPP_ETCAM_ID_NUM];
+	ZXIC_UINT32 etcam_ctrl_as_index_cnt[DPP_ETCAM_ID_NUM]; /* 有效返回计数 */
+	ZXIC_UINT32 etcam_ctrl_as_hit_cnt[DPP_ETCAM_ID_NUM];
+	ZXIC_UINT32 as_smmu0_req_cnt;
+	ZXIC_UINT32 learn_hla_wr_cnt; /* 硬件学习 */
+	ZXIC_UINT32 as_smmu1_req_cnt;
+	ZXIC_UINT32 se_cfg_mac_dat_cnt; /* 到DMA计数 */
+	ZXIC_UINT32 alg_as_hash_fc_cnt[DPP_HASH_ID_NUM];
+	ZXIC_UINT32 alg_as_lpm_fc_cnt;
+	ZXIC_UINT32 as_alg_hash_fc_cnt[DPP_HASH_ID_NUM];
+	ZXIC_UINT32 as_alg_lpm_fc_cnt;
+	ZXIC_UINT32 as_pbu_fc_cnt;
+	ZXIC_UINT32 pbu_se_dpi_key_fc_cnt;
+	ZXIC_UINT32 as_etcam_ctrl_fc_cnt[DPP_ETCAM_ID_NUM];
+	ZXIC_UINT32 etcam_ctrl_as_fc_cnt[DPP_ETCAM_ID_NUM];
+	ZXIC_UINT32 smmu0_as_mac_age_fc_cnt;
+	ZXIC_UINT32 alg_learn_fc_cnt;
+	ZXIC_UINT32 smmu1_as_fc_cnt;
+	ZXIC_UINT32 cfg_se_mac_fc_cnt;
+} SE_AS_DBG_CNT_T;
+
+/* hash 是否响应dma流控使能*/
+typedef enum se_as_hash_dma_fc_en_e {
+	HASH_EN_DMA_FC = 0,
+	HASH_UN_EN_DMA_FC = 1,
+} SE_AS_HASH_DMA_FC_EN_E;
+/*se_as模块 计数�? 结束*/
+
+/**  alg模块调试计数*/
+typedef struct se_alg_dbg_cnt_t {
+	ZXIC_UINT32 hash_key_cnt[4];
+	ZXIC_UINT32 hash_rsp_cnt[4];
+	ZXIC_UINT32 hash_hit_cnt[4];
+	ZXIC_UINT32 hash_space_vld_cnt[4];
+	ZXIC_UINT32 hash_ddr3_req_vld_cnt[4];
+	ZXIC_UINT32 hash_ddr3_rsp_vld_cnt[4];
+
+	ZXIC_UINT32 lpm_key_cnt;
+	ZXIC_UINT32 lpm_rsp_cnt;
+	ZXIC_UINT32 lpm_hit_cnt;
+	ZXIC_UINT32 lpm_key_ddr3_req_vld_cnt; /**<  @brief LPM_SMMU1_P4口用于键�?*/
+	ZXIC_UINT32 lpm_key_ddr3_rsp_vld_cnt; /**<  @brief LPM_SMMU1_P4口用于键�?*/
+	ZXIC_UINT32 lpm_as_ddr3_req_vld_cnt; /**<  @brief LPM_SMMU1_P5口用于关联结�?*/
+	ZXIC_UINT32 lpm_as_ddr3_rsp_vld_cnt; /**<  @brief LPM_SMMU1_P5口用于关联结�?*/
+} SE_ALG_DBG_CNT_T;
+
+typedef struct se_alg_dbg_excp_cnt_t {
+	ZXIC_UINT32 schd_learn_fifo_int_cnt;
+	ZXIC_UINT32 schd_hash_fifo_int_cnt[4];
+	ZXIC_UINT32 schd_lpm_fifo_int_cnt;
+	ZXIC_UINT32 schd_learn_fifo_parity_err_cnt;
+	ZXIC_UINT32 schd_hash_fifo_parity_err_cnt[4];
+	ZXIC_UINT32 schd_lpm_fifo_parity_err_cnt;
+	ZXIC_UINT32
+	rd_init_cft_cnt; /**<  @brief 初始化过程中出现的CPU读命令冲突计�?*/
+	ZXIC_UINT32 zblk_ecc_err_cnt[32]; /**<  @brief 32个zblock的ecc错误计数*/
+	ZXIC_UINT32 zcam_hash_parity_err_cnt
+			[4]; /**<  @brief 4个hash业务口的parity错误计数*/
+	ZXIC_UINT32 zcam_lpm_err_cnt; /**<  @brief LPM业务口错误计�?*/
+
+	ZXIC_UINT32 hash_sreq_fifo_parity_err_cnt[4];
+	ZXIC_UINT32 hash_sreq_fifo_int_cnt[4];
+	ZXIC_UINT32 hash_key_fifo_int_cnt[4];
+	ZXIC_UINT32 hash_int_rsp_fifo_parity_err_cnt[4];
+	ZXIC_UINT32 hash_ext_rsp_fifo_parity_err_cnt[4];
+	ZXIC_UINT32 hash_ext_rsp_fifo_int_cnt[4];
+	ZXIC_UINT32 hash_int_rsp_fifo_int_cnt[4];
+
+	ZXIC_UINT32 lpm_ext_rsp_fifo_int_cnt;
+	ZXIC_UINT32 lpm_ext_v6_fifo_int_cnt;
+	ZXIC_UINT32 lpm_ext_v4_fifo_int_cnt;
+	ZXIC_UINT32 lpm_ext_addr_fifo_int_cnt;
+	ZXIC_UINT32 lpm_ext_v4_fifo_parity_err_cnt;
+	ZXIC_UINT32 lpm_ext_v6_fifo_parity_err_cnt;
+	ZXIC_UINT32 lpm_ext_rsp_fifo_parity_err_cnt;
+	ZXIC_UINT32 lpm_as_req_fifo_int_cnt;
+	ZXIC_UINT32 lpm_as_int_rsp_fifo_int_cnt;
+} SE_ALG_DBG_EXCP_CNT_T;
+
+#define LPM_HW_DAT_BUFF_SIZE_MAX (16 * 1024)
+typedef enum {
+	LPM_DAT_WR_TYPE_DMA = 1UL,
+	LPM_DAT_WR_TYPE_REG = 2UL,
+} LPM_DAT_WR_TYPE;
+
+typedef enum {
+	LPM_DAT_ZECLL = 1UL,
+	LPM_DAT_ZREG = 2UL,
+	LPM_DAT_DDR = 3UL,
+	LPM_DAT_DDR_RST = 4UL,
+	LPM_DAT_ERAM_RST = 5UL,
+	LPM_DAT_TYPE_MAX,
+} ROUTE_DAT_TYPE;
+
+typedef struct _lpm_hw_dat_ddr {
+	ZXIC_UINT32 dat_type; /* ROUTE_DAT_TYPE :LPM_DAT_DDR/LPM_DAT_DDR_RST */
+	ZXIC_UINT32 v4v6_flag; /* ALG_LPM_TYPE_E */
+	ZXIC_UINT32 lpm_wr_vld; /* 0-WR 1-RD */
+	ZXIC_UINT32 tbl_id; /* 对应复制通道 */
+	ZXIC_UINT32 base_addr; /* 19b */
+	ZXIC_UINT32 index; /* by rw_len */
+	ZXIC_UINT32 ecc_en;
+	ZXIC_UINT32 rw_len; /* SMMU1_DDR_WRT_MODE_E */
+	ZXIC_UINT8 data[512 / 8]; /* 左对�? */
+} ROUTE_HW_DAT_DDR;
+
+typedef struct _lpm_hw_dat_zcam {
+	ZXIC_UINT32 dat_type; /* ROUTE_DAT_TYPE :LPM_DAT_ZREG/LPM_DAT_ZECLL */
+	ZXIC_UINT32 ram_reg_flag; /* 0-reg 1-cell */
+	ZXIC_UINT32 rw_addr; /* by 512b */
+	ZXIC_UINT8 data[512 / 8]; /* 左对�? */
+} ROUTE_HW_DAT_ZCAM;
+
+typedef struct _lpm_hw_dat_eram {
+	ZXIC_UINT32 dat_type; /* ROUTE_DAT_TYPE :LPM_DAT_ERAM_RST */
+	ZXIC_UINT32 base_addr; /* by 128b */
+	ZXIC_UINT32 index; /* by rw_len*/
+	ZXIC_UINT32 rw_len; /* DPP_ERAM128_TBL_MODE_E */
+	ZXIC_UINT8 data[128 / 8]; /* 左对�? */
+} ROUTE_HW_DAT_ERAM;
+
+typedef struct ppu_stat_cfg_t {
+	ZXIC_UINT32 eram_baddr; /*片内统计基地址，单位128bit*/
+	ZXIC_UINT32 eram_depth; /*片内深度，单位128bit*/
+	ZXIC_UINT32
+	ddr_base_addr; /*片外统计基地址(PPU和OAM的片外计数共用此基地址)，单位2k*256bit*/
+	ZXIC_UINT32 ppu_addr_offset; /*PPU统计偏移地址,单位128bit*/
+} PPU_STAT_CFG_T;
+
+/***********************************************************/
+/** dpp hash的smmu1属性设�?
+     * @param   dev_id       设备�?
+     * @param   hash_id      hash引擎�?
+     * @param   tbl_id       hash表号
+     * @param   ecc_en       ecc使能
+     * @param   baddr        ddr基地址
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  �?
+     * @see
+     * @author  ls      @date  2016/04/12
+     ************************************************************/
+DPP_STATUS dpp_se_smmu1_hash_tbl_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 hash_id,
+										 ZXIC_UINT32 tbl_id, ZXIC_UINT32 ecc_en,
+										 ZXIC_UINT32 baddr);
+
+/** 获取hash算法访问DDR空间的属性，从软件获取(待优化)
+     * @param   dev_id    设备号
+     * @param   hash_id      hash引擎号
+     * @param   bulk_id      Hash引擎存储资源划分块数的ID号
+     * @param   p_ecc_en     使能ECC校验
+     * @param   p_base_addr  DDR空间基地址
+     * @return  DPP_OK-成功，DPP_ERR-失败
+     * @remark  无
+     * @see
+     * @author  tf      @date  2016/06/15
+     ************************************************************/
+DPP_STATUS dpp_se_smmu1_hash_tbl_soft_cfg_get(DPP_DEV_T *dev,
+											  ZXIC_UINT32 hash_id,
+											  ZXIC_UINT32 bulk_id,
+											  ZXIC_UINT32 *p_ecc_en,
+											  ZXIC_UINT32 *p_base_addr);
+
+DPP_STATUS dpp_se_zblk_serv_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 zblk_idx,
+									ZXIC_UINT32 serv_sel, ZXIC_UINT32 hash_id,
+									ZXIC_UINT32 enable);
+
+DPP_STATUS dpp_se_zcell_mono_cfg_set(
+		DPP_DEV_T *dev, ZXIC_UINT32 zblk_idx, ZXIC_UINT32 zcell0_tbl_id,
+		ZXIC_UINT32 zcell0_mono_flag, ZXIC_UINT32 zcell1_tbl_id,
+		ZXIC_UINT32 zcell1_mono_flag, ZXIC_UINT32 zcell2_tbl_id,
+		ZXIC_UINT32 zcell2_mono_flag, ZXIC_UINT32 zcell3_tbl_id,
+		ZXIC_UINT32 zcell3_mono_flag);
+
+DPP_STATUS dpp_se_zcell_mono_cfg_get(
+		DPP_DEV_T *dev, ZXIC_UINT32 zblk_idx, ZXIC_UINT32 *zcell0_tbl_id,
+		ZXIC_UINT32 *zcell0_mono_flag, ZXIC_UINT32 *zcell1_tbl_id,
+		ZXIC_UINT32 *zcell1_mono_flag, ZXIC_UINT32 *zcell2_tbl_id,
+		ZXIC_UINT32 *zcell2_mono_flag, ZXIC_UINT32 *zcell3_tbl_id,
+		ZXIC_UINT32 *zcell3_mono_flag);
+
+DPP_STATUS
+dpp_se_zreg_mono_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 zblk_idx,
+						 ZXIC_UINT32 zreg0_tbl_id, ZXIC_UINT32 zreg0_mono_flag,
+						 ZXIC_UINT32 zreg1_tbl_id, ZXIC_UINT32 zreg1_mono_flag,
+						 ZXIC_UINT32 zreg2_tbl_id, ZXIC_UINT32 zreg2_mono_flag,
+						 ZXIC_UINT32 zreg3_tbl_id, ZXIC_UINT32 zreg3_mono_flag);
+
+DPP_STATUS dpp_se_zreg_mono_cfg_get(
+		DPP_DEV_T *dev, ZXIC_UINT32 zblk_idx, ZXIC_UINT32 *zreg0_tbl_id,
+		ZXIC_UINT32 *zreg0_mono_flag, ZXIC_UINT32 *zreg1_tbl_id,
+		ZXIC_UINT32 *zreg1_mono_flag, ZXIC_UINT32 *zreg2_tbl_id,
+		ZXIC_UINT32 *zreg2_mono_flag, ZXIC_UINT32 *zreg3_tbl_id,
+		ZXIC_UINT32 *zreg3_mono_flag);
+DPP_STATUS dpp_se_hash_zcam_mono_flags_set(DPP_DEV_T *dev,
+										   ZXIC_UINT32 hash0_mono_flag,
+										   ZXIC_UINT32 hash1_mono_flag,
+										   ZXIC_UINT32 hash2_mono_flag,
+										   ZXIC_UINT32 hash3_mono_flag);
+
+DPP_STATUS dpp_se_hash_zcam_mono_flags_get(DPP_DEV_T *dev,
+										   ZXIC_UINT32 *hash0_mono_flag,
+										   ZXIC_UINT32 *hash1_mono_flag,
+										   ZXIC_UINT32 *hash2_mono_flag,
+										   ZXIC_UINT32 *hash3_mono_flag);
+
+DPP_STATUS dpp_se_hash_ext_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 hash_id,
+								   ZXIC_UINT32 ext_mode, ZXIC_UINT32 flag);
+DPP_STATUS dpp_se_hash_ext_cfg_get(DPP_DEV_T *dev, ZXIC_UINT32 hash_id,
+								   ZXIC_UINT32 *p_content_type,
+								   ZXIC_UINT32 *p_flag);
+DPP_STATUS dpp_se_hash_tbl_depth_set(
+		DPP_DEV_T *dev, ZXIC_UINT32 hash_id, ZXIC_UINT32 hash_tbl0_depth,
+		ZXIC_UINT32 hash_tbl1_depth, ZXIC_UINT32 hash_tbl2_depth,
+		ZXIC_UINT32 hash_tbl3_depth, ZXIC_UINT32 hash_tbl4_depth,
+		ZXIC_UINT32 hash_tbl5_depth, ZXIC_UINT32 hash_tbl6_depth,
+		ZXIC_UINT32 hash_tbl7_depth);
+DPP_STATUS dpp_se_hash_tbl_depth_get(
+		DPP_DEV_T *dev, ZXIC_UINT32 hash_id, ZXIC_UINT32 *hash_tbl0_depth,
+		ZXIC_UINT32 *hash_tbl1_depth, ZXIC_UINT32 *hash_tbl2_depth,
+		ZXIC_UINT32 *hash_tbl3_depth, ZXIC_UINT32 *hash_tbl4_depth,
+		ZXIC_UINT32 *hash_tbl5_depth, ZXIC_UINT32 *hash_tbl6_depth,
+		ZXIC_UINT32 *hash_tbl7_depth);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_stat_car.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_stat_car.h
old mode 100755
new mode 100644
index afa4ca54a8626937435712fea7817efe93542116..065c05f9d345514acd8cefa56e2ad7c223d44491
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_stat_car.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_stat_car.h
@@ -1,1047 +1,996 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_stat_car.h
-* 文件标识 : 
-* 内容摘要 : 
-* 其它说明 : 
-* 当前版本 : 
-* 作    者 : ls
-* 完成日期 : 2016/04/05
-* DEPARTMENT: ASIC_FPGA_R&D_Dept 
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* 版 本 号:  
-* 修 改 人:  
-* 修改内容:  
-***************************************************************/
-#ifndef _DPP_STAT_CAR_H_
-#define _DPP_STAT_CAR_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "dpp_dev.h"
-#include "dpp_stat_api.h"
-
-
-#define     DPP_CAR_ID_MAX                                  (1)
-
-#define     DPP_CAR_DEBUG_SWITCH                            (0)
-
-#define     DPP_CAR_A_FLOW_ID_MAX                           (0x7fff)  /*car A支持动态配置暂取32K, 后续待修改*/
-#define     DPP_CAR_B_FLOW_ID_MAX                           (0xfff)
-#define     DPP_CAR_C_FLOW_ID_MAX                           (0x3ff)
-#define     DPP_CAR_A_FLOW_ID_NUM                           (0x8000)  /*car A支持动态配置暂取32K, 后续待修改*/
-#define     DPP_CAR_B_FLOW_ID_NUM                           (0x1000)
-#define     DPP_CAR_C_FLOW_ID_NUM                           (0x400)
-
-#define     DPP_CAR_PROFILE_ID_TOTAL                        ((0x200 + 0x80 + 0x20) * DPP_CAR_ID_MAX)
-
-#define     DPP_CAR_PKT_PROFILE_ID_MAX                      (0x200)  /* 512 */
-#define     DPP_CAR_A_PROFILE_ID_MAX                        (0x1ff)
-#define     DPP_CAR_B_PROFILE_ID_MAX                        (0x7f)
-#define     DPP_CAR_C_PROFILE_ID_MAX                        (0x1f)
-
-#define     DPP_CAR_B_PROFILE_ID_RANDOM_MAX                 (0x1f)
-#define     DPP_CAR_C_PROFILE_ID_RANDOM_MAX                 (0x7)
-#define     DPP_CAR_RANDOM_OFFSET_VAL                       (7)
-
-#define     DPP_CAR_MAX_CBS_VALUE                           ((1<<27) - 1)
-#define     DPP_CAR_MAX_EBS_VALUE                           ((1<<27) - 1)
-#define     DPP_CAR_MAX_CIR_VALUE                           ((1<<23) - 1)
-#define     DPP_CAR_MAX_EIR_VALUE                           ((1<<23) - 1)
-#define     DPP_CAR_MAX_PRI_VALUE                           ((1<<5) - 1)
-
-#define     DPP_CAR_QUEUQ_CFG_TQ_LEN                        (64)
-#define     DPP_CAR_QUEUQ_CFG_TQ_HIGH_13BIT_POS             (44)
-#define     DPP_CAR_QUEUQ_CFG_TQ_HIGH_13BIT_LEN             (13)
-#define     DPP_CAR_QUEUQ_CFG_TQ_LOW_32BIT_POS              (31)
-#define     DPP_CAR_QUEUQ_CFG_TQ_LOW_32BIT_LEN              (32)
-
-#define     DPP_CAR_PROFILE_CFG_ZXIC_UINT8                        (28)
-#define     DPP_CAR_PROFILE_CFG_ZXIC_UINT32                      (DPP_CAR_PROFILE_CFG_ZXIC_UINT8>>2)
-#define     DPP_CAR_PROFILE_CFG_WIDTH                       (DPP_CAR_PROFILE_CFG_ZXIC_UINT8<<3)
-
-#define     DPP_CAR_QUEUE_CFG_ZXIC_UINT8                          (4)
-#define     DPP_CAR_QUEUE_CFG_WIDTH                         (DPP_CAR_QUEUE_CFG_ZXIC_UINT8<<3)
-
-#define     DPP_CAR_PROFILE_CFG_CAR_TYPE_POS                (1)
-#define     DPP_CAR_PROFILE_CFG_CAR_TYPE_LEN                (2)
-#define     DPP_CAR_PROFILE_CFG_PKT_SIGN_POS                (2)
-#define     DPP_CAR_PROFILE_CFG_PKT_SIGN_LEN                (1)
-#define     DPP_CAR_PROFILE_CFG_CD_POS                      (4)
-#define     DPP_CAR_PROFILE_CFG_CD_LEN                      (2)
-#define     DPP_CAR_PROFILE_CFG_CF_POS                      (5)
-#define     DPP_CAR_PROFILE_CFG_CF_LEN                      (1)
-#define     DPP_CAR_PROFILE_CFG_CM_POS                      (6)
-#define     DPP_CAR_PROFILE_CFG_CM_LEN                      (1)
-#define     DPP_CAR_PROFILE_CFG_EIR_POS                     (28)
-#define     DPP_CAR_PROFILE_CFG_EIR_LEN                     (22)
-#define     DPP_CAR_PROFILE_CFG_CIR_POS                     (50)
-#define     DPP_CAR_PROFILE_CFG_CIR_LEN                     (22)
-#define     DPP_CAR_PROFILE_CFG_EBS_POS                     (77)
-#define     DPP_CAR_PROFILE_CFG_EBS_LEN                     (27)
-#define     DPP_CAR_PROFILE_CFG_CBS_POS                     (104)
-#define     DPP_CAR_PROFILE_CFG_CBS_LEN                     (27)
-#define     DPP_CAR_PROFILE_CFG_C_PRI1_POS                  (139)
-#define     DPP_CAR_PROFILE_CFG_C_PRI1_LEN                  (5)
-#define     DPP_CAR_PROFILE_CFG_E_G_PRI1_POS                (174)
-#define     DPP_CAR_PROFILE_CFG_E_G_PRI1_LEN                (5)
-#define     DPP_CAR_PROFILE_CFG_E_Y_PRI0_POS                (214)
-#define     DPP_CAR_PROFILE_CFG_E_Y_PRI0_LEN                (5)
-
-#define     DPP_CAR_PKT_PROFILE_CFG_CAR_TYPE_POS            (1)
-#define     DPP_CAR_PKT_PROFILE_CFG_CAR_TYPE_LEN            (2)
-#define     DPP_CAR_PKT_PROFILE_CFG_PKT_SIGN_POS            (2)
-#define     DPP_CAR_PKT_PROFILE_CFG_PKT_SIGN_LEN            (1)
-#define     DPP_CAR_PKT_PROFILE_CFG_CIR_POS                 (32)
-#define     DPP_CAR_PKT_PROFILE_CFG_CIR_LEN                 (30)
-#define     DPP_CAR_PKT_PROFILE_CFG_CBS_POS                 (46)
-#define     DPP_CAR_PKT_PROFILE_CFG_CBS_LEN                 (14)
-#define     DPP_CAR_PKT_PROFILE_CFG_C_PRI0_POS              (86)
-#define     DPP_CAR_PKT_PROFILE_CFG_C_PRI0_LEN              (5)
-
-#define     DPP_CAR_QUEUE_CFG_CAR_TYPE_POS                  (1)
-#define     DPP_CAR_QUEUE_CFG_CAR_TYPE_LEN                  (2)
-#define     DPP_CAR_QUEUE_CFG_PKT_SIGN_POS                  (2)
-#define     DPP_CAR_QUEUE_CFG_PKT_SIGN_LEN                  (1)
-#define     DPP_CAR_QUEUE_CFG_QUEUE_ID_POS                  (16)
-#define     DPP_CAR_QUEUE_CFG_QUEUE_ID_LEN                  (14)
-
-/* car 算法模式 */
-typedef enum dpp_car_cd_mode_e
-{
-    CAR_CD_MODE_SRTCM   = 0,
-    CAR_CD_MODE_TRTCM,
-    CAR_CD_MODE_MEF10_1,
-    CAR_CD_MODE_INVALID
-}DPP_CAR_CD_MODE_E;
-
-/* car 读清模式*/
-typedef enum dpp_car_rd_mode_e
-{
-    CAR_READ_NOT_CLEAR = 0,
-    CAR_READ_AND_CLEAR = 1,
-}DPP_CAR_RD_MODE_E;
-
-/* car 翻转模式 */
-typedef enum dpp_car_overflow_mode_e
-{
-    CAR_KEEP_COUNT   = 0,
-    CAR_RE_COUNT     = 1,
-}DPP_CAR_OVERFLOW_MODE_E;
-
-/** QVOS翻转模式 */
-typedef enum dpp_car_qvos_mode_e
-{
-    CAR_QVOS_MODE_OVERFLOW_0 = 0,
-    CAR_QVOS_MODE_OVERFLOW_1 = 1,
-    CAR_QVOS_MODE_OVERFLOW_2 = 2,
-    CAR_QVOS_MODE_OVERFLOW_MAX
-}DPP_CAR_QVOS_MODE_E;
-
-typedef enum dpp_car_en_mode_e
-{
-    DPP_CAR_EN_MODE_BOTH_EN =  0,
-    DPP_CAR_EN_MODE_A_EN    =  1,
-    DPP_CAR_EN_MODE_A_B_EN  =  2,
-    DPP_CAR_EN_MODE_INVALID
-}DPP_CAR_EN_MODE_E;
-
-typedef enum dpp_car_cfg_operate_mode_e
-{
-    CAR_OPERATE_MODE_ADD    = 0,
-    CAR_OPERATE_MODE_DEL    = 1,
-    CAR_OPERATE_MODE_SRH    = 2,
-    CAR_OPERATE_MODE_GET    = 3,
-    CAR_OPERATE_MODE_MAX,
-}DPP_CAR_CFG_OPERATE_MODE_E;
-
-typedef struct dpp_stat_car_dbg_cnt_t
-{
-    ZXIC_UINT32 pkt_input_total_cnt;
-    ZXIC_UINT32 pkt_input_green_cnt;
-    ZXIC_UINT32 pkt_input_yellow_cnt;
-    ZXIC_UINT32 pkt_input_red_cnt;
-    ZXIC_UINT32 pkt_output_total_cnt;
-    ZXIC_UINT32 pkt_output_green_cnt;
-    ZXIC_UINT32 pkt_output_yellow_cnt;
-    ZXIC_UINT32 pkt_output_red_cnt;
-    ZXIC_UINT32 pkt_fc_dbg_cnt;
-    ZXIC_UINT32 pkt_size_cnt;
-}DPP_STAT_CAR_DBG_CNT_T;
-
-/** car 包监管模板参数设置的参数 */
-typedef struct dpp_stat_car_pkt_profile_cfg_t
-{
-    ZXIC_UINT32 profile_id;
-    ZXIC_UINT32 pkt_sign;
-    ZXIC_UINT32 cir;
-    ZXIC_UINT32 cbs;
-    ZXIC_UINT32 pri[DPP_CAR_PRI_MAX];              /**< @brief pri 0~7是有效值*/
-}DPP_STAT_CAR_PKT_PROFILE_CFG_T;
-
-/** car A包队列设置的参数 */
-typedef struct dpp_stat_car_a_pkt_queue_cfg_t
-{
-    ZXIC_UINT32 flow_id;
-    ZXIC_UINT32 drop_flag;
-    ZXIC_UINT32 plcr_en;
-    ZXIC_UINT32 profile_id;
-    ZXIC_UINT64 tq;
-    ZXIC_UINT64 dc;
-    ZXIC_UINT32 tc;
-}DPP_STAT_CAR_A_PKT_QUEUE_CFG_T;
-
-/** car B 队列设置的参数 */
-typedef struct dpp_stat_car_b_queue_cfg_t
-{
-    ZXIC_UINT32 flow_id;
-    ZXIC_UINT32 drop_flag;
-    ZXIC_UINT32 plcr_en;
-    ZXIC_UINT32 profile_id;
-    ZXIC_UINT64 tq;
-    ZXIC_UINT32 tce_flag;
-    ZXIC_UINT32 tce;
-    ZXIC_UINT32 tc;
-    ZXIC_UINT32 te;
-}DPP_STAT_CAR_B_QUEUE_CFG_T;
-
-/** car C 队列设置的参数 */
-typedef struct dpp_stat_car_c_queue_cfg_t
-{
-    ZXIC_UINT32 flow_id;
-    ZXIC_UINT32 drop_flag;
-    ZXIC_UINT32 plcr_en;
-    ZXIC_UINT32 profile_id;
-    ZXIC_UINT64 tq;
-    ZXIC_UINT32 tce_flag;
-    ZXIC_UINT32 tce;
-    ZXIC_UINT32 tc;
-    ZXIC_UINT32 te;
-}DPP_STAT_CAR_C_QUEUE_CFG_T;
-
-/* profile配置键值 */
-typedef struct dpp_car_profile_rb_key_t
-{
-    /**carprofile: 
-         car_type[2]+pkt_sign[1]+cd[2]+cf[1]+cm[1]+eir[22]+cir[22]+ebs[27]+cbs[27]+cpri[35]+e_g_pri[35]+e_y_pri[40]+0[9]*/
-    /**carpktprofile: 
-         car_type[2]+pkt_sign[1]+cir[30]+cbs[14]+c_pri[32]+0[115]*/
-    ZXIC_UINT32 profile_cfg[DPP_CAR_PROFILE_CFG_ZXIC_UINT32];
-    ZXIC_UINT32 is_static;                                    /* 是否静态，静态的profile必须由用户手动删除,待实现 */
-    ZXIC_UINT32 use_count;
-}DPP_CAR_PROFILE_RB_KEY_T;
-
-/* profile id与profile 配置节点关系键值 */
-typedef struct dpp_car_profile_id_rb_key_t
-{
-    ZXIC_UINT32 profile_id;
-    void * p_car_node;
-    ZXIC_UINT32 is_used;
-}DPP_CAR_PROFILE_ID_RB_KEY_T;
-
-/* 队列和profile id绑定关系键值 */
-typedef struct dpp_car_queue_rb_key_t
-{   /** carqueue
-          car_type[2]+pkt_sign[1]+queue_id[14]+15[0]*/
-    ZXIC_UINT8 profile_cfg[DPP_CAR_QUEUE_CFG_ZXIC_UINT8];   
-    ZXIC_UINT32 is_used;
-    ZXIC_UINT32 profile_id;
-}DPP_CAR_QUEUE_RB_KEY_T;
-
-/* 红黑树管理 */
-typedef struct dpp_car_rb_mng_t
-{
-    ZXIC_UINT32          init_en;
-    ZXIC_UINT32          total_num;
-    ZXIC_UINT32          key_size;               /** 单个红黑树节点空间的大小 */
-    ZXIC_RB_CMPFUN   p_cmpfun;
-    ZXIC_RB_CMPFUN   p_id_cmpfun;
-    ZXIC_RB_CFG *    p_plcr_rb;
-    ZXIC_RB_CFG *    p_plcr_id_rb;           /** 由id反查car的配置 的红黑树结构 */
-    ZXIC_LISTSTACK_MANGER *p_liststack_mng;  /** 索引分配 */
-}DPP_CAR_RB_MNG_T;
-
-/* profile管理 */
-typedef struct dpp_car_profile_mng_t
-{
-    ZXIC_UINT32    is_init;
-    DPP_CAR_RB_MNG_T *p_car_a_rb_profile_mng;
-    DPP_CAR_RB_MNG_T *p_car_b_rb_profile_mng;
-    DPP_CAR_RB_MNG_T *p_car_c_rb_profile_mng;
-}DPP_CAR_PROFILE_MNG_T;
-
-/* 队列管理 */
-typedef struct dpp_car_queue_mng_t
-{
-    ZXIC_UINT32    is_init;
-    DPP_CAR_RB_MNG_T *p_car_rb_queue_mng;       /** 不同的car*/
-}DPP_CAR_QUEUE_MNG_T;
-
-/* car配置信息 */
-typedef struct dpp_car_cfg_t
-{
-    ZXIC_UINT32 is_init[DPP_DEV_CHANNEL_MAX];
-    ZXIC_UINT32 car0_mono_mode[DPP_DEV_CHANNEL_MAX];
-    DPP_CAR_QUEUE_MNG_T *     p_car_queue_mng[DPP_DEV_CHANNEL_MAX];
-    DPP_CAR_PROFILE_MNG_T * p_car_profile_mng[DPP_DEV_CHANNEL_MAX];
-}DPP_CAR_CFG_T;
-
-/* car软复位需要存储的参数 */
-typedef struct dpp_car_soft_reset_item_t
-{
-    ZXIC_UINT32 flow_id;
-    ZXIC_UINT32 profile_id;
-}DPP_CAR_SOFT_RESET_ITEM_T;
-
-typedef struct dpp_car_soft_reset_data_t
-{
-    ZXIC_UINT8 car_pkt_sign[DPP_CAR_PKT_PROFILE_ID_MAX];   /*  */
-
-    ZXIC_UINT32 is_init;                                   /* car是否初始化标志位 */
-    ZXIC_UINT32 car0_pkt_num;                              /*  */
-
-    ZXIC_UINT32 cara_flow_num;             /* car0已配置过的流ID数目 */
-    ZXIC_UINT32 carb_flow_num;             /* car0已配置过的流ID数目 */
-    ZXIC_UINT32 carc_flow_num;             /* car0已配置过的流ID数目 */
-
-    DPP_CAR_SOFT_RESET_ITEM_T cara_item[DPP_CAR_A_FLOW_ID_NUM];
-    DPP_CAR_SOFT_RESET_ITEM_T carb_item[DPP_CAR_B_FLOW_ID_NUM];
-    DPP_CAR_SOFT_RESET_ITEM_T carc_item[DPP_CAR_C_FLOW_ID_NUM];
-
-}DPP_CAR_SOFT_RESET_DATA_T;
-
-typedef struct dpp_car_random_ram_t
-{
-    ZXIC_UINT32 p1;    /* 第一档丢弃概率(百分比)，取值0-100，推荐为1(百分比) */
-    ZXIC_UINT32 p2;    /* 第二档丢弃概率(百分比)，取值0-100，推荐为10(百分比) */
-    ZXIC_UINT32 p3;    /* 第三档丢弃概率(百分比)，取值0-100，推荐为50(百分比) */
-    ZXIC_UINT32 tc;    /* 桶深，即CBS或EBS */
-    ZXIC_UINT32 t1;    /* 桶深的低水线，取值0-CBS/EBS，推荐是70%的桶深 */
-    ZXIC_UINT32 t2;    /* 桶深的中水线，取值0-CBS/EBS，推荐是85%的桶深 */
-    ZXIC_UINT32 t3;    /* 桶深的高水线，取值0-CBS/EBS，推荐是95%的桶深 */
-}DPP_CAR_RANDOM_RAM_T;
-
-typedef struct dpp_car_soft_reset_queue_t
-{
-    ZXIC_UINT32 car_type;
-    ZXIC_UINT32 flow_id;
-    ZXIC_UINT32 drop_flag;
-    ZXIC_UINT32 plcr_en;
-    ZXIC_UINT32 profile_id;
-
-}DPP_CAR_SOFT_RESET_QUEUE_T;
-
-/***********************************************************/
-/** car A包限速监管模板设定
-* @param   dev_id               设备号               car号
-* @param   profile_id           监管模板号
-* @param   p_cara_profile_cfg   监管模板配置
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_cara_pkt_profile_cfg_set(DPP_DEV_T *dev,
-                                             ZXIC_UINT32 profile_id,
-                                             DPP_STAT_CAR_PKT_PROFILE_CFG_T* p_cara_profile_cfg);
-
-/***********************************************************/
-/** 获取car A 包长监管流配置
-* @param   dev_id               设备号               car号
-* @param   flow_id              流号
-* @param   p_cara_queue_cfg     car A流配置信息
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_cara_pkt_queue_cfg_get(DPP_DEV_T *dev,
-                                           ZXIC_UINT32 flow_id,
-                                           DPP_STAT_CAR_A_PKT_QUEUE_CFG_T* p_cara_queue_cfg);
-
-/***********************************************************/
-/** 配置car B 概率丢弃配置参数
-* @param   dev_id      
-* @param   profile_id   
-* @param   p_random_ram   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  YXH      @date  2019/04/01
-************************************************************/
-DPP_STATUS dpp_stat_carb_random_ram_set(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 profile_id,
-                                        DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
-                                        DPP_CAR_RANDOM_RAM_T *p_random_ram_c);
-
-/***********************************************************/
-/** 获取car B 概率丢弃配置参数
-* @param   dev_id      
-* @param   profile_id   
-* @param   p_random_ram   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  YXH      @date  2019/04/01
-************************************************************/
-DPP_STATUS dpp_stat_carb_random_ram_get(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 profile_id,
-                                        DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
-                                        DPP_CAR_RANDOM_RAM_T *p_random_ram_c);
-
-/***********************************************************/
-/** 配置car C 概率丢弃配置参数
-* @param   dev_id      
-* @param   profile_id   
-* @param   p_random_ram   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  YXH      @date  2019/04/01
-************************************************************/
-DPP_STATUS dpp_stat_carc_random_ram_set(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 profile_id,
-                                        DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
-                                        DPP_CAR_RANDOM_RAM_T *p_random_ram_c);
-
-/***********************************************************/
-/** 获取car B 概率丢弃配置参数
-* @param   dev_id      
-* @param   profile_id   
-* @param   p_random_ram   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  YXH      @date  2019/04/01
-************************************************************/
-DPP_STATUS dpp_stat_carc_random_ram_get(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 profile_id,
-                                        DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
-                                        DPP_CAR_RANDOM_RAM_T *p_random_ram_c);
-
-/***********************************************************/
-/** 获取car的包长偏移
-* @param   dev_id
-* @param   p_pkt_size_off  
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_car_pkt_size_offset_get(DPP_DEV_T *dev,
-                                            ZXIC_UINT32 *p_pkt_size_off);
-
-/***********************************************************/
-/** 配置cara的最大包长
-* @param   dev_id
-* @param   max_pkt_size  
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_cara_max_pkt_size_set(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 max_pkt_size);
-
-/***********************************************************/
-/** 获取cara的最大包长
-* @param   dev_id
-* @param   p_max_pkt_size  
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_cara_max_pkt_size_get(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 *p_max_pkt_size);
-
-/***********************************************************/
-/** 配置carb的最大包长
-* @param   dev_id
-* @param   max_pkt_size  
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_carb_max_pkt_size_set(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 max_pkt_size);
-
-/***********************************************************/
-/** 获取carb的最大包长
-* @param   dev_id
-* @param   p_max_pkt_size  
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_carb_max_pkt_size_get(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 *p_max_pkt_size);
-
-/***********************************************************/
-/** 配置carc的最大包长
-* @param   dev_id
-* @param   max_pkt_size  
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_carc_max_pkt_size_set(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 max_pkt_size);
-
-/***********************************************************/
-/** 获取carc的最大包长
-* @param   dev_id
-* @param   p_max_pkt_size  
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_carc_max_pkt_size_get(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 *p_max_pkt_size);
-
-/***********************************************************/
-/** 获取最大包长
-* @param   dev_id
-* @param   car_type
-* @param   p_max_pkt_len
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_car_max_pkt_size_get(DPP_DEV_T *dev,
-                                         ZXIC_UINT32 car_type,
-                                         ZXIC_UINT32 *p_max_pkt_len);
-
-/***********************************************************/
-/** 配置car的包长偏移
-* @param   dev_id
-* @param   pkt_size_off  
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_car_pkt_size_offset_set(DPP_DEV_T *dev,
-                                            ZXIC_UINT32 pkt_size_off);
-
-/***********************************************************/
-/** 配置最大包长
-* @param   dev_id
-* @param   car_type
-* @param   max_pkt_size
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_car_max_pkt_size_set(DPP_DEV_T *dev,
-                                         ZXIC_UINT32 car_type,
-                                         ZXIC_UINT32 max_pkt_size);
-
-/***********************************************************/
-/** car 模块流配置
-* @param   dev_id      
-* @param   car_type   
-* @param   flow_id   
-* @param   drop_flag   
-* @param   plcr_en   
-* @param   profile_id   
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/05/06
-************************************************************/
-DPP_STATUS dpp_stat_car_queue_cfg_set(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 car_type,
-                                      ZXIC_UINT32 flow_id,
-                                      ZXIC_UINT32 drop_flag,
-                                      ZXIC_UINT32 plcr_en,
-                                      ZXIC_UINT32 profile_id);
-
-/***********************************************************/
-/** car profile硬件写入
-* @param   dev_id      
-* @param   car_type   
-* @param   pkt_sign   
-* @param   profile_id   
-* @param   p_car_profile_cfg   
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/05/06
-************************************************************/
-DPP_STATUS dpp_stat_car_profile_cfg_set(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 car_type,
-                                        ZXIC_UINT32 pkt_sign,
-                                        ZXIC_UINT32 profile_id,
-                                        ZXIC_VOID* p_car_profile_cfg);
-
-/***********************************************************/
-/** car 队列映射关系配置
-* @param   dev_id      设备号      0:上行CAR限速 1:下行CAR限速
-* @param   car_type    0:A级car，1:B级car，2:C级car
-* @param   flow_id     流号
-* @param   map_flow_id 映射后的流号
-* @param   map_sp      映射后的优先级
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/09/27
-************************************************************/
-DPP_STATUS dpp_stat_car_queue_map_set(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 car_type,
-                                      ZXIC_UINT32 flow_id,
-                                      ZXIC_UINT32 map_flow_id,
-                                      ZXIC_UINT32 map_sp);
-
-/***********************************************************/
-/** 
-* @param   dev_id      
-* @param   car_type   
-* @param   pkt_sign   
-* @param   flow_id   
-* @param   p_data   
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/09/27
-************************************************************/
-DPP_STATUS dpp_stat_car_queue_get(DPP_DEV_T *dev,
-                                  ZXIC_UINT32 car_type,
-                                  ZXIC_UINT32 pkt_sign,
-                                  ZXIC_UINT32 flow_id,
-                                  ZXIC_VOID* p_data);
-/***********************************************************/
-/** car 模块流配置获取
-* @param   dev_id      
-* @param   car_type   
-* @param   flow_id   
-* @param   p_drop_flag   
-* @param   p_plcr_en   
-* @param   p_profile_id   
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/08/19
-************************************************************/
-DPP_STATUS dpp_stat_car_queue_cfg_get(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 car_type,
-                                      ZXIC_UINT32 flow_id,
-                                      ZXIC_UINT32 *p_drop_flag,
-                                      ZXIC_UINT32 *p_plcr_en,
-                                      ZXIC_UINT32 *p_profile_id);
-
-DPP_STATUS dpp_stat_car_profile_cfg_get(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 car_type,
-                                        ZXIC_UINT32 pkt_sign,
-                                        ZXIC_UINT32 profile_id,
-                                        ZXIC_VOID* p_car_profile_cfg);
-
-/***********************************************************/
-/** 
-* @param   dev_id         设备ID         car ID
-* @param   profile_id     模板ID
-* @param   p_random_ram_e E桶概率丢弃配置参数
-* @param   p_random_ram_c C桶概率丢弃配置参数
-*
-* @return  
-* @remark  无
-* @see     
-* @author  YXH      @date  2019/04/01
-************************************************************/
-DPP_STATUS dpp_stat_car_random_ram_set(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 car_type,
-                                       ZXIC_UINT32 profile_id,
-                                       DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
-                                       DPP_CAR_RANDOM_RAM_T *p_random_ram_c);
-
-/***********************************************************/
-/** 
-* @param   dev_id         设备ID         car ID
-* @param   profile_id     模板ID
-* @param   p_random_ram_e E桶概率丢弃配置参数
-* @param   p_random_ram_c C桶概率丢弃配置参数
-*
-* @return  
-* @remark  无
-* @see     
-* @author  YXH      @date  2019/04/01
-************************************************************/
-DPP_STATUS dpp_stat_car_random_ram_get(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 car_type,
-                                       ZXIC_UINT32 profile_id,
-                                       DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
-                                       DPP_CAR_RANDOM_RAM_T *p_random_ram_c);
-
-/***********************************************************/
-/** 获取 car 流号的绑定关系
-* @param   dev_id      
-* @param   car_type   
-* @param   flow_id   
-* @param   p_map_flow_id   
-* @param   p_map_sp   
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/09/27
-************************************************************/
-DPP_STATUS dpp_stat_car_queue_map_get(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 car_type,
-                                      ZXIC_UINT32 flow_id,
-                                      ZXIC_UINT32* p_map_flow_id,
-                                      ZXIC_UINT32* p_map_sp);
-
-/***********************************************************/
-/** car 模块调试计数 获取
-* @param   dev_id      
-* @param   car_type   
-* @param   p_car_dbg_cnt   
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/09/27
-************************************************************/
-DPP_STATUS dpp_stat_car_dbg_cnt_get(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 car_type,
-                                    DPP_STAT_CAR_DBG_CNT_T *p_car_dbg_cnt);
-/***********************************************************/
-/** 
-* @param   dev_id      
-* @param   car_type   
-* @param   overflow_mode   
-* @param   rd_mode   
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/09/27
-************************************************************/
-DPP_STATUS dpp_stat_car_dbg_cnt_mode_set(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 car_type,
-                                         ZXIC_UINT32 overflow_mode,
-                                         ZXIC_UINT32 rd_mode);
-/***********************************************************/
-/** 
-* @param   dev_id      
-* @param   car_type   
-* @param   p_overflow_mode   
-* @param   p_rd_mode   
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/09/27
-************************************************************/
-DPP_STATUS dpp_stat_car_dbg_cnt_mode_get(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 car_type,
-                                         ZXIC_UINT32* p_overflow_mode,
-                                         ZXIC_UINT32* p_rd_mode);
-
-/***********************************************************/
-/** car 模块初始化
-* @param   dev_id   
-* @param   p_car_cfg   
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/05/05
-************************************************************/
-DPP_STATUS dpp_stat_car_init(ZXIC_UINT32 dev_id,
-                             DPP_CAR_CFG_T *p_car_cfg);
-
-
-/***********************************************************/
-/** STAT CAR复位获取全局变量大小函数
-* @param   dev_id   
-* @param   p_size   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  yxh      @date  2018/06/26
-************************************************************/
-DPP_STATUS dpp_stat_car_glb_size_get(DPP_DEV_T *dev, ZXIC_UINT32* p_size);
-
-/***********************************************************/
-/** STAT CAR复位设置全局变量函数
-* @param   dev_id           设备号
-* @param   size             大小，字节数
-* @param   p_data_buff      全局变量数据
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  yxh      @date  2018/06/26
-************************************************************/
-DPP_STATUS dpp_stat_car_glb_mgr_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 size, ZXIC_UINT8 *p_data_buff);
-
-/***********************************************************/
-/** STAT CAR复位获取全局变量函数
-* @param   dev_id               设备号
-* @param   p_flag               释放使能，1-需要手动free，0-不需要手动free
-* @param   p_size               数据大小
-* @param   pp_data_buff         全局变量数据
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  yxh      @date  2018/06/26
-************************************************************/
-DPP_STATUS dpp_stat_car_glb_mgr_get(ZXIC_UINT32 dev_id, 
-                                    ZXIC_UINT32 *p_flag,
-                                    ZXIC_UINT32 *p_size, 
-                                    ZXIC_UINT8 **pp_data_buff);
-
-DPP_STATUS dpp_stat_queue_rb_root_prt(ZXIC_RB_CFG *p_rb_cfg);
-DPP_STATUS dpp_stat_car_profile_id_rb_root_prt(ZXIC_UINT32 dev_id, ZXIC_RB_CFG *p_rb_cfg);
-
-/***********************************************************/
-/** 配置car A的qvos溢出模式
-* @param   dev_id        设备号           car编号
-* @param   flow_id          流号
-* @param   qvos_mode        溢出模式，参见DPP_CAR_QVOS_MODE_E
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_cara_queue_qvos_set(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 flow_id,
-                                        ZXIC_UINT32 qvos_mode);
-
-/***********************************************************/
-/** 获取car A的qvos溢出模式
-* @param   dev_id        设备号        car编号
-* @param   flow_id       流号
-* @param   p_qvos_mode   qvos溢出模式
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls	   @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_cara_queue_qvos_get(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 flow_id,
-                                        ZXIC_UINT32 *p_qvos_mode);
-
-/***********************************************************/
-/** car A指定队列模式配置，仅用于调试
-* @param   dev_id           设备号           car编号
-* @param   global_en        全局队列使能，0-不使能，1-使能
-* @param   sp_en            优先级队列使能，0-不使能，1-使能
-* @param   appoint_sp       指定的优先级
-* @param   appoint_queue    指定的队列号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls       @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_cara_queue_appoint_mode_set(DPP_DEV_T *dev,
-                                                ZXIC_UINT32 global_en,
-                                                ZXIC_UINT32 sp_en,
-                                                ZXIC_UINT32 appoint_sp,
-                                                ZXIC_UINT32 appoint_queue);
-
-/***********************************************************/
-/** 获取car A指定队列模式的配置
-* @param   dev_id           设备号           car编号
-* @param   p_global_en      全局队列使能，0-不使能，1-使能
-* @param   p_sp_en          优先级队列使能，0-不使能，1-使能
-* @param   p_appoint_sp     指定的优先级
-* @param   p_appoint_queue  指定的队列号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls       @date  2016/04/07
-************************************************************/
-DPP_STATUS dpp_stat_cara_queue_appoint_mode_get(DPP_DEV_T *dev,
-                                                ZXIC_UINT32 *p_global_en,
-                                                ZXIC_UINT32 *p_sp_en,
-                                                ZXIC_UINT32 *p_appoint_sp,
-                                                ZXIC_UINT32 *p_appoint_queue);
-
-/***********************************************************/
-/** 配置car B的qvos溢出模式
-* @param   dev_id           设备号           car编号
-* @param   flow_id          流号
-* @param   qvos_mode        溢出模式，参见DPP_CAR_QVOS_MODE_E
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carb_queue_qvos_set(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 flow_id,
-                                        ZXIC_UINT32 qvos_mode);
-
-/***********************************************************/
-/** 获取car B的qvos溢出模式
-* @param   dev_id           设备号           car编号
-* @param   flow_id          流号
-* @param   p_qvos_mode      qvos溢出模式
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls       @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carb_queue_qvos_get(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 flow_id,
-                                        ZXIC_UINT32 *p_qvos_mode);
-
-/***********************************************************/
-/** car B指定队列模式配置，仅用于调试
-* @param   dev_id           设备号           car编号
-* @param   global_en        全局队列使能，0-不使能，1-使能
-* @param   sp_en            优先级队列使能，0-不使能，1-使能
-* @param   appoint_sp       指定的优先级
-* @param   appoint_queue    指定的队列号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls       @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carb_queue_appoint_mode_set(ZXIC_UINT32 dev_id,
-                                                ZXIC_UINT32 global_en,
-                                                ZXIC_UINT32 sp_en,
-                                                ZXIC_UINT32 appoint_sp,
-                                                ZXIC_UINT32 appoint_queue);
-/***********************************************************/
-/** 获取car B指定队列模式的配置
-* @param   dev_id        设备号           car编号
-* @param   p_global_en      全局队列使能，0-不使能，1-使能
-* @param   p_sp_en          优先级队列使能，0-不使能，1-使能
-* @param   p_appoint_sp     指定的优先级
-* @param   p_appoint_queue  指定的队列号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/07
-************************************************************/
-DPP_STATUS dpp_stat_carb_queue_appoint_mode_get(ZXIC_UINT32 dev_id,
-                                                ZXIC_UINT32 *p_global_en,
-                                                ZXIC_UINT32 *p_sp_en,
-                                                ZXIC_UINT32 *p_appoint_sp,
-                                                ZXIC_UINT32 *p_appoint_queue);
-
-/***********************************************************/
-/** 配置car C的qvos溢出模式
-* @param   dev_id           设备号           car编号
-* @param   flow_id          流号
-* @param   qvos_mode        溢出模式，参见DPP_CAR_QVOS_MODE_E
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carc_queue_qvos_set(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 flow_id,
-                                        ZXIC_UINT32 qvos_mode);
-
-/***********************************************************/
-/** 获取car C的qvos溢出模式
-* @param   dev_id           设备号           car编号
-* @param   flow_id          流号
-* @param   p_qvos_mode      qvos溢出模式
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carc_queue_qvos_get(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 flow_id,
-                                        ZXIC_UINT32 *p_qvos_mode);
-
-/***********************************************************/
-/** car C指定队列模式配置，仅用于调试
-* @param   dev_id           设备号           car编号
-* @param   global_en        全局队列使能，0-不使能，1-使能
-* @param   sp_en            优先级队列使能，0-不使能，1-使能
-* @param   appoint_sp       指定的优先级
-* @param   appoint_queue    指定的队列号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carc_queue_appoint_mode_set(ZXIC_UINT32 dev_id,
-                                                ZXIC_UINT32 global_en,
-                                                ZXIC_UINT32 sp_en,
-                                                ZXIC_UINT32 appoint_sp,
-                                                ZXIC_UINT32 appoint_queue);
-
-/***********************************************************/
-/** 获取car C指定队列模式的配置
-* @param   dev_id           设备号           car编号
-* @param   p_global_en      全局队列使能，0-不使能，1-使能
-* @param   p_sp_en          优先级队列使能，0-不使能，1-使能
-* @param   p_appoint_sp     指定的优先级
-* @param   p_appoint_queue  指定的队列号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/07
-************************************************************/
-DPP_STATUS dpp_stat_carc_queue_appoint_mode_get(ZXIC_UINT32 dev_id,
-                                                ZXIC_UINT32 *p_global_en,
-                                                ZXIC_UINT32 *p_sp_en,
-                                                ZXIC_UINT32 *p_appoint_sp,
-                                                ZXIC_UINT32 *p_appoint_queue);
-
-/***********************************************************/
-/**
-* @param   dev_id
-* @param   p_mode
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/09/28
-************************************************************/
-DPP_STATUS dpp_stat_car_en_mode_get(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 *p_mode);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-
-
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_stat_car.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : ls
+* 完成日期 : 2016/04/05
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#ifndef _DPP_STAT_CAR_H_
+#define _DPP_STAT_CAR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dpp_dev.h"
+#include "dpp_stat_api.h"
+
+#define DPP_CAR_ID_MAX (1)
+
+#define DPP_CAR_DEBUG_SWITCH (0)
+
+#define DPP_CAR_A_FLOW_ID_MAX (0x7fff) /*car A支持动态配置暂取32K, 后续待修改*/
+#define DPP_CAR_B_FLOW_ID_MAX (0xfff)
+#define DPP_CAR_C_FLOW_ID_MAX (0x3ff)
+#define DPP_CAR_A_FLOW_ID_NUM (0x8000) /*car A支持动态配置暂取32K, 后续待修改*/
+#define DPP_CAR_B_FLOW_ID_NUM (0x1000)
+#define DPP_CAR_C_FLOW_ID_NUM (0x400)
+
+#define DPP_CAR_PROFILE_ID_TOTAL ((0x200 + 0x80 + 0x20) * DPP_CAR_ID_MAX)
+
+#define DPP_CAR_PKT_PROFILE_ID_MAX (0x200) /* 512 */
+#define DPP_CAR_A_PROFILE_ID_MAX (0x1ff)
+#define DPP_CAR_B_PROFILE_ID_MAX (0x7f)
+#define DPP_CAR_C_PROFILE_ID_MAX (0x1f)
+
+#define DPP_CAR_B_PROFILE_ID_RANDOM_MAX (0x1f)
+#define DPP_CAR_C_PROFILE_ID_RANDOM_MAX (0x7)
+#define DPP_CAR_RANDOM_OFFSET_VAL (7)
+
+#define DPP_CAR_MAX_CBS_VALUE ((1 << 27) - 1)
+#define DPP_CAR_MAX_EBS_VALUE ((1 << 27) - 1)
+#define DPP_CAR_MAX_CIR_VALUE ((1 << 23) - 1)
+#define DPP_CAR_MAX_EIR_VALUE ((1 << 23) - 1)
+#define DPP_CAR_MAX_PRI_VALUE ((1 << 5) - 1)
+
+#define DPP_CAR_QUEUQ_CFG_TQ_LEN (64)
+#define DPP_CAR_QUEUQ_CFG_TQ_HIGH_13BIT_POS (44)
+#define DPP_CAR_QUEUQ_CFG_TQ_HIGH_13BIT_LEN (13)
+#define DPP_CAR_QUEUQ_CFG_TQ_LOW_32BIT_POS (31)
+#define DPP_CAR_QUEUQ_CFG_TQ_LOW_32BIT_LEN (32)
+
+#define DPP_CAR_PROFILE_CFG_ZXIC_UINT8 (28)
+#define DPP_CAR_PROFILE_CFG_ZXIC_UINT32 (DPP_CAR_PROFILE_CFG_ZXIC_UINT8 >> 2)
+#define DPP_CAR_PROFILE_CFG_WIDTH (DPP_CAR_PROFILE_CFG_ZXIC_UINT8 << 3)
+
+#define DPP_CAR_QUEUE_CFG_ZXIC_UINT8 (4)
+#define DPP_CAR_QUEUE_CFG_WIDTH (DPP_CAR_QUEUE_CFG_ZXIC_UINT8 << 3)
+
+#define DPP_CAR_PROFILE_CFG_CAR_TYPE_POS (1)
+#define DPP_CAR_PROFILE_CFG_CAR_TYPE_LEN (2)
+#define DPP_CAR_PROFILE_CFG_PKT_SIGN_POS (2)
+#define DPP_CAR_PROFILE_CFG_PKT_SIGN_LEN (1)
+#define DPP_CAR_PROFILE_CFG_CD_POS (4)
+#define DPP_CAR_PROFILE_CFG_CD_LEN (2)
+#define DPP_CAR_PROFILE_CFG_CF_POS (5)
+#define DPP_CAR_PROFILE_CFG_CF_LEN (1)
+#define DPP_CAR_PROFILE_CFG_CM_POS (6)
+#define DPP_CAR_PROFILE_CFG_CM_LEN (1)
+#define DPP_CAR_PROFILE_CFG_EIR_POS (28)
+#define DPP_CAR_PROFILE_CFG_EIR_LEN (22)
+#define DPP_CAR_PROFILE_CFG_CIR_POS (50)
+#define DPP_CAR_PROFILE_CFG_CIR_LEN (22)
+#define DPP_CAR_PROFILE_CFG_EBS_POS (77)
+#define DPP_CAR_PROFILE_CFG_EBS_LEN (27)
+#define DPP_CAR_PROFILE_CFG_CBS_POS (104)
+#define DPP_CAR_PROFILE_CFG_CBS_LEN (27)
+#define DPP_CAR_PROFILE_CFG_C_PRI1_POS (139)
+#define DPP_CAR_PROFILE_CFG_C_PRI1_LEN (5)
+#define DPP_CAR_PROFILE_CFG_E_G_PRI1_POS (174)
+#define DPP_CAR_PROFILE_CFG_E_G_PRI1_LEN (5)
+#define DPP_CAR_PROFILE_CFG_E_Y_PRI0_POS (214)
+#define DPP_CAR_PROFILE_CFG_E_Y_PRI0_LEN (5)
+
+#define DPP_CAR_PKT_PROFILE_CFG_CAR_TYPE_POS (1)
+#define DPP_CAR_PKT_PROFILE_CFG_CAR_TYPE_LEN (2)
+#define DPP_CAR_PKT_PROFILE_CFG_PKT_SIGN_POS (2)
+#define DPP_CAR_PKT_PROFILE_CFG_PKT_SIGN_LEN (1)
+#define DPP_CAR_PKT_PROFILE_CFG_CIR_POS (32)
+#define DPP_CAR_PKT_PROFILE_CFG_CIR_LEN (30)
+#define DPP_CAR_PKT_PROFILE_CFG_CBS_POS (46)
+#define DPP_CAR_PKT_PROFILE_CFG_CBS_LEN (14)
+#define DPP_CAR_PKT_PROFILE_CFG_C_PRI0_POS (86)
+#define DPP_CAR_PKT_PROFILE_CFG_C_PRI0_LEN (5)
+
+#define DPP_CAR_QUEUE_CFG_CAR_TYPE_POS (1)
+#define DPP_CAR_QUEUE_CFG_CAR_TYPE_LEN (2)
+#define DPP_CAR_QUEUE_CFG_PKT_SIGN_POS (2)
+#define DPP_CAR_QUEUE_CFG_PKT_SIGN_LEN (1)
+#define DPP_CAR_QUEUE_CFG_QUEUE_ID_POS (16)
+#define DPP_CAR_QUEUE_CFG_QUEUE_ID_LEN (14)
+
+/* car 算法模式 */
+typedef enum dpp_car_cd_mode_e {
+	CAR_CD_MODE_SRTCM = 0,
+	CAR_CD_MODE_TRTCM,
+	CAR_CD_MODE_MEF10_1,
+	CAR_CD_MODE_INVALID
+} DPP_CAR_CD_MODE_E;
+
+/* car 读清模式*/
+typedef enum dpp_car_rd_mode_e {
+	CAR_READ_NOT_CLEAR = 0,
+	CAR_READ_AND_CLEAR = 1,
+} DPP_CAR_RD_MODE_E;
+
+/* car 翻转模式 */
+typedef enum dpp_car_overflow_mode_e {
+	CAR_KEEP_COUNT = 0,
+	CAR_RE_COUNT = 1,
+} DPP_CAR_OVERFLOW_MODE_E;
+
+/** QVOS翻转模式 */
+typedef enum dpp_car_qvos_mode_e {
+	CAR_QVOS_MODE_OVERFLOW_0 = 0,
+	CAR_QVOS_MODE_OVERFLOW_1 = 1,
+	CAR_QVOS_MODE_OVERFLOW_2 = 2,
+	CAR_QVOS_MODE_OVERFLOW_MAX
+} DPP_CAR_QVOS_MODE_E;
+
+typedef enum dpp_car_en_mode_e {
+	DPP_CAR_EN_MODE_BOTH_EN = 0,
+	DPP_CAR_EN_MODE_A_EN = 1,
+	DPP_CAR_EN_MODE_A_B_EN = 2,
+	DPP_CAR_EN_MODE_INVALID
+} DPP_CAR_EN_MODE_E;
+
+typedef enum dpp_car_cfg_operate_mode_e {
+	CAR_OPERATE_MODE_ADD = 0,
+	CAR_OPERATE_MODE_DEL = 1,
+	CAR_OPERATE_MODE_SRH = 2,
+	CAR_OPERATE_MODE_GET = 3,
+	CAR_OPERATE_MODE_MAX,
+} DPP_CAR_CFG_OPERATE_MODE_E;
+
+typedef struct dpp_stat_car_dbg_cnt_t {
+	ZXIC_UINT32 pkt_input_total_cnt;
+	ZXIC_UINT32 pkt_input_green_cnt;
+	ZXIC_UINT32 pkt_input_yellow_cnt;
+	ZXIC_UINT32 pkt_input_red_cnt;
+	ZXIC_UINT32 pkt_output_total_cnt;
+	ZXIC_UINT32 pkt_output_green_cnt;
+	ZXIC_UINT32 pkt_output_yellow_cnt;
+	ZXIC_UINT32 pkt_output_red_cnt;
+	ZXIC_UINT32 pkt_fc_dbg_cnt;
+	ZXIC_UINT32 pkt_size_cnt;
+} DPP_STAT_CAR_DBG_CNT_T;
+
+/** car 包监管模板参数设置的参数 */
+typedef struct dpp_stat_car_pkt_profile_cfg_t {
+	ZXIC_UINT32 profile_id;
+	ZXIC_UINT32 pkt_sign;
+	ZXIC_UINT32 cir;
+	ZXIC_UINT32 cbs;
+	ZXIC_UINT32 pri[DPP_CAR_PRI_MAX]; /**< @brief pri 0~7是有效值*/
+} DPP_STAT_CAR_PKT_PROFILE_CFG_T;
+
+/** car A包队列设置的参数 */
+typedef struct dpp_stat_car_a_pkt_queue_cfg_t {
+	ZXIC_UINT32 flow_id;
+	ZXIC_UINT32 drop_flag;
+	ZXIC_UINT32 plcr_en;
+	ZXIC_UINT32 profile_id;
+	ZXIC_UINT64 tq;
+	ZXIC_UINT64 dc;
+	ZXIC_UINT32 tc;
+} DPP_STAT_CAR_A_PKT_QUEUE_CFG_T;
+
+/** car B 队列设置的参数 */
+typedef struct dpp_stat_car_b_queue_cfg_t {
+	ZXIC_UINT32 flow_id;
+	ZXIC_UINT32 drop_flag;
+	ZXIC_UINT32 plcr_en;
+	ZXIC_UINT32 profile_id;
+	ZXIC_UINT64 tq;
+	ZXIC_UINT32 tce_flag;
+	ZXIC_UINT32 tce;
+	ZXIC_UINT32 tc;
+	ZXIC_UINT32 te;
+} DPP_STAT_CAR_B_QUEUE_CFG_T;
+
+/** car C 队列设置的参数 */
+typedef struct dpp_stat_car_c_queue_cfg_t {
+	ZXIC_UINT32 flow_id;
+	ZXIC_UINT32 drop_flag;
+	ZXIC_UINT32 plcr_en;
+	ZXIC_UINT32 profile_id;
+	ZXIC_UINT64 tq;
+	ZXIC_UINT32 tce_flag;
+	ZXIC_UINT32 tce;
+	ZXIC_UINT32 tc;
+	ZXIC_UINT32 te;
+} DPP_STAT_CAR_C_QUEUE_CFG_T;
+
+/* profile配置键值 */
+typedef struct dpp_car_profile_rb_key_t {
+	/**carprofile:
+     car_type[2]+pkt_sign[1]+cd[2]+cf[1]+cm[1]+eir[22]+cir[22]+ebs[27]+cbs[27]+cpri[35]+e_g_pri[35]+e_y_pri[40]+0[9]*/
+	/**carpktprofile:
+     car_type[2]+pkt_sign[1]+cir[30]+cbs[14]+c_pri[32]+0[115]*/
+	ZXIC_UINT32 profile_cfg[DPP_CAR_PROFILE_CFG_ZXIC_UINT32];
+	ZXIC_UINT32 is_static; /* 是否静态，静态的profile必须由用户手动删除,待实现 */
+	ZXIC_UINT32 use_count;
+} DPP_CAR_PROFILE_RB_KEY_T;
+
+/* profile id与profile 配置节点关系键值 */
+typedef struct dpp_car_profile_id_rb_key_t {
+	ZXIC_UINT32 profile_id;
+	void *p_car_node;
+	ZXIC_UINT32 is_used;
+} DPP_CAR_PROFILE_ID_RB_KEY_T;
+
+/* 队列和profile id绑定关系键值 */
+typedef struct dpp_car_queue_rb_key_t { /** carqueue
+car_type[2]+pkt_sign[1]+queue_id[14]+15[0]*/
+	ZXIC_UINT8 profile_cfg[DPP_CAR_QUEUE_CFG_ZXIC_UINT8];
+	ZXIC_UINT32 is_used;
+	ZXIC_UINT32 profile_id;
+} DPP_CAR_QUEUE_RB_KEY_T;
+
+/* 红黑树管理 */
+typedef struct dpp_car_rb_mng_t {
+	ZXIC_UINT32 init_en;
+	ZXIC_UINT32 total_num;
+	ZXIC_UINT32 key_size; /** 单个红黑树节点空间的大小 */
+	ZXIC_RB_CMPFUN p_cmpfun;
+	ZXIC_RB_CMPFUN p_id_cmpfun;
+	ZXIC_RB_CFG *p_plcr_rb;
+	ZXIC_RB_CFG *p_plcr_id_rb; /** 由id反查car的配置 的红黑树结构 */
+	ZXIC_LISTSTACK_MANGER *p_liststack_mng; /** 索引分配 */
+} DPP_CAR_RB_MNG_T;
+
+/* profile管理 */
+typedef struct dpp_car_profile_mng_t {
+	ZXIC_UINT32 is_init;
+	DPP_CAR_RB_MNG_T *p_car_a_rb_profile_mng;
+	DPP_CAR_RB_MNG_T *p_car_b_rb_profile_mng;
+	DPP_CAR_RB_MNG_T *p_car_c_rb_profile_mng;
+} DPP_CAR_PROFILE_MNG_T;
+
+/* 队列管理 */
+typedef struct dpp_car_queue_mng_t {
+	ZXIC_UINT32 is_init;
+	DPP_CAR_RB_MNG_T *p_car_rb_queue_mng; /** 不同的car*/
+} DPP_CAR_QUEUE_MNG_T;
+
+/* car配置信息 */
+typedef struct dpp_car_cfg_t {
+	ZXIC_UINT32 is_init[DPP_DEV_CHANNEL_MAX];
+	ZXIC_UINT32 car0_mono_mode[DPP_DEV_CHANNEL_MAX];
+	DPP_CAR_QUEUE_MNG_T * p_car_queue_mng[DPP_DEV_CHANNEL_MAX];
+	DPP_CAR_PROFILE_MNG_T * p_car_profile_mng[DPP_DEV_CHANNEL_MAX];
+} DPP_CAR_CFG_T;
+
+/* car软复位需要存储的参数 */
+typedef struct dpp_car_soft_reset_item_t {
+	ZXIC_UINT32 flow_id;
+	ZXIC_UINT32 profile_id;
+} DPP_CAR_SOFT_RESET_ITEM_T;
+
+typedef struct dpp_car_soft_reset_data_t {
+	ZXIC_UINT8 car_pkt_sign[DPP_CAR_PKT_PROFILE_ID_MAX]; /*  */
+
+	ZXIC_UINT32 is_init; /* car是否初始化标志位 */
+	ZXIC_UINT32 car0_pkt_num; /*  */
+
+	ZXIC_UINT32 cara_flow_num; /* car0已配置过的流ID数目 */
+	ZXIC_UINT32 carb_flow_num; /* car0已配置过的流ID数目 */
+	ZXIC_UINT32 carc_flow_num; /* car0已配置过的流ID数目 */
+
+	DPP_CAR_SOFT_RESET_ITEM_T cara_item[DPP_CAR_A_FLOW_ID_NUM];
+	DPP_CAR_SOFT_RESET_ITEM_T carb_item[DPP_CAR_B_FLOW_ID_NUM];
+	DPP_CAR_SOFT_RESET_ITEM_T carc_item[DPP_CAR_C_FLOW_ID_NUM];
+
+} DPP_CAR_SOFT_RESET_DATA_T;
+
+typedef struct dpp_car_random_ram_t {
+	ZXIC_UINT32 p1; /* 第一档丢弃概率(百分比)，取值0-100，推荐为1(百分比) */
+	ZXIC_UINT32 p2; /* 第二档丢弃概率(百分比)，取值0-100，推荐为10(百分比) */
+	ZXIC_UINT32 p3; /* 第三档丢弃概率(百分比)，取值0-100，推荐为50(百分比) */
+	ZXIC_UINT32 tc; /* 桶深，即CBS或EBS */
+	ZXIC_UINT32 t1; /* 桶深的低水线，取值0-CBS/EBS，推荐是70%的桶深 */
+	ZXIC_UINT32 t2; /* 桶深的中水线，取值0-CBS/EBS，推荐是85%的桶深 */
+	ZXIC_UINT32 t3; /* 桶深的高水线，取值0-CBS/EBS，推荐是95%的桶深 */
+} DPP_CAR_RANDOM_RAM_T;
+
+typedef struct dpp_car_soft_reset_queue_t {
+	ZXIC_UINT32 car_type;
+	ZXIC_UINT32 flow_id;
+	ZXIC_UINT32 drop_flag;
+	ZXIC_UINT32 plcr_en;
+	ZXIC_UINT32 profile_id;
+
+} DPP_CAR_SOFT_RESET_QUEUE_T;
+
+/***********************************************************/
+/** car A包限速监管模板设定
+     * @param   dev_id               设备号               car号
+     * @param   profile_id           监管模板号
+     * @param   p_cara_profile_cfg   监管模板配置
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/04/05
+     ************************************************************/
+DPP_STATUS dpp_stat_cara_pkt_profile_cfg_set(
+		DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+		DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_cara_profile_cfg);
+
+/***********************************************************/
+/** 获取car A 包长监管流配置
+     * @param   dev_id               设备号               car号
+     * @param   flow_id              流号
+     * @param   p_cara_queue_cfg     car A流配置信息
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/04/05
+     ************************************************************/
+DPP_STATUS dpp_stat_cara_pkt_queue_cfg_get(
+		DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+		DPP_STAT_CAR_A_PKT_QUEUE_CFG_T *p_cara_queue_cfg);
+
+/***********************************************************/
+/** 配置car B 概率丢弃配置参数
+     * @param   dev_id
+     * @param   profile_id
+     * @param   p_random_ram
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  YXH      @date  2019/04/01
+     ************************************************************/
+DPP_STATUS dpp_stat_carb_random_ram_set(DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+										DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
+										DPP_CAR_RANDOM_RAM_T *p_random_ram_c);
+
+/***********************************************************/
+/** 获取car B 概率丢弃配置参数
+     * @param   dev_id
+     * @param   profile_id
+     * @param   p_random_ram
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  YXH      @date  2019/04/01
+     ************************************************************/
+DPP_STATUS dpp_stat_carb_random_ram_get(DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+										DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
+										DPP_CAR_RANDOM_RAM_T *p_random_ram_c);
+
+/***********************************************************/
+/** 配置car C 概率丢弃配置参数
+     * @param   dev_id
+     * @param   profile_id
+     * @param   p_random_ram
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  YXH      @date  2019/04/01
+     ************************************************************/
+DPP_STATUS dpp_stat_carc_random_ram_set(DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+										DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
+										DPP_CAR_RANDOM_RAM_T *p_random_ram_c);
+
+/***********************************************************/
+/** 获取car B 概率丢弃配置参数
+     * @param   dev_id
+     * @param   profile_id
+     * @param   p_random_ram
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  YXH      @date  2019/04/01
+     ************************************************************/
+DPP_STATUS dpp_stat_carc_random_ram_get(DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+										DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
+										DPP_CAR_RANDOM_RAM_T *p_random_ram_c);
+
+/***********************************************************/
+/** 获取car的包长偏移
+     * @param   dev_id
+     * @param   p_pkt_size_off
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  wll      @date  2019/06/06
+     ************************************************************/
+DPP_STATUS dpp_stat_car_pkt_size_offset_get(DPP_DEV_T *dev,
+											ZXIC_UINT32 *p_pkt_size_off);
+
+/***********************************************************/
+/** 配置cara的最大包长
+     * @param   dev_id
+     * @param   max_pkt_size
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  wll      @date  2019/06/06
+     ************************************************************/
+DPP_STATUS dpp_stat_cara_max_pkt_size_set(DPP_DEV_T *dev,
+										  ZXIC_UINT32 max_pkt_size);
+
+/***********************************************************/
+/** 获取cara的最大包长
+     * @param   dev_id
+     * @param   p_max_pkt_size
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  wll      @date  2019/06/06
+     ************************************************************/
+DPP_STATUS dpp_stat_cara_max_pkt_size_get(DPP_DEV_T *dev,
+										  ZXIC_UINT32 *p_max_pkt_size);
+
+/***********************************************************/
+/** 配置carb的最大包长
+     * @param   dev_id
+     * @param   max_pkt_size
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  wll      @date  2019/06/06
+     ************************************************************/
+DPP_STATUS dpp_stat_carb_max_pkt_size_set(DPP_DEV_T *dev,
+										  ZXIC_UINT32 max_pkt_size);
+
+/***********************************************************/
+/** 获取carb的最大包长
+     * @param   dev_id
+     * @param   p_max_pkt_size
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  wll      @date  2019/06/06
+     ************************************************************/
+DPP_STATUS dpp_stat_carb_max_pkt_size_get(DPP_DEV_T *dev,
+										  ZXIC_UINT32 *p_max_pkt_size);
+
+/***********************************************************/
+/** 配置carc的最大包长
+     * @param   dev_id
+     * @param   max_pkt_size
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  wll      @date  2019/06/06
+     ************************************************************/
+DPP_STATUS dpp_stat_carc_max_pkt_size_set(DPP_DEV_T *dev,
+										  ZXIC_UINT32 max_pkt_size);
+
+/***********************************************************/
+/** 获取carc的最大包长
+     * @param   dev_id
+     * @param   p_max_pkt_size
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  wll      @date  2019/06/06
+     ************************************************************/
+DPP_STATUS dpp_stat_carc_max_pkt_size_get(DPP_DEV_T *dev,
+										  ZXIC_UINT32 *p_max_pkt_size);
+
+/***********************************************************/
+/** 获取最大包长
+     * @param   dev_id
+     * @param   car_type
+     * @param   p_max_pkt_len
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  wll      @date  2019/06/06
+     ************************************************************/
+DPP_STATUS dpp_stat_car_max_pkt_size_get(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+										 ZXIC_UINT32 *p_max_pkt_len);
+
+/***********************************************************/
+/** 配置car的包长偏移
+     * @param   dev_id
+     * @param   pkt_size_off
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  wll      @date  2019/06/06
+     ************************************************************/
+DPP_STATUS dpp_stat_car_pkt_size_offset_set(DPP_DEV_T *dev,
+											ZXIC_UINT32 pkt_size_off);
+
+/***********************************************************/
+/** 配置最大包长
+     * @param   dev_id
+     * @param   car_type
+     * @param   max_pkt_size
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  wll      @date  2019/06/06
+     ************************************************************/
+DPP_STATUS dpp_stat_car_max_pkt_size_set(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+										 ZXIC_UINT32 max_pkt_size);
+
+/***********************************************************/
+/** car 模块流配置
+     * @param   dev_id
+     * @param   car_type
+     * @param   flow_id
+     * @param   drop_flag
+     * @param   plcr_en
+     * @param   profile_id
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/05/06
+     ************************************************************/
+DPP_STATUS dpp_stat_car_queue_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+									  ZXIC_UINT32 flow_id,
+									  ZXIC_UINT32 drop_flag,
+									  ZXIC_UINT32 plcr_en,
+									  ZXIC_UINT32 profile_id);
+
+/***********************************************************/
+/** car profile硬件写入
+     * @param   dev_id
+     * @param   car_type
+     * @param   pkt_sign
+     * @param   profile_id
+     * @param   p_car_profile_cfg
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/05/06
+     ************************************************************/
+DPP_STATUS dpp_stat_car_profile_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+										ZXIC_UINT32 pkt_sign,
+										ZXIC_UINT32 profile_id,
+										ZXIC_VOID *p_car_profile_cfg);
+
+/***********************************************************/
+/** car 队列映射关系配置
+     * @param   dev_id      设备号      0:上行CAR限速 1:下行CAR限速
+     * @param   car_type    0:A级car，1:B级car，2:C级car
+     * @param   flow_id     流号
+     * @param   map_flow_id 映射后的流号
+     * @param   map_sp      映射后的优先级
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/09/27
+     ************************************************************/
+DPP_STATUS dpp_stat_car_queue_map_set(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+									  ZXIC_UINT32 flow_id,
+									  ZXIC_UINT32 map_flow_id,
+									  ZXIC_UINT32 map_sp);
+
+/***********************************************************/
+/**
+     * @param   dev_id
+     * @param   car_type
+     * @param   pkt_sign
+     * @param   flow_id
+     * @param   p_data
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/09/27
+     ************************************************************/
+DPP_STATUS dpp_stat_car_queue_get(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+								  ZXIC_UINT32 pkt_sign, ZXIC_UINT32 flow_id,
+								  ZXIC_VOID *p_data);
+/***********************************************************/
+/** car 模块流配置获取
+     * @param   dev_id
+     * @param   car_type
+     * @param   flow_id
+     * @param   p_drop_flag
+     * @param   p_plcr_en
+     * @param   p_profile_id
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/08/19
+     ************************************************************/
+DPP_STATUS dpp_stat_car_queue_cfg_get(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+									  ZXIC_UINT32 flow_id,
+									  ZXIC_UINT32 *p_drop_flag,
+									  ZXIC_UINT32 *p_plcr_en,
+									  ZXIC_UINT32 *p_profile_id);
+
+DPP_STATUS dpp_stat_car_profile_cfg_get(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+										ZXIC_UINT32 pkt_sign,
+										ZXIC_UINT32 profile_id,
+										ZXIC_VOID *p_car_profile_cfg);
+
+/***********************************************************/
+/**
+     * @param   dev_id         设备ID         car ID
+     * @param   profile_id     模板ID
+     * @param   p_random_ram_e E桶概率丢弃配置参数
+     * @param   p_random_ram_c C桶概率丢弃配置参数
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  YXH      @date  2019/04/01
+     ************************************************************/
+DPP_STATUS dpp_stat_car_random_ram_set(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+									   ZXIC_UINT32 profile_id,
+									   DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
+									   DPP_CAR_RANDOM_RAM_T *p_random_ram_c);
+
+/***********************************************************/
+/**
+     * @param   dev_id         设备ID         car ID
+     * @param   profile_id     模板ID
+     * @param   p_random_ram_e E桶概率丢弃配置参数
+     * @param   p_random_ram_c C桶概率丢弃配置参数
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  YXH      @date  2019/04/01
+     ************************************************************/
+DPP_STATUS dpp_stat_car_random_ram_get(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+									   ZXIC_UINT32 profile_id,
+									   DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
+									   DPP_CAR_RANDOM_RAM_T *p_random_ram_c);
+
+/***********************************************************/
+/** 获取 car 流号的绑定关系
+     * @param   dev_id
+     * @param   car_type
+     * @param   flow_id
+     * @param   p_map_flow_id
+     * @param   p_map_sp
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/09/27
+     ************************************************************/
+DPP_STATUS dpp_stat_car_queue_map_get(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+									  ZXIC_UINT32 flow_id,
+									  ZXIC_UINT32 *p_map_flow_id,
+									  ZXIC_UINT32 *p_map_sp);
+
+/***********************************************************/
+/** car 模块调试计数 获取
+     * @param   dev_id
+     * @param   car_type
+     * @param   p_car_dbg_cnt
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/09/27
+     ************************************************************/
+DPP_STATUS dpp_stat_car_dbg_cnt_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 car_type,
+									DPP_STAT_CAR_DBG_CNT_T *p_car_dbg_cnt);
+/***********************************************************/
+/**
+     * @param   dev_id
+     * @param   car_type
+     * @param   overflow_mode
+     * @param   rd_mode
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/09/27
+     ************************************************************/
+DPP_STATUS dpp_stat_car_dbg_cnt_mode_set(ZXIC_UINT32 dev_id,
+										 ZXIC_UINT32 car_type,
+										 ZXIC_UINT32 overflow_mode,
+										 ZXIC_UINT32 rd_mode);
+/***********************************************************/
+/**
+     * @param   dev_id
+     * @param   car_type
+     * @param   p_overflow_mode
+     * @param   p_rd_mode
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/09/27
+     ************************************************************/
+DPP_STATUS dpp_stat_car_dbg_cnt_mode_get(ZXIC_UINT32 dev_id,
+										 ZXIC_UINT32 car_type,
+										 ZXIC_UINT32 *p_overflow_mode,
+										 ZXIC_UINT32 *p_rd_mode);
+
+/***********************************************************/
+/** car 模块初始化
+     * @param   dev_id
+     * @param   p_car_cfg
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/05/05
+     ************************************************************/
+DPP_STATUS dpp_stat_car_init(ZXIC_UINT32 dev_id, DPP_CAR_CFG_T *p_car_cfg);
+
+/***********************************************************/
+/** STAT CAR复位获取全局变量大小函数
+     * @param   dev_id
+     * @param   p_size
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  yxh      @date  2018/06/26
+     ************************************************************/
+DPP_STATUS dpp_stat_car_glb_size_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_size);
+
+/***********************************************************/
+/** STAT CAR复位设置全局变量函数
+     * @param   dev_id           设备号
+     * @param   size             大小，字节数
+     * @param   p_data_buff      全局变量数据
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  yxh      @date  2018/06/26
+     ************************************************************/
+DPP_STATUS dpp_stat_car_glb_mgr_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 size,
+									ZXIC_UINT8 *p_data_buff);
+
+/***********************************************************/
+/** STAT CAR复位获取全局变量函数
+     * @param   dev_id               设备号
+     * @param   p_flag               释放使能，1-需要手动free，0-不需要手动free
+     * @param   p_size               数据大小
+     * @param   pp_data_buff         全局变量数据
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  yxh      @date  2018/06/26
+     ************************************************************/
+DPP_STATUS dpp_stat_car_glb_mgr_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_flag,
+									ZXIC_UINT32 *p_size,
+									ZXIC_UINT8 **pp_data_buff);
+
+DPP_STATUS dpp_stat_queue_rb_root_prt(ZXIC_RB_CFG *p_rb_cfg);
+DPP_STATUS dpp_stat_car_profile_id_rb_root_prt(ZXIC_UINT32 dev_id,
+											   ZXIC_RB_CFG *p_rb_cfg);
+
+/***********************************************************/
+/** 配置car A的qvos溢出模式
+     * @param   dev_id        设备号           car编号
+     * @param   flow_id          流号
+     * @param   qvos_mode        溢出模式，参见DPP_CAR_QVOS_MODE_E
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/04/06
+     ************************************************************/
+DPP_STATUS dpp_stat_cara_queue_qvos_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+										ZXIC_UINT32 qvos_mode);
+
+/***********************************************************/
+/** 获取car A的qvos溢出模式
+     * @param   dev_id        设备号        car编号
+     * @param   flow_id       流号
+     * @param   p_qvos_mode   qvos溢出模式
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls	   @date  2016/04/06
+     ************************************************************/
+DPP_STATUS dpp_stat_cara_queue_qvos_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+										ZXIC_UINT32 *p_qvos_mode);
+
+/***********************************************************/
+/** car A指定队列模式配置，仅用于调试
+     * @param   dev_id           设备号           car编号
+     * @param   global_en        全局队列使能，0-不使能，1-使能
+     * @param   sp_en            优先级队列使能，0-不使能，1-使能
+     * @param   appoint_sp       指定的优先级
+     * @param   appoint_queue    指定的队列号
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls       @date  2016/04/06
+     ************************************************************/
+DPP_STATUS dpp_stat_cara_queue_appoint_mode_set(DPP_DEV_T *dev,
+												ZXIC_UINT32 global_en,
+												ZXIC_UINT32 sp_en,
+												ZXIC_UINT32 appoint_sp,
+												ZXIC_UINT32 appoint_queue);
+
+/***********************************************************/
+/** 获取car A指定队列模式的配置
+     * @param   dev_id           设备号           car编号
+     * @param   p_global_en      全局队列使能，0-不使能，1-使能
+     * @param   p_sp_en          优先级队列使能，0-不使能，1-使能
+     * @param   p_appoint_sp     指定的优先级
+     * @param   p_appoint_queue  指定的队列号
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls       @date  2016/04/07
+     ************************************************************/
+DPP_STATUS dpp_stat_cara_queue_appoint_mode_get(DPP_DEV_T *dev,
+												ZXIC_UINT32 *p_global_en,
+												ZXIC_UINT32 *p_sp_en,
+												ZXIC_UINT32 *p_appoint_sp,
+												ZXIC_UINT32 *p_appoint_queue);
+
+/***********************************************************/
+/** 配置car B的qvos溢出模式
+     * @param   dev_id           设备号           car编号
+     * @param   flow_id          流号
+     * @param   qvos_mode        溢出模式，参见DPP_CAR_QVOS_MODE_E
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/04/06
+     ************************************************************/
+DPP_STATUS dpp_stat_carb_queue_qvos_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+										ZXIC_UINT32 qvos_mode);
+
+/***********************************************************/
+/** 获取car B的qvos溢出模式
+     * @param   dev_id           设备号           car编号
+     * @param   flow_id          流号
+     * @param   p_qvos_mode      qvos溢出模式
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls       @date  2016/04/06
+     ************************************************************/
+DPP_STATUS dpp_stat_carb_queue_qvos_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+										ZXIC_UINT32 *p_qvos_mode);
+
+/***********************************************************/
+/** car B指定队列模式配置，仅用于调试
+     * @param   dev_id           设备号           car编号
+     * @param   global_en        全局队列使能，0-不使能，1-使能
+     * @param   sp_en            优先级队列使能，0-不使能，1-使能
+     * @param   appoint_sp       指定的优先级
+     * @param   appoint_queue    指定的队列号
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls       @date  2016/04/06
+     ************************************************************/
+DPP_STATUS dpp_stat_carb_queue_appoint_mode_set(ZXIC_UINT32 dev_id,
+												ZXIC_UINT32 global_en,
+												ZXIC_UINT32 sp_en,
+												ZXIC_UINT32 appoint_sp,
+												ZXIC_UINT32 appoint_queue);
+/***********************************************************/
+/** 获取car B指定队列模式的配置
+     * @param   dev_id        设备号           car编号
+     * @param   p_global_en      全局队列使能，0-不使能，1-使能
+     * @param   p_sp_en          优先级队列使能，0-不使能，1-使能
+     * @param   p_appoint_sp     指定的优先级
+     * @param   p_appoint_queue  指定的队列号
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/04/07
+     ************************************************************/
+DPP_STATUS dpp_stat_carb_queue_appoint_mode_get(ZXIC_UINT32 dev_id,
+												ZXIC_UINT32 *p_global_en,
+												ZXIC_UINT32 *p_sp_en,
+												ZXIC_UINT32 *p_appoint_sp,
+												ZXIC_UINT32 *p_appoint_queue);
+
+/***********************************************************/
+/** 配置car C的qvos溢出模式
+     * @param   dev_id           设备号           car编号
+     * @param   flow_id          流号
+     * @param   qvos_mode        溢出模式，参见DPP_CAR_QVOS_MODE_E
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/04/06
+     ************************************************************/
+DPP_STATUS dpp_stat_carc_queue_qvos_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+										ZXIC_UINT32 qvos_mode);
+
+/***********************************************************/
+/** 获取car C的qvos溢出模式
+     * @param   dev_id           设备号           car编号
+     * @param   flow_id          流号
+     * @param   p_qvos_mode      qvos溢出模式
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/04/06
+     ************************************************************/
+DPP_STATUS dpp_stat_carc_queue_qvos_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+										ZXIC_UINT32 *p_qvos_mode);
+
+/***********************************************************/
+/** car C指定队列模式配置，仅用于调试
+     * @param   dev_id           设备号           car编号
+     * @param   global_en        全局队列使能，0-不使能，1-使能
+     * @param   sp_en            优先级队列使能，0-不使能，1-使能
+     * @param   appoint_sp       指定的优先级
+     * @param   appoint_queue    指定的队列号
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/04/06
+     ************************************************************/
+DPP_STATUS dpp_stat_carc_queue_appoint_mode_set(ZXIC_UINT32 dev_id,
+												ZXIC_UINT32 global_en,
+												ZXIC_UINT32 sp_en,
+												ZXIC_UINT32 appoint_sp,
+												ZXIC_UINT32 appoint_queue);
+
+/***********************************************************/
+/** 获取car C指定队列模式的配置
+     * @param   dev_id           设备号           car编号
+     * @param   p_global_en      全局队列使能，0-不使能，1-使能
+     * @param   p_sp_en          优先级队列使能，0-不使能，1-使能
+     * @param   p_appoint_sp     指定的优先级
+     * @param   p_appoint_queue  指定的队列号
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/04/07
+     ************************************************************/
+DPP_STATUS dpp_stat_carc_queue_appoint_mode_get(ZXIC_UINT32 dev_id,
+												ZXIC_UINT32 *p_global_en,
+												ZXIC_UINT32 *p_sp_en,
+												ZXIC_UINT32 *p_appoint_sp,
+												ZXIC_UINT32 *p_appoint_queue);
+
+/***********************************************************/
+/**
+     * @param   dev_id
+     * @param   p_mode
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/09/28
+     ************************************************************/
+DPP_STATUS dpp_stat_car_en_mode_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_mode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_stat_cfg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_stat_cfg.h
old mode 100755
new mode 100644
index bd4a1cf68357848afb294b9bf0981206f7516a71..fb1bf95918cefe53b74cb29602cb7efbb77534ad
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_stat_cfg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/se/dpp_stat_cfg.h
@@ -1,196 +1,187 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_stat_cfg.h
-* 文件标识 : 
-* 内容摘要 : 
-* 其它说明 : 
-* 当前版本 : 
-* 作    者 : ls
-* 完成日期 : 2016/03/29
-* DEPARTMENT: ASIC_FPGA_R&D_Dept 
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* 版 本 号:  
-* 修 改 人:  
-* 修改内容:  
-***************************************************************/
-#ifndef _DPP_STAT_CFG_H_
-#define _DPP_STAT_CFG_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "dpp_stat_api.h"
-
-#if ZXIC_REAL("Variable definition")
-
-#define         DPP_STAT_TM_PORT_MAX                (4)
-#define         DPP_STAT_ETM_ADDR_MAX               (9*1024)
-#define         DPP_STAT_FTM_ADDR_MAX               (2048)	
-#define         DPP_STAT_IND_WR_MODE                (0)
-#define         DPP_STAT_IND_RD_MODE                (1)
-#define         DPP_STAT_TM_MOV_PERIOD_MAX          (0xff)
-
-#define         DPP_STAT_WIDTH_3_MAX_VALUE          ((1<<3) - 1)
-#define         DPP_STAT_WIDTH_4_MAX_VALUE          ((1<<4) - 1)
-#define         DPP_STAT_PPU_ERAM_DEPTH_MAX         (0x7ffff)
-#define         DPP_STAT_PPU_ERAM_BADDR_MAX         (0x7ffff)
-#define         DPP_STAT_PPU_DDR_BADDR_MAX          (0x4ffffff)
-
-#define         DPP_STAT_OAM_ERAM_BADDR_MAX         (0x7ffff)
-#define         DPP_STAT_OAM_DDR_BADDR_MAX          (0x4ffffff)
-
-#define         DPP_STAT_PLCR_ERAM_BADDR_MAX        (0x7ffff)
-#define         DPP_STAT_PLCR_ID                (0)
-
-#define         DPP_STAT_TM_FLAG_FTM_PKT_EN         (0)
-#define         DPP_STAT_TM_FLAG_ETM_PKT_EN         (1)
-#define         DPP_STAT_TM_FLAG_ERAM_EN            (2)
-
-#define         DPP_STAT_PPU_STAT_CHANNEL_NUM       (16)
-#define         DPP_STAT_PPU_MEX_NUM                (6)
-#define         CMMU_DDR_DIR_CPY_NUM                (15)
-
-
-/** stat TM类型 */
-typedef enum dpp_stat_tm_type_e
-{
-    DPP_STAT_TM_TYPE_ETM = 0,   /*<@brief FTM模式 */
-    DPP_STAT_TM_TYPE_FTM = 1,   /*<@brief ETM模式 */
-    DPP_STAT_TM_TYPE_MAX
-}DPP_STAT_TM_TYPE_E;
-
-
-typedef enum dpp_stat_tm_store_mode_e
-{
-    DPP_STAT_TM_STORE_MODE_ERAM = 0,    /* 片内存储模式 */
-    DPP_STAT_TM_STORE_MODE_MIX  = 1,    /* 混合存储模式 */
-    DPP_STAT_TM_STORE_MODE_MAX,
-}DPP_STAT_TM_STORE_MODE_E;
-
-typedef enum dpp_stat_etm_depth_mode_e
-{
-    DPP_STAT_ETM_DEPTH_ERAM_1K = 0,
-    DPP_STAT_ETM_DEPTH_ERAM_4K = 1,
-    DPP_STAT_ETM_DEPTH_ERAM_5K = 2,
-    DPP_STAT_ETM_DEPTH_ERAM_8K = 3,
-    DPP_STAT_ETM_DEPTH_ERAM_9K = 4,
-    DPP_STAT_ETM_DEPTH_MIX_2K  = 5,
-    DPP_STAT_ETM_DEPTH_MIX_8K  = 6,
-    DPP_STAT_ETM_DEPTH_MIX_9K  = 7,
-    DPP_STAT_ETM_DEPTH_MAX,
-}DPP_STAT_ETM_DEPTH_MODE_E;
-
-typedef enum stat_store_mode_e
-{
-    STAT_STORE_MODE_IN_ERAM = 0,
-    STAT_STORE_MODE_IN_DDR  = 1,
-    STAT_STORE_MODE_MAX,
-}STAT_STORE_MODE_E;
-
-typedef enum stat_oam_type_e
-{
-    STAT_OAM_TYPE_ERAM     = 0,
-    STAT_OAM_TYPE_LM_ERAM  = 1,
-    STAT_OAM_TYPE_DDR      = 2,
-    STAT_OAM_TYPE_MAX,
-}STAT_OAM_TYPE_E;
-
-typedef struct dpp_stat_dbg_cnt_t
-{
-    ZXIC_UINT32 stat_to_smmu0_rsp_fc_cnt[DPP_STAT_PPU_STAT_CHANNEL_NUM];
-    ZXIC_UINT32 stat_rcv_smmu0_req_fc_cnt[DPP_STAT_PPU_STAT_CHANNEL_NUM];
-    ZXIC_UINT32 stat_to_ppu_req_fc_cnt[DPP_STAT_PPU_MEX_NUM];
-    ZXIC_UINT32 stat_rcv_ppu_rsp_fc_cnt[DPP_STAT_PPU_MEX_NUM];
-    ZXIC_UINT32 stat_rcv_se_etm_wr_fc_cnt;
-    ZXIC_UINT32 stat_rcv_se_etm_rd_fc_cnt;
-    ZXIC_UINT32 stat_rcv_se_ftm_wr_fc_cnt;
-    ZXIC_UINT32 stat_rcv_se_ftm_rd_fc_cnt;
-    ZXIC_UINT32 stat_to_etm_deq_fc_cnt;
-    ZXIC_UINT32 stat_to_etm_enq_fc_cnt;
-    ZXIC_UINT32 stat_to_ftm_deq_fc_cnt;
-    ZXIC_UINT32 stat_to_ftm_enq_fc_cnt;
-    ZXIC_UINT32 stat_to_oam_lm_fc_cnt;
-    ZXIC_UINT32 stat_rcv_oam_lm_fc_cnt;
-    ZXIC_UINT32 stat_to_oam_fc_cnt;
-    ZXIC_UINT32 stat_rcv_cmmu_fc_cnt;
-    ZXIC_UINT32 stat_to_cmmu_req_cnt;
-    ZXIC_UINT32 stat_rcv_smmu0_rsp_cnt[DPP_STAT_PPU_STAT_CHANNEL_NUM];
-    ZXIC_UINT32 stat_to_smmu0_req_cnt[DPP_STAT_PPU_STAT_CHANNEL_NUM];
-    ZXIC_UINT32 stat_plcr_rcv_smmu0_rsp1_cnt;
-    ZXIC_UINT32 stat_plcr_rcv_smmu0_rsp0_cnt;
-    ZXIC_UINT32 stat_plcr_to_smmu0_req1_cnt;
-    ZXIC_UINT32 stat_plcr_to_smmu0_req0_cnt;
-    ZXIC_UINT32 stat_to_ppu_mex_rsp_cnt[DPP_STAT_PPU_MEX_NUM];
-    ZXIC_UINT32 stat_oam_lm_rsp_cnt;
-    ZXIC_UINT32 stat_rcv_oam_lm_req_cnt;
-    ZXIC_UINT32 stat_rcv_oam_req_cnt;
-    ZXIC_UINT32 stat_rcv_ppu_mex_key_cnt[DPP_STAT_PPU_MEX_NUM];
-    ZXIC_UINT32 stat_rcv_se_etm_rsp_cnt;
-    ZXIC_UINT32 stat_rcv_etm_se_wr_req_cnt;
-    ZXIC_UINT32 stat_rcv_etm_se_rd_req_cnt;
-    ZXIC_UINT32 stat_rcv_se_ftm_rsp_cnt;
-    ZXIC_UINT32 stat_to_ftm_se_wr_req_cnt;
-    ZXIC_UINT32 stat_to_ftm_se_rd_req_cnt;
-    ZXIC_UINT32 stat_rcv_ftm_smmu0_req_cnt0;
-    ZXIC_UINT32 stat_rcv_ftm_smmu0_req_cnt1;
-    ZXIC_UINT32 stat_rcv_etm_smmu0_req_cnt0;
-    ZXIC_UINT32 stat_rcv_etm_smmu0_req_cnt1;
-    ZXIC_UINT32 ppu_no_exist_opcd_ex_cnt[DPP_STAT_PPU_MEX_NUM];
-    ZXIC_UINT32 stat_rcv_tm_eram_cpu_rsp_cnt;
-    ZXIC_UINT32 cpu_rd_eram_req_cnt;
-    ZXIC_UINT32 cpu_wr_eram_req_cnt;
-    ZXIC_UINT32 tm_stat_ddr_cpu_rsp_cnt;
-    ZXIC_UINT32 cpu_rd_ddr_req_cnt;
-    ZXIC_UINT32 cpu_wr_ddr_req_cnt;
-}DPP_STAT_DBG_CNT_T;
-
-#endif
-
-/***********************************************************/
-/** 获取ppu统计片内深度
-* @param   dev_id               设备号
-* @param   p_ppu_eram_depth     ppu统计片内深度
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/03/31
-************************************************************/
-DPP_STATUS dpp_stat_ppu_eram_depth_get(DPP_DEV_T *dev,
-                                       ZXIC_UINT32* p_ppu_eram_depth);
-
-
-/***********************************************************/
-/** 获取ppu统计 ERAM基地址
-* @param   dev_id               设备号
-* @param   p_ppu_eram_baddr     ppu统计片内基地址
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/03/31
-************************************************************/
-DPP_STATUS dpp_stat_ppu_eram_baddr_get(DPP_DEV_T *dev,
-                                       ZXIC_UINT32* p_ppu_eram_baddr);
-
-/***********************************************************/
-/** 获取ppu统计 ddr基地址
-* @param   dev_id               设备号
-* @param   p_ppu_ddr_baddr      ppu统计片外基地址
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see     
-* @author  ls      @date  2016/03/31
-************************************************************/
-DPP_STATUS dpp_stat_ppu_ddr_baddr_get(DPP_DEV_T *dev,
-                                      ZXIC_UINT32* p_ppu_ddr_baddr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_stat_cfg.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : ls
+* 完成日期 : 2016/03/29
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#ifndef _DPP_STAT_CFG_H_
+#define _DPP_STAT_CFG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "dpp_stat_api.h"
+
+#if ZXIC_REAL("Variable definition")
+
+#define DPP_STAT_TM_PORT_MAX (4)
+#define DPP_STAT_ETM_ADDR_MAX (9 * 1024)
+#define DPP_STAT_FTM_ADDR_MAX (2048)
+#define DPP_STAT_IND_WR_MODE (0)
+#define DPP_STAT_IND_RD_MODE (1)
+#define DPP_STAT_TM_MOV_PERIOD_MAX (0xff)
+
+#define DPP_STAT_WIDTH_3_MAX_VALUE ((1 << 3) - 1)
+#define DPP_STAT_WIDTH_4_MAX_VALUE ((1 << 4) - 1)
+#define DPP_STAT_PPU_ERAM_DEPTH_MAX (0x7ffff)
+#define DPP_STAT_PPU_ERAM_BADDR_MAX (0x7ffff)
+#define DPP_STAT_PPU_DDR_BADDR_MAX (0x4ffffff)
+
+#define DPP_STAT_OAM_ERAM_BADDR_MAX (0x7ffff)
+#define DPP_STAT_OAM_DDR_BADDR_MAX (0x4ffffff)
+
+#define DPP_STAT_PLCR_ERAM_BADDR_MAX (0x7ffff)
+#define DPP_STAT_PLCR_ID (0)
+
+#define DPP_STAT_TM_FLAG_FTM_PKT_EN (0)
+#define DPP_STAT_TM_FLAG_ETM_PKT_EN (1)
+#define DPP_STAT_TM_FLAG_ERAM_EN (2)
+
+#define DPP_STAT_PPU_STAT_CHANNEL_NUM (16)
+#define DPP_STAT_PPU_MEX_NUM (6)
+#define CMMU_DDR_DIR_CPY_NUM (15)
+
+/** stat TM类型 */
+typedef enum dpp_stat_tm_type_e {
+	DPP_STAT_TM_TYPE_ETM = 0, /*<@brief FTM模式 */
+	DPP_STAT_TM_TYPE_FTM = 1, /*<@brief ETM模式 */
+	DPP_STAT_TM_TYPE_MAX
+} DPP_STAT_TM_TYPE_E;
+
+typedef enum dpp_stat_tm_store_mode_e {
+	DPP_STAT_TM_STORE_MODE_ERAM = 0, /* 片内存储模式 */
+	DPP_STAT_TM_STORE_MODE_MIX = 1, /* 混合存储模式 */
+	DPP_STAT_TM_STORE_MODE_MAX,
+} DPP_STAT_TM_STORE_MODE_E;
+
+typedef enum dpp_stat_etm_depth_mode_e {
+	DPP_STAT_ETM_DEPTH_ERAM_1K = 0,
+	DPP_STAT_ETM_DEPTH_ERAM_4K = 1,
+	DPP_STAT_ETM_DEPTH_ERAM_5K = 2,
+	DPP_STAT_ETM_DEPTH_ERAM_8K = 3,
+	DPP_STAT_ETM_DEPTH_ERAM_9K = 4,
+	DPP_STAT_ETM_DEPTH_MIX_2K = 5,
+	DPP_STAT_ETM_DEPTH_MIX_8K = 6,
+	DPP_STAT_ETM_DEPTH_MIX_9K = 7,
+	DPP_STAT_ETM_DEPTH_MAX,
+} DPP_STAT_ETM_DEPTH_MODE_E;
+
+typedef enum stat_store_mode_e {
+	STAT_STORE_MODE_IN_ERAM = 0,
+	STAT_STORE_MODE_IN_DDR = 1,
+	STAT_STORE_MODE_MAX,
+} STAT_STORE_MODE_E;
+
+typedef enum stat_oam_type_e {
+	STAT_OAM_TYPE_ERAM = 0,
+	STAT_OAM_TYPE_LM_ERAM = 1,
+	STAT_OAM_TYPE_DDR = 2,
+	STAT_OAM_TYPE_MAX,
+} STAT_OAM_TYPE_E;
+
+typedef struct dpp_stat_dbg_cnt_t {
+	ZXIC_UINT32 stat_to_smmu0_rsp_fc_cnt[DPP_STAT_PPU_STAT_CHANNEL_NUM];
+	ZXIC_UINT32 stat_rcv_smmu0_req_fc_cnt[DPP_STAT_PPU_STAT_CHANNEL_NUM];
+	ZXIC_UINT32 stat_to_ppu_req_fc_cnt[DPP_STAT_PPU_MEX_NUM];
+	ZXIC_UINT32 stat_rcv_ppu_rsp_fc_cnt[DPP_STAT_PPU_MEX_NUM];
+	ZXIC_UINT32 stat_rcv_se_etm_wr_fc_cnt;
+	ZXIC_UINT32 stat_rcv_se_etm_rd_fc_cnt;
+	ZXIC_UINT32 stat_rcv_se_ftm_wr_fc_cnt;
+	ZXIC_UINT32 stat_rcv_se_ftm_rd_fc_cnt;
+	ZXIC_UINT32 stat_to_etm_deq_fc_cnt;
+	ZXIC_UINT32 stat_to_etm_enq_fc_cnt;
+	ZXIC_UINT32 stat_to_ftm_deq_fc_cnt;
+	ZXIC_UINT32 stat_to_ftm_enq_fc_cnt;
+	ZXIC_UINT32 stat_to_oam_lm_fc_cnt;
+	ZXIC_UINT32 stat_rcv_oam_lm_fc_cnt;
+	ZXIC_UINT32 stat_to_oam_fc_cnt;
+	ZXIC_UINT32 stat_rcv_cmmu_fc_cnt;
+	ZXIC_UINT32 stat_to_cmmu_req_cnt;
+	ZXIC_UINT32 stat_rcv_smmu0_rsp_cnt[DPP_STAT_PPU_STAT_CHANNEL_NUM];
+	ZXIC_UINT32 stat_to_smmu0_req_cnt[DPP_STAT_PPU_STAT_CHANNEL_NUM];
+	ZXIC_UINT32 stat_plcr_rcv_smmu0_rsp1_cnt;
+	ZXIC_UINT32 stat_plcr_rcv_smmu0_rsp0_cnt;
+	ZXIC_UINT32 stat_plcr_to_smmu0_req1_cnt;
+	ZXIC_UINT32 stat_plcr_to_smmu0_req0_cnt;
+	ZXIC_UINT32 stat_to_ppu_mex_rsp_cnt[DPP_STAT_PPU_MEX_NUM];
+	ZXIC_UINT32 stat_oam_lm_rsp_cnt;
+	ZXIC_UINT32 stat_rcv_oam_lm_req_cnt;
+	ZXIC_UINT32 stat_rcv_oam_req_cnt;
+	ZXIC_UINT32 stat_rcv_ppu_mex_key_cnt[DPP_STAT_PPU_MEX_NUM];
+	ZXIC_UINT32 stat_rcv_se_etm_rsp_cnt;
+	ZXIC_UINT32 stat_rcv_etm_se_wr_req_cnt;
+	ZXIC_UINT32 stat_rcv_etm_se_rd_req_cnt;
+	ZXIC_UINT32 stat_rcv_se_ftm_rsp_cnt;
+	ZXIC_UINT32 stat_to_ftm_se_wr_req_cnt;
+	ZXIC_UINT32 stat_to_ftm_se_rd_req_cnt;
+	ZXIC_UINT32 stat_rcv_ftm_smmu0_req_cnt0;
+	ZXIC_UINT32 stat_rcv_ftm_smmu0_req_cnt1;
+	ZXIC_UINT32 stat_rcv_etm_smmu0_req_cnt0;
+	ZXIC_UINT32 stat_rcv_etm_smmu0_req_cnt1;
+	ZXIC_UINT32 ppu_no_exist_opcd_ex_cnt[DPP_STAT_PPU_MEX_NUM];
+	ZXIC_UINT32 stat_rcv_tm_eram_cpu_rsp_cnt;
+	ZXIC_UINT32 cpu_rd_eram_req_cnt;
+	ZXIC_UINT32 cpu_wr_eram_req_cnt;
+	ZXIC_UINT32 tm_stat_ddr_cpu_rsp_cnt;
+	ZXIC_UINT32 cpu_rd_ddr_req_cnt;
+	ZXIC_UINT32 cpu_wr_ddr_req_cnt;
+} DPP_STAT_DBG_CNT_T;
+
+#endif
+
+/***********************************************************/
+/** 获取ppu统计片内深度
+     * @param   dev_id               设备号
+     * @param   p_ppu_eram_depth     ppu统计片内深度
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/03/31
+     ************************************************************/
+DPP_STATUS dpp_stat_ppu_eram_depth_get(DPP_DEV_T *dev,
+									   ZXIC_UINT32 *p_ppu_eram_depth);
+
+/***********************************************************/
+/** 获取ppu统计 ERAM基地址
+     * @param   dev_id               设备号
+     * @param   p_ppu_eram_baddr     ppu统计片内基地址
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/03/31
+     ************************************************************/
+DPP_STATUS dpp_stat_ppu_eram_baddr_get(DPP_DEV_T *dev,
+									   ZXIC_UINT32 *p_ppu_eram_baddr);
+
+/***********************************************************/
+/** 获取ppu统计 ddr基地址
+     * @param   dev_id               设备号
+     * @param   p_ppu_ddr_baddr      ppu统计片外基地址
+     *
+     * @return  NPE_OK-成功，NPE_ERR-失败
+     * @remark  无
+     * @see
+     * @author  ls      @date  2016/03/31
+     ************************************************************/
+DPP_STATUS dpp_stat_ppu_ddr_baddr_get(DPP_DEV_T *dev,
+									  ZXIC_UINT32 *p_ppu_ddr_baddr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt.h
old mode 100755
new mode 100644
index 4bfd7456f168e19cd9aaac790266d82fc097df62..a6cd0b89bcb342ad53879ab6e2a6c824a3bb1446
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt.h
@@ -1,164 +1,167 @@
-/*********************************************************************
-* 版权所有 (C)2013, 深圳市中兴通讯股份有限公司。
-*
-* 文件名称：
-* 文件标识：
-* 内容摘要:
-* 其它说明:
-*
-*
-* 当前版本：
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT   : 100%
-* 作    者： 王春雷10111187
-* 完成日期： 2013-9-2
-********************************************************************/
-
-#ifndef _DPP_SDT_H_
-#define _DPP_SDT_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "dpp_ppu.h"
-
-/**  SDT属性表高32bit中各比特字段的位宽定义*/
-#define DPP_SDT_H_TBL_TYPE_BT_POS                   (29)
-#define DPP_SDT_H_TBL_TYPE_BT_LEN                   (3)
-
-#define DPP_SDT_H_ERAM_MODE_BT_POS                  (26)
-#define DPP_SDT_H_ERAM_MODE_BT_LEN                  (3)
-#define DPP_SDT_H_ERAM_BASE_ADDR_BT_POS             (7)
-#define DPP_SDT_H_ERAM_BASE_ADDR_BT_LEN             (19)
-#define DPP_SDT_L_ERAM_TABLE_DEPTH_BT_POS           (1)
-#define DPP_SDT_L_ERAM_TABLE_DEPTH_BT_LEN           (22)
-
-#define DPP_SDT_H_DDR3_BASE_ADDR_BT_POS             (9)
-#define DPP_SDT_H_DDR3_BASE_ADDR_BT_LEN             (20)
-#define DPP_SDT_H_DDR3_SHARE_TYPE_BT_POS            (7)
-#define DPP_SDT_H_DDR3_SHARE_TYPE_BT_LEN            (2)
-#define DPP_SDT_H_DDR3_RW_LEN_BT_POS                (5)
-#define DPP_SDT_H_DDR3_RW_LEN_BT_LEN                (2)
-#define DPP_SDT_H_DDR3_SDT_NUM_BT_POS               (0)
-#define DPP_SDT_H_DDR3_SDT_NUM_BT_LEN               (5)
-#define DPP_SDT_L_DDR3_SDT_NUM_BT_POS               (29)
-#define DPP_SDT_L_DDR3_SDT_NUM_BT_LEN               (3)
-#define DPP_SDT_L_DDR3_ECC_EN_BT_POS                (28)
-#define DPP_SDT_L_DDR3_ECC_EN_BT_LEN                (1)
-
-#define DPP_SDT_H_HASH_ID_BT_POS                    (27)
-#define DPP_SDT_H_HASH_ID_BT_LEN                    (2)
-#define DPP_SDT_H_HASH_TABLE_WIDTH_BT_POS           (25)
-#define DPP_SDT_H_HASH_TABLE_WIDTH_BT_LEN           (2)
-#define DPP_SDT_H_HASH_KEY_SIZE_BT_POS              (19)
-#define DPP_SDT_H_HASH_KEY_SIZE_BT_LEN              (6)
-#define DPP_SDT_H_HASH_TABLE_ID_BT_POS              (14)
-#define DPP_SDT_H_HASH_TABLE_ID_BT_LEN              (5)
-#define DPP_SDT_H_LEARN_EN_BT_POS                   (13)
-#define DPP_SDT_H_LEARN_EN_BT_LEN                   (1)
-#define DPP_SDT_H_KEEP_ALIVE_BT_POS                 (12)
-#define DPP_SDT_H_KEEP_ALIVE_BT_LEN                 (1)
-#define DPP_SDT_H_KEEP_ALIVE_BADDR_BT_POS           (0)
-#define DPP_SDT_H_KEEP_ALIVE_BADDR_BT_LEN           (12)
-#define DPP_SDT_L_KEEP_ALIVE_BADDR_BT_POS           (25)
-#define DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN           (7)
-#define DPP_SDT_L_RSP_MODE_BT_POS                   (23)
-#define DPP_SDT_L_RSP_MODE_BT_LEN                   (2)
-
-#define DPP_SDT_H_LPM_V46ID_BT_POS                  (28)
-#define DPP_SDT_H_LPM_V46ID_BT_LEN                  (1)
-#define DPP_SDT_H_LPM_RSP_MODE_BT_POS               (0)
-#define DPP_SDT_H_LPM_RSP_MODE_BT_LEN               (2)
-#define DPP_SDT_L_LPM_TABLE_DEPTH_BT_POS            (1)
-#define DPP_SDT_L_LPM_TABLE_DEPTH_BT_LEN            (30)
-
-#define DPP_SDT_H_ETCAM_ID_BT_POS                   (27)
-#define DPP_SDT_H_ETCAM_ID_BT_LEN                   (1)
-#define DPP_SDT_H_ETCAM_KEY_MODE_BT_POS             (25)
-#define DPP_SDT_H_ETCAM_KEY_MODE_BT_LEN             (2)
-#define DPP_SDT_H_ETCAM_TABLE_ID_BT_POS             (21)
-#define DPP_SDT_H_ETCAM_TABLE_ID_BT_LEN             (4)
-#define DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS        (19)
-#define DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN        (2)
-#define DPP_SDT_H_ETCAM_AS_EN_BT_POS                (18)
-#define DPP_SDT_H_ETCAM_AS_EN_BT_LEN                (1)
-#define DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS        (0)
-#define DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN        (18)
-#define DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS        (31)
-#define DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN        (1)
-#define DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_POS          (28)
-#define DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN          (3)
-#define DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_POS          (1)
-#define DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN          (20)
-
-#define DPP_SDT_L_CLUTCH_EN_BT_POS                  (0)
-#define DPP_SDT_L_CLUTCH_EN_BT_LEN                  (1)
-
-#define DPP_SDT_TBL_TYPE_NUM                        (8)
-
-/***********************************************************/
-/** 解析从硬件读取的64bit SDT属性
-* @param   sdt_hig32   硬件表中存储的SDT属性高32bit
-* @param   sdt_low32   硬件表中存储的SDT属性低32bit
-* @param   p_sdt_info  解析之后的SDT属性，根据SDT属性中的table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n
-*                      DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR3_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、\n
-*                      DPP_SDTTBL_ETCAM_T、DPP_SDTTBL_PORTTBL_T。
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/07/13
-************************************************************/
-DPP_STATUS dpp_sdt_tbl_data_parser(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_hig32, ZXIC_UINT32 sdt_low32, ZXIC_VOID *p_sdt_info);
-
-/***********************************************************/
-/** 从软件缓存中获取table data信息
-* @param   dev_id      设备号
-* @param   sdt_no      业务表对应的sdt号,0-255
-* @param   p_sdt_data  sdt表信息
-*
-* @return  
-* @remark  无
-* @see
-* @author  lim      @date  2020/04/16
-************************************************************/
-DPP_STATUS dpp_sdt_tbl_data_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, DPP_SDT_TBL_DATA_T *p_sdt_data);
-
-/***********************************************************/
-/** 将sdt信息保存在软件缓存中
-* @param   dev_id      设备号
-* @param   sdt_no      业务表对应的sdt号
-* @param   table_type  SDT属性中的表类型，取值参考DPP_SDT_TABLE_TYPE_E的定义
-* @param   p_sdt_info  写入的SDT表信息。
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lim      @date  2020/04/16
-************************************************************/
-DPP_STATUS dpp_soft_sdt_tbl_set(ZXIC_UINT32 dev_id, 
-                                ZXIC_UINT32 sdt_no, 
-                                ZXIC_UINT32 table_type, 
-                                DPP_SDT_TBL_DATA_T *p_sdt_info);
-
-/***********************************************************/
-/** 从软件缓存中获取sdt信息
-* @param   device_id   设备号
-* @param   sdt_no      业务表对应的sdt号
-* @param   p_sdt_info  写入的SDT属性。由table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n
-*                      DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、
-*                      DPP_SDTTBL_ETCAM_T。
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lim      @date  2020/04/16
-************************************************************/
-DPP_STATUS dpp_soft_sdt_tbl_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, ZXIC_VOID *p_sdt_info);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/*********************************************************************
+ * 版权所有 (C)2013, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：
+ * 文件标识：
+ * 内容摘要:
+ * 其它说明:
+ *
+ *
+ * 当前版本：
+ * DEPARTMENT: ASIC_FPGA_R&D_Dept
+ * MANUAL_PERCENT   : 100%
+ * 作    者： 王春雷10111187
+ * 完成日期： 2013-9-2
+ ********************************************************************/
+
+#ifndef _DPP_SDT_H_
+#define _DPP_SDT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dpp_ppu.h"
+
+/**  SDT属性表高32bit中各比特字段的位宽定义*/
+#define DPP_SDT_H_TBL_TYPE_BT_POS (29)
+#define DPP_SDT_H_TBL_TYPE_BT_LEN (3)
+
+#define DPP_SDT_H_ERAM_MODE_BT_POS (26)
+#define DPP_SDT_H_ERAM_MODE_BT_LEN (3)
+#define DPP_SDT_H_ERAM_BASE_ADDR_BT_POS (7)
+#define DPP_SDT_H_ERAM_BASE_ADDR_BT_LEN (19)
+#define DPP_SDT_L_ERAM_TABLE_DEPTH_BT_POS (1)
+#define DPP_SDT_L_ERAM_TABLE_DEPTH_BT_LEN (22)
+
+#define DPP_SDT_H_DDR3_BASE_ADDR_BT_POS (9)
+#define DPP_SDT_H_DDR3_BASE_ADDR_BT_LEN (20)
+#define DPP_SDT_H_DDR3_SHARE_TYPE_BT_POS (7)
+#define DPP_SDT_H_DDR3_SHARE_TYPE_BT_LEN (2)
+#define DPP_SDT_H_DDR3_RW_LEN_BT_POS (5)
+#define DPP_SDT_H_DDR3_RW_LEN_BT_LEN (2)
+#define DPP_SDT_H_DDR3_SDT_NUM_BT_POS (0)
+#define DPP_SDT_H_DDR3_SDT_NUM_BT_LEN (5)
+#define DPP_SDT_L_DDR3_SDT_NUM_BT_POS (29)
+#define DPP_SDT_L_DDR3_SDT_NUM_BT_LEN (3)
+#define DPP_SDT_L_DDR3_ECC_EN_BT_POS (28)
+#define DPP_SDT_L_DDR3_ECC_EN_BT_LEN (1)
+
+#define DPP_SDT_H_HASH_ID_BT_POS (27)
+#define DPP_SDT_H_HASH_ID_BT_LEN (2)
+#define DPP_SDT_H_HASH_TABLE_WIDTH_BT_POS (25)
+#define DPP_SDT_H_HASH_TABLE_WIDTH_BT_LEN (2)
+#define DPP_SDT_H_HASH_KEY_SIZE_BT_POS (19)
+#define DPP_SDT_H_HASH_KEY_SIZE_BT_LEN (6)
+#define DPP_SDT_H_HASH_TABLE_ID_BT_POS (14)
+#define DPP_SDT_H_HASH_TABLE_ID_BT_LEN (5)
+#define DPP_SDT_H_LEARN_EN_BT_POS (13)
+#define DPP_SDT_H_LEARN_EN_BT_LEN (1)
+#define DPP_SDT_H_KEEP_ALIVE_BT_POS (12)
+#define DPP_SDT_H_KEEP_ALIVE_BT_LEN (1)
+#define DPP_SDT_H_KEEP_ALIVE_BADDR_BT_POS (0)
+#define DPP_SDT_H_KEEP_ALIVE_BADDR_BT_LEN (12)
+#define DPP_SDT_L_KEEP_ALIVE_BADDR_BT_POS (25)
+#define DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN (7)
+#define DPP_SDT_L_RSP_MODE_BT_POS (23)
+#define DPP_SDT_L_RSP_MODE_BT_LEN (2)
+
+#define DPP_SDT_H_LPM_V46ID_BT_POS (28)
+#define DPP_SDT_H_LPM_V46ID_BT_LEN (1)
+#define DPP_SDT_H_LPM_RSP_MODE_BT_POS (0)
+#define DPP_SDT_H_LPM_RSP_MODE_BT_LEN (2)
+#define DPP_SDT_L_LPM_TABLE_DEPTH_BT_POS (1)
+#define DPP_SDT_L_LPM_TABLE_DEPTH_BT_LEN (30)
+
+#define DPP_SDT_H_ETCAM_ID_BT_POS (27)
+#define DPP_SDT_H_ETCAM_ID_BT_LEN (1)
+#define DPP_SDT_H_ETCAM_KEY_MODE_BT_POS (25)
+#define DPP_SDT_H_ETCAM_KEY_MODE_BT_LEN (2)
+#define DPP_SDT_H_ETCAM_TABLE_ID_BT_POS (21)
+#define DPP_SDT_H_ETCAM_TABLE_ID_BT_LEN (4)
+#define DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS (19)
+#define DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN (2)
+#define DPP_SDT_H_ETCAM_AS_EN_BT_POS (18)
+#define DPP_SDT_H_ETCAM_AS_EN_BT_LEN (1)
+#define DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS (0)
+#define DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN (18)
+#define DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS (31)
+#define DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN (1)
+#define DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_POS (28)
+#define DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN (3)
+#define DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_POS (1)
+#define DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN (20)
+
+#define DPP_SDT_L_CLUTCH_EN_BT_POS (0)
+#define DPP_SDT_L_CLUTCH_EN_BT_LEN (1)
+
+#define DPP_SDT_TBL_TYPE_NUM (8)
+
+/***********************************************************/
+/** 解析从硬件读取的64bit SDT属性
+     * @param   sdt_hig32   硬件表中存储的SDT属性高32bit
+     * @param   sdt_low32   硬件表中存储的SDT属性低32bit
+     * @param   p_sdt_info  解析之后的SDT属性，根据SDT属性中的table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n
+     *                      DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR3_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、\n
+     *                      DPP_SDTTBL_ETCAM_T、DPP_SDTTBL_PORTTBL_T。
+     *
+     * @return  DPP_OK-成功，DPP_ERR-失败
+     * @remark  无
+     * @see
+     * @author  王春雷      @date  2015/07/13
+     ************************************************************/
+DPP_STATUS dpp_sdt_tbl_data_parser(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_hig32,
+								   ZXIC_UINT32 sdt_low32,
+								   ZXIC_VOID *p_sdt_info);
+
+/***********************************************************/
+/** 从软件缓存中获取table data信息
+     * @param   dev_id      设备号
+     * @param   sdt_no      业务表对应的sdt号,0-255
+     * @param   p_sdt_data  sdt表信息
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  lim      @date  2020/04/16
+     ************************************************************/
+DPP_STATUS dpp_sdt_tbl_data_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no,
+								DPP_SDT_TBL_DATA_T *p_sdt_data);
+
+/***********************************************************/
+/** 将sdt信息保存在软件缓存中
+     * @param   dev_id      设备号
+     * @param   sdt_no      业务表对应的sdt号
+     * @param   table_type  SDT属性中的表类型，取值参考DPP_SDT_TABLE_TYPE_E的定义
+     * @param   p_sdt_info  写入的SDT表信息。
+     *
+     * @return  DPP_OK-成功，DPP_ERR-失败
+     * @remark  无
+     * @see
+     * @author  lim      @date  2020/04/16
+     ************************************************************/
+DPP_STATUS dpp_soft_sdt_tbl_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no,
+								ZXIC_UINT32 table_type,
+								DPP_SDT_TBL_DATA_T *p_sdt_info);
+
+/***********************************************************/
+/** 从软件缓存中获取sdt信息
+     * @param   device_id   设备号
+     * @param   sdt_no      业务表对应的sdt号
+     * @param   p_sdt_info  写入的SDT属性。由table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n
+     *                      DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、
+     *                      DPP_SDTTBL_ETCAM_T。
+     *
+     * @return  DPP_OK-成功，DPP_ERR-失败
+     * @remark  无
+     * @see
+     * @author  lim      @date  2020/04/16
+     ************************************************************/
+DPP_STATUS dpp_soft_sdt_tbl_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no,
+								ZXIC_VOID *p_sdt_info);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt_def.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt_def.h
old mode 100755
new mode 100644
index 4b8e89514ac7fa0471febf3b48094b8008ff1011..6c917fd2359df5e840b9b0706d00eaf8521dc3ae
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt_def.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt_def.h
@@ -1,143 +1,129 @@
 /*********************************************************************
-* 版权所有 (C)2001, 深圳市中兴通讯股份有限公司。
-*
-* 文件名称：
-* 文件标识：
-* 内容摘要:
-* 其它说明:
-*
-*
-* 当前版本：
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT   : 100%
-* 作    者： 石金锋
-* 完成日期：2012-09-21
-********************************************************************/
+ * 版权所有 (C)2001, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：
+ * 文件标识：
+ * 内容摘要:
+ * 其它说明:
+ *
+ *
+ * 当前版本：
+ * DEPARTMENT: ASIC_FPGA_R&D_Dept
+ * MANUAL_PERCENT   : 100%
+ * 作    者： 石金锋
+ * 完成日期：2012-09-21
+ ********************************************************************/
 #ifndef _DPP_SDT_DEF_H_
 #define _DPP_SDT_DEF_H_
 
-
-typedef enum   dpp_tbl_type_e
-{
-    TblType_Invalid = 0,
-    TblType_Eram128 = 1,
-    TblType_DDR3    = 2,
-    TblType_HASH    = 3,
-    TblType_LPM     = 4,
-    TblType_eTcam   = 5,
-    TblType_PORTTBL = 6,
-    TblType_MAX     = 7
+typedef enum dpp_tbl_type_e {
+	TblType_Invalid = 0,
+	TblType_Eram128 = 1,
+	TblType_DDR3 = 2,
+	TblType_HASH = 3,
+	TblType_LPM = 4,
+	TblType_eTcam = 5,
+	TblType_PORTTBL = 6,
+	TblType_MAX = 7
 } DPP_TBL_TYPE_E;
 
-typedef enum   dpp_eram128_mode_e
-{
-    Eram128Mode_1BITS   = 0,
-    Eram128Mode_32BITS  = 1,
-    Eram128Mode_64BITS  = 2,
-    Eram128Mode_128BITS = 3,
-    Eram128Mode_2BITS   = 4,/** Add By LiuShuo @ 2016年2月24日15:56:39*/
-    Eram128Mode_4BITS   = 5,
-    Eram128Mode_8BITS   = 6,
-    Eram128Mode_16BITS  = 7,
-    Eram128Mode_MAX     = 8
+typedef enum dpp_eram128_mode_e {
+	Eram128Mode_1BITS = 0,
+	Eram128Mode_32BITS = 1,
+	Eram128Mode_64BITS = 2,
+	Eram128Mode_128BITS = 3,
+	Eram128Mode_2BITS = 4, /** Add By LiuShuo @ 2016年2月24日15:56:39*/
+	Eram128Mode_4BITS = 5,
+	Eram128Mode_8BITS = 6,
+	Eram128Mode_16BITS = 7,
+	Eram128Mode_MAX = 8
 } DPP_ERAM128_MODE_E;
 
-typedef enum   dpp_dde3_mode_e
-{
-    DDR3Mode_128BITS = 0,
-    DDR3Mode_256BITS = 1,    
-    DDR3Mode_512BITS = 2,
-    DDR3Mode_MAX     = 3
+typedef enum dpp_dde3_mode_e {
+	DDR3Mode_128BITS = 0,
+	DDR3Mode_256BITS = 1,
+	DDR3Mode_512BITS = 2,
+	DDR3Mode_MAX = 3
 } DPP_DDR3_MODE_E;
 /** DDR3 共享模式 */
-typedef enum   dpp_ddr3_share_mode_e
-{
-    DDR_SHARE_MODE_NONE = 0,    /** <@brief 不共享模式  */
-    DDR_SHARE_MODE_1_2  = 1,    /** <@brief 1/2共享模式 */
-    DDR_SHARE_MODE_1_4  = 2,    /** <@brief 1/4共享模式 */
-    DDR_SHARE_MODE_1_8  = 3,    /** <@brief 1/8共享模式 */
-    DDR_SHARE_MODE_MAX  = 4,    /** <@brief 不可用      */
+typedef enum dpp_ddr3_share_mode_e {
+	DDR_SHARE_MODE_NONE = 0, /** <@brief 不共享模式  */
+	DDR_SHARE_MODE_1_2 = 1, /** <@brief 1/2共享模式 */
+	DDR_SHARE_MODE_1_4 = 2, /** <@brief 1/4共享模式 */
+	DDR_SHARE_MODE_1_8 = 3, /** <@brief 1/8共享模式 */
+	DDR_SHARE_MODE_MAX = 4, /** <@brief 不可用      */
 } DPP_DDR3_SHARE_MODE_E;
 
-typedef enum dpp_ddr3_copy_type_e
-{
-    DDR3_COPY_TYPE_INN_0  = 0,
-    DDR3_COPY_TYPE_INN_2  = 1,
-    DDR3_COPY_TYPE_INN_4  = 2,
-    DDR3_COPY_TYPE_INN_8  = 3,
-    DDR3_COPY_TYPE_OUT_0  = 4,
-    DDR3_COPY_TYPE_OUT_1  = 5,
-    DDR3_COPY_TYPE_OUT_2  = 7,
+typedef enum dpp_ddr3_copy_type_e {
+	DDR3_COPY_TYPE_INN_0 = 0,
+	DDR3_COPY_TYPE_INN_2 = 1,
+	DDR3_COPY_TYPE_INN_4 = 2,
+	DDR3_COPY_TYPE_INN_8 = 3,
+	DDR3_COPY_TYPE_OUT_0 = 4,
+	DDR3_COPY_TYPE_OUT_1 = 5,
+	DDR3_COPY_TYPE_OUT_2 = 7,
 } DPP_DDR3_COPY_TYPE_E;
 
 /**  仿真器表项操作特殊定制，仅用于操作仿真器设备*/
-#define HASH_SIM_ADD_ADDR       (0xFFFFFFF4)
-#define HASH_SIM_DEL_ADDR       (0xFFFFFFF8)
-#define LPM_SIM_ADD_ADDR        (0xFFFFFFE4)
-#define LPM_SIM_DEL_ADDR        (0xFFFFFFE8)
-#define ETCAM_SIM_ADD_ADDR      (0xFFFFFFD4)
-#define ETCAM_SIM_DEL_ADDR      (0xFFFFFFD8)
+#define HASH_SIM_ADD_ADDR (0xFFFFFFF4)
+#define HASH_SIM_DEL_ADDR (0xFFFFFFF8)
+#define LPM_SIM_ADD_ADDR (0xFFFFFFE4)
+#define LPM_SIM_DEL_ADDR (0xFFFFFFE8)
+#define ETCAM_SIM_ADD_ADDR (0xFFFFFFD4)
+#define ETCAM_SIM_DEL_ADDR (0xFFFFFFD8)
 
-typedef struct dpp_sdt_smmu0_t
-{
-    ZXIC_UINT32    *p_data;            /*输入,输出数据地址       */
-    ZXIC_UINT32     wr_rd_flag;        /*0: Write 1: Read        */
-    ZXIC_UINT32     tbl_index;         /*表项索引                */
-    ZXIC_UINT32     tbl_base_addr;     /*表项基地址              */
-    ZXIC_UINT32     mode;              /*参见DPP_ERAM128_MODE_E  */
-    ZXIC_UINT32     tbl_depth;         /*表项的深度，越界检测    */
+typedef struct dpp_sdt_smmu0_t {
+	ZXIC_UINT32 *p_data; /*输入,输出数据地址       */
+	ZXIC_UINT32 wr_rd_flag; /*0: Write 1: Read        */
+	ZXIC_UINT32 tbl_index; /*表项索引                */
+	ZXIC_UINT32 tbl_base_addr; /*表项基地址              */
+	ZXIC_UINT32 mode; /*参见DPP_ERAM128_MODE_E  */
+	ZXIC_UINT32 tbl_depth; /*表项的深度，越界检测    */
 } DPP_SDT_SMMU0_T;
 
-typedef struct dpp_sdt_smmu1_t
-{
-    ZXIC_UINT32    *p_data;            /*输入,输出数据地址           */
-    ZXIC_UINT32     crc_chk_en;        /*Crc效验使能                 */
-    ZXIC_UINT32     wr_rd_flag;        /*0: Write 1: Read            */
-    ZXIC_UINT32     ddr_share_type;    /*参见DPP_DDR3_SHARE_MODE_E   */
-    ZXIC_UINT32     tbl_index;         /*表项索引                    */
-    ZXIC_UINT32     tbl_base_addr;     /*DDR3片内基地址              */
-    ZXIC_UINT32     ddr_mode;          /*参见DPP_DDR3_MODE_E         */
-    ZXIC_UINT32     sdt_no;            /*SDT表号                     */
+typedef struct dpp_sdt_smmu1_t {
+	ZXIC_UINT32 *p_data; /*输入,输出数据地址           */
+	ZXIC_UINT32 crc_chk_en; /*Crc效验使能                 */
+	ZXIC_UINT32 wr_rd_flag; /*0: Write 1: Read            */
+	ZXIC_UINT32 ddr_share_type; /*参见DPP_DDR3_SHARE_MODE_E   */
+	ZXIC_UINT32 tbl_index; /*表项索引                    */
+	ZXIC_UINT32 tbl_base_addr; /*DDR3片内基地址              */
+	ZXIC_UINT32 ddr_mode; /*参见DPP_DDR3_MODE_E         */
+	ZXIC_UINT32 sdt_no; /*SDT表号                     */
 } DPP_SDT_SMMU1_T;
 
-typedef struct dpp_sdt_hash_t
-{
-    ZXIC_UINT32     id;           /* hash引擎号 */
-    ZXIC_UINT32     tbl_id;       /* hash业务号 */
-    ZXIC_UINT32     *p_data;
-    ZXIC_UINT32     addr;
-    ZXIC_UINT32     length;       /* 数据长度，以4字节为单位 */
-    ZXIC_UINT32     key_size;     /* 键值长度，以字节为单位 */
-    ZXIC_UINT32     key_type;     /* 表项存储位宽 */
-    ZXIC_UINT32     rsp_mode;
-    ZXIC_UINT32     wr_rd_flag;   /* 0: Write 1: Read */
+typedef struct dpp_sdt_hash_t {
+	ZXIC_UINT32 id; /* hash引擎号 */
+	ZXIC_UINT32 tbl_id; /* hash业务号 */
+	ZXIC_UINT32 *p_data;
+	ZXIC_UINT32 addr;
+	ZXIC_UINT32 length; /* 数据长度，以4字节为单位 */
+	ZXIC_UINT32 key_size; /* 键值长度，以字节为单位 */
+	ZXIC_UINT32 key_type; /* 表项存储位宽 */
+	ZXIC_UINT32 rsp_mode;
+	ZXIC_UINT32 wr_rd_flag; /* 0: Write 1: Read */
 } DPP_SDT_HASH_T;
 
-typedef struct dpp_sdt_lpm_t
-{
-    ZXIC_UINT32     *p_data;
-    ZXIC_UINT32     addr;
-    ZXIC_UINT32     length;       /* 数据长度，以4字节为单位 */
-    ZXIC_UINT32     wr_rd_flag;   /* 0: Write 1: Read */
-    ZXIC_UINT32     v46_flag;     /* 1:ipv4, 0:ipv6 */
+typedef struct dpp_sdt_lpm_t {
+	ZXIC_UINT32 *p_data;
+	ZXIC_UINT32 addr;
+	ZXIC_UINT32 length; /* 数据长度，以4字节为单位 */
+	ZXIC_UINT32 wr_rd_flag; /* 0: Write 1: Read */
+	ZXIC_UINT32 v46_flag; /* 1:ipv4, 0:ipv6 */
 } DPP_SDT_LPM_T;
 
-typedef struct dpp_sdt_etcam_t
-{
-    ZXIC_UINT32     id;           /* etcam号 */
-    ZXIC_UINT32     tbl_id;       /* 业务号 */
-    ZXIC_UINT32     *p_data;
-    ZXIC_UINT32     length;       /* 数据长度，以4字节为单位 */
-    ZXIC_UINT32     addr;
-    ZXIC_UINT32     wr_rd_flag;   /* 0: Write 1: Read */
-    ZXIC_UINT32     key_mode;
-    ZXIC_UINT32     rsp_mode;
-    ZXIC_UINT32     as_en;
-    ZXIC_UINT32     as_eram_baddr;
-    ZXIC_UINT32     as_rsp_mode;
+typedef struct dpp_sdt_etcam_t {
+	ZXIC_UINT32 id; /* etcam号 */
+	ZXIC_UINT32 tbl_id; /* 业务号 */
+	ZXIC_UINT32 *p_data;
+	ZXIC_UINT32 length; /* 数据长度，以4字节为单位 */
+	ZXIC_UINT32 addr;
+	ZXIC_UINT32 wr_rd_flag; /* 0: Write 1: Read */
+	ZXIC_UINT32 key_mode;
+	ZXIC_UINT32 rsp_mode;
+	ZXIC_UINT32 as_en;
+	ZXIC_UINT32 as_eram_baddr;
+	ZXIC_UINT32 as_rsp_mode;
 } DPP_SDT_ETCAM_T;
 
 #endif
-
-
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt_mgr.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt_mgr.h
old mode 100755
new mode 100644
index fa7f714fcde52a9b8b9c515c433a0e97485c275c..9cc873f486f4c06b39bec73596ffbe5113c9fc2a
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt_mgr.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/sdt/dpp_sdt_mgr.h
@@ -1,147 +1,150 @@
-/*********************************************************************
-* 版权所有 (C)2013, 深圳市中兴通讯股份有限公司。
-*
-* 文件名称：
-* 文件标识：
-* 内容摘要:
-* 其它说明:
-*
-*
-* 当前版本：
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT   : 100%
-* 作    者： 王春雷10111187
-* 完成日期： 2013-9-2
-********************************************************************/
-
-#ifndef _DPP_SDT_MGR_H_
-#define _DPP_SDT_MGR_H_
-
-#include "dpp_sdt_def.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define DPP_SDT_CFG_LEN         (2)
-
-#define DPP_SDT_VALID           (1)
-#define DPP_SDT_INVALID         (0)
-
-#define DPP_SDT_WRITE          (0)
-#define DPP_SDT_READ           (1)
-
-#define DPP_SDT_MAX_BUFF       (18)
-
-#define DPP_TBL_DATA_MAX       (50)
-
-typedef enum dpp_opr_type_e
-{
-    DPP_TABLE_UPDATE = 0,
-    DPP_TABLE_DELETE = 1,
-    DPP_TABLE_SEARCH = 2,
-} DPP_OPR_TYEP_E;
-
-/** eRam SDT变量获取中间结构 */
-typedef struct dpp_eram128_params_t
-{
-    ZXIC_UINT32              tbl_base_addr;     /** 表项基地址，128bit为单位         */
-    DPP_ERAM128_MODE_E  eram128_mode;      /** 表项位宽模式                     */
-    ZXIC_UINT32              tbl_depth;         /** 表项深度值。越界检测             */
-    ZXIC_UINT32              count;             /** 表示写入数据的长度，以32bit为单位*/
-} DPP_ERAM128_PARAMS_T;
-
-/** DDR3 SDT变量获取中间结构 */
-typedef struct dpp_ddr3_params_t
-{
-    ZXIC_UINT32          base_addr;             /** 表项基地址，以4K*128bit 为单位   */
-    ZXIC_UINT32          crc_check;             /** ECC校验使能位                     */
-    DPP_DDR3_MODE_E ddr3_mode;             /** DDR位宽模式                       */
-    ZXIC_UINT32          tbl_share_mode;        /** bank 共享模式                     */
-    ZXIC_UINT32          wr_rd_count;           /** 表示写入数据的长度，以32bit为单位 */
-} DPP_DDR3_PARAMS_T;
-
-typedef enum dpp_hash_key_width_e
-{
-    HashKey_Invalid = 0,
-    HashKey_128b,
-    HashKey_256b,
-    HashKey_512b,
-    HashKey_MAX
-} DPP_HASH_KEY_WIDTH_E;
-
-/** HASH SDT变量获取中间结构 */
-typedef struct dpp_hash_params_t
-{
-    ZXIC_UINT8      hash_id;              /** hash引擎号          */
-    ZXIC_UINT8      key_tbl_width;        /** hash表项存储位宽,   */
-    ZXIC_UINT8      key_size;             /** hash键值长度,以8bit为单位，1~48 */
-    ZXIC_UINT8      table_id;             /** hash逻辑表号        */
-    ZXIC_UINT8      rsp_mode;             /** 返回数据宽度    0:32  1:64  2:128  3:256*/
-} DPP_HASH_PARAMS_T;
-
-typedef struct dpp_lpm_params_t
-{
-    ZXIC_UINT8      v46_flag; /* 1:Ipv4, 0:Ipv6 */
-    ZXIC_UINT8      count;    /* 以4字节为单位  */
-    ZXIC_UINT8      pad[2];   /* 字节对齐       */
-} DPP_LPM_PARAMS_T;
-
-typedef struct dpp_etcam_params_t
-{
-    ZXIC_UINT8 id;
-    ZXIC_UINT8 table_id;
-    ZXIC_UINT8 key_mode;
-    ZXIC_UINT8 rsp_mode;
-    ZXIC_UINT8 as_en;
-    ZXIC_UINT32 as_baddr;
-    ZXIC_UINT8 as_rsp_mode;
-} DPP_ETCAM_PARAMS_T;
-
-typedef ZXIC_UINT32 (*dpp_sdt_mgr_smmu0_mux_fun_ptr)(ZXIC_UINT32 dev_id, DPP_SDT_SMMU0_T *p_sdt_smmu0);
-typedef ZXIC_UINT32 (*dpp_sdt_mgr_smmu1_mux_fun_ptr)(ZXIC_UINT32 dev_id, DPP_SDT_SMMU1_T *p_sdt_smmu1);
-typedef ZXIC_UINT32 (*dpp_sdt_mgr_hash_mux_fun_ptr)(ZXIC_UINT32  dev_id, DPP_SDT_HASH_T  *p_sdt_hash);
-typedef ZXIC_UINT32 (*dpp_sdt_mgr_lpm_mux_fun_ptr)(ZXIC_UINT32  dev_id,  DPP_SDT_LPM_T   *p_sdt_lpm);
-typedef ZXIC_UINT32 (*dpp_sdt_mgr_etcam_mux_fun_ptr)(ZXIC_UINT32  dev_id,  DPP_SDT_ETCAM_T   *p_sdt_etcam);
-
-typedef struct dpp_sdt_item_t
-{
-    ZXIC_UINT32     valid;
-    ZXIC_UINT32     table_cfg[DPP_SDT_CFG_LEN];
-} DPP_SDT_ITEM_T;
-
-typedef struct dpp_sdt_soft_table_t
-{
-    ZXIC_UINT32          device_id;
-    DPP_SDT_ITEM_T  sdt_array[DPP_DEV_SDT_ID_MAX];
-} DPP_SDT_SOFT_TABLE_T;
-
-typedef struct dpp_sdt_mgr_t
-{
-    ZXIC_UINT32          channel_num;
-    ZXIC_UINT32          is_init;
-    DPP_SDT_SOFT_TABLE_T* sdt_tbl_array[DPP_DEV_CHANNEL_MAX];
-    dpp_sdt_mgr_smmu0_mux_fun_ptr p_sdt_mgr_smmu0_mux;
-    dpp_sdt_mgr_smmu1_mux_fun_ptr p_sdt_mgr_smmu1_mux;
-    dpp_sdt_mgr_hash_mux_fun_ptr  p_sdt_mgr_hash_mux;
-    dpp_sdt_mgr_lpm_mux_fun_ptr   p_sdt_mgr_lpm_mux;
-    dpp_sdt_mgr_etcam_mux_fun_ptr p_sdt_mgr_etcam_mux;
-} DPP_SDT_MGR_T;
-
-ZXIC_UINT32 dpp_sdt_mgr_init(ZXIC_VOID);
-ZXIC_UINT32 dpp_sdt_mgr_create(ZXIC_UINT32 dev_id);
-ZXIC_UINT32 dpp_sdt_mgr_destroy(ZXIC_UINT32 dev_id);
-
-DPP_STATUS dpp_sdt_mgr_sdt_item_add(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, ZXIC_UINT32 sdt_hig32, ZXIC_UINT32 sdt_low32);
-DPP_STATUS dpp_sdt_mgr_sdt_item_srh(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, ZXIC_UINT32 *p_sdt_hig32, ZXIC_UINT32 *p_sdt_low32);
-DPP_STATUS dpp_sdt_mgr_sdt_item_del(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no);
-
-ZXIC_UINT32 dpp_sdt_mgr_get_as_table_en(ZXIC_UINT32 *table_cfg, ZXIC_UINT32 *p_as_en);
-ZXIC_UINT32 dpp_sdt_mgr_get_as_table_type(ZXIC_UINT32 *table_cfg, DPP_TBL_TYPE_E *p_as_type);
-ZXIC_UINT32 dpp_sdt_mgr_get_ddr3_page(ZXIC_UINT32 copy_type, ZXIC_UINT32 copy_position, ZXIC_UINT32 *p_page);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/*********************************************************************
+ * 版权所有 (C)2013, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：
+ * 文件标识：
+ * 内容摘要:
+ * 其它说明:
+ *
+ *
+ * 当前版本：
+ * DEPARTMENT: ASIC_FPGA_R&D_Dept
+ * MANUAL_PERCENT   : 100%
+ * 作    者： 王春雷10111187
+ * 完成日期： 2013-9-2
+ ********************************************************************/
+
+#ifndef _DPP_SDT_MGR_H_
+#define _DPP_SDT_MGR_H_
+
+#include "dpp_sdt_def.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DPP_SDT_CFG_LEN (2)
+
+#define DPP_SDT_VALID (1)
+#define DPP_SDT_INVALID (0)
+
+#define DPP_SDT_WRITE (0)
+#define DPP_SDT_READ (1)
+
+#define DPP_SDT_MAX_BUFF (18)
+
+#define DPP_TBL_DATA_MAX (50)
+
+typedef enum dpp_opr_type_e {
+	DPP_TABLE_UPDATE = 0,
+	DPP_TABLE_DELETE = 1,
+	DPP_TABLE_SEARCH = 2,
+} DPP_OPR_TYEP_E;
+
+/** eRam SDT变量获取中间结构 */
+typedef struct dpp_eram128_params_t {
+	ZXIC_UINT32 tbl_base_addr; /** 表项基地址，128bit为单位         */
+	DPP_ERAM128_MODE_E eram128_mode; /** 表项位宽模式                     */
+	ZXIC_UINT32 tbl_depth; /** 表项深度值。越界检测             */
+	ZXIC_UINT32 count; /** 表示写入数据的长度，以32bit为单位*/
+} DPP_ERAM128_PARAMS_T;
+
+/** DDR3 SDT变量获取中间结构 */
+typedef struct dpp_ddr3_params_t {
+	ZXIC_UINT32 base_addr; /** 表项基地址，以4K*128bit 为单位   */
+	ZXIC_UINT32 crc_check; /** ECC校验使能位                     */
+	DPP_DDR3_MODE_E ddr3_mode; /** DDR位宽模式                       */
+	ZXIC_UINT32 tbl_share_mode; /** bank 共享模式                     */
+	ZXIC_UINT32 wr_rd_count; /** 表示写入数据的长度，以32bit为单位 */
+} DPP_DDR3_PARAMS_T;
+
+typedef enum dpp_hash_key_width_e {
+	HashKey_Invalid = 0,
+	HashKey_128b,
+	HashKey_256b,
+	HashKey_512b,
+	HashKey_MAX
+} DPP_HASH_KEY_WIDTH_E;
+
+/** HASH SDT变量获取中间结构 */
+typedef struct dpp_hash_params_t {
+	ZXIC_UINT8 hash_id; /** hash引擎号          */
+	ZXIC_UINT8 key_tbl_width; /** hash表项存储位宽,   */
+	ZXIC_UINT8 key_size; /** hash键值长度,以8bit为单位，1~48 */
+	ZXIC_UINT8 table_id; /** hash逻辑表号        */
+	ZXIC_UINT8 rsp_mode; /** 返回数据宽度    0:32  1:64  2:128  3:256*/
+} DPP_HASH_PARAMS_T;
+
+typedef struct dpp_lpm_params_t {
+	ZXIC_UINT8 v46_flag; /* 1:Ipv4, 0:Ipv6 */
+	ZXIC_UINT8 count; /* 以4字节为单位  */
+	ZXIC_UINT8 pad[2]; /* 字节对齐       */
+} DPP_LPM_PARAMS_T;
+
+typedef struct dpp_etcam_params_t {
+	ZXIC_UINT8 id;
+	ZXIC_UINT8 table_id;
+	ZXIC_UINT8 key_mode;
+	ZXIC_UINT8 rsp_mode;
+	ZXIC_UINT8 as_en;
+	ZXIC_UINT32 as_baddr;
+	ZXIC_UINT8 as_rsp_mode;
+} DPP_ETCAM_PARAMS_T;
+
+typedef ZXIC_UINT32 (*dpp_sdt_mgr_smmu0_mux_fun_ptr)(
+		ZXIC_UINT32 dev_id, DPP_SDT_SMMU0_T *p_sdt_smmu0);
+typedef ZXIC_UINT32 (*dpp_sdt_mgr_smmu1_mux_fun_ptr)(
+		ZXIC_UINT32 dev_id, DPP_SDT_SMMU1_T *p_sdt_smmu1);
+typedef ZXIC_UINT32 (*dpp_sdt_mgr_hash_mux_fun_ptr)(ZXIC_UINT32 dev_id,
+													DPP_SDT_HASH_T *p_sdt_hash);
+typedef ZXIC_UINT32 (*dpp_sdt_mgr_lpm_mux_fun_ptr)(ZXIC_UINT32 dev_id,
+												   DPP_SDT_LPM_T *p_sdt_lpm);
+typedef ZXIC_UINT32 (*dpp_sdt_mgr_etcam_mux_fun_ptr)(
+		ZXIC_UINT32 dev_id, DPP_SDT_ETCAM_T *p_sdt_etcam);
+
+typedef struct dpp_sdt_item_t {
+	ZXIC_UINT32 valid;
+	ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN];
+} DPP_SDT_ITEM_T;
+
+typedef struct dpp_sdt_soft_table_t {
+	ZXIC_UINT32 device_id;
+	DPP_SDT_ITEM_T sdt_array[DPP_DEV_SDT_ID_MAX];
+} DPP_SDT_SOFT_TABLE_T;
+
+typedef struct dpp_sdt_mgr_t {
+	ZXIC_UINT32 channel_num;
+	ZXIC_UINT32 is_init;
+	DPP_SDT_SOFT_TABLE_T * sdt_tbl_array[DPP_DEV_CHANNEL_MAX];
+	dpp_sdt_mgr_smmu0_mux_fun_ptr p_sdt_mgr_smmu0_mux;
+	dpp_sdt_mgr_smmu1_mux_fun_ptr p_sdt_mgr_smmu1_mux;
+	dpp_sdt_mgr_hash_mux_fun_ptr p_sdt_mgr_hash_mux;
+	dpp_sdt_mgr_lpm_mux_fun_ptr p_sdt_mgr_lpm_mux;
+	dpp_sdt_mgr_etcam_mux_fun_ptr p_sdt_mgr_etcam_mux;
+} DPP_SDT_MGR_T;
+
+ZXIC_UINT32 dpp_sdt_mgr_init(ZXIC_VOID);
+ZXIC_UINT32 dpp_sdt_mgr_create(ZXIC_UINT32 dev_id);
+ZXIC_UINT32 dpp_sdt_mgr_destroy(ZXIC_UINT32 dev_id);
+
+DPP_STATUS dpp_sdt_mgr_sdt_item_add(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no,
+									ZXIC_UINT32 sdt_hig32,
+									ZXIC_UINT32 sdt_low32);
+DPP_STATUS dpp_sdt_mgr_sdt_item_srh(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no,
+									ZXIC_UINT32 *p_sdt_hig32,
+									ZXIC_UINT32 *p_sdt_low32);
+DPP_STATUS dpp_sdt_mgr_sdt_item_del(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no);
+
+ZXIC_UINT32 dpp_sdt_mgr_get_as_table_en(ZXIC_UINT32 *table_cfg,
+										ZXIC_UINT32 *p_as_en);
+ZXIC_UINT32 dpp_sdt_mgr_get_as_table_type(ZXIC_UINT32 *table_cfg,
+										  DPP_TBL_TYPE_E *p_as_type);
+ZXIC_UINT32 dpp_sdt_mgr_get_ddr3_page(ZXIC_UINT32 copy_type,
+									  ZXIC_UINT32 copy_position,
+									  ZXIC_UINT32 *p_page);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_acl.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_acl.h
old mode 100755
new mode 100644
index b8ae6727131cf562613d25d1a8dda6ab4abc2534..9eb0fce9133a9869a702fb084fec1f9b46a1bcb0
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_acl.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_acl.h
@@ -1,103 +1,103 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_acl.h
-* 文件标识 : 
-* 内容摘要 : 
-* 其它说明 : 
-* 当前版本 : 
-* 作    者 : 王春雷
-* 完成日期 : 2014/12/17
-* DEPARTMENT: ASIC_FPGA_R&D_Dept 
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* 版 本 号:  
-* 修 改 人:  
-* 修改内容:  
-***************************************************************/
-#ifndef _DPP_ACL_H_
-#define _DPP_ACL_H_
-
-#include "dpp_se_api.h"
-
-#define DPP_ACL_TBL_ID_MIN      (0)
-#define DPP_ACL_TBL_ID_MAX      (7)
-#define DPP_ACL_ETCAM_ID_MIN    (0)
-#define DPP_ACL_ETCAM_ID_MAX    (0)
-
-#define DPP_ACL_ENTRY_MAX_GET(key_mode, block_num) \
-    ((block_num) * DPP_ETCAM_RAM_DEPTH * (1U<<(key_mode)))
-
-#define DPP_ACL_AS_RSLT_SIZE_GET(mode) \
-    (((mode)==DPP_ACL_AS_MODE_128b)?(128/8):(((mode)==DPP_ACL_AS_MODE_64b)?(64/8):(((mode)==DPP_ACL_AS_MODE_32b)?\
-    (32/8):(((mode)==DPP_ACL_AS_MODE_16b)?(16/8):(0)))))
-
-/** 仅内部调试接口使用*/
-#define DPP_ACL_AS_RSLT_SIZE_GET_EX(mode) (2U<<(mode))
-
-
-/**  ACL关联查找结果表位宽模式，仅调试用*/
-typedef enum dpp_acl_as_mode_ex_e
-{
-    DPP_ACL_AS_MODE_EX_64b  = 1,  /**<  @brief 64bit结果位宽*/
-    DPP_ACL_AS_MODE_EX_128b = 2,  /**<  @brief 128bit结果位宽*/
-    DPP_ACL_AS_MODE_EX_256b = 3,  /**<  @brief 256bit结果位宽，仅当关联结果表为DDR时有效*/
-    DPP_ACL_AS_MODE_EX_INVALID,
-}DPP_ACL_AS_MODE_EX_E;
-
-/***********************************************************/
-/** 初始化ACL公共管理数据结构
-* @param   p_acl_cfg     ACL公共管理数据结构指针
-* @param   p_client      用户自定义数据指针，目前仅为传入dev_id的值
-* @param   flags         ACL初始化使能标志，详见DPP_ACL_FLAG_ETCAM0_EN等的定义
-* @param   p_as_wrt_fun  关联结果G从布s表回调函数指针
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wcl      @date  2015/05/20
-************************************************************/
-DPP_STATUS dpp_acl_cfg_init(DPP_ACL_CFG_T *p_acl_cfg,
-                            ZXIC_VOID *p_client,
-                            ZXIC_UINT32 flags,
-                            ACL_AS_RSLT_WRT_FUNCTION p_as_wrt_fun);
-
-/***********************************************************/
-/** 获取ACL公共管理数据结构
-* @param   p_acl_cfg     ACL公共管理配置结构指针
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-************************************************************/
-DPP_STATUS dpp_acl_cfg_get(DPP_ACL_CFG_EX_T **p_acl_cfg);
-
-/***********************************************************/
-/** 初始化ACL业务表属G?
-* @param   p_acl_cfg   ACL公共管理数据结构指针
-* @param   table_id    业务表号，取值范围0~15
-* @param   as_enable   是否使能关联结果查找，0-不使能，1-使能
-* @param   entry_num   最大条目数
-* @param   key_mode    键值位宽模式，取值参照DPP_ACL_KEY_MODE_E的定义
-* @param   as_mode     关联结果位宽模式，取值参照DPP_ACL_AS_MODE_E的定义
-* @param   block_num   分配给当前业务表号的block数目
-* @param   p_block_idx 分配给当前业务表号的block编号数组
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wcl      @date  2015/05/20
-************************************************************/
-DPP_STATUS dpp_acl_tbl_init(DPP_ACL_CFG_T *p_acl_cfg,
-                            ZXIC_UINT32 table_id,
-                            ZXIC_UINT32 as_enable,
-                            ZXIC_UINT32 entry_num,
-                            DPP_ACL_KEY_MODE_E key_mode,
-                            DPP_ACL_AS_MODE_E  as_mode,
-                            ZXIC_UINT32 block_num,
-                            ZXIC_UINT32 *p_block_idx);
-
-DPP_STATUS dpp_acl_hdw_addr_get(DPP_ACL_TBL_CFG_T *p_tbl_cfg, ZXIC_UINT32 handle, ZXIC_UINT32 *p_block_idx, ZXIC_UINT32 *p_addr, ZXIC_UINT32 *p_wr_mask);
-#endif
-
-
-
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_acl.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2014/12/17
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#ifndef _DPP_ACL_H_
+#define _DPP_ACL_H_
+
+#include "dpp_se_api.h"
+
+#define DPP_ACL_TBL_ID_MIN (0)
+#define DPP_ACL_TBL_ID_MAX (7)
+#define DPP_ACL_ETCAM_ID_MIN (0)
+#define DPP_ACL_ETCAM_ID_MAX (0)
+
+#define DPP_ACL_ENTRY_MAX_GET(key_mode, block_num) \
+	((block_num)*DPP_ETCAM_RAM_DEPTH * (1U << (key_mode)))
+
+#define DPP_ACL_AS_RSLT_SIZE_GET(mode)                                       \
+	(((mode) == DPP_ACL_AS_MODE_128b) ?                                      \
+			   (128 / 8) :                                                     \
+			   (((mode) == DPP_ACL_AS_MODE_64b) ?                              \
+						(64 / 8) :                                             \
+						(((mode) == DPP_ACL_AS_MODE_32b) ?                     \
+								 (32 / 8) :                                    \
+								 (((mode) == DPP_ACL_AS_MODE_16b) ? (16 / 8) : \
+																	(0)))))
+
+/** 仅内部调试接口使用*/
+#define DPP_ACL_AS_RSLT_SIZE_GET_EX(mode) (2U << (mode))
+
+/**  ACL关联查找结果表位宽模式，仅调试用*/
+typedef enum dpp_acl_as_mode_ex_e {
+	DPP_ACL_AS_MODE_EX_64b = 1, /**<  @brief 64bit结果位宽*/
+	DPP_ACL_AS_MODE_EX_128b = 2, /**<  @brief 128bit结果位宽*/
+	DPP_ACL_AS_MODE_EX_256b =
+			3, /**<  @brief 256bit结果位宽，仅当关联结果表为DDR时有效*/
+	DPP_ACL_AS_MODE_EX_INVALID,
+} DPP_ACL_AS_MODE_EX_E;
+
+/***********************************************************/
+/** 初始化ACL公共管理数据结构
+ * @param   p_acl_cfg     ACL公共管理数据结构指针
+ * @param   p_client      用户自定义数据指针，目前仅为传入dev_id的值
+ * @param   flags         ACL初始化使能标志，详见DPP_ACL_FLAG_ETCAM0_EN等的定义
+ * @param   p_as_wrt_fun  关联结果G从布s表回调函数指针
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/05/20
+ ************************************************************/
+DPP_STATUS dpp_acl_cfg_init(DPP_ACL_CFG_T *p_acl_cfg, ZXIC_VOID *p_client,
+							ZXIC_UINT32 flags,
+							ACL_AS_RSLT_WRT_FUNCTION p_as_wrt_fun);
+
+/***********************************************************/
+/** 获取ACL公共管理数据结构
+ * @param   p_acl_cfg     ACL公共管理配置结构指针
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ ************************************************************/
+DPP_STATUS dpp_acl_cfg_get(DPP_ACL_CFG_EX_T **p_acl_cfg);
+
+/***********************************************************/
+/** 初始化ACL业务表属G?
+ * @param   p_acl_cfg   ACL公共管理数据结构指针
+ * @param   table_id    业务表号，取值范围0~15
+ * @param   as_enable   是否使能关联结果查找，0-不使能，1-使能
+ * @param   entry_num   最大条目数
+ * @param   key_mode    键值位宽模式，取值参照DPP_ACL_KEY_MODE_E的定义
+ * @param   as_mode     关联结果位宽模式，取值参照DPP_ACL_AS_MODE_E的定义
+ * @param   block_num   分配给当前业务表号的block数目
+ * @param   p_block_idx 分配给当前业务表号的block编号数组
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/05/20
+ ************************************************************/
+DPP_STATUS dpp_acl_tbl_init(DPP_ACL_CFG_T *p_acl_cfg, ZXIC_UINT32 table_id,
+							ZXIC_UINT32 as_enable, ZXIC_UINT32 entry_num,
+							DPP_ACL_KEY_MODE_E key_mode,
+							DPP_ACL_AS_MODE_E as_mode, ZXIC_UINT32 block_num,
+							ZXIC_UINT32 *p_block_idx);
+
+DPP_STATUS dpp_acl_hdw_addr_get(DPP_ACL_TBL_CFG_T *p_tbl_cfg,
+								ZXIC_UINT32 handle, ZXIC_UINT32 *p_block_idx,
+								ZXIC_UINT32 *p_addr, ZXIC_UINT32 *p_wr_mask);
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_dtb_table.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_dtb_table.h
index e5f4ac1049b9b58bd382f0fad23c10ab3219918f..b4af18d54fb59e090f23369fe45b1c62ae7990f4 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_dtb_table.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_dtb_table.h
@@ -2,7 +2,7 @@
 #define _DPP_DTB_TABLE_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
 #include "dpp_dev.h"
@@ -18,9 +18,9 @@ extern "C"{
 
 #define DTB_QUEUE_MAX (128)
 #define DTB_QUEUE_ELEMENT_MAX (32)
-#define DTB_DATA_SIZE_BIT (16*1024*8)
-#define DPP_DTB_TABLE_DATA_BUFF_SIZE (1024*16)
-#define DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE (1024*4)
+#define DTB_DATA_SIZE_BIT (16 * 1024 * 8)
+#define DPP_DTB_TABLE_DATA_BUFF_SIZE (1024 * 16)
+#define DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE (1024 * 4)
 #define DTB_TABLE_CMD_SIZE_BIT (128)
 #define DTB_TABLE_CMD_SIZE_BYTE (16)
 #define DTB_ERAM_DATA_SIZE_1b (128)
@@ -28,17 +28,18 @@ extern "C"{
 #define DTB_ERAM_DATA_SIZE_128b (256)
 #define DTB_ERAM_ENTRY_CNT_MAX_1b (DTB_DATA_SIZE_BIT / DTB_ERAM_DATA_SIZE_1b)
 #define DTB_ERAM_ENTRY_CNT_MAX_64b (DTB_DATA_SIZE_BIT / DTB_ERAM_DATA_SIZE_64b)
-#define DTB_ERAM_ENTRY_CNT_MAX_128b (DTB_DATA_SIZE_BIT / DTB_ERAM_DATA_SIZE_128b)
+#define DTB_ERAM_ENTRY_CNT_MAX_128b \
+	(DTB_DATA_SIZE_BIT / DTB_ERAM_DATA_SIZE_128b)
 #define DTB_ZCAM_LEN_SIZE (5) /*单位16字节*/
 #define DTB_ETCAM_LEN_SIZE (6) /*单位16字节*/
 #define DTB_MC_HASH_LEN_SIZE (5) /*单位16字节*/
-#define DTB_ZCAM_DATA_SIZE   (ZXIC_UINT32)(64)
-#define DTB_DMUP_DATA_MAX    (ZXIC_UINT32)(4*1024*1024)
+#define DTB_ZCAM_DATA_SIZE ((ZXIC_UINT32)(64))
+#define DTB_DMUP_DATA_MAX ((ZXIC_UINT32)(4 * 1024 * 1024))
 #define DTB_DUMP_DDR_ITEMS_MAX (0x10000)
 
-#define DTB_SDT_DUMP_SIZE (0x400000) //4MB
+#define DTB_SDT_DUMP_SIZE (0x400000) // 4MB
 
-#define DTB_TABLE_VALID  (1)
+#define DTB_TABLE_VALID (1)
 #define DTB_LEN_POS_SETP (16) /*DTB len 单位16字节 */
 
 #define LPM_IPV4 (1)
@@ -53,7 +54,7 @@ extern "C"{
 #define DTB_TABLE_MODE_MC_HASH (4)
 
 #define DTB_DUMP_MODE_ERAM (0)
-#define DTB_DUMP_MODE_DDR  (1)
+#define DTB_DUMP_MODE_DDR (1)
 #define DTB_DUMP_MODE_ZCAM (2)
 #define DTB_DUMP_MODE_ETCAM (3)
 
@@ -62,656 +63,605 @@ extern "C"{
 
 /* DTB 表信息管理 */
 /*表顺序与g_dpp_dtb_table_info中顺序一致*/
-typedef enum dpp_dtb_table_info_e
-{
-    DTB_TABLE_DDR  			= 0,
-    DTB_TABLE_ERAM_1 		= 1,
-	DTB_TABLE_ERAM_64 	    = 2,
-	DTB_TABLE_ERAM_128      = 3,
-    DTB_TABLE_ZCAM 			= 4,
-    DTB_TABLE_ETCAM 		= 5,
-    DTB_TABLE_MC_HASH 	    = 6,
+typedef enum dpp_dtb_table_info_e {
+	DTB_TABLE_DDR = 0,
+	DTB_TABLE_ERAM_1 = 1,
+	DTB_TABLE_ERAM_64 = 2,
+	DTB_TABLE_ERAM_128 = 3,
+	DTB_TABLE_ZCAM = 4,
+	DTB_TABLE_ETCAM = 5,
+	DTB_TABLE_MC_HASH = 6,
 	DTB_TABLE_ENUM_MAX
-}DPP_DTB_TABLE_INFO_E;
-
-typedef enum dpp_dtb_dump_info_e
-{
-    DTB_DUMP_ERAM = 0,
-    DTB_DUMP_DDR  = 1,
-    DTB_DUMP_ZCAM = 2,
-    DTB_DUMP_ETCAM = 3,
+} DPP_DTB_TABLE_INFO_E;
+
+typedef enum dpp_dtb_dump_info_e {
+	DTB_DUMP_ERAM = 0,
+	DTB_DUMP_DDR = 1,
+	DTB_DUMP_ZCAM = 2,
+	DTB_DUMP_ETCAM = 3,
 	DTB_DUMP_ENUM_MAX
-}DPP_DTB_DUMP_INFO_E;
-
-typedef enum dpp_dtb_dump_zcam_width_e
-{
-    DTB_DUMP_ZCAM_128b = 0,
-    DTB_DUMP_ZCAM_256b = 1,
-    DTB_DUMP_ZCAM_512b = 2,
-	DTB_DUMP_ZCAM_RSV  = 3,
-}DPP_DTB_DUMP_ZCAM_WIDTH_E;
-
-typedef enum dpp_dtb_dump_etcam_width_e
-{
-    DTB_DUMP_ETCAM_80b = 0,
-    DTB_DUMP_ETCAM_160b = 1,
-    DTB_DUMP_ETCAM_320b = 2,
-	DTB_DUMP_ETCAM_640b  = 3,
+} DPP_DTB_DUMP_INFO_E;
+
+typedef enum dpp_dtb_dump_zcam_width_e {
+	DTB_DUMP_ZCAM_128b = 0,
+	DTB_DUMP_ZCAM_256b = 1,
+	DTB_DUMP_ZCAM_512b = 2,
+	DTB_DUMP_ZCAM_RSV = 3,
+} DPP_DTB_DUMP_ZCAM_WIDTH_E;
+
+typedef enum dpp_dtb_dump_etcam_width_e {
+	DTB_DUMP_ETCAM_80b = 0,
+	DTB_DUMP_ETCAM_160b = 1,
+	DTB_DUMP_ETCAM_320b = 2,
+	DTB_DUMP_ETCAM_640b = 3,
 	DTB_DUMP_ETCAM_MAX
-}DPP_DTB_DUMP_ETCAM_WIDTH_E;
+} DPP_DTB_DUMP_ETCAM_WIDTH_E;
 
 /* DTB下表格式字段定义 */
-typedef struct dpp_dtb_ddr_table_form_t
-{
-	ZXIC_UINT32 valid;       /* 有效标识 1有效*/
-	ZXIC_UINT32 type_mode;   /* DDR：0x1 */
-    ZXIC_UINT32 rw_len;      /*数据长度 00:128  01:256  10:384  11:512*/
-    ZXIC_UINT32 v46_flag;    /*1：IPV4  0:IPV6*/
-    ZXIC_UINT32 lpm_wr_vld;  /*lpm表写有效标识*/
-    ZXIC_UINT32 baddr;       /*表基地址*/
-    ZXIC_UINT32 ecc_en;      /* ECC 使能*/
-    ZXIC_UINT32 rw_addr;     /*以数据宽度为单位的index*/
-}DPP_DTB_DDR_TABLE_FORM_T;
-
-typedef struct dpp_dtb_eram_table_form_t
-{
-	ZXIC_UINT32 valid;        /* 有效标识 1有效*/
-	ZXIC_UINT32 type_mode;    /* ERAM：0x0 */
-	ZXIC_UINT32 data_mode;    /*数据长度 00:128  01:64  10:1*/
-	ZXIC_UINT32 cpu_wr;       /*CPU写使能*/
-	ZXIC_UINT32 cpu_rd;       /*CPU读使能*/
-	ZXIC_UINT32 cpu_rd_mode;  /*CPU读模式 0：读 1：读清*/
-	ZXIC_UINT32 addr;         /*访问eram 1bit为单位*/
-	ZXIC_UINT32 data_h;       /*数据高32bit*/
-	ZXIC_UINT32 data_l;       /*数据低32bit*/
-}DPP_DTB_ERAM_TABLE_FORM_T;
-
-typedef struct dpp_dtb_zcam_table_form_t
-{
-    ZXIC_UINT32 valid;         /* 有效标识 1有效*/
-    ZXIC_UINT32 type_mode;     /* zcam：0x2 */
-    ZXIC_UINT32 ram_reg_flag;  /* ram reg 标识 */
-    ZXIC_UINT32 zgroup_id;     /* zgroup id */
-    ZXIC_UINT32 zblock_id;     /* zblock id */
-    ZXIC_UINT32 zcell_id;      /* zcell id */
-    ZXIC_UINT32 mask;          /* 掩码 */
-    ZXIC_UINT32 sram_addr;     /* ram地址 */
-
-}DPP_DTB_ZCAM_TABLE_FORM_T;
-
-typedef struct dpp_dtb_etcam_table_form_t
-{
-	ZXIC_UINT32 valid;             /* 有效标识 1有效*/
-	ZXIC_UINT32 type_mode;         /* etcam：0x3 */
-	ZXIC_UINT32 block_sel;         /*block索引 0 - 7*/
-	ZXIC_UINT32 init_en;           /*初始化使能 高有效*/
-	ZXIC_UINT32 row_or_col_msk;    /* 1 write row mask reg  0:write col mask reg*/
-	ZXIC_UINT32 vben;              /* enable the valid bit addressed by addr*/
-	ZXIC_UINT32 reg_tcam_flag;     /* 1:配置内部row_col_mask寄存器 0：读写tcam*/
-	ZXIC_UINT32 uload;             /*使能标识删除对应addr的表项条目，（80bit为单位，含义与wr_mode一一对应）*/
-	ZXIC_UINT32 rd_wr;             /*读写标志 0写 1读*/
-	ZXIC_UINT32 wr_mode;           /*写入掩码，最高8bit，对应bit为1代表对应的80bit的数据*/
-	ZXIC_UINT32 data_or_mask;      /*数据或掩码标志 1：写x(data),0:写y(mask)*/
-	ZXIC_UINT32 addr;              /*etcam地址（0-511）*/
-	ZXIC_UINT32 vbit;              /*valid bit input*/
-
-}DPP_DTB_ETCAM_TABLE_FORM_T;
-
-typedef struct dpp_dtb_mc_hash_table_form_t
-{
-	ZXIC_UINT32 valid;              /* 有效标识 1有效  */
-	ZXIC_UINT32 type_mode;          /* 微码写hash 0x4 */
-    ZXIC_UINT32 std_h;              /* sdt信息高32bit */
-	ZXIC_UINT32 std_l;              /* sdt信息低32bit */
-}DPP_DTB_MC_HASH_TABLE_FORM_T;
+typedef struct dpp_dtb_ddr_table_form_t {
+	ZXIC_UINT32 valid; /* 有效标识 1有效*/
+	ZXIC_UINT32 type_mode; /* DDR：0x1 */
+	ZXIC_UINT32 rw_len; /*数据长度 00:128  01:256  10:384  11:512*/
+	ZXIC_UINT32 v46_flag; /*1：IPV4  0:IPV6*/
+	ZXIC_UINT32 lpm_wr_vld; /*lpm表写有效标识*/
+	ZXIC_UINT32 baddr; /*表基地址*/
+	ZXIC_UINT32 ecc_en; /* ECC 使能*/
+	ZXIC_UINT32 rw_addr; /*以数据宽度为单位的index*/
+} DPP_DTB_DDR_TABLE_FORM_T;
+
+typedef struct dpp_dtb_eram_table_form_t {
+	ZXIC_UINT32 valid; /* 有效标识 1有效*/
+	ZXIC_UINT32 type_mode; /* ERAM：0x0 */
+	ZXIC_UINT32 data_mode; /*数据长度 00:128  01:64  10:1*/
+	ZXIC_UINT32 cpu_wr; /*CPU写使能*/
+	ZXIC_UINT32 cpu_rd; /*CPU读使能*/
+	ZXIC_UINT32 cpu_rd_mode; /*CPU读模式 0：读 1：读清*/
+	ZXIC_UINT32 addr; /*访问eram 1bit为单位*/
+	ZXIC_UINT32 data_h; /*数据高32bit*/
+	ZXIC_UINT32 data_l; /*数据低32bit*/
+} DPP_DTB_ERAM_TABLE_FORM_T;
+
+typedef struct dpp_dtb_zcam_table_form_t {
+	ZXIC_UINT32 valid; /* 有效标识 1有效*/
+	ZXIC_UINT32 type_mode; /* zcam：0x2 */
+	ZXIC_UINT32 ram_reg_flag; /* ram reg 标识 */
+	ZXIC_UINT32 zgroup_id; /* zgroup id */
+	ZXIC_UINT32 zblock_id; /* zblock id */
+	ZXIC_UINT32 zcell_id; /* zcell id */
+	ZXIC_UINT32 mask; /* 掩码 */
+	ZXIC_UINT32 sram_addr; /* ram地址 */
+
+} DPP_DTB_ZCAM_TABLE_FORM_T;
+
+typedef struct dpp_dtb_etcam_table_form_t {
+	ZXIC_UINT32 valid; /* 有效标识 1有效*/
+	ZXIC_UINT32 type_mode; /* etcam：0x3 */
+	ZXIC_UINT32 block_sel; /*block索引 0 - 7*/
+	ZXIC_UINT32 init_en; /*初始化使能 高有效*/
+	ZXIC_UINT32 row_or_col_msk; /* 1 write row mask reg  0:write col mask reg*/
+	ZXIC_UINT32 vben; /* enable the valid bit addressed by addr*/
+	ZXIC_UINT32 reg_tcam_flag; /* 1:配置内部row_col_mask寄存器 0：读写tcam*/
+	ZXIC_UINT32
+	uload; /*使能标识删除对应addr的表项条目，（80bit为单位，含义与wr_mode一一对应）*/
+	ZXIC_UINT32 rd_wr; /*读写标志 0写 1读*/
+	ZXIC_UINT32 wr_mode; /*写入掩码，最高8bit，对应bit为1代表对应的80bit的数据*/
+	ZXIC_UINT32 data_or_mask; /*数据或掩码标志 1：写x(data),0:写y(mask)*/
+	ZXIC_UINT32 addr; /*etcam地址（0-511）*/
+	ZXIC_UINT32 vbit; /*valid bit input*/
+
+} DPP_DTB_ETCAM_TABLE_FORM_T;
+
+typedef struct dpp_dtb_mc_hash_table_form_t {
+	ZXIC_UINT32 valid; /* 有效标识 1有效  */
+	ZXIC_UINT32 type_mode; /* 微码写hash 0x4 */
+	ZXIC_UINT32 std_h; /* sdt信息高32bit */
+	ZXIC_UINT32 std_l; /* sdt信息低32bit */
+} DPP_DTB_MC_HASH_TABLE_FORM_T;
 
 /* DTB DUMP表格式 */
-typedef struct dpp_dtb_eram_dump_form_t
-{
-	ZXIC_UINT32 valid;              /* 有效标识 1有效 */
-	ZXIC_UINT32 up_type;            /* 00:eram */
-	ZXIC_UINT32 base_addr;          /* 128bit为单位 */
-	ZXIC_UINT32 tb_depth;           /* 表项深度，每条条目位宽128bit */
-	ZXIC_UINT32 tb_dst_addr_h;      /* 数据目的地址高32bit */
-	ZXIC_UINT32 tb_dst_addr_l;      /* 数据目的地址低32bit */
-
-}DPP_DTB_ERAM_DUMP_FORM_T;
-
-typedef struct dpp_dtb_ddr_dump_form_t
-{
+typedef struct dpp_dtb_eram_dump_form_t {
+	ZXIC_UINT32 valid; /* 有效标识 1有效 */
+	ZXIC_UINT32 up_type; /* 00:eram */
+	ZXIC_UINT32 base_addr; /* 128bit为单位 */
+	ZXIC_UINT32 tb_depth; /* 表项深度，每条条目位宽128bit */
+	ZXIC_UINT32 tb_dst_addr_h; /* 数据目的地址高32bit */
+	ZXIC_UINT32 tb_dst_addr_l; /* 数据目的地址低32bit */
+
+} DPP_DTB_ERAM_DUMP_FORM_T;
+
+typedef struct dpp_dtb_ddr_dump_form_t {
 	ZXIC_UINT32 valid;
-	ZXIC_UINT32 up_type;            /* 01:ddr */
-	ZXIC_UINT32 base_addr;          /* 128bit为单位 */
-	ZXIC_UINT32 tb_depth;        /* 表项深度，每条条目位宽512bit */
+	ZXIC_UINT32 up_type; /* 01:ddr */
+	ZXIC_UINT32 base_addr; /* 128bit为单位 */
+	ZXIC_UINT32 tb_depth; /* 表项深度，每条条目位宽512bit */
 	ZXIC_UINT32 tb_dst_addr_h;
 	ZXIC_UINT32 tb_dst_addr_l;
 
-}DPP_DTB_DDR_DUMP_FORM_T;
+} DPP_DTB_DDR_DUMP_FORM_T;
 
-typedef struct dpp_dtb_zcam_dump_form_t
-{
+typedef struct dpp_dtb_zcam_dump_form_t {
 	ZXIC_UINT32 valid;
-	ZXIC_UINT32 up_type;            /* 10:zcam */
-	ZXIC_UINT32 zgroup_id;          /*  */
-	ZXIC_UINT32 zblock_id;          /*  */
+	ZXIC_UINT32 up_type; /* 10:zcam */
+	ZXIC_UINT32 zgroup_id; /*  */
+	ZXIC_UINT32 zblock_id; /*  */
 	ZXIC_UINT32 ram_reg_flag;
 	ZXIC_UINT32 z_reg_cell_id;
 	ZXIC_UINT32 sram_addr;
-	ZXIC_UINT32 tb_depth;        /* 表项深度 */
-	ZXIC_UINT32 tb_width;        /* 表项宽度 */
+	ZXIC_UINT32 tb_depth; /* 表项深度 */
+	ZXIC_UINT32 tb_width; /* 表项宽度 */
 	ZXIC_UINT32 tb_dst_addr_h;
 	ZXIC_UINT32 tb_dst_addr_l;
 
-
-}DPP_DTB_ZCAM_DUMP_FORM_T;
-typedef struct dpp_dtb_etcam_dump_form_t
-{
+} DPP_DTB_ZCAM_DUMP_FORM_T;
+typedef struct dpp_dtb_etcam_dump_form_t {
 	ZXIC_UINT32 valid;
-	ZXIC_UINT32 up_type;         /* 11:etcam */
-	ZXIC_UINT32 block_sel;       /* block num */
-	ZXIC_UINT32 addr;            /* 640bit位单位 */
-	ZXIC_UINT32 rd_mode;         /* 读模式，共8bit，每bit控制ram中对应位置的80bit数据是否有效*/ 
-	ZXIC_UINT32 data_or_mask;    /* data：1 mask：0*/
-	ZXIC_UINT32 tb_depth;        /* dump出数据深度，以640bit为单位 */
-	ZXIC_UINT32 tb_width;        /* dump出数据宽度 00:80bit 01:160bit 10:320bit 11:640bit */
-	ZXIC_UINT32 tb_dst_addr_h;   /* dma地址高32bit */
-	ZXIC_UINT32 tb_dst_addr_l;   /* dma地址低32bit */
-}DPP_DTB_ETCAM_DUMP_FORM_T;
-
-typedef struct etcam_dump_info_t
-{
-	ZXIC_UINT32 block_sel;          /* block index 0-7 */
-	ZXIC_UINT32 addr;               /* 单个block的RAM地址，范围0~511 640bit为单位 */
-	ZXIC_UINT32 rd_mode;            /* 读模式，共8bit，每bit控制ram中对应位置的80bit数据是否有效 */
-	ZXIC_UINT32 data_or_mask;       /* data：1 mask：0 参照DPP_ETCAM_DATA_TYPE_E定义*/
-	ZXIC_UINT32 tb_depth;           /* dump出表深度，以640bit为单位 */
-	ZXIC_UINT32 tb_width;           /* dump出数据宽度 00:80bit 01:160bit 10:320bit 11:640bit */
-}ETCAM_DUMP_INFO_T;
+	ZXIC_UINT32 up_type; /* 11:etcam */
+	ZXIC_UINT32 block_sel; /* block num */
+	ZXIC_UINT32 addr; /* 640bit位单位 */
+	ZXIC_UINT32
+	rd_mode; /* 读模式，共8bit，每bit控制ram中对应位置的80bit数据是否有效*/
+	ZXIC_UINT32 data_or_mask; /* data：1 mask：0*/
+	ZXIC_UINT32 tb_depth; /* dump出数据深度，以640bit为单位 */
+	ZXIC_UINT32
+	tb_width; /* dump出数据宽度 00:80bit 01:160bit 10:320bit 11:640bit */
+	ZXIC_UINT32 tb_dst_addr_h; /* dma地址高32bit */
+	ZXIC_UINT32 tb_dst_addr_l; /* dma地址低32bit */
+} DPP_DTB_ETCAM_DUMP_FORM_T;
+
+typedef struct etcam_dump_info_t {
+	ZXIC_UINT32 block_sel; /* block index 0-7 */
+	ZXIC_UINT32 addr; /* 单个block的RAM地址，范围0~511 640bit为单位 */
+	ZXIC_UINT32
+	rd_mode; /* 读模式，共8bit，每bit控制ram中对应位置的80bit数据是否有效 */
+	ZXIC_UINT32 data_or_mask; /* data：1 mask：0 参照DPP_ETCAM_DATA_TYPE_E定义*/
+	ZXIC_UINT32 tb_depth; /* dump出表深度，以640bit为单位 */
+	ZXIC_UINT32
+	tb_width; /* dump出数据宽度 00:80bit 01:160bit 10:320bit 11:640bit */
+} ETCAM_DUMP_INFO_T;
 
 /* 表信息结构 */
-typedef struct dpp_dtb_field_t
-{
-    ZXIC_CHAR    *p_name;                         /* 字段名 */
-    ZXIC_UINT16  lsb_pos;                         /* 最低比特位置，以寄存器列表为准*/
-    ZXIC_UINT16  len;                             /* 字段长度，以比特为单位 */
-}DPP_DTB_FIELD_T;
-
-typedef struct dpp_dtb_table_t
-{
-    ZXIC_CHAR    *table_type;                       /* 表类型名称*/
-    ZXIC_UINT32  table_no;                          /* 表编号 */
-    ZXIC_UINT32  field_num;                         /* 包含的字段个数 */
-    DPP_DTB_FIELD_T *p_fields;                      /* 表格式所有字段 */
-}DPP_DTB_TABLE_T;
-
-typedef struct dpp_dtb_entry_t
-{
-	ZXIC_UINT8 *cmd;		      /* 命令 128bit 即 16B*/
-	ZXIC_UINT8 *data;	          /* 数据 */
+typedef struct dpp_dtb_field_t {
+	ZXIC_CHAR *p_name; /* 字段名 */
+	ZXIC_UINT16 lsb_pos; /* 最低比特位置，以寄存器列表为准*/
+	ZXIC_UINT16 len; /* 字段长度，以比特为单位 */
+} DPP_DTB_FIELD_T;
+
+typedef struct dpp_dtb_table_t {
+	ZXIC_CHAR *table_type; /* 表类型名称*/
+	ZXIC_UINT32 table_no; /* 表编号 */
+	ZXIC_UINT32 field_num; /* 包含的字段个数 */
+	DPP_DTB_FIELD_T *p_fields; /* 表格式所有字段 */
+} DPP_DTB_TABLE_T;
+
+typedef struct dpp_dtb_entry_t {
+	ZXIC_UINT8 *cmd; /* 命令 128bit 即 16B*/
+	ZXIC_UINT8 *data; /* 数据 */
 	ZXIC_UINT32 data_in_cmd_flag; /*eram 1/64 bit模式时使用,1表示data在cmd中*/
-	ZXIC_UINT32 data_size;        /* 数据长度，以字节为单位 */
-}DPP_DTB_ENTRY_T;
-
-typedef struct dpp_dtb_cmd_t
-{
-	ZXIC_UINT32 queue_id;          /*队列id*/
-    ZXIC_UINT32 dtb_phy_addr_hi32; /*dtb描述符物理地址高32bit*/
-    ZXIC_UINT32 dtb_phy_addr_lo32; /*dtb描述符物理地址低32bit*/
-	ZXIC_UINT32 cmd_type;          /*0为流表下发命令，1为流表dump命令*/
-	ZXIC_UINT32 int_enable;        /* 中断使能 */
-	ZXIC_UINT32 dtb_len;           /* 指示配表内容或dump描述符长度，以16字节为单位 */
-}DPP_DTB_CMD_T;
-
-
-typedef struct dpp_dtb_mc_hash_key_t
-{
-    ZXIC_UINT32 hash_key[16];
-}DPP_DTB_MC_HASH_KEY_T;
-
-typedef struct dpp_dtb_mixed_table_t
-{
-    ZXIC_UINT32 down_cmd_len;        /**down描述符长度，字节为单位*/
-    ZXIC_UINT32 dump_cmd_len;        /**dump描述符长度，字节为单位*/
-    ZXIC_UINT32 down_buff_offset;    /**down buff 偏移，字节为单位*/
-    ZXIC_UINT32 dump_buff_offset;    /**dump buff 偏移，字节为单位*/
-    ZXIC_UINT8 * p_down_cmd_buff;    /**指向下表描述符空间，空间为16KB*/
-    ZXIC_UINT8 * p_dump_cmd_buff;    /**指向dump描述符空间，空间为4KB*/
-}DPP_DTB_MIXED_TABLE_T;
-
-typedef struct dpp_dtb_mc_hash_entry_info_t
-{
-    ZXIC_UINT32 delete_en; /* delete 浣胯兘 */
-    ZXIC_UINT32 dma_en;    /* dma 浣胯兘 */
-    ZXIC_UINT32 *p_data;    /*hash 鏉＄洰鎸囬拡 闀垮害512bit*/    
-}DPP_DTB_MC_HASH_ENTRY_INFO_T;
+	ZXIC_UINT32 data_size; /* 数据长度，以字节为单位 */
+} DPP_DTB_ENTRY_T;
+
+typedef struct dpp_dtb_cmd_t {
+	ZXIC_UINT32 queue_id; /*队列id*/
+	ZXIC_UINT32 dtb_phy_addr_hi32; /*dtb描述符物理地址高32bit*/
+	ZXIC_UINT32 dtb_phy_addr_lo32; /*dtb描述符物理地址低32bit*/
+	ZXIC_UINT32 cmd_type; /*0为流表下发命令，1为流表dump命令*/
+	ZXIC_UINT32 int_enable; /* 中断使能 */
+	ZXIC_UINT32 dtb_len; /* 指示配表内容或dump描述符长度，以16字节为单位 */
+} DPP_DTB_CMD_T;
+
+typedef struct dpp_dtb_mc_hash_key_t {
+	ZXIC_UINT32 hash_key[16];
+} DPP_DTB_MC_HASH_KEY_T;
+
+typedef struct dpp_dtb_mixed_table_t {
+	ZXIC_UINT32 down_cmd_len; /**down描述符长度，字节为单位*/
+	ZXIC_UINT32 dump_cmd_len; /**dump描述符长度，字节为单位*/
+	ZXIC_UINT32 down_buff_offset; /**down buff 偏移，字节为单位*/
+	ZXIC_UINT32 dump_buff_offset; /**dump buff 偏移，字节为单位*/
+	ZXIC_UINT8 *p_down_cmd_buff; /**指向下表描述符空间，空间为16KB*/
+	ZXIC_UINT8 *p_dump_cmd_buff; /**指向dump描述符空间，空间为4KB*/
+} DPP_DTB_MIXED_TABLE_T;
+
+typedef struct dpp_dtb_mc_hash_entry_info_t {
+	ZXIC_UINT32 delete_en; /* delete 浣胯兘 */
+	ZXIC_UINT32 dma_en; /* dma 浣胯兘 */
+	ZXIC_UINT32 *p_data; /*hash 鏉＄洰鎸囬拡 闀垮害512bit*/
+} DPP_DTB_MC_HASH_ENTRY_INFO_T;
 
 /** dtb 中断配置
-* @param   int_enable  中断使能
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
+     * @param   int_enable  中断使能
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2022/08/30
+     ************************************************************/
 DPP_STATUS dpp_dtb_interrupt_status_set(ZXIC_UINT32 int_enable);
 
 /** dtb 中断获取
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2022/08/30
+     ************************************************************/
 ZXIC_UINT32 dpp_dtb_interrupt_status_get(ZXIC_VOID);
 
 /** dtb cmd 大小端设置
-* @param   int_enable  中断使能
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
+     * @param   int_enable  中断使能
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2022/08/30
+     ************************************************************/
 DPP_STATUS dpp_dtb_cmd_endian_status_set(ZXIC_UINT32 endian);
 
 /** dtb cmd 大小端获取
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
+     *
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2022/08/30
+     ************************************************************/
 DPP_STATUS dpp_dtb_cmd_endian_status_get(ZXIC_VOID);
 
 /** dtb写smmu0中的数据，数据长度不限
-* @param   dev_id          设备号
-* @param   queue_id        队列号
-* @param   smmu0_base_addr smmu0基地址，以128bit为单位
-* @param   smmu0_wr_mode   smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式
-* @param   entry_num       下发的条目数
-* @param   p_entry_arr     待下发表项内容结构体数组指针
-* @param   element_id      返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2024/01/04
-************************************************************/
-DPP_STATUS dpp_dtb_smmu0_data_write(DPP_DEV_T *dev, 
-                                    ZXIC_UINT32 queue_id,
-                                    ZXIC_UINT32 smmu0_base_addr,
-                                    ZXIC_UINT32 smmu0_wr_mode,
-                                    ZXIC_UINT32 entry_num,
-                                    DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr,
-                                    ZXIC_UINT32 *element_id);
+     * @param   dev_id          设备号
+     * @param   queue_id        队列号
+     * @param   smmu0_base_addr smmu0基地址，以128bit为单位
+     * @param   smmu0_wr_mode   smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式
+     * @param   entry_num       下发的条目数
+     * @param   p_entry_arr     待下发表项内容结构体数组指针
+     * @param   element_id      返回下表使用的元素id
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2024/01/04
+     ************************************************************/
+DPP_STATUS dpp_dtb_smmu0_data_write(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									ZXIC_UINT32 smmu0_base_addr,
+									ZXIC_UINT32 smmu0_wr_mode,
+									ZXIC_UINT32 entry_num,
+									DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr,
+									ZXIC_UINT32 *element_id);
 
 /** dtb flush smmu0中的数据,大数据量
-* @param   dev_id          设备号
-* @param   queue_id        队列号
-* @param   smmu0_base_addr smmu0基地址，以128bit为单位
-* @param   smmu0_wr_mode   smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式
-* @param   start_index     flush开始的条目
-* @param   entry_num       下发的条目数
-* @param   element_id      返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2024/01/04
-************************************************************/
-DPP_STATUS dpp_dtb_smmu0_flush(DPP_DEV_T *dev,
-                               ZXIC_UINT32 queue_id,
-                               ZXIC_UINT32 smmu0_base_addr,
-                               ZXIC_UINT32 smmu0_wr_mode,
-                               ZXIC_UINT32 start_index,
-                               ZXIC_UINT32 entry_num,
-                               ZXIC_UINT32 *element_id);
+     * @param   dev_id          设备号
+     * @param   queue_id        队列号
+     * @param   smmu0_base_addr smmu0基地址，以128bit为单位
+     * @param   smmu0_wr_mode   smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式
+     * @param   start_index     flush开始的条目
+     * @param   entry_num       下发的条目数
+     * @param   element_id      返回下表使用的元素id
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2024/01/04
+     ************************************************************/
+DPP_STATUS dpp_dtb_smmu0_flush(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+							   ZXIC_UINT32 smmu0_base_addr,
+							   ZXIC_UINT32 smmu0_wr_mode,
+							   ZXIC_UINT32 start_index, ZXIC_UINT32 entry_num,
+							   ZXIC_UINT32 *element_id);
 
 /** dtb写eRam表
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   sdt_no    eram表sdt表号
-* @param   entry_cnt 下发的条目数
-* @param   p_entry_arr   待下发表项内容结构体数组指针
-* @param   element_id   返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_eram_dma_write(DPP_DEV_T *dev, 
-                                      ZXIC_UINT32 queue_id, 
-                                      ZXIC_UINT32 sdt_no, 
-                                      ZXIC_UINT32 entry_num, 
-                                      DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr,
-                                      ZXIC_UINT32 *element_id);
+     * @param   dev_id    设备号
+     * @param   queue_id  队列号
+     * @param   sdt_no    eram表sdt表号
+     * @param   entry_cnt 下发的条目数
+     * @param   p_entry_arr   待下发表项内容结构体数组指针
+     * @param   element_id   返回下表使用的元素id
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2022/08/30
+     ************************************************************/
+DPP_STATUS dpp_dtb_eram_dma_write(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								  ZXIC_UINT32 sdt_no, ZXIC_UINT32 entry_num,
+								  DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr,
+								  ZXIC_UINT32 *element_id);
 
 /** dtb写HASH表,在插入条目时如果冲突，则对冲突条目进行记录
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   sdt_no    hash表sdt表号
-* @param   entry_cnt 下发的条目数
-* @param   p_entry_arr   待下发表项内容结构体数组指针
-* @param   element_id   返回下表使用的元素id
-* @return
-* @remark  无 是否是有一个写不成功就返回，还是继续进行下一个条目并记录错误的条目
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_hash_dma_insert(DPP_DEV_T *dev, 
-                                   ZXIC_UINT32 queue_id, 
-                                   ZXIC_UINT32 sdt_no, 
-                                   ZXIC_UINT32 entry_num, 
-                                   DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry,
-                                   ZXIC_UINT32 *element_id);
+     * @param   dev_id    设备号
+     * @param   queue_id  队列号
+     * @param   sdt_no    hash表sdt表号
+     * @param   entry_cnt 下发的条目数
+     * @param   p_entry_arr   待下发表项内容结构体数组指针
+     * @param   element_id   返回下表使用的元素id
+     * @return
+     * @remark  无 是否是有一个写不成功就返回，还是继续进行下一个条目并记录错误的条目
+     * @see
+     * @author  cbb      @date  2022/08/30
+     ************************************************************/
+DPP_STATUS dpp_dtb_hash_dma_insert(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								   ZXIC_UINT32 sdt_no, ZXIC_UINT32 entry_num,
+								   DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry,
+								   ZXIC_UINT32 *element_id);
 
 /** dtb删除HASH表
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   sdt_no    hash表sdt表号
-* @param   entry_cnt 删除的条目数
-* @param   p_entry_arr   待下发表项内容结构体数组指针
-* @param   element_id   返回下表使用的元素id
-* @return
-* @remark  无 
-* @see
-* @author        @date  2023/03/14
-************************************************************/
-DPP_STATUS dpp_dtb_hash_dma_delete(DPP_DEV_T *dev, 
-                                   ZXIC_UINT32 queue_id, 
-                                   ZXIC_UINT32 sdt_no, 
-                                   ZXIC_UINT32 entry_num, 
-                                   DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry,
-                                   ZXIC_UINT32 *element_id); 
+     * @param   dev_id    设备号
+     * @param   queue_id  队列号
+     * @param   sdt_no    hash表sdt表号
+     * @param   entry_cnt 删除的条目数
+     * @param   p_entry_arr   待下发表项内容结构体数组指针
+     * @param   element_id   返回下表使用的元素id
+     * @return
+     * @remark  无
+     * @see
+     * @author        @date  2023/03/14
+     ************************************************************/
+DPP_STATUS dpp_dtb_hash_dma_delete(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								   ZXIC_UINT32 sdt_no, ZXIC_UINT32 entry_num,
+								   DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry,
+								   ZXIC_UINT32 *element_id);
 
 /** dtb写ACL表 （SPECIFY模式，条目中指定handle，支持级联64bit/128bit）
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   sdt_no    ACL表sdt表号
-* @param   entry_num 下发的条目数
-* @param   p_acl_entry_arr   待下发表项内容结构体数组指针
-* @param   element_id    返回下表使用的元素id
-* @return
-* @remark  无 是否是有一个写不成功就返回，还是继续进行下一个条目并记录错误的条目
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_acl_dma_insert(DPP_DEV_T *dev,  
-                                      ZXIC_UINT32 queue_id, 
-                                      ZXIC_UINT32 sdt_no, 
-                                      ZXIC_UINT32 entry_num, 
-                                      DPP_DTB_ACL_ENTRY_INFO_T *p_acl_entry_arr,
-                                      ZXIC_UINT32 *element_id
-                                      );
-
+     * @param   dev_id    设备号
+     * @param   queue_id  队列号
+     * @param   sdt_no    ACL表sdt表号
+     * @param   entry_num 下发的条目数
+     * @param   p_acl_entry_arr   待下发表项内容结构体数组指针
+     * @param   element_id    返回下表使用的元素id
+     * @return
+     * @remark  无 是否是有一个写不成功就返回，还是继续进行下一个条目并记录错误的条目
+     * @see
+     * @author  cbb      @date  2022/08/30
+     ************************************************************/
+DPP_STATUS dpp_dtb_acl_dma_insert(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								  ZXIC_UINT32 sdt_no, ZXIC_UINT32 entry_num,
+								  DPP_DTB_ACL_ENTRY_INFO_T *p_acl_entry_arr,
+								  ZXIC_UINT32 *element_id);
 
 /** dtb dump eram直接表表项内容
-* @param   dev_id       设备号
-* @param   queue_id     队列号
-* @param   sdt_no       eram表sdt表号
-* @param   p_dump_eram_entry  eram数据结构，数据已分配相应内存
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_eram_data_get(DPP_DEV_T *dev, 
-                                 ZXIC_UINT32 queue_id, 
-                                 ZXIC_UINT32 sdt_no, 
-                                 DPP_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry);
+     * @param   dev_id       设备号
+     * @param   queue_id     队列号
+     * @param   sdt_no       eram表sdt表号
+     * @param   p_dump_eram_entry  eram数据结构，数据已分配相应内存
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2022/08/30
+     ************************************************************/
+DPP_STATUS dpp_dtb_eram_data_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								 ZXIC_UINT32 sdt_no,
+								 DPP_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry);
 
 /** dtb dump eram直接表表项内容
-* @param   dev_id       设备号
-* @param   queue_id     队列号
-* @param   sdt_no       eram表sdt表号
-* @param   p_dump_eram_entry  eram数据结构，数据已分配相应内存
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_eram_stat_data_get(DPP_DEV_T *dev, 
-                                      ZXIC_UINT32 queue_id, 
-                                      ZXIC_UINT32 base_addr, 
-                                      ZXIC_UINT32 rd_mode, 
-                                      ZXIC_UINT32 index,
-                                      ZXIC_UINT32 *p_data);
+     * @param   dev_id       设备号
+     * @param   queue_id     队列号
+     * @param   sdt_no       eram表sdt表号
+     * @param   p_dump_eram_entry  eram数据结构，数据已分配相应内存
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2022/08/30
+     ************************************************************/
+DPP_STATUS dpp_dtb_eram_stat_data_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									  ZXIC_UINT32 base_addr,
+									  ZXIC_UINT32 rd_mode, ZXIC_UINT32 index,
+									  ZXIC_UINT32 *p_data);
 
 /***********************************************************/
 /** 配置数据获取模式
-* @param   srh_mode   0:软件获取  1:硬件获取
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
+     * @param   srh_mode   0:软件获取  1:硬件获取
+     * @return
+     * @remark  无
+     * @see
+     * @author  cq      @date  2023/08/02
+     ************************************************************/
 ZXIC_VOID dpp_dtb_srh_mode_set(ZXIC_UINT32 srh_mode);
 
 /** 获取查找方式
-* @param   
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
+     * @param
+     * @return
+     * @remark  无
+     * @see
+     * @author  cq      @date  2023/08/02
+     ************************************************************/
 ZXIC_UINT32 dpp_dtb_srh_mode_get(ZXIC_VOID);
 
 /** 根据键值查找hash表
-* @param   dev_id       设备号，支持多芯片 
-* @param   queue_id     队列id 
-* @param   sdt_no       0~255 
-* @param   p_dtb_hash_entry    出参，返回描述符信息
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-
-ZXIC_UINT32 dpp_dtb_hash_data_get(DPP_DEV_T *dev, 
-                                ZXIC_UINT32 queue_id,
-                                ZXIC_UINT32 sdt_no,
-                                DPP_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry);
+     * @param   dev_id       设备号，支持多芯片
+     * @param   queue_id     队列id
+     * @param   sdt_no       0~255
+     * @param   p_dtb_hash_entry    出参，返回描述符信息
+     * @return
+     * @remark  无
+     * @see
+     * @author  cq      @date  2023/08/02
+     ************************************************************/
+
+ZXIC_UINT32 dpp_dtb_hash_data_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								  ZXIC_UINT32 sdt_no,
+								  DPP_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry);
 
 /** dtb 通过key和mask获取ACL表级联结果
-* @param   dev_id       设备号
-* @param   queue_id     队列号
-* @param   sdt_no       eram表sdt表号
-* @param   p_dump_acl_entry  etcam 数据结构，数据已分配相应内存,需要输入key和mask
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_acl_data_get(DPP_DEV_T *dev,
-                                ZXIC_UINT32 queue_id, 
-                                ZXIC_UINT32 sdt_no, 
-                                DPP_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry);
+     * @param   dev_id       设备号
+     * @param   queue_id     队列号
+     * @param   sdt_no       eram表sdt表号
+     * @param   p_dump_acl_entry  etcam 数据结构，数据已分配相应内存,需要输入key和mask
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2022/08/30
+     ************************************************************/
+DPP_STATUS dpp_dtb_acl_data_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								ZXIC_UINT32 sdt_no,
+								DPP_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry);
 
 /** dtb etcam 数据get接口，通过handle值获取etcam数据
-* @param   dev_id       设备号
-* @param   queue_id     队列号
-* @param   sdt_no       eram表sdt表号
-* @param   p_dump_acl_entry  etcam 数据结构，数据已分配相应内存
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_etcam_data_get(DPP_DEV_T *dev,
-                                  ZXIC_UINT32 queue_id, 
-                                  ZXIC_UINT32 sdt_no, 
-                                  DPP_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry);
-
+     * @param   dev_id       设备号
+     * @param   queue_id     队列号
+     * @param   sdt_no       eram表sdt表号
+     * @param   p_dump_acl_entry  etcam 数据结构，数据已分配相应内存
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2022/08/30
+     ************************************************************/
+DPP_STATUS dpp_dtb_etcam_data_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								  ZXIC_UINT32 sdt_no,
+								  DPP_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry);
 
 /***********************************************************/
 /** flush当前hash引擎占用的ZCAM空间
-* @param   p_se_cfg   全局数据结构
-* @param   queue_id   队列id
-* @param   fun_id     hash引擎0~3
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-DPP_STATUS dpp_dtb_zcam_space_clr(DPP_DEV_T *dev,
-                                  DPP_SE_CFG *p_se_cfg,
-                                  ZXIC_UINT32 queue_id,
-                                  ZXIC_UINT32 fun_id);
+     * @param   p_se_cfg   全局数据结构
+     * @param   queue_id   队列id
+     * @param   fun_id     hash引擎0~3
+     * @return
+     * @remark  无
+     * @see
+     * @author  cq      @date  2023/08/02
+     ************************************************************/
+DPP_STATUS dpp_dtb_zcam_space_clr(DPP_DEV_T *dev, DPP_SE_CFG *p_se_cfg,
+								  ZXIC_UINT32 queue_id, ZXIC_UINT32 fun_id);
 
 /***********************************************************/
 /** flush指定eram空间
-* @param   dev_id     设备id
-* @param   queue_id   队列id
-* @param   sdt_no     sdt号
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-DPP_STATUS dpp_dtb_eram_table_flush(DPP_DEV_T *dev,
-                               ZXIC_UINT32 queue_id,
-                               ZXIC_UINT32 sdt_no);
+     * @param   dev_id     设备id
+     * @param   queue_id   队列id
+     * @param   sdt_no     sdt号
+     * @return
+     * @remark  无
+     * @see
+     * @author  cq      @date  2023/08/02
+     ************************************************************/
+DPP_STATUS dpp_dtb_eram_table_flush(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									ZXIC_UINT32 sdt_no);
 
 /***********************************************************/
 /** flush指定hash空间(DDR/ZCAM)
-* @param   dev_id     设备id
-* @param   queue_id   队列id
-* @param   sdt_no     sdt号
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-DPP_STATUS dpp_dtb_hash_table_flush(DPP_DEV_T *dev,
-                               ZXIC_UINT32 queue_id,
-                               ZXIC_UINT32 sdt_no);
+     * @param   dev_id     设备id
+     * @param   queue_id   队列id
+     * @param   sdt_no     sdt号
+     * @return
+     * @remark  无
+     * @see
+     * @author  cq      @date  2023/08/02
+     ************************************************************/
+DPP_STATUS dpp_dtb_hash_table_flush(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									ZXIC_UINT32 sdt_no);
 
 /***********************************************************/
 /** 清除hash表资源(硬件和软件，硬件通过dtb方式清除)
-* @param   dev_id     设备id
-* @param   queue_id   队列id
-* @param   hash_id    hash引擎 0~3
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/09/26
-************************************************************/
-DPP_STATUS dpp_dtb_hash_all_entry_delete(DPP_DEV_T *dev, 
-                                        ZXIC_UINT32 queue_id, 
-                                        ZXIC_UINT32 hash_id);
+     * @param   dev_id     设备id
+     * @param   queue_id   队列id
+     * @param   hash_id    hash引擎 0~3
+     * @return
+     * @remark  无
+     * @see
+     * @author  cq      @date  2023/09/26
+     ************************************************************/
+DPP_STATUS dpp_dtb_hash_all_entry_delete(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+										 ZXIC_UINT32 hash_id);
 
 /***********************************************************/
-/** DTB etcam 整个流表清空Flush 
-* @param   devId      NP设备号
-* @param   queueId    DTB队列编号
-* @param   sdtNo      流表std号
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/  
-DPP_STATUS dpp_dtb_etcam_table_flush(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 queue_id,
-                                     ZXIC_UINT32 sdt_no);
+/** DTB etcam 整个流表清空Flush
+     * @param   devId      NP设备号
+     * @param   queueId    DTB队列编号
+     * @param   sdtNo      流表std号
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2023/07/03
+     ************************************************************/
+DPP_STATUS dpp_dtb_etcam_table_flush(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									 ZXIC_UINT32 sdt_no);
 
 /** dtb dump eram直接表表项内容 支持64bit/128bit
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   sdt_no    eram表sdt表号
-* @param   start_index 要dump的起始index，单位是sdt_no该表的mode
-* @param   p_dump_data_arr 本次dump出的数据，数据格式与下表格式相同
-* @param   entry_num       本次dump实际的条目数
-* @param   next_start_index  下次dump是开始的index  
-* @param   finish_flag       整个表dump完成标志，1表示完成，0表示未完成
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
- DPP_STATUS dpp_dtb_eram_table_dump(DPP_DEV_T *dev,
-                               ZXIC_UINT32 queue_id,
-                               ZXIC_UINT32 sdt_no,
-                               DPP_DTB_DUMP_INDEX_T start_index,
-                               DPP_DTB_ERAM_ENTRY_INFO_T* p_dump_data_arr,
-                               ZXIC_UINT32 *entry_num,
-                               DPP_DTB_DUMP_INDEX_T *next_start_index,
-                               ZXIC_UINT32 *finish_flag);
+     * @param   dev_id    设备号
+     * @param   queue_id  队列号
+     * @param   sdt_no    eram表sdt表号
+     * @param   start_index 要dump的起始index，单位是sdt_no该表的mode
+     * @param   p_dump_data_arr 本次dump出的数据，数据格式与下表格式相同
+     * @param   entry_num       本次dump实际的条目数
+     * @param   next_start_index  下次dump是开始的index
+     * @param   finish_flag       整个表dump完成标志，1表示完成，0表示未完成
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2022/08/30
+     ************************************************************/
+DPP_STATUS dpp_dtb_eram_table_dump(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								   ZXIC_UINT32 sdt_no,
+								   DPP_DTB_DUMP_INDEX_T start_index,
+								   DPP_DTB_ERAM_ENTRY_INFO_T *p_dump_data_arr,
+								   ZXIC_UINT32 *entry_num,
+								   DPP_DTB_DUMP_INDEX_T *next_start_index,
+								   ZXIC_UINT32 *finish_flag);
 
 /***********************************************************/
 /** 只dump hash表的zcam内容
-* @param   dev_id         设备id   
-* @param   queue_id       队列id 0~127
-* @param   sdt_no         sdt号  0~255
-* @param   pDumpData      出参，dump数据，内存由用户分配，结构体DPP_DTB_HASH_ENTRY_INFO_T
-* @param   entryNum       出参，dump出的有效hash条目
-* @return
-* @remark  无
-* @see
-* @author  cq      @date  2023/08/22
-************************************************************/  
+     * @param   dev_id         设备id
+     * @param   queue_id       队列id 0~127
+     * @param   sdt_no         sdt号  0~255
+     * @param   pDumpData      出参，dump数据，内存由用户分配，结构体DPP_DTB_HASH_ENTRY_INFO_T
+     * @param   entryNum       出参，dump出的有效hash条目
+     * @return
+     * @remark  无
+     * @see
+     * @author  cq      @date  2023/08/22
+     ************************************************************/
 DPP_STATUS dpp_dtb_hash_table_only_zcam_dump(DPP_DEV_T *dev,
-                                            ZXIC_UINT32 queue_id,
-                                            ZXIC_UINT32 sdt_no,
-                                            ZXIC_UINT8* pDumpData,
-                                            ZXIC_UINT32 *entryNum);
+											 ZXIC_UINT32 queue_id,
+											 ZXIC_UINT32 sdt_no,
+											 ZXIC_UINT8 *pDumpData,
+											 ZXIC_UINT32 *entryNum);
 
 /** dtb dump etcam直接表表项内容 级联eram支持64bit/128bit
-* @param   dev_id             设备号
-* @param   queue_id           队列号
-* @param   sdt_no             acl表sdt表号
-* @param   start_index        要dump的起始index，单位是sdt_no该表的mode
-* @param   p_dump_data_arr    本次dump出的数据，数据格式与下表格式相同
-* @param   entry_num          本次dump实际的条目数
-* @param   next_start_index   下次dump是开始的index  
-* @param   finish_flag        整个表dump完成标志，1表示完成，0表示未完成
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
- DPP_STATUS dpp_dtb_acl_table_dump(DPP_DEV_T *dev,
-                               ZXIC_UINT32 queue_id,
-                               ZXIC_UINT32 sdt_no,
-                               DPP_DTB_DUMP_INDEX_T start_index,
-                               DPP_DTB_ACL_ENTRY_INFO_T* p_dump_data_arr,
-                               ZXIC_UINT32 *entry_num,
-                               DPP_DTB_DUMP_INDEX_T *next_start_index,
-                               ZXIC_UINT32 *finish_flag);
-
-ZXIC_VOID dpp_data_buff_print(ZXIC_UINT8 *buff, ZXIC_UINT32 size);   
-ZXIC_VOID dpp_acl_data_print(ZXIC_UINT8 *p_data, ZXIC_UINT8 *p_mask, ZXIC_UINT32 etcam_mode);                                   
+     * @param   dev_id             设备号
+     * @param   queue_id           队列号
+     * @param   sdt_no             acl表sdt表号
+     * @param   start_index        要dump的起始index，单位是sdt_no该表的mode
+     * @param   p_dump_data_arr    本次dump出的数据，数据格式与下表格式相同
+     * @param   entry_num          本次dump实际的条目数
+     * @param   next_start_index   下次dump是开始的index
+     * @param   finish_flag        整个表dump完成标志，1表示完成，0表示未完成
+     * @return
+     * @remark  无
+     * @see
+     * @author  cbb      @date  2022/08/30
+     ************************************************************/
+DPP_STATUS dpp_dtb_acl_table_dump(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								  ZXIC_UINT32 sdt_no,
+								  DPP_DTB_DUMP_INDEX_T start_index,
+								  DPP_DTB_ACL_ENTRY_INFO_T *p_dump_data_arr,
+								  ZXIC_UINT32 *entry_num,
+								  DPP_DTB_DUMP_INDEX_T *next_start_index,
+								  ZXIC_UINT32 *finish_flag);
+
+ZXIC_VOID dpp_data_buff_print(ZXIC_UINT8 *buff, ZXIC_UINT32 size);
+ZXIC_VOID dpp_acl_data_print(ZXIC_UINT8 *p_data, ZXIC_UINT8 *p_mask,
+							 ZXIC_UINT32 etcam_mode);
 ZXIC_VOID dpp_dtb_data_print(ZXIC_UINT8 *p_data, ZXIC_UINT32 len);
 
-ZXIC_UINT32 dpp_ddr_index_calc(ZXIC_UINT32 index,
-                               ZXIC_UINT32 width_mode,
-                               ZXIC_UINT32 key_type,
-                               ZXIC_UINT32 byte_offset);
-
-DPP_STATUS dpp_dtb_hash_dma_delete_hardware(DPP_DEV_T *dev, 
-                                   ZXIC_UINT32 queue_id, 
-                                   ZXIC_UINT32 sdt_no, 
-                                   ZXIC_UINT32 entry_num, 
-                                   DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry,
-                                   ZXIC_UINT32 *element_id);
-
-ZXIC_UINT32 dpp_dtb_hash_zcam_delete_hardware(DPP_DEV_T *dev, 
-                                 ZXIC_UINT32 queue_id,
-                                 HASH_ENTRY_CFG  *p_hash_entry_cfg,
-                                 DPP_HASH_ENTRY  *p_hash_entry,
-                                 DPP_DTB_ENTRY_T *p_entry,
-                                 ZXIC_UINT8 *p_srh_succ);
-
-DPP_STATUS dpp_dtb_se_zcam_dma_dump(DPP_DEV_T *dev, 
-                                      ZXIC_UINT32 queue_id, 
-                                      ZXIC_UINT32 addr, 
-                                      ZXIC_UINT32 tb_width,
-                                      ZXIC_UINT32 depth,
-                                      ZXIC_UINT32 *p_data,
-                                      ZXIC_UINT32 *element_id);
-
-ZXIC_UINT32 dpp_dtb_hash_data_parse(ZXIC_UINT32 item_type, 
-                                   ZXIC_UINT32 key_by_size,
-                                   DPP_HASH_ENTRY *p_entry,
-                                   ZXIC_UINT8  *p_item_data,
-                                   ZXIC_UINT8  *p_data_offset);
+ZXIC_UINT32 dpp_ddr_index_calc(ZXIC_UINT32 index, ZXIC_UINT32 width_mode,
+							   ZXIC_UINT32 key_type, ZXIC_UINT32 byte_offset);
+
+DPP_STATUS
+dpp_dtb_hash_dma_delete_hardware(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								 ZXIC_UINT32 sdt_no, ZXIC_UINT32 entry_num,
+								 DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry,
+								 ZXIC_UINT32 *element_id);
+
+ZXIC_UINT32 dpp_dtb_hash_zcam_delete_hardware(DPP_DEV_T *dev,
+											  ZXIC_UINT32 queue_id,
+											  HASH_ENTRY_CFG *p_hash_entry_cfg,
+											  DPP_HASH_ENTRY *p_hash_entry,
+											  DPP_DTB_ENTRY_T *p_entry,
+											  ZXIC_UINT8 *p_srh_succ);
+
+DPP_STATUS dpp_dtb_se_zcam_dma_dump(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									ZXIC_UINT32 addr, ZXIC_UINT32 tb_width,
+									ZXIC_UINT32 depth, ZXIC_UINT32 *p_data,
+									ZXIC_UINT32 *element_id);
+
+ZXIC_UINT32 dpp_dtb_hash_data_parse(ZXIC_UINT32 item_type,
+									ZXIC_UINT32 key_by_size,
+									DPP_HASH_ENTRY *p_entry,
+									ZXIC_UINT8 *p_item_data,
+									ZXIC_UINT8 *p_data_offset);
 
 #ifdef __cplusplus
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_hash.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_hash.h
old mode 100755
new mode 100644
index e2a986ca4a21eb7fa6d5b6ffd436fc7164642607..95beac31877179d6c785cac3f51aa12415417588
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_hash.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_hash.h
@@ -1,402 +1,413 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_hash.h
-* 文件标识 : 
-* 内容摘要 : 
-* 其它说明 : 
-* 当前版本 : 
-* 作    者 : wcl
-* 完成日期 : 2014/02/14
-* DEPARTMENT: ASIC_FPGA_R&D_Dept 
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* 版 本 号:  
-* 修 改 人:  
-* 修改内容:  
-***************************************************************/
-
-#ifndef _DPP_HASH_H_
-#define _DPP_HASH_H_
-
-#include "dpp_se_cfg.h"
-
-#define HASH_FUNC_ID_MIN          (0)
-#define HASH_FUNC_ID_NUM          (4)
-
-#define HASH_DDR_CRC_NUM          (4)
-
-#define HASH_KEY_MAX              (49) /* 最大键值长度，以字节为单位 */
-#define HASH_RST_MAX              (32) /* 最大结果长度，以字节为单位 */
-#define HASH_ENTRY_POS_STEP       (16) 
-
-#define HASH_TBL_ID_NUM           (32) /* 每个Hash引擎中的最大业务表数目 */
-#define HASH_BULK_NUM             (8)  /* 每个Hash引擎DDR资源划分的块数 */
-
-
-#define HASH_ACTU_KEY_MIN         (1)  /* 业务实际键值长度 */
-#define HASH_ACTU_KEY_MAX         (48)
-#define HASH_ACTU_KEY_STEP        (1)  /* actual key的长度单位: 1字节 */
-#define HASH_KEY_CTR_SIZE         (1)  /* key中控制信息的长度, 1字节 */
-#define ITEM_ENTRY_NUM_2          (2)
-#define ITEM_ENTRY_NUM_4          (4)
-
-#define HASH_DDR_ITEM_MIN         (1<<14)
-#define HASH_DDR_ITEM_MAX         (1<<26)
-
-#define HASH_ZBLK_ID_MAX          (31)
-
-/* hash ext cfg reg */
-#define HASH_EXT_MODE_BT_START    (1)
-#define HASH_EXT_MODE_BT_WIDTH    (8)
-#define HASH_EXT_FLAG_BT_START    (0)
-#define HASH_EXT_FLAG_BT_WIDTH    (1)
-
-/* hash tbl30 depth reg */
-#define HASH_TBL0_DEPTH_BT_START     (0)
-#define HASH_TBL0_DEPTH_BT_WIDTH     (8)
-#define HASH_TBL1_DEPTH_BT_START     (8)
-#define HASH_TBL1_DEPTH_BT_WIDTH     (8)
-#define HASH_TBL2_DEPTH_BT_START     (16)
-#define HASH_TBL2_DEPTH_BT_WIDTH     (8)
-#define HASH_TBL3_DEPTH_BT_START     (24)
-#define HASH_TBL3_DEPTH_BT_WIDTH     (8)
-
-/* hash tbl74 depth reg*/
-#define HASH_TBL4_DEPTH_BT_START     (0)
-#define HASH_TBL4_DEPTH_BT_WIDTH     (8)
-#define HASH_TBL5_DEPTH_BT_START     (8)
-#define HASH_TBL5_DEPTH_BT_WIDTH     (8)
-#define HASH_TBL6_DEPTH_BT_START     (16)
-#define HASH_TBL6_DEPTH_BT_WIDTH     (8)
-#define HASH_TBL7_DEPTH_BT_START     (24)
-#define HASH_TBL7_DEPTH_BT_WIDTH     (8)
-  
-/* hash ext crc cfg*/  
-#define TBL0_EXT_CRC_CFG_BT_START    (0)
-#define TBL0_EXT_CRC_CFG_BT_WIDTH    (2)
-#define TBL1_EXT_CRC_CFG_BT_START    (2)
-#define TBL1_EXT_CRC_CFG_BT_WIDTH    (2)
-#define TBL2_EXT_CRC_CFG_BT_START    (4)
-#define TBL2_EXT_CRC_CFG_BT_WIDTH    (2)
-#define TBL3_EXT_CRC_CFG_BT_START    (6)
-#define TBL3_EXT_CRC_CFG_BT_WIDTH    (2)
-#define TBL4_EXT_CRC_CFG_BT_START    (8)
-#define TBL4_EXT_CRC_CFG_BT_WIDTH    (2)
-#define TBL5_EXT_CRC_CFG_BT_START    (10)
-#define TBL5_EXT_CRC_CFG_BT_WIDTH    (2)
-#define TBL6_EXT_CRC_CFG_BT_START    (12)
-#define TBL6_EXT_CRC_CFG_BT_WIDTH    (2)
-#define TBL7_EXT_CRC_CFG_BT_START    (14)
-#define TBL7_EXT_CRC_CFG_BT_WIDTH    (2)
-
-/* hash mono flags*/
-#define HASH0_MONO_FLAG_BT_START     (0)
-#define HASH0_MONO_FLAG_BT_WIDTH     (8)
-#define HASH1_MONO_FLAG_BT_START     (8)
-#define HASH1_MONO_FLAG_BT_WIDTH     (8)
-#define HASH2_MONO_FLAG_BT_START     (16)
-#define HASH2_MONO_FLAG_BT_WIDTH     (8)
-#define HASH3_MONO_FLAG_BT_START     (24)
-#define HASH3_MONO_FLAG_BT_WIDTH     (8)
-
-/* hash zcell mono*/
-#define ZCELL0_BULK_ID_BT_START      (2)
-#define ZCELL0_BULK_ID_BT_WIDTH      (3)
-#define ZCELL0_MONO_FLAG_BT_START    (3)
-#define ZCELL0_MONO_FLAG_BT_WIDTH    (1)
-#define ZCELL1_BULK_ID_BT_START      (10)
-#define ZCELL1_BULK_ID_BT_WIDTH      (3)
-#define ZCELL1_MONO_FLAG_BT_START    (11)
-#define ZCELL1_MONO_FLAG_BT_WIDTH    (1)
-#define ZCELL2_BULK_ID_BT_START      (18)
-#define ZCELL2_BULK_ID_BT_WIDTH      (3)
-#define ZCELL2_MONO_FLAG_BT_START    (19)
-#define ZCELL2_MONO_FLAG_BT_WIDTH    (1)
-#define ZCELL3_BULK_ID_BT_START      (26)
-#define ZCELL3_BULK_ID_BT_WIDTH      (3)
-#define ZCELL3_MONO_FLAG_BT_START    (27)
-#define ZCELL3_MONO_FLAG_BT_WIDTH    (1)
-
-/* hash zreg mono                         */
-#define ZREG0_BULK_ID_BT_START       (2) 
-#define ZREG0_BULK_ID_BT_WIDTH       (3) 
-#define ZREG0_MONO_FLAG_BT_START     (3) 
-#define ZREG0_MONO_FLAG_BT_WIDTH     (1) 
-#define ZREG1_BULK_ID_BT_START       (10)
-#define ZREG1_BULK_ID_BT_WIDTH       (3) 
-#define ZREG1_MONO_FLAG_BT_START     (11)
-#define ZREG1_MONO_FLAG_BT_WIDTH     (1) 
-#define ZREG2_BULK_ID_BT_START       (18)
-#define ZREG2_BULK_ID_BT_WIDTH       (3) 
-#define ZREG2_MONO_FLAG_BT_START     (19)
-#define ZREG2_MONO_FLAG_BT_WIDTH     (1) 
-#define ZREG3_BULK_ID_BT_START       (26)
-#define ZREG3_BULK_ID_BT_WIDTH       (3) 
-#define ZREG3_MONO_FLAG_BT_START     (27)
-#define ZREG3_MONO_FLAG_BT_WIDTH     (1) 
-
-#define OPR_CLR                (0)
-#define OPR_WR                 (1)
-
-#define OBTAIN_CONFLICT_KEY    (0)
-
-/* HASH soft reset*/
-#define  HASH_ARG_NUM_PER_BULK (8)  /* 每个bulk 需要记录的参数数目 */
-#define  HASH_ARG_NUM_PER_TBL  (4)  /* 每个表   需要记录的参数数目 */
-#define  HASH_INIT_NUM         (8)  /* HASH引擎初始化参数数目 */
-#define  HASH_BULK_INIT_NUM    (1+HASH_BULK_NUM*HASH_ARG_NUM_PER_BULK+3)   /* 1-bulk_valid +3是为了凑够4的倍数 */
-#define  HASH_TBL_INIT_NUM     (1+HASH_TBL_ID_NUM*HASH_ARG_NUM_PER_TBL+3)  /* 1-tbl_valid  +3是为了凑够4的整数倍 */
-
-typedef struct dpp_hash_table_stat
-{
-    ZXIC_FLOAT ddr;
-    ZXIC_FLOAT zcell;
-    ZXIC_FLOAT zreg;
-    ZXIC_FLOAT sum;
-}DPP_HASH_TABLE_STAT;
-
-typedef struct dpp_hash_zreg_mono_stat
-{
-    ZXIC_UINT32 zblk_id;
-    ZXIC_UINT32 zreg_id;
-}DPP_HASH_ZREG_MONO_STAT;
-
-typedef struct dpp_hash_bulk_zcam_stat
-{
-    ZXIC_UINT32 zcell_mono_idx[SE_ZBLK_NUM*SE_ZCELL_NUM];
-    DPP_HASH_ZREG_MONO_STAT zreg_mono_id[SE_ZBLK_NUM][SE_ZREG_NUM];
-}DPP_HASH_BULK_ZCAM_STAT;
-
-typedef struct dpp_hash_stat
-{
-    ZXIC_UINT32 insert_ok;
-    ZXIC_UINT32 insert_fail;
-    ZXIC_UINT32 insert_same;
-    ZXIC_UINT32 insert_ddr;
-    ZXIC_UINT32 insert_zcell;
-    ZXIC_UINT32 insert_zreg;
-
-    ZXIC_UINT32 delete_ok;
-    ZXIC_UINT32 delete_fail;
-
-    ZXIC_UINT32 search_ok;
-    ZXIC_UINT32 search_fail;
-
-    ZXIC_UINT32 zblock_num;
-    ZXIC_UINT32 zblock_array[SE_ZBLK_NUM];
-
-    DPP_HASH_TABLE_STAT insert_table[HASH_TBL_ID_NUM];
-    DPP_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono[HASH_BULK_NUM];
-}DPP_HASH_STAT;
-
-typedef enum dpp_hash_itme_pos
-{
-    HASH_ITEM_POS_0   = 0,
-    HASH_ITEM_POS_1   = 1,
-    HASH_ITEM_POS_2   = 2,
-    HASH_ITEM_POS_3   = 3,
-    HASH_ITEM_POS_MAX = 4,
-}DPP_HASH_ITME_POS;
-
-typedef enum dpp_hash_item_inst_mode
-{
-    HASH_ITEM_INSERT_LAST = 0,
-    HASH_ITEM_INSERT_1ST,
-    HASH_ITEM_INSERT_NULL
-}DPP_HASH_ITEM_INST_MODE;
-
-/* hash 表项信息 */
-typedef struct dpp_hash_tbl_info
-{
-    ZXIC_UINT32 fun_id;
-    ZXIC_UINT32 actu_key_size;  /**<  @brief 实际键值长度，以1字节为单位 */
-    ZXIC_UINT32 key_type;       /**<  @brief 表项长度类型: 1-128bit, 2-256bit, 3-512bit */
-    ZXIC_UINT8 is_init;        /**<  @brief 是否初始化*/
-    ZXIC_UINT8 mono_zcell;     /**<  @brief 是否有独占的zcell*/
-    ZXIC_UINT8 zcell_num;      /**<  @brief 独占的zcell的数目*/
-    ZXIC_UINT8 mono_zreg;     /**<  @brief 是否有独占的zcell*/
-    ZXIC_UINT8 zreg_num;      /**<  @brief 独占的zcell的数目*/    
-    ZXIC_UINT8 is_age;         /* 硬件老化标志，业务表支持硬件老化 */
-    ZXIC_UINT8 is_lrn;         /* 硬件学习标志，业务表支持硬件学习 */
-    ZXIC_UINT8 is_mc_wrt;      /* 微码写表标志，业务表支持微码写表 */
-    //ZXIC_UINT8 pad[3];
-}DPP_HASH_TBL_ID_INFO;
-
-typedef struct dpp_hash_rbkey_info
-{
-    ZXIC_UINT8         key[HASH_KEY_MAX];
-    ZXIC_UINT8         rst[HASH_RST_MAX];
-    D_NODE       entry_dn;
-    SE_ITEM_CFG  *p_item_info;
-/*    ZXIC_UINT32       rb_idx;*/
-    ZXIC_UINT32       entry_size;   /* 条目宽度，以字节为单位 */
-    ZXIC_UINT32       entry_pos;    /* 条目在item中的起始位置，以128bit为偏移单位 */
-}DPP_HASH_RBKEY_INFO;
-
-/* DDR*/
-typedef struct hash_ddr_cfg
-{
-    ZXIC_UINT32                  bulk_use;         /**< @brief 该hash引擎bulk空间是否已经使用*/
-    ZXIC_UINT32                  ddr_baddr;        /**< @brief 分配给hash的DDR空间的硬件基地址*/
-    ZXIC_UINT32                  ddr_ecc_en;       /**< @brief DDR ECC使能: 0-不使能，1-使能*/
-    ZXIC_UINT32                  item_num;         /**< @brief 硬件分配的ddr存储单元数目，以位宽为单位*/
-    ZXIC_UINT32                  bulk_id;          /**< @brief DDR空间编号*/
-    ZXIC_UINT32                  hash_ddr_arg;     /**< @brief hash ddr CRC 计算式*/
-    ZXIC_UINT32                  width_mode;       /**< @brief ddr3 位宽*/
-    ZXIC_UINT32                  hw_baddr;         /**< @brief ddr3 存储单元起始偏移，以256bit为单位*/
-    ZXIC_UINT32                  zcell_num;          /*cpu 软复位 存储记录该参数*/
-    ZXIC_UINT32                  zreg_num;           /*cpu 软复位 存储记录该参数*/
-
-    SE_ITEM_CFG             **p_item_array;   /**< @brief 指向数组指针的指针*/
-}HASH_DDR_CFG;
-
-#define HASH_ADDR_EXT_FLAG_BT_OFF    (31)
-#define HASH_ADDR_WRT_MASK_BT_OFF    (27)
-#define HASH_ADDR_BT_OFF             (1)
-#define HASH_ADDR_DDR_BT_LEN         (26)
-#define HASH_ADDR_ZCAM_BT_LEN        (17)
-typedef struct dpp_hash_wrt_lrn_rsp
-{
-    ZXIC_UINT8   space_vld; /* 仅硬件学习时此标志有效 */
-    ZXIC_UINT8   ext_flag;  /* 软件模拟硬件学习标志位*/
-    ZXIC_UINT8   wrt_mask;
-    ZXIC_UINT8   width_flag;
-    ZXIC_UINT32 lrn_addr;
-}DPP_HASH_WRT_LRN_RSP;
-
-typedef struct dpp_hash_cfg
-{
-    ZXIC_UINT32             fun_id;
-    ZXIC_UINT8               ddr_valid;     /* 是否使用DDR表项 */
-    ZXIC_UINT8               pad[3];
-    HASH_FUNCTION32    p_hash32_fun;
-    HASH_FUNCTION      p_hash16_fun;
-
-    HASH_DDR_CFG       *p_bulk_ddr_info[HASH_BULK_NUM];   /* 每个DDR空间的配置*/
-    ZXIC_UINT8               bulk_ram_mono[HASH_BULK_NUM];      /* 每个ZCAM空间独占标志*/
-    SHARE_RAM          hash_shareram; /* 共享的ZCAM资源 */
-    DPP_SE_CFG         *p_se_info;
-
-    ZXIC_RB_CFG         hash_rb;
-    ZXIC_RB_CFG         ddr_cfg_rb;
-    DPP_HASH_STAT      hash_stat;
-}DPP_HASH_CFG;
-
-typedef struct hash_entry_cfg
-{
-    ZXIC_UINT32 fun_id;
-    ZXIC_UINT8 bulk_id;
-    ZXIC_UINT8 table_id;
-    ZXIC_UINT8 key_type;
-    ZXIC_UINT8 rsp_mode;
-    ZXIC_UINT32 actu_key_size;
-    ZXIC_UINT32 key_by_size;
-    ZXIC_UINT32 rst_by_size;
-    DPP_SE_CFG *p_se_cfg;
-    DPP_HASH_CFG *p_hash_cfg;
-    DPP_HASH_RBKEY_INFO *p_rbkey_new;
-    ZXIC_RB_TN *p_rb_tn_new;
-}HASH_ENTRY_CFG;
-
-#define DPP_GET_HASH_KEY_CTRL(valid, type, tbl_id)  (((valid & 0x1) << 7) | ((type & 0x3) << 5) | (tbl_id & 0x1f))
-#define DPP_GET_HASH_TBL_ID(p_key)    ((p_key)[0] & 0x1F)
-#define DPP_GET_HASH_KEY_TYPE(p_key)  (((p_key)[0] >> 5) & 0x3)
-#define DPP_GET_HASH_KEY_VALID(p_key) (((p_key)[0] >> 7) & 0x1)
-
-/** 根据hash的类型获取其字节数，返回值包括16B,32B和64B，或者0*/
-#define DPP_GET_HASH_ENTRY_SIZE(key_type) \
-    ((key_type == HASH_KEY_128b)?16U:       \
-       ((key_type == HASH_KEY_256b)?32U:    \
-         ((key_type == HASH_KEY_512b)?64U:0)))
-
-#define DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) \
-    (actu_key_size * HASH_ACTU_KEY_STEP)
-
-#define DPP_GET_KEY_SIZE(actu_key_size) \
-    (DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) + HASH_KEY_CTR_SIZE)
-#define DPP_GET_RST_SIZE(key_type, actu_key_size) \
-    ((DPP_GET_HASH_ENTRY_SIZE(key_type) != 0)? \
-    (DPP_GET_HASH_ENTRY_SIZE(key_type) - DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) - HASH_KEY_CTR_SIZE): 0xFF)  /* modify coverity kfr 2022.05.31 */
-
-#define DPP_GET_HASH_RB_KEY(p_hash_rb, idx) \
-    ((p_hash_rb)->p_keybase + ((p_hash_rb)->key_size * (idx)))
-
-#define DPP_GET_DDR_WR_MODE(key_type) ((key_type == HASH_KEY_512b)?key_type : (key_type - 1))
-
-/** 根据条目位宽和起始的位置获取写入掩码 */
-#define DPP_GET_HASH_ENTRY_MASK(entry_size, entry_pos) \
-    ((((1U << (entry_size/16U)) - 1U) << (4U - entry_size/16U - entry_pos)) & 0xF)
-
-DPP_STATUS dpp_hash_zblkcfg_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id, SE_ZBLK_CFG  *p_zblk_cfg);
-
-DPP_STATUS dpp_hash_bulk_mono_flags_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 hash_id, ZXIC_UINT32 bulk_id);
-
-DPP_STATUS dpp_hash_zcell_mono_write(DPP_SE_CFG *p_se_cfg, SE_ZCELL_CFG *p_zcell_cfg);
-
-DPP_STATUS dpp_hash_zreg_mono_write(DPP_SE_CFG *p_se_cfg,  
-                                    ZXIC_UINT32     tbl_id,
-                                    ZXIC_UINT32     zblk_idx,
-                                    ZXIC_UINT32     zreg_id);
-
-DPP_STATUS dpp_hash_ext_cfg_write(DPP_SE_CFG   *p_se_cfg, 
-                                  ZXIC_UINT32       fun_id,
-                                  ZXIC_UINT32       bulk_id,
-                                  HASH_DDR_CFG   *p_ddr_cfg);
-
-DPP_STATUS dpp_hash_ext_cfg_clr(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id);
-
-DPP_STATUS dpp_hash_tbl_depth_write(DPP_SE_CFG   *p_se_cfg, 
-                                    ZXIC_UINT32       fun_id,
-                                    ZXIC_UINT32       bulk_id,
-                                    HASH_DDR_CFG   *p_ddr_cfg);
-
-DPP_STATUS dpp_hash_tbl_depth_clr(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id);
-
-DPP_STATUS dpp_hash_tbl_crc_poly_write(DPP_SE_CFG *p_se_cfg,
-                                       ZXIC_UINT32 fun_id,
-                                       ZXIC_UINT32 bulk_id,
-                                       ZXIC_UINT32 crc_sel);
-
-ZXIC_SINT32 dpp_hash_rb_key_cmp(ZXIC_VOID *p_new, ZXIC_VOID *p_old, ZXIC_UINT32 key_size);
-
-DPP_STATUS dpp_hash_insrt_to_item(DPP_HASH_CFG *p_hash_cfg,
-                                  DPP_HASH_RBKEY_INFO *p_rbkey,
-                                  SE_ITEM_CFG *p_item,
-                                  ZXIC_UINT32 item_idx,
-                                  ZXIC_UINT32 item_type,
-                                  ZXIC_UINT32 insrt_key_type);
-
-DPP_STATUS dpp_hash_red_black_node_alloc(DPP_DEV_T *dev,ZXIC_RB_TN **p_rb_tn_new,DPP_HASH_RBKEY_INFO **p_rbkey_new);
-
-DPP_STATUS dpp_hash_rb_insert(DPP_DEV_T *dev,HASH_ENTRY_CFG *p_hash_entry_cfg,DPP_HASH_ENTRY *p_entry);
-
-DPP_STATUS dpp_hash_set_crc_key(DPP_DEV_T *dev,HASH_ENTRY_CFG *p_hash_entry_cfg,DPP_HASH_ENTRY *p_entry,ZXIC_UINT8 *p_temp_key);
-
-DPP_STATUS dpp_hash_insert_ddr(DPP_DEV_T *dev,HASH_ENTRY_CFG *p_hash_entry_cfg,ZXIC_UINT8 *p_temp_key,ZXIC_UINT8 *p_end_flag);
-
-DPP_STATUS dpp_hash_insert_zcell(DPP_DEV_T *dev,DPP_SE_CFG *p_se_cfg,HASH_ENTRY_CFG *p_hash_entry_cfg,ZXIC_UINT8 *p_temp_key,ZXIC_UINT8 *p_end_flag);
-
-DPP_STATUS dpp_hash_insert_zreg(DPP_DEV_T *dev,HASH_ENTRY_CFG *p_hash_entry_cfg,ZXIC_UINT8 *p_temp_key,ZXIC_UINT8 *p_end_flag);
-
-/***********************************************************/
-/** 清除hash引擎的所有hash表项(清除软件配置)
-* @param   p_se_cfg
-* @param   hash_id
-* @param   bulk_id
-*
-* @return
-* @remark  无
-* @see
-* @author  cq      @date  2023/08/18
-************************************************************/
-DPP_STATUS dpp_hash_soft_all_entry_delete(DPP_SE_CFG *p_se_cfg,ZXIC_UINT32 hash_id);
-
-DPP_STATUS dpp_hash_get_hash_info_from_sdt(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, HASH_ENTRY_CFG *p_hash_entry_cfg);
-
-DPP_STATUS dpp_hash_soft_uninstall(ZXIC_UINT32 dev_id);
-
-DPP_STATUS dpp_one_hash_soft_uninstall(ZXIC_UINT32 dev_id,ZXIC_UINT32 hash_id);
-
-#endif /* dpp_hash.h */
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_hash.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : wcl
+* 完成日期 : 2014/02/14
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#ifndef _DPP_HASH_H_
+#define _DPP_HASH_H_
+
+#include "dpp_se_cfg.h"
+
+#define HASH_FUNC_ID_MIN (0)
+#define HASH_FUNC_ID_NUM (4)
+
+#define HASH_DDR_CRC_NUM (4)
+
+#define HASH_KEY_MAX (49) /* 最大键值长度，以字节为单位 */
+#define HASH_RST_MAX (32) /* 最大结果长度，以字节为单位 */
+#define HASH_ENTRY_POS_STEP (16)
+
+#define HASH_TBL_ID_NUM (32) /* 每个Hash引擎中的最大业务表数目 */
+#define HASH_BULK_NUM (8) /* 每个Hash引擎DDR资源划分的块数 */
+
+#define HASH_ACTU_KEY_MIN (1) /* 业务实际键值长度 */
+#define HASH_ACTU_KEY_MAX (48)
+#define HASH_ACTU_KEY_STEP (1) /* actual key的长度单位: 1字节 */
+#define HASH_KEY_CTR_SIZE (1) /* key中控制信息的长度, 1字节 */
+#define ITEM_ENTRY_NUM_2 (2)
+#define ITEM_ENTRY_NUM_4 (4)
+
+#define HASH_DDR_ITEM_MIN (1 << 14)
+#define HASH_DDR_ITEM_MAX (1 << 26)
+
+#define HASH_ZBLK_ID_MAX (31)
+
+/* hash ext cfg reg */
+#define HASH_EXT_MODE_BT_START (1)
+#define HASH_EXT_MODE_BT_WIDTH (8)
+#define HASH_EXT_FLAG_BT_START (0)
+#define HASH_EXT_FLAG_BT_WIDTH (1)
+
+/* hash tbl30 depth reg */
+#define HASH_TBL0_DEPTH_BT_START (0)
+#define HASH_TBL0_DEPTH_BT_WIDTH (8)
+#define HASH_TBL1_DEPTH_BT_START (8)
+#define HASH_TBL1_DEPTH_BT_WIDTH (8)
+#define HASH_TBL2_DEPTH_BT_START (16)
+#define HASH_TBL2_DEPTH_BT_WIDTH (8)
+#define HASH_TBL3_DEPTH_BT_START (24)
+#define HASH_TBL3_DEPTH_BT_WIDTH (8)
+
+/* hash tbl74 depth reg*/
+#define HASH_TBL4_DEPTH_BT_START (0)
+#define HASH_TBL4_DEPTH_BT_WIDTH (8)
+#define HASH_TBL5_DEPTH_BT_START (8)
+#define HASH_TBL5_DEPTH_BT_WIDTH (8)
+#define HASH_TBL6_DEPTH_BT_START (16)
+#define HASH_TBL6_DEPTH_BT_WIDTH (8)
+#define HASH_TBL7_DEPTH_BT_START (24)
+#define HASH_TBL7_DEPTH_BT_WIDTH (8)
+
+/* hash ext crc cfg*/
+#define TBL0_EXT_CRC_CFG_BT_START (0)
+#define TBL0_EXT_CRC_CFG_BT_WIDTH (2)
+#define TBL1_EXT_CRC_CFG_BT_START (2)
+#define TBL1_EXT_CRC_CFG_BT_WIDTH (2)
+#define TBL2_EXT_CRC_CFG_BT_START (4)
+#define TBL2_EXT_CRC_CFG_BT_WIDTH (2)
+#define TBL3_EXT_CRC_CFG_BT_START (6)
+#define TBL3_EXT_CRC_CFG_BT_WIDTH (2)
+#define TBL4_EXT_CRC_CFG_BT_START (8)
+#define TBL4_EXT_CRC_CFG_BT_WIDTH (2)
+#define TBL5_EXT_CRC_CFG_BT_START (10)
+#define TBL5_EXT_CRC_CFG_BT_WIDTH (2)
+#define TBL6_EXT_CRC_CFG_BT_START (12)
+#define TBL6_EXT_CRC_CFG_BT_WIDTH (2)
+#define TBL7_EXT_CRC_CFG_BT_START (14)
+#define TBL7_EXT_CRC_CFG_BT_WIDTH (2)
+
+/* hash mono flags*/
+#define HASH0_MONO_FLAG_BT_START (0)
+#define HASH0_MONO_FLAG_BT_WIDTH (8)
+#define HASH1_MONO_FLAG_BT_START (8)
+#define HASH1_MONO_FLAG_BT_WIDTH (8)
+#define HASH2_MONO_FLAG_BT_START (16)
+#define HASH2_MONO_FLAG_BT_WIDTH (8)
+#define HASH3_MONO_FLAG_BT_START (24)
+#define HASH3_MONO_FLAG_BT_WIDTH (8)
+
+/* hash zcell mono*/
+#define ZCELL0_BULK_ID_BT_START (2)
+#define ZCELL0_BULK_ID_BT_WIDTH (3)
+#define ZCELL0_MONO_FLAG_BT_START (3)
+#define ZCELL0_MONO_FLAG_BT_WIDTH (1)
+#define ZCELL1_BULK_ID_BT_START (10)
+#define ZCELL1_BULK_ID_BT_WIDTH (3)
+#define ZCELL1_MONO_FLAG_BT_START (11)
+#define ZCELL1_MONO_FLAG_BT_WIDTH (1)
+#define ZCELL2_BULK_ID_BT_START (18)
+#define ZCELL2_BULK_ID_BT_WIDTH (3)
+#define ZCELL2_MONO_FLAG_BT_START (19)
+#define ZCELL2_MONO_FLAG_BT_WIDTH (1)
+#define ZCELL3_BULK_ID_BT_START (26)
+#define ZCELL3_BULK_ID_BT_WIDTH (3)
+#define ZCELL3_MONO_FLAG_BT_START (27)
+#define ZCELL3_MONO_FLAG_BT_WIDTH (1)
+
+/* hash zreg mono                         */
+#define ZREG0_BULK_ID_BT_START (2)
+#define ZREG0_BULK_ID_BT_WIDTH (3)
+#define ZREG0_MONO_FLAG_BT_START (3)
+#define ZREG0_MONO_FLAG_BT_WIDTH (1)
+#define ZREG1_BULK_ID_BT_START (10)
+#define ZREG1_BULK_ID_BT_WIDTH (3)
+#define ZREG1_MONO_FLAG_BT_START (11)
+#define ZREG1_MONO_FLAG_BT_WIDTH (1)
+#define ZREG2_BULK_ID_BT_START (18)
+#define ZREG2_BULK_ID_BT_WIDTH (3)
+#define ZREG2_MONO_FLAG_BT_START (19)
+#define ZREG2_MONO_FLAG_BT_WIDTH (1)
+#define ZREG3_BULK_ID_BT_START (26)
+#define ZREG3_BULK_ID_BT_WIDTH (3)
+#define ZREG3_MONO_FLAG_BT_START (27)
+#define ZREG3_MONO_FLAG_BT_WIDTH (1)
+
+#define OPR_CLR (0)
+#define OPR_WR (1)
+
+/* HASH soft reset*/
+#define HASH_ARG_NUM_PER_BULK (8) /* 每个bulk 需要记录的参数数目 */
+#define HASH_ARG_NUM_PER_TBL (4) /* 每个表   需要记录的参数数目 */
+#define HASH_INIT_NUM (8) /* HASH引擎初始化参数数目 */
+#define HASH_BULK_INIT_NUM                       \
+	(1 + HASH_BULK_NUM * HASH_ARG_NUM_PER_BULK + \
+	 3) /* 1-bulk_valid +3是为了凑够4的倍数 */
+#define HASH_TBL_INIT_NUM                         \
+	(1 + HASH_TBL_ID_NUM * HASH_ARG_NUM_PER_TBL + \
+	 3) /* 1-tbl_valid  +3是为了凑够4的整数倍 */
+
+typedef struct dpp_hash_table_stat {
+	ZXIC_FLOAT ddr;
+	ZXIC_FLOAT zcell;
+	ZXIC_FLOAT zreg;
+	ZXIC_FLOAT sum;
+} DPP_HASH_TABLE_STAT;
+
+typedef struct dpp_hash_zreg_mono_stat {
+	ZXIC_UINT32 zblk_id;
+	ZXIC_UINT32 zreg_id;
+} DPP_HASH_ZREG_MONO_STAT;
+
+typedef struct dpp_hash_bulk_zcam_stat {
+	ZXIC_UINT32 zcell_mono_idx[SE_ZBLK_NUM * SE_ZCELL_NUM];
+	DPP_HASH_ZREG_MONO_STAT zreg_mono_id[SE_ZBLK_NUM][SE_ZREG_NUM];
+} DPP_HASH_BULK_ZCAM_STAT;
+
+typedef struct dpp_hash_stat {
+	ZXIC_UINT32 insert_ok;
+	ZXIC_UINT32 insert_fail;
+	ZXIC_UINT32 insert_same;
+	ZXIC_UINT32 insert_ddr;
+	ZXIC_UINT32 insert_zcell;
+	ZXIC_UINT32 insert_zreg;
+
+	ZXIC_UINT32 delete_ok;
+	ZXIC_UINT32 delete_fail;
+
+	ZXIC_UINT32 search_ok;
+	ZXIC_UINT32 search_fail;
+
+	ZXIC_UINT32 zblock_num;
+	ZXIC_UINT32 zblock_array[SE_ZBLK_NUM];
+
+	DPP_HASH_TABLE_STAT insert_table[HASH_TBL_ID_NUM];
+	DPP_HASH_BULK_ZCAM_STAT * p_bulk_zcam_mono[HASH_BULK_NUM];
+} DPP_HASH_STAT;
+
+typedef enum dpp_hash_itme_pos {
+	HASH_ITEM_POS_0 = 0,
+	HASH_ITEM_POS_1 = 1,
+	HASH_ITEM_POS_2 = 2,
+	HASH_ITEM_POS_3 = 3,
+	HASH_ITEM_POS_MAX = 4,
+} DPP_HASH_ITME_POS;
+
+typedef enum dpp_hash_item_inst_mode {
+	HASH_ITEM_INSERT_LAST = 0,
+	HASH_ITEM_INSERT_1ST,
+	HASH_ITEM_INSERT_NULL
+} DPP_HASH_ITEM_INST_MODE;
+
+/* hash 表项信息 */
+typedef struct dpp_hash_tbl_info {
+	ZXIC_UINT32 fun_id;
+	ZXIC_UINT32 actu_key_size; /**<  @brief 实际键值长度，以1字节为单位 */
+	ZXIC_UINT32
+	key_type; /**<  @brief 表项长度类型: 1-128bit, 2-256bit, 3-512bit */
+	ZXIC_UINT8 is_init; /**<  @brief 是否初始化*/
+	ZXIC_UINT8 mono_zcell; /**<  @brief 是否有独占的zcell*/
+	ZXIC_UINT8 zcell_num; /**<  @brief 独占的zcell的数目*/
+	ZXIC_UINT8 mono_zreg; /**<  @brief 是否有独占的zcell*/
+	ZXIC_UINT8 zreg_num; /**<  @brief 独占的zcell的数目*/
+	ZXIC_UINT8 is_age; /* 硬件老化标志，业务表支持硬件老化 */
+	ZXIC_UINT8 is_lrn; /* 硬件学习标志，业务表支持硬件学习 */
+	ZXIC_UINT8 is_mc_wrt; /* 微码写表标志，业务表支持微码写表 */
+	// ZXIC_UINT8 pad[3];
+} DPP_HASH_TBL_ID_INFO;
+
+typedef struct dpp_hash_rbkey_info {
+	ZXIC_UINT8 key[HASH_KEY_MAX];
+	ZXIC_UINT8 rst[HASH_RST_MAX];
+	D_NODE entry_dn;
+	SE_ITEM_CFG *p_item_info;
+	/*    ZXIC_UINT32       rb_idx;*/
+	ZXIC_UINT32 entry_size; /* 条目宽度，以字节为单位 */
+	ZXIC_UINT32 entry_pos; /* 条目在item中的起始位置，以128bit为偏移单位 */
+} DPP_HASH_RBKEY_INFO;
+
+/* DDR*/
+typedef struct hash_ddr_cfg {
+	ZXIC_UINT32 bulk_use; /**< @brief 该hash引擎bulk空间是否已经使用*/
+	ZXIC_UINT32 ddr_baddr; /**< @brief 分配给hash的DDR空间的硬件基地址*/
+	ZXIC_UINT32 ddr_ecc_en; /**< @brief DDR ECC使能: 0-不使能，1-使能*/
+	ZXIC_UINT32 item_num; /**< @brief 硬件分配的ddr存储单元数目，以位宽为单位*/
+	ZXIC_UINT32 bulk_id; /**< @brief DDR空间编号*/
+	ZXIC_UINT32 hash_ddr_arg; /**< @brief hash ddr CRC 计算式*/
+	ZXIC_UINT32 width_mode; /**< @brief ddr3 位宽*/
+	ZXIC_UINT32 hw_baddr; /**< @brief ddr3 存储单元起始偏移，以256bit为单位*/
+	ZXIC_UINT32 zcell_num; /*cpu 软复位 存储记录该参数*/
+	ZXIC_UINT32 zreg_num; /*cpu 软复位 存储记录该参数*/
+
+	SE_ITEM_CFG **p_item_array; /**< @brief 指向数组指针的指针*/
+} HASH_DDR_CFG;
+
+#define HASH_ADDR_EXT_FLAG_BT_OFF (31)
+#define HASH_ADDR_WRT_MASK_BT_OFF (27)
+#define HASH_ADDR_BT_OFF (1)
+#define HASH_ADDR_DDR_BT_LEN (26)
+#define HASH_ADDR_ZCAM_BT_LEN (17)
+typedef struct dpp_hash_wrt_lrn_rsp {
+	ZXIC_UINT8 space_vld; /* 仅硬件学习时此标志有效 */
+	ZXIC_UINT8 ext_flag; /* 软件模拟硬件学习标志位*/
+	ZXIC_UINT8 wrt_mask;
+	ZXIC_UINT8 width_flag;
+	ZXIC_UINT32 lrn_addr;
+} DPP_HASH_WRT_LRN_RSP;
+
+typedef struct dpp_hash_cfg {
+	ZXIC_UINT32 fun_id;
+	ZXIC_UINT8 ddr_valid; /* 是否使用DDR表项 */
+	ZXIC_UINT8 pad[3];
+	HASH_FUNCTION32 p_hash32_fun;
+	HASH_FUNCTION p_hash16_fun;
+
+	HASH_DDR_CFG * p_bulk_ddr_info[HASH_BULK_NUM]; /* 每个DDR空间的配置*/
+	ZXIC_UINT8 bulk_ram_mono[HASH_BULK_NUM]; /* 每个ZCAM空间独占标志*/
+	SHARE_RAM hash_shareram; /* 共享的ZCAM资源 */
+	DPP_SE_CFG *p_se_info;
+
+	ZXIC_RB_CFG hash_rb;
+	ZXIC_RB_CFG ddr_cfg_rb;
+	DPP_HASH_STAT hash_stat;
+} DPP_HASH_CFG;
+
+typedef struct hash_entry_cfg {
+	ZXIC_UINT32 fun_id;
+	ZXIC_UINT8 bulk_id;
+	ZXIC_UINT8 table_id;
+	ZXIC_UINT8 key_type;
+	ZXIC_UINT8 rsp_mode;
+	ZXIC_UINT32 actu_key_size;
+	ZXIC_UINT32 key_by_size;
+	ZXIC_UINT32 rst_by_size;
+	DPP_SE_CFG *p_se_cfg;
+	DPP_HASH_CFG *p_hash_cfg;
+	DPP_HASH_RBKEY_INFO *p_rbkey_new;
+	ZXIC_RB_TN *p_rb_tn_new;
+} HASH_ENTRY_CFG;
+
+#define DPP_GET_HASH_KEY_CTRL(valid, type, tbl_id) \
+	(((valid & 0x1) << 7) | ((type & 0x3) << 5) | (tbl_id & 0x1f))
+#define DPP_GET_HASH_TBL_ID(p_key) ((p_key)[0] & 0x1F)
+#define DPP_GET_HASH_KEY_TYPE(p_key) (((p_key)[0] >> 5) & 0x3)
+#define DPP_GET_HASH_KEY_VALID(p_key) (((p_key)[0] >> 7) & 0x1)
+
+/** 根据hash的类型获取其字节数，返回值包括16B,32B和64B，或者0*/
+#define DPP_GET_HASH_ENTRY_SIZE(key_type)   \
+	((key_type == HASH_KEY_128b) ?          \
+			   16U :                          \
+			   ((key_type == HASH_KEY_256b) ? \
+						32U :                 \
+						((key_type == HASH_KEY_512b) ? 64U : 0)))
+
+#define DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) \
+	(actu_key_size * HASH_ACTU_KEY_STEP)
+
+#define DPP_GET_KEY_SIZE(actu_key_size) \
+	(DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) + HASH_KEY_CTR_SIZE)
+#define DPP_GET_RST_SIZE(key_type, actu_key_size)                            \
+	((DPP_GET_HASH_ENTRY_SIZE(key_type) != 0) ?                              \
+			   (DPP_GET_HASH_ENTRY_SIZE(key_type) -                            \
+			  DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) - HASH_KEY_CTR_SIZE) : \
+			   0xFF) /* modify coverity kfr 2022.05.31 */
+
+#define DPP_GET_HASH_RB_KEY(p_hash_rb, idx) \
+	((p_hash_rb)->p_keybase + ((p_hash_rb)->key_size * (idx)))
+
+#define DPP_GET_DDR_WR_MODE(key_type) \
+	((key_type == HASH_KEY_512b) ? key_type : (key_type - 1))
+
+/** 根据条目位宽和起始的位置获取写入掩码 */
+#define DPP_GET_HASH_ENTRY_MASK(entry_size, entry_pos) \
+	((((1U << (entry_size / 16U)) - 1U)                \
+	  << (4U - entry_size / 16U - entry_pos)) &        \
+	 0xF)
+
+DPP_STATUS dpp_hash_zblkcfg_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id,
+								  SE_ZBLK_CFG *p_zblk_cfg);
+
+DPP_STATUS dpp_hash_bulk_mono_flags_write(DPP_SE_CFG *p_se_cfg,
+										  ZXIC_UINT32 hash_id,
+										  ZXIC_UINT32 bulk_id);
+
+DPP_STATUS dpp_hash_zcell_mono_write(DPP_SE_CFG *p_se_cfg,
+									 SE_ZCELL_CFG *p_zcell_cfg);
+
+DPP_STATUS dpp_hash_zreg_mono_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 tbl_id,
+									ZXIC_UINT32 zblk_idx, ZXIC_UINT32 zreg_id);
+
+DPP_STATUS dpp_hash_ext_cfg_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id,
+								  ZXIC_UINT32 bulk_id, HASH_DDR_CFG *p_ddr_cfg);
+
+DPP_STATUS dpp_hash_ext_cfg_clr(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id);
+
+DPP_STATUS dpp_hash_tbl_depth_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id,
+									ZXIC_UINT32 bulk_id,
+									HASH_DDR_CFG *p_ddr_cfg);
+
+DPP_STATUS dpp_hash_tbl_depth_clr(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id);
+
+DPP_STATUS dpp_hash_tbl_crc_poly_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id,
+									   ZXIC_UINT32 bulk_id,
+									   ZXIC_UINT32 crc_sel);
+
+ZXIC_SINT32 dpp_hash_rb_key_cmp(ZXIC_VOID *p_new, ZXIC_VOID *p_old,
+								ZXIC_UINT32 key_size);
+
+DPP_STATUS dpp_hash_insrt_to_item(DPP_HASH_CFG *p_hash_cfg,
+								  DPP_HASH_RBKEY_INFO *p_rbkey,
+								  SE_ITEM_CFG *p_item, ZXIC_UINT32 item_idx,
+								  ZXIC_UINT32 item_type,
+								  ZXIC_UINT32 insrt_key_type);
+
+DPP_STATUS dpp_hash_red_black_node_alloc(DPP_DEV_T *dev,
+										 ZXIC_RB_TN **p_rb_tn_new,
+										 DPP_HASH_RBKEY_INFO **p_rbkey_new);
+
+DPP_STATUS dpp_hash_rb_insert(DPP_DEV_T *dev, HASH_ENTRY_CFG *p_hash_entry_cfg,
+							  DPP_HASH_ENTRY *p_entry);
+
+DPP_STATUS dpp_hash_set_crc_key(DPP_DEV_T *dev,
+								HASH_ENTRY_CFG *p_hash_entry_cfg,
+								DPP_HASH_ENTRY *p_entry,
+								ZXIC_UINT8 *p_temp_key);
+
+DPP_STATUS dpp_hash_insert_ddr(DPP_DEV_T *dev, HASH_ENTRY_CFG *p_hash_entry_cfg,
+							   ZXIC_UINT8 *p_temp_key, ZXIC_UINT8 *p_end_flag);
+
+DPP_STATUS dpp_hash_insert_zcell(DPP_DEV_T *dev, DPP_SE_CFG *p_se_cfg,
+								 HASH_ENTRY_CFG *p_hash_entry_cfg,
+								 ZXIC_UINT8 *p_temp_key,
+								 ZXIC_UINT8 *p_end_flag);
+
+DPP_STATUS dpp_hash_insert_zreg(DPP_DEV_T *dev,
+								HASH_ENTRY_CFG *p_hash_entry_cfg,
+								ZXIC_UINT8 *p_temp_key, ZXIC_UINT8 *p_end_flag);
+
+/***********************************************************/
+/** 清除hash引擎的所有hash表项(清除软件配置)
+ * @param   p_se_cfg
+ * @param   hash_id
+ * @param   bulk_id
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/18
+ ************************************************************/
+DPP_STATUS dpp_hash_soft_all_entry_delete(DPP_SE_CFG *p_se_cfg,
+										  ZXIC_UINT32 hash_id);
+
+DPP_STATUS dpp_hash_get_hash_info_from_sdt(ZXIC_UINT32 dev_id,
+										   ZXIC_UINT32 sdt_no,
+										   HASH_ENTRY_CFG *p_hash_entry_cfg);
+
+DPP_STATUS dpp_hash_soft_uninstall(ZXIC_UINT32 dev_id);
+
+DPP_STATUS dpp_one_hash_soft_uninstall(ZXIC_UINT32 dev_id, ZXIC_UINT32 hash_id);
+
+#endif /* dpp_hash.h */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_hash_crc.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_hash_crc.h
old mode 100755
new mode 100644
index 33fde7089d041d4a3871edccedb5ea9e7c34205b..eac7b0e5954b2ad08c3dc77af97de0f72627e8a6
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_hash_crc.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_hash_crc.h
@@ -1,16 +1,17 @@
-#ifndef _DPP_HASH_CRC_H_
-#define _DPP_HASH_CRC_H_
-
-#define MAX_CRC_WIDTH     (20)
-
-ZXIC_UINT32 dpp_crc32_calc(ZXIC_UINT8 *pInputKey,ZXIC_UINT32 dwByteNum,ZXIC_UINT32 dwCrcPoly);
-
-ZXIC_UINT16 dpp_crc16_calc(ZXIC_UINT8 *pInputKey,ZXIC_UINT32 dwByteNum,ZXIC_UINT16 dwCrcPoly);
-
-ZXIC_UINT16 dpp_crc16_get_idx(ZXIC_UINT16 crc_val);
-
-ZXIC_UINT16 dpp_crc16_table_lookup(ZXIC_UINT8 *pInputKey, ZXIC_UINT32 dwByteNum, ZXIC_UINT16 dwCrcPoly);
-
-#endif
-
-
+#ifndef _DPP_HASH_CRC_H_
+#define _DPP_HASH_CRC_H_
+
+#define MAX_CRC_WIDTH (20)
+
+ZXIC_UINT32 dpp_crc32_calc(ZXIC_UINT8 *pInputKey, ZXIC_UINT32 dwByteNum,
+						   ZXIC_UINT32 dwCrcPoly);
+
+ZXIC_UINT16 dpp_crc16_calc(ZXIC_UINT8 *pInputKey, ZXIC_UINT32 dwByteNum,
+						   ZXIC_UINT16 dwCrcPoly);
+
+ZXIC_UINT16 dpp_crc16_get_idx(ZXIC_UINT16 crc_val);
+
+ZXIC_UINT16 dpp_crc16_table_lookup(ZXIC_UINT8 *pInputKey, ZXIC_UINT32 dwByteNum,
+								   ZXIC_UINT16 dwCrcPoly);
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_se_cfg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_se_cfg.h
old mode 100755
new mode 100644
index 7f66a226bdf8d1b6e428d6a2ff2beb95726049f4..1979e51730d3cdb8c8f93715ebc931fc94aab8f0
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_se_cfg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/table/se/dpp_se_cfg.h
@@ -1,279 +1,271 @@
-/*****************************************************************************
- * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。
- * 
- * 文件名称：   dpp_se_cfg.h
- * 文件标识：   SE配置部分头文件
- * 内容摘要：   
- * 其它说明：   
- * 当前版本：    
- * 作    者：    ChenWei10088471
- * 完成日期：   
- * 当前责任人-1：
- * 当前责任人-2：
- *
- * DEPARTMENT       : ASIC_FPGA_R&D_Dept
- * MANUAL_PERCENT   : 100% 
- *****************************************************************************/
-
-#ifndef _DPP_SE_CFG_H_
-#define _DPP_SE_CFG_H_
-
-#include "dpp_se_api.h"
-
-
-#define DPP_WRITE_FILE_EN         (0)
-
-#define LPM_OPTIMIZE_EZXIC_VOLUTION_TIME_SET_EN (0)
-
-#define SE_ITEM_WIDTH_MAX         (64) /* 单条item最大宽度, 以字节为单位 */
-#define SE_ENTRY_WIDTH_MAX        (64) /* 单条entry最大宽度, 以字节为单位 */
-
-#define SE_RAM_WIDTH              (512)
-
-#define IPV4_DDR_WIDTH            (256)
-#define IPV6_DDR_WIDTH            (512)
-#define IPV6_DDR_WIDTH_LR         (384)    /*线速宽度为384*/
-
-#define ROUTE_DEFAULT_REG_NUM     (8)
-#define ZBLK_LAST_INDREG_ADDR     (0x15)
-#define ZBLK_ECC_STATU_REG_ADDR   (0x11)
-#define ZBLK_HASH_LIST_REG0_ADDR  (0xd)
-#define ZBLK_HASH_LIST_REG3_ADDR  (0x10)
-
-#define ZCELL_ADDR_BT_START       (0)
-#define ZCELL_ADDR_BT_WIDTH       (9)
-#define ZCELL_IDX_BT_START        (9)
-#define ZCELL_IDX_BT_WIDTH        (2)
-#define ZBLK_IDX_BT_START         (11)
-#define ZBLK_IDX_BT_WIDTH         (3)
-#define ZGRP_IDX_BT_START         (14)
-#define ZGRP_IDX_BT_WIDTH         (2)
-#define REG_SRAM_FLAG_BT_START    (16)
-#define REG_SRAM_FLAG_BT_WIDTH    (1)
-#define ZBLK_WRT_MASK_BT_START    (17)
-#define ZBLK_WRT_MASK_BT_WIDTH    (4)
-
-#define ZBLK_NUM_PER_ZGRP         (8)
-
-/*片外部分*/
-#define     SE_DDR_WIDTH          (128)
-
-
-struct def_route_info;
-
-
-/*HASH 函数部分*/
-typedef ZXIC_UINT16 (*HASH_FUNCTION)(ZXIC_UINT8 *pkey,ZXIC_UINT32 width,ZXIC_UINT16 arg);
-typedef ZXIC_UINT32 (*HASH_FUNCTION32)(ZXIC_UINT8 *pkey,ZXIC_UINT32 width,ZXIC_UINT32 arg);
-
-typedef ZXIC_UINT32 (*WR_PROCESS) (ZXIC_UINT8*p_buff, ZXIC_UINT32 size);
-
-
-typedef enum file_type
-{
-    FILE_TYPE_REG = 0,
-    FILE_TYPE_RAM,
-    FILE_TYPE_ZBLK_CFG,
-    FILE_TYPE_ZCELL_CFG,
-    FILE_TYPE_DEF_ROUTE,
-    FILE_TYPE_DDR256,
-    FILE_TYPE_DDR512, 
-    FILE_TYPE_V6CMP_CFG,
-    FILE_TYPE_V4CMP_CFG,
-    FILE_TYPE_DDR128,
-}FILE_TYPE;
-
-typedef enum se_item_type
-{
-    ITEM_INVALID = 0,
-    ITEM_RAM,
-    ITEM_DDR_256,
-    ITEM_DDR_512,
-    ITEM_REG,
-}SE_ITEM_TYPE;
-
-
-typedef enum se_fun_type
-{
-    FUN_HASH = 1,
-    FUN_LPM,
-    FUN_ACL,
-    FUN_MAX
-}SE_FUN_TYPE;
-
-
-typedef struct file_info
-{
-    ZXIC_FILE       *fp;
-    ZXIC_UINT32     f_status; /*1 open, 0 close*/    
-}FILE_INFO;
-
-typedef struct file_mng
-{
-    ZXIC_RB_CFG   rb_fn;
-    FILE_INFO    *p_fi;
-}SE_FILE_MNG;
-
-
-#define     ZBLK_CFG_BASE          (0x8000)
-#define     SERVICE_REG_ADDR       (0)
-#define     MASK_REG_ADDR          (1)
-#define     DEFAULT_REG_ADDR       (5)
-#define     V6CMP_REG_ADDR         (0x12)
-#define     V4CMP_REG_ADDR         (0x13)
-
-#define GET_ZBLK_IDX(zcell_idx) \
-    (((zcell_idx) & 0x7F) >> 2)
-
-#define GET_ZCELL_IDX(zcell_idx) \
-    ((zcell_idx) & 0x3)
-
-#define DPP_SE_GET_ZBLK_CFG(p_se,zblk_idx) \
-    (&(((DPP_SE_CFG*)(p_se))->zblk_info[zblk_idx]))
-
-#define DPP_SE_GET_ZCELL_CFG(p_se,zcell_idx) \
-    (&(((DPP_SE_CFG*)(p_se))->zblk_info[GET_ZBLK_IDX(zcell_idx)].zcell_info[GET_ZCELL_IDX(zcell_idx)]))
-
-#define DPP_GET_FUN_INFO(p_se,fun_id) \
-    (&(((DPP_SE_CFG*)(p_se))->fun_info[fun_id]))
-
-
-#define ZBLK_CHECK_FULL(p_zblk_cfg) \
-    (((((SE_ZBLK_CFG*)(p_zblk_cfg))->zcell_bm & 0xF )== 0xF ) ?  1 : 0 )
-
-#define GET_ZCELL_CRC_VAL(zcell_id, crc16_val) \
-    (((crc16_val) >> (zcell_id)) & (SE_RAM_DEPTH - 1))
-
-#define ZBLK_ADDR_CONV(zblk_idx) \
-    (((zblk_idx) / ZBLK_NUM_PER_ZGRP) * (1 << ZBLK_IDX_BT_WIDTH) + (zblk_idx)%ZBLK_NUM_PER_ZGRP)
-
-#define ZCELL_ADDR_CONV(zcell_idx) \
-    ((ZBLK_ADDR_CONV(((zcell_idx) >> ZCELL_IDX_BT_WIDTH) & ((1<<(ZBLK_IDX_BT_WIDTH+ZGRP_IDX_BT_WIDTH))-1)) << ZCELL_IDX_BT_WIDTH) | ((zcell_idx) & ((1<<ZCELL_IDX_BT_WIDTH)-1)))
-
-#define ZCELL_BASE_ADDR_CALC(zcell_idx) \
-    ((0xF << ZBLK_WRT_MASK_BT_START) | (((ZCELL_ADDR_CONV(zcell_idx)) & ((1<<(ZCELL_IDX_BT_WIDTH+ZBLK_IDX_BT_WIDTH+ZGRP_IDX_BT_WIDTH))-1)) << ZCELL_ADDR_BT_WIDTH))
-
-#define ZBLK_ITEM_ADDR_CALC(zcell_idx,item_idx) \
-    ((ZCELL_BASE_ADDR_CALC(zcell_idx)) | ((item_idx) & (SE_RAM_DEPTH - 1)))
-
-#define ZBLK_REG_ADDR_CALC(zblk_idx, offset) \
-    ((0xF << ZBLK_WRT_MASK_BT_START) | (0x1 << REG_SRAM_FLAG_BT_START) | ((ZBLK_ADDR_CONV(zblk_idx) & 0x1F) << ZBLK_IDX_BT_START) | ((offset) & 0x1FF))
-
-#define ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, reg_idx) \
-    (ZBLK_REG_ADDR_CALC((zblk_idx), (0xD + (reg_idx))))
-
-
-#define  ROUTEID_CONVT_ROUTEMODE(rout_id)       ((rout_id & 0x01) ? DPP_ROUTE_MODE_IPV6 : DPP_ROUTE_MODE_IPV4)
-
-
-DPP_STATUS dpp_se_cfg_set(ZXIC_UINT32 dev_id, DPP_SE_CFG *p_se_cfg);
-
-DPP_STATUS dpp_se_cfg_get(ZXIC_UINT32 dev_id, DPP_SE_CFG **p_se_cfg);
-
-DPP_STATUS dpp_se_init(DPP_DEV_T *dev, DPP_SE_CFG *p_se_cfg);
-
-DPP_STATUS dpp_se_fun_init(DPP_SE_CFG *p_se_cfg, ZXIC_UINT8 id, ZXIC_UINT32 fun_type);
-
-DPP_STATUS dpp_se_fun_deinit(DPP_SE_CFG *p_se_cfg, ZXIC_UINT8 id, ZXIC_UINT32 fun_type);
-
-#define DPP_SE_CHECK_FUN(p_func_id,id,type) \
-    do{\
-        if (!(p_func_id)->is_used)\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],is_used Fun_id is invalid,(p_func_id)->is_used is [%d]",DPP_SE_RC_FUN_INVALID,(p_func_id)->is_used);\
-            return DPP_SE_RC_FUN_INVALID;\
-        }\
-        else if ((p_func_id)->fun_id != (id))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],fun_id != (id) Fun_id is invalid;p_func_id->fun_id is [%d]",DPP_SE_RC_FUN_INVALID,(p_func_id)->fun_id);\
-            return DPP_SE_RC_FUN_INVALID;\
-        }\
-        else if (!(p_func_id)->fun_ptr)\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],fun_ptr Fun_id is invalid",DPP_SE_RC_FUN_INVALID);\
-            return DPP_SE_RC_FUN_INVALID;\
-        }\
-        else if ((p_func_id)->fun_type != (type))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],type Fun_id is invalid",DPP_SE_RC_FUN_INVALID);\
-            return DPP_SE_RC_FUN_INVALID;\
-        }\
-     }while (0)
-
-#define DPP_SE_CHECK_FUN_MEMORY_FREE(p_func_id,id,type,ptr) \
-    do{\
-        if (!(p_func_id)->is_used)\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],is_used Fun_id is invalid,(p_func_id)->is_used is [%d]",DPP_SE_RC_FUN_INVALID,(p_func_id)->is_used);\
-            ZXIC_COMM_FREE(ptr);\
-            return DPP_SE_RC_FUN_INVALID;\
-        }\
-        else if ((p_func_id)->fun_id != (id))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],fun_id != (id) Fun_id is invalid;p_func_id->fun_id is [%d]",DPP_SE_RC_FUN_INVALID,(p_func_id)->fun_id);\
-            ZXIC_COMM_FREE(ptr);\
-            return DPP_SE_RC_FUN_INVALID;\
-        }\
-        else if (!(p_func_id)->fun_ptr)\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],fun_ptr Fun_id is invalid",DPP_SE_RC_FUN_INVALID);\
-            ZXIC_COMM_FREE(ptr);\
-            return DPP_SE_RC_FUN_INVALID;\
-        }\
-        else if ((p_func_id)->fun_type != (type))\
-        {\
-            ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],type Fun_id is invalid",DPP_SE_RC_FUN_INVALID);\
-            ZXIC_COMM_FREE(ptr);\
-            return DPP_SE_RC_FUN_INVALID;\
-        }\
-     }while (0)
-
-#define DPP_SE_CHECK_FUN_MUTEX_UNLOCK(p_func_id, id, type, mutex) \
-do{\
-    if (!(p_func_id)->is_used)\
-    {\
-        ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],is_used Fun_id is invalid,(p_func_id)->is_used is [%d]", DPP_SE_RC_FUN_INVALID,(p_func_id)->is_used);\
-        zxic_comm_mutex_unlock(mutex);\
-        return DPP_SE_RC_FUN_INVALID;\
-    }\
-    else if ((p_func_id)->fun_id != (id))\
-    {\
-        ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],fun_id != (id) Fun_id is invalid;p_func_id->fun_id is [%d]", DPP_SE_RC_FUN_INVALID,(p_func_id)->fun_id);\
-        zxic_comm_mutex_unlock(mutex);\
-        return DPP_SE_RC_FUN_INVALID;\
-    }\
-    else if (!(p_func_id)->fun_ptr)\
-    {\
-        ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],fun_ptr Fun_id is invalid", DPP_SE_RC_FUN_INVALID);\
-        zxic_comm_mutex_unlock(mutex);\
-        return DPP_SE_RC_FUN_INVALID;\
-    }\
-    else if ((p_func_id)->fun_type != (type))\
-    {\
-        ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],type Fun_id is invalid", DPP_SE_RC_FUN_INVALID);\
-        zxic_comm_mutex_unlock(mutex);\
-        return DPP_SE_RC_FUN_INVALID;\
-    }\
-  }while (0) 
-
-
-#define  DPP_SE_HW_POS(x) (SE_RAM_WIDTH - 1 -(x))  
-
-#define         DPP_SE_ZBLK_OUT_DDR_V6_START         (0)
-#define         DPP_SE_ZBLK_OUT_DDR_V6_END           (0)
-
-#define         DPP_SE_ZBLK_OUT_DDR_V4_START         (0)
-#define         DPP_SE_ZBLK_OUT_DDR_V4_END           (0)
-
-#define         DPP_SE_ZBLK_SERVICE_TYPE_START      (3)
-#define         DPP_SE_ZBLK_SERVICE_TYPE_END        (3)
-
-#define         DPP_SE_ZBLK_HASH_CHAN_START         (2)
-#define         DPP_SE_ZBLK_HASH_CHAN_END           (1)
-
-#define         DPP_SE_ZBLK_HW_POS_EN_START         (0)
-#define         DPP_SE_ZBLK_HW_POS_EN_END           (0)
-
-#endif
-
-
+/*****************************************************************************
+ * 版权所有 (C)2001-2015, 深圳市中兴通讯股份有限公司。
+ *
+ * 文件名称：   dpp_se_cfg.h
+ * 文件标识：   SE配置部分头文件
+ * 内容摘要：
+ * 其它说明：
+ * 当前版本：
+ * 作    者：    ChenWei10088471
+ * 完成日期：
+ * 当前责任人-1：
+ * 当前责任人-2：
+ *
+ * DEPARTMENT       : ASIC_FPGA_R&D_Dept
+ * MANUAL_PERCENT   : 100%
+ *****************************************************************************/
+
+#ifndef _DPP_SE_CFG_H_
+#define _DPP_SE_CFG_H_
+
+#include "dpp_se_api.h"
+
+#define LPM_OPTIMIZE_EZXIC_VOLUTION_TIME_SET_EN (0)
+
+#define SE_ITEM_WIDTH_MAX (64) /* 单条item最大宽度, 以字节为单位 */
+#define SE_ENTRY_WIDTH_MAX (64) /* 单条entry最大宽度, 以字节为单位 */
+
+#define SE_RAM_WIDTH (512)
+
+#define IPV4_DDR_WIDTH (256)
+#define IPV6_DDR_WIDTH (512)
+#define IPV6_DDR_WIDTH_LR (384) /*线速宽度为384*/
+
+#define ROUTE_DEFAULT_REG_NUM (8)
+#define ZBLK_LAST_INDREG_ADDR (0x15)
+#define ZBLK_ECC_STATU_REG_ADDR (0x11)
+#define ZBLK_HASH_LIST_REG0_ADDR (0xd)
+#define ZBLK_HASH_LIST_REG3_ADDR (0x10)
+
+#define ZCELL_ADDR_BT_START (0)
+#define ZCELL_ADDR_BT_WIDTH (9)
+#define ZCELL_IDX_BT_START (9)
+#define ZCELL_IDX_BT_WIDTH (2)
+#define ZBLK_IDX_BT_START (11)
+#define ZBLK_IDX_BT_WIDTH (3)
+#define ZGRP_IDX_BT_START (14)
+#define ZGRP_IDX_BT_WIDTH (2)
+#define REG_SRAM_FLAG_BT_START (16)
+#define REG_SRAM_FLAG_BT_WIDTH (1)
+#define ZBLK_WRT_MASK_BT_START (17)
+#define ZBLK_WRT_MASK_BT_WIDTH (4)
+
+#define ZBLK_NUM_PER_ZGRP (8)
+
+/*片外部分*/
+#define SE_DDR_WIDTH (128)
+
+struct def_route_info;
+
+/*HASH 函数部分*/
+typedef ZXIC_UINT16 (*HASH_FUNCTION)(ZXIC_UINT8 *pkey, ZXIC_UINT32 width,
+									 ZXIC_UINT16 arg);
+typedef ZXIC_UINT32 (*HASH_FUNCTION32)(ZXIC_UINT8 *pkey, ZXIC_UINT32 width,
+									   ZXIC_UINT32 arg);
+
+typedef ZXIC_UINT32 (*WR_PROCESS)(ZXIC_UINT8 *p_buff, ZXIC_UINT32 size);
+
+typedef enum file_type {
+	FILE_TYPE_REG = 0,
+	FILE_TYPE_RAM,
+	FILE_TYPE_ZBLK_CFG,
+	FILE_TYPE_ZCELL_CFG,
+	FILE_TYPE_DEF_ROUTE,
+	FILE_TYPE_DDR256,
+	FILE_TYPE_DDR512,
+	FILE_TYPE_V6CMP_CFG,
+	FILE_TYPE_V4CMP_CFG,
+	FILE_TYPE_DDR128,
+} FILE_TYPE;
+
+typedef enum se_item_type {
+	ITEM_INVALID = 0,
+	ITEM_RAM,
+	ITEM_DDR_256,
+	ITEM_DDR_512,
+	ITEM_REG,
+} SE_ITEM_TYPE;
+
+typedef enum se_fun_type {
+	FUN_HASH = 1,
+	FUN_LPM,
+	FUN_ACL,
+	FUN_MAX
+} SE_FUN_TYPE;
+
+typedef struct file_info {
+	ZXIC_FILE *fp;
+	ZXIC_UINT32 f_status; /*1 open, 0 close*/
+} FILE_INFO;
+
+typedef struct file_mng {
+	ZXIC_RB_CFG rb_fn;
+	FILE_INFO *p_fi;
+} SE_FILE_MNG;
+
+#define ZBLK_CFG_BASE (0x8000)
+#define SERVICE_REG_ADDR (0)
+#define MASK_REG_ADDR (1)
+#define DEFAULT_REG_ADDR (5)
+#define V6CMP_REG_ADDR (0x12)
+#define V4CMP_REG_ADDR (0x13)
+
+#define GET_ZBLK_IDX(zcell_idx) (((zcell_idx)&0x7F) >> 2)
+
+#define GET_ZCELL_IDX(zcell_idx) ((zcell_idx)&0x3)
+
+#define DPP_SE_GET_ZBLK_CFG(p_se, zblk_idx) \
+	(&(((DPP_SE_CFG *)(p_se))->zblk_info[zblk_idx]))
+
+#define DPP_SE_GET_ZCELL_CFG(p_se, zcell_idx)       \
+	(&(((DPP_SE_CFG *)(p_se))                       \
+			   ->zblk_info[GET_ZBLK_IDX(zcell_idx)] \
+			   .zcell_info[GET_ZCELL_IDX(zcell_idx)]))
+
+#define DPP_GET_FUN_INFO(p_se, fun_id) \
+	(&(((DPP_SE_CFG *)(p_se))->fun_info[fun_id]))
+
+#define ZBLK_CHECK_FULL(p_zblk_cfg) \
+	(((((SE_ZBLK_CFG *)(p_zblk_cfg))->zcell_bm & 0xF) == 0xF) ? 1 : 0)
+
+#define GET_ZCELL_CRC_VAL(zcell_id, crc16_val) \
+	(((crc16_val) >> (zcell_id)) & (SE_RAM_DEPTH - 1))
+
+#define ZBLK_ADDR_CONV(zblk_idx)                                   \
+	(((zblk_idx) / ZBLK_NUM_PER_ZGRP) * (1 << ZBLK_IDX_BT_WIDTH) + \
+	 (zblk_idx) % ZBLK_NUM_PER_ZGRP)
+
+#define ZCELL_ADDR_CONV(zcell_idx)                                         \
+	((ZBLK_ADDR_CONV(((zcell_idx) >> ZCELL_IDX_BT_WIDTH) &                 \
+					 ((1 << (ZBLK_IDX_BT_WIDTH + ZGRP_IDX_BT_WIDTH)) - 1)) \
+	  << ZCELL_IDX_BT_WIDTH) |                                             \
+	 ((zcell_idx) & ((1 << ZCELL_IDX_BT_WIDTH) - 1)))
+
+#define ZCELL_BASE_ADDR_CALC(zcell_idx)                                       \
+	((0xF << ZBLK_WRT_MASK_BT_START) |                                        \
+	 (((ZCELL_ADDR_CONV(zcell_idx)) &                                         \
+	   ((1 << (ZCELL_IDX_BT_WIDTH + ZBLK_IDX_BT_WIDTH + ZGRP_IDX_BT_WIDTH)) - \
+		1))                                                                   \
+	  << ZCELL_ADDR_BT_WIDTH))
+
+#define ZBLK_ITEM_ADDR_CALC(zcell_idx, item_idx) \
+	((ZCELL_BASE_ADDR_CALC(zcell_idx)) | ((item_idx) & (SE_RAM_DEPTH - 1)))
+
+#define ZBLK_REG_ADDR_CALC(zblk_idx, offset)                             \
+	((0xF << ZBLK_WRT_MASK_BT_START) | (0x1 << REG_SRAM_FLAG_BT_START) | \
+	 ((ZBLK_ADDR_CONV(zblk_idx) & 0x1F) << ZBLK_IDX_BT_START) |          \
+	 ((offset)&0x1FF))
+
+#define ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, reg_idx) \
+	(ZBLK_REG_ADDR_CALC((zblk_idx), (0xD + (reg_idx))))
+
+#define ROUTEID_CONVT_ROUTEMODE(rout_id) \
+	((rout_id & 0x01) ? DPP_ROUTE_MODE_IPV6 : DPP_ROUTE_MODE_IPV4)
+
+DPP_STATUS dpp_se_cfg_set(ZXIC_UINT32 dev_id, DPP_SE_CFG *p_se_cfg);
+
+DPP_STATUS dpp_se_cfg_get(ZXIC_UINT32 dev_id, DPP_SE_CFG **p_se_cfg);
+
+DPP_STATUS dpp_se_init(DPP_DEV_T *dev, DPP_SE_CFG *p_se_cfg);
+
+DPP_STATUS dpp_se_fun_init(DPP_SE_CFG *p_se_cfg, ZXIC_UINT8 id,
+						   ZXIC_UINT32 fun_type);
+
+DPP_STATUS dpp_se_fun_deinit(DPP_SE_CFG *p_se_cfg, ZXIC_UINT8 id,
+							 ZXIC_UINT32 fun_type);
+
+#define DPP_SE_CHECK_FUN(p_func_id, id, type)                                                    \
+	do {                                                                                         \
+		if (!(p_func_id)->is_used) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                               \
+					"\n Error[0x%x],is_used Fun_id is invalid,(p_func_id)->is_used is [%d]",     \
+					DPP_SE_RC_FUN_INVALID, (p_func_id)->is_used);                                \
+			return DPP_SE_RC_FUN_INVALID;                                                        \
+		} else if ((p_func_id)->fun_id != (id)) {                                                \
+			ZXIC_COMM_TRACE_ERROR(                                                               \
+					"\n Error[0x%x],fun_id != (id) Fun_id is invalid;p_func_id->fun_id is [%d]", \
+					DPP_SE_RC_FUN_INVALID, (p_func_id)->fun_id);                                 \
+			return DPP_SE_RC_FUN_INVALID;                                                        \
+		} else if (!(p_func_id)->fun_ptr) {                                                      \
+			ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],fun_ptr Fun_id is invalid",                    \
+								  DPP_SE_RC_FUN_INVALID);                                        \
+			return DPP_SE_RC_FUN_INVALID;                                                        \
+		} else if ((p_func_id)->fun_type != (type)) {                                            \
+			ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],type Fun_id is invalid",                       \
+								  DPP_SE_RC_FUN_INVALID);                                        \
+			return DPP_SE_RC_FUN_INVALID;                                                        \
+		}                                                                                        \
+	} while (0)
+
+#define DPP_SE_CHECK_FUN_MEMORY_FREE(p_func_id, id, type, ptr)                                   \
+	do {                                                                                         \
+		if (!(p_func_id)->is_used) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                               \
+					"\n Error[0x%x],is_used Fun_id is invalid,(p_func_id)->is_used is [%d]",     \
+					DPP_SE_RC_FUN_INVALID, (p_func_id)->is_used);                                \
+			ZXIC_COMM_FREE(ptr);                                                                 \
+			return DPP_SE_RC_FUN_INVALID;                                                        \
+		} else if ((p_func_id)->fun_id != (id)) {                                                \
+			ZXIC_COMM_TRACE_ERROR(                                                               \
+					"\n Error[0x%x],fun_id != (id) Fun_id is invalid;p_func_id->fun_id is [%d]", \
+					DPP_SE_RC_FUN_INVALID, (p_func_id)->fun_id);                                 \
+			ZXIC_COMM_FREE(ptr);                                                                 \
+			return DPP_SE_RC_FUN_INVALID;                                                        \
+		} else if (!(p_func_id)->fun_ptr) {                                                      \
+			ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],fun_ptr Fun_id is invalid",                    \
+								  DPP_SE_RC_FUN_INVALID);                                        \
+			ZXIC_COMM_FREE(ptr);                                                                 \
+			return DPP_SE_RC_FUN_INVALID;                                                        \
+		} else if ((p_func_id)->fun_type != (type)) {                                            \
+			ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],type Fun_id is invalid",                       \
+								  DPP_SE_RC_FUN_INVALID);                                        \
+			ZXIC_COMM_FREE(ptr);                                                                 \
+			return DPP_SE_RC_FUN_INVALID;                                                        \
+		}                                                                                        \
+	} while (0)
+
+#define DPP_SE_CHECK_FUN_MUTEX_UNLOCK(p_func_id, id, type, mutex)                                \
+	do {                                                                                         \
+		if (!(p_func_id)->is_used) {                                                             \
+			ZXIC_COMM_TRACE_ERROR(                                                               \
+					"\n Error[0x%x],is_used Fun_id is invalid,(p_func_id)->is_used is [%d]",     \
+					DPP_SE_RC_FUN_INVALID, (p_func_id)->is_used);                                \
+			zxic_comm_mutex_unlock(mutex);                                                       \
+			return DPP_SE_RC_FUN_INVALID;                                                        \
+		} else if ((p_func_id)->fun_id != (id)) {                                                \
+			ZXIC_COMM_TRACE_ERROR(                                                               \
+					"\n Error[0x%x],fun_id != (id) Fun_id is invalid;p_func_id->fun_id is [%d]", \
+					DPP_SE_RC_FUN_INVALID, (p_func_id)->fun_id);                                 \
+			zxic_comm_mutex_unlock(mutex);                                                       \
+			return DPP_SE_RC_FUN_INVALID;                                                        \
+		} else if (!(p_func_id)->fun_ptr) {                                                      \
+			ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],fun_ptr Fun_id is invalid",                    \
+								  DPP_SE_RC_FUN_INVALID);                                        \
+			zxic_comm_mutex_unlock(mutex);                                                       \
+			return DPP_SE_RC_FUN_INVALID;                                                        \
+		} else if ((p_func_id)->fun_type != (type)) {                                            \
+			ZXIC_COMM_TRACE_ERROR("\n Error[0x%x],type Fun_id is invalid",                       \
+								  DPP_SE_RC_FUN_INVALID);                                        \
+			zxic_comm_mutex_unlock(mutex);                                                       \
+			return DPP_SE_RC_FUN_INVALID;                                                        \
+		}                                                                                        \
+	} while (0)
+
+#define DPP_SE_HW_POS(x) (SE_RAM_WIDTH - 1 - (x))
+
+#define DPP_SE_ZBLK_OUT_DDR_V6_START (0)
+#define DPP_SE_ZBLK_OUT_DDR_V6_END (0)
+
+#define DPP_SE_ZBLK_OUT_DDR_V4_START (0)
+#define DPP_SE_ZBLK_OUT_DDR_V4_END (0)
+
+#define DPP_SE_ZBLK_SERVICE_TYPE_START (3)
+#define DPP_SE_ZBLK_SERVICE_TYPE_END (3)
+
+#define DPP_SE_ZBLK_HASH_CHAN_START (2)
+#define DPP_SE_ZBLK_HASH_CHAN_END (1)
+
+#define DPP_SE_ZBLK_HW_POS_EN_START (0)
+#define DPP_SE_ZBLK_HW_POS_EN_END (0)
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/tm/dpp_tm.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/tm/dpp_tm.h
old mode 100755
new mode 100644
index 35c2a9024fc03cd336226d8d0b041468e5db4114..6360c4db9864a28f7c0486bb6e1ea9c3519018ab
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/tm/dpp_tm.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/module/tm/dpp_tm.h
@@ -1,4917 +1,4798 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_tm.h
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : djf
-* 完成日期 : 2014/02/25
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-#ifndef  _DPP_ETM_H_
-#define  _DPP_ETM_H_
-
-
-#include "dpp_tm_api.h"
-#include "dpp_etm_reg.h"
-#if ZXIC_REAL("ETM_MACRO")
-/******************************************************************************
- *                               START: 宏定义                                *
- *****************************************************************************/
-#define ETM_WRITE_CHECK (1)
-#define DPP_TM_CGAVD_KILO_UL   (1024)/* Kbyte和byte换算 */
-#define DPP_TM_CGAVD_TD_MAX (16*512)
-/* CIR颗粒度: bps */
-#define DPP_TM_SHAPE_CIR_STEP  ((ZXIC_DOUBLE) 400 * 1000 * 1000 * 1000 / 0x3FFFFFE)
-//#define DPP_TM_SHAPE_CIR_STEP  (160069565217 / 0x3FFFFFE)
-/* EIR颗粒度: bps */
-//define DPP_TM_SHAPE_EIR_STEP  ((ZXIC_FLOAT) 160 * 1000 * 1000 * 1000 / 0x3FFFFFE)
-#define DPP_TM_SHAPE_EIR_STEP  (160 * 1000 * 1000 * 1000 / 0x3FFFFFE)
-#define DPP_TM_SHAPE_DEFAULT_CBS   (20)/*寄存器写入CBS的最小值，小于该值时，整形不准*/
-#define DPP_TM_KILO_UL   (1024)
-#define DPP_TM_KILO_ULL   (1000)
-#define DPP_TM_QMU_PORT_SHAP_MAG (1.03)
-#define DPP_ETM_SA_EGRS_MAX_PORTID   (66)
-/*cfgmt_byte_mode:0:block mode 1:byte mode*/
-#define DPP_TM_CGAVD_BLOCK_MODE   (0)
-#define DPP_TM_CGAVD_ZXIC_UINT8_MODE   (1)
-
-/*shap整形模板最大值:每2K流或调度器一一映射一块令牌桶资源,每块资源拥有0-127个模板*/
-/*ETM 0xABFF/2K = 21 */
-#define DPP_ETM_SHAP_TABEL_ID_MAX (22)
-/*FTM 0x17FF/2K = 2 */
-#define DPP_FTM_SHAP_TABEL_ID_MAX (3)
-#define DPP_TM_SHAP_MAP_ID_MAX (128)
-
-/******************************************************************************
- *                                END: 宏定义                                 *
- *****************************************************************************/
-#endif /* ETM_MACRO */
-
-
-
-#if ZXIC_REAL("ETM_STRUCT")
-/******************************************************************************
- *                              START: 类型定义                               *
- *****************************************************************************/
-/* block长度模式 */
-typedef enum dpp_tm_blk_size_e
-{
-    DPP_ETM_BLK_SIZE_128_B = 0,
-    DPP_ETM_BLK_SIZE_256_B,
-    DPP_ETM_BLK_SIZE_512_B,
-    DPP_ETM_BLK_SIZE_1024_B,
-    DPP_ETM_BLK_SIZE_INVALID
-} DPP_ETM_BLK_SIZE_E;
-
-/* 动态门限放大因子参数 */
-typedef struct dpp_tm_amplify_gene_para_t
-{
-    ZXIC_UINT32 amplify_gene[16];
-} DPP_ETM_AMPLIFY_GENE_PARA_T;
-
-/* 等价包长阈值 */
-typedef struct dpp_tm_equal_pkt_len_th_para_t
-{
-    ZXIC_UINT32 equal_pkt_len_th[7];
-} DPP_ETM_EQUAL_PKT_LEN_TH_PARA_T;
-
-/* 等价包长*/
-typedef struct dpp_tm_equal_pkt_len_para_t
-{
-    ZXIC_UINT32 equal_pkt_len[8];
-} DPP_ETM_EQUAL_PKT_LEN_PARA_T;
-
-/*ETM_STRUCT_STAT */
-typedef enum dpp_tm_cgavd_stat_qnum_e
-{
-    DPP_ETM_CGAVD_STAT_QNUM1 = 0,
-    DPP_ETM_CGAVD_STAT_QNUM2 = 1,
-    DPP_ETM_CGAVD_STAT_QNUM_INVALID
-} DPP_ETM_CGAVD_STAT_QNUM_E;
-
-typedef enum dpp_tm_cgavd_stat_mode_e
-{
-    DPP_ETM_CGAVD_STAT_ALL_QUEUE = 0,
-    DPP_ETM_CGAVD_STAT_ONE_QUEUE = 1,
-    DPP_ETM_CGAVD_STAT_MODE_INVALID
-} DPP_ETM_CGAVD_STAT_MODE_E;
-
-
-typedef struct dpp_tm_cgavd_stat_para_t
-{
-    DPP_ETM_CGAVD_STAT_MODE_E mode;
-    ZXIC_UINT32 q_id;
-} DPP_ETM_CGAVD_STAT_PARA_T;
-
-typedef struct dpp_tm_cgavd_stat_info_t
-{
-    DPP_ETM_CGAVD_STAT_MODE_E mode;
-    ZXIC_UINT32 q_id;
-    ZXIC_UINT32 lif_in_pkt_num;
-    ZXIC_UINT32 enqueue_pkt_num;
-    ZXIC_UINT32 dequeue_pkt_num;
-    ZXIC_UINT32 td_drop_pkt_num;
-    ZXIC_UINT32 wred_drop_pkt_num;
-    ZXIC_UINT32 wred_dpi_pkt_num[8];
-    ZXIC_UINT32 gred_drop_pkt_num;
-    ZXIC_UINT32 gred_dpi_pkt_num[8];
-} DPP_ETM_CGAVD_STAT_INFO_T;
-
-typedef struct dpp_tm_qmu_stat_info_t
-{
-    ZXIC_UINT32 fc_cnt_mode;
-    ZXIC_UINT32 mmu_qmu_wr_fc_cnt;
-    ZXIC_UINT32 mmu_qmu_rd_fc_cnt;
-    ZXIC_UINT32 qmu_cgavd_fc_cnt;
-    ZXIC_UINT32 cgavd_qmu_pkt_cnt;
-    ZXIC_UINT32 cgavd_qmu_pktlen_all;
-    ZXIC_UINT32 cgavd_qmu_drop_tap;
-    ZXIC_UINT32 last_drop_qnum;
-    ZXIC_UINT32 crdt_qmu_credit_cnt;
-    ZXIC_UINT32 qmu_to_qsch_report_cnt;
-    ZXIC_UINT32 qmu_to_cgavd_report_cnt;
-    ZXIC_UINT32 qmu_crdt_crs_normal_cnt;
-    ZXIC_UINT32 qmu_crdt_crs_off_cnt;
-    ZXIC_UINT32 qsch_qlist_shedule_cnt;
-    ZXIC_UINT32 qsch_qlist_sch_ept_cnt;
-    ZXIC_UINT32 qmu_to_mmu_blk_wr_cnt;
-    ZXIC_UINT32 qmu_to_csw_blk_rd_cnt;
-    ZXIC_UINT32 qmu_to_mmu_sop_wr_cnt;
-    ZXIC_UINT32 qmu_to_mmu_eop_wr_cnt;
-    ZXIC_UINT32 qmu_to_mmu_drop_wr_cnt;
-    ZXIC_UINT32 qmu_to_csw_sop_rd_cnt;
-    ZXIC_UINT32 qmu_to_csw_eop_rd_cnt;
-    ZXIC_UINT32 qmu_to_csw_drop_rd_cnt;
-    ZXIC_UINT32 mmu_to_qmu_wr_release_cnt;
-    ZXIC_UINT32 mmu_to_qmu_rd_release_cnt;
-} DPP_ETM_QMU_STAT_INFO_T;
-
-typedef struct dpp_tm_qmu_spec_q_stat_info_t
-{
-    ZXIC_UINT32 observe_portfc_spec;
-    ZXIC_UINT32 spec_lif_portfc_count;
-    ZXIC_UINT32 observe_qnum_set;
-    ZXIC_UINT32 spec_q_pkt_received;
-    ZXIC_UINT32 spec_q_pkt_dropped;
-    ZXIC_UINT32 spec_q_pkt_scheduled;
-    ZXIC_UINT32 spec_q_wr_cmd_sent;
-    ZXIC_UINT32 spec_q_rd_cmd_sent;
-    ZXIC_UINT32 spec_q_pkt_enq;
-    ZXIC_UINT32 spec_q_pkt_deq;
-    ZXIC_UINT32 spec_q_crdt_uncon_received;
-    ZXIC_UINT32 spec_q_crdt_cong_received;
-    ZXIC_UINT32 spec_q_crs_normal_cnt;
-    ZXIC_UINT32 spec_q_crs_off_cnt;
-} DPP_ETM_QMU_SPEC_Q_STAT_INFO_T;
-
-typedef struct dpp_tm_qmu_spec_bat_stat_info_t
-{
-    ZXIC_UINT32 observe_batch_set;
-    ZXIC_UINT32 spec_bat_pkt_received;
-    ZXIC_UINT32 spec_bat_pkt_dropped;
-    ZXIC_UINT32 spec_bat_blk_scheduled;
-    ZXIC_UINT32 spec_bat_wr_cmd_sent;
-    ZXIC_UINT32 spec_bat_rd_cmd_sent;
-    ZXIC_UINT32 spec_bat_pkt_enq;
-    ZXIC_UINT32 spec_bat_pkt_deq;
-    ZXIC_UINT32 spec_bat_crdt_uncon_received;
-    ZXIC_UINT32 spec_bat_crdt_cong_received;
-    ZXIC_UINT32 spec_bat_crs_normal_cnt;
-    ZXIC_UINT32 spec_bat_crs_off_cnt;
-} DPP_ETM_QMU_SPEC_BAT_STAT_INFO_T;
-
-typedef struct qmu_port_shape_para
-{
-    ZXIC_UINT32 shape_value_amplified;
-    ZXIC_UINT32 token_add_num;
-    ZXIC_UINT32 token_gap;
-} QMU_PORT_SHAPE_PARA;
-
-/*etm 实际使用的ddr_attach、bank_num、depth(mmu中看到的)*/
-typedef struct dpp_etm_qmu_init_para
-{
-    ZXIC_UINT32 etm_mmu_ddr_attach;
-    ZXIC_UINT32 etm_mmu_bank_num;
-    ZXIC_UINT32 etm_mmu_depth;
-} DPP_ETM_QMU_INIT_PARA;
-
-/*ftm 实际使用的ddr_attach、bank_num、depth(mmu中看到的)*/
-typedef struct dpp_ftm_qmu_init_para
-{
-    ZXIC_UINT32 ftm_mmu_ddr_attach;
-    ZXIC_UINT32 ftm_mmu_bank_num;
-    ZXIC_UINT32 ftm_mmu_depth;
-} DPP_FTM_QMU_INIT_PARA;
-
-typedef struct dpp_tm_crdt_spwfq_start_num_t
-{
-    ZXIC_UINT32 start_num_fq;
-    ZXIC_UINT32 start_num_fq2;
-    ZXIC_UINT32 start_num_fq4;
-    ZXIC_UINT32 start_num_fq8;
-    ZXIC_UINT32 start_num_sp;
-    ZXIC_UINT32 start_num_wfq;
-    ZXIC_UINT32 start_num_wfq2;
-    ZXIC_UINT32 start_num_wfq4;
-    ZXIC_UINT32 start_num_wfq8;
-} DPP_TM_CRDT_SPWFQ_START_NUM_T;
-
-
-/******************************************************************************
- *                               END: 类型定义                                *
- *****************************************************************************/
-#endif
-
-
-
-#if ZXIC_REAL("ETM_FUNCTION")
-/******************************************************************************
- *                              START: 函数声明                               *
- *****************************************************************************/
-/***********************************************************/
-/** 打印指定的全局数组值以及清空全局数组
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   para_x   数组index_x
-* @param   para_y   数组index_y
-* @param   clear_flag 清空shape全局数组
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark
-* @see
-* @author  xuhb      @date  2019/06/10
-************************************************************/
-DPP_STATUS dpp_tm_shape_para_array_prt(ZXIC_UINT32 dev_id,
-                                       ZXIC_UINT32 para_x,
-                                       ZXIC_UINT32 para_y,
-                                       ZXIC_UINT32 clear_flag);
-
-DPP_STATUS dpp_tm_qmu_qlist_set(ZXIC_UINT32 dev_id,
-                                ZXIC_UINT32 ddr_num,
-                                ZXIC_UINT32 bank_num_para,
-                                ZXIC_UINT32 bank_vld,
-                                ZXIC_UINT32 gene_para);
-
-DPP_STATUS dpp_tm_cgavd_td_th_together_wr(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 level,
-                                          ZXIC_UINT32 id,
-                                          ZXIC_UINT32 td_th,
-                                          ZXIC_UINT32 num);
-
-
-DPP_STATUS dpp_tm_cgavd_td_th_together_get(DPP_DEV_T *dev,
-                                           ZXIC_UINT32 level,
-                                           ZXIC_UINT32 id,
-                                           ZXIC_UINT32 num);
-
-DPP_STATUS dpp_tm_cgavd_dyn_th_en_set_more(DPP_DEV_T *dev,
-                                           DPP_TM_CGAVD_LEVEL_E level,
-                                           ZXIC_UINT32 id,
-                                           ZXIC_UINT32 en,
-                                           ZXIC_UINT32 num);
-
-/***********************************************************/
-/**  配置基于优先级的QMU接收NPPU数据的fifo阈值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sp  优先级0~7
-* @param   th  指定优先级的fifo阈值0~511，单位为fifo条目，fifo深度512
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_move_drop_sp_th_set(ZXIC_UINT32 dev_id,
-                                            ZXIC_UINT32 sp,
-                                            ZXIC_UINT32 th);
-
-
-DPP_STATUS dpp_tm_wred_dp_line_para_wr(ZXIC_UINT32 dev_id,
-                                       ZXIC_UINT32 level,
-                                       ZXIC_UINT32 wred_id,
-                                       ZXIC_UINT32 dp,
-                                       ZXIC_UINT32 max_th,
-                                       ZXIC_UINT32 min_th,
-                                       ZXIC_UINT32 max_p,
-                                       ZXIC_UINT32 weight,
-                                       ZXIC_UINT32 q_len_th);
-
-
-DPP_STATUS dpp_tm_gred_dp_line_para_wr(ZXIC_UINT32 dev_id,
-                                       ZXIC_UINT32 dp,
-                                       ZXIC_UINT32 max_th,
-                                       ZXIC_UINT32 mid_th,
-                                       ZXIC_UINT32 min_th,
-                                       ZXIC_UINT32 max_p,
-                                       ZXIC_UINT32 weight,
-                                       ZXIC_UINT32 q_len_th);
-
-DPP_STATUS dpp_tm_crdt_idle_check(DPP_DEV_T *dev);
-
-/***********************************************************/
-/** 获取各调度器的起始编号（etm共25K=25600,ftm共1920个）
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_spwfq_start_num  调度器起始编号结构体
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/28
-************************************************************/
-DPP_STATUS dpp_tm_crdt_wfqsp_get(DPP_DEV_T *dev,
-                                 DPP_TM_CRDT_SPWFQ_START_NUM_T *p_spwfq_start_num);
-
-/***********************************************************/
-/** 获取调度器挂接配置参数
-* @param   dev_id      设备编号
-* @param   tm_type     0-ETM,1-FTM
-* @param   se_id       调度器编号
-* @param   p_se_para_tbl  调度器参数
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_para_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id, DPP_ETM_CRDT_SE_PARA_TBL_T *p_se_para_tbl);
-
-
-
-/***********************************************************/
-/** 配置QMU工作模式，2M节点或4M节点
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   mode   0-第一种工作模式2M节点，1-第二种工作模式4M节点
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_qmu_work_mode_set(DPP_DEV_T *dev, DPP_TM_QMU_WORK_MODE_E mode);
-
-/***********************************************************/
-/** 读取QMU工作模式，2M节点或4M节点
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_mode   0-第一种工作模式2M节点，1-第二种工作模式4M节点
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_qmu_work_mode_get(DPP_DEV_T *dev, DPP_TM_QMU_WORK_MODE_E *p_mode);
-
-/***********************************************************/
-/** 配置本地sa_id，SA模式下需要配置
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sa_id   配置的sa_id值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25    ftm模式下使用
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_local_sa_id_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 sa_id);
-
-/***********************************************************/
-/** 读取本地sa_id，SA模式下有效
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_sa_id   读取的sa_id值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_local_sa_id_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_sa_id);
-
-/***********************************************************/
-/** CPU设置的各级队列深度配置
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level      拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   q_len_use_cpu_set_en   0：选取RAM中读出的队列深度；
-* @param                          1：选取q_len_cpu_set值
-* @param   q_len_cpu_set    CPU设置的各级队列深度,单位为block。
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_q_len_use_cpu_set(DPP_DEV_T *dev,
-                                    DPP_TM_CGAVD_LEVEL_E level,
-                                    ZXIC_UINT32 q_len_use_cpu_set_en,
-                                    ZXIC_UINT32 q_len_cpu_set);
-
-/***********************************************************/
-/** CPU设置的各级平均队列深度配置
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level      拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   q_avg_len_use_cpu_set_en   0：选取RAM中读出的队列深度；
-* @param                              1：选取q_avg_len_cpu_set值
-* @param   q_avg_len_cpu_set    CPU设置的各级平均队列深度。
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_q_avg_len_use_cpu_set(DPP_DEV_T *dev,
-                                        DPP_TM_CGAVD_LEVEL_E level,
-                                        ZXIC_UINT32 q_avg_len_use_cpu_set_en,
-                                        ZXIC_UINT32 q_avg_len_cpu_set);
-
-/***********************************************************/
-/** 配置QMU查询队列Qos开关
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   q_id:  队列号
-* @param   qos_sign: qos开关 0:关闭  1:开启
-* @param
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/03
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qos_sign_set(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 q_id,
-                                   ZXIC_UINT32 qos_sign);
-
-/***********************************************************/
-/** 配置授权分发使能或者关闭
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   配置的值，0-关闭授权分发，1-使能授权分发
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_crdt_credit_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en);
-
-/***********************************************************/
-/** 读取授权分发使能或者关闭
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_en   读出的值，0-关闭授权分发，1-使能授权分发
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_crdt_credit_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en);
-
-/***********************************************************/
-/** 配置授权产生间隔
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   crdt_space_choose  授权发送间隔 0:固定16个周期 1：查表
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/10
-************************************************************/
-DPP_STATUS dpp_tm_crdt_space_choose_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crdt_space_choose);
-
-/***********************************************************/
-/** 获得授权产生间隔
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   crdt_space_choose   授权发送间隔 0:固定16个周期 1：查表
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/10
-************************************************************/
-DPP_STATUS dpp_tm_crdt_space_choose_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_crdt_space_choose);
-
-/***********************************************************/
-/** 配置端口拥塞令牌桶使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   port_id   端口号：0~63
-* @param   port_en   端口拥塞令牌桶使能，1表示不使用拥塞令牌桶的授权，0表示可以使用拥塞令牌桶授权
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/11
-************************************************************/
-DPP_STATUS dpp_tm_crdt_port_congest_en_set(DPP_DEV_T *dev,
-                                           ZXIC_UINT32 port_id,
-                                           ZXIC_UINT32 port_en);
-
-/***********************************************************/
-/** 获得端口拥塞令牌桶使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   port_id   端口号：0~120
-* @param   p_port_en   端口拥塞令牌桶使能，1表示不使用拥塞令牌桶的授权，0表示可以使用拥塞令牌桶授权
-*
-* @return
-* @remark  无
-* @see
-* @author  djf      @date  2015/03/11
-************************************************************/
-DPP_STATUS dpp_tm_crdt_port_congest_en_get(DPP_DEV_T *dev,
-                                           ZXIC_UINT32 port_id,
-                                           ZXIC_UINT32 *p_port_en);
-
-/***********************************************************/
-/** 流级中间级补充扫描机制使能配置
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   renew_scan_flow:0为不开启补充扫描  others:开启补充扫描，扫描间隔
-* @param   renew_scan_mid:0为不开启补充扫描  others:开启补充扫描，扫描间隔
-* @param
-* @return
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/03
-************************************************************/
-DPP_STATUS dpp_tm_crdt_renew_scan_set(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 renew_scan_flow,
-                                      ZXIC_UINT32 renew_scan_mid);
-
-/***********************************************************/
-/** 获取流级中间级补充扫描机制使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   renew_scan_flow:0为不开启补充扫描  others:开启补充扫描，扫描间隔
-* @param   renew_scan_mid:0为不开启补充扫描  others:开启补充扫描，扫描间隔
-* @param
-* @return
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/03
-************************************************************/
-DPP_STATUS dpp_tm_crdt_renew_scan_get(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 *renew_scan_flow,
-                                      ZXIC_UINT32 *renew_scan_mid);
-
-
-/***********************************************************/
-/**cpu配置flow_id的crs强制为normal或者off开关使能，用于检测SA模式下队列到授权流的多对一问题
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id:流号(和授权流号一一对应)
-*                en   强制配置crs的使能，0-不使能，1-使能
-*                crs_value:强制配置crs的值2'b00:off; 2'b01:low; 2'b10:normal；
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/04/25
-************************************************************/
-DPP_STATUS dpp_tm_crdt_crs_sheild_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 flow_id, ZXIC_UINT32 en, ZXIC_UINT32 crs_value);
-
-
-/***********************************************************/
-/**获取flow_id的crs强制为normal或者off开关使能，用于检测SA模式下队列到授权流的多对一问题
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id:流号(和授权流号一一对应)
-*                en   强制配置crs的使能，0-不使能，1-使能
-*                crs_value:强制配置crs的值2'b00:off; 2'b01:low; 2'b10:normal；
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/04/25
-************************************************************/
-DPP_STATUS dpp_tm_crdt_crs_sheild_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_flow_id, ZXIC_UINT32 *p_en, ZXIC_UINT32 *p_crs_value);
-
-/***********************************************************/
-/** 控制授权速率的门限
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   index   0~6
-* @param   rci_grade_th_0_data
-*
-* @return
-* @remark  无
-* @see
-* @author  wush      @date  2017/10/17
-************************************************************/
-DPP_STATUS dpp_tm_crdt_rci_grade_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 index, ZXIC_UINT32 rci_grade_th_0_data);
-
-DPP_STATUS dpp_tm_crdt_rci_grade_th_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 index, ZXIC_UINT32 *p_rci_grade_th_0_data);
-
-
-/***********************************************************/
-/** 控制授权间隔的门限，建议大于等于0XF，不可取0；
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   index   0~7
-* @param   asm_interval_0_data   控制授权间隔的门限，建议大于等于0XF，不可取0；
-*
-* @return
-* @remark  无
-* @see
-* @author  wush      @date  2017/10/17
-************************************************************/
-DPP_STATUS dpp_tm_crdt_asm_interval_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 index, ZXIC_UINT32 asm_interval_0_data);
-
-DPP_STATUS dpp_tm_crdt_asm_interval_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 index, ZXIC_UINT32 *p_asm_interval_0_data);
-
-
-/***********************************************************/
-/** rci的级别
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_rci_grade_data
-*
-* @return
-* @remark  无
-* @see
-* @author  wush      @date  2017/10/17
-************************************************************/
-DPP_STATUS dpp_tm_crdt_rci_grade_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_rci_grade_data);
-
-DPP_STATUS dpp_tm_crdt_rci_value_r_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_crdt_rci_value_r_data);
-
-DPP_STATUS dpp_tm_crdt_interval_now_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_crdt_interval_now_data);
-
-
-/***********************************************************/
-/** 配置crdt interval使能，
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   crdt_interval_en_cfg_data   授权分发间隔使能，1打开，0关闭
-*
-* @return
-* @remark  无
-* @see
-* @author  wush      @date  2017/03/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_interval_en_cfg_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crdt_interval_en_cfg_data);
-
-/***********************************************************/
-/**配置拥塞状态(有效链路数+UCN等级)到授权产生间隔的映射表
-* @param   dev_id   设备编号
-* @param   valid_serdes_num   有效的链路数(0~32)
-* @param   ucn_level   UCN等级(0~7)
-* @param   cr_clk   授权产生间隔(0~0x3fffff)
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2017/03/28
-************************************************************/
-DPP_STATUS dpp_tm_crdt_cfgmt_interval_set(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 valid_serdes_num,
-                                          ZXIC_UINT32 ucn_level,
-                                          ZXIC_UINT32 cr_clk);
-
-/***********************************************************/
-/** 读取crdt interval使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   crdt_interval_en_cfg_data   授权分发间隔使能，1打开，0关闭
-*
-* @return
-* @remark  无
-* @see
-* @author  wush      @date  2017/03/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_interval_en_cfg_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_crdt_interval_en_cfg_data);
-
-
-/***********************************************************/
-/** 屏蔽ucn/asm_rdy的时能信号
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   ucn_rdy_shield_en   是否屏蔽ucn_rdy信号，1屏蔽，0不屏蔽
-* @param   asm_rdy_shield_en   是否屏蔽asm_rdy信号，1屏蔽，0不屏蔽
-*
-* @return
-* @remark  无
-* @see
-* @author  wush      @date  2017/10/17
-************************************************************/
-DPP_STATUS dpp_tm_crdt_ucn_asm_rdy_shield_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ucn_rdy_shield_en, ZXIC_UINT32 asm_rdy_shield_en);
-
-DPP_STATUS dpp_tm_crdt_ucn_asm_rdy_shield_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_ucn_rdy_shield_en, ZXIC_UINT32 *p_asm_rdy_shield_en);
-
-
-/***********************************************************/
-/** 配置QMU队列授权价值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   credit_value   授权价值，默认值是400Byte
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_credit_value_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 credit_value);
-
-/***********************************************************/
-/** QMU DDR随机模式时，DDR随机组配置
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   ddr_num   ddr组数，1-6组
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_ddr_rand_grp_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_num);
-
-/***********************************************************/
-/** 配置QMU DDR BANK随机模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   ddr_random   模式:0-轮询模式；1-随机模式
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_ddr_random_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_random);
-
-/***********************************************************/
-/** QMU配置完成寄存器，在QMU链表和DDR随机模式寄存器写入后，将此寄存器写1，完成QMU配置
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_cfg_done_set(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** 配置CRS的e桶产生的crbal门限值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   index   crs组数：0~15
-* @param   crs_th   CRS产生的crbal门限值
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2021/02/14
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_eir_th_set(ZXIC_UINT32 dev_id,
-                                 ZXIC_UINT32 index,
-                                 ZXIC_UINT32 crs_th);
-
-
-/***********************************************************/
-/** 配置CRS产生的crbal门限值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   index   crs组数：0~15
-* @param   crs_th   CRS产生的crbal门限值
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/11
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_th_set(ZXIC_UINT32 dev_id,
-                                 ZXIC_UINT32 index,
-                                 ZXIC_UINT32 crs_th);
-
-/***********************************************************/
-/** 配置CRS产生的空队列确保门限值
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   que_type   队列类型编号(0~15)
-* @param   empty_que_ack_th   空队列确保授权门限
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_th2_set(ZXIC_UINT32 dev_id,
-                                  ZXIC_UINT32 que_type,
-                                  ZXIC_UINT32 empty_que_ack_th);
-
-/***********************************************************/
-/** 配置QMU端口间交织模式
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   pkt_blk_mode   交织模式: 1-按包交织; 0-按block交织SA模式只能配置为1
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  szq      @date  2015/03/25
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pkt_blk_mode_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 pkt_blk_mode);
-
-/***********************************************************/
-/** 获取QMU端口间交织模式
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_pkt_blk_mode   交织模式: 0-按包交织; 1-按block交织SA模式只能配置为1
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  szq      @date  2015/03/25
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pkt_blk_mode_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_pkt_blk_mode);
-
-/***********************************************************/
-/** 配置读命令老化使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   aged_en   读命令老化使能：0：不使能；1：使能
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/11
-************************************************************/
-DPP_STATUS dpp_tm_qmu_wr_aged_en_set(DPP_DEV_T *dev, ZXIC_UINT32 aged_en);
-
-/***********************************************************/
-/** 配置读命令老化速率
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   scan_time   读命令老化速率（扫描间隔时间）
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/11
-************************************************************/
-DPP_STATUS dpp_tm_qmu_wr_aged_scan_time_set(DPP_DEV_T *dev, ZXIC_UINT32 scan_time);
-
-/***********************************************************/
-/** 获得读命令老化速率
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_scan_time   读命令老化速率（扫描间隔时间）
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/11
-************************************************************/
-DPP_STATUS dpp_tm_qmu_wr_aged_scan_time_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_scan_time);
-
-
-/***********************************************************/
-/** 配置QMU队列到目的SAId的映射ETM 模式没有，
-FTM 模式才有1024个。
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   que_id   队列号
-* @param   dest_said   目的said
-*
-* @return   0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  szq      @date  2015/04/08
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qcfg_dest_id_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id, ZXIC_UINT32 dest_said);
-
-
-/***********************************************************/
-/** 获取QMU队列到目的SAId的映射ETM 模式没有，
-FTM 模式才有1024个。
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   que_id   队列号
-* @param   p_dest_said   目的said
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  szq      @date  2015/04/08
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qcfg_dest_id_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id, ZXIC_UINT32 *p_dest_said);
-
-/***********************************************************/
-/** 配置出队暂存使用的进程总数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   used_inall   出队暂存使用的进程总数=19-N，默认3表示使用16个进程
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/18
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pid_use_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 used_inall);
-
-/***********************************************************/
-/** 获得出队暂存使用的进程总数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_used_inall   出队暂存使用的进程总数=19-N，默认3表示使用16个进程
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pid_use_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_used_inall);
-
-/***********************************************************/
-/** 配置出队暂存自回加进程总数阈值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   round_th   出队暂存自回加进程总数阈值=19-N，默认4表示使用15个进程就自回加
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/18
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pid_round_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 round_th);
-
-/***********************************************************/
-/** 获得出队暂存自回加进程总数阈值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_round_th   出队暂存自回加进程总数阈值=19-N，默认4表示使用15个进程就自回加
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-
-DPP_STATUS dpp_tm_qmu_pid_round_th_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_round_th);
-
-/***********************************************************/
-/** 配置CRS发送强制使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   配置的值，0-不使能，1-使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_force_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en);
-
-/***********************************************************/
-/** 配置CRS发送强制的队列
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   q_id   队列号
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_force_q_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 q_id);
-
-
-/***********************************************************/
-/** 配置CRS发送强置的状态
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   crs_state   CRS发送强置的状态
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/18
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_force_state_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crs_state);
-
-/***********************************************************/
-/** 配置特定队列发送特定CRS
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   队列号
-*               qcfg_qsch_crs_force_crs:CRS状态(0：off；1：normal。)
-                 qcfg_qsch_crs_force_en:CRS发送强置使能(0：不使能；1：使能。)
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qnum_crs_force(ZXIC_UINT32 dev_id,
-                                     ZXIC_UINT32 qnum,
-                                     ZXIC_UINT32 qcfg_qsch_crs_force_crs,
-                                     ZXIC_UINT32 qcfg_qsch_crs_force_en);
-
-
-/***********************************************************/
-/** 配置CRS状态
-* @param   dev_id  设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   队列号
-* @param   state
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_state_set(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 qnum,
-                                    ZXIC_UINT32 state);
-
-/***********************************************************/
-/** 获得CRS状态
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   队列号
-* @param   p_state
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_state_get(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 qnum,
-                                    ZXIC_UINT32 *p_state);
-
-/***********************************************************/
-/** 配置自动授权队列范围
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   first_que   自授权起始队列号
-* @param   last_que   自授权终止队列号
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_qmu_auto_credit_que_set(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 first_que,
-                                          ZXIC_UINT32 last_que);
-
-/***********************************************************/
-/** 获得自动授权队列范围
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_first_que   自授权起始队列号
-* @param   p_last_que   自授权终止队列号
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_auto_credit_que_get(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 *p_first_que,
-                                          ZXIC_UINT32 *p_last_que);
-
-/***********************************************************/
-/** 配置自动授权开启使能及扫描速率
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   auto_crdt_en   自动授权开启使能，默认关闭。0：关闭；1：开启
-* @param   auto_crdt_rate   自授权速率配置
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_qmu_auto_credit_rate_set(DPP_DEV_T *dev,
-                                           ZXIC_UINT32 auto_crdt_en,
-                                           ZXIC_UINT32 auto_crdt_rate);
-
-/***********************************************************/
-/** 获得自动授权开启使能及扫描速率
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_auto_crdt_en   自动授权开启使能，默认关闭。0：关闭；1：开启
-* @param   p_auto_crdt_rate   自授权速率配置
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_auto_credit_rate_get(DPP_DEV_T *dev,
-                                           ZXIC_UINT32 *p_auto_crdt_en,
-                                           ZXIC_UINT32 *p_auto_crdt_rate);
-
-/***********************************************************/
-/** 配置授权丢弃使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   all_drop_en   所有授权丢弃使能：1：允许丢弃所有授权；0：仅允许丢弃拥塞授权
-* @param   drop_en   授权丢弃使能：1：允许丢弃授权；0：禁止丢弃授权
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crbal_drop_en_set(ZXIC_UINT32 dev_id,
-                                        ZXIC_UINT32 all_drop_en,
-                                        ZXIC_UINT32 drop_en);
-
-/***********************************************************/
-/** 获得授权丢弃使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_all_drop_en   所有授权丢弃使能：1：允许丢弃所有授权；0：仅允许丢弃拥塞授权
-* @param   p_drop_en   授权丢弃使能：1：允许丢弃授权；0：禁止丢弃授权
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crbal_drop_en_get(ZXIC_UINT32 dev_id,
-                                        ZXIC_UINT32 *p_all_drop_en,
-                                        ZXIC_UINT32 *p_drop_en);
-
-/***********************************************************/
-/**设置自然拥塞反压门限值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param
-* @return
-* @remark  无
-* @see
-* @author  yjd     @date  2015/07/16
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qcfg_csch_congest_th_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id, ZXIC_UINT32 qmu_congest_th);
-
-/***********************************************************/
-/**获取自然拥塞反压门限值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param
-* @return
-* @remark  无
-* @see
-* @author  yjd     @date  2015/07/16
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qcfg_csch_congest_th_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id, ZXIC_UINT32 *p_qmu_congest_th);
-
-/***********************************************************/
-/**设置CMD_SCH分优先级反压门限值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param
-* @return
-* @remark  无
-* @see
-* @author  yjd     @date  2015/07/16
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qcfg_csch_sp_fc_th_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id, ZXIC_UINT32 q_pri, ZXIC_UINT32 qmu_sp_fc_th);
-
-/***********************************************************/
-/**获取自然拥塞反压门限值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param
-* @return
-* @remark  无
-* @see
-* @author  yjd     @date  2015/07/16
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qcfg_csch_sp_fc_th_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id, ZXIC_UINT32 q_pri, ZXIC_UINT32 *p_qmu_sp_fc_th);
-
-/***********************************************************/
-/** 配置QMU需要检测流控的端口号
-* @param   dev_id   设备号
-* @param   tm_type   0-ETM,1-FTM
-* @param   port_id   端口号
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/05/07
-************************************************************/
-DPP_STATUS dpp_tm_qmu_observe_portfc_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id);
-
-/***********************************************************/
-/** 配置pfc使能
-* @param   dev_id   设备编号
-* @param   pfc_en   配置的值，0-不使能pfc，1-使能pfc
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lsy      @date  2022/08/22
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pfc_en_set(DPP_DEV_T *dev, ZXIC_UINT32 pfc_en);
-
-/***********************************************************/
-/** 读取pfc使能
-* @param   dev_id   设备编号
-* @param   pfc_en   配置的值，0-不使能pfc，1-使能pfc
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lsy      @date  2022/08/22
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pfc_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *pfc_en);
-
-/***********************************************************/
-/** 配置端口pfc掩码
-* @param   dev_id   设备编号
-* @param   port_id   端口号：0~63
-* @param   port_en   端口掩码配置，1pfc模式下该端口接收olif的优先级反压，
-*                                  0pfc模式下该端口不接受olif的优先级反压，并将反压信号全部置1
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lsy      @date  2022/08/22
-************************************************************/
-DPP_STATUS dpp_tm_qmu_port_pfc_make_set(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 port_id,
-                                        ZXIC_UINT32 port_en);
-
-/***********************************************************/
-/** 获得端口pfc掩码
-* @param   dev_id   设备编号
-* @param   port_id   端口号：0~63
-* @param   port_en   端口掩码配置，1pfc模式下该端口接收olif的优先级反压，
-*                                  0pfc模式下该端口不接受olif的优先级反压，并将反压信号全部置1
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lsy      @date  2022/08/22
-************************************************************/
-DPP_STATUS dpp_tm_qmu_port_pfc_make_get(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 port_id,
-                                        ZXIC_UINT32 *p_port_en);
-
-
-
-/***********************************************************/
-/** QMU初始化配置场景一：4组*2bank，MMU开启rotatjon，MMU实际分配4~7组，每组2~3bank
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_1(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** QMU初始化配置场景一：4组*2bank，MMU开启rotatjon，MMU实际分配0~3组，每组2~3bank
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_1(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** QMU初始化配置场景一ddr4模式，开启MMU/IP rotatjon，tm看到4组*2bank，对应DDR分配4~7组，每组2~3bank*************
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_1(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配4~7组，每组2~3,6~7bank
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_2(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配0~3组，每组2~3,6~7bank*
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_2(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配4~7组，每组2~3,6~7bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_2(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配4~7组，每组2~3,6~7bank
-*    depth=64,代表16k
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_pd16k_2(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth);
-
-
-/***********************************************************/
-/** QMU初始化配置场景二：ddr3模式，8组*8bank
-*    depth=64,代表16k
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/04/12
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_chuk32(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth);
-
-/***********************************************************/
-/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配0~3组，每组2~3,6~7bank*
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_pd16k_2(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth);
-
-
-/***********************************************************/
-/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配4~7组，每组2~3,6~7bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_pd16k_2(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth);
-
-/***********************************************************/
-/** QMU初始化配置场景：ddr3模式，8组ddr*8bank
-* @param   dev_id   设备编号
-* @param   depth   bank depth
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/04/12
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_chuk32(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth);
-
-
-/***********************************************************/
-/** QMU初始化配置场景三：8组*2bank，MMU开启rotatjon，MMU实际分配0~7组，每组6~7bank
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_3(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** QMU初始化配置场景三：8组*2bank，MMU开启rotatjon，MMU实际分配0~3组，每组2~3bank
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_3(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** QMU初始化配置场景三ETM: 8组*2bank，MMU开启rotatjon，MMU实际分配0~7组，每组6~7bank
-*     FTM: 8组*2bank，MMU开启rotatjon，MMU实际分配0~3组，每组2~3bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_3(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/**场景4：TM共享2组ddr:FTM为2、4组ddr的01bank，ETM为2、4组ddr 23bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/06/06
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_4(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/**场景4：TM共享2组ddr:FTM为2、4组ddr的01bank，ETM为2、4组ddr 23bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/06/06
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_4(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/**场景4：TM共享2组ddr:FTM为2、4组ddr的01bank，ETM为2、4组ddr 23bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/06/06
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_4(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** 场景5：TM共享4组ddr:FTM为1234组ddr的01bank，ETM为1234组ddr 23bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/06/06
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_5(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** 场景5：TM共享4组ddr:FTM为1234组ddr的01bank，ETM为1234组ddr 23bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/06/06
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_5(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** 场景5：TM共享4组ddr:FTM为1234组ddr的01bank，ETM为1234组ddr 23bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/06/06
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_5(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** QMU初始化配置场景6：4组*2bank，MMU实际分配ftm:4,6,7,9组(01bank); etm:4,6,7,9组(23bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/05/13
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_6(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** QMU初始化配置场景6：4组*2bank，MMU实际分配ftm:4,6,7,9组(01bank); etm:4,6,7,9组(23bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/05/13
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_6(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** QMU初始化配置场景6：4组*2bank，MMU实际分配ftm:4,6,7,9组(01bank); etm:4,6,7,9组(23bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/05/13
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_6(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** QMU初始化配置场景6：4组*4bank，MMU实际分配1,2(ftm); 5,6(etm)组，每组2~3 6~7bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_7(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** QMU初始化配置场景6：4组*4bank，MMU实际分配5~6组，每组2~3 6~7bank
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_7(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** QMU初始化配置场景6：4组*4bank，MMU实际分配1~2组，每组2~3 6~7bank
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_7(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** QMU初始化配置场景6：4组*4bank，MMU实际分配1,2(ftm); 5,6(etm)组，每组2~3 6~7bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_8(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** QMU初始化配置场景6：4组*4bank，MMU实际分配5~6组，每组2~3 6~7bank
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_8(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** QMU初始化配置场景6：4组*4bank，MMU实际分配1~2组，每组2~3 6~7bank
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_8(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** QMU初始化配置场景9：4组*2bank，MMU实际分配ftm:6,7,8,9组(01bank); etm:6,7,8,9组(23bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/09/28
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_9(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** QMU初始化配置场景9：4组*2bank，MMU实际分配ftm:6,7,8,9组(01bank); etm:6,7,8,9组(23bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/09/28
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_9(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** QMU初始化配置场景9：4组*2bank，MMU实际分配ftm:6,7,8,9组(01bank); etm:6,7,8,9组(23bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/09/28
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_9(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** QMU初始化配置场景10：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/12/16
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_10(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** QMU初始化配置场景10：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/12/16
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_10(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** QMU初始化配置场景10：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/12/16
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_10(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/**场景11：TM共享2组ddr:FTM为ddr_no1、ddr_no2组ddr的01bank，ETM为ddr_no1、ddr_no2组ddr 23bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/06/06
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_11(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no1, ZXIC_UINT32 ddr_no2);
-
-/***********************************************************/
-/**场景11：TM共享2组ddr:FTM为ddr_no1、ddr_no2组ddr的01bank，ETM为ddr_no1、ddr_no2组ddr 23bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/06/06
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_11(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no1, ZXIC_UINT32 ddr_no2);
-
-/***********************************************************/
-/**场景4：TM共享2组ddr:FTM为ddr_no1,ddr_no2组ddr的01bank，ETM为ddr_no1,ddr_no2组ddr 23bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/06/06
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_11(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no1, ZXIC_UINT32 ddr_no2);
-
-
-/***********************************************************/
-/** 
-QMU/MMU初始化配置场景12：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(4567bank); etm:0-9中指定组(0123bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/4/14
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_12(ZXIC_UINT32 dev_id, ZXIC_UINT32 ftm_ddr_no);
-
-
-/***********************************************************/
-/** 
-QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(4567bank); etm:0-9中指定组(0123bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/4/14
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_12(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no);
-
-
-
-/***********************************************************/
-/** QMU初始化配置场景13：TM独享4组ddr:FTM为指定4组ddr的0~7bank，
-                                      ETM为指定4组ddr 0~7bank
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_13(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no);
-
-/***********************************************************/
-/** QMU初始化配置场景13：TM独享4组ddr:FTM为指定4组ddr的0~7bank，
-                                      ETM为指定4组ddr 0~7bank
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_13(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no);
-
-
-/***********************************************************/
-/** QMU/MMU初始化配置场景13：TM独享4组ddr:FTM为指定4组ddr的0~7bank 
-                                          ETM为指定4组ddr的0-7bank
-*   MMU开启rotatjon
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_13(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no);
-
-
-/** QMU/MMU初始化配置场景14：每个tm只用1组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/4/14
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_14(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no, ZXIC_UINT32 ftm_ddr_no);
-
-
-/** QMU/MMU初始化配置场景14：每个tm只用1组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/4/14
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_14(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no);
-
-
-/** QMU/MMU初始化配置场景14：每个tm只用1组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/4/14
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_14(ZXIC_UINT32 dev_id, ZXIC_UINT32 ftm_ddr_no);
-
-
-/** QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(0123bank); etm:0-9中指定组(0123bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/4/14
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_15(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no, ZXIC_UINT32 ftm_ddr_no);
-
-
-/** QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(0123bank); etm:0-9中指定组(0123bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/4/14
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_15(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no);
-
-
-/** QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(0123bank); etm:0-9中指定组(0123bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/4/14
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_15(ZXIC_UINT32 dev_id, ZXIC_UINT32 ftm_ddr_no);
-
-
-/***********************************************************/
-/** QMU初始化配置场景16：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/12/16
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_16(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no, ZXIC_UINT32 ftm_ddr_no);
-
-/***********************************************************/
-/** QMU初始化配置场景16：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/12/16
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_16(ZXIC_UINT32 dev_id, ZXIC_UINT32 ftm_ddr_no);
-
-/***********************************************************/
-/** QMU初始化配置场景16：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/12/16
-************************************************************/
-DPP_STATUS dpp_ftm_qmu_init_set_16(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no);
-
-/***********************************************************/
-/** 64k队列的简单挂接函数配置
-*flow0~65535 -> ses0~4095 -> pp0
-:具体为flow0~15挂接到ses0的sp0，flow16~31挂接到ses1的sp0，以此类推
-*                                  ses到PP的挂接都是挂接于pp0的sp0
-*@param   dev_id   设备编号
-*         port_id端口号
-* @
-* @return
-* @remark  无
-* @see
-* @author  cy      @date  2015/06/30
-************************************************************/
-DPP_STATUS dpp_tm_crdt_sch_64k_test(ZXIC_UINT32 dev_id, ZXIC_UINT32 port_id);
-
-
-/***********************************************************/
-/** 把整数分解成(指定位长)最高有效数和(2的)指数位数的形式，data=p_remdata*2^(p_exp)
-* @param   data   需要转换前的数
-* @param   rembitsum   余数的位数
-* @param   p_remdata   余数大小
-* @param   p_exp   指数大小
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/27
-************************************************************/
-DPP_STATUS dpp_tm_rem_and_exp_translate(ZXIC_UINT32 data,
-                                        ZXIC_UINT32 rembitsum,
-                                        ZXIC_UINT32 *p_remdata,
-                                        ZXIC_UINT32 *p_exp);
-
-/***********************************************************/
-/** 配置统计计数寄存器的统计方式
-* @param   dev_id   设备编号
-* @param   qnum   支持2组统计寄存器，0-qnum1，1-qnum2
-* @param   mode   统计方式，0-统计全部队列，1-统计指定q_id
-* @param   q_id   mode=1时生效，统计该队列的信息
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_stat_q_set(ZXIC_UINT32 dev_id,
-                                   DPP_ETM_CGAVD_STAT_QNUM_E qnum,
-                                   DPP_ETM_CGAVD_STAT_MODE_E mode,
-                                   ZXIC_UINT32 q_id);
-
-/***********************************************************/
-/** 读取统计计数寄存器的计数信息
-* @param   dev_id   设备编号
-* @param   qnum   支持2组统计寄存器，0-qnum1，1-qnum2
-* @param   p_para   获得的统计信息
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_stat_q_get(ZXIC_UINT32 dev_id,
-                                   DPP_ETM_CGAVD_STAT_QNUM_E qnum,
-                                   DPP_ETM_CGAVD_STAT_INFO_T *p_para);
-
-/***********************************************************/
-/** 配置等价包长
-* @param   dev_id
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_equal_pkt_len 等价包长
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_equal_pkt_len_para_set(DPP_DEV_T *dev,
-                                               DPP_ETM_EQUAL_PKT_LEN_PARA_T *p_equal_pkt_len);
-
-/***********************************************************/
-/** 读取等价包长
-* @param   dev_id
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_equal_pkt_len 等价包长
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_equal_pkt_len_para_get(DPP_DEV_T *dev,
-                                               DPP_ETM_EQUAL_PKT_LEN_PARA_T *p_equal_pkt_len);
-
-/***********************************************************/
-/** 动态门限放大因子参数配置
-* @param   dev_id
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_amplify_gene_para 动态门限放大因子参数
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_amplify_gene_para_set(DPP_DEV_T *dev,
-                                              DPP_ETM_AMPLIFY_GENE_PARA_T *p_amplify_gene_para);
-
-
-/***********************************************************/
-/** 动态门限放大因子参数获取
-* @param   dev_id
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_amplify_gene_para 动态门限放大因子参数
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_amplify_gene_para_get(DPP_DEV_T *dev,
-                                              DPP_ETM_AMPLIFY_GENE_PARA_T *p_amplify_gene_para);
-
-/***********************************************************/
-/** 配置等价包长阈值
-* @param   dev_id
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_equal_pkt_len_th 等价包长阈值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_equal_pkt_len_th_para_set(DPP_DEV_T *dev,
-                                                  DPP_ETM_EQUAL_PKT_LEN_TH_PARA_T *p_equal_pkt_len_th);
-
-/***********************************************************/
-/** 配置QMU DDR BANK随机模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_ddr_random   模式:0-轮询模式；1-随机模式
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_ddr_random_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_ddr_random);
-
-/***********************************************************/
-/** 读取等价包长阈值
-* @param   dev_id
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_equal_pkt_len_th 等价包长阈值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_equal_pkt_len_th_para_get(DPP_DEV_T *dev,
-                                                  DPP_ETM_EQUAL_PKT_LEN_TH_PARA_T *p_equal_pkt_len_th);
-
-
-
-/***********************************************************/
-/** 读取全部队列的计数信息
-* @param   dev_id   设备编号*
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark   使用第2组统计寄存器进行统计
-* @see
-* @author    yjd    @date  2015/07/04
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_stat_q_all_get_diag(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** 读取某一队列统计计数寄存器的计数信息
-* @param   dev_id   设备编号
-* @param   q_id   统计该队列的信息
-*          使用第1组统计寄存器进行统计
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/04
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_stat_q_single_get_diag(ZXIC_UINT32 dev_id);
-
-
-
-/***********************************************************/
-/**  配置默认队列使能
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   配置的值，0-不使能默认队列，1-使能默认队列，
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush     @date  2016/08/16
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_default_queue_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en);
-
-/***********************************************************/
-/**  读取默认队列使能
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_en   读取的值，0-不使能默认队列，1-使能默认队列，
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush     @date  2016/08/16
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_default_queue_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en);
-
-
-/***********************************************************/
-/**  配置默认队列起始末尾
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   def_start_que  起始默认队列block/byte单位
-* @param   def_finish_que  结束默认队列block/byte单位
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush     @date  2016/08/16
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_default_queue_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 def_start_queue, ZXIC_UINT32 def_finish_queue);
-
-/***********************************************************/
-/**  读取默认队列起始末尾值
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_def_start_que   默认队列起始值block/byte单位
-* @param   p_def_finish_que   默认队列结束值block/byte单位
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2016/08/16
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_default_queue_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_def_start_queue, ZXIC_UINT32 *p_def_finish_queue);
-
-/***********************************************************/
-/**  配置协议队列使能
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   配置的值，0-不使能默认队列，1-使能默认队列，
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2016/08/16
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_protocol_queue_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en);
-
-/***********************************************************/
-/**  读取协议队列使能
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_en   读取的值，0-不使能通用门限，1-使能通用门限，
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2016/08/16
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_protocol_queue_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en);
-
-/***********************************************************/
-/**  配置协议队列起始末尾
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   protocol_start_que  起始协议队列block/byte单位
-*@param   protocol_-finish_que 末尾协议队列block/byte单位
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2016/08/16
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_protocol_queue_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 protocol_start_que, ZXIC_UINT32 protocol_finish_que);
-
-/***********************************************************/
-/**  读取协议队列起始末尾值
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_protocol_start_que   协议认队列起始值block/byte单位
-* @param   p_protocol_finish_que   协议认队列末尾值block/byte单位
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush     @date  2016/08/16
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_protocol_queue_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_protocol_start_que, ZXIC_UINT32 *p_protocol_finish_que);
-
-
-/***********************************************************/
-/** 配置QMU需要统计的队列组
-* @param   dev_id   设备号
-* @param   tm_type   0-ETM,1-FTM
-* @param   batch_id   队列组
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/05/07
-************************************************************/
-DPP_STATUS dpp_tm_qmu_observe_batch_set(DPP_DEV_T *dev, ZXIC_UINT32 batch_id);
-
-/***********************************************************/
-/** 配置QMU需要统计的队列号
-* @param   dev_id   设备号
-* @param   tm_type   0-ETM,1-FTM
-* @param   q_id   队列号
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/05/07
-************************************************************/
-DPP_STATUS dpp_tm_qmu_observe_qnum_set(DPP_DEV_T *dev, ZXIC_UINT32 q_id);
-
-/***********************************************************/
-/** 配置授权盈余初始化值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   crbal_initial_value   授权盈余初始化值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crbal_initial_value_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crbal_initial_value);
-
-/***********************************************************/
-/**  配置等价包长使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   使能标记，0-不使能，1-使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_equal_pkt_len_en_set(DPP_DEV_T *dev, ZXIC_UINT32 en);
-
-/***********************************************************/
-/**  读取等价包长使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_en   使能标记，0-不使能，1-使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_equal_pkt_len_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_en);
-
-
-/***********************************************************/
-/**  读取指定队列获得授权个数(只打印授权非零的队列号)
-* @param   dev_id   设备编号
-* @param   ackflow_start   授权起始流号
-* @param   ackflow_end   授权终止流号
-* @param   sleep_time_ms   等待时间
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2017/01/19
-************************************************************/
-DPP_STATUS dpp_etm_crdt_traffic_diag(ZXIC_UINT32 dev_id,
-                                     ZXIC_UINT32 ackflow_start,
-                                     ZXIC_UINT32 ackflow_end,
-                                     ZXIC_UINT32 sleep_time_ms);
-
-/***********************************************************/
-/**  读取指定队列获得授权个数(只打印授权非零的队列号)
-* @param   dev_id   设备编号
-* @param   ackflow_start   授权起始流号
-* @param   ackflow_end   授权终止流号
-* @param   sleep_time_ms   等待时间
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2017/01/19
-************************************************************/
-DPP_STATUS dpp_ftm_crdt_traffic_diag(ZXIC_UINT32 dev_id,
-                                     ZXIC_UINT32 ackflow_start,
-                                     ZXIC_UINT32 ackflow_end,
-                                     ZXIC_UINT32 sleep_time_ms);
-
-
-/***********************************************************/
-/** 读取指定队列获得授权个数(只打印授权非零的队列号)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM, 1FTM
-* @param   ackflow_start   授权流起始
-* @param   ackflow_end   授权流终止
-* @param   sleep_time_ms   等待时间
-*
-* @return
-* @remark  无
-* @see
-* @author  wush      @date  2017/01/24
-************************************************************/
-DPP_STATUS diag_dpp_tm_crdt_traffic_diag(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 ackflow_start,
-                                         ZXIC_UINT32 ackflow_end,
-                                         ZXIC_UINT32 sleep_time_ms);
-
-/***********************************************************/
-/**
-* @param   dev_id
-* @param   tm_type
-* @param   i_or_e_sel
-* @param   port_or_dest_id_sel
-* @param   start_id
-* @param   start_port_dest_id
-* @param   num
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xjw      @date  2018/02/01
-************************************************************/
-DPP_STATUS dpp_tm_olif_stat_set_mul(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 i_or_e_sel,
-                                    ZXIC_UINT32 port_or_dest_id_sel,
-                                    ZXIC_UINT32 start_id,
-                                    ZXIC_UINT32 start_port_dest_id,
-                                    ZXIC_UINT32 num);
-
-
-/******************************************************************************
- *                               END: 函数声明                                *
- *****************************************************************************/
-#endif
-
-
-#if ZXIC_REAL("ETM_STAT")
-
-
-/***********************************************************/
-/** 打印dpp tm所有模块中断状态
-* @param   tm_type   0-ETM,1-FTM
-* @param   dev_id   设备编号
-* @param
-* @param
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/09
-************************************************************/
-DPP_STATUS diag_dpp_tm_int(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** 获取tm.c中qmu_init_set中配置的case_num
-* @param   tm_type   0-ETM,1-FTM
-* @param   dev_id   设备编号
-* @param
-* @param
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/04/15
-************************************************************/
-DPP_STATUS dpp_tm_case_no_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *case_no);
-
-/***********************************************************/
-/** 配置dpp tm所有模块中断屏蔽
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   int_mask_flag    0:不屏蔽   1:屏蔽
-* @param
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/09
-************************************************************/
-DPP_STATUS dpp_tm_int_mask_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 int_mask_flag);
-
-/***********************************************************/
-/**  读取基于优先级的QMU接收NPPU数据的fifo阈值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sp  优先级0~7
-* @param   p_th  指定优先级的fifo阈值0~511，单位为fifo条目，fifo深度512
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_move_drop_sp_th_get(ZXIC_UINT32 dev_id,
-                                            ZXIC_UINT32 sp,
-                                            ZXIC_UINT32 *p_th);
-
-/***********************************************************/
-/** 打印cgavd模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_mode   0:block mode 1:byte mode
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/07/29
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_cfg_mode_get_diag(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** 打印cgavd TD阈值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号，系统级时，id参数无效
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/08/01
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_td_byte_block_th_get_diag(ZXIC_UINT32 dev_id,
-                                                  DPP_TM_CGAVD_LEVEL_E level,
-                                                  ZXIC_UINT32 id);
-
-/***********************************************************/
-/** QMU MMU 配置清除
-* @param   dev_id   
-* @param   tm_type   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  XXX      @date  2020/04/13
-************************************************************/
-DPP_STATUS dpp_tm_qmu_mmu_cfg_clr(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** 读取QMU所有队列的统计信息
-* @param   dev_id   设备编号
-* @param   p_para   获得的统计信息
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_stat_get(ZXIC_UINT32 dev_id, DPP_ETM_QMU_STAT_INFO_T *p_para);
-
-/***********************************************************/
-/** 读取QMU指定队列的计数信息
-* @param   dev_id   设备编号
-* @param   p_para   获得的统计信息
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_spec_q_stat_get(ZXIC_UINT32 dev_id, DPP_ETM_QMU_SPEC_Q_STAT_INFO_T *p_para);
-
-/***********************************************************/
-/** 读取QMU指定队列组的计数信息
-* @param   dev_id   设备编号
-* @param   p_para   获得的统计信息
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_spec_bat_stat_get(ZXIC_UINT32 dev_id, DPP_ETM_QMU_SPEC_BAT_STAT_INFO_T *p_para);
-
-/***********************************************************/
-/** 配置QMU流控计数模式
-* @param   dev_id   设备号
-* @param   tm_type   0-ETM,1-FTM
-* @param   mode   流控模式，0-电平流控；1-边沿流控
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/05/07
-************************************************************/
-DPP_STATUS dpp_tm_qmu_fc_cnt_mode_set(DPP_DEV_T *dev, ZXIC_UINT32 mode);
-
-/***********************************************************/
-/** 读取QMU流控计数模式
-* @param   dev_id   设备号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_mode   流控模式，0-电平流控；1-边沿流控
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/05/07
-************************************************************/
-DPP_STATUS dpp_tm_qmu_fc_cnt_mode_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_mode);
-
-/***********************************************************/
-/** 打印block长度
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/20
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_blk_size_get_diag(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** 打印队列空标志查询
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   配置的队列号
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/06/20
-************************************************************/
-DPP_STATUS dpp_tm_qlist_ept_flag_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum);
-
-
-/***********************************************************/
-/** 获得队列空标志查询
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   配置的队列号
-* @param   p_value   队列空标志查询
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/06/20
-************************************************************/
-DPP_STATUS dpp_tm_qlist_ept_flag_get(ZXIC_UINT32 dev_id,
-                                     ZXIC_UINT32 qnum,
-                                     ZXIC_UINT32 *p_value);
-
-
-/***********************************************************/
-/** 获得队列深度计数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   配置的队列号
-* @param   p_value  队列深度计数
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/06/20
-************************************************************/
-DPP_STATUS dpp_tm_qlist_r_bcnt_get(ZXIC_UINT32 dev_id,
-                                   ZXIC_UINT32 qnum,
-                                   ZXIC_UINT32 *p_value);
-
-
-/***********************************************************/
-/** 打印队列深度计数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   配置的队列号
-* @param   p_value  队列深度计数
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/06/20
-************************************************************/
-DPP_STATUS dpp_tm_qlist_r_bcnt_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum);
-
-/***********************************************************/
-/** CMDSCH中分端口分优先级的BLOCK计数
-* @param   dev_id   设备编号
-* @param   pri   
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/09/19
-************************************************************/
-DPP_STATUS dpp_tm_csch_r_block_cnt_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 pri, ZXIC_UINT32 *p_value);
-
-/***********************************************************/
-/** 打印CMDSCH中分端口分优先级的BLOCK计数
-* @param   dev_id   设备编号
-* @param   port   
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/09/19
-************************************************************/
-DPP_STATUS dpp_tm_csch_r_block_cnt_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 port);
-
-/***********************************************************/
-/** 打印队列入链状态
-* @param   dev_id   设备编号
-* @param   flow_id   
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/09/19
-************************************************************/
-DPP_STATUS dpp_tm_crdt_flow_link_state_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 flow_id);
-
-/***********************************************************/
-/** 打印调度器入链状态
-* @param   dev_id   设备编号
-* @param   flow_id   
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/09/19
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_link_state_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 se_id);
-
-/***********************************************************/
-/** 打印olif的fifo是否空状态
-* @param   dev_id   设备编号
-* @param      
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/09/19
-************************************************************/
-DPP_STATUS dpp_tm_olif_fifo_empty_state_get_diag(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** 授权个数统计寄存器清零
-* @param   dev_id  设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_crdt_clr_diag(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/**cpu配置flow_id的crs强制为normal或者off开关使能，用于检测SA模式下队列到授权流的多对一问题
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id:流号(和授权流号一一对应)
-*                en   强制配置crs的使能，0-不使能，1-使能
-*                crs_value:强制配置crs的值2'b00:off; 2'b01:low; 2'b10:normal；
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/04/25
-************************************************************/
-DPP_STATUS dpp_tm_crdt_crs_sheild_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 flow_id, ZXIC_UINT32 en, ZXIC_UINT32 crs_value);
-
-
-/***********************************************************/
-/**获取flow_id的crs强制为normal或者off开关使能，用于检测SA模式下队列到授权流的多对一问题
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id:流号(和授权流号一一对应)
-*                en   强制配置crs的使能，0-不使能，1-使能
-*                crs_value:强制配置crs的值2'b00:off; 2'b01:low; 2'b10:normal；
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/04/25
-************************************************************/
-DPP_STATUS dpp_tm_crdt_crs_sheild_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_flow_id, ZXIC_UINT32 *p_en, ZXIC_UINT32 *p_crs_value);
-
-
-/***********************************************************/
-/** 获得拥塞状态(有效链路数+UCN等级)到授权产生间隔的映射表
-* @param   dev_id   设备编号
-* @param   valid_serdes_num   有效的链路数(0~32
-* @param   ucn_level   UCN等级(0~7)
-* @param   p_cr_clk   UCN等级(0~7)
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2017/03/28
-************************************************************/
-DPP_STATUS dpp_tm_crdt_cfgmt_interval_get(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 valid_serdes_num,
-                                          ZXIC_UINT32 ucn_level,
-                                          ZXIC_UINT32 *p_cr_clk);
-
-/***********************************************************/
-/**每隔10s获取crs状态的个数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param
-* @return
-* @remark  无
-* @see
-* @author  zmy     @date  2015/08/07
-************************************************************/
-DPP_STATUS dpp_tm_crs_statics(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id);
-
-
-/***********************************************************/
-/** 统计QMU发送和CRDT模块指定授权流接收的CRS计数(10s内)
-* @param   dev_id  设备编号
-* @param   que_id   QMU队列号
-* @param   ackflow_id   授权流号
-* @param   valid_flag   0:队列发送和授权流接收都统计; 1:只关注队列发送，2:只关注授权流接收。
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2017/05/12
-************************************************************/
-DPP_STATUS dpp_tm_crs_cnt_prt(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id, ZXIC_UINT32 ackflow_id, ZXIC_UINT32 valid_flag);
-
-
-/***********************************************************/
-/** 带停流的统计QMU发送和CRDT模块指定授权流接收的CRS计数
-* @param   dev_id  设备编号
-* @param   que_id   QMU队列号
-* @param   ackflow_id   授权流号
-* @param   valid_flag   0:默认队列发送和授权流接收都统计,此时队列授权都在本板;
-*                       1:只关注队列发送，2:只关注授权流接收，需要与源端队列停流配合使用，
-                        先停流，运行该函数；或者直接不停流得到的是某段时间的计数。
-* @param   sleep_time   统计多长时间内的crs计数
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2017/05/12
-************************************************************/
-DPP_STATUS dpp_tm_crs_cnt_prt_1(ZXIC_UINT32 dev_id,
-                                ZXIC_UINT32 que_id,
-                                ZXIC_UINT32 ackflow_id,
-                                ZXIC_UINT32 valid_flag,
-                                ZXIC_UINT32 sleep_time);
-
-/***********************************************************/
-/** 读取qlist入队及出队状态监控
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2015/08/26
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qlist_state_query(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** 打印被指定统计的第0~15个端口消耗的令牌个数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  统计时间为2s，其中c桶统计1s，e桶统计1s
-* @see
-* @author  whuashan      @date  2019/03/15
-************************************************************/
-DPP_STATUS dpp_tm_shape_token_dec_cnt_diag(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** 打印被指定统计的第0~15个端口接收的令牌个数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  统计时间为2s，其中c桶统计1s，e桶统计1s
-* @see
-* @author  whuashan      @date  2019/03/15
-************************************************************/
-DPP_STATUS dpp_tm_shape_token_dist_cnt_diag(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** 配置olif统计组信息
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   id   olif统计组号
-* @param   all_or_by_port   0-统计所有，1-统计某一端口或某一dest_id
-* @param   i_or_e_sel   10-统计片外，01-统计片内，其他值-统计所有
-* @param   port_or_dest_id_sel   0-统计port，1-统计dest_id
-* @param   port_dest_id   port号或dest_id号
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/04/21
-************************************************************/
-DPP_STATUS dpp_tm_olif_stat_set(ZXIC_UINT32 dev_id,
-                                ZXIC_UINT32 id,
-                                ZXIC_UINT32 all_or_by_port,
-                                ZXIC_UINT32 i_or_e_sel,
-                                ZXIC_UINT32 port_or_dest_id_sel,
-                                ZXIC_UINT32 port_dest_id);
-
-
-/***********************************************************/
-/** 查看CRDT接收到和发送的某端口拥塞授权总数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   pp_id   0~63
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/12/08
-************************************************************/
-DPP_STATUS diag_dpp_tm_crdt_port_congest_credit_cnt(ZXIC_UINT32 dev_id, ZXIC_UINT32 pp_id);
-
-#endif /*ETM_STAT */
-
-
-#if ZXIC_REAL("TM_REG")
-/***********************************************************/
-/** 写TM寄存器
-* @param   module_id 区分TM子模块
-* @param   addr   基于子模块的地址
-* @param   data   写入的数据
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/26
-************************************************************/
-DPP_STATUS dpp_tm_wr_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 addr, ZXIC_UINT32 data);
-
-
-/***********************************************************/
-/** 读TM寄存器
-* @param   module_id 区分TM子模块
-* @param   addr   基于子模块的地址
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/26
-************************************************************/
-DPP_STATUS dpp_tm_rd_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 addr);
-
-
-/***********************************************************/
-/** 读一片连续的TM寄存器
-* @param   module_id 区分TM子模块
-* @param   first_addr   起始寄存器的地址
-* @param   reg_num   总共读取的寄存器数
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2017/07/26
-************************************************************/
-DPP_STATUS dpp_tm_rd_more_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 first_addr, ZXIC_UINT32 reg_num);
-
-/***********************************************************/
-/** 写tm模块二层间接寄存器(仅crdt/shap模块使用)
-* @param   module_id 区分TM子模块
-* @param   addr   基于子模块的地址
-* @param   data   写入的数据
-*
-* @return
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/25
-************************************************************/
-DPP_STATUS dpp_tm_ind_wr_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 addr, ZXIC_UINT64 data);
-
-/***********************************************************/
-/** 读tm模块二层间接寄存器(仅crdt/shap模块使用)
-* @param   module_id 区分TM子模块
-* @param   addr   基于子模块的地址
-*
-* @return
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/25
-************************************************************/
-DPP_STATUS dpp_tm_ind_rd_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 addr);
-#endif /*TM_REG */
-
-#if ZXIC_REAL("TM_CFGMT")
-/***********************************************************/
-/** 校验子系统初始化就绪，所有子系统均初始化就绪，p_rdy值为1
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_rdy   初始化就绪标记，1-就绪，0-未就绪
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_subsystem_rdy_check(ZXIC_UINT32 dev_id);
-
-
-/***********************************************************/
-/** cpu读写通道验证，其读出值等于写入值。读出值不等于写入值时，返回err
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_cpu_check(DPP_DEV_T *dev);
-
-
-/***********************************************************/
-/** 读取内置TM的工作模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_mode   读取的值，0-TM模式，1-SA模式
-*ETM仅工作在TM模式，FTM可以工作TM或SA模式
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_sa_work_mode_get(DPP_DEV_T *dev, DPP_TM_WORK_MODE_E *p_mode);
-
-
-/***********************************************************/
-/** 配置ddr3挂接组数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   ddr_num   ddr组数，1-6组
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_ddr_attach_set(DPP_DEV_T *dev, ZXIC_UINT32 ddr_num);
-
-
-/***********************************************************/
-/** 读取ddr3挂接组数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_ddr_num   ddr组数,1-6组
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_ddr_attach_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_ddr_num);
-
-DPP_STATUS dpp_qmu_init_info(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** 配置包存储的CRC功能是否使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   配置的值，0-禁止CRC功能，1-允许CRC功能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_crc_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en);
-
-
-/***********************************************************/
-/** 配置qmu端口转换使能，SA模式下需要配置
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   配置的使能值，0-不使能，1-使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_port_transfer_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en);
-
-
-/***********************************************************/
-/** 读取qmu端口转换使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_en   读取的使能值，0-不使能，1-使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_port_transfer_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en);
-
-
-/***********************************************************/
-/** 读取包存储的CRC功能是否使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_en   读取的值，0-禁止CRC功能，1-允许CRC功能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_crc_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en);
-
-
-/***********************************************************/
-/** 配置block长度模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   size   block长度模式:256/512/1024
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_blk_size_set(DPP_DEV_T *dev, ZXIC_UINT32 size);
-
-
-/***********************************************************/
-/** 配置计数模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_mode   计数模式
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_cnt_mode_set(ZXIC_UINT32 dev_id, DPP_TM_CNT_MODE_T *p_mode);
-
-
-/***********************************************************/
-/** 读取计数模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_mode   计数模式
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_cnt_mode_get(ZXIC_UINT32 dev_id, DPP_TM_CNT_MODE_T *p_mode);
-
-
-/***********************************************************/
-/** 配置中断屏蔽
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_para   中断屏蔽
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_int_mask_set(ZXIC_UINT32 dev_id, DPP_TM_INT_T *p_para);
-
-
-/***********************************************************/
-/** 读取中断屏蔽
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_para   中断屏蔽
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_int_mask_get(ZXIC_UINT32 dev_id, DPP_TM_INT_T *p_para);
-
-
-/***********************************************************/
-/** 读取中断状态
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_para   中断状态
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_int_state_get(ZXIC_UINT32 dev_id, DPP_TM_INT_T *p_para);
-
-/***********************************************************/
-/** 配置tm时钟门控是否使能
-* @param   dev_id   设备编号
-* @param   en   配置的值，0-禁止tm时钟门控，1-使能tm时钟门控
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lsy      @date  2022/08/22
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_clkgate_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en);
-
-/***********************************************************/
-/** 读取tm时钟门控是否使能
-* @param   dev_id   设备编号
-* @param   en   配置的值，0-禁止tm时钟门控，1-使能tm时钟门控
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lsy      @date  2022/08/22
-
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_clkgate_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en);
-
-/***********************************************************/
-/** 配置tm软复位是否使能
-* @param   dev_id   设备编号
-* @param   en   配置的值，0-禁止tm软复位，1-使能tm软复位
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lsy      @date  2022/08/22
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_softrst_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en);
-
-/***********************************************************/
-/** 读取tm软复位是否使能
-* @param   dev_id   设备编号
-* @param   en   配置的值，0-禁止tm软复位，1-使能tm软复位
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lsy      @date  2022/08/22
-
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_softrst_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en);
-
-#endif /*TM_CFGMT */
-
-#if ZXIC_REAL("TM_CGAVD")
-/***********************************************************/
-/**  读取各级搬移功能使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级
-* @param   p_en   读出的使能标记，0-不使能，1-使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-#ifdef ETM_REAL
-DPP_STATUS dpp_tm_cgavd_move_en_get(ZXIC_UINT32 dev_id,
-                                    DPP_TM_CGAVD_LEVEL_E level,
-                                    ZXIC_UINT32 *p_en);
-
-/***********************************************************/
-/** 配置各级搬移门限
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号，系统级时，id参数无效
-* @param   value   端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B；
-                   流级时为搬移profile_id,0~15
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_move_th_set(ZXIC_UINT32 dev_id,
-                                    DPP_TM_CGAVD_LEVEL_E level,
-                                    ZXIC_UINT32 id,
-                                    ZXIC_UINT32 value);
-
-/***********************************************************/
-/** 读取各级搬移门限
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号，系统级时，id参数无效
-* @param   p_value   端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B；
-                     流级时为搬移profile_id,0~15
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_move_th_get(ZXIC_UINT32 dev_id,
-                                    DPP_TM_CGAVD_LEVEL_E level,
-                                    ZXIC_UINT32 id,
-                                    ZXIC_UINT32 *p_value);
-
-/***********************************************************/
-/**  读取flow级的搬移策略
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   move_profile  flow级的搬移门限分组索引,0~15
-* @param   p_th  flow级的搬移门限，单位为KB；
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_flow_move_profile_get(ZXIC_UINT32 dev_id,
-                                              ZXIC_UINT32 move_profile,
-                                              ZXIC_UINT32 *p_th);
-#endif
-/***********************************************************/
-/**  读取端口共享的搬移门限
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_th  端口共享的搬移门限，单位为NPPU存包的单位，256B；
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_port_share_th_get(ZXIC_UINT32 dev_id,
-                                           ZXIC_UINT32 *p_th);
-
-/***********************************************************/
-/**  读取各级拥塞避免功能使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   要读取的拥塞避免层次号，0:队列级，1:端口级，2:系统级
-* @param   p_en   读出的使能标记，0-不使能，1-使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_en_get(DPP_DEV_T *dev,
-                               DPP_TM_CGAVD_LEVEL_E level,
-                               ZXIC_UINT32 *p_en);
-
-/***********************************************************/
-/**  dp选取来源
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级
-* @param   dp_sel   dp选取来源，0-dp，1-tc，2-pkt_len[2:0]
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2017/03/14
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_dp_sel_set(DPP_DEV_T *dev,
-                                   DPP_TM_CGAVD_LEVEL_E level,
-                                   DPP_TM_CGAVD_DP_SEL_E dp_sel);
-
-/***********************************************************/
-/** 读取拥塞避免算法
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号,系统级时,id参数无效
-* @param   p_method   配置的拥塞避免算法,0:TD,1:WRED/GRED
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_method_get(DPP_DEV_T *dev,
-                                   DPP_TM_CGAVD_LEVEL_E level,
-                                   ZXIC_UINT32 id,
-                                   DPP_TM_CGAVD_METHOD_E *p_method);
-
-
-/***********************************************************/
-/** 流队列级队列深度的获取
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   que_id      队列号
-*          p_len       队列深度以KB为单位
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_flow_que_len_get(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 que_id,
-                                   ZXIC_UINT32 *p_len);
-
-/***********************************************************/
-/** 端口级队列深度的获取
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   pp_id      队列号
-*          pp_len       队列深度以KB为单位
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_port_que_len_get(ZXIC_UINT32 dev_id,
-                                   ZXIC_UINT32 pp_id,
-                                   ZXIC_UINT32 *pp_len);
-
-/***********************************************************/
-/** 系统级队列深度的获取
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sys_len       系统级深度以block为单位
-*          sys_protocol_len       系统级包含协议队列深度以KB为单位
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_sys_que_len_get(ZXIC_UINT32 dev_id,
-                                  ZXIC_UINT32 *sys_len,
-                                  ZXIC_UINT32 *sys_protocol_len);
-
-/***********************************************************/
-/** 读取TD拥塞避免模式下的丢弃门限值
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号，系统级时，id参数无效
-* @param   p_td_th   配置的丢弃门限值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_td_th_get(DPP_DEV_T *dev,
-                                  DPP_TM_CGAVD_LEVEL_E level,
-                                  ZXIC_UINT32 id,
-                                  ZXIC_UINT32 *p_td_th);
-
-/***********************************************************/
-/** 读取指定端口或队列绑定的WRED GROUP ID
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   id   队列号或端口号
-* @param   p_wred_id   配置的WRED GROUP ID
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_wred_id_get(ZXIC_UINT32 dev_id,
-                                    DPP_TM_CGAVD_LEVEL_E level,
-                                    ZXIC_UINT32 id,
-                                    ZXIC_UINT32 *p_wred_id);
-
-/***********************************************************/
-/** 读取WRED丢弃曲线对应的参数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   wred_id   队列级共支持16个WRED组0-15，端口级支持8组0-7
-* @param   dp   共支持8个dp，取值0-7
-* @param   p_para   配置的WRED组参数值，包含以下五个参数
-           max_th  平均队列深度上限阈值
-           min_th  平均队列深度下限阈值
-           max_p  最大丢弃概率
-           weight   平均队列深度计算权重
-           q_len_th 队列深度阈值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  taq     @date  2015/04/20
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_wred_dp_line_para_get(ZXIC_UINT32 dev_id,
-                                              DPP_TM_CGAVD_LEVEL_E level,
-                                              ZXIC_UINT32 wred_id,
-                                              ZXIC_UINT32 dp,
-                                              DPP_TM_WRED_DP_LINE_PARA_T *p_para);
-
-/***********************************************************/
-/** 配置系统级GRED丢弃曲线对应的参数
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   dp   共支持8个dp，取值0-7
-* @param   p_para  配置的GRED丢弃曲线参数值，包含以下六个参数
-           max_th  平均队列深度上限阈值
-           mid_th  平均队列深度中间阈值
-           min_th  平均队列深度下限阈值
-           max_p   最大丢弃概率
-           weight   平均队列深度计算权重
-           q_len_th 队列深度阈值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/04/20
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_gred_dp_line_para_set(ZXIC_UINT32 dev_id,
-                                              ZXIC_UINT32 dp,
-                                              DPP_TM_GRED_DP_LINE_PARA_T *p_para);
-
-/***********************************************************/
-/** 配置系统级阶梯TD 丢弃曲线对应的参数
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   dp   共支持8个dp，取值0-7
-* @param   td_th  TD 门限
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/08/02
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_ladtd_dp_line_para_set(ZXIC_UINT32 dev_id,
-                                               ZXIC_UINT32 dp,
-                                               ZXIC_UINT32 td_th);
-
-
-/***********************************************************/
-/** 读取系统级GRED丢弃曲线对应的参数
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   dp   共支持8个dp，取值0-7
-* @param   p_para  配置的GRED丢弃曲线参数值，包含以下六个参数
-           max_th  平均队列深度上限阈值
-           mid_th  平均队列深度中间阈值
-           min_th  平均队列深度下限阈值
-           max_p   最大丢弃概率
-           weight   平均队列深度计算权重
-           q_len_th 队列深度阈值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/04/20
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_gred_dp_line_para_get(ZXIC_UINT32 dev_id,
-                                              ZXIC_UINT32 dp,
-                                              DPP_TM_GRED_DP_LINE_PARA_T *p_para);
-
-/***********************************************************/
-/** 读取指定端口或队列是否支持动态门限机制
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   id   队列号或端口号
-* @param   p_en   读取的值，0-不支持动态门限机制，1-支持动态门限机制
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_dyn_th_en_get(DPP_DEV_T *dev,
-                                      DPP_TM_CGAVD_LEVEL_E level,
-                                      ZXIC_UINT32 id,
-                                      ZXIC_UINT32 *p_en);
-
-/***********************************************************/
-/**  配置通用门限使能
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   配置的值，0-不使能通用门限，1-使能通用门限，
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_uniform_th_en_set(DPP_DEV_T *dev, ZXIC_UINT32 en);
-
-/***********************************************************/
-/**  读取通用门限使能
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_en   读取的值，0-不使能通用门限，1-使能通用门限，
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_uniform_th_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_en);
-
-/***********************************************************/
-/**  配置通用门限
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   th   通用门限值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_uniform_th_set(DPP_DEV_T *dev, ZXIC_UINT32 th);
-
-/***********************************************************/
-/**  读取通用门限
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_th   通用门限值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_uniform_th_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_th);
-
-/***********************************************************/
-/**  配置流队列所属优先级
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   q_id   队列号
-* @param   pri   配置的优先级，0~7
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_q_pri_set(DPP_DEV_T *dev,
-                                  ZXIC_UINT32 q_id,
-                                  ZXIC_UINT32 pri);
-
-/***********************************************************/
-/** 读取TM模式下流队列挂接的端口号；SA模式下流队列映射的目的芯片ID
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   q_id   队列号
-* @param   p_pp_id   读取的端口号
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_q_map_pp_get(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 q_id,
-                                     ZXIC_UINT32 *p_pp_id);
-
-/***********************************************************/
-/** 读取配置TM模式tc到flow的映射
-* @param   dev_id 设备编号
-* @param   tc_id   itmd tc优先级（0~7）
-* @param   flow_id 读取映射的flowid号 （0~4095）
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/07/04
-************************************************************/
-DPP_STATUS dpp_tm_tc_map_flow_get(DPP_DEV_T *dev,
-                                  ZXIC_UINT32 tc_id,
-                                  ZXIC_UINT32 *flow_id);
-
-/***********************************************************/
-/**  获取强制片内或片外
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en      1:使能
-* @param   mode   1 :omem 强制片外  0:imem 强制片内
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2017/10/14
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_imem_omem_get(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 *p_en,
-                                      ZXIC_UINT32 *p_mode);
-
-/***********************************************************/
-/** 连续配置各级搬移门限
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   start_id 为起始 队列号或端口号，系统级时，id参数无效
-* @param   value   端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B；
-                   流级时为搬移profile_id,0~15
-* @param  num   为队列或端口个数
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2016/11/19
-************************************************************/
-#ifdef ETM_REAL
-DPP_STATUS dpp_tm_cgavd_move_th_together_wr(ZXIC_UINT32 dev_id,
-                                            DPP_TM_CGAVD_LEVEL_E level,
-                                            ZXIC_UINT32 start_id,
-                                            ZXIC_UINT32 value,
-                                            ZXIC_UINT32 num);
-#endif
-/***********************************************************/
-/** 系统级缓存使用上下限阈值配置
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   th_h: 系统级缓存使用上限阈值
-* @param   th_l: 系统级缓存使用下限阈值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/03
-************************************************************/
-DPP_STATUS dpp_tm_sys_window_th_set(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 th_h,
-                                    ZXIC_UINT32 th_l);
-
-/***********************************************************/
-/** 配置cgavd强制反压
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   cgavd_fc: 0:不强制反压    1:强制反压
-* @param
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/07/03
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_cfg_fc_set(ZXIC_UINT32 dev_id,
-                                   ZXIC_UINT32 cgavd_fc);
-
-/***********************************************************/
-/** 获取cgavd强制反压状态
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   cgavd_fc: 0:不强制反压    1:强制反压
-* @param
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/07/03
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_cfg_fc_get(ZXIC_UINT32 dev_id,
-                                   ZXIC_UINT32 *cgavd_fc);
-
-/***********************************************************/
-/** 配置cgavd强制不反压
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   cgavd_no_fc: 0:不强制     1:强制不反压
-* @param
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/07/03
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_cfg_no_fc_set(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 cgavd_no_fc);
-
-/***********************************************************/
-/** 获取cgavd强制不反压状态
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   cgavd_no_fc: 0:不强制 1:强制不反压
-* @param
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/07/03
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_cfg_no_fc_get(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 *cgavd_no_fc);
-
-
-/***********************************************************/
-/** 配置cgavd平均队列深度归零
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en: 0:关闭     1:使能
-* @param
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/08/05
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_avg_qlen_return_zero_en_set(ZXIC_UINT32 dev_id,
-                                                ZXIC_UINT32 en);
-#endif /*TM_CGAVD */
-
-/** crdt ram初始化
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/22
-************************************************************/
-DPP_STATUS dpp_tm_crdt_ram_init(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** 获取调度器类型
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   se_id     调度器编号
-* @param   item_num  调度器中包含的子调度器个数
-* @param   sch_type_num  调度器类型编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/26
-************************************************************/
-DPP_STATUS dpp_tm_crdt_sch_type_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id, ZXIC_UINT32 *item_num, ZXIC_UINT32 *sch_type_num);
-
-/***********************************************************/
-/** 配置flow级流队列的挂接关系(flow到上级调度器的挂接)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id   流队列号
-* @param   c_linkid  c桶要挂接到的上级调度器id
-* @param   c_weight  c桶挂接到上级调度器的权重[1~511]
-* @param   c_sp      c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
-* @param   mode      挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可
-* @param   e_linkid  e桶要挂接到的上级调度器id
-* @param   e_weight  e桶挂接到上级调度器的权重[1~511]
-* @param   e_sp      e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_flow_link_wr(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 flow_id,
-                                    DPP_TM_SCH_FLOW_PARA_T *p_flow_para);
-
-/***********************************************************/
-/** 批量配置flow级流队列的挂接关系
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id_s 起始流队列号
-* @param   flow_id_e 终止流队列号
-* @param   c_linkid  c桶要挂接到的上级调度器id
-* @param   c_weight  c桶挂接到上级调度器的权重[1~511]
-* @param   c_sp      c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
-* @param   mode      挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可
-* @param   e_linkid  e桶要挂接到的上级调度器id
-* @param   e_weight  e桶挂接到上级调度器的权重[1~511]
-* @param   e_sp      e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_flow_link_more_set(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 flow_id_s,
-                                          ZXIC_UINT32 flow_id_e,
-                                          ZXIC_UINT32 c_linkid,
-                                          ZXIC_UINT32 c_weight,
-                                          ZXIC_UINT32 c_sp,
-                                          ZXIC_UINT32 mode,
-                                          ZXIC_UINT32 e_linkid,
-                                          ZXIC_UINT32 e_weight,
-                                          ZXIC_UINT32 e_sp);
-
-/***********************************************************/
-/** 配置调度器层次化QOS的挂接关系:非优先级传递
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   se_id      本级调度器id
-* @param   se_linkid  要挂接到的上级调度器id
-* @param   se_weight  挂接到上级调度器的权重[1~511]
-* @param   se_sp      挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
-* @param   se_insw    优先级传递使能：0-关 1-开。该参数不传递直接配0
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_link_wr(DPP_DEV_T *dev,
-                                  ZXIC_UINT32 se_id,
-                                  DPP_TM_SCH_SE_PARA_T *p_sch_se_para);
-
-
-/***********************************************************/
-/** 配置调度器层次化QOS的挂接关系:优先级传递
-* @param   dev_id       设备编号
-* @param   tm_type      0-ETM,1-FTM
-* @param   se_id        本级调度器id
-* @param   se_linkid    要挂接到的上级调度器id
-* @param   se_sp        挂接到上级调度器的sp优先级,有效值[0-3],最多4级，优先级按调度单元分配，
-*                       每个调度单元内部调度器优先级相同！
-* @param   se_weight0-7 WFQ8中各调度器权重值[1~511]，若是WFQ2/4 只取前面对应值，后面无效
-* @param   se_insw      优先级传递使能：0-关 1-开. 该参数不传递直接配1
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_link_insw_wr(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 se_id,
-                                       DPP_TM_SCH_SE_PARA_INSW_T *p_sch_se_para_insw);
-
-/***********************************************************/
-/** 获取流队列入链状态
-* @param   dev_id      设备编号
-* @param   tm_type     0-ETM,1-FTM
-* @param   flow_id     流队列号
-* @param   link_state  0-未入链     1-在调度器链表中
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_flow_link_state_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id, ZXIC_UINT32 *link_state);
-
-/***********************************************************/
-/** 获取调度器入链状态
-* @param   dev_id      设备编号
-* @param   tm_type     0-ETM,1-FTM
-* @param   se_id       调度器编号
-* @param   link_state  0-未入链     1-在调度器链表中
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_link_state_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id, ZXIC_UINT32 *link_state);
-
-/***********************************************************/
-/** 判断crdt流删除命令是否空闲
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_del_cmd_idle(DPP_DEV_T *dev);
-
-/***********************************************************/
-/** 删除流/调度器挂接关系
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   id        要删除的流号或调度器id
-*          ETM范围:0--0xABFF; FTM范围:0-0x177F
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_del_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id);
-
-
-
-
-/***********************************************************/
-/** 获取pp->dev挂接关系
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   pp_id   0~63
-* @param   p_weight  0~127
-* @param   p_sp_mapping   0~7
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/04/20
-************************************************************/
-DPP_STATUS dpp_tm_crdt_pp_para_get(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 pp_id,
-                                   ZXIC_UINT32 *p_weight,
-                                   ZXIC_UINT32 *p_sp_mapping);
-
-/***********************************************************/
-/**
-* @param   dev_id   设备编号
-* @param   tm_type  0-ETM,1-FTM
-* @param   que_id_s 起始队列号
-* @param   que_id_e 终止队列号
-* @param   en       1:过滤E桶队列CRS状态为SLOW的入链请求；0:E桶队列CRS SLOW正常入链；
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2019/05/08
-************************************************************/
-DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_more_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id_s, ZXIC_UINT32 que_id_e, ZXIC_UINT32 en);
-
-
-/***********************************************************/
-/**
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   que_id   queue id
-* @param   p_en
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2019/05/08
-************************************************************/
-DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id, ZXIC_UINT32 *p_en);
-
-/***********************************************************/
-/**
-* @param   dev_id
-* @param   tm_type
-* @param   que_id
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2019/05/08
-************************************************************/
-DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id);
-
-
-/***********************************************************/
-/** 打印指定的全局数组值以及清空全局数组
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   para_x   数组index_x
-* @param   para_y   数组index_y
-* @param   clear_flag 清空shape全局数组
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark
-* @see
-* @author  xuhb      @date  2019/06/10
-************************************************************/
-DPP_STATUS dpp_tm_shape_para_array_prt(ZXIC_UINT32 dev_id, ZXIC_UINT32 para_x, ZXIC_UINT32 para_y, ZXIC_UINT32 clear_flag);
-
-
-/***********************************************************/
-/** 配置shap模块中 crd_grain授权价值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   credit_value   授权价值，默认值是0x5feByte
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/08/13
-************************************************************/
-DPP_STATUS dpp_tm_shap_crd_grain_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 credit_value);
-
-
-/***********************************************************/
-/** shap ram初始化
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/22
-************************************************************/
-DPP_STATUS dpp_tm_shap_ram_init(ZXIC_UINT32 dev_id);
-
-/***********************************************************/
-/** 获取流队列双桶整形使能及模式
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   db_en     双桶整形使能
-* @param   mode      0:c+e模式，1:c+p模式
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_flow_db_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *db_en, ZXIC_UINT32 *mode);
-
-/***********************************************************/
-/** 配置桶深最小单位配置:共8档：0-7
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   token_grain    3’d0：最小单位为128K
-*                         3’d1：最小单位为64k
-*                         3’d2：最小单位为32k
-*                         3’d3：最小单位为16k
-*                         3’d4：最小单位为8k
-*                         3’d5：最小单位为4k
-*                         3’d6：最小单位为2k
-*                         3’d7：最小单位为1k
-*           默认为0，即128K
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_token_grain_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 token_grain);
-
-/***********************************************************/
-/** 获取桶深最小单位配置:共8档：0-7
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   token_grain    3’d0：最小单位为128K
-*                         3’d1：最小单位为64k
-*                         3’d2：最小单位为32k
-*                         3’d3：最小单位为16k
-*                         3’d4：最小单位为8k
-*                         3’d5：最小单位为4k
-*                         3’d6：最小单位为2k
-*                         3’d7：最小单位为1k
-*           默认为0，即128K
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_token_grain_get(DPP_DEV_T *dev, ZXIC_UINT32 *token_grain);
-
-/***********************************************************/
-/** 配置流或调度器映射到整形参数表的某个ID
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   id        流或调度器编号ETM:0-ABFF,FTM:0-177F
-* @param   profile_id  整形参数表:[0-127]
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_map_table_set(DPP_DEV_T *dev, ZXIC_UINT32 id, ZXIC_UINT32 profile_id);
-
-/***********************************************************/
-/** 获取流或调度器映射到整形参数表的配置ID
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   id        流或调度器编号ETM:0-ABFF,FTM:0-177F
-* @param   profile_id  整形参数表:[0-127]
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_map_table_get(DPP_DEV_T *dev, ZXIC_UINT32 id, ZXIC_UINT32 *profile_id);
-
-/***********************************************************/
-/** 获取流级整形参数
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id   流队列号 ETM:0-9215,FTM:0-2047
-* @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
-* @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
-*                    注：cbs=0 表示关闭整形,即不限速
-* @param   mode_e    整形模式，0-获取c桶参数，1-获取对应e桶参数
-* @param   p_para_id   整形模板索引：ETM=[0-AFF]，FTM=[0-17F]
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_flow_para_get(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 flow_id,
-                                      ZXIC_UINT32 mode,
-                                      ZXIC_UINT32 *p_para_id,
-                                      DPP_TM_SHAPE_PARA_TABLE *p_flow_para_tbl);
-
-
-/***********************************************************/
-/** etm配置流级整形参数
-* @param   dev_id    设备编号
-* @param   flow_id   流队列号 ETM:0-9215,FTM:0-2047
-* @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
-* @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
-* @param   db_en     双桶整形使能，0-单桶，1-双桶
-* @param   eir       eir速率，单位Kb，范围同cir
-* @param   ebs       ebs桶深，单位Kb，范围同cbs
-*                    注：cbs=0 表示关闭整形,即不限速
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_etm_shape_flow_para_set(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 flow_id,
-                                       ZXIC_UINT32 cir,
-                                       ZXIC_UINT32 cbs,
-                                       ZXIC_UINT32 db_en,
-                                       ZXIC_UINT32 eir,
-                                       ZXIC_UINT32 ebs);
-
-/***********************************************************/
-/** 获取调度单元整形参数
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   se_id     调度器单元号 ETM:0-63FF,FTM:0-77F
-* @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
-* @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
-* @param   mode    整形模式，0-获取p桶参数，1-获取对应c桶参数(仅FQ8/WFQ8支持)
-* @param   p_para_id   整形模板索引：ETM=[0-AFF]，FTM=[0-17F]
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_se_para_get(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 se_id,
-                                    ZXIC_UINT32 mode,
-                                    ZXIC_UINT32 *p_para_id,
-                                    DPP_TM_SHAPE_PARA_TABLE *p_se_para_tbl);
-
-
-
-/***********************************************************/
-/** ftm配置调度器整形参数
-* @param   dev_id    设备编号
-* @param   se_id     调度器编号号 ETM:0x4800-0xABFF,FTM:0x1000-0x177F
-* @param   pir       pir总速率，单位Kb，范围同cir
-* @param   pbs       pbs总桶深，单位Kb，范围同cbs
-* @param   db_en     整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效
-* @param   cir       [0-3]调度器cir速率，单位Kb，范围[64Kb - 160Gb]
-* @param   cbs       [0-3]调度器cbs桶深，单位KB，范围[1KB - 64M]
-*                    注：cbs=0 表示关闭整形,即不限速
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_ftm_shape_se_para_set(ZXIC_UINT32 dev_id,
-                                     ZXIC_UINT32 se_id,
-                                     ZXIC_UINT32 pir,
-                                     ZXIC_UINT32 pbs,
-                                     ZXIC_UINT32 db_en,
-                                     ZXIC_UINT32 cir,
-                                     ZXIC_UINT32 cbs);
-
-/***********************************************************/
-/** etm配置调度器整形参数
-* @param   dev_id    设备编号
-* @param   se_id     调度器编号号 ETM:0x4800-0xABFF,FTM:0x1000-0x177F
-* @param   pir       pir总速率，单位Kb，范围同cir
-* @param   pbs       pbs总桶深，单位Kb，范围同cbs
-* @param   db_en     整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效
-* @param   cir       [0-3]调度器cir速率，单位Kb，范围[64Kb - 160Gb]
-* @param   cbs       [0-3]调度器cbs桶深，单位KB，范围[1KB - 64M]
-*                    注：cbs=0 表示关闭整形,即不限速
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_etm_shape_se_para_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 se_id,
-                                     ZXIC_UINT32 pir,
-                                     ZXIC_UINT32 pbs,
-                                     ZXIC_UINT32 db_en,
-                                     ZXIC_UINT32 cir,
-                                     ZXIC_UINT32 cbs);
-
-
-/***********************************************************/
-/** 写入流/调度器整形参数配置表
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   map_id    整形参数表中模板索引id ETM:0-AFF,FTM:0-17F
-* @param   cir       整形速率(c/e桶统一)
-* @param   cbs       桶深
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_para_set(DPP_DEV_T *dev,
-                                 ZXIC_UINT32 total_para_id,
-                                 ZXIC_UINT32 cir,
-                                 ZXIC_UINT32 cbs);
-
-/***********************************************************/
-/** 读取流/调度器整形参数配置表
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   total_para_id    整形参数表中模板索引id ETM:0-AFF,FTM:0-17F
-* @param   cir       整形速率(c/e桶统一)
-* @param   cbs       桶深
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_para_get(DPP_DEV_T *dev,
-                                 ZXIC_UINT32 total_para_id,
-                                 DPP_TM_SHAPE_PARA_TABLE *p_shap_para_tbl);
-
-/***********************************************************/
-/** 配置第0~15个被统计得到令牌个数的端口号
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   port_id   被统计得到令牌个数的端口号
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/3/15           STM模式下使用
-************************************************************/
-DPP_STATUS dpp_tm_shape_token_pp_cfg(ZXIC_UINT32 dev_id,
-                                     ZXIC_UINT32 port_id);
-
-/***********************************************************/
-/** 打印各级及指定被统计的第0~15个授权流得到的授权个数 stm模式下使用
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_crdt_ackcnt_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 delay_ms);
-
-/***********************************************************/
-/** 读取端口级整形参数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   port_id   端口号
-* @param   p_para   整形信息:CIR/CBS/EN
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/04/15
-************************************************************/
-DPP_STATUS dpp_tm_shape_pp_para_get(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 port_id,
-                                    DPP_TM_SHAPE_PP_PARA_T *p_para);
-
-/***********************************************************/
-/** 配置SA模式下各个版本的授权价值
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sa_ver_id   版本号(0~7)
-* @param   sa_credit_value   授权价值
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  szq      @date  2015/03/25
-************************************************************/
-DPP_STATUS dpp_tm_qmu_sa_credit_value_set(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 sa_ver_id,
-                                          ZXIC_UINT32 sa_credit_value);
-
-/***********************************************************/
-/** 获取SA模式下各个版本的授权价值
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sa_ver_id   版本号(0~7)
-* @param   p_sa_credit_value   授权价值
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  szq      @date  2015/03/25
-************************************************************/
-DPP_STATUS dpp_tm_qmu_sa_credit_value_get(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 sa_ver_id,
-                                          ZXIC_UINT32 *p_sa_credit_value);
-
-/***********************************************************/
-/** 配置CRS发送的速率
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sent_cyc   CRS发送的间隔(单位:时钟周期)
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  szq      @date  2015/03/25
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_sent_rate_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 sent_cyc);
-
-/***********************************************************/
-/** 获取CRS发送的速率
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_sent_cyc   CRS发送的间隔(单位:时钟周期)
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  szq      @date  2015/03/25
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_sent_rate_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_sent_cyc);
-
-/***********************************************************/
-/** 配置CRS过滤使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   配置的值，0-不使能过滤，1-使能过滤
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_filter_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en);
-
-
-/***********************************************************/
-/** 配置多播授权令牌添加个数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   token_add_num   令牌添加时，每次增加的令牌数目，取值范围为1~255，默认为1；禁止配置为0，配置为0时，将不会产生授权。
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_mul_token_gen_num_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 token_add_num);
-
-/***********************************************************/
-/** 配置多播授权整形桶参数和使能参数
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   q3_lb_control_en   3号队列整形功能开启使能。0：关闭；1：开启。
-* @param   q012_lb_control_en   0～2号队列整形功能开启使能。0：关闭；1：开启。
-* @param   q3_lb_max_cnt   3号队列整形桶桶深。
-* @param   q012_lb_max_cnt   0～2号队列整形桶桶深。
-* @param   q3_lb_add_rate   3号队列令牌添加速率，时钟周期为单位。不可配置为0，配置为0整形使能时，不能产生队列3授权调度信号。
-* @param   q012_lb_add_rate   0～2号队列令牌添加速率，以时钟周期单位。不可配置为0，配置为0并整形使能时，不能产生队列0、1、2授权调度信号。
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_mul_ack_lb_set(ZXIC_UINT32 dev_id,
-                                     ZXIC_UINT32 q3_lb_control_en,
-                                     ZXIC_UINT32 q012_lb_control_en,
-                                     ZXIC_UINT32 q3_lb_max_cnt,
-                                     ZXIC_UINT32 q012_lb_max_cnt,
-                                     ZXIC_UINT32 q3_lb_add_rate,
-                                     ZXIC_UINT32 q012_lb_add_rate);
-
-/***********************************************************/
-/** 配置0,1号队列挂接1或2号MCN漏桶信息
-* @param   tm_type   0-ETM,1-FTM
-* @param   dev_id   设备索引编号
-* @param   mcn_lb_sel   0：0,1号队列挂接1号MCN漏桶 1：0,1号队列挂接2号MCN漏桶
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_mcn_lb_sel_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 mcn_lb_sel);
-
-/***********************************************************/
-/** 配置多播队列0~2的授权输出SP、DWRR
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sp_or_dwrr   SP、DWRR模式选择。0：SP；1：DWRR。
-* @param   dwrr_w0   0号队列DWRR权重(0~127)
-* @param   dwrr_w1   1号队列DWRR权重(0~127)
-* @param   dwrr_w2   2号队列DWRR权重(0~127)
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_mul_sp_dwrr_set(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 sp_or_dwrr,
-                                      ZXIC_UINT32 dwrr_w0,
-                                      ZXIC_UINT32 dwrr_w1,
-                                      ZXIC_UINT32 dwrr_w2);
-
-/***********************************************************/
-/** 配置分目的SA整形打开或关闭
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   shap_en   分目的SA整形使能开关 0：表示关闭 1：表示打开
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_dest_sa_shap_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 shap_en);
-
-/***********************************************************/
-/** 获得轮转扫描使能和扫描速率
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   scan_en   轮转扫描使能。0：关闭，1：开启
-* @param   scan_rate   轮转扫描速率，配置扫描周期不得少于256个周期
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/10
-************************************************************/
-DPP_STATUS dpp_tm_qmu_scan_rate_get(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 *p_scan_en,
-                                    ZXIC_UINT32 *p_scan_rate);
-
-/***********************************************************/
-/** 配置轮转扫描队列范围
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   first_que  起始队列号
-* @param   last_que   终止队列号
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/09/10
-************************************************************/
-DPP_STATUS dpp_tm_qmu_scan_que_range_set(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 first_que,
-                                         ZXIC_UINT32 last_que);
-
-/***********************************************************/
-/** 获取轮转扫描队列范围
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   first_que  起始队列号
-* @param   last_que   终止队列号
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/09/10
-************************************************************/
-DPP_STATUS dpp_tm_qmu_scan_que_range_get(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 *first_que,
-                                         ZXIC_UINT32 *last_que);
-
-/***********************************************************/
-/** 获取QMU清空状态
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_clr_done_flag   队列是否清空完成
-*
-* @return
-* @remark  无
-* @see
-* @author  szq      @date  2015/05/21
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qlist_qcfg_clr_done_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_clr_done_flag);
-
-
-/***********************************************************/
-/** 配置qsch调度分端口整形速率和使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   shape_en   整形使能
-* @param   token_add_num   [23:12]:添加令牌数目
-* @param   token_gap   [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1
-* @param   token_depth 桶深，单位B,范围[0-0x1EE00]
-*公式：（600*8*token_num）/(gap+1) = X Mbps
-*     主频= 600 MHz
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  xuhb   2020-5-15
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qsch_port_shape_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 port_id,
-                                     ZXIC_UINT32 token_add_num,
-                                     ZXIC_UINT32 token_gap,
-                                     ZXIC_UINT32 token_depth,
-                                     ZXIC_UINT32 shape_en);
-
-/***********************************************************/
-/** 配置CMD_SW分端口整形速率和使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   shape_en   整形使能
-* @param   token_add_num   [23:12]:添加令牌数目
-* @param   token_gap   [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1
-* @param   token_depth 桶深，单位B,范围[0-0x1EE00]
-*公式：（600*8*token_num）/(gap+1) = X Mbps
-*     主频= 600 MHz
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  whuashan   2020-3-17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_port_shape_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 port_id,
-                                     ZXIC_UINT32 token_add_num,
-                                     ZXIC_UINT32 token_gap,
-                                     ZXIC_UINT32 token_depth,
-                                     ZXIC_UINT32 shape_en);
-
-/***********************************************************/
-/** 获得CMD_SW分端口整形速率和使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_shape_en   整形使能
-* @param   p_token_add_num   [23:12]:添加令牌数目
-* @param   p_token_gap   [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1
-* @param   p_token_depth 桶深，单位B
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  whuashan   2020-3-17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_port_shape_get(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 port_id,
-                                     ZXIC_UINT32 *p_token_add_num,
-                                     ZXIC_UINT32 *p_token_gap,
-                                     ZXIC_UINT32 *p_token_depth,
-                                     ZXIC_UINT32 *p_shape_en);
-
-/***********************************************************/
-/** 获取CMD_SW分端口整形速率和使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   shape_vlue 整形值，单位Mbps
-* @param   shape_en   整形使能
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author   zmy   @20151217
-************************************************************/
-DPP_STATUS dpp_tm_qmu_egress_shape_get(ZXIC_UINT32 dev_id,
-                                       ZXIC_UINT32 port_id,
-                                       ZXIC_UINT32 *shape_value,
-                                       ZXIC_UINT32 *shape_en);
-
-
-/***********************************************************/
-/** 配置需要检测的特定队列号
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   需要检测统计的特定的队列号
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/18
-************************************************************/
-DPP_STATUS dpp_tm_qmu_spec_qnum_set(DPP_DEV_T *dev, ZXIC_UINT32 qnum);
-
-/***********************************************************/
-/** 获得特定的队列号
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_qnum   需要检测统计的特定的队列号
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_spec_qnum_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_qnum);
-
-/***********************************************************/
-/** 配置需要检测的队列组
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   group_num   需要检测统计的特定的队列组。这里按取q的低3bit
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/18
-************************************************************/
-DPP_STATUS dpp_tm_qmu_spec_group_set(DPP_DEV_T *dev, ZXIC_UINT32 group_num);
-
-/***********************************************************/
-/** 获得需要检测的队列组
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_group_num   需要检测统计的特定的队列组。这里按取q的低3bit
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_spec_group_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_group_num);
-
-
-/***********************************************************/
-/** 配置队列授权盈余
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   配置的队列号
-* @param   value   授权盈余
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/18
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crbal_value_set(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 qnum,
-                                      ZXIC_UINT32 value);
-
-/***********************************************************/
-/** 获得队列授权盈余
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   配置的队列号
-* @param   p_value   授权盈余
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crbal_value_get(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 qnum,
-                                      ZXIC_UINT32 *p_value);
-
-/***********************************************************/
-/** 配置分目的SA整形桶深上、下限参数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   max_value   分目的SA整形桶深上限，必须配置为正值
-* @param   min_value   分目的SA整形桶深下限，必须配置为负值
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/18
-************************************************************/
-DPP_STATUS dpp_tm_qmu_dest_sa_shape_para_set(ZXIC_UINT32 dev_id,
-                                             ZXIC_SINT32 max_value,
-                                             ZXIC_SINT32 min_value);
-
-/***********************************************************/
-/** 获得分目的SA整形桶深上、下限参数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_max_value   分目的SA整形桶深上限，必须配置为正值
-* @param   p_min_value   分目的SA整形桶深下限，必须配置为负值
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_dest_sa_shape_para_get(ZXIC_UINT32 dev_id,
-                                             ZXIC_UINT32 *p_max_value,
-                                             ZXIC_UINT32 *p_min_value);
-
-/***********************************************************/
-/** 获取特定队列发送的crs normal的个数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   注 须先设置统计的特定队列
-* @param
-* @return
-* @remark  无
-* @see
-* @author  yjd     @date  2015/07/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_spec_q_crs_normal_cnt(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_que_crs_normal_cnt);
-
-/***********************************************************/
-/** 获取特定队列发送的crs off的个数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   注 须先设置统计的特定队列
-* @param
-* @return
-* @remark  无
-* @see
-* @author  yjd     @date  2015/07/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_spec_q_crs_off_cnt(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_que_crs_off_cnt);
-
-/***********************************************************/
-/** QMU初始化配置场景
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   case_no   四组QMU初始化场景编号为1-4;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8.
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 case_no);
-
-/***********************************************************/
-/** TMMU TM纯片内模式配置获取
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_imem_en  1纯片内
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2017/10/14
-************************************************************/
-DPP_STATUS dpp_tm_tmmu_imem_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_imem_en);
-
-/***********************************************************/
-/** TMMU 强制DDR RDY配置获取
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_ddr_force_rdy  1、如果bit【0】配置为1，则QMU看到的DDR0 RDY一直为1。
-                            2、bit【0】代表DDR0，bit【7】代表DDR7。
-                            3、纯片内模式需要配置为8'hff，排除DDR干扰。
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2017/10/14
-************************************************************/
-DPP_STATUS dpp_tm_tmmu_ddr_force_rdy_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_ddr_force_rdy);
-
-DPP_STATUS dpp_tm_mr_init(ZXIC_UINT32 dev_id);
-/***********************************************************/
-/** 配置TM模式下初始化代码
-* @param   dev_id
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_tm_init_info    配置TM模式下初始化信息包括以下
-*          blk_size  配置qmu block大小
-*          case_num  四组QMU初始化场景编号为1-4;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8.
-*          imem_omem;   0:片内外混合; 1:纯片内;2:纯片外
-*          mode 0:TM 1:SA
-*
-* @return
-* @remark  无
-* @see
-* @author  szq      @date  2015/03/26
-************************************************************/
-DPP_STATUS dpp_tm_asic_init(ZXIC_UINT32 dev_id, DPP_TM_ASIC_INIT_INFO_T *p_tm_asic_init_info);
-
-/***********************************************************/
-/** 配置TM模式下初始化代码
-* @param   dev_id
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_tm_init_info    配置TM模式下初始化信息包括以下
-*          blk_size  配置qmu block大小
-*          case_num  四组QMU初始化场景编号为1-4;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8.
-*          imem_omem;   0:片内外混合; 1:纯片内;2:纯片外
-*          mode 0:TM 1:SA
-*
-* @return
-* @remark  无
-* @see
-* @author  szq      @date  2015/03/26
-************************************************************/
-DPP_STATUS dpp_tm_asic_init_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 blk_size, ZXIC_UINT32 case_num, ZXIC_UINT32 imem_omem, ZXIC_UINT32 mode);
-
-/****************************************************************************
-* 函数名称: dpp_tm_avg_que_len_get
-* 功能描述: 各级平均队列深度获取
-* 输入参数: dev_id: 设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-*           cgavd_level: 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-*           que_id: 本级别层次内的队列编号。
-* 输出参数: p_avg_len: 平均队列深度，单位为BLOCK。
-* 返 回 值: DPP_OK-成功，DPP_ERR-失败
-* 其它说明:
-* author  cy      @date  2015/06/29
-*****************************************************************************/
-DPP_STATUS dpp_tm_avg_que_len_get(ZXIC_UINT32 dev_id,
-                                  DPP_TM_CGAVD_LEVEL_E cgavd_level,
-                                  ZXIC_UINT32 que_id,
-                                  ZXIC_UINT32 *p_avg_len);
-
-/***********************************************************/
-/** 获取配置CPU设置的报文长度是否参与计算丢弃概率的使能
-* @param   tm_type   0-ETM,1-FTM
-* @param   flag   忽略乘法里的当前包长和最大包长比标志位:1为忽略
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy     @date  2015/11/9
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_wred_pke_len_calc_sign_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_flag);
-
-/***********************************************************/
-/**  配置配置cgavd模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   mode   0:block mode 1:byte mode
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/07/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_cfg_mode_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 mode);
-
-
-/***********************************************************/
-/**  配置配置cgavd模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_mode   0:block mode 1:byte mode
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/07/29
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_cfg_mode_get(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 *p_mode);
-
-
-/***********************************************************/
-/** 配置TD拥塞避免模式下的丢弃门限值
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号，系统级时，id参数无效
-* @param   byte_block_th   配置的丢弃门限值，ZXIC_UINT8/BLOCK单位写入寄存器
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/07/29
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_td_byte_block_th_set(DPP_DEV_T *dev,
-                                             DPP_TM_CGAVD_LEVEL_E level,
-                                             ZXIC_UINT32 id,
-                                             ZXIC_UINT32 byte_block_th);
-
-
-/***********************************************************/
-/** 读取TD拥塞避免模式下的丢弃门限值字节模式
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号，系统级时，id参数无效
-* @param   p_byte_block_th   配置的丢弃门限值ZXIC_UINT8/BLOCK单位
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/07/29
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_td_byte_block_th_get(DPP_DEV_T *dev,
-                                             DPP_TM_CGAVD_LEVEL_E level,
-                                             ZXIC_UINT32 id,
-                                             ZXIC_UINT32 *p_byte_block_th);
-
-
-/***********************************************************/
-/**  配置通用门限block模式
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   byte_block_uni_th   通用门限值block/byte单位
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/08/01
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_uniform_byte_block_th_set(DPP_DEV_T *dev, ZXIC_UINT32 byte_block_uni_th);
-
-/***********************************************************/
-/**  读取通用门限
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_byte_block_uni_th   通用门限值block/byte单位
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/08/01
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_uniform_byte_block_th_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_byte_block_uni_th);
-
-
-
-/***********TM CPU软复位接口 Begin*************/
-/***********************************************************/
-/**  设置TM的全局变量，shape_para只保存profile被使用的数量，整形相关参数从寄存器中重新读取
-* @param   dev_id
-* @param   size         data_buff的长度
-* @param   p_data_buff  需要恢复的内容
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2018/06/25
-************************************************************/
-DPP_STATUS dpp_tm_glb_mgr_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 size, ZXIC_UINT8 *p_data_buff);
-
-/***********************************************************/
-/** 获取TM的全局变量，shape_para只保存profile被使用的数量，整形相关参数从寄存器中重新读取
-* @param   dev_id
-* @param   p_flag           上层释放data_buff的标志，1:需要上层free,0:不需要上层free
-* @param   p_size           data_buff的长度
-* @param   pp_data_buff     二级指针(指向函数内部malloc空间的地址)
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2018/06/25
-************************************************************/
-DPP_STATUS dpp_tm_glb_mgr_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_flag, ZXIC_UINT32 *p_size, ZXIC_UINT8 **pp_data_buff);
-
-/***********************************************************/
-/** 获取TM的全局变量，shape_para只保存profile被使用的数量，整形相关参数从寄存器中重新读取
-* @param   dev_id
-* @param   p_size           data_buff的长度
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2018/06/25
-************************************************************/
-DPP_STATUS dpp_tm_glb_size_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_size);
-
-
-/***********************************************************/
-/** 配置tm授权价值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   credit_value   授权价值，默认值是0x5feByte
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/08/13
-************************************************************/
-DPP_STATUS dpp_tm_credit_value_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 credit_value);
-
-/***********************************************************/
-/** 获取全局数组中用户实际配置的整形值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id   流队列号 ETM:0-9215,FTM:0-2047
-* @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
-* @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
-*                    注：cbs=0 表示关闭整形,即不限速
-* @param   mode_e    整形模式，0-获取c桶参数，1-获取对应e桶参数
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark
-* @see
-* @author  xuhb      @date  2019/06/10
-************************************************************/
-DPP_STATUS dpp_tm_shape_flow_para_array_get(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 flow_id,
-                                      ZXIC_UINT32 mode,
-                                      DPP_TM_SHAPE_PARA_TABLE *p_flow_para_tbl);
-
-
-#endif
-/* 必须有个空行，否则可能编不过 */
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_tm.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : djf
+* 完成日期 : 2014/02/25
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#ifndef _DPP_ETM_H_
+#define _DPP_ETM_H_
+
+#include "dpp_tm_api.h"
+#include "dpp_etm_reg.h"
+#if ZXIC_REAL("ETM_MACRO")
+/******************************************************************************
+ *                               START: 宏定义                                *
+ *****************************************************************************/
+#define ETM_WRITE_CHECK (1)
+#define DPP_TM_CGAVD_KILO_UL (1024) /* Kbyte和byte换算 */
+#define DPP_TM_CGAVD_TD_MAX (16 * 512)
+/* CIR颗粒度: bps */
+#define DPP_TM_SHAPE_CIR_STEP \
+	((ZXIC_DOUBLE)400 * 1000 * 1000 * 1000 / 0x3FFFFFE)
+//#define DPP_TM_SHAPE_CIR_STEP  (160069565217 / 0x3FFFFFE)
+/* EIR颗粒度: bps */
+// define DPP_TM_SHAPE_EIR_STEP  ((ZXIC_FLOAT) 160 * 1000 * 1000 * 1000 / 0x3FFFFFE)
+#define DPP_TM_SHAPE_EIR_STEP (160 * 1000 * 1000 * 1000 / 0x3FFFFFE)
+#define DPP_TM_SHAPE_DEFAULT_CBS \
+	(20) /*寄存器写入CBS的最小值，小于该值时，整形不准*/
+#define DPP_TM_KILO_UL (1024)
+#define DPP_TM_KILO_ULL (1000)
+#define DPP_TM_QMU_PORT_SHAP_MAG (1.03)
+#define DPP_ETM_SA_EGRS_MAX_PORTID (66)
+/*cfgmt_byte_mode:0:block mode 1:byte mode*/
+#define DPP_TM_CGAVD_BLOCK_MODE (0)
+#define DPP_TM_CGAVD_ZXIC_UINT8_MODE (1)
+
+/*shap整形模板最大值:每2K流或调度器一一映射一块令牌桶资源,每块资源拥有0-127个模板*/
+/*ETM 0xABFF/2K = 21 */
+#define DPP_ETM_SHAP_TABEL_ID_MAX (22)
+/*FTM 0x17FF/2K = 2 */
+#define DPP_FTM_SHAP_TABEL_ID_MAX (3)
+#define DPP_TM_SHAP_MAP_ID_MAX (128)
+
+/******************************************************************************
+ *                                END: 宏定义                                 *
+ *****************************************************************************/
+#endif /* ETM_MACRO */
+
+#if ZXIC_REAL("ETM_STRUCT")
+/******************************************************************************
+ *                              START: 类型定义                               *
+ *****************************************************************************/
+/* block长度模式 */
+typedef enum dpp_tm_blk_size_e {
+	DPP_ETM_BLK_SIZE_128_B = 0,
+	DPP_ETM_BLK_SIZE_256_B,
+	DPP_ETM_BLK_SIZE_512_B,
+	DPP_ETM_BLK_SIZE_1024_B,
+	DPP_ETM_BLK_SIZE_INVALID
+} DPP_ETM_BLK_SIZE_E;
+
+/* 动态门限放大因子参数 */
+typedef struct dpp_tm_amplify_gene_para_t {
+	ZXIC_UINT32 amplify_gene[16];
+} DPP_ETM_AMPLIFY_GENE_PARA_T;
+
+/* 等价包长阈值 */
+typedef struct dpp_tm_equal_pkt_len_th_para_t {
+	ZXIC_UINT32 equal_pkt_len_th[7];
+} DPP_ETM_EQUAL_PKT_LEN_TH_PARA_T;
+
+/* 等价包长*/
+typedef struct dpp_tm_equal_pkt_len_para_t {
+	ZXIC_UINT32 equal_pkt_len[8];
+} DPP_ETM_EQUAL_PKT_LEN_PARA_T;
+
+/*ETM_STRUCT_STAT */
+typedef enum dpp_tm_cgavd_stat_qnum_e {
+	DPP_ETM_CGAVD_STAT_QNUM1 = 0,
+	DPP_ETM_CGAVD_STAT_QNUM2 = 1,
+	DPP_ETM_CGAVD_STAT_QNUM_INVALID
+} DPP_ETM_CGAVD_STAT_QNUM_E;
+
+typedef enum dpp_tm_cgavd_stat_mode_e {
+	DPP_ETM_CGAVD_STAT_ALL_QUEUE = 0,
+	DPP_ETM_CGAVD_STAT_ONE_QUEUE = 1,
+	DPP_ETM_CGAVD_STAT_MODE_INVALID
+} DPP_ETM_CGAVD_STAT_MODE_E;
+
+typedef struct dpp_tm_cgavd_stat_para_t {
+	DPP_ETM_CGAVD_STAT_MODE_E mode;
+	ZXIC_UINT32 q_id;
+} DPP_ETM_CGAVD_STAT_PARA_T;
+
+typedef struct dpp_tm_cgavd_stat_info_t {
+	DPP_ETM_CGAVD_STAT_MODE_E mode;
+	ZXIC_UINT32 q_id;
+	ZXIC_UINT32 lif_in_pkt_num;
+	ZXIC_UINT32 enqueue_pkt_num;
+	ZXIC_UINT32 dequeue_pkt_num;
+	ZXIC_UINT32 td_drop_pkt_num;
+	ZXIC_UINT32 wred_drop_pkt_num;
+	ZXIC_UINT32 wred_dpi_pkt_num[8];
+	ZXIC_UINT32 gred_drop_pkt_num;
+	ZXIC_UINT32 gred_dpi_pkt_num[8];
+} DPP_ETM_CGAVD_STAT_INFO_T;
+
+typedef struct dpp_tm_qmu_stat_info_t {
+	ZXIC_UINT32 fc_cnt_mode;
+	ZXIC_UINT32 mmu_qmu_wr_fc_cnt;
+	ZXIC_UINT32 mmu_qmu_rd_fc_cnt;
+	ZXIC_UINT32 qmu_cgavd_fc_cnt;
+	ZXIC_UINT32 cgavd_qmu_pkt_cnt;
+	ZXIC_UINT32 cgavd_qmu_pktlen_all;
+	ZXIC_UINT32 cgavd_qmu_drop_tap;
+	ZXIC_UINT32 last_drop_qnum;
+	ZXIC_UINT32 crdt_qmu_credit_cnt;
+	ZXIC_UINT32 qmu_to_qsch_report_cnt;
+	ZXIC_UINT32 qmu_to_cgavd_report_cnt;
+	ZXIC_UINT32 qmu_crdt_crs_normal_cnt;
+	ZXIC_UINT32 qmu_crdt_crs_off_cnt;
+	ZXIC_UINT32 qsch_qlist_shedule_cnt;
+	ZXIC_UINT32 qsch_qlist_sch_ept_cnt;
+	ZXIC_UINT32 qmu_to_mmu_blk_wr_cnt;
+	ZXIC_UINT32 qmu_to_csw_blk_rd_cnt;
+	ZXIC_UINT32 qmu_to_mmu_sop_wr_cnt;
+	ZXIC_UINT32 qmu_to_mmu_eop_wr_cnt;
+	ZXIC_UINT32 qmu_to_mmu_drop_wr_cnt;
+	ZXIC_UINT32 qmu_to_csw_sop_rd_cnt;
+	ZXIC_UINT32 qmu_to_csw_eop_rd_cnt;
+	ZXIC_UINT32 qmu_to_csw_drop_rd_cnt;
+	ZXIC_UINT32 mmu_to_qmu_wr_release_cnt;
+	ZXIC_UINT32 mmu_to_qmu_rd_release_cnt;
+} DPP_ETM_QMU_STAT_INFO_T;
+
+typedef struct dpp_tm_qmu_spec_q_stat_info_t {
+	ZXIC_UINT32 observe_portfc_spec;
+	ZXIC_UINT32 spec_lif_portfc_count;
+	ZXIC_UINT32 observe_qnum_set;
+	ZXIC_UINT32 spec_q_pkt_received;
+	ZXIC_UINT32 spec_q_pkt_dropped;
+	ZXIC_UINT32 spec_q_pkt_scheduled;
+	ZXIC_UINT32 spec_q_wr_cmd_sent;
+	ZXIC_UINT32 spec_q_rd_cmd_sent;
+	ZXIC_UINT32 spec_q_pkt_enq;
+	ZXIC_UINT32 spec_q_pkt_deq;
+	ZXIC_UINT32 spec_q_crdt_uncon_received;
+	ZXIC_UINT32 spec_q_crdt_cong_received;
+	ZXIC_UINT32 spec_q_crs_normal_cnt;
+	ZXIC_UINT32 spec_q_crs_off_cnt;
+} DPP_ETM_QMU_SPEC_Q_STAT_INFO_T;
+
+typedef struct dpp_tm_qmu_spec_bat_stat_info_t {
+	ZXIC_UINT32 observe_batch_set;
+	ZXIC_UINT32 spec_bat_pkt_received;
+	ZXIC_UINT32 spec_bat_pkt_dropped;
+	ZXIC_UINT32 spec_bat_blk_scheduled;
+	ZXIC_UINT32 spec_bat_wr_cmd_sent;
+	ZXIC_UINT32 spec_bat_rd_cmd_sent;
+	ZXIC_UINT32 spec_bat_pkt_enq;
+	ZXIC_UINT32 spec_bat_pkt_deq;
+	ZXIC_UINT32 spec_bat_crdt_uncon_received;
+	ZXIC_UINT32 spec_bat_crdt_cong_received;
+	ZXIC_UINT32 spec_bat_crs_normal_cnt;
+	ZXIC_UINT32 spec_bat_crs_off_cnt;
+} DPP_ETM_QMU_SPEC_BAT_STAT_INFO_T;
+
+typedef struct qmu_port_shape_para {
+	ZXIC_UINT32 shape_value_amplified;
+	ZXIC_UINT32 token_add_num;
+	ZXIC_UINT32 token_gap;
+} QMU_PORT_SHAPE_PARA;
+
+/*etm 实际使用的ddr_attach、bank_num、depth(mmu中看到的)*/
+typedef struct dpp_etm_qmu_init_para {
+	ZXIC_UINT32 etm_mmu_ddr_attach;
+	ZXIC_UINT32 etm_mmu_bank_num;
+	ZXIC_UINT32 etm_mmu_depth;
+} DPP_ETM_QMU_INIT_PARA;
+
+/*ftm 实际使用的ddr_attach、bank_num、depth(mmu中看到的)*/
+typedef struct dpp_ftm_qmu_init_para {
+	ZXIC_UINT32 ftm_mmu_ddr_attach;
+	ZXIC_UINT32 ftm_mmu_bank_num;
+	ZXIC_UINT32 ftm_mmu_depth;
+} DPP_FTM_QMU_INIT_PARA;
+
+typedef struct dpp_tm_crdt_spwfq_start_num_t {
+	ZXIC_UINT32 start_num_fq;
+	ZXIC_UINT32 start_num_fq2;
+	ZXIC_UINT32 start_num_fq4;
+	ZXIC_UINT32 start_num_fq8;
+	ZXIC_UINT32 start_num_sp;
+	ZXIC_UINT32 start_num_wfq;
+	ZXIC_UINT32 start_num_wfq2;
+	ZXIC_UINT32 start_num_wfq4;
+	ZXIC_UINT32 start_num_wfq8;
+} DPP_TM_CRDT_SPWFQ_START_NUM_T;
+
+/******************************************************************************
+ *                               END: 类型定义                                *
+ *****************************************************************************/
+#endif
+
+#if ZXIC_REAL("ETM_FUNCTION")
+/******************************************************************************
+ *                              START: 函数声明                               *
+ *****************************************************************************/
+/***********************************************************/
+/** 打印指定的全局数组值以及清空全局数组
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   para_x   数组index_x
+ * @param   para_y   数组index_y
+ * @param   clear_flag 清空shape全局数组
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark
+ * @see
+ * @author  xuhb      @date  2019/06/10
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_para_array_prt(ZXIC_UINT32 dev_id, ZXIC_UINT32 para_x,
+									   ZXIC_UINT32 para_y,
+									   ZXIC_UINT32 clear_flag);
+
+DPP_STATUS dpp_tm_qmu_qlist_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_num,
+								ZXIC_UINT32 bank_num_para, ZXIC_UINT32 bank_vld,
+								ZXIC_UINT32 gene_para);
+
+DPP_STATUS dpp_tm_cgavd_td_th_together_wr(DPP_DEV_T *dev, ZXIC_UINT32 level,
+										  ZXIC_UINT32 id, ZXIC_UINT32 td_th,
+										  ZXIC_UINT32 num);
+
+DPP_STATUS dpp_tm_cgavd_td_th_together_get(DPP_DEV_T *dev, ZXIC_UINT32 level,
+										   ZXIC_UINT32 id, ZXIC_UINT32 num);
+
+DPP_STATUS dpp_tm_cgavd_dyn_th_en_set_more(DPP_DEV_T *dev,
+										   DPP_TM_CGAVD_LEVEL_E level,
+										   ZXIC_UINT32 id, ZXIC_UINT32 en,
+										   ZXIC_UINT32 num);
+
+/***********************************************************/
+/**  配置基于优先级的QMU接收NPPU数据的fifo阈值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   sp  优先级0~7
+ * @param   th  指定优先级的fifo阈值0~511，单位为fifo条目，fifo深度512
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2016/10/18
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_move_drop_sp_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 sp,
+											ZXIC_UINT32 th);
+
+DPP_STATUS dpp_tm_wred_dp_line_para_wr(ZXIC_UINT32 dev_id, ZXIC_UINT32 level,
+									   ZXIC_UINT32 wred_id, ZXIC_UINT32 dp,
+									   ZXIC_UINT32 max_th, ZXIC_UINT32 min_th,
+									   ZXIC_UINT32 max_p, ZXIC_UINT32 weight,
+									   ZXIC_UINT32 q_len_th);
+
+DPP_STATUS dpp_tm_gred_dp_line_para_wr(ZXIC_UINT32 dev_id, ZXIC_UINT32 dp,
+									   ZXIC_UINT32 max_th, ZXIC_UINT32 mid_th,
+									   ZXIC_UINT32 min_th, ZXIC_UINT32 max_p,
+									   ZXIC_UINT32 weight,
+									   ZXIC_UINT32 q_len_th);
+
+DPP_STATUS dpp_tm_crdt_idle_check(DPP_DEV_T *dev);
+
+/***********************************************************/
+/** 获取各调度器的起始编号（etm共25K=25600,ftm共1920个）
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_spwfq_start_num  调度器起始编号结构体
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/28
+ ************************************************************/
+DPP_STATUS
+dpp_tm_crdt_wfqsp_get(DPP_DEV_T *dev,
+					  DPP_TM_CRDT_SPWFQ_START_NUM_T *p_spwfq_start_num);
+
+/***********************************************************/
+/** 获取调度器挂接配置参数
+ * @param   dev_id      设备编号
+ * @param   tm_type     0-ETM,1-FTM
+ * @param   se_id       调度器编号
+ * @param   p_se_para_tbl  调度器参数
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_se_para_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+								   DPP_ETM_CRDT_SE_PARA_TBL_T *p_se_para_tbl);
+
+/***********************************************************/
+/** 配置QMU工作模式，2M节点或4M节点
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   mode   0-第一种工作模式2M节点，1-第二种工作模式4M节点
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/25
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_qmu_work_mode_set(DPP_DEV_T *dev,
+										  DPP_TM_QMU_WORK_MODE_E mode);
+
+/***********************************************************/
+/** 读取QMU工作模式，2M节点或4M节点
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_mode   0-第一种工作模式2M节点，1-第二种工作模式4M节点
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/25
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_qmu_work_mode_get(DPP_DEV_T *dev,
+										  DPP_TM_QMU_WORK_MODE_E *p_mode);
+
+/***********************************************************/
+/** 配置本地sa_id，SA模式下需要配置
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   sa_id   配置的sa_id值
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/25    ftm模式下使用
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_local_sa_id_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 sa_id);
+
+/***********************************************************/
+/** 读取本地sa_id，SA模式下有效
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_sa_id   读取的sa_id值
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/25
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_local_sa_id_get(ZXIC_UINT32 dev_id,
+										ZXIC_UINT32 *p_sa_id);
+
+/***********************************************************/
+/** CPU设置的各级队列深度配置
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level      拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   q_len_use_cpu_set_en   0：选取RAM中读出的队列深度；
+ * @param                          1：选取q_len_cpu_set值
+ * @param   q_len_cpu_set    CPU设置的各级队列深度,单位为block。
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/06/19
+ ************************************************************/
+DPP_STATUS dpp_tm_q_len_use_cpu_set(DPP_DEV_T *dev, DPP_TM_CGAVD_LEVEL_E level,
+									ZXIC_UINT32 q_len_use_cpu_set_en,
+									ZXIC_UINT32 q_len_cpu_set);
+
+/***********************************************************/
+/** CPU设置的各级平均队列深度配置
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level      拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   q_avg_len_use_cpu_set_en   0：选取RAM中读出的队列深度；
+ * @param                              1：选取q_avg_len_cpu_set值
+ * @param   q_avg_len_cpu_set    CPU设置的各级平均队列深度。
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/06/19
+ ************************************************************/
+DPP_STATUS dpp_tm_q_avg_len_use_cpu_set(DPP_DEV_T *dev,
+										DPP_TM_CGAVD_LEVEL_E level,
+										ZXIC_UINT32 q_avg_len_use_cpu_set_en,
+										ZXIC_UINT32 q_avg_len_cpu_set);
+
+/***********************************************************/
+/** 配置QMU查询队列Qos开关
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   q_id:  队列号
+ * @param   qos_sign: qos开关 0:关闭  1:开启
+ * @param
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/07/03
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_qos_sign_set(DPP_DEV_T *dev, ZXIC_UINT32 q_id,
+								   ZXIC_UINT32 qos_sign);
+
+/***********************************************************/
+/** 配置授权分发使能或者关闭
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   en   配置的值，0-关闭授权分发，1-使能授权分发
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/25
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_credit_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en);
+
+/***********************************************************/
+/** 读取授权分发使能或者关闭
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_en   读出的值，0-关闭授权分发，1-使能授权分发
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/25
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_credit_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en);
+
+/***********************************************************/
+/** 配置授权产生间隔
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   crdt_space_choose  授权发送间隔 0:固定16个周期 1：查表
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/10
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_space_choose_set(ZXIC_UINT32 dev_id,
+										ZXIC_UINT32 crdt_space_choose);
+
+/***********************************************************/
+/** 获得授权产生间隔
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   crdt_space_choose   授权发送间隔 0:固定16个周期 1：查表
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/10
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_space_choose_get(ZXIC_UINT32 dev_id,
+										ZXIC_UINT32 *p_crdt_space_choose);
+
+/***********************************************************/
+/** 配置端口拥塞令牌桶使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   port_id   端口号：0~63
+ * @param   port_en   端口拥塞令牌桶使能，1表示不使用拥塞令牌桶的授权，0表示可以使用拥塞令牌桶授权
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_port_congest_en_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+										   ZXIC_UINT32 port_en);
+
+/***********************************************************/
+/** 获得端口拥塞令牌桶使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   port_id   端口号：0~120
+ * @param   p_port_en   端口拥塞令牌桶使能，1表示不使用拥塞令牌桶的授权，0表示可以使用拥塞令牌桶授权
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  djf      @date  2015/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_port_congest_en_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+										   ZXIC_UINT32 *p_port_en);
+
+/***********************************************************/
+/** 流级中间级补充扫描机制使能配置
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   renew_scan_flow:0为不开启补充扫描  others:开启补充扫描，扫描间隔
+ * @param   renew_scan_mid:0为不开启补充扫描  others:开启补充扫描，扫描间隔
+ * @param
+ * @return
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/07/03
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_renew_scan_set(ZXIC_UINT32 dev_id,
+									  ZXIC_UINT32 renew_scan_flow,
+									  ZXIC_UINT32 renew_scan_mid);
+
+/***********************************************************/
+/** 获取流级中间级补充扫描机制使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   renew_scan_flow:0为不开启补充扫描  others:开启补充扫描，扫描间隔
+ * @param   renew_scan_mid:0为不开启补充扫描  others:开启补充扫描，扫描间隔
+ * @param
+ * @return
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/07/03
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_renew_scan_get(ZXIC_UINT32 dev_id,
+									  ZXIC_UINT32 *renew_scan_flow,
+									  ZXIC_UINT32 *renew_scan_mid);
+
+/***********************************************************/
+/**cpu配置flow_id的crs强制为normal或者off开关使能，用于检测SA模式下队列到授权流的多对一问题
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flow_id:流号(和授权流号一一对应)
+ *                en   强制配置crs的使能，0-不使能，1-使能
+ *                crs_value:强制配置crs的值2'b00:off; 2'b01:low; 2'b10:normal；
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/04/25
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_crs_sheild_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 flow_id,
+									  ZXIC_UINT32 en, ZXIC_UINT32 crs_value);
+
+/***********************************************************/
+/**获取flow_id的crs强制为normal或者off开关使能，用于检测SA模式下队列到授权流的多对一问题
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flow_id:流号(和授权流号一一对应)
+ *                en   强制配置crs的使能，0-不使能，1-使能
+ *                crs_value:强制配置crs的值2'b00:off; 2'b01:low; 2'b10:normal；
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/04/25
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_crs_sheild_get(ZXIC_UINT32 dev_id,
+									  ZXIC_UINT32 *p_flow_id, ZXIC_UINT32 *p_en,
+									  ZXIC_UINT32 *p_crs_value);
+
+/***********************************************************/
+/** 控制授权速率的门限
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   index   0~6
+ * @param   rci_grade_th_0_data
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wush      @date  2017/10/17
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_rci_grade_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 index,
+										ZXIC_UINT32 rci_grade_th_0_data);
+
+DPP_STATUS dpp_tm_crdt_rci_grade_th_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 index,
+										ZXIC_UINT32 *p_rci_grade_th_0_data);
+
+/***********************************************************/
+/** 控制授权间隔的门限，建议大于等于0XF，不可取0；
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   index   0~7
+ * @param   asm_interval_0_data   控制授权间隔的门限，建议大于等于0XF，不可取0；
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wush      @date  2017/10/17
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_asm_interval_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 index,
+										ZXIC_UINT32 asm_interval_0_data);
+
+DPP_STATUS dpp_tm_crdt_asm_interval_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 index,
+										ZXIC_UINT32 *p_asm_interval_0_data);
+
+/***********************************************************/
+/** rci的级别
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_rci_grade_data
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wush      @date  2017/10/17
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_rci_grade_get(ZXIC_UINT32 dev_id,
+									 ZXIC_UINT32 *p_rci_grade_data);
+
+DPP_STATUS dpp_tm_crdt_rci_value_r_get(ZXIC_UINT32 dev_id,
+									   ZXIC_UINT32 *p_crdt_rci_value_r_data);
+
+DPP_STATUS dpp_tm_crdt_interval_now_get(ZXIC_UINT32 dev_id,
+										ZXIC_UINT32 *p_crdt_interval_now_data);
+
+/***********************************************************/
+/** 配置crdt interval使能，
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   crdt_interval_en_cfg_data   授权分发间隔使能，1打开，0关闭
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wush      @date  2017/03/27
+ ************************************************************/
+DPP_STATUS
+dpp_tm_crdt_interval_en_cfg_set(ZXIC_UINT32 dev_id,
+								ZXIC_UINT32 crdt_interval_en_cfg_data);
+
+/***********************************************************/
+/**配置拥塞状态(有效链路数+UCN等级)到授权产生间隔的映射表
+ * @param   dev_id   设备编号
+ * @param   valid_serdes_num   有效的链路数(0~32)
+ * @param   ucn_level   UCN等级(0~7)
+ * @param   cr_clk   授权产生间隔(0~0x3fffff)
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wush      @date  2017/03/28
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_cfgmt_interval_set(ZXIC_UINT32 dev_id,
+										  ZXIC_UINT32 valid_serdes_num,
+										  ZXIC_UINT32 ucn_level,
+										  ZXIC_UINT32 cr_clk);
+
+/***********************************************************/
+/** 读取crdt interval使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   crdt_interval_en_cfg_data   授权分发间隔使能，1打开，0关闭
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wush      @date  2017/03/27
+ ************************************************************/
+DPP_STATUS
+dpp_tm_crdt_interval_en_cfg_get(ZXIC_UINT32 dev_id,
+								ZXIC_UINT32 *p_crdt_interval_en_cfg_data);
+
+/***********************************************************/
+/** 屏蔽ucn/asm_rdy的时能信号
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   ucn_rdy_shield_en   是否屏蔽ucn_rdy信号，1屏蔽，0不屏蔽
+ * @param   asm_rdy_shield_en   是否屏蔽asm_rdy信号，1屏蔽，0不屏蔽
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wush      @date  2017/10/17
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_ucn_asm_rdy_shield_en_set(ZXIC_UINT32 dev_id,
+												 ZXIC_UINT32 ucn_rdy_shield_en,
+												 ZXIC_UINT32 asm_rdy_shield_en);
+
+DPP_STATUS
+dpp_tm_crdt_ucn_asm_rdy_shield_en_get(ZXIC_UINT32 dev_id,
+									  ZXIC_UINT32 *p_ucn_rdy_shield_en,
+									  ZXIC_UINT32 *p_asm_rdy_shield_en);
+
+/***********************************************************/
+/** 配置QMU队列授权价值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   credit_value   授权价值，默认值是400Byte
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/03/04
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_credit_value_set(ZXIC_UINT32 dev_id,
+									   ZXIC_UINT32 credit_value);
+
+/***********************************************************/
+/** QMU DDR随机模式时，DDR随机组配置
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   ddr_num   ddr组数，1-6组
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/03/04
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_ddr_rand_grp_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_num);
+
+/***********************************************************/
+/** 配置QMU DDR BANK随机模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   ddr_random   模式:0-轮询模式；1-随机模式
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/03/04
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_ddr_random_set(ZXIC_UINT32 dev_id,
+									 ZXIC_UINT32 ddr_random);
+
+/***********************************************************/
+/** QMU配置完成寄存器，在QMU链表和DDR随机模式寄存器写入后，将此寄存器写1，完成QMU配置
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/03/04
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_cfg_done_set(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 配置CRS的e桶产生的crbal门限值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   index   crs组数：0~15
+ * @param   crs_th   CRS产生的crbal门限值
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2021/02/14
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_crs_eir_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 index,
+									 ZXIC_UINT32 crs_th);
+
+/***********************************************************/
+/** 配置CRS产生的crbal门限值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   index   crs组数：0~15
+ * @param   crs_th   CRS产生的crbal门限值
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_crs_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 index,
+								 ZXIC_UINT32 crs_th);
+
+/***********************************************************/
+/** 配置CRS产生的空队列确保门限值
+ * @param   dev_id   设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   que_type   队列类型编号(0~15)
+ * @param   empty_que_ack_th   空队列确保授权门限
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/09
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_crs_th2_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_type,
+								  ZXIC_UINT32 empty_que_ack_th);
+
+/***********************************************************/
+/** 配置QMU端口间交织模式
+ * @param   dev_id   设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   pkt_blk_mode   交织模式: 1-按包交织; 0-按block交织SA模式只能配置为1
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  szq      @date  2015/03/25
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_pkt_blk_mode_set(ZXIC_UINT32 dev_id,
+									   ZXIC_UINT32 pkt_blk_mode);
+
+/***********************************************************/
+/** 获取QMU端口间交织模式
+ * @param   dev_id   设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_pkt_blk_mode   交织模式: 0-按包交织; 1-按block交织SA模式只能配置为1
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  szq      @date  2015/03/25
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_pkt_blk_mode_get(ZXIC_UINT32 dev_id,
+									   ZXIC_UINT32 *p_pkt_blk_mode);
+
+/***********************************************************/
+/** 配置读命令老化使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   aged_en   读命令老化使能：0：不使能；1：使能
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_wr_aged_en_set(DPP_DEV_T *dev, ZXIC_UINT32 aged_en);
+
+/***********************************************************/
+/** 配置读命令老化速率
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   scan_time   读命令老化速率（扫描间隔时间）
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_wr_aged_scan_time_set(DPP_DEV_T *dev,
+											ZXIC_UINT32 scan_time);
+
+/***********************************************************/
+/** 获得读命令老化速率
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_scan_time   读命令老化速率（扫描间隔时间）
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_wr_aged_scan_time_get(DPP_DEV_T *dev,
+											ZXIC_UINT32 *p_scan_time);
+
+/***********************************************************/
+/** 配置QMU队列到目的SAId的映射ETM 模式没有，
+FTM 模式才有1024个。
+* @param   dev_id   设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @param   que_id   队列号
+* @param   dest_said   目的said
+*
+* @return   0表示成功 非0表示操作失败
+* @remark  无
+* @see
+* @author  szq      @date  2015/04/08
+************************************************************/
+DPP_STATUS dpp_tm_qmu_qcfg_dest_id_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id,
+									   ZXIC_UINT32 dest_said);
+
+/***********************************************************/
+/** 获取QMU队列到目的SAId的映射ETM 模式没有，
+FTM 模式才有1024个。
+* @param   dev_id   设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @param   que_id   队列号
+* @param   p_dest_said   目的said
+*
+* @return  0表示成功 非0表示操作失败
+* @remark  无
+* @see
+* @author  szq      @date  2015/04/08
+************************************************************/
+DPP_STATUS dpp_tm_qmu_qcfg_dest_id_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id,
+									   ZXIC_UINT32 *p_dest_said);
+
+/***********************************************************/
+/** 配置出队暂存使用的进程总数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   used_inall   出队暂存使用的进程总数=19-N，默认3表示使用16个进程
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/18
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_pid_use_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 used_inall);
+
+/***********************************************************/
+/** 获得出队暂存使用的进程总数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_used_inall   出队暂存使用的进程总数=19-N，默认3表示使用16个进程
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/23
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_pid_use_get(ZXIC_UINT32 dev_id,
+								  ZXIC_UINT32 *p_used_inall);
+
+/***********************************************************/
+/** 配置出队暂存自回加进程总数阈值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   round_th   出队暂存自回加进程总数阈值=19-N，默认4表示使用15个进程就自回加
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/18
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_pid_round_th_set(ZXIC_UINT32 dev_id,
+									   ZXIC_UINT32 round_th);
+
+/***********************************************************/
+/** 获得出队暂存自回加进程总数阈值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_round_th   出队暂存自回加进程总数阈值=19-N，默认4表示使用15个进程就自回加
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/23
+ ************************************************************/
+
+DPP_STATUS dpp_tm_qmu_pid_round_th_get(ZXIC_UINT32 dev_id,
+									   ZXIC_UINT32 *p_round_th);
+
+/***********************************************************/
+/** 配置CRS发送强制使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   en   配置的值，0-不使能，1-使能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/03/04
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_crs_force_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en);
+
+/***********************************************************/
+/** 配置CRS发送强制的队列
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   q_id   队列号
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/03/04
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_crs_force_q_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 q_id);
+
+/***********************************************************/
+/** 配置CRS发送强置的状态
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   crs_state   CRS发送强置的状态
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/18
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_crs_force_state_set(ZXIC_UINT32 dev_id,
+										  ZXIC_UINT32 crs_state);
+
+/***********************************************************/
+/** 配置特定队列发送特定CRS
+* @param   dev_id   设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @param   qnum   队列号
+*               qcfg_qsch_crs_force_crs:CRS状态(0：off；1：normal。)
+*				qcfg_qsch_crs_force_en:CRS发送强置使能(0：不使能；1：使能。)
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  djf      @date  2014/03/04
+************************************************************/
+DPP_STATUS dpp_tm_qmu_qnum_crs_force(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum,
+									 ZXIC_UINT32 qcfg_qsch_crs_force_crs,
+									 ZXIC_UINT32 qcfg_qsch_crs_force_en);
+
+/***********************************************************/
+/** 配置CRS状态
+ * @param   dev_id  设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   qnum   队列号
+ * @param   state
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/19
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_crs_state_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum,
+									ZXIC_UINT32 state);
+
+/***********************************************************/
+/** 获得CRS状态
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   qnum   队列号
+ * @param   p_state
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/23
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_crs_state_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum,
+									ZXIC_UINT32 *p_state);
+
+/***********************************************************/
+/** 配置自动授权队列范围
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   first_que   自授权起始队列号
+ * @param   last_que   自授权终止队列号
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/19
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_auto_credit_que_set(DPP_DEV_T *dev, ZXIC_UINT32 first_que,
+										  ZXIC_UINT32 last_que);
+
+/***********************************************************/
+/** 获得自动授权队列范围
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_first_que   自授权起始队列号
+ * @param   p_last_que   自授权终止队列号
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/23
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_auto_credit_que_get(DPP_DEV_T *dev,
+										  ZXIC_UINT32 *p_first_que,
+										  ZXIC_UINT32 *p_last_que);
+
+/***********************************************************/
+/** 配置自动授权开启使能及扫描速率
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   auto_crdt_en   自动授权开启使能，默认关闭。0：关闭；1：开启
+ * @param   auto_crdt_rate   自授权速率配置
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/19
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_auto_credit_rate_set(DPP_DEV_T *dev,
+										   ZXIC_UINT32 auto_crdt_en,
+										   ZXIC_UINT32 auto_crdt_rate);
+
+/***********************************************************/
+/** 获得自动授权开启使能及扫描速率
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_auto_crdt_en   自动授权开启使能，默认关闭。0：关闭；1：开启
+ * @param   p_auto_crdt_rate   自授权速率配置
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/23
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_auto_credit_rate_get(DPP_DEV_T *dev,
+										   ZXIC_UINT32 *p_auto_crdt_en,
+										   ZXIC_UINT32 *p_auto_crdt_rate);
+
+/***********************************************************/
+/** 配置授权丢弃使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   all_drop_en   所有授权丢弃使能：1：允许丢弃所有授权；0：仅允许丢弃拥塞授权
+ * @param   drop_en   授权丢弃使能：1：允许丢弃授权；0：禁止丢弃授权
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/23
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_crbal_drop_en_set(ZXIC_UINT32 dev_id,
+										ZXIC_UINT32 all_drop_en,
+										ZXIC_UINT32 drop_en);
+
+/***********************************************************/
+/** 获得授权丢弃使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_all_drop_en   所有授权丢弃使能：1：允许丢弃所有授权；0：仅允许丢弃拥塞授权
+ * @param   p_drop_en   授权丢弃使能：1：允许丢弃授权；0：禁止丢弃授权
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/23
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_crbal_drop_en_get(ZXIC_UINT32 dev_id,
+										ZXIC_UINT32 *p_all_drop_en,
+										ZXIC_UINT32 *p_drop_en);
+
+/***********************************************************/
+/**设置自然拥塞反压门限值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param
+ * @return
+ * @remark  无
+ * @see
+ * @author  yjd     @date  2015/07/16
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_qcfg_csch_congest_th_set(DPP_DEV_T *dev,
+											   ZXIC_UINT32 port_id,
+											   ZXIC_UINT32 qmu_congest_th);
+
+/***********************************************************/
+/**获取自然拥塞反压门限值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param
+ * @return
+ * @remark  无
+ * @see
+ * @author  yjd     @date  2015/07/16
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_qcfg_csch_congest_th_get(DPP_DEV_T *dev,
+											   ZXIC_UINT32 port_id,
+											   ZXIC_UINT32 *p_qmu_congest_th);
+
+/***********************************************************/
+/**设置CMD_SCH分优先级反压门限值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param
+ * @return
+ * @remark  无
+ * @see
+ * @author  yjd     @date  2015/07/16
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_qcfg_csch_sp_fc_th_set(DPP_DEV_T *dev,
+											 ZXIC_UINT32 port_id,
+											 ZXIC_UINT32 q_pri,
+											 ZXIC_UINT32 qmu_sp_fc_th);
+
+/***********************************************************/
+/**获取自然拥塞反压门限值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param
+ * @return
+ * @remark  无
+ * @see
+ * @author  yjd     @date  2015/07/16
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_qcfg_csch_sp_fc_th_get(DPP_DEV_T *dev,
+											 ZXIC_UINT32 port_id,
+											 ZXIC_UINT32 q_pri,
+											 ZXIC_UINT32 *p_qmu_sp_fc_th);
+
+/***********************************************************/
+/** 配置QMU需要检测流控的端口号
+ * @param   dev_id   设备号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   port_id   端口号
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/05/07
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_observe_portfc_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id);
+
+/***********************************************************/
+/** 配置pfc使能
+ * @param   dev_id   设备编号
+ * @param   pfc_en   配置的值，0-不使能pfc，1-使能pfc
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  lsy      @date  2022/08/22
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_pfc_en_set(DPP_DEV_T *dev, ZXIC_UINT32 pfc_en);
+
+/***********************************************************/
+/** 读取pfc使能
+ * @param   dev_id   设备编号
+ * @param   pfc_en   配置的值，0-不使能pfc，1-使能pfc
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  lsy      @date  2022/08/22
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_pfc_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *pfc_en);
+
+/***********************************************************/
+/** 配置端口pfc掩码
+ * @param   dev_id   设备编号
+ * @param   port_id   端口号：0~63
+ * @param   port_en   端口掩码配置，1pfc模式下该端口接收olif的优先级反压，
+ *                                  0pfc模式下该端口不接受olif的优先级反压，并将反压信号全部置1
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  lsy      @date  2022/08/22
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_port_pfc_make_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+										ZXIC_UINT32 port_en);
+
+/***********************************************************/
+/** 获得端口pfc掩码
+ * @param   dev_id   设备编号
+ * @param   port_id   端口号：0~63
+ * @param   port_en   端口掩码配置，1pfc模式下该端口接收olif的优先级反压，
+ *                                  0pfc模式下该端口不接受olif的优先级反压，并将反压信号全部置1
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  lsy      @date  2022/08/22
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_port_pfc_make_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+										ZXIC_UINT32 *p_port_en);
+
+/***********************************************************/
+/** QMU初始化配置场景一：4组*2bank，MMU开启rotatjon，MMU实际分配4~7组，每组2~3bank
+ * @param   dev_id   设备编号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_1(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景一：4组*2bank，MMU开启rotatjon，MMU实际分配0~3组，每组2~3bank
+ * @param   dev_id   设备编号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_1(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景一ddr4模式，开启MMU/IP rotatjon，tm看到4组*2bank，对应DDR分配4~7组，每组2~3bank*************
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_1(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配4~7组，每组2~3,6~7bank
+ * @param   dev_id   设备编号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_2(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配0~3组，每组2~3,6~7bank*
+ * @param   dev_id   设备编号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_2(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配4~7组，每组2~3,6~7bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_2(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配4~7组，每组2~3,6~7bank
+ *    depth=64,代表16k
+ * @param   dev_id   设备编号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_pd16k_2(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth);
+
+/***********************************************************/
+/** QMU初始化配置场景二：ddr3模式，8组*8bank
+ *    depth=64,代表16k
+ * @param   dev_id   设备编号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/04/12
+ ************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_chuk32(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth);
+
+/***********************************************************/
+/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配0~3组，每组2~3,6~7bank*
+ * @param   dev_id   设备编号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_pd16k_2(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth);
+
+/***********************************************************/
+/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配4~7组，每组2~3,6~7bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_pd16k_2(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth);
+
+/***********************************************************/
+/** QMU初始化配置场景：ddr3模式，8组ddr*8bank
+ * @param   dev_id   设备编号
+ * @param   depth   bank depth
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/04/12
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_chuk32(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth);
+
+/***********************************************************/
+/** QMU初始化配置场景三：8组*2bank，MMU开启rotatjon，MMU实际分配0~7组，每组6~7bank
+ * @param   dev_id   设备编号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_3(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景三：8组*2bank，MMU开启rotatjon，MMU实际分配0~3组，每组2~3bank
+ * @param   dev_id   设备编号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_3(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景三ETM: 8组*2bank，MMU开启rotatjon，MMU实际分配0~7组，每组6~7bank
+ *     FTM: 8组*2bank，MMU开启rotatjon，MMU实际分配0~3组，每组2~3bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_3(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/**场景4：TM共享2组ddr:FTM为2、4组ddr的01bank，ETM为2、4组ddr 23bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/06/06
+ ************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_4(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/**场景4：TM共享2组ddr:FTM为2、4组ddr的01bank，ETM为2、4组ddr 23bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/06/06
+ ************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_4(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/**场景4：TM共享2组ddr:FTM为2、4组ddr的01bank，ETM为2、4组ddr 23bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/06/06
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_4(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 场景5：TM共享4组ddr:FTM为1234组ddr的01bank，ETM为1234组ddr 23bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/06/06
+ ************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_5(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 场景5：TM共享4组ddr:FTM为1234组ddr的01bank，ETM为1234组ddr 23bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/06/06
+ ************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_5(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 场景5：TM共享4组ddr:FTM为1234组ddr的01bank，ETM为1234组ddr 23bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/06/06
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_5(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景6：4组*2bank，MMU实际分配ftm:4,6,7,9组(01bank); etm:4,6,7,9组(23bank)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/05/13
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_6(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景6：4组*2bank，MMU实际分配ftm:4,6,7,9组(01bank); etm:4,6,7,9组(23bank)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/05/13
+ ************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_6(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景6：4组*2bank，MMU实际分配ftm:4,6,7,9组(01bank); etm:4,6,7,9组(23bank)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/05/13
+ ************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_6(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景6：4组*4bank，MMU实际分配1,2(ftm); 5,6(etm)组，每组2~3 6~7bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_7(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景6：4组*4bank，MMU实际分配5~6组，每组2~3 6~7bank
+ * @param   dev_id   设备编号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_7(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景6：4组*4bank，MMU实际分配1~2组，每组2~3 6~7bank
+ * @param   dev_id   设备编号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_7(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景6：4组*4bank，MMU实际分配1,2(ftm); 5,6(etm)组，每组2~3 6~7bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_8(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景6：4组*4bank，MMU实际分配5~6组，每组2~3 6~7bank
+ * @param   dev_id   设备编号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_8(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景6：4组*4bank，MMU实际分配1~2组，每组2~3 6~7bank
+ * @param   dev_id   设备编号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_8(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景9：4组*2bank，MMU实际分配ftm:6,7,8,9组(01bank); etm:6,7,8,9组(23bank)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/09/28
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_9(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景9：4组*2bank，MMU实际分配ftm:6,7,8,9组(01bank); etm:6,7,8,9组(23bank)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/09/28
+ ************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_9(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景9：4组*2bank，MMU实际分配ftm:6,7,8,9组(01bank); etm:6,7,8,9组(23bank)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/09/28
+ ************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_9(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景10：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/12/16
+ ************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_10(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景10：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/12/16
+ ************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_10(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** QMU初始化配置场景10：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/12/16
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_10(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/**场景11：TM共享2组ddr:FTM为ddr_no1、ddr_no2组ddr的01bank，ETM为ddr_no1、ddr_no2组ddr 23bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/06/06
+ ************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_11(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no1,
+								   ZXIC_UINT32 ddr_no2);
+
+/***********************************************************/
+/**场景11：TM共享2组ddr:FTM为ddr_no1、ddr_no2组ddr的01bank，ETM为ddr_no1、ddr_no2组ddr 23bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/06/06
+ ************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_11(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no1,
+								   ZXIC_UINT32 ddr_no2);
+
+/***********************************************************/
+/**场景4：TM共享2组ddr:FTM为ddr_no1,ddr_no2组ddr的01bank，ETM为ddr_no1,ddr_no2组ddr 23bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/06/06
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_11(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no1,
+								  ZXIC_UINT32 ddr_no2);
+
+/***********************************************************/
+/**
+QMU/MMU初始化配置场景12：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(4567bank); etm:0-9中指定组(0123bank)
+* @param   dev_id   设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  xuhb      @date  2020/4/14
+************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_12(ZXIC_UINT32 dev_id, ZXIC_UINT32 ftm_ddr_no);
+
+/***********************************************************/
+/**
+QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(4567bank); etm:0-9中指定组(0123bank)
+* @param   dev_id   设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  xuhb      @date  2020/4/14
+************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_12(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no);
+
+/***********************************************************/
+/** QMU初始化配置场景13：TM独享4组ddr:FTM为指定4组ddr的0~7bank，
+*                                      ETM为指定4组ddr 0~7bank
+* @param   dev_id   设备编号
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  xuhb      @date  2016/11/17
+************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_13(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no);
+
+/***********************************************************/
+/** QMU初始化配置场景13：TM独享4组ddr:FTM为指定4组ddr的0~7bank，
+*                                      ETM为指定4组ddr 0~7bank
+* @param   dev_id   设备编号
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  xuhb      @date  2016/11/17
+************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_13(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no);
+
+/***********************************************************/
+/** QMU/MMU初始化配置场景13：TM独享4组ddr:FTM为指定4组ddr的0~7bank
+*                                          ETM为指定4组ddr的0-7bank
+*   MMU开启rotatjon
+* @param   dev_id   设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  xuhb      @date  2016/11/17
+************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_13(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no);
+
+/** QMU/MMU初始化配置场景14：每个tm只用1组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/4/14
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_14(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no,
+								  ZXIC_UINT32 ftm_ddr_no);
+
+/** QMU/MMU初始化配置场景14：每个tm只用1组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/4/14
+ ************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_14(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no);
+
+/** QMU/MMU初始化配置场景14：每个tm只用1组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/4/14
+ ************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_14(ZXIC_UINT32 dev_id, ZXIC_UINT32 ftm_ddr_no);
+
+/** QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(0123bank); etm:0-9中指定组(0123bank)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/4/14
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_15(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no,
+								  ZXIC_UINT32 ftm_ddr_no);
+
+/** QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(0123bank); etm:0-9中指定组(0123bank)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/4/14
+ ************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_15(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no);
+
+/** QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(0123bank); etm:0-9中指定组(0123bank)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/4/14
+ ************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_15(ZXIC_UINT32 dev_id, ZXIC_UINT32 ftm_ddr_no);
+
+/***********************************************************/
+/** QMU初始化配置场景16：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/12/16
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set_16(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no,
+								  ZXIC_UINT32 ftm_ddr_no);
+
+/***********************************************************/
+/** QMU初始化配置场景16：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/12/16
+ ************************************************************/
+DPP_STATUS dpp_etm_qmu_init_set_16(ZXIC_UINT32 dev_id, ZXIC_UINT32 ftm_ddr_no);
+
+/***********************************************************/
+/** QMU初始化配置场景16：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/12/16
+ ************************************************************/
+DPP_STATUS dpp_ftm_qmu_init_set_16(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no);
+
+/***********************************************************/
+/** 64k队列的简单挂接函数配置
+*flow0~65535 -> ses0~4095 -> pp0
+:具体为flow0~15挂接到ses0的sp0，flow16~31挂接到ses1的sp0，以此类推
+*                                  ses到PP的挂接都是挂接于pp0的sp0
+*@param   dev_id   设备编号
+*         port_id端口号
+* @
+* @return
+* @remark  无
+* @see
+* @author  cy      @date  2015/06/30
+************************************************************/
+DPP_STATUS dpp_tm_crdt_sch_64k_test(ZXIC_UINT32 dev_id, ZXIC_UINT32 port_id);
+
+/***********************************************************/
+/** 把整数分解成(指定位长)最高有效数和(2的)指数位数的形式，data=p_remdata*2^(p_exp)
+ * @param   data   需要转换前的数
+ * @param   rembitsum   余数的位数
+ * @param   p_remdata   余数大小
+ * @param   p_exp   指数大小
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_rem_and_exp_translate(ZXIC_UINT32 data, ZXIC_UINT32 rembitsum,
+										ZXIC_UINT32 *p_remdata,
+										ZXIC_UINT32 *p_exp);
+
+/***********************************************************/
+/** 配置统计计数寄存器的统计方式
+ * @param   dev_id   设备编号
+ * @param   qnum   支持2组统计寄存器，0-qnum1，1-qnum2
+ * @param   mode   统计方式，0-统计全部队列，1-统计指定q_id
+ * @param   q_id   mode=1时生效，统计该队列的信息
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/03/04
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_stat_q_set(ZXIC_UINT32 dev_id,
+								   DPP_ETM_CGAVD_STAT_QNUM_E qnum,
+								   DPP_ETM_CGAVD_STAT_MODE_E mode,
+								   ZXIC_UINT32 q_id);
+
+/***********************************************************/
+/** 读取统计计数寄存器的计数信息
+ * @param   dev_id   设备编号
+ * @param   qnum   支持2组统计寄存器，0-qnum1，1-qnum2
+ * @param   p_para   获得的统计信息
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/03/04
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_stat_q_get(ZXIC_UINT32 dev_id,
+								   DPP_ETM_CGAVD_STAT_QNUM_E qnum,
+								   DPP_ETM_CGAVD_STAT_INFO_T *p_para);
+
+/***********************************************************/
+/** 配置等价包长
+ * @param   dev_id
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_equal_pkt_len 等价包长
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_equal_pkt_len_para_set(
+		DPP_DEV_T *dev, DPP_ETM_EQUAL_PKT_LEN_PARA_T *p_equal_pkt_len);
+
+/***********************************************************/
+/** 读取等价包长
+ * @param   dev_id
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_equal_pkt_len 等价包长
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_equal_pkt_len_para_get(
+		DPP_DEV_T *dev, DPP_ETM_EQUAL_PKT_LEN_PARA_T *p_equal_pkt_len);
+
+/***********************************************************/
+/** 动态门限放大因子参数配置
+ * @param   dev_id
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_amplify_gene_para 动态门限放大因子参数
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_amplify_gene_para_set(
+		DPP_DEV_T *dev, DPP_ETM_AMPLIFY_GENE_PARA_T *p_amplify_gene_para);
+
+/***********************************************************/
+/** 动态门限放大因子参数获取
+ * @param   dev_id
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_amplify_gene_para 动态门限放大因子参数
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_amplify_gene_para_get(
+		DPP_DEV_T *dev, DPP_ETM_AMPLIFY_GENE_PARA_T *p_amplify_gene_para);
+
+/***********************************************************/
+/** 配置等价包长阈值
+ * @param   dev_id
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_equal_pkt_len_th 等价包长阈值
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_equal_pkt_len_th_para_set(
+		DPP_DEV_T *dev, DPP_ETM_EQUAL_PKT_LEN_TH_PARA_T *p_equal_pkt_len_th);
+
+/***********************************************************/
+/** 配置QMU DDR BANK随机模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_ddr_random   模式:0-轮询模式；1-随机模式
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/03/04
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_ddr_random_get(ZXIC_UINT32 dev_id,
+									 ZXIC_UINT32 *p_ddr_random);
+
+/***********************************************************/
+/** 读取等价包长阈值
+ * @param   dev_id
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_equal_pkt_len_th 等价包长阈值
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_equal_pkt_len_th_para_get(
+		DPP_DEV_T *dev, DPP_ETM_EQUAL_PKT_LEN_TH_PARA_T *p_equal_pkt_len_th);
+
+/***********************************************************/
+/** 读取全部队列的计数信息
+ * @param   dev_id   设备编号*
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark   使用第2组统计寄存器进行统计
+ * @see
+ * @author    yjd    @date  2015/07/04
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_stat_q_all_get_diag(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 读取某一队列统计计数寄存器的计数信息
+ * @param   dev_id   设备编号
+ * @param   q_id   统计该队列的信息
+ *          使用第1组统计寄存器进行统计
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/07/04
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_stat_q_single_get_diag(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/**  配置默认队列使能
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   en   配置的值，0-不使能默认队列，1-使能默认队列，
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wush     @date  2016/08/16
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_default_queue_en_set(ZXIC_UINT32 dev_id,
+											 ZXIC_UINT32 en);
+
+/***********************************************************/
+/**  读取默认队列使能
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_en   读取的值，0-不使能默认队列，1-使能默认队列，
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wush     @date  2016/08/16
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_default_queue_en_get(ZXIC_UINT32 dev_id,
+											 ZXIC_UINT32 *p_en);
+
+/***********************************************************/
+/**  配置默认队列起始末尾
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   def_start_que  起始默认队列block/byte单位
+ * @param   def_finish_que  结束默认队列block/byte单位
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wush     @date  2016/08/16
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_default_queue_set(ZXIC_UINT32 dev_id,
+										  ZXIC_UINT32 def_start_queue,
+										  ZXIC_UINT32 def_finish_queue);
+
+/***********************************************************/
+/**  读取默认队列起始末尾值
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_def_start_que   默认队列起始值block/byte单位
+ * @param   p_def_finish_que   默认队列结束值block/byte单位
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wush      @date  2016/08/16
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_default_queue_get(ZXIC_UINT32 dev_id,
+										  ZXIC_UINT32 *p_def_start_queue,
+										  ZXIC_UINT32 *p_def_finish_queue);
+
+/***********************************************************/
+/**  配置协议队列使能
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   en   配置的值，0-不使能默认队列，1-使能默认队列，
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wush      @date  2016/08/16
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_protocol_queue_en_set(ZXIC_UINT32 dev_id,
+											  ZXIC_UINT32 en);
+
+/***********************************************************/
+/**  读取协议队列使能
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_en   读取的值，0-不使能通用门限，1-使能通用门限，
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wush      @date  2016/08/16
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_protocol_queue_en_get(ZXIC_UINT32 dev_id,
+											  ZXIC_UINT32 *p_en);
+
+/***********************************************************/
+/**  配置协议队列起始末尾
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   protocol_start_que  起始协议队列block/byte单位
+ *@param   protocol_-finish_que 末尾协议队列block/byte单位
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wush      @date  2016/08/16
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_protocol_queue_set(ZXIC_UINT32 dev_id,
+										   ZXIC_UINT32 protocol_start_que,
+										   ZXIC_UINT32 protocol_finish_que);
+
+/***********************************************************/
+/**  读取协议队列起始末尾值
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_protocol_start_que   协议认队列起始值block/byte单位
+ * @param   p_protocol_finish_que   协议认队列末尾值block/byte单位
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wush     @date  2016/08/16
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_protocol_queue_get(ZXIC_UINT32 dev_id,
+										   ZXIC_UINT32 *p_protocol_start_que,
+										   ZXIC_UINT32 *p_protocol_finish_que);
+
+/***********************************************************/
+/** 配置QMU需要统计的队列组
+ * @param   dev_id   设备号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   batch_id   队列组
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/05/07
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_observe_batch_set(DPP_DEV_T *dev, ZXIC_UINT32 batch_id);
+
+/***********************************************************/
+/** 配置QMU需要统计的队列号
+ * @param   dev_id   设备号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   q_id   队列号
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/05/07
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_observe_qnum_set(DPP_DEV_T *dev, ZXIC_UINT32 q_id);
+
+/***********************************************************/
+/** 配置授权盈余初始化值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   crbal_initial_value   授权盈余初始化值
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/03/04
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_crbal_initial_value_set(ZXIC_UINT32 dev_id,
+											  ZXIC_UINT32 crbal_initial_value);
+
+/***********************************************************/
+/**  配置等价包长使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   en   使能标记，0-不使能，1-使能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_equal_pkt_len_en_set(DPP_DEV_T *dev, ZXIC_UINT32 en);
+
+/***********************************************************/
+/**  读取等价包长使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_en   使能标记，0-不使能，1-使能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_equal_pkt_len_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_en);
+
+/***********************************************************/
+/**  读取指定队列获得授权个数(只打印授权非零的队列号)
+ * @param   dev_id   设备编号
+ * @param   ackflow_start   授权起始流号
+ * @param   ackflow_end   授权终止流号
+ * @param   sleep_time_ms   等待时间
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wush      @date  2017/01/19
+ ************************************************************/
+DPP_STATUS dpp_etm_crdt_traffic_diag(ZXIC_UINT32 dev_id,
+									 ZXIC_UINT32 ackflow_start,
+									 ZXIC_UINT32 ackflow_end,
+									 ZXIC_UINT32 sleep_time_ms);
+
+/***********************************************************/
+/**  读取指定队列获得授权个数(只打印授权非零的队列号)
+ * @param   dev_id   设备编号
+ * @param   ackflow_start   授权起始流号
+ * @param   ackflow_end   授权终止流号
+ * @param   sleep_time_ms   等待时间
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wush      @date  2017/01/19
+ ************************************************************/
+DPP_STATUS dpp_ftm_crdt_traffic_diag(ZXIC_UINT32 dev_id,
+									 ZXIC_UINT32 ackflow_start,
+									 ZXIC_UINT32 ackflow_end,
+									 ZXIC_UINT32 sleep_time_ms);
+
+/***********************************************************/
+/** 读取指定队列获得授权个数(只打印授权非零的队列号)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM, 1FTM
+ * @param   ackflow_start   授权流起始
+ * @param   ackflow_end   授权流终止
+ * @param   sleep_time_ms   等待时间
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wush      @date  2017/01/24
+ ************************************************************/
+DPP_STATUS diag_dpp_tm_crdt_traffic_diag(ZXIC_UINT32 dev_id,
+										 ZXIC_UINT32 ackflow_start,
+										 ZXIC_UINT32 ackflow_end,
+										 ZXIC_UINT32 sleep_time_ms);
+
+/***********************************************************/
+/**
+ * @param   dev_id
+ * @param   tm_type
+ * @param   i_or_e_sel
+ * @param   port_or_dest_id_sel
+ * @param   start_id
+ * @param   start_port_dest_id
+ * @param   num
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xjw      @date  2018/02/01
+ ************************************************************/
+DPP_STATUS dpp_tm_olif_stat_set_mul(ZXIC_UINT32 dev_id, ZXIC_UINT32 i_or_e_sel,
+									ZXIC_UINT32 port_or_dest_id_sel,
+									ZXIC_UINT32 start_id,
+									ZXIC_UINT32 start_port_dest_id,
+									ZXIC_UINT32 num);
+
+/******************************************************************************
+ *                               END: 函数声明                                *
+ *****************************************************************************/
+#endif
+
+#if ZXIC_REAL("ETM_STAT")
+
+/***********************************************************/
+/** 打印dpp tm所有模块中断状态
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   dev_id   设备编号
+ * @param
+ * @param
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/07/09
+ ************************************************************/
+DPP_STATUS diag_dpp_tm_int(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 获取tm.c中qmu_init_set中配置的case_num
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   dev_id   设备编号
+ * @param
+ * @param
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/04/15
+ ************************************************************/
+DPP_STATUS dpp_tm_case_no_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *case_no);
+
+/***********************************************************/
+/** 配置dpp tm所有模块中断屏蔽
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   int_mask_flag    0:不屏蔽   1:屏蔽
+ * @param
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/07/09
+ ************************************************************/
+DPP_STATUS dpp_tm_int_mask_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 int_mask_flag);
+
+/***********************************************************/
+/**  读取基于优先级的QMU接收NPPU数据的fifo阈值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   sp  优先级0~7
+ * @param   p_th  指定优先级的fifo阈值0~511，单位为fifo条目，fifo深度512
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2016/10/18
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_move_drop_sp_th_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 sp,
+											ZXIC_UINT32 *p_th);
+
+/***********************************************************/
+/** 打印cgavd模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_mode   0:block mode 1:byte mode
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/07/29
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_cfg_mode_get_diag(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 打印cgavd TD阈值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   id   队列号或端口号，系统级时，id参数无效
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/08/01
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_td_byte_block_th_get_diag(ZXIC_UINT32 dev_id,
+												  DPP_TM_CGAVD_LEVEL_E level,
+												  ZXIC_UINT32 id);
+
+/***********************************************************/
+/** QMU MMU 配置清除
+ * @param   dev_id
+ * @param   tm_type
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XXX      @date  2020/04/13
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_mmu_cfg_clr(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 读取QMU所有队列的统计信息
+ * @param   dev_id   设备编号
+ * @param   p_para   获得的统计信息
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/03/04
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_stat_get(ZXIC_UINT32 dev_id,
+							   DPP_ETM_QMU_STAT_INFO_T *p_para);
+
+/***********************************************************/
+/** 读取QMU指定队列的计数信息
+ * @param   dev_id   设备编号
+ * @param   p_para   获得的统计信息
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/03/04
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_spec_q_stat_get(ZXIC_UINT32 dev_id,
+									  DPP_ETM_QMU_SPEC_Q_STAT_INFO_T *p_para);
+
+/***********************************************************/
+/** 读取QMU指定队列组的计数信息
+ * @param   dev_id   设备编号
+ * @param   p_para   获得的统计信息
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/03/04
+ ************************************************************/
+DPP_STATUS
+dpp_tm_qmu_spec_bat_stat_get(ZXIC_UINT32 dev_id,
+							 DPP_ETM_QMU_SPEC_BAT_STAT_INFO_T *p_para);
+
+/***********************************************************/
+/** 配置QMU流控计数模式
+ * @param   dev_id   设备号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   mode   流控模式，0-电平流控；1-边沿流控
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/05/07
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_fc_cnt_mode_set(DPP_DEV_T *dev, ZXIC_UINT32 mode);
+
+/***********************************************************/
+/** 读取QMU流控计数模式
+ * @param   dev_id   设备号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_mode   流控模式，0-电平流控；1-边沿流控
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/05/07
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_fc_cnt_mode_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_mode);
+
+/***********************************************************/
+/** 打印block长度
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/07/20
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_blk_size_get_diag(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 打印队列空标志查询
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   qnum   配置的队列号
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/06/20
+ ************************************************************/
+DPP_STATUS dpp_tm_qlist_ept_flag_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum);
+
+/***********************************************************/
+/** 获得队列空标志查询
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   qnum   配置的队列号
+ * @param   p_value   队列空标志查询
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/06/20
+ ************************************************************/
+DPP_STATUS dpp_tm_qlist_ept_flag_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum,
+									 ZXIC_UINT32 *p_value);
+
+/***********************************************************/
+/** 获得队列深度计数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   qnum   配置的队列号
+ * @param   p_value  队列深度计数
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/06/20
+ ************************************************************/
+DPP_STATUS dpp_tm_qlist_r_bcnt_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum,
+								   ZXIC_UINT32 *p_value);
+
+/***********************************************************/
+/** 打印队列深度计数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   qnum   配置的队列号
+ * @param   p_value  队列深度计数
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/06/20
+ ************************************************************/
+DPP_STATUS dpp_tm_qlist_r_bcnt_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum);
+
+/***********************************************************/
+/** CMDSCH中分端口分优先级的BLOCK计数
+ * @param   dev_id   设备编号
+ * @param   pri
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/09/19
+ ************************************************************/
+DPP_STATUS dpp_tm_csch_r_block_cnt_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 pri,
+									   ZXIC_UINT32 *p_value);
+
+/***********************************************************/
+/** 打印CMDSCH中分端口分优先级的BLOCK计数
+ * @param   dev_id   设备编号
+ * @param   port
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/09/19
+ ************************************************************/
+DPP_STATUS dpp_tm_csch_r_block_cnt_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 port);
+
+/***********************************************************/
+/** 打印队列入链状态
+ * @param   dev_id   设备编号
+ * @param   flow_id
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/09/19
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_flow_link_state_get_diag(ZXIC_UINT32 dev_id,
+												ZXIC_UINT32 flow_id);
+
+/***********************************************************/
+/** 打印调度器入链状态
+ * @param   dev_id   设备编号
+ * @param   flow_id
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/09/19
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_se_link_state_get_diag(ZXIC_UINT32 dev_id,
+											  ZXIC_UINT32 se_id);
+
+/***********************************************************/
+/** 打印olif的fifo是否空状态
+ * @param   dev_id   设备编号
+ * @param
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/09/19
+ ************************************************************/
+DPP_STATUS dpp_tm_olif_fifo_empty_state_get_diag(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 授权个数统计寄存器清零
+ * @param   dev_id  设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/19
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_clr_diag(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/**cpu配置flow_id的crs强制为normal或者off开关使能，用于检测SA模式下队列到授权流的多对一问题
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flow_id:流号(和授权流号一一对应)
+ *                en   强制配置crs的使能，0-不使能，1-使能
+ *                crs_value:强制配置crs的值2'b00:off; 2'b01:low; 2'b10:normal；
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/04/25
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_crs_sheild_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 flow_id,
+									  ZXIC_UINT32 en, ZXIC_UINT32 crs_value);
+
+/***********************************************************/
+/**获取flow_id的crs强制为normal或者off开关使能，用于检测SA模式下队列到授权流的多对一问题
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flow_id:流号(和授权流号一一对应)
+ *                en   强制配置crs的使能，0-不使能，1-使能
+ *                crs_value:强制配置crs的值2'b00:off; 2'b01:low; 2'b10:normal；
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/04/25
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_crs_sheild_get(ZXIC_UINT32 dev_id,
+									  ZXIC_UINT32 *p_flow_id, ZXIC_UINT32 *p_en,
+									  ZXIC_UINT32 *p_crs_value);
+
+/***********************************************************/
+/** 获得拥塞状态(有效链路数+UCN等级)到授权产生间隔的映射表
+ * @param   dev_id   设备编号
+ * @param   valid_serdes_num   有效的链路数(0~32
+ * @param   ucn_level   UCN等级(0~7)
+ * @param   p_cr_clk   UCN等级(0~7)
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wush      @date  2017/03/28
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_cfgmt_interval_get(ZXIC_UINT32 dev_id,
+										  ZXIC_UINT32 valid_serdes_num,
+										  ZXIC_UINT32 ucn_level,
+										  ZXIC_UINT32 *p_cr_clk);
+
+/***********************************************************/
+/**每隔10s获取crs状态的个数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param
+ * @return
+ * @remark  无
+ * @see
+ * @author  zmy     @date  2015/08/07
+ ************************************************************/
+DPP_STATUS dpp_tm_crs_statics(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id);
+
+/***********************************************************/
+/** 统计QMU发送和CRDT模块指定授权流接收的CRS计数(10s内)
+ * @param   dev_id  设备编号
+ * @param   que_id   QMU队列号
+ * @param   ackflow_id   授权流号
+ * @param   valid_flag   0:队列发送和授权流接收都统计; 1:只关注队列发送，2:只关注授权流接收。
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wush      @date  2017/05/12
+ ************************************************************/
+DPP_STATUS dpp_tm_crs_cnt_prt(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id,
+							  ZXIC_UINT32 ackflow_id, ZXIC_UINT32 valid_flag);
+
+/***********************************************************/
+/** 带停流的统计QMU发送和CRDT模块指定授权流接收的CRS计数
+* @param   dev_id  设备编号
+* @param   que_id   QMU队列号
+* @param   ackflow_id   授权流号
+* @param   valid_flag   0:默认队列发送和授权流接收都统计,此时队列授权都在本板;
+*                       1:只关注队列发送，2:只关注授权流接收，需要与源端队列停流配合使用，
+*                        先停流，运行该函数；或者直接不停流得到的是某段时间的计数。
+* @param   sleep_time   统计多长时间内的crs计数
+*
+* @return  DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  wush      @date  2017/05/12
+************************************************************/
+DPP_STATUS dpp_tm_crs_cnt_prt_1(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id,
+								ZXIC_UINT32 ackflow_id, ZXIC_UINT32 valid_flag,
+								ZXIC_UINT32 sleep_time);
+
+/***********************************************************/
+/** 读取qlist入队及出队状态监控
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2015/08/26
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_qlist_state_query(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 打印被指定统计的第0~15个端口消耗的令牌个数
+* @param   dev_id   设备编号
+* @param   tm_type   0-ETM,1-FTM
+
+* @return  DPP_OK-成功，DPP_ERR-失败
+* @remark  统计时间为2s，其中c桶统计1s，e桶统计1s
+* @see
+* @author  whuashan      @date  2019/03/15
+************************************************************/
+DPP_STATUS dpp_tm_shape_token_dec_cnt_diag(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 打印被指定统计的第0~15个端口接收的令牌个数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  统计时间为2s，其中c桶统计1s，e桶统计1s
+ * @see
+ * @author  whuashan      @date  2019/03/15
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_token_dist_cnt_diag(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 配置olif统计组信息
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   id   olif统计组号
+ * @param   all_or_by_port   0-统计所有，1-统计某一端口或某一dest_id
+ * @param   i_or_e_sel   10-统计片外，01-统计片内，其他值-统计所有
+ * @param   port_or_dest_id_sel   0-统计port，1-统计dest_id
+ * @param   port_dest_id   port号或dest_id号
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/04/21
+ ************************************************************/
+DPP_STATUS dpp_tm_olif_stat_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 id,
+								ZXIC_UINT32 all_or_by_port,
+								ZXIC_UINT32 i_or_e_sel,
+								ZXIC_UINT32 port_or_dest_id_sel,
+								ZXIC_UINT32 port_dest_id);
+
+/***********************************************************/
+/** 查看CRDT接收到和发送的某端口拥塞授权总数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   pp_id   0~63
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/12/08
+ ************************************************************/
+DPP_STATUS diag_dpp_tm_crdt_port_congest_credit_cnt(ZXIC_UINT32 dev_id,
+													ZXIC_UINT32 pp_id);
+
+#endif /*ETM_STAT */
+
+#if ZXIC_REAL("TM_REG")
+/***********************************************************/
+/** 写TM寄存器
+ * @param   module_id 区分TM子模块
+ * @param   addr   基于子模块的地址
+ * @param   data   写入的数据
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/07/26
+ ************************************************************/
+DPP_STATUS dpp_tm_wr_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id,
+						 ZXIC_UINT32 addr, ZXIC_UINT32 data);
+
+/***********************************************************/
+/** 读TM寄存器
+ * @param   module_id 区分TM子模块
+ * @param   addr   基于子模块的地址
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/07/26
+ ************************************************************/
+DPP_STATUS dpp_tm_rd_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id,
+						 ZXIC_UINT32 addr);
+
+/***********************************************************/
+/** 读一片连续的TM寄存器
+ * @param   module_id 区分TM子模块
+ * @param   first_addr   起始寄存器的地址
+ * @param   reg_num   总共读取的寄存器数
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2017/07/26
+ ************************************************************/
+DPP_STATUS dpp_tm_rd_more_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id,
+							  ZXIC_UINT32 first_addr, ZXIC_UINT32 reg_num);
+
+/***********************************************************/
+/** 写tm模块二层间接寄存器(仅crdt/shap模块使用)
+ * @param   module_id 区分TM子模块
+ * @param   addr   基于子模块的地址
+ * @param   data   写入的数据
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/25
+ ************************************************************/
+DPP_STATUS dpp_tm_ind_wr_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id,
+							 ZXIC_UINT32 addr, ZXIC_UINT64 data);
+
+/***********************************************************/
+/** 读tm模块二层间接寄存器(仅crdt/shap模块使用)
+ * @param   module_id 区分TM子模块
+ * @param   addr   基于子模块的地址
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/25
+ ************************************************************/
+DPP_STATUS dpp_tm_ind_rd_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id,
+							 ZXIC_UINT32 addr);
+#endif /*TM_REG */
+
+#if ZXIC_REAL("TM_CFGMT")
+/***********************************************************/
+/** 校验子系统初始化就绪，所有子系统均初始化就绪，p_rdy值为1
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_rdy   初始化就绪标记，1-就绪，0-未就绪
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/04/09
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_subsystem_rdy_check(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** cpu读写通道验证，其读出值等于写入值。读出值不等于写入值时，返回err
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/04/09
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_cpu_check(DPP_DEV_T *dev);
+
+/***********************************************************/
+/** 读取内置TM的工作模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_mode   读取的值，0-TM模式，1-SA模式
+ *ETM仅工作在TM模式，FTM可以工作TM或SA模式
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/25
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_sa_work_mode_get(DPP_DEV_T *dev,
+										 DPP_TM_WORK_MODE_E *p_mode);
+
+/***********************************************************/
+/** 配置ddr3挂接组数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   ddr_num   ddr组数，1-6组
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/04/09
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_ddr_attach_set(DPP_DEV_T *dev, ZXIC_UINT32 ddr_num);
+
+/***********************************************************/
+/** 读取ddr3挂接组数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_ddr_num   ddr组数,1-6组
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/04/09
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_ddr_attach_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_ddr_num);
+
+DPP_STATUS dpp_qmu_init_info(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 配置包存储的CRC功能是否使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   en   配置的值，0-禁止CRC功能，1-允许CRC功能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/25
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_crc_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en);
+
+/***********************************************************/
+/** 配置qmu端口转换使能，SA模式下需要配置
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   en   配置的使能值，0-不使能，1-使能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/25
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_port_transfer_en_set(ZXIC_UINT32 dev_id,
+											 ZXIC_UINT32 en);
+
+/***********************************************************/
+/** 读取qmu端口转换使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_en   读取的使能值，0-不使能，1-使能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/25
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_port_transfer_en_get(ZXIC_UINT32 dev_id,
+											 ZXIC_UINT32 *p_en);
+
+/***********************************************************/
+/** 读取包存储的CRC功能是否使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_en   读取的值，0-禁止CRC功能，1-允许CRC功能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/25
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_crc_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en);
+
+/***********************************************************/
+/** 配置block长度模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   size   block长度模式:256/512/1024
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/04/09
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_blk_size_set(DPP_DEV_T *dev, ZXIC_UINT32 size);
+
+/***********************************************************/
+/** 配置计数模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_mode   计数模式
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/04/09
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_cnt_mode_set(ZXIC_UINT32 dev_id,
+									 DPP_TM_CNT_MODE_T *p_mode);
+
+/***********************************************************/
+/** 读取计数模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_mode   计数模式
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/04/09
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_cnt_mode_get(ZXIC_UINT32 dev_id,
+									 DPP_TM_CNT_MODE_T *p_mode);
+
+/***********************************************************/
+/** 配置中断屏蔽
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_para   中断屏蔽
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/04/09
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_int_mask_set(ZXIC_UINT32 dev_id, DPP_TM_INT_T *p_para);
+
+/***********************************************************/
+/** 读取中断屏蔽
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_para   中断屏蔽
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/04/09
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_int_mask_get(ZXIC_UINT32 dev_id, DPP_TM_INT_T *p_para);
+
+/***********************************************************/
+/** 读取中断状态
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_para   中断状态
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/04/09
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_int_state_get(ZXIC_UINT32 dev_id, DPP_TM_INT_T *p_para);
+
+/***********************************************************/
+/** 配置tm时钟门控是否使能
+ * @param   dev_id   设备编号
+ * @param   en   配置的值，0-禁止tm时钟门控，1-使能tm时钟门控
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  lsy      @date  2022/08/22
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_clkgate_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en);
+
+/***********************************************************/
+/** 读取tm时钟门控是否使能
+* @param   dev_id   设备编号
+* @param   en   配置的值，0-禁止tm时钟门控，1-使能tm时钟门控
+*
+* @return  DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  lsy      @date  2022/08/22
+
+************************************************************/
+DPP_STATUS dpp_tm_cfgmt_clkgate_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en);
+
+/***********************************************************/
+/** 配置tm软复位是否使能
+ * @param   dev_id   设备编号
+ * @param   en   配置的值，0-禁止tm软复位，1-使能tm软复位
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  lsy      @date  2022/08/22
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_softrst_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en);
+
+/***********************************************************/
+/** 读取tm软复位是否使能
+* @param   dev_id   设备编号
+* @param   en   配置的值，0-禁止tm软复位，1-使能tm软复位
+*
+* @return  DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  lsy      @date  2022/08/22
+
+************************************************************/
+DPP_STATUS dpp_tm_cfgmt_softrst_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en);
+
+#endif /*TM_CFGMT */
+
+#if ZXIC_REAL("TM_CGAVD")
+/***********************************************************/
+/**  读取各级搬移功能使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级
+ * @param   p_en   读出的使能标记，0-不使能，1-使能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2016/10/18
+ ************************************************************/
+#ifdef ETM_REAL
+DPP_STATUS dpp_tm_cgavd_move_en_get(ZXIC_UINT32 dev_id,
+									DPP_TM_CGAVD_LEVEL_E level,
+									ZXIC_UINT32 *p_en);
+
+/***********************************************************/
+/** 配置各级搬移门限
+* @param   dev_id 设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+* @param   id   队列号或端口号，系统级时，id参数无效
+* @param   value   端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B；
+*                   流级时为搬移profile_id,0~15
+*
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  djf      @date  2016/10/18
+************************************************************/
+DPP_STATUS dpp_tm_cgavd_move_th_set(ZXIC_UINT32 dev_id,
+									DPP_TM_CGAVD_LEVEL_E level, ZXIC_UINT32 id,
+									ZXIC_UINT32 value);
+
+/***********************************************************/
+/** 读取各级搬移门限
+* @param   dev_id 设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+* @param   id   队列号或端口号，系统级时，id参数无效
+* @param   p_value   端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B；
+*                     流级时为搬移profile_id,0~15
+*
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  djf      @date  2016/10/18
+************************************************************/
+DPP_STATUS dpp_tm_cgavd_move_th_get(ZXIC_UINT32 dev_id,
+									DPP_TM_CGAVD_LEVEL_E level, ZXIC_UINT32 id,
+									ZXIC_UINT32 *p_value);
+
+/***********************************************************/
+/**  读取flow级的搬移策略
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   move_profile  flow级的搬移门限分组索引,0~15
+ * @param   p_th  flow级的搬移门限，单位为KB；
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2016/10/18
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_flow_move_profile_get(ZXIC_UINT32 dev_id,
+											  ZXIC_UINT32 move_profile,
+											  ZXIC_UINT32 *p_th);
+#endif
+/***********************************************************/
+/**  读取端口共享的搬移门限
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_th  端口共享的搬移门限，单位为NPPU存包的单位，256B；
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2016/10/18
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_port_share_th_get(ZXIC_UINT32 dev_id,
+										  ZXIC_UINT32 *p_th);
+
+/***********************************************************/
+/**  读取各级拥塞避免功能使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   要读取的拥塞避免层次号，0:队列级，1:端口级，2:系统级
+ * @param   p_en   读出的使能标记，0-不使能，1-使能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_en_get(DPP_DEV_T *dev, DPP_TM_CGAVD_LEVEL_E level,
+							   ZXIC_UINT32 *p_en);
+
+/***********************************************************/
+/**  dp选取来源
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级
+ * @param   dp_sel   dp选取来源，0-dp，1-tc，2-pkt_len[2:0]
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2017/03/14
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_dp_sel_set(DPP_DEV_T *dev, DPP_TM_CGAVD_LEVEL_E level,
+								   DPP_TM_CGAVD_DP_SEL_E dp_sel);
+
+/***********************************************************/
+/** 读取拥塞避免算法
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   id   队列号或端口号,系统级时,id参数无效
+ * @param   p_method   配置的拥塞避免算法,0:TD,1:WRED/GRED
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_method_get(DPP_DEV_T *dev, DPP_TM_CGAVD_LEVEL_E level,
+								   ZXIC_UINT32 id,
+								   DPP_TM_CGAVD_METHOD_E *p_method);
+
+/***********************************************************/
+/** 流队列级队列深度的获取
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   que_id      队列号
+ *          p_len       队列深度以KB为单位
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/06/19
+ ************************************************************/
+DPP_STATUS dpp_tm_flow_que_len_get(DPP_DEV_T *dev, ZXIC_UINT32 que_id,
+								   ZXIC_UINT32 *p_len);
+
+/***********************************************************/
+/** 端口级队列深度的获取
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   pp_id      队列号
+ *          pp_len       队列深度以KB为单位
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/06/19
+ ************************************************************/
+DPP_STATUS dpp_tm_port_que_len_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 pp_id,
+								   ZXIC_UINT32 *pp_len);
+
+/***********************************************************/
+/** 系统级队列深度的获取
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   sys_len       系统级深度以block为单位
+ *          sys_protocol_len       系统级包含协议队列深度以KB为单位
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/06/19
+ ************************************************************/
+DPP_STATUS dpp_tm_sys_que_len_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *sys_len,
+								  ZXIC_UINT32 *sys_protocol_len);
+
+/***********************************************************/
+/** 读取TD拥塞避免模式下的丢弃门限值
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   id   队列号或端口号，系统级时，id参数无效
+ * @param   p_td_th   配置的丢弃门限值
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_td_th_get(DPP_DEV_T *dev, DPP_TM_CGAVD_LEVEL_E level,
+								  ZXIC_UINT32 id, ZXIC_UINT32 *p_td_th);
+
+/***********************************************************/
+/** 读取指定端口或队列绑定的WRED GROUP ID
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   WRED支持层次号，0:队列级，1:端口级
+ * @param   id   队列号或端口号
+ * @param   p_wred_id   配置的WRED GROUP ID
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_wred_id_get(ZXIC_UINT32 dev_id,
+									DPP_TM_CGAVD_LEVEL_E level, ZXIC_UINT32 id,
+									ZXIC_UINT32 *p_wred_id);
+
+/***********************************************************/
+/** 读取WRED丢弃曲线对应的参数
+* @param   dev_id   设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @param   level   WRED支持层次号，0:队列级，1:端口级
+* @param   wred_id   队列级共支持16个WRED组0-15，端口级支持8组0-7
+* @param   dp   共支持8个dp，取值0-7
+* @param   p_para   配置的WRED组参数值，包含以下五个参数
+*           max_th  平均队列深度上限阈值
+*           min_th  平均队列深度下限阈值
+*           max_p  最大丢弃概率
+*           weight   平均队列深度计算权重
+*           q_len_th 队列深度阈值
+*
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  taq     @date  2015/04/20
+************************************************************/
+DPP_STATUS dpp_tm_cgavd_wred_dp_line_para_get(
+		ZXIC_UINT32 dev_id, DPP_TM_CGAVD_LEVEL_E level, ZXIC_UINT32 wred_id,
+		ZXIC_UINT32 dp, DPP_TM_WRED_DP_LINE_PARA_T *p_para);
+
+/***********************************************************/
+/** 配置系统级GRED丢弃曲线对应的参数
+* @param   dev_id 设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @param   dp   共支持8个dp，取值0-7
+* @param   p_para  配置的GRED丢弃曲线参数值，包含以下六个参数
+*           max_th  平均队列深度上限阈值
+*           mid_th  平均队列深度中间阈值
+*           min_th  平均队列深度下限阈值
+*           max_p   最大丢弃概率
+*           weight   平均队列深度计算权重
+*           q_len_th 队列深度阈值
+*
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  taq      @date  2015/04/20
+************************************************************/
+DPP_STATUS
+dpp_tm_cgavd_gred_dp_line_para_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 dp,
+								   DPP_TM_GRED_DP_LINE_PARA_T *p_para);
+
+/***********************************************************/
+/** 配置系统级阶梯TD 丢弃曲线对应的参数
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   dp   共支持8个dp，取值0-7
+ * @param   td_th  TD 门限
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/08/02
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_ladtd_dp_line_para_set(ZXIC_UINT32 dev_id,
+											   ZXIC_UINT32 dp,
+											   ZXIC_UINT32 td_th);
+
+/***********************************************************/
+/** 读取系统级GRED丢弃曲线对应的参数
+* @param   dev_id 设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @param   dp   共支持8个dp，取值0-7
+* @param   p_para  配置的GRED丢弃曲线参数值，包含以下六个参数
+*           max_th  平均队列深度上限阈值
+*           mid_th  平均队列深度中间阈值
+*           min_th  平均队列深度下限阈值
+*           max_p   最大丢弃概率
+*           weight   平均队列深度计算权重
+*           q_len_th 队列深度阈值
+*
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  taq      @date  2015/04/20
+************************************************************/
+DPP_STATUS
+dpp_tm_cgavd_gred_dp_line_para_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 dp,
+								   DPP_TM_GRED_DP_LINE_PARA_T *p_para);
+
+/***********************************************************/
+/** 读取指定端口或队列是否支持动态门限机制
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   WRED支持层次号，0:队列级，1:端口级
+ * @param   id   队列号或端口号
+ * @param   p_en   读取的值，0-不支持动态门限机制，1-支持动态门限机制
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_dyn_th_en_get(DPP_DEV_T *dev,
+									  DPP_TM_CGAVD_LEVEL_E level,
+									  ZXIC_UINT32 id, ZXIC_UINT32 *p_en);
+
+/***********************************************************/
+/**  配置通用门限使能
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   en   配置的值，0-不使能通用门限，1-使能通用门限，
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_uniform_th_en_set(DPP_DEV_T *dev, ZXIC_UINT32 en);
+
+/***********************************************************/
+/**  读取通用门限使能
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_en   读取的值，0-不使能通用门限，1-使能通用门限，
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_uniform_th_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_en);
+
+/***********************************************************/
+/**  配置通用门限
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   th   通用门限值
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_uniform_th_set(DPP_DEV_T *dev, ZXIC_UINT32 th);
+
+/***********************************************************/
+/**  读取通用门限
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_th   通用门限值
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_uniform_th_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_th);
+
+/***********************************************************/
+/**  配置流队列所属优先级
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   q_id   队列号
+ * @param   pri   配置的优先级，0~7
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_q_pri_set(DPP_DEV_T *dev, ZXIC_UINT32 q_id,
+								  ZXIC_UINT32 pri);
+
+/***********************************************************/
+/** 读取TM模式下流队列挂接的端口号；SA模式下流队列映射的目的芯片ID
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   q_id   队列号
+ * @param   p_pp_id   读取的端口号
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/18
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_q_map_pp_get(DPP_DEV_T *dev, ZXIC_UINT32 q_id,
+									 ZXIC_UINT32 *p_pp_id);
+
+/***********************************************************/
+/** 读取配置TM模式tc到flow的映射
+ * @param   dev_id 设备编号
+ * @param   tc_id   itmd tc优先级（0~7）
+ * @param   flow_id 读取映射的flowid号 （0~4095）
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/07/04
+ ************************************************************/
+DPP_STATUS dpp_tm_tc_map_flow_get(DPP_DEV_T *dev, ZXIC_UINT32 tc_id,
+								  ZXIC_UINT32 *flow_id);
+
+/***********************************************************/
+/**  获取强制片内或片外
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   en      1:使能
+ * @param   mode   1 :omem 强制片外  0:imem 强制片内
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wush      @date  2017/10/14
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_imem_omem_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en,
+									  ZXIC_UINT32 *p_mode);
+
+/***********************************************************/
+/** 连续配置各级搬移门限
+* @param   dev_id 设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+* @param   start_id 为起始 队列号或端口号，系统级时，id参数无效
+* @param   value   端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B；
+*                   流级时为搬移profile_id,0~15
+* @param  num   为队列或端口个数
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  wush      @date  2016/11/19
+************************************************************/
+#ifdef ETM_REAL
+DPP_STATUS dpp_tm_cgavd_move_th_together_wr(ZXIC_UINT32 dev_id,
+											DPP_TM_CGAVD_LEVEL_E level,
+											ZXIC_UINT32 start_id,
+											ZXIC_UINT32 value, ZXIC_UINT32 num);
+#endif
+/***********************************************************/
+/** 系统级缓存使用上下限阈值配置
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   th_h: 系统级缓存使用上限阈值
+ * @param   th_l: 系统级缓存使用下限阈值
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/07/03
+ ************************************************************/
+DPP_STATUS dpp_tm_sys_window_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 th_h,
+									ZXIC_UINT32 th_l);
+
+/***********************************************************/
+/** 配置cgavd强制反压
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   cgavd_fc: 0:不强制反压    1:强制反压
+ * @param
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/07/03
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_cfg_fc_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 cgavd_fc);
+
+/***********************************************************/
+/** 获取cgavd强制反压状态
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   cgavd_fc: 0:不强制反压    1:强制反压
+ * @param
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/07/03
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_cfg_fc_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *cgavd_fc);
+
+/***********************************************************/
+/** 配置cgavd强制不反压
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   cgavd_no_fc: 0:不强制     1:强制不反压
+ * @param
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/07/03
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_cfg_no_fc_set(ZXIC_UINT32 dev_id,
+									  ZXIC_UINT32 cgavd_no_fc);
+
+/***********************************************************/
+/** 获取cgavd强制不反压状态
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   cgavd_no_fc: 0:不强制 1:强制不反压
+ * @param
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/07/03
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_cfg_no_fc_get(ZXIC_UINT32 dev_id,
+									  ZXIC_UINT32 *cgavd_no_fc);
+
+/***********************************************************/
+/** 配置cgavd平均队列深度归零
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   en: 0:关闭     1:使能
+ * @param
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/08/05
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_avg_qlen_return_zero_en_set(ZXIC_UINT32 dev_id,
+													ZXIC_UINT32 en);
+#endif /*TM_CGAVD */
+
+/** crdt ram初始化
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/22
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_ram_init(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 获取调度器类型
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   se_id     调度器编号
+ * @param   item_num  调度器中包含的子调度器个数
+ * @param   sch_type_num  调度器类型编号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/26
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_sch_type_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+									ZXIC_UINT32 *item_num,
+									ZXIC_UINT32 *sch_type_num);
+
+/***********************************************************/
+/** 配置flow级流队列的挂接关系(flow到上级调度器的挂接)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flow_id   流队列号
+ * @param   c_linkid  c桶要挂接到的上级调度器id
+ * @param   c_weight  c桶挂接到上级调度器的权重[1~511]
+ * @param   c_sp      c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
+ * @param   mode      挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可
+ * @param   e_linkid  e桶要挂接到的上级调度器id
+ * @param   e_weight  e桶挂接到上级调度器的权重[1~511]
+ * @param   e_sp      e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_flow_link_wr(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									DPP_TM_SCH_FLOW_PARA_T *p_flow_para);
+
+/***********************************************************/
+/** 批量配置flow级流队列的挂接关系
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flow_id_s 起始流队列号
+ * @param   flow_id_e 终止流队列号
+ * @param   c_linkid  c桶要挂接到的上级调度器id
+ * @param   c_weight  c桶挂接到上级调度器的权重[1~511]
+ * @param   c_sp      c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
+ * @param   mode      挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可
+ * @param   e_linkid  e桶要挂接到的上级调度器id
+ * @param   e_weight  e桶挂接到上级调度器的权重[1~511]
+ * @param   e_sp      e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS
+dpp_tm_crdt_flow_link_more_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id_s,
+							   ZXIC_UINT32 flow_id_e, ZXIC_UINT32 c_linkid,
+							   ZXIC_UINT32 c_weight, ZXIC_UINT32 c_sp,
+							   ZXIC_UINT32 mode, ZXIC_UINT32 e_linkid,
+							   ZXIC_UINT32 e_weight, ZXIC_UINT32 e_sp);
+
+/***********************************************************/
+/** 配置调度器层次化QOS的挂接关系:非优先级传递
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   se_id      本级调度器id
+ * @param   se_linkid  要挂接到的上级调度器id
+ * @param   se_weight  挂接到上级调度器的权重[1~511]
+ * @param   se_sp      挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
+ * @param   se_insw    优先级传递使能：0-关 1-开。该参数不传递直接配0
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_se_link_wr(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+								  DPP_TM_SCH_SE_PARA_T *p_sch_se_para);
+
+/***********************************************************/
+/** 配置调度器层次化QOS的挂接关系:优先级传递
+ * @param   dev_id       设备编号
+ * @param   tm_type      0-ETM,1-FTM
+ * @param   se_id        本级调度器id
+ * @param   se_linkid    要挂接到的上级调度器id
+ * @param   se_sp        挂接到上级调度器的sp优先级,有效值[0-3],最多4级，优先级按调度单元分配，
+ *                       每个调度单元内部调度器优先级相同！
+ * @param   se_weight0-7 WFQ8中各调度器权重值[1~511]，若是WFQ2/4 只取前面对应值，后面无效
+ * @param   se_insw      优先级传递使能：0-关 1-开. 该参数不传递直接配1
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS
+dpp_tm_crdt_se_link_insw_wr(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+							DPP_TM_SCH_SE_PARA_INSW_T *p_sch_se_para_insw);
+
+/***********************************************************/
+/** 获取流队列入链状态
+ * @param   dev_id      设备编号
+ * @param   tm_type     0-ETM,1-FTM
+ * @param   flow_id     流队列号
+ * @param   link_state  0-未入链     1-在调度器链表中
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_flow_link_state_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+										   ZXIC_UINT32 *link_state);
+
+/***********************************************************/
+/** 获取调度器入链状态
+ * @param   dev_id      设备编号
+ * @param   tm_type     0-ETM,1-FTM
+ * @param   se_id       调度器编号
+ * @param   link_state  0-未入链     1-在调度器链表中
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_se_link_state_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+										 ZXIC_UINT32 *link_state);
+
+/***********************************************************/
+/** 判断crdt流删除命令是否空闲
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_del_cmd_idle(DPP_DEV_T *dev);
+
+/***********************************************************/
+/** 删除流/调度器挂接关系
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   id        要删除的流号或调度器id
+ *          ETM范围:0--0xABFF; FTM范围:0-0x177F
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_del_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id);
+
+/***********************************************************/
+/** 获取pp->dev挂接关系
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   pp_id   0~63
+ * @param   p_weight  0~127
+ * @param   p_sp_mapping   0~7
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/04/20
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_pp_para_get(DPP_DEV_T *dev, ZXIC_UINT32 pp_id,
+								   ZXIC_UINT32 *p_weight,
+								   ZXIC_UINT32 *p_sp_mapping);
+
+/***********************************************************/
+/**
+ * @param   dev_id   设备编号
+ * @param   tm_type  0-ETM,1-FTM
+ * @param   que_id_s 起始队列号
+ * @param   que_id_e 终止队列号
+ * @param   en       1:过滤E桶队列CRS状态为SLOW的入链请求；0:E桶队列CRS SLOW正常入链；
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XXX      @date  2019/05/08
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_more_set(ZXIC_UINT32 dev_id,
+												  ZXIC_UINT32 que_id_s,
+												  ZXIC_UINT32 que_id_e,
+												  ZXIC_UINT32 en);
+
+/***********************************************************/
+/**
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   que_id   queue id
+ * @param   p_en
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XXX      @date  2019/05/08
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_get(ZXIC_UINT32 dev_id,
+											 ZXIC_UINT32 que_id,
+											 ZXIC_UINT32 *p_en);
+
+/***********************************************************/
+/**
+ * @param   dev_id
+ * @param   tm_type
+ * @param   que_id
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XXX      @date  2019/05/08
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_get_diag(ZXIC_UINT32 dev_id,
+												  ZXIC_UINT32 que_id);
+
+/***********************************************************/
+/** 打印指定的全局数组值以及清空全局数组
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   para_x   数组index_x
+ * @param   para_y   数组index_y
+ * @param   clear_flag 清空shape全局数组
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark
+ * @see
+ * @author  xuhb      @date  2019/06/10
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_para_array_prt(ZXIC_UINT32 dev_id, ZXIC_UINT32 para_x,
+									   ZXIC_UINT32 para_y,
+									   ZXIC_UINT32 clear_flag);
+
+/***********************************************************/
+/** 配置shap模块中 crd_grain授权价值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   credit_value   授权价值，默认值是0x5feByte
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/08/13
+ ************************************************************/
+DPP_STATUS dpp_tm_shap_crd_grain_set(ZXIC_UINT32 dev_id,
+									 ZXIC_UINT32 credit_value);
+
+/***********************************************************/
+/** shap ram初始化
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/22
+ ************************************************************/
+DPP_STATUS dpp_tm_shap_ram_init(ZXIC_UINT32 dev_id);
+
+/***********************************************************/
+/** 获取流队列双桶整形使能及模式
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   db_en     双桶整形使能
+ * @param   mode      0:c+e模式，1:c+p模式
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_flow_db_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *db_en,
+									   ZXIC_UINT32 *mode);
+
+/***********************************************************/
+/** 配置桶深最小单位配置:共8档：0-7
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   token_grain    3’d0：最小单位为128K
+ *                         3’d1：最小单位为64k
+ *                         3’d2：最小单位为32k
+ *                         3’d3：最小单位为16k
+ *                         3’d4：最小单位为8k
+ *                         3’d5：最小单位为4k
+ *                         3’d6：最小单位为2k
+ *                         3’d7：最小单位为1k
+ *           默认为0，即128K
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_token_grain_set(ZXIC_UINT32 dev_id,
+										ZXIC_UINT32 token_grain);
+
+/***********************************************************/
+/** 获取桶深最小单位配置:共8档：0-7
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   token_grain    3’d0：最小单位为128K
+ *                         3’d1：最小单位为64k
+ *                         3’d2：最小单位为32k
+ *                         3’d3：最小单位为16k
+ *                         3’d4：最小单位为8k
+ *                         3’d5：最小单位为4k
+ *                         3’d6：最小单位为2k
+ *                         3’d7：最小单位为1k
+ *           默认为0，即128K
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_token_grain_get(DPP_DEV_T *dev,
+										ZXIC_UINT32 *token_grain);
+
+/***********************************************************/
+/** 配置流或调度器映射到整形参数表的某个ID
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   id        流或调度器编号ETM:0-ABFF,FTM:0-177F
+ * @param   profile_id  整形参数表:[0-127]
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_map_table_set(DPP_DEV_T *dev, ZXIC_UINT32 id,
+									  ZXIC_UINT32 profile_id);
+
+/***********************************************************/
+/** 获取流或调度器映射到整形参数表的配置ID
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   id        流或调度器编号ETM:0-ABFF,FTM:0-177F
+ * @param   profile_id  整形参数表:[0-127]
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_map_table_get(DPP_DEV_T *dev, ZXIC_UINT32 id,
+									  ZXIC_UINT32 *profile_id);
+
+/***********************************************************/
+/** 获取流级整形参数
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flow_id   流队列号 ETM:0-9215,FTM:0-2047
+ * @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
+ * @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
+ *                    注：cbs=0 表示关闭整形,即不限速
+ * @param   mode_e    整形模式，0-获取c桶参数，1-获取对应e桶参数
+ * @param   p_para_id   整形模板索引：ETM=[0-AFF]，FTM=[0-17F]
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_flow_para_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									  ZXIC_UINT32 mode, ZXIC_UINT32 *p_para_id,
+									  DPP_TM_SHAPE_PARA_TABLE *p_flow_para_tbl);
+
+/***********************************************************/
+/** etm配置流级整形参数
+ * @param   dev_id    设备编号
+ * @param   flow_id   流队列号 ETM:0-9215,FTM:0-2047
+ * @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
+ * @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
+ * @param   db_en     双桶整形使能，0-单桶，1-双桶
+ * @param   eir       eir速率，单位Kb，范围同cir
+ * @param   ebs       ebs桶深，单位Kb，范围同cbs
+ *                    注：cbs=0 表示关闭整形,即不限速
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_etm_shape_flow_para_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									   ZXIC_UINT32 cir, ZXIC_UINT32 cbs,
+									   ZXIC_UINT32 db_en, ZXIC_UINT32 eir,
+									   ZXIC_UINT32 ebs);
+
+/***********************************************************/
+/** 获取调度单元整形参数
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   se_id     调度器单元号 ETM:0-63FF,FTM:0-77F
+ * @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
+ * @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
+ * @param   mode    整形模式，0-获取p桶参数，1-获取对应c桶参数(仅FQ8/WFQ8支持)
+ * @param   p_para_id   整形模板索引：ETM=[0-AFF]，FTM=[0-17F]
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_se_para_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+									ZXIC_UINT32 mode, ZXIC_UINT32 *p_para_id,
+									DPP_TM_SHAPE_PARA_TABLE *p_se_para_tbl);
+
+/***********************************************************/
+/** ftm配置调度器整形参数
+ * @param   dev_id    设备编号
+ * @param   se_id     调度器编号号 ETM:0x4800-0xABFF,FTM:0x1000-0x177F
+ * @param   pir       pir总速率，单位Kb，范围同cir
+ * @param   pbs       pbs总桶深，单位Kb，范围同cbs
+ * @param   db_en     整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效
+ * @param   cir       [0-3]调度器cir速率，单位Kb，范围[64Kb - 160Gb]
+ * @param   cbs       [0-3]调度器cbs桶深，单位KB，范围[1KB - 64M]
+ *                    注：cbs=0 表示关闭整形,即不限速
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_ftm_shape_se_para_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 se_id,
+									 ZXIC_UINT32 pir, ZXIC_UINT32 pbs,
+									 ZXIC_UINT32 db_en, ZXIC_UINT32 cir,
+									 ZXIC_UINT32 cbs);
+
+/***********************************************************/
+/** etm配置调度器整形参数
+ * @param   dev_id    设备编号
+ * @param   se_id     调度器编号号 ETM:0x4800-0xABFF,FTM:0x1000-0x177F
+ * @param   pir       pir总速率，单位Kb，范围同cir
+ * @param   pbs       pbs总桶深，单位Kb，范围同cbs
+ * @param   db_en     整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效
+ * @param   cir       [0-3]调度器cir速率，单位Kb，范围[64Kb - 160Gb]
+ * @param   cbs       [0-3]调度器cbs桶深，单位KB，范围[1KB - 64M]
+ *                    注：cbs=0 表示关闭整形,即不限速
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_etm_shape_se_para_set(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+									 ZXIC_UINT32 pir, ZXIC_UINT32 pbs,
+									 ZXIC_UINT32 db_en, ZXIC_UINT32 cir,
+									 ZXIC_UINT32 cbs);
+
+/***********************************************************/
+/** 写入流/调度器整形参数配置表
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   map_id    整形参数表中模板索引id ETM:0-AFF,FTM:0-17F
+ * @param   cir       整形速率(c/e桶统一)
+ * @param   cbs       桶深
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_para_set(DPP_DEV_T *dev, ZXIC_UINT32 total_para_id,
+								 ZXIC_UINT32 cir, ZXIC_UINT32 cbs);
+
+/***********************************************************/
+/** 读取流/调度器整形参数配置表
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   total_para_id    整形参数表中模板索引id ETM:0-AFF,FTM:0-17F
+ * @param   cir       整形速率(c/e桶统一)
+ * @param   cbs       桶深
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_para_get(DPP_DEV_T *dev, ZXIC_UINT32 total_para_id,
+								 DPP_TM_SHAPE_PARA_TABLE *p_shap_para_tbl);
+
+/***********************************************************/
+/** 配置第0~15个被统计得到令牌个数的端口号
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   port_id   被统计得到令牌个数的端口号
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/3/15           STM模式下使用
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_token_pp_cfg(ZXIC_UINT32 dev_id, ZXIC_UINT32 port_id);
+
+/***********************************************************/
+/** 打印各级及指定被统计的第0~15个授权流得到的授权个数 stm模式下使用
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/06/19
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_ackcnt_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 delay_ms);
+
+/***********************************************************/
+/** 读取端口级整形参数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   port_id   端口号
+ * @param   p_para   整形信息:CIR/CBS/EN
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/04/15
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_pp_para_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+									DPP_TM_SHAPE_PP_PARA_T *p_para);
+
+/***********************************************************/
+/** 配置SA模式下各个版本的授权价值
+ * @param   dev_id   设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   sa_ver_id   版本号(0~7)
+ * @param   sa_credit_value   授权价值
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  szq      @date  2015/03/25
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_sa_credit_value_set(ZXIC_UINT32 dev_id,
+										  ZXIC_UINT32 sa_ver_id,
+										  ZXIC_UINT32 sa_credit_value);
+
+/***********************************************************/
+/** 获取SA模式下各个版本的授权价值
+ * @param   dev_id   设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   sa_ver_id   版本号(0~7)
+ * @param   p_sa_credit_value   授权价值
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  szq      @date  2015/03/25
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_sa_credit_value_get(ZXIC_UINT32 dev_id,
+										  ZXIC_UINT32 sa_ver_id,
+										  ZXIC_UINT32 *p_sa_credit_value);
+
+/***********************************************************/
+/** 配置CRS发送的速率
+ * @param   dev_id   设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   sent_cyc   CRS发送的间隔(单位:时钟周期)
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  szq      @date  2015/03/25
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_crs_sent_rate_set(ZXIC_UINT32 dev_id,
+										ZXIC_UINT32 sent_cyc);
+
+/***********************************************************/
+/** 获取CRS发送的速率
+ * @param   dev_id   设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_sent_cyc   CRS发送的间隔(单位:时钟周期)
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  szq      @date  2015/03/25
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_crs_sent_rate_get(ZXIC_UINT32 dev_id,
+										ZXIC_UINT32 *p_sent_cyc);
+
+/***********************************************************/
+/** 配置CRS过滤使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   en   配置的值，0-不使能过滤，1-使能过滤
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/03/04
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_crs_filter_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en);
+
+/***********************************************************/
+/** 配置多播授权令牌添加个数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   token_add_num
+ *令牌添加时，每次增加的令牌数目，取值范围为1~255，默认为1；禁止配置为0，配置为0时，将不会产生授权。
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/09
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_mul_token_gen_num_set(ZXIC_UINT32 dev_id,
+											ZXIC_UINT32 token_add_num);
+
+/***********************************************************/
+/** 配置多播授权整形桶参数和使能参数
+ * @param   dev_id   设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   q3_lb_control_en   3号队列整形功能开启使能。0：关闭；1：开启。
+ * @param   q012_lb_control_en   0～2号队列整形功能开启使能。0：关闭；1：开启。
+ * @param   q3_lb_max_cnt   3号队列整形桶桶深。
+ * @param   q012_lb_max_cnt   0～2号队列整形桶桶深。
+ * @param   q3_lb_add_rate
+ *3号队列令牌添加速率，时钟周期为单位。不可配置为0，配置为0整形使能时，不能产生队列3授权调度信号。
+ * @param   q012_lb_add_rate
+ *0～2号队列令牌添加速率，以时钟周期单位。不可配置为0，配置为0并整形使能时，不能产生队列0、1、2授权调度信号。
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/09
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_mul_ack_lb_set(ZXIC_UINT32 dev_id,
+									 ZXIC_UINT32 q3_lb_control_en,
+									 ZXIC_UINT32 q012_lb_control_en,
+									 ZXIC_UINT32 q3_lb_max_cnt,
+									 ZXIC_UINT32 q012_lb_max_cnt,
+									 ZXIC_UINT32 q3_lb_add_rate,
+									 ZXIC_UINT32 q012_lb_add_rate);
+
+/***********************************************************/
+/** 配置0,1号队列挂接1或2号MCN漏桶信息
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   dev_id   设备索引编号
+ * @param   mcn_lb_sel   0：0,1号队列挂接1号MCN漏桶 1：0,1号队列挂接2号MCN漏桶
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/09
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_mcn_lb_sel_set(ZXIC_UINT32 dev_id,
+									 ZXIC_UINT32 mcn_lb_sel);
+
+/***********************************************************/
+/** 配置多播队列0~2的授权输出SP、DWRR
+ * @param   dev_id   设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   sp_or_dwrr   SP、DWRR模式选择。0：SP；1：DWRR。
+ * @param   dwrr_w0   0号队列DWRR权重(0~127)
+ * @param   dwrr_w1   1号队列DWRR权重(0~127)
+ * @param   dwrr_w2   2号队列DWRR权重(0~127)
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/09
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_mul_sp_dwrr_set(ZXIC_UINT32 dev_id,
+									  ZXIC_UINT32 sp_or_dwrr,
+									  ZXIC_UINT32 dwrr_w0, ZXIC_UINT32 dwrr_w1,
+									  ZXIC_UINT32 dwrr_w2);
+
+/***********************************************************/
+/** 配置分目的SA整形打开或关闭
+ * @param   dev_id   设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   shap_en   分目的SA整形使能开关 0：表示关闭 1：表示打开
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/09
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_dest_sa_shap_en_set(ZXIC_UINT32 dev_id,
+										  ZXIC_UINT32 shap_en);
+
+/***********************************************************/
+/** 获得轮转扫描使能和扫描速率
+ * @param   dev_id   设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   scan_en   轮转扫描使能。0：关闭，1：开启
+ * @param   scan_rate   轮转扫描速率，配置扫描周期不得少于256个周期
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/10
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_scan_rate_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_scan_en,
+									ZXIC_UINT32 *p_scan_rate);
+
+/***********************************************************/
+/** 配置轮转扫描队列范围
+ * @param   dev_id   设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   first_que  起始队列号
+ * @param   last_que   终止队列号
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/09/10
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_scan_que_range_set(ZXIC_UINT32 dev_id,
+										 ZXIC_UINT32 first_que,
+										 ZXIC_UINT32 last_que);
+
+/***********************************************************/
+/** 获取轮转扫描队列范围
+ * @param   dev_id   设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   first_que  起始队列号
+ * @param   last_que   终止队列号
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/09/10
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_scan_que_range_get(ZXIC_UINT32 dev_id,
+										 ZXIC_UINT32 *first_que,
+										 ZXIC_UINT32 *last_que);
+
+/***********************************************************/
+/** 获取QMU清空状态
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_clr_done_flag   队列是否清空完成
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  szq      @date  2015/05/21
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_qlist_qcfg_clr_done_get(DPP_DEV_T *dev,
+											  ZXIC_UINT32 *p_clr_done_flag);
+
+/***********************************************************/
+/** 配置qsch调度分端口整形速率和使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   shape_en   整形使能
+ * @param   token_add_num   [23:12]:添加令牌数目
+ * @param   token_gap   [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1
+ * @param   token_depth 桶深，单位B,范围[0-0x1EE00]
+ *公式：（600*8*token_num）/(gap+1) = X Mbps
+ *     主频= 600 MHz
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  xuhb   2020-5-15
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_qsch_port_shape_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+										  ZXIC_UINT32 token_add_num,
+										  ZXIC_UINT32 token_gap,
+										  ZXIC_UINT32 token_depth,
+										  ZXIC_UINT32 shape_en);
+
+/***********************************************************/
+/** 配置CMD_SW分端口整形速率和使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   shape_en   整形使能
+ * @param   token_add_num   [23:12]:添加令牌数目
+ * @param   token_gap   [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1
+ * @param   token_depth 桶深，单位B,范围[0-0x1EE00]
+ *公式：（600*8*token_num）/(gap+1) = X Mbps
+ *     主频= 600 MHz
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  whuashan   2020-3-17
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_port_shape_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+									 ZXIC_UINT32 token_add_num,
+									 ZXIC_UINT32 token_gap,
+									 ZXIC_UINT32 token_depth,
+									 ZXIC_UINT32 shape_en);
+
+/***********************************************************/
+/** 获得CMD_SW分端口整形速率和使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_shape_en   整形使能
+ * @param   p_token_add_num   [23:12]:添加令牌数目
+ * @param   p_token_gap   [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1
+ * @param   p_token_depth 桶深，单位B
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  whuashan   2020-3-17
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_port_shape_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+									 ZXIC_UINT32 *p_token_add_num,
+									 ZXIC_UINT32 *p_token_gap,
+									 ZXIC_UINT32 *p_token_depth,
+									 ZXIC_UINT32 *p_shape_en);
+
+/***********************************************************/
+/** 获取CMD_SW分端口整形速率和使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   shape_vlue 整形值，单位Mbps
+ * @param   shape_en   整形使能
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author   zmy   @20151217
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_egress_shape_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 port_id,
+									   ZXIC_UINT32 *shape_value,
+									   ZXIC_UINT32 *shape_en);
+
+/***********************************************************/
+/** 配置需要检测的特定队列号
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   qnum   需要检测统计的特定的队列号
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/18
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_spec_qnum_set(DPP_DEV_T *dev, ZXIC_UINT32 qnum);
+
+/***********************************************************/
+/** 获得特定的队列号
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_qnum   需要检测统计的特定的队列号
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/23
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_spec_qnum_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_qnum);
+
+/***********************************************************/
+/** 配置需要检测的队列组
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   group_num   需要检测统计的特定的队列组。这里按取q的低3bit
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/18
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_spec_group_set(DPP_DEV_T *dev, ZXIC_UINT32 group_num);
+
+/***********************************************************/
+/** 获得需要检测的队列组
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_group_num   需要检测统计的特定的队列组。这里按取q的低3bit
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/23
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_spec_group_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_group_num);
+
+/***********************************************************/
+/** 配置队列授权盈余
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   qnum   配置的队列号
+ * @param   value   授权盈余
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/18
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_crbal_value_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum,
+									  ZXIC_UINT32 value);
+
+/***********************************************************/
+/** 获得队列授权盈余
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   qnum   配置的队列号
+ * @param   p_value   授权盈余
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/23
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_crbal_value_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum,
+									  ZXIC_UINT32 *p_value);
+
+/***********************************************************/
+/** 配置分目的SA整形桶深上、下限参数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   max_value   分目的SA整形桶深上限，必须配置为正值
+ * @param   min_value   分目的SA整形桶深下限，必须配置为负值
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/18
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_dest_sa_shape_para_set(ZXIC_UINT32 dev_id,
+											 ZXIC_SINT32 max_value,
+											 ZXIC_SINT32 min_value);
+
+/***********************************************************/
+/** 获得分目的SA整形桶深上、下限参数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_max_value   分目的SA整形桶深上限，必须配置为正值
+ * @param   p_min_value   分目的SA整形桶深下限，必须配置为负值
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/23
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_dest_sa_shape_para_get(ZXIC_UINT32 dev_id,
+											 ZXIC_UINT32 *p_max_value,
+											 ZXIC_UINT32 *p_min_value);
+
+/***********************************************************/
+/** 获取特定队列发送的crs normal的个数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   注 须先设置统计的特定队列
+ * @param
+ * @return
+ * @remark  无
+ * @see
+ * @author  yjd     @date  2015/07/09
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_spec_q_crs_normal_cnt(ZXIC_UINT32 dev_id,
+											ZXIC_UINT32 *p_que_crs_normal_cnt);
+
+/***********************************************************/
+/** 获取特定队列发送的crs off的个数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   注 须先设置统计的特定队列
+ * @param
+ * @return
+ * @remark  无
+ * @see
+ * @author  yjd     @date  2015/07/09
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_spec_q_crs_off_cnt(ZXIC_UINT32 dev_id,
+										 ZXIC_UINT32 *p_que_crs_off_cnt);
+
+/***********************************************************/
+/** QMU初始化配置场景
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   case_no   四组QMU初始化场景编号为1-4;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8.
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/11/17
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_init_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 case_no);
+
+/***********************************************************/
+/** TMMU TM纯片内模式配置获取
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_imem_en  1纯片内
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wush      @date  2017/10/14
+ ************************************************************/
+DPP_STATUS dpp_tm_tmmu_imem_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_imem_en);
+
+/***********************************************************/
+/** TMMU 强制DDR RDY配置获取
+* @param   dev_id   设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @param   p_ddr_force_rdy  1、如果bit【0】配置为1，则QMU看到的DDR0 RDY一直为1。
+*                           2、bit【0】代表DDR0，bit【7】代表DDR7。
+*                           3、纯片内模式需要配置为8'hff，排除DDR干扰。
+*
+* @return  DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  wush      @date  2017/10/14
+************************************************************/
+DPP_STATUS dpp_tm_tmmu_ddr_force_rdy_get(ZXIC_UINT32 dev_id,
+										 ZXIC_UINT32 *p_ddr_force_rdy);
+
+DPP_STATUS dpp_tm_mr_init(ZXIC_UINT32 dev_id);
+/***********************************************************/
+/** 配置TM模式下初始化代码
+ * @param   dev_id
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_tm_init_info    配置TM模式下初始化信息包括以下
+ *          blk_size  配置qmu block大小
+ *          case_num  四组QMU初始化场景编号为1-4;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8.
+ *          imem_omem;   0:片内外混合; 1:纯片内;2:纯片外
+ *          mode 0:TM 1:SA
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  szq      @date  2015/03/26
+ ************************************************************/
+DPP_STATUS dpp_tm_asic_init(ZXIC_UINT32 dev_id,
+							DPP_TM_ASIC_INIT_INFO_T *p_tm_asic_init_info);
+
+/***********************************************************/
+/** 配置TM模式下初始化代码
+ * @param   dev_id
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_tm_init_info    配置TM模式下初始化信息包括以下
+ *          blk_size  配置qmu block大小
+ *          case_num  四组QMU初始化场景编号为1-4;ddr*bank:1:4x2;2:4x4;3:8x2;4:4x8.
+ *          imem_omem;   0:片内外混合; 1:纯片内;2:纯片外
+ *          mode 0:TM 1:SA
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  szq      @date  2015/03/26
+ ************************************************************/
+DPP_STATUS dpp_tm_asic_init_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 blk_size,
+								 ZXIC_UINT32 case_num, ZXIC_UINT32 imem_omem,
+								 ZXIC_UINT32 mode);
+
+/****************************************************************************
+ * 函数名称: dpp_tm_avg_que_len_get
+ * 功能描述: 各级平均队列深度获取
+ * 输入参数: dev_id: 设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ *           cgavd_level: 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ *           que_id: 本级别层次内的队列编号。
+ * 输出参数: p_avg_len: 平均队列深度，单位为BLOCK。
+ * 返 回 值: DPP_OK-成功，DPP_ERR-失败
+ * 其它说明:
+ * author  cy      @date  2015/06/29
+ *****************************************************************************/
+DPP_STATUS dpp_tm_avg_que_len_get(ZXIC_UINT32 dev_id,
+								  DPP_TM_CGAVD_LEVEL_E cgavd_level,
+								  ZXIC_UINT32 que_id, ZXIC_UINT32 *p_avg_len);
+
+/***********************************************************/
+/** 获取配置CPU设置的报文长度是否参与计算丢弃概率的使能
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flag   忽略乘法里的当前包长和最大包长比标志位:1为忽略
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy     @date  2015/11/9
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_wred_pke_len_calc_sign_get(ZXIC_UINT32 dev_id,
+												   ZXIC_UINT32 *p_flag);
+
+/***********************************************************/
+/**  配置配置cgavd模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   mode   0:block mode 1:byte mode
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/07/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_cfg_mode_set(DPP_DEV_T *dev, ZXIC_UINT32 mode);
+
+/***********************************************************/
+/**  配置配置cgavd模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_mode   0:block mode 1:byte mode
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/07/29
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_cfg_mode_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_mode);
+
+/***********************************************************/
+/** 配置TD拥塞避免模式下的丢弃门限值
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   id   队列号或端口号，系统级时，id参数无效
+ * @param   byte_block_th   配置的丢弃门限值，ZXIC_UINT8/BLOCK单位写入寄存器
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/07/29
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_td_byte_block_th_set(DPP_DEV_T *dev,
+											 DPP_TM_CGAVD_LEVEL_E level,
+											 ZXIC_UINT32 id,
+											 ZXIC_UINT32 byte_block_th);
+
+/***********************************************************/
+/** 读取TD拥塞避免模式下的丢弃门限值字节模式
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   id   队列号或端口号，系统级时，id参数无效
+ * @param   p_byte_block_th   配置的丢弃门限值ZXIC_UINT8/BLOCK单位
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/07/29
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_td_byte_block_th_get(DPP_DEV_T *dev,
+											 DPP_TM_CGAVD_LEVEL_E level,
+											 ZXIC_UINT32 id,
+											 ZXIC_UINT32 *p_byte_block_th);
+
+/***********************************************************/
+/**  配置通用门限block模式
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   byte_block_uni_th   通用门限值block/byte单位
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/08/01
+ ************************************************************/
+DPP_STATUS
+dpp_tm_cgavd_uniform_byte_block_th_set(DPP_DEV_T *dev,
+									   ZXIC_UINT32 byte_block_uni_th);
+
+/***********************************************************/
+/**  读取通用门限
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_byte_block_uni_th   通用门限值block/byte单位
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/08/01
+ ************************************************************/
+DPP_STATUS
+dpp_tm_cgavd_uniform_byte_block_th_get(DPP_DEV_T *dev,
+									   ZXIC_UINT32 *p_byte_block_uni_th);
+
+/***********TM CPU软复位接口 Begin*************/
+/***********************************************************/
+/**  设置TM的全局变量，shape_para只保存profile被使用的数量，整形相关参数从寄存器中重新读取
+ * @param   dev_id
+ * @param   size         data_buff的长度
+ * @param   p_data_buff  需要恢复的内容
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XXX      @date  2018/06/25
+ ************************************************************/
+DPP_STATUS dpp_tm_glb_mgr_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 size,
+							  ZXIC_UINT8 *p_data_buff);
+
+/***********************************************************/
+/** 获取TM的全局变量，shape_para只保存profile被使用的数量，整形相关参数从寄存器中重新读取
+ * @param   dev_id
+ * @param   p_flag           上层释放data_buff的标志，1:需要上层free,0:不需要上层free
+ * @param   p_size           data_buff的长度
+ * @param   pp_data_buff     二级指针(指向函数内部malloc空间的地址)
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XXX      @date  2018/06/25
+ ************************************************************/
+DPP_STATUS dpp_tm_glb_mgr_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_flag,
+							  ZXIC_UINT32 *p_size, ZXIC_UINT8 **pp_data_buff);
+
+/***********************************************************/
+/** 获取TM的全局变量，shape_para只保存profile被使用的数量，整形相关参数从寄存器中重新读取
+ * @param   dev_id
+ * @param   p_size           data_buff的长度
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XXX      @date  2018/06/25
+ ************************************************************/
+DPP_STATUS dpp_tm_glb_size_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_size);
+
+/***********************************************************/
+/** 配置tm授权价值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   credit_value   授权价值，默认值是0x5feByte
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  xuhb      @date  2020/08/13
+ ************************************************************/
+DPP_STATUS dpp_tm_credit_value_set(ZXIC_UINT32 dev_id,
+								   ZXIC_UINT32 credit_value);
+
+/***********************************************************/
+/** 获取全局数组中用户实际配置的整形值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flow_id   流队列号 ETM:0-9215,FTM:0-2047
+ * @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
+ * @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
+ *                    注：cbs=0 表示关闭整形,即不限速
+ * @param   mode_e    整形模式，0-获取c桶参数，1-获取对应e桶参数
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark
+ * @see
+ * @author  xuhb      @date  2019/06/10
+ ************************************************************/
+DPP_STATUS
+dpp_tm_shape_flow_para_array_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+								 ZXIC_UINT32 mode,
+								 DPP_TM_SHAPE_PARA_TABLE *p_flow_para_tbl);
+
+#endif
+/* 必须有个空行，否则可能编不过 */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_axi_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_axi_reg.h
index 12bb803bb3d0b4fd04d6ca5d7830fd88712a0756..e3d25e5c98e6c388d6db60594c37a6c3f62f774d 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_axi_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_axi_reg.h
@@ -3,48 +3,40 @@
 #define _DPP_AXI_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_axi_axi_conv_cfg_epid_v_func_num_t
-{
-    ZXIC_UINT32 user_en;
-    ZXIC_UINT32 cfg_epid;
-    ZXIC_UINT32 cfg_vfunc_num;
-    ZXIC_UINT32 cfg_func_num;
-    ZXIC_UINT32 cfg_vfunc_active;
-}DPP_AXI_AXI_CONV_CFG_EPID_V_FUNC_NUM_T;
-
-typedef struct dpp_axi_axi_conv_info_axim_rw_hsk_cnt_t
-{
-    ZXIC_UINT32 axim_rd_handshake_cnt;
-    ZXIC_UINT32 axim_wr_handshake_cnt;
-}DPP_AXI_AXI_CONV_INFO_AXIM_RW_HSK_CNT_T;
-
-typedef struct dpp_axi_axi_conv_info_axim_last_wr_id_t
-{
-    ZXIC_UINT32 axim_rd_id;
-    ZXIC_UINT32 axim_wr_id;
-}DPP_AXI_AXI_CONV_INFO_AXIM_LAST_WR_ID_T;
-
-typedef struct dpp_axi_axi_conv_info_axim_last_wr_addr_h_t
-{
-    ZXIC_UINT32 aximlastwraddrhigh;
-}DPP_AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_H_T;
-
-typedef struct dpp_axi_axi_conv_info_axim_last_wr_addr_l_t
-{
-    ZXIC_UINT32 aximlastrdaddrlow;
-}DPP_AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_L_T;
-
-typedef struct dpp_axi_axi_conv_cfg_debug_info_clr_en_t
-{
-    ZXIC_UINT32 cfg_global_clr_en;
-}DPP_AXI_AXI_CONV_CFG_DEBUG_INFO_CLR_EN_T;
+typedef struct dpp_axi_axi_conv_cfg_epid_v_func_num_t {
+	ZXIC_UINT32 user_en;
+	ZXIC_UINT32 cfg_epid;
+	ZXIC_UINT32 cfg_vfunc_num;
+	ZXIC_UINT32 cfg_func_num;
+	ZXIC_UINT32 cfg_vfunc_active;
+} DPP_AXI_AXI_CONV_CFG_EPID_V_FUNC_NUM_T;
 
+typedef struct dpp_axi_axi_conv_info_axim_rw_hsk_cnt_t {
+	ZXIC_UINT32 axim_rd_handshake_cnt;
+	ZXIC_UINT32 axim_wr_handshake_cnt;
+} DPP_AXI_AXI_CONV_INFO_AXIM_RW_HSK_CNT_T;
+
+typedef struct dpp_axi_axi_conv_info_axim_last_wr_id_t {
+	ZXIC_UINT32 axim_rd_id;
+	ZXIC_UINT32 axim_wr_id;
+} DPP_AXI_AXI_CONV_INFO_AXIM_LAST_WR_ID_T;
+
+typedef struct dpp_axi_axi_conv_info_axim_last_wr_addr_h_t {
+	ZXIC_UINT32 aximlastwraddrhigh;
+} DPP_AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_H_T;
+
+typedef struct dpp_axi_axi_conv_info_axim_last_wr_addr_l_t {
+	ZXIC_UINT32 aximlastrdaddrlow;
+} DPP_AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_L_T;
+
+typedef struct dpp_axi_axi_conv_cfg_debug_info_clr_en_t {
+	ZXIC_UINT32 cfg_global_clr_en;
+} DPP_AXI_AXI_CONV_CFG_DEBUG_INFO_CLR_EN_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_cfg_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_cfg_reg.h
index fa2fd7f69111c16fbf0df2cac5c952ef2e52d41c..3589db9123eab3349921884c130633cecedbe413 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_cfg_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_cfg_reg.h
@@ -3,1246 +3,998 @@
 #define _DPP_CFG_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_cfg_pcie_int_repeat_t
-{
-    ZXIC_UINT32 int_repeat;
-}DPP_CFG_PCIE_INT_REPEAT_T;
-
-typedef struct dpp_cfg_dma_dma_up_size_t
-{
-    ZXIC_UINT32 dma_up_size;
-}DPP_CFG_DMA_DMA_UP_SIZE_T;
-
-typedef struct dpp_cfg_csr_soc_wr_time_out_thresh_t
-{
-    ZXIC_UINT32 soc_wr_time_out_thresh;
-}DPP_CFG_CSR_SOC_WR_TIME_OUT_THRESH_T;
-
-typedef struct dpp_cfg_pcie_pcie_ddr_switch_t
-{
-    ZXIC_UINT32 pcie_ddr_switch;
-}DPP_CFG_PCIE_PCIE_DDR_SWITCH_T;
-
-typedef struct dpp_cfg_pcie_user0_int_en_t
-{
-    ZXIC_UINT32 user_int_en;
-}DPP_CFG_PCIE_USER0_INT_EN_T;
-
-typedef struct dpp_cfg_pcie_user0_int_mask_t
-{
-    ZXIC_UINT32 user_int_mask;
-}DPP_CFG_PCIE_USER0_INT_MASK_T;
-
-typedef struct dpp_cfg_pcie_user0_int_status_t
-{
-    ZXIC_UINT32 user_int_status;
-}DPP_CFG_PCIE_USER0_INT_STATUS_T;
-
-typedef struct dpp_cfg_pcie_user1_int_en_t
-{
-    ZXIC_UINT32 user_int_en;
-}DPP_CFG_PCIE_USER1_INT_EN_T;
-
-typedef struct dpp_cfg_pcie_user1_int_mask_t
-{
-    ZXIC_UINT32 user_int_mask;
-}DPP_CFG_PCIE_USER1_INT_MASK_T;
-
-typedef struct dpp_cfg_pcie_user1_int_status_t
-{
-    ZXIC_UINT32 user_int_status;
-}DPP_CFG_PCIE_USER1_INT_STATUS_T;
-
-typedef struct dpp_cfg_pcie_user2_int_en_t
-{
-    ZXIC_UINT32 user_int_en;
-}DPP_CFG_PCIE_USER2_INT_EN_T;
-
-typedef struct dpp_cfg_pcie_user2_int_mask_t
-{
-    ZXIC_UINT32 user_int_mask;
-}DPP_CFG_PCIE_USER2_INT_MASK_T;
-
-typedef struct dpp_cfg_pcie_user2_int_status_t
-{
-    ZXIC_UINT32 user_int_status;
-}DPP_CFG_PCIE_USER2_INT_STATUS_T;
-
-typedef struct dpp_cfg_pcie_ecc_1b_int_en_t
-{
-    ZXIC_UINT32 ecc_1b_int_en;
-}DPP_CFG_PCIE_ECC_1B_INT_EN_T;
-
-typedef struct dpp_cfg_pcie_ecc_1b_int_mask_t
-{
-    ZXIC_UINT32 ecc_1b_int_mask;
-}DPP_CFG_PCIE_ECC_1B_INT_MASK_T;
-
-typedef struct dpp_cfg_pcie_ecc_1b_int_status_t
-{
-    ZXIC_UINT32 ecc_1b_int_status;
-}DPP_CFG_PCIE_ECC_1B_INT_STATUS_T;
-
-typedef struct dpp_cfg_pcie_ecc_2b_int_en_t
-{
-    ZXIC_UINT32 ecc_2b_int_en;
-}DPP_CFG_PCIE_ECC_2B_INT_EN_T;
-
-typedef struct dpp_cfg_pcie_ecc_2b_int_mask_t
-{
-    ZXIC_UINT32 ecc_2b_int_mask;
-}DPP_CFG_PCIE_ECC_2B_INT_MASK_T;
-
-typedef struct dpp_cfg_pcie_ecc_2b_int_status_t
-{
-    ZXIC_UINT32 ecc_2b_int_status;
-}DPP_CFG_PCIE_ECC_2B_INT_STATUS_T;
-
-typedef struct dpp_cfg_pcie_cfg_int_status_t
-{
-    ZXIC_UINT32 cfg_int_status;
-}DPP_CFG_PCIE_CFG_INT_STATUS_T;
-
-typedef struct dpp_cfg_pcie_i_core_to_cntl_t
-{
-    ZXIC_UINT32 i_core_to_cntl;
-}DPP_CFG_PCIE_I_CORE_TO_CNTL_T;
-
-typedef struct dpp_cfg_pcie_test_in_low_t
-{
-    ZXIC_UINT32 test_in_low;
-}DPP_CFG_PCIE_TEST_IN_LOW_T;
-
-typedef struct dpp_cfg_pcie_test_in_high_t
-{
-    ZXIC_UINT32 test_in_high;
-}DPP_CFG_PCIE_TEST_IN_HIGH_T;
-
-typedef struct dpp_cfg_pcie_local_interrupt_out_t
-{
-    ZXIC_UINT32 local_interrupt_out;
-}DPP_CFG_PCIE_LOCAL_INTERRUPT_OUT_T;
-
-typedef struct dpp_cfg_pcie_pl_ltssm_t
-{
-    ZXIC_UINT32 pl_ltssm;
-}DPP_CFG_PCIE_PL_LTSSM_T;
-
-typedef struct dpp_cfg_pcie_test_out0_t
-{
-    ZXIC_UINT32 test_out0;
-}DPP_CFG_PCIE_TEST_OUT0_T;
-
-typedef struct dpp_cfg_pcie_test_out1_t
-{
-    ZXIC_UINT32 test_out1;
-}DPP_CFG_PCIE_TEST_OUT1_T;
-
-typedef struct dpp_cfg_pcie_test_out2_t
-{
-    ZXIC_UINT32 test_out2;
-}DPP_CFG_PCIE_TEST_OUT2_T;
-
-typedef struct dpp_cfg_pcie_test_out3_t
-{
-    ZXIC_UINT32 test_out3;
-}DPP_CFG_PCIE_TEST_OUT3_T;
-
-typedef struct dpp_cfg_pcie_test_out4_t
-{
-    ZXIC_UINT32 test_out4;
-}DPP_CFG_PCIE_TEST_OUT4_T;
-
-typedef struct dpp_cfg_pcie_test_out5_t
-{
-    ZXIC_UINT32 test_out5;
-}DPP_CFG_PCIE_TEST_OUT5_T;
-
-typedef struct dpp_cfg_pcie_test_out6_t
-{
-    ZXIC_UINT32 test_out6;
-}DPP_CFG_PCIE_TEST_OUT6_T;
-
-typedef struct dpp_cfg_pcie_test_out7_t
-{
-    ZXIC_UINT32 test_out7;
-}DPP_CFG_PCIE_TEST_OUT7_T;
-
-typedef struct dpp_cfg_pcie_sync_o_core_status_t
-{
-    ZXIC_UINT32 sync_o_core_status;
-}DPP_CFG_PCIE_SYNC_O_CORE_STATUS_T;
-
-typedef struct dpp_cfg_pcie_sync_o_alert_dbe_t
-{
-    ZXIC_UINT32 sync_o_alert_dbe;
-}DPP_CFG_PCIE_SYNC_O_ALERT_DBE_T;
-
-typedef struct dpp_cfg_pcie_sync_o_alert_sbe_t
-{
-    ZXIC_UINT32 sync_o_alert_sbe;
-}DPP_CFG_PCIE_SYNC_O_ALERT_SBE_T;
-
-typedef struct dpp_cfg_pcie_sync_o_link_loopback_en_t
-{
-    ZXIC_UINT32 sync_o_link_loopback_en;
-}DPP_CFG_PCIE_SYNC_O_LINK_LOOPBACK_EN_T;
-
-typedef struct dpp_cfg_pcie_sync_o_local_fs_lf_valid_t
-{
-    ZXIC_UINT32 sync_o_local_fs_lf_valid;
-}DPP_CFG_PCIE_SYNC_O_LOCAL_FS_LF_VALID_T;
-
-typedef struct dpp_cfg_pcie_sync_o_rx_idle_detect_t
-{
-    ZXIC_UINT32 sync_o_rx_idle_detect;
-}DPP_CFG_PCIE_SYNC_O_RX_IDLE_DETECT_T;
-
-typedef struct dpp_cfg_pcie_sync_o_rx_rdy_t
-{
-    ZXIC_UINT32 sync_o_rx_rdy;
-}DPP_CFG_PCIE_SYNC_O_RX_RDY_T;
-
-typedef struct dpp_cfg_pcie_sync_o_tx_rdy_t
-{
-    ZXIC_UINT32 sync_o_tx_rdy;
-}DPP_CFG_PCIE_SYNC_O_TX_RDY_T;
-
-typedef struct dpp_cfg_pcie_pcie_link_up_cnt_t
-{
-    ZXIC_UINT32 pcie_link_up_cnt;
-}DPP_CFG_PCIE_PCIE_LINK_UP_CNT_T;
-
-typedef struct dpp_cfg_pcie_test_out_pcie0_t
-{
-    ZXIC_UINT32 test_out_pcie0;
-}DPP_CFG_PCIE_TEST_OUT_PCIE0_T;
-
-typedef struct dpp_cfg_pcie_test_out_pcie1_t
-{
-    ZXIC_UINT32 test_out_pcie1;
-}DPP_CFG_PCIE_TEST_OUT_PCIE1_T;
-
-typedef struct dpp_cfg_pcie_test_out_pcie2_t
-{
-    ZXIC_UINT32 test_out_pcie2;
-}DPP_CFG_PCIE_TEST_OUT_PCIE2_T;
-
-typedef struct dpp_cfg_pcie_test_out_pcie3_t
-{
-    ZXIC_UINT32 test_out_pcie3;
-}DPP_CFG_PCIE_TEST_OUT_PCIE3_T;
-
-typedef struct dpp_cfg_pcie_test_out_pcie4_t
-{
-    ZXIC_UINT32 test_out_pcie4;
-}DPP_CFG_PCIE_TEST_OUT_PCIE4_T;
-
-typedef struct dpp_cfg_pcie_test_out_pcie5_t
-{
-    ZXIC_UINT32 test_out_pcie5;
-}DPP_CFG_PCIE_TEST_OUT_PCIE5_T;
-
-typedef struct dpp_cfg_pcie_test_out_pcie6_t
-{
-    ZXIC_UINT32 test_out_pcie6;
-}DPP_CFG_PCIE_TEST_OUT_PCIE6_T;
-
-typedef struct dpp_cfg_pcie_test_out_pcie7_t
-{
-    ZXIC_UINT32 test_out_pcie7;
-}DPP_CFG_PCIE_TEST_OUT_PCIE7_T;
-
-typedef struct dpp_cfg_pcie_test_out_pcie8_t
-{
-    ZXIC_UINT32 test_out_pcie8;
-}DPP_CFG_PCIE_TEST_OUT_PCIE8_T;
-
-typedef struct dpp_cfg_pcie_test_out_pcie9_t
-{
-    ZXIC_UINT32 test_out_pcie9;
-}DPP_CFG_PCIE_TEST_OUT_PCIE9_T;
-
-typedef struct dpp_cfg_pcie_test_out_pcie10_t
-{
-    ZXIC_UINT32 test_out_pcie10;
-}DPP_CFG_PCIE_TEST_OUT_PCIE10_T;
-
-typedef struct dpp_cfg_pcie_test_out_pcie11_t
-{
-    ZXIC_UINT32 test_out_pcie11;
-}DPP_CFG_PCIE_TEST_OUT_PCIE11_T;
-
-typedef struct dpp_cfg_pcie_test_out_pcie12_t
-{
-    ZXIC_UINT32 test_out_pcie12;
-}DPP_CFG_PCIE_TEST_OUT_PCIE12_T;
-
-typedef struct dpp_cfg_pcie_test_out_pcie13_t
-{
-    ZXIC_UINT32 test_out_pcie13;
-}DPP_CFG_PCIE_TEST_OUT_PCIE13_T;
-
-typedef struct dpp_cfg_pcie_test_out_pcie14_t
-{
-    ZXIC_UINT32 test_out_pcie14;
-}DPP_CFG_PCIE_TEST_OUT_PCIE14_T;
-
-typedef struct dpp_cfg_pcie_test_out_pcie15_t
-{
-    ZXIC_UINT32 test_out_pcie15;
-}DPP_CFG_PCIE_TEST_OUT_PCIE15_T;
-
-typedef struct dpp_cfg_pcie_int_repeat_en_t
-{
-    ZXIC_UINT32 int_repeat_en;
-}DPP_CFG_PCIE_INT_REPEAT_EN_T;
-
-typedef struct dpp_cfg_pcie_dbg_awid_axi_mst_t
-{
-    ZXIC_UINT32 dbg_awid_axi_mst;
-}DPP_CFG_PCIE_DBG_AWID_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_awaddr_axi_mst0_t
-{
-    ZXIC_UINT32 dbg_awaddr_axi_mst0;
-}DPP_CFG_PCIE_DBG_AWADDR_AXI_MST0_T;
-
-typedef struct dpp_cfg_pcie_dbg_awaddr_axi_mst1_t
-{
-    ZXIC_UINT32 dbg_awaddr_axi_mst1;
-}DPP_CFG_PCIE_DBG_AWADDR_AXI_MST1_T;
-
-typedef struct dpp_cfg_pcie_dbg_awlen_axi_mst_t
-{
-    ZXIC_UINT32 dbg_awlen_axi_mst;
-}DPP_CFG_PCIE_DBG_AWLEN_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_awsize_axi_mst_t
-{
-    ZXIC_UINT32 dbg_awid_axi_mst;
-}DPP_CFG_PCIE_DBG_AWSIZE_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_awburst_axi_mst_t
-{
-    ZXIC_UINT32 dbg_awburst_axi_mst;
-}DPP_CFG_PCIE_DBG_AWBURST_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_awlock_axi_mst_t
-{
-    ZXIC_UINT32 dbg_awlock_axi_mst;
-}DPP_CFG_PCIE_DBG_AWLOCK_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_awcache_axi_mst_t
-{
-    ZXIC_UINT32 dbg_awcache_axi_mst;
-}DPP_CFG_PCIE_DBG_AWCACHE_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_awprot_axi_mst_t
-{
-    ZXIC_UINT32 dbg_awprot_axi_mst;
-}DPP_CFG_PCIE_DBG_AWPROT_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_wid_axi_mst_t
-{
-    ZXIC_UINT32 dbg_wid_axi_mst;
-}DPP_CFG_PCIE_DBG_WID_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_wdata_axi_mst0_t
-{
-    ZXIC_UINT32 dbg_wdata_axi_mst0;
-}DPP_CFG_PCIE_DBG_WDATA_AXI_MST0_T;
-
-typedef struct dpp_cfg_pcie_dbg_wdata_axi_mst1_t
-{
-    ZXIC_UINT32 dbg_wdata_axi_mst1;
-}DPP_CFG_PCIE_DBG_WDATA_AXI_MST1_T;
-
-typedef struct dpp_cfg_pcie_dbg_wdata_axi_mst2_t
-{
-    ZXIC_UINT32 dbg_wdata_axi_mst2;
-}DPP_CFG_PCIE_DBG_WDATA_AXI_MST2_T;
-
-typedef struct dpp_cfg_pcie_dbg_wdata_axi_mst3_t
-{
-    ZXIC_UINT32 dbg_wdata_axi_mst3;
-}DPP_CFG_PCIE_DBG_WDATA_AXI_MST3_T;
-
-typedef struct dpp_cfg_pcie_dbg_wstrb_axi_mst_t
-{
-    ZXIC_UINT32 dbg_wstrb_axi_mst;
-}DPP_CFG_PCIE_DBG_WSTRB_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_wlast_axi_mst_t
-{
-    ZXIC_UINT32 dbg_wlast_axi_mst;
-}DPP_CFG_PCIE_DBG_WLAST_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_arid_axi_mst_t
-{
-    ZXIC_UINT32 dbg_arid_axi_mst;
-}DPP_CFG_PCIE_DBG_ARID_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_araddr_axi_mst0_t
-{
-    ZXIC_UINT32 dbg_araddr_axi_mst0;
-}DPP_CFG_PCIE_DBG_ARADDR_AXI_MST0_T;
-
-typedef struct dpp_cfg_pcie_dbg_araddr_axi_mst1_t
-{
-    ZXIC_UINT32 dbg_araddr_axi_mst1;
-}DPP_CFG_PCIE_DBG_ARADDR_AXI_MST1_T;
-
-typedef struct dpp_cfg_pcie_dbg_arlen_axi_mst_t
-{
-    ZXIC_UINT32 dbg_arlen_axi_mst;
-}DPP_CFG_PCIE_DBG_ARLEN_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_arsize_axi_mst_t
-{
-    ZXIC_UINT32 dbg_arsize_axi_mst;
-}DPP_CFG_PCIE_DBG_ARSIZE_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_arburst_axi_mst_t
-{
-    ZXIC_UINT32 dbg_arburst_axi_mst;
-}DPP_CFG_PCIE_DBG_ARBURST_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_arlock_axi_mst_t
-{
-    ZXIC_UINT32 dbg_arlock_axi_mst;
-}DPP_CFG_PCIE_DBG_ARLOCK_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_arcache_axi_mst_t
-{
-    ZXIC_UINT32 dbg_arcache_axi_mst;
-}DPP_CFG_PCIE_DBG_ARCACHE_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_arprot_axi_mst_t
-{
-    ZXIC_UINT32 dbg_arprot_axi_mst;
-}DPP_CFG_PCIE_DBG_ARPROT_AXI_MST_T;
-
-typedef struct dpp_cfg_pcie_dbg_rdata_axi_mst0_t
-{
-    ZXIC_UINT32 dbg_rdata_axi_mst0;
-}DPP_CFG_PCIE_DBG_RDATA_AXI_MST0_T;
-
-typedef struct dpp_cfg_pcie_dbg_rdata_axi_mst1_t
-{
-    ZXIC_UINT32 dbg_rdata_axi_mst1;
-}DPP_CFG_PCIE_DBG_RDATA_AXI_MST1_T;
-
-typedef struct dpp_cfg_pcie_dbg_rdata_axi_mst2_t
-{
-    ZXIC_UINT32 dbg_rdata_axi_mst2;
-}DPP_CFG_PCIE_DBG_RDATA_AXI_MST2_T;
-
-typedef struct dpp_cfg_pcie_dbg_rdata_axi_mst3_t
-{
-    ZXIC_UINT32 dbg_rdata_axi_mst3;
-}DPP_CFG_PCIE_DBG_RDATA_AXI_MST3_T;
-
-typedef struct dpp_cfg_pcie_axi_mst_state_t
-{
-    ZXIC_UINT32 axi_mst_state;
-}DPP_CFG_PCIE_AXI_MST_STATE_T;
-
-typedef struct dpp_cfg_pcie_axi_cfg_state_t
-{
-    ZXIC_UINT32 axi_cfg_state;
-}DPP_CFG_PCIE_AXI_CFG_STATE_T;
-
-typedef struct dpp_cfg_pcie_axi_slv_rd_state_t
-{
-    ZXIC_UINT32 axi_slv_rd_state;
-}DPP_CFG_PCIE_AXI_SLV_RD_STATE_T;
-
-typedef struct dpp_cfg_pcie_axi_slv_wr_state_t
-{
-    ZXIC_UINT32 axi_slv_wr_state;
-}DPP_CFG_PCIE_AXI_SLV_WR_STATE_T;
-
-typedef struct dpp_cfg_pcie_axim_delay_en_t
-{
-    ZXIC_UINT32 axim_delay_en;
-}DPP_CFG_PCIE_AXIM_DELAY_EN_T;
-
-typedef struct dpp_cfg_pcie_axim_delay_t
-{
-    ZXIC_UINT32 axim_delay;
-}DPP_CFG_PCIE_AXIM_DELAY_T;
-
-typedef struct dpp_cfg_pcie_axim_speed_wr_t
-{
-    ZXIC_UINT32 axim_speed_wr;
-}DPP_CFG_PCIE_AXIM_SPEED_WR_T;
-
-typedef struct dpp_cfg_pcie_axim_speed_rd_t
-{
-    ZXIC_UINT32 axim_speed_rd;
-}DPP_CFG_PCIE_AXIM_SPEED_RD_T;
-
-typedef struct dpp_cfg_pcie_dbg_awaddr_axi_slv0_t
-{
-    ZXIC_UINT32 dbg_awaddr_axi_slv0;
-}DPP_CFG_PCIE_DBG_AWADDR_AXI_SLV0_T;
-
-typedef struct dpp_cfg_pcie_dbg_awaddr_axi_slv1_t
-{
-    ZXIC_UINT32 dbg_awaddr_axi_slv1;
-}DPP_CFG_PCIE_DBG_AWADDR_AXI_SLV1_T;
-
-typedef struct dpp_cfg_pcie_dbg0_wdata_axi_slv0_t
-{
-    ZXIC_UINT32 dbg0_wdata_axi_slv0;
-}DPP_CFG_PCIE_DBG0_WDATA_AXI_SLV0_T;
-
-typedef struct dpp_cfg_pcie_dbg0_wdata_axi_slv1_t
-{
-    ZXIC_UINT32 dbg0_wdata_axi_slv1;
-}DPP_CFG_PCIE_DBG0_WDATA_AXI_SLV1_T;
-
-typedef struct dpp_cfg_pcie_dbg0_wdata_axi_slv2_t
-{
-    ZXIC_UINT32 dbg0_wdata_axi_slv2;
-}DPP_CFG_PCIE_DBG0_WDATA_AXI_SLV2_T;
-
-typedef struct dpp_cfg_pcie_dbg0_wdata_axi_slv3_t
-{
-    ZXIC_UINT32 dbg0_wdata_axi_slv3;
-}DPP_CFG_PCIE_DBG0_WDATA_AXI_SLV3_T;
-
-typedef struct dpp_cfg_pcie_dbg1_wdata_axi_slv0_t
-{
-    ZXIC_UINT32 dbg1_wdata_axi_slv0;
-}DPP_CFG_PCIE_DBG1_WDATA_AXI_SLV0_T;
-
-typedef struct dpp_cfg_pcie_dbg1_wdata_axi_slv1_t
-{
-    ZXIC_UINT32 dbg1_wdata_axi_slv1;
-}DPP_CFG_PCIE_DBG1_WDATA_AXI_SLV1_T;
-
-typedef struct dpp_cfg_pcie_dbg1_wdata_axi_slv2_t
-{
-    ZXIC_UINT32 dbg1_wdata_axi_slv2;
-}DPP_CFG_PCIE_DBG1_WDATA_AXI_SLV2_T;
-
-typedef struct dpp_cfg_pcie_dbg1_wdata_axi_slv3_t
-{
-    ZXIC_UINT32 dbg1_wdata_axi_slv3;
-}DPP_CFG_PCIE_DBG1_WDATA_AXI_SLV3_T;
-
-typedef struct dpp_cfg_pcie_dbg2_wdata_axi_slv0_t
-{
-    ZXIC_UINT32 dbg2_wdata_axi_slv0;
-}DPP_CFG_PCIE_DBG2_WDATA_AXI_SLV0_T;
-
-typedef struct dpp_cfg_pcie_dbg2_wdata_axi_slv1_t
-{
-    ZXIC_UINT32 dbg2_wdata_axi_slv1;
-}DPP_CFG_PCIE_DBG2_WDATA_AXI_SLV1_T;
-
-typedef struct dpp_cfg_pcie_dbg2_wdata_axi_slv2_t
-{
-    ZXIC_UINT32 dbg2_wdata_axi_slv2;
-}DPP_CFG_PCIE_DBG2_WDATA_AXI_SLV2_T;
-
-typedef struct dpp_cfg_pcie_dbg2_wdata_axi_slv3_t
-{
-    ZXIC_UINT32 dbg2_wdata_axi_slv3;
-}DPP_CFG_PCIE_DBG2_WDATA_AXI_SLV3_T;
-
-typedef struct dpp_cfg_pcie_dbg3_wdata_axi_slv0_t
-{
-    ZXIC_UINT32 dbg3_wdata_axi_slv0;
-}DPP_CFG_PCIE_DBG3_WDATA_AXI_SLV0_T;
-
-typedef struct dpp_cfg_pcie_dbg3_wdata_axi_slv1_t
-{
-    ZXIC_UINT32 dbg3_wdata_axi_slv1;
-}DPP_CFG_PCIE_DBG3_WDATA_AXI_SLV1_T;
-
-typedef struct dpp_cfg_pcie_dbg3_wdata_axi_slv2_t
-{
-    ZXIC_UINT32 dbg3_wdata_axi_slv2;
-}DPP_CFG_PCIE_DBG3_WDATA_AXI_SLV2_T;
-
-typedef struct dpp_cfg_pcie_dbg3_wdata_axi_slv3_t
-{
-    ZXIC_UINT32 dbg3_wdata_axi_slv3;
-}DPP_CFG_PCIE_DBG3_WDATA_AXI_SLV3_T;
-
-typedef struct dpp_cfg_pcie_dbg4_wdata_axi_slv0_t
-{
-    ZXIC_UINT32 dbg4_wdata_axi_slv0;
-}DPP_CFG_PCIE_DBG4_WDATA_AXI_SLV0_T;
-
-typedef struct dpp_cfg_pcie_dbg4_wdata_axi_slv1_t
-{
-    ZXIC_UINT32 dbg4_wdata_axi_slv1;
-}DPP_CFG_PCIE_DBG4_WDATA_AXI_SLV1_T;
-
-typedef struct dpp_cfg_pcie_dbg4_wdata_axi_slv2_t
-{
-    ZXIC_UINT32 dbg4_wdata_axi_slv2;
-}DPP_CFG_PCIE_DBG4_WDATA_AXI_SLV2_T;
-
-typedef struct dpp_cfg_pcie_dbg4_wdata_axi_slv3_t
-{
-    ZXIC_UINT32 dbg4_wdata_axi_slv3;
-}DPP_CFG_PCIE_DBG4_WDATA_AXI_SLV3_T;
-
-typedef struct dpp_cfg_pcie_dbg5_wdata_axi_slv0_t
-{
-    ZXIC_UINT32 dbg5_wdata_axi_slv0;
-}DPP_CFG_PCIE_DBG5_WDATA_AXI_SLV0_T;
-
-typedef struct dpp_cfg_pcie_dbg5_wdata_axi_slv1_t
-{
-    ZXIC_UINT32 dbg5_wdata_axi_slv1;
-}DPP_CFG_PCIE_DBG5_WDATA_AXI_SLV1_T;
-
-typedef struct dpp_cfg_pcie_dbg5_wdata_axi_slv2_t
-{
-    ZXIC_UINT32 dbg5_wdata_axi_slv2;
-}DPP_CFG_PCIE_DBG5_WDATA_AXI_SLV2_T;
-
-typedef struct dpp_cfg_pcie_dbg5_wdata_axi_slv3_t
-{
-    ZXIC_UINT32 dbg5_wdata_axi_slv3;
-}DPP_CFG_PCIE_DBG5_WDATA_AXI_SLV3_T;
-
-typedef struct dpp_cfg_pcie_dbg6_wdata_axi_slv0_t
-{
-    ZXIC_UINT32 dbg6_wdata_axi_slv0;
-}DPP_CFG_PCIE_DBG6_WDATA_AXI_SLV0_T;
-
-typedef struct dpp_cfg_pcie_dbg6_wdata_axi_slv1_t
-{
-    ZXIC_UINT32 dbg6_wdata_axi_slv1;
-}DPP_CFG_PCIE_DBG6_WDATA_AXI_SLV1_T;
-
-typedef struct dpp_cfg_pcie_dbg6_wdata_axi_slv2_t
-{
-    ZXIC_UINT32 dbg6_wdata_axi_slv2;
-}DPP_CFG_PCIE_DBG6_WDATA_AXI_SLV2_T;
-
-typedef struct dpp_cfg_pcie_dbg6_wdata_axi_slv3_t
-{
-    ZXIC_UINT32 dbg6_wdata_axi_slv3;
-}DPP_CFG_PCIE_DBG6_WDATA_AXI_SLV3_T;
-
-typedef struct dpp_cfg_pcie_dbg7_wdata_axi_slv0_t
-{
-    ZXIC_UINT32 dbg7_wdata_axi_slv0;
-}DPP_CFG_PCIE_DBG7_WDATA_AXI_SLV0_T;
-
-typedef struct dpp_cfg_pcie_dbg7_wdata_axi_slv1_t
-{
-    ZXIC_UINT32 dbg7_wdata_axi_slv1;
-}DPP_CFG_PCIE_DBG7_WDATA_AXI_SLV1_T;
-
-typedef struct dpp_cfg_pcie_dbg7_wdata_axi_slv2_t
-{
-    ZXIC_UINT32 dbg7_wdata_axi_slv2;
-}DPP_CFG_PCIE_DBG7_WDATA_AXI_SLV2_T;
-
-typedef struct dpp_cfg_pcie_dbg7_wdata_axi_slv3_t
-{
-    ZXIC_UINT32 dbg7_wdata_axi_slv3;
-}DPP_CFG_PCIE_DBG7_WDATA_AXI_SLV3_T;
-
-typedef struct dpp_cfg_pcie_dbg8_wdata_axi_slv0_t
-{
-    ZXIC_UINT32 dbg8_wdata_axi_slv0;
-}DPP_CFG_PCIE_DBG8_WDATA_AXI_SLV0_T;
-
-typedef struct dpp_cfg_pcie_dbg8_wdata_axi_slv1_t
-{
-    ZXIC_UINT32 dbg8_wdata_axi_slv1;
-}DPP_CFG_PCIE_DBG8_WDATA_AXI_SLV1_T;
-
-typedef struct dpp_cfg_pcie_dbg8_wdata_axi_slv2_t
-{
-    ZXIC_UINT32 dbg8_wdata_axi_slv2;
-}DPP_CFG_PCIE_DBG8_WDATA_AXI_SLV2_T;
-
-typedef struct dpp_cfg_pcie_dbg8_wdata_axi_slv3_t
-{
-    ZXIC_UINT32 dbg8_wdata_axi_slv3;
-}DPP_CFG_PCIE_DBG8_WDATA_AXI_SLV3_T;
-
-typedef struct dpp_cfg_pcie_dbg9_wdata_axi_slv0_t
-{
-    ZXIC_UINT32 dbg9_wdata_axi_slv0;
-}DPP_CFG_PCIE_DBG9_WDATA_AXI_SLV0_T;
-
-typedef struct dpp_cfg_pcie_dbg9_wdata_axi_slv1_t
-{
-    ZXIC_UINT32 dbg9_wdata_axi_slv1;
-}DPP_CFG_PCIE_DBG9_WDATA_AXI_SLV1_T;
-
-typedef struct dpp_cfg_pcie_dbg9_wdata_axi_slv2_t
-{
-    ZXIC_UINT32 dbg9_wdata_axi_slv2;
-}DPP_CFG_PCIE_DBG9_WDATA_AXI_SLV2_T;
-
-typedef struct dpp_cfg_pcie_dbg9_wdata_axi_slv3_t
-{
-    ZXIC_UINT32 dbg9_wdata_axi_slv3;
-}DPP_CFG_PCIE_DBG9_WDATA_AXI_SLV3_T;
-
-typedef struct dpp_cfg_pcie_dbg_awlen_axi_slv_t
-{
-    ZXIC_UINT32 dbg_awlen_axi_slv;
-}DPP_CFG_PCIE_DBG_AWLEN_AXI_SLV_T;
-
-typedef struct dpp_cfg_pcie_dbg_wlast_axi_slv_t
-{
-    ZXIC_UINT32 dbg_wlast_axi_slv;
-}DPP_CFG_PCIE_DBG_WLAST_AXI_SLV_T;
-
-typedef struct dpp_cfg_pcie_dbg_araddr_axi_slv0_t
-{
-    ZXIC_UINT32 dbg5_wdata_axi_slv1;
-}DPP_CFG_PCIE_DBG_ARADDR_AXI_SLV0_T;
-
-typedef struct dpp_cfg_pcie_dbg_araddr_axi_slv1_t
-{
-    ZXIC_UINT32 dbg5_wdata_axi_slv2;
-}DPP_CFG_PCIE_DBG_ARADDR_AXI_SLV1_T;
-
-typedef struct dpp_cfg_pcie_dbg0_rdata_axi_slv0_t
-{
-    ZXIC_UINT32 dbg5_wdata_axi_slv3;
-}DPP_CFG_PCIE_DBG0_RDATA_AXI_SLV0_T;
-
-typedef struct dpp_cfg_pcie_dbg0_rdata_axi_slv1_t
-{
-    ZXIC_UINT32 dbg6_wdata_axi_slv0;
-}DPP_CFG_PCIE_DBG0_RDATA_AXI_SLV1_T;
-
-typedef struct dpp_cfg_pcie_dbg0_rdata_axi_slv2_t
-{
-    ZXIC_UINT32 dbg6_wdata_axi_slv1;
-}DPP_CFG_PCIE_DBG0_RDATA_AXI_SLV2_T;
-
-typedef struct dpp_cfg_pcie_dbg0_rdata_axi_slv3_t
-{
-    ZXIC_UINT32 dbg6_wdata_axi_slv2;
-}DPP_CFG_PCIE_DBG0_RDATA_AXI_SLV3_T;
-
-typedef struct dpp_cfg_pcie_dbg1_rdata_axi_slv0_t
-{
-    ZXIC_UINT32 dbg6_wdata_axi_slv3;
-}DPP_CFG_PCIE_DBG1_RDATA_AXI_SLV0_T;
-
-typedef struct dpp_cfg_pcie_dbg1_rdata_axi_slv1_t
-{
-    ZXIC_UINT32 dbg7_wdata_axi_slv0;
-}DPP_CFG_PCIE_DBG1_RDATA_AXI_SLV1_T;
-
-typedef struct dpp_cfg_pcie_dbg1_rdata_axi_slv2_t
-{
-    ZXIC_UINT32 dbg7_wdata_axi_slv1;
-}DPP_CFG_PCIE_DBG1_RDATA_AXI_SLV2_T;
-
-typedef struct dpp_cfg_pcie_dbg1_rdata_axi_slv3_t
-{
-    ZXIC_UINT32 dbg7_wdata_axi_slv2;
-}DPP_CFG_PCIE_DBG1_RDATA_AXI_SLV3_T;
-
-typedef struct dpp_cfg_pcie_dbg_rlast_axi_slv_t
-{
-    ZXIC_UINT32 dbg_rlast_axi_slv;
-}DPP_CFG_PCIE_DBG_RLAST_AXI_SLV_T;
-
-typedef struct dpp_cfg_dma_dma_enable_t
-{
-    ZXIC_UINT32 dma_enable;
-}DPP_CFG_DMA_DMA_ENABLE_T;
-
-typedef struct dpp_cfg_dma_up_req_t
-{
-    ZXIC_UINT32 up_req;
-}DPP_CFG_DMA_UP_REQ_T;
-
-typedef struct dpp_cfg_dma_dma_up_current_state_t
-{
-    ZXIC_UINT32 dma_up_current_state;
-}DPP_CFG_DMA_DMA_UP_CURRENT_STATE_T;
-
-typedef struct dpp_cfg_dma_dma_up_req_ack_t
-{
-    ZXIC_UINT32 dma_up_req_ack;
-}DPP_CFG_DMA_DMA_UP_REQ_ACK_T;
-
-typedef struct dpp_cfg_dma_dma_done_latch_t
-{
-    ZXIC_UINT32 done_latch;
-}DPP_CFG_DMA_DMA_DONE_LATCH_T;
-
-typedef struct dpp_cfg_dma_dma_up_cpu_addr_low32_t
-{
-    ZXIC_UINT32 dma_up_cpu_addr_low;
-}DPP_CFG_DMA_DMA_UP_CPU_ADDR_LOW32_T;
-
-typedef struct dpp_cfg_dma_dma_up_cpu_addr_high32_t
-{
-    ZXIC_UINT32 dma_up_cpu_addr_high;
-}DPP_CFG_DMA_DMA_UP_CPU_ADDR_HIGH32_T;
-
-typedef struct dpp_cfg_dma_dma_up_se_addr_t
-{
-    ZXIC_UINT32 dma_up_se_addr;
-}DPP_CFG_DMA_DMA_UP_SE_ADDR_T;
-
-typedef struct dpp_cfg_dma_dma_done_int_t
-{
-    ZXIC_UINT32 dma_done_int;
-}DPP_CFG_DMA_DMA_DONE_INT_T;
-
-typedef struct dpp_cfg_dma_sp_cfg_t
-{
-    ZXIC_UINT32 sp_cfg;
-}DPP_CFG_DMA_SP_CFG_T;
-
-typedef struct dpp_cfg_dma_dma_ing_t
-{
-    ZXIC_UINT32 dma_ing;
-}DPP_CFG_DMA_DMA_ING_T;
-
-typedef struct dpp_cfg_dma_rd_timeout_thresh_t
-{
-    ZXIC_UINT32 rd_timeout_thresh;
-}DPP_CFG_DMA_RD_TIMEOUT_THRESH_T;
-
-typedef struct dpp_cfg_dma_dma_tab_sta_up_fifo_gap_t
-{
-    ZXIC_UINT32 dma_tab_sta_up_fifo_gap;
-}DPP_CFG_DMA_DMA_TAB_STA_UP_FIFO_GAP_T;
-
-typedef struct dpp_cfg_dma_cfg_mac_tim_t
-{
-    ZXIC_UINT32 cfg_mac_tim;
-}DPP_CFG_DMA_CFG_MAC_TIM_T;
-
-typedef struct dpp_cfg_dma_cfg_mac_num_t
-{
-    ZXIC_UINT32 cfg_mac_num;
-}DPP_CFG_DMA_CFG_MAC_NUM_T;
-
-typedef struct dpp_cfg_dma_init_bd_addr_t
-{
-    ZXIC_UINT32 init_bd_addr;
-}DPP_CFG_DMA_INIT_BD_ADDR_T;
-
-typedef struct dpp_cfg_dma_mac_up_bd_addr1_low32_t
-{
-    ZXIC_UINT32 mac_up_bd_addr1_low32;
-}DPP_CFG_DMA_MAC_UP_BD_ADDR1_LOW32_T;
-
-typedef struct dpp_cfg_dma_mac_up_bd_addr1_high32_t
-{
-    ZXIC_UINT32 mac_up_bd_addr1_high32;
-}DPP_CFG_DMA_MAC_UP_BD_ADDR1_HIGH32_T;
-
-typedef struct dpp_cfg_dma_mac_up_bd_addr2_low32_t
-{
-    ZXIC_UINT32 mac_up_bd_addr2_low32;
-}DPP_CFG_DMA_MAC_UP_BD_ADDR2_LOW32_T;
-
-typedef struct dpp_cfg_dma_mac_up_bd_addr2_high32_t
-{
-    ZXIC_UINT32 mac_up_bd_addr2_high32;
-}DPP_CFG_DMA_MAC_UP_BD_ADDR2_HIGH32_T;
-
-typedef struct dpp_cfg_dma_cfg_mac_max_num_t
-{
-    ZXIC_UINT32 cfg_mac_max_num;
-}DPP_CFG_DMA_CFG_MAC_MAX_NUM_T;
-
-typedef struct dpp_cfg_dma_dma_wbuf_ff_empty_t
-{
-    ZXIC_UINT32 dma_wbuf_ff_empty;
-}DPP_CFG_DMA_DMA_WBUF_FF_EMPTY_T;
-
-typedef struct dpp_cfg_dma_dma_wbuf_state_t
-{
-    ZXIC_UINT32 dma_wbuf_state;
-}DPP_CFG_DMA_DMA_WBUF_STATE_T;
-
-typedef struct dpp_cfg_dma_dma_mac_bd_addr_low32_t
-{
-    ZXIC_UINT32 dma_mac_bd_addr_low32;
-}DPP_CFG_DMA_DMA_MAC_BD_ADDR_LOW32_T;
-
-typedef struct dpp_cfg_dma_dma_mac_bd_addr_high32_t
-{
-    ZXIC_UINT32 dma_mac_bd_addr_high32;
-}DPP_CFG_DMA_DMA_MAC_BD_ADDR_HIGH32_T;
-
-typedef struct dpp_cfg_dma_mac_up_enable_t
-{
-    ZXIC_UINT32 mac_up_enable;
-}DPP_CFG_DMA_MAC_UP_ENABLE_T;
-
-typedef struct dpp_cfg_dma_mac_endian_t
-{
-    ZXIC_UINT32 mac_endian;
-}DPP_CFG_DMA_MAC_ENDIAN_T;
-
-typedef struct dpp_cfg_dma_up_endian_t
-{
-    ZXIC_UINT32 up_endian;
-}DPP_CFG_DMA_UP_ENDIAN_T;
-
-typedef struct dpp_cfg_dma_dma_up_rd_cnt_latch_t
-{
-    ZXIC_UINT32 dma_up_rd_cnt_latch;
-}DPP_CFG_DMA_DMA_UP_RD_CNT_LATCH_T;
-
-typedef struct dpp_cfg_dma_dma_up_rcv_cnt_latch_t
-{
-    ZXIC_UINT32 dma_up_rcv_cnt_latch;
-}DPP_CFG_DMA_DMA_UP_RCV_CNT_LATCH_T;
-
-typedef struct dpp_cfg_dma_dma_up_cnt_latch_t
-{
-    ZXIC_UINT32 dma_up_cnt_latch;
-}DPP_CFG_DMA_DMA_UP_CNT_LATCH_T;
-
-typedef struct dpp_cfg_dma_cpu_rd_bd_pulse_t
-{
-    ZXIC_UINT32 cpu_rd_bd_pulse;
-}DPP_CFG_DMA_CPU_RD_BD_PULSE_T;
-
-typedef struct dpp_cfg_dma_cpu_bd_threshold_t
-{
-    ZXIC_UINT32 cpu_bd_threshold;
-}DPP_CFG_DMA_CPU_BD_THRESHOLD_T;
-
-typedef struct dpp_cfg_dma_cpu_bd_used_cnt_t
-{
-    ZXIC_UINT32 cpu_bd_used_cnt;
-}DPP_CFG_DMA_CPU_BD_USED_CNT_T;
-
-typedef struct dpp_cfg_dma_dma_up_rcv_status_t
-{
-    ZXIC_UINT32 dma_up_rcv_status;
-}DPP_CFG_DMA_DMA_UP_RCV_STATUS_T;
-
-typedef struct dpp_cfg_dma_slv_rid_err_en_t
-{
-    ZXIC_UINT32 slv_rid_err_en;
-}DPP_CFG_DMA_SLV_RID_ERR_EN_T;
-
-typedef struct dpp_cfg_dma_slv_rresp_err_en_t
-{
-    ZXIC_UINT32 slv_rresp_err_en;
-}DPP_CFG_DMA_SLV_RRESP_ERR_EN_T;
-
-typedef struct dpp_cfg_dma_se_rdbk_ff_full_t
-{
-    ZXIC_UINT32 se_rdbk_ff_full;
-}DPP_CFG_DMA_SE_RDBK_FF_FULL_T;
-
-typedef struct dpp_cfg_dma_dma_up_data_count_t
-{
-    ZXIC_UINT32 dma_up_data_count;
-}DPP_CFG_DMA_DMA_UP_DATA_COUNT_T;
-
-typedef struct dpp_cfg_dma_dma_mwr_fifo_afull_gap_t
-{
-    ZXIC_UINT32 dma_mwr_fifo_afull_gap;
-}DPP_CFG_DMA_DMA_MWR_FIFO_AFULL_GAP_T;
-
-typedef struct dpp_cfg_dma_dma_info_fifo_afull_gap_t
-{
-    ZXIC_UINT32 dma_mwr_fifo_afull_gap;
-}DPP_CFG_DMA_DMA_INFO_FIFO_AFULL_GAP_T;
-
-typedef struct dpp_cfg_dma_dma_rd_timeout_set_t
-{
-    ZXIC_UINT32 dma_rd_timeout_set;
-}DPP_CFG_DMA_DMA_RD_TIMEOUT_SET_T;
-
-typedef struct dpp_cfg_dma_dma_bd_dat_err_en_t
-{
-    ZXIC_UINT32 dma_bd_dat_err_en;
-}DPP_CFG_DMA_DMA_BD_DAT_ERR_EN_T;
-
-typedef struct dpp_cfg_dma_dma_repeat_cnt_t
-{
-    ZXIC_UINT32 dma_repeat_cnt;
-}DPP_CFG_DMA_DMA_REPEAT_CNT_T;
-
-typedef struct dpp_cfg_dma_dma_rd_timeout_en_t
-{
-    ZXIC_UINT32 dma_rd_timeout_en;
-}DPP_CFG_DMA_DMA_RD_TIMEOUT_EN_T;
-
-typedef struct dpp_cfg_dma_dma_repeat_read_t
-{
-    ZXIC_UINT32 dma_repeat_read;
-}DPP_CFG_DMA_DMA_REPEAT_READ_T;
-
-typedef struct dpp_cfg_dma_dma_repeat_read_en_t
-{
-    ZXIC_UINT32 dma_repeat_read_en;
-}DPP_CFG_DMA_DMA_REPEAT_READ_EN_T;
-
-typedef struct dpp_cfg_dma_bd_ctl_state_t
-{
-    ZXIC_UINT32 bd_ctl_state;
-}DPP_CFG_DMA_BD_CTL_STATE_T;
-
-typedef struct dpp_cfg_dma_dma_done_int_cnt_wr_t
-{
-    ZXIC_UINT32 dma_done_int_cnt_wr;
-}DPP_CFG_DMA_DMA_DONE_INT_CNT_WR_T;
-
-typedef struct dpp_cfg_dma_dma_done_int_cnt_mac_t
-{
-    ZXIC_UINT32 dma_done_int_cnt_mac;
-}DPP_CFG_DMA_DMA_DONE_INT_CNT_MAC_T;
-
-typedef struct dpp_cfg_dma_current_mac_num_t
-{
-    ZXIC_UINT32 current_mac_num;
-}DPP_CFG_DMA_CURRENT_MAC_NUM_T;
-
-typedef struct dpp_cfg_dma_cfg_mac_afifo_afull_t
-{
-    ZXIC_UINT32 cfg_mac_afifo_afull;
-}DPP_CFG_DMA_CFG_MAC_AFIFO_AFULL_T;
-
-typedef struct dpp_cfg_dma_dma_mac_ff_full_t
-{
-    ZXIC_UINT32 dma_mac_ff_full;
-}DPP_CFG_DMA_DMA_MAC_FF_FULL_T;
-
-typedef struct dpp_cfg_dma_user_axi_mst_t
-{
-    ZXIC_UINT32 user_en;
-    ZXIC_UINT32 cfg_epid;
-    ZXIC_UINT32 cfg_vfunc_num;
-    ZXIC_UINT32 cfg_func_num;
-    ZXIC_UINT32 cfg_vfunc_active;
-}DPP_CFG_DMA_USER_AXI_MST_T;
-
-typedef struct dpp_cfg_csr_sbus_state_t
-{
-    ZXIC_UINT32 sbus_state;
-}DPP_CFG_CSR_SBUS_STATE_T;
-
-typedef struct dpp_cfg_csr_mst_debug_en_t
-{
-    ZXIC_UINT32 mst_debug_en;
-}DPP_CFG_CSR_MST_DEBUG_EN_T;
-
-typedef struct dpp_cfg_csr_sbus_command_sel_t
-{
-    ZXIC_UINT32 sbus_command_sel;
-}DPP_CFG_CSR_SBUS_COMMAND_SEL_T;
-
-typedef struct dpp_cfg_csr_soc_rd_time_out_thresh_t
-{
-    ZXIC_UINT32 soc_rd_time_out_thresh;
-}DPP_CFG_CSR_SOC_RD_TIME_OUT_THRESH_T;
-
-typedef struct dpp_cfg_csr_big_little_byte_order_t
-{
-    ZXIC_UINT32 big_little_byte_order;
-}DPP_CFG_CSR_BIG_LITTLE_BYTE_ORDER_T;
-
-typedef struct dpp_cfg_csr_ecc_bypass_read_t
-{
-    ZXIC_UINT32 ecc_bypass_read;
-}DPP_CFG_CSR_ECC_BYPASS_READ_T;
-
-typedef struct dpp_cfg_csr_ahb_async_wr_fifo_afull_gap_t
-{
-    ZXIC_UINT32 ahb_async_wr_fifo_afull_gap;
-}DPP_CFG_CSR_AHB_ASYNC_WR_FIFO_AFULL_GAP_T;
-
-typedef struct dpp_cfg_csr_ahb_async_rd_fifo_afull_gap_t
-{
-    ZXIC_UINT32 ahb_async_rd_fifo_afull_gap;
-}DPP_CFG_CSR_AHB_ASYNC_RD_FIFO_AFULL_GAP_T;
-
-typedef struct dpp_cfg_csr_ahb_async_cpl_fifo_afull_gap_t
-{
-    ZXIC_UINT32 ahb_async_cpl_fifo_afull_gap;
-}DPP_CFG_CSR_AHB_ASYNC_CPL_FIFO_AFULL_GAP_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data0_high26_t
-{
-    ZXIC_UINT32 mst_debug_data0_high26;
-}DPP_CFG_CSR_MST_DEBUG_DATA0_HIGH26_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data0_low32_t
-{
-    ZXIC_UINT32 mst_debug_data0_low32;
-}DPP_CFG_CSR_MST_DEBUG_DATA0_LOW32_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data1_high26_t
-{
-    ZXIC_UINT32 mst_debug_data1_high26;
-}DPP_CFG_CSR_MST_DEBUG_DATA1_HIGH26_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data1_low32_t
-{
-    ZXIC_UINT32 mst_debug_data1_low32;
-}DPP_CFG_CSR_MST_DEBUG_DATA1_LOW32_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data2_high26_t
-{
-    ZXIC_UINT32 mst_debug_data2_high26;
-}DPP_CFG_CSR_MST_DEBUG_DATA2_HIGH26_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data2_low32_t
-{
-    ZXIC_UINT32 mst_debug_data2_low32;
-}DPP_CFG_CSR_MST_DEBUG_DATA2_LOW32_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data3_high26_t
-{
-    ZXIC_UINT32 mst_debug_data3_high26;
-}DPP_CFG_CSR_MST_DEBUG_DATA3_HIGH26_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data3_low32_t
-{
-    ZXIC_UINT32 mst_debug_data3_low32;
-}DPP_CFG_CSR_MST_DEBUG_DATA3_LOW32_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data4_high26_t
-{
-    ZXIC_UINT32 mst_debug_data4_high26;
-}DPP_CFG_CSR_MST_DEBUG_DATA4_HIGH26_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data4_low32_t
-{
-    ZXIC_UINT32 mst_debug_data4_low32;
-}DPP_CFG_CSR_MST_DEBUG_DATA4_LOW32_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data5_high26_t
-{
-    ZXIC_UINT32 mst_debug_data5_high26;
-}DPP_CFG_CSR_MST_DEBUG_DATA5_HIGH26_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data5_low32_t
-{
-    ZXIC_UINT32 mst_debug_data5_low32;
-}DPP_CFG_CSR_MST_DEBUG_DATA5_LOW32_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data6_high26_t
-{
-    ZXIC_UINT32 mst_debug_data6_high26;
-}DPP_CFG_CSR_MST_DEBUG_DATA6_HIGH26_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data6_low32_t
-{
-    ZXIC_UINT32 mst_debug_data6_low32;
-}DPP_CFG_CSR_MST_DEBUG_DATA6_LOW32_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data7_high26_t
-{
-    ZXIC_UINT32 mst_debug_data7_high26;
-}DPP_CFG_CSR_MST_DEBUG_DATA7_HIGH26_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data7_low32_t
-{
-    ZXIC_UINT32 mst_debug_data7_low32;
-}DPP_CFG_CSR_MST_DEBUG_DATA7_LOW32_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data8_high26_t
-{
-    ZXIC_UINT32 mst_debug_data8_high26;
-}DPP_CFG_CSR_MST_DEBUG_DATA8_HIGH26_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data8_low32_t
-{
-    ZXIC_UINT32 mst_debug_data8_low32;
-}DPP_CFG_CSR_MST_DEBUG_DATA8_LOW32_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data9_high26_t
-{
-    ZXIC_UINT32 mst_debug_data9_high26;
-}DPP_CFG_CSR_MST_DEBUG_DATA9_HIGH26_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data9_low32_t
-{
-    ZXIC_UINT32 mst_debug_data9_low32;
-}DPP_CFG_CSR_MST_DEBUG_DATA9_LOW32_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data10_high26_t
-{
-    ZXIC_UINT32 mst_debug_data10_high26;
-}DPP_CFG_CSR_MST_DEBUG_DATA10_HIGH26_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data10_low32_t
-{
-    ZXIC_UINT32 mst_debug_data10_low32;
-}DPP_CFG_CSR_MST_DEBUG_DATA10_LOW32_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data11_high26_t
-{
-    ZXIC_UINT32 mst_debug_data11_high26;
-}DPP_CFG_CSR_MST_DEBUG_DATA11_HIGH26_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data11_low32_t
-{
-    ZXIC_UINT32 mst_debug_data11_low32;
-}DPP_CFG_CSR_MST_DEBUG_DATA11_LOW32_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data12_high26_t
-{
-    ZXIC_UINT32 mst_debug_data12_high26;
-}DPP_CFG_CSR_MST_DEBUG_DATA12_HIGH26_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data12_low32_t
-{
-    ZXIC_UINT32 mst_debug_data12_low32;
-}DPP_CFG_CSR_MST_DEBUG_DATA12_LOW32_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data13_high26_t
-{
-    ZXIC_UINT32 mst_debug_data13_high26;
-}DPP_CFG_CSR_MST_DEBUG_DATA13_HIGH26_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data13_low32_t
-{
-    ZXIC_UINT32 mst_debug_data13_low32;
-}DPP_CFG_CSR_MST_DEBUG_DATA13_LOW32_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data14_high26_t
-{
-    ZXIC_UINT32 mst_debug_data14_high26;
-}DPP_CFG_CSR_MST_DEBUG_DATA14_HIGH26_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data14_low32_t
-{
-    ZXIC_UINT32 mst_debug_data14_low32;
-}DPP_CFG_CSR_MST_DEBUG_DATA14_LOW32_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data15_high26_t
-{
-    ZXIC_UINT32 mst_debug_data15_high26;
-}DPP_CFG_CSR_MST_DEBUG_DATA15_HIGH26_T;
-
-typedef struct dpp_cfg_csr_mst_debug_data15_low32_t
-{
-    ZXIC_UINT32 mst_debug_data15_low32;
-}DPP_CFG_CSR_MST_DEBUG_DATA15_LOW32_T;
+typedef struct dpp_cfg_pcie_int_repeat_t {
+	ZXIC_UINT32 int_repeat;
+} DPP_CFG_PCIE_INT_REPEAT_T;
 
+typedef struct dpp_cfg_dma_dma_up_size_t {
+	ZXIC_UINT32 dma_up_size;
+} DPP_CFG_DMA_DMA_UP_SIZE_T;
+
+typedef struct dpp_cfg_csr_soc_wr_time_out_thresh_t {
+	ZXIC_UINT32 soc_wr_time_out_thresh;
+} DPP_CFG_CSR_SOC_WR_TIME_OUT_THRESH_T;
+
+typedef struct dpp_cfg_pcie_pcie_ddr_switch_t {
+	ZXIC_UINT32 pcie_ddr_switch;
+} DPP_CFG_PCIE_PCIE_DDR_SWITCH_T;
+
+typedef struct dpp_cfg_pcie_user0_int_en_t {
+	ZXIC_UINT32 user_int_en;
+} DPP_CFG_PCIE_USER0_INT_EN_T;
+
+typedef struct dpp_cfg_pcie_user0_int_mask_t {
+	ZXIC_UINT32 user_int_mask;
+} DPP_CFG_PCIE_USER0_INT_MASK_T;
+
+typedef struct dpp_cfg_pcie_user0_int_status_t {
+	ZXIC_UINT32 user_int_status;
+} DPP_CFG_PCIE_USER0_INT_STATUS_T;
+
+typedef struct dpp_cfg_pcie_user1_int_en_t {
+	ZXIC_UINT32 user_int_en;
+} DPP_CFG_PCIE_USER1_INT_EN_T;
+
+typedef struct dpp_cfg_pcie_user1_int_mask_t {
+	ZXIC_UINT32 user_int_mask;
+} DPP_CFG_PCIE_USER1_INT_MASK_T;
+
+typedef struct dpp_cfg_pcie_user1_int_status_t {
+	ZXIC_UINT32 user_int_status;
+} DPP_CFG_PCIE_USER1_INT_STATUS_T;
+
+typedef struct dpp_cfg_pcie_user2_int_en_t {
+	ZXIC_UINT32 user_int_en;
+} DPP_CFG_PCIE_USER2_INT_EN_T;
+
+typedef struct dpp_cfg_pcie_user2_int_mask_t {
+	ZXIC_UINT32 user_int_mask;
+} DPP_CFG_PCIE_USER2_INT_MASK_T;
+
+typedef struct dpp_cfg_pcie_user2_int_status_t {
+	ZXIC_UINT32 user_int_status;
+} DPP_CFG_PCIE_USER2_INT_STATUS_T;
+
+typedef struct dpp_cfg_pcie_ecc_1b_int_en_t {
+	ZXIC_UINT32 ecc_1b_int_en;
+} DPP_CFG_PCIE_ECC_1B_INT_EN_T;
+
+typedef struct dpp_cfg_pcie_ecc_1b_int_mask_t {
+	ZXIC_UINT32 ecc_1b_int_mask;
+} DPP_CFG_PCIE_ECC_1B_INT_MASK_T;
+
+typedef struct dpp_cfg_pcie_ecc_1b_int_status_t {
+	ZXIC_UINT32 ecc_1b_int_status;
+} DPP_CFG_PCIE_ECC_1B_INT_STATUS_T;
+
+typedef struct dpp_cfg_pcie_ecc_2b_int_en_t {
+	ZXIC_UINT32 ecc_2b_int_en;
+} DPP_CFG_PCIE_ECC_2B_INT_EN_T;
+
+typedef struct dpp_cfg_pcie_ecc_2b_int_mask_t {
+	ZXIC_UINT32 ecc_2b_int_mask;
+} DPP_CFG_PCIE_ECC_2B_INT_MASK_T;
+
+typedef struct dpp_cfg_pcie_ecc_2b_int_status_t {
+	ZXIC_UINT32 ecc_2b_int_status;
+} DPP_CFG_PCIE_ECC_2B_INT_STATUS_T;
+
+typedef struct dpp_cfg_pcie_cfg_int_status_t {
+	ZXIC_UINT32 cfg_int_status;
+} DPP_CFG_PCIE_CFG_INT_STATUS_T;
+
+typedef struct dpp_cfg_pcie_i_core_to_cntl_t {
+	ZXIC_UINT32 i_core_to_cntl;
+} DPP_CFG_PCIE_I_CORE_TO_CNTL_T;
+
+typedef struct dpp_cfg_pcie_test_in_low_t {
+	ZXIC_UINT32 test_in_low;
+} DPP_CFG_PCIE_TEST_IN_LOW_T;
+
+typedef struct dpp_cfg_pcie_test_in_high_t {
+	ZXIC_UINT32 test_in_high;
+} DPP_CFG_PCIE_TEST_IN_HIGH_T;
+
+typedef struct dpp_cfg_pcie_local_interrupt_out_t {
+	ZXIC_UINT32 local_interrupt_out;
+} DPP_CFG_PCIE_LOCAL_INTERRUPT_OUT_T;
+
+typedef struct dpp_cfg_pcie_pl_ltssm_t {
+	ZXIC_UINT32 pl_ltssm;
+} DPP_CFG_PCIE_PL_LTSSM_T;
+
+typedef struct dpp_cfg_pcie_test_out0_t {
+	ZXIC_UINT32 test_out0;
+} DPP_CFG_PCIE_TEST_OUT0_T;
+
+typedef struct dpp_cfg_pcie_test_out1_t {
+	ZXIC_UINT32 test_out1;
+} DPP_CFG_PCIE_TEST_OUT1_T;
+
+typedef struct dpp_cfg_pcie_test_out2_t {
+	ZXIC_UINT32 test_out2;
+} DPP_CFG_PCIE_TEST_OUT2_T;
+
+typedef struct dpp_cfg_pcie_test_out3_t {
+	ZXIC_UINT32 test_out3;
+} DPP_CFG_PCIE_TEST_OUT3_T;
+
+typedef struct dpp_cfg_pcie_test_out4_t {
+	ZXIC_UINT32 test_out4;
+} DPP_CFG_PCIE_TEST_OUT4_T;
+
+typedef struct dpp_cfg_pcie_test_out5_t {
+	ZXIC_UINT32 test_out5;
+} DPP_CFG_PCIE_TEST_OUT5_T;
+
+typedef struct dpp_cfg_pcie_test_out6_t {
+	ZXIC_UINT32 test_out6;
+} DPP_CFG_PCIE_TEST_OUT6_T;
+
+typedef struct dpp_cfg_pcie_test_out7_t {
+	ZXIC_UINT32 test_out7;
+} DPP_CFG_PCIE_TEST_OUT7_T;
+
+typedef struct dpp_cfg_pcie_sync_o_core_status_t {
+	ZXIC_UINT32 sync_o_core_status;
+} DPP_CFG_PCIE_SYNC_O_CORE_STATUS_T;
+
+typedef struct dpp_cfg_pcie_sync_o_alert_dbe_t {
+	ZXIC_UINT32 sync_o_alert_dbe;
+} DPP_CFG_PCIE_SYNC_O_ALERT_DBE_T;
+
+typedef struct dpp_cfg_pcie_sync_o_alert_sbe_t {
+	ZXIC_UINT32 sync_o_alert_sbe;
+} DPP_CFG_PCIE_SYNC_O_ALERT_SBE_T;
+
+typedef struct dpp_cfg_pcie_sync_o_link_loopback_en_t {
+	ZXIC_UINT32 sync_o_link_loopback_en;
+} DPP_CFG_PCIE_SYNC_O_LINK_LOOPBACK_EN_T;
+
+typedef struct dpp_cfg_pcie_sync_o_local_fs_lf_valid_t {
+	ZXIC_UINT32 sync_o_local_fs_lf_valid;
+} DPP_CFG_PCIE_SYNC_O_LOCAL_FS_LF_VALID_T;
+
+typedef struct dpp_cfg_pcie_sync_o_rx_idle_detect_t {
+	ZXIC_UINT32 sync_o_rx_idle_detect;
+} DPP_CFG_PCIE_SYNC_O_RX_IDLE_DETECT_T;
+
+typedef struct dpp_cfg_pcie_sync_o_rx_rdy_t {
+	ZXIC_UINT32 sync_o_rx_rdy;
+} DPP_CFG_PCIE_SYNC_O_RX_RDY_T;
+
+typedef struct dpp_cfg_pcie_sync_o_tx_rdy_t {
+	ZXIC_UINT32 sync_o_tx_rdy;
+} DPP_CFG_PCIE_SYNC_O_TX_RDY_T;
+
+typedef struct dpp_cfg_pcie_pcie_link_up_cnt_t {
+	ZXIC_UINT32 pcie_link_up_cnt;
+} DPP_CFG_PCIE_PCIE_LINK_UP_CNT_T;
+
+typedef struct dpp_cfg_pcie_test_out_pcie0_t {
+	ZXIC_UINT32 test_out_pcie0;
+} DPP_CFG_PCIE_TEST_OUT_PCIE0_T;
+
+typedef struct dpp_cfg_pcie_test_out_pcie1_t {
+	ZXIC_UINT32 test_out_pcie1;
+} DPP_CFG_PCIE_TEST_OUT_PCIE1_T;
+
+typedef struct dpp_cfg_pcie_test_out_pcie2_t {
+	ZXIC_UINT32 test_out_pcie2;
+} DPP_CFG_PCIE_TEST_OUT_PCIE2_T;
+
+typedef struct dpp_cfg_pcie_test_out_pcie3_t {
+	ZXIC_UINT32 test_out_pcie3;
+} DPP_CFG_PCIE_TEST_OUT_PCIE3_T;
+
+typedef struct dpp_cfg_pcie_test_out_pcie4_t {
+	ZXIC_UINT32 test_out_pcie4;
+} DPP_CFG_PCIE_TEST_OUT_PCIE4_T;
+
+typedef struct dpp_cfg_pcie_test_out_pcie5_t {
+	ZXIC_UINT32 test_out_pcie5;
+} DPP_CFG_PCIE_TEST_OUT_PCIE5_T;
+
+typedef struct dpp_cfg_pcie_test_out_pcie6_t {
+	ZXIC_UINT32 test_out_pcie6;
+} DPP_CFG_PCIE_TEST_OUT_PCIE6_T;
+
+typedef struct dpp_cfg_pcie_test_out_pcie7_t {
+	ZXIC_UINT32 test_out_pcie7;
+} DPP_CFG_PCIE_TEST_OUT_PCIE7_T;
+
+typedef struct dpp_cfg_pcie_test_out_pcie8_t {
+	ZXIC_UINT32 test_out_pcie8;
+} DPP_CFG_PCIE_TEST_OUT_PCIE8_T;
+
+typedef struct dpp_cfg_pcie_test_out_pcie9_t {
+	ZXIC_UINT32 test_out_pcie9;
+} DPP_CFG_PCIE_TEST_OUT_PCIE9_T;
+
+typedef struct dpp_cfg_pcie_test_out_pcie10_t {
+	ZXIC_UINT32 test_out_pcie10;
+} DPP_CFG_PCIE_TEST_OUT_PCIE10_T;
+
+typedef struct dpp_cfg_pcie_test_out_pcie11_t {
+	ZXIC_UINT32 test_out_pcie11;
+} DPP_CFG_PCIE_TEST_OUT_PCIE11_T;
+
+typedef struct dpp_cfg_pcie_test_out_pcie12_t {
+	ZXIC_UINT32 test_out_pcie12;
+} DPP_CFG_PCIE_TEST_OUT_PCIE12_T;
+
+typedef struct dpp_cfg_pcie_test_out_pcie13_t {
+	ZXIC_UINT32 test_out_pcie13;
+} DPP_CFG_PCIE_TEST_OUT_PCIE13_T;
+
+typedef struct dpp_cfg_pcie_test_out_pcie14_t {
+	ZXIC_UINT32 test_out_pcie14;
+} DPP_CFG_PCIE_TEST_OUT_PCIE14_T;
+
+typedef struct dpp_cfg_pcie_test_out_pcie15_t {
+	ZXIC_UINT32 test_out_pcie15;
+} DPP_CFG_PCIE_TEST_OUT_PCIE15_T;
+
+typedef struct dpp_cfg_pcie_int_repeat_en_t {
+	ZXIC_UINT32 int_repeat_en;
+} DPP_CFG_PCIE_INT_REPEAT_EN_T;
+
+typedef struct dpp_cfg_pcie_dbg_awid_axi_mst_t {
+	ZXIC_UINT32 dbg_awid_axi_mst;
+} DPP_CFG_PCIE_DBG_AWID_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_awaddr_axi_mst0_t {
+	ZXIC_UINT32 dbg_awaddr_axi_mst0;
+} DPP_CFG_PCIE_DBG_AWADDR_AXI_MST0_T;
+
+typedef struct dpp_cfg_pcie_dbg_awaddr_axi_mst1_t {
+	ZXIC_UINT32 dbg_awaddr_axi_mst1;
+} DPP_CFG_PCIE_DBG_AWADDR_AXI_MST1_T;
+
+typedef struct dpp_cfg_pcie_dbg_awlen_axi_mst_t {
+	ZXIC_UINT32 dbg_awlen_axi_mst;
+} DPP_CFG_PCIE_DBG_AWLEN_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_awsize_axi_mst_t {
+	ZXIC_UINT32 dbg_awid_axi_mst;
+} DPP_CFG_PCIE_DBG_AWSIZE_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_awburst_axi_mst_t {
+	ZXIC_UINT32 dbg_awburst_axi_mst;
+} DPP_CFG_PCIE_DBG_AWBURST_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_awlock_axi_mst_t {
+	ZXIC_UINT32 dbg_awlock_axi_mst;
+} DPP_CFG_PCIE_DBG_AWLOCK_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_awcache_axi_mst_t {
+	ZXIC_UINT32 dbg_awcache_axi_mst;
+} DPP_CFG_PCIE_DBG_AWCACHE_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_awprot_axi_mst_t {
+	ZXIC_UINT32 dbg_awprot_axi_mst;
+} DPP_CFG_PCIE_DBG_AWPROT_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_wid_axi_mst_t {
+	ZXIC_UINT32 dbg_wid_axi_mst;
+} DPP_CFG_PCIE_DBG_WID_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_wdata_axi_mst0_t {
+	ZXIC_UINT32 dbg_wdata_axi_mst0;
+} DPP_CFG_PCIE_DBG_WDATA_AXI_MST0_T;
+
+typedef struct dpp_cfg_pcie_dbg_wdata_axi_mst1_t {
+	ZXIC_UINT32 dbg_wdata_axi_mst1;
+} DPP_CFG_PCIE_DBG_WDATA_AXI_MST1_T;
+
+typedef struct dpp_cfg_pcie_dbg_wdata_axi_mst2_t {
+	ZXIC_UINT32 dbg_wdata_axi_mst2;
+} DPP_CFG_PCIE_DBG_WDATA_AXI_MST2_T;
+
+typedef struct dpp_cfg_pcie_dbg_wdata_axi_mst3_t {
+	ZXIC_UINT32 dbg_wdata_axi_mst3;
+} DPP_CFG_PCIE_DBG_WDATA_AXI_MST3_T;
+
+typedef struct dpp_cfg_pcie_dbg_wstrb_axi_mst_t {
+	ZXIC_UINT32 dbg_wstrb_axi_mst;
+} DPP_CFG_PCIE_DBG_WSTRB_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_wlast_axi_mst_t {
+	ZXIC_UINT32 dbg_wlast_axi_mst;
+} DPP_CFG_PCIE_DBG_WLAST_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_arid_axi_mst_t {
+	ZXIC_UINT32 dbg_arid_axi_mst;
+} DPP_CFG_PCIE_DBG_ARID_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_araddr_axi_mst0_t {
+	ZXIC_UINT32 dbg_araddr_axi_mst0;
+} DPP_CFG_PCIE_DBG_ARADDR_AXI_MST0_T;
+
+typedef struct dpp_cfg_pcie_dbg_araddr_axi_mst1_t {
+	ZXIC_UINT32 dbg_araddr_axi_mst1;
+} DPP_CFG_PCIE_DBG_ARADDR_AXI_MST1_T;
+
+typedef struct dpp_cfg_pcie_dbg_arlen_axi_mst_t {
+	ZXIC_UINT32 dbg_arlen_axi_mst;
+} DPP_CFG_PCIE_DBG_ARLEN_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_arsize_axi_mst_t {
+	ZXIC_UINT32 dbg_arsize_axi_mst;
+} DPP_CFG_PCIE_DBG_ARSIZE_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_arburst_axi_mst_t {
+	ZXIC_UINT32 dbg_arburst_axi_mst;
+} DPP_CFG_PCIE_DBG_ARBURST_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_arlock_axi_mst_t {
+	ZXIC_UINT32 dbg_arlock_axi_mst;
+} DPP_CFG_PCIE_DBG_ARLOCK_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_arcache_axi_mst_t {
+	ZXIC_UINT32 dbg_arcache_axi_mst;
+} DPP_CFG_PCIE_DBG_ARCACHE_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_arprot_axi_mst_t {
+	ZXIC_UINT32 dbg_arprot_axi_mst;
+} DPP_CFG_PCIE_DBG_ARPROT_AXI_MST_T;
+
+typedef struct dpp_cfg_pcie_dbg_rdata_axi_mst0_t {
+	ZXIC_UINT32 dbg_rdata_axi_mst0;
+} DPP_CFG_PCIE_DBG_RDATA_AXI_MST0_T;
+
+typedef struct dpp_cfg_pcie_dbg_rdata_axi_mst1_t {
+	ZXIC_UINT32 dbg_rdata_axi_mst1;
+} DPP_CFG_PCIE_DBG_RDATA_AXI_MST1_T;
+
+typedef struct dpp_cfg_pcie_dbg_rdata_axi_mst2_t {
+	ZXIC_UINT32 dbg_rdata_axi_mst2;
+} DPP_CFG_PCIE_DBG_RDATA_AXI_MST2_T;
+
+typedef struct dpp_cfg_pcie_dbg_rdata_axi_mst3_t {
+	ZXIC_UINT32 dbg_rdata_axi_mst3;
+} DPP_CFG_PCIE_DBG_RDATA_AXI_MST3_T;
+
+typedef struct dpp_cfg_pcie_axi_mst_state_t {
+	ZXIC_UINT32 axi_mst_state;
+} DPP_CFG_PCIE_AXI_MST_STATE_T;
+
+typedef struct dpp_cfg_pcie_axi_cfg_state_t {
+	ZXIC_UINT32 axi_cfg_state;
+} DPP_CFG_PCIE_AXI_CFG_STATE_T;
+
+typedef struct dpp_cfg_pcie_axi_slv_rd_state_t {
+	ZXIC_UINT32 axi_slv_rd_state;
+} DPP_CFG_PCIE_AXI_SLV_RD_STATE_T;
+
+typedef struct dpp_cfg_pcie_axi_slv_wr_state_t {
+	ZXIC_UINT32 axi_slv_wr_state;
+} DPP_CFG_PCIE_AXI_SLV_WR_STATE_T;
+
+typedef struct dpp_cfg_pcie_axim_delay_en_t {
+	ZXIC_UINT32 axim_delay_en;
+} DPP_CFG_PCIE_AXIM_DELAY_EN_T;
+
+typedef struct dpp_cfg_pcie_axim_delay_t {
+	ZXIC_UINT32 axim_delay;
+} DPP_CFG_PCIE_AXIM_DELAY_T;
+
+typedef struct dpp_cfg_pcie_axim_speed_wr_t {
+	ZXIC_UINT32 axim_speed_wr;
+} DPP_CFG_PCIE_AXIM_SPEED_WR_T;
+
+typedef struct dpp_cfg_pcie_axim_speed_rd_t {
+	ZXIC_UINT32 axim_speed_rd;
+} DPP_CFG_PCIE_AXIM_SPEED_RD_T;
+
+typedef struct dpp_cfg_pcie_dbg_awaddr_axi_slv0_t {
+	ZXIC_UINT32 dbg_awaddr_axi_slv0;
+} DPP_CFG_PCIE_DBG_AWADDR_AXI_SLV0_T;
+
+typedef struct dpp_cfg_pcie_dbg_awaddr_axi_slv1_t {
+	ZXIC_UINT32 dbg_awaddr_axi_slv1;
+} DPP_CFG_PCIE_DBG_AWADDR_AXI_SLV1_T;
+
+typedef struct dpp_cfg_pcie_dbg0_wdata_axi_slv0_t {
+	ZXIC_UINT32 dbg0_wdata_axi_slv0;
+} DPP_CFG_PCIE_DBG0_WDATA_AXI_SLV0_T;
+
+typedef struct dpp_cfg_pcie_dbg0_wdata_axi_slv1_t {
+	ZXIC_UINT32 dbg0_wdata_axi_slv1;
+} DPP_CFG_PCIE_DBG0_WDATA_AXI_SLV1_T;
+
+typedef struct dpp_cfg_pcie_dbg0_wdata_axi_slv2_t {
+	ZXIC_UINT32 dbg0_wdata_axi_slv2;
+} DPP_CFG_PCIE_DBG0_WDATA_AXI_SLV2_T;
+
+typedef struct dpp_cfg_pcie_dbg0_wdata_axi_slv3_t {
+	ZXIC_UINT32 dbg0_wdata_axi_slv3;
+} DPP_CFG_PCIE_DBG0_WDATA_AXI_SLV3_T;
+
+typedef struct dpp_cfg_pcie_dbg1_wdata_axi_slv0_t {
+	ZXIC_UINT32 dbg1_wdata_axi_slv0;
+} DPP_CFG_PCIE_DBG1_WDATA_AXI_SLV0_T;
+
+typedef struct dpp_cfg_pcie_dbg1_wdata_axi_slv1_t {
+	ZXIC_UINT32 dbg1_wdata_axi_slv1;
+} DPP_CFG_PCIE_DBG1_WDATA_AXI_SLV1_T;
+
+typedef struct dpp_cfg_pcie_dbg1_wdata_axi_slv2_t {
+	ZXIC_UINT32 dbg1_wdata_axi_slv2;
+} DPP_CFG_PCIE_DBG1_WDATA_AXI_SLV2_T;
+
+typedef struct dpp_cfg_pcie_dbg1_wdata_axi_slv3_t {
+	ZXIC_UINT32 dbg1_wdata_axi_slv3;
+} DPP_CFG_PCIE_DBG1_WDATA_AXI_SLV3_T;
+
+typedef struct dpp_cfg_pcie_dbg2_wdata_axi_slv0_t {
+	ZXIC_UINT32 dbg2_wdata_axi_slv0;
+} DPP_CFG_PCIE_DBG2_WDATA_AXI_SLV0_T;
+
+typedef struct dpp_cfg_pcie_dbg2_wdata_axi_slv1_t {
+	ZXIC_UINT32 dbg2_wdata_axi_slv1;
+} DPP_CFG_PCIE_DBG2_WDATA_AXI_SLV1_T;
+
+typedef struct dpp_cfg_pcie_dbg2_wdata_axi_slv2_t {
+	ZXIC_UINT32 dbg2_wdata_axi_slv2;
+} DPP_CFG_PCIE_DBG2_WDATA_AXI_SLV2_T;
+
+typedef struct dpp_cfg_pcie_dbg2_wdata_axi_slv3_t {
+	ZXIC_UINT32 dbg2_wdata_axi_slv3;
+} DPP_CFG_PCIE_DBG2_WDATA_AXI_SLV3_T;
+
+typedef struct dpp_cfg_pcie_dbg3_wdata_axi_slv0_t {
+	ZXIC_UINT32 dbg3_wdata_axi_slv0;
+} DPP_CFG_PCIE_DBG3_WDATA_AXI_SLV0_T;
+
+typedef struct dpp_cfg_pcie_dbg3_wdata_axi_slv1_t {
+	ZXIC_UINT32 dbg3_wdata_axi_slv1;
+} DPP_CFG_PCIE_DBG3_WDATA_AXI_SLV1_T;
+
+typedef struct dpp_cfg_pcie_dbg3_wdata_axi_slv2_t {
+	ZXIC_UINT32 dbg3_wdata_axi_slv2;
+} DPP_CFG_PCIE_DBG3_WDATA_AXI_SLV2_T;
+
+typedef struct dpp_cfg_pcie_dbg3_wdata_axi_slv3_t {
+	ZXIC_UINT32 dbg3_wdata_axi_slv3;
+} DPP_CFG_PCIE_DBG3_WDATA_AXI_SLV3_T;
+
+typedef struct dpp_cfg_pcie_dbg4_wdata_axi_slv0_t {
+	ZXIC_UINT32 dbg4_wdata_axi_slv0;
+} DPP_CFG_PCIE_DBG4_WDATA_AXI_SLV0_T;
+
+typedef struct dpp_cfg_pcie_dbg4_wdata_axi_slv1_t {
+	ZXIC_UINT32 dbg4_wdata_axi_slv1;
+} DPP_CFG_PCIE_DBG4_WDATA_AXI_SLV1_T;
+
+typedef struct dpp_cfg_pcie_dbg4_wdata_axi_slv2_t {
+	ZXIC_UINT32 dbg4_wdata_axi_slv2;
+} DPP_CFG_PCIE_DBG4_WDATA_AXI_SLV2_T;
+
+typedef struct dpp_cfg_pcie_dbg4_wdata_axi_slv3_t {
+	ZXIC_UINT32 dbg4_wdata_axi_slv3;
+} DPP_CFG_PCIE_DBG4_WDATA_AXI_SLV3_T;
+
+typedef struct dpp_cfg_pcie_dbg5_wdata_axi_slv0_t {
+	ZXIC_UINT32 dbg5_wdata_axi_slv0;
+} DPP_CFG_PCIE_DBG5_WDATA_AXI_SLV0_T;
+
+typedef struct dpp_cfg_pcie_dbg5_wdata_axi_slv1_t {
+	ZXIC_UINT32 dbg5_wdata_axi_slv1;
+} DPP_CFG_PCIE_DBG5_WDATA_AXI_SLV1_T;
+
+typedef struct dpp_cfg_pcie_dbg5_wdata_axi_slv2_t {
+	ZXIC_UINT32 dbg5_wdata_axi_slv2;
+} DPP_CFG_PCIE_DBG5_WDATA_AXI_SLV2_T;
+
+typedef struct dpp_cfg_pcie_dbg5_wdata_axi_slv3_t {
+	ZXIC_UINT32 dbg5_wdata_axi_slv3;
+} DPP_CFG_PCIE_DBG5_WDATA_AXI_SLV3_T;
+
+typedef struct dpp_cfg_pcie_dbg6_wdata_axi_slv0_t {
+	ZXIC_UINT32 dbg6_wdata_axi_slv0;
+} DPP_CFG_PCIE_DBG6_WDATA_AXI_SLV0_T;
+
+typedef struct dpp_cfg_pcie_dbg6_wdata_axi_slv1_t {
+	ZXIC_UINT32 dbg6_wdata_axi_slv1;
+} DPP_CFG_PCIE_DBG6_WDATA_AXI_SLV1_T;
+
+typedef struct dpp_cfg_pcie_dbg6_wdata_axi_slv2_t {
+	ZXIC_UINT32 dbg6_wdata_axi_slv2;
+} DPP_CFG_PCIE_DBG6_WDATA_AXI_SLV2_T;
+
+typedef struct dpp_cfg_pcie_dbg6_wdata_axi_slv3_t {
+	ZXIC_UINT32 dbg6_wdata_axi_slv3;
+} DPP_CFG_PCIE_DBG6_WDATA_AXI_SLV3_T;
+
+typedef struct dpp_cfg_pcie_dbg7_wdata_axi_slv0_t {
+	ZXIC_UINT32 dbg7_wdata_axi_slv0;
+} DPP_CFG_PCIE_DBG7_WDATA_AXI_SLV0_T;
+
+typedef struct dpp_cfg_pcie_dbg7_wdata_axi_slv1_t {
+	ZXIC_UINT32 dbg7_wdata_axi_slv1;
+} DPP_CFG_PCIE_DBG7_WDATA_AXI_SLV1_T;
+
+typedef struct dpp_cfg_pcie_dbg7_wdata_axi_slv2_t {
+	ZXIC_UINT32 dbg7_wdata_axi_slv2;
+} DPP_CFG_PCIE_DBG7_WDATA_AXI_SLV2_T;
+
+typedef struct dpp_cfg_pcie_dbg7_wdata_axi_slv3_t {
+	ZXIC_UINT32 dbg7_wdata_axi_slv3;
+} DPP_CFG_PCIE_DBG7_WDATA_AXI_SLV3_T;
+
+typedef struct dpp_cfg_pcie_dbg8_wdata_axi_slv0_t {
+	ZXIC_UINT32 dbg8_wdata_axi_slv0;
+} DPP_CFG_PCIE_DBG8_WDATA_AXI_SLV0_T;
+
+typedef struct dpp_cfg_pcie_dbg8_wdata_axi_slv1_t {
+	ZXIC_UINT32 dbg8_wdata_axi_slv1;
+} DPP_CFG_PCIE_DBG8_WDATA_AXI_SLV1_T;
+
+typedef struct dpp_cfg_pcie_dbg8_wdata_axi_slv2_t {
+	ZXIC_UINT32 dbg8_wdata_axi_slv2;
+} DPP_CFG_PCIE_DBG8_WDATA_AXI_SLV2_T;
+
+typedef struct dpp_cfg_pcie_dbg8_wdata_axi_slv3_t {
+	ZXIC_UINT32 dbg8_wdata_axi_slv3;
+} DPP_CFG_PCIE_DBG8_WDATA_AXI_SLV3_T;
+
+typedef struct dpp_cfg_pcie_dbg9_wdata_axi_slv0_t {
+	ZXIC_UINT32 dbg9_wdata_axi_slv0;
+} DPP_CFG_PCIE_DBG9_WDATA_AXI_SLV0_T;
+
+typedef struct dpp_cfg_pcie_dbg9_wdata_axi_slv1_t {
+	ZXIC_UINT32 dbg9_wdata_axi_slv1;
+} DPP_CFG_PCIE_DBG9_WDATA_AXI_SLV1_T;
+
+typedef struct dpp_cfg_pcie_dbg9_wdata_axi_slv2_t {
+	ZXIC_UINT32 dbg9_wdata_axi_slv2;
+} DPP_CFG_PCIE_DBG9_WDATA_AXI_SLV2_T;
+
+typedef struct dpp_cfg_pcie_dbg9_wdata_axi_slv3_t {
+	ZXIC_UINT32 dbg9_wdata_axi_slv3;
+} DPP_CFG_PCIE_DBG9_WDATA_AXI_SLV3_T;
+
+typedef struct dpp_cfg_pcie_dbg_awlen_axi_slv_t {
+	ZXIC_UINT32 dbg_awlen_axi_slv;
+} DPP_CFG_PCIE_DBG_AWLEN_AXI_SLV_T;
+
+typedef struct dpp_cfg_pcie_dbg_wlast_axi_slv_t {
+	ZXIC_UINT32 dbg_wlast_axi_slv;
+} DPP_CFG_PCIE_DBG_WLAST_AXI_SLV_T;
+
+typedef struct dpp_cfg_pcie_dbg_araddr_axi_slv0_t {
+	ZXIC_UINT32 dbg5_wdata_axi_slv1;
+} DPP_CFG_PCIE_DBG_ARADDR_AXI_SLV0_T;
+
+typedef struct dpp_cfg_pcie_dbg_araddr_axi_slv1_t {
+	ZXIC_UINT32 dbg5_wdata_axi_slv2;
+} DPP_CFG_PCIE_DBG_ARADDR_AXI_SLV1_T;
+
+typedef struct dpp_cfg_pcie_dbg0_rdata_axi_slv0_t {
+	ZXIC_UINT32 dbg5_wdata_axi_slv3;
+} DPP_CFG_PCIE_DBG0_RDATA_AXI_SLV0_T;
+
+typedef struct dpp_cfg_pcie_dbg0_rdata_axi_slv1_t {
+	ZXIC_UINT32 dbg6_wdata_axi_slv0;
+} DPP_CFG_PCIE_DBG0_RDATA_AXI_SLV1_T;
+
+typedef struct dpp_cfg_pcie_dbg0_rdata_axi_slv2_t {
+	ZXIC_UINT32 dbg6_wdata_axi_slv1;
+} DPP_CFG_PCIE_DBG0_RDATA_AXI_SLV2_T;
+
+typedef struct dpp_cfg_pcie_dbg0_rdata_axi_slv3_t {
+	ZXIC_UINT32 dbg6_wdata_axi_slv2;
+} DPP_CFG_PCIE_DBG0_RDATA_AXI_SLV3_T;
+
+typedef struct dpp_cfg_pcie_dbg1_rdata_axi_slv0_t {
+	ZXIC_UINT32 dbg6_wdata_axi_slv3;
+} DPP_CFG_PCIE_DBG1_RDATA_AXI_SLV0_T;
+
+typedef struct dpp_cfg_pcie_dbg1_rdata_axi_slv1_t {
+	ZXIC_UINT32 dbg7_wdata_axi_slv0;
+} DPP_CFG_PCIE_DBG1_RDATA_AXI_SLV1_T;
+
+typedef struct dpp_cfg_pcie_dbg1_rdata_axi_slv2_t {
+	ZXIC_UINT32 dbg7_wdata_axi_slv1;
+} DPP_CFG_PCIE_DBG1_RDATA_AXI_SLV2_T;
+
+typedef struct dpp_cfg_pcie_dbg1_rdata_axi_slv3_t {
+	ZXIC_UINT32 dbg7_wdata_axi_slv2;
+} DPP_CFG_PCIE_DBG1_RDATA_AXI_SLV3_T;
+
+typedef struct dpp_cfg_pcie_dbg_rlast_axi_slv_t {
+	ZXIC_UINT32 dbg_rlast_axi_slv;
+} DPP_CFG_PCIE_DBG_RLAST_AXI_SLV_T;
+
+typedef struct dpp_cfg_dma_dma_enable_t {
+	ZXIC_UINT32 dma_enable;
+} DPP_CFG_DMA_DMA_ENABLE_T;
+
+typedef struct dpp_cfg_dma_up_req_t {
+	ZXIC_UINT32 up_req;
+} DPP_CFG_DMA_UP_REQ_T;
+
+typedef struct dpp_cfg_dma_dma_up_current_state_t {
+	ZXIC_UINT32 dma_up_current_state;
+} DPP_CFG_DMA_DMA_UP_CURRENT_STATE_T;
+
+typedef struct dpp_cfg_dma_dma_up_req_ack_t {
+	ZXIC_UINT32 dma_up_req_ack;
+} DPP_CFG_DMA_DMA_UP_REQ_ACK_T;
+
+typedef struct dpp_cfg_dma_dma_done_latch_t {
+	ZXIC_UINT32 done_latch;
+} DPP_CFG_DMA_DMA_DONE_LATCH_T;
+
+typedef struct dpp_cfg_dma_dma_up_cpu_addr_low32_t {
+	ZXIC_UINT32 dma_up_cpu_addr_low;
+} DPP_CFG_DMA_DMA_UP_CPU_ADDR_LOW32_T;
+
+typedef struct dpp_cfg_dma_dma_up_cpu_addr_high32_t {
+	ZXIC_UINT32 dma_up_cpu_addr_high;
+} DPP_CFG_DMA_DMA_UP_CPU_ADDR_HIGH32_T;
+
+typedef struct dpp_cfg_dma_dma_up_se_addr_t {
+	ZXIC_UINT32 dma_up_se_addr;
+} DPP_CFG_DMA_DMA_UP_SE_ADDR_T;
+
+typedef struct dpp_cfg_dma_dma_done_int_t {
+	ZXIC_UINT32 dma_done_int;
+} DPP_CFG_DMA_DMA_DONE_INT_T;
+
+typedef struct dpp_cfg_dma_sp_cfg_t {
+	ZXIC_UINT32 sp_cfg;
+} DPP_CFG_DMA_SP_CFG_T;
+
+typedef struct dpp_cfg_dma_dma_ing_t {
+	ZXIC_UINT32 dma_ing;
+} DPP_CFG_DMA_DMA_ING_T;
+
+typedef struct dpp_cfg_dma_rd_timeout_thresh_t {
+	ZXIC_UINT32 rd_timeout_thresh;
+} DPP_CFG_DMA_RD_TIMEOUT_THRESH_T;
+
+typedef struct dpp_cfg_dma_dma_tab_sta_up_fifo_gap_t {
+	ZXIC_UINT32 dma_tab_sta_up_fifo_gap;
+} DPP_CFG_DMA_DMA_TAB_STA_UP_FIFO_GAP_T;
+
+typedef struct dpp_cfg_dma_cfg_mac_tim_t {
+	ZXIC_UINT32 cfg_mac_tim;
+} DPP_CFG_DMA_CFG_MAC_TIM_T;
+
+typedef struct dpp_cfg_dma_cfg_mac_num_t {
+	ZXIC_UINT32 cfg_mac_num;
+} DPP_CFG_DMA_CFG_MAC_NUM_T;
+
+typedef struct dpp_cfg_dma_init_bd_addr_t {
+	ZXIC_UINT32 init_bd_addr;
+} DPP_CFG_DMA_INIT_BD_ADDR_T;
+
+typedef struct dpp_cfg_dma_mac_up_bd_addr1_low32_t {
+	ZXIC_UINT32 mac_up_bd_addr1_low32;
+} DPP_CFG_DMA_MAC_UP_BD_ADDR1_LOW32_T;
+
+typedef struct dpp_cfg_dma_mac_up_bd_addr1_high32_t {
+	ZXIC_UINT32 mac_up_bd_addr1_high32;
+} DPP_CFG_DMA_MAC_UP_BD_ADDR1_HIGH32_T;
+
+typedef struct dpp_cfg_dma_mac_up_bd_addr2_low32_t {
+	ZXIC_UINT32 mac_up_bd_addr2_low32;
+} DPP_CFG_DMA_MAC_UP_BD_ADDR2_LOW32_T;
+
+typedef struct dpp_cfg_dma_mac_up_bd_addr2_high32_t {
+	ZXIC_UINT32 mac_up_bd_addr2_high32;
+} DPP_CFG_DMA_MAC_UP_BD_ADDR2_HIGH32_T;
+
+typedef struct dpp_cfg_dma_cfg_mac_max_num_t {
+	ZXIC_UINT32 cfg_mac_max_num;
+} DPP_CFG_DMA_CFG_MAC_MAX_NUM_T;
+
+typedef struct dpp_cfg_dma_dma_wbuf_ff_empty_t {
+	ZXIC_UINT32 dma_wbuf_ff_empty;
+} DPP_CFG_DMA_DMA_WBUF_FF_EMPTY_T;
+
+typedef struct dpp_cfg_dma_dma_wbuf_state_t {
+	ZXIC_UINT32 dma_wbuf_state;
+} DPP_CFG_DMA_DMA_WBUF_STATE_T;
+
+typedef struct dpp_cfg_dma_dma_mac_bd_addr_low32_t {
+	ZXIC_UINT32 dma_mac_bd_addr_low32;
+} DPP_CFG_DMA_DMA_MAC_BD_ADDR_LOW32_T;
+
+typedef struct dpp_cfg_dma_dma_mac_bd_addr_high32_t {
+	ZXIC_UINT32 dma_mac_bd_addr_high32;
+} DPP_CFG_DMA_DMA_MAC_BD_ADDR_HIGH32_T;
+
+typedef struct dpp_cfg_dma_mac_up_enable_t {
+	ZXIC_UINT32 mac_up_enable;
+} DPP_CFG_DMA_MAC_UP_ENABLE_T;
+
+typedef struct dpp_cfg_dma_mac_endian_t {
+	ZXIC_UINT32 mac_endian;
+} DPP_CFG_DMA_MAC_ENDIAN_T;
+
+typedef struct dpp_cfg_dma_up_endian_t {
+	ZXIC_UINT32 up_endian;
+} DPP_CFG_DMA_UP_ENDIAN_T;
+
+typedef struct dpp_cfg_dma_dma_up_rd_cnt_latch_t {
+	ZXIC_UINT32 dma_up_rd_cnt_latch;
+} DPP_CFG_DMA_DMA_UP_RD_CNT_LATCH_T;
+
+typedef struct dpp_cfg_dma_dma_up_rcv_cnt_latch_t {
+	ZXIC_UINT32 dma_up_rcv_cnt_latch;
+} DPP_CFG_DMA_DMA_UP_RCV_CNT_LATCH_T;
+
+typedef struct dpp_cfg_dma_dma_up_cnt_latch_t {
+	ZXIC_UINT32 dma_up_cnt_latch;
+} DPP_CFG_DMA_DMA_UP_CNT_LATCH_T;
+
+typedef struct dpp_cfg_dma_cpu_rd_bd_pulse_t {
+	ZXIC_UINT32 cpu_rd_bd_pulse;
+} DPP_CFG_DMA_CPU_RD_BD_PULSE_T;
+
+typedef struct dpp_cfg_dma_cpu_bd_threshold_t {
+	ZXIC_UINT32 cpu_bd_threshold;
+} DPP_CFG_DMA_CPU_BD_THRESHOLD_T;
+
+typedef struct dpp_cfg_dma_cpu_bd_used_cnt_t {
+	ZXIC_UINT32 cpu_bd_used_cnt;
+} DPP_CFG_DMA_CPU_BD_USED_CNT_T;
+
+typedef struct dpp_cfg_dma_dma_up_rcv_status_t {
+	ZXIC_UINT32 dma_up_rcv_status;
+} DPP_CFG_DMA_DMA_UP_RCV_STATUS_T;
+
+typedef struct dpp_cfg_dma_slv_rid_err_en_t {
+	ZXIC_UINT32 slv_rid_err_en;
+} DPP_CFG_DMA_SLV_RID_ERR_EN_T;
+
+typedef struct dpp_cfg_dma_slv_rresp_err_en_t {
+	ZXIC_UINT32 slv_rresp_err_en;
+} DPP_CFG_DMA_SLV_RRESP_ERR_EN_T;
+
+typedef struct dpp_cfg_dma_se_rdbk_ff_full_t {
+	ZXIC_UINT32 se_rdbk_ff_full;
+} DPP_CFG_DMA_SE_RDBK_FF_FULL_T;
+
+typedef struct dpp_cfg_dma_dma_up_data_count_t {
+	ZXIC_UINT32 dma_up_data_count;
+} DPP_CFG_DMA_DMA_UP_DATA_COUNT_T;
+
+typedef struct dpp_cfg_dma_dma_mwr_fifo_afull_gap_t {
+	ZXIC_UINT32 dma_mwr_fifo_afull_gap;
+} DPP_CFG_DMA_DMA_MWR_FIFO_AFULL_GAP_T;
+
+typedef struct dpp_cfg_dma_dma_info_fifo_afull_gap_t {
+	ZXIC_UINT32 dma_mwr_fifo_afull_gap;
+} DPP_CFG_DMA_DMA_INFO_FIFO_AFULL_GAP_T;
+
+typedef struct dpp_cfg_dma_dma_rd_timeout_set_t {
+	ZXIC_UINT32 dma_rd_timeout_set;
+} DPP_CFG_DMA_DMA_RD_TIMEOUT_SET_T;
+
+typedef struct dpp_cfg_dma_dma_bd_dat_err_en_t {
+	ZXIC_UINT32 dma_bd_dat_err_en;
+} DPP_CFG_DMA_DMA_BD_DAT_ERR_EN_T;
+
+typedef struct dpp_cfg_dma_dma_repeat_cnt_t {
+	ZXIC_UINT32 dma_repeat_cnt;
+} DPP_CFG_DMA_DMA_REPEAT_CNT_T;
+
+typedef struct dpp_cfg_dma_dma_rd_timeout_en_t {
+	ZXIC_UINT32 dma_rd_timeout_en;
+} DPP_CFG_DMA_DMA_RD_TIMEOUT_EN_T;
+
+typedef struct dpp_cfg_dma_dma_repeat_read_t {
+	ZXIC_UINT32 dma_repeat_read;
+} DPP_CFG_DMA_DMA_REPEAT_READ_T;
+
+typedef struct dpp_cfg_dma_dma_repeat_read_en_t {
+	ZXIC_UINT32 dma_repeat_read_en;
+} DPP_CFG_DMA_DMA_REPEAT_READ_EN_T;
+
+typedef struct dpp_cfg_dma_bd_ctl_state_t {
+	ZXIC_UINT32 bd_ctl_state;
+} DPP_CFG_DMA_BD_CTL_STATE_T;
+
+typedef struct dpp_cfg_dma_dma_done_int_cnt_wr_t {
+	ZXIC_UINT32 dma_done_int_cnt_wr;
+} DPP_CFG_DMA_DMA_DONE_INT_CNT_WR_T;
+
+typedef struct dpp_cfg_dma_dma_done_int_cnt_mac_t {
+	ZXIC_UINT32 dma_done_int_cnt_mac;
+} DPP_CFG_DMA_DMA_DONE_INT_CNT_MAC_T;
+
+typedef struct dpp_cfg_dma_current_mac_num_t {
+	ZXIC_UINT32 current_mac_num;
+} DPP_CFG_DMA_CURRENT_MAC_NUM_T;
+
+typedef struct dpp_cfg_dma_cfg_mac_afifo_afull_t {
+	ZXIC_UINT32 cfg_mac_afifo_afull;
+} DPP_CFG_DMA_CFG_MAC_AFIFO_AFULL_T;
+
+typedef struct dpp_cfg_dma_dma_mac_ff_full_t {
+	ZXIC_UINT32 dma_mac_ff_full;
+} DPP_CFG_DMA_DMA_MAC_FF_FULL_T;
+
+typedef struct dpp_cfg_dma_user_axi_mst_t {
+	ZXIC_UINT32 user_en;
+	ZXIC_UINT32 cfg_epid;
+	ZXIC_UINT32 cfg_vfunc_num;
+	ZXIC_UINT32 cfg_func_num;
+	ZXIC_UINT32 cfg_vfunc_active;
+} DPP_CFG_DMA_USER_AXI_MST_T;
+
+typedef struct dpp_cfg_csr_sbus_state_t {
+	ZXIC_UINT32 sbus_state;
+} DPP_CFG_CSR_SBUS_STATE_T;
+
+typedef struct dpp_cfg_csr_mst_debug_en_t {
+	ZXIC_UINT32 mst_debug_en;
+} DPP_CFG_CSR_MST_DEBUG_EN_T;
+
+typedef struct dpp_cfg_csr_sbus_command_sel_t {
+	ZXIC_UINT32 sbus_command_sel;
+} DPP_CFG_CSR_SBUS_COMMAND_SEL_T;
+
+typedef struct dpp_cfg_csr_soc_rd_time_out_thresh_t {
+	ZXIC_UINT32 soc_rd_time_out_thresh;
+} DPP_CFG_CSR_SOC_RD_TIME_OUT_THRESH_T;
+
+typedef struct dpp_cfg_csr_big_little_byte_order_t {
+	ZXIC_UINT32 big_little_byte_order;
+} DPP_CFG_CSR_BIG_LITTLE_BYTE_ORDER_T;
+
+typedef struct dpp_cfg_csr_ecc_bypass_read_t {
+	ZXIC_UINT32 ecc_bypass_read;
+} DPP_CFG_CSR_ECC_BYPASS_READ_T;
+
+typedef struct dpp_cfg_csr_ahb_async_wr_fifo_afull_gap_t {
+	ZXIC_UINT32 ahb_async_wr_fifo_afull_gap;
+} DPP_CFG_CSR_AHB_ASYNC_WR_FIFO_AFULL_GAP_T;
+
+typedef struct dpp_cfg_csr_ahb_async_rd_fifo_afull_gap_t {
+	ZXIC_UINT32 ahb_async_rd_fifo_afull_gap;
+} DPP_CFG_CSR_AHB_ASYNC_RD_FIFO_AFULL_GAP_T;
+
+typedef struct dpp_cfg_csr_ahb_async_cpl_fifo_afull_gap_t {
+	ZXIC_UINT32 ahb_async_cpl_fifo_afull_gap;
+} DPP_CFG_CSR_AHB_ASYNC_CPL_FIFO_AFULL_GAP_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data0_high26_t {
+	ZXIC_UINT32 mst_debug_data0_high26;
+} DPP_CFG_CSR_MST_DEBUG_DATA0_HIGH26_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data0_low32_t {
+	ZXIC_UINT32 mst_debug_data0_low32;
+} DPP_CFG_CSR_MST_DEBUG_DATA0_LOW32_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data1_high26_t {
+	ZXIC_UINT32 mst_debug_data1_high26;
+} DPP_CFG_CSR_MST_DEBUG_DATA1_HIGH26_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data1_low32_t {
+	ZXIC_UINT32 mst_debug_data1_low32;
+} DPP_CFG_CSR_MST_DEBUG_DATA1_LOW32_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data2_high26_t {
+	ZXIC_UINT32 mst_debug_data2_high26;
+} DPP_CFG_CSR_MST_DEBUG_DATA2_HIGH26_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data2_low32_t {
+	ZXIC_UINT32 mst_debug_data2_low32;
+} DPP_CFG_CSR_MST_DEBUG_DATA2_LOW32_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data3_high26_t {
+	ZXIC_UINT32 mst_debug_data3_high26;
+} DPP_CFG_CSR_MST_DEBUG_DATA3_HIGH26_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data3_low32_t {
+	ZXIC_UINT32 mst_debug_data3_low32;
+} DPP_CFG_CSR_MST_DEBUG_DATA3_LOW32_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data4_high26_t {
+	ZXIC_UINT32 mst_debug_data4_high26;
+} DPP_CFG_CSR_MST_DEBUG_DATA4_HIGH26_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data4_low32_t {
+	ZXIC_UINT32 mst_debug_data4_low32;
+} DPP_CFG_CSR_MST_DEBUG_DATA4_LOW32_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data5_high26_t {
+	ZXIC_UINT32 mst_debug_data5_high26;
+} DPP_CFG_CSR_MST_DEBUG_DATA5_HIGH26_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data5_low32_t {
+	ZXIC_UINT32 mst_debug_data5_low32;
+} DPP_CFG_CSR_MST_DEBUG_DATA5_LOW32_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data6_high26_t {
+	ZXIC_UINT32 mst_debug_data6_high26;
+} DPP_CFG_CSR_MST_DEBUG_DATA6_HIGH26_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data6_low32_t {
+	ZXIC_UINT32 mst_debug_data6_low32;
+} DPP_CFG_CSR_MST_DEBUG_DATA6_LOW32_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data7_high26_t {
+	ZXIC_UINT32 mst_debug_data7_high26;
+} DPP_CFG_CSR_MST_DEBUG_DATA7_HIGH26_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data7_low32_t {
+	ZXIC_UINT32 mst_debug_data7_low32;
+} DPP_CFG_CSR_MST_DEBUG_DATA7_LOW32_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data8_high26_t {
+	ZXIC_UINT32 mst_debug_data8_high26;
+} DPP_CFG_CSR_MST_DEBUG_DATA8_HIGH26_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data8_low32_t {
+	ZXIC_UINT32 mst_debug_data8_low32;
+} DPP_CFG_CSR_MST_DEBUG_DATA8_LOW32_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data9_high26_t {
+	ZXIC_UINT32 mst_debug_data9_high26;
+} DPP_CFG_CSR_MST_DEBUG_DATA9_HIGH26_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data9_low32_t {
+	ZXIC_UINT32 mst_debug_data9_low32;
+} DPP_CFG_CSR_MST_DEBUG_DATA9_LOW32_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data10_high26_t {
+	ZXIC_UINT32 mst_debug_data10_high26;
+} DPP_CFG_CSR_MST_DEBUG_DATA10_HIGH26_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data10_low32_t {
+	ZXIC_UINT32 mst_debug_data10_low32;
+} DPP_CFG_CSR_MST_DEBUG_DATA10_LOW32_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data11_high26_t {
+	ZXIC_UINT32 mst_debug_data11_high26;
+} DPP_CFG_CSR_MST_DEBUG_DATA11_HIGH26_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data11_low32_t {
+	ZXIC_UINT32 mst_debug_data11_low32;
+} DPP_CFG_CSR_MST_DEBUG_DATA11_LOW32_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data12_high26_t {
+	ZXIC_UINT32 mst_debug_data12_high26;
+} DPP_CFG_CSR_MST_DEBUG_DATA12_HIGH26_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data12_low32_t {
+	ZXIC_UINT32 mst_debug_data12_low32;
+} DPP_CFG_CSR_MST_DEBUG_DATA12_LOW32_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data13_high26_t {
+	ZXIC_UINT32 mst_debug_data13_high26;
+} DPP_CFG_CSR_MST_DEBUG_DATA13_HIGH26_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data13_low32_t {
+	ZXIC_UINT32 mst_debug_data13_low32;
+} DPP_CFG_CSR_MST_DEBUG_DATA13_LOW32_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data14_high26_t {
+	ZXIC_UINT32 mst_debug_data14_high26;
+} DPP_CFG_CSR_MST_DEBUG_DATA14_HIGH26_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data14_low32_t {
+	ZXIC_UINT32 mst_debug_data14_low32;
+} DPP_CFG_CSR_MST_DEBUG_DATA14_LOW32_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data15_high26_t {
+	ZXIC_UINT32 mst_debug_data15_high26;
+} DPP_CFG_CSR_MST_DEBUG_DATA15_HIGH26_T;
+
+typedef struct dpp_cfg_csr_mst_debug_data15_low32_t {
+	ZXIC_UINT32 mst_debug_data15_low32;
+} DPP_CFG_CSR_MST_DEBUG_DATA15_LOW32_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_dtb4k_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_dtb4k_reg.h
index 5ae6c123d095c955123b60a0bc61e232eeb6aba1..6f5a624b1ef9d6cda33f50eb4bc5d153ee22b219 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_dtb4k_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_dtb4k_reg.h
@@ -3,45 +3,38 @@
 #define _DPP_DTB4K_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_dtb4k_dtb_enq_cfg_queue_dtb_addr_h_0_127_t
-{
-    ZXIC_UINT32 cfg_queue_dtb_addr_h;
-}DPP_DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_H_0_127_T;
-
-typedef struct dpp_dtb4k_dtb_enq_cfg_queue_dtb_addr_l_0_127_t
-{
-    ZXIC_UINT32 cfg_queue_dtb_addr_l;
-}DPP_DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_L_0_127_T;
-
-typedef struct dpp_dtb4k_dtb_enq_cfg_queue_dtb_len_0_127_t
-{
-    ZXIC_UINT32 cfg_dtb_cmd_type;
-    ZXIC_UINT32 cfg_dtb_cmd_int_en;
-    ZXIC_UINT32 cfg_queue_dtb_len;
-}DPP_DTB4K_DTB_ENQ_CFG_QUEUE_DTB_LEN_0_127_T;
-
-typedef struct dpp_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_t
-{
-    ZXIC_UINT32 info_queue_buf_space_left;
-}DPP_DTB4K_DTB_ENQ_INFO_QUEUE_BUF_SPACE_LEFT_0_127_T;
-
-typedef struct dpp_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_t
-{
-    ZXIC_UINT32 dbi_en;
-    ZXIC_UINT32 queue_en;
-    ZXIC_UINT32 cfg_epid;
-    ZXIC_UINT32 cfg_vfunc_num;
-    ZXIC_UINT32 cfg_vector;
-    ZXIC_UINT32 cfg_func_num;
-    ZXIC_UINT32 cfg_vfunc_active;
-}DPP_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T;
-
+typedef struct dpp_dtb4k_dtb_enq_cfg_queue_dtb_addr_h_0_127_t {
+	ZXIC_UINT32 cfg_queue_dtb_addr_h;
+} DPP_DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_H_0_127_T;
+
+typedef struct dpp_dtb4k_dtb_enq_cfg_queue_dtb_addr_l_0_127_t {
+	ZXIC_UINT32 cfg_queue_dtb_addr_l;
+} DPP_DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_L_0_127_T;
+
+typedef struct dpp_dtb4k_dtb_enq_cfg_queue_dtb_len_0_127_t {
+	ZXIC_UINT32 cfg_dtb_cmd_type;
+	ZXIC_UINT32 cfg_dtb_cmd_int_en;
+	ZXIC_UINT32 cfg_queue_dtb_len;
+} DPP_DTB4K_DTB_ENQ_CFG_QUEUE_DTB_LEN_0_127_T;
+
+typedef struct dpp_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_t {
+	ZXIC_UINT32 info_queue_buf_space_left;
+} DPP_DTB4K_DTB_ENQ_INFO_QUEUE_BUF_SPACE_LEFT_0_127_T;
+
+typedef struct dpp_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_t {
+	ZXIC_UINT32 dbi_en;
+	ZXIC_UINT32 queue_en;
+	ZXIC_UINT32 cfg_epid;
+	ZXIC_UINT32 cfg_vfunc_num;
+	ZXIC_UINT32 cfg_vector;
+	ZXIC_UINT32 cfg_func_num;
+	ZXIC_UINT32 cfg_vfunc_active;
+} DPP_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_dtb_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_dtb_reg.h
index b0989ce51d36ac0b4d1050b42cd55ce62357ac52..561adc9d53811badfa06ef18b59c3e14fff1dba7 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_dtb_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_dtb_reg.h
@@ -3,597 +3,482 @@
 #define _DPP_DTB_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_dtb_dtb_cfg_cfg_eram_wr_interval_cnt_t
-{
-    ZXIC_UINT32 cfg_eram_wr_interval_cnt;
-}DPP_DTB_DTB_CFG_CFG_ERAM_WR_INTERVAL_CNT_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_zcam_wr_interval_cnt_t
-{
-    ZXIC_UINT32 cfg_zcam_wr_interval_cnt;
-}DPP_DTB_DTB_CFG_CFG_ZCAM_WR_INTERVAL_CNT_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_tcam_wr_interval_cnt_t
-{
-    ZXIC_UINT32 cfg_zcam_wr_interval_cnt;
-}DPP_DTB_DTB_CFG_CFG_TCAM_WR_INTERVAL_CNT_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_ddr_wr_interval_cnt_t
-{
-    ZXIC_UINT32 cfg_ddr_wr_interval_cnt;
-}DPP_DTB_DTB_CFG_CFG_DDR_WR_INTERVAL_CNT_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_hash_wr_interval_cnt_t
-{
-    ZXIC_UINT32 cfg_hash_wr_interval_cnt;
-}DPP_DTB_DTB_CFG_CFG_HASH_WR_INTERVAL_CNT_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_eram_rd_interval_cnt_t
-{
-    ZXIC_UINT32 cfg_eram_rd_interval_cnt;
-}DPP_DTB_DTB_CFG_CFG_ERAM_RD_INTERVAL_CNT_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_zcam_rd_interval_cnt_t
-{
-    ZXIC_UINT32 cfg_zcam_rd_interval_cnt;
-}DPP_DTB_DTB_CFG_CFG_ZCAM_RD_INTERVAL_CNT_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_tcam_rd_interval_cnt_t
-{
-    ZXIC_UINT32 cfg_tcam_rd_interval_cnt;
-}DPP_DTB_DTB_CFG_CFG_TCAM_RD_INTERVAL_CNT_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_ddr_rd_interval_cnt_t
-{
-    ZXIC_UINT32 cfg_ddr_rd_interval_cnt;
-}DPP_DTB_DTB_CFG_CFG_DDR_RD_INTERVAL_CNT_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_dtb_queue_lock_state_0_3_t
-{
-    ZXIC_UINT32 cfg_dtb_queue_lock_state;
-}DPP_DTB_DTB_CFG_CFG_DTB_QUEUE_LOCK_STATE_0_3_T;
-
-typedef struct dpp_dtb_dtb_axim0_w_convert_0_mode_t
-{
-    ZXIC_UINT32 w_convert_mode;
-}DPP_DTB_DTB_AXIM0_W_CONVERT_0_MODE_T;
-
-typedef struct dpp_dtb_dtb_axim0_r_convert_0_mode_t
-{
-    ZXIC_UINT32 r_convert_mode;
-}DPP_DTB_DTB_AXIM0_R_CONVERT_0_MODE_T;
-
-typedef struct dpp_dtb_dtb_axim0_aximr_os_t
-{
-    ZXIC_UINT32 aximr_os;
-}DPP_DTB_DTB_AXIM0_AXIMR_OS_T;
-
-typedef struct dpp_dtb_dtb_axim1_w_convert_1_mode_t
-{
-    ZXIC_UINT32 w_convert_mode;
-}DPP_DTB_DTB_AXIM1_W_CONVERT_1_MODE_T;
-
-typedef struct dpp_dtb_dtb_axim1_r_convert_1_mode_t
-{
-    ZXIC_UINT32 r_convert_mode;
-}DPP_DTB_DTB_AXIM1_R_CONVERT_1_MODE_T;
-
-typedef struct dpp_dtb_dtb_axis_axis_convert_mode_t
-{
-    ZXIC_UINT32 w_r_convert_mode;
-}DPP_DTB_DTB_AXIS_AXIS_CONVERT_MODE_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_event0_t
-{
-    ZXIC_UINT32 cfg_finish_int_event0;
-}DPP_DTB_DTB_CFG_CFG_FINISH_INT_EVENT0_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_event1_t
-{
-    ZXIC_UINT32 cfg_finish_int_event1;
-}DPP_DTB_DTB_CFG_CFG_FINISH_INT_EVENT1_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_event2_t
-{
-    ZXIC_UINT32 cfg_finish_int_event2;
-}DPP_DTB_DTB_CFG_CFG_FINISH_INT_EVENT2_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_event3_t
-{
-    ZXIC_UINT32 cfg_finish_int_event3;
-}DPP_DTB_DTB_CFG_CFG_FINISH_INT_EVENT3_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_maks0_t
-{
-    ZXIC_UINT32 cfg_finish_int_mask0;
-}DPP_DTB_DTB_CFG_CFG_FINISH_INT_MAKS0_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_maks1_t
-{
-    ZXIC_UINT32 cfg_finish_int_mask1;
-}DPP_DTB_DTB_CFG_CFG_FINISH_INT_MAKS1_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_maks2_t
-{
-    ZXIC_UINT32 cfg_finish_int_mask2;
-}DPP_DTB_DTB_CFG_CFG_FINISH_INT_MAKS2_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_maks3_t
-{
-    ZXIC_UINT32 cfg_finish_int_mask3;
-}DPP_DTB_DTB_CFG_CFG_FINISH_INT_MAKS3_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_test0_t
-{
-    ZXIC_UINT32 cfg_finish_int_test0;
-}DPP_DTB_DTB_CFG_CFG_FINISH_INT_TEST0_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_test1_t
-{
-    ZXIC_UINT32 cfg_finish_int_test1;
-}DPP_DTB_DTB_CFG_CFG_FINISH_INT_TEST1_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_test2_t
-{
-    ZXIC_UINT32 cfg_finish_int_test2;
-}DPP_DTB_DTB_CFG_CFG_FINISH_INT_TEST2_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_test3_t
-{
-    ZXIC_UINT32 cfg_finish_int_test3;
-}DPP_DTB_DTB_CFG_CFG_FINISH_INT_TEST3_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_dtb_int_to_riscv_sel_t
-{
-    ZXIC_UINT32 cfg_dtb_int_to_riscv_sel0;
-}DPP_DTB_DTB_CFG_CFG_DTB_INT_TO_RISCV_SEL_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_dtb_ep_int_msix_enable_t
-{
-    ZXIC_UINT32 cfg_dtb_ep_int_msix_enable;
-}DPP_DTB_DTB_CFG_CFG_DTB_EP_INT_MSIX_ENABLE_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_h_0_15_t
-{
-    ZXIC_UINT32 cfg_dtb_ep_doorbell_addr_h_0_15;
-}DPP_DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_H_0_15_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_l_0_15_t
-{
-    ZXIC_UINT32 cfg_dtb_ep_doorbell_addr_l_0_15;
-}DPP_DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_L_0_15_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_dtb_debug_mode_en_t
-{
-    ZXIC_UINT32 cfg_dtb_debug_mode_en;
-}DPP_DTB_DTB_CFG_CFG_DTB_DEBUG_MODE_EN_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_table_addr_high_t
-{
-    ZXIC_UINT32 info_axi_last_rd_table_addr_high;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_HIGH_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_table_addr_low_t
-{
-    ZXIC_UINT32 info_axi_last_rd_table_addr_low;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_LOW_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_table_len_t
-{
-    ZXIC_UINT32 info_axi_last_rd_table_len;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_LEN_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_table_user_t
-{
-    ZXIC_UINT32 info_rd_table_user_en;
-    ZXIC_UINT32 info_rd_table_epid;
-    ZXIC_UINT32 info_rd_table_vfunc_num;
-    ZXIC_UINT32 info_rd_table_func_num;
-    ZXIC_UINT32 info_rd_table_vfunc_active;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_table_onload_cnt_t
-{
-    ZXIC_UINT32 info_axi_last_rd_table_onload_cnt;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ONLOAD_CNT_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_axi_rd_table_resp_err_t
-{
-    ZXIC_UINT32 cnt_axi_rd_table_resp_err;
-}DPP_DTB_DTB_CFG_CNT_AXI_RD_TABLE_RESP_ERR_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_pd_addr_high_t
-{
-    ZXIC_UINT32 info_axi_last_rd_pd_addr_high;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_HIGH_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_pd_addr_low_t
-{
-    ZXIC_UINT32 info_axi_last_rd_pd_addr_low;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_LOW_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_pd_len_t
-{
-    ZXIC_UINT32 info_axi_last_rd_pd_len;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_LEN_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_pd_user_t
-{
-    ZXIC_UINT32 info_rd_pd_user_en;
-    ZXIC_UINT32 info_rd_pd_epid;
-    ZXIC_UINT32 info_rd_pd_vfunc_num;
-    ZXIC_UINT32 info_rd_pd_func_num;
-    ZXIC_UINT32 info_rd_pd_vfunc_active;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_pd_onload_cnt_t
-{
-    ZXIC_UINT32 info_axi_last_rd_pd_onload_cnt;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ONLOAD_CNT_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_axi_rd_pd_resp_err_t
-{
-    ZXIC_UINT32 cnt_axi_rd_pd_resp_err;
-}DPP_DTB_DTB_CFG_CNT_AXI_RD_PD_RESP_ERR_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_high_t
-{
-    ZXIC_UINT32 info_axi_last_wr_ctrl_addr_high;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_HIGH_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_low_t
-{
-    ZXIC_UINT32 info_axi_last_wr_ctrl_addr_low;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_LOW_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ctrl_len_t
-{
-    ZXIC_UINT32 info_axi_last_wr_ctrl_len;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_LEN_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ctrl_user_t
-{
-    ZXIC_UINT32 info_wr_ctrl_user_en;
-    ZXIC_UINT32 info_wr_ctrl_epid;
-    ZXIC_UINT32 info_wr_ctrl_vfunc_num;
-    ZXIC_UINT32 info_wr_ctrl_func_num;
-    ZXIC_UINT32 info_wr_ctrl_vfunc_active;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ctrl_onload_cnt_t
-{
-    ZXIC_UINT32 info_axi_last_wr_ctrl_onload_cnt;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ONLOAD_CNT_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_axi_wr_ctrl_resp_err_t
-{
-    ZXIC_UINT32 cnt_axi_wr_ctrl_resp_err;
-}DPP_DTB_DTB_CFG_CNT_AXI_WR_CTRL_RESP_ERR_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_high_t
-{
-    ZXIC_UINT32 info_axi_last_wr_ddr_addr_high;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_HIGH_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_low_t
-{
-    ZXIC_UINT32 info_axi_last_wr_ddr_addr_low;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_LOW_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ddr_len_t
-{
-    ZXIC_UINT32 info_axi_last_wr_ddr_len;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_LEN_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ddr_user_t
-{
-    ZXIC_UINT32 info_wr_ddr_user_en;
-    ZXIC_UINT32 info_wr_ddr_epid;
-    ZXIC_UINT32 info_wr_ddr_vfunc_num;
-    ZXIC_UINT32 info_wr_ddr_func_num;
-    ZXIC_UINT32 info_wr_ddr_vfunc_active;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ddr_onload_cnt_t
-{
-    ZXIC_UINT32 info_axi_last_wr_ddr_onload_cnt;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ONLOAD_CNT_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_axi_wr_ddr_resp_err_t
-{
-    ZXIC_UINT32 cnt_axi_wr_ddr_resp_err;
-}DPP_DTB_DTB_CFG_CNT_AXI_WR_DDR_RESP_ERR_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_fin_addr_high_t
-{
-    ZXIC_UINT32 info_axi_last_wr_fin_addr_high;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_HIGH_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_fin_addr_low_t
-{
-    ZXIC_UINT32 info_axi_last_wr_fin_addr_low;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_LOW_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_fin_len_t
-{
-    ZXIC_UINT32 info_axi_last_wr_fin_len;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_LEN_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_fin_user_t
-{
-    ZXIC_UINT32 info_wr_fin_user_en;
-    ZXIC_UINT32 info_wr_fin_epid;
-    ZXIC_UINT32 info_wr_fin_vfunc_num;
-    ZXIC_UINT32 info_wr_fin_func_num;
-    ZXIC_UINT32 info_wr_fin_vfunc_active;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_fin_onload_cnt_t
-{
-    ZXIC_UINT32 info_axi_last_wr_fin_onload_cnt;
-}DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ONLOAD_CNT_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_axi_wr_fin_resp_err_t
-{
-    ZXIC_UINT32 cnt_axi_wr_fin_resp_err;
-}DPP_DTB_DTB_CFG_CNT_AXI_WR_FIN_RESP_ERR_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_high_t
-{
-    ZXIC_UINT32 cnt_dtb_wr_smmu0_table_high;
-}DPP_DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_HIGH_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_low_t
-{
-    ZXIC_UINT32 cnt_dtb_wr_smmu0_table_low;
-}DPP_DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_LOW_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_high_t
-{
-    ZXIC_UINT32 cnt_dtb_wr_smmu1_table_high;
-}DPP_DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_HIGH_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_low_t
-{
-    ZXIC_UINT32 cnt_dtb_wr_smmu1_table_low;
-}DPP_DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_LOW_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_high_t
-{
-    ZXIC_UINT32 cnt_dtb_wr_zcam_table_high;
-}DPP_DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_HIGH_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_low_t
-{
-    ZXIC_UINT32 cnt_dtb_wr_zcam_table_low;
-}DPP_DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_LOW_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_high_t
-{
-    ZXIC_UINT32 cnt_dtb_wr_etcam_table_high;
-}DPP_DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_HIGH_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_low_t
-{
-    ZXIC_UINT32 cnt_dtb_wr_etcam_table_low;
-}DPP_DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_LOW_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_hash_table_high_t
-{
-    ZXIC_UINT32 cnt_dtb_wr_hash_table_high;
-}DPP_DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_HIGH_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_hash_table_low_t
-{
-    ZXIC_UINT32 cnt_dtb_wr_hash_table_low;
-}DPP_DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_LOW_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_high_t
-{
-    ZXIC_UINT32 cnt_dtb_rd_smmu0_table_high;
-}DPP_DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_HIGH_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_low_t
-{
-    ZXIC_UINT32 cnt_dtb_rd_smmu0_table_low;
-}DPP_DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_LOW_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_high_t
-{
-    ZXIC_UINT32 cnt_dtb_rd_smmu1_table_high;
-}DPP_DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_HIGH_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_low_t
-{
-    ZXIC_UINT32 cnt_dtb_rd_smmu1_table_low;
-}DPP_DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_LOW_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_high_t
-{
-    ZXIC_UINT32 cnt_dtb_rd_zcam_table_high;
-}DPP_DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_HIGH_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_low_t
-{
-    ZXIC_UINT32 cnt_dtb_rd_zcam_table_low;
-}DPP_DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_LOW_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_high_t
-{
-    ZXIC_UINT32 cnt_dtb_rd_etcam_table_high;
-}DPP_DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_HIGH_T;
-
-typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_low_t
-{
-    ZXIC_UINT32 cnt_dtb_rd_etcam_table_low;
-}DPP_DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_LOW_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_wr_ctrl_state_t
-{
-    ZXIC_UINT32 info_wr_ctrl_state;
-}DPP_DTB_DTB_CFG_INFO_WR_CTRL_STATE_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_rd_table_state_t
-{
-    ZXIC_UINT32 info_rd_table_state;
-}DPP_DTB_DTB_CFG_INFO_RD_TABLE_STATE_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_rd_pd_state_t
-{
-    ZXIC_UINT32 info_rd_pd_state;
-}DPP_DTB_DTB_CFG_INFO_RD_PD_STATE_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_dump_cmd_state_t
-{
-    ZXIC_UINT32 info_dump_cmd_state;
-}DPP_DTB_DTB_CFG_INFO_DUMP_CMD_STATE_T;
-
-typedef struct dpp_dtb_dtb_cfg_info_wr_ddr_state_t
-{
-    ZXIC_UINT32 info_wr_ddr_state;
-}DPP_DTB_DTB_CFG_INFO_WR_DDR_STATE_T;
-
-typedef struct dpp_dtb_dtb_cfg_cfg_dtb_debug_info_clr_t
-{
-    ZXIC_UINT32 cfg_dtb_debug_info_clr;
-}DPP_DTB_DTB_CFG_CFG_DTB_DEBUG_INFO_CLR_T;
-
-typedef struct dpp_dtb_ddos_cfg_ddos_stat_dump_thrd_0_15_t
-{
-    ZXIC_UINT32 cfg_ddos_stat_dump_thrd;
-}DPP_DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_0_15_T;
-
-typedef struct dpp_dtb_ddos_cfg_ddos_stat_dump_thrd_comp_en_t
-{
-    ZXIC_UINT32 cfg_ddos_stat_dump_thrd_comp_en;
-}DPP_DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_COMP_EN_T;
-
-typedef struct dpp_dtb_ddos_cfg_ddos_dump_stat_num_t
-{
-    ZXIC_UINT32 cfg_ddos_dump_stat_num;
-}DPP_DTB_DDOS_CFG_DDOS_DUMP_STAT_NUM_T;
-
-typedef struct dpp_dtb_ddos_cfg_ddos_even_hash_table_baddr_t
-{
-    ZXIC_UINT32 cfg_ddos_even_hash_table_baddr;
-}DPP_DTB_DDOS_CFG_DDOS_EVEN_HASH_TABLE_BADDR_T;
-
-typedef struct dpp_dtb_ddos_cfg_ddos_odd_hash_table_baddr_t
-{
-    ZXIC_UINT32 cfg_ddos_odd_hash_table_baddr;
-}DPP_DTB_DDOS_CFG_DDOS_ODD_HASH_TABLE_BADDR_T;
-
-typedef struct dpp_dtb_ddos_cfg_ddos_stat_index_offset_t
-{
-    ZXIC_UINT32 cfg_ddos_stat_index_offset;
-}DPP_DTB_DDOS_CFG_DDOS_STAT_INDEX_OFFSET_T;
-
-typedef struct dpp_dtb_ddos_cfg_ddos_ns_flag_cnt_t
-{
-    ZXIC_UINT32 cfg_ddos_ns_flag_cnt;
-}DPP_DTB_DDOS_CFG_DDOS_NS_FLAG_CNT_T;
-
-typedef struct dpp_dtb_ddos_cfg_ddos_even_stat_table_baddr_t
-{
-    ZXIC_UINT32 cfg_ddos_even_stat_table_baddr;
-}DPP_DTB_DDOS_CFG_DDOS_EVEN_STAT_TABLE_BADDR_T;
-
-typedef struct dpp_dtb_ddos_cfg_ddos_odd_stat_table_baddr_t
-{
-    ZXIC_UINT32 cfg_ddos_odd_stat_table_baddr;
-}DPP_DTB_DDOS_CFG_DDOS_ODD_STAT_TABLE_BADDR_T;
-
-typedef struct dpp_dtb_ddos_cfg_ddos_even_stat_dump_daddr_h_t
-{
-    ZXIC_UINT32 cfg_ddos_even_stat_dump_daddr_h;
-}DPP_DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_H_T;
-
-typedef struct dpp_dtb_ddos_cfg_ddos_even_stat_dump_daddr_l_t
-{
-    ZXIC_UINT32 cfg_ddos_even_stat_dump_daddr_l;
-}DPP_DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_L_T;
-
-typedef struct dpp_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_h_t
-{
-    ZXIC_UINT32 cfg_ddos_odd_stat_dump_daddr_h;
-}DPP_DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_H_T;
-
-typedef struct dpp_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_l_t
-{
-    ZXIC_UINT32 cfg_ddos_odd_stat_dump_daddr_l;
-}DPP_DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_L_T;
-
-typedef struct dpp_dtb_ddos_cfg_ddos_work_mode_enable_t
-{
-    ZXIC_UINT32 cfg_ddos_mode_work_enable;
-}DPP_DTB_DDOS_CFG_DDOS_WORK_MODE_ENABLE_T;
-
-typedef struct dpp_dtb_ddos_cfg_ddos_stat_table_len_t
-{
-    ZXIC_UINT32 cfg_ddos_stat_table_len;
-}DPP_DTB_DDOS_CFG_DDOS_STAT_TABLE_LEN_T;
-
-typedef struct dpp_dtb_ddos_cfg_ddos_hash_table_len_t
-{
-    ZXIC_UINT32 cfg_ddos_hash_table_len;
-}DPP_DTB_DDOS_CFG_DDOS_HASH_TABLE_LEN_T;
-
-typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram0_0_255_t
-{
-    ZXIC_UINT32 traf_ctrl_ram0_0_255;
-}DPP_DTB_DTB_RAM_TRAF_CTRL_RAM0_0_255_T;
-
-typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram1_0_255_t
-{
-    ZXIC_UINT32 traf_ctrl_ram1_0_255;
-}DPP_DTB_DTB_RAM_TRAF_CTRL_RAM1_0_255_T;
-
-typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram2_0_255_t
-{
-    ZXIC_UINT32 traf_ctrl_ram2_0_255;
-}DPP_DTB_DTB_RAM_TRAF_CTRL_RAM2_0_255_T;
-
-typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram3_0_255_t
-{
-    ZXIC_UINT32 traf_ctrl_ram3_0_255;
-}DPP_DTB_DTB_RAM_TRAF_CTRL_RAM3_0_255_T;
-
-typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram4_0_255_t
-{
-    ZXIC_UINT32 traf_ctrl_ram4_0_255;
-}DPP_DTB_DTB_RAM_TRAF_CTRL_RAM4_0_255_T;
-
-typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram5_0_63_t
-{
-    ZXIC_UINT32 traf_ctrl_ram5_0_63;
-}DPP_DTB_DTB_RAM_TRAF_CTRL_RAM5_0_63_T;
-
-typedef struct dpp_dtb_dtb_ram_dump_pd_ram_0_2047_t
-{
-    ZXIC_UINT32 dump_pd_ram_0_2047;
-}DPP_DTB_DTB_RAM_DUMP_PD_RAM_0_2047_T;
-
-typedef struct dpp_dtb_dtb_ram_rd_ctrl_ram_0_4095_t
-{
-    ZXIC_UINT32 rd_ctrl_ram_0_4095;
-}DPP_DTB_DTB_RAM_RD_CTRL_RAM_0_4095_T;
-
-typedef struct dpp_dtb_dtb_ram_rd_table_ram_0_8191_t
-{
-    ZXIC_UINT32 rd_table_ram_0_8191;
-}DPP_DTB_DTB_RAM_RD_TABLE_RAM_0_8191_T;
-
-typedef struct dpp_dtb_dtb_ram_dtb_cmd_man_ram_0_16383_t
-{
-    ZXIC_UINT32 dtb_cmd_man_ram_0_16383;
-}DPP_DTB_DTB_RAM_DTB_CMD_MAN_RAM_0_16383_T;
+typedef struct dpp_dtb_dtb_cfg_cfg_eram_wr_interval_cnt_t {
+	ZXIC_UINT32 cfg_eram_wr_interval_cnt;
+} DPP_DTB_DTB_CFG_CFG_ERAM_WR_INTERVAL_CNT_T;
 
+typedef struct dpp_dtb_dtb_cfg_cfg_zcam_wr_interval_cnt_t {
+	ZXIC_UINT32 cfg_zcam_wr_interval_cnt;
+} DPP_DTB_DTB_CFG_CFG_ZCAM_WR_INTERVAL_CNT_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_tcam_wr_interval_cnt_t {
+	ZXIC_UINT32 cfg_zcam_wr_interval_cnt;
+} DPP_DTB_DTB_CFG_CFG_TCAM_WR_INTERVAL_CNT_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_ddr_wr_interval_cnt_t {
+	ZXIC_UINT32 cfg_ddr_wr_interval_cnt;
+} DPP_DTB_DTB_CFG_CFG_DDR_WR_INTERVAL_CNT_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_hash_wr_interval_cnt_t {
+	ZXIC_UINT32 cfg_hash_wr_interval_cnt;
+} DPP_DTB_DTB_CFG_CFG_HASH_WR_INTERVAL_CNT_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_eram_rd_interval_cnt_t {
+	ZXIC_UINT32 cfg_eram_rd_interval_cnt;
+} DPP_DTB_DTB_CFG_CFG_ERAM_RD_INTERVAL_CNT_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_zcam_rd_interval_cnt_t {
+	ZXIC_UINT32 cfg_zcam_rd_interval_cnt;
+} DPP_DTB_DTB_CFG_CFG_ZCAM_RD_INTERVAL_CNT_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_tcam_rd_interval_cnt_t {
+	ZXIC_UINT32 cfg_tcam_rd_interval_cnt;
+} DPP_DTB_DTB_CFG_CFG_TCAM_RD_INTERVAL_CNT_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_ddr_rd_interval_cnt_t {
+	ZXIC_UINT32 cfg_ddr_rd_interval_cnt;
+} DPP_DTB_DTB_CFG_CFG_DDR_RD_INTERVAL_CNT_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_dtb_queue_lock_state_0_3_t {
+	ZXIC_UINT32 cfg_dtb_queue_lock_state;
+} DPP_DTB_DTB_CFG_CFG_DTB_QUEUE_LOCK_STATE_0_3_T;
+
+typedef struct dpp_dtb_dtb_axim0_w_convert_0_mode_t {
+	ZXIC_UINT32 w_convert_mode;
+} DPP_DTB_DTB_AXIM0_W_CONVERT_0_MODE_T;
+
+typedef struct dpp_dtb_dtb_axim0_r_convert_0_mode_t {
+	ZXIC_UINT32 r_convert_mode;
+} DPP_DTB_DTB_AXIM0_R_CONVERT_0_MODE_T;
+
+typedef struct dpp_dtb_dtb_axim0_aximr_os_t {
+	ZXIC_UINT32 aximr_os;
+} DPP_DTB_DTB_AXIM0_AXIMR_OS_T;
+
+typedef struct dpp_dtb_dtb_axim1_w_convert_1_mode_t {
+	ZXIC_UINT32 w_convert_mode;
+} DPP_DTB_DTB_AXIM1_W_CONVERT_1_MODE_T;
+
+typedef struct dpp_dtb_dtb_axim1_r_convert_1_mode_t {
+	ZXIC_UINT32 r_convert_mode;
+} DPP_DTB_DTB_AXIM1_R_CONVERT_1_MODE_T;
+
+typedef struct dpp_dtb_dtb_axis_axis_convert_mode_t {
+	ZXIC_UINT32 w_r_convert_mode;
+} DPP_DTB_DTB_AXIS_AXIS_CONVERT_MODE_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_event0_t {
+	ZXIC_UINT32 cfg_finish_int_event0;
+} DPP_DTB_DTB_CFG_CFG_FINISH_INT_EVENT0_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_event1_t {
+	ZXIC_UINT32 cfg_finish_int_event1;
+} DPP_DTB_DTB_CFG_CFG_FINISH_INT_EVENT1_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_event2_t {
+	ZXIC_UINT32 cfg_finish_int_event2;
+} DPP_DTB_DTB_CFG_CFG_FINISH_INT_EVENT2_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_event3_t {
+	ZXIC_UINT32 cfg_finish_int_event3;
+} DPP_DTB_DTB_CFG_CFG_FINISH_INT_EVENT3_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_maks0_t {
+	ZXIC_UINT32 cfg_finish_int_mask0;
+} DPP_DTB_DTB_CFG_CFG_FINISH_INT_MAKS0_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_maks1_t {
+	ZXIC_UINT32 cfg_finish_int_mask1;
+} DPP_DTB_DTB_CFG_CFG_FINISH_INT_MAKS1_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_maks2_t {
+	ZXIC_UINT32 cfg_finish_int_mask2;
+} DPP_DTB_DTB_CFG_CFG_FINISH_INT_MAKS2_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_maks3_t {
+	ZXIC_UINT32 cfg_finish_int_mask3;
+} DPP_DTB_DTB_CFG_CFG_FINISH_INT_MAKS3_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_test0_t {
+	ZXIC_UINT32 cfg_finish_int_test0;
+} DPP_DTB_DTB_CFG_CFG_FINISH_INT_TEST0_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_test1_t {
+	ZXIC_UINT32 cfg_finish_int_test1;
+} DPP_DTB_DTB_CFG_CFG_FINISH_INT_TEST1_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_test2_t {
+	ZXIC_UINT32 cfg_finish_int_test2;
+} DPP_DTB_DTB_CFG_CFG_FINISH_INT_TEST2_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_finish_int_test3_t {
+	ZXIC_UINT32 cfg_finish_int_test3;
+} DPP_DTB_DTB_CFG_CFG_FINISH_INT_TEST3_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_dtb_int_to_riscv_sel_t {
+	ZXIC_UINT32 cfg_dtb_int_to_riscv_sel0;
+} DPP_DTB_DTB_CFG_CFG_DTB_INT_TO_RISCV_SEL_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_dtb_ep_int_msix_enable_t {
+	ZXIC_UINT32 cfg_dtb_ep_int_msix_enable;
+} DPP_DTB_DTB_CFG_CFG_DTB_EP_INT_MSIX_ENABLE_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_h_0_15_t {
+	ZXIC_UINT32 cfg_dtb_ep_doorbell_addr_h_0_15;
+} DPP_DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_H_0_15_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_l_0_15_t {
+	ZXIC_UINT32 cfg_dtb_ep_doorbell_addr_l_0_15;
+} DPP_DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_L_0_15_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_dtb_debug_mode_en_t {
+	ZXIC_UINT32 cfg_dtb_debug_mode_en;
+} DPP_DTB_DTB_CFG_CFG_DTB_DEBUG_MODE_EN_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_table_addr_high_t {
+	ZXIC_UINT32 info_axi_last_rd_table_addr_high;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_HIGH_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_table_addr_low_t {
+	ZXIC_UINT32 info_axi_last_rd_table_addr_low;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_LOW_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_table_len_t {
+	ZXIC_UINT32 info_axi_last_rd_table_len;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_LEN_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_table_user_t {
+	ZXIC_UINT32 info_rd_table_user_en;
+	ZXIC_UINT32 info_rd_table_epid;
+	ZXIC_UINT32 info_rd_table_vfunc_num;
+	ZXIC_UINT32 info_rd_table_func_num;
+	ZXIC_UINT32 info_rd_table_vfunc_active;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_table_onload_cnt_t {
+	ZXIC_UINT32 info_axi_last_rd_table_onload_cnt;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ONLOAD_CNT_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_axi_rd_table_resp_err_t {
+	ZXIC_UINT32 cnt_axi_rd_table_resp_err;
+} DPP_DTB_DTB_CFG_CNT_AXI_RD_TABLE_RESP_ERR_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_pd_addr_high_t {
+	ZXIC_UINT32 info_axi_last_rd_pd_addr_high;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_HIGH_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_pd_addr_low_t {
+	ZXIC_UINT32 info_axi_last_rd_pd_addr_low;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_LOW_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_pd_len_t {
+	ZXIC_UINT32 info_axi_last_rd_pd_len;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_LEN_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_pd_user_t {
+	ZXIC_UINT32 info_rd_pd_user_en;
+	ZXIC_UINT32 info_rd_pd_epid;
+	ZXIC_UINT32 info_rd_pd_vfunc_num;
+	ZXIC_UINT32 info_rd_pd_func_num;
+	ZXIC_UINT32 info_rd_pd_vfunc_active;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_rd_pd_onload_cnt_t {
+	ZXIC_UINT32 info_axi_last_rd_pd_onload_cnt;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ONLOAD_CNT_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_axi_rd_pd_resp_err_t {
+	ZXIC_UINT32 cnt_axi_rd_pd_resp_err;
+} DPP_DTB_DTB_CFG_CNT_AXI_RD_PD_RESP_ERR_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_high_t {
+	ZXIC_UINT32 info_axi_last_wr_ctrl_addr_high;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_HIGH_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_low_t {
+	ZXIC_UINT32 info_axi_last_wr_ctrl_addr_low;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_LOW_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ctrl_len_t {
+	ZXIC_UINT32 info_axi_last_wr_ctrl_len;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_LEN_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ctrl_user_t {
+	ZXIC_UINT32 info_wr_ctrl_user_en;
+	ZXIC_UINT32 info_wr_ctrl_epid;
+	ZXIC_UINT32 info_wr_ctrl_vfunc_num;
+	ZXIC_UINT32 info_wr_ctrl_func_num;
+	ZXIC_UINT32 info_wr_ctrl_vfunc_active;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ctrl_onload_cnt_t {
+	ZXIC_UINT32 info_axi_last_wr_ctrl_onload_cnt;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ONLOAD_CNT_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_axi_wr_ctrl_resp_err_t {
+	ZXIC_UINT32 cnt_axi_wr_ctrl_resp_err;
+} DPP_DTB_DTB_CFG_CNT_AXI_WR_CTRL_RESP_ERR_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_high_t {
+	ZXIC_UINT32 info_axi_last_wr_ddr_addr_high;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_HIGH_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_low_t {
+	ZXIC_UINT32 info_axi_last_wr_ddr_addr_low;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_LOW_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ddr_len_t {
+	ZXIC_UINT32 info_axi_last_wr_ddr_len;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_LEN_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ddr_user_t {
+	ZXIC_UINT32 info_wr_ddr_user_en;
+	ZXIC_UINT32 info_wr_ddr_epid;
+	ZXIC_UINT32 info_wr_ddr_vfunc_num;
+	ZXIC_UINT32 info_wr_ddr_func_num;
+	ZXIC_UINT32 info_wr_ddr_vfunc_active;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_ddr_onload_cnt_t {
+	ZXIC_UINT32 info_axi_last_wr_ddr_onload_cnt;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ONLOAD_CNT_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_axi_wr_ddr_resp_err_t {
+	ZXIC_UINT32 cnt_axi_wr_ddr_resp_err;
+} DPP_DTB_DTB_CFG_CNT_AXI_WR_DDR_RESP_ERR_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_fin_addr_high_t {
+	ZXIC_UINT32 info_axi_last_wr_fin_addr_high;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_HIGH_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_fin_addr_low_t {
+	ZXIC_UINT32 info_axi_last_wr_fin_addr_low;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_LOW_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_fin_len_t {
+	ZXIC_UINT32 info_axi_last_wr_fin_len;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_LEN_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_fin_user_t {
+	ZXIC_UINT32 info_wr_fin_user_en;
+	ZXIC_UINT32 info_wr_fin_epid;
+	ZXIC_UINT32 info_wr_fin_vfunc_num;
+	ZXIC_UINT32 info_wr_fin_func_num;
+	ZXIC_UINT32 info_wr_fin_vfunc_active;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_axi_last_wr_fin_onload_cnt_t {
+	ZXIC_UINT32 info_axi_last_wr_fin_onload_cnt;
+} DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ONLOAD_CNT_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_axi_wr_fin_resp_err_t {
+	ZXIC_UINT32 cnt_axi_wr_fin_resp_err;
+} DPP_DTB_DTB_CFG_CNT_AXI_WR_FIN_RESP_ERR_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_high_t {
+	ZXIC_UINT32 cnt_dtb_wr_smmu0_table_high;
+} DPP_DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_HIGH_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_low_t {
+	ZXIC_UINT32 cnt_dtb_wr_smmu0_table_low;
+} DPP_DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_LOW_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_high_t {
+	ZXIC_UINT32 cnt_dtb_wr_smmu1_table_high;
+} DPP_DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_HIGH_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_low_t {
+	ZXIC_UINT32 cnt_dtb_wr_smmu1_table_low;
+} DPP_DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_LOW_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_high_t {
+	ZXIC_UINT32 cnt_dtb_wr_zcam_table_high;
+} DPP_DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_HIGH_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_low_t {
+	ZXIC_UINT32 cnt_dtb_wr_zcam_table_low;
+} DPP_DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_LOW_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_high_t {
+	ZXIC_UINT32 cnt_dtb_wr_etcam_table_high;
+} DPP_DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_HIGH_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_low_t {
+	ZXIC_UINT32 cnt_dtb_wr_etcam_table_low;
+} DPP_DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_LOW_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_hash_table_high_t {
+	ZXIC_UINT32 cnt_dtb_wr_hash_table_high;
+} DPP_DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_HIGH_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_wr_hash_table_low_t {
+	ZXIC_UINT32 cnt_dtb_wr_hash_table_low;
+} DPP_DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_LOW_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_high_t {
+	ZXIC_UINT32 cnt_dtb_rd_smmu0_table_high;
+} DPP_DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_HIGH_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_low_t {
+	ZXIC_UINT32 cnt_dtb_rd_smmu0_table_low;
+} DPP_DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_LOW_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_high_t {
+	ZXIC_UINT32 cnt_dtb_rd_smmu1_table_high;
+} DPP_DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_HIGH_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_low_t {
+	ZXIC_UINT32 cnt_dtb_rd_smmu1_table_low;
+} DPP_DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_LOW_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_high_t {
+	ZXIC_UINT32 cnt_dtb_rd_zcam_table_high;
+} DPP_DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_HIGH_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_low_t {
+	ZXIC_UINT32 cnt_dtb_rd_zcam_table_low;
+} DPP_DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_LOW_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_high_t {
+	ZXIC_UINT32 cnt_dtb_rd_etcam_table_high;
+} DPP_DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_HIGH_T;
+
+typedef struct dpp_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_low_t {
+	ZXIC_UINT32 cnt_dtb_rd_etcam_table_low;
+} DPP_DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_LOW_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_wr_ctrl_state_t {
+	ZXIC_UINT32 info_wr_ctrl_state;
+} DPP_DTB_DTB_CFG_INFO_WR_CTRL_STATE_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_rd_table_state_t {
+	ZXIC_UINT32 info_rd_table_state;
+} DPP_DTB_DTB_CFG_INFO_RD_TABLE_STATE_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_rd_pd_state_t {
+	ZXIC_UINT32 info_rd_pd_state;
+} DPP_DTB_DTB_CFG_INFO_RD_PD_STATE_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_dump_cmd_state_t {
+	ZXIC_UINT32 info_dump_cmd_state;
+} DPP_DTB_DTB_CFG_INFO_DUMP_CMD_STATE_T;
+
+typedef struct dpp_dtb_dtb_cfg_info_wr_ddr_state_t {
+	ZXIC_UINT32 info_wr_ddr_state;
+} DPP_DTB_DTB_CFG_INFO_WR_DDR_STATE_T;
+
+typedef struct dpp_dtb_dtb_cfg_cfg_dtb_debug_info_clr_t {
+	ZXIC_UINT32 cfg_dtb_debug_info_clr;
+} DPP_DTB_DTB_CFG_CFG_DTB_DEBUG_INFO_CLR_T;
+
+typedef struct dpp_dtb_ddos_cfg_ddos_stat_dump_thrd_0_15_t {
+	ZXIC_UINT32 cfg_ddos_stat_dump_thrd;
+} DPP_DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_0_15_T;
+
+typedef struct dpp_dtb_ddos_cfg_ddos_stat_dump_thrd_comp_en_t {
+	ZXIC_UINT32 cfg_ddos_stat_dump_thrd_comp_en;
+} DPP_DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_COMP_EN_T;
+
+typedef struct dpp_dtb_ddos_cfg_ddos_dump_stat_num_t {
+	ZXIC_UINT32 cfg_ddos_dump_stat_num;
+} DPP_DTB_DDOS_CFG_DDOS_DUMP_STAT_NUM_T;
+
+typedef struct dpp_dtb_ddos_cfg_ddos_even_hash_table_baddr_t {
+	ZXIC_UINT32 cfg_ddos_even_hash_table_baddr;
+} DPP_DTB_DDOS_CFG_DDOS_EVEN_HASH_TABLE_BADDR_T;
+
+typedef struct dpp_dtb_ddos_cfg_ddos_odd_hash_table_baddr_t {
+	ZXIC_UINT32 cfg_ddos_odd_hash_table_baddr;
+} DPP_DTB_DDOS_CFG_DDOS_ODD_HASH_TABLE_BADDR_T;
+
+typedef struct dpp_dtb_ddos_cfg_ddos_stat_index_offset_t {
+	ZXIC_UINT32 cfg_ddos_stat_index_offset;
+} DPP_DTB_DDOS_CFG_DDOS_STAT_INDEX_OFFSET_T;
+
+typedef struct dpp_dtb_ddos_cfg_ddos_ns_flag_cnt_t {
+	ZXIC_UINT32 cfg_ddos_ns_flag_cnt;
+} DPP_DTB_DDOS_CFG_DDOS_NS_FLAG_CNT_T;
+
+typedef struct dpp_dtb_ddos_cfg_ddos_even_stat_table_baddr_t {
+	ZXIC_UINT32 cfg_ddos_even_stat_table_baddr;
+} DPP_DTB_DDOS_CFG_DDOS_EVEN_STAT_TABLE_BADDR_T;
+
+typedef struct dpp_dtb_ddos_cfg_ddos_odd_stat_table_baddr_t {
+	ZXIC_UINT32 cfg_ddos_odd_stat_table_baddr;
+} DPP_DTB_DDOS_CFG_DDOS_ODD_STAT_TABLE_BADDR_T;
+
+typedef struct dpp_dtb_ddos_cfg_ddos_even_stat_dump_daddr_h_t {
+	ZXIC_UINT32 cfg_ddos_even_stat_dump_daddr_h;
+} DPP_DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_H_T;
+
+typedef struct dpp_dtb_ddos_cfg_ddos_even_stat_dump_daddr_l_t {
+	ZXIC_UINT32 cfg_ddos_even_stat_dump_daddr_l;
+} DPP_DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_L_T;
+
+typedef struct dpp_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_h_t {
+	ZXIC_UINT32 cfg_ddos_odd_stat_dump_daddr_h;
+} DPP_DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_H_T;
+
+typedef struct dpp_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_l_t {
+	ZXIC_UINT32 cfg_ddos_odd_stat_dump_daddr_l;
+} DPP_DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_L_T;
+
+typedef struct dpp_dtb_ddos_cfg_ddos_work_mode_enable_t {
+	ZXIC_UINT32 cfg_ddos_mode_work_enable;
+} DPP_DTB_DDOS_CFG_DDOS_WORK_MODE_ENABLE_T;
+
+typedef struct dpp_dtb_ddos_cfg_ddos_stat_table_len_t {
+	ZXIC_UINT32 cfg_ddos_stat_table_len;
+} DPP_DTB_DDOS_CFG_DDOS_STAT_TABLE_LEN_T;
+
+typedef struct dpp_dtb_ddos_cfg_ddos_hash_table_len_t {
+	ZXIC_UINT32 cfg_ddos_hash_table_len;
+} DPP_DTB_DDOS_CFG_DDOS_HASH_TABLE_LEN_T;
+
+typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram0_0_255_t {
+	ZXIC_UINT32 traf_ctrl_ram0_0_255;
+} DPP_DTB_DTB_RAM_TRAF_CTRL_RAM0_0_255_T;
+
+typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram1_0_255_t {
+	ZXIC_UINT32 traf_ctrl_ram1_0_255;
+} DPP_DTB_DTB_RAM_TRAF_CTRL_RAM1_0_255_T;
+
+typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram2_0_255_t {
+	ZXIC_UINT32 traf_ctrl_ram2_0_255;
+} DPP_DTB_DTB_RAM_TRAF_CTRL_RAM2_0_255_T;
+
+typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram3_0_255_t {
+	ZXIC_UINT32 traf_ctrl_ram3_0_255;
+} DPP_DTB_DTB_RAM_TRAF_CTRL_RAM3_0_255_T;
+
+typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram4_0_255_t {
+	ZXIC_UINT32 traf_ctrl_ram4_0_255;
+} DPP_DTB_DTB_RAM_TRAF_CTRL_RAM4_0_255_T;
+
+typedef struct dpp_dtb_dtb_ram_traf_ctrl_ram5_0_63_t {
+	ZXIC_UINT32 traf_ctrl_ram5_0_63;
+} DPP_DTB_DTB_RAM_TRAF_CTRL_RAM5_0_63_T;
+
+typedef struct dpp_dtb_dtb_ram_dump_pd_ram_0_2047_t {
+	ZXIC_UINT32 dump_pd_ram_0_2047;
+} DPP_DTB_DTB_RAM_DUMP_PD_RAM_0_2047_T;
+
+typedef struct dpp_dtb_dtb_ram_rd_ctrl_ram_0_4095_t {
+	ZXIC_UINT32 rd_ctrl_ram_0_4095;
+} DPP_DTB_DTB_RAM_RD_CTRL_RAM_0_4095_T;
+
+typedef struct dpp_dtb_dtb_ram_rd_table_ram_0_8191_t {
+	ZXIC_UINT32 rd_table_ram_0_8191;
+} DPP_DTB_DTB_RAM_RD_TABLE_RAM_0_8191_T;
+
+typedef struct dpp_dtb_dtb_ram_dtb_cmd_man_ram_0_16383_t {
+	ZXIC_UINT32 dtb_cmd_man_ram_0_16383;
+} DPP_DTB_DTB_RAM_DTB_CMD_MAN_RAM_0_16383_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_etm_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_etm_reg.h
index 60d749114df8b17330af52ac4111d0833649a904..480d67074f619fd8ae8d86cf753e8404e255cb3c 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_etm_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_etm_reg.h
@@ -3,4924 +3,4054 @@
 #define _DPP_ETM_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_etm_cfgmt_cpu_check_reg_t
-{
-    ZXIC_UINT32 cpu_check_reg;
-}DPP_ETM_CFGMT_CPU_CHECK_REG_T;
-
-typedef struct dpp_etm_cfgmt_cfgmt_blksize_t
-{
-    ZXIC_UINT32 cfgmt_blksize;
-}DPP_ETM_CFGMT_CFGMT_BLKSIZE_T;
-
-typedef struct dpp_etm_cfgmt_reg_int_state_reg_t
-{
-    ZXIC_UINT32 shap_int;
-    ZXIC_UINT32 crdt_int;
-    ZXIC_UINT32 mmu_int;
-    ZXIC_UINT32 qmu_int;
-    ZXIC_UINT32 cgavd_int;
-    ZXIC_UINT32 olif_int;
-    ZXIC_UINT32 cfgmt_int_buf;
-}DPP_ETM_CFGMT_REG_INT_STATE_REG_T;
-
-typedef struct dpp_etm_cfgmt_reg_int_mask_reg_t
-{
-    ZXIC_UINT32 shap_int_mask;
-    ZXIC_UINT32 crdt_int_mask;
-    ZXIC_UINT32 tmmu_int_mask;
-    ZXIC_UINT32 qmu_int_mask;
-    ZXIC_UINT32 cgavd_int_mask;
-    ZXIC_UINT32 olif_int_mask;
-    ZXIC_UINT32 cfgmt_int_buf_mask;
-}DPP_ETM_CFGMT_REG_INT_MASK_REG_T;
-
-typedef struct dpp_etm_cfgmt_timeout_limit_t
-{
-    ZXIC_UINT32 timeout_limit;
-}DPP_ETM_CFGMT_TIMEOUT_LIMIT_T;
-
-typedef struct dpp_etm_cfgmt_subsystem_rdy_reg_t
-{
-    ZXIC_UINT32 olif_rdy;
-    ZXIC_UINT32 qmu_rdy;
-    ZXIC_UINT32 cgavd_rdy;
-    ZXIC_UINT32 tmmu_rdy;
-    ZXIC_UINT32 shap_rdy;
-    ZXIC_UINT32 crdt_rdy;
-}DPP_ETM_CFGMT_SUBSYSTEM_RDY_REG_T;
-
-typedef struct dpp_etm_cfgmt_subsystem_en_reg_t
-{
-    ZXIC_UINT32 subsystem_en_buf_31_28;
-    ZXIC_UINT32 subsystem_en_buf_25_0;
-}DPP_ETM_CFGMT_SUBSYSTEM_EN_REG_T;
-
-typedef struct dpp_etm_cfgmt_cfgmt_int_reg_t
-{
-    ZXIC_UINT32 cfgmt_int_buf;
-}DPP_ETM_CFGMT_CFGMT_INT_REG_T;
-
-typedef struct dpp_etm_cfgmt_qmu_work_mode_t
-{
-    ZXIC_UINT32 qmu_work_mode;
-}DPP_ETM_CFGMT_QMU_WORK_MODE_T;
-
-typedef struct dpp_etm_cfgmt_cfgmt_ddr_attach_t
-{
-    ZXIC_UINT32 cfgmt_ddr_attach;
-}DPP_ETM_CFGMT_CFGMT_DDR_ATTACH_T;
-
-typedef struct dpp_etm_cfgmt_cnt_mode_reg_t
-{
-    ZXIC_UINT32 cfgmt_fc_count_mode;
-    ZXIC_UINT32 cfgmt_count_rd_mode;
-    ZXIC_UINT32 cfgmt_count_overflow_mode;
-}DPP_ETM_CFGMT_CNT_MODE_REG_T;
-
-typedef struct dpp_etm_cfgmt_clkgate_en_t
-{
-    ZXIC_UINT32 clkgate_en;
-}DPP_ETM_CFGMT_CLKGATE_EN_T;
-
-typedef struct dpp_etm_cfgmt_softrst_en_t
-{
-    ZXIC_UINT32 softrst_en;
-}DPP_ETM_CFGMT_SOFTRST_EN_T;
-
-typedef struct dpp_etm_olif_imem_prog_full_t
-{
-    ZXIC_UINT32 imem_prog_full_assert;
-    ZXIC_UINT32 imem_prog_full_negate;
-}DPP_ETM_OLIF_IMEM_PROG_FULL_T;
-
-typedef struct dpp_etm_olif_qmu_para_prog_full_t
-{
-    ZXIC_UINT32 qmu_para_prog_full_assert;
-    ZXIC_UINT32 qmu_para_prog_full_negate;
-}DPP_ETM_OLIF_QMU_PARA_PROG_FULL_T;
-
-typedef struct dpp_etm_olif_olif_int_mask_t
-{
-    ZXIC_UINT32 emem_dat_sop_err_mask;
-    ZXIC_UINT32 emem_dat_eop_err_mask;
-    ZXIC_UINT32 imem_dat_sop_err_mask;
-    ZXIC_UINT32 imem_dat_eop_err_mask;
-    ZXIC_UINT32 crcram_parity_err_mask;
-    ZXIC_UINT32 emem_fifo_ecc_mask;
-    ZXIC_UINT32 imem_fifo_ecc_mask;
-    ZXIC_UINT32 emem_fifo_ovf_mask;
-    ZXIC_UINT32 emem_fifo_udf_mask;
-    ZXIC_UINT32 imem_fifo_ovf_mask;
-    ZXIC_UINT32 imem_fifo_udf_mask;
-    ZXIC_UINT32 para_fifo_ecc_mask;
-    ZXIC_UINT32 para_fifo_ovf_mask;
-    ZXIC_UINT32 para_fifo_udf_mask;
-    ZXIC_UINT32 itmh_ecc_single_err_mask;
-    ZXIC_UINT32 itmh_ecc_double_err_mask;
-    ZXIC_UINT32 order_fifo_parity_err_mask;
-    ZXIC_UINT32 order_fifo_ovf_mask;
-    ZXIC_UINT32 order_fifo_udf_mask;
-}DPP_ETM_OLIF_OLIF_INT_MASK_T;
-
-typedef struct dpp_etm_olif_itmhram_parity_err_2_int_t
-{
-    ZXIC_UINT32 emem_dat_sop_err;
-    ZXIC_UINT32 emem_dat_eop_err;
-    ZXIC_UINT32 imem_dat_sop_err;
-    ZXIC_UINT32 imem_dat_eop_err;
-    ZXIC_UINT32 crcram_parity_err_1_int;
-    ZXIC_UINT32 emem_fifo_ecc_single_err_int;
-    ZXIC_UINT32 emem_fifo_ecc_double_err_int;
-    ZXIC_UINT32 imem_fifo_ecc_single_err_int;
-    ZXIC_UINT32 imem_fifo_ecc_double_err_int;
-    ZXIC_UINT32 emem_fifo_ovf_int;
-    ZXIC_UINT32 emem_fifo_udf_int;
-    ZXIC_UINT32 imem_fifo_ovf_int;
-    ZXIC_UINT32 imem_fifo_udf_int;
-    ZXIC_UINT32 para_fifo_ecc_single_err_int;
-    ZXIC_UINT32 para_fifo_ecc_double_err_int;
-    ZXIC_UINT32 para_fifo_ovf_int;
-    ZXIC_UINT32 para_fifo_udf_int;
-    ZXIC_UINT32 itmh_ecc_single_err_int;
-    ZXIC_UINT32 itmh_ecc_double_err_int;
-    ZXIC_UINT32 order_fifo_parity_err_int;
-    ZXIC_UINT32 order_fifo_ovf_int;
-    ZXIC_UINT32 order_fifo_udf_int;
-}DPP_ETM_OLIF_ITMHRAM_PARITY_ERR_2_INT_T;
-
-typedef struct dpp_etm_olif_lif0_port_rdy_mask_h_t
-{
-    ZXIC_UINT32 lif0_port_rdy_mask_h;
-}DPP_ETM_OLIF_LIF0_PORT_RDY_MASK_H_T;
-
-typedef struct dpp_etm_olif_lif0_port_rdy_mask_l_t
-{
-    ZXIC_UINT32 lif0_port_rdy_mask_l;
-}DPP_ETM_OLIF_LIF0_PORT_RDY_MASK_L_T;
-
-typedef struct dpp_etm_olif_lif0_port_rdy_cfg_h_t
-{
-    ZXIC_UINT32 lif0_port_rdy_cfg_h;
-}DPP_ETM_OLIF_LIF0_PORT_RDY_CFG_H_T;
-
-typedef struct dpp_etm_olif_lif0_port_rdy_cfg_l_t
-{
-    ZXIC_UINT32 lif0_port_rdy_cfg_l;
-}DPP_ETM_OLIF_LIF0_PORT_RDY_CFG_L_T;
-
-typedef struct dpp_etm_olif_lif0_link_rdy_mask_cfg_t
-{
-    ZXIC_UINT32 lif0_link_rdy_mask;
-    ZXIC_UINT32 lif0_link_rdy_cfg;
-}DPP_ETM_OLIF_LIF0_LINK_RDY_MASK_CFG_T;
-
-typedef struct dpp_etm_olif_tm_lif_stat_cfg_t
-{
-    ZXIC_UINT32 all_or_by_port;
-    ZXIC_UINT32 i_or_e_sel;
-    ZXIC_UINT32 port_or_dest_id_sel;
-    ZXIC_UINT32 port_dest_id;
-}DPP_ETM_OLIF_TM_LIF_STAT_CFG_T;
-
-typedef struct dpp_etm_olif_tm_lif_sop_stat_t
-{
-    ZXIC_UINT32 tm_lif_sop_stat;
-}DPP_ETM_OLIF_TM_LIF_SOP_STAT_T;
-
-typedef struct dpp_etm_olif_tm_lif_eop_stat_t
-{
-    ZXIC_UINT32 tm_lif_eop_stat;
-}DPP_ETM_OLIF_TM_LIF_EOP_STAT_T;
-
-typedef struct dpp_etm_olif_tm_lif_vld_stat_t
-{
-    ZXIC_UINT32 tm_lif_vld_stat;
-}DPP_ETM_OLIF_TM_LIF_VLD_STAT_T;
-
-typedef struct dpp_etm_cgavd_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 prog_full_assert_cfg;
-    ZXIC_UINT32 prog_full_negate_cfg;
-}DPP_ETM_CGAVD_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_etm_cgavd_cgavd_int_t
-{
-    ZXIC_UINT32 cgavd_int;
-}DPP_ETM_CGAVD_CGAVD_INT_T;
-
-typedef struct dpp_etm_cgavd_cgavd_ram_err_t
-{
-    ZXIC_UINT32 flow_qnum_intb;
-    ZXIC_UINT32 flow_qnum_inta;
-    ZXIC_UINT32 pp_qlen_inta;
-    ZXIC_UINT32 pp_qlen_intb;
-    ZXIC_UINT32 pp_tdth_int;
-    ZXIC_UINT32 flow_tdth_inta;
-    ZXIC_UINT32 flow_tdth_intb;
-    ZXIC_UINT32 flow_qlen_inta;
-    ZXIC_UINT32 flow_qlen_intb;
-    ZXIC_UINT32 qmu_cgavd_fifo_uv_int;
-    ZXIC_UINT32 qmu_cgavd_fifo_ov_int;
-    ZXIC_UINT32 pds_deal_fifo_ov_int;
-    ZXIC_UINT32 pds_deal_fifo_uv_int;
-}DPP_ETM_CGAVD_CGAVD_RAM_ERR_T;
-
-typedef struct dpp_etm_cgavd_cgavd_int_mask_t
-{
-    ZXIC_UINT32 cgavd_int_mask;
-}DPP_ETM_CGAVD_CGAVD_INT_MASK_T;
-
-typedef struct dpp_etm_cgavd_cgavd_ram_err_int_mask_t
-{
-    ZXIC_UINT32 flow_qnum_inta_mask;
-    ZXIC_UINT32 flow_qnum_intb_mask;
-    ZXIC_UINT32 pp_qlen_inta_mask;
-    ZXIC_UINT32 pp_qlen_intb_mask;
-    ZXIC_UINT32 pp_tdth_int_mask;
-    ZXIC_UINT32 flow_tdth_inta_mask;
-    ZXIC_UINT32 flow_tdth_intb_mask;
-    ZXIC_UINT32 flow_qlen_inta_mask;
-    ZXIC_UINT32 flow_qlen_intb_mask;
-    ZXIC_UINT32 qmu_cgavd_fifo_uv_int_mask;
-    ZXIC_UINT32 qmu_cgavd_fifo_ov_int_mask;
-    ZXIC_UINT32 pds_deal_fifo_ov_int_mask;
-    ZXIC_UINT32 pds_deal_fifo_uv_int_mask;
-}DPP_ETM_CGAVD_CGAVD_RAM_ERR_INT_MASK_T;
-
-typedef struct dpp_etm_cgavd_cfgmt_byte_mode_t
-{
-    ZXIC_UINT32 cfgmt_byte_mode;
-}DPP_ETM_CGAVD_CFGMT_BYTE_MODE_T;
-
-typedef struct dpp_etm_cgavd_avg_qlen_return_zero_en_t
-{
-    ZXIC_UINT32 avg_qlen_return_zero_en;
-}DPP_ETM_CGAVD_AVG_QLEN_RETURN_ZERO_EN_T;
-
-typedef struct dpp_etm_cgavd_flow_wred_q_len_th_t
-{
-    ZXIC_UINT32 flow_wred_q_len_th;
-}DPP_ETM_CGAVD_FLOW_WRED_Q_LEN_TH_T;
-
-typedef struct dpp_etm_cgavd_flow_wq_t
-{
-    ZXIC_UINT32 wq_flow;
-}DPP_ETM_CGAVD_FLOW_WQ_T;
-
-typedef struct dpp_etm_cgavd_flow_wred_max_th_t
-{
-    ZXIC_UINT32 flow_wred_max_th;
-}DPP_ETM_CGAVD_FLOW_WRED_MAX_TH_T;
-
-typedef struct dpp_etm_cgavd_flow_wred_min_th_t
-{
-    ZXIC_UINT32 flow_wred_min_th;
-}DPP_ETM_CGAVD_FLOW_WRED_MIN_TH_T;
-
-typedef struct dpp_etm_cgavd_flow_wred_cfg_para_t
-{
-    ZXIC_UINT32 flow_wred_cfg_para;
-}DPP_ETM_CGAVD_FLOW_WRED_CFG_PARA_T;
-
-typedef struct dpp_etm_cgavd_pp_avg_q_len_t
-{
-    ZXIC_UINT32 pp_avg_q_len;
-}DPP_ETM_CGAVD_PP_AVG_Q_LEN_T;
-
-typedef struct dpp_etm_cgavd_pp_td_th_t
-{
-    ZXIC_UINT32 pp_td_th;
-}DPP_ETM_CGAVD_PP_TD_TH_T;
-
-typedef struct dpp_etm_cgavd_pp_ca_mtd_t
-{
-    ZXIC_UINT32 pp_ca_mtd;
-}DPP_ETM_CGAVD_PP_CA_MTD_T;
-
-typedef struct dpp_etm_cgavd_pp_wred_grp_th_en_t
-{
-    ZXIC_UINT32 pp_wred_grp;
-    ZXIC_UINT32 pp_wred_grp_th_en;
-}DPP_ETM_CGAVD_PP_WRED_GRP_TH_EN_T;
-
-typedef struct dpp_etm_cgavd_pp_wred_q_len_th_t
-{
-    ZXIC_UINT32 pp_wred_q_len_th;
-}DPP_ETM_CGAVD_PP_WRED_Q_LEN_TH_T;
-
-typedef struct dpp_etm_cgavd_pp_wq_t
-{
-    ZXIC_UINT32 wq_pp;
-}DPP_ETM_CGAVD_PP_WQ_T;
-
-typedef struct dpp_etm_cgavd_pp_wred_max_th_t
-{
-    ZXIC_UINT32 pp_wred_max_th;
-}DPP_ETM_CGAVD_PP_WRED_MAX_TH_T;
-
-typedef struct dpp_etm_cgavd_pp_wred_min_th_t
-{
-    ZXIC_UINT32 pp_wred_min_th;
-}DPP_ETM_CGAVD_PP_WRED_MIN_TH_T;
-
-typedef struct dpp_etm_cgavd_pp_cfg_para_t
-{
-    ZXIC_UINT32 pp_cfg_para;
-}DPP_ETM_CGAVD_PP_CFG_PARA_T;
-
-typedef struct dpp_etm_cgavd_sys_avg_q_len_t
-{
-    ZXIC_UINT32 sys_avg_q_len;
-}DPP_ETM_CGAVD_SYS_AVG_Q_LEN_T;
-
-typedef struct dpp_etm_cgavd_sys_td_th_t
-{
-    ZXIC_UINT32 sys_td_th;
-}DPP_ETM_CGAVD_SYS_TD_TH_T;
-
-typedef struct dpp_etm_cgavd_sys_cgavd_metd_t
-{
-    ZXIC_UINT32 sys_cgavd_metd;
-}DPP_ETM_CGAVD_SYS_CGAVD_METD_T;
-
-typedef struct dpp_etm_cgavd_sys_cfg_q_grp_para_t
-{
-    ZXIC_UINT32 gred_q_len_th_sys;
-}DPP_ETM_CGAVD_SYS_CFG_Q_GRP_PARA_T;
-
-typedef struct dpp_etm_cgavd_sys_wq_t
-{
-    ZXIC_UINT32 wq_sys;
-}DPP_ETM_CGAVD_SYS_WQ_T;
-
-typedef struct dpp_etm_cgavd_gred_max_th_t
-{
-    ZXIC_UINT32 gred_max_th;
-}DPP_ETM_CGAVD_GRED_MAX_TH_T;
-
-typedef struct dpp_etm_cgavd_gred_mid_th_t
-{
-    ZXIC_UINT32 gred_mid_th;
-}DPP_ETM_CGAVD_GRED_MID_TH_T;
-
-typedef struct dpp_etm_cgavd_gred_min_th_t
-{
-    ZXIC_UINT32 gred_min_th;
-}DPP_ETM_CGAVD_GRED_MIN_TH_T;
-
-typedef struct dpp_etm_cgavd_gred_cfg_para0_t
-{
-    ZXIC_UINT32 gred_cfg_para0;
-}DPP_ETM_CGAVD_GRED_CFG_PARA0_T;
-
-typedef struct dpp_etm_cgavd_gred_cfg_para1_t
-{
-    ZXIC_UINT32 gred_cfg_para1;
-}DPP_ETM_CGAVD_GRED_CFG_PARA1_T;
-
-typedef struct dpp_etm_cgavd_gred_cfg_para2_t
-{
-    ZXIC_UINT32 gred_cfg_para2;
-}DPP_ETM_CGAVD_GRED_CFG_PARA2_T;
-
-typedef struct dpp_etm_cgavd_sys_window_th_h_t
-{
-    ZXIC_UINT32 sys_window_th_h;
-}DPP_ETM_CGAVD_SYS_WINDOW_TH_H_T;
-
-typedef struct dpp_etm_cgavd_sys_window_th_l_t
-{
-    ZXIC_UINT32 sys_window_th_l;
-}DPP_ETM_CGAVD_SYS_WINDOW_TH_L_T;
-
-typedef struct dpp_etm_cgavd_amplify_gene0_t
-{
-    ZXIC_UINT32 amplify_gene0;
-}DPP_ETM_CGAVD_AMPLIFY_GENE0_T;
-
-typedef struct dpp_etm_cgavd_amplify_gene1_t
-{
-    ZXIC_UINT32 amplify_gene1;
-}DPP_ETM_CGAVD_AMPLIFY_GENE1_T;
-
-typedef struct dpp_etm_cgavd_amplify_gene2_t
-{
-    ZXIC_UINT32 amplify_gene2;
-}DPP_ETM_CGAVD_AMPLIFY_GENE2_T;
-
-typedef struct dpp_etm_cgavd_amplify_gene3_t
-{
-    ZXIC_UINT32 amplify_gene3;
-}DPP_ETM_CGAVD_AMPLIFY_GENE3_T;
-
-typedef struct dpp_etm_cgavd_amplify_gene4_t
-{
-    ZXIC_UINT32 amplify_gene4;
-}DPP_ETM_CGAVD_AMPLIFY_GENE4_T;
-
-typedef struct dpp_etm_cgavd_amplify_gene5_t
-{
-    ZXIC_UINT32 amplify_gene5;
-}DPP_ETM_CGAVD_AMPLIFY_GENE5_T;
-
-typedef struct dpp_etm_cgavd_amplify_gene6_t
-{
-    ZXIC_UINT32 amplify_gene6;
-}DPP_ETM_CGAVD_AMPLIFY_GENE6_T;
-
-typedef struct dpp_etm_cgavd_amplify_gene7_t
-{
-    ZXIC_UINT32 amplify_gene7;
-}DPP_ETM_CGAVD_AMPLIFY_GENE7_T;
-
-typedef struct dpp_etm_cgavd_amplify_gene8_t
-{
-    ZXIC_UINT32 amplify_gene8;
-}DPP_ETM_CGAVD_AMPLIFY_GENE8_T;
-
-typedef struct dpp_etm_cgavd_amplify_gene9_t
-{
-    ZXIC_UINT32 amplify_gene9;
-}DPP_ETM_CGAVD_AMPLIFY_GENE9_T;
-
-typedef struct dpp_etm_cgavd_amplify_gene10_t
-{
-    ZXIC_UINT32 amplify_gene10;
-}DPP_ETM_CGAVD_AMPLIFY_GENE10_T;
-
-typedef struct dpp_etm_cgavd_amplify_gene11_t
-{
-    ZXIC_UINT32 amplify_gene11;
-}DPP_ETM_CGAVD_AMPLIFY_GENE11_T;
-
-typedef struct dpp_etm_cgavd_amplify_gene12_t
-{
-    ZXIC_UINT32 amplify_gene12;
-}DPP_ETM_CGAVD_AMPLIFY_GENE12_T;
-
-typedef struct dpp_etm_cgavd_amplify_gene13_t
-{
-    ZXIC_UINT32 amplify_gene13;
-}DPP_ETM_CGAVD_AMPLIFY_GENE13_T;
-
-typedef struct dpp_etm_cgavd_amplify_gene14_t
-{
-    ZXIC_UINT32 amplify_gene14;
-}DPP_ETM_CGAVD_AMPLIFY_GENE14_T;
-
-typedef struct dpp_etm_cgavd_amplify_gene15_t
-{
-    ZXIC_UINT32 amplify_gene15;
-}DPP_ETM_CGAVD_AMPLIFY_GENE15_T;
-
-typedef struct dpp_etm_cgavd_equal_pkt_len_en_t
-{
-    ZXIC_UINT32 equal_pkt_len_en;
-}DPP_ETM_CGAVD_EQUAL_PKT_LEN_EN_T;
-
-typedef struct dpp_etm_cgavd_equal_pkt_len_th0_t
-{
-    ZXIC_UINT32 equal_pkt_len_th0;
-}DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH0_T;
-
-typedef struct dpp_etm_cgavd_equal_pkt_len_th1_t
-{
-    ZXIC_UINT32 equal_pkt_len_th1;
-}DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH1_T;
-
-typedef struct dpp_etm_cgavd_equal_pkt_len_th2_t
-{
-    ZXIC_UINT32 equal_pkt_len_th2;
-}DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH2_T;
-
-typedef struct dpp_etm_cgavd_equal_pkt_len_th3_t
-{
-    ZXIC_UINT32 equal_pkt_len_th3;
-}DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH3_T;
-
-typedef struct dpp_etm_cgavd_equal_pkt_len_th4_t
-{
-    ZXIC_UINT32 equal_pkt_len_th4;
-}DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH4_T;
-
-typedef struct dpp_etm_cgavd_equal_pkt_len_th5_t
-{
-    ZXIC_UINT32 equal_pkt_len_th5;
-}DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH5_T;
-
-typedef struct dpp_etm_cgavd_equal_pkt_len_th6_t
-{
-    ZXIC_UINT32 equal_pkt_len_th6;
-}DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH6_T;
-
-typedef struct dpp_etm_cgavd_equal_pkt_len0_t
-{
-    ZXIC_UINT32 equal_pkt_len0;
-}DPP_ETM_CGAVD_EQUAL_PKT_LEN0_T;
-
-typedef struct dpp_etm_cgavd_equal_pkt_len1_t
-{
-    ZXIC_UINT32 equal_pkt_len1;
-}DPP_ETM_CGAVD_EQUAL_PKT_LEN1_T;
-
-typedef struct dpp_etm_cgavd_equal_pkt_len2_t
-{
-    ZXIC_UINT32 equal_pkt_len2;
-}DPP_ETM_CGAVD_EQUAL_PKT_LEN2_T;
-
-typedef struct dpp_etm_cgavd_equal_pkt_len3_t
-{
-    ZXIC_UINT32 equal_pkt_len3;
-}DPP_ETM_CGAVD_EQUAL_PKT_LEN3_T;
-
-typedef struct dpp_etm_cgavd_equal_pkt_len4_t
-{
-    ZXIC_UINT32 equal_pkt_len4;
-}DPP_ETM_CGAVD_EQUAL_PKT_LEN4_T;
-
-typedef struct dpp_etm_cgavd_equal_pkt_len5_t
-{
-    ZXIC_UINT32 equal_pkt_len5;
-}DPP_ETM_CGAVD_EQUAL_PKT_LEN5_T;
-
-typedef struct dpp_etm_cgavd_equal_pkt_len6_t
-{
-    ZXIC_UINT32 equal_pkt_len6;
-}DPP_ETM_CGAVD_EQUAL_PKT_LEN6_T;
-
-typedef struct dpp_etm_cgavd_equal_pkt_len7_t
-{
-    ZXIC_UINT32 equal_pkt_len7;
-}DPP_ETM_CGAVD_EQUAL_PKT_LEN7_T;
-
-typedef struct dpp_etm_cgavd_flow_cpu_set_avg_len_t
-{
-    ZXIC_UINT32 flow_cpu_set_avg_len;
-}DPP_ETM_CGAVD_FLOW_CPU_SET_AVG_LEN_T;
-
-typedef struct dpp_etm_cgavd_flow_cpu_set_q_len_t
-{
-    ZXIC_UINT32 flow_cpu_set_q_len;
-}DPP_ETM_CGAVD_FLOW_CPU_SET_Q_LEN_T;
-
-typedef struct dpp_etm_cgavd_pp_cpu_set_avg_q_len_t
-{
-    ZXIC_UINT32 pp_cpu_set_avg_q_len;
-}DPP_ETM_CGAVD_PP_CPU_SET_AVG_Q_LEN_T;
-
-typedef struct dpp_etm_cgavd_pp_cpu_set_q_len_t
-{
-    ZXIC_UINT32 pp_cpu_set_q_len;
-}DPP_ETM_CGAVD_PP_CPU_SET_Q_LEN_T;
-
-typedef struct dpp_etm_cgavd_sys_cpu_set_avg_len_t
-{
-    ZXIC_UINT32 sys_cpu_set_avg_len;
-}DPP_ETM_CGAVD_SYS_CPU_SET_AVG_LEN_T;
-
-typedef struct dpp_etm_cgavd_sys_cpu_set_q_len_t
-{
-    ZXIC_UINT32 sys_cpu_set_q_len;
-}DPP_ETM_CGAVD_SYS_CPU_SET_Q_LEN_T;
-
-typedef struct dpp_etm_cgavd_pke_len_calc_sign_t
-{
-    ZXIC_UINT32 pke_len_calc_sign;
-}DPP_ETM_CGAVD_PKE_LEN_CALC_SIGN_T;
-
-typedef struct dpp_etm_cgavd_rd_cpu_or_ram_t
-{
-    ZXIC_UINT32 cpu_sel_sys_q_len_en;
-    ZXIC_UINT32 cpu_sel_sys_avg_q_len_en;
-    ZXIC_UINT32 cpu_sel_pp_q_len_en;
-    ZXIC_UINT32 cpu_sel_pp_avg_q_len_en;
-    ZXIC_UINT32 cpu_sel_flow_q_len_en;
-    ZXIC_UINT32 cpu_sel_flow_avg_q_len_en;
-}DPP_ETM_CGAVD_RD_CPU_OR_RAM_T;
-
-typedef struct dpp_etm_cgavd_q_len_update_disable_t
-{
-    ZXIC_UINT32 q_len_sys_update_en;
-    ZXIC_UINT32 q_len_pp_update_en;
-    ZXIC_UINT32 q_len_flow_update_en;
-}DPP_ETM_CGAVD_Q_LEN_UPDATE_DISABLE_T;
-
-typedef struct dpp_etm_cgavd_cgavd_dp_sel_t
-{
-    ZXIC_UINT32 flow_dp_sel_high;
-    ZXIC_UINT32 flow_dp_sel_mid;
-    ZXIC_UINT32 flow_dp_sel_low;
-    ZXIC_UINT32 pp_dp_sel_high;
-    ZXIC_UINT32 pp_dp_sel_mid;
-    ZXIC_UINT32 pp_dp_sel_low;
-    ZXIC_UINT32 sys_dp_sel_high;
-    ZXIC_UINT32 sys_dp_sel_mid;
-    ZXIC_UINT32 sys_dp_sel_low;
-}DPP_ETM_CGAVD_CGAVD_DP_SEL_T;
-
-typedef struct dpp_etm_cgavd_cgavd_sub_en_t
-{
-    ZXIC_UINT32 cgavd_sa_sub_en;
-    ZXIC_UINT32 cgavd_sys_sub_en;
-    ZXIC_UINT32 cgavd_pp_sub_en;
-    ZXIC_UINT32 cgavd_flow_sub_en;
-}DPP_ETM_CGAVD_CGAVD_SUB_EN_T;
-
-typedef struct dpp_etm_cgavd_default_start_queue_t
-{
-    ZXIC_UINT32 default_start_queue;
-}DPP_ETM_CGAVD_DEFAULT_START_QUEUE_T;
-
-typedef struct dpp_etm_cgavd_default_finish_queue_t
-{
-    ZXIC_UINT32 default_finish_queue;
-}DPP_ETM_CGAVD_DEFAULT_FINISH_QUEUE_T;
-
-typedef struct dpp_etm_cgavd_protocol_start_queue_t
-{
-    ZXIC_UINT32 protocol_start_queue;
-}DPP_ETM_CGAVD_PROTOCOL_START_QUEUE_T;
-
-typedef struct dpp_etm_cgavd_protocol_finish_queue_t
-{
-    ZXIC_UINT32 protocol_finish_queue;
-}DPP_ETM_CGAVD_PROTOCOL_FINISH_QUEUE_T;
-
-typedef struct dpp_etm_cgavd_uniform_td_th_t
-{
-    ZXIC_UINT32 uniform_td_th;
-}DPP_ETM_CGAVD_UNIFORM_TD_TH_T;
-
-typedef struct dpp_etm_cgavd_uniform_td_th_en_t
-{
-    ZXIC_UINT32 uniform_td_th_en;
-}DPP_ETM_CGAVD_UNIFORM_TD_TH_EN_T;
-
-typedef struct dpp_etm_cgavd_cgavd_cfg_fc_t
-{
-    ZXIC_UINT32 cgavd_cfg_fc;
-}DPP_ETM_CGAVD_CGAVD_CFG_FC_T;
-
-typedef struct dpp_etm_cgavd_cgavd_cfg_no_fc_t
-{
-    ZXIC_UINT32 cgavd_cfg_no_fc;
-}DPP_ETM_CGAVD_CGAVD_CFG_NO_FC_T;
-
-typedef struct dpp_etm_cgavd_cgavd_force_imem_omem_t
-{
-    ZXIC_UINT32 imem_omem_force_en;
-    ZXIC_UINT32 choose_imem_omem;
-}DPP_ETM_CGAVD_CGAVD_FORCE_IMEM_OMEM_T;
-
-typedef struct dpp_etm_cgavd_cgavd_sys_q_len_l_t
-{
-    ZXIC_UINT32 cgavd_sys_q_len_l;
-}DPP_ETM_CGAVD_CGAVD_SYS_Q_LEN_L_T;
-
-typedef struct dpp_etm_cgavd_default_queue_en_t
-{
-    ZXIC_UINT32 default_queue_en;
-}DPP_ETM_CGAVD_DEFAULT_QUEUE_EN_T;
-
-typedef struct dpp_etm_cgavd_protocol_queue_en_t
-{
-    ZXIC_UINT32 protocol_queue_en;
-}DPP_ETM_CGAVD_PROTOCOL_QUEUE_EN_T;
-
-typedef struct dpp_etm_cgavd_cfg_tc_flowid_dat_t
-{
-    ZXIC_UINT32 cfg_tc_flowid_dat;
-}DPP_ETM_CGAVD_CFG_TC_FLOWID_DAT_T;
-
-typedef struct dpp_etm_cgavd_flow_td_th_t
-{
-    ZXIC_UINT32 flow_td_th;
-}DPP_ETM_CGAVD_FLOW_TD_TH_T;
-
-typedef struct dpp_etm_cgavd_flow_ca_mtd_t
-{
-    ZXIC_UINT32 flow_ca_mtd;
-}DPP_ETM_CGAVD_FLOW_CA_MTD_T;
-
-typedef struct dpp_etm_cgavd_flow_dynamic_th_en_t
-{
-    ZXIC_UINT32 flow_dynamic_th_en;
-}DPP_ETM_CGAVD_FLOW_DYNAMIC_TH_EN_T;
-
-typedef struct dpp_etm_cgavd_pp_num_t
-{
-    ZXIC_UINT32 pp_num;
-}DPP_ETM_CGAVD_PP_NUM_T;
-
-typedef struct dpp_etm_cgavd_flow_q_len_t
-{
-    ZXIC_UINT32 flow_q_len;
-}DPP_ETM_CGAVD_FLOW_Q_LEN_T;
-
-typedef struct dpp_etm_cgavd_flow_wred_grp_t
-{
-    ZXIC_UINT32 flow_wred_grp;
-}DPP_ETM_CGAVD_FLOW_WRED_GRP_T;
-
-typedef struct dpp_etm_cgavd_flow_avg_q_len_t
-{
-    ZXIC_UINT32 flow_avg_q_len;
-}DPP_ETM_CGAVD_FLOW_AVG_Q_LEN_T;
-
-typedef struct dpp_etm_cgavd_qos_sign_t
-{
-    ZXIC_UINT32 qos_sign_flow_cfg_din;
-}DPP_ETM_CGAVD_QOS_SIGN_T;
-
-typedef struct dpp_etm_cgavd_q_pri_t
-{
-    ZXIC_UINT32 qpri_flow_cfg_din;
-}DPP_ETM_CGAVD_Q_PRI_T;
-
-typedef struct dpp_etm_cgavd_odma_tm_itmd_rd_low_t
-{
-    ZXIC_UINT32 odma_tm_itmd_low;
-}DPP_ETM_CGAVD_ODMA_TM_ITMD_RD_LOW_T;
-
-typedef struct dpp_etm_cgavd_odma_tm_itmd_rd_mid_t
-{
-    ZXIC_UINT32 odma_tm_itmd_mid;
-}DPP_ETM_CGAVD_ODMA_TM_ITMD_RD_MID_T;
-
-typedef struct dpp_etm_cgavd_odma_tm_itmd_rd_high_t
-{
-    ZXIC_UINT32 odma_tm_itmd_high;
-}DPP_ETM_CGAVD_ODMA_TM_ITMD_RD_HIGH_T;
-
-typedef struct dpp_etm_cgavd_cgavd_stat_pkt_len_t
-{
-    ZXIC_UINT32 expect_deq_pkt_len;
-    ZXIC_UINT32 expect_enq_pkt_len;
-}DPP_ETM_CGAVD_CGAVD_STAT_PKT_LEN_T;
-
-typedef struct dpp_etm_cgavd_cgavd_stat_qnum_t
-{
-    ZXIC_UINT32 cgavd_unexcept_qnum;
-    ZXIC_UINT32 cgavd_except_qnum;
-}DPP_ETM_CGAVD_CGAVD_STAT_QNUM_T;
-
-typedef struct dpp_etm_cgavd_cgavd_stat_dp_t
-{
-    ZXIC_UINT32 cgavd_stat_dp;
-}DPP_ETM_CGAVD_CGAVD_STAT_DP_T;
-
-typedef struct dpp_etm_cgavd_flow_num0_t
-{
-    ZXIC_UINT32 flow_num0;
-}DPP_ETM_CGAVD_FLOW_NUM0_T;
-
-typedef struct dpp_etm_cgavd_flow_num1_t
-{
-    ZXIC_UINT32 flow_num1;
-}DPP_ETM_CGAVD_FLOW_NUM1_T;
-
-typedef struct dpp_etm_cgavd_flow_num2_t
-{
-    ZXIC_UINT32 flow_num2;
-}DPP_ETM_CGAVD_FLOW_NUM2_T;
-
-typedef struct dpp_etm_cgavd_flow_num3_t
-{
-    ZXIC_UINT32 flow_num3;
-}DPP_ETM_CGAVD_FLOW_NUM3_T;
-
-typedef struct dpp_etm_cgavd_flow_num4_t
-{
-    ZXIC_UINT32 flow_num4;
-}DPP_ETM_CGAVD_FLOW_NUM4_T;
-
-typedef struct dpp_etm_cgavd_flow0_imem_cnt_t
-{
-    ZXIC_UINT32 flow0_imem_cnt;
-}DPP_ETM_CGAVD_FLOW0_IMEM_CNT_T;
-
-typedef struct dpp_etm_cgavd_flow1_imem_cnt_t
-{
-    ZXIC_UINT32 flow1_imem_cnt;
-}DPP_ETM_CGAVD_FLOW1_IMEM_CNT_T;
-
-typedef struct dpp_etm_cgavd_flow2_imem_cnt_t
-{
-    ZXIC_UINT32 flow2_imem_cnt;
-}DPP_ETM_CGAVD_FLOW2_IMEM_CNT_T;
-
-typedef struct dpp_etm_cgavd_flow3_imem_cnt_t
-{
-    ZXIC_UINT32 flow3_imem_cnt;
-}DPP_ETM_CGAVD_FLOW3_IMEM_CNT_T;
-
-typedef struct dpp_etm_cgavd_flow4_imem_cnt_t
-{
-    ZXIC_UINT32 flow4_imem_cnt;
-}DPP_ETM_CGAVD_FLOW4_IMEM_CNT_T;
-
-typedef struct dpp_etm_cgavd_flow0_drop_cnt_t
-{
-    ZXIC_UINT32 flow0_drop_cnt;
-}DPP_ETM_CGAVD_FLOW0_DROP_CNT_T;
-
-typedef struct dpp_etm_cgavd_flow1_drop_cnt_t
-{
-    ZXIC_UINT32 flow1_drop_cnt;
-}DPP_ETM_CGAVD_FLOW1_DROP_CNT_T;
-
-typedef struct dpp_etm_cgavd_flow2_drop_cnt_t
-{
-    ZXIC_UINT32 flow2_drop_cnt;
-}DPP_ETM_CGAVD_FLOW2_DROP_CNT_T;
-
-typedef struct dpp_etm_cgavd_flow3_drop_cnt_t
-{
-    ZXIC_UINT32 flow3_drop_cnt;
-}DPP_ETM_CGAVD_FLOW3_DROP_CNT_T;
-
-typedef struct dpp_etm_cgavd_flow4_drop_cnt_t
-{
-    ZXIC_UINT32 flow4_drop_cnt;
-}DPP_ETM_CGAVD_FLOW4_DROP_CNT_T;
-
-typedef struct dpp_etm_cgavd_fc_count_mode_t
-{
-    ZXIC_UINT32 fc_count_mode;
-}DPP_ETM_CGAVD_FC_COUNT_MODE_T;
-
-typedef struct dpp_etm_cgavd_qmu_cgavd_fc_num_t
-{
-    ZXIC_UINT32 qmu_cgavd_fc_state;
-    ZXIC_UINT32 qmu_cgavd_fc_num;
-}DPP_ETM_CGAVD_QMU_CGAVD_FC_NUM_T;
-
-typedef struct dpp_etm_cgavd_cgavd_odma_fc_num_t
-{
-    ZXIC_UINT32 cgavd_lif_fc_state;
-    ZXIC_UINT32 cgavd_lif_fc_num;
-}DPP_ETM_CGAVD_CGAVD_ODMA_FC_NUM_T;
-
-typedef struct dpp_etm_cgavd_cfg_offset_t
-{
-    ZXIC_UINT32 cfg_offset;
-}DPP_ETM_CGAVD_CFG_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_tmmu_init_done_t
-{
-    ZXIC_UINT32 tmmu_init_done;
-}DPP_ETM_TMMU_TMMU_INIT_DONE_T;
-
-typedef struct dpp_etm_tmmu_tmmu_int_mask_1_t
-{
-    ZXIC_UINT32 imem_enq_rd_fifo_full_mask;
-    ZXIC_UINT32 imem_enq_rd_fifo_overflow_mask;
-    ZXIC_UINT32 imem_enq_rd_fifo_underflow_mask;
-    ZXIC_UINT32 imem_enq_drop_fifo_full_mask;
-    ZXIC_UINT32 imem_enq_drop_fifo_overflow_mask;
-    ZXIC_UINT32 imem_enq_drop_fifo_underflow_mask;
-    ZXIC_UINT32 imem_deq_rd_fifo_full_mask;
-    ZXIC_UINT32 imem_deq_rd_fifo_overflow_mask;
-    ZXIC_UINT32 imem_deq_rd_fifo_underflow_mask;
-    ZXIC_UINT32 imem_deq_drop_fifo_full_mask;
-    ZXIC_UINT32 imem_deq_drop_fifo_overflow_mask;
-    ZXIC_UINT32 imem_deq_drop_fifo_underflow_mask;
-    ZXIC_UINT32 dma_data_fifo_full_mask;
-    ZXIC_UINT32 dma_data_fifo_overflow_mask;
-    ZXIC_UINT32 dma_data_fifo_underflow_mask;
-    ZXIC_UINT32 wr_cmd_fifo_full_mask;
-    ZXIC_UINT32 wr_cmd_fifo_overflow_mask;
-    ZXIC_UINT32 wr_cmd_fifo_underflow_mask;
-    ZXIC_UINT32 cached_pd_fifo_full_mask;
-    ZXIC_UINT32 cached_pd_fifo_overflow_mask;
-    ZXIC_UINT32 cached_pd_fifo_underflow_mask;
-    ZXIC_UINT32 emem_pd_fifo_full_mask;
-    ZXIC_UINT32 emem_pd_fifo_overflow_mask;
-    ZXIC_UINT32 emem_pd_fifo_underflow_mask;
-    ZXIC_UINT32 pd_order_fifo_full_mask;
-    ZXIC_UINT32 pd_order_fifo_overflow_mask;
-    ZXIC_UINT32 pd_order_fifo_underflow_mask;
-}DPP_ETM_TMMU_TMMU_INT_MASK_1_T;
-
-typedef struct dpp_etm_tmmu_tmmu_int_mask_2_t
-{
-    ZXIC_UINT32 dma_data_fifo_parity_err_mask;
-    ZXIC_UINT32 imem_enq_rd_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 imem_enq_rd_fifo_ecc_double_err_mask;
-    ZXIC_UINT32 imem_enq_drop_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 imem_enq_drop_fifo_ecc_double_err_mask;
-    ZXIC_UINT32 imem_deq_rd_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 imem_deq_rd_fifo_ecc_double_err_mask;
-    ZXIC_UINT32 imem_deq_drop_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 imem_deq_drop_fifo_ecc_double_err_mask;
-    ZXIC_UINT32 wr_cmd_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 wr_cmd_fifo_ecc_double_err_mask;
-    ZXIC_UINT32 pd_cache_ram_ecc_single_err_mask;
-    ZXIC_UINT32 pd_cache_ram_ecc_double_err_mask;
-    ZXIC_UINT32 cached_pd_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 cached_pd_fifo_ecc_double_err_mask;
-    ZXIC_UINT32 emem_pd_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 emem_pd_fifo_ecc_double_err_mask;
-}DPP_ETM_TMMU_TMMU_INT_MASK_2_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_tm_pure_imem_en_t
-{
-    ZXIC_UINT32 cfgmt_tm_pure_imem_en;
-}DPP_ETM_TMMU_CFGMT_TM_PURE_IMEM_EN_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_force_ddr_rdy_cfg_t
-{
-    ZXIC_UINT32 cfgmt_force_ddr_rdy_cfg;
-}DPP_ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFG_T;
-
-typedef struct dpp_etm_tmmu_pd_order_fifo_aful_th_t
-{
-    ZXIC_UINT32 pd_order_fifo_aful_th;
-}DPP_ETM_TMMU_PD_ORDER_FIFO_AFUL_TH_T;
-
-typedef struct dpp_etm_tmmu_cached_pd_fifo_aful_th_t
-{
-    ZXIC_UINT32 cached_pd_fifo_aful_th;
-}DPP_ETM_TMMU_CACHED_PD_FIFO_AFUL_TH_T;
-
-typedef struct dpp_etm_tmmu_wr_cmd_fifo_aful_th_t
-{
-    ZXIC_UINT32 wr_cmd_fifo_aful_th;
-}DPP_ETM_TMMU_WR_CMD_FIFO_AFUL_TH_T;
-
-typedef struct dpp_etm_tmmu_imem_enq_rd_fifo_aful_th_t
-{
-    ZXIC_UINT32 imem_enq_rd_fifo_aful_th;
-}DPP_ETM_TMMU_IMEM_ENQ_RD_FIFO_AFUL_TH_T;
-
-typedef struct dpp_etm_tmmu_imem_enq_drop_fifo_aful_th_t
-{
-    ZXIC_UINT32 imem_enq_drop_fifo_aful_th;
-}DPP_ETM_TMMU_IMEM_ENQ_DROP_FIFO_AFUL_TH_T;
-
-typedef struct dpp_etm_tmmu_imem_deq_drop_fifo_aful_th_t
-{
-    ZXIC_UINT32 imem_deq_drop_fifo_aful_th;
-}DPP_ETM_TMMU_IMEM_DEQ_DROP_FIFO_AFUL_TH_T;
-
-typedef struct dpp_etm_tmmu_imem_deq_rd_fifo_aful_th_t
-{
-    ZXIC_UINT32 imem_deq_rd_fifo_aful_th;
-}DPP_ETM_TMMU_IMEM_DEQ_RD_FIFO_AFUL_TH_T;
-
-typedef struct dpp_etm_tmmu_tmmu_states_1_t
-{
-    ZXIC_UINT32 imem_enq_rd_fifo_full;
-    ZXIC_UINT32 imem_enq_rd_fifo_overflow;
-    ZXIC_UINT32 imem_enq_rd_fifo_underflow;
-    ZXIC_UINT32 imem_enq_drop_fifo_full;
-    ZXIC_UINT32 imem_enq_drop_fifo_overflow;
-    ZXIC_UINT32 imem_enq_drop_fifo_underflow;
-    ZXIC_UINT32 imem_deq_rd_fifo_full;
-    ZXIC_UINT32 imem_deq_rd_fifo_overflow;
-    ZXIC_UINT32 imem_deq_rd_fifo_underflow;
-    ZXIC_UINT32 imem_deq_drop_fifo_full;
-    ZXIC_UINT32 imem_deq_drop_fifo_overflow;
-    ZXIC_UINT32 imem_deq_drop_fifo_underflow;
-    ZXIC_UINT32 dma_data_fifo_full;
-    ZXIC_UINT32 dma_data_fifo_overflow;
-    ZXIC_UINT32 dma_data_fifo_underflow;
-    ZXIC_UINT32 wr_cmd_fifo_full;
-    ZXIC_UINT32 wr_cmd_fifo_overflow;
-    ZXIC_UINT32 wr_cmd_fifo_underflow;
-    ZXIC_UINT32 cached_pd_fifo_full;
-    ZXIC_UINT32 cached_pd_fifo_overflow;
-    ZXIC_UINT32 cached_pd_fifo_underflow;
-    ZXIC_UINT32 emem_pd_fifo_full;
-    ZXIC_UINT32 emem_pd_fifo_overflow;
-    ZXIC_UINT32 emem_pd_fifo_underflow;
-    ZXIC_UINT32 pd_order_fifo_full;
-    ZXIC_UINT32 pd_order_fifo_overflow;
-    ZXIC_UINT32 pd_order_fifo_underflow;
-}DPP_ETM_TMMU_TMMU_STATES_1_T;
-
-typedef struct dpp_etm_tmmu_tmmu_states_2_t
-{
-    ZXIC_UINT32 dma_data_fifo_parity_err;
-    ZXIC_UINT32 imem_enq_rd_fifo_ecc_single_err;
-    ZXIC_UINT32 imem_enq_rd_fifo_ecc_double_err;
-    ZXIC_UINT32 imem_enq_drop_fifo_ecc_single_err;
-    ZXIC_UINT32 imem_enq_drop_fifo_ecc_double_err;
-    ZXIC_UINT32 imem_deq_rd_fifo_ecc_single_err;
-    ZXIC_UINT32 imem_deq_rd_fifo_ecc_double_err;
-    ZXIC_UINT32 imem_deq_drop_fifo_ecc_single_err;
-    ZXIC_UINT32 imem_deq_drop_fifo_ecc_double_err;
-    ZXIC_UINT32 wr_cmd_fifo_ecc_single_err;
-    ZXIC_UINT32 wr_cmd_fifo_ecc_double_err;
-    ZXIC_UINT32 pd_cache_ram_ecc_single_err;
-    ZXIC_UINT32 pd_cache_ram_ecc_double_err;
-    ZXIC_UINT32 cached_pd_fifo_ecc_single_err;
-    ZXIC_UINT32 cached_pd_fifo_ecc_double_err;
-    ZXIC_UINT32 emem_pd_fifo_ecc_single_err;
-    ZXIC_UINT32 emem_pd_fifo_ecc_double_err;
-}DPP_ETM_TMMU_TMMU_STATES_2_T;
-
-typedef struct dpp_etm_shap_shap_ind_cmd_t
-{
-    ZXIC_UINT32 rd;
-    ZXIC_UINT32 mem_id;
-    ZXIC_UINT32 addr;
-}DPP_ETM_SHAP_SHAP_IND_CMD_T;
-
-typedef struct dpp_etm_shap_shap_ind_sta_t
-{
-    ZXIC_UINT32 indirectaccessdone;
-}DPP_ETM_SHAP_SHAP_IND_STA_T;
-
-typedef struct dpp_etm_shap_shap_ind_data0_t
-{
-    ZXIC_UINT32 indirectdata0;
-}DPP_ETM_SHAP_SHAP_IND_DATA0_T;
-
-typedef struct dpp_etm_shap_shap_ind_data1_t
-{
-    ZXIC_UINT32 indirectdata1;
-}DPP_ETM_SHAP_SHAP_IND_DATA1_T;
-
-typedef struct dpp_etm_shap_full_threshold_t
-{
-    ZXIC_UINT32 full_threshold;
-}DPP_ETM_SHAP_FULL_THRESHOLD_T;
-
-typedef struct dpp_etm_shap_empty_threshold_t
-{
-    ZXIC_UINT32 empty_threshold;
-}DPP_ETM_SHAP_EMPTY_THRESHOLD_T;
-
-typedef struct dpp_etm_shap_shap_sta_init_cfg_t
-{
-    ZXIC_UINT32 sta_ram_init_done;
-    ZXIC_UINT32 sta_ram_init_en;
-}DPP_ETM_SHAP_SHAP_STA_INIT_CFG_T;
-
-typedef struct dpp_etm_shap_shap_cfg_init_cfg_t
-{
-    ZXIC_UINT32 cfg_ram_init_done;
-    ZXIC_UINT32 cfg_ram_init_en;
-}DPP_ETM_SHAP_SHAP_CFG_INIT_CFG_T;
-
-typedef struct dpp_etm_shap_token_mode_switch_t
-{
-    ZXIC_UINT32 token_mode_switch;
-}DPP_ETM_SHAP_TOKEN_MODE_SWITCH_T;
-
-typedef struct dpp_etm_shap_token_grain_t
-{
-    ZXIC_UINT32 token_grain;
-}DPP_ETM_SHAP_TOKEN_GRAIN_T;
-
-typedef struct dpp_etm_shap_crd_grain_t
-{
-    ZXIC_UINT32 crd_grain;
-}DPP_ETM_SHAP_CRD_GRAIN_T;
-
-typedef struct dpp_etm_shap_shap_stat_ctrl_t
-{
-    ZXIC_UINT32 shap_stat_ctrl;
-}DPP_ETM_SHAP_SHAP_STAT_CTRL_T;
-
-typedef struct dpp_etm_shap_token_stat_id_t
-{
-    ZXIC_UINT32 token_stat_id;
-}DPP_ETM_SHAP_TOKEN_STAT_ID_T;
-
-typedef struct dpp_etm_shap_token_stat_t
-{
-    ZXIC_UINT32 token_stat;
-}DPP_ETM_SHAP_TOKEN_STAT_T;
-
-typedef struct dpp_etm_shap_shap_stat_clk_cnt_t
-{
-    ZXIC_UINT32 shap_stat_clk_cnt;
-}DPP_ETM_SHAP_SHAP_STAT_CLK_CNT_T;
-
-typedef struct dpp_etm_shap_shap_bucket_map_tbl_t
-{
-    ZXIC_UINT32 shap_map;
-}DPP_ETM_SHAP_SHAP_BUCKET_MAP_TBL_T;
-
-typedef struct dpp_etm_shap_bkt_para_tbl_t
-{
-    ZXIC_UINT32 bucket_depth;
-    ZXIC_UINT32 bucket_rate;
-}DPP_ETM_SHAP_BKT_PARA_TBL_T;
-
-typedef struct dpp_etm_crdt_credit_en_t
-{
-    ZXIC_UINT32 credit_en;
-}DPP_ETM_CRDT_CREDIT_EN_T;
-
-typedef struct dpp_etm_crdt_crt_inter1_t
-{
-    ZXIC_UINT32 crd_inter1;
-}DPP_ETM_CRDT_CRT_INTER1_T;
-
-typedef struct dpp_etm_crdt_db_token_t
-{
-    ZXIC_UINT32 db_token;
-}DPP_ETM_CRDT_DB_TOKEN_T;
-
-typedef struct dpp_etm_crdt_crs_flt_cfg_t
-{
-    ZXIC_UINT32 crs_flt_cfg;
-}DPP_ETM_CRDT_CRS_FLT_CFG_T;
-
-typedef struct dpp_etm_crdt_th_sp_t
-{
-    ZXIC_UINT32 th_sp;
-}DPP_ETM_CRDT_TH_SP_T;
-
-typedef struct dpp_etm_crdt_th_wfq_fq_t
-{
-    ZXIC_UINT32 th_fq;
-    ZXIC_UINT32 th_wfq;
-}DPP_ETM_CRDT_TH_WFQ_FQ_T;
-
-typedef struct dpp_etm_crdt_th_wfq2_fq2_t
-{
-    ZXIC_UINT32 th_fq2;
-    ZXIC_UINT32 th_wfq2;
-}DPP_ETM_CRDT_TH_WFQ2_FQ2_T;
-
-typedef struct dpp_etm_crdt_th_wfq4_fq4_t
-{
-    ZXIC_UINT32 th_fq4;
-    ZXIC_UINT32 th_wfq4;
-}DPP_ETM_CRDT_TH_WFQ4_FQ4_T;
-
-typedef struct dpp_etm_crdt_cfg_state_t
-{
-    ZXIC_UINT32 cfg_state;
-}DPP_ETM_CRDT_CFG_STATE_T;
-
-typedef struct dpp_etm_crdt_crdt_ind_cmd_t
-{
-    ZXIC_UINT32 rd;
-    ZXIC_UINT32 mem_id;
-    ZXIC_UINT32 addr;
-}DPP_ETM_CRDT_CRDT_IND_CMD_T;
-
-typedef struct dpp_etm_crdt_crdt_ind_sta_t
-{
-    ZXIC_UINT32 indirectaccessdone;
-}DPP_ETM_CRDT_CRDT_IND_STA_T;
-
-typedef struct dpp_etm_crdt_crdt_ind_data0_t
-{
-    ZXIC_UINT32 indirectdata0;
-}DPP_ETM_CRDT_CRDT_IND_DATA0_T;
-
-typedef struct dpp_etm_crdt_crdt_ind_data1_t
-{
-    ZXIC_UINT32 indirectdata1;
-}DPP_ETM_CRDT_CRDT_IND_DATA1_T;
-
-typedef struct dpp_etm_crdt_crdt_state_t
-{
-    ZXIC_UINT32 crdt_int;
-    ZXIC_UINT32 crdt_rdy;
-}DPP_ETM_CRDT_CRDT_STATE_T;
-
-typedef struct dpp_etm_crdt_stat_que_id_0_t
-{
-    ZXIC_UINT32 stat_que_id_0;
-}DPP_ETM_CRDT_STAT_QUE_ID_0_T;
-
-typedef struct dpp_etm_crdt_stat_que_id_1_t
-{
-    ZXIC_UINT32 stat_que_id_1;
-}DPP_ETM_CRDT_STAT_QUE_ID_1_T;
-
-typedef struct dpp_etm_crdt_stat_que_id_2_t
-{
-    ZXIC_UINT32 stat_que_id_2;
-}DPP_ETM_CRDT_STAT_QUE_ID_2_T;
-
-typedef struct dpp_etm_crdt_stat_que_id_3_t
-{
-    ZXIC_UINT32 stat_que_id_3;
-}DPP_ETM_CRDT_STAT_QUE_ID_3_T;
-
-typedef struct dpp_etm_crdt_stat_que_id_4_t
-{
-    ZXIC_UINT32 stat_que_id_4;
-}DPP_ETM_CRDT_STAT_QUE_ID_4_T;
-
-typedef struct dpp_etm_crdt_stat_que_id_5_t
-{
-    ZXIC_UINT32 stat_que_id_5;
-}DPP_ETM_CRDT_STAT_QUE_ID_5_T;
-
-typedef struct dpp_etm_crdt_stat_que_id_6_t
-{
-    ZXIC_UINT32 stat_que_id_6;
-}DPP_ETM_CRDT_STAT_QUE_ID_6_T;
-
-typedef struct dpp_etm_crdt_stat_que_id_7_t
-{
-    ZXIC_UINT32 stat_que_id_7;
-}DPP_ETM_CRDT_STAT_QUE_ID_7_T;
-
-typedef struct dpp_etm_crdt_stat_que_id_8_t
-{
-    ZXIC_UINT32 stat_que_id_8;
-}DPP_ETM_CRDT_STAT_QUE_ID_8_T;
-
-typedef struct dpp_etm_crdt_stat_que_id_9_t
-{
-    ZXIC_UINT32 stat_que_id_9;
-}DPP_ETM_CRDT_STAT_QUE_ID_9_T;
-
-typedef struct dpp_etm_crdt_stat_que_id_10_t
-{
-    ZXIC_UINT32 stat_que_id_10;
-}DPP_ETM_CRDT_STAT_QUE_ID_10_T;
-
-typedef struct dpp_etm_crdt_stat_que_id_11_t
-{
-    ZXIC_UINT32 stat_que_id_11;
-}DPP_ETM_CRDT_STAT_QUE_ID_11_T;
-
-typedef struct dpp_etm_crdt_stat_que_id_12_t
-{
-    ZXIC_UINT32 stat_que_id_12;
-}DPP_ETM_CRDT_STAT_QUE_ID_12_T;
-
-typedef struct dpp_etm_crdt_stat_que_id_13_t
-{
-    ZXIC_UINT32 stat_que_id_13;
-}DPP_ETM_CRDT_STAT_QUE_ID_13_T;
-
-typedef struct dpp_etm_crdt_stat_que_id_14_t
-{
-    ZXIC_UINT32 stat_que_id_14;
-}DPP_ETM_CRDT_STAT_QUE_ID_14_T;
-
-typedef struct dpp_etm_crdt_stat_que_id_15_t
-{
-    ZXIC_UINT32 stat_que_id_15;
-}DPP_ETM_CRDT_STAT_QUE_ID_15_T;
-
-typedef struct dpp_etm_crdt_stat_que_credit_t
-{
-    ZXIC_UINT32 stat_que_credit_cnt;
-}DPP_ETM_CRDT_STAT_QUE_CREDIT_T;
-
-typedef struct dpp_etm_crdt_crdt_cfg_ram_init_t
-{
-    ZXIC_UINT32 cfg_ram_init_done;
-    ZXIC_UINT32 cfg_ram_init_en;
-}DPP_ETM_CRDT_CRDT_CFG_RAM_INIT_T;
-
-typedef struct dpp_etm_crdt_crdt_sta_ram_init_t
-{
-    ZXIC_UINT32 sta_ram_init_done;
-    ZXIC_UINT32 sta_ram_init_en;
-}DPP_ETM_CRDT_CRDT_STA_RAM_INIT_T;
-
-typedef struct dpp_etm_crdt_crs_que_id_t
-{
-    ZXIC_UINT32 crs_que_id;
-}DPP_ETM_CRDT_CRS_QUE_ID_T;
-
-typedef struct dpp_etm_crdt_qmu_crs_end_state_t
-{
-    ZXIC_UINT32 qmu_crs_end_state;
-}DPP_ETM_CRDT_QMU_CRS_END_STATE_T;
-
-typedef struct dpp_etm_crdt_shap_rdy_t
-{
-    ZXIC_UINT32 shap_rdy;
-}DPP_ETM_CRDT_SHAP_RDY_T;
-
-typedef struct dpp_etm_crdt_shap_int_reg_t
-{
-    ZXIC_UINT32 pp_c_token_min_int;
-}DPP_ETM_CRDT_SHAP_INT_REG_T;
-
-typedef struct dpp_etm_crdt_shap_int_mask_reg_t
-{
-    ZXIC_UINT32 pp_c_token_min_int_mask;
-}DPP_ETM_CRDT_SHAP_INT_MASK_REG_T;
-
-typedef struct dpp_etm_crdt_token_state_almost_empty_th_t
-{
-    ZXIC_UINT32 token_state_almost_empty_th;
-}DPP_ETM_CRDT_TOKEN_STATE_ALMOST_EMPTY_TH_T;
-
-typedef struct dpp_etm_crdt_token_state_empty_th_t
-{
-    ZXIC_UINT32 token_state_empty_th;
-}DPP_ETM_CRDT_TOKEN_STATE_EMPTY_TH_T;
-
-typedef struct dpp_etm_crdt_full_th_t
-{
-    ZXIC_UINT32 token_state_full_th;
-}DPP_ETM_CRDT_FULL_TH_T;
-
-typedef struct dpp_etm_crdt_pp_c_level_shap_en_t
-{
-    ZXIC_UINT32 pp_c_level_shap_en;
-}DPP_ETM_CRDT_PP_C_LEVEL_SHAP_EN_T;
-
-typedef struct dpp_etm_crdt_enq_token_th_t
-{
-    ZXIC_UINT32 enq_token_th;
-}DPP_ETM_CRDT_ENQ_TOKEN_TH_T;
-
-typedef struct dpp_etm_crdt_pp_tokenq_level1_qstate_weight_cir_t
-{
-    ZXIC_UINT32 pp_pp_q_state_cir;
-    ZXIC_UINT32 pp_pp_q_weight_wfq_l1_cir;
-}DPP_ETM_CRDT_PP_TOKENQ_LEVEL1_QSTATE_WEIGHT_CIR_T;
-
-typedef struct dpp_etm_crdt_pp_idle_weight_level1_cir_t
-{
-    ZXIC_UINT32 pp_idle_q_weight_wfq_l1_cir;
-}DPP_ETM_CRDT_PP_IDLE_WEIGHT_LEVEL1_CIR_T;
-
-typedef struct dpp_etm_crdt_rci_grade_th_0_cfg_t
-{
-    ZXIC_UINT32 rci_grade_th_0_cfg;
-}DPP_ETM_CRDT_RCI_GRADE_TH_0_CFG_T;
-
-typedef struct dpp_etm_crdt_rci_grade_th_1_cfg_t
-{
-    ZXIC_UINT32 rci_grade_th_1_cfg;
-}DPP_ETM_CRDT_RCI_GRADE_TH_1_CFG_T;
-
-typedef struct dpp_etm_crdt_rci_grade_th_2_cfg_t
-{
-    ZXIC_UINT32 rci_grade_th_2_cfg;
-}DPP_ETM_CRDT_RCI_GRADE_TH_2_CFG_T;
-
-typedef struct dpp_etm_crdt_rci_grade_th_3_cfg_t
-{
-    ZXIC_UINT32 rci_grade_th_3_cfg;
-}DPP_ETM_CRDT_RCI_GRADE_TH_3_CFG_T;
-
-typedef struct dpp_etm_crdt_rci_grade_th_4_cfg_t
-{
-    ZXIC_UINT32 rci_grade_th_4_cfg;
-}DPP_ETM_CRDT_RCI_GRADE_TH_4_CFG_T;
-
-typedef struct dpp_etm_crdt_rci_grade_th_5_cfg_t
-{
-    ZXIC_UINT32 rci_grade_th_5_cfg;
-}DPP_ETM_CRDT_RCI_GRADE_TH_5_CFG_T;
-
-typedef struct dpp_etm_crdt_rci_grade_th_6_cfg_t
-{
-    ZXIC_UINT32 rci_grade_th_6_cfg;
-}DPP_ETM_CRDT_RCI_GRADE_TH_6_CFG_T;
-
-typedef struct dpp_etm_crdt_flow_del_cmd_t
-{
-    ZXIC_UINT32 flow_del_busy;
-    ZXIC_UINT32 flow_alt_cmd;
-    ZXIC_UINT32 flow_alt_ind;
-}DPP_ETM_CRDT_FLOW_DEL_CMD_T;
-
-typedef struct dpp_etm_crdt_cnt_clr_t
-{
-    ZXIC_UINT32 cnt_clr;
-}DPP_ETM_CRDT_CNT_CLR_T;
-
-typedef struct dpp_etm_crdt_crdt_int_bus_t
-{
-    ZXIC_UINT32 ldstr_fifo15_ovf_int;
-    ZXIC_UINT32 ldstr_fifo14_ovf_int;
-    ZXIC_UINT32 ldstr_fifo13_ovf_int;
-    ZXIC_UINT32 ldstr_fifo12_ovf_int;
-    ZXIC_UINT32 ldstr_fifo11_ovf_int;
-    ZXIC_UINT32 ldstr_fifo10_ovf_int;
-    ZXIC_UINT32 ldstr_fifo9_ovf_int;
-    ZXIC_UINT32 ldstr_fifo8_ovf_int;
-    ZXIC_UINT32 ldstr_fifo7_ovf_int;
-    ZXIC_UINT32 ldstr_fifo6_ovf_int;
-    ZXIC_UINT32 ldstr_fifo5_ovf_int;
-    ZXIC_UINT32 ldstr_fifo4_ovf_int;
-    ZXIC_UINT32 ldstr_fifo3_ovf_int;
-    ZXIC_UINT32 ldstr_fifo2_ovf_int;
-    ZXIC_UINT32 ldstr_fifo1_ovf_int;
-    ZXIC_UINT32 ldstr_fifo0_ovf_int;
-    ZXIC_UINT32 cfg_del_err_int;
-    ZXIC_UINT32 flwin_secrs_fifo_ovf_int;
-    ZXIC_UINT32 flwin_voqcrs_fifo_ovf_int;
-}DPP_ETM_CRDT_CRDT_INT_BUS_T;
-
-typedef struct dpp_etm_crdt_crdt_int_mask_t
-{
-    ZXIC_UINT32 crdt_int_mask;
-}DPP_ETM_CRDT_CRDT_INT_MASK_T;
-
-typedef struct dpp_etm_crdt_cfg_weight_together_t
-{
-    ZXIC_UINT32 cfg_weight_together;
-}DPP_ETM_CRDT_CFG_WEIGHT_TOGETHER_T;
-
-typedef struct dpp_etm_crdt_weight_t
-{
-    ZXIC_UINT32 c_weight;
-    ZXIC_UINT32 e_weight;
-}DPP_ETM_CRDT_WEIGHT_T;
-
-typedef struct dpp_etm_crdt_dev_sp_state_t
-{
-    ZXIC_UINT32 dev_sp_state;
-}DPP_ETM_CRDT_DEV_SP_STATE_T;
-
-typedef struct dpp_etm_crdt_dev_crs_t
-{
-    ZXIC_UINT32 dev_crs;
-}DPP_ETM_CRDT_DEV_CRS_T;
-
-typedef struct dpp_etm_crdt_congest_token_disable_31_0_t
-{
-    ZXIC_UINT32 congest_token_disable_31_0;
-}DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0_T;
-
-typedef struct dpp_etm_crdt_congest_token_disable_63_32_t
-{
-    ZXIC_UINT32 congest_token_disable_63_32;
-}DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32_T;
-
-typedef struct dpp_etm_crdt_crdt_interval_en_cfg_t
-{
-    ZXIC_UINT32 crdt_interval_en;
-}DPP_ETM_CRDT_CRDT_INTERVAL_EN_CFG_T;
-
-typedef struct dpp_etm_crdt_q_token_staue_cfg_t
-{
-    ZXIC_UINT32 test_token_q_id;
-}DPP_ETM_CRDT_Q_TOKEN_STAUE_CFG_T;
-
-typedef struct dpp_etm_crdt_q_token_dist_cnt_t
-{
-    ZXIC_UINT32 q_token_dist_counter;
-}DPP_ETM_CRDT_Q_TOKEN_DIST_CNT_T;
-
-typedef struct dpp_etm_crdt_q_token_dec_cnt_t
-{
-    ZXIC_UINT32 q_token_dec_counter;
-}DPP_ETM_CRDT_Q_TOKEN_DEC_CNT_T;
-
-typedef struct dpp_etm_crdt_pp_weight_ram_t
-{
-    ZXIC_UINT32 pp_c_weight;
-}DPP_ETM_CRDT_PP_WEIGHT_RAM_T;
-
-typedef struct dpp_etm_crdt_pp_cbs_shape_en_ram_t
-{
-    ZXIC_UINT32 pp_cbs;
-    ZXIC_UINT32 pp_c_shap_en;
-}DPP_ETM_CRDT_PP_CBS_SHAPE_EN_RAM_T;
-
-typedef struct dpp_etm_crdt_pp_next_pc_q_state_ram_t
-{
-    ZXIC_UINT32 pp_next_pc;
-    ZXIC_UINT32 pp_token_num;
-    ZXIC_UINT32 pp_q_state;
-}DPP_ETM_CRDT_PP_NEXT_PC_Q_STATE_RAM_T;
-
-typedef struct dpp_etm_crdt_dev_interval_t
-{
-    ZXIC_UINT32 dev_interval;
-}DPP_ETM_CRDT_DEV_INTERVAL_T;
-
-typedef struct dpp_etm_crdt_dev_wfq_cnt_t
-{
-    ZXIC_UINT32 dev_wfq_cnt;
-}DPP_ETM_CRDT_DEV_WFQ_CNT_T;
-
-typedef struct dpp_etm_crdt_dev_wfq_state_t
-{
-    ZXIC_UINT32 dev_wfq_state;
-}DPP_ETM_CRDT_DEV_WFQ_STATE_T;
-
-typedef struct dpp_etm_crdt_dev_active_head_ptr_t
-{
-    ZXIC_UINT32 dev_active_head_ptr;
-}DPP_ETM_CRDT_DEV_ACTIVE_HEAD_PTR_T;
-
-typedef struct dpp_etm_crdt_dev_active_tail_ptr_t
-{
-    ZXIC_UINT32 dev_active_tail_ptr;
-}DPP_ETM_CRDT_DEV_ACTIVE_TAIL_PTR_T;
-
-typedef struct dpp_etm_crdt_dev_unactive_head_ptr_t
-{
-    ZXIC_UINT32 dev_unactive_head_ptr;
-}DPP_ETM_CRDT_DEV_UNACTIVE_HEAD_PTR_T;
-
-typedef struct dpp_etm_crdt_dev_unactive_tail_ptr_t
-{
-    ZXIC_UINT32 dev_unactive_tail_ptr;
-}DPP_ETM_CRDT_DEV_UNACTIVE_TAIL_PTR_T;
-
-typedef struct dpp_etm_crdt_pp_weight_t
-{
-    ZXIC_UINT32 pp_weight;
-}DPP_ETM_CRDT_PP_WEIGHT_T;
-
-typedef struct dpp_etm_crdt_pp_que_state_t
-{
-    ZXIC_UINT32 pp_enque_flag;
-    ZXIC_UINT32 pp_cir;
-    ZXIC_UINT32 pp_congest_cir;
-    ZXIC_UINT32 pp_crs;
-    ZXIC_UINT32 dev_sp;
-}DPP_ETM_CRDT_PP_QUE_STATE_T;
-
-typedef struct dpp_etm_crdt_pp_next_ptr_t
-{
-    ZXIC_UINT32 pp_next_ptr;
-}DPP_ETM_CRDT_PP_NEXT_PTR_T;
-
-typedef struct dpp_etm_crdt_pp_cfg_t
-{
-    ZXIC_UINT32 pp_cfg;
-}DPP_ETM_CRDT_PP_CFG_T;
-
-typedef struct dpp_etm_crdt_pp_up_ptr_t
-{
-    ZXIC_UINT32 pp_up_ptr;
-}DPP_ETM_CRDT_PP_UP_PTR_T;
-
-typedef struct dpp_etm_crdt_credit_drop_num_t
-{
-    ZXIC_UINT32 credit_drop_num;
-}DPP_ETM_CRDT_CREDIT_DROP_NUM_T;
-
-typedef struct dpp_etm_crdt_se_id_lv0_t
-{
-    ZXIC_UINT32 se_id_out_lv0;
-}DPP_ETM_CRDT_SE_ID_LV0_T;
-
-typedef struct dpp_etm_crdt_se_id_lv1_t
-{
-    ZXIC_UINT32 se_id_out_lv1;
-}DPP_ETM_CRDT_SE_ID_LV1_T;
-
-typedef struct dpp_etm_crdt_se_id_lv2_t
-{
-    ZXIC_UINT32 se_id_out_lv2;
-}DPP_ETM_CRDT_SE_ID_LV2_T;
-
-typedef struct dpp_etm_crdt_se_id_lv3_t
-{
-    ZXIC_UINT32 se_id_out_lv3;
-}DPP_ETM_CRDT_SE_ID_LV3_T;
-
-typedef struct dpp_etm_crdt_se_id_lv4_t
-{
-    ZXIC_UINT32 se_id_out_lv4;
-}DPP_ETM_CRDT_SE_ID_LV4_T;
-
-typedef struct dpp_etm_crdt_que_id_t
-{
-    ZXIC_UINT32 que_id_out;
-}DPP_ETM_CRDT_QUE_ID_T;
-
-typedef struct dpp_etm_crdt_se_info_lv0_t
-{
-    ZXIC_UINT32 se_shape_lv0;
-    ZXIC_UINT32 se_ins_out_lv0;
-    ZXIC_UINT32 se_state_out_lv0;
-    ZXIC_UINT32 se_new_state_out_lv0;
-}DPP_ETM_CRDT_SE_INFO_LV0_T;
-
-typedef struct dpp_etm_crdt_se_info_lv1_t
-{
-    ZXIC_UINT32 se_shape_lv1;
-    ZXIC_UINT32 se_ins_out_lv1;
-    ZXIC_UINT32 se_state_out_lv1;
-    ZXIC_UINT32 se_new_state_out_lv1;
-}DPP_ETM_CRDT_SE_INFO_LV1_T;
-
-typedef struct dpp_etm_crdt_se_info_lv2_t
-{
-    ZXIC_UINT32 se_shape_lv2;
-    ZXIC_UINT32 se_ins_out_lv2;
-    ZXIC_UINT32 se_state_out_lv2;
-    ZXIC_UINT32 se_new_state_out_lv2;
-}DPP_ETM_CRDT_SE_INFO_LV2_T;
-
-typedef struct dpp_etm_crdt_se_info_lv3_t
-{
-    ZXIC_UINT32 se_shape_lv3;
-    ZXIC_UINT32 se_ins_out_lv3;
-    ZXIC_UINT32 se_state_out_lv3;
-    ZXIC_UINT32 se_new_state_out_lv3;
-}DPP_ETM_CRDT_SE_INFO_LV3_T;
-
-typedef struct dpp_etm_crdt_se_info_lv4_t
-{
-    ZXIC_UINT32 se_shape_lv4;
-    ZXIC_UINT32 se_ins_out_lv4;
-    ZXIC_UINT32 se_state_out_lv4;
-    ZXIC_UINT32 se_new_state_out_lv4;
-}DPP_ETM_CRDT_SE_INFO_LV4_T;
-
-typedef struct dpp_etm_crdt_que_state_t
-{
-    ZXIC_UINT32 que_state_out;
-}DPP_ETM_CRDT_QUE_STATE_T;
-
-typedef struct dpp_etm_crdt_eir_off_in_advance_t
-{
-    ZXIC_UINT32 eir_crs_filter;
-}DPP_ETM_CRDT_EIR_OFF_IN_ADVANCE_T;
-
-typedef struct dpp_etm_crdt_double_level_shap_prevent_t
-{
-    ZXIC_UINT32 double_level_shap_prevent;
-}DPP_ETM_CRDT_DOUBLE_LEVEL_SHAP_PREVENT_T;
-
-typedef struct dpp_etm_crdt_add_store_cycle_t
-{
-    ZXIC_UINT32 add_store_cycle;
-}DPP_ETM_CRDT_ADD_STORE_CYCLE_T;
-
-typedef struct dpp_etm_crdt_tflag2_wr_flag_sum_t
-{
-    ZXIC_UINT32 tflag2_wr_flag_sum;
-}DPP_ETM_CRDT_TFLAG2_WR_FLAG_SUM_T;
-
-typedef struct dpp_etm_crdt_flowque_para_tbl_t
-{
-    ZXIC_UINT32 flowque_link;
-    ZXIC_UINT32 flowque_w;
-    ZXIC_UINT32 flowque_pri;
-}DPP_ETM_CRDT_FLOWQUE_PARA_TBL_T;
-
-typedef struct dpp_etm_crdt_se_para_tbl_t
-{
-    ZXIC_UINT32 se_insw;
-    ZXIC_UINT32 se_link;
-    ZXIC_UINT32 cp_token_en;
-    ZXIC_UINT32 se_w;
-    ZXIC_UINT32 se_pri;
-}DPP_ETM_CRDT_SE_PARA_TBL_T;
-
-typedef struct dpp_etm_crdt_flowque_ins_tbl_t
-{
-    ZXIC_UINT32 flowque_ins;
-}DPP_ETM_CRDT_FLOWQUE_INS_TBL_T;
-
-typedef struct dpp_etm_crdt_se_ins_tbl_t
-{
-    ZXIC_UINT32 se_ins_flag;
-    ZXIC_UINT32 se_ins_priority;
-}DPP_ETM_CRDT_SE_INS_TBL_T;
-
-typedef struct dpp_etm_crdt_eir_crs_filter_tbl_t
-{
-    ZXIC_UINT32 eir_crs_filter;
-}DPP_ETM_CRDT_EIR_CRS_FILTER_TBL_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_cfg_done_t
-{
-    ZXIC_UINT32 qcfg_qlist_cfg_done;
-}DPP_ETM_QMU_QCFG_QLIST_CFG_DONE_T;
-
-typedef struct dpp_etm_qmu_qcfg_qsch_credit_value_t
-{
-    ZXIC_UINT32 qcfg_qsch_credit_value;
-}DPP_ETM_QMU_QCFG_QSCH_CREDIT_VALUE_T;
-
-typedef struct dpp_etm_qmu_qcfg_qsch_crbal_init_value_t
-{
-    ZXIC_UINT32 qcfg_qsch_crbal_init_value;
-}DPP_ETM_QMU_QCFG_QSCH_CRBAL_INIT_VALUE_T;
-
-typedef struct dpp_etm_qmu_qcfg_qsch_crbal_init_mask_t
-{
-    ZXIC_UINT32 qcfg_qsch_crbal_init_mask;
-}DPP_ETM_QMU_QCFG_QSCH_CRBAL_INIT_MASK_T;
-
-typedef struct dpp_etm_qmu_cmdsch_rd_cmd_aful_th_t
-{
-    ZXIC_UINT32 cmdsch_rd_cmd_aful_th;
-}DPP_ETM_QMU_CMDSCH_RD_CMD_AFUL_TH_T;
-
-typedef struct dpp_etm_qmu_cfg_port_fc_interval_t
-{
-    ZXIC_UINT32 cfg_port_fc_interval;
-}DPP_ETM_QMU_CFG_PORT_FC_INTERVAL_T;
-
-typedef struct dpp_etm_qmu_qcfg_csch_aged_cfg_t
-{
-    ZXIC_UINT32 qcfg_csch_aged_cfg;
-}DPP_ETM_QMU_QCFG_CSCH_AGED_CFG_T;
-
-typedef struct dpp_etm_qmu_qcfg_csch_aged_scan_time_t
-{
-    ZXIC_UINT32 qcfg_csch_aged_scan_time;
-}DPP_ETM_QMU_QCFG_CSCH_AGED_SCAN_TIME_T;
-
-typedef struct dpp_etm_qmu_qcfg_qmu_qlist_state_query_t
-{
-    ZXIC_UINT32 pkt_age_req_fifo_afull;
-    ZXIC_UINT32 rd_release_fwft_afull;
-    ZXIC_UINT32 drop_imem_fwft_afull;
-    ZXIC_UINT32 pkt_age_req_fifo_empty;
-    ZXIC_UINT32 rd_release_fwft_empty;
-    ZXIC_UINT32 drop_imem_fwft_empty;
-    ZXIC_UINT32 mmu_qmu_sop_rd_rdy;
-    ZXIC_UINT32 big_fifo_empty;
-    ZXIC_UINT32 qmu_mmu_rd_release_rdy;
-    ZXIC_UINT32 xsw_qmu_crs_rdy;
-    ZXIC_UINT32 mmu_qmu_rdy;
-    ZXIC_UINT32 mmu_ql_wr_rdy;
-    ZXIC_UINT32 mmu_ql_rd_rdy;
-    ZXIC_UINT32 csw_ql_rdy;
-    ZXIC_UINT32 ql_init_done;
-    ZXIC_UINT32 free_addr_ready;
-    ZXIC_UINT32 bank_group_afull;
-    ZXIC_UINT32 pds_fwft_empty;
-    ZXIC_UINT32 enq_rpt_fwft_afull;
-}DPP_ETM_QMU_QCFG_QMU_QLIST_STATE_QUERY_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qsch_crbal_drop_en_t
-{
-    ZXIC_UINT32 cfgmt_qsch_all_crbal_drop_en;
-    ZXIC_UINT32 cfgmt_qsch_crbal_drop_en;
-}DPP_ETM_QMU_CFGMT_QSCH_CRBAL_DROP_EN_T;
-
-typedef struct dpp_etm_qmu_cfgmt_wlist_qnum_fifo_aful_th_t
-{
-    ZXIC_UINT32 cfgmt_wlist_qnum_fifo_aful_th;
-}DPP_ETM_QMU_CFGMT_WLIST_QNUM_FIFO_AFUL_TH_T;
-
-typedef struct dpp_etm_qmu_qcfg_csw_pkt_blk_mode_t
-{
-    ZXIC_UINT32 qcfg_csw_pkt_blk_mode;
-}DPP_ETM_QMU_QCFG_CSW_PKT_BLK_MODE_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_ram_init_cancel_t
-{
-    ZXIC_UINT32 qcfg_qlist_ram_init_cancel;
-}DPP_ETM_QMU_QCFG_QLIST_RAM_INIT_CANCEL_T;
-
-typedef struct dpp_etm_qmu_qcfg_qsch_crbal_transfer_mode_t
-{
-    ZXIC_UINT32 qcfg_qsch_crbal_transfer_mode;
-    ZXIC_UINT32 qcfg_qsch_crbal_transfer_value;
-}DPP_ETM_QMU_QCFG_QSCH_CRBAL_TRANSFER_MODE_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_qclr_interval_t
-{
-    ZXIC_UINT32 qcfg_qlist_qclr_interval;
-}DPP_ETM_QMU_QCFG_QLIST_QCLR_INTERVAL_T;
-
-typedef struct dpp_etm_qmu_qcfg_qsch_qclr_rate_t
-{
-    ZXIC_UINT32 qcfg_qsch_qclr_rate;
-}DPP_ETM_QMU_QCFG_QSCH_QCLR_RATE_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_ddr_random_t
-{
-    ZXIC_UINT32 qcfg_qlist_ddr_random;
-}DPP_ETM_QMU_QCFG_QLIST_DDR_RANDOM_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qlist_pds_fifo_afull_th_t
-{
-    ZXIC_UINT32 cfgmt_qlist_pds_fifo_afull_th;
-}DPP_ETM_QMU_CFGMT_QLIST_PDS_FIFO_AFULL_TH_T;
-
-typedef struct dpp_etm_qmu_cfgmt_sop_cmd_fifo_afull_th_t
-{
-    ZXIC_UINT32 cfgmt_sop_cmd_fifo_afull_th;
-}DPP_ETM_QMU_CFGMT_SOP_CMD_FIFO_AFULL_TH_T;
-
-typedef struct dpp_etm_qmu_cfgmt_non_sop_cmd_fifo_afull_th_t
-{
-    ZXIC_UINT32 cfgmt_non_sop_cmd_fifo_afull_th;
-}DPP_ETM_QMU_CFGMT_NON_SOP_CMD_FIFO_AFULL_TH_T;
-
-typedef struct dpp_etm_qmu_cfgmt_mmu_data_fifo_afull_th_t
-{
-    ZXIC_UINT32 cfgmt_mmu_data_fifo_afull_th;
-}DPP_ETM_QMU_CFGMT_MMU_DATA_FIFO_AFULL_TH_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_bank_ept_th_t
-{
-    ZXIC_UINT32 qcfg_qlist_bank_ept_th;
-}DPP_ETM_QMU_QCFG_QLIST_BANK_EPT_TH_T;
-
-typedef struct dpp_etm_qmu_random_bypass_en_t
-{
-    ZXIC_UINT32 random_bypass_en;
-}DPP_ETM_QMU_RANDOM_BYPASS_EN_T;
-
-typedef struct dpp_etm_qmu_cfgmt_crs_spd_bypass_t
-{
-    ZXIC_UINT32 cfgmt_crs_spd_bypass;
-}DPP_ETM_QMU_CFGMT_CRS_SPD_BYPASS_T;
-
-typedef struct dpp_etm_qmu_cfgmt_crs_interval_t
-{
-    ZXIC_UINT32 cfgmt_crs_interval;
-}DPP_ETM_QMU_CFGMT_CRS_INTERVAL_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_auto_credit_control_en_t
-{
-    ZXIC_UINT32 cfg_qsch_auto_credit_control_en;
-}DPP_ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_EN_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_autocrfrstque_t
-{
-    ZXIC_UINT32 cfg_qsch_autocrfrstque;
-}DPP_ETM_QMU_CFG_QSCH_AUTOCRFRSTQUE_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_autocrlastque_t
-{
-    ZXIC_UINT32 cfg_qsch_autocrlastque;
-}DPP_ETM_QMU_CFG_QSCH_AUTOCRLASTQUE_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_autocreditrate_t
-{
-    ZXIC_UINT32 cfg_qsch_autocreditrate;
-}DPP_ETM_QMU_CFG_QSCH_AUTOCREDITRATE_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_scanfrstque_t
-{
-    ZXIC_UINT32 cfg_qsch_scanfrstque;
-}DPP_ETM_QMU_CFG_QSCH_SCANFRSTQUE_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_scanlastque_t
-{
-    ZXIC_UINT32 cfg_qsch_scanlastque;
-}DPP_ETM_QMU_CFG_QSCH_SCANLASTQUE_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_scanrate_t
-{
-    ZXIC_UINT32 cfg_qsch_scanrate;
-}DPP_ETM_QMU_CFG_QSCH_SCANRATE_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_scan_en_t
-{
-    ZXIC_UINT32 cfg_qsch_scan_en;
-}DPP_ETM_QMU_CFG_QSCH_SCAN_EN_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qsch_rd_credit_fifo_rate_t
-{
-    ZXIC_UINT32 cfgmt_qsch_rd_credit_fifo_rate;
-}DPP_ETM_QMU_CFGMT_QSCH_RD_CREDIT_FIFO_RATE_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_bdep_t
-{
-    ZXIC_UINT32 qcfg_qlist_bdep;
-}DPP_ETM_QMU_QCFG_QLIST_BDEP_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_bhead_t
-{
-    ZXIC_UINT32 bank_vld;
-    ZXIC_UINT32 qcfg_qlist_bhead;
-}DPP_ETM_QMU_QCFG_QLIST_BHEAD_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_btail_t
-{
-    ZXIC_UINT32 qcfg_qlist_btail;
-}DPP_ETM_QMU_QCFG_QLIST_BTAIL_T;
-
-typedef struct dpp_etm_qmu_qcfg_qsch_shap_param_t
-{
-    ZXIC_UINT32 qcfg_qsch_shap_en;
-    ZXIC_UINT32 qcfg_qsch_shap_param1;
-    ZXIC_UINT32 qcfg_qsch_shap_param2;
-}DPP_ETM_QMU_QCFG_QSCH_SHAP_PARAM_T;
-
-typedef struct dpp_etm_qmu_qcfg_qsch_shap_token_t
-{
-    ZXIC_UINT32 qcfg_qsch_shap_token;
-}DPP_ETM_QMU_QCFG_QSCH_SHAP_TOKEN_T;
-
-typedef struct dpp_etm_qmu_qcfg_qsch_shap_offset_t
-{
-    ZXIC_UINT32 qcfg_qsch_shap_offset;
-}DPP_ETM_QMU_QCFG_QSCH_SHAP_OFFSET_T;
-
-typedef struct dpp_etm_qmu_qcfg_qsch_crs_eir_th_t
-{
-    ZXIC_UINT32 qcfg_qsch_crs_eir_th;
-}DPP_ETM_QMU_QCFG_QSCH_CRS_EIR_TH_T;
-
-typedef struct dpp_etm_qmu_qcfg_qsch_crs_th1_t
-{
-    ZXIC_UINT32 qcfg_qsch_crs_th1;
-}DPP_ETM_QMU_QCFG_QSCH_CRS_TH1_T;
-
-typedef struct dpp_etm_qmu_qcfg_qsch_crs_th2_t
-{
-    ZXIC_UINT32 qcfg_qsch_crs_th2;
-}DPP_ETM_QMU_QCFG_QSCH_CRS_TH2_T;
-
-typedef struct dpp_etm_qmu_qcfg_csch_congest_th_t
-{
-    ZXIC_UINT32 qcfg_csch_congest_th;
-}DPP_ETM_QMU_QCFG_CSCH_CONGEST_TH_T;
-
-typedef struct dpp_etm_qmu_qcfg_csch_sp_fc_th_t
-{
-    ZXIC_UINT32 qcfg_csch_sp_fc_th;
-}DPP_ETM_QMU_QCFG_CSCH_SP_FC_TH_T;
-
-typedef struct dpp_etm_qmu_qcfg_csw_shap_parameter_t
-{
-    ZXIC_UINT32 qcfg_csw_shap_en;
-    ZXIC_UINT32 qcfg_csw_shap_parameter;
-}DPP_ETM_QMU_QCFG_CSW_SHAP_PARAMETER_T;
-
-typedef struct dpp_etm_qmu_cfgmt_rd_release_aful_th_t
-{
-    ZXIC_UINT32 cfgmt_rd_release_aful_th;
-}DPP_ETM_QMU_CFGMT_RD_RELEASE_AFUL_TH_T;
-
-typedef struct dpp_etm_qmu_cfgmt_drop_imem_release_fifo_aful_th_t
-{
-    ZXIC_UINT32 cfgmt_drop_imem_release_fifo_aful_th;
-}DPP_ETM_QMU_CFGMT_DROP_IMEM_RELEASE_FIFO_AFUL_TH_T;
-
-typedef struct dpp_etm_qmu_cfgmt_nnh_rd_buf_aful_th_t
-{
-    ZXIC_UINT32 cfgmt_nnh_rd_buf_aful_th;
-}DPP_ETM_QMU_CFGMT_NNH_RD_BUF_AFUL_TH_T;
-
-typedef struct dpp_etm_qmu_cfg_pid_use_inall_t
-{
-    ZXIC_UINT32 cfgmt_nod_rd_buf_0_aful_th;
-}DPP_ETM_QMU_CFG_PID_USE_INALL_T;
-
-typedef struct dpp_etm_qmu_cfg_pid_round_th_t
-{
-    ZXIC_UINT32 cfgmt_nod_rd_buf_1_aful_th;
-}DPP_ETM_QMU_CFG_PID_ROUND_TH_T;
-
-typedef struct dpp_etm_qmu_cfgmt_credit_fifo_afull_th_t
-{
-    ZXIC_UINT32 cfgmt_credit_fifo_afull_th;
-}DPP_ETM_QMU_CFGMT_CREDIT_FIFO_AFULL_TH_T;
-
-typedef struct dpp_etm_qmu_cfgmt_scan_fifo_afull_th_t
-{
-    ZXIC_UINT32 cfgmt_scan_fifo_afull_th;
-}DPP_ETM_QMU_CFGMT_SCAN_FIFO_AFULL_TH_T;
-
-typedef struct dpp_etm_qmu_cfgmt_small_fifo_aful_th_t
-{
-    ZXIC_UINT32 cfgmt_small_fifo_aful_th;
-}DPP_ETM_QMU_CFGMT_SMALL_FIFO_AFUL_TH_T;
-
-typedef struct dpp_etm_qmu_cfgmt_free_addr_fifo_aful_th_t
-{
-    ZXIC_UINT32 cfgmt_free_addr_fifo_aful_th;
-}DPP_ETM_QMU_CFGMT_FREE_ADDR_FIFO_AFUL_TH_T;
-
-typedef struct dpp_etm_qmu_cfgmt_enq_rpt_fifo_aful_th_t
-{
-    ZXIC_UINT32 cfgmt_enq_rpt_fifo_aful_th;
-}DPP_ETM_QMU_CFGMT_ENQ_RPT_FIFO_AFUL_TH_T;
-
-typedef struct dpp_etm_qmu_qcfg_csw_shap_token_depth_t
-{
-    ZXIC_UINT32 qcfg_csw_shap_token_depth;
-}DPP_ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTH_T;
-
-typedef struct dpp_etm_qmu_qcfg_csw_shap_offset_value_t
-{
-    ZXIC_UINT32 qcfg_csw_shap_offset_value;
-}DPP_ETM_QMU_QCFG_CSW_SHAP_OFFSET_VALUE_T;
-
-typedef struct dpp_etm_qmu_qcfg_csw_fc_offset_value_t
-{
-    ZXIC_UINT32 qcfg_csw_fc_offset_value;
-}DPP_ETM_QMU_QCFG_CSW_FC_OFFSET_VALUE_T;
-
-typedef struct dpp_etm_qmu_qmu_init_done_state_t
-{
-    ZXIC_UINT32 csch_qcfg_init_done;
-    ZXIC_UINT32 qsch_qcfg_init_done;
-    ZXIC_UINT32 qlist_qcfg_init_done;
-    ZXIC_UINT32 qcsr_ram_init_done;
-}DPP_ETM_QMU_QMU_INIT_DONE_STATE_T;
-
-typedef struct dpp_etm_qmu_csw_qcfg_port_shap_rdy_0_t
-{
-    ZXIC_UINT32 csw_qcfg_port_shap_rdy_0;
-}DPP_ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_0_T;
-
-typedef struct dpp_etm_qmu_csw_qcfg_port_shap_rdy_1_t
-{
-    ZXIC_UINT32 csw_qcfg_port_shap_rdy_1;
-}DPP_ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_1_T;
-
-typedef struct dpp_etm_qmu_qlist_cfgmt_ram_init_done_t
-{
-    ZXIC_UINT32 qlist_qcfg_qds_ram_init_done;
-    ZXIC_UINT32 qlist_qcfg_chk_ram_init_done;
-    ZXIC_UINT32 qlist_qcfg_ept_ram_init_done;
-    ZXIC_UINT32 qlist_qcfg_cti_ram_init_done;
-    ZXIC_UINT32 qlist_qcfg_cto_ram_init_done;
-    ZXIC_UINT32 qlist_qcfg_bcnt_ram_init_done;
-    ZXIC_UINT32 qlist_qcfg_biu_ram_init_done;
-    ZXIC_UINT32 qlist_qcfg_baram_init_done;
-}DPP_ETM_QMU_QLIST_CFGMT_RAM_INIT_DONE_T;
-
-typedef struct dpp_etm_qmu_qlist_cfgmt_ram_ecc_err_t
-{
-    ZXIC_UINT32 qds_ram_parity_err;
-    ZXIC_UINT32 qcsr_qnum_fifo_parity_err;
-    ZXIC_UINT32 sa_id_ram_parity_err;
-    ZXIC_UINT32 enq_rpt_fifo_parity_err;
-    ZXIC_UINT32 bcnts_parity_err;
-    ZXIC_UINT32 baram_parity_err_a;
-    ZXIC_UINT32 baram_parity_err_b;
-    ZXIC_UINT32 bcntm_ram_parity_err;
-    ZXIC_UINT32 biu_ram_single_ecc_err;
-    ZXIC_UINT32 chk_ram_single_ecc_err;
-    ZXIC_UINT32 cmd_sch_cmd_ram_single_ecc_err;
-    ZXIC_UINT32 cmd_sch_list_ram_single_ecc_err;
-    ZXIC_UINT32 cmd_sch_hp_ram_single_ecc_err;
-    ZXIC_UINT32 cmd_sch_tp_ram_single_ecc_err;
-    ZXIC_UINT32 cmd_sch_enq_active_ram_single_ecc_err;
-    ZXIC_UINT32 cmd_sch_deq_active_ram_single_ecc_err;
-    ZXIC_UINT32 cmd_sch_empty_ram_single_ecc_err;
-    ZXIC_UINT32 cmd_sch_eop_ram_single_ecc_err;
-    ZXIC_UINT32 cmd_sch_blkcnt_ram_single_ecc_err;
-    ZXIC_UINT32 biu_ram_double_ecc_err;
-    ZXIC_UINT32 chk_ram_double_ecc_err;
-    ZXIC_UINT32 cmd_sch_cmd_ram_double_ecc_err;
-    ZXIC_UINT32 cmd_sch_list_ram_double_ecc_err;
-    ZXIC_UINT32 cmd_sch_hp_ram_double_ecc_err;
-    ZXIC_UINT32 cmd_sch_tp_ram_double_ecc_err;
-    ZXIC_UINT32 cmd_sch_enq_active_ram_double_ecc_err;
-    ZXIC_UINT32 cmd_sch_deq_active_ram_double_ecc_err;
-    ZXIC_UINT32 cmd_sch_empty_ram_double_ecc_err;
-    ZXIC_UINT32 cmd_sch_eop_ram_double_ecc_err;
-    ZXIC_UINT32 cmd_sch_blkcnt_ram_double_ecc_err;
-}DPP_ETM_QMU_QLIST_CFGMT_RAM_ECC_ERR_T;
-
-typedef struct dpp_etm_qmu_qlist_cfgmt_ram_slot_err_t
-{
-    ZXIC_UINT32 qds_ram_enq_rd_slot_err;
-    ZXIC_UINT32 qds_ram_deq_rd_slot_err;
-    ZXIC_UINT32 qds_ram_enq_wr_slot_err;
-    ZXIC_UINT32 qds_ram_deq_wr_slot_err;
-    ZXIC_UINT32 chk_ram_enq_rd_slot_err;
-    ZXIC_UINT32 chk_ram_deq_rd_slot_err;
-    ZXIC_UINT32 chk_ram_enq_wr_slot_err;
-    ZXIC_UINT32 chk_ram_deq_wr_slot_err;
-    ZXIC_UINT32 ept_ram_enq_rd_slot_err;
-    ZXIC_UINT32 ept_ram_deq_rd_slot_err;
-    ZXIC_UINT32 ept_ram_enq_wr_slot_err;
-    ZXIC_UINT32 ept_ram_deq_wr_slot_err;
-    ZXIC_UINT32 cti_ram_enq_rd_slot_err;
-    ZXIC_UINT32 cti_ram_deq_rd_slot_err;
-    ZXIC_UINT32 cti_ram_enq_wr_slot_err;
-    ZXIC_UINT32 cti_ram_deq_wr_slot_err;
-    ZXIC_UINT32 cto_ram_enq_rd_slot_err;
-    ZXIC_UINT32 cto_ram_deq_rd_slot_err;
-    ZXIC_UINT32 cto_ram_enq_wr_slot_err;
-    ZXIC_UINT32 cto_ram_deq_wr_slot_err;
-}DPP_ETM_QMU_QLIST_CFGMT_RAM_SLOT_ERR_T;
-
-typedef struct dpp_etm_qmu_qsch_cfgmt_ram_ecc_t
-{
-    ZXIC_UINT32 crbal_rama_parity_error;
-    ZXIC_UINT32 crbal_ramb_parity_error;
-    ZXIC_UINT32 crs_ram_parity_error;
-    ZXIC_UINT32 wlist_flag_ram_single_ecc_err;
-    ZXIC_UINT32 wlist_next_single_ecc_err;
-    ZXIC_UINT32 wlist_wactive_ram_single_ecc_err;
-    ZXIC_UINT32 wlist_ractive_ram_single_ecc_err;
-    ZXIC_UINT32 wlist_tp1_ram_single_ecc_err;
-    ZXIC_UINT32 wlist_tp2_ram_single_ecc_err;
-    ZXIC_UINT32 wlist_empty1_ram_single_ecc_err_a;
-    ZXIC_UINT32 wlist_empty1_ram_single_ecc_err_b;
-    ZXIC_UINT32 wlist_empty2_ram_single_ecc_err_a;
-    ZXIC_UINT32 wlist_empty2_ram_single_ecc_err_b;
-    ZXIC_UINT32 wlist_hp_ram_single_ecc_err_a;
-    ZXIC_UINT32 wlist_hp_ram_single_ecc_err_b;
-    ZXIC_UINT32 wlist_flag_ram_double_ecc_err;
-    ZXIC_UINT32 wlist_next_double_ecc_err;
-    ZXIC_UINT32 wlist_wactive_ram_double_ecc_err;
-    ZXIC_UINT32 wlist_ractive_ram_double_ecc_err;
-    ZXIC_UINT32 wlist_tp1_ram_double_ecc_err;
-    ZXIC_UINT32 wlist_tp2_ram_double_ecc_err;
-    ZXIC_UINT32 wlist_empty1_ram_double_ecc_err_a;
-    ZXIC_UINT32 wlist_empty1_ram_double_ecc_err_b;
-    ZXIC_UINT32 wlist_empty2_ram_double_ecc_err_a;
-    ZXIC_UINT32 wlist_empty2_ram_double_ecc_err_b;
-    ZXIC_UINT32 wlist_hp_ram_double_ecc_err_a;
-    ZXIC_UINT32 wlist_hp_ram_double_ecc_err_b;
-}DPP_ETM_QMU_QSCH_CFGMT_RAM_ECC_T;
-
-typedef struct dpp_etm_qmu_qlist_cfgmt_fifo_state_t
-{
-    ZXIC_UINT32 pkt_age_req_fifo_overflow;
-    ZXIC_UINT32 pkt_age_req_fifo_underflow;
-    ZXIC_UINT32 qcsr_big_fifo_ovfl;
-    ZXIC_UINT32 qcsr_small_fifo_overflow;
-    ZXIC_UINT32 enq_rpt_fifo_overflow;
-    ZXIC_UINT32 enq_rpt_fifo_underflow;
-    ZXIC_UINT32 pds_fwft_overflow;
-    ZXIC_UINT32 pds_fwft_underflow;
-    ZXIC_UINT32 free_addr_fifo_overflow;
-    ZXIC_UINT32 free_addr_fifo_underflow;
-    ZXIC_UINT32 rd_release_fwft_overflow;
-    ZXIC_UINT32 rd_release_fwft_underflow;
-    ZXIC_UINT32 pid_free_list_overflow;
-    ZXIC_UINT32 pid_free_list_underflow;
-    ZXIC_UINT32 pid_prp_list_overflow;
-    ZXIC_UINT32 pid_prp_list_underflow;
-    ZXIC_UINT32 pid_rdy_list_overflow;
-    ZXIC_UINT32 pid_rdy_list_underflow;
-    ZXIC_UINT32 drop_imem_release_fwft_overflow;
-    ZXIC_UINT32 drop_imem_release_fwft_underflow;
-    ZXIC_UINT32 nnh_rd_buf_fifo_overflow;
-    ZXIC_UINT32 nnh_rd_buf_fifo_underflow;
-    ZXIC_UINT32 nod_rd_buf_0_fifo_overflow;
-    ZXIC_UINT32 nod_rd_buf_0_fifo_underflow;
-    ZXIC_UINT32 nod_rd_buf_1_fifo_overflow;
-    ZXIC_UINT32 nod_rd_buf_1_fifo_underflow;
-}DPP_ETM_QMU_QLIST_CFGMT_FIFO_STATE_T;
-
-typedef struct dpp_etm_qmu_qlist_qcfg_clr_done_t
-{
-    ZXIC_UINT32 qlist_qcfg_clr_done;
-}DPP_ETM_QMU_QLIST_QCFG_CLR_DONE_T;
-
-typedef struct dpp_etm_qmu_qmu_int_mask1_t
-{
-    ZXIC_UINT32 qmu_int_mask1;
-}DPP_ETM_QMU_QMU_INT_MASK1_T;
-
-typedef struct dpp_etm_qmu_qmu_int_mask2_t
-{
-    ZXIC_UINT32 qmu_int_mask2;
-}DPP_ETM_QMU_QMU_INT_MASK2_T;
-
-typedef struct dpp_etm_qmu_qmu_int_mask3_t
-{
-    ZXIC_UINT32 qmu_int_mask3;
-}DPP_ETM_QMU_QMU_INT_MASK3_T;
-
-typedef struct dpp_etm_qmu_qmu_int_mask4_t
-{
-    ZXIC_UINT32 qmu_int_mask4;
-}DPP_ETM_QMU_QMU_INT_MASK4_T;
-
-typedef struct dpp_etm_qmu_qmu_int_mask5_t
-{
-    ZXIC_UINT32 qmu_int_mask5;
-}DPP_ETM_QMU_QMU_INT_MASK5_T;
-
-typedef struct dpp_etm_qmu_qmu_int_mask6_t
-{
-    ZXIC_UINT32 qmu_int_mask6;
-}DPP_ETM_QMU_QMU_INT_MASK6_T;
-
-typedef struct dpp_etm_qmu_cmd_sch_cfgmt_fifo_state_t
-{
-    ZXIC_UINT32 nsop_fifo_parity_err;
-    ZXIC_UINT32 cmdsch_rd_cmd_fifo_parity_err;
-    ZXIC_UINT32 sop_fifo_afull;
-    ZXIC_UINT32 sop_fifo_empty;
-    ZXIC_UINT32 sop_fifo_overflow;
-    ZXIC_UINT32 sop_fifo_underflow;
-    ZXIC_UINT32 mmu_data_fifo_afull;
-    ZXIC_UINT32 mmu_data_fifo_empty;
-    ZXIC_UINT32 mmudat_fifo_overflow;
-    ZXIC_UINT32 mmudat_fifo_underflow;
-    ZXIC_UINT32 non_sop_fifo_afull;
-    ZXIC_UINT32 non_sop_fifo_empty;
-    ZXIC_UINT32 nsop_fifo_overflow;
-    ZXIC_UINT32 nsop_fifo_underflow;
-    ZXIC_UINT32 cmdsch_rd_cmd_fifo_afull;
-    ZXIC_UINT32 cmdsch_rd_cmd_fifo_empty;
-    ZXIC_UINT32 cmdsch_rd_cmd_fifo_overflow;
-    ZXIC_UINT32 cmdsch_rd_cmd_fifo_underflow;
-    ZXIC_UINT32 wlist_qnum_fifo_overflow;
-    ZXIC_UINT32 wlist_qnum_fifo_underflow;
-    ZXIC_UINT32 qsch_scan_fifo_overflow;
-    ZXIC_UINT32 qsch_scan_fifo_underflow;
-    ZXIC_UINT32 qsch_credit_fifo_overflow;
-    ZXIC_UINT32 qsch_credit_fifo_underflow;
-    ZXIC_UINT32 qsch_credit_fifo2_overflow;
-    ZXIC_UINT32 qsch_credit_fifo2_underflow;
-}DPP_ETM_QMU_CMD_SCH_CFGMT_FIFO_STATE_T;
-
-typedef struct dpp_etm_qmu_qlist_r_bcnt_t
-{
-    ZXIC_UINT32 qlist_r_bcnt;
-}DPP_ETM_QMU_QLIST_R_BCNT_T;
-
-typedef struct dpp_etm_qmu_qsch_rw_crbal_t
-{
-    ZXIC_UINT32 qsch_rw_crbal;
-}DPP_ETM_QMU_QSCH_RW_CRBAL_T;
-
-typedef struct dpp_etm_qmu_qsch_rw_crs_t
-{
-    ZXIC_UINT32 qsch_rw_crs;
-}DPP_ETM_QMU_QSCH_RW_CRS_T;
-
-typedef struct dpp_etm_qmu_qsch_r_wlist_empty_t
-{
-    ZXIC_UINT32 qsch_r_wlist_empty;
-}DPP_ETM_QMU_QSCH_R_WLIST_EMPTY_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_baram_rd_t
-{
-    ZXIC_UINT32 qcfg_qlist_baram_rd;
-}DPP_ETM_QMU_QCFG_QLIST_BARAM_RD_T;
-
-typedef struct dpp_etm_qmu_qcfg_qsch_crbal_fb_rw_t
-{
-    ZXIC_UINT32 qcfg_qlist_crbal_fb_rw;
-}DPP_ETM_QMU_QCFG_QSCH_CRBAL_FB_RW_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_grp0_bank_t
-{
-    ZXIC_UINT32 qcfg_qlist_grp0_bank_wr;
-}DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_grp1_bank_t
-{
-    ZXIC_UINT32 qcfg_qlist_grp1_bank_wr;
-}DPP_ETM_QMU_QCFG_QLIST_GRP1_BANK_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_grp2_bank_t
-{
-    ZXIC_UINT32 qcfg_qlist_grp2_bank_wr;
-}DPP_ETM_QMU_QCFG_QLIST_GRP2_BANK_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_grp3_bank_t
-{
-    ZXIC_UINT32 qcfg_qlist_grp3_bank_wr;
-}DPP_ETM_QMU_QCFG_QLIST_GRP3_BANK_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_grp4_bank_t
-{
-    ZXIC_UINT32 qcfg_qlist_grp4_bank_wr;
-}DPP_ETM_QMU_QCFG_QLIST_GRP4_BANK_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_grp5_bank_t
-{
-    ZXIC_UINT32 qcfg_qlist_grp5_bank_wr;
-}DPP_ETM_QMU_QCFG_QLIST_GRP5_BANK_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_grp6_bank_t
-{
-    ZXIC_UINT32 qcfg_qlist_grp6_bank_wr;
-}DPP_ETM_QMU_QCFG_QLIST_GRP6_BANK_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_grp7_bank_t
-{
-    ZXIC_UINT32 qcfg_qlist_grp7_bank_wr;
-}DPP_ETM_QMU_QCFG_QLIST_GRP7_BANK_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_grp_t
-{
-    ZXIC_UINT32 qcfg_qlist_grp_wr;
-}DPP_ETM_QMU_QCFG_QLIST_GRP_T;
-
-typedef struct dpp_etm_qmu_cfgmt_active_to_bank_cfg_t
-{
-    ZXIC_UINT32 cfgmt_active_to_bank_cfg;
-}DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T;
-
-typedef struct dpp_etm_qmu_cfgmt_ddr_in_mmu_cfg_t
-{
-    ZXIC_UINT32 cfgmt_ddr_in_mmu_cfg;
-}DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T;
-
-typedef struct dpp_etm_qmu_cfgmt_ddr_in_qmu_cfg_t
-{
-    ZXIC_UINT32 cfgmt_ddr_in_qmu_cfg;
-}DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T;
-
-typedef struct dpp_etm_qmu_cfgmt_bank_to_mmu_cfg_t
-{
-    ZXIC_UINT32 cfgmt_bank_in_mmu_cfg;
-}DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T;
-
-typedef struct dpp_etm_qmu_cfgmt_bank_to_qmu_cfg_t
-{
-    ZXIC_UINT32 cfgmt_bank_in_qmu_cfg;
-}DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T;
-
-typedef struct dpp_etm_qmu_cfgmt_grp_ram_n_clr_thd_t
-{
-    ZXIC_UINT32 cfgmt_grp_ram_n_clr_thd;
-}DPP_ETM_QMU_CFGMT_GRP_RAM_N_CLR_THD_T;
-
-typedef struct dpp_etm_qmu_cfgmt_age_pkt_num_t
-{
-    ZXIC_UINT32 cfgmt_age_pkt_num;
-}DPP_ETM_QMU_CFGMT_AGE_PKT_NUM_T;
-
-typedef struct dpp_etm_qmu_cfgmt_age_multi_interval_t
-{
-    ZXIC_UINT32 cfgmt_age_multi_interval;
-}DPP_ETM_QMU_CFGMT_AGE_MULTI_INTERVAL_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_pkt_age_en_t
-{
-    ZXIC_UINT32 cfgmt_qmu_pkt_age_en;
-}DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_EN_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_pkt_age_interval_t
-{
-    ZXIC_UINT32 cfgmt_qmu_pkt_age_interval;
-}DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_INTERVAL_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_pkt_age_start_end_t
-{
-    ZXIC_UINT32 cfgmt_qmu_pkt_age_end;
-    ZXIC_UINT32 cfgmt_qmu_pkt_age_start;
-}DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_START_END_T;
-
-typedef struct dpp_etm_qmu_cfgmt_pkt_age_req_aful_th_t
-{
-    ZXIC_UINT32 cfgmt_pkt_age_req_aful_th;
-}DPP_ETM_QMU_CFGMT_PKT_AGE_REQ_AFUL_TH_T;
-
-typedef struct dpp_etm_qmu_cfgmt_pkt_age_step_interval_t
-{
-    ZXIC_UINT32 cfgmt_pkt_age_step_interval;
-}DPP_ETM_QMU_CFGMT_PKT_AGE_STEP_INTERVAL_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_imem_age_mode_t
-{
-    ZXIC_UINT32 cfgmt_qmu_imem_age_en;
-    ZXIC_UINT32 cfgmt_qmu_imem_age_qlen_en;
-    ZXIC_UINT32 cfgmt_qmu_imem_age_time_en;
-}DPP_ETM_QMU_CFGMT_QMU_IMEM_AGE_MODE_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_imem_qlen_age_interval_t
-{
-    ZXIC_UINT32 cfgmt_qmu_imem_qlen_age_interval;
-}DPP_ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_INTERVAL_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_imem_time_age_interval_t
-{
-    ZXIC_UINT32 cfgmt_qmu_imem_time_age_interval;
-}DPP_ETM_QMU_CFGMT_QMU_IMEM_TIME_AGE_INTERVAL_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_imem_qlen_age_thd_t
-{
-    ZXIC_UINT32 cfgmt_qmu_imem_qlen_age_thd;
-}DPP_ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_THD_T;
-
-typedef struct dpp_etm_qmu_cfgmt_imem_age_step_interval_t
-{
-    ZXIC_UINT32 cfgmt_imem_age_step_interval;
-}DPP_ETM_QMU_CFGMT_IMEM_AGE_STEP_INTERVAL_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_ecc_bypass_read_t
-{
-    ZXIC_UINT32 cfgmt_qmu_ecc_bypass_read;
-}DPP_ETM_QMU_CFGMT_QMU_ECC_BYPASS_READ_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_resp_stat_fc_en_t
-{
-    ZXIC_UINT32 cfgmt_qmu_resp_stat_fc_en;
-}DPP_ETM_QMU_CFGMT_QMU_RESP_STAT_FC_EN_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_bank_xoff_pds_mode_t
-{
-    ZXIC_UINT32 cfgmt_qmu_bank_xoff_pds_mode;
-}DPP_ETM_QMU_CFGMT_QMU_BANK_XOFF_PDS_MODE_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_stat_offset_t
-{
-    ZXIC_UINT32 cfgmt_qmu_stat_offset;
-}DPP_ETM_QMU_CFGMT_QMU_STAT_OFFSET_T;
-
-typedef struct dpp_etm_qmu_fc_cnt_mode_t
-{
-    ZXIC_UINT32 fc_cnt_mode;
-}DPP_ETM_QMU_FC_CNT_MODE_T;
-
-typedef struct dpp_etm_qmu_mmu_qmu_wr_fc_cnt_t
-{
-    ZXIC_UINT32 mmu_qmu_wr_fc_cnt;
-}DPP_ETM_QMU_MMU_QMU_WR_FC_CNT_T;
-
-typedef struct dpp_etm_qmu_mmu_qmu_rd_fc_cnt_t
-{
-    ZXIC_UINT32 mmu_qmu_rd_fc_cnt;
-}DPP_ETM_QMU_MMU_QMU_RD_FC_CNT_T;
-
-typedef struct dpp_etm_qmu_qmu_cgavd_fc_cnt_t
-{
-    ZXIC_UINT32 qmu_cgavd_fc_cnt;
-}DPP_ETM_QMU_QMU_CGAVD_FC_CNT_T;
-
-typedef struct dpp_etm_qmu_cgavd_qmu_pkt_cnt_t
-{
-    ZXIC_UINT32 cgavd_qmu_pkt_cnt;
-}DPP_ETM_QMU_CGAVD_QMU_PKT_CNT_T;
-
-typedef struct dpp_etm_qmu_cgavd_qmu_pktlen_all_t
-{
-    ZXIC_UINT32 cgavd_qmu_pktlen_all;
-}DPP_ETM_QMU_CGAVD_QMU_PKTLEN_ALL_T;
-
-typedef struct dpp_etm_qmu_observe_portfc_spec_t
-{
-    ZXIC_UINT32 observe_portfc_spec;
-}DPP_ETM_QMU_OBSERVE_PORTFC_SPEC_T;
-
-typedef struct dpp_etm_qmu_spec_lif_portfc_count_t
-{
-    ZXIC_UINT32 spec_lif_portfc_count;
-}DPP_ETM_QMU_SPEC_LIF_PORTFC_COUNT_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_pfc_en_t
-{
-    ZXIC_UINT32 cfgmt_qmu_pfc_en;
-}DPP_ETM_QMU_CFGMT_QMU_PFC_EN_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_pfc_mask_1_t
-{
-    ZXIC_UINT32 cfgmt_qmu_pfc_mask_1;
-}DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_1_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_pfc_mask_2_t
-{
-    ZXIC_UINT32 cfgmt_qmu_pfc_mask_2;
-}DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_2_T;
-
-typedef struct dpp_etm_cfgmt_chip_version_reg_t
-{
-    ZXIC_UINT32 chip_version_reg;
-    ZXIC_UINT32 chip_sub_reg;
-    ZXIC_UINT32 chip_type_reg;
-}DPP_ETM_CFGMT_CHIP_VERSION_REG_T;
-
-typedef struct dpp_etm_cfgmt_chip_date_reg_t
-{
-    ZXIC_UINT32 chip_date_reg;
-}DPP_ETM_CFGMT_CHIP_DATE_REG_T;
-
-typedef struct dpp_etm_cfgmt_cfgmt_crc_en_t
-{
-    ZXIC_UINT32 cfgmt_crc_en;
-}DPP_ETM_CFGMT_CFGMT_CRC_EN_T;
-
-typedef struct dpp_etm_cfgmt_cfg_port_transfer_en_t
-{
-    ZXIC_UINT32 cfg_port_transfer_en;
-}DPP_ETM_CFGMT_CFG_PORT_TRANSFER_EN_T;
-
-typedef struct dpp_etm_cfgmt_tm_sa_work_mode_t
-{
-    ZXIC_UINT32 tm_sa_work_mode;
-}DPP_ETM_CFGMT_TM_SA_WORK_MODE_T;
-
-typedef struct dpp_etm_cfgmt_local_sa_id_t
-{
-    ZXIC_UINT32 local_sa_id;
-}DPP_ETM_CFGMT_LOCAL_SA_ID_T;
-
-typedef struct dpp_etm_olif_olif_rdy_t
-{
-    ZXIC_UINT32 cfgmt_block_mode;
-    ZXIC_UINT32 cfgmt_count_overflow_mode;
-    ZXIC_UINT32 cfgmt_count_rd_mode;
-    ZXIC_UINT32 olif_rdy;
-}DPP_ETM_OLIF_OLIF_RDY_T;
-
-typedef struct dpp_etm_olif_emem_prog_full_t
-{
-    ZXIC_UINT32 emem_prog_full_assert;
-    ZXIC_UINT32 emem_prog_full_negate;
-}DPP_ETM_OLIF_EMEM_PROG_FULL_T;
-
-typedef struct dpp_etm_olif_port_order_fifo_full_t
-{
-    ZXIC_UINT32 port_order_fifo_full_assert;
-    ZXIC_UINT32 port_order_fifo_full_negate;
-}DPP_ETM_OLIF_PORT_ORDER_FIFO_FULL_T;
-
-typedef struct dpp_etm_olif_olif_release_last_t
-{
-    ZXIC_UINT32 olif_release_last_addr;
-    ZXIC_UINT32 olif_release_last_bank;
-}DPP_ETM_OLIF_OLIF_RELEASE_LAST_T;
-
-typedef struct dpp_etm_olif_olif_fifo_empty_state_t
-{
-    ZXIC_UINT32 qmu_para_fifo_empty;
-    ZXIC_UINT32 emem_empty;
-    ZXIC_UINT32 imem_empty;
-}DPP_ETM_OLIF_OLIF_FIFO_EMPTY_STATE_T;
-
-typedef struct dpp_etm_olif_qmu_olif_release_fc_cnt_t
-{
-    ZXIC_UINT32 qmu_olif_release_fc_cnt;
-}DPP_ETM_OLIF_QMU_OLIF_RELEASE_FC_CNT_T;
-
-typedef struct dpp_etm_olif_olif_qmu_link_fc_cnt_t
-{
-    ZXIC_UINT32 olif_qmu_link_fc_cnt;
-}DPP_ETM_OLIF_OLIF_QMU_LINK_FC_CNT_T;
-
-typedef struct dpp_etm_olif_lif0_link_fc_cnt_t
-{
-    ZXIC_UINT32 lif0_link_fc_cnt;
-}DPP_ETM_OLIF_LIF0_LINK_FC_CNT_T;
-
-typedef struct dpp_etm_olif_olif_tmmu_fc_cnt_t
-{
-    ZXIC_UINT32 olif_tmmu_fc_cnt;
-}DPP_ETM_OLIF_OLIF_TMMU_FC_CNT_T;
-
-typedef struct dpp_etm_olif_olif_mmu_fc_cnt_t
-{
-    ZXIC_UINT32 olif_mmu_fc_cnt;
-}DPP_ETM_OLIF_OLIF_MMU_FC_CNT_T;
-
-typedef struct dpp_etm_olif_olif_qmu_port_rdy_h_t
-{
-    ZXIC_UINT32 olif_qmu_port_rdy_h;
-}DPP_ETM_OLIF_OLIF_QMU_PORT_RDY_H_T;
-
-typedef struct dpp_etm_olif_olif_qmu_port_rdy_l_t
-{
-    ZXIC_UINT32 olif_qmu_port_rdy_l;
-}DPP_ETM_OLIF_OLIF_QMU_PORT_RDY_L_T;
-
-typedef struct dpp_etm_olif_lif0_port_rdy_h_t
-{
-    ZXIC_UINT32 lif0_port_rdy_h;
-}DPP_ETM_OLIF_LIF0_PORT_RDY_H_T;
-
-typedef struct dpp_etm_olif_lif0_port_rdy_l_t
-{
-    ZXIC_UINT32 lif0_port_rdy_l;
-}DPP_ETM_OLIF_LIF0_PORT_RDY_L_T;
-
-typedef struct dpp_etm_olif_qmu_olif_rd_sop_cnt_t
-{
-    ZXIC_UINT32 qmu_olif_rd_sop_cnt;
-}DPP_ETM_OLIF_QMU_OLIF_RD_SOP_CNT_T;
-
-typedef struct dpp_etm_olif_qmu_olif_rd_eop_cnt_t
-{
-    ZXIC_UINT32 qmu_olif_rd_eop_cnt;
-}DPP_ETM_OLIF_QMU_OLIF_RD_EOP_CNT_T;
-
-typedef struct dpp_etm_olif_qmu_olif_rd_vld_cnt_t
-{
-    ZXIC_UINT32 qmu_olif_rd_vld_cnt;
-}DPP_ETM_OLIF_QMU_OLIF_RD_VLD_CNT_T;
-
-typedef struct dpp_etm_olif_qmu_olif_rd_blk_cnt_t
-{
-    ZXIC_UINT32 qmu_olif_rd_blk_cnt;
-}DPP_ETM_OLIF_QMU_OLIF_RD_BLK_CNT_T;
-
-typedef struct dpp_etm_olif_mmu_tm_data_sop_cnt_t
-{
-    ZXIC_UINT32 mmu_tm_data_sop_cnt;
-}DPP_ETM_OLIF_MMU_TM_DATA_SOP_CNT_T;
-
-typedef struct dpp_etm_olif_mmu_tm_data_eop_cnt_t
-{
-    ZXIC_UINT32 mmu_tm_data_eop_cnt;
-}DPP_ETM_OLIF_MMU_TM_DATA_EOP_CNT_T;
-
-typedef struct dpp_etm_olif_mmu_tm_data_vld_cnt_t
-{
-    ZXIC_UINT32 mmu_tm_data_vld_cnt;
-}DPP_ETM_OLIF_MMU_TM_DATA_VLD_CNT_T;
-
-typedef struct dpp_etm_olif_odma_tm_data_sop_cnt_t
-{
-    ZXIC_UINT32 odma_tm_data_sop_cnt;
-}DPP_ETM_OLIF_ODMA_TM_DATA_SOP_CNT_T;
-
-typedef struct dpp_etm_olif_odma_tm_data_eop_cnt_t
-{
-    ZXIC_UINT32 odma_tm_data_eop_cnt;
-}DPP_ETM_OLIF_ODMA_TM_DATA_EOP_CNT_T;
-
-typedef struct dpp_etm_olif_odma_tm_deq_vld_cnt_t
-{
-    ZXIC_UINT32 odma_tm_deq_vld_cnt;
-}DPP_ETM_OLIF_ODMA_TM_DEQ_VLD_CNT_T;
-
-typedef struct dpp_etm_olif_olif_qmu_release_vld_cnt_t
-{
-    ZXIC_UINT32 olif_qmu_release_vld_cnt;
-}DPP_ETM_OLIF_OLIF_QMU_RELEASE_VLD_CNT_T;
-
-typedef struct dpp_etm_olif_emem_dat_vld_cnt_t
-{
-    ZXIC_UINT32 emem_dat_vld_cnt;
-}DPP_ETM_OLIF_EMEM_DAT_VLD_CNT_T;
-
-typedef struct dpp_etm_olif_imem_dat_vld_cnt_t
-{
-    ZXIC_UINT32 imem_dat_vld_cnt;
-}DPP_ETM_OLIF_IMEM_DAT_VLD_CNT_T;
-
-typedef struct dpp_etm_olif_emem_dat_rd_cnt_t
-{
-    ZXIC_UINT32 emem_dat_rd_cnt;
-}DPP_ETM_OLIF_EMEM_DAT_RD_CNT_T;
-
-typedef struct dpp_etm_olif_imem_dat_rd_cnt_t
-{
-    ZXIC_UINT32 imem_dat_rd_cnt;
-}DPP_ETM_OLIF_IMEM_DAT_RD_CNT_T;
-
-typedef struct dpp_etm_olif_qmu_olif_rd_sop_emem_cnt_t
-{
-    ZXIC_UINT32 qmu_olif_rd_sop_emem_cnt;
-}DPP_ETM_OLIF_QMU_OLIF_RD_SOP_EMEM_CNT_T;
-
-typedef struct dpp_etm_olif_qmu_olif_rd_vld_emem_cnt_t
-{
-    ZXIC_UINT32 qmu_olif_rd_vld_emem_cnt;
-}DPP_ETM_OLIF_QMU_OLIF_RD_VLD_EMEM_CNT_T;
-
-typedef struct dpp_etm_olif_cpu_last_wr_addr_t
-{
-    ZXIC_UINT32 cpu_last_wr_addr;
-}DPP_ETM_OLIF_CPU_LAST_WR_ADDR_T;
-
-typedef struct dpp_etm_olif_cpu_last_wr_data_t
-{
-    ZXIC_UINT32 cpu_last_wr_data;
-}DPP_ETM_OLIF_CPU_LAST_WR_DATA_T;
-
-typedef struct dpp_etm_olif_cpu_last_rd_addr_t
-{
-    ZXIC_UINT32 cpu_last_rd_addr;
-}DPP_ETM_OLIF_CPU_LAST_RD_ADDR_T;
-
-typedef struct dpp_etm_olif_qmu_olif_last_port_t
-{
-    ZXIC_UINT32 qmu_olif_last_port;
-}DPP_ETM_OLIF_QMU_OLIF_LAST_PORT_T;
-
-typedef struct dpp_etm_olif_qmu_olif_last_addr_t
-{
-    ZXIC_UINT32 qmu_olif_last_addr;
-}DPP_ETM_OLIF_QMU_OLIF_LAST_ADDR_T;
-
-typedef struct dpp_etm_olif_qmu_olif_last_bank_t
-{
-    ZXIC_UINT32 qmu_olif_last_bank;
-}DPP_ETM_OLIF_QMU_OLIF_LAST_BANK_T;
-
-typedef struct dpp_etm_olif_tm_lif_byte_stat_t
-{
-    ZXIC_UINT32 tm_lif_byte_stat;
-}DPP_ETM_OLIF_TM_LIF_BYTE_STAT_T;
-
-typedef struct dpp_etm_olif_tm_lif_err_stat_t
-{
-    ZXIC_UINT32 tm_lif_err_stat;
-}DPP_ETM_OLIF_TM_LIF_ERR_STAT_T;
-
-typedef struct dpp_etm_cgavd_port_share_cnt_t
-{
-    ZXIC_UINT32 port_share_cnt;
-}DPP_ETM_CGAVD_PORT_SHARE_CNT_T;
-
-typedef struct dpp_etm_cgavd_total_imem_cnt_t
-{
-    ZXIC_UINT32 total_imem_cnt;
-}DPP_ETM_CGAVD_TOTAL_IMEM_CNT_T;
-
-typedef struct dpp_etm_cgavd_pp_q_len_t
-{
-    ZXIC_UINT32 pp_q_len;
-}DPP_ETM_CGAVD_PP_Q_LEN_T;
-
-typedef struct dpp_etm_cgavd_sys_q_len_t
-{
-    ZXIC_UINT32 sys_q_len;
-}DPP_ETM_CGAVD_SYS_Q_LEN_T;
-
-typedef struct dpp_etm_cgavd_cgavd_cfg_error_warning_t
-{
-    ZXIC_UINT32 error_correction_11;
-    ZXIC_UINT32 error_correction_10;
-    ZXIC_UINT32 error_correction_9;
-    ZXIC_UINT32 error_correction_8;
-    ZXIC_UINT32 error_correction_7;
-    ZXIC_UINT32 error_correction_6;
-    ZXIC_UINT32 error_correction5;
-    ZXIC_UINT32 error_correction_4;
-    ZXIC_UINT32 error_correction_3;
-    ZXIC_UINT32 error_correction_2;
-    ZXIC_UINT32 error_correction_1;
-    ZXIC_UINT32 error_correction_0;
-}DPP_ETM_CGAVD_CGAVD_CFG_ERROR_WARNING_T;
-
-typedef struct dpp_etm_cgavd_mult_qlen_th_en_t
-{
-    ZXIC_UINT32 mult_qlen_th;
-}DPP_ETM_CGAVD_MULT_QLEN_TH_EN_T;
-
-typedef struct dpp_etm_cgavd_mult_qlen_th_t
-{
-    ZXIC_UINT32 mult_qlen_th;
-}DPP_ETM_CGAVD_MULT_QLEN_TH_T;
-
-typedef struct dpp_etm_cgavd_cgavd_cfg_move_t
-{
-    ZXIC_UINT32 cfgmt_sys_move_en;
-    ZXIC_UINT32 cfgmt_port_move_en;
-    ZXIC_UINT32 cfgmt_flow_move_en;
-}DPP_ETM_CGAVD_CGAVD_CFG_MOVE_T;
-
-typedef struct dpp_etm_cgavd_cfgmt_total_th_t
-{
-    ZXIC_UINT32 cfgmt_total_th;
-}DPP_ETM_CGAVD_CFGMT_TOTAL_TH_T;
-
-typedef struct dpp_etm_cgavd_cfgmt_port_share_th_t
-{
-    ZXIC_UINT32 cfgmt_port_share_th;
-}DPP_ETM_CGAVD_CFGMT_PORT_SHARE_TH_T;
-
-typedef struct dpp_etm_cgavd_sa_unreach_state_t
-{
-    ZXIC_UINT32 sa_unreach_state;
-}DPP_ETM_CGAVD_SA_UNREACH_STATE_T;
-
-typedef struct dpp_etm_cgavd_mv_port_th_t
-{
-    ZXIC_UINT32 port_th;
-}DPP_ETM_CGAVD_MV_PORT_TH_T;
-
-typedef struct dpp_etm_cgavd_mv_drop_sp_th_t
-{
-    ZXIC_UINT32 mvdrop_sp_th;
-}DPP_ETM_CGAVD_MV_DROP_SP_TH_T;
-
-typedef struct dpp_etm_cgavd_cgavd_state_warning_t
-{
-    ZXIC_UINT32 deq_q_num_warning;
-    ZXIC_UINT32 deq_pkt_len_warning;
-    ZXIC_UINT32 enq_pkt_dp_warning;
-    ZXIC_UINT32 unenq_q_num_warning;
-    ZXIC_UINT32 enq_q_num_warning;
-    ZXIC_UINT32 enq_pkt_len_warning;
-}DPP_ETM_CGAVD_CGAVD_STATE_WARNING_T;
-
-typedef struct dpp_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_t
-{
-    ZXIC_UINT32 tmmu_cgavd_dma_fifo_cnt;
-}DPP_ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNT_T;
-
-typedef struct dpp_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_max_t
-{
-    ZXIC_UINT32 tmmu_cgavd_dma_fifo_cnt_max;
-}DPP_ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNT_MAX_T;
-
-typedef struct dpp_etm_cgavd_imem_total_cnt_t
-{
-    ZXIC_UINT32 imem_total_cnt;
-}DPP_ETM_CGAVD_IMEM_TOTAL_CNT_T;
-
-typedef struct dpp_etm_cgavd_imem_total_cnt_max_t
-{
-    ZXIC_UINT32 imem_total_cnt_max;
-}DPP_ETM_CGAVD_IMEM_TOTAL_CNT_MAX_T;
-
-typedef struct dpp_etm_cgavd_flow0_omem_cnt_t
-{
-    ZXIC_UINT32 flow0_omem_cnt;
-}DPP_ETM_CGAVD_FLOW0_OMEM_CNT_T;
-
-typedef struct dpp_etm_cgavd_flow1_omem_cnt_t
-{
-    ZXIC_UINT32 flow1_omem_cnt;
-}DPP_ETM_CGAVD_FLOW1_OMEM_CNT_T;
-
-typedef struct dpp_etm_cgavd_flow2_omem_cnt_t
-{
-    ZXIC_UINT32 flow2_omem_cnt;
-}DPP_ETM_CGAVD_FLOW2_OMEM_CNT_T;
-
-typedef struct dpp_etm_cgavd_flow3_omem_cnt_t
-{
-    ZXIC_UINT32 flow3_omem_cnt;
-}DPP_ETM_CGAVD_FLOW3_OMEM_CNT_T;
-
-typedef struct dpp_etm_cgavd_flow4_omem_cnt_t
-{
-    ZXIC_UINT32 flow4_omem_cnt;
-}DPP_ETM_CGAVD_FLOW4_OMEM_CNT_T;
-
-typedef struct dpp_etm_cgavd_appoint_flow_num_message_1_t
-{
-    ZXIC_UINT32 appoint_flow_num_en_1;
-    ZXIC_UINT32 appoint_flow_num_1;
-}DPP_ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_1_T;
-
-typedef struct dpp_etm_cgavd_appoint_flow_num_message_2_t
-{
-    ZXIC_UINT32 appoint_flow_num_en_2;
-    ZXIC_UINT32 appoint_flow_num_2;
-}DPP_ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_2_T;
-
-typedef struct dpp_etm_cgavd_odma_cgavd_pkt_num_1_t
-{
-    ZXIC_UINT32 odma_cgavd_pkt_num_1;
-}DPP_ETM_CGAVD_ODMA_CGAVD_PKT_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_odma_cgavd_byte_num_1_t
-{
-    ZXIC_UINT32 odma_cgavd_byte_num_1;
-}DPP_ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_enqueue_pkt_num_1_t
-{
-    ZXIC_UINT32 cgavd_enqueue_pkt_num_1;
-}DPP_ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_dequeue_pkt_num_1_t
-{
-    ZXIC_UINT32 cgavd_dequeue_pkt_num_1;
-}DPP_ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_imem_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_pkt_imem_num_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_omem_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_pkt_omem_num_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_byte_imem_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_byte_imem_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_byte_omem_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_byte_omem_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_drop_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_pkt_drop_num_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_byte_drop_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_byte_drop_num_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_forbid_drop_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_forbid_drop_num_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_flow_td_drop_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_flow_td_drop_num_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_flow_wred_drop_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_flow_wred_drop_num_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_flow_wred_dp_drop_num1;
-}DPP_ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_pp_td_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_pp_td_num_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_pp_wred_drop_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_pp_wred_drop_num_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_pp_wred_dp_drop_num1;
-}DPP_ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_sys_td_drop_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_sys_td_drop_num_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_sys_gred_drop_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_sys_gred_drop_num_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num1_t
-{
-    ZXIC_UINT32 cgavd_qmu_sys_gred_dp_drop_num1;
-}DPP_ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_sa_drop_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_sa_drop_num_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_move_drop_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_move_drop_num_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_tm_mult_drop_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_tm_mult_drop_num_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_tm_error_drop_num_1_t
-{
-    ZXIC_UINT32 cgavd_qmu_tm_error_drop_num_1;
-}DPP_ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_1_T;
-
-typedef struct dpp_etm_cgavd_odma_cgavd_pkt_num_2_t
-{
-    ZXIC_UINT32 odma_cgavd_pkt_num_2;
-}DPP_ETM_CGAVD_ODMA_CGAVD_PKT_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_odma_cgavd_byte_num_2_t
-{
-    ZXIC_UINT32 odma_cgavd_byte_num_2;
-}DPP_ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_enqueue_pkt_num_2_t
-{
-    ZXIC_UINT32 cgavd_enqueue_pkt_num_2;
-}DPP_ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_dequeue_pkt_num_2_t
-{
-    ZXIC_UINT32 cgavd_dequeue_pkt_num_2;
-}DPP_ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_imem_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_pkt_imem_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_omem_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_pkt_omem_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_byte_imem_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_byte_imem_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_byte_omem_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_byte_omem_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_drop_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_pkt_drop_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_byte_drop_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_byte_drop_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_forbid_drop_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_forbid_drop_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_flow_td_drop_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_flow_td_drop_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_flow_wred_drop_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_flow_wred_drop_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_flow_wred_dp_drop_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_pp_td_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_pp_td_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_pp_wred_drop_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_pp_wred_drop_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_pp_wred_dp_drop_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_sys_td_drop_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_sys_td_drop_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_sys_gred_drop_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_sys_gred_drop_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_sys_gred_dp_drop_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_sa_drop_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_sa_drop_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_move_drop_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_move_drop_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_tm_mult_drop_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_tm_mult_drop_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_cgavd_qmu_tm_error_drop_num_2_t
-{
-    ZXIC_UINT32 cgavd_qmu_tm_error_drop_num_2;
-}DPP_ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_2_T;
-
-typedef struct dpp_etm_cgavd_move_flow_th_profile_t
-{
-    ZXIC_UINT32 move_drop_profile;
-}DPP_ETM_CGAVD_MOVE_FLOW_TH_PROFILE_T;
-
-typedef struct dpp_etm_cgavd_move_flow_th_t
-{
-    ZXIC_UINT32 move_drop_flow_th;
-}DPP_ETM_CGAVD_MOVE_FLOW_TH_T;
-
-typedef struct dpp_etm_tmmu_emem_pd_fifo_aful_th_t
-{
-    ZXIC_UINT32 emem_pd_fifo_aful_th;
-}DPP_ETM_TMMU_EMEM_PD_FIFO_AFUL_TH_T;
-
-typedef struct dpp_etm_tmmu_dma_data_fifo_aful_th_t
-{
-    ZXIC_UINT32 dma_data_fifo_aful_th;
-}DPP_ETM_TMMU_DMA_DATA_FIFO_AFUL_TH_T;
-
-typedef struct dpp_etm_tmmu_tmmu_states_0_t
-{
-    ZXIC_UINT32 tm_odma_pkt_rdy;
-    ZXIC_UINT32 dma_data_fifo_empty;
-    ZXIC_UINT32 imem_enq_rd_fifo_empty;
-    ZXIC_UINT32 imem_enq_drop_fifo_empty;
-    ZXIC_UINT32 imem_deq_rd_fifo_empty;
-    ZXIC_UINT32 imem_deq_drop_fifo_empty;
-    ZXIC_UINT32 wr_cmd_fifo_empty;
-    ZXIC_UINT32 cached_pd_fifo_empty;
-    ZXIC_UINT32 emem_pd_fifo_empty;
-    ZXIC_UINT32 pd_order_fifo_empty;
-    ZXIC_UINT32 odma_tm_data_rdy;
-    ZXIC_UINT32 odma_tm_discard_rdy;
-    ZXIC_UINT32 olif_tmmu_rdy;
-    ZXIC_UINT32 mmu_tm_cmd_wr_rdy;
-    ZXIC_UINT32 mmu_tm_data_wr_rdy;
-    ZXIC_UINT32 mmu_tm_rd_rdy;
-    ZXIC_UINT32 mmu_tm_sop_rd_rdy;
-    ZXIC_UINT32 qmu_tmmu_sop_data_rdy;
-    ZXIC_UINT32 tmmu_cmdsw_imem_release_rdy;
-    ZXIC_UINT32 imem_age_release_rdy;
-    ZXIC_UINT32 tmmu_qmu_wr_rdy;
-    ZXIC_UINT32 tmmu_qmu_rdy_7;
-    ZXIC_UINT32 tmmu_qmu_rdy_6;
-    ZXIC_UINT32 tmmu_qmu_rdy_5;
-    ZXIC_UINT32 tmmu_qmu_rdy_4;
-    ZXIC_UINT32 tmmu_qmu_rdy_3;
-    ZXIC_UINT32 tmmu_qmu_rdy_2;
-    ZXIC_UINT32 tmmu_qmu_rdy_1;
-    ZXIC_UINT32 tmmu_qmu_rdy_0;
-    ZXIC_UINT32 tmmu_qmu_rd_rdy;
-    ZXIC_UINT32 tmmu_qmu_sop_rd_rdy;
-}DPP_ETM_TMMU_TMMU_STATES_0_T;
-
-typedef struct dpp_etm_tmmu_qmu_tmmu_wr_sop_cnt_t
-{
-    ZXIC_UINT32 qmu_tmmu_wr_sop_cnt;
-}DPP_ETM_TMMU_QMU_TMMU_WR_SOP_CNT_T;
-
-typedef struct dpp_etm_tmmu_qmu_tmmu_wr_eop_cnt_t
-{
-    ZXIC_UINT32 qmu_tmmu_wr_eop_cnt;
-}DPP_ETM_TMMU_QMU_TMMU_WR_EOP_CNT_T;
-
-typedef struct dpp_etm_tmmu_qmu_tmmu_wr_drop_cnt_t
-{
-    ZXIC_UINT32 qmu_tmmu_wr_drop_cnt;
-}DPP_ETM_TMMU_QMU_TMMU_WR_DROP_CNT_T;
-
-typedef struct dpp_etm_tmmu_qmu_tmmu_wr_emem_cnt_t
-{
-    ZXIC_UINT32 qmu_tmmu_wr_emem_cnt;
-}DPP_ETM_TMMU_QMU_TMMU_WR_EMEM_CNT_T;
-
-typedef struct dpp_etm_tmmu_qmu_tmmu_wr_imem_cnt_t
-{
-    ZXIC_UINT32 qmu_tmmu_wr_imem_cnt;
-}DPP_ETM_TMMU_QMU_TMMU_WR_IMEM_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_mmu_wr_sop_cnt_t
-{
-    ZXIC_UINT32 tmmu_mmu_wr_sop_cnt;
-}DPP_ETM_TMMU_TMMU_MMU_WR_SOP_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_mmu_wr_eop_cnt_t
-{
-    ZXIC_UINT32 tmmu_mmu_wr_eop_cnt;
-}DPP_ETM_TMMU_TMMU_MMU_WR_EOP_CNT_T;
-
-typedef struct dpp_etm_tmmu_qmu_tmmu_rd_sop_cnt_t
-{
-    ZXIC_UINT32 qmu_tmmu_rd_sop_cnt;
-}DPP_ETM_TMMU_QMU_TMMU_RD_SOP_CNT_T;
-
-typedef struct dpp_etm_tmmu_qmu_tmmu_rd_eop_cnt_t
-{
-    ZXIC_UINT32 qmu_tmmu_rd_eop_cnt;
-}DPP_ETM_TMMU_QMU_TMMU_RD_EOP_CNT_T;
-
-typedef struct dpp_etm_tmmu_qmu_tmmu_rd_drop_cnt_t
-{
-    ZXIC_UINT32 qmu_tmmu_rd_drop_cnt;
-}DPP_ETM_TMMU_QMU_TMMU_RD_DROP_CNT_T;
-
-typedef struct dpp_etm_tmmu_qmu_tmmu_rd_emem_cnt_t
-{
-    ZXIC_UINT32 qmu_tmmu_rd_emem_cnt;
-}DPP_ETM_TMMU_QMU_TMMU_RD_EMEM_CNT_T;
-
-typedef struct dpp_etm_tmmu_qmu_tmmu_rd_imem_cnt_t
-{
-    ZXIC_UINT32 qmu_tmmu_rd_imem_cnt;
-}DPP_ETM_TMMU_QMU_TMMU_RD_IMEM_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_mmu_rd_sop_cnt_t
-{
-    ZXIC_UINT32 tmmu_mmu_rd_sop_cnt;
-}DPP_ETM_TMMU_TMMU_MMU_RD_SOP_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_mmu_rd_eop_cnt_t
-{
-    ZXIC_UINT32 tmmu_mmu_rd_eop_cnt;
-}DPP_ETM_TMMU_TMMU_MMU_RD_EOP_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_odma_in_sop_cnt_t
-{
-    ZXIC_UINT32 tmmu_odma_in_sop_cnt;
-}DPP_ETM_TMMU_TMMU_ODMA_IN_SOP_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_odma_in_eop_cnt_t
-{
-    ZXIC_UINT32 tmmu_odma_in_eop_cnt;
-}DPP_ETM_TMMU_TMMU_ODMA_IN_EOP_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_odma_vld_cnt_t
-{
-    ZXIC_UINT32 tmmu_odma_vld_cnt;
-}DPP_ETM_TMMU_TMMU_ODMA_VLD_CNT_T;
-
-typedef struct dpp_etm_tmmu_qmu_pd_in_cnt_t
-{
-    ZXIC_UINT32 qmu_pd_in_cnt;
-}DPP_ETM_TMMU_QMU_PD_IN_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_pd_hit_cnt_t
-{
-    ZXIC_UINT32 tmmu_pd_hit_cnt;
-}DPP_ETM_TMMU_TMMU_PD_HIT_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_pd_out_cnt_t
-{
-    ZXIC_UINT32 tmmu_pd_out_cnt;
-}DPP_ETM_TMMU_TMMU_PD_OUT_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_wr_cmd_fifo_wr_cnt_t
-{
-    ZXIC_UINT32 tmmu_wr_cmd_fifo_wr_cnt;
-}DPP_ETM_TMMU_TMMU_WR_CMD_FIFO_WR_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_imem_age_cnt_t
-{
-    ZXIC_UINT32 tmmu_imem_age_cnt;
-}DPP_ETM_TMMU_TMMU_IMEM_AGE_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_cmdsch_rd_cnt_t
-{
-    ZXIC_UINT32 tmmu_cmdsch_rd_cnt;
-}DPP_ETM_TMMU_TMMU_CMDSCH_RD_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_cmdsch_drop_cnt_t
-{
-    ZXIC_UINT32 tmmu_cmdsch_drop_cnt;
-}DPP_ETM_TMMU_TMMU_CMDSCH_DROP_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_cmdsw_drop_cnt_t
-{
-    ZXIC_UINT32 tmmu_cmdsw_drop_cnt;
-}DPP_ETM_TMMU_TMMU_CMDSW_DROP_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_odma_enq_rd_cnt_t
-{
-    ZXIC_UINT32 tmmu_odma_enq_rd_cnt;
-}DPP_ETM_TMMU_TMMU_ODMA_ENQ_RD_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_odma_enq_drop_cnt_t
-{
-    ZXIC_UINT32 tmmu_odma_enq_drop_cnt;
-}DPP_ETM_TMMU_TMMU_ODMA_ENQ_DROP_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_odma_imem_age_cnt_t
-{
-    ZXIC_UINT32 tmmu_odma_imem_age_cnt;
-}DPP_ETM_TMMU_TMMU_ODMA_IMEM_AGE_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_odma_deq_rd_cnt_t
-{
-    ZXIC_UINT32 tmmu_odma_deq_rd_cnt;
-}DPP_ETM_TMMU_TMMU_ODMA_DEQ_RD_CNT_T;
-
-typedef struct dpp_etm_tmmu_tmmu_odma_deq_drop_cnt_t
-{
-    ZXIC_UINT32 tmmu_odma_deq_drop_cnt;
-}DPP_ETM_TMMU_TMMU_ODMA_DEQ_DROP_CNT_T;
-
-typedef struct dpp_etm_tmmu_olif_tmmu_xoff_cnt_t
-{
-    ZXIC_UINT32 olif_tmmu_xoff_cnt;
-}DPP_ETM_TMMU_OLIF_TMMU_XOFF_CNT_T;
-
-typedef struct dpp_etm_tmmu_odma_tm_data_xoff_cnt_t
-{
-    ZXIC_UINT32 odma_tm_data_xoff_cnt;
-}DPP_ETM_TMMU_ODMA_TM_DATA_XOFF_CNT_T;
-
-typedef struct dpp_etm_tmmu_tm_odma_pkt_xoff_cnt_t
-{
-    ZXIC_UINT32 tm_odma_pkt_xoff_cnt;
-}DPP_ETM_TMMU_TM_ODMA_PKT_XOFF_CNT_T;
-
-typedef struct dpp_etm_tmmu_tm_state_3_t
-{
-    ZXIC_UINT32 tmmu_qmu_rdy_9;
-    ZXIC_UINT32 tmmu_qmu_rdy_8;
-}DPP_ETM_TMMU_TM_STATE_3_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_pd_cache_cmd_t
-{
-    ZXIC_UINT32 cfgmt_pd_cache_addr;
-}DPP_ETM_TMMU_CFGMT_PD_CACHE_CMD_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_pd_cache_rd_done_t
-{
-    ZXIC_UINT32 cfgmt_pd_cache_rd_done;
-}DPP_ETM_TMMU_CFGMT_PD_CACHE_RD_DONE_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_pd_cache_rd_data_0_t
-{
-    ZXIC_UINT32 cfgmt_pd_cache_rd_data_0;
-}DPP_ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_0_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_pd_cache_rd_data_1_t
-{
-    ZXIC_UINT32 cfgmt_pd_cache_rd_data_1;
-}DPP_ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_1_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_pd_cache_rd_data_2_t
-{
-    ZXIC_UINT32 cfgmt_pd_cache_rd_data_2;
-}DPP_ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_2_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_pd_cache_rd_data_3_t
-{
-    ZXIC_UINT32 cfgmt_pd_cache_rd_data_3;
-}DPP_ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_3_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_tmmu_to_odma_para_t
-{
-    ZXIC_UINT32 cfgmt_tmmu_to_odma_para;
-}DPP_ETM_TMMU_CFGMT_TMMU_TO_ODMA_PARA_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_dma_data_fifo_cnt_t
-{
-    ZXIC_UINT32 cfgmt_dma_data_fifo_cnt;
-}DPP_ETM_TMMU_CFGMT_DMA_DATA_FIFO_CNT_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit0_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_tag_bit0_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT0_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit1_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_tag_bit1_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT1_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit2_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_tag_bit2_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT2_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit3_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_tag_bit3_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT3_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit4_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_tag_bit4_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT4_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit5_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_tag_bit5_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT5_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit0_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_index_bit0_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT0_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit1_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_index_bit1_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT1_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit2_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_index_bit2_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT2_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit3_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_index_bit3_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT3_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit4_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_index_bit4_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT4_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit5_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_index_bit5_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT5_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit6_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_index_bit6_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT6_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit7_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_index_bit7_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT7_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit8_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_index_bit8_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT8_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit9_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_index_bit9_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT9_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit10_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_index_bit10_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT10_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit11_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_index_bit11_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT11_OFFSET_T;
-
-typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit12_offset_t
-{
-    ZXIC_UINT32 cfgmt_cache_index_bit12_offset;
-}DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT12_OFFSET_T;
-
-typedef struct dpp_etm_shap_bktfull_fifo_full_flagregister_t
-{
-    ZXIC_UINT32 bktfull_fifo_full_flag_core;
-}DPP_ETM_SHAP_BKTFULL_FIFO_FULL_FLAGREGISTER_T;
-
-typedef struct dpp_etm_shap_fifo_full_regregister_t
-{
-    ZXIC_UINT32 fifo_full_reg;
-}DPP_ETM_SHAP_FIFO_FULL_REGREGISTER_T;
-
-typedef struct dpp_etm_shap_fifo_empty_regregister_t
-{
-    ZXIC_UINT32 fifo_empty_reg;
-}DPP_ETM_SHAP_FIFO_EMPTY_REGREGISTER_T;
-
-typedef struct dpp_etm_shap_fifo_almost_full_regregister_t
-{
-    ZXIC_UINT32 fifo_almost_full_reg;
-}DPP_ETM_SHAP_FIFO_ALMOST_FULL_REGREGISTER_T;
-
-typedef struct dpp_etm_shap_fifo_almost_empty_regregister_t
-{
-    ZXIC_UINT32 fifo_almost_empty_reg;
-}DPP_ETM_SHAP_FIFO_ALMOST_EMPTY_REGREGISTER_T;
-
-typedef struct dpp_etm_crdt_credit_space_select_t
-{
-    ZXIC_UINT32 credit_space_select;
-}DPP_ETM_CRDT_CREDIT_SPACE_SELECT_T;
-
-typedef struct dpp_etm_crdt_stat_space_max_t
-{
-    ZXIC_UINT32 stat_space_max;
-}DPP_ETM_CRDT_STAT_SPACE_MAX_T;
-
-typedef struct dpp_etm_crdt_stat_space_min_t
-{
-    ZXIC_UINT32 stat_space_min;
-}DPP_ETM_CRDT_STAT_SPACE_MIN_T;
-
-typedef struct dpp_etm_crdt_stat_space_credit_t
-{
-    ZXIC_UINT32 stat_space_credit;
-}DPP_ETM_CRDT_STAT_SPACE_CREDIT_T;
-
-typedef struct dpp_etm_crdt_stat_que_step8_credit_t
-{
-    ZXIC_UINT32 stat_que_step8_credit;
-}DPP_ETM_CRDT_STAT_QUE_STEP8_CREDIT_T;
-
-typedef struct dpp_etm_crdt_special_que_t
-{
-    ZXIC_UINT32 special_que_id;
-}DPP_ETM_CRDT_SPECIAL_QUE_T;
-
-typedef struct dpp_etm_crdt_special_que_credit_t
-{
-    ZXIC_UINT32 special_que_credit;
-}DPP_ETM_CRDT_SPECIAL_QUE_CREDIT_T;
-
-typedef struct dpp_etm_crdt_lif_congest_credit_cnt_t
-{
-    ZXIC_UINT32 lif_congest_credit_cnt;
-}DPP_ETM_CRDT_LIF_CONGEST_CREDIT_CNT_T;
-
-typedef struct dpp_etm_crdt_lif_port_congest_credit_cnt_t
-{
-    ZXIC_UINT32 lif_port_congest_credit_cnt;
-}DPP_ETM_CRDT_LIF_PORT_CONGEST_CREDIT_CNT_T;
-
-typedef struct dpp_etm_crdt_crdt_congest_credit_cnt_t
-{
-    ZXIC_UINT32 crdt_congest_credit_cnt;
-}DPP_ETM_CRDT_CRDT_CONGEST_CREDIT_CNT_T;
-
-typedef struct dpp_etm_crdt_crdt_port_congest_credit_cnt_t
-{
-    ZXIC_UINT32 crdt_port_congest_credit_cnt;
-}DPP_ETM_CRDT_CRDT_PORT_CONGEST_CREDIT_CNT_T;
-
-typedef struct dpp_etm_crdt_congest_port_id_t
-{
-    ZXIC_UINT32 congest_port_id;
-}DPP_ETM_CRDT_CONGEST_PORT_ID_T;
-
-typedef struct dpp_etm_crdt_dev_link_control_t
-{
-    ZXIC_UINT32 dev_link_control;
-}DPP_ETM_CRDT_DEV_LINK_CONTROL_T;
-
-typedef struct dpp_etm_crdt_crdt_sa_port_rdy_t
-{
-    ZXIC_UINT32 crdt_sa_port_rdy;
-}DPP_ETM_CRDT_CRDT_SA_PORT_RDY_T;
-
-typedef struct dpp_etm_crdt_crdt_congest_mode_select_t
-{
-    ZXIC_UINT32 crdt_congest_mode_selectr;
-}DPP_ETM_CRDT_CRDT_CONGEST_MODE_SELECT_T;
-
-typedef struct dpp_etm_crdt_fifo_out_all_crs_normal_cnt_t
-{
-    ZXIC_UINT32 fifo_out_all_crs_normal_cnt;
-}DPP_ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNT_T;
-
-typedef struct dpp_etm_crdt_fifo_out_all_crs_off_cnt_t
-{
-    ZXIC_UINT32 fifo_out_all_crs_off_cnt;
-}DPP_ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNT_T;
-
-typedef struct dpp_etm_crdt_fifo_out_que_crs_normal_cnt_t
-{
-    ZXIC_UINT32 fifo_out_que_crs_normal_cnt;
-}DPP_ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNT_T;
-
-typedef struct dpp_etm_crdt_fifo_out_que_crs_off_cnt_t
-{
-    ZXIC_UINT32 fifo_out_que_crs_off_cnt;
-}DPP_ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNT_T;
-
-typedef struct dpp_etm_crdt_mode_add_60g_t
-{
-    ZXIC_UINT32 mode_add_60g;
-}DPP_ETM_CRDT_MODE_ADD_60G_T;
-
-typedef struct dpp_etm_crdt_pp_token_add_t
-{
-    ZXIC_UINT32 pp_token_add_cir;
-}DPP_ETM_CRDT_PP_TOKEN_ADD_T;
-
-typedef struct dpp_etm_crdt_pp_cir_token_total_dist_cnt_t
-{
-    ZXIC_UINT32 pp_cir_token_total_dist_counter;
-}DPP_ETM_CRDT_PP_CIR_TOKEN_TOTAL_DIST_CNT_T;
-
-typedef struct dpp_etm_crdt_pp_cir_token_total_dec_cnt_t
-{
-    ZXIC_UINT32 pp_cir_token_total_dec_counter;
-}DPP_ETM_CRDT_PP_CIR_TOKEN_TOTAL_DEC_CNT_T;
-
-typedef struct dpp_etm_crdt_dev_credit_cnt_t
-{
-    ZXIC_UINT32 dev_credit_cnt;
-}DPP_ETM_CRDT_DEV_CREDIT_CNT_T;
-
-typedef struct dpp_etm_crdt_no_credit_cnt1_t
-{
-    ZXIC_UINT32 no_credit_cnt1;
-}DPP_ETM_CRDT_NO_CREDIT_CNT1_T;
-
-typedef struct dpp_etm_crdt_no_credit_cnt2_t
-{
-    ZXIC_UINT32 no_credit_cnt2;
-}DPP_ETM_CRDT_NO_CREDIT_CNT2_T;
-
-typedef struct dpp_etm_crdt_asm_interval_0_cfg_t
-{
-    ZXIC_UINT32 asm_interval_0_cfg;
-}DPP_ETM_CRDT_ASM_INTERVAL_0_CFG_T;
-
-typedef struct dpp_etm_crdt_asm_interval_1_cfg_t
-{
-    ZXIC_UINT32 asm_interval_1_cfg;
-}DPP_ETM_CRDT_ASM_INTERVAL_1_CFG_T;
-
-typedef struct dpp_etm_crdt_asm_interval_2_cfg_t
-{
-    ZXIC_UINT32 asm_interval_2_cfg;
-}DPP_ETM_CRDT_ASM_INTERVAL_2_CFG_T;
-
-typedef struct dpp_etm_crdt_asm_interval_3_cfg_t
-{
-    ZXIC_UINT32 asm_interval_3_cfg;
-}DPP_ETM_CRDT_ASM_INTERVAL_3_CFG_T;
-
-typedef struct dpp_etm_crdt_asm_interval_4_cfg_t
-{
-    ZXIC_UINT32 asm_interval_4_cfg;
-}DPP_ETM_CRDT_ASM_INTERVAL_4_CFG_T;
-
-typedef struct dpp_etm_crdt_asm_interval_5cfg_t
-{
-    ZXIC_UINT32 asm_interval_5_cfg;
-}DPP_ETM_CRDT_ASM_INTERVAL_5CFG_T;
-
-typedef struct dpp_etm_crdt_asm_interval_6_cfg_t
-{
-    ZXIC_UINT32 asm_interval_6_cfg;
-}DPP_ETM_CRDT_ASM_INTERVAL_6_CFG_T;
-
-typedef struct dpp_etm_crdt_asm_interval_7_cfg_t
-{
-    ZXIC_UINT32 asm_interval_7_cfg;
-}DPP_ETM_CRDT_ASM_INTERVAL_7_CFG_T;
-
-typedef struct dpp_etm_crdt_crdt_total_congest_mode_cfg_t
-{
-    ZXIC_UINT32 crdt_total_congest_mode_cfg;
-}DPP_ETM_CRDT_CRDT_TOTAL_CONGEST_MODE_CFG_T;
-
-typedef struct dpp_etm_crdt_rci_fifo_ini_deep_cfg_t
-{
-    ZXIC_UINT32 rci_fifo_ini_deep_cfg;
-}DPP_ETM_CRDT_RCI_FIFO_INI_DEEP_CFG_T;
-
-typedef struct dpp_etm_crdt_crdt_ecc_t
-{
-    ZXIC_UINT32 seinfo_wfq_single_ecc_err;
-    ZXIC_UINT32 seinfo_wfq_double_ecc_err;
-    ZXIC_UINT32 seinfo_fq_single_ecc_err;
-    ZXIC_UINT32 seinfo_fq_double_ecc_err;
-    ZXIC_UINT32 ecc_bypass;
-}DPP_ETM_CRDT_CRDT_ECC_T;
-
-typedef struct dpp_etm_crdt_ucn_asm_rdy_shield_en_t
-{
-    ZXIC_UINT32 ucn_rdy_shield_en;
-    ZXIC_UINT32 asm_rdy_shield_en;
-}DPP_ETM_CRDT_UCN_ASM_RDY_SHIELD_EN_T;
-
-typedef struct dpp_etm_crdt_ucn_asm_rdy_t
-{
-    ZXIC_UINT32 ucn_rdy;
-    ZXIC_UINT32 asm_rdy;
-}DPP_ETM_CRDT_UCN_ASM_RDY_T;
-
-typedef struct dpp_etm_crdt_rci_grade_t
-{
-    ZXIC_UINT32 rci_grade;
-}DPP_ETM_CRDT_RCI_GRADE_T;
-
-typedef struct dpp_etm_crdt_crdt_rci_value_r_t
-{
-    ZXIC_UINT32 crdt_rci_value_r;
-}DPP_ETM_CRDT_CRDT_RCI_VALUE_R_T;
-
-typedef struct dpp_etm_crdt_crdt_interval_now_t
-{
-    ZXIC_UINT32 crdt_interval_now;
-}DPP_ETM_CRDT_CRDT_INTERVAL_NOW_T;
-
-typedef struct dpp_etm_crdt_crs_sheild_flow_id_cfg_t
-{
-    ZXIC_UINT32 crs_sheild_flow_id_cfg;
-}DPP_ETM_CRDT_CRS_SHEILD_FLOW_ID_CFG_T;
-
-typedef struct dpp_etm_crdt_crs_sheild_en_cfg_t
-{
-    ZXIC_UINT32 crs_sheild_en_cfg;
-}DPP_ETM_CRDT_CRS_SHEILD_EN_CFG_T;
-
-typedef struct dpp_etm_crdt_crs_sheild_value_cfg_t
-{
-    ZXIC_UINT32 crs_sheild_value_cfg;
-}DPP_ETM_CRDT_CRS_SHEILD_VALUE_CFG_T;
-
-typedef struct dpp_etm_crdt_test_token_calc_ctrl_t
-{
-    ZXIC_UINT32 test_token_calc_state;
-    ZXIC_UINT32 test_token_calc_trigger;
-}DPP_ETM_CRDT_TEST_TOKEN_CALC_CTRL_T;
-
-typedef struct dpp_etm_crdt_test_token_sample_cycle_num_t
-{
-    ZXIC_UINT32 sample_cycle_num;
-}DPP_ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUM_T;
-
-typedef struct dpp_etm_crdt_q_state_0_7_t
-{
-    ZXIC_UINT32 q_token_state_7;
-    ZXIC_UINT32 q_token_state_6;
-    ZXIC_UINT32 q_token_state_5;
-    ZXIC_UINT32 q_token_state_4;
-    ZXIC_UINT32 q_token_state_3;
-    ZXIC_UINT32 q_token_state_2;
-    ZXIC_UINT32 q_token_state_1;
-    ZXIC_UINT32 q_token_state_0;
-}DPP_ETM_CRDT_Q_STATE_0_7_T;
-
-typedef struct dpp_etm_crdt_q_state_8_15_t
-{
-    ZXIC_UINT32 q_token_state_15;
-    ZXIC_UINT32 q_token_state_14;
-    ZXIC_UINT32 q_token_state_13;
-    ZXIC_UINT32 q_token_state_12;
-    ZXIC_UINT32 q_token_state_11;
-    ZXIC_UINT32 q_token_state_10;
-    ZXIC_UINT32 q_token_state_9;
-    ZXIC_UINT32 q_token_state_8;
-}DPP_ETM_CRDT_Q_STATE_8_15_T;
-
-typedef struct dpp_etm_qmu_csw_csch_rd_cmd_cnt_t
-{
-    ZXIC_UINT32 csw_csch_rd_cmd_cnt;
-}DPP_ETM_QMU_CSW_CSCH_RD_CMD_CNT_T;
-
-typedef struct dpp_etm_qmu_csw_csch_rd_sop_cnt_t
-{
-    ZXIC_UINT32 csw_csch_rd_sop_cnt;
-}DPP_ETM_QMU_CSW_CSCH_RD_SOP_CNT_T;
-
-typedef struct dpp_etm_qmu_csw_csch_rd_eop_cnt_t
-{
-    ZXIC_UINT32 csw_csch_rd_eop_cnt;
-}DPP_ETM_QMU_CSW_CSCH_RD_EOP_CNT_T;
-
-typedef struct dpp_etm_qmu_csw_csch_rd_drop_cnt_t
-{
-    ZXIC_UINT32 csw_csch_rd_drop_cnt;
-}DPP_ETM_QMU_CSW_CSCH_RD_DROP_CNT_T;
-
-typedef struct dpp_etm_qmu_csch_mmu_rd_cmd_cnt_t
-{
-    ZXIC_UINT32 csch_mmu_rd_cmd_cnt;
-}DPP_ETM_QMU_CSCH_MMU_RD_CMD_CNT_T;
-
-typedef struct dpp_etm_qmu_csch_mmu_rd_sop_cnt_t
-{
-    ZXIC_UINT32 csch_mmu_rd_sop_cnt;
-}DPP_ETM_QMU_CSCH_MMU_RD_SOP_CNT_T;
-
-typedef struct dpp_etm_qmu_csch_mmu_rd_eop_cnt_t
-{
-    ZXIC_UINT32 csch_mmu_rd_eop_cnt;
-}DPP_ETM_QMU_CSCH_MMU_RD_EOP_CNT_T;
-
-typedef struct dpp_etm_qmu_csch_mmu_rd_drop_cnt_t
-{
-    ZXIC_UINT32 csch_mmu_rd_drop_cnt;
-}DPP_ETM_QMU_CSCH_MMU_RD_DROP_CNT_T;
-
-typedef struct dpp_etm_qmu_qcfg_qsch_crs_filter_t
-{
-    ZXIC_UINT32 qcfg_qsch_crs_filter;
-}DPP_ETM_QMU_QCFG_QSCH_CRS_FILTER_T;
-
-typedef struct dpp_etm_qmu_qcfg_qsch_crs_force_en_t
-{
-    ZXIC_UINT32 qcfg_qsch_crs_force_en;
-}DPP_ETM_QMU_QCFG_QSCH_CRS_FORCE_EN_T;
-
-typedef struct dpp_etm_qmu_qcfg_qsch_crs_force_qnum_t
-{
-    ZXIC_UINT32 qcfg_qsch_crs_force_qnum;
-}DPP_ETM_QMU_QCFG_QSCH_CRS_FORCE_QNUM_T;
-
-typedef struct dpp_etm_qmu_qcfg_qsch_crs_force_crs_t
-{
-    ZXIC_UINT32 qcfg_qsch_crs_force_crs;
-}DPP_ETM_QMU_QCFG_QSCH_CRS_FORCE_CRS_T;
-
-typedef struct dpp_etm_qmu_cfgmt_oshp_sgmii_shap_mode_t
-{
-    ZXIC_UINT32 cfgmt_oshp_sgmii_shap_mode;
-}DPP_ETM_QMU_CFGMT_OSHP_SGMII_SHAP_MODE_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_sashap_en_t
-{
-    ZXIC_UINT32 cfgmt_qmu_sashap_en;
-}DPP_ETM_QMU_CFGMT_QMU_SASHAP_EN_T;
-
-typedef struct dpp_etm_qmu_cfgmt_sashap_token_max_t
-{
-    ZXIC_UINT32 cfgmt_sashap_token_max;
-}DPP_ETM_QMU_CFGMT_SASHAP_TOKEN_MAX_T;
-
-typedef struct dpp_etm_qmu_cfgmt_sashap_token_min_t
-{
-    ZXIC_UINT32 cfgmt_sashap_token_min;
-}DPP_ETM_QMU_CFGMT_SASHAP_TOKEN_MIN_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_q3lbaddrate_t
-{
-    ZXIC_UINT32 cfg_qsch_q3lbaddrate;
-}DPP_ETM_QMU_CFG_QSCH_Q3LBADDRATE_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_q012lbaddrate_t
-{
-    ZXIC_UINT32 cfg_qsch_q012lbaddrate;
-}DPP_ETM_QMU_CFG_QSCH_Q012LBADDRATE_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_q3creditlbmaxcnt_t
-{
-    ZXIC_UINT32 cfg_qsch_q3creditlbmaxcnt;
-}DPP_ETM_QMU_CFG_QSCH_Q3CREDITLBMAXCNT_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_q012creditlbmaxcnt_t
-{
-    ZXIC_UINT32 cfg_qsch_q012creditlbmaxcnt;
-}DPP_ETM_QMU_CFG_QSCH_Q012CREDITLBMAXCNT_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mul_token_gen_num_t
-{
-    ZXIC_UINT32 cfg_qsch_mul_token_gen_num;
-}DPP_ETM_QMU_CFG_QSCH_MUL_TOKEN_GEN_NUM_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_q3_credit_lb_control_en_t
-{
-    ZXIC_UINT32 cfg_qsch_q3_credit_lb_control_en;
-}DPP_ETM_QMU_CFG_QSCH_Q3_CREDIT_LB_CONTROL_EN_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_q012_credit_lb_control_en_t
-{
-    ZXIC_UINT32 cfg_qsch_q012_credit_lb_control_en;
-}DPP_ETM_QMU_CFG_QSCH_Q012_CREDIT_LB_CONTROL_EN_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_sp_dwrr_en_t
-{
-    ZXIC_UINT32 cfg_qsch_sp_dwrr_en;
-}DPP_ETM_QMU_CFG_QSCH_SP_DWRR_EN_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_q01_attach_en_t
-{
-    ZXIC_UINT32 cfg_qsch_q01_attach_en;
-}DPP_ETM_QMU_CFG_QSCH_Q01_ATTACH_EN_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_w0_t
-{
-    ZXIC_UINT32 cfg_qsch_w0;
-}DPP_ETM_QMU_CFG_QSCH_W0_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_w1_t
-{
-    ZXIC_UINT32 cfg_qsch_w1;
-}DPP_ETM_QMU_CFG_QSCH_W1_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_w2_t
-{
-    ZXIC_UINT32 cfg_qsch_w2;
-}DPP_ETM_QMU_CFG_QSCH_W2_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_lkybktmaxcnt1_t
-{
-    ZXIC_UINT32 cfg_qsch_lkybktmaxcnt1;
-}DPP_ETM_QMU_CFG_QSCH_LKYBKTMAXCNT1_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_lkybktmaxcnt2_t
-{
-    ZXIC_UINT32 cfg_qsch_lkybktmaxcnt2;
-}DPP_ETM_QMU_CFG_QSCH_LKYBKTMAXCNT2_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_lkybktdcrrate1_t
-{
-    ZXIC_UINT32 cfg_qsch_lkybktdcrrate1;
-}DPP_ETM_QMU_CFG_QSCH_LKYBKTDCRRATE1_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_lkybktdcrrate2_t
-{
-    ZXIC_UINT32 cfg_qsch_lkybktdcrrate2;
-}DPP_ETM_QMU_CFG_QSCH_LKYBKTDCRRATE2_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_lkybktdcrrate3_t
-{
-    ZXIC_UINT32 cfg_qsch_lkybktdcrrate3;
-}DPP_ETM_QMU_CFG_QSCH_LKYBKTDCRRATE3_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_lkybktmaxcnt3_t
-{
-    ZXIC_UINT32 cfg_qsch_lkybktmaxcnt3;
-}DPP_ETM_QMU_CFG_QSCH_LKYBKTMAXCNT3_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_qmu_mul_auto_sa_version_t
-{
-    ZXIC_UINT32 cfg_qsch_qmu_mul_auto_sa_version;
-}DPP_ETM_QMU_CFG_QSCH_QMU_MUL_AUTO_SA_VERSION_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_0_t
-{
-    ZXIC_UINT32 cfg_qsch_sa_credit_value_0;
-}DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_1_t
-{
-    ZXIC_UINT32 cfg_qsch_sa_credit_value_1;
-}DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_1_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_2_t
-{
-    ZXIC_UINT32 cfg_qsch_sa_credit_value_2;
-}DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_2_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_3_t
-{
-    ZXIC_UINT32 cfg_qsch_sa_credit_value_3;
-}DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_3_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_4_t
-{
-    ZXIC_UINT32 cfg_qsch_sa_credit_value_4;
-}DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_4_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_5_t
-{
-    ZXIC_UINT32 cfg_qsch_sa_credit_value_5;
-}DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_5_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_6_t
-{
-    ZXIC_UINT32 cfg_qsch_sa_credit_value_6;
-}DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_6_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_7_t
-{
-    ZXIC_UINT32 cfg_qsch_sa_credit_value_7;
-}DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_7_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_remote_credit_fifo_almost_full_th_t
-{
-    ZXIC_UINT32 cfg_qsch_remote_credit_fifo_almost_full_th;
-}DPP_ETM_QMU_CFG_QSCH_REMOTE_CREDIT_FIFO_ALMOST_FULL_TH_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_auto_credit_fifo_almost_full_th_t
-{
-    ZXIC_UINT32 cfg_qsch_auto_credit_fifo_almost_full_th;
-}DPP_ETM_QMU_CFG_QSCH_AUTO_CREDIT_FIFO_ALMOST_FULL_TH_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_q3_credit_fifo_almost_full_th_t
-{
-    ZXIC_UINT32 cfg_qsch_q3_credit_fifo_almost_full_th;
-}DPP_ETM_QMU_CFG_QSCH_Q3_CREDIT_FIFO_ALMOST_FULL_TH_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_q012_credit_fifo_almost_full_th_t
-{
-    ZXIC_UINT32 cfg_qsch_q012_credit_fifo_almost_full_th;
-}DPP_ETM_QMU_CFG_QSCH_Q012_CREDIT_FIFO_ALMOST_FULL_TH_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mul_fc_res_en_t
-{
-    ZXIC_UINT32 cfg_qsch_mul_fc_res_en;
-}DPP_ETM_QMU_CFG_QSCH_MUL_FC_RES_EN_T;
-
-typedef struct dpp_etm_qmu_cfgmt_mul_ovf_udf_flg_query_t
-{
-    ZXIC_UINT32 qsch_cfg_remote_credit_fifo_full;
-    ZXIC_UINT32 qsch_cfg_remote_credit_fifo_empty;
-    ZXIC_UINT32 qsch_cfg_remote_credit_fifo_overflow;
-    ZXIC_UINT32 qsch_cfg_remote_credit_fifo_underflow;
-    ZXIC_UINT32 qsch_cfg_auto_credit_fifo_full;
-    ZXIC_UINT32 qsch_cfg_auto_credit_fifo_empty;
-    ZXIC_UINT32 qsch_cfg_auto_credit_fifo_overflow;
-    ZXIC_UINT32 qsch_cfg_auto_credit_fifo_underflow;
-    ZXIC_UINT32 qsch_cfg_q3_credit_fifo_full;
-    ZXIC_UINT32 qsch_cfg_q3_credit_fifo_empty;
-    ZXIC_UINT32 qsch_cfg_q3_credit_fifo_overflow;
-    ZXIC_UINT32 qsch_cfg_q3_credit_fifo_underflow;
-    ZXIC_UINT32 qsch_cfg_q012_credit_fifo_full;
-    ZXIC_UINT32 qsch_cfg_q012_credit_fifo_empty;
-    ZXIC_UINT32 qsch_cfg_q012_credit_fifo_overflow;
-    ZXIC_UINT32 qsch_cfg_q012_credit_fifo_underflow;
-    ZXIC_UINT32 qsch_cfg_lkybktoverflow1;
-    ZXIC_UINT32 qsch_cfg_lkybktoverflow2;
-    ZXIC_UINT32 qsch_cfg_lkybktoverflow3;
-}DPP_ETM_QMU_CFGMT_MUL_OVF_UDF_FLG_QUERY_T;
-
-typedef struct dpp_etm_qmu_cfgmt_mul_cng_flg_query_t
-{
-    ZXIC_UINT32 qsch_cfg_q3cngflag;
-    ZXIC_UINT32 qsch_cfg_q012cngflag;
-    ZXIC_UINT32 qsch_cfg_cngflag1;
-    ZXIC_UINT32 qsch_cfg_cngflag2;
-    ZXIC_UINT32 qsch_cfg_cngflag3;
-}DPP_ETM_QMU_CFGMT_MUL_CNG_FLG_QUERY_T;
-
-typedef struct dpp_etm_qmu_qsch_cfg_lkybktval1_t
-{
-    ZXIC_UINT32 qsch_cfg_lkybktval1;
-}DPP_ETM_QMU_QSCH_CFG_LKYBKTVAL1_T;
-
-typedef struct dpp_etm_qmu_qsch_cfg_lkybktval2_t
-{
-    ZXIC_UINT32 qsch_cfg_lkybktval2;
-}DPP_ETM_QMU_QSCH_CFG_LKYBKTVAL2_T;
-
-typedef struct dpp_etm_qmu_qsch_cfg_lkybktval3_t
-{
-    ZXIC_UINT32 qsch_cfg_lkybktval3;
-}DPP_ETM_QMU_QSCH_CFG_LKYBKTVAL3_T;
-
-typedef struct dpp_etm_qmu_qsch_cfg_q3lbval_t
-{
-    ZXIC_UINT32 qsch_cfg_q3lbval;
-}DPP_ETM_QMU_QSCH_CFG_Q3LBVAL_T;
-
-typedef struct dpp_etm_qmu_qsch_cfg_q012lbval_t
-{
-    ZXIC_UINT32 qsch_cfg_q012lbval;
-}DPP_ETM_QMU_QSCH_CFG_Q012LBVAL_T;
-
-typedef struct dpp_etm_qmu_qlist_cfgmt_ram_ecc_err2_t
-{
-    ZXIC_UINT32 qlist_imem_pd_ram_single_ecc_err;
-    ZXIC_UINT32 qlist_imem_pd_ram_double_ecc_err;
-    ZXIC_UINT32 qlist_imem_up_ptr_ram_single_ecc_err;
-    ZXIC_UINT32 qlist_imem_up_ptr_ram_double_ecc_err;
-    ZXIC_UINT32 qlist_imem_down_ptr_ram_single_ecc_err;
-    ZXIC_UINT32 qlist_imem_down_ptr_ram_double_ecc_err;
-    ZXIC_UINT32 cmdsw_sop_fifo_single_ecc_err;
-    ZXIC_UINT32 cmdsw_sop_fifo_double_ecc_err;
-    ZXIC_UINT32 cmdsw_nsop_fifo_single_ecc_err;
-    ZXIC_UINT32 cmdsw_nsop_fifo_double_ecc_err;
-    ZXIC_UINT32 cmdsw_mmudat_fifo_single_ecc_err;
-    ZXIC_UINT32 cmdsw_mmudat_fifo_double_ecc_err;
-    ZXIC_UINT32 qlist_rd_release_fwft_single_ecc_err;
-    ZXIC_UINT32 qlist_rd_release_fwft_double_ecc_err;
-    ZXIC_UINT32 qlist_drop_imem_fwft_single_ecc_err;
-    ZXIC_UINT32 qlist_drop_imem_fwft_double_ecc_err;
-}DPP_ETM_QMU_QLIST_CFGMT_RAM_ECC_ERR2_T;
-
-typedef struct dpp_etm_qmu_csch_aged_cmd_cnt_t
-{
-    ZXIC_UINT32 csch_aged_cmd_cnt;
-}DPP_ETM_QMU_CSCH_AGED_CMD_CNT_T;
-
-typedef struct dpp_etm_qmu_csch_qcfg_csch_congest_cnt_t
-{
-    ZXIC_UINT32 csch_qcfg_csch_congest_cnt;
-}DPP_ETM_QMU_CSCH_QCFG_CSCH_CONGEST_CNT_T;
-
-typedef struct dpp_etm_qmu_csch_qcfg_qlist_csch_sop_cnt_t
-{
-    ZXIC_UINT32 csch_qcfg_qlist_csch_sop_cnt;
-}DPP_ETM_QMU_CSCH_QCFG_QLIST_CSCH_SOP_CNT_T;
-
-typedef struct dpp_etm_qmu_csch_qcfg_qlist_csch_eop_cnt_t
-{
-    ZXIC_UINT32 csch_qcfg_qlist_csch_eop_cnt;
-}DPP_ETM_QMU_CSCH_QCFG_QLIST_CSCH_EOP_CNT_T;
-
-typedef struct dpp_etm_qmu_csch_qcfg_csch_csw_sop_cnt_t
-{
-    ZXIC_UINT32 csch_qcfg_csch_csw_sop_cnt;
-}DPP_ETM_QMU_CSCH_QCFG_CSCH_CSW_SOP_CNT_T;
-
-typedef struct dpp_etm_qmu_csch_qcfg_csch_csw_eop_cnt_t
-{
-    ZXIC_UINT32 csch_qcfg_csch_csw_eop_cnt;
-}DPP_ETM_QMU_CSCH_QCFG_CSCH_CSW_EOP_CNT_T;
-
-typedef struct dpp_etm_qmu_csch_qcfg_qlist_csch_drop_cnt_t
-{
-    ZXIC_UINT32 csch_qcfg_qlist_csch_drop_cnt;
-}DPP_ETM_QMU_CSCH_QCFG_QLIST_CSCH_DROP_CNT_T;
-
-typedef struct dpp_etm_qmu_csch_qcfg_csch_csw_drop_cnt_t
-{
-    ZXIC_UINT32 csch_qcfg_csch_csw_drop_cnt;
-}DPP_ETM_QMU_CSCH_QCFG_CSCH_CSW_DROP_CNT_T;
-
-typedef struct dpp_etm_qmu_csw_mmu_sop_cmd_cnt_t
-{
-    ZXIC_UINT32 csw_mmu_sop_cmd_cnt;
-}DPP_ETM_QMU_CSW_MMU_SOP_CMD_CNT_T;
-
-typedef struct dpp_etm_qmu_mmu_csw_sop_data_cnt_t
-{
-    ZXIC_UINT32 mmu_csw_sop_data_cnt;
-}DPP_ETM_QMU_MMU_CSW_SOP_DATA_CNT_T;
-
-typedef struct dpp_etm_qmu_csw_qsch_feedb_cnt_t
-{
-    ZXIC_UINT32 csw_qsch_feedb_cnt;
-}DPP_ETM_QMU_CSW_QSCH_FEEDB_CNT_T;
-
-typedef struct dpp_etm_qmu_qmu_crdt_port_fc_cnt_t
-{
-    ZXIC_UINT32 qmu_crdt_port_fc_cnt;
-}DPP_ETM_QMU_QMU_CRDT_PORT_FC_CNT_T;
-
-typedef struct dpp_etm_qmu_csch_r_block_cnt_t
-{
-    ZXIC_UINT32 csch_r_block_cnt;
-}DPP_ETM_QMU_CSCH_R_BLOCK_CNT_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_qds_head_rd_t
-{
-    ZXIC_UINT32 qcfg_qlist_qds_head_rd;
-}DPP_ETM_QMU_QCFG_QLIST_QDS_HEAD_RD_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_qds_tail_rd_t
-{
-    ZXIC_UINT32 qcfg_qlist_qds_tail_rd;
-}DPP_ETM_QMU_QCFG_QLIST_QDS_TAIL_RD_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_ept_rd_t
-{
-    ZXIC_UINT32 qcfg_qlist_ept_rd;
-}DPP_ETM_QMU_QCFG_QLIST_EPT_RD_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_age_flag_rd_t
-{
-    ZXIC_UINT32 qcfg_qlist_age_flag_rd;
-}DPP_ETM_QMU_QCFG_QLIST_AGE_FLAG_RD_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_cti_rd_t
-{
-    ZXIC_UINT32 qcfg_qlist_cti_rd;
-}DPP_ETM_QMU_QCFG_QLIST_CTI_RD_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_cto_rd_t
-{
-    ZXIC_UINT32 qcfg_qlist_cto_rd;
-}DPP_ETM_QMU_QCFG_QLIST_CTO_RD_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_chk_rd_t
-{
-    ZXIC_UINT32 qcfg_qlist_chk_rd;
-}DPP_ETM_QMU_QCFG_QLIST_CHK_RD_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_nod_rd_t
-{
-    ZXIC_UINT32 qcfg_qlist_nod_rd;
-}DPP_ETM_QMU_QCFG_QLIST_NOD_RD_T;
-
-typedef struct dpp_etm_qmu_qcfg_qlist_biu_rd_t
-{
-    ZXIC_UINT32 qcfg_qlist_biu_rd;
-}DPP_ETM_QMU_QCFG_QLIST_BIU_RD_T;
-
-typedef struct dpp_etm_qmu_qsch_r_wlist_flag_t
-{
-    ZXIC_UINT32 qsch_r_wlist_flag;
-}DPP_ETM_QMU_QSCH_R_WLIST_FLAG_T;
-
-typedef struct dpp_etm_qmu_qcfg_crs_flg_rd_t
-{
-    ZXIC_UINT32 qcfg_crs_flg_rd;
-}DPP_ETM_QMU_QCFG_CRS_FLG_RD_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_imem_age_qds_t
-{
-    ZXIC_UINT32 cfgmt_qmu_imem_tp;
-    ZXIC_UINT32 cfgmt_qmu_imem_hp;
-}DPP_ETM_QMU_CFGMT_QMU_IMEM_AGE_QDS_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_imem_age_qlen_t
-{
-    ZXIC_UINT32 cfgmt_qmu_imem_no_empty;
-    ZXIC_UINT32 cfgmt_qmu_imem_qlen;
-}DPP_ETM_QMU_CFGMT_QMU_IMEM_AGE_QLEN_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_imem_pd_ram_low_t
-{
-    ZXIC_UINT32 cfgmt_qmu_imem_pd_ram_low;
-}DPP_ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_LOW_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_imem_pd_ram_high_t
-{
-    ZXIC_UINT32 cfgmt_qmu_imem_pd_ram_high;
-}DPP_ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_HIGH_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_imem_up_ptr_t
-{
-    ZXIC_UINT32 cfgmt_qmu_imem_up_ptr;
-}DPP_ETM_QMU_CFGMT_QMU_IMEM_UP_PTR_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_imem_down_ptr_t
-{
-    ZXIC_UINT32 cfgmt_qmu_imem_down_ptr;
-}DPP_ETM_QMU_CFGMT_QMU_IMEM_DOWN_PTR_T;
-
-typedef struct dpp_etm_qmu_cfgmt_qmu_imem_age_flag_t
-{
-    ZXIC_UINT32 cfgmt_qmu_imem_age_flag;
-}DPP_ETM_QMU_CFGMT_QMU_IMEM_AGE_FLAG_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_lkybkt2cngth_t
-{
-    ZXIC_UINT32 cfg_qsch_lkybkt2cngth;
-}DPP_ETM_QMU_CFG_QSCH_LKYBKT2CNGTH_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_lkybkt1cngth_t
-{
-    ZXIC_UINT32 cfg_qsch_lkybkt1cngth;
-}DPP_ETM_QMU_CFG_QSCH_LKYBKT1CNGTH_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_lkybkt3cngth_t
-{
-    ZXIC_UINT32 cfg_qsch_lkybkt3cngth;
-}DPP_ETM_QMU_CFG_QSCH_LKYBKT3CNGTH_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn1_credit_value_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_credit_value;
-}DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN1_CREDIT_VALUE_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn2_credit_value_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_credit_value;
-}DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN2_CREDIT_VALUE_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn3_credit_value_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_credit_value;
-}DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN3_CREDIT_VALUE_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_ansr_seed_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_mchsm_en;
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_ansr_seed;
-}DPP_ETM_QMU_RM_MUL_MCN1_RAND_ANSR_SEED_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_ansr_seed_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_mchsm_en;
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_ansr_seed;
-}DPP_ETM_QMU_RM_MUL_MCN2_RAND_ANSR_SEED_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_ansr_seed_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_mchsm_en;
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_ansr_seed;
-}DPP_ETM_QMU_RM_MUL_MCN3_RAND_ANSR_SEED_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_ansr_th_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_ansr_th;
-}DPP_ETM_QMU_RM_MUL_MCN1_RAND_ANSR_TH_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_ansr_th_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_ansr_th;
-}DPP_ETM_QMU_RM_MUL_MCN2_RAND_ANSR_TH_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_ansr_th_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_ansr_th;
-}DPP_ETM_QMU_RM_MUL_MCN3_RAND_ANSR_TH_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_hold_base_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_mchsm_en;
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_hold_base;
-}DPP_ETM_QMU_RM_MUL_MCN1_RAND_HOLD_BASE_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_hold_base_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_mchsm_en;
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_hold_base;
-}DPP_ETM_QMU_RM_MUL_MCN2_RAND_HOLD_BASE_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_hold_base_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_mchsm_en;
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_hold_base;
-}DPP_ETM_QMU_RM_MUL_MCN3_RAND_HOLD_BASE_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_sel_mask_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_sel_mask;
-}DPP_ETM_QMU_RM_MUL_MCN1_RAND_SEL_MASK_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_sel_mask_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_sel_mask;
-}DPP_ETM_QMU_RM_MUL_MCN2_RAND_SEL_MASK_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_sel_mask_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_sel_mask;
-}DPP_ETM_QMU_RM_MUL_MCN3_RAND_SEL_MASK_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg0_t
-{
-    ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed7;
-    ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed6;
-    ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed5;
-    ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed4;
-    ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed3;
-    ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed2;
-    ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed1;
-    ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed0;
-}DPP_ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG0_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg1_t
-{
-    ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed8;
-}DPP_ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG1_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg0_t
-{
-    ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed7;
-    ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed6;
-    ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed5;
-    ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed4;
-    ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed3;
-    ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed2;
-    ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed1;
-    ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed0;
-}DPP_ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG0_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg1_t
-{
-    ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed8;
-}DPP_ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG1_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg0_t
-{
-    ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed7;
-    ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed6;
-    ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed5;
-    ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed4;
-    ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed3;
-    ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed2;
-    ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed1;
-    ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed0;
-}DPP_ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG0_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg1_t
-{
-    ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed8;
-}DPP_ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG1_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th1_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th1;
-}DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH1_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th2_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th2;
-}DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH2_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th3_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th3;
-}DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH3_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th4_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th4;
-}DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH4_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th5_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th5;
-}DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH5_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th6_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th6;
-}DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH6_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th7_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th7;
-}DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH7_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th1_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th1;
-}DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH1_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th2_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th2;
-}DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH2_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th3_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th3;
-}DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH3_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th4_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th4;
-}DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH4_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th5_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th5;
-}DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH5_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th6_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th6;
-}DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH6_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th7_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th7;
-}DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH7_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th1_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th1;
-}DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH1_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th2_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th2;
-}DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH2_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th3_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th3;
-}DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH3_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th4_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th4;
-}DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH4_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th5_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th5;
-}DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH5_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th6_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th6;
-}DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH6_T;
-
-typedef struct dpp_etm_qmu_rm_mul_mcn3step_wait_th7_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th7;
-}DPP_ETM_QMU_RM_MUL_MCN3STEP_WAIT_TH7_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate0_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate0;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE0_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate1_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate1;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE1_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate2_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate2;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE2_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate3_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate3;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE3_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate4_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate4;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE4_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate5_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate5;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE5_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate6_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate6;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE6_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate7_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate7;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE7_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate8_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate8;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE8_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate9_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate9;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE9_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate10_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate10;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE10_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate11_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate11;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE11_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate12_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate12;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE12_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate13_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate13;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE13_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate14_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate14;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE14_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate15_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate15;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE15_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate16_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate16;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE16_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate17_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate17;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE17_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate18_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate18;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE18_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate19_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate19;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE19_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate20_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate20;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE20_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate21_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate21;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE21_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate22_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate22;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE22_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate23_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate23;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE23_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate24_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate24;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE24_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate25_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate25;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE25_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate26_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate26;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE26_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate27_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate27;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE27_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate28_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate28;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE28_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate29_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate29;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE29_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate30_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate30;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE30_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate31_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate31;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE31_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate32_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate32;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE32_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate33_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate33;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE33_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate34_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate34;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE34_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate35_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate35;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE35_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate36_t
-{
-    ZXIC_UINT32 cfg_qsch_mulcrdcntrate36;
-}DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE36_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn1_rand_hold_shift_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_hold_shift;
-}DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN1_RAND_HOLD_SHIFT_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn2_rand_hold_shift_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_hold_shift;
-}DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN2_RAND_HOLD_SHIFT_T;
-
-typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn3_rand_hold_shift_t
-{
-    ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_hold_shift;
-}DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN3_RAND_HOLD_SHIFT_T;
-
-typedef struct dpp_etm_qmu_last_drop_qnum_get_t
-{
-    ZXIC_UINT32 cgavd_qmu_drop_tap;
-    ZXIC_UINT32 last_drop_qnum;
-}DPP_ETM_QMU_LAST_DROP_QNUM_GET_T;
-
-typedef struct dpp_etm_qmu_crdt_qmu_credit_cnt_t
-{
-    ZXIC_UINT32 crdt_qmu_credit_cnt;
-}DPP_ETM_QMU_CRDT_QMU_CREDIT_CNT_T;
-
-typedef struct dpp_etm_qmu_qmu_to_qsch_report_cnt_t
-{
-    ZXIC_UINT32 qmu_to_qsch_report_cnt;
-}DPP_ETM_QMU_QMU_TO_QSCH_REPORT_CNT_T;
-
-typedef struct dpp_etm_qmu_qmu_to_cgavd_report_cnt_t
-{
-    ZXIC_UINT32 qmu_to_cgavd_report_cnt;
-}DPP_ETM_QMU_QMU_TO_CGAVD_REPORT_CNT_T;
-
-typedef struct dpp_etm_qmu_qmu_crdt_crs_normal_cnt_t
-{
-    ZXIC_UINT32 qmu_crdt_crs_normal_cnt;
-}DPP_ETM_QMU_QMU_CRDT_CRS_NORMAL_CNT_T;
-
-typedef struct dpp_etm_qmu_qmu_crdt_crs_off_cnt_t
-{
-    ZXIC_UINT32 qmu_crdt_crs_off_cnt;
-}DPP_ETM_QMU_QMU_CRDT_CRS_OFF_CNT_T;
-
-typedef struct dpp_etm_qmu_qsch_qlist_shedule_cnt_t
-{
-    ZXIC_UINT32 qsch_qlist_shedule_cnt;
-}DPP_ETM_QMU_QSCH_QLIST_SHEDULE_CNT_T;
-
-typedef struct dpp_etm_qmu_qsch_qlist_sch_ept_cnt_t
-{
-    ZXIC_UINT32 qsch_qlist_sch_ept_cnt;
-}DPP_ETM_QMU_QSCH_QLIST_SCH_EPT_CNT_T;
-
-typedef struct dpp_etm_qmu_qmu_to_mmu_blk_wr_cnt_t
-{
-    ZXIC_UINT32 qmu_to_mmu_blk_wr_cnt;
-}DPP_ETM_QMU_QMU_TO_MMU_BLK_WR_CNT_T;
-
-typedef struct dpp_etm_qmu_qmu_to_csw_blk_rd_cnt_t
-{
-    ZXIC_UINT32 qmu_to_csw_blk_rd_cnt;
-}DPP_ETM_QMU_QMU_TO_CSW_BLK_RD_CNT_T;
-
-typedef struct dpp_etm_qmu_qmu_to_mmu_sop_wr_cnt_t
-{
-    ZXIC_UINT32 qmu_to_mmu_sop_wr_cnt;
-}DPP_ETM_QMU_QMU_TO_MMU_SOP_WR_CNT_T;
-
-typedef struct dpp_etm_qmu_qmu_to_mmu_eop_wr_cnt_t
-{
-    ZXIC_UINT32 qmu_to_mmu_eop_wr_cnt;
-}DPP_ETM_QMU_QMU_TO_MMU_EOP_WR_CNT_T;
-
-typedef struct dpp_etm_qmu_qmu_to_mmu_drop_wr_cnt_t
-{
-    ZXIC_UINT32 qmu_to_mmu_drop_wr_cnt;
-}DPP_ETM_QMU_QMU_TO_MMU_DROP_WR_CNT_T;
-
-typedef struct dpp_etm_qmu_qmu_to_csw_sop_rd_cnt_t
-{
-    ZXIC_UINT32 qmu_to_csw_sop_rd_cnt;
-}DPP_ETM_QMU_QMU_TO_CSW_SOP_RD_CNT_T;
-
-typedef struct dpp_etm_qmu_qmu_to_csw_eop_rd_cnt_t
-{
-    ZXIC_UINT32 qmu_to_csw_eop_rd_cnt;
-}DPP_ETM_QMU_QMU_TO_CSW_EOP_RD_CNT_T;
-
-typedef struct dpp_etm_qmu_qmu_to_csw_drop_rd_cnt_t
-{
-    ZXIC_UINT32 qmu_to_csw_drop_rd_cnt;
-}DPP_ETM_QMU_QMU_TO_CSW_DROP_RD_CNT_T;
-
-typedef struct dpp_etm_qmu_mmu_to_qmu_wr_release_cnt_t
-{
-    ZXIC_UINT32 mmu_to_qmu_wr_release_cnt;
-}DPP_ETM_QMU_MMU_TO_QMU_WR_RELEASE_CNT_T;
-
-typedef struct dpp_etm_qmu_mmu_to_qmu_rd_release_cnt_t
-{
-    ZXIC_UINT32 mmu_to_qmu_rd_release_cnt;
-}DPP_ETM_QMU_MMU_TO_QMU_RD_RELEASE_CNT_T;
-
-typedef struct dpp_etm_qmu_observe_qnum_set_t
-{
-    ZXIC_UINT32 observe_qnum_set;
-}DPP_ETM_QMU_OBSERVE_QNUM_SET_T;
-
-typedef struct dpp_etm_qmu_spec_q_pkt_received_t
-{
-    ZXIC_UINT32 spec_q_pkt_received;
-}DPP_ETM_QMU_SPEC_Q_PKT_RECEIVED_T;
-
-typedef struct dpp_etm_qmu_spec_q_pkt_dropped_t
-{
-    ZXIC_UINT32 spec_q_pkt_dropped;
-}DPP_ETM_QMU_SPEC_Q_PKT_DROPPED_T;
-
-typedef struct dpp_etm_qmu_spec_q_pkt_scheduled_t
-{
-    ZXIC_UINT32 spec_q_pkt_scheduled;
-}DPP_ETM_QMU_SPEC_Q_PKT_SCHEDULED_T;
-
-typedef struct dpp_etm_qmu_spec_q_wr_cmd_sent_t
-{
-    ZXIC_UINT32 spec_q_wr_cmd_sent;
-}DPP_ETM_QMU_SPEC_Q_WR_CMD_SENT_T;
-
-typedef struct dpp_etm_qmu_spec_q_rd_cmd_sent_t
-{
-    ZXIC_UINT32 spec_q_rd_cmd_sent;
-}DPP_ETM_QMU_SPEC_Q_RD_CMD_SENT_T;
-
-typedef struct dpp_etm_qmu_spec_q_pkt_enq_t
-{
-    ZXIC_UINT32 spec_q_pkt_enq;
-}DPP_ETM_QMU_SPEC_Q_PKT_ENQ_T;
-
-typedef struct dpp_etm_qmu_spec_q_pkt_deq_t
-{
-    ZXIC_UINT32 spec_q_pkt_deq;
-}DPP_ETM_QMU_SPEC_Q_PKT_DEQ_T;
-
-typedef struct dpp_etm_qmu_spec_q_crdt_uncon_received_t
-{
-    ZXIC_UINT32 spec_q_crdt_uncon_received;
-}DPP_ETM_QMU_SPEC_Q_CRDT_UNCON_RECEIVED_T;
-
-typedef struct dpp_etm_qmu_spec_q_crdt_cong_received_t
-{
-    ZXIC_UINT32 spec_q_crdt_cong_received;
-}DPP_ETM_QMU_SPEC_Q_CRDT_CONG_RECEIVED_T;
-
-typedef struct dpp_etm_qmu_spec_q_crs_normal_cnt_t
-{
-    ZXIC_UINT32 spec_q_crs_normal_cnt;
-}DPP_ETM_QMU_SPEC_Q_CRS_NORMAL_CNT_T;
-
-typedef struct dpp_etm_qmu_spec_q_crs_off_cnt_t
-{
-    ZXIC_UINT32 spec_q_crs_off_cnt;
-}DPP_ETM_QMU_SPEC_Q_CRS_OFF_CNT_T;
-
-typedef struct dpp_etm_qmu_observe_batch_set_t
-{
-    ZXIC_UINT32 observe_batch_set;
-}DPP_ETM_QMU_OBSERVE_BATCH_SET_T;
-
-typedef struct dpp_etm_qmu_spec_bat_pkt_received_t
-{
-    ZXIC_UINT32 spec_bat_pkt_received;
-}DPP_ETM_QMU_SPEC_BAT_PKT_RECEIVED_T;
-
-typedef struct dpp_etm_qmu_spec_bat_pkt_dropped_t
-{
-    ZXIC_UINT32 spec_bat_pkt_dropped;
-}DPP_ETM_QMU_SPEC_BAT_PKT_DROPPED_T;
-
-typedef struct dpp_etm_qmu_spec_bat_blk_scheduled_t
-{
-    ZXIC_UINT32 spec_bat_blk_scheduled;
-}DPP_ETM_QMU_SPEC_BAT_BLK_SCHEDULED_T;
-
-typedef struct dpp_etm_qmu_spec_bat_wr_cmd_sent_t
-{
-    ZXIC_UINT32 spec_bat_wr_cmd_sent;
-}DPP_ETM_QMU_SPEC_BAT_WR_CMD_SENT_T;
-
-typedef struct dpp_etm_qmu_spec_bat_rd_cmd_sent_t
-{
-    ZXIC_UINT32 spec_bat_rd_cmd_sent;
-}DPP_ETM_QMU_SPEC_BAT_RD_CMD_SENT_T;
-
-typedef struct dpp_etm_qmu_spec_bat_pkt_enq_t
-{
-    ZXIC_UINT32 spec_bat_pkt_enq;
-}DPP_ETM_QMU_SPEC_BAT_PKT_ENQ_T;
-
-typedef struct dpp_etm_qmu_spec_bat_pkt_deq_t
-{
-    ZXIC_UINT32 spec_bat_pkt_deq;
-}DPP_ETM_QMU_SPEC_BAT_PKT_DEQ_T;
-
-typedef struct dpp_etm_qmu_spec_bat_crdt_uncon_received_t
-{
-    ZXIC_UINT32 spec_bat_crdt_uncon_received;
-}DPP_ETM_QMU_SPEC_BAT_CRDT_UNCON_RECEIVED_T;
-
-typedef struct dpp_etm_qmu_spec_bat_crdt_cong_received_t
-{
-    ZXIC_UINT32 spec_bat_crdt_cong_received;
-}DPP_ETM_QMU_SPEC_BAT_CRDT_CONG_RECEIVED_T;
-
-typedef struct dpp_etm_qmu_spec_bat_crs_normal_cnt_t
-{
-    ZXIC_UINT32 spec_bat_crs_normal_cnt;
-}DPP_ETM_QMU_SPEC_BAT_CRS_NORMAL_CNT_T;
-
-typedef struct dpp_etm_qmu_spec_bat_crs_off_cnt_t
-{
-    ZXIC_UINT32 spec_bat_crs_off_cnt;
-}DPP_ETM_QMU_SPEC_BAT_CRS_OFF_CNT_T;
-
-typedef struct dpp_etm_qmu_bcntm_ovfl_qnum_get_t
-{
-    ZXIC_UINT32 bcntm_ovfl_qnum_get;
-}DPP_ETM_QMU_BCNTM_OVFL_QNUM_GET_T;
-
-typedef struct dpp_etm_qmu_crbal_a_ovf_qnum_get_t
-{
-    ZXIC_UINT32 crbal_a_ovf_qnum_get;
-}DPP_ETM_QMU_CRBAL_A_OVF_QNUM_GET_T;
-
-typedef struct dpp_etm_qmu_crbal_b_ovf_qnum_get_t
-{
-    ZXIC_UINT32 crbal_b_ovf_qnum_get;
-}DPP_ETM_QMU_CRBAL_B_OVF_QNUM_GET_T;
-
-typedef struct dpp_etm_qmu_crbal_drop_qnum_get_t
-{
-    ZXIC_UINT32 crbal_drop_qnum_get;
-}DPP_ETM_QMU_CRBAL_DROP_QNUM_GET_T;
-
-typedef struct dpp_etm_qmu_deq_flg_report_cnt_t
-{
-    ZXIC_UINT32 deq_flg_report_cnt;
-}DPP_ETM_QMU_DEQ_FLG_REPORT_CNT_T;
-
-typedef struct dpp_etm_qmu_spec_q_crs_get_t
-{
-    ZXIC_UINT32 spec_q_crs_get;
-}DPP_ETM_QMU_SPEC_Q_CRS_GET_T;
-
-typedef struct dpp_etm_qmu_spec_q_crs_in_get_t
-{
-    ZXIC_UINT32 spec_q_crs_in_get;
-}DPP_ETM_QMU_SPEC_Q_CRS_IN_GET_T;
-
-typedef struct dpp_etm_qmu_spec_q_crs_flg_csol_get_t
-{
-    ZXIC_UINT32 spec_q_crs_flg_csol_get;
-}DPP_ETM_QMU_SPEC_Q_CRS_FLG_CSOL_GET_T;
-
-typedef struct dpp_etm_qmu_ept_sch_qnum_get_t
-{
-    ZXIC_UINT32 ept_sch_qnum_get;
-}DPP_ETM_QMU_EPT_SCH_QNUM_GET_T;
+typedef struct dpp_etm_cfgmt_cpu_check_reg_t {
+	ZXIC_UINT32 cpu_check_reg;
+} DPP_ETM_CFGMT_CPU_CHECK_REG_T;
+
+typedef struct dpp_etm_cfgmt_cfgmt_blksize_t {
+	ZXIC_UINT32 cfgmt_blksize;
+} DPP_ETM_CFGMT_CFGMT_BLKSIZE_T;
+
+typedef struct dpp_etm_cfgmt_reg_int_state_reg_t {
+	ZXIC_UINT32 shap_int;
+	ZXIC_UINT32 crdt_int;
+	ZXIC_UINT32 mmu_int;
+	ZXIC_UINT32 qmu_int;
+	ZXIC_UINT32 cgavd_int;
+	ZXIC_UINT32 olif_int;
+	ZXIC_UINT32 cfgmt_int_buf;
+} DPP_ETM_CFGMT_REG_INT_STATE_REG_T;
+
+typedef struct dpp_etm_cfgmt_reg_int_mask_reg_t {
+	ZXIC_UINT32 shap_int_mask;
+	ZXIC_UINT32 crdt_int_mask;
+	ZXIC_UINT32 tmmu_int_mask;
+	ZXIC_UINT32 qmu_int_mask;
+	ZXIC_UINT32 cgavd_int_mask;
+	ZXIC_UINT32 olif_int_mask;
+	ZXIC_UINT32 cfgmt_int_buf_mask;
+} DPP_ETM_CFGMT_REG_INT_MASK_REG_T;
+
+typedef struct dpp_etm_cfgmt_timeout_limit_t {
+	ZXIC_UINT32 timeout_limit;
+} DPP_ETM_CFGMT_TIMEOUT_LIMIT_T;
+
+typedef struct dpp_etm_cfgmt_subsystem_rdy_reg_t {
+	ZXIC_UINT32 olif_rdy;
+	ZXIC_UINT32 qmu_rdy;
+	ZXIC_UINT32 cgavd_rdy;
+	ZXIC_UINT32 tmmu_rdy;
+	ZXIC_UINT32 shap_rdy;
+	ZXIC_UINT32 crdt_rdy;
+} DPP_ETM_CFGMT_SUBSYSTEM_RDY_REG_T;
+
+typedef struct dpp_etm_cfgmt_subsystem_en_reg_t {
+	ZXIC_UINT32 subsystem_en_buf_31_28;
+	ZXIC_UINT32 subsystem_en_buf_25_0;
+} DPP_ETM_CFGMT_SUBSYSTEM_EN_REG_T;
+
+typedef struct dpp_etm_cfgmt_cfgmt_int_reg_t {
+	ZXIC_UINT32 cfgmt_int_buf;
+} DPP_ETM_CFGMT_CFGMT_INT_REG_T;
+
+typedef struct dpp_etm_cfgmt_qmu_work_mode_t {
+	ZXIC_UINT32 qmu_work_mode;
+} DPP_ETM_CFGMT_QMU_WORK_MODE_T;
+
+typedef struct dpp_etm_cfgmt_cfgmt_ddr_attach_t {
+	ZXIC_UINT32 cfgmt_ddr_attach;
+} DPP_ETM_CFGMT_CFGMT_DDR_ATTACH_T;
+
+typedef struct dpp_etm_cfgmt_cnt_mode_reg_t {
+	ZXIC_UINT32 cfgmt_fc_count_mode;
+	ZXIC_UINT32 cfgmt_count_rd_mode;
+	ZXIC_UINT32 cfgmt_count_overflow_mode;
+} DPP_ETM_CFGMT_CNT_MODE_REG_T;
+
+typedef struct dpp_etm_cfgmt_clkgate_en_t {
+	ZXIC_UINT32 clkgate_en;
+} DPP_ETM_CFGMT_CLKGATE_EN_T;
+
+typedef struct dpp_etm_cfgmt_softrst_en_t {
+	ZXIC_UINT32 softrst_en;
+} DPP_ETM_CFGMT_SOFTRST_EN_T;
+
+typedef struct dpp_etm_olif_imem_prog_full_t {
+	ZXIC_UINT32 imem_prog_full_assert;
+	ZXIC_UINT32 imem_prog_full_negate;
+} DPP_ETM_OLIF_IMEM_PROG_FULL_T;
+
+typedef struct dpp_etm_olif_qmu_para_prog_full_t {
+	ZXIC_UINT32 qmu_para_prog_full_assert;
+	ZXIC_UINT32 qmu_para_prog_full_negate;
+} DPP_ETM_OLIF_QMU_PARA_PROG_FULL_T;
+
+typedef struct dpp_etm_olif_olif_int_mask_t {
+	ZXIC_UINT32 emem_dat_sop_err_mask;
+	ZXIC_UINT32 emem_dat_eop_err_mask;
+	ZXIC_UINT32 imem_dat_sop_err_mask;
+	ZXIC_UINT32 imem_dat_eop_err_mask;
+	ZXIC_UINT32 crcram_parity_err_mask;
+	ZXIC_UINT32 emem_fifo_ecc_mask;
+	ZXIC_UINT32 imem_fifo_ecc_mask;
+	ZXIC_UINT32 emem_fifo_ovf_mask;
+	ZXIC_UINT32 emem_fifo_udf_mask;
+	ZXIC_UINT32 imem_fifo_ovf_mask;
+	ZXIC_UINT32 imem_fifo_udf_mask;
+	ZXIC_UINT32 para_fifo_ecc_mask;
+	ZXIC_UINT32 para_fifo_ovf_mask;
+	ZXIC_UINT32 para_fifo_udf_mask;
+	ZXIC_UINT32 itmh_ecc_single_err_mask;
+	ZXIC_UINT32 itmh_ecc_double_err_mask;
+	ZXIC_UINT32 order_fifo_parity_err_mask;
+	ZXIC_UINT32 order_fifo_ovf_mask;
+	ZXIC_UINT32 order_fifo_udf_mask;
+} DPP_ETM_OLIF_OLIF_INT_MASK_T;
+
+typedef struct dpp_etm_olif_itmhram_parity_err_2_int_t {
+	ZXIC_UINT32 emem_dat_sop_err;
+	ZXIC_UINT32 emem_dat_eop_err;
+	ZXIC_UINT32 imem_dat_sop_err;
+	ZXIC_UINT32 imem_dat_eop_err;
+	ZXIC_UINT32 crcram_parity_err_1_int;
+	ZXIC_UINT32 emem_fifo_ecc_single_err_int;
+	ZXIC_UINT32 emem_fifo_ecc_double_err_int;
+	ZXIC_UINT32 imem_fifo_ecc_single_err_int;
+	ZXIC_UINT32 imem_fifo_ecc_double_err_int;
+	ZXIC_UINT32 emem_fifo_ovf_int;
+	ZXIC_UINT32 emem_fifo_udf_int;
+	ZXIC_UINT32 imem_fifo_ovf_int;
+	ZXIC_UINT32 imem_fifo_udf_int;
+	ZXIC_UINT32 para_fifo_ecc_single_err_int;
+	ZXIC_UINT32 para_fifo_ecc_double_err_int;
+	ZXIC_UINT32 para_fifo_ovf_int;
+	ZXIC_UINT32 para_fifo_udf_int;
+	ZXIC_UINT32 itmh_ecc_single_err_int;
+	ZXIC_UINT32 itmh_ecc_double_err_int;
+	ZXIC_UINT32 order_fifo_parity_err_int;
+	ZXIC_UINT32 order_fifo_ovf_int;
+	ZXIC_UINT32 order_fifo_udf_int;
+} DPP_ETM_OLIF_ITMHRAM_PARITY_ERR_2_INT_T;
+
+typedef struct dpp_etm_olif_lif0_port_rdy_mask_h_t {
+	ZXIC_UINT32 lif0_port_rdy_mask_h;
+} DPP_ETM_OLIF_LIF0_PORT_RDY_MASK_H_T;
+
+typedef struct dpp_etm_olif_lif0_port_rdy_mask_l_t {
+	ZXIC_UINT32 lif0_port_rdy_mask_l;
+} DPP_ETM_OLIF_LIF0_PORT_RDY_MASK_L_T;
+
+typedef struct dpp_etm_olif_lif0_port_rdy_cfg_h_t {
+	ZXIC_UINT32 lif0_port_rdy_cfg_h;
+} DPP_ETM_OLIF_LIF0_PORT_RDY_CFG_H_T;
+
+typedef struct dpp_etm_olif_lif0_port_rdy_cfg_l_t {
+	ZXIC_UINT32 lif0_port_rdy_cfg_l;
+} DPP_ETM_OLIF_LIF0_PORT_RDY_CFG_L_T;
+
+typedef struct dpp_etm_olif_lif0_link_rdy_mask_cfg_t {
+	ZXIC_UINT32 lif0_link_rdy_mask;
+	ZXIC_UINT32 lif0_link_rdy_cfg;
+} DPP_ETM_OLIF_LIF0_LINK_RDY_MASK_CFG_T;
+
+typedef struct dpp_etm_olif_tm_lif_stat_cfg_t {
+	ZXIC_UINT32 all_or_by_port;
+	ZXIC_UINT32 i_or_e_sel;
+	ZXIC_UINT32 port_or_dest_id_sel;
+	ZXIC_UINT32 port_dest_id;
+} DPP_ETM_OLIF_TM_LIF_STAT_CFG_T;
+
+typedef struct dpp_etm_olif_tm_lif_sop_stat_t {
+	ZXIC_UINT32 tm_lif_sop_stat;
+} DPP_ETM_OLIF_TM_LIF_SOP_STAT_T;
+
+typedef struct dpp_etm_olif_tm_lif_eop_stat_t {
+	ZXIC_UINT32 tm_lif_eop_stat;
+} DPP_ETM_OLIF_TM_LIF_EOP_STAT_T;
+
+typedef struct dpp_etm_olif_tm_lif_vld_stat_t {
+	ZXIC_UINT32 tm_lif_vld_stat;
+} DPP_ETM_OLIF_TM_LIF_VLD_STAT_T;
+
+typedef struct dpp_etm_cgavd_prog_full_assert_cfg_t {
+	ZXIC_UINT32 prog_full_assert_cfg;
+	ZXIC_UINT32 prog_full_negate_cfg;
+} DPP_ETM_CGAVD_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_etm_cgavd_cgavd_int_t {
+	ZXIC_UINT32 cgavd_int;
+} DPP_ETM_CGAVD_CGAVD_INT_T;
+
+typedef struct dpp_etm_cgavd_cgavd_ram_err_t {
+	ZXIC_UINT32 flow_qnum_intb;
+	ZXIC_UINT32 flow_qnum_inta;
+	ZXIC_UINT32 pp_qlen_inta;
+	ZXIC_UINT32 pp_qlen_intb;
+	ZXIC_UINT32 pp_tdth_int;
+	ZXIC_UINT32 flow_tdth_inta;
+	ZXIC_UINT32 flow_tdth_intb;
+	ZXIC_UINT32 flow_qlen_inta;
+	ZXIC_UINT32 flow_qlen_intb;
+	ZXIC_UINT32 qmu_cgavd_fifo_uv_int;
+	ZXIC_UINT32 qmu_cgavd_fifo_ov_int;
+	ZXIC_UINT32 pds_deal_fifo_ov_int;
+	ZXIC_UINT32 pds_deal_fifo_uv_int;
+} DPP_ETM_CGAVD_CGAVD_RAM_ERR_T;
+
+typedef struct dpp_etm_cgavd_cgavd_int_mask_t {
+	ZXIC_UINT32 cgavd_int_mask;
+} DPP_ETM_CGAVD_CGAVD_INT_MASK_T;
+
+typedef struct dpp_etm_cgavd_cgavd_ram_err_int_mask_t {
+	ZXIC_UINT32 flow_qnum_inta_mask;
+	ZXIC_UINT32 flow_qnum_intb_mask;
+	ZXIC_UINT32 pp_qlen_inta_mask;
+	ZXIC_UINT32 pp_qlen_intb_mask;
+	ZXIC_UINT32 pp_tdth_int_mask;
+	ZXIC_UINT32 flow_tdth_inta_mask;
+	ZXIC_UINT32 flow_tdth_intb_mask;
+	ZXIC_UINT32 flow_qlen_inta_mask;
+	ZXIC_UINT32 flow_qlen_intb_mask;
+	ZXIC_UINT32 qmu_cgavd_fifo_uv_int_mask;
+	ZXIC_UINT32 qmu_cgavd_fifo_ov_int_mask;
+	ZXIC_UINT32 pds_deal_fifo_ov_int_mask;
+	ZXIC_UINT32 pds_deal_fifo_uv_int_mask;
+} DPP_ETM_CGAVD_CGAVD_RAM_ERR_INT_MASK_T;
+
+typedef struct dpp_etm_cgavd_cfgmt_byte_mode_t {
+	ZXIC_UINT32 cfgmt_byte_mode;
+} DPP_ETM_CGAVD_CFGMT_BYTE_MODE_T;
+
+typedef struct dpp_etm_cgavd_avg_qlen_return_zero_en_t {
+	ZXIC_UINT32 avg_qlen_return_zero_en;
+} DPP_ETM_CGAVD_AVG_QLEN_RETURN_ZERO_EN_T;
+
+typedef struct dpp_etm_cgavd_flow_wred_q_len_th_t {
+	ZXIC_UINT32 flow_wred_q_len_th;
+} DPP_ETM_CGAVD_FLOW_WRED_Q_LEN_TH_T;
+
+typedef struct dpp_etm_cgavd_flow_wq_t {
+	ZXIC_UINT32 wq_flow;
+} DPP_ETM_CGAVD_FLOW_WQ_T;
+
+typedef struct dpp_etm_cgavd_flow_wred_max_th_t {
+	ZXIC_UINT32 flow_wred_max_th;
+} DPP_ETM_CGAVD_FLOW_WRED_MAX_TH_T;
+
+typedef struct dpp_etm_cgavd_flow_wred_min_th_t {
+	ZXIC_UINT32 flow_wred_min_th;
+} DPP_ETM_CGAVD_FLOW_WRED_MIN_TH_T;
+
+typedef struct dpp_etm_cgavd_flow_wred_cfg_para_t {
+	ZXIC_UINT32 flow_wred_cfg_para;
+} DPP_ETM_CGAVD_FLOW_WRED_CFG_PARA_T;
+
+typedef struct dpp_etm_cgavd_pp_avg_q_len_t {
+	ZXIC_UINT32 pp_avg_q_len;
+} DPP_ETM_CGAVD_PP_AVG_Q_LEN_T;
+
+typedef struct dpp_etm_cgavd_pp_td_th_t {
+	ZXIC_UINT32 pp_td_th;
+} DPP_ETM_CGAVD_PP_TD_TH_T;
+
+typedef struct dpp_etm_cgavd_pp_ca_mtd_t {
+	ZXIC_UINT32 pp_ca_mtd;
+} DPP_ETM_CGAVD_PP_CA_MTD_T;
+
+typedef struct dpp_etm_cgavd_pp_wred_grp_th_en_t {
+	ZXIC_UINT32 pp_wred_grp;
+	ZXIC_UINT32 pp_wred_grp_th_en;
+} DPP_ETM_CGAVD_PP_WRED_GRP_TH_EN_T;
+
+typedef struct dpp_etm_cgavd_pp_wred_q_len_th_t {
+	ZXIC_UINT32 pp_wred_q_len_th;
+} DPP_ETM_CGAVD_PP_WRED_Q_LEN_TH_T;
+
+typedef struct dpp_etm_cgavd_pp_wq_t {
+	ZXIC_UINT32 wq_pp;
+} DPP_ETM_CGAVD_PP_WQ_T;
+
+typedef struct dpp_etm_cgavd_pp_wred_max_th_t {
+	ZXIC_UINT32 pp_wred_max_th;
+} DPP_ETM_CGAVD_PP_WRED_MAX_TH_T;
+
+typedef struct dpp_etm_cgavd_pp_wred_min_th_t {
+	ZXIC_UINT32 pp_wred_min_th;
+} DPP_ETM_CGAVD_PP_WRED_MIN_TH_T;
+
+typedef struct dpp_etm_cgavd_pp_cfg_para_t {
+	ZXIC_UINT32 pp_cfg_para;
+} DPP_ETM_CGAVD_PP_CFG_PARA_T;
+
+typedef struct dpp_etm_cgavd_sys_avg_q_len_t {
+	ZXIC_UINT32 sys_avg_q_len;
+} DPP_ETM_CGAVD_SYS_AVG_Q_LEN_T;
+
+typedef struct dpp_etm_cgavd_sys_td_th_t {
+	ZXIC_UINT32 sys_td_th;
+} DPP_ETM_CGAVD_SYS_TD_TH_T;
+
+typedef struct dpp_etm_cgavd_sys_cgavd_metd_t {
+	ZXIC_UINT32 sys_cgavd_metd;
+} DPP_ETM_CGAVD_SYS_CGAVD_METD_T;
+
+typedef struct dpp_etm_cgavd_sys_cfg_q_grp_para_t {
+	ZXIC_UINT32 gred_q_len_th_sys;
+} DPP_ETM_CGAVD_SYS_CFG_Q_GRP_PARA_T;
+
+typedef struct dpp_etm_cgavd_sys_wq_t {
+	ZXIC_UINT32 wq_sys;
+} DPP_ETM_CGAVD_SYS_WQ_T;
+
+typedef struct dpp_etm_cgavd_gred_max_th_t {
+	ZXIC_UINT32 gred_max_th;
+} DPP_ETM_CGAVD_GRED_MAX_TH_T;
+
+typedef struct dpp_etm_cgavd_gred_mid_th_t {
+	ZXIC_UINT32 gred_mid_th;
+} DPP_ETM_CGAVD_GRED_MID_TH_T;
+
+typedef struct dpp_etm_cgavd_gred_min_th_t {
+	ZXIC_UINT32 gred_min_th;
+} DPP_ETM_CGAVD_GRED_MIN_TH_T;
 
+typedef struct dpp_etm_cgavd_gred_cfg_para0_t {
+	ZXIC_UINT32 gred_cfg_para0;
+} DPP_ETM_CGAVD_GRED_CFG_PARA0_T;
+
+typedef struct dpp_etm_cgavd_gred_cfg_para1_t {
+	ZXIC_UINT32 gred_cfg_para1;
+} DPP_ETM_CGAVD_GRED_CFG_PARA1_T;
+
+typedef struct dpp_etm_cgavd_gred_cfg_para2_t {
+	ZXIC_UINT32 gred_cfg_para2;
+} DPP_ETM_CGAVD_GRED_CFG_PARA2_T;
+
+typedef struct dpp_etm_cgavd_sys_window_th_h_t {
+	ZXIC_UINT32 sys_window_th_h;
+} DPP_ETM_CGAVD_SYS_WINDOW_TH_H_T;
+
+typedef struct dpp_etm_cgavd_sys_window_th_l_t {
+	ZXIC_UINT32 sys_window_th_l;
+} DPP_ETM_CGAVD_SYS_WINDOW_TH_L_T;
+
+typedef struct dpp_etm_cgavd_amplify_gene0_t {
+	ZXIC_UINT32 amplify_gene0;
+} DPP_ETM_CGAVD_AMPLIFY_GENE0_T;
+
+typedef struct dpp_etm_cgavd_amplify_gene1_t {
+	ZXIC_UINT32 amplify_gene1;
+} DPP_ETM_CGAVD_AMPLIFY_GENE1_T;
+
+typedef struct dpp_etm_cgavd_amplify_gene2_t {
+	ZXIC_UINT32 amplify_gene2;
+} DPP_ETM_CGAVD_AMPLIFY_GENE2_T;
+
+typedef struct dpp_etm_cgavd_amplify_gene3_t {
+	ZXIC_UINT32 amplify_gene3;
+} DPP_ETM_CGAVD_AMPLIFY_GENE3_T;
+
+typedef struct dpp_etm_cgavd_amplify_gene4_t {
+	ZXIC_UINT32 amplify_gene4;
+} DPP_ETM_CGAVD_AMPLIFY_GENE4_T;
+
+typedef struct dpp_etm_cgavd_amplify_gene5_t {
+	ZXIC_UINT32 amplify_gene5;
+} DPP_ETM_CGAVD_AMPLIFY_GENE5_T;
+
+typedef struct dpp_etm_cgavd_amplify_gene6_t {
+	ZXIC_UINT32 amplify_gene6;
+} DPP_ETM_CGAVD_AMPLIFY_GENE6_T;
+
+typedef struct dpp_etm_cgavd_amplify_gene7_t {
+	ZXIC_UINT32 amplify_gene7;
+} DPP_ETM_CGAVD_AMPLIFY_GENE7_T;
+
+typedef struct dpp_etm_cgavd_amplify_gene8_t {
+	ZXIC_UINT32 amplify_gene8;
+} DPP_ETM_CGAVD_AMPLIFY_GENE8_T;
+
+typedef struct dpp_etm_cgavd_amplify_gene9_t {
+	ZXIC_UINT32 amplify_gene9;
+} DPP_ETM_CGAVD_AMPLIFY_GENE9_T;
+
+typedef struct dpp_etm_cgavd_amplify_gene10_t {
+	ZXIC_UINT32 amplify_gene10;
+} DPP_ETM_CGAVD_AMPLIFY_GENE10_T;
+
+typedef struct dpp_etm_cgavd_amplify_gene11_t {
+	ZXIC_UINT32 amplify_gene11;
+} DPP_ETM_CGAVD_AMPLIFY_GENE11_T;
+
+typedef struct dpp_etm_cgavd_amplify_gene12_t {
+	ZXIC_UINT32 amplify_gene12;
+} DPP_ETM_CGAVD_AMPLIFY_GENE12_T;
+
+typedef struct dpp_etm_cgavd_amplify_gene13_t {
+	ZXIC_UINT32 amplify_gene13;
+} DPP_ETM_CGAVD_AMPLIFY_GENE13_T;
+
+typedef struct dpp_etm_cgavd_amplify_gene14_t {
+	ZXIC_UINT32 amplify_gene14;
+} DPP_ETM_CGAVD_AMPLIFY_GENE14_T;
+
+typedef struct dpp_etm_cgavd_amplify_gene15_t {
+	ZXIC_UINT32 amplify_gene15;
+} DPP_ETM_CGAVD_AMPLIFY_GENE15_T;
+
+typedef struct dpp_etm_cgavd_equal_pkt_len_en_t {
+	ZXIC_UINT32 equal_pkt_len_en;
+} DPP_ETM_CGAVD_EQUAL_PKT_LEN_EN_T;
+
+typedef struct dpp_etm_cgavd_equal_pkt_len_th0_t {
+	ZXIC_UINT32 equal_pkt_len_th0;
+} DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH0_T;
+
+typedef struct dpp_etm_cgavd_equal_pkt_len_th1_t {
+	ZXIC_UINT32 equal_pkt_len_th1;
+} DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH1_T;
+
+typedef struct dpp_etm_cgavd_equal_pkt_len_th2_t {
+	ZXIC_UINT32 equal_pkt_len_th2;
+} DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH2_T;
+
+typedef struct dpp_etm_cgavd_equal_pkt_len_th3_t {
+	ZXIC_UINT32 equal_pkt_len_th3;
+} DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH3_T;
+
+typedef struct dpp_etm_cgavd_equal_pkt_len_th4_t {
+	ZXIC_UINT32 equal_pkt_len_th4;
+} DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH4_T;
+
+typedef struct dpp_etm_cgavd_equal_pkt_len_th5_t {
+	ZXIC_UINT32 equal_pkt_len_th5;
+} DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH5_T;
+
+typedef struct dpp_etm_cgavd_equal_pkt_len_th6_t {
+	ZXIC_UINT32 equal_pkt_len_th6;
+} DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH6_T;
+
+typedef struct dpp_etm_cgavd_equal_pkt_len0_t {
+	ZXIC_UINT32 equal_pkt_len0;
+} DPP_ETM_CGAVD_EQUAL_PKT_LEN0_T;
+
+typedef struct dpp_etm_cgavd_equal_pkt_len1_t {
+	ZXIC_UINT32 equal_pkt_len1;
+} DPP_ETM_CGAVD_EQUAL_PKT_LEN1_T;
+
+typedef struct dpp_etm_cgavd_equal_pkt_len2_t {
+	ZXIC_UINT32 equal_pkt_len2;
+} DPP_ETM_CGAVD_EQUAL_PKT_LEN2_T;
+
+typedef struct dpp_etm_cgavd_equal_pkt_len3_t {
+	ZXIC_UINT32 equal_pkt_len3;
+} DPP_ETM_CGAVD_EQUAL_PKT_LEN3_T;
+
+typedef struct dpp_etm_cgavd_equal_pkt_len4_t {
+	ZXIC_UINT32 equal_pkt_len4;
+} DPP_ETM_CGAVD_EQUAL_PKT_LEN4_T;
+
+typedef struct dpp_etm_cgavd_equal_pkt_len5_t {
+	ZXIC_UINT32 equal_pkt_len5;
+} DPP_ETM_CGAVD_EQUAL_PKT_LEN5_T;
+
+typedef struct dpp_etm_cgavd_equal_pkt_len6_t {
+	ZXIC_UINT32 equal_pkt_len6;
+} DPP_ETM_CGAVD_EQUAL_PKT_LEN6_T;
+
+typedef struct dpp_etm_cgavd_equal_pkt_len7_t {
+	ZXIC_UINT32 equal_pkt_len7;
+} DPP_ETM_CGAVD_EQUAL_PKT_LEN7_T;
+
+typedef struct dpp_etm_cgavd_flow_cpu_set_avg_len_t {
+	ZXIC_UINT32 flow_cpu_set_avg_len;
+} DPP_ETM_CGAVD_FLOW_CPU_SET_AVG_LEN_T;
+
+typedef struct dpp_etm_cgavd_flow_cpu_set_q_len_t {
+	ZXIC_UINT32 flow_cpu_set_q_len;
+} DPP_ETM_CGAVD_FLOW_CPU_SET_Q_LEN_T;
+
+typedef struct dpp_etm_cgavd_pp_cpu_set_avg_q_len_t {
+	ZXIC_UINT32 pp_cpu_set_avg_q_len;
+} DPP_ETM_CGAVD_PP_CPU_SET_AVG_Q_LEN_T;
+
+typedef struct dpp_etm_cgavd_pp_cpu_set_q_len_t {
+	ZXIC_UINT32 pp_cpu_set_q_len;
+} DPP_ETM_CGAVD_PP_CPU_SET_Q_LEN_T;
+
+typedef struct dpp_etm_cgavd_sys_cpu_set_avg_len_t {
+	ZXIC_UINT32 sys_cpu_set_avg_len;
+} DPP_ETM_CGAVD_SYS_CPU_SET_AVG_LEN_T;
+
+typedef struct dpp_etm_cgavd_sys_cpu_set_q_len_t {
+	ZXIC_UINT32 sys_cpu_set_q_len;
+} DPP_ETM_CGAVD_SYS_CPU_SET_Q_LEN_T;
+
+typedef struct dpp_etm_cgavd_pke_len_calc_sign_t {
+	ZXIC_UINT32 pke_len_calc_sign;
+} DPP_ETM_CGAVD_PKE_LEN_CALC_SIGN_T;
+
+typedef struct dpp_etm_cgavd_rd_cpu_or_ram_t {
+	ZXIC_UINT32 cpu_sel_sys_q_len_en;
+	ZXIC_UINT32 cpu_sel_sys_avg_q_len_en;
+	ZXIC_UINT32 cpu_sel_pp_q_len_en;
+	ZXIC_UINT32 cpu_sel_pp_avg_q_len_en;
+	ZXIC_UINT32 cpu_sel_flow_q_len_en;
+	ZXIC_UINT32 cpu_sel_flow_avg_q_len_en;
+} DPP_ETM_CGAVD_RD_CPU_OR_RAM_T;
+
+typedef struct dpp_etm_cgavd_q_len_update_disable_t {
+	ZXIC_UINT32 q_len_sys_update_en;
+	ZXIC_UINT32 q_len_pp_update_en;
+	ZXIC_UINT32 q_len_flow_update_en;
+} DPP_ETM_CGAVD_Q_LEN_UPDATE_DISABLE_T;
+
+typedef struct dpp_etm_cgavd_cgavd_dp_sel_t {
+	ZXIC_UINT32 flow_dp_sel_high;
+	ZXIC_UINT32 flow_dp_sel_mid;
+	ZXIC_UINT32 flow_dp_sel_low;
+	ZXIC_UINT32 pp_dp_sel_high;
+	ZXIC_UINT32 pp_dp_sel_mid;
+	ZXIC_UINT32 pp_dp_sel_low;
+	ZXIC_UINT32 sys_dp_sel_high;
+	ZXIC_UINT32 sys_dp_sel_mid;
+	ZXIC_UINT32 sys_dp_sel_low;
+} DPP_ETM_CGAVD_CGAVD_DP_SEL_T;
+
+typedef struct dpp_etm_cgavd_cgavd_sub_en_t {
+	ZXIC_UINT32 cgavd_sa_sub_en;
+	ZXIC_UINT32 cgavd_sys_sub_en;
+	ZXIC_UINT32 cgavd_pp_sub_en;
+	ZXIC_UINT32 cgavd_flow_sub_en;
+} DPP_ETM_CGAVD_CGAVD_SUB_EN_T;
+
+typedef struct dpp_etm_cgavd_default_start_queue_t {
+	ZXIC_UINT32 default_start_queue;
+} DPP_ETM_CGAVD_DEFAULT_START_QUEUE_T;
+
+typedef struct dpp_etm_cgavd_default_finish_queue_t {
+	ZXIC_UINT32 default_finish_queue;
+} DPP_ETM_CGAVD_DEFAULT_FINISH_QUEUE_T;
+
+typedef struct dpp_etm_cgavd_protocol_start_queue_t {
+	ZXIC_UINT32 protocol_start_queue;
+} DPP_ETM_CGAVD_PROTOCOL_START_QUEUE_T;
+
+typedef struct dpp_etm_cgavd_protocol_finish_queue_t {
+	ZXIC_UINT32 protocol_finish_queue;
+} DPP_ETM_CGAVD_PROTOCOL_FINISH_QUEUE_T;
+
+typedef struct dpp_etm_cgavd_uniform_td_th_t {
+	ZXIC_UINT32 uniform_td_th;
+} DPP_ETM_CGAVD_UNIFORM_TD_TH_T;
+
+typedef struct dpp_etm_cgavd_uniform_td_th_en_t {
+	ZXIC_UINT32 uniform_td_th_en;
+} DPP_ETM_CGAVD_UNIFORM_TD_TH_EN_T;
+
+typedef struct dpp_etm_cgavd_cgavd_cfg_fc_t {
+	ZXIC_UINT32 cgavd_cfg_fc;
+} DPP_ETM_CGAVD_CGAVD_CFG_FC_T;
+
+typedef struct dpp_etm_cgavd_cgavd_cfg_no_fc_t {
+	ZXIC_UINT32 cgavd_cfg_no_fc;
+} DPP_ETM_CGAVD_CGAVD_CFG_NO_FC_T;
+
+typedef struct dpp_etm_cgavd_cgavd_force_imem_omem_t {
+	ZXIC_UINT32 imem_omem_force_en;
+	ZXIC_UINT32 choose_imem_omem;
+} DPP_ETM_CGAVD_CGAVD_FORCE_IMEM_OMEM_T;
+
+typedef struct dpp_etm_cgavd_cgavd_sys_q_len_l_t {
+	ZXIC_UINT32 cgavd_sys_q_len_l;
+} DPP_ETM_CGAVD_CGAVD_SYS_Q_LEN_L_T;
+
+typedef struct dpp_etm_cgavd_default_queue_en_t {
+	ZXIC_UINT32 default_queue_en;
+} DPP_ETM_CGAVD_DEFAULT_QUEUE_EN_T;
+
+typedef struct dpp_etm_cgavd_protocol_queue_en_t {
+	ZXIC_UINT32 protocol_queue_en;
+} DPP_ETM_CGAVD_PROTOCOL_QUEUE_EN_T;
+
+typedef struct dpp_etm_cgavd_cfg_tc_flowid_dat_t {
+	ZXIC_UINT32 cfg_tc_flowid_dat;
+} DPP_ETM_CGAVD_CFG_TC_FLOWID_DAT_T;
+
+typedef struct dpp_etm_cgavd_flow_td_th_t {
+	ZXIC_UINT32 flow_td_th;
+} DPP_ETM_CGAVD_FLOW_TD_TH_T;
+
+typedef struct dpp_etm_cgavd_flow_ca_mtd_t {
+	ZXIC_UINT32 flow_ca_mtd;
+} DPP_ETM_CGAVD_FLOW_CA_MTD_T;
+
+typedef struct dpp_etm_cgavd_flow_dynamic_th_en_t {
+	ZXIC_UINT32 flow_dynamic_th_en;
+} DPP_ETM_CGAVD_FLOW_DYNAMIC_TH_EN_T;
+
+typedef struct dpp_etm_cgavd_pp_num_t {
+	ZXIC_UINT32 pp_num;
+} DPP_ETM_CGAVD_PP_NUM_T;
+
+typedef struct dpp_etm_cgavd_flow_q_len_t {
+	ZXIC_UINT32 flow_q_len;
+} DPP_ETM_CGAVD_FLOW_Q_LEN_T;
+
+typedef struct dpp_etm_cgavd_flow_wred_grp_t {
+	ZXIC_UINT32 flow_wred_grp;
+} DPP_ETM_CGAVD_FLOW_WRED_GRP_T;
+
+typedef struct dpp_etm_cgavd_flow_avg_q_len_t {
+	ZXIC_UINT32 flow_avg_q_len;
+} DPP_ETM_CGAVD_FLOW_AVG_Q_LEN_T;
+
+typedef struct dpp_etm_cgavd_qos_sign_t {
+	ZXIC_UINT32 qos_sign_flow_cfg_din;
+} DPP_ETM_CGAVD_QOS_SIGN_T;
+
+typedef struct dpp_etm_cgavd_q_pri_t {
+	ZXIC_UINT32 qpri_flow_cfg_din;
+} DPP_ETM_CGAVD_Q_PRI_T;
+
+typedef struct dpp_etm_cgavd_odma_tm_itmd_rd_low_t {
+	ZXIC_UINT32 odma_tm_itmd_low;
+} DPP_ETM_CGAVD_ODMA_TM_ITMD_RD_LOW_T;
+
+typedef struct dpp_etm_cgavd_odma_tm_itmd_rd_mid_t {
+	ZXIC_UINT32 odma_tm_itmd_mid;
+} DPP_ETM_CGAVD_ODMA_TM_ITMD_RD_MID_T;
+
+typedef struct dpp_etm_cgavd_odma_tm_itmd_rd_high_t {
+	ZXIC_UINT32 odma_tm_itmd_high;
+} DPP_ETM_CGAVD_ODMA_TM_ITMD_RD_HIGH_T;
+
+typedef struct dpp_etm_cgavd_cgavd_stat_pkt_len_t {
+	ZXIC_UINT32 expect_deq_pkt_len;
+	ZXIC_UINT32 expect_enq_pkt_len;
+} DPP_ETM_CGAVD_CGAVD_STAT_PKT_LEN_T;
+
+typedef struct dpp_etm_cgavd_cgavd_stat_qnum_t {
+	ZXIC_UINT32 cgavd_unexcept_qnum;
+	ZXIC_UINT32 cgavd_except_qnum;
+} DPP_ETM_CGAVD_CGAVD_STAT_QNUM_T;
+
+typedef struct dpp_etm_cgavd_cgavd_stat_dp_t {
+	ZXIC_UINT32 cgavd_stat_dp;
+} DPP_ETM_CGAVD_CGAVD_STAT_DP_T;
+
+typedef struct dpp_etm_cgavd_flow_num0_t {
+	ZXIC_UINT32 flow_num0;
+} DPP_ETM_CGAVD_FLOW_NUM0_T;
+
+typedef struct dpp_etm_cgavd_flow_num1_t {
+	ZXIC_UINT32 flow_num1;
+} DPP_ETM_CGAVD_FLOW_NUM1_T;
+
+typedef struct dpp_etm_cgavd_flow_num2_t {
+	ZXIC_UINT32 flow_num2;
+} DPP_ETM_CGAVD_FLOW_NUM2_T;
+
+typedef struct dpp_etm_cgavd_flow_num3_t {
+	ZXIC_UINT32 flow_num3;
+} DPP_ETM_CGAVD_FLOW_NUM3_T;
+
+typedef struct dpp_etm_cgavd_flow_num4_t {
+	ZXIC_UINT32 flow_num4;
+} DPP_ETM_CGAVD_FLOW_NUM4_T;
+
+typedef struct dpp_etm_cgavd_flow0_imem_cnt_t {
+	ZXIC_UINT32 flow0_imem_cnt;
+} DPP_ETM_CGAVD_FLOW0_IMEM_CNT_T;
+
+typedef struct dpp_etm_cgavd_flow1_imem_cnt_t {
+	ZXIC_UINT32 flow1_imem_cnt;
+} DPP_ETM_CGAVD_FLOW1_IMEM_CNT_T;
+
+typedef struct dpp_etm_cgavd_flow2_imem_cnt_t {
+	ZXIC_UINT32 flow2_imem_cnt;
+} DPP_ETM_CGAVD_FLOW2_IMEM_CNT_T;
+
+typedef struct dpp_etm_cgavd_flow3_imem_cnt_t {
+	ZXIC_UINT32 flow3_imem_cnt;
+} DPP_ETM_CGAVD_FLOW3_IMEM_CNT_T;
+
+typedef struct dpp_etm_cgavd_flow4_imem_cnt_t {
+	ZXIC_UINT32 flow4_imem_cnt;
+} DPP_ETM_CGAVD_FLOW4_IMEM_CNT_T;
+
+typedef struct dpp_etm_cgavd_flow0_drop_cnt_t {
+	ZXIC_UINT32 flow0_drop_cnt;
+} DPP_ETM_CGAVD_FLOW0_DROP_CNT_T;
+
+typedef struct dpp_etm_cgavd_flow1_drop_cnt_t {
+	ZXIC_UINT32 flow1_drop_cnt;
+} DPP_ETM_CGAVD_FLOW1_DROP_CNT_T;
+
+typedef struct dpp_etm_cgavd_flow2_drop_cnt_t {
+	ZXIC_UINT32 flow2_drop_cnt;
+} DPP_ETM_CGAVD_FLOW2_DROP_CNT_T;
+
+typedef struct dpp_etm_cgavd_flow3_drop_cnt_t {
+	ZXIC_UINT32 flow3_drop_cnt;
+} DPP_ETM_CGAVD_FLOW3_DROP_CNT_T;
+
+typedef struct dpp_etm_cgavd_flow4_drop_cnt_t {
+	ZXIC_UINT32 flow4_drop_cnt;
+} DPP_ETM_CGAVD_FLOW4_DROP_CNT_T;
+
+typedef struct dpp_etm_cgavd_fc_count_mode_t {
+	ZXIC_UINT32 fc_count_mode;
+} DPP_ETM_CGAVD_FC_COUNT_MODE_T;
+
+typedef struct dpp_etm_cgavd_qmu_cgavd_fc_num_t {
+	ZXIC_UINT32 qmu_cgavd_fc_state;
+	ZXIC_UINT32 qmu_cgavd_fc_num;
+} DPP_ETM_CGAVD_QMU_CGAVD_FC_NUM_T;
+
+typedef struct dpp_etm_cgavd_cgavd_odma_fc_num_t {
+	ZXIC_UINT32 cgavd_lif_fc_state;
+	ZXIC_UINT32 cgavd_lif_fc_num;
+} DPP_ETM_CGAVD_CGAVD_ODMA_FC_NUM_T;
+
+typedef struct dpp_etm_cgavd_cfg_offset_t {
+	ZXIC_UINT32 cfg_offset;
+} DPP_ETM_CGAVD_CFG_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_tmmu_init_done_t {
+	ZXIC_UINT32 tmmu_init_done;
+} DPP_ETM_TMMU_TMMU_INIT_DONE_T;
+
+typedef struct dpp_etm_tmmu_tmmu_int_mask_1_t {
+	ZXIC_UINT32 imem_enq_rd_fifo_full_mask;
+	ZXIC_UINT32 imem_enq_rd_fifo_overflow_mask;
+	ZXIC_UINT32 imem_enq_rd_fifo_underflow_mask;
+	ZXIC_UINT32 imem_enq_drop_fifo_full_mask;
+	ZXIC_UINT32 imem_enq_drop_fifo_overflow_mask;
+	ZXIC_UINT32 imem_enq_drop_fifo_underflow_mask;
+	ZXIC_UINT32 imem_deq_rd_fifo_full_mask;
+	ZXIC_UINT32 imem_deq_rd_fifo_overflow_mask;
+	ZXIC_UINT32 imem_deq_rd_fifo_underflow_mask;
+	ZXIC_UINT32 imem_deq_drop_fifo_full_mask;
+	ZXIC_UINT32 imem_deq_drop_fifo_overflow_mask;
+	ZXIC_UINT32 imem_deq_drop_fifo_underflow_mask;
+	ZXIC_UINT32 dma_data_fifo_full_mask;
+	ZXIC_UINT32 dma_data_fifo_overflow_mask;
+	ZXIC_UINT32 dma_data_fifo_underflow_mask;
+	ZXIC_UINT32 wr_cmd_fifo_full_mask;
+	ZXIC_UINT32 wr_cmd_fifo_overflow_mask;
+	ZXIC_UINT32 wr_cmd_fifo_underflow_mask;
+	ZXIC_UINT32 cached_pd_fifo_full_mask;
+	ZXIC_UINT32 cached_pd_fifo_overflow_mask;
+	ZXIC_UINT32 cached_pd_fifo_underflow_mask;
+	ZXIC_UINT32 emem_pd_fifo_full_mask;
+	ZXIC_UINT32 emem_pd_fifo_overflow_mask;
+	ZXIC_UINT32 emem_pd_fifo_underflow_mask;
+	ZXIC_UINT32 pd_order_fifo_full_mask;
+	ZXIC_UINT32 pd_order_fifo_overflow_mask;
+	ZXIC_UINT32 pd_order_fifo_underflow_mask;
+} DPP_ETM_TMMU_TMMU_INT_MASK_1_T;
+
+typedef struct dpp_etm_tmmu_tmmu_int_mask_2_t {
+	ZXIC_UINT32 dma_data_fifo_parity_err_mask;
+	ZXIC_UINT32 imem_enq_rd_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 imem_enq_rd_fifo_ecc_double_err_mask;
+	ZXIC_UINT32 imem_enq_drop_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 imem_enq_drop_fifo_ecc_double_err_mask;
+	ZXIC_UINT32 imem_deq_rd_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 imem_deq_rd_fifo_ecc_double_err_mask;
+	ZXIC_UINT32 imem_deq_drop_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 imem_deq_drop_fifo_ecc_double_err_mask;
+	ZXIC_UINT32 wr_cmd_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 wr_cmd_fifo_ecc_double_err_mask;
+	ZXIC_UINT32 pd_cache_ram_ecc_single_err_mask;
+	ZXIC_UINT32 pd_cache_ram_ecc_double_err_mask;
+	ZXIC_UINT32 cached_pd_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 cached_pd_fifo_ecc_double_err_mask;
+	ZXIC_UINT32 emem_pd_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 emem_pd_fifo_ecc_double_err_mask;
+} DPP_ETM_TMMU_TMMU_INT_MASK_2_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_tm_pure_imem_en_t {
+	ZXIC_UINT32 cfgmt_tm_pure_imem_en;
+} DPP_ETM_TMMU_CFGMT_TM_PURE_IMEM_EN_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_force_ddr_rdy_cfg_t {
+	ZXIC_UINT32 cfgmt_force_ddr_rdy_cfg;
+} DPP_ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFG_T;
+
+typedef struct dpp_etm_tmmu_pd_order_fifo_aful_th_t {
+	ZXIC_UINT32 pd_order_fifo_aful_th;
+} DPP_ETM_TMMU_PD_ORDER_FIFO_AFUL_TH_T;
+
+typedef struct dpp_etm_tmmu_cached_pd_fifo_aful_th_t {
+	ZXIC_UINT32 cached_pd_fifo_aful_th;
+} DPP_ETM_TMMU_CACHED_PD_FIFO_AFUL_TH_T;
+
+typedef struct dpp_etm_tmmu_wr_cmd_fifo_aful_th_t {
+	ZXIC_UINT32 wr_cmd_fifo_aful_th;
+} DPP_ETM_TMMU_WR_CMD_FIFO_AFUL_TH_T;
+
+typedef struct dpp_etm_tmmu_imem_enq_rd_fifo_aful_th_t {
+	ZXIC_UINT32 imem_enq_rd_fifo_aful_th;
+} DPP_ETM_TMMU_IMEM_ENQ_RD_FIFO_AFUL_TH_T;
+
+typedef struct dpp_etm_tmmu_imem_enq_drop_fifo_aful_th_t {
+	ZXIC_UINT32 imem_enq_drop_fifo_aful_th;
+} DPP_ETM_TMMU_IMEM_ENQ_DROP_FIFO_AFUL_TH_T;
+
+typedef struct dpp_etm_tmmu_imem_deq_drop_fifo_aful_th_t {
+	ZXIC_UINT32 imem_deq_drop_fifo_aful_th;
+} DPP_ETM_TMMU_IMEM_DEQ_DROP_FIFO_AFUL_TH_T;
+
+typedef struct dpp_etm_tmmu_imem_deq_rd_fifo_aful_th_t {
+	ZXIC_UINT32 imem_deq_rd_fifo_aful_th;
+} DPP_ETM_TMMU_IMEM_DEQ_RD_FIFO_AFUL_TH_T;
+
+typedef struct dpp_etm_tmmu_tmmu_states_1_t {
+	ZXIC_UINT32 imem_enq_rd_fifo_full;
+	ZXIC_UINT32 imem_enq_rd_fifo_overflow;
+	ZXIC_UINT32 imem_enq_rd_fifo_underflow;
+	ZXIC_UINT32 imem_enq_drop_fifo_full;
+	ZXIC_UINT32 imem_enq_drop_fifo_overflow;
+	ZXIC_UINT32 imem_enq_drop_fifo_underflow;
+	ZXIC_UINT32 imem_deq_rd_fifo_full;
+	ZXIC_UINT32 imem_deq_rd_fifo_overflow;
+	ZXIC_UINT32 imem_deq_rd_fifo_underflow;
+	ZXIC_UINT32 imem_deq_drop_fifo_full;
+	ZXIC_UINT32 imem_deq_drop_fifo_overflow;
+	ZXIC_UINT32 imem_deq_drop_fifo_underflow;
+	ZXIC_UINT32 dma_data_fifo_full;
+	ZXIC_UINT32 dma_data_fifo_overflow;
+	ZXIC_UINT32 dma_data_fifo_underflow;
+	ZXIC_UINT32 wr_cmd_fifo_full;
+	ZXIC_UINT32 wr_cmd_fifo_overflow;
+	ZXIC_UINT32 wr_cmd_fifo_underflow;
+	ZXIC_UINT32 cached_pd_fifo_full;
+	ZXIC_UINT32 cached_pd_fifo_overflow;
+	ZXIC_UINT32 cached_pd_fifo_underflow;
+	ZXIC_UINT32 emem_pd_fifo_full;
+	ZXIC_UINT32 emem_pd_fifo_overflow;
+	ZXIC_UINT32 emem_pd_fifo_underflow;
+	ZXIC_UINT32 pd_order_fifo_full;
+	ZXIC_UINT32 pd_order_fifo_overflow;
+	ZXIC_UINT32 pd_order_fifo_underflow;
+} DPP_ETM_TMMU_TMMU_STATES_1_T;
+
+typedef struct dpp_etm_tmmu_tmmu_states_2_t {
+	ZXIC_UINT32 dma_data_fifo_parity_err;
+	ZXIC_UINT32 imem_enq_rd_fifo_ecc_single_err;
+	ZXIC_UINT32 imem_enq_rd_fifo_ecc_double_err;
+	ZXIC_UINT32 imem_enq_drop_fifo_ecc_single_err;
+	ZXIC_UINT32 imem_enq_drop_fifo_ecc_double_err;
+	ZXIC_UINT32 imem_deq_rd_fifo_ecc_single_err;
+	ZXIC_UINT32 imem_deq_rd_fifo_ecc_double_err;
+	ZXIC_UINT32 imem_deq_drop_fifo_ecc_single_err;
+	ZXIC_UINT32 imem_deq_drop_fifo_ecc_double_err;
+	ZXIC_UINT32 wr_cmd_fifo_ecc_single_err;
+	ZXIC_UINT32 wr_cmd_fifo_ecc_double_err;
+	ZXIC_UINT32 pd_cache_ram_ecc_single_err;
+	ZXIC_UINT32 pd_cache_ram_ecc_double_err;
+	ZXIC_UINT32 cached_pd_fifo_ecc_single_err;
+	ZXIC_UINT32 cached_pd_fifo_ecc_double_err;
+	ZXIC_UINT32 emem_pd_fifo_ecc_single_err;
+	ZXIC_UINT32 emem_pd_fifo_ecc_double_err;
+} DPP_ETM_TMMU_TMMU_STATES_2_T;
+
+typedef struct dpp_etm_shap_shap_ind_cmd_t {
+	ZXIC_UINT32 rd;
+	ZXIC_UINT32 mem_id;
+	ZXIC_UINT32 addr;
+} DPP_ETM_SHAP_SHAP_IND_CMD_T;
+
+typedef struct dpp_etm_shap_shap_ind_sta_t {
+	ZXIC_UINT32 indirectaccessdone;
+} DPP_ETM_SHAP_SHAP_IND_STA_T;
+
+typedef struct dpp_etm_shap_shap_ind_data0_t {
+	ZXIC_UINT32 indirectdata0;
+} DPP_ETM_SHAP_SHAP_IND_DATA0_T;
+
+typedef struct dpp_etm_shap_shap_ind_data1_t {
+	ZXIC_UINT32 indirectdata1;
+} DPP_ETM_SHAP_SHAP_IND_DATA1_T;
+
+typedef struct dpp_etm_shap_full_threshold_t {
+	ZXIC_UINT32 full_threshold;
+} DPP_ETM_SHAP_FULL_THRESHOLD_T;
+
+typedef struct dpp_etm_shap_empty_threshold_t {
+	ZXIC_UINT32 empty_threshold;
+} DPP_ETM_SHAP_EMPTY_THRESHOLD_T;
+
+typedef struct dpp_etm_shap_shap_sta_init_cfg_t {
+	ZXIC_UINT32 sta_ram_init_done;
+	ZXIC_UINT32 sta_ram_init_en;
+} DPP_ETM_SHAP_SHAP_STA_INIT_CFG_T;
+
+typedef struct dpp_etm_shap_shap_cfg_init_cfg_t {
+	ZXIC_UINT32 cfg_ram_init_done;
+	ZXIC_UINT32 cfg_ram_init_en;
+} DPP_ETM_SHAP_SHAP_CFG_INIT_CFG_T;
+
+typedef struct dpp_etm_shap_token_mode_switch_t {
+	ZXIC_UINT32 token_mode_switch;
+} DPP_ETM_SHAP_TOKEN_MODE_SWITCH_T;
+
+typedef struct dpp_etm_shap_token_grain_t {
+	ZXIC_UINT32 token_grain;
+} DPP_ETM_SHAP_TOKEN_GRAIN_T;
+
+typedef struct dpp_etm_shap_crd_grain_t {
+	ZXIC_UINT32 crd_grain;
+} DPP_ETM_SHAP_CRD_GRAIN_T;
+
+typedef struct dpp_etm_shap_shap_stat_ctrl_t {
+	ZXIC_UINT32 shap_stat_ctrl;
+} DPP_ETM_SHAP_SHAP_STAT_CTRL_T;
+
+typedef struct dpp_etm_shap_token_stat_id_t {
+	ZXIC_UINT32 token_stat_id;
+} DPP_ETM_SHAP_TOKEN_STAT_ID_T;
+
+typedef struct dpp_etm_shap_token_stat_t {
+	ZXIC_UINT32 token_stat;
+} DPP_ETM_SHAP_TOKEN_STAT_T;
+
+typedef struct dpp_etm_shap_shap_stat_clk_cnt_t {
+	ZXIC_UINT32 shap_stat_clk_cnt;
+} DPP_ETM_SHAP_SHAP_STAT_CLK_CNT_T;
+
+typedef struct dpp_etm_shap_shap_bucket_map_tbl_t {
+	ZXIC_UINT32 shap_map;
+} DPP_ETM_SHAP_SHAP_BUCKET_MAP_TBL_T;
+
+typedef struct dpp_etm_shap_bkt_para_tbl_t {
+	ZXIC_UINT32 bucket_depth;
+	ZXIC_UINT32 bucket_rate;
+} DPP_ETM_SHAP_BKT_PARA_TBL_T;
+
+typedef struct dpp_etm_crdt_credit_en_t {
+	ZXIC_UINT32 credit_en;
+} DPP_ETM_CRDT_CREDIT_EN_T;
+
+typedef struct dpp_etm_crdt_crt_inter1_t {
+	ZXIC_UINT32 crd_inter1;
+} DPP_ETM_CRDT_CRT_INTER1_T;
+
+typedef struct dpp_etm_crdt_db_token_t {
+	ZXIC_UINT32 db_token;
+} DPP_ETM_CRDT_DB_TOKEN_T;
+
+typedef struct dpp_etm_crdt_crs_flt_cfg_t {
+	ZXIC_UINT32 crs_flt_cfg;
+} DPP_ETM_CRDT_CRS_FLT_CFG_T;
+
+typedef struct dpp_etm_crdt_th_sp_t {
+	ZXIC_UINT32 th_sp;
+} DPP_ETM_CRDT_TH_SP_T;
+
+typedef struct dpp_etm_crdt_th_wfq_fq_t {
+	ZXIC_UINT32 th_fq;
+	ZXIC_UINT32 th_wfq;
+} DPP_ETM_CRDT_TH_WFQ_FQ_T;
+
+typedef struct dpp_etm_crdt_th_wfq2_fq2_t {
+	ZXIC_UINT32 th_fq2;
+	ZXIC_UINT32 th_wfq2;
+} DPP_ETM_CRDT_TH_WFQ2_FQ2_T;
+
+typedef struct dpp_etm_crdt_th_wfq4_fq4_t {
+	ZXIC_UINT32 th_fq4;
+	ZXIC_UINT32 th_wfq4;
+} DPP_ETM_CRDT_TH_WFQ4_FQ4_T;
+
+typedef struct dpp_etm_crdt_cfg_state_t {
+	ZXIC_UINT32 cfg_state;
+} DPP_ETM_CRDT_CFG_STATE_T;
+
+typedef struct dpp_etm_crdt_crdt_ind_cmd_t {
+	ZXIC_UINT32 rd;
+	ZXIC_UINT32 mem_id;
+	ZXIC_UINT32 addr;
+} DPP_ETM_CRDT_CRDT_IND_CMD_T;
+
+typedef struct dpp_etm_crdt_crdt_ind_sta_t {
+	ZXIC_UINT32 indirectaccessdone;
+} DPP_ETM_CRDT_CRDT_IND_STA_T;
+
+typedef struct dpp_etm_crdt_crdt_ind_data0_t {
+	ZXIC_UINT32 indirectdata0;
+} DPP_ETM_CRDT_CRDT_IND_DATA0_T;
+
+typedef struct dpp_etm_crdt_crdt_ind_data1_t {
+	ZXIC_UINT32 indirectdata1;
+} DPP_ETM_CRDT_CRDT_IND_DATA1_T;
+
+typedef struct dpp_etm_crdt_crdt_state_t {
+	ZXIC_UINT32 crdt_int;
+	ZXIC_UINT32 crdt_rdy;
+} DPP_ETM_CRDT_CRDT_STATE_T;
+
+typedef struct dpp_etm_crdt_stat_que_id_0_t {
+	ZXIC_UINT32 stat_que_id_0;
+} DPP_ETM_CRDT_STAT_QUE_ID_0_T;
+
+typedef struct dpp_etm_crdt_stat_que_id_1_t {
+	ZXIC_UINT32 stat_que_id_1;
+} DPP_ETM_CRDT_STAT_QUE_ID_1_T;
+
+typedef struct dpp_etm_crdt_stat_que_id_2_t {
+	ZXIC_UINT32 stat_que_id_2;
+} DPP_ETM_CRDT_STAT_QUE_ID_2_T;
+
+typedef struct dpp_etm_crdt_stat_que_id_3_t {
+	ZXIC_UINT32 stat_que_id_3;
+} DPP_ETM_CRDT_STAT_QUE_ID_3_T;
+
+typedef struct dpp_etm_crdt_stat_que_id_4_t {
+	ZXIC_UINT32 stat_que_id_4;
+} DPP_ETM_CRDT_STAT_QUE_ID_4_T;
+
+typedef struct dpp_etm_crdt_stat_que_id_5_t {
+	ZXIC_UINT32 stat_que_id_5;
+} DPP_ETM_CRDT_STAT_QUE_ID_5_T;
+
+typedef struct dpp_etm_crdt_stat_que_id_6_t {
+	ZXIC_UINT32 stat_que_id_6;
+} DPP_ETM_CRDT_STAT_QUE_ID_6_T;
+
+typedef struct dpp_etm_crdt_stat_que_id_7_t {
+	ZXIC_UINT32 stat_que_id_7;
+} DPP_ETM_CRDT_STAT_QUE_ID_7_T;
+
+typedef struct dpp_etm_crdt_stat_que_id_8_t {
+	ZXIC_UINT32 stat_que_id_8;
+} DPP_ETM_CRDT_STAT_QUE_ID_8_T;
+
+typedef struct dpp_etm_crdt_stat_que_id_9_t {
+	ZXIC_UINT32 stat_que_id_9;
+} DPP_ETM_CRDT_STAT_QUE_ID_9_T;
+
+typedef struct dpp_etm_crdt_stat_que_id_10_t {
+	ZXIC_UINT32 stat_que_id_10;
+} DPP_ETM_CRDT_STAT_QUE_ID_10_T;
+
+typedef struct dpp_etm_crdt_stat_que_id_11_t {
+	ZXIC_UINT32 stat_que_id_11;
+} DPP_ETM_CRDT_STAT_QUE_ID_11_T;
+
+typedef struct dpp_etm_crdt_stat_que_id_12_t {
+	ZXIC_UINT32 stat_que_id_12;
+} DPP_ETM_CRDT_STAT_QUE_ID_12_T;
+
+typedef struct dpp_etm_crdt_stat_que_id_13_t {
+	ZXIC_UINT32 stat_que_id_13;
+} DPP_ETM_CRDT_STAT_QUE_ID_13_T;
+
+typedef struct dpp_etm_crdt_stat_que_id_14_t {
+	ZXIC_UINT32 stat_que_id_14;
+} DPP_ETM_CRDT_STAT_QUE_ID_14_T;
+
+typedef struct dpp_etm_crdt_stat_que_id_15_t {
+	ZXIC_UINT32 stat_que_id_15;
+} DPP_ETM_CRDT_STAT_QUE_ID_15_T;
+
+typedef struct dpp_etm_crdt_stat_que_credit_t {
+	ZXIC_UINT32 stat_que_credit_cnt;
+} DPP_ETM_CRDT_STAT_QUE_CREDIT_T;
+
+typedef struct dpp_etm_crdt_crdt_cfg_ram_init_t {
+	ZXIC_UINT32 cfg_ram_init_done;
+	ZXIC_UINT32 cfg_ram_init_en;
+} DPP_ETM_CRDT_CRDT_CFG_RAM_INIT_T;
+
+typedef struct dpp_etm_crdt_crdt_sta_ram_init_t {
+	ZXIC_UINT32 sta_ram_init_done;
+	ZXIC_UINT32 sta_ram_init_en;
+} DPP_ETM_CRDT_CRDT_STA_RAM_INIT_T;
+
+typedef struct dpp_etm_crdt_crs_que_id_t {
+	ZXIC_UINT32 crs_que_id;
+} DPP_ETM_CRDT_CRS_QUE_ID_T;
+
+typedef struct dpp_etm_crdt_qmu_crs_end_state_t {
+	ZXIC_UINT32 qmu_crs_end_state;
+} DPP_ETM_CRDT_QMU_CRS_END_STATE_T;
+
+typedef struct dpp_etm_crdt_shap_rdy_t {
+	ZXIC_UINT32 shap_rdy;
+} DPP_ETM_CRDT_SHAP_RDY_T;
+
+typedef struct dpp_etm_crdt_shap_int_reg_t {
+	ZXIC_UINT32 pp_c_token_min_int;
+} DPP_ETM_CRDT_SHAP_INT_REG_T;
+
+typedef struct dpp_etm_crdt_shap_int_mask_reg_t {
+	ZXIC_UINT32 pp_c_token_min_int_mask;
+} DPP_ETM_CRDT_SHAP_INT_MASK_REG_T;
+
+typedef struct dpp_etm_crdt_token_state_almost_empty_th_t {
+	ZXIC_UINT32 token_state_almost_empty_th;
+} DPP_ETM_CRDT_TOKEN_STATE_ALMOST_EMPTY_TH_T;
+
+typedef struct dpp_etm_crdt_token_state_empty_th_t {
+	ZXIC_UINT32 token_state_empty_th;
+} DPP_ETM_CRDT_TOKEN_STATE_EMPTY_TH_T;
+
+typedef struct dpp_etm_crdt_full_th_t {
+	ZXIC_UINT32 token_state_full_th;
+} DPP_ETM_CRDT_FULL_TH_T;
+
+typedef struct dpp_etm_crdt_pp_c_level_shap_en_t {
+	ZXIC_UINT32 pp_c_level_shap_en;
+} DPP_ETM_CRDT_PP_C_LEVEL_SHAP_EN_T;
+
+typedef struct dpp_etm_crdt_enq_token_th_t {
+	ZXIC_UINT32 enq_token_th;
+} DPP_ETM_CRDT_ENQ_TOKEN_TH_T;
+
+typedef struct dpp_etm_crdt_pp_tokenq_level1_qstate_weight_cir_t {
+	ZXIC_UINT32 pp_pp_q_state_cir;
+	ZXIC_UINT32 pp_pp_q_weight_wfq_l1_cir;
+} DPP_ETM_CRDT_PP_TOKENQ_LEVEL1_QSTATE_WEIGHT_CIR_T;
+
+typedef struct dpp_etm_crdt_pp_idle_weight_level1_cir_t {
+	ZXIC_UINT32 pp_idle_q_weight_wfq_l1_cir;
+} DPP_ETM_CRDT_PP_IDLE_WEIGHT_LEVEL1_CIR_T;
+
+typedef struct dpp_etm_crdt_rci_grade_th_0_cfg_t {
+	ZXIC_UINT32 rci_grade_th_0_cfg;
+} DPP_ETM_CRDT_RCI_GRADE_TH_0_CFG_T;
+
+typedef struct dpp_etm_crdt_rci_grade_th_1_cfg_t {
+	ZXIC_UINT32 rci_grade_th_1_cfg;
+} DPP_ETM_CRDT_RCI_GRADE_TH_1_CFG_T;
+
+typedef struct dpp_etm_crdt_rci_grade_th_2_cfg_t {
+	ZXIC_UINT32 rci_grade_th_2_cfg;
+} DPP_ETM_CRDT_RCI_GRADE_TH_2_CFG_T;
+
+typedef struct dpp_etm_crdt_rci_grade_th_3_cfg_t {
+	ZXIC_UINT32 rci_grade_th_3_cfg;
+} DPP_ETM_CRDT_RCI_GRADE_TH_3_CFG_T;
+
+typedef struct dpp_etm_crdt_rci_grade_th_4_cfg_t {
+	ZXIC_UINT32 rci_grade_th_4_cfg;
+} DPP_ETM_CRDT_RCI_GRADE_TH_4_CFG_T;
+
+typedef struct dpp_etm_crdt_rci_grade_th_5_cfg_t {
+	ZXIC_UINT32 rci_grade_th_5_cfg;
+} DPP_ETM_CRDT_RCI_GRADE_TH_5_CFG_T;
+
+typedef struct dpp_etm_crdt_rci_grade_th_6_cfg_t {
+	ZXIC_UINT32 rci_grade_th_6_cfg;
+} DPP_ETM_CRDT_RCI_GRADE_TH_6_CFG_T;
+
+typedef struct dpp_etm_crdt_flow_del_cmd_t {
+	ZXIC_UINT32 flow_del_busy;
+	ZXIC_UINT32 flow_alt_cmd;
+	ZXIC_UINT32 flow_alt_ind;
+} DPP_ETM_CRDT_FLOW_DEL_CMD_T;
+
+typedef struct dpp_etm_crdt_cnt_clr_t {
+	ZXIC_UINT32 cnt_clr;
+} DPP_ETM_CRDT_CNT_CLR_T;
+
+typedef struct dpp_etm_crdt_crdt_int_bus_t {
+	ZXIC_UINT32 ldstr_fifo15_ovf_int;
+	ZXIC_UINT32 ldstr_fifo14_ovf_int;
+	ZXIC_UINT32 ldstr_fifo13_ovf_int;
+	ZXIC_UINT32 ldstr_fifo12_ovf_int;
+	ZXIC_UINT32 ldstr_fifo11_ovf_int;
+	ZXIC_UINT32 ldstr_fifo10_ovf_int;
+	ZXIC_UINT32 ldstr_fifo9_ovf_int;
+	ZXIC_UINT32 ldstr_fifo8_ovf_int;
+	ZXIC_UINT32 ldstr_fifo7_ovf_int;
+	ZXIC_UINT32 ldstr_fifo6_ovf_int;
+	ZXIC_UINT32 ldstr_fifo5_ovf_int;
+	ZXIC_UINT32 ldstr_fifo4_ovf_int;
+	ZXIC_UINT32 ldstr_fifo3_ovf_int;
+	ZXIC_UINT32 ldstr_fifo2_ovf_int;
+	ZXIC_UINT32 ldstr_fifo1_ovf_int;
+	ZXIC_UINT32 ldstr_fifo0_ovf_int;
+	ZXIC_UINT32 cfg_del_err_int;
+	ZXIC_UINT32 flwin_secrs_fifo_ovf_int;
+	ZXIC_UINT32 flwin_voqcrs_fifo_ovf_int;
+} DPP_ETM_CRDT_CRDT_INT_BUS_T;
+
+typedef struct dpp_etm_crdt_crdt_int_mask_t {
+	ZXIC_UINT32 crdt_int_mask;
+} DPP_ETM_CRDT_CRDT_INT_MASK_T;
+
+typedef struct dpp_etm_crdt_cfg_weight_together_t {
+	ZXIC_UINT32 cfg_weight_together;
+} DPP_ETM_CRDT_CFG_WEIGHT_TOGETHER_T;
+
+typedef struct dpp_etm_crdt_weight_t {
+	ZXIC_UINT32 c_weight;
+	ZXIC_UINT32 e_weight;
+} DPP_ETM_CRDT_WEIGHT_T;
+
+typedef struct dpp_etm_crdt_dev_sp_state_t {
+	ZXIC_UINT32 dev_sp_state;
+} DPP_ETM_CRDT_DEV_SP_STATE_T;
+
+typedef struct dpp_etm_crdt_dev_crs_t {
+	ZXIC_UINT32 dev_crs;
+} DPP_ETM_CRDT_DEV_CRS_T;
+
+typedef struct dpp_etm_crdt_congest_token_disable_31_0_t {
+	ZXIC_UINT32 congest_token_disable_31_0;
+} DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0_T;
+
+typedef struct dpp_etm_crdt_congest_token_disable_63_32_t {
+	ZXIC_UINT32 congest_token_disable_63_32;
+} DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32_T;
+
+typedef struct dpp_etm_crdt_crdt_interval_en_cfg_t {
+	ZXIC_UINT32 crdt_interval_en;
+} DPP_ETM_CRDT_CRDT_INTERVAL_EN_CFG_T;
+
+typedef struct dpp_etm_crdt_q_token_staue_cfg_t {
+	ZXIC_UINT32 test_token_q_id;
+} DPP_ETM_CRDT_Q_TOKEN_STAUE_CFG_T;
+
+typedef struct dpp_etm_crdt_q_token_dist_cnt_t {
+	ZXIC_UINT32 q_token_dist_counter;
+} DPP_ETM_CRDT_Q_TOKEN_DIST_CNT_T;
+
+typedef struct dpp_etm_crdt_q_token_dec_cnt_t {
+	ZXIC_UINT32 q_token_dec_counter;
+} DPP_ETM_CRDT_Q_TOKEN_DEC_CNT_T;
+
+typedef struct dpp_etm_crdt_pp_weight_ram_t {
+	ZXIC_UINT32 pp_c_weight;
+} DPP_ETM_CRDT_PP_WEIGHT_RAM_T;
+
+typedef struct dpp_etm_crdt_pp_cbs_shape_en_ram_t {
+	ZXIC_UINT32 pp_cbs;
+	ZXIC_UINT32 pp_c_shap_en;
+} DPP_ETM_CRDT_PP_CBS_SHAPE_EN_RAM_T;
+
+typedef struct dpp_etm_crdt_pp_next_pc_q_state_ram_t {
+	ZXIC_UINT32 pp_next_pc;
+	ZXIC_UINT32 pp_token_num;
+	ZXIC_UINT32 pp_q_state;
+} DPP_ETM_CRDT_PP_NEXT_PC_Q_STATE_RAM_T;
+
+typedef struct dpp_etm_crdt_dev_interval_t {
+	ZXIC_UINT32 dev_interval;
+} DPP_ETM_CRDT_DEV_INTERVAL_T;
+
+typedef struct dpp_etm_crdt_dev_wfq_cnt_t {
+	ZXIC_UINT32 dev_wfq_cnt;
+} DPP_ETM_CRDT_DEV_WFQ_CNT_T;
+
+typedef struct dpp_etm_crdt_dev_wfq_state_t {
+	ZXIC_UINT32 dev_wfq_state;
+} DPP_ETM_CRDT_DEV_WFQ_STATE_T;
+
+typedef struct dpp_etm_crdt_dev_active_head_ptr_t {
+	ZXIC_UINT32 dev_active_head_ptr;
+} DPP_ETM_CRDT_DEV_ACTIVE_HEAD_PTR_T;
+
+typedef struct dpp_etm_crdt_dev_active_tail_ptr_t {
+	ZXIC_UINT32 dev_active_tail_ptr;
+} DPP_ETM_CRDT_DEV_ACTIVE_TAIL_PTR_T;
+
+typedef struct dpp_etm_crdt_dev_unactive_head_ptr_t {
+	ZXIC_UINT32 dev_unactive_head_ptr;
+} DPP_ETM_CRDT_DEV_UNACTIVE_HEAD_PTR_T;
+
+typedef struct dpp_etm_crdt_dev_unactive_tail_ptr_t {
+	ZXIC_UINT32 dev_unactive_tail_ptr;
+} DPP_ETM_CRDT_DEV_UNACTIVE_TAIL_PTR_T;
+
+typedef struct dpp_etm_crdt_pp_weight_t {
+	ZXIC_UINT32 pp_weight;
+} DPP_ETM_CRDT_PP_WEIGHT_T;
+
+typedef struct dpp_etm_crdt_pp_que_state_t {
+	ZXIC_UINT32 pp_enque_flag;
+	ZXIC_UINT32 pp_cir;
+	ZXIC_UINT32 pp_congest_cir;
+	ZXIC_UINT32 pp_crs;
+	ZXIC_UINT32 dev_sp;
+} DPP_ETM_CRDT_PP_QUE_STATE_T;
+
+typedef struct dpp_etm_crdt_pp_next_ptr_t {
+	ZXIC_UINT32 pp_next_ptr;
+} DPP_ETM_CRDT_PP_NEXT_PTR_T;
+
+typedef struct dpp_etm_crdt_pp_cfg_t {
+	ZXIC_UINT32 pp_cfg;
+} DPP_ETM_CRDT_PP_CFG_T;
+
+typedef struct dpp_etm_crdt_pp_up_ptr_t {
+	ZXIC_UINT32 pp_up_ptr;
+} DPP_ETM_CRDT_PP_UP_PTR_T;
+
+typedef struct dpp_etm_crdt_credit_drop_num_t {
+	ZXIC_UINT32 credit_drop_num;
+} DPP_ETM_CRDT_CREDIT_DROP_NUM_T;
+
+typedef struct dpp_etm_crdt_se_id_lv0_t {
+	ZXIC_UINT32 se_id_out_lv0;
+} DPP_ETM_CRDT_SE_ID_LV0_T;
+
+typedef struct dpp_etm_crdt_se_id_lv1_t {
+	ZXIC_UINT32 se_id_out_lv1;
+} DPP_ETM_CRDT_SE_ID_LV1_T;
+
+typedef struct dpp_etm_crdt_se_id_lv2_t {
+	ZXIC_UINT32 se_id_out_lv2;
+} DPP_ETM_CRDT_SE_ID_LV2_T;
+
+typedef struct dpp_etm_crdt_se_id_lv3_t {
+	ZXIC_UINT32 se_id_out_lv3;
+} DPP_ETM_CRDT_SE_ID_LV3_T;
+
+typedef struct dpp_etm_crdt_se_id_lv4_t {
+	ZXIC_UINT32 se_id_out_lv4;
+} DPP_ETM_CRDT_SE_ID_LV4_T;
+
+typedef struct dpp_etm_crdt_que_id_t {
+	ZXIC_UINT32 que_id_out;
+} DPP_ETM_CRDT_QUE_ID_T;
+
+typedef struct dpp_etm_crdt_se_info_lv0_t {
+	ZXIC_UINT32 se_shape_lv0;
+	ZXIC_UINT32 se_ins_out_lv0;
+	ZXIC_UINT32 se_state_out_lv0;
+	ZXIC_UINT32 se_new_state_out_lv0;
+} DPP_ETM_CRDT_SE_INFO_LV0_T;
+
+typedef struct dpp_etm_crdt_se_info_lv1_t {
+	ZXIC_UINT32 se_shape_lv1;
+	ZXIC_UINT32 se_ins_out_lv1;
+	ZXIC_UINT32 se_state_out_lv1;
+	ZXIC_UINT32 se_new_state_out_lv1;
+} DPP_ETM_CRDT_SE_INFO_LV1_T;
+
+typedef struct dpp_etm_crdt_se_info_lv2_t {
+	ZXIC_UINT32 se_shape_lv2;
+	ZXIC_UINT32 se_ins_out_lv2;
+	ZXIC_UINT32 se_state_out_lv2;
+	ZXIC_UINT32 se_new_state_out_lv2;
+} DPP_ETM_CRDT_SE_INFO_LV2_T;
+
+typedef struct dpp_etm_crdt_se_info_lv3_t {
+	ZXIC_UINT32 se_shape_lv3;
+	ZXIC_UINT32 se_ins_out_lv3;
+	ZXIC_UINT32 se_state_out_lv3;
+	ZXIC_UINT32 se_new_state_out_lv3;
+} DPP_ETM_CRDT_SE_INFO_LV3_T;
+
+typedef struct dpp_etm_crdt_se_info_lv4_t {
+	ZXIC_UINT32 se_shape_lv4;
+	ZXIC_UINT32 se_ins_out_lv4;
+	ZXIC_UINT32 se_state_out_lv4;
+	ZXIC_UINT32 se_new_state_out_lv4;
+} DPP_ETM_CRDT_SE_INFO_LV4_T;
+
+typedef struct dpp_etm_crdt_que_state_t {
+	ZXIC_UINT32 que_state_out;
+} DPP_ETM_CRDT_QUE_STATE_T;
+
+typedef struct dpp_etm_crdt_eir_off_in_advance_t {
+	ZXIC_UINT32 eir_crs_filter;
+} DPP_ETM_CRDT_EIR_OFF_IN_ADVANCE_T;
+
+typedef struct dpp_etm_crdt_double_level_shap_prevent_t {
+	ZXIC_UINT32 double_level_shap_prevent;
+} DPP_ETM_CRDT_DOUBLE_LEVEL_SHAP_PREVENT_T;
+
+typedef struct dpp_etm_crdt_add_store_cycle_t {
+	ZXIC_UINT32 add_store_cycle;
+} DPP_ETM_CRDT_ADD_STORE_CYCLE_T;
+
+typedef struct dpp_etm_crdt_tflag2_wr_flag_sum_t {
+	ZXIC_UINT32 tflag2_wr_flag_sum;
+} DPP_ETM_CRDT_TFLAG2_WR_FLAG_SUM_T;
+
+typedef struct dpp_etm_crdt_flowque_para_tbl_t {
+	ZXIC_UINT32 flowque_link;
+	ZXIC_UINT32 flowque_w;
+	ZXIC_UINT32 flowque_pri;
+} DPP_ETM_CRDT_FLOWQUE_PARA_TBL_T;
+
+typedef struct dpp_etm_crdt_se_para_tbl_t {
+	ZXIC_UINT32 se_insw;
+	ZXIC_UINT32 se_link;
+	ZXIC_UINT32 cp_token_en;
+	ZXIC_UINT32 se_w;
+	ZXIC_UINT32 se_pri;
+} DPP_ETM_CRDT_SE_PARA_TBL_T;
+
+typedef struct dpp_etm_crdt_flowque_ins_tbl_t {
+	ZXIC_UINT32 flowque_ins;
+} DPP_ETM_CRDT_FLOWQUE_INS_TBL_T;
+
+typedef struct dpp_etm_crdt_se_ins_tbl_t {
+	ZXIC_UINT32 se_ins_flag;
+	ZXIC_UINT32 se_ins_priority;
+} DPP_ETM_CRDT_SE_INS_TBL_T;
+
+typedef struct dpp_etm_crdt_eir_crs_filter_tbl_t {
+	ZXIC_UINT32 eir_crs_filter;
+} DPP_ETM_CRDT_EIR_CRS_FILTER_TBL_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_cfg_done_t {
+	ZXIC_UINT32 qcfg_qlist_cfg_done;
+} DPP_ETM_QMU_QCFG_QLIST_CFG_DONE_T;
+
+typedef struct dpp_etm_qmu_qcfg_qsch_credit_value_t {
+	ZXIC_UINT32 qcfg_qsch_credit_value;
+} DPP_ETM_QMU_QCFG_QSCH_CREDIT_VALUE_T;
+
+typedef struct dpp_etm_qmu_qcfg_qsch_crbal_init_value_t {
+	ZXIC_UINT32 qcfg_qsch_crbal_init_value;
+} DPP_ETM_QMU_QCFG_QSCH_CRBAL_INIT_VALUE_T;
+
+typedef struct dpp_etm_qmu_qcfg_qsch_crbal_init_mask_t {
+	ZXIC_UINT32 qcfg_qsch_crbal_init_mask;
+} DPP_ETM_QMU_QCFG_QSCH_CRBAL_INIT_MASK_T;
+
+typedef struct dpp_etm_qmu_cmdsch_rd_cmd_aful_th_t {
+	ZXIC_UINT32 cmdsch_rd_cmd_aful_th;
+} DPP_ETM_QMU_CMDSCH_RD_CMD_AFUL_TH_T;
+
+typedef struct dpp_etm_qmu_cfg_port_fc_interval_t {
+	ZXIC_UINT32 cfg_port_fc_interval;
+} DPP_ETM_QMU_CFG_PORT_FC_INTERVAL_T;
+
+typedef struct dpp_etm_qmu_qcfg_csch_aged_cfg_t {
+	ZXIC_UINT32 qcfg_csch_aged_cfg;
+} DPP_ETM_QMU_QCFG_CSCH_AGED_CFG_T;
+
+typedef struct dpp_etm_qmu_qcfg_csch_aged_scan_time_t {
+	ZXIC_UINT32 qcfg_csch_aged_scan_time;
+} DPP_ETM_QMU_QCFG_CSCH_AGED_SCAN_TIME_T;
+
+typedef struct dpp_etm_qmu_qcfg_qmu_qlist_state_query_t {
+	ZXIC_UINT32 pkt_age_req_fifo_afull;
+	ZXIC_UINT32 rd_release_fwft_afull;
+	ZXIC_UINT32 drop_imem_fwft_afull;
+	ZXIC_UINT32 pkt_age_req_fifo_empty;
+	ZXIC_UINT32 rd_release_fwft_empty;
+	ZXIC_UINT32 drop_imem_fwft_empty;
+	ZXIC_UINT32 mmu_qmu_sop_rd_rdy;
+	ZXIC_UINT32 big_fifo_empty;
+	ZXIC_UINT32 qmu_mmu_rd_release_rdy;
+	ZXIC_UINT32 xsw_qmu_crs_rdy;
+	ZXIC_UINT32 mmu_qmu_rdy;
+	ZXIC_UINT32 mmu_ql_wr_rdy;
+	ZXIC_UINT32 mmu_ql_rd_rdy;
+	ZXIC_UINT32 csw_ql_rdy;
+	ZXIC_UINT32 ql_init_done;
+	ZXIC_UINT32 free_addr_ready;
+	ZXIC_UINT32 bank_group_afull;
+	ZXIC_UINT32 pds_fwft_empty;
+	ZXIC_UINT32 enq_rpt_fwft_afull;
+} DPP_ETM_QMU_QCFG_QMU_QLIST_STATE_QUERY_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qsch_crbal_drop_en_t {
+	ZXIC_UINT32 cfgmt_qsch_all_crbal_drop_en;
+	ZXIC_UINT32 cfgmt_qsch_crbal_drop_en;
+} DPP_ETM_QMU_CFGMT_QSCH_CRBAL_DROP_EN_T;
+
+typedef struct dpp_etm_qmu_cfgmt_wlist_qnum_fifo_aful_th_t {
+	ZXIC_UINT32 cfgmt_wlist_qnum_fifo_aful_th;
+} DPP_ETM_QMU_CFGMT_WLIST_QNUM_FIFO_AFUL_TH_T;
+
+typedef struct dpp_etm_qmu_qcfg_csw_pkt_blk_mode_t {
+	ZXIC_UINT32 qcfg_csw_pkt_blk_mode;
+} DPP_ETM_QMU_QCFG_CSW_PKT_BLK_MODE_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_ram_init_cancel_t {
+	ZXIC_UINT32 qcfg_qlist_ram_init_cancel;
+} DPP_ETM_QMU_QCFG_QLIST_RAM_INIT_CANCEL_T;
+
+typedef struct dpp_etm_qmu_qcfg_qsch_crbal_transfer_mode_t {
+	ZXIC_UINT32 qcfg_qsch_crbal_transfer_mode;
+	ZXIC_UINT32 qcfg_qsch_crbal_transfer_value;
+} DPP_ETM_QMU_QCFG_QSCH_CRBAL_TRANSFER_MODE_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_qclr_interval_t {
+	ZXIC_UINT32 qcfg_qlist_qclr_interval;
+} DPP_ETM_QMU_QCFG_QLIST_QCLR_INTERVAL_T;
+
+typedef struct dpp_etm_qmu_qcfg_qsch_qclr_rate_t {
+	ZXIC_UINT32 qcfg_qsch_qclr_rate;
+} DPP_ETM_QMU_QCFG_QSCH_QCLR_RATE_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_ddr_random_t {
+	ZXIC_UINT32 qcfg_qlist_ddr_random;
+} DPP_ETM_QMU_QCFG_QLIST_DDR_RANDOM_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qlist_pds_fifo_afull_th_t {
+	ZXIC_UINT32 cfgmt_qlist_pds_fifo_afull_th;
+} DPP_ETM_QMU_CFGMT_QLIST_PDS_FIFO_AFULL_TH_T;
+
+typedef struct dpp_etm_qmu_cfgmt_sop_cmd_fifo_afull_th_t {
+	ZXIC_UINT32 cfgmt_sop_cmd_fifo_afull_th;
+} DPP_ETM_QMU_CFGMT_SOP_CMD_FIFO_AFULL_TH_T;
+
+typedef struct dpp_etm_qmu_cfgmt_non_sop_cmd_fifo_afull_th_t {
+	ZXIC_UINT32 cfgmt_non_sop_cmd_fifo_afull_th;
+} DPP_ETM_QMU_CFGMT_NON_SOP_CMD_FIFO_AFULL_TH_T;
+
+typedef struct dpp_etm_qmu_cfgmt_mmu_data_fifo_afull_th_t {
+	ZXIC_UINT32 cfgmt_mmu_data_fifo_afull_th;
+} DPP_ETM_QMU_CFGMT_MMU_DATA_FIFO_AFULL_TH_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_bank_ept_th_t {
+	ZXIC_UINT32 qcfg_qlist_bank_ept_th;
+} DPP_ETM_QMU_QCFG_QLIST_BANK_EPT_TH_T;
+
+typedef struct dpp_etm_qmu_random_bypass_en_t {
+	ZXIC_UINT32 random_bypass_en;
+} DPP_ETM_QMU_RANDOM_BYPASS_EN_T;
+
+typedef struct dpp_etm_qmu_cfgmt_crs_spd_bypass_t {
+	ZXIC_UINT32 cfgmt_crs_spd_bypass;
+} DPP_ETM_QMU_CFGMT_CRS_SPD_BYPASS_T;
+
+typedef struct dpp_etm_qmu_cfgmt_crs_interval_t {
+	ZXIC_UINT32 cfgmt_crs_interval;
+} DPP_ETM_QMU_CFGMT_CRS_INTERVAL_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_auto_credit_control_en_t {
+	ZXIC_UINT32 cfg_qsch_auto_credit_control_en;
+} DPP_ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_EN_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_autocrfrstque_t {
+	ZXIC_UINT32 cfg_qsch_autocrfrstque;
+} DPP_ETM_QMU_CFG_QSCH_AUTOCRFRSTQUE_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_autocrlastque_t {
+	ZXIC_UINT32 cfg_qsch_autocrlastque;
+} DPP_ETM_QMU_CFG_QSCH_AUTOCRLASTQUE_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_autocreditrate_t {
+	ZXIC_UINT32 cfg_qsch_autocreditrate;
+} DPP_ETM_QMU_CFG_QSCH_AUTOCREDITRATE_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_scanfrstque_t {
+	ZXIC_UINT32 cfg_qsch_scanfrstque;
+} DPP_ETM_QMU_CFG_QSCH_SCANFRSTQUE_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_scanlastque_t {
+	ZXIC_UINT32 cfg_qsch_scanlastque;
+} DPP_ETM_QMU_CFG_QSCH_SCANLASTQUE_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_scanrate_t {
+	ZXIC_UINT32 cfg_qsch_scanrate;
+} DPP_ETM_QMU_CFG_QSCH_SCANRATE_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_scan_en_t {
+	ZXIC_UINT32 cfg_qsch_scan_en;
+} DPP_ETM_QMU_CFG_QSCH_SCAN_EN_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qsch_rd_credit_fifo_rate_t {
+	ZXIC_UINT32 cfgmt_qsch_rd_credit_fifo_rate;
+} DPP_ETM_QMU_CFGMT_QSCH_RD_CREDIT_FIFO_RATE_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_bdep_t {
+	ZXIC_UINT32 qcfg_qlist_bdep;
+} DPP_ETM_QMU_QCFG_QLIST_BDEP_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_bhead_t {
+	ZXIC_UINT32 bank_vld;
+	ZXIC_UINT32 qcfg_qlist_bhead;
+} DPP_ETM_QMU_QCFG_QLIST_BHEAD_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_btail_t {
+	ZXIC_UINT32 qcfg_qlist_btail;
+} DPP_ETM_QMU_QCFG_QLIST_BTAIL_T;
+
+typedef struct dpp_etm_qmu_qcfg_qsch_shap_param_t {
+	ZXIC_UINT32 qcfg_qsch_shap_en;
+	ZXIC_UINT32 qcfg_qsch_shap_param1;
+	ZXIC_UINT32 qcfg_qsch_shap_param2;
+} DPP_ETM_QMU_QCFG_QSCH_SHAP_PARAM_T;
+
+typedef struct dpp_etm_qmu_qcfg_qsch_shap_token_t {
+	ZXIC_UINT32 qcfg_qsch_shap_token;
+} DPP_ETM_QMU_QCFG_QSCH_SHAP_TOKEN_T;
+
+typedef struct dpp_etm_qmu_qcfg_qsch_shap_offset_t {
+	ZXIC_UINT32 qcfg_qsch_shap_offset;
+} DPP_ETM_QMU_QCFG_QSCH_SHAP_OFFSET_T;
+
+typedef struct dpp_etm_qmu_qcfg_qsch_crs_eir_th_t {
+	ZXIC_UINT32 qcfg_qsch_crs_eir_th;
+} DPP_ETM_QMU_QCFG_QSCH_CRS_EIR_TH_T;
+
+typedef struct dpp_etm_qmu_qcfg_qsch_crs_th1_t {
+	ZXIC_UINT32 qcfg_qsch_crs_th1;
+} DPP_ETM_QMU_QCFG_QSCH_CRS_TH1_T;
+
+typedef struct dpp_etm_qmu_qcfg_qsch_crs_th2_t {
+	ZXIC_UINT32 qcfg_qsch_crs_th2;
+} DPP_ETM_QMU_QCFG_QSCH_CRS_TH2_T;
+
+typedef struct dpp_etm_qmu_qcfg_csch_congest_th_t {
+	ZXIC_UINT32 qcfg_csch_congest_th;
+} DPP_ETM_QMU_QCFG_CSCH_CONGEST_TH_T;
+
+typedef struct dpp_etm_qmu_qcfg_csch_sp_fc_th_t {
+	ZXIC_UINT32 qcfg_csch_sp_fc_th;
+} DPP_ETM_QMU_QCFG_CSCH_SP_FC_TH_T;
+
+typedef struct dpp_etm_qmu_qcfg_csw_shap_parameter_t {
+	ZXIC_UINT32 qcfg_csw_shap_en;
+	ZXIC_UINT32 qcfg_csw_shap_parameter;
+} DPP_ETM_QMU_QCFG_CSW_SHAP_PARAMETER_T;
+
+typedef struct dpp_etm_qmu_cfgmt_rd_release_aful_th_t {
+	ZXIC_UINT32 cfgmt_rd_release_aful_th;
+} DPP_ETM_QMU_CFGMT_RD_RELEASE_AFUL_TH_T;
+
+typedef struct dpp_etm_qmu_cfgmt_drop_imem_release_fifo_aful_th_t {
+	ZXIC_UINT32 cfgmt_drop_imem_release_fifo_aful_th;
+} DPP_ETM_QMU_CFGMT_DROP_IMEM_RELEASE_FIFO_AFUL_TH_T;
+
+typedef struct dpp_etm_qmu_cfgmt_nnh_rd_buf_aful_th_t {
+	ZXIC_UINT32 cfgmt_nnh_rd_buf_aful_th;
+} DPP_ETM_QMU_CFGMT_NNH_RD_BUF_AFUL_TH_T;
+
+typedef struct dpp_etm_qmu_cfg_pid_use_inall_t {
+	ZXIC_UINT32 cfgmt_nod_rd_buf_0_aful_th;
+} DPP_ETM_QMU_CFG_PID_USE_INALL_T;
+
+typedef struct dpp_etm_qmu_cfg_pid_round_th_t {
+	ZXIC_UINT32 cfgmt_nod_rd_buf_1_aful_th;
+} DPP_ETM_QMU_CFG_PID_ROUND_TH_T;
+
+typedef struct dpp_etm_qmu_cfgmt_credit_fifo_afull_th_t {
+	ZXIC_UINT32 cfgmt_credit_fifo_afull_th;
+} DPP_ETM_QMU_CFGMT_CREDIT_FIFO_AFULL_TH_T;
+
+typedef struct dpp_etm_qmu_cfgmt_scan_fifo_afull_th_t {
+	ZXIC_UINT32 cfgmt_scan_fifo_afull_th;
+} DPP_ETM_QMU_CFGMT_SCAN_FIFO_AFULL_TH_T;
+
+typedef struct dpp_etm_qmu_cfgmt_small_fifo_aful_th_t {
+	ZXIC_UINT32 cfgmt_small_fifo_aful_th;
+} DPP_ETM_QMU_CFGMT_SMALL_FIFO_AFUL_TH_T;
+
+typedef struct dpp_etm_qmu_cfgmt_free_addr_fifo_aful_th_t {
+	ZXIC_UINT32 cfgmt_free_addr_fifo_aful_th;
+} DPP_ETM_QMU_CFGMT_FREE_ADDR_FIFO_AFUL_TH_T;
+
+typedef struct dpp_etm_qmu_cfgmt_enq_rpt_fifo_aful_th_t {
+	ZXIC_UINT32 cfgmt_enq_rpt_fifo_aful_th;
+} DPP_ETM_QMU_CFGMT_ENQ_RPT_FIFO_AFUL_TH_T;
+
+typedef struct dpp_etm_qmu_qcfg_csw_shap_token_depth_t {
+	ZXIC_UINT32 qcfg_csw_shap_token_depth;
+} DPP_ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTH_T;
+
+typedef struct dpp_etm_qmu_qcfg_csw_shap_offset_value_t {
+	ZXIC_UINT32 qcfg_csw_shap_offset_value;
+} DPP_ETM_QMU_QCFG_CSW_SHAP_OFFSET_VALUE_T;
+
+typedef struct dpp_etm_qmu_qcfg_csw_fc_offset_value_t {
+	ZXIC_UINT32 qcfg_csw_fc_offset_value;
+} DPP_ETM_QMU_QCFG_CSW_FC_OFFSET_VALUE_T;
+
+typedef struct dpp_etm_qmu_qmu_init_done_state_t {
+	ZXIC_UINT32 csch_qcfg_init_done;
+	ZXIC_UINT32 qsch_qcfg_init_done;
+	ZXIC_UINT32 qlist_qcfg_init_done;
+	ZXIC_UINT32 qcsr_ram_init_done;
+} DPP_ETM_QMU_QMU_INIT_DONE_STATE_T;
+
+typedef struct dpp_etm_qmu_csw_qcfg_port_shap_rdy_0_t {
+	ZXIC_UINT32 csw_qcfg_port_shap_rdy_0;
+} DPP_ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_0_T;
+
+typedef struct dpp_etm_qmu_csw_qcfg_port_shap_rdy_1_t {
+	ZXIC_UINT32 csw_qcfg_port_shap_rdy_1;
+} DPP_ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_1_T;
+
+typedef struct dpp_etm_qmu_qlist_cfgmt_ram_init_done_t {
+	ZXIC_UINT32 qlist_qcfg_qds_ram_init_done;
+	ZXIC_UINT32 qlist_qcfg_chk_ram_init_done;
+	ZXIC_UINT32 qlist_qcfg_ept_ram_init_done;
+	ZXIC_UINT32 qlist_qcfg_cti_ram_init_done;
+	ZXIC_UINT32 qlist_qcfg_cto_ram_init_done;
+	ZXIC_UINT32 qlist_qcfg_bcnt_ram_init_done;
+	ZXIC_UINT32 qlist_qcfg_biu_ram_init_done;
+	ZXIC_UINT32 qlist_qcfg_baram_init_done;
+} DPP_ETM_QMU_QLIST_CFGMT_RAM_INIT_DONE_T;
+
+typedef struct dpp_etm_qmu_qlist_cfgmt_ram_ecc_err_t {
+	ZXIC_UINT32 qds_ram_parity_err;
+	ZXIC_UINT32 qcsr_qnum_fifo_parity_err;
+	ZXIC_UINT32 sa_id_ram_parity_err;
+	ZXIC_UINT32 enq_rpt_fifo_parity_err;
+	ZXIC_UINT32 bcnts_parity_err;
+	ZXIC_UINT32 baram_parity_err_a;
+	ZXIC_UINT32 baram_parity_err_b;
+	ZXIC_UINT32 bcntm_ram_parity_err;
+	ZXIC_UINT32 biu_ram_single_ecc_err;
+	ZXIC_UINT32 chk_ram_single_ecc_err;
+	ZXIC_UINT32 cmd_sch_cmd_ram_single_ecc_err;
+	ZXIC_UINT32 cmd_sch_list_ram_single_ecc_err;
+	ZXIC_UINT32 cmd_sch_hp_ram_single_ecc_err;
+	ZXIC_UINT32 cmd_sch_tp_ram_single_ecc_err;
+	ZXIC_UINT32 cmd_sch_enq_active_ram_single_ecc_err;
+	ZXIC_UINT32 cmd_sch_deq_active_ram_single_ecc_err;
+	ZXIC_UINT32 cmd_sch_empty_ram_single_ecc_err;
+	ZXIC_UINT32 cmd_sch_eop_ram_single_ecc_err;
+	ZXIC_UINT32 cmd_sch_blkcnt_ram_single_ecc_err;
+	ZXIC_UINT32 biu_ram_double_ecc_err;
+	ZXIC_UINT32 chk_ram_double_ecc_err;
+	ZXIC_UINT32 cmd_sch_cmd_ram_double_ecc_err;
+	ZXIC_UINT32 cmd_sch_list_ram_double_ecc_err;
+	ZXIC_UINT32 cmd_sch_hp_ram_double_ecc_err;
+	ZXIC_UINT32 cmd_sch_tp_ram_double_ecc_err;
+	ZXIC_UINT32 cmd_sch_enq_active_ram_double_ecc_err;
+	ZXIC_UINT32 cmd_sch_deq_active_ram_double_ecc_err;
+	ZXIC_UINT32 cmd_sch_empty_ram_double_ecc_err;
+	ZXIC_UINT32 cmd_sch_eop_ram_double_ecc_err;
+	ZXIC_UINT32 cmd_sch_blkcnt_ram_double_ecc_err;
+} DPP_ETM_QMU_QLIST_CFGMT_RAM_ECC_ERR_T;
+
+typedef struct dpp_etm_qmu_qlist_cfgmt_ram_slot_err_t {
+	ZXIC_UINT32 qds_ram_enq_rd_slot_err;
+	ZXIC_UINT32 qds_ram_deq_rd_slot_err;
+	ZXIC_UINT32 qds_ram_enq_wr_slot_err;
+	ZXIC_UINT32 qds_ram_deq_wr_slot_err;
+	ZXIC_UINT32 chk_ram_enq_rd_slot_err;
+	ZXIC_UINT32 chk_ram_deq_rd_slot_err;
+	ZXIC_UINT32 chk_ram_enq_wr_slot_err;
+	ZXIC_UINT32 chk_ram_deq_wr_slot_err;
+	ZXIC_UINT32 ept_ram_enq_rd_slot_err;
+	ZXIC_UINT32 ept_ram_deq_rd_slot_err;
+	ZXIC_UINT32 ept_ram_enq_wr_slot_err;
+	ZXIC_UINT32 ept_ram_deq_wr_slot_err;
+	ZXIC_UINT32 cti_ram_enq_rd_slot_err;
+	ZXIC_UINT32 cti_ram_deq_rd_slot_err;
+	ZXIC_UINT32 cti_ram_enq_wr_slot_err;
+	ZXIC_UINT32 cti_ram_deq_wr_slot_err;
+	ZXIC_UINT32 cto_ram_enq_rd_slot_err;
+	ZXIC_UINT32 cto_ram_deq_rd_slot_err;
+	ZXIC_UINT32 cto_ram_enq_wr_slot_err;
+	ZXIC_UINT32 cto_ram_deq_wr_slot_err;
+} DPP_ETM_QMU_QLIST_CFGMT_RAM_SLOT_ERR_T;
+
+typedef struct dpp_etm_qmu_qsch_cfgmt_ram_ecc_t {
+	ZXIC_UINT32 crbal_rama_parity_error;
+	ZXIC_UINT32 crbal_ramb_parity_error;
+	ZXIC_UINT32 crs_ram_parity_error;
+	ZXIC_UINT32 wlist_flag_ram_single_ecc_err;
+	ZXIC_UINT32 wlist_next_single_ecc_err;
+	ZXIC_UINT32 wlist_wactive_ram_single_ecc_err;
+	ZXIC_UINT32 wlist_ractive_ram_single_ecc_err;
+	ZXIC_UINT32 wlist_tp1_ram_single_ecc_err;
+	ZXIC_UINT32 wlist_tp2_ram_single_ecc_err;
+	ZXIC_UINT32 wlist_empty1_ram_single_ecc_err_a;
+	ZXIC_UINT32 wlist_empty1_ram_single_ecc_err_b;
+	ZXIC_UINT32 wlist_empty2_ram_single_ecc_err_a;
+	ZXIC_UINT32 wlist_empty2_ram_single_ecc_err_b;
+	ZXIC_UINT32 wlist_hp_ram_single_ecc_err_a;
+	ZXIC_UINT32 wlist_hp_ram_single_ecc_err_b;
+	ZXIC_UINT32 wlist_flag_ram_double_ecc_err;
+	ZXIC_UINT32 wlist_next_double_ecc_err;
+	ZXIC_UINT32 wlist_wactive_ram_double_ecc_err;
+	ZXIC_UINT32 wlist_ractive_ram_double_ecc_err;
+	ZXIC_UINT32 wlist_tp1_ram_double_ecc_err;
+	ZXIC_UINT32 wlist_tp2_ram_double_ecc_err;
+	ZXIC_UINT32 wlist_empty1_ram_double_ecc_err_a;
+	ZXIC_UINT32 wlist_empty1_ram_double_ecc_err_b;
+	ZXIC_UINT32 wlist_empty2_ram_double_ecc_err_a;
+	ZXIC_UINT32 wlist_empty2_ram_double_ecc_err_b;
+	ZXIC_UINT32 wlist_hp_ram_double_ecc_err_a;
+	ZXIC_UINT32 wlist_hp_ram_double_ecc_err_b;
+} DPP_ETM_QMU_QSCH_CFGMT_RAM_ECC_T;
+
+typedef struct dpp_etm_qmu_qlist_cfgmt_fifo_state_t {
+	ZXIC_UINT32 pkt_age_req_fifo_overflow;
+	ZXIC_UINT32 pkt_age_req_fifo_underflow;
+	ZXIC_UINT32 qcsr_big_fifo_ovfl;
+	ZXIC_UINT32 qcsr_small_fifo_overflow;
+	ZXIC_UINT32 enq_rpt_fifo_overflow;
+	ZXIC_UINT32 enq_rpt_fifo_underflow;
+	ZXIC_UINT32 pds_fwft_overflow;
+	ZXIC_UINT32 pds_fwft_underflow;
+	ZXIC_UINT32 free_addr_fifo_overflow;
+	ZXIC_UINT32 free_addr_fifo_underflow;
+	ZXIC_UINT32 rd_release_fwft_overflow;
+	ZXIC_UINT32 rd_release_fwft_underflow;
+	ZXIC_UINT32 pid_free_list_overflow;
+	ZXIC_UINT32 pid_free_list_underflow;
+	ZXIC_UINT32 pid_prp_list_overflow;
+	ZXIC_UINT32 pid_prp_list_underflow;
+	ZXIC_UINT32 pid_rdy_list_overflow;
+	ZXIC_UINT32 pid_rdy_list_underflow;
+	ZXIC_UINT32 drop_imem_release_fwft_overflow;
+	ZXIC_UINT32 drop_imem_release_fwft_underflow;
+	ZXIC_UINT32 nnh_rd_buf_fifo_overflow;
+	ZXIC_UINT32 nnh_rd_buf_fifo_underflow;
+	ZXIC_UINT32 nod_rd_buf_0_fifo_overflow;
+	ZXIC_UINT32 nod_rd_buf_0_fifo_underflow;
+	ZXIC_UINT32 nod_rd_buf_1_fifo_overflow;
+	ZXIC_UINT32 nod_rd_buf_1_fifo_underflow;
+} DPP_ETM_QMU_QLIST_CFGMT_FIFO_STATE_T;
+
+typedef struct dpp_etm_qmu_qlist_qcfg_clr_done_t {
+	ZXIC_UINT32 qlist_qcfg_clr_done;
+} DPP_ETM_QMU_QLIST_QCFG_CLR_DONE_T;
+
+typedef struct dpp_etm_qmu_qmu_int_mask1_t {
+	ZXIC_UINT32 qmu_int_mask1;
+} DPP_ETM_QMU_QMU_INT_MASK1_T;
+
+typedef struct dpp_etm_qmu_qmu_int_mask2_t {
+	ZXIC_UINT32 qmu_int_mask2;
+} DPP_ETM_QMU_QMU_INT_MASK2_T;
+
+typedef struct dpp_etm_qmu_qmu_int_mask3_t {
+	ZXIC_UINT32 qmu_int_mask3;
+} DPP_ETM_QMU_QMU_INT_MASK3_T;
+
+typedef struct dpp_etm_qmu_qmu_int_mask4_t {
+	ZXIC_UINT32 qmu_int_mask4;
+} DPP_ETM_QMU_QMU_INT_MASK4_T;
+
+typedef struct dpp_etm_qmu_qmu_int_mask5_t {
+	ZXIC_UINT32 qmu_int_mask5;
+} DPP_ETM_QMU_QMU_INT_MASK5_T;
+
+typedef struct dpp_etm_qmu_qmu_int_mask6_t {
+	ZXIC_UINT32 qmu_int_mask6;
+} DPP_ETM_QMU_QMU_INT_MASK6_T;
+
+typedef struct dpp_etm_qmu_cmd_sch_cfgmt_fifo_state_t {
+	ZXIC_UINT32 nsop_fifo_parity_err;
+	ZXIC_UINT32 cmdsch_rd_cmd_fifo_parity_err;
+	ZXIC_UINT32 sop_fifo_afull;
+	ZXIC_UINT32 sop_fifo_empty;
+	ZXIC_UINT32 sop_fifo_overflow;
+	ZXIC_UINT32 sop_fifo_underflow;
+	ZXIC_UINT32 mmu_data_fifo_afull;
+	ZXIC_UINT32 mmu_data_fifo_empty;
+	ZXIC_UINT32 mmudat_fifo_overflow;
+	ZXIC_UINT32 mmudat_fifo_underflow;
+	ZXIC_UINT32 non_sop_fifo_afull;
+	ZXIC_UINT32 non_sop_fifo_empty;
+	ZXIC_UINT32 nsop_fifo_overflow;
+	ZXIC_UINT32 nsop_fifo_underflow;
+	ZXIC_UINT32 cmdsch_rd_cmd_fifo_afull;
+	ZXIC_UINT32 cmdsch_rd_cmd_fifo_empty;
+	ZXIC_UINT32 cmdsch_rd_cmd_fifo_overflow;
+	ZXIC_UINT32 cmdsch_rd_cmd_fifo_underflow;
+	ZXIC_UINT32 wlist_qnum_fifo_overflow;
+	ZXIC_UINT32 wlist_qnum_fifo_underflow;
+	ZXIC_UINT32 qsch_scan_fifo_overflow;
+	ZXIC_UINT32 qsch_scan_fifo_underflow;
+	ZXIC_UINT32 qsch_credit_fifo_overflow;
+	ZXIC_UINT32 qsch_credit_fifo_underflow;
+	ZXIC_UINT32 qsch_credit_fifo2_overflow;
+	ZXIC_UINT32 qsch_credit_fifo2_underflow;
+} DPP_ETM_QMU_CMD_SCH_CFGMT_FIFO_STATE_T;
+
+typedef struct dpp_etm_qmu_qlist_r_bcnt_t {
+	ZXIC_UINT32 qlist_r_bcnt;
+} DPP_ETM_QMU_QLIST_R_BCNT_T;
+
+typedef struct dpp_etm_qmu_qsch_rw_crbal_t {
+	ZXIC_UINT32 qsch_rw_crbal;
+} DPP_ETM_QMU_QSCH_RW_CRBAL_T;
+
+typedef struct dpp_etm_qmu_qsch_rw_crs_t {
+	ZXIC_UINT32 qsch_rw_crs;
+} DPP_ETM_QMU_QSCH_RW_CRS_T;
+
+typedef struct dpp_etm_qmu_qsch_r_wlist_empty_t {
+	ZXIC_UINT32 qsch_r_wlist_empty;
+} DPP_ETM_QMU_QSCH_R_WLIST_EMPTY_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_baram_rd_t {
+	ZXIC_UINT32 qcfg_qlist_baram_rd;
+} DPP_ETM_QMU_QCFG_QLIST_BARAM_RD_T;
+
+typedef struct dpp_etm_qmu_qcfg_qsch_crbal_fb_rw_t {
+	ZXIC_UINT32 qcfg_qlist_crbal_fb_rw;
+} DPP_ETM_QMU_QCFG_QSCH_CRBAL_FB_RW_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_grp0_bank_t {
+	ZXIC_UINT32 qcfg_qlist_grp0_bank_wr;
+} DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_grp1_bank_t {
+	ZXIC_UINT32 qcfg_qlist_grp1_bank_wr;
+} DPP_ETM_QMU_QCFG_QLIST_GRP1_BANK_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_grp2_bank_t {
+	ZXIC_UINT32 qcfg_qlist_grp2_bank_wr;
+} DPP_ETM_QMU_QCFG_QLIST_GRP2_BANK_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_grp3_bank_t {
+	ZXIC_UINT32 qcfg_qlist_grp3_bank_wr;
+} DPP_ETM_QMU_QCFG_QLIST_GRP3_BANK_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_grp4_bank_t {
+	ZXIC_UINT32 qcfg_qlist_grp4_bank_wr;
+} DPP_ETM_QMU_QCFG_QLIST_GRP4_BANK_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_grp5_bank_t {
+	ZXIC_UINT32 qcfg_qlist_grp5_bank_wr;
+} DPP_ETM_QMU_QCFG_QLIST_GRP5_BANK_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_grp6_bank_t {
+	ZXIC_UINT32 qcfg_qlist_grp6_bank_wr;
+} DPP_ETM_QMU_QCFG_QLIST_GRP6_BANK_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_grp7_bank_t {
+	ZXIC_UINT32 qcfg_qlist_grp7_bank_wr;
+} DPP_ETM_QMU_QCFG_QLIST_GRP7_BANK_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_grp_t {
+	ZXIC_UINT32 qcfg_qlist_grp_wr;
+} DPP_ETM_QMU_QCFG_QLIST_GRP_T;
+
+typedef struct dpp_etm_qmu_cfgmt_active_to_bank_cfg_t {
+	ZXIC_UINT32 cfgmt_active_to_bank_cfg;
+} DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T;
+
+typedef struct dpp_etm_qmu_cfgmt_ddr_in_mmu_cfg_t {
+	ZXIC_UINT32 cfgmt_ddr_in_mmu_cfg;
+} DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T;
+
+typedef struct dpp_etm_qmu_cfgmt_ddr_in_qmu_cfg_t {
+	ZXIC_UINT32 cfgmt_ddr_in_qmu_cfg;
+} DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T;
+
+typedef struct dpp_etm_qmu_cfgmt_bank_to_mmu_cfg_t {
+	ZXIC_UINT32 cfgmt_bank_in_mmu_cfg;
+} DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T;
+
+typedef struct dpp_etm_qmu_cfgmt_bank_to_qmu_cfg_t {
+	ZXIC_UINT32 cfgmt_bank_in_qmu_cfg;
+} DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T;
+
+typedef struct dpp_etm_qmu_cfgmt_grp_ram_n_clr_thd_t {
+	ZXIC_UINT32 cfgmt_grp_ram_n_clr_thd;
+} DPP_ETM_QMU_CFGMT_GRP_RAM_N_CLR_THD_T;
+
+typedef struct dpp_etm_qmu_cfgmt_age_pkt_num_t {
+	ZXIC_UINT32 cfgmt_age_pkt_num;
+} DPP_ETM_QMU_CFGMT_AGE_PKT_NUM_T;
+
+typedef struct dpp_etm_qmu_cfgmt_age_multi_interval_t {
+	ZXIC_UINT32 cfgmt_age_multi_interval;
+} DPP_ETM_QMU_CFGMT_AGE_MULTI_INTERVAL_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_pkt_age_en_t {
+	ZXIC_UINT32 cfgmt_qmu_pkt_age_en;
+} DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_EN_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_pkt_age_interval_t {
+	ZXIC_UINT32 cfgmt_qmu_pkt_age_interval;
+} DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_INTERVAL_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_pkt_age_start_end_t {
+	ZXIC_UINT32 cfgmt_qmu_pkt_age_end;
+	ZXIC_UINT32 cfgmt_qmu_pkt_age_start;
+} DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_START_END_T;
+
+typedef struct dpp_etm_qmu_cfgmt_pkt_age_req_aful_th_t {
+	ZXIC_UINT32 cfgmt_pkt_age_req_aful_th;
+} DPP_ETM_QMU_CFGMT_PKT_AGE_REQ_AFUL_TH_T;
+
+typedef struct dpp_etm_qmu_cfgmt_pkt_age_step_interval_t {
+	ZXIC_UINT32 cfgmt_pkt_age_step_interval;
+} DPP_ETM_QMU_CFGMT_PKT_AGE_STEP_INTERVAL_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_imem_age_mode_t {
+	ZXIC_UINT32 cfgmt_qmu_imem_age_en;
+	ZXIC_UINT32 cfgmt_qmu_imem_age_qlen_en;
+	ZXIC_UINT32 cfgmt_qmu_imem_age_time_en;
+} DPP_ETM_QMU_CFGMT_QMU_IMEM_AGE_MODE_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_imem_qlen_age_interval_t {
+	ZXIC_UINT32 cfgmt_qmu_imem_qlen_age_interval;
+} DPP_ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_INTERVAL_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_imem_time_age_interval_t {
+	ZXIC_UINT32 cfgmt_qmu_imem_time_age_interval;
+} DPP_ETM_QMU_CFGMT_QMU_IMEM_TIME_AGE_INTERVAL_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_imem_qlen_age_thd_t {
+	ZXIC_UINT32 cfgmt_qmu_imem_qlen_age_thd;
+} DPP_ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_THD_T;
+
+typedef struct dpp_etm_qmu_cfgmt_imem_age_step_interval_t {
+	ZXIC_UINT32 cfgmt_imem_age_step_interval;
+} DPP_ETM_QMU_CFGMT_IMEM_AGE_STEP_INTERVAL_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_ecc_bypass_read_t {
+	ZXIC_UINT32 cfgmt_qmu_ecc_bypass_read;
+} DPP_ETM_QMU_CFGMT_QMU_ECC_BYPASS_READ_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_resp_stat_fc_en_t {
+	ZXIC_UINT32 cfgmt_qmu_resp_stat_fc_en;
+} DPP_ETM_QMU_CFGMT_QMU_RESP_STAT_FC_EN_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_bank_xoff_pds_mode_t {
+	ZXIC_UINT32 cfgmt_qmu_bank_xoff_pds_mode;
+} DPP_ETM_QMU_CFGMT_QMU_BANK_XOFF_PDS_MODE_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_stat_offset_t {
+	ZXIC_UINT32 cfgmt_qmu_stat_offset;
+} DPP_ETM_QMU_CFGMT_QMU_STAT_OFFSET_T;
+
+typedef struct dpp_etm_qmu_fc_cnt_mode_t {
+	ZXIC_UINT32 fc_cnt_mode;
+} DPP_ETM_QMU_FC_CNT_MODE_T;
+
+typedef struct dpp_etm_qmu_mmu_qmu_wr_fc_cnt_t {
+	ZXIC_UINT32 mmu_qmu_wr_fc_cnt;
+} DPP_ETM_QMU_MMU_QMU_WR_FC_CNT_T;
+
+typedef struct dpp_etm_qmu_mmu_qmu_rd_fc_cnt_t {
+	ZXIC_UINT32 mmu_qmu_rd_fc_cnt;
+} DPP_ETM_QMU_MMU_QMU_RD_FC_CNT_T;
+
+typedef struct dpp_etm_qmu_qmu_cgavd_fc_cnt_t {
+	ZXIC_UINT32 qmu_cgavd_fc_cnt;
+} DPP_ETM_QMU_QMU_CGAVD_FC_CNT_T;
+
+typedef struct dpp_etm_qmu_cgavd_qmu_pkt_cnt_t {
+	ZXIC_UINT32 cgavd_qmu_pkt_cnt;
+} DPP_ETM_QMU_CGAVD_QMU_PKT_CNT_T;
+
+typedef struct dpp_etm_qmu_cgavd_qmu_pktlen_all_t {
+	ZXIC_UINT32 cgavd_qmu_pktlen_all;
+} DPP_ETM_QMU_CGAVD_QMU_PKTLEN_ALL_T;
+
+typedef struct dpp_etm_qmu_observe_portfc_spec_t {
+	ZXIC_UINT32 observe_portfc_spec;
+} DPP_ETM_QMU_OBSERVE_PORTFC_SPEC_T;
+
+typedef struct dpp_etm_qmu_spec_lif_portfc_count_t {
+	ZXIC_UINT32 spec_lif_portfc_count;
+} DPP_ETM_QMU_SPEC_LIF_PORTFC_COUNT_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_pfc_en_t {
+	ZXIC_UINT32 cfgmt_qmu_pfc_en;
+} DPP_ETM_QMU_CFGMT_QMU_PFC_EN_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_pfc_mask_1_t {
+	ZXIC_UINT32 cfgmt_qmu_pfc_mask_1;
+} DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_1_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_pfc_mask_2_t {
+	ZXIC_UINT32 cfgmt_qmu_pfc_mask_2;
+} DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_2_T;
+
+typedef struct dpp_etm_cfgmt_chip_version_reg_t {
+	ZXIC_UINT32 chip_version_reg;
+	ZXIC_UINT32 chip_sub_reg;
+	ZXIC_UINT32 chip_type_reg;
+} DPP_ETM_CFGMT_CHIP_VERSION_REG_T;
+
+typedef struct dpp_etm_cfgmt_chip_date_reg_t {
+	ZXIC_UINT32 chip_date_reg;
+} DPP_ETM_CFGMT_CHIP_DATE_REG_T;
+
+typedef struct dpp_etm_cfgmt_cfgmt_crc_en_t {
+	ZXIC_UINT32 cfgmt_crc_en;
+} DPP_ETM_CFGMT_CFGMT_CRC_EN_T;
+
+typedef struct dpp_etm_cfgmt_cfg_port_transfer_en_t {
+	ZXIC_UINT32 cfg_port_transfer_en;
+} DPP_ETM_CFGMT_CFG_PORT_TRANSFER_EN_T;
+
+typedef struct dpp_etm_cfgmt_tm_sa_work_mode_t {
+	ZXIC_UINT32 tm_sa_work_mode;
+} DPP_ETM_CFGMT_TM_SA_WORK_MODE_T;
+
+typedef struct dpp_etm_cfgmt_local_sa_id_t {
+	ZXIC_UINT32 local_sa_id;
+} DPP_ETM_CFGMT_LOCAL_SA_ID_T;
+
+typedef struct dpp_etm_olif_olif_rdy_t {
+	ZXIC_UINT32 cfgmt_block_mode;
+	ZXIC_UINT32 cfgmt_count_overflow_mode;
+	ZXIC_UINT32 cfgmt_count_rd_mode;
+	ZXIC_UINT32 olif_rdy;
+} DPP_ETM_OLIF_OLIF_RDY_T;
+
+typedef struct dpp_etm_olif_emem_prog_full_t {
+	ZXIC_UINT32 emem_prog_full_assert;
+	ZXIC_UINT32 emem_prog_full_negate;
+} DPP_ETM_OLIF_EMEM_PROG_FULL_T;
+
+typedef struct dpp_etm_olif_port_order_fifo_full_t {
+	ZXIC_UINT32 port_order_fifo_full_assert;
+	ZXIC_UINT32 port_order_fifo_full_negate;
+} DPP_ETM_OLIF_PORT_ORDER_FIFO_FULL_T;
+
+typedef struct dpp_etm_olif_olif_release_last_t {
+	ZXIC_UINT32 olif_release_last_addr;
+	ZXIC_UINT32 olif_release_last_bank;
+} DPP_ETM_OLIF_OLIF_RELEASE_LAST_T;
+
+typedef struct dpp_etm_olif_olif_fifo_empty_state_t {
+	ZXIC_UINT32 qmu_para_fifo_empty;
+	ZXIC_UINT32 emem_empty;
+	ZXIC_UINT32 imem_empty;
+} DPP_ETM_OLIF_OLIF_FIFO_EMPTY_STATE_T;
+
+typedef struct dpp_etm_olif_qmu_olif_release_fc_cnt_t {
+	ZXIC_UINT32 qmu_olif_release_fc_cnt;
+} DPP_ETM_OLIF_QMU_OLIF_RELEASE_FC_CNT_T;
+
+typedef struct dpp_etm_olif_olif_qmu_link_fc_cnt_t {
+	ZXIC_UINT32 olif_qmu_link_fc_cnt;
+} DPP_ETM_OLIF_OLIF_QMU_LINK_FC_CNT_T;
+
+typedef struct dpp_etm_olif_lif0_link_fc_cnt_t {
+	ZXIC_UINT32 lif0_link_fc_cnt;
+} DPP_ETM_OLIF_LIF0_LINK_FC_CNT_T;
+
+typedef struct dpp_etm_olif_olif_tmmu_fc_cnt_t {
+	ZXIC_UINT32 olif_tmmu_fc_cnt;
+} DPP_ETM_OLIF_OLIF_TMMU_FC_CNT_T;
+
+typedef struct dpp_etm_olif_olif_mmu_fc_cnt_t {
+	ZXIC_UINT32 olif_mmu_fc_cnt;
+} DPP_ETM_OLIF_OLIF_MMU_FC_CNT_T;
+
+typedef struct dpp_etm_olif_olif_qmu_port_rdy_h_t {
+	ZXIC_UINT32 olif_qmu_port_rdy_h;
+} DPP_ETM_OLIF_OLIF_QMU_PORT_RDY_H_T;
+
+typedef struct dpp_etm_olif_olif_qmu_port_rdy_l_t {
+	ZXIC_UINT32 olif_qmu_port_rdy_l;
+} DPP_ETM_OLIF_OLIF_QMU_PORT_RDY_L_T;
+
+typedef struct dpp_etm_olif_lif0_port_rdy_h_t {
+	ZXIC_UINT32 lif0_port_rdy_h;
+} DPP_ETM_OLIF_LIF0_PORT_RDY_H_T;
+
+typedef struct dpp_etm_olif_lif0_port_rdy_l_t {
+	ZXIC_UINT32 lif0_port_rdy_l;
+} DPP_ETM_OLIF_LIF0_PORT_RDY_L_T;
+
+typedef struct dpp_etm_olif_qmu_olif_rd_sop_cnt_t {
+	ZXIC_UINT32 qmu_olif_rd_sop_cnt;
+} DPP_ETM_OLIF_QMU_OLIF_RD_SOP_CNT_T;
+
+typedef struct dpp_etm_olif_qmu_olif_rd_eop_cnt_t {
+	ZXIC_UINT32 qmu_olif_rd_eop_cnt;
+} DPP_ETM_OLIF_QMU_OLIF_RD_EOP_CNT_T;
+
+typedef struct dpp_etm_olif_qmu_olif_rd_vld_cnt_t {
+	ZXIC_UINT32 qmu_olif_rd_vld_cnt;
+} DPP_ETM_OLIF_QMU_OLIF_RD_VLD_CNT_T;
+
+typedef struct dpp_etm_olif_qmu_olif_rd_blk_cnt_t {
+	ZXIC_UINT32 qmu_olif_rd_blk_cnt;
+} DPP_ETM_OLIF_QMU_OLIF_RD_BLK_CNT_T;
+
+typedef struct dpp_etm_olif_mmu_tm_data_sop_cnt_t {
+	ZXIC_UINT32 mmu_tm_data_sop_cnt;
+} DPP_ETM_OLIF_MMU_TM_DATA_SOP_CNT_T;
+
+typedef struct dpp_etm_olif_mmu_tm_data_eop_cnt_t {
+	ZXIC_UINT32 mmu_tm_data_eop_cnt;
+} DPP_ETM_OLIF_MMU_TM_DATA_EOP_CNT_T;
+
+typedef struct dpp_etm_olif_mmu_tm_data_vld_cnt_t {
+	ZXIC_UINT32 mmu_tm_data_vld_cnt;
+} DPP_ETM_OLIF_MMU_TM_DATA_VLD_CNT_T;
+
+typedef struct dpp_etm_olif_odma_tm_data_sop_cnt_t {
+	ZXIC_UINT32 odma_tm_data_sop_cnt;
+} DPP_ETM_OLIF_ODMA_TM_DATA_SOP_CNT_T;
+
+typedef struct dpp_etm_olif_odma_tm_data_eop_cnt_t {
+	ZXIC_UINT32 odma_tm_data_eop_cnt;
+} DPP_ETM_OLIF_ODMA_TM_DATA_EOP_CNT_T;
+
+typedef struct dpp_etm_olif_odma_tm_deq_vld_cnt_t {
+	ZXIC_UINT32 odma_tm_deq_vld_cnt;
+} DPP_ETM_OLIF_ODMA_TM_DEQ_VLD_CNT_T;
+
+typedef struct dpp_etm_olif_olif_qmu_release_vld_cnt_t {
+	ZXIC_UINT32 olif_qmu_release_vld_cnt;
+} DPP_ETM_OLIF_OLIF_QMU_RELEASE_VLD_CNT_T;
+
+typedef struct dpp_etm_olif_emem_dat_vld_cnt_t {
+	ZXIC_UINT32 emem_dat_vld_cnt;
+} DPP_ETM_OLIF_EMEM_DAT_VLD_CNT_T;
+
+typedef struct dpp_etm_olif_imem_dat_vld_cnt_t {
+	ZXIC_UINT32 imem_dat_vld_cnt;
+} DPP_ETM_OLIF_IMEM_DAT_VLD_CNT_T;
+
+typedef struct dpp_etm_olif_emem_dat_rd_cnt_t {
+	ZXIC_UINT32 emem_dat_rd_cnt;
+} DPP_ETM_OLIF_EMEM_DAT_RD_CNT_T;
+
+typedef struct dpp_etm_olif_imem_dat_rd_cnt_t {
+	ZXIC_UINT32 imem_dat_rd_cnt;
+} DPP_ETM_OLIF_IMEM_DAT_RD_CNT_T;
+
+typedef struct dpp_etm_olif_qmu_olif_rd_sop_emem_cnt_t {
+	ZXIC_UINT32 qmu_olif_rd_sop_emem_cnt;
+} DPP_ETM_OLIF_QMU_OLIF_RD_SOP_EMEM_CNT_T;
+
+typedef struct dpp_etm_olif_qmu_olif_rd_vld_emem_cnt_t {
+	ZXIC_UINT32 qmu_olif_rd_vld_emem_cnt;
+} DPP_ETM_OLIF_QMU_OLIF_RD_VLD_EMEM_CNT_T;
+
+typedef struct dpp_etm_olif_cpu_last_wr_addr_t {
+	ZXIC_UINT32 cpu_last_wr_addr;
+} DPP_ETM_OLIF_CPU_LAST_WR_ADDR_T;
+
+typedef struct dpp_etm_olif_cpu_last_wr_data_t {
+	ZXIC_UINT32 cpu_last_wr_data;
+} DPP_ETM_OLIF_CPU_LAST_WR_DATA_T;
+
+typedef struct dpp_etm_olif_cpu_last_rd_addr_t {
+	ZXIC_UINT32 cpu_last_rd_addr;
+} DPP_ETM_OLIF_CPU_LAST_RD_ADDR_T;
+
+typedef struct dpp_etm_olif_qmu_olif_last_port_t {
+	ZXIC_UINT32 qmu_olif_last_port;
+} DPP_ETM_OLIF_QMU_OLIF_LAST_PORT_T;
+
+typedef struct dpp_etm_olif_qmu_olif_last_addr_t {
+	ZXIC_UINT32 qmu_olif_last_addr;
+} DPP_ETM_OLIF_QMU_OLIF_LAST_ADDR_T;
+
+typedef struct dpp_etm_olif_qmu_olif_last_bank_t {
+	ZXIC_UINT32 qmu_olif_last_bank;
+} DPP_ETM_OLIF_QMU_OLIF_LAST_BANK_T;
+
+typedef struct dpp_etm_olif_tm_lif_byte_stat_t {
+	ZXIC_UINT32 tm_lif_byte_stat;
+} DPP_ETM_OLIF_TM_LIF_BYTE_STAT_T;
+
+typedef struct dpp_etm_olif_tm_lif_err_stat_t {
+	ZXIC_UINT32 tm_lif_err_stat;
+} DPP_ETM_OLIF_TM_LIF_ERR_STAT_T;
+
+typedef struct dpp_etm_cgavd_port_share_cnt_t {
+	ZXIC_UINT32 port_share_cnt;
+} DPP_ETM_CGAVD_PORT_SHARE_CNT_T;
+
+typedef struct dpp_etm_cgavd_total_imem_cnt_t {
+	ZXIC_UINT32 total_imem_cnt;
+} DPP_ETM_CGAVD_TOTAL_IMEM_CNT_T;
+
+typedef struct dpp_etm_cgavd_pp_q_len_t {
+	ZXIC_UINT32 pp_q_len;
+} DPP_ETM_CGAVD_PP_Q_LEN_T;
+
+typedef struct dpp_etm_cgavd_sys_q_len_t {
+	ZXIC_UINT32 sys_q_len;
+} DPP_ETM_CGAVD_SYS_Q_LEN_T;
+
+typedef struct dpp_etm_cgavd_cgavd_cfg_error_warning_t {
+	ZXIC_UINT32 error_correction_11;
+	ZXIC_UINT32 error_correction_10;
+	ZXIC_UINT32 error_correction_9;
+	ZXIC_UINT32 error_correction_8;
+	ZXIC_UINT32 error_correction_7;
+	ZXIC_UINT32 error_correction_6;
+	ZXIC_UINT32 error_correction5;
+	ZXIC_UINT32 error_correction_4;
+	ZXIC_UINT32 error_correction_3;
+	ZXIC_UINT32 error_correction_2;
+	ZXIC_UINT32 error_correction_1;
+	ZXIC_UINT32 error_correction_0;
+} DPP_ETM_CGAVD_CGAVD_CFG_ERROR_WARNING_T;
+
+typedef struct dpp_etm_cgavd_mult_qlen_th_en_t {
+	ZXIC_UINT32 mult_qlen_th;
+} DPP_ETM_CGAVD_MULT_QLEN_TH_EN_T;
+
+typedef struct dpp_etm_cgavd_mult_qlen_th_t {
+	ZXIC_UINT32 mult_qlen_th;
+} DPP_ETM_CGAVD_MULT_QLEN_TH_T;
+
+typedef struct dpp_etm_cgavd_cgavd_cfg_move_t {
+	ZXIC_UINT32 cfgmt_sys_move_en;
+	ZXIC_UINT32 cfgmt_port_move_en;
+	ZXIC_UINT32 cfgmt_flow_move_en;
+} DPP_ETM_CGAVD_CGAVD_CFG_MOVE_T;
+
+typedef struct dpp_etm_cgavd_cfgmt_total_th_t {
+	ZXIC_UINT32 cfgmt_total_th;
+} DPP_ETM_CGAVD_CFGMT_TOTAL_TH_T;
+
+typedef struct dpp_etm_cgavd_cfgmt_port_share_th_t {
+	ZXIC_UINT32 cfgmt_port_share_th;
+} DPP_ETM_CGAVD_CFGMT_PORT_SHARE_TH_T;
+
+typedef struct dpp_etm_cgavd_sa_unreach_state_t {
+	ZXIC_UINT32 sa_unreach_state;
+} DPP_ETM_CGAVD_SA_UNREACH_STATE_T;
+
+typedef struct dpp_etm_cgavd_mv_port_th_t {
+	ZXIC_UINT32 port_th;
+} DPP_ETM_CGAVD_MV_PORT_TH_T;
+
+typedef struct dpp_etm_cgavd_mv_drop_sp_th_t {
+	ZXIC_UINT32 mvdrop_sp_th;
+} DPP_ETM_CGAVD_MV_DROP_SP_TH_T;
+
+typedef struct dpp_etm_cgavd_cgavd_state_warning_t {
+	ZXIC_UINT32 deq_q_num_warning;
+	ZXIC_UINT32 deq_pkt_len_warning;
+	ZXIC_UINT32 enq_pkt_dp_warning;
+	ZXIC_UINT32 unenq_q_num_warning;
+	ZXIC_UINT32 enq_q_num_warning;
+	ZXIC_UINT32 enq_pkt_len_warning;
+} DPP_ETM_CGAVD_CGAVD_STATE_WARNING_T;
+
+typedef struct dpp_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_t {
+	ZXIC_UINT32 tmmu_cgavd_dma_fifo_cnt;
+} DPP_ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNT_T;
+
+typedef struct dpp_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_max_t {
+	ZXIC_UINT32 tmmu_cgavd_dma_fifo_cnt_max;
+} DPP_ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNT_MAX_T;
+
+typedef struct dpp_etm_cgavd_imem_total_cnt_t {
+	ZXIC_UINT32 imem_total_cnt;
+} DPP_ETM_CGAVD_IMEM_TOTAL_CNT_T;
+
+typedef struct dpp_etm_cgavd_imem_total_cnt_max_t {
+	ZXIC_UINT32 imem_total_cnt_max;
+} DPP_ETM_CGAVD_IMEM_TOTAL_CNT_MAX_T;
+
+typedef struct dpp_etm_cgavd_flow0_omem_cnt_t {
+	ZXIC_UINT32 flow0_omem_cnt;
+} DPP_ETM_CGAVD_FLOW0_OMEM_CNT_T;
+
+typedef struct dpp_etm_cgavd_flow1_omem_cnt_t {
+	ZXIC_UINT32 flow1_omem_cnt;
+} DPP_ETM_CGAVD_FLOW1_OMEM_CNT_T;
+
+typedef struct dpp_etm_cgavd_flow2_omem_cnt_t {
+	ZXIC_UINT32 flow2_omem_cnt;
+} DPP_ETM_CGAVD_FLOW2_OMEM_CNT_T;
+
+typedef struct dpp_etm_cgavd_flow3_omem_cnt_t {
+	ZXIC_UINT32 flow3_omem_cnt;
+} DPP_ETM_CGAVD_FLOW3_OMEM_CNT_T;
+
+typedef struct dpp_etm_cgavd_flow4_omem_cnt_t {
+	ZXIC_UINT32 flow4_omem_cnt;
+} DPP_ETM_CGAVD_FLOW4_OMEM_CNT_T;
+
+typedef struct dpp_etm_cgavd_appoint_flow_num_message_1_t {
+	ZXIC_UINT32 appoint_flow_num_en_1;
+	ZXIC_UINT32 appoint_flow_num_1;
+} DPP_ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_1_T;
+
+typedef struct dpp_etm_cgavd_appoint_flow_num_message_2_t {
+	ZXIC_UINT32 appoint_flow_num_en_2;
+	ZXIC_UINT32 appoint_flow_num_2;
+} DPP_ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_2_T;
+
+typedef struct dpp_etm_cgavd_odma_cgavd_pkt_num_1_t {
+	ZXIC_UINT32 odma_cgavd_pkt_num_1;
+} DPP_ETM_CGAVD_ODMA_CGAVD_PKT_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_odma_cgavd_byte_num_1_t {
+	ZXIC_UINT32 odma_cgavd_byte_num_1;
+} DPP_ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_enqueue_pkt_num_1_t {
+	ZXIC_UINT32 cgavd_enqueue_pkt_num_1;
+} DPP_ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_dequeue_pkt_num_1_t {
+	ZXIC_UINT32 cgavd_dequeue_pkt_num_1;
+} DPP_ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_imem_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_pkt_imem_num_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_omem_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_pkt_omem_num_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_byte_imem_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_byte_imem_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_byte_omem_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_byte_omem_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_drop_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_pkt_drop_num_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_byte_drop_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_byte_drop_num_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_forbid_drop_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_forbid_drop_num_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_flow_td_drop_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_flow_td_drop_num_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_flow_wred_drop_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_flow_wred_drop_num_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_flow_wred_dp_drop_num1;
+} DPP_ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_pp_td_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_pp_td_num_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_pp_wred_drop_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_pp_wred_drop_num_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_pp_wred_dp_drop_num1;
+} DPP_ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_sys_td_drop_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_sys_td_drop_num_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_sys_gred_drop_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_sys_gred_drop_num_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num1_t {
+	ZXIC_UINT32 cgavd_qmu_sys_gred_dp_drop_num1;
+} DPP_ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_sa_drop_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_sa_drop_num_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_move_drop_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_move_drop_num_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_tm_mult_drop_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_tm_mult_drop_num_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_tm_error_drop_num_1_t {
+	ZXIC_UINT32 cgavd_qmu_tm_error_drop_num_1;
+} DPP_ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_1_T;
+
+typedef struct dpp_etm_cgavd_odma_cgavd_pkt_num_2_t {
+	ZXIC_UINT32 odma_cgavd_pkt_num_2;
+} DPP_ETM_CGAVD_ODMA_CGAVD_PKT_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_odma_cgavd_byte_num_2_t {
+	ZXIC_UINT32 odma_cgavd_byte_num_2;
+} DPP_ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_enqueue_pkt_num_2_t {
+	ZXIC_UINT32 cgavd_enqueue_pkt_num_2;
+} DPP_ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_dequeue_pkt_num_2_t {
+	ZXIC_UINT32 cgavd_dequeue_pkt_num_2;
+} DPP_ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_imem_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_pkt_imem_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_omem_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_pkt_omem_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_byte_imem_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_byte_imem_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_byte_omem_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_byte_omem_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_pkt_drop_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_pkt_drop_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_byte_drop_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_byte_drop_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_forbid_drop_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_forbid_drop_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_flow_td_drop_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_flow_td_drop_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_flow_wred_drop_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_flow_wred_drop_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_flow_wred_dp_drop_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_pp_td_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_pp_td_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_pp_wred_drop_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_pp_wred_drop_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_pp_wred_dp_drop_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_sys_td_drop_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_sys_td_drop_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_sys_gred_drop_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_sys_gred_drop_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_sys_gred_dp_drop_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_sa_drop_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_sa_drop_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_move_drop_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_move_drop_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_tm_mult_drop_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_tm_mult_drop_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_cgavd_qmu_tm_error_drop_num_2_t {
+	ZXIC_UINT32 cgavd_qmu_tm_error_drop_num_2;
+} DPP_ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_2_T;
+
+typedef struct dpp_etm_cgavd_move_flow_th_profile_t {
+	ZXIC_UINT32 move_drop_profile;
+} DPP_ETM_CGAVD_MOVE_FLOW_TH_PROFILE_T;
+
+typedef struct dpp_etm_cgavd_move_flow_th_t {
+	ZXIC_UINT32 move_drop_flow_th;
+} DPP_ETM_CGAVD_MOVE_FLOW_TH_T;
+
+typedef struct dpp_etm_tmmu_emem_pd_fifo_aful_th_t {
+	ZXIC_UINT32 emem_pd_fifo_aful_th;
+} DPP_ETM_TMMU_EMEM_PD_FIFO_AFUL_TH_T;
+
+typedef struct dpp_etm_tmmu_dma_data_fifo_aful_th_t {
+	ZXIC_UINT32 dma_data_fifo_aful_th;
+} DPP_ETM_TMMU_DMA_DATA_FIFO_AFUL_TH_T;
+
+typedef struct dpp_etm_tmmu_tmmu_states_0_t {
+	ZXIC_UINT32 tm_odma_pkt_rdy;
+	ZXIC_UINT32 dma_data_fifo_empty;
+	ZXIC_UINT32 imem_enq_rd_fifo_empty;
+	ZXIC_UINT32 imem_enq_drop_fifo_empty;
+	ZXIC_UINT32 imem_deq_rd_fifo_empty;
+	ZXIC_UINT32 imem_deq_drop_fifo_empty;
+	ZXIC_UINT32 wr_cmd_fifo_empty;
+	ZXIC_UINT32 cached_pd_fifo_empty;
+	ZXIC_UINT32 emem_pd_fifo_empty;
+	ZXIC_UINT32 pd_order_fifo_empty;
+	ZXIC_UINT32 odma_tm_data_rdy;
+	ZXIC_UINT32 odma_tm_discard_rdy;
+	ZXIC_UINT32 olif_tmmu_rdy;
+	ZXIC_UINT32 mmu_tm_cmd_wr_rdy;
+	ZXIC_UINT32 mmu_tm_data_wr_rdy;
+	ZXIC_UINT32 mmu_tm_rd_rdy;
+	ZXIC_UINT32 mmu_tm_sop_rd_rdy;
+	ZXIC_UINT32 qmu_tmmu_sop_data_rdy;
+	ZXIC_UINT32 tmmu_cmdsw_imem_release_rdy;
+	ZXIC_UINT32 imem_age_release_rdy;
+	ZXIC_UINT32 tmmu_qmu_wr_rdy;
+	ZXIC_UINT32 tmmu_qmu_rdy_7;
+	ZXIC_UINT32 tmmu_qmu_rdy_6;
+	ZXIC_UINT32 tmmu_qmu_rdy_5;
+	ZXIC_UINT32 tmmu_qmu_rdy_4;
+	ZXIC_UINT32 tmmu_qmu_rdy_3;
+	ZXIC_UINT32 tmmu_qmu_rdy_2;
+	ZXIC_UINT32 tmmu_qmu_rdy_1;
+	ZXIC_UINT32 tmmu_qmu_rdy_0;
+	ZXIC_UINT32 tmmu_qmu_rd_rdy;
+	ZXIC_UINT32 tmmu_qmu_sop_rd_rdy;
+} DPP_ETM_TMMU_TMMU_STATES_0_T;
+
+typedef struct dpp_etm_tmmu_qmu_tmmu_wr_sop_cnt_t {
+	ZXIC_UINT32 qmu_tmmu_wr_sop_cnt;
+} DPP_ETM_TMMU_QMU_TMMU_WR_SOP_CNT_T;
+
+typedef struct dpp_etm_tmmu_qmu_tmmu_wr_eop_cnt_t {
+	ZXIC_UINT32 qmu_tmmu_wr_eop_cnt;
+} DPP_ETM_TMMU_QMU_TMMU_WR_EOP_CNT_T;
+
+typedef struct dpp_etm_tmmu_qmu_tmmu_wr_drop_cnt_t {
+	ZXIC_UINT32 qmu_tmmu_wr_drop_cnt;
+} DPP_ETM_TMMU_QMU_TMMU_WR_DROP_CNT_T;
+
+typedef struct dpp_etm_tmmu_qmu_tmmu_wr_emem_cnt_t {
+	ZXIC_UINT32 qmu_tmmu_wr_emem_cnt;
+} DPP_ETM_TMMU_QMU_TMMU_WR_EMEM_CNT_T;
+
+typedef struct dpp_etm_tmmu_qmu_tmmu_wr_imem_cnt_t {
+	ZXIC_UINT32 qmu_tmmu_wr_imem_cnt;
+} DPP_ETM_TMMU_QMU_TMMU_WR_IMEM_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_mmu_wr_sop_cnt_t {
+	ZXIC_UINT32 tmmu_mmu_wr_sop_cnt;
+} DPP_ETM_TMMU_TMMU_MMU_WR_SOP_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_mmu_wr_eop_cnt_t {
+	ZXIC_UINT32 tmmu_mmu_wr_eop_cnt;
+} DPP_ETM_TMMU_TMMU_MMU_WR_EOP_CNT_T;
+
+typedef struct dpp_etm_tmmu_qmu_tmmu_rd_sop_cnt_t {
+	ZXIC_UINT32 qmu_tmmu_rd_sop_cnt;
+} DPP_ETM_TMMU_QMU_TMMU_RD_SOP_CNT_T;
+
+typedef struct dpp_etm_tmmu_qmu_tmmu_rd_eop_cnt_t {
+	ZXIC_UINT32 qmu_tmmu_rd_eop_cnt;
+} DPP_ETM_TMMU_QMU_TMMU_RD_EOP_CNT_T;
+
+typedef struct dpp_etm_tmmu_qmu_tmmu_rd_drop_cnt_t {
+	ZXIC_UINT32 qmu_tmmu_rd_drop_cnt;
+} DPP_ETM_TMMU_QMU_TMMU_RD_DROP_CNT_T;
+
+typedef struct dpp_etm_tmmu_qmu_tmmu_rd_emem_cnt_t {
+	ZXIC_UINT32 qmu_tmmu_rd_emem_cnt;
+} DPP_ETM_TMMU_QMU_TMMU_RD_EMEM_CNT_T;
+
+typedef struct dpp_etm_tmmu_qmu_tmmu_rd_imem_cnt_t {
+	ZXIC_UINT32 qmu_tmmu_rd_imem_cnt;
+} DPP_ETM_TMMU_QMU_TMMU_RD_IMEM_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_mmu_rd_sop_cnt_t {
+	ZXIC_UINT32 tmmu_mmu_rd_sop_cnt;
+} DPP_ETM_TMMU_TMMU_MMU_RD_SOP_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_mmu_rd_eop_cnt_t {
+	ZXIC_UINT32 tmmu_mmu_rd_eop_cnt;
+} DPP_ETM_TMMU_TMMU_MMU_RD_EOP_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_odma_in_sop_cnt_t {
+	ZXIC_UINT32 tmmu_odma_in_sop_cnt;
+} DPP_ETM_TMMU_TMMU_ODMA_IN_SOP_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_odma_in_eop_cnt_t {
+	ZXIC_UINT32 tmmu_odma_in_eop_cnt;
+} DPP_ETM_TMMU_TMMU_ODMA_IN_EOP_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_odma_vld_cnt_t {
+	ZXIC_UINT32 tmmu_odma_vld_cnt;
+} DPP_ETM_TMMU_TMMU_ODMA_VLD_CNT_T;
+
+typedef struct dpp_etm_tmmu_qmu_pd_in_cnt_t {
+	ZXIC_UINT32 qmu_pd_in_cnt;
+} DPP_ETM_TMMU_QMU_PD_IN_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_pd_hit_cnt_t {
+	ZXIC_UINT32 tmmu_pd_hit_cnt;
+} DPP_ETM_TMMU_TMMU_PD_HIT_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_pd_out_cnt_t {
+	ZXIC_UINT32 tmmu_pd_out_cnt;
+} DPP_ETM_TMMU_TMMU_PD_OUT_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_wr_cmd_fifo_wr_cnt_t {
+	ZXIC_UINT32 tmmu_wr_cmd_fifo_wr_cnt;
+} DPP_ETM_TMMU_TMMU_WR_CMD_FIFO_WR_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_imem_age_cnt_t {
+	ZXIC_UINT32 tmmu_imem_age_cnt;
+} DPP_ETM_TMMU_TMMU_IMEM_AGE_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_cmdsch_rd_cnt_t {
+	ZXIC_UINT32 tmmu_cmdsch_rd_cnt;
+} DPP_ETM_TMMU_TMMU_CMDSCH_RD_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_cmdsch_drop_cnt_t {
+	ZXIC_UINT32 tmmu_cmdsch_drop_cnt;
+} DPP_ETM_TMMU_TMMU_CMDSCH_DROP_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_cmdsw_drop_cnt_t {
+	ZXIC_UINT32 tmmu_cmdsw_drop_cnt;
+} DPP_ETM_TMMU_TMMU_CMDSW_DROP_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_odma_enq_rd_cnt_t {
+	ZXIC_UINT32 tmmu_odma_enq_rd_cnt;
+} DPP_ETM_TMMU_TMMU_ODMA_ENQ_RD_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_odma_enq_drop_cnt_t {
+	ZXIC_UINT32 tmmu_odma_enq_drop_cnt;
+} DPP_ETM_TMMU_TMMU_ODMA_ENQ_DROP_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_odma_imem_age_cnt_t {
+	ZXIC_UINT32 tmmu_odma_imem_age_cnt;
+} DPP_ETM_TMMU_TMMU_ODMA_IMEM_AGE_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_odma_deq_rd_cnt_t {
+	ZXIC_UINT32 tmmu_odma_deq_rd_cnt;
+} DPP_ETM_TMMU_TMMU_ODMA_DEQ_RD_CNT_T;
+
+typedef struct dpp_etm_tmmu_tmmu_odma_deq_drop_cnt_t {
+	ZXIC_UINT32 tmmu_odma_deq_drop_cnt;
+} DPP_ETM_TMMU_TMMU_ODMA_DEQ_DROP_CNT_T;
+
+typedef struct dpp_etm_tmmu_olif_tmmu_xoff_cnt_t {
+	ZXIC_UINT32 olif_tmmu_xoff_cnt;
+} DPP_ETM_TMMU_OLIF_TMMU_XOFF_CNT_T;
+
+typedef struct dpp_etm_tmmu_odma_tm_data_xoff_cnt_t {
+	ZXIC_UINT32 odma_tm_data_xoff_cnt;
+} DPP_ETM_TMMU_ODMA_TM_DATA_XOFF_CNT_T;
+
+typedef struct dpp_etm_tmmu_tm_odma_pkt_xoff_cnt_t {
+	ZXIC_UINT32 tm_odma_pkt_xoff_cnt;
+} DPP_ETM_TMMU_TM_ODMA_PKT_XOFF_CNT_T;
+
+typedef struct dpp_etm_tmmu_tm_state_3_t {
+	ZXIC_UINT32 tmmu_qmu_rdy_9;
+	ZXIC_UINT32 tmmu_qmu_rdy_8;
+} DPP_ETM_TMMU_TM_STATE_3_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_pd_cache_cmd_t {
+	ZXIC_UINT32 cfgmt_pd_cache_addr;
+} DPP_ETM_TMMU_CFGMT_PD_CACHE_CMD_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_pd_cache_rd_done_t {
+	ZXIC_UINT32 cfgmt_pd_cache_rd_done;
+} DPP_ETM_TMMU_CFGMT_PD_CACHE_RD_DONE_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_pd_cache_rd_data_0_t {
+	ZXIC_UINT32 cfgmt_pd_cache_rd_data_0;
+} DPP_ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_0_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_pd_cache_rd_data_1_t {
+	ZXIC_UINT32 cfgmt_pd_cache_rd_data_1;
+} DPP_ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_1_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_pd_cache_rd_data_2_t {
+	ZXIC_UINT32 cfgmt_pd_cache_rd_data_2;
+} DPP_ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_2_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_pd_cache_rd_data_3_t {
+	ZXIC_UINT32 cfgmt_pd_cache_rd_data_3;
+} DPP_ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_3_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_tmmu_to_odma_para_t {
+	ZXIC_UINT32 cfgmt_tmmu_to_odma_para;
+} DPP_ETM_TMMU_CFGMT_TMMU_TO_ODMA_PARA_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_dma_data_fifo_cnt_t {
+	ZXIC_UINT32 cfgmt_dma_data_fifo_cnt;
+} DPP_ETM_TMMU_CFGMT_DMA_DATA_FIFO_CNT_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit0_offset_t {
+	ZXIC_UINT32 cfgmt_cache_tag_bit0_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT0_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit1_offset_t {
+	ZXIC_UINT32 cfgmt_cache_tag_bit1_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT1_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit2_offset_t {
+	ZXIC_UINT32 cfgmt_cache_tag_bit2_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT2_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit3_offset_t {
+	ZXIC_UINT32 cfgmt_cache_tag_bit3_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT3_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit4_offset_t {
+	ZXIC_UINT32 cfgmt_cache_tag_bit4_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT4_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_tag_bit5_offset_t {
+	ZXIC_UINT32 cfgmt_cache_tag_bit5_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_TAG_BIT5_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit0_offset_t {
+	ZXIC_UINT32 cfgmt_cache_index_bit0_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT0_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit1_offset_t {
+	ZXIC_UINT32 cfgmt_cache_index_bit1_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT1_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit2_offset_t {
+	ZXIC_UINT32 cfgmt_cache_index_bit2_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT2_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit3_offset_t {
+	ZXIC_UINT32 cfgmt_cache_index_bit3_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT3_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit4_offset_t {
+	ZXIC_UINT32 cfgmt_cache_index_bit4_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT4_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit5_offset_t {
+	ZXIC_UINT32 cfgmt_cache_index_bit5_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT5_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit6_offset_t {
+	ZXIC_UINT32 cfgmt_cache_index_bit6_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT6_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit7_offset_t {
+	ZXIC_UINT32 cfgmt_cache_index_bit7_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT7_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit8_offset_t {
+	ZXIC_UINT32 cfgmt_cache_index_bit8_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT8_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit9_offset_t {
+	ZXIC_UINT32 cfgmt_cache_index_bit9_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT9_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit10_offset_t {
+	ZXIC_UINT32 cfgmt_cache_index_bit10_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT10_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit11_offset_t {
+	ZXIC_UINT32 cfgmt_cache_index_bit11_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT11_OFFSET_T;
+
+typedef struct dpp_etm_tmmu_cfgmt_cache_index_bit12_offset_t {
+	ZXIC_UINT32 cfgmt_cache_index_bit12_offset;
+} DPP_ETM_TMMU_CFGMT_CACHE_INDEX_BIT12_OFFSET_T;
+
+typedef struct dpp_etm_shap_bktfull_fifo_full_flagregister_t {
+	ZXIC_UINT32 bktfull_fifo_full_flag_core;
+} DPP_ETM_SHAP_BKTFULL_FIFO_FULL_FLAGREGISTER_T;
+
+typedef struct dpp_etm_shap_fifo_full_regregister_t {
+	ZXIC_UINT32 fifo_full_reg;
+} DPP_ETM_SHAP_FIFO_FULL_REGREGISTER_T;
+
+typedef struct dpp_etm_shap_fifo_empty_regregister_t {
+	ZXIC_UINT32 fifo_empty_reg;
+} DPP_ETM_SHAP_FIFO_EMPTY_REGREGISTER_T;
+
+typedef struct dpp_etm_shap_fifo_almost_full_regregister_t {
+	ZXIC_UINT32 fifo_almost_full_reg;
+} DPP_ETM_SHAP_FIFO_ALMOST_FULL_REGREGISTER_T;
+
+typedef struct dpp_etm_shap_fifo_almost_empty_regregister_t {
+	ZXIC_UINT32 fifo_almost_empty_reg;
+} DPP_ETM_SHAP_FIFO_ALMOST_EMPTY_REGREGISTER_T;
+
+typedef struct dpp_etm_crdt_credit_space_select_t {
+	ZXIC_UINT32 credit_space_select;
+} DPP_ETM_CRDT_CREDIT_SPACE_SELECT_T;
+
+typedef struct dpp_etm_crdt_stat_space_max_t {
+	ZXIC_UINT32 stat_space_max;
+} DPP_ETM_CRDT_STAT_SPACE_MAX_T;
+
+typedef struct dpp_etm_crdt_stat_space_min_t {
+	ZXIC_UINT32 stat_space_min;
+} DPP_ETM_CRDT_STAT_SPACE_MIN_T;
+
+typedef struct dpp_etm_crdt_stat_space_credit_t {
+	ZXIC_UINT32 stat_space_credit;
+} DPP_ETM_CRDT_STAT_SPACE_CREDIT_T;
+
+typedef struct dpp_etm_crdt_stat_que_step8_credit_t {
+	ZXIC_UINT32 stat_que_step8_credit;
+} DPP_ETM_CRDT_STAT_QUE_STEP8_CREDIT_T;
+
+typedef struct dpp_etm_crdt_special_que_t {
+	ZXIC_UINT32 special_que_id;
+} DPP_ETM_CRDT_SPECIAL_QUE_T;
+
+typedef struct dpp_etm_crdt_special_que_credit_t {
+	ZXIC_UINT32 special_que_credit;
+} DPP_ETM_CRDT_SPECIAL_QUE_CREDIT_T;
+
+typedef struct dpp_etm_crdt_lif_congest_credit_cnt_t {
+	ZXIC_UINT32 lif_congest_credit_cnt;
+} DPP_ETM_CRDT_LIF_CONGEST_CREDIT_CNT_T;
+
+typedef struct dpp_etm_crdt_lif_port_congest_credit_cnt_t {
+	ZXIC_UINT32 lif_port_congest_credit_cnt;
+} DPP_ETM_CRDT_LIF_PORT_CONGEST_CREDIT_CNT_T;
+
+typedef struct dpp_etm_crdt_crdt_congest_credit_cnt_t {
+	ZXIC_UINT32 crdt_congest_credit_cnt;
+} DPP_ETM_CRDT_CRDT_CONGEST_CREDIT_CNT_T;
+
+typedef struct dpp_etm_crdt_crdt_port_congest_credit_cnt_t {
+	ZXIC_UINT32 crdt_port_congest_credit_cnt;
+} DPP_ETM_CRDT_CRDT_PORT_CONGEST_CREDIT_CNT_T;
+
+typedef struct dpp_etm_crdt_congest_port_id_t {
+	ZXIC_UINT32 congest_port_id;
+} DPP_ETM_CRDT_CONGEST_PORT_ID_T;
+
+typedef struct dpp_etm_crdt_dev_link_control_t {
+	ZXIC_UINT32 dev_link_control;
+} DPP_ETM_CRDT_DEV_LINK_CONTROL_T;
+
+typedef struct dpp_etm_crdt_crdt_sa_port_rdy_t {
+	ZXIC_UINT32 crdt_sa_port_rdy;
+} DPP_ETM_CRDT_CRDT_SA_PORT_RDY_T;
+
+typedef struct dpp_etm_crdt_crdt_congest_mode_select_t {
+	ZXIC_UINT32 crdt_congest_mode_selectr;
+} DPP_ETM_CRDT_CRDT_CONGEST_MODE_SELECT_T;
+
+typedef struct dpp_etm_crdt_fifo_out_all_crs_normal_cnt_t {
+	ZXIC_UINT32 fifo_out_all_crs_normal_cnt;
+} DPP_ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNT_T;
+
+typedef struct dpp_etm_crdt_fifo_out_all_crs_off_cnt_t {
+	ZXIC_UINT32 fifo_out_all_crs_off_cnt;
+} DPP_ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNT_T;
+
+typedef struct dpp_etm_crdt_fifo_out_que_crs_normal_cnt_t {
+	ZXIC_UINT32 fifo_out_que_crs_normal_cnt;
+} DPP_ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNT_T;
+
+typedef struct dpp_etm_crdt_fifo_out_que_crs_off_cnt_t {
+	ZXIC_UINT32 fifo_out_que_crs_off_cnt;
+} DPP_ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNT_T;
+
+typedef struct dpp_etm_crdt_mode_add_60g_t {
+	ZXIC_UINT32 mode_add_60g;
+} DPP_ETM_CRDT_MODE_ADD_60G_T;
+
+typedef struct dpp_etm_crdt_pp_token_add_t {
+	ZXIC_UINT32 pp_token_add_cir;
+} DPP_ETM_CRDT_PP_TOKEN_ADD_T;
+
+typedef struct dpp_etm_crdt_pp_cir_token_total_dist_cnt_t {
+	ZXIC_UINT32 pp_cir_token_total_dist_counter;
+} DPP_ETM_CRDT_PP_CIR_TOKEN_TOTAL_DIST_CNT_T;
+
+typedef struct dpp_etm_crdt_pp_cir_token_total_dec_cnt_t {
+	ZXIC_UINT32 pp_cir_token_total_dec_counter;
+} DPP_ETM_CRDT_PP_CIR_TOKEN_TOTAL_DEC_CNT_T;
+
+typedef struct dpp_etm_crdt_dev_credit_cnt_t {
+	ZXIC_UINT32 dev_credit_cnt;
+} DPP_ETM_CRDT_DEV_CREDIT_CNT_T;
+
+typedef struct dpp_etm_crdt_no_credit_cnt1_t {
+	ZXIC_UINT32 no_credit_cnt1;
+} DPP_ETM_CRDT_NO_CREDIT_CNT1_T;
+
+typedef struct dpp_etm_crdt_no_credit_cnt2_t {
+	ZXIC_UINT32 no_credit_cnt2;
+} DPP_ETM_CRDT_NO_CREDIT_CNT2_T;
+
+typedef struct dpp_etm_crdt_asm_interval_0_cfg_t {
+	ZXIC_UINT32 asm_interval_0_cfg;
+} DPP_ETM_CRDT_ASM_INTERVAL_0_CFG_T;
+
+typedef struct dpp_etm_crdt_asm_interval_1_cfg_t {
+	ZXIC_UINT32 asm_interval_1_cfg;
+} DPP_ETM_CRDT_ASM_INTERVAL_1_CFG_T;
+
+typedef struct dpp_etm_crdt_asm_interval_2_cfg_t {
+	ZXIC_UINT32 asm_interval_2_cfg;
+} DPP_ETM_CRDT_ASM_INTERVAL_2_CFG_T;
+
+typedef struct dpp_etm_crdt_asm_interval_3_cfg_t {
+	ZXIC_UINT32 asm_interval_3_cfg;
+} DPP_ETM_CRDT_ASM_INTERVAL_3_CFG_T;
+
+typedef struct dpp_etm_crdt_asm_interval_4_cfg_t {
+	ZXIC_UINT32 asm_interval_4_cfg;
+} DPP_ETM_CRDT_ASM_INTERVAL_4_CFG_T;
+
+typedef struct dpp_etm_crdt_asm_interval_5cfg_t {
+	ZXIC_UINT32 asm_interval_5_cfg;
+} DPP_ETM_CRDT_ASM_INTERVAL_5CFG_T;
+
+typedef struct dpp_etm_crdt_asm_interval_6_cfg_t {
+	ZXIC_UINT32 asm_interval_6_cfg;
+} DPP_ETM_CRDT_ASM_INTERVAL_6_CFG_T;
+
+typedef struct dpp_etm_crdt_asm_interval_7_cfg_t {
+	ZXIC_UINT32 asm_interval_7_cfg;
+} DPP_ETM_CRDT_ASM_INTERVAL_7_CFG_T;
+
+typedef struct dpp_etm_crdt_crdt_total_congest_mode_cfg_t {
+	ZXIC_UINT32 crdt_total_congest_mode_cfg;
+} DPP_ETM_CRDT_CRDT_TOTAL_CONGEST_MODE_CFG_T;
+
+typedef struct dpp_etm_crdt_rci_fifo_ini_deep_cfg_t {
+	ZXIC_UINT32 rci_fifo_ini_deep_cfg;
+} DPP_ETM_CRDT_RCI_FIFO_INI_DEEP_CFG_T;
+
+typedef struct dpp_etm_crdt_crdt_ecc_t {
+	ZXIC_UINT32 seinfo_wfq_single_ecc_err;
+	ZXIC_UINT32 seinfo_wfq_double_ecc_err;
+	ZXIC_UINT32 seinfo_fq_single_ecc_err;
+	ZXIC_UINT32 seinfo_fq_double_ecc_err;
+	ZXIC_UINT32 ecc_bypass;
+} DPP_ETM_CRDT_CRDT_ECC_T;
+
+typedef struct dpp_etm_crdt_ucn_asm_rdy_shield_en_t {
+	ZXIC_UINT32 ucn_rdy_shield_en;
+	ZXIC_UINT32 asm_rdy_shield_en;
+} DPP_ETM_CRDT_UCN_ASM_RDY_SHIELD_EN_T;
+
+typedef struct dpp_etm_crdt_ucn_asm_rdy_t {
+	ZXIC_UINT32 ucn_rdy;
+	ZXIC_UINT32 asm_rdy;
+} DPP_ETM_CRDT_UCN_ASM_RDY_T;
+
+typedef struct dpp_etm_crdt_rci_grade_t {
+	ZXIC_UINT32 rci_grade;
+} DPP_ETM_CRDT_RCI_GRADE_T;
+
+typedef struct dpp_etm_crdt_crdt_rci_value_r_t {
+	ZXIC_UINT32 crdt_rci_value_r;
+} DPP_ETM_CRDT_CRDT_RCI_VALUE_R_T;
+
+typedef struct dpp_etm_crdt_crdt_interval_now_t {
+	ZXIC_UINT32 crdt_interval_now;
+} DPP_ETM_CRDT_CRDT_INTERVAL_NOW_T;
+
+typedef struct dpp_etm_crdt_crs_sheild_flow_id_cfg_t {
+	ZXIC_UINT32 crs_sheild_flow_id_cfg;
+} DPP_ETM_CRDT_CRS_SHEILD_FLOW_ID_CFG_T;
+
+typedef struct dpp_etm_crdt_crs_sheild_en_cfg_t {
+	ZXIC_UINT32 crs_sheild_en_cfg;
+} DPP_ETM_CRDT_CRS_SHEILD_EN_CFG_T;
+
+typedef struct dpp_etm_crdt_crs_sheild_value_cfg_t {
+	ZXIC_UINT32 crs_sheild_value_cfg;
+} DPP_ETM_CRDT_CRS_SHEILD_VALUE_CFG_T;
+
+typedef struct dpp_etm_crdt_test_token_calc_ctrl_t {
+	ZXIC_UINT32 test_token_calc_state;
+	ZXIC_UINT32 test_token_calc_trigger;
+} DPP_ETM_CRDT_TEST_TOKEN_CALC_CTRL_T;
+
+typedef struct dpp_etm_crdt_test_token_sample_cycle_num_t {
+	ZXIC_UINT32 sample_cycle_num;
+} DPP_ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUM_T;
+
+typedef struct dpp_etm_crdt_q_state_0_7_t {
+	ZXIC_UINT32 q_token_state_7;
+	ZXIC_UINT32 q_token_state_6;
+	ZXIC_UINT32 q_token_state_5;
+	ZXIC_UINT32 q_token_state_4;
+	ZXIC_UINT32 q_token_state_3;
+	ZXIC_UINT32 q_token_state_2;
+	ZXIC_UINT32 q_token_state_1;
+	ZXIC_UINT32 q_token_state_0;
+} DPP_ETM_CRDT_Q_STATE_0_7_T;
+
+typedef struct dpp_etm_crdt_q_state_8_15_t {
+	ZXIC_UINT32 q_token_state_15;
+	ZXIC_UINT32 q_token_state_14;
+	ZXIC_UINT32 q_token_state_13;
+	ZXIC_UINT32 q_token_state_12;
+	ZXIC_UINT32 q_token_state_11;
+	ZXIC_UINT32 q_token_state_10;
+	ZXIC_UINT32 q_token_state_9;
+	ZXIC_UINT32 q_token_state_8;
+} DPP_ETM_CRDT_Q_STATE_8_15_T;
+
+typedef struct dpp_etm_qmu_csw_csch_rd_cmd_cnt_t {
+	ZXIC_UINT32 csw_csch_rd_cmd_cnt;
+} DPP_ETM_QMU_CSW_CSCH_RD_CMD_CNT_T;
+
+typedef struct dpp_etm_qmu_csw_csch_rd_sop_cnt_t {
+	ZXIC_UINT32 csw_csch_rd_sop_cnt;
+} DPP_ETM_QMU_CSW_CSCH_RD_SOP_CNT_T;
+
+typedef struct dpp_etm_qmu_csw_csch_rd_eop_cnt_t {
+	ZXIC_UINT32 csw_csch_rd_eop_cnt;
+} DPP_ETM_QMU_CSW_CSCH_RD_EOP_CNT_T;
+
+typedef struct dpp_etm_qmu_csw_csch_rd_drop_cnt_t {
+	ZXIC_UINT32 csw_csch_rd_drop_cnt;
+} DPP_ETM_QMU_CSW_CSCH_RD_DROP_CNT_T;
+
+typedef struct dpp_etm_qmu_csch_mmu_rd_cmd_cnt_t {
+	ZXIC_UINT32 csch_mmu_rd_cmd_cnt;
+} DPP_ETM_QMU_CSCH_MMU_RD_CMD_CNT_T;
+
+typedef struct dpp_etm_qmu_csch_mmu_rd_sop_cnt_t {
+	ZXIC_UINT32 csch_mmu_rd_sop_cnt;
+} DPP_ETM_QMU_CSCH_MMU_RD_SOP_CNT_T;
+
+typedef struct dpp_etm_qmu_csch_mmu_rd_eop_cnt_t {
+	ZXIC_UINT32 csch_mmu_rd_eop_cnt;
+} DPP_ETM_QMU_CSCH_MMU_RD_EOP_CNT_T;
+
+typedef struct dpp_etm_qmu_csch_mmu_rd_drop_cnt_t {
+	ZXIC_UINT32 csch_mmu_rd_drop_cnt;
+} DPP_ETM_QMU_CSCH_MMU_RD_DROP_CNT_T;
+
+typedef struct dpp_etm_qmu_qcfg_qsch_crs_filter_t {
+	ZXIC_UINT32 qcfg_qsch_crs_filter;
+} DPP_ETM_QMU_QCFG_QSCH_CRS_FILTER_T;
+
+typedef struct dpp_etm_qmu_qcfg_qsch_crs_force_en_t {
+	ZXIC_UINT32 qcfg_qsch_crs_force_en;
+} DPP_ETM_QMU_QCFG_QSCH_CRS_FORCE_EN_T;
+
+typedef struct dpp_etm_qmu_qcfg_qsch_crs_force_qnum_t {
+	ZXIC_UINT32 qcfg_qsch_crs_force_qnum;
+} DPP_ETM_QMU_QCFG_QSCH_CRS_FORCE_QNUM_T;
+
+typedef struct dpp_etm_qmu_qcfg_qsch_crs_force_crs_t {
+	ZXIC_UINT32 qcfg_qsch_crs_force_crs;
+} DPP_ETM_QMU_QCFG_QSCH_CRS_FORCE_CRS_T;
+
+typedef struct dpp_etm_qmu_cfgmt_oshp_sgmii_shap_mode_t {
+	ZXIC_UINT32 cfgmt_oshp_sgmii_shap_mode;
+} DPP_ETM_QMU_CFGMT_OSHP_SGMII_SHAP_MODE_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_sashap_en_t {
+	ZXIC_UINT32 cfgmt_qmu_sashap_en;
+} DPP_ETM_QMU_CFGMT_QMU_SASHAP_EN_T;
+
+typedef struct dpp_etm_qmu_cfgmt_sashap_token_max_t {
+	ZXIC_UINT32 cfgmt_sashap_token_max;
+} DPP_ETM_QMU_CFGMT_SASHAP_TOKEN_MAX_T;
+
+typedef struct dpp_etm_qmu_cfgmt_sashap_token_min_t {
+	ZXIC_UINT32 cfgmt_sashap_token_min;
+} DPP_ETM_QMU_CFGMT_SASHAP_TOKEN_MIN_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_q3lbaddrate_t {
+	ZXIC_UINT32 cfg_qsch_q3lbaddrate;
+} DPP_ETM_QMU_CFG_QSCH_Q3LBADDRATE_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_q012lbaddrate_t {
+	ZXIC_UINT32 cfg_qsch_q012lbaddrate;
+} DPP_ETM_QMU_CFG_QSCH_Q012LBADDRATE_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_q3creditlbmaxcnt_t {
+	ZXIC_UINT32 cfg_qsch_q3creditlbmaxcnt;
+} DPP_ETM_QMU_CFG_QSCH_Q3CREDITLBMAXCNT_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_q012creditlbmaxcnt_t {
+	ZXIC_UINT32 cfg_qsch_q012creditlbmaxcnt;
+} DPP_ETM_QMU_CFG_QSCH_Q012CREDITLBMAXCNT_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mul_token_gen_num_t {
+	ZXIC_UINT32 cfg_qsch_mul_token_gen_num;
+} DPP_ETM_QMU_CFG_QSCH_MUL_TOKEN_GEN_NUM_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_q3_credit_lb_control_en_t {
+	ZXIC_UINT32 cfg_qsch_q3_credit_lb_control_en;
+} DPP_ETM_QMU_CFG_QSCH_Q3_CREDIT_LB_CONTROL_EN_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_q012_credit_lb_control_en_t {
+	ZXIC_UINT32 cfg_qsch_q012_credit_lb_control_en;
+} DPP_ETM_QMU_CFG_QSCH_Q012_CREDIT_LB_CONTROL_EN_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_sp_dwrr_en_t {
+	ZXIC_UINT32 cfg_qsch_sp_dwrr_en;
+} DPP_ETM_QMU_CFG_QSCH_SP_DWRR_EN_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_q01_attach_en_t {
+	ZXIC_UINT32 cfg_qsch_q01_attach_en;
+} DPP_ETM_QMU_CFG_QSCH_Q01_ATTACH_EN_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_w0_t {
+	ZXIC_UINT32 cfg_qsch_w0;
+} DPP_ETM_QMU_CFG_QSCH_W0_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_w1_t {
+	ZXIC_UINT32 cfg_qsch_w1;
+} DPP_ETM_QMU_CFG_QSCH_W1_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_w2_t {
+	ZXIC_UINT32 cfg_qsch_w2;
+} DPP_ETM_QMU_CFG_QSCH_W2_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_lkybktmaxcnt1_t {
+	ZXIC_UINT32 cfg_qsch_lkybktmaxcnt1;
+} DPP_ETM_QMU_CFG_QSCH_LKYBKTMAXCNT1_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_lkybktmaxcnt2_t {
+	ZXIC_UINT32 cfg_qsch_lkybktmaxcnt2;
+} DPP_ETM_QMU_CFG_QSCH_LKYBKTMAXCNT2_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_lkybktdcrrate1_t {
+	ZXIC_UINT32 cfg_qsch_lkybktdcrrate1;
+} DPP_ETM_QMU_CFG_QSCH_LKYBKTDCRRATE1_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_lkybktdcrrate2_t {
+	ZXIC_UINT32 cfg_qsch_lkybktdcrrate2;
+} DPP_ETM_QMU_CFG_QSCH_LKYBKTDCRRATE2_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_lkybktdcrrate3_t {
+	ZXIC_UINT32 cfg_qsch_lkybktdcrrate3;
+} DPP_ETM_QMU_CFG_QSCH_LKYBKTDCRRATE3_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_lkybktmaxcnt3_t {
+	ZXIC_UINT32 cfg_qsch_lkybktmaxcnt3;
+} DPP_ETM_QMU_CFG_QSCH_LKYBKTMAXCNT3_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_qmu_mul_auto_sa_version_t {
+	ZXIC_UINT32 cfg_qsch_qmu_mul_auto_sa_version;
+} DPP_ETM_QMU_CFG_QSCH_QMU_MUL_AUTO_SA_VERSION_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_0_t {
+	ZXIC_UINT32 cfg_qsch_sa_credit_value_0;
+} DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_1_t {
+	ZXIC_UINT32 cfg_qsch_sa_credit_value_1;
+} DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_1_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_2_t {
+	ZXIC_UINT32 cfg_qsch_sa_credit_value_2;
+} DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_2_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_3_t {
+	ZXIC_UINT32 cfg_qsch_sa_credit_value_3;
+} DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_3_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_4_t {
+	ZXIC_UINT32 cfg_qsch_sa_credit_value_4;
+} DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_4_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_5_t {
+	ZXIC_UINT32 cfg_qsch_sa_credit_value_5;
+} DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_5_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_6_t {
+	ZXIC_UINT32 cfg_qsch_sa_credit_value_6;
+} DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_6_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_sa_credit_value_7_t {
+	ZXIC_UINT32 cfg_qsch_sa_credit_value_7;
+} DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_7_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_remote_credit_fifo_almost_full_th_t {
+	ZXIC_UINT32 cfg_qsch_remote_credit_fifo_almost_full_th;
+} DPP_ETM_QMU_CFG_QSCH_REMOTE_CREDIT_FIFO_ALMOST_FULL_TH_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_auto_credit_fifo_almost_full_th_t {
+	ZXIC_UINT32 cfg_qsch_auto_credit_fifo_almost_full_th;
+} DPP_ETM_QMU_CFG_QSCH_AUTO_CREDIT_FIFO_ALMOST_FULL_TH_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_q3_credit_fifo_almost_full_th_t {
+	ZXIC_UINT32 cfg_qsch_q3_credit_fifo_almost_full_th;
+} DPP_ETM_QMU_CFG_QSCH_Q3_CREDIT_FIFO_ALMOST_FULL_TH_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_q012_credit_fifo_almost_full_th_t {
+	ZXIC_UINT32 cfg_qsch_q012_credit_fifo_almost_full_th;
+} DPP_ETM_QMU_CFG_QSCH_Q012_CREDIT_FIFO_ALMOST_FULL_TH_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mul_fc_res_en_t {
+	ZXIC_UINT32 cfg_qsch_mul_fc_res_en;
+} DPP_ETM_QMU_CFG_QSCH_MUL_FC_RES_EN_T;
+
+typedef struct dpp_etm_qmu_cfgmt_mul_ovf_udf_flg_query_t {
+	ZXIC_UINT32 qsch_cfg_remote_credit_fifo_full;
+	ZXIC_UINT32 qsch_cfg_remote_credit_fifo_empty;
+	ZXIC_UINT32 qsch_cfg_remote_credit_fifo_overflow;
+	ZXIC_UINT32 qsch_cfg_remote_credit_fifo_underflow;
+	ZXIC_UINT32 qsch_cfg_auto_credit_fifo_full;
+	ZXIC_UINT32 qsch_cfg_auto_credit_fifo_empty;
+	ZXIC_UINT32 qsch_cfg_auto_credit_fifo_overflow;
+	ZXIC_UINT32 qsch_cfg_auto_credit_fifo_underflow;
+	ZXIC_UINT32 qsch_cfg_q3_credit_fifo_full;
+	ZXIC_UINT32 qsch_cfg_q3_credit_fifo_empty;
+	ZXIC_UINT32 qsch_cfg_q3_credit_fifo_overflow;
+	ZXIC_UINT32 qsch_cfg_q3_credit_fifo_underflow;
+	ZXIC_UINT32 qsch_cfg_q012_credit_fifo_full;
+	ZXIC_UINT32 qsch_cfg_q012_credit_fifo_empty;
+	ZXIC_UINT32 qsch_cfg_q012_credit_fifo_overflow;
+	ZXIC_UINT32 qsch_cfg_q012_credit_fifo_underflow;
+	ZXIC_UINT32 qsch_cfg_lkybktoverflow1;
+	ZXIC_UINT32 qsch_cfg_lkybktoverflow2;
+	ZXIC_UINT32 qsch_cfg_lkybktoverflow3;
+} DPP_ETM_QMU_CFGMT_MUL_OVF_UDF_FLG_QUERY_T;
+
+typedef struct dpp_etm_qmu_cfgmt_mul_cng_flg_query_t {
+	ZXIC_UINT32 qsch_cfg_q3cngflag;
+	ZXIC_UINT32 qsch_cfg_q012cngflag;
+	ZXIC_UINT32 qsch_cfg_cngflag1;
+	ZXIC_UINT32 qsch_cfg_cngflag2;
+	ZXIC_UINT32 qsch_cfg_cngflag3;
+} DPP_ETM_QMU_CFGMT_MUL_CNG_FLG_QUERY_T;
+
+typedef struct dpp_etm_qmu_qsch_cfg_lkybktval1_t {
+	ZXIC_UINT32 qsch_cfg_lkybktval1;
+} DPP_ETM_QMU_QSCH_CFG_LKYBKTVAL1_T;
+
+typedef struct dpp_etm_qmu_qsch_cfg_lkybktval2_t {
+	ZXIC_UINT32 qsch_cfg_lkybktval2;
+} DPP_ETM_QMU_QSCH_CFG_LKYBKTVAL2_T;
+
+typedef struct dpp_etm_qmu_qsch_cfg_lkybktval3_t {
+	ZXIC_UINT32 qsch_cfg_lkybktval3;
+} DPP_ETM_QMU_QSCH_CFG_LKYBKTVAL3_T;
+
+typedef struct dpp_etm_qmu_qsch_cfg_q3lbval_t {
+	ZXIC_UINT32 qsch_cfg_q3lbval;
+} DPP_ETM_QMU_QSCH_CFG_Q3LBVAL_T;
+
+typedef struct dpp_etm_qmu_qsch_cfg_q012lbval_t {
+	ZXIC_UINT32 qsch_cfg_q012lbval;
+} DPP_ETM_QMU_QSCH_CFG_Q012LBVAL_T;
+
+typedef struct dpp_etm_qmu_qlist_cfgmt_ram_ecc_err2_t {
+	ZXIC_UINT32 qlist_imem_pd_ram_single_ecc_err;
+	ZXIC_UINT32 qlist_imem_pd_ram_double_ecc_err;
+	ZXIC_UINT32 qlist_imem_up_ptr_ram_single_ecc_err;
+	ZXIC_UINT32 qlist_imem_up_ptr_ram_double_ecc_err;
+	ZXIC_UINT32 qlist_imem_down_ptr_ram_single_ecc_err;
+	ZXIC_UINT32 qlist_imem_down_ptr_ram_double_ecc_err;
+	ZXIC_UINT32 cmdsw_sop_fifo_single_ecc_err;
+	ZXIC_UINT32 cmdsw_sop_fifo_double_ecc_err;
+	ZXIC_UINT32 cmdsw_nsop_fifo_single_ecc_err;
+	ZXIC_UINT32 cmdsw_nsop_fifo_double_ecc_err;
+	ZXIC_UINT32 cmdsw_mmudat_fifo_single_ecc_err;
+	ZXIC_UINT32 cmdsw_mmudat_fifo_double_ecc_err;
+	ZXIC_UINT32 qlist_rd_release_fwft_single_ecc_err;
+	ZXIC_UINT32 qlist_rd_release_fwft_double_ecc_err;
+	ZXIC_UINT32 qlist_drop_imem_fwft_single_ecc_err;
+	ZXIC_UINT32 qlist_drop_imem_fwft_double_ecc_err;
+} DPP_ETM_QMU_QLIST_CFGMT_RAM_ECC_ERR2_T;
+
+typedef struct dpp_etm_qmu_csch_aged_cmd_cnt_t {
+	ZXIC_UINT32 csch_aged_cmd_cnt;
+} DPP_ETM_QMU_CSCH_AGED_CMD_CNT_T;
+
+typedef struct dpp_etm_qmu_csch_qcfg_csch_congest_cnt_t {
+	ZXIC_UINT32 csch_qcfg_csch_congest_cnt;
+} DPP_ETM_QMU_CSCH_QCFG_CSCH_CONGEST_CNT_T;
+
+typedef struct dpp_etm_qmu_csch_qcfg_qlist_csch_sop_cnt_t {
+	ZXIC_UINT32 csch_qcfg_qlist_csch_sop_cnt;
+} DPP_ETM_QMU_CSCH_QCFG_QLIST_CSCH_SOP_CNT_T;
+
+typedef struct dpp_etm_qmu_csch_qcfg_qlist_csch_eop_cnt_t {
+	ZXIC_UINT32 csch_qcfg_qlist_csch_eop_cnt;
+} DPP_ETM_QMU_CSCH_QCFG_QLIST_CSCH_EOP_CNT_T;
+
+typedef struct dpp_etm_qmu_csch_qcfg_csch_csw_sop_cnt_t {
+	ZXIC_UINT32 csch_qcfg_csch_csw_sop_cnt;
+} DPP_ETM_QMU_CSCH_QCFG_CSCH_CSW_SOP_CNT_T;
+
+typedef struct dpp_etm_qmu_csch_qcfg_csch_csw_eop_cnt_t {
+	ZXIC_UINT32 csch_qcfg_csch_csw_eop_cnt;
+} DPP_ETM_QMU_CSCH_QCFG_CSCH_CSW_EOP_CNT_T;
+
+typedef struct dpp_etm_qmu_csch_qcfg_qlist_csch_drop_cnt_t {
+	ZXIC_UINT32 csch_qcfg_qlist_csch_drop_cnt;
+} DPP_ETM_QMU_CSCH_QCFG_QLIST_CSCH_DROP_CNT_T;
+
+typedef struct dpp_etm_qmu_csch_qcfg_csch_csw_drop_cnt_t {
+	ZXIC_UINT32 csch_qcfg_csch_csw_drop_cnt;
+} DPP_ETM_QMU_CSCH_QCFG_CSCH_CSW_DROP_CNT_T;
+
+typedef struct dpp_etm_qmu_csw_mmu_sop_cmd_cnt_t {
+	ZXIC_UINT32 csw_mmu_sop_cmd_cnt;
+} DPP_ETM_QMU_CSW_MMU_SOP_CMD_CNT_T;
+
+typedef struct dpp_etm_qmu_mmu_csw_sop_data_cnt_t {
+	ZXIC_UINT32 mmu_csw_sop_data_cnt;
+} DPP_ETM_QMU_MMU_CSW_SOP_DATA_CNT_T;
+
+typedef struct dpp_etm_qmu_csw_qsch_feedb_cnt_t {
+	ZXIC_UINT32 csw_qsch_feedb_cnt;
+} DPP_ETM_QMU_CSW_QSCH_FEEDB_CNT_T;
+
+typedef struct dpp_etm_qmu_qmu_crdt_port_fc_cnt_t {
+	ZXIC_UINT32 qmu_crdt_port_fc_cnt;
+} DPP_ETM_QMU_QMU_CRDT_PORT_FC_CNT_T;
+
+typedef struct dpp_etm_qmu_csch_r_block_cnt_t {
+	ZXIC_UINT32 csch_r_block_cnt;
+} DPP_ETM_QMU_CSCH_R_BLOCK_CNT_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_qds_head_rd_t {
+	ZXIC_UINT32 qcfg_qlist_qds_head_rd;
+} DPP_ETM_QMU_QCFG_QLIST_QDS_HEAD_RD_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_qds_tail_rd_t {
+	ZXIC_UINT32 qcfg_qlist_qds_tail_rd;
+} DPP_ETM_QMU_QCFG_QLIST_QDS_TAIL_RD_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_ept_rd_t {
+	ZXIC_UINT32 qcfg_qlist_ept_rd;
+} DPP_ETM_QMU_QCFG_QLIST_EPT_RD_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_age_flag_rd_t {
+	ZXIC_UINT32 qcfg_qlist_age_flag_rd;
+} DPP_ETM_QMU_QCFG_QLIST_AGE_FLAG_RD_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_cti_rd_t {
+	ZXIC_UINT32 qcfg_qlist_cti_rd;
+} DPP_ETM_QMU_QCFG_QLIST_CTI_RD_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_cto_rd_t {
+	ZXIC_UINT32 qcfg_qlist_cto_rd;
+} DPP_ETM_QMU_QCFG_QLIST_CTO_RD_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_chk_rd_t {
+	ZXIC_UINT32 qcfg_qlist_chk_rd;
+} DPP_ETM_QMU_QCFG_QLIST_CHK_RD_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_nod_rd_t {
+	ZXIC_UINT32 qcfg_qlist_nod_rd;
+} DPP_ETM_QMU_QCFG_QLIST_NOD_RD_T;
+
+typedef struct dpp_etm_qmu_qcfg_qlist_biu_rd_t {
+	ZXIC_UINT32 qcfg_qlist_biu_rd;
+} DPP_ETM_QMU_QCFG_QLIST_BIU_RD_T;
+
+typedef struct dpp_etm_qmu_qsch_r_wlist_flag_t {
+	ZXIC_UINT32 qsch_r_wlist_flag;
+} DPP_ETM_QMU_QSCH_R_WLIST_FLAG_T;
+
+typedef struct dpp_etm_qmu_qcfg_crs_flg_rd_t {
+	ZXIC_UINT32 qcfg_crs_flg_rd;
+} DPP_ETM_QMU_QCFG_CRS_FLG_RD_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_imem_age_qds_t {
+	ZXIC_UINT32 cfgmt_qmu_imem_tp;
+	ZXIC_UINT32 cfgmt_qmu_imem_hp;
+} DPP_ETM_QMU_CFGMT_QMU_IMEM_AGE_QDS_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_imem_age_qlen_t {
+	ZXIC_UINT32 cfgmt_qmu_imem_no_empty;
+	ZXIC_UINT32 cfgmt_qmu_imem_qlen;
+} DPP_ETM_QMU_CFGMT_QMU_IMEM_AGE_QLEN_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_imem_pd_ram_low_t {
+	ZXIC_UINT32 cfgmt_qmu_imem_pd_ram_low;
+} DPP_ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_LOW_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_imem_pd_ram_high_t {
+	ZXIC_UINT32 cfgmt_qmu_imem_pd_ram_high;
+} DPP_ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_HIGH_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_imem_up_ptr_t {
+	ZXIC_UINT32 cfgmt_qmu_imem_up_ptr;
+} DPP_ETM_QMU_CFGMT_QMU_IMEM_UP_PTR_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_imem_down_ptr_t {
+	ZXIC_UINT32 cfgmt_qmu_imem_down_ptr;
+} DPP_ETM_QMU_CFGMT_QMU_IMEM_DOWN_PTR_T;
+
+typedef struct dpp_etm_qmu_cfgmt_qmu_imem_age_flag_t {
+	ZXIC_UINT32 cfgmt_qmu_imem_age_flag;
+} DPP_ETM_QMU_CFGMT_QMU_IMEM_AGE_FLAG_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_lkybkt2cngth_t {
+	ZXIC_UINT32 cfg_qsch_lkybkt2cngth;
+} DPP_ETM_QMU_CFG_QSCH_LKYBKT2CNGTH_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_lkybkt1cngth_t {
+	ZXIC_UINT32 cfg_qsch_lkybkt1cngth;
+} DPP_ETM_QMU_CFG_QSCH_LKYBKT1CNGTH_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_lkybkt3cngth_t {
+	ZXIC_UINT32 cfg_qsch_lkybkt3cngth;
+} DPP_ETM_QMU_CFG_QSCH_LKYBKT3CNGTH_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn1_credit_value_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_credit_value;
+} DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN1_CREDIT_VALUE_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn2_credit_value_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_credit_value;
+} DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN2_CREDIT_VALUE_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn3_credit_value_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_credit_value;
+} DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN3_CREDIT_VALUE_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_ansr_seed_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_mchsm_en;
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_ansr_seed;
+} DPP_ETM_QMU_RM_MUL_MCN1_RAND_ANSR_SEED_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_ansr_seed_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_mchsm_en;
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_ansr_seed;
+} DPP_ETM_QMU_RM_MUL_MCN2_RAND_ANSR_SEED_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_ansr_seed_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_mchsm_en;
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_ansr_seed;
+} DPP_ETM_QMU_RM_MUL_MCN3_RAND_ANSR_SEED_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_ansr_th_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_ansr_th;
+} DPP_ETM_QMU_RM_MUL_MCN1_RAND_ANSR_TH_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_ansr_th_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_ansr_th;
+} DPP_ETM_QMU_RM_MUL_MCN2_RAND_ANSR_TH_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_ansr_th_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_ansr_th;
+} DPP_ETM_QMU_RM_MUL_MCN3_RAND_ANSR_TH_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_hold_base_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_mchsm_en;
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_hold_base;
+} DPP_ETM_QMU_RM_MUL_MCN1_RAND_HOLD_BASE_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_hold_base_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_mchsm_en;
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_hold_base;
+} DPP_ETM_QMU_RM_MUL_MCN2_RAND_HOLD_BASE_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_hold_base_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_mchsm_en;
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_hold_base;
+} DPP_ETM_QMU_RM_MUL_MCN3_RAND_HOLD_BASE_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_sel_mask_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_sel_mask;
+} DPP_ETM_QMU_RM_MUL_MCN1_RAND_SEL_MASK_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_sel_mask_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_sel_mask;
+} DPP_ETM_QMU_RM_MUL_MCN2_RAND_SEL_MASK_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_sel_mask_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_sel_mask;
+} DPP_ETM_QMU_RM_MUL_MCN3_RAND_SEL_MASK_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg0_t {
+	ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed7;
+	ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed6;
+	ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed5;
+	ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed4;
+	ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed3;
+	ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed2;
+	ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed1;
+	ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed0;
+} DPP_ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG0_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg1_t {
+	ZXIC_UINT32 rm_mul_mcn1_rand_sel_seed8;
+} DPP_ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG1_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg0_t {
+	ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed7;
+	ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed6;
+	ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed5;
+	ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed4;
+	ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed3;
+	ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed2;
+	ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed1;
+	ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed0;
+} DPP_ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG0_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg1_t {
+	ZXIC_UINT32 rm_mul_mcn2_rand_sel_seed8;
+} DPP_ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG1_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg0_t {
+	ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed7;
+	ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed6;
+	ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed5;
+	ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed4;
+	ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed3;
+	ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed2;
+	ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed1;
+	ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed0;
+} DPP_ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG0_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg1_t {
+	ZXIC_UINT32 rm_mul_mcn3_rand_sel_seed8;
+} DPP_ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG1_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th1_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th1;
+} DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH1_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th2_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th2;
+} DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH2_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th3_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th3;
+} DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH3_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th4_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th4;
+} DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH4_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th5_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th5;
+} DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH5_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th6_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th6;
+} DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH6_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn1_step_wait_th7_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_step_wait_th7;
+} DPP_ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH7_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th1_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th1;
+} DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH1_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th2_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th2;
+} DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH2_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th3_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th3;
+} DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH3_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th4_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th4;
+} DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH4_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th5_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th5;
+} DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH5_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th6_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th6;
+} DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH6_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn2_step_wait_th7_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_step_wait_th7;
+} DPP_ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH7_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th1_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th1;
+} DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH1_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th2_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th2;
+} DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH2_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th3_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th3;
+} DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH3_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th4_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th4;
+} DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH4_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th5_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th5;
+} DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH5_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn3_step_wait_th6_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th6;
+} DPP_ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH6_T;
+
+typedef struct dpp_etm_qmu_rm_mul_mcn3step_wait_th7_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_step_wait_th7;
+} DPP_ETM_QMU_RM_MUL_MCN3STEP_WAIT_TH7_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate0_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate0;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE0_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate1_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate1;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE1_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate2_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate2;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE2_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate3_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate3;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE3_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate4_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate4;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE4_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate5_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate5;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE5_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate6_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate6;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE6_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate7_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate7;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE7_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate8_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate8;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE8_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate9_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate9;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE9_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate10_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate10;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE10_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate11_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate11;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE11_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate12_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate12;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE12_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate13_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate13;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE13_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate14_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate14;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE14_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate15_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate15;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE15_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate16_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate16;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE16_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate17_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate17;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE17_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate18_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate18;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE18_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate19_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate19;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE19_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate20_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate20;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE20_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate21_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate21;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE21_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate22_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate22;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE22_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate23_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate23;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE23_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate24_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate24;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE24_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate25_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate25;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE25_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate26_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate26;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE26_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate27_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate27;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE27_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate28_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate28;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE28_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate29_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate29;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE29_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate30_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate30;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE30_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate31_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate31;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE31_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate32_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate32;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE32_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate33_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate33;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE33_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate34_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate34;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE34_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate35_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate35;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE35_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_mulcrdcntrate36_t {
+	ZXIC_UINT32 cfg_qsch_mulcrdcntrate36;
+} DPP_ETM_QMU_CFG_QSCH_MULCRDCNTRATE36_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn1_rand_hold_shift_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn1_rand_hold_shift;
+} DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN1_RAND_HOLD_SHIFT_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn2_rand_hold_shift_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn2_rand_hold_shift;
+} DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN2_RAND_HOLD_SHIFT_T;
+
+typedef struct dpp_etm_qmu_cfg_qsch_rm_mul_mcn3_rand_hold_shift_t {
+	ZXIC_UINT32 cfg_qsch_rm_mul_mcn3_rand_hold_shift;
+} DPP_ETM_QMU_CFG_QSCH_RM_MUL_MCN3_RAND_HOLD_SHIFT_T;
+
+typedef struct dpp_etm_qmu_last_drop_qnum_get_t {
+	ZXIC_UINT32 cgavd_qmu_drop_tap;
+	ZXIC_UINT32 last_drop_qnum;
+} DPP_ETM_QMU_LAST_DROP_QNUM_GET_T;
+
+typedef struct dpp_etm_qmu_crdt_qmu_credit_cnt_t {
+	ZXIC_UINT32 crdt_qmu_credit_cnt;
+} DPP_ETM_QMU_CRDT_QMU_CREDIT_CNT_T;
+
+typedef struct dpp_etm_qmu_qmu_to_qsch_report_cnt_t {
+	ZXIC_UINT32 qmu_to_qsch_report_cnt;
+} DPP_ETM_QMU_QMU_TO_QSCH_REPORT_CNT_T;
+
+typedef struct dpp_etm_qmu_qmu_to_cgavd_report_cnt_t {
+	ZXIC_UINT32 qmu_to_cgavd_report_cnt;
+} DPP_ETM_QMU_QMU_TO_CGAVD_REPORT_CNT_T;
+
+typedef struct dpp_etm_qmu_qmu_crdt_crs_normal_cnt_t {
+	ZXIC_UINT32 qmu_crdt_crs_normal_cnt;
+} DPP_ETM_QMU_QMU_CRDT_CRS_NORMAL_CNT_T;
+
+typedef struct dpp_etm_qmu_qmu_crdt_crs_off_cnt_t {
+	ZXIC_UINT32 qmu_crdt_crs_off_cnt;
+} DPP_ETM_QMU_QMU_CRDT_CRS_OFF_CNT_T;
+
+typedef struct dpp_etm_qmu_qsch_qlist_shedule_cnt_t {
+	ZXIC_UINT32 qsch_qlist_shedule_cnt;
+} DPP_ETM_QMU_QSCH_QLIST_SHEDULE_CNT_T;
+
+typedef struct dpp_etm_qmu_qsch_qlist_sch_ept_cnt_t {
+	ZXIC_UINT32 qsch_qlist_sch_ept_cnt;
+} DPP_ETM_QMU_QSCH_QLIST_SCH_EPT_CNT_T;
+
+typedef struct dpp_etm_qmu_qmu_to_mmu_blk_wr_cnt_t {
+	ZXIC_UINT32 qmu_to_mmu_blk_wr_cnt;
+} DPP_ETM_QMU_QMU_TO_MMU_BLK_WR_CNT_T;
+
+typedef struct dpp_etm_qmu_qmu_to_csw_blk_rd_cnt_t {
+	ZXIC_UINT32 qmu_to_csw_blk_rd_cnt;
+} DPP_ETM_QMU_QMU_TO_CSW_BLK_RD_CNT_T;
+
+typedef struct dpp_etm_qmu_qmu_to_mmu_sop_wr_cnt_t {
+	ZXIC_UINT32 qmu_to_mmu_sop_wr_cnt;
+} DPP_ETM_QMU_QMU_TO_MMU_SOP_WR_CNT_T;
+
+typedef struct dpp_etm_qmu_qmu_to_mmu_eop_wr_cnt_t {
+	ZXIC_UINT32 qmu_to_mmu_eop_wr_cnt;
+} DPP_ETM_QMU_QMU_TO_MMU_EOP_WR_CNT_T;
+
+typedef struct dpp_etm_qmu_qmu_to_mmu_drop_wr_cnt_t {
+	ZXIC_UINT32 qmu_to_mmu_drop_wr_cnt;
+} DPP_ETM_QMU_QMU_TO_MMU_DROP_WR_CNT_T;
+
+typedef struct dpp_etm_qmu_qmu_to_csw_sop_rd_cnt_t {
+	ZXIC_UINT32 qmu_to_csw_sop_rd_cnt;
+} DPP_ETM_QMU_QMU_TO_CSW_SOP_RD_CNT_T;
+
+typedef struct dpp_etm_qmu_qmu_to_csw_eop_rd_cnt_t {
+	ZXIC_UINT32 qmu_to_csw_eop_rd_cnt;
+} DPP_ETM_QMU_QMU_TO_CSW_EOP_RD_CNT_T;
+
+typedef struct dpp_etm_qmu_qmu_to_csw_drop_rd_cnt_t {
+	ZXIC_UINT32 qmu_to_csw_drop_rd_cnt;
+} DPP_ETM_QMU_QMU_TO_CSW_DROP_RD_CNT_T;
+
+typedef struct dpp_etm_qmu_mmu_to_qmu_wr_release_cnt_t {
+	ZXIC_UINT32 mmu_to_qmu_wr_release_cnt;
+} DPP_ETM_QMU_MMU_TO_QMU_WR_RELEASE_CNT_T;
+
+typedef struct dpp_etm_qmu_mmu_to_qmu_rd_release_cnt_t {
+	ZXIC_UINT32 mmu_to_qmu_rd_release_cnt;
+} DPP_ETM_QMU_MMU_TO_QMU_RD_RELEASE_CNT_T;
+
+typedef struct dpp_etm_qmu_observe_qnum_set_t {
+	ZXIC_UINT32 observe_qnum_set;
+} DPP_ETM_QMU_OBSERVE_QNUM_SET_T;
+
+typedef struct dpp_etm_qmu_spec_q_pkt_received_t {
+	ZXIC_UINT32 spec_q_pkt_received;
+} DPP_ETM_QMU_SPEC_Q_PKT_RECEIVED_T;
+
+typedef struct dpp_etm_qmu_spec_q_pkt_dropped_t {
+	ZXIC_UINT32 spec_q_pkt_dropped;
+} DPP_ETM_QMU_SPEC_Q_PKT_DROPPED_T;
+
+typedef struct dpp_etm_qmu_spec_q_pkt_scheduled_t {
+	ZXIC_UINT32 spec_q_pkt_scheduled;
+} DPP_ETM_QMU_SPEC_Q_PKT_SCHEDULED_T;
+
+typedef struct dpp_etm_qmu_spec_q_wr_cmd_sent_t {
+	ZXIC_UINT32 spec_q_wr_cmd_sent;
+} DPP_ETM_QMU_SPEC_Q_WR_CMD_SENT_T;
+
+typedef struct dpp_etm_qmu_spec_q_rd_cmd_sent_t {
+	ZXIC_UINT32 spec_q_rd_cmd_sent;
+} DPP_ETM_QMU_SPEC_Q_RD_CMD_SENT_T;
+
+typedef struct dpp_etm_qmu_spec_q_pkt_enq_t {
+	ZXIC_UINT32 spec_q_pkt_enq;
+} DPP_ETM_QMU_SPEC_Q_PKT_ENQ_T;
+
+typedef struct dpp_etm_qmu_spec_q_pkt_deq_t {
+	ZXIC_UINT32 spec_q_pkt_deq;
+} DPP_ETM_QMU_SPEC_Q_PKT_DEQ_T;
+
+typedef struct dpp_etm_qmu_spec_q_crdt_uncon_received_t {
+	ZXIC_UINT32 spec_q_crdt_uncon_received;
+} DPP_ETM_QMU_SPEC_Q_CRDT_UNCON_RECEIVED_T;
+
+typedef struct dpp_etm_qmu_spec_q_crdt_cong_received_t {
+	ZXIC_UINT32 spec_q_crdt_cong_received;
+} DPP_ETM_QMU_SPEC_Q_CRDT_CONG_RECEIVED_T;
+
+typedef struct dpp_etm_qmu_spec_q_crs_normal_cnt_t {
+	ZXIC_UINT32 spec_q_crs_normal_cnt;
+} DPP_ETM_QMU_SPEC_Q_CRS_NORMAL_CNT_T;
+
+typedef struct dpp_etm_qmu_spec_q_crs_off_cnt_t {
+	ZXIC_UINT32 spec_q_crs_off_cnt;
+} DPP_ETM_QMU_SPEC_Q_CRS_OFF_CNT_T;
+
+typedef struct dpp_etm_qmu_observe_batch_set_t {
+	ZXIC_UINT32 observe_batch_set;
+} DPP_ETM_QMU_OBSERVE_BATCH_SET_T;
+
+typedef struct dpp_etm_qmu_spec_bat_pkt_received_t {
+	ZXIC_UINT32 spec_bat_pkt_received;
+} DPP_ETM_QMU_SPEC_BAT_PKT_RECEIVED_T;
+
+typedef struct dpp_etm_qmu_spec_bat_pkt_dropped_t {
+	ZXIC_UINT32 spec_bat_pkt_dropped;
+} DPP_ETM_QMU_SPEC_BAT_PKT_DROPPED_T;
+
+typedef struct dpp_etm_qmu_spec_bat_blk_scheduled_t {
+	ZXIC_UINT32 spec_bat_blk_scheduled;
+} DPP_ETM_QMU_SPEC_BAT_BLK_SCHEDULED_T;
+
+typedef struct dpp_etm_qmu_spec_bat_wr_cmd_sent_t {
+	ZXIC_UINT32 spec_bat_wr_cmd_sent;
+} DPP_ETM_QMU_SPEC_BAT_WR_CMD_SENT_T;
+
+typedef struct dpp_etm_qmu_spec_bat_rd_cmd_sent_t {
+	ZXIC_UINT32 spec_bat_rd_cmd_sent;
+} DPP_ETM_QMU_SPEC_BAT_RD_CMD_SENT_T;
+
+typedef struct dpp_etm_qmu_spec_bat_pkt_enq_t {
+	ZXIC_UINT32 spec_bat_pkt_enq;
+} DPP_ETM_QMU_SPEC_BAT_PKT_ENQ_T;
+
+typedef struct dpp_etm_qmu_spec_bat_pkt_deq_t {
+	ZXIC_UINT32 spec_bat_pkt_deq;
+} DPP_ETM_QMU_SPEC_BAT_PKT_DEQ_T;
+
+typedef struct dpp_etm_qmu_spec_bat_crdt_uncon_received_t {
+	ZXIC_UINT32 spec_bat_crdt_uncon_received;
+} DPP_ETM_QMU_SPEC_BAT_CRDT_UNCON_RECEIVED_T;
+
+typedef struct dpp_etm_qmu_spec_bat_crdt_cong_received_t {
+	ZXIC_UINT32 spec_bat_crdt_cong_received;
+} DPP_ETM_QMU_SPEC_BAT_CRDT_CONG_RECEIVED_T;
+
+typedef struct dpp_etm_qmu_spec_bat_crs_normal_cnt_t {
+	ZXIC_UINT32 spec_bat_crs_normal_cnt;
+} DPP_ETM_QMU_SPEC_BAT_CRS_NORMAL_CNT_T;
+
+typedef struct dpp_etm_qmu_spec_bat_crs_off_cnt_t {
+	ZXIC_UINT32 spec_bat_crs_off_cnt;
+} DPP_ETM_QMU_SPEC_BAT_CRS_OFF_CNT_T;
+
+typedef struct dpp_etm_qmu_bcntm_ovfl_qnum_get_t {
+	ZXIC_UINT32 bcntm_ovfl_qnum_get;
+} DPP_ETM_QMU_BCNTM_OVFL_QNUM_GET_T;
+
+typedef struct dpp_etm_qmu_crbal_a_ovf_qnum_get_t {
+	ZXIC_UINT32 crbal_a_ovf_qnum_get;
+} DPP_ETM_QMU_CRBAL_A_OVF_QNUM_GET_T;
+
+typedef struct dpp_etm_qmu_crbal_b_ovf_qnum_get_t {
+	ZXIC_UINT32 crbal_b_ovf_qnum_get;
+} DPP_ETM_QMU_CRBAL_B_OVF_QNUM_GET_T;
+
+typedef struct dpp_etm_qmu_crbal_drop_qnum_get_t {
+	ZXIC_UINT32 crbal_drop_qnum_get;
+} DPP_ETM_QMU_CRBAL_DROP_QNUM_GET_T;
+
+typedef struct dpp_etm_qmu_deq_flg_report_cnt_t {
+	ZXIC_UINT32 deq_flg_report_cnt;
+} DPP_ETM_QMU_DEQ_FLG_REPORT_CNT_T;
+
+typedef struct dpp_etm_qmu_spec_q_crs_get_t {
+	ZXIC_UINT32 spec_q_crs_get;
+} DPP_ETM_QMU_SPEC_Q_CRS_GET_T;
+
+typedef struct dpp_etm_qmu_spec_q_crs_in_get_t {
+	ZXIC_UINT32 spec_q_crs_in_get;
+} DPP_ETM_QMU_SPEC_Q_CRS_IN_GET_T;
+
+typedef struct dpp_etm_qmu_spec_q_crs_flg_csol_get_t {
+	ZXIC_UINT32 spec_q_crs_flg_csol_get;
+} DPP_ETM_QMU_SPEC_Q_CRS_FLG_CSOL_GET_T;
+
+typedef struct dpp_etm_qmu_ept_sch_qnum_get_t {
+	ZXIC_UINT32 ept_sch_qnum_get;
+} DPP_ETM_QMU_EPT_SCH_QNUM_GET_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_mem_info.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_mem_info.h
old mode 100755
new mode 100644
index ddf091fc5bc1ac261fcabafdccf7b9d002e4d645..03d471087ea6e540220d9deda9562e93e69b6b67
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_mem_info.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_mem_info.h
@@ -1,66 +1,60 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_mem.h
-* 文件标识 : 
-* 内容摘要 : 
-* 其它说明 : 
-* 当前版本 : 
-* 作    者 : 王春雷
-* 完成日期 : 2014/03/20
-* DEPARTMENT: ASIC_FPGA_R&D_Dept 
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* 版 本 号:  
-* 修 改 人:  
-* 修改内容:  
-***************************************************************/
-
-#ifndef _DPP_MEM_H_
-#define _DPP_MEM_H_
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-typedef enum dpp_mem_no_e
-{
-    PKTRX_PHYPORT_UDF_ATTRIm           = 0,
-    PKTRX_PHYPORT_HDW_ATTRIm           = 1,
-    PKTRX_PHYPORT_FLOW_PCm             = 2,
-    PKTRX_ICU_TCAMm                    = 3,
-    PKTRX_FLOWNUM_TCAMm                = 4,
-}DPP_MEM_NO_E;
-
-typedef struct dpp_mem_field_t
-{
-    ZXIC_SINT8   *p_name;         /* 字段名 */
-    ZXIC_UINT32  flags;           /* 标志位 */
-    ZXIC_UINT16  msb_pos;         /* 最高比特位置，以寄存器列表为准*/
-    ZXIC_UINT16  len;             /* 字段长度，以比特为单位 */
-}DPP_MEM_FIELD_T;
-
-
-#define DPP_MEM_FLAG_TCAM     (1<<0)  /* Tcam类型的表 */
-typedef struct dpp_mem_info_t
-{
-    ZXIC_UINT32 mem_no;
-    ZXIC_UINT32 module_no;
-    ZXIC_UINT32 flags;
-    ZXIC_UINT32 mem_id;     /* 模块内部的mem标识 */
-    ZXIC_UINT32 index_min;  /* 最小索引值 */
-    ZXIC_UINT32 index_max;  /* 最大索引值 */
-    ZXIC_UINT32 width;      /* 表项宽度，以字节为单位 */
-
-    DPP_MEM_FIELD_T *p_fileds;  /* 表项所有字段 */
-
-}DPP_MEM_INFO_T;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_mem.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2014/03/20
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#ifndef _DPP_MEM_H_
+#define _DPP_MEM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum dpp_mem_no_e {
+	PKTRX_PHYPORT_UDF_ATTRIm = 0,
+	PKTRX_PHYPORT_HDW_ATTRIm = 1,
+	PKTRX_PHYPORT_FLOW_PCm = 2,
+	PKTRX_ICU_TCAMm = 3,
+	PKTRX_FLOWNUM_TCAMm = 4,
+} DPP_MEM_NO_E;
+
+typedef struct dpp_mem_field_t {
+	ZXIC_SINT8 *p_name; /* 字段名 */
+	ZXIC_UINT32 flags; /* 标志位 */
+	ZXIC_UINT16 msb_pos; /* 最高比特位置，以寄存器列表为准*/
+	ZXIC_UINT16 len; /* 字段长度，以比特为单位 */
+} DPP_MEM_FIELD_T;
+
+#define DPP_MEM_FLAG_TCAM (1 << 0) /* Tcam类型的表 */
+typedef struct dpp_mem_info_t {
+	ZXIC_UINT32 mem_no;
+	ZXIC_UINT32 module_no;
+	ZXIC_UINT32 flags;
+	ZXIC_UINT32 mem_id; /* 模块内部的mem标识 */
+	ZXIC_UINT32 index_min; /* 最小索引值 */
+	ZXIC_UINT32 index_max; /* 最大索引值 */
+	ZXIC_UINT32 width; /* 表项宽度，以字节为单位 */
+
+	DPP_MEM_FIELD_T *p_fileds; /* 表项所有字段 */
+
+} DPP_MEM_INFO_T;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_module.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_module.h
old mode 100755
new mode 100644
index 7c48381505249967e57d4d277bcd3ad921ac39c4..ac746a7dfcde1950b7bb390205811ba4de659529
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_module.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_module.h
@@ -1,214 +1,200 @@
-#ifndef _DPP_MODULE_H_
-#define _DPP_MODULE_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "zxic_common.h"
-#include "dpp_dev.h"
-#include "dpp_type_api.h"
-
-/**  for PPU*/
-#ifdef DPP_TEST_BAORD_SSP2T
-#define DPP_PPU_CLUSTER_NUM              (1)
-#else
-#define DPP_PPU_CLUSTER_NUM              (6)
-#endif
-
-#define DPP_PPU_ME_EXCEPTION_MAX         (8)
-#define DPP_PPU_CLUSTER_MEPERCLS_NUM     (8)
-#define DPP_PPU_CLUSTER_SPACE_SIZE       (0x00008000)
-#define DPP_MAX_CHCHK_NUM                (50)
-
-#define DPP_TRPG_PORT_NUM                (32)
-#define DPP_TRPG_PORT_SPACE_SIZE         (0x10000)
-
-#define DPP_TRPG_RAM_NUM                 (16)
-#define DPP_TRPG_RAM_SPACE_SIZE          (0x10000)
-
-#define DPP_TSN_PORT_NUM                (4)
-#define DPP_TSN_PORT_SPACE_SIZE         (0x4000)
-
-typedef enum dpp_module_e
-{
-    CFG = 1,             /**<  @brief 1*/
-    NPPU,                /**<  @brief 2*/
-    PPU,                 /**<  @brief 3*/
-    ETM,                 /**<  @brief 4*/
-    STAT,                /**<  @brief 5*/
-    CAR,                 /**<  @brief 6*/
-    SE,                  /**<  @brief 7*/
-    SMMU0       = SE,    /**<  @brief 7*/
-    SMMU1       = SE,    /**<  @brief 7*/
-    DTB,                 /**<  @brief 8*/
-    TRPG ,               /**<  @brief 9*/
-    TSN ,                /**<  @brief 10*/
-    AXI ,                /**<  @brief 11*/
-    PTPTM ,              /**<  @brief 12*/
-    DTB4K,               /**<  @brief 13*/
-    STAT4K,              /**<  @brief 14*/
-    PPU4K,               /**<  @brief 15*/
-    SE4K,                /**<  @brief 16*/
-    SMMU14K,             /**<  @brief 17*/
-    MODULE_MAX           
-} DPP_MODULE_E;
-
-typedef enum module_tm_e
-{
-    MODULE_TM_CFGMT = 0,
-    MODULE_TM_OLIF  = 1,
-    MODULE_TM_CGAVD = 2,
-    MODULE_TM_TMMU  = 3,
-    MODULE_TM_SHAP  = 4,
-    MODULE_TM_CRDT  = 5,
-    MODULE_TM_QMU   = 6,
-    MODULE_TM_MAX
-} MODULE_TM_E;
-
-/*NP 在PICE中的偏移地址*/
-#define SYS_VF_NP_BASE_OFFSET      0X0000000000
-/*NP 在DPU中的基地址*/
-
-#if DPP_DEV_VPCI_EN
-#define SYS_NP_BASE_ADDR           0x6300000000
-#define SYS_NP_BASE_ADDR0          0x14000000
-#define SYS_NP_BASE_ADDR1          0x16000000
-#else
-#define SYS_NP_BASE_ADDR           0x6218000000
-#define SYS_NP_BASE_ADDR0          0x00000000
-#define SYS_NP_BASE_ADDR1          0x02000000
-#endif
-
-/**  sub system base address*/
-typedef enum sys_base_addr_e
-{
-    SYS_NPPU_BASE_ADDR               = (SYS_NP_BASE_ADDR0 + 0x00000000),
-    SYS_PPU_BASE_ADDR                = (SYS_NP_BASE_ADDR0 + 0x00080000),
-    SYS_ETM_BASE_ADDR                = (SYS_NP_BASE_ADDR0 + 0x00180000),
-    SYS_STAT_BASE_ADDR               = (SYS_NP_BASE_ADDR0 + 0x00200000),
-    SYS_SE_BASE_ADDR                 = (SYS_NP_BASE_ADDR0 + 0x00280000),
-    SYS_SE_SMMU0_BASE_ADDR           = (SYS_NP_BASE_ADDR0 + 0x00300000),
-    SYS_SE_SMMU1_BASE_ADDR           = (SYS_NP_BASE_ADDR0 + 0x00310000),
-//    SYS_TRPG_BASE_ADDR               = (SYS_NP_BASE_ADDR0 + 0x00320000),
-    SYS_CFG_BASE_ADDR                = (SYS_NP_BASE_ADDR0 + 0x00330000),
-    SYS_PTP0_BASE_ADDR               = (SYS_NP_BASE_ADDR0 + 0x00340000),
-    SYS_PTP1_BASE_ADDR               = (SYS_NP_BASE_ADDR0 + 0x00344000),
-    SYS_TSN_BASE_ADDR                = (SYS_NP_BASE_ADDR0 + 0x00350000),
-    SYS_TRPG_BASE_ADDR               = (SYS_NP_BASE_ADDR0 + 0x00400000),
-
-    SYS_DTB_BASE_ADDR                = (SYS_NP_BASE_ADDR1 + 0x00000000),
-    SYS_AXIM0_BASE_ADDR              = (SYS_NP_BASE_ADDR1 + 0x01400000),
-    SYS_AXIM1_BASE_ADDR              = (SYS_NP_BASE_ADDR1 + 0x01408000),
-    SYS_AXI_CONV_BASE_ADDR           = (SYS_NP_BASE_ADDR1 + 0x01410000),
-    SYS_AXIS_BASE_ADDR               = (SYS_NP_BASE_ADDR1 + 0x01418000),
-    SYS_TLB_BASE_ADDR                = (SYS_NP_BASE_ADDR1 + 0x01420000),
-    
-    SYS_MAX_BASE_ADDR                = 0x20000000,
-} SYS_BASE_ADDR_E;
-
-/**  module base address*/
-typedef enum module_base_addr_e
-{
-    /* CFG         */
-    MODULE_CFG_PCIE_BASE_ADDR        = 0x00000000,
-    MODULE_CFG_DMA_BASE_ADDR         = 0x00001000,
-    MODULE_CFG_CSR_BASE_ADDR         = 0x00003000,
-
-    /* NPPU       */
-    MODULE_NPPU_MR_CFG_BASE_ADDR           = 0x00000000,
-    MODULE_NPPU_PKTRX_CFG_BASE_ADDR        = 0x00000800,
-    MODULE_NPPU_PKTRX_STAT_BASE_ADDR       = 0x00001000,
-    MODULE_NPPU_IDMA_CFG_BASE_ADDR         = 0x00001800,
-    MODULE_NPPU_IDMA_STAT_BASE_ADDR        = 0x00002000,
-    MODULE_NPPU_PBU_CFG_BASE_ADDR          = 0x00002800,
-    MODULE_NPPU_PBU_STAT_BASE_ADDR         = 0x00003000,
-    MODULE_NPPU_ISU_CFG_BASE_ADDR          = 0x00003800,
-    MODULE_NPPU_ISU_STAT_BASE_ADDR         = 0x00004000,
-    MODULE_NPPU_ODMA_CFG_BASE_ADDR         = 0x00004800,
-    MODULE_NPPU_ODMA_STAT_BASE_ADDR        = 0x00005000,
-    MODULE_NPPU_OAM_CFG_BASE_ADDR          = 0x00005800,
-    MODULE_NPPU_OAM_STAT_BASE_ADDR         = 0x00006000,
-    MODULE_NPPU_OAM_INT_IDX0_BASE_ADDR     = 0x00006800,
-    MODULE_NPPU_OAM_INT_IDX1_BASE_ADDR     = 0x00007000,
-
-    /* PPU         */
-    MODULE_PPU_CSR_BASE_ADDR         = 0x00000000,
-    MODULE_PPU_DBG_BASE_ADDR         = 0x00000800,
-    MODULE_CLUSTER0_BASE_ADDR        = 0x00008000,
-    MODULE_CLUSTER1_BASE_ADDR        = 0x00010000,
-    MODULE_CLUSTER2_BASE_ADDR        = 0x00018000,
-    MODULE_CLUSTER3_BASE_ADDR        = 0x00020000,
-
-    /* TM          */
-    MODULE_TM_CFGMT_BASE_ADDR        = 0x00000000,
-    MODULE_TM_OLIF_BASE_ADDR         = 0x00020000,
-    MODULE_TM_CGAVD_BASE_ADDR        = 0x00030000,
-    MODULE_TM_TMMU_BASE_ADDR         = 0x00040000,
-    MODULE_TM_SHAP_BASE_ADDR         = 0x00050000,
-    MODULE_TM_CRDT_BASE_ADDR         = 0x00060000,
-    MODULE_TM_QMU_BASE_ADDR          = 0x00070000,
-
-    /* STAT        */
-    MODULE_STAT_CAR0_BASE_ADDR       = 0x00000000,
-    MODULE_STAT_ETCAM_BASE_ADDR      = 0x00002000,
-    MODULE_STAT_GLBL_BASE_ADDR       = 0x00003000,
-
-    /* SE          */
-    MODULE_SE_ALG_BASE_ADDR          = 0x00000000,         
-    MODULE_SE_KSCHD_BASE_ADDR        = 0x00004000,        
-    MODULE_SE_RSCHD_BASE_ADDR        = 0x00008000,         
-    MODULE_SE_PARSER_BASE_ADDR       = 0x0000c000,        
-    MODULE_SE_AS_BASE_ADDR           = 0x00010000,        
-    MODULE_SE_CFG_BASE_ADDR          = 0x00014000, 
-    
-    /* SMMU0          */
-    MODULE_SE_SMMU0_BASE_ADDR        = 0x00000000,         
-
-    /* SMMU1          */
-    MODULE_SE_SMMU1_BASE_ADDR        = 0x00000000,         
-    MODULE_SE_CMMU_BASE_ADDR         = 0x00004000,    
-
-    /* DTB          */
-    MODULE_DTB_ENQ_BASE_ADDR        = 0x00000000,         
-    MODULE_DTB_CFG_BASE_ADDR        = 0x01000000, 
-    MODULE_DTB_DDOS_BASE_ADDR       = 0x01010000,
-    MODULE_DTB_RAM_BASE_ADDR        = 0x01100000,
-
-    /* TRPG          */
-    MODULE_TRPG_RX_BASE_ADDR                = 0x00000000,         
-    MODULE_TRPG_TX_BASE_ADDR                = 0x00400000, 
-    MODULE_TRPG_TX_GLB_BASE_ADDR            = 0x00600000,
-    MODULE_TRPG_TX_ETM_PORT_BASE_ADDR       = 0x00610000,
-    MODULE_TRPG_RX_RAM_BASE_ADDR            = 0x00200000,
-    MODULE_TRPG_TX_RAM_BASE_ADDR            = 0x00620000,
-    MODULE_TRPG_TX_ETM_RAM_BASE_ADDR        = 0x00710000,
-    MODULE_TRPG_TX_TODTIME_RAM_BASE_ADDR    = 0x00720000,
-    
-
-
-    /* TSN          */
-    MODULE_TSN_PORT0_BASE_ADDR      = 0x00000000,
-    MODULE_TSN_PORT1_BASE_ADDR      = 0x00004000,
-    MODULE_TSN_PORT2_BASE_ADDR      = 0x00008000,
-    MODULE_TSN_PORT3_BASE_ADDR      = 0x0000C000,
-      
-} MODULE_BASE_ADDR_E;
-
-DPP_STATUS dpp_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data);
-DPP_STATUS dpp_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data);
-
-DPP_STATUS dpp_se_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data);
-DPP_STATUS dpp_se_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data);
-
-DPP_STATUS dpp_se_alg_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data);
-DPP_STATUS dpp_se_alg_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data);
-
-DPP_STATUS dpp_ppu_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data);
-DPP_STATUS dpp_ppu_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef _DPP_MODULE_H_
+#define _DPP_MODULE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "zxic_common.h"
+#include "dpp_dev.h"
+#include "dpp_type_api.h"
+
+/**  for PPU*/
+#define DPP_PPU_CLUSTER_NUM (6)
+
+#define DPP_PPU_ME_EXCEPTION_MAX (8)
+#define DPP_PPU_CLUSTER_MEPERCLS_NUM (8)
+#define DPP_PPU_CLUSTER_SPACE_SIZE (0x00008000)
+#define DPP_MAX_CHCHK_NUM (50)
+
+#define DPP_TRPG_PORT_NUM (32)
+#define DPP_TRPG_PORT_SPACE_SIZE (0x10000)
+
+#define DPP_TRPG_RAM_NUM (16)
+#define DPP_TRPG_RAM_SPACE_SIZE (0x10000)
+
+#define DPP_TSN_PORT_NUM (4)
+#define DPP_TSN_PORT_SPACE_SIZE (0x4000)
+
+typedef enum dpp_module_e {
+	CFG = 1, /**<  @brief 1*/
+	NPPU, /**<  @brief 2*/
+	PPU, /**<  @brief 3*/
+	ETM, /**<  @brief 4*/
+	STAT, /**<  @brief 5*/
+	CAR, /**<  @brief 6*/
+	SE, /**<  @brief 7*/
+	SMMU0 = SE, /**<  @brief 7*/
+	SMMU1 = SE, /**<  @brief 7*/
+	DTB, /**<  @brief 8*/
+	TRPG, /**<  @brief 9*/
+	TSN, /**<  @brief 10*/
+	AXI, /**<  @brief 11*/
+	PTPTM, /**<  @brief 12*/
+	DTB4K, /**<  @brief 13*/
+	STAT4K, /**<  @brief 14*/
+	PPU4K, /**<  @brief 15*/
+	SE4K, /**<  @brief 16*/
+	SMMU14K, /**<  @brief 17*/
+	MODULE_MAX
+} DPP_MODULE_E;
+
+typedef enum module_tm_e {
+	MODULE_TM_CFGMT = 0,
+	MODULE_TM_OLIF = 1,
+	MODULE_TM_CGAVD = 2,
+	MODULE_TM_TMMU = 3,
+	MODULE_TM_SHAP = 4,
+	MODULE_TM_CRDT = 5,
+	MODULE_TM_QMU = 6,
+	MODULE_TM_MAX
+} MODULE_TM_E;
+
+/*NP 在PICE中的偏移地址*/
+#define SYS_VF_NP_BASE_OFFSET 0X0000000000
+/*NP 在DPU中的基地址*/
+
+#define SYS_NP_BASE_ADDR 0x6218000000
+#define SYS_NP_BASE_ADDR0 0x00000000
+#define SYS_NP_BASE_ADDR1 0x02000000
+
+/**  sub system base address*/
+typedef enum sys_base_addr_e {
+	SYS_NPPU_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00000000),
+	SYS_PPU_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00080000),
+	SYS_ETM_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00180000),
+	SYS_STAT_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00200000),
+	SYS_SE_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00280000),
+	SYS_SE_SMMU0_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00300000),
+	SYS_SE_SMMU1_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00310000),
+	//    SYS_TRPG_BASE_ADDR               = (SYS_NP_BASE_ADDR0 + 0x00320000),
+	SYS_CFG_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00330000),
+	SYS_PTP0_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00340000),
+	SYS_PTP1_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00344000),
+	SYS_TSN_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00350000),
+	SYS_TRPG_BASE_ADDR = (SYS_NP_BASE_ADDR0 + 0x00400000),
+
+	SYS_DTB_BASE_ADDR = (SYS_NP_BASE_ADDR1 + 0x00000000),
+	SYS_AXIM0_BASE_ADDR = (SYS_NP_BASE_ADDR1 + 0x01400000),
+	SYS_AXIM1_BASE_ADDR = (SYS_NP_BASE_ADDR1 + 0x01408000),
+	SYS_AXI_CONV_BASE_ADDR = (SYS_NP_BASE_ADDR1 + 0x01410000),
+	SYS_AXIS_BASE_ADDR = (SYS_NP_BASE_ADDR1 + 0x01418000),
+	SYS_TLB_BASE_ADDR = (SYS_NP_BASE_ADDR1 + 0x01420000),
+
+	SYS_MAX_BASE_ADDR = 0x20000000,
+} SYS_BASE_ADDR_E;
+
+/**  module base address*/
+typedef enum module_base_addr_e {
+	/* CFG         */
+	MODULE_CFG_PCIE_BASE_ADDR = 0x00000000,
+	MODULE_CFG_DMA_BASE_ADDR = 0x00001000,
+	MODULE_CFG_CSR_BASE_ADDR = 0x00003000,
+
+	/* NPPU       */
+	MODULE_NPPU_MR_CFG_BASE_ADDR = 0x00000000,
+	MODULE_NPPU_PKTRX_CFG_BASE_ADDR = 0x00000800,
+	MODULE_NPPU_PKTRX_STAT_BASE_ADDR = 0x00001000,
+	MODULE_NPPU_IDMA_CFG_BASE_ADDR = 0x00001800,
+	MODULE_NPPU_IDMA_STAT_BASE_ADDR = 0x00002000,
+	MODULE_NPPU_PBU_CFG_BASE_ADDR = 0x00002800,
+	MODULE_NPPU_PBU_STAT_BASE_ADDR = 0x00003000,
+	MODULE_NPPU_ISU_CFG_BASE_ADDR = 0x00003800,
+	MODULE_NPPU_ISU_STAT_BASE_ADDR = 0x00004000,
+	MODULE_NPPU_ODMA_CFG_BASE_ADDR = 0x00004800,
+	MODULE_NPPU_ODMA_STAT_BASE_ADDR = 0x00005000,
+	MODULE_NPPU_OAM_CFG_BASE_ADDR = 0x00005800,
+	MODULE_NPPU_OAM_STAT_BASE_ADDR = 0x00006000,
+	MODULE_NPPU_OAM_INT_IDX0_BASE_ADDR = 0x00006800,
+	MODULE_NPPU_OAM_INT_IDX1_BASE_ADDR = 0x00007000,
+
+	/* PPU         */
+	MODULE_PPU_CSR_BASE_ADDR = 0x00000000,
+	MODULE_PPU_DBG_BASE_ADDR = 0x00000800,
+	MODULE_CLUSTER0_BASE_ADDR = 0x00008000,
+	MODULE_CLUSTER1_BASE_ADDR = 0x00010000,
+	MODULE_CLUSTER2_BASE_ADDR = 0x00018000,
+	MODULE_CLUSTER3_BASE_ADDR = 0x00020000,
+
+	/* TM          */
+	MODULE_TM_CFGMT_BASE_ADDR = 0x00000000,
+	MODULE_TM_OLIF_BASE_ADDR = 0x00020000,
+	MODULE_TM_CGAVD_BASE_ADDR = 0x00030000,
+	MODULE_TM_TMMU_BASE_ADDR = 0x00040000,
+	MODULE_TM_SHAP_BASE_ADDR = 0x00050000,
+	MODULE_TM_CRDT_BASE_ADDR = 0x00060000,
+	MODULE_TM_QMU_BASE_ADDR = 0x00070000,
+
+	/* STAT        */
+	MODULE_STAT_CAR0_BASE_ADDR = 0x00000000,
+	MODULE_STAT_ETCAM_BASE_ADDR = 0x00002000,
+	MODULE_STAT_GLBL_BASE_ADDR = 0x00003000,
+
+	/* SE          */
+	MODULE_SE_ALG_BASE_ADDR = 0x00000000,
+	MODULE_SE_KSCHD_BASE_ADDR = 0x00004000,
+	MODULE_SE_RSCHD_BASE_ADDR = 0x00008000,
+	MODULE_SE_PARSER_BASE_ADDR = 0x0000c000,
+	MODULE_SE_AS_BASE_ADDR = 0x00010000,
+	MODULE_SE_CFG_BASE_ADDR = 0x00014000,
+
+	/* SMMU0          */
+	MODULE_SE_SMMU0_BASE_ADDR = 0x00000000,
+
+	/* SMMU1          */
+	MODULE_SE_SMMU1_BASE_ADDR = 0x00000000,
+	MODULE_SE_CMMU_BASE_ADDR = 0x00004000,
+
+	/* DTB          */
+	MODULE_DTB_ENQ_BASE_ADDR = 0x00000000,
+	MODULE_DTB_CFG_BASE_ADDR = 0x01000000,
+	MODULE_DTB_DDOS_BASE_ADDR = 0x01010000,
+	MODULE_DTB_RAM_BASE_ADDR = 0x01100000,
+
+	/* TRPG          */
+	MODULE_TRPG_RX_BASE_ADDR = 0x00000000,
+	MODULE_TRPG_TX_BASE_ADDR = 0x00400000,
+	MODULE_TRPG_TX_GLB_BASE_ADDR = 0x00600000,
+	MODULE_TRPG_TX_ETM_PORT_BASE_ADDR = 0x00610000,
+	MODULE_TRPG_RX_RAM_BASE_ADDR = 0x00200000,
+	MODULE_TRPG_TX_RAM_BASE_ADDR = 0x00620000,
+	MODULE_TRPG_TX_ETM_RAM_BASE_ADDR = 0x00710000,
+	MODULE_TRPG_TX_TODTIME_RAM_BASE_ADDR = 0x00720000,
+
+	/* TSN          */
+	MODULE_TSN_PORT0_BASE_ADDR = 0x00000000,
+	MODULE_TSN_PORT1_BASE_ADDR = 0x00004000,
+	MODULE_TSN_PORT2_BASE_ADDR = 0x00008000,
+	MODULE_TSN_PORT3_BASE_ADDR = 0x0000C000,
+
+} MODULE_BASE_ADDR_E;
+
+DPP_STATUS dpp_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data);
+DPP_STATUS dpp_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data);
+
+DPP_STATUS dpp_se_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data);
+DPP_STATUS dpp_se_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data);
+
+DPP_STATUS dpp_se_alg_read(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+						   ZXIC_UINT32 *p_data);
+DPP_STATUS dpp_se_alg_write(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+							ZXIC_UINT32 *p_data);
+
+DPP_STATUS dpp_ppu_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data);
+DPP_STATUS dpp_ppu_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_nppu_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_nppu_reg.h
index 38d66671f0aec1bf1c6f14caac2456b39a591b11..2714bd7cec33eeaff615534b0d92e15e270e12fa 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_nppu_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_nppu_reg.h
@@ -3,3848 +3,3279 @@
 #define _DPP_NPPU_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_nppu_mr_cfg_cfg_shap_param_t
-{
-    ZXIC_UINT32 shap_en;
-    ZXIC_UINT32 shap_rate;
-}DPP_NPPU_MR_CFG_CFG_SHAP_PARAM_T;
-
-typedef struct dpp_nppu_mr_cfg_cfg_shap_token_t
-{
-    ZXIC_UINT32 cfg_shap_plen_offset;
-    ZXIC_UINT32 cfg_shap_token;
-}DPP_NPPU_MR_CFG_CFG_SHAP_TOKEN_T;
-
-typedef struct dpp_nppu_mr_cfg_idle_ptr_fifo_aful_th_t
-{
-    ZXIC_UINT32 idle_ptr3_fifo_aful_th;
-    ZXIC_UINT32 idle_ptr2_fifo_aful_th;
-    ZXIC_UINT32 idle_ptr1_fifo_aful_th;
-    ZXIC_UINT32 idle_ptr0_fifo_aful_th;
-}DPP_NPPU_MR_CFG_IDLE_PTR_FIFO_AFUL_TH_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos_port_cfg_t
-{
-    ZXIC_UINT32 cos3_port_cfg;
-    ZXIC_UINT32 cos2_port_cfg;
-    ZXIC_UINT32 cos1_port_cfg;
-    ZXIC_UINT32 cos0_port_cfg;
-}DPP_NPPU_MR_CFG_MR_COS_PORT_CFG_T;
-
-typedef struct dpp_nppu_pktrx_cfg_ind_status_t
-{
-    ZXIC_UINT32 ind_access_done;
-}DPP_NPPU_PKTRX_CFG_IND_STATUS_T;
-
-typedef struct dpp_nppu_pktrx_cfg_ind_cmd_t
-{
-    ZXIC_UINT32 ind_rd_or_wr;
-    ZXIC_UINT32 ind_mem_id;
-    ZXIC_UINT32 ind_mem_addr;
-}DPP_NPPU_PKTRX_CFG_IND_CMD_T;
-
-typedef struct dpp_nppu_pktrx_cfg_ind_data0_t
-{
-    ZXIC_UINT32 ind_dat0;
-}DPP_NPPU_PKTRX_CFG_IND_DATA0_T;
-
-typedef struct dpp_nppu_pktrx_cfg_ind_data1_t
-{
-    ZXIC_UINT32 ind_dat1;
-}DPP_NPPU_PKTRX_CFG_IND_DATA1_T;
-
-typedef struct dpp_nppu_pktrx_cfg_ind_data2_t
-{
-    ZXIC_UINT32 ind_dat2;
-}DPP_NPPU_PKTRX_CFG_IND_DATA2_T;
-
-typedef struct dpp_nppu_pktrx_cfg_ind_data3_t
-{
-    ZXIC_UINT32 ind_dat3;
-}DPP_NPPU_PKTRX_CFG_IND_DATA3_T;
-
-typedef struct dpp_nppu_pktrx_cfg_ind_data4_t
-{
-    ZXIC_UINT32 ind_dat4;
-}DPP_NPPU_PKTRX_CFG_IND_DATA4_T;
-
-typedef struct dpp_nppu_pktrx_cfg_ind_data5_t
-{
-    ZXIC_UINT32 ind_dat5;
-}DPP_NPPU_PKTRX_CFG_IND_DATA5_T;
-
-typedef struct dpp_nppu_pktrx_cfg_ind_data6_t
-{
-    ZXIC_UINT32 ind_dat6;
-}DPP_NPPU_PKTRX_CFG_IND_DATA6_T;
-
-typedef struct dpp_nppu_pktrx_cfg_ind_data7_t
-{
-    ZXIC_UINT32 ind_dat7;
-}DPP_NPPU_PKTRX_CFG_IND_DATA7_T;
-
-typedef struct dpp_nppu_pktrx_cfg_tcam_0_cmd_t
-{
-    ZXIC_UINT32 cfg_vben;
-    ZXIC_UINT32 cfg_vbi;
-    ZXIC_UINT32 cfg_t_strwc;
-    ZXIC_UINT32 tcam0_sm;
-    ZXIC_UINT32 tcam0_smen;
-    ZXIC_UINT32 tcam0_rm;
-    ZXIC_UINT32 tcam0_rmen;
-    ZXIC_UINT32 tcam0_enable;
-    ZXIC_UINT32 tcam0_flush;
-    ZXIC_UINT32 tcam0_unload;
-    ZXIC_UINT32 tcam0_unload_addr;
-}DPP_NPPU_PKTRX_CFG_TCAM_0_CMD_T;
-
-typedef struct dpp_nppu_pktrx_cfg_tcam_1_cmd_t
-{
-    ZXIC_UINT32 tcam1_sm;
-    ZXIC_UINT32 tcam1_smen;
-    ZXIC_UINT32 tcam1_rm;
-    ZXIC_UINT32 tcam1_rmen;
-    ZXIC_UINT32 tcam1_enable;
-    ZXIC_UINT32 tcam1_flush;
-    ZXIC_UINT32 tcam1_unload;
-    ZXIC_UINT32 tcam1_unload_addr;
-}DPP_NPPU_PKTRX_CFG_TCAM_1_CMD_T;
-
-typedef struct dpp_nppu_pktrx_cfg_port_en_0_t
-{
-    ZXIC_UINT32 cfg_isch_port_en_0;
-}DPP_NPPU_PKTRX_CFG_PORT_EN_0_T;
-
-typedef struct dpp_nppu_pktrx_cfg_port_en_1_t
-{
-    ZXIC_UINT32 cfg_isch_port_en_1;
-}DPP_NPPU_PKTRX_CFG_PORT_EN_1_T;
-
-typedef struct dpp_nppu_pktrx_cfg_port_en_2_t
-{
-    ZXIC_UINT32 cfg_isch_port_en_2;
-}DPP_NPPU_PKTRX_CFG_PORT_EN_2_T;
-
-typedef struct dpp_nppu_pktrx_cfg_port_en_3_t
-{
-    ZXIC_UINT32 cfg_port_change_en_0;
-    ZXIC_UINT32 cfg_port_change_en_1;
-    ZXIC_UINT32 cfg_isch_port_en_3;
-}DPP_NPPU_PKTRX_CFG_PORT_EN_3_T;
-
-typedef struct dpp_nppu_pktrx_cfg_cfg_port_l2_offset_mode_0_t
-{
-    ZXIC_UINT32 cfg_port_l2_offset_mode_0;
-}DPP_NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_0_T;
-
-typedef struct dpp_nppu_pktrx_cfg_cfg_port_l2_offset_mode_1_t
-{
-    ZXIC_UINT32 cfg_port_l2_offset_mode_1;
-}DPP_NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_1_T;
-
-typedef struct dpp_nppu_pktrx_cfg_cfg_port_l2_offset_mode_2_t
-{
-    ZXIC_UINT32 cfg_port_l2_offset_mode_2;
-}DPP_NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_2_T;
-
-typedef struct dpp_nppu_pktrx_cfg_cfg_port_l2_offset_mode_3_t
-{
-    ZXIC_UINT32 cfg_port_l2_offset_mode_3;
-}DPP_NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_3_T;
-
-typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_0_t
-{
-    ZXIC_UINT32 cfg_isch_fc_mode_0;
-}DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_0_T;
-
-typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_1_t
-{
-    ZXIC_UINT32 cfg_isch_fc_mode_1;
-}DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_1_T;
-
-typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_2_t
-{
-    ZXIC_UINT32 cfg_isch_fc_mode_2;
-}DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_2_T;
-
-typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_3_t
-{
-    ZXIC_UINT32 cfg_isch_fc_mode_3;
-}DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_3_T;
-
-typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_4_t
-{
-    ZXIC_UINT32 cfg_isch_fc_mode_4;
-}DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_4_T;
-
-typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_5_t
-{
-    ZXIC_UINT32 cfg_isch_fc_mode_5;
-}DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_5_T;
-
-typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_6_t
-{
-    ZXIC_UINT32 cfg_isch_fc_mode_6;
-}DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_6_T;
-
-typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_7_t
-{
-    ZXIC_UINT32 cfg_pfu_aging_en;
-    ZXIC_UINT32 cfg_isch_aging_en;
-    ZXIC_UINT32 cfg_isch_fc_mode_7;
-}DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_7_T;
-
-typedef struct dpp_nppu_pktrx_cfg_cfg_isch_aging_th_t
-{
-    ZXIC_UINT32 cfg_pfu_delay_cycle;
-    ZXIC_UINT32 cfg_isch_aging_th;
-}DPP_NPPU_PKTRX_CFG_CFG_ISCH_AGING_TH_T;
-
-typedef struct dpp_nppu_pktrx_cfg_isch_fifo_th_0_t
-{
-    ZXIC_UINT32 cfg_sch_fifo3_fc_th;
-    ZXIC_UINT32 cfg_sch_fifo2_fc_th;
-    ZXIC_UINT32 cfg_sch_fifo1_fc_th;
-    ZXIC_UINT32 cfg_sch_fifo0_fc_th;
-}DPP_NPPU_PKTRX_CFG_ISCH_FIFO_TH_0_T;
-
-typedef struct dpp_nppu_pktrx_cfg_isch_cfg_1_t
-{
-    ZXIC_UINT32 cfg_parser_max_len_en;
-    ZXIC_UINT32 cfg_parser_max_len;
-    ZXIC_UINT32 cfg_parser_min_len_en;
-    ZXIC_UINT32 cfg_parser_min_len;
-    ZXIC_UINT32 sp_sch_sel;
-}DPP_NPPU_PKTRX_CFG_ISCH_CFG_1_T;
-
-typedef struct dpp_nppu_pktrx_cfg_tcam_0_vld_t
-{
-    ZXIC_UINT32 cfg_tcam0_vld;
-}DPP_NPPU_PKTRX_CFG_TCAM_0_VLD_T;
-
-typedef struct dpp_nppu_pktrx_cfg_tcam_1_vld_t
-{
-    ZXIC_UINT32 cfg_tcam1_vld;
-}DPP_NPPU_PKTRX_CFG_TCAM_1_VLD_T;
-
-typedef struct dpp_nppu_pktrx_cfg_cpu_port_en_mask_t
-{
-    ZXIC_UINT32 cpu_port_en_mask;
-}DPP_NPPU_PKTRX_CFG_CPU_PORT_EN_MASK_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_glbal_cfg_0_t
-{
-    ZXIC_UINT32 pktrx_glbal_cfg_0;
-}DPP_NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_0_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_glbal_cfg_1_t
-{
-    ZXIC_UINT32 pktrx_glbal_cfg_1;
-}DPP_NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_1_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_glbal_cfg_2_t
-{
-    ZXIC_UINT32 pktrx_glbal_cfg_2;
-}DPP_NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_2_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_glbal_cfg_3_t
-{
-    ZXIC_UINT32 pktrx_glbal_cfg_3;
-}DPP_NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_3_T;
-
-typedef struct dpp_nppu_pktrx_cfg_nppu_start_t
-{
-    ZXIC_UINT32 nppu_start;
-}DPP_NPPU_PKTRX_CFG_NPPU_START_T;
-
-typedef struct dpp_nppu_pktrx_stat_ind_status_t
-{
-    ZXIC_UINT32 ind_access_done;
-}DPP_NPPU_PKTRX_STAT_IND_STATUS_T;
-
-typedef struct dpp_nppu_pktrx_stat_ind_cmd_t
-{
-    ZXIC_UINT32 ind_rd_or_wr;
-    ZXIC_UINT32 ind_mem_id;
-    ZXIC_UINT32 ind_mem_addr;
-}DPP_NPPU_PKTRX_STAT_IND_CMD_T;
-
-typedef struct dpp_nppu_pktrx_stat_ind_data0_t
-{
-    ZXIC_UINT32 ind_dat0;
-}DPP_NPPU_PKTRX_STAT_IND_DATA0_T;
-
-typedef struct dpp_nppu_idma_cfg_debug_cnt_ovfl_mode_t
-{
-    ZXIC_UINT32 debug_cnt_ovfl_mode;
-}DPP_NPPU_IDMA_CFG_DEBUG_CNT_OVFL_MODE_T;
-
-typedef struct dpp_nppu_idma_stat_ind_status_t
-{
-    ZXIC_UINT32 ind_access_done;
-}DPP_NPPU_IDMA_STAT_IND_STATUS_T;
-
-typedef struct dpp_nppu_idma_stat_ind_cmd_t
-{
-    ZXIC_UINT32 ind_rd_or_wr;
-    ZXIC_UINT32 ind_mem_id;
-    ZXIC_UINT32 ind_mem_addr;
-}DPP_NPPU_IDMA_STAT_IND_CMD_T;
-
-typedef struct dpp_nppu_idma_stat_ind_data0_t
-{
-    ZXIC_UINT32 ind_data0;
-}DPP_NPPU_IDMA_STAT_IND_DATA0_T;
-
-typedef struct dpp_nppu_pbu_cfg_ind_status_t
-{
-    ZXIC_UINT32 ind_access_done;
-}DPP_NPPU_PBU_CFG_IND_STATUS_T;
-
-typedef struct dpp_nppu_pbu_cfg_ind_cmd_t
-{
-    ZXIC_UINT32 ind_rd_or_wr;
-    ZXIC_UINT32 ind_mem_id;
-    ZXIC_UINT32 ind_mem_addr;
-}DPP_NPPU_PBU_CFG_IND_CMD_T;
-
-typedef struct dpp_nppu_pbu_cfg_ind_data0_t
-{
-    ZXIC_UINT32 ind_data0;
-}DPP_NPPU_PBU_CFG_IND_DATA0_T;
-
-typedef struct dpp_nppu_pbu_cfg_ind_data1_t
-{
-    ZXIC_UINT32 ind_data1;
-}DPP_NPPU_PBU_CFG_IND_DATA1_T;
-
-typedef struct dpp_nppu_pbu_cfg_ind_data2_t
-{
-    ZXIC_UINT32 ind_data2;
-}DPP_NPPU_PBU_CFG_IND_DATA2_T;
-
-typedef struct dpp_nppu_pbu_cfg_ind_data3_t
-{
-    ZXIC_UINT32 ind_data3;
-}DPP_NPPU_PBU_CFG_IND_DATA3_T;
-
-typedef struct dpp_nppu_pbu_cfg_ind_data4_t
-{
-    ZXIC_UINT32 ind_data4;
-}DPP_NPPU_PBU_CFG_IND_DATA4_T;
-
-typedef struct dpp_nppu_pbu_cfg_ind_data5_t
-{
-    ZXIC_UINT32 ind_data5;
-}DPP_NPPU_PBU_CFG_IND_DATA5_T;
-
-typedef struct dpp_nppu_pbu_cfg_ind_data6_t
-{
-    ZXIC_UINT32 ind_data6;
-}DPP_NPPU_PBU_CFG_IND_DATA6_T;
-
-typedef struct dpp_nppu_pbu_cfg_ind_data7_t
-{
-    ZXIC_UINT32 ind_data7;
-}DPP_NPPU_PBU_CFG_IND_DATA7_T;
-
-typedef struct dpp_nppu_pbu_cfg_idma_public_th_t
-{
-    ZXIC_UINT32 idma_public_th;
-}DPP_NPPU_PBU_CFG_IDMA_PUBLIC_TH_T;
-
-typedef struct dpp_nppu_pbu_cfg_lif_public_th_t
-{
-    ZXIC_UINT32 lif_public_th;
-}DPP_NPPU_PBU_CFG_LIF_PUBLIC_TH_T;
-
-typedef struct dpp_nppu_pbu_cfg_idma_total_th_t
-{
-    ZXIC_UINT32 idma_total_th;
-}DPP_NPPU_PBU_CFG_IDMA_TOTAL_TH_T;
-
-typedef struct dpp_nppu_pbu_cfg_lif_total_th_t
-{
-    ZXIC_UINT32 lif_total_th;
-}DPP_NPPU_PBU_CFG_LIF_TOTAL_TH_T;
-
-typedef struct dpp_nppu_pbu_cfg_mc_total_th_t
-{
-    ZXIC_UINT32 mc_total_th;
-}DPP_NPPU_PBU_CFG_MC_TOTAL_TH_T;
-
-typedef struct dpp_nppu_pbu_cfg_mc_cos10_th_t
-{
-    ZXIC_UINT32 mc_cos1_mode;
-    ZXIC_UINT32 mc_cos0_mode;
-    ZXIC_UINT32 mc_cos1_th;
-    ZXIC_UINT32 mc_cos0_th;
-}DPP_NPPU_PBU_CFG_MC_COS10_TH_T;
-
-typedef struct dpp_nppu_pbu_cfg_mc_cos32_th_t
-{
-    ZXIC_UINT32 mc_cos3_mode;
-    ZXIC_UINT32 mc_cos2_mode;
-    ZXIC_UINT32 mc_cos3_th;
-    ZXIC_UINT32 mc_cos2_th;
-}DPP_NPPU_PBU_CFG_MC_COS32_TH_T;
-
-typedef struct dpp_nppu_pbu_cfg_mc_cos54_th_t
-{
-    ZXIC_UINT32 mc_cos5_mode;
-    ZXIC_UINT32 mc_cos4_mode;
-    ZXIC_UINT32 mc_cos5_th;
-    ZXIC_UINT32 mc_cos4_th;
-}DPP_NPPU_PBU_CFG_MC_COS54_TH_T;
-
-typedef struct dpp_nppu_pbu_cfg_mc_cos76_th_t
-{
-    ZXIC_UINT32 mc_cos7_mode;
-    ZXIC_UINT32 mc_cos6_mode;
-    ZXIC_UINT32 mc_cos7_th;
-    ZXIC_UINT32 mc_cos6_th;
-}DPP_NPPU_PBU_CFG_MC_COS76_TH_T;
-
-typedef struct dpp_nppu_pbu_cfg_debug_cnt_ovfl_mode_t
-{
-    ZXIC_UINT32 debug_cnt_ovfl_mode;
-}DPP_NPPU_PBU_CFG_DEBUG_CNT_OVFL_MODE_T;
-
-typedef struct dpp_nppu_pbu_cfg_se_key_aful_negate_cfg_t
-{
-    ZXIC_UINT32 se_key_aful_negate_cfg;
-}DPP_NPPU_PBU_CFG_SE_KEY_AFUL_NEGATE_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_sa_flag_t
-{
-    ZXIC_UINT32 sa_flag;
-}DPP_NPPU_PBU_CFG_SA_FLAG_T;
-
-typedef struct dpp_nppu_pbu_stat_ind_data_t
-{
-    ZXIC_UINT32 ind_data;
-}DPP_NPPU_PBU_STAT_IND_DATA_T;
-
-typedef struct dpp_nppu_pbu_stat_ind_status_t
-{
-    ZXIC_UINT32 ind_access_done;
-}DPP_NPPU_PBU_STAT_IND_STATUS_T;
-
-typedef struct dpp_nppu_pbu_stat_ind_cmd_t
-{
-    ZXIC_UINT32 ind_rd_or_wr;
-    ZXIC_UINT32 ind_mem_id;
-    ZXIC_UINT32 ind_mem_addr;
-}DPP_NPPU_PBU_STAT_IND_CMD_T;
-
-typedef struct dpp_nppu_pbu_stat_total_cnt_t
-{
-    ZXIC_UINT32 total_cnt;
-}DPP_NPPU_PBU_STAT_TOTAL_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_idma_pub_cnt_t
-{
-    ZXIC_UINT32 idma_pub_cnt;
-}DPP_NPPU_PBU_STAT_IDMA_PUB_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_lif_pub_cnt_t
-{
-    ZXIC_UINT32 lif_pub_cnt;
-}DPP_NPPU_PBU_STAT_LIF_PUB_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_mc_total_cnt_t
-{
-    ZXIC_UINT32 mc_total_cnt;
-}DPP_NPPU_PBU_STAT_MC_TOTAL_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_pbu_thram_init_done_t
-{
-    ZXIC_UINT32 pbu_thram_init_done;
-}DPP_NPPU_PBU_STAT_PBU_THRAM_INIT_DONE_T;
-
-typedef struct dpp_nppu_pbu_stat_ifb_fptr_init_done_t
-{
-    ZXIC_UINT32 ifb_fptr_init_done;
-}DPP_NPPU_PBU_STAT_IFB_FPTR_INIT_DONE_T;
-
-typedef struct dpp_nppu_isu_cfg_weight_normal_uc_t
-{
-    ZXIC_UINT32 weight_normal_uc;
-}DPP_NPPU_ISU_CFG_WEIGHT_NORMAL_UC_T;
-
-typedef struct dpp_nppu_isu_cfg_fabric_or_saip_t
-{
-    ZXIC_UINT32 fabric_or_saip;
-}DPP_NPPU_ISU_CFG_FABRIC_OR_SAIP_T;
-
-typedef struct dpp_nppu_isu_stat_ind_status_t
-{
-    ZXIC_UINT32 ind_access_done;
-}DPP_NPPU_ISU_STAT_IND_STATUS_T;
-
-typedef struct dpp_nppu_isu_stat_ind_cmd_t
-{
-    ZXIC_UINT32 ind_rd_or_wr;
-    ZXIC_UINT32 ind_mem_id;
-    ZXIC_UINT32 ind_mem_addr;
-}DPP_NPPU_ISU_STAT_IND_CMD_T;
-
-typedef struct dpp_nppu_isu_stat_ind_dat0_t
-{
-    ZXIC_UINT32 ind_dat0;
-}DPP_NPPU_ISU_STAT_IND_DAT0_T;
-
-typedef struct dpp_nppu_odma_cfg_ind_access_done_t
-{
-    ZXIC_UINT32 ind_access_done;
-}DPP_NPPU_ODMA_CFG_IND_ACCESS_DONE_T;
-
-typedef struct dpp_nppu_odma_cfg_ind_command_t
-{
-    ZXIC_UINT32 ind_rd_or_wr;
-    ZXIC_UINT32 ind_mem_id;
-    ZXIC_UINT32 ind_mem_addr;
-}DPP_NPPU_ODMA_CFG_IND_COMMAND_T;
-
-typedef struct dpp_nppu_odma_cfg_ind_dat0_t
-{
-    ZXIC_UINT32 ind_dat0;
-}DPP_NPPU_ODMA_CFG_IND_DAT0_T;
-
-typedef struct dpp_nppu_odma_cfg_ind_dat1_t
-{
-    ZXIC_UINT32 ind_dat1;
-}DPP_NPPU_ODMA_CFG_IND_DAT1_T;
-
-typedef struct dpp_nppu_odma_cfg_fabric_or_saip_t
-{
-    ZXIC_UINT32 fabric_or_saip;
-}DPP_NPPU_ODMA_CFG_FABRIC_OR_SAIP_T;
-
-typedef struct dpp_nppu_odma_cfg_max_pkt_len_t
-{
-    ZXIC_UINT32 max_pkt_len;
-}DPP_NPPU_ODMA_CFG_MAX_PKT_LEN_T;
-
-typedef struct dpp_nppu_odma_cfg_age_en_t
-{
-    ZXIC_UINT32 age_en;
-}DPP_NPPU_ODMA_CFG_AGE_EN_T;
-
-typedef struct dpp_nppu_odma_cfg_age_mode_t
-{
-    ZXIC_UINT32 age_mode;
-}DPP_NPPU_ODMA_CFG_AGE_MODE_T;
-
-typedef struct dpp_nppu_odma_cfg_age_value_time_t
-{
-    ZXIC_UINT32 age_value_time;
-}DPP_NPPU_ODMA_CFG_AGE_VALUE_TIME_T;
-
-typedef struct dpp_nppu_odma_cfg_age_value_room_t
-{
-    ZXIC_UINT32 age_value_room;
-}DPP_NPPU_ODMA_CFG_AGE_VALUE_ROOM_T;
-
-typedef struct dpp_nppu_odma_cfg_age_out_cnt_t
-{
-    ZXIC_UINT32 age_out_cnt;
-}DPP_NPPU_ODMA_CFG_AGE_OUT_CNT_T;
-
-typedef struct dpp_nppu_odma_cfg_token_value_a_t
-{
-    ZXIC_UINT32 token_value_a;
-}DPP_NPPU_ODMA_CFG_TOKEN_VALUE_A_T;
-
-typedef struct dpp_nppu_odma_cfg_token_value_b_t
-{
-    ZXIC_UINT32 token_value_b;
-}DPP_NPPU_ODMA_CFG_TOKEN_VALUE_B_T;
-
-typedef struct dpp_nppu_odma_cfg_cfg_shap_en_p0_t
-{
-    ZXIC_UINT32 cfg_shap_en_p0;
-}DPP_NPPU_ODMA_CFG_CFG_SHAP_EN_P0_T;
-
-typedef struct dpp_nppu_odma_cfg_cfg_shap_en_p1_t
-{
-    ZXIC_UINT32 cfg_shap_en_p1;
-}DPP_NPPU_ODMA_CFG_CFG_SHAP_EN_P1_T;
-
-typedef struct dpp_nppu_odma_cfg_cfg_shap_en_tm_t
-{
-    ZXIC_UINT32 cfg_shap_en_tm;
-}DPP_NPPU_ODMA_CFG_CFG_SHAP_EN_TM_T;
-
-typedef struct dpp_nppu_odma_stat_ind_status_t
-{
-    ZXIC_UINT32 ind_access_done;
-}DPP_NPPU_ODMA_STAT_IND_STATUS_T;
-
-typedef struct dpp_nppu_odma_stat_ind_cmd_t
-{
-    ZXIC_UINT32 ind_rd_or_wr;
-    ZXIC_UINT32 ind_mem_id;
-    ZXIC_UINT32 ind_mem_addr;
-}DPP_NPPU_ODMA_STAT_IND_CMD_T;
-
-typedef struct dpp_nppu_odma_stat_ind_data0_t
-{
-    ZXIC_UINT32 ind_dat0;
-}DPP_NPPU_ODMA_STAT_IND_DATA0_T;
-
-typedef struct dpp_nppu_odma_stat_debug_cnt_cfg_t
-{
-    ZXIC_UINT32 debug_cnt_ovf_mode;
-    ZXIC_UINT32 debug_cnt_rdclr_mode;
-    ZXIC_UINT32 user_cnt_value;
-}DPP_NPPU_ODMA_STAT_DEBUG_CNT_CFG_T;
-
-typedef struct dpp_nppu_oam_cfg_bfd_firstchk_th_t
-{
-    ZXIC_UINT32 bfd_firstchk_th;
-}DPP_NPPU_OAM_CFG_BFD_FIRSTCHK_TH_T;
-
-typedef struct dpp_nppu_pbu_cfg_memid_0_pbu_fc_idmath_ram_t
-{
-    ZXIC_UINT32 lif_th_15;
-    ZXIC_UINT32 lif_prv_15;
-    ZXIC_UINT32 idma_prv_15;
-    ZXIC_UINT32 idma_th_cos0_15;
-    ZXIC_UINT32 idma_th_cos1_15;
-    ZXIC_UINT32 idma_th_cos2_15;
-    ZXIC_UINT32 idma_th_cos3_15;
-    ZXIC_UINT32 idma_th_cos4_15;
-    ZXIC_UINT32 idma_th_cos5_15;
-    ZXIC_UINT32 idma_th_cos6_15;
-    ZXIC_UINT32 idma_th_cos7_15;
-}DPP_NPPU_PBU_CFG_MEMID_0_PBU_FC_IDMATH_RAM_T;
-
-typedef struct dpp_nppu_pbu_cfg_memid_1_pbu_fc_macth_ram_t
-{
-    ZXIC_UINT32 cos7_th;
-    ZXIC_UINT32 cos6_th;
-    ZXIC_UINT32 cos5_th;
-    ZXIC_UINT32 cos4_th;
-    ZXIC_UINT32 cos3_th;
-    ZXIC_UINT32 cos2_th;
-    ZXIC_UINT32 cos1_th;
-    ZXIC_UINT32 cos0_th;
-}DPP_NPPU_PBU_CFG_MEMID_1_PBU_FC_MACTH_RAM_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_1_all_kind_port_cnt_t
-{
-    ZXIC_UINT32 peak_port_cnt;
-    ZXIC_UINT32 current_port_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_1_ALL_KIND_PORT_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_2_ppu_pbu_ifb_req_vld_cnt_t
-{
-    ZXIC_UINT32 ppu_pbu_ifb_req_vld_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_2_PPU_PBU_IFB_REQ_VLD_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_ifb_rsp_vld_cnt_t
-{
-    ZXIC_UINT32 pbu_ppu_ifb_rsp_vld_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_IFB_RSP_VLD_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_2_odma_pbu_recy_ptr_vld_cnt_t
-{
-    ZXIC_UINT32 odma_pbu_recy_ptr_vld_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_2_ODMA_PBU_RECY_PTR_VLD_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_2_ppu_pbu_mcode_pf_req_cnt_t
-{
-    ZXIC_UINT32 ppu_pbu_mcode_pf_req_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_2_PPU_PBU_MCODE_PF_REQ_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_rsp_cnt_t
-{
-    ZXIC_UINT32 pbu_ppu_mcode_pf_rsp_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_RSP_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_2_ppu_pbu_logic_pf_req_cnt_t
-{
-    ZXIC_UINT32 ppu_pbu_logic_pf_req_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_2_PPU_PBU_LOGIC_PF_REQ_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_rsp_cnt_t
-{
-    ZXIC_UINT32 pbu_ppu_logic_pf_rsp_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_RSP_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_2_ppu_use_ptr_pulse_cnt_t
-{
-    ZXIC_UINT32 ppu_use_ptr_pulse_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_2_PPU_USE_PTR_PULSE_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_2_ppu_pbu_wb_vld_cnt_t
-{
-    ZXIC_UINT32 ppu_pbu_wb_vld_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_2_PPU_PBU_WB_VLD_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_reorder_para_vld_cnt_t
-{
-    ZXIC_UINT32 pbu_ppu_reorder_para_vld_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_REORDER_PARA_VLD_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_2_se_pbu_dpi_key_vld_cnt_t
-{
-    ZXIC_UINT32 se_pbu_dpi_key_vld_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_2_SE_PBU_DPI_KEY_VLD_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_2_pbu_se_dpi_rsp_datvld_cnt_t
-{
-    ZXIC_UINT32 pbu_se_dpi_rsp_datvld_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_2_PBU_SE_DPI_RSP_DATVLD_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd1_cnt_t
-{
-    ZXIC_UINT32 odma_pbu_ifb_rd1_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD1_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd2_cnt_t
-{
-    ZXIC_UINT32 odma_pbu_ifb_rd2_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD2_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_no_rsp_cnt_t
-{
-    ZXIC_UINT32 pbu_ppu_mcode_pf_no_rsp_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_NO_RSP_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_no_rsp_cnt_t
-{
-    ZXIC_UINT32 pbu_ppu_logic_pf_no_rsp_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_NO_RSP_CNT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_3_cpu_rd_ifb_data_t
-{
-    ZXIC_UINT32 cpu_rd_ifb_data;
-}DPP_NPPU_PBU_STAT_MEMID_3_CPU_RD_IFB_DATA_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_4_mux_sel_rgt_t
-{
-    ZXIC_UINT32 current_port_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_4_MUX_SEL_RGT_T;
-
-typedef struct dpp_nppu_pbu_stat_memid_5_port_pub_cnt_t
-{
-    ZXIC_UINT32 port_pub_cnt;
-}DPP_NPPU_PBU_STAT_MEMID_5_PORT_PUB_CNT_T;
-
-typedef struct dpp_nppu_idma_stat_memid_1_idma_o_isu_pkt_pulse_total_cnt_t
-{
-    ZXIC_UINT32 idma_o_isu_pkt_pulse_total_cnt;
-}DPP_NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_PKT_PULSE_TOTAL_CNT_T;
-
-typedef struct dpp_nppu_idma_stat_memid_1_idma_o_isu_epkt_pulse_total_cnt_t
-{
-    ZXIC_UINT32 idma_o_isu_epkt_pulse_total_cnt;
-}DPP_NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_EPKT_PULSE_TOTAL_CNT_T;
-
-typedef struct dpp_nppu_idma_stat_memid_1_idma_dispkt_pulse_total_cnt_t
-{
-    ZXIC_UINT32 idma_dispkt_pulse_total_cnt;
-}DPP_NPPU_IDMA_STAT_MEMID_1_IDMA_DISPKT_PULSE_TOTAL_CNT_T;
-
-typedef struct dpp_nppu_idma_stat_memid_0_idma_o_isu_pkt_pulse_cnt_t
-{
-    ZXIC_UINT32 idma_o_isu_pkt_pulse_cnt;
-}DPP_NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_PKT_PULSE_CNT_T;
-
-typedef struct dpp_nppu_idma_stat_memid_0_idma_o_isu_epkt_pulse_cnt_t
-{
-    ZXIC_UINT32 idma_o_isu_epkt_pulse_cnt;
-}DPP_NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_EPKT_PULSE_CNT_T;
-
-typedef struct dpp_nppu_idma_stat_memid_0_idma_dispkt_pulse_cnt_t
-{
-    ZXIC_UINT32 idma_dispkt_pulse_cnt;
-}DPP_NPPU_IDMA_STAT_MEMID_0_IDMA_DISPKT_PULSE_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_ind_access_states_t
-{
-    ZXIC_UINT32 ind_access_done;
-}DPP_NPPU_MR_CFG_IND_ACCESS_STATES_T;
-
-typedef struct dpp_nppu_mr_cfg_ind_access_cmd0_t
-{
-    ZXIC_UINT32 wr_mode;
-    ZXIC_UINT32 rd_or_wr;
-    ZXIC_UINT32 ind_access_addr0;
-}DPP_NPPU_MR_CFG_IND_ACCESS_CMD0_T;
-
-typedef struct dpp_nppu_mr_cfg_ind_access_data0_t
-{
-    ZXIC_UINT32 ind_access_data0;
-}DPP_NPPU_MR_CFG_IND_ACCESS_DATA0_T;
-
-typedef struct dpp_nppu_mr_cfg_ind_access_data1_t
-{
-    ZXIC_UINT32 ind_access_data1;
-}DPP_NPPU_MR_CFG_IND_ACCESS_DATA1_T;
-
-typedef struct dpp_nppu_mr_cfg_ind_access_cmd1_t
-{
-    ZXIC_UINT32 ind_access_addr1;
-}DPP_NPPU_MR_CFG_IND_ACCESS_CMD1_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_init_done_t
-{
-    ZXIC_UINT32 mr_init_done;
-}DPP_NPPU_MR_CFG_MR_INIT_DONE_T;
-
-typedef struct dpp_nppu_mr_cfg_cnt_mode_reg_t
-{
-    ZXIC_UINT32 cfgmt_count_rd_mode;
-    ZXIC_UINT32 cfgmt_count_overflow_mode;
-}DPP_NPPU_MR_CFG_CNT_MODE_REG_T;
-
-typedef struct dpp_nppu_mr_cfg_cfg_ecc_bypass_read_t
-{
-    ZXIC_UINT32 cfg_ecc_bypass_read;
-}DPP_NPPU_MR_CFG_CFG_ECC_BYPASS_READ_T;
-
-typedef struct dpp_nppu_mr_cfg_cfg_rep_mod_t
-{
-    ZXIC_UINT32 cfg_rep_mod;
-}DPP_NPPU_MR_CFG_CFG_REP_MOD_T;
-
-typedef struct dpp_nppu_mr_cfg_block_ptr_fifo_aful_th_t
-{
-    ZXIC_UINT32 block_ptr3_fifo_aful_th;
-    ZXIC_UINT32 block_ptr2_fifo_aful_th;
-    ZXIC_UINT32 block_ptr1_fifo_aful_th;
-    ZXIC_UINT32 block_ptr0_fifo_aful_th;
-}DPP_NPPU_MR_CFG_BLOCK_PTR_FIFO_AFUL_TH_T;
-
-typedef struct dpp_nppu_mr_cfg_pre_rcv_ptr_fifo_aful_th_t
-{
-    ZXIC_UINT32 pre_rcv_ptr3_fifo_aful_th;
-    ZXIC_UINT32 pre_rcv_ptr2_fifo_aful_th;
-    ZXIC_UINT32 pre_rcv_ptr1_fifo_aful_th;
-    ZXIC_UINT32 pre_rcv_ptr0_fifo_aful_th;
-}DPP_NPPU_MR_CFG_PRE_RCV_PTR_FIFO_AFUL_TH_T;
-
-typedef struct dpp_nppu_mr_cfg_mgid_fifo_aful_th_t
-{
-    ZXIC_UINT32 mgid3_fifo_aful_th;
-    ZXIC_UINT32 mgid2_fifo_aful_th;
-    ZXIC_UINT32 mgid1_fifo_aful_th;
-    ZXIC_UINT32 mgid0_fifo_aful_th;
-}DPP_NPPU_MR_CFG_MGID_FIFO_AFUL_TH_T;
-
-typedef struct dpp_nppu_mr_cfg_rep_cmd_fifo_aful_th_t
-{
-    ZXIC_UINT32 rep_cmd3_fifo_aful_th;
-    ZXIC_UINT32 rep_cmd2_fifo_aful_th;
-    ZXIC_UINT32 rep_cmd1_fifo_aful_th;
-    ZXIC_UINT32 rep_cmd0_fifo_aful_th;
-}DPP_NPPU_MR_CFG_REP_CMD_FIFO_AFUL_TH_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_int_mask_1_t
-{
-    ZXIC_UINT32 free_ptr0_fifo_full_mask;
-    ZXIC_UINT32 free_ptr1_fifo_full_mask;
-    ZXIC_UINT32 free_ptr2_fifo_full_mask;
-    ZXIC_UINT32 free_ptr3_fifo_full_mask;
-    ZXIC_UINT32 block_ptr0_fifo_full_mask;
-    ZXIC_UINT32 block_ptr1_fifo_full_mask;
-    ZXIC_UINT32 block_ptr2_fifo_full_mask;
-    ZXIC_UINT32 block_ptr3_fifo_full_mask;
-    ZXIC_UINT32 mgid0_fifo_full_mask;
-    ZXIC_UINT32 mgid1_fifo_full_mask;
-    ZXIC_UINT32 mgid2_fifo_full_mask;
-    ZXIC_UINT32 mgid3_fifo_full_mask;
-    ZXIC_UINT32 pre_rcv_ptr0_fifo_full_mask;
-    ZXIC_UINT32 pre_rcv_ptr1_fifo_full_mask;
-    ZXIC_UINT32 pre_rcv_ptr2_fifo_full_mask;
-    ZXIC_UINT32 pre_rcv_ptr3_fifo_full_mask;
-    ZXIC_UINT32 rep_cmd0_fifo_full_mask;
-    ZXIC_UINT32 rep_cmd1_fifo_full_mask;
-    ZXIC_UINT32 rep_cmd2_fifo_full_mask;
-    ZXIC_UINT32 rep_cmd3_fifo_full_mask;
-}DPP_NPPU_MR_CFG_MR_INT_MASK_1_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_int_mask_2_t
-{
-    ZXIC_UINT32 free_ptr0_fifo_udf_mask;
-    ZXIC_UINT32 free_ptr1_fifo_udf_mask;
-    ZXIC_UINT32 free_ptr2_fifo_udf_mask;
-    ZXIC_UINT32 free_ptr3_fifo_udf_mask;
-    ZXIC_UINT32 block_ptr0_fifo_udf_mask;
-    ZXIC_UINT32 block_ptr1_fifo_udf_mask;
-    ZXIC_UINT32 block_ptr2_fifo_udf_mask;
-    ZXIC_UINT32 block_ptr3_fifo_udf_mask;
-    ZXIC_UINT32 mgid0_fifo_udf_mask;
-    ZXIC_UINT32 mgid1_fifo_udf_mask;
-    ZXIC_UINT32 mgid2_fifo_udf_mask;
-    ZXIC_UINT32 mgid3_fifo_udf_mask;
-    ZXIC_UINT32 pre_rcv_ptr0_fifo_udf_mask;
-    ZXIC_UINT32 pre_rcv_ptr1_fifo_udf_mask;
-    ZXIC_UINT32 pre_rcv_ptr2_fifo_udf_mask;
-    ZXIC_UINT32 pre_rcv_ptr3_fifo_udf_mask;
-    ZXIC_UINT32 rep_cmd0_fifo_udf_mask;
-    ZXIC_UINT32 rep_cmd1_fifo_udf_mask;
-    ZXIC_UINT32 rep_cmd2_fifo_udf_mask;
-    ZXIC_UINT32 rep_cmd3_fifo_udf_mask;
-}DPP_NPPU_MR_CFG_MR_INT_MASK_2_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_int_mask_3_t
-{
-    ZXIC_UINT32 free_ptr0_fifo_ovf_mask;
-    ZXIC_UINT32 free_ptr1_fifo_ovf_mask;
-    ZXIC_UINT32 free_ptr2_fifo_ovf_mask;
-    ZXIC_UINT32 free_ptr3_fifo_ovf_mask;
-    ZXIC_UINT32 block_ptr0_fifo_ovf_mask;
-    ZXIC_UINT32 block_ptr1_fifo_ovf_mask;
-    ZXIC_UINT32 block_ptr2_fifo_ovf_mask;
-    ZXIC_UINT32 block_ptr3_fifo_ovf_mask;
-    ZXIC_UINT32 mgid0_fifo_ovf_mask;
-    ZXIC_UINT32 mgid1_fifo_ovf_mask;
-    ZXIC_UINT32 mgid2_fifo_ovf_mask;
-    ZXIC_UINT32 mgid3_fifo_ovf_mask;
-    ZXIC_UINT32 pre_rcv_ptr0_fifo_ovf_mask;
-    ZXIC_UINT32 pre_rcv_ptr1_fifo_ovf_mask;
-    ZXIC_UINT32 pre_rcv_ptr2_fifo_ovf_mask;
-    ZXIC_UINT32 pre_rcv_ptr3_fifo_ovf_mask;
-    ZXIC_UINT32 rep_cmd0_fifo_ovf_mask;
-    ZXIC_UINT32 rep_cmd1_fifo_ovf_mask;
-    ZXIC_UINT32 rep_cmd2_fifo_ovf_mask;
-    ZXIC_UINT32 rep_cmd3_fifo_ovf_mask;
-}DPP_NPPU_MR_CFG_MR_INT_MASK_3_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_int_mask_4_t
-{
-    ZXIC_UINT32 data_buf0_ram_parity_err_mask;
-    ZXIC_UINT32 data_buf1_ram_parity_err_mask;
-    ZXIC_UINT32 data_buf2_ram_parity_err_mask;
-    ZXIC_UINT32 data_buf3_ram_parity_err_mask;
-    ZXIC_UINT32 mlt_ecc_single_err_mask;
-    ZXIC_UINT32 free_ptr0_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 free_ptr1_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 free_ptr2_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 free_ptr3_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 block_ptr0_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 block_ptr1_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 block_ptr2_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 block_ptr3_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 mgid0_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 mgid1_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 mgid2_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 mgid3_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 pre_rcv_ptr0_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 pre_rcv_ptr1_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 pre_rcv_ptr2_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 pre_rcv_ptr3_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 rep_cmd0_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 rep_cmd1_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 rep_cmd2_fifo_ecc_single_err_mask;
-    ZXIC_UINT32 rep_cmd3_fifo_ecc_single_err_mask;
-}DPP_NPPU_MR_CFG_MR_INT_MASK_4_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_states_1_t
-{
-    ZXIC_UINT32 free_ptr0_fifo_full;
-    ZXIC_UINT32 free_ptr1_fifo_full;
-    ZXIC_UINT32 free_ptr2_fifo_full;
-    ZXIC_UINT32 free_ptr3_fifo_full;
-    ZXIC_UINT32 block_ptr0_fifo_full;
-    ZXIC_UINT32 block_ptr1_fifo_full;
-    ZXIC_UINT32 block_ptr2_fifo_full;
-    ZXIC_UINT32 block_ptr3_fifo_full;
-    ZXIC_UINT32 mgid0_fifo_full;
-    ZXIC_UINT32 mgid1_fifo_full;
-    ZXIC_UINT32 mgid2_fifo_full;
-    ZXIC_UINT32 mgid3_fifo_full;
-    ZXIC_UINT32 pre_rcv_ptr0_fifo_full;
-    ZXIC_UINT32 pre_rcv_ptr1_fifo_full;
-    ZXIC_UINT32 pre_rcv_ptr2_fifo_full;
-    ZXIC_UINT32 pre_rcv_ptr3_fifo_full;
-    ZXIC_UINT32 rep_cmd0_fifo_full;
-    ZXIC_UINT32 rep_cmd1_fifo_full;
-    ZXIC_UINT32 rep_cmd2_fifo_full;
-    ZXIC_UINT32 rep_cmd3_fifo_full;
-}DPP_NPPU_MR_CFG_MR_STATES_1_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_states_2_t
-{
-    ZXIC_UINT32 free_ptr0_fifo_udf;
-    ZXIC_UINT32 free_ptr1_fifo_udf;
-    ZXIC_UINT32 free_ptr2_fifo_udf;
-    ZXIC_UINT32 free_ptr3_fifo_udf;
-    ZXIC_UINT32 block_ptr0_fifo_udf;
-    ZXIC_UINT32 block_ptr1_fifo_udf;
-    ZXIC_UINT32 block_ptr2_fifo_udf;
-    ZXIC_UINT32 block_ptr3_fifo_udf;
-    ZXIC_UINT32 mgid0_fifo_udf;
-    ZXIC_UINT32 mgid1_fifo_udf;
-    ZXIC_UINT32 mgid2_fifo_udf;
-    ZXIC_UINT32 mgid3_fifo_udf;
-    ZXIC_UINT32 pre_rcv_ptr0_fifo_udf;
-    ZXIC_UINT32 pre_rcv_ptr1_fifo_udf;
-    ZXIC_UINT32 pre_rcv_ptr2_fifo_udf;
-    ZXIC_UINT32 pre_rcv_ptr3_fifo_udf;
-    ZXIC_UINT32 rep_cmd0_fifo_udf;
-    ZXIC_UINT32 rep_cmd1_fifo_udf;
-    ZXIC_UINT32 rep_cmd2_fifo_udf;
-    ZXIC_UINT32 rep_cmd3_fifo_udf;
-}DPP_NPPU_MR_CFG_MR_STATES_2_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_states_3_t
-{
-    ZXIC_UINT32 free_ptr0_fifo_ovf;
-    ZXIC_UINT32 free_ptr1_fifo_ovf;
-    ZXIC_UINT32 free_ptr2_fifo_ovf;
-    ZXIC_UINT32 free_ptr3_fifo_ovf;
-    ZXIC_UINT32 block_ptr0_fifo_ovf;
-    ZXIC_UINT32 block_ptr1_fifo_ovf;
-    ZXIC_UINT32 block_ptr2_fifo_ovf;
-    ZXIC_UINT32 block_ptr3_fifo_ovf;
-    ZXIC_UINT32 mgid0_fifo_ovf;
-    ZXIC_UINT32 mgid1_fifo_ovf;
-    ZXIC_UINT32 mgid2_fifo_ovf;
-    ZXIC_UINT32 mgid3_fifo_ovf;
-    ZXIC_UINT32 pre_rcv_ptr0_fifo_ovf;
-    ZXIC_UINT32 pre_rcv_ptr1_fifo_ovf;
-    ZXIC_UINT32 pre_rcv_ptr2_fifo_ovf;
-    ZXIC_UINT32 pre_rcv_ptr3_fifo_ovf;
-    ZXIC_UINT32 rep_cmd0_fifo_ovf;
-    ZXIC_UINT32 rep_cmd1_fifo_ovf;
-    ZXIC_UINT32 rep_cmd2_fifo_ovf;
-    ZXIC_UINT32 rep_cmd3_fifo_ovf;
-}DPP_NPPU_MR_CFG_MR_STATES_3_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_states_4_t
-{
-    ZXIC_UINT32 data_buf0_ram_parity_err;
-    ZXIC_UINT32 data_buf1_ram_parity_err;
-    ZXIC_UINT32 data_buf2_ram_parity_err;
-    ZXIC_UINT32 data_buf3_ram_parity_err;
-    ZXIC_UINT32 mlt_ecc_single_err;
-    ZXIC_UINT32 free_ptr0_fifo_ecc_single_err;
-    ZXIC_UINT32 free_ptr1_fifo_ecc_single_err;
-    ZXIC_UINT32 free_ptr2_fifo_ecc_single_err;
-    ZXIC_UINT32 free_ptr3_fifo_ecc_single_err;
-    ZXIC_UINT32 block_ptr0_fifo_ecc_single_err;
-    ZXIC_UINT32 block_ptr1_fifo_ecc_single_err;
-    ZXIC_UINT32 block_ptr2_fifo_ecc_single_err;
-    ZXIC_UINT32 block_ptr3_fifo_ecc_single_err;
-    ZXIC_UINT32 mgid0_fifo_ecc_single_err;
-    ZXIC_UINT32 mgid1_fifo_ecc_single_err;
-    ZXIC_UINT32 mgid2_fifo_ecc_single_err;
-    ZXIC_UINT32 mgid3_fifo_ecc_single_err;
-    ZXIC_UINT32 pre_rcv_ptr0_fifo_ecc_single_err;
-    ZXIC_UINT32 pre_rcv_ptr1_fifo_ecc_single_err;
-    ZXIC_UINT32 pre_rcv_ptr2_fifo_ecc_single_err;
-    ZXIC_UINT32 pre_rcv_ptr3_fifo_ecc_single_err;
-    ZXIC_UINT32 rep_cmd0_fifo_ecc_single_err;
-    ZXIC_UINT32 rep_cmd1_fifo_ecc_single_err;
-    ZXIC_UINT32 rep_cmd2_fifo_ecc_single_err;
-    ZXIC_UINT32 rep_cmd3_fifo_ecc_single_err;
-}DPP_NPPU_MR_CFG_MR_STATES_4_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_states_5_t
-{
-    ZXIC_UINT32 mlt_ecc_double_err;
-    ZXIC_UINT32 free_ptr0_fifo_ecc_double_err;
-    ZXIC_UINT32 free_ptr1_fifo_ecc_double_err;
-    ZXIC_UINT32 free_ptr2_fifo_ecc_double_err;
-    ZXIC_UINT32 free_ptr3_fifo_ecc_double_err;
-    ZXIC_UINT32 block_ptr0_fifo_ecc_double_err;
-    ZXIC_UINT32 block_ptr1_fifo_ecc_double_err;
-    ZXIC_UINT32 block_ptr2_fifo_ecc_double_err;
-    ZXIC_UINT32 block_ptr3_fifo_ecc_double_err;
-    ZXIC_UINT32 mgid0_fifo_ecc_double_err;
-    ZXIC_UINT32 mgid1_fifo_ecc_double_err;
-    ZXIC_UINT32 mgid2_fifo_ecc_double_err;
-    ZXIC_UINT32 mgid3_fifo_ecc_double_err;
-    ZXIC_UINT32 pre_rcv_ptr0_fifo_ecc_double_err;
-    ZXIC_UINT32 pre_rcv_ptr1_fifo_ecc_double_err;
-    ZXIC_UINT32 pre_rcv_ptr2_fifo_ecc_double_err;
-    ZXIC_UINT32 pre_rcv_ptr3_fifo_ecc_double_err;
-    ZXIC_UINT32 rep_cmd0_fifo_ecc_double_err;
-    ZXIC_UINT32 rep_cmd1_fifo_ecc_double_err;
-    ZXIC_UINT32 rep_cmd2_fifo_ecc_double_err;
-    ZXIC_UINT32 rep_cmd3_fifo_ecc_double_err;
-}DPP_NPPU_MR_CFG_MR_STATES_5_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_states_6_t
-{
-    ZXIC_UINT32 free_ptr0_fifo_empty;
-    ZXIC_UINT32 free_ptr1_fifo_empty;
-    ZXIC_UINT32 free_ptr2_fifo_empty;
-    ZXIC_UINT32 free_ptr3_fifo_empty;
-    ZXIC_UINT32 block_ptr0_fifo_empty;
-    ZXIC_UINT32 block_ptr1_fifo_empty;
-    ZXIC_UINT32 block_ptr2_fifo_empty;
-    ZXIC_UINT32 block_ptr3_fifo_empty;
-    ZXIC_UINT32 mgid0_fifo_empty;
-    ZXIC_UINT32 mgid1_fifo_empty;
-    ZXIC_UINT32 mgid2_fifo_empty;
-    ZXIC_UINT32 mgid3_fifo_empty;
-    ZXIC_UINT32 pre_rcv_ptr0_fifo_empty;
-    ZXIC_UINT32 pre_rcv_ptr1_fifo_empty;
-    ZXIC_UINT32 pre_rcv_ptr2_fifo_empty;
-    ZXIC_UINT32 pre_rcv_ptr3_fifo_empty;
-    ZXIC_UINT32 rep_cmd0_fifo_empty;
-    ZXIC_UINT32 rep_cmd1_fifo_empty;
-    ZXIC_UINT32 rep_cmd2_fifo_empty;
-    ZXIC_UINT32 rep_cmd3_fifo_empty;
-}DPP_NPPU_MR_CFG_MR_STATES_6_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_states_7_t
-{
-    ZXIC_UINT32 cos0_is_rep_busy;
-    ZXIC_UINT32 cos1_is_rep_busy;
-    ZXIC_UINT32 cos2_is_rep_busy;
-    ZXIC_UINT32 cos3_is_rep_busy;
-    ZXIC_UINT32 block_ptr0_fifo_non_sop_ren_rdy;
-    ZXIC_UINT32 block_ptr1_fifo_non_sop_ren_rdy;
-    ZXIC_UINT32 block_ptr2_fifo_non_sop_ren_rdy;
-    ZXIC_UINT32 block_ptr3_fifo_non_sop_ren_rdy;
-    ZXIC_UINT32 pre_rcv_ptr0_fifo_non_sop_ren_rdy;
-    ZXIC_UINT32 pre_rcv_ptr1_fifo_non_sop_ren_rdy;
-    ZXIC_UINT32 pre_rcv_ptr2_fifo_non_sop_ren_rdy;
-    ZXIC_UINT32 pre_rcv_ptr3_fifo_non_sop_ren_rdy;
-    ZXIC_UINT32 port_shap_rdy;
-    ZXIC_UINT32 mr_lif_group0_rdy_3;
-    ZXIC_UINT32 mr_lif_group0_rdy_2;
-    ZXIC_UINT32 mr_lif_group0_rdy_1;
-    ZXIC_UINT32 mr_lif_group0_rdy_0;
-    ZXIC_UINT32 pktrx_pfc_rdy_3;
-    ZXIC_UINT32 pktrx_pfc_rdy_2;
-    ZXIC_UINT32 pktrx_pfc_rdy_1;
-    ZXIC_UINT32 pktrx_pfc_rdy_0;
-    ZXIC_UINT32 pktrx_link_rdy;
-}DPP_NPPU_MR_CFG_MR_STATES_7_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_states_8_t
-{
-    ZXIC_UINT32 mr_head;
-}DPP_NPPU_MR_CFG_MR_STATES_8_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_sop_in_cnt_t
-{
-    ZXIC_UINT32 mr_sop_in_cnt;
-}DPP_NPPU_MR_CFG_MR_SOP_IN_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_eop_in_cnt_t
-{
-    ZXIC_UINT32 mr_eop_in_cnt;
-}DPP_NPPU_MR_CFG_MR_EOP_IN_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_sop_out_cnt_t
-{
-    ZXIC_UINT32 mr_sop_out_cnt;
-}DPP_NPPU_MR_CFG_MR_SOP_OUT_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_eop_out_cnt_t
-{
-    ZXIC_UINT32 mr_eop_out_cnt;
-}DPP_NPPU_MR_CFG_MR_EOP_OUT_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos0_in_cnt_t
-{
-    ZXIC_UINT32 mr_cos0_in_cnt;
-}DPP_NPPU_MR_CFG_MR_COS0_IN_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos1_in_cnt_t
-{
-    ZXIC_UINT32 mr_cos1_in_cnt;
-}DPP_NPPU_MR_CFG_MR_COS1_IN_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos2_in_cnt_t
-{
-    ZXIC_UINT32 mr_cos2_in_cnt;
-}DPP_NPPU_MR_CFG_MR_COS2_IN_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos3_in_cnt_t
-{
-    ZXIC_UINT32 mr_cos3_in_cnt;
-}DPP_NPPU_MR_CFG_MR_COS3_IN_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos0_out_cnt_t
-{
-    ZXIC_UINT32 mr_cos0_out_cnt;
-}DPP_NPPU_MR_CFG_MR_COS0_OUT_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos1_out_cnt_t
-{
-    ZXIC_UINT32 mr_cos1_out_cnt;
-}DPP_NPPU_MR_CFG_MR_COS1_OUT_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos2_out_cnt_t
-{
-    ZXIC_UINT32 mr_cos2_out_cnt;
-}DPP_NPPU_MR_CFG_MR_COS2_OUT_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos3_out_cnt_t
-{
-    ZXIC_UINT32 mr_cos3_out_cnt;
-}DPP_NPPU_MR_CFG_MR_COS3_OUT_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_err_in_cnt_t
-{
-    ZXIC_UINT32 mr_err_in_cnt;
-}DPP_NPPU_MR_CFG_MR_ERR_IN_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos0_sop_in_cnt_t
-{
-    ZXIC_UINT32 mr_cos0_sop_in_cnt;
-}DPP_NPPU_MR_CFG_MR_COS0_SOP_IN_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos0_eop_in_cnt_t
-{
-    ZXIC_UINT32 mr_cos0_eop_in_cnt;
-}DPP_NPPU_MR_CFG_MR_COS0_EOP_IN_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos1_sop_in_cnt_t
-{
-    ZXIC_UINT32 mr_cos1_sop_in_cnt;
-}DPP_NPPU_MR_CFG_MR_COS1_SOP_IN_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos1_eop_in_cnt_t
-{
-    ZXIC_UINT32 mr_cos1_eop_in_cnt;
-}DPP_NPPU_MR_CFG_MR_COS1_EOP_IN_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos2_sop_in_cnt_t
-{
-    ZXIC_UINT32 mr_cos2_sop_in_cnt;
-}DPP_NPPU_MR_CFG_MR_COS2_SOP_IN_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos2_eop_in_cnt_t
-{
-    ZXIC_UINT32 mr_cos2_eop_in_cnt;
-}DPP_NPPU_MR_CFG_MR_COS2_EOP_IN_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos3_sop_in_cnt_t
-{
-    ZXIC_UINT32 mr_cos3_sop_in_cnt;
-}DPP_NPPU_MR_CFG_MR_COS3_SOP_IN_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos3_eop_in_cnt_t
-{
-    ZXIC_UINT32 mr_cos3_eop_in_cnt;
-}DPP_NPPU_MR_CFG_MR_COS3_EOP_IN_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos0_in_err_cnt_t
-{
-    ZXIC_UINT32 mr_cos0_in_err_cnt;
-}DPP_NPPU_MR_CFG_MR_COS0_IN_ERR_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos1_in_err_cnt_t
-{
-    ZXIC_UINT32 mr_cos1_in_err_cnt;
-}DPP_NPPU_MR_CFG_MR_COS1_IN_ERR_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos2_in_err_cnt_t
-{
-    ZXIC_UINT32 mr_cos2_in_err_cnt;
-}DPP_NPPU_MR_CFG_MR_COS2_IN_ERR_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos3_in_err_cnt_t
-{
-    ZXIC_UINT32 mr_cos3_in_err_cnt;
-}DPP_NPPU_MR_CFG_MR_COS3_IN_ERR_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos0_sop_out_cnt_t
-{
-    ZXIC_UINT32 mr_cos0_sop_out_cnt;
-}DPP_NPPU_MR_CFG_MR_COS0_SOP_OUT_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos0_eop_out_cnt_t
-{
-    ZXIC_UINT32 mr_cos0_eop_out_cnt;
-}DPP_NPPU_MR_CFG_MR_COS0_EOP_OUT_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos1_sop_out_cnt_t
-{
-    ZXIC_UINT32 mr_cos1_sop_out_cnt;
-}DPP_NPPU_MR_CFG_MR_COS1_SOP_OUT_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos1_eop_out_cnt_t
-{
-    ZXIC_UINT32 mr_cos1_eop_out_cnt;
-}DPP_NPPU_MR_CFG_MR_COS1_EOP_OUT_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos2_sop_out_cnt_t
-{
-    ZXIC_UINT32 mr_cos2_sop_out_cnt;
-}DPP_NPPU_MR_CFG_MR_COS2_SOP_OUT_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos2_eop_out_cnt_t
-{
-    ZXIC_UINT32 mr_cos2_eop_out_cnt;
-}DPP_NPPU_MR_CFG_MR_COS2_EOP_OUT_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos3_sop_out_cnt_t
-{
-    ZXIC_UINT32 mr_cos3_sop_out_cnt;
-}DPP_NPPU_MR_CFG_MR_COS3_SOP_OUT_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_cos3_eop_out_cnt_t
-{
-    ZXIC_UINT32 mr_cos3_eop_out_cnt;
-}DPP_NPPU_MR_CFG_MR_COS3_EOP_OUT_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_mlt_unvld_cnt_t
-{
-    ZXIC_UINT32 mr_mlt_unvld_cnt;
-}DPP_NPPU_MR_CFG_MR_MLT_UNVLD_CNT_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_sop_eop_match_cfg_t
-{
-    ZXIC_UINT32 mr_sop_eop_macth_en;
-    ZXIC_UINT32 mr_sop_eop_macth_dicard_th;
-}DPP_NPPU_MR_CFG_MR_SOP_EOP_MATCH_CFG_T;
-
-typedef struct dpp_nppu_mr_cfg_mr_mlt_unvld_mgid_t
-{
-    ZXIC_UINT32 mr_mlt_unvld_mgid;
-}DPP_NPPU_MR_CFG_MR_MLT_UNVLD_MGID_T;
-
-typedef struct dpp_nppu_pktrx_cfg_isch_fifo_th_1_t
-{
-    ZXIC_UINT32 cfg_sch_fifo7_fc_th;
-    ZXIC_UINT32 cfg_sch_fifo6_fc_th;
-    ZXIC_UINT32 cfg_sch_fifo5_fc_th;
-    ZXIC_UINT32 cfg_sch_fifo4_fc_th;
-}DPP_NPPU_PKTRX_CFG_ISCH_FIFO_TH_1_T;
-
-typedef struct dpp_nppu_pktrx_cfg_isch_fifo_th_2_t
-{
-    ZXIC_UINT32 cfg_sch_fifo3_drop_th;
-    ZXIC_UINT32 cfg_sch_fifo1_drop_th;
-    ZXIC_UINT32 cfg_sch_fifo0_drop_th;
-    ZXIC_UINT32 cfg_sch_fifo8_fc_th;
-}DPP_NPPU_PKTRX_CFG_ISCH_FIFO_TH_2_T;
-
-typedef struct dpp_nppu_pktrx_cfg_isch_fifo_th_3_t
-{
-    ZXIC_UINT32 cfg_sch_fifo6_drop_th;
-    ZXIC_UINT32 cfg_sch_fifo5_drop_th;
-    ZXIC_UINT32 cfg_sch_fifo4_drop_th;
-    ZXIC_UINT32 cfg_sch_fifo2_drop_th;
-}DPP_NPPU_PKTRX_CFG_ISCH_FIFO_TH_3_T;
-
-typedef struct dpp_nppu_pktrx_cfg_isch_fifo_th_4_t
-{
-    ZXIC_UINT32 cfg_sch_fifo9_fc_th;
-    ZXIC_UINT32 cfg_sch_fifo9_drop_th;
-    ZXIC_UINT32 cfg_sch_fifo8_drop_th;
-    ZXIC_UINT32 cfg_sch_fifo7_drop_th;
-}DPP_NPPU_PKTRX_CFG_ISCH_FIFO_TH_4_T;
-
-typedef struct dpp_nppu_pktrx_cfg_isch_cfg_0_t
-{
-    ZXIC_UINT32 cfg_sch_wrr1_weight1;
-}DPP_NPPU_PKTRX_CFG_ISCH_CFG_0_T;
-
-typedef struct dpp_nppu_pktrx_cfg_hdu_ex_tpid_0_t
-{
-    ZXIC_UINT32 cfg_type0;
-    ZXIC_UINT32 cfg_type1;
-}DPP_NPPU_PKTRX_CFG_HDU_EX_TPID_0_T;
-
-typedef struct dpp_nppu_pktrx_cfg_hdu_ex_tpid_1_t
-{
-    ZXIC_UINT32 cfg_type2;
-    ZXIC_UINT32 cfg_type3;
-}DPP_NPPU_PKTRX_CFG_HDU_EX_TPID_1_T;
-
-typedef struct dpp_nppu_pktrx_cfg_hdu_int_tpid_0_t
-{
-    ZXIC_UINT32 cfg_inner_type0;
-    ZXIC_UINT32 cfg_inner_type1;
-}DPP_NPPU_PKTRX_CFG_HDU_INT_TPID_0_T;
-
-typedef struct dpp_nppu_pktrx_cfg_hdu_int_tpid_1_t
-{
-    ZXIC_UINT32 cfg_inner_type2;
-    ZXIC_UINT32 cfg_inner_type3;
-}DPP_NPPU_PKTRX_CFG_HDU_INT_TPID_1_T;
-
-typedef struct dpp_nppu_pktrx_cfg_hdu_hdlc_0_t
-{
-    ZXIC_UINT32 hdlc_cfg0_type;
-    ZXIC_UINT32 hdlc_cfg1_type;
-}DPP_NPPU_PKTRX_CFG_HDU_HDLC_0_T;
-
-typedef struct dpp_nppu_pktrx_cfg_hdu_hdlc_1_t
-{
-    ZXIC_UINT32 hdlc_cfg2_type;
-    ZXIC_UINT32 hdlc_cfg3_type;
-}DPP_NPPU_PKTRX_CFG_HDU_HDLC_1_T;
-
-typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l3type_0_t
-{
-    ZXIC_UINT32 cfg_l3_type0;
-    ZXIC_UINT32 cfg_l3_type1;
-}DPP_NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_0_T;
-
-typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l3type_1_t
-{
-    ZXIC_UINT32 cfg_l3_type2;
-    ZXIC_UINT32 cfg_l3_type3;
-}DPP_NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_1_T;
-
-typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l3type_2_t
-{
-    ZXIC_UINT32 cfg_l3_type4;
-    ZXIC_UINT32 cfg_l3_type5;
-}DPP_NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_2_T;
-
-typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l3type_3_t
-{
-    ZXIC_UINT32 cfg_l3_type6;
-    ZXIC_UINT32 cfg_l3_type7;
-}DPP_NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_3_T;
-
-typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l4type_0_t
-{
-    ZXIC_UINT32 cfg_l4_type0;
-    ZXIC_UINT32 cfg_l4_type1;
-    ZXIC_UINT32 cfg_l4_type2;
-    ZXIC_UINT32 cfg_l4_type3;
-}DPP_NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_0_T;
-
-typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l4type_1_t
-{
-    ZXIC_UINT32 cfg_l4_type4;
-    ZXIC_UINT32 cfg_l4_type5;
-    ZXIC_UINT32 cfg_l4_type6;
-    ZXIC_UINT32 cfg_l4_type7;
-}DPP_NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_1_T;
-
-typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l4type_2_t
-{
-    ZXIC_UINT32 cfg_l4_type8;
-    ZXIC_UINT32 cfg_l4_type9;
-    ZXIC_UINT32 cfg_l4_type10;
-}DPP_NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_2_T;
-
-typedef struct dpp_nppu_pktrx_cfg_slot_no_cfg_t
-{
-    ZXIC_UINT32 cfg_parser_slot_no;
-}DPP_NPPU_PKTRX_CFG_SLOT_NO_CFG_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_int_en_0_t
-{
-    ZXIC_UINT32 pktrx_int_en_31;
-    ZXIC_UINT32 pktrx_int_en_30;
-    ZXIC_UINT32 pktrx_int_en_29;
-    ZXIC_UINT32 pktrx_int_en_28;
-    ZXIC_UINT32 pktrx_int_en_27;
-    ZXIC_UINT32 pktrx_int_en_26;
-    ZXIC_UINT32 pktrx_int_en_25;
-    ZXIC_UINT32 pktrx_int_en_24;
-    ZXIC_UINT32 pktrx_int_en_23;
-    ZXIC_UINT32 pktrx_int_en_22;
-    ZXIC_UINT32 pktrx_int_en_21;
-    ZXIC_UINT32 pktrx_int_en_20;
-    ZXIC_UINT32 pktrx_int_en_19;
-    ZXIC_UINT32 pktrx_int_en_18;
-    ZXIC_UINT32 pktrx_int_en_17;
-    ZXIC_UINT32 pktrx_int_en_16;
-    ZXIC_UINT32 pktrx_int_en_15;
-    ZXIC_UINT32 pktrx_int_en_14;
-    ZXIC_UINT32 pktrx_int_en_13;
-    ZXIC_UINT32 pktrx_int_en_12;
-    ZXIC_UINT32 pktrx_int_en_11;
-    ZXIC_UINT32 pktrx_int_en_10;
-    ZXIC_UINT32 pktrx_int_en_9;
-    ZXIC_UINT32 pktrx_int_en_8;
-    ZXIC_UINT32 pktrx_int_en_7;
-    ZXIC_UINT32 pktrx_int_en_6;
-    ZXIC_UINT32 pktrx_int_en_5;
-    ZXIC_UINT32 pktrx_int_en_4;
-    ZXIC_UINT32 pktrx_int_en_3;
-    ZXIC_UINT32 pktrx_int_en_2;
-    ZXIC_UINT32 pktrx_int_en_1;
-    ZXIC_UINT32 pktrx_int_en_0;
-}DPP_NPPU_PKTRX_CFG_PKTRX_INT_EN_0_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_int_en_1_t
-{
-    ZXIC_UINT32 pktrx_int_en_35;
-    ZXIC_UINT32 pktrx_int_en_34;
-    ZXIC_UINT32 pktrx_int_en_33;
-    ZXIC_UINT32 pktrx_int_en_32;
-}DPP_NPPU_PKTRX_CFG_PKTRX_INT_EN_1_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_int_mask_0_t
-{
-    ZXIC_UINT32 pktrx_int_mask_31;
-    ZXIC_UINT32 pktrx_int_mask_30;
-    ZXIC_UINT32 pktrx_int_mask_29;
-    ZXIC_UINT32 pktrx_int_mask_28;
-    ZXIC_UINT32 pktrx_int_mask_27;
-    ZXIC_UINT32 pktrx_int_mask_26;
-    ZXIC_UINT32 pktrx_int_mask_25;
-    ZXIC_UINT32 pktrx_int_mask_24;
-    ZXIC_UINT32 pktrx_int_mask_23;
-    ZXIC_UINT32 pktrx_int_mask_22;
-    ZXIC_UINT32 pktrx_int_mask_21;
-    ZXIC_UINT32 pktrx_int_mask_20;
-    ZXIC_UINT32 pktrx_int_mask_19;
-    ZXIC_UINT32 pktrx_int_mask_18;
-    ZXIC_UINT32 pktrx_int_mask_17;
-    ZXIC_UINT32 pktrx_int_mask_16;
-    ZXIC_UINT32 pktrx_int_mask_15;
-    ZXIC_UINT32 pktrx_int_mask_14;
-    ZXIC_UINT32 pktrx_int_mask_13;
-    ZXIC_UINT32 pktrx_int_mask_12;
-    ZXIC_UINT32 pktrx_int_mask_11;
-    ZXIC_UINT32 pktrx_int_mask_10;
-    ZXIC_UINT32 pktrx_int_mask_9;
-    ZXIC_UINT32 pktrx_int_mask_8;
-    ZXIC_UINT32 pktrx_int_mask_7;
-    ZXIC_UINT32 pktrx_int_mask_6;
-    ZXIC_UINT32 pktrx_int_mask_5;
-    ZXIC_UINT32 pktrx_int_mask_4;
-    ZXIC_UINT32 pktrx_int_mask_3;
-    ZXIC_UINT32 pktrx_int_mask_2;
-    ZXIC_UINT32 pktrx_int_mask_1;
-    ZXIC_UINT32 pktrx_int_mask_0;
-}DPP_NPPU_PKTRX_CFG_PKTRX_INT_MASK_0_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_int_mask_1_t
-{
-    ZXIC_UINT32 pktrx_int_mask_35;
-    ZXIC_UINT32 pktrx_int_mask_34;
-    ZXIC_UINT32 pktrx_int_mask_33;
-    ZXIC_UINT32 pktrx_int_mask_32;
-}DPP_NPPU_PKTRX_CFG_PKTRX_INT_MASK_1_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_int_status_t
-{
-    ZXIC_UINT32 int_status;
-}DPP_NPPU_PKTRX_CFG_PKTRX_INT_STATUS_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_port_rdy0_t
-{
-    ZXIC_UINT32 pktrx_trpgrx_r1_rdy;
-    ZXIC_UINT32 pktrx_trpgrx_r2_rdy;
-}DPP_NPPU_PKTRX_CFG_PKTRX_PORT_RDY0_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy0_t
-{
-    ZXIC_UINT32 pktrx_trpgrx_r1_pfc_rdy_0;
-}DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY0_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy1_t
-{
-    ZXIC_UINT32 pktrx_trpgrx_r1_pfc_rdy_1;
-}DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY1_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy2_t
-{
-    ZXIC_UINT32 pktrx_trpgrx_r1_pfc_rdy_2;
-}DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY2_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy3_t
-{
-    ZXIC_UINT32 pktrx_trpgrx_r2_pfc_rdy_3;
-}DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY3_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy4_t
-{
-    ZXIC_UINT32 pktrx_trpgrx_r2_pfc_rdy_4;
-}DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY4_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy5_t
-{
-    ZXIC_UINT32 pktrx_trpgrx_r2_pfc_rdy_5;
-}DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY5_T;
-
-typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy6_t
-{
-    ZXIC_UINT32 pktrx_trpgrx_r2_pfc_rdy_6;
-}DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY6_T;
-
-typedef struct dpp_nppu_pktrx_cfg_cfg_port_l2_offset_mode_t
-{
-    ZXIC_UINT32 cfg_port_l2_offset_mode;
-}DPP_NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_T;
-
-typedef struct dpp_nppu_idma_cfg_int_ram_en_t
-{
-    ZXIC_UINT32 phy_sts_parity_err;
-    ZXIC_UINT32 ptr_buf_parity_err;
-}DPP_NPPU_IDMA_CFG_INT_RAM_EN_T;
-
-typedef struct dpp_nppu_idma_cfg_int_ram_mask_t
-{
-    ZXIC_UINT32 phy_sts_parity_err;
-    ZXIC_UINT32 ptr_buf_parity_err;
-}DPP_NPPU_IDMA_CFG_INT_RAM_MASK_T;
-
-typedef struct dpp_nppu_idma_cfg_int_ram_status_t
-{
-    ZXIC_UINT32 phy_sts_parity_err;
-    ZXIC_UINT32 ptr_buf_parity_err;
-}DPP_NPPU_IDMA_CFG_INT_RAM_STATUS_T;
-
-typedef struct dpp_nppu_idma_cfg_subsys_int_mask_flag_t
-{
-    ZXIC_UINT32 subsys_int_mask_flag;
-}DPP_NPPU_IDMA_CFG_SUBSYS_INT_MASK_FLAG_T;
-
-typedef struct dpp_nppu_idma_cfg_subsys_int_unmask_flag_t
-{
-    ZXIC_UINT32 subsys_int_unmask_flag;
-}DPP_NPPU_IDMA_CFG_SUBSYS_INT_UNMASK_FLAG_T;
-
-typedef struct dpp_nppu_idma_cfg_debug_cnt_rdclr_mode_t
-{
-    ZXIC_UINT32 debug_cnt_rdclr_mode;
-}DPP_NPPU_IDMA_CFG_DEBUG_CNT_RDCLR_MODE_T;
-
-typedef struct dpp_nppu_pbu_cfg_int_ram_en0_t
-{
-    ZXIC_UINT32 int_ram_en_31;
-    ZXIC_UINT32 int_ram_en_30;
-    ZXIC_UINT32 int_ram_en_29;
-    ZXIC_UINT32 int_ram_en_28;
-    ZXIC_UINT32 int_ram_en_27;
-    ZXIC_UINT32 int_ram_en_26;
-    ZXIC_UINT32 int_ram_en_25;
-    ZXIC_UINT32 int_ram_en_24;
-    ZXIC_UINT32 int_ram_en_23;
-    ZXIC_UINT32 int_ram_en_22;
-    ZXIC_UINT32 int_ram_en_21;
-    ZXIC_UINT32 int_ram_en_20;
-    ZXIC_UINT32 int_ram_en_19;
-    ZXIC_UINT32 int_ram_en_18;
-    ZXIC_UINT32 int_ram_en_17;
-    ZXIC_UINT32 int_ram_en_16;
-    ZXIC_UINT32 int_ram_en_15;
-    ZXIC_UINT32 int_ram_en_14;
-    ZXIC_UINT32 int_ram_en_13;
-    ZXIC_UINT32 int_ram_en_12;
-    ZXIC_UINT32 int_ram_en_11;
-    ZXIC_UINT32 int_ram_en_10;
-    ZXIC_UINT32 int_ram_en_9;
-    ZXIC_UINT32 int_ram_en_8;
-    ZXIC_UINT32 int_ram_en_7;
-    ZXIC_UINT32 int_ram_en_6;
-    ZXIC_UINT32 int_ram_en_5;
-    ZXIC_UINT32 int_ram_en_4;
-    ZXIC_UINT32 int_ram_en_3;
-    ZXIC_UINT32 int_ram_en_2;
-    ZXIC_UINT32 int_ram_en_1;
-    ZXIC_UINT32 int_ram_en_0;
-}DPP_NPPU_PBU_CFG_INT_RAM_EN0_T;
-
-typedef struct dpp_nppu_pbu_cfg_int_ram_mask0_t
-{
-    ZXIC_UINT32 int_ram_mask_31;
-    ZXIC_UINT32 int_ram_mask_30;
-    ZXIC_UINT32 int_ram_mask_29;
-    ZXIC_UINT32 int_ram_mask_28;
-    ZXIC_UINT32 int_ram_mask_27;
-    ZXIC_UINT32 int_ram_mask_26;
-    ZXIC_UINT32 int_ram_mask_25;
-    ZXIC_UINT32 int_ram_mask_24;
-    ZXIC_UINT32 int_ram_mask_23;
-    ZXIC_UINT32 int_ram_mask_22;
-    ZXIC_UINT32 int_ram_mask_21;
-    ZXIC_UINT32 int_ram_mask_20;
-    ZXIC_UINT32 int_ram_mask_19;
-    ZXIC_UINT32 int_ram_mask_18;
-    ZXIC_UINT32 int_ram_mask_17;
-    ZXIC_UINT32 int_ram_mask_16;
-    ZXIC_UINT32 int_ram_mask_15;
-    ZXIC_UINT32 int_ram_mask_14;
-    ZXIC_UINT32 int_ram_mask_13;
-    ZXIC_UINT32 int_ram_mask_12;
-    ZXIC_UINT32 int_ram_mask_11;
-    ZXIC_UINT32 int_ram_mask_10;
-    ZXIC_UINT32 int_ram_mask_9;
-    ZXIC_UINT32 int_ram_mask_8;
-    ZXIC_UINT32 int_ram_mask_7;
-    ZXIC_UINT32 int_ram_mask_6;
-    ZXIC_UINT32 int_ram_mask_5;
-    ZXIC_UINT32 int_ram_mask_4;
-    ZXIC_UINT32 int_ram_mask_3;
-    ZXIC_UINT32 int_ram_mask_2;
-    ZXIC_UINT32 int_ram_mask_1;
-    ZXIC_UINT32 int_ram_mask_0;
-}DPP_NPPU_PBU_CFG_INT_RAM_MASK0_T;
-
-typedef struct dpp_nppu_pbu_cfg_int_ram_status0_t
-{
-    ZXIC_UINT32 int_ram_status_31;
-    ZXIC_UINT32 int_ram_status_30;
-    ZXIC_UINT32 int_ram_status_29;
-    ZXIC_UINT32 int_ram_status_28;
-    ZXIC_UINT32 int_ram_status_27;
-    ZXIC_UINT32 int_ram_status_26;
-    ZXIC_UINT32 int_ram_status_25;
-    ZXIC_UINT32 int_ram_status_24;
-    ZXIC_UINT32 int_ram_status_23;
-    ZXIC_UINT32 int_ram_status_22;
-    ZXIC_UINT32 int_ram_status_21;
-    ZXIC_UINT32 int_ram_status_20;
-    ZXIC_UINT32 int_ram_status_19;
-    ZXIC_UINT32 int_ram_status_18;
-    ZXIC_UINT32 int_ram_status_17;
-    ZXIC_UINT32 int_ram_status_16;
-    ZXIC_UINT32 int_ram_status_15;
-    ZXIC_UINT32 int_ram_status_14;
-    ZXIC_UINT32 int_ram_status_13;
-    ZXIC_UINT32 int_ram_status_12;
-    ZXIC_UINT32 int_ram_status_11;
-    ZXIC_UINT32 int_ram_status_10;
-    ZXIC_UINT32 int_ram_status_9;
-    ZXIC_UINT32 int_ram_status_8;
-    ZXIC_UINT32 int_ram_status_7;
-    ZXIC_UINT32 int_ram_status_6;
-    ZXIC_UINT32 int_ram_status_5;
-    ZXIC_UINT32 int_ram_status_4;
-    ZXIC_UINT32 int_ram_status_3;
-    ZXIC_UINT32 int_ram_status_2;
-    ZXIC_UINT32 int_ram_status_1;
-    ZXIC_UINT32 int_ram_status_0;
-}DPP_NPPU_PBU_CFG_INT_RAM_STATUS0_T;
-
-typedef struct dpp_nppu_pbu_cfg_int_fifo_en0_t
-{
-    ZXIC_UINT32 int_fifo_en_31;
-    ZXIC_UINT32 int_fifo_en_30;
-    ZXIC_UINT32 int_fifo_en_29;
-    ZXIC_UINT32 int_fifo_en_28;
-    ZXIC_UINT32 int_fifo_en_27;
-    ZXIC_UINT32 int_fifo_en_26;
-    ZXIC_UINT32 int_fifo_en_25;
-    ZXIC_UINT32 int_fifo_en_24;
-    ZXIC_UINT32 int_fifo_en_23;
-    ZXIC_UINT32 int_fifo_en_22;
-    ZXIC_UINT32 int_fifo_en_21;
-    ZXIC_UINT32 int_fifo_en_20;
-    ZXIC_UINT32 int_fifo_en_19;
-    ZXIC_UINT32 int_fifo_en_18;
-    ZXIC_UINT32 int_fifo_en_17;
-    ZXIC_UINT32 int_fifo_en_16;
-    ZXIC_UINT32 int_fifo_en_15;
-    ZXIC_UINT32 int_fifo_en_14;
-    ZXIC_UINT32 int_fifo_en_13;
-    ZXIC_UINT32 int_fifo_en_12;
-    ZXIC_UINT32 int_fifo_en_11;
-    ZXIC_UINT32 int_fifo_en_10;
-    ZXIC_UINT32 int_fifo_en_9;
-    ZXIC_UINT32 int_fifo_en_8;
-    ZXIC_UINT32 int_fifo_en_7;
-    ZXIC_UINT32 int_fifo_en_6;
-    ZXIC_UINT32 int_fifo_en_5;
-    ZXIC_UINT32 int_fifo_en_4;
-    ZXIC_UINT32 int_fifo_en_3;
-    ZXIC_UINT32 int_fifo_en_2;
-    ZXIC_UINT32 int_fifo_en_1;
-    ZXIC_UINT32 int_fifo_en_0;
-}DPP_NPPU_PBU_CFG_INT_FIFO_EN0_T;
-
-typedef struct dpp_nppu_pbu_cfg_int_fifo_en1_t
-{
-    ZXIC_UINT32 int_fifo_en_35;
-    ZXIC_UINT32 int_fifo_en_34;
-    ZXIC_UINT32 int_fifo_en_33;
-    ZXIC_UINT32 int_fifo_en_32;
-}DPP_NPPU_PBU_CFG_INT_FIFO_EN1_T;
-
-typedef struct dpp_nppu_pbu_cfg_int_fifo_mask0_t
-{
-    ZXIC_UINT32 int_fifo_mask_31;
-    ZXIC_UINT32 int_fifo_mask_30;
-    ZXIC_UINT32 int_fifo_mask_29;
-    ZXIC_UINT32 int_fifo_mask_28;
-    ZXIC_UINT32 int_fifo_mask_27;
-    ZXIC_UINT32 int_fifo_mask_26;
-    ZXIC_UINT32 int_fifo_mask_25;
-    ZXIC_UINT32 int_fifo_mask_24;
-    ZXIC_UINT32 int_fifo_mask_23;
-    ZXIC_UINT32 int_fifo_mask_22;
-    ZXIC_UINT32 int_fifo_mask_21;
-    ZXIC_UINT32 int_fifo_mask_20;
-    ZXIC_UINT32 int_fifo_mask_19;
-    ZXIC_UINT32 int_fifo_mask_18;
-    ZXIC_UINT32 int_fifo_mask_17;
-    ZXIC_UINT32 int_fifo_mask_16;
-    ZXIC_UINT32 int_fifo_mask_15;
-    ZXIC_UINT32 int_fifo_mask_14;
-    ZXIC_UINT32 int_fifo_mask_13;
-    ZXIC_UINT32 int_fifo_mask_12;
-    ZXIC_UINT32 int_fifo_mask_11;
-    ZXIC_UINT32 int_fifo_mask_10;
-    ZXIC_UINT32 int_fifo_mask_9;
-    ZXIC_UINT32 int_fifo_mask_8;
-    ZXIC_UINT32 int_fifo_mask_7;
-    ZXIC_UINT32 int_fifo_mask_6;
-    ZXIC_UINT32 int_fifo_mask_5;
-    ZXIC_UINT32 int_fifo_mask_4;
-    ZXIC_UINT32 int_fifo_mask_3;
-    ZXIC_UINT32 int_fifo_mask_2;
-    ZXIC_UINT32 int_fifo_mask_1;
-    ZXIC_UINT32 int_fifo_mask_0;
-}DPP_NPPU_PBU_CFG_INT_FIFO_MASK0_T;
-
-typedef struct dpp_nppu_pbu_cfg_int_fifo_mask1_t
-{
-    ZXIC_UINT32 int_fifo_mask_35;
-    ZXIC_UINT32 int_fifo_mask_34;
-    ZXIC_UINT32 int_fifo_mask_33;
-    ZXIC_UINT32 int_fifo_mask_32;
-}DPP_NPPU_PBU_CFG_INT_FIFO_MASK1_T;
-
-typedef struct dpp_nppu_pbu_cfg_int_fifo_status0_t
-{
-    ZXIC_UINT32 int_fifo_status_31;
-    ZXIC_UINT32 int_fifo_status_30;
-    ZXIC_UINT32 int_fifo_status_29;
-    ZXIC_UINT32 int_fifo_status_28;
-    ZXIC_UINT32 int_fifo_status_27;
-    ZXIC_UINT32 int_fifo_status_26;
-    ZXIC_UINT32 int_fifo_status_25;
-    ZXIC_UINT32 int_fifo_status_24;
-    ZXIC_UINT32 int_fifo_status_23;
-    ZXIC_UINT32 int_fifo_status_22;
-    ZXIC_UINT32 int_fifo_status_21;
-    ZXIC_UINT32 int_fifo_status_20;
-    ZXIC_UINT32 int_fifo_status_19;
-    ZXIC_UINT32 int_fifo_status_18;
-    ZXIC_UINT32 int_fifo_status_17;
-    ZXIC_UINT32 int_fifo_status_16;
-    ZXIC_UINT32 int_fifo_status_15;
-    ZXIC_UINT32 int_fifo_status_14;
-    ZXIC_UINT32 int_fifo_status_13;
-    ZXIC_UINT32 int_fifo_status_12;
-    ZXIC_UINT32 int_fifo_status_11;
-    ZXIC_UINT32 int_fifo_status_10;
-    ZXIC_UINT32 int_fifo_status_9;
-    ZXIC_UINT32 int_fifo_status_8;
-    ZXIC_UINT32 int_fifo_status_7;
-    ZXIC_UINT32 int_fifo_status_6;
-    ZXIC_UINT32 int_fifo_status_5;
-    ZXIC_UINT32 int_fifo_status_4;
-    ZXIC_UINT32 int_fifo_status_3;
-    ZXIC_UINT32 int_fifo_status_2;
-    ZXIC_UINT32 int_fifo_status_1;
-    ZXIC_UINT32 int_fifo_status_0;
-}DPP_NPPU_PBU_CFG_INT_FIFO_STATUS0_T;
-
-typedef struct dpp_nppu_pbu_cfg_int_fifo_status1_t
-{
-    ZXIC_UINT32 int_fifo_status_35;
-    ZXIC_UINT32 int_fifo_status_34;
-    ZXIC_UINT32 int_fifo_status_33;
-    ZXIC_UINT32 int_fifo_status_32;
-}DPP_NPPU_PBU_CFG_INT_FIFO_STATUS1_T;
-
-typedef struct dpp_nppu_pbu_cfg_subsys_int_mask_flag_t
-{
-    ZXIC_UINT32 subsys_int_mask_flag;
-}DPP_NPPU_PBU_CFG_SUBSYS_INT_MASK_FLAG_T;
-
-typedef struct dpp_nppu_pbu_cfg_subsys_int_unmask_flag_t
-{
-    ZXIC_UINT32 subsys_int_unmask_flag;
-}DPP_NPPU_PBU_CFG_SUBSYS_INT_UNMASK_FLAG_T;
-
-typedef struct dpp_nppu_pbu_cfg_sa_ip_en_t
-{
-    ZXIC_UINT32 sa_ip_en;
-}DPP_NPPU_PBU_CFG_SA_IP_EN_T;
-
-typedef struct dpp_nppu_pbu_cfg_debug_cnt_rdclr_mode_t
-{
-    ZXIC_UINT32 debug_cnt_rdclr_mode;
-}DPP_NPPU_PBU_CFG_DEBUG_CNT_RDCLR_MODE_T;
-
-typedef struct dpp_nppu_pbu_cfg_fptr_fifo_aful_assert_cfg_t
-{
-    ZXIC_UINT32 fptr_fifo_aful_assert_cfg;
-}DPP_NPPU_PBU_CFG_FPTR_FIFO_AFUL_ASSERT_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_fptr_fifo_aful_negate_cfg_t
-{
-    ZXIC_UINT32 fptr_fifo_aful_negate_cfg;
-}DPP_NPPU_PBU_CFG_FPTR_FIFO_AFUL_NEGATE_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_pf_fifo_aful_assert_cfg_t
-{
-    ZXIC_UINT32 pf_fifo_aful_assert_cfg;
-}DPP_NPPU_PBU_CFG_PF_FIFO_AFUL_ASSERT_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_pf_fifo_aful_negate_cfg_t
-{
-    ZXIC_UINT32 pf_fifo_aful_negate_cfg;
-}DPP_NPPU_PBU_CFG_PF_FIFO_AFUL_NEGATE_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_pf_fifo_aept_assert_cfg_t
-{
-    ZXIC_UINT32 pf_fifo_aept_assert_cfg;
-}DPP_NPPU_PBU_CFG_PF_FIFO_AEPT_ASSERT_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_pf_fifo_aept_negate_cfg_t
-{
-    ZXIC_UINT32 pf_fifo_aept_negate_cfg;
-}DPP_NPPU_PBU_CFG_PF_FIFO_AEPT_NEGATE_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_wb_aful_assert_cfg_t
-{
-    ZXIC_UINT32 wb_aful_assert_cfg;
-}DPP_NPPU_PBU_CFG_WB_AFUL_ASSERT_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_wb_aful_negate_cfg_t
-{
-    ZXIC_UINT32 wb_aful_negate_cfg;
-}DPP_NPPU_PBU_CFG_WB_AFUL_NEGATE_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_se_key_aful_assert_cfg_t
-{
-    ZXIC_UINT32 se_key_aful_assert_cfg;
-}DPP_NPPU_PBU_CFG_SE_KEY_AFUL_ASSERT_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_ifbrd_se_aful_assert_cfg_t
-{
-    ZXIC_UINT32 ifbrd_se_aful_assert_cfg;
-}DPP_NPPU_PBU_CFG_IFBRD_SE_AFUL_ASSERT_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_ifbrd_se_aful_negate_cfg_t
-{
-    ZXIC_UINT32 ifbrd_se_aful_negate_cfg;
-}DPP_NPPU_PBU_CFG_IFBRD_SE_AFUL_NEGATE_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_ifbrd_odma_aful_assert_cfg_t
-{
-    ZXIC_UINT32 ifbrd_odma_aful_assert_cfg;
-}DPP_NPPU_PBU_CFG_IFBRD_ODMA_AFUL_ASSERT_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_ifbrd_odma_aful_negate_cfg_t
-{
-    ZXIC_UINT32 ifbrd_odma_aful_negate_cfg;
-}DPP_NPPU_PBU_CFG_IFBRD_ODMA_AFUL_NEGATE_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_ifbrd_ppu_aful_assert_cfg_t
-{
-    ZXIC_UINT32 ifbrd_ppu_aful_assert_cfg;
-}DPP_NPPU_PBU_CFG_IFBRD_PPU_AFUL_ASSERT_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_ifbrd_ppu_aful_negate_cfg_t
-{
-    ZXIC_UINT32 ifbrd_ppu_aful_negate_cfg;
-}DPP_NPPU_PBU_CFG_IFBRD_PPU_AFUL_NEGATE_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_mc_logic_aful_assert_cfg_t
-{
-    ZXIC_UINT32 mc_logic_aful_assert_cfg;
-}DPP_NPPU_PBU_CFG_MC_LOGIC_AFUL_ASSERT_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_mc_logic_aful_negate_cfg_t
-{
-    ZXIC_UINT32 mc_logic_aful_negate_cfg;
-}DPP_NPPU_PBU_CFG_MC_LOGIC_AFUL_NEGATE_CFG_T;
-
-typedef struct dpp_nppu_pbu_cfg_mc_logic_diff_t
-{
-    ZXIC_UINT32 mc_logic_diff;
-}DPP_NPPU_PBU_CFG_MC_LOGIC_DIFF_T;
-
-typedef struct dpp_nppu_pbu_cfg_cfg_peak_port_cnt_clr_t
-{
-    ZXIC_UINT32 cfg_peak_port_cnt_clr;
-}DPP_NPPU_PBU_CFG_CFG_PEAK_PORT_CNT_CLR_T;
-
-typedef struct dpp_nppu_pbu_cfg_all_ftm_crdt_th_t
-{
-    ZXIC_UINT32 ftm_crdt_port_cng_th;
-    ZXIC_UINT32 ftm_crdt_port_th;
-}DPP_NPPU_PBU_CFG_ALL_FTM_CRDT_TH_T;
-
-typedef struct dpp_nppu_pbu_cfg_all_ftm_link_th_01_t
-{
-    ZXIC_UINT32 total_congest_th1;
-    ZXIC_UINT32 total_congest_th0;
-}DPP_NPPU_PBU_CFG_ALL_FTM_LINK_TH_01_T;
-
-typedef struct dpp_nppu_pbu_cfg_all_ftm_link_th_23_t
-{
-    ZXIC_UINT32 total_congest_th3;
-    ZXIC_UINT32 total_congest_th2;
-}DPP_NPPU_PBU_CFG_ALL_FTM_LINK_TH_23_T;
-
-typedef struct dpp_nppu_pbu_cfg_all_ftm_link_th_45_t
-{
-    ZXIC_UINT32 total_congest_th5;
-    ZXIC_UINT32 total_congest_th4;
-}DPP_NPPU_PBU_CFG_ALL_FTM_LINK_TH_45_T;
-
-typedef struct dpp_nppu_pbu_cfg_all_ftm_link_th_6_t
-{
-    ZXIC_UINT32 total_congest_th6;
-}DPP_NPPU_PBU_CFG_ALL_FTM_LINK_TH_6_T;
-
-typedef struct dpp_nppu_pbu_cfg_all_ftm_total_congest_th_t
-{
-    ZXIC_UINT32 all_ftm_total_congest_th;
-}DPP_NPPU_PBU_CFG_ALL_FTM_TOTAL_CONGEST_TH_T;
-
-typedef struct dpp_nppu_pbu_cfg_cfg_crdt_mode_t
-{
-    ZXIC_UINT32 cfg_crdt_mode;
-}DPP_NPPU_PBU_CFG_CFG_CRDT_MODE_T;
-
-typedef struct dpp_nppu_pbu_cfg_cfg_pfc_rdy_high_time_t
-{
-    ZXIC_UINT32 cfg_pfc_rdy_high_time;
-}DPP_NPPU_PBU_CFG_CFG_PFC_RDY_HIGH_TIME_T;
-
-typedef struct dpp_nppu_pbu_cfg_cfg_pfc_rdy_low_time_t
-{
-    ZXIC_UINT32 cfg_pfc_rdy_low_time;
-}DPP_NPPU_PBU_CFG_CFG_PFC_RDY_LOW_TIME_T;
-
-typedef struct dpp_nppu_pbu_stat_pbu_fc_rdy_t
-{
-    ZXIC_UINT32 pbu_oam_send_fc_rdy;
-    ZXIC_UINT32 pbu_odma_fc_rdy;
-    ZXIC_UINT32 pbu_tm_fc_rdy;
-    ZXIC_UINT32 pbu_idma_cos_rdy;
-}DPP_NPPU_PBU_STAT_PBU_FC_RDY_T;
-
-typedef struct dpp_nppu_pbu_stat_pbu_lif_group0_rdy0_t
-{
-    ZXIC_UINT32 pbu_ipg1_rdy;
-    ZXIC_UINT32 pbu_ipg0_rdy;
-    ZXIC_UINT32 pbu_trpgrx_xge_rdy;
-    ZXIC_UINT32 pbu_trpgrx_cge1_rdy;
-    ZXIC_UINT32 pbu_trpgrx_cge0_rdy;
-}DPP_NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY0_T;
-
-typedef struct dpp_nppu_pbu_stat_pbu_lif_group0_rdy1_t
-{
-    ZXIC_UINT32 pbu_lif_group0_rdy1;
-}DPP_NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY1_T;
-
-typedef struct dpp_nppu_pbu_stat_pbu_lif_group1_rdy_t
-{
-    ZXIC_UINT32 pbu_lif_group1_rdy1;
-}DPP_NPPU_PBU_STAT_PBU_LIF_GROUP1_RDY_T;
-
-typedef struct dpp_nppu_pbu_stat_pbu_lif_group0_pfc_rdy_t
-{
-    ZXIC_UINT32 pbu_lif_group0_pfc_rdy;
-}DPP_NPPU_PBU_STAT_PBU_LIF_GROUP0_PFC_RDY_T;
-
-typedef struct dpp_nppu_pbu_stat_pbu_lif_group1_pfc_rdy_t
-{
-    ZXIC_UINT32 pbu_lif_group1_pfc_rdy;
-}DPP_NPPU_PBU_STAT_PBU_LIF_GROUP1_PFC_RDY_T;
-
-typedef struct dpp_nppu_pbu_stat_pbu_sa_port_rdy_0_31_t
-{
-    ZXIC_UINT32 pbu_sa_port_rdy_0_31;
-}DPP_NPPU_PBU_STAT_PBU_SA_PORT_RDY_0_31_T;
-
-typedef struct dpp_nppu_pbu_stat_pbu_sa_port_rdy_32_50_t
-{
-    ZXIC_UINT32 pbu_sa_port_rdy_32_50;
-}DPP_NPPU_PBU_STAT_PBU_SA_PORT_RDY_32_50_T;
-
-typedef struct dpp_nppu_pbu_stat_pbu_pktrx_mr_pfc_rdy_t
-{
-    ZXIC_UINT32 pbu_pktrx_mr_pfc_rdy;
-}DPP_NPPU_PBU_STAT_PBU_PKTRX_MR_PFC_RDY_T;
-
-typedef struct dpp_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_0_31_t
-{
-    ZXIC_UINT32 pbu_ftm_crdt_port_rdy_0_31;
-}DPP_NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_0_31_T;
-
-typedef struct dpp_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_32_47_t
-{
-    ZXIC_UINT32 pbu_ftm_crdt_port_rdy_32_47;
-}DPP_NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_32_47_T;
-
-typedef struct dpp_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_0_31_t
-{
-    ZXIC_UINT32 pbu_ftm_crdt_port_cng_rdy_0_31;
-}DPP_NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_0_31_T;
-
-typedef struct dpp_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_32_47_t
-{
-    ZXIC_UINT32 pbu_ftm_crdt_port_cng_rdy_32_47;
-}DPP_NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_32_47_T;
-
-typedef struct dpp_nppu_pbu_stat_pbu_ftm_crdt_sys_info_t
-{
-    ZXIC_UINT32 pbu_ftm_crdt_sys_info;
-}DPP_NPPU_PBU_STAT_PBU_FTM_CRDT_SYS_INFO_T;
-
-typedef struct dpp_nppu_isu_cfg_weight_normal_mc_t
-{
-    ZXIC_UINT32 weight_normal_mc;
-}DPP_NPPU_ISU_CFG_WEIGHT_NORMAL_MC_T;
-
-typedef struct dpp_nppu_isu_cfg_weight_sa_mc_t
-{
-    ZXIC_UINT32 weight_sa_mc;
-}DPP_NPPU_ISU_CFG_WEIGHT_SA_MC_T;
-
-typedef struct dpp_nppu_isu_cfg_weight_etm_t
-{
-    ZXIC_UINT32 weight_etm;
-}DPP_NPPU_ISU_CFG_WEIGHT_ETM_T;
-
-typedef struct dpp_nppu_isu_cfg_weight_lp_mc_t
-{
-    ZXIC_UINT32 weight_lp_mc;
-}DPP_NPPU_ISU_CFG_WEIGHT_LP_MC_T;
-
-typedef struct dpp_nppu_isu_cfg_weight_oam_t
-{
-    ZXIC_UINT32 weight_oam;
-}DPP_NPPU_ISU_CFG_WEIGHT_OAM_T;
-
-typedef struct dpp_nppu_isu_cfg_weight_lif_ctrl1_t
-{
-    ZXIC_UINT32 weight_lif_ctrl1;
-}DPP_NPPU_ISU_CFG_WEIGHT_LIF_CTRL1_T;
-
-typedef struct dpp_nppu_isu_cfg_weight_lif_ctrl2_t
-{
-    ZXIC_UINT32 weight_lif_ctrl2;
-}DPP_NPPU_ISU_CFG_WEIGHT_LIF_CTRL2_T;
-
-typedef struct dpp_nppu_isu_cfg_ecc_bypass_read_t
-{
-    ZXIC_UINT32 eccbypass;
-}DPP_NPPU_ISU_CFG_ECC_BYPASS_READ_T;
-
-typedef struct dpp_nppu_isu_cfg_isu_int_mask_t
-{
-    ZXIC_UINT32 isu_int_mask;
-}DPP_NPPU_ISU_CFG_ISU_INT_MASK_T;
-
-typedef struct dpp_nppu_isu_cfg_cfg_crdt_cycle_t
-{
-    ZXIC_UINT32 cfg_cycle;
-}DPP_NPPU_ISU_CFG_CFG_CRDT_CYCLE_T;
-
-typedef struct dpp_nppu_isu_cfg_cfg_crdt_value_t
-{
-    ZXIC_UINT32 cfg_value;
-}DPP_NPPU_ISU_CFG_CFG_CRDT_VALUE_T;
-
-typedef struct dpp_nppu_isu_cfg_isu_int_en_t
-{
-    ZXIC_UINT32 isu_int_en;
-}DPP_NPPU_ISU_CFG_ISU_INT_EN_T;
-
-typedef struct dpp_nppu_isu_cfg_isu_ppu_fifo_fc_t
-{
-    ZXIC_UINT32 isu_ppu_fifo_fc;
-}DPP_NPPU_ISU_CFG_ISU_PPU_FIFO_FC_T;
-
-typedef struct dpp_nppu_isu_cfg_isu_int_status_t
-{
-    ZXIC_UINT32 isu_int_status_26;
-    ZXIC_UINT32 isu_int_status_25;
-    ZXIC_UINT32 isu_int_status_24;
-    ZXIC_UINT32 isu_int_status_23;
-    ZXIC_UINT32 isu_int_status_22;
-    ZXIC_UINT32 isu_int_status_21;
-    ZXIC_UINT32 isu_int_status_20;
-    ZXIC_UINT32 isu_int_status_19;
-    ZXIC_UINT32 isu_int_status_18;
-    ZXIC_UINT32 isu_int_status_17;
-    ZXIC_UINT32 isu_int_status_16;
-    ZXIC_UINT32 isu_int_status_15;
-    ZXIC_UINT32 isu_int_status_14;
-    ZXIC_UINT32 isu_int_status_13;
-    ZXIC_UINT32 isu_int_status_12;
-    ZXIC_UINT32 isu_int_status_11;
-    ZXIC_UINT32 isu_int_status_10;
-    ZXIC_UINT32 isu_int_status_9;
-    ZXIC_UINT32 isu_int_status_8;
-    ZXIC_UINT32 isu_int_status_7;
-    ZXIC_UINT32 isu_int_status_6;
-    ZXIC_UINT32 isu_int_status_5;
-    ZXIC_UINT32 isu_int_status_4;
-    ZXIC_UINT32 isu_int_status_3;
-    ZXIC_UINT32 isu_int_status_2;
-    ZXIC_UINT32 isu_int_status_1;
-    ZXIC_UINT32 isu_int_status_0;
-}DPP_NPPU_ISU_CFG_ISU_INT_STATUS_T;
-
-typedef struct dpp_nppu_isu_cfg_fd_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 fd_prog_full_assert_cfg;
-}DPP_NPPU_ISU_CFG_FD_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_nppu_isu_cfg_fd_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 fd_prog_full_negate_cfg;
-}DPP_NPPU_ISU_CFG_FD_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_nppu_isu_cfg_lp_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 lp_prog_ept_assert_cfg;
-}DPP_NPPU_ISU_CFG_LP_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_nppu_isu_cfg_lp_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 lp_prog_ept_negate_cfg;
-}DPP_NPPU_ISU_CFG_LP_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat0_t
-{
-    ZXIC_UINT32 debug_cnt_dat0;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT0_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat1_t
-{
-    ZXIC_UINT32 debug_cnt_dat1;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT1_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat2_t
-{
-    ZXIC_UINT32 debug_cnt_dat2;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT2_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat3_t
-{
-    ZXIC_UINT32 debug_cnt_dat3;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT3_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat4_t
-{
-    ZXIC_UINT32 debug_cnt_dat4;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT4_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat5_t
-{
-    ZXIC_UINT32 debug_cnt_dat5;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT5_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat6_t
-{
-    ZXIC_UINT32 debug_cnt_dat6;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT6_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat7_t
-{
-    ZXIC_UINT32 debug_cnt_dat7;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT7_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat8_t
-{
-    ZXIC_UINT32 debug_cnt_dat8;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT8_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat9_t
-{
-    ZXIC_UINT32 debug_cnt_dat9;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT9_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat10_t
-{
-    ZXIC_UINT32 debug_cnt_dat10;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT10_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat11_t
-{
-    ZXIC_UINT32 debug_cnt_dat11;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT11_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat12_t
-{
-    ZXIC_UINT32 debug_cnt_dat12;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT12_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat13_t
-{
-    ZXIC_UINT32 debug_cnt_dat13;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT13_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat14_t
-{
-    ZXIC_UINT32 debug_cnt_dat14;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT14_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat15_t
-{
-    ZXIC_UINT32 debug_cnt_dat15;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT15_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat16_t
-{
-    ZXIC_UINT32 debug_cnt_dat16;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT16_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat17_t
-{
-    ZXIC_UINT32 debug_cnt_dat17;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT17_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat18_t
-{
-    ZXIC_UINT32 debug_cnt_dat18;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT18_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_dat19_t
-{
-    ZXIC_UINT32 debug_cnt_dat18;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT19_T;
-
-typedef struct dpp_nppu_isu_stat_debug_cnt_cfg_t
-{
-    ZXIC_UINT32 debug_cnt_ovf_mode;
-    ZXIC_UINT32 debug_cnt_rdclr_mode;
-    ZXIC_UINT32 user_cnt_value;
-}DPP_NPPU_ISU_STAT_DEBUG_CNT_CFG_T;
-
-typedef struct dpp_nppu_odma_cfg_exsa_tdm_offset_t
-{
-    ZXIC_UINT32 exsa_tdm_offset;
-}DPP_NPPU_ODMA_CFG_EXSA_TDM_OFFSET_T;
-
-typedef struct dpp_nppu_odma_cfg_ecc_bypass_readt_t
-{
-    ZXIC_UINT32 ecc_bypass_read;
-}DPP_NPPU_ODMA_CFG_ECC_BYPASS_READT_T;
-
-typedef struct dpp_nppu_odma_cfg_odma_int_en_0_t
-{
-    ZXIC_UINT32 odma_int_en_31;
-    ZXIC_UINT32 odma_int_en_30;
-    ZXIC_UINT32 odma_int_en_29;
-    ZXIC_UINT32 odma_int_en_28;
-    ZXIC_UINT32 odma_int_en_27;
-    ZXIC_UINT32 odma_int_en_26;
-    ZXIC_UINT32 odma_int_en_25;
-    ZXIC_UINT32 odma_int_en_24;
-    ZXIC_UINT32 odma_int_en_22;
-    ZXIC_UINT32 odma_int_en_21;
-    ZXIC_UINT32 odma_int_en_18;
-}DPP_NPPU_ODMA_CFG_ODMA_INT_EN_0_T;
-
-typedef struct dpp_nppu_odma_cfg_odma_int_en_1_t
-{
-    ZXIC_UINT32 odma_int_en_63;
-    ZXIC_UINT32 odma_int_en_62;
-    ZXIC_UINT32 odma_int_en_61;
-    ZXIC_UINT32 odma_int_en_59;
-    ZXIC_UINT32 odma_int_en_58;
-    ZXIC_UINT32 odma_int_en_57;
-    ZXIC_UINT32 odma_int_en_56;
-    ZXIC_UINT32 odma_int_en_55;
-    ZXIC_UINT32 odma_int_en_54;
-    ZXIC_UINT32 odma_int_en_53;
-    ZXIC_UINT32 odma_int_en_52;
-    ZXIC_UINT32 odma_int_en_51;
-    ZXIC_UINT32 odma_int_en_49;
-    ZXIC_UINT32 odma_int_en_47;
-    ZXIC_UINT32 odma_int_en_45;
-    ZXIC_UINT32 odma_int_en_39;
-    ZXIC_UINT32 odma_int_en_38;
-    ZXIC_UINT32 odma_int_en_37;
-    ZXIC_UINT32 odma_int_en_36;
-    ZXIC_UINT32 odma_int_en_35;
-    ZXIC_UINT32 odma_int_en_34;
-    ZXIC_UINT32 odma_int_en_33;
-    ZXIC_UINT32 odma_int_en_32;
-}DPP_NPPU_ODMA_CFG_ODMA_INT_EN_1_T;
-
-typedef struct dpp_nppu_odma_cfg_odma_int_en_2_t
-{
-    ZXIC_UINT32 odma_int_en_91;
-    ZXIC_UINT32 odma_int_en_88;
-    ZXIC_UINT32 odma_int_en_85;
-    ZXIC_UINT32 odma_int_en_82;
-    ZXIC_UINT32 odma_int_en_79;
-    ZXIC_UINT32 odma_int_en_75;
-    ZXIC_UINT32 odma_int_en_74;
-    ZXIC_UINT32 odma_int_en_71;
-    ZXIC_UINT32 odma_int_en_65;
-    ZXIC_UINT32 odma_int_en_64;
-}DPP_NPPU_ODMA_CFG_ODMA_INT_EN_2_T;
-
-typedef struct dpp_nppu_odma_cfg_odma_int_en_3_t
-{
-    ZXIC_UINT32 odma_int_en_115;
-    ZXIC_UINT32 odma_int_en_114;
-    ZXIC_UINT32 odma_int_en_112;
-    ZXIC_UINT32 odma_int_en_110;
-    ZXIC_UINT32 odma_int_en_109;
-    ZXIC_UINT32 odma_int_en_108;
-    ZXIC_UINT32 odma_int_en_107;
-    ZXIC_UINT32 odma_int_en_106;
-    ZXIC_UINT32 odma_int_en_102;
-    ZXIC_UINT32 odma_int_en_101;
-    ZXIC_UINT32 odma_int_en_100;
-    ZXIC_UINT32 odma_int_en_98;
-    ZXIC_UINT32 odma_int_en_96;
-}DPP_NPPU_ODMA_CFG_ODMA_INT_EN_3_T;
-
-typedef struct dpp_nppu_odma_cfg_odma_int_mask_0_t
-{
-    ZXIC_UINT32 odma_int_mask_31;
-    ZXIC_UINT32 odma_int_mask_30;
-    ZXIC_UINT32 odma_int_mask_29;
-    ZXIC_UINT32 odma_int_mask_28;
-    ZXIC_UINT32 odma_int_mask_27;
-    ZXIC_UINT32 odma_int_mask_26;
-    ZXIC_UINT32 odma_int_mask_25;
-    ZXIC_UINT32 odma_int_mask_24;
-    ZXIC_UINT32 odma_int_mask_22;
-    ZXIC_UINT32 odma_int_mask_21;
-    ZXIC_UINT32 odma_int_mask_18;
-}DPP_NPPU_ODMA_CFG_ODMA_INT_MASK_0_T;
-
-typedef struct dpp_nppu_odma_cfg_odma_int_mask_1_t
-{
-    ZXIC_UINT32 odma_int_mask_63;
-    ZXIC_UINT32 odma_int_mask_62;
-    ZXIC_UINT32 odma_int_mask_61;
-    ZXIC_UINT32 odma_int_mask_59;
-    ZXIC_UINT32 odma_int_mask_58;
-    ZXIC_UINT32 odma_int_mask_57;
-    ZXIC_UINT32 odma_int_mask_56;
-    ZXIC_UINT32 odma_int_mask_55;
-    ZXIC_UINT32 odma_int_mask_54;
-    ZXIC_UINT32 odma_int_mask_53;
-    ZXIC_UINT32 odma_int_mask_52;
-    ZXIC_UINT32 odma_int_mask_51;
-    ZXIC_UINT32 odma_int_mask_50;
-    ZXIC_UINT32 odma_int_mask_49;
-    ZXIC_UINT32 odma_int_mask_47;
-    ZXIC_UINT32 odma_int_mask_45;
-    ZXIC_UINT32 odma_int_mask_39;
-    ZXIC_UINT32 odma_int_mask_38;
-    ZXIC_UINT32 odma_int_mask_37;
-    ZXIC_UINT32 odma_int_mask_36;
-    ZXIC_UINT32 odma_int_mask_35;
-    ZXIC_UINT32 odma_int_mask_34;
-    ZXIC_UINT32 odma_int_mask_33;
-    ZXIC_UINT32 odma_int_mask_32;
-}DPP_NPPU_ODMA_CFG_ODMA_INT_MASK_1_T;
-
-typedef struct dpp_nppu_odma_cfg_odma_int_mask_2_t
-{
-    ZXIC_UINT32 odma_int_mask_91;
-    ZXIC_UINT32 odma_int_mask_88;
-    ZXIC_UINT32 odma_int_mask_85;
-    ZXIC_UINT32 odma_int_mask_82;
-    ZXIC_UINT32 odma_int_mask_79;
-    ZXIC_UINT32 odma_int_mask_75;
-    ZXIC_UINT32 odma_int_mask_74;
-    ZXIC_UINT32 odma_int_mask_71;
-    ZXIC_UINT32 odma_int_mask_65;
-    ZXIC_UINT32 odma_int_mask_64;
-}DPP_NPPU_ODMA_CFG_ODMA_INT_MASK_2_T;
-
-typedef struct dpp_nppu_odma_cfg_odma_int_mask_3_t
-{
-    ZXIC_UINT32 odma_int_mask_115;
-    ZXIC_UINT32 odma_int_mask_114;
-    ZXIC_UINT32 odma_int_mask_112;
-    ZXIC_UINT32 odma_int_mask_110;
-    ZXIC_UINT32 odma_int_mask_109;
-    ZXIC_UINT32 odma_int_mask_108;
-    ZXIC_UINT32 odma_int_mask_107;
-    ZXIC_UINT32 odma_int_mask_106;
-    ZXIC_UINT32 odma_int_mask_102;
-    ZXIC_UINT32 odma_int_mask_101;
-    ZXIC_UINT32 odma_int_mask_100;
-    ZXIC_UINT32 odma_int_mask_98;
-    ZXIC_UINT32 odma_int_mask_96;
-}DPP_NPPU_ODMA_CFG_ODMA_INT_MASK_3_T;
-
-typedef struct dpp_nppu_odma_cfg_odma_int_status_0_t
-{
-    ZXIC_UINT32 odma_int_status_31;
-    ZXIC_UINT32 odma_int_status_30;
-    ZXIC_UINT32 odma_int_status_29;
-    ZXIC_UINT32 odma_int_status_28;
-    ZXIC_UINT32 odma_int_status_27;
-    ZXIC_UINT32 odma_int_status_26;
-    ZXIC_UINT32 odma_int_status_25;
-    ZXIC_UINT32 odma_int_status_24;
-    ZXIC_UINT32 odma_int_status_22;
-    ZXIC_UINT32 odma_int_status_21;
-    ZXIC_UINT32 odma_int_status_18;
-}DPP_NPPU_ODMA_CFG_ODMA_INT_STATUS_0_T;
-
-typedef struct dpp_nppu_odma_cfg_odma_int_status_1_t
-{
-    ZXIC_UINT32 odma_int_status_63;
-    ZXIC_UINT32 odma_int_status_62;
-    ZXIC_UINT32 odma_int_status_61;
-    ZXIC_UINT32 odma_int_status_59;
-    ZXIC_UINT32 odma_int_status_58;
-    ZXIC_UINT32 odma_int_status_57;
-    ZXIC_UINT32 odma_int_status_56;
-    ZXIC_UINT32 odma_int_status_55;
-    ZXIC_UINT32 odma_int_status_54;
-    ZXIC_UINT32 odma_int_status_53;
-    ZXIC_UINT32 odma_int_status_52;
-    ZXIC_UINT32 odma_int_status_51;
-    ZXIC_UINT32 odma_int_status_49;
-    ZXIC_UINT32 odma_int_status_47;
-    ZXIC_UINT32 odma_int_status_45;
-    ZXIC_UINT32 odma_int_status_39;
-    ZXIC_UINT32 odma_int_status_38;
-    ZXIC_UINT32 odma_int_status_37;
-    ZXIC_UINT32 odma_int_status_36;
-    ZXIC_UINT32 odma_int_status_35;
-    ZXIC_UINT32 odma_int_status_34;
-    ZXIC_UINT32 odma_int_status_33;
-    ZXIC_UINT32 odma_int_status_32;
-}DPP_NPPU_ODMA_CFG_ODMA_INT_STATUS_1_T;
-
-typedef struct dpp_nppu_odma_cfg_odma_int_status_2_t
-{
-    ZXIC_UINT32 odma_int_status_91;
-    ZXIC_UINT32 odma_int_status_88;
-    ZXIC_UINT32 odma_int_status_85;
-    ZXIC_UINT32 odma_int_status_82;
-    ZXIC_UINT32 odma_int_status_79;
-    ZXIC_UINT32 odma_int_status_75;
-    ZXIC_UINT32 odma_int_status_74;
-    ZXIC_UINT32 odma_int_status_71;
-    ZXIC_UINT32 odma_int_status_65;
-    ZXIC_UINT32 odma_int_status_64;
-}DPP_NPPU_ODMA_CFG_ODMA_INT_STATUS_2_T;
-
-typedef struct dpp_nppu_odma_cfg_odma_int_status_3_t
-{
-    ZXIC_UINT32 odma_int_status_117;
-    ZXIC_UINT32 odma_int_status_116;
-    ZXIC_UINT32 odma_int_status_115;
-    ZXIC_UINT32 odma_int_status_114;
-    ZXIC_UINT32 odma_int_status_112;
-    ZXIC_UINT32 odma_int_status_110;
-    ZXIC_UINT32 odma_int_status_109;
-    ZXIC_UINT32 odma_int_status_108;
-    ZXIC_UINT32 odma_int_status_107;
-    ZXIC_UINT32 odma_int_status_106;
-    ZXIC_UINT32 odma_int_status_102;
-    ZXIC_UINT32 odma_int_status_101;
-    ZXIC_UINT32 odma_int_status_100;
-    ZXIC_UINT32 odma_int_status_98;
-    ZXIC_UINT32 odma_int_status_96;
-}DPP_NPPU_ODMA_CFG_ODMA_INT_STATUS_3_T;
-
-typedef struct dpp_nppu_odma_cfg_sp_tdm_err_nor_cfg_t
-{
-    ZXIC_UINT32 sp_tdm_err_nor_cfg;
-}DPP_NPPU_ODMA_CFG_SP_TDM_ERR_NOR_CFG_T;
-
-typedef struct dpp_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 etm_dis_ptr_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 etm_dis_ptr_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 ftm_dis_ptr_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 ftm_dis_ptr_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 tm_dis_fifo_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 tm_dis_fifo_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_err_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 err_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_err_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 err_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_tdmuc_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 tdmuc_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_tdmuc_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 tdmuc_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 tdmmc_groupid_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 tdmmc_groupid_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 tdmmc_no_bitmap_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 tdmmc_no_bitmap_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_tdmmc_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 tdmmc_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_tdmmc_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 tdmmc_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_desc_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 desc_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_desc_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 desc_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_dly_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 dly_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_dly_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 dly_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_rsp_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 rsp_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_rsp_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 rsp_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_nor_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 nor_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_nor_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 nor_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_etm_nor_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 etm_nor_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_etm_nor_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 etm_nor_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_ftm_nor_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 ftm_nor_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_ftm_nor_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 ftm_nor_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_etm_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 etm_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_etm_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 etm_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_ftm_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 ftm_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_ftm_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 ftm_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 etm_nrdcnt_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 etm_nrdcnt_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 ftm_nrdcnt_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 ftm_nrdcnt_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_pp_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 pp_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_PP_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_pp_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 pp_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_PP_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_tm_weight_t
-{
-    ZXIC_UINT32 tm_weight;
-}DPP_NPPU_ODMA_CFG_TM_WEIGHT_T;
-
-typedef struct dpp_nppu_odma_cfg_pp_weight_t
-{
-    ZXIC_UINT32 pp_weight;
-}DPP_NPPU_ODMA_CFG_PP_WEIGHT_T;
-
-typedef struct dpp_nppu_odma_cfg_ifbcmd_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 ifbcmd_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_ifbcmd_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 ifbcmd_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_mccnt_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 mccnt_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_mccnt_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 mccnt_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_int_or_pon_t
-{
-    ZXIC_UINT32 int_or_pon;
-}DPP_NPPU_ODMA_CFG_INT_OR_PON_T;
-
-typedef struct dpp_nppu_odma_cfg_quemng_cnt_in_err_cnt_t
-{
-    ZXIC_UINT32 quemng_cnt_in_err_cnt;
-}DPP_NPPU_ODMA_CFG_QUEMNG_CNT_IN_ERR_CNT_T;
-
-typedef struct dpp_nppu_odma_cfg_lif0_port_eop_cnt_t
-{
-    ZXIC_UINT32 lif0_port_eop_cnt;
-}DPP_NPPU_ODMA_CFG_LIF0_PORT_EOP_CNT_T;
-
-typedef struct dpp_nppu_odma_cfg_lif1_port_eop_cnt_t
-{
-    ZXIC_UINT32 lif1_port_eop_cnt;
-}DPP_NPPU_ODMA_CFG_LIF1_PORT_EOP_CNT_T;
-
-typedef struct dpp_nppu_odma_cfg_lifc_port0_eop_cnt_t
-{
-    ZXIC_UINT32 lifc_port0_eop_cnt;
-}DPP_NPPU_ODMA_CFG_LIFC_PORT0_EOP_CNT_T;
-
-typedef struct dpp_nppu_odma_cfg_lifc_port1_eop_cnt_t
-{
-    ZXIC_UINT32 lifc_port1_eop_cnt;
-}DPP_NPPU_ODMA_CFG_LIFC_PORT1_EOP_CNT_T;
-
-typedef struct dpp_nppu_odma_cfg_fptr_fifo_prog_ept_cfg_n_t
-{
-    ZXIC_UINT32 fptr_fifo_prog_ept_cfg_n;
-}DPP_NPPU_ODMA_CFG_FPTR_FIFO_PROG_EPT_CFG_N_T;
-
-typedef struct dpp_nppu_odma_cfg_isu_fifo_prog_full_cfg_a_t
-{
-    ZXIC_UINT32 isu_fifo_prog_full_cfg_a;
-}DPP_NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_A_T;
-
-typedef struct dpp_nppu_odma_cfg_isu_fifo_prog_full_cfg_n_t
-{
-    ZXIC_UINT32 isu_fifo_prog_full_cfg_n;
-}DPP_NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_N_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_access_done_t
-{
-    ZXIC_UINT32 ind_access_done;
-}DPP_NPPU_OAM_CFG_IND_ACCESS_DONE_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_access_command_t
-{
-    ZXIC_UINT32 ind_rd_or_wr;
-    ZXIC_UINT32 ind_mem_mask;
-    ZXIC_UINT32 ind_mem_id;
-    ZXIC_UINT32 ind_mem_addr;
-}DPP_NPPU_OAM_CFG_IND_ACCESS_COMMAND_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_dat0_t
-{
-    ZXIC_UINT32 ind_dat0;
-}DPP_NPPU_OAM_CFG_IND_DAT0_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_dat1_t
-{
-    ZXIC_UINT32 ind_dat1;
-}DPP_NPPU_OAM_CFG_IND_DAT1_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_dat2_t
-{
-    ZXIC_UINT32 ind_dat2;
-}DPP_NPPU_OAM_CFG_IND_DAT2_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_dat3_t
-{
-    ZXIC_UINT32 ind_dat3;
-}DPP_NPPU_OAM_CFG_IND_DAT3_T;
-
-typedef struct dpp_nppu_oam_cfg_oam_tx_main_en_t
-{
-    ZXIC_UINT32 oam_tx_main_en;
-}DPP_NPPU_OAM_CFG_OAM_TX_MAIN_EN_T;
-
-typedef struct dpp_nppu_oam_cfg_tx_total_num_t
-{
-    ZXIC_UINT32 tx_total_num;
-}DPP_NPPU_OAM_CFG_TX_TOTAL_NUM_T;
-
-typedef struct dpp_nppu_oam_cfg_oam_chk_main_en_t
-{
-    ZXIC_UINT32 oam_chk_main_en;
-}DPP_NPPU_OAM_CFG_OAM_CHK_MAIN_EN_T;
-
-typedef struct dpp_nppu_oam_cfg_chk_total_num0_t
-{
-    ZXIC_UINT32 chk_total_num0;
-}DPP_NPPU_OAM_CFG_CHK_TOTAL_NUM0_T;
-
-typedef struct dpp_nppu_oam_cfg_ma_chk_main_en_t
-{
-    ZXIC_UINT32 oam_chk_main_en;
-}DPP_NPPU_OAM_CFG_MA_CHK_MAIN_EN_T;
-
-typedef struct dpp_nppu_oam_cfg_chk_total_num1_t
-{
-    ZXIC_UINT32 chk_total_num0;
-}DPP_NPPU_OAM_CFG_CHK_TOTAL_NUM1_T;
-
-typedef struct dpp_nppu_oam_cfg_tx_stat_en_t
-{
-    ZXIC_UINT32 tx_stat_en;
-}DPP_NPPU_OAM_CFG_TX_STAT_EN_T;
-
-typedef struct dpp_nppu_oam_cfg_rec_stat_en_t
-{
-    ZXIC_UINT32 rec_stat_en;
-}DPP_NPPU_OAM_CFG_REC_STAT_EN_T;
-
-typedef struct dpp_nppu_oam_cfg_stat_oam_rdy_mask_t
-{
-    ZXIC_UINT32 stat_oam_rdy_mask;
-}DPP_NPPU_OAM_CFG_STAT_OAM_RDY_MASK_T;
-
-typedef struct dpp_nppu_oam_cfg_session_grading0_t
-{
-    ZXIC_UINT32 session_grading0;
-}DPP_NPPU_OAM_CFG_SESSION_GRADING0_T;
-
-typedef struct dpp_nppu_oam_cfg_session_grading1_t
-{
-    ZXIC_UINT32 session_grading1;
-}DPP_NPPU_OAM_CFG_SESSION_GRADING1_T;
-
-typedef struct dpp_nppu_oam_cfg_session_grading2_t
-{
-    ZXIC_UINT32 session_grading2;
-}DPP_NPPU_OAM_CFG_SESSION_GRADING2_T;
-
-typedef struct dpp_nppu_oam_cfg_session_grading3_t
-{
-    ZXIC_UINT32 session_grading3;
-}DPP_NPPU_OAM_CFG_SESSION_GRADING3_T;
-
-typedef struct dpp_nppu_oam_cfg_bfd_chk_haddr_t
-{
-    ZXIC_UINT32 bfd_chk_haddr;
-}DPP_NPPU_OAM_CFG_BFD_CHK_HADDR_T;
-
-typedef struct dpp_nppu_oam_cfg_ethccm_chk_haddr_t
-{
-    ZXIC_UINT32 ethccm_chk_haddr;
-}DPP_NPPU_OAM_CFG_ETHCCM_CHK_HADDR_T;
-
-typedef struct dpp_nppu_oam_cfg_tpbfd_chk_haddr_t
-{
-    ZXIC_UINT32 tpbfd_chk_haddr;
-}DPP_NPPU_OAM_CFG_TPBFD_CHK_HADDR_T;
-
-typedef struct dpp_nppu_oam_cfg_tpoam_ccm_chk_haddr_t
-{
-    ZXIC_UINT32 tpoam_ccm_chk_haddr;
-}DPP_NPPU_OAM_CFG_TPOAM_CCM_CHK_HADDR_T;
-
-typedef struct dpp_nppu_oam_cfg_bfd_tx_haddr_t
-{
-    ZXIC_UINT32 bfd_tx_haddr;
-}DPP_NPPU_OAM_CFG_BFD_TX_HADDR_T;
-
-typedef struct dpp_nppu_oam_cfg_ethccm_tx_haddr_t
-{
-    ZXIC_UINT32 ethccm_tx_haddr;
-}DPP_NPPU_OAM_CFG_ETHCCM_TX_HADDR_T;
-
-typedef struct dpp_nppu_oam_cfg_tpbfd_tx_haddr_t
-{
-    ZXIC_UINT32 tpbfd_tx_haddr;
-}DPP_NPPU_OAM_CFG_TPBFD_TX_HADDR_T;
-
-typedef struct dpp_nppu_oam_cfg_tpoam_ccm_tx_haddr_t
-{
-    ZXIC_UINT32 tpoam_ccm_tx_haddr;
-}DPP_NPPU_OAM_CFG_TPOAM_CCM_TX_HADDR_T;
-
-typedef struct dpp_nppu_oam_cfg_ethccm_ma_chk_haddr_t
-{
-    ZXIC_UINT32 ethccm_ma_chk_haddr;
-}DPP_NPPU_OAM_CFG_ETHCCM_MA_CHK_HADDR_T;
-
-typedef struct dpp_nppu_oam_cfg_tpccm_ma_chk_haddr_t
-{
-    ZXIC_UINT32 tpccm_ma_chk_haddr;
-}DPP_NPPU_OAM_CFG_TPCCM_MA_CHK_HADDR_T;
-
-typedef struct dpp_nppu_oam_cfg_groupnum_ram_clr_t
-{
-    ZXIC_UINT32 groupnum_ram_clr;
-}DPP_NPPU_OAM_CFG_GROUPNUM_RAM_CLR_T;
-
-typedef struct dpp_nppu_oam_cfg_index_ram0_clr_t
-{
-    ZXIC_UINT32 index_ram0_clr;
-}DPP_NPPU_OAM_CFG_INDEX_RAM0_CLR_T;
-
-typedef struct dpp_nppu_oam_cfg_index_ram1_clr_t
-{
-    ZXIC_UINT32 index_ram1_clr;
-}DPP_NPPU_OAM_CFG_INDEX_RAM1_CLR_T;
-
-typedef struct dpp_nppu_oam_cfg_rmep_ram_clr_t
-{
-    ZXIC_UINT32 rmep_ram_clr;
-}DPP_NPPU_OAM_CFG_RMEP_RAM_CLR_T;
-
-typedef struct dpp_nppu_oam_cfg_ma_ram_clr_t
-{
-    ZXIC_UINT32 ma_ram_clr;
-}DPP_NPPU_OAM_CFG_MA_RAM_CLR_T;
-
-typedef struct dpp_nppu_oam_cfg_ram_init_done_t
-{
-    ZXIC_UINT32 ram_init_done;
-}DPP_NPPU_OAM_CFG_RAM_INIT_DONE_T;
-
-typedef struct dpp_nppu_oam_cfg_rec_bfd_debug_en_t
-{
-    ZXIC_UINT32 rec_bfd_debug_en;
-}DPP_NPPU_OAM_CFG_REC_BFD_DEBUG_EN_T;
-
-typedef struct dpp_nppu_oam_cfg_oam_session_int_t
-{
-    ZXIC_UINT32 tpma_int;
-    ZXIC_UINT32 ethma_int;
-    ZXIC_UINT32 bfd_int;
-    ZXIC_UINT32 ethoam_int;
-    ZXIC_UINT32 tpbfd_int;
-    ZXIC_UINT32 tpoam_int;
-}DPP_NPPU_OAM_CFG_OAM_SESSION_INT_T;
-
-typedef struct dpp_nppu_oam_cfg_pon_int_t
-{
-    ZXIC_UINT32 fifo_int;
-    ZXIC_UINT32 pon_protect_int;
-}DPP_NPPU_OAM_CFG_PON_INT_T;
-
-typedef struct dpp_nppu_oam_cfg_oam_int_clr_t
-{
-    ZXIC_UINT32 oam_int_clr;
-}DPP_NPPU_OAM_CFG_OAM_INT_CLR_T;
-
-typedef struct dpp_nppu_oam_cfg_type_int_clr0_t
-{
-    ZXIC_UINT32 tpma_int_clr;
-    ZXIC_UINT32 ethma_int_clr;
-    ZXIC_UINT32 bfd_int_clr;
-    ZXIC_UINT32 ethoam_int_clr;
-    ZXIC_UINT32 tpbfd_int_clr;
-    ZXIC_UINT32 tpoam_int_clr;
-}DPP_NPPU_OAM_CFG_TYPE_INT_CLR0_T;
-
-typedef struct dpp_nppu_oam_cfg_type_int_clr1_t
-{
-    ZXIC_UINT32 fifo_int_clr;
-    ZXIC_UINT32 pon_protect_int_clr;
-}DPP_NPPU_OAM_CFG_TYPE_INT_CLR1_T;
-
-typedef struct dpp_nppu_oam_cfg_interrupt_mask_t
-{
-    ZXIC_UINT32 fifo_interrupt_mask;
-    ZXIC_UINT32 pon_protect_interruptmask;
-    ZXIC_UINT32 tpma_interrupt_mask;
-    ZXIC_UINT32 ethma_interrupt_mask;
-    ZXIC_UINT32 bfd_interrupt_mask;
-    ZXIC_UINT32 ethoam_interrupt_mask;
-    ZXIC_UINT32 tpbfd_interrupt_mask;
-    ZXIC_UINT32 tpoam_interrupt_mask;
-}DPP_NPPU_OAM_CFG_INTERRUPT_MASK_T;
-
-typedef struct dpp_nppu_oam_cfg_int0_index_t
-{
-    ZXIC_UINT32 int0_index0;
-}DPP_NPPU_OAM_CFG_INT0_INDEX_T;
-
-typedef struct dpp_nppu_oam_cfg_int1_index_t
-{
-    ZXIC_UINT32 int1_index0;
-}DPP_NPPU_OAM_CFG_INT1_INDEX_T;
-
-typedef struct dpp_nppu_oam_cfg_int0_index_region_t
-{
-    ZXIC_UINT32 int0_index_region;
-}DPP_NPPU_OAM_CFG_INT0_INDEX_REGION_T;
-
-typedef struct dpp_nppu_oam_cfg_int1_index_region_t
-{
-    ZXIC_UINT32 int1_index_region;
-}DPP_NPPU_OAM_CFG_INT1_INDEX_REGION_T;
-
-typedef struct dpp_nppu_oam_cfg_bdiinfo_fwft_fifo_th_t
-{
-    ZXIC_UINT32 bdiinfo_fwft_fifo_th;
-}DPP_NPPU_OAM_CFG_BDIINFO_FWFT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_recsec_fwft_fifo_th_t
-{
-    ZXIC_UINT32 recsec_fwft_fifo_th;
-}DPP_NPPU_OAM_CFG_RECSEC_FWFT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_timing_chk_info0_fwft_fifo_th_t
-{
-    ZXIC_UINT32 timing_chk_info0_fwft_fifo_th;
-}DPP_NPPU_OAM_CFG_TIMING_CHK_INFO0_FWFT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_recma_fwft_fifo_th_t
-{
-    ZXIC_UINT32 recma_fwft_fifo_th;
-}DPP_NPPU_OAM_CFG_RECMA_FWFT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_timing_chk_info1_fwft_fifo_th_t
-{
-    ZXIC_UINT32 timing_chk_info1_fwft_fifo_th;
-}DPP_NPPU_OAM_CFG_TIMING_CHK_INFO1_FWFT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_oam_txinst_fifo_th_t
-{
-    ZXIC_UINT32 oam_txinst_fifo_th;
-}DPP_NPPU_OAM_CFG_OAM_TXINST_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_oam_rdinfo_fwft_fifo_th_t
-{
-    ZXIC_UINT32 oam_rdinfo_fwft_fifo_th;
-}DPP_NPPU_OAM_CFG_OAM_RDINFO_FWFT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_lm_cnt_fwft_fifo_th_t
-{
-    ZXIC_UINT32 lm_cnt_fwft_fifo_th;
-}DPP_NPPU_OAM_CFG_LM_CNT_FWFT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_oam_pkt_fifo_th_t
-{
-    ZXIC_UINT32 oam_pkt_fifo_th;
-}DPP_NPPU_OAM_CFG_OAM_PKT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_reclm_stat_fifo_th_t
-{
-    ZXIC_UINT32 reclm_stat_fifo_th;
-}DPP_NPPU_OAM_CFG_RECLM_STAT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_txlm_stat_fifo_th_t
-{
-    ZXIC_UINT32 txlm_stat_fifo_th;
-}DPP_NPPU_OAM_CFG_TXLM_STAT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_oam_chk_fwft_fifo_th_t
-{
-    ZXIC_UINT32 oam_chk_fwft_fifo_th;
-}DPP_NPPU_OAM_CFG_OAM_CHK_FWFT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_txoam_stat_fifo_th_t
-{
-    ZXIC_UINT32 txoam_stat_fifo_th;
-}DPP_NPPU_OAM_CFG_TXOAM_STAT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_recoam_stat_fifo_th_t
-{
-    ZXIC_UINT32 recoam_stat_fifo_th;
-}DPP_NPPU_OAM_CFG_RECOAM_STAT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_txpkt_data_fwft_fifo_th_t
-{
-    ZXIC_UINT32 txpkt_data_fwft_fifo_th;
-}DPP_NPPU_OAM_CFG_TXPKT_DATA_FWFT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_tstpkt_fwft_fifo_th_t
-{
-    ZXIC_UINT32 tstpkt_fwft_fifo_th;
-}DPP_NPPU_OAM_CFG_TSTPKT_FWFT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_tst_txinst_fwft_fifo_th_t
-{
-    ZXIC_UINT32 tst_txinst_fwft_fifo_th;
-}DPP_NPPU_OAM_CFG_TST_TXINST_FWFT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_tstrx_main_en_t
-{
-    ZXIC_UINT32 tstrx_main_en;
-}DPP_NPPU_OAM_CFG_TSTRX_MAIN_EN_T;
-
-typedef struct dpp_nppu_oam_cfg_tsttx_cfg_para_tbl2_t
-{
-    ZXIC_UINT32 ddr_self_test_tx_en;
-    ZXIC_UINT32 tm_self_test_tx_en;
-    ZXIC_UINT32 fast_aging_tx_en;
-    ZXIC_UINT32 timing_aging_tx_en;
-    ZXIC_UINT32 backgroud_flow_tx_en;
-    ZXIC_UINT32 tsttx_tx_en;
-    ZXIC_UINT32 tx_freq;
-    ZXIC_UINT32 tx_offset;
-}DPP_NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL2_T;
-
-typedef struct dpp_nppu_oam_cfg_tsttx_cfg_para_tbl1_t
-{
-    ZXIC_UINT32 tx_count;
-}DPP_NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL1_T;
-
-typedef struct dpp_nppu_oam_cfg_tsttx_cfg_para_tbl0_t
-{
-    ZXIC_UINT32 fast_tx_mode_en;
-    ZXIC_UINT32 tsttx_tx_head_len;
-    ZXIC_UINT32 tsttx_tx_interval;
-}DPP_NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL0_T;
-
-typedef struct dpp_nppu_oam_cfg_tstrx_cfg_para_t
-{
-    ZXIC_UINT32 tstrx_session_num;
-    ZXIC_UINT32 tstrx_session_en;
-}DPP_NPPU_OAM_CFG_TSTRX_CFG_PARA_T;
-
-typedef struct dpp_nppu_oam_cfg_fifo_status_int_en_0_t
-{
-    ZXIC_UINT32 fifo_status_int_en_31;
-    ZXIC_UINT32 fifo_status_int_en_30;
-    ZXIC_UINT32 fifo_status_int_en_29;
-    ZXIC_UINT32 fifo_status_int_en_28;
-    ZXIC_UINT32 fifo_status_int_en_27;
-    ZXIC_UINT32 fifo_status_int_en_26;
-    ZXIC_UINT32 fifo_status_int_en_25;
-    ZXIC_UINT32 fifo_status_int_en_24;
-    ZXIC_UINT32 fifo_status_int_en_23;
-    ZXIC_UINT32 fifo_status_int_en_22;
-    ZXIC_UINT32 fifo_status_int_en_21;
-    ZXIC_UINT32 fifo_status_int_en_20;
-    ZXIC_UINT32 fifo_status_int_en_19;
-    ZXIC_UINT32 fifo_status_int_en_18;
-    ZXIC_UINT32 fifo_status_int_en_17;
-    ZXIC_UINT32 fifo_status_int_en_16;
-    ZXIC_UINT32 fifo_status_int_en_15;
-    ZXIC_UINT32 fifo_status_int_en_14;
-    ZXIC_UINT32 fifo_status_int_en_13;
-    ZXIC_UINT32 fifo_status_int_en_12;
-    ZXIC_UINT32 fifo_status_int_en_11;
-    ZXIC_UINT32 fifo_status_int_en_10;
-    ZXIC_UINT32 fifo_status_int_en_9;
-    ZXIC_UINT32 fifo_status_int_en_8;
-    ZXIC_UINT32 fifo_status_int_en_7;
-    ZXIC_UINT32 fifo_status_int_en_6;
-    ZXIC_UINT32 fifo_status_int_en_5;
-    ZXIC_UINT32 fifo_status_int_en_4;
-    ZXIC_UINT32 fifo_status_int_en_3;
-    ZXIC_UINT32 fifo_status_int_en_2;
-    ZXIC_UINT32 fifo_status_int_en_1;
-    ZXIC_UINT32 fifo_status_int_en_0;
-}DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_EN_0_T;
-
-typedef struct dpp_nppu_oam_cfg_fifo_status_int_en_1_t
-{
-    ZXIC_UINT32 fifo_status_int_en_41;
-    ZXIC_UINT32 fifo_status_int_en_40;
-    ZXIC_UINT32 fifo_status_int_en_39;
-    ZXIC_UINT32 fifo_status_int_en_38;
-    ZXIC_UINT32 fifo_status_int_en_37;
-    ZXIC_UINT32 fifo_status_int_en_36;
-    ZXIC_UINT32 fifo_status_int_en_35;
-    ZXIC_UINT32 fifo_status_int_en_34;
-    ZXIC_UINT32 fifo_status_int_en_33;
-    ZXIC_UINT32 fifo_status_int_en_32;
-}DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_EN_1_T;
-
-typedef struct dpp_nppu_oam_cfg_fifo_status_int_mask_0_t
-{
-    ZXIC_UINT32 fifo_status_int_mask_31;
-    ZXIC_UINT32 fifo_status_int_mask_30;
-    ZXIC_UINT32 fifo_status_int_mask_29;
-    ZXIC_UINT32 fifo_status_int_mask_28;
-    ZXIC_UINT32 fifo_status_int_mask_27;
-    ZXIC_UINT32 fifo_status_int_mask_26;
-    ZXIC_UINT32 fifo_status_int_mask_25;
-    ZXIC_UINT32 fifo_status_int_mask_24;
-    ZXIC_UINT32 fifo_status_int_mask_23;
-    ZXIC_UINT32 fifo_status_int_mask_22;
-    ZXIC_UINT32 fifo_status_int_mask_21;
-    ZXIC_UINT32 fifo_status_int_mask_20;
-    ZXIC_UINT32 fifo_status_int_mask_19;
-    ZXIC_UINT32 fifo_status_int_mask_18;
-    ZXIC_UINT32 fifo_status_int_mask_17;
-    ZXIC_UINT32 fifo_status_int_mask_16;
-    ZXIC_UINT32 fifo_status_int_mask_15;
-    ZXIC_UINT32 fifo_status_int_mask_14;
-    ZXIC_UINT32 fifo_status_int_mask_13;
-    ZXIC_UINT32 fifo_status_int_mask_12;
-    ZXIC_UINT32 fifo_status_int_mask_11;
-    ZXIC_UINT32 fifo_status_int_mask_10;
-    ZXIC_UINT32 fifo_status_int_mask_9;
-    ZXIC_UINT32 fifo_status_int_mask_8;
-    ZXIC_UINT32 fifo_status_int_mask_7;
-    ZXIC_UINT32 fifo_status_int_mask_6;
-    ZXIC_UINT32 fifo_status_int_mask_5;
-    ZXIC_UINT32 fifo_status_int_mask_4;
-    ZXIC_UINT32 fifo_status_int_mask_3;
-    ZXIC_UINT32 fifo_status_int_mask_2;
-    ZXIC_UINT32 fifo_status_int_mask_1;
-    ZXIC_UINT32 fifo_status_int_mask_0;
-}DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_0_T;
-
-typedef struct dpp_nppu_oam_cfg_fifo_status_int_mask_1_t
-{
-    ZXIC_UINT32 fifo_status_int_mask_41;
-    ZXIC_UINT32 fifo_status_int_mask_40;
-    ZXIC_UINT32 fifo_status_int_mask_39;
-    ZXIC_UINT32 fifo_status_int_mask_38;
-    ZXIC_UINT32 fifo_status_int_mask_37;
-    ZXIC_UINT32 fifo_status_int_mask_36;
-    ZXIC_UINT32 fifo_status_int_mask_35;
-    ZXIC_UINT32 fifo_status_int_mask_34;
-    ZXIC_UINT32 fifo_status_int_mask_33;
-    ZXIC_UINT32 fifo_status_int_mask_32;
-}DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_1_T;
-
-typedef struct dpp_nppu_oam_cfg_fifo_status_int_status_t
-{
-    ZXIC_UINT32 fifo_status_int_status;
-}DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS_T;
-
-typedef struct dpp_nppu_oam_cfg_main_frequency_t
-{
-    ZXIC_UINT32 main_frequency;
-}DPP_NPPU_OAM_CFG_MAIN_FREQUENCY_T;
-
-typedef struct dpp_nppu_oam_cfg_oam_cfg_type_t
-{
-    ZXIC_UINT32 oam_cfg_type;
-}DPP_NPPU_OAM_CFG_OAM_CFG_TYPE_T;
-
-typedef struct dpp_nppu_oam_cfg_fst_swch_eth_head0_t
-{
-    ZXIC_UINT32 fst_swch_eth_head;
-}DPP_NPPU_OAM_CFG_FST_SWCH_ETH_HEAD0_T;
-
-typedef struct dpp_nppu_oam_cfg_fst_swch_eth_head1_t
-{
-    ZXIC_UINT32 fst_swch_eth_head1;
-}DPP_NPPU_OAM_CFG_FST_SWCH_ETH_HEAD1_T;
-
-typedef struct dpp_nppu_oam_cfg_fst_swch_eth_head2_t
-{
-    ZXIC_UINT32 fst_swch_eth_head2;
-}DPP_NPPU_OAM_CFG_FST_SWCH_ETH_HEAD2_T;
-
-typedef struct dpp_nppu_oam_cfg_fst_swch_eth_head3_t
-{
-    ZXIC_UINT32 fst_swch_eth_head3;
-}DPP_NPPU_OAM_CFG_FST_SWCH_ETH_HEAD3_T;
-
-typedef struct dpp_nppu_oam_cfg_oam_fs_txinst_fifo_th_t
-{
-    ZXIC_UINT32 oam_fs_txinst_fifo_th;
-}DPP_NPPU_OAM_CFG_OAM_FS_TXINST_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_oam_ma_fs_txinst_fifo_th_t
-{
-    ZXIC_UINT32 oam_ma_fs_txinst_fifo_th;
-}DPP_NPPU_OAM_CFG_OAM_MA_FS_TXINST_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_pon_int_ram_clr_t
-{
-    ZXIC_UINT32 pon_int_ram_clr;
-}DPP_NPPU_OAM_CFG_PON_INT_RAM_CLR_T;
-
-typedef struct dpp_nppu_oam_cfg_pon_p_int_index_t
-{
-    ZXIC_UINT32 pon_p_int_index;
-}DPP_NPPU_OAM_CFG_PON_P_INT_INDEX_T;
-
-typedef struct dpp_nppu_oam_cfg_pon_protect_pkt_fifo_th_t
-{
-    ZXIC_UINT32 pon_protect_pkt_fifo_th;
-}DPP_NPPU_OAM_CFG_PON_PROTECT_PKT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_pon_laser_off_en_t
-{
-    ZXIC_UINT32 pon_laser_off_en;
-}DPP_NPPU_OAM_CFG_PON_LASER_OFF_EN_T;
-
-typedef struct dpp_nppu_oam_cfg_pon_prtct_pkt_tx_en_t
-{
-    ZXIC_UINT32 pon_prtct_pkt_tx_en;
-}DPP_NPPU_OAM_CFG_PON_PRTCT_PKT_TX_EN_T;
-
-typedef struct dpp_nppu_oam_cfg_cfg_pon_master_t
-{
-    ZXIC_UINT32 cfg_pon_master;
-}DPP_NPPU_OAM_CFG_CFG_PON_MASTER_T;
-
-typedef struct dpp_nppu_oam_cfg_level_mode_t
-{
-    ZXIC_UINT32 level_mode;
-}DPP_NPPU_OAM_CFG_LEVEL_MODE_T;
-
-typedef struct dpp_nppu_oam_cfg_interrupt_en_t
-{
-    ZXIC_UINT32 interrupt_en;
-}DPP_NPPU_OAM_CFG_INTERRUPT_EN_T;
-
-typedef struct dpp_nppu_oam_cfg_pon_laser_on_en_t
-{
-    ZXIC_UINT32 pon_laser_on_en;
-}DPP_NPPU_OAM_CFG_PON_LASER_ON_EN_T;
-
-typedef struct dpp_nppu_oam_cfg_ti_pon_sd_t
-{
-    ZXIC_UINT32 ti_pon_sd;
-}DPP_NPPU_OAM_CFG_TI_PON_SD_T;
-
-typedef struct dpp_nppu_oam_cfg_ti_pon_los_t
-{
-    ZXIC_UINT32 ti_pon_los;
-}DPP_NPPU_OAM_CFG_TI_PON_LOS_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_dat4_t
-{
-    ZXIC_UINT32 ind_dat4;
-}DPP_NPPU_OAM_CFG_IND_DAT4_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_dat5_t
-{
-    ZXIC_UINT32 ind_dat5;
-}DPP_NPPU_OAM_CFG_IND_DAT5_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_dat6_t
-{
-    ZXIC_UINT32 ind_dat6;
-}DPP_NPPU_OAM_CFG_IND_DAT6_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_dat7_t
-{
-    ZXIC_UINT32 ind_dat7;
-}DPP_NPPU_OAM_CFG_IND_DAT7_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_dat8_t
-{
-    ZXIC_UINT32 ind_dat8;
-}DPP_NPPU_OAM_CFG_IND_DAT8_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_dat9_t
-{
-    ZXIC_UINT32 ind_dat9;
-}DPP_NPPU_OAM_CFG_IND_DAT9_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_dat10_t
-{
-    ZXIC_UINT32 ind_dat10;
-}DPP_NPPU_OAM_CFG_IND_DAT10_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_dat11_t
-{
-    ZXIC_UINT32 ind_dat11;
-}DPP_NPPU_OAM_CFG_IND_DAT11_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_dat12_t
-{
-    ZXIC_UINT32 ind_dat12;
-}DPP_NPPU_OAM_CFG_IND_DAT12_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_dat13_t
-{
-    ZXIC_UINT32 ind_dat13;
-}DPP_NPPU_OAM_CFG_IND_DAT13_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_dat14_t
-{
-    ZXIC_UINT32 ind_dat14;
-}DPP_NPPU_OAM_CFG_IND_DAT14_T;
-
-typedef struct dpp_nppu_oam_cfg_ind_dat15_t
-{
-    ZXIC_UINT32 ind_dat15;
-}DPP_NPPU_OAM_CFG_IND_DAT15_T;
-
-typedef struct dpp_nppu_oam_cfg_oam_2544_pkt_fifo_th_t
-{
-    ZXIC_UINT32 oam_2544_pkt_fifo_th;
-}DPP_NPPU_OAM_CFG_OAM_2544_PKT_FIFO_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_txinfo_ram_clr_t
-{
-    ZXIC_UINT32 txinfo_ram_clr;
-}DPP_NPPU_OAM_CFG_TXINFO_RAM_CLR_T;
-
-typedef struct dpp_nppu_oam_cfg_txinfo_ram_init_done_t
-{
-    ZXIC_UINT32 txinfo_ram_init_done;
-}DPP_NPPU_OAM_CFG_TXINFO_RAM_INIT_DONE_T;
-
-typedef struct dpp_nppu_oam_cfg_fifo_status_int_status40_t
-{
-    ZXIC_UINT32 fifo_status_int_status40;
-}DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS40_T;
-
-typedef struct dpp_nppu_oam_cfg_fifo_status_int_status41_t
-{
-    ZXIC_UINT32 fifo_status_int_status41;
-}DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS41_T;
-
-typedef struct dpp_nppu_oam_cfg_oam_2544_fun_en_t
-{
-    ZXIC_UINT32 oam_2544_fun_en;
-}DPP_NPPU_OAM_CFG_OAM_2544_FUN_EN_T;
-
-typedef struct dpp_nppu_oam_cfg_oam_2544_stat_clr_t
-{
-    ZXIC_UINT32 oam_2544_stat_clr;
-}DPP_NPPU_OAM_CFG_OAM_2544_STAT_CLR_T;
-
-typedef struct dpp_nppu_oam_cfg_txdis_default_t
-{
-    ZXIC_UINT32 txdis_default;
-}DPP_NPPU_OAM_CFG_TXDIS_DEFAULT_T;
-
-typedef struct dpp_nppu_oam_cfg_txdis_default_en_t
-{
-    ZXIC_UINT32 txdis_default_en;
-}DPP_NPPU_OAM_CFG_TXDIS_DEFAULT_EN_T;
-
-typedef struct dpp_nppu_oam_cfg_tpbfd_firstchk_th_t
-{
-    ZXIC_UINT32 tpbfd_firstchk_th;
-}DPP_NPPU_OAM_CFG_TPBFD_FIRSTCHK_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_ethccm_firstchk_th_t
-{
-    ZXIC_UINT32 ethccm_firstchk_th;
-}DPP_NPPU_OAM_CFG_ETHCCM_FIRSTCHK_TH_T;
-
-typedef struct dpp_nppu_oam_cfg_tpccm_firstchk_th_t
-{
-    ZXIC_UINT32 tpccm_firstchk_th;
-}DPP_NPPU_OAM_CFG_TPCCM_FIRSTCHK_TH_T;
-
-typedef struct dpp_nppu_oam_stat_txstat_req_cnt_t
-{
-    ZXIC_UINT32 txstat_req_cnt;
-}DPP_NPPU_OAM_STAT_TXSTAT_REQ_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_chkstat_req_cnt_t
-{
-    ZXIC_UINT32 chkstat_req_cnt;
-}DPP_NPPU_OAM_STAT_CHKSTAT_REQ_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_stat_oam_fc_cnt_t
-{
-    ZXIC_UINT32 stat1_oam_fc_cnt;
-}DPP_NPPU_OAM_STAT_STAT_OAM_FC_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_bfdseq_req_cnt_t
-{
-    ZXIC_UINT32 bfdseq_req_cnt;
-}DPP_NPPU_OAM_STAT_BFDSEQ_REQ_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_lmcnt_req_cnt_t
-{
-    ZXIC_UINT32 lmcnt_req_cnt;
-}DPP_NPPU_OAM_STAT_LMCNT_REQ_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_stat_oam_lm_rsp_cnt_t
-{
-    ZXIC_UINT32 stat2_rsp_cnt;
-}DPP_NPPU_OAM_STAT_STAT_OAM_LM_RSP_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_stat_oam_lm_fc_cnt_t
-{
-    ZXIC_UINT32 stat2_oam_fc_cnt;
-}DPP_NPPU_OAM_STAT_STAT_OAM_LM_FC_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_se_req_cnt_t
-{
-    ZXIC_UINT32 se_req_cnt;
-}DPP_NPPU_OAM_STAT_SE_REQ_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_se_rsp_cnt_t
-{
-    ZXIC_UINT32 se_rsp_cnt;
-}DPP_NPPU_OAM_STAT_SE_RSP_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_se_oam_fc_cnt_t
-{
-    ZXIC_UINT32 se_oam_fc_cnt;
-}DPP_NPPU_OAM_STAT_SE_OAM_FC_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_oam_se_fc_cnt_t
-{
-    ZXIC_UINT32 oam_se_fc_cnt;
-}DPP_NPPU_OAM_STAT_OAM_SE_FC_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_oam_pktrx_sop_cnt_t
-{
-    ZXIC_UINT32 oam_pktrx_sop_cnt;
-}DPP_NPPU_OAM_STAT_OAM_PKTRX_SOP_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_oam_pktrx_eop_cnt_t
-{
-    ZXIC_UINT32 oam_pktrx_eop_cnt;
-}DPP_NPPU_OAM_STAT_OAM_PKTRX_EOP_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_pktrx_oam_fc_cnt_t
-{
-    ZXIC_UINT32 pktrx_oam_fc_cnt;
-}DPP_NPPU_OAM_STAT_PKTRX_OAM_FC_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_pktrx_oam_tst_fc_cnt_t
-{
-    ZXIC_UINT32 pktrx_oam_tst_fc_cnt;
-}DPP_NPPU_OAM_STAT_PKTRX_OAM_TST_FC_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_odma_oam_sop_cnt_t
-{
-    ZXIC_UINT32 odma_oam_sop_cnt;
-}DPP_NPPU_OAM_STAT_ODMA_OAM_SOP_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_odma_oam_eop_cnt_t
-{
-    ZXIC_UINT32 odma_oam_eop_cnt;
-}DPP_NPPU_OAM_STAT_ODMA_OAM_EOP_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_oam_odma_fc_cnt_t
-{
-    ZXIC_UINT32 oam_odma_fc_cnt;
-}DPP_NPPU_OAM_STAT_OAM_ODMA_FC_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_rec_ma_pkt_illegal_cnt_t
-{
-    ZXIC_UINT32 rec_ma_pkt_illegal_cnt;
-}DPP_NPPU_OAM_STAT_REC_MA_PKT_ILLEGAL_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_rec_rmep_pkt_illegal_cnt_t
-{
-    ZXIC_UINT32 rec_rmep_pkt_illegal_cnt;
-}DPP_NPPU_OAM_STAT_REC_RMEP_PKT_ILLEGAL_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_rec_eth_ais_pkt_cnt_t
-{
-    ZXIC_UINT32 rec_eth_ais_pkt_cnt;
-}DPP_NPPU_OAM_STAT_REC_ETH_AIS_PKT_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_rec_tp_ais_pkt_cnt_t
-{
-    ZXIC_UINT32 rec_tp_ais_pkt_cnt;
-}DPP_NPPU_OAM_STAT_REC_TP_AIS_PKT_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_rec_tp_csf_pkt_cnt_t
-{
-    ZXIC_UINT32 rec_tp_csf_pkt_cnt;
-}DPP_NPPU_OAM_STAT_REC_TP_CSF_PKT_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_rec_eth_level_defect_cnt_t
-{
-    ZXIC_UINT32 rec_eth_level_defect_cnt;
-}DPP_NPPU_OAM_STAT_REC_ETH_LEVEL_DEFECT_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_rec_eth_megid_defect_cnt_t
-{
-    ZXIC_UINT32 rec_eth_megid_defect_cnt;
-}DPP_NPPU_OAM_STAT_REC_ETH_MEGID_DEFECT_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_rec_eth_mepid_defect_cnt_t
-{
-    ZXIC_UINT32 rec_eth_mepid_defect_cnt;
-}DPP_NPPU_OAM_STAT_REC_ETH_MEPID_DEFECT_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_rec_eth_interval_defect_cnt_t
-{
-    ZXIC_UINT32 rec_eth_interval_defect_cnt;
-}DPP_NPPU_OAM_STAT_REC_ETH_INTERVAL_DEFECT_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_rec_sess_unenable_cnt_t
-{
-    ZXIC_UINT32 rec_sess_unenable_cnt;
-}DPP_NPPU_OAM_STAT_REC_SESS_UNENABLE_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_oam_2544_rd_pkt_cnt_t
-{
-    ZXIC_UINT32 oam_2544_rd_pkt_cnt;
-}DPP_NPPU_OAM_STAT_OAM_2544_RD_PKT_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_debug_cnt_clr_t
-{
-    ZXIC_UINT32 debug_cnt_clr;
-}DPP_NPPU_OAM_STAT_DEBUG_CNT_CLR_T;
-
-typedef struct dpp_nppu_oam_stat_oam_pktrx_catch_data_t
-{
-    ZXIC_UINT32 oam_pktrx_catch_data;
-}DPP_NPPU_OAM_STAT_OAM_PKTRX_CATCH_DATA_T;
-
-typedef struct dpp_nppu_oam_stat_odma_oam_catch_data_t
-{
-    ZXIC_UINT32 odma_oam_catch_data;
-}DPP_NPPU_OAM_STAT_ODMA_OAM_CATCH_DATA_T;
-
-typedef struct dpp_nppu_oam_stat_tst_session_tx_cnt_t
-{
-    ZXIC_UINT32 tst_session_tx_cnt;
-}DPP_NPPU_OAM_STAT_TST_SESSION_TX_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_tst_session_rx_cnt_t
-{
-    ZXIC_UINT32 tst_session_rx_cnt;
-}DPP_NPPU_OAM_STAT_TST_SESSION_RX_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_tstrx_lost_cnt_t
-{
-    ZXIC_UINT32 tstrx_lost_cnt;
-}DPP_NPPU_OAM_STAT_TSTRX_LOST_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_bfdseq_wr_cnt_t
-{
-    ZXIC_UINT32 bfdseq_wr_cnt;
-}DPP_NPPU_OAM_STAT_BFDSEQ_WR_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_bfdtime_wr_cnt_t
-{
-    ZXIC_UINT32 bfdtime_wr_cnt;
-}DPP_NPPU_OAM_STAT_BFDTIME_WR_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_lmcnt_wr_cnt_t
-{
-    ZXIC_UINT32 lmcnt_wr_cnt;
-}DPP_NPPU_OAM_STAT_LMCNT_WR_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_oam_fs_pkt_cnt_t
-{
-    ZXIC_UINT32 oam_fs_pkt_cnt;
-}DPP_NPPU_OAM_STAT_OAM_FS_PKT_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_oam_ma_fs_pkt_cnt_t
-{
-    ZXIC_UINT32 lmcnt_wr_cnt;
-}DPP_NPPU_OAM_STAT_OAM_MA_FS_PKT_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_rec_tp_level_defect_cnt_t
-{
-    ZXIC_UINT32 rec_tp_level_defect_cnt;
-}DPP_NPPU_OAM_STAT_REC_TP_LEVEL_DEFECT_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_rec_tp_megid_defect_cnt_t
-{
-    ZXIC_UINT32 rec_tp_megid_defect_cnt;
-}DPP_NPPU_OAM_STAT_REC_TP_MEGID_DEFECT_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_rec_tp_mepid_defect_cnt_t
-{
-    ZXIC_UINT32 rec_tp_mepid_defect_cnt;
-}DPP_NPPU_OAM_STAT_REC_TP_MEPID_DEFECT_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_rec_tp_interval_defect_cnt_t
-{
-    ZXIC_UINT32 rec_tp_interval_defect_cnt;
-}DPP_NPPU_OAM_STAT_REC_TP_INTERVAL_DEFECT_CNT_T;
-
-typedef struct dpp_nppu_oam_stat_rd_reg_clear_mode_t
-{
-    ZXIC_UINT32 rd_clear_mode_cfg;
-}DPP_NPPU_OAM_STAT_RD_REG_CLEAR_MODE_T;
-
-typedef struct dpp_nppu_oam_stat_rd_data_reg_clear_mode_t
-{
-    ZXIC_UINT32 rd_data_reg_clear_mode_cfg;
-}DPP_NPPU_OAM_STAT_RD_DATA_REG_CLEAR_MODE_T;
-
-typedef struct dpp_nppu_oam_cfg_indir_oam_int_status_ram_0_t
-{
-    ZXIC_UINT32 bfd_diag_value_bit4;
-    ZXIC_UINT32 bfd_diag_value_bit3;
-    ZXIC_UINT32 bfd_diag_value_bit2;
-    ZXIC_UINT32 bfd_diag_value_bit1;
-    ZXIC_UINT32 bfd_diag_value_bit0;
-    ZXIC_UINT32 dloc_int;
-    ZXIC_UINT32 drdi_int;
-}DPP_NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM_0_T;
-
-typedef struct dpp_nppu_oam_cfg_indir_oam_int_status_ram1_t
-{
-    ZXIC_UINT32 sticky_error_level_defect;
-    ZXIC_UINT32 sticky_error_megid_defect;
-    ZXIC_UINT32 sticky_error_mepid_defect;
-    ZXIC_UINT32 sticky_error_inter_defect;
-    ZXIC_UINT32 sticky_ais_defect;
-    ZXIC_UINT32 sticky_csf_defect;
-    ZXIC_UINT32 current_error_level_defect;
-    ZXIC_UINT32 current_error_megid_defect;
-    ZXIC_UINT32 current_error_mepid_defect;
-    ZXIC_UINT32 current_error_inter_defect;
-    ZXIC_UINT32 current_ais_defect;
-    ZXIC_UINT32 current_csf_defect;
-}DPP_NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM1_T;
-
-typedef struct dpp_nppu_oam_cfg_indir_tst_pkt_tx_para_ram_t
-{
-    ZXIC_UINT32 ddr_self_test_tx_en;
-    ZXIC_UINT32 tm_self_test_tx_en;
-    ZXIC_UINT32 fast_aging_tx_en;
-    ZXIC_UINT32 timing_aging_tx_en;
-    ZXIC_UINT32 backgroud_flow_tx_en;
-    ZXIC_UINT32 tsttx_session_en;
-    ZXIC_UINT32 tx_freq;
-    ZXIC_UINT32 tx_offset;
-    ZXIC_UINT32 tx_count;
-    ZXIC_UINT32 fast_tx_mode_en;
-    ZXIC_UINT32 tsttx_pkthead_len;
-    ZXIC_UINT32 tsttx_interval;
-}DPP_NPPU_OAM_CFG_INDIR_TST_PKT_TX_PARA_RAM_T;
-
-typedef struct dpp_nppu_oam_cfg_indir_groupnumram_t
-{
-    ZXIC_UINT32 mep_down_num;
-}DPP_NPPU_OAM_CFG_INDIR_GROUPNUMRAM_T;
-
-typedef struct dpp_nppu_oam_cfg_indir_oam_tx_tbl_ram_t
-{
-    ZXIC_UINT32 oam_tx_en;
-    ZXIC_UINT32 oam_tx_type;
-    ZXIC_UINT32 oam_fetch_len;
-    ZXIC_UINT32 bfd_seq_tx_en;
-    ZXIC_UINT32 tx_para;
-    ZXIC_UINT32 oam_tx_interval;
-    ZXIC_UINT32 hd_ena_flag;
-    ZXIC_UINT32 last_tx_time;
-}DPP_NPPU_OAM_CFG_INDIR_OAM_TX_TBL_RAM_T;
-
-typedef struct dpp_nppu_oam_cfg_indir_oam_chk_tbl_ram_t
-{
-    ZXIC_UINT32 fast_switch_en;
-    ZXIC_UINT32 oam_chk_en;
-    ZXIC_UINT32 oam_chk_type;
-    ZXIC_UINT32 ccm_predel_flag;
-    ZXIC_UINT32 lm_chk_en;
-    ZXIC_UINT32 ccm_group_id;
-    ZXIC_UINT32 oam_chk_internal;
-    ZXIC_UINT32 fist_chk_flag;
-    ZXIC_UINT32 last_chk_time;
-}DPP_NPPU_OAM_CFG_INDIR_OAM_CHK_TBL_RAM_T;
-
-typedef struct dpp_nppu_oam_cfg_indir_oam_ma_chk_tbl_ram_t
-{
-    ZXIC_UINT32 ma_fast_switch_en;
-    ZXIC_UINT32 ma_chk_en;
-    ZXIC_UINT32 ma_type;
-    ZXIC_UINT32 error_level_defect_en;
-    ZXIC_UINT32 error_megid_defect_en;
-    ZXIC_UINT32 error_mepid_defect_en;
-    ZXIC_UINT32 error_inter_defect_en;
-    ZXIC_UINT32 ais_defect_en;
-    ZXIC_UINT32 csf_defect_en;
-    ZXIC_UINT32 error_level_defect_ccm;
-    ZXIC_UINT32 error_megid_defect_ccm;
-    ZXIC_UINT32 error_mepid_defect_ccm;
-    ZXIC_UINT32 error_inter_defect_ccm;
-    ZXIC_UINT32 ais_defect_ccm;
-    ZXIC_UINT32 csf_defect_ccm;
-    ZXIC_UINT32 ma_predel_en;
-    ZXIC_UINT32 error_level_defect_ts;
-    ZXIC_UINT32 error_megid_defect_ts;
-    ZXIC_UINT32 error_mepid_defect_ts;
-    ZXIC_UINT32 error_inter_defect_ts;
-    ZXIC_UINT32 ais_defect_ts;
-    ZXIC_UINT32 csf_defect_ts;
-}DPP_NPPU_OAM_CFG_INDIR_OAM_MA_CHK_TBL_RAM_T;
-
-typedef struct dpp_nppu_oam_cfg_indir_oam_2544_tx_ram_t
-{
-    ZXIC_UINT32 tx_en_2544;
-    ZXIC_UINT32 tx_cfg_times_2544;
-    ZXIC_UINT32 current_times;
-    ZXIC_UINT32 slice_num;
-    ZXIC_UINT32 pkt_mty;
-}DPP_NPPU_OAM_CFG_INDIR_OAM_2544_TX_RAM_T;
+typedef struct dpp_nppu_mr_cfg_cfg_shap_param_t {
+	ZXIC_UINT32 shap_en;
+	ZXIC_UINT32 shap_rate;
+} DPP_NPPU_MR_CFG_CFG_SHAP_PARAM_T;
+
+typedef struct dpp_nppu_mr_cfg_cfg_shap_token_t {
+	ZXIC_UINT32 cfg_shap_plen_offset;
+	ZXIC_UINT32 cfg_shap_token;
+} DPP_NPPU_MR_CFG_CFG_SHAP_TOKEN_T;
+
+typedef struct dpp_nppu_mr_cfg_idle_ptr_fifo_aful_th_t {
+	ZXIC_UINT32 idle_ptr3_fifo_aful_th;
+	ZXIC_UINT32 idle_ptr2_fifo_aful_th;
+	ZXIC_UINT32 idle_ptr1_fifo_aful_th;
+	ZXIC_UINT32 idle_ptr0_fifo_aful_th;
+} DPP_NPPU_MR_CFG_IDLE_PTR_FIFO_AFUL_TH_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos_port_cfg_t {
+	ZXIC_UINT32 cos3_port_cfg;
+	ZXIC_UINT32 cos2_port_cfg;
+	ZXIC_UINT32 cos1_port_cfg;
+	ZXIC_UINT32 cos0_port_cfg;
+} DPP_NPPU_MR_CFG_MR_COS_PORT_CFG_T;
+
+typedef struct dpp_nppu_pktrx_cfg_ind_status_t {
+	ZXIC_UINT32 ind_access_done;
+} DPP_NPPU_PKTRX_CFG_IND_STATUS_T;
+
+typedef struct dpp_nppu_pktrx_cfg_ind_cmd_t {
+	ZXIC_UINT32 ind_rd_or_wr;
+	ZXIC_UINT32 ind_mem_id;
+	ZXIC_UINT32 ind_mem_addr;
+} DPP_NPPU_PKTRX_CFG_IND_CMD_T;
+
+typedef struct dpp_nppu_pktrx_cfg_ind_data0_t {
+	ZXIC_UINT32 ind_dat0;
+} DPP_NPPU_PKTRX_CFG_IND_DATA0_T;
+
+typedef struct dpp_nppu_pktrx_cfg_ind_data1_t {
+	ZXIC_UINT32 ind_dat1;
+} DPP_NPPU_PKTRX_CFG_IND_DATA1_T;
+
+typedef struct dpp_nppu_pktrx_cfg_ind_data2_t {
+	ZXIC_UINT32 ind_dat2;
+} DPP_NPPU_PKTRX_CFG_IND_DATA2_T;
+
+typedef struct dpp_nppu_pktrx_cfg_ind_data3_t {
+	ZXIC_UINT32 ind_dat3;
+} DPP_NPPU_PKTRX_CFG_IND_DATA3_T;
+
+typedef struct dpp_nppu_pktrx_cfg_ind_data4_t {
+	ZXIC_UINT32 ind_dat4;
+} DPP_NPPU_PKTRX_CFG_IND_DATA4_T;
+
+typedef struct dpp_nppu_pktrx_cfg_ind_data5_t {
+	ZXIC_UINT32 ind_dat5;
+} DPP_NPPU_PKTRX_CFG_IND_DATA5_T;
+
+typedef struct dpp_nppu_pktrx_cfg_ind_data6_t {
+	ZXIC_UINT32 ind_dat6;
+} DPP_NPPU_PKTRX_CFG_IND_DATA6_T;
+
+typedef struct dpp_nppu_pktrx_cfg_ind_data7_t {
+	ZXIC_UINT32 ind_dat7;
+} DPP_NPPU_PKTRX_CFG_IND_DATA7_T;
+
+typedef struct dpp_nppu_pktrx_cfg_tcam_0_cmd_t {
+	ZXIC_UINT32 cfg_vben;
+	ZXIC_UINT32 cfg_vbi;
+	ZXIC_UINT32 cfg_t_strwc;
+	ZXIC_UINT32 tcam0_sm;
+	ZXIC_UINT32 tcam0_smen;
+	ZXIC_UINT32 tcam0_rm;
+	ZXIC_UINT32 tcam0_rmen;
+	ZXIC_UINT32 tcam0_enable;
+	ZXIC_UINT32 tcam0_flush;
+	ZXIC_UINT32 tcam0_unload;
+	ZXIC_UINT32 tcam0_unload_addr;
+} DPP_NPPU_PKTRX_CFG_TCAM_0_CMD_T;
+
+typedef struct dpp_nppu_pktrx_cfg_tcam_1_cmd_t {
+	ZXIC_UINT32 tcam1_sm;
+	ZXIC_UINT32 tcam1_smen;
+	ZXIC_UINT32 tcam1_rm;
+	ZXIC_UINT32 tcam1_rmen;
+	ZXIC_UINT32 tcam1_enable;
+	ZXIC_UINT32 tcam1_flush;
+	ZXIC_UINT32 tcam1_unload;
+	ZXIC_UINT32 tcam1_unload_addr;
+} DPP_NPPU_PKTRX_CFG_TCAM_1_CMD_T;
+
+typedef struct dpp_nppu_pktrx_cfg_port_en_0_t {
+	ZXIC_UINT32 cfg_isch_port_en_0;
+} DPP_NPPU_PKTRX_CFG_PORT_EN_0_T;
+
+typedef struct dpp_nppu_pktrx_cfg_port_en_1_t {
+	ZXIC_UINT32 cfg_isch_port_en_1;
+} DPP_NPPU_PKTRX_CFG_PORT_EN_1_T;
+
+typedef struct dpp_nppu_pktrx_cfg_port_en_2_t {
+	ZXIC_UINT32 cfg_isch_port_en_2;
+} DPP_NPPU_PKTRX_CFG_PORT_EN_2_T;
+
+typedef struct dpp_nppu_pktrx_cfg_port_en_3_t {
+	ZXIC_UINT32 cfg_port_change_en_0;
+	ZXIC_UINT32 cfg_port_change_en_1;
+	ZXIC_UINT32 cfg_isch_port_en_3;
+} DPP_NPPU_PKTRX_CFG_PORT_EN_3_T;
+
+typedef struct dpp_nppu_pktrx_cfg_cfg_port_l2_offset_mode_0_t {
+	ZXIC_UINT32 cfg_port_l2_offset_mode_0;
+} DPP_NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_0_T;
+
+typedef struct dpp_nppu_pktrx_cfg_cfg_port_l2_offset_mode_1_t {
+	ZXIC_UINT32 cfg_port_l2_offset_mode_1;
+} DPP_NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_1_T;
+
+typedef struct dpp_nppu_pktrx_cfg_cfg_port_l2_offset_mode_2_t {
+	ZXIC_UINT32 cfg_port_l2_offset_mode_2;
+} DPP_NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_2_T;
+
+typedef struct dpp_nppu_pktrx_cfg_cfg_port_l2_offset_mode_3_t {
+	ZXIC_UINT32 cfg_port_l2_offset_mode_3;
+} DPP_NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_3_T;
+
+typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_0_t {
+	ZXIC_UINT32 cfg_isch_fc_mode_0;
+} DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_0_T;
+
+typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_1_t {
+	ZXIC_UINT32 cfg_isch_fc_mode_1;
+} DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_1_T;
+
+typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_2_t {
+	ZXIC_UINT32 cfg_isch_fc_mode_2;
+} DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_2_T;
+
+typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_3_t {
+	ZXIC_UINT32 cfg_isch_fc_mode_3;
+} DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_3_T;
+
+typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_4_t {
+	ZXIC_UINT32 cfg_isch_fc_mode_4;
+} DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_4_T;
+
+typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_5_t {
+	ZXIC_UINT32 cfg_isch_fc_mode_5;
+} DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_5_T;
+
+typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_6_t {
+	ZXIC_UINT32 cfg_isch_fc_mode_6;
+} DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_6_T;
+
+typedef struct dpp_nppu_pktrx_cfg_port_fc_mode_7_t {
+	ZXIC_UINT32 cfg_pfu_aging_en;
+	ZXIC_UINT32 cfg_isch_aging_en;
+	ZXIC_UINT32 cfg_isch_fc_mode_7;
+} DPP_NPPU_PKTRX_CFG_PORT_FC_MODE_7_T;
+
+typedef struct dpp_nppu_pktrx_cfg_cfg_isch_aging_th_t {
+	ZXIC_UINT32 cfg_pfu_delay_cycle;
+	ZXIC_UINT32 cfg_isch_aging_th;
+} DPP_NPPU_PKTRX_CFG_CFG_ISCH_AGING_TH_T;
+
+typedef struct dpp_nppu_pktrx_cfg_isch_fifo_th_0_t {
+	ZXIC_UINT32 cfg_sch_fifo3_fc_th;
+	ZXIC_UINT32 cfg_sch_fifo2_fc_th;
+	ZXIC_UINT32 cfg_sch_fifo1_fc_th;
+	ZXIC_UINT32 cfg_sch_fifo0_fc_th;
+} DPP_NPPU_PKTRX_CFG_ISCH_FIFO_TH_0_T;
+
+typedef struct dpp_nppu_pktrx_cfg_isch_cfg_1_t {
+	ZXIC_UINT32 cfg_parser_max_len_en;
+	ZXIC_UINT32 cfg_parser_max_len;
+	ZXIC_UINT32 cfg_parser_min_len_en;
+	ZXIC_UINT32 cfg_parser_min_len;
+	ZXIC_UINT32 sp_sch_sel;
+} DPP_NPPU_PKTRX_CFG_ISCH_CFG_1_T;
+
+typedef struct dpp_nppu_pktrx_cfg_tcam_0_vld_t {
+	ZXIC_UINT32 cfg_tcam0_vld;
+} DPP_NPPU_PKTRX_CFG_TCAM_0_VLD_T;
+
+typedef struct dpp_nppu_pktrx_cfg_tcam_1_vld_t {
+	ZXIC_UINT32 cfg_tcam1_vld;
+} DPP_NPPU_PKTRX_CFG_TCAM_1_VLD_T;
+
+typedef struct dpp_nppu_pktrx_cfg_cpu_port_en_mask_t {
+	ZXIC_UINT32 cpu_port_en_mask;
+} DPP_NPPU_PKTRX_CFG_CPU_PORT_EN_MASK_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_glbal_cfg_0_t {
+	ZXIC_UINT32 pktrx_glbal_cfg_0;
+} DPP_NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_0_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_glbal_cfg_1_t {
+	ZXIC_UINT32 pktrx_glbal_cfg_1;
+} DPP_NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_1_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_glbal_cfg_2_t {
+	ZXIC_UINT32 pktrx_glbal_cfg_2;
+} DPP_NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_2_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_glbal_cfg_3_t {
+	ZXIC_UINT32 pktrx_glbal_cfg_3;
+} DPP_NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_3_T;
+
+typedef struct dpp_nppu_pktrx_cfg_nppu_start_t {
+	ZXIC_UINT32 nppu_start;
+} DPP_NPPU_PKTRX_CFG_NPPU_START_T;
+
+typedef struct dpp_nppu_pktrx_stat_ind_status_t {
+	ZXIC_UINT32 ind_access_done;
+} DPP_NPPU_PKTRX_STAT_IND_STATUS_T;
+
+typedef struct dpp_nppu_pktrx_stat_ind_cmd_t {
+	ZXIC_UINT32 ind_rd_or_wr;
+	ZXIC_UINT32 ind_mem_id;
+	ZXIC_UINT32 ind_mem_addr;
+} DPP_NPPU_PKTRX_STAT_IND_CMD_T;
+
+typedef struct dpp_nppu_pktrx_stat_ind_data0_t {
+	ZXIC_UINT32 ind_dat0;
+} DPP_NPPU_PKTRX_STAT_IND_DATA0_T;
+
+typedef struct dpp_nppu_idma_cfg_debug_cnt_ovfl_mode_t {
+	ZXIC_UINT32 debug_cnt_ovfl_mode;
+} DPP_NPPU_IDMA_CFG_DEBUG_CNT_OVFL_MODE_T;
+
+typedef struct dpp_nppu_idma_stat_ind_status_t {
+	ZXIC_UINT32 ind_access_done;
+} DPP_NPPU_IDMA_STAT_IND_STATUS_T;
+
+typedef struct dpp_nppu_idma_stat_ind_cmd_t {
+	ZXIC_UINT32 ind_rd_or_wr;
+	ZXIC_UINT32 ind_mem_id;
+	ZXIC_UINT32 ind_mem_addr;
+} DPP_NPPU_IDMA_STAT_IND_CMD_T;
+
+typedef struct dpp_nppu_idma_stat_ind_data0_t {
+	ZXIC_UINT32 ind_data0;
+} DPP_NPPU_IDMA_STAT_IND_DATA0_T;
+
+typedef struct dpp_nppu_pbu_cfg_ind_status_t {
+	ZXIC_UINT32 ind_access_done;
+} DPP_NPPU_PBU_CFG_IND_STATUS_T;
+
+typedef struct dpp_nppu_pbu_cfg_ind_cmd_t {
+	ZXIC_UINT32 ind_rd_or_wr;
+	ZXIC_UINT32 ind_mem_id;
+	ZXIC_UINT32 ind_mem_addr;
+} DPP_NPPU_PBU_CFG_IND_CMD_T;
+
+typedef struct dpp_nppu_pbu_cfg_ind_data0_t {
+	ZXIC_UINT32 ind_data0;
+} DPP_NPPU_PBU_CFG_IND_DATA0_T;
+
+typedef struct dpp_nppu_pbu_cfg_ind_data1_t {
+	ZXIC_UINT32 ind_data1;
+} DPP_NPPU_PBU_CFG_IND_DATA1_T;
+
+typedef struct dpp_nppu_pbu_cfg_ind_data2_t {
+	ZXIC_UINT32 ind_data2;
+} DPP_NPPU_PBU_CFG_IND_DATA2_T;
+
+typedef struct dpp_nppu_pbu_cfg_ind_data3_t {
+	ZXIC_UINT32 ind_data3;
+} DPP_NPPU_PBU_CFG_IND_DATA3_T;
+
+typedef struct dpp_nppu_pbu_cfg_ind_data4_t {
+	ZXIC_UINT32 ind_data4;
+} DPP_NPPU_PBU_CFG_IND_DATA4_T;
+
+typedef struct dpp_nppu_pbu_cfg_ind_data5_t {
+	ZXIC_UINT32 ind_data5;
+} DPP_NPPU_PBU_CFG_IND_DATA5_T;
+
+typedef struct dpp_nppu_pbu_cfg_ind_data6_t {
+	ZXIC_UINT32 ind_data6;
+} DPP_NPPU_PBU_CFG_IND_DATA6_T;
+
+typedef struct dpp_nppu_pbu_cfg_ind_data7_t {
+	ZXIC_UINT32 ind_data7;
+} DPP_NPPU_PBU_CFG_IND_DATA7_T;
+
+typedef struct dpp_nppu_pbu_cfg_idma_public_th_t {
+	ZXIC_UINT32 idma_public_th;
+} DPP_NPPU_PBU_CFG_IDMA_PUBLIC_TH_T;
+
+typedef struct dpp_nppu_pbu_cfg_lif_public_th_t {
+	ZXIC_UINT32 lif_public_th;
+} DPP_NPPU_PBU_CFG_LIF_PUBLIC_TH_T;
+
+typedef struct dpp_nppu_pbu_cfg_idma_total_th_t {
+	ZXIC_UINT32 idma_total_th;
+} DPP_NPPU_PBU_CFG_IDMA_TOTAL_TH_T;
+
+typedef struct dpp_nppu_pbu_cfg_lif_total_th_t {
+	ZXIC_UINT32 lif_total_th;
+} DPP_NPPU_PBU_CFG_LIF_TOTAL_TH_T;
+
+typedef struct dpp_nppu_pbu_cfg_mc_total_th_t {
+	ZXIC_UINT32 mc_total_th;
+} DPP_NPPU_PBU_CFG_MC_TOTAL_TH_T;
+
+typedef struct dpp_nppu_pbu_cfg_mc_cos10_th_t {
+	ZXIC_UINT32 mc_cos1_mode;
+	ZXIC_UINT32 mc_cos0_mode;
+	ZXIC_UINT32 mc_cos1_th;
+	ZXIC_UINT32 mc_cos0_th;
+} DPP_NPPU_PBU_CFG_MC_COS10_TH_T;
+
+typedef struct dpp_nppu_pbu_cfg_mc_cos32_th_t {
+	ZXIC_UINT32 mc_cos3_mode;
+	ZXIC_UINT32 mc_cos2_mode;
+	ZXIC_UINT32 mc_cos3_th;
+	ZXIC_UINT32 mc_cos2_th;
+} DPP_NPPU_PBU_CFG_MC_COS32_TH_T;
+
+typedef struct dpp_nppu_pbu_cfg_mc_cos54_th_t {
+	ZXIC_UINT32 mc_cos5_mode;
+	ZXIC_UINT32 mc_cos4_mode;
+	ZXIC_UINT32 mc_cos5_th;
+	ZXIC_UINT32 mc_cos4_th;
+} DPP_NPPU_PBU_CFG_MC_COS54_TH_T;
+
+typedef struct dpp_nppu_pbu_cfg_mc_cos76_th_t {
+	ZXIC_UINT32 mc_cos7_mode;
+	ZXIC_UINT32 mc_cos6_mode;
+	ZXIC_UINT32 mc_cos7_th;
+	ZXIC_UINT32 mc_cos6_th;
+} DPP_NPPU_PBU_CFG_MC_COS76_TH_T;
+
+typedef struct dpp_nppu_pbu_cfg_debug_cnt_ovfl_mode_t {
+	ZXIC_UINT32 debug_cnt_ovfl_mode;
+} DPP_NPPU_PBU_CFG_DEBUG_CNT_OVFL_MODE_T;
+
+typedef struct dpp_nppu_pbu_cfg_se_key_aful_negate_cfg_t {
+	ZXIC_UINT32 se_key_aful_negate_cfg;
+} DPP_NPPU_PBU_CFG_SE_KEY_AFUL_NEGATE_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_sa_flag_t {
+	ZXIC_UINT32 sa_flag;
+} DPP_NPPU_PBU_CFG_SA_FLAG_T;
+
+typedef struct dpp_nppu_pbu_stat_ind_data_t {
+	ZXIC_UINT32 ind_data;
+} DPP_NPPU_PBU_STAT_IND_DATA_T;
+
+typedef struct dpp_nppu_pbu_stat_ind_status_t {
+	ZXIC_UINT32 ind_access_done;
+} DPP_NPPU_PBU_STAT_IND_STATUS_T;
+
+typedef struct dpp_nppu_pbu_stat_ind_cmd_t {
+	ZXIC_UINT32 ind_rd_or_wr;
+	ZXIC_UINT32 ind_mem_id;
+	ZXIC_UINT32 ind_mem_addr;
+} DPP_NPPU_PBU_STAT_IND_CMD_T;
+
+typedef struct dpp_nppu_pbu_stat_total_cnt_t {
+	ZXIC_UINT32 total_cnt;
+} DPP_NPPU_PBU_STAT_TOTAL_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_idma_pub_cnt_t {
+	ZXIC_UINT32 idma_pub_cnt;
+} DPP_NPPU_PBU_STAT_IDMA_PUB_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_lif_pub_cnt_t {
+	ZXIC_UINT32 lif_pub_cnt;
+} DPP_NPPU_PBU_STAT_LIF_PUB_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_mc_total_cnt_t {
+	ZXIC_UINT32 mc_total_cnt;
+} DPP_NPPU_PBU_STAT_MC_TOTAL_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_pbu_thram_init_done_t {
+	ZXIC_UINT32 pbu_thram_init_done;
+} DPP_NPPU_PBU_STAT_PBU_THRAM_INIT_DONE_T;
+
+typedef struct dpp_nppu_pbu_stat_ifb_fptr_init_done_t {
+	ZXIC_UINT32 ifb_fptr_init_done;
+} DPP_NPPU_PBU_STAT_IFB_FPTR_INIT_DONE_T;
+
+typedef struct dpp_nppu_isu_cfg_weight_normal_uc_t {
+	ZXIC_UINT32 weight_normal_uc;
+} DPP_NPPU_ISU_CFG_WEIGHT_NORMAL_UC_T;
+
+typedef struct dpp_nppu_isu_cfg_fabric_or_saip_t {
+	ZXIC_UINT32 fabric_or_saip;
+} DPP_NPPU_ISU_CFG_FABRIC_OR_SAIP_T;
+
+typedef struct dpp_nppu_isu_stat_ind_status_t {
+	ZXIC_UINT32 ind_access_done;
+} DPP_NPPU_ISU_STAT_IND_STATUS_T;
+
+typedef struct dpp_nppu_isu_stat_ind_cmd_t {
+	ZXIC_UINT32 ind_rd_or_wr;
+	ZXIC_UINT32 ind_mem_id;
+	ZXIC_UINT32 ind_mem_addr;
+} DPP_NPPU_ISU_STAT_IND_CMD_T;
+
+typedef struct dpp_nppu_isu_stat_ind_dat0_t {
+	ZXIC_UINT32 ind_dat0;
+} DPP_NPPU_ISU_STAT_IND_DAT0_T;
+
+typedef struct dpp_nppu_odma_cfg_ind_access_done_t {
+	ZXIC_UINT32 ind_access_done;
+} DPP_NPPU_ODMA_CFG_IND_ACCESS_DONE_T;
+
+typedef struct dpp_nppu_odma_cfg_ind_command_t {
+	ZXIC_UINT32 ind_rd_or_wr;
+	ZXIC_UINT32 ind_mem_id;
+	ZXIC_UINT32 ind_mem_addr;
+} DPP_NPPU_ODMA_CFG_IND_COMMAND_T;
+
+typedef struct dpp_nppu_odma_cfg_ind_dat0_t {
+	ZXIC_UINT32 ind_dat0;
+} DPP_NPPU_ODMA_CFG_IND_DAT0_T;
+
+typedef struct dpp_nppu_odma_cfg_ind_dat1_t {
+	ZXIC_UINT32 ind_dat1;
+} DPP_NPPU_ODMA_CFG_IND_DAT1_T;
+
+typedef struct dpp_nppu_odma_cfg_fabric_or_saip_t {
+	ZXIC_UINT32 fabric_or_saip;
+} DPP_NPPU_ODMA_CFG_FABRIC_OR_SAIP_T;
+
+typedef struct dpp_nppu_odma_cfg_max_pkt_len_t {
+	ZXIC_UINT32 max_pkt_len;
+} DPP_NPPU_ODMA_CFG_MAX_PKT_LEN_T;
+
+typedef struct dpp_nppu_odma_cfg_age_en_t {
+	ZXIC_UINT32 age_en;
+} DPP_NPPU_ODMA_CFG_AGE_EN_T;
+
+typedef struct dpp_nppu_odma_cfg_age_mode_t {
+	ZXIC_UINT32 age_mode;
+} DPP_NPPU_ODMA_CFG_AGE_MODE_T;
+
+typedef struct dpp_nppu_odma_cfg_age_value_time_t {
+	ZXIC_UINT32 age_value_time;
+} DPP_NPPU_ODMA_CFG_AGE_VALUE_TIME_T;
+
+typedef struct dpp_nppu_odma_cfg_age_value_room_t {
+	ZXIC_UINT32 age_value_room;
+} DPP_NPPU_ODMA_CFG_AGE_VALUE_ROOM_T;
+
+typedef struct dpp_nppu_odma_cfg_age_out_cnt_t {
+	ZXIC_UINT32 age_out_cnt;
+} DPP_NPPU_ODMA_CFG_AGE_OUT_CNT_T;
+
+typedef struct dpp_nppu_odma_cfg_token_value_a_t {
+	ZXIC_UINT32 token_value_a;
+} DPP_NPPU_ODMA_CFG_TOKEN_VALUE_A_T;
+
+typedef struct dpp_nppu_odma_cfg_token_value_b_t {
+	ZXIC_UINT32 token_value_b;
+} DPP_NPPU_ODMA_CFG_TOKEN_VALUE_B_T;
+
+typedef struct dpp_nppu_odma_cfg_cfg_shap_en_p0_t {
+	ZXIC_UINT32 cfg_shap_en_p0;
+} DPP_NPPU_ODMA_CFG_CFG_SHAP_EN_P0_T;
+
+typedef struct dpp_nppu_odma_cfg_cfg_shap_en_p1_t {
+	ZXIC_UINT32 cfg_shap_en_p1;
+} DPP_NPPU_ODMA_CFG_CFG_SHAP_EN_P1_T;
+
+typedef struct dpp_nppu_odma_cfg_cfg_shap_en_tm_t {
+	ZXIC_UINT32 cfg_shap_en_tm;
+} DPP_NPPU_ODMA_CFG_CFG_SHAP_EN_TM_T;
+
+typedef struct dpp_nppu_odma_stat_ind_status_t {
+	ZXIC_UINT32 ind_access_done;
+} DPP_NPPU_ODMA_STAT_IND_STATUS_T;
+
+typedef struct dpp_nppu_odma_stat_ind_cmd_t {
+	ZXIC_UINT32 ind_rd_or_wr;
+	ZXIC_UINT32 ind_mem_id;
+	ZXIC_UINT32 ind_mem_addr;
+} DPP_NPPU_ODMA_STAT_IND_CMD_T;
+
+typedef struct dpp_nppu_odma_stat_ind_data0_t {
+	ZXIC_UINT32 ind_dat0;
+} DPP_NPPU_ODMA_STAT_IND_DATA0_T;
+
+typedef struct dpp_nppu_odma_stat_debug_cnt_cfg_t {
+	ZXIC_UINT32 debug_cnt_ovf_mode;
+	ZXIC_UINT32 debug_cnt_rdclr_mode;
+	ZXIC_UINT32 user_cnt_value;
+} DPP_NPPU_ODMA_STAT_DEBUG_CNT_CFG_T;
+
+typedef struct dpp_nppu_oam_cfg_bfd_firstchk_th_t {
+	ZXIC_UINT32 bfd_firstchk_th;
+} DPP_NPPU_OAM_CFG_BFD_FIRSTCHK_TH_T;
+
+typedef struct dpp_nppu_pbu_cfg_memid_0_pbu_fc_idmath_ram_t {
+	ZXIC_UINT32 lif_th_15;
+	ZXIC_UINT32 lif_prv_15;
+	ZXIC_UINT32 idma_prv_15;
+	ZXIC_UINT32 idma_th_cos0_15;
+	ZXIC_UINT32 idma_th_cos1_15;
+	ZXIC_UINT32 idma_th_cos2_15;
+	ZXIC_UINT32 idma_th_cos3_15;
+	ZXIC_UINT32 idma_th_cos4_15;
+	ZXIC_UINT32 idma_th_cos5_15;
+	ZXIC_UINT32 idma_th_cos6_15;
+	ZXIC_UINT32 idma_th_cos7_15;
+} DPP_NPPU_PBU_CFG_MEMID_0_PBU_FC_IDMATH_RAM_T;
+
+typedef struct dpp_nppu_pbu_cfg_memid_1_pbu_fc_macth_ram_t {
+	ZXIC_UINT32 cos7_th;
+	ZXIC_UINT32 cos6_th;
+	ZXIC_UINT32 cos5_th;
+	ZXIC_UINT32 cos4_th;
+	ZXIC_UINT32 cos3_th;
+	ZXIC_UINT32 cos2_th;
+	ZXIC_UINT32 cos1_th;
+	ZXIC_UINT32 cos0_th;
+} DPP_NPPU_PBU_CFG_MEMID_1_PBU_FC_MACTH_RAM_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_1_all_kind_port_cnt_t {
+	ZXIC_UINT32 peak_port_cnt;
+	ZXIC_UINT32 current_port_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_1_ALL_KIND_PORT_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_2_ppu_pbu_ifb_req_vld_cnt_t {
+	ZXIC_UINT32 ppu_pbu_ifb_req_vld_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_2_PPU_PBU_IFB_REQ_VLD_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_ifb_rsp_vld_cnt_t {
+	ZXIC_UINT32 pbu_ppu_ifb_rsp_vld_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_IFB_RSP_VLD_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_2_odma_pbu_recy_ptr_vld_cnt_t {
+	ZXIC_UINT32 odma_pbu_recy_ptr_vld_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_2_ODMA_PBU_RECY_PTR_VLD_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_2_ppu_pbu_mcode_pf_req_cnt_t {
+	ZXIC_UINT32 ppu_pbu_mcode_pf_req_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_2_PPU_PBU_MCODE_PF_REQ_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_rsp_cnt_t {
+	ZXIC_UINT32 pbu_ppu_mcode_pf_rsp_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_RSP_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_2_ppu_pbu_logic_pf_req_cnt_t {
+	ZXIC_UINT32 ppu_pbu_logic_pf_req_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_2_PPU_PBU_LOGIC_PF_REQ_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_rsp_cnt_t {
+	ZXIC_UINT32 pbu_ppu_logic_pf_rsp_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_RSP_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_2_ppu_use_ptr_pulse_cnt_t {
+	ZXIC_UINT32 ppu_use_ptr_pulse_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_2_PPU_USE_PTR_PULSE_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_2_ppu_pbu_wb_vld_cnt_t {
+	ZXIC_UINT32 ppu_pbu_wb_vld_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_2_PPU_PBU_WB_VLD_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_reorder_para_vld_cnt_t {
+	ZXIC_UINT32 pbu_ppu_reorder_para_vld_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_REORDER_PARA_VLD_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_2_se_pbu_dpi_key_vld_cnt_t {
+	ZXIC_UINT32 se_pbu_dpi_key_vld_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_2_SE_PBU_DPI_KEY_VLD_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_2_pbu_se_dpi_rsp_datvld_cnt_t {
+	ZXIC_UINT32 pbu_se_dpi_rsp_datvld_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_2_PBU_SE_DPI_RSP_DATVLD_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd1_cnt_t {
+	ZXIC_UINT32 odma_pbu_ifb_rd1_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD1_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd2_cnt_t {
+	ZXIC_UINT32 odma_pbu_ifb_rd2_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD2_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_no_rsp_cnt_t {
+	ZXIC_UINT32 pbu_ppu_mcode_pf_no_rsp_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_NO_RSP_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_no_rsp_cnt_t {
+	ZXIC_UINT32 pbu_ppu_logic_pf_no_rsp_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_NO_RSP_CNT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_3_cpu_rd_ifb_data_t {
+	ZXIC_UINT32 cpu_rd_ifb_data;
+} DPP_NPPU_PBU_STAT_MEMID_3_CPU_RD_IFB_DATA_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_4_mux_sel_rgt_t {
+	ZXIC_UINT32 current_port_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_4_MUX_SEL_RGT_T;
+
+typedef struct dpp_nppu_pbu_stat_memid_5_port_pub_cnt_t {
+	ZXIC_UINT32 port_pub_cnt;
+} DPP_NPPU_PBU_STAT_MEMID_5_PORT_PUB_CNT_T;
+
+typedef struct dpp_nppu_idma_stat_memid_1_idma_o_isu_pkt_pulse_total_cnt_t {
+	ZXIC_UINT32 idma_o_isu_pkt_pulse_total_cnt;
+} DPP_NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_PKT_PULSE_TOTAL_CNT_T;
+
+typedef struct dpp_nppu_idma_stat_memid_1_idma_o_isu_epkt_pulse_total_cnt_t {
+	ZXIC_UINT32 idma_o_isu_epkt_pulse_total_cnt;
+} DPP_NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_EPKT_PULSE_TOTAL_CNT_T;
+
+typedef struct dpp_nppu_idma_stat_memid_1_idma_dispkt_pulse_total_cnt_t {
+	ZXIC_UINT32 idma_dispkt_pulse_total_cnt;
+} DPP_NPPU_IDMA_STAT_MEMID_1_IDMA_DISPKT_PULSE_TOTAL_CNT_T;
+
+typedef struct dpp_nppu_idma_stat_memid_0_idma_o_isu_pkt_pulse_cnt_t {
+	ZXIC_UINT32 idma_o_isu_pkt_pulse_cnt;
+} DPP_NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_PKT_PULSE_CNT_T;
+
+typedef struct dpp_nppu_idma_stat_memid_0_idma_o_isu_epkt_pulse_cnt_t {
+	ZXIC_UINT32 idma_o_isu_epkt_pulse_cnt;
+} DPP_NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_EPKT_PULSE_CNT_T;
+
+typedef struct dpp_nppu_idma_stat_memid_0_idma_dispkt_pulse_cnt_t {
+	ZXIC_UINT32 idma_dispkt_pulse_cnt;
+} DPP_NPPU_IDMA_STAT_MEMID_0_IDMA_DISPKT_PULSE_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_ind_access_states_t {
+	ZXIC_UINT32 ind_access_done;
+} DPP_NPPU_MR_CFG_IND_ACCESS_STATES_T;
+
+typedef struct dpp_nppu_mr_cfg_ind_access_cmd0_t {
+	ZXIC_UINT32 wr_mode;
+	ZXIC_UINT32 rd_or_wr;
+	ZXIC_UINT32 ind_access_addr0;
+} DPP_NPPU_MR_CFG_IND_ACCESS_CMD0_T;
+
+typedef struct dpp_nppu_mr_cfg_ind_access_data0_t {
+	ZXIC_UINT32 ind_access_data0;
+} DPP_NPPU_MR_CFG_IND_ACCESS_DATA0_T;
+
+typedef struct dpp_nppu_mr_cfg_ind_access_data1_t {
+	ZXIC_UINT32 ind_access_data1;
+} DPP_NPPU_MR_CFG_IND_ACCESS_DATA1_T;
+
+typedef struct dpp_nppu_mr_cfg_ind_access_cmd1_t {
+	ZXIC_UINT32 ind_access_addr1;
+} DPP_NPPU_MR_CFG_IND_ACCESS_CMD1_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_init_done_t {
+	ZXIC_UINT32 mr_init_done;
+} DPP_NPPU_MR_CFG_MR_INIT_DONE_T;
+
+typedef struct dpp_nppu_mr_cfg_cnt_mode_reg_t {
+	ZXIC_UINT32 cfgmt_count_rd_mode;
+	ZXIC_UINT32 cfgmt_count_overflow_mode;
+} DPP_NPPU_MR_CFG_CNT_MODE_REG_T;
+
+typedef struct dpp_nppu_mr_cfg_cfg_ecc_bypass_read_t {
+	ZXIC_UINT32 cfg_ecc_bypass_read;
+} DPP_NPPU_MR_CFG_CFG_ECC_BYPASS_READ_T;
+
+typedef struct dpp_nppu_mr_cfg_cfg_rep_mod_t {
+	ZXIC_UINT32 cfg_rep_mod;
+} DPP_NPPU_MR_CFG_CFG_REP_MOD_T;
+
+typedef struct dpp_nppu_mr_cfg_block_ptr_fifo_aful_th_t {
+	ZXIC_UINT32 block_ptr3_fifo_aful_th;
+	ZXIC_UINT32 block_ptr2_fifo_aful_th;
+	ZXIC_UINT32 block_ptr1_fifo_aful_th;
+	ZXIC_UINT32 block_ptr0_fifo_aful_th;
+} DPP_NPPU_MR_CFG_BLOCK_PTR_FIFO_AFUL_TH_T;
+
+typedef struct dpp_nppu_mr_cfg_pre_rcv_ptr_fifo_aful_th_t {
+	ZXIC_UINT32 pre_rcv_ptr3_fifo_aful_th;
+	ZXIC_UINT32 pre_rcv_ptr2_fifo_aful_th;
+	ZXIC_UINT32 pre_rcv_ptr1_fifo_aful_th;
+	ZXIC_UINT32 pre_rcv_ptr0_fifo_aful_th;
+} DPP_NPPU_MR_CFG_PRE_RCV_PTR_FIFO_AFUL_TH_T;
+
+typedef struct dpp_nppu_mr_cfg_mgid_fifo_aful_th_t {
+	ZXIC_UINT32 mgid3_fifo_aful_th;
+	ZXIC_UINT32 mgid2_fifo_aful_th;
+	ZXIC_UINT32 mgid1_fifo_aful_th;
+	ZXIC_UINT32 mgid0_fifo_aful_th;
+} DPP_NPPU_MR_CFG_MGID_FIFO_AFUL_TH_T;
+
+typedef struct dpp_nppu_mr_cfg_rep_cmd_fifo_aful_th_t {
+	ZXIC_UINT32 rep_cmd3_fifo_aful_th;
+	ZXIC_UINT32 rep_cmd2_fifo_aful_th;
+	ZXIC_UINT32 rep_cmd1_fifo_aful_th;
+	ZXIC_UINT32 rep_cmd0_fifo_aful_th;
+} DPP_NPPU_MR_CFG_REP_CMD_FIFO_AFUL_TH_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_int_mask_1_t {
+	ZXIC_UINT32 free_ptr0_fifo_full_mask;
+	ZXIC_UINT32 free_ptr1_fifo_full_mask;
+	ZXIC_UINT32 free_ptr2_fifo_full_mask;
+	ZXIC_UINT32 free_ptr3_fifo_full_mask;
+	ZXIC_UINT32 block_ptr0_fifo_full_mask;
+	ZXIC_UINT32 block_ptr1_fifo_full_mask;
+	ZXIC_UINT32 block_ptr2_fifo_full_mask;
+	ZXIC_UINT32 block_ptr3_fifo_full_mask;
+	ZXIC_UINT32 mgid0_fifo_full_mask;
+	ZXIC_UINT32 mgid1_fifo_full_mask;
+	ZXIC_UINT32 mgid2_fifo_full_mask;
+	ZXIC_UINT32 mgid3_fifo_full_mask;
+	ZXIC_UINT32 pre_rcv_ptr0_fifo_full_mask;
+	ZXIC_UINT32 pre_rcv_ptr1_fifo_full_mask;
+	ZXIC_UINT32 pre_rcv_ptr2_fifo_full_mask;
+	ZXIC_UINT32 pre_rcv_ptr3_fifo_full_mask;
+	ZXIC_UINT32 rep_cmd0_fifo_full_mask;
+	ZXIC_UINT32 rep_cmd1_fifo_full_mask;
+	ZXIC_UINT32 rep_cmd2_fifo_full_mask;
+	ZXIC_UINT32 rep_cmd3_fifo_full_mask;
+} DPP_NPPU_MR_CFG_MR_INT_MASK_1_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_int_mask_2_t {
+	ZXIC_UINT32 free_ptr0_fifo_udf_mask;
+	ZXIC_UINT32 free_ptr1_fifo_udf_mask;
+	ZXIC_UINT32 free_ptr2_fifo_udf_mask;
+	ZXIC_UINT32 free_ptr3_fifo_udf_mask;
+	ZXIC_UINT32 block_ptr0_fifo_udf_mask;
+	ZXIC_UINT32 block_ptr1_fifo_udf_mask;
+	ZXIC_UINT32 block_ptr2_fifo_udf_mask;
+	ZXIC_UINT32 block_ptr3_fifo_udf_mask;
+	ZXIC_UINT32 mgid0_fifo_udf_mask;
+	ZXIC_UINT32 mgid1_fifo_udf_mask;
+	ZXIC_UINT32 mgid2_fifo_udf_mask;
+	ZXIC_UINT32 mgid3_fifo_udf_mask;
+	ZXIC_UINT32 pre_rcv_ptr0_fifo_udf_mask;
+	ZXIC_UINT32 pre_rcv_ptr1_fifo_udf_mask;
+	ZXIC_UINT32 pre_rcv_ptr2_fifo_udf_mask;
+	ZXIC_UINT32 pre_rcv_ptr3_fifo_udf_mask;
+	ZXIC_UINT32 rep_cmd0_fifo_udf_mask;
+	ZXIC_UINT32 rep_cmd1_fifo_udf_mask;
+	ZXIC_UINT32 rep_cmd2_fifo_udf_mask;
+	ZXIC_UINT32 rep_cmd3_fifo_udf_mask;
+} DPP_NPPU_MR_CFG_MR_INT_MASK_2_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_int_mask_3_t {
+	ZXIC_UINT32 free_ptr0_fifo_ovf_mask;
+	ZXIC_UINT32 free_ptr1_fifo_ovf_mask;
+	ZXIC_UINT32 free_ptr2_fifo_ovf_mask;
+	ZXIC_UINT32 free_ptr3_fifo_ovf_mask;
+	ZXIC_UINT32 block_ptr0_fifo_ovf_mask;
+	ZXIC_UINT32 block_ptr1_fifo_ovf_mask;
+	ZXIC_UINT32 block_ptr2_fifo_ovf_mask;
+	ZXIC_UINT32 block_ptr3_fifo_ovf_mask;
+	ZXIC_UINT32 mgid0_fifo_ovf_mask;
+	ZXIC_UINT32 mgid1_fifo_ovf_mask;
+	ZXIC_UINT32 mgid2_fifo_ovf_mask;
+	ZXIC_UINT32 mgid3_fifo_ovf_mask;
+	ZXIC_UINT32 pre_rcv_ptr0_fifo_ovf_mask;
+	ZXIC_UINT32 pre_rcv_ptr1_fifo_ovf_mask;
+	ZXIC_UINT32 pre_rcv_ptr2_fifo_ovf_mask;
+	ZXIC_UINT32 pre_rcv_ptr3_fifo_ovf_mask;
+	ZXIC_UINT32 rep_cmd0_fifo_ovf_mask;
+	ZXIC_UINT32 rep_cmd1_fifo_ovf_mask;
+	ZXIC_UINT32 rep_cmd2_fifo_ovf_mask;
+	ZXIC_UINT32 rep_cmd3_fifo_ovf_mask;
+} DPP_NPPU_MR_CFG_MR_INT_MASK_3_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_int_mask_4_t {
+	ZXIC_UINT32 data_buf0_ram_parity_err_mask;
+	ZXIC_UINT32 data_buf1_ram_parity_err_mask;
+	ZXIC_UINT32 data_buf2_ram_parity_err_mask;
+	ZXIC_UINT32 data_buf3_ram_parity_err_mask;
+	ZXIC_UINT32 mlt_ecc_single_err_mask;
+	ZXIC_UINT32 free_ptr0_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 free_ptr1_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 free_ptr2_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 free_ptr3_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 block_ptr0_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 block_ptr1_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 block_ptr2_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 block_ptr3_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 mgid0_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 mgid1_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 mgid2_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 mgid3_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 pre_rcv_ptr0_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 pre_rcv_ptr1_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 pre_rcv_ptr2_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 pre_rcv_ptr3_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 rep_cmd0_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 rep_cmd1_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 rep_cmd2_fifo_ecc_single_err_mask;
+	ZXIC_UINT32 rep_cmd3_fifo_ecc_single_err_mask;
+} DPP_NPPU_MR_CFG_MR_INT_MASK_4_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_states_1_t {
+	ZXIC_UINT32 free_ptr0_fifo_full;
+	ZXIC_UINT32 free_ptr1_fifo_full;
+	ZXIC_UINT32 free_ptr2_fifo_full;
+	ZXIC_UINT32 free_ptr3_fifo_full;
+	ZXIC_UINT32 block_ptr0_fifo_full;
+	ZXIC_UINT32 block_ptr1_fifo_full;
+	ZXIC_UINT32 block_ptr2_fifo_full;
+	ZXIC_UINT32 block_ptr3_fifo_full;
+	ZXIC_UINT32 mgid0_fifo_full;
+	ZXIC_UINT32 mgid1_fifo_full;
+	ZXIC_UINT32 mgid2_fifo_full;
+	ZXIC_UINT32 mgid3_fifo_full;
+	ZXIC_UINT32 pre_rcv_ptr0_fifo_full;
+	ZXIC_UINT32 pre_rcv_ptr1_fifo_full;
+	ZXIC_UINT32 pre_rcv_ptr2_fifo_full;
+	ZXIC_UINT32 pre_rcv_ptr3_fifo_full;
+	ZXIC_UINT32 rep_cmd0_fifo_full;
+	ZXIC_UINT32 rep_cmd1_fifo_full;
+	ZXIC_UINT32 rep_cmd2_fifo_full;
+	ZXIC_UINT32 rep_cmd3_fifo_full;
+} DPP_NPPU_MR_CFG_MR_STATES_1_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_states_2_t {
+	ZXIC_UINT32 free_ptr0_fifo_udf;
+	ZXIC_UINT32 free_ptr1_fifo_udf;
+	ZXIC_UINT32 free_ptr2_fifo_udf;
+	ZXIC_UINT32 free_ptr3_fifo_udf;
+	ZXIC_UINT32 block_ptr0_fifo_udf;
+	ZXIC_UINT32 block_ptr1_fifo_udf;
+	ZXIC_UINT32 block_ptr2_fifo_udf;
+	ZXIC_UINT32 block_ptr3_fifo_udf;
+	ZXIC_UINT32 mgid0_fifo_udf;
+	ZXIC_UINT32 mgid1_fifo_udf;
+	ZXIC_UINT32 mgid2_fifo_udf;
+	ZXIC_UINT32 mgid3_fifo_udf;
+	ZXIC_UINT32 pre_rcv_ptr0_fifo_udf;
+	ZXIC_UINT32 pre_rcv_ptr1_fifo_udf;
+	ZXIC_UINT32 pre_rcv_ptr2_fifo_udf;
+	ZXIC_UINT32 pre_rcv_ptr3_fifo_udf;
+	ZXIC_UINT32 rep_cmd0_fifo_udf;
+	ZXIC_UINT32 rep_cmd1_fifo_udf;
+	ZXIC_UINT32 rep_cmd2_fifo_udf;
+	ZXIC_UINT32 rep_cmd3_fifo_udf;
+} DPP_NPPU_MR_CFG_MR_STATES_2_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_states_3_t {
+	ZXIC_UINT32 free_ptr0_fifo_ovf;
+	ZXIC_UINT32 free_ptr1_fifo_ovf;
+	ZXIC_UINT32 free_ptr2_fifo_ovf;
+	ZXIC_UINT32 free_ptr3_fifo_ovf;
+	ZXIC_UINT32 block_ptr0_fifo_ovf;
+	ZXIC_UINT32 block_ptr1_fifo_ovf;
+	ZXIC_UINT32 block_ptr2_fifo_ovf;
+	ZXIC_UINT32 block_ptr3_fifo_ovf;
+	ZXIC_UINT32 mgid0_fifo_ovf;
+	ZXIC_UINT32 mgid1_fifo_ovf;
+	ZXIC_UINT32 mgid2_fifo_ovf;
+	ZXIC_UINT32 mgid3_fifo_ovf;
+	ZXIC_UINT32 pre_rcv_ptr0_fifo_ovf;
+	ZXIC_UINT32 pre_rcv_ptr1_fifo_ovf;
+	ZXIC_UINT32 pre_rcv_ptr2_fifo_ovf;
+	ZXIC_UINT32 pre_rcv_ptr3_fifo_ovf;
+	ZXIC_UINT32 rep_cmd0_fifo_ovf;
+	ZXIC_UINT32 rep_cmd1_fifo_ovf;
+	ZXIC_UINT32 rep_cmd2_fifo_ovf;
+	ZXIC_UINT32 rep_cmd3_fifo_ovf;
+} DPP_NPPU_MR_CFG_MR_STATES_3_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_states_4_t {
+	ZXIC_UINT32 data_buf0_ram_parity_err;
+	ZXIC_UINT32 data_buf1_ram_parity_err;
+	ZXIC_UINT32 data_buf2_ram_parity_err;
+	ZXIC_UINT32 data_buf3_ram_parity_err;
+	ZXIC_UINT32 mlt_ecc_single_err;
+	ZXIC_UINT32 free_ptr0_fifo_ecc_single_err;
+	ZXIC_UINT32 free_ptr1_fifo_ecc_single_err;
+	ZXIC_UINT32 free_ptr2_fifo_ecc_single_err;
+	ZXIC_UINT32 free_ptr3_fifo_ecc_single_err;
+	ZXIC_UINT32 block_ptr0_fifo_ecc_single_err;
+	ZXIC_UINT32 block_ptr1_fifo_ecc_single_err;
+	ZXIC_UINT32 block_ptr2_fifo_ecc_single_err;
+	ZXIC_UINT32 block_ptr3_fifo_ecc_single_err;
+	ZXIC_UINT32 mgid0_fifo_ecc_single_err;
+	ZXIC_UINT32 mgid1_fifo_ecc_single_err;
+	ZXIC_UINT32 mgid2_fifo_ecc_single_err;
+	ZXIC_UINT32 mgid3_fifo_ecc_single_err;
+	ZXIC_UINT32 pre_rcv_ptr0_fifo_ecc_single_err;
+	ZXIC_UINT32 pre_rcv_ptr1_fifo_ecc_single_err;
+	ZXIC_UINT32 pre_rcv_ptr2_fifo_ecc_single_err;
+	ZXIC_UINT32 pre_rcv_ptr3_fifo_ecc_single_err;
+	ZXIC_UINT32 rep_cmd0_fifo_ecc_single_err;
+	ZXIC_UINT32 rep_cmd1_fifo_ecc_single_err;
+	ZXIC_UINT32 rep_cmd2_fifo_ecc_single_err;
+	ZXIC_UINT32 rep_cmd3_fifo_ecc_single_err;
+} DPP_NPPU_MR_CFG_MR_STATES_4_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_states_5_t {
+	ZXIC_UINT32 mlt_ecc_double_err;
+	ZXIC_UINT32 free_ptr0_fifo_ecc_double_err;
+	ZXIC_UINT32 free_ptr1_fifo_ecc_double_err;
+	ZXIC_UINT32 free_ptr2_fifo_ecc_double_err;
+	ZXIC_UINT32 free_ptr3_fifo_ecc_double_err;
+	ZXIC_UINT32 block_ptr0_fifo_ecc_double_err;
+	ZXIC_UINT32 block_ptr1_fifo_ecc_double_err;
+	ZXIC_UINT32 block_ptr2_fifo_ecc_double_err;
+	ZXIC_UINT32 block_ptr3_fifo_ecc_double_err;
+	ZXIC_UINT32 mgid0_fifo_ecc_double_err;
+	ZXIC_UINT32 mgid1_fifo_ecc_double_err;
+	ZXIC_UINT32 mgid2_fifo_ecc_double_err;
+	ZXIC_UINT32 mgid3_fifo_ecc_double_err;
+	ZXIC_UINT32 pre_rcv_ptr0_fifo_ecc_double_err;
+	ZXIC_UINT32 pre_rcv_ptr1_fifo_ecc_double_err;
+	ZXIC_UINT32 pre_rcv_ptr2_fifo_ecc_double_err;
+	ZXIC_UINT32 pre_rcv_ptr3_fifo_ecc_double_err;
+	ZXIC_UINT32 rep_cmd0_fifo_ecc_double_err;
+	ZXIC_UINT32 rep_cmd1_fifo_ecc_double_err;
+	ZXIC_UINT32 rep_cmd2_fifo_ecc_double_err;
+	ZXIC_UINT32 rep_cmd3_fifo_ecc_double_err;
+} DPP_NPPU_MR_CFG_MR_STATES_5_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_states_6_t {
+	ZXIC_UINT32 free_ptr0_fifo_empty;
+	ZXIC_UINT32 free_ptr1_fifo_empty;
+	ZXIC_UINT32 free_ptr2_fifo_empty;
+	ZXIC_UINT32 free_ptr3_fifo_empty;
+	ZXIC_UINT32 block_ptr0_fifo_empty;
+	ZXIC_UINT32 block_ptr1_fifo_empty;
+	ZXIC_UINT32 block_ptr2_fifo_empty;
+	ZXIC_UINT32 block_ptr3_fifo_empty;
+	ZXIC_UINT32 mgid0_fifo_empty;
+	ZXIC_UINT32 mgid1_fifo_empty;
+	ZXIC_UINT32 mgid2_fifo_empty;
+	ZXIC_UINT32 mgid3_fifo_empty;
+	ZXIC_UINT32 pre_rcv_ptr0_fifo_empty;
+	ZXIC_UINT32 pre_rcv_ptr1_fifo_empty;
+	ZXIC_UINT32 pre_rcv_ptr2_fifo_empty;
+	ZXIC_UINT32 pre_rcv_ptr3_fifo_empty;
+	ZXIC_UINT32 rep_cmd0_fifo_empty;
+	ZXIC_UINT32 rep_cmd1_fifo_empty;
+	ZXIC_UINT32 rep_cmd2_fifo_empty;
+	ZXIC_UINT32 rep_cmd3_fifo_empty;
+} DPP_NPPU_MR_CFG_MR_STATES_6_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_states_7_t {
+	ZXIC_UINT32 cos0_is_rep_busy;
+	ZXIC_UINT32 cos1_is_rep_busy;
+	ZXIC_UINT32 cos2_is_rep_busy;
+	ZXIC_UINT32 cos3_is_rep_busy;
+	ZXIC_UINT32 block_ptr0_fifo_non_sop_ren_rdy;
+	ZXIC_UINT32 block_ptr1_fifo_non_sop_ren_rdy;
+	ZXIC_UINT32 block_ptr2_fifo_non_sop_ren_rdy;
+	ZXIC_UINT32 block_ptr3_fifo_non_sop_ren_rdy;
+	ZXIC_UINT32 pre_rcv_ptr0_fifo_non_sop_ren_rdy;
+	ZXIC_UINT32 pre_rcv_ptr1_fifo_non_sop_ren_rdy;
+	ZXIC_UINT32 pre_rcv_ptr2_fifo_non_sop_ren_rdy;
+	ZXIC_UINT32 pre_rcv_ptr3_fifo_non_sop_ren_rdy;
+	ZXIC_UINT32 port_shap_rdy;
+	ZXIC_UINT32 mr_lif_group0_rdy_3;
+	ZXIC_UINT32 mr_lif_group0_rdy_2;
+	ZXIC_UINT32 mr_lif_group0_rdy_1;
+	ZXIC_UINT32 mr_lif_group0_rdy_0;
+	ZXIC_UINT32 pktrx_pfc_rdy_3;
+	ZXIC_UINT32 pktrx_pfc_rdy_2;
+	ZXIC_UINT32 pktrx_pfc_rdy_1;
+	ZXIC_UINT32 pktrx_pfc_rdy_0;
+	ZXIC_UINT32 pktrx_link_rdy;
+} DPP_NPPU_MR_CFG_MR_STATES_7_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_states_8_t {
+	ZXIC_UINT32 mr_head;
+} DPP_NPPU_MR_CFG_MR_STATES_8_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_sop_in_cnt_t {
+	ZXIC_UINT32 mr_sop_in_cnt;
+} DPP_NPPU_MR_CFG_MR_SOP_IN_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_eop_in_cnt_t {
+	ZXIC_UINT32 mr_eop_in_cnt;
+} DPP_NPPU_MR_CFG_MR_EOP_IN_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_sop_out_cnt_t {
+	ZXIC_UINT32 mr_sop_out_cnt;
+} DPP_NPPU_MR_CFG_MR_SOP_OUT_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_eop_out_cnt_t {
+	ZXIC_UINT32 mr_eop_out_cnt;
+} DPP_NPPU_MR_CFG_MR_EOP_OUT_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos0_in_cnt_t {
+	ZXIC_UINT32 mr_cos0_in_cnt;
+} DPP_NPPU_MR_CFG_MR_COS0_IN_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos1_in_cnt_t {
+	ZXIC_UINT32 mr_cos1_in_cnt;
+} DPP_NPPU_MR_CFG_MR_COS1_IN_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos2_in_cnt_t {
+	ZXIC_UINT32 mr_cos2_in_cnt;
+} DPP_NPPU_MR_CFG_MR_COS2_IN_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos3_in_cnt_t {
+	ZXIC_UINT32 mr_cos3_in_cnt;
+} DPP_NPPU_MR_CFG_MR_COS3_IN_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos0_out_cnt_t {
+	ZXIC_UINT32 mr_cos0_out_cnt;
+} DPP_NPPU_MR_CFG_MR_COS0_OUT_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos1_out_cnt_t {
+	ZXIC_UINT32 mr_cos1_out_cnt;
+} DPP_NPPU_MR_CFG_MR_COS1_OUT_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos2_out_cnt_t {
+	ZXIC_UINT32 mr_cos2_out_cnt;
+} DPP_NPPU_MR_CFG_MR_COS2_OUT_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos3_out_cnt_t {
+	ZXIC_UINT32 mr_cos3_out_cnt;
+} DPP_NPPU_MR_CFG_MR_COS3_OUT_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_err_in_cnt_t {
+	ZXIC_UINT32 mr_err_in_cnt;
+} DPP_NPPU_MR_CFG_MR_ERR_IN_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos0_sop_in_cnt_t {
+	ZXIC_UINT32 mr_cos0_sop_in_cnt;
+} DPP_NPPU_MR_CFG_MR_COS0_SOP_IN_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos0_eop_in_cnt_t {
+	ZXIC_UINT32 mr_cos0_eop_in_cnt;
+} DPP_NPPU_MR_CFG_MR_COS0_EOP_IN_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos1_sop_in_cnt_t {
+	ZXIC_UINT32 mr_cos1_sop_in_cnt;
+} DPP_NPPU_MR_CFG_MR_COS1_SOP_IN_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos1_eop_in_cnt_t {
+	ZXIC_UINT32 mr_cos1_eop_in_cnt;
+} DPP_NPPU_MR_CFG_MR_COS1_EOP_IN_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos2_sop_in_cnt_t {
+	ZXIC_UINT32 mr_cos2_sop_in_cnt;
+} DPP_NPPU_MR_CFG_MR_COS2_SOP_IN_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos2_eop_in_cnt_t {
+	ZXIC_UINT32 mr_cos2_eop_in_cnt;
+} DPP_NPPU_MR_CFG_MR_COS2_EOP_IN_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos3_sop_in_cnt_t {
+	ZXIC_UINT32 mr_cos3_sop_in_cnt;
+} DPP_NPPU_MR_CFG_MR_COS3_SOP_IN_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos3_eop_in_cnt_t {
+	ZXIC_UINT32 mr_cos3_eop_in_cnt;
+} DPP_NPPU_MR_CFG_MR_COS3_EOP_IN_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos0_in_err_cnt_t {
+	ZXIC_UINT32 mr_cos0_in_err_cnt;
+} DPP_NPPU_MR_CFG_MR_COS0_IN_ERR_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos1_in_err_cnt_t {
+	ZXIC_UINT32 mr_cos1_in_err_cnt;
+} DPP_NPPU_MR_CFG_MR_COS1_IN_ERR_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos2_in_err_cnt_t {
+	ZXIC_UINT32 mr_cos2_in_err_cnt;
+} DPP_NPPU_MR_CFG_MR_COS2_IN_ERR_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos3_in_err_cnt_t {
+	ZXIC_UINT32 mr_cos3_in_err_cnt;
+} DPP_NPPU_MR_CFG_MR_COS3_IN_ERR_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos0_sop_out_cnt_t {
+	ZXIC_UINT32 mr_cos0_sop_out_cnt;
+} DPP_NPPU_MR_CFG_MR_COS0_SOP_OUT_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos0_eop_out_cnt_t {
+	ZXIC_UINT32 mr_cos0_eop_out_cnt;
+} DPP_NPPU_MR_CFG_MR_COS0_EOP_OUT_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos1_sop_out_cnt_t {
+	ZXIC_UINT32 mr_cos1_sop_out_cnt;
+} DPP_NPPU_MR_CFG_MR_COS1_SOP_OUT_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos1_eop_out_cnt_t {
+	ZXIC_UINT32 mr_cos1_eop_out_cnt;
+} DPP_NPPU_MR_CFG_MR_COS1_EOP_OUT_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos2_sop_out_cnt_t {
+	ZXIC_UINT32 mr_cos2_sop_out_cnt;
+} DPP_NPPU_MR_CFG_MR_COS2_SOP_OUT_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos2_eop_out_cnt_t {
+	ZXIC_UINT32 mr_cos2_eop_out_cnt;
+} DPP_NPPU_MR_CFG_MR_COS2_EOP_OUT_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos3_sop_out_cnt_t {
+	ZXIC_UINT32 mr_cos3_sop_out_cnt;
+} DPP_NPPU_MR_CFG_MR_COS3_SOP_OUT_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_cos3_eop_out_cnt_t {
+	ZXIC_UINT32 mr_cos3_eop_out_cnt;
+} DPP_NPPU_MR_CFG_MR_COS3_EOP_OUT_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_mlt_unvld_cnt_t {
+	ZXIC_UINT32 mr_mlt_unvld_cnt;
+} DPP_NPPU_MR_CFG_MR_MLT_UNVLD_CNT_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_sop_eop_match_cfg_t {
+	ZXIC_UINT32 mr_sop_eop_macth_en;
+	ZXIC_UINT32 mr_sop_eop_macth_dicard_th;
+} DPP_NPPU_MR_CFG_MR_SOP_EOP_MATCH_CFG_T;
+
+typedef struct dpp_nppu_mr_cfg_mr_mlt_unvld_mgid_t {
+	ZXIC_UINT32 mr_mlt_unvld_mgid;
+} DPP_NPPU_MR_CFG_MR_MLT_UNVLD_MGID_T;
+
+typedef struct dpp_nppu_pktrx_cfg_isch_fifo_th_1_t {
+	ZXIC_UINT32 cfg_sch_fifo7_fc_th;
+	ZXIC_UINT32 cfg_sch_fifo6_fc_th;
+	ZXIC_UINT32 cfg_sch_fifo5_fc_th;
+	ZXIC_UINT32 cfg_sch_fifo4_fc_th;
+} DPP_NPPU_PKTRX_CFG_ISCH_FIFO_TH_1_T;
+
+typedef struct dpp_nppu_pktrx_cfg_isch_fifo_th_2_t {
+	ZXIC_UINT32 cfg_sch_fifo3_drop_th;
+	ZXIC_UINT32 cfg_sch_fifo1_drop_th;
+	ZXIC_UINT32 cfg_sch_fifo0_drop_th;
+	ZXIC_UINT32 cfg_sch_fifo8_fc_th;
+} DPP_NPPU_PKTRX_CFG_ISCH_FIFO_TH_2_T;
+
+typedef struct dpp_nppu_pktrx_cfg_isch_fifo_th_3_t {
+	ZXIC_UINT32 cfg_sch_fifo6_drop_th;
+	ZXIC_UINT32 cfg_sch_fifo5_drop_th;
+	ZXIC_UINT32 cfg_sch_fifo4_drop_th;
+	ZXIC_UINT32 cfg_sch_fifo2_drop_th;
+} DPP_NPPU_PKTRX_CFG_ISCH_FIFO_TH_3_T;
+
+typedef struct dpp_nppu_pktrx_cfg_isch_fifo_th_4_t {
+	ZXIC_UINT32 cfg_sch_fifo9_fc_th;
+	ZXIC_UINT32 cfg_sch_fifo9_drop_th;
+	ZXIC_UINT32 cfg_sch_fifo8_drop_th;
+	ZXIC_UINT32 cfg_sch_fifo7_drop_th;
+} DPP_NPPU_PKTRX_CFG_ISCH_FIFO_TH_4_T;
+
+typedef struct dpp_nppu_pktrx_cfg_isch_cfg_0_t {
+	ZXIC_UINT32 cfg_sch_wrr1_weight1;
+} DPP_NPPU_PKTRX_CFG_ISCH_CFG_0_T;
+
+typedef struct dpp_nppu_pktrx_cfg_hdu_ex_tpid_0_t {
+	ZXIC_UINT32 cfg_type0;
+	ZXIC_UINT32 cfg_type1;
+} DPP_NPPU_PKTRX_CFG_HDU_EX_TPID_0_T;
+
+typedef struct dpp_nppu_pktrx_cfg_hdu_ex_tpid_1_t {
+	ZXIC_UINT32 cfg_type2;
+	ZXIC_UINT32 cfg_type3;
+} DPP_NPPU_PKTRX_CFG_HDU_EX_TPID_1_T;
+
+typedef struct dpp_nppu_pktrx_cfg_hdu_int_tpid_0_t {
+	ZXIC_UINT32 cfg_inner_type0;
+	ZXIC_UINT32 cfg_inner_type1;
+} DPP_NPPU_PKTRX_CFG_HDU_INT_TPID_0_T;
+
+typedef struct dpp_nppu_pktrx_cfg_hdu_int_tpid_1_t {
+	ZXIC_UINT32 cfg_inner_type2;
+	ZXIC_UINT32 cfg_inner_type3;
+} DPP_NPPU_PKTRX_CFG_HDU_INT_TPID_1_T;
+
+typedef struct dpp_nppu_pktrx_cfg_hdu_hdlc_0_t {
+	ZXIC_UINT32 hdlc_cfg0_type;
+	ZXIC_UINT32 hdlc_cfg1_type;
+} DPP_NPPU_PKTRX_CFG_HDU_HDLC_0_T;
+
+typedef struct dpp_nppu_pktrx_cfg_hdu_hdlc_1_t {
+	ZXIC_UINT32 hdlc_cfg2_type;
+	ZXIC_UINT32 hdlc_cfg3_type;
+} DPP_NPPU_PKTRX_CFG_HDU_HDLC_1_T;
+
+typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l3type_0_t {
+	ZXIC_UINT32 cfg_l3_type0;
+	ZXIC_UINT32 cfg_l3_type1;
+} DPP_NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_0_T;
+
+typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l3type_1_t {
+	ZXIC_UINT32 cfg_l3_type2;
+	ZXIC_UINT32 cfg_l3_type3;
+} DPP_NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_1_T;
+
+typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l3type_2_t {
+	ZXIC_UINT32 cfg_l3_type4;
+	ZXIC_UINT32 cfg_l3_type5;
+} DPP_NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_2_T;
+
+typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l3type_3_t {
+	ZXIC_UINT32 cfg_l3_type6;
+	ZXIC_UINT32 cfg_l3_type7;
+} DPP_NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_3_T;
+
+typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l4type_0_t {
+	ZXIC_UINT32 cfg_l4_type0;
+	ZXIC_UINT32 cfg_l4_type1;
+	ZXIC_UINT32 cfg_l4_type2;
+	ZXIC_UINT32 cfg_l4_type3;
+} DPP_NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_0_T;
+
+typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l4type_1_t {
+	ZXIC_UINT32 cfg_l4_type4;
+	ZXIC_UINT32 cfg_l4_type5;
+	ZXIC_UINT32 cfg_l4_type6;
+	ZXIC_UINT32 cfg_l4_type7;
+} DPP_NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_1_T;
+
+typedef struct dpp_nppu_pktrx_cfg_hdu_udf_l4type_2_t {
+	ZXIC_UINT32 cfg_l4_type8;
+	ZXIC_UINT32 cfg_l4_type9;
+	ZXIC_UINT32 cfg_l4_type10;
+} DPP_NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_2_T;
+
+typedef struct dpp_nppu_pktrx_cfg_slot_no_cfg_t {
+	ZXIC_UINT32 cfg_parser_slot_no;
+} DPP_NPPU_PKTRX_CFG_SLOT_NO_CFG_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_int_en_0_t {
+	ZXIC_UINT32 pktrx_int_en_31;
+	ZXIC_UINT32 pktrx_int_en_30;
+	ZXIC_UINT32 pktrx_int_en_29;
+	ZXIC_UINT32 pktrx_int_en_28;
+	ZXIC_UINT32 pktrx_int_en_27;
+	ZXIC_UINT32 pktrx_int_en_26;
+	ZXIC_UINT32 pktrx_int_en_25;
+	ZXIC_UINT32 pktrx_int_en_24;
+	ZXIC_UINT32 pktrx_int_en_23;
+	ZXIC_UINT32 pktrx_int_en_22;
+	ZXIC_UINT32 pktrx_int_en_21;
+	ZXIC_UINT32 pktrx_int_en_20;
+	ZXIC_UINT32 pktrx_int_en_19;
+	ZXIC_UINT32 pktrx_int_en_18;
+	ZXIC_UINT32 pktrx_int_en_17;
+	ZXIC_UINT32 pktrx_int_en_16;
+	ZXIC_UINT32 pktrx_int_en_15;
+	ZXIC_UINT32 pktrx_int_en_14;
+	ZXIC_UINT32 pktrx_int_en_13;
+	ZXIC_UINT32 pktrx_int_en_12;
+	ZXIC_UINT32 pktrx_int_en_11;
+	ZXIC_UINT32 pktrx_int_en_10;
+	ZXIC_UINT32 pktrx_int_en_9;
+	ZXIC_UINT32 pktrx_int_en_8;
+	ZXIC_UINT32 pktrx_int_en_7;
+	ZXIC_UINT32 pktrx_int_en_6;
+	ZXIC_UINT32 pktrx_int_en_5;
+	ZXIC_UINT32 pktrx_int_en_4;
+	ZXIC_UINT32 pktrx_int_en_3;
+	ZXIC_UINT32 pktrx_int_en_2;
+	ZXIC_UINT32 pktrx_int_en_1;
+	ZXIC_UINT32 pktrx_int_en_0;
+} DPP_NPPU_PKTRX_CFG_PKTRX_INT_EN_0_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_int_en_1_t {
+	ZXIC_UINT32 pktrx_int_en_35;
+	ZXIC_UINT32 pktrx_int_en_34;
+	ZXIC_UINT32 pktrx_int_en_33;
+	ZXIC_UINT32 pktrx_int_en_32;
+} DPP_NPPU_PKTRX_CFG_PKTRX_INT_EN_1_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_int_mask_0_t {
+	ZXIC_UINT32 pktrx_int_mask_31;
+	ZXIC_UINT32 pktrx_int_mask_30;
+	ZXIC_UINT32 pktrx_int_mask_29;
+	ZXIC_UINT32 pktrx_int_mask_28;
+	ZXIC_UINT32 pktrx_int_mask_27;
+	ZXIC_UINT32 pktrx_int_mask_26;
+	ZXIC_UINT32 pktrx_int_mask_25;
+	ZXIC_UINT32 pktrx_int_mask_24;
+	ZXIC_UINT32 pktrx_int_mask_23;
+	ZXIC_UINT32 pktrx_int_mask_22;
+	ZXIC_UINT32 pktrx_int_mask_21;
+	ZXIC_UINT32 pktrx_int_mask_20;
+	ZXIC_UINT32 pktrx_int_mask_19;
+	ZXIC_UINT32 pktrx_int_mask_18;
+	ZXIC_UINT32 pktrx_int_mask_17;
+	ZXIC_UINT32 pktrx_int_mask_16;
+	ZXIC_UINT32 pktrx_int_mask_15;
+	ZXIC_UINT32 pktrx_int_mask_14;
+	ZXIC_UINT32 pktrx_int_mask_13;
+	ZXIC_UINT32 pktrx_int_mask_12;
+	ZXIC_UINT32 pktrx_int_mask_11;
+	ZXIC_UINT32 pktrx_int_mask_10;
+	ZXIC_UINT32 pktrx_int_mask_9;
+	ZXIC_UINT32 pktrx_int_mask_8;
+	ZXIC_UINT32 pktrx_int_mask_7;
+	ZXIC_UINT32 pktrx_int_mask_6;
+	ZXIC_UINT32 pktrx_int_mask_5;
+	ZXIC_UINT32 pktrx_int_mask_4;
+	ZXIC_UINT32 pktrx_int_mask_3;
+	ZXIC_UINT32 pktrx_int_mask_2;
+	ZXIC_UINT32 pktrx_int_mask_1;
+	ZXIC_UINT32 pktrx_int_mask_0;
+} DPP_NPPU_PKTRX_CFG_PKTRX_INT_MASK_0_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_int_mask_1_t {
+	ZXIC_UINT32 pktrx_int_mask_35;
+	ZXIC_UINT32 pktrx_int_mask_34;
+	ZXIC_UINT32 pktrx_int_mask_33;
+	ZXIC_UINT32 pktrx_int_mask_32;
+} DPP_NPPU_PKTRX_CFG_PKTRX_INT_MASK_1_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_int_status_t {
+	ZXIC_UINT32 int_status;
+} DPP_NPPU_PKTRX_CFG_PKTRX_INT_STATUS_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_port_rdy0_t {
+	ZXIC_UINT32 pktrx_trpgrx_r1_rdy;
+	ZXIC_UINT32 pktrx_trpgrx_r2_rdy;
+} DPP_NPPU_PKTRX_CFG_PKTRX_PORT_RDY0_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy0_t {
+	ZXIC_UINT32 pktrx_trpgrx_r1_pfc_rdy_0;
+} DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY0_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy1_t {
+	ZXIC_UINT32 pktrx_trpgrx_r1_pfc_rdy_1;
+} DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY1_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy2_t {
+	ZXIC_UINT32 pktrx_trpgrx_r1_pfc_rdy_2;
+} DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY2_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy3_t {
+	ZXIC_UINT32 pktrx_trpgrx_r2_pfc_rdy_3;
+} DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY3_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy4_t {
+	ZXIC_UINT32 pktrx_trpgrx_r2_pfc_rdy_4;
+} DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY4_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy5_t {
+	ZXIC_UINT32 pktrx_trpgrx_r2_pfc_rdy_5;
+} DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY5_T;
+
+typedef struct dpp_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy6_t {
+	ZXIC_UINT32 pktrx_trpgrx_r2_pfc_rdy_6;
+} DPP_NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY6_T;
+
+typedef struct dpp_nppu_pktrx_cfg_cfg_port_l2_offset_mode_t {
+	ZXIC_UINT32 cfg_port_l2_offset_mode;
+} DPP_NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_T;
+
+typedef struct dpp_nppu_idma_cfg_int_ram_en_t {
+	ZXIC_UINT32 phy_sts_parity_err;
+	ZXIC_UINT32 ptr_buf_parity_err;
+} DPP_NPPU_IDMA_CFG_INT_RAM_EN_T;
+
+typedef struct dpp_nppu_idma_cfg_int_ram_mask_t {
+	ZXIC_UINT32 phy_sts_parity_err;
+	ZXIC_UINT32 ptr_buf_parity_err;
+} DPP_NPPU_IDMA_CFG_INT_RAM_MASK_T;
+
+typedef struct dpp_nppu_idma_cfg_int_ram_status_t {
+	ZXIC_UINT32 phy_sts_parity_err;
+	ZXIC_UINT32 ptr_buf_parity_err;
+} DPP_NPPU_IDMA_CFG_INT_RAM_STATUS_T;
+
+typedef struct dpp_nppu_idma_cfg_subsys_int_mask_flag_t {
+	ZXIC_UINT32 subsys_int_mask_flag;
+} DPP_NPPU_IDMA_CFG_SUBSYS_INT_MASK_FLAG_T;
+
+typedef struct dpp_nppu_idma_cfg_subsys_int_unmask_flag_t {
+	ZXIC_UINT32 subsys_int_unmask_flag;
+} DPP_NPPU_IDMA_CFG_SUBSYS_INT_UNMASK_FLAG_T;
+
+typedef struct dpp_nppu_idma_cfg_debug_cnt_rdclr_mode_t {
+	ZXIC_UINT32 debug_cnt_rdclr_mode;
+} DPP_NPPU_IDMA_CFG_DEBUG_CNT_RDCLR_MODE_T;
+
+typedef struct dpp_nppu_pbu_cfg_int_ram_en0_t {
+	ZXIC_UINT32 int_ram_en_31;
+	ZXIC_UINT32 int_ram_en_30;
+	ZXIC_UINT32 int_ram_en_29;
+	ZXIC_UINT32 int_ram_en_28;
+	ZXIC_UINT32 int_ram_en_27;
+	ZXIC_UINT32 int_ram_en_26;
+	ZXIC_UINT32 int_ram_en_25;
+	ZXIC_UINT32 int_ram_en_24;
+	ZXIC_UINT32 int_ram_en_23;
+	ZXIC_UINT32 int_ram_en_22;
+	ZXIC_UINT32 int_ram_en_21;
+	ZXIC_UINT32 int_ram_en_20;
+	ZXIC_UINT32 int_ram_en_19;
+	ZXIC_UINT32 int_ram_en_18;
+	ZXIC_UINT32 int_ram_en_17;
+	ZXIC_UINT32 int_ram_en_16;
+	ZXIC_UINT32 int_ram_en_15;
+	ZXIC_UINT32 int_ram_en_14;
+	ZXIC_UINT32 int_ram_en_13;
+	ZXIC_UINT32 int_ram_en_12;
+	ZXIC_UINT32 int_ram_en_11;
+	ZXIC_UINT32 int_ram_en_10;
+	ZXIC_UINT32 int_ram_en_9;
+	ZXIC_UINT32 int_ram_en_8;
+	ZXIC_UINT32 int_ram_en_7;
+	ZXIC_UINT32 int_ram_en_6;
+	ZXIC_UINT32 int_ram_en_5;
+	ZXIC_UINT32 int_ram_en_4;
+	ZXIC_UINT32 int_ram_en_3;
+	ZXIC_UINT32 int_ram_en_2;
+	ZXIC_UINT32 int_ram_en_1;
+	ZXIC_UINT32 int_ram_en_0;
+} DPP_NPPU_PBU_CFG_INT_RAM_EN0_T;
+
+typedef struct dpp_nppu_pbu_cfg_int_ram_mask0_t {
+	ZXIC_UINT32 int_ram_mask_31;
+	ZXIC_UINT32 int_ram_mask_30;
+	ZXIC_UINT32 int_ram_mask_29;
+	ZXIC_UINT32 int_ram_mask_28;
+	ZXIC_UINT32 int_ram_mask_27;
+	ZXIC_UINT32 int_ram_mask_26;
+	ZXIC_UINT32 int_ram_mask_25;
+	ZXIC_UINT32 int_ram_mask_24;
+	ZXIC_UINT32 int_ram_mask_23;
+	ZXIC_UINT32 int_ram_mask_22;
+	ZXIC_UINT32 int_ram_mask_21;
+	ZXIC_UINT32 int_ram_mask_20;
+	ZXIC_UINT32 int_ram_mask_19;
+	ZXIC_UINT32 int_ram_mask_18;
+	ZXIC_UINT32 int_ram_mask_17;
+	ZXIC_UINT32 int_ram_mask_16;
+	ZXIC_UINT32 int_ram_mask_15;
+	ZXIC_UINT32 int_ram_mask_14;
+	ZXIC_UINT32 int_ram_mask_13;
+	ZXIC_UINT32 int_ram_mask_12;
+	ZXIC_UINT32 int_ram_mask_11;
+	ZXIC_UINT32 int_ram_mask_10;
+	ZXIC_UINT32 int_ram_mask_9;
+	ZXIC_UINT32 int_ram_mask_8;
+	ZXIC_UINT32 int_ram_mask_7;
+	ZXIC_UINT32 int_ram_mask_6;
+	ZXIC_UINT32 int_ram_mask_5;
+	ZXIC_UINT32 int_ram_mask_4;
+	ZXIC_UINT32 int_ram_mask_3;
+	ZXIC_UINT32 int_ram_mask_2;
+	ZXIC_UINT32 int_ram_mask_1;
+	ZXIC_UINT32 int_ram_mask_0;
+} DPP_NPPU_PBU_CFG_INT_RAM_MASK0_T;
+
+typedef struct dpp_nppu_pbu_cfg_int_ram_status0_t {
+	ZXIC_UINT32 int_ram_status_31;
+	ZXIC_UINT32 int_ram_status_30;
+	ZXIC_UINT32 int_ram_status_29;
+	ZXIC_UINT32 int_ram_status_28;
+	ZXIC_UINT32 int_ram_status_27;
+	ZXIC_UINT32 int_ram_status_26;
+	ZXIC_UINT32 int_ram_status_25;
+	ZXIC_UINT32 int_ram_status_24;
+	ZXIC_UINT32 int_ram_status_23;
+	ZXIC_UINT32 int_ram_status_22;
+	ZXIC_UINT32 int_ram_status_21;
+	ZXIC_UINT32 int_ram_status_20;
+	ZXIC_UINT32 int_ram_status_19;
+	ZXIC_UINT32 int_ram_status_18;
+	ZXIC_UINT32 int_ram_status_17;
+	ZXIC_UINT32 int_ram_status_16;
+	ZXIC_UINT32 int_ram_status_15;
+	ZXIC_UINT32 int_ram_status_14;
+	ZXIC_UINT32 int_ram_status_13;
+	ZXIC_UINT32 int_ram_status_12;
+	ZXIC_UINT32 int_ram_status_11;
+	ZXIC_UINT32 int_ram_status_10;
+	ZXIC_UINT32 int_ram_status_9;
+	ZXIC_UINT32 int_ram_status_8;
+	ZXIC_UINT32 int_ram_status_7;
+	ZXIC_UINT32 int_ram_status_6;
+	ZXIC_UINT32 int_ram_status_5;
+	ZXIC_UINT32 int_ram_status_4;
+	ZXIC_UINT32 int_ram_status_3;
+	ZXIC_UINT32 int_ram_status_2;
+	ZXIC_UINT32 int_ram_status_1;
+	ZXIC_UINT32 int_ram_status_0;
+} DPP_NPPU_PBU_CFG_INT_RAM_STATUS0_T;
+
+typedef struct dpp_nppu_pbu_cfg_int_fifo_en0_t {
+	ZXIC_UINT32 int_fifo_en_31;
+	ZXIC_UINT32 int_fifo_en_30;
+	ZXIC_UINT32 int_fifo_en_29;
+	ZXIC_UINT32 int_fifo_en_28;
+	ZXIC_UINT32 int_fifo_en_27;
+	ZXIC_UINT32 int_fifo_en_26;
+	ZXIC_UINT32 int_fifo_en_25;
+	ZXIC_UINT32 int_fifo_en_24;
+	ZXIC_UINT32 int_fifo_en_23;
+	ZXIC_UINT32 int_fifo_en_22;
+	ZXIC_UINT32 int_fifo_en_21;
+	ZXIC_UINT32 int_fifo_en_20;
+	ZXIC_UINT32 int_fifo_en_19;
+	ZXIC_UINT32 int_fifo_en_18;
+	ZXIC_UINT32 int_fifo_en_17;
+	ZXIC_UINT32 int_fifo_en_16;
+	ZXIC_UINT32 int_fifo_en_15;
+	ZXIC_UINT32 int_fifo_en_14;
+	ZXIC_UINT32 int_fifo_en_13;
+	ZXIC_UINT32 int_fifo_en_12;
+	ZXIC_UINT32 int_fifo_en_11;
+	ZXIC_UINT32 int_fifo_en_10;
+	ZXIC_UINT32 int_fifo_en_9;
+	ZXIC_UINT32 int_fifo_en_8;
+	ZXIC_UINT32 int_fifo_en_7;
+	ZXIC_UINT32 int_fifo_en_6;
+	ZXIC_UINT32 int_fifo_en_5;
+	ZXIC_UINT32 int_fifo_en_4;
+	ZXIC_UINT32 int_fifo_en_3;
+	ZXIC_UINT32 int_fifo_en_2;
+	ZXIC_UINT32 int_fifo_en_1;
+	ZXIC_UINT32 int_fifo_en_0;
+} DPP_NPPU_PBU_CFG_INT_FIFO_EN0_T;
+
+typedef struct dpp_nppu_pbu_cfg_int_fifo_en1_t {
+	ZXIC_UINT32 int_fifo_en_35;
+	ZXIC_UINT32 int_fifo_en_34;
+	ZXIC_UINT32 int_fifo_en_33;
+	ZXIC_UINT32 int_fifo_en_32;
+} DPP_NPPU_PBU_CFG_INT_FIFO_EN1_T;
+
+typedef struct dpp_nppu_pbu_cfg_int_fifo_mask0_t {
+	ZXIC_UINT32 int_fifo_mask_31;
+	ZXIC_UINT32 int_fifo_mask_30;
+	ZXIC_UINT32 int_fifo_mask_29;
+	ZXIC_UINT32 int_fifo_mask_28;
+	ZXIC_UINT32 int_fifo_mask_27;
+	ZXIC_UINT32 int_fifo_mask_26;
+	ZXIC_UINT32 int_fifo_mask_25;
+	ZXIC_UINT32 int_fifo_mask_24;
+	ZXIC_UINT32 int_fifo_mask_23;
+	ZXIC_UINT32 int_fifo_mask_22;
+	ZXIC_UINT32 int_fifo_mask_21;
+	ZXIC_UINT32 int_fifo_mask_20;
+	ZXIC_UINT32 int_fifo_mask_19;
+	ZXIC_UINT32 int_fifo_mask_18;
+	ZXIC_UINT32 int_fifo_mask_17;
+	ZXIC_UINT32 int_fifo_mask_16;
+	ZXIC_UINT32 int_fifo_mask_15;
+	ZXIC_UINT32 int_fifo_mask_14;
+	ZXIC_UINT32 int_fifo_mask_13;
+	ZXIC_UINT32 int_fifo_mask_12;
+	ZXIC_UINT32 int_fifo_mask_11;
+	ZXIC_UINT32 int_fifo_mask_10;
+	ZXIC_UINT32 int_fifo_mask_9;
+	ZXIC_UINT32 int_fifo_mask_8;
+	ZXIC_UINT32 int_fifo_mask_7;
+	ZXIC_UINT32 int_fifo_mask_6;
+	ZXIC_UINT32 int_fifo_mask_5;
+	ZXIC_UINT32 int_fifo_mask_4;
+	ZXIC_UINT32 int_fifo_mask_3;
+	ZXIC_UINT32 int_fifo_mask_2;
+	ZXIC_UINT32 int_fifo_mask_1;
+	ZXIC_UINT32 int_fifo_mask_0;
+} DPP_NPPU_PBU_CFG_INT_FIFO_MASK0_T;
+
+typedef struct dpp_nppu_pbu_cfg_int_fifo_mask1_t {
+	ZXIC_UINT32 int_fifo_mask_35;
+	ZXIC_UINT32 int_fifo_mask_34;
+	ZXIC_UINT32 int_fifo_mask_33;
+	ZXIC_UINT32 int_fifo_mask_32;
+} DPP_NPPU_PBU_CFG_INT_FIFO_MASK1_T;
+
+typedef struct dpp_nppu_pbu_cfg_int_fifo_status0_t {
+	ZXIC_UINT32 int_fifo_status_31;
+	ZXIC_UINT32 int_fifo_status_30;
+	ZXIC_UINT32 int_fifo_status_29;
+	ZXIC_UINT32 int_fifo_status_28;
+	ZXIC_UINT32 int_fifo_status_27;
+	ZXIC_UINT32 int_fifo_status_26;
+	ZXIC_UINT32 int_fifo_status_25;
+	ZXIC_UINT32 int_fifo_status_24;
+	ZXIC_UINT32 int_fifo_status_23;
+	ZXIC_UINT32 int_fifo_status_22;
+	ZXIC_UINT32 int_fifo_status_21;
+	ZXIC_UINT32 int_fifo_status_20;
+	ZXIC_UINT32 int_fifo_status_19;
+	ZXIC_UINT32 int_fifo_status_18;
+	ZXIC_UINT32 int_fifo_status_17;
+	ZXIC_UINT32 int_fifo_status_16;
+	ZXIC_UINT32 int_fifo_status_15;
+	ZXIC_UINT32 int_fifo_status_14;
+	ZXIC_UINT32 int_fifo_status_13;
+	ZXIC_UINT32 int_fifo_status_12;
+	ZXIC_UINT32 int_fifo_status_11;
+	ZXIC_UINT32 int_fifo_status_10;
+	ZXIC_UINT32 int_fifo_status_9;
+	ZXIC_UINT32 int_fifo_status_8;
+	ZXIC_UINT32 int_fifo_status_7;
+	ZXIC_UINT32 int_fifo_status_6;
+	ZXIC_UINT32 int_fifo_status_5;
+	ZXIC_UINT32 int_fifo_status_4;
+	ZXIC_UINT32 int_fifo_status_3;
+	ZXIC_UINT32 int_fifo_status_2;
+	ZXIC_UINT32 int_fifo_status_1;
+	ZXIC_UINT32 int_fifo_status_0;
+} DPP_NPPU_PBU_CFG_INT_FIFO_STATUS0_T;
+
+typedef struct dpp_nppu_pbu_cfg_int_fifo_status1_t {
+	ZXIC_UINT32 int_fifo_status_35;
+	ZXIC_UINT32 int_fifo_status_34;
+	ZXIC_UINT32 int_fifo_status_33;
+	ZXIC_UINT32 int_fifo_status_32;
+} DPP_NPPU_PBU_CFG_INT_FIFO_STATUS1_T;
+
+typedef struct dpp_nppu_pbu_cfg_subsys_int_mask_flag_t {
+	ZXIC_UINT32 subsys_int_mask_flag;
+} DPP_NPPU_PBU_CFG_SUBSYS_INT_MASK_FLAG_T;
+
+typedef struct dpp_nppu_pbu_cfg_subsys_int_unmask_flag_t {
+	ZXIC_UINT32 subsys_int_unmask_flag;
+} DPP_NPPU_PBU_CFG_SUBSYS_INT_UNMASK_FLAG_T;
+
+typedef struct dpp_nppu_pbu_cfg_sa_ip_en_t {
+	ZXIC_UINT32 sa_ip_en;
+} DPP_NPPU_PBU_CFG_SA_IP_EN_T;
+
+typedef struct dpp_nppu_pbu_cfg_debug_cnt_rdclr_mode_t {
+	ZXIC_UINT32 debug_cnt_rdclr_mode;
+} DPP_NPPU_PBU_CFG_DEBUG_CNT_RDCLR_MODE_T;
+
+typedef struct dpp_nppu_pbu_cfg_fptr_fifo_aful_assert_cfg_t {
+	ZXIC_UINT32 fptr_fifo_aful_assert_cfg;
+} DPP_NPPU_PBU_CFG_FPTR_FIFO_AFUL_ASSERT_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_fptr_fifo_aful_negate_cfg_t {
+	ZXIC_UINT32 fptr_fifo_aful_negate_cfg;
+} DPP_NPPU_PBU_CFG_FPTR_FIFO_AFUL_NEGATE_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_pf_fifo_aful_assert_cfg_t {
+	ZXIC_UINT32 pf_fifo_aful_assert_cfg;
+} DPP_NPPU_PBU_CFG_PF_FIFO_AFUL_ASSERT_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_pf_fifo_aful_negate_cfg_t {
+	ZXIC_UINT32 pf_fifo_aful_negate_cfg;
+} DPP_NPPU_PBU_CFG_PF_FIFO_AFUL_NEGATE_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_pf_fifo_aept_assert_cfg_t {
+	ZXIC_UINT32 pf_fifo_aept_assert_cfg;
+} DPP_NPPU_PBU_CFG_PF_FIFO_AEPT_ASSERT_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_pf_fifo_aept_negate_cfg_t {
+	ZXIC_UINT32 pf_fifo_aept_negate_cfg;
+} DPP_NPPU_PBU_CFG_PF_FIFO_AEPT_NEGATE_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_wb_aful_assert_cfg_t {
+	ZXIC_UINT32 wb_aful_assert_cfg;
+} DPP_NPPU_PBU_CFG_WB_AFUL_ASSERT_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_wb_aful_negate_cfg_t {
+	ZXIC_UINT32 wb_aful_negate_cfg;
+} DPP_NPPU_PBU_CFG_WB_AFUL_NEGATE_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_se_key_aful_assert_cfg_t {
+	ZXIC_UINT32 se_key_aful_assert_cfg;
+} DPP_NPPU_PBU_CFG_SE_KEY_AFUL_ASSERT_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_ifbrd_se_aful_assert_cfg_t {
+	ZXIC_UINT32 ifbrd_se_aful_assert_cfg;
+} DPP_NPPU_PBU_CFG_IFBRD_SE_AFUL_ASSERT_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_ifbrd_se_aful_negate_cfg_t {
+	ZXIC_UINT32 ifbrd_se_aful_negate_cfg;
+} DPP_NPPU_PBU_CFG_IFBRD_SE_AFUL_NEGATE_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_ifbrd_odma_aful_assert_cfg_t {
+	ZXIC_UINT32 ifbrd_odma_aful_assert_cfg;
+} DPP_NPPU_PBU_CFG_IFBRD_ODMA_AFUL_ASSERT_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_ifbrd_odma_aful_negate_cfg_t {
+	ZXIC_UINT32 ifbrd_odma_aful_negate_cfg;
+} DPP_NPPU_PBU_CFG_IFBRD_ODMA_AFUL_NEGATE_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_ifbrd_ppu_aful_assert_cfg_t {
+	ZXIC_UINT32 ifbrd_ppu_aful_assert_cfg;
+} DPP_NPPU_PBU_CFG_IFBRD_PPU_AFUL_ASSERT_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_ifbrd_ppu_aful_negate_cfg_t {
+	ZXIC_UINT32 ifbrd_ppu_aful_negate_cfg;
+} DPP_NPPU_PBU_CFG_IFBRD_PPU_AFUL_NEGATE_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_mc_logic_aful_assert_cfg_t {
+	ZXIC_UINT32 mc_logic_aful_assert_cfg;
+} DPP_NPPU_PBU_CFG_MC_LOGIC_AFUL_ASSERT_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_mc_logic_aful_negate_cfg_t {
+	ZXIC_UINT32 mc_logic_aful_negate_cfg;
+} DPP_NPPU_PBU_CFG_MC_LOGIC_AFUL_NEGATE_CFG_T;
+
+typedef struct dpp_nppu_pbu_cfg_mc_logic_diff_t {
+	ZXIC_UINT32 mc_logic_diff;
+} DPP_NPPU_PBU_CFG_MC_LOGIC_DIFF_T;
+
+typedef struct dpp_nppu_pbu_cfg_cfg_peak_port_cnt_clr_t {
+	ZXIC_UINT32 cfg_peak_port_cnt_clr;
+} DPP_NPPU_PBU_CFG_CFG_PEAK_PORT_CNT_CLR_T;
+
+typedef struct dpp_nppu_pbu_cfg_all_ftm_crdt_th_t {
+	ZXIC_UINT32 ftm_crdt_port_cng_th;
+	ZXIC_UINT32 ftm_crdt_port_th;
+} DPP_NPPU_PBU_CFG_ALL_FTM_CRDT_TH_T;
+
+typedef struct dpp_nppu_pbu_cfg_all_ftm_link_th_01_t {
+	ZXIC_UINT32 total_congest_th1;
+	ZXIC_UINT32 total_congest_th0;
+} DPP_NPPU_PBU_CFG_ALL_FTM_LINK_TH_01_T;
+
+typedef struct dpp_nppu_pbu_cfg_all_ftm_link_th_23_t {
+	ZXIC_UINT32 total_congest_th3;
+	ZXIC_UINT32 total_congest_th2;
+} DPP_NPPU_PBU_CFG_ALL_FTM_LINK_TH_23_T;
+
+typedef struct dpp_nppu_pbu_cfg_all_ftm_link_th_45_t {
+	ZXIC_UINT32 total_congest_th5;
+	ZXIC_UINT32 total_congest_th4;
+} DPP_NPPU_PBU_CFG_ALL_FTM_LINK_TH_45_T;
+
+typedef struct dpp_nppu_pbu_cfg_all_ftm_link_th_6_t {
+	ZXIC_UINT32 total_congest_th6;
+} DPP_NPPU_PBU_CFG_ALL_FTM_LINK_TH_6_T;
+
+typedef struct dpp_nppu_pbu_cfg_all_ftm_total_congest_th_t {
+	ZXIC_UINT32 all_ftm_total_congest_th;
+} DPP_NPPU_PBU_CFG_ALL_FTM_TOTAL_CONGEST_TH_T;
+
+typedef struct dpp_nppu_pbu_cfg_cfg_crdt_mode_t {
+	ZXIC_UINT32 cfg_crdt_mode;
+} DPP_NPPU_PBU_CFG_CFG_CRDT_MODE_T;
+
+typedef struct dpp_nppu_pbu_cfg_cfg_pfc_rdy_high_time_t {
+	ZXIC_UINT32 cfg_pfc_rdy_high_time;
+} DPP_NPPU_PBU_CFG_CFG_PFC_RDY_HIGH_TIME_T;
+
+typedef struct dpp_nppu_pbu_cfg_cfg_pfc_rdy_low_time_t {
+	ZXIC_UINT32 cfg_pfc_rdy_low_time;
+} DPP_NPPU_PBU_CFG_CFG_PFC_RDY_LOW_TIME_T;
+
+typedef struct dpp_nppu_pbu_stat_pbu_fc_rdy_t {
+	ZXIC_UINT32 pbu_oam_send_fc_rdy;
+	ZXIC_UINT32 pbu_odma_fc_rdy;
+	ZXIC_UINT32 pbu_tm_fc_rdy;
+	ZXIC_UINT32 pbu_idma_cos_rdy;
+} DPP_NPPU_PBU_STAT_PBU_FC_RDY_T;
+
+typedef struct dpp_nppu_pbu_stat_pbu_lif_group0_rdy0_t {
+	ZXIC_UINT32 pbu_ipg1_rdy;
+	ZXIC_UINT32 pbu_ipg0_rdy;
+	ZXIC_UINT32 pbu_trpgrx_xge_rdy;
+	ZXIC_UINT32 pbu_trpgrx_cge1_rdy;
+	ZXIC_UINT32 pbu_trpgrx_cge0_rdy;
+} DPP_NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY0_T;
+
+typedef struct dpp_nppu_pbu_stat_pbu_lif_group0_rdy1_t {
+	ZXIC_UINT32 pbu_lif_group0_rdy1;
+} DPP_NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY1_T;
+
+typedef struct dpp_nppu_pbu_stat_pbu_lif_group1_rdy_t {
+	ZXIC_UINT32 pbu_lif_group1_rdy1;
+} DPP_NPPU_PBU_STAT_PBU_LIF_GROUP1_RDY_T;
+
+typedef struct dpp_nppu_pbu_stat_pbu_lif_group0_pfc_rdy_t {
+	ZXIC_UINT32 pbu_lif_group0_pfc_rdy;
+} DPP_NPPU_PBU_STAT_PBU_LIF_GROUP0_PFC_RDY_T;
+
+typedef struct dpp_nppu_pbu_stat_pbu_lif_group1_pfc_rdy_t {
+	ZXIC_UINT32 pbu_lif_group1_pfc_rdy;
+} DPP_NPPU_PBU_STAT_PBU_LIF_GROUP1_PFC_RDY_T;
+
+typedef struct dpp_nppu_pbu_stat_pbu_sa_port_rdy_0_31_t {
+	ZXIC_UINT32 pbu_sa_port_rdy_0_31;
+} DPP_NPPU_PBU_STAT_PBU_SA_PORT_RDY_0_31_T;
+
+typedef struct dpp_nppu_pbu_stat_pbu_sa_port_rdy_32_50_t {
+	ZXIC_UINT32 pbu_sa_port_rdy_32_50;
+} DPP_NPPU_PBU_STAT_PBU_SA_PORT_RDY_32_50_T;
+
+typedef struct dpp_nppu_pbu_stat_pbu_pktrx_mr_pfc_rdy_t {
+	ZXIC_UINT32 pbu_pktrx_mr_pfc_rdy;
+} DPP_NPPU_PBU_STAT_PBU_PKTRX_MR_PFC_RDY_T;
+
+typedef struct dpp_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_0_31_t {
+	ZXIC_UINT32 pbu_ftm_crdt_port_rdy_0_31;
+} DPP_NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_0_31_T;
+
+typedef struct dpp_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_32_47_t {
+	ZXIC_UINT32 pbu_ftm_crdt_port_rdy_32_47;
+} DPP_NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_32_47_T;
+
+typedef struct dpp_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_0_31_t {
+	ZXIC_UINT32 pbu_ftm_crdt_port_cng_rdy_0_31;
+} DPP_NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_0_31_T;
+
+typedef struct dpp_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_32_47_t {
+	ZXIC_UINT32 pbu_ftm_crdt_port_cng_rdy_32_47;
+} DPP_NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_32_47_T;
+
+typedef struct dpp_nppu_pbu_stat_pbu_ftm_crdt_sys_info_t {
+	ZXIC_UINT32 pbu_ftm_crdt_sys_info;
+} DPP_NPPU_PBU_STAT_PBU_FTM_CRDT_SYS_INFO_T;
+
+typedef struct dpp_nppu_isu_cfg_weight_normal_mc_t {
+	ZXIC_UINT32 weight_normal_mc;
+} DPP_NPPU_ISU_CFG_WEIGHT_NORMAL_MC_T;
+
+typedef struct dpp_nppu_isu_cfg_weight_sa_mc_t {
+	ZXIC_UINT32 weight_sa_mc;
+} DPP_NPPU_ISU_CFG_WEIGHT_SA_MC_T;
+
+typedef struct dpp_nppu_isu_cfg_weight_etm_t {
+	ZXIC_UINT32 weight_etm;
+} DPP_NPPU_ISU_CFG_WEIGHT_ETM_T;
+
+typedef struct dpp_nppu_isu_cfg_weight_lp_mc_t {
+	ZXIC_UINT32 weight_lp_mc;
+} DPP_NPPU_ISU_CFG_WEIGHT_LP_MC_T;
+
+typedef struct dpp_nppu_isu_cfg_weight_oam_t {
+	ZXIC_UINT32 weight_oam;
+} DPP_NPPU_ISU_CFG_WEIGHT_OAM_T;
+
+typedef struct dpp_nppu_isu_cfg_weight_lif_ctrl1_t {
+	ZXIC_UINT32 weight_lif_ctrl1;
+} DPP_NPPU_ISU_CFG_WEIGHT_LIF_CTRL1_T;
+
+typedef struct dpp_nppu_isu_cfg_weight_lif_ctrl2_t {
+	ZXIC_UINT32 weight_lif_ctrl2;
+} DPP_NPPU_ISU_CFG_WEIGHT_LIF_CTRL2_T;
+
+typedef struct dpp_nppu_isu_cfg_ecc_bypass_read_t {
+	ZXIC_UINT32 eccbypass;
+} DPP_NPPU_ISU_CFG_ECC_BYPASS_READ_T;
+
+typedef struct dpp_nppu_isu_cfg_isu_int_mask_t {
+	ZXIC_UINT32 isu_int_mask;
+} DPP_NPPU_ISU_CFG_ISU_INT_MASK_T;
+
+typedef struct dpp_nppu_isu_cfg_cfg_crdt_cycle_t {
+	ZXIC_UINT32 cfg_cycle;
+} DPP_NPPU_ISU_CFG_CFG_CRDT_CYCLE_T;
+
+typedef struct dpp_nppu_isu_cfg_cfg_crdt_value_t {
+	ZXIC_UINT32 cfg_value;
+} DPP_NPPU_ISU_CFG_CFG_CRDT_VALUE_T;
+
+typedef struct dpp_nppu_isu_cfg_isu_int_en_t {
+	ZXIC_UINT32 isu_int_en;
+} DPP_NPPU_ISU_CFG_ISU_INT_EN_T;
+
+typedef struct dpp_nppu_isu_cfg_isu_ppu_fifo_fc_t {
+	ZXIC_UINT32 isu_ppu_fifo_fc;
+} DPP_NPPU_ISU_CFG_ISU_PPU_FIFO_FC_T;
+
+typedef struct dpp_nppu_isu_cfg_isu_int_status_t {
+	ZXIC_UINT32 isu_int_status_26;
+	ZXIC_UINT32 isu_int_status_25;
+	ZXIC_UINT32 isu_int_status_24;
+	ZXIC_UINT32 isu_int_status_23;
+	ZXIC_UINT32 isu_int_status_22;
+	ZXIC_UINT32 isu_int_status_21;
+	ZXIC_UINT32 isu_int_status_20;
+	ZXIC_UINT32 isu_int_status_19;
+	ZXIC_UINT32 isu_int_status_18;
+	ZXIC_UINT32 isu_int_status_17;
+	ZXIC_UINT32 isu_int_status_16;
+	ZXIC_UINT32 isu_int_status_15;
+	ZXIC_UINT32 isu_int_status_14;
+	ZXIC_UINT32 isu_int_status_13;
+	ZXIC_UINT32 isu_int_status_12;
+	ZXIC_UINT32 isu_int_status_11;
+	ZXIC_UINT32 isu_int_status_10;
+	ZXIC_UINT32 isu_int_status_9;
+	ZXIC_UINT32 isu_int_status_8;
+	ZXIC_UINT32 isu_int_status_7;
+	ZXIC_UINT32 isu_int_status_6;
+	ZXIC_UINT32 isu_int_status_5;
+	ZXIC_UINT32 isu_int_status_4;
+	ZXIC_UINT32 isu_int_status_3;
+	ZXIC_UINT32 isu_int_status_2;
+	ZXIC_UINT32 isu_int_status_1;
+	ZXIC_UINT32 isu_int_status_0;
+} DPP_NPPU_ISU_CFG_ISU_INT_STATUS_T;
+
+typedef struct dpp_nppu_isu_cfg_fd_prog_full_assert_cfg_t {
+	ZXIC_UINT32 fd_prog_full_assert_cfg;
+} DPP_NPPU_ISU_CFG_FD_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_nppu_isu_cfg_fd_prog_full_negate_cfg_t {
+	ZXIC_UINT32 fd_prog_full_negate_cfg;
+} DPP_NPPU_ISU_CFG_FD_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_nppu_isu_cfg_lp_prog_full_assert_cfg_t {
+	ZXIC_UINT32 lp_prog_ept_assert_cfg;
+} DPP_NPPU_ISU_CFG_LP_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_nppu_isu_cfg_lp_prog_full_negate_cfg_t {
+	ZXIC_UINT32 lp_prog_ept_negate_cfg;
+} DPP_NPPU_ISU_CFG_LP_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat0_t {
+	ZXIC_UINT32 debug_cnt_dat0;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT0_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat1_t {
+	ZXIC_UINT32 debug_cnt_dat1;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT1_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat2_t {
+	ZXIC_UINT32 debug_cnt_dat2;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT2_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat3_t {
+	ZXIC_UINT32 debug_cnt_dat3;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT3_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat4_t {
+	ZXIC_UINT32 debug_cnt_dat4;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT4_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat5_t {
+	ZXIC_UINT32 debug_cnt_dat5;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT5_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat6_t {
+	ZXIC_UINT32 debug_cnt_dat6;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT6_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat7_t {
+	ZXIC_UINT32 debug_cnt_dat7;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT7_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat8_t {
+	ZXIC_UINT32 debug_cnt_dat8;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT8_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat9_t {
+	ZXIC_UINT32 debug_cnt_dat9;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT9_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat10_t {
+	ZXIC_UINT32 debug_cnt_dat10;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT10_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat11_t {
+	ZXIC_UINT32 debug_cnt_dat11;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT11_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat12_t {
+	ZXIC_UINT32 debug_cnt_dat12;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT12_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat13_t {
+	ZXIC_UINT32 debug_cnt_dat13;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT13_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat14_t {
+	ZXIC_UINT32 debug_cnt_dat14;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT14_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat15_t {
+	ZXIC_UINT32 debug_cnt_dat15;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT15_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat16_t {
+	ZXIC_UINT32 debug_cnt_dat16;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT16_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat17_t {
+	ZXIC_UINT32 debug_cnt_dat17;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT17_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat18_t {
+	ZXIC_UINT32 debug_cnt_dat18;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT18_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_dat19_t {
+	ZXIC_UINT32 debug_cnt_dat18;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_DAT19_T;
+
+typedef struct dpp_nppu_isu_stat_debug_cnt_cfg_t {
+	ZXIC_UINT32 debug_cnt_ovf_mode;
+	ZXIC_UINT32 debug_cnt_rdclr_mode;
+	ZXIC_UINT32 user_cnt_value;
+} DPP_NPPU_ISU_STAT_DEBUG_CNT_CFG_T;
+
+typedef struct dpp_nppu_odma_cfg_exsa_tdm_offset_t {
+	ZXIC_UINT32 exsa_tdm_offset;
+} DPP_NPPU_ODMA_CFG_EXSA_TDM_OFFSET_T;
+
+typedef struct dpp_nppu_odma_cfg_ecc_bypass_readt_t {
+	ZXIC_UINT32 ecc_bypass_read;
+} DPP_NPPU_ODMA_CFG_ECC_BYPASS_READT_T;
+
+typedef struct dpp_nppu_odma_cfg_odma_int_en_0_t {
+	ZXIC_UINT32 odma_int_en_31;
+	ZXIC_UINT32 odma_int_en_30;
+	ZXIC_UINT32 odma_int_en_29;
+	ZXIC_UINT32 odma_int_en_28;
+	ZXIC_UINT32 odma_int_en_27;
+	ZXIC_UINT32 odma_int_en_26;
+	ZXIC_UINT32 odma_int_en_25;
+	ZXIC_UINT32 odma_int_en_24;
+	ZXIC_UINT32 odma_int_en_22;
+	ZXIC_UINT32 odma_int_en_21;
+	ZXIC_UINT32 odma_int_en_18;
+} DPP_NPPU_ODMA_CFG_ODMA_INT_EN_0_T;
+
+typedef struct dpp_nppu_odma_cfg_odma_int_en_1_t {
+	ZXIC_UINT32 odma_int_en_63;
+	ZXIC_UINT32 odma_int_en_62;
+	ZXIC_UINT32 odma_int_en_61;
+	ZXIC_UINT32 odma_int_en_59;
+	ZXIC_UINT32 odma_int_en_58;
+	ZXIC_UINT32 odma_int_en_57;
+	ZXIC_UINT32 odma_int_en_56;
+	ZXIC_UINT32 odma_int_en_55;
+	ZXIC_UINT32 odma_int_en_54;
+	ZXIC_UINT32 odma_int_en_53;
+	ZXIC_UINT32 odma_int_en_52;
+	ZXIC_UINT32 odma_int_en_51;
+	ZXIC_UINT32 odma_int_en_49;
+	ZXIC_UINT32 odma_int_en_47;
+	ZXIC_UINT32 odma_int_en_45;
+	ZXIC_UINT32 odma_int_en_39;
+	ZXIC_UINT32 odma_int_en_38;
+	ZXIC_UINT32 odma_int_en_37;
+	ZXIC_UINT32 odma_int_en_36;
+	ZXIC_UINT32 odma_int_en_35;
+	ZXIC_UINT32 odma_int_en_34;
+	ZXIC_UINT32 odma_int_en_33;
+	ZXIC_UINT32 odma_int_en_32;
+} DPP_NPPU_ODMA_CFG_ODMA_INT_EN_1_T;
+
+typedef struct dpp_nppu_odma_cfg_odma_int_en_2_t {
+	ZXIC_UINT32 odma_int_en_91;
+	ZXIC_UINT32 odma_int_en_88;
+	ZXIC_UINT32 odma_int_en_85;
+	ZXIC_UINT32 odma_int_en_82;
+	ZXIC_UINT32 odma_int_en_79;
+	ZXIC_UINT32 odma_int_en_75;
+	ZXIC_UINT32 odma_int_en_74;
+	ZXIC_UINT32 odma_int_en_71;
+	ZXIC_UINT32 odma_int_en_65;
+	ZXIC_UINT32 odma_int_en_64;
+} DPP_NPPU_ODMA_CFG_ODMA_INT_EN_2_T;
+
+typedef struct dpp_nppu_odma_cfg_odma_int_en_3_t {
+	ZXIC_UINT32 odma_int_en_115;
+	ZXIC_UINT32 odma_int_en_114;
+	ZXIC_UINT32 odma_int_en_112;
+	ZXIC_UINT32 odma_int_en_110;
+	ZXIC_UINT32 odma_int_en_109;
+	ZXIC_UINT32 odma_int_en_108;
+	ZXIC_UINT32 odma_int_en_107;
+	ZXIC_UINT32 odma_int_en_106;
+	ZXIC_UINT32 odma_int_en_102;
+	ZXIC_UINT32 odma_int_en_101;
+	ZXIC_UINT32 odma_int_en_100;
+	ZXIC_UINT32 odma_int_en_98;
+	ZXIC_UINT32 odma_int_en_96;
+} DPP_NPPU_ODMA_CFG_ODMA_INT_EN_3_T;
+
+typedef struct dpp_nppu_odma_cfg_odma_int_mask_0_t {
+	ZXIC_UINT32 odma_int_mask_31;
+	ZXIC_UINT32 odma_int_mask_30;
+	ZXIC_UINT32 odma_int_mask_29;
+	ZXIC_UINT32 odma_int_mask_28;
+	ZXIC_UINT32 odma_int_mask_27;
+	ZXIC_UINT32 odma_int_mask_26;
+	ZXIC_UINT32 odma_int_mask_25;
+	ZXIC_UINT32 odma_int_mask_24;
+	ZXIC_UINT32 odma_int_mask_22;
+	ZXIC_UINT32 odma_int_mask_21;
+	ZXIC_UINT32 odma_int_mask_18;
+} DPP_NPPU_ODMA_CFG_ODMA_INT_MASK_0_T;
+
+typedef struct dpp_nppu_odma_cfg_odma_int_mask_1_t {
+	ZXIC_UINT32 odma_int_mask_63;
+	ZXIC_UINT32 odma_int_mask_62;
+	ZXIC_UINT32 odma_int_mask_61;
+	ZXIC_UINT32 odma_int_mask_59;
+	ZXIC_UINT32 odma_int_mask_58;
+	ZXIC_UINT32 odma_int_mask_57;
+	ZXIC_UINT32 odma_int_mask_56;
+	ZXIC_UINT32 odma_int_mask_55;
+	ZXIC_UINT32 odma_int_mask_54;
+	ZXIC_UINT32 odma_int_mask_53;
+	ZXIC_UINT32 odma_int_mask_52;
+	ZXIC_UINT32 odma_int_mask_51;
+	ZXIC_UINT32 odma_int_mask_50;
+	ZXIC_UINT32 odma_int_mask_49;
+	ZXIC_UINT32 odma_int_mask_47;
+	ZXIC_UINT32 odma_int_mask_45;
+	ZXIC_UINT32 odma_int_mask_39;
+	ZXIC_UINT32 odma_int_mask_38;
+	ZXIC_UINT32 odma_int_mask_37;
+	ZXIC_UINT32 odma_int_mask_36;
+	ZXIC_UINT32 odma_int_mask_35;
+	ZXIC_UINT32 odma_int_mask_34;
+	ZXIC_UINT32 odma_int_mask_33;
+	ZXIC_UINT32 odma_int_mask_32;
+} DPP_NPPU_ODMA_CFG_ODMA_INT_MASK_1_T;
+
+typedef struct dpp_nppu_odma_cfg_odma_int_mask_2_t {
+	ZXIC_UINT32 odma_int_mask_91;
+	ZXIC_UINT32 odma_int_mask_88;
+	ZXIC_UINT32 odma_int_mask_85;
+	ZXIC_UINT32 odma_int_mask_82;
+	ZXIC_UINT32 odma_int_mask_79;
+	ZXIC_UINT32 odma_int_mask_75;
+	ZXIC_UINT32 odma_int_mask_74;
+	ZXIC_UINT32 odma_int_mask_71;
+	ZXIC_UINT32 odma_int_mask_65;
+	ZXIC_UINT32 odma_int_mask_64;
+} DPP_NPPU_ODMA_CFG_ODMA_INT_MASK_2_T;
+
+typedef struct dpp_nppu_odma_cfg_odma_int_mask_3_t {
+	ZXIC_UINT32 odma_int_mask_115;
+	ZXIC_UINT32 odma_int_mask_114;
+	ZXIC_UINT32 odma_int_mask_112;
+	ZXIC_UINT32 odma_int_mask_110;
+	ZXIC_UINT32 odma_int_mask_109;
+	ZXIC_UINT32 odma_int_mask_108;
+	ZXIC_UINT32 odma_int_mask_107;
+	ZXIC_UINT32 odma_int_mask_106;
+	ZXIC_UINT32 odma_int_mask_102;
+	ZXIC_UINT32 odma_int_mask_101;
+	ZXIC_UINT32 odma_int_mask_100;
+	ZXIC_UINT32 odma_int_mask_98;
+	ZXIC_UINT32 odma_int_mask_96;
+} DPP_NPPU_ODMA_CFG_ODMA_INT_MASK_3_T;
+
+typedef struct dpp_nppu_odma_cfg_odma_int_status_0_t {
+	ZXIC_UINT32 odma_int_status_31;
+	ZXIC_UINT32 odma_int_status_30;
+	ZXIC_UINT32 odma_int_status_29;
+	ZXIC_UINT32 odma_int_status_28;
+	ZXIC_UINT32 odma_int_status_27;
+	ZXIC_UINT32 odma_int_status_26;
+	ZXIC_UINT32 odma_int_status_25;
+	ZXIC_UINT32 odma_int_status_24;
+	ZXIC_UINT32 odma_int_status_22;
+	ZXIC_UINT32 odma_int_status_21;
+	ZXIC_UINT32 odma_int_status_18;
+} DPP_NPPU_ODMA_CFG_ODMA_INT_STATUS_0_T;
+
+typedef struct dpp_nppu_odma_cfg_odma_int_status_1_t {
+	ZXIC_UINT32 odma_int_status_63;
+	ZXIC_UINT32 odma_int_status_62;
+	ZXIC_UINT32 odma_int_status_61;
+	ZXIC_UINT32 odma_int_status_59;
+	ZXIC_UINT32 odma_int_status_58;
+	ZXIC_UINT32 odma_int_status_57;
+	ZXIC_UINT32 odma_int_status_56;
+	ZXIC_UINT32 odma_int_status_55;
+	ZXIC_UINT32 odma_int_status_54;
+	ZXIC_UINT32 odma_int_status_53;
+	ZXIC_UINT32 odma_int_status_52;
+	ZXIC_UINT32 odma_int_status_51;
+	ZXIC_UINT32 odma_int_status_49;
+	ZXIC_UINT32 odma_int_status_47;
+	ZXIC_UINT32 odma_int_status_45;
+	ZXIC_UINT32 odma_int_status_39;
+	ZXIC_UINT32 odma_int_status_38;
+	ZXIC_UINT32 odma_int_status_37;
+	ZXIC_UINT32 odma_int_status_36;
+	ZXIC_UINT32 odma_int_status_35;
+	ZXIC_UINT32 odma_int_status_34;
+	ZXIC_UINT32 odma_int_status_33;
+	ZXIC_UINT32 odma_int_status_32;
+} DPP_NPPU_ODMA_CFG_ODMA_INT_STATUS_1_T;
+
+typedef struct dpp_nppu_odma_cfg_odma_int_status_2_t {
+	ZXIC_UINT32 odma_int_status_91;
+	ZXIC_UINT32 odma_int_status_88;
+	ZXIC_UINT32 odma_int_status_85;
+	ZXIC_UINT32 odma_int_status_82;
+	ZXIC_UINT32 odma_int_status_79;
+	ZXIC_UINT32 odma_int_status_75;
+	ZXIC_UINT32 odma_int_status_74;
+	ZXIC_UINT32 odma_int_status_71;
+	ZXIC_UINT32 odma_int_status_65;
+	ZXIC_UINT32 odma_int_status_64;
+} DPP_NPPU_ODMA_CFG_ODMA_INT_STATUS_2_T;
+
+typedef struct dpp_nppu_odma_cfg_odma_int_status_3_t {
+	ZXIC_UINT32 odma_int_status_117;
+	ZXIC_UINT32 odma_int_status_116;
+	ZXIC_UINT32 odma_int_status_115;
+	ZXIC_UINT32 odma_int_status_114;
+	ZXIC_UINT32 odma_int_status_112;
+	ZXIC_UINT32 odma_int_status_110;
+	ZXIC_UINT32 odma_int_status_109;
+	ZXIC_UINT32 odma_int_status_108;
+	ZXIC_UINT32 odma_int_status_107;
+	ZXIC_UINT32 odma_int_status_106;
+	ZXIC_UINT32 odma_int_status_102;
+	ZXIC_UINT32 odma_int_status_101;
+	ZXIC_UINT32 odma_int_status_100;
+	ZXIC_UINT32 odma_int_status_98;
+	ZXIC_UINT32 odma_int_status_96;
+} DPP_NPPU_ODMA_CFG_ODMA_INT_STATUS_3_T;
+
+typedef struct dpp_nppu_odma_cfg_sp_tdm_err_nor_cfg_t {
+	ZXIC_UINT32 sp_tdm_err_nor_cfg;
+} DPP_NPPU_ODMA_CFG_SP_TDM_ERR_NOR_CFG_T;
+
+typedef struct dpp_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_a_t {
+	ZXIC_UINT32 etm_dis_ptr_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_n_t {
+	ZXIC_UINT32 etm_dis_ptr_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_a_t {
+	ZXIC_UINT32 ftm_dis_ptr_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_n_t {
+	ZXIC_UINT32 ftm_dis_ptr_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_a_t {
+	ZXIC_UINT32 tm_dis_fifo_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_n_t {
+	ZXIC_UINT32 tm_dis_fifo_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_err_prog_full_cfg_a_t {
+	ZXIC_UINT32 err_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_err_prog_full_cfg_n_t {
+	ZXIC_UINT32 err_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_tdmuc_prog_full_cfg_a_t {
+	ZXIC_UINT32 tdmuc_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_tdmuc_prog_full_cfg_n_t {
+	ZXIC_UINT32 tdmuc_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_a_t {
+	ZXIC_UINT32 tdmmc_groupid_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_n_t {
+	ZXIC_UINT32 tdmmc_groupid_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_a_t {
+	ZXIC_UINT32 tdmmc_no_bitmap_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_n_t {
+	ZXIC_UINT32 tdmmc_no_bitmap_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_tdmmc_prog_full_cfg_a_t {
+	ZXIC_UINT32 tdmmc_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_tdmmc_prog_full_cfg_n_t {
+	ZXIC_UINT32 tdmmc_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_desc_prog_full_cfg_a_t {
+	ZXIC_UINT32 desc_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_desc_prog_full_cfg_n_t {
+	ZXIC_UINT32 desc_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_dly_prog_full_cfg_a_t {
+	ZXIC_UINT32 dly_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_dly_prog_full_cfg_n_t {
+	ZXIC_UINT32 dly_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_rsp_prog_full_cfg_a_t {
+	ZXIC_UINT32 rsp_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_rsp_prog_full_cfg_n_t {
+	ZXIC_UINT32 rsp_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_nor_prog_full_cfg_a_t {
+	ZXIC_UINT32 nor_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_A_T;
 
+typedef struct dpp_nppu_odma_cfg_nor_prog_full_cfg_n_t {
+	ZXIC_UINT32 nor_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_etm_nor_prog_full_cfg_a_t {
+	ZXIC_UINT32 etm_nor_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_etm_nor_prog_full_cfg_n_t {
+	ZXIC_UINT32 etm_nor_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_ftm_nor_prog_full_cfg_a_t {
+	ZXIC_UINT32 ftm_nor_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_ftm_nor_prog_full_cfg_n_t {
+	ZXIC_UINT32 ftm_nor_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_etm_prog_full_cfg_a_t {
+	ZXIC_UINT32 etm_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_etm_prog_full_cfg_n_t {
+	ZXIC_UINT32 etm_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_ftm_prog_full_cfg_a_t {
+	ZXIC_UINT32 ftm_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_ftm_prog_full_cfg_n_t {
+	ZXIC_UINT32 ftm_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_a_t {
+	ZXIC_UINT32 etm_nrdcnt_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_n_t {
+	ZXIC_UINT32 etm_nrdcnt_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_a_t {
+	ZXIC_UINT32 ftm_nrdcnt_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_n_t {
+	ZXIC_UINT32 ftm_nrdcnt_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_pp_prog_full_cfg_a_t {
+	ZXIC_UINT32 pp_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_PP_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_pp_prog_full_cfg_n_t {
+	ZXIC_UINT32 pp_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_PP_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_tm_weight_t {
+	ZXIC_UINT32 tm_weight;
+} DPP_NPPU_ODMA_CFG_TM_WEIGHT_T;
+
+typedef struct dpp_nppu_odma_cfg_pp_weight_t {
+	ZXIC_UINT32 pp_weight;
+} DPP_NPPU_ODMA_CFG_PP_WEIGHT_T;
+
+typedef struct dpp_nppu_odma_cfg_ifbcmd_prog_full_cfg_a_t {
+	ZXIC_UINT32 ifbcmd_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_ifbcmd_prog_full_cfg_n_t {
+	ZXIC_UINT32 ifbcmd_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_mccnt_prog_full_cfg_a_t {
+	ZXIC_UINT32 mccnt_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_mccnt_prog_full_cfg_n_t {
+	ZXIC_UINT32 mccnt_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_int_or_pon_t {
+	ZXIC_UINT32 int_or_pon;
+} DPP_NPPU_ODMA_CFG_INT_OR_PON_T;
+
+typedef struct dpp_nppu_odma_cfg_quemng_cnt_in_err_cnt_t {
+	ZXIC_UINT32 quemng_cnt_in_err_cnt;
+} DPP_NPPU_ODMA_CFG_QUEMNG_CNT_IN_ERR_CNT_T;
+
+typedef struct dpp_nppu_odma_cfg_lif0_port_eop_cnt_t {
+	ZXIC_UINT32 lif0_port_eop_cnt;
+} DPP_NPPU_ODMA_CFG_LIF0_PORT_EOP_CNT_T;
+
+typedef struct dpp_nppu_odma_cfg_lif1_port_eop_cnt_t {
+	ZXIC_UINT32 lif1_port_eop_cnt;
+} DPP_NPPU_ODMA_CFG_LIF1_PORT_EOP_CNT_T;
+
+typedef struct dpp_nppu_odma_cfg_lifc_port0_eop_cnt_t {
+	ZXIC_UINT32 lifc_port0_eop_cnt;
+} DPP_NPPU_ODMA_CFG_LIFC_PORT0_EOP_CNT_T;
+
+typedef struct dpp_nppu_odma_cfg_lifc_port1_eop_cnt_t {
+	ZXIC_UINT32 lifc_port1_eop_cnt;
+} DPP_NPPU_ODMA_CFG_LIFC_PORT1_EOP_CNT_T;
+
+typedef struct dpp_nppu_odma_cfg_fptr_fifo_prog_ept_cfg_n_t {
+	ZXIC_UINT32 fptr_fifo_prog_ept_cfg_n;
+} DPP_NPPU_ODMA_CFG_FPTR_FIFO_PROG_EPT_CFG_N_T;
+
+typedef struct dpp_nppu_odma_cfg_isu_fifo_prog_full_cfg_a_t {
+	ZXIC_UINT32 isu_fifo_prog_full_cfg_a;
+} DPP_NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_A_T;
+
+typedef struct dpp_nppu_odma_cfg_isu_fifo_prog_full_cfg_n_t {
+	ZXIC_UINT32 isu_fifo_prog_full_cfg_n;
+} DPP_NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_N_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_access_done_t {
+	ZXIC_UINT32 ind_access_done;
+} DPP_NPPU_OAM_CFG_IND_ACCESS_DONE_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_access_command_t {
+	ZXIC_UINT32 ind_rd_or_wr;
+	ZXIC_UINT32 ind_mem_mask;
+	ZXIC_UINT32 ind_mem_id;
+	ZXIC_UINT32 ind_mem_addr;
+} DPP_NPPU_OAM_CFG_IND_ACCESS_COMMAND_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_dat0_t {
+	ZXIC_UINT32 ind_dat0;
+} DPP_NPPU_OAM_CFG_IND_DAT0_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_dat1_t {
+	ZXIC_UINT32 ind_dat1;
+} DPP_NPPU_OAM_CFG_IND_DAT1_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_dat2_t {
+	ZXIC_UINT32 ind_dat2;
+} DPP_NPPU_OAM_CFG_IND_DAT2_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_dat3_t {
+	ZXIC_UINT32 ind_dat3;
+} DPP_NPPU_OAM_CFG_IND_DAT3_T;
+
+typedef struct dpp_nppu_oam_cfg_oam_tx_main_en_t {
+	ZXIC_UINT32 oam_tx_main_en;
+} DPP_NPPU_OAM_CFG_OAM_TX_MAIN_EN_T;
+
+typedef struct dpp_nppu_oam_cfg_tx_total_num_t {
+	ZXIC_UINT32 tx_total_num;
+} DPP_NPPU_OAM_CFG_TX_TOTAL_NUM_T;
+
+typedef struct dpp_nppu_oam_cfg_oam_chk_main_en_t {
+	ZXIC_UINT32 oam_chk_main_en;
+} DPP_NPPU_OAM_CFG_OAM_CHK_MAIN_EN_T;
+
+typedef struct dpp_nppu_oam_cfg_chk_total_num0_t {
+	ZXIC_UINT32 chk_total_num0;
+} DPP_NPPU_OAM_CFG_CHK_TOTAL_NUM0_T;
+
+typedef struct dpp_nppu_oam_cfg_ma_chk_main_en_t {
+	ZXIC_UINT32 oam_chk_main_en;
+} DPP_NPPU_OAM_CFG_MA_CHK_MAIN_EN_T;
+
+typedef struct dpp_nppu_oam_cfg_chk_total_num1_t {
+	ZXIC_UINT32 chk_total_num0;
+} DPP_NPPU_OAM_CFG_CHK_TOTAL_NUM1_T;
+
+typedef struct dpp_nppu_oam_cfg_tx_stat_en_t {
+	ZXIC_UINT32 tx_stat_en;
+} DPP_NPPU_OAM_CFG_TX_STAT_EN_T;
+
+typedef struct dpp_nppu_oam_cfg_rec_stat_en_t {
+	ZXIC_UINT32 rec_stat_en;
+} DPP_NPPU_OAM_CFG_REC_STAT_EN_T;
+
+typedef struct dpp_nppu_oam_cfg_stat_oam_rdy_mask_t {
+	ZXIC_UINT32 stat_oam_rdy_mask;
+} DPP_NPPU_OAM_CFG_STAT_OAM_RDY_MASK_T;
+
+typedef struct dpp_nppu_oam_cfg_session_grading0_t {
+	ZXIC_UINT32 session_grading0;
+} DPP_NPPU_OAM_CFG_SESSION_GRADING0_T;
+
+typedef struct dpp_nppu_oam_cfg_session_grading1_t {
+	ZXIC_UINT32 session_grading1;
+} DPP_NPPU_OAM_CFG_SESSION_GRADING1_T;
+
+typedef struct dpp_nppu_oam_cfg_session_grading2_t {
+	ZXIC_UINT32 session_grading2;
+} DPP_NPPU_OAM_CFG_SESSION_GRADING2_T;
+
+typedef struct dpp_nppu_oam_cfg_session_grading3_t {
+	ZXIC_UINT32 session_grading3;
+} DPP_NPPU_OAM_CFG_SESSION_GRADING3_T;
+
+typedef struct dpp_nppu_oam_cfg_bfd_chk_haddr_t {
+	ZXIC_UINT32 bfd_chk_haddr;
+} DPP_NPPU_OAM_CFG_BFD_CHK_HADDR_T;
+
+typedef struct dpp_nppu_oam_cfg_ethccm_chk_haddr_t {
+	ZXIC_UINT32 ethccm_chk_haddr;
+} DPP_NPPU_OAM_CFG_ETHCCM_CHK_HADDR_T;
+
+typedef struct dpp_nppu_oam_cfg_tpbfd_chk_haddr_t {
+	ZXIC_UINT32 tpbfd_chk_haddr;
+} DPP_NPPU_OAM_CFG_TPBFD_CHK_HADDR_T;
+
+typedef struct dpp_nppu_oam_cfg_tpoam_ccm_chk_haddr_t {
+	ZXIC_UINT32 tpoam_ccm_chk_haddr;
+} DPP_NPPU_OAM_CFG_TPOAM_CCM_CHK_HADDR_T;
+
+typedef struct dpp_nppu_oam_cfg_bfd_tx_haddr_t {
+	ZXIC_UINT32 bfd_tx_haddr;
+} DPP_NPPU_OAM_CFG_BFD_TX_HADDR_T;
+
+typedef struct dpp_nppu_oam_cfg_ethccm_tx_haddr_t {
+	ZXIC_UINT32 ethccm_tx_haddr;
+} DPP_NPPU_OAM_CFG_ETHCCM_TX_HADDR_T;
+
+typedef struct dpp_nppu_oam_cfg_tpbfd_tx_haddr_t {
+	ZXIC_UINT32 tpbfd_tx_haddr;
+} DPP_NPPU_OAM_CFG_TPBFD_TX_HADDR_T;
+
+typedef struct dpp_nppu_oam_cfg_tpoam_ccm_tx_haddr_t {
+	ZXIC_UINT32 tpoam_ccm_tx_haddr;
+} DPP_NPPU_OAM_CFG_TPOAM_CCM_TX_HADDR_T;
+
+typedef struct dpp_nppu_oam_cfg_ethccm_ma_chk_haddr_t {
+	ZXIC_UINT32 ethccm_ma_chk_haddr;
+} DPP_NPPU_OAM_CFG_ETHCCM_MA_CHK_HADDR_T;
+
+typedef struct dpp_nppu_oam_cfg_tpccm_ma_chk_haddr_t {
+	ZXIC_UINT32 tpccm_ma_chk_haddr;
+} DPP_NPPU_OAM_CFG_TPCCM_MA_CHK_HADDR_T;
+
+typedef struct dpp_nppu_oam_cfg_groupnum_ram_clr_t {
+	ZXIC_UINT32 groupnum_ram_clr;
+} DPP_NPPU_OAM_CFG_GROUPNUM_RAM_CLR_T;
+
+typedef struct dpp_nppu_oam_cfg_index_ram0_clr_t {
+	ZXIC_UINT32 index_ram0_clr;
+} DPP_NPPU_OAM_CFG_INDEX_RAM0_CLR_T;
+
+typedef struct dpp_nppu_oam_cfg_index_ram1_clr_t {
+	ZXIC_UINT32 index_ram1_clr;
+} DPP_NPPU_OAM_CFG_INDEX_RAM1_CLR_T;
+
+typedef struct dpp_nppu_oam_cfg_rmep_ram_clr_t {
+	ZXIC_UINT32 rmep_ram_clr;
+} DPP_NPPU_OAM_CFG_RMEP_RAM_CLR_T;
+
+typedef struct dpp_nppu_oam_cfg_ma_ram_clr_t {
+	ZXIC_UINT32 ma_ram_clr;
+} DPP_NPPU_OAM_CFG_MA_RAM_CLR_T;
+
+typedef struct dpp_nppu_oam_cfg_ram_init_done_t {
+	ZXIC_UINT32 ram_init_done;
+} DPP_NPPU_OAM_CFG_RAM_INIT_DONE_T;
+
+typedef struct dpp_nppu_oam_cfg_rec_bfd_debug_en_t {
+	ZXIC_UINT32 rec_bfd_debug_en;
+} DPP_NPPU_OAM_CFG_REC_BFD_DEBUG_EN_T;
+
+typedef struct dpp_nppu_oam_cfg_oam_session_int_t {
+	ZXIC_UINT32 tpma_int;
+	ZXIC_UINT32 ethma_int;
+	ZXIC_UINT32 bfd_int;
+	ZXIC_UINT32 ethoam_int;
+	ZXIC_UINT32 tpbfd_int;
+	ZXIC_UINT32 tpoam_int;
+} DPP_NPPU_OAM_CFG_OAM_SESSION_INT_T;
+
+typedef struct dpp_nppu_oam_cfg_pon_int_t {
+	ZXIC_UINT32 fifo_int;
+	ZXIC_UINT32 pon_protect_int;
+} DPP_NPPU_OAM_CFG_PON_INT_T;
+
+typedef struct dpp_nppu_oam_cfg_oam_int_clr_t {
+	ZXIC_UINT32 oam_int_clr;
+} DPP_NPPU_OAM_CFG_OAM_INT_CLR_T;
+
+typedef struct dpp_nppu_oam_cfg_type_int_clr0_t {
+	ZXIC_UINT32 tpma_int_clr;
+	ZXIC_UINT32 ethma_int_clr;
+	ZXIC_UINT32 bfd_int_clr;
+	ZXIC_UINT32 ethoam_int_clr;
+	ZXIC_UINT32 tpbfd_int_clr;
+	ZXIC_UINT32 tpoam_int_clr;
+} DPP_NPPU_OAM_CFG_TYPE_INT_CLR0_T;
+
+typedef struct dpp_nppu_oam_cfg_type_int_clr1_t {
+	ZXIC_UINT32 fifo_int_clr;
+	ZXIC_UINT32 pon_protect_int_clr;
+} DPP_NPPU_OAM_CFG_TYPE_INT_CLR1_T;
+
+typedef struct dpp_nppu_oam_cfg_interrupt_mask_t {
+	ZXIC_UINT32 fifo_interrupt_mask;
+	ZXIC_UINT32 pon_protect_interruptmask;
+	ZXIC_UINT32 tpma_interrupt_mask;
+	ZXIC_UINT32 ethma_interrupt_mask;
+	ZXIC_UINT32 bfd_interrupt_mask;
+	ZXIC_UINT32 ethoam_interrupt_mask;
+	ZXIC_UINT32 tpbfd_interrupt_mask;
+	ZXIC_UINT32 tpoam_interrupt_mask;
+} DPP_NPPU_OAM_CFG_INTERRUPT_MASK_T;
+
+typedef struct dpp_nppu_oam_cfg_int0_index_t {
+	ZXIC_UINT32 int0_index0;
+} DPP_NPPU_OAM_CFG_INT0_INDEX_T;
+
+typedef struct dpp_nppu_oam_cfg_int1_index_t {
+	ZXIC_UINT32 int1_index0;
+} DPP_NPPU_OAM_CFG_INT1_INDEX_T;
+
+typedef struct dpp_nppu_oam_cfg_int0_index_region_t {
+	ZXIC_UINT32 int0_index_region;
+} DPP_NPPU_OAM_CFG_INT0_INDEX_REGION_T;
+
+typedef struct dpp_nppu_oam_cfg_int1_index_region_t {
+	ZXIC_UINT32 int1_index_region;
+} DPP_NPPU_OAM_CFG_INT1_INDEX_REGION_T;
+
+typedef struct dpp_nppu_oam_cfg_bdiinfo_fwft_fifo_th_t {
+	ZXIC_UINT32 bdiinfo_fwft_fifo_th;
+} DPP_NPPU_OAM_CFG_BDIINFO_FWFT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_recsec_fwft_fifo_th_t {
+	ZXIC_UINT32 recsec_fwft_fifo_th;
+} DPP_NPPU_OAM_CFG_RECSEC_FWFT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_timing_chk_info0_fwft_fifo_th_t {
+	ZXIC_UINT32 timing_chk_info0_fwft_fifo_th;
+} DPP_NPPU_OAM_CFG_TIMING_CHK_INFO0_FWFT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_recma_fwft_fifo_th_t {
+	ZXIC_UINT32 recma_fwft_fifo_th;
+} DPP_NPPU_OAM_CFG_RECMA_FWFT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_timing_chk_info1_fwft_fifo_th_t {
+	ZXIC_UINT32 timing_chk_info1_fwft_fifo_th;
+} DPP_NPPU_OAM_CFG_TIMING_CHK_INFO1_FWFT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_oam_txinst_fifo_th_t {
+	ZXIC_UINT32 oam_txinst_fifo_th;
+} DPP_NPPU_OAM_CFG_OAM_TXINST_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_oam_rdinfo_fwft_fifo_th_t {
+	ZXIC_UINT32 oam_rdinfo_fwft_fifo_th;
+} DPP_NPPU_OAM_CFG_OAM_RDINFO_FWFT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_lm_cnt_fwft_fifo_th_t {
+	ZXIC_UINT32 lm_cnt_fwft_fifo_th;
+} DPP_NPPU_OAM_CFG_LM_CNT_FWFT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_oam_pkt_fifo_th_t {
+	ZXIC_UINT32 oam_pkt_fifo_th;
+} DPP_NPPU_OAM_CFG_OAM_PKT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_reclm_stat_fifo_th_t {
+	ZXIC_UINT32 reclm_stat_fifo_th;
+} DPP_NPPU_OAM_CFG_RECLM_STAT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_txlm_stat_fifo_th_t {
+	ZXIC_UINT32 txlm_stat_fifo_th;
+} DPP_NPPU_OAM_CFG_TXLM_STAT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_oam_chk_fwft_fifo_th_t {
+	ZXIC_UINT32 oam_chk_fwft_fifo_th;
+} DPP_NPPU_OAM_CFG_OAM_CHK_FWFT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_txoam_stat_fifo_th_t {
+	ZXIC_UINT32 txoam_stat_fifo_th;
+} DPP_NPPU_OAM_CFG_TXOAM_STAT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_recoam_stat_fifo_th_t {
+	ZXIC_UINT32 recoam_stat_fifo_th;
+} DPP_NPPU_OAM_CFG_RECOAM_STAT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_txpkt_data_fwft_fifo_th_t {
+	ZXIC_UINT32 txpkt_data_fwft_fifo_th;
+} DPP_NPPU_OAM_CFG_TXPKT_DATA_FWFT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_tstpkt_fwft_fifo_th_t {
+	ZXIC_UINT32 tstpkt_fwft_fifo_th;
+} DPP_NPPU_OAM_CFG_TSTPKT_FWFT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_tst_txinst_fwft_fifo_th_t {
+	ZXIC_UINT32 tst_txinst_fwft_fifo_th;
+} DPP_NPPU_OAM_CFG_TST_TXINST_FWFT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_tstrx_main_en_t {
+	ZXIC_UINT32 tstrx_main_en;
+} DPP_NPPU_OAM_CFG_TSTRX_MAIN_EN_T;
+
+typedef struct dpp_nppu_oam_cfg_tsttx_cfg_para_tbl2_t {
+	ZXIC_UINT32 ddr_self_test_tx_en;
+	ZXIC_UINT32 tm_self_test_tx_en;
+	ZXIC_UINT32 fast_aging_tx_en;
+	ZXIC_UINT32 timing_aging_tx_en;
+	ZXIC_UINT32 backgroud_flow_tx_en;
+	ZXIC_UINT32 tsttx_tx_en;
+	ZXIC_UINT32 tx_freq;
+	ZXIC_UINT32 tx_offset;
+} DPP_NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL2_T;
+
+typedef struct dpp_nppu_oam_cfg_tsttx_cfg_para_tbl1_t {
+	ZXIC_UINT32 tx_count;
+} DPP_NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL1_T;
+
+typedef struct dpp_nppu_oam_cfg_tsttx_cfg_para_tbl0_t {
+	ZXIC_UINT32 fast_tx_mode_en;
+	ZXIC_UINT32 tsttx_tx_head_len;
+	ZXIC_UINT32 tsttx_tx_interval;
+} DPP_NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL0_T;
+
+typedef struct dpp_nppu_oam_cfg_tstrx_cfg_para_t {
+	ZXIC_UINT32 tstrx_session_num;
+	ZXIC_UINT32 tstrx_session_en;
+} DPP_NPPU_OAM_CFG_TSTRX_CFG_PARA_T;
+
+typedef struct dpp_nppu_oam_cfg_fifo_status_int_en_0_t {
+	ZXIC_UINT32 fifo_status_int_en_31;
+	ZXIC_UINT32 fifo_status_int_en_30;
+	ZXIC_UINT32 fifo_status_int_en_29;
+	ZXIC_UINT32 fifo_status_int_en_28;
+	ZXIC_UINT32 fifo_status_int_en_27;
+	ZXIC_UINT32 fifo_status_int_en_26;
+	ZXIC_UINT32 fifo_status_int_en_25;
+	ZXIC_UINT32 fifo_status_int_en_24;
+	ZXIC_UINT32 fifo_status_int_en_23;
+	ZXIC_UINT32 fifo_status_int_en_22;
+	ZXIC_UINT32 fifo_status_int_en_21;
+	ZXIC_UINT32 fifo_status_int_en_20;
+	ZXIC_UINT32 fifo_status_int_en_19;
+	ZXIC_UINT32 fifo_status_int_en_18;
+	ZXIC_UINT32 fifo_status_int_en_17;
+	ZXIC_UINT32 fifo_status_int_en_16;
+	ZXIC_UINT32 fifo_status_int_en_15;
+	ZXIC_UINT32 fifo_status_int_en_14;
+	ZXIC_UINT32 fifo_status_int_en_13;
+	ZXIC_UINT32 fifo_status_int_en_12;
+	ZXIC_UINT32 fifo_status_int_en_11;
+	ZXIC_UINT32 fifo_status_int_en_10;
+	ZXIC_UINT32 fifo_status_int_en_9;
+	ZXIC_UINT32 fifo_status_int_en_8;
+	ZXIC_UINT32 fifo_status_int_en_7;
+	ZXIC_UINT32 fifo_status_int_en_6;
+	ZXIC_UINT32 fifo_status_int_en_5;
+	ZXIC_UINT32 fifo_status_int_en_4;
+	ZXIC_UINT32 fifo_status_int_en_3;
+	ZXIC_UINT32 fifo_status_int_en_2;
+	ZXIC_UINT32 fifo_status_int_en_1;
+	ZXIC_UINT32 fifo_status_int_en_0;
+} DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_EN_0_T;
+
+typedef struct dpp_nppu_oam_cfg_fifo_status_int_en_1_t {
+	ZXIC_UINT32 fifo_status_int_en_41;
+	ZXIC_UINT32 fifo_status_int_en_40;
+	ZXIC_UINT32 fifo_status_int_en_39;
+	ZXIC_UINT32 fifo_status_int_en_38;
+	ZXIC_UINT32 fifo_status_int_en_37;
+	ZXIC_UINT32 fifo_status_int_en_36;
+	ZXIC_UINT32 fifo_status_int_en_35;
+	ZXIC_UINT32 fifo_status_int_en_34;
+	ZXIC_UINT32 fifo_status_int_en_33;
+	ZXIC_UINT32 fifo_status_int_en_32;
+} DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_EN_1_T;
+
+typedef struct dpp_nppu_oam_cfg_fifo_status_int_mask_0_t {
+	ZXIC_UINT32 fifo_status_int_mask_31;
+	ZXIC_UINT32 fifo_status_int_mask_30;
+	ZXIC_UINT32 fifo_status_int_mask_29;
+	ZXIC_UINT32 fifo_status_int_mask_28;
+	ZXIC_UINT32 fifo_status_int_mask_27;
+	ZXIC_UINT32 fifo_status_int_mask_26;
+	ZXIC_UINT32 fifo_status_int_mask_25;
+	ZXIC_UINT32 fifo_status_int_mask_24;
+	ZXIC_UINT32 fifo_status_int_mask_23;
+	ZXIC_UINT32 fifo_status_int_mask_22;
+	ZXIC_UINT32 fifo_status_int_mask_21;
+	ZXIC_UINT32 fifo_status_int_mask_20;
+	ZXIC_UINT32 fifo_status_int_mask_19;
+	ZXIC_UINT32 fifo_status_int_mask_18;
+	ZXIC_UINT32 fifo_status_int_mask_17;
+	ZXIC_UINT32 fifo_status_int_mask_16;
+	ZXIC_UINT32 fifo_status_int_mask_15;
+	ZXIC_UINT32 fifo_status_int_mask_14;
+	ZXIC_UINT32 fifo_status_int_mask_13;
+	ZXIC_UINT32 fifo_status_int_mask_12;
+	ZXIC_UINT32 fifo_status_int_mask_11;
+	ZXIC_UINT32 fifo_status_int_mask_10;
+	ZXIC_UINT32 fifo_status_int_mask_9;
+	ZXIC_UINT32 fifo_status_int_mask_8;
+	ZXIC_UINT32 fifo_status_int_mask_7;
+	ZXIC_UINT32 fifo_status_int_mask_6;
+	ZXIC_UINT32 fifo_status_int_mask_5;
+	ZXIC_UINT32 fifo_status_int_mask_4;
+	ZXIC_UINT32 fifo_status_int_mask_3;
+	ZXIC_UINT32 fifo_status_int_mask_2;
+	ZXIC_UINT32 fifo_status_int_mask_1;
+	ZXIC_UINT32 fifo_status_int_mask_0;
+} DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_0_T;
+
+typedef struct dpp_nppu_oam_cfg_fifo_status_int_mask_1_t {
+	ZXIC_UINT32 fifo_status_int_mask_41;
+	ZXIC_UINT32 fifo_status_int_mask_40;
+	ZXIC_UINT32 fifo_status_int_mask_39;
+	ZXIC_UINT32 fifo_status_int_mask_38;
+	ZXIC_UINT32 fifo_status_int_mask_37;
+	ZXIC_UINT32 fifo_status_int_mask_36;
+	ZXIC_UINT32 fifo_status_int_mask_35;
+	ZXIC_UINT32 fifo_status_int_mask_34;
+	ZXIC_UINT32 fifo_status_int_mask_33;
+	ZXIC_UINT32 fifo_status_int_mask_32;
+} DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_1_T;
+
+typedef struct dpp_nppu_oam_cfg_fifo_status_int_status_t {
+	ZXIC_UINT32 fifo_status_int_status;
+} DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS_T;
+
+typedef struct dpp_nppu_oam_cfg_main_frequency_t {
+	ZXIC_UINT32 main_frequency;
+} DPP_NPPU_OAM_CFG_MAIN_FREQUENCY_T;
+
+typedef struct dpp_nppu_oam_cfg_oam_cfg_type_t {
+	ZXIC_UINT32 oam_cfg_type;
+} DPP_NPPU_OAM_CFG_OAM_CFG_TYPE_T;
+
+typedef struct dpp_nppu_oam_cfg_fst_swch_eth_head0_t {
+	ZXIC_UINT32 fst_swch_eth_head;
+} DPP_NPPU_OAM_CFG_FST_SWCH_ETH_HEAD0_T;
+
+typedef struct dpp_nppu_oam_cfg_fst_swch_eth_head1_t {
+	ZXIC_UINT32 fst_swch_eth_head1;
+} DPP_NPPU_OAM_CFG_FST_SWCH_ETH_HEAD1_T;
+
+typedef struct dpp_nppu_oam_cfg_fst_swch_eth_head2_t {
+	ZXIC_UINT32 fst_swch_eth_head2;
+} DPP_NPPU_OAM_CFG_FST_SWCH_ETH_HEAD2_T;
+
+typedef struct dpp_nppu_oam_cfg_fst_swch_eth_head3_t {
+	ZXIC_UINT32 fst_swch_eth_head3;
+} DPP_NPPU_OAM_CFG_FST_SWCH_ETH_HEAD3_T;
+
+typedef struct dpp_nppu_oam_cfg_oam_fs_txinst_fifo_th_t {
+	ZXIC_UINT32 oam_fs_txinst_fifo_th;
+} DPP_NPPU_OAM_CFG_OAM_FS_TXINST_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_oam_ma_fs_txinst_fifo_th_t {
+	ZXIC_UINT32 oam_ma_fs_txinst_fifo_th;
+} DPP_NPPU_OAM_CFG_OAM_MA_FS_TXINST_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_pon_int_ram_clr_t {
+	ZXIC_UINT32 pon_int_ram_clr;
+} DPP_NPPU_OAM_CFG_PON_INT_RAM_CLR_T;
+
+typedef struct dpp_nppu_oam_cfg_pon_p_int_index_t {
+	ZXIC_UINT32 pon_p_int_index;
+} DPP_NPPU_OAM_CFG_PON_P_INT_INDEX_T;
+
+typedef struct dpp_nppu_oam_cfg_pon_protect_pkt_fifo_th_t {
+	ZXIC_UINT32 pon_protect_pkt_fifo_th;
+} DPP_NPPU_OAM_CFG_PON_PROTECT_PKT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_pon_laser_off_en_t {
+	ZXIC_UINT32 pon_laser_off_en;
+} DPP_NPPU_OAM_CFG_PON_LASER_OFF_EN_T;
+
+typedef struct dpp_nppu_oam_cfg_pon_prtct_pkt_tx_en_t {
+	ZXIC_UINT32 pon_prtct_pkt_tx_en;
+} DPP_NPPU_OAM_CFG_PON_PRTCT_PKT_TX_EN_T;
+
+typedef struct dpp_nppu_oam_cfg_cfg_pon_master_t {
+	ZXIC_UINT32 cfg_pon_master;
+} DPP_NPPU_OAM_CFG_CFG_PON_MASTER_T;
+
+typedef struct dpp_nppu_oam_cfg_level_mode_t {
+	ZXIC_UINT32 level_mode;
+} DPP_NPPU_OAM_CFG_LEVEL_MODE_T;
+
+typedef struct dpp_nppu_oam_cfg_interrupt_en_t {
+	ZXIC_UINT32 interrupt_en;
+} DPP_NPPU_OAM_CFG_INTERRUPT_EN_T;
+
+typedef struct dpp_nppu_oam_cfg_pon_laser_on_en_t {
+	ZXIC_UINT32 pon_laser_on_en;
+} DPP_NPPU_OAM_CFG_PON_LASER_ON_EN_T;
+
+typedef struct dpp_nppu_oam_cfg_ti_pon_sd_t {
+	ZXIC_UINT32 ti_pon_sd;
+} DPP_NPPU_OAM_CFG_TI_PON_SD_T;
+
+typedef struct dpp_nppu_oam_cfg_ti_pon_los_t {
+	ZXIC_UINT32 ti_pon_los;
+} DPP_NPPU_OAM_CFG_TI_PON_LOS_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_dat4_t {
+	ZXIC_UINT32 ind_dat4;
+} DPP_NPPU_OAM_CFG_IND_DAT4_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_dat5_t {
+	ZXIC_UINT32 ind_dat5;
+} DPP_NPPU_OAM_CFG_IND_DAT5_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_dat6_t {
+	ZXIC_UINT32 ind_dat6;
+} DPP_NPPU_OAM_CFG_IND_DAT6_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_dat7_t {
+	ZXIC_UINT32 ind_dat7;
+} DPP_NPPU_OAM_CFG_IND_DAT7_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_dat8_t {
+	ZXIC_UINT32 ind_dat8;
+} DPP_NPPU_OAM_CFG_IND_DAT8_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_dat9_t {
+	ZXIC_UINT32 ind_dat9;
+} DPP_NPPU_OAM_CFG_IND_DAT9_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_dat10_t {
+	ZXIC_UINT32 ind_dat10;
+} DPP_NPPU_OAM_CFG_IND_DAT10_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_dat11_t {
+	ZXIC_UINT32 ind_dat11;
+} DPP_NPPU_OAM_CFG_IND_DAT11_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_dat12_t {
+	ZXIC_UINT32 ind_dat12;
+} DPP_NPPU_OAM_CFG_IND_DAT12_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_dat13_t {
+	ZXIC_UINT32 ind_dat13;
+} DPP_NPPU_OAM_CFG_IND_DAT13_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_dat14_t {
+	ZXIC_UINT32 ind_dat14;
+} DPP_NPPU_OAM_CFG_IND_DAT14_T;
+
+typedef struct dpp_nppu_oam_cfg_ind_dat15_t {
+	ZXIC_UINT32 ind_dat15;
+} DPP_NPPU_OAM_CFG_IND_DAT15_T;
+
+typedef struct dpp_nppu_oam_cfg_oam_2544_pkt_fifo_th_t {
+	ZXIC_UINT32 oam_2544_pkt_fifo_th;
+} DPP_NPPU_OAM_CFG_OAM_2544_PKT_FIFO_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_txinfo_ram_clr_t {
+	ZXIC_UINT32 txinfo_ram_clr;
+} DPP_NPPU_OAM_CFG_TXINFO_RAM_CLR_T;
+
+typedef struct dpp_nppu_oam_cfg_txinfo_ram_init_done_t {
+	ZXIC_UINT32 txinfo_ram_init_done;
+} DPP_NPPU_OAM_CFG_TXINFO_RAM_INIT_DONE_T;
+
+typedef struct dpp_nppu_oam_cfg_fifo_status_int_status40_t {
+	ZXIC_UINT32 fifo_status_int_status40;
+} DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS40_T;
+
+typedef struct dpp_nppu_oam_cfg_fifo_status_int_status41_t {
+	ZXIC_UINT32 fifo_status_int_status41;
+} DPP_NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS41_T;
+
+typedef struct dpp_nppu_oam_cfg_oam_2544_fun_en_t {
+	ZXIC_UINT32 oam_2544_fun_en;
+} DPP_NPPU_OAM_CFG_OAM_2544_FUN_EN_T;
+
+typedef struct dpp_nppu_oam_cfg_oam_2544_stat_clr_t {
+	ZXIC_UINT32 oam_2544_stat_clr;
+} DPP_NPPU_OAM_CFG_OAM_2544_STAT_CLR_T;
+
+typedef struct dpp_nppu_oam_cfg_txdis_default_t {
+	ZXIC_UINT32 txdis_default;
+} DPP_NPPU_OAM_CFG_TXDIS_DEFAULT_T;
+
+typedef struct dpp_nppu_oam_cfg_txdis_default_en_t {
+	ZXIC_UINT32 txdis_default_en;
+} DPP_NPPU_OAM_CFG_TXDIS_DEFAULT_EN_T;
+
+typedef struct dpp_nppu_oam_cfg_tpbfd_firstchk_th_t {
+	ZXIC_UINT32 tpbfd_firstchk_th;
+} DPP_NPPU_OAM_CFG_TPBFD_FIRSTCHK_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_ethccm_firstchk_th_t {
+	ZXIC_UINT32 ethccm_firstchk_th;
+} DPP_NPPU_OAM_CFG_ETHCCM_FIRSTCHK_TH_T;
+
+typedef struct dpp_nppu_oam_cfg_tpccm_firstchk_th_t {
+	ZXIC_UINT32 tpccm_firstchk_th;
+} DPP_NPPU_OAM_CFG_TPCCM_FIRSTCHK_TH_T;
+
+typedef struct dpp_nppu_oam_stat_txstat_req_cnt_t {
+	ZXIC_UINT32 txstat_req_cnt;
+} DPP_NPPU_OAM_STAT_TXSTAT_REQ_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_chkstat_req_cnt_t {
+	ZXIC_UINT32 chkstat_req_cnt;
+} DPP_NPPU_OAM_STAT_CHKSTAT_REQ_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_stat_oam_fc_cnt_t {
+	ZXIC_UINT32 stat1_oam_fc_cnt;
+} DPP_NPPU_OAM_STAT_STAT_OAM_FC_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_bfdseq_req_cnt_t {
+	ZXIC_UINT32 bfdseq_req_cnt;
+} DPP_NPPU_OAM_STAT_BFDSEQ_REQ_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_lmcnt_req_cnt_t {
+	ZXIC_UINT32 lmcnt_req_cnt;
+} DPP_NPPU_OAM_STAT_LMCNT_REQ_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_stat_oam_lm_rsp_cnt_t {
+	ZXIC_UINT32 stat2_rsp_cnt;
+} DPP_NPPU_OAM_STAT_STAT_OAM_LM_RSP_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_stat_oam_lm_fc_cnt_t {
+	ZXIC_UINT32 stat2_oam_fc_cnt;
+} DPP_NPPU_OAM_STAT_STAT_OAM_LM_FC_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_se_req_cnt_t {
+	ZXIC_UINT32 se_req_cnt;
+} DPP_NPPU_OAM_STAT_SE_REQ_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_se_rsp_cnt_t {
+	ZXIC_UINT32 se_rsp_cnt;
+} DPP_NPPU_OAM_STAT_SE_RSP_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_se_oam_fc_cnt_t {
+	ZXIC_UINT32 se_oam_fc_cnt;
+} DPP_NPPU_OAM_STAT_SE_OAM_FC_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_oam_se_fc_cnt_t {
+	ZXIC_UINT32 oam_se_fc_cnt;
+} DPP_NPPU_OAM_STAT_OAM_SE_FC_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_oam_pktrx_sop_cnt_t {
+	ZXIC_UINT32 oam_pktrx_sop_cnt;
+} DPP_NPPU_OAM_STAT_OAM_PKTRX_SOP_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_oam_pktrx_eop_cnt_t {
+	ZXIC_UINT32 oam_pktrx_eop_cnt;
+} DPP_NPPU_OAM_STAT_OAM_PKTRX_EOP_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_pktrx_oam_fc_cnt_t {
+	ZXIC_UINT32 pktrx_oam_fc_cnt;
+} DPP_NPPU_OAM_STAT_PKTRX_OAM_FC_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_pktrx_oam_tst_fc_cnt_t {
+	ZXIC_UINT32 pktrx_oam_tst_fc_cnt;
+} DPP_NPPU_OAM_STAT_PKTRX_OAM_TST_FC_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_odma_oam_sop_cnt_t {
+	ZXIC_UINT32 odma_oam_sop_cnt;
+} DPP_NPPU_OAM_STAT_ODMA_OAM_SOP_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_odma_oam_eop_cnt_t {
+	ZXIC_UINT32 odma_oam_eop_cnt;
+} DPP_NPPU_OAM_STAT_ODMA_OAM_EOP_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_oam_odma_fc_cnt_t {
+	ZXIC_UINT32 oam_odma_fc_cnt;
+} DPP_NPPU_OAM_STAT_OAM_ODMA_FC_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_rec_ma_pkt_illegal_cnt_t {
+	ZXIC_UINT32 rec_ma_pkt_illegal_cnt;
+} DPP_NPPU_OAM_STAT_REC_MA_PKT_ILLEGAL_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_rec_rmep_pkt_illegal_cnt_t {
+	ZXIC_UINT32 rec_rmep_pkt_illegal_cnt;
+} DPP_NPPU_OAM_STAT_REC_RMEP_PKT_ILLEGAL_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_rec_eth_ais_pkt_cnt_t {
+	ZXIC_UINT32 rec_eth_ais_pkt_cnt;
+} DPP_NPPU_OAM_STAT_REC_ETH_AIS_PKT_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_rec_tp_ais_pkt_cnt_t {
+	ZXIC_UINT32 rec_tp_ais_pkt_cnt;
+} DPP_NPPU_OAM_STAT_REC_TP_AIS_PKT_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_rec_tp_csf_pkt_cnt_t {
+	ZXIC_UINT32 rec_tp_csf_pkt_cnt;
+} DPP_NPPU_OAM_STAT_REC_TP_CSF_PKT_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_rec_eth_level_defect_cnt_t {
+	ZXIC_UINT32 rec_eth_level_defect_cnt;
+} DPP_NPPU_OAM_STAT_REC_ETH_LEVEL_DEFECT_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_rec_eth_megid_defect_cnt_t {
+	ZXIC_UINT32 rec_eth_megid_defect_cnt;
+} DPP_NPPU_OAM_STAT_REC_ETH_MEGID_DEFECT_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_rec_eth_mepid_defect_cnt_t {
+	ZXIC_UINT32 rec_eth_mepid_defect_cnt;
+} DPP_NPPU_OAM_STAT_REC_ETH_MEPID_DEFECT_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_rec_eth_interval_defect_cnt_t {
+	ZXIC_UINT32 rec_eth_interval_defect_cnt;
+} DPP_NPPU_OAM_STAT_REC_ETH_INTERVAL_DEFECT_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_rec_sess_unenable_cnt_t {
+	ZXIC_UINT32 rec_sess_unenable_cnt;
+} DPP_NPPU_OAM_STAT_REC_SESS_UNENABLE_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_oam_2544_rd_pkt_cnt_t {
+	ZXIC_UINT32 oam_2544_rd_pkt_cnt;
+} DPP_NPPU_OAM_STAT_OAM_2544_RD_PKT_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_debug_cnt_clr_t {
+	ZXIC_UINT32 debug_cnt_clr;
+} DPP_NPPU_OAM_STAT_DEBUG_CNT_CLR_T;
+
+typedef struct dpp_nppu_oam_stat_oam_pktrx_catch_data_t {
+	ZXIC_UINT32 oam_pktrx_catch_data;
+} DPP_NPPU_OAM_STAT_OAM_PKTRX_CATCH_DATA_T;
+
+typedef struct dpp_nppu_oam_stat_odma_oam_catch_data_t {
+	ZXIC_UINT32 odma_oam_catch_data;
+} DPP_NPPU_OAM_STAT_ODMA_OAM_CATCH_DATA_T;
+
+typedef struct dpp_nppu_oam_stat_tst_session_tx_cnt_t {
+	ZXIC_UINT32 tst_session_tx_cnt;
+} DPP_NPPU_OAM_STAT_TST_SESSION_TX_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_tst_session_rx_cnt_t {
+	ZXIC_UINT32 tst_session_rx_cnt;
+} DPP_NPPU_OAM_STAT_TST_SESSION_RX_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_tstrx_lost_cnt_t {
+	ZXIC_UINT32 tstrx_lost_cnt;
+} DPP_NPPU_OAM_STAT_TSTRX_LOST_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_bfdseq_wr_cnt_t {
+	ZXIC_UINT32 bfdseq_wr_cnt;
+} DPP_NPPU_OAM_STAT_BFDSEQ_WR_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_bfdtime_wr_cnt_t {
+	ZXIC_UINT32 bfdtime_wr_cnt;
+} DPP_NPPU_OAM_STAT_BFDTIME_WR_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_lmcnt_wr_cnt_t {
+	ZXIC_UINT32 lmcnt_wr_cnt;
+} DPP_NPPU_OAM_STAT_LMCNT_WR_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_oam_fs_pkt_cnt_t {
+	ZXIC_UINT32 oam_fs_pkt_cnt;
+} DPP_NPPU_OAM_STAT_OAM_FS_PKT_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_oam_ma_fs_pkt_cnt_t {
+	ZXIC_UINT32 lmcnt_wr_cnt;
+} DPP_NPPU_OAM_STAT_OAM_MA_FS_PKT_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_rec_tp_level_defect_cnt_t {
+	ZXIC_UINT32 rec_tp_level_defect_cnt;
+} DPP_NPPU_OAM_STAT_REC_TP_LEVEL_DEFECT_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_rec_tp_megid_defect_cnt_t {
+	ZXIC_UINT32 rec_tp_megid_defect_cnt;
+} DPP_NPPU_OAM_STAT_REC_TP_MEGID_DEFECT_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_rec_tp_mepid_defect_cnt_t {
+	ZXIC_UINT32 rec_tp_mepid_defect_cnt;
+} DPP_NPPU_OAM_STAT_REC_TP_MEPID_DEFECT_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_rec_tp_interval_defect_cnt_t {
+	ZXIC_UINT32 rec_tp_interval_defect_cnt;
+} DPP_NPPU_OAM_STAT_REC_TP_INTERVAL_DEFECT_CNT_T;
+
+typedef struct dpp_nppu_oam_stat_rd_reg_clear_mode_t {
+	ZXIC_UINT32 rd_clear_mode_cfg;
+} DPP_NPPU_OAM_STAT_RD_REG_CLEAR_MODE_T;
+
+typedef struct dpp_nppu_oam_stat_rd_data_reg_clear_mode_t {
+	ZXIC_UINT32 rd_data_reg_clear_mode_cfg;
+} DPP_NPPU_OAM_STAT_RD_DATA_REG_CLEAR_MODE_T;
+
+typedef struct dpp_nppu_oam_cfg_indir_oam_int_status_ram_0_t {
+	ZXIC_UINT32 bfd_diag_value_bit4;
+	ZXIC_UINT32 bfd_diag_value_bit3;
+	ZXIC_UINT32 bfd_diag_value_bit2;
+	ZXIC_UINT32 bfd_diag_value_bit1;
+	ZXIC_UINT32 bfd_diag_value_bit0;
+	ZXIC_UINT32 dloc_int;
+	ZXIC_UINT32 drdi_int;
+} DPP_NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM_0_T;
+
+typedef struct dpp_nppu_oam_cfg_indir_oam_int_status_ram1_t {
+	ZXIC_UINT32 sticky_error_level_defect;
+	ZXIC_UINT32 sticky_error_megid_defect;
+	ZXIC_UINT32 sticky_error_mepid_defect;
+	ZXIC_UINT32 sticky_error_inter_defect;
+	ZXIC_UINT32 sticky_ais_defect;
+	ZXIC_UINT32 sticky_csf_defect;
+	ZXIC_UINT32 current_error_level_defect;
+	ZXIC_UINT32 current_error_megid_defect;
+	ZXIC_UINT32 current_error_mepid_defect;
+	ZXIC_UINT32 current_error_inter_defect;
+	ZXIC_UINT32 current_ais_defect;
+	ZXIC_UINT32 current_csf_defect;
+} DPP_NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM1_T;
+
+typedef struct dpp_nppu_oam_cfg_indir_tst_pkt_tx_para_ram_t {
+	ZXIC_UINT32 ddr_self_test_tx_en;
+	ZXIC_UINT32 tm_self_test_tx_en;
+	ZXIC_UINT32 fast_aging_tx_en;
+	ZXIC_UINT32 timing_aging_tx_en;
+	ZXIC_UINT32 backgroud_flow_tx_en;
+	ZXIC_UINT32 tsttx_session_en;
+	ZXIC_UINT32 tx_freq;
+	ZXIC_UINT32 tx_offset;
+	ZXIC_UINT32 tx_count;
+	ZXIC_UINT32 fast_tx_mode_en;
+	ZXIC_UINT32 tsttx_pkthead_len;
+	ZXIC_UINT32 tsttx_interval;
+} DPP_NPPU_OAM_CFG_INDIR_TST_PKT_TX_PARA_RAM_T;
+
+typedef struct dpp_nppu_oam_cfg_indir_groupnumram_t {
+	ZXIC_UINT32 mep_down_num;
+} DPP_NPPU_OAM_CFG_INDIR_GROUPNUMRAM_T;
+
+typedef struct dpp_nppu_oam_cfg_indir_oam_tx_tbl_ram_t {
+	ZXIC_UINT32 oam_tx_en;
+	ZXIC_UINT32 oam_tx_type;
+	ZXIC_UINT32 oam_fetch_len;
+	ZXIC_UINT32 bfd_seq_tx_en;
+	ZXIC_UINT32 tx_para;
+	ZXIC_UINT32 oam_tx_interval;
+	ZXIC_UINT32 hd_ena_flag;
+	ZXIC_UINT32 last_tx_time;
+} DPP_NPPU_OAM_CFG_INDIR_OAM_TX_TBL_RAM_T;
+
+typedef struct dpp_nppu_oam_cfg_indir_oam_chk_tbl_ram_t {
+	ZXIC_UINT32 fast_switch_en;
+	ZXIC_UINT32 oam_chk_en;
+	ZXIC_UINT32 oam_chk_type;
+	ZXIC_UINT32 ccm_predel_flag;
+	ZXIC_UINT32 lm_chk_en;
+	ZXIC_UINT32 ccm_group_id;
+	ZXIC_UINT32 oam_chk_internal;
+	ZXIC_UINT32 fist_chk_flag;
+	ZXIC_UINT32 last_chk_time;
+} DPP_NPPU_OAM_CFG_INDIR_OAM_CHK_TBL_RAM_T;
+
+typedef struct dpp_nppu_oam_cfg_indir_oam_ma_chk_tbl_ram_t {
+	ZXIC_UINT32 ma_fast_switch_en;
+	ZXIC_UINT32 ma_chk_en;
+	ZXIC_UINT32 ma_type;
+	ZXIC_UINT32 error_level_defect_en;
+	ZXIC_UINT32 error_megid_defect_en;
+	ZXIC_UINT32 error_mepid_defect_en;
+	ZXIC_UINT32 error_inter_defect_en;
+	ZXIC_UINT32 ais_defect_en;
+	ZXIC_UINT32 csf_defect_en;
+	ZXIC_UINT32 error_level_defect_ccm;
+	ZXIC_UINT32 error_megid_defect_ccm;
+	ZXIC_UINT32 error_mepid_defect_ccm;
+	ZXIC_UINT32 error_inter_defect_ccm;
+	ZXIC_UINT32 ais_defect_ccm;
+	ZXIC_UINT32 csf_defect_ccm;
+	ZXIC_UINT32 ma_predel_en;
+	ZXIC_UINT32 error_level_defect_ts;
+	ZXIC_UINT32 error_megid_defect_ts;
+	ZXIC_UINT32 error_mepid_defect_ts;
+	ZXIC_UINT32 error_inter_defect_ts;
+	ZXIC_UINT32 ais_defect_ts;
+	ZXIC_UINT32 csf_defect_ts;
+} DPP_NPPU_OAM_CFG_INDIR_OAM_MA_CHK_TBL_RAM_T;
+
+typedef struct dpp_nppu_oam_cfg_indir_oam_2544_tx_ram_t {
+	ZXIC_UINT32 tx_en_2544;
+	ZXIC_UINT32 tx_cfg_times_2544;
+	ZXIC_UINT32 current_times;
+	ZXIC_UINT32 slice_num;
+	ZXIC_UINT32 pkt_mty;
+} DPP_NPPU_OAM_CFG_INDIR_OAM_2544_TX_RAM_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_pci.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_pci.h
old mode 100755
new mode 100644
index 7d8a02761ec00378a56098ebdb82556ff1a66aaa..1e2125ed1ff6d11e768bcd3e8df87e51a45dc451
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_pci.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_pci.h
@@ -27,8 +27,10 @@ extern "C" {
 #include "dpp_dev.h"
 #include "dpp_module.h"
 
-ZXIC_UINT32 dpp_pci_write32(DPP_DEV_T *dev, ZXIC_ADDR_T abs_addr, ZXIC_UINT32 *p_data);
-ZXIC_UINT32 dpp_pci_read32(DPP_DEV_T *dev, ZXIC_ADDR_T  abs_addr, ZXIC_UINT32 *p_data);
+ZXIC_UINT32 dpp_pci_write32(DPP_DEV_T *dev, ZXIC_ADDR_T abs_addr,
+							ZXIC_UINT32 *p_data);
+ZXIC_UINT32 dpp_pci_read32(DPP_DEV_T *dev, ZXIC_ADDR_T abs_addr,
+						   ZXIC_UINT32 *p_data);
 
 #ifdef __cplusplus
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ppu4k_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ppu4k_reg.h
index 468a04296166187b137072358d8ee2a333962cd6..81e5b270e44ca3db8acddf1236e0659350d70a3d 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ppu4k_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ppu4k_reg.h
@@ -3,43 +3,35 @@
 #define _DPP_PPU4K_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_ppu4k_cluster_wr_high_data_r_mex_t
-{
-    ZXIC_UINT32 wr_high_data_r_mex;
-}DPP_PPU4K_CLUSTER_WR_HIGH_DATA_R_MEX_T;
+typedef struct dpp_ppu4k_cluster_wr_high_data_r_mex_t {
+	ZXIC_UINT32 wr_high_data_r_mex;
+} DPP_PPU4K_CLUSTER_WR_HIGH_DATA_R_MEX_T;
 
-typedef struct dpp_ppu4k_cluster_wr_low_data_r_mex_t
-{
-    ZXIC_UINT32 wr_low_data_r_mex;
-}DPP_PPU4K_CLUSTER_WR_LOW_DATA_R_MEX_T;
+typedef struct dpp_ppu4k_cluster_wr_low_data_r_mex_t {
+	ZXIC_UINT32 wr_low_data_r_mex;
+} DPP_PPU4K_CLUSTER_WR_LOW_DATA_R_MEX_T;
 
-typedef struct dpp_ppu4k_cluster_addr_r_mex_t
-{
-    ZXIC_UINT32 operate_type;
-    ZXIC_UINT32 addr_r_mex;
-}DPP_PPU4K_CLUSTER_ADDR_R_MEX_T;
+typedef struct dpp_ppu4k_cluster_addr_r_mex_t {
+	ZXIC_UINT32 operate_type;
+	ZXIC_UINT32 addr_r_mex;
+} DPP_PPU4K_CLUSTER_ADDR_R_MEX_T;
 
-typedef struct dpp_ppu4k_cluster_sdt_tbl_ind_access_done_t
-{
-    ZXIC_UINT32 rd_addr_r_mex;
-}DPP_PPU4K_CLUSTER_SDT_TBL_IND_ACCESS_DONE_T;
+typedef struct dpp_ppu4k_cluster_sdt_tbl_ind_access_done_t {
+	ZXIC_UINT32 rd_addr_r_mex;
+} DPP_PPU4K_CLUSTER_SDT_TBL_IND_ACCESS_DONE_T;
 
-typedef struct dpp_ppu4k_cluster_rd_high_data_r_mex_t
-{
-    ZXIC_UINT32 rd_high_data_r_mex;
-}DPP_PPU4K_CLUSTER_RD_HIGH_DATA_R_MEX_T;
-
-typedef struct dpp_ppu4k_cluster_rd_low_data_r_mex_t
-{
-    ZXIC_UINT32 rd_low_data_r_mex;
-}DPP_PPU4K_CLUSTER_RD_LOW_DATA_R_MEX_T;
+typedef struct dpp_ppu4k_cluster_rd_high_data_r_mex_t {
+	ZXIC_UINT32 rd_high_data_r_mex;
+} DPP_PPU4K_CLUSTER_RD_HIGH_DATA_R_MEX_T;
 
+typedef struct dpp_ppu4k_cluster_rd_low_data_r_mex_t {
+	ZXIC_UINT32 rd_low_data_r_mex;
+} DPP_PPU4K_CLUSTER_RD_LOW_DATA_R_MEX_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ppu_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ppu_reg.h
index c604dc896daa74e128b869624ae2829c24401ef0..a3bae3d5548a30861d20ab1de3cf9115252e3d6b 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ppu_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ppu_reg.h
@@ -3,4306 +3,3603 @@
 #define _DPP_PPU_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_ppu_ppu_test_r_t
-{
-    ZXIC_UINT32 test_r;
-}DPP_PPU_PPU_TEST_R_T;
-
-typedef struct dpp_ppu_ppu_ppu_debug_en_r_t
-{
-    ZXIC_UINT32 debug_en_r;
-}DPP_PPU_PPU_PPU_DEBUG_EN_R_T;
-
-typedef struct dpp_ppu_ppu_csr_dup_table_wr_data_t
-{
-    ZXIC_UINT32 item_vld;
-    ZXIC_UINT32 flownum_vld;
-    ZXIC_UINT32 start_pc;
-    ZXIC_UINT32 flownum;
-}DPP_PPU_PPU_CSR_DUP_TABLE_WR_DATA_T;
-
-typedef struct dpp_ppu_ppu_csr_dup_table_rd_data_t
-{
-    ZXIC_UINT32 item_vld;
-    ZXIC_UINT32 flownum_vld;
-    ZXIC_UINT32 start_pc;
-    ZXIC_UINT32 flownum;
-}DPP_PPU_PPU_CSR_DUP_TABLE_RD_DATA_T;
-
-typedef struct dpp_ppu_ppu_csr_dup_table_addr_t
-{
-    ZXIC_UINT32 csr_dup_table_operation;
-    ZXIC_UINT32 csr_dup_table_addr;
-}DPP_PPU_PPU_CSR_DUP_TABLE_ADDR_T;
-
-typedef struct dpp_ppu_ppu_ppu_debug_vld_t
-{
-    ZXIC_UINT32 ppu_debug_vld;
-}DPP_PPU_PPU_PPU_DEBUG_VLD_T;
-
-typedef struct dpp_ppu_ppu_cop_thash_rsk_319_288_t
-{
-    ZXIC_UINT32 rsk_319_288;
-}DPP_PPU_PPU_COP_THASH_RSK_319_288_T;
-
-typedef struct dpp_ppu_ppu_cop_thash_rsk_287_256_t
-{
-    ZXIC_UINT32 rsk_287_256;
-}DPP_PPU_PPU_COP_THASH_RSK_287_256_T;
-
-typedef struct dpp_ppu_ppu_cop_thash_rsk_255_224_t
-{
-    ZXIC_UINT32 rsk_255_224;
-}DPP_PPU_PPU_COP_THASH_RSK_255_224_T;
-
-typedef struct dpp_ppu_ppu_cop_thash_rsk_223_192_t
-{
-    ZXIC_UINT32 rsk_223_192;
-}DPP_PPU_PPU_COP_THASH_RSK_223_192_T;
-
-typedef struct dpp_ppu_ppu_cop_thash_rsk_191_160_t
-{
-    ZXIC_UINT32 rsk_191_160;
-}DPP_PPU_PPU_COP_THASH_RSK_191_160_T;
-
-typedef struct dpp_ppu_ppu_cop_thash_rsk_159_128_t
-{
-    ZXIC_UINT32 rsk_159_128;
-}DPP_PPU_PPU_COP_THASH_RSK_159_128_T;
-
-typedef struct dpp_ppu_ppu_cop_thash_rsk_127_096_t
-{
-    ZXIC_UINT32 rsk_127_096;
-}DPP_PPU_PPU_COP_THASH_RSK_127_096_T;
-
-typedef struct dpp_ppu_ppu_cop_thash_rsk_095_064_t
-{
-    ZXIC_UINT32 rsk_095_064;
-}DPP_PPU_PPU_COP_THASH_RSK_095_064_T;
-
-typedef struct dpp_ppu_ppu_cop_thash_rsk_063_032_t
-{
-    ZXIC_UINT32 rsk_063_032;
-}DPP_PPU_PPU_COP_THASH_RSK_063_032_T;
-
-typedef struct dpp_ppu_ppu_cop_thash_rsk_031_000_t
-{
-    ZXIC_UINT32 rsk_031_000;
-}DPP_PPU_PPU_COP_THASH_RSK_031_000_T;
-
-typedef struct dpp_ppu_ppu_cfg_ipv4_ipid_start_value_t
-{
-    ZXIC_UINT32 cfg_ipv4_ipid_start_value;
-}DPP_PPU_PPU_CFG_IPV4_IPID_START_VALUE_T;
-
-typedef struct dpp_ppu_ppu_cfg_ipv4_ipid_end_value_t
-{
-    ZXIC_UINT32 cfg_ipv4_ipid_end_value;
-}DPP_PPU_PPU_CFG_IPV4_IPID_END_VALUE_T;
-
-typedef struct dpp_ppu_ppu_cluster_mf_in_en_t
-{
-    ZXIC_UINT32 cluster_mf_in_en;
-}DPP_PPU_PPU_CLUSTER_MF_IN_EN_T;
-
-typedef struct dpp_ppu_ppu_ppu_empty_t
-{
-    ZXIC_UINT32 ppu_empty;
-}DPP_PPU_PPU_PPU_EMPTY_T;
-
-typedef struct dpp_ppu_ppu_instrmem_w_addr_t
-{
-    ZXIC_UINT32 instrmem_w_addr;
-}DPP_PPU_PPU_INSTRMEM_W_ADDR_T;
-
-typedef struct dpp_ppu_ppu_instrmem_w_data_191_160_t
-{
-    ZXIC_UINT32 instrmem_w_data_191_160;
-}DPP_PPU_PPU_INSTRMEM_W_DATA_191_160_T;
-
-typedef struct dpp_ppu_ppu_instrmem_w_data_159_128_t
-{
-    ZXIC_UINT32 instrmem_w_data_159_128;
-}DPP_PPU_PPU_INSTRMEM_W_DATA_159_128_T;
-
-typedef struct dpp_ppu_ppu_instrmem_w_data_127_96_t
-{
-    ZXIC_UINT32 instrmem_w_data_127_96;
-}DPP_PPU_PPU_INSTRMEM_W_DATA_127_96_T;
-
-typedef struct dpp_ppu_ppu_instrmem_w_data_95_64_t
-{
-    ZXIC_UINT32 instrmem_w_data_95_64;
-}DPP_PPU_PPU_INSTRMEM_W_DATA_95_64_T;
-
-typedef struct dpp_ppu_ppu_instrmem_w_data_63_32_t
-{
-    ZXIC_UINT32 instrmem_w_data_63_32;
-}DPP_PPU_PPU_INSTRMEM_W_DATA_63_32_T;
-
-typedef struct dpp_ppu_ppu_instrmem_w_data_31_0_t
-{
-    ZXIC_UINT32 instrmem_w_data_31_0;
-}DPP_PPU_PPU_INSTRMEM_W_DATA_31_0_T;
-
-typedef struct dpp_ppu_ppu_isu_fwft_mf_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 isu_fwft_mf_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_isu_fwft_mf_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 isu_fwft_mf_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_int_1200m_mask_t
-{
-    ZXIC_UINT32 me7_interrupt_mask;
-    ZXIC_UINT32 me6_interrupt_mask;
-    ZXIC_UINT32 me5_interrupt_mask;
-    ZXIC_UINT32 me4_interrupt_mask;
-    ZXIC_UINT32 me3_interrupt_mask;
-    ZXIC_UINT32 me2_interrupt_mask;
-    ZXIC_UINT32 me1_interrupt_mask;
-    ZXIC_UINT32 me0_interrupt_mask;
-}DPP_PPU_CLUSTER_INT_1200M_MASK_T;
-
-typedef struct dpp_ppu_ppu_interrupt_en_r_t
-{
-    ZXIC_UINT32 interrupt_en_r;
-}DPP_PPU_PPU_INTERRUPT_EN_R_T;
-
-typedef struct dpp_ppu_ppu_mec_host_interrupt_t
-{
-    ZXIC_UINT32 mec_host_interrupt;
-}DPP_PPU_PPU_MEC_HOST_INTERRUPT_T;
-
-typedef struct dpp_ppu_ppu_dbg_rtl_date_t
-{
-    ZXIC_UINT32 dbg_rtl_date;
-}DPP_PPU_PPU_DBG_RTL_DATE_T;
-
-typedef struct dpp_ppu_ppu_dup_start_num_cfg_t
-{
-    ZXIC_UINT32 dup_start_num_cfg;
-}DPP_PPU_PPU_DUP_START_NUM_CFG_T;
-
-typedef struct dpp_ppu_ppu_debug_data_write_complete_t
-{
-    ZXIC_UINT32 debug_data_write_complete;
-}DPP_PPU_PPU_DEBUG_DATA_WRITE_COMPLETE_T;
-
-typedef struct dpp_ppu_ppu_uc_mc_wrr_cfg_t
-{
-    ZXIC_UINT32 uc_mc_wrr_cfg;
-}DPP_PPU_PPU_UC_MC_WRR_CFG_T;
-
-typedef struct dpp_ppu_ppu_debug_pkt_send_en_t
-{
-    ZXIC_UINT32 debug_pkt_send_en;
-}DPP_PPU_PPU_DEBUG_PKT_SEND_EN_T;
-
-typedef struct dpp_ppu_ppu_dup_tbl_ind_access_done_t
-{
-    ZXIC_UINT32 dup_tbl_ind_access_done;
-}DPP_PPU_PPU_DUP_TBL_IND_ACCESS_DONE_T;
-
-typedef struct dpp_ppu_ppu_isu_ppu_demux_fifo_interrupt_mask_t
-{
-    ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_underflow_mask;
-}DPP_PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_MASK_T;
-
-typedef struct dpp_ppu_ppu_ppu_multicast_fifo_interrupt_mask_t
-{
-    ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 car_flag_fifo_32x1_wrapper_overflow_mask;
-    ZXIC_UINT32 car_flag_fifo_32x1_wrapper_underflow_mask;
-}DPP_PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_MASK_T;
-
-typedef struct dpp_ppu_ppu_ppu_in_schedule_fifo_interrupt_mask_t
-{
-    ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_underflow_mask;
-}DPP_PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_MASK_T;
-
-typedef struct dpp_ppu_ppu_ppu_mf_out_fifo_interrupt_mask_t
-{
-    ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_mask;
-}DPP_PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_MASK_T;
-
-typedef struct dpp_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_mask_t
-{
-    ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask;
-}DPP_PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_MASK_T;
-
-typedef struct dpp_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_mask_t
-{
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_mask;
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_mask;
-}DPP_PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_MASK_T;
-
-typedef struct dpp_ppu_ppu_ppu_mccnt_fifo_interrupt_mask_t
-{
-    ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_underflow_mask;
-}DPP_PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_MASK_T;
-
-typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_mask_l_t
-{
-    ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask;
-}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_L_T;
-
-typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_mask_m_t
-{
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_mask;
-    ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask;
-    ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask;
-    ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask;
-}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_M_T;
-
-typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_mask_h_t
-{
-    ZXIC_UINT32 coprocessor_fwft_fifo_16x80_wrapper_overflow_mask;
-    ZXIC_UINT32 coprocessor_fwft_fifo_16x80_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_mask;
-}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_H_T;
-
-typedef struct dpp_ppu_ppu_ppu_ram_check_err_mask_t
-{
-    ZXIC_UINT32 parity_err_mask;
-}DPP_PPU_PPU_PPU_RAM_CHECK_ERR_MASK_T;
-
-typedef struct dpp_ppu_ppu_instrmem_fifo_interrupt_mask_t
-{
-    ZXIC_UINT32 instrmem2_wr_fifo_ovf_mask;
-    ZXIC_UINT32 instrmem2_wr_fifo_udf_mask;
-    ZXIC_UINT32 instrmem2_rd_fifo_ovf_mask;
-    ZXIC_UINT32 instrmem2_rd_fifo_udf_mask;
-    ZXIC_UINT32 instrmem1_wr_fifo_ovf_mask;
-    ZXIC_UINT32 instrmem1_wr_fifo_udf_mask;
-    ZXIC_UINT32 instrmem1_rd_fifo_ovf_mask;
-    ZXIC_UINT32 instrmem1_rd_fifo_udf_mask;
-    ZXIC_UINT32 instrmem0_wr_fifo_ovf_mask;
-    ZXIC_UINT32 instrmem0_wr_fifo_udf_mask;
-    ZXIC_UINT32 instrmem0_rd_fifo_ovf_mask;
-    ZXIC_UINT32 instrmem0_rd_fifo_udf_mask;
-}DPP_PPU_PPU_INSTRMEM_FIFO_INTERRUPT_MASK_T;
-
-typedef struct dpp_ppu_ppu_isu_ppu_demux_fifo_interrupt_sta_t
-{
-    ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_sta;
-    ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_underflow_sta;
-}DPP_PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_STA_T;
-
-typedef struct dpp_ppu_ppu_ppu_multicast_fifo_interrupt_sta_t
-{
-    ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_sta;
-    ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_underflow_sta;
-    ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_sta;
-    ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_underflow_sta;
-    ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_sta;
-    ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_underflow_sta;
-    ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_underflow_sta;
-    ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_sta;
-    ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_sta;
-    ZXIC_UINT32 car_flag_fifo_32x1_wrapper_overflow_sta;
-    ZXIC_UINT32 car_flag_fifo_32x1_wrapper_underflow_sta;
-}DPP_PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_STA_T;
-
-typedef struct dpp_ppu_ppu_ppu_in_schedule_fifo_interrupt_sta_t
-{
-    ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_sta;
-    ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_underflow_sta;
-    ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_underflow_sta;
-}DPP_PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_STA_T;
-
-typedef struct dpp_ppu_ppu_ppu_mf_out_fifo_interrupt_sta_t
-{
-    ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_sta;
-}DPP_PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_STA_T;
-
-typedef struct dpp_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_sta_t
-{
-    ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta;
-}DPP_PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_STA_T;
-
-typedef struct dpp_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_sta_t
-{
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_sta;
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_sta;
-}DPP_PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_STA_T;
-
-typedef struct dpp_ppu_ppu_ppu_mccnt_fifo_interrupt_sta_t
-{
-    ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_underflow_sta;
-    ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_sta;
-    ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_underflow_sta;
-}DPP_PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_STA_T;
-
-typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_sta_l_t
-{
-    ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta;
-}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_L_T;
-
-typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_sta_m_t
-{
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_sta;
-    ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta;
-    ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta;
-    ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta;
-}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_M_T;
-
-typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_sta_h_t
-{
-    ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_sta;
-}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_H_T;
-
-typedef struct dpp_ppu_ppu_instrmem_fifo_interrupt_sta_t
-{
-    ZXIC_UINT32 instrmem1_wr_fifo_ovf_sta;
-    ZXIC_UINT32 instrmem1_wr_fifo_udf_sta;
-    ZXIC_UINT32 instrmem1_rd_fifo_ovf_sta;
-    ZXIC_UINT32 instrmem1_rd_fifo_udf_sta;
-    ZXIC_UINT32 instrmem0_wr_fifo_ovf_sta;
-    ZXIC_UINT32 instrmem0_wr_fifo_udf_sta;
-    ZXIC_UINT32 instrmem0_rd_fifo_ovf_sta;
-    ZXIC_UINT32 instrmem0_rd_fifo_udf_sta;
-}DPP_PPU_PPU_INSTRMEM_FIFO_INTERRUPT_STA_T;
-
-typedef struct dpp_ppu_ppu_ppu_ram_check_ecc_err_flag_1_t
-{
-    ZXIC_UINT32 ecc_single_err_sa_para_fifo_int_flag;
-    ZXIC_UINT32 ecc_double_err_sa_para_fifo_int_flag;
-    ZXIC_UINT32 ecc_single_err_dup_para_fifo_int_flag;
-    ZXIC_UINT32 ecc_double_err_dup_para_fifo_int_flag;
-    ZXIC_UINT32 ecc_single_err_pf_rsp_fifo_int_flag;
-    ZXIC_UINT32 ecc_double_err_pf_rsp_fifo_int_flag;
-    ZXIC_UINT32 ecc_single_err_pf_req_fifo_int_flag;
-    ZXIC_UINT32 ecc_double_err_pf_req_fifo_int_flag;
-    ZXIC_UINT32 ecc_single_err_ppu_reorder_link_ram0_int_flag;
-    ZXIC_UINT32 ecc_double_err_ppu_reorder_link_ram0_int_flag;
-    ZXIC_UINT32 ecc_single_err_ppu_reorder_link_ram1_int_flag;
-    ZXIC_UINT32 ecc_double_err_ppu_reorder_link_ram1_int_flag;
-    ZXIC_UINT32 ecc_single_err_ppu_reorder_link_flag_array_ram0_int_flag;
-    ZXIC_UINT32 ecc_single_err_ppu_reorder_link_flag_array_ram1_int_flag;
-    ZXIC_UINT32 ecc_single_err_ppu_reorder_ifb_ram_int_flag;
-    ZXIC_UINT32 ecc_double_err_ppu_reorder_ifb_ram_int_flag;
-    ZXIC_UINT32 ecc_single_err_ppu_reorder_flag_array_ram0_int_flag;
-    ZXIC_UINT32 ecc_single_err_ppu_reorder_flag_array_ram1_int_flag;
-    ZXIC_UINT32 ecc_single_err_ppu_reorder_flag_ram0_int_flag;
-    ZXIC_UINT32 ecc_single_err_ppu_reorder_flag_ram1_int_flag;
-    ZXIC_UINT32 ecc_single_err_uc_mf_fifo_int_flag;
-    ZXIC_UINT32 ecc_double_err_uc_mf_fifo_int_flag;
-    ZXIC_UINT32 ecc_single_err_mc_mf_fifo_int_flag;
-    ZXIC_UINT32 ecc_double_err_mc_mf_fifo_int_flag;
-    ZXIC_UINT32 ecc_single_err_free_global_num_fifo_int_flag;
-    ZXIC_UINT32 ecc_double_err_free_global_num_fifo_int_flag;
-}DPP_PPU_PPU_PPU_RAM_CHECK_ECC_ERR_FLAG_1_T;
-
-typedef struct dpp_ppu_ppu_isu_ppu_demux_fifo_interrupt_flag_t
-{
-    ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_underflow_flag;
-}DPP_PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_FLAG_T;
-
-typedef struct dpp_ppu_ppu_ppu_multicast_fifo_interrupt_flag_t
-{
-    ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 car_flag_fifo_32x1_wrapper_overflow_flag;
-    ZXIC_UINT32 car_flag_fifo_32x1_wrapper_underflow_flag;
-}DPP_PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_FLAG_T;
-
-typedef struct dpp_ppu_ppu_ppu_in_schedule_fifo_interrupt_flag_t
-{
-    ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_underflow_flag;
-}DPP_PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_FLAG_T;
-
-typedef struct dpp_ppu_ppu_ppu_mf_out_fifo_interrupt_flag_t
-{
-    ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_flag;
-}DPP_PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_FLAG_T;
-
-typedef struct dpp_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_flag_t
-{
-    ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag;
-}DPP_PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_FLAG_T;
-
-typedef struct dpp_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_flag_t
-{
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_flag;
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_flag;
-}DPP_PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_FLAG_T;
-
-typedef struct dpp_ppu_ppu_ppu_mccnt_fifo_interrupt_flag_t
-{
-    ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_underflow_flag;
-}DPP_PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_FLAG_T;
-
-typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_flag_l_t
-{
-    ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flag;
-    ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flag;
-    ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;
-    ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;
-    ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flag;
-    ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flag;
-    ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;
-    ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag;
-    ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flag;
-    ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flag;
-    ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;
-    ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;
-    ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flag;
-    ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flag;
-    ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;
-    ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag;
-    ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flag;
-    ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flag;
-    ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;
-    ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;
-    ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flag;
-    ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flag;
-    ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;
-    ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag;
-    ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flag;
-    ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flag;
-    ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;
-    ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;
-    ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flag;
-    ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flag;
-    ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;
-    ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag;
-}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_L_T;
-
-typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_flag_m_t
-{
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_flag;
-    ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flag;
-    ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flag;
-    ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;
-    ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;
-    ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flag;
-    ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flag;
-    ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;
-    ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag;
-    ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flag;
-    ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flag;
-    ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;
-    ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;
-    ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flag;
-    ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flag;
-    ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;
-    ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag;
-}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_M_T;
-
-typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_flag_h_t
-{
-    ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_flag;
-}DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_H_T;
-
-typedef struct dpp_ppu_ppu_instrmem_fifo_interrupt_flag_t
-{
-    ZXIC_UINT32 instrmem2_wr_fifo_ovf_flag;
-    ZXIC_UINT32 instrmem2_wr_fifo_udf_flag;
-    ZXIC_UINT32 instrmem2_rd_fifo_ovf_flag;
-    ZXIC_UINT32 instrmem2_rd_fifo_udf_flag;
-    ZXIC_UINT32 instrmem1_wr_fifo_ovf_flag;
-    ZXIC_UINT32 instrmem1_wr_fifo_udf_flag;
-    ZXIC_UINT32 instrmem1_rd_fifo_ovf_flag;
-    ZXIC_UINT32 instrmem1_rd_fifo_udf_flag;
-    ZXIC_UINT32 instrmem0_wr_fifo_ovf_flag;
-    ZXIC_UINT32 instrmem0_wr_fifo_udf_flag;
-    ZXIC_UINT32 instrmem0_rd_fifo_ovf_flag;
-    ZXIC_UINT32 instrmem0_rd_fifo_udf_flag;
-}DPP_PPU_PPU_INSTRMEM_FIFO_INTERRUPT_FLAG_T;
-
-typedef struct dpp_ppu_ppu_instrmem_ram_int_out_t
-{
-    ZXIC_UINT32 instrmem2_bank3_ram_parity_err_int_out;
-    ZXIC_UINT32 instrmem2_bank2_ram_parity_err_int_out;
-    ZXIC_UINT32 instrmem2_bank1_ram_parity_err_int_out;
-    ZXIC_UINT32 instrmem2_bank0_ram_parity_err_int_out;
-    ZXIC_UINT32 instrmem1_bank3_ram_parity_err_int_out;
-    ZXIC_UINT32 instrmem1_bank2_ram_parity_err_int_out;
-    ZXIC_UINT32 instrmem1_bank1_ram_parity_err_int_out;
-    ZXIC_UINT32 instrmem1_bank0_ram_parity_err_int_out;
-    ZXIC_UINT32 instrmem0_bank3_ram_parity_err_int_out;
-    ZXIC_UINT32 instrmem0_bank2_ram_parity_err_int_out;
-    ZXIC_UINT32 instrmem0_bank1_ram_parity_err_int_out;
-    ZXIC_UINT32 instrmem0_bank0_ram_parity_err_int_out;
-}DPP_PPU_PPU_INSTRMEM_RAM_INT_OUT_T;
-
-typedef struct dpp_ppu_ppu_instrmem_ram_int_mask_t
-{
-    ZXIC_UINT32 instrmem2_bank3_ram_parity_err_mask;
-    ZXIC_UINT32 instrmem2_bank2_ram_parity_err_mask;
-    ZXIC_UINT32 instrmem2_bank1_ram_parity_err_mask;
-    ZXIC_UINT32 instrmem2_bank0_ram_parity_err_mask;
-    ZXIC_UINT32 instrmem1_bank3_ram_parity_err_mask;
-    ZXIC_UINT32 instrmem1_bank2_ram_parity_err_mask;
-    ZXIC_UINT32 instrmem1_bank1_ram_parity_err_mask;
-    ZXIC_UINT32 instrmem1_bank0_ram_parity_err_mask;
-    ZXIC_UINT32 instrmem0_bank3_ram_parity_err_mask;
-    ZXIC_UINT32 instrmem0_bank2_ram_parity_err_mask;
-    ZXIC_UINT32 instrmem0_bank1_ram_parity_err_mask;
-    ZXIC_UINT32 instrmem0_bank0_ram_parity_err_mask;
-}DPP_PPU_PPU_INSTRMEM_RAM_INT_MASK_T;
-
-typedef struct dpp_ppu_ppu_instrmem_ram_int_stat_t
-{
-    ZXIC_UINT32 instrmem2_bank3_ram_parity_errstat;
-    ZXIC_UINT32 instrmem2_bank2_ram_parity_errstat;
-    ZXIC_UINT32 instrmem2_bank1_ram_parity_errstat;
-    ZXIC_UINT32 instrmem2_bank0_ram_parity_errstat;
-    ZXIC_UINT32 instrmem1_bank3_ram_parity_errstat;
-    ZXIC_UINT32 instrmem1_bank2_ram_parity_errstat;
-    ZXIC_UINT32 instrmem1_bank1_ram_parity_errstat;
-    ZXIC_UINT32 instrmem1_bank0_ram_parity_errstat;
-    ZXIC_UINT32 instrmem0_bank3_ram_parity_errstat;
-    ZXIC_UINT32 instrmem0_bank2_ram_parity_errstat;
-    ZXIC_UINT32 instrmem0_bank1_ram_parity_errstat;
-    ZXIC_UINT32 instrmem0_bank0_ram_parity_errstat;
-}DPP_PPU_PPU_INSTRMEM_RAM_INT_STAT_T;
-
-typedef struct dpp_ppu_ppu_instrmem_ram_int_flag_t
-{
-    ZXIC_UINT32 instrmem2_bank3_ram_parity_err_flag;
-    ZXIC_UINT32 instrmem2_bank2_ram_parity_err_flag;
-    ZXIC_UINT32 instrmem2_bank1_ram_parity_err_flag;
-    ZXIC_UINT32 instrmem2_bank0_ram_parity_err_flag;
-    ZXIC_UINT32 instrmem1_bank3_ram_parity_err_flag;
-    ZXIC_UINT32 instrmem1_bank2_ram_parity_err_flag;
-    ZXIC_UINT32 instrmem1_bank1_ram_parity_err_flag;
-    ZXIC_UINT32 instrmem1_bank0_ram_parity_err_flag;
-    ZXIC_UINT32 instrmem0_bank3_ram_parity_err_flag;
-    ZXIC_UINT32 instrmem0_bank2_ram_parity_err_flag;
-    ZXIC_UINT32 instrmem0_bank1_ram_parity_err_flag;
-    ZXIC_UINT32 instrmem0_bank0_ram_parity_err_flag;
-}DPP_PPU_PPU_INSTRMEM_RAM_INT_FLAG_T;
-
-typedef struct dpp_ppu_ppu_ppu_count_cfg_t
-{
-    ZXIC_UINT32 ppu_count_overflow_mode;
-    ZXIC_UINT32 ppu_count_rd_mode;
-}DPP_PPU_PPU_PPU_COUNT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_statics_cfg_t
-{
-    ZXIC_UINT32 csr_statics_mc_type;
-    ZXIC_UINT32 csr_statics_bufnum;
-    ZXIC_UINT32 csr_statics_portnum1;
-    ZXIC_UINT32 csr_statics_portnum0;
-}DPP_PPU_PPU_PPU_STATICS_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_statics_wb_cfg_t
-{
-    ZXIC_UINT32 csr_statics_wb_halt_send_type;
-    ZXIC_UINT32 csr_statics_wb_mf_type;
-    ZXIC_UINT32 csr_statics_wb_halt_continue_end;
-    ZXIC_UINT32 csr_statics_wb_dup_flag;
-    ZXIC_UINT32 csr_statics_wb_last_flag;
-    ZXIC_UINT32 csr_statics_wb_dis_flag;
-}DPP_PPU_PPU_PPU_STATICS_WB_CFG_T;
-
-typedef struct dpp_ppu_ppu_wr_table_self_rsp_en_cfg_t
-{
-    ZXIC_UINT32 wr_table_self_rsp_en_cfg;
-}DPP_PPU_PPU_WR_TABLE_SELF_RSP_EN_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_random_arbiter_8to1_cfg_t
-{
-    ZXIC_UINT32 ppu_random_arbiter_8to1_cfg;
-}DPP_PPU_PPU_PPU_RANDOM_ARBITER_8TO1_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_reorder_bypass_flow_num_cfg_t
-{
-    ZXIC_UINT32 ppu_reorder_bypass_flow_num_cfg;
-}DPP_PPU_PPU_PPU_REORDER_BYPASS_FLOW_NUM_CFG_T;
-
-typedef struct dpp_ppu_ppu_cos_meter_cfg_h_t
-{
-    ZXIC_UINT32 cbs;
-    ZXIC_UINT32 pbs;
-    ZXIC_UINT32 green_action;
-    ZXIC_UINT32 yellow_action;
-    ZXIC_UINT32 red_action;
-}DPP_PPU_PPU_COS_METER_CFG_H_T;
-
-typedef struct dpp_ppu_ppu_cos_meter_cfg_l_t
-{
-    ZXIC_UINT32 cir;
-    ZXIC_UINT32 pir;
-    ZXIC_UINT32 car_en;
-}DPP_PPU_PPU_COS_METER_CFG_L_T;
-
-typedef struct dpp_ppu_ppu_instrmem_rdy_t
-{
-    ZXIC_UINT32 instrmem_rdy;
-}DPP_PPU_PPU_INSTRMEM_RDY_T;
-
-typedef struct dpp_ppu_ppu_instrmem_addr_t
-{
-    ZXIC_UINT32 instrmem_operate;
-    ZXIC_UINT32 instrmem_addr;
-}DPP_PPU_PPU_INSTRMEM_ADDR_T;
-
-typedef struct dpp_ppu_ppu_instrmem_ind_access_done_t
-{
-    ZXIC_UINT32 instrmem_ind_access_done;
-}DPP_PPU_PPU_INSTRMEM_IND_ACCESS_DONE_T;
-
-typedef struct dpp_ppu_ppu_instrmem_instr0_data_l_t
-{
-    ZXIC_UINT32 instrmem_instr0_data_l;
-}DPP_PPU_PPU_INSTRMEM_INSTR0_DATA_L_T;
-
-typedef struct dpp_ppu_ppu_instrmem_instr0_data_h_t
-{
-    ZXIC_UINT32 instrmem_instr0_data_h;
-}DPP_PPU_PPU_INSTRMEM_INSTR0_DATA_H_T;
-
-typedef struct dpp_ppu_ppu_instrmem_instr1_data_l_t
-{
-    ZXIC_UINT32 instrmem_instr1_data_l;
-}DPP_PPU_PPU_INSTRMEM_INSTR1_DATA_L_T;
-
-typedef struct dpp_ppu_ppu_instrmem_instr1_data_h_t
-{
-    ZXIC_UINT32 instrmem_instr1_data_h;
-}DPP_PPU_PPU_INSTRMEM_INSTR1_DATA_H_T;
-
-typedef struct dpp_ppu_ppu_instrmem_instr2_data_l_t
-{
-    ZXIC_UINT32 instrmem_instr2_data_l;
-}DPP_PPU_PPU_INSTRMEM_INSTR2_DATA_L_T;
-
-typedef struct dpp_ppu_ppu_instrmem_instr2_data_h_t
-{
-    ZXIC_UINT32 instrmem_instr2_data_h;
-}DPP_PPU_PPU_INSTRMEM_INSTR2_DATA_H_T;
-
-typedef struct dpp_ppu_ppu_instrmem_instr3_data_l_t
-{
-    ZXIC_UINT32 instrmem_instr3_data_l;
-}DPP_PPU_PPU_INSTRMEM_INSTR3_DATA_L_T;
-
-typedef struct dpp_ppu_ppu_instrmem_instr3_data_h_t
-{
-    ZXIC_UINT32 instrmem_instr3_data_h;
-}DPP_PPU_PPU_INSTRMEM_INSTR3_DATA_H_T;
-
-typedef struct dpp_ppu_ppu_instrmem_read_instr0_data_l_t
-{
-    ZXIC_UINT32 instrmem_read_instr0_data_l;
-}DPP_PPU_PPU_INSTRMEM_READ_INSTR0_DATA_L_T;
-
-typedef struct dpp_ppu_ppu_instrmem_read_instr0_data_h_t
-{
-    ZXIC_UINT32 instrmem_read_instr0_data_h;
-}DPP_PPU_PPU_INSTRMEM_READ_INSTR0_DATA_H_T;
-
-typedef struct dpp_ppu_ppu_instrmem_read_instr1_data_l_t
-{
-    ZXIC_UINT32 instrmem_read_instr1_data_l;
-}DPP_PPU_PPU_INSTRMEM_READ_INSTR1_DATA_L_T;
-
-typedef struct dpp_ppu_ppu_instrmem_read_instr1_data_h_t
-{
-    ZXIC_UINT32 instrmem_read_instr1_data_h;
-}DPP_PPU_PPU_INSTRMEM_READ_INSTR1_DATA_H_T;
-
-typedef struct dpp_ppu_ppu_instrmem_read_instr2_data_l_t
-{
-    ZXIC_UINT32 instrmem_read_instr2_data_l;
-}DPP_PPU_PPU_INSTRMEM_READ_INSTR2_DATA_L_T;
-
-typedef struct dpp_ppu_ppu_instrmem_read_instr2_data_h_t
-{
-    ZXIC_UINT32 instrmem_read_instr2_data_h;
-}DPP_PPU_PPU_INSTRMEM_READ_INSTR2_DATA_H_T;
-
-typedef struct dpp_ppu_ppu_instrmem_read_instr3_data_l_t
-{
-    ZXIC_UINT32 instrmem_read_instr3_data_l;
-}DPP_PPU_PPU_INSTRMEM_READ_INSTR3_DATA_L_T;
-
-typedef struct dpp_ppu_ppu_instrmem_read_instr3_data_h_t
-{
-    ZXIC_UINT32 instrmem_read_instr3_data_h;
-}DPP_PPU_PPU_INSTRMEM_READ_INSTR3_DATA_H_T;
-
-typedef struct dpp_ppu_ppu_se_ppu_mc_srh_fc_cnt_h_t
-{
-    ZXIC_UINT32 se_ppu_mc_srh_fc_cnt_h;
-}DPP_PPU_PPU_SE_PPU_MC_SRH_FC_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_se_ppu_mc_srh_fc_cnt_l_t
-{
-    ZXIC_UINT32 se_ppu_mc_srh_fc_cnt_l;
-}DPP_PPU_PPU_SE_PPU_MC_SRH_FC_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_ppu_se_mc_srh_fc_cnt_h_t
-{
-    ZXIC_UINT32 ppu_se_mc_srh_fc_cnt_h;
-}DPP_PPU_PPU_PPU_SE_MC_SRH_FC_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_ppu_se_mc_srh_fc_cnt_l_t
-{
-    ZXIC_UINT32 ppu_se_mc_srh_fc_cnt_l;
-}DPP_PPU_PPU_PPU_SE_MC_SRH_FC_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_ppu_se_mc_srh_vld_cnt_h_t
-{
-    ZXIC_UINT32 ppu_se_mc_srh_vld_cnt_h;
-}DPP_PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_ppu_se_mc_srh_vld_cnt_l_t
-{
-    ZXIC_UINT32 ppu_se_mc_srh_vld_cnt_l;
-}DPP_PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_se_ppu_mc_srh_vld_cnt_h_t
-{
-    ZXIC_UINT32 se_ppu_mc_srh_vld_cnt_h;
-}DPP_PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_se_ppu_mc_srh_vld_cnt_l_t
-{
-    ZXIC_UINT32 se_ppu_mc_srh_vld_cnt_l;
-}DPP_PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_h_t
-{
-    ZXIC_UINT32 pbu_ppu_logic_pf_fc_cnt_h;
-}DPP_PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_l_t
-{
-    ZXIC_UINT32 pbu_ppu_logic_pf_fc_cnt_l;
-}DPP_PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_h_t
-{
-    ZXIC_UINT32 ppu_pbu_logic_rsp_fc_cnt_h;
-}DPP_PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_l_t
-{
-    ZXIC_UINT32 ppu_pbu_logic_rsp_fc_cnt_l;
-}DPP_PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_h_t
-{
-    ZXIC_UINT32 ppu_pbu_logic_pf_req_vld_cnt_h;
-}DPP_PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_l_t
-{
-    ZXIC_UINT32 ppu_pbu_logic_pf_req_vld_cnt_l;
-}DPP_PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_h_t
-{
-    ZXIC_UINT32 pbu_ppu_logic_pf_rsp_vld_cnt_h;
-}DPP_PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_l_t
-{
-    ZXIC_UINT32 pbu_ppu_logic_pf_rsp_vld_cnt_l;
-}DPP_PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_h_t
-{
-    ZXIC_UINT32 pbu_ppu_ifb_rd_fc_cnt_h;
-}DPP_PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_l_t
-{
-    ZXIC_UINT32 pbu_ppu_ifb_rd_fc_cnt_l;
-}DPP_PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_pbu_ppu_wb_fc_cnt_h_t
-{
-    ZXIC_UINT32 pbu_ppu_wb_fc_cnt_h;
-}DPP_PPU_PPU_PBU_PPU_WB_FC_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_pbu_ppu_wb_fc_cnt_l_t
-{
-    ZXIC_UINT32 pbu_ppu_wb_fc_cnt_l;
-}DPP_PPU_PPU_PBU_PPU_WB_FC_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_h_t
-{
-    ZXIC_UINT32 ppu_pbu_mcode_pf_req_vld_cnt_h;
-}DPP_PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_l_t
-{
-    ZXIC_UINT32 ppu_pbu_mcode_pf_req_vld_cnt_l;
-}DPP_PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_h_t
-{
-    ZXIC_UINT32 pbu_ppu_mcode_pf_rsp_vld_cnt_h;
-}DPP_PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_l_t
-{
-    ZXIC_UINT32 pbu_ppu_mcode_pf_rsp_vld_cnt_l;
-}DPP_PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_odma_ppu_para_fc_cnt_h_t
-{
-    ZXIC_UINT32 odma_ppu_para_fc_cnt_h;
-}DPP_PPU_PPU_ODMA_PPU_PARA_FC_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_odma_ppu_para_fc_cnt_l_t
-{
-    ZXIC_UINT32 odma_ppu_para_fc_cnt_l;
-}DPP_PPU_PPU_ODMA_PPU_PARA_FC_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_h_t
-{
-    ZXIC_UINT32 odma_ppu_mccnt_wr_fc_cnt_h;
-}DPP_PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_l_t
-{
-    ZXIC_UINT32 odma_ppu_mccnt_wr_fc_cnt_l;
-}DPP_PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_h_t
-{
-    ZXIC_UINT32 ppu_odma_mccnt_wr_vld_cnt_h;
-}DPP_PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_l_t
-{
-    ZXIC_UINT32 ppu_odma_mccnt_wr_vld_cnt_l;
-}DPP_PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_h_t
-{
-    ZXIC_UINT32 odma_ppu_mccnt_rsp_vld_cnt_h;
-}DPP_PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_l_t
-{
-    ZXIC_UINT32 odma_ppu_mccnt_rsp_vld_cnt_l;
-}DPP_PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_ppu_pktrx_uc_fc_cnt_h_t
-{
-    ZXIC_UINT32 ppu_pktrx_uc_fc_cnt_h;
-}DPP_PPU_PPU_PPU_PKTRX_UC_FC_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_ppu_pktrx_uc_fc_cnt_l_t
-{
-    ZXIC_UINT32 ppu_pktrx_uc_fc_cnt_l;
-}DPP_PPU_PPU_PPU_PKTRX_UC_FC_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_ppu_pktrx_mc_fc_cnt_h_t
-{
-    ZXIC_UINT32 ppu_pktrx_mc_fc_cnt_h;
-}DPP_PPU_PPU_PPU_PKTRX_MC_FC_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_ppu_pktrx_mc_fc_cnt_l_t
-{
-    ZXIC_UINT32 ppu_pktrx_mc_fc_cnt_l;
-}DPP_PPU_PPU_PPU_PKTRX_MC_FC_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_pktrx_ppu_desc_vld_cnt_h_t
-{
-    ZXIC_UINT32 pktrx_ppu_desc_vld_cnt_h;
-}DPP_PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_pktrx_ppu_desc_vld_cnt_l_t
-{
-    ZXIC_UINT32 pktrx_ppu_desc_vld_cnt_l;
-}DPP_PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_h_t
-{
-    ZXIC_UINT32 ppu_pbu_ifb_req_vld_cnt_h;
-}DPP_PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_l_t
-{
-    ZXIC_UINT32 ppu_pbu_ifb_req_vld_cnt_l;
-}DPP_PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_h_t
-{
-    ZXIC_UINT32 pbu_ppu_ifb_rsp_vld_cnt_h;
-}DPP_PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_l_t
-{
-    ZXIC_UINT32 pbu_ppu_ifb_rsp_vld_cnt_l;
-}DPP_PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_ppu_pbu_wb_vld_cnt_h_t
-{
-    ZXIC_UINT32 ppu_pbu_wb_vld_cnt_h;
-}DPP_PPU_PPU_PPU_PBU_WB_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_ppu_pbu_wb_vld_cnt_l_t
-{
-    ZXIC_UINT32 ppu_pbu_wb_vld_cnt_l;
-}DPP_PPU_PPU_PPU_PBU_WB_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_h_t
-{
-    ZXIC_UINT32 pbu_ppu_reorder_para_vld_cnt_h;
-}DPP_PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_l_t
-{
-    ZXIC_UINT32 pbu_ppu_reorder_para_vld_cnt_l;
-}DPP_PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_ppu_odma_para_vld_cnt_h_t
-{
-    ZXIC_UINT32 ppu_odma_para_vld_cnt_h;
-}DPP_PPU_PPU_PPU_ODMA_PARA_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_ppu_odma_para_vld_cnt_l_t
-{
-    ZXIC_UINT32 ppu_odma_para_vld_cnt_l;
-}DPP_PPU_PPU_PPU_ODMA_PARA_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_isu_ppu_mc_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_isu_ppu_mc_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_isu_ppu_mc_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_isu_ppu_mc_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_isu_ppu_mc_loop_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_isu_ppu_mc_loop_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_isu_ppu_uc_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_isu_ppu_uc_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_isu_ppu_uc_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_isu_ppu_uc_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_isu_ppu_uc_bufnumis0_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_isu_ppu_uc_bufnumis0_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_demux_schedule_mc_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_demux_schedule_mc_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_demux_schedule_mc_bufnumis0_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_demux_schedule_mc_bufnumis0_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_demux_schedule_mc_srcportis0_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_demux_schedule_mc_srcportis0_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_demux_schedule_mc_srcportis1_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_demux_schedule_mc_srcportis1_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_demux_schedule_uc_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_demux_schedule_uc_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_demux_schedule_uc_bufnumis0_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_demux_schedule_uc_bufnumis0_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_demux_schedule_uc_srcportis0_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_demux_schedule_uc_srcportis0_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_demux_schedule_uc_srcportis1_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_demux_schedule_uc_srcportis1_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_ppu_wb_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_PPU_WB_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_ppu_wb_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_PPU_WB_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_ppu_wb_bufnumis0_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_ppu_wb_bufnumis0_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_ppu_wb_srcportis0_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_ppu_wb_srcportis0_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_ppu_wb_srcportis1_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_ppu_wb_srcportis1_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_ppu_wb_halt_send_type_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_ppu_wb_halt_send_type_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_ppu_wb_mf_type_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_ppu_wb_mf_type_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_ppu_wb_halt_continue_end_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_ppu_wb_halt_continue_end_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_ppu_wb_dup_flag_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_ppu_wb_dup_flag_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_ppu_wb_last_flag_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_ppu_wb_last_flag_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_ppu_wb_dis_flag_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_ppu_wb_dis_flag_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_pbu_ppu_reorder_mf_type_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_pbu_ppu_reorder_mf_type_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h_t
-{
-    ZXIC_UINT32 statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h;
-}DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l_t
-{
-    ZXIC_UINT32 statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l;
-}DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_car_green_pkt_vld_cnt_h_t
-{
-    ZXIC_UINT32 car_green_pkt_vld_cnt_h;
-}DPP_PPU_PPU_CAR_GREEN_PKT_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_car_green_pkt_vld_cnt_l_t
-{
-    ZXIC_UINT32 car_green_pkt_vld_cnt_l;
-}DPP_PPU_PPU_CAR_GREEN_PKT_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_car_yellow_pkt_vld_cnt_h_t
-{
-    ZXIC_UINT32 car_yellow_pkt_vld_cnt_h;
-}DPP_PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_car_yellow_pkt_vld_cnt_l_t
-{
-    ZXIC_UINT32 car_yellow_pkt_vld_cnt_l;
-}DPP_PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_car_red_pkt_vld_cnt_h_t
-{
-    ZXIC_UINT32 car_red_pkt_vld_cnt_h;
-}DPP_PPU_PPU_CAR_RED_PKT_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_car_red_pkt_vld_cnt_l_t
-{
-    ZXIC_UINT32 car_red_pkt_vld_cnt_l;
-}DPP_PPU_PPU_CAR_RED_PKT_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_car_drop_pkt_vld_cnt_h_t
-{
-    ZXIC_UINT32 car_drop_pkt_vld_cnt_h;
-}DPP_PPU_PPU_CAR_DROP_PKT_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_car_drop_pkt_vld_cnt_l_t
-{
-    ZXIC_UINT32 car_drop_pkt_vld_cnt_l;
-}DPP_PPU_PPU_CAR_DROP_PKT_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_h_t
-{
-    ZXIC_UINT32 ppu_pktrx_mc_ptr_vld_cnt_h;
-}DPP_PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_l_t
-{
-    ZXIC_UINT32 ppu_pktrx_mc_ptr_vld_cnt_l;
-}DPP_PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_isu_ppu_loopback_fc_cnt_h_t
-{
-    ZXIC_UINT32 ppu_pktrx_mc_ptr_vld_cnt_h;
-}DPP_PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_H_T;
-
-typedef struct dpp_ppu_ppu_isu_ppu_loopback_fc_cnt_l_t
-{
-    ZXIC_UINT32 ppu_pktrx_mc_ptr_vld_cnt_l;
-}DPP_PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_L_T;
-
-typedef struct dpp_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg;
-}DPP_PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg;
-}DPP_PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg;
-}DPP_PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg;
-}DPP_PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg;
-}DPP_PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg;
-}DPP_PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg;
-}DPP_PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg;
-}DPP_PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_mccnt_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 mccnt_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_MCCNT_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_mccnt_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 mccnt_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_MCCNT_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_mccnt_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 mccnt_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_MCCNT_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_mccnt_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 mccnt_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_MCCNT_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_uc_mf_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 uc_mf_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_UC_MF_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_uc_mf_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 uc_mf_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_UC_MF_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_uc_mf_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 uc_mf_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_UC_MF_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_uc_mf_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 uc_mf_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_UC_MF_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_mc_mf_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 mc_mf_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_MC_MF_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_mc_mf_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 mc_mf_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_MC_MF_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_mc_mf_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 mc_mf_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_MC_MF_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_mc_mf_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 mc_mf_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_MC_MF_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_isu_mf_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 isu_mf_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_ISU_MF_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_isu_mf_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 isu_mf_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_ISU_MF_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_isu_mf_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 isu_mf_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_isu_mf_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 isu_mf_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_isu_fwft_mf_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 isu_fwft_mf_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_isu_fwft_mf_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 isu_fwft_mf_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_isu_mc_para_mf_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 isu_mc_para_mf_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_isu_mc_para_mf_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 isu_mc_para_mf_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 isu_mc_para_mf_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 isu_mc_para_mf_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_group_id_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 group_id_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_GROUP_ID_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_group_id_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 group_id_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_GROUP_ID_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_group_id_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 group_id_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_group_id_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 group_id_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_sa_para_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 sa_para_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_SA_PARA_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_sa_para_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 sa_para_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_SA_PARA_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_sa_para_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 sa_para_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_sa_para_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 sa_para_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_se_mc_rsp_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 se_mc_rsp_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_se_mc_rsp_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 se_mc_rsp_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_se_mc_rsp_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 se_mc_rsp_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_se_mc_rsp_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 se_mc_rsp_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_dup_para_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 dup_para_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_DUP_PARA_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_dup_para_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 dup_para_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_DUP_PARA_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_dup_para_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 dup_para_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_dup_para_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 dup_para_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_pf_rsp_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 pf_rsp_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_PF_RSP_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_pf_rsp_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 pf_rsp_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_PF_RSP_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_pf_rsp_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 pf_rsp_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_pf_rsp_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 pf_rsp_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_dup_freeptr_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 dup_freeptr_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_dup_freeptr_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 dup_freeptr_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_dup_freeptr_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 dup_freeptr_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_dup_freeptr_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 dup_freeptr_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_pf_req_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 pf_req_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_PF_REQ_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_pf_req_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 pf_req_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_PF_REQ_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_pf_req_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 pf_req_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_pf_req_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 pf_req_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_car_flag_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 car_flag_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_car_flag_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 car_flag_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_car_flag_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 car_flag_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_car_flag_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 car_flag_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cluster_mf_out_afifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cluster_mf_out_afifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cluster_mf_out_afifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cluster_mf_out_afifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_key_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_key_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_key_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_key_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_key_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_key_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_key_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_key_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_random_mod_para_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_random_mod_para_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_random_mod_result_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_random_mod_result_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_checksum_result_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_checksum_result_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_checksum_result_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_checksum_result_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_crc_first_para_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_crc_first_para_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_crc_bypass_delay_prog_full_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_crc_bypass_delay_prog_full_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_crc_bypass_delay_prog_empty_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_crc_bypass_delay_prog_empty_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_crc_second_para_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_crc_second_para_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_multiply_para_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_multiply_para_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_multiply_para_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_multiply_para_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_free_global_num_fwft_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 free_global_num_fwft_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_free_global_num_fwft_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 free_global_num_fwft_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_free_global_num_fwft_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 free_global_num_fwft_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_free_global_num_fwft_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 free_global_num_fwft_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg;
-}DPP_PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg;
-}DPP_PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg;
-}DPP_PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg;
-}DPP_PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_ppu_pkt_data0_t
-{
-    ZXIC_UINT32 pkt_data0;
-}DPP_PPU_PPU_PKT_DATA0_T;
-
-typedef struct dpp_ppu_ppu_pkt_data1_t
-{
-    ZXIC_UINT32 pkt_data1;
-}DPP_PPU_PPU_PKT_DATA1_T;
-
-typedef struct dpp_ppu_ppu_pkt_data2_t
-{
-    ZXIC_UINT32 pkt_data2;
-}DPP_PPU_PPU_PKT_DATA2_T;
-
-typedef struct dpp_ppu_ppu_pkt_data3_t
-{
-    ZXIC_UINT32 pkt_data3;
-}DPP_PPU_PPU_PKT_DATA3_T;
-
-typedef struct dpp_ppu_ppu_pkt_data4_t
-{
-    ZXIC_UINT32 pkt_data4;
-}DPP_PPU_PPU_PKT_DATA4_T;
-
-typedef struct dpp_ppu_ppu_pkt_data5_t
-{
-    ZXIC_UINT32 pkt_data5;
-}DPP_PPU_PPU_PKT_DATA5_T;
-
-typedef struct dpp_ppu_ppu_pkt_data6_t
-{
-    ZXIC_UINT32 pkt_data6;
-}DPP_PPU_PPU_PKT_DATA6_T;
-
-typedef struct dpp_ppu_ppu_pkt_data7_t
-{
-    ZXIC_UINT32 pkt_data7;
-}DPP_PPU_PPU_PKT_DATA7_T;
-
-typedef struct dpp_ppu_ppu_pkt_data8_t
-{
-    ZXIC_UINT32 pkt_data8;
-}DPP_PPU_PPU_PKT_DATA8_T;
-
-typedef struct dpp_ppu_ppu_pkt_data9_t
-{
-    ZXIC_UINT32 pkt_data9;
-}DPP_PPU_PPU_PKT_DATA9_T;
-
-typedef struct dpp_ppu_ppu_pkt_data10_t
-{
-    ZXIC_UINT32 pkt_data10;
-}DPP_PPU_PPU_PKT_DATA10_T;
-
-typedef struct dpp_ppu_ppu_pkt_data11_t
-{
-    ZXIC_UINT32 pkt_data11;
-}DPP_PPU_PPU_PKT_DATA11_T;
-
-typedef struct dpp_ppu_ppu_pkt_data12_t
-{
-    ZXIC_UINT32 pkt_data12;
-}DPP_PPU_PPU_PKT_DATA12_T;
-
-typedef struct dpp_ppu_ppu_pkt_data13_t
-{
-    ZXIC_UINT32 pkt_data13;
-}DPP_PPU_PPU_PKT_DATA13_T;
-
-typedef struct dpp_ppu_ppu_pkt_data14_t
-{
-    ZXIC_UINT32 pkt_data14;
-}DPP_PPU_PPU_PKT_DATA14_T;
-
-typedef struct dpp_ppu_ppu_pkt_data15_t
-{
-    ZXIC_UINT32 pkt_data15;
-}DPP_PPU_PPU_PKT_DATA15_T;
-
-typedef struct dpp_ppu_ppu_pkt_data16_t
-{
-    ZXIC_UINT32 pkt_data16;
-}DPP_PPU_PPU_PKT_DATA16_T;
-
-typedef struct dpp_ppu_ppu_pkt_data17_t
-{
-    ZXIC_UINT32 pkt_data17;
-}DPP_PPU_PPU_PKT_DATA17_T;
-
-typedef struct dpp_ppu_ppu_pkt_data18_t
-{
-    ZXIC_UINT32 pkt_data18;
-}DPP_PPU_PPU_PKT_DATA18_T;
-
-typedef struct dpp_ppu_ppu_pkt_data19_t
-{
-    ZXIC_UINT32 pkt_data19;
-}DPP_PPU_PPU_PKT_DATA19_T;
-
-typedef struct dpp_ppu_ppu_pkt_data20_t
-{
-    ZXIC_UINT32 pkt_data20;
-}DPP_PPU_PPU_PKT_DATA20_T;
-
-typedef struct dpp_ppu_ppu_pkt_data21_t
-{
-    ZXIC_UINT32 pkt_data21;
-}DPP_PPU_PPU_PKT_DATA21_T;
-
-typedef struct dpp_ppu_ppu_pkt_data22_t
-{
-    ZXIC_UINT32 pkt_data22;
-}DPP_PPU_PPU_PKT_DATA22_T;
-
-typedef struct dpp_ppu_ppu_pkt_data23_t
-{
-    ZXIC_UINT32 pkt_data23;
-}DPP_PPU_PPU_PKT_DATA23_T;
-
-typedef struct dpp_ppu_ppu_pkt_data24_t
-{
-    ZXIC_UINT32 pkt_data24;
-}DPP_PPU_PPU_PKT_DATA24_T;
-
-typedef struct dpp_ppu_ppu_pkt_data25_t
-{
-    ZXIC_UINT32 pkt_data25;
-}DPP_PPU_PPU_PKT_DATA25_T;
-
-typedef struct dpp_ppu_ppu_pkt_data26_t
-{
-    ZXIC_UINT32 pkt_data26;
-}DPP_PPU_PPU_PKT_DATA26_T;
-
-typedef struct dpp_ppu_ppu_pkt_data27_t
-{
-    ZXIC_UINT32 pkt_data27;
-}DPP_PPU_PPU_PKT_DATA27_T;
-
-typedef struct dpp_ppu_ppu_pkt_data28_t
-{
-    ZXIC_UINT32 pkt_data28;
-}DPP_PPU_PPU_PKT_DATA28_T;
-
-typedef struct dpp_ppu_ppu_pkt_data29_t
-{
-    ZXIC_UINT32 pkt_data29;
-}DPP_PPU_PPU_PKT_DATA29_T;
-
-typedef struct dpp_ppu_ppu_pkt_data30_t
-{
-    ZXIC_UINT32 pkt_data30;
-}DPP_PPU_PPU_PKT_DATA30_T;
-
-typedef struct dpp_ppu_ppu_pkt_data31_t
-{
-    ZXIC_UINT32 pkt_data31;
-}DPP_PPU_PPU_PKT_DATA31_T;
-
-typedef struct dpp_ppu_ppu_pkt_data32_t
-{
-    ZXIC_UINT32 pkt_data32;
-}DPP_PPU_PPU_PKT_DATA32_T;
-
-typedef struct dpp_ppu_ppu_pkt_data33_t
-{
-    ZXIC_UINT32 pkt_data33;
-}DPP_PPU_PPU_PKT_DATA33_T;
-
-typedef struct dpp_ppu_ppu_pkt_data34_t
-{
-    ZXIC_UINT32 pkt_data34;
-}DPP_PPU_PPU_PKT_DATA34_T;
-
-typedef struct dpp_ppu_ppu_pkt_data35_t
-{
-    ZXIC_UINT32 pkt_data35;
-}DPP_PPU_PPU_PKT_DATA35_T;
-
-typedef struct dpp_ppu_ppu_pkt_data36_t
-{
-    ZXIC_UINT32 pkt_data36;
-}DPP_PPU_PPU_PKT_DATA36_T;
-
-typedef struct dpp_ppu_ppu_pkt_data37_t
-{
-    ZXIC_UINT32 pkt_data37;
-}DPP_PPU_PPU_PKT_DATA37_T;
-
-typedef struct dpp_ppu_ppu_pkt_data38_t
-{
-    ZXIC_UINT32 pkt_data38;
-}DPP_PPU_PPU_PKT_DATA38_T;
-
-typedef struct dpp_ppu_ppu_pkt_data39_t
-{
-    ZXIC_UINT32 pkt_data39;
-}DPP_PPU_PPU_PKT_DATA39_T;
-
-typedef struct dpp_ppu_ppu_pkt_data40_t
-{
-    ZXIC_UINT32 pkt_data40;
-}DPP_PPU_PPU_PKT_DATA40_T;
-
-typedef struct dpp_ppu_ppu_pkt_data41_t
-{
-    ZXIC_UINT32 pkt_data41;
-}DPP_PPU_PPU_PKT_DATA41_T;
-
-typedef struct dpp_ppu_ppu_pkt_data42_t
-{
-    ZXIC_UINT32 pkt_data42;
-}DPP_PPU_PPU_PKT_DATA42_T;
-
-typedef struct dpp_ppu_ppu_pkt_data43_t
-{
-    ZXIC_UINT32 pkt_data43;
-}DPP_PPU_PPU_PKT_DATA43_T;
-
-typedef struct dpp_ppu_ppu_pkt_data44_t
-{
-    ZXIC_UINT32 pkt_data44;
-}DPP_PPU_PPU_PKT_DATA44_T;
-
-typedef struct dpp_ppu_ppu_pkt_data45_t
-{
-    ZXIC_UINT32 pkt_data45;
-}DPP_PPU_PPU_PKT_DATA45_T;
-
-typedef struct dpp_ppu_ppu_pkt_data46_t
-{
-    ZXIC_UINT32 pkt_data46;
-}DPP_PPU_PPU_PKT_DATA46_T;
-
-typedef struct dpp_ppu_ppu_pkt_data47_t
-{
-    ZXIC_UINT32 pkt_data47;
-}DPP_PPU_PPU_PKT_DATA47_T;
-
-typedef struct dpp_ppu_ppu_pkt_data48_t
-{
-    ZXIC_UINT32 pkt_data48;
-}DPP_PPU_PPU_PKT_DATA48_T;
-
-typedef struct dpp_ppu_ppu_pkt_data49_t
-{
-    ZXIC_UINT32 pkt_data49;
-}DPP_PPU_PPU_PKT_DATA49_T;
-
-typedef struct dpp_ppu_ppu_pkt_data50_t
-{
-    ZXIC_UINT32 pkt_data50;
-}DPP_PPU_PPU_PKT_DATA50_T;
-
-typedef struct dpp_ppu_ppu_pkt_data51_t
-{
-    ZXIC_UINT32 pkt_data51;
-}DPP_PPU_PPU_PKT_DATA51_T;
-
-typedef struct dpp_ppu_ppu_pkt_data52_t
-{
-    ZXIC_UINT32 pkt_data52;
-}DPP_PPU_PPU_PKT_DATA52_T;
-
-typedef struct dpp_ppu_ppu_pkt_data53_t
-{
-    ZXIC_UINT32 pkt_data53;
-}DPP_PPU_PPU_PKT_DATA53_T;
-
-typedef struct dpp_ppu_ppu_pkt_data54_t
-{
-    ZXIC_UINT32 pkt_data54;
-}DPP_PPU_PPU_PKT_DATA54_T;
-
-typedef struct dpp_ppu_ppu_pkt_data55_t
-{
-    ZXIC_UINT32 pkt_data55;
-}DPP_PPU_PPU_PKT_DATA55_T;
-
-typedef struct dpp_ppu_ppu_pkt_data56_t
-{
-    ZXIC_UINT32 pkt_data56;
-}DPP_PPU_PPU_PKT_DATA56_T;
-
-typedef struct dpp_ppu_ppu_pkt_data57_t
-{
-    ZXIC_UINT32 pkt_data57;
-}DPP_PPU_PPU_PKT_DATA57_T;
-
-typedef struct dpp_ppu_ppu_pkt_data58_t
-{
-    ZXIC_UINT32 pkt_data58;
-}DPP_PPU_PPU_PKT_DATA58_T;
-
-typedef struct dpp_ppu_ppu_pkt_data59_t
-{
-    ZXIC_UINT32 pkt_data59;
-}DPP_PPU_PPU_PKT_DATA59_T;
-
-typedef struct dpp_ppu_ppu_pkt_data60_t
-{
-    ZXIC_UINT32 pkt_data60;
-}DPP_PPU_PPU_PKT_DATA60_T;
-
-typedef struct dpp_ppu_ppu_pkt_data61_t
-{
-    ZXIC_UINT32 pkt_data61;
-}DPP_PPU_PPU_PKT_DATA61_T;
-
-typedef struct dpp_ppu_ppu_pkt_data62_t
-{
-    ZXIC_UINT32 pkt_data62;
-}DPP_PPU_PPU_PKT_DATA62_T;
-
-typedef struct dpp_ppu_ppu_pkt_data63_t
-{
-    ZXIC_UINT32 pkt_data63;
-}DPP_PPU_PPU_PKT_DATA63_T;
-
-typedef struct dpp_ppu_ppu_pkt_data64_t
-{
-    ZXIC_UINT32 pkt_data64;
-}DPP_PPU_PPU_PKT_DATA64_T;
-
-typedef struct dpp_ppu_ppu_pkt_data65_t
-{
-    ZXIC_UINT32 pkt_data65;
-}DPP_PPU_PPU_PKT_DATA65_T;
-
-typedef struct dpp_ppu_ppu_pkt_data66_t
-{
-    ZXIC_UINT32 pkt_data66;
-}DPP_PPU_PPU_PKT_DATA66_T;
-
-typedef struct dpp_ppu_ppu_pkt_data67_t
-{
-    ZXIC_UINT32 pkt_data67;
-}DPP_PPU_PPU_PKT_DATA67_T;
-
-typedef struct dpp_ppu_ppu_pkt_data68_t
-{
-    ZXIC_UINT32 pkt_data68;
-}DPP_PPU_PPU_PKT_DATA68_T;
-
-typedef struct dpp_ppu_ppu_pkt_data69_t
-{
-    ZXIC_UINT32 pkt_data69;
-}DPP_PPU_PPU_PKT_DATA69_T;
-
-typedef struct dpp_ppu_ppu_pkt_data70_t
-{
-    ZXIC_UINT32 pkt_data70;
-}DPP_PPU_PPU_PKT_DATA70_T;
-
-typedef struct dpp_ppu_ppu_pkt_data71_t
-{
-    ZXIC_UINT32 pkt_data71;
-}DPP_PPU_PPU_PKT_DATA71_T;
-
-typedef struct dpp_ppu_ppu_pkt_data72_t
-{
-    ZXIC_UINT32 pkt_data72;
-}DPP_PPU_PPU_PKT_DATA72_T;
-
-typedef struct dpp_ppu_ppu_pkt_data73_t
-{
-    ZXIC_UINT32 pkt_data73;
-}DPP_PPU_PPU_PKT_DATA73_T;
-
-typedef struct dpp_ppu_ppu_pkt_data74_t
-{
-    ZXIC_UINT32 pkt_data74;
-}DPP_PPU_PPU_PKT_DATA74_T;
-
-typedef struct dpp_ppu_ppu_pkt_data75_t
-{
-    ZXIC_UINT32 pkt_data75;
-}DPP_PPU_PPU_PKT_DATA75_T;
-
-typedef struct dpp_ppu_ppu_pkt_data76_t
-{
-    ZXIC_UINT32 pkt_data76;
-}DPP_PPU_PPU_PKT_DATA76_T;
-
-typedef struct dpp_ppu_ppu_pkt_data77_t
-{
-    ZXIC_UINT32 pkt_data77;
-}DPP_PPU_PPU_PKT_DATA77_T;
-
-typedef struct dpp_ppu_ppu_pkt_data78_t
-{
-    ZXIC_UINT32 pkt_data78;
-}DPP_PPU_PPU_PKT_DATA78_T;
-
-typedef struct dpp_ppu_ppu_pkt_data79_t
-{
-    ZXIC_UINT32 pkt_data79;
-}DPP_PPU_PPU_PKT_DATA79_T;
-
-typedef struct dpp_ppu_ppu_pkt_data80_t
-{
-    ZXIC_UINT32 pkt_data80;
-}DPP_PPU_PPU_PKT_DATA80_T;
-
-typedef struct dpp_ppu_ppu_pkt_data81_t
-{
-    ZXIC_UINT32 pkt_data81;
-}DPP_PPU_PPU_PKT_DATA81_T;
-
-typedef struct dpp_ppu_ppu_pkt_data82_t
-{
-    ZXIC_UINT32 pkt_data82;
-}DPP_PPU_PPU_PKT_DATA82_T;
-
-typedef struct dpp_ppu_ppu_pkt_data83_t
-{
-    ZXIC_UINT32 pkt_data83;
-}DPP_PPU_PPU_PKT_DATA83_T;
-
-typedef struct dpp_ppu_ppu_pkt_data84_t
-{
-    ZXIC_UINT32 pkt_data84;
-}DPP_PPU_PPU_PKT_DATA84_T;
-
-typedef struct dpp_ppu_ppu_pkt_data85_t
-{
-    ZXIC_UINT32 pkt_data85;
-}DPP_PPU_PPU_PKT_DATA85_T;
-
-typedef struct dpp_ppu_ppu_pkt_data86_t
-{
-    ZXIC_UINT32 pkt_data86;
-}DPP_PPU_PPU_PKT_DATA86_T;
-
-typedef struct dpp_ppu_ppu_pkt_data87_t
-{
-    ZXIC_UINT32 pkt_data87;
-}DPP_PPU_PPU_PKT_DATA87_T;
-
-typedef struct dpp_ppu_ppu_pkt_data88_t
-{
-    ZXIC_UINT32 pkt_data88;
-}DPP_PPU_PPU_PKT_DATA88_T;
-
-typedef struct dpp_ppu_ppu_pkt_data89_t
-{
-    ZXIC_UINT32 pkt_data89;
-}DPP_PPU_PPU_PKT_DATA89_T;
-
-typedef struct dpp_ppu_ppu_pkt_data90_t
-{
-    ZXIC_UINT32 pkt_data90;
-}DPP_PPU_PPU_PKT_DATA90_T;
-
-typedef struct dpp_ppu_ppu_pkt_data91_t
-{
-    ZXIC_UINT32 pkt_data91;
-}DPP_PPU_PPU_PKT_DATA91_T;
-
-typedef struct dpp_ppu_ppu_pkt_data92_t
-{
-    ZXIC_UINT32 pkt_data92;
-}DPP_PPU_PPU_PKT_DATA92_T;
-
-typedef struct dpp_ppu_ppu_pkt_data93_t
-{
-    ZXIC_UINT32 pkt_data93;
-}DPP_PPU_PPU_PKT_DATA93_T;
-
-typedef struct dpp_ppu_ppu_pkt_data94_t
-{
-    ZXIC_UINT32 pkt_data94;
-}DPP_PPU_PPU_PKT_DATA94_T;
-
-typedef struct dpp_ppu_ppu_pkt_data95_t
-{
-    ZXIC_UINT32 pkt_data95;
-}DPP_PPU_PPU_PKT_DATA95_T;
-
-typedef struct dpp_ppu_ppu_pkt_data96_t
-{
-    ZXIC_UINT32 pkt_data96;
-}DPP_PPU_PPU_PKT_DATA96_T;
-
-typedef struct dpp_ppu_ppu_pkt_data97_t
-{
-    ZXIC_UINT32 pkt_data97;
-}DPP_PPU_PPU_PKT_DATA97_T;
-
-typedef struct dpp_ppu_ppu_pkt_data98_t
-{
-    ZXIC_UINT32 pkt_data98;
-}DPP_PPU_PPU_PKT_DATA98_T;
-
-typedef struct dpp_ppu_ppu_pkt_data99_t
-{
-    ZXIC_UINT32 pkt_data99;
-}DPP_PPU_PPU_PKT_DATA99_T;
-
-typedef struct dpp_ppu_ppu_pkt_data100_t
-{
-    ZXIC_UINT32 pkt_data100;
-}DPP_PPU_PPU_PKT_DATA100_T;
-
-typedef struct dpp_ppu_ppu_pkt_data101_t
-{
-    ZXIC_UINT32 pkt_data101;
-}DPP_PPU_PPU_PKT_DATA101_T;
-
-typedef struct dpp_ppu_ppu_pkt_data102_t
-{
-    ZXIC_UINT32 pkt_data102;
-}DPP_PPU_PPU_PKT_DATA102_T;
-
-typedef struct dpp_ppu_ppu_pkt_data103_t
-{
-    ZXIC_UINT32 pkt_data103;
-}DPP_PPU_PPU_PKT_DATA103_T;
-
-typedef struct dpp_ppu_ppu_pkt_data104_t
-{
-    ZXIC_UINT32 pkt_data104;
-}DPP_PPU_PPU_PKT_DATA104_T;
-
-typedef struct dpp_ppu_ppu_pkt_data105_t
-{
-    ZXIC_UINT32 pkt_data105;
-}DPP_PPU_PPU_PKT_DATA105_T;
-
-typedef struct dpp_ppu_ppu_pkt_data106_t
-{
-    ZXIC_UINT32 pkt_data106;
-}DPP_PPU_PPU_PKT_DATA106_T;
-
-typedef struct dpp_ppu_ppu_pkt_data107_t
-{
-    ZXIC_UINT32 pkt_data107;
-}DPP_PPU_PPU_PKT_DATA107_T;
-
-typedef struct dpp_ppu_ppu_pkt_data108_t
-{
-    ZXIC_UINT32 pkt_data108;
-}DPP_PPU_PPU_PKT_DATA108_T;
-
-typedef struct dpp_ppu_ppu_pkt_data109_t
-{
-    ZXIC_UINT32 pkt_data109;
-}DPP_PPU_PPU_PKT_DATA109_T;
-
-typedef struct dpp_ppu_ppu_pkt_data110_t
-{
-    ZXIC_UINT32 pkt_data110;
-}DPP_PPU_PPU_PKT_DATA110_T;
-
-typedef struct dpp_ppu_ppu_pkt_data111_t
-{
-    ZXIC_UINT32 pkt_data111;
-}DPP_PPU_PPU_PKT_DATA111_T;
-
-typedef struct dpp_ppu_ppu_pkt_data112_t
-{
-    ZXIC_UINT32 pkt_data112;
-}DPP_PPU_PPU_PKT_DATA112_T;
-
-typedef struct dpp_ppu_ppu_pkt_data113_t
-{
-    ZXIC_UINT32 pkt_data113;
-}DPP_PPU_PPU_PKT_DATA113_T;
-
-typedef struct dpp_ppu_ppu_pkt_data114_t
-{
-    ZXIC_UINT32 pkt_data114;
-}DPP_PPU_PPU_PKT_DATA114_T;
-
-typedef struct dpp_ppu_ppu_pkt_data115_t
-{
-    ZXIC_UINT32 pkt_data115;
-}DPP_PPU_PPU_PKT_DATA115_T;
-
-typedef struct dpp_ppu_ppu_pkt_data116_t
-{
-    ZXIC_UINT32 pkt_data116;
-}DPP_PPU_PPU_PKT_DATA116_T;
-
-typedef struct dpp_ppu_ppu_pkt_data117_t
-{
-    ZXIC_UINT32 pkt_data117;
-}DPP_PPU_PPU_PKT_DATA117_T;
-
-typedef struct dpp_ppu_ppu_pkt_data118_t
-{
-    ZXIC_UINT32 pkt_data118;
-}DPP_PPU_PPU_PKT_DATA118_T;
-
-typedef struct dpp_ppu_ppu_pkt_data119_t
-{
-    ZXIC_UINT32 pkt_data119;
-}DPP_PPU_PPU_PKT_DATA119_T;
-
-typedef struct dpp_ppu_ppu_pkt_data120_t
-{
-    ZXIC_UINT32 pkt_data120;
-}DPP_PPU_PPU_PKT_DATA120_T;
-
-typedef struct dpp_ppu_ppu_pkt_data121_t
-{
-    ZXIC_UINT32 pkt_data121;
-}DPP_PPU_PPU_PKT_DATA121_T;
-
-typedef struct dpp_ppu_ppu_pkt_data122_t
-{
-    ZXIC_UINT32 pkt_data122;
-}DPP_PPU_PPU_PKT_DATA122_T;
-
-typedef struct dpp_ppu_ppu_pkt_data123_t
-{
-    ZXIC_UINT32 pkt_data123;
-}DPP_PPU_PPU_PKT_DATA123_T;
-
-typedef struct dpp_ppu_ppu_pkt_data124_t
-{
-    ZXIC_UINT32 pkt_data124;
-}DPP_PPU_PPU_PKT_DATA124_T;
-
-typedef struct dpp_ppu_ppu_pkt_data125_t
-{
-    ZXIC_UINT32 pkt_data125;
-}DPP_PPU_PPU_PKT_DATA125_T;
-
-typedef struct dpp_ppu_ppu_pkt_data126_t
-{
-    ZXIC_UINT32 pkt_data126;
-}DPP_PPU_PPU_PKT_DATA126_T;
-
-typedef struct dpp_ppu_ppu_pkt_data127_t
-{
-    ZXIC_UINT32 pkt_data127;
-}DPP_PPU_PPU_PKT_DATA127_T;
-
-typedef struct dpp_ppu_ppu_spr0_t
-{
-    ZXIC_UINT32 spr0;
-}DPP_PPU_PPU_SPR0_T;
-
-typedef struct dpp_ppu_ppu_spr1_t
-{
-    ZXIC_UINT32 spr1;
-}DPP_PPU_PPU_SPR1_T;
-
-typedef struct dpp_ppu_ppu_spr2_t
-{
-    ZXIC_UINT32 spr2;
-}DPP_PPU_PPU_SPR2_T;
-
-typedef struct dpp_ppu_ppu_spr3_t
-{
-    ZXIC_UINT32 spr3;
-}DPP_PPU_PPU_SPR3_T;
-
-typedef struct dpp_ppu_ppu_spr4_t
-{
-    ZXIC_UINT32 spr4;
-}DPP_PPU_PPU_SPR4_T;
-
-typedef struct dpp_ppu_ppu_spr5_t
-{
-    ZXIC_UINT32 spr5;
-}DPP_PPU_PPU_SPR5_T;
-
-typedef struct dpp_ppu_ppu_spr6_t
-{
-    ZXIC_UINT32 spr6;
-}DPP_PPU_PPU_SPR6_T;
-
-typedef struct dpp_ppu_ppu_spr7_t
-{
-    ZXIC_UINT32 spr7;
-}DPP_PPU_PPU_SPR7_T;
-
-typedef struct dpp_ppu_ppu_spr8_t
-{
-    ZXIC_UINT32 spr8;
-}DPP_PPU_PPU_SPR8_T;
-
-typedef struct dpp_ppu_ppu_spr9_t
-{
-    ZXIC_UINT32 spr9;
-}DPP_PPU_PPU_SPR9_T;
-
-typedef struct dpp_ppu_ppu_spr10_t
-{
-    ZXIC_UINT32 spr10;
-}DPP_PPU_PPU_SPR10_T;
-
-typedef struct dpp_ppu_ppu_spr11_t
-{
-    ZXIC_UINT32 spr11;
-}DPP_PPU_PPU_SPR11_T;
-
-typedef struct dpp_ppu_ppu_spr12_t
-{
-    ZXIC_UINT32 spr12;
-}DPP_PPU_PPU_SPR12_T;
-
-typedef struct dpp_ppu_ppu_spr13_t
-{
-    ZXIC_UINT32 spr13;
-}DPP_PPU_PPU_SPR13_T;
-
-typedef struct dpp_ppu_ppu_spr14_t
-{
-    ZXIC_UINT32 spr14;
-}DPP_PPU_PPU_SPR14_T;
-
-typedef struct dpp_ppu_ppu_spr15_t
-{
-    ZXIC_UINT32 spr15;
-}DPP_PPU_PPU_SPR15_T;
-
-typedef struct dpp_ppu_ppu_spr16_t
-{
-    ZXIC_UINT32 spr16;
-}DPP_PPU_PPU_SPR16_T;
-
-typedef struct dpp_ppu_ppu_spr17_t
-{
-    ZXIC_UINT32 spr17;
-}DPP_PPU_PPU_SPR17_T;
-
-typedef struct dpp_ppu_ppu_spr18_t
-{
-    ZXIC_UINT32 spr18;
-}DPP_PPU_PPU_SPR18_T;
-
-typedef struct dpp_ppu_ppu_spr19_t
-{
-    ZXIC_UINT32 spr19;
-}DPP_PPU_PPU_SPR19_T;
-
-typedef struct dpp_ppu_ppu_spr20_t
-{
-    ZXIC_UINT32 spr20;
-}DPP_PPU_PPU_SPR20_T;
-
-typedef struct dpp_ppu_ppu_spr21_t
-{
-    ZXIC_UINT32 spr21;
-}DPP_PPU_PPU_SPR21_T;
-
-typedef struct dpp_ppu_ppu_spr22_t
-{
-    ZXIC_UINT32 spr22;
-}DPP_PPU_PPU_SPR22_T;
-
-typedef struct dpp_ppu_ppu_spr23_t
-{
-    ZXIC_UINT32 spr23;
-}DPP_PPU_PPU_SPR23_T;
-
-typedef struct dpp_ppu_ppu_spr24_t
-{
-    ZXIC_UINT32 spr24;
-}DPP_PPU_PPU_SPR24_T;
-
-typedef struct dpp_ppu_ppu_spr25_t
-{
-    ZXIC_UINT32 spr25;
-}DPP_PPU_PPU_SPR25_T;
-
-typedef struct dpp_ppu_ppu_spr26_t
-{
-    ZXIC_UINT32 spr26;
-}DPP_PPU_PPU_SPR26_T;
-
-typedef struct dpp_ppu_ppu_spr27_t
-{
-    ZXIC_UINT32 spr27;
-}DPP_PPU_PPU_SPR27_T;
-
-typedef struct dpp_ppu_ppu_spr28_t
-{
-    ZXIC_UINT32 spr28;
-}DPP_PPU_PPU_SPR28_T;
-
-typedef struct dpp_ppu_ppu_spr29_t
-{
-    ZXIC_UINT32 spr29;
-}DPP_PPU_PPU_SPR29_T;
-
-typedef struct dpp_ppu_ppu_spr30_t
-{
-    ZXIC_UINT32 spr30;
-}DPP_PPU_PPU_SPR30_T;
-
-typedef struct dpp_ppu_ppu_spr31_t
-{
-    ZXIC_UINT32 spr31;
-}DPP_PPU_PPU_SPR31_T;
-
-typedef struct dpp_ppu_ppu_rsp0_t
-{
-    ZXIC_UINT32 rsp0;
-}DPP_PPU_PPU_RSP0_T;
-
-typedef struct dpp_ppu_ppu_rsp1_t
-{
-    ZXIC_UINT32 rsp1;
-}DPP_PPU_PPU_RSP1_T;
-
-typedef struct dpp_ppu_ppu_rsp2_t
-{
-    ZXIC_UINT32 rsp2;
-}DPP_PPU_PPU_RSP2_T;
-
-typedef struct dpp_ppu_ppu_rsp3_t
-{
-    ZXIC_UINT32 rsp3;
-}DPP_PPU_PPU_RSP3_T;
-
-typedef struct dpp_ppu_ppu_rsp4_t
-{
-    ZXIC_UINT32 rsp4;
-}DPP_PPU_PPU_RSP4_T;
-
-typedef struct dpp_ppu_ppu_rsp5_t
-{
-    ZXIC_UINT32 rsp5;
-}DPP_PPU_PPU_RSP5_T;
-
-typedef struct dpp_ppu_ppu_rsp6_t
-{
-    ZXIC_UINT32 rsp6;
-}DPP_PPU_PPU_RSP6_T;
-
-typedef struct dpp_ppu_ppu_rsp7_t
-{
-    ZXIC_UINT32 rsp7;
-}DPP_PPU_PPU_RSP7_T;
-
-typedef struct dpp_ppu_ppu_rsp8_t
-{
-    ZXIC_UINT32 rsp8;
-}DPP_PPU_PPU_RSP8_T;
-
-typedef struct dpp_ppu_ppu_rsp9_t
-{
-    ZXIC_UINT32 rsp9;
-}DPP_PPU_PPU_RSP9_T;
-
-typedef struct dpp_ppu_ppu_rsp10_t
-{
-    ZXIC_UINT32 rsp10;
-}DPP_PPU_PPU_RSP10_T;
-
-typedef struct dpp_ppu_ppu_rsp11_t
-{
-    ZXIC_UINT32 rsp11;
-}DPP_PPU_PPU_RSP11_T;
-
-typedef struct dpp_ppu_ppu_rsp12_t
-{
-    ZXIC_UINT32 rsp12;
-}DPP_PPU_PPU_RSP12_T;
-
-typedef struct dpp_ppu_ppu_rsp13_t
-{
-    ZXIC_UINT32 rsp13;
-}DPP_PPU_PPU_RSP13_T;
-
-typedef struct dpp_ppu_ppu_rsp14_t
-{
-    ZXIC_UINT32 rsp14;
-}DPP_PPU_PPU_RSP14_T;
-
-typedef struct dpp_ppu_ppu_rsp15_t
-{
-    ZXIC_UINT32 rsp15;
-}DPP_PPU_PPU_RSP15_T;
-
-typedef struct dpp_ppu_ppu_rsp16_t
-{
-    ZXIC_UINT32 rsp16;
-}DPP_PPU_PPU_RSP16_T;
-
-typedef struct dpp_ppu_ppu_rsp17_t
-{
-    ZXIC_UINT32 rsp17;
-}DPP_PPU_PPU_RSP17_T;
-
-typedef struct dpp_ppu_ppu_rsp18_t
-{
-    ZXIC_UINT32 rsp18;
-}DPP_PPU_PPU_RSP18_T;
-
-typedef struct dpp_ppu_ppu_rsp19_t
-{
-    ZXIC_UINT32 rsp19;
-}DPP_PPU_PPU_RSP19_T;
-
-typedef struct dpp_ppu_ppu_rsp20_t
-{
-    ZXIC_UINT32 rsp20;
-}DPP_PPU_PPU_RSP20_T;
-
-typedef struct dpp_ppu_ppu_rsp21_t
-{
-    ZXIC_UINT32 rsp21;
-}DPP_PPU_PPU_RSP21_T;
-
-typedef struct dpp_ppu_ppu_rsp22_t
-{
-    ZXIC_UINT32 rsp22;
-}DPP_PPU_PPU_RSP22_T;
-
-typedef struct dpp_ppu_ppu_rsp23_t
-{
-    ZXIC_UINT32 rsp23;
-}DPP_PPU_PPU_RSP23_T;
-
-typedef struct dpp_ppu_ppu_rsp24_t
-{
-    ZXIC_UINT32 rsp24;
-}DPP_PPU_PPU_RSP24_T;
-
-typedef struct dpp_ppu_ppu_rsp25_t
-{
-    ZXIC_UINT32 rsp25;
-}DPP_PPU_PPU_RSP25_T;
-
-typedef struct dpp_ppu_ppu_rsp26_t
-{
-    ZXIC_UINT32 rsp26;
-}DPP_PPU_PPU_RSP26_T;
-
-typedef struct dpp_ppu_ppu_rsp27_t
-{
-    ZXIC_UINT32 rsp27;
-}DPP_PPU_PPU_RSP27_T;
-
-typedef struct dpp_ppu_ppu_rsp28_t
-{
-    ZXIC_UINT32 rsp28;
-}DPP_PPU_PPU_RSP28_T;
-
-typedef struct dpp_ppu_ppu_rsp29_t
-{
-    ZXIC_UINT32 rsp29;
-}DPP_PPU_PPU_RSP29_T;
-
-typedef struct dpp_ppu_ppu_rsp30_t
-{
-    ZXIC_UINT32 rsp30;
-}DPP_PPU_PPU_RSP30_T;
-
-typedef struct dpp_ppu_ppu_rsp31_t
-{
-    ZXIC_UINT32 rsp31;
-}DPP_PPU_PPU_RSP31_T;
-
-typedef struct dpp_ppu_ppu_key0_t
-{
-    ZXIC_UINT32 key0;
-}DPP_PPU_PPU_KEY0_T;
-
-typedef struct dpp_ppu_ppu_key1_t
-{
-    ZXIC_UINT32 key1;
-}DPP_PPU_PPU_KEY1_T;
-
-typedef struct dpp_ppu_ppu_key2_t
-{
-    ZXIC_UINT32 key2;
-}DPP_PPU_PPU_KEY2_T;
-
-typedef struct dpp_ppu_ppu_key3_t
-{
-    ZXIC_UINT32 key3;
-}DPP_PPU_PPU_KEY3_T;
-
-typedef struct dpp_ppu_ppu_key4_t
-{
-    ZXIC_UINT32 key4;
-}DPP_PPU_PPU_KEY4_T;
-
-typedef struct dpp_ppu_ppu_key5_t
-{
-    ZXIC_UINT32 key5;
-}DPP_PPU_PPU_KEY5_T;
-
-typedef struct dpp_ppu_ppu_key6_t
-{
-    ZXIC_UINT32 key6;
-}DPP_PPU_PPU_KEY6_T;
-
-typedef struct dpp_ppu_ppu_key7_t
-{
-    ZXIC_UINT32 key7;
-}DPP_PPU_PPU_KEY7_T;
-
-typedef struct dpp_ppu_ppu_key8_t
-{
-    ZXIC_UINT32 key8;
-}DPP_PPU_PPU_KEY8_T;
-
-typedef struct dpp_ppu_ppu_key9_t
-{
-    ZXIC_UINT32 key9;
-}DPP_PPU_PPU_KEY9_T;
-
-typedef struct dpp_ppu_ppu_key10_t
-{
-    ZXIC_UINT32 key10;
-}DPP_PPU_PPU_KEY10_T;
-
-typedef struct dpp_ppu_ppu_key11_t
-{
-    ZXIC_UINT32 key11;
-}DPP_PPU_PPU_KEY11_T;
-
-typedef struct dpp_ppu_ppu_key12_t
-{
-    ZXIC_UINT32 key12;
-}DPP_PPU_PPU_KEY12_T;
-
-typedef struct dpp_ppu_ppu_key13_t
-{
-    ZXIC_UINT32 key13;
-}DPP_PPU_PPU_KEY13_T;
-
-typedef struct dpp_ppu_ppu_key14_t
-{
-    ZXIC_UINT32 key14;
-}DPP_PPU_PPU_KEY14_T;
-
-typedef struct dpp_ppu_ppu_key15_t
-{
-    ZXIC_UINT32 key15;
-}DPP_PPU_PPU_KEY15_T;
-
-typedef struct dpp_ppu_ppu_key16_t
-{
-    ZXIC_UINT32 key16;
-}DPP_PPU_PPU_KEY16_T;
-
-typedef struct dpp_ppu_ppu_key17_t
-{
-    ZXIC_UINT32 key17;
-}DPP_PPU_PPU_KEY17_T;
-
-typedef struct dpp_ppu_ppu_key18_t
-{
-    ZXIC_UINT32 key18;
-}DPP_PPU_PPU_KEY18_T;
-
-typedef struct dpp_ppu_ppu_key19_t
-{
-    ZXIC_UINT32 key19;
-}DPP_PPU_PPU_KEY19_T;
-
-typedef struct dpp_ppu_ppu_flag_t
-{
-    ZXIC_UINT32 me_num;
-    ZXIC_UINT32 thread_num;
-    ZXIC_UINT32 flag;
-}DPP_PPU_PPU_FLAG_T;
-
-typedef struct dpp_ppu_cluster_int_1200m_flag_t
-{
-    ZXIC_UINT32 me7_interrupt_flag;
-    ZXIC_UINT32 me6_interrupt_flag;
-    ZXIC_UINT32 me5_interrupt_flag;
-    ZXIC_UINT32 me4_interrupt_flag;
-    ZXIC_UINT32 me3_interrupt_flag;
-    ZXIC_UINT32 me2_interrupt_flag;
-    ZXIC_UINT32 me1_interrupt_flag;
-    ZXIC_UINT32 me0_interrupt_flag;
-}DPP_PPU_CLUSTER_INT_1200M_FLAG_T;
-
-typedef struct dpp_ppu_cluster_bp_instr_l_t
-{
-    ZXIC_UINT32 bp_instr_l;
-}DPP_PPU_CLUSTER_BP_INSTR_L_T;
-
-typedef struct dpp_ppu_cluster_bp_instr_h_t
-{
-    ZXIC_UINT32 bp_instr_h;
-}DPP_PPU_CLUSTER_BP_INSTR_H_T;
-
-typedef struct dpp_ppu_cluster_bp_addr_t
-{
-    ZXIC_UINT32 bp_addr;
-}DPP_PPU_CLUSTER_BP_ADDR_T;
-
-typedef struct dpp_ppu_cluster_drr_t
-{
-    ZXIC_UINT32 drr;
-}DPP_PPU_CLUSTER_DRR_T;
-
-typedef struct dpp_ppu_cluster_dsr_t
-{
-    ZXIC_UINT32 dsr;
-}DPP_PPU_CLUSTER_DSR_T;
-
-typedef struct dpp_ppu_cluster_dbg_rtl_date_t
-{
-    ZXIC_UINT32 dbg_rtl_date;
-}DPP_PPU_CLUSTER_DBG_RTL_DATE_T;
-
-typedef struct dpp_ppu_cluster_me_continue_t
-{
-    ZXIC_UINT32 me_continue;
-}DPP_PPU_CLUSTER_ME_CONTINUE_T;
-
-typedef struct dpp_ppu_cluster_me_step_t
-{
-    ZXIC_UINT32 me_step;
-}DPP_PPU_CLUSTER_ME_STEP_T;
-
-typedef struct dpp_ppu_cluster_me_refresh_t
-{
-    ZXIC_UINT32 me_refresh;
-}DPP_PPU_CLUSTER_ME_REFRESH_T;
-
-typedef struct dpp_ppu_cluster_drr_clr_t
-{
-    ZXIC_UINT32 drr_clr;
-}DPP_PPU_CLUSTER_DRR_CLR_T;
-
-typedef struct dpp_ppu_cluster_me_busy_thresold_t
-{
-    ZXIC_UINT32 me_busy_thresold;
-}DPP_PPU_CLUSTER_ME_BUSY_THRESOLD_T;
-
-typedef struct dpp_ppu_cluster_int_1200m_sta_t
-{
-    ZXIC_UINT32 me7_interrupt_sta;
-    ZXIC_UINT32 me6_interrupt_sta;
-    ZXIC_UINT32 me5_interrupt_sta;
-    ZXIC_UINT32 me4_interrupt_sta;
-    ZXIC_UINT32 me3_interrupt_sta;
-    ZXIC_UINT32 me2_interrupt_sta;
-    ZXIC_UINT32 me1_interrupt_sta;
-    ZXIC_UINT32 me0_interrupt_sta;
-}DPP_PPU_CLUSTER_INT_1200M_STA_T;
-
-typedef struct dpp_ppu_cluster_int_1200m_me_fifo_mask_l_t
-{
-    ZXIC_UINT32 me_free_pkt_q_overflow_mask;
-    ZXIC_UINT32 me_free_pkt_q_underflow_mask;
-    ZXIC_UINT32 me_free_thread_q_overflow_mask;
-    ZXIC_UINT32 me_free_thread_q_underflow_mask;
-    ZXIC_UINT32 me_pkt_in_overflow_mask;
-    ZXIC_UINT32 me_pkt_in_underflow_mask;
-    ZXIC_UINT32 me_rdy_q_overflow_mask;
-    ZXIC_UINT32 me_rdy_q_underflow_mask;
-    ZXIC_UINT32 me_pkt_out_q_overflow_mask;
-    ZXIC_UINT32 me_pkt_out_q_underflow_mask;
-    ZXIC_UINT32 me_continue_q_overflow_mask;
-    ZXIC_UINT32 me_continue_q_underflow_mask;
-    ZXIC_UINT32 me_esrh_q_overflow_mask;
-    ZXIC_UINT32 me_esrh_q_underflow_mask;
-    ZXIC_UINT32 me_isrh_q_overflow_mask;
-    ZXIC_UINT32 me_isrh_q_underflow_mask;
-    ZXIC_UINT32 me_cache_miss_q_overflow_mask;
-    ZXIC_UINT32 me_cache_miss_q_underflow_mask;
-    ZXIC_UINT32 me_base_q_u0_overflow_mask;
-    ZXIC_UINT32 me_base_q_u0_underflow_mask;
-    ZXIC_UINT32 me_base_q_u1_overflow_mask;
-    ZXIC_UINT32 me_base_q_u1_underflow_mask;
-    ZXIC_UINT32 me_base_q_u2_overflow_mask;
-    ZXIC_UINT32 me_base_q_u2_underflow_mask;
-    ZXIC_UINT32 me_base_q_u3_overflow_mask;
-    ZXIC_UINT32 me_base_q_u3_underflow_mask;
-    ZXIC_UINT32 me_reg_pc_q_overflow_mask;
-    ZXIC_UINT32 me_reg_pc_q_underflow_mask;
-    ZXIC_UINT32 me_branch_q_overflow_mask;
-    ZXIC_UINT32 me_branch_q_underflow_mask;
-    ZXIC_UINT32 me_pkt_base_q_overflow_mask;
-    ZXIC_UINT32 me_pkt_base_q_underflow_mask;
-}DPP_PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_L_T;
-
-typedef struct dpp_ppu_cluster_int_1200m_me_fifo_mask_h_t
-{
-    ZXIC_UINT32 me_except_refetch_pc_overflow_mask;
-    ZXIC_UINT32 me_except_refetch_pc_underflow_mask;
-}DPP_PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_H_T;
-
-typedef struct dpp_ppu_cluster_me_fifo_interrupt_flag_l_t
-{
-    ZXIC_UINT32 me_free_pkt_q_overflow_flag;
-    ZXIC_UINT32 me_free_pkt_q_underflow_flag;
-    ZXIC_UINT32 me_free_thread_q_overflow_flag;
-    ZXIC_UINT32 me_free_thread_q_underflow_flag;
-    ZXIC_UINT32 me_pkt_in_overflow_flag;
-    ZXIC_UINT32 me_pkt_in_underflow_flag;
-    ZXIC_UINT32 me_rdy_q_overflow_flag;
-    ZXIC_UINT32 me_rdy_q_underflow_flag;
-    ZXIC_UINT32 me_pkt_out_q_overflow_flag;
-    ZXIC_UINT32 me_pkt_out_q_underflow_flag;
-    ZXIC_UINT32 me_continue_q_overflow_flag;
-    ZXIC_UINT32 me_continue_q_underflow_flag;
-    ZXIC_UINT32 me_esrh_q_overflow_flag;
-    ZXIC_UINT32 me_esrh_q_underflow_flag;
-    ZXIC_UINT32 me_isrh_q_overflow_flag;
-    ZXIC_UINT32 me_isrh_q_underflow_flag;
-    ZXIC_UINT32 me_cache_miss_q_overflow_flag;
-    ZXIC_UINT32 me_cache_miss_q_underflow_flag;
-    ZXIC_UINT32 me_base_q_u0_overflow_flag;
-    ZXIC_UINT32 me_base_q_u0_underflow_flag;
-    ZXIC_UINT32 me_base_q_u1_overflow_flag;
-    ZXIC_UINT32 me_base_q_u1_underflow_flag;
-    ZXIC_UINT32 me_base_q_u2_overflow_flag;
-    ZXIC_UINT32 me_base_q_u2_underflow_flag;
-    ZXIC_UINT32 me_base_q_u3_overflow_flag;
-    ZXIC_UINT32 me_base_q_u3_underflow_flag;
-    ZXIC_UINT32 me_reg_pc_q_overflow_flag;
-    ZXIC_UINT32 me_reg_pc_q_underflow_flag;
-    ZXIC_UINT32 me_branch_q_overflow_flag;
-    ZXIC_UINT32 me_branch_q_underflow_flag;
-    ZXIC_UINT32 me_pkt_base_q_overflow_flag;
-    ZXIC_UINT32 me_pkt_base_q_underflow_flag;
-}DPP_PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_L_T;
-
-typedef struct dpp_ppu_cluster_me_fifo_interrupt_flag_h_t
-{
-    ZXIC_UINT32 me_except_refetch_pc_overflow_flag;
-    ZXIC_UINT32 me_except_refetch_pc_underflow_flag;
-}DPP_PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_H_T;
-
-typedef struct dpp_ppu_cluster_me_fifo_interrupt_sta_l_t
-{
-    ZXIC_UINT32 me_free_pkt_q_overflow_sta;
-    ZXIC_UINT32 me_free_pkt_q_underflow_sta;
-    ZXIC_UINT32 me_free_thread_q_overflow_sta;
-    ZXIC_UINT32 me_free_thread_q_underflow_sta;
-    ZXIC_UINT32 me_pkt_in_overflow_sta;
-    ZXIC_UINT32 me_pkt_in_underflow_sta;
-    ZXIC_UINT32 me_rdy_q_overflow_sta;
-    ZXIC_UINT32 me_rdy_q_underflow_sta;
-    ZXIC_UINT32 me_pkt_out_q_overflow_sta;
-    ZXIC_UINT32 me_pkt_out_q_underflow_sta;
-    ZXIC_UINT32 me_continue_q_overflow_sta;
-    ZXIC_UINT32 me_continue_q_underflow_sta;
-    ZXIC_UINT32 me_esrh_q_overflow_sta;
-    ZXIC_UINT32 me_esrh_q_underflow_sta;
-    ZXIC_UINT32 me_isrh_q_overflow_sta;
-    ZXIC_UINT32 me_isrh_q_underflow_sta;
-    ZXIC_UINT32 me_cache_miss_q_overflow_sta;
-    ZXIC_UINT32 me_cache_miss_q_underflow_sta;
-    ZXIC_UINT32 me_base_q_u0_overflow_sta;
-    ZXIC_UINT32 me_base_q_u0_underflow_sta;
-    ZXIC_UINT32 me_base_q_u1_overflow_sta;
-    ZXIC_UINT32 me_base_q_u1_underflow_sta;
-    ZXIC_UINT32 me_base_q_u2_overflow_sta;
-    ZXIC_UINT32 me_base_q_u2_underflow_sta;
-    ZXIC_UINT32 me_base_q_u3_overflow_sta;
-    ZXIC_UINT32 me_base_q_u3_underflow_sta;
-    ZXIC_UINT32 me_reg_pc_q_overflow_sta;
-    ZXIC_UINT32 me_reg_pc_q_underflow_sta;
-    ZXIC_UINT32 me_branch_q_overflow_sta;
-    ZXIC_UINT32 me_branch_q_underflow_sta;
-    ZXIC_UINT32 me_pkt_base_q_overflow_sta;
-    ZXIC_UINT32 me_pkt_base_q_underflow_sta;
-}DPP_PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_L_T;
-
-typedef struct dpp_ppu_cluster_me_fifo_interrupt_sta_h_t
-{
-    ZXIC_UINT32 me_except_refetch_pc_overflow_sta;
-    ZXIC_UINT32 me_except_refetch_pc_underflow_sta;
-}DPP_PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_H_T;
-
-typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_mask_l_t
-{
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_overflow_mask;
-    ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_underflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_mask;
-    ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_mask;
-}DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_L_T;
-
-typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_mask_h_t
-{
-    ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_overflow_mask;
-    ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_underflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_mask;
-}DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_H_T;
-
-typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_flag_l_t
-{
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_overflow_flag;
-    ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_underflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_flag;
-    ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_flag;
-}DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_L_T;
-
-typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_flag_h_t
-{
-    ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_overflow_flag;
-    ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_underflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag;
-}DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_H_T;
-
-typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_stat_l_t
-{
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_stat;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_stat;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_stat;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_stat;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_stat;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_stat;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_stat;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_stat;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_stat;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_stat;
-    ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_overflow_stat;
-    ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_underflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_stat;
-    ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_stat;
-    ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_underflow_stat;
-    ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_stat;
-    ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_stat;
-}DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_L_T;
-
-typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_stat_h_t
-{
-    ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_overflow_stat;
-    ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_overflow_stat;
-    ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_overflow_stat;
-    ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_stat;
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_stat;
-    ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_stat;
-    ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_stat;
-    ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_stat;
-    ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_stat;
-    ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_stat;
-    ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_stat;
-    ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_overflow_stat;
-    ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_underflow_stat;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_stat;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_stat;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_stat;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_stat;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_stat;
-    ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_stat;
-}DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_H_T;
-
-typedef struct dpp_ppu_cluster_ppu_statics_wb_exception_cfg_t
-{
-    ZXIC_UINT32 csr_statics_wb_exception_code5;
-    ZXIC_UINT32 csr_statics_wb_exception_code4;
-    ZXIC_UINT32 csr_statics_wb_exception_code3;
-    ZXIC_UINT32 csr_statics_wb_exception_code2;
-    ZXIC_UINT32 csr_statics_wb_exception_code1;
-    ZXIC_UINT32 csr_statics_wb_exception_code0;
-}DPP_PPU_CLUSTER_PPU_STATICS_WB_EXCEPTION_CFG_T;
-
-typedef struct dpp_ppu_cluster_thread_switch_en_t
-{
-    ZXIC_UINT32 thread_switch_en;
-}DPP_PPU_CLUSTER_THREAD_SWITCH_EN_T;
-
-typedef struct dpp_ppu_cluster_is_me_not_idle_t
-{
-    ZXIC_UINT32 me7_is_not_idle;
-    ZXIC_UINT32 me6_is_not_idle;
-    ZXIC_UINT32 me5_is_not_idle;
-    ZXIC_UINT32 me4_is_not_idle;
-    ZXIC_UINT32 me3_is_not_idle;
-    ZXIC_UINT32 me2_is_not_idle;
-    ZXIC_UINT32 me1_is_not_idle;
-    ZXIC_UINT32 me0_is_not_idle;
-}DPP_PPU_CLUSTER_IS_ME_NOT_IDLE_T;
-
-typedef struct dpp_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cluster_mf_in_afifo_prog_empty_assert_cfg;
-}DPP_PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cluster_mf_in_afifo_prog_empty_negate_cfg;
-}DPP_PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ese_rsp_afifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ese_rsp_afifo_prog_empty_assert_cfg;
-}DPP_PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ese_rsp_afifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ese_rsp_afifo_prog_empty_negate_cfg;
-}DPP_PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ise_rsp_afifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ise_rsp_afifo_prog_empty_assert_cfg;
-}DPP_PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ise_rsp_afifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ise_rsp_afifo_prog_empty_negate_cfg;
-}DPP_PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg;
-}DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg;
-}DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg;
-}DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg;
-}DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg;
-}DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg;
-}DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg;
-}DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg;
-}DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_sta_rsp_afifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 sta_rsp_afifo_prog_empty_assert_cfg;
-}DPP_PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_sta_rsp_afifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 sta_rsp_afifo_prog_empty_negate_cfg;
-}DPP_PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg;
-}DPP_PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg;
-}DPP_PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg;
-}DPP_PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg;
-}DPP_PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_cop_rsp_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 cop_rsp_fifo_prog_full_assert_cfg;
-}DPP_PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_cop_rsp_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 cop_rsp_fifo_prog_full_negate_cfg;
-}DPP_PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_cop_rsp_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 cop_rsp_fifo_prog_empty_assert_cfg;
-}DPP_PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_cop_rsp_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 cop_rsp_fifo_prog_empty_negate_cfg;
-}DPP_PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_mcode_pf_rsp_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 mcode_pf_rsp_fifo_prog_full_assert_cfg;
-}DPP_PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_mcode_pf_rsp_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 mcode_pf_rsp_fifo_prog_full_negate_cfg;
-}DPP_PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 mcode_pf_rsp_fifo_prog_empty_assert_cfg;
-}DPP_PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 mcode_pf_rsp_fifo_prog_empty_negate_cfg;
-}DPP_PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg;
-}DPP_PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg;
-}DPP_PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg;
-}DPP_PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg;
-}DPP_PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_ise_key_afifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_ise_key_afifo_prog_full_assert_cfg;
-}DPP_PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_ise_key_afifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_ise_key_afifo_prog_full_negate_cfg;
-}DPP_PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_ese_key_afifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_ese_key_afifo_prog_full_assert_cfg;
-}DPP_PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_ese_key_afifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_ese_key_afifo_prog_full_negate_cfg;
-}DPP_PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_sta_key_afifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_sta_key_afifo_prog_full_assert_cfg;
-}DPP_PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_sta_key_afifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_sta_key_afifo_prog_full_negate_cfg;
-}DPP_PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_int_600m_cluster_mex_fifo_mask_t
-{
-    ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_underflow_mask;
-    ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_mask;
-    ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_mask;
-    ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_overflow_mask;
-}DPP_PPU_CLUSTER_INT_600M_CLUSTER_MEX_FIFO_MASK_T;
-
-typedef struct dpp_ppu_cluster_cluster_mex_fifo_600m_interrupt_flag_t
-{
-    ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_underflow_flag;
-    ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_flag;
-    ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_flag;
-    ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_overflow_flag;
-}DPP_PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_FLAG_T;
-
-typedef struct dpp_ppu_cluster_cluster_mex_fifo_600m_interrupt_sta_t
-{
-    ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_underflow_sta;
-    ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_sta;
-    ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_sta;
-    ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_overflow_sta;
-}DPP_PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_STA_T;
-
-typedef struct dpp_ppu_cluster_mex_cnt_cfg_t
-{
-    ZXIC_UINT32 csr_count_overflow_mode;
-    ZXIC_UINT32 csr_count_rd_mode;
-}DPP_PPU_CLUSTER_MEX_CNT_CFG_T;
-
-typedef struct dpp_ppu_cluster_int_600m_cluster_mex_ram_ecc_error_interrupt_mask_t
-{
-    ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_double_err_mask;
-    ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_double_err_mask;
-    ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_double_err_mask;
-    ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_single_err_flag;
-    ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_single_err_mask;
-    ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_single_err_mask;
-}DPP_PPU_CLUSTER_INT_600M_CLUSTER_MEX_RAM_ECC_ERROR_INTERRUPT_MASK_T;
-
-typedef struct dpp_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_flag_t
-{
-    ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_double_err_flag;
-    ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_double_err_flag;
-    ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_double_err_flag;
-    ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_single_err_flag;
-    ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_single_err_flag;
-    ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_single_err_flag;
-}DPP_PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_FLAG_T;
-
-typedef struct dpp_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_sta_t
-{
-    ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_double_err_stat;
-    ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_double_err_stat;
-    ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_double_err_stat;
-    ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_single_err_stat;
-    ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_single_err_stat;
-    ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_single_err_stat;
-}DPP_PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_STA_T;
-
-typedef struct dpp_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_cluster_mf_in_afifo_prog_full_assert_cfg;
-}DPP_PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_cluster_mf_in_afifo_prog_full_negate_cfg;
-}DPP_PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ese_rsp_afifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ese_rsp_afifo_prog_full_assert_cfg;
-}DPP_PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ese_rsp_afifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ese_rsp_afifo_prog_full_negate_cfg;
-}DPP_PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ise_rsp_afifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 ise_rsp_afifo_prog_full_assert_cfg;
-}DPP_PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ise_rsp_afifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 ise_rsp_afifo_prog_full_negate_cfg;
-}DPP_PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_sta_rsp_afifo_prog_full_assert_cfg_t
-{
-    ZXIC_UINT32 sta_rsp_afifo_prog_full_assert_cfg;
-}DPP_PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_sta_rsp_afifo_prog_full_negate_cfg_t
-{
-    ZXIC_UINT32 sta_rsp_afifo_prog_full_negate_cfg;
-}DPP_PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_ise_key_afifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_ise_key_afifo_prog_empty_assert_cfg;
-}DPP_PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_ise_key_afifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_ise_key_afifo_prog_empty_negate_cfg;
-}DPP_PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_ese_key_afifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_ese_key_afifo_prog_empty_assert_cfg;
-}DPP_PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_ese_key_afifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_ese_key_afifo_prog_empty_negate_cfg;
-}DPP_PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_sta_key_afifo_prog_empty_assert_cfg_t
-{
-    ZXIC_UINT32 ppu_sta_key_afifo_prog_empty_assert_cfg;
-}DPP_PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_ASSERT_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_sta_key_afifo_prog_empty_negate_cfg_t
-{
-    ZXIC_UINT32 ppu_sta_key_afifo_prog_empty_negate_cfg;
-}DPP_PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_NEGATE_CFG_T;
-
-typedef struct dpp_ppu_cluster_ppu_cluster_mf_vld_cnt_h_t
-{
-    ZXIC_UINT32 ppu_cluster_mf_vld_cnt_h;
-}DPP_PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_ppu_cluster_mf_vld_cnt_l_t
-{
-    ZXIC_UINT32 ppu_cluster_mf_vld_cnt_l;
-}DPP_PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_cluster_ise_key_out_vld_cnt_t
-{
-    ZXIC_UINT32 cluster_ise_key_out_vld_cnt;
-}DPP_PPU_CLUSTER_CLUSTER_ISE_KEY_OUT_VLD_CNT_T;
-
-typedef struct dpp_ppu_cluster_ise_cluster_rsp_in_vld_cnt_t
-{
-    ZXIC_UINT32 ise_cluster_rsp_in_vld_cnt;
-}DPP_PPU_CLUSTER_ISE_CLUSTER_RSP_IN_VLD_CNT_T;
-
-typedef struct dpp_ppu_cluster_cluster_ese_key_out_vld_cnt_t
-{
-    ZXIC_UINT32 cluster_ese_key_out_vld_cnt;
-}DPP_PPU_CLUSTER_CLUSTER_ESE_KEY_OUT_VLD_CNT_T;
-
-typedef struct dpp_ppu_cluster_ese_cluster_rsp_in_vld_cnt_t
-{
-    ZXIC_UINT32 ese_cluster_rsp_in_vld_cnt;
-}DPP_PPU_CLUSTER_ESE_CLUSTER_RSP_IN_VLD_CNT_T;
-
-typedef struct dpp_ppu_cluster_cluster_stat_cmd_vld_cnt_t
-{
-    ZXIC_UINT32 cluster_stat_cmd_vld_cnt;
-}DPP_PPU_CLUSTER_CLUSTER_STAT_CMD_VLD_CNT_T;
-
-typedef struct dpp_ppu_cluster_stat_cluster_rsp_vld_cnt_t
-{
-    ZXIC_UINT32 stat_cluster_rsp_vld_cnt;
-}DPP_PPU_CLUSTER_STAT_CLUSTER_RSP_VLD_CNT_T;
-
-typedef struct dpp_ppu_cluster_mex_debug_key_vld_cnt_t
-{
-    ZXIC_UINT32 mex_debug_key_vld_cnt;
-}DPP_PPU_CLUSTER_MEX_DEBUG_KEY_VLD_CNT_T;
-
-typedef struct dpp_ppu_cluster_ise_cluster_key_fc_cnt_t
-{
-    ZXIC_UINT32 ise_cluster_key_fc_cnt;
-}DPP_PPU_CLUSTER_ISE_CLUSTER_KEY_FC_CNT_T;
-
-typedef struct dpp_ppu_cluster_ese_cluster_key_fc_cnt_t
-{
-    ZXIC_UINT32 ese_cluster_key_fc_cnt;
-}DPP_PPU_CLUSTER_ESE_CLUSTER_KEY_FC_CNT_T;
-
-typedef struct dpp_ppu_cluster_cluster_ise_rsp_fc_cnt_t
-{
-    ZXIC_UINT32 cluster_ise_rsp_fc_cnt;
-}DPP_PPU_CLUSTER_CLUSTER_ISE_RSP_FC_CNT_T;
-
-typedef struct dpp_ppu_cluster_cluster_ese_rsp_fc_cnt_t
-{
-    ZXIC_UINT32 cluster_ese_rsp_fc_cnt;
-}DPP_PPU_CLUSTER_CLUSTER_ESE_RSP_FC_CNT_T;
-
-typedef struct dpp_ppu_cluster_stat_cluster_cmd_fc_cnt_t
-{
-    ZXIC_UINT32 stat_cluster_cmd_fc_cnt;
-}DPP_PPU_CLUSTER_STAT_CLUSTER_CMD_FC_CNT_T;
-
-typedef struct dpp_ppu_cluster_cluster_stat_rsp_fc_cnt_t
-{
-    ZXIC_UINT32 cluster_stat_rsp_fc_cnt;
-}DPP_PPU_CLUSTER_CLUSTER_STAT_RSP_FC_CNT_T;
-
-typedef struct dpp_ppu_cluster_cluster_ppu_mf_vld_cnt_l_t
-{
-    ZXIC_UINT32 cluster_ppu_mf_vld_cnt_l;
-}DPP_PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_cluster_ppu_mf_vld_cnt_h_t
-{
-    ZXIC_UINT32 cluster_ppu_mf_vld_cnt_h;
-}DPP_PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_cluster_cop_key_vld_cnt_l_t
-{
-    ZXIC_UINT32 cluster_cop_key_vld_cnt_l;
-}DPP_PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_cluster_cop_key_vld_cnt_h_t
-{
-    ZXIC_UINT32 cluster_cop_key_vld_cnt_h;
-}DPP_PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_cop_cluster_rsp_vld_cnt_l_t
-{
-    ZXIC_UINT32 cop_cluster_rsp_vld_cnt_l;
-}DPP_PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_cop_cluster_rsp_vld_cnt_h_t
-{
-    ZXIC_UINT32 cop_cluster_rsp_vld_cnt_h;
-}DPP_PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_mex_me_pkt_in_sop_cnt_l_t
-{
-    ZXIC_UINT32 mex_me_pkt_in_sop_cnt_l;
-}DPP_PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_mex_me_pkt_in_sop_cnt_h_t
-{
-    ZXIC_UINT32 mex_me_pkt_in_sop_cnt_h;
-}DPP_PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_mex_me_pkt_in_eop_cnt_l_t
-{
-    ZXIC_UINT32 mex_me_pkt_in_eop_cnt_l;
-}DPP_PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_mex_me_pkt_in_eop_cnt_h_t
-{
-    ZXIC_UINT32 mex_me_pkt_in_eop_cnt_h;
-}DPP_PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_mex_me_pkt_in_vld_cnt_l_t
-{
-    ZXIC_UINT32 mex_me_pkt_in_vld_cnt_l;
-}DPP_PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_mex_me_pkt_in_vld_cnt_h_t
-{
-    ZXIC_UINT32 mex_me_pkt_in_vld_cnt_h;
-}DPP_PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_mex_pkt_out_sop_cnt_l_t
-{
-    ZXIC_UINT32 me_mex_pkt_out_sop_cnt_l;
-}DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_mex_pkt_out_sop_cnt_h_t
-{
-    ZXIC_UINT32 me_mex_pkt_out_sop_cnt_h;
-}DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_mex_pkt_out_eop_cnt_l_t
-{
-    ZXIC_UINT32 me_mex_pkt_out_eop_cnt_l;
-}DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_mex_pkt_out_eop_cnt_h_t
-{
-    ZXIC_UINT32 me_mex_pkt_out_eop_cnt_h;
-}DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_mex_pkt_out_vld_cnt_l_t
-{
-    ZXIC_UINT32 me_mex_pkt_out_vld_cnt_l;
-}DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_mex_pkt_out_vld_cnt_h_t
-{
-    ZXIC_UINT32 me_mex_pkt_out_vld_cnt_h;
-}DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_mex_i_key_out_sop_cnt_l_t
-{
-    ZXIC_UINT32 me_mex_i_key_out_sop_cnt_l;
-}DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_mex_i_key_out_sop_cnt_h_t
-{
-    ZXIC_UINT32 me_mex_i_key_out_sop_cnt_h;
-}DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_mex_i_key_out_eop_cnt_l_t
-{
-    ZXIC_UINT32 me_mex_i_key_out_eop_cnt_l;
-}DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_mex_i_key_out_eop_cnt_h_t
-{
-    ZXIC_UINT32 me_mex_i_key_out_eop_cnt_h;
-}DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_mex_i_key_out_vld_cnt_l_t
-{
-    ZXIC_UINT32 me_mex_i_key_out_vld_cnt_l;
-}DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_mex_i_key_out_vld_cnt_h_t
-{
-    ZXIC_UINT32 me_mex_i_key_out_vld_cnt_h;
-}DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_mex_e_key_out_sop_cnt_l_t
-{
-    ZXIC_UINT32 me_mex_e_key_out_sop_cnt_l;
-}DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_mex_e_key_out_sop_cnt_h_t
-{
-    ZXIC_UINT32 me_mex_e_key_out_sop_cnt_h;
-}DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_mex_e_key_out_eop_cnt_l_t
-{
-    ZXIC_UINT32 me_mex_e_key_out_eop_cnt_l;
-}DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_mex_e_key_out_eop_cnt_h_t
-{
-    ZXIC_UINT32 me_mex_e_key_out_eop_cnt_h;
-}DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_mex_e_key_out_vld_cnt_l_t
-{
-    ZXIC_UINT32 me_mex_e_key_out_vld_cnt_l;
-}DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_mex_e_key_out_vld_cnt_h_t
-{
-    ZXIC_UINT32 me_mex_e_key_out_vld_cnt_h;
-}DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_mex_demux_ise_key_vld_cnt_l_t
-{
-    ZXIC_UINT32 me_mex_demux_ise_key_vld_cnt_l;
-}DPP_PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_mex_demux_ise_key_vld_cnt_h_t
-{
-    ZXIC_UINT32 me_mex_demux_ise_key_vld_cnt_h;
-}DPP_PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_mex_demux_ese_key_vld_cnt_l_t
-{
-    ZXIC_UINT32 me_mex_demux_ese_key_vld_cnt_l;
-}DPP_PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_mex_demux_ese_key_vld_cnt_h_t
-{
-    ZXIC_UINT32 me_mex_demux_ese_key_vld_cnt_h;
-}DPP_PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_mex_demux_sta_key_vld_cnt_l_t
-{
-    ZXIC_UINT32 me_mex_demux_sta_key_vld_cnt_l;
-}DPP_PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_mex_demux_sta_key_vld_cnt_h_t
-{
-    ZXIC_UINT32 me_mex_demux_sta_key_vld_cnt_h;
-}DPP_PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_mex_demux_cop_key_vld_cnt_l_t
-{
-    ZXIC_UINT32 me_mex_demux_cop_key_vld_cnt_l;
-}DPP_PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_mex_demux_cop_key_vld_cnt_h_t
-{
-    ZXIC_UINT32 me_mex_demux_cop_key_vld_cnt_h;
-}DPP_PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_l_t
-{
-    ZXIC_UINT32 mex_me_demux_ise_rsp_vld_cnt_l;
-}DPP_PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_h_t
-{
-    ZXIC_UINT32 mex_me_demux_ise_rsp_vld_cnt_h;
-}DPP_PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_l_t
-{
-    ZXIC_UINT32 mex_me_demux_ese_rsp_vld_cnt_l;
-}DPP_PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_h_t
-{
-    ZXIC_UINT32 mex_me_demux_ese_rsp_vld_cnt_h;
-}DPP_PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_l_t
-{
-    ZXIC_UINT32 mex_me_demux_sta_rsp_vld_cnt_l;
-}DPP_PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_h_t
-{
-    ZXIC_UINT32 mex_me_demux_sta_rsp_vld_cnt_h;
-}DPP_PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_l_t
-{
-    ZXIC_UINT32 mex_me_demux_cop_rsp_vld_cnt_l;
-}DPP_PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_h_t
-{
-    ZXIC_UINT32 mex_me_demux_cop_rsp_vld_cnt_h;
-}DPP_PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_exception_code0_cnt_l_t
-{
-    ZXIC_UINT32 me_exception_code0_cnt_l;
-}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_exception_code0_cnt_h_t
-{
-    ZXIC_UINT32 me_exception_code0_cnt_h;
-}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_exception_code1_cnt_l_t
-{
-    ZXIC_UINT32 me_exception_code1_cnt_l;
-}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_exception_code1_cnt_h_t
-{
-    ZXIC_UINT32 me_exception_code1_cnt_h;
-}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_exception_code2_cnt_l_t
-{
-    ZXIC_UINT32 me_exception_code2_cnt_l;
-}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_exception_code2_cnt_h_t
-{
-    ZXIC_UINT32 me_exception_code2_cnt_h;
-}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_exception_code3_cnt_l_t
-{
-    ZXIC_UINT32 me_exception_code3_cnt_l;
-}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_exception_code3_cnt_h_t
-{
-    ZXIC_UINT32 me_exception_code3_cnt_h;
-}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_exception_code4_cnt_l_t
-{
-    ZXIC_UINT32 me_exception_code4_cnt_l;
-}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_exception_code4_cnt_h_t
-{
-    ZXIC_UINT32 me_exception_code4_cnt_h;
-}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_H_T;
-
-typedef struct dpp_ppu_cluster_me_exception_code5_cnt_l_t
-{
-    ZXIC_UINT32 me_exception_code5_cnt_l;
-}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_L_T;
-
-typedef struct dpp_ppu_cluster_me_exception_code5_cnt_h_t
-{
-    ZXIC_UINT32 me_exception_code5_cnt_h;
-}DPP_PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_H_T;
+typedef struct dpp_ppu_ppu_test_r_t {
+	ZXIC_UINT32 test_r;
+} DPP_PPU_PPU_TEST_R_T;
+
+typedef struct dpp_ppu_ppu_ppu_debug_en_r_t {
+	ZXIC_UINT32 debug_en_r;
+} DPP_PPU_PPU_PPU_DEBUG_EN_R_T;
+
+typedef struct dpp_ppu_ppu_csr_dup_table_wr_data_t {
+	ZXIC_UINT32 item_vld;
+	ZXIC_UINT32 flownum_vld;
+	ZXIC_UINT32 start_pc;
+	ZXIC_UINT32 flownum;
+} DPP_PPU_PPU_CSR_DUP_TABLE_WR_DATA_T;
+
+typedef struct dpp_ppu_ppu_csr_dup_table_rd_data_t {
+	ZXIC_UINT32 item_vld;
+	ZXIC_UINT32 flownum_vld;
+	ZXIC_UINT32 start_pc;
+	ZXIC_UINT32 flownum;
+} DPP_PPU_PPU_CSR_DUP_TABLE_RD_DATA_T;
+
+typedef struct dpp_ppu_ppu_csr_dup_table_addr_t {
+	ZXIC_UINT32 csr_dup_table_operation;
+	ZXIC_UINT32 csr_dup_table_addr;
+} DPP_PPU_PPU_CSR_DUP_TABLE_ADDR_T;
+
+typedef struct dpp_ppu_ppu_ppu_debug_vld_t {
+	ZXIC_UINT32 ppu_debug_vld;
+} DPP_PPU_PPU_PPU_DEBUG_VLD_T;
+
+typedef struct dpp_ppu_ppu_cop_thash_rsk_319_288_t {
+	ZXIC_UINT32 rsk_319_288;
+} DPP_PPU_PPU_COP_THASH_RSK_319_288_T;
+
+typedef struct dpp_ppu_ppu_cop_thash_rsk_287_256_t {
+	ZXIC_UINT32 rsk_287_256;
+} DPP_PPU_PPU_COP_THASH_RSK_287_256_T;
+
+typedef struct dpp_ppu_ppu_cop_thash_rsk_255_224_t {
+	ZXIC_UINT32 rsk_255_224;
+} DPP_PPU_PPU_COP_THASH_RSK_255_224_T;
+
+typedef struct dpp_ppu_ppu_cop_thash_rsk_223_192_t {
+	ZXIC_UINT32 rsk_223_192;
+} DPP_PPU_PPU_COP_THASH_RSK_223_192_T;
+
+typedef struct dpp_ppu_ppu_cop_thash_rsk_191_160_t {
+	ZXIC_UINT32 rsk_191_160;
+} DPP_PPU_PPU_COP_THASH_RSK_191_160_T;
+
+typedef struct dpp_ppu_ppu_cop_thash_rsk_159_128_t {
+	ZXIC_UINT32 rsk_159_128;
+} DPP_PPU_PPU_COP_THASH_RSK_159_128_T;
+
+typedef struct dpp_ppu_ppu_cop_thash_rsk_127_096_t {
+	ZXIC_UINT32 rsk_127_096;
+} DPP_PPU_PPU_COP_THASH_RSK_127_096_T;
+
+typedef struct dpp_ppu_ppu_cop_thash_rsk_095_064_t {
+	ZXIC_UINT32 rsk_095_064;
+} DPP_PPU_PPU_COP_THASH_RSK_095_064_T;
+
+typedef struct dpp_ppu_ppu_cop_thash_rsk_063_032_t {
+	ZXIC_UINT32 rsk_063_032;
+} DPP_PPU_PPU_COP_THASH_RSK_063_032_T;
+
+typedef struct dpp_ppu_ppu_cop_thash_rsk_031_000_t {
+	ZXIC_UINT32 rsk_031_000;
+} DPP_PPU_PPU_COP_THASH_RSK_031_000_T;
+
+typedef struct dpp_ppu_ppu_cfg_ipv4_ipid_start_value_t {
+	ZXIC_UINT32 cfg_ipv4_ipid_start_value;
+} DPP_PPU_PPU_CFG_IPV4_IPID_START_VALUE_T;
+
+typedef struct dpp_ppu_ppu_cfg_ipv4_ipid_end_value_t {
+	ZXIC_UINT32 cfg_ipv4_ipid_end_value;
+} DPP_PPU_PPU_CFG_IPV4_IPID_END_VALUE_T;
+
+typedef struct dpp_ppu_ppu_cluster_mf_in_en_t {
+	ZXIC_UINT32 cluster_mf_in_en;
+} DPP_PPU_PPU_CLUSTER_MF_IN_EN_T;
+
+typedef struct dpp_ppu_ppu_ppu_empty_t {
+	ZXIC_UINT32 ppu_empty;
+} DPP_PPU_PPU_PPU_EMPTY_T;
+
+typedef struct dpp_ppu_ppu_instrmem_w_addr_t {
+	ZXIC_UINT32 instrmem_w_addr;
+} DPP_PPU_PPU_INSTRMEM_W_ADDR_T;
+
+typedef struct dpp_ppu_ppu_instrmem_w_data_191_160_t {
+	ZXIC_UINT32 instrmem_w_data_191_160;
+} DPP_PPU_PPU_INSTRMEM_W_DATA_191_160_T;
+
+typedef struct dpp_ppu_ppu_instrmem_w_data_159_128_t {
+	ZXIC_UINT32 instrmem_w_data_159_128;
+} DPP_PPU_PPU_INSTRMEM_W_DATA_159_128_T;
+
+typedef struct dpp_ppu_ppu_instrmem_w_data_127_96_t {
+	ZXIC_UINT32 instrmem_w_data_127_96;
+} DPP_PPU_PPU_INSTRMEM_W_DATA_127_96_T;
+
+typedef struct dpp_ppu_ppu_instrmem_w_data_95_64_t {
+	ZXIC_UINT32 instrmem_w_data_95_64;
+} DPP_PPU_PPU_INSTRMEM_W_DATA_95_64_T;
+
+typedef struct dpp_ppu_ppu_instrmem_w_data_63_32_t {
+	ZXIC_UINT32 instrmem_w_data_63_32;
+} DPP_PPU_PPU_INSTRMEM_W_DATA_63_32_T;
+
+typedef struct dpp_ppu_ppu_instrmem_w_data_31_0_t {
+	ZXIC_UINT32 instrmem_w_data_31_0;
+} DPP_PPU_PPU_INSTRMEM_W_DATA_31_0_T;
+
+typedef struct dpp_ppu_ppu_isu_fwft_mf_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 isu_fwft_mf_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_isu_fwft_mf_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 isu_fwft_mf_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_int_1200m_mask_t {
+	ZXIC_UINT32 me7_interrupt_mask;
+	ZXIC_UINT32 me6_interrupt_mask;
+	ZXIC_UINT32 me5_interrupt_mask;
+	ZXIC_UINT32 me4_interrupt_mask;
+	ZXIC_UINT32 me3_interrupt_mask;
+	ZXIC_UINT32 me2_interrupt_mask;
+	ZXIC_UINT32 me1_interrupt_mask;
+	ZXIC_UINT32 me0_interrupt_mask;
+} DPP_PPU_CLUSTER_INT_1200M_MASK_T;
+
+typedef struct dpp_ppu_ppu_interrupt_en_r_t {
+	ZXIC_UINT32 interrupt_en_r;
+} DPP_PPU_PPU_INTERRUPT_EN_R_T;
+
+typedef struct dpp_ppu_ppu_mec_host_interrupt_t {
+	ZXIC_UINT32 mec_host_interrupt;
+} DPP_PPU_PPU_MEC_HOST_INTERRUPT_T;
+
+typedef struct dpp_ppu_ppu_dbg_rtl_date_t {
+	ZXIC_UINT32 dbg_rtl_date;
+} DPP_PPU_PPU_DBG_RTL_DATE_T;
+
+typedef struct dpp_ppu_ppu_dup_start_num_cfg_t {
+	ZXIC_UINT32 dup_start_num_cfg;
+} DPP_PPU_PPU_DUP_START_NUM_CFG_T;
+
+typedef struct dpp_ppu_ppu_debug_data_write_complete_t {
+	ZXIC_UINT32 debug_data_write_complete;
+} DPP_PPU_PPU_DEBUG_DATA_WRITE_COMPLETE_T;
+
+typedef struct dpp_ppu_ppu_uc_mc_wrr_cfg_t {
+	ZXIC_UINT32 uc_mc_wrr_cfg;
+} DPP_PPU_PPU_UC_MC_WRR_CFG_T;
+
+typedef struct dpp_ppu_ppu_debug_pkt_send_en_t {
+	ZXIC_UINT32 debug_pkt_send_en;
+} DPP_PPU_PPU_DEBUG_PKT_SEND_EN_T;
+
+typedef struct dpp_ppu_ppu_dup_tbl_ind_access_done_t {
+	ZXIC_UINT32 dup_tbl_ind_access_done;
+} DPP_PPU_PPU_DUP_TBL_IND_ACCESS_DONE_T;
+
+typedef struct dpp_ppu_ppu_isu_ppu_demux_fifo_interrupt_mask_t {
+	ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_underflow_mask;
+} DPP_PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_MASK_T;
+
+typedef struct dpp_ppu_ppu_ppu_multicast_fifo_interrupt_mask_t {
+	ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 car_flag_fifo_32x1_wrapper_overflow_mask;
+	ZXIC_UINT32 car_flag_fifo_32x1_wrapper_underflow_mask;
+} DPP_PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_MASK_T;
+
+typedef struct dpp_ppu_ppu_ppu_in_schedule_fifo_interrupt_mask_t {
+	ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_underflow_mask;
+} DPP_PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_MASK_T;
+
+typedef struct dpp_ppu_ppu_ppu_mf_out_fifo_interrupt_mask_t {
+	ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_mask;
+} DPP_PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_MASK_T;
+
+typedef struct dpp_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_mask_t {
+	ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask;
+} DPP_PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_MASK_T;
+
+typedef struct dpp_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_mask_t {
+	ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_mask;
+	ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_mask;
+} DPP_PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_MASK_T;
+
+typedef struct dpp_ppu_ppu_ppu_mccnt_fifo_interrupt_mask_t {
+	ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_underflow_mask;
+} DPP_PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_MASK_T;
+
+typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_mask_l_t {
+	ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask;
+} DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_L_T;
+
+typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_mask_m_t {
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_mask;
+	ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask;
+	ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask;
+	ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask;
+} DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_M_T;
+
+typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_mask_h_t {
+	ZXIC_UINT32 coprocessor_fwft_fifo_16x80_wrapper_overflow_mask;
+	ZXIC_UINT32 coprocessor_fwft_fifo_16x80_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_mask;
+} DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_H_T;
+
+typedef struct dpp_ppu_ppu_ppu_ram_check_err_mask_t {
+	ZXIC_UINT32 parity_err_mask;
+} DPP_PPU_PPU_PPU_RAM_CHECK_ERR_MASK_T;
+
+typedef struct dpp_ppu_ppu_instrmem_fifo_interrupt_mask_t {
+	ZXIC_UINT32 instrmem2_wr_fifo_ovf_mask;
+	ZXIC_UINT32 instrmem2_wr_fifo_udf_mask;
+	ZXIC_UINT32 instrmem2_rd_fifo_ovf_mask;
+	ZXIC_UINT32 instrmem2_rd_fifo_udf_mask;
+	ZXIC_UINT32 instrmem1_wr_fifo_ovf_mask;
+	ZXIC_UINT32 instrmem1_wr_fifo_udf_mask;
+	ZXIC_UINT32 instrmem1_rd_fifo_ovf_mask;
+	ZXIC_UINT32 instrmem1_rd_fifo_udf_mask;
+	ZXIC_UINT32 instrmem0_wr_fifo_ovf_mask;
+	ZXIC_UINT32 instrmem0_wr_fifo_udf_mask;
+	ZXIC_UINT32 instrmem0_rd_fifo_ovf_mask;
+	ZXIC_UINT32 instrmem0_rd_fifo_udf_mask;
+} DPP_PPU_PPU_INSTRMEM_FIFO_INTERRUPT_MASK_T;
+
+typedef struct dpp_ppu_ppu_isu_ppu_demux_fifo_interrupt_sta_t {
+	ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_sta;
+	ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_underflow_sta;
+} DPP_PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_STA_T;
+
+typedef struct dpp_ppu_ppu_ppu_multicast_fifo_interrupt_sta_t {
+	ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_sta;
+	ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_underflow_sta;
+	ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_sta;
+	ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_underflow_sta;
+	ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_sta;
+	ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_underflow_sta;
+	ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_underflow_sta;
+	ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_sta;
+	ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_sta;
+	ZXIC_UINT32 car_flag_fifo_32x1_wrapper_overflow_sta;
+	ZXIC_UINT32 car_flag_fifo_32x1_wrapper_underflow_sta;
+} DPP_PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_STA_T;
+
+typedef struct dpp_ppu_ppu_ppu_in_schedule_fifo_interrupt_sta_t {
+	ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_sta;
+	ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_underflow_sta;
+	ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_underflow_sta;
+} DPP_PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_STA_T;
+
+typedef struct dpp_ppu_ppu_ppu_mf_out_fifo_interrupt_sta_t {
+	ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_sta;
+} DPP_PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_STA_T;
+
+typedef struct dpp_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_sta_t {
+	ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta;
+} DPP_PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_STA_T;
+
+typedef struct dpp_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_sta_t {
+	ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_sta;
+	ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_sta;
+} DPP_PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_STA_T;
+
+typedef struct dpp_ppu_ppu_ppu_mccnt_fifo_interrupt_sta_t {
+	ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_underflow_sta;
+	ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_sta;
+	ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_underflow_sta;
+} DPP_PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_STA_T;
+
+typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_sta_l_t {
+	ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta;
+} DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_L_T;
+
+typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_sta_m_t {
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_sta;
+	ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta;
+	ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta;
+	ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta;
+} DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_M_T;
+
+typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_sta_h_t {
+	ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_sta;
+} DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_H_T;
+
+typedef struct dpp_ppu_ppu_instrmem_fifo_interrupt_sta_t {
+	ZXIC_UINT32 instrmem1_wr_fifo_ovf_sta;
+	ZXIC_UINT32 instrmem1_wr_fifo_udf_sta;
+	ZXIC_UINT32 instrmem1_rd_fifo_ovf_sta;
+	ZXIC_UINT32 instrmem1_rd_fifo_udf_sta;
+	ZXIC_UINT32 instrmem0_wr_fifo_ovf_sta;
+	ZXIC_UINT32 instrmem0_wr_fifo_udf_sta;
+	ZXIC_UINT32 instrmem0_rd_fifo_ovf_sta;
+	ZXIC_UINT32 instrmem0_rd_fifo_udf_sta;
+} DPP_PPU_PPU_INSTRMEM_FIFO_INTERRUPT_STA_T;
+
+typedef struct dpp_ppu_ppu_ppu_ram_check_ecc_err_flag_1_t {
+	ZXIC_UINT32 ecc_single_err_sa_para_fifo_int_flag;
+	ZXIC_UINT32 ecc_double_err_sa_para_fifo_int_flag;
+	ZXIC_UINT32 ecc_single_err_dup_para_fifo_int_flag;
+	ZXIC_UINT32 ecc_double_err_dup_para_fifo_int_flag;
+	ZXIC_UINT32 ecc_single_err_pf_rsp_fifo_int_flag;
+	ZXIC_UINT32 ecc_double_err_pf_rsp_fifo_int_flag;
+	ZXIC_UINT32 ecc_single_err_pf_req_fifo_int_flag;
+	ZXIC_UINT32 ecc_double_err_pf_req_fifo_int_flag;
+	ZXIC_UINT32 ecc_single_err_ppu_reorder_link_ram0_int_flag;
+	ZXIC_UINT32 ecc_double_err_ppu_reorder_link_ram0_int_flag;
+	ZXIC_UINT32 ecc_single_err_ppu_reorder_link_ram1_int_flag;
+	ZXIC_UINT32 ecc_double_err_ppu_reorder_link_ram1_int_flag;
+	ZXIC_UINT32 ecc_single_err_ppu_reorder_link_flag_array_ram0_int_flag;
+	ZXIC_UINT32 ecc_single_err_ppu_reorder_link_flag_array_ram1_int_flag;
+	ZXIC_UINT32 ecc_single_err_ppu_reorder_ifb_ram_int_flag;
+	ZXIC_UINT32 ecc_double_err_ppu_reorder_ifb_ram_int_flag;
+	ZXIC_UINT32 ecc_single_err_ppu_reorder_flag_array_ram0_int_flag;
+	ZXIC_UINT32 ecc_single_err_ppu_reorder_flag_array_ram1_int_flag;
+	ZXIC_UINT32 ecc_single_err_ppu_reorder_flag_ram0_int_flag;
+	ZXIC_UINT32 ecc_single_err_ppu_reorder_flag_ram1_int_flag;
+	ZXIC_UINT32 ecc_single_err_uc_mf_fifo_int_flag;
+	ZXIC_UINT32 ecc_double_err_uc_mf_fifo_int_flag;
+	ZXIC_UINT32 ecc_single_err_mc_mf_fifo_int_flag;
+	ZXIC_UINT32 ecc_double_err_mc_mf_fifo_int_flag;
+	ZXIC_UINT32 ecc_single_err_free_global_num_fifo_int_flag;
+	ZXIC_UINT32 ecc_double_err_free_global_num_fifo_int_flag;
+} DPP_PPU_PPU_PPU_RAM_CHECK_ECC_ERR_FLAG_1_T;
+
+typedef struct dpp_ppu_ppu_isu_ppu_demux_fifo_interrupt_flag_t {
+	ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 isu_in_fifo_64x81_wrapper_u0_underflow_flag;
+} DPP_PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_FLAG_T;
+
+typedef struct dpp_ppu_ppu_ppu_multicast_fifo_interrupt_flag_t {
+	ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 pf_req_fwft_fifo_16x36_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 dup_para_fwft_fifo_16x35_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 sa_para_fwft_fifo_64x17_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 group_id_fifo_64x16_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 car_flag_fifo_32x1_wrapper_overflow_flag;
+	ZXIC_UINT32 car_flag_fifo_32x1_wrapper_underflow_flag;
+} DPP_PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_FLAG_T;
+
+typedef struct dpp_ppu_ppu_ppu_in_schedule_fifo_interrupt_flag_t {
+	ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 mc_mf_fifo_16x2048_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 uc_mf_fifo_96x2048_wrapper_u0_underflow_flag;
+} DPP_PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_FLAG_T;
+
+typedef struct dpp_ppu_ppu_ppu_mf_out_fifo_interrupt_flag_t {
+	ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_flag;
+} DPP_PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_FLAG_T;
+
+typedef struct dpp_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_flag_t {
+	ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag;
+} DPP_PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_FLAG_T;
+
+typedef struct dpp_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_flag_t {
+	ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_flag;
+	ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_flag;
+} DPP_PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_FLAG_T;
+
+typedef struct dpp_ppu_ppu_ppu_mccnt_fifo_interrupt_flag_t {
+	ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 ppu_mccnt_fifo_32x15_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 mccnt_rsp_fifo_32x1_wrapper_u0_underflow_flag;
+} DPP_PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_FLAG_T;
+
+typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_flag_l_t {
+	ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flag;
+	ZXIC_UINT32 mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flag;
+	ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;
+	ZXIC_UINT32 mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;
+	ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flag;
+	ZXIC_UINT32 mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flag;
+	ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;
+	ZXIC_UINT32 mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag;
+	ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flag;
+	ZXIC_UINT32 mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flag;
+	ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;
+	ZXIC_UINT32 mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;
+	ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flag;
+	ZXIC_UINT32 mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flag;
+	ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;
+	ZXIC_UINT32 mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag;
+	ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flag;
+	ZXIC_UINT32 mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flag;
+	ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;
+	ZXIC_UINT32 mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;
+	ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flag;
+	ZXIC_UINT32 mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flag;
+	ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;
+	ZXIC_UINT32 mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag;
+	ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flag;
+	ZXIC_UINT32 mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flag;
+	ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;
+	ZXIC_UINT32 mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;
+	ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flag;
+	ZXIC_UINT32 mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flag;
+	ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;
+	ZXIC_UINT32 mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag;
+} DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_L_T;
+
+typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_flag_m_t {
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cop_delay_fifo_48x16_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x48_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x32_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cop_delay_fifo_16x16_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_flag;
+	ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flag;
+	ZXIC_UINT32 mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flag;
+	ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;
+	ZXIC_UINT32 mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;
+	ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flag;
+	ZXIC_UINT32 mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flag;
+	ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;
+	ZXIC_UINT32 mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag;
+	ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flag;
+	ZXIC_UINT32 mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flag;
+	ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flag;
+	ZXIC_UINT32 mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flag;
+	ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flag;
+	ZXIC_UINT32 mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flag;
+	ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag;
+	ZXIC_UINT32 mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag;
+} DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_M_T;
+
+typedef struct dpp_ppu_ppu_coprocessor_fifo_interrupt_flag_h_t {
+	ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_flag;
+} DPP_PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_H_T;
+
+typedef struct dpp_ppu_ppu_instrmem_fifo_interrupt_flag_t {
+	ZXIC_UINT32 instrmem2_wr_fifo_ovf_flag;
+	ZXIC_UINT32 instrmem2_wr_fifo_udf_flag;
+	ZXIC_UINT32 instrmem2_rd_fifo_ovf_flag;
+	ZXIC_UINT32 instrmem2_rd_fifo_udf_flag;
+	ZXIC_UINT32 instrmem1_wr_fifo_ovf_flag;
+	ZXIC_UINT32 instrmem1_wr_fifo_udf_flag;
+	ZXIC_UINT32 instrmem1_rd_fifo_ovf_flag;
+	ZXIC_UINT32 instrmem1_rd_fifo_udf_flag;
+	ZXIC_UINT32 instrmem0_wr_fifo_ovf_flag;
+	ZXIC_UINT32 instrmem0_wr_fifo_udf_flag;
+	ZXIC_UINT32 instrmem0_rd_fifo_ovf_flag;
+	ZXIC_UINT32 instrmem0_rd_fifo_udf_flag;
+} DPP_PPU_PPU_INSTRMEM_FIFO_INTERRUPT_FLAG_T;
+
+typedef struct dpp_ppu_ppu_instrmem_ram_int_out_t {
+	ZXIC_UINT32 instrmem2_bank3_ram_parity_err_int_out;
+	ZXIC_UINT32 instrmem2_bank2_ram_parity_err_int_out;
+	ZXIC_UINT32 instrmem2_bank1_ram_parity_err_int_out;
+	ZXIC_UINT32 instrmem2_bank0_ram_parity_err_int_out;
+	ZXIC_UINT32 instrmem1_bank3_ram_parity_err_int_out;
+	ZXIC_UINT32 instrmem1_bank2_ram_parity_err_int_out;
+	ZXIC_UINT32 instrmem1_bank1_ram_parity_err_int_out;
+	ZXIC_UINT32 instrmem1_bank0_ram_parity_err_int_out;
+	ZXIC_UINT32 instrmem0_bank3_ram_parity_err_int_out;
+	ZXIC_UINT32 instrmem0_bank2_ram_parity_err_int_out;
+	ZXIC_UINT32 instrmem0_bank1_ram_parity_err_int_out;
+	ZXIC_UINT32 instrmem0_bank0_ram_parity_err_int_out;
+} DPP_PPU_PPU_INSTRMEM_RAM_INT_OUT_T;
+
+typedef struct dpp_ppu_ppu_instrmem_ram_int_mask_t {
+	ZXIC_UINT32 instrmem2_bank3_ram_parity_err_mask;
+	ZXIC_UINT32 instrmem2_bank2_ram_parity_err_mask;
+	ZXIC_UINT32 instrmem2_bank1_ram_parity_err_mask;
+	ZXIC_UINT32 instrmem2_bank0_ram_parity_err_mask;
+	ZXIC_UINT32 instrmem1_bank3_ram_parity_err_mask;
+	ZXIC_UINT32 instrmem1_bank2_ram_parity_err_mask;
+	ZXIC_UINT32 instrmem1_bank1_ram_parity_err_mask;
+	ZXIC_UINT32 instrmem1_bank0_ram_parity_err_mask;
+	ZXIC_UINT32 instrmem0_bank3_ram_parity_err_mask;
+	ZXIC_UINT32 instrmem0_bank2_ram_parity_err_mask;
+	ZXIC_UINT32 instrmem0_bank1_ram_parity_err_mask;
+	ZXIC_UINT32 instrmem0_bank0_ram_parity_err_mask;
+} DPP_PPU_PPU_INSTRMEM_RAM_INT_MASK_T;
+
+typedef struct dpp_ppu_ppu_instrmem_ram_int_stat_t {
+	ZXIC_UINT32 instrmem2_bank3_ram_parity_errstat;
+	ZXIC_UINT32 instrmem2_bank2_ram_parity_errstat;
+	ZXIC_UINT32 instrmem2_bank1_ram_parity_errstat;
+	ZXIC_UINT32 instrmem2_bank0_ram_parity_errstat;
+	ZXIC_UINT32 instrmem1_bank3_ram_parity_errstat;
+	ZXIC_UINT32 instrmem1_bank2_ram_parity_errstat;
+	ZXIC_UINT32 instrmem1_bank1_ram_parity_errstat;
+	ZXIC_UINT32 instrmem1_bank0_ram_parity_errstat;
+	ZXIC_UINT32 instrmem0_bank3_ram_parity_errstat;
+	ZXIC_UINT32 instrmem0_bank2_ram_parity_errstat;
+	ZXIC_UINT32 instrmem0_bank1_ram_parity_errstat;
+	ZXIC_UINT32 instrmem0_bank0_ram_parity_errstat;
+} DPP_PPU_PPU_INSTRMEM_RAM_INT_STAT_T;
+
+typedef struct dpp_ppu_ppu_instrmem_ram_int_flag_t {
+	ZXIC_UINT32 instrmem2_bank3_ram_parity_err_flag;
+	ZXIC_UINT32 instrmem2_bank2_ram_parity_err_flag;
+	ZXIC_UINT32 instrmem2_bank1_ram_parity_err_flag;
+	ZXIC_UINT32 instrmem2_bank0_ram_parity_err_flag;
+	ZXIC_UINT32 instrmem1_bank3_ram_parity_err_flag;
+	ZXIC_UINT32 instrmem1_bank2_ram_parity_err_flag;
+	ZXIC_UINT32 instrmem1_bank1_ram_parity_err_flag;
+	ZXIC_UINT32 instrmem1_bank0_ram_parity_err_flag;
+	ZXIC_UINT32 instrmem0_bank3_ram_parity_err_flag;
+	ZXIC_UINT32 instrmem0_bank2_ram_parity_err_flag;
+	ZXIC_UINT32 instrmem0_bank1_ram_parity_err_flag;
+	ZXIC_UINT32 instrmem0_bank0_ram_parity_err_flag;
+} DPP_PPU_PPU_INSTRMEM_RAM_INT_FLAG_T;
+
+typedef struct dpp_ppu_ppu_ppu_count_cfg_t {
+	ZXIC_UINT32 ppu_count_overflow_mode;
+	ZXIC_UINT32 ppu_count_rd_mode;
+} DPP_PPU_PPU_PPU_COUNT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_statics_cfg_t {
+	ZXIC_UINT32 csr_statics_mc_type;
+	ZXIC_UINT32 csr_statics_bufnum;
+	ZXIC_UINT32 csr_statics_portnum1;
+	ZXIC_UINT32 csr_statics_portnum0;
+} DPP_PPU_PPU_PPU_STATICS_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_statics_wb_cfg_t {
+	ZXIC_UINT32 csr_statics_wb_halt_send_type;
+	ZXIC_UINT32 csr_statics_wb_mf_type;
+	ZXIC_UINT32 csr_statics_wb_halt_continue_end;
+	ZXIC_UINT32 csr_statics_wb_dup_flag;
+	ZXIC_UINT32 csr_statics_wb_last_flag;
+	ZXIC_UINT32 csr_statics_wb_dis_flag;
+} DPP_PPU_PPU_PPU_STATICS_WB_CFG_T;
+
+typedef struct dpp_ppu_ppu_wr_table_self_rsp_en_cfg_t {
+	ZXIC_UINT32 wr_table_self_rsp_en_cfg;
+} DPP_PPU_PPU_WR_TABLE_SELF_RSP_EN_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_random_arbiter_8to1_cfg_t {
+	ZXIC_UINT32 ppu_random_arbiter_8to1_cfg;
+} DPP_PPU_PPU_PPU_RANDOM_ARBITER_8TO1_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_reorder_bypass_flow_num_cfg_t {
+	ZXIC_UINT32 ppu_reorder_bypass_flow_num_cfg;
+} DPP_PPU_PPU_PPU_REORDER_BYPASS_FLOW_NUM_CFG_T;
+
+typedef struct dpp_ppu_ppu_cos_meter_cfg_h_t {
+	ZXIC_UINT32 cbs;
+	ZXIC_UINT32 pbs;
+	ZXIC_UINT32 green_action;
+	ZXIC_UINT32 yellow_action;
+	ZXIC_UINT32 red_action;
+} DPP_PPU_PPU_COS_METER_CFG_H_T;
+
+typedef struct dpp_ppu_ppu_cos_meter_cfg_l_t {
+	ZXIC_UINT32 cir;
+	ZXIC_UINT32 pir;
+	ZXIC_UINT32 car_en;
+} DPP_PPU_PPU_COS_METER_CFG_L_T;
+
+typedef struct dpp_ppu_ppu_instrmem_rdy_t {
+	ZXIC_UINT32 instrmem_rdy;
+} DPP_PPU_PPU_INSTRMEM_RDY_T;
+
+typedef struct dpp_ppu_ppu_instrmem_addr_t {
+	ZXIC_UINT32 instrmem_operate;
+	ZXIC_UINT32 instrmem_addr;
+} DPP_PPU_PPU_INSTRMEM_ADDR_T;
+
+typedef struct dpp_ppu_ppu_instrmem_ind_access_done_t {
+	ZXIC_UINT32 instrmem_ind_access_done;
+} DPP_PPU_PPU_INSTRMEM_IND_ACCESS_DONE_T;
+
+typedef struct dpp_ppu_ppu_instrmem_instr0_data_l_t {
+	ZXIC_UINT32 instrmem_instr0_data_l;
+} DPP_PPU_PPU_INSTRMEM_INSTR0_DATA_L_T;
+
+typedef struct dpp_ppu_ppu_instrmem_instr0_data_h_t {
+	ZXIC_UINT32 instrmem_instr0_data_h;
+} DPP_PPU_PPU_INSTRMEM_INSTR0_DATA_H_T;
+
+typedef struct dpp_ppu_ppu_instrmem_instr1_data_l_t {
+	ZXIC_UINT32 instrmem_instr1_data_l;
+} DPP_PPU_PPU_INSTRMEM_INSTR1_DATA_L_T;
+
+typedef struct dpp_ppu_ppu_instrmem_instr1_data_h_t {
+	ZXIC_UINT32 instrmem_instr1_data_h;
+} DPP_PPU_PPU_INSTRMEM_INSTR1_DATA_H_T;
+
+typedef struct dpp_ppu_ppu_instrmem_instr2_data_l_t {
+	ZXIC_UINT32 instrmem_instr2_data_l;
+} DPP_PPU_PPU_INSTRMEM_INSTR2_DATA_L_T;
+
+typedef struct dpp_ppu_ppu_instrmem_instr2_data_h_t {
+	ZXIC_UINT32 instrmem_instr2_data_h;
+} DPP_PPU_PPU_INSTRMEM_INSTR2_DATA_H_T;
+
+typedef struct dpp_ppu_ppu_instrmem_instr3_data_l_t {
+	ZXIC_UINT32 instrmem_instr3_data_l;
+} DPP_PPU_PPU_INSTRMEM_INSTR3_DATA_L_T;
+
+typedef struct dpp_ppu_ppu_instrmem_instr3_data_h_t {
+	ZXIC_UINT32 instrmem_instr3_data_h;
+} DPP_PPU_PPU_INSTRMEM_INSTR3_DATA_H_T;
+
+typedef struct dpp_ppu_ppu_instrmem_read_instr0_data_l_t {
+	ZXIC_UINT32 instrmem_read_instr0_data_l;
+} DPP_PPU_PPU_INSTRMEM_READ_INSTR0_DATA_L_T;
+
+typedef struct dpp_ppu_ppu_instrmem_read_instr0_data_h_t {
+	ZXIC_UINT32 instrmem_read_instr0_data_h;
+} DPP_PPU_PPU_INSTRMEM_READ_INSTR0_DATA_H_T;
+
+typedef struct dpp_ppu_ppu_instrmem_read_instr1_data_l_t {
+	ZXIC_UINT32 instrmem_read_instr1_data_l;
+} DPP_PPU_PPU_INSTRMEM_READ_INSTR1_DATA_L_T;
+
+typedef struct dpp_ppu_ppu_instrmem_read_instr1_data_h_t {
+	ZXIC_UINT32 instrmem_read_instr1_data_h;
+} DPP_PPU_PPU_INSTRMEM_READ_INSTR1_DATA_H_T;
+
+typedef struct dpp_ppu_ppu_instrmem_read_instr2_data_l_t {
+	ZXIC_UINT32 instrmem_read_instr2_data_l;
+} DPP_PPU_PPU_INSTRMEM_READ_INSTR2_DATA_L_T;
+
+typedef struct dpp_ppu_ppu_instrmem_read_instr2_data_h_t {
+	ZXIC_UINT32 instrmem_read_instr2_data_h;
+} DPP_PPU_PPU_INSTRMEM_READ_INSTR2_DATA_H_T;
+
+typedef struct dpp_ppu_ppu_instrmem_read_instr3_data_l_t {
+	ZXIC_UINT32 instrmem_read_instr3_data_l;
+} DPP_PPU_PPU_INSTRMEM_READ_INSTR3_DATA_L_T;
+
+typedef struct dpp_ppu_ppu_instrmem_read_instr3_data_h_t {
+	ZXIC_UINT32 instrmem_read_instr3_data_h;
+} DPP_PPU_PPU_INSTRMEM_READ_INSTR3_DATA_H_T;
+
+typedef struct dpp_ppu_ppu_se_ppu_mc_srh_fc_cnt_h_t {
+	ZXIC_UINT32 se_ppu_mc_srh_fc_cnt_h;
+} DPP_PPU_PPU_SE_PPU_MC_SRH_FC_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_se_ppu_mc_srh_fc_cnt_l_t {
+	ZXIC_UINT32 se_ppu_mc_srh_fc_cnt_l;
+} DPP_PPU_PPU_SE_PPU_MC_SRH_FC_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_ppu_se_mc_srh_fc_cnt_h_t {
+	ZXIC_UINT32 ppu_se_mc_srh_fc_cnt_h;
+} DPP_PPU_PPU_PPU_SE_MC_SRH_FC_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_ppu_se_mc_srh_fc_cnt_l_t {
+	ZXIC_UINT32 ppu_se_mc_srh_fc_cnt_l;
+} DPP_PPU_PPU_PPU_SE_MC_SRH_FC_CNT_L_T;
 
+typedef struct dpp_ppu_ppu_ppu_se_mc_srh_vld_cnt_h_t {
+	ZXIC_UINT32 ppu_se_mc_srh_vld_cnt_h;
+} DPP_PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_ppu_se_mc_srh_vld_cnt_l_t {
+	ZXIC_UINT32 ppu_se_mc_srh_vld_cnt_l;
+} DPP_PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_se_ppu_mc_srh_vld_cnt_h_t {
+	ZXIC_UINT32 se_ppu_mc_srh_vld_cnt_h;
+} DPP_PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_se_ppu_mc_srh_vld_cnt_l_t {
+	ZXIC_UINT32 se_ppu_mc_srh_vld_cnt_l;
+} DPP_PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_h_t {
+	ZXIC_UINT32 pbu_ppu_logic_pf_fc_cnt_h;
+} DPP_PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_l_t {
+	ZXIC_UINT32 pbu_ppu_logic_pf_fc_cnt_l;
+} DPP_PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_h_t {
+	ZXIC_UINT32 ppu_pbu_logic_rsp_fc_cnt_h;
+} DPP_PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_l_t {
+	ZXIC_UINT32 ppu_pbu_logic_rsp_fc_cnt_l;
+} DPP_PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_h_t {
+	ZXIC_UINT32 ppu_pbu_logic_pf_req_vld_cnt_h;
+} DPP_PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_l_t {
+	ZXIC_UINT32 ppu_pbu_logic_pf_req_vld_cnt_l;
+} DPP_PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_h_t {
+	ZXIC_UINT32 pbu_ppu_logic_pf_rsp_vld_cnt_h;
+} DPP_PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_l_t {
+	ZXIC_UINT32 pbu_ppu_logic_pf_rsp_vld_cnt_l;
+} DPP_PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_h_t {
+	ZXIC_UINT32 pbu_ppu_ifb_rd_fc_cnt_h;
+} DPP_PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_l_t {
+	ZXIC_UINT32 pbu_ppu_ifb_rd_fc_cnt_l;
+} DPP_PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_pbu_ppu_wb_fc_cnt_h_t {
+	ZXIC_UINT32 pbu_ppu_wb_fc_cnt_h;
+} DPP_PPU_PPU_PBU_PPU_WB_FC_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_pbu_ppu_wb_fc_cnt_l_t {
+	ZXIC_UINT32 pbu_ppu_wb_fc_cnt_l;
+} DPP_PPU_PPU_PBU_PPU_WB_FC_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_h_t {
+	ZXIC_UINT32 ppu_pbu_mcode_pf_req_vld_cnt_h;
+} DPP_PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_l_t {
+	ZXIC_UINT32 ppu_pbu_mcode_pf_req_vld_cnt_l;
+} DPP_PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_h_t {
+	ZXIC_UINT32 pbu_ppu_mcode_pf_rsp_vld_cnt_h;
+} DPP_PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_l_t {
+	ZXIC_UINT32 pbu_ppu_mcode_pf_rsp_vld_cnt_l;
+} DPP_PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_odma_ppu_para_fc_cnt_h_t {
+	ZXIC_UINT32 odma_ppu_para_fc_cnt_h;
+} DPP_PPU_PPU_ODMA_PPU_PARA_FC_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_odma_ppu_para_fc_cnt_l_t {
+	ZXIC_UINT32 odma_ppu_para_fc_cnt_l;
+} DPP_PPU_PPU_ODMA_PPU_PARA_FC_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_h_t {
+	ZXIC_UINT32 odma_ppu_mccnt_wr_fc_cnt_h;
+} DPP_PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_l_t {
+	ZXIC_UINT32 odma_ppu_mccnt_wr_fc_cnt_l;
+} DPP_PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_h_t {
+	ZXIC_UINT32 ppu_odma_mccnt_wr_vld_cnt_h;
+} DPP_PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_l_t {
+	ZXIC_UINT32 ppu_odma_mccnt_wr_vld_cnt_l;
+} DPP_PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_h_t {
+	ZXIC_UINT32 odma_ppu_mccnt_rsp_vld_cnt_h;
+} DPP_PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_l_t {
+	ZXIC_UINT32 odma_ppu_mccnt_rsp_vld_cnt_l;
+} DPP_PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_ppu_pktrx_uc_fc_cnt_h_t {
+	ZXIC_UINT32 ppu_pktrx_uc_fc_cnt_h;
+} DPP_PPU_PPU_PPU_PKTRX_UC_FC_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_ppu_pktrx_uc_fc_cnt_l_t {
+	ZXIC_UINT32 ppu_pktrx_uc_fc_cnt_l;
+} DPP_PPU_PPU_PPU_PKTRX_UC_FC_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_ppu_pktrx_mc_fc_cnt_h_t {
+	ZXIC_UINT32 ppu_pktrx_mc_fc_cnt_h;
+} DPP_PPU_PPU_PPU_PKTRX_MC_FC_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_ppu_pktrx_mc_fc_cnt_l_t {
+	ZXIC_UINT32 ppu_pktrx_mc_fc_cnt_l;
+} DPP_PPU_PPU_PPU_PKTRX_MC_FC_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_pktrx_ppu_desc_vld_cnt_h_t {
+	ZXIC_UINT32 pktrx_ppu_desc_vld_cnt_h;
+} DPP_PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_pktrx_ppu_desc_vld_cnt_l_t {
+	ZXIC_UINT32 pktrx_ppu_desc_vld_cnt_l;
+} DPP_PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_h_t {
+	ZXIC_UINT32 ppu_pbu_ifb_req_vld_cnt_h;
+} DPP_PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_l_t {
+	ZXIC_UINT32 ppu_pbu_ifb_req_vld_cnt_l;
+} DPP_PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_h_t {
+	ZXIC_UINT32 pbu_ppu_ifb_rsp_vld_cnt_h;
+} DPP_PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_l_t {
+	ZXIC_UINT32 pbu_ppu_ifb_rsp_vld_cnt_l;
+} DPP_PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_ppu_pbu_wb_vld_cnt_h_t {
+	ZXIC_UINT32 ppu_pbu_wb_vld_cnt_h;
+} DPP_PPU_PPU_PPU_PBU_WB_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_ppu_pbu_wb_vld_cnt_l_t {
+	ZXIC_UINT32 ppu_pbu_wb_vld_cnt_l;
+} DPP_PPU_PPU_PPU_PBU_WB_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_h_t {
+	ZXIC_UINT32 pbu_ppu_reorder_para_vld_cnt_h;
+} DPP_PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_l_t {
+	ZXIC_UINT32 pbu_ppu_reorder_para_vld_cnt_l;
+} DPP_PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_ppu_odma_para_vld_cnt_h_t {
+	ZXIC_UINT32 ppu_odma_para_vld_cnt_h;
+} DPP_PPU_PPU_PPU_ODMA_PARA_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_ppu_odma_para_vld_cnt_l_t {
+	ZXIC_UINT32 ppu_odma_para_vld_cnt_l;
+} DPP_PPU_PPU_PPU_ODMA_PARA_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_isu_ppu_mc_vld_cnt_h_t {
+	ZXIC_UINT32 statics_isu_ppu_mc_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_isu_ppu_mc_vld_cnt_l_t {
+	ZXIC_UINT32 statics_isu_ppu_mc_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_h_t {
+	ZXIC_UINT32 statics_isu_ppu_mc_loop_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_l_t {
+	ZXIC_UINT32 statics_isu_ppu_mc_loop_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_isu_ppu_uc_vld_cnt_h_t {
+	ZXIC_UINT32 statics_isu_ppu_uc_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_isu_ppu_uc_vld_cnt_l_t {
+	ZXIC_UINT32 statics_isu_ppu_uc_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_h_t {
+	ZXIC_UINT32 statics_isu_ppu_uc_bufnumis0_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_l_t {
+	ZXIC_UINT32 statics_isu_ppu_uc_bufnumis0_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_vld_cnt_h_t {
+	ZXIC_UINT32 statics_demux_schedule_mc_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_vld_cnt_l_t {
+	ZXIC_UINT32 statics_demux_schedule_mc_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_h_t {
+	ZXIC_UINT32 statics_demux_schedule_mc_bufnumis0_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_l_t {
+	ZXIC_UINT32 statics_demux_schedule_mc_bufnumis0_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_h_t {
+	ZXIC_UINT32 statics_demux_schedule_mc_srcportis0_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_l_t {
+	ZXIC_UINT32 statics_demux_schedule_mc_srcportis0_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_h_t {
+	ZXIC_UINT32 statics_demux_schedule_mc_srcportis1_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_l_t {
+	ZXIC_UINT32 statics_demux_schedule_mc_srcportis1_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_vld_cnt_h_t {
+	ZXIC_UINT32 statics_demux_schedule_uc_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_vld_cnt_l_t {
+	ZXIC_UINT32 statics_demux_schedule_uc_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_h_t {
+	ZXIC_UINT32 statics_demux_schedule_uc_bufnumis0_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_l_t {
+	ZXIC_UINT32 statics_demux_schedule_uc_bufnumis0_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_h_t {
+	ZXIC_UINT32 statics_demux_schedule_uc_srcportis0_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_l_t {
+	ZXIC_UINT32 statics_demux_schedule_uc_srcportis0_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_h_t {
+	ZXIC_UINT32 statics_demux_schedule_uc_srcportis1_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_l_t {
+	ZXIC_UINT32 statics_demux_schedule_uc_srcportis1_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_vld_cnt_h_t {
+	ZXIC_UINT32 statics_ppu_wb_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_PPU_WB_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_vld_cnt_l_t {
+	ZXIC_UINT32 statics_ppu_wb_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_PPU_WB_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_h_t {
+	ZXIC_UINT32 statics_ppu_wb_bufnumis0_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_l_t {
+	ZXIC_UINT32 statics_ppu_wb_bufnumis0_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_h_t {
+	ZXIC_UINT32 statics_ppu_wb_srcportis0_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_l_t {
+	ZXIC_UINT32 statics_ppu_wb_srcportis0_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_h_t {
+	ZXIC_UINT32 statics_ppu_wb_srcportis1_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_l_t {
+	ZXIC_UINT32 statics_ppu_wb_srcportis1_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_h_t {
+	ZXIC_UINT32 statics_ppu_wb_halt_send_type_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_l_t {
+	ZXIC_UINT32 statics_ppu_wb_halt_send_type_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_h_t {
+	ZXIC_UINT32 statics_ppu_wb_mf_type_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_l_t {
+	ZXIC_UINT32 statics_ppu_wb_mf_type_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_h_t {
+	ZXIC_UINT32 statics_ppu_wb_halt_continue_end_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_l_t {
+	ZXIC_UINT32 statics_ppu_wb_halt_continue_end_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_h_t {
+	ZXIC_UINT32 statics_ppu_wb_dup_flag_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_l_t {
+	ZXIC_UINT32 statics_ppu_wb_dup_flag_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_h_t {
+	ZXIC_UINT32 statics_ppu_wb_last_flag_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_l_t {
+	ZXIC_UINT32 statics_ppu_wb_last_flag_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_h_t {
+	ZXIC_UINT32 statics_ppu_wb_dis_flag_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_l_t {
+	ZXIC_UINT32 statics_ppu_wb_dis_flag_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h_t {
+	ZXIC_UINT32 statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l_t {
+	ZXIC_UINT32 statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_h_t {
+	ZXIC_UINT32 statics_pbu_ppu_reorder_mf_type_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_l_t {
+	ZXIC_UINT32 statics_pbu_ppu_reorder_mf_type_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h_t {
+	ZXIC_UINT32 statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h;
+} DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l_t {
+	ZXIC_UINT32 statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l;
+} DPP_PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_car_green_pkt_vld_cnt_h_t {
+	ZXIC_UINT32 car_green_pkt_vld_cnt_h;
+} DPP_PPU_PPU_CAR_GREEN_PKT_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_car_green_pkt_vld_cnt_l_t {
+	ZXIC_UINT32 car_green_pkt_vld_cnt_l;
+} DPP_PPU_PPU_CAR_GREEN_PKT_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_car_yellow_pkt_vld_cnt_h_t {
+	ZXIC_UINT32 car_yellow_pkt_vld_cnt_h;
+} DPP_PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_car_yellow_pkt_vld_cnt_l_t {
+	ZXIC_UINT32 car_yellow_pkt_vld_cnt_l;
+} DPP_PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_car_red_pkt_vld_cnt_h_t {
+	ZXIC_UINT32 car_red_pkt_vld_cnt_h;
+} DPP_PPU_PPU_CAR_RED_PKT_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_car_red_pkt_vld_cnt_l_t {
+	ZXIC_UINT32 car_red_pkt_vld_cnt_l;
+} DPP_PPU_PPU_CAR_RED_PKT_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_car_drop_pkt_vld_cnt_h_t {
+	ZXIC_UINT32 car_drop_pkt_vld_cnt_h;
+} DPP_PPU_PPU_CAR_DROP_PKT_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_car_drop_pkt_vld_cnt_l_t {
+	ZXIC_UINT32 car_drop_pkt_vld_cnt_l;
+} DPP_PPU_PPU_CAR_DROP_PKT_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_h_t {
+	ZXIC_UINT32 ppu_pktrx_mc_ptr_vld_cnt_h;
+} DPP_PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_l_t {
+	ZXIC_UINT32 ppu_pktrx_mc_ptr_vld_cnt_l;
+} DPP_PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_isu_ppu_loopback_fc_cnt_h_t {
+	ZXIC_UINT32 ppu_pktrx_mc_ptr_vld_cnt_h;
+} DPP_PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_H_T;
+
+typedef struct dpp_ppu_ppu_isu_ppu_loopback_fc_cnt_l_t {
+	ZXIC_UINT32 ppu_pktrx_mc_ptr_vld_cnt_l;
+} DPP_PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_L_T;
+
+typedef struct dpp_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg;
+} DPP_PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg;
+} DPP_PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg;
+} DPP_PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg;
+} DPP_PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg;
+} DPP_PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg;
+} DPP_PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg;
+} DPP_PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg;
+} DPP_PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_mccnt_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 mccnt_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_MCCNT_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_mccnt_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 mccnt_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_MCCNT_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_mccnt_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 mccnt_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_MCCNT_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_mccnt_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 mccnt_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_MCCNT_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_uc_mf_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 uc_mf_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_UC_MF_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_uc_mf_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 uc_mf_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_UC_MF_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_uc_mf_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 uc_mf_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_UC_MF_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_uc_mf_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 uc_mf_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_UC_MF_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_mc_mf_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 mc_mf_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_MC_MF_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_mc_mf_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 mc_mf_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_MC_MF_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_mc_mf_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 mc_mf_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_MC_MF_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_mc_mf_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 mc_mf_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_MC_MF_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_isu_mf_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 isu_mf_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_ISU_MF_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_isu_mf_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 isu_mf_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_ISU_MF_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_isu_mf_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 isu_mf_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_isu_mf_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 isu_mf_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_isu_fwft_mf_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 isu_fwft_mf_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_isu_fwft_mf_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 isu_fwft_mf_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_isu_mc_para_mf_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 isu_mc_para_mf_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_isu_mc_para_mf_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 isu_mc_para_mf_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 isu_mc_para_mf_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 isu_mc_para_mf_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_group_id_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 group_id_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_GROUP_ID_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_group_id_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 group_id_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_GROUP_ID_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_group_id_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 group_id_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_group_id_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 group_id_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_sa_para_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 sa_para_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_SA_PARA_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_sa_para_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 sa_para_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_SA_PARA_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_sa_para_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 sa_para_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_sa_para_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 sa_para_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_se_mc_rsp_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 se_mc_rsp_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_se_mc_rsp_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 se_mc_rsp_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_se_mc_rsp_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 se_mc_rsp_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_se_mc_rsp_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 se_mc_rsp_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_dup_para_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 dup_para_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_DUP_PARA_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_dup_para_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 dup_para_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_DUP_PARA_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_dup_para_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 dup_para_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_dup_para_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 dup_para_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_pf_rsp_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 pf_rsp_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_PF_RSP_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_pf_rsp_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 pf_rsp_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_PF_RSP_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_pf_rsp_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 pf_rsp_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_pf_rsp_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 pf_rsp_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_dup_freeptr_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 dup_freeptr_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_dup_freeptr_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 dup_freeptr_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_dup_freeptr_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 dup_freeptr_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_dup_freeptr_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 dup_freeptr_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_pf_req_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 pf_req_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_PF_REQ_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_pf_req_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 pf_req_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_PF_REQ_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_pf_req_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 pf_req_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_pf_req_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 pf_req_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_car_flag_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 car_flag_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_car_flag_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 car_flag_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_car_flag_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 car_flag_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_car_flag_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 car_flag_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_cluster_mf_out_afifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_cluster_mf_out_afifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_cluster_mf_out_afifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_cluster_mf_out_afifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_key_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_key_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_key_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_key_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_key_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_key_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_key_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_key_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_random_mod_para_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_random_mod_para_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_random_mod_result_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_random_mod_result_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_checksum_result_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_checksum_result_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_checksum_result_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_checksum_result_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_crc_first_para_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_crc_first_para_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_crc_bypass_delay_prog_full_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_crc_bypass_delay_prog_full_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_crc_bypass_delay_prog_empty_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_crc_bypass_delay_prog_empty_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_crc_second_para_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_crc_second_para_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_multiply_para_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_multiply_para_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_multiply_para_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_multiply_para_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_free_global_num_fwft_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 free_global_num_fwft_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_free_global_num_fwft_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 free_global_num_fwft_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_free_global_num_fwft_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 free_global_num_fwft_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_free_global_num_fwft_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 free_global_num_fwft_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg;
+} DPP_PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg;
+} DPP_PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg;
+} DPP_PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg;
+} DPP_PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_ppu_pkt_data0_t {
+	ZXIC_UINT32 pkt_data0;
+} DPP_PPU_PPU_PKT_DATA0_T;
+
+typedef struct dpp_ppu_ppu_pkt_data1_t {
+	ZXIC_UINT32 pkt_data1;
+} DPP_PPU_PPU_PKT_DATA1_T;
+
+typedef struct dpp_ppu_ppu_pkt_data2_t {
+	ZXIC_UINT32 pkt_data2;
+} DPP_PPU_PPU_PKT_DATA2_T;
+
+typedef struct dpp_ppu_ppu_pkt_data3_t {
+	ZXIC_UINT32 pkt_data3;
+} DPP_PPU_PPU_PKT_DATA3_T;
+
+typedef struct dpp_ppu_ppu_pkt_data4_t {
+	ZXIC_UINT32 pkt_data4;
+} DPP_PPU_PPU_PKT_DATA4_T;
+
+typedef struct dpp_ppu_ppu_pkt_data5_t {
+	ZXIC_UINT32 pkt_data5;
+} DPP_PPU_PPU_PKT_DATA5_T;
+
+typedef struct dpp_ppu_ppu_pkt_data6_t {
+	ZXIC_UINT32 pkt_data6;
+} DPP_PPU_PPU_PKT_DATA6_T;
+
+typedef struct dpp_ppu_ppu_pkt_data7_t {
+	ZXIC_UINT32 pkt_data7;
+} DPP_PPU_PPU_PKT_DATA7_T;
+
+typedef struct dpp_ppu_ppu_pkt_data8_t {
+	ZXIC_UINT32 pkt_data8;
+} DPP_PPU_PPU_PKT_DATA8_T;
+
+typedef struct dpp_ppu_ppu_pkt_data9_t {
+	ZXIC_UINT32 pkt_data9;
+} DPP_PPU_PPU_PKT_DATA9_T;
+
+typedef struct dpp_ppu_ppu_pkt_data10_t {
+	ZXIC_UINT32 pkt_data10;
+} DPP_PPU_PPU_PKT_DATA10_T;
+
+typedef struct dpp_ppu_ppu_pkt_data11_t {
+	ZXIC_UINT32 pkt_data11;
+} DPP_PPU_PPU_PKT_DATA11_T;
+
+typedef struct dpp_ppu_ppu_pkt_data12_t {
+	ZXIC_UINT32 pkt_data12;
+} DPP_PPU_PPU_PKT_DATA12_T;
+
+typedef struct dpp_ppu_ppu_pkt_data13_t {
+	ZXIC_UINT32 pkt_data13;
+} DPP_PPU_PPU_PKT_DATA13_T;
+
+typedef struct dpp_ppu_ppu_pkt_data14_t {
+	ZXIC_UINT32 pkt_data14;
+} DPP_PPU_PPU_PKT_DATA14_T;
+
+typedef struct dpp_ppu_ppu_pkt_data15_t {
+	ZXIC_UINT32 pkt_data15;
+} DPP_PPU_PPU_PKT_DATA15_T;
+
+typedef struct dpp_ppu_ppu_pkt_data16_t {
+	ZXIC_UINT32 pkt_data16;
+} DPP_PPU_PPU_PKT_DATA16_T;
+
+typedef struct dpp_ppu_ppu_pkt_data17_t {
+	ZXIC_UINT32 pkt_data17;
+} DPP_PPU_PPU_PKT_DATA17_T;
+
+typedef struct dpp_ppu_ppu_pkt_data18_t {
+	ZXIC_UINT32 pkt_data18;
+} DPP_PPU_PPU_PKT_DATA18_T;
+
+typedef struct dpp_ppu_ppu_pkt_data19_t {
+	ZXIC_UINT32 pkt_data19;
+} DPP_PPU_PPU_PKT_DATA19_T;
+
+typedef struct dpp_ppu_ppu_pkt_data20_t {
+	ZXIC_UINT32 pkt_data20;
+} DPP_PPU_PPU_PKT_DATA20_T;
+
+typedef struct dpp_ppu_ppu_pkt_data21_t {
+	ZXIC_UINT32 pkt_data21;
+} DPP_PPU_PPU_PKT_DATA21_T;
+
+typedef struct dpp_ppu_ppu_pkt_data22_t {
+	ZXIC_UINT32 pkt_data22;
+} DPP_PPU_PPU_PKT_DATA22_T;
+
+typedef struct dpp_ppu_ppu_pkt_data23_t {
+	ZXIC_UINT32 pkt_data23;
+} DPP_PPU_PPU_PKT_DATA23_T;
+
+typedef struct dpp_ppu_ppu_pkt_data24_t {
+	ZXIC_UINT32 pkt_data24;
+} DPP_PPU_PPU_PKT_DATA24_T;
+
+typedef struct dpp_ppu_ppu_pkt_data25_t {
+	ZXIC_UINT32 pkt_data25;
+} DPP_PPU_PPU_PKT_DATA25_T;
+
+typedef struct dpp_ppu_ppu_pkt_data26_t {
+	ZXIC_UINT32 pkt_data26;
+} DPP_PPU_PPU_PKT_DATA26_T;
+
+typedef struct dpp_ppu_ppu_pkt_data27_t {
+	ZXIC_UINT32 pkt_data27;
+} DPP_PPU_PPU_PKT_DATA27_T;
+
+typedef struct dpp_ppu_ppu_pkt_data28_t {
+	ZXIC_UINT32 pkt_data28;
+} DPP_PPU_PPU_PKT_DATA28_T;
+
+typedef struct dpp_ppu_ppu_pkt_data29_t {
+	ZXIC_UINT32 pkt_data29;
+} DPP_PPU_PPU_PKT_DATA29_T;
+
+typedef struct dpp_ppu_ppu_pkt_data30_t {
+	ZXIC_UINT32 pkt_data30;
+} DPP_PPU_PPU_PKT_DATA30_T;
+
+typedef struct dpp_ppu_ppu_pkt_data31_t {
+	ZXIC_UINT32 pkt_data31;
+} DPP_PPU_PPU_PKT_DATA31_T;
+
+typedef struct dpp_ppu_ppu_pkt_data32_t {
+	ZXIC_UINT32 pkt_data32;
+} DPP_PPU_PPU_PKT_DATA32_T;
+
+typedef struct dpp_ppu_ppu_pkt_data33_t {
+	ZXIC_UINT32 pkt_data33;
+} DPP_PPU_PPU_PKT_DATA33_T;
+
+typedef struct dpp_ppu_ppu_pkt_data34_t {
+	ZXIC_UINT32 pkt_data34;
+} DPP_PPU_PPU_PKT_DATA34_T;
+
+typedef struct dpp_ppu_ppu_pkt_data35_t {
+	ZXIC_UINT32 pkt_data35;
+} DPP_PPU_PPU_PKT_DATA35_T;
+
+typedef struct dpp_ppu_ppu_pkt_data36_t {
+	ZXIC_UINT32 pkt_data36;
+} DPP_PPU_PPU_PKT_DATA36_T;
+
+typedef struct dpp_ppu_ppu_pkt_data37_t {
+	ZXIC_UINT32 pkt_data37;
+} DPP_PPU_PPU_PKT_DATA37_T;
+
+typedef struct dpp_ppu_ppu_pkt_data38_t {
+	ZXIC_UINT32 pkt_data38;
+} DPP_PPU_PPU_PKT_DATA38_T;
+
+typedef struct dpp_ppu_ppu_pkt_data39_t {
+	ZXIC_UINT32 pkt_data39;
+} DPP_PPU_PPU_PKT_DATA39_T;
+
+typedef struct dpp_ppu_ppu_pkt_data40_t {
+	ZXIC_UINT32 pkt_data40;
+} DPP_PPU_PPU_PKT_DATA40_T;
+
+typedef struct dpp_ppu_ppu_pkt_data41_t {
+	ZXIC_UINT32 pkt_data41;
+} DPP_PPU_PPU_PKT_DATA41_T;
+
+typedef struct dpp_ppu_ppu_pkt_data42_t {
+	ZXIC_UINT32 pkt_data42;
+} DPP_PPU_PPU_PKT_DATA42_T;
+
+typedef struct dpp_ppu_ppu_pkt_data43_t {
+	ZXIC_UINT32 pkt_data43;
+} DPP_PPU_PPU_PKT_DATA43_T;
+
+typedef struct dpp_ppu_ppu_pkt_data44_t {
+	ZXIC_UINT32 pkt_data44;
+} DPP_PPU_PPU_PKT_DATA44_T;
+
+typedef struct dpp_ppu_ppu_pkt_data45_t {
+	ZXIC_UINT32 pkt_data45;
+} DPP_PPU_PPU_PKT_DATA45_T;
+
+typedef struct dpp_ppu_ppu_pkt_data46_t {
+	ZXIC_UINT32 pkt_data46;
+} DPP_PPU_PPU_PKT_DATA46_T;
+
+typedef struct dpp_ppu_ppu_pkt_data47_t {
+	ZXIC_UINT32 pkt_data47;
+} DPP_PPU_PPU_PKT_DATA47_T;
+
+typedef struct dpp_ppu_ppu_pkt_data48_t {
+	ZXIC_UINT32 pkt_data48;
+} DPP_PPU_PPU_PKT_DATA48_T;
+
+typedef struct dpp_ppu_ppu_pkt_data49_t {
+	ZXIC_UINT32 pkt_data49;
+} DPP_PPU_PPU_PKT_DATA49_T;
+
+typedef struct dpp_ppu_ppu_pkt_data50_t {
+	ZXIC_UINT32 pkt_data50;
+} DPP_PPU_PPU_PKT_DATA50_T;
+
+typedef struct dpp_ppu_ppu_pkt_data51_t {
+	ZXIC_UINT32 pkt_data51;
+} DPP_PPU_PPU_PKT_DATA51_T;
+
+typedef struct dpp_ppu_ppu_pkt_data52_t {
+	ZXIC_UINT32 pkt_data52;
+} DPP_PPU_PPU_PKT_DATA52_T;
+
+typedef struct dpp_ppu_ppu_pkt_data53_t {
+	ZXIC_UINT32 pkt_data53;
+} DPP_PPU_PPU_PKT_DATA53_T;
+
+typedef struct dpp_ppu_ppu_pkt_data54_t {
+	ZXIC_UINT32 pkt_data54;
+} DPP_PPU_PPU_PKT_DATA54_T;
+
+typedef struct dpp_ppu_ppu_pkt_data55_t {
+	ZXIC_UINT32 pkt_data55;
+} DPP_PPU_PPU_PKT_DATA55_T;
+
+typedef struct dpp_ppu_ppu_pkt_data56_t {
+	ZXIC_UINT32 pkt_data56;
+} DPP_PPU_PPU_PKT_DATA56_T;
+
+typedef struct dpp_ppu_ppu_pkt_data57_t {
+	ZXIC_UINT32 pkt_data57;
+} DPP_PPU_PPU_PKT_DATA57_T;
+
+typedef struct dpp_ppu_ppu_pkt_data58_t {
+	ZXIC_UINT32 pkt_data58;
+} DPP_PPU_PPU_PKT_DATA58_T;
+
+typedef struct dpp_ppu_ppu_pkt_data59_t {
+	ZXIC_UINT32 pkt_data59;
+} DPP_PPU_PPU_PKT_DATA59_T;
+
+typedef struct dpp_ppu_ppu_pkt_data60_t {
+	ZXIC_UINT32 pkt_data60;
+} DPP_PPU_PPU_PKT_DATA60_T;
+
+typedef struct dpp_ppu_ppu_pkt_data61_t {
+	ZXIC_UINT32 pkt_data61;
+} DPP_PPU_PPU_PKT_DATA61_T;
+
+typedef struct dpp_ppu_ppu_pkt_data62_t {
+	ZXIC_UINT32 pkt_data62;
+} DPP_PPU_PPU_PKT_DATA62_T;
+
+typedef struct dpp_ppu_ppu_pkt_data63_t {
+	ZXIC_UINT32 pkt_data63;
+} DPP_PPU_PPU_PKT_DATA63_T;
+
+typedef struct dpp_ppu_ppu_pkt_data64_t {
+	ZXIC_UINT32 pkt_data64;
+} DPP_PPU_PPU_PKT_DATA64_T;
+
+typedef struct dpp_ppu_ppu_pkt_data65_t {
+	ZXIC_UINT32 pkt_data65;
+} DPP_PPU_PPU_PKT_DATA65_T;
+
+typedef struct dpp_ppu_ppu_pkt_data66_t {
+	ZXIC_UINT32 pkt_data66;
+} DPP_PPU_PPU_PKT_DATA66_T;
+
+typedef struct dpp_ppu_ppu_pkt_data67_t {
+	ZXIC_UINT32 pkt_data67;
+} DPP_PPU_PPU_PKT_DATA67_T;
+
+typedef struct dpp_ppu_ppu_pkt_data68_t {
+	ZXIC_UINT32 pkt_data68;
+} DPP_PPU_PPU_PKT_DATA68_T;
+
+typedef struct dpp_ppu_ppu_pkt_data69_t {
+	ZXIC_UINT32 pkt_data69;
+} DPP_PPU_PPU_PKT_DATA69_T;
+
+typedef struct dpp_ppu_ppu_pkt_data70_t {
+	ZXIC_UINT32 pkt_data70;
+} DPP_PPU_PPU_PKT_DATA70_T;
+
+typedef struct dpp_ppu_ppu_pkt_data71_t {
+	ZXIC_UINT32 pkt_data71;
+} DPP_PPU_PPU_PKT_DATA71_T;
+
+typedef struct dpp_ppu_ppu_pkt_data72_t {
+	ZXIC_UINT32 pkt_data72;
+} DPP_PPU_PPU_PKT_DATA72_T;
+
+typedef struct dpp_ppu_ppu_pkt_data73_t {
+	ZXIC_UINT32 pkt_data73;
+} DPP_PPU_PPU_PKT_DATA73_T;
+
+typedef struct dpp_ppu_ppu_pkt_data74_t {
+	ZXIC_UINT32 pkt_data74;
+} DPP_PPU_PPU_PKT_DATA74_T;
+
+typedef struct dpp_ppu_ppu_pkt_data75_t {
+	ZXIC_UINT32 pkt_data75;
+} DPP_PPU_PPU_PKT_DATA75_T;
+
+typedef struct dpp_ppu_ppu_pkt_data76_t {
+	ZXIC_UINT32 pkt_data76;
+} DPP_PPU_PPU_PKT_DATA76_T;
+
+typedef struct dpp_ppu_ppu_pkt_data77_t {
+	ZXIC_UINT32 pkt_data77;
+} DPP_PPU_PPU_PKT_DATA77_T;
+
+typedef struct dpp_ppu_ppu_pkt_data78_t {
+	ZXIC_UINT32 pkt_data78;
+} DPP_PPU_PPU_PKT_DATA78_T;
+
+typedef struct dpp_ppu_ppu_pkt_data79_t {
+	ZXIC_UINT32 pkt_data79;
+} DPP_PPU_PPU_PKT_DATA79_T;
+
+typedef struct dpp_ppu_ppu_pkt_data80_t {
+	ZXIC_UINT32 pkt_data80;
+} DPP_PPU_PPU_PKT_DATA80_T;
+
+typedef struct dpp_ppu_ppu_pkt_data81_t {
+	ZXIC_UINT32 pkt_data81;
+} DPP_PPU_PPU_PKT_DATA81_T;
+
+typedef struct dpp_ppu_ppu_pkt_data82_t {
+	ZXIC_UINT32 pkt_data82;
+} DPP_PPU_PPU_PKT_DATA82_T;
+
+typedef struct dpp_ppu_ppu_pkt_data83_t {
+	ZXIC_UINT32 pkt_data83;
+} DPP_PPU_PPU_PKT_DATA83_T;
+
+typedef struct dpp_ppu_ppu_pkt_data84_t {
+	ZXIC_UINT32 pkt_data84;
+} DPP_PPU_PPU_PKT_DATA84_T;
+
+typedef struct dpp_ppu_ppu_pkt_data85_t {
+	ZXIC_UINT32 pkt_data85;
+} DPP_PPU_PPU_PKT_DATA85_T;
+
+typedef struct dpp_ppu_ppu_pkt_data86_t {
+	ZXIC_UINT32 pkt_data86;
+} DPP_PPU_PPU_PKT_DATA86_T;
+
+typedef struct dpp_ppu_ppu_pkt_data87_t {
+	ZXIC_UINT32 pkt_data87;
+} DPP_PPU_PPU_PKT_DATA87_T;
+
+typedef struct dpp_ppu_ppu_pkt_data88_t {
+	ZXIC_UINT32 pkt_data88;
+} DPP_PPU_PPU_PKT_DATA88_T;
+
+typedef struct dpp_ppu_ppu_pkt_data89_t {
+	ZXIC_UINT32 pkt_data89;
+} DPP_PPU_PPU_PKT_DATA89_T;
+
+typedef struct dpp_ppu_ppu_pkt_data90_t {
+	ZXIC_UINT32 pkt_data90;
+} DPP_PPU_PPU_PKT_DATA90_T;
+
+typedef struct dpp_ppu_ppu_pkt_data91_t {
+	ZXIC_UINT32 pkt_data91;
+} DPP_PPU_PPU_PKT_DATA91_T;
+
+typedef struct dpp_ppu_ppu_pkt_data92_t {
+	ZXIC_UINT32 pkt_data92;
+} DPP_PPU_PPU_PKT_DATA92_T;
+
+typedef struct dpp_ppu_ppu_pkt_data93_t {
+	ZXIC_UINT32 pkt_data93;
+} DPP_PPU_PPU_PKT_DATA93_T;
+
+typedef struct dpp_ppu_ppu_pkt_data94_t {
+	ZXIC_UINT32 pkt_data94;
+} DPP_PPU_PPU_PKT_DATA94_T;
+
+typedef struct dpp_ppu_ppu_pkt_data95_t {
+	ZXIC_UINT32 pkt_data95;
+} DPP_PPU_PPU_PKT_DATA95_T;
+
+typedef struct dpp_ppu_ppu_pkt_data96_t {
+	ZXIC_UINT32 pkt_data96;
+} DPP_PPU_PPU_PKT_DATA96_T;
+
+typedef struct dpp_ppu_ppu_pkt_data97_t {
+	ZXIC_UINT32 pkt_data97;
+} DPP_PPU_PPU_PKT_DATA97_T;
+
+typedef struct dpp_ppu_ppu_pkt_data98_t {
+	ZXIC_UINT32 pkt_data98;
+} DPP_PPU_PPU_PKT_DATA98_T;
+
+typedef struct dpp_ppu_ppu_pkt_data99_t {
+	ZXIC_UINT32 pkt_data99;
+} DPP_PPU_PPU_PKT_DATA99_T;
+
+typedef struct dpp_ppu_ppu_pkt_data100_t {
+	ZXIC_UINT32 pkt_data100;
+} DPP_PPU_PPU_PKT_DATA100_T;
+
+typedef struct dpp_ppu_ppu_pkt_data101_t {
+	ZXIC_UINT32 pkt_data101;
+} DPP_PPU_PPU_PKT_DATA101_T;
+
+typedef struct dpp_ppu_ppu_pkt_data102_t {
+	ZXIC_UINT32 pkt_data102;
+} DPP_PPU_PPU_PKT_DATA102_T;
+
+typedef struct dpp_ppu_ppu_pkt_data103_t {
+	ZXIC_UINT32 pkt_data103;
+} DPP_PPU_PPU_PKT_DATA103_T;
+
+typedef struct dpp_ppu_ppu_pkt_data104_t {
+	ZXIC_UINT32 pkt_data104;
+} DPP_PPU_PPU_PKT_DATA104_T;
+
+typedef struct dpp_ppu_ppu_pkt_data105_t {
+	ZXIC_UINT32 pkt_data105;
+} DPP_PPU_PPU_PKT_DATA105_T;
+
+typedef struct dpp_ppu_ppu_pkt_data106_t {
+	ZXIC_UINT32 pkt_data106;
+} DPP_PPU_PPU_PKT_DATA106_T;
+
+typedef struct dpp_ppu_ppu_pkt_data107_t {
+	ZXIC_UINT32 pkt_data107;
+} DPP_PPU_PPU_PKT_DATA107_T;
+
+typedef struct dpp_ppu_ppu_pkt_data108_t {
+	ZXIC_UINT32 pkt_data108;
+} DPP_PPU_PPU_PKT_DATA108_T;
+
+typedef struct dpp_ppu_ppu_pkt_data109_t {
+	ZXIC_UINT32 pkt_data109;
+} DPP_PPU_PPU_PKT_DATA109_T;
+
+typedef struct dpp_ppu_ppu_pkt_data110_t {
+	ZXIC_UINT32 pkt_data110;
+} DPP_PPU_PPU_PKT_DATA110_T;
+
+typedef struct dpp_ppu_ppu_pkt_data111_t {
+	ZXIC_UINT32 pkt_data111;
+} DPP_PPU_PPU_PKT_DATA111_T;
+
+typedef struct dpp_ppu_ppu_pkt_data112_t {
+	ZXIC_UINT32 pkt_data112;
+} DPP_PPU_PPU_PKT_DATA112_T;
+
+typedef struct dpp_ppu_ppu_pkt_data113_t {
+	ZXIC_UINT32 pkt_data113;
+} DPP_PPU_PPU_PKT_DATA113_T;
+
+typedef struct dpp_ppu_ppu_pkt_data114_t {
+	ZXIC_UINT32 pkt_data114;
+} DPP_PPU_PPU_PKT_DATA114_T;
+
+typedef struct dpp_ppu_ppu_pkt_data115_t {
+	ZXIC_UINT32 pkt_data115;
+} DPP_PPU_PPU_PKT_DATA115_T;
+
+typedef struct dpp_ppu_ppu_pkt_data116_t {
+	ZXIC_UINT32 pkt_data116;
+} DPP_PPU_PPU_PKT_DATA116_T;
+
+typedef struct dpp_ppu_ppu_pkt_data117_t {
+	ZXIC_UINT32 pkt_data117;
+} DPP_PPU_PPU_PKT_DATA117_T;
+
+typedef struct dpp_ppu_ppu_pkt_data118_t {
+	ZXIC_UINT32 pkt_data118;
+} DPP_PPU_PPU_PKT_DATA118_T;
+
+typedef struct dpp_ppu_ppu_pkt_data119_t {
+	ZXIC_UINT32 pkt_data119;
+} DPP_PPU_PPU_PKT_DATA119_T;
+
+typedef struct dpp_ppu_ppu_pkt_data120_t {
+	ZXIC_UINT32 pkt_data120;
+} DPP_PPU_PPU_PKT_DATA120_T;
+
+typedef struct dpp_ppu_ppu_pkt_data121_t {
+	ZXIC_UINT32 pkt_data121;
+} DPP_PPU_PPU_PKT_DATA121_T;
+
+typedef struct dpp_ppu_ppu_pkt_data122_t {
+	ZXIC_UINT32 pkt_data122;
+} DPP_PPU_PPU_PKT_DATA122_T;
+
+typedef struct dpp_ppu_ppu_pkt_data123_t {
+	ZXIC_UINT32 pkt_data123;
+} DPP_PPU_PPU_PKT_DATA123_T;
+
+typedef struct dpp_ppu_ppu_pkt_data124_t {
+	ZXIC_UINT32 pkt_data124;
+} DPP_PPU_PPU_PKT_DATA124_T;
+
+typedef struct dpp_ppu_ppu_pkt_data125_t {
+	ZXIC_UINT32 pkt_data125;
+} DPP_PPU_PPU_PKT_DATA125_T;
+
+typedef struct dpp_ppu_ppu_pkt_data126_t {
+	ZXIC_UINT32 pkt_data126;
+} DPP_PPU_PPU_PKT_DATA126_T;
+
+typedef struct dpp_ppu_ppu_pkt_data127_t {
+	ZXIC_UINT32 pkt_data127;
+} DPP_PPU_PPU_PKT_DATA127_T;
+
+typedef struct dpp_ppu_ppu_spr0_t {
+	ZXIC_UINT32 spr0;
+} DPP_PPU_PPU_SPR0_T;
+
+typedef struct dpp_ppu_ppu_spr1_t {
+	ZXIC_UINT32 spr1;
+} DPP_PPU_PPU_SPR1_T;
+
+typedef struct dpp_ppu_ppu_spr2_t {
+	ZXIC_UINT32 spr2;
+} DPP_PPU_PPU_SPR2_T;
+
+typedef struct dpp_ppu_ppu_spr3_t {
+	ZXIC_UINT32 spr3;
+} DPP_PPU_PPU_SPR3_T;
+
+typedef struct dpp_ppu_ppu_spr4_t {
+	ZXIC_UINT32 spr4;
+} DPP_PPU_PPU_SPR4_T;
+
+typedef struct dpp_ppu_ppu_spr5_t {
+	ZXIC_UINT32 spr5;
+} DPP_PPU_PPU_SPR5_T;
+
+typedef struct dpp_ppu_ppu_spr6_t {
+	ZXIC_UINT32 spr6;
+} DPP_PPU_PPU_SPR6_T;
+
+typedef struct dpp_ppu_ppu_spr7_t {
+	ZXIC_UINT32 spr7;
+} DPP_PPU_PPU_SPR7_T;
+
+typedef struct dpp_ppu_ppu_spr8_t {
+	ZXIC_UINT32 spr8;
+} DPP_PPU_PPU_SPR8_T;
+
+typedef struct dpp_ppu_ppu_spr9_t {
+	ZXIC_UINT32 spr9;
+} DPP_PPU_PPU_SPR9_T;
+
+typedef struct dpp_ppu_ppu_spr10_t {
+	ZXIC_UINT32 spr10;
+} DPP_PPU_PPU_SPR10_T;
+
+typedef struct dpp_ppu_ppu_spr11_t {
+	ZXIC_UINT32 spr11;
+} DPP_PPU_PPU_SPR11_T;
+
+typedef struct dpp_ppu_ppu_spr12_t {
+	ZXIC_UINT32 spr12;
+} DPP_PPU_PPU_SPR12_T;
+
+typedef struct dpp_ppu_ppu_spr13_t {
+	ZXIC_UINT32 spr13;
+} DPP_PPU_PPU_SPR13_T;
+
+typedef struct dpp_ppu_ppu_spr14_t {
+	ZXIC_UINT32 spr14;
+} DPP_PPU_PPU_SPR14_T;
+
+typedef struct dpp_ppu_ppu_spr15_t {
+	ZXIC_UINT32 spr15;
+} DPP_PPU_PPU_SPR15_T;
+
+typedef struct dpp_ppu_ppu_spr16_t {
+	ZXIC_UINT32 spr16;
+} DPP_PPU_PPU_SPR16_T;
+
+typedef struct dpp_ppu_ppu_spr17_t {
+	ZXIC_UINT32 spr17;
+} DPP_PPU_PPU_SPR17_T;
+
+typedef struct dpp_ppu_ppu_spr18_t {
+	ZXIC_UINT32 spr18;
+} DPP_PPU_PPU_SPR18_T;
+
+typedef struct dpp_ppu_ppu_spr19_t {
+	ZXIC_UINT32 spr19;
+} DPP_PPU_PPU_SPR19_T;
+
+typedef struct dpp_ppu_ppu_spr20_t {
+	ZXIC_UINT32 spr20;
+} DPP_PPU_PPU_SPR20_T;
+
+typedef struct dpp_ppu_ppu_spr21_t {
+	ZXIC_UINT32 spr21;
+} DPP_PPU_PPU_SPR21_T;
+
+typedef struct dpp_ppu_ppu_spr22_t {
+	ZXIC_UINT32 spr22;
+} DPP_PPU_PPU_SPR22_T;
+
+typedef struct dpp_ppu_ppu_spr23_t {
+	ZXIC_UINT32 spr23;
+} DPP_PPU_PPU_SPR23_T;
+
+typedef struct dpp_ppu_ppu_spr24_t {
+	ZXIC_UINT32 spr24;
+} DPP_PPU_PPU_SPR24_T;
+
+typedef struct dpp_ppu_ppu_spr25_t {
+	ZXIC_UINT32 spr25;
+} DPP_PPU_PPU_SPR25_T;
+
+typedef struct dpp_ppu_ppu_spr26_t {
+	ZXIC_UINT32 spr26;
+} DPP_PPU_PPU_SPR26_T;
+
+typedef struct dpp_ppu_ppu_spr27_t {
+	ZXIC_UINT32 spr27;
+} DPP_PPU_PPU_SPR27_T;
+
+typedef struct dpp_ppu_ppu_spr28_t {
+	ZXIC_UINT32 spr28;
+} DPP_PPU_PPU_SPR28_T;
+
+typedef struct dpp_ppu_ppu_spr29_t {
+	ZXIC_UINT32 spr29;
+} DPP_PPU_PPU_SPR29_T;
+
+typedef struct dpp_ppu_ppu_spr30_t {
+	ZXIC_UINT32 spr30;
+} DPP_PPU_PPU_SPR30_T;
+
+typedef struct dpp_ppu_ppu_spr31_t {
+	ZXIC_UINT32 spr31;
+} DPP_PPU_PPU_SPR31_T;
+
+typedef struct dpp_ppu_ppu_rsp0_t {
+	ZXIC_UINT32 rsp0;
+} DPP_PPU_PPU_RSP0_T;
+
+typedef struct dpp_ppu_ppu_rsp1_t {
+	ZXIC_UINT32 rsp1;
+} DPP_PPU_PPU_RSP1_T;
+
+typedef struct dpp_ppu_ppu_rsp2_t {
+	ZXIC_UINT32 rsp2;
+} DPP_PPU_PPU_RSP2_T;
+
+typedef struct dpp_ppu_ppu_rsp3_t {
+	ZXIC_UINT32 rsp3;
+} DPP_PPU_PPU_RSP3_T;
+
+typedef struct dpp_ppu_ppu_rsp4_t {
+	ZXIC_UINT32 rsp4;
+} DPP_PPU_PPU_RSP4_T;
+
+typedef struct dpp_ppu_ppu_rsp5_t {
+	ZXIC_UINT32 rsp5;
+} DPP_PPU_PPU_RSP5_T;
+
+typedef struct dpp_ppu_ppu_rsp6_t {
+	ZXIC_UINT32 rsp6;
+} DPP_PPU_PPU_RSP6_T;
+
+typedef struct dpp_ppu_ppu_rsp7_t {
+	ZXIC_UINT32 rsp7;
+} DPP_PPU_PPU_RSP7_T;
+
+typedef struct dpp_ppu_ppu_rsp8_t {
+	ZXIC_UINT32 rsp8;
+} DPP_PPU_PPU_RSP8_T;
+
+typedef struct dpp_ppu_ppu_rsp9_t {
+	ZXIC_UINT32 rsp9;
+} DPP_PPU_PPU_RSP9_T;
+
+typedef struct dpp_ppu_ppu_rsp10_t {
+	ZXIC_UINT32 rsp10;
+} DPP_PPU_PPU_RSP10_T;
+
+typedef struct dpp_ppu_ppu_rsp11_t {
+	ZXIC_UINT32 rsp11;
+} DPP_PPU_PPU_RSP11_T;
+
+typedef struct dpp_ppu_ppu_rsp12_t {
+	ZXIC_UINT32 rsp12;
+} DPP_PPU_PPU_RSP12_T;
+
+typedef struct dpp_ppu_ppu_rsp13_t {
+	ZXIC_UINT32 rsp13;
+} DPP_PPU_PPU_RSP13_T;
+
+typedef struct dpp_ppu_ppu_rsp14_t {
+	ZXIC_UINT32 rsp14;
+} DPP_PPU_PPU_RSP14_T;
+
+typedef struct dpp_ppu_ppu_rsp15_t {
+	ZXIC_UINT32 rsp15;
+} DPP_PPU_PPU_RSP15_T;
+
+typedef struct dpp_ppu_ppu_rsp16_t {
+	ZXIC_UINT32 rsp16;
+} DPP_PPU_PPU_RSP16_T;
+
+typedef struct dpp_ppu_ppu_rsp17_t {
+	ZXIC_UINT32 rsp17;
+} DPP_PPU_PPU_RSP17_T;
+
+typedef struct dpp_ppu_ppu_rsp18_t {
+	ZXIC_UINT32 rsp18;
+} DPP_PPU_PPU_RSP18_T;
+
+typedef struct dpp_ppu_ppu_rsp19_t {
+	ZXIC_UINT32 rsp19;
+} DPP_PPU_PPU_RSP19_T;
+
+typedef struct dpp_ppu_ppu_rsp20_t {
+	ZXIC_UINT32 rsp20;
+} DPP_PPU_PPU_RSP20_T;
+
+typedef struct dpp_ppu_ppu_rsp21_t {
+	ZXIC_UINT32 rsp21;
+} DPP_PPU_PPU_RSP21_T;
+
+typedef struct dpp_ppu_ppu_rsp22_t {
+	ZXIC_UINT32 rsp22;
+} DPP_PPU_PPU_RSP22_T;
+
+typedef struct dpp_ppu_ppu_rsp23_t {
+	ZXIC_UINT32 rsp23;
+} DPP_PPU_PPU_RSP23_T;
+
+typedef struct dpp_ppu_ppu_rsp24_t {
+	ZXIC_UINT32 rsp24;
+} DPP_PPU_PPU_RSP24_T;
+
+typedef struct dpp_ppu_ppu_rsp25_t {
+	ZXIC_UINT32 rsp25;
+} DPP_PPU_PPU_RSP25_T;
+
+typedef struct dpp_ppu_ppu_rsp26_t {
+	ZXIC_UINT32 rsp26;
+} DPP_PPU_PPU_RSP26_T;
+
+typedef struct dpp_ppu_ppu_rsp27_t {
+	ZXIC_UINT32 rsp27;
+} DPP_PPU_PPU_RSP27_T;
+
+typedef struct dpp_ppu_ppu_rsp28_t {
+	ZXIC_UINT32 rsp28;
+} DPP_PPU_PPU_RSP28_T;
+
+typedef struct dpp_ppu_ppu_rsp29_t {
+	ZXIC_UINT32 rsp29;
+} DPP_PPU_PPU_RSP29_T;
+
+typedef struct dpp_ppu_ppu_rsp30_t {
+	ZXIC_UINT32 rsp30;
+} DPP_PPU_PPU_RSP30_T;
+
+typedef struct dpp_ppu_ppu_rsp31_t {
+	ZXIC_UINT32 rsp31;
+} DPP_PPU_PPU_RSP31_T;
+
+typedef struct dpp_ppu_ppu_key0_t {
+	ZXIC_UINT32 key0;
+} DPP_PPU_PPU_KEY0_T;
+
+typedef struct dpp_ppu_ppu_key1_t {
+	ZXIC_UINT32 key1;
+} DPP_PPU_PPU_KEY1_T;
+
+typedef struct dpp_ppu_ppu_key2_t {
+	ZXIC_UINT32 key2;
+} DPP_PPU_PPU_KEY2_T;
+
+typedef struct dpp_ppu_ppu_key3_t {
+	ZXIC_UINT32 key3;
+} DPP_PPU_PPU_KEY3_T;
+
+typedef struct dpp_ppu_ppu_key4_t {
+	ZXIC_UINT32 key4;
+} DPP_PPU_PPU_KEY4_T;
+
+typedef struct dpp_ppu_ppu_key5_t {
+	ZXIC_UINT32 key5;
+} DPP_PPU_PPU_KEY5_T;
+
+typedef struct dpp_ppu_ppu_key6_t {
+	ZXIC_UINT32 key6;
+} DPP_PPU_PPU_KEY6_T;
+
+typedef struct dpp_ppu_ppu_key7_t {
+	ZXIC_UINT32 key7;
+} DPP_PPU_PPU_KEY7_T;
+
+typedef struct dpp_ppu_ppu_key8_t {
+	ZXIC_UINT32 key8;
+} DPP_PPU_PPU_KEY8_T;
+
+typedef struct dpp_ppu_ppu_key9_t {
+	ZXIC_UINT32 key9;
+} DPP_PPU_PPU_KEY9_T;
+
+typedef struct dpp_ppu_ppu_key10_t {
+	ZXIC_UINT32 key10;
+} DPP_PPU_PPU_KEY10_T;
+
+typedef struct dpp_ppu_ppu_key11_t {
+	ZXIC_UINT32 key11;
+} DPP_PPU_PPU_KEY11_T;
+
+typedef struct dpp_ppu_ppu_key12_t {
+	ZXIC_UINT32 key12;
+} DPP_PPU_PPU_KEY12_T;
+
+typedef struct dpp_ppu_ppu_key13_t {
+	ZXIC_UINT32 key13;
+} DPP_PPU_PPU_KEY13_T;
+
+typedef struct dpp_ppu_ppu_key14_t {
+	ZXIC_UINT32 key14;
+} DPP_PPU_PPU_KEY14_T;
+
+typedef struct dpp_ppu_ppu_key15_t {
+	ZXIC_UINT32 key15;
+} DPP_PPU_PPU_KEY15_T;
+
+typedef struct dpp_ppu_ppu_key16_t {
+	ZXIC_UINT32 key16;
+} DPP_PPU_PPU_KEY16_T;
+
+typedef struct dpp_ppu_ppu_key17_t {
+	ZXIC_UINT32 key17;
+} DPP_PPU_PPU_KEY17_T;
+
+typedef struct dpp_ppu_ppu_key18_t {
+	ZXIC_UINT32 key18;
+} DPP_PPU_PPU_KEY18_T;
+
+typedef struct dpp_ppu_ppu_key19_t {
+	ZXIC_UINT32 key19;
+} DPP_PPU_PPU_KEY19_T;
+
+typedef struct dpp_ppu_ppu_flag_t {
+	ZXIC_UINT32 me_num;
+	ZXIC_UINT32 thread_num;
+	ZXIC_UINT32 flag;
+} DPP_PPU_PPU_FLAG_T;
+
+typedef struct dpp_ppu_cluster_int_1200m_flag_t {
+	ZXIC_UINT32 me7_interrupt_flag;
+	ZXIC_UINT32 me6_interrupt_flag;
+	ZXIC_UINT32 me5_interrupt_flag;
+	ZXIC_UINT32 me4_interrupt_flag;
+	ZXIC_UINT32 me3_interrupt_flag;
+	ZXIC_UINT32 me2_interrupt_flag;
+	ZXIC_UINT32 me1_interrupt_flag;
+	ZXIC_UINT32 me0_interrupt_flag;
+} DPP_PPU_CLUSTER_INT_1200M_FLAG_T;
+
+typedef struct dpp_ppu_cluster_bp_instr_l_t {
+	ZXIC_UINT32 bp_instr_l;
+} DPP_PPU_CLUSTER_BP_INSTR_L_T;
+
+typedef struct dpp_ppu_cluster_bp_instr_h_t {
+	ZXIC_UINT32 bp_instr_h;
+} DPP_PPU_CLUSTER_BP_INSTR_H_T;
+
+typedef struct dpp_ppu_cluster_bp_addr_t {
+	ZXIC_UINT32 bp_addr;
+} DPP_PPU_CLUSTER_BP_ADDR_T;
+
+typedef struct dpp_ppu_cluster_drr_t {
+	ZXIC_UINT32 drr;
+} DPP_PPU_CLUSTER_DRR_T;
+
+typedef struct dpp_ppu_cluster_dsr_t {
+	ZXIC_UINT32 dsr;
+} DPP_PPU_CLUSTER_DSR_T;
+
+typedef struct dpp_ppu_cluster_dbg_rtl_date_t {
+	ZXIC_UINT32 dbg_rtl_date;
+} DPP_PPU_CLUSTER_DBG_RTL_DATE_T;
+
+typedef struct dpp_ppu_cluster_me_continue_t {
+	ZXIC_UINT32 me_continue;
+} DPP_PPU_CLUSTER_ME_CONTINUE_T;
+
+typedef struct dpp_ppu_cluster_me_step_t {
+	ZXIC_UINT32 me_step;
+} DPP_PPU_CLUSTER_ME_STEP_T;
+
+typedef struct dpp_ppu_cluster_me_refresh_t {
+	ZXIC_UINT32 me_refresh;
+} DPP_PPU_CLUSTER_ME_REFRESH_T;
+
+typedef struct dpp_ppu_cluster_drr_clr_t {
+	ZXIC_UINT32 drr_clr;
+} DPP_PPU_CLUSTER_DRR_CLR_T;
+
+typedef struct dpp_ppu_cluster_me_busy_thresold_t {
+	ZXIC_UINT32 me_busy_thresold;
+} DPP_PPU_CLUSTER_ME_BUSY_THRESOLD_T;
+
+typedef struct dpp_ppu_cluster_int_1200m_sta_t {
+	ZXIC_UINT32 me7_interrupt_sta;
+	ZXIC_UINT32 me6_interrupt_sta;
+	ZXIC_UINT32 me5_interrupt_sta;
+	ZXIC_UINT32 me4_interrupt_sta;
+	ZXIC_UINT32 me3_interrupt_sta;
+	ZXIC_UINT32 me2_interrupt_sta;
+	ZXIC_UINT32 me1_interrupt_sta;
+	ZXIC_UINT32 me0_interrupt_sta;
+} DPP_PPU_CLUSTER_INT_1200M_STA_T;
+
+typedef struct dpp_ppu_cluster_int_1200m_me_fifo_mask_l_t {
+	ZXIC_UINT32 me_free_pkt_q_overflow_mask;
+	ZXIC_UINT32 me_free_pkt_q_underflow_mask;
+	ZXIC_UINT32 me_free_thread_q_overflow_mask;
+	ZXIC_UINT32 me_free_thread_q_underflow_mask;
+	ZXIC_UINT32 me_pkt_in_overflow_mask;
+	ZXIC_UINT32 me_pkt_in_underflow_mask;
+	ZXIC_UINT32 me_rdy_q_overflow_mask;
+	ZXIC_UINT32 me_rdy_q_underflow_mask;
+	ZXIC_UINT32 me_pkt_out_q_overflow_mask;
+	ZXIC_UINT32 me_pkt_out_q_underflow_mask;
+	ZXIC_UINT32 me_continue_q_overflow_mask;
+	ZXIC_UINT32 me_continue_q_underflow_mask;
+	ZXIC_UINT32 me_esrh_q_overflow_mask;
+	ZXIC_UINT32 me_esrh_q_underflow_mask;
+	ZXIC_UINT32 me_isrh_q_overflow_mask;
+	ZXIC_UINT32 me_isrh_q_underflow_mask;
+	ZXIC_UINT32 me_cache_miss_q_overflow_mask;
+	ZXIC_UINT32 me_cache_miss_q_underflow_mask;
+	ZXIC_UINT32 me_base_q_u0_overflow_mask;
+	ZXIC_UINT32 me_base_q_u0_underflow_mask;
+	ZXIC_UINT32 me_base_q_u1_overflow_mask;
+	ZXIC_UINT32 me_base_q_u1_underflow_mask;
+	ZXIC_UINT32 me_base_q_u2_overflow_mask;
+	ZXIC_UINT32 me_base_q_u2_underflow_mask;
+	ZXIC_UINT32 me_base_q_u3_overflow_mask;
+	ZXIC_UINT32 me_base_q_u3_underflow_mask;
+	ZXIC_UINT32 me_reg_pc_q_overflow_mask;
+	ZXIC_UINT32 me_reg_pc_q_underflow_mask;
+	ZXIC_UINT32 me_branch_q_overflow_mask;
+	ZXIC_UINT32 me_branch_q_underflow_mask;
+	ZXIC_UINT32 me_pkt_base_q_overflow_mask;
+	ZXIC_UINT32 me_pkt_base_q_underflow_mask;
+} DPP_PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_L_T;
+
+typedef struct dpp_ppu_cluster_int_1200m_me_fifo_mask_h_t {
+	ZXIC_UINT32 me_except_refetch_pc_overflow_mask;
+	ZXIC_UINT32 me_except_refetch_pc_underflow_mask;
+} DPP_PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_H_T;
+
+typedef struct dpp_ppu_cluster_me_fifo_interrupt_flag_l_t {
+	ZXIC_UINT32 me_free_pkt_q_overflow_flag;
+	ZXIC_UINT32 me_free_pkt_q_underflow_flag;
+	ZXIC_UINT32 me_free_thread_q_overflow_flag;
+	ZXIC_UINT32 me_free_thread_q_underflow_flag;
+	ZXIC_UINT32 me_pkt_in_overflow_flag;
+	ZXIC_UINT32 me_pkt_in_underflow_flag;
+	ZXIC_UINT32 me_rdy_q_overflow_flag;
+	ZXIC_UINT32 me_rdy_q_underflow_flag;
+	ZXIC_UINT32 me_pkt_out_q_overflow_flag;
+	ZXIC_UINT32 me_pkt_out_q_underflow_flag;
+	ZXIC_UINT32 me_continue_q_overflow_flag;
+	ZXIC_UINT32 me_continue_q_underflow_flag;
+	ZXIC_UINT32 me_esrh_q_overflow_flag;
+	ZXIC_UINT32 me_esrh_q_underflow_flag;
+	ZXIC_UINT32 me_isrh_q_overflow_flag;
+	ZXIC_UINT32 me_isrh_q_underflow_flag;
+	ZXIC_UINT32 me_cache_miss_q_overflow_flag;
+	ZXIC_UINT32 me_cache_miss_q_underflow_flag;
+	ZXIC_UINT32 me_base_q_u0_overflow_flag;
+	ZXIC_UINT32 me_base_q_u0_underflow_flag;
+	ZXIC_UINT32 me_base_q_u1_overflow_flag;
+	ZXIC_UINT32 me_base_q_u1_underflow_flag;
+	ZXIC_UINT32 me_base_q_u2_overflow_flag;
+	ZXIC_UINT32 me_base_q_u2_underflow_flag;
+	ZXIC_UINT32 me_base_q_u3_overflow_flag;
+	ZXIC_UINT32 me_base_q_u3_underflow_flag;
+	ZXIC_UINT32 me_reg_pc_q_overflow_flag;
+	ZXIC_UINT32 me_reg_pc_q_underflow_flag;
+	ZXIC_UINT32 me_branch_q_overflow_flag;
+	ZXIC_UINT32 me_branch_q_underflow_flag;
+	ZXIC_UINT32 me_pkt_base_q_overflow_flag;
+	ZXIC_UINT32 me_pkt_base_q_underflow_flag;
+} DPP_PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_L_T;
+
+typedef struct dpp_ppu_cluster_me_fifo_interrupt_flag_h_t {
+	ZXIC_UINT32 me_except_refetch_pc_overflow_flag;
+	ZXIC_UINT32 me_except_refetch_pc_underflow_flag;
+} DPP_PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_H_T;
+
+typedef struct dpp_ppu_cluster_me_fifo_interrupt_sta_l_t {
+	ZXIC_UINT32 me_free_pkt_q_overflow_sta;
+	ZXIC_UINT32 me_free_pkt_q_underflow_sta;
+	ZXIC_UINT32 me_free_thread_q_overflow_sta;
+	ZXIC_UINT32 me_free_thread_q_underflow_sta;
+	ZXIC_UINT32 me_pkt_in_overflow_sta;
+	ZXIC_UINT32 me_pkt_in_underflow_sta;
+	ZXIC_UINT32 me_rdy_q_overflow_sta;
+	ZXIC_UINT32 me_rdy_q_underflow_sta;
+	ZXIC_UINT32 me_pkt_out_q_overflow_sta;
+	ZXIC_UINT32 me_pkt_out_q_underflow_sta;
+	ZXIC_UINT32 me_continue_q_overflow_sta;
+	ZXIC_UINT32 me_continue_q_underflow_sta;
+	ZXIC_UINT32 me_esrh_q_overflow_sta;
+	ZXIC_UINT32 me_esrh_q_underflow_sta;
+	ZXIC_UINT32 me_isrh_q_overflow_sta;
+	ZXIC_UINT32 me_isrh_q_underflow_sta;
+	ZXIC_UINT32 me_cache_miss_q_overflow_sta;
+	ZXIC_UINT32 me_cache_miss_q_underflow_sta;
+	ZXIC_UINT32 me_base_q_u0_overflow_sta;
+	ZXIC_UINT32 me_base_q_u0_underflow_sta;
+	ZXIC_UINT32 me_base_q_u1_overflow_sta;
+	ZXIC_UINT32 me_base_q_u1_underflow_sta;
+	ZXIC_UINT32 me_base_q_u2_overflow_sta;
+	ZXIC_UINT32 me_base_q_u2_underflow_sta;
+	ZXIC_UINT32 me_base_q_u3_overflow_sta;
+	ZXIC_UINT32 me_base_q_u3_underflow_sta;
+	ZXIC_UINT32 me_reg_pc_q_overflow_sta;
+	ZXIC_UINT32 me_reg_pc_q_underflow_sta;
+	ZXIC_UINT32 me_branch_q_overflow_sta;
+	ZXIC_UINT32 me_branch_q_underflow_sta;
+	ZXIC_UINT32 me_pkt_base_q_overflow_sta;
+	ZXIC_UINT32 me_pkt_base_q_underflow_sta;
+} DPP_PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_L_T;
+
+typedef struct dpp_ppu_cluster_me_fifo_interrupt_sta_h_t {
+	ZXIC_UINT32 me_except_refetch_pc_overflow_sta;
+	ZXIC_UINT32 me_except_refetch_pc_underflow_sta;
+} DPP_PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_H_T;
+
+typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_mask_l_t {
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_overflow_mask;
+	ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_underflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_mask;
+	ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_mask;
+} DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_L_T;
+
+typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_mask_h_t {
+	ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_overflow_mask;
+	ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_underflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_mask;
+} DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_H_T;
+
+typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_flag_l_t {
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_overflow_flag;
+	ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_underflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_flag;
+	ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_flag;
+} DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_L_T;
+
+typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_flag_h_t {
+	ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_overflow_flag;
+	ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_underflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag;
+} DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_H_T;
+
+typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_stat_l_t {
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_stat;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_stat;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_stat;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_stat;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_stat;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_stat;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_stat;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_stat;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_stat;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_stat;
+	ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_overflow_stat;
+	ZXIC_UINT32 ise_rsp_ram_free_ptr_u0_underflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_stat;
+	ZXIC_UINT32 ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_stat;
+	ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_underflow_stat;
+	ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_stat;
+	ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_stat;
+} DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_L_T;
+
+typedef struct dpp_ppu_cluster_int_1200m_cluster_mex_fifo_stat_h_t {
+	ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_overflow_stat;
+	ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_overflow_stat;
+	ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_overflow_stat;
+	ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_stat;
+	ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_stat;
+	ZXIC_UINT32 ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_stat;
+	ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_stat;
+	ZXIC_UINT32 ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_stat;
+	ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_stat;
+	ZXIC_UINT32 ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_stat;
+	ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_stat;
+	ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_overflow_stat;
+	ZXIC_UINT32 ese_rsp_ram_free_ptr_u0_underflow_stat;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_stat;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_stat;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_stat;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_stat;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_stat;
+	ZXIC_UINT32 ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_stat;
+} DPP_PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_H_T;
+
+typedef struct dpp_ppu_cluster_ppu_statics_wb_exception_cfg_t {
+	ZXIC_UINT32 csr_statics_wb_exception_code5;
+	ZXIC_UINT32 csr_statics_wb_exception_code4;
+	ZXIC_UINT32 csr_statics_wb_exception_code3;
+	ZXIC_UINT32 csr_statics_wb_exception_code2;
+	ZXIC_UINT32 csr_statics_wb_exception_code1;
+	ZXIC_UINT32 csr_statics_wb_exception_code0;
+} DPP_PPU_CLUSTER_PPU_STATICS_WB_EXCEPTION_CFG_T;
+
+typedef struct dpp_ppu_cluster_thread_switch_en_t {
+	ZXIC_UINT32 thread_switch_en;
+} DPP_PPU_CLUSTER_THREAD_SWITCH_EN_T;
+
+typedef struct dpp_ppu_cluster_is_me_not_idle_t {
+	ZXIC_UINT32 me7_is_not_idle;
+	ZXIC_UINT32 me6_is_not_idle;
+	ZXIC_UINT32 me5_is_not_idle;
+	ZXIC_UINT32 me4_is_not_idle;
+	ZXIC_UINT32 me3_is_not_idle;
+	ZXIC_UINT32 me2_is_not_idle;
+	ZXIC_UINT32 me1_is_not_idle;
+	ZXIC_UINT32 me0_is_not_idle;
+} DPP_PPU_CLUSTER_IS_ME_NOT_IDLE_T;
+
+typedef struct dpp_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_cluster_mf_in_afifo_prog_empty_assert_cfg;
+} DPP_PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_cluster_mf_in_afifo_prog_empty_negate_cfg;
+} DPP_PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ese_rsp_afifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ese_rsp_afifo_prog_empty_assert_cfg;
+} DPP_PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ese_rsp_afifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ese_rsp_afifo_prog_empty_negate_cfg;
+} DPP_PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ise_rsp_afifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ise_rsp_afifo_prog_empty_assert_cfg;
+} DPP_PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ise_rsp_afifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ise_rsp_afifo_prog_empty_negate_cfg;
+} DPP_PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg;
+} DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg;
+} DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg;
+} DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg;
+} DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg;
+} DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg;
+} DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg;
+} DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg;
+} DPP_PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_sta_rsp_afifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 sta_rsp_afifo_prog_empty_assert_cfg;
+} DPP_PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_sta_rsp_afifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 sta_rsp_afifo_prog_empty_negate_cfg;
+} DPP_PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg;
+} DPP_PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg;
+} DPP_PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg;
+} DPP_PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg;
+} DPP_PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_cop_rsp_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 cop_rsp_fifo_prog_full_assert_cfg;
+} DPP_PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_cop_rsp_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 cop_rsp_fifo_prog_full_negate_cfg;
+} DPP_PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_cop_rsp_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 cop_rsp_fifo_prog_empty_assert_cfg;
+} DPP_PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_cop_rsp_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 cop_rsp_fifo_prog_empty_negate_cfg;
+} DPP_PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_mcode_pf_rsp_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 mcode_pf_rsp_fifo_prog_full_assert_cfg;
+} DPP_PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_mcode_pf_rsp_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 mcode_pf_rsp_fifo_prog_full_negate_cfg;
+} DPP_PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 mcode_pf_rsp_fifo_prog_empty_assert_cfg;
+} DPP_PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 mcode_pf_rsp_fifo_prog_empty_negate_cfg;
+} DPP_PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg;
+} DPP_PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg;
+} DPP_PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg;
+} DPP_PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg;
+} DPP_PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_ise_key_afifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_ise_key_afifo_prog_full_assert_cfg;
+} DPP_PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_ise_key_afifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_ise_key_afifo_prog_full_negate_cfg;
+} DPP_PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_ese_key_afifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_ese_key_afifo_prog_full_assert_cfg;
+} DPP_PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_ese_key_afifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_ese_key_afifo_prog_full_negate_cfg;
+} DPP_PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_sta_key_afifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_sta_key_afifo_prog_full_assert_cfg;
+} DPP_PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_sta_key_afifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_sta_key_afifo_prog_full_negate_cfg;
+} DPP_PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_int_600m_cluster_mex_fifo_mask_t {
+	ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_underflow_mask;
+	ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_mask;
+	ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_mask;
+	ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_overflow_mask;
+} DPP_PPU_CLUSTER_INT_600M_CLUSTER_MEX_FIFO_MASK_T;
+
+typedef struct dpp_ppu_cluster_cluster_mex_fifo_600m_interrupt_flag_t {
+	ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_underflow_flag;
+	ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_flag;
+	ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_flag;
+	ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_overflow_flag;
+} DPP_PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_FLAG_T;
+
+typedef struct dpp_ppu_cluster_cluster_mex_fifo_600m_interrupt_sta_t {
+	ZXIC_UINT32 ppu_se_key_afifo_32x54_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_se_key_afifo_32x665_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_sta_key_afifo_32x110_wrapper_underflow_sta;
+	ZXIC_UINT32 ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_sta;
+	ZXIC_UINT32 ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_sta;
+	ZXIC_UINT32 ppu_sta_rsp_afifo_64x79_wrapper_overflow_sta;
+} DPP_PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_STA_T;
+
+typedef struct dpp_ppu_cluster_mex_cnt_cfg_t {
+	ZXIC_UINT32 csr_count_overflow_mode;
+	ZXIC_UINT32 csr_count_rd_mode;
+} DPP_PPU_CLUSTER_MEX_CNT_CFG_T;
+
+typedef struct dpp_ppu_cluster_int_600m_cluster_mex_ram_ecc_error_interrupt_mask_t {
+	ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_double_err_mask;
+	ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_double_err_mask;
+	ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_double_err_mask;
+	ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_single_err_flag;
+	ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_single_err_mask;
+	ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_single_err_mask;
+} DPP_PPU_CLUSTER_INT_600M_CLUSTER_MEX_RAM_ECC_ERROR_INTERRUPT_MASK_T;
+
+typedef struct dpp_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_flag_t {
+	ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_double_err_flag;
+	ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_double_err_flag;
+	ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_double_err_flag;
+	ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_single_err_flag;
+	ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_single_err_flag;
+	ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_single_err_flag;
+} DPP_PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_FLAG_T;
+
+typedef struct dpp_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_sta_t {
+	ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_double_err_stat;
+	ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_double_err_stat;
+	ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_double_err_stat;
+	ZXIC_UINT32 ppu_sta_key_ram_1r1w_32x110_ecc_single_err_stat;
+	ZXIC_UINT32 ppu_se_key_afifo_32x665_ecc_single_err_stat;
+	ZXIC_UINT32 ppu_se_key_afifo_32x54_ecc_single_err_stat;
+} DPP_PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_STA_T;
+
+typedef struct dpp_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ppu_cluster_mf_in_afifo_prog_full_assert_cfg;
+} DPP_PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ppu_cluster_mf_in_afifo_prog_full_negate_cfg;
+} DPP_PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ese_rsp_afifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ese_rsp_afifo_prog_full_assert_cfg;
+} DPP_PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ese_rsp_afifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ese_rsp_afifo_prog_full_negate_cfg;
+} DPP_PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ise_rsp_afifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 ise_rsp_afifo_prog_full_assert_cfg;
+} DPP_PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ise_rsp_afifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 ise_rsp_afifo_prog_full_negate_cfg;
+} DPP_PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_sta_rsp_afifo_prog_full_assert_cfg_t {
+	ZXIC_UINT32 sta_rsp_afifo_prog_full_assert_cfg;
+} DPP_PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_sta_rsp_afifo_prog_full_negate_cfg_t {
+	ZXIC_UINT32 sta_rsp_afifo_prog_full_negate_cfg;
+} DPP_PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_ise_key_afifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_ise_key_afifo_prog_empty_assert_cfg;
+} DPP_PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_ise_key_afifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_ise_key_afifo_prog_empty_negate_cfg;
+} DPP_PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_ese_key_afifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_ese_key_afifo_prog_empty_assert_cfg;
+} DPP_PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_ese_key_afifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_ese_key_afifo_prog_empty_negate_cfg;
+} DPP_PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_sta_key_afifo_prog_empty_assert_cfg_t {
+	ZXIC_UINT32 ppu_sta_key_afifo_prog_empty_assert_cfg;
+} DPP_PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_ASSERT_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_sta_key_afifo_prog_empty_negate_cfg_t {
+	ZXIC_UINT32 ppu_sta_key_afifo_prog_empty_negate_cfg;
+} DPP_PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_NEGATE_CFG_T;
+
+typedef struct dpp_ppu_cluster_ppu_cluster_mf_vld_cnt_h_t {
+	ZXIC_UINT32 ppu_cluster_mf_vld_cnt_h;
+} DPP_PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_ppu_cluster_mf_vld_cnt_l_t {
+	ZXIC_UINT32 ppu_cluster_mf_vld_cnt_l;
+} DPP_PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_cluster_ise_key_out_vld_cnt_t {
+	ZXIC_UINT32 cluster_ise_key_out_vld_cnt;
+} DPP_PPU_CLUSTER_CLUSTER_ISE_KEY_OUT_VLD_CNT_T;
+
+typedef struct dpp_ppu_cluster_ise_cluster_rsp_in_vld_cnt_t {
+	ZXIC_UINT32 ise_cluster_rsp_in_vld_cnt;
+} DPP_PPU_CLUSTER_ISE_CLUSTER_RSP_IN_VLD_CNT_T;
+
+typedef struct dpp_ppu_cluster_cluster_ese_key_out_vld_cnt_t {
+	ZXIC_UINT32 cluster_ese_key_out_vld_cnt;
+} DPP_PPU_CLUSTER_CLUSTER_ESE_KEY_OUT_VLD_CNT_T;
+
+typedef struct dpp_ppu_cluster_ese_cluster_rsp_in_vld_cnt_t {
+	ZXIC_UINT32 ese_cluster_rsp_in_vld_cnt;
+} DPP_PPU_CLUSTER_ESE_CLUSTER_RSP_IN_VLD_CNT_T;
+
+typedef struct dpp_ppu_cluster_cluster_stat_cmd_vld_cnt_t {
+	ZXIC_UINT32 cluster_stat_cmd_vld_cnt;
+} DPP_PPU_CLUSTER_CLUSTER_STAT_CMD_VLD_CNT_T;
+
+typedef struct dpp_ppu_cluster_stat_cluster_rsp_vld_cnt_t {
+	ZXIC_UINT32 stat_cluster_rsp_vld_cnt;
+} DPP_PPU_CLUSTER_STAT_CLUSTER_RSP_VLD_CNT_T;
+
+typedef struct dpp_ppu_cluster_mex_debug_key_vld_cnt_t {
+	ZXIC_UINT32 mex_debug_key_vld_cnt;
+} DPP_PPU_CLUSTER_MEX_DEBUG_KEY_VLD_CNT_T;
+
+typedef struct dpp_ppu_cluster_ise_cluster_key_fc_cnt_t {
+	ZXIC_UINT32 ise_cluster_key_fc_cnt;
+} DPP_PPU_CLUSTER_ISE_CLUSTER_KEY_FC_CNT_T;
+
+typedef struct dpp_ppu_cluster_ese_cluster_key_fc_cnt_t {
+	ZXIC_UINT32 ese_cluster_key_fc_cnt;
+} DPP_PPU_CLUSTER_ESE_CLUSTER_KEY_FC_CNT_T;
+
+typedef struct dpp_ppu_cluster_cluster_ise_rsp_fc_cnt_t {
+	ZXIC_UINT32 cluster_ise_rsp_fc_cnt;
+} DPP_PPU_CLUSTER_CLUSTER_ISE_RSP_FC_CNT_T;
+
+typedef struct dpp_ppu_cluster_cluster_ese_rsp_fc_cnt_t {
+	ZXIC_UINT32 cluster_ese_rsp_fc_cnt;
+} DPP_PPU_CLUSTER_CLUSTER_ESE_RSP_FC_CNT_T;
+
+typedef struct dpp_ppu_cluster_stat_cluster_cmd_fc_cnt_t {
+	ZXIC_UINT32 stat_cluster_cmd_fc_cnt;
+} DPP_PPU_CLUSTER_STAT_CLUSTER_CMD_FC_CNT_T;
+
+typedef struct dpp_ppu_cluster_cluster_stat_rsp_fc_cnt_t {
+	ZXIC_UINT32 cluster_stat_rsp_fc_cnt;
+} DPP_PPU_CLUSTER_CLUSTER_STAT_RSP_FC_CNT_T;
+
+typedef struct dpp_ppu_cluster_cluster_ppu_mf_vld_cnt_l_t {
+	ZXIC_UINT32 cluster_ppu_mf_vld_cnt_l;
+} DPP_PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_cluster_ppu_mf_vld_cnt_h_t {
+	ZXIC_UINT32 cluster_ppu_mf_vld_cnt_h;
+} DPP_PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_cluster_cop_key_vld_cnt_l_t {
+	ZXIC_UINT32 cluster_cop_key_vld_cnt_l;
+} DPP_PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_cluster_cop_key_vld_cnt_h_t {
+	ZXIC_UINT32 cluster_cop_key_vld_cnt_h;
+} DPP_PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_cop_cluster_rsp_vld_cnt_l_t {
+	ZXIC_UINT32 cop_cluster_rsp_vld_cnt_l;
+} DPP_PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_cop_cluster_rsp_vld_cnt_h_t {
+	ZXIC_UINT32 cop_cluster_rsp_vld_cnt_h;
+} DPP_PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_mex_me_pkt_in_sop_cnt_l_t {
+	ZXIC_UINT32 mex_me_pkt_in_sop_cnt_l;
+} DPP_PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_mex_me_pkt_in_sop_cnt_h_t {
+	ZXIC_UINT32 mex_me_pkt_in_sop_cnt_h;
+} DPP_PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_mex_me_pkt_in_eop_cnt_l_t {
+	ZXIC_UINT32 mex_me_pkt_in_eop_cnt_l;
+} DPP_PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_mex_me_pkt_in_eop_cnt_h_t {
+	ZXIC_UINT32 mex_me_pkt_in_eop_cnt_h;
+} DPP_PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_mex_me_pkt_in_vld_cnt_l_t {
+	ZXIC_UINT32 mex_me_pkt_in_vld_cnt_l;
+} DPP_PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_mex_me_pkt_in_vld_cnt_h_t {
+	ZXIC_UINT32 mex_me_pkt_in_vld_cnt_h;
+} DPP_PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_mex_pkt_out_sop_cnt_l_t {
+	ZXIC_UINT32 me_mex_pkt_out_sop_cnt_l;
+} DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_mex_pkt_out_sop_cnt_h_t {
+	ZXIC_UINT32 me_mex_pkt_out_sop_cnt_h;
+} DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_mex_pkt_out_eop_cnt_l_t {
+	ZXIC_UINT32 me_mex_pkt_out_eop_cnt_l;
+} DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_mex_pkt_out_eop_cnt_h_t {
+	ZXIC_UINT32 me_mex_pkt_out_eop_cnt_h;
+} DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_mex_pkt_out_vld_cnt_l_t {
+	ZXIC_UINT32 me_mex_pkt_out_vld_cnt_l;
+} DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_mex_pkt_out_vld_cnt_h_t {
+	ZXIC_UINT32 me_mex_pkt_out_vld_cnt_h;
+} DPP_PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_mex_i_key_out_sop_cnt_l_t {
+	ZXIC_UINT32 me_mex_i_key_out_sop_cnt_l;
+} DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_mex_i_key_out_sop_cnt_h_t {
+	ZXIC_UINT32 me_mex_i_key_out_sop_cnt_h;
+} DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_mex_i_key_out_eop_cnt_l_t {
+	ZXIC_UINT32 me_mex_i_key_out_eop_cnt_l;
+} DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_mex_i_key_out_eop_cnt_h_t {
+	ZXIC_UINT32 me_mex_i_key_out_eop_cnt_h;
+} DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_mex_i_key_out_vld_cnt_l_t {
+	ZXIC_UINT32 me_mex_i_key_out_vld_cnt_l;
+} DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_mex_i_key_out_vld_cnt_h_t {
+	ZXIC_UINT32 me_mex_i_key_out_vld_cnt_h;
+} DPP_PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_mex_e_key_out_sop_cnt_l_t {
+	ZXIC_UINT32 me_mex_e_key_out_sop_cnt_l;
+} DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_mex_e_key_out_sop_cnt_h_t {
+	ZXIC_UINT32 me_mex_e_key_out_sop_cnt_h;
+} DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_mex_e_key_out_eop_cnt_l_t {
+	ZXIC_UINT32 me_mex_e_key_out_eop_cnt_l;
+} DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_mex_e_key_out_eop_cnt_h_t {
+	ZXIC_UINT32 me_mex_e_key_out_eop_cnt_h;
+} DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_mex_e_key_out_vld_cnt_l_t {
+	ZXIC_UINT32 me_mex_e_key_out_vld_cnt_l;
+} DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_mex_e_key_out_vld_cnt_h_t {
+	ZXIC_UINT32 me_mex_e_key_out_vld_cnt_h;
+} DPP_PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_mex_demux_ise_key_vld_cnt_l_t {
+	ZXIC_UINT32 me_mex_demux_ise_key_vld_cnt_l;
+} DPP_PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_mex_demux_ise_key_vld_cnt_h_t {
+	ZXIC_UINT32 me_mex_demux_ise_key_vld_cnt_h;
+} DPP_PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_mex_demux_ese_key_vld_cnt_l_t {
+	ZXIC_UINT32 me_mex_demux_ese_key_vld_cnt_l;
+} DPP_PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_mex_demux_ese_key_vld_cnt_h_t {
+	ZXIC_UINT32 me_mex_demux_ese_key_vld_cnt_h;
+} DPP_PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_mex_demux_sta_key_vld_cnt_l_t {
+	ZXIC_UINT32 me_mex_demux_sta_key_vld_cnt_l;
+} DPP_PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_mex_demux_sta_key_vld_cnt_h_t {
+	ZXIC_UINT32 me_mex_demux_sta_key_vld_cnt_h;
+} DPP_PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_mex_demux_cop_key_vld_cnt_l_t {
+	ZXIC_UINT32 me_mex_demux_cop_key_vld_cnt_l;
+} DPP_PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_mex_demux_cop_key_vld_cnt_h_t {
+	ZXIC_UINT32 me_mex_demux_cop_key_vld_cnt_h;
+} DPP_PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_l_t {
+	ZXIC_UINT32 mex_me_demux_ise_rsp_vld_cnt_l;
+} DPP_PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_h_t {
+	ZXIC_UINT32 mex_me_demux_ise_rsp_vld_cnt_h;
+} DPP_PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_l_t {
+	ZXIC_UINT32 mex_me_demux_ese_rsp_vld_cnt_l;
+} DPP_PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_h_t {
+	ZXIC_UINT32 mex_me_demux_ese_rsp_vld_cnt_h;
+} DPP_PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_l_t {
+	ZXIC_UINT32 mex_me_demux_sta_rsp_vld_cnt_l;
+} DPP_PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_h_t {
+	ZXIC_UINT32 mex_me_demux_sta_rsp_vld_cnt_h;
+} DPP_PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_l_t {
+	ZXIC_UINT32 mex_me_demux_cop_rsp_vld_cnt_l;
+} DPP_PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_h_t {
+	ZXIC_UINT32 mex_me_demux_cop_rsp_vld_cnt_h;
+} DPP_PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_exception_code0_cnt_l_t {
+	ZXIC_UINT32 me_exception_code0_cnt_l;
+} DPP_PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_exception_code0_cnt_h_t {
+	ZXIC_UINT32 me_exception_code0_cnt_h;
+} DPP_PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_exception_code1_cnt_l_t {
+	ZXIC_UINT32 me_exception_code1_cnt_l;
+} DPP_PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_exception_code1_cnt_h_t {
+	ZXIC_UINT32 me_exception_code1_cnt_h;
+} DPP_PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_exception_code2_cnt_l_t {
+	ZXIC_UINT32 me_exception_code2_cnt_l;
+} DPP_PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_exception_code2_cnt_h_t {
+	ZXIC_UINT32 me_exception_code2_cnt_h;
+} DPP_PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_exception_code3_cnt_l_t {
+	ZXIC_UINT32 me_exception_code3_cnt_l;
+} DPP_PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_exception_code3_cnt_h_t {
+	ZXIC_UINT32 me_exception_code3_cnt_h;
+} DPP_PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_exception_code4_cnt_l_t {
+	ZXIC_UINT32 me_exception_code4_cnt_l;
+} DPP_PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_exception_code4_cnt_h_t {
+	ZXIC_UINT32 me_exception_code4_cnt_h;
+} DPP_PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_H_T;
+
+typedef struct dpp_ppu_cluster_me_exception_code5_cnt_l_t {
+	ZXIC_UINT32 me_exception_code5_cnt_l;
+} DPP_PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_L_T;
+
+typedef struct dpp_ppu_cluster_me_exception_code5_cnt_h_t {
+	ZXIC_UINT32 me_exception_code5_cnt_h;
+} DPP_PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_H_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ptptm_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ptptm_reg.h
index db871f40365bee6ae24d5c8071484dbe3883f6aa..0c6e037243f7bf6b1df7487717a5422943fe6563 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ptptm_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_ptptm_reg.h
@@ -3,893 +3,727 @@
 #define _DPP_PTPTM_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_ptptm_ptp_top_pp1s_interrupt_t
-{
-    ZXIC_UINT32 int_state;
-    ZXIC_UINT32 int_test;
-    ZXIC_UINT32 int_clr;
-    ZXIC_UINT32 int_en;
-}DPP_PTPTM_PTP_TOP_PP1S_INTERRUPT_T;
-
-typedef struct dpp_ptptm_ptp_top_pp1s_external_select_t
-{
-    ZXIC_UINT32 pp1s_external_select;
-}DPP_PTPTM_PTP_TOP_PP1S_EXTERNAL_SELECT_T;
-
-typedef struct dpp_ptptm_ptp_top_pp1s_out_select_t
-{
-    ZXIC_UINT32 pp1s_out_sel;
-}DPP_PTPTM_PTP_TOP_PP1S_OUT_SELECT_T;
-
-typedef struct dpp_ptptm_ptp_top_test_pp1s_select_t
-{
-    ZXIC_UINT32 test_pp1s_sel;
-}DPP_PTPTM_PTP_TOP_TEST_PP1S_SELECT_T;
-
-typedef struct dpp_ptptm_ptp_top_local_pp1s_en_t
-{
-    ZXIC_UINT32 local_pp1s_en;
-}DPP_PTPTM_PTP_TOP_LOCAL_PP1S_EN_T;
-
-typedef struct dpp_ptptm_ptp_top_local_pp1s_adjust_t
-{
-    ZXIC_UINT32 local_pp1s_adjust_sel;
-    ZXIC_UINT32 local_pp1s_adjust_en;
-}DPP_PTPTM_PTP_TOP_LOCAL_PP1S_ADJUST_T;
-
-typedef struct dpp_ptptm_ptp_top_local_pp1s_adjust_value_t
-{
-    ZXIC_UINT32 local_pp1s_adjust_value;
-}DPP_PTPTM_PTP_TOP_LOCAL_PP1S_ADJUST_VALUE_T;
-
-typedef struct dpp_ptptm_ptp_top_pp1s_to_np_select_t
-{
-    ZXIC_UINT32 pp1s_to_np_sel;
-}DPP_PTPTM_PTP_TOP_PP1S_TO_NP_SELECT_T;
-
-typedef struct dpp_ptptm_ptp_top_pd_u1_sel_t
-{
-    ZXIC_UINT32 pd_u1_sel1;
-    ZXIC_UINT32 pd_u1_sel0;
-}DPP_PTPTM_PTP_TOP_PD_U1_SEL_T;
-
-typedef struct dpp_ptptm_ptp_top_pd_u1_pd0_shift_t
-{
-    ZXIC_UINT32 pd_u1_pd0_shift;
-}DPP_PTPTM_PTP_TOP_PD_U1_PD0_SHIFT_T;
-
-typedef struct dpp_ptptm_ptp_top_pd_u1_pd1_shift_t
-{
-    ZXIC_UINT32 pd_u1_pd1_shift;
-}DPP_PTPTM_PTP_TOP_PD_U1_PD1_SHIFT_T;
-
-typedef struct dpp_ptptm_ptp_top_pd_u1_result_t
-{
-    ZXIC_UINT32 pd_u1_result_sign;
-    ZXIC_UINT32 pd_u1_overflow;
-    ZXIC_UINT32 pd_u1_result;
-}DPP_PTPTM_PTP_TOP_PD_U1_RESULT_T;
-
-typedef struct dpp_ptptm_ptp_top_pd_u2_sel_t
-{
-    ZXIC_UINT32 pd_u2_sel1;
-    ZXIC_UINT32 pd_u2_sel0;
-}DPP_PTPTM_PTP_TOP_PD_U2_SEL_T;
-
-typedef struct dpp_ptptm_ptp_top_pd_u2_pd0_shift_t
-{
-    ZXIC_UINT32 pd_u2_pd0_shift;
-}DPP_PTPTM_PTP_TOP_PD_U2_PD0_SHIFT_T;
-
-typedef struct dpp_ptptm_ptp_top_pd_u2_pd1_shift_t
-{
-    ZXIC_UINT32 pd_u2_pd1_shift;
-}DPP_PTPTM_PTP_TOP_PD_U2_PD1_SHIFT_T;
-
-typedef struct dpp_ptptm_ptp_top_pd_u2_result_t
-{
-    ZXIC_UINT32 pd_u2_result_sign;
-    ZXIC_UINT32 pd_u2_overflow;
-    ZXIC_UINT32 pd_u2_result;
-}DPP_PTPTM_PTP_TOP_PD_U2_RESULT_T;
-
-typedef struct dpp_ptptm_ptp_top_tsn_group_nanosecond_delay0_t
-{
-    ZXIC_UINT32 tsn_group_nanosecond_delay0;
-}DPP_PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY0_T;
-
-typedef struct dpp_ptptm_ptp_top_tsn_group_fracnanosecond_delay0_t
-{
-    ZXIC_UINT32 tsn_group_fracnanosecond_delay0;
-}DPP_PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY0_T;
-
-typedef struct dpp_ptptm_ptp_top_tsn_group_nanosecond_delay1_t
-{
-    ZXIC_UINT32 tsn_group_nanosecond_delay1;
-}DPP_PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY1_T;
-
-typedef struct dpp_ptptm_ptp_top_tsn_group_fracnanosecond_delay1_t
-{
-    ZXIC_UINT32 tsn_group_fracnanosecond_delay1;
-}DPP_PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY1_T;
-
-typedef struct dpp_ptptm_ptp_top_tsn_group_nanosecond_delay2_t
-{
-    ZXIC_UINT32 tsn_group_nanosecond_delay2;
-}DPP_PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY2_T;
-
-typedef struct dpp_ptptm_ptp_top_tsn_group_fracnanosecond_delay2_t
-{
-    ZXIC_UINT32 tsn_group_fracnanosecond_delay2;
-}DPP_PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY2_T;
-
-typedef struct dpp_ptptm_ptp_top_tsn_group_nanosecond_delay3_t
-{
-    ZXIC_UINT32 tsn_group_nanosecond_delay3;
-}DPP_PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY3_T;
-
-typedef struct dpp_ptptm_ptp_top_tsn_group_fracnanosecond_delay3_t
-{
-    ZXIC_UINT32 tsn_group_fracnanosecond_delay3;
-}DPP_PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY3_T;
-
-typedef struct dpp_ptptm_ptp_top_tsn_ptp1588_rdma_nanosecond_delay_t
-{
-    ZXIC_UINT32 ptp1588_rdma_nanosecond_delay;
-}DPP_PTPTM_PTP_TOP_TSN_PTP1588_RDMA_NANOSECOND_DELAY_T;
-
-typedef struct dpp_ptptm_ptp_top_ptp1588_rdma_fracnanosecond_delay_t
-{
-    ZXIC_UINT32 ptp1588_rdma_fracnanosecond_delay;
-}DPP_PTPTM_PTP_TOP_PTP1588_RDMA_FRACNANOSECOND_DELAY_T;
-
-typedef struct dpp_ptptm_ptp_top_ptp1588_np_nanosecond_delay_t
-{
-    ZXIC_UINT32 ptp1588_np_nanosecond_delay;
-}DPP_PTPTM_PTP_TOP_PTP1588_NP_NANOSECOND_DELAY_T;
-
-typedef struct dpp_ptptm_ptp_top_ptp1588_np_fracnanosecond_delay_t
-{
-    ZXIC_UINT32 ptp1588_np_fracnanosecond_delay;
-}DPP_PTPTM_PTP_TOP_PTP1588_NP_FRACNANOSECOND_DELAY_T;
-
-typedef struct dpp_ptptm_ptp_top_time_sync_period_t
-{
-    ZXIC_UINT32 time_sync_period;
-}DPP_PTPTM_PTP_TOP_TIME_SYNC_PERIOD_T;
-
-typedef struct dpp_ptptm_ptptm_module_id_t
-{
-    ZXIC_UINT32 module_id;
-}DPP_PTPTM_PTPTM_MODULE_ID_T;
-
-typedef struct dpp_ptptm_ptptm_module_version_t
-{
-    ZXIC_UINT32 module_major_version;
-    ZXIC_UINT32 module_minor_version;
-}DPP_PTPTM_PTPTM_MODULE_VERSION_T;
-
-typedef struct dpp_ptptm_ptptm_module_date_t
-{
-    ZXIC_UINT32 year;
-    ZXIC_UINT32 month;
-    ZXIC_UINT32 date;
-}DPP_PTPTM_PTPTM_MODULE_DATE_T;
-
-typedef struct dpp_ptptm_ptptm_interrupt_status_t
-{
-    ZXIC_UINT32 pps_in_status;
-    ZXIC_UINT32 fifo_almost_full_status;
-    ZXIC_UINT32 fifo_no_empty_status;
-    ZXIC_UINT32 trigger_output_status;
-    ZXIC_UINT32 trigger_input_status;
-}DPP_PTPTM_PTPTM_INTERRUPT_STATUS_T;
-
-typedef struct dpp_ptptm_ptptm_interrupt_event_t
-{
-    ZXIC_UINT32 pps_in_event;
-    ZXIC_UINT32 fifo_almost_full_event;
-    ZXIC_UINT32 fifo_no_empty_event;
-    ZXIC_UINT32 trigger_output_event;
-    ZXIC_UINT32 trigger_input_event;
-}DPP_PTPTM_PTPTM_INTERRUPT_EVENT_T;
-
-typedef struct dpp_ptptm_ptptm_interrupt_mask_t
-{
-    ZXIC_UINT32 pps_in_event_mask;
-    ZXIC_UINT32 fifo_almost_full_event_mask;
-    ZXIC_UINT32 fifo_no_empty_event_mask;
-    ZXIC_UINT32 trigger_output_event_mask;
-    ZXIC_UINT32 trigger_input_eventt_mask;
-}DPP_PTPTM_PTPTM_INTERRUPT_MASK_T;
-
-typedef struct dpp_ptptm_ptptm_interrupt_test_t
-{
-    ZXIC_UINT32 trigger_pps_in_event_test;
-    ZXIC_UINT32 trigger_fifo_almost_full_event_test;
-    ZXIC_UINT32 trigger_fifo_no_empty_event_test;
-    ZXIC_UINT32 trigger_output_event_test;
-    ZXIC_UINT32 trigger_input_event_test;
-}DPP_PTPTM_PTPTM_INTERRUPT_TEST_T;
-
-typedef struct dpp_ptptm_ptptm_hw_clock_cycle_integer_t
-{
-    ZXIC_UINT32 integeral_nanosecond_of_hw_clock_cycle;
-}DPP_PTPTM_PTPTM_HW_CLOCK_CYCLE_INTEGER_T;
-
-typedef struct dpp_ptptm_ptptm_hw_clock_cycle_fraction_t
-{
-    ZXIC_UINT32 fractional_nanosecond_of_hw_clock_cycle;
-}DPP_PTPTM_PTPTM_HW_CLOCK_CYCLE_FRACTION_T;
-
-typedef struct dpp_ptptm_ptptm_ptp_clock_cycle_integer_t
-{
-    ZXIC_UINT32 integeral_nanosecond_of_ptp_clock_cycle;
-}DPP_PTPTM_PTPTM_PTP_CLOCK_CYCLE_INTEGER_T;
-
-typedef struct dpp_ptptm_ptptm_ptp_clock_cycle_fraction_t
-{
-    ZXIC_UINT32 fractional_nanosecond_of_ptp_clock_cycle;
-}DPP_PTPTM_PTPTM_PTP_CLOCK_CYCLE_FRACTION_T;
-
-typedef struct dpp_ptptm_ptptm_ptp_configuration_t
-{
-    ZXIC_UINT32 trig_oe;
-    ZXIC_UINT32 hw_time_update_en;
-    ZXIC_UINT32 ptp1588_tod_time_update_en;
-    ZXIC_UINT32 timer_enable;
-    ZXIC_UINT32 pps_output_enable;
-    ZXIC_UINT32 pp1_output_enable;
-    ZXIC_UINT32 pp2_output_enable;
-    ZXIC_UINT32 enable_writing_timestamps_to_the_fifo;
-    ZXIC_UINT32 l2s_time_output_select;
-    ZXIC_UINT32 reserved_9;
-    ZXIC_UINT32 pps_input_select;
-    ZXIC_UINT32 pp_output_select;
-    ZXIC_UINT32 reserved_6;
-    ZXIC_UINT32 timer_run_mode;
-    ZXIC_UINT32 update_command_select;
-    ZXIC_UINT32 trigger_out_enable;
-    ZXIC_UINT32 trigger_in_enable;
-    ZXIC_UINT32 timer_capture_slave_mode;
-}DPP_PTPTM_PTPTM_PTP_CONFIGURATION_T;
-
-typedef struct dpp_ptptm_ptptm_timer_control_t
-{
-    ZXIC_UINT32 ptpmoutputsynchroningstate;
-    ZXIC_UINT32 ptp1588_fifo_read_command;
-    ZXIC_UINT32 adjust_the_timer;
-}DPP_PTPTM_PTPTM_TIMER_CONTROL_T;
-
-typedef struct dpp_ptptm_ptptm_pps_income_delay_t
-{
-    ZXIC_UINT32 pps_income_delay_nanosecond;
-    ZXIC_UINT32 pps_income_delay_frac_nanosecond;
-}DPP_PTPTM_PTPTM_PPS_INCOME_DELAY_T;
-
-typedef struct dpp_ptptm_ptptm_clock_cycle_update_t
-{
-    ZXIC_UINT32 tsn3_clock_cycle_update_enable;
-    ZXIC_UINT32 tsn2_clock_cycle_update_enable;
-    ZXIC_UINT32 tsn1_clock_cycle_update_enable;
-    ZXIC_UINT32 tsn0_clock_cycle_update_enable;
-    ZXIC_UINT32 ptp1588_clock_cycle_update_enable;
-}DPP_PTPTM_PTPTM_CLOCK_CYCLE_UPDATE_T;
-
-typedef struct dpp_ptptm_ptptm_cycle_time_of_output_period_pulse_1_t
-{
-    ZXIC_UINT32 clock_number_of_output_period_pulse_1;
-}DPP_PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_1_T;
-
-typedef struct dpp_ptptm_ptptm_cycle_time_of_output_period_pulse_2_t
-{
-    ZXIC_UINT32 clock_number_of_output_period_pulse_2;
-}DPP_PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_2_T;
-
-typedef struct dpp_ptptm_ptptm_timer_latch_en_t
-{
-    ZXIC_UINT32 latch_the_timer_en;
-}DPP_PTPTM_PTPTM_TIMER_LATCH_EN_T;
-
-typedef struct dpp_ptptm_ptptm_timer_latch_sel_t
-{
-    ZXIC_UINT32 timer_latch_sel;
-}DPP_PTPTM_PTPTM_TIMER_LATCH_SEL_T;
-
-typedef struct dpp_ptptm_ptptm_trigger_in_tod_nanosecond_t
-{
-    ZXIC_UINT32 trigger_in_tod_nanosecond;
-}DPP_PTPTM_PTPTM_TRIGGER_IN_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_trigger_in_lower_tod_second_t
-{
-    ZXIC_UINT32 trigger_in_lower_tod_second;
-}DPP_PTPTM_PTPTM_TRIGGER_IN_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_trigger_in_high_tod_second_t
-{
-    ZXIC_UINT32 trigger_in_high_tod_second;
-}DPP_PTPTM_PTPTM_TRIGGER_IN_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_trigger_in_fracnanosecond_t
-{
-    ZXIC_UINT32 trigger_in_fracnanosecond;
-}DPP_PTPTM_PTPTM_TRIGGER_IN_FRACNANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_trigger_in_hardware_time_low_t
-{
-    ZXIC_UINT32 trigger_in_hardware_time_low;
-}DPP_PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_LOW_T;
-
-typedef struct dpp_ptptm_ptptm_trigger_in_hardware_time_high_t
-{
-    ZXIC_UINT32 trigger_in_hardware_time_high;
-}DPP_PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_HIGH_T;
-
-typedef struct dpp_ptptm_ptptm_trigger_out_tod_nanosecond_t
-{
-    ZXIC_UINT32 trigger_out_tod_nanosecond;
-}DPP_PTPTM_PTPTM_TRIGGER_OUT_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_trigger_out_lower_tod_second_t
-{
-    ZXIC_UINT32 trigger_out_lower_tod_second;
-}DPP_PTPTM_PTPTM_TRIGGER_OUT_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_trigger_out_high_tod_second_t
-{
-    ZXIC_UINT32 trigger_out_high_tod_second;
-}DPP_PTPTM_PTPTM_TRIGGER_OUT_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_trigger_out_hardware_time_low_t
-{
-    ZXIC_UINT32 trigger_out_hardware_time_low;
-}DPP_PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_LOW_T;
-
-typedef struct dpp_ptptm_ptptm_trigger_out_hardware_time_high_t
-{
-    ZXIC_UINT32 trigger_out_hardware_time_high;
-}DPP_PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_HIGH_T;
-
-typedef struct dpp_ptptm_ptptm_adjust_tod_nanosecond_t
-{
-    ZXIC_UINT32 adjust_tod_nanosecond;
-}DPP_PTPTM_PTPTM_ADJUST_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_adjust_lower_tod_second_t
-{
-    ZXIC_UINT32 adjust_lower_tod_second;
-}DPP_PTPTM_PTPTM_ADJUST_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_adjust_high_tod_second_t
-{
-    ZXIC_UINT32 adjust_high_tod_second;
-}DPP_PTPTM_PTPTM_ADJUST_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_adjust_fracnanosecond_t
-{
-    ZXIC_UINT32 adjust_fracnanosecond;
-}DPP_PTPTM_PTPTM_ADJUST_FRACNANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_adjust_hardware_time_low_t
-{
-    ZXIC_UINT32 adjust_hardware_time_low;
-}DPP_PTPTM_PTPTM_ADJUST_HARDWARE_TIME_LOW_T;
-
-typedef struct dpp_ptptm_ptptm_adjust_hardware_time_high_t
-{
-    ZXIC_UINT32 adjust_hardware_time_high;
-}DPP_PTPTM_PTPTM_ADJUST_HARDWARE_TIME_HIGH_T;
-
-typedef struct dpp_ptptm_ptptm_latch_tod_nanosecond_t
-{
-    ZXIC_UINT32 latch_tod_nanosecond;
-}DPP_PTPTM_PTPTM_LATCH_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_latch_lower_tod_second_t
-{
-    ZXIC_UINT32 latch_lower_tod_second;
-}DPP_PTPTM_PTPTM_LATCH_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_latch_high_tod_second_t
-{
-    ZXIC_UINT32 latch_high_tod_second;
-}DPP_PTPTM_PTPTM_LATCH_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_latch_fracnanosecond_t
-{
-    ZXIC_UINT32 latch_fracnanosecond;
-}DPP_PTPTM_PTPTM_LATCH_FRACNANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_latch_hardware_time_low_t
-{
-    ZXIC_UINT32 latch_hardware_time_low;
-}DPP_PTPTM_PTPTM_LATCH_HARDWARE_TIME_LOW_T;
-
-typedef struct dpp_ptptm_ptptm_latch_hardware_time_high_t
-{
-    ZXIC_UINT32 latch_hardware_time_high;
-}DPP_PTPTM_PTPTM_LATCH_HARDWARE_TIME_HIGH_T;
-
-typedef struct dpp_ptptm_ptptm_real_tod_nanosecond_t
-{
-    ZXIC_UINT32 real_tod_nanosecond;
-}DPP_PTPTM_PTPTM_REAL_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_real_lower_tod_second_t
-{
-    ZXIC_UINT32 real_lower_tod_second;
-}DPP_PTPTM_PTPTM_REAL_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_real_high_tod_second_t
-{
-    ZXIC_UINT32 real_high_tod_second;
-}DPP_PTPTM_PTPTM_REAL_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_real_hardware_time_low_t
-{
-    ZXIC_UINT32 real_hardware_time_low;
-}DPP_PTPTM_PTPTM_REAL_HARDWARE_TIME_LOW_T;
-
-typedef struct dpp_ptptm_ptptm_real_hardware_time_high_t
-{
-    ZXIC_UINT32 real_hardware_time_high;
-}DPP_PTPTM_PTPTM_REAL_HARDWARE_TIME_HIGH_T;
-
-typedef struct dpp_ptptm_ptptm_ptp1588_event_message_port_t
-{
-    ZXIC_UINT32 ptp1588_event_message_port;
-}DPP_PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_PORT_T;
-
-typedef struct dpp_ptptm_ptptm_ptp1588_event_message_timestamp_low_t
-{
-    ZXIC_UINT32 ptp1588_event_message_timestamp_low;
-}DPP_PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_LOW_T;
-
-typedef struct dpp_ptptm_ptptm_ptp1588_event_message_timestamp_high_t
-{
-    ZXIC_UINT32 ptp1588_event_message_timestamp_high;
-}DPP_PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_HIGH_T;
-
-typedef struct dpp_ptptm_ptptm_ptp1588_event_message_fifo_status_t
-{
-    ZXIC_UINT32 fifo_full;
-    ZXIC_UINT32 fifo_empty;
-    ZXIC_UINT32 timestamps_count;
-}DPP_PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_FIFO_STATUS_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tod_nanosecond_t
-{
-    ZXIC_UINT32 latch_1588tod_nanosecond;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_lower_tod_second_t
-{
-    ZXIC_UINT32 latch_lower_1588tod_second;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_high_tod_second_t
-{
-    ZXIC_UINT32 latch_high_1588tod_second;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_fracnanosecond_t
-{
-    ZXIC_UINT32 latch_1588fracnanosecond;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_FRACNANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn_time_configuration_t
-{
-    ZXIC_UINT32 tsn_pps_enable;
-    ZXIC_UINT32 tsn_timer_enable;
-    ZXIC_UINT32 tsn_timer_run_mode;
-    ZXIC_UINT32 timer_capture_slave_mode;
-}DPP_PTPTM_PTPTM_TSN_TIME_CONFIGURATION_T;
-
-typedef struct dpp_ptptm_ptptm_tsn_timer_control_t
-{
-    ZXIC_UINT32 adjust_the_tsn3_timer;
-    ZXIC_UINT32 adjust_the_tsn2_timer;
-    ZXIC_UINT32 adjust_the_tsn1_timer;
-    ZXIC_UINT32 adjust_the_tsn0_timer;
-}DPP_PTPTM_PTPTM_TSN_TIMER_CONTROL_T;
-
-typedef struct dpp_ptptm_ptptm_tsn0_clock_cycle_integer_t
-{
-    ZXIC_UINT32 integeral_nanosecond_of_tsn0_clock_cycle;
-}DPP_PTPTM_PTPTM_TSN0_CLOCK_CYCLE_INTEGER_T;
-
-typedef struct dpp_ptptm_ptptm_tsn0_clock_cycle_fraction_t
-{
-    ZXIC_UINT32 fractional_nanosecond_of_tsn0_clock_cycle;
-}DPP_PTPTM_PTPTM_TSN0_CLOCK_CYCLE_FRACTION_T;
-
-typedef struct dpp_ptptm_ptptm_tsn1_clock_cycle_integer_t
-{
-    ZXIC_UINT32 integeral_nanosecond_of_tsn1_clock_cycle;
-}DPP_PTPTM_PTPTM_TSN1_CLOCK_CYCLE_INTEGER_T;
-
-typedef struct dpp_ptptm_ptptm_tsn1_clock_cycle_fraction_t
-{
-    ZXIC_UINT32 fractional_nanosecond_of_tsn1_clock_cycle;
-}DPP_PTPTM_PTPTM_TSN1_CLOCK_CYCLE_FRACTION_T;
-
-typedef struct dpp_ptptm_ptptm_tsn2_clock_cycle_integer_t
-{
-    ZXIC_UINT32 integeral_nanosecond_of_tsn2_clock_cycle;
-}DPP_PTPTM_PTPTM_TSN2_CLOCK_CYCLE_INTEGER_T;
-
-typedef struct dpp_ptptm_ptptm_tsn2_clock_cycle_fraction_t
-{
-    ZXIC_UINT32 fractional_nanosecond_of_tsn2_clock_cycle;
-}DPP_PTPTM_PTPTM_TSN2_CLOCK_CYCLE_FRACTION_T;
-
-typedef struct dpp_ptptm_ptptm_tsn3_clock_cycle_integer_t
-{
-    ZXIC_UINT32 integeral_nanosecond_of_tsn3_clock_cycle;
-}DPP_PTPTM_PTPTM_TSN3_CLOCK_CYCLE_INTEGER_T;
-
-typedef struct dpp_ptptm_ptptm_tsn3_clock_cycle_fraction_t
-{
-    ZXIC_UINT32 fractional_nanosecond_of_tsn3_clock_cycle;
-}DPP_PTPTM_PTPTM_TSN3_CLOCK_CYCLE_FRACTION_T;
-
-typedef struct dpp_ptptm_ptptm_tsn0_adjust_tod_nanosecond_t
-{
-    ZXIC_UINT32 tsn0_adjust_tod_nanosecond;
-}DPP_PTPTM_PTPTM_TSN0_ADJUST_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn0_adjust_lower_tod_second_t
-{
-    ZXIC_UINT32 tsn0_adjust_lower_tod_second;
-}DPP_PTPTM_PTPTM_TSN0_ADJUST_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn0_adjust_high_tod_second_t
-{
-    ZXIC_UINT32 tsn0_adjust_high_tod_second;
-}DPP_PTPTM_PTPTM_TSN0_ADJUST_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn0_adjust_fracnanosecond_t
-{
-    ZXIC_UINT32 tsn0_adjust_fracnanosecond;
-}DPP_PTPTM_PTPTM_TSN0_ADJUST_FRACNANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn1_adjust_tod_nanosecond_t
-{
-    ZXIC_UINT32 tsn1_adjust_tod_nanosecond;
-}DPP_PTPTM_PTPTM_TSN1_ADJUST_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn1_adjust_lower_tod_second_t
-{
-    ZXIC_UINT32 tsn1_adjust_lower_tod_second;
-}DPP_PTPTM_PTPTM_TSN1_ADJUST_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn1_adjust_high_tod_second_t
-{
-    ZXIC_UINT32 tsn1_adjust_high_tod_second;
-}DPP_PTPTM_PTPTM_TSN1_ADJUST_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn1_adjust_fracnanosecond_t
-{
-    ZXIC_UINT32 tsn1_adjust_fracnanosecond;
-}DPP_PTPTM_PTPTM_TSN1_ADJUST_FRACNANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn2_adjust_tod_nanosecond_t
-{
-    ZXIC_UINT32 tsn2_adjust_tod_nanosecond;
-}DPP_PTPTM_PTPTM_TSN2_ADJUST_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn2_adjust_lower_tod_second_t
-{
-    ZXIC_UINT32 tsn2_adjust_lower_tod_second;
-}DPP_PTPTM_PTPTM_TSN2_ADJUST_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn2_adjust_high_tod_second_t
-{
-    ZXIC_UINT32 tsn2_adjust_high_tod_second;
-}DPP_PTPTM_PTPTM_TSN2_ADJUST_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn2_adjust_fracnanosecond_t
-{
-    ZXIC_UINT32 tsn2_adjust_fracnanosecond;
-}DPP_PTPTM_PTPTM_TSN2_ADJUST_FRACNANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn3_adjust_tod_nanosecond_t
-{
-    ZXIC_UINT32 tsn3_adjust_tod_nanosecond;
-}DPP_PTPTM_PTPTM_TSN3_ADJUST_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn3_adjust_lower_tod_second_t
-{
-    ZXIC_UINT32 tsn3_adjust_lower_tod_second;
-}DPP_PTPTM_PTPTM_TSN3_ADJUST_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn3_adjust_high_tod_second_t
-{
-    ZXIC_UINT32 tsn3_adjust_high_tod_second;
-}DPP_PTPTM_PTPTM_TSN3_ADJUST_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn3_adjust_fracnanosecond_t
-{
-    ZXIC_UINT32 tsn3_adjust_fracnanosecond;
-}DPP_PTPTM_PTPTM_TSN3_ADJUST_FRACNANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn0_latch_tod_nanosecond_t
-{
-    ZXIC_UINT32 tsn0_latch_tod_nanosecond;
-}DPP_PTPTM_PTPTM_TSN0_LATCH_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn0_latch_lower_tod_second_t
-{
-    ZXIC_UINT32 tsn0_latch_lower_tod_second;
-}DPP_PTPTM_PTPTM_TSN0_LATCH_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn0_latch_high_tod_second_t
-{
-    ZXIC_UINT32 tsn0_latch_high_tod_second;
-}DPP_PTPTM_PTPTM_TSN0_LATCH_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn0_latch_fracnanosecond_t
-{
-    ZXIC_UINT32 tsn0_latch_fracnanosecond;
-}DPP_PTPTM_PTPTM_TSN0_LATCH_FRACNANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn1_latch_tod_nanosecond_t
-{
-    ZXIC_UINT32 tsn1_latch_tod_nanosecond;
-}DPP_PTPTM_PTPTM_TSN1_LATCH_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn1_latch_lower_tod_second_t
-{
-    ZXIC_UINT32 tsn1_latch_lower_tod_second;
-}DPP_PTPTM_PTPTM_TSN1_LATCH_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn1_latch_high_tod_second_t
-{
-    ZXIC_UINT32 tsn1_latch_high_tod_second;
-}DPP_PTPTM_PTPTM_TSN1_LATCH_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn1_latch_fracnanosecond_t
-{
-    ZXIC_UINT32 tsn1_latch_fracnanosecond;
-}DPP_PTPTM_PTPTM_TSN1_LATCH_FRACNANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn2_latch_tod_nanosecond_t
-{
-    ZXIC_UINT32 tsn2_latch_tod_nanosecond;
-}DPP_PTPTM_PTPTM_TSN2_LATCH_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn2_latch_lower_tod_second_t
-{
-    ZXIC_UINT32 tsn2_latch_lower_tod_second;
-}DPP_PTPTM_PTPTM_TSN2_LATCH_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn2_latch_high_tod_second_t
-{
-    ZXIC_UINT32 tsn2_latch_high_tod_second;
-}DPP_PTPTM_PTPTM_TSN2_LATCH_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn2_latch_fracnanosecond_t
-{
-    ZXIC_UINT32 tsn2_latch_fracnanosecond;
-}DPP_PTPTM_PTPTM_TSN2_LATCH_FRACNANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn3_latch_tod_nanosecond_t
-{
-    ZXIC_UINT32 tsn3_latch_tod_nanosecond;
-}DPP_PTPTM_PTPTM_TSN3_LATCH_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn3_latch_lower_tod_second_t
-{
-    ZXIC_UINT32 tsn3_latch_lower_tod_second;
-}DPP_PTPTM_PTPTM_TSN3_LATCH_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn3_latch_high_tod_second_t
-{
-    ZXIC_UINT32 tsn3_latch_high_tod_second;
-}DPP_PTPTM_PTPTM_TSN3_LATCH_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn3_latch_fracnanosecond_t
-{
-    ZXIC_UINT32 tsn3_latch_fracnanosecond;
-}DPP_PTPTM_PTPTM_TSN3_LATCH_FRACNANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn0_tod_nanosecond_t
-{
-    ZXIC_UINT32 latch_tsn0_tod_nanosecond;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN0_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn0_lower_tod_second_t
-{
-    ZXIC_UINT32 latch_lower_tsn0_tod_second;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN0_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn0_high_tod_second_t
-{
-    ZXIC_UINT32 latch_high_tsn0_tod_second;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN0_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn0_fracnanosecond_t
-{
-    ZXIC_UINT32 latch_tsn0_fracnanosecond;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN0_FRACNANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn1_tod_nanosecond_t
-{
-    ZXIC_UINT32 latch_tsn1_tod_nanosecond;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN1_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn1_lower_tod_second_t
-{
-    ZXIC_UINT32 latch_lower_tsn1_tod_second;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN1_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn1_high_tod_second_t
-{
-    ZXIC_UINT32 latch_high_tsn1_tod_second;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN1_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn1_fracnanosecond_t
-{
-    ZXIC_UINT32 latch_tsn1_fracnanosecond;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN1_FRACNANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn2_tod_nanosecond_t
-{
-    ZXIC_UINT32 latch_tsn2_tod_nanosecond;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN2_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn2_lower_tod_second_t
-{
-    ZXIC_UINT32 latch_lower_tsn2_tod_second;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN2_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn2_high_tod_second_t
-{
-    ZXIC_UINT32 latch_high_tsn2_tod_second;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN2_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn2_fracnanosecond_t
-{
-    ZXIC_UINT32 latch_tsn2_fracnanosecond;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN2_FRACNANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn3_tod_nanosecond_t
-{
-    ZXIC_UINT32 latch_tsn3_tod_nanosecond;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN3_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn3_lower_tod_second_t
-{
-    ZXIC_UINT32 latch_lower_tsn3_tod_second;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN3_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn3_high_tod_second_t
-{
-    ZXIC_UINT32 latch_high_tsn3_tod_second;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN3_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn3_fracnanosecond_t
-{
-    ZXIC_UINT32 latch_tsn3_fracnanosecond;
-}DPP_PTPTM_PTPTM_PP1S_LATCH_TSN3_FRACNANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn0_real_tod_nanosecond_t
-{
-    ZXIC_UINT32 tsn0_real_tod_nanosecond;
-}DPP_PTPTM_PTPTM_TSN0_REAL_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn0_real_lower_tod_second_t
-{
-    ZXIC_UINT32 tsn0_real_lower_tod_second;
-}DPP_PTPTM_PTPTM_TSN0_REAL_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn0_real_high_tod_second_t
-{
-    ZXIC_UINT32 tsn0_real_high_tod_second;
-}DPP_PTPTM_PTPTM_TSN0_REAL_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn1_real_tod_nanosecond_t
-{
-    ZXIC_UINT32 tsn1_real_tod_nanosecond;
-}DPP_PTPTM_PTPTM_TSN1_REAL_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn1_real_lower_tod_second_t
-{
-    ZXIC_UINT32 tsn1_real_lower_tod_second;
-}DPP_PTPTM_PTPTM_TSN1_REAL_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn1_real_high_tod_second_t
-{
-    ZXIC_UINT32 tsn1_real_high_tod_second;
-}DPP_PTPTM_PTPTM_TSN1_REAL_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn2_real_tod_nanosecond_t
-{
-    ZXIC_UINT32 tsn2_real_tod_nanosecond;
-}DPP_PTPTM_PTPTM_TSN2_REAL_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn2_real_lower_tod_second_t
-{
-    ZXIC_UINT32 tsn2_real_lower_tod_second;
-}DPP_PTPTM_PTPTM_TSN2_REAL_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn2_real_high_tod_second_t
-{
-    ZXIC_UINT32 tsn2_real_high_tod_second;
-}DPP_PTPTM_PTPTM_TSN2_REAL_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn3_real_tod_nanosecond_t
-{
-    ZXIC_UINT32 tsn3_real_tod_nanosecond;
-}DPP_PTPTM_PTPTM_TSN3_REAL_TOD_NANOSECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn3_real_lower_tod_second_t
-{
-    ZXIC_UINT32 tsn3_real_lower_tod_second;
-}DPP_PTPTM_PTPTM_TSN3_REAL_LOWER_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_tsn3_real_high_tod_second_t
-{
-    ZXIC_UINT32 tsn3_real_high_tod_second;
-}DPP_PTPTM_PTPTM_TSN3_REAL_HIGH_TOD_SECOND_T;
-
-typedef struct dpp_ptptm_ptptm_real_ptp_clock_cycle_integer_t
-{
-    ZXIC_UINT32 integeral_nanosecond_of_real_ptp_clock_cycle;
-}DPP_PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_INTEGER_T;
-
-typedef struct dpp_ptptm_ptptm_real_ptp_clock_cycle_fraction_t
-{
-    ZXIC_UINT32 fractional_nanosecond_of_real_ptp_clock_cycle;
-}DPP_PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_FRACTION_T;
-
-typedef struct dpp_ptptm_ptptm_real_tsn0_clock_cycle_integer_t
-{
-    ZXIC_UINT32 integeral_nanosecond_of_real_tsn0_clock_cycle;
-}DPP_PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_INTEGER_T;
-
-typedef struct dpp_ptptm_ptptm_real_tsn0_clock_cycle_fraction_t
-{
-    ZXIC_UINT32 fractional_nanosecond_of_real_tsn0_clock_cycle;
-}DPP_PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_FRACTION_T;
-
-typedef struct dpp_ptptm_ptptm_real_tsn1_clock_cycle_integer_t
-{
-    ZXIC_UINT32 integeral_nanosecond_of_real_tsn1_clock_cycle;
-}DPP_PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_INTEGER_T;
-
-typedef struct dpp_ptptm_ptptm_real_tsn1_clock_cycle_fraction_t
-{
-    ZXIC_UINT32 fractional_nanosecond_of_real_tsn1_clock_cycle;
-}DPP_PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_FRACTION_T;
-
-typedef struct dpp_ptptm_ptptm_real_tsn2_clock_cycle_integer_t
-{
-    ZXIC_UINT32 integeral_nanosecond_of_real_tsn2_clock_cycle;
-}DPP_PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_INTEGER_T;
-
-typedef struct dpp_ptptm_ptptm_real_tsn2_clock_cycle_fraction_t
-{
-    ZXIC_UINT32 fractional_nanosecond_of_real_tsn2_clock_cycle;
-}DPP_PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_FRACTION_T;
-
-typedef struct dpp_ptptm_ptptm_real_tsn3_clock_cycle_integer_t
-{
-    ZXIC_UINT32 integeral_nanosecond_of_real_tsn3_clock_cycle;
-}DPP_PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_INTEGER_T;
-
-typedef struct dpp_ptptm_ptptm_real_tsn3_clock_cycle_fraction_t
-{
-    ZXIC_UINT32 fractional_nanosecond_of_real_tsn3_clock_cycle;
-}DPP_PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_FRACTION_T;
+typedef struct dpp_ptptm_ptp_top_pp1s_interrupt_t {
+	ZXIC_UINT32 int_state;
+	ZXIC_UINT32 int_test;
+	ZXIC_UINT32 int_clr;
+	ZXIC_UINT32 int_en;
+} DPP_PTPTM_PTP_TOP_PP1S_INTERRUPT_T;
+
+typedef struct dpp_ptptm_ptp_top_pp1s_external_select_t {
+	ZXIC_UINT32 pp1s_external_select;
+} DPP_PTPTM_PTP_TOP_PP1S_EXTERNAL_SELECT_T;
+
+typedef struct dpp_ptptm_ptp_top_pp1s_out_select_t {
+	ZXIC_UINT32 pp1s_out_sel;
+} DPP_PTPTM_PTP_TOP_PP1S_OUT_SELECT_T;
+
+typedef struct dpp_ptptm_ptp_top_test_pp1s_select_t {
+	ZXIC_UINT32 test_pp1s_sel;
+} DPP_PTPTM_PTP_TOP_TEST_PP1S_SELECT_T;
+
+typedef struct dpp_ptptm_ptp_top_local_pp1s_en_t {
+	ZXIC_UINT32 local_pp1s_en;
+} DPP_PTPTM_PTP_TOP_LOCAL_PP1S_EN_T;
+
+typedef struct dpp_ptptm_ptp_top_local_pp1s_adjust_t {
+	ZXIC_UINT32 local_pp1s_adjust_sel;
+	ZXIC_UINT32 local_pp1s_adjust_en;
+} DPP_PTPTM_PTP_TOP_LOCAL_PP1S_ADJUST_T;
+
+typedef struct dpp_ptptm_ptp_top_local_pp1s_adjust_value_t {
+	ZXIC_UINT32 local_pp1s_adjust_value;
+} DPP_PTPTM_PTP_TOP_LOCAL_PP1S_ADJUST_VALUE_T;
+
+typedef struct dpp_ptptm_ptp_top_pp1s_to_np_select_t {
+	ZXIC_UINT32 pp1s_to_np_sel;
+} DPP_PTPTM_PTP_TOP_PP1S_TO_NP_SELECT_T;
+
+typedef struct dpp_ptptm_ptp_top_pd_u1_sel_t {
+	ZXIC_UINT32 pd_u1_sel1;
+	ZXIC_UINT32 pd_u1_sel0;
+} DPP_PTPTM_PTP_TOP_PD_U1_SEL_T;
+
+typedef struct dpp_ptptm_ptp_top_pd_u1_pd0_shift_t {
+	ZXIC_UINT32 pd_u1_pd0_shift;
+} DPP_PTPTM_PTP_TOP_PD_U1_PD0_SHIFT_T;
+
+typedef struct dpp_ptptm_ptp_top_pd_u1_pd1_shift_t {
+	ZXIC_UINT32 pd_u1_pd1_shift;
+} DPP_PTPTM_PTP_TOP_PD_U1_PD1_SHIFT_T;
+
+typedef struct dpp_ptptm_ptp_top_pd_u1_result_t {
+	ZXIC_UINT32 pd_u1_result_sign;
+	ZXIC_UINT32 pd_u1_overflow;
+	ZXIC_UINT32 pd_u1_result;
+} DPP_PTPTM_PTP_TOP_PD_U1_RESULT_T;
+
+typedef struct dpp_ptptm_ptp_top_pd_u2_sel_t {
+	ZXIC_UINT32 pd_u2_sel1;
+	ZXIC_UINT32 pd_u2_sel0;
+} DPP_PTPTM_PTP_TOP_PD_U2_SEL_T;
+
+typedef struct dpp_ptptm_ptp_top_pd_u2_pd0_shift_t {
+	ZXIC_UINT32 pd_u2_pd0_shift;
+} DPP_PTPTM_PTP_TOP_PD_U2_PD0_SHIFT_T;
+
+typedef struct dpp_ptptm_ptp_top_pd_u2_pd1_shift_t {
+	ZXIC_UINT32 pd_u2_pd1_shift;
+} DPP_PTPTM_PTP_TOP_PD_U2_PD1_SHIFT_T;
+
+typedef struct dpp_ptptm_ptp_top_pd_u2_result_t {
+	ZXIC_UINT32 pd_u2_result_sign;
+	ZXIC_UINT32 pd_u2_overflow;
+	ZXIC_UINT32 pd_u2_result;
+} DPP_PTPTM_PTP_TOP_PD_U2_RESULT_T;
+
+typedef struct dpp_ptptm_ptp_top_tsn_group_nanosecond_delay0_t {
+	ZXIC_UINT32 tsn_group_nanosecond_delay0;
+} DPP_PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY0_T;
+
+typedef struct dpp_ptptm_ptp_top_tsn_group_fracnanosecond_delay0_t {
+	ZXIC_UINT32 tsn_group_fracnanosecond_delay0;
+} DPP_PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY0_T;
+
+typedef struct dpp_ptptm_ptp_top_tsn_group_nanosecond_delay1_t {
+	ZXIC_UINT32 tsn_group_nanosecond_delay1;
+} DPP_PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY1_T;
+
+typedef struct dpp_ptptm_ptp_top_tsn_group_fracnanosecond_delay1_t {
+	ZXIC_UINT32 tsn_group_fracnanosecond_delay1;
+} DPP_PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY1_T;
+
+typedef struct dpp_ptptm_ptp_top_tsn_group_nanosecond_delay2_t {
+	ZXIC_UINT32 tsn_group_nanosecond_delay2;
+} DPP_PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY2_T;
+
+typedef struct dpp_ptptm_ptp_top_tsn_group_fracnanosecond_delay2_t {
+	ZXIC_UINT32 tsn_group_fracnanosecond_delay2;
+} DPP_PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY2_T;
+
+typedef struct dpp_ptptm_ptp_top_tsn_group_nanosecond_delay3_t {
+	ZXIC_UINT32 tsn_group_nanosecond_delay3;
+} DPP_PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY3_T;
+
+typedef struct dpp_ptptm_ptp_top_tsn_group_fracnanosecond_delay3_t {
+	ZXIC_UINT32 tsn_group_fracnanosecond_delay3;
+} DPP_PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY3_T;
+
+typedef struct dpp_ptptm_ptp_top_tsn_ptp1588_rdma_nanosecond_delay_t {
+	ZXIC_UINT32 ptp1588_rdma_nanosecond_delay;
+} DPP_PTPTM_PTP_TOP_TSN_PTP1588_RDMA_NANOSECOND_DELAY_T;
+
+typedef struct dpp_ptptm_ptp_top_ptp1588_rdma_fracnanosecond_delay_t {
+	ZXIC_UINT32 ptp1588_rdma_fracnanosecond_delay;
+} DPP_PTPTM_PTP_TOP_PTP1588_RDMA_FRACNANOSECOND_DELAY_T;
+
+typedef struct dpp_ptptm_ptp_top_ptp1588_np_nanosecond_delay_t {
+	ZXIC_UINT32 ptp1588_np_nanosecond_delay;
+} DPP_PTPTM_PTP_TOP_PTP1588_NP_NANOSECOND_DELAY_T;
+
+typedef struct dpp_ptptm_ptp_top_ptp1588_np_fracnanosecond_delay_t {
+	ZXIC_UINT32 ptp1588_np_fracnanosecond_delay;
+} DPP_PTPTM_PTP_TOP_PTP1588_NP_FRACNANOSECOND_DELAY_T;
+
+typedef struct dpp_ptptm_ptp_top_time_sync_period_t {
+	ZXIC_UINT32 time_sync_period;
+} DPP_PTPTM_PTP_TOP_TIME_SYNC_PERIOD_T;
+
+typedef struct dpp_ptptm_ptptm_module_id_t {
+	ZXIC_UINT32 module_id;
+} DPP_PTPTM_PTPTM_MODULE_ID_T;
+
+typedef struct dpp_ptptm_ptptm_module_version_t {
+	ZXIC_UINT32 module_major_version;
+	ZXIC_UINT32 module_minor_version;
+} DPP_PTPTM_PTPTM_MODULE_VERSION_T;
+
+typedef struct dpp_ptptm_ptptm_module_date_t {
+	ZXIC_UINT32 year;
+	ZXIC_UINT32 month;
+	ZXIC_UINT32 date;
+} DPP_PTPTM_PTPTM_MODULE_DATE_T;
+
+typedef struct dpp_ptptm_ptptm_interrupt_status_t {
+	ZXIC_UINT32 pps_in_status;
+	ZXIC_UINT32 fifo_almost_full_status;
+	ZXIC_UINT32 fifo_no_empty_status;
+	ZXIC_UINT32 trigger_output_status;
+	ZXIC_UINT32 trigger_input_status;
+} DPP_PTPTM_PTPTM_INTERRUPT_STATUS_T;
+
+typedef struct dpp_ptptm_ptptm_interrupt_event_t {
+	ZXIC_UINT32 pps_in_event;
+	ZXIC_UINT32 fifo_almost_full_event;
+	ZXIC_UINT32 fifo_no_empty_event;
+	ZXIC_UINT32 trigger_output_event;
+	ZXIC_UINT32 trigger_input_event;
+} DPP_PTPTM_PTPTM_INTERRUPT_EVENT_T;
+
+typedef struct dpp_ptptm_ptptm_interrupt_mask_t {
+	ZXIC_UINT32 pps_in_event_mask;
+	ZXIC_UINT32 fifo_almost_full_event_mask;
+	ZXIC_UINT32 fifo_no_empty_event_mask;
+	ZXIC_UINT32 trigger_output_event_mask;
+	ZXIC_UINT32 trigger_input_eventt_mask;
+} DPP_PTPTM_PTPTM_INTERRUPT_MASK_T;
+
+typedef struct dpp_ptptm_ptptm_interrupt_test_t {
+	ZXIC_UINT32 trigger_pps_in_event_test;
+	ZXIC_UINT32 trigger_fifo_almost_full_event_test;
+	ZXIC_UINT32 trigger_fifo_no_empty_event_test;
+	ZXIC_UINT32 trigger_output_event_test;
+	ZXIC_UINT32 trigger_input_event_test;
+} DPP_PTPTM_PTPTM_INTERRUPT_TEST_T;
+
+typedef struct dpp_ptptm_ptptm_hw_clock_cycle_integer_t {
+	ZXIC_UINT32 integeral_nanosecond_of_hw_clock_cycle;
+} DPP_PTPTM_PTPTM_HW_CLOCK_CYCLE_INTEGER_T;
+
+typedef struct dpp_ptptm_ptptm_hw_clock_cycle_fraction_t {
+	ZXIC_UINT32 fractional_nanosecond_of_hw_clock_cycle;
+} DPP_PTPTM_PTPTM_HW_CLOCK_CYCLE_FRACTION_T;
+
+typedef struct dpp_ptptm_ptptm_ptp_clock_cycle_integer_t {
+	ZXIC_UINT32 integeral_nanosecond_of_ptp_clock_cycle;
+} DPP_PTPTM_PTPTM_PTP_CLOCK_CYCLE_INTEGER_T;
+
+typedef struct dpp_ptptm_ptptm_ptp_clock_cycle_fraction_t {
+	ZXIC_UINT32 fractional_nanosecond_of_ptp_clock_cycle;
+} DPP_PTPTM_PTPTM_PTP_CLOCK_CYCLE_FRACTION_T;
+
+typedef struct dpp_ptptm_ptptm_ptp_configuration_t {
+	ZXIC_UINT32 trig_oe;
+	ZXIC_UINT32 hw_time_update_en;
+	ZXIC_UINT32 ptp1588_tod_time_update_en;
+	ZXIC_UINT32 timer_enable;
+	ZXIC_UINT32 pps_output_enable;
+	ZXIC_UINT32 pp1_output_enable;
+	ZXIC_UINT32 pp2_output_enable;
+	ZXIC_UINT32 enable_writing_timestamps_to_the_fifo;
+	ZXIC_UINT32 l2s_time_output_select;
+	ZXIC_UINT32 reserved_9;
+	ZXIC_UINT32 pps_input_select;
+	ZXIC_UINT32 pp_output_select;
+	ZXIC_UINT32 reserved_6;
+	ZXIC_UINT32 timer_run_mode;
+	ZXIC_UINT32 update_command_select;
+	ZXIC_UINT32 trigger_out_enable;
+	ZXIC_UINT32 trigger_in_enable;
+	ZXIC_UINT32 timer_capture_slave_mode;
+} DPP_PTPTM_PTPTM_PTP_CONFIGURATION_T;
+
+typedef struct dpp_ptptm_ptptm_timer_control_t {
+	ZXIC_UINT32 ptpmoutputsynchroningstate;
+	ZXIC_UINT32 ptp1588_fifo_read_command;
+	ZXIC_UINT32 adjust_the_timer;
+} DPP_PTPTM_PTPTM_TIMER_CONTROL_T;
+
+typedef struct dpp_ptptm_ptptm_pps_income_delay_t {
+	ZXIC_UINT32 pps_income_delay_nanosecond;
+	ZXIC_UINT32 pps_income_delay_frac_nanosecond;
+} DPP_PTPTM_PTPTM_PPS_INCOME_DELAY_T;
+
+typedef struct dpp_ptptm_ptptm_clock_cycle_update_t {
+	ZXIC_UINT32 tsn3_clock_cycle_update_enable;
+	ZXIC_UINT32 tsn2_clock_cycle_update_enable;
+	ZXIC_UINT32 tsn1_clock_cycle_update_enable;
+	ZXIC_UINT32 tsn0_clock_cycle_update_enable;
+	ZXIC_UINT32 ptp1588_clock_cycle_update_enable;
+} DPP_PTPTM_PTPTM_CLOCK_CYCLE_UPDATE_T;
+
+typedef struct dpp_ptptm_ptptm_cycle_time_of_output_period_pulse_1_t {
+	ZXIC_UINT32 clock_number_of_output_period_pulse_1;
+} DPP_PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_1_T;
+
+typedef struct dpp_ptptm_ptptm_cycle_time_of_output_period_pulse_2_t {
+	ZXIC_UINT32 clock_number_of_output_period_pulse_2;
+} DPP_PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_2_T;
+
+typedef struct dpp_ptptm_ptptm_timer_latch_en_t {
+	ZXIC_UINT32 latch_the_timer_en;
+} DPP_PTPTM_PTPTM_TIMER_LATCH_EN_T;
+
+typedef struct dpp_ptptm_ptptm_timer_latch_sel_t {
+	ZXIC_UINT32 timer_latch_sel;
+} DPP_PTPTM_PTPTM_TIMER_LATCH_SEL_T;
+
+typedef struct dpp_ptptm_ptptm_trigger_in_tod_nanosecond_t {
+	ZXIC_UINT32 trigger_in_tod_nanosecond;
+} DPP_PTPTM_PTPTM_TRIGGER_IN_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_trigger_in_lower_tod_second_t {
+	ZXIC_UINT32 trigger_in_lower_tod_second;
+} DPP_PTPTM_PTPTM_TRIGGER_IN_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_trigger_in_high_tod_second_t {
+	ZXIC_UINT32 trigger_in_high_tod_second;
+} DPP_PTPTM_PTPTM_TRIGGER_IN_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_trigger_in_fracnanosecond_t {
+	ZXIC_UINT32 trigger_in_fracnanosecond;
+} DPP_PTPTM_PTPTM_TRIGGER_IN_FRACNANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_trigger_in_hardware_time_low_t {
+	ZXIC_UINT32 trigger_in_hardware_time_low;
+} DPP_PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_LOW_T;
+
+typedef struct dpp_ptptm_ptptm_trigger_in_hardware_time_high_t {
+	ZXIC_UINT32 trigger_in_hardware_time_high;
+} DPP_PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_HIGH_T;
+
+typedef struct dpp_ptptm_ptptm_trigger_out_tod_nanosecond_t {
+	ZXIC_UINT32 trigger_out_tod_nanosecond;
+} DPP_PTPTM_PTPTM_TRIGGER_OUT_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_trigger_out_lower_tod_second_t {
+	ZXIC_UINT32 trigger_out_lower_tod_second;
+} DPP_PTPTM_PTPTM_TRIGGER_OUT_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_trigger_out_high_tod_second_t {
+	ZXIC_UINT32 trigger_out_high_tod_second;
+} DPP_PTPTM_PTPTM_TRIGGER_OUT_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_trigger_out_hardware_time_low_t {
+	ZXIC_UINT32 trigger_out_hardware_time_low;
+} DPP_PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_LOW_T;
+
+typedef struct dpp_ptptm_ptptm_trigger_out_hardware_time_high_t {
+	ZXIC_UINT32 trigger_out_hardware_time_high;
+} DPP_PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_HIGH_T;
+
+typedef struct dpp_ptptm_ptptm_adjust_tod_nanosecond_t {
+	ZXIC_UINT32 adjust_tod_nanosecond;
+} DPP_PTPTM_PTPTM_ADJUST_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_adjust_lower_tod_second_t {
+	ZXIC_UINT32 adjust_lower_tod_second;
+} DPP_PTPTM_PTPTM_ADJUST_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_adjust_high_tod_second_t {
+	ZXIC_UINT32 adjust_high_tod_second;
+} DPP_PTPTM_PTPTM_ADJUST_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_adjust_fracnanosecond_t {
+	ZXIC_UINT32 adjust_fracnanosecond;
+} DPP_PTPTM_PTPTM_ADJUST_FRACNANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_adjust_hardware_time_low_t {
+	ZXIC_UINT32 adjust_hardware_time_low;
+} DPP_PTPTM_PTPTM_ADJUST_HARDWARE_TIME_LOW_T;
+
+typedef struct dpp_ptptm_ptptm_adjust_hardware_time_high_t {
+	ZXIC_UINT32 adjust_hardware_time_high;
+} DPP_PTPTM_PTPTM_ADJUST_HARDWARE_TIME_HIGH_T;
+
+typedef struct dpp_ptptm_ptptm_latch_tod_nanosecond_t {
+	ZXIC_UINT32 latch_tod_nanosecond;
+} DPP_PTPTM_PTPTM_LATCH_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_latch_lower_tod_second_t {
+	ZXIC_UINT32 latch_lower_tod_second;
+} DPP_PTPTM_PTPTM_LATCH_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_latch_high_tod_second_t {
+	ZXIC_UINT32 latch_high_tod_second;
+} DPP_PTPTM_PTPTM_LATCH_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_latch_fracnanosecond_t {
+	ZXIC_UINT32 latch_fracnanosecond;
+} DPP_PTPTM_PTPTM_LATCH_FRACNANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_latch_hardware_time_low_t {
+	ZXIC_UINT32 latch_hardware_time_low;
+} DPP_PTPTM_PTPTM_LATCH_HARDWARE_TIME_LOW_T;
+
+typedef struct dpp_ptptm_ptptm_latch_hardware_time_high_t {
+	ZXIC_UINT32 latch_hardware_time_high;
+} DPP_PTPTM_PTPTM_LATCH_HARDWARE_TIME_HIGH_T;
+
+typedef struct dpp_ptptm_ptptm_real_tod_nanosecond_t {
+	ZXIC_UINT32 real_tod_nanosecond;
+} DPP_PTPTM_PTPTM_REAL_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_real_lower_tod_second_t {
+	ZXIC_UINT32 real_lower_tod_second;
+} DPP_PTPTM_PTPTM_REAL_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_real_high_tod_second_t {
+	ZXIC_UINT32 real_high_tod_second;
+} DPP_PTPTM_PTPTM_REAL_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_real_hardware_time_low_t {
+	ZXIC_UINT32 real_hardware_time_low;
+} DPP_PTPTM_PTPTM_REAL_HARDWARE_TIME_LOW_T;
+
+typedef struct dpp_ptptm_ptptm_real_hardware_time_high_t {
+	ZXIC_UINT32 real_hardware_time_high;
+} DPP_PTPTM_PTPTM_REAL_HARDWARE_TIME_HIGH_T;
+
+typedef struct dpp_ptptm_ptptm_ptp1588_event_message_port_t {
+	ZXIC_UINT32 ptp1588_event_message_port;
+} DPP_PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_PORT_T;
+
+typedef struct dpp_ptptm_ptptm_ptp1588_event_message_timestamp_low_t {
+	ZXIC_UINT32 ptp1588_event_message_timestamp_low;
+} DPP_PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_LOW_T;
+
+typedef struct dpp_ptptm_ptptm_ptp1588_event_message_timestamp_high_t {
+	ZXIC_UINT32 ptp1588_event_message_timestamp_high;
+} DPP_PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_HIGH_T;
+
+typedef struct dpp_ptptm_ptptm_ptp1588_event_message_fifo_status_t {
+	ZXIC_UINT32 fifo_full;
+	ZXIC_UINT32 fifo_empty;
+	ZXIC_UINT32 timestamps_count;
+} DPP_PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_FIFO_STATUS_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tod_nanosecond_t {
+	ZXIC_UINT32 latch_1588tod_nanosecond;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_lower_tod_second_t {
+	ZXIC_UINT32 latch_lower_1588tod_second;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_high_tod_second_t {
+	ZXIC_UINT32 latch_high_1588tod_second;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_fracnanosecond_t {
+	ZXIC_UINT32 latch_1588fracnanosecond;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_FRACNANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn_time_configuration_t {
+	ZXIC_UINT32 tsn_pps_enable;
+	ZXIC_UINT32 tsn_timer_enable;
+	ZXIC_UINT32 tsn_timer_run_mode;
+	ZXIC_UINT32 timer_capture_slave_mode;
+} DPP_PTPTM_PTPTM_TSN_TIME_CONFIGURATION_T;
+
+typedef struct dpp_ptptm_ptptm_tsn_timer_control_t {
+	ZXIC_UINT32 adjust_the_tsn3_timer;
+	ZXIC_UINT32 adjust_the_tsn2_timer;
+	ZXIC_UINT32 adjust_the_tsn1_timer;
+	ZXIC_UINT32 adjust_the_tsn0_timer;
+} DPP_PTPTM_PTPTM_TSN_TIMER_CONTROL_T;
+
+typedef struct dpp_ptptm_ptptm_tsn0_clock_cycle_integer_t {
+	ZXIC_UINT32 integeral_nanosecond_of_tsn0_clock_cycle;
+} DPP_PTPTM_PTPTM_TSN0_CLOCK_CYCLE_INTEGER_T;
+
+typedef struct dpp_ptptm_ptptm_tsn0_clock_cycle_fraction_t {
+	ZXIC_UINT32 fractional_nanosecond_of_tsn0_clock_cycle;
+} DPP_PTPTM_PTPTM_TSN0_CLOCK_CYCLE_FRACTION_T;
+
+typedef struct dpp_ptptm_ptptm_tsn1_clock_cycle_integer_t {
+	ZXIC_UINT32 integeral_nanosecond_of_tsn1_clock_cycle;
+} DPP_PTPTM_PTPTM_TSN1_CLOCK_CYCLE_INTEGER_T;
+
+typedef struct dpp_ptptm_ptptm_tsn1_clock_cycle_fraction_t {
+	ZXIC_UINT32 fractional_nanosecond_of_tsn1_clock_cycle;
+} DPP_PTPTM_PTPTM_TSN1_CLOCK_CYCLE_FRACTION_T;
+
+typedef struct dpp_ptptm_ptptm_tsn2_clock_cycle_integer_t {
+	ZXIC_UINT32 integeral_nanosecond_of_tsn2_clock_cycle;
+} DPP_PTPTM_PTPTM_TSN2_CLOCK_CYCLE_INTEGER_T;
+
+typedef struct dpp_ptptm_ptptm_tsn2_clock_cycle_fraction_t {
+	ZXIC_UINT32 fractional_nanosecond_of_tsn2_clock_cycle;
+} DPP_PTPTM_PTPTM_TSN2_CLOCK_CYCLE_FRACTION_T;
+
+typedef struct dpp_ptptm_ptptm_tsn3_clock_cycle_integer_t {
+	ZXIC_UINT32 integeral_nanosecond_of_tsn3_clock_cycle;
+} DPP_PTPTM_PTPTM_TSN3_CLOCK_CYCLE_INTEGER_T;
+
+typedef struct dpp_ptptm_ptptm_tsn3_clock_cycle_fraction_t {
+	ZXIC_UINT32 fractional_nanosecond_of_tsn3_clock_cycle;
+} DPP_PTPTM_PTPTM_TSN3_CLOCK_CYCLE_FRACTION_T;
+
+typedef struct dpp_ptptm_ptptm_tsn0_adjust_tod_nanosecond_t {
+	ZXIC_UINT32 tsn0_adjust_tod_nanosecond;
+} DPP_PTPTM_PTPTM_TSN0_ADJUST_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn0_adjust_lower_tod_second_t {
+	ZXIC_UINT32 tsn0_adjust_lower_tod_second;
+} DPP_PTPTM_PTPTM_TSN0_ADJUST_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn0_adjust_high_tod_second_t {
+	ZXIC_UINT32 tsn0_adjust_high_tod_second;
+} DPP_PTPTM_PTPTM_TSN0_ADJUST_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn0_adjust_fracnanosecond_t {
+	ZXIC_UINT32 tsn0_adjust_fracnanosecond;
+} DPP_PTPTM_PTPTM_TSN0_ADJUST_FRACNANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn1_adjust_tod_nanosecond_t {
+	ZXIC_UINT32 tsn1_adjust_tod_nanosecond;
+} DPP_PTPTM_PTPTM_TSN1_ADJUST_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn1_adjust_lower_tod_second_t {
+	ZXIC_UINT32 tsn1_adjust_lower_tod_second;
+} DPP_PTPTM_PTPTM_TSN1_ADJUST_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn1_adjust_high_tod_second_t {
+	ZXIC_UINT32 tsn1_adjust_high_tod_second;
+} DPP_PTPTM_PTPTM_TSN1_ADJUST_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn1_adjust_fracnanosecond_t {
+	ZXIC_UINT32 tsn1_adjust_fracnanosecond;
+} DPP_PTPTM_PTPTM_TSN1_ADJUST_FRACNANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn2_adjust_tod_nanosecond_t {
+	ZXIC_UINT32 tsn2_adjust_tod_nanosecond;
+} DPP_PTPTM_PTPTM_TSN2_ADJUST_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn2_adjust_lower_tod_second_t {
+	ZXIC_UINT32 tsn2_adjust_lower_tod_second;
+} DPP_PTPTM_PTPTM_TSN2_ADJUST_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn2_adjust_high_tod_second_t {
+	ZXIC_UINT32 tsn2_adjust_high_tod_second;
+} DPP_PTPTM_PTPTM_TSN2_ADJUST_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn2_adjust_fracnanosecond_t {
+	ZXIC_UINT32 tsn2_adjust_fracnanosecond;
+} DPP_PTPTM_PTPTM_TSN2_ADJUST_FRACNANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn3_adjust_tod_nanosecond_t {
+	ZXIC_UINT32 tsn3_adjust_tod_nanosecond;
+} DPP_PTPTM_PTPTM_TSN3_ADJUST_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn3_adjust_lower_tod_second_t {
+	ZXIC_UINT32 tsn3_adjust_lower_tod_second;
+} DPP_PTPTM_PTPTM_TSN3_ADJUST_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn3_adjust_high_tod_second_t {
+	ZXIC_UINT32 tsn3_adjust_high_tod_second;
+} DPP_PTPTM_PTPTM_TSN3_ADJUST_HIGH_TOD_SECOND_T;
 
+typedef struct dpp_ptptm_ptptm_tsn3_adjust_fracnanosecond_t {
+	ZXIC_UINT32 tsn3_adjust_fracnanosecond;
+} DPP_PTPTM_PTPTM_TSN3_ADJUST_FRACNANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn0_latch_tod_nanosecond_t {
+	ZXIC_UINT32 tsn0_latch_tod_nanosecond;
+} DPP_PTPTM_PTPTM_TSN0_LATCH_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn0_latch_lower_tod_second_t {
+	ZXIC_UINT32 tsn0_latch_lower_tod_second;
+} DPP_PTPTM_PTPTM_TSN0_LATCH_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn0_latch_high_tod_second_t {
+	ZXIC_UINT32 tsn0_latch_high_tod_second;
+} DPP_PTPTM_PTPTM_TSN0_LATCH_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn0_latch_fracnanosecond_t {
+	ZXIC_UINT32 tsn0_latch_fracnanosecond;
+} DPP_PTPTM_PTPTM_TSN0_LATCH_FRACNANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn1_latch_tod_nanosecond_t {
+	ZXIC_UINT32 tsn1_latch_tod_nanosecond;
+} DPP_PTPTM_PTPTM_TSN1_LATCH_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn1_latch_lower_tod_second_t {
+	ZXIC_UINT32 tsn1_latch_lower_tod_second;
+} DPP_PTPTM_PTPTM_TSN1_LATCH_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn1_latch_high_tod_second_t {
+	ZXIC_UINT32 tsn1_latch_high_tod_second;
+} DPP_PTPTM_PTPTM_TSN1_LATCH_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn1_latch_fracnanosecond_t {
+	ZXIC_UINT32 tsn1_latch_fracnanosecond;
+} DPP_PTPTM_PTPTM_TSN1_LATCH_FRACNANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn2_latch_tod_nanosecond_t {
+	ZXIC_UINT32 tsn2_latch_tod_nanosecond;
+} DPP_PTPTM_PTPTM_TSN2_LATCH_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn2_latch_lower_tod_second_t {
+	ZXIC_UINT32 tsn2_latch_lower_tod_second;
+} DPP_PTPTM_PTPTM_TSN2_LATCH_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn2_latch_high_tod_second_t {
+	ZXIC_UINT32 tsn2_latch_high_tod_second;
+} DPP_PTPTM_PTPTM_TSN2_LATCH_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn2_latch_fracnanosecond_t {
+	ZXIC_UINT32 tsn2_latch_fracnanosecond;
+} DPP_PTPTM_PTPTM_TSN2_LATCH_FRACNANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn3_latch_tod_nanosecond_t {
+	ZXIC_UINT32 tsn3_latch_tod_nanosecond;
+} DPP_PTPTM_PTPTM_TSN3_LATCH_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn3_latch_lower_tod_second_t {
+	ZXIC_UINT32 tsn3_latch_lower_tod_second;
+} DPP_PTPTM_PTPTM_TSN3_LATCH_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn3_latch_high_tod_second_t {
+	ZXIC_UINT32 tsn3_latch_high_tod_second;
+} DPP_PTPTM_PTPTM_TSN3_LATCH_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn3_latch_fracnanosecond_t {
+	ZXIC_UINT32 tsn3_latch_fracnanosecond;
+} DPP_PTPTM_PTPTM_TSN3_LATCH_FRACNANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn0_tod_nanosecond_t {
+	ZXIC_UINT32 latch_tsn0_tod_nanosecond;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TSN0_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn0_lower_tod_second_t {
+	ZXIC_UINT32 latch_lower_tsn0_tod_second;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TSN0_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn0_high_tod_second_t {
+	ZXIC_UINT32 latch_high_tsn0_tod_second;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TSN0_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn0_fracnanosecond_t {
+	ZXIC_UINT32 latch_tsn0_fracnanosecond;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TSN0_FRACNANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn1_tod_nanosecond_t {
+	ZXIC_UINT32 latch_tsn1_tod_nanosecond;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TSN1_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn1_lower_tod_second_t {
+	ZXIC_UINT32 latch_lower_tsn1_tod_second;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TSN1_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn1_high_tod_second_t {
+	ZXIC_UINT32 latch_high_tsn1_tod_second;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TSN1_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn1_fracnanosecond_t {
+	ZXIC_UINT32 latch_tsn1_fracnanosecond;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TSN1_FRACNANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn2_tod_nanosecond_t {
+	ZXIC_UINT32 latch_tsn2_tod_nanosecond;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TSN2_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn2_lower_tod_second_t {
+	ZXIC_UINT32 latch_lower_tsn2_tod_second;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TSN2_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn2_high_tod_second_t {
+	ZXIC_UINT32 latch_high_tsn2_tod_second;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TSN2_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn2_fracnanosecond_t {
+	ZXIC_UINT32 latch_tsn2_fracnanosecond;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TSN2_FRACNANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn3_tod_nanosecond_t {
+	ZXIC_UINT32 latch_tsn3_tod_nanosecond;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TSN3_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn3_lower_tod_second_t {
+	ZXIC_UINT32 latch_lower_tsn3_tod_second;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TSN3_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn3_high_tod_second_t {
+	ZXIC_UINT32 latch_high_tsn3_tod_second;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TSN3_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_pp1s_latch_tsn3_fracnanosecond_t {
+	ZXIC_UINT32 latch_tsn3_fracnanosecond;
+} DPP_PTPTM_PTPTM_PP1S_LATCH_TSN3_FRACNANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn0_real_tod_nanosecond_t {
+	ZXIC_UINT32 tsn0_real_tod_nanosecond;
+} DPP_PTPTM_PTPTM_TSN0_REAL_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn0_real_lower_tod_second_t {
+	ZXIC_UINT32 tsn0_real_lower_tod_second;
+} DPP_PTPTM_PTPTM_TSN0_REAL_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn0_real_high_tod_second_t {
+	ZXIC_UINT32 tsn0_real_high_tod_second;
+} DPP_PTPTM_PTPTM_TSN0_REAL_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn1_real_tod_nanosecond_t {
+	ZXIC_UINT32 tsn1_real_tod_nanosecond;
+} DPP_PTPTM_PTPTM_TSN1_REAL_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn1_real_lower_tod_second_t {
+	ZXIC_UINT32 tsn1_real_lower_tod_second;
+} DPP_PTPTM_PTPTM_TSN1_REAL_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn1_real_high_tod_second_t {
+	ZXIC_UINT32 tsn1_real_high_tod_second;
+} DPP_PTPTM_PTPTM_TSN1_REAL_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn2_real_tod_nanosecond_t {
+	ZXIC_UINT32 tsn2_real_tod_nanosecond;
+} DPP_PTPTM_PTPTM_TSN2_REAL_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn2_real_lower_tod_second_t {
+	ZXIC_UINT32 tsn2_real_lower_tod_second;
+} DPP_PTPTM_PTPTM_TSN2_REAL_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn2_real_high_tod_second_t {
+	ZXIC_UINT32 tsn2_real_high_tod_second;
+} DPP_PTPTM_PTPTM_TSN2_REAL_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn3_real_tod_nanosecond_t {
+	ZXIC_UINT32 tsn3_real_tod_nanosecond;
+} DPP_PTPTM_PTPTM_TSN3_REAL_TOD_NANOSECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn3_real_lower_tod_second_t {
+	ZXIC_UINT32 tsn3_real_lower_tod_second;
+} DPP_PTPTM_PTPTM_TSN3_REAL_LOWER_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_tsn3_real_high_tod_second_t {
+	ZXIC_UINT32 tsn3_real_high_tod_second;
+} DPP_PTPTM_PTPTM_TSN3_REAL_HIGH_TOD_SECOND_T;
+
+typedef struct dpp_ptptm_ptptm_real_ptp_clock_cycle_integer_t {
+	ZXIC_UINT32 integeral_nanosecond_of_real_ptp_clock_cycle;
+} DPP_PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_INTEGER_T;
+
+typedef struct dpp_ptptm_ptptm_real_ptp_clock_cycle_fraction_t {
+	ZXIC_UINT32 fractional_nanosecond_of_real_ptp_clock_cycle;
+} DPP_PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_FRACTION_T;
+
+typedef struct dpp_ptptm_ptptm_real_tsn0_clock_cycle_integer_t {
+	ZXIC_UINT32 integeral_nanosecond_of_real_tsn0_clock_cycle;
+} DPP_PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_INTEGER_T;
+
+typedef struct dpp_ptptm_ptptm_real_tsn0_clock_cycle_fraction_t {
+	ZXIC_UINT32 fractional_nanosecond_of_real_tsn0_clock_cycle;
+} DPP_PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_FRACTION_T;
+
+typedef struct dpp_ptptm_ptptm_real_tsn1_clock_cycle_integer_t {
+	ZXIC_UINT32 integeral_nanosecond_of_real_tsn1_clock_cycle;
+} DPP_PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_INTEGER_T;
+
+typedef struct dpp_ptptm_ptptm_real_tsn1_clock_cycle_fraction_t {
+	ZXIC_UINT32 fractional_nanosecond_of_real_tsn1_clock_cycle;
+} DPP_PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_FRACTION_T;
+
+typedef struct dpp_ptptm_ptptm_real_tsn2_clock_cycle_integer_t {
+	ZXIC_UINT32 integeral_nanosecond_of_real_tsn2_clock_cycle;
+} DPP_PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_INTEGER_T;
+
+typedef struct dpp_ptptm_ptptm_real_tsn2_clock_cycle_fraction_t {
+	ZXIC_UINT32 fractional_nanosecond_of_real_tsn2_clock_cycle;
+} DPP_PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_FRACTION_T;
+
+typedef struct dpp_ptptm_ptptm_real_tsn3_clock_cycle_integer_t {
+	ZXIC_UINT32 integeral_nanosecond_of_real_tsn3_clock_cycle;
+} DPP_PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_INTEGER_T;
+
+typedef struct dpp_ptptm_ptptm_real_tsn3_clock_cycle_fraction_t {
+	ZXIC_UINT32 fractional_nanosecond_of_real_tsn3_clock_cycle;
+} DPP_PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_FRACTION_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg.h
old mode 100755
new mode 100644
index 19d45913397a851696b2a01bde98141b19535731..8286ec87199c8b28b645e5c030995ca30f521600
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg.h
@@ -1,62 +1,53 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_reg.h
-* 文件标识 : 
-* 内容摘要 : 
-* 其它说明 : 
-* 当前版本 : 
-* 作    者 : 王春雷
-* 完成日期 : 2014/03/18
-* DEPARTMENT: ASIC_FPGA_R&D_Dept 
-* MANUAL_PERCENT: 100%   
- 
-* 修改记录1: 
-* 修改日期:  
-* 版 本 号:  
-* 修 改 人:  
-* 修改内容:  
-***************************************************************/
-
-#ifndef _DPP_REG_H_
-#define _DPP_REG_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "dpp_reg_struct.h"
-#include "dpp_reg_info.h"
-#include "dpp_reg_api.h"
-#include "dpp_module.h"
-
-
-#include "dpp_cfg_reg.h"
-#include "dpp_etm_reg.h"
-#include "dpp_nppu_reg.h"
-#include "dpp_ppu_reg.h"
-#include "dpp_smmu0_reg.h"
-#include "dpp_smmu1_reg.h"
-#include "dpp_se_reg.h"
-#include "dpp_stat_reg.h"
-#include "dpp_axi_reg.h"
-#include "dpp_dtb_reg.h"
-#include "dpp_trpg_reg.h"
-#include "dpp_tsn_reg.h"
-#include "dpp_ptptm_reg.h"
-
-
-#include "zxic_comm_socket.h"
-#include "zxic_comm_thread.h"
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-
-
-
-
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_reg.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2014/03/18
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#ifndef _DPP_REG_H_
+#define _DPP_REG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dpp_reg_struct.h"
+#include "dpp_reg_info.h"
+#include "dpp_reg_api.h"
+#include "dpp_module.h"
+
+#include "dpp_cfg_reg.h"
+#include "dpp_etm_reg.h"
+#include "dpp_nppu_reg.h"
+#include "dpp_ppu_reg.h"
+#include "dpp_smmu0_reg.h"
+#include "dpp_smmu1_reg.h"
+#include "dpp_se_reg.h"
+#include "dpp_stat_reg.h"
+#include "dpp_axi_reg.h"
+#include "dpp_dtb_reg.h"
+#include "dpp_trpg_reg.h"
+#include "dpp_tsn_reg.h"
+#include "dpp_ptptm_reg.h"
+
+#include "zxic_comm_socket.h"
+#include "zxic_comm_thread.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg_info.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg_info.h
index 6a46639aebd6d64a589392c74e3b8418a6cf7ebf..4ae10b510101fb1b35ba144505a978e796c72265 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg_info.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg_info.h
@@ -3,4456 +3,4454 @@
 #define _DPP_REG_INFO_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef enum dpp_reg_info_e
-{
-    ETM_CFGMT_CPU_CHECK_REGr                                              = 0,
-    ETM_CFGMT_CFGMT_BLKSIZEr                                              = 1,
-    ETM_CFGMT_REG_INT_STATE_REGr                                          = 2,
-    ETM_CFGMT_REG_INT_MASK_REGr                                           = 3,
-    ETM_CFGMT_TIMEOUT_LIMITr                                              = 4,
-    ETM_CFGMT_SUBSYSTEM_RDY_REGr                                          = 5,
-    ETM_CFGMT_SUBSYSTEM_EN_REGr                                           = 6,
-    ETM_CFGMT_CFGMT_INT_REGr                                              = 7,
-    ETM_CFGMT_QMU_WORK_MODEr                                              = 8,
-    ETM_CFGMT_CFGMT_DDR_ATTACHr                                           = 9,
-    ETM_CFGMT_CNT_MODE_REGr                                               = 10,
-    ETM_CFGMT_CLKGATE_ENr                                                 = 11,
-    ETM_CFGMT_SOFTRST_ENr                                                 = 12,
-    ETM_OLIF_IMEM_PROG_FULLr                                              = 13,
-    ETM_OLIF_QMU_PARA_PROG_FULLr                                          = 14,
-    ETM_OLIF_OLIF_INT_MASKr                                               = 15,
-    ETM_OLIF_ITMHRAM_PARITY_ERR_2_INTr                                    = 16,
-    ETM_OLIF_LIF0_PORT_RDY_MASK_Hr                                        = 17,
-    ETM_OLIF_LIF0_PORT_RDY_MASK_Lr                                        = 18,
-    ETM_OLIF_LIF0_PORT_RDY_CFG_Hr                                         = 19,
-    ETM_OLIF_LIF0_PORT_RDY_CFG_Lr                                         = 20,
-    ETM_OLIF_LIF0_LINK_RDY_MASK_CFGr                                      = 21,
-    ETM_OLIF_TM_LIF_STAT_CFGr                                             = 22,
-    ETM_OLIF_TM_LIF_SOP_STATr                                             = 23,
-    ETM_OLIF_TM_LIF_EOP_STATr                                             = 24,
-    ETM_OLIF_TM_LIF_VLD_STATr                                             = 25,
-    ETM_CGAVD_PROG_FULL_ASSERT_CFGr                                       = 26,
-    ETM_CGAVD_CGAVD_INTr                                                  = 27,
-    ETM_CGAVD_CGAVD_RAM_ERRr                                              = 28,
-    ETM_CGAVD_CGAVD_INT_MASKr                                             = 29,
-    ETM_CGAVD_CGAVD_RAM_ERR_INT_MASKr                                     = 30,
-    ETM_CGAVD_CFGMT_BYTE_MODEr                                            = 31,
-    ETM_CGAVD_AVG_QLEN_RETURN_ZERO_ENr                                    = 32,
-    ETM_CGAVD_FLOW_WRED_Q_LEN_THr                                         = 33,
-    ETM_CGAVD_FLOW_WQr                                                    = 34,
-    ETM_CGAVD_FLOW_WRED_MAX_THr                                           = 35,
-    ETM_CGAVD_FLOW_WRED_MIN_THr                                           = 36,
-    ETM_CGAVD_FLOW_WRED_CFG_PARAr                                         = 37,
-    ETM_CGAVD_PP_AVG_Q_LENr                                               = 38,
-    ETM_CGAVD_PP_TD_THr                                                   = 39,
-    ETM_CGAVD_PP_CA_MTDr                                                  = 40,
-    ETM_CGAVD_PP_WRED_GRP_TH_ENr                                          = 41,
-    ETM_CGAVD_PP_WRED_Q_LEN_THr                                           = 42,
-    ETM_CGAVD_PP_WQr                                                      = 43,
-    ETM_CGAVD_PP_WRED_MAX_THr                                             = 44,
-    ETM_CGAVD_PP_WRED_MIN_THr                                             = 45,
-    ETM_CGAVD_PP_CFG_PARAr                                                = 46,
-    ETM_CGAVD_SYS_AVG_Q_LENr                                              = 47,
-    ETM_CGAVD_SYS_TD_THr                                                  = 48,
-    ETM_CGAVD_SYS_CGAVD_METDr                                             = 49,
-    ETM_CGAVD_SYS_CFG_Q_GRP_PARAr                                         = 50,
-    ETM_CGAVD_SYS_WQr                                                     = 51,
-    ETM_CGAVD_GRED_MAX_THr                                                = 52,
-    ETM_CGAVD_GRED_MID_THr                                                = 53,
-    ETM_CGAVD_GRED_MIN_THr                                                = 54,
-    ETM_CGAVD_GRED_CFG_PARA0r                                             = 55,
-    ETM_CGAVD_GRED_CFG_PARA1r                                             = 56,
-    ETM_CGAVD_GRED_CFG_PARA2r                                             = 57,
-    ETM_CGAVD_SYS_WINDOW_TH_Hr                                            = 58,
-    ETM_CGAVD_SYS_WINDOW_TH_Lr                                            = 59,
-    ETM_CGAVD_AMPLIFY_GENE0r                                              = 60,
-    ETM_CGAVD_AMPLIFY_GENE1r                                              = 61,
-    ETM_CGAVD_AMPLIFY_GENE2r                                              = 62,
-    ETM_CGAVD_AMPLIFY_GENE3r                                              = 63,
-    ETM_CGAVD_AMPLIFY_GENE4r                                              = 64,
-    ETM_CGAVD_AMPLIFY_GENE5r                                              = 65,
-    ETM_CGAVD_AMPLIFY_GENE6r                                              = 66,
-    ETM_CGAVD_AMPLIFY_GENE7r                                              = 67,
-    ETM_CGAVD_AMPLIFY_GENE8r                                              = 68,
-    ETM_CGAVD_AMPLIFY_GENE9r                                              = 69,
-    ETM_CGAVD_AMPLIFY_GENE10r                                             = 70,
-    ETM_CGAVD_AMPLIFY_GENE11r                                             = 71,
-    ETM_CGAVD_AMPLIFY_GENE12r                                             = 72,
-    ETM_CGAVD_AMPLIFY_GENE13r                                             = 73,
-    ETM_CGAVD_AMPLIFY_GENE14r                                             = 74,
-    ETM_CGAVD_AMPLIFY_GENE15r                                             = 75,
-    ETM_CGAVD_EQUAL_PKT_LEN_ENr                                           = 76,
-    ETM_CGAVD_EQUAL_PKT_LEN_TH0r                                          = 77,
-    ETM_CGAVD_EQUAL_PKT_LEN_TH1r                                          = 78,
-    ETM_CGAVD_EQUAL_PKT_LEN_TH2r                                          = 79,
-    ETM_CGAVD_EQUAL_PKT_LEN_TH3r                                          = 80,
-    ETM_CGAVD_EQUAL_PKT_LEN_TH4r                                          = 81,
-    ETM_CGAVD_EQUAL_PKT_LEN_TH5r                                          = 82,
-    ETM_CGAVD_EQUAL_PKT_LEN_TH6r                                          = 83,
-    ETM_CGAVD_EQUAL_PKT_LEN0r                                             = 84,
-    ETM_CGAVD_EQUAL_PKT_LEN1r                                             = 85,
-    ETM_CGAVD_EQUAL_PKT_LEN2r                                             = 86,
-    ETM_CGAVD_EQUAL_PKT_LEN3r                                             = 87,
-    ETM_CGAVD_EQUAL_PKT_LEN4r                                             = 88,
-    ETM_CGAVD_EQUAL_PKT_LEN5r                                             = 89,
-    ETM_CGAVD_EQUAL_PKT_LEN6r                                             = 90,
-    ETM_CGAVD_EQUAL_PKT_LEN7r                                             = 91,
-    ETM_CGAVD_FLOW_CPU_SET_AVG_LENr                                       = 92,
-    ETM_CGAVD_FLOW_CPU_SET_Q_LENr                                         = 93,
-    ETM_CGAVD_PP_CPU_SET_AVG_Q_LENr                                       = 94,
-    ETM_CGAVD_PP_CPU_SET_Q_LENr                                           = 95,
-    ETM_CGAVD_SYS_CPU_SET_AVG_LENr                                        = 96,
-    ETM_CGAVD_SYS_CPU_SET_Q_LENr                                          = 97,
-    ETM_CGAVD_PKE_LEN_CALC_SIGNr                                          = 98,
-    ETM_CGAVD_RD_CPU_OR_RAMr                                              = 99,
-    ETM_CGAVD_Q_LEN_UPDATE_DISABLEr                                       = 100,
-    ETM_CGAVD_CGAVD_DP_SELr                                               = 101,
-    ETM_CGAVD_CGAVD_SUB_ENr                                               = 102,
-    ETM_CGAVD_DEFAULT_START_QUEUEr                                        = 103,
-    ETM_CGAVD_DEFAULT_FINISH_QUEUEr                                       = 104,
-    ETM_CGAVD_PROTOCOL_START_QUEUEr                                       = 105,
-    ETM_CGAVD_PROTOCOL_FINISH_QUEUEr                                      = 106,
-    ETM_CGAVD_UNIFORM_TD_THr                                              = 107,
-    ETM_CGAVD_UNIFORM_TD_TH_ENr                                           = 108,
-    ETM_CGAVD_CGAVD_CFG_FCr                                               = 109,
-    ETM_CGAVD_CGAVD_CFG_NO_FCr                                            = 110,
-    ETM_CGAVD_CGAVD_FORCE_IMEM_OMEMr                                      = 111,
-    ETM_CGAVD_CGAVD_SYS_Q_LEN_Lr                                          = 112,
-    ETM_CGAVD_DEFAULT_QUEUE_ENr                                           = 113,
-    ETM_CGAVD_PROTOCOL_QUEUE_ENr                                          = 114,
-    ETM_CGAVD_CFG_TC_FLOWID_DATr                                          = 115,
-    ETM_CGAVD_FLOW_TD_THr                                                 = 116,
-    ETM_CGAVD_FLOW_CA_MTDr                                                = 117,
-    ETM_CGAVD_FLOW_DYNAMIC_TH_ENr                                         = 118,
-    ETM_CGAVD_PP_NUMr                                                     = 119,
-    ETM_CGAVD_FLOW_Q_LENr                                                 = 120,
-    ETM_CGAVD_FLOW_WRED_GRPr                                              = 121,
-    ETM_CGAVD_FLOW_AVG_Q_LENr                                             = 122,
-    ETM_CGAVD_QOS_SIGNr                                                   = 123,
-    ETM_CGAVD_Q_PRIr                                                      = 124,
-    ETM_CGAVD_ODMA_TM_ITMD_RD_LOWr                                        = 125,
-    ETM_CGAVD_ODMA_TM_ITMD_RD_MIDr                                        = 126,
-    ETM_CGAVD_ODMA_TM_ITMD_RD_HIGHr                                       = 127,
-    ETM_CGAVD_CGAVD_STAT_PKT_LENr                                         = 128,
-    ETM_CGAVD_CGAVD_STAT_QNUMr                                            = 129,
-    ETM_CGAVD_CGAVD_STAT_DPr                                              = 130,
-    ETM_CGAVD_FLOW_NUM0r                                                  = 131,
-    ETM_CGAVD_FLOW_NUM1r                                                  = 132,
-    ETM_CGAVD_FLOW_NUM2r                                                  = 133,
-    ETM_CGAVD_FLOW_NUM3r                                                  = 134,
-    ETM_CGAVD_FLOW_NUM4r                                                  = 135,
-    ETM_CGAVD_FLOW0_IMEM_CNTr                                             = 136,
-    ETM_CGAVD_FLOW1_IMEM_CNTr                                             = 137,
-    ETM_CGAVD_FLOW2_IMEM_CNTr                                             = 138,
-    ETM_CGAVD_FLOW3_IMEM_CNTr                                             = 139,
-    ETM_CGAVD_FLOW4_IMEM_CNTr                                             = 140,
-    ETM_CGAVD_FLOW0_DROP_CNTr                                             = 141,
-    ETM_CGAVD_FLOW1_DROP_CNTr                                             = 142,
-    ETM_CGAVD_FLOW2_DROP_CNTr                                             = 143,
-    ETM_CGAVD_FLOW3_DROP_CNTr                                             = 144,
-    ETM_CGAVD_FLOW4_DROP_CNTr                                             = 145,
-    ETM_CGAVD_FC_COUNT_MODEr                                              = 146,
-    ETM_CGAVD_QMU_CGAVD_FC_NUMr                                           = 147,
-    ETM_CGAVD_CGAVD_ODMA_FC_NUMr                                          = 148,
-    ETM_CGAVD_CFG_OFFSETr                                                 = 149,
-    ETM_TMMU_TMMU_INIT_DONEr                                              = 150,
-    ETM_TMMU_TMMU_INT_MASK_1r                                             = 151,
-    ETM_TMMU_TMMU_INT_MASK_2r                                             = 152,
-    ETM_TMMU_CFGMT_TM_PURE_IMEM_ENr                                       = 153,
-    ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFGr                                     = 154,
-    ETM_TMMU_PD_ORDER_FIFO_AFUL_THr                                       = 155,
-    ETM_TMMU_CACHED_PD_FIFO_AFUL_THr                                      = 156,
-    ETM_TMMU_WR_CMD_FIFO_AFUL_THr                                         = 157,
-    ETM_TMMU_IMEM_ENQ_RD_FIFO_AFUL_THr                                    = 158,
-    ETM_TMMU_IMEM_ENQ_DROP_FIFO_AFUL_THr                                  = 159,
-    ETM_TMMU_IMEM_DEQ_DROP_FIFO_AFUL_THr                                  = 160,
-    ETM_TMMU_IMEM_DEQ_RD_FIFO_AFUL_THr                                    = 161,
-    ETM_TMMU_TMMU_STATES_1r                                               = 162,
-    ETM_TMMU_TMMU_STATES_2r                                               = 163,
-    ETM_SHAP_SHAP_IND_CMDr                                                = 164,
-    ETM_SHAP_SHAP_IND_STAr                                                = 165,
-    ETM_SHAP_SHAP_IND_DATA0r                                              = 166,
-    ETM_SHAP_SHAP_IND_DATA1r                                              = 167,
-    ETM_SHAP_FULL_THRESHOLDr                                              = 168,
-    ETM_SHAP_EMPTY_THRESHOLDr                                             = 169,
-    ETM_SHAP_SHAP_STA_INIT_CFGr                                           = 170,
-    ETM_SHAP_SHAP_CFG_INIT_CFGr                                           = 171,
-    ETM_SHAP_TOKEN_MODE_SWITCHr                                           = 172,
-    ETM_SHAP_TOKEN_GRAINr                                                 = 173,
-    ETM_SHAP_CRD_GRAINr                                                   = 174,
-    ETM_SHAP_SHAP_STAT_CTRLr                                              = 175,
-    ETM_SHAP_TOKEN_STAT_IDr                                               = 176,
-    ETM_SHAP_TOKEN_STATr                                                  = 177,
-    ETM_SHAP_SHAP_STAT_CLK_CNTr                                           = 178,
-    ETM_SHAP_SHAP_BUCKET_MAP_TBLr                                         = 179,
-    ETM_SHAP_BKT_PARA_TBLr                                                = 180,
-    ETM_CRDT_CREDIT_ENr                                                   = 181,
-    ETM_CRDT_CRT_INTER1r                                                  = 182,
-    ETM_CRDT_DB_TOKENr                                                    = 183,
-    ETM_CRDT_CRS_FLT_CFGr                                                 = 184,
-    ETM_CRDT_TH_SPr                                                       = 185,
-    ETM_CRDT_TH_WFQ_FQr                                                   = 186,
-    ETM_CRDT_TH_WFQ2_FQ2r                                                 = 187,
-    ETM_CRDT_TH_WFQ4_FQ4r                                                 = 188,
-    ETM_CRDT_CFG_STATEr                                                   = 189,
-    ETM_CRDT_CRDT_IND_CMDr                                                = 190,
-    ETM_CRDT_CRDT_IND_STAr                                                = 191,
-    ETM_CRDT_CRDT_IND_DATA0r                                              = 192,
-    ETM_CRDT_CRDT_IND_DATA1r                                              = 193,
-    ETM_CRDT_CRDT_STATEr                                                  = 194,
-    ETM_CRDT_STAT_QUE_ID_0r                                               = 195,
-    ETM_CRDT_STAT_QUE_ID_1r                                               = 196,
-    ETM_CRDT_STAT_QUE_ID_2r                                               = 197,
-    ETM_CRDT_STAT_QUE_ID_3r                                               = 198,
-    ETM_CRDT_STAT_QUE_ID_4r                                               = 199,
-    ETM_CRDT_STAT_QUE_ID_5r                                               = 200,
-    ETM_CRDT_STAT_QUE_ID_6r                                               = 201,
-    ETM_CRDT_STAT_QUE_ID_7r                                               = 202,
-    ETM_CRDT_STAT_QUE_ID_8r                                               = 203,
-    ETM_CRDT_STAT_QUE_ID_9r                                               = 204,
-    ETM_CRDT_STAT_QUE_ID_10r                                              = 205,
-    ETM_CRDT_STAT_QUE_ID_11r                                              = 206,
-    ETM_CRDT_STAT_QUE_ID_12r                                              = 207,
-    ETM_CRDT_STAT_QUE_ID_13r                                              = 208,
-    ETM_CRDT_STAT_QUE_ID_14r                                              = 209,
-    ETM_CRDT_STAT_QUE_ID_15r                                              = 210,
-    ETM_CRDT_STAT_QUE_CREDITr                                             = 211,
-    ETM_CRDT_CRDT_CFG_RAM_INITr                                           = 212,
-    ETM_CRDT_CRDT_STA_RAM_INITr                                           = 213,
-    ETM_CRDT_CRS_QUE_IDr                                                  = 214,
-    ETM_CRDT_QMU_CRS_END_STATEr                                           = 215,
-    ETM_CRDT_SHAP_RDYr                                                    = 216,
-    ETM_CRDT_SHAP_INT_REGr                                                = 217,
-    ETM_CRDT_SHAP_INT_MASK_REGr                                           = 218,
-    ETM_CRDT_TOKEN_STATE_ALMOST_EMPTY_THr                                 = 219,
-    ETM_CRDT_TOKEN_STATE_EMPTY_THr                                        = 220,
-    ETM_CRDT_FULL_THr                                                     = 221,
-    ETM_CRDT_PP_C_LEVEL_SHAP_ENr                                          = 222,
-    ETM_CRDT_ENQ_TOKEN_THr                                                = 223,
-    ETM_CRDT_PP_TOKENQ_LEVEL1_QSTATE_WEIGHT_CIRr                          = 224,
-    ETM_CRDT_PP_IDLE_WEIGHT_LEVEL1_CIRr                                   = 225,
-    ETM_CRDT_RCI_GRADE_TH_0_CFGr                                          = 226,
-    ETM_CRDT_RCI_GRADE_TH_1_CFGr                                          = 227,
-    ETM_CRDT_RCI_GRADE_TH_2_CFGr                                          = 228,
-    ETM_CRDT_RCI_GRADE_TH_3_CFGr                                          = 229,
-    ETM_CRDT_RCI_GRADE_TH_4_CFGr                                          = 230,
-    ETM_CRDT_RCI_GRADE_TH_5_CFGr                                          = 231,
-    ETM_CRDT_RCI_GRADE_TH_6_CFGr                                          = 232,
-    ETM_CRDT_FLOW_DEL_CMDr                                                = 233,
-    ETM_CRDT_CNT_CLRr                                                     = 234,
-    ETM_CRDT_CRDT_INT_BUSr                                                = 235,
-    ETM_CRDT_CRDT_INT_MASKr                                               = 236,
-    ETM_CRDT_CFG_WEIGHT_TOGETHERr                                         = 237,
-    ETM_CRDT_WEIGHTr                                                      = 238,
-    ETM_CRDT_DEV_SP_STATEr                                                = 239,
-    ETM_CRDT_DEV_CRSr                                                     = 240,
-    ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0r                                  = 241,
-    ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32r                                 = 242,
-    ETM_CRDT_CRDT_INTERVAL_EN_CFGr                                        = 243,
-    ETM_CRDT_Q_TOKEN_STAUE_CFGr                                           = 244,
-    ETM_CRDT_Q_TOKEN_DIST_CNTr                                            = 245,
-    ETM_CRDT_Q_TOKEN_DEC_CNTr                                             = 246,
-    ETM_CRDT_PP_WEIGHT_RAMr                                               = 247,
-    ETM_CRDT_PP_CBS_SHAPE_EN_RAMr                                         = 248,
-    ETM_CRDT_PP_NEXT_PC_Q_STATE_RAMr                                      = 249,
-    ETM_CRDT_DEV_INTERVALr                                                = 250,
-    ETM_CRDT_DEV_WFQ_CNTr                                                 = 251,
-    ETM_CRDT_DEV_WFQ_STATEr                                               = 252,
-    ETM_CRDT_DEV_ACTIVE_HEAD_PTRr                                         = 253,
-    ETM_CRDT_DEV_ACTIVE_TAIL_PTRr                                         = 254,
-    ETM_CRDT_DEV_UNACTIVE_HEAD_PTRr                                       = 255,
-    ETM_CRDT_DEV_UNACTIVE_TAIL_PTRr                                       = 256,
-    ETM_CRDT_PP_WEIGHTr                                                   = 257,
-    ETM_CRDT_PP_QUE_STATEr                                                = 258,
-    ETM_CRDT_PP_NEXT_PTRr                                                 = 259,
-    ETM_CRDT_PP_CFGr                                                      = 260,
-    ETM_CRDT_PP_UP_PTRr                                                   = 261,
-    ETM_CRDT_CREDIT_DROP_NUMr                                             = 262,
-    ETM_CRDT_SE_ID_LV0r                                                   = 263,
-    ETM_CRDT_SE_ID_LV1r                                                   = 264,
-    ETM_CRDT_SE_ID_LV2r                                                   = 265,
-    ETM_CRDT_SE_ID_LV3r                                                   = 266,
-    ETM_CRDT_SE_ID_LV4r                                                   = 267,
-    ETM_CRDT_QUE_IDr                                                      = 268,
-    ETM_CRDT_SE_INFO_LV0r                                                 = 269,
-    ETM_CRDT_SE_INFO_LV1r                                                 = 270,
-    ETM_CRDT_SE_INFO_LV2r                                                 = 271,
-    ETM_CRDT_SE_INFO_LV3r                                                 = 272,
-    ETM_CRDT_SE_INFO_LV4r                                                 = 273,
-    ETM_CRDT_QUE_STATEr                                                   = 274,
-    ETM_CRDT_EIR_OFF_IN_ADVANCEr                                          = 275,
-    ETM_CRDT_DOUBLE_LEVEL_SHAP_PREVENTr                                   = 276,
-    ETM_CRDT_ADD_STORE_CYCLEr                                             = 277,
-    ETM_CRDT_TFLAG2_WR_FLAG_SUMr                                          = 278,
-    ETM_CRDT_FLOWQUE_PARA_TBLr                                            = 279,
-    ETM_CRDT_SE_PARA_TBLr                                                 = 280,
-    ETM_CRDT_FLOWQUE_INS_TBLr                                             = 281,
-    ETM_CRDT_SE_INS_TBLr                                                  = 282,
-    ETM_CRDT_EIR_CRS_FILTER_TBLr                                          = 283,
-    ETM_QMU_QCFG_QLIST_CFG_DONEr                                          = 284,
-    ETM_QMU_QCFG_QSCH_CREDIT_VALUEr                                       = 285,
-    ETM_QMU_QCFG_QSCH_CRBAL_INIT_VALUEr                                   = 286,
-    ETM_QMU_QCFG_QSCH_CRBAL_INIT_MASKr                                    = 287,
-    ETM_QMU_CMDSCH_RD_CMD_AFUL_THr                                        = 288,
-    ETM_QMU_CFG_PORT_FC_INTERVALr                                         = 289,
-    ETM_QMU_QCFG_CSCH_AGED_CFGr                                           = 290,
-    ETM_QMU_QCFG_CSCH_AGED_SCAN_TIMEr                                     = 291,
-    ETM_QMU_QCFG_QMU_QLIST_STATE_QUERYr                                   = 292,
-    ETM_QMU_CFGMT_QSCH_CRBAL_DROP_ENr                                     = 293,
-    ETM_QMU_CFGMT_WLIST_QNUM_FIFO_AFUL_THr                                = 294,
-    ETM_QMU_QCFG_CSW_PKT_BLK_MODEr                                        = 295,
-    ETM_QMU_QCFG_QLIST_RAM_INIT_CANCELr                                   = 296,
-    ETM_QMU_QCFG_QSCH_CRBAL_TRANSFER_MODEr                                = 297,
-    ETM_QMU_QCFG_QLIST_QCLR_INTERVALr                                     = 298,
-    ETM_QMU_QCFG_QSCH_QCLR_RATEr                                          = 299,
-    ETM_QMU_QCFG_QLIST_DDR_RANDOMr                                        = 300,
-    ETM_QMU_CFGMT_QLIST_PDS_FIFO_AFULL_THr                                = 301,
-    ETM_QMU_CFGMT_SOP_CMD_FIFO_AFULL_THr                                  = 302,
-    ETM_QMU_CFGMT_NON_SOP_CMD_FIFO_AFULL_THr                              = 303,
-    ETM_QMU_CFGMT_MMU_DATA_FIFO_AFULL_THr                                 = 304,
-    ETM_QMU_QCFG_QLIST_BANK_EPT_THr                                       = 305,
-    ETM_QMU_RANDOM_BYPASS_ENr                                             = 306,
-    ETM_QMU_CFGMT_CRS_SPD_BYPASSr                                         = 307,
-    ETM_QMU_CFGMT_CRS_INTERVALr                                           = 308,
-    ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_ENr                              = 309,
-    ETM_QMU_CFG_QSCH_AUTOCRFRSTQUEr                                       = 310,
-    ETM_QMU_CFG_QSCH_AUTOCRLASTQUEr                                       = 311,
-    ETM_QMU_CFG_QSCH_AUTOCREDITRATEr                                      = 312,
-    ETM_QMU_CFG_QSCH_SCANFRSTQUEr                                         = 313,
-    ETM_QMU_CFG_QSCH_SCANLASTQUEr                                         = 314,
-    ETM_QMU_CFG_QSCH_SCANRATEr                                            = 315,
-    ETM_QMU_CFG_QSCH_SCAN_ENr                                             = 316,
-    ETM_QMU_CFGMT_QSCH_RD_CREDIT_FIFO_RATEr                               = 317,
-    ETM_QMU_QCFG_QLIST_BDEPr                                              = 318,
-    ETM_QMU_QCFG_QLIST_BHEADr                                             = 319,
-    ETM_QMU_QCFG_QLIST_BTAILr                                             = 320,
-    ETM_QMU_QCFG_QSCH_SHAP_PARAMr                                         = 321,
-    ETM_QMU_QCFG_QSCH_SHAP_TOKENr                                         = 322,
-    ETM_QMU_QCFG_QSCH_SHAP_OFFSETr                                        = 323,
-    ETM_QMU_QCFG_QSCH_CRS_EIR_THr                                         = 324,
-    ETM_QMU_QCFG_QSCH_CRS_TH1r                                            = 325,
-    ETM_QMU_QCFG_QSCH_CRS_TH2r                                            = 326,
-    ETM_QMU_QCFG_CSCH_CONGEST_THr                                         = 327,
-    ETM_QMU_QCFG_CSCH_SP_FC_THr                                           = 328,
-    ETM_QMU_QCFG_CSW_SHAP_PARAMETERr                                      = 329,
-    ETM_QMU_CFGMT_RD_RELEASE_AFUL_THr                                     = 330,
-    ETM_QMU_CFGMT_DROP_IMEM_RELEASE_FIFO_AFUL_THr                         = 331,
-    ETM_QMU_CFGMT_NNH_RD_BUF_AFUL_THr                                     = 332,
-    ETM_QMU_CFG_PID_USE_INALLr                                            = 333,
-    ETM_QMU_CFG_PID_ROUND_THr                                             = 334,
-    ETM_QMU_CFGMT_CREDIT_FIFO_AFULL_THr                                   = 335,
-    ETM_QMU_CFGMT_SCAN_FIFO_AFULL_THr                                     = 336,
-    ETM_QMU_CFGMT_SMALL_FIFO_AFUL_THr                                     = 337,
-    ETM_QMU_CFGMT_FREE_ADDR_FIFO_AFUL_THr                                 = 338,
-    ETM_QMU_CFGMT_ENQ_RPT_FIFO_AFUL_THr                                   = 339,
-    ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTHr                                    = 340,
-    ETM_QMU_QCFG_CSW_SHAP_OFFSET_VALUEr                                   = 341,
-    ETM_QMU_QCFG_CSW_FC_OFFSET_VALUEr                                     = 342,
-    ETM_QMU_QMU_INIT_DONE_STATEr                                          = 343,
-    ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_0r                                     = 344,
-    ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_1r                                     = 345,
-    ETM_QMU_QLIST_CFGMT_RAM_INIT_DONEr                                    = 346,
-    ETM_QMU_QLIST_CFGMT_RAM_ECC_ERRr                                      = 347,
-    ETM_QMU_QLIST_CFGMT_RAM_SLOT_ERRr                                     = 348,
-    ETM_QMU_QSCH_CFGMT_RAM_ECCr                                           = 349,
-    ETM_QMU_QLIST_CFGMT_FIFO_STATEr                                       = 350,
-    ETM_QMU_QLIST_QCFG_CLR_DONEr                                          = 351,
-    ETM_QMU_QMU_INT_MASK1r                                                = 352,
-    ETM_QMU_QMU_INT_MASK2r                                                = 353,
-    ETM_QMU_QMU_INT_MASK3r                                                = 354,
-    ETM_QMU_QMU_INT_MASK4r                                                = 355,
-    ETM_QMU_QMU_INT_MASK5r                                                = 356,
-    ETM_QMU_QMU_INT_MASK6r                                                = 357,
-    ETM_QMU_CMD_SCH_CFGMT_FIFO_STATEr                                     = 358,
-    ETM_QMU_QLIST_R_BCNTr                                                 = 359,
-    ETM_QMU_QSCH_RW_CRBALr                                                = 360,
-    ETM_QMU_QSCH_RW_CRSr                                                  = 361,
-    ETM_QMU_QSCH_R_WLIST_EMPTYr                                           = 362,
-    ETM_QMU_QCFG_QLIST_BARAM_RDr                                          = 363,
-    ETM_QMU_QCFG_QSCH_CRBAL_FB_RWr                                        = 364,
-    ETM_QMU_QCFG_QLIST_GRP0_BANKr                                         = 365,
-    ETM_QMU_QCFG_QLIST_GRP1_BANKr                                         = 366,
-    ETM_QMU_QCFG_QLIST_GRP2_BANKr                                         = 367,
-    ETM_QMU_QCFG_QLIST_GRP3_BANKr                                         = 368,
-    ETM_QMU_QCFG_QLIST_GRP4_BANKr                                         = 369,
-    ETM_QMU_QCFG_QLIST_GRP5_BANKr                                         = 370,
-    ETM_QMU_QCFG_QLIST_GRP6_BANKr                                         = 371,
-    ETM_QMU_QCFG_QLIST_GRP7_BANKr                                         = 372,
-    ETM_QMU_QCFG_QLIST_GRPr                                               = 373,
-    ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr                                     = 374,
-    ETM_QMU_CFGMT_DDR_IN_MMU_CFGr                                         = 375,
-    ETM_QMU_CFGMT_DDR_IN_QMU_CFGr                                         = 376,
-    ETM_QMU_CFGMT_BANK_TO_MMU_CFGr                                        = 377,
-    ETM_QMU_CFGMT_BANK_TO_QMU_CFGr                                        = 378,
-    ETM_QMU_CFGMT_GRP_RAM_N_CLR_THDr                                      = 379,
-    ETM_QMU_CFGMT_AGE_PKT_NUMr                                            = 380,
-    ETM_QMU_CFGMT_AGE_MULTI_INTERVALr                                     = 381,
-    ETM_QMU_CFGMT_QMU_PKT_AGE_ENr                                         = 382,
-    ETM_QMU_CFGMT_QMU_PKT_AGE_INTERVALr                                   = 383,
-    ETM_QMU_CFGMT_QMU_PKT_AGE_START_ENDr                                  = 384,
-    ETM_QMU_CFGMT_PKT_AGE_REQ_AFUL_THr                                    = 385,
-    ETM_QMU_CFGMT_PKT_AGE_STEP_INTERVALr                                  = 386,
-    ETM_QMU_CFGMT_QMU_IMEM_AGE_MODEr                                      = 387,
-    ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_INTERVALr                             = 388,
-    ETM_QMU_CFGMT_QMU_IMEM_TIME_AGE_INTERVALr                             = 389,
-    ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_THDr                                  = 390,
-    ETM_QMU_CFGMT_IMEM_AGE_STEP_INTERVALr                                 = 391,
-    ETM_QMU_CFGMT_QMU_ECC_BYPASS_READr                                    = 392,
-    ETM_QMU_CFGMT_QMU_RESP_STAT_FC_ENr                                    = 393,
-    ETM_QMU_CFGMT_QMU_BANK_XOFF_PDS_MODEr                                 = 394,
-    ETM_QMU_CFGMT_QMU_STAT_OFFSETr                                        = 395,
-    ETM_QMU_FC_CNT_MODEr                                                  = 396,
-    ETM_QMU_MMU_QMU_WR_FC_CNTr                                            = 397,
-    ETM_QMU_MMU_QMU_RD_FC_CNTr                                            = 398,
-    ETM_QMU_QMU_CGAVD_FC_CNTr                                             = 399,
-    ETM_QMU_CGAVD_QMU_PKT_CNTr                                            = 400,
-    ETM_QMU_CGAVD_QMU_PKTLEN_ALLr                                         = 401,
-    ETM_QMU_OBSERVE_PORTFC_SPECr                                          = 402,
-    ETM_QMU_SPEC_LIF_PORTFC_COUNTr                                        = 403,
-    ETM_QMU_CFGMT_QMU_PFC_ENr                                             = 404,
-    ETM_QMU_CFGMT_QMU_PFC_MASK_1r                                         = 405,
-    ETM_QMU_CFGMT_QMU_PFC_MASK_2r                                         = 406,
-    CFG_PCIE_INT_REPEATr                                                  = 407,
-    CFG_DMA_DMA_UP_SIZEr                                                  = 408,
-    CFG_CSR_SOC_WR_TIME_OUT_THRESHr                                       = 409,
-    NPPU_MR_CFG_CFG_SHAP_PARAMr                                           = 410,
-    NPPU_MR_CFG_CFG_SHAP_TOKENr                                           = 411,
-    NPPU_MR_CFG_IDLE_PTR_FIFO_AFUL_THr                                    = 412,
-    NPPU_MR_CFG_MR_COS_PORT_CFGr                                          = 413,
-    NPPU_PKTRX_CFG_IND_STATUSr                                            = 414,
-    NPPU_PKTRX_CFG_IND_CMDr                                               = 415,
-    NPPU_PKTRX_CFG_IND_DATA0r                                             = 416,
-    NPPU_PKTRX_CFG_IND_DATA1r                                             = 417,
-    NPPU_PKTRX_CFG_IND_DATA2r                                             = 418,
-    NPPU_PKTRX_CFG_IND_DATA3r                                             = 419,
-    NPPU_PKTRX_CFG_IND_DATA4r                                             = 420,
-    NPPU_PKTRX_CFG_IND_DATA5r                                             = 421,
-    NPPU_PKTRX_CFG_IND_DATA6r                                             = 422,
-    NPPU_PKTRX_CFG_IND_DATA7r                                             = 423,
-    NPPU_PKTRX_CFG_TCAM_0_CMDr                                            = 424,
-    NPPU_PKTRX_CFG_TCAM_1_CMDr                                            = 425,
-    NPPU_PKTRX_CFG_PORT_EN_0r                                             = 426,
-    NPPU_PKTRX_CFG_PORT_EN_1r                                             = 427,
-    NPPU_PKTRX_CFG_PORT_EN_2r                                             = 428,
-    NPPU_PKTRX_CFG_PORT_EN_3r                                             = 429,
-    NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_0r                             = 430,
-    NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_1r                             = 431,
-    NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_2r                             = 432,
-    NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_3r                             = 433,
-    NPPU_PKTRX_CFG_PORT_FC_MODE_0r                                        = 434,
-    NPPU_PKTRX_CFG_PORT_FC_MODE_1r                                        = 435,
-    NPPU_PKTRX_CFG_PORT_FC_MODE_2r                                        = 436,
-    NPPU_PKTRX_CFG_PORT_FC_MODE_3r                                        = 437,
-    NPPU_PKTRX_CFG_PORT_FC_MODE_4r                                        = 438,
-    NPPU_PKTRX_CFG_PORT_FC_MODE_5r                                        = 439,
-    NPPU_PKTRX_CFG_PORT_FC_MODE_6r                                        = 440,
-    NPPU_PKTRX_CFG_PORT_FC_MODE_7r                                        = 441,
-    NPPU_PKTRX_CFG_CFG_ISCH_AGING_THr                                     = 442,
-    NPPU_PKTRX_CFG_ISCH_FIFO_TH_0r                                        = 443,
-    NPPU_PKTRX_CFG_ISCH_CFG_1r                                            = 444,
-    NPPU_PKTRX_CFG_TCAM_0_VLDr                                            = 445,
-    NPPU_PKTRX_CFG_TCAM_1_VLDr                                            = 446,
-    NPPU_PKTRX_CFG_CPU_PORT_EN_MASKr                                      = 447,
-    NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_0r                                     = 448,
-    NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_1r                                     = 449,
-    NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_2r                                     = 450,
-    NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_3r                                     = 451,
-    NPPU_PKTRX_CFG_NPPU_STARTr                                            = 452,
-    NPPU_PKTRX_STAT_IND_STATUSr                                           = 453,
-    NPPU_PKTRX_STAT_IND_CMDr                                              = 454,
-    NPPU_PKTRX_STAT_IND_DATA0r                                            = 455,
-    NPPU_IDMA_CFG_DEBUG_CNT_OVFL_MODEr                                    = 456,
-    NPPU_IDMA_STAT_IND_STATUSr                                            = 457,
-    NPPU_IDMA_STAT_IND_CMDr                                               = 458,
-    NPPU_IDMA_STAT_IND_DATA0r                                             = 459,
-    NPPU_PBU_CFG_IND_STATUSr                                              = 460,
-    NPPU_PBU_CFG_IND_CMDr                                                 = 461,
-    NPPU_PBU_CFG_IND_DATA0r                                               = 462,
-    NPPU_PBU_CFG_IND_DATA1r                                               = 463,
-    NPPU_PBU_CFG_IND_DATA2r                                               = 464,
-    NPPU_PBU_CFG_IND_DATA3r                                               = 465,
-    NPPU_PBU_CFG_IND_DATA4r                                               = 466,
-    NPPU_PBU_CFG_IND_DATA5r                                               = 467,
-    NPPU_PBU_CFG_IND_DATA6r                                               = 468,
-    NPPU_PBU_CFG_IND_DATA7r                                               = 469,
-    NPPU_PBU_CFG_IDMA_PUBLIC_THr                                          = 470,
-    NPPU_PBU_CFG_LIF_PUBLIC_THr                                           = 471,
-    NPPU_PBU_CFG_IDMA_TOTAL_THr                                           = 472,
-    NPPU_PBU_CFG_LIF_TOTAL_THr                                            = 473,
-    NPPU_PBU_CFG_MC_TOTAL_THr                                             = 474,
-    NPPU_PBU_CFG_MC_COS10_THr                                             = 475,
-    NPPU_PBU_CFG_MC_COS32_THr                                             = 476,
-    NPPU_PBU_CFG_MC_COS54_THr                                             = 477,
-    NPPU_PBU_CFG_MC_COS76_THr                                             = 478,
-    NPPU_PBU_CFG_DEBUG_CNT_OVFL_MODEr                                     = 479,
-    NPPU_PBU_CFG_SE_KEY_AFUL_NEGATE_CFGr                                  = 480,
-    NPPU_PBU_CFG_SA_FLAGr                                                 = 481,
-    NPPU_PBU_STAT_IND_DATAr                                               = 482,
-    NPPU_PBU_STAT_IND_STATUSr                                             = 483,
-    NPPU_PBU_STAT_IND_CMDr                                                = 484,
-    NPPU_PBU_STAT_TOTAL_CNTr                                              = 485,
-    NPPU_PBU_STAT_IDMA_PUB_CNTr                                           = 486,
-    NPPU_PBU_STAT_LIF_PUB_CNTr                                            = 487,
-    NPPU_PBU_STAT_MC_TOTAL_CNTr                                           = 488,
-    NPPU_PBU_STAT_PBU_THRAM_INIT_DONEr                                    = 489,
-    NPPU_PBU_STAT_IFB_FPTR_INIT_DONEr                                     = 490,
-    NPPU_ISU_CFG_WEIGHT_NORMAL_UCr                                        = 491,
-    NPPU_ISU_CFG_FABRIC_OR_SAIPr                                          = 492,
-    NPPU_ISU_STAT_IND_STATUSr                                             = 493,
-    NPPU_ISU_STAT_IND_CMDr                                                = 494,
-    NPPU_ISU_STAT_IND_DAT0r                                               = 495,
-    NPPU_ODMA_CFG_IND_ACCESS_DONEr                                        = 496,
-    NPPU_ODMA_CFG_IND_COMMANDr                                            = 497,
-    NPPU_ODMA_CFG_IND_DAT0r                                               = 498,
-    NPPU_ODMA_CFG_IND_DAT1r                                               = 499,
-    NPPU_ODMA_CFG_FABRIC_OR_SAIPr                                         = 500,
-    NPPU_ODMA_CFG_MAX_PKT_LENr                                            = 501,
-    NPPU_ODMA_CFG_AGE_ENr                                                 = 502,
-    NPPU_ODMA_CFG_AGE_MODEr                                               = 503,
-    NPPU_ODMA_CFG_AGE_VALUE_TIMEr                                         = 504,
-    NPPU_ODMA_CFG_AGE_VALUE_ROOMr                                         = 505,
-    NPPU_ODMA_CFG_AGE_OUT_CNTr                                            = 506,
-    NPPU_ODMA_CFG_TOKEN_VALUE_Ar                                          = 507,
-    NPPU_ODMA_CFG_TOKEN_VALUE_Br                                          = 508,
-    NPPU_ODMA_CFG_CFG_SHAP_EN_P0r                                         = 509,
-    NPPU_ODMA_CFG_CFG_SHAP_EN_P1r                                         = 510,
-    NPPU_ODMA_CFG_CFG_SHAP_EN_TMr                                         = 511,
-    NPPU_ODMA_STAT_IND_STATUSr                                            = 512,
-    NPPU_ODMA_STAT_IND_CMDr                                               = 513,
-    NPPU_ODMA_STAT_IND_DATA0r                                             = 514,
-    NPPU_ODMA_STAT_DEBUG_CNT_CFGr                                         = 515,
-    NPPU_OAM_CFG_BFD_FIRSTCHK_THr                                         = 516,
-    NPPU_PBU_CFG_MEMID_0_PBU_FC_IDMATH_RAMr                               = 517,
-    NPPU_PBU_CFG_MEMID_1_PBU_FC_MACTH_RAMr                                = 518,
-    NPPU_PBU_STAT_MEMID_1_ALL_KIND_PORT_CNTr                              = 519,
-    NPPU_PBU_STAT_MEMID_2_PPU_PBU_IFB_REQ_VLD_CNTr                        = 520,
-    NPPU_PBU_STAT_MEMID_2_PBU_PPU_IFB_RSP_VLD_CNTr                        = 521,
-    NPPU_PBU_STAT_MEMID_2_ODMA_PBU_RECY_PTR_VLD_CNTr                      = 522,
-    NPPU_PBU_STAT_MEMID_2_PPU_PBU_MCODE_PF_REQ_CNTr                       = 523,
-    NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_RSP_CNTr                       = 524,
-    NPPU_PBU_STAT_MEMID_2_PPU_PBU_LOGIC_PF_REQ_CNTr                       = 525,
-    NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_RSP_CNTr                       = 526,
-    NPPU_PBU_STAT_MEMID_2_PPU_USE_PTR_PULSE_CNTr                          = 527,
-    NPPU_PBU_STAT_MEMID_2_PPU_PBU_WB_VLD_CNTr                             = 528,
-    NPPU_PBU_STAT_MEMID_2_PBU_PPU_REORDER_PARA_VLD_CNTr                   = 529,
-    NPPU_PBU_STAT_MEMID_2_SE_PBU_DPI_KEY_VLD_CNTr                         = 530,
-    NPPU_PBU_STAT_MEMID_2_PBU_SE_DPI_RSP_DATVLD_CNTr                      = 531,
-    NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD1_CNTr                           = 532,
-    NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD2_CNTr                           = 533,
-    NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_NO_RSP_CNTr                    = 534,
-    NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_NO_RSP_CNTr                    = 535,
-    NPPU_PBU_STAT_MEMID_3_CPU_RD_IFB_DATAr                                = 536,
-    NPPU_PBU_STAT_MEMID_4_MUX_SEL_RGTr                                    = 537,
-    NPPU_PBU_STAT_MEMID_5_PORT_PUB_CNTr                                   = 538,
-    NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_PKT_PULSE_TOTAL_CNTr                = 539,
-    NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_EPKT_PULSE_TOTAL_CNTr               = 540,
-    NPPU_IDMA_STAT_MEMID_1_IDMA_DISPKT_PULSE_TOTAL_CNTr                   = 541,
-    NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_PKT_PULSE_CNTr                      = 542,
-    NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_EPKT_PULSE_CNTr                     = 543,
-    NPPU_IDMA_STAT_MEMID_0_IDMA_DISPKT_PULSE_CNTr                         = 544,
-    PPU_PPU_TEST_Rr                                                       = 545,
-    PPU_PPU_PPU_DEBUG_EN_Rr                                               = 546,
-    PPU_PPU_CSR_DUP_TABLE_WR_DATAr                                        = 547,
-    PPU_PPU_CSR_DUP_TABLE_RD_DATAr                                        = 548,
-    PPU_PPU_CSR_DUP_TABLE_ADDRr                                           = 549,
-    PPU_PPU_PPU_DEBUG_VLDr                                                = 550,
-    PPU_PPU_COP_THASH_RSK_319_288r                                        = 551,
-    PPU_PPU_COP_THASH_RSK_287_256r                                        = 552,
-    PPU_PPU_COP_THASH_RSK_255_224r                                        = 553,
-    PPU_PPU_COP_THASH_RSK_223_192r                                        = 554,
-    PPU_PPU_COP_THASH_RSK_191_160r                                        = 555,
-    PPU_PPU_COP_THASH_RSK_159_128r                                        = 556,
-    PPU_PPU_COP_THASH_RSK_127_096r                                        = 557,
-    PPU_PPU_COP_THASH_RSK_095_064r                                        = 558,
-    PPU_PPU_COP_THASH_RSK_063_032r                                        = 559,
-    PPU_PPU_COP_THASH_RSK_031_000r                                        = 560,
-    PPU_PPU_CFG_IPV4_IPID_START_VALUEr                                    = 561,
-    PPU_PPU_CFG_IPV4_IPID_END_VALUEr                                      = 562,
-    PPU_PPU_CLUSTER_MF_IN_ENr                                             = 563,
-    PPU_PPU_PPU_EMPTYr                                                    = 564,
-    PPU_PPU_INSTRMEM_W_ADDRr                                              = 565,
-    PPU_PPU_INSTRMEM_W_DATA_191_160r                                      = 566,
-    PPU_PPU_INSTRMEM_W_DATA_159_128r                                      = 567,
-    PPU_PPU_INSTRMEM_W_DATA_127_96r                                       = 568,
-    PPU_PPU_INSTRMEM_W_DATA_95_64r                                        = 569,
-    PPU_PPU_INSTRMEM_W_DATA_63_32r                                        = 570,
-    PPU_PPU_INSTRMEM_W_DATA_31_0r                                         = 571,
-    PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_ASSERT_CFGr                        = 572,
-    PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_NEGATE_CFGr                        = 573,
-    PPU_CLUSTER_INT_1200M_MASKr                                           = 574,
-    PPU4K_CLUSTER_WR_HIGH_DATA_R_MEXr                                     = 575,
-    PPU4K_CLUSTER_WR_LOW_DATA_R_MEXr                                      = 576,
-    PPU4K_CLUSTER_ADDR_R_MEXr                                             = 577,
-    PPU4K_CLUSTER_SDT_TBL_IND_ACCESS_DONEr                                = 578,
-    PPU4K_CLUSTER_RD_HIGH_DATA_R_MEXr                                     = 579,
-    PPU4K_CLUSTER_RD_LOW_DATA_R_MEXr                                      = 580,
-    SE_ALG_INIT_OKr                                                       = 581,
-    SE_ALG_CPU_RD_RDYr                                                    = 582,
-    SE_ALG_CPU_RD_DATA_TMP0r                                              = 583,
-    SE_ALG_CPU_RD_DATA_TMP1r                                              = 584,
-    SE_ALG_CPU_RD_DATA_TMP2r                                              = 585,
-    SE_ALG_CPU_RD_DATA_TMP3r                                              = 586,
-    SE_ALG_CPU_RD_DATA_TMP4r                                              = 587,
-    SE_ALG_CPU_RD_DATA_TMP5r                                              = 588,
-    SE_ALG_CPU_RD_DATA_TMP6r                                              = 589,
-    SE_ALG_CPU_RD_DATA_TMP7r                                              = 590,
-    SE_ALG_CPU_RD_DATA_TMP8r                                              = 591,
-    SE_ALG_CPU_RD_DATA_TMP9r                                              = 592,
-    SE_ALG_CPU_RD_DATA_TMP10r                                             = 593,
-    SE_ALG_CPU_RD_DATA_TMP11r                                             = 594,
-    SE_ALG_CPU_RD_DATA_TMP12r                                             = 595,
-    SE_ALG_CPU_RD_DATA_TMP13r                                             = 596,
-    SE_ALG_CPU_RD_DATA_TMP14r                                             = 597,
-    SE_ALG_CPU_RD_DATA_TMP15r                                             = 598,
-    SE_ALG_LPM_V4_CONFIG_RGTr                                             = 599,
-    SE_ALG_LPM_V6_CONFIG_RGTr                                             = 600,
-    SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_ASTr                                 = 601,
-    SE_AS_HASH_AGE_PAT_CFGr                                               = 602,
-    SE_AS_LEARN_RDY_CFGr                                                  = 603,
-    SE_KSCHD_KSCHD_AS_PFUL_CFGr                                           = 604,
-    SE_KSCHD_KSCHD_DIR_PFUL_CFGr                                          = 605,
-    SE_KSCHD_KSCHD_AS_EPT_CFGr                                            = 606,
-    SE_KSCHD_CPU_ARBI_PFUL_CFGr                                           = 607,
-    SE_KSCHD_KSCHD_PBU_PFUL_CFGr                                          = 608,
-    SE_RSCHD_RSCHD_DIR_PFUL_CFGr                                          = 609,
-    SE_RSCHD_RSCHD_DIR_EPT_CFGr                                           = 610,
-    SE4K_SE_ALG_CPU_CMD_RGTr                                              = 611,
-    SE4K_SE_ALG_CPU_WR_DATA_TMP0r                                         = 612,
-    SE4K_SE_ALG_CPU_WR_DATA_TMP1r                                         = 613,
-    SE4K_SE_ALG_CPU_WR_DATA_TMP2r                                         = 614,
-    SE4K_SE_ALG_CPU_WR_DATA_TMP3r                                         = 615,
-    SE4K_SE_ALG_CPU_WR_DATA_TMP4r                                         = 616,
-    SE4K_SE_ALG_CPU_WR_DATA_TMP5r                                         = 617,
-    SE4K_SE_ALG_CPU_WR_DATA_TMP6r                                         = 618,
-    SE4K_SE_ALG_CPU_WR_DATA_TMP7r                                         = 619,
-    SE4K_SE_ALG_CPU_WR_DATA_TMP8r                                         = 620,
-    SE4K_SE_ALG_CPU_WR_DATA_TMP9r                                         = 621,
-    SE4K_SE_ALG_CPU_WR_DATA_TMP10r                                        = 622,
-    SE4K_SE_ALG_CPU_WR_DATA_TMP11r                                        = 623,
-    SE4K_SE_ALG_CPU_WR_DATA_TMP12r                                        = 624,
-    SE4K_SE_ALG_CPU_WR_DATA_TMP13r                                        = 625,
-    SE4K_SE_ALG_CPU_WR_DATA_TMP14r                                        = 626,
-    SE4K_SE_ALG_CPU_WR_DATA_TMP15r                                        = 627,
-    SE4K_SE_ALG_CPU_RD_RDYr                                               = 628,
-    SE4K_SE_ALG_CPU_RD_DATA_TMP0r                                         = 629,
-    SE4K_SE_ALG_CPU_RD_DATA_TMP1r                                         = 630,
-    SE4K_SE_ALG_CPU_RD_DATA_TMP2r                                         = 631,
-    SE4K_SE_ALG_CPU_RD_DATA_TMP3r                                         = 632,
-    SE4K_SE_ALG_CPU_RD_DATA_TMP4r                                         = 633,
-    SE4K_SE_ALG_CPU_RD_DATA_TMP5r                                         = 634,
-    SE4K_SE_ALG_CPU_RD_DATA_TMP6r                                         = 635,
-    SE4K_SE_ALG_CPU_RD_DATA_TMP7r                                         = 636,
-    SE4K_SE_ALG_CPU_RD_DATA_TMP8r                                         = 637,
-    SE4K_SE_ALG_CPU_RD_DATA_TMP9r                                         = 638,
-    SE4K_SE_ALG_CPU_RD_DATA_TMP10r                                        = 639,
-    SE4K_SE_ALG_CPU_RD_DATA_TMP11r                                        = 640,
-    SE4K_SE_ALG_CPU_RD_DATA_TMP12r                                        = 641,
-    SE4K_SE_ALG_CPU_RD_DATA_TMP13r                                        = 642,
-    SE4K_SE_ALG_CPU_RD_DATA_TMP14r                                        = 643,
-    SE4K_SE_ALG_CPU_RD_DATA_TMP15r                                        = 644,
-    SE4K_SE_ALG_HASH0_EXT_CFG_RGTr                                        = 645,
-    SE4K_SE_ALG_HASH1_EXT_CFG_RGTr                                        = 646,
-    SE4K_SE_ALG_HASH2_EXT_CFG_RGTr                                        = 647,
-    SE4K_SE_ALG_HASH3_EXT_CFG_RGTr                                        = 648,
-    SE4K_SE_ALG_HASH0_TBL30_DEPTHr                                        = 649,
-    SE4K_SE_ALG_HASH0_TBL74_DEPTHr                                        = 650,
-    SE4K_SE_ALG_HASH1_TBL30_DEPTHr                                        = 651,
-    SE4K_SE_ALG_HASH1_TBL74_DEPTHr                                        = 652,
-    SE4K_SE_ALG_HASH2_TBL30_DEPTHr                                        = 653,
-    SE4K_SE_ALG_HASH2_TBL74_DEPTHr                                        = 654,
-    SE4K_SE_ALG_HASH3_TBL30_DEPTHr                                        = 655,
-    SE4K_SE_ALG_HASH3_TBL74_DEPTHr                                        = 656,
-    SE4K_SE_ALG_WR_RSP_CFGr                                               = 657,
-    SE4K_SE_ALG_HASH_MONO_FLAGr                                           = 658,
-    SE4K_SE_ALG_HASH10_EXT_CRC_CFGr                                       = 659,
-    SE4K_SE_ALG_HASH32_EXT_CRC_CFGr                                       = 660,
-    SE4K_SE_ALG_ZBLOCK_SERVICE_CONFIGUREr                                 = 661,
-    SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONOr                                   = 662,
-    SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONOr                                     = 663,
-    SMMU0_SMMU0_INIT_DONEr                                                = 664,
-    SMMU0_SMMU0_CPU_IND_WDAT0r                                            = 665,
-    SMMU0_SMMU0_CPU_IND_WDAT1r                                            = 666,
-    SMMU0_SMMU0_CPU_IND_WDAT2r                                            = 667,
-    SMMU0_SMMU0_CPU_IND_WDAT3r                                            = 668,
-    SMMU0_SMMU0_CPU_IND_CMDr                                              = 669,
-    SMMU0_SMMU0_CPU_IND_RD_DONEr                                          = 670,
-    SMMU0_SMMU0_CPU_IND_RDAT0r                                            = 671,
-    SMMU0_SMMU0_CPU_IND_RDAT1r                                            = 672,
-    SMMU0_SMMU0_CPU_IND_RDAT2r                                            = 673,
-    SMMU0_SMMU0_CPU_IND_RDAT3r                                            = 674,
-    SMMU0_SMMU0_CFG_PLCR_MONOr                                            = 675,
-    SMMU0_SMMU0_WR_ARB_CPU_RDYr                                           = 676,
-    SMMU0_SMMU0_TM_STAT_EN_CFGr                                           = 677,
-    SE_SMMU1_DDR_WDAT0r                                                   = 678,
-    SE_SMMU1_DIR_ARBI_SER_RPFULr                                          = 679,
-    SE_SMMU1_CFG_WR_ARBI_PFUL2r                                           = 680,
-    SE_SMMU1_ETM_TBL_CFGr                                                 = 681,
-    SE_SMMU1_CFG_CASH_ADDR_PFULr                                          = 682,
-    SE_SMMU1_CTRL_RFIFO_CFGr                                              = 683,
-    SE_SMMU1_CACHE_REQ_FIFO_CFGr                                          = 684,
-    STAT_STAT_CFG_CPU_IND_ERAM_WDAT0r                                     = 685,
-    STAT_STAT_CFG_ETM_PORT_SEL_CFGr                                       = 686,
-    STAT_STAT_CFG_TM_STAT_CFGr                                            = 687,
-    STAT_STAT_CFG_PPU_ERAM_DEPTHr                                         = 688,
-    STAT_STAT_CFG_PPU_ERAM_BASE_ADDRr                                     = 689,
-    STAT_STAT_CFG_PPU_DDR_BASE_ADDRr                                      = 690,
-    STAT_STAT_CFG_PLCR0_BASE_ADDRr                                        = 691,
-    STAT_STAT_CFG_ETM_STAT_START_ADDR_CFGr                                = 692,
-    STAT_STAT_CFG_ETM_STAT_DEPTH_CFGr                                     = 693,
-    STAT_STAT_CFG_CYCLE_MOV_EN_CFGr                                       = 694,
-    STAT_ETCAM_CPU_IND_WDAT0r                                             = 695,
-    STAT_ETCAM_CPU_IND_CTRL_TMP0r                                         = 696,
-    STAT_ETCAM_CPU_IND_CTRL_TMP1r                                         = 697,
-    STAT_ETCAM_CPU_IND_RD_DONEr                                           = 698,
-    STAT_ETCAM_CPU_RDAT0r                                                 = 699,
-    STAT_ETCAM_CPU_RDAT1r                                                 = 700,
-    STAT_ETCAM_CPU_RDAT2r                                                 = 701,
-    STAT_ETCAM_CPU_RDAT3r                                                 = 702,
-    STAT_ETCAM_CPU_RDAT4r                                                 = 703,
-    STAT_ETCAM_CPU_RDAT5r                                                 = 704,
-    STAT_ETCAM_CPU_RDAT6r                                                 = 705,
-    STAT_ETCAM_CPU_RDAT7r                                                 = 706,
-    STAT_ETCAM_CPU_RDAT8r                                                 = 707,
-    STAT_ETCAM_CPU_RDAT9r                                                 = 708,
-    STAT_ETCAM_CPU_RDAT10r                                                = 709,
-    STAT_ETCAM_CPU_RDAT11r                                                = 710,
-    STAT_ETCAM_CPU_RDAT12r                                                = 711,
-    STAT_ETCAM_CPU_RDAT13r                                                = 712,
-    STAT_ETCAM_CPU_RDAT14r                                                = 713,
-    STAT_ETCAM_CPU_RDAT15r                                                = 714,
-    STAT_ETCAM_CPU_RDAT16r                                                = 715,
-    STAT_ETCAM_CPU_RDAT17r                                                = 716,
-    STAT_ETCAM_CPU_RDAT18r                                                = 717,
-    STAT_ETCAM_CPU_RDAT19r                                                = 718,
-    STAT_ETCAM_QVBOr                                                      = 719,
-    STAT_ETCAM_CNT_OVERFLOW_MODEr                                         = 720,
-    STAT_CAR0_CARA_QUEUE_RAM0_159_0r                                      = 721,
-    STAT_CAR0_CARA_PROFILE_RAM1_255_0r                                    = 722,
-    STAT_CAR0_CARA_QOVS_RAM_RAM2r                                         = 723,
-    STAT_CAR0_LOOK_UP_TABLE1r                                             = 724,
-    STAT_CAR0_CARA_PKT_DES_I_CNTr                                         = 725,
-    STAT_CAR0_CARA_GREEN_PKT_I_CNTr                                       = 726,
-    STAT_CAR0_CARA_YELLOW_PKT_I_CNTr                                      = 727,
-    STAT_CAR0_CARA_RED_PKT_I_CNTr                                         = 728,
-    STAT_CAR0_CARA_PKT_DES_O_CNTr                                         = 729,
-    STAT_CAR0_CARA_GREEN_PKT_O_CNTr                                       = 730,
-    STAT_CAR0_CARA_YELLOW_PKT_O_CNTr                                      = 731,
-    STAT_CAR0_CARA_RED_PKT_O_CNTr                                         = 732,
-    STAT_CAR0_CARA_PKT_DES_FC_FOR_CFG_CNTr                                = 733,
-    STAT_CAR0_CARA_APPOINT_QNUM_OR_SPr                                    = 734,
-    STAT_CAR0_CARA_CFGMT_COUNT_MODEr                                      = 735,
-    STAT_CAR0_CARA_PKT_SIZE_CNTr                                          = 736,
-    STAT_CAR0_CARA_PLCR_INIT_DONTr                                        = 737,
-    STAT_CAR0_CARB_QUEUE_RAM0_159_0r                                      = 738,
-    STAT_CAR0_CARB_PROFILE_RAM1_255_0r                                    = 739,
-    STAT_CAR0_CARB_QOVS_RAM_RAM2r                                         = 740,
-    STAT_CAR0_LOOK_UP_TABLE2r                                             = 741,
-    STAT_CAR0_CARB_PKT_DES_I_CNTr                                         = 742,
-    STAT_CAR0_CARB_GREEN_PKT_I_CNTr                                       = 743,
-    STAT_CAR0_CARB_YELLOW_PKT_I_CNTr                                      = 744,
-    STAT_CAR0_CARB_RED_PKT_I_CNTr                                         = 745,
-    STAT_CAR0_CARB_PKT_DES_O_CNTr                                         = 746,
-    STAT_CAR0_CARB_GREEN_PKT_O_CNTr                                       = 747,
-    STAT_CAR0_CARB_YELLOW_PKT_O_CNTr                                      = 748,
-    STAT_CAR0_CARB_RED_PKT_O_CNTr                                         = 749,
-    STAT_CAR0_CARB_PKT_DES_FC_FOR_CFG_CNTr                                = 750,
-    STAT_CAR0_CARB_APPOINT_QNUM_OR_SPr                                    = 751,
-    STAT_CAR0_CARB_CFGMT_COUNT_MODEr                                      = 752,
-    STAT_CAR0_CARB_PKT_SIZE_CNTr                                          = 753,
-    STAT_CAR0_CARB_PLCR_INIT_DONTr                                        = 754,
-    STAT_CAR0_CARC_QUEUE_RAM0_159_0r                                      = 755,
-    STAT_CAR0_CARC_PROFILE_RAM1_255_0r                                    = 756,
-    STAT_CAR0_CARC_QOVS_RAM_RAM2r                                         = 757,
-    STAT_CAR0_CARC_PKT_DES_I_CNTr                                         = 758,
-    STAT_CAR0_CARC_GREEN_PKT_I_CNTr                                       = 759,
-    STAT_CAR0_CARC_YELLOW_PKT_I_CNTr                                      = 760,
-    STAT_CAR0_CARC_RED_PKT_I_CNTr                                         = 761,
-    STAT_CAR0_CARC_PKT_DES_O_CNTr                                         = 762,
-    STAT_CAR0_CARC_GREEN_PKT_O_CNTr                                       = 763,
-    STAT_CAR0_CARC_YELLOW_PKT_O_CNTr                                      = 764,
-    STAT_CAR0_CARC_RED_PKT_O_CNTr                                         = 765,
-    STAT_CAR0_CARC_PKT_DES_FC_FOR_CFG_CNTr                                = 766,
-    STAT_CAR0_CARC_APPOINT_QNUM_OR_SPr                                    = 767,
-    STAT_CAR0_CARC_CFGMT_COUNT_MODEr                                      = 768,
-    STAT_CAR0_CARC_PKT_SIZE_CNTr                                          = 769,
-    STAT_CAR0_CARC_PLCR_INIT_DONTr                                        = 770,
-    STAT_CAR0_CARB_RANDOM_RAMr                                            = 771,
-    STAT_CAR0_CARC_RANDOM_RAMr                                            = 772,
-    STAT_CAR0_CARA_BEGIN_FLOW_IDr                                         = 773,
-    STAT_CAR0_CARB_BEGIN_FLOW_IDr                                         = 774,
-    STAT_CAR0_CARC_BEGIN_FLOW_IDr                                         = 775,
-    STAT_CAR0_PROG_FULL_ASSERT_CFG_Wr                                     = 776,
-    STAT_CAR0_PROG_FULL_NEGATE_CFG_Wr                                     = 777,
-    STAT_CAR0_TIMEOUT_LIMITr                                              = 778,
-    STAT_CAR0_PKT_DES_FIFO_OVERFLOWr                                      = 779,
-    STAT_CAR0_PKT_DES_FIFO_UNDERFLOWr                                     = 780,
-    STAT_CAR0_PKT_DES_FIFO_PROG_FULLr                                     = 781,
-    STAT_CAR0_PKT_DES_FIFO_PROG_EMPTYr                                    = 782,
-    STAT_CAR0_PKT_DES_FIFO_FULLr                                          = 783,
-    STAT_CAR0_PKT_DES_FIFO_EMPTYr                                         = 784,
-    STAT_CAR0_PKT_SIZE_OFFSETr                                            = 785,
-    STAT_CAR0_CAR_PLCR_INIT_DONTr                                         = 786,
-    STAT_CAR0_MAX_PKT_SIZE_Ar                                             = 787,
-    STAT_CAR0_MAX_PKT_SIZE_Br                                             = 788,
-    STAT_CAR0_MAX_PKT_SIZE_Cr                                             = 789,
-    STAT_CAR0_CAR_HIERARCHY_MODEr                                         = 790,
-    STAT_CAR0_PROG_EMPTY_ASSERT_CFG_Wr                                    = 791,
-    STAT_CAR0_PROG_EMPTY_NEGATE_CFG_Wr                                    = 792,
-    STAT_CAR0_PKT_DES_FIFO_OVF_INTr                                       = 793,
-    STAT_CAR0_PKT_DES_FIFO_DATA_COUNTr                                    = 794,
-    STAT_CAR0_PKT_DES_FIFO_UDF_INTr                                       = 795,
-    STAT_CAR0_CARA_QUEUE_RAM0_159_0_PKTr                                  = 796,
-    STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKTr                                = 797,
-    STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFGr                                    = 798,
-    STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFGr                                  = 799,
-    STAT4K_ETCAM_BLOCK4_7_BASE_ADDR_CFGr                                  = 800,
-    DTB_DTB_CFG_CFG_ERAM_WR_INTERVAL_CNTr                                 = 801,
-    DTB_DTB_CFG_CFG_ZCAM_WR_INTERVAL_CNTr                                 = 802,
-    DTB_DTB_CFG_CFG_TCAM_WR_INTERVAL_CNTr                                 = 803,
-    DTB_DTB_CFG_CFG_DDR_WR_INTERVAL_CNTr                                  = 804,
-    DTB_DTB_CFG_CFG_HASH_WR_INTERVAL_CNTr                                 = 805,
-    DTB_DTB_CFG_CFG_ERAM_RD_INTERVAL_CNTr                                 = 806,
-    DTB_DTB_CFG_CFG_ZCAM_RD_INTERVAL_CNTr                                 = 807,
-    DTB_DTB_CFG_CFG_TCAM_RD_INTERVAL_CNTr                                 = 808,
-    DTB_DTB_CFG_CFG_DDR_RD_INTERVAL_CNTr                                  = 809,
-    DTB_DTB_CFG_CFG_DTB_QUEUE_LOCK_STATE_0_3r                             = 810,
-    DTB_DTB_AXIM0_W_CONVERT_0_MODEr                                       = 811,
-    DTB_DTB_AXIM0_R_CONVERT_0_MODEr                                       = 812,
-    DTB_DTB_AXIM0_AXIMR_OSr                                               = 813,
-    DTB_DTB_AXIM1_W_CONVERT_1_MODEr                                       = 814,
-    DTB_DTB_AXIM1_R_CONVERT_1_MODEr                                       = 815,
-    DTB_DTB_AXIS_AXIS_CONVERT_MODEr                                       = 816,
-    DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_H_0_127r                             = 817,
-    DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_L_0_127r                             = 818,
-    DTB4K_DTB_ENQ_CFG_QUEUE_DTB_LEN_0_127r                                = 819,
-    DTB4K_DTB_ENQ_INFO_QUEUE_BUF_SPACE_LEFT_0_127r                        = 820,
-    DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127r                              = 821,
-    TRPG_TRPG_RX_PORT_CPU_TRPG_MS_ENr                                     = 822,
-    TRPG_TRPG_RX_PORT_CPU_TRPG_PORT_ENr                                   = 823,
-    TRPG_TRPG_RX_PORT_CPU_TRPG_LOOK_ENr                                   = 824,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_ALMOST_FULLr                         = 825,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_TEST_ENr                             = 826,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_INMOD_PFC_RDY_ENr                        = 827,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_Hr                               = 828,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_Lr                               = 829,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_Hr                          = 830,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_Lr                          = 831,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_CNT_CLRr                             = 832,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_CLK_FREQr                             = 833,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_ENr                                   = 834,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_ADD_NUMr                        = 835,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_MAX_NUMr                        = 836,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_PORT_STATE_INFOr                         = 837,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEPr                        = 838,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEP_CLRr                    = 839,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LENr                        = 840,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LEN_CLRr                    = 841,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LENr                        = 842,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LEN_CLRr                    = 843,
-    TRPG_TRPG_RX_RAM_TRPG_RX_DATA_RAMr                                    = 844,
-    TRPG_TRPG_RX_RAM_TRPG_RX_INFO_RAMr                                    = 845,
-    TRPG_TRPG_TX_PORT_CPU_TRPG_MS_ENr                                     = 846,
-    TRPG_TRPG_TX_PORT_CPU_TRPG_PORT_ENr                                   = 847,
-    TRPG_TRPG_TX_PORT_CPU_TRPG_LOOK_ENr                                   = 848,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_ALMOST_FULLr                         = 849,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_TEST_ENr                             = 850,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_Hr                               = 851,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_Lr                               = 852,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_Hr                          = 853,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_Lr                          = 854,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_CNT_CLRr                             = 855,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_CLK_FREQr                             = 856,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_ENr                                   = 857,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_ADD_NUMr                        = 858,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_MAX_NUMr                        = 859,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_PORT_STATE_INFOr                         = 860,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEPr                        = 861,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEP_CLRr                    = 862,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LENr                        = 863,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LEN_CLRr                    = 864,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LENr                        = 865,
-    TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LEN_CLRr                    = 866,
-    TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_ALMOST_FULLr                 = 867,
-    TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_TEST_ENr                     = 868,
-    TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_MASKr                         = 869,
-    TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_CLRr                          = 870,
-    TRPG_TRPG_TX_GLB_CPU_TODTIME_RAM_TEST_ENr                             = 871,
-    TRPG_TRPG_TX_RAM_TRPG_TX_DATA_RAMr                                    = 872,
-    TRPG_TRPG_TX_RAM_TRPG_TX_INFO_RAMr                                    = 873,
-    TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_DATA_RAMr                            = 874,
-    TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_INFO_RAMr                            = 875,
-    ETM_CFGMT_CHIP_VERSION_REGr                                           = 876,
-    ETM_CFGMT_CHIP_DATE_REGr                                              = 877,
-    ETM_CFGMT_CFGMT_CRC_ENr                                               = 878,
-    ETM_CFGMT_CFG_PORT_TRANSFER_ENr                                       = 879,
-    ETM_CFGMT_TM_SA_WORK_MODEr                                            = 880,
-    ETM_CFGMT_LOCAL_SA_IDr                                                = 881,
-    ETM_OLIF_OLIF_RDYr                                                    = 882,
-    ETM_OLIF_EMEM_PROG_FULLr                                              = 883,
-    ETM_OLIF_PORT_ORDER_FIFO_FULLr                                        = 884,
-    ETM_OLIF_OLIF_RELEASE_LASTr                                           = 885,
-    ETM_OLIF_OLIF_FIFO_EMPTY_STATEr                                       = 886,
-    ETM_OLIF_QMU_OLIF_RELEASE_FC_CNTr                                     = 887,
-    ETM_OLIF_OLIF_QMU_LINK_FC_CNTr                                        = 888,
-    ETM_OLIF_LIF0_LINK_FC_CNTr                                            = 889,
-    ETM_OLIF_OLIF_TMMU_FC_CNTr                                            = 890,
-    ETM_OLIF_OLIF_MMU_FC_CNTr                                             = 891,
-    ETM_OLIF_OLIF_QMU_PORT_RDY_Hr                                         = 892,
-    ETM_OLIF_OLIF_QMU_PORT_RDY_Lr                                         = 893,
-    ETM_OLIF_LIF0_PORT_RDY_Hr                                             = 894,
-    ETM_OLIF_LIF0_PORT_RDY_Lr                                             = 895,
-    ETM_OLIF_QMU_OLIF_RD_SOP_CNTr                                         = 896,
-    ETM_OLIF_QMU_OLIF_RD_EOP_CNTr                                         = 897,
-    ETM_OLIF_QMU_OLIF_RD_VLD_CNTr                                         = 898,
-    ETM_OLIF_QMU_OLIF_RD_BLK_CNTr                                         = 899,
-    ETM_OLIF_MMU_TM_DATA_SOP_CNTr                                         = 900,
-    ETM_OLIF_MMU_TM_DATA_EOP_CNTr                                         = 901,
-    ETM_OLIF_MMU_TM_DATA_VLD_CNTr                                         = 902,
-    ETM_OLIF_ODMA_TM_DATA_SOP_CNTr                                        = 903,
-    ETM_OLIF_ODMA_TM_DATA_EOP_CNTr                                        = 904,
-    ETM_OLIF_ODMA_TM_DEQ_VLD_CNTr                                         = 905,
-    ETM_OLIF_OLIF_QMU_RELEASE_VLD_CNTr                                    = 906,
-    ETM_OLIF_EMEM_DAT_VLD_CNTr                                            = 907,
-    ETM_OLIF_IMEM_DAT_VLD_CNTr                                            = 908,
-    ETM_OLIF_EMEM_DAT_RD_CNTr                                             = 909,
-    ETM_OLIF_IMEM_DAT_RD_CNTr                                             = 910,
-    ETM_OLIF_QMU_OLIF_RD_SOP_EMEM_CNTr                                    = 911,
-    ETM_OLIF_QMU_OLIF_RD_VLD_EMEM_CNTr                                    = 912,
-    ETM_OLIF_CPU_LAST_WR_ADDRr                                            = 913,
-    ETM_OLIF_CPU_LAST_WR_DATAr                                            = 914,
-    ETM_OLIF_CPU_LAST_RD_ADDRr                                            = 915,
-    ETM_OLIF_QMU_OLIF_LAST_PORTr                                          = 916,
-    ETM_OLIF_QMU_OLIF_LAST_ADDRr                                          = 917,
-    ETM_OLIF_QMU_OLIF_LAST_BANKr                                          = 918,
-    ETM_OLIF_TM_LIF_BYTE_STATr                                            = 919,
-    ETM_OLIF_TM_LIF_ERR_STATr                                             = 920,
-    ETM_CGAVD_PORT_SHARE_CNTr                                             = 921,
-    ETM_CGAVD_TOTAL_IMEM_CNTr                                             = 922,
-    ETM_CGAVD_PP_Q_LENr                                                   = 923,
-    ETM_CGAVD_SYS_Q_LENr                                                  = 924,
-    ETM_CGAVD_CGAVD_CFG_ERROR_WARNINGr                                    = 925,
-    ETM_CGAVD_MULT_QLEN_TH_ENr                                            = 926,
-    ETM_CGAVD_MULT_QLEN_THr                                               = 927,
-    ETM_CGAVD_CGAVD_CFG_MOVEr                                             = 928,
-    ETM_CGAVD_CFGMT_TOTAL_THr                                             = 929,
-    ETM_CGAVD_CFGMT_PORT_SHARE_THr                                        = 930,
-    ETM_CGAVD_SA_UNREACH_STATEr                                           = 931,
-    ETM_CGAVD_MV_PORT_THr                                                 = 932,
-    ETM_CGAVD_MV_DROP_SP_THr                                              = 933,
-    ETM_CGAVD_CGAVD_STATE_WARNINGr                                        = 934,
-    ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNTr                                    = 935,
-    ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNT_MAXr                                = 936,
-    ETM_CGAVD_IMEM_TOTAL_CNTr                                             = 937,
-    ETM_CGAVD_IMEM_TOTAL_CNT_MAXr                                         = 938,
-    ETM_CGAVD_FLOW0_OMEM_CNTr                                             = 939,
-    ETM_CGAVD_FLOW1_OMEM_CNTr                                             = 940,
-    ETM_CGAVD_FLOW2_OMEM_CNTr                                             = 941,
-    ETM_CGAVD_FLOW3_OMEM_CNTr                                             = 942,
-    ETM_CGAVD_FLOW4_OMEM_CNTr                                             = 943,
-    ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_1r                                 = 944,
-    ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_2r                                 = 945,
-    ETM_CGAVD_ODMA_CGAVD_PKT_NUM_1r                                       = 946,
-    ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_1r                                      = 947,
-    ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_1r                                    = 948,
-    ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_1r                                    = 949,
-    ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_1r                                   = 950,
-    ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_1r                                   = 951,
-    ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_1r                                  = 952,
-    ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_1r                                  = 953,
-    ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_1r                                   = 954,
-    ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_1r                                  = 955,
-    ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_1r                                = 956,
-    ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_1r                               = 957,
-    ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_1r                             = 958,
-    ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_1r                          = 959,
-    ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_1r                                      = 960,
-    ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_1r                               = 961,
-    ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_1r                            = 962,
-    ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_1r                                = 963,
-    ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_1r                              = 964,
-    ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM1r                            = 965,
-    ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_1r                                    = 966,
-    ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_1r                                  = 967,
-    ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_1r                               = 968,
-    ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_1r                              = 969,
-    ETM_CGAVD_ODMA_CGAVD_PKT_NUM_2r                                       = 970,
-    ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_2r                                      = 971,
-    ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_2r                                    = 972,
-    ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_2r                                    = 973,
-    ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_2r                                   = 974,
-    ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_2r                                   = 975,
-    ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_2r                                  = 976,
-    ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_2r                                  = 977,
-    ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_2r                                   = 978,
-    ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_2r                                  = 979,
-    ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_2r                                = 980,
-    ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_2r                               = 981,
-    ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_2r                             = 982,
-    ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_2r                          = 983,
-    ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_2r                                      = 984,
-    ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_2r                               = 985,
-    ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_2r                            = 986,
-    ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_2r                                = 987,
-    ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_2r                              = 988,
-    ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM_2r                           = 989,
-    ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_2r                                    = 990,
-    ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_2r                                  = 991,
-    ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_2r                               = 992,
-    ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_2r                              = 993,
-    ETM_CGAVD_MOVE_FLOW_TH_PROFILEr                                       = 994,
-    ETM_CGAVD_MOVE_FLOW_THr                                               = 995,
-    ETM_TMMU_EMEM_PD_FIFO_AFUL_THr                                        = 996,
-    ETM_TMMU_DMA_DATA_FIFO_AFUL_THr                                       = 997,
-    ETM_TMMU_TMMU_STATES_0r                                               = 998,
-    ETM_TMMU_QMU_TMMU_WR_SOP_CNTr                                         = 999,
-    ETM_TMMU_QMU_TMMU_WR_EOP_CNTr                                         = 1000,
-    ETM_TMMU_QMU_TMMU_WR_DROP_CNTr                                        = 1001,
-    ETM_TMMU_QMU_TMMU_WR_EMEM_CNTr                                        = 1002,
-    ETM_TMMU_QMU_TMMU_WR_IMEM_CNTr                                        = 1003,
-    ETM_TMMU_TMMU_MMU_WR_SOP_CNTr                                         = 1004,
-    ETM_TMMU_TMMU_MMU_WR_EOP_CNTr                                         = 1005,
-    ETM_TMMU_QMU_TMMU_RD_SOP_CNTr                                         = 1006,
-    ETM_TMMU_QMU_TMMU_RD_EOP_CNTr                                         = 1007,
-    ETM_TMMU_QMU_TMMU_RD_DROP_CNTr                                        = 1008,
-    ETM_TMMU_QMU_TMMU_RD_EMEM_CNTr                                        = 1009,
-    ETM_TMMU_QMU_TMMU_RD_IMEM_CNTr                                        = 1010,
-    ETM_TMMU_TMMU_MMU_RD_SOP_CNTr                                         = 1011,
-    ETM_TMMU_TMMU_MMU_RD_EOP_CNTr                                         = 1012,
-    ETM_TMMU_TMMU_ODMA_IN_SOP_CNTr                                        = 1013,
-    ETM_TMMU_TMMU_ODMA_IN_EOP_CNTr                                        = 1014,
-    ETM_TMMU_TMMU_ODMA_VLD_CNTr                                           = 1015,
-    ETM_TMMU_QMU_PD_IN_CNTr                                               = 1016,
-    ETM_TMMU_TMMU_PD_HIT_CNTr                                             = 1017,
-    ETM_TMMU_TMMU_PD_OUT_CNTr                                             = 1018,
-    ETM_TMMU_TMMU_WR_CMD_FIFO_WR_CNTr                                     = 1019,
-    ETM_TMMU_TMMU_IMEM_AGE_CNTr                                           = 1020,
-    ETM_TMMU_TMMU_CMDSCH_RD_CNTr                                          = 1021,
-    ETM_TMMU_TMMU_CMDSCH_DROP_CNTr                                        = 1022,
-    ETM_TMMU_TMMU_CMDSW_DROP_CNTr                                         = 1023,
-    ETM_TMMU_TMMU_ODMA_ENQ_RD_CNTr                                        = 1024,
-    ETM_TMMU_TMMU_ODMA_ENQ_DROP_CNTr                                      = 1025,
-    ETM_TMMU_TMMU_ODMA_IMEM_AGE_CNTr                                      = 1026,
-    ETM_TMMU_TMMU_ODMA_DEQ_RD_CNTr                                        = 1027,
-    ETM_TMMU_TMMU_ODMA_DEQ_DROP_CNTr                                      = 1028,
-    ETM_TMMU_OLIF_TMMU_XOFF_CNTr                                          = 1029,
-    ETM_TMMU_ODMA_TM_DATA_XOFF_CNTr                                       = 1030,
-    ETM_TMMU_TM_ODMA_PKT_XOFF_CNTr                                        = 1031,
-    ETM_TMMU_TM_STATE_3r                                                  = 1032,
-    ETM_TMMU_CFGMT_PD_CACHE_CMDr                                          = 1033,
-    ETM_TMMU_CFGMT_PD_CACHE_RD_DONEr                                      = 1034,
-    ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_0r                                    = 1035,
-    ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_1r                                    = 1036,
-    ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_2r                                    = 1037,
-    ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_3r                                    = 1038,
-    ETM_TMMU_CFGMT_TMMU_TO_ODMA_PARAr                                     = 1039,
-    ETM_TMMU_CFGMT_DMA_DATA_FIFO_CNTr                                     = 1040,
-    ETM_TMMU_CFGMT_CACHE_TAG_BIT0_OFFSETr                                 = 1041,
-    ETM_TMMU_CFGMT_CACHE_TAG_BIT1_OFFSETr                                 = 1042,
-    ETM_TMMU_CFGMT_CACHE_TAG_BIT2_OFFSETr                                 = 1043,
-    ETM_TMMU_CFGMT_CACHE_TAG_BIT3_OFFSETr                                 = 1044,
-    ETM_TMMU_CFGMT_CACHE_TAG_BIT4_OFFSETr                                 = 1045,
-    ETM_TMMU_CFGMT_CACHE_TAG_BIT5_OFFSETr                                 = 1046,
-    ETM_TMMU_CFGMT_CACHE_INDEX_BIT0_OFFSETr                               = 1047,
-    ETM_TMMU_CFGMT_CACHE_INDEX_BIT1_OFFSETr                               = 1048,
-    ETM_TMMU_CFGMT_CACHE_INDEX_BIT2_OFFSETr                               = 1049,
-    ETM_TMMU_CFGMT_CACHE_INDEX_BIT3_OFFSETr                               = 1050,
-    ETM_TMMU_CFGMT_CACHE_INDEX_BIT4_OFFSETr                               = 1051,
-    ETM_TMMU_CFGMT_CACHE_INDEX_BIT5_OFFSETr                               = 1052,
-    ETM_TMMU_CFGMT_CACHE_INDEX_BIT6_OFFSETr                               = 1053,
-    ETM_TMMU_CFGMT_CACHE_INDEX_BIT7_OFFSETr                               = 1054,
-    ETM_TMMU_CFGMT_CACHE_INDEX_BIT8_OFFSETr                               = 1055,
-    ETM_TMMU_CFGMT_CACHE_INDEX_BIT9_OFFSETr                               = 1056,
-    ETM_TMMU_CFGMT_CACHE_INDEX_BIT10_OFFSETr                              = 1057,
-    ETM_TMMU_CFGMT_CACHE_INDEX_BIT11_OFFSETr                              = 1058,
-    ETM_TMMU_CFGMT_CACHE_INDEX_BIT12_OFFSETr                              = 1059,
-    ETM_SHAP_BKTFULL_FIFO_FULL_FLAGREGISTERr                              = 1060,
-    ETM_SHAP_FIFO_FULL_REGREGISTERr                                       = 1061,
-    ETM_SHAP_FIFO_EMPTY_REGREGISTERr                                      = 1062,
-    ETM_SHAP_FIFO_ALMOST_FULL_REGREGISTERr                                = 1063,
-    ETM_SHAP_FIFO_ALMOST_EMPTY_REGREGISTERr                               = 1064,
-    ETM_CRDT_CREDIT_SPACE_SELECTr                                         = 1065,
-    ETM_CRDT_STAT_SPACE_MAXr                                              = 1066,
-    ETM_CRDT_STAT_SPACE_MINr                                              = 1067,
-    ETM_CRDT_STAT_SPACE_CREDITr                                           = 1068,
-    ETM_CRDT_STAT_QUE_STEP8_CREDITr                                       = 1069,
-    ETM_CRDT_SPECIAL_QUEr                                                 = 1070,
-    ETM_CRDT_SPECIAL_QUE_CREDITr                                          = 1071,
-    ETM_CRDT_LIF_CONGEST_CREDIT_CNTr                                      = 1072,
-    ETM_CRDT_LIF_PORT_CONGEST_CREDIT_CNTr                                 = 1073,
-    ETM_CRDT_CRDT_CONGEST_CREDIT_CNTr                                     = 1074,
-    ETM_CRDT_CRDT_PORT_CONGEST_CREDIT_CNTr                                = 1075,
-    ETM_CRDT_CONGEST_PORT_IDr                                             = 1076,
-    ETM_CRDT_DEV_LINK_CONTROLr                                            = 1077,
-    ETM_CRDT_CRDT_SA_PORT_RDYr                                            = 1078,
-    ETM_CRDT_CRDT_CONGEST_MODE_SELECTr                                    = 1079,
-    ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNTr                                 = 1080,
-    ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNTr                                    = 1081,
-    ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNTr                                 = 1082,
-    ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNTr                                    = 1083,
-    ETM_CRDT_MODE_ADD_60Gr                                                = 1084,
-    ETM_CRDT_PP_TOKEN_ADDr                                                = 1085,
-    ETM_CRDT_PP_CIR_TOKEN_TOTAL_DIST_CNTr                                 = 1086,
-    ETM_CRDT_PP_CIR_TOKEN_TOTAL_DEC_CNTr                                  = 1087,
-    ETM_CRDT_DEV_CREDIT_CNTr                                              = 1088,
-    ETM_CRDT_NO_CREDIT_CNT1r                                              = 1089,
-    ETM_CRDT_NO_CREDIT_CNT2r                                              = 1090,
-    ETM_CRDT_ASM_INTERVAL_0_CFGr                                          = 1091,
-    ETM_CRDT_ASM_INTERVAL_1_CFGr                                          = 1092,
-    ETM_CRDT_ASM_INTERVAL_2_CFGr                                          = 1093,
-    ETM_CRDT_ASM_INTERVAL_3_CFGr                                          = 1094,
-    ETM_CRDT_ASM_INTERVAL_4_CFGr                                          = 1095,
-    ETM_CRDT_ASM_INTERVAL_5CFGr                                           = 1096,
-    ETM_CRDT_ASM_INTERVAL_6_CFGr                                          = 1097,
-    ETM_CRDT_ASM_INTERVAL_7_CFGr                                          = 1098,
-    ETM_CRDT_CRDT_TOTAL_CONGEST_MODE_CFGr                                 = 1099,
-    ETM_CRDT_RCI_FIFO_INI_DEEP_CFGr                                       = 1100,
-    ETM_CRDT_CRDT_ECCr                                                    = 1101,
-    ETM_CRDT_UCN_ASM_RDY_SHIELD_ENr                                       = 1102,
-    ETM_CRDT_UCN_ASM_RDYr                                                 = 1103,
-    ETM_CRDT_RCI_GRADEr                                                   = 1104,
-    ETM_CRDT_CRDT_RCI_VALUE_Rr                                            = 1105,
-    ETM_CRDT_CRDT_INTERVAL_NOWr                                           = 1106,
-    ETM_CRDT_CRS_SHEILD_FLOW_ID_CFGr                                      = 1107,
-    ETM_CRDT_CRS_SHEILD_EN_CFGr                                           = 1108,
-    ETM_CRDT_CRS_SHEILD_VALUE_CFGr                                        = 1109,
-    ETM_CRDT_TEST_TOKEN_CALC_CTRLr                                        = 1110,
-    ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUMr                                 = 1111,
-    ETM_CRDT_Q_STATE_0_7r                                                 = 1112,
-    ETM_CRDT_Q_STATE_8_15r                                                = 1113,
-    ETM_QMU_CSW_CSCH_RD_CMD_CNTr                                          = 1114,
-    ETM_QMU_CSW_CSCH_RD_SOP_CNTr                                          = 1115,
-    ETM_QMU_CSW_CSCH_RD_EOP_CNTr                                          = 1116,
-    ETM_QMU_CSW_CSCH_RD_DROP_CNTr                                         = 1117,
-    ETM_QMU_CSCH_MMU_RD_CMD_CNTr                                          = 1118,
-    ETM_QMU_CSCH_MMU_RD_SOP_CNTr                                          = 1119,
-    ETM_QMU_CSCH_MMU_RD_EOP_CNTr                                          = 1120,
-    ETM_QMU_CSCH_MMU_RD_DROP_CNTr                                         = 1121,
-    ETM_QMU_QCFG_QSCH_CRS_FILTERr                                         = 1122,
-    ETM_QMU_QCFG_QSCH_CRS_FORCE_ENr                                       = 1123,
-    ETM_QMU_QCFG_QSCH_CRS_FORCE_QNUMr                                     = 1124,
-    ETM_QMU_QCFG_QSCH_CRS_FORCE_CRSr                                      = 1125,
-    ETM_QMU_CFGMT_OSHP_SGMII_SHAP_MODEr                                   = 1126,
-    ETM_QMU_CFGMT_QMU_SASHAP_ENr                                          = 1127,
-    ETM_QMU_CFGMT_SASHAP_TOKEN_MAXr                                       = 1128,
-    ETM_QMU_CFGMT_SASHAP_TOKEN_MINr                                       = 1129,
-    ETM_QMU_CFG_QSCH_Q3LBADDRATEr                                         = 1130,
-    ETM_QMU_CFG_QSCH_Q012LBADDRATEr                                       = 1131,
-    ETM_QMU_CFG_QSCH_Q3CREDITLBMAXCNTr                                    = 1132,
-    ETM_QMU_CFG_QSCH_Q012CREDITLBMAXCNTr                                  = 1133,
-    ETM_QMU_CFG_QSCH_MUL_TOKEN_GEN_NUMr                                   = 1134,
-    ETM_QMU_CFG_QSCH_Q3_CREDIT_LB_CONTROL_ENr                             = 1135,
-    ETM_QMU_CFG_QSCH_Q012_CREDIT_LB_CONTROL_ENr                           = 1136,
-    ETM_QMU_CFG_QSCH_SP_DWRR_ENr                                          = 1137,
-    ETM_QMU_CFG_QSCH_Q01_ATTACH_ENr                                       = 1138,
-    ETM_QMU_CFG_QSCH_W0r                                                  = 1139,
-    ETM_QMU_CFG_QSCH_W1r                                                  = 1140,
-    ETM_QMU_CFG_QSCH_W2r                                                  = 1141,
-    ETM_QMU_CFG_QSCH_LKYBKTMAXCNT1r                                       = 1142,
-    ETM_QMU_CFG_QSCH_LKYBKTMAXCNT2r                                       = 1143,
-    ETM_QMU_CFG_QSCH_LKYBKTDCRRATE1r                                      = 1144,
-    ETM_QMU_CFG_QSCH_LKYBKTDCRRATE2r                                      = 1145,
-    ETM_QMU_CFG_QSCH_LKYBKTDCRRATE3r                                      = 1146,
-    ETM_QMU_CFG_QSCH_LKYBKTMAXCNT3r                                       = 1147,
-    ETM_QMU_CFG_QSCH_QMU_MUL_AUTO_SA_VERSIONr                             = 1148,
-    ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0r                                   = 1149,
-    ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_1r                                   = 1150,
-    ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_2r                                   = 1151,
-    ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_3r                                   = 1152,
-    ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_4r                                   = 1153,
-    ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_5r                                   = 1154,
-    ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_6r                                   = 1155,
-    ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_7r                                   = 1156,
-    ETM_QMU_CFG_QSCH_REMOTE_CREDIT_FIFO_ALMOST_FULL_THr                   = 1157,
-    ETM_QMU_CFG_QSCH_AUTO_CREDIT_FIFO_ALMOST_FULL_THr                     = 1158,
-    ETM_QMU_CFG_QSCH_Q3_CREDIT_FIFO_ALMOST_FULL_THr                       = 1159,
-    ETM_QMU_CFG_QSCH_Q012_CREDIT_FIFO_ALMOST_FULL_THr                     = 1160,
-    ETM_QMU_CFG_QSCH_MUL_FC_RES_ENr                                       = 1161,
-    ETM_QMU_CFGMT_MUL_OVF_UDF_FLG_QUERYr                                  = 1162,
-    ETM_QMU_CFGMT_MUL_CNG_FLG_QUERYr                                      = 1163,
-    ETM_QMU_QSCH_CFG_LKYBKTVAL1r                                          = 1164,
-    ETM_QMU_QSCH_CFG_LKYBKTVAL2r                                          = 1165,
-    ETM_QMU_QSCH_CFG_LKYBKTVAL3r                                          = 1166,
-    ETM_QMU_QSCH_CFG_Q3LBVALr                                             = 1167,
-    ETM_QMU_QSCH_CFG_Q012LBVALr                                           = 1168,
-    ETM_QMU_QLIST_CFGMT_RAM_ECC_ERR2r                                     = 1169,
-    ETM_QMU_CSCH_AGED_CMD_CNTr                                            = 1170,
-    ETM_QMU_CSCH_QCFG_CSCH_CONGEST_CNTr                                   = 1171,
-    ETM_QMU_CSCH_QCFG_QLIST_CSCH_SOP_CNTr                                 = 1172,
-    ETM_QMU_CSCH_QCFG_QLIST_CSCH_EOP_CNTr                                 = 1173,
-    ETM_QMU_CSCH_QCFG_CSCH_CSW_SOP_CNTr                                   = 1174,
-    ETM_QMU_CSCH_QCFG_CSCH_CSW_EOP_CNTr                                   = 1175,
-    ETM_QMU_CSCH_QCFG_QLIST_CSCH_DROP_CNTr                                = 1176,
-    ETM_QMU_CSCH_QCFG_CSCH_CSW_DROP_CNTr                                  = 1177,
-    ETM_QMU_CSW_MMU_SOP_CMD_CNTr                                          = 1178,
-    ETM_QMU_MMU_CSW_SOP_DATA_CNTr                                         = 1179,
-    ETM_QMU_CSW_QSCH_FEEDB_CNTr                                           = 1180,
-    ETM_QMU_QMU_CRDT_PORT_FC_CNTr                                         = 1181,
-    ETM_QMU_CSCH_R_BLOCK_CNTr                                             = 1182,
-    ETM_QMU_QCFG_QLIST_QDS_HEAD_RDr                                       = 1183,
-    ETM_QMU_QCFG_QLIST_QDS_TAIL_RDr                                       = 1184,
-    ETM_QMU_QCFG_QLIST_EPT_RDr                                            = 1185,
-    ETM_QMU_QCFG_QLIST_AGE_FLAG_RDr                                       = 1186,
-    ETM_QMU_QCFG_QLIST_CTI_RDr                                            = 1187,
-    ETM_QMU_QCFG_QLIST_CTO_RDr                                            = 1188,
-    ETM_QMU_QCFG_QLIST_CHK_RDr                                            = 1189,
-    ETM_QMU_QCFG_QLIST_NOD_RDr                                            = 1190,
-    ETM_QMU_QCFG_QLIST_BIU_RDr                                            = 1191,
-    ETM_QMU_QSCH_R_WLIST_FLAGr                                            = 1192,
-    ETM_QMU_QCFG_CRS_FLG_RDr                                              = 1193,
-    ETM_QMU_CFGMT_QMU_IMEM_AGE_QDSr                                       = 1194,
-    ETM_QMU_CFGMT_QMU_IMEM_AGE_QLENr                                      = 1195,
-    ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_LOWr                                    = 1196,
-    ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_HIGHr                                   = 1197,
-    ETM_QMU_CFGMT_QMU_IMEM_UP_PTRr                                        = 1198,
-    ETM_QMU_CFGMT_QMU_IMEM_DOWN_PTRr                                      = 1199,
-    ETM_QMU_CFGMT_QMU_IMEM_AGE_FLAGr                                      = 1200,
-    ETM_QMU_CFG_QSCH_LKYBKT2CNGTHr                                        = 1201,
-    ETM_QMU_CFG_QSCH_LKYBKT1CNGTHr                                        = 1202,
-    ETM_QMU_CFG_QSCH_LKYBKT3CNGTHr                                        = 1203,
-    ETM_QMU_CFG_QSCH_RM_MUL_MCN1_CREDIT_VALUEr                            = 1204,
-    ETM_QMU_CFG_QSCH_RM_MUL_MCN2_CREDIT_VALUEr                            = 1205,
-    ETM_QMU_CFG_QSCH_RM_MUL_MCN3_CREDIT_VALUEr                            = 1206,
-    ETM_QMU_RM_MUL_MCN1_RAND_ANSR_SEEDr                                   = 1207,
-    ETM_QMU_RM_MUL_MCN2_RAND_ANSR_SEEDr                                   = 1208,
-    ETM_QMU_RM_MUL_MCN3_RAND_ANSR_SEEDr                                   = 1209,
-    ETM_QMU_RM_MUL_MCN1_RAND_ANSR_THr                                     = 1210,
-    ETM_QMU_RM_MUL_MCN2_RAND_ANSR_THr                                     = 1211,
-    ETM_QMU_RM_MUL_MCN3_RAND_ANSR_THr                                     = 1212,
-    ETM_QMU_RM_MUL_MCN1_RAND_HOLD_BASEr                                   = 1213,
-    ETM_QMU_RM_MUL_MCN2_RAND_HOLD_BASEr                                   = 1214,
-    ETM_QMU_RM_MUL_MCN3_RAND_HOLD_BASEr                                   = 1215,
-    ETM_QMU_RM_MUL_MCN1_RAND_SEL_MASKr                                    = 1216,
-    ETM_QMU_RM_MUL_MCN2_RAND_SEL_MASKr                                    = 1217,
-    ETM_QMU_RM_MUL_MCN3_RAND_SEL_MASKr                                    = 1218,
-    ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG0r                               = 1219,
-    ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG1r                               = 1220,
-    ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG0r                               = 1221,
-    ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG1r                               = 1222,
-    ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG0r                               = 1223,
-    ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG1r                               = 1224,
-    ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH1r                                    = 1225,
-    ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH2r                                    = 1226,
-    ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH3r                                    = 1227,
-    ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH4r                                    = 1228,
-    ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH5r                                    = 1229,
-    ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH6r                                    = 1230,
-    ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH7r                                    = 1231,
-    ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH1r                                    = 1232,
-    ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH2r                                    = 1233,
-    ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH3r                                    = 1234,
-    ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH4r                                    = 1235,
-    ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH5r                                    = 1236,
-    ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH6r                                    = 1237,
-    ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH7r                                    = 1238,
-    ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH1r                                    = 1239,
-    ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH2r                                    = 1240,
-    ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH3r                                    = 1241,
-    ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH4r                                    = 1242,
-    ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH5r                                    = 1243,
-    ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH6r                                    = 1244,
-    ETM_QMU_RM_MUL_MCN3STEP_WAIT_TH7r                                     = 1245,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE0r                                      = 1246,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE1r                                      = 1247,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE2r                                      = 1248,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE3r                                      = 1249,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE4r                                      = 1250,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE5r                                      = 1251,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE6r                                      = 1252,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE7r                                      = 1253,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE8r                                      = 1254,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE9r                                      = 1255,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE10r                                     = 1256,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE11r                                     = 1257,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE12r                                     = 1258,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE13r                                     = 1259,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE14r                                     = 1260,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE15r                                     = 1261,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE16r                                     = 1262,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE17r                                     = 1263,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE18r                                     = 1264,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE19r                                     = 1265,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE20r                                     = 1266,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE21r                                     = 1267,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE22r                                     = 1268,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE23r                                     = 1269,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE24r                                     = 1270,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE25r                                     = 1271,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE26r                                     = 1272,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE27r                                     = 1273,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE28r                                     = 1274,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE29r                                     = 1275,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE30r                                     = 1276,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE31r                                     = 1277,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE32r                                     = 1278,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE33r                                     = 1279,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE34r                                     = 1280,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE35r                                     = 1281,
-    ETM_QMU_CFG_QSCH_MULCRDCNTRATE36r                                     = 1282,
-    ETM_QMU_CFG_QSCH_RM_MUL_MCN1_RAND_HOLD_SHIFTr                         = 1283,
-    ETM_QMU_CFG_QSCH_RM_MUL_MCN2_RAND_HOLD_SHIFTr                         = 1284,
-    ETM_QMU_CFG_QSCH_RM_MUL_MCN3_RAND_HOLD_SHIFTr                         = 1285,
-    ETM_QMU_LAST_DROP_QNUM_GETr                                           = 1286,
-    ETM_QMU_CRDT_QMU_CREDIT_CNTr                                          = 1287,
-    ETM_QMU_QMU_TO_QSCH_REPORT_CNTr                                       = 1288,
-    ETM_QMU_QMU_TO_CGAVD_REPORT_CNTr                                      = 1289,
-    ETM_QMU_QMU_CRDT_CRS_NORMAL_CNTr                                      = 1290,
-    ETM_QMU_QMU_CRDT_CRS_OFF_CNTr                                         = 1291,
-    ETM_QMU_QSCH_QLIST_SHEDULE_CNTr                                       = 1292,
-    ETM_QMU_QSCH_QLIST_SCH_EPT_CNTr                                       = 1293,
-    ETM_QMU_QMU_TO_MMU_BLK_WR_CNTr                                        = 1294,
-    ETM_QMU_QMU_TO_CSW_BLK_RD_CNTr                                        = 1295,
-    ETM_QMU_QMU_TO_MMU_SOP_WR_CNTr                                        = 1296,
-    ETM_QMU_QMU_TO_MMU_EOP_WR_CNTr                                        = 1297,
-    ETM_QMU_QMU_TO_MMU_DROP_WR_CNTr                                       = 1298,
-    ETM_QMU_QMU_TO_CSW_SOP_RD_CNTr                                        = 1299,
-    ETM_QMU_QMU_TO_CSW_EOP_RD_CNTr                                        = 1300,
-    ETM_QMU_QMU_TO_CSW_DROP_RD_CNTr                                       = 1301,
-    ETM_QMU_MMU_TO_QMU_WR_RELEASE_CNTr                                    = 1302,
-    ETM_QMU_MMU_TO_QMU_RD_RELEASE_CNTr                                    = 1303,
-    ETM_QMU_OBSERVE_QNUM_SETr                                             = 1304,
-    ETM_QMU_SPEC_Q_PKT_RECEIVEDr                                          = 1305,
-    ETM_QMU_SPEC_Q_PKT_DROPPEDr                                           = 1306,
-    ETM_QMU_SPEC_Q_PKT_SCHEDULEDr                                         = 1307,
-    ETM_QMU_SPEC_Q_WR_CMD_SENTr                                           = 1308,
-    ETM_QMU_SPEC_Q_RD_CMD_SENTr                                           = 1309,
-    ETM_QMU_SPEC_Q_PKT_ENQr                                               = 1310,
-    ETM_QMU_SPEC_Q_PKT_DEQr                                               = 1311,
-    ETM_QMU_SPEC_Q_CRDT_UNCON_RECEIVEDr                                   = 1312,
-    ETM_QMU_SPEC_Q_CRDT_CONG_RECEIVEDr                                    = 1313,
-    ETM_QMU_SPEC_Q_CRS_NORMAL_CNTr                                        = 1314,
-    ETM_QMU_SPEC_Q_CRS_OFF_CNTr                                           = 1315,
-    ETM_QMU_OBSERVE_BATCH_SETr                                            = 1316,
-    ETM_QMU_SPEC_BAT_PKT_RECEIVEDr                                        = 1317,
-    ETM_QMU_SPEC_BAT_PKT_DROPPEDr                                         = 1318,
-    ETM_QMU_SPEC_BAT_BLK_SCHEDULEDr                                       = 1319,
-    ETM_QMU_SPEC_BAT_WR_CMD_SENTr                                         = 1320,
-    ETM_QMU_SPEC_BAT_RD_CMD_SENTr                                         = 1321,
-    ETM_QMU_SPEC_BAT_PKT_ENQr                                             = 1322,
-    ETM_QMU_SPEC_BAT_PKT_DEQr                                             = 1323,
-    ETM_QMU_SPEC_BAT_CRDT_UNCON_RECEIVEDr                                 = 1324,
-    ETM_QMU_SPEC_BAT_CRDT_CONG_RECEIVEDr                                  = 1325,
-    ETM_QMU_SPEC_BAT_CRS_NORMAL_CNTr                                      = 1326,
-    ETM_QMU_SPEC_BAT_CRS_OFF_CNTr                                         = 1327,
-    ETM_QMU_BCNTM_OVFL_QNUM_GETr                                          = 1328,
-    ETM_QMU_CRBAL_A_OVF_QNUM_GETr                                         = 1329,
-    ETM_QMU_CRBAL_B_OVF_QNUM_GETr                                         = 1330,
-    ETM_QMU_CRBAL_DROP_QNUM_GETr                                          = 1331,
-    ETM_QMU_DEQ_FLG_REPORT_CNTr                                           = 1332,
-    ETM_QMU_SPEC_Q_CRS_GETr                                               = 1333,
-    ETM_QMU_SPEC_Q_CRS_IN_GETr                                            = 1334,
-    ETM_QMU_SPEC_Q_CRS_FLG_CSOL_GETr                                      = 1335,
-    ETM_QMU_EPT_SCH_QNUM_GETr                                             = 1336,
-    CFG_PCIE_PCIE_DDR_SWITCHr                                             = 1337,
-    CFG_PCIE_USER0_INT_ENr                                                = 1338,
-    CFG_PCIE_USER0_INT_MASKr                                              = 1339,
-    CFG_PCIE_USER0_INT_STATUSr                                            = 1340,
-    CFG_PCIE_USER1_INT_ENr                                                = 1341,
-    CFG_PCIE_USER1_INT_MASKr                                              = 1342,
-    CFG_PCIE_USER1_INT_STATUSr                                            = 1343,
-    CFG_PCIE_USER2_INT_ENr                                                = 1344,
-    CFG_PCIE_USER2_INT_MASKr                                              = 1345,
-    CFG_PCIE_USER2_INT_STATUSr                                            = 1346,
-    CFG_PCIE_ECC_1B_INT_ENr                                               = 1347,
-    CFG_PCIE_ECC_1B_INT_MASKr                                             = 1348,
-    CFG_PCIE_ECC_1B_INT_STATUSr                                           = 1349,
-    CFG_PCIE_ECC_2B_INT_ENr                                               = 1350,
-    CFG_PCIE_ECC_2B_INT_MASKr                                             = 1351,
-    CFG_PCIE_ECC_2B_INT_STATUSr                                           = 1352,
-    CFG_PCIE_CFG_INT_STATUSr                                              = 1353,
-    CFG_PCIE_I_CORE_TO_CNTLr                                              = 1354,
-    CFG_PCIE_TEST_IN_LOWr                                                 = 1355,
-    CFG_PCIE_TEST_IN_HIGHr                                                = 1356,
-    CFG_PCIE_LOCAL_INTERRUPT_OUTr                                         = 1357,
-    CFG_PCIE_PL_LTSSMr                                                    = 1358,
-    CFG_PCIE_TEST_OUT0r                                                   = 1359,
-    CFG_PCIE_TEST_OUT1r                                                   = 1360,
-    CFG_PCIE_TEST_OUT2r                                                   = 1361,
-    CFG_PCIE_TEST_OUT3r                                                   = 1362,
-    CFG_PCIE_TEST_OUT4r                                                   = 1363,
-    CFG_PCIE_TEST_OUT5r                                                   = 1364,
-    CFG_PCIE_TEST_OUT6r                                                   = 1365,
-    CFG_PCIE_TEST_OUT7r                                                   = 1366,
-    CFG_PCIE_SYNC_O_CORE_STATUSr                                          = 1367,
-    CFG_PCIE_SYNC_O_ALERT_DBEr                                            = 1368,
-    CFG_PCIE_SYNC_O_ALERT_SBEr                                            = 1369,
-    CFG_PCIE_SYNC_O_LINK_LOOPBACK_ENr                                     = 1370,
-    CFG_PCIE_SYNC_O_LOCAL_FS_LF_VALIDr                                    = 1371,
-    CFG_PCIE_SYNC_O_RX_IDLE_DETECTr                                       = 1372,
-    CFG_PCIE_SYNC_O_RX_RDYr                                               = 1373,
-    CFG_PCIE_SYNC_O_TX_RDYr                                               = 1374,
-    CFG_PCIE_PCIE_LINK_UP_CNTr                                            = 1375,
-    CFG_PCIE_TEST_OUT_PCIE0r                                              = 1376,
-    CFG_PCIE_TEST_OUT_PCIE1r                                              = 1377,
-    CFG_PCIE_TEST_OUT_PCIE2r                                              = 1378,
-    CFG_PCIE_TEST_OUT_PCIE3r                                              = 1379,
-    CFG_PCIE_TEST_OUT_PCIE4r                                              = 1380,
-    CFG_PCIE_TEST_OUT_PCIE5r                                              = 1381,
-    CFG_PCIE_TEST_OUT_PCIE6r                                              = 1382,
-    CFG_PCIE_TEST_OUT_PCIE7r                                              = 1383,
-    CFG_PCIE_TEST_OUT_PCIE8r                                              = 1384,
-    CFG_PCIE_TEST_OUT_PCIE9r                                              = 1385,
-    CFG_PCIE_TEST_OUT_PCIE10r                                             = 1386,
-    CFG_PCIE_TEST_OUT_PCIE11r                                             = 1387,
-    CFG_PCIE_TEST_OUT_PCIE12r                                             = 1388,
-    CFG_PCIE_TEST_OUT_PCIE13r                                             = 1389,
-    CFG_PCIE_TEST_OUT_PCIE14r                                             = 1390,
-    CFG_PCIE_TEST_OUT_PCIE15r                                             = 1391,
-    CFG_PCIE_INT_REPEAT_ENr                                               = 1392,
-    CFG_PCIE_DBG_AWID_AXI_MSTr                                            = 1393,
-    CFG_PCIE_DBG_AWADDR_AXI_MST0r                                         = 1394,
-    CFG_PCIE_DBG_AWADDR_AXI_MST1r                                         = 1395,
-    CFG_PCIE_DBG_AWLEN_AXI_MSTr                                           = 1396,
-    CFG_PCIE_DBG_AWSIZE_AXI_MSTr                                          = 1397,
-    CFG_PCIE_DBG_AWBURST_AXI_MSTr                                         = 1398,
-    CFG_PCIE_DBG_AWLOCK_AXI_MSTr                                          = 1399,
-    CFG_PCIE_DBG_AWCACHE_AXI_MSTr                                         = 1400,
-    CFG_PCIE_DBG_AWPROT_AXI_MSTr                                          = 1401,
-    CFG_PCIE_DBG_WID_AXI_MSTr                                             = 1402,
-    CFG_PCIE_DBG_WDATA_AXI_MST0r                                          = 1403,
-    CFG_PCIE_DBG_WDATA_AXI_MST1r                                          = 1404,
-    CFG_PCIE_DBG_WDATA_AXI_MST2r                                          = 1405,
-    CFG_PCIE_DBG_WDATA_AXI_MST3r                                          = 1406,
-    CFG_PCIE_DBG_WSTRB_AXI_MSTr                                           = 1407,
-    CFG_PCIE_DBG_WLAST_AXI_MSTr                                           = 1408,
-    CFG_PCIE_DBG_ARID_AXI_MSTr                                            = 1409,
-    CFG_PCIE_DBG_ARADDR_AXI_MST0r                                         = 1410,
-    CFG_PCIE_DBG_ARADDR_AXI_MST1r                                         = 1411,
-    CFG_PCIE_DBG_ARLEN_AXI_MSTr                                           = 1412,
-    CFG_PCIE_DBG_ARSIZE_AXI_MSTr                                          = 1413,
-    CFG_PCIE_DBG_ARBURST_AXI_MSTr                                         = 1414,
-    CFG_PCIE_DBG_ARLOCK_AXI_MSTr                                          = 1415,
-    CFG_PCIE_DBG_ARCACHE_AXI_MSTr                                         = 1416,
-    CFG_PCIE_DBG_ARPROT_AXI_MSTr                                          = 1417,
-    CFG_PCIE_DBG_RDATA_AXI_MST0r                                          = 1418,
-    CFG_PCIE_DBG_RDATA_AXI_MST1r                                          = 1419,
-    CFG_PCIE_DBG_RDATA_AXI_MST2r                                          = 1420,
-    CFG_PCIE_DBG_RDATA_AXI_MST3r                                          = 1421,
-    CFG_PCIE_AXI_MST_STATEr                                               = 1422,
-    CFG_PCIE_AXI_CFG_STATEr                                               = 1423,
-    CFG_PCIE_AXI_SLV_RD_STATEr                                            = 1424,
-    CFG_PCIE_AXI_SLV_WR_STATEr                                            = 1425,
-    CFG_PCIE_AXIM_DELAY_ENr                                               = 1426,
-    CFG_PCIE_AXIM_DELAYr                                                  = 1427,
-    CFG_PCIE_AXIM_SPEED_WRr                                               = 1428,
-    CFG_PCIE_AXIM_SPEED_RDr                                               = 1429,
-    CFG_PCIE_DBG_AWADDR_AXI_SLV0r                                         = 1430,
-    CFG_PCIE_DBG_AWADDR_AXI_SLV1r                                         = 1431,
-    CFG_PCIE_DBG0_WDATA_AXI_SLV0r                                         = 1432,
-    CFG_PCIE_DBG0_WDATA_AXI_SLV1r                                         = 1433,
-    CFG_PCIE_DBG0_WDATA_AXI_SLV2r                                         = 1434,
-    CFG_PCIE_DBG0_WDATA_AXI_SLV3r                                         = 1435,
-    CFG_PCIE_DBG1_WDATA_AXI_SLV0r                                         = 1436,
-    CFG_PCIE_DBG1_WDATA_AXI_SLV1r                                         = 1437,
-    CFG_PCIE_DBG1_WDATA_AXI_SLV2r                                         = 1438,
-    CFG_PCIE_DBG1_WDATA_AXI_SLV3r                                         = 1439,
-    CFG_PCIE_DBG2_WDATA_AXI_SLV0r                                         = 1440,
-    CFG_PCIE_DBG2_WDATA_AXI_SLV1r                                         = 1441,
-    CFG_PCIE_DBG2_WDATA_AXI_SLV2r                                         = 1442,
-    CFG_PCIE_DBG2_WDATA_AXI_SLV3r                                         = 1443,
-    CFG_PCIE_DBG3_WDATA_AXI_SLV0r                                         = 1444,
-    CFG_PCIE_DBG3_WDATA_AXI_SLV1r                                         = 1445,
-    CFG_PCIE_DBG3_WDATA_AXI_SLV2r                                         = 1446,
-    CFG_PCIE_DBG3_WDATA_AXI_SLV3r                                         = 1447,
-    CFG_PCIE_DBG4_WDATA_AXI_SLV0r                                         = 1448,
-    CFG_PCIE_DBG4_WDATA_AXI_SLV1r                                         = 1449,
-    CFG_PCIE_DBG4_WDATA_AXI_SLV2r                                         = 1450,
-    CFG_PCIE_DBG4_WDATA_AXI_SLV3r                                         = 1451,
-    CFG_PCIE_DBG5_WDATA_AXI_SLV0r                                         = 1452,
-    CFG_PCIE_DBG5_WDATA_AXI_SLV1r                                         = 1453,
-    CFG_PCIE_DBG5_WDATA_AXI_SLV2r                                         = 1454,
-    CFG_PCIE_DBG5_WDATA_AXI_SLV3r                                         = 1455,
-    CFG_PCIE_DBG6_WDATA_AXI_SLV0r                                         = 1456,
-    CFG_PCIE_DBG6_WDATA_AXI_SLV1r                                         = 1457,
-    CFG_PCIE_DBG6_WDATA_AXI_SLV2r                                         = 1458,
-    CFG_PCIE_DBG6_WDATA_AXI_SLV3r                                         = 1459,
-    CFG_PCIE_DBG7_WDATA_AXI_SLV0r                                         = 1460,
-    CFG_PCIE_DBG7_WDATA_AXI_SLV1r                                         = 1461,
-    CFG_PCIE_DBG7_WDATA_AXI_SLV2r                                         = 1462,
-    CFG_PCIE_DBG7_WDATA_AXI_SLV3r                                         = 1463,
-    CFG_PCIE_DBG8_WDATA_AXI_SLV0r                                         = 1464,
-    CFG_PCIE_DBG8_WDATA_AXI_SLV1r                                         = 1465,
-    CFG_PCIE_DBG8_WDATA_AXI_SLV2r                                         = 1466,
-    CFG_PCIE_DBG8_WDATA_AXI_SLV3r                                         = 1467,
-    CFG_PCIE_DBG9_WDATA_AXI_SLV0r                                         = 1468,
-    CFG_PCIE_DBG9_WDATA_AXI_SLV1r                                         = 1469,
-    CFG_PCIE_DBG9_WDATA_AXI_SLV2r                                         = 1470,
-    CFG_PCIE_DBG9_WDATA_AXI_SLV3r                                         = 1471,
-    CFG_PCIE_DBG_AWLEN_AXI_SLVr                                           = 1472,
-    CFG_PCIE_DBG_WLAST_AXI_SLVr                                           = 1473,
-    CFG_PCIE_DBG_ARADDR_AXI_SLV0r                                         = 1474,
-    CFG_PCIE_DBG_ARADDR_AXI_SLV1r                                         = 1475,
-    CFG_PCIE_DBG0_RDATA_AXI_SLV0r                                         = 1476,
-    CFG_PCIE_DBG0_RDATA_AXI_SLV1r                                         = 1477,
-    CFG_PCIE_DBG0_RDATA_AXI_SLV2r                                         = 1478,
-    CFG_PCIE_DBG0_RDATA_AXI_SLV3r                                         = 1479,
-    CFG_PCIE_DBG1_RDATA_AXI_SLV0r                                         = 1480,
-    CFG_PCIE_DBG1_RDATA_AXI_SLV1r                                         = 1481,
-    CFG_PCIE_DBG1_RDATA_AXI_SLV2r                                         = 1482,
-    CFG_PCIE_DBG1_RDATA_AXI_SLV3r                                         = 1483,
-    CFG_PCIE_DBG_RLAST_AXI_SLVr                                           = 1484,
-    CFG_DMA_DMA_ENABLEr                                                   = 1485,
-    CFG_DMA_UP_REQr                                                       = 1486,
-    CFG_DMA_DMA_UP_CURRENT_STATEr                                         = 1487,
-    CFG_DMA_DMA_UP_REQ_ACKr                                               = 1488,
-    CFG_DMA_DMA_DONE_LATCHr                                               = 1489,
-    CFG_DMA_DMA_UP_CPU_ADDR_LOW32r                                        = 1490,
-    CFG_DMA_DMA_UP_CPU_ADDR_HIGH32r                                       = 1491,
-    CFG_DMA_DMA_UP_SE_ADDRr                                               = 1492,
-    CFG_DMA_DMA_DONE_INTr                                                 = 1493,
-    CFG_DMA_SP_CFGr                                                       = 1494,
-    CFG_DMA_DMA_INGr                                                      = 1495,
-    CFG_DMA_RD_TIMEOUT_THRESHr                                            = 1496,
-    CFG_DMA_DMA_TAB_STA_UP_FIFO_GAPr                                      = 1497,
-    CFG_DMA_CFG_MAC_TIMr                                                  = 1498,
-    CFG_DMA_CFG_MAC_NUMr                                                  = 1499,
-    CFG_DMA_INIT_BD_ADDRr                                                 = 1500,
-    CFG_DMA_MAC_UP_BD_ADDR1_LOW32r                                        = 1501,
-    CFG_DMA_MAC_UP_BD_ADDR1_HIGH32r                                       = 1502,
-    CFG_DMA_MAC_UP_BD_ADDR2_LOW32r                                        = 1503,
-    CFG_DMA_MAC_UP_BD_ADDR2_HIGH32r                                       = 1504,
-    CFG_DMA_CFG_MAC_MAX_NUMr                                              = 1505,
-    CFG_DMA_DMA_WBUF_FF_EMPTYr                                            = 1506,
-    CFG_DMA_DMA_WBUF_STATEr                                               = 1507,
-    CFG_DMA_DMA_MAC_BD_ADDR_LOW32r                                        = 1508,
-    CFG_DMA_DMA_MAC_BD_ADDR_HIGH32r                                       = 1509,
-    CFG_DMA_MAC_UP_ENABLEr                                                = 1510,
-    CFG_DMA_MAC_ENDIANr                                                   = 1511,
-    CFG_DMA_UP_ENDIANr                                                    = 1512,
-    CFG_DMA_DMA_UP_RD_CNT_LATCHr                                          = 1513,
-    CFG_DMA_DMA_UP_RCV_CNT_LATCHr                                         = 1514,
-    CFG_DMA_DMA_UP_CNT_LATCHr                                             = 1515,
-    CFG_DMA_CPU_RD_BD_PULSEr                                              = 1516,
-    CFG_DMA_CPU_BD_THRESHOLDr                                             = 1517,
-    CFG_DMA_CPU_BD_USED_CNTr                                              = 1518,
-    CFG_DMA_DMA_UP_RCV_STATUSr                                            = 1519,
-    CFG_DMA_SLV_RID_ERR_ENr                                               = 1520,
-    CFG_DMA_SLV_RRESP_ERR_ENr                                             = 1521,
-    CFG_DMA_SE_RDBK_FF_FULLr                                              = 1522,
-    CFG_DMA_DMA_UP_DATA_COUNTr                                            = 1523,
-    CFG_DMA_DMA_MWR_FIFO_AFULL_GAPr                                       = 1524,
-    CFG_DMA_DMA_INFO_FIFO_AFULL_GAPr                                      = 1525,
-    CFG_DMA_DMA_RD_TIMEOUT_SETr                                           = 1526,
-    CFG_DMA_DMA_BD_DAT_ERR_ENr                                            = 1527,
-    CFG_DMA_DMA_REPEAT_CNTr                                               = 1528,
-    CFG_DMA_DMA_RD_TIMEOUT_ENr                                            = 1529,
-    CFG_DMA_DMA_REPEAT_READr                                              = 1530,
-    CFG_DMA_DMA_REPEAT_READ_ENr                                           = 1531,
-    CFG_DMA_BD_CTL_STATEr                                                 = 1532,
-    CFG_DMA_DMA_DONE_INT_CNT_WRr                                          = 1533,
-    CFG_DMA_DMA_DONE_INT_CNT_MACr                                         = 1534,
-    CFG_DMA_CURRENT_MAC_NUMr                                              = 1535,
-    CFG_DMA_CFG_MAC_AFIFO_AFULLr                                          = 1536,
-    CFG_DMA_DMA_MAC_FF_FULLr                                              = 1537,
-    CFG_DMA_USER_AXI_MSTr                                                 = 1538,
-    CFG_CSR_SBUS_STATEr                                                   = 1539,
-    CFG_CSR_MST_DEBUG_ENr                                                 = 1540,
-    CFG_CSR_SBUS_COMMAND_SELr                                             = 1541,
-    CFG_CSR_SOC_RD_TIME_OUT_THRESHr                                       = 1542,
-    CFG_CSR_BIG_LITTLE_BYTE_ORDERr                                        = 1543,
-    CFG_CSR_ECC_BYPASS_READr                                              = 1544,
-    CFG_CSR_AHB_ASYNC_WR_FIFO_AFULL_GAPr                                  = 1545,
-    CFG_CSR_AHB_ASYNC_RD_FIFO_AFULL_GAPr                                  = 1546,
-    CFG_CSR_AHB_ASYNC_CPL_FIFO_AFULL_GAPr                                 = 1547,
-    CFG_CSR_MST_DEBUG_DATA0_HIGH26r                                       = 1548,
-    CFG_CSR_MST_DEBUG_DATA0_LOW32r                                        = 1549,
-    CFG_CSR_MST_DEBUG_DATA1_HIGH26r                                       = 1550,
-    CFG_CSR_MST_DEBUG_DATA1_LOW32r                                        = 1551,
-    CFG_CSR_MST_DEBUG_DATA2_HIGH26r                                       = 1552,
-    CFG_CSR_MST_DEBUG_DATA2_LOW32r                                        = 1553,
-    CFG_CSR_MST_DEBUG_DATA3_HIGH26r                                       = 1554,
-    CFG_CSR_MST_DEBUG_DATA3_LOW32r                                        = 1555,
-    CFG_CSR_MST_DEBUG_DATA4_HIGH26r                                       = 1556,
-    CFG_CSR_MST_DEBUG_DATA4_LOW32r                                        = 1557,
-    CFG_CSR_MST_DEBUG_DATA5_HIGH26r                                       = 1558,
-    CFG_CSR_MST_DEBUG_DATA5_LOW32r                                        = 1559,
-    CFG_CSR_MST_DEBUG_DATA6_HIGH26r                                       = 1560,
-    CFG_CSR_MST_DEBUG_DATA6_LOW32r                                        = 1561,
-    CFG_CSR_MST_DEBUG_DATA7_HIGH26r                                       = 1562,
-    CFG_CSR_MST_DEBUG_DATA7_LOW32r                                        = 1563,
-    CFG_CSR_MST_DEBUG_DATA8_HIGH26r                                       = 1564,
-    CFG_CSR_MST_DEBUG_DATA8_LOW32r                                        = 1565,
-    CFG_CSR_MST_DEBUG_DATA9_HIGH26r                                       = 1566,
-    CFG_CSR_MST_DEBUG_DATA9_LOW32r                                        = 1567,
-    CFG_CSR_MST_DEBUG_DATA10_HIGH26r                                      = 1568,
-    CFG_CSR_MST_DEBUG_DATA10_LOW32r                                       = 1569,
-    CFG_CSR_MST_DEBUG_DATA11_HIGH26r                                      = 1570,
-    CFG_CSR_MST_DEBUG_DATA11_LOW32r                                       = 1571,
-    CFG_CSR_MST_DEBUG_DATA12_HIGH26r                                      = 1572,
-    CFG_CSR_MST_DEBUG_DATA12_LOW32r                                       = 1573,
-    CFG_CSR_MST_DEBUG_DATA13_HIGH26r                                      = 1574,
-    CFG_CSR_MST_DEBUG_DATA13_LOW32r                                       = 1575,
-    CFG_CSR_MST_DEBUG_DATA14_HIGH26r                                      = 1576,
-    CFG_CSR_MST_DEBUG_DATA14_LOW32r                                       = 1577,
-    CFG_CSR_MST_DEBUG_DATA15_HIGH26r                                      = 1578,
-    CFG_CSR_MST_DEBUG_DATA15_LOW32r                                       = 1579,
-    NPPU_MR_CFG_IND_ACCESS_STATESr                                        = 1580,
-    NPPU_MR_CFG_IND_ACCESS_CMD0r                                          = 1581,
-    NPPU_MR_CFG_IND_ACCESS_DATA0r                                         = 1582,
-    NPPU_MR_CFG_IND_ACCESS_DATA1r                                         = 1583,
-    NPPU_MR_CFG_IND_ACCESS_CMD1r                                          = 1584,
-    NPPU_MR_CFG_MR_INIT_DONEr                                             = 1585,
-    NPPU_MR_CFG_CNT_MODE_REGr                                             = 1586,
-    NPPU_MR_CFG_CFG_ECC_BYPASS_READr                                      = 1587,
-    NPPU_MR_CFG_CFG_REP_MODr                                              = 1588,
-    NPPU_MR_CFG_BLOCK_PTR_FIFO_AFUL_THr                                   = 1589,
-    NPPU_MR_CFG_PRE_RCV_PTR_FIFO_AFUL_THr                                 = 1590,
-    NPPU_MR_CFG_MGID_FIFO_AFUL_THr                                        = 1591,
-    NPPU_MR_CFG_REP_CMD_FIFO_AFUL_THr                                     = 1592,
-    NPPU_MR_CFG_MR_INT_MASK_1r                                            = 1593,
-    NPPU_MR_CFG_MR_INT_MASK_2r                                            = 1594,
-    NPPU_MR_CFG_MR_INT_MASK_3r                                            = 1595,
-    NPPU_MR_CFG_MR_INT_MASK_4r                                            = 1596,
-    NPPU_MR_CFG_MR_STATES_1r                                              = 1597,
-    NPPU_MR_CFG_MR_STATES_2r                                              = 1598,
-    NPPU_MR_CFG_MR_STATES_3r                                              = 1599,
-    NPPU_MR_CFG_MR_STATES_4r                                              = 1600,
-    NPPU_MR_CFG_MR_STATES_5r                                              = 1601,
-    NPPU_MR_CFG_MR_STATES_6r                                              = 1602,
-    NPPU_MR_CFG_MR_STATES_7r                                              = 1603,
-    NPPU_MR_CFG_MR_STATES_8r                                              = 1604,
-    NPPU_MR_CFG_MR_SOP_IN_CNTr                                            = 1605,
-    NPPU_MR_CFG_MR_EOP_IN_CNTr                                            = 1606,
-    NPPU_MR_CFG_MR_SOP_OUT_CNTr                                           = 1607,
-    NPPU_MR_CFG_MR_EOP_OUT_CNTr                                           = 1608,
-    NPPU_MR_CFG_MR_COS0_IN_CNTr                                           = 1609,
-    NPPU_MR_CFG_MR_COS1_IN_CNTr                                           = 1610,
-    NPPU_MR_CFG_MR_COS2_IN_CNTr                                           = 1611,
-    NPPU_MR_CFG_MR_COS3_IN_CNTr                                           = 1612,
-    NPPU_MR_CFG_MR_COS0_OUT_CNTr                                          = 1613,
-    NPPU_MR_CFG_MR_COS1_OUT_CNTr                                          = 1614,
-    NPPU_MR_CFG_MR_COS2_OUT_CNTr                                          = 1615,
-    NPPU_MR_CFG_MR_COS3_OUT_CNTr                                          = 1616,
-    NPPU_MR_CFG_MR_ERR_IN_CNTr                                            = 1617,
-    NPPU_MR_CFG_MR_COS0_SOP_IN_CNTr                                       = 1618,
-    NPPU_MR_CFG_MR_COS0_EOP_IN_CNTr                                       = 1619,
-    NPPU_MR_CFG_MR_COS1_SOP_IN_CNTr                                       = 1620,
-    NPPU_MR_CFG_MR_COS1_EOP_IN_CNTr                                       = 1621,
-    NPPU_MR_CFG_MR_COS2_SOP_IN_CNTr                                       = 1622,
-    NPPU_MR_CFG_MR_COS2_EOP_IN_CNTr                                       = 1623,
-    NPPU_MR_CFG_MR_COS3_SOP_IN_CNTr                                       = 1624,
-    NPPU_MR_CFG_MR_COS3_EOP_IN_CNTr                                       = 1625,
-    NPPU_MR_CFG_MR_COS0_IN_ERR_CNTr                                       = 1626,
-    NPPU_MR_CFG_MR_COS1_IN_ERR_CNTr                                       = 1627,
-    NPPU_MR_CFG_MR_COS2_IN_ERR_CNTr                                       = 1628,
-    NPPU_MR_CFG_MR_COS3_IN_ERR_CNTr                                       = 1629,
-    NPPU_MR_CFG_MR_COS0_SOP_OUT_CNTr                                      = 1630,
-    NPPU_MR_CFG_MR_COS0_EOP_OUT_CNTr                                      = 1631,
-    NPPU_MR_CFG_MR_COS1_SOP_OUT_CNTr                                      = 1632,
-    NPPU_MR_CFG_MR_COS1_EOP_OUT_CNTr                                      = 1633,
-    NPPU_MR_CFG_MR_COS2_SOP_OUT_CNTr                                      = 1634,
-    NPPU_MR_CFG_MR_COS2_EOP_OUT_CNTr                                      = 1635,
-    NPPU_MR_CFG_MR_COS3_SOP_OUT_CNTr                                      = 1636,
-    NPPU_MR_CFG_MR_COS3_EOP_OUT_CNTr                                      = 1637,
-    NPPU_MR_CFG_MR_MLT_UNVLD_CNTr                                         = 1638,
-    NPPU_MR_CFG_MR_SOP_EOP_MATCH_CFGr                                     = 1639,
-    NPPU_MR_CFG_MR_MLT_UNVLD_MGIDr                                        = 1640,
-    NPPU_PKTRX_CFG_ISCH_FIFO_TH_1r                                        = 1641,
-    NPPU_PKTRX_CFG_ISCH_FIFO_TH_2r                                        = 1642,
-    NPPU_PKTRX_CFG_ISCH_FIFO_TH_3r                                        = 1643,
-    NPPU_PKTRX_CFG_ISCH_FIFO_TH_4r                                        = 1644,
-    NPPU_PKTRX_CFG_ISCH_CFG_0r                                            = 1645,
-    NPPU_PKTRX_CFG_HDU_EX_TPID_0r                                         = 1646,
-    NPPU_PKTRX_CFG_HDU_EX_TPID_1r                                         = 1647,
-    NPPU_PKTRX_CFG_HDU_INT_TPID_0r                                        = 1648,
-    NPPU_PKTRX_CFG_HDU_INT_TPID_1r                                        = 1649,
-    NPPU_PKTRX_CFG_HDU_HDLC_0r                                            = 1650,
-    NPPU_PKTRX_CFG_HDU_HDLC_1r                                            = 1651,
-    NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_0r                                      = 1652,
-    NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_1r                                      = 1653,
-    NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_2r                                      = 1654,
-    NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_3r                                      = 1655,
-    NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_0r                                      = 1656,
-    NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_1r                                      = 1657,
-    NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_2r                                      = 1658,
-    NPPU_PKTRX_CFG_SLOT_NO_CFGr                                           = 1659,
-    NPPU_PKTRX_CFG_PKTRX_INT_EN_0r                                        = 1660,
-    NPPU_PKTRX_CFG_PKTRX_INT_EN_1r                                        = 1661,
-    NPPU_PKTRX_CFG_PKTRX_INT_MASK_0r                                      = 1662,
-    NPPU_PKTRX_CFG_PKTRX_INT_MASK_1r                                      = 1663,
-    NPPU_PKTRX_CFG_PKTRX_INT_STATUSr                                      = 1664,
-    NPPU_PKTRX_CFG_PKTRX_PORT_RDY0r                                       = 1665,
-    NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY0r                                   = 1666,
-    NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY1r                                   = 1667,
-    NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY2r                                   = 1668,
-    NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY3r                                   = 1669,
-    NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY4r                                   = 1670,
-    NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY5r                                   = 1671,
-    NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY6r                                   = 1672,
-    NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODEr                               = 1673,
-    NPPU_IDMA_CFG_INT_RAM_ENr                                             = 1674,
-    NPPU_IDMA_CFG_INT_RAM_MASKr                                           = 1675,
-    NPPU_IDMA_CFG_INT_RAM_STATUSr                                         = 1676,
-    NPPU_IDMA_CFG_SUBSYS_INT_MASK_FLAGr                                   = 1677,
-    NPPU_IDMA_CFG_SUBSYS_INT_UNMASK_FLAGr                                 = 1678,
-    NPPU_IDMA_CFG_DEBUG_CNT_RDCLR_MODEr                                   = 1679,
-    NPPU_PBU_CFG_INT_RAM_EN0r                                             = 1680,
-    NPPU_PBU_CFG_INT_RAM_MASK0r                                           = 1681,
-    NPPU_PBU_CFG_INT_RAM_STATUS0r                                         = 1682,
-    NPPU_PBU_CFG_INT_FIFO_EN0r                                            = 1683,
-    NPPU_PBU_CFG_INT_FIFO_EN1r                                            = 1684,
-    NPPU_PBU_CFG_INT_FIFO_MASK0r                                          = 1685,
-    NPPU_PBU_CFG_INT_FIFO_MASK1r                                          = 1686,
-    NPPU_PBU_CFG_INT_FIFO_STATUS0r                                        = 1687,
-    NPPU_PBU_CFG_INT_FIFO_STATUS1r                                        = 1688,
-    NPPU_PBU_CFG_SUBSYS_INT_MASK_FLAGr                                    = 1689,
-    NPPU_PBU_CFG_SUBSYS_INT_UNMASK_FLAGr                                  = 1690,
-    NPPU_PBU_CFG_SA_IP_ENr                                                = 1691,
-    NPPU_PBU_CFG_DEBUG_CNT_RDCLR_MODEr                                    = 1692,
-    NPPU_PBU_CFG_FPTR_FIFO_AFUL_ASSERT_CFGr                               = 1693,
-    NPPU_PBU_CFG_FPTR_FIFO_AFUL_NEGATE_CFGr                               = 1694,
-    NPPU_PBU_CFG_PF_FIFO_AFUL_ASSERT_CFGr                                 = 1695,
-    NPPU_PBU_CFG_PF_FIFO_AFUL_NEGATE_CFGr                                 = 1696,
-    NPPU_PBU_CFG_PF_FIFO_AEPT_ASSERT_CFGr                                 = 1697,
-    NPPU_PBU_CFG_PF_FIFO_AEPT_NEGATE_CFGr                                 = 1698,
-    NPPU_PBU_CFG_WB_AFUL_ASSERT_CFGr                                      = 1699,
-    NPPU_PBU_CFG_WB_AFUL_NEGATE_CFGr                                      = 1700,
-    NPPU_PBU_CFG_SE_KEY_AFUL_ASSERT_CFGr                                  = 1701,
-    NPPU_PBU_CFG_IFBRD_SE_AFUL_ASSERT_CFGr                                = 1702,
-    NPPU_PBU_CFG_IFBRD_SE_AFUL_NEGATE_CFGr                                = 1703,
-    NPPU_PBU_CFG_IFBRD_ODMA_AFUL_ASSERT_CFGr                              = 1704,
-    NPPU_PBU_CFG_IFBRD_ODMA_AFUL_NEGATE_CFGr                              = 1705,
-    NPPU_PBU_CFG_IFBRD_PPU_AFUL_ASSERT_CFGr                               = 1706,
-    NPPU_PBU_CFG_IFBRD_PPU_AFUL_NEGATE_CFGr                               = 1707,
-    NPPU_PBU_CFG_MC_LOGIC_AFUL_ASSERT_CFGr                                = 1708,
-    NPPU_PBU_CFG_MC_LOGIC_AFUL_NEGATE_CFGr                                = 1709,
-    NPPU_PBU_CFG_MC_LOGIC_DIFFr                                           = 1710,
-    NPPU_PBU_CFG_CFG_PEAK_PORT_CNT_CLRr                                   = 1711,
-    NPPU_PBU_CFG_ALL_FTM_CRDT_THr                                         = 1712,
-    NPPU_PBU_CFG_ALL_FTM_LINK_TH_01r                                      = 1713,
-    NPPU_PBU_CFG_ALL_FTM_LINK_TH_23r                                      = 1714,
-    NPPU_PBU_CFG_ALL_FTM_LINK_TH_45r                                      = 1715,
-    NPPU_PBU_CFG_ALL_FTM_LINK_TH_6r                                       = 1716,
-    NPPU_PBU_CFG_ALL_FTM_TOTAL_CONGEST_THr                                = 1717,
-    NPPU_PBU_CFG_CFG_CRDT_MODEr                                           = 1718,
-    NPPU_PBU_CFG_CFG_PFC_RDY_HIGH_TIMEr                                   = 1719,
-    NPPU_PBU_CFG_CFG_PFC_RDY_LOW_TIMEr                                    = 1720,
-    NPPU_PBU_STAT_PBU_FC_RDYr                                             = 1721,
-    NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY0r                                    = 1722,
-    NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY1r                                    = 1723,
-    NPPU_PBU_STAT_PBU_LIF_GROUP1_RDYr                                     = 1724,
-    NPPU_PBU_STAT_PBU_LIF_GROUP0_PFC_RDYr                                 = 1725,
-    NPPU_PBU_STAT_PBU_LIF_GROUP1_PFC_RDYr                                 = 1726,
-    NPPU_PBU_STAT_PBU_SA_PORT_RDY_0_31r                                   = 1727,
-    NPPU_PBU_STAT_PBU_SA_PORT_RDY_32_50r                                  = 1728,
-    NPPU_PBU_STAT_PBU_PKTRX_MR_PFC_RDYr                                   = 1729,
-    NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_0_31r                             = 1730,
-    NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_32_47r                            = 1731,
-    NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_0_31r                         = 1732,
-    NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_32_47r                        = 1733,
-    NPPU_PBU_STAT_PBU_FTM_CRDT_SYS_INFOr                                  = 1734,
-    NPPU_ISU_CFG_WEIGHT_NORMAL_MCr                                        = 1735,
-    NPPU_ISU_CFG_WEIGHT_SA_MCr                                            = 1736,
-    NPPU_ISU_CFG_WEIGHT_ETMr                                              = 1737,
-    NPPU_ISU_CFG_WEIGHT_LP_MCr                                            = 1738,
-    NPPU_ISU_CFG_WEIGHT_OAMr                                              = 1739,
-    NPPU_ISU_CFG_WEIGHT_LIF_CTRL1r                                        = 1740,
-    NPPU_ISU_CFG_WEIGHT_LIF_CTRL2r                                        = 1741,
-    NPPU_ISU_CFG_ECC_BYPASS_READr                                         = 1742,
-    NPPU_ISU_CFG_ISU_INT_MASKr                                            = 1743,
-    NPPU_ISU_CFG_CFG_CRDT_CYCLEr                                          = 1744,
-    NPPU_ISU_CFG_CFG_CRDT_VALUEr                                          = 1745,
-    NPPU_ISU_CFG_ISU_INT_ENr                                              = 1746,
-    NPPU_ISU_CFG_ISU_PPU_FIFO_FCr                                         = 1747,
-    NPPU_ISU_CFG_ISU_INT_STATUSr                                          = 1748,
-    NPPU_ISU_CFG_FD_PROG_FULL_ASSERT_CFGr                                 = 1749,
-    NPPU_ISU_CFG_FD_PROG_FULL_NEGATE_CFGr                                 = 1750,
-    NPPU_ISU_CFG_LP_PROG_FULL_ASSERT_CFGr                                 = 1751,
-    NPPU_ISU_CFG_LP_PROG_FULL_NEGATE_CFGr                                 = 1752,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT0r                                         = 1753,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT1r                                         = 1754,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT2r                                         = 1755,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT3r                                         = 1756,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT4r                                         = 1757,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT5r                                         = 1758,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT6r                                         = 1759,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT7r                                         = 1760,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT8r                                         = 1761,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT9r                                         = 1762,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT10r                                        = 1763,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT11r                                        = 1764,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT12r                                        = 1765,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT13r                                        = 1766,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT14r                                        = 1767,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT15r                                        = 1768,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT16r                                        = 1769,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT17r                                        = 1770,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT18r                                        = 1771,
-    NPPU_ISU_STAT_DEBUG_CNT_DAT19r                                        = 1772,
-    NPPU_ISU_STAT_DEBUG_CNT_CFGr                                          = 1773,
-    NPPU_ODMA_CFG_EXSA_TDM_OFFSETr                                        = 1774,
-    NPPU_ODMA_CFG_ECC_BYPASS_READTr                                       = 1775,
-    NPPU_ODMA_CFG_ODMA_INT_EN_0r                                          = 1776,
-    NPPU_ODMA_CFG_ODMA_INT_EN_1r                                          = 1777,
-    NPPU_ODMA_CFG_ODMA_INT_EN_2r                                          = 1778,
-    NPPU_ODMA_CFG_ODMA_INT_EN_3r                                          = 1779,
-    NPPU_ODMA_CFG_ODMA_INT_MASK_0r                                        = 1780,
-    NPPU_ODMA_CFG_ODMA_INT_MASK_1r                                        = 1781,
-    NPPU_ODMA_CFG_ODMA_INT_MASK_2r                                        = 1782,
-    NPPU_ODMA_CFG_ODMA_INT_MASK_3r                                        = 1783,
-    NPPU_ODMA_CFG_ODMA_INT_STATUS_0r                                      = 1784,
-    NPPU_ODMA_CFG_ODMA_INT_STATUS_1r                                      = 1785,
-    NPPU_ODMA_CFG_ODMA_INT_STATUS_2r                                      = 1786,
-    NPPU_ODMA_CFG_ODMA_INT_STATUS_3r                                      = 1787,
-    NPPU_ODMA_CFG_SP_TDM_ERR_NOR_CFGr                                     = 1788,
-    NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_Ar                            = 1789,
-    NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_Nr                            = 1790,
-    NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_Ar                            = 1791,
-    NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_Nr                            = 1792,
-    NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_Ar                            = 1793,
-    NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_Nr                            = 1794,
-    NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_Ar                                    = 1795,
-    NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_Nr                                    = 1796,
-    NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_Ar                                  = 1797,
-    NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_Nr                                  = 1798,
-    NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_Ar                          = 1799,
-    NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_Nr                          = 1800,
-    NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_Ar                        = 1801,
-    NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_Nr                        = 1802,
-    NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_Ar                                  = 1803,
-    NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_Nr                                  = 1804,
-    NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_Ar                                   = 1805,
-    NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_Nr                                   = 1806,
-    NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_Ar                                    = 1807,
-    NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_Nr                                    = 1808,
-    NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_Ar                                    = 1809,
-    NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_Nr                                    = 1810,
-    NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_Ar                                    = 1811,
-    NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_Nr                                    = 1812,
-    NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_Ar                                = 1813,
-    NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_Nr                                = 1814,
-    NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_Ar                                = 1815,
-    NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_Nr                                = 1816,
-    NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_Ar                                    = 1817,
-    NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_Nr                                    = 1818,
-    NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_Ar                                    = 1819,
-    NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_Nr                                    = 1820,
-    NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_Ar                             = 1821,
-    NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_Nr                             = 1822,
-    NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_Ar                             = 1823,
-    NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_Nr                             = 1824,
-    NPPU_ODMA_CFG_PP_PROG_FULL_CFG_Ar                                     = 1825,
-    NPPU_ODMA_CFG_PP_PROG_FULL_CFG_Nr                                     = 1826,
-    NPPU_ODMA_CFG_TM_WEIGHTr                                              = 1827,
-    NPPU_ODMA_CFG_PP_WEIGHTr                                              = 1828,
-    NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_Ar                                 = 1829,
-    NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_Nr                                 = 1830,
-    NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_Ar                                  = 1831,
-    NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_Nr                                  = 1832,
-    NPPU_ODMA_CFG_INT_OR_PONr                                             = 1833,
-    NPPU_ODMA_CFG_QUEMNG_CNT_IN_ERR_CNTr                                  = 1834,
-    NPPU_ODMA_CFG_LIF0_PORT_EOP_CNTr                                      = 1835,
-    NPPU_ODMA_CFG_LIF1_PORT_EOP_CNTr                                      = 1836,
-    NPPU_ODMA_CFG_LIFC_PORT0_EOP_CNTr                                     = 1837,
-    NPPU_ODMA_CFG_LIFC_PORT1_EOP_CNTr                                     = 1838,
-    NPPU_ODMA_CFG_FPTR_FIFO_PROG_EPT_CFG_Nr                               = 1839,
-    NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_Ar                               = 1840,
-    NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_Nr                               = 1841,
-    NPPU_OAM_CFG_IND_ACCESS_DONEr                                         = 1842,
-    NPPU_OAM_CFG_IND_ACCESS_COMMANDr                                      = 1843,
-    NPPU_OAM_CFG_IND_DAT0r                                                = 1844,
-    NPPU_OAM_CFG_IND_DAT1r                                                = 1845,
-    NPPU_OAM_CFG_IND_DAT2r                                                = 1846,
-    NPPU_OAM_CFG_IND_DAT3r                                                = 1847,
-    NPPU_OAM_CFG_OAM_TX_MAIN_ENr                                          = 1848,
-    NPPU_OAM_CFG_TX_TOTAL_NUMr                                            = 1849,
-    NPPU_OAM_CFG_OAM_CHK_MAIN_ENr                                         = 1850,
-    NPPU_OAM_CFG_CHK_TOTAL_NUM0r                                          = 1851,
-    NPPU_OAM_CFG_MA_CHK_MAIN_ENr                                          = 1852,
-    NPPU_OAM_CFG_CHK_TOTAL_NUM1r                                          = 1853,
-    NPPU_OAM_CFG_TX_STAT_ENr                                              = 1854,
-    NPPU_OAM_CFG_REC_STAT_ENr                                             = 1855,
-    NPPU_OAM_CFG_STAT_OAM_RDY_MASKr                                       = 1856,
-    NPPU_OAM_CFG_SESSION_GRADING0r                                        = 1857,
-    NPPU_OAM_CFG_SESSION_GRADING1r                                        = 1858,
-    NPPU_OAM_CFG_SESSION_GRADING2r                                        = 1859,
-    NPPU_OAM_CFG_SESSION_GRADING3r                                        = 1860,
-    NPPU_OAM_CFG_BFD_CHK_HADDRr                                           = 1861,
-    NPPU_OAM_CFG_ETHCCM_CHK_HADDRr                                        = 1862,
-    NPPU_OAM_CFG_TPBFD_CHK_HADDRr                                         = 1863,
-    NPPU_OAM_CFG_TPOAM_CCM_CHK_HADDRr                                     = 1864,
-    NPPU_OAM_CFG_BFD_TX_HADDRr                                            = 1865,
-    NPPU_OAM_CFG_ETHCCM_TX_HADDRr                                         = 1866,
-    NPPU_OAM_CFG_TPBFD_TX_HADDRr                                          = 1867,
-    NPPU_OAM_CFG_TPOAM_CCM_TX_HADDRr                                      = 1868,
-    NPPU_OAM_CFG_ETHCCM_MA_CHK_HADDRr                                     = 1869,
-    NPPU_OAM_CFG_TPCCM_MA_CHK_HADDRr                                      = 1870,
-    NPPU_OAM_CFG_GROUPNUM_RAM_CLRr                                        = 1871,
-    NPPU_OAM_CFG_INDEX_RAM0_CLRr                                          = 1872,
-    NPPU_OAM_CFG_INDEX_RAM1_CLRr                                          = 1873,
-    NPPU_OAM_CFG_RMEP_RAM_CLRr                                            = 1874,
-    NPPU_OAM_CFG_MA_RAM_CLRr                                              = 1875,
-    NPPU_OAM_CFG_RAM_INIT_DONEr                                           = 1876,
-    NPPU_OAM_CFG_REC_BFD_DEBUG_ENr                                        = 1877,
-    NPPU_OAM_CFG_OAM_SESSION_INTr                                         = 1878,
-    NPPU_OAM_CFG_PON_INTr                                                 = 1879,
-    NPPU_OAM_CFG_OAM_INT_CLRr                                             = 1880,
-    NPPU_OAM_CFG_TYPE_INT_CLR0r                                           = 1881,
-    NPPU_OAM_CFG_TYPE_INT_CLR1r                                           = 1882,
-    NPPU_OAM_CFG_INTERRUPT_MASKr                                          = 1883,
-    NPPU_OAM_CFG_INT0_INDEXr                                              = 1884,
-    NPPU_OAM_CFG_INT1_INDEXr                                              = 1885,
-    NPPU_OAM_CFG_INT0_INDEX_REGIONr                                       = 1886,
-    NPPU_OAM_CFG_INT1_INDEX_REGIONr                                       = 1887,
-    NPPU_OAM_CFG_BDIINFO_FWFT_FIFO_THr                                    = 1888,
-    NPPU_OAM_CFG_RECSEC_FWFT_FIFO_THr                                     = 1889,
-    NPPU_OAM_CFG_TIMING_CHK_INFO0_FWFT_FIFO_THr                           = 1890,
-    NPPU_OAM_CFG_RECMA_FWFT_FIFO_THr                                      = 1891,
-    NPPU_OAM_CFG_TIMING_CHK_INFO1_FWFT_FIFO_THr                           = 1892,
-    NPPU_OAM_CFG_OAM_TXINST_FIFO_THr                                      = 1893,
-    NPPU_OAM_CFG_OAM_RDINFO_FWFT_FIFO_THr                                 = 1894,
-    NPPU_OAM_CFG_LM_CNT_FWFT_FIFO_THr                                     = 1895,
-    NPPU_OAM_CFG_OAM_PKT_FIFO_THr                                         = 1896,
-    NPPU_OAM_CFG_RECLM_STAT_FIFO_THr                                      = 1897,
-    NPPU_OAM_CFG_TXLM_STAT_FIFO_THr                                       = 1898,
-    NPPU_OAM_CFG_OAM_CHK_FWFT_FIFO_THr                                    = 1899,
-    NPPU_OAM_CFG_TXOAM_STAT_FIFO_THr                                      = 1900,
-    NPPU_OAM_CFG_RECOAM_STAT_FIFO_THr                                     = 1901,
-    NPPU_OAM_CFG_TXPKT_DATA_FWFT_FIFO_THr                                 = 1902,
-    NPPU_OAM_CFG_TSTPKT_FWFT_FIFO_THr                                     = 1903,
-    NPPU_OAM_CFG_TST_TXINST_FWFT_FIFO_THr                                 = 1904,
-    NPPU_OAM_CFG_TSTRX_MAIN_ENr                                           = 1905,
-    NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL2r                                     = 1906,
-    NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL1r                                     = 1907,
-    NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL0r                                     = 1908,
-    NPPU_OAM_CFG_TSTRX_CFG_PARAr                                          = 1909,
-    NPPU_OAM_CFG_FIFO_STATUS_INT_EN_0r                                    = 1910,
-    NPPU_OAM_CFG_FIFO_STATUS_INT_EN_1r                                    = 1911,
-    NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_0r                                  = 1912,
-    NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_1r                                  = 1913,
-    NPPU_OAM_CFG_FIFO_STATUS_INT_STATUSr                                  = 1914,
-    NPPU_OAM_CFG_MAIN_FREQUENCYr                                          = 1915,
-    NPPU_OAM_CFG_OAM_CFG_TYPEr                                            = 1916,
-    NPPU_OAM_CFG_FST_SWCH_ETH_HEAD0r                                      = 1917,
-    NPPU_OAM_CFG_FST_SWCH_ETH_HEAD1r                                      = 1918,
-    NPPU_OAM_CFG_FST_SWCH_ETH_HEAD2r                                      = 1919,
-    NPPU_OAM_CFG_FST_SWCH_ETH_HEAD3r                                      = 1920,
-    NPPU_OAM_CFG_OAM_FS_TXINST_FIFO_THr                                   = 1921,
-    NPPU_OAM_CFG_OAM_MA_FS_TXINST_FIFO_THr                                = 1922,
-    NPPU_OAM_CFG_PON_INT_RAM_CLRr                                         = 1923,
-    NPPU_OAM_CFG_PON_P_INT_INDEXr                                         = 1924,
-    NPPU_OAM_CFG_PON_PROTECT_PKT_FIFO_THr                                 = 1925,
-    NPPU_OAM_CFG_PON_LASER_OFF_ENr                                        = 1926,
-    NPPU_OAM_CFG_PON_PRTCT_PKT_TX_ENr                                     = 1927,
-    NPPU_OAM_CFG_CFG_PON_MASTERr                                          = 1928,
-    NPPU_OAM_CFG_LEVEL_MODEr                                              = 1929,
-    NPPU_OAM_CFG_INTERRUPT_ENr                                            = 1930,
-    NPPU_OAM_CFG_PON_LASER_ON_ENr                                         = 1931,
-    NPPU_OAM_CFG_TI_PON_SDr                                               = 1932,
-    NPPU_OAM_CFG_TI_PON_LOSr                                              = 1933,
-    NPPU_OAM_CFG_IND_DAT4r                                                = 1934,
-    NPPU_OAM_CFG_IND_DAT5r                                                = 1935,
-    NPPU_OAM_CFG_IND_DAT6r                                                = 1936,
-    NPPU_OAM_CFG_IND_DAT7r                                                = 1937,
-    NPPU_OAM_CFG_IND_DAT8r                                                = 1938,
-    NPPU_OAM_CFG_IND_DAT9r                                                = 1939,
-    NPPU_OAM_CFG_IND_DAT10r                                               = 1940,
-    NPPU_OAM_CFG_IND_DAT11r                                               = 1941,
-    NPPU_OAM_CFG_IND_DAT12r                                               = 1942,
-    NPPU_OAM_CFG_IND_DAT13r                                               = 1943,
-    NPPU_OAM_CFG_IND_DAT14r                                               = 1944,
-    NPPU_OAM_CFG_IND_DAT15r                                               = 1945,
-    NPPU_OAM_CFG_OAM_2544_PKT_FIFO_THr                                    = 1946,
-    NPPU_OAM_CFG_TXINFO_RAM_CLRr                                          = 1947,
-    NPPU_OAM_CFG_TXINFO_RAM_INIT_DONEr                                    = 1948,
-    NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS40r                                = 1949,
-    NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS41r                                = 1950,
-    NPPU_OAM_CFG_OAM_2544_FUN_ENr                                         = 1951,
-    NPPU_OAM_CFG_OAM_2544_STAT_CLRr                                       = 1952,
-    NPPU_OAM_CFG_TXDIS_DEFAULTr                                           = 1953,
-    NPPU_OAM_CFG_TXDIS_DEFAULT_ENr                                        = 1954,
-    NPPU_OAM_CFG_TPBFD_FIRSTCHK_THr                                       = 1955,
-    NPPU_OAM_CFG_ETHCCM_FIRSTCHK_THr                                      = 1956,
-    NPPU_OAM_CFG_TPCCM_FIRSTCHK_THr                                       = 1957,
-    NPPU_OAM_STAT_TXSTAT_REQ_CNTr                                         = 1958,
-    NPPU_OAM_STAT_CHKSTAT_REQ_CNTr                                        = 1959,
-    NPPU_OAM_STAT_STAT_OAM_FC_CNTr                                        = 1960,
-    NPPU_OAM_STAT_BFDSEQ_REQ_CNTr                                         = 1961,
-    NPPU_OAM_STAT_LMCNT_REQ_CNTr                                          = 1962,
-    NPPU_OAM_STAT_STAT_OAM_LM_RSP_CNTr                                    = 1963,
-    NPPU_OAM_STAT_STAT_OAM_LM_FC_CNTr                                     = 1964,
-    NPPU_OAM_STAT_SE_REQ_CNTr                                             = 1965,
-    NPPU_OAM_STAT_SE_RSP_CNTr                                             = 1966,
-    NPPU_OAM_STAT_SE_OAM_FC_CNTr                                          = 1967,
-    NPPU_OAM_STAT_OAM_SE_FC_CNTr                                          = 1968,
-    NPPU_OAM_STAT_OAM_PKTRX_SOP_CNTr                                      = 1969,
-    NPPU_OAM_STAT_OAM_PKTRX_EOP_CNTr                                      = 1970,
-    NPPU_OAM_STAT_PKTRX_OAM_FC_CNTr                                       = 1971,
-    NPPU_OAM_STAT_PKTRX_OAM_TST_FC_CNTr                                   = 1972,
-    NPPU_OAM_STAT_ODMA_OAM_SOP_CNTr                                       = 1973,
-    NPPU_OAM_STAT_ODMA_OAM_EOP_CNTr                                       = 1974,
-    NPPU_OAM_STAT_OAM_ODMA_FC_CNTr                                        = 1975,
-    NPPU_OAM_STAT_REC_MA_PKT_ILLEGAL_CNTr                                 = 1976,
-    NPPU_OAM_STAT_REC_RMEP_PKT_ILLEGAL_CNTr                               = 1977,
-    NPPU_OAM_STAT_REC_ETH_AIS_PKT_CNTr                                    = 1978,
-    NPPU_OAM_STAT_REC_TP_AIS_PKT_CNTr                                     = 1979,
-    NPPU_OAM_STAT_REC_TP_CSF_PKT_CNTr                                     = 1980,
-    NPPU_OAM_STAT_REC_ETH_LEVEL_DEFECT_CNTr                               = 1981,
-    NPPU_OAM_STAT_REC_ETH_MEGID_DEFECT_CNTr                               = 1982,
-    NPPU_OAM_STAT_REC_ETH_MEPID_DEFECT_CNTr                               = 1983,
-    NPPU_OAM_STAT_REC_ETH_INTERVAL_DEFECT_CNTr                            = 1984,
-    NPPU_OAM_STAT_REC_SESS_UNENABLE_CNTr                                  = 1985,
-    NPPU_OAM_STAT_OAM_2544_RD_PKT_CNTr                                    = 1986,
-    NPPU_OAM_STAT_DEBUG_CNT_CLRr                                          = 1987,
-    NPPU_OAM_STAT_OAM_PKTRX_CATCH_DATAr                                   = 1988,
-    NPPU_OAM_STAT_ODMA_OAM_CATCH_DATAr                                    = 1989,
-    NPPU_OAM_STAT_TST_SESSION_TX_CNTr                                     = 1990,
-    NPPU_OAM_STAT_TST_SESSION_RX_CNTr                                     = 1991,
-    NPPU_OAM_STAT_TSTRX_LOST_CNTr                                         = 1992,
-    NPPU_OAM_STAT_BFDSEQ_WR_CNTr                                          = 1993,
-    NPPU_OAM_STAT_BFDTIME_WR_CNTr                                         = 1994,
-    NPPU_OAM_STAT_LMCNT_WR_CNTr                                           = 1995,
-    NPPU_OAM_STAT_OAM_FS_PKT_CNTr                                         = 1996,
-    NPPU_OAM_STAT_OAM_MA_FS_PKT_CNTr                                      = 1997,
-    NPPU_OAM_STAT_REC_TP_LEVEL_DEFECT_CNTr                                = 1998,
-    NPPU_OAM_STAT_REC_TP_MEGID_DEFECT_CNTr                                = 1999,
-    NPPU_OAM_STAT_REC_TP_MEPID_DEFECT_CNTr                                = 2000,
-    NPPU_OAM_STAT_REC_TP_INTERVAL_DEFECT_CNTr                             = 2001,
-    NPPU_OAM_STAT_RD_REG_CLEAR_MODEr                                      = 2002,
-    NPPU_OAM_STAT_RD_DATA_REG_CLEAR_MODEr                                 = 2003,
-    NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM_0r                              = 2004,
-    NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM1r                               = 2005,
-    NPPU_OAM_CFG_INDIR_TST_PKT_TX_PARA_RAMr                               = 2006,
-    NPPU_OAM_CFG_INDIR_GROUPNUMRAMr                                       = 2007,
-    NPPU_OAM_CFG_INDIR_OAM_TX_TBL_RAMr                                    = 2008,
-    NPPU_OAM_CFG_INDIR_OAM_CHK_TBL_RAMr                                   = 2009,
-    NPPU_OAM_CFG_INDIR_OAM_MA_CHK_TBL_RAMr                                = 2010,
-    NPPU_OAM_CFG_INDIR_OAM_2544_TX_RAMr                                   = 2011,
-    PPU_PPU_INTERRUPT_EN_Rr                                               = 2012,
-    PPU_PPU_MEC_HOST_INTERRUPTr                                           = 2013,
-    PPU_PPU_DBG_RTL_DATEr                                                 = 2014,
-    PPU_PPU_DUP_START_NUM_CFGr                                            = 2015,
-    PPU_PPU_DEBUG_DATA_WRITE_COMPLETEr                                    = 2016,
-    PPU_PPU_UC_MC_WRR_CFGr                                                = 2017,
-    PPU_PPU_DEBUG_PKT_SEND_ENr                                            = 2018,
-    PPU_PPU_DUP_TBL_IND_ACCESS_DONEr                                      = 2019,
-    PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_MASKr                            = 2020,
-    PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_MASKr                            = 2021,
-    PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_MASKr                          = 2022,
-    PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_MASKr                               = 2023,
-    PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_MASKr                = 2024,
-    PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_MASKr                = 2025,
-    PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_MASKr                                = 2026,
-    PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Lr                            = 2027,
-    PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Mr                            = 2028,
-    PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Hr                            = 2029,
-    PPU_PPU_PPU_RAM_CHECK_ERR_MASKr                                       = 2030,
-    PPU_PPU_INSTRMEM_FIFO_INTERRUPT_MASKr                                 = 2031,
-    PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_STAr                             = 2032,
-    PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_STAr                             = 2033,
-    PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_STAr                           = 2034,
-    PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_STAr                                = 2035,
-    PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_STAr                 = 2036,
-    PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_STAr                 = 2037,
-    PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_STAr                                 = 2038,
-    PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Lr                             = 2039,
-    PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Mr                             = 2040,
-    PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Hr                             = 2041,
-    PPU_PPU_INSTRMEM_FIFO_INTERRUPT_STAr                                  = 2042,
-    PPU_PPU_PPU_RAM_CHECK_ECC_ERR_FLAG_1r                                 = 2043,
-    PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_FLAGr                            = 2044,
-    PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_FLAGr                            = 2045,
-    PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_FLAGr                          = 2046,
-    PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_FLAGr                               = 2047,
-    PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_FLAGr                = 2048,
-    PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_FLAGr                = 2049,
-    PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_FLAGr                                = 2050,
-    PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Lr                            = 2051,
-    PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Mr                            = 2052,
-    PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Hr                            = 2053,
-    PPU_PPU_INSTRMEM_FIFO_INTERRUPT_FLAGr                                 = 2054,
-    PPU_PPU_INSTRMEM_RAM_INT_OUTr                                         = 2055,
-    PPU_PPU_INSTRMEM_RAM_INT_MASKr                                        = 2056,
-    PPU_PPU_INSTRMEM_RAM_INT_STATr                                        = 2057,
-    PPU_PPU_INSTRMEM_RAM_INT_FLAGr                                        = 2058,
-    PPU_PPU_PPU_COUNT_CFGr                                                = 2059,
-    PPU_PPU_PPU_STATICS_CFGr                                              = 2060,
-    PPU_PPU_PPU_STATICS_WB_CFGr                                           = 2061,
-    PPU_PPU_WR_TABLE_SELF_RSP_EN_CFGr                                     = 2062,
-    PPU_PPU_PPU_RANDOM_ARBITER_8TO1_CFGr                                  = 2063,
-    PPU_PPU_PPU_REORDER_BYPASS_FLOW_NUM_CFGr                              = 2064,
-    PPU_PPU_COS_METER_CFG_Hr                                              = 2065,
-    PPU_PPU_COS_METER_CFG_Lr                                              = 2066,
-    PPU_PPU_INSTRMEM_RDYr                                                 = 2067,
-    PPU_PPU_INSTRMEM_ADDRr                                                = 2068,
-    PPU_PPU_INSTRMEM_IND_ACCESS_DONEr                                     = 2069,
-    PPU_PPU_INSTRMEM_INSTR0_DATA_Lr                                       = 2070,
-    PPU_PPU_INSTRMEM_INSTR0_DATA_Hr                                       = 2071,
-    PPU_PPU_INSTRMEM_INSTR1_DATA_Lr                                       = 2072,
-    PPU_PPU_INSTRMEM_INSTR1_DATA_Hr                                       = 2073,
-    PPU_PPU_INSTRMEM_INSTR2_DATA_Lr                                       = 2074,
-    PPU_PPU_INSTRMEM_INSTR2_DATA_Hr                                       = 2075,
-    PPU_PPU_INSTRMEM_INSTR3_DATA_Lr                                       = 2076,
-    PPU_PPU_INSTRMEM_INSTR3_DATA_Hr                                       = 2077,
-    PPU_PPU_INSTRMEM_READ_INSTR0_DATA_Lr                                  = 2078,
-    PPU_PPU_INSTRMEM_READ_INSTR0_DATA_Hr                                  = 2079,
-    PPU_PPU_INSTRMEM_READ_INSTR1_DATA_Lr                                  = 2080,
-    PPU_PPU_INSTRMEM_READ_INSTR1_DATA_Hr                                  = 2081,
-    PPU_PPU_INSTRMEM_READ_INSTR2_DATA_Lr                                  = 2082,
-    PPU_PPU_INSTRMEM_READ_INSTR2_DATA_Hr                                  = 2083,
-    PPU_PPU_INSTRMEM_READ_INSTR3_DATA_Lr                                  = 2084,
-    PPU_PPU_INSTRMEM_READ_INSTR3_DATA_Hr                                  = 2085,
-    PPU_PPU_SE_PPU_MC_SRH_FC_CNT_Hr                                       = 2086,
-    PPU_PPU_SE_PPU_MC_SRH_FC_CNT_Lr                                       = 2087,
-    PPU_PPU_PPU_SE_MC_SRH_FC_CNT_Hr                                       = 2088,
-    PPU_PPU_PPU_SE_MC_SRH_FC_CNT_Lr                                       = 2089,
-    PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_Hr                                      = 2090,
-    PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_Lr                                      = 2091,
-    PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_Hr                                      = 2092,
-    PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_Lr                                      = 2093,
-    PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_Hr                                    = 2094,
-    PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_Lr                                    = 2095,
-    PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_Hr                                   = 2096,
-    PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_Lr                                   = 2097,
-    PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_Hr                               = 2098,
-    PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_Lr                               = 2099,
-    PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_Hr                               = 2100,
-    PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_Lr                               = 2101,
-    PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_Hr                                      = 2102,
-    PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_Lr                                      = 2103,
-    PPU_PPU_PBU_PPU_WB_FC_CNT_Hr                                          = 2104,
-    PPU_PPU_PBU_PPU_WB_FC_CNT_Lr                                          = 2105,
-    PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_Hr                               = 2106,
-    PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_Lr                               = 2107,
-    PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_Hr                               = 2108,
-    PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_Lr                               = 2109,
-    PPU_PPU_ODMA_PPU_PARA_FC_CNT_Hr                                       = 2110,
-    PPU_PPU_ODMA_PPU_PARA_FC_CNT_Lr                                       = 2111,
-    PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_Hr                                   = 2112,
-    PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_Lr                                   = 2113,
-    PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_Hr                                  = 2114,
-    PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_Lr                                  = 2115,
-    PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_Hr                                 = 2116,
-    PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_Lr                                 = 2117,
-    PPU_PPU_PPU_PKTRX_UC_FC_CNT_Hr                                        = 2118,
-    PPU_PPU_PPU_PKTRX_UC_FC_CNT_Lr                                        = 2119,
-    PPU_PPU_PPU_PKTRX_MC_FC_CNT_Hr                                        = 2120,
-    PPU_PPU_PPU_PKTRX_MC_FC_CNT_Lr                                        = 2121,
-    PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_Hr                                     = 2122,
-    PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_Lr                                     = 2123,
-    PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_Hr                                    = 2124,
-    PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_Lr                                    = 2125,
-    PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_Hr                                    = 2126,
-    PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_Lr                                    = 2127,
-    PPU_PPU_PPU_PBU_WB_VLD_CNT_Hr                                         = 2128,
-    PPU_PPU_PPU_PBU_WB_VLD_CNT_Lr                                         = 2129,
-    PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_Hr                               = 2130,
-    PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_Lr                               = 2131,
-    PPU_PPU_PPU_ODMA_PARA_VLD_CNT_Hr                                      = 2132,
-    PPU_PPU_PPU_ODMA_PARA_VLD_CNT_Lr                                      = 2133,
-    PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_Hr                                 = 2134,
-    PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_Lr                                 = 2135,
-    PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_Hr                            = 2136,
-    PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_Lr                            = 2137,
-    PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_Hr                                 = 2138,
-    PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_Lr                                 = 2139,
-    PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_Hr                       = 2140,
-    PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_Lr                       = 2141,
-    PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_Hr                          = 2142,
-    PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_Lr                          = 2143,
-    PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_Hr                = 2144,
-    PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_Lr                = 2145,
-    PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_Hr               = 2146,
-    PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_Lr               = 2147,
-    PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_Hr               = 2148,
-    PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_Lr               = 2149,
-    PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_Hr                          = 2150,
-    PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_Lr                          = 2151,
-    PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_Hr                = 2152,
-    PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_Lr                = 2153,
-    PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_Hr               = 2154,
-    PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_Lr               = 2155,
-    PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_Hr               = 2156,
-    PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_Lr               = 2157,
-    PPU_PPU_STATICS_PPU_WB_VLD_CNT_Hr                                     = 2158,
-    PPU_PPU_STATICS_PPU_WB_VLD_CNT_Lr                                     = 2159,
-    PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_Hr                           = 2160,
-    PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_Lr                           = 2161,
-    PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_Hr                          = 2162,
-    PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_Lr                          = 2163,
-    PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_Hr                          = 2164,
-    PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_Lr                          = 2165,
-    PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_Hr                      = 2166,
-    PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_Lr                      = 2167,
-    PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_Hr                             = 2168,
-    PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_Lr                             = 2169,
-    PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_Hr                   = 2170,
-    PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_Lr                   = 2171,
-    PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_Hr                            = 2172,
-    PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_Lr                            = 2173,
-    PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_Hr                           = 2174,
-    PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_Lr                           = 2175,
-    PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_Hr                            = 2176,
-    PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_Lr                            = 2177,
-    PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_Hr             = 2178,
-    PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_Lr             = 2179,
-    PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_Hr                    = 2180,
-    PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_Lr                    = 2181,
-    PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_Hr          = 2182,
-    PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_Lr          = 2183,
-    PPU_PPU_CAR_GREEN_PKT_VLD_CNT_Hr                                      = 2184,
-    PPU_PPU_CAR_GREEN_PKT_VLD_CNT_Lr                                      = 2185,
-    PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_Hr                                     = 2186,
-    PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_Lr                                     = 2187,
-    PPU_PPU_CAR_RED_PKT_VLD_CNT_Hr                                        = 2188,
-    PPU_PPU_CAR_RED_PKT_VLD_CNT_Lr                                        = 2189,
-    PPU_PPU_CAR_DROP_PKT_VLD_CNT_Hr                                       = 2190,
-    PPU_PPU_CAR_DROP_PKT_VLD_CNT_Lr                                       = 2191,
-    PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_Hr                                   = 2192,
-    PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_Lr                                   = 2193,
-    PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_Hr                                    = 2194,
-    PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_Lr                                    = 2195,
-    PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_ASSERT_CFGr            = 2196,
-    PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_NEGATE_CFGr            = 2197,
-    PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_ASSERT_CFGr           = 2198,
-    PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_NEGATE_CFGr           = 2199,
-    PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_ASSERT_CFGr                    = 2200,
-    PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_NEGATE_CFGr                    = 2201,
-    PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_ASSERT_CFGr                   = 2202,
-    PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_NEGATE_CFGr                   = 2203,
-    PPU_PPU_MCCNT_FIFO_PROG_FULL_ASSERT_CFGr                              = 2204,
-    PPU_PPU_MCCNT_FIFO_PROG_FULL_NEGATE_CFGr                              = 2205,
-    PPU_PPU_MCCNT_FIFO_PROG_EMPTY_ASSERT_CFGr                             = 2206,
-    PPU_PPU_MCCNT_FIFO_PROG_EMPTY_NEGATE_CFGr                             = 2207,
-    PPU_PPU_UC_MF_FIFO_PROG_FULL_ASSERT_CFGr                              = 2208,
-    PPU_PPU_UC_MF_FIFO_PROG_FULL_NEGATE_CFGr                              = 2209,
-    PPU_PPU_UC_MF_FIFO_PROG_EMPTY_ASSERT_CFGr                             = 2210,
-    PPU_PPU_UC_MF_FIFO_PROG_EMPTY_NEGATE_CFGr                             = 2211,
-    PPU_PPU_MC_MF_FIFO_PROG_FULL_ASSERT_CFGr                              = 2212,
-    PPU_PPU_MC_MF_FIFO_PROG_FULL_NEGATE_CFGr                              = 2213,
-    PPU_PPU_MC_MF_FIFO_PROG_EMPTY_ASSERT_CFGr                             = 2214,
-    PPU_PPU_MC_MF_FIFO_PROG_EMPTY_NEGATE_CFGr                             = 2215,
-    PPU_PPU_ISU_MF_FIFO_PROG_FULL_ASSERT_CFGr                             = 2216,
-    PPU_PPU_ISU_MF_FIFO_PROG_FULL_NEGATE_CFGr                             = 2217,
-    PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_ASSERT_CFGr                            = 2218,
-    PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_NEGATE_CFGr                            = 2219,
-    PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_ASSERT_CFGr                       = 2220,
-    PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_NEGATE_CFGr                       = 2221,
-    PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_ASSERT_CFGr                     = 2222,
-    PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_NEGATE_CFGr                     = 2223,
-    PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_ASSERT_CFGr                    = 2224,
-    PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_NEGATE_CFGr                    = 2225,
-    PPU_PPU_GROUP_ID_FIFO_PROG_FULL_ASSERT_CFGr                           = 2226,
-    PPU_PPU_GROUP_ID_FIFO_PROG_FULL_NEGATE_CFGr                           = 2227,
-    PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_ASSERT_CFGr                          = 2228,
-    PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_NEGATE_CFGr                          = 2229,
-    PPU_PPU_SA_PARA_FIFO_PROG_FULL_ASSERT_CFGr                            = 2230,
-    PPU_PPU_SA_PARA_FIFO_PROG_FULL_NEGATE_CFGr                            = 2231,
-    PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr                           = 2232,
-    PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr                           = 2233,
-    PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_ASSERT_CFGr                          = 2234,
-    PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_NEGATE_CFGr                          = 2235,
-    PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr                         = 2236,
-    PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr                         = 2237,
-    PPU_PPU_DUP_PARA_FIFO_PROG_FULL_ASSERT_CFGr                           = 2238,
-    PPU_PPU_DUP_PARA_FIFO_PROG_FULL_NEGATE_CFGr                           = 2239,
-    PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr                          = 2240,
-    PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr                          = 2241,
-    PPU_PPU_PF_RSP_FIFO_PROG_FULL_ASSERT_CFGr                             = 2242,
-    PPU_PPU_PF_RSP_FIFO_PROG_FULL_NEGATE_CFGr                             = 2243,
-    PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr                            = 2244,
-    PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr                            = 2245,
-    PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_ASSERT_CFGr                        = 2246,
-    PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_NEGATE_CFGr                        = 2247,
-    PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_ASSERT_CFGr                       = 2248,
-    PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_NEGATE_CFGr                       = 2249,
-    PPU_PPU_PF_REQ_FIFO_PROG_FULL_ASSERT_CFGr                             = 2250,
-    PPU_PPU_PF_REQ_FIFO_PROG_FULL_NEGATE_CFGr                             = 2251,
-    PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_ASSERT_CFGr                            = 2252,
-    PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_NEGATE_CFGr                            = 2253,
-    PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_ASSERT_CFGr                           = 2254,
-    PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_NEGATE_CFGr                           = 2255,
-    PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_ASSERT_CFGr                          = 2256,
-    PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_NEGATE_CFGr                          = 2257,
-    PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_ASSERT_CFGr                = 2258,
-    PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_NEGATE_CFGr                = 2259,
-    PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_ASSERT_CFGr               = 2260,
-    PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_NEGATE_CFGr               = 2261,
-    PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_ASSERT_CFGr                        = 2262,
-    PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_NEGATE_CFGr                        = 2263,
-    PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_ASSERT_CFGr                       = 2264,
-    PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_NEGATE_CFGr                       = 2265,
-    PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_ASSERT_CFGr            = 2266,
-    PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_NEGATE_CFGr            = 2267,
-    PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr           = 2268,
-    PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr           = 2269,
-    PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_ASSERT_CFGr          = 2270,
-    PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_NEGATE_CFGr          = 2271,
-    PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr         = 2272,
-    PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr         = 2273,
-    PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_ASSERT_CFGr            = 2274,
-    PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_NEGATE_CFGr            = 2275,
-    PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr           = 2276,
-    PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr           = 2277,
-    PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_ASSERT_CFGr             = 2278,
-    PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_NEGATE_CFGr             = 2279,
-    PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr            = 2280,
-    PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr            = 2281,
-    PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_ASSERT_CFGr                = 2282,
-    PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_NEGATE_CFGr                = 2283,
-    PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_ASSERT_CFGr               = 2284,
-    PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_NEGATE_CFGr               = 2285,
-    PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_ASSERT_CFGr            = 2286,
-    PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_NEGATE_CFGr            = 2287,
-    PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr           = 2288,
-    PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr           = 2289,
-    PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_ASSERT_CFGr            = 2290,
-    PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_NEGATE_CFGr            = 2291,
-    PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr           = 2292,
-    PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr           = 2293,
-    PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_ASSERT_CFGr              = 2294,
-    PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_NEGATE_CFGr              = 2295,
-    PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr             = 2296,
-    PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr             = 2297,
-    PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_ASSERT_CFGr       = 2298,
-    PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_NEGATE_CFGr       = 2299,
-    PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr      = 2300,
-    PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr      = 2301,
-    PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_ASSERT_CFGr               = 2302,
-    PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_NEGATE_CFGr               = 2303,
-    PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr              = 2304,
-    PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr              = 2305,
-    PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_ASSERT_CFGr                   = 2306,
-    PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_NEGATE_CFGr                   = 2307,
-    PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_ASSERT_CFGr                  = 2308,
-    PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_NEGATE_CFGr                  = 2309,
-    PPU_PPU_PKT_DATA0r                                                    = 2310,
-    PPU_PPU_PKT_DATA1r                                                    = 2311,
-    PPU_PPU_PKT_DATA2r                                                    = 2312,
-    PPU_PPU_PKT_DATA3r                                                    = 2313,
-    PPU_PPU_PKT_DATA4r                                                    = 2314,
-    PPU_PPU_PKT_DATA5r                                                    = 2315,
-    PPU_PPU_PKT_DATA6r                                                    = 2316,
-    PPU_PPU_PKT_DATA7r                                                    = 2317,
-    PPU_PPU_PKT_DATA8r                                                    = 2318,
-    PPU_PPU_PKT_DATA9r                                                    = 2319,
-    PPU_PPU_PKT_DATA10r                                                   = 2320,
-    PPU_PPU_PKT_DATA11r                                                   = 2321,
-    PPU_PPU_PKT_DATA12r                                                   = 2322,
-    PPU_PPU_PKT_DATA13r                                                   = 2323,
-    PPU_PPU_PKT_DATA14r                                                   = 2324,
-    PPU_PPU_PKT_DATA15r                                                   = 2325,
-    PPU_PPU_PKT_DATA16r                                                   = 2326,
-    PPU_PPU_PKT_DATA17r                                                   = 2327,
-    PPU_PPU_PKT_DATA18r                                                   = 2328,
-    PPU_PPU_PKT_DATA19r                                                   = 2329,
-    PPU_PPU_PKT_DATA20r                                                   = 2330,
-    PPU_PPU_PKT_DATA21r                                                   = 2331,
-    PPU_PPU_PKT_DATA22r                                                   = 2332,
-    PPU_PPU_PKT_DATA23r                                                   = 2333,
-    PPU_PPU_PKT_DATA24r                                                   = 2334,
-    PPU_PPU_PKT_DATA25r                                                   = 2335,
-    PPU_PPU_PKT_DATA26r                                                   = 2336,
-    PPU_PPU_PKT_DATA27r                                                   = 2337,
-    PPU_PPU_PKT_DATA28r                                                   = 2338,
-    PPU_PPU_PKT_DATA29r                                                   = 2339,
-    PPU_PPU_PKT_DATA30r                                                   = 2340,
-    PPU_PPU_PKT_DATA31r                                                   = 2341,
-    PPU_PPU_PKT_DATA32r                                                   = 2342,
-    PPU_PPU_PKT_DATA33r                                                   = 2343,
-    PPU_PPU_PKT_DATA34r                                                   = 2344,
-    PPU_PPU_PKT_DATA35r                                                   = 2345,
-    PPU_PPU_PKT_DATA36r                                                   = 2346,
-    PPU_PPU_PKT_DATA37r                                                   = 2347,
-    PPU_PPU_PKT_DATA38r                                                   = 2348,
-    PPU_PPU_PKT_DATA39r                                                   = 2349,
-    PPU_PPU_PKT_DATA40r                                                   = 2350,
-    PPU_PPU_PKT_DATA41r                                                   = 2351,
-    PPU_PPU_PKT_DATA42r                                                   = 2352,
-    PPU_PPU_PKT_DATA43r                                                   = 2353,
-    PPU_PPU_PKT_DATA44r                                                   = 2354,
-    PPU_PPU_PKT_DATA45r                                                   = 2355,
-    PPU_PPU_PKT_DATA46r                                                   = 2356,
-    PPU_PPU_PKT_DATA47r                                                   = 2357,
-    PPU_PPU_PKT_DATA48r                                                   = 2358,
-    PPU_PPU_PKT_DATA49r                                                   = 2359,
-    PPU_PPU_PKT_DATA50r                                                   = 2360,
-    PPU_PPU_PKT_DATA51r                                                   = 2361,
-    PPU_PPU_PKT_DATA52r                                                   = 2362,
-    PPU_PPU_PKT_DATA53r                                                   = 2363,
-    PPU_PPU_PKT_DATA54r                                                   = 2364,
-    PPU_PPU_PKT_DATA55r                                                   = 2365,
-    PPU_PPU_PKT_DATA56r                                                   = 2366,
-    PPU_PPU_PKT_DATA57r                                                   = 2367,
-    PPU_PPU_PKT_DATA58r                                                   = 2368,
-    PPU_PPU_PKT_DATA59r                                                   = 2369,
-    PPU_PPU_PKT_DATA60r                                                   = 2370,
-    PPU_PPU_PKT_DATA61r                                                   = 2371,
-    PPU_PPU_PKT_DATA62r                                                   = 2372,
-    PPU_PPU_PKT_DATA63r                                                   = 2373,
-    PPU_PPU_PKT_DATA64r                                                   = 2374,
-    PPU_PPU_PKT_DATA65r                                                   = 2375,
-    PPU_PPU_PKT_DATA66r                                                   = 2376,
-    PPU_PPU_PKT_DATA67r                                                   = 2377,
-    PPU_PPU_PKT_DATA68r                                                   = 2378,
-    PPU_PPU_PKT_DATA69r                                                   = 2379,
-    PPU_PPU_PKT_DATA70r                                                   = 2380,
-    PPU_PPU_PKT_DATA71r                                                   = 2381,
-    PPU_PPU_PKT_DATA72r                                                   = 2382,
-    PPU_PPU_PKT_DATA73r                                                   = 2383,
-    PPU_PPU_PKT_DATA74r                                                   = 2384,
-    PPU_PPU_PKT_DATA75r                                                   = 2385,
-    PPU_PPU_PKT_DATA76r                                                   = 2386,
-    PPU_PPU_PKT_DATA77r                                                   = 2387,
-    PPU_PPU_PKT_DATA78r                                                   = 2388,
-    PPU_PPU_PKT_DATA79r                                                   = 2389,
-    PPU_PPU_PKT_DATA80r                                                   = 2390,
-    PPU_PPU_PKT_DATA81r                                                   = 2391,
-    PPU_PPU_PKT_DATA82r                                                   = 2392,
-    PPU_PPU_PKT_DATA83r                                                   = 2393,
-    PPU_PPU_PKT_DATA84r                                                   = 2394,
-    PPU_PPU_PKT_DATA85r                                                   = 2395,
-    PPU_PPU_PKT_DATA86r                                                   = 2396,
-    PPU_PPU_PKT_DATA87r                                                   = 2397,
-    PPU_PPU_PKT_DATA88r                                                   = 2398,
-    PPU_PPU_PKT_DATA89r                                                   = 2399,
-    PPU_PPU_PKT_DATA90r                                                   = 2400,
-    PPU_PPU_PKT_DATA91r                                                   = 2401,
-    PPU_PPU_PKT_DATA92r                                                   = 2402,
-    PPU_PPU_PKT_DATA93r                                                   = 2403,
-    PPU_PPU_PKT_DATA94r                                                   = 2404,
-    PPU_PPU_PKT_DATA95r                                                   = 2405,
-    PPU_PPU_PKT_DATA96r                                                   = 2406,
-    PPU_PPU_PKT_DATA97r                                                   = 2407,
-    PPU_PPU_PKT_DATA98r                                                   = 2408,
-    PPU_PPU_PKT_DATA99r                                                   = 2409,
-    PPU_PPU_PKT_DATA100r                                                  = 2410,
-    PPU_PPU_PKT_DATA101r                                                  = 2411,
-    PPU_PPU_PKT_DATA102r                                                  = 2412,
-    PPU_PPU_PKT_DATA103r                                                  = 2413,
-    PPU_PPU_PKT_DATA104r                                                  = 2414,
-    PPU_PPU_PKT_DATA105r                                                  = 2415,
-    PPU_PPU_PKT_DATA106r                                                  = 2416,
-    PPU_PPU_PKT_DATA107r                                                  = 2417,
-    PPU_PPU_PKT_DATA108r                                                  = 2418,
-    PPU_PPU_PKT_DATA109r                                                  = 2419,
-    PPU_PPU_PKT_DATA110r                                                  = 2420,
-    PPU_PPU_PKT_DATA111r                                                  = 2421,
-    PPU_PPU_PKT_DATA112r                                                  = 2422,
-    PPU_PPU_PKT_DATA113r                                                  = 2423,
-    PPU_PPU_PKT_DATA114r                                                  = 2424,
-    PPU_PPU_PKT_DATA115r                                                  = 2425,
-    PPU_PPU_PKT_DATA116r                                                  = 2426,
-    PPU_PPU_PKT_DATA117r                                                  = 2427,
-    PPU_PPU_PKT_DATA118r                                                  = 2428,
-    PPU_PPU_PKT_DATA119r                                                  = 2429,
-    PPU_PPU_PKT_DATA120r                                                  = 2430,
-    PPU_PPU_PKT_DATA121r                                                  = 2431,
-    PPU_PPU_PKT_DATA122r                                                  = 2432,
-    PPU_PPU_PKT_DATA123r                                                  = 2433,
-    PPU_PPU_PKT_DATA124r                                                  = 2434,
-    PPU_PPU_PKT_DATA125r                                                  = 2435,
-    PPU_PPU_PKT_DATA126r                                                  = 2436,
-    PPU_PPU_PKT_DATA127r                                                  = 2437,
-    PPU_PPU_SPR0r                                                         = 2438,
-    PPU_PPU_SPR1r                                                         = 2439,
-    PPU_PPU_SPR2r                                                         = 2440,
-    PPU_PPU_SPR3r                                                         = 2441,
-    PPU_PPU_SPR4r                                                         = 2442,
-    PPU_PPU_SPR5r                                                         = 2443,
-    PPU_PPU_SPR6r                                                         = 2444,
-    PPU_PPU_SPR7r                                                         = 2445,
-    PPU_PPU_SPR8r                                                         = 2446,
-    PPU_PPU_SPR9r                                                         = 2447,
-    PPU_PPU_SPR10r                                                        = 2448,
-    PPU_PPU_SPR11r                                                        = 2449,
-    PPU_PPU_SPR12r                                                        = 2450,
-    PPU_PPU_SPR13r                                                        = 2451,
-    PPU_PPU_SPR14r                                                        = 2452,
-    PPU_PPU_SPR15r                                                        = 2453,
-    PPU_PPU_SPR16r                                                        = 2454,
-    PPU_PPU_SPR17r                                                        = 2455,
-    PPU_PPU_SPR18r                                                        = 2456,
-    PPU_PPU_SPR19r                                                        = 2457,
-    PPU_PPU_SPR20r                                                        = 2458,
-    PPU_PPU_SPR21r                                                        = 2459,
-    PPU_PPU_SPR22r                                                        = 2460,
-    PPU_PPU_SPR23r                                                        = 2461,
-    PPU_PPU_SPR24r                                                        = 2462,
-    PPU_PPU_SPR25r                                                        = 2463,
-    PPU_PPU_SPR26r                                                        = 2464,
-    PPU_PPU_SPR27r                                                        = 2465,
-    PPU_PPU_SPR28r                                                        = 2466,
-    PPU_PPU_SPR29r                                                        = 2467,
-    PPU_PPU_SPR30r                                                        = 2468,
-    PPU_PPU_SPR31r                                                        = 2469,
-    PPU_PPU_RSP0r                                                         = 2470,
-    PPU_PPU_RSP1r                                                         = 2471,
-    PPU_PPU_RSP2r                                                         = 2472,
-    PPU_PPU_RSP3r                                                         = 2473,
-    PPU_PPU_RSP4r                                                         = 2474,
-    PPU_PPU_RSP5r                                                         = 2475,
-    PPU_PPU_RSP6r                                                         = 2476,
-    PPU_PPU_RSP7r                                                         = 2477,
-    PPU_PPU_RSP8r                                                         = 2478,
-    PPU_PPU_RSP9r                                                         = 2479,
-    PPU_PPU_RSP10r                                                        = 2480,
-    PPU_PPU_RSP11r                                                        = 2481,
-    PPU_PPU_RSP12r                                                        = 2482,
-    PPU_PPU_RSP13r                                                        = 2483,
-    PPU_PPU_RSP14r                                                        = 2484,
-    PPU_PPU_RSP15r                                                        = 2485,
-    PPU_PPU_RSP16r                                                        = 2486,
-    PPU_PPU_RSP17r                                                        = 2487,
-    PPU_PPU_RSP18r                                                        = 2488,
-    PPU_PPU_RSP19r                                                        = 2489,
-    PPU_PPU_RSP20r                                                        = 2490,
-    PPU_PPU_RSP21r                                                        = 2491,
-    PPU_PPU_RSP22r                                                        = 2492,
-    PPU_PPU_RSP23r                                                        = 2493,
-    PPU_PPU_RSP24r                                                        = 2494,
-    PPU_PPU_RSP25r                                                        = 2495,
-    PPU_PPU_RSP26r                                                        = 2496,
-    PPU_PPU_RSP27r                                                        = 2497,
-    PPU_PPU_RSP28r                                                        = 2498,
-    PPU_PPU_RSP29r                                                        = 2499,
-    PPU_PPU_RSP30r                                                        = 2500,
-    PPU_PPU_RSP31r                                                        = 2501,
-    PPU_PPU_KEY0r                                                         = 2502,
-    PPU_PPU_KEY1r                                                         = 2503,
-    PPU_PPU_KEY2r                                                         = 2504,
-    PPU_PPU_KEY3r                                                         = 2505,
-    PPU_PPU_KEY4r                                                         = 2506,
-    PPU_PPU_KEY5r                                                         = 2507,
-    PPU_PPU_KEY6r                                                         = 2508,
-    PPU_PPU_KEY7r                                                         = 2509,
-    PPU_PPU_KEY8r                                                         = 2510,
-    PPU_PPU_KEY9r                                                         = 2511,
-    PPU_PPU_KEY10r                                                        = 2512,
-    PPU_PPU_KEY11r                                                        = 2513,
-    PPU_PPU_KEY12r                                                        = 2514,
-    PPU_PPU_KEY13r                                                        = 2515,
-    PPU_PPU_KEY14r                                                        = 2516,
-    PPU_PPU_KEY15r                                                        = 2517,
-    PPU_PPU_KEY16r                                                        = 2518,
-    PPU_PPU_KEY17r                                                        = 2519,
-    PPU_PPU_KEY18r                                                        = 2520,
-    PPU_PPU_KEY19r                                                        = 2521,
-    PPU_PPU_FLAGr                                                         = 2522,
-    PPU_CLUSTER_INT_1200M_FLAGr                                           = 2523,
-    PPU_CLUSTER_BP_INSTR_Lr                                               = 2524,
-    PPU_CLUSTER_BP_INSTR_Hr                                               = 2525,
-    PPU_CLUSTER_BP_ADDRr                                                  = 2526,
-    PPU_CLUSTER_DRRr                                                      = 2527,
-    PPU_CLUSTER_DSRr                                                      = 2528,
-    PPU_CLUSTER_DBG_RTL_DATEr                                             = 2529,
-    PPU_CLUSTER_ME_CONTINUEr                                              = 2530,
-    PPU_CLUSTER_ME_STEPr                                                  = 2531,
-    PPU_CLUSTER_ME_REFRESHr                                               = 2532,
-    PPU_CLUSTER_DRR_CLRr                                                  = 2533,
-    PPU_CLUSTER_ME_BUSY_THRESOLDr                                         = 2534,
-    PPU_CLUSTER_INT_1200M_STAr                                            = 2535,
-    PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_Lr                                 = 2536,
-    PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_Hr                                 = 2537,
-    PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_Lr                                 = 2538,
-    PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_Hr                                 = 2539,
-    PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_Lr                                  = 2540,
-    PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_Hr                                  = 2541,
-    PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_Lr                        = 2542,
-    PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_Hr                        = 2543,
-    PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_Lr                        = 2544,
-    PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_Hr                        = 2545,
-    PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_Lr                        = 2546,
-    PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_Hr                        = 2547,
-    PPU_CLUSTER_PPU_STATICS_WB_EXCEPTION_CFGr                             = 2548,
-    PPU_CLUSTER_THREAD_SWITCH_ENr                                         = 2549,
-    PPU_CLUSTER_IS_ME_NOT_IDLEr                                           = 2550,
-    PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_ASSERT_CFGr            = 2551,
-    PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_NEGATE_CFGr            = 2552,
-    PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr                      = 2553,
-    PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr                      = 2554,
-    PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr                      = 2555,
-    PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr                      = 2556,
-    PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_ASSERT_CFGr              = 2557,
-    PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_NEGATE_CFGr              = 2558,
-    PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_ASSERT_CFGr             = 2559,
-    PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_NEGATE_CFGr             = 2560,
-    PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_ASSERT_CFGr              = 2561,
-    PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_NEGATE_CFGr              = 2562,
-    PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_ASSERT_CFGr             = 2563,
-    PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_NEGATE_CFGr             = 2564,
-    PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr                      = 2565,
-    PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr                      = 2566,
-    PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFGr               = 2567,
-    PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFGr               = 2568,
-    PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr              = 2569,
-    PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr              = 2570,
-    PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_ASSERT_CFGr                        = 2571,
-    PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_NEGATE_CFGr                        = 2572,
-    PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr                       = 2573,
-    PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr                       = 2574,
-    PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_ASSERT_CFGr                   = 2575,
-    PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_NEGATE_CFGr                   = 2576,
-    PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr                  = 2577,
-    PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr                  = 2578,
-    PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFGr               = 2579,
-    PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFGr               = 2580,
-    PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr              = 2581,
-    PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr              = 2582,
-    PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_ASSERT_CFGr                   = 2583,
-    PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_NEGATE_CFGr                   = 2584,
-    PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_ASSERT_CFGr                   = 2585,
-    PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_NEGATE_CFGr                   = 2586,
-    PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_ASSERT_CFGr                   = 2587,
-    PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_NEGATE_CFGr                   = 2588,
-    PPU_CLUSTER_INT_600M_CLUSTER_MEX_FIFO_MASKr                           = 2589,
-    PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_FLAGr                     = 2590,
-    PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_STAr                      = 2591,
-    PPU_CLUSTER_MEX_CNT_CFGr                                              = 2592,
-    PPU_CLUSTER_INT_600M_CLUSTER_MEX_RAM_ECC_ERROR_INTERRUPT_MASKr        = 2593,
-    PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_FLAGr            = 2594,
-    PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_STAr             = 2595,
-    PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_ASSERT_CFGr             = 2596,
-    PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_NEGATE_CFGr             = 2597,
-    PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_ASSERT_CFGr                       = 2598,
-    PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_NEGATE_CFGr                       = 2599,
-    PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_ASSERT_CFGr                       = 2600,
-    PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_NEGATE_CFGr                       = 2601,
-    PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_ASSERT_CFGr                       = 2602,
-    PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_NEGATE_CFGr                       = 2603,
-    PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr                  = 2604,
-    PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr                  = 2605,
-    PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr                  = 2606,
-    PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr                  = 2607,
-    PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr                  = 2608,
-    PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr                  = 2609,
-    PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_Hr                                 = 2610,
-    PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_Lr                                 = 2611,
-    PPU_CLUSTER_CLUSTER_ISE_KEY_OUT_VLD_CNTr                              = 2612,
-    PPU_CLUSTER_ISE_CLUSTER_RSP_IN_VLD_CNTr                               = 2613,
-    PPU_CLUSTER_CLUSTER_ESE_KEY_OUT_VLD_CNTr                              = 2614,
-    PPU_CLUSTER_ESE_CLUSTER_RSP_IN_VLD_CNTr                               = 2615,
-    PPU_CLUSTER_CLUSTER_STAT_CMD_VLD_CNTr                                 = 2616,
-    PPU_CLUSTER_STAT_CLUSTER_RSP_VLD_CNTr                                 = 2617,
-    PPU_CLUSTER_MEX_DEBUG_KEY_VLD_CNTr                                    = 2618,
-    PPU_CLUSTER_ISE_CLUSTER_KEY_FC_CNTr                                   = 2619,
-    PPU_CLUSTER_ESE_CLUSTER_KEY_FC_CNTr                                   = 2620,
-    PPU_CLUSTER_CLUSTER_ISE_RSP_FC_CNTr                                   = 2621,
-    PPU_CLUSTER_CLUSTER_ESE_RSP_FC_CNTr                                   = 2622,
-    PPU_CLUSTER_STAT_CLUSTER_CMD_FC_CNTr                                  = 2623,
-    PPU_CLUSTER_CLUSTER_STAT_RSP_FC_CNTr                                  = 2624,
-    PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_Lr                                 = 2625,
-    PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_Hr                                 = 2626,
-    PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_Lr                                = 2627,
-    PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_Hr                                = 2628,
-    PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_Lr                                = 2629,
-    PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_Hr                                = 2630,
-    PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_Lr                                  = 2631,
-    PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_Hr                                  = 2632,
-    PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_Lr                                  = 2633,
-    PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_Hr                                  = 2634,
-    PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_Lr                                  = 2635,
-    PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_Hr                                  = 2636,
-    PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_Lr                                 = 2637,
-    PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_Hr                                 = 2638,
-    PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_Lr                                 = 2639,
-    PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_Hr                                 = 2640,
-    PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_Lr                                 = 2641,
-    PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_Hr                                 = 2642,
-    PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_Lr                               = 2643,
-    PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_Hr                               = 2644,
-    PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_Lr                               = 2645,
-    PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_Hr                               = 2646,
-    PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_Lr                               = 2647,
-    PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_Hr                               = 2648,
-    PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_Lr                               = 2649,
-    PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_Hr                               = 2650,
-    PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_Lr                               = 2651,
-    PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_Hr                               = 2652,
-    PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_Lr                               = 2653,
-    PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_Hr                               = 2654,
-    PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_Lr                           = 2655,
-    PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_Hr                           = 2656,
-    PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_Lr                           = 2657,
-    PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_Hr                           = 2658,
-    PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_Lr                           = 2659,
-    PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_Hr                           = 2660,
-    PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_Lr                           = 2661,
-    PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_Hr                           = 2662,
-    PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_Lr                           = 2663,
-    PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_Hr                           = 2664,
-    PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_Lr                           = 2665,
-    PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_Hr                           = 2666,
-    PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_Lr                           = 2667,
-    PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_Hr                           = 2668,
-    PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_Lr                           = 2669,
-    PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_Hr                           = 2670,
-    PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_Lr                                 = 2671,
-    PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_Hr                                 = 2672,
-    PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_Lr                                 = 2673,
-    PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_Hr                                 = 2674,
-    PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_Lr                                 = 2675,
-    PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_Hr                                 = 2676,
-    PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_Lr                                 = 2677,
-    PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_Hr                                 = 2678,
-    PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_Lr                                 = 2679,
-    PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_Hr                                 = 2680,
-    PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_Lr                                 = 2681,
-    PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_Hr                                 = 2682,
-    SE_CFG_PPU_SOFT_RSTr                                                  = 2683,
-    SE_CFG_EPT_FLAGr                                                      = 2684,
-    SE_CFG_DDR_KEY_LK0_3r                                                 = 2685,
-    SE_CFG_DDR_KEY_LK0_2r                                                 = 2686,
-    SE_CFG_DDR_KEY_LK0_1r                                                 = 2687,
-    SE_CFG_DDR_KEY_LK0_0r                                                 = 2688,
-    SE_CFG_DDR_KEY_LK1_3r                                                 = 2689,
-    SE_CFG_DDR_KEY_LK1_2r                                                 = 2690,
-    SE_CFG_DDR_KEY_LK1_1r                                                 = 2691,
-    SE_CFG_DDR_KEY_LK1_0r                                                 = 2692,
-    SE_CFG_HASH_KEY_LK0_18r                                               = 2693,
-    SE_CFG_HASH_KEY_LK0_17r                                               = 2694,
-    SE_CFG_HASH_KEY_LK0_16r                                               = 2695,
-    SE_CFG_HASH_KEY_LK0_15r                                               = 2696,
-    SE_CFG_HASH_KEY_LK0_14r                                               = 2697,
-    SE_CFG_HASH_KEY_LK0_13r                                               = 2698,
-    SE_CFG_HASH_KEY_LK0_12r                                               = 2699,
-    SE_CFG_HASH_KEY_LK0_11r                                               = 2700,
-    SE_CFG_HASH_KEY_LK0_10r                                               = 2701,
-    SE_CFG_HASH_KEY_LK0_9r                                                = 2702,
-    SE_CFG_HASH_KEY_LK0_8r                                                = 2703,
-    SE_CFG_HASH_KEY_LK0_7r                                                = 2704,
-    SE_CFG_HASH_KEY_LK0_6r                                                = 2705,
-    SE_CFG_HASH_KEY_LK0_5r                                                = 2706,
-    SE_CFG_HASH_KEY_LK0_4r                                                = 2707,
-    SE_CFG_HASH_KEY_LK0_3r                                                = 2708,
-    SE_CFG_HASH_KEY_LK0_2r                                                = 2709,
-    SE_CFG_HASH_KEY_LK0_1r                                                = 2710,
-    SE_CFG_HASH_KEY_LK0_0r                                                = 2711,
-    SE_CFG_HASH_KEY_LK1_18r                                               = 2712,
-    SE_CFG_HASH_KEY_LK1_17r                                               = 2713,
-    SE_CFG_HASH_KEY_LK1_16r                                               = 2714,
-    SE_CFG_HASH_KEY_LK1_15r                                               = 2715,
-    SE_CFG_HASH_KEY_LK1_14r                                               = 2716,
-    SE_CFG_HASH_KEY_LK1_13r                                               = 2717,
-    SE_CFG_HASH_KEY_LK1_12r                                               = 2718,
-    SE_CFG_HASH_KEY_LK1_11r                                               = 2719,
-    SE_CFG_HASH_KEY_LK1_10r                                               = 2720,
-    SE_CFG_HASH_KEY_LK1_9r                                                = 2721,
-    SE_CFG_HASH_KEY_LK1_8r                                                = 2722,
-    SE_CFG_HASH_KEY_LK1_7r                                                = 2723,
-    SE_CFG_HASH_KEY_LK1_6r                                                = 2724,
-    SE_CFG_HASH_KEY_LK1_5r                                                = 2725,
-    SE_CFG_HASH_KEY_LK1_4r                                                = 2726,
-    SE_CFG_HASH_KEY_LK1_3r                                                = 2727,
-    SE_CFG_HASH_KEY_LK1_2r                                                = 2728,
-    SE_CFG_HASH_KEY_LK1_1r                                                = 2729,
-    SE_CFG_HASH_KEY_LK1_0r                                                = 2730,
-    SE_CFG_HASH_KEY_LK2_18r                                               = 2731,
-    SE_CFG_HASH_KEY_LK2_17r                                               = 2732,
-    SE_CFG_HASH_KEY_LK2_16r                                               = 2733,
-    SE_CFG_HASH_KEY_LK2_15r                                               = 2734,
-    SE_CFG_HASH_KEY_LK2_14r                                               = 2735,
-    SE_CFG_HASH_KEY_LK2_13r                                               = 2736,
-    SE_CFG_HASH_KEY_LK2_12r                                               = 2737,
-    SE_CFG_HASH_KEY_LK2_11r                                               = 2738,
-    SE_CFG_HASH_KEY_LK2_10r                                               = 2739,
-    SE_CFG_HASH_KEY_LK2_9r                                                = 2740,
-    SE_CFG_HASH_KEY_LK2_8r                                                = 2741,
-    SE_CFG_HASH_KEY_LK2_7r                                                = 2742,
-    SE_CFG_HASH_KEY_LK2_6r                                                = 2743,
-    SE_CFG_HASH_KEY_LK2_5r                                                = 2744,
-    SE_CFG_HASH_KEY_LK2_4r                                                = 2745,
-    SE_CFG_HASH_KEY_LK2_3r                                                = 2746,
-    SE_CFG_HASH_KEY_LK2_2r                                                = 2747,
-    SE_CFG_HASH_KEY_LK2_1r                                                = 2748,
-    SE_CFG_HASH_KEY_LK2_0r                                                = 2749,
-    SE_CFG_HASH_KEY_LK3_18r                                               = 2750,
-    SE_CFG_HASH_KEY_LK3_17r                                               = 2751,
-    SE_CFG_HASH_KEY_LK3_16r                                               = 2752,
-    SE_CFG_HASH_KEY_LK3_15r                                               = 2753,
-    SE_CFG_HASH_KEY_LK3_14r                                               = 2754,
-    SE_CFG_HASH_KEY_LK3_13r                                               = 2755,
-    SE_CFG_HASH_KEY_LK3_12r                                               = 2756,
-    SE_CFG_HASH_KEY_LK3_11r                                               = 2757,
-    SE_CFG_HASH_KEY_LK3_10r                                               = 2758,
-    SE_CFG_HASH_KEY_LK3_9r                                                = 2759,
-    SE_CFG_HASH_KEY_LK3_8r                                                = 2760,
-    SE_CFG_HASH_KEY_LK3_7r                                                = 2761,
-    SE_CFG_HASH_KEY_LK3_6r                                                = 2762,
-    SE_CFG_HASH_KEY_LK3_5r                                                = 2763,
-    SE_CFG_HASH_KEY_LK3_4r                                                = 2764,
-    SE_CFG_HASH_KEY_LK3_3r                                                = 2765,
-    SE_CFG_HASH_KEY_LK3_2r                                                = 2766,
-    SE_CFG_HASH_KEY_LK3_1r                                                = 2767,
-    SE_CFG_HASH_KEY_LK3_0r                                                = 2768,
-    SE_CFG_LPM_KEY_LK0_6r                                                 = 2769,
-    SE_CFG_LPM_KEY_LK0_5r                                                 = 2770,
-    SE_CFG_LPM_KEY_LK0_4r                                                 = 2771,
-    SE_CFG_LPM_KEY_LK0_3r                                                 = 2772,
-    SE_CFG_LPM_KEY_LK0_2r                                                 = 2773,
-    SE_CFG_LPM_KEY_LK0_1r                                                 = 2774,
-    SE_CFG_LPM_KEY_LK0_0r                                                 = 2775,
-    SE_CFG_LPM_KEY_LK1_6r                                                 = 2776,
-    SE_CFG_LPM_KEY_LK1_5r                                                 = 2777,
-    SE_CFG_LPM_KEY_LK1_4r                                                 = 2778,
-    SE_CFG_LPM_KEY_LK1_3r                                                 = 2779,
-    SE_CFG_LPM_KEY_LK1_2r                                                 = 2780,
-    SE_CFG_LPM_KEY_LK1_1r                                                 = 2781,
-    SE_CFG_LPM_KEY_LK1_0r                                                 = 2782,
-    SE_CFG_LPM_KEY_LK2_6r                                                 = 2783,
-    SE_CFG_LPM_KEY_LK2_5r                                                 = 2784,
-    SE_CFG_LPM_KEY_LK2_4r                                                 = 2785,
-    SE_CFG_LPM_KEY_LK2_3r                                                 = 2786,
-    SE_CFG_LPM_KEY_LK2_2r                                                 = 2787,
-    SE_CFG_LPM_KEY_LK2_1r                                                 = 2788,
-    SE_CFG_LPM_KEY_LK2_0r                                                 = 2789,
-    SE_CFG_LPM_KEY_LK3_6r                                                 = 2790,
-    SE_CFG_LPM_KEY_LK3_5r                                                 = 2791,
-    SE_CFG_LPM_KEY_LK3_4r                                                 = 2792,
-    SE_CFG_LPM_KEY_LK3_3r                                                 = 2793,
-    SE_CFG_LPM_KEY_LK3_2r                                                 = 2794,
-    SE_CFG_LPM_KEY_LK3_1r                                                 = 2795,
-    SE_CFG_LPM_KEY_LK3_0r                                                 = 2796,
-    SE_CFG_ETCAM_KEY_LK0_22r                                              = 2797,
-    SE_CFG_ETCAM_KEY_LK0_21r                                              = 2798,
-    SE_CFG_ETCAM_KEY_LK0_20r                                              = 2799,
-    SE_CFG_ETCAM_KEY_LK0_19r                                              = 2800,
-    SE_CFG_ETCAM_KEY_LK0_18r                                              = 2801,
-    SE_CFG_ETCAM_KEY_LK0_17r                                              = 2802,
-    SE_CFG_ETCAM_KEY_LK0_16r                                              = 2803,
-    SE_CFG_ETCAM_KEY_LK0_15r                                              = 2804,
-    SE_CFG_ETCAM_KEY_LK0_14r                                              = 2805,
-    SE_CFG_ETCAM_KEY_LK0_13r                                              = 2806,
-    SE_CFG_ETCAM_KEY_LK0_12r                                              = 2807,
-    SE_CFG_ETCAM_KEY_LK0_11r                                              = 2808,
-    SE_CFG_ETCAM_KEY_LK0_10r                                              = 2809,
-    SE_CFG_ETCAM_KEY_LK0_9r                                               = 2810,
-    SE_CFG_ETCAM_KEY_LK0_8r                                               = 2811,
-    SE_CFG_ETCAM_KEY_LK0_7r                                               = 2812,
-    SE_CFG_ETCAM_KEY_LK0_6r                                               = 2813,
-    SE_CFG_ETCAM_KEY_LK0_5r                                               = 2814,
-    SE_CFG_ETCAM_KEY_LK0_4r                                               = 2815,
-    SE_CFG_ETCAM_KEY_LK0_3r                                               = 2816,
-    SE_CFG_ETCAM_KEY_LK0_2r                                               = 2817,
-    SE_CFG_ETCAM_KEY_LK0_1r                                               = 2818,
-    SE_CFG_ETCAM_KEY_LK0_0r                                               = 2819,
-    SE_CFG_ETCAM_KEY_LK1_22r                                              = 2820,
-    SE_CFG_ETCAM_KEY_LK1_21r                                              = 2821,
-    SE_CFG_ETCAM_KEY_LK1_20r                                              = 2822,
-    SE_CFG_ETCAM_KEY_LK1_19r                                              = 2823,
-    SE_CFG_ETCAM_KEY_LK1_18r                                              = 2824,
-    SE_CFG_ETCAM_KEY_LK1_17r                                              = 2825,
-    SE_CFG_ETCAM_KEY_LK1_16r                                              = 2826,
-    SE_CFG_ETCAM_KEY_LK1_15r                                              = 2827,
-    SE_CFG_ETCAM_KEY_LK1_14r                                              = 2828,
-    SE_CFG_ETCAM_KEY_LK1_13r                                              = 2829,
-    SE_CFG_ETCAM_KEY_LK1_12r                                              = 2830,
-    SE_CFG_ETCAM_KEY_LK1_11r                                              = 2831,
-    SE_CFG_ETCAM_KEY_LK1_10r                                              = 2832,
-    SE_CFG_ETCAM_KEY_LK1_9r                                               = 2833,
-    SE_CFG_ETCAM_KEY_LK1_8r                                               = 2834,
-    SE_CFG_ETCAM_KEY_LK1_7r                                               = 2835,
-    SE_CFG_ETCAM_KEY_LK1_6r                                               = 2836,
-    SE_CFG_ETCAM_KEY_LK1_5r                                               = 2837,
-    SE_CFG_ETCAM_KEY_LK1_4r                                               = 2838,
-    SE_CFG_ETCAM_KEY_LK1_3r                                               = 2839,
-    SE_CFG_ETCAM_KEY_LK1_2r                                               = 2840,
-    SE_CFG_ETCAM_KEY_LK1_1r                                               = 2841,
-    SE_CFG_ETCAM_KEY_LK1_0r                                               = 2842,
-    SE_CFG_ETCAM_KEY_LK2_22r                                              = 2843,
-    SE_CFG_ETCAM_KEY_LK2_21r                                              = 2844,
-    SE_CFG_ETCAM_KEY_LK2_20r                                              = 2845,
-    SE_CFG_ETCAM_KEY_LK2_19r                                              = 2846,
-    SE_CFG_ETCAM_KEY_LK2_18r                                              = 2847,
-    SE_CFG_ETCAM_KEY_LK2_17r                                              = 2848,
-    SE_CFG_ETCAM_KEY_LK2_16r                                              = 2849,
-    SE_CFG_ETCAM_KEY_LK2_15r                                              = 2850,
-    SE_CFG_ETCAM_KEY_LK2_14r                                              = 2851,
-    SE_CFG_ETCAM_KEY_LK2_13r                                              = 2852,
-    SE_CFG_ETCAM_KEY_LK2_12r                                              = 2853,
-    SE_CFG_ETCAM_KEY_LK2_11r                                              = 2854,
-    SE_CFG_ETCAM_KEY_LK2_10r                                              = 2855,
-    SE_CFG_ETCAM_KEY_LK2_9r                                               = 2856,
-    SE_CFG_ETCAM_KEY_LK2_8r                                               = 2857,
-    SE_CFG_ETCAM_KEY_LK2_7r                                               = 2858,
-    SE_CFG_ETCAM_KEY_LK2_6r                                               = 2859,
-    SE_CFG_ETCAM_KEY_LK2_5r                                               = 2860,
-    SE_CFG_ETCAM_KEY_LK2_4r                                               = 2861,
-    SE_CFG_ETCAM_KEY_LK2_3r                                               = 2862,
-    SE_CFG_ETCAM_KEY_LK2_2r                                               = 2863,
-    SE_CFG_ETCAM_KEY_LK2_1r                                               = 2864,
-    SE_CFG_ETCAM_KEY_LK2_0r                                               = 2865,
-    SE_CFG_ETCAM_KEY_LK3_22r                                              = 2866,
-    SE_CFG_ETCAM_KEY_LK3_21r                                              = 2867,
-    SE_CFG_ETCAM_KEY_LK3_20r                                              = 2868,
-    SE_CFG_ETCAM_KEY_LK3_19r                                              = 2869,
-    SE_CFG_ETCAM_KEY_LK3_18r                                              = 2870,
-    SE_CFG_ETCAM_KEY_LK3_17r                                              = 2871,
-    SE_CFG_ETCAM_KEY_LK3_16r                                              = 2872,
-    SE_CFG_ETCAM_KEY_LK3_15r                                              = 2873,
-    SE_CFG_ETCAM_KEY_LK3_14r                                              = 2874,
-    SE_CFG_ETCAM_KEY_LK3_13r                                              = 2875,
-    SE_CFG_ETCAM_KEY_LK3_12r                                              = 2876,
-    SE_CFG_ETCAM_KEY_LK3_11r                                              = 2877,
-    SE_CFG_ETCAM_KEY_LK3_10r                                              = 2878,
-    SE_CFG_ETCAM_KEY_LK3_9r                                               = 2879,
-    SE_CFG_ETCAM_KEY_LK3_8r                                               = 2880,
-    SE_CFG_ETCAM_KEY_LK3_7r                                               = 2881,
-    SE_CFG_ETCAM_KEY_LK3_6r                                               = 2882,
-    SE_CFG_ETCAM_KEY_LK3_5r                                               = 2883,
-    SE_CFG_ETCAM_KEY_LK3_4r                                               = 2884,
-    SE_CFG_ETCAM_KEY_LK3_3r                                               = 2885,
-    SE_CFG_ETCAM_KEY_LK3_2r                                               = 2886,
-    SE_CFG_ETCAM_KEY_LK3_1r                                               = 2887,
-    SE_CFG_ETCAM_KEY_LK3_0r                                               = 2888,
-    SE_CFG_PBU_KEY_LK0_3r                                                 = 2889,
-    SE_CFG_PBU_KEY_LK0_2r                                                 = 2890,
-    SE_CFG_PBU_KEY_LK0_1r                                                 = 2891,
-    SE_CFG_PBU_KEY_LK0_0r                                                 = 2892,
-    SE_CFG_PBU_KEY_LK1_3r                                                 = 2893,
-    SE_CFG_PBU_KEY_LK1_2r                                                 = 2894,
-    SE_CFG_PBU_KEY_LK1_1r                                                 = 2895,
-    SE_CFG_PBU_KEY_LK1_0r                                                 = 2896,
-    SE_CFG_PBU_KEY_LK2_3r                                                 = 2897,
-    SE_CFG_PBU_KEY_LK2_2r                                                 = 2898,
-    SE_CFG_PBU_KEY_LK2_1r                                                 = 2899,
-    SE_CFG_PBU_KEY_LK2_0r                                                 = 2900,
-    SE_CFG_PBU_KEY_LK3_3r                                                 = 2901,
-    SE_CFG_PBU_KEY_LK3_2r                                                 = 2902,
-    SE_CFG_PBU_KEY_LK3_1r                                                 = 2903,
-    SE_CFG_PBU_KEY_LK3_0r                                                 = 2904,
-    SE_ALG_SCHD_LEARN_FIFO_PFULL_ASTr                                     = 2905,
-    SE_ALG_SCHD_LEARN_FIFO_PFULL_NEGr                                     = 2906,
-    SE_ALG_SCHD_HASH0_FIFO_PFULL_ASTr                                     = 2907,
-    SE_ALG_SCHD_HASH0_FIFO_PFULL_NEGr                                     = 2908,
-    SE_ALG_SCHD_HASH1_FIFO_PFULL_ASTr                                     = 2909,
-    SE_ALG_SCHD_HASH1_FIFO_PFULL_NEGr                                     = 2910,
-    SE_ALG_SCHD_HASH2_FIFO_PFULL_ASTr                                     = 2911,
-    SE_ALG_SCHD_HASH2_FIFO_PFULL_NEGr                                     = 2912,
-    SE_ALG_SCHD_HASH3_FIFO_PFULL_ASTr                                     = 2913,
-    SE_ALG_SCHD_HASH3_FIFO_PFULL_NEGr                                     = 2914,
-    SE_ALG_SCHD_LPM_FIFO_PFULL_ASTr                                       = 2915,
-    SE_ALG_SCHD_LPM_FIFO_PFULL_NEGr                                       = 2916,
-    SE_ALG_HASH0_KEY_FIFO_PFULL_ASTr                                      = 2917,
-    SE_ALG_HASH0_KEY_FIFO_PFULL_NEGr                                      = 2918,
-    SE_ALG_HASH0_SREQ_FIFO_PFULL_ASTr                                     = 2919,
-    SE_ALG_HASH0_SREQ_FIFO_PFULL_NEGr                                     = 2920,
-    SE_ALG_HASH0_INT_RSP_FIFO_PFULL_ASTr                                  = 2921,
-    SE_ALG_HASH0_INT_RSP_FIFO_PFULL_NEGr                                  = 2922,
-    SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_ASTr                                  = 2923,
-    SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_NEGr                                  = 2924,
-    SE_ALG_HASH1_KEY_FIFO_PFULL_ASTr                                      = 2925,
-    SE_ALG_HASH1_KEY_FIFO_PFULL_NEGr                                      = 2926,
-    SE_ALG_HASH1_SREQ_FIFO_PFULL_ASTr                                     = 2927,
-    SE_ALG_HASH1_SREQ_FIFO_PFULL_NEGr                                     = 2928,
-    SE_ALG_HASH1_INT_RSP_FIFO_PFULL_ASTr                                  = 2929,
-    SE_ALG_HASH1_INT_RSP_FIFO_PFULL_NEGr                                  = 2930,
-    SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_ASTr                                  = 2931,
-    SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_NEGr                                  = 2932,
-    SE_ALG_HASH2_KEY_FIFO_PFULL_ASTr                                      = 2933,
-    SE_ALG_HASH2_KEY_FIFO_PFULL_NEGr                                      = 2934,
-    SE_ALG_HASH2_SREQ_FIFO_PFULL_ASTr                                     = 2935,
-    SE_ALG_HASH2_SREQ_FIFO_PFULL_NEGr                                     = 2936,
-    SE_ALG_HASH2_INT_RSP_FIFO_PFULL_ASTr                                  = 2937,
-    SE_ALG_HASH2_INT_RSP_FIFO_PFULL_NEGr                                  = 2938,
-    SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_ASTr                                  = 2939,
-    SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_NEGr                                  = 2940,
-    SE_ALG_HASH3_KEY_FIFO_PFULL_ASTr                                      = 2941,
-    SE_ALG_HASH3_KEY_FIFO_PFULL_NEGr                                      = 2942,
-    SE_ALG_HASH3_SREQ_FIFO_PFULL_ASTr                                     = 2943,
-    SE_ALG_HASH3_SREQ_FIFO_PFULL_NEGr                                     = 2944,
-    SE_ALG_HASH3_INT_RSP_FIFO_PFULL_ASTr                                  = 2945,
-    SE_ALG_HASH3_INT_RSP_FIFO_PFULL_NEGr                                  = 2946,
-    SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_ASTr                                  = 2947,
-    SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_NEGr                                  = 2948,
-    SE_ALG_LPM_AS_INFOr                                                   = 2949,
-    SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_NEGr                                 = 2950,
-    SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_ASTr                                 = 2951,
-    SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_NEGr                                 = 2952,
-    SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_ASTr                                 = 2953,
-    SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_NEGr                                 = 2954,
-    SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_ASTr                                 = 2955,
-    SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_NEGr                                 = 2956,
-    SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_ASTr                                  = 2957,
-    SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_NEGr                                  = 2958,
-    SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_ASTr                                  = 2959,
-    SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_NEGr                                  = 2960,
-    SE_ALG_LPM_V4_DDR3_BASE_ADDRr                                         = 2961,
-    SE_ALG_LPM_V6_DDR3_BASE_ADDRr                                         = 2962,
-    SE_ALG_DEBUG_CNT_MODEr                                                = 2963,
-    SE_ALG_HASH_P0_KEY_VLD_CNTr                                           = 2964,
-    SE_ALG_HASH_P1_KEY_VLD_CNTr                                           = 2965,
-    SE_ALG_HASH_P2_KEY_VLD_CNTr                                           = 2966,
-    SE_ALG_HASH_P3_KEY_VLD_CNTr                                           = 2967,
-    SE_ALG_LPM_P0_KEY_VLD_CNTr                                            = 2968,
-    SE_ALG_HASH_P0_RSP_VLD_CNTr                                           = 2969,
-    SE_ALG_HASH_P1_RSP_VLD_CNTr                                           = 2970,
-    SE_ALG_HASH_P2_RSP_VLD_CNTr                                           = 2971,
-    SE_ALG_HASH_P3_RSP_VLD_CNTr                                           = 2972,
-    SE_ALG_LPM_P0_RSP_VLD_CNTr                                            = 2973,
-    SE_ALG_HASH_P0_SMF_CNTr                                               = 2974,
-    SE_ALG_HASH_P1_SMF_CNTr                                               = 2975,
-    SE_ALG_HASH_P2_SMF_CNTr                                               = 2976,
-    SE_ALG_HASH_P3_SMF_CNTr                                               = 2977,
-    SE_ALG_LPM_P0_SMF_CNTr                                                = 2978,
-    SE_ALG_HASH_P0_SPACEVLD_CNTr                                          = 2979,
-    SE_ALG_HASH_P1_SPACEVLD_CNTr                                          = 2980,
-    SE_ALG_HASH_P2_SPACEVLD_CNTr                                          = 2981,
-    SE_ALG_HASH_P3_SPACEVLD_CNTr                                          = 2982,
-    SE_ALG_SMMU1_P0_REQ_VLD_CNTr                                          = 2983,
-    SE_ALG_SMMU1_P1_REQ_VLD_CNTr                                          = 2984,
-    SE_ALG_SMMU1_P2_REQ_VLD_CNTr                                          = 2985,
-    SE_ALG_SMMU1_P3_REQ_VLD_CNTr                                          = 2986,
-    SE_ALG_SMMU1_P4_REQ_VLD_CNTr                                          = 2987,
-    SE_ALG_SMMU1_P5_REQ_VLD_CNTr                                          = 2988,
-    SE_ALG_SMMU1_P0_RSP_VLD_CNTr                                          = 2989,
-    SE_ALG_SMMU1_P1_RSP_VLD_CNTr                                          = 2990,
-    SE_ALG_SMMU1_P2_RSP_VLD_CNTr                                          = 2991,
-    SE_ALG_SMMU1_P3_RSP_VLD_CNTr                                          = 2992,
-    SE_ALG_SMMU1_P4_RSP_VLD_CNTr                                          = 2993,
-    SE_ALG_SMMU1_P5_RSP_VLD_CNTr                                          = 2994,
-    SE_ALG_SCHD_LEARN_FIFO_INT_CNTr                                       = 2995,
-    SE_ALG_SCHD_HASH0_FIFO_INT_CNTr                                       = 2996,
-    SE_ALG_SCHD_HASH1_FIFO_INT_CNTr                                       = 2997,
-    SE_ALG_SCHD_HASH2_FIFO_INT_CNTr                                       = 2998,
-    SE_ALG_SCHD_HASH3_FIFO_INT_CNTr                                       = 2999,
-    SE_ALG_SCHD_LPM_FIFO_INT_CNTr                                         = 3000,
-    SE_ALG_SCHD_LEARN_FIFO_PARITY_ERR_CNTr                                = 3001,
-    SE_ALG_SCHD_HASH0_FIFO_PARITY_ERR_CNTr                                = 3002,
-    SE_ALG_SCHD_HASH1_FIFO_PARITY_ERR_CNTr                                = 3003,
-    SE_ALG_SCHD_HASH2_FIFO_PARITY_ERR_CNTr                                = 3004,
-    SE_ALG_SCHD_HASH3_FIFO_PARITY_ERR_CNTr                                = 3005,
-    SE_ALG_SCHD_LPM_FIFO_PARITY_ERR_CNTr                                  = 3006,
-    SE_ALG_RD_INIT_CFT_CNTr                                               = 3007,
-    SE_ALG_ZGP0_ZBLK0_ECC_ERR_CNTr                                        = 3008,
-    SE_ALG_ZGP0_ZBLK1_ECC_ERR_CNTr                                        = 3009,
-    SE_ALG_ZGP0_ZBLK2_ECC_ERR_CNTr                                        = 3010,
-    SE_ALG_ZGP0_ZBLK3_ECC_ERR_CNTr                                        = 3011,
-    SE_ALG_ZGP0_ZBLK4_ECC_ERR_CNTr                                        = 3012,
-    SE_ALG_ZGP0_ZBLK5_ECC_ERR_CNTr                                        = 3013,
-    SE_ALG_ZGP0_ZBLK6_ECC_ERR_CNTr                                        = 3014,
-    SE_ALG_ZGP0_ZBLK7_ECC_ERR_CNTr                                        = 3015,
-    SE_ALG_ZGP1_ZBLK0_ECC_ERR_CNTr                                        = 3016,
-    SE_ALG_ZGP1_ZBLK1_ECC_ERR_CNTr                                        = 3017,
-    SE_ALG_ZGP1_ZBLK2_ECC_ERR_CNTr                                        = 3018,
-    SE_ALG_ZGP1_ZBLK3_ECC_ERR_CNTr                                        = 3019,
-    SE_ALG_ZGP1_ZBLK4_ECC_ERR_CNTr                                        = 3020,
-    SE_ALG_ZGP1_ZBLK5_ECC_ERR_CNTr                                        = 3021,
-    SE_ALG_ZGP1_ZBLK6_ECC_ERR_CNTr                                        = 3022,
-    SE_ALG_ZGP1_ZBLK7_ECC_ERR_CNTr                                        = 3023,
-    SE_ALG_ZGP2_ZBLK0_ECC_ERR_CNTr                                        = 3024,
-    SE_ALG_ZGP2_ZBLK1_ECC_ERR_CNTr                                        = 3025,
-    SE_ALG_ZGP2_ZBLK2_ECC_ERR_CNTr                                        = 3026,
-    SE_ALG_ZGP2_ZBLK3_ECC_ERR_CNTr                                        = 3027,
-    SE_ALG_ZGP2_ZBLK4_ECC_ERR_CNTr                                        = 3028,
-    SE_ALG_ZGP2_ZBLK5_ECC_ERR_CNTr                                        = 3029,
-    SE_ALG_ZGP2_ZBLK6_ECC_ERR_CNTr                                        = 3030,
-    SE_ALG_ZGP2_ZBLK7_ECC_ERR_CNTr                                        = 3031,
-    SE_ALG_ZGP3_ZBLK0_ECC_ERR_CNTr                                        = 3032,
-    SE_ALG_ZGP3_ZBLK1_ECC_ERR_CNTr                                        = 3033,
-    SE_ALG_ZGP3_ZBLK2_ECC_ERR_CNTr                                        = 3034,
-    SE_ALG_ZGP3_ZBLK3_ECC_ERR_CNTr                                        = 3035,
-    SE_ALG_ZGP3_ZBLK4_ECC_ERR_CNTr                                        = 3036,
-    SE_ALG_ZGP3_ZBLK5_ECC_ERR_CNTr                                        = 3037,
-    SE_ALG_ZGP3_ZBLK6_ECC_ERR_CNTr                                        = 3038,
-    SE_ALG_ZGP3_ZBLK7_ECC_ERR_CNTr                                        = 3039,
-    SE_ALG_ZCAM_HASH_P0_ERR_CNTr                                          = 3040,
-    SE_ALG_ZCAM_HASH_P1_ERR_CNTr                                          = 3041,
-    SE_ALG_ZCAM_HASH_P2_ERR_CNTr                                          = 3042,
-    SE_ALG_ZCAM_HASH_P3_ERR_CNTr                                          = 3043,
-    SE_ALG_ZCAM_LPM_ERR_CNTr                                              = 3044,
-    SE_ALG_HASH0_SREQ_FIFO_PARITY_ERR_CNTr                                = 3045,
-    SE_ALG_HASH0_SREQ_FIFO_INT_CNTr                                       = 3046,
-    SE_ALG_HASH0_KEY_FIFO_INT_CNTr                                        = 3047,
-    SE_ALG_HASH0_INT_RSP_FIFO_PARITY_ERR_CNTr                             = 3048,
-    SE_ALG_HASH0_EXT_RSP_FIFO_PARITY_ERR_CNTr                             = 3049,
-    SE_ALG_HASH0_EXT_RSP_FIFO_INT_CNTr                                    = 3050,
-    SE_ALG_HASH0_INT_RSP_FIFO_INT_CNTr                                    = 3051,
-    SE_ALG_HASH1_SREQ_FIFO_PARITY_ERR_CNTr                                = 3052,
-    SE_ALG_HASH1_SREQ_FIFO_INT_CNTr                                       = 3053,
-    SE_ALG_HASH1_KEY_FIFO_INT_CNTr                                        = 3054,
-    SE_ALG_HASH1_INT_RSP_FIFO_PARITY_ERR_CNTr                             = 3055,
-    SE_ALG_HASH1_EXT_RSP_FIFO_PARITY_ERR_CNTr                             = 3056,
-    SE_ALG_HASH1_EXT_RSP_FIFO_INT_CNTr                                    = 3057,
-    SE_ALG_HASH1_INT_RSP_FIFO_INT_CNTr                                    = 3058,
-    SE_ALG_HASH2_SREQ_FIFO_PARITY_ERR_CNTr                                = 3059,
-    SE_ALG_HASH2_SREQ_FIFO_INT_CNTr                                       = 3060,
-    SE_ALG_HASH2_KEY_FIFO_INT_CNTr                                        = 3061,
-    SE_ALG_HASH2_INT_RSP_FIFO_PARITY_ERR_CNTr                             = 3062,
-    SE_ALG_HASH2_EXT_RSP_FIFO_PARITY_ERR_CNTr                             = 3063,
-    SE_ALG_HASH2_EXT_RSP_FIFO_INT_CNTr                                    = 3064,
-    SE_ALG_HASH2_INT_RSP_FIFO_INT_CNTr                                    = 3065,
-    SE_ALG_HASH3_SREQ_FIFO_PARITY_ERR_CNTr                                = 3066,
-    SE_ALG_HASH3_SREQ_FIFO_INT_CNTr                                       = 3067,
-    SE_ALG_HASH3_KEY_FIFO_INT_CNTr                                        = 3068,
-    SE_ALG_HASH3_INT_RSP_FIFO_PARITY_ERR_CNTr                             = 3069,
-    SE_ALG_HASH3_EXT_RSP_FIFO_PARITY_ERR_CNTr                             = 3070,
-    SE_ALG_HASH3_EXT_RSP_FIFO_INT_CNTr                                    = 3071,
-    SE_ALG_HASH3_INT_RSP_FIFO_INT_CNTr                                    = 3072,
-    SE_ALG_LPM_EXT_RSP_FIFO_INT_CNTr                                      = 3073,
-    SE_ALG_LPM_EXT_V6_FIFO_INT_CNTr                                       = 3074,
-    SE_ALG_LPM_EXT_V4_FIFO_INT_CNTr                                       = 3075,
-    SE_ALG_LPM_EXT_ADDR_FIFO_INT_CNTr                                     = 3076,
-    SE_ALG_LPM_EXT_V4_FIFO_PARITY_ERR_CNTr                                = 3077,
-    SE_ALG_LPM_EXT_V6_FIFO_PARITY_ERR_CNTr                                = 3078,
-    SE_ALG_LPM_EXT_RSP_FIFO_PARITY_ERR_CNTr                               = 3079,
-    SE_ALG_LPM_AS_REQ_FIFO_INT_CNTr                                       = 3080,
-    SE_ALG_LPM_AS_INT_RSP_FIFO_INT_CNTr                                   = 3081,
-    SE_ALG_SE_ALG_INT_STATUSr                                             = 3082,
-    SE_ALG_SCHD_INT_ENr                                                   = 3083,
-    SE_ALG_SCHD_INT_MASKr                                                 = 3084,
-    SE_ALG_SCHD_INT_STATUSr                                               = 3085,
-    SE_ALG_ZBLK_ECC_INT_ENr                                               = 3086,
-    SE_ALG_ZBLK_ECC_INT_MASKr                                             = 3087,
-    SE_ALG_ZBLK_ECC_INT_STATUSr                                           = 3088,
-    SE_ALG_HASH0_INT_ENr                                                  = 3089,
-    SE_ALG_HASH0_INT_MASKr                                                = 3090,
-    SE_ALG_HASH0_INT_STATUSr                                              = 3091,
-    SE_ALG_HASH1_INT_ENr                                                  = 3092,
-    SE_ALG_HASH1_INT_MASKr                                                = 3093,
-    SE_ALG_HASH1_INT_STATUSr                                              = 3094,
-    SE_ALG_HASH2_INT_ENr                                                  = 3095,
-    SE_ALG_HASH2_INT_MASKr                                                = 3096,
-    SE_ALG_HASH2_INT_STATUSr                                              = 3097,
-    SE_ALG_HASH3_INT_ENr                                                  = 3098,
-    SE_ALG_HASH3_INT_MASKr                                                = 3099,
-    SE_ALG_HASH3_INT_STATUSr                                              = 3100,
-    SE_ALG_LPM_INT_ENr                                                    = 3101,
-    SE_ALG_LPM_INT_MASKr                                                  = 3102,
-    SE_ALG_LPM_INT_STATUSr                                                = 3103,
-    SE_ALG_ZBLOCK_LPM_MASK0r                                              = 3104,
-    SE_ALG_ZBLOCK_LPM_MASK1r                                              = 3105,
-    SE_ALG_ZBLOCK_LPM_MASK2r                                              = 3106,
-    SE_ALG_ZBLOCK_LPM_MASK3r                                              = 3107,
-    SE_ALG_ZBLOCK_DEFAULT_ROUTE0r                                         = 3108,
-    SE_ALG_ZBLOCK_DEFAULT_ROUTE1r                                         = 3109,
-    SE_ALG_ZBLOCK_DEFAULT_ROUTE2r                                         = 3110,
-    SE_ALG_ZBLOCK_DEFAULT_ROUTE3r                                         = 3111,
-    SE_ALG_ZBLOCK_DEFAULT_ROUTE4r                                         = 3112,
-    SE_ALG_ZBLOCK_DEFAULT_ROUTE5r                                         = 3113,
-    SE_ALG_ZBLOCK_DEFAULT_ROUTE6r                                         = 3114,
-    SE_ALG_ZBLOCK_DEFAULT_ROUTE7r                                         = 3115,
-    SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM0r                                   = 3116,
-    SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM1r                                   = 3117,
-    SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM2r                                   = 3118,
-    SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM3r                                   = 3119,
-    SE_ALG_ZBLOCK_ECC_ERR_STATUSr                                         = 3120,
-    SE_ALG_ZBLOCK_LPM_V6_SRAM_CMPr                                        = 3121,
-    SE_ALG_ZBLOCK_LPM_V4_SRAM_CMPr                                        = 3122,
-    SE_PARSER_KSCHD_PFUL_CFGr                                             = 3123,
-    SE_PARSER_DEBUG_CNT_MODEr                                             = 3124,
-    SE_PARSER_PARSER_INT_ENr                                              = 3125,
-    SE_PARSER_PARSER_INT_MASKr                                            = 3126,
-    SE_PARSER_PARSER_INT_STATUSr                                          = 3127,
-    SE_PARSER_PARSER_INT_UNMASK_FLAGr                                     = 3128,
-    SE_PARSER_ECC_BYPASS_READr                                            = 3129,
-    SE_PARSER_MEX0_5_REQ_CNTr                                             = 3130,
-    SE_PARSER_KSCHD_REQ0_5_CNTr                                           = 3131,
-    SE_PARSER_KSCHD_PARSER_FC0_5_CNTr                                     = 3132,
-    SE_PARSER_SE_PPU_MEX0_5_FC_CNTr                                       = 3133,
-    SE_PARSER_SMMU0_MARC_FC_CNTr                                          = 3134,
-    SE_PARSER_SMMU0_MARC_KEY_CNTr                                         = 3135,
-    SE_PARSER_CMMU_KEY_CNTr                                               = 3136,
-    SE_PARSER_CMMU_PARSER_FC_CNTr                                         = 3137,
-    SE_PARSER_MARC_TAB_TYPE_ERR_MEX0_5_CNTr                               = 3138,
-    SE_PARSER_ERAM_FULLADDR_DROP_CNTr                                     = 3139,
-    SE_AS_HASH0_PFUL_CFGr                                                 = 3140,
-    SE_AS_HASH1_PFUL_CFGr                                                 = 3141,
-    SE_AS_HASH2_PFUL_CFGr                                                 = 3142,
-    SE_AS_HASH3_PFUL_CFGr                                                 = 3143,
-    SE_AS_PBU_PFUL_CFGr                                                   = 3144,
-    SE_AS_LPM_PFUL_CFGr                                                   = 3145,
-    SE_AS_ETCAM_PFUL_CFGr                                                 = 3146,
-    SE_AS_AS_LEARN0_FIFO_CFGr                                             = 3147,
-    SE_AS_AS_LEARN1_FIFO_CFGr                                             = 3148,
-    SE_AS_AS_DMA_FIFO_CFGr                                                = 3149,
-    SE_AS_AGE_PFUL_CFGr                                                   = 3150,
-    SE_AS_ETCAM_RSP_CFGr                                                  = 3151,
-    SE_AS_PBU_ECC_BYPASS_READr                                            = 3152,
-    SE_AS_ETCAM0_ECC_BYPASS_READr                                         = 3153,
-    SE_AS_ETCAM1_ECC_BYPASS_READr                                         = 3154,
-    SE_AS_LPM_ECC_BYPASS_READr                                            = 3155,
-    SE_AS_HASH_ECC_BYPASS_READr                                           = 3156,
-    SE_AS_HASH_LEARN_ECC_BYPASS_READr                                     = 3157,
-    SE_AS_DEBUG_CNT_MODEr                                                 = 3158,
-    SE_AS_AS_INT_0_ENr                                                    = 3159,
-    SE_AS_AS_INT_0_MASKr                                                  = 3160,
-    SE_AS_AS_INT_1_ENr                                                    = 3161,
-    SE_AS_AS_INT_1_MASKr                                                  = 3162,
-    SE_AS_AS_INT_2_ENr                                                    = 3163,
-    SE_AS_AS_INT_2_MASKr                                                  = 3164,
-    SE_AS_AS_INT_0_STATUSr                                                = 3165,
-    SE_AS_AS_INT_1_STATUSr                                                = 3166,
-    SE_AS_AS_INT_2_STATUSr                                                = 3167,
-    SE_AS_SE_AS_INT_STATUSr                                               = 3168,
-    SE_AS_HASH0_3_WR_REQ_CNTr                                             = 3169,
-    SE_AS_SMMU0_ETCAM0_1_FC_CNTr                                          = 3170,
-    SE_AS_ETCAM0_1_SMMU0_REQ_CNTr                                         = 3171,
-    SE_AS_SMMU0_ETCAM0_1_RSP_CNTr                                         = 3172,
-    SE_AS_AS_HLA_HASH_P0_3_KEY_CNTr                                       = 3173,
-    SE_AS_AS_HLA_LPM_P0_KEY_CNTr                                          = 3174,
-    SE_AS_ALG_AS_HASH_P0_3_RSP_CNTr                                       = 3175,
-    SE_AS_ALG_AS_HASH_P0_3_SMF_RSP_CNTr                                   = 3176,
-    SE_AS_ALG_AS_LPM_P0_RSP_CNTr                                          = 3177,
-    SE_AS_ALG_AS_LPM_P0_3_SMF_RSP_CNTr                                    = 3178,
-    SE_AS_AS_PBU_KEY_CNTr                                                 = 3179,
-    SE_AS_PBU_SE_DPI_RSP_DAT_CNTr                                         = 3180,
-    SE_AS_AS_ETCAM_CTRL_REQ0_CNTr                                         = 3181,
-    SE_AS_ETCAM_CTRL_AS_INDEX0_1_CNTr                                     = 3182,
-    SE_AS_ETCAM_CTRL_AS_HIT0_1_CNTr                                       = 3183,
-    SE_AS_AS_SMMU0_REQ_CNTr                                               = 3184,
-    SE_AS_LEARN_HLA_WR_CNTr                                               = 3185,
-    SE_AS_AS_SMMU1_REQ_CNTr                                               = 3186,
-    SE_AS_SE_CFG_MAC_DAT_CNTr                                             = 3187,
-    SE_AS_ALG_AS_HASH_P0_3_FC_CNTr                                        = 3188,
-    SE_AS_ALG_AS_LPM_P0_FC_CNTr                                           = 3189,
-    SE_AS_AS_ALG_HASH_P0_3_FC_CNTr                                        = 3190,
-    SE_AS_AS_ALG_LPM_P0_FC_CNTr                                           = 3191,
-    SE_AS_AS_PBU_FC_CNTr                                                  = 3192,
-    SE_AS_PBU_SE_DPI_KEY_FC_CNTr                                          = 3193,
-    SE_AS_AS_ETCAM_CTRL_FC0_1_CNTr                                        = 3194,
-    SE_AS_ETCAM_CTRL_AS_FC0_1_CNTr                                        = 3195,
-    SE_AS_SMMU0_AS_MAC_AGE_FC_CNTr                                        = 3196,
-    SE_AS_ALG_LEARN_FC_CNTr                                               = 3197,
-    SE_AS_SMMU1_AS_FC_CNTr                                                = 3198,
-    SE_AS_CFG_SE_MAC_FC_CNTr                                              = 3199,
-    SE_KSCHD_KSCHD_CPU_RDYr                                               = 3200,
-    SE_KSCHD_PPU0_ECC_BYPASS_READr                                        = 3201,
-    SE_KSCHD_PBU_ECC_BYPASS_READr                                         = 3202,
-    SE_KSCHD_SMMU1_ECC_BYPASS_READr                                       = 3203,
-    SE_KSCHD_ASS_ECC_BYPASS_READr                                         = 3204,
-    SE_KSCHD_SDT_Hr                                                       = 3205,
-    SE_KSCHD_SDT_Lr                                                       = 3206,
-    SE_KSCHD_HASH_KEY15r                                                  = 3207,
-    SE_KSCHD_HASH_KEY14r                                                  = 3208,
-    SE_KSCHD_HASH_KEY13r                                                  = 3209,
-    SE_KSCHD_HASH_KEY12r                                                  = 3210,
-    SE_KSCHD_HASH_KEY11r                                                  = 3211,
-    SE_KSCHD_HASH_KEY10r                                                  = 3212,
-    SE_KSCHD_HASH_KEY9r                                                   = 3213,
-    SE_KSCHD_HASH_KEY8r                                                   = 3214,
-    SE_KSCHD_HASH_KEY7r                                                   = 3215,
-    SE_KSCHD_HASH_KEY6r                                                   = 3216,
-    SE_KSCHD_HASH_KEY5r                                                   = 3217,
-    SE_KSCHD_HASH_KEY4r                                                   = 3218,
-    SE_KSCHD_HASH_KEY3r                                                   = 3219,
-    SE_KSCHD_HASH_KEY2r                                                   = 3220,
-    SE_KSCHD_HASH_KEY1r                                                   = 3221,
-    SE_KSCHD_HASH_KEY0r                                                   = 3222,
-    SE_KSCHD_SCHD_INT_0_ENr                                               = 3223,
-    SE_KSCHD_SCHD_INT_0_MASKr                                             = 3224,
-    SE_KSCHD_SCHD_INT_1_ENr                                               = 3225,
-    SE_KSCHD_SCHD_INT_1_MASKr                                             = 3226,
-    SE_KSCHD_SCHD_INT_2_ENr                                               = 3227,
-    SE_KSCHD_SCHD_INT_2_MASKr                                             = 3228,
-    SE_KSCHD_SCHD_INT_3_ENr                                               = 3229,
-    SE_KSCHD_SCHD_INT_3_MASKr                                             = 3230,
-    SE_KSCHD_SCHD_INT_4_ENr                                               = 3231,
-    SE_KSCHD_SCHD_INT_4_MASKr                                             = 3232,
-    SE_KSCHD_SCHD_INT_0_STATUSr                                           = 3233,
-    SE_KSCHD_SCHD_INT_1_STATUSr                                           = 3234,
-    SE_KSCHD_SCHD_INT_2_STATUSr                                           = 3235,
-    SE_KSCHD_SCHD_INT_3_STATUSr                                           = 3236,
-    SE_KSCHD_SCHD_INT_4_STATUSr                                           = 3237,
-    SE_KSCHD_SE_KSCHD_INT_STATUSr                                         = 3238,
-    SE_KSCHD_DEBUG_CNT_MODEr                                              = 3239,
-    SE_KSCHD_SE_PARSER_KSCHD_KEY0_3_CNTr                                  = 3240,
-    SE_KSCHD_SE_SMMU1_KEY0_3_CNTr                                         = 3241,
-    SE_KSCHD_KSCHD_AS_KEY0_CNTr                                           = 3242,
-    SE_KSCHD_KSCHD_AS_KEY1_CNTr                                           = 3243,
-    SE_KSCHD_KSCHD_AS_KEY2_CNTr                                           = 3244,
-    SE_KSCHD_KSCHD_AS_KEY3_CNTr                                           = 3245,
-    SE_KSCHD_KSCHD_AS_KEY4_CNTr                                           = 3246,
-    SE_KSCHD_KSCHD_AS_KEY5_CNTr                                           = 3247,
-    SE_KSCHD_KSCHD_AS_KEY6_CNTr                                           = 3248,
-    SE_KSCHD_KSCHD_AS_KEY9_CNTr                                           = 3249,
-    SE_KSCHD_KSCHD_SE_PARSER_FC0_3_CNTr                                   = 3250,
-    SE_KSCHD_SMMU1_SE_FC0_3_CNTr                                          = 3251,
-    SE_KSCHD_AS_KSCHD_FC_CNT0r                                            = 3252,
-    SE_KSCHD_AS_KSCHD_FC_CNT1r                                            = 3253,
-    SE_KSCHD_AS_KSCHD_FC_CNT2r                                            = 3254,
-    SE_KSCHD_AS_KSCHD_FC_CNT3r                                            = 3255,
-    SE_KSCHD_AS_KSCHD_FC_CNT4r                                            = 3256,
-    SE_KSCHD_AS_KSCHD_FC_CNT5r                                            = 3257,
-    SE_KSCHD_AS_KSCHD_FC_CNT6r                                            = 3258,
-    SE_KSCHD_AS_KSCHD_FC_CNT9r                                            = 3259,
-    SE_RSCHD_RSCHD_HASH_PFUL_CFGr                                         = 3260,
-    SE_RSCHD_RSCHD_HASH_EPT_CFGr                                          = 3261,
-    SE_RSCHD_RSCHD_PBU_PFUL_CFGr                                          = 3262,
-    SE_RSCHD_RSCHD_PBU_EPT_CFGr                                           = 3263,
-    SE_RSCHD_RSCHD_LPM_PFUL_CFGr                                          = 3264,
-    SE_RSCHD_RSCHD_LPM_EPT_CFGr                                           = 3265,
-    SE_RSCHD_RSCHD_ETCAM_PFUL_CFGr                                        = 3266,
-    SE_RSCHD_RSCHD_ETCAM_EPT_CFGr                                         = 3267,
-    SE_RSCHD_SMMU0_WB_PFUL_CFGr                                           = 3268,
-    SE_RSCHD_SMMU0_WB_EPT_CFGr                                            = 3269,
-    SE_RSCHD_SMMU1_WB_PFUL_CFGr                                           = 3270,
-    SE_RSCHD_SMMU1_WB_EPT_CFGr                                            = 3271,
-    SE_RSCHD_ALG_WB_PFUL_CFGr                                             = 3272,
-    SE_RSCHD_ALG_WB_EPT_CFGr                                              = 3273,
-    SE_RSCHD_WR_RSP_VLD_ENr                                               = 3274,
-    SE_RSCHD_NPPU_WB_PFUL_CFGr                                            = 3275,
-    SE_RSCHD_NPPU_WB_EPT_CFGr                                             = 3276,
-    SE_RSCHD_PORT0_INT_ENr                                                = 3277,
-    SE_RSCHD_PORT0_INT_MASKr                                              = 3278,
-    SE_RSCHD_PORT1_INT_ENr                                                = 3279,
-    SE_RSCHD_PORT1_INT_MASKr                                              = 3280,
-    SE_RSCHD_PORT0_INT_STATUSr                                            = 3281,
-    SE_RSCHD_PORT1_INT_STATUSr                                            = 3282,
-    SE_RSCHD_SE_RSCHD_INT_STATUSr                                         = 3283,
-    SE_RSCHD_DEBUG_CNT_MODEr                                              = 3284,
-    SE_RSCHD_SE_PPU_MEX0_5_RSP1_CNTr                                      = 3285,
-    SE_RSCHD_AS_RSCHD_RSP0_CNTr                                           = 3286,
-    SE_RSCHD_AS_RSCHD_RSP1_CNTr                                           = 3287,
-    SE_RSCHD_AS_RSCHD_RSP2_CNTr                                           = 3288,
-    SE_RSCHD_AS_RSCHD_RSP3_CNTr                                           = 3289,
-    SE_RSCHD_AS_RSCHD_RSP4_CNTr                                           = 3290,
-    SE_RSCHD_AS_RSCHD_RSP5_CNTr                                           = 3291,
-    SE_RSCHD_AS_RSCHD_RSP6_CNTr                                           = 3292,
-    SE_RSCHD_AS_RSCHD_RSP9_CNTr                                           = 3293,
-    SE_RSCHD_SMMU1_SE_RSP0_3_CNTr                                         = 3294,
-    SE_RSCHD_PPU_SE_MEX0_3_FC_CNTr                                        = 3295,
-    SE_RSCHD_RSCHD_AS_FC_CNT0r                                            = 3296,
-    SE_RSCHD_RSCHD_AS_FC_CNT1r                                            = 3297,
-    SE_RSCHD_RSCHD_AS_FC_CNT2r                                            = 3298,
-    SE_RSCHD_RSCHD_AS_FC_CNT3r                                            = 3299,
-    SE_RSCHD_RSCHD_AS_FC_CNT4r                                            = 3300,
-    SE_RSCHD_RSCHD_AS_FC_CNT5r                                            = 3301,
-    SE_RSCHD_RSCHD_AS_FC_CNT6r                                            = 3302,
-    SE_RSCHD_RSCHD_AS_FC_CNT9r                                            = 3303,
-    SE_RSCHD_SE_SMMU1_FC0_3_CNTr                                          = 3304,
-    SE_RSCHD_SMMU0_SE_WR_DONE_CNTr                                        = 3305,
-    SE_RSCHD_SE_SMMU0_WR_DONE_FC_CNTr                                     = 3306,
-    SE_RSCHD_SMMU1_SE_WR_RSP_CNTr                                         = 3307,
-    SE_RSCHD_SE_SMMU1_WR_RSP_FC_CNTr                                      = 3308,
-    SE_RSCHD_ALG_SE_WR_RSP_CNTr                                           = 3309,
-    SE_RSCHD_SE_ALG_WR_RSP_FC_CNTr                                        = 3310,
-    SMMU0_SMMU0_KSCHD_PFUL_CFG0r                                          = 3311,
-    SMMU0_SMMU0_KSCHD_PFUL_CFG1r                                          = 3312,
-    SMMU0_SMMU0_CTRL_PFUL1_CFGr                                           = 3313,
-    SMMU0_SMMU0_CTRL_PFUL2_CFGr                                           = 3314,
-    SMMU0_SMMU0_CTRL_PFUL3_CFGr                                           = 3315,
-    SMMU0_SMMU0_RSCHD_PFUL_CFGr                                           = 3316,
-    SMMU0_SMMU0_RSCHD_EPT_CFGr                                            = 3317,
-    SMMU0_SMMU0_ALUCMD_PFUL_CFGr                                          = 3318,
-    SMMU0_SMMU0_ALUWR_PFUL_CFGr                                           = 3319,
-    SMMU0_SMMU0_WR_ARB_PFUL_CFG0r                                         = 3320,
-    SMMU0_SMMU0_WR_ARB_PFUL_CFG1r                                         = 3321,
-    SMMU0_SMMU0_ORD_PFUL_CFGr                                             = 3322,
-    SMMU0_SMMU0_CFG_DMA_BADDRr                                            = 3323,
-    SMMU0_SMMU0_CFG_ODMA0_BADDRr                                          = 3324,
-    SMMU0_SMMU0_CFG_ODMA1_BADDRr                                          = 3325,
-    SMMU0_SMMU0_CFG_ODMA2_BADDRr                                          = 3326,
-    SMMU0_SMMU0_CFG_ODMA_TDM_BADDRr                                       = 3327,
-    SMMU0_SMMU0_CFG_MCAST_BADDRr                                          = 3328,
-    SMMU0_SMMU0_CFG_LPM0r                                                 = 3329,
-    SMMU0_SMMU0_CFG_LPM1r                                                 = 3330,
-    SMMU0_SMMU0_CFG_LPM2r                                                 = 3331,
-    SMMU0_SMMU0_CFG_LPM3r                                                 = 3332,
-    SMMU0_SMMU0_CFG_LPM4r                                                 = 3333,
-    SMMU0_SMMU0_CFG_LPM5r                                                 = 3334,
-    SMMU0_SMMU0_CFG_LPM6r                                                 = 3335,
-    SMMU0_SMMU0_CFG_LPM7r                                                 = 3336,
-    SMMU0_SMMU0_DEBUG_CNT_MODEr                                           = 3337,
-    SMMU0_SMMU0_STAT_OVERFLOW_MODEr                                       = 3338,
-    SMMU0_SMMU0_INIT_EN_CFG_TMPr                                          = 3339,
-    SMMU0_SMMU0_SMMU0_INT_UNMASK_FLAGr                                    = 3340,
-    SMMU0_SMMU0_SMMU0_INT0_ENr                                            = 3341,
-    SMMU0_SMMU0_SMMU0_INT0_MASKr                                          = 3342,
-    SMMU0_SMMU0_SMMU0_INT0_STATUSr                                        = 3343,
-    SMMU0_SMMU0_SMMU0_INT1_ENr                                            = 3344,
-    SMMU0_SMMU0_SMMU0_INT1_MASKr                                          = 3345,
-    SMMU0_SMMU0_SMMU0_INT1_STATUSr                                        = 3346,
-    SMMU0_SMMU0_SMMU0_INT2_ENr                                            = 3347,
-    SMMU0_SMMU0_SMMU0_INT2_MASKr                                          = 3348,
-    SMMU0_SMMU0_SMMU0_INT2_STATUSr                                        = 3349,
-    SMMU0_SMMU0_SMMU0_INT3_ENr                                            = 3350,
-    SMMU0_SMMU0_SMMU0_INT3_MASKr                                          = 3351,
-    SMMU0_SMMU0_SMMU0_INT3_STATUSr                                        = 3352,
-    SMMU0_SMMU0_SMMU0_INT4_ENr                                            = 3353,
-    SMMU0_SMMU0_SMMU0_INT4_MASKr                                          = 3354,
-    SMMU0_SMMU0_SMMU0_INT4_STATUSr                                        = 3355,
-    SMMU0_SMMU0_SMMU0_INT5_ENr                                            = 3356,
-    SMMU0_SMMU0_SMMU0_INT5_MASKr                                          = 3357,
-    SMMU0_SMMU0_SMMU0_INT5_STATUSr                                        = 3358,
-    SMMU0_SMMU0_SMMU0_INT6_ENr                                            = 3359,
-    SMMU0_SMMU0_SMMU0_INT6_MASKr                                          = 3360,
-    SMMU0_SMMU0_SMMU0_INT6_STATUSr                                        = 3361,
-    SMMU0_SMMU0_SMMU0_INT7_ENr                                            = 3362,
-    SMMU0_SMMU0_SMMU0_INT7_MASKr                                          = 3363,
-    SMMU0_SMMU0_SMMU0_INT7_STATUSr                                        = 3364,
-    SMMU0_SMMU0_SMMU0_INT8_ENr                                            = 3365,
-    SMMU0_SMMU0_SMMU0_INT8_MASKr                                          = 3366,
-    SMMU0_SMMU0_SMMU0_INT8_STATUSr                                        = 3367,
-    SMMU0_SMMU0_SMMU0_INT9_ENr                                            = 3368,
-    SMMU0_SMMU0_SMMU0_INT9_MASKr                                          = 3369,
-    SMMU0_SMMU0_SMMU0_INT9_STATUSr                                        = 3370,
-    SMMU0_SMMU0_SMMU0_INT10_ENr                                           = 3371,
-    SMMU0_SMMU0_SMMU0_INT10_MASKr                                         = 3372,
-    SMMU0_SMMU0_SMMU0_INT10_STATUSr                                       = 3373,
-    SMMU0_SMMU0_SMMU0_INT11_ENr                                           = 3374,
-    SMMU0_SMMU0_SMMU0_INT11_MASKr                                         = 3375,
-    SMMU0_SMMU0_SMMU0_INT11_STATUSr                                       = 3376,
-    SMMU0_SMMU0_SMMU0_INT12_ENr                                           = 3377,
-    SMMU0_SMMU0_SMMU0_INT12_MASKr                                         = 3378,
-    SMMU0_SMMU0_SMMU0_INT12_STATUSr                                       = 3379,
-    SMMU0_SMMU0_SMMU0_INT13_ENr                                           = 3380,
-    SMMU0_SMMU0_SMMU0_INT13_MASKr                                         = 3381,
-    SMMU0_SMMU0_SMMU0_INT13_STATUSr                                       = 3382,
-    SMMU0_SMMU0_SMMU0_INT14_ENr                                           = 3383,
-    SMMU0_SMMU0_SMMU0_INT14_MASKr                                         = 3384,
-    SMMU0_SMMU0_SMMU0_INT14_STATUSr                                       = 3385,
-    SMMU0_SMMU0_SMMU0_ECC_UNMASK_FLAGr                                    = 3386,
-    SMMU0_SMMU0_SMMU0_INT15_ENr                                           = 3387,
-    SMMU0_SMMU0_SMMU0_INT15_MASKr                                         = 3388,
-    SMMU0_SMMU0_SMMU0_INT15_STATUSr                                       = 3389,
-    SMMU0_SMMU0_SMMU0_INT16_ENr                                           = 3390,
-    SMMU0_SMMU0_SMMU0_INT16_MASKr                                         = 3391,
-    SMMU0_SMMU0_SMMU0_INT16_STATUSr                                       = 3392,
-    SMMU0_SMMU0_SMMU0_INT17_ENr                                           = 3393,
-    SMMU0_SMMU0_SMMU0_INT17_MASKr                                         = 3394,
-    SMMU0_SMMU0_SMMU0_INT17_STATUSr                                       = 3395,
-    SMMU0_SMMU0_SMMU0_INT18_ENr                                           = 3396,
-    SMMU0_SMMU0_SMMU0_INT18_MASKr                                         = 3397,
-    SMMU0_SMMU0_SMMU0_INT18_STATUSr                                       = 3398,
-    SMMU0_SMMU0_SMMU0_INT19_ENr                                           = 3399,
-    SMMU0_SMMU0_SMMU0_INT19_MASKr                                         = 3400,
-    SMMU0_SMMU0_SMMU0_INT19_STATUSr                                       = 3401,
-    SMMU0_SMMU0_SMMU0_INT20_ENr                                           = 3402,
-    SMMU0_SMMU0_SMMU0_INT20_MASKr                                         = 3403,
-    SMMU0_SMMU0_SMMU0_INT20_STATUSr                                       = 3404,
-    SMMU0_SMMU0_SMMU0_INT21_ENr                                           = 3405,
-    SMMU0_SMMU0_SMMU0_INT21_MASKr                                         = 3406,
-    SMMU0_SMMU0_SMMU0_INT21_STATUSr                                       = 3407,
-    SMMU0_SMMU0_SMMU0_INT22_ENr                                           = 3408,
-    SMMU0_SMMU0_SMMU0_INT22_MASKr                                         = 3409,
-    SMMU0_SMMU0_SMMU0_INT22_STATUSr                                       = 3410,
-    SMMU0_SMMU0_SMMU0_INT23_ENr                                           = 3411,
-    SMMU0_SMMU0_SMMU0_INT23_MASKr                                         = 3412,
-    SMMU0_SMMU0_SMMU0_INT23_STATUSr                                       = 3413,
-    SMMU0_SMMU0_SMMU0_INT24_ENr                                           = 3414,
-    SMMU0_SMMU0_SMMU0_INT24_MASKr                                         = 3415,
-    SMMU0_SMMU0_SMMU0_INT24_STATUSr                                       = 3416,
-    SMMU0_SMMU0_SMMU0_INT25_ENr                                           = 3417,
-    SMMU0_SMMU0_SMMU0_INT25_MASKr                                         = 3418,
-    SMMU0_SMMU0_SMMU0_INT25_STATUSr                                       = 3419,
-    SMMU0_SMMU0_SMMU0_INT26_ENr                                           = 3420,
-    SMMU0_SMMU0_SMMU0_INT26_MASKr                                         = 3421,
-    SMMU0_SMMU0_SMMU0_INT26_STATUSr                                       = 3422,
-    SMMU0_SMMU0_SMMU0_INT27_ENr                                           = 3423,
-    SMMU0_SMMU0_SMMU0_INT27_MASKr                                         = 3424,
-    SMMU0_SMMU0_SMMU0_INT27_STATUSr                                       = 3425,
-    SMMU0_SMMU0_SMMU0_INT28_ENr                                           = 3426,
-    SMMU0_SMMU0_SMMU0_INT28_MASKr                                         = 3427,
-    SMMU0_SMMU0_SMMU0_INT28_STATUSr                                       = 3428,
-    SMMU0_SMMU0_SMMU0_INT29_ENr                                           = 3429,
-    SMMU0_SMMU0_SMMU0_INT29_MASKr                                         = 3430,
-    SMMU0_SMMU0_SMMU0_INT29_STATUSr                                       = 3431,
-    SMMU0_SMMU0_SMMU0_INT30_ENr                                           = 3432,
-    SMMU0_SMMU0_SMMU0_INT30_MASKr                                         = 3433,
-    SMMU0_SMMU0_SMMU0_INT30_STATUSr                                       = 3434,
-    SMMU0_SMMU0_SMMU0_INT31_ENr                                           = 3435,
-    SMMU0_SMMU0_SMMU0_INT31_MASKr                                         = 3436,
-    SMMU0_SMMU0_SMMU0_INT31_STATUSr                                       = 3437,
-    SMMU0_SMMU0_SMMU0_INT32_ENr                                           = 3438,
-    SMMU0_SMMU0_SMMU0_INT32_MASKr                                         = 3439,
-    SMMU0_SMMU0_SMMU0_INT32_STATUSr                                       = 3440,
-    SMMU0_SMMU0_SMMU0_INT33_ENr                                           = 3441,
-    SMMU0_SMMU0_SMMU0_INT33_MASKr                                         = 3442,
-    SMMU0_SMMU0_SMMU0_INT33_STATUSr                                       = 3443,
-    SMMU0_SMMU0_SMMU0_INT34_ENr                                           = 3444,
-    SMMU0_SMMU0_SMMU0_INT34_MASKr                                         = 3445,
-    SMMU0_SMMU0_SMMU0_INT34_STATUSr                                       = 3446,
-    SMMU0_SMMU0_SMMU0_INT35_ENr                                           = 3447,
-    SMMU0_SMMU0_SMMU0_INT35_MASKr                                         = 3448,
-    SMMU0_SMMU0_SMMU0_INT35_STATUSr                                       = 3449,
-    SMMU0_SMMU0_SMMU0_INT36_ENr                                           = 3450,
-    SMMU0_SMMU0_SMMU0_INT36_MASKr                                         = 3451,
-    SMMU0_SMMU0_SMMU0_INT36_STATUSr                                       = 3452,
-    SMMU0_SMMU0_SMMU0_INT37_ENr                                           = 3453,
-    SMMU0_SMMU0_SMMU0_INT37_MASKr                                         = 3454,
-    SMMU0_SMMU0_SMMU0_INT37_STATUSr                                       = 3455,
-    SMMU0_SMMU0_SMMU0_INT38_ENr                                           = 3456,
-    SMMU0_SMMU0_SMMU0_INT38_MASKr                                         = 3457,
-    SMMU0_SMMU0_SMMU0_INT38_STATUSr                                       = 3458,
-    SMMU0_SMMU0_SMMU0_INT39_ENr                                           = 3459,
-    SMMU0_SMMU0_SMMU0_INT39_MASKr                                         = 3460,
-    SMMU0_SMMU0_SMMU0_INT39_STATUSr                                       = 3461,
-    SMMU0_SMMU0_SMMU0_INT40_ENr                                           = 3462,
-    SMMU0_SMMU0_SMMU0_INT40_MASKr                                         = 3463,
-    SMMU0_SMMU0_SMMU0_INT40_STATUSr                                       = 3464,
-    SMMU0_SMMU0_SMMU0_INT41_ENr                                           = 3465,
-    SMMU0_SMMU0_SMMU0_INT41_MASKr                                         = 3466,
-    SMMU0_SMMU0_SMMU0_INT41_STATUSr                                       = 3467,
-    SMMU0_SMMU0_SMMU0_INT42_ENr                                           = 3468,
-    SMMU0_SMMU0_SMMU0_INT42_MASKr                                         = 3469,
-    SMMU0_SMMU0_SMMU0_INT42_STATUSr                                       = 3470,
-    SMMU0_SMMU0_SMMU0_INT43_ENr                                           = 3471,
-    SMMU0_SMMU0_SMMU0_INT43_MASKr                                         = 3472,
-    SMMU0_SMMU0_SMMU0_INT43_STATUSr                                       = 3473,
-    SMMU0_SMMU0_SMMU0_INT44_ENr                                           = 3474,
-    SMMU0_SMMU0_SMMU0_INT44_MASKr                                         = 3475,
-    SMMU0_SMMU0_SMMU0_INT44_STATUSr                                       = 3476,
-    SMMU0_SMMU0_SMMU0_INT45_ENr                                           = 3477,
-    SMMU0_SMMU0_SMMU0_INT45_MASKr                                         = 3478,
-    SMMU0_SMMU0_SMMU0_INT45_STATUSr                                       = 3479,
-    SMMU0_SMMU0_SMMU0_INT46_ENr                                           = 3480,
-    SMMU0_SMMU0_SMMU0_INT46_MASKr                                         = 3481,
-    SMMU0_SMMU0_SMMU0_INT46_STATUSr                                       = 3482,
-    SMMU0_SMMU0_SMMU0_INT47_ENr                                           = 3483,
-    SMMU0_SMMU0_SMMU0_INT47_MASKr                                         = 3484,
-    SMMU0_SMMU0_SMMU0_INT47_STATUSr                                       = 3485,
-    SMMU0_SMMU0_SMMU0_INT48_ENr                                           = 3486,
-    SMMU0_SMMU0_SMMU0_INT48_MASKr                                         = 3487,
-    SMMU0_SMMU0_SMMU0_INT48_STATUSr                                       = 3488,
-    SMMU0_SMMU0_SMMU0_INT49_ENr                                           = 3489,
-    SMMU0_SMMU0_SMMU0_INT49_MASKr                                         = 3490,
-    SMMU0_SMMU0_SMMU0_INT49_STATUSr                                       = 3491,
-    SMMU0_SMMU0_SMMU0_INT50_ENr                                           = 3492,
-    SMMU0_SMMU0_SMMU0_INT50_MASKr                                         = 3493,
-    SMMU0_SMMU0_SMMU0_INT50_STATUSr                                       = 3494,
-    SMMU0_SMMU0_SMMU0_INT51_ENr                                           = 3495,
-    SMMU0_SMMU0_SMMU0_INT51_MASKr                                         = 3496,
-    SMMU0_SMMU0_SMMU0_INT51_STATUSr                                       = 3497,
-    SMMU0_SMMU0_SMMU0_INT52_ENr                                           = 3498,
-    SMMU0_SMMU0_SMMU0_INT52_MASKr                                         = 3499,
-    SMMU0_SMMU0_SMMU0_INT52_STATUSr                                       = 3500,
-    SMMU0_SMMU0_SMMU0_INT53_ENr                                           = 3501,
-    SMMU0_SMMU0_SMMU0_INT53_MASKr                                         = 3502,
-    SMMU0_SMMU0_SMMU0_INT53_STATUSr                                       = 3503,
-    SMMU0_SMMU0_CTRL0_ARBITER_ECC_BYPASSr                                 = 3504,
-    SMMU0_SMMU0_CTRL2_ARBITER_ECC_BYPASSr                                 = 3505,
-    SMMU0_SMMU0_CTRL4_ARBITER_ECC_BYPASSr                                 = 3506,
-    SMMU0_SMMU0_CTRL6_ARBITER_ECC_BYPASSr                                 = 3507,
-    SMMU0_SMMU0_CTRL8_ARBITER_ECC_BYPASSr                                 = 3508,
-    SMMU0_SMMU0_CTRL10_ARBITER_ECC_BYPASSr                                = 3509,
-    SMMU0_SMMU0_CTRL12_ARBITER_ECC_BYPASSr                                = 3510,
-    SMMU0_SMMU0_CTRL14_ARBITER_ECC_BYPASSr                                = 3511,
-    SMMU0_SMMU0_CTRL16_ARBITER_ECC_BYPASSr                                = 3512,
-    SMMU0_SMMU0_CTRL18_ARBITER_ECC_BYPASSr                                = 3513,
-    SMMU0_SMMU0_CTRL20_ARBITER_ECC_BYPASSr                                = 3514,
-    SMMU0_SMMU0_CTRL22_ARBITER_ECC_BYPASSr                                = 3515,
-    SMMU0_SMMU0_CTRL24_ARBITER_ECC_BYPASSr                                = 3516,
-    SMMU0_SMMU0_CTRL26_ARBITER_ECC_BYPASSr                                = 3517,
-    SMMU0_SMMU0_CTRL28_ARBITER_ECC_BYPASSr                                = 3518,
-    SMMU0_SMMU0_CTRL30_ARBITER_ECC_BYPASSr                                = 3519,
-    SMMU0_SMMU0_CTRL_REQ_ECC_BYPASSr                                      = 3520,
-    SMMU0_SMMU0_CTRL_INFO_ECC_BYPASSr                                     = 3521,
-    SMMU0_SMMU0_SMMU0_RSCHD_ECC_BYPASSr                                   = 3522,
-    SMMU0_SMMU0_SMMU0_WR_ECC_BYPASSr                                      = 3523,
-    SMMU0_SMMU0_CTRL0_ARBITER_ECC_ERRr                                    = 3524,
-    SMMU0_SMMU0_CTRL1_ARBITER_ECC_ERRr                                    = 3525,
-    SMMU0_SMMU0_CTRL2_ARBITER_ECC_ERRr                                    = 3526,
-    SMMU0_SMMU0_CTRL3_ARBITER_ECC_ERRr                                    = 3527,
-    SMMU0_SMMU0_CTRL4_ARBITER_ECC_ERRr                                    = 3528,
-    SMMU0_SMMU0_CTRL5_ARBITER_ECC_ERRr                                    = 3529,
-    SMMU0_SMMU0_CTRL6_ARBITER_ECC_ERRr                                    = 3530,
-    SMMU0_SMMU0_CTRL7_ARBITER_ECC_ERRr                                    = 3531,
-    SMMU0_SMMU0_CTRL8_ARBITER_ECC_ERRr                                    = 3532,
-    SMMU0_SMMU0_CTRL9_ARBITER_ECC_ERRr                                    = 3533,
-    SMMU0_SMMU0_CTRL10_ARBITER_ECC_ERRr                                   = 3534,
-    SMMU0_SMMU0_CTRL11_ARBITER_ECC_ERRr                                   = 3535,
-    SMMU0_SMMU0_CTRL12_ARBITER_ECC_ERRr                                   = 3536,
-    SMMU0_SMMU0_CTRL13_ARBITER_ECC_ERRr                                   = 3537,
-    SMMU0_SMMU0_CTRL14_ARBITER_ECC_ERRr                                   = 3538,
-    SMMU0_SMMU0_CTRL15_ARBITER_ECC_ERRr                                   = 3539,
-    SMMU0_SMMU0_CTRL16_ARBITER_ECC_ERRr                                   = 3540,
-    SMMU0_SMMU0_CTRL17_ARBITER_ECC_ERRr                                   = 3541,
-    SMMU0_SMMU0_CTRL18_ARBITER_ECC_ERRr                                   = 3542,
-    SMMU0_SMMU0_CTRL19_ARBITER_ECC_ERRr                                   = 3543,
-    SMMU0_SMMU0_CTRL20_ARBITER_ECC_ERRr                                   = 3544,
-    SMMU0_SMMU0_CTRL21_ARBITER_ECC_ERRr                                   = 3545,
-    SMMU0_SMMU0_CTRL22_ARBITER_ECC_ERRr                                   = 3546,
-    SMMU0_SMMU0_CTRL23_ARBITER_ECC_ERRr                                   = 3547,
-    SMMU0_SMMU0_CTRL24_ARBITER_ECC_ERRr                                   = 3548,
-    SMMU0_SMMU0_CTRL25_ARBITER_ECC_ERRr                                   = 3549,
-    SMMU0_SMMU0_CTRL26_ARBITER_ECC_ERRr                                   = 3550,
-    SMMU0_SMMU0_CTRL27_ARBITER_ECC_ERRr                                   = 3551,
-    SMMU0_SMMU0_CTRL28_ARBITER_ECC_ERRr                                   = 3552,
-    SMMU0_SMMU0_CTRL29_ARBITER_ECC_ERRr                                   = 3553,
-    SMMU0_SMMU0_CTRL30_ARBITER_ECC_ERRr                                   = 3554,
-    SMMU0_SMMU0_CTRL31_ARBITER_ECC_ERRr                                   = 3555,
-    SMMU0_SMMU0_CTRL_REQ_ECC_SINGLE_ERRr                                  = 3556,
-    SMMU0_SMMU0_CTRL_REQ_ECC_DOUBLE_ERRr                                  = 3557,
-    SMMU0_SMMU0_CTRL_INFO_ECC_SINGLE_ERRr                                 = 3558,
-    SMMU0_SMMU0_CTRL_INFO_ECC_DOUBLE_ERRr                                 = 3559,
-    SMMU0_SMMU0_SMMU0_WR_ECC_ERRr                                         = 3560,
-    SMMU0_SMMU0_SMMU0_RSCHD_ECC_SINGLE_ERRr                               = 3561,
-    SMMU0_SMMU0_SMMU0_RSCHD_ECC_DOUBLE_ERRr                               = 3562,
-    SMMU0_SMMU0_ORD_FIFO_EMPTYr                                           = 3563,
-    SMMU0_SMMU0_WR_ARB_FIFO_EMPTYr                                        = 3564,
-    SMMU0_SMMU0_CTRL_FIFO_EMPTY0r                                         = 3565,
-    SMMU0_SMMU0_CTRL_FIFO_EMPTY1r                                         = 3566,
-    SMMU0_SMMU0_CTRL_FIFO_EMPTY2r                                         = 3567,
-    SMMU0_SMMU0_CTRL_FIFO_EMPTY3r                                         = 3568,
-    SMMU0_SMMU0_CTRL_FIFO_EMPTY4r                                         = 3569,
-    SMMU0_SMMU0_CTRL_FIFO_EMPTY5r                                         = 3570,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY0r                                        = 3571,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY1r                                        = 3572,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY2r                                        = 3573,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY3r                                        = 3574,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY4r                                        = 3575,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY5r                                        = 3576,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY6r                                        = 3577,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY7r                                        = 3578,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY8r                                        = 3579,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY9r                                        = 3580,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY10r                                       = 3581,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY11r                                       = 3582,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY12r                                       = 3583,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY13r                                       = 3584,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY14r                                       = 3585,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY15r                                       = 3586,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY16r                                       = 3587,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY17r                                       = 3588,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY18r                                       = 3589,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY19r                                       = 3590,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY20r                                       = 3591,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY21r                                       = 3592,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY22r                                       = 3593,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY23r                                       = 3594,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY24r                                       = 3595,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY25r                                       = 3596,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY26r                                       = 3597,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY27r                                       = 3598,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY28r                                       = 3599,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY29r                                       = 3600,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY30r                                       = 3601,
-    SMMU0_SMMU0_KSCHD_FIFO_EMPTY31r                                       = 3602,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY0r                                        = 3603,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY1r                                        = 3604,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY2r                                        = 3605,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY3r                                        = 3606,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY4r                                        = 3607,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY5r                                        = 3608,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY6r                                        = 3609,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY7r                                        = 3610,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY8r                                        = 3611,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY9r                                        = 3612,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY10r                                       = 3613,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY11r                                       = 3614,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY12r                                       = 3615,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY13r                                       = 3616,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY14r                                       = 3617,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY15r                                       = 3618,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY16r                                       = 3619,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY17r                                       = 3620,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY18r                                       = 3621,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY19r                                       = 3622,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY20r                                       = 3623,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY21r                                       = 3624,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY22r                                       = 3625,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY23r                                       = 3626,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY24r                                       = 3627,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY25r                                       = 3628,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY26r                                       = 3629,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY27r                                       = 3630,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY28r                                       = 3631,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY29r                                       = 3632,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY30r                                       = 3633,
-    SMMU0_SMMU0_RSCHD_FIFO_EMPTY31r                                       = 3634,
-    SMMU0_SMMU0_EPT_FLAGr                                                 = 3635,
-    SMMU0_SMMU0_PPU_SOFT_RSTr                                             = 3636,
-    SMMU0_SMMU0_SMMU0_AS_MAC_AGE_FC_CNTr                                  = 3637,
-    SMMU0_SMMU0_SMMU0_MARC_SE_PARSER_FC_CNTr                              = 3638,
-    SMMU0_SMMU0_WR_ARB_CPU_FC_CNTr                                        = 3639,
-    SMMU0_SMMU0_SMMU0_LPM_AS_FC_CNTr                                      = 3640,
-    SMMU0_SMMU0_LPM_AS_SMMU0_FC_CNTr                                      = 3641,
-    SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_FC_CNTr                                 = 3642,
-    SMMU0_SMMU0_AS_ETCAM1_0_SMMU0_FC_CNTr                                 = 3643,
-    SMMU0_SMMU0_SMMU0_PPU_MCAST_FC_CNTr                                   = 3644,
-    SMMU0_SMMU0_PPU_SMMU0_MCAST_FC_CNTr                                   = 3645,
-    SMMU0_SMMU0_ODMA_SMMU0_TDM_FC_RSP_FC_CNTr                             = 3646,
-    SMMU0_SMMU0_SMMU0_ODMA_TDM_FC_KEY_FC_CNTr                             = 3647,
-    SMMU0_SMMU0_SMMU0_ODMA_FC_CNTr                                        = 3648,
-    SMMU0_SMMU0_SMMU0_CFG_TAB_RD_FC_CNTr                                  = 3649,
-    SMMU0_SMMU0_SMMU0_STAT_FC15_0_CNTr                                    = 3650,
-    SMMU0_SMMU0_STAT_SMMU0_FC15_0_CNTr                                    = 3651,
-    SMMU0_SMMU0_SMMU0_PPU_MEX5_0_FC_CNTr                                  = 3652,
-    SMMU0_SMMU0_PPU_SMMU0_MEX5_0_FC_CNTr                                  = 3653,
-    SMMU0_SMMU0_AS_SMMU0_MAC_AGE_REQ_CNTr                                 = 3654,
-    SMMU0_SMMU0_SE_PARSER_SMMU0_MARC_KEY_CNTr                             = 3655,
-    SMMU0_SMMU0_CPU_IND_RDAT_CNTr                                         = 3656,
-    SMMU0_SMMU0_CPU_IND_RD_REQ_CNTr                                       = 3657,
-    SMMU0_SMMU0_CPU_IND_WR_REQ_CNTr                                       = 3658,
-    SMMU0_SMMU0_SMMU0_PLCR_RSP0_CNTr                                      = 3659,
-    SMMU0_SMMU0_PLCR_SMMU0_REQ0_CNTr                                      = 3660,
-    SMMU0_SMMU0_SMMU0_LPM_AS_RSP_CNTr                                     = 3661,
-    SMMU0_SMMU0_LPM_AS_SMMU0_REQ_CNTr                                     = 3662,
-    SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_RSP_CNTr                                = 3663,
-    SMMU0_SMMU0_ETCAM1_0_AS_SMMU0_REQ_CNTr                                = 3664,
-    SMMU0_SMMU0_SMMU0_PPU_MCAST_RSP_CNTr                                  = 3665,
-    SMMU0_SMMU0_PPU_SMMU0_MCAST_KEY_CNTr                                  = 3666,
-    SMMU0_SMMU0_SMMU0_ODMA_TDM_MC_RSP_CNTr                                = 3667,
-    SMMU0_SMMU0_ODMA_SMMU0_TDM_MC_KEY_CNTr                                = 3668,
-    SMMU0_SMMU0_SMMU0_ODMA_RSP_CNTr                                       = 3669,
-    SMMU0_SMMU0_ODMA_SMMU0_CMD_CNTr                                       = 3670,
-    SMMU0_SMMU0_SMMU0_CFG_TAB_RDAT_CNTr                                   = 3671,
-    SMMU0_SMMU0_CFG_SMMU0_TAB_RD_CNTr                                     = 3672,
-    SMMU0_SMMU0_SMMU0_STAT_RSP15_0_CNTr                                   = 3673,
-    SMMU0_SMMU0_STAT_SMMU0_REQ15_0_CNTr                                   = 3674,
-    SMMU0_SMMU0_SMMU0_PPU_MEX5_0_RSP_CNTr                                 = 3675,
-    SMMU0_SMMU0_PPU_SMMU0_MEX5_0_KEY_CNTr                                 = 3676,
-    SMMU0_SMMU0_FTM_STAT_SMMU0_REQ0_CNTr                                  = 3677,
-    SMMU0_SMMU0_FTM_STAT_SMMU0_REQ1_CNTr                                  = 3678,
-    SMMU0_SMMU0_ETM_STAT_SMMU0_REQ0_CNTr                                  = 3679,
-    SMMU0_SMMU0_ETM_STAT_SMMU0_REQ1_CNTr                                  = 3680,
-    SMMU0_SMMU0_REQ_ERAM0_31_RD_CNTr                                      = 3681,
-    SMMU0_SMMU0_REQ_ERAM0_31_WR_CNTr                                      = 3682,
-    SE_SMMU1_DDR_WDAT1r                                                   = 3683,
-    SE_SMMU1_DDR_WDAT2r                                                   = 3684,
-    SE_SMMU1_DDR_WDAT3r                                                   = 3685,
-    SE_SMMU1_DDR_WDAT4r                                                   = 3686,
-    SE_SMMU1_DDR_WDAT5r                                                   = 3687,
-    SE_SMMU1_DDR_WDAT6r                                                   = 3688,
-    SE_SMMU1_DDR_WDAT7r                                                   = 3689,
-    SE_SMMU1_DDR_WDAT8r                                                   = 3690,
-    SE_SMMU1_DDR_WDAT9r                                                   = 3691,
-    SE_SMMU1_DDR_WDAT10r                                                  = 3692,
-    SE_SMMU1_DDR_WDAT11r                                                  = 3693,
-    SE_SMMU1_DDR_WDAT12r                                                  = 3694,
-    SE_SMMU1_DDR_WDAT13r                                                  = 3695,
-    SE_SMMU1_DDR_WDAT14r                                                  = 3696,
-    SE_SMMU1_DDR_WDAT15r                                                  = 3697,
-    SE_SMMU1_CNT_STAT_CACHE_ENr                                           = 3698,
-    SE_SMMU1_CNT_STAT_CACHE_CLRr                                          = 3699,
-    SE_SMMU1_CNT_STAT_CACHE_REQ_63_32r                                    = 3700,
-    SE_SMMU1_CNT_STAT_CACHE_REQ_31_0r                                     = 3701,
-    SE_SMMU1_CNT_STAT_CACHE_HIT_63_32r                                    = 3702,
-    SE_SMMU1_CNT_STAT_CACHE_HIT_31_0r                                     = 3703,
-    SE_SMMU1_DDR_CMD0r                                                    = 3704,
-    SE_SMMU1_INFO_ADDRr                                                   = 3705,
-    SE_SMMU1_DDR_CMD1r                                                    = 3706,
-    SE_SMMU1_CLR_START_ADDRr                                              = 3707,
-    SE_SMMU1_CLR_END_ADDRr                                                = 3708,
-    SE_SMMU1_CLR_TBL_ENr                                                  = 3709,
-    SE_SMMU1_DEBUG_CNT_MODEr                                              = 3710,
-    SE_SMMU1_INIT_DONEr                                                   = 3711,
-    SE_SMMU1_CPU_RSP_RD_DONEr                                             = 3712,
-    SE_SMMU1_KSCH_OAM_SP_ENr                                              = 3713,
-    SE_SMMU1_CFG_CACHE_ENr                                                = 3714,
-    SE_SMMU1_CACHE_AGE_ENr                                                = 3715,
-    SE_SMMU1_CPU_RDAT0r                                                   = 3716,
-    SE_SMMU1_CPU_RDAT1r                                                   = 3717,
-    SE_SMMU1_CPU_RDAT2r                                                   = 3718,
-    SE_SMMU1_CPU_RDAT3r                                                   = 3719,
-    SE_SMMU1_CPU_RDAT4r                                                   = 3720,
-    SE_SMMU1_CPU_RDAT5r                                                   = 3721,
-    SE_SMMU1_CPU_RDAT6r                                                   = 3722,
-    SE_SMMU1_CPU_RDAT7r                                                   = 3723,
-    SE_SMMU1_CPU_RDAT8r                                                   = 3724,
-    SE_SMMU1_CPU_RDAT9r                                                   = 3725,
-    SE_SMMU1_CPU_RDAT10r                                                  = 3726,
-    SE_SMMU1_CPU_RDAT11r                                                  = 3727,
-    SE_SMMU1_CPU_RDAT12r                                                  = 3728,
-    SE_SMMU1_CPU_RDAT13r                                                  = 3729,
-    SE_SMMU1_CPU_RDAT14r                                                  = 3730,
-    SE_SMMU1_CPU_RDAT15r                                                  = 3731,
-    SE_SMMU1_CTRL_CPU_RD_RDYr                                             = 3732,
-    SE_SMMU1_CPU_WARBI_RDY_CFGr                                           = 3733,
-    SE_SMMU1_DIR_ARBI_CPU_RPFULr                                          = 3734,
-    SE_SMMU1_DIR_ARBI_WPFULr                                              = 3735,
-    SE_SMMU1_CFG_WR_ARBI_PFUL0r                                           = 3736,
-    SE_SMMU1_CFG_WR_ARBI_PFUL1r                                           = 3737,
-    SE_SMMU1_SMMU1_WDONE_PFUL_CFGr                                        = 3738,
-    SE_SMMU1_STAT_RATE_CFG_CNTr                                           = 3739,
-    SE_SMMU1_FTM_RATE_CFG_CNTr                                            = 3740,
-    SE_SMMU1_ETM_RATE_CFG_CNTr                                            = 3741,
-    SE_SMMU1_DIR_RATE_CFG_CNTr                                            = 3742,
-    SE_SMMU1_HASH_RATE_CFG_CNTr                                           = 3743,
-    SE_SMMU1_FTM_TBL_CFGr                                                 = 3744,
-    SE_SMMU1_LPM_V4_AS_TBL_CFGr                                           = 3745,
-    SE_SMMU1_LPM_V4_TBL_CFGr                                              = 3746,
-    SE_SMMU1_LPM_V6_TBL_CFGr                                              = 3747,
-    SE_SMMU1_LPM_V6_AS_TBL_CFGr                                           = 3748,
-    SE_SMMU1_DMA_TBL_CFGr                                                 = 3749,
-    SE_SMMU1_OAM_TBL_CFGr                                                 = 3750,
-    SE_SMMU1_CTRL_RPAR_CPU_PFULr                                          = 3751,
-    SE_SMMU1_CFG_KSCH_DIR_PFULr                                           = 3752,
-    SE_SMMU1_CFG_KSCH_HASH_PFULr                                          = 3753,
-    SE_SMMU1_CFG_KSCH_LPM_PFULr                                           = 3754,
-    SE_SMMU1_CFG_KSCH_LPM_AS_PFULr                                        = 3755,
-    SE_SMMU1_CFG_KSCH_STAT_PFULr                                          = 3756,
-    SE_SMMU1_CFG_KSCH_TM_PFULr                                            = 3757,
-    SE_SMMU1_CFG_KSCH_OAM_PFULr                                           = 3758,
-    SE_SMMU1_CFG_KSCH_DMA_PFULr                                           = 3759,
-    SE_SMMU1_CTRL_WFIFO_CFGr                                              = 3760,
-    SE_SMMU1_RSCH_HASH_PTR_CFGr                                           = 3761,
-    SE_SMMU1_RSCH_LPM_PTR_CFGr                                            = 3762,
-    SE_SMMU1_RSCH_LPM_AS_PTR_CFGr                                         = 3763,
-    SE_SMMU1_RSCH_STAT_PTR_CFGr                                           = 3764,
-    SE_SMMU1_RSCH_OAM_PTR_CFGr                                            = 3765,
-    SE_SMMU1_RSCHD_FIFO_PEPT_CFGr                                         = 3766,
-    SE_SMMU1_DIR_FIFO_PFUL_CFGr                                           = 3767,
-    SE_SMMU1_HASH_FIFO_PFUL_CFGr                                          = 3768,
-    SE_SMMU1_LPM_FIFO_PFUL_CFGr                                           = 3769,
-    SE_SMMU1_LPM_AS_FIFO_PFUL_CFGr                                        = 3770,
-    SE_SMMU1_STAT_FIFO_PFUL_CFGr                                          = 3771,
-    SE_SMMU1_FTM_FIFO_PFUL_CFGr                                           = 3772,
-    SE_SMMU1_ETM_FIFO_PFUL_CFGr                                           = 3773,
-    SE_SMMU1_OAM_FIFO_PFUL_CFGr                                           = 3774,
-    SE_SMMU1_DMA_FIFO_PFUL_CFGr                                           = 3775,
-    SE_SMMU1_CACHE_RSP_RR_FIFO_CFGr                                       = 3776,
-    SE_SMMU1_DDR_RSP_RR_FIFO_CFGr                                         = 3777,
-    SE_SMMU1_CPU_CAHCE_FIFO_CFGr                                          = 3778,
-    SE_SMMU1_CACHE_RSP_FIFO_CFGr                                          = 3779,
-    SE_SMMU1_TEST_STATEr                                                  = 3780,
-    SE_SMMU1_CACHE_FIFO_EPTr                                              = 3781,
-    SE_SMMU1_RR_FIFO_EPTr                                                 = 3782,
-    SE_SMMU1_WR_FIFO_EPTr                                                 = 3783,
-    SE_SMMU1_WDONE_FIFO_EPTr                                              = 3784,
-    SE_SMMU1_KSCHD_FIFO_EPT0r                                             = 3785,
-    SE_SMMU1_CASH_FIFO_EPTr                                               = 3786,
-    SE_SMMU1_CTRL_FIFO_EPTr                                               = 3787,
-    SE_SMMU1_SMMU1_RSCHD_EPT3r                                            = 3788,
-    SE_SMMU1_SMMU1_RSCHD_EPT2r                                            = 3789,
-    SE_SMMU1_SMMU1_RSCHD_EPT1r                                            = 3790,
-    SE_SMMU1_SMMU1_RSCHD_EPT0r                                            = 3791,
-    SE_SMMU1_CASH0_ECC_ERR_ADDRr                                          = 3792,
-    SE_SMMU1_ARBI_CPU_WR_RDYr                                             = 3793,
-    SE_SMMU1_SMMU1_INT_0_ENr                                              = 3794,
-    SE_SMMU1_SMMU1_INT_0_MASKr                                            = 3795,
-    SE_SMMU1_SMMU1_INT_1_ENr                                              = 3796,
-    SE_SMMU1_SMMU1_INT_1_MASKr                                            = 3797,
-    SE_SMMU1_SMMU1_INT_2_ENr                                              = 3798,
-    SE_SMMU1_SMMU1_INT_2_MASKr                                            = 3799,
-    SE_SMMU1_SMMU1_INT_3_ENr                                              = 3800,
-    SE_SMMU1_SMMU1_INT_3_MASKr                                            = 3801,
-    SE_SMMU1_SMMU1_INT_0_STATUSr                                          = 3802,
-    SE_SMMU1_SMMU1_INT_1_STATUSr                                          = 3803,
-    SE_SMMU1_SMMU1_INT_2_STATUSr                                          = 3804,
-    SE_SMMU1_SMMU1_INT_3_STATUSr                                          = 3805,
-    SE_SMMU1_SMMU1_INT_STATUSr                                            = 3806,
-    SE_SMMU1_CTRL_TO_CASH7_0_FC_CNTr                                      = 3807,
-    SE_SMMU1_CASH7_0_TO_CTRL_REQ_CNTr                                     = 3808,
-    SE_SMMU1_RSCHD_TO_CACHE7_FC_CNTr                                      = 3809,
-    SE_SMMU1_CASH7_TO_CACHE_RSP_CNTr                                      = 3810,
-    SE_SMMU1_CASH7_TO_CTRL_FC_CNTr                                        = 3811,
-    SE_SMMU1_CTRL_TO_CASH7_0_RSP_CNTr                                     = 3812,
-    SE_SMMU1_KSCHD_TO_CACHE7_0_REQ_CNTr                                   = 3813,
-    SE_SMMU1_CACHE7_0_TO_KSCHD_FC_CNTr                                    = 3814,
-    SE_SMMU1_DMA_TO_SMMU1_RD_REQ_CNTr                                     = 3815,
-    SE_SMMU1_OAM_TO_KSCHD_REQ_CNTr                                        = 3816,
-    SE_SMMU1_OAM_RR_STATE_RSP_CNTr                                        = 3817,
-    SE_SMMU1_OAM_CLASH_INFO_CNTr                                          = 3818,
-    SE_SMMU1_OAM_TO_RR_REQ_CNTr                                           = 3819,
-    SE_SMMU1_LPM_AS_TO_KSCHD_REQ_CNTr                                     = 3820,
-    SE_SMMU1_LPM_AS_RR_STATE_RSP_CNTr                                     = 3821,
-    SE_SMMU1_LPM_AS_CLASH_INFO_CNTr                                       = 3822,
-    SE_SMMU1_LPM_AS_TO_RR_REQ_CNTr                                        = 3823,
-    SE_SMMU1_LPM_TO_KSCHD_REQ_CNTr                                        = 3824,
-    SE_SMMU1_LPM_RR_STATE_RSP_CNTr                                        = 3825,
-    SE_SMMU1_LPM_CLASH_INFO_CNTr                                          = 3826,
-    SE_SMMU1_LPM_TO_RR_REQ_CNTr                                           = 3827,
-    SE_SMMU1_HASH3_0_TO_KSCHD_REQ_CNTr                                    = 3828,
-    SE_SMMU1_HASH3_0_RR_STATE_RSP_CNTr                                    = 3829,
-    SE_SMMU1_HASH3_0_CLASH_INFO_CNTr                                      = 3830,
-    SE_SMMU1_HASH3_0_TO_RR_REQ_CNTr                                       = 3831,
-    SE_SMMU1_DIR3_0_TO_KSCHD_REQ_CNTr                                     = 3832,
-    SE_SMMU1_DIR3_0_CLASH_INFO_CNTr                                       = 3833,
-    SE_SMMU1_DIR_TBL_WR_REQ_CNTr                                          = 3834,
-    SE_SMMU1_WARBI_TO_DIR_TBL_WARBI_FC_CNTr                               = 3835,
-    SE_SMMU1_DIR3_0_TO_BANK_RR_REQ_CNTr                                   = 3836,
-    SE_SMMU1_KSCHD_TO_DIR3_0_FC_CNTr                                      = 3837,
-    SE_SMMU1_DIR3_0_RR_STATE_RSP_CNTr                                     = 3838,
-    SE_SMMU1_WR_DONE_TO_WARBI_FC_CNTr                                     = 3839,
-    SE_SMMU1_WR_DONE_PTR_REQ_CNTr                                         = 3840,
-    SE_SMMU1_CTRL7_0_TO_WARBI_FC_CNTr                                     = 3841,
-    SE_SMMU1_WARBI_TO_CTRL7_0_WR_REQ_CNTr                                 = 3842,
-    SE_SMMU1_WARBI_TO_CASH7_0_WR_REQ_CNTr                                 = 3843,
-    SE_SMMU1_WARBI_TO_CPU_WR_FC_CNTr                                      = 3844,
-    SE_SMMU1_CPU_WR_REQ_CNTr                                              = 3845,
-    SE_SMMU1_CTRL7_0_TO_CPU_RD_RSP_CNTr                                   = 3846,
-    SE_SMMU1_CPU_TO_CTRL7_0_RD_REQ_CNTr                                   = 3847,
-    SE_SMMU1_CPU_RD_DIR_TBL_RSP_CNTr                                      = 3848,
-    SE_SMMU1_CPU_TO_DIR_TBL_RD_WR_REQ_CNTr                                = 3849,
-    SE_SMMU1_SMMU1_TO_MMU_7_0_RSP_FC_CNTr                                 = 3850,
-    SE_SMMU1_MMU_7_0_TO_SMMU1_RD_RSP_CNTr                                 = 3851,
-    SE_SMMU1_MMU_7_0_TO_SMMU1_RD_FC_CNTr                                  = 3852,
-    SE_SMMU1_SMMU1_TO_MMU_7_RD_REQ_CNTr                                   = 3853,
-    SE_SMMU1_MMU_7_TO_SMMU1_WR_FC_CNTr                                    = 3854,
-    SE_SMMU1_SMMU1_TO_MMU_7_0_WR_REQ_CNTr                                 = 3855,
-    SE_SMMU1_SE_TO_SMMU1_WR_RSP_FC_CNTr                                   = 3856,
-    SE_SMMU1_SMMU1_TO_SE_WR_RSP_CNTr                                      = 3857,
-    SE_SMMU1_DDR7_0_WR_RSP_CNTr                                           = 3858,
-    SE_SMMU1_SMMU1_TO_AS_FC_CNTr                                          = 3859,
-    SE_SMMU1_AS_TO_SMMU1_WR_REQ_CNTr                                      = 3860,
-    SE_SMMU1_SMMU1_TO_SE_PARSER_FC_CNTr                                   = 3861,
-    SE_SMMU1_SE_PARSER_TO_SMMU1_REQ_CNTr                                  = 3862,
-    SE_SMMU1_SMMU1_TO_ETM_WR_FC_CNTr                                      = 3863,
-    SE_SMMU1_ETM_WR_REQ_CNTr                                              = 3864,
-    SE_SMMU1_SMMU1_TO_FTM_WR_FC_CNTr                                      = 3865,
-    SE_SMMU1_FTM_WR_REQ_CNTr                                              = 3866,
-    SE_SMMU1_SMMU1_TO_STATE_WR_FC_CNTr                                    = 3867,
-    SE_SMMU1_STATE_WR_REQ_CNTr                                            = 3868,
-    SE_SMMU1_SE_TO_DMA_RSP_CNTr                                           = 3869,
-    SE_SMMU1_SE_TO_DMA_FC_CNTr                                            = 3870,
-    SE_SMMU1_OAM_TO_SMMU1_FC_CNTr                                         = 3871,
-    SE_SMMU1_SMMU1_TO_OAM_RSP_CNTr                                        = 3872,
-    SE_SMMU1_SMMU1_TO_OAM_FC_CNTr                                         = 3873,
-    SE_SMMU1_OAM_TO_SMMU1_REQ_CNTr                                        = 3874,
-    SE_SMMU1_SMMU1_TO_ETM_RSP_CNTr                                        = 3875,
-    SE_SMMU1_SMMU1_TO_FTM_RSP_CNTr                                        = 3876,
-    SE_SMMU1_SMMU1_TO_ETM_FC_CNTr                                         = 3877,
-    SE_SMMU1_ETM_TO_SMMU1_REQ_CNTr                                        = 3878,
-    SE_SMMU1_SMMU1_TO_FTM_FC_CNTr                                         = 3879,
-    SE_SMMU1_FTM_TO_SMMU1_REQ_CNTr                                        = 3880,
-    SE_SMMU1_SMMU1_TO_STAT_RSP_CNTr                                       = 3881,
-    SE_SMMU1_SMMU1_TO_STAT_FC_CNTr                                        = 3882,
-    SE_SMMU1_STAT_TO_SMMU1_REQ_CNTr                                       = 3883,
-    SE_SMMU1_LPM_AS_TO_SMMU1_FC_CNTr                                      = 3884,
-    SE_SMMU1_LPM_TO_SMMU1_FC_CNTr                                         = 3885,
-    SE_SMMU1_SMMU1_TO_LPM_AS_RSP_CNTr                                     = 3886,
-    SE_SMMU1_SMMU1_TO_LPM_RSP_CNTr                                        = 3887,
-    SE_SMMU1_SMMU1_TO_LPM_AS_FC_CNTr                                      = 3888,
-    SE_SMMU1_SMMU1_TO_LPM_FC_CNTr                                         = 3889,
-    SE_SMMU1_LPM_AS_TO_SMMU1_REQ_CNTr                                     = 3890,
-    SE_SMMU1_LPM_TO_SMMU1_REQ_CNTr                                        = 3891,
-    SE_SMMU1_HASH3_0_TO_SMMU1_FC_CNTr                                     = 3892,
-    SE_SMMU1_SMMU1_TO_HASH3_0_RSP_CNTr                                    = 3893,
-    SE_SMMU1_SMMU1_TO_HASH3_0_FC_CNTr                                     = 3894,
-    SE_SMMU1_HASH3_0_TO_SMMU1_CNTr                                        = 3895,
-    SE_SMMU1_SE_TO_SMMU1_DIR3_0_RSP_FC_CNTr                               = 3896,
-    SE_SMMU1_SMMU1_TO_SE_DIR3_0_RSP_CNTr                                  = 3897,
-    SE_SMMU1_SMMU1_TO_SE_DIR3_0_FC_CNTr                                   = 3898,
-    SE_SMMU1_SE_TO_SMMU1_DIR3_0_CNTr                                      = 3899,
-    SE_SMMU1_CACHE7_0_TO_RSCHD_RSP_CNTr                                   = 3900,
-    SE_CMMU_DDR_RW_ADDRr                                                  = 3901,
-    SE_CMMU_DDR_RW_MODEr                                                  = 3902,
-    SE_CMMU_CP_CMDr                                                       = 3903,
-    SE_CMMU_CPU_IND_RD_DONEr                                              = 3904,
-    SE_CMMU_CPU_IND_RDAT0r                                                = 3905,
-    SE_CMMU_CPU_IND_RDAT1r                                                = 3906,
-    SE_CMMU_CPU_IND_RDAT2r                                                = 3907,
-    SE_CMMU_CPU_IND_RDAT3r                                                = 3908,
-    SE_CMMU_CPU_DDR_FIFO_ALMFULr                                          = 3909,
-    SE_CMMU_DEBUG_CNT_MODEr                                               = 3910,
-    SE_CMMU_CMMU_PFUL_CFGr                                                = 3911,
-    SE_CMMU_CMMU_STAT_PFUL_CFGr                                           = 3912,
-    SE_CMMU_STAT_OVERFLOW_MODEr                                           = 3913,
-    SE_CMMU_CMMU_CP_FIFO_PFULr                                            = 3914,
-    SE_CMMU_DDR_WR_DAT0r                                                  = 3915,
-    SE_CMMU_DDR_WR_DAT1r                                                  = 3916,
-    SE_CMMU_CMMU_INT_UNMASK_FLAGr                                         = 3917,
-    SE_CMMU_CMMU_INT_ENr                                                  = 3918,
-    SE_CMMU_CMMU_INT_MASKr                                                = 3919,
-    SE_CMMU_CMMU_INT_STATUSr                                              = 3920,
-    SE_CMMU_STAT_CMMU_REQ_CNTr                                            = 3921,
-    SE_CMMU_CMMU_FC0_CNTr                                                 = 3922,
-    SE_CMMU_CMMU_FC1_CNTr                                                 = 3923,
-    SE_CMMU_CMMU_FC2_CNTr                                                 = 3924,
-    SMMU14K_SE_SMMU1_HASH0_TBL0_CFGr                                      = 3925,
-    SMMU14K_SE_SMMU1_HASH0_TBL1_CFGr                                      = 3926,
-    SMMU14K_SE_SMMU1_HASH0_TBL2_CFGr                                      = 3927,
-    SMMU14K_SE_SMMU1_HASH0_TBL3_CFGr                                      = 3928,
-    SMMU14K_SE_SMMU1_HASH0_TBL4_CFGr                                      = 3929,
-    SMMU14K_SE_SMMU1_HASH0_TBL5_CFGr                                      = 3930,
-    SMMU14K_SE_SMMU1_HASH0_TBL6_CFGr                                      = 3931,
-    SMMU14K_SE_SMMU1_HASH0_TBL7_CFGr                                      = 3932,
-    SMMU14K_SE_SMMU1_HASH1_TBL0_CFGr                                      = 3933,
-    SMMU14K_SE_SMMU1_HASH1_TBL1_CFGr                                      = 3934,
-    SMMU14K_SE_SMMU1_HASH1_TBL2_CFGr                                      = 3935,
-    SMMU14K_SE_SMMU1_HASH1_TBL3_CFGr                                      = 3936,
-    SMMU14K_SE_SMMU1_HASH1_TBL4_CFGr                                      = 3937,
-    SMMU14K_SE_SMMU1_HASH1_TBL5_CFGr                                      = 3938,
-    SMMU14K_SE_SMMU1_HASH1_TBL6_CFGr                                      = 3939,
-    SMMU14K_SE_SMMU1_HASH1_TBL7_CFGr                                      = 3940,
-    SMMU14K_SE_SMMU1_HASH2_TBL0_CFGr                                      = 3941,
-    SMMU14K_SE_SMMU1_HASH2_TBL1_CFGr                                      = 3942,
-    SMMU14K_SE_SMMU1_HASH2_TBL2_CFGr                                      = 3943,
-    SMMU14K_SE_SMMU1_HASH2_TBL3_CFGr                                      = 3944,
-    SMMU14K_SE_SMMU1_HASH2_TBL4_CFGr                                      = 3945,
-    SMMU14K_SE_SMMU1_HASH2_TBL5_CFGr                                      = 3946,
-    SMMU14K_SE_SMMU1_HASH2_TBL6_CFGr                                      = 3947,
-    SMMU14K_SE_SMMU1_HASH2_TBL7_CFGr                                      = 3948,
-    SMMU14K_SE_SMMU1_HASH3_TBL0_CFGr                                      = 3949,
-    SMMU14K_SE_SMMU1_HASH3_TBL1_CFGr                                      = 3950,
-    SMMU14K_SE_SMMU1_HASH3_TBL2_CFGr                                      = 3951,
-    SMMU14K_SE_SMMU1_HASH3_TBL3_CFGr                                      = 3952,
-    SMMU14K_SE_SMMU1_HASH3_TBL4_CFGr                                      = 3953,
-    SMMU14K_SE_SMMU1_HASH3_TBL5_CFGr                                      = 3954,
-    SMMU14K_SE_SMMU1_HASH3_TBL6_CFGr                                      = 3955,
-    SMMU14K_SE_SMMU1_HASH3_TBL7_CFGr                                      = 3956,
-    STAT_STAT_CFG_CPU_IND_ERAM_WDAT1r                                     = 3957,
-    STAT_STAT_CFG_CPU_IND_ERAM_WDAT2r                                     = 3958,
-    STAT_STAT_CFG_CPU_IND_ERAM_WDAT3r                                     = 3959,
-    STAT_STAT_CFG_CPU_IND_ERAM_REQ_INFOr                                  = 3960,
-    STAT_STAT_CFG_CPU_IND_ERAM_RD_DONEr                                   = 3961,
-    STAT_STAT_CFG_CPU_IND_ERAM_RDAT0r                                     = 3962,
-    STAT_STAT_CFG_CPU_IND_ERAM_RDAT1r                                     = 3963,
-    STAT_STAT_CFG_CPU_IND_ERAM_RDAT2r                                     = 3964,
-    STAT_STAT_CFG_CPU_IND_ERAM_RDAT3r                                     = 3965,
-    STAT_STAT_CFG_TM_ALU_ERAM_CPU_RDYr                                    = 3966,
-    STAT_STAT_CFG_OAM_STAT_CFGr                                           = 3967,
-    STAT_STAT_CFG_FTM_PORT_SEL_CFGr                                       = 3968,
-    STAT_STAT_CFG_OAM_ERAM_BASE_ADDRr                                     = 3969,
-    STAT_STAT_CFG_OAM_LM_ERAM_BASE_ADDRr                                  = 3970,
-    STAT_STAT_CFG_OAM_DDR_BASE_ADDRr                                      = 3971,
-    STAT_STAT_CFG_PLCR0_SCHD_PFUL_CFGr                                    = 3972,
-    STAT_STAT_CFG_OAM_LM_ORD_PFUL_CFGr                                    = 3973,
-    STAT_STAT_CFG_DDR_SCHD_PFUL_CFGr                                      = 3974,
-    STAT_STAT_CFG_ERAM_SCHD_PFUL_CFGr                                     = 3975,
-    STAT_STAT_CFG_ERAM_SCHD_PEPT_CFGr                                     = 3976,
-    STAT_STAT_CFG_ERAM_SCHD_OAM_PFUL_CFGr                                 = 3977,
-    STAT_STAT_CFG_ERAM_SCHD_OAM_PEPT_CFGr                                 = 3978,
-    STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PFUL_CFGr                              = 3979,
-    STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PEPT_CFGr                              = 3980,
-    STAT_STAT_CFG_RSCHD_PFUL_CFGr                                         = 3981,
-    STAT_STAT_CFG_RSCHD_PEPT_CFGr                                         = 3982,
-    STAT_STAT_CFG_RSCHD_PLCR_PFUL_CFGr                                    = 3983,
-    STAT_STAT_CFG_RSCHD_PLCR_PEPT_CFGr                                    = 3984,
-    STAT_STAT_CFG_RSCHD_PLCR_INFO_PFUL_CFGr                               = 3985,
-    STAT_STAT_CFG_ALU_ARB_CPU_PFUL_CFGr                                   = 3986,
-    STAT_STAT_CFG_ALU_ARB_USER_PFUL_CFGr                                  = 3987,
-    STAT_STAT_CFG_ALU_ARB_STAT_PFUL_CFGr                                  = 3988,
-    STAT_STAT_CFG_CYCMOV_DAT_PFUL_CFGr                                    = 3989,
-    STAT_STAT_CFG_DDR_OPR_PFUL_CFGr                                       = 3990,
-    STAT_STAT_CFG_CYCLE_MOV_PFUL_CFGr                                     = 3991,
-    STAT_STAT_CFG_CNTOVF_PFUL_CFGr                                        = 3992,
-    STAT_STAT_CFG_ERAM_SCHD_PLCR_PFUL_CFGr                                = 3993,
-    STAT_STAT_CFG_ERAM_SCHD_PLCR_PEPT_CFGr                                = 3994,
-    STAT_STAT_CFG_DEBUG_CNT_MODEr                                         = 3995,
-    STAT_STAT_CFG_TM_MOV_PERIOD_CFGr                                      = 3996,
-    STAT_STAT_CFG_ALU_DDR_CPU_REQ_PFUL_CFGr                               = 3997,
-    STAT_STAT_CFG_CYCMOV_ADDR_PFUL_CFGr                                   = 3998,
-    STAT_STAT_CFG_ORD_DDR_PLCR_FIFO_EMPTYr                                = 3999,
-    STAT_STAT_CFG_TM_STAT_FIFO_EMPTYr                                     = 4000,
-    STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_0_1r                               = 4001,
-    STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_2_3r                               = 4002,
-    STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_4_5r                               = 4003,
-    STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_6_7r                               = 4004,
-    STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_FREE_8r                            = 4005,
-    STAT_STAT_CFG_RSCHD_FIFO_EMPTY_0_3r                                   = 4006,
-    STAT_STAT_CFG_RSCHD_FIFO_EMPTY_4_7r                                   = 4007,
-    STAT_STAT_CFG_RSCHD_FIFO_EMPTY_8_11r                                  = 4008,
-    STAT_STAT_CFG_RSCHD_FIFO_EMPTY_12_15r                                 = 4009,
-    STAT_STAT_CFG_RSCHD_FIFO_EMPTY_PLCR_16_17r                            = 4010,
-    STAT_STAT_CFG_STAT_INT_UNMASK_FLAGr                                   = 4011,
-    STAT_STAT_CFG_STAT_INT0_ENr                                           = 4012,
-    STAT_STAT_CFG_STAT_INT0_MASKr                                         = 4013,
-    STAT_STAT_CFG_STAT_INT0_STATUSr                                       = 4014,
-    STAT_STAT_CFG_STAT_INT1_ENr                                           = 4015,
-    STAT_STAT_CFG_STAT_INT1_MASKr                                         = 4016,
-    STAT_STAT_CFG_STAT_INT1_STATUSr                                       = 4017,
-    STAT_STAT_CFG_STAT_INT2_ENr                                           = 4018,
-    STAT_STAT_CFG_STAT_INT2_MASKr                                         = 4019,
-    STAT_STAT_CFG_STAT_INT2_STATUSr                                       = 4020,
-    STAT_STAT_CFG_STAT_INT3_ENr                                           = 4021,
-    STAT_STAT_CFG_STAT_INT3_MASKr                                         = 4022,
-    STAT_STAT_CFG_STAT_INT3_STATUSr                                       = 4023,
-    STAT_STAT_CFG_STAT_INT4_ENr                                           = 4024,
-    STAT_STAT_CFG_STAT_INT4_MASKr                                         = 4025,
-    STAT_STAT_CFG_STAT_INT4_STATUSr                                       = 4026,
-    STAT_STAT_CFG_STAT_INT5_ENr                                           = 4027,
-    STAT_STAT_CFG_STAT_INT5_MASKr                                         = 4028,
-    STAT_STAT_CFG_STAT_INT5_STATUSr                                       = 4029,
-    STAT_STAT_CFG_RSCHD_ECC_BYPASSr                                       = 4030,
-    STAT_STAT_CFG_RSCHD_ECC_SINGLE_ERRr                                   = 4031,
-    STAT_STAT_CFG_RSCHD_ECC_DOUBLE_ERRr                                   = 4032,
-    STAT_STAT_CFG_CPU_IND_DDR_WDAT0r                                      = 4033,
-    STAT_STAT_CFG_CPU_IND_DDR_WDAT1r                                      = 4034,
-    STAT_STAT_CFG_CPU_IND_DDR_WDAT2r                                      = 4035,
-    STAT_STAT_CFG_CPU_IND_DDR_WDAT3r                                      = 4036,
-    STAT_STAT_CFG_CPU_IND_DDR_WDAT4r                                      = 4037,
-    STAT_STAT_CFG_CPU_IND_DDR_WDAT5r                                      = 4038,
-    STAT_STAT_CFG_CPU_IND_DDR_WDAT6r                                      = 4039,
-    STAT_STAT_CFG_CPU_IND_DDR_WDAT7r                                      = 4040,
-    STAT_STAT_CFG_CPU_IND_DDR_WDAT8r                                      = 4041,
-    STAT_STAT_CFG_CPU_IND_DDR_WDAT9r                                      = 4042,
-    STAT_STAT_CFG_CPU_IND_DDR_WDAT10r                                     = 4043,
-    STAT_STAT_CFG_CPU_IND_DDR_WDAT11r                                     = 4044,
-    STAT_STAT_CFG_CPU_IND_DDR_WDAT12r                                     = 4045,
-    STAT_STAT_CFG_CPU_IND_DDR_WDAT13r                                     = 4046,
-    STAT_STAT_CFG_CPU_IND_DDR_WDAT14r                                     = 4047,
-    STAT_STAT_CFG_CPU_IND_DDR_WDAT15r                                     = 4048,
-    STAT_STAT_CFG_CPU_IND_DDR_REQ_INFOr                                   = 4049,
-    STAT_STAT_CFG_CPU_IND_DDR_RD_DONEr                                    = 4050,
-    STAT_STAT_CFG_CPU_IND_DDR_RDAT0r                                      = 4051,
-    STAT_STAT_CFG_CPU_IND_DDR_RDAT1r                                      = 4052,
-    STAT_STAT_CFG_CPU_IND_DDR_RDAT2r                                      = 4053,
-    STAT_STAT_CFG_CPU_IND_DDR_RDAT3r                                      = 4054,
-    STAT_STAT_CFG_CPU_IND_DDR_RDAT4r                                      = 4055,
-    STAT_STAT_CFG_CPU_IND_DDR_RDAT5r                                      = 4056,
-    STAT_STAT_CFG_CPU_IND_DDR_RDAT6r                                      = 4057,
-    STAT_STAT_CFG_CPU_IND_DDR_RDAT7r                                      = 4058,
-    STAT_STAT_CFG_CPU_IND_DDR_RDAT8r                                      = 4059,
-    STAT_STAT_CFG_CPU_IND_DDR_RDAT9r                                      = 4060,
-    STAT_STAT_CFG_CPU_IND_DDR_RDAT10r                                     = 4061,
-    STAT_STAT_CFG_CPU_IND_DDR_RDAT11r                                     = 4062,
-    STAT_STAT_CFG_CPU_IND_DDR_RDAT12r                                     = 4063,
-    STAT_STAT_CFG_CPU_IND_DDR_RDAT13r                                     = 4064,
-    STAT_STAT_CFG_CPU_IND_DDR_RDAT14r                                     = 4065,
-    STAT_STAT_CFG_CPU_IND_DDR_RDAT15r                                     = 4066,
-    STAT_STAT_CFG_TM_ALU_DDR_CPU_RDYr                                     = 4067,
-    STAT_STAT_CFG_EPT_FLAGr                                               = 4068,
-    STAT_STAT_CFG_PPU_SOFT_RSTr                                           = 4069,
-    STAT_STAT_CFG_STAT_SMMU0_FC15_0_CNTr                                  = 4070,
-    STAT_STAT_CFG_SMMU0_STAT_FC15_0_CNTr                                  = 4071,
-    STAT_STAT_CFG_SMMU0_STAT_RSP15_0_CNTr                                 = 4072,
-    STAT_STAT_CFG_STAT_SMMU0_REQ15_0_CNTr                                 = 4073,
-    STAT_STAT_CFG_PPU_STAT_MEC5_0_RSP_FC_CNTr                             = 4074,
-    STAT_STAT_CFG_STAT_PPU_MEC5_0_KEY_FC_CNTr                             = 4075,
-    STAT_STAT_CFG_STAT_PPU_MEC5_0_RSP_CNTr                                = 4076,
-    STAT_STAT_CFG_PPU_STAT_MEC5_0_KEY_CNTr                                = 4077,
-    STAT_STAT_CFG_PPU5_0_NO_EXIST_OPCD_EX_CNTr                            = 4078,
-    STAT_STAT_CFG_SE_ETM_STAT_WR_FC_CNTr                                  = 4079,
-    STAT_STAT_CFG_SE_ETM_STAT_RD_FC_CNTr                                  = 4080,
-    STAT_STAT_CFG_STAT_ETM_DEQ_FC_CNTr                                    = 4081,
-    STAT_STAT_CFG_STAT_ETM_ENQ_FC_CNTr                                    = 4082,
-    STAT_STAT_CFG_STAT_OAM_LM_FC_CNTr                                     = 4083,
-    STAT_STAT_CFG_OAM_STAT_LM_FC_CNTr                                     = 4084,
-    STAT_STAT_CFG_STAT_OAM_FC_CNTr                                        = 4085,
-    STAT_STAT_CFG_CMMU_STAT_FC_CNTr                                       = 4086,
-    STAT_STAT_CFG_STAT_CMMU_REQ_CNTr                                      = 4087,
-    STAT_STAT_CFG_SMMU0_PLCR_RSP0_CNTr                                    = 4088,
-    STAT_STAT_CFG_PLCR_SMMU0_REQ0_CNTr                                    = 4089,
-    STAT_STAT_CFG_STAT_OAM_LM_RSP_CNTr                                    = 4090,
-    STAT_STAT_CFG_OAM_STAT_LM_REQ_CNTr                                    = 4091,
-    STAT_STAT_CFG_OAM_STAT_REQ_CNTr                                       = 4092,
-    STAT_STAT_CFG_SE_ETM_STAT_RSP_CNTr                                    = 4093,
-    STAT_STAT_CFG_ETM_STAT_SE_WR_REQ_CNTr                                 = 4094,
-    STAT_STAT_CFG_ETM_STAT_SE_RD_REQ_CNTr                                 = 4095,
-    STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT0r                                = 4096,
-    STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT1r                                = 4097,
-    STAT_STAT_CFG_TM_STAT_ERAM_CPU_RSP_CNTr                               = 4098,
-    STAT_STAT_CFG_CPU_RD_ERAM_REQ_CNTr                                    = 4099,
-    STAT_STAT_CFG_CPU_WR_ERAM_REQ_CNTr                                    = 4100,
-    STAT_STAT_CFG_TM_STAT_DDR_CPU_RSP_CNTr                                = 4101,
-    STAT_STAT_CFG_CPU_RD_DDR_REQ_CNTr                                     = 4102,
-    STAT_STAT_CFG_CPU_WR_DDR_REQ_CNTr                                     = 4103,
-    STAT_ETCAM_CPU_IND_WDAT1r                                             = 4104,
-    STAT_ETCAM_CPU_IND_WDAT2r                                             = 4105,
-    STAT_ETCAM_CPU_IND_WDAT3r                                             = 4106,
-    STAT_ETCAM_CPU_IND_WDAT4r                                             = 4107,
-    STAT_ETCAM_CPU_IND_WDAT5r                                             = 4108,
-    STAT_ETCAM_CPU_IND_WDAT6r                                             = 4109,
-    STAT_ETCAM_CPU_IND_WDAT7r                                             = 4110,
-    STAT_ETCAM_CPU_IND_WDAT8r                                             = 4111,
-    STAT_ETCAM_CPU_IND_WDAT9r                                             = 4112,
-    STAT_ETCAM_CPU_IND_WDAT10r                                            = 4113,
-    STAT_ETCAM_CPU_IND_WDAT11r                                            = 4114,
-    STAT_ETCAM_CPU_IND_WDAT12r                                            = 4115,
-    STAT_ETCAM_CPU_IND_WDAT13r                                            = 4116,
-    STAT_ETCAM_CPU_IND_WDAT14r                                            = 4117,
-    STAT_ETCAM_CPU_IND_WDAT15r                                            = 4118,
-    STAT_ETCAM_CPU_IND_WDAT16r                                            = 4119,
-    STAT_ETCAM_CPU_IND_WDAT17r                                            = 4120,
-    STAT_ETCAM_CPU_IND_WDAT18r                                            = 4121,
-    STAT_ETCAM_CPU_IND_WDAT19r                                            = 4122,
-    STAT_ETCAM_T_STRWC_CFGr                                               = 4123,
-    STAT_ETCAM_ETCAM_INT_UNMASK_FLAGr                                     = 4124,
-    STAT_ETCAM_ETCAM_INT_EN0r                                             = 4125,
-    STAT_ETCAM_ETCAM_INT_MASK0r                                           = 4126,
-    STAT_ETCAM_ETCAM_INT_STATUSr                                          = 4127,
-    STAT_ETCAM_INT_TB_INI_OKr                                             = 4128,
-    STAT_ETCAM_ETCAM_CLK_ENr                                              = 4129,
-    STAT_ETCAM_AS_ETCAM_REQ0_CNTr                                         = 4130,
-    STAT_ETCAM_AS_ETCAM_REQ1_CNTr                                         = 4131,
-    STAT_ETCAM_ETCAM_AS_INDEX0_CNTr                                       = 4132,
-    STAT_ETCAM_ETCAM_AS_INDEX1_CNTr                                       = 4133,
-    STAT_ETCAM_ETCAM_NOT_HIT0_CNTr                                        = 4134,
-    STAT_ETCAM_ETCAM_NOT_HIT1_CNTr                                        = 4135,
-    STAT_ETCAM_TABLE_ID_NOT_MATCH_CNTr                                    = 4136,
-    STAT_ETCAM_TABLE_ID_CLASH01_CNTr                                      = 4137,
-    STAT_ETCAM_ETCAM_CPU_FLr                                              = 4138,
-    STAT_ETCAM_ETCAM_ARB_EMPTYr                                           = 4139,
-    DTB_DTB_CFG_CFG_FINISH_INT_EVENT0r                                    = 4140,
-    DTB_DTB_CFG_CFG_FINISH_INT_EVENT1r                                    = 4141,
-    DTB_DTB_CFG_CFG_FINISH_INT_EVENT2r                                    = 4142,
-    DTB_DTB_CFG_CFG_FINISH_INT_EVENT3r                                    = 4143,
-    DTB_DTB_CFG_CFG_FINISH_INT_MAKS0r                                     = 4144,
-    DTB_DTB_CFG_CFG_FINISH_INT_MAKS1r                                     = 4145,
-    DTB_DTB_CFG_CFG_FINISH_INT_MAKS2r                                     = 4146,
-    DTB_DTB_CFG_CFG_FINISH_INT_MAKS3r                                     = 4147,
-    DTB_DTB_CFG_CFG_FINISH_INT_TEST0r                                     = 4148,
-    DTB_DTB_CFG_CFG_FINISH_INT_TEST1r                                     = 4149,
-    DTB_DTB_CFG_CFG_FINISH_INT_TEST2r                                     = 4150,
-    DTB_DTB_CFG_CFG_FINISH_INT_TEST3r                                     = 4151,
-    DTB_DTB_CFG_CFG_DTB_INT_TO_RISCV_SELr                                 = 4152,
-    DTB_DTB_CFG_CFG_DTB_EP_INT_MSIX_ENABLEr                               = 4153,
-    DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_H_0_15r                          = 4154,
-    DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_L_0_15r                          = 4155,
-    DTB_DTB_CFG_CFG_DTB_DEBUG_MODE_ENr                                    = 4156,
-    DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_HIGHr                         = 4157,
-    DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_LOWr                          = 4158,
-    DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_LENr                               = 4159,
-    DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USERr                              = 4160,
-    DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ONLOAD_CNTr                        = 4161,
-    DTB_DTB_CFG_CNT_AXI_RD_TABLE_RESP_ERRr                                = 4162,
-    DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_HIGHr                            = 4163,
-    DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_LOWr                             = 4164,
-    DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_LENr                                  = 4165,
-    DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USERr                                 = 4166,
-    DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ONLOAD_CNTr                           = 4167,
-    DTB_DTB_CFG_CNT_AXI_RD_PD_RESP_ERRr                                   = 4168,
-    DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_HIGHr                          = 4169,
-    DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_LOWr                           = 4170,
-    DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_LENr                                = 4171,
-    DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USERr                               = 4172,
-    DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ONLOAD_CNTr                         = 4173,
-    DTB_DTB_CFG_CNT_AXI_WR_CTRL_RESP_ERRr                                 = 4174,
-    DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_HIGHr                           = 4175,
-    DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_LOWr                            = 4176,
-    DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_LENr                                 = 4177,
-    DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USERr                                = 4178,
-    DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ONLOAD_CNTr                          = 4179,
-    DTB_DTB_CFG_CNT_AXI_WR_DDR_RESP_ERRr                                  = 4180,
-    DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_HIGHr                           = 4181,
-    DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_LOWr                            = 4182,
-    DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_LENr                                 = 4183,
-    DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USERr                                = 4184,
-    DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ONLOAD_CNTr                          = 4185,
-    DTB_DTB_CFG_CNT_AXI_WR_FIN_RESP_ERRr                                  = 4186,
-    DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_HIGHr                              = 4187,
-    DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_LOWr                               = 4188,
-    DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_HIGHr                              = 4189,
-    DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_LOWr                               = 4190,
-    DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_HIGHr                               = 4191,
-    DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_LOWr                                = 4192,
-    DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_HIGHr                              = 4193,
-    DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_LOWr                               = 4194,
-    DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_HIGHr                               = 4195,
-    DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_LOWr                                = 4196,
-    DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_HIGHr                              = 4197,
-    DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_LOWr                               = 4198,
-    DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_HIGHr                              = 4199,
-    DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_LOWr                               = 4200,
-    DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_HIGHr                               = 4201,
-    DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_LOWr                                = 4202,
-    DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_HIGHr                              = 4203,
-    DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_LOWr                               = 4204,
-    DTB_DTB_CFG_INFO_WR_CTRL_STATEr                                       = 4205,
-    DTB_DTB_CFG_INFO_RD_TABLE_STATEr                                      = 4206,
-    DTB_DTB_CFG_INFO_RD_PD_STATEr                                         = 4207,
-    DTB_DTB_CFG_INFO_DUMP_CMD_STATEr                                      = 4208,
-    DTB_DTB_CFG_INFO_WR_DDR_STATEr                                        = 4209,
-    DTB_DTB_CFG_CFG_DTB_DEBUG_INFO_CLRr                                   = 4210,
-    DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_0_15r                                = 4211,
-    DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_COMP_ENr                             = 4212,
-    DTB_DDOS_CFG_DDOS_DUMP_STAT_NUMr                                      = 4213,
-    DTB_DDOS_CFG_DDOS_EVEN_HASH_TABLE_BADDRr                              = 4214,
-    DTB_DDOS_CFG_DDOS_ODD_HASH_TABLE_BADDRr                               = 4215,
-    DTB_DDOS_CFG_DDOS_STAT_INDEX_OFFSETr                                  = 4216,
-    DTB_DDOS_CFG_DDOS_NS_FLAG_CNTr                                        = 4217,
-    DTB_DDOS_CFG_DDOS_EVEN_STAT_TABLE_BADDRr                              = 4218,
-    DTB_DDOS_CFG_DDOS_ODD_STAT_TABLE_BADDRr                               = 4219,
-    DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_Hr                             = 4220,
-    DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_Lr                             = 4221,
-    DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_Hr                              = 4222,
-    DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_Lr                              = 4223,
-    DTB_DDOS_CFG_DDOS_WORK_MODE_ENABLEr                                   = 4224,
-    DTB_DDOS_CFG_DDOS_STAT_TABLE_LENr                                     = 4225,
-    DTB_DDOS_CFG_DDOS_HASH_TABLE_LENr                                     = 4226,
-    DTB_DTB_RAM_TRAF_CTRL_RAM0_0_255r                                     = 4227,
-    DTB_DTB_RAM_TRAF_CTRL_RAM1_0_255r                                     = 4228,
-    DTB_DTB_RAM_TRAF_CTRL_RAM2_0_255r                                     = 4229,
-    DTB_DTB_RAM_TRAF_CTRL_RAM3_0_255r                                     = 4230,
-    DTB_DTB_RAM_TRAF_CTRL_RAM4_0_255r                                     = 4231,
-    DTB_DTB_RAM_TRAF_CTRL_RAM5_0_63r                                      = 4232,
-    DTB_DTB_RAM_DUMP_PD_RAM_0_2047r                                       = 4233,
-    DTB_DTB_RAM_RD_CTRL_RAM_0_4095r                                       = 4234,
-    DTB_DTB_RAM_RD_TABLE_RAM_0_8191r                                      = 4235,
-    DTB_DTB_RAM_DTB_CMD_MAN_RAM_0_16383r                                  = 4236,
-    TRPG_TRPG_RX_PORT_CPU_TRPG_MS_STr                                     = 4237,
-    TRPG_TRPG_RX_PORT_CPU_TRPG_MS_INDr                                    = 4238,
-    TRPG_TRPG_RX_PORT_CPU_TRPG_MS_SLAVE_INDr                              = 4239,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_UP_WATER_LEVELr                          = 4240,
-    TRPG_TRPG_RX_PORT_CPU_TRPGRX_LOW_WATER_LEVELr                         = 4241,
-    TRPG_TRPG_TX_PORT_CPU_TRPG_MS_STr                                     = 4242,
-    TRPG_TRPG_TX_PORT_CPU_TRPG_MS_INDr                                    = 4243,
-    TRPG_TRPG_TX_PORT_CPU_TRPG_MS_SLAVE_INDr                              = 4244,
-    TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_EVENTr                        = 4245,
-    TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_TESTr                         = 4246,
-    TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_ADDRr                         = 4247,
-    TRPG_TRPG_TX_TODTIME_RAM_TRPG_TX_TODTIME_RAMr                         = 4248,
-    TSN_TSN_PORT_CFG_TSN_TEST_REGr                                        = 4249,
-    TSN_TSN_PORT_CFG_TSN_PORT_QBV_ENABLEr                                 = 4250,
-    TSN_TSN_PORT_CFG_TSN_PHY_PORT_SELr                                    = 4251,
-    TSN_TSN_PORT_CFG_TSN_PORT_TIME_SELr                                   = 4252,
-    TSN_TSN_PORT_CFG_TSN_CLK_FREQr                                        = 4253,
-    TSN_TSN_PORT_CFG_TSN_READ_RAM_Nr                                      = 4254,
-    TSN_TSN_PORT_CFG_TSN_EXE_TIMEr                                        = 4255,
-    TSN_TSN_PORT_CFG_TSN_PORT_ITR_SHIFTr                                  = 4256,
-    TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_Hr                                = 4257,
-    TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_Lr                                = 4258,
-    TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_Hr                               = 4259,
-    TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_Lr                               = 4260,
-    TSN_TSN_PORT_CFG_TSN_PORT_GUARD_BAND_TIMEr                            = 4261,
-    TSN_TSN_PORT_CFG_TSN_PORT_DEFAULT_GATE_ENr                            = 4262,
-    TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_GATE_ENr                             = 4263,
-    TSN_TSN_PORT_CFG_TSN_PORT_INIT_FINISHr                                = 4264,
-    TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_ENr                                  = 4265,
-    TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM0r                                   = 4266,
-    TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM1r                                   = 4267,
-    TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE0r                                 = 4268,
-    TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE1r                                 = 4269,
-    AXI_AXI_CONV_CFG_EPID_V_FUNC_NUMr                                     = 4270,
-    AXI_AXI_CONV_INFO_AXIM_RW_HSK_CNTr                                    = 4271,
-    AXI_AXI_CONV_INFO_AXIM_LAST_WR_IDr                                    = 4272,
-    AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_Hr                                = 4273,
-    AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_Lr                                = 4274,
-    AXI_AXI_CONV_CFG_DEBUG_INFO_CLR_ENr                                   = 4275,
-    PTPTM_PTP_TOP_PP1S_INTERRUPTr                                         = 4276,
-    PTPTM_PTP_TOP_PP1S_EXTERNAL_SELECTr                                   = 4277,
-    PTPTM_PTP_TOP_PP1S_OUT_SELECTr                                        = 4278,
-    PTPTM_PTP_TOP_TEST_PP1S_SELECTr                                       = 4279,
-    PTPTM_PTP_TOP_LOCAL_PP1S_ENr                                          = 4280,
-    PTPTM_PTP_TOP_LOCAL_PP1S_ADJUSTr                                      = 4281,
-    PTPTM_PTP_TOP_LOCAL_PP1S_ADJUST_VALUEr                                = 4282,
-    PTPTM_PTP_TOP_PP1S_TO_NP_SELECTr                                      = 4283,
-    PTPTM_PTP_TOP_PD_U1_SELr                                              = 4284,
-    PTPTM_PTP_TOP_PD_U1_PD0_SHIFTr                                        = 4285,
-    PTPTM_PTP_TOP_PD_U1_PD1_SHIFTr                                        = 4286,
-    PTPTM_PTP_TOP_PD_U1_RESULTr                                           = 4287,
-    PTPTM_PTP_TOP_PD_U2_SELr                                              = 4288,
-    PTPTM_PTP_TOP_PD_U2_PD0_SHIFTr                                        = 4289,
-    PTPTM_PTP_TOP_PD_U2_PD1_SHIFTr                                        = 4290,
-    PTPTM_PTP_TOP_PD_U2_RESULTr                                           = 4291,
-    PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY0r                            = 4292,
-    PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY0r                        = 4293,
-    PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY1r                            = 4294,
-    PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY1r                        = 4295,
-    PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY2r                            = 4296,
-    PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY2r                        = 4297,
-    PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY3r                            = 4298,
-    PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY3r                        = 4299,
-    PTPTM_PTP_TOP_TSN_PTP1588_RDMA_NANOSECOND_DELAYr                      = 4300,
-    PTPTM_PTP_TOP_PTP1588_RDMA_FRACNANOSECOND_DELAYr                      = 4301,
-    PTPTM_PTP_TOP_PTP1588_NP_NANOSECOND_DELAYr                            = 4302,
-    PTPTM_PTP_TOP_PTP1588_NP_FRACNANOSECOND_DELAYr                        = 4303,
-    PTPTM_PTP_TOP_TIME_SYNC_PERIODr                                       = 4304,
-    PTPTM_PTPTM_MODULE_IDr                                                = 4305,
-    PTPTM_PTPTM_MODULE_VERSIONr                                           = 4306,
-    PTPTM_PTPTM_MODULE_DATEr                                              = 4307,
-    PTPTM_PTPTM_INTERRUPT_STATUSr                                         = 4308,
-    PTPTM_PTPTM_INTERRUPT_EVENTr                                          = 4309,
-    PTPTM_PTPTM_INTERRUPT_MASKr                                           = 4310,
-    PTPTM_PTPTM_INTERRUPT_TESTr                                           = 4311,
-    PTPTM_PTPTM_HW_CLOCK_CYCLE_INTEGERr                                   = 4312,
-    PTPTM_PTPTM_HW_CLOCK_CYCLE_FRACTIONr                                  = 4313,
-    PTPTM_PTPTM_PTP_CLOCK_CYCLE_INTEGERr                                  = 4314,
-    PTPTM_PTPTM_PTP_CLOCK_CYCLE_FRACTIONr                                 = 4315,
-    PTPTM_PTPTM_PTP_CONFIGURATIONr                                        = 4316,
-    PTPTM_PTPTM_TIMER_CONTROLr                                            = 4317,
-    PTPTM_PTPTM_PPS_INCOME_DELAYr                                         = 4318,
-    PTPTM_PTPTM_CLOCK_CYCLE_UPDATEr                                       = 4319,
-    PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_1r                      = 4320,
-    PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_2r                      = 4321,
-    PTPTM_PTPTM_TIMER_LATCH_ENr                                           = 4322,
-    PTPTM_PTPTM_TIMER_LATCH_SELr                                          = 4323,
-    PTPTM_PTPTM_TRIGGER_IN_TOD_NANOSECONDr                                = 4324,
-    PTPTM_PTPTM_TRIGGER_IN_LOWER_TOD_SECONDr                              = 4325,
-    PTPTM_PTPTM_TRIGGER_IN_HIGH_TOD_SECONDr                               = 4326,
-    PTPTM_PTPTM_TRIGGER_IN_FRACNANOSECONDr                                = 4327,
-    PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_LOWr                             = 4328,
-    PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_HIGHr                            = 4329,
-    PTPTM_PTPTM_TRIGGER_OUT_TOD_NANOSECONDr                               = 4330,
-    PTPTM_PTPTM_TRIGGER_OUT_LOWER_TOD_SECONDr                             = 4331,
-    PTPTM_PTPTM_TRIGGER_OUT_HIGH_TOD_SECONDr                              = 4332,
-    PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_LOWr                            = 4333,
-    PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_HIGHr                           = 4334,
-    PTPTM_PTPTM_ADJUST_TOD_NANOSECONDr                                    = 4335,
-    PTPTM_PTPTM_ADJUST_LOWER_TOD_SECONDr                                  = 4336,
-    PTPTM_PTPTM_ADJUST_HIGH_TOD_SECONDr                                   = 4337,
-    PTPTM_PTPTM_ADJUST_FRACNANOSECONDr                                    = 4338,
-    PTPTM_PTPTM_ADJUST_HARDWARE_TIME_LOWr                                 = 4339,
-    PTPTM_PTPTM_ADJUST_HARDWARE_TIME_HIGHr                                = 4340,
-    PTPTM_PTPTM_LATCH_TOD_NANOSECONDr                                     = 4341,
-    PTPTM_PTPTM_LATCH_LOWER_TOD_SECONDr                                   = 4342,
-    PTPTM_PTPTM_LATCH_HIGH_TOD_SECONDr                                    = 4343,
-    PTPTM_PTPTM_LATCH_FRACNANOSECONDr                                     = 4344,
-    PTPTM_PTPTM_LATCH_HARDWARE_TIME_LOWr                                  = 4345,
-    PTPTM_PTPTM_LATCH_HARDWARE_TIME_HIGHr                                 = 4346,
-    PTPTM_PTPTM_REAL_TOD_NANOSECONDr                                      = 4347,
-    PTPTM_PTPTM_REAL_LOWER_TOD_SECONDr                                    = 4348,
-    PTPTM_PTPTM_REAL_HIGH_TOD_SECONDr                                     = 4349,
-    PTPTM_PTPTM_REAL_HARDWARE_TIME_LOWr                                   = 4350,
-    PTPTM_PTPTM_REAL_HARDWARE_TIME_HIGHr                                  = 4351,
-    PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_PORTr                               = 4352,
-    PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_LOWr                      = 4353,
-    PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_HIGHr                     = 4354,
-    PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_FIFO_STATUSr                        = 4355,
-    PTPTM_PTPTM_PP1S_LATCH_TOD_NANOSECONDr                                = 4356,
-    PTPTM_PTPTM_PP1S_LATCH_LOWER_TOD_SECONDr                              = 4357,
-    PTPTM_PTPTM_PP1S_LATCH_HIGH_TOD_SECONDr                               = 4358,
-    PTPTM_PTPTM_PP1S_LATCH_FRACNANOSECONDr                                = 4359,
-    PTPTM_PTPTM_TSN_TIME_CONFIGURATIONr                                   = 4360,
-    PTPTM_PTPTM_TSN_TIMER_CONTROLr                                        = 4361,
-    PTPTM_PTPTM_TSN0_CLOCK_CYCLE_INTEGERr                                 = 4362,
-    PTPTM_PTPTM_TSN0_CLOCK_CYCLE_FRACTIONr                                = 4363,
-    PTPTM_PTPTM_TSN1_CLOCK_CYCLE_INTEGERr                                 = 4364,
-    PTPTM_PTPTM_TSN1_CLOCK_CYCLE_FRACTIONr                                = 4365,
-    PTPTM_PTPTM_TSN2_CLOCK_CYCLE_INTEGERr                                 = 4366,
-    PTPTM_PTPTM_TSN2_CLOCK_CYCLE_FRACTIONr                                = 4367,
-    PTPTM_PTPTM_TSN3_CLOCK_CYCLE_INTEGERr                                 = 4368,
-    PTPTM_PTPTM_TSN3_CLOCK_CYCLE_FRACTIONr                                = 4369,
-    PTPTM_PTPTM_TSN0_ADJUST_TOD_NANOSECONDr                               = 4370,
-    PTPTM_PTPTM_TSN0_ADJUST_LOWER_TOD_SECONDr                             = 4371,
-    PTPTM_PTPTM_TSN0_ADJUST_HIGH_TOD_SECONDr                              = 4372,
-    PTPTM_PTPTM_TSN0_ADJUST_FRACNANOSECONDr                               = 4373,
-    PTPTM_PTPTM_TSN1_ADJUST_TOD_NANOSECONDr                               = 4374,
-    PTPTM_PTPTM_TSN1_ADJUST_LOWER_TOD_SECONDr                             = 4375,
-    PTPTM_PTPTM_TSN1_ADJUST_HIGH_TOD_SECONDr                              = 4376,
-    PTPTM_PTPTM_TSN1_ADJUST_FRACNANOSECONDr                               = 4377,
-    PTPTM_PTPTM_TSN2_ADJUST_TOD_NANOSECONDr                               = 4378,
-    PTPTM_PTPTM_TSN2_ADJUST_LOWER_TOD_SECONDr                             = 4379,
-    PTPTM_PTPTM_TSN2_ADJUST_HIGH_TOD_SECONDr                              = 4380,
-    PTPTM_PTPTM_TSN2_ADJUST_FRACNANOSECONDr                               = 4381,
-    PTPTM_PTPTM_TSN3_ADJUST_TOD_NANOSECONDr                               = 4382,
-    PTPTM_PTPTM_TSN3_ADJUST_LOWER_TOD_SECONDr                             = 4383,
-    PTPTM_PTPTM_TSN3_ADJUST_HIGH_TOD_SECONDr                              = 4384,
-    PTPTM_PTPTM_TSN3_ADJUST_FRACNANOSECONDr                               = 4385,
-    PTPTM_PTPTM_TSN0_LATCH_TOD_NANOSECONDr                                = 4386,
-    PTPTM_PTPTM_TSN0_LATCH_LOWER_TOD_SECONDr                              = 4387,
-    PTPTM_PTPTM_TSN0_LATCH_HIGH_TOD_SECONDr                               = 4388,
-    PTPTM_PTPTM_TSN0_LATCH_FRACNANOSECONDr                                = 4389,
-    PTPTM_PTPTM_TSN1_LATCH_TOD_NANOSECONDr                                = 4390,
-    PTPTM_PTPTM_TSN1_LATCH_LOWER_TOD_SECONDr                              = 4391,
-    PTPTM_PTPTM_TSN1_LATCH_HIGH_TOD_SECONDr                               = 4392,
-    PTPTM_PTPTM_TSN1_LATCH_FRACNANOSECONDr                                = 4393,
-    PTPTM_PTPTM_TSN2_LATCH_TOD_NANOSECONDr                                = 4394,
-    PTPTM_PTPTM_TSN2_LATCH_LOWER_TOD_SECONDr                              = 4395,
-    PTPTM_PTPTM_TSN2_LATCH_HIGH_TOD_SECONDr                               = 4396,
-    PTPTM_PTPTM_TSN2_LATCH_FRACNANOSECONDr                                = 4397,
-    PTPTM_PTPTM_TSN3_LATCH_TOD_NANOSECONDr                                = 4398,
-    PTPTM_PTPTM_TSN3_LATCH_LOWER_TOD_SECONDr                              = 4399,
-    PTPTM_PTPTM_TSN3_LATCH_HIGH_TOD_SECONDr                               = 4400,
-    PTPTM_PTPTM_TSN3_LATCH_FRACNANOSECONDr                                = 4401,
-    PTPTM_PTPTM_PP1S_LATCH_TSN0_TOD_NANOSECONDr                           = 4402,
-    PTPTM_PTPTM_PP1S_LATCH_TSN0_LOWER_TOD_SECONDr                         = 4403,
-    PTPTM_PTPTM_PP1S_LATCH_TSN0_HIGH_TOD_SECONDr                          = 4404,
-    PTPTM_PTPTM_PP1S_LATCH_TSN0_FRACNANOSECONDr                           = 4405,
-    PTPTM_PTPTM_PP1S_LATCH_TSN1_TOD_NANOSECONDr                           = 4406,
-    PTPTM_PTPTM_PP1S_LATCH_TSN1_LOWER_TOD_SECONDr                         = 4407,
-    PTPTM_PTPTM_PP1S_LATCH_TSN1_HIGH_TOD_SECONDr                          = 4408,
-    PTPTM_PTPTM_PP1S_LATCH_TSN1_FRACNANOSECONDr                           = 4409,
-    PTPTM_PTPTM_PP1S_LATCH_TSN2_TOD_NANOSECONDr                           = 4410,
-    PTPTM_PTPTM_PP1S_LATCH_TSN2_LOWER_TOD_SECONDr                         = 4411,
-    PTPTM_PTPTM_PP1S_LATCH_TSN2_HIGH_TOD_SECONDr                          = 4412,
-    PTPTM_PTPTM_PP1S_LATCH_TSN2_FRACNANOSECONDr                           = 4413,
-    PTPTM_PTPTM_PP1S_LATCH_TSN3_TOD_NANOSECONDr                           = 4414,
-    PTPTM_PTPTM_PP1S_LATCH_TSN3_LOWER_TOD_SECONDr                         = 4415,
-    PTPTM_PTPTM_PP1S_LATCH_TSN3_HIGH_TOD_SECONDr                          = 4416,
-    PTPTM_PTPTM_PP1S_LATCH_TSN3_FRACNANOSECONDr                           = 4417,
-    PTPTM_PTPTM_TSN0_REAL_TOD_NANOSECONDr                                 = 4418,
-    PTPTM_PTPTM_TSN0_REAL_LOWER_TOD_SECONDr                               = 4419,
-    PTPTM_PTPTM_TSN0_REAL_HIGH_TOD_SECONDr                                = 4420,
-    PTPTM_PTPTM_TSN1_REAL_TOD_NANOSECONDr                                 = 4421,
-    PTPTM_PTPTM_TSN1_REAL_LOWER_TOD_SECONDr                               = 4422,
-    PTPTM_PTPTM_TSN1_REAL_HIGH_TOD_SECONDr                                = 4423,
-    PTPTM_PTPTM_TSN2_REAL_TOD_NANOSECONDr                                 = 4424,
-    PTPTM_PTPTM_TSN2_REAL_LOWER_TOD_SECONDr                               = 4425,
-    PTPTM_PTPTM_TSN2_REAL_HIGH_TOD_SECONDr                                = 4426,
-    PTPTM_PTPTM_TSN3_REAL_TOD_NANOSECONDr                                 = 4427,
-    PTPTM_PTPTM_TSN3_REAL_LOWER_TOD_SECONDr                               = 4428,
-    PTPTM_PTPTM_TSN3_REAL_HIGH_TOD_SECONDr                                = 4429,
-    PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_INTEGERr                             = 4430,
-    PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_FRACTIONr                            = 4431,
-    PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_INTEGERr                            = 4432,
-    PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_FRACTIONr                           = 4433,
-    PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_INTEGERr                            = 4434,
-    PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_FRACTIONr                           = 4435,
-    PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_INTEGERr                            = 4436,
-    PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_FRACTIONr                           = 4437,
-    PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_INTEGERr                            = 4438,
-    PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_FRACTIONr                           = 4439,
-    REG_ENUM_MAX_VALUE
-}DPP_REG_INFO_E;
+typedef enum dpp_reg_info_e {
+	ETM_CFGMT_CPU_CHECK_REGr = 0,
+	ETM_CFGMT_CFGMT_BLKSIZEr = 1,
+	ETM_CFGMT_REG_INT_STATE_REGr = 2,
+	ETM_CFGMT_REG_INT_MASK_REGr = 3,
+	ETM_CFGMT_TIMEOUT_LIMITr = 4,
+	ETM_CFGMT_SUBSYSTEM_RDY_REGr = 5,
+	ETM_CFGMT_SUBSYSTEM_EN_REGr = 6,
+	ETM_CFGMT_CFGMT_INT_REGr = 7,
+	ETM_CFGMT_QMU_WORK_MODEr = 8,
+	ETM_CFGMT_CFGMT_DDR_ATTACHr = 9,
+	ETM_CFGMT_CNT_MODE_REGr = 10,
+	ETM_CFGMT_CLKGATE_ENr = 11,
+	ETM_CFGMT_SOFTRST_ENr = 12,
+	ETM_OLIF_IMEM_PROG_FULLr = 13,
+	ETM_OLIF_QMU_PARA_PROG_FULLr = 14,
+	ETM_OLIF_OLIF_INT_MASKr = 15,
+	ETM_OLIF_ITMHRAM_PARITY_ERR_2_INTr = 16,
+	ETM_OLIF_LIF0_PORT_RDY_MASK_Hr = 17,
+	ETM_OLIF_LIF0_PORT_RDY_MASK_Lr = 18,
+	ETM_OLIF_LIF0_PORT_RDY_CFG_Hr = 19,
+	ETM_OLIF_LIF0_PORT_RDY_CFG_Lr = 20,
+	ETM_OLIF_LIF0_LINK_RDY_MASK_CFGr = 21,
+	ETM_OLIF_TM_LIF_STAT_CFGr = 22,
+	ETM_OLIF_TM_LIF_SOP_STATr = 23,
+	ETM_OLIF_TM_LIF_EOP_STATr = 24,
+	ETM_OLIF_TM_LIF_VLD_STATr = 25,
+	ETM_CGAVD_PROG_FULL_ASSERT_CFGr = 26,
+	ETM_CGAVD_CGAVD_INTr = 27,
+	ETM_CGAVD_CGAVD_RAM_ERRr = 28,
+	ETM_CGAVD_CGAVD_INT_MASKr = 29,
+	ETM_CGAVD_CGAVD_RAM_ERR_INT_MASKr = 30,
+	ETM_CGAVD_CFGMT_BYTE_MODEr = 31,
+	ETM_CGAVD_AVG_QLEN_RETURN_ZERO_ENr = 32,
+	ETM_CGAVD_FLOW_WRED_Q_LEN_THr = 33,
+	ETM_CGAVD_FLOW_WQr = 34,
+	ETM_CGAVD_FLOW_WRED_MAX_THr = 35,
+	ETM_CGAVD_FLOW_WRED_MIN_THr = 36,
+	ETM_CGAVD_FLOW_WRED_CFG_PARAr = 37,
+	ETM_CGAVD_PP_AVG_Q_LENr = 38,
+	ETM_CGAVD_PP_TD_THr = 39,
+	ETM_CGAVD_PP_CA_MTDr = 40,
+	ETM_CGAVD_PP_WRED_GRP_TH_ENr = 41,
+	ETM_CGAVD_PP_WRED_Q_LEN_THr = 42,
+	ETM_CGAVD_PP_WQr = 43,
+	ETM_CGAVD_PP_WRED_MAX_THr = 44,
+	ETM_CGAVD_PP_WRED_MIN_THr = 45,
+	ETM_CGAVD_PP_CFG_PARAr = 46,
+	ETM_CGAVD_SYS_AVG_Q_LENr = 47,
+	ETM_CGAVD_SYS_TD_THr = 48,
+	ETM_CGAVD_SYS_CGAVD_METDr = 49,
+	ETM_CGAVD_SYS_CFG_Q_GRP_PARAr = 50,
+	ETM_CGAVD_SYS_WQr = 51,
+	ETM_CGAVD_GRED_MAX_THr = 52,
+	ETM_CGAVD_GRED_MID_THr = 53,
+	ETM_CGAVD_GRED_MIN_THr = 54,
+	ETM_CGAVD_GRED_CFG_PARA0r = 55,
+	ETM_CGAVD_GRED_CFG_PARA1r = 56,
+	ETM_CGAVD_GRED_CFG_PARA2r = 57,
+	ETM_CGAVD_SYS_WINDOW_TH_Hr = 58,
+	ETM_CGAVD_SYS_WINDOW_TH_Lr = 59,
+	ETM_CGAVD_AMPLIFY_GENE0r = 60,
+	ETM_CGAVD_AMPLIFY_GENE1r = 61,
+	ETM_CGAVD_AMPLIFY_GENE2r = 62,
+	ETM_CGAVD_AMPLIFY_GENE3r = 63,
+	ETM_CGAVD_AMPLIFY_GENE4r = 64,
+	ETM_CGAVD_AMPLIFY_GENE5r = 65,
+	ETM_CGAVD_AMPLIFY_GENE6r = 66,
+	ETM_CGAVD_AMPLIFY_GENE7r = 67,
+	ETM_CGAVD_AMPLIFY_GENE8r = 68,
+	ETM_CGAVD_AMPLIFY_GENE9r = 69,
+	ETM_CGAVD_AMPLIFY_GENE10r = 70,
+	ETM_CGAVD_AMPLIFY_GENE11r = 71,
+	ETM_CGAVD_AMPLIFY_GENE12r = 72,
+	ETM_CGAVD_AMPLIFY_GENE13r = 73,
+	ETM_CGAVD_AMPLIFY_GENE14r = 74,
+	ETM_CGAVD_AMPLIFY_GENE15r = 75,
+	ETM_CGAVD_EQUAL_PKT_LEN_ENr = 76,
+	ETM_CGAVD_EQUAL_PKT_LEN_TH0r = 77,
+	ETM_CGAVD_EQUAL_PKT_LEN_TH1r = 78,
+	ETM_CGAVD_EQUAL_PKT_LEN_TH2r = 79,
+	ETM_CGAVD_EQUAL_PKT_LEN_TH3r = 80,
+	ETM_CGAVD_EQUAL_PKT_LEN_TH4r = 81,
+	ETM_CGAVD_EQUAL_PKT_LEN_TH5r = 82,
+	ETM_CGAVD_EQUAL_PKT_LEN_TH6r = 83,
+	ETM_CGAVD_EQUAL_PKT_LEN0r = 84,
+	ETM_CGAVD_EQUAL_PKT_LEN1r = 85,
+	ETM_CGAVD_EQUAL_PKT_LEN2r = 86,
+	ETM_CGAVD_EQUAL_PKT_LEN3r = 87,
+	ETM_CGAVD_EQUAL_PKT_LEN4r = 88,
+	ETM_CGAVD_EQUAL_PKT_LEN5r = 89,
+	ETM_CGAVD_EQUAL_PKT_LEN6r = 90,
+	ETM_CGAVD_EQUAL_PKT_LEN7r = 91,
+	ETM_CGAVD_FLOW_CPU_SET_AVG_LENr = 92,
+	ETM_CGAVD_FLOW_CPU_SET_Q_LENr = 93,
+	ETM_CGAVD_PP_CPU_SET_AVG_Q_LENr = 94,
+	ETM_CGAVD_PP_CPU_SET_Q_LENr = 95,
+	ETM_CGAVD_SYS_CPU_SET_AVG_LENr = 96,
+	ETM_CGAVD_SYS_CPU_SET_Q_LENr = 97,
+	ETM_CGAVD_PKE_LEN_CALC_SIGNr = 98,
+	ETM_CGAVD_RD_CPU_OR_RAMr = 99,
+	ETM_CGAVD_Q_LEN_UPDATE_DISABLEr = 100,
+	ETM_CGAVD_CGAVD_DP_SELr = 101,
+	ETM_CGAVD_CGAVD_SUB_ENr = 102,
+	ETM_CGAVD_DEFAULT_START_QUEUEr = 103,
+	ETM_CGAVD_DEFAULT_FINISH_QUEUEr = 104,
+	ETM_CGAVD_PROTOCOL_START_QUEUEr = 105,
+	ETM_CGAVD_PROTOCOL_FINISH_QUEUEr = 106,
+	ETM_CGAVD_UNIFORM_TD_THr = 107,
+	ETM_CGAVD_UNIFORM_TD_TH_ENr = 108,
+	ETM_CGAVD_CGAVD_CFG_FCr = 109,
+	ETM_CGAVD_CGAVD_CFG_NO_FCr = 110,
+	ETM_CGAVD_CGAVD_FORCE_IMEM_OMEMr = 111,
+	ETM_CGAVD_CGAVD_SYS_Q_LEN_Lr = 112,
+	ETM_CGAVD_DEFAULT_QUEUE_ENr = 113,
+	ETM_CGAVD_PROTOCOL_QUEUE_ENr = 114,
+	ETM_CGAVD_CFG_TC_FLOWID_DATr = 115,
+	ETM_CGAVD_FLOW_TD_THr = 116,
+	ETM_CGAVD_FLOW_CA_MTDr = 117,
+	ETM_CGAVD_FLOW_DYNAMIC_TH_ENr = 118,
+	ETM_CGAVD_PP_NUMr = 119,
+	ETM_CGAVD_FLOW_Q_LENr = 120,
+	ETM_CGAVD_FLOW_WRED_GRPr = 121,
+	ETM_CGAVD_FLOW_AVG_Q_LENr = 122,
+	ETM_CGAVD_QOS_SIGNr = 123,
+	ETM_CGAVD_Q_PRIr = 124,
+	ETM_CGAVD_ODMA_TM_ITMD_RD_LOWr = 125,
+	ETM_CGAVD_ODMA_TM_ITMD_RD_MIDr = 126,
+	ETM_CGAVD_ODMA_TM_ITMD_RD_HIGHr = 127,
+	ETM_CGAVD_CGAVD_STAT_PKT_LENr = 128,
+	ETM_CGAVD_CGAVD_STAT_QNUMr = 129,
+	ETM_CGAVD_CGAVD_STAT_DPr = 130,
+	ETM_CGAVD_FLOW_NUM0r = 131,
+	ETM_CGAVD_FLOW_NUM1r = 132,
+	ETM_CGAVD_FLOW_NUM2r = 133,
+	ETM_CGAVD_FLOW_NUM3r = 134,
+	ETM_CGAVD_FLOW_NUM4r = 135,
+	ETM_CGAVD_FLOW0_IMEM_CNTr = 136,
+	ETM_CGAVD_FLOW1_IMEM_CNTr = 137,
+	ETM_CGAVD_FLOW2_IMEM_CNTr = 138,
+	ETM_CGAVD_FLOW3_IMEM_CNTr = 139,
+	ETM_CGAVD_FLOW4_IMEM_CNTr = 140,
+	ETM_CGAVD_FLOW0_DROP_CNTr = 141,
+	ETM_CGAVD_FLOW1_DROP_CNTr = 142,
+	ETM_CGAVD_FLOW2_DROP_CNTr = 143,
+	ETM_CGAVD_FLOW3_DROP_CNTr = 144,
+	ETM_CGAVD_FLOW4_DROP_CNTr = 145,
+	ETM_CGAVD_FC_COUNT_MODEr = 146,
+	ETM_CGAVD_QMU_CGAVD_FC_NUMr = 147,
+	ETM_CGAVD_CGAVD_ODMA_FC_NUMr = 148,
+	ETM_CGAVD_CFG_OFFSETr = 149,
+	ETM_TMMU_TMMU_INIT_DONEr = 150,
+	ETM_TMMU_TMMU_INT_MASK_1r = 151,
+	ETM_TMMU_TMMU_INT_MASK_2r = 152,
+	ETM_TMMU_CFGMT_TM_PURE_IMEM_ENr = 153,
+	ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFGr = 154,
+	ETM_TMMU_PD_ORDER_FIFO_AFUL_THr = 155,
+	ETM_TMMU_CACHED_PD_FIFO_AFUL_THr = 156,
+	ETM_TMMU_WR_CMD_FIFO_AFUL_THr = 157,
+	ETM_TMMU_IMEM_ENQ_RD_FIFO_AFUL_THr = 158,
+	ETM_TMMU_IMEM_ENQ_DROP_FIFO_AFUL_THr = 159,
+	ETM_TMMU_IMEM_DEQ_DROP_FIFO_AFUL_THr = 160,
+	ETM_TMMU_IMEM_DEQ_RD_FIFO_AFUL_THr = 161,
+	ETM_TMMU_TMMU_STATES_1r = 162,
+	ETM_TMMU_TMMU_STATES_2r = 163,
+	ETM_SHAP_SHAP_IND_CMDr = 164,
+	ETM_SHAP_SHAP_IND_STAr = 165,
+	ETM_SHAP_SHAP_IND_DATA0r = 166,
+	ETM_SHAP_SHAP_IND_DATA1r = 167,
+	ETM_SHAP_FULL_THRESHOLDr = 168,
+	ETM_SHAP_EMPTY_THRESHOLDr = 169,
+	ETM_SHAP_SHAP_STA_INIT_CFGr = 170,
+	ETM_SHAP_SHAP_CFG_INIT_CFGr = 171,
+	ETM_SHAP_TOKEN_MODE_SWITCHr = 172,
+	ETM_SHAP_TOKEN_GRAINr = 173,
+	ETM_SHAP_CRD_GRAINr = 174,
+	ETM_SHAP_SHAP_STAT_CTRLr = 175,
+	ETM_SHAP_TOKEN_STAT_IDr = 176,
+	ETM_SHAP_TOKEN_STATr = 177,
+	ETM_SHAP_SHAP_STAT_CLK_CNTr = 178,
+	ETM_SHAP_SHAP_BUCKET_MAP_TBLr = 179,
+	ETM_SHAP_BKT_PARA_TBLr = 180,
+	ETM_CRDT_CREDIT_ENr = 181,
+	ETM_CRDT_CRT_INTER1r = 182,
+	ETM_CRDT_DB_TOKENr = 183,
+	ETM_CRDT_CRS_FLT_CFGr = 184,
+	ETM_CRDT_TH_SPr = 185,
+	ETM_CRDT_TH_WFQ_FQr = 186,
+	ETM_CRDT_TH_WFQ2_FQ2r = 187,
+	ETM_CRDT_TH_WFQ4_FQ4r = 188,
+	ETM_CRDT_CFG_STATEr = 189,
+	ETM_CRDT_CRDT_IND_CMDr = 190,
+	ETM_CRDT_CRDT_IND_STAr = 191,
+	ETM_CRDT_CRDT_IND_DATA0r = 192,
+	ETM_CRDT_CRDT_IND_DATA1r = 193,
+	ETM_CRDT_CRDT_STATEr = 194,
+	ETM_CRDT_STAT_QUE_ID_0r = 195,
+	ETM_CRDT_STAT_QUE_ID_1r = 196,
+	ETM_CRDT_STAT_QUE_ID_2r = 197,
+	ETM_CRDT_STAT_QUE_ID_3r = 198,
+	ETM_CRDT_STAT_QUE_ID_4r = 199,
+	ETM_CRDT_STAT_QUE_ID_5r = 200,
+	ETM_CRDT_STAT_QUE_ID_6r = 201,
+	ETM_CRDT_STAT_QUE_ID_7r = 202,
+	ETM_CRDT_STAT_QUE_ID_8r = 203,
+	ETM_CRDT_STAT_QUE_ID_9r = 204,
+	ETM_CRDT_STAT_QUE_ID_10r = 205,
+	ETM_CRDT_STAT_QUE_ID_11r = 206,
+	ETM_CRDT_STAT_QUE_ID_12r = 207,
+	ETM_CRDT_STAT_QUE_ID_13r = 208,
+	ETM_CRDT_STAT_QUE_ID_14r = 209,
+	ETM_CRDT_STAT_QUE_ID_15r = 210,
+	ETM_CRDT_STAT_QUE_CREDITr = 211,
+	ETM_CRDT_CRDT_CFG_RAM_INITr = 212,
+	ETM_CRDT_CRDT_STA_RAM_INITr = 213,
+	ETM_CRDT_CRS_QUE_IDr = 214,
+	ETM_CRDT_QMU_CRS_END_STATEr = 215,
+	ETM_CRDT_SHAP_RDYr = 216,
+	ETM_CRDT_SHAP_INT_REGr = 217,
+	ETM_CRDT_SHAP_INT_MASK_REGr = 218,
+	ETM_CRDT_TOKEN_STATE_ALMOST_EMPTY_THr = 219,
+	ETM_CRDT_TOKEN_STATE_EMPTY_THr = 220,
+	ETM_CRDT_FULL_THr = 221,
+	ETM_CRDT_PP_C_LEVEL_SHAP_ENr = 222,
+	ETM_CRDT_ENQ_TOKEN_THr = 223,
+	ETM_CRDT_PP_TOKENQ_LEVEL1_QSTATE_WEIGHT_CIRr = 224,
+	ETM_CRDT_PP_IDLE_WEIGHT_LEVEL1_CIRr = 225,
+	ETM_CRDT_RCI_GRADE_TH_0_CFGr = 226,
+	ETM_CRDT_RCI_GRADE_TH_1_CFGr = 227,
+	ETM_CRDT_RCI_GRADE_TH_2_CFGr = 228,
+	ETM_CRDT_RCI_GRADE_TH_3_CFGr = 229,
+	ETM_CRDT_RCI_GRADE_TH_4_CFGr = 230,
+	ETM_CRDT_RCI_GRADE_TH_5_CFGr = 231,
+	ETM_CRDT_RCI_GRADE_TH_6_CFGr = 232,
+	ETM_CRDT_FLOW_DEL_CMDr = 233,
+	ETM_CRDT_CNT_CLRr = 234,
+	ETM_CRDT_CRDT_INT_BUSr = 235,
+	ETM_CRDT_CRDT_INT_MASKr = 236,
+	ETM_CRDT_CFG_WEIGHT_TOGETHERr = 237,
+	ETM_CRDT_WEIGHTr = 238,
+	ETM_CRDT_DEV_SP_STATEr = 239,
+	ETM_CRDT_DEV_CRSr = 240,
+	ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0r = 241,
+	ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32r = 242,
+	ETM_CRDT_CRDT_INTERVAL_EN_CFGr = 243,
+	ETM_CRDT_Q_TOKEN_STAUE_CFGr = 244,
+	ETM_CRDT_Q_TOKEN_DIST_CNTr = 245,
+	ETM_CRDT_Q_TOKEN_DEC_CNTr = 246,
+	ETM_CRDT_PP_WEIGHT_RAMr = 247,
+	ETM_CRDT_PP_CBS_SHAPE_EN_RAMr = 248,
+	ETM_CRDT_PP_NEXT_PC_Q_STATE_RAMr = 249,
+	ETM_CRDT_DEV_INTERVALr = 250,
+	ETM_CRDT_DEV_WFQ_CNTr = 251,
+	ETM_CRDT_DEV_WFQ_STATEr = 252,
+	ETM_CRDT_DEV_ACTIVE_HEAD_PTRr = 253,
+	ETM_CRDT_DEV_ACTIVE_TAIL_PTRr = 254,
+	ETM_CRDT_DEV_UNACTIVE_HEAD_PTRr = 255,
+	ETM_CRDT_DEV_UNACTIVE_TAIL_PTRr = 256,
+	ETM_CRDT_PP_WEIGHTr = 257,
+	ETM_CRDT_PP_QUE_STATEr = 258,
+	ETM_CRDT_PP_NEXT_PTRr = 259,
+	ETM_CRDT_PP_CFGr = 260,
+	ETM_CRDT_PP_UP_PTRr = 261,
+	ETM_CRDT_CREDIT_DROP_NUMr = 262,
+	ETM_CRDT_SE_ID_LV0r = 263,
+	ETM_CRDT_SE_ID_LV1r = 264,
+	ETM_CRDT_SE_ID_LV2r = 265,
+	ETM_CRDT_SE_ID_LV3r = 266,
+	ETM_CRDT_SE_ID_LV4r = 267,
+	ETM_CRDT_QUE_IDr = 268,
+	ETM_CRDT_SE_INFO_LV0r = 269,
+	ETM_CRDT_SE_INFO_LV1r = 270,
+	ETM_CRDT_SE_INFO_LV2r = 271,
+	ETM_CRDT_SE_INFO_LV3r = 272,
+	ETM_CRDT_SE_INFO_LV4r = 273,
+	ETM_CRDT_QUE_STATEr = 274,
+	ETM_CRDT_EIR_OFF_IN_ADVANCEr = 275,
+	ETM_CRDT_DOUBLE_LEVEL_SHAP_PREVENTr = 276,
+	ETM_CRDT_ADD_STORE_CYCLEr = 277,
+	ETM_CRDT_TFLAG2_WR_FLAG_SUMr = 278,
+	ETM_CRDT_FLOWQUE_PARA_TBLr = 279,
+	ETM_CRDT_SE_PARA_TBLr = 280,
+	ETM_CRDT_FLOWQUE_INS_TBLr = 281,
+	ETM_CRDT_SE_INS_TBLr = 282,
+	ETM_CRDT_EIR_CRS_FILTER_TBLr = 283,
+	ETM_QMU_QCFG_QLIST_CFG_DONEr = 284,
+	ETM_QMU_QCFG_QSCH_CREDIT_VALUEr = 285,
+	ETM_QMU_QCFG_QSCH_CRBAL_INIT_VALUEr = 286,
+	ETM_QMU_QCFG_QSCH_CRBAL_INIT_MASKr = 287,
+	ETM_QMU_CMDSCH_RD_CMD_AFUL_THr = 288,
+	ETM_QMU_CFG_PORT_FC_INTERVALr = 289,
+	ETM_QMU_QCFG_CSCH_AGED_CFGr = 290,
+	ETM_QMU_QCFG_CSCH_AGED_SCAN_TIMEr = 291,
+	ETM_QMU_QCFG_QMU_QLIST_STATE_QUERYr = 292,
+	ETM_QMU_CFGMT_QSCH_CRBAL_DROP_ENr = 293,
+	ETM_QMU_CFGMT_WLIST_QNUM_FIFO_AFUL_THr = 294,
+	ETM_QMU_QCFG_CSW_PKT_BLK_MODEr = 295,
+	ETM_QMU_QCFG_QLIST_RAM_INIT_CANCELr = 296,
+	ETM_QMU_QCFG_QSCH_CRBAL_TRANSFER_MODEr = 297,
+	ETM_QMU_QCFG_QLIST_QCLR_INTERVALr = 298,
+	ETM_QMU_QCFG_QSCH_QCLR_RATEr = 299,
+	ETM_QMU_QCFG_QLIST_DDR_RANDOMr = 300,
+	ETM_QMU_CFGMT_QLIST_PDS_FIFO_AFULL_THr = 301,
+	ETM_QMU_CFGMT_SOP_CMD_FIFO_AFULL_THr = 302,
+	ETM_QMU_CFGMT_NON_SOP_CMD_FIFO_AFULL_THr = 303,
+	ETM_QMU_CFGMT_MMU_DATA_FIFO_AFULL_THr = 304,
+	ETM_QMU_QCFG_QLIST_BANK_EPT_THr = 305,
+	ETM_QMU_RANDOM_BYPASS_ENr = 306,
+	ETM_QMU_CFGMT_CRS_SPD_BYPASSr = 307,
+	ETM_QMU_CFGMT_CRS_INTERVALr = 308,
+	ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_ENr = 309,
+	ETM_QMU_CFG_QSCH_AUTOCRFRSTQUEr = 310,
+	ETM_QMU_CFG_QSCH_AUTOCRLASTQUEr = 311,
+	ETM_QMU_CFG_QSCH_AUTOCREDITRATEr = 312,
+	ETM_QMU_CFG_QSCH_SCANFRSTQUEr = 313,
+	ETM_QMU_CFG_QSCH_SCANLASTQUEr = 314,
+	ETM_QMU_CFG_QSCH_SCANRATEr = 315,
+	ETM_QMU_CFG_QSCH_SCAN_ENr = 316,
+	ETM_QMU_CFGMT_QSCH_RD_CREDIT_FIFO_RATEr = 317,
+	ETM_QMU_QCFG_QLIST_BDEPr = 318,
+	ETM_QMU_QCFG_QLIST_BHEADr = 319,
+	ETM_QMU_QCFG_QLIST_BTAILr = 320,
+	ETM_QMU_QCFG_QSCH_SHAP_PARAMr = 321,
+	ETM_QMU_QCFG_QSCH_SHAP_TOKENr = 322,
+	ETM_QMU_QCFG_QSCH_SHAP_OFFSETr = 323,
+	ETM_QMU_QCFG_QSCH_CRS_EIR_THr = 324,
+	ETM_QMU_QCFG_QSCH_CRS_TH1r = 325,
+	ETM_QMU_QCFG_QSCH_CRS_TH2r = 326,
+	ETM_QMU_QCFG_CSCH_CONGEST_THr = 327,
+	ETM_QMU_QCFG_CSCH_SP_FC_THr = 328,
+	ETM_QMU_QCFG_CSW_SHAP_PARAMETERr = 329,
+	ETM_QMU_CFGMT_RD_RELEASE_AFUL_THr = 330,
+	ETM_QMU_CFGMT_DROP_IMEM_RELEASE_FIFO_AFUL_THr = 331,
+	ETM_QMU_CFGMT_NNH_RD_BUF_AFUL_THr = 332,
+	ETM_QMU_CFG_PID_USE_INALLr = 333,
+	ETM_QMU_CFG_PID_ROUND_THr = 334,
+	ETM_QMU_CFGMT_CREDIT_FIFO_AFULL_THr = 335,
+	ETM_QMU_CFGMT_SCAN_FIFO_AFULL_THr = 336,
+	ETM_QMU_CFGMT_SMALL_FIFO_AFUL_THr = 337,
+	ETM_QMU_CFGMT_FREE_ADDR_FIFO_AFUL_THr = 338,
+	ETM_QMU_CFGMT_ENQ_RPT_FIFO_AFUL_THr = 339,
+	ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTHr = 340,
+	ETM_QMU_QCFG_CSW_SHAP_OFFSET_VALUEr = 341,
+	ETM_QMU_QCFG_CSW_FC_OFFSET_VALUEr = 342,
+	ETM_QMU_QMU_INIT_DONE_STATEr = 343,
+	ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_0r = 344,
+	ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_1r = 345,
+	ETM_QMU_QLIST_CFGMT_RAM_INIT_DONEr = 346,
+	ETM_QMU_QLIST_CFGMT_RAM_ECC_ERRr = 347,
+	ETM_QMU_QLIST_CFGMT_RAM_SLOT_ERRr = 348,
+	ETM_QMU_QSCH_CFGMT_RAM_ECCr = 349,
+	ETM_QMU_QLIST_CFGMT_FIFO_STATEr = 350,
+	ETM_QMU_QLIST_QCFG_CLR_DONEr = 351,
+	ETM_QMU_QMU_INT_MASK1r = 352,
+	ETM_QMU_QMU_INT_MASK2r = 353,
+	ETM_QMU_QMU_INT_MASK3r = 354,
+	ETM_QMU_QMU_INT_MASK4r = 355,
+	ETM_QMU_QMU_INT_MASK5r = 356,
+	ETM_QMU_QMU_INT_MASK6r = 357,
+	ETM_QMU_CMD_SCH_CFGMT_FIFO_STATEr = 358,
+	ETM_QMU_QLIST_R_BCNTr = 359,
+	ETM_QMU_QSCH_RW_CRBALr = 360,
+	ETM_QMU_QSCH_RW_CRSr = 361,
+	ETM_QMU_QSCH_R_WLIST_EMPTYr = 362,
+	ETM_QMU_QCFG_QLIST_BARAM_RDr = 363,
+	ETM_QMU_QCFG_QSCH_CRBAL_FB_RWr = 364,
+	ETM_QMU_QCFG_QLIST_GRP0_BANKr = 365,
+	ETM_QMU_QCFG_QLIST_GRP1_BANKr = 366,
+	ETM_QMU_QCFG_QLIST_GRP2_BANKr = 367,
+	ETM_QMU_QCFG_QLIST_GRP3_BANKr = 368,
+	ETM_QMU_QCFG_QLIST_GRP4_BANKr = 369,
+	ETM_QMU_QCFG_QLIST_GRP5_BANKr = 370,
+	ETM_QMU_QCFG_QLIST_GRP6_BANKr = 371,
+	ETM_QMU_QCFG_QLIST_GRP7_BANKr = 372,
+	ETM_QMU_QCFG_QLIST_GRPr = 373,
+	ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr = 374,
+	ETM_QMU_CFGMT_DDR_IN_MMU_CFGr = 375,
+	ETM_QMU_CFGMT_DDR_IN_QMU_CFGr = 376,
+	ETM_QMU_CFGMT_BANK_TO_MMU_CFGr = 377,
+	ETM_QMU_CFGMT_BANK_TO_QMU_CFGr = 378,
+	ETM_QMU_CFGMT_GRP_RAM_N_CLR_THDr = 379,
+	ETM_QMU_CFGMT_AGE_PKT_NUMr = 380,
+	ETM_QMU_CFGMT_AGE_MULTI_INTERVALr = 381,
+	ETM_QMU_CFGMT_QMU_PKT_AGE_ENr = 382,
+	ETM_QMU_CFGMT_QMU_PKT_AGE_INTERVALr = 383,
+	ETM_QMU_CFGMT_QMU_PKT_AGE_START_ENDr = 384,
+	ETM_QMU_CFGMT_PKT_AGE_REQ_AFUL_THr = 385,
+	ETM_QMU_CFGMT_PKT_AGE_STEP_INTERVALr = 386,
+	ETM_QMU_CFGMT_QMU_IMEM_AGE_MODEr = 387,
+	ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_INTERVALr = 388,
+	ETM_QMU_CFGMT_QMU_IMEM_TIME_AGE_INTERVALr = 389,
+	ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_THDr = 390,
+	ETM_QMU_CFGMT_IMEM_AGE_STEP_INTERVALr = 391,
+	ETM_QMU_CFGMT_QMU_ECC_BYPASS_READr = 392,
+	ETM_QMU_CFGMT_QMU_RESP_STAT_FC_ENr = 393,
+	ETM_QMU_CFGMT_QMU_BANK_XOFF_PDS_MODEr = 394,
+	ETM_QMU_CFGMT_QMU_STAT_OFFSETr = 395,
+	ETM_QMU_FC_CNT_MODEr = 396,
+	ETM_QMU_MMU_QMU_WR_FC_CNTr = 397,
+	ETM_QMU_MMU_QMU_RD_FC_CNTr = 398,
+	ETM_QMU_QMU_CGAVD_FC_CNTr = 399,
+	ETM_QMU_CGAVD_QMU_PKT_CNTr = 400,
+	ETM_QMU_CGAVD_QMU_PKTLEN_ALLr = 401,
+	ETM_QMU_OBSERVE_PORTFC_SPECr = 402,
+	ETM_QMU_SPEC_LIF_PORTFC_COUNTr = 403,
+	ETM_QMU_CFGMT_QMU_PFC_ENr = 404,
+	ETM_QMU_CFGMT_QMU_PFC_MASK_1r = 405,
+	ETM_QMU_CFGMT_QMU_PFC_MASK_2r = 406,
+	CFG_PCIE_INT_REPEATr = 407,
+	CFG_DMA_DMA_UP_SIZEr = 408,
+	CFG_CSR_SOC_WR_TIME_OUT_THRESHr = 409,
+	NPPU_MR_CFG_CFG_SHAP_PARAMr = 410,
+	NPPU_MR_CFG_CFG_SHAP_TOKENr = 411,
+	NPPU_MR_CFG_IDLE_PTR_FIFO_AFUL_THr = 412,
+	NPPU_MR_CFG_MR_COS_PORT_CFGr = 413,
+	NPPU_PKTRX_CFG_IND_STATUSr = 414,
+	NPPU_PKTRX_CFG_IND_CMDr = 415,
+	NPPU_PKTRX_CFG_IND_DATA0r = 416,
+	NPPU_PKTRX_CFG_IND_DATA1r = 417,
+	NPPU_PKTRX_CFG_IND_DATA2r = 418,
+	NPPU_PKTRX_CFG_IND_DATA3r = 419,
+	NPPU_PKTRX_CFG_IND_DATA4r = 420,
+	NPPU_PKTRX_CFG_IND_DATA5r = 421,
+	NPPU_PKTRX_CFG_IND_DATA6r = 422,
+	NPPU_PKTRX_CFG_IND_DATA7r = 423,
+	NPPU_PKTRX_CFG_TCAM_0_CMDr = 424,
+	NPPU_PKTRX_CFG_TCAM_1_CMDr = 425,
+	NPPU_PKTRX_CFG_PORT_EN_0r = 426,
+	NPPU_PKTRX_CFG_PORT_EN_1r = 427,
+	NPPU_PKTRX_CFG_PORT_EN_2r = 428,
+	NPPU_PKTRX_CFG_PORT_EN_3r = 429,
+	NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_0r = 430,
+	NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_1r = 431,
+	NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_2r = 432,
+	NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_3r = 433,
+	NPPU_PKTRX_CFG_PORT_FC_MODE_0r = 434,
+	NPPU_PKTRX_CFG_PORT_FC_MODE_1r = 435,
+	NPPU_PKTRX_CFG_PORT_FC_MODE_2r = 436,
+	NPPU_PKTRX_CFG_PORT_FC_MODE_3r = 437,
+	NPPU_PKTRX_CFG_PORT_FC_MODE_4r = 438,
+	NPPU_PKTRX_CFG_PORT_FC_MODE_5r = 439,
+	NPPU_PKTRX_CFG_PORT_FC_MODE_6r = 440,
+	NPPU_PKTRX_CFG_PORT_FC_MODE_7r = 441,
+	NPPU_PKTRX_CFG_CFG_ISCH_AGING_THr = 442,
+	NPPU_PKTRX_CFG_ISCH_FIFO_TH_0r = 443,
+	NPPU_PKTRX_CFG_ISCH_CFG_1r = 444,
+	NPPU_PKTRX_CFG_TCAM_0_VLDr = 445,
+	NPPU_PKTRX_CFG_TCAM_1_VLDr = 446,
+	NPPU_PKTRX_CFG_CPU_PORT_EN_MASKr = 447,
+	NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_0r = 448,
+	NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_1r = 449,
+	NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_2r = 450,
+	NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_3r = 451,
+	NPPU_PKTRX_CFG_NPPU_STARTr = 452,
+	NPPU_PKTRX_STAT_IND_STATUSr = 453,
+	NPPU_PKTRX_STAT_IND_CMDr = 454,
+	NPPU_PKTRX_STAT_IND_DATA0r = 455,
+	NPPU_IDMA_CFG_DEBUG_CNT_OVFL_MODEr = 456,
+	NPPU_IDMA_STAT_IND_STATUSr = 457,
+	NPPU_IDMA_STAT_IND_CMDr = 458,
+	NPPU_IDMA_STAT_IND_DATA0r = 459,
+	NPPU_PBU_CFG_IND_STATUSr = 460,
+	NPPU_PBU_CFG_IND_CMDr = 461,
+	NPPU_PBU_CFG_IND_DATA0r = 462,
+	NPPU_PBU_CFG_IND_DATA1r = 463,
+	NPPU_PBU_CFG_IND_DATA2r = 464,
+	NPPU_PBU_CFG_IND_DATA3r = 465,
+	NPPU_PBU_CFG_IND_DATA4r = 466,
+	NPPU_PBU_CFG_IND_DATA5r = 467,
+	NPPU_PBU_CFG_IND_DATA6r = 468,
+	NPPU_PBU_CFG_IND_DATA7r = 469,
+	NPPU_PBU_CFG_IDMA_PUBLIC_THr = 470,
+	NPPU_PBU_CFG_LIF_PUBLIC_THr = 471,
+	NPPU_PBU_CFG_IDMA_TOTAL_THr = 472,
+	NPPU_PBU_CFG_LIF_TOTAL_THr = 473,
+	NPPU_PBU_CFG_MC_TOTAL_THr = 474,
+	NPPU_PBU_CFG_MC_COS10_THr = 475,
+	NPPU_PBU_CFG_MC_COS32_THr = 476,
+	NPPU_PBU_CFG_MC_COS54_THr = 477,
+	NPPU_PBU_CFG_MC_COS76_THr = 478,
+	NPPU_PBU_CFG_DEBUG_CNT_OVFL_MODEr = 479,
+	NPPU_PBU_CFG_SE_KEY_AFUL_NEGATE_CFGr = 480,
+	NPPU_PBU_CFG_SA_FLAGr = 481,
+	NPPU_PBU_STAT_IND_DATAr = 482,
+	NPPU_PBU_STAT_IND_STATUSr = 483,
+	NPPU_PBU_STAT_IND_CMDr = 484,
+	NPPU_PBU_STAT_TOTAL_CNTr = 485,
+	NPPU_PBU_STAT_IDMA_PUB_CNTr = 486,
+	NPPU_PBU_STAT_LIF_PUB_CNTr = 487,
+	NPPU_PBU_STAT_MC_TOTAL_CNTr = 488,
+	NPPU_PBU_STAT_PBU_THRAM_INIT_DONEr = 489,
+	NPPU_PBU_STAT_IFB_FPTR_INIT_DONEr = 490,
+	NPPU_ISU_CFG_WEIGHT_NORMAL_UCr = 491,
+	NPPU_ISU_CFG_FABRIC_OR_SAIPr = 492,
+	NPPU_ISU_STAT_IND_STATUSr = 493,
+	NPPU_ISU_STAT_IND_CMDr = 494,
+	NPPU_ISU_STAT_IND_DAT0r = 495,
+	NPPU_ODMA_CFG_IND_ACCESS_DONEr = 496,
+	NPPU_ODMA_CFG_IND_COMMANDr = 497,
+	NPPU_ODMA_CFG_IND_DAT0r = 498,
+	NPPU_ODMA_CFG_IND_DAT1r = 499,
+	NPPU_ODMA_CFG_FABRIC_OR_SAIPr = 500,
+	NPPU_ODMA_CFG_MAX_PKT_LENr = 501,
+	NPPU_ODMA_CFG_AGE_ENr = 502,
+	NPPU_ODMA_CFG_AGE_MODEr = 503,
+	NPPU_ODMA_CFG_AGE_VALUE_TIMEr = 504,
+	NPPU_ODMA_CFG_AGE_VALUE_ROOMr = 505,
+	NPPU_ODMA_CFG_AGE_OUT_CNTr = 506,
+	NPPU_ODMA_CFG_TOKEN_VALUE_Ar = 507,
+	NPPU_ODMA_CFG_TOKEN_VALUE_Br = 508,
+	NPPU_ODMA_CFG_CFG_SHAP_EN_P0r = 509,
+	NPPU_ODMA_CFG_CFG_SHAP_EN_P1r = 510,
+	NPPU_ODMA_CFG_CFG_SHAP_EN_TMr = 511,
+	NPPU_ODMA_STAT_IND_STATUSr = 512,
+	NPPU_ODMA_STAT_IND_CMDr = 513,
+	NPPU_ODMA_STAT_IND_DATA0r = 514,
+	NPPU_ODMA_STAT_DEBUG_CNT_CFGr = 515,
+	NPPU_OAM_CFG_BFD_FIRSTCHK_THr = 516,
+	NPPU_PBU_CFG_MEMID_0_PBU_FC_IDMATH_RAMr = 517,
+	NPPU_PBU_CFG_MEMID_1_PBU_FC_MACTH_RAMr = 518,
+	NPPU_PBU_STAT_MEMID_1_ALL_KIND_PORT_CNTr = 519,
+	NPPU_PBU_STAT_MEMID_2_PPU_PBU_IFB_REQ_VLD_CNTr = 520,
+	NPPU_PBU_STAT_MEMID_2_PBU_PPU_IFB_RSP_VLD_CNTr = 521,
+	NPPU_PBU_STAT_MEMID_2_ODMA_PBU_RECY_PTR_VLD_CNTr = 522,
+	NPPU_PBU_STAT_MEMID_2_PPU_PBU_MCODE_PF_REQ_CNTr = 523,
+	NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_RSP_CNTr = 524,
+	NPPU_PBU_STAT_MEMID_2_PPU_PBU_LOGIC_PF_REQ_CNTr = 525,
+	NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_RSP_CNTr = 526,
+	NPPU_PBU_STAT_MEMID_2_PPU_USE_PTR_PULSE_CNTr = 527,
+	NPPU_PBU_STAT_MEMID_2_PPU_PBU_WB_VLD_CNTr = 528,
+	NPPU_PBU_STAT_MEMID_2_PBU_PPU_REORDER_PARA_VLD_CNTr = 529,
+	NPPU_PBU_STAT_MEMID_2_SE_PBU_DPI_KEY_VLD_CNTr = 530,
+	NPPU_PBU_STAT_MEMID_2_PBU_SE_DPI_RSP_DATVLD_CNTr = 531,
+	NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD1_CNTr = 532,
+	NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD2_CNTr = 533,
+	NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_NO_RSP_CNTr = 534,
+	NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_NO_RSP_CNTr = 535,
+	NPPU_PBU_STAT_MEMID_3_CPU_RD_IFB_DATAr = 536,
+	NPPU_PBU_STAT_MEMID_4_MUX_SEL_RGTr = 537,
+	NPPU_PBU_STAT_MEMID_5_PORT_PUB_CNTr = 538,
+	NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_PKT_PULSE_TOTAL_CNTr = 539,
+	NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_EPKT_PULSE_TOTAL_CNTr = 540,
+	NPPU_IDMA_STAT_MEMID_1_IDMA_DISPKT_PULSE_TOTAL_CNTr = 541,
+	NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_PKT_PULSE_CNTr = 542,
+	NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_EPKT_PULSE_CNTr = 543,
+	NPPU_IDMA_STAT_MEMID_0_IDMA_DISPKT_PULSE_CNTr = 544,
+	PPU_PPU_TEST_Rr = 545,
+	PPU_PPU_PPU_DEBUG_EN_Rr = 546,
+	PPU_PPU_CSR_DUP_TABLE_WR_DATAr = 547,
+	PPU_PPU_CSR_DUP_TABLE_RD_DATAr = 548,
+	PPU_PPU_CSR_DUP_TABLE_ADDRr = 549,
+	PPU_PPU_PPU_DEBUG_VLDr = 550,
+	PPU_PPU_COP_THASH_RSK_319_288r = 551,
+	PPU_PPU_COP_THASH_RSK_287_256r = 552,
+	PPU_PPU_COP_THASH_RSK_255_224r = 553,
+	PPU_PPU_COP_THASH_RSK_223_192r = 554,
+	PPU_PPU_COP_THASH_RSK_191_160r = 555,
+	PPU_PPU_COP_THASH_RSK_159_128r = 556,
+	PPU_PPU_COP_THASH_RSK_127_096r = 557,
+	PPU_PPU_COP_THASH_RSK_095_064r = 558,
+	PPU_PPU_COP_THASH_RSK_063_032r = 559,
+	PPU_PPU_COP_THASH_RSK_031_000r = 560,
+	PPU_PPU_CFG_IPV4_IPID_START_VALUEr = 561,
+	PPU_PPU_CFG_IPV4_IPID_END_VALUEr = 562,
+	PPU_PPU_CLUSTER_MF_IN_ENr = 563,
+	PPU_PPU_PPU_EMPTYr = 564,
+	PPU_PPU_INSTRMEM_W_ADDRr = 565,
+	PPU_PPU_INSTRMEM_W_DATA_191_160r = 566,
+	PPU_PPU_INSTRMEM_W_DATA_159_128r = 567,
+	PPU_PPU_INSTRMEM_W_DATA_127_96r = 568,
+	PPU_PPU_INSTRMEM_W_DATA_95_64r = 569,
+	PPU_PPU_INSTRMEM_W_DATA_63_32r = 570,
+	PPU_PPU_INSTRMEM_W_DATA_31_0r = 571,
+	PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_ASSERT_CFGr = 572,
+	PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_NEGATE_CFGr = 573,
+	PPU_CLUSTER_INT_1200M_MASKr = 574,
+	PPU4K_CLUSTER_WR_HIGH_DATA_R_MEXr = 575,
+	PPU4K_CLUSTER_WR_LOW_DATA_R_MEXr = 576,
+	PPU4K_CLUSTER_ADDR_R_MEXr = 577,
+	PPU4K_CLUSTER_SDT_TBL_IND_ACCESS_DONEr = 578,
+	PPU4K_CLUSTER_RD_HIGH_DATA_R_MEXr = 579,
+	PPU4K_CLUSTER_RD_LOW_DATA_R_MEXr = 580,
+	SE_ALG_INIT_OKr = 581,
+	SE_ALG_CPU_RD_RDYr = 582,
+	SE_ALG_CPU_RD_DATA_TMP0r = 583,
+	SE_ALG_CPU_RD_DATA_TMP1r = 584,
+	SE_ALG_CPU_RD_DATA_TMP2r = 585,
+	SE_ALG_CPU_RD_DATA_TMP3r = 586,
+	SE_ALG_CPU_RD_DATA_TMP4r = 587,
+	SE_ALG_CPU_RD_DATA_TMP5r = 588,
+	SE_ALG_CPU_RD_DATA_TMP6r = 589,
+	SE_ALG_CPU_RD_DATA_TMP7r = 590,
+	SE_ALG_CPU_RD_DATA_TMP8r = 591,
+	SE_ALG_CPU_RD_DATA_TMP9r = 592,
+	SE_ALG_CPU_RD_DATA_TMP10r = 593,
+	SE_ALG_CPU_RD_DATA_TMP11r = 594,
+	SE_ALG_CPU_RD_DATA_TMP12r = 595,
+	SE_ALG_CPU_RD_DATA_TMP13r = 596,
+	SE_ALG_CPU_RD_DATA_TMP14r = 597,
+	SE_ALG_CPU_RD_DATA_TMP15r = 598,
+	SE_ALG_LPM_V4_CONFIG_RGTr = 599,
+	SE_ALG_LPM_V6_CONFIG_RGTr = 600,
+	SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_ASTr = 601,
+	SE_AS_HASH_AGE_PAT_CFGr = 602,
+	SE_AS_LEARN_RDY_CFGr = 603,
+	SE_KSCHD_KSCHD_AS_PFUL_CFGr = 604,
+	SE_KSCHD_KSCHD_DIR_PFUL_CFGr = 605,
+	SE_KSCHD_KSCHD_AS_EPT_CFGr = 606,
+	SE_KSCHD_CPU_ARBI_PFUL_CFGr = 607,
+	SE_KSCHD_KSCHD_PBU_PFUL_CFGr = 608,
+	SE_RSCHD_RSCHD_DIR_PFUL_CFGr = 609,
+	SE_RSCHD_RSCHD_DIR_EPT_CFGr = 610,
+	SE4K_SE_ALG_CPU_CMD_RGTr = 611,
+	SE4K_SE_ALG_CPU_WR_DATA_TMP0r = 612,
+	SE4K_SE_ALG_CPU_WR_DATA_TMP1r = 613,
+	SE4K_SE_ALG_CPU_WR_DATA_TMP2r = 614,
+	SE4K_SE_ALG_CPU_WR_DATA_TMP3r = 615,
+	SE4K_SE_ALG_CPU_WR_DATA_TMP4r = 616,
+	SE4K_SE_ALG_CPU_WR_DATA_TMP5r = 617,
+	SE4K_SE_ALG_CPU_WR_DATA_TMP6r = 618,
+	SE4K_SE_ALG_CPU_WR_DATA_TMP7r = 619,
+	SE4K_SE_ALG_CPU_WR_DATA_TMP8r = 620,
+	SE4K_SE_ALG_CPU_WR_DATA_TMP9r = 621,
+	SE4K_SE_ALG_CPU_WR_DATA_TMP10r = 622,
+	SE4K_SE_ALG_CPU_WR_DATA_TMP11r = 623,
+	SE4K_SE_ALG_CPU_WR_DATA_TMP12r = 624,
+	SE4K_SE_ALG_CPU_WR_DATA_TMP13r = 625,
+	SE4K_SE_ALG_CPU_WR_DATA_TMP14r = 626,
+	SE4K_SE_ALG_CPU_WR_DATA_TMP15r = 627,
+	SE4K_SE_ALG_CPU_RD_RDYr = 628,
+	SE4K_SE_ALG_CPU_RD_DATA_TMP0r = 629,
+	SE4K_SE_ALG_CPU_RD_DATA_TMP1r = 630,
+	SE4K_SE_ALG_CPU_RD_DATA_TMP2r = 631,
+	SE4K_SE_ALG_CPU_RD_DATA_TMP3r = 632,
+	SE4K_SE_ALG_CPU_RD_DATA_TMP4r = 633,
+	SE4K_SE_ALG_CPU_RD_DATA_TMP5r = 634,
+	SE4K_SE_ALG_CPU_RD_DATA_TMP6r = 635,
+	SE4K_SE_ALG_CPU_RD_DATA_TMP7r = 636,
+	SE4K_SE_ALG_CPU_RD_DATA_TMP8r = 637,
+	SE4K_SE_ALG_CPU_RD_DATA_TMP9r = 638,
+	SE4K_SE_ALG_CPU_RD_DATA_TMP10r = 639,
+	SE4K_SE_ALG_CPU_RD_DATA_TMP11r = 640,
+	SE4K_SE_ALG_CPU_RD_DATA_TMP12r = 641,
+	SE4K_SE_ALG_CPU_RD_DATA_TMP13r = 642,
+	SE4K_SE_ALG_CPU_RD_DATA_TMP14r = 643,
+	SE4K_SE_ALG_CPU_RD_DATA_TMP15r = 644,
+	SE4K_SE_ALG_HASH0_EXT_CFG_RGTr = 645,
+	SE4K_SE_ALG_HASH1_EXT_CFG_RGTr = 646,
+	SE4K_SE_ALG_HASH2_EXT_CFG_RGTr = 647,
+	SE4K_SE_ALG_HASH3_EXT_CFG_RGTr = 648,
+	SE4K_SE_ALG_HASH0_TBL30_DEPTHr = 649,
+	SE4K_SE_ALG_HASH0_TBL74_DEPTHr = 650,
+	SE4K_SE_ALG_HASH1_TBL30_DEPTHr = 651,
+	SE4K_SE_ALG_HASH1_TBL74_DEPTHr = 652,
+	SE4K_SE_ALG_HASH2_TBL30_DEPTHr = 653,
+	SE4K_SE_ALG_HASH2_TBL74_DEPTHr = 654,
+	SE4K_SE_ALG_HASH3_TBL30_DEPTHr = 655,
+	SE4K_SE_ALG_HASH3_TBL74_DEPTHr = 656,
+	SE4K_SE_ALG_WR_RSP_CFGr = 657,
+	SE4K_SE_ALG_HASH_MONO_FLAGr = 658,
+	SE4K_SE_ALG_HASH10_EXT_CRC_CFGr = 659,
+	SE4K_SE_ALG_HASH32_EXT_CRC_CFGr = 660,
+	SE4K_SE_ALG_ZBLOCK_SERVICE_CONFIGUREr = 661,
+	SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONOr = 662,
+	SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONOr = 663,
+	SMMU0_SMMU0_INIT_DONEr = 664,
+	SMMU0_SMMU0_CPU_IND_WDAT0r = 665,
+	SMMU0_SMMU0_CPU_IND_WDAT1r = 666,
+	SMMU0_SMMU0_CPU_IND_WDAT2r = 667,
+	SMMU0_SMMU0_CPU_IND_WDAT3r = 668,
+	SMMU0_SMMU0_CPU_IND_CMDr = 669,
+	SMMU0_SMMU0_CPU_IND_RD_DONEr = 670,
+	SMMU0_SMMU0_CPU_IND_RDAT0r = 671,
+	SMMU0_SMMU0_CPU_IND_RDAT1r = 672,
+	SMMU0_SMMU0_CPU_IND_RDAT2r = 673,
+	SMMU0_SMMU0_CPU_IND_RDAT3r = 674,
+	SMMU0_SMMU0_CFG_PLCR_MONOr = 675,
+	SMMU0_SMMU0_WR_ARB_CPU_RDYr = 676,
+	SMMU0_SMMU0_TM_STAT_EN_CFGr = 677,
+	SE_SMMU1_DDR_WDAT0r = 678,
+	SE_SMMU1_DIR_ARBI_SER_RPFULr = 679,
+	SE_SMMU1_CFG_WR_ARBI_PFUL2r = 680,
+	SE_SMMU1_ETM_TBL_CFGr = 681,
+	SE_SMMU1_CFG_CASH_ADDR_PFULr = 682,
+	SE_SMMU1_CTRL_RFIFO_CFGr = 683,
+	SE_SMMU1_CACHE_REQ_FIFO_CFGr = 684,
+	STAT_STAT_CFG_CPU_IND_ERAM_WDAT0r = 685,
+	STAT_STAT_CFG_ETM_PORT_SEL_CFGr = 686,
+	STAT_STAT_CFG_TM_STAT_CFGr = 687,
+	STAT_STAT_CFG_PPU_ERAM_DEPTHr = 688,
+	STAT_STAT_CFG_PPU_ERAM_BASE_ADDRr = 689,
+	STAT_STAT_CFG_PPU_DDR_BASE_ADDRr = 690,
+	STAT_STAT_CFG_PLCR0_BASE_ADDRr = 691,
+	STAT_STAT_CFG_ETM_STAT_START_ADDR_CFGr = 692,
+	STAT_STAT_CFG_ETM_STAT_DEPTH_CFGr = 693,
+	STAT_STAT_CFG_CYCLE_MOV_EN_CFGr = 694,
+	STAT_ETCAM_CPU_IND_WDAT0r = 695,
+	STAT_ETCAM_CPU_IND_CTRL_TMP0r = 696,
+	STAT_ETCAM_CPU_IND_CTRL_TMP1r = 697,
+	STAT_ETCAM_CPU_IND_RD_DONEr = 698,
+	STAT_ETCAM_CPU_RDAT0r = 699,
+	STAT_ETCAM_CPU_RDAT1r = 700,
+	STAT_ETCAM_CPU_RDAT2r = 701,
+	STAT_ETCAM_CPU_RDAT3r = 702,
+	STAT_ETCAM_CPU_RDAT4r = 703,
+	STAT_ETCAM_CPU_RDAT5r = 704,
+	STAT_ETCAM_CPU_RDAT6r = 705,
+	STAT_ETCAM_CPU_RDAT7r = 706,
+	STAT_ETCAM_CPU_RDAT8r = 707,
+	STAT_ETCAM_CPU_RDAT9r = 708,
+	STAT_ETCAM_CPU_RDAT10r = 709,
+	STAT_ETCAM_CPU_RDAT11r = 710,
+	STAT_ETCAM_CPU_RDAT12r = 711,
+	STAT_ETCAM_CPU_RDAT13r = 712,
+	STAT_ETCAM_CPU_RDAT14r = 713,
+	STAT_ETCAM_CPU_RDAT15r = 714,
+	STAT_ETCAM_CPU_RDAT16r = 715,
+	STAT_ETCAM_CPU_RDAT17r = 716,
+	STAT_ETCAM_CPU_RDAT18r = 717,
+	STAT_ETCAM_CPU_RDAT19r = 718,
+	STAT_ETCAM_QVBOr = 719,
+	STAT_ETCAM_CNT_OVERFLOW_MODEr = 720,
+	STAT_CAR0_CARA_QUEUE_RAM0_159_0r = 721,
+	STAT_CAR0_CARA_PROFILE_RAM1_255_0r = 722,
+	STAT_CAR0_CARA_QOVS_RAM_RAM2r = 723,
+	STAT_CAR0_LOOK_UP_TABLE1r = 724,
+	STAT_CAR0_CARA_PKT_DES_I_CNTr = 725,
+	STAT_CAR0_CARA_GREEN_PKT_I_CNTr = 726,
+	STAT_CAR0_CARA_YELLOW_PKT_I_CNTr = 727,
+	STAT_CAR0_CARA_RED_PKT_I_CNTr = 728,
+	STAT_CAR0_CARA_PKT_DES_O_CNTr = 729,
+	STAT_CAR0_CARA_GREEN_PKT_O_CNTr = 730,
+	STAT_CAR0_CARA_YELLOW_PKT_O_CNTr = 731,
+	STAT_CAR0_CARA_RED_PKT_O_CNTr = 732,
+	STAT_CAR0_CARA_PKT_DES_FC_FOR_CFG_CNTr = 733,
+	STAT_CAR0_CARA_APPOINT_QNUM_OR_SPr = 734,
+	STAT_CAR0_CARA_CFGMT_COUNT_MODEr = 735,
+	STAT_CAR0_CARA_PKT_SIZE_CNTr = 736,
+	STAT_CAR0_CARA_PLCR_INIT_DONTr = 737,
+	STAT_CAR0_CARB_QUEUE_RAM0_159_0r = 738,
+	STAT_CAR0_CARB_PROFILE_RAM1_255_0r = 739,
+	STAT_CAR0_CARB_QOVS_RAM_RAM2r = 740,
+	STAT_CAR0_LOOK_UP_TABLE2r = 741,
+	STAT_CAR0_CARB_PKT_DES_I_CNTr = 742,
+	STAT_CAR0_CARB_GREEN_PKT_I_CNTr = 743,
+	STAT_CAR0_CARB_YELLOW_PKT_I_CNTr = 744,
+	STAT_CAR0_CARB_RED_PKT_I_CNTr = 745,
+	STAT_CAR0_CARB_PKT_DES_O_CNTr = 746,
+	STAT_CAR0_CARB_GREEN_PKT_O_CNTr = 747,
+	STAT_CAR0_CARB_YELLOW_PKT_O_CNTr = 748,
+	STAT_CAR0_CARB_RED_PKT_O_CNTr = 749,
+	STAT_CAR0_CARB_PKT_DES_FC_FOR_CFG_CNTr = 750,
+	STAT_CAR0_CARB_APPOINT_QNUM_OR_SPr = 751,
+	STAT_CAR0_CARB_CFGMT_COUNT_MODEr = 752,
+	STAT_CAR0_CARB_PKT_SIZE_CNTr = 753,
+	STAT_CAR0_CARB_PLCR_INIT_DONTr = 754,
+	STAT_CAR0_CARC_QUEUE_RAM0_159_0r = 755,
+	STAT_CAR0_CARC_PROFILE_RAM1_255_0r = 756,
+	STAT_CAR0_CARC_QOVS_RAM_RAM2r = 757,
+	STAT_CAR0_CARC_PKT_DES_I_CNTr = 758,
+	STAT_CAR0_CARC_GREEN_PKT_I_CNTr = 759,
+	STAT_CAR0_CARC_YELLOW_PKT_I_CNTr = 760,
+	STAT_CAR0_CARC_RED_PKT_I_CNTr = 761,
+	STAT_CAR0_CARC_PKT_DES_O_CNTr = 762,
+	STAT_CAR0_CARC_GREEN_PKT_O_CNTr = 763,
+	STAT_CAR0_CARC_YELLOW_PKT_O_CNTr = 764,
+	STAT_CAR0_CARC_RED_PKT_O_CNTr = 765,
+	STAT_CAR0_CARC_PKT_DES_FC_FOR_CFG_CNTr = 766,
+	STAT_CAR0_CARC_APPOINT_QNUM_OR_SPr = 767,
+	STAT_CAR0_CARC_CFGMT_COUNT_MODEr = 768,
+	STAT_CAR0_CARC_PKT_SIZE_CNTr = 769,
+	STAT_CAR0_CARC_PLCR_INIT_DONTr = 770,
+	STAT_CAR0_CARB_RANDOM_RAMr = 771,
+	STAT_CAR0_CARC_RANDOM_RAMr = 772,
+	STAT_CAR0_CARA_BEGIN_FLOW_IDr = 773,
+	STAT_CAR0_CARB_BEGIN_FLOW_IDr = 774,
+	STAT_CAR0_CARC_BEGIN_FLOW_IDr = 775,
+	STAT_CAR0_PROG_FULL_ASSERT_CFG_Wr = 776,
+	STAT_CAR0_PROG_FULL_NEGATE_CFG_Wr = 777,
+	STAT_CAR0_TIMEOUT_LIMITr = 778,
+	STAT_CAR0_PKT_DES_FIFO_OVERFLOWr = 779,
+	STAT_CAR0_PKT_DES_FIFO_UNDERFLOWr = 780,
+	STAT_CAR0_PKT_DES_FIFO_PROG_FULLr = 781,
+	STAT_CAR0_PKT_DES_FIFO_PROG_EMPTYr = 782,
+	STAT_CAR0_PKT_DES_FIFO_FULLr = 783,
+	STAT_CAR0_PKT_DES_FIFO_EMPTYr = 784,
+	STAT_CAR0_PKT_SIZE_OFFSETr = 785,
+	STAT_CAR0_CAR_PLCR_INIT_DONTr = 786,
+	STAT_CAR0_MAX_PKT_SIZE_Ar = 787,
+	STAT_CAR0_MAX_PKT_SIZE_Br = 788,
+	STAT_CAR0_MAX_PKT_SIZE_Cr = 789,
+	STAT_CAR0_CAR_HIERARCHY_MODEr = 790,
+	STAT_CAR0_PROG_EMPTY_ASSERT_CFG_Wr = 791,
+	STAT_CAR0_PROG_EMPTY_NEGATE_CFG_Wr = 792,
+	STAT_CAR0_PKT_DES_FIFO_OVF_INTr = 793,
+	STAT_CAR0_PKT_DES_FIFO_DATA_COUNTr = 794,
+	STAT_CAR0_PKT_DES_FIFO_UDF_INTr = 795,
+	STAT_CAR0_CARA_QUEUE_RAM0_159_0_PKTr = 796,
+	STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKTr = 797,
+	STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFGr = 798,
+	STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFGr = 799,
+	STAT4K_ETCAM_BLOCK4_7_BASE_ADDR_CFGr = 800,
+	DTB_DTB_CFG_CFG_ERAM_WR_INTERVAL_CNTr = 801,
+	DTB_DTB_CFG_CFG_ZCAM_WR_INTERVAL_CNTr = 802,
+	DTB_DTB_CFG_CFG_TCAM_WR_INTERVAL_CNTr = 803,
+	DTB_DTB_CFG_CFG_DDR_WR_INTERVAL_CNTr = 804,
+	DTB_DTB_CFG_CFG_HASH_WR_INTERVAL_CNTr = 805,
+	DTB_DTB_CFG_CFG_ERAM_RD_INTERVAL_CNTr = 806,
+	DTB_DTB_CFG_CFG_ZCAM_RD_INTERVAL_CNTr = 807,
+	DTB_DTB_CFG_CFG_TCAM_RD_INTERVAL_CNTr = 808,
+	DTB_DTB_CFG_CFG_DDR_RD_INTERVAL_CNTr = 809,
+	DTB_DTB_CFG_CFG_DTB_QUEUE_LOCK_STATE_0_3r = 810,
+	DTB_DTB_AXIM0_W_CONVERT_0_MODEr = 811,
+	DTB_DTB_AXIM0_R_CONVERT_0_MODEr = 812,
+	DTB_DTB_AXIM0_AXIMR_OSr = 813,
+	DTB_DTB_AXIM1_W_CONVERT_1_MODEr = 814,
+	DTB_DTB_AXIM1_R_CONVERT_1_MODEr = 815,
+	DTB_DTB_AXIS_AXIS_CONVERT_MODEr = 816,
+	DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_H_0_127r = 817,
+	DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_L_0_127r = 818,
+	DTB4K_DTB_ENQ_CFG_QUEUE_DTB_LEN_0_127r = 819,
+	DTB4K_DTB_ENQ_INFO_QUEUE_BUF_SPACE_LEFT_0_127r = 820,
+	DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127r = 821,
+	TRPG_TRPG_RX_PORT_CPU_TRPG_MS_ENr = 822,
+	TRPG_TRPG_RX_PORT_CPU_TRPG_PORT_ENr = 823,
+	TRPG_TRPG_RX_PORT_CPU_TRPG_LOOK_ENr = 824,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_ALMOST_FULLr = 825,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_TEST_ENr = 826,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_INMOD_PFC_RDY_ENr = 827,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_Hr = 828,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_Lr = 829,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_Hr = 830,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_Lr = 831,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_CNT_CLRr = 832,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_CLK_FREQr = 833,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_ENr = 834,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_ADD_NUMr = 835,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_MAX_NUMr = 836,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_PORT_STATE_INFOr = 837,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEPr = 838,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEP_CLRr = 839,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LENr = 840,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LEN_CLRr = 841,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LENr = 842,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LEN_CLRr = 843,
+	TRPG_TRPG_RX_RAM_TRPG_RX_DATA_RAMr = 844,
+	TRPG_TRPG_RX_RAM_TRPG_RX_INFO_RAMr = 845,
+	TRPG_TRPG_TX_PORT_CPU_TRPG_MS_ENr = 846,
+	TRPG_TRPG_TX_PORT_CPU_TRPG_PORT_ENr = 847,
+	TRPG_TRPG_TX_PORT_CPU_TRPG_LOOK_ENr = 848,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_ALMOST_FULLr = 849,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_TEST_ENr = 850,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_Hr = 851,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_Lr = 852,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_Hr = 853,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_Lr = 854,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_CNT_CLRr = 855,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_CLK_FREQr = 856,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_ENr = 857,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_ADD_NUMr = 858,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_MAX_NUMr = 859,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_PORT_STATE_INFOr = 860,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEPr = 861,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEP_CLRr = 862,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LENr = 863,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LEN_CLRr = 864,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LENr = 865,
+	TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LEN_CLRr = 866,
+	TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_ALMOST_FULLr = 867,
+	TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_TEST_ENr = 868,
+	TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_MASKr = 869,
+	TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_CLRr = 870,
+	TRPG_TRPG_TX_GLB_CPU_TODTIME_RAM_TEST_ENr = 871,
+	TRPG_TRPG_TX_RAM_TRPG_TX_DATA_RAMr = 872,
+	TRPG_TRPG_TX_RAM_TRPG_TX_INFO_RAMr = 873,
+	TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_DATA_RAMr = 874,
+	TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_INFO_RAMr = 875,
+	ETM_CFGMT_CHIP_VERSION_REGr = 876,
+	ETM_CFGMT_CHIP_DATE_REGr = 877,
+	ETM_CFGMT_CFGMT_CRC_ENr = 878,
+	ETM_CFGMT_CFG_PORT_TRANSFER_ENr = 879,
+	ETM_CFGMT_TM_SA_WORK_MODEr = 880,
+	ETM_CFGMT_LOCAL_SA_IDr = 881,
+	ETM_OLIF_OLIF_RDYr = 882,
+	ETM_OLIF_EMEM_PROG_FULLr = 883,
+	ETM_OLIF_PORT_ORDER_FIFO_FULLr = 884,
+	ETM_OLIF_OLIF_RELEASE_LASTr = 885,
+	ETM_OLIF_OLIF_FIFO_EMPTY_STATEr = 886,
+	ETM_OLIF_QMU_OLIF_RELEASE_FC_CNTr = 887,
+	ETM_OLIF_OLIF_QMU_LINK_FC_CNTr = 888,
+	ETM_OLIF_LIF0_LINK_FC_CNTr = 889,
+	ETM_OLIF_OLIF_TMMU_FC_CNTr = 890,
+	ETM_OLIF_OLIF_MMU_FC_CNTr = 891,
+	ETM_OLIF_OLIF_QMU_PORT_RDY_Hr = 892,
+	ETM_OLIF_OLIF_QMU_PORT_RDY_Lr = 893,
+	ETM_OLIF_LIF0_PORT_RDY_Hr = 894,
+	ETM_OLIF_LIF0_PORT_RDY_Lr = 895,
+	ETM_OLIF_QMU_OLIF_RD_SOP_CNTr = 896,
+	ETM_OLIF_QMU_OLIF_RD_EOP_CNTr = 897,
+	ETM_OLIF_QMU_OLIF_RD_VLD_CNTr = 898,
+	ETM_OLIF_QMU_OLIF_RD_BLK_CNTr = 899,
+	ETM_OLIF_MMU_TM_DATA_SOP_CNTr = 900,
+	ETM_OLIF_MMU_TM_DATA_EOP_CNTr = 901,
+	ETM_OLIF_MMU_TM_DATA_VLD_CNTr = 902,
+	ETM_OLIF_ODMA_TM_DATA_SOP_CNTr = 903,
+	ETM_OLIF_ODMA_TM_DATA_EOP_CNTr = 904,
+	ETM_OLIF_ODMA_TM_DEQ_VLD_CNTr = 905,
+	ETM_OLIF_OLIF_QMU_RELEASE_VLD_CNTr = 906,
+	ETM_OLIF_EMEM_DAT_VLD_CNTr = 907,
+	ETM_OLIF_IMEM_DAT_VLD_CNTr = 908,
+	ETM_OLIF_EMEM_DAT_RD_CNTr = 909,
+	ETM_OLIF_IMEM_DAT_RD_CNTr = 910,
+	ETM_OLIF_QMU_OLIF_RD_SOP_EMEM_CNTr = 911,
+	ETM_OLIF_QMU_OLIF_RD_VLD_EMEM_CNTr = 912,
+	ETM_OLIF_CPU_LAST_WR_ADDRr = 913,
+	ETM_OLIF_CPU_LAST_WR_DATAr = 914,
+	ETM_OLIF_CPU_LAST_RD_ADDRr = 915,
+	ETM_OLIF_QMU_OLIF_LAST_PORTr = 916,
+	ETM_OLIF_QMU_OLIF_LAST_ADDRr = 917,
+	ETM_OLIF_QMU_OLIF_LAST_BANKr = 918,
+	ETM_OLIF_TM_LIF_BYTE_STATr = 919,
+	ETM_OLIF_TM_LIF_ERR_STATr = 920,
+	ETM_CGAVD_PORT_SHARE_CNTr = 921,
+	ETM_CGAVD_TOTAL_IMEM_CNTr = 922,
+	ETM_CGAVD_PP_Q_LENr = 923,
+	ETM_CGAVD_SYS_Q_LENr = 924,
+	ETM_CGAVD_CGAVD_CFG_ERROR_WARNINGr = 925,
+	ETM_CGAVD_MULT_QLEN_TH_ENr = 926,
+	ETM_CGAVD_MULT_QLEN_THr = 927,
+	ETM_CGAVD_CGAVD_CFG_MOVEr = 928,
+	ETM_CGAVD_CFGMT_TOTAL_THr = 929,
+	ETM_CGAVD_CFGMT_PORT_SHARE_THr = 930,
+	ETM_CGAVD_SA_UNREACH_STATEr = 931,
+	ETM_CGAVD_MV_PORT_THr = 932,
+	ETM_CGAVD_MV_DROP_SP_THr = 933,
+	ETM_CGAVD_CGAVD_STATE_WARNINGr = 934,
+	ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNTr = 935,
+	ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNT_MAXr = 936,
+	ETM_CGAVD_IMEM_TOTAL_CNTr = 937,
+	ETM_CGAVD_IMEM_TOTAL_CNT_MAXr = 938,
+	ETM_CGAVD_FLOW0_OMEM_CNTr = 939,
+	ETM_CGAVD_FLOW1_OMEM_CNTr = 940,
+	ETM_CGAVD_FLOW2_OMEM_CNTr = 941,
+	ETM_CGAVD_FLOW3_OMEM_CNTr = 942,
+	ETM_CGAVD_FLOW4_OMEM_CNTr = 943,
+	ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_1r = 944,
+	ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_2r = 945,
+	ETM_CGAVD_ODMA_CGAVD_PKT_NUM_1r = 946,
+	ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_1r = 947,
+	ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_1r = 948,
+	ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_1r = 949,
+	ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_1r = 950,
+	ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_1r = 951,
+	ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_1r = 952,
+	ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_1r = 953,
+	ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_1r = 954,
+	ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_1r = 955,
+	ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_1r = 956,
+	ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_1r = 957,
+	ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_1r = 958,
+	ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_1r = 959,
+	ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_1r = 960,
+	ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_1r = 961,
+	ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_1r = 962,
+	ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_1r = 963,
+	ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_1r = 964,
+	ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM1r = 965,
+	ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_1r = 966,
+	ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_1r = 967,
+	ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_1r = 968,
+	ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_1r = 969,
+	ETM_CGAVD_ODMA_CGAVD_PKT_NUM_2r = 970,
+	ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_2r = 971,
+	ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_2r = 972,
+	ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_2r = 973,
+	ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_2r = 974,
+	ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_2r = 975,
+	ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_2r = 976,
+	ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_2r = 977,
+	ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_2r = 978,
+	ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_2r = 979,
+	ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_2r = 980,
+	ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_2r = 981,
+	ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_2r = 982,
+	ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_2r = 983,
+	ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_2r = 984,
+	ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_2r = 985,
+	ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_2r = 986,
+	ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_2r = 987,
+	ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_2r = 988,
+	ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM_2r = 989,
+	ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_2r = 990,
+	ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_2r = 991,
+	ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_2r = 992,
+	ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_2r = 993,
+	ETM_CGAVD_MOVE_FLOW_TH_PROFILEr = 994,
+	ETM_CGAVD_MOVE_FLOW_THr = 995,
+	ETM_TMMU_EMEM_PD_FIFO_AFUL_THr = 996,
+	ETM_TMMU_DMA_DATA_FIFO_AFUL_THr = 997,
+	ETM_TMMU_TMMU_STATES_0r = 998,
+	ETM_TMMU_QMU_TMMU_WR_SOP_CNTr = 999,
+	ETM_TMMU_QMU_TMMU_WR_EOP_CNTr = 1000,
+	ETM_TMMU_QMU_TMMU_WR_DROP_CNTr = 1001,
+	ETM_TMMU_QMU_TMMU_WR_EMEM_CNTr = 1002,
+	ETM_TMMU_QMU_TMMU_WR_IMEM_CNTr = 1003,
+	ETM_TMMU_TMMU_MMU_WR_SOP_CNTr = 1004,
+	ETM_TMMU_TMMU_MMU_WR_EOP_CNTr = 1005,
+	ETM_TMMU_QMU_TMMU_RD_SOP_CNTr = 1006,
+	ETM_TMMU_QMU_TMMU_RD_EOP_CNTr = 1007,
+	ETM_TMMU_QMU_TMMU_RD_DROP_CNTr = 1008,
+	ETM_TMMU_QMU_TMMU_RD_EMEM_CNTr = 1009,
+	ETM_TMMU_QMU_TMMU_RD_IMEM_CNTr = 1010,
+	ETM_TMMU_TMMU_MMU_RD_SOP_CNTr = 1011,
+	ETM_TMMU_TMMU_MMU_RD_EOP_CNTr = 1012,
+	ETM_TMMU_TMMU_ODMA_IN_SOP_CNTr = 1013,
+	ETM_TMMU_TMMU_ODMA_IN_EOP_CNTr = 1014,
+	ETM_TMMU_TMMU_ODMA_VLD_CNTr = 1015,
+	ETM_TMMU_QMU_PD_IN_CNTr = 1016,
+	ETM_TMMU_TMMU_PD_HIT_CNTr = 1017,
+	ETM_TMMU_TMMU_PD_OUT_CNTr = 1018,
+	ETM_TMMU_TMMU_WR_CMD_FIFO_WR_CNTr = 1019,
+	ETM_TMMU_TMMU_IMEM_AGE_CNTr = 1020,
+	ETM_TMMU_TMMU_CMDSCH_RD_CNTr = 1021,
+	ETM_TMMU_TMMU_CMDSCH_DROP_CNTr = 1022,
+	ETM_TMMU_TMMU_CMDSW_DROP_CNTr = 1023,
+	ETM_TMMU_TMMU_ODMA_ENQ_RD_CNTr = 1024,
+	ETM_TMMU_TMMU_ODMA_ENQ_DROP_CNTr = 1025,
+	ETM_TMMU_TMMU_ODMA_IMEM_AGE_CNTr = 1026,
+	ETM_TMMU_TMMU_ODMA_DEQ_RD_CNTr = 1027,
+	ETM_TMMU_TMMU_ODMA_DEQ_DROP_CNTr = 1028,
+	ETM_TMMU_OLIF_TMMU_XOFF_CNTr = 1029,
+	ETM_TMMU_ODMA_TM_DATA_XOFF_CNTr = 1030,
+	ETM_TMMU_TM_ODMA_PKT_XOFF_CNTr = 1031,
+	ETM_TMMU_TM_STATE_3r = 1032,
+	ETM_TMMU_CFGMT_PD_CACHE_CMDr = 1033,
+	ETM_TMMU_CFGMT_PD_CACHE_RD_DONEr = 1034,
+	ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_0r = 1035,
+	ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_1r = 1036,
+	ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_2r = 1037,
+	ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_3r = 1038,
+	ETM_TMMU_CFGMT_TMMU_TO_ODMA_PARAr = 1039,
+	ETM_TMMU_CFGMT_DMA_DATA_FIFO_CNTr = 1040,
+	ETM_TMMU_CFGMT_CACHE_TAG_BIT0_OFFSETr = 1041,
+	ETM_TMMU_CFGMT_CACHE_TAG_BIT1_OFFSETr = 1042,
+	ETM_TMMU_CFGMT_CACHE_TAG_BIT2_OFFSETr = 1043,
+	ETM_TMMU_CFGMT_CACHE_TAG_BIT3_OFFSETr = 1044,
+	ETM_TMMU_CFGMT_CACHE_TAG_BIT4_OFFSETr = 1045,
+	ETM_TMMU_CFGMT_CACHE_TAG_BIT5_OFFSETr = 1046,
+	ETM_TMMU_CFGMT_CACHE_INDEX_BIT0_OFFSETr = 1047,
+	ETM_TMMU_CFGMT_CACHE_INDEX_BIT1_OFFSETr = 1048,
+	ETM_TMMU_CFGMT_CACHE_INDEX_BIT2_OFFSETr = 1049,
+	ETM_TMMU_CFGMT_CACHE_INDEX_BIT3_OFFSETr = 1050,
+	ETM_TMMU_CFGMT_CACHE_INDEX_BIT4_OFFSETr = 1051,
+	ETM_TMMU_CFGMT_CACHE_INDEX_BIT5_OFFSETr = 1052,
+	ETM_TMMU_CFGMT_CACHE_INDEX_BIT6_OFFSETr = 1053,
+	ETM_TMMU_CFGMT_CACHE_INDEX_BIT7_OFFSETr = 1054,
+	ETM_TMMU_CFGMT_CACHE_INDEX_BIT8_OFFSETr = 1055,
+	ETM_TMMU_CFGMT_CACHE_INDEX_BIT9_OFFSETr = 1056,
+	ETM_TMMU_CFGMT_CACHE_INDEX_BIT10_OFFSETr = 1057,
+	ETM_TMMU_CFGMT_CACHE_INDEX_BIT11_OFFSETr = 1058,
+	ETM_TMMU_CFGMT_CACHE_INDEX_BIT12_OFFSETr = 1059,
+	ETM_SHAP_BKTFULL_FIFO_FULL_FLAGREGISTERr = 1060,
+	ETM_SHAP_FIFO_FULL_REGREGISTERr = 1061,
+	ETM_SHAP_FIFO_EMPTY_REGREGISTERr = 1062,
+	ETM_SHAP_FIFO_ALMOST_FULL_REGREGISTERr = 1063,
+	ETM_SHAP_FIFO_ALMOST_EMPTY_REGREGISTERr = 1064,
+	ETM_CRDT_CREDIT_SPACE_SELECTr = 1065,
+	ETM_CRDT_STAT_SPACE_MAXr = 1066,
+	ETM_CRDT_STAT_SPACE_MINr = 1067,
+	ETM_CRDT_STAT_SPACE_CREDITr = 1068,
+	ETM_CRDT_STAT_QUE_STEP8_CREDITr = 1069,
+	ETM_CRDT_SPECIAL_QUEr = 1070,
+	ETM_CRDT_SPECIAL_QUE_CREDITr = 1071,
+	ETM_CRDT_LIF_CONGEST_CREDIT_CNTr = 1072,
+	ETM_CRDT_LIF_PORT_CONGEST_CREDIT_CNTr = 1073,
+	ETM_CRDT_CRDT_CONGEST_CREDIT_CNTr = 1074,
+	ETM_CRDT_CRDT_PORT_CONGEST_CREDIT_CNTr = 1075,
+	ETM_CRDT_CONGEST_PORT_IDr = 1076,
+	ETM_CRDT_DEV_LINK_CONTROLr = 1077,
+	ETM_CRDT_CRDT_SA_PORT_RDYr = 1078,
+	ETM_CRDT_CRDT_CONGEST_MODE_SELECTr = 1079,
+	ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNTr = 1080,
+	ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNTr = 1081,
+	ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNTr = 1082,
+	ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNTr = 1083,
+	ETM_CRDT_MODE_ADD_60Gr = 1084,
+	ETM_CRDT_PP_TOKEN_ADDr = 1085,
+	ETM_CRDT_PP_CIR_TOKEN_TOTAL_DIST_CNTr = 1086,
+	ETM_CRDT_PP_CIR_TOKEN_TOTAL_DEC_CNTr = 1087,
+	ETM_CRDT_DEV_CREDIT_CNTr = 1088,
+	ETM_CRDT_NO_CREDIT_CNT1r = 1089,
+	ETM_CRDT_NO_CREDIT_CNT2r = 1090,
+	ETM_CRDT_ASM_INTERVAL_0_CFGr = 1091,
+	ETM_CRDT_ASM_INTERVAL_1_CFGr = 1092,
+	ETM_CRDT_ASM_INTERVAL_2_CFGr = 1093,
+	ETM_CRDT_ASM_INTERVAL_3_CFGr = 1094,
+	ETM_CRDT_ASM_INTERVAL_4_CFGr = 1095,
+	ETM_CRDT_ASM_INTERVAL_5CFGr = 1096,
+	ETM_CRDT_ASM_INTERVAL_6_CFGr = 1097,
+	ETM_CRDT_ASM_INTERVAL_7_CFGr = 1098,
+	ETM_CRDT_CRDT_TOTAL_CONGEST_MODE_CFGr = 1099,
+	ETM_CRDT_RCI_FIFO_INI_DEEP_CFGr = 1100,
+	ETM_CRDT_CRDT_ECCr = 1101,
+	ETM_CRDT_UCN_ASM_RDY_SHIELD_ENr = 1102,
+	ETM_CRDT_UCN_ASM_RDYr = 1103,
+	ETM_CRDT_RCI_GRADEr = 1104,
+	ETM_CRDT_CRDT_RCI_VALUE_Rr = 1105,
+	ETM_CRDT_CRDT_INTERVAL_NOWr = 1106,
+	ETM_CRDT_CRS_SHEILD_FLOW_ID_CFGr = 1107,
+	ETM_CRDT_CRS_SHEILD_EN_CFGr = 1108,
+	ETM_CRDT_CRS_SHEILD_VALUE_CFGr = 1109,
+	ETM_CRDT_TEST_TOKEN_CALC_CTRLr = 1110,
+	ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUMr = 1111,
+	ETM_CRDT_Q_STATE_0_7r = 1112,
+	ETM_CRDT_Q_STATE_8_15r = 1113,
+	ETM_QMU_CSW_CSCH_RD_CMD_CNTr = 1114,
+	ETM_QMU_CSW_CSCH_RD_SOP_CNTr = 1115,
+	ETM_QMU_CSW_CSCH_RD_EOP_CNTr = 1116,
+	ETM_QMU_CSW_CSCH_RD_DROP_CNTr = 1117,
+	ETM_QMU_CSCH_MMU_RD_CMD_CNTr = 1118,
+	ETM_QMU_CSCH_MMU_RD_SOP_CNTr = 1119,
+	ETM_QMU_CSCH_MMU_RD_EOP_CNTr = 1120,
+	ETM_QMU_CSCH_MMU_RD_DROP_CNTr = 1121,
+	ETM_QMU_QCFG_QSCH_CRS_FILTERr = 1122,
+	ETM_QMU_QCFG_QSCH_CRS_FORCE_ENr = 1123,
+	ETM_QMU_QCFG_QSCH_CRS_FORCE_QNUMr = 1124,
+	ETM_QMU_QCFG_QSCH_CRS_FORCE_CRSr = 1125,
+	ETM_QMU_CFGMT_OSHP_SGMII_SHAP_MODEr = 1126,
+	ETM_QMU_CFGMT_QMU_SASHAP_ENr = 1127,
+	ETM_QMU_CFGMT_SASHAP_TOKEN_MAXr = 1128,
+	ETM_QMU_CFGMT_SASHAP_TOKEN_MINr = 1129,
+	ETM_QMU_CFG_QSCH_Q3LBADDRATEr = 1130,
+	ETM_QMU_CFG_QSCH_Q012LBADDRATEr = 1131,
+	ETM_QMU_CFG_QSCH_Q3CREDITLBMAXCNTr = 1132,
+	ETM_QMU_CFG_QSCH_Q012CREDITLBMAXCNTr = 1133,
+	ETM_QMU_CFG_QSCH_MUL_TOKEN_GEN_NUMr = 1134,
+	ETM_QMU_CFG_QSCH_Q3_CREDIT_LB_CONTROL_ENr = 1135,
+	ETM_QMU_CFG_QSCH_Q012_CREDIT_LB_CONTROL_ENr = 1136,
+	ETM_QMU_CFG_QSCH_SP_DWRR_ENr = 1137,
+	ETM_QMU_CFG_QSCH_Q01_ATTACH_ENr = 1138,
+	ETM_QMU_CFG_QSCH_W0r = 1139,
+	ETM_QMU_CFG_QSCH_W1r = 1140,
+	ETM_QMU_CFG_QSCH_W2r = 1141,
+	ETM_QMU_CFG_QSCH_LKYBKTMAXCNT1r = 1142,
+	ETM_QMU_CFG_QSCH_LKYBKTMAXCNT2r = 1143,
+	ETM_QMU_CFG_QSCH_LKYBKTDCRRATE1r = 1144,
+	ETM_QMU_CFG_QSCH_LKYBKTDCRRATE2r = 1145,
+	ETM_QMU_CFG_QSCH_LKYBKTDCRRATE3r = 1146,
+	ETM_QMU_CFG_QSCH_LKYBKTMAXCNT3r = 1147,
+	ETM_QMU_CFG_QSCH_QMU_MUL_AUTO_SA_VERSIONr = 1148,
+	ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0r = 1149,
+	ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_1r = 1150,
+	ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_2r = 1151,
+	ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_3r = 1152,
+	ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_4r = 1153,
+	ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_5r = 1154,
+	ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_6r = 1155,
+	ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_7r = 1156,
+	ETM_QMU_CFG_QSCH_REMOTE_CREDIT_FIFO_ALMOST_FULL_THr = 1157,
+	ETM_QMU_CFG_QSCH_AUTO_CREDIT_FIFO_ALMOST_FULL_THr = 1158,
+	ETM_QMU_CFG_QSCH_Q3_CREDIT_FIFO_ALMOST_FULL_THr = 1159,
+	ETM_QMU_CFG_QSCH_Q012_CREDIT_FIFO_ALMOST_FULL_THr = 1160,
+	ETM_QMU_CFG_QSCH_MUL_FC_RES_ENr = 1161,
+	ETM_QMU_CFGMT_MUL_OVF_UDF_FLG_QUERYr = 1162,
+	ETM_QMU_CFGMT_MUL_CNG_FLG_QUERYr = 1163,
+	ETM_QMU_QSCH_CFG_LKYBKTVAL1r = 1164,
+	ETM_QMU_QSCH_CFG_LKYBKTVAL2r = 1165,
+	ETM_QMU_QSCH_CFG_LKYBKTVAL3r = 1166,
+	ETM_QMU_QSCH_CFG_Q3LBVALr = 1167,
+	ETM_QMU_QSCH_CFG_Q012LBVALr = 1168,
+	ETM_QMU_QLIST_CFGMT_RAM_ECC_ERR2r = 1169,
+	ETM_QMU_CSCH_AGED_CMD_CNTr = 1170,
+	ETM_QMU_CSCH_QCFG_CSCH_CONGEST_CNTr = 1171,
+	ETM_QMU_CSCH_QCFG_QLIST_CSCH_SOP_CNTr = 1172,
+	ETM_QMU_CSCH_QCFG_QLIST_CSCH_EOP_CNTr = 1173,
+	ETM_QMU_CSCH_QCFG_CSCH_CSW_SOP_CNTr = 1174,
+	ETM_QMU_CSCH_QCFG_CSCH_CSW_EOP_CNTr = 1175,
+	ETM_QMU_CSCH_QCFG_QLIST_CSCH_DROP_CNTr = 1176,
+	ETM_QMU_CSCH_QCFG_CSCH_CSW_DROP_CNTr = 1177,
+	ETM_QMU_CSW_MMU_SOP_CMD_CNTr = 1178,
+	ETM_QMU_MMU_CSW_SOP_DATA_CNTr = 1179,
+	ETM_QMU_CSW_QSCH_FEEDB_CNTr = 1180,
+	ETM_QMU_QMU_CRDT_PORT_FC_CNTr = 1181,
+	ETM_QMU_CSCH_R_BLOCK_CNTr = 1182,
+	ETM_QMU_QCFG_QLIST_QDS_HEAD_RDr = 1183,
+	ETM_QMU_QCFG_QLIST_QDS_TAIL_RDr = 1184,
+	ETM_QMU_QCFG_QLIST_EPT_RDr = 1185,
+	ETM_QMU_QCFG_QLIST_AGE_FLAG_RDr = 1186,
+	ETM_QMU_QCFG_QLIST_CTI_RDr = 1187,
+	ETM_QMU_QCFG_QLIST_CTO_RDr = 1188,
+	ETM_QMU_QCFG_QLIST_CHK_RDr = 1189,
+	ETM_QMU_QCFG_QLIST_NOD_RDr = 1190,
+	ETM_QMU_QCFG_QLIST_BIU_RDr = 1191,
+	ETM_QMU_QSCH_R_WLIST_FLAGr = 1192,
+	ETM_QMU_QCFG_CRS_FLG_RDr = 1193,
+	ETM_QMU_CFGMT_QMU_IMEM_AGE_QDSr = 1194,
+	ETM_QMU_CFGMT_QMU_IMEM_AGE_QLENr = 1195,
+	ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_LOWr = 1196,
+	ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_HIGHr = 1197,
+	ETM_QMU_CFGMT_QMU_IMEM_UP_PTRr = 1198,
+	ETM_QMU_CFGMT_QMU_IMEM_DOWN_PTRr = 1199,
+	ETM_QMU_CFGMT_QMU_IMEM_AGE_FLAGr = 1200,
+	ETM_QMU_CFG_QSCH_LKYBKT2CNGTHr = 1201,
+	ETM_QMU_CFG_QSCH_LKYBKT1CNGTHr = 1202,
+	ETM_QMU_CFG_QSCH_LKYBKT3CNGTHr = 1203,
+	ETM_QMU_CFG_QSCH_RM_MUL_MCN1_CREDIT_VALUEr = 1204,
+	ETM_QMU_CFG_QSCH_RM_MUL_MCN2_CREDIT_VALUEr = 1205,
+	ETM_QMU_CFG_QSCH_RM_MUL_MCN3_CREDIT_VALUEr = 1206,
+	ETM_QMU_RM_MUL_MCN1_RAND_ANSR_SEEDr = 1207,
+	ETM_QMU_RM_MUL_MCN2_RAND_ANSR_SEEDr = 1208,
+	ETM_QMU_RM_MUL_MCN3_RAND_ANSR_SEEDr = 1209,
+	ETM_QMU_RM_MUL_MCN1_RAND_ANSR_THr = 1210,
+	ETM_QMU_RM_MUL_MCN2_RAND_ANSR_THr = 1211,
+	ETM_QMU_RM_MUL_MCN3_RAND_ANSR_THr = 1212,
+	ETM_QMU_RM_MUL_MCN1_RAND_HOLD_BASEr = 1213,
+	ETM_QMU_RM_MUL_MCN2_RAND_HOLD_BASEr = 1214,
+	ETM_QMU_RM_MUL_MCN3_RAND_HOLD_BASEr = 1215,
+	ETM_QMU_RM_MUL_MCN1_RAND_SEL_MASKr = 1216,
+	ETM_QMU_RM_MUL_MCN2_RAND_SEL_MASKr = 1217,
+	ETM_QMU_RM_MUL_MCN3_RAND_SEL_MASKr = 1218,
+	ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG0r = 1219,
+	ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG1r = 1220,
+	ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG0r = 1221,
+	ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG1r = 1222,
+	ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG0r = 1223,
+	ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG1r = 1224,
+	ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH1r = 1225,
+	ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH2r = 1226,
+	ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH3r = 1227,
+	ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH4r = 1228,
+	ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH5r = 1229,
+	ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH6r = 1230,
+	ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH7r = 1231,
+	ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH1r = 1232,
+	ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH2r = 1233,
+	ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH3r = 1234,
+	ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH4r = 1235,
+	ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH5r = 1236,
+	ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH6r = 1237,
+	ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH7r = 1238,
+	ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH1r = 1239,
+	ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH2r = 1240,
+	ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH3r = 1241,
+	ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH4r = 1242,
+	ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH5r = 1243,
+	ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH6r = 1244,
+	ETM_QMU_RM_MUL_MCN3STEP_WAIT_TH7r = 1245,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE0r = 1246,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE1r = 1247,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE2r = 1248,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE3r = 1249,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE4r = 1250,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE5r = 1251,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE6r = 1252,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE7r = 1253,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE8r = 1254,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE9r = 1255,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE10r = 1256,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE11r = 1257,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE12r = 1258,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE13r = 1259,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE14r = 1260,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE15r = 1261,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE16r = 1262,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE17r = 1263,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE18r = 1264,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE19r = 1265,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE20r = 1266,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE21r = 1267,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE22r = 1268,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE23r = 1269,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE24r = 1270,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE25r = 1271,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE26r = 1272,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE27r = 1273,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE28r = 1274,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE29r = 1275,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE30r = 1276,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE31r = 1277,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE32r = 1278,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE33r = 1279,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE34r = 1280,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE35r = 1281,
+	ETM_QMU_CFG_QSCH_MULCRDCNTRATE36r = 1282,
+	ETM_QMU_CFG_QSCH_RM_MUL_MCN1_RAND_HOLD_SHIFTr = 1283,
+	ETM_QMU_CFG_QSCH_RM_MUL_MCN2_RAND_HOLD_SHIFTr = 1284,
+	ETM_QMU_CFG_QSCH_RM_MUL_MCN3_RAND_HOLD_SHIFTr = 1285,
+	ETM_QMU_LAST_DROP_QNUM_GETr = 1286,
+	ETM_QMU_CRDT_QMU_CREDIT_CNTr = 1287,
+	ETM_QMU_QMU_TO_QSCH_REPORT_CNTr = 1288,
+	ETM_QMU_QMU_TO_CGAVD_REPORT_CNTr = 1289,
+	ETM_QMU_QMU_CRDT_CRS_NORMAL_CNTr = 1290,
+	ETM_QMU_QMU_CRDT_CRS_OFF_CNTr = 1291,
+	ETM_QMU_QSCH_QLIST_SHEDULE_CNTr = 1292,
+	ETM_QMU_QSCH_QLIST_SCH_EPT_CNTr = 1293,
+	ETM_QMU_QMU_TO_MMU_BLK_WR_CNTr = 1294,
+	ETM_QMU_QMU_TO_CSW_BLK_RD_CNTr = 1295,
+	ETM_QMU_QMU_TO_MMU_SOP_WR_CNTr = 1296,
+	ETM_QMU_QMU_TO_MMU_EOP_WR_CNTr = 1297,
+	ETM_QMU_QMU_TO_MMU_DROP_WR_CNTr = 1298,
+	ETM_QMU_QMU_TO_CSW_SOP_RD_CNTr = 1299,
+	ETM_QMU_QMU_TO_CSW_EOP_RD_CNTr = 1300,
+	ETM_QMU_QMU_TO_CSW_DROP_RD_CNTr = 1301,
+	ETM_QMU_MMU_TO_QMU_WR_RELEASE_CNTr = 1302,
+	ETM_QMU_MMU_TO_QMU_RD_RELEASE_CNTr = 1303,
+	ETM_QMU_OBSERVE_QNUM_SETr = 1304,
+	ETM_QMU_SPEC_Q_PKT_RECEIVEDr = 1305,
+	ETM_QMU_SPEC_Q_PKT_DROPPEDr = 1306,
+	ETM_QMU_SPEC_Q_PKT_SCHEDULEDr = 1307,
+	ETM_QMU_SPEC_Q_WR_CMD_SENTr = 1308,
+	ETM_QMU_SPEC_Q_RD_CMD_SENTr = 1309,
+	ETM_QMU_SPEC_Q_PKT_ENQr = 1310,
+	ETM_QMU_SPEC_Q_PKT_DEQr = 1311,
+	ETM_QMU_SPEC_Q_CRDT_UNCON_RECEIVEDr = 1312,
+	ETM_QMU_SPEC_Q_CRDT_CONG_RECEIVEDr = 1313,
+	ETM_QMU_SPEC_Q_CRS_NORMAL_CNTr = 1314,
+	ETM_QMU_SPEC_Q_CRS_OFF_CNTr = 1315,
+	ETM_QMU_OBSERVE_BATCH_SETr = 1316,
+	ETM_QMU_SPEC_BAT_PKT_RECEIVEDr = 1317,
+	ETM_QMU_SPEC_BAT_PKT_DROPPEDr = 1318,
+	ETM_QMU_SPEC_BAT_BLK_SCHEDULEDr = 1319,
+	ETM_QMU_SPEC_BAT_WR_CMD_SENTr = 1320,
+	ETM_QMU_SPEC_BAT_RD_CMD_SENTr = 1321,
+	ETM_QMU_SPEC_BAT_PKT_ENQr = 1322,
+	ETM_QMU_SPEC_BAT_PKT_DEQr = 1323,
+	ETM_QMU_SPEC_BAT_CRDT_UNCON_RECEIVEDr = 1324,
+	ETM_QMU_SPEC_BAT_CRDT_CONG_RECEIVEDr = 1325,
+	ETM_QMU_SPEC_BAT_CRS_NORMAL_CNTr = 1326,
+	ETM_QMU_SPEC_BAT_CRS_OFF_CNTr = 1327,
+	ETM_QMU_BCNTM_OVFL_QNUM_GETr = 1328,
+	ETM_QMU_CRBAL_A_OVF_QNUM_GETr = 1329,
+	ETM_QMU_CRBAL_B_OVF_QNUM_GETr = 1330,
+	ETM_QMU_CRBAL_DROP_QNUM_GETr = 1331,
+	ETM_QMU_DEQ_FLG_REPORT_CNTr = 1332,
+	ETM_QMU_SPEC_Q_CRS_GETr = 1333,
+	ETM_QMU_SPEC_Q_CRS_IN_GETr = 1334,
+	ETM_QMU_SPEC_Q_CRS_FLG_CSOL_GETr = 1335,
+	ETM_QMU_EPT_SCH_QNUM_GETr = 1336,
+	CFG_PCIE_PCIE_DDR_SWITCHr = 1337,
+	CFG_PCIE_USER0_INT_ENr = 1338,
+	CFG_PCIE_USER0_INT_MASKr = 1339,
+	CFG_PCIE_USER0_INT_STATUSr = 1340,
+	CFG_PCIE_USER1_INT_ENr = 1341,
+	CFG_PCIE_USER1_INT_MASKr = 1342,
+	CFG_PCIE_USER1_INT_STATUSr = 1343,
+	CFG_PCIE_USER2_INT_ENr = 1344,
+	CFG_PCIE_USER2_INT_MASKr = 1345,
+	CFG_PCIE_USER2_INT_STATUSr = 1346,
+	CFG_PCIE_ECC_1B_INT_ENr = 1347,
+	CFG_PCIE_ECC_1B_INT_MASKr = 1348,
+	CFG_PCIE_ECC_1B_INT_STATUSr = 1349,
+	CFG_PCIE_ECC_2B_INT_ENr = 1350,
+	CFG_PCIE_ECC_2B_INT_MASKr = 1351,
+	CFG_PCIE_ECC_2B_INT_STATUSr = 1352,
+	CFG_PCIE_CFG_INT_STATUSr = 1353,
+	CFG_PCIE_I_CORE_TO_CNTLr = 1354,
+	CFG_PCIE_TEST_IN_LOWr = 1355,
+	CFG_PCIE_TEST_IN_HIGHr = 1356,
+	CFG_PCIE_LOCAL_INTERRUPT_OUTr = 1357,
+	CFG_PCIE_PL_LTSSMr = 1358,
+	CFG_PCIE_TEST_OUT0r = 1359,
+	CFG_PCIE_TEST_OUT1r = 1360,
+	CFG_PCIE_TEST_OUT2r = 1361,
+	CFG_PCIE_TEST_OUT3r = 1362,
+	CFG_PCIE_TEST_OUT4r = 1363,
+	CFG_PCIE_TEST_OUT5r = 1364,
+	CFG_PCIE_TEST_OUT6r = 1365,
+	CFG_PCIE_TEST_OUT7r = 1366,
+	CFG_PCIE_SYNC_O_CORE_STATUSr = 1367,
+	CFG_PCIE_SYNC_O_ALERT_DBEr = 1368,
+	CFG_PCIE_SYNC_O_ALERT_SBEr = 1369,
+	CFG_PCIE_SYNC_O_LINK_LOOPBACK_ENr = 1370,
+	CFG_PCIE_SYNC_O_LOCAL_FS_LF_VALIDr = 1371,
+	CFG_PCIE_SYNC_O_RX_IDLE_DETECTr = 1372,
+	CFG_PCIE_SYNC_O_RX_RDYr = 1373,
+	CFG_PCIE_SYNC_O_TX_RDYr = 1374,
+	CFG_PCIE_PCIE_LINK_UP_CNTr = 1375,
+	CFG_PCIE_TEST_OUT_PCIE0r = 1376,
+	CFG_PCIE_TEST_OUT_PCIE1r = 1377,
+	CFG_PCIE_TEST_OUT_PCIE2r = 1378,
+	CFG_PCIE_TEST_OUT_PCIE3r = 1379,
+	CFG_PCIE_TEST_OUT_PCIE4r = 1380,
+	CFG_PCIE_TEST_OUT_PCIE5r = 1381,
+	CFG_PCIE_TEST_OUT_PCIE6r = 1382,
+	CFG_PCIE_TEST_OUT_PCIE7r = 1383,
+	CFG_PCIE_TEST_OUT_PCIE8r = 1384,
+	CFG_PCIE_TEST_OUT_PCIE9r = 1385,
+	CFG_PCIE_TEST_OUT_PCIE10r = 1386,
+	CFG_PCIE_TEST_OUT_PCIE11r = 1387,
+	CFG_PCIE_TEST_OUT_PCIE12r = 1388,
+	CFG_PCIE_TEST_OUT_PCIE13r = 1389,
+	CFG_PCIE_TEST_OUT_PCIE14r = 1390,
+	CFG_PCIE_TEST_OUT_PCIE15r = 1391,
+	CFG_PCIE_INT_REPEAT_ENr = 1392,
+	CFG_PCIE_DBG_AWID_AXI_MSTr = 1393,
+	CFG_PCIE_DBG_AWADDR_AXI_MST0r = 1394,
+	CFG_PCIE_DBG_AWADDR_AXI_MST1r = 1395,
+	CFG_PCIE_DBG_AWLEN_AXI_MSTr = 1396,
+	CFG_PCIE_DBG_AWSIZE_AXI_MSTr = 1397,
+	CFG_PCIE_DBG_AWBURST_AXI_MSTr = 1398,
+	CFG_PCIE_DBG_AWLOCK_AXI_MSTr = 1399,
+	CFG_PCIE_DBG_AWCACHE_AXI_MSTr = 1400,
+	CFG_PCIE_DBG_AWPROT_AXI_MSTr = 1401,
+	CFG_PCIE_DBG_WID_AXI_MSTr = 1402,
+	CFG_PCIE_DBG_WDATA_AXI_MST0r = 1403,
+	CFG_PCIE_DBG_WDATA_AXI_MST1r = 1404,
+	CFG_PCIE_DBG_WDATA_AXI_MST2r = 1405,
+	CFG_PCIE_DBG_WDATA_AXI_MST3r = 1406,
+	CFG_PCIE_DBG_WSTRB_AXI_MSTr = 1407,
+	CFG_PCIE_DBG_WLAST_AXI_MSTr = 1408,
+	CFG_PCIE_DBG_ARID_AXI_MSTr = 1409,
+	CFG_PCIE_DBG_ARADDR_AXI_MST0r = 1410,
+	CFG_PCIE_DBG_ARADDR_AXI_MST1r = 1411,
+	CFG_PCIE_DBG_ARLEN_AXI_MSTr = 1412,
+	CFG_PCIE_DBG_ARSIZE_AXI_MSTr = 1413,
+	CFG_PCIE_DBG_ARBURST_AXI_MSTr = 1414,
+	CFG_PCIE_DBG_ARLOCK_AXI_MSTr = 1415,
+	CFG_PCIE_DBG_ARCACHE_AXI_MSTr = 1416,
+	CFG_PCIE_DBG_ARPROT_AXI_MSTr = 1417,
+	CFG_PCIE_DBG_RDATA_AXI_MST0r = 1418,
+	CFG_PCIE_DBG_RDATA_AXI_MST1r = 1419,
+	CFG_PCIE_DBG_RDATA_AXI_MST2r = 1420,
+	CFG_PCIE_DBG_RDATA_AXI_MST3r = 1421,
+	CFG_PCIE_AXI_MST_STATEr = 1422,
+	CFG_PCIE_AXI_CFG_STATEr = 1423,
+	CFG_PCIE_AXI_SLV_RD_STATEr = 1424,
+	CFG_PCIE_AXI_SLV_WR_STATEr = 1425,
+	CFG_PCIE_AXIM_DELAY_ENr = 1426,
+	CFG_PCIE_AXIM_DELAYr = 1427,
+	CFG_PCIE_AXIM_SPEED_WRr = 1428,
+	CFG_PCIE_AXIM_SPEED_RDr = 1429,
+	CFG_PCIE_DBG_AWADDR_AXI_SLV0r = 1430,
+	CFG_PCIE_DBG_AWADDR_AXI_SLV1r = 1431,
+	CFG_PCIE_DBG0_WDATA_AXI_SLV0r = 1432,
+	CFG_PCIE_DBG0_WDATA_AXI_SLV1r = 1433,
+	CFG_PCIE_DBG0_WDATA_AXI_SLV2r = 1434,
+	CFG_PCIE_DBG0_WDATA_AXI_SLV3r = 1435,
+	CFG_PCIE_DBG1_WDATA_AXI_SLV0r = 1436,
+	CFG_PCIE_DBG1_WDATA_AXI_SLV1r = 1437,
+	CFG_PCIE_DBG1_WDATA_AXI_SLV2r = 1438,
+	CFG_PCIE_DBG1_WDATA_AXI_SLV3r = 1439,
+	CFG_PCIE_DBG2_WDATA_AXI_SLV0r = 1440,
+	CFG_PCIE_DBG2_WDATA_AXI_SLV1r = 1441,
+	CFG_PCIE_DBG2_WDATA_AXI_SLV2r = 1442,
+	CFG_PCIE_DBG2_WDATA_AXI_SLV3r = 1443,
+	CFG_PCIE_DBG3_WDATA_AXI_SLV0r = 1444,
+	CFG_PCIE_DBG3_WDATA_AXI_SLV1r = 1445,
+	CFG_PCIE_DBG3_WDATA_AXI_SLV2r = 1446,
+	CFG_PCIE_DBG3_WDATA_AXI_SLV3r = 1447,
+	CFG_PCIE_DBG4_WDATA_AXI_SLV0r = 1448,
+	CFG_PCIE_DBG4_WDATA_AXI_SLV1r = 1449,
+	CFG_PCIE_DBG4_WDATA_AXI_SLV2r = 1450,
+	CFG_PCIE_DBG4_WDATA_AXI_SLV3r = 1451,
+	CFG_PCIE_DBG5_WDATA_AXI_SLV0r = 1452,
+	CFG_PCIE_DBG5_WDATA_AXI_SLV1r = 1453,
+	CFG_PCIE_DBG5_WDATA_AXI_SLV2r = 1454,
+	CFG_PCIE_DBG5_WDATA_AXI_SLV3r = 1455,
+	CFG_PCIE_DBG6_WDATA_AXI_SLV0r = 1456,
+	CFG_PCIE_DBG6_WDATA_AXI_SLV1r = 1457,
+	CFG_PCIE_DBG6_WDATA_AXI_SLV2r = 1458,
+	CFG_PCIE_DBG6_WDATA_AXI_SLV3r = 1459,
+	CFG_PCIE_DBG7_WDATA_AXI_SLV0r = 1460,
+	CFG_PCIE_DBG7_WDATA_AXI_SLV1r = 1461,
+	CFG_PCIE_DBG7_WDATA_AXI_SLV2r = 1462,
+	CFG_PCIE_DBG7_WDATA_AXI_SLV3r = 1463,
+	CFG_PCIE_DBG8_WDATA_AXI_SLV0r = 1464,
+	CFG_PCIE_DBG8_WDATA_AXI_SLV1r = 1465,
+	CFG_PCIE_DBG8_WDATA_AXI_SLV2r = 1466,
+	CFG_PCIE_DBG8_WDATA_AXI_SLV3r = 1467,
+	CFG_PCIE_DBG9_WDATA_AXI_SLV0r = 1468,
+	CFG_PCIE_DBG9_WDATA_AXI_SLV1r = 1469,
+	CFG_PCIE_DBG9_WDATA_AXI_SLV2r = 1470,
+	CFG_PCIE_DBG9_WDATA_AXI_SLV3r = 1471,
+	CFG_PCIE_DBG_AWLEN_AXI_SLVr = 1472,
+	CFG_PCIE_DBG_WLAST_AXI_SLVr = 1473,
+	CFG_PCIE_DBG_ARADDR_AXI_SLV0r = 1474,
+	CFG_PCIE_DBG_ARADDR_AXI_SLV1r = 1475,
+	CFG_PCIE_DBG0_RDATA_AXI_SLV0r = 1476,
+	CFG_PCIE_DBG0_RDATA_AXI_SLV1r = 1477,
+	CFG_PCIE_DBG0_RDATA_AXI_SLV2r = 1478,
+	CFG_PCIE_DBG0_RDATA_AXI_SLV3r = 1479,
+	CFG_PCIE_DBG1_RDATA_AXI_SLV0r = 1480,
+	CFG_PCIE_DBG1_RDATA_AXI_SLV1r = 1481,
+	CFG_PCIE_DBG1_RDATA_AXI_SLV2r = 1482,
+	CFG_PCIE_DBG1_RDATA_AXI_SLV3r = 1483,
+	CFG_PCIE_DBG_RLAST_AXI_SLVr = 1484,
+	CFG_DMA_DMA_ENABLEr = 1485,
+	CFG_DMA_UP_REQr = 1486,
+	CFG_DMA_DMA_UP_CURRENT_STATEr = 1487,
+	CFG_DMA_DMA_UP_REQ_ACKr = 1488,
+	CFG_DMA_DMA_DONE_LATCHr = 1489,
+	CFG_DMA_DMA_UP_CPU_ADDR_LOW32r = 1490,
+	CFG_DMA_DMA_UP_CPU_ADDR_HIGH32r = 1491,
+	CFG_DMA_DMA_UP_SE_ADDRr = 1492,
+	CFG_DMA_DMA_DONE_INTr = 1493,
+	CFG_DMA_SP_CFGr = 1494,
+	CFG_DMA_DMA_INGr = 1495,
+	CFG_DMA_RD_TIMEOUT_THRESHr = 1496,
+	CFG_DMA_DMA_TAB_STA_UP_FIFO_GAPr = 1497,
+	CFG_DMA_CFG_MAC_TIMr = 1498,
+	CFG_DMA_CFG_MAC_NUMr = 1499,
+	CFG_DMA_INIT_BD_ADDRr = 1500,
+	CFG_DMA_MAC_UP_BD_ADDR1_LOW32r = 1501,
+	CFG_DMA_MAC_UP_BD_ADDR1_HIGH32r = 1502,
+	CFG_DMA_MAC_UP_BD_ADDR2_LOW32r = 1503,
+	CFG_DMA_MAC_UP_BD_ADDR2_HIGH32r = 1504,
+	CFG_DMA_CFG_MAC_MAX_NUMr = 1505,
+	CFG_DMA_DMA_WBUF_FF_EMPTYr = 1506,
+	CFG_DMA_DMA_WBUF_STATEr = 1507,
+	CFG_DMA_DMA_MAC_BD_ADDR_LOW32r = 1508,
+	CFG_DMA_DMA_MAC_BD_ADDR_HIGH32r = 1509,
+	CFG_DMA_MAC_UP_ENABLEr = 1510,
+	CFG_DMA_MAC_ENDIANr = 1511,
+	CFG_DMA_UP_ENDIANr = 1512,
+	CFG_DMA_DMA_UP_RD_CNT_LATCHr = 1513,
+	CFG_DMA_DMA_UP_RCV_CNT_LATCHr = 1514,
+	CFG_DMA_DMA_UP_CNT_LATCHr = 1515,
+	CFG_DMA_CPU_RD_BD_PULSEr = 1516,
+	CFG_DMA_CPU_BD_THRESHOLDr = 1517,
+	CFG_DMA_CPU_BD_USED_CNTr = 1518,
+	CFG_DMA_DMA_UP_RCV_STATUSr = 1519,
+	CFG_DMA_SLV_RID_ERR_ENr = 1520,
+	CFG_DMA_SLV_RRESP_ERR_ENr = 1521,
+	CFG_DMA_SE_RDBK_FF_FULLr = 1522,
+	CFG_DMA_DMA_UP_DATA_COUNTr = 1523,
+	CFG_DMA_DMA_MWR_FIFO_AFULL_GAPr = 1524,
+	CFG_DMA_DMA_INFO_FIFO_AFULL_GAPr = 1525,
+	CFG_DMA_DMA_RD_TIMEOUT_SETr = 1526,
+	CFG_DMA_DMA_BD_DAT_ERR_ENr = 1527,
+	CFG_DMA_DMA_REPEAT_CNTr = 1528,
+	CFG_DMA_DMA_RD_TIMEOUT_ENr = 1529,
+	CFG_DMA_DMA_REPEAT_READr = 1530,
+	CFG_DMA_DMA_REPEAT_READ_ENr = 1531,
+	CFG_DMA_BD_CTL_STATEr = 1532,
+	CFG_DMA_DMA_DONE_INT_CNT_WRr = 1533,
+	CFG_DMA_DMA_DONE_INT_CNT_MACr = 1534,
+	CFG_DMA_CURRENT_MAC_NUMr = 1535,
+	CFG_DMA_CFG_MAC_AFIFO_AFULLr = 1536,
+	CFG_DMA_DMA_MAC_FF_FULLr = 1537,
+	CFG_DMA_USER_AXI_MSTr = 1538,
+	CFG_CSR_SBUS_STATEr = 1539,
+	CFG_CSR_MST_DEBUG_ENr = 1540,
+	CFG_CSR_SBUS_COMMAND_SELr = 1541,
+	CFG_CSR_SOC_RD_TIME_OUT_THRESHr = 1542,
+	CFG_CSR_BIG_LITTLE_BYTE_ORDERr = 1543,
+	CFG_CSR_ECC_BYPASS_READr = 1544,
+	CFG_CSR_AHB_ASYNC_WR_FIFO_AFULL_GAPr = 1545,
+	CFG_CSR_AHB_ASYNC_RD_FIFO_AFULL_GAPr = 1546,
+	CFG_CSR_AHB_ASYNC_CPL_FIFO_AFULL_GAPr = 1547,
+	CFG_CSR_MST_DEBUG_DATA0_HIGH26r = 1548,
+	CFG_CSR_MST_DEBUG_DATA0_LOW32r = 1549,
+	CFG_CSR_MST_DEBUG_DATA1_HIGH26r = 1550,
+	CFG_CSR_MST_DEBUG_DATA1_LOW32r = 1551,
+	CFG_CSR_MST_DEBUG_DATA2_HIGH26r = 1552,
+	CFG_CSR_MST_DEBUG_DATA2_LOW32r = 1553,
+	CFG_CSR_MST_DEBUG_DATA3_HIGH26r = 1554,
+	CFG_CSR_MST_DEBUG_DATA3_LOW32r = 1555,
+	CFG_CSR_MST_DEBUG_DATA4_HIGH26r = 1556,
+	CFG_CSR_MST_DEBUG_DATA4_LOW32r = 1557,
+	CFG_CSR_MST_DEBUG_DATA5_HIGH26r = 1558,
+	CFG_CSR_MST_DEBUG_DATA5_LOW32r = 1559,
+	CFG_CSR_MST_DEBUG_DATA6_HIGH26r = 1560,
+	CFG_CSR_MST_DEBUG_DATA6_LOW32r = 1561,
+	CFG_CSR_MST_DEBUG_DATA7_HIGH26r = 1562,
+	CFG_CSR_MST_DEBUG_DATA7_LOW32r = 1563,
+	CFG_CSR_MST_DEBUG_DATA8_HIGH26r = 1564,
+	CFG_CSR_MST_DEBUG_DATA8_LOW32r = 1565,
+	CFG_CSR_MST_DEBUG_DATA9_HIGH26r = 1566,
+	CFG_CSR_MST_DEBUG_DATA9_LOW32r = 1567,
+	CFG_CSR_MST_DEBUG_DATA10_HIGH26r = 1568,
+	CFG_CSR_MST_DEBUG_DATA10_LOW32r = 1569,
+	CFG_CSR_MST_DEBUG_DATA11_HIGH26r = 1570,
+	CFG_CSR_MST_DEBUG_DATA11_LOW32r = 1571,
+	CFG_CSR_MST_DEBUG_DATA12_HIGH26r = 1572,
+	CFG_CSR_MST_DEBUG_DATA12_LOW32r = 1573,
+	CFG_CSR_MST_DEBUG_DATA13_HIGH26r = 1574,
+	CFG_CSR_MST_DEBUG_DATA13_LOW32r = 1575,
+	CFG_CSR_MST_DEBUG_DATA14_HIGH26r = 1576,
+	CFG_CSR_MST_DEBUG_DATA14_LOW32r = 1577,
+	CFG_CSR_MST_DEBUG_DATA15_HIGH26r = 1578,
+	CFG_CSR_MST_DEBUG_DATA15_LOW32r = 1579,
+	NPPU_MR_CFG_IND_ACCESS_STATESr = 1580,
+	NPPU_MR_CFG_IND_ACCESS_CMD0r = 1581,
+	NPPU_MR_CFG_IND_ACCESS_DATA0r = 1582,
+	NPPU_MR_CFG_IND_ACCESS_DATA1r = 1583,
+	NPPU_MR_CFG_IND_ACCESS_CMD1r = 1584,
+	NPPU_MR_CFG_MR_INIT_DONEr = 1585,
+	NPPU_MR_CFG_CNT_MODE_REGr = 1586,
+	NPPU_MR_CFG_CFG_ECC_BYPASS_READr = 1587,
+	NPPU_MR_CFG_CFG_REP_MODr = 1588,
+	NPPU_MR_CFG_BLOCK_PTR_FIFO_AFUL_THr = 1589,
+	NPPU_MR_CFG_PRE_RCV_PTR_FIFO_AFUL_THr = 1590,
+	NPPU_MR_CFG_MGID_FIFO_AFUL_THr = 1591,
+	NPPU_MR_CFG_REP_CMD_FIFO_AFUL_THr = 1592,
+	NPPU_MR_CFG_MR_INT_MASK_1r = 1593,
+	NPPU_MR_CFG_MR_INT_MASK_2r = 1594,
+	NPPU_MR_CFG_MR_INT_MASK_3r = 1595,
+	NPPU_MR_CFG_MR_INT_MASK_4r = 1596,
+	NPPU_MR_CFG_MR_STATES_1r = 1597,
+	NPPU_MR_CFG_MR_STATES_2r = 1598,
+	NPPU_MR_CFG_MR_STATES_3r = 1599,
+	NPPU_MR_CFG_MR_STATES_4r = 1600,
+	NPPU_MR_CFG_MR_STATES_5r = 1601,
+	NPPU_MR_CFG_MR_STATES_6r = 1602,
+	NPPU_MR_CFG_MR_STATES_7r = 1603,
+	NPPU_MR_CFG_MR_STATES_8r = 1604,
+	NPPU_MR_CFG_MR_SOP_IN_CNTr = 1605,
+	NPPU_MR_CFG_MR_EOP_IN_CNTr = 1606,
+	NPPU_MR_CFG_MR_SOP_OUT_CNTr = 1607,
+	NPPU_MR_CFG_MR_EOP_OUT_CNTr = 1608,
+	NPPU_MR_CFG_MR_COS0_IN_CNTr = 1609,
+	NPPU_MR_CFG_MR_COS1_IN_CNTr = 1610,
+	NPPU_MR_CFG_MR_COS2_IN_CNTr = 1611,
+	NPPU_MR_CFG_MR_COS3_IN_CNTr = 1612,
+	NPPU_MR_CFG_MR_COS0_OUT_CNTr = 1613,
+	NPPU_MR_CFG_MR_COS1_OUT_CNTr = 1614,
+	NPPU_MR_CFG_MR_COS2_OUT_CNTr = 1615,
+	NPPU_MR_CFG_MR_COS3_OUT_CNTr = 1616,
+	NPPU_MR_CFG_MR_ERR_IN_CNTr = 1617,
+	NPPU_MR_CFG_MR_COS0_SOP_IN_CNTr = 1618,
+	NPPU_MR_CFG_MR_COS0_EOP_IN_CNTr = 1619,
+	NPPU_MR_CFG_MR_COS1_SOP_IN_CNTr = 1620,
+	NPPU_MR_CFG_MR_COS1_EOP_IN_CNTr = 1621,
+	NPPU_MR_CFG_MR_COS2_SOP_IN_CNTr = 1622,
+	NPPU_MR_CFG_MR_COS2_EOP_IN_CNTr = 1623,
+	NPPU_MR_CFG_MR_COS3_SOP_IN_CNTr = 1624,
+	NPPU_MR_CFG_MR_COS3_EOP_IN_CNTr = 1625,
+	NPPU_MR_CFG_MR_COS0_IN_ERR_CNTr = 1626,
+	NPPU_MR_CFG_MR_COS1_IN_ERR_CNTr = 1627,
+	NPPU_MR_CFG_MR_COS2_IN_ERR_CNTr = 1628,
+	NPPU_MR_CFG_MR_COS3_IN_ERR_CNTr = 1629,
+	NPPU_MR_CFG_MR_COS0_SOP_OUT_CNTr = 1630,
+	NPPU_MR_CFG_MR_COS0_EOP_OUT_CNTr = 1631,
+	NPPU_MR_CFG_MR_COS1_SOP_OUT_CNTr = 1632,
+	NPPU_MR_CFG_MR_COS1_EOP_OUT_CNTr = 1633,
+	NPPU_MR_CFG_MR_COS2_SOP_OUT_CNTr = 1634,
+	NPPU_MR_CFG_MR_COS2_EOP_OUT_CNTr = 1635,
+	NPPU_MR_CFG_MR_COS3_SOP_OUT_CNTr = 1636,
+	NPPU_MR_CFG_MR_COS3_EOP_OUT_CNTr = 1637,
+	NPPU_MR_CFG_MR_MLT_UNVLD_CNTr = 1638,
+	NPPU_MR_CFG_MR_SOP_EOP_MATCH_CFGr = 1639,
+	NPPU_MR_CFG_MR_MLT_UNVLD_MGIDr = 1640,
+	NPPU_PKTRX_CFG_ISCH_FIFO_TH_1r = 1641,
+	NPPU_PKTRX_CFG_ISCH_FIFO_TH_2r = 1642,
+	NPPU_PKTRX_CFG_ISCH_FIFO_TH_3r = 1643,
+	NPPU_PKTRX_CFG_ISCH_FIFO_TH_4r = 1644,
+	NPPU_PKTRX_CFG_ISCH_CFG_0r = 1645,
+	NPPU_PKTRX_CFG_HDU_EX_TPID_0r = 1646,
+	NPPU_PKTRX_CFG_HDU_EX_TPID_1r = 1647,
+	NPPU_PKTRX_CFG_HDU_INT_TPID_0r = 1648,
+	NPPU_PKTRX_CFG_HDU_INT_TPID_1r = 1649,
+	NPPU_PKTRX_CFG_HDU_HDLC_0r = 1650,
+	NPPU_PKTRX_CFG_HDU_HDLC_1r = 1651,
+	NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_0r = 1652,
+	NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_1r = 1653,
+	NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_2r = 1654,
+	NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_3r = 1655,
+	NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_0r = 1656,
+	NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_1r = 1657,
+	NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_2r = 1658,
+	NPPU_PKTRX_CFG_SLOT_NO_CFGr = 1659,
+	NPPU_PKTRX_CFG_PKTRX_INT_EN_0r = 1660,
+	NPPU_PKTRX_CFG_PKTRX_INT_EN_1r = 1661,
+	NPPU_PKTRX_CFG_PKTRX_INT_MASK_0r = 1662,
+	NPPU_PKTRX_CFG_PKTRX_INT_MASK_1r = 1663,
+	NPPU_PKTRX_CFG_PKTRX_INT_STATUSr = 1664,
+	NPPU_PKTRX_CFG_PKTRX_PORT_RDY0r = 1665,
+	NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY0r = 1666,
+	NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY1r = 1667,
+	NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY2r = 1668,
+	NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY3r = 1669,
+	NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY4r = 1670,
+	NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY5r = 1671,
+	NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY6r = 1672,
+	NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODEr = 1673,
+	NPPU_IDMA_CFG_INT_RAM_ENr = 1674,
+	NPPU_IDMA_CFG_INT_RAM_MASKr = 1675,
+	NPPU_IDMA_CFG_INT_RAM_STATUSr = 1676,
+	NPPU_IDMA_CFG_SUBSYS_INT_MASK_FLAGr = 1677,
+	NPPU_IDMA_CFG_SUBSYS_INT_UNMASK_FLAGr = 1678,
+	NPPU_IDMA_CFG_DEBUG_CNT_RDCLR_MODEr = 1679,
+	NPPU_PBU_CFG_INT_RAM_EN0r = 1680,
+	NPPU_PBU_CFG_INT_RAM_MASK0r = 1681,
+	NPPU_PBU_CFG_INT_RAM_STATUS0r = 1682,
+	NPPU_PBU_CFG_INT_FIFO_EN0r = 1683,
+	NPPU_PBU_CFG_INT_FIFO_EN1r = 1684,
+	NPPU_PBU_CFG_INT_FIFO_MASK0r = 1685,
+	NPPU_PBU_CFG_INT_FIFO_MASK1r = 1686,
+	NPPU_PBU_CFG_INT_FIFO_STATUS0r = 1687,
+	NPPU_PBU_CFG_INT_FIFO_STATUS1r = 1688,
+	NPPU_PBU_CFG_SUBSYS_INT_MASK_FLAGr = 1689,
+	NPPU_PBU_CFG_SUBSYS_INT_UNMASK_FLAGr = 1690,
+	NPPU_PBU_CFG_SA_IP_ENr = 1691,
+	NPPU_PBU_CFG_DEBUG_CNT_RDCLR_MODEr = 1692,
+	NPPU_PBU_CFG_FPTR_FIFO_AFUL_ASSERT_CFGr = 1693,
+	NPPU_PBU_CFG_FPTR_FIFO_AFUL_NEGATE_CFGr = 1694,
+	NPPU_PBU_CFG_PF_FIFO_AFUL_ASSERT_CFGr = 1695,
+	NPPU_PBU_CFG_PF_FIFO_AFUL_NEGATE_CFGr = 1696,
+	NPPU_PBU_CFG_PF_FIFO_AEPT_ASSERT_CFGr = 1697,
+	NPPU_PBU_CFG_PF_FIFO_AEPT_NEGATE_CFGr = 1698,
+	NPPU_PBU_CFG_WB_AFUL_ASSERT_CFGr = 1699,
+	NPPU_PBU_CFG_WB_AFUL_NEGATE_CFGr = 1700,
+	NPPU_PBU_CFG_SE_KEY_AFUL_ASSERT_CFGr = 1701,
+	NPPU_PBU_CFG_IFBRD_SE_AFUL_ASSERT_CFGr = 1702,
+	NPPU_PBU_CFG_IFBRD_SE_AFUL_NEGATE_CFGr = 1703,
+	NPPU_PBU_CFG_IFBRD_ODMA_AFUL_ASSERT_CFGr = 1704,
+	NPPU_PBU_CFG_IFBRD_ODMA_AFUL_NEGATE_CFGr = 1705,
+	NPPU_PBU_CFG_IFBRD_PPU_AFUL_ASSERT_CFGr = 1706,
+	NPPU_PBU_CFG_IFBRD_PPU_AFUL_NEGATE_CFGr = 1707,
+	NPPU_PBU_CFG_MC_LOGIC_AFUL_ASSERT_CFGr = 1708,
+	NPPU_PBU_CFG_MC_LOGIC_AFUL_NEGATE_CFGr = 1709,
+	NPPU_PBU_CFG_MC_LOGIC_DIFFr = 1710,
+	NPPU_PBU_CFG_CFG_PEAK_PORT_CNT_CLRr = 1711,
+	NPPU_PBU_CFG_ALL_FTM_CRDT_THr = 1712,
+	NPPU_PBU_CFG_ALL_FTM_LINK_TH_01r = 1713,
+	NPPU_PBU_CFG_ALL_FTM_LINK_TH_23r = 1714,
+	NPPU_PBU_CFG_ALL_FTM_LINK_TH_45r = 1715,
+	NPPU_PBU_CFG_ALL_FTM_LINK_TH_6r = 1716,
+	NPPU_PBU_CFG_ALL_FTM_TOTAL_CONGEST_THr = 1717,
+	NPPU_PBU_CFG_CFG_CRDT_MODEr = 1718,
+	NPPU_PBU_CFG_CFG_PFC_RDY_HIGH_TIMEr = 1719,
+	NPPU_PBU_CFG_CFG_PFC_RDY_LOW_TIMEr = 1720,
+	NPPU_PBU_STAT_PBU_FC_RDYr = 1721,
+	NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY0r = 1722,
+	NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY1r = 1723,
+	NPPU_PBU_STAT_PBU_LIF_GROUP1_RDYr = 1724,
+	NPPU_PBU_STAT_PBU_LIF_GROUP0_PFC_RDYr = 1725,
+	NPPU_PBU_STAT_PBU_LIF_GROUP1_PFC_RDYr = 1726,
+	NPPU_PBU_STAT_PBU_SA_PORT_RDY_0_31r = 1727,
+	NPPU_PBU_STAT_PBU_SA_PORT_RDY_32_50r = 1728,
+	NPPU_PBU_STAT_PBU_PKTRX_MR_PFC_RDYr = 1729,
+	NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_0_31r = 1730,
+	NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_32_47r = 1731,
+	NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_0_31r = 1732,
+	NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_32_47r = 1733,
+	NPPU_PBU_STAT_PBU_FTM_CRDT_SYS_INFOr = 1734,
+	NPPU_ISU_CFG_WEIGHT_NORMAL_MCr = 1735,
+	NPPU_ISU_CFG_WEIGHT_SA_MCr = 1736,
+	NPPU_ISU_CFG_WEIGHT_ETMr = 1737,
+	NPPU_ISU_CFG_WEIGHT_LP_MCr = 1738,
+	NPPU_ISU_CFG_WEIGHT_OAMr = 1739,
+	NPPU_ISU_CFG_WEIGHT_LIF_CTRL1r = 1740,
+	NPPU_ISU_CFG_WEIGHT_LIF_CTRL2r = 1741,
+	NPPU_ISU_CFG_ECC_BYPASS_READr = 1742,
+	NPPU_ISU_CFG_ISU_INT_MASKr = 1743,
+	NPPU_ISU_CFG_CFG_CRDT_CYCLEr = 1744,
+	NPPU_ISU_CFG_CFG_CRDT_VALUEr = 1745,
+	NPPU_ISU_CFG_ISU_INT_ENr = 1746,
+	NPPU_ISU_CFG_ISU_PPU_FIFO_FCr = 1747,
+	NPPU_ISU_CFG_ISU_INT_STATUSr = 1748,
+	NPPU_ISU_CFG_FD_PROG_FULL_ASSERT_CFGr = 1749,
+	NPPU_ISU_CFG_FD_PROG_FULL_NEGATE_CFGr = 1750,
+	NPPU_ISU_CFG_LP_PROG_FULL_ASSERT_CFGr = 1751,
+	NPPU_ISU_CFG_LP_PROG_FULL_NEGATE_CFGr = 1752,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT0r = 1753,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT1r = 1754,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT2r = 1755,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT3r = 1756,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT4r = 1757,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT5r = 1758,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT6r = 1759,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT7r = 1760,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT8r = 1761,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT9r = 1762,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT10r = 1763,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT11r = 1764,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT12r = 1765,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT13r = 1766,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT14r = 1767,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT15r = 1768,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT16r = 1769,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT17r = 1770,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT18r = 1771,
+	NPPU_ISU_STAT_DEBUG_CNT_DAT19r = 1772,
+	NPPU_ISU_STAT_DEBUG_CNT_CFGr = 1773,
+	NPPU_ODMA_CFG_EXSA_TDM_OFFSETr = 1774,
+	NPPU_ODMA_CFG_ECC_BYPASS_READTr = 1775,
+	NPPU_ODMA_CFG_ODMA_INT_EN_0r = 1776,
+	NPPU_ODMA_CFG_ODMA_INT_EN_1r = 1777,
+	NPPU_ODMA_CFG_ODMA_INT_EN_2r = 1778,
+	NPPU_ODMA_CFG_ODMA_INT_EN_3r = 1779,
+	NPPU_ODMA_CFG_ODMA_INT_MASK_0r = 1780,
+	NPPU_ODMA_CFG_ODMA_INT_MASK_1r = 1781,
+	NPPU_ODMA_CFG_ODMA_INT_MASK_2r = 1782,
+	NPPU_ODMA_CFG_ODMA_INT_MASK_3r = 1783,
+	NPPU_ODMA_CFG_ODMA_INT_STATUS_0r = 1784,
+	NPPU_ODMA_CFG_ODMA_INT_STATUS_1r = 1785,
+	NPPU_ODMA_CFG_ODMA_INT_STATUS_2r = 1786,
+	NPPU_ODMA_CFG_ODMA_INT_STATUS_3r = 1787,
+	NPPU_ODMA_CFG_SP_TDM_ERR_NOR_CFGr = 1788,
+	NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_Ar = 1789,
+	NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_Nr = 1790,
+	NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_Ar = 1791,
+	NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_Nr = 1792,
+	NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_Ar = 1793,
+	NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_Nr = 1794,
+	NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_Ar = 1795,
+	NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_Nr = 1796,
+	NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_Ar = 1797,
+	NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_Nr = 1798,
+	NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_Ar = 1799,
+	NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_Nr = 1800,
+	NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_Ar = 1801,
+	NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_Nr = 1802,
+	NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_Ar = 1803,
+	NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_Nr = 1804,
+	NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_Ar = 1805,
+	NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_Nr = 1806,
+	NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_Ar = 1807,
+	NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_Nr = 1808,
+	NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_Ar = 1809,
+	NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_Nr = 1810,
+	NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_Ar = 1811,
+	NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_Nr = 1812,
+	NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_Ar = 1813,
+	NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_Nr = 1814,
+	NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_Ar = 1815,
+	NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_Nr = 1816,
+	NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_Ar = 1817,
+	NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_Nr = 1818,
+	NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_Ar = 1819,
+	NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_Nr = 1820,
+	NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_Ar = 1821,
+	NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_Nr = 1822,
+	NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_Ar = 1823,
+	NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_Nr = 1824,
+	NPPU_ODMA_CFG_PP_PROG_FULL_CFG_Ar = 1825,
+	NPPU_ODMA_CFG_PP_PROG_FULL_CFG_Nr = 1826,
+	NPPU_ODMA_CFG_TM_WEIGHTr = 1827,
+	NPPU_ODMA_CFG_PP_WEIGHTr = 1828,
+	NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_Ar = 1829,
+	NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_Nr = 1830,
+	NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_Ar = 1831,
+	NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_Nr = 1832,
+	NPPU_ODMA_CFG_INT_OR_PONr = 1833,
+	NPPU_ODMA_CFG_QUEMNG_CNT_IN_ERR_CNTr = 1834,
+	NPPU_ODMA_CFG_LIF0_PORT_EOP_CNTr = 1835,
+	NPPU_ODMA_CFG_LIF1_PORT_EOP_CNTr = 1836,
+	NPPU_ODMA_CFG_LIFC_PORT0_EOP_CNTr = 1837,
+	NPPU_ODMA_CFG_LIFC_PORT1_EOP_CNTr = 1838,
+	NPPU_ODMA_CFG_FPTR_FIFO_PROG_EPT_CFG_Nr = 1839,
+	NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_Ar = 1840,
+	NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_Nr = 1841,
+	NPPU_OAM_CFG_IND_ACCESS_DONEr = 1842,
+	NPPU_OAM_CFG_IND_ACCESS_COMMANDr = 1843,
+	NPPU_OAM_CFG_IND_DAT0r = 1844,
+	NPPU_OAM_CFG_IND_DAT1r = 1845,
+	NPPU_OAM_CFG_IND_DAT2r = 1846,
+	NPPU_OAM_CFG_IND_DAT3r = 1847,
+	NPPU_OAM_CFG_OAM_TX_MAIN_ENr = 1848,
+	NPPU_OAM_CFG_TX_TOTAL_NUMr = 1849,
+	NPPU_OAM_CFG_OAM_CHK_MAIN_ENr = 1850,
+	NPPU_OAM_CFG_CHK_TOTAL_NUM0r = 1851,
+	NPPU_OAM_CFG_MA_CHK_MAIN_ENr = 1852,
+	NPPU_OAM_CFG_CHK_TOTAL_NUM1r = 1853,
+	NPPU_OAM_CFG_TX_STAT_ENr = 1854,
+	NPPU_OAM_CFG_REC_STAT_ENr = 1855,
+	NPPU_OAM_CFG_STAT_OAM_RDY_MASKr = 1856,
+	NPPU_OAM_CFG_SESSION_GRADING0r = 1857,
+	NPPU_OAM_CFG_SESSION_GRADING1r = 1858,
+	NPPU_OAM_CFG_SESSION_GRADING2r = 1859,
+	NPPU_OAM_CFG_SESSION_GRADING3r = 1860,
+	NPPU_OAM_CFG_BFD_CHK_HADDRr = 1861,
+	NPPU_OAM_CFG_ETHCCM_CHK_HADDRr = 1862,
+	NPPU_OAM_CFG_TPBFD_CHK_HADDRr = 1863,
+	NPPU_OAM_CFG_TPOAM_CCM_CHK_HADDRr = 1864,
+	NPPU_OAM_CFG_BFD_TX_HADDRr = 1865,
+	NPPU_OAM_CFG_ETHCCM_TX_HADDRr = 1866,
+	NPPU_OAM_CFG_TPBFD_TX_HADDRr = 1867,
+	NPPU_OAM_CFG_TPOAM_CCM_TX_HADDRr = 1868,
+	NPPU_OAM_CFG_ETHCCM_MA_CHK_HADDRr = 1869,
+	NPPU_OAM_CFG_TPCCM_MA_CHK_HADDRr = 1870,
+	NPPU_OAM_CFG_GROUPNUM_RAM_CLRr = 1871,
+	NPPU_OAM_CFG_INDEX_RAM0_CLRr = 1872,
+	NPPU_OAM_CFG_INDEX_RAM1_CLRr = 1873,
+	NPPU_OAM_CFG_RMEP_RAM_CLRr = 1874,
+	NPPU_OAM_CFG_MA_RAM_CLRr = 1875,
+	NPPU_OAM_CFG_RAM_INIT_DONEr = 1876,
+	NPPU_OAM_CFG_REC_BFD_DEBUG_ENr = 1877,
+	NPPU_OAM_CFG_OAM_SESSION_INTr = 1878,
+	NPPU_OAM_CFG_PON_INTr = 1879,
+	NPPU_OAM_CFG_OAM_INT_CLRr = 1880,
+	NPPU_OAM_CFG_TYPE_INT_CLR0r = 1881,
+	NPPU_OAM_CFG_TYPE_INT_CLR1r = 1882,
+	NPPU_OAM_CFG_INTERRUPT_MASKr = 1883,
+	NPPU_OAM_CFG_INT0_INDEXr = 1884,
+	NPPU_OAM_CFG_INT1_INDEXr = 1885,
+	NPPU_OAM_CFG_INT0_INDEX_REGIONr = 1886,
+	NPPU_OAM_CFG_INT1_INDEX_REGIONr = 1887,
+	NPPU_OAM_CFG_BDIINFO_FWFT_FIFO_THr = 1888,
+	NPPU_OAM_CFG_RECSEC_FWFT_FIFO_THr = 1889,
+	NPPU_OAM_CFG_TIMING_CHK_INFO0_FWFT_FIFO_THr = 1890,
+	NPPU_OAM_CFG_RECMA_FWFT_FIFO_THr = 1891,
+	NPPU_OAM_CFG_TIMING_CHK_INFO1_FWFT_FIFO_THr = 1892,
+	NPPU_OAM_CFG_OAM_TXINST_FIFO_THr = 1893,
+	NPPU_OAM_CFG_OAM_RDINFO_FWFT_FIFO_THr = 1894,
+	NPPU_OAM_CFG_LM_CNT_FWFT_FIFO_THr = 1895,
+	NPPU_OAM_CFG_OAM_PKT_FIFO_THr = 1896,
+	NPPU_OAM_CFG_RECLM_STAT_FIFO_THr = 1897,
+	NPPU_OAM_CFG_TXLM_STAT_FIFO_THr = 1898,
+	NPPU_OAM_CFG_OAM_CHK_FWFT_FIFO_THr = 1899,
+	NPPU_OAM_CFG_TXOAM_STAT_FIFO_THr = 1900,
+	NPPU_OAM_CFG_RECOAM_STAT_FIFO_THr = 1901,
+	NPPU_OAM_CFG_TXPKT_DATA_FWFT_FIFO_THr = 1902,
+	NPPU_OAM_CFG_TSTPKT_FWFT_FIFO_THr = 1903,
+	NPPU_OAM_CFG_TST_TXINST_FWFT_FIFO_THr = 1904,
+	NPPU_OAM_CFG_TSTRX_MAIN_ENr = 1905,
+	NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL2r = 1906,
+	NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL1r = 1907,
+	NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL0r = 1908,
+	NPPU_OAM_CFG_TSTRX_CFG_PARAr = 1909,
+	NPPU_OAM_CFG_FIFO_STATUS_INT_EN_0r = 1910,
+	NPPU_OAM_CFG_FIFO_STATUS_INT_EN_1r = 1911,
+	NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_0r = 1912,
+	NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_1r = 1913,
+	NPPU_OAM_CFG_FIFO_STATUS_INT_STATUSr = 1914,
+	NPPU_OAM_CFG_MAIN_FREQUENCYr = 1915,
+	NPPU_OAM_CFG_OAM_CFG_TYPEr = 1916,
+	NPPU_OAM_CFG_FST_SWCH_ETH_HEAD0r = 1917,
+	NPPU_OAM_CFG_FST_SWCH_ETH_HEAD1r = 1918,
+	NPPU_OAM_CFG_FST_SWCH_ETH_HEAD2r = 1919,
+	NPPU_OAM_CFG_FST_SWCH_ETH_HEAD3r = 1920,
+	NPPU_OAM_CFG_OAM_FS_TXINST_FIFO_THr = 1921,
+	NPPU_OAM_CFG_OAM_MA_FS_TXINST_FIFO_THr = 1922,
+	NPPU_OAM_CFG_PON_INT_RAM_CLRr = 1923,
+	NPPU_OAM_CFG_PON_P_INT_INDEXr = 1924,
+	NPPU_OAM_CFG_PON_PROTECT_PKT_FIFO_THr = 1925,
+	NPPU_OAM_CFG_PON_LASER_OFF_ENr = 1926,
+	NPPU_OAM_CFG_PON_PRTCT_PKT_TX_ENr = 1927,
+	NPPU_OAM_CFG_CFG_PON_MASTERr = 1928,
+	NPPU_OAM_CFG_LEVEL_MODEr = 1929,
+	NPPU_OAM_CFG_INTERRUPT_ENr = 1930,
+	NPPU_OAM_CFG_PON_LASER_ON_ENr = 1931,
+	NPPU_OAM_CFG_TI_PON_SDr = 1932,
+	NPPU_OAM_CFG_TI_PON_LOSr = 1933,
+	NPPU_OAM_CFG_IND_DAT4r = 1934,
+	NPPU_OAM_CFG_IND_DAT5r = 1935,
+	NPPU_OAM_CFG_IND_DAT6r = 1936,
+	NPPU_OAM_CFG_IND_DAT7r = 1937,
+	NPPU_OAM_CFG_IND_DAT8r = 1938,
+	NPPU_OAM_CFG_IND_DAT9r = 1939,
+	NPPU_OAM_CFG_IND_DAT10r = 1940,
+	NPPU_OAM_CFG_IND_DAT11r = 1941,
+	NPPU_OAM_CFG_IND_DAT12r = 1942,
+	NPPU_OAM_CFG_IND_DAT13r = 1943,
+	NPPU_OAM_CFG_IND_DAT14r = 1944,
+	NPPU_OAM_CFG_IND_DAT15r = 1945,
+	NPPU_OAM_CFG_OAM_2544_PKT_FIFO_THr = 1946,
+	NPPU_OAM_CFG_TXINFO_RAM_CLRr = 1947,
+	NPPU_OAM_CFG_TXINFO_RAM_INIT_DONEr = 1948,
+	NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS40r = 1949,
+	NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS41r = 1950,
+	NPPU_OAM_CFG_OAM_2544_FUN_ENr = 1951,
+	NPPU_OAM_CFG_OAM_2544_STAT_CLRr = 1952,
+	NPPU_OAM_CFG_TXDIS_DEFAULTr = 1953,
+	NPPU_OAM_CFG_TXDIS_DEFAULT_ENr = 1954,
+	NPPU_OAM_CFG_TPBFD_FIRSTCHK_THr = 1955,
+	NPPU_OAM_CFG_ETHCCM_FIRSTCHK_THr = 1956,
+	NPPU_OAM_CFG_TPCCM_FIRSTCHK_THr = 1957,
+	NPPU_OAM_STAT_TXSTAT_REQ_CNTr = 1958,
+	NPPU_OAM_STAT_CHKSTAT_REQ_CNTr = 1959,
+	NPPU_OAM_STAT_STAT_OAM_FC_CNTr = 1960,
+	NPPU_OAM_STAT_BFDSEQ_REQ_CNTr = 1961,
+	NPPU_OAM_STAT_LMCNT_REQ_CNTr = 1962,
+	NPPU_OAM_STAT_STAT_OAM_LM_RSP_CNTr = 1963,
+	NPPU_OAM_STAT_STAT_OAM_LM_FC_CNTr = 1964,
+	NPPU_OAM_STAT_SE_REQ_CNTr = 1965,
+	NPPU_OAM_STAT_SE_RSP_CNTr = 1966,
+	NPPU_OAM_STAT_SE_OAM_FC_CNTr = 1967,
+	NPPU_OAM_STAT_OAM_SE_FC_CNTr = 1968,
+	NPPU_OAM_STAT_OAM_PKTRX_SOP_CNTr = 1969,
+	NPPU_OAM_STAT_OAM_PKTRX_EOP_CNTr = 1970,
+	NPPU_OAM_STAT_PKTRX_OAM_FC_CNTr = 1971,
+	NPPU_OAM_STAT_PKTRX_OAM_TST_FC_CNTr = 1972,
+	NPPU_OAM_STAT_ODMA_OAM_SOP_CNTr = 1973,
+	NPPU_OAM_STAT_ODMA_OAM_EOP_CNTr = 1974,
+	NPPU_OAM_STAT_OAM_ODMA_FC_CNTr = 1975,
+	NPPU_OAM_STAT_REC_MA_PKT_ILLEGAL_CNTr = 1976,
+	NPPU_OAM_STAT_REC_RMEP_PKT_ILLEGAL_CNTr = 1977,
+	NPPU_OAM_STAT_REC_ETH_AIS_PKT_CNTr = 1978,
+	NPPU_OAM_STAT_REC_TP_AIS_PKT_CNTr = 1979,
+	NPPU_OAM_STAT_REC_TP_CSF_PKT_CNTr = 1980,
+	NPPU_OAM_STAT_REC_ETH_LEVEL_DEFECT_CNTr = 1981,
+	NPPU_OAM_STAT_REC_ETH_MEGID_DEFECT_CNTr = 1982,
+	NPPU_OAM_STAT_REC_ETH_MEPID_DEFECT_CNTr = 1983,
+	NPPU_OAM_STAT_REC_ETH_INTERVAL_DEFECT_CNTr = 1984,
+	NPPU_OAM_STAT_REC_SESS_UNENABLE_CNTr = 1985,
+	NPPU_OAM_STAT_OAM_2544_RD_PKT_CNTr = 1986,
+	NPPU_OAM_STAT_DEBUG_CNT_CLRr = 1987,
+	NPPU_OAM_STAT_OAM_PKTRX_CATCH_DATAr = 1988,
+	NPPU_OAM_STAT_ODMA_OAM_CATCH_DATAr = 1989,
+	NPPU_OAM_STAT_TST_SESSION_TX_CNTr = 1990,
+	NPPU_OAM_STAT_TST_SESSION_RX_CNTr = 1991,
+	NPPU_OAM_STAT_TSTRX_LOST_CNTr = 1992,
+	NPPU_OAM_STAT_BFDSEQ_WR_CNTr = 1993,
+	NPPU_OAM_STAT_BFDTIME_WR_CNTr = 1994,
+	NPPU_OAM_STAT_LMCNT_WR_CNTr = 1995,
+	NPPU_OAM_STAT_OAM_FS_PKT_CNTr = 1996,
+	NPPU_OAM_STAT_OAM_MA_FS_PKT_CNTr = 1997,
+	NPPU_OAM_STAT_REC_TP_LEVEL_DEFECT_CNTr = 1998,
+	NPPU_OAM_STAT_REC_TP_MEGID_DEFECT_CNTr = 1999,
+	NPPU_OAM_STAT_REC_TP_MEPID_DEFECT_CNTr = 2000,
+	NPPU_OAM_STAT_REC_TP_INTERVAL_DEFECT_CNTr = 2001,
+	NPPU_OAM_STAT_RD_REG_CLEAR_MODEr = 2002,
+	NPPU_OAM_STAT_RD_DATA_REG_CLEAR_MODEr = 2003,
+	NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM_0r = 2004,
+	NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM1r = 2005,
+	NPPU_OAM_CFG_INDIR_TST_PKT_TX_PARA_RAMr = 2006,
+	NPPU_OAM_CFG_INDIR_GROUPNUMRAMr = 2007,
+	NPPU_OAM_CFG_INDIR_OAM_TX_TBL_RAMr = 2008,
+	NPPU_OAM_CFG_INDIR_OAM_CHK_TBL_RAMr = 2009,
+	NPPU_OAM_CFG_INDIR_OAM_MA_CHK_TBL_RAMr = 2010,
+	NPPU_OAM_CFG_INDIR_OAM_2544_TX_RAMr = 2011,
+	PPU_PPU_INTERRUPT_EN_Rr = 2012,
+	PPU_PPU_MEC_HOST_INTERRUPTr = 2013,
+	PPU_PPU_DBG_RTL_DATEr = 2014,
+	PPU_PPU_DUP_START_NUM_CFGr = 2015,
+	PPU_PPU_DEBUG_DATA_WRITE_COMPLETEr = 2016,
+	PPU_PPU_UC_MC_WRR_CFGr = 2017,
+	PPU_PPU_DEBUG_PKT_SEND_ENr = 2018,
+	PPU_PPU_DUP_TBL_IND_ACCESS_DONEr = 2019,
+	PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_MASKr = 2020,
+	PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_MASKr = 2021,
+	PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_MASKr = 2022,
+	PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_MASKr = 2023,
+	PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_MASKr = 2024,
+	PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_MASKr = 2025,
+	PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_MASKr = 2026,
+	PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Lr = 2027,
+	PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Mr = 2028,
+	PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Hr = 2029,
+	PPU_PPU_PPU_RAM_CHECK_ERR_MASKr = 2030,
+	PPU_PPU_INSTRMEM_FIFO_INTERRUPT_MASKr = 2031,
+	PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_STAr = 2032,
+	PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_STAr = 2033,
+	PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_STAr = 2034,
+	PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_STAr = 2035,
+	PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_STAr = 2036,
+	PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_STAr = 2037,
+	PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_STAr = 2038,
+	PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Lr = 2039,
+	PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Mr = 2040,
+	PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Hr = 2041,
+	PPU_PPU_INSTRMEM_FIFO_INTERRUPT_STAr = 2042,
+	PPU_PPU_PPU_RAM_CHECK_ECC_ERR_FLAG_1r = 2043,
+	PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_FLAGr = 2044,
+	PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_FLAGr = 2045,
+	PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_FLAGr = 2046,
+	PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_FLAGr = 2047,
+	PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_FLAGr = 2048,
+	PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_FLAGr = 2049,
+	PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_FLAGr = 2050,
+	PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Lr = 2051,
+	PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Mr = 2052,
+	PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Hr = 2053,
+	PPU_PPU_INSTRMEM_FIFO_INTERRUPT_FLAGr = 2054,
+	PPU_PPU_INSTRMEM_RAM_INT_OUTr = 2055,
+	PPU_PPU_INSTRMEM_RAM_INT_MASKr = 2056,
+	PPU_PPU_INSTRMEM_RAM_INT_STATr = 2057,
+	PPU_PPU_INSTRMEM_RAM_INT_FLAGr = 2058,
+	PPU_PPU_PPU_COUNT_CFGr = 2059,
+	PPU_PPU_PPU_STATICS_CFGr = 2060,
+	PPU_PPU_PPU_STATICS_WB_CFGr = 2061,
+	PPU_PPU_WR_TABLE_SELF_RSP_EN_CFGr = 2062,
+	PPU_PPU_PPU_RANDOM_ARBITER_8TO1_CFGr = 2063,
+	PPU_PPU_PPU_REORDER_BYPASS_FLOW_NUM_CFGr = 2064,
+	PPU_PPU_COS_METER_CFG_Hr = 2065,
+	PPU_PPU_COS_METER_CFG_Lr = 2066,
+	PPU_PPU_INSTRMEM_RDYr = 2067,
+	PPU_PPU_INSTRMEM_ADDRr = 2068,
+	PPU_PPU_INSTRMEM_IND_ACCESS_DONEr = 2069,
+	PPU_PPU_INSTRMEM_INSTR0_DATA_Lr = 2070,
+	PPU_PPU_INSTRMEM_INSTR0_DATA_Hr = 2071,
+	PPU_PPU_INSTRMEM_INSTR1_DATA_Lr = 2072,
+	PPU_PPU_INSTRMEM_INSTR1_DATA_Hr = 2073,
+	PPU_PPU_INSTRMEM_INSTR2_DATA_Lr = 2074,
+	PPU_PPU_INSTRMEM_INSTR2_DATA_Hr = 2075,
+	PPU_PPU_INSTRMEM_INSTR3_DATA_Lr = 2076,
+	PPU_PPU_INSTRMEM_INSTR3_DATA_Hr = 2077,
+	PPU_PPU_INSTRMEM_READ_INSTR0_DATA_Lr = 2078,
+	PPU_PPU_INSTRMEM_READ_INSTR0_DATA_Hr = 2079,
+	PPU_PPU_INSTRMEM_READ_INSTR1_DATA_Lr = 2080,
+	PPU_PPU_INSTRMEM_READ_INSTR1_DATA_Hr = 2081,
+	PPU_PPU_INSTRMEM_READ_INSTR2_DATA_Lr = 2082,
+	PPU_PPU_INSTRMEM_READ_INSTR2_DATA_Hr = 2083,
+	PPU_PPU_INSTRMEM_READ_INSTR3_DATA_Lr = 2084,
+	PPU_PPU_INSTRMEM_READ_INSTR3_DATA_Hr = 2085,
+	PPU_PPU_SE_PPU_MC_SRH_FC_CNT_Hr = 2086,
+	PPU_PPU_SE_PPU_MC_SRH_FC_CNT_Lr = 2087,
+	PPU_PPU_PPU_SE_MC_SRH_FC_CNT_Hr = 2088,
+	PPU_PPU_PPU_SE_MC_SRH_FC_CNT_Lr = 2089,
+	PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_Hr = 2090,
+	PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_Lr = 2091,
+	PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_Hr = 2092,
+	PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_Lr = 2093,
+	PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_Hr = 2094,
+	PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_Lr = 2095,
+	PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_Hr = 2096,
+	PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_Lr = 2097,
+	PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_Hr = 2098,
+	PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_Lr = 2099,
+	PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_Hr = 2100,
+	PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_Lr = 2101,
+	PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_Hr = 2102,
+	PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_Lr = 2103,
+	PPU_PPU_PBU_PPU_WB_FC_CNT_Hr = 2104,
+	PPU_PPU_PBU_PPU_WB_FC_CNT_Lr = 2105,
+	PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_Hr = 2106,
+	PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_Lr = 2107,
+	PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_Hr = 2108,
+	PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_Lr = 2109,
+	PPU_PPU_ODMA_PPU_PARA_FC_CNT_Hr = 2110,
+	PPU_PPU_ODMA_PPU_PARA_FC_CNT_Lr = 2111,
+	PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_Hr = 2112,
+	PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_Lr = 2113,
+	PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_Hr = 2114,
+	PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_Lr = 2115,
+	PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_Hr = 2116,
+	PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_Lr = 2117,
+	PPU_PPU_PPU_PKTRX_UC_FC_CNT_Hr = 2118,
+	PPU_PPU_PPU_PKTRX_UC_FC_CNT_Lr = 2119,
+	PPU_PPU_PPU_PKTRX_MC_FC_CNT_Hr = 2120,
+	PPU_PPU_PPU_PKTRX_MC_FC_CNT_Lr = 2121,
+	PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_Hr = 2122,
+	PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_Lr = 2123,
+	PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_Hr = 2124,
+	PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_Lr = 2125,
+	PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_Hr = 2126,
+	PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_Lr = 2127,
+	PPU_PPU_PPU_PBU_WB_VLD_CNT_Hr = 2128,
+	PPU_PPU_PPU_PBU_WB_VLD_CNT_Lr = 2129,
+	PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_Hr = 2130,
+	PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_Lr = 2131,
+	PPU_PPU_PPU_ODMA_PARA_VLD_CNT_Hr = 2132,
+	PPU_PPU_PPU_ODMA_PARA_VLD_CNT_Lr = 2133,
+	PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_Hr = 2134,
+	PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_Lr = 2135,
+	PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_Hr = 2136,
+	PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_Lr = 2137,
+	PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_Hr = 2138,
+	PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_Lr = 2139,
+	PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_Hr = 2140,
+	PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_Lr = 2141,
+	PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_Hr = 2142,
+	PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_Lr = 2143,
+	PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_Hr = 2144,
+	PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_Lr = 2145,
+	PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_Hr = 2146,
+	PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_Lr = 2147,
+	PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_Hr = 2148,
+	PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_Lr = 2149,
+	PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_Hr = 2150,
+	PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_Lr = 2151,
+	PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_Hr = 2152,
+	PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_Lr = 2153,
+	PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_Hr = 2154,
+	PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_Lr = 2155,
+	PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_Hr = 2156,
+	PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_Lr = 2157,
+	PPU_PPU_STATICS_PPU_WB_VLD_CNT_Hr = 2158,
+	PPU_PPU_STATICS_PPU_WB_VLD_CNT_Lr = 2159,
+	PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_Hr = 2160,
+	PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_Lr = 2161,
+	PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_Hr = 2162,
+	PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_Lr = 2163,
+	PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_Hr = 2164,
+	PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_Lr = 2165,
+	PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_Hr = 2166,
+	PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_Lr = 2167,
+	PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_Hr = 2168,
+	PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_Lr = 2169,
+	PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_Hr = 2170,
+	PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_Lr = 2171,
+	PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_Hr = 2172,
+	PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_Lr = 2173,
+	PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_Hr = 2174,
+	PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_Lr = 2175,
+	PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_Hr = 2176,
+	PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_Lr = 2177,
+	PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_Hr = 2178,
+	PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_Lr = 2179,
+	PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_Hr = 2180,
+	PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_Lr = 2181,
+	PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_Hr = 2182,
+	PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_Lr = 2183,
+	PPU_PPU_CAR_GREEN_PKT_VLD_CNT_Hr = 2184,
+	PPU_PPU_CAR_GREEN_PKT_VLD_CNT_Lr = 2185,
+	PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_Hr = 2186,
+	PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_Lr = 2187,
+	PPU_PPU_CAR_RED_PKT_VLD_CNT_Hr = 2188,
+	PPU_PPU_CAR_RED_PKT_VLD_CNT_Lr = 2189,
+	PPU_PPU_CAR_DROP_PKT_VLD_CNT_Hr = 2190,
+	PPU_PPU_CAR_DROP_PKT_VLD_CNT_Lr = 2191,
+	PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_Hr = 2192,
+	PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_Lr = 2193,
+	PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_Hr = 2194,
+	PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_Lr = 2195,
+	PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_ASSERT_CFGr = 2196,
+	PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_NEGATE_CFGr = 2197,
+	PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_ASSERT_CFGr = 2198,
+	PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_NEGATE_CFGr = 2199,
+	PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_ASSERT_CFGr = 2200,
+	PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_NEGATE_CFGr = 2201,
+	PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_ASSERT_CFGr = 2202,
+	PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_NEGATE_CFGr = 2203,
+	PPU_PPU_MCCNT_FIFO_PROG_FULL_ASSERT_CFGr = 2204,
+	PPU_PPU_MCCNT_FIFO_PROG_FULL_NEGATE_CFGr = 2205,
+	PPU_PPU_MCCNT_FIFO_PROG_EMPTY_ASSERT_CFGr = 2206,
+	PPU_PPU_MCCNT_FIFO_PROG_EMPTY_NEGATE_CFGr = 2207,
+	PPU_PPU_UC_MF_FIFO_PROG_FULL_ASSERT_CFGr = 2208,
+	PPU_PPU_UC_MF_FIFO_PROG_FULL_NEGATE_CFGr = 2209,
+	PPU_PPU_UC_MF_FIFO_PROG_EMPTY_ASSERT_CFGr = 2210,
+	PPU_PPU_UC_MF_FIFO_PROG_EMPTY_NEGATE_CFGr = 2211,
+	PPU_PPU_MC_MF_FIFO_PROG_FULL_ASSERT_CFGr = 2212,
+	PPU_PPU_MC_MF_FIFO_PROG_FULL_NEGATE_CFGr = 2213,
+	PPU_PPU_MC_MF_FIFO_PROG_EMPTY_ASSERT_CFGr = 2214,
+	PPU_PPU_MC_MF_FIFO_PROG_EMPTY_NEGATE_CFGr = 2215,
+	PPU_PPU_ISU_MF_FIFO_PROG_FULL_ASSERT_CFGr = 2216,
+	PPU_PPU_ISU_MF_FIFO_PROG_FULL_NEGATE_CFGr = 2217,
+	PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_ASSERT_CFGr = 2218,
+	PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_NEGATE_CFGr = 2219,
+	PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_ASSERT_CFGr = 2220,
+	PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_NEGATE_CFGr = 2221,
+	PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_ASSERT_CFGr = 2222,
+	PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_NEGATE_CFGr = 2223,
+	PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_ASSERT_CFGr = 2224,
+	PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_NEGATE_CFGr = 2225,
+	PPU_PPU_GROUP_ID_FIFO_PROG_FULL_ASSERT_CFGr = 2226,
+	PPU_PPU_GROUP_ID_FIFO_PROG_FULL_NEGATE_CFGr = 2227,
+	PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_ASSERT_CFGr = 2228,
+	PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_NEGATE_CFGr = 2229,
+	PPU_PPU_SA_PARA_FIFO_PROG_FULL_ASSERT_CFGr = 2230,
+	PPU_PPU_SA_PARA_FIFO_PROG_FULL_NEGATE_CFGr = 2231,
+	PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr = 2232,
+	PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr = 2233,
+	PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_ASSERT_CFGr = 2234,
+	PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_NEGATE_CFGr = 2235,
+	PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr = 2236,
+	PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr = 2237,
+	PPU_PPU_DUP_PARA_FIFO_PROG_FULL_ASSERT_CFGr = 2238,
+	PPU_PPU_DUP_PARA_FIFO_PROG_FULL_NEGATE_CFGr = 2239,
+	PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr = 2240,
+	PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr = 2241,
+	PPU_PPU_PF_RSP_FIFO_PROG_FULL_ASSERT_CFGr = 2242,
+	PPU_PPU_PF_RSP_FIFO_PROG_FULL_NEGATE_CFGr = 2243,
+	PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr = 2244,
+	PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr = 2245,
+	PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_ASSERT_CFGr = 2246,
+	PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_NEGATE_CFGr = 2247,
+	PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_ASSERT_CFGr = 2248,
+	PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_NEGATE_CFGr = 2249,
+	PPU_PPU_PF_REQ_FIFO_PROG_FULL_ASSERT_CFGr = 2250,
+	PPU_PPU_PF_REQ_FIFO_PROG_FULL_NEGATE_CFGr = 2251,
+	PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_ASSERT_CFGr = 2252,
+	PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_NEGATE_CFGr = 2253,
+	PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_ASSERT_CFGr = 2254,
+	PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_NEGATE_CFGr = 2255,
+	PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_ASSERT_CFGr = 2256,
+	PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_NEGATE_CFGr = 2257,
+	PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_ASSERT_CFGr = 2258,
+	PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_NEGATE_CFGr = 2259,
+	PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_ASSERT_CFGr = 2260,
+	PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_NEGATE_CFGr = 2261,
+	PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_ASSERT_CFGr = 2262,
+	PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_NEGATE_CFGr = 2263,
+	PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_ASSERT_CFGr = 2264,
+	PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_NEGATE_CFGr = 2265,
+	PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_ASSERT_CFGr = 2266,
+	PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_NEGATE_CFGr = 2267,
+	PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr = 2268,
+	PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr = 2269,
+	PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_ASSERT_CFGr = 2270,
+	PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_NEGATE_CFGr = 2271,
+	PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr = 2272,
+	PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr = 2273,
+	PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_ASSERT_CFGr = 2274,
+	PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_NEGATE_CFGr = 2275,
+	PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr = 2276,
+	PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr = 2277,
+	PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_ASSERT_CFGr = 2278,
+	PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_NEGATE_CFGr = 2279,
+	PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr = 2280,
+	PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr = 2281,
+	PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_ASSERT_CFGr = 2282,
+	PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_NEGATE_CFGr = 2283,
+	PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_ASSERT_CFGr = 2284,
+	PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_NEGATE_CFGr = 2285,
+	PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_ASSERT_CFGr = 2286,
+	PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_NEGATE_CFGr = 2287,
+	PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr = 2288,
+	PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr = 2289,
+	PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_ASSERT_CFGr = 2290,
+	PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_NEGATE_CFGr = 2291,
+	PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr = 2292,
+	PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr = 2293,
+	PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_ASSERT_CFGr = 2294,
+	PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_NEGATE_CFGr = 2295,
+	PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr = 2296,
+	PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr = 2297,
+	PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_ASSERT_CFGr = 2298,
+	PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_NEGATE_CFGr = 2299,
+	PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr = 2300,
+	PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr = 2301,
+	PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_ASSERT_CFGr = 2302,
+	PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_NEGATE_CFGr = 2303,
+	PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr = 2304,
+	PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr = 2305,
+	PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_ASSERT_CFGr = 2306,
+	PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_NEGATE_CFGr = 2307,
+	PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_ASSERT_CFGr = 2308,
+	PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_NEGATE_CFGr = 2309,
+	PPU_PPU_PKT_DATA0r = 2310,
+	PPU_PPU_PKT_DATA1r = 2311,
+	PPU_PPU_PKT_DATA2r = 2312,
+	PPU_PPU_PKT_DATA3r = 2313,
+	PPU_PPU_PKT_DATA4r = 2314,
+	PPU_PPU_PKT_DATA5r = 2315,
+	PPU_PPU_PKT_DATA6r = 2316,
+	PPU_PPU_PKT_DATA7r = 2317,
+	PPU_PPU_PKT_DATA8r = 2318,
+	PPU_PPU_PKT_DATA9r = 2319,
+	PPU_PPU_PKT_DATA10r = 2320,
+	PPU_PPU_PKT_DATA11r = 2321,
+	PPU_PPU_PKT_DATA12r = 2322,
+	PPU_PPU_PKT_DATA13r = 2323,
+	PPU_PPU_PKT_DATA14r = 2324,
+	PPU_PPU_PKT_DATA15r = 2325,
+	PPU_PPU_PKT_DATA16r = 2326,
+	PPU_PPU_PKT_DATA17r = 2327,
+	PPU_PPU_PKT_DATA18r = 2328,
+	PPU_PPU_PKT_DATA19r = 2329,
+	PPU_PPU_PKT_DATA20r = 2330,
+	PPU_PPU_PKT_DATA21r = 2331,
+	PPU_PPU_PKT_DATA22r = 2332,
+	PPU_PPU_PKT_DATA23r = 2333,
+	PPU_PPU_PKT_DATA24r = 2334,
+	PPU_PPU_PKT_DATA25r = 2335,
+	PPU_PPU_PKT_DATA26r = 2336,
+	PPU_PPU_PKT_DATA27r = 2337,
+	PPU_PPU_PKT_DATA28r = 2338,
+	PPU_PPU_PKT_DATA29r = 2339,
+	PPU_PPU_PKT_DATA30r = 2340,
+	PPU_PPU_PKT_DATA31r = 2341,
+	PPU_PPU_PKT_DATA32r = 2342,
+	PPU_PPU_PKT_DATA33r = 2343,
+	PPU_PPU_PKT_DATA34r = 2344,
+	PPU_PPU_PKT_DATA35r = 2345,
+	PPU_PPU_PKT_DATA36r = 2346,
+	PPU_PPU_PKT_DATA37r = 2347,
+	PPU_PPU_PKT_DATA38r = 2348,
+	PPU_PPU_PKT_DATA39r = 2349,
+	PPU_PPU_PKT_DATA40r = 2350,
+	PPU_PPU_PKT_DATA41r = 2351,
+	PPU_PPU_PKT_DATA42r = 2352,
+	PPU_PPU_PKT_DATA43r = 2353,
+	PPU_PPU_PKT_DATA44r = 2354,
+	PPU_PPU_PKT_DATA45r = 2355,
+	PPU_PPU_PKT_DATA46r = 2356,
+	PPU_PPU_PKT_DATA47r = 2357,
+	PPU_PPU_PKT_DATA48r = 2358,
+	PPU_PPU_PKT_DATA49r = 2359,
+	PPU_PPU_PKT_DATA50r = 2360,
+	PPU_PPU_PKT_DATA51r = 2361,
+	PPU_PPU_PKT_DATA52r = 2362,
+	PPU_PPU_PKT_DATA53r = 2363,
+	PPU_PPU_PKT_DATA54r = 2364,
+	PPU_PPU_PKT_DATA55r = 2365,
+	PPU_PPU_PKT_DATA56r = 2366,
+	PPU_PPU_PKT_DATA57r = 2367,
+	PPU_PPU_PKT_DATA58r = 2368,
+	PPU_PPU_PKT_DATA59r = 2369,
+	PPU_PPU_PKT_DATA60r = 2370,
+	PPU_PPU_PKT_DATA61r = 2371,
+	PPU_PPU_PKT_DATA62r = 2372,
+	PPU_PPU_PKT_DATA63r = 2373,
+	PPU_PPU_PKT_DATA64r = 2374,
+	PPU_PPU_PKT_DATA65r = 2375,
+	PPU_PPU_PKT_DATA66r = 2376,
+	PPU_PPU_PKT_DATA67r = 2377,
+	PPU_PPU_PKT_DATA68r = 2378,
+	PPU_PPU_PKT_DATA69r = 2379,
+	PPU_PPU_PKT_DATA70r = 2380,
+	PPU_PPU_PKT_DATA71r = 2381,
+	PPU_PPU_PKT_DATA72r = 2382,
+	PPU_PPU_PKT_DATA73r = 2383,
+	PPU_PPU_PKT_DATA74r = 2384,
+	PPU_PPU_PKT_DATA75r = 2385,
+	PPU_PPU_PKT_DATA76r = 2386,
+	PPU_PPU_PKT_DATA77r = 2387,
+	PPU_PPU_PKT_DATA78r = 2388,
+	PPU_PPU_PKT_DATA79r = 2389,
+	PPU_PPU_PKT_DATA80r = 2390,
+	PPU_PPU_PKT_DATA81r = 2391,
+	PPU_PPU_PKT_DATA82r = 2392,
+	PPU_PPU_PKT_DATA83r = 2393,
+	PPU_PPU_PKT_DATA84r = 2394,
+	PPU_PPU_PKT_DATA85r = 2395,
+	PPU_PPU_PKT_DATA86r = 2396,
+	PPU_PPU_PKT_DATA87r = 2397,
+	PPU_PPU_PKT_DATA88r = 2398,
+	PPU_PPU_PKT_DATA89r = 2399,
+	PPU_PPU_PKT_DATA90r = 2400,
+	PPU_PPU_PKT_DATA91r = 2401,
+	PPU_PPU_PKT_DATA92r = 2402,
+	PPU_PPU_PKT_DATA93r = 2403,
+	PPU_PPU_PKT_DATA94r = 2404,
+	PPU_PPU_PKT_DATA95r = 2405,
+	PPU_PPU_PKT_DATA96r = 2406,
+	PPU_PPU_PKT_DATA97r = 2407,
+	PPU_PPU_PKT_DATA98r = 2408,
+	PPU_PPU_PKT_DATA99r = 2409,
+	PPU_PPU_PKT_DATA100r = 2410,
+	PPU_PPU_PKT_DATA101r = 2411,
+	PPU_PPU_PKT_DATA102r = 2412,
+	PPU_PPU_PKT_DATA103r = 2413,
+	PPU_PPU_PKT_DATA104r = 2414,
+	PPU_PPU_PKT_DATA105r = 2415,
+	PPU_PPU_PKT_DATA106r = 2416,
+	PPU_PPU_PKT_DATA107r = 2417,
+	PPU_PPU_PKT_DATA108r = 2418,
+	PPU_PPU_PKT_DATA109r = 2419,
+	PPU_PPU_PKT_DATA110r = 2420,
+	PPU_PPU_PKT_DATA111r = 2421,
+	PPU_PPU_PKT_DATA112r = 2422,
+	PPU_PPU_PKT_DATA113r = 2423,
+	PPU_PPU_PKT_DATA114r = 2424,
+	PPU_PPU_PKT_DATA115r = 2425,
+	PPU_PPU_PKT_DATA116r = 2426,
+	PPU_PPU_PKT_DATA117r = 2427,
+	PPU_PPU_PKT_DATA118r = 2428,
+	PPU_PPU_PKT_DATA119r = 2429,
+	PPU_PPU_PKT_DATA120r = 2430,
+	PPU_PPU_PKT_DATA121r = 2431,
+	PPU_PPU_PKT_DATA122r = 2432,
+	PPU_PPU_PKT_DATA123r = 2433,
+	PPU_PPU_PKT_DATA124r = 2434,
+	PPU_PPU_PKT_DATA125r = 2435,
+	PPU_PPU_PKT_DATA126r = 2436,
+	PPU_PPU_PKT_DATA127r = 2437,
+	PPU_PPU_SPR0r = 2438,
+	PPU_PPU_SPR1r = 2439,
+	PPU_PPU_SPR2r = 2440,
+	PPU_PPU_SPR3r = 2441,
+	PPU_PPU_SPR4r = 2442,
+	PPU_PPU_SPR5r = 2443,
+	PPU_PPU_SPR6r = 2444,
+	PPU_PPU_SPR7r = 2445,
+	PPU_PPU_SPR8r = 2446,
+	PPU_PPU_SPR9r = 2447,
+	PPU_PPU_SPR10r = 2448,
+	PPU_PPU_SPR11r = 2449,
+	PPU_PPU_SPR12r = 2450,
+	PPU_PPU_SPR13r = 2451,
+	PPU_PPU_SPR14r = 2452,
+	PPU_PPU_SPR15r = 2453,
+	PPU_PPU_SPR16r = 2454,
+	PPU_PPU_SPR17r = 2455,
+	PPU_PPU_SPR18r = 2456,
+	PPU_PPU_SPR19r = 2457,
+	PPU_PPU_SPR20r = 2458,
+	PPU_PPU_SPR21r = 2459,
+	PPU_PPU_SPR22r = 2460,
+	PPU_PPU_SPR23r = 2461,
+	PPU_PPU_SPR24r = 2462,
+	PPU_PPU_SPR25r = 2463,
+	PPU_PPU_SPR26r = 2464,
+	PPU_PPU_SPR27r = 2465,
+	PPU_PPU_SPR28r = 2466,
+	PPU_PPU_SPR29r = 2467,
+	PPU_PPU_SPR30r = 2468,
+	PPU_PPU_SPR31r = 2469,
+	PPU_PPU_RSP0r = 2470,
+	PPU_PPU_RSP1r = 2471,
+	PPU_PPU_RSP2r = 2472,
+	PPU_PPU_RSP3r = 2473,
+	PPU_PPU_RSP4r = 2474,
+	PPU_PPU_RSP5r = 2475,
+	PPU_PPU_RSP6r = 2476,
+	PPU_PPU_RSP7r = 2477,
+	PPU_PPU_RSP8r = 2478,
+	PPU_PPU_RSP9r = 2479,
+	PPU_PPU_RSP10r = 2480,
+	PPU_PPU_RSP11r = 2481,
+	PPU_PPU_RSP12r = 2482,
+	PPU_PPU_RSP13r = 2483,
+	PPU_PPU_RSP14r = 2484,
+	PPU_PPU_RSP15r = 2485,
+	PPU_PPU_RSP16r = 2486,
+	PPU_PPU_RSP17r = 2487,
+	PPU_PPU_RSP18r = 2488,
+	PPU_PPU_RSP19r = 2489,
+	PPU_PPU_RSP20r = 2490,
+	PPU_PPU_RSP21r = 2491,
+	PPU_PPU_RSP22r = 2492,
+	PPU_PPU_RSP23r = 2493,
+	PPU_PPU_RSP24r = 2494,
+	PPU_PPU_RSP25r = 2495,
+	PPU_PPU_RSP26r = 2496,
+	PPU_PPU_RSP27r = 2497,
+	PPU_PPU_RSP28r = 2498,
+	PPU_PPU_RSP29r = 2499,
+	PPU_PPU_RSP30r = 2500,
+	PPU_PPU_RSP31r = 2501,
+	PPU_PPU_KEY0r = 2502,
+	PPU_PPU_KEY1r = 2503,
+	PPU_PPU_KEY2r = 2504,
+	PPU_PPU_KEY3r = 2505,
+	PPU_PPU_KEY4r = 2506,
+	PPU_PPU_KEY5r = 2507,
+	PPU_PPU_KEY6r = 2508,
+	PPU_PPU_KEY7r = 2509,
+	PPU_PPU_KEY8r = 2510,
+	PPU_PPU_KEY9r = 2511,
+	PPU_PPU_KEY10r = 2512,
+	PPU_PPU_KEY11r = 2513,
+	PPU_PPU_KEY12r = 2514,
+	PPU_PPU_KEY13r = 2515,
+	PPU_PPU_KEY14r = 2516,
+	PPU_PPU_KEY15r = 2517,
+	PPU_PPU_KEY16r = 2518,
+	PPU_PPU_KEY17r = 2519,
+	PPU_PPU_KEY18r = 2520,
+	PPU_PPU_KEY19r = 2521,
+	PPU_PPU_FLAGr = 2522,
+	PPU_CLUSTER_INT_1200M_FLAGr = 2523,
+	PPU_CLUSTER_BP_INSTR_Lr = 2524,
+	PPU_CLUSTER_BP_INSTR_Hr = 2525,
+	PPU_CLUSTER_BP_ADDRr = 2526,
+	PPU_CLUSTER_DRRr = 2527,
+	PPU_CLUSTER_DSRr = 2528,
+	PPU_CLUSTER_DBG_RTL_DATEr = 2529,
+	PPU_CLUSTER_ME_CONTINUEr = 2530,
+	PPU_CLUSTER_ME_STEPr = 2531,
+	PPU_CLUSTER_ME_REFRESHr = 2532,
+	PPU_CLUSTER_DRR_CLRr = 2533,
+	PPU_CLUSTER_ME_BUSY_THRESOLDr = 2534,
+	PPU_CLUSTER_INT_1200M_STAr = 2535,
+	PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_Lr = 2536,
+	PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_Hr = 2537,
+	PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_Lr = 2538,
+	PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_Hr = 2539,
+	PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_Lr = 2540,
+	PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_Hr = 2541,
+	PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_Lr = 2542,
+	PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_Hr = 2543,
+	PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_Lr = 2544,
+	PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_Hr = 2545,
+	PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_Lr = 2546,
+	PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_Hr = 2547,
+	PPU_CLUSTER_PPU_STATICS_WB_EXCEPTION_CFGr = 2548,
+	PPU_CLUSTER_THREAD_SWITCH_ENr = 2549,
+	PPU_CLUSTER_IS_ME_NOT_IDLEr = 2550,
+	PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_ASSERT_CFGr = 2551,
+	PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_NEGATE_CFGr = 2552,
+	PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr = 2553,
+	PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr = 2554,
+	PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr = 2555,
+	PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr = 2556,
+	PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_ASSERT_CFGr = 2557,
+	PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_NEGATE_CFGr = 2558,
+	PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_ASSERT_CFGr = 2559,
+	PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_NEGATE_CFGr = 2560,
+	PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_ASSERT_CFGr = 2561,
+	PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_NEGATE_CFGr = 2562,
+	PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_ASSERT_CFGr = 2563,
+	PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_NEGATE_CFGr = 2564,
+	PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr = 2565,
+	PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr = 2566,
+	PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFGr = 2567,
+	PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFGr = 2568,
+	PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr = 2569,
+	PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr = 2570,
+	PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_ASSERT_CFGr = 2571,
+	PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_NEGATE_CFGr = 2572,
+	PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr = 2573,
+	PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr = 2574,
+	PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_ASSERT_CFGr = 2575,
+	PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_NEGATE_CFGr = 2576,
+	PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr = 2577,
+	PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr = 2578,
+	PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFGr = 2579,
+	PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFGr = 2580,
+	PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr = 2581,
+	PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr = 2582,
+	PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_ASSERT_CFGr = 2583,
+	PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_NEGATE_CFGr = 2584,
+	PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_ASSERT_CFGr = 2585,
+	PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_NEGATE_CFGr = 2586,
+	PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_ASSERT_CFGr = 2587,
+	PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_NEGATE_CFGr = 2588,
+	PPU_CLUSTER_INT_600M_CLUSTER_MEX_FIFO_MASKr = 2589,
+	PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_FLAGr = 2590,
+	PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_STAr = 2591,
+	PPU_CLUSTER_MEX_CNT_CFGr = 2592,
+	PPU_CLUSTER_INT_600M_CLUSTER_MEX_RAM_ECC_ERROR_INTERRUPT_MASKr = 2593,
+	PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_FLAGr = 2594,
+	PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_STAr = 2595,
+	PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_ASSERT_CFGr = 2596,
+	PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_NEGATE_CFGr = 2597,
+	PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_ASSERT_CFGr = 2598,
+	PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_NEGATE_CFGr = 2599,
+	PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_ASSERT_CFGr = 2600,
+	PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_NEGATE_CFGr = 2601,
+	PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_ASSERT_CFGr = 2602,
+	PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_NEGATE_CFGr = 2603,
+	PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr = 2604,
+	PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr = 2605,
+	PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr = 2606,
+	PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr = 2607,
+	PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr = 2608,
+	PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr = 2609,
+	PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_Hr = 2610,
+	PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_Lr = 2611,
+	PPU_CLUSTER_CLUSTER_ISE_KEY_OUT_VLD_CNTr = 2612,
+	PPU_CLUSTER_ISE_CLUSTER_RSP_IN_VLD_CNTr = 2613,
+	PPU_CLUSTER_CLUSTER_ESE_KEY_OUT_VLD_CNTr = 2614,
+	PPU_CLUSTER_ESE_CLUSTER_RSP_IN_VLD_CNTr = 2615,
+	PPU_CLUSTER_CLUSTER_STAT_CMD_VLD_CNTr = 2616,
+	PPU_CLUSTER_STAT_CLUSTER_RSP_VLD_CNTr = 2617,
+	PPU_CLUSTER_MEX_DEBUG_KEY_VLD_CNTr = 2618,
+	PPU_CLUSTER_ISE_CLUSTER_KEY_FC_CNTr = 2619,
+	PPU_CLUSTER_ESE_CLUSTER_KEY_FC_CNTr = 2620,
+	PPU_CLUSTER_CLUSTER_ISE_RSP_FC_CNTr = 2621,
+	PPU_CLUSTER_CLUSTER_ESE_RSP_FC_CNTr = 2622,
+	PPU_CLUSTER_STAT_CLUSTER_CMD_FC_CNTr = 2623,
+	PPU_CLUSTER_CLUSTER_STAT_RSP_FC_CNTr = 2624,
+	PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_Lr = 2625,
+	PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_Hr = 2626,
+	PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_Lr = 2627,
+	PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_Hr = 2628,
+	PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_Lr = 2629,
+	PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_Hr = 2630,
+	PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_Lr = 2631,
+	PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_Hr = 2632,
+	PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_Lr = 2633,
+	PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_Hr = 2634,
+	PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_Lr = 2635,
+	PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_Hr = 2636,
+	PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_Lr = 2637,
+	PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_Hr = 2638,
+	PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_Lr = 2639,
+	PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_Hr = 2640,
+	PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_Lr = 2641,
+	PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_Hr = 2642,
+	PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_Lr = 2643,
+	PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_Hr = 2644,
+	PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_Lr = 2645,
+	PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_Hr = 2646,
+	PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_Lr = 2647,
+	PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_Hr = 2648,
+	PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_Lr = 2649,
+	PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_Hr = 2650,
+	PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_Lr = 2651,
+	PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_Hr = 2652,
+	PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_Lr = 2653,
+	PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_Hr = 2654,
+	PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_Lr = 2655,
+	PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_Hr = 2656,
+	PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_Lr = 2657,
+	PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_Hr = 2658,
+	PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_Lr = 2659,
+	PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_Hr = 2660,
+	PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_Lr = 2661,
+	PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_Hr = 2662,
+	PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_Lr = 2663,
+	PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_Hr = 2664,
+	PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_Lr = 2665,
+	PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_Hr = 2666,
+	PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_Lr = 2667,
+	PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_Hr = 2668,
+	PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_Lr = 2669,
+	PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_Hr = 2670,
+	PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_Lr = 2671,
+	PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_Hr = 2672,
+	PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_Lr = 2673,
+	PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_Hr = 2674,
+	PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_Lr = 2675,
+	PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_Hr = 2676,
+	PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_Lr = 2677,
+	PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_Hr = 2678,
+	PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_Lr = 2679,
+	PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_Hr = 2680,
+	PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_Lr = 2681,
+	PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_Hr = 2682,
+	SE_CFG_PPU_SOFT_RSTr = 2683,
+	SE_CFG_EPT_FLAGr = 2684,
+	SE_CFG_DDR_KEY_LK0_3r = 2685,
+	SE_CFG_DDR_KEY_LK0_2r = 2686,
+	SE_CFG_DDR_KEY_LK0_1r = 2687,
+	SE_CFG_DDR_KEY_LK0_0r = 2688,
+	SE_CFG_DDR_KEY_LK1_3r = 2689,
+	SE_CFG_DDR_KEY_LK1_2r = 2690,
+	SE_CFG_DDR_KEY_LK1_1r = 2691,
+	SE_CFG_DDR_KEY_LK1_0r = 2692,
+	SE_CFG_HASH_KEY_LK0_18r = 2693,
+	SE_CFG_HASH_KEY_LK0_17r = 2694,
+	SE_CFG_HASH_KEY_LK0_16r = 2695,
+	SE_CFG_HASH_KEY_LK0_15r = 2696,
+	SE_CFG_HASH_KEY_LK0_14r = 2697,
+	SE_CFG_HASH_KEY_LK0_13r = 2698,
+	SE_CFG_HASH_KEY_LK0_12r = 2699,
+	SE_CFG_HASH_KEY_LK0_11r = 2700,
+	SE_CFG_HASH_KEY_LK0_10r = 2701,
+	SE_CFG_HASH_KEY_LK0_9r = 2702,
+	SE_CFG_HASH_KEY_LK0_8r = 2703,
+	SE_CFG_HASH_KEY_LK0_7r = 2704,
+	SE_CFG_HASH_KEY_LK0_6r = 2705,
+	SE_CFG_HASH_KEY_LK0_5r = 2706,
+	SE_CFG_HASH_KEY_LK0_4r = 2707,
+	SE_CFG_HASH_KEY_LK0_3r = 2708,
+	SE_CFG_HASH_KEY_LK0_2r = 2709,
+	SE_CFG_HASH_KEY_LK0_1r = 2710,
+	SE_CFG_HASH_KEY_LK0_0r = 2711,
+	SE_CFG_HASH_KEY_LK1_18r = 2712,
+	SE_CFG_HASH_KEY_LK1_17r = 2713,
+	SE_CFG_HASH_KEY_LK1_16r = 2714,
+	SE_CFG_HASH_KEY_LK1_15r = 2715,
+	SE_CFG_HASH_KEY_LK1_14r = 2716,
+	SE_CFG_HASH_KEY_LK1_13r = 2717,
+	SE_CFG_HASH_KEY_LK1_12r = 2718,
+	SE_CFG_HASH_KEY_LK1_11r = 2719,
+	SE_CFG_HASH_KEY_LK1_10r = 2720,
+	SE_CFG_HASH_KEY_LK1_9r = 2721,
+	SE_CFG_HASH_KEY_LK1_8r = 2722,
+	SE_CFG_HASH_KEY_LK1_7r = 2723,
+	SE_CFG_HASH_KEY_LK1_6r = 2724,
+	SE_CFG_HASH_KEY_LK1_5r = 2725,
+	SE_CFG_HASH_KEY_LK1_4r = 2726,
+	SE_CFG_HASH_KEY_LK1_3r = 2727,
+	SE_CFG_HASH_KEY_LK1_2r = 2728,
+	SE_CFG_HASH_KEY_LK1_1r = 2729,
+	SE_CFG_HASH_KEY_LK1_0r = 2730,
+	SE_CFG_HASH_KEY_LK2_18r = 2731,
+	SE_CFG_HASH_KEY_LK2_17r = 2732,
+	SE_CFG_HASH_KEY_LK2_16r = 2733,
+	SE_CFG_HASH_KEY_LK2_15r = 2734,
+	SE_CFG_HASH_KEY_LK2_14r = 2735,
+	SE_CFG_HASH_KEY_LK2_13r = 2736,
+	SE_CFG_HASH_KEY_LK2_12r = 2737,
+	SE_CFG_HASH_KEY_LK2_11r = 2738,
+	SE_CFG_HASH_KEY_LK2_10r = 2739,
+	SE_CFG_HASH_KEY_LK2_9r = 2740,
+	SE_CFG_HASH_KEY_LK2_8r = 2741,
+	SE_CFG_HASH_KEY_LK2_7r = 2742,
+	SE_CFG_HASH_KEY_LK2_6r = 2743,
+	SE_CFG_HASH_KEY_LK2_5r = 2744,
+	SE_CFG_HASH_KEY_LK2_4r = 2745,
+	SE_CFG_HASH_KEY_LK2_3r = 2746,
+	SE_CFG_HASH_KEY_LK2_2r = 2747,
+	SE_CFG_HASH_KEY_LK2_1r = 2748,
+	SE_CFG_HASH_KEY_LK2_0r = 2749,
+	SE_CFG_HASH_KEY_LK3_18r = 2750,
+	SE_CFG_HASH_KEY_LK3_17r = 2751,
+	SE_CFG_HASH_KEY_LK3_16r = 2752,
+	SE_CFG_HASH_KEY_LK3_15r = 2753,
+	SE_CFG_HASH_KEY_LK3_14r = 2754,
+	SE_CFG_HASH_KEY_LK3_13r = 2755,
+	SE_CFG_HASH_KEY_LK3_12r = 2756,
+	SE_CFG_HASH_KEY_LK3_11r = 2757,
+	SE_CFG_HASH_KEY_LK3_10r = 2758,
+	SE_CFG_HASH_KEY_LK3_9r = 2759,
+	SE_CFG_HASH_KEY_LK3_8r = 2760,
+	SE_CFG_HASH_KEY_LK3_7r = 2761,
+	SE_CFG_HASH_KEY_LK3_6r = 2762,
+	SE_CFG_HASH_KEY_LK3_5r = 2763,
+	SE_CFG_HASH_KEY_LK3_4r = 2764,
+	SE_CFG_HASH_KEY_LK3_3r = 2765,
+	SE_CFG_HASH_KEY_LK3_2r = 2766,
+	SE_CFG_HASH_KEY_LK3_1r = 2767,
+	SE_CFG_HASH_KEY_LK3_0r = 2768,
+	SE_CFG_LPM_KEY_LK0_6r = 2769,
+	SE_CFG_LPM_KEY_LK0_5r = 2770,
+	SE_CFG_LPM_KEY_LK0_4r = 2771,
+	SE_CFG_LPM_KEY_LK0_3r = 2772,
+	SE_CFG_LPM_KEY_LK0_2r = 2773,
+	SE_CFG_LPM_KEY_LK0_1r = 2774,
+	SE_CFG_LPM_KEY_LK0_0r = 2775,
+	SE_CFG_LPM_KEY_LK1_6r = 2776,
+	SE_CFG_LPM_KEY_LK1_5r = 2777,
+	SE_CFG_LPM_KEY_LK1_4r = 2778,
+	SE_CFG_LPM_KEY_LK1_3r = 2779,
+	SE_CFG_LPM_KEY_LK1_2r = 2780,
+	SE_CFG_LPM_KEY_LK1_1r = 2781,
+	SE_CFG_LPM_KEY_LK1_0r = 2782,
+	SE_CFG_LPM_KEY_LK2_6r = 2783,
+	SE_CFG_LPM_KEY_LK2_5r = 2784,
+	SE_CFG_LPM_KEY_LK2_4r = 2785,
+	SE_CFG_LPM_KEY_LK2_3r = 2786,
+	SE_CFG_LPM_KEY_LK2_2r = 2787,
+	SE_CFG_LPM_KEY_LK2_1r = 2788,
+	SE_CFG_LPM_KEY_LK2_0r = 2789,
+	SE_CFG_LPM_KEY_LK3_6r = 2790,
+	SE_CFG_LPM_KEY_LK3_5r = 2791,
+	SE_CFG_LPM_KEY_LK3_4r = 2792,
+	SE_CFG_LPM_KEY_LK3_3r = 2793,
+	SE_CFG_LPM_KEY_LK3_2r = 2794,
+	SE_CFG_LPM_KEY_LK3_1r = 2795,
+	SE_CFG_LPM_KEY_LK3_0r = 2796,
+	SE_CFG_ETCAM_KEY_LK0_22r = 2797,
+	SE_CFG_ETCAM_KEY_LK0_21r = 2798,
+	SE_CFG_ETCAM_KEY_LK0_20r = 2799,
+	SE_CFG_ETCAM_KEY_LK0_19r = 2800,
+	SE_CFG_ETCAM_KEY_LK0_18r = 2801,
+	SE_CFG_ETCAM_KEY_LK0_17r = 2802,
+	SE_CFG_ETCAM_KEY_LK0_16r = 2803,
+	SE_CFG_ETCAM_KEY_LK0_15r = 2804,
+	SE_CFG_ETCAM_KEY_LK0_14r = 2805,
+	SE_CFG_ETCAM_KEY_LK0_13r = 2806,
+	SE_CFG_ETCAM_KEY_LK0_12r = 2807,
+	SE_CFG_ETCAM_KEY_LK0_11r = 2808,
+	SE_CFG_ETCAM_KEY_LK0_10r = 2809,
+	SE_CFG_ETCAM_KEY_LK0_9r = 2810,
+	SE_CFG_ETCAM_KEY_LK0_8r = 2811,
+	SE_CFG_ETCAM_KEY_LK0_7r = 2812,
+	SE_CFG_ETCAM_KEY_LK0_6r = 2813,
+	SE_CFG_ETCAM_KEY_LK0_5r = 2814,
+	SE_CFG_ETCAM_KEY_LK0_4r = 2815,
+	SE_CFG_ETCAM_KEY_LK0_3r = 2816,
+	SE_CFG_ETCAM_KEY_LK0_2r = 2817,
+	SE_CFG_ETCAM_KEY_LK0_1r = 2818,
+	SE_CFG_ETCAM_KEY_LK0_0r = 2819,
+	SE_CFG_ETCAM_KEY_LK1_22r = 2820,
+	SE_CFG_ETCAM_KEY_LK1_21r = 2821,
+	SE_CFG_ETCAM_KEY_LK1_20r = 2822,
+	SE_CFG_ETCAM_KEY_LK1_19r = 2823,
+	SE_CFG_ETCAM_KEY_LK1_18r = 2824,
+	SE_CFG_ETCAM_KEY_LK1_17r = 2825,
+	SE_CFG_ETCAM_KEY_LK1_16r = 2826,
+	SE_CFG_ETCAM_KEY_LK1_15r = 2827,
+	SE_CFG_ETCAM_KEY_LK1_14r = 2828,
+	SE_CFG_ETCAM_KEY_LK1_13r = 2829,
+	SE_CFG_ETCAM_KEY_LK1_12r = 2830,
+	SE_CFG_ETCAM_KEY_LK1_11r = 2831,
+	SE_CFG_ETCAM_KEY_LK1_10r = 2832,
+	SE_CFG_ETCAM_KEY_LK1_9r = 2833,
+	SE_CFG_ETCAM_KEY_LK1_8r = 2834,
+	SE_CFG_ETCAM_KEY_LK1_7r = 2835,
+	SE_CFG_ETCAM_KEY_LK1_6r = 2836,
+	SE_CFG_ETCAM_KEY_LK1_5r = 2837,
+	SE_CFG_ETCAM_KEY_LK1_4r = 2838,
+	SE_CFG_ETCAM_KEY_LK1_3r = 2839,
+	SE_CFG_ETCAM_KEY_LK1_2r = 2840,
+	SE_CFG_ETCAM_KEY_LK1_1r = 2841,
+	SE_CFG_ETCAM_KEY_LK1_0r = 2842,
+	SE_CFG_ETCAM_KEY_LK2_22r = 2843,
+	SE_CFG_ETCAM_KEY_LK2_21r = 2844,
+	SE_CFG_ETCAM_KEY_LK2_20r = 2845,
+	SE_CFG_ETCAM_KEY_LK2_19r = 2846,
+	SE_CFG_ETCAM_KEY_LK2_18r = 2847,
+	SE_CFG_ETCAM_KEY_LK2_17r = 2848,
+	SE_CFG_ETCAM_KEY_LK2_16r = 2849,
+	SE_CFG_ETCAM_KEY_LK2_15r = 2850,
+	SE_CFG_ETCAM_KEY_LK2_14r = 2851,
+	SE_CFG_ETCAM_KEY_LK2_13r = 2852,
+	SE_CFG_ETCAM_KEY_LK2_12r = 2853,
+	SE_CFG_ETCAM_KEY_LK2_11r = 2854,
+	SE_CFG_ETCAM_KEY_LK2_10r = 2855,
+	SE_CFG_ETCAM_KEY_LK2_9r = 2856,
+	SE_CFG_ETCAM_KEY_LK2_8r = 2857,
+	SE_CFG_ETCAM_KEY_LK2_7r = 2858,
+	SE_CFG_ETCAM_KEY_LK2_6r = 2859,
+	SE_CFG_ETCAM_KEY_LK2_5r = 2860,
+	SE_CFG_ETCAM_KEY_LK2_4r = 2861,
+	SE_CFG_ETCAM_KEY_LK2_3r = 2862,
+	SE_CFG_ETCAM_KEY_LK2_2r = 2863,
+	SE_CFG_ETCAM_KEY_LK2_1r = 2864,
+	SE_CFG_ETCAM_KEY_LK2_0r = 2865,
+	SE_CFG_ETCAM_KEY_LK3_22r = 2866,
+	SE_CFG_ETCAM_KEY_LK3_21r = 2867,
+	SE_CFG_ETCAM_KEY_LK3_20r = 2868,
+	SE_CFG_ETCAM_KEY_LK3_19r = 2869,
+	SE_CFG_ETCAM_KEY_LK3_18r = 2870,
+	SE_CFG_ETCAM_KEY_LK3_17r = 2871,
+	SE_CFG_ETCAM_KEY_LK3_16r = 2872,
+	SE_CFG_ETCAM_KEY_LK3_15r = 2873,
+	SE_CFG_ETCAM_KEY_LK3_14r = 2874,
+	SE_CFG_ETCAM_KEY_LK3_13r = 2875,
+	SE_CFG_ETCAM_KEY_LK3_12r = 2876,
+	SE_CFG_ETCAM_KEY_LK3_11r = 2877,
+	SE_CFG_ETCAM_KEY_LK3_10r = 2878,
+	SE_CFG_ETCAM_KEY_LK3_9r = 2879,
+	SE_CFG_ETCAM_KEY_LK3_8r = 2880,
+	SE_CFG_ETCAM_KEY_LK3_7r = 2881,
+	SE_CFG_ETCAM_KEY_LK3_6r = 2882,
+	SE_CFG_ETCAM_KEY_LK3_5r = 2883,
+	SE_CFG_ETCAM_KEY_LK3_4r = 2884,
+	SE_CFG_ETCAM_KEY_LK3_3r = 2885,
+	SE_CFG_ETCAM_KEY_LK3_2r = 2886,
+	SE_CFG_ETCAM_KEY_LK3_1r = 2887,
+	SE_CFG_ETCAM_KEY_LK3_0r = 2888,
+	SE_CFG_PBU_KEY_LK0_3r = 2889,
+	SE_CFG_PBU_KEY_LK0_2r = 2890,
+	SE_CFG_PBU_KEY_LK0_1r = 2891,
+	SE_CFG_PBU_KEY_LK0_0r = 2892,
+	SE_CFG_PBU_KEY_LK1_3r = 2893,
+	SE_CFG_PBU_KEY_LK1_2r = 2894,
+	SE_CFG_PBU_KEY_LK1_1r = 2895,
+	SE_CFG_PBU_KEY_LK1_0r = 2896,
+	SE_CFG_PBU_KEY_LK2_3r = 2897,
+	SE_CFG_PBU_KEY_LK2_2r = 2898,
+	SE_CFG_PBU_KEY_LK2_1r = 2899,
+	SE_CFG_PBU_KEY_LK2_0r = 2900,
+	SE_CFG_PBU_KEY_LK3_3r = 2901,
+	SE_CFG_PBU_KEY_LK3_2r = 2902,
+	SE_CFG_PBU_KEY_LK3_1r = 2903,
+	SE_CFG_PBU_KEY_LK3_0r = 2904,
+	SE_ALG_SCHD_LEARN_FIFO_PFULL_ASTr = 2905,
+	SE_ALG_SCHD_LEARN_FIFO_PFULL_NEGr = 2906,
+	SE_ALG_SCHD_HASH0_FIFO_PFULL_ASTr = 2907,
+	SE_ALG_SCHD_HASH0_FIFO_PFULL_NEGr = 2908,
+	SE_ALG_SCHD_HASH1_FIFO_PFULL_ASTr = 2909,
+	SE_ALG_SCHD_HASH1_FIFO_PFULL_NEGr = 2910,
+	SE_ALG_SCHD_HASH2_FIFO_PFULL_ASTr = 2911,
+	SE_ALG_SCHD_HASH2_FIFO_PFULL_NEGr = 2912,
+	SE_ALG_SCHD_HASH3_FIFO_PFULL_ASTr = 2913,
+	SE_ALG_SCHD_HASH3_FIFO_PFULL_NEGr = 2914,
+	SE_ALG_SCHD_LPM_FIFO_PFULL_ASTr = 2915,
+	SE_ALG_SCHD_LPM_FIFO_PFULL_NEGr = 2916,
+	SE_ALG_HASH0_KEY_FIFO_PFULL_ASTr = 2917,
+	SE_ALG_HASH0_KEY_FIFO_PFULL_NEGr = 2918,
+	SE_ALG_HASH0_SREQ_FIFO_PFULL_ASTr = 2919,
+	SE_ALG_HASH0_SREQ_FIFO_PFULL_NEGr = 2920,
+	SE_ALG_HASH0_INT_RSP_FIFO_PFULL_ASTr = 2921,
+	SE_ALG_HASH0_INT_RSP_FIFO_PFULL_NEGr = 2922,
+	SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_ASTr = 2923,
+	SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_NEGr = 2924,
+	SE_ALG_HASH1_KEY_FIFO_PFULL_ASTr = 2925,
+	SE_ALG_HASH1_KEY_FIFO_PFULL_NEGr = 2926,
+	SE_ALG_HASH1_SREQ_FIFO_PFULL_ASTr = 2927,
+	SE_ALG_HASH1_SREQ_FIFO_PFULL_NEGr = 2928,
+	SE_ALG_HASH1_INT_RSP_FIFO_PFULL_ASTr = 2929,
+	SE_ALG_HASH1_INT_RSP_FIFO_PFULL_NEGr = 2930,
+	SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_ASTr = 2931,
+	SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_NEGr = 2932,
+	SE_ALG_HASH2_KEY_FIFO_PFULL_ASTr = 2933,
+	SE_ALG_HASH2_KEY_FIFO_PFULL_NEGr = 2934,
+	SE_ALG_HASH2_SREQ_FIFO_PFULL_ASTr = 2935,
+	SE_ALG_HASH2_SREQ_FIFO_PFULL_NEGr = 2936,
+	SE_ALG_HASH2_INT_RSP_FIFO_PFULL_ASTr = 2937,
+	SE_ALG_HASH2_INT_RSP_FIFO_PFULL_NEGr = 2938,
+	SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_ASTr = 2939,
+	SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_NEGr = 2940,
+	SE_ALG_HASH3_KEY_FIFO_PFULL_ASTr = 2941,
+	SE_ALG_HASH3_KEY_FIFO_PFULL_NEGr = 2942,
+	SE_ALG_HASH3_SREQ_FIFO_PFULL_ASTr = 2943,
+	SE_ALG_HASH3_SREQ_FIFO_PFULL_NEGr = 2944,
+	SE_ALG_HASH3_INT_RSP_FIFO_PFULL_ASTr = 2945,
+	SE_ALG_HASH3_INT_RSP_FIFO_PFULL_NEGr = 2946,
+	SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_ASTr = 2947,
+	SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_NEGr = 2948,
+	SE_ALG_LPM_AS_INFOr = 2949,
+	SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_NEGr = 2950,
+	SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_ASTr = 2951,
+	SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_NEGr = 2952,
+	SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_ASTr = 2953,
+	SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_NEGr = 2954,
+	SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_ASTr = 2955,
+	SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_NEGr = 2956,
+	SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_ASTr = 2957,
+	SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_NEGr = 2958,
+	SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_ASTr = 2959,
+	SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_NEGr = 2960,
+	SE_ALG_LPM_V4_DDR3_BASE_ADDRr = 2961,
+	SE_ALG_LPM_V6_DDR3_BASE_ADDRr = 2962,
+	SE_ALG_DEBUG_CNT_MODEr = 2963,
+	SE_ALG_HASH_P0_KEY_VLD_CNTr = 2964,
+	SE_ALG_HASH_P1_KEY_VLD_CNTr = 2965,
+	SE_ALG_HASH_P2_KEY_VLD_CNTr = 2966,
+	SE_ALG_HASH_P3_KEY_VLD_CNTr = 2967,
+	SE_ALG_LPM_P0_KEY_VLD_CNTr = 2968,
+	SE_ALG_HASH_P0_RSP_VLD_CNTr = 2969,
+	SE_ALG_HASH_P1_RSP_VLD_CNTr = 2970,
+	SE_ALG_HASH_P2_RSP_VLD_CNTr = 2971,
+	SE_ALG_HASH_P3_RSP_VLD_CNTr = 2972,
+	SE_ALG_LPM_P0_RSP_VLD_CNTr = 2973,
+	SE_ALG_HASH_P0_SMF_CNTr = 2974,
+	SE_ALG_HASH_P1_SMF_CNTr = 2975,
+	SE_ALG_HASH_P2_SMF_CNTr = 2976,
+	SE_ALG_HASH_P3_SMF_CNTr = 2977,
+	SE_ALG_LPM_P0_SMF_CNTr = 2978,
+	SE_ALG_HASH_P0_SPACEVLD_CNTr = 2979,
+	SE_ALG_HASH_P1_SPACEVLD_CNTr = 2980,
+	SE_ALG_HASH_P2_SPACEVLD_CNTr = 2981,
+	SE_ALG_HASH_P3_SPACEVLD_CNTr = 2982,
+	SE_ALG_SMMU1_P0_REQ_VLD_CNTr = 2983,
+	SE_ALG_SMMU1_P1_REQ_VLD_CNTr = 2984,
+	SE_ALG_SMMU1_P2_REQ_VLD_CNTr = 2985,
+	SE_ALG_SMMU1_P3_REQ_VLD_CNTr = 2986,
+	SE_ALG_SMMU1_P4_REQ_VLD_CNTr = 2987,
+	SE_ALG_SMMU1_P5_REQ_VLD_CNTr = 2988,
+	SE_ALG_SMMU1_P0_RSP_VLD_CNTr = 2989,
+	SE_ALG_SMMU1_P1_RSP_VLD_CNTr = 2990,
+	SE_ALG_SMMU1_P2_RSP_VLD_CNTr = 2991,
+	SE_ALG_SMMU1_P3_RSP_VLD_CNTr = 2992,
+	SE_ALG_SMMU1_P4_RSP_VLD_CNTr = 2993,
+	SE_ALG_SMMU1_P5_RSP_VLD_CNTr = 2994,
+	SE_ALG_SCHD_LEARN_FIFO_INT_CNTr = 2995,
+	SE_ALG_SCHD_HASH0_FIFO_INT_CNTr = 2996,
+	SE_ALG_SCHD_HASH1_FIFO_INT_CNTr = 2997,
+	SE_ALG_SCHD_HASH2_FIFO_INT_CNTr = 2998,
+	SE_ALG_SCHD_HASH3_FIFO_INT_CNTr = 2999,
+	SE_ALG_SCHD_LPM_FIFO_INT_CNTr = 3000,
+	SE_ALG_SCHD_LEARN_FIFO_PARITY_ERR_CNTr = 3001,
+	SE_ALG_SCHD_HASH0_FIFO_PARITY_ERR_CNTr = 3002,
+	SE_ALG_SCHD_HASH1_FIFO_PARITY_ERR_CNTr = 3003,
+	SE_ALG_SCHD_HASH2_FIFO_PARITY_ERR_CNTr = 3004,
+	SE_ALG_SCHD_HASH3_FIFO_PARITY_ERR_CNTr = 3005,
+	SE_ALG_SCHD_LPM_FIFO_PARITY_ERR_CNTr = 3006,
+	SE_ALG_RD_INIT_CFT_CNTr = 3007,
+	SE_ALG_ZGP0_ZBLK0_ECC_ERR_CNTr = 3008,
+	SE_ALG_ZGP0_ZBLK1_ECC_ERR_CNTr = 3009,
+	SE_ALG_ZGP0_ZBLK2_ECC_ERR_CNTr = 3010,
+	SE_ALG_ZGP0_ZBLK3_ECC_ERR_CNTr = 3011,
+	SE_ALG_ZGP0_ZBLK4_ECC_ERR_CNTr = 3012,
+	SE_ALG_ZGP0_ZBLK5_ECC_ERR_CNTr = 3013,
+	SE_ALG_ZGP0_ZBLK6_ECC_ERR_CNTr = 3014,
+	SE_ALG_ZGP0_ZBLK7_ECC_ERR_CNTr = 3015,
+	SE_ALG_ZGP1_ZBLK0_ECC_ERR_CNTr = 3016,
+	SE_ALG_ZGP1_ZBLK1_ECC_ERR_CNTr = 3017,
+	SE_ALG_ZGP1_ZBLK2_ECC_ERR_CNTr = 3018,
+	SE_ALG_ZGP1_ZBLK3_ECC_ERR_CNTr = 3019,
+	SE_ALG_ZGP1_ZBLK4_ECC_ERR_CNTr = 3020,
+	SE_ALG_ZGP1_ZBLK5_ECC_ERR_CNTr = 3021,
+	SE_ALG_ZGP1_ZBLK6_ECC_ERR_CNTr = 3022,
+	SE_ALG_ZGP1_ZBLK7_ECC_ERR_CNTr = 3023,
+	SE_ALG_ZGP2_ZBLK0_ECC_ERR_CNTr = 3024,
+	SE_ALG_ZGP2_ZBLK1_ECC_ERR_CNTr = 3025,
+	SE_ALG_ZGP2_ZBLK2_ECC_ERR_CNTr = 3026,
+	SE_ALG_ZGP2_ZBLK3_ECC_ERR_CNTr = 3027,
+	SE_ALG_ZGP2_ZBLK4_ECC_ERR_CNTr = 3028,
+	SE_ALG_ZGP2_ZBLK5_ECC_ERR_CNTr = 3029,
+	SE_ALG_ZGP2_ZBLK6_ECC_ERR_CNTr = 3030,
+	SE_ALG_ZGP2_ZBLK7_ECC_ERR_CNTr = 3031,
+	SE_ALG_ZGP3_ZBLK0_ECC_ERR_CNTr = 3032,
+	SE_ALG_ZGP3_ZBLK1_ECC_ERR_CNTr = 3033,
+	SE_ALG_ZGP3_ZBLK2_ECC_ERR_CNTr = 3034,
+	SE_ALG_ZGP3_ZBLK3_ECC_ERR_CNTr = 3035,
+	SE_ALG_ZGP3_ZBLK4_ECC_ERR_CNTr = 3036,
+	SE_ALG_ZGP3_ZBLK5_ECC_ERR_CNTr = 3037,
+	SE_ALG_ZGP3_ZBLK6_ECC_ERR_CNTr = 3038,
+	SE_ALG_ZGP3_ZBLK7_ECC_ERR_CNTr = 3039,
+	SE_ALG_ZCAM_HASH_P0_ERR_CNTr = 3040,
+	SE_ALG_ZCAM_HASH_P1_ERR_CNTr = 3041,
+	SE_ALG_ZCAM_HASH_P2_ERR_CNTr = 3042,
+	SE_ALG_ZCAM_HASH_P3_ERR_CNTr = 3043,
+	SE_ALG_ZCAM_LPM_ERR_CNTr = 3044,
+	SE_ALG_HASH0_SREQ_FIFO_PARITY_ERR_CNTr = 3045,
+	SE_ALG_HASH0_SREQ_FIFO_INT_CNTr = 3046,
+	SE_ALG_HASH0_KEY_FIFO_INT_CNTr = 3047,
+	SE_ALG_HASH0_INT_RSP_FIFO_PARITY_ERR_CNTr = 3048,
+	SE_ALG_HASH0_EXT_RSP_FIFO_PARITY_ERR_CNTr = 3049,
+	SE_ALG_HASH0_EXT_RSP_FIFO_INT_CNTr = 3050,
+	SE_ALG_HASH0_INT_RSP_FIFO_INT_CNTr = 3051,
+	SE_ALG_HASH1_SREQ_FIFO_PARITY_ERR_CNTr = 3052,
+	SE_ALG_HASH1_SREQ_FIFO_INT_CNTr = 3053,
+	SE_ALG_HASH1_KEY_FIFO_INT_CNTr = 3054,
+	SE_ALG_HASH1_INT_RSP_FIFO_PARITY_ERR_CNTr = 3055,
+	SE_ALG_HASH1_EXT_RSP_FIFO_PARITY_ERR_CNTr = 3056,
+	SE_ALG_HASH1_EXT_RSP_FIFO_INT_CNTr = 3057,
+	SE_ALG_HASH1_INT_RSP_FIFO_INT_CNTr = 3058,
+	SE_ALG_HASH2_SREQ_FIFO_PARITY_ERR_CNTr = 3059,
+	SE_ALG_HASH2_SREQ_FIFO_INT_CNTr = 3060,
+	SE_ALG_HASH2_KEY_FIFO_INT_CNTr = 3061,
+	SE_ALG_HASH2_INT_RSP_FIFO_PARITY_ERR_CNTr = 3062,
+	SE_ALG_HASH2_EXT_RSP_FIFO_PARITY_ERR_CNTr = 3063,
+	SE_ALG_HASH2_EXT_RSP_FIFO_INT_CNTr = 3064,
+	SE_ALG_HASH2_INT_RSP_FIFO_INT_CNTr = 3065,
+	SE_ALG_HASH3_SREQ_FIFO_PARITY_ERR_CNTr = 3066,
+	SE_ALG_HASH3_SREQ_FIFO_INT_CNTr = 3067,
+	SE_ALG_HASH3_KEY_FIFO_INT_CNTr = 3068,
+	SE_ALG_HASH3_INT_RSP_FIFO_PARITY_ERR_CNTr = 3069,
+	SE_ALG_HASH3_EXT_RSP_FIFO_PARITY_ERR_CNTr = 3070,
+	SE_ALG_HASH3_EXT_RSP_FIFO_INT_CNTr = 3071,
+	SE_ALG_HASH3_INT_RSP_FIFO_INT_CNTr = 3072,
+	SE_ALG_LPM_EXT_RSP_FIFO_INT_CNTr = 3073,
+	SE_ALG_LPM_EXT_V6_FIFO_INT_CNTr = 3074,
+	SE_ALG_LPM_EXT_V4_FIFO_INT_CNTr = 3075,
+	SE_ALG_LPM_EXT_ADDR_FIFO_INT_CNTr = 3076,
+	SE_ALG_LPM_EXT_V4_FIFO_PARITY_ERR_CNTr = 3077,
+	SE_ALG_LPM_EXT_V6_FIFO_PARITY_ERR_CNTr = 3078,
+	SE_ALG_LPM_EXT_RSP_FIFO_PARITY_ERR_CNTr = 3079,
+	SE_ALG_LPM_AS_REQ_FIFO_INT_CNTr = 3080,
+	SE_ALG_LPM_AS_INT_RSP_FIFO_INT_CNTr = 3081,
+	SE_ALG_SE_ALG_INT_STATUSr = 3082,
+	SE_ALG_SCHD_INT_ENr = 3083,
+	SE_ALG_SCHD_INT_MASKr = 3084,
+	SE_ALG_SCHD_INT_STATUSr = 3085,
+	SE_ALG_ZBLK_ECC_INT_ENr = 3086,
+	SE_ALG_ZBLK_ECC_INT_MASKr = 3087,
+	SE_ALG_ZBLK_ECC_INT_STATUSr = 3088,
+	SE_ALG_HASH0_INT_ENr = 3089,
+	SE_ALG_HASH0_INT_MASKr = 3090,
+	SE_ALG_HASH0_INT_STATUSr = 3091,
+	SE_ALG_HASH1_INT_ENr = 3092,
+	SE_ALG_HASH1_INT_MASKr = 3093,
+	SE_ALG_HASH1_INT_STATUSr = 3094,
+	SE_ALG_HASH2_INT_ENr = 3095,
+	SE_ALG_HASH2_INT_MASKr = 3096,
+	SE_ALG_HASH2_INT_STATUSr = 3097,
+	SE_ALG_HASH3_INT_ENr = 3098,
+	SE_ALG_HASH3_INT_MASKr = 3099,
+	SE_ALG_HASH3_INT_STATUSr = 3100,
+	SE_ALG_LPM_INT_ENr = 3101,
+	SE_ALG_LPM_INT_MASKr = 3102,
+	SE_ALG_LPM_INT_STATUSr = 3103,
+	SE_ALG_ZBLOCK_LPM_MASK0r = 3104,
+	SE_ALG_ZBLOCK_LPM_MASK1r = 3105,
+	SE_ALG_ZBLOCK_LPM_MASK2r = 3106,
+	SE_ALG_ZBLOCK_LPM_MASK3r = 3107,
+	SE_ALG_ZBLOCK_DEFAULT_ROUTE0r = 3108,
+	SE_ALG_ZBLOCK_DEFAULT_ROUTE1r = 3109,
+	SE_ALG_ZBLOCK_DEFAULT_ROUTE2r = 3110,
+	SE_ALG_ZBLOCK_DEFAULT_ROUTE3r = 3111,
+	SE_ALG_ZBLOCK_DEFAULT_ROUTE4r = 3112,
+	SE_ALG_ZBLOCK_DEFAULT_ROUTE5r = 3113,
+	SE_ALG_ZBLOCK_DEFAULT_ROUTE6r = 3114,
+	SE_ALG_ZBLOCK_DEFAULT_ROUTE7r = 3115,
+	SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM0r = 3116,
+	SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM1r = 3117,
+	SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM2r = 3118,
+	SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM3r = 3119,
+	SE_ALG_ZBLOCK_ECC_ERR_STATUSr = 3120,
+	SE_ALG_ZBLOCK_LPM_V6_SRAM_CMPr = 3121,
+	SE_ALG_ZBLOCK_LPM_V4_SRAM_CMPr = 3122,
+	SE_PARSER_KSCHD_PFUL_CFGr = 3123,
+	SE_PARSER_DEBUG_CNT_MODEr = 3124,
+	SE_PARSER_PARSER_INT_ENr = 3125,
+	SE_PARSER_PARSER_INT_MASKr = 3126,
+	SE_PARSER_PARSER_INT_STATUSr = 3127,
+	SE_PARSER_PARSER_INT_UNMASK_FLAGr = 3128,
+	SE_PARSER_ECC_BYPASS_READr = 3129,
+	SE_PARSER_MEX0_5_REQ_CNTr = 3130,
+	SE_PARSER_KSCHD_REQ0_5_CNTr = 3131,
+	SE_PARSER_KSCHD_PARSER_FC0_5_CNTr = 3132,
+	SE_PARSER_SE_PPU_MEX0_5_FC_CNTr = 3133,
+	SE_PARSER_SMMU0_MARC_FC_CNTr = 3134,
+	SE_PARSER_SMMU0_MARC_KEY_CNTr = 3135,
+	SE_PARSER_CMMU_KEY_CNTr = 3136,
+	SE_PARSER_CMMU_PARSER_FC_CNTr = 3137,
+	SE_PARSER_MARC_TAB_TYPE_ERR_MEX0_5_CNTr = 3138,
+	SE_PARSER_ERAM_FULLADDR_DROP_CNTr = 3139,
+	SE_AS_HASH0_PFUL_CFGr = 3140,
+	SE_AS_HASH1_PFUL_CFGr = 3141,
+	SE_AS_HASH2_PFUL_CFGr = 3142,
+	SE_AS_HASH3_PFUL_CFGr = 3143,
+	SE_AS_PBU_PFUL_CFGr = 3144,
+	SE_AS_LPM_PFUL_CFGr = 3145,
+	SE_AS_ETCAM_PFUL_CFGr = 3146,
+	SE_AS_AS_LEARN0_FIFO_CFGr = 3147,
+	SE_AS_AS_LEARN1_FIFO_CFGr = 3148,
+	SE_AS_AS_DMA_FIFO_CFGr = 3149,
+	SE_AS_AGE_PFUL_CFGr = 3150,
+	SE_AS_ETCAM_RSP_CFGr = 3151,
+	SE_AS_PBU_ECC_BYPASS_READr = 3152,
+	SE_AS_ETCAM0_ECC_BYPASS_READr = 3153,
+	SE_AS_ETCAM1_ECC_BYPASS_READr = 3154,
+	SE_AS_LPM_ECC_BYPASS_READr = 3155,
+	SE_AS_HASH_ECC_BYPASS_READr = 3156,
+	SE_AS_HASH_LEARN_ECC_BYPASS_READr = 3157,
+	SE_AS_DEBUG_CNT_MODEr = 3158,
+	SE_AS_AS_INT_0_ENr = 3159,
+	SE_AS_AS_INT_0_MASKr = 3160,
+	SE_AS_AS_INT_1_ENr = 3161,
+	SE_AS_AS_INT_1_MASKr = 3162,
+	SE_AS_AS_INT_2_ENr = 3163,
+	SE_AS_AS_INT_2_MASKr = 3164,
+	SE_AS_AS_INT_0_STATUSr = 3165,
+	SE_AS_AS_INT_1_STATUSr = 3166,
+	SE_AS_AS_INT_2_STATUSr = 3167,
+	SE_AS_SE_AS_INT_STATUSr = 3168,
+	SE_AS_HASH0_3_WR_REQ_CNTr = 3169,
+	SE_AS_SMMU0_ETCAM0_1_FC_CNTr = 3170,
+	SE_AS_ETCAM0_1_SMMU0_REQ_CNTr = 3171,
+	SE_AS_SMMU0_ETCAM0_1_RSP_CNTr = 3172,
+	SE_AS_AS_HLA_HASH_P0_3_KEY_CNTr = 3173,
+	SE_AS_AS_HLA_LPM_P0_KEY_CNTr = 3174,
+	SE_AS_ALG_AS_HASH_P0_3_RSP_CNTr = 3175,
+	SE_AS_ALG_AS_HASH_P0_3_SMF_RSP_CNTr = 3176,
+	SE_AS_ALG_AS_LPM_P0_RSP_CNTr = 3177,
+	SE_AS_ALG_AS_LPM_P0_3_SMF_RSP_CNTr = 3178,
+	SE_AS_AS_PBU_KEY_CNTr = 3179,
+	SE_AS_PBU_SE_DPI_RSP_DAT_CNTr = 3180,
+	SE_AS_AS_ETCAM_CTRL_REQ0_CNTr = 3181,
+	SE_AS_ETCAM_CTRL_AS_INDEX0_1_CNTr = 3182,
+	SE_AS_ETCAM_CTRL_AS_HIT0_1_CNTr = 3183,
+	SE_AS_AS_SMMU0_REQ_CNTr = 3184,
+	SE_AS_LEARN_HLA_WR_CNTr = 3185,
+	SE_AS_AS_SMMU1_REQ_CNTr = 3186,
+	SE_AS_SE_CFG_MAC_DAT_CNTr = 3187,
+	SE_AS_ALG_AS_HASH_P0_3_FC_CNTr = 3188,
+	SE_AS_ALG_AS_LPM_P0_FC_CNTr = 3189,
+	SE_AS_AS_ALG_HASH_P0_3_FC_CNTr = 3190,
+	SE_AS_AS_ALG_LPM_P0_FC_CNTr = 3191,
+	SE_AS_AS_PBU_FC_CNTr = 3192,
+	SE_AS_PBU_SE_DPI_KEY_FC_CNTr = 3193,
+	SE_AS_AS_ETCAM_CTRL_FC0_1_CNTr = 3194,
+	SE_AS_ETCAM_CTRL_AS_FC0_1_CNTr = 3195,
+	SE_AS_SMMU0_AS_MAC_AGE_FC_CNTr = 3196,
+	SE_AS_ALG_LEARN_FC_CNTr = 3197,
+	SE_AS_SMMU1_AS_FC_CNTr = 3198,
+	SE_AS_CFG_SE_MAC_FC_CNTr = 3199,
+	SE_KSCHD_KSCHD_CPU_RDYr = 3200,
+	SE_KSCHD_PPU0_ECC_BYPASS_READr = 3201,
+	SE_KSCHD_PBU_ECC_BYPASS_READr = 3202,
+	SE_KSCHD_SMMU1_ECC_BYPASS_READr = 3203,
+	SE_KSCHD_ASS_ECC_BYPASS_READr = 3204,
+	SE_KSCHD_SDT_Hr = 3205,
+	SE_KSCHD_SDT_Lr = 3206,
+	SE_KSCHD_HASH_KEY15r = 3207,
+	SE_KSCHD_HASH_KEY14r = 3208,
+	SE_KSCHD_HASH_KEY13r = 3209,
+	SE_KSCHD_HASH_KEY12r = 3210,
+	SE_KSCHD_HASH_KEY11r = 3211,
+	SE_KSCHD_HASH_KEY10r = 3212,
+	SE_KSCHD_HASH_KEY9r = 3213,
+	SE_KSCHD_HASH_KEY8r = 3214,
+	SE_KSCHD_HASH_KEY7r = 3215,
+	SE_KSCHD_HASH_KEY6r = 3216,
+	SE_KSCHD_HASH_KEY5r = 3217,
+	SE_KSCHD_HASH_KEY4r = 3218,
+	SE_KSCHD_HASH_KEY3r = 3219,
+	SE_KSCHD_HASH_KEY2r = 3220,
+	SE_KSCHD_HASH_KEY1r = 3221,
+	SE_KSCHD_HASH_KEY0r = 3222,
+	SE_KSCHD_SCHD_INT_0_ENr = 3223,
+	SE_KSCHD_SCHD_INT_0_MASKr = 3224,
+	SE_KSCHD_SCHD_INT_1_ENr = 3225,
+	SE_KSCHD_SCHD_INT_1_MASKr = 3226,
+	SE_KSCHD_SCHD_INT_2_ENr = 3227,
+	SE_KSCHD_SCHD_INT_2_MASKr = 3228,
+	SE_KSCHD_SCHD_INT_3_ENr = 3229,
+	SE_KSCHD_SCHD_INT_3_MASKr = 3230,
+	SE_KSCHD_SCHD_INT_4_ENr = 3231,
+	SE_KSCHD_SCHD_INT_4_MASKr = 3232,
+	SE_KSCHD_SCHD_INT_0_STATUSr = 3233,
+	SE_KSCHD_SCHD_INT_1_STATUSr = 3234,
+	SE_KSCHD_SCHD_INT_2_STATUSr = 3235,
+	SE_KSCHD_SCHD_INT_3_STATUSr = 3236,
+	SE_KSCHD_SCHD_INT_4_STATUSr = 3237,
+	SE_KSCHD_SE_KSCHD_INT_STATUSr = 3238,
+	SE_KSCHD_DEBUG_CNT_MODEr = 3239,
+	SE_KSCHD_SE_PARSER_KSCHD_KEY0_3_CNTr = 3240,
+	SE_KSCHD_SE_SMMU1_KEY0_3_CNTr = 3241,
+	SE_KSCHD_KSCHD_AS_KEY0_CNTr = 3242,
+	SE_KSCHD_KSCHD_AS_KEY1_CNTr = 3243,
+	SE_KSCHD_KSCHD_AS_KEY2_CNTr = 3244,
+	SE_KSCHD_KSCHD_AS_KEY3_CNTr = 3245,
+	SE_KSCHD_KSCHD_AS_KEY4_CNTr = 3246,
+	SE_KSCHD_KSCHD_AS_KEY5_CNTr = 3247,
+	SE_KSCHD_KSCHD_AS_KEY6_CNTr = 3248,
+	SE_KSCHD_KSCHD_AS_KEY9_CNTr = 3249,
+	SE_KSCHD_KSCHD_SE_PARSER_FC0_3_CNTr = 3250,
+	SE_KSCHD_SMMU1_SE_FC0_3_CNTr = 3251,
+	SE_KSCHD_AS_KSCHD_FC_CNT0r = 3252,
+	SE_KSCHD_AS_KSCHD_FC_CNT1r = 3253,
+	SE_KSCHD_AS_KSCHD_FC_CNT2r = 3254,
+	SE_KSCHD_AS_KSCHD_FC_CNT3r = 3255,
+	SE_KSCHD_AS_KSCHD_FC_CNT4r = 3256,
+	SE_KSCHD_AS_KSCHD_FC_CNT5r = 3257,
+	SE_KSCHD_AS_KSCHD_FC_CNT6r = 3258,
+	SE_KSCHD_AS_KSCHD_FC_CNT9r = 3259,
+	SE_RSCHD_RSCHD_HASH_PFUL_CFGr = 3260,
+	SE_RSCHD_RSCHD_HASH_EPT_CFGr = 3261,
+	SE_RSCHD_RSCHD_PBU_PFUL_CFGr = 3262,
+	SE_RSCHD_RSCHD_PBU_EPT_CFGr = 3263,
+	SE_RSCHD_RSCHD_LPM_PFUL_CFGr = 3264,
+	SE_RSCHD_RSCHD_LPM_EPT_CFGr = 3265,
+	SE_RSCHD_RSCHD_ETCAM_PFUL_CFGr = 3266,
+	SE_RSCHD_RSCHD_ETCAM_EPT_CFGr = 3267,
+	SE_RSCHD_SMMU0_WB_PFUL_CFGr = 3268,
+	SE_RSCHD_SMMU0_WB_EPT_CFGr = 3269,
+	SE_RSCHD_SMMU1_WB_PFUL_CFGr = 3270,
+	SE_RSCHD_SMMU1_WB_EPT_CFGr = 3271,
+	SE_RSCHD_ALG_WB_PFUL_CFGr = 3272,
+	SE_RSCHD_ALG_WB_EPT_CFGr = 3273,
+	SE_RSCHD_WR_RSP_VLD_ENr = 3274,
+	SE_RSCHD_NPPU_WB_PFUL_CFGr = 3275,
+	SE_RSCHD_NPPU_WB_EPT_CFGr = 3276,
+	SE_RSCHD_PORT0_INT_ENr = 3277,
+	SE_RSCHD_PORT0_INT_MASKr = 3278,
+	SE_RSCHD_PORT1_INT_ENr = 3279,
+	SE_RSCHD_PORT1_INT_MASKr = 3280,
+	SE_RSCHD_PORT0_INT_STATUSr = 3281,
+	SE_RSCHD_PORT1_INT_STATUSr = 3282,
+	SE_RSCHD_SE_RSCHD_INT_STATUSr = 3283,
+	SE_RSCHD_DEBUG_CNT_MODEr = 3284,
+	SE_RSCHD_SE_PPU_MEX0_5_RSP1_CNTr = 3285,
+	SE_RSCHD_AS_RSCHD_RSP0_CNTr = 3286,
+	SE_RSCHD_AS_RSCHD_RSP1_CNTr = 3287,
+	SE_RSCHD_AS_RSCHD_RSP2_CNTr = 3288,
+	SE_RSCHD_AS_RSCHD_RSP3_CNTr = 3289,
+	SE_RSCHD_AS_RSCHD_RSP4_CNTr = 3290,
+	SE_RSCHD_AS_RSCHD_RSP5_CNTr = 3291,
+	SE_RSCHD_AS_RSCHD_RSP6_CNTr = 3292,
+	SE_RSCHD_AS_RSCHD_RSP9_CNTr = 3293,
+	SE_RSCHD_SMMU1_SE_RSP0_3_CNTr = 3294,
+	SE_RSCHD_PPU_SE_MEX0_3_FC_CNTr = 3295,
+	SE_RSCHD_RSCHD_AS_FC_CNT0r = 3296,
+	SE_RSCHD_RSCHD_AS_FC_CNT1r = 3297,
+	SE_RSCHD_RSCHD_AS_FC_CNT2r = 3298,
+	SE_RSCHD_RSCHD_AS_FC_CNT3r = 3299,
+	SE_RSCHD_RSCHD_AS_FC_CNT4r = 3300,
+	SE_RSCHD_RSCHD_AS_FC_CNT5r = 3301,
+	SE_RSCHD_RSCHD_AS_FC_CNT6r = 3302,
+	SE_RSCHD_RSCHD_AS_FC_CNT9r = 3303,
+	SE_RSCHD_SE_SMMU1_FC0_3_CNTr = 3304,
+	SE_RSCHD_SMMU0_SE_WR_DONE_CNTr = 3305,
+	SE_RSCHD_SE_SMMU0_WR_DONE_FC_CNTr = 3306,
+	SE_RSCHD_SMMU1_SE_WR_RSP_CNTr = 3307,
+	SE_RSCHD_SE_SMMU1_WR_RSP_FC_CNTr = 3308,
+	SE_RSCHD_ALG_SE_WR_RSP_CNTr = 3309,
+	SE_RSCHD_SE_ALG_WR_RSP_FC_CNTr = 3310,
+	SMMU0_SMMU0_KSCHD_PFUL_CFG0r = 3311,
+	SMMU0_SMMU0_KSCHD_PFUL_CFG1r = 3312,
+	SMMU0_SMMU0_CTRL_PFUL1_CFGr = 3313,
+	SMMU0_SMMU0_CTRL_PFUL2_CFGr = 3314,
+	SMMU0_SMMU0_CTRL_PFUL3_CFGr = 3315,
+	SMMU0_SMMU0_RSCHD_PFUL_CFGr = 3316,
+	SMMU0_SMMU0_RSCHD_EPT_CFGr = 3317,
+	SMMU0_SMMU0_ALUCMD_PFUL_CFGr = 3318,
+	SMMU0_SMMU0_ALUWR_PFUL_CFGr = 3319,
+	SMMU0_SMMU0_WR_ARB_PFUL_CFG0r = 3320,
+	SMMU0_SMMU0_WR_ARB_PFUL_CFG1r = 3321,
+	SMMU0_SMMU0_ORD_PFUL_CFGr = 3322,
+	SMMU0_SMMU0_CFG_DMA_BADDRr = 3323,
+	SMMU0_SMMU0_CFG_ODMA0_BADDRr = 3324,
+	SMMU0_SMMU0_CFG_ODMA1_BADDRr = 3325,
+	SMMU0_SMMU0_CFG_ODMA2_BADDRr = 3326,
+	SMMU0_SMMU0_CFG_ODMA_TDM_BADDRr = 3327,
+	SMMU0_SMMU0_CFG_MCAST_BADDRr = 3328,
+	SMMU0_SMMU0_CFG_LPM0r = 3329,
+	SMMU0_SMMU0_CFG_LPM1r = 3330,
+	SMMU0_SMMU0_CFG_LPM2r = 3331,
+	SMMU0_SMMU0_CFG_LPM3r = 3332,
+	SMMU0_SMMU0_CFG_LPM4r = 3333,
+	SMMU0_SMMU0_CFG_LPM5r = 3334,
+	SMMU0_SMMU0_CFG_LPM6r = 3335,
+	SMMU0_SMMU0_CFG_LPM7r = 3336,
+	SMMU0_SMMU0_DEBUG_CNT_MODEr = 3337,
+	SMMU0_SMMU0_STAT_OVERFLOW_MODEr = 3338,
+	SMMU0_SMMU0_INIT_EN_CFG_TMPr = 3339,
+	SMMU0_SMMU0_SMMU0_INT_UNMASK_FLAGr = 3340,
+	SMMU0_SMMU0_SMMU0_INT0_ENr = 3341,
+	SMMU0_SMMU0_SMMU0_INT0_MASKr = 3342,
+	SMMU0_SMMU0_SMMU0_INT0_STATUSr = 3343,
+	SMMU0_SMMU0_SMMU0_INT1_ENr = 3344,
+	SMMU0_SMMU0_SMMU0_INT1_MASKr = 3345,
+	SMMU0_SMMU0_SMMU0_INT1_STATUSr = 3346,
+	SMMU0_SMMU0_SMMU0_INT2_ENr = 3347,
+	SMMU0_SMMU0_SMMU0_INT2_MASKr = 3348,
+	SMMU0_SMMU0_SMMU0_INT2_STATUSr = 3349,
+	SMMU0_SMMU0_SMMU0_INT3_ENr = 3350,
+	SMMU0_SMMU0_SMMU0_INT3_MASKr = 3351,
+	SMMU0_SMMU0_SMMU0_INT3_STATUSr = 3352,
+	SMMU0_SMMU0_SMMU0_INT4_ENr = 3353,
+	SMMU0_SMMU0_SMMU0_INT4_MASKr = 3354,
+	SMMU0_SMMU0_SMMU0_INT4_STATUSr = 3355,
+	SMMU0_SMMU0_SMMU0_INT5_ENr = 3356,
+	SMMU0_SMMU0_SMMU0_INT5_MASKr = 3357,
+	SMMU0_SMMU0_SMMU0_INT5_STATUSr = 3358,
+	SMMU0_SMMU0_SMMU0_INT6_ENr = 3359,
+	SMMU0_SMMU0_SMMU0_INT6_MASKr = 3360,
+	SMMU0_SMMU0_SMMU0_INT6_STATUSr = 3361,
+	SMMU0_SMMU0_SMMU0_INT7_ENr = 3362,
+	SMMU0_SMMU0_SMMU0_INT7_MASKr = 3363,
+	SMMU0_SMMU0_SMMU0_INT7_STATUSr = 3364,
+	SMMU0_SMMU0_SMMU0_INT8_ENr = 3365,
+	SMMU0_SMMU0_SMMU0_INT8_MASKr = 3366,
+	SMMU0_SMMU0_SMMU0_INT8_STATUSr = 3367,
+	SMMU0_SMMU0_SMMU0_INT9_ENr = 3368,
+	SMMU0_SMMU0_SMMU0_INT9_MASKr = 3369,
+	SMMU0_SMMU0_SMMU0_INT9_STATUSr = 3370,
+	SMMU0_SMMU0_SMMU0_INT10_ENr = 3371,
+	SMMU0_SMMU0_SMMU0_INT10_MASKr = 3372,
+	SMMU0_SMMU0_SMMU0_INT10_STATUSr = 3373,
+	SMMU0_SMMU0_SMMU0_INT11_ENr = 3374,
+	SMMU0_SMMU0_SMMU0_INT11_MASKr = 3375,
+	SMMU0_SMMU0_SMMU0_INT11_STATUSr = 3376,
+	SMMU0_SMMU0_SMMU0_INT12_ENr = 3377,
+	SMMU0_SMMU0_SMMU0_INT12_MASKr = 3378,
+	SMMU0_SMMU0_SMMU0_INT12_STATUSr = 3379,
+	SMMU0_SMMU0_SMMU0_INT13_ENr = 3380,
+	SMMU0_SMMU0_SMMU0_INT13_MASKr = 3381,
+	SMMU0_SMMU0_SMMU0_INT13_STATUSr = 3382,
+	SMMU0_SMMU0_SMMU0_INT14_ENr = 3383,
+	SMMU0_SMMU0_SMMU0_INT14_MASKr = 3384,
+	SMMU0_SMMU0_SMMU0_INT14_STATUSr = 3385,
+	SMMU0_SMMU0_SMMU0_ECC_UNMASK_FLAGr = 3386,
+	SMMU0_SMMU0_SMMU0_INT15_ENr = 3387,
+	SMMU0_SMMU0_SMMU0_INT15_MASKr = 3388,
+	SMMU0_SMMU0_SMMU0_INT15_STATUSr = 3389,
+	SMMU0_SMMU0_SMMU0_INT16_ENr = 3390,
+	SMMU0_SMMU0_SMMU0_INT16_MASKr = 3391,
+	SMMU0_SMMU0_SMMU0_INT16_STATUSr = 3392,
+	SMMU0_SMMU0_SMMU0_INT17_ENr = 3393,
+	SMMU0_SMMU0_SMMU0_INT17_MASKr = 3394,
+	SMMU0_SMMU0_SMMU0_INT17_STATUSr = 3395,
+	SMMU0_SMMU0_SMMU0_INT18_ENr = 3396,
+	SMMU0_SMMU0_SMMU0_INT18_MASKr = 3397,
+	SMMU0_SMMU0_SMMU0_INT18_STATUSr = 3398,
+	SMMU0_SMMU0_SMMU0_INT19_ENr = 3399,
+	SMMU0_SMMU0_SMMU0_INT19_MASKr = 3400,
+	SMMU0_SMMU0_SMMU0_INT19_STATUSr = 3401,
+	SMMU0_SMMU0_SMMU0_INT20_ENr = 3402,
+	SMMU0_SMMU0_SMMU0_INT20_MASKr = 3403,
+	SMMU0_SMMU0_SMMU0_INT20_STATUSr = 3404,
+	SMMU0_SMMU0_SMMU0_INT21_ENr = 3405,
+	SMMU0_SMMU0_SMMU0_INT21_MASKr = 3406,
+	SMMU0_SMMU0_SMMU0_INT21_STATUSr = 3407,
+	SMMU0_SMMU0_SMMU0_INT22_ENr = 3408,
+	SMMU0_SMMU0_SMMU0_INT22_MASKr = 3409,
+	SMMU0_SMMU0_SMMU0_INT22_STATUSr = 3410,
+	SMMU0_SMMU0_SMMU0_INT23_ENr = 3411,
+	SMMU0_SMMU0_SMMU0_INT23_MASKr = 3412,
+	SMMU0_SMMU0_SMMU0_INT23_STATUSr = 3413,
+	SMMU0_SMMU0_SMMU0_INT24_ENr = 3414,
+	SMMU0_SMMU0_SMMU0_INT24_MASKr = 3415,
+	SMMU0_SMMU0_SMMU0_INT24_STATUSr = 3416,
+	SMMU0_SMMU0_SMMU0_INT25_ENr = 3417,
+	SMMU0_SMMU0_SMMU0_INT25_MASKr = 3418,
+	SMMU0_SMMU0_SMMU0_INT25_STATUSr = 3419,
+	SMMU0_SMMU0_SMMU0_INT26_ENr = 3420,
+	SMMU0_SMMU0_SMMU0_INT26_MASKr = 3421,
+	SMMU0_SMMU0_SMMU0_INT26_STATUSr = 3422,
+	SMMU0_SMMU0_SMMU0_INT27_ENr = 3423,
+	SMMU0_SMMU0_SMMU0_INT27_MASKr = 3424,
+	SMMU0_SMMU0_SMMU0_INT27_STATUSr = 3425,
+	SMMU0_SMMU0_SMMU0_INT28_ENr = 3426,
+	SMMU0_SMMU0_SMMU0_INT28_MASKr = 3427,
+	SMMU0_SMMU0_SMMU0_INT28_STATUSr = 3428,
+	SMMU0_SMMU0_SMMU0_INT29_ENr = 3429,
+	SMMU0_SMMU0_SMMU0_INT29_MASKr = 3430,
+	SMMU0_SMMU0_SMMU0_INT29_STATUSr = 3431,
+	SMMU0_SMMU0_SMMU0_INT30_ENr = 3432,
+	SMMU0_SMMU0_SMMU0_INT30_MASKr = 3433,
+	SMMU0_SMMU0_SMMU0_INT30_STATUSr = 3434,
+	SMMU0_SMMU0_SMMU0_INT31_ENr = 3435,
+	SMMU0_SMMU0_SMMU0_INT31_MASKr = 3436,
+	SMMU0_SMMU0_SMMU0_INT31_STATUSr = 3437,
+	SMMU0_SMMU0_SMMU0_INT32_ENr = 3438,
+	SMMU0_SMMU0_SMMU0_INT32_MASKr = 3439,
+	SMMU0_SMMU0_SMMU0_INT32_STATUSr = 3440,
+	SMMU0_SMMU0_SMMU0_INT33_ENr = 3441,
+	SMMU0_SMMU0_SMMU0_INT33_MASKr = 3442,
+	SMMU0_SMMU0_SMMU0_INT33_STATUSr = 3443,
+	SMMU0_SMMU0_SMMU0_INT34_ENr = 3444,
+	SMMU0_SMMU0_SMMU0_INT34_MASKr = 3445,
+	SMMU0_SMMU0_SMMU0_INT34_STATUSr = 3446,
+	SMMU0_SMMU0_SMMU0_INT35_ENr = 3447,
+	SMMU0_SMMU0_SMMU0_INT35_MASKr = 3448,
+	SMMU0_SMMU0_SMMU0_INT35_STATUSr = 3449,
+	SMMU0_SMMU0_SMMU0_INT36_ENr = 3450,
+	SMMU0_SMMU0_SMMU0_INT36_MASKr = 3451,
+	SMMU0_SMMU0_SMMU0_INT36_STATUSr = 3452,
+	SMMU0_SMMU0_SMMU0_INT37_ENr = 3453,
+	SMMU0_SMMU0_SMMU0_INT37_MASKr = 3454,
+	SMMU0_SMMU0_SMMU0_INT37_STATUSr = 3455,
+	SMMU0_SMMU0_SMMU0_INT38_ENr = 3456,
+	SMMU0_SMMU0_SMMU0_INT38_MASKr = 3457,
+	SMMU0_SMMU0_SMMU0_INT38_STATUSr = 3458,
+	SMMU0_SMMU0_SMMU0_INT39_ENr = 3459,
+	SMMU0_SMMU0_SMMU0_INT39_MASKr = 3460,
+	SMMU0_SMMU0_SMMU0_INT39_STATUSr = 3461,
+	SMMU0_SMMU0_SMMU0_INT40_ENr = 3462,
+	SMMU0_SMMU0_SMMU0_INT40_MASKr = 3463,
+	SMMU0_SMMU0_SMMU0_INT40_STATUSr = 3464,
+	SMMU0_SMMU0_SMMU0_INT41_ENr = 3465,
+	SMMU0_SMMU0_SMMU0_INT41_MASKr = 3466,
+	SMMU0_SMMU0_SMMU0_INT41_STATUSr = 3467,
+	SMMU0_SMMU0_SMMU0_INT42_ENr = 3468,
+	SMMU0_SMMU0_SMMU0_INT42_MASKr = 3469,
+	SMMU0_SMMU0_SMMU0_INT42_STATUSr = 3470,
+	SMMU0_SMMU0_SMMU0_INT43_ENr = 3471,
+	SMMU0_SMMU0_SMMU0_INT43_MASKr = 3472,
+	SMMU0_SMMU0_SMMU0_INT43_STATUSr = 3473,
+	SMMU0_SMMU0_SMMU0_INT44_ENr = 3474,
+	SMMU0_SMMU0_SMMU0_INT44_MASKr = 3475,
+	SMMU0_SMMU0_SMMU0_INT44_STATUSr = 3476,
+	SMMU0_SMMU0_SMMU0_INT45_ENr = 3477,
+	SMMU0_SMMU0_SMMU0_INT45_MASKr = 3478,
+	SMMU0_SMMU0_SMMU0_INT45_STATUSr = 3479,
+	SMMU0_SMMU0_SMMU0_INT46_ENr = 3480,
+	SMMU0_SMMU0_SMMU0_INT46_MASKr = 3481,
+	SMMU0_SMMU0_SMMU0_INT46_STATUSr = 3482,
+	SMMU0_SMMU0_SMMU0_INT47_ENr = 3483,
+	SMMU0_SMMU0_SMMU0_INT47_MASKr = 3484,
+	SMMU0_SMMU0_SMMU0_INT47_STATUSr = 3485,
+	SMMU0_SMMU0_SMMU0_INT48_ENr = 3486,
+	SMMU0_SMMU0_SMMU0_INT48_MASKr = 3487,
+	SMMU0_SMMU0_SMMU0_INT48_STATUSr = 3488,
+	SMMU0_SMMU0_SMMU0_INT49_ENr = 3489,
+	SMMU0_SMMU0_SMMU0_INT49_MASKr = 3490,
+	SMMU0_SMMU0_SMMU0_INT49_STATUSr = 3491,
+	SMMU0_SMMU0_SMMU0_INT50_ENr = 3492,
+	SMMU0_SMMU0_SMMU0_INT50_MASKr = 3493,
+	SMMU0_SMMU0_SMMU0_INT50_STATUSr = 3494,
+	SMMU0_SMMU0_SMMU0_INT51_ENr = 3495,
+	SMMU0_SMMU0_SMMU0_INT51_MASKr = 3496,
+	SMMU0_SMMU0_SMMU0_INT51_STATUSr = 3497,
+	SMMU0_SMMU0_SMMU0_INT52_ENr = 3498,
+	SMMU0_SMMU0_SMMU0_INT52_MASKr = 3499,
+	SMMU0_SMMU0_SMMU0_INT52_STATUSr = 3500,
+	SMMU0_SMMU0_SMMU0_INT53_ENr = 3501,
+	SMMU0_SMMU0_SMMU0_INT53_MASKr = 3502,
+	SMMU0_SMMU0_SMMU0_INT53_STATUSr = 3503,
+	SMMU0_SMMU0_CTRL0_ARBITER_ECC_BYPASSr = 3504,
+	SMMU0_SMMU0_CTRL2_ARBITER_ECC_BYPASSr = 3505,
+	SMMU0_SMMU0_CTRL4_ARBITER_ECC_BYPASSr = 3506,
+	SMMU0_SMMU0_CTRL6_ARBITER_ECC_BYPASSr = 3507,
+	SMMU0_SMMU0_CTRL8_ARBITER_ECC_BYPASSr = 3508,
+	SMMU0_SMMU0_CTRL10_ARBITER_ECC_BYPASSr = 3509,
+	SMMU0_SMMU0_CTRL12_ARBITER_ECC_BYPASSr = 3510,
+	SMMU0_SMMU0_CTRL14_ARBITER_ECC_BYPASSr = 3511,
+	SMMU0_SMMU0_CTRL16_ARBITER_ECC_BYPASSr = 3512,
+	SMMU0_SMMU0_CTRL18_ARBITER_ECC_BYPASSr = 3513,
+	SMMU0_SMMU0_CTRL20_ARBITER_ECC_BYPASSr = 3514,
+	SMMU0_SMMU0_CTRL22_ARBITER_ECC_BYPASSr = 3515,
+	SMMU0_SMMU0_CTRL24_ARBITER_ECC_BYPASSr = 3516,
+	SMMU0_SMMU0_CTRL26_ARBITER_ECC_BYPASSr = 3517,
+	SMMU0_SMMU0_CTRL28_ARBITER_ECC_BYPASSr = 3518,
+	SMMU0_SMMU0_CTRL30_ARBITER_ECC_BYPASSr = 3519,
+	SMMU0_SMMU0_CTRL_REQ_ECC_BYPASSr = 3520,
+	SMMU0_SMMU0_CTRL_INFO_ECC_BYPASSr = 3521,
+	SMMU0_SMMU0_SMMU0_RSCHD_ECC_BYPASSr = 3522,
+	SMMU0_SMMU0_SMMU0_WR_ECC_BYPASSr = 3523,
+	SMMU0_SMMU0_CTRL0_ARBITER_ECC_ERRr = 3524,
+	SMMU0_SMMU0_CTRL1_ARBITER_ECC_ERRr = 3525,
+	SMMU0_SMMU0_CTRL2_ARBITER_ECC_ERRr = 3526,
+	SMMU0_SMMU0_CTRL3_ARBITER_ECC_ERRr = 3527,
+	SMMU0_SMMU0_CTRL4_ARBITER_ECC_ERRr = 3528,
+	SMMU0_SMMU0_CTRL5_ARBITER_ECC_ERRr = 3529,
+	SMMU0_SMMU0_CTRL6_ARBITER_ECC_ERRr = 3530,
+	SMMU0_SMMU0_CTRL7_ARBITER_ECC_ERRr = 3531,
+	SMMU0_SMMU0_CTRL8_ARBITER_ECC_ERRr = 3532,
+	SMMU0_SMMU0_CTRL9_ARBITER_ECC_ERRr = 3533,
+	SMMU0_SMMU0_CTRL10_ARBITER_ECC_ERRr = 3534,
+	SMMU0_SMMU0_CTRL11_ARBITER_ECC_ERRr = 3535,
+	SMMU0_SMMU0_CTRL12_ARBITER_ECC_ERRr = 3536,
+	SMMU0_SMMU0_CTRL13_ARBITER_ECC_ERRr = 3537,
+	SMMU0_SMMU0_CTRL14_ARBITER_ECC_ERRr = 3538,
+	SMMU0_SMMU0_CTRL15_ARBITER_ECC_ERRr = 3539,
+	SMMU0_SMMU0_CTRL16_ARBITER_ECC_ERRr = 3540,
+	SMMU0_SMMU0_CTRL17_ARBITER_ECC_ERRr = 3541,
+	SMMU0_SMMU0_CTRL18_ARBITER_ECC_ERRr = 3542,
+	SMMU0_SMMU0_CTRL19_ARBITER_ECC_ERRr = 3543,
+	SMMU0_SMMU0_CTRL20_ARBITER_ECC_ERRr = 3544,
+	SMMU0_SMMU0_CTRL21_ARBITER_ECC_ERRr = 3545,
+	SMMU0_SMMU0_CTRL22_ARBITER_ECC_ERRr = 3546,
+	SMMU0_SMMU0_CTRL23_ARBITER_ECC_ERRr = 3547,
+	SMMU0_SMMU0_CTRL24_ARBITER_ECC_ERRr = 3548,
+	SMMU0_SMMU0_CTRL25_ARBITER_ECC_ERRr = 3549,
+	SMMU0_SMMU0_CTRL26_ARBITER_ECC_ERRr = 3550,
+	SMMU0_SMMU0_CTRL27_ARBITER_ECC_ERRr = 3551,
+	SMMU0_SMMU0_CTRL28_ARBITER_ECC_ERRr = 3552,
+	SMMU0_SMMU0_CTRL29_ARBITER_ECC_ERRr = 3553,
+	SMMU0_SMMU0_CTRL30_ARBITER_ECC_ERRr = 3554,
+	SMMU0_SMMU0_CTRL31_ARBITER_ECC_ERRr = 3555,
+	SMMU0_SMMU0_CTRL_REQ_ECC_SINGLE_ERRr = 3556,
+	SMMU0_SMMU0_CTRL_REQ_ECC_DOUBLE_ERRr = 3557,
+	SMMU0_SMMU0_CTRL_INFO_ECC_SINGLE_ERRr = 3558,
+	SMMU0_SMMU0_CTRL_INFO_ECC_DOUBLE_ERRr = 3559,
+	SMMU0_SMMU0_SMMU0_WR_ECC_ERRr = 3560,
+	SMMU0_SMMU0_SMMU0_RSCHD_ECC_SINGLE_ERRr = 3561,
+	SMMU0_SMMU0_SMMU0_RSCHD_ECC_DOUBLE_ERRr = 3562,
+	SMMU0_SMMU0_ORD_FIFO_EMPTYr = 3563,
+	SMMU0_SMMU0_WR_ARB_FIFO_EMPTYr = 3564,
+	SMMU0_SMMU0_CTRL_FIFO_EMPTY0r = 3565,
+	SMMU0_SMMU0_CTRL_FIFO_EMPTY1r = 3566,
+	SMMU0_SMMU0_CTRL_FIFO_EMPTY2r = 3567,
+	SMMU0_SMMU0_CTRL_FIFO_EMPTY3r = 3568,
+	SMMU0_SMMU0_CTRL_FIFO_EMPTY4r = 3569,
+	SMMU0_SMMU0_CTRL_FIFO_EMPTY5r = 3570,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY0r = 3571,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY1r = 3572,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY2r = 3573,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY3r = 3574,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY4r = 3575,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY5r = 3576,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY6r = 3577,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY7r = 3578,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY8r = 3579,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY9r = 3580,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY10r = 3581,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY11r = 3582,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY12r = 3583,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY13r = 3584,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY14r = 3585,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY15r = 3586,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY16r = 3587,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY17r = 3588,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY18r = 3589,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY19r = 3590,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY20r = 3591,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY21r = 3592,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY22r = 3593,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY23r = 3594,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY24r = 3595,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY25r = 3596,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY26r = 3597,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY27r = 3598,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY28r = 3599,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY29r = 3600,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY30r = 3601,
+	SMMU0_SMMU0_KSCHD_FIFO_EMPTY31r = 3602,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY0r = 3603,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY1r = 3604,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY2r = 3605,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY3r = 3606,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY4r = 3607,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY5r = 3608,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY6r = 3609,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY7r = 3610,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY8r = 3611,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY9r = 3612,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY10r = 3613,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY11r = 3614,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY12r = 3615,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY13r = 3616,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY14r = 3617,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY15r = 3618,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY16r = 3619,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY17r = 3620,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY18r = 3621,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY19r = 3622,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY20r = 3623,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY21r = 3624,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY22r = 3625,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY23r = 3626,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY24r = 3627,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY25r = 3628,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY26r = 3629,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY27r = 3630,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY28r = 3631,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY29r = 3632,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY30r = 3633,
+	SMMU0_SMMU0_RSCHD_FIFO_EMPTY31r = 3634,
+	SMMU0_SMMU0_EPT_FLAGr = 3635,
+	SMMU0_SMMU0_PPU_SOFT_RSTr = 3636,
+	SMMU0_SMMU0_SMMU0_AS_MAC_AGE_FC_CNTr = 3637,
+	SMMU0_SMMU0_SMMU0_MARC_SE_PARSER_FC_CNTr = 3638,
+	SMMU0_SMMU0_WR_ARB_CPU_FC_CNTr = 3639,
+	SMMU0_SMMU0_SMMU0_LPM_AS_FC_CNTr = 3640,
+	SMMU0_SMMU0_LPM_AS_SMMU0_FC_CNTr = 3641,
+	SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_FC_CNTr = 3642,
+	SMMU0_SMMU0_AS_ETCAM1_0_SMMU0_FC_CNTr = 3643,
+	SMMU0_SMMU0_SMMU0_PPU_MCAST_FC_CNTr = 3644,
+	SMMU0_SMMU0_PPU_SMMU0_MCAST_FC_CNTr = 3645,
+	SMMU0_SMMU0_ODMA_SMMU0_TDM_FC_RSP_FC_CNTr = 3646,
+	SMMU0_SMMU0_SMMU0_ODMA_TDM_FC_KEY_FC_CNTr = 3647,
+	SMMU0_SMMU0_SMMU0_ODMA_FC_CNTr = 3648,
+	SMMU0_SMMU0_SMMU0_CFG_TAB_RD_FC_CNTr = 3649,
+	SMMU0_SMMU0_SMMU0_STAT_FC15_0_CNTr = 3650,
+	SMMU0_SMMU0_STAT_SMMU0_FC15_0_CNTr = 3651,
+	SMMU0_SMMU0_SMMU0_PPU_MEX5_0_FC_CNTr = 3652,
+	SMMU0_SMMU0_PPU_SMMU0_MEX5_0_FC_CNTr = 3653,
+	SMMU0_SMMU0_AS_SMMU0_MAC_AGE_REQ_CNTr = 3654,
+	SMMU0_SMMU0_SE_PARSER_SMMU0_MARC_KEY_CNTr = 3655,
+	SMMU0_SMMU0_CPU_IND_RDAT_CNTr = 3656,
+	SMMU0_SMMU0_CPU_IND_RD_REQ_CNTr = 3657,
+	SMMU0_SMMU0_CPU_IND_WR_REQ_CNTr = 3658,
+	SMMU0_SMMU0_SMMU0_PLCR_RSP0_CNTr = 3659,
+	SMMU0_SMMU0_PLCR_SMMU0_REQ0_CNTr = 3660,
+	SMMU0_SMMU0_SMMU0_LPM_AS_RSP_CNTr = 3661,
+	SMMU0_SMMU0_LPM_AS_SMMU0_REQ_CNTr = 3662,
+	SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_RSP_CNTr = 3663,
+	SMMU0_SMMU0_ETCAM1_0_AS_SMMU0_REQ_CNTr = 3664,
+	SMMU0_SMMU0_SMMU0_PPU_MCAST_RSP_CNTr = 3665,
+	SMMU0_SMMU0_PPU_SMMU0_MCAST_KEY_CNTr = 3666,
+	SMMU0_SMMU0_SMMU0_ODMA_TDM_MC_RSP_CNTr = 3667,
+	SMMU0_SMMU0_ODMA_SMMU0_TDM_MC_KEY_CNTr = 3668,
+	SMMU0_SMMU0_SMMU0_ODMA_RSP_CNTr = 3669,
+	SMMU0_SMMU0_ODMA_SMMU0_CMD_CNTr = 3670,
+	SMMU0_SMMU0_SMMU0_CFG_TAB_RDAT_CNTr = 3671,
+	SMMU0_SMMU0_CFG_SMMU0_TAB_RD_CNTr = 3672,
+	SMMU0_SMMU0_SMMU0_STAT_RSP15_0_CNTr = 3673,
+	SMMU0_SMMU0_STAT_SMMU0_REQ15_0_CNTr = 3674,
+	SMMU0_SMMU0_SMMU0_PPU_MEX5_0_RSP_CNTr = 3675,
+	SMMU0_SMMU0_PPU_SMMU0_MEX5_0_KEY_CNTr = 3676,
+	SMMU0_SMMU0_FTM_STAT_SMMU0_REQ0_CNTr = 3677,
+	SMMU0_SMMU0_FTM_STAT_SMMU0_REQ1_CNTr = 3678,
+	SMMU0_SMMU0_ETM_STAT_SMMU0_REQ0_CNTr = 3679,
+	SMMU0_SMMU0_ETM_STAT_SMMU0_REQ1_CNTr = 3680,
+	SMMU0_SMMU0_REQ_ERAM0_31_RD_CNTr = 3681,
+	SMMU0_SMMU0_REQ_ERAM0_31_WR_CNTr = 3682,
+	SE_SMMU1_DDR_WDAT1r = 3683,
+	SE_SMMU1_DDR_WDAT2r = 3684,
+	SE_SMMU1_DDR_WDAT3r = 3685,
+	SE_SMMU1_DDR_WDAT4r = 3686,
+	SE_SMMU1_DDR_WDAT5r = 3687,
+	SE_SMMU1_DDR_WDAT6r = 3688,
+	SE_SMMU1_DDR_WDAT7r = 3689,
+	SE_SMMU1_DDR_WDAT8r = 3690,
+	SE_SMMU1_DDR_WDAT9r = 3691,
+	SE_SMMU1_DDR_WDAT10r = 3692,
+	SE_SMMU1_DDR_WDAT11r = 3693,
+	SE_SMMU1_DDR_WDAT12r = 3694,
+	SE_SMMU1_DDR_WDAT13r = 3695,
+	SE_SMMU1_DDR_WDAT14r = 3696,
+	SE_SMMU1_DDR_WDAT15r = 3697,
+	SE_SMMU1_CNT_STAT_CACHE_ENr = 3698,
+	SE_SMMU1_CNT_STAT_CACHE_CLRr = 3699,
+	SE_SMMU1_CNT_STAT_CACHE_REQ_63_32r = 3700,
+	SE_SMMU1_CNT_STAT_CACHE_REQ_31_0r = 3701,
+	SE_SMMU1_CNT_STAT_CACHE_HIT_63_32r = 3702,
+	SE_SMMU1_CNT_STAT_CACHE_HIT_31_0r = 3703,
+	SE_SMMU1_DDR_CMD0r = 3704,
+	SE_SMMU1_INFO_ADDRr = 3705,
+	SE_SMMU1_DDR_CMD1r = 3706,
+	SE_SMMU1_CLR_START_ADDRr = 3707,
+	SE_SMMU1_CLR_END_ADDRr = 3708,
+	SE_SMMU1_CLR_TBL_ENr = 3709,
+	SE_SMMU1_DEBUG_CNT_MODEr = 3710,
+	SE_SMMU1_INIT_DONEr = 3711,
+	SE_SMMU1_CPU_RSP_RD_DONEr = 3712,
+	SE_SMMU1_KSCH_OAM_SP_ENr = 3713,
+	SE_SMMU1_CFG_CACHE_ENr = 3714,
+	SE_SMMU1_CACHE_AGE_ENr = 3715,
+	SE_SMMU1_CPU_RDAT0r = 3716,
+	SE_SMMU1_CPU_RDAT1r = 3717,
+	SE_SMMU1_CPU_RDAT2r = 3718,
+	SE_SMMU1_CPU_RDAT3r = 3719,
+	SE_SMMU1_CPU_RDAT4r = 3720,
+	SE_SMMU1_CPU_RDAT5r = 3721,
+	SE_SMMU1_CPU_RDAT6r = 3722,
+	SE_SMMU1_CPU_RDAT7r = 3723,
+	SE_SMMU1_CPU_RDAT8r = 3724,
+	SE_SMMU1_CPU_RDAT9r = 3725,
+	SE_SMMU1_CPU_RDAT10r = 3726,
+	SE_SMMU1_CPU_RDAT11r = 3727,
+	SE_SMMU1_CPU_RDAT12r = 3728,
+	SE_SMMU1_CPU_RDAT13r = 3729,
+	SE_SMMU1_CPU_RDAT14r = 3730,
+	SE_SMMU1_CPU_RDAT15r = 3731,
+	SE_SMMU1_CTRL_CPU_RD_RDYr = 3732,
+	SE_SMMU1_CPU_WARBI_RDY_CFGr = 3733,
+	SE_SMMU1_DIR_ARBI_CPU_RPFULr = 3734,
+	SE_SMMU1_DIR_ARBI_WPFULr = 3735,
+	SE_SMMU1_CFG_WR_ARBI_PFUL0r = 3736,
+	SE_SMMU1_CFG_WR_ARBI_PFUL1r = 3737,
+	SE_SMMU1_SMMU1_WDONE_PFUL_CFGr = 3738,
+	SE_SMMU1_STAT_RATE_CFG_CNTr = 3739,
+	SE_SMMU1_FTM_RATE_CFG_CNTr = 3740,
+	SE_SMMU1_ETM_RATE_CFG_CNTr = 3741,
+	SE_SMMU1_DIR_RATE_CFG_CNTr = 3742,
+	SE_SMMU1_HASH_RATE_CFG_CNTr = 3743,
+	SE_SMMU1_FTM_TBL_CFGr = 3744,
+	SE_SMMU1_LPM_V4_AS_TBL_CFGr = 3745,
+	SE_SMMU1_LPM_V4_TBL_CFGr = 3746,
+	SE_SMMU1_LPM_V6_TBL_CFGr = 3747,
+	SE_SMMU1_LPM_V6_AS_TBL_CFGr = 3748,
+	SE_SMMU1_DMA_TBL_CFGr = 3749,
+	SE_SMMU1_OAM_TBL_CFGr = 3750,
+	SE_SMMU1_CTRL_RPAR_CPU_PFULr = 3751,
+	SE_SMMU1_CFG_KSCH_DIR_PFULr = 3752,
+	SE_SMMU1_CFG_KSCH_HASH_PFULr = 3753,
+	SE_SMMU1_CFG_KSCH_LPM_PFULr = 3754,
+	SE_SMMU1_CFG_KSCH_LPM_AS_PFULr = 3755,
+	SE_SMMU1_CFG_KSCH_STAT_PFULr = 3756,
+	SE_SMMU1_CFG_KSCH_TM_PFULr = 3757,
+	SE_SMMU1_CFG_KSCH_OAM_PFULr = 3758,
+	SE_SMMU1_CFG_KSCH_DMA_PFULr = 3759,
+	SE_SMMU1_CTRL_WFIFO_CFGr = 3760,
+	SE_SMMU1_RSCH_HASH_PTR_CFGr = 3761,
+	SE_SMMU1_RSCH_LPM_PTR_CFGr = 3762,
+	SE_SMMU1_RSCH_LPM_AS_PTR_CFGr = 3763,
+	SE_SMMU1_RSCH_STAT_PTR_CFGr = 3764,
+	SE_SMMU1_RSCH_OAM_PTR_CFGr = 3765,
+	SE_SMMU1_RSCHD_FIFO_PEPT_CFGr = 3766,
+	SE_SMMU1_DIR_FIFO_PFUL_CFGr = 3767,
+	SE_SMMU1_HASH_FIFO_PFUL_CFGr = 3768,
+	SE_SMMU1_LPM_FIFO_PFUL_CFGr = 3769,
+	SE_SMMU1_LPM_AS_FIFO_PFUL_CFGr = 3770,
+	SE_SMMU1_STAT_FIFO_PFUL_CFGr = 3771,
+	SE_SMMU1_FTM_FIFO_PFUL_CFGr = 3772,
+	SE_SMMU1_ETM_FIFO_PFUL_CFGr = 3773,
+	SE_SMMU1_OAM_FIFO_PFUL_CFGr = 3774,
+	SE_SMMU1_DMA_FIFO_PFUL_CFGr = 3775,
+	SE_SMMU1_CACHE_RSP_RR_FIFO_CFGr = 3776,
+	SE_SMMU1_DDR_RSP_RR_FIFO_CFGr = 3777,
+	SE_SMMU1_CPU_CAHCE_FIFO_CFGr = 3778,
+	SE_SMMU1_CACHE_RSP_FIFO_CFGr = 3779,
+	SE_SMMU1_TEST_STATEr = 3780,
+	SE_SMMU1_CACHE_FIFO_EPTr = 3781,
+	SE_SMMU1_RR_FIFO_EPTr = 3782,
+	SE_SMMU1_WR_FIFO_EPTr = 3783,
+	SE_SMMU1_WDONE_FIFO_EPTr = 3784,
+	SE_SMMU1_KSCHD_FIFO_EPT0r = 3785,
+	SE_SMMU1_CASH_FIFO_EPTr = 3786,
+	SE_SMMU1_CTRL_FIFO_EPTr = 3787,
+	SE_SMMU1_SMMU1_RSCHD_EPT3r = 3788,
+	SE_SMMU1_SMMU1_RSCHD_EPT2r = 3789,
+	SE_SMMU1_SMMU1_RSCHD_EPT1r = 3790,
+	SE_SMMU1_SMMU1_RSCHD_EPT0r = 3791,
+	SE_SMMU1_CASH0_ECC_ERR_ADDRr = 3792,
+	SE_SMMU1_ARBI_CPU_WR_RDYr = 3793,
+	SE_SMMU1_SMMU1_INT_0_ENr = 3794,
+	SE_SMMU1_SMMU1_INT_0_MASKr = 3795,
+	SE_SMMU1_SMMU1_INT_1_ENr = 3796,
+	SE_SMMU1_SMMU1_INT_1_MASKr = 3797,
+	SE_SMMU1_SMMU1_INT_2_ENr = 3798,
+	SE_SMMU1_SMMU1_INT_2_MASKr = 3799,
+	SE_SMMU1_SMMU1_INT_3_ENr = 3800,
+	SE_SMMU1_SMMU1_INT_3_MASKr = 3801,
+	SE_SMMU1_SMMU1_INT_0_STATUSr = 3802,
+	SE_SMMU1_SMMU1_INT_1_STATUSr = 3803,
+	SE_SMMU1_SMMU1_INT_2_STATUSr = 3804,
+	SE_SMMU1_SMMU1_INT_3_STATUSr = 3805,
+	SE_SMMU1_SMMU1_INT_STATUSr = 3806,
+	SE_SMMU1_CTRL_TO_CASH7_0_FC_CNTr = 3807,
+	SE_SMMU1_CASH7_0_TO_CTRL_REQ_CNTr = 3808,
+	SE_SMMU1_RSCHD_TO_CACHE7_FC_CNTr = 3809,
+	SE_SMMU1_CASH7_TO_CACHE_RSP_CNTr = 3810,
+	SE_SMMU1_CASH7_TO_CTRL_FC_CNTr = 3811,
+	SE_SMMU1_CTRL_TO_CASH7_0_RSP_CNTr = 3812,
+	SE_SMMU1_KSCHD_TO_CACHE7_0_REQ_CNTr = 3813,
+	SE_SMMU1_CACHE7_0_TO_KSCHD_FC_CNTr = 3814,
+	SE_SMMU1_DMA_TO_SMMU1_RD_REQ_CNTr = 3815,
+	SE_SMMU1_OAM_TO_KSCHD_REQ_CNTr = 3816,
+	SE_SMMU1_OAM_RR_STATE_RSP_CNTr = 3817,
+	SE_SMMU1_OAM_CLASH_INFO_CNTr = 3818,
+	SE_SMMU1_OAM_TO_RR_REQ_CNTr = 3819,
+	SE_SMMU1_LPM_AS_TO_KSCHD_REQ_CNTr = 3820,
+	SE_SMMU1_LPM_AS_RR_STATE_RSP_CNTr = 3821,
+	SE_SMMU1_LPM_AS_CLASH_INFO_CNTr = 3822,
+	SE_SMMU1_LPM_AS_TO_RR_REQ_CNTr = 3823,
+	SE_SMMU1_LPM_TO_KSCHD_REQ_CNTr = 3824,
+	SE_SMMU1_LPM_RR_STATE_RSP_CNTr = 3825,
+	SE_SMMU1_LPM_CLASH_INFO_CNTr = 3826,
+	SE_SMMU1_LPM_TO_RR_REQ_CNTr = 3827,
+	SE_SMMU1_HASH3_0_TO_KSCHD_REQ_CNTr = 3828,
+	SE_SMMU1_HASH3_0_RR_STATE_RSP_CNTr = 3829,
+	SE_SMMU1_HASH3_0_CLASH_INFO_CNTr = 3830,
+	SE_SMMU1_HASH3_0_TO_RR_REQ_CNTr = 3831,
+	SE_SMMU1_DIR3_0_TO_KSCHD_REQ_CNTr = 3832,
+	SE_SMMU1_DIR3_0_CLASH_INFO_CNTr = 3833,
+	SE_SMMU1_DIR_TBL_WR_REQ_CNTr = 3834,
+	SE_SMMU1_WARBI_TO_DIR_TBL_WARBI_FC_CNTr = 3835,
+	SE_SMMU1_DIR3_0_TO_BANK_RR_REQ_CNTr = 3836,
+	SE_SMMU1_KSCHD_TO_DIR3_0_FC_CNTr = 3837,
+	SE_SMMU1_DIR3_0_RR_STATE_RSP_CNTr = 3838,
+	SE_SMMU1_WR_DONE_TO_WARBI_FC_CNTr = 3839,
+	SE_SMMU1_WR_DONE_PTR_REQ_CNTr = 3840,
+	SE_SMMU1_CTRL7_0_TO_WARBI_FC_CNTr = 3841,
+	SE_SMMU1_WARBI_TO_CTRL7_0_WR_REQ_CNTr = 3842,
+	SE_SMMU1_WARBI_TO_CASH7_0_WR_REQ_CNTr = 3843,
+	SE_SMMU1_WARBI_TO_CPU_WR_FC_CNTr = 3844,
+	SE_SMMU1_CPU_WR_REQ_CNTr = 3845,
+	SE_SMMU1_CTRL7_0_TO_CPU_RD_RSP_CNTr = 3846,
+	SE_SMMU1_CPU_TO_CTRL7_0_RD_REQ_CNTr = 3847,
+	SE_SMMU1_CPU_RD_DIR_TBL_RSP_CNTr = 3848,
+	SE_SMMU1_CPU_TO_DIR_TBL_RD_WR_REQ_CNTr = 3849,
+	SE_SMMU1_SMMU1_TO_MMU_7_0_RSP_FC_CNTr = 3850,
+	SE_SMMU1_MMU_7_0_TO_SMMU1_RD_RSP_CNTr = 3851,
+	SE_SMMU1_MMU_7_0_TO_SMMU1_RD_FC_CNTr = 3852,
+	SE_SMMU1_SMMU1_TO_MMU_7_RD_REQ_CNTr = 3853,
+	SE_SMMU1_MMU_7_TO_SMMU1_WR_FC_CNTr = 3854,
+	SE_SMMU1_SMMU1_TO_MMU_7_0_WR_REQ_CNTr = 3855,
+	SE_SMMU1_SE_TO_SMMU1_WR_RSP_FC_CNTr = 3856,
+	SE_SMMU1_SMMU1_TO_SE_WR_RSP_CNTr = 3857,
+	SE_SMMU1_DDR7_0_WR_RSP_CNTr = 3858,
+	SE_SMMU1_SMMU1_TO_AS_FC_CNTr = 3859,
+	SE_SMMU1_AS_TO_SMMU1_WR_REQ_CNTr = 3860,
+	SE_SMMU1_SMMU1_TO_SE_PARSER_FC_CNTr = 3861,
+	SE_SMMU1_SE_PARSER_TO_SMMU1_REQ_CNTr = 3862,
+	SE_SMMU1_SMMU1_TO_ETM_WR_FC_CNTr = 3863,
+	SE_SMMU1_ETM_WR_REQ_CNTr = 3864,
+	SE_SMMU1_SMMU1_TO_FTM_WR_FC_CNTr = 3865,
+	SE_SMMU1_FTM_WR_REQ_CNTr = 3866,
+	SE_SMMU1_SMMU1_TO_STATE_WR_FC_CNTr = 3867,
+	SE_SMMU1_STATE_WR_REQ_CNTr = 3868,
+	SE_SMMU1_SE_TO_DMA_RSP_CNTr = 3869,
+	SE_SMMU1_SE_TO_DMA_FC_CNTr = 3870,
+	SE_SMMU1_OAM_TO_SMMU1_FC_CNTr = 3871,
+	SE_SMMU1_SMMU1_TO_OAM_RSP_CNTr = 3872,
+	SE_SMMU1_SMMU1_TO_OAM_FC_CNTr = 3873,
+	SE_SMMU1_OAM_TO_SMMU1_REQ_CNTr = 3874,
+	SE_SMMU1_SMMU1_TO_ETM_RSP_CNTr = 3875,
+	SE_SMMU1_SMMU1_TO_FTM_RSP_CNTr = 3876,
+	SE_SMMU1_SMMU1_TO_ETM_FC_CNTr = 3877,
+	SE_SMMU1_ETM_TO_SMMU1_REQ_CNTr = 3878,
+	SE_SMMU1_SMMU1_TO_FTM_FC_CNTr = 3879,
+	SE_SMMU1_FTM_TO_SMMU1_REQ_CNTr = 3880,
+	SE_SMMU1_SMMU1_TO_STAT_RSP_CNTr = 3881,
+	SE_SMMU1_SMMU1_TO_STAT_FC_CNTr = 3882,
+	SE_SMMU1_STAT_TO_SMMU1_REQ_CNTr = 3883,
+	SE_SMMU1_LPM_AS_TO_SMMU1_FC_CNTr = 3884,
+	SE_SMMU1_LPM_TO_SMMU1_FC_CNTr = 3885,
+	SE_SMMU1_SMMU1_TO_LPM_AS_RSP_CNTr = 3886,
+	SE_SMMU1_SMMU1_TO_LPM_RSP_CNTr = 3887,
+	SE_SMMU1_SMMU1_TO_LPM_AS_FC_CNTr = 3888,
+	SE_SMMU1_SMMU1_TO_LPM_FC_CNTr = 3889,
+	SE_SMMU1_LPM_AS_TO_SMMU1_REQ_CNTr = 3890,
+	SE_SMMU1_LPM_TO_SMMU1_REQ_CNTr = 3891,
+	SE_SMMU1_HASH3_0_TO_SMMU1_FC_CNTr = 3892,
+	SE_SMMU1_SMMU1_TO_HASH3_0_RSP_CNTr = 3893,
+	SE_SMMU1_SMMU1_TO_HASH3_0_FC_CNTr = 3894,
+	SE_SMMU1_HASH3_0_TO_SMMU1_CNTr = 3895,
+	SE_SMMU1_SE_TO_SMMU1_DIR3_0_RSP_FC_CNTr = 3896,
+	SE_SMMU1_SMMU1_TO_SE_DIR3_0_RSP_CNTr = 3897,
+	SE_SMMU1_SMMU1_TO_SE_DIR3_0_FC_CNTr = 3898,
+	SE_SMMU1_SE_TO_SMMU1_DIR3_0_CNTr = 3899,
+	SE_SMMU1_CACHE7_0_TO_RSCHD_RSP_CNTr = 3900,
+	SE_CMMU_DDR_RW_ADDRr = 3901,
+	SE_CMMU_DDR_RW_MODEr = 3902,
+	SE_CMMU_CP_CMDr = 3903,
+	SE_CMMU_CPU_IND_RD_DONEr = 3904,
+	SE_CMMU_CPU_IND_RDAT0r = 3905,
+	SE_CMMU_CPU_IND_RDAT1r = 3906,
+	SE_CMMU_CPU_IND_RDAT2r = 3907,
+	SE_CMMU_CPU_IND_RDAT3r = 3908,
+	SE_CMMU_CPU_DDR_FIFO_ALMFULr = 3909,
+	SE_CMMU_DEBUG_CNT_MODEr = 3910,
+	SE_CMMU_CMMU_PFUL_CFGr = 3911,
+	SE_CMMU_CMMU_STAT_PFUL_CFGr = 3912,
+	SE_CMMU_STAT_OVERFLOW_MODEr = 3913,
+	SE_CMMU_CMMU_CP_FIFO_PFULr = 3914,
+	SE_CMMU_DDR_WR_DAT0r = 3915,
+	SE_CMMU_DDR_WR_DAT1r = 3916,
+	SE_CMMU_CMMU_INT_UNMASK_FLAGr = 3917,
+	SE_CMMU_CMMU_INT_ENr = 3918,
+	SE_CMMU_CMMU_INT_MASKr = 3919,
+	SE_CMMU_CMMU_INT_STATUSr = 3920,
+	SE_CMMU_STAT_CMMU_REQ_CNTr = 3921,
+	SE_CMMU_CMMU_FC0_CNTr = 3922,
+	SE_CMMU_CMMU_FC1_CNTr = 3923,
+	SE_CMMU_CMMU_FC2_CNTr = 3924,
+	SMMU14K_SE_SMMU1_HASH0_TBL0_CFGr = 3925,
+	SMMU14K_SE_SMMU1_HASH0_TBL1_CFGr = 3926,
+	SMMU14K_SE_SMMU1_HASH0_TBL2_CFGr = 3927,
+	SMMU14K_SE_SMMU1_HASH0_TBL3_CFGr = 3928,
+	SMMU14K_SE_SMMU1_HASH0_TBL4_CFGr = 3929,
+	SMMU14K_SE_SMMU1_HASH0_TBL5_CFGr = 3930,
+	SMMU14K_SE_SMMU1_HASH0_TBL6_CFGr = 3931,
+	SMMU14K_SE_SMMU1_HASH0_TBL7_CFGr = 3932,
+	SMMU14K_SE_SMMU1_HASH1_TBL0_CFGr = 3933,
+	SMMU14K_SE_SMMU1_HASH1_TBL1_CFGr = 3934,
+	SMMU14K_SE_SMMU1_HASH1_TBL2_CFGr = 3935,
+	SMMU14K_SE_SMMU1_HASH1_TBL3_CFGr = 3936,
+	SMMU14K_SE_SMMU1_HASH1_TBL4_CFGr = 3937,
+	SMMU14K_SE_SMMU1_HASH1_TBL5_CFGr = 3938,
+	SMMU14K_SE_SMMU1_HASH1_TBL6_CFGr = 3939,
+	SMMU14K_SE_SMMU1_HASH1_TBL7_CFGr = 3940,
+	SMMU14K_SE_SMMU1_HASH2_TBL0_CFGr = 3941,
+	SMMU14K_SE_SMMU1_HASH2_TBL1_CFGr = 3942,
+	SMMU14K_SE_SMMU1_HASH2_TBL2_CFGr = 3943,
+	SMMU14K_SE_SMMU1_HASH2_TBL3_CFGr = 3944,
+	SMMU14K_SE_SMMU1_HASH2_TBL4_CFGr = 3945,
+	SMMU14K_SE_SMMU1_HASH2_TBL5_CFGr = 3946,
+	SMMU14K_SE_SMMU1_HASH2_TBL6_CFGr = 3947,
+	SMMU14K_SE_SMMU1_HASH2_TBL7_CFGr = 3948,
+	SMMU14K_SE_SMMU1_HASH3_TBL0_CFGr = 3949,
+	SMMU14K_SE_SMMU1_HASH3_TBL1_CFGr = 3950,
+	SMMU14K_SE_SMMU1_HASH3_TBL2_CFGr = 3951,
+	SMMU14K_SE_SMMU1_HASH3_TBL3_CFGr = 3952,
+	SMMU14K_SE_SMMU1_HASH3_TBL4_CFGr = 3953,
+	SMMU14K_SE_SMMU1_HASH3_TBL5_CFGr = 3954,
+	SMMU14K_SE_SMMU1_HASH3_TBL6_CFGr = 3955,
+	SMMU14K_SE_SMMU1_HASH3_TBL7_CFGr = 3956,
+	STAT_STAT_CFG_CPU_IND_ERAM_WDAT1r = 3957,
+	STAT_STAT_CFG_CPU_IND_ERAM_WDAT2r = 3958,
+	STAT_STAT_CFG_CPU_IND_ERAM_WDAT3r = 3959,
+	STAT_STAT_CFG_CPU_IND_ERAM_REQ_INFOr = 3960,
+	STAT_STAT_CFG_CPU_IND_ERAM_RD_DONEr = 3961,
+	STAT_STAT_CFG_CPU_IND_ERAM_RDAT0r = 3962,
+	STAT_STAT_CFG_CPU_IND_ERAM_RDAT1r = 3963,
+	STAT_STAT_CFG_CPU_IND_ERAM_RDAT2r = 3964,
+	STAT_STAT_CFG_CPU_IND_ERAM_RDAT3r = 3965,
+	STAT_STAT_CFG_TM_ALU_ERAM_CPU_RDYr = 3966,
+	STAT_STAT_CFG_OAM_STAT_CFGr = 3967,
+	STAT_STAT_CFG_FTM_PORT_SEL_CFGr = 3968,
+	STAT_STAT_CFG_OAM_ERAM_BASE_ADDRr = 3969,
+	STAT_STAT_CFG_OAM_LM_ERAM_BASE_ADDRr = 3970,
+	STAT_STAT_CFG_OAM_DDR_BASE_ADDRr = 3971,
+	STAT_STAT_CFG_PLCR0_SCHD_PFUL_CFGr = 3972,
+	STAT_STAT_CFG_OAM_LM_ORD_PFUL_CFGr = 3973,
+	STAT_STAT_CFG_DDR_SCHD_PFUL_CFGr = 3974,
+	STAT_STAT_CFG_ERAM_SCHD_PFUL_CFGr = 3975,
+	STAT_STAT_CFG_ERAM_SCHD_PEPT_CFGr = 3976,
+	STAT_STAT_CFG_ERAM_SCHD_OAM_PFUL_CFGr = 3977,
+	STAT_STAT_CFG_ERAM_SCHD_OAM_PEPT_CFGr = 3978,
+	STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PFUL_CFGr = 3979,
+	STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PEPT_CFGr = 3980,
+	STAT_STAT_CFG_RSCHD_PFUL_CFGr = 3981,
+	STAT_STAT_CFG_RSCHD_PEPT_CFGr = 3982,
+	STAT_STAT_CFG_RSCHD_PLCR_PFUL_CFGr = 3983,
+	STAT_STAT_CFG_RSCHD_PLCR_PEPT_CFGr = 3984,
+	STAT_STAT_CFG_RSCHD_PLCR_INFO_PFUL_CFGr = 3985,
+	STAT_STAT_CFG_ALU_ARB_CPU_PFUL_CFGr = 3986,
+	STAT_STAT_CFG_ALU_ARB_USER_PFUL_CFGr = 3987,
+	STAT_STAT_CFG_ALU_ARB_STAT_PFUL_CFGr = 3988,
+	STAT_STAT_CFG_CYCMOV_DAT_PFUL_CFGr = 3989,
+	STAT_STAT_CFG_DDR_OPR_PFUL_CFGr = 3990,
+	STAT_STAT_CFG_CYCLE_MOV_PFUL_CFGr = 3991,
+	STAT_STAT_CFG_CNTOVF_PFUL_CFGr = 3992,
+	STAT_STAT_CFG_ERAM_SCHD_PLCR_PFUL_CFGr = 3993,
+	STAT_STAT_CFG_ERAM_SCHD_PLCR_PEPT_CFGr = 3994,
+	STAT_STAT_CFG_DEBUG_CNT_MODEr = 3995,
+	STAT_STAT_CFG_TM_MOV_PERIOD_CFGr = 3996,
+	STAT_STAT_CFG_ALU_DDR_CPU_REQ_PFUL_CFGr = 3997,
+	STAT_STAT_CFG_CYCMOV_ADDR_PFUL_CFGr = 3998,
+	STAT_STAT_CFG_ORD_DDR_PLCR_FIFO_EMPTYr = 3999,
+	STAT_STAT_CFG_TM_STAT_FIFO_EMPTYr = 4000,
+	STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_0_1r = 4001,
+	STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_2_3r = 4002,
+	STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_4_5r = 4003,
+	STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_6_7r = 4004,
+	STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_FREE_8r = 4005,
+	STAT_STAT_CFG_RSCHD_FIFO_EMPTY_0_3r = 4006,
+	STAT_STAT_CFG_RSCHD_FIFO_EMPTY_4_7r = 4007,
+	STAT_STAT_CFG_RSCHD_FIFO_EMPTY_8_11r = 4008,
+	STAT_STAT_CFG_RSCHD_FIFO_EMPTY_12_15r = 4009,
+	STAT_STAT_CFG_RSCHD_FIFO_EMPTY_PLCR_16_17r = 4010,
+	STAT_STAT_CFG_STAT_INT_UNMASK_FLAGr = 4011,
+	STAT_STAT_CFG_STAT_INT0_ENr = 4012,
+	STAT_STAT_CFG_STAT_INT0_MASKr = 4013,
+	STAT_STAT_CFG_STAT_INT0_STATUSr = 4014,
+	STAT_STAT_CFG_STAT_INT1_ENr = 4015,
+	STAT_STAT_CFG_STAT_INT1_MASKr = 4016,
+	STAT_STAT_CFG_STAT_INT1_STATUSr = 4017,
+	STAT_STAT_CFG_STAT_INT2_ENr = 4018,
+	STAT_STAT_CFG_STAT_INT2_MASKr = 4019,
+	STAT_STAT_CFG_STAT_INT2_STATUSr = 4020,
+	STAT_STAT_CFG_STAT_INT3_ENr = 4021,
+	STAT_STAT_CFG_STAT_INT3_MASKr = 4022,
+	STAT_STAT_CFG_STAT_INT3_STATUSr = 4023,
+	STAT_STAT_CFG_STAT_INT4_ENr = 4024,
+	STAT_STAT_CFG_STAT_INT4_MASKr = 4025,
+	STAT_STAT_CFG_STAT_INT4_STATUSr = 4026,
+	STAT_STAT_CFG_STAT_INT5_ENr = 4027,
+	STAT_STAT_CFG_STAT_INT5_MASKr = 4028,
+	STAT_STAT_CFG_STAT_INT5_STATUSr = 4029,
+	STAT_STAT_CFG_RSCHD_ECC_BYPASSr = 4030,
+	STAT_STAT_CFG_RSCHD_ECC_SINGLE_ERRr = 4031,
+	STAT_STAT_CFG_RSCHD_ECC_DOUBLE_ERRr = 4032,
+	STAT_STAT_CFG_CPU_IND_DDR_WDAT0r = 4033,
+	STAT_STAT_CFG_CPU_IND_DDR_WDAT1r = 4034,
+	STAT_STAT_CFG_CPU_IND_DDR_WDAT2r = 4035,
+	STAT_STAT_CFG_CPU_IND_DDR_WDAT3r = 4036,
+	STAT_STAT_CFG_CPU_IND_DDR_WDAT4r = 4037,
+	STAT_STAT_CFG_CPU_IND_DDR_WDAT5r = 4038,
+	STAT_STAT_CFG_CPU_IND_DDR_WDAT6r = 4039,
+	STAT_STAT_CFG_CPU_IND_DDR_WDAT7r = 4040,
+	STAT_STAT_CFG_CPU_IND_DDR_WDAT8r = 4041,
+	STAT_STAT_CFG_CPU_IND_DDR_WDAT9r = 4042,
+	STAT_STAT_CFG_CPU_IND_DDR_WDAT10r = 4043,
+	STAT_STAT_CFG_CPU_IND_DDR_WDAT11r = 4044,
+	STAT_STAT_CFG_CPU_IND_DDR_WDAT12r = 4045,
+	STAT_STAT_CFG_CPU_IND_DDR_WDAT13r = 4046,
+	STAT_STAT_CFG_CPU_IND_DDR_WDAT14r = 4047,
+	STAT_STAT_CFG_CPU_IND_DDR_WDAT15r = 4048,
+	STAT_STAT_CFG_CPU_IND_DDR_REQ_INFOr = 4049,
+	STAT_STAT_CFG_CPU_IND_DDR_RD_DONEr = 4050,
+	STAT_STAT_CFG_CPU_IND_DDR_RDAT0r = 4051,
+	STAT_STAT_CFG_CPU_IND_DDR_RDAT1r = 4052,
+	STAT_STAT_CFG_CPU_IND_DDR_RDAT2r = 4053,
+	STAT_STAT_CFG_CPU_IND_DDR_RDAT3r = 4054,
+	STAT_STAT_CFG_CPU_IND_DDR_RDAT4r = 4055,
+	STAT_STAT_CFG_CPU_IND_DDR_RDAT5r = 4056,
+	STAT_STAT_CFG_CPU_IND_DDR_RDAT6r = 4057,
+	STAT_STAT_CFG_CPU_IND_DDR_RDAT7r = 4058,
+	STAT_STAT_CFG_CPU_IND_DDR_RDAT8r = 4059,
+	STAT_STAT_CFG_CPU_IND_DDR_RDAT9r = 4060,
+	STAT_STAT_CFG_CPU_IND_DDR_RDAT10r = 4061,
+	STAT_STAT_CFG_CPU_IND_DDR_RDAT11r = 4062,
+	STAT_STAT_CFG_CPU_IND_DDR_RDAT12r = 4063,
+	STAT_STAT_CFG_CPU_IND_DDR_RDAT13r = 4064,
+	STAT_STAT_CFG_CPU_IND_DDR_RDAT14r = 4065,
+	STAT_STAT_CFG_CPU_IND_DDR_RDAT15r = 4066,
+	STAT_STAT_CFG_TM_ALU_DDR_CPU_RDYr = 4067,
+	STAT_STAT_CFG_EPT_FLAGr = 4068,
+	STAT_STAT_CFG_PPU_SOFT_RSTr = 4069,
+	STAT_STAT_CFG_STAT_SMMU0_FC15_0_CNTr = 4070,
+	STAT_STAT_CFG_SMMU0_STAT_FC15_0_CNTr = 4071,
+	STAT_STAT_CFG_SMMU0_STAT_RSP15_0_CNTr = 4072,
+	STAT_STAT_CFG_STAT_SMMU0_REQ15_0_CNTr = 4073,
+	STAT_STAT_CFG_PPU_STAT_MEC5_0_RSP_FC_CNTr = 4074,
+	STAT_STAT_CFG_STAT_PPU_MEC5_0_KEY_FC_CNTr = 4075,
+	STAT_STAT_CFG_STAT_PPU_MEC5_0_RSP_CNTr = 4076,
+	STAT_STAT_CFG_PPU_STAT_MEC5_0_KEY_CNTr = 4077,
+	STAT_STAT_CFG_PPU5_0_NO_EXIST_OPCD_EX_CNTr = 4078,
+	STAT_STAT_CFG_SE_ETM_STAT_WR_FC_CNTr = 4079,
+	STAT_STAT_CFG_SE_ETM_STAT_RD_FC_CNTr = 4080,
+	STAT_STAT_CFG_STAT_ETM_DEQ_FC_CNTr = 4081,
+	STAT_STAT_CFG_STAT_ETM_ENQ_FC_CNTr = 4082,
+	STAT_STAT_CFG_STAT_OAM_LM_FC_CNTr = 4083,
+	STAT_STAT_CFG_OAM_STAT_LM_FC_CNTr = 4084,
+	STAT_STAT_CFG_STAT_OAM_FC_CNTr = 4085,
+	STAT_STAT_CFG_CMMU_STAT_FC_CNTr = 4086,
+	STAT_STAT_CFG_STAT_CMMU_REQ_CNTr = 4087,
+	STAT_STAT_CFG_SMMU0_PLCR_RSP0_CNTr = 4088,
+	STAT_STAT_CFG_PLCR_SMMU0_REQ0_CNTr = 4089,
+	STAT_STAT_CFG_STAT_OAM_LM_RSP_CNTr = 4090,
+	STAT_STAT_CFG_OAM_STAT_LM_REQ_CNTr = 4091,
+	STAT_STAT_CFG_OAM_STAT_REQ_CNTr = 4092,
+	STAT_STAT_CFG_SE_ETM_STAT_RSP_CNTr = 4093,
+	STAT_STAT_CFG_ETM_STAT_SE_WR_REQ_CNTr = 4094,
+	STAT_STAT_CFG_ETM_STAT_SE_RD_REQ_CNTr = 4095,
+	STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT0r = 4096,
+	STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT1r = 4097,
+	STAT_STAT_CFG_TM_STAT_ERAM_CPU_RSP_CNTr = 4098,
+	STAT_STAT_CFG_CPU_RD_ERAM_REQ_CNTr = 4099,
+	STAT_STAT_CFG_CPU_WR_ERAM_REQ_CNTr = 4100,
+	STAT_STAT_CFG_TM_STAT_DDR_CPU_RSP_CNTr = 4101,
+	STAT_STAT_CFG_CPU_RD_DDR_REQ_CNTr = 4102,
+	STAT_STAT_CFG_CPU_WR_DDR_REQ_CNTr = 4103,
+	STAT_ETCAM_CPU_IND_WDAT1r = 4104,
+	STAT_ETCAM_CPU_IND_WDAT2r = 4105,
+	STAT_ETCAM_CPU_IND_WDAT3r = 4106,
+	STAT_ETCAM_CPU_IND_WDAT4r = 4107,
+	STAT_ETCAM_CPU_IND_WDAT5r = 4108,
+	STAT_ETCAM_CPU_IND_WDAT6r = 4109,
+	STAT_ETCAM_CPU_IND_WDAT7r = 4110,
+	STAT_ETCAM_CPU_IND_WDAT8r = 4111,
+	STAT_ETCAM_CPU_IND_WDAT9r = 4112,
+	STAT_ETCAM_CPU_IND_WDAT10r = 4113,
+	STAT_ETCAM_CPU_IND_WDAT11r = 4114,
+	STAT_ETCAM_CPU_IND_WDAT12r = 4115,
+	STAT_ETCAM_CPU_IND_WDAT13r = 4116,
+	STAT_ETCAM_CPU_IND_WDAT14r = 4117,
+	STAT_ETCAM_CPU_IND_WDAT15r = 4118,
+	STAT_ETCAM_CPU_IND_WDAT16r = 4119,
+	STAT_ETCAM_CPU_IND_WDAT17r = 4120,
+	STAT_ETCAM_CPU_IND_WDAT18r = 4121,
+	STAT_ETCAM_CPU_IND_WDAT19r = 4122,
+	STAT_ETCAM_T_STRWC_CFGr = 4123,
+	STAT_ETCAM_ETCAM_INT_UNMASK_FLAGr = 4124,
+	STAT_ETCAM_ETCAM_INT_EN0r = 4125,
+	STAT_ETCAM_ETCAM_INT_MASK0r = 4126,
+	STAT_ETCAM_ETCAM_INT_STATUSr = 4127,
+	STAT_ETCAM_INT_TB_INI_OKr = 4128,
+	STAT_ETCAM_ETCAM_CLK_ENr = 4129,
+	STAT_ETCAM_AS_ETCAM_REQ0_CNTr = 4130,
+	STAT_ETCAM_AS_ETCAM_REQ1_CNTr = 4131,
+	STAT_ETCAM_ETCAM_AS_INDEX0_CNTr = 4132,
+	STAT_ETCAM_ETCAM_AS_INDEX1_CNTr = 4133,
+	STAT_ETCAM_ETCAM_NOT_HIT0_CNTr = 4134,
+	STAT_ETCAM_ETCAM_NOT_HIT1_CNTr = 4135,
+	STAT_ETCAM_TABLE_ID_NOT_MATCH_CNTr = 4136,
+	STAT_ETCAM_TABLE_ID_CLASH01_CNTr = 4137,
+	STAT_ETCAM_ETCAM_CPU_FLr = 4138,
+	STAT_ETCAM_ETCAM_ARB_EMPTYr = 4139,
+	DTB_DTB_CFG_CFG_FINISH_INT_EVENT0r = 4140,
+	DTB_DTB_CFG_CFG_FINISH_INT_EVENT1r = 4141,
+	DTB_DTB_CFG_CFG_FINISH_INT_EVENT2r = 4142,
+	DTB_DTB_CFG_CFG_FINISH_INT_EVENT3r = 4143,
+	DTB_DTB_CFG_CFG_FINISH_INT_MAKS0r = 4144,
+	DTB_DTB_CFG_CFG_FINISH_INT_MAKS1r = 4145,
+	DTB_DTB_CFG_CFG_FINISH_INT_MAKS2r = 4146,
+	DTB_DTB_CFG_CFG_FINISH_INT_MAKS3r = 4147,
+	DTB_DTB_CFG_CFG_FINISH_INT_TEST0r = 4148,
+	DTB_DTB_CFG_CFG_FINISH_INT_TEST1r = 4149,
+	DTB_DTB_CFG_CFG_FINISH_INT_TEST2r = 4150,
+	DTB_DTB_CFG_CFG_FINISH_INT_TEST3r = 4151,
+	DTB_DTB_CFG_CFG_DTB_INT_TO_RISCV_SELr = 4152,
+	DTB_DTB_CFG_CFG_DTB_EP_INT_MSIX_ENABLEr = 4153,
+	DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_H_0_15r = 4154,
+	DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_L_0_15r = 4155,
+	DTB_DTB_CFG_CFG_DTB_DEBUG_MODE_ENr = 4156,
+	DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_HIGHr = 4157,
+	DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_LOWr = 4158,
+	DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_LENr = 4159,
+	DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USERr = 4160,
+	DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ONLOAD_CNTr = 4161,
+	DTB_DTB_CFG_CNT_AXI_RD_TABLE_RESP_ERRr = 4162,
+	DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_HIGHr = 4163,
+	DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_LOWr = 4164,
+	DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_LENr = 4165,
+	DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USERr = 4166,
+	DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ONLOAD_CNTr = 4167,
+	DTB_DTB_CFG_CNT_AXI_RD_PD_RESP_ERRr = 4168,
+	DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_HIGHr = 4169,
+	DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_LOWr = 4170,
+	DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_LENr = 4171,
+	DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USERr = 4172,
+	DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ONLOAD_CNTr = 4173,
+	DTB_DTB_CFG_CNT_AXI_WR_CTRL_RESP_ERRr = 4174,
+	DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_HIGHr = 4175,
+	DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_LOWr = 4176,
+	DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_LENr = 4177,
+	DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USERr = 4178,
+	DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ONLOAD_CNTr = 4179,
+	DTB_DTB_CFG_CNT_AXI_WR_DDR_RESP_ERRr = 4180,
+	DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_HIGHr = 4181,
+	DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_LOWr = 4182,
+	DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_LENr = 4183,
+	DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USERr = 4184,
+	DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ONLOAD_CNTr = 4185,
+	DTB_DTB_CFG_CNT_AXI_WR_FIN_RESP_ERRr = 4186,
+	DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_HIGHr = 4187,
+	DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_LOWr = 4188,
+	DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_HIGHr = 4189,
+	DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_LOWr = 4190,
+	DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_HIGHr = 4191,
+	DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_LOWr = 4192,
+	DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_HIGHr = 4193,
+	DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_LOWr = 4194,
+	DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_HIGHr = 4195,
+	DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_LOWr = 4196,
+	DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_HIGHr = 4197,
+	DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_LOWr = 4198,
+	DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_HIGHr = 4199,
+	DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_LOWr = 4200,
+	DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_HIGHr = 4201,
+	DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_LOWr = 4202,
+	DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_HIGHr = 4203,
+	DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_LOWr = 4204,
+	DTB_DTB_CFG_INFO_WR_CTRL_STATEr = 4205,
+	DTB_DTB_CFG_INFO_RD_TABLE_STATEr = 4206,
+	DTB_DTB_CFG_INFO_RD_PD_STATEr = 4207,
+	DTB_DTB_CFG_INFO_DUMP_CMD_STATEr = 4208,
+	DTB_DTB_CFG_INFO_WR_DDR_STATEr = 4209,
+	DTB_DTB_CFG_CFG_DTB_DEBUG_INFO_CLRr = 4210,
+	DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_0_15r = 4211,
+	DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_COMP_ENr = 4212,
+	DTB_DDOS_CFG_DDOS_DUMP_STAT_NUMr = 4213,
+	DTB_DDOS_CFG_DDOS_EVEN_HASH_TABLE_BADDRr = 4214,
+	DTB_DDOS_CFG_DDOS_ODD_HASH_TABLE_BADDRr = 4215,
+	DTB_DDOS_CFG_DDOS_STAT_INDEX_OFFSETr = 4216,
+	DTB_DDOS_CFG_DDOS_NS_FLAG_CNTr = 4217,
+	DTB_DDOS_CFG_DDOS_EVEN_STAT_TABLE_BADDRr = 4218,
+	DTB_DDOS_CFG_DDOS_ODD_STAT_TABLE_BADDRr = 4219,
+	DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_Hr = 4220,
+	DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_Lr = 4221,
+	DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_Hr = 4222,
+	DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_Lr = 4223,
+	DTB_DDOS_CFG_DDOS_WORK_MODE_ENABLEr = 4224,
+	DTB_DDOS_CFG_DDOS_STAT_TABLE_LENr = 4225,
+	DTB_DDOS_CFG_DDOS_HASH_TABLE_LENr = 4226,
+	DTB_DTB_RAM_TRAF_CTRL_RAM0_0_255r = 4227,
+	DTB_DTB_RAM_TRAF_CTRL_RAM1_0_255r = 4228,
+	DTB_DTB_RAM_TRAF_CTRL_RAM2_0_255r = 4229,
+	DTB_DTB_RAM_TRAF_CTRL_RAM3_0_255r = 4230,
+	DTB_DTB_RAM_TRAF_CTRL_RAM4_0_255r = 4231,
+	DTB_DTB_RAM_TRAF_CTRL_RAM5_0_63r = 4232,
+	DTB_DTB_RAM_DUMP_PD_RAM_0_2047r = 4233,
+	DTB_DTB_RAM_RD_CTRL_RAM_0_4095r = 4234,
+	DTB_DTB_RAM_RD_TABLE_RAM_0_8191r = 4235,
+	DTB_DTB_RAM_DTB_CMD_MAN_RAM_0_16383r = 4236,
+	TRPG_TRPG_RX_PORT_CPU_TRPG_MS_STr = 4237,
+	TRPG_TRPG_RX_PORT_CPU_TRPG_MS_INDr = 4238,
+	TRPG_TRPG_RX_PORT_CPU_TRPG_MS_SLAVE_INDr = 4239,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_UP_WATER_LEVELr = 4240,
+	TRPG_TRPG_RX_PORT_CPU_TRPGRX_LOW_WATER_LEVELr = 4241,
+	TRPG_TRPG_TX_PORT_CPU_TRPG_MS_STr = 4242,
+	TRPG_TRPG_TX_PORT_CPU_TRPG_MS_INDr = 4243,
+	TRPG_TRPG_TX_PORT_CPU_TRPG_MS_SLAVE_INDr = 4244,
+	TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_EVENTr = 4245,
+	TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_TESTr = 4246,
+	TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_ADDRr = 4247,
+	TRPG_TRPG_TX_TODTIME_RAM_TRPG_TX_TODTIME_RAMr = 4248,
+	TSN_TSN_PORT_CFG_TSN_TEST_REGr = 4249,
+	TSN_TSN_PORT_CFG_TSN_PORT_QBV_ENABLEr = 4250,
+	TSN_TSN_PORT_CFG_TSN_PHY_PORT_SELr = 4251,
+	TSN_TSN_PORT_CFG_TSN_PORT_TIME_SELr = 4252,
+	TSN_TSN_PORT_CFG_TSN_CLK_FREQr = 4253,
+	TSN_TSN_PORT_CFG_TSN_READ_RAM_Nr = 4254,
+	TSN_TSN_PORT_CFG_TSN_EXE_TIMEr = 4255,
+	TSN_TSN_PORT_CFG_TSN_PORT_ITR_SHIFTr = 4256,
+	TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_Hr = 4257,
+	TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_Lr = 4258,
+	TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_Hr = 4259,
+	TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_Lr = 4260,
+	TSN_TSN_PORT_CFG_TSN_PORT_GUARD_BAND_TIMEr = 4261,
+	TSN_TSN_PORT_CFG_TSN_PORT_DEFAULT_GATE_ENr = 4262,
+	TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_GATE_ENr = 4263,
+	TSN_TSN_PORT_CFG_TSN_PORT_INIT_FINISHr = 4264,
+	TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_ENr = 4265,
+	TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM0r = 4266,
+	TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM1r = 4267,
+	TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE0r = 4268,
+	TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE1r = 4269,
+	AXI_AXI_CONV_CFG_EPID_V_FUNC_NUMr = 4270,
+	AXI_AXI_CONV_INFO_AXIM_RW_HSK_CNTr = 4271,
+	AXI_AXI_CONV_INFO_AXIM_LAST_WR_IDr = 4272,
+	AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_Hr = 4273,
+	AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_Lr = 4274,
+	AXI_AXI_CONV_CFG_DEBUG_INFO_CLR_ENr = 4275,
+	PTPTM_PTP_TOP_PP1S_INTERRUPTr = 4276,
+	PTPTM_PTP_TOP_PP1S_EXTERNAL_SELECTr = 4277,
+	PTPTM_PTP_TOP_PP1S_OUT_SELECTr = 4278,
+	PTPTM_PTP_TOP_TEST_PP1S_SELECTr = 4279,
+	PTPTM_PTP_TOP_LOCAL_PP1S_ENr = 4280,
+	PTPTM_PTP_TOP_LOCAL_PP1S_ADJUSTr = 4281,
+	PTPTM_PTP_TOP_LOCAL_PP1S_ADJUST_VALUEr = 4282,
+	PTPTM_PTP_TOP_PP1S_TO_NP_SELECTr = 4283,
+	PTPTM_PTP_TOP_PD_U1_SELr = 4284,
+	PTPTM_PTP_TOP_PD_U1_PD0_SHIFTr = 4285,
+	PTPTM_PTP_TOP_PD_U1_PD1_SHIFTr = 4286,
+	PTPTM_PTP_TOP_PD_U1_RESULTr = 4287,
+	PTPTM_PTP_TOP_PD_U2_SELr = 4288,
+	PTPTM_PTP_TOP_PD_U2_PD0_SHIFTr = 4289,
+	PTPTM_PTP_TOP_PD_U2_PD1_SHIFTr = 4290,
+	PTPTM_PTP_TOP_PD_U2_RESULTr = 4291,
+	PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY0r = 4292,
+	PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY0r = 4293,
+	PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY1r = 4294,
+	PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY1r = 4295,
+	PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY2r = 4296,
+	PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY2r = 4297,
+	PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY3r = 4298,
+	PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY3r = 4299,
+	PTPTM_PTP_TOP_TSN_PTP1588_RDMA_NANOSECOND_DELAYr = 4300,
+	PTPTM_PTP_TOP_PTP1588_RDMA_FRACNANOSECOND_DELAYr = 4301,
+	PTPTM_PTP_TOP_PTP1588_NP_NANOSECOND_DELAYr = 4302,
+	PTPTM_PTP_TOP_PTP1588_NP_FRACNANOSECOND_DELAYr = 4303,
+	PTPTM_PTP_TOP_TIME_SYNC_PERIODr = 4304,
+	PTPTM_PTPTM_MODULE_IDr = 4305,
+	PTPTM_PTPTM_MODULE_VERSIONr = 4306,
+	PTPTM_PTPTM_MODULE_DATEr = 4307,
+	PTPTM_PTPTM_INTERRUPT_STATUSr = 4308,
+	PTPTM_PTPTM_INTERRUPT_EVENTr = 4309,
+	PTPTM_PTPTM_INTERRUPT_MASKr = 4310,
+	PTPTM_PTPTM_INTERRUPT_TESTr = 4311,
+	PTPTM_PTPTM_HW_CLOCK_CYCLE_INTEGERr = 4312,
+	PTPTM_PTPTM_HW_CLOCK_CYCLE_FRACTIONr = 4313,
+	PTPTM_PTPTM_PTP_CLOCK_CYCLE_INTEGERr = 4314,
+	PTPTM_PTPTM_PTP_CLOCK_CYCLE_FRACTIONr = 4315,
+	PTPTM_PTPTM_PTP_CONFIGURATIONr = 4316,
+	PTPTM_PTPTM_TIMER_CONTROLr = 4317,
+	PTPTM_PTPTM_PPS_INCOME_DELAYr = 4318,
+	PTPTM_PTPTM_CLOCK_CYCLE_UPDATEr = 4319,
+	PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_1r = 4320,
+	PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_2r = 4321,
+	PTPTM_PTPTM_TIMER_LATCH_ENr = 4322,
+	PTPTM_PTPTM_TIMER_LATCH_SELr = 4323,
+	PTPTM_PTPTM_TRIGGER_IN_TOD_NANOSECONDr = 4324,
+	PTPTM_PTPTM_TRIGGER_IN_LOWER_TOD_SECONDr = 4325,
+	PTPTM_PTPTM_TRIGGER_IN_HIGH_TOD_SECONDr = 4326,
+	PTPTM_PTPTM_TRIGGER_IN_FRACNANOSECONDr = 4327,
+	PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_LOWr = 4328,
+	PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_HIGHr = 4329,
+	PTPTM_PTPTM_TRIGGER_OUT_TOD_NANOSECONDr = 4330,
+	PTPTM_PTPTM_TRIGGER_OUT_LOWER_TOD_SECONDr = 4331,
+	PTPTM_PTPTM_TRIGGER_OUT_HIGH_TOD_SECONDr = 4332,
+	PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_LOWr = 4333,
+	PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_HIGHr = 4334,
+	PTPTM_PTPTM_ADJUST_TOD_NANOSECONDr = 4335,
+	PTPTM_PTPTM_ADJUST_LOWER_TOD_SECONDr = 4336,
+	PTPTM_PTPTM_ADJUST_HIGH_TOD_SECONDr = 4337,
+	PTPTM_PTPTM_ADJUST_FRACNANOSECONDr = 4338,
+	PTPTM_PTPTM_ADJUST_HARDWARE_TIME_LOWr = 4339,
+	PTPTM_PTPTM_ADJUST_HARDWARE_TIME_HIGHr = 4340,
+	PTPTM_PTPTM_LATCH_TOD_NANOSECONDr = 4341,
+	PTPTM_PTPTM_LATCH_LOWER_TOD_SECONDr = 4342,
+	PTPTM_PTPTM_LATCH_HIGH_TOD_SECONDr = 4343,
+	PTPTM_PTPTM_LATCH_FRACNANOSECONDr = 4344,
+	PTPTM_PTPTM_LATCH_HARDWARE_TIME_LOWr = 4345,
+	PTPTM_PTPTM_LATCH_HARDWARE_TIME_HIGHr = 4346,
+	PTPTM_PTPTM_REAL_TOD_NANOSECONDr = 4347,
+	PTPTM_PTPTM_REAL_LOWER_TOD_SECONDr = 4348,
+	PTPTM_PTPTM_REAL_HIGH_TOD_SECONDr = 4349,
+	PTPTM_PTPTM_REAL_HARDWARE_TIME_LOWr = 4350,
+	PTPTM_PTPTM_REAL_HARDWARE_TIME_HIGHr = 4351,
+	PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_PORTr = 4352,
+	PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_LOWr = 4353,
+	PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_HIGHr = 4354,
+	PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_FIFO_STATUSr = 4355,
+	PTPTM_PTPTM_PP1S_LATCH_TOD_NANOSECONDr = 4356,
+	PTPTM_PTPTM_PP1S_LATCH_LOWER_TOD_SECONDr = 4357,
+	PTPTM_PTPTM_PP1S_LATCH_HIGH_TOD_SECONDr = 4358,
+	PTPTM_PTPTM_PP1S_LATCH_FRACNANOSECONDr = 4359,
+	PTPTM_PTPTM_TSN_TIME_CONFIGURATIONr = 4360,
+	PTPTM_PTPTM_TSN_TIMER_CONTROLr = 4361,
+	PTPTM_PTPTM_TSN0_CLOCK_CYCLE_INTEGERr = 4362,
+	PTPTM_PTPTM_TSN0_CLOCK_CYCLE_FRACTIONr = 4363,
+	PTPTM_PTPTM_TSN1_CLOCK_CYCLE_INTEGERr = 4364,
+	PTPTM_PTPTM_TSN1_CLOCK_CYCLE_FRACTIONr = 4365,
+	PTPTM_PTPTM_TSN2_CLOCK_CYCLE_INTEGERr = 4366,
+	PTPTM_PTPTM_TSN2_CLOCK_CYCLE_FRACTIONr = 4367,
+	PTPTM_PTPTM_TSN3_CLOCK_CYCLE_INTEGERr = 4368,
+	PTPTM_PTPTM_TSN3_CLOCK_CYCLE_FRACTIONr = 4369,
+	PTPTM_PTPTM_TSN0_ADJUST_TOD_NANOSECONDr = 4370,
+	PTPTM_PTPTM_TSN0_ADJUST_LOWER_TOD_SECONDr = 4371,
+	PTPTM_PTPTM_TSN0_ADJUST_HIGH_TOD_SECONDr = 4372,
+	PTPTM_PTPTM_TSN0_ADJUST_FRACNANOSECONDr = 4373,
+	PTPTM_PTPTM_TSN1_ADJUST_TOD_NANOSECONDr = 4374,
+	PTPTM_PTPTM_TSN1_ADJUST_LOWER_TOD_SECONDr = 4375,
+	PTPTM_PTPTM_TSN1_ADJUST_HIGH_TOD_SECONDr = 4376,
+	PTPTM_PTPTM_TSN1_ADJUST_FRACNANOSECONDr = 4377,
+	PTPTM_PTPTM_TSN2_ADJUST_TOD_NANOSECONDr = 4378,
+	PTPTM_PTPTM_TSN2_ADJUST_LOWER_TOD_SECONDr = 4379,
+	PTPTM_PTPTM_TSN2_ADJUST_HIGH_TOD_SECONDr = 4380,
+	PTPTM_PTPTM_TSN2_ADJUST_FRACNANOSECONDr = 4381,
+	PTPTM_PTPTM_TSN3_ADJUST_TOD_NANOSECONDr = 4382,
+	PTPTM_PTPTM_TSN3_ADJUST_LOWER_TOD_SECONDr = 4383,
+	PTPTM_PTPTM_TSN3_ADJUST_HIGH_TOD_SECONDr = 4384,
+	PTPTM_PTPTM_TSN3_ADJUST_FRACNANOSECONDr = 4385,
+	PTPTM_PTPTM_TSN0_LATCH_TOD_NANOSECONDr = 4386,
+	PTPTM_PTPTM_TSN0_LATCH_LOWER_TOD_SECONDr = 4387,
+	PTPTM_PTPTM_TSN0_LATCH_HIGH_TOD_SECONDr = 4388,
+	PTPTM_PTPTM_TSN0_LATCH_FRACNANOSECONDr = 4389,
+	PTPTM_PTPTM_TSN1_LATCH_TOD_NANOSECONDr = 4390,
+	PTPTM_PTPTM_TSN1_LATCH_LOWER_TOD_SECONDr = 4391,
+	PTPTM_PTPTM_TSN1_LATCH_HIGH_TOD_SECONDr = 4392,
+	PTPTM_PTPTM_TSN1_LATCH_FRACNANOSECONDr = 4393,
+	PTPTM_PTPTM_TSN2_LATCH_TOD_NANOSECONDr = 4394,
+	PTPTM_PTPTM_TSN2_LATCH_LOWER_TOD_SECONDr = 4395,
+	PTPTM_PTPTM_TSN2_LATCH_HIGH_TOD_SECONDr = 4396,
+	PTPTM_PTPTM_TSN2_LATCH_FRACNANOSECONDr = 4397,
+	PTPTM_PTPTM_TSN3_LATCH_TOD_NANOSECONDr = 4398,
+	PTPTM_PTPTM_TSN3_LATCH_LOWER_TOD_SECONDr = 4399,
+	PTPTM_PTPTM_TSN3_LATCH_HIGH_TOD_SECONDr = 4400,
+	PTPTM_PTPTM_TSN3_LATCH_FRACNANOSECONDr = 4401,
+	PTPTM_PTPTM_PP1S_LATCH_TSN0_TOD_NANOSECONDr = 4402,
+	PTPTM_PTPTM_PP1S_LATCH_TSN0_LOWER_TOD_SECONDr = 4403,
+	PTPTM_PTPTM_PP1S_LATCH_TSN0_HIGH_TOD_SECONDr = 4404,
+	PTPTM_PTPTM_PP1S_LATCH_TSN0_FRACNANOSECONDr = 4405,
+	PTPTM_PTPTM_PP1S_LATCH_TSN1_TOD_NANOSECONDr = 4406,
+	PTPTM_PTPTM_PP1S_LATCH_TSN1_LOWER_TOD_SECONDr = 4407,
+	PTPTM_PTPTM_PP1S_LATCH_TSN1_HIGH_TOD_SECONDr = 4408,
+	PTPTM_PTPTM_PP1S_LATCH_TSN1_FRACNANOSECONDr = 4409,
+	PTPTM_PTPTM_PP1S_LATCH_TSN2_TOD_NANOSECONDr = 4410,
+	PTPTM_PTPTM_PP1S_LATCH_TSN2_LOWER_TOD_SECONDr = 4411,
+	PTPTM_PTPTM_PP1S_LATCH_TSN2_HIGH_TOD_SECONDr = 4412,
+	PTPTM_PTPTM_PP1S_LATCH_TSN2_FRACNANOSECONDr = 4413,
+	PTPTM_PTPTM_PP1S_LATCH_TSN3_TOD_NANOSECONDr = 4414,
+	PTPTM_PTPTM_PP1S_LATCH_TSN3_LOWER_TOD_SECONDr = 4415,
+	PTPTM_PTPTM_PP1S_LATCH_TSN3_HIGH_TOD_SECONDr = 4416,
+	PTPTM_PTPTM_PP1S_LATCH_TSN3_FRACNANOSECONDr = 4417,
+	PTPTM_PTPTM_TSN0_REAL_TOD_NANOSECONDr = 4418,
+	PTPTM_PTPTM_TSN0_REAL_LOWER_TOD_SECONDr = 4419,
+	PTPTM_PTPTM_TSN0_REAL_HIGH_TOD_SECONDr = 4420,
+	PTPTM_PTPTM_TSN1_REAL_TOD_NANOSECONDr = 4421,
+	PTPTM_PTPTM_TSN1_REAL_LOWER_TOD_SECONDr = 4422,
+	PTPTM_PTPTM_TSN1_REAL_HIGH_TOD_SECONDr = 4423,
+	PTPTM_PTPTM_TSN2_REAL_TOD_NANOSECONDr = 4424,
+	PTPTM_PTPTM_TSN2_REAL_LOWER_TOD_SECONDr = 4425,
+	PTPTM_PTPTM_TSN2_REAL_HIGH_TOD_SECONDr = 4426,
+	PTPTM_PTPTM_TSN3_REAL_TOD_NANOSECONDr = 4427,
+	PTPTM_PTPTM_TSN3_REAL_LOWER_TOD_SECONDr = 4428,
+	PTPTM_PTPTM_TSN3_REAL_HIGH_TOD_SECONDr = 4429,
+	PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_INTEGERr = 4430,
+	PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_FRACTIONr = 4431,
+	PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_INTEGERr = 4432,
+	PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_FRACTIONr = 4433,
+	PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_INTEGERr = 4434,
+	PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_FRACTIONr = 4435,
+	PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_INTEGERr = 4436,
+	PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_FRACTIONr = 4437,
+	PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_INTEGERr = 4438,
+	PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_FRACTIONr = 4439,
+	REG_ENUM_MAX_VALUE
+} DPP_REG_INFO_E;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg_struct.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg_struct.h
old mode 100755
new mode 100644
index a91092c3168b57c29661ed33a67b4b132b2a4b85..75e75d689cbd16354fea5ed5615418ff872e59d7
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg_struct.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_reg_struct.h
@@ -1,88 +1,81 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_reg_struct.h
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : 石金锋
-* 完成日期 : 2014/02/10
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-#ifndef _DPP_REG_STRUCT_H_
-#define _DPP_REG_STRUCT_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "zxic_common.h"
-#include "dpp_dev.h"
-#include "dpp_type_api.h"
-
-
-typedef ZXIC_UINT32 (*DPP_REG_WRITE)(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data);
-typedef ZXIC_UINT32 (*DPP_REG_READ)(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data);
-
-
-#define DPP_FIELD_FLAG_RO      (1<<0)        /* 只读标志 */
-#define DPP_FIELD_FLAG_RW      (1<<1)        /* 读写标志 */
-#define DPP_FIELD_FLAG_RC      (1<<2)        /* 读清标志 */
-#define DPP_FIELD_FLAG_WO      (1<<3)        /* 只写标志 */
-#define DPP_FIELD_FLAG_WC      (1<<4)        /* 写清标志 */
-
-typedef struct dpp_field_t
-{
-    ZXIC_CHAR    *p_name;                         /* 字段名 */
-    ZXIC_UINT32  flags;                           /* 标志位 */
-    ZXIC_UINT16  msb_pos;                         /* 最高比特位置，以寄存器列表为准*/
-    ZXIC_UINT16  len;                             /* 字段长度，以比特为单位 */
-    ZXIC_UINT32  default_value;                   /* 缺省值 */
-    ZXIC_UINT32  default_step;                    /* 缺省值步长*/
-}DPP_FIELD_T;
-
-
-#define DPP_REG_FLAG_DIRECT      (0<<0)      /* 直接读写寄存器 */
-#define DPP_REG_FLAG_INDIRECT    (1<<0)      /* 间接读写寄存器 */
-#define DPP_REG_FLAG_WO          (1<<1)      /* 只写寄存器 */
-
-#define DPP_REG_NUL_ARRAY        (0<<0)      /*零元寄存器序列 */
-#define DPP_REG_UNI_ARRAY        (1<<0)      /*一元寄存器序列 */
-#define DPP_REG_BIN_ARRAY        (1<<1)      /*二元寄存器序列 */
-
-typedef struct dpp_reg_t
-{
-    ZXIC_CHAR    *reg_name;                       /* 寄存器名称*/
-    ZXIC_UINT32  reg_no;                          /* 寄存器的编号 */
-    ZXIC_UINT32  module_no;                       /* 寄存器归属的模块的编号 */
-    ZXIC_UINT32  flags;                           /* 标志位 */
-    ZXIC_UINT32  array_type;                      /* 寄存器偏移类型*/
-    ZXIC_UINT32  addr;                            /* 寄存器的芯片地址*/
-    ZXIC_UINT32  width;                           /* 寄存器位宽，以字节为单位 */
-    ZXIC_UINT32  m_size;                          /* 寄存器序列参数1的个数 */
-    ZXIC_UINT32  n_size;                          /* 寄存器序列参数2的个数*/
-    ZXIC_UINT32  m_step;                          /* 寄存器序列参数1的偏移步长 */
-    ZXIC_UINT32  n_step;                          /* 寄存器序列参数2的偏移步长 */
-    ZXIC_UINT32  field_num;                       /* 包含的字段个数 */
-    DPP_FIELD_T *p_fields;                   /* 寄存器所有字段 */
-
-    DPP_REG_WRITE      p_write_fun;          /* 寄存器写函数 */
-    DPP_REG_READ       p_read_fun;           /* 寄存器读函数 */
-}DPP_REG_T;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-
-
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_reg_struct.h
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 石金锋
+* 完成日期 : 2014/02/10
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#ifndef _DPP_REG_STRUCT_H_
+#define _DPP_REG_STRUCT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "zxic_common.h"
+#include "dpp_dev.h"
+#include "dpp_type_api.h"
+
+typedef ZXIC_UINT32 (*DPP_REG_WRITE)(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+									 ZXIC_UINT32 *p_data);
+typedef ZXIC_UINT32 (*DPP_REG_READ)(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+									ZXIC_UINT32 *p_data);
+
+#define DPP_FIELD_FLAG_RO (1 << 0) /* 只读标志 */
+#define DPP_FIELD_FLAG_RW (1 << 1) /* 读写标志 */
+#define DPP_FIELD_FLAG_RC (1 << 2) /* 读清标志 */
+#define DPP_FIELD_FLAG_WO (1 << 3) /* 只写标志 */
+#define DPP_FIELD_FLAG_WC (1 << 4) /* 写清标志 */
+
+typedef struct dpp_field_t {
+	ZXIC_CHAR *p_name; /* 字段名 */
+	ZXIC_UINT32 flags; /* 标志位 */
+	ZXIC_UINT16 msb_pos; /* 最高比特位置，以寄存器列表为准*/
+	ZXIC_UINT16 len; /* 字段长度，以比特为单位 */
+	ZXIC_UINT32 default_value; /* 缺省值 */
+	ZXIC_UINT32 default_step; /* 缺省值步长*/
+} DPP_FIELD_T;
+
+#define DPP_REG_FLAG_DIRECT (0 << 0) /* 直接读写寄存器 */
+#define DPP_REG_FLAG_INDIRECT (1 << 0) /* 间接读写寄存器 */
+#define DPP_REG_FLAG_WO (1 << 1) /* 只写寄存器 */
+
+#define DPP_REG_NUL_ARRAY (0 << 0) /*零元寄存器序列 */
+#define DPP_REG_UNI_ARRAY (1 << 0) /*一元寄存器序列 */
+#define DPP_REG_BIN_ARRAY (1 << 1) /*二元寄存器序列 */
+
+typedef struct dpp_reg_t {
+	ZXIC_CHAR *reg_name; /* 寄存器名称*/
+	ZXIC_UINT32 reg_no; /* 寄存器的编号 */
+	ZXIC_UINT32 module_no; /* 寄存器归属的模块的编号 */
+	ZXIC_UINT32 flags; /* 标志位 */
+	ZXIC_UINT32 array_type; /* 寄存器偏移类型*/
+	ZXIC_UINT32 addr; /* 寄存器的芯片地址*/
+	ZXIC_UINT32 width; /* 寄存器位宽，以字节为单位 */
+	ZXIC_UINT32 m_size; /* 寄存器序列参数1的个数 */
+	ZXIC_UINT32 n_size; /* 寄存器序列参数2的个数*/
+	ZXIC_UINT32 m_step; /* 寄存器序列参数1的偏移步长 */
+	ZXIC_UINT32 n_step; /* 寄存器序列参数2的偏移步长 */
+	ZXIC_UINT32 field_num; /* 包含的字段个数 */
+	DPP_FIELD_T *p_fields; /* 寄存器所有字段 */
+
+	DPP_REG_WRITE p_write_fun; /* 寄存器写函数 */
+	DPP_REG_READ p_read_fun; /* 寄存器读函数 */
+} DPP_REG_T;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_se4k_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_se4k_reg.h
index 4ab258c90ccdbb23e0a3a7680da4bee0912243fc..f3dc4efc6e036d36c76e716d16bb8fe1472d4fb3 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_se4k_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_se4k_reg.h
@@ -3,332 +3,277 @@
 #define _DPP_SE4K_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_se4k_se_alg_cpu_cmd_rgt_t
-{
-    ZXIC_UINT32 rd_flag;
-    ZXIC_UINT32 mask;
-    ZXIC_UINT32 reg_sram_flag;
-    ZXIC_UINT32 zgroup_id;
-    ZXIC_UINT32 zblock_id;
-    ZXIC_UINT32 zcell_id;
-    ZXIC_UINT32 addr;
-}DPP_SE4K_SE_ALG_CPU_CMD_RGT_T;
-
-typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp0_t
-{
-    ZXIC_UINT32 cpu_wr_data_tmp0;
-}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP0_T;
-
-typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp1_t
-{
-    ZXIC_UINT32 cpu_wr_data_tmp1;
-}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP1_T;
-
-typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp2_t
-{
-    ZXIC_UINT32 cpu_wr_data_tmp2;
-}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP2_T;
-
-typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp3_t
-{
-    ZXIC_UINT32 cpu_wr_data_tmp3;
-}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP3_T;
-
-typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp4_t
-{
-    ZXIC_UINT32 cpu_wr_data_tmp4;
-}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP4_T;
-
-typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp5_t
-{
-    ZXIC_UINT32 cpu_wr_data_tmp5;
-}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP5_T;
-
-typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp6_t
-{
-    ZXIC_UINT32 cpu_wr_data_tmp6;
-}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP6_T;
-
-typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp7_t
-{
-    ZXIC_UINT32 cpu_wr_data_tmp7;
-}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP7_T;
-
-typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp8_t
-{
-    ZXIC_UINT32 cpu_wr_data_tmp8;
-}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP8_T;
-
-typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp9_t
-{
-    ZXIC_UINT32 cpu_wr_data_tmp9;
-}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP9_T;
-
-typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp10_t
-{
-    ZXIC_UINT32 cpu_wr_data_tmp10;
-}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP10_T;
-
-typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp11_t
-{
-    ZXIC_UINT32 cpu_wr_data_tmp11;
-}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP11_T;
-
-typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp12_t
-{
-    ZXIC_UINT32 cpu_wr_data_tmp12;
-}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP12_T;
-
-typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp13_t
-{
-    ZXIC_UINT32 cpu_wr_data_tmp13;
-}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP13_T;
-
-typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp14_t
-{
-    ZXIC_UINT32 cpu_wr_data_tmp14;
-}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP14_T;
-
-typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp15_t
-{
-    ZXIC_UINT32 cpu_wr_data_tmp15;
-}DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP15_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_rdy_t
-{
-    ZXIC_UINT32 cpu_rd_rdy;
-}DPP_SE4K_SE_ALG_CPU_RD_RDY_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp0_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp0;
-}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP0_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp1_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp1;
-}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP1_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp2_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp2;
-}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP2_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp3_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp3;
-}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP3_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp4_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp4;
-}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP4_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp5_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp5;
-}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP5_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp6_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp6;
-}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP6_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp7_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp7;
-}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP7_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp8_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp8;
-}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP8_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp9_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp9;
-}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP9_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp10_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp10;
-}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP10_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp11_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp11;
-}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP11_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp12_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp12;
-}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP12_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp13_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp13;
-}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP13_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp14_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp14;
-}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP14_T;
-
-typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp15_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp15;
-}DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP15_T;
-
-typedef struct dpp_se4k_se_alg_hash0_ext_cfg_rgt_t
-{
-    ZXIC_UINT32 hash0_ext_mode;
-    ZXIC_UINT32 hash0_ext_flag;
-}DPP_SE4K_SE_ALG_HASH0_EXT_CFG_RGT_T;
-
-typedef struct dpp_se4k_se_alg_hash1_ext_cfg_rgt_t
-{
-    ZXIC_UINT32 hash1_ext_mode;
-    ZXIC_UINT32 hash1_ext_flag;
-}DPP_SE4K_SE_ALG_HASH1_EXT_CFG_RGT_T;
-
-typedef struct dpp_se4k_se_alg_hash2_ext_cfg_rgt_t
-{
-    ZXIC_UINT32 hash2_ext_mode;
-    ZXIC_UINT32 hash2_ext_flag;
-}DPP_SE4K_SE_ALG_HASH2_EXT_CFG_RGT_T;
-
-typedef struct dpp_se4k_se_alg_hash3_ext_cfg_rgt_t
-{
-    ZXIC_UINT32 hash3_ext_mode;
-    ZXIC_UINT32 hash3_ext_flag;
-}DPP_SE4K_SE_ALG_HASH3_EXT_CFG_RGT_T;
-
-typedef struct dpp_se4k_se_alg_hash0_tbl30_depth_t
-{
-    ZXIC_UINT32 hash0_tbl3_depth;
-    ZXIC_UINT32 hash0_tbl2_depth;
-    ZXIC_UINT32 hash0_tbl1_depth;
-    ZXIC_UINT32 hash0_tbl0_depth;
-}DPP_SE4K_SE_ALG_HASH0_TBL30_DEPTH_T;
-
-typedef struct dpp_se4k_se_alg_hash0_tbl74_depth_t
-{
-    ZXIC_UINT32 hash0_tbl7_depth;
-    ZXIC_UINT32 hash0_tbl6_depth;
-    ZXIC_UINT32 hash0_tbl5_depth;
-    ZXIC_UINT32 hash0_tbl4_depth;
-}DPP_SE4K_SE_ALG_HASH0_TBL74_DEPTH_T;
-
-typedef struct dpp_se4k_se_alg_hash1_tbl30_depth_t
-{
-    ZXIC_UINT32 hash1_tbl3_depth;
-    ZXIC_UINT32 hash1_tbl2_depth;
-    ZXIC_UINT32 hash1_tbl1_depth;
-    ZXIC_UINT32 hash1_tbl0_depth;
-}DPP_SE4K_SE_ALG_HASH1_TBL30_DEPTH_T;
-
-typedef struct dpp_se4k_se_alg_hash1_tbl74_depth_t
-{
-    ZXIC_UINT32 hash1_tbl7_depth;
-    ZXIC_UINT32 hash1_tbl6_depth;
-    ZXIC_UINT32 hash1_tbl5_depth;
-    ZXIC_UINT32 hash1_tbl4_depth;
-}DPP_SE4K_SE_ALG_HASH1_TBL74_DEPTH_T;
-
-typedef struct dpp_se4k_se_alg_hash2_tbl30_depth_t
-{
-    ZXIC_UINT32 hash2_tbl3_depth;
-    ZXIC_UINT32 hash2_tbl2_depth;
-    ZXIC_UINT32 hash2_tbl1_depth;
-    ZXIC_UINT32 hash2_tbl0_depth;
-}DPP_SE4K_SE_ALG_HASH2_TBL30_DEPTH_T;
-
-typedef struct dpp_se4k_se_alg_hash2_tbl74_depth_t
-{
-    ZXIC_UINT32 hash2_tbl7_depth;
-    ZXIC_UINT32 hash2_tbl6_depth;
-    ZXIC_UINT32 hash2_tbl5_depth;
-    ZXIC_UINT32 hash2_tbl4_depth;
-}DPP_SE4K_SE_ALG_HASH2_TBL74_DEPTH_T;
-
-typedef struct dpp_se4k_se_alg_hash3_tbl30_depth_t
-{
-    ZXIC_UINT32 hash3_tbl3_depth;
-    ZXIC_UINT32 hash3_tbl2_depth;
-    ZXIC_UINT32 hash3_tbl1_depth;
-    ZXIC_UINT32 hash3_tbl0_depth;
-}DPP_SE4K_SE_ALG_HASH3_TBL30_DEPTH_T;
-
-typedef struct dpp_se4k_se_alg_hash3_tbl74_depth_t
-{
-    ZXIC_UINT32 hash3_tbl7_depth;
-    ZXIC_UINT32 hash3_tbl6_depth;
-    ZXIC_UINT32 hash3_tbl5_depth;
-    ZXIC_UINT32 hash3_tbl4_depth;
-}DPP_SE4K_SE_ALG_HASH3_TBL74_DEPTH_T;
-
-typedef struct dpp_se4k_se_alg_wr_rsp_cfg_t
-{
-    ZXIC_UINT32 wr_rsp_fifo_cfg;
-}DPP_SE4K_SE_ALG_WR_RSP_CFG_T;
-
-typedef struct dpp_se4k_se_alg_hash_mono_flag_t
-{
-    ZXIC_UINT32 hash3_mono_flag;
-    ZXIC_UINT32 hash2_mono_flag;
-    ZXIC_UINT32 hash1_mono_flag;
-    ZXIC_UINT32 hash0_mono_flag;
-}DPP_SE4K_SE_ALG_HASH_MONO_FLAG_T;
-
-typedef struct dpp_se4k_se_alg_hash10_ext_crc_cfg_t
-{
-    ZXIC_UINT32 hash1_crc_cfg;
-    ZXIC_UINT32 hash0_crc_cfg;
-}DPP_SE4K_SE_ALG_HASH10_EXT_CRC_CFG_T;
-
-typedef struct dpp_se4k_se_alg_hash32_ext_crc_cfg_t
-{
-    ZXIC_UINT32 hash3_crc_cfg;
-    ZXIC_UINT32 hash2_crc_cfg;
-}DPP_SE4K_SE_ALG_HASH32_EXT_CRC_CFG_T;
-
-typedef struct dpp_se4k_se_alg_zblock_service_configure_t
-{
-    ZXIC_UINT32 service_sel;
-    ZXIC_UINT32 hash_channel_sel;
-    ZXIC_UINT32 st_en;
-}DPP_SE4K_SE_ALG_ZBLOCK_SERVICE_CONFIGURE_T;
-
-typedef struct dpp_se4k_se_alg_zblock_hash_zcell_mono_t
-{
-    ZXIC_UINT32 ha_zcell3_mono_flag;
-    ZXIC_UINT32 ha_zcell3_tbl_id;
-    ZXIC_UINT32 ha_zcell2_mono_flag;
-    ZXIC_UINT32 ha_zcell2_tbl_id;
-    ZXIC_UINT32 ha_zcell1_mono_flag;
-    ZXIC_UINT32 ha_zcell1_tbl_id;
-    ZXIC_UINT32 ha_zcell0_mono_flag;
-    ZXIC_UINT32 ha_zcell0_tbl_id;
-}DPP_SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONO_T;
-
-typedef struct dpp_se4k_se_alg_zlock_hash_zreg_mono_t
-{
-    ZXIC_UINT32 ha_zreg3_mono_flag;
-    ZXIC_UINT32 ha_zreg3_tbl_id;
-    ZXIC_UINT32 ha_zreg2_mono_flag;
-    ZXIC_UINT32 ha_zreg2_tbl_id;
-    ZXIC_UINT32 ha_zreg1_mono_flag;
-    ZXIC_UINT32 ha_zreg1_tbl_id;
-    ZXIC_UINT32 ha_zreg0_mono_flag;
-    ZXIC_UINT32 ha_zreg0_tbl_id;
-}DPP_SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONO_T;
+typedef struct dpp_se4k_se_alg_cpu_cmd_rgt_t {
+	ZXIC_UINT32 rd_flag;
+	ZXIC_UINT32 mask;
+	ZXIC_UINT32 reg_sram_flag;
+	ZXIC_UINT32 zgroup_id;
+	ZXIC_UINT32 zblock_id;
+	ZXIC_UINT32 zcell_id;
+	ZXIC_UINT32 addr;
+} DPP_SE4K_SE_ALG_CPU_CMD_RGT_T;
 
+typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp0_t {
+	ZXIC_UINT32 cpu_wr_data_tmp0;
+} DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP0_T;
+
+typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp1_t {
+	ZXIC_UINT32 cpu_wr_data_tmp1;
+} DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP1_T;
+
+typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp2_t {
+	ZXIC_UINT32 cpu_wr_data_tmp2;
+} DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP2_T;
+
+typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp3_t {
+	ZXIC_UINT32 cpu_wr_data_tmp3;
+} DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP3_T;
+
+typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp4_t {
+	ZXIC_UINT32 cpu_wr_data_tmp4;
+} DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP4_T;
+
+typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp5_t {
+	ZXIC_UINT32 cpu_wr_data_tmp5;
+} DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP5_T;
+
+typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp6_t {
+	ZXIC_UINT32 cpu_wr_data_tmp6;
+} DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP6_T;
+
+typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp7_t {
+	ZXIC_UINT32 cpu_wr_data_tmp7;
+} DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP7_T;
+
+typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp8_t {
+	ZXIC_UINT32 cpu_wr_data_tmp8;
+} DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP8_T;
+
+typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp9_t {
+	ZXIC_UINT32 cpu_wr_data_tmp9;
+} DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP9_T;
+
+typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp10_t {
+	ZXIC_UINT32 cpu_wr_data_tmp10;
+} DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP10_T;
+
+typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp11_t {
+	ZXIC_UINT32 cpu_wr_data_tmp11;
+} DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP11_T;
+
+typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp12_t {
+	ZXIC_UINT32 cpu_wr_data_tmp12;
+} DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP12_T;
+
+typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp13_t {
+	ZXIC_UINT32 cpu_wr_data_tmp13;
+} DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP13_T;
+
+typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp14_t {
+	ZXIC_UINT32 cpu_wr_data_tmp14;
+} DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP14_T;
+
+typedef struct dpp_se4k_se_alg_cpu_wr_data_tmp15_t {
+	ZXIC_UINT32 cpu_wr_data_tmp15;
+} DPP_SE4K_SE_ALG_CPU_WR_DATA_TMP15_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_rdy_t {
+	ZXIC_UINT32 cpu_rd_rdy;
+} DPP_SE4K_SE_ALG_CPU_RD_RDY_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp0_t {
+	ZXIC_UINT32 cpu_rd_data_tmp0;
+} DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP0_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp1_t {
+	ZXIC_UINT32 cpu_rd_data_tmp1;
+} DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP1_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp2_t {
+	ZXIC_UINT32 cpu_rd_data_tmp2;
+} DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP2_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp3_t {
+	ZXIC_UINT32 cpu_rd_data_tmp3;
+} DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP3_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp4_t {
+	ZXIC_UINT32 cpu_rd_data_tmp4;
+} DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP4_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp5_t {
+	ZXIC_UINT32 cpu_rd_data_tmp5;
+} DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP5_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp6_t {
+	ZXIC_UINT32 cpu_rd_data_tmp6;
+} DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP6_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp7_t {
+	ZXIC_UINT32 cpu_rd_data_tmp7;
+} DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP7_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp8_t {
+	ZXIC_UINT32 cpu_rd_data_tmp8;
+} DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP8_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp9_t {
+	ZXIC_UINT32 cpu_rd_data_tmp9;
+} DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP9_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp10_t {
+	ZXIC_UINT32 cpu_rd_data_tmp10;
+} DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP10_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp11_t {
+	ZXIC_UINT32 cpu_rd_data_tmp11;
+} DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP11_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp12_t {
+	ZXIC_UINT32 cpu_rd_data_tmp12;
+} DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP12_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp13_t {
+	ZXIC_UINT32 cpu_rd_data_tmp13;
+} DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP13_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp14_t {
+	ZXIC_UINT32 cpu_rd_data_tmp14;
+} DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP14_T;
+
+typedef struct dpp_se4k_se_alg_cpu_rd_data_tmp15_t {
+	ZXIC_UINT32 cpu_rd_data_tmp15;
+} DPP_SE4K_SE_ALG_CPU_RD_DATA_TMP15_T;
+
+typedef struct dpp_se4k_se_alg_hash0_ext_cfg_rgt_t {
+	ZXIC_UINT32 hash0_ext_mode;
+	ZXIC_UINT32 hash0_ext_flag;
+} DPP_SE4K_SE_ALG_HASH0_EXT_CFG_RGT_T;
+
+typedef struct dpp_se4k_se_alg_hash1_ext_cfg_rgt_t {
+	ZXIC_UINT32 hash1_ext_mode;
+	ZXIC_UINT32 hash1_ext_flag;
+} DPP_SE4K_SE_ALG_HASH1_EXT_CFG_RGT_T;
+
+typedef struct dpp_se4k_se_alg_hash2_ext_cfg_rgt_t {
+	ZXIC_UINT32 hash2_ext_mode;
+	ZXIC_UINT32 hash2_ext_flag;
+} DPP_SE4K_SE_ALG_HASH2_EXT_CFG_RGT_T;
+
+typedef struct dpp_se4k_se_alg_hash3_ext_cfg_rgt_t {
+	ZXIC_UINT32 hash3_ext_mode;
+	ZXIC_UINT32 hash3_ext_flag;
+} DPP_SE4K_SE_ALG_HASH3_EXT_CFG_RGT_T;
+
+typedef struct dpp_se4k_se_alg_hash0_tbl30_depth_t {
+	ZXIC_UINT32 hash0_tbl3_depth;
+	ZXIC_UINT32 hash0_tbl2_depth;
+	ZXIC_UINT32 hash0_tbl1_depth;
+	ZXIC_UINT32 hash0_tbl0_depth;
+} DPP_SE4K_SE_ALG_HASH0_TBL30_DEPTH_T;
+
+typedef struct dpp_se4k_se_alg_hash0_tbl74_depth_t {
+	ZXIC_UINT32 hash0_tbl7_depth;
+	ZXIC_UINT32 hash0_tbl6_depth;
+	ZXIC_UINT32 hash0_tbl5_depth;
+	ZXIC_UINT32 hash0_tbl4_depth;
+} DPP_SE4K_SE_ALG_HASH0_TBL74_DEPTH_T;
+
+typedef struct dpp_se4k_se_alg_hash1_tbl30_depth_t {
+	ZXIC_UINT32 hash1_tbl3_depth;
+	ZXIC_UINT32 hash1_tbl2_depth;
+	ZXIC_UINT32 hash1_tbl1_depth;
+	ZXIC_UINT32 hash1_tbl0_depth;
+} DPP_SE4K_SE_ALG_HASH1_TBL30_DEPTH_T;
+
+typedef struct dpp_se4k_se_alg_hash1_tbl74_depth_t {
+	ZXIC_UINT32 hash1_tbl7_depth;
+	ZXIC_UINT32 hash1_tbl6_depth;
+	ZXIC_UINT32 hash1_tbl5_depth;
+	ZXIC_UINT32 hash1_tbl4_depth;
+} DPP_SE4K_SE_ALG_HASH1_TBL74_DEPTH_T;
+
+typedef struct dpp_se4k_se_alg_hash2_tbl30_depth_t {
+	ZXIC_UINT32 hash2_tbl3_depth;
+	ZXIC_UINT32 hash2_tbl2_depth;
+	ZXIC_UINT32 hash2_tbl1_depth;
+	ZXIC_UINT32 hash2_tbl0_depth;
+} DPP_SE4K_SE_ALG_HASH2_TBL30_DEPTH_T;
+
+typedef struct dpp_se4k_se_alg_hash2_tbl74_depth_t {
+	ZXIC_UINT32 hash2_tbl7_depth;
+	ZXIC_UINT32 hash2_tbl6_depth;
+	ZXIC_UINT32 hash2_tbl5_depth;
+	ZXIC_UINT32 hash2_tbl4_depth;
+} DPP_SE4K_SE_ALG_HASH2_TBL74_DEPTH_T;
+
+typedef struct dpp_se4k_se_alg_hash3_tbl30_depth_t {
+	ZXIC_UINT32 hash3_tbl3_depth;
+	ZXIC_UINT32 hash3_tbl2_depth;
+	ZXIC_UINT32 hash3_tbl1_depth;
+	ZXIC_UINT32 hash3_tbl0_depth;
+} DPP_SE4K_SE_ALG_HASH3_TBL30_DEPTH_T;
+
+typedef struct dpp_se4k_se_alg_hash3_tbl74_depth_t {
+	ZXIC_UINT32 hash3_tbl7_depth;
+	ZXIC_UINT32 hash3_tbl6_depth;
+	ZXIC_UINT32 hash3_tbl5_depth;
+	ZXIC_UINT32 hash3_tbl4_depth;
+} DPP_SE4K_SE_ALG_HASH3_TBL74_DEPTH_T;
+
+typedef struct dpp_se4k_se_alg_wr_rsp_cfg_t {
+	ZXIC_UINT32 wr_rsp_fifo_cfg;
+} DPP_SE4K_SE_ALG_WR_RSP_CFG_T;
+
+typedef struct dpp_se4k_se_alg_hash_mono_flag_t {
+	ZXIC_UINT32 hash3_mono_flag;
+	ZXIC_UINT32 hash2_mono_flag;
+	ZXIC_UINT32 hash1_mono_flag;
+	ZXIC_UINT32 hash0_mono_flag;
+} DPP_SE4K_SE_ALG_HASH_MONO_FLAG_T;
+
+typedef struct dpp_se4k_se_alg_hash10_ext_crc_cfg_t {
+	ZXIC_UINT32 hash1_crc_cfg;
+	ZXIC_UINT32 hash0_crc_cfg;
+} DPP_SE4K_SE_ALG_HASH10_EXT_CRC_CFG_T;
+
+typedef struct dpp_se4k_se_alg_hash32_ext_crc_cfg_t {
+	ZXIC_UINT32 hash3_crc_cfg;
+	ZXIC_UINT32 hash2_crc_cfg;
+} DPP_SE4K_SE_ALG_HASH32_EXT_CRC_CFG_T;
+
+typedef struct dpp_se4k_se_alg_zblock_service_configure_t {
+	ZXIC_UINT32 service_sel;
+	ZXIC_UINT32 hash_channel_sel;
+	ZXIC_UINT32 st_en;
+} DPP_SE4K_SE_ALG_ZBLOCK_SERVICE_CONFIGURE_T;
+
+typedef struct dpp_se4k_se_alg_zblock_hash_zcell_mono_t {
+	ZXIC_UINT32 ha_zcell3_mono_flag;
+	ZXIC_UINT32 ha_zcell3_tbl_id;
+	ZXIC_UINT32 ha_zcell2_mono_flag;
+	ZXIC_UINT32 ha_zcell2_tbl_id;
+	ZXIC_UINT32 ha_zcell1_mono_flag;
+	ZXIC_UINT32 ha_zcell1_tbl_id;
+	ZXIC_UINT32 ha_zcell0_mono_flag;
+	ZXIC_UINT32 ha_zcell0_tbl_id;
+} DPP_SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONO_T;
+
+typedef struct dpp_se4k_se_alg_zlock_hash_zreg_mono_t {
+	ZXIC_UINT32 ha_zreg3_mono_flag;
+	ZXIC_UINT32 ha_zreg3_tbl_id;
+	ZXIC_UINT32 ha_zreg2_mono_flag;
+	ZXIC_UINT32 ha_zreg2_tbl_id;
+	ZXIC_UINT32 ha_zreg1_mono_flag;
+	ZXIC_UINT32 ha_zreg1_tbl_id;
+	ZXIC_UINT32 ha_zreg0_mono_flag;
+	ZXIC_UINT32 ha_zreg0_tbl_id;
+} DPP_SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONO_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_se_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_se_reg.h
index 2328ea6ab804f8016175ec67bd96cb21bf53c026..064f1ba96066fa78f7538d35de26a34f64ebee65 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_se_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_se_reg.h
@@ -3,3436 +3,2776 @@
 #define _DPP_SE_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_se_alg_init_ok_t
-{
-    ZXIC_UINT32 init_ok;
-}DPP_SE_ALG_INIT_OK_T;
-
-typedef struct dpp_se_alg_cpu_rd_rdy_t
-{
-    ZXIC_UINT32 cpu_rd_rdy;
-}DPP_SE_ALG_CPU_RD_RDY_T;
-
-typedef struct dpp_se_alg_cpu_rd_data_tmp0_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp0;
-}DPP_SE_ALG_CPU_RD_DATA_TMP0_T;
-
-typedef struct dpp_se_alg_cpu_rd_data_tmp1_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp1;
-}DPP_SE_ALG_CPU_RD_DATA_TMP1_T;
-
-typedef struct dpp_se_alg_cpu_rd_data_tmp2_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp2;
-}DPP_SE_ALG_CPU_RD_DATA_TMP2_T;
-
-typedef struct dpp_se_alg_cpu_rd_data_tmp3_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp3;
-}DPP_SE_ALG_CPU_RD_DATA_TMP3_T;
-
-typedef struct dpp_se_alg_cpu_rd_data_tmp4_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp4;
-}DPP_SE_ALG_CPU_RD_DATA_TMP4_T;
-
-typedef struct dpp_se_alg_cpu_rd_data_tmp5_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp5;
-}DPP_SE_ALG_CPU_RD_DATA_TMP5_T;
-
-typedef struct dpp_se_alg_cpu_rd_data_tmp6_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp6;
-}DPP_SE_ALG_CPU_RD_DATA_TMP6_T;
-
-typedef struct dpp_se_alg_cpu_rd_data_tmp7_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp7;
-}DPP_SE_ALG_CPU_RD_DATA_TMP7_T;
-
-typedef struct dpp_se_alg_cpu_rd_data_tmp8_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp8;
-}DPP_SE_ALG_CPU_RD_DATA_TMP8_T;
-
-typedef struct dpp_se_alg_cpu_rd_data_tmp9_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp9;
-}DPP_SE_ALG_CPU_RD_DATA_TMP9_T;
-
-typedef struct dpp_se_alg_cpu_rd_data_tmp10_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp10;
-}DPP_SE_ALG_CPU_RD_DATA_TMP10_T;
-
-typedef struct dpp_se_alg_cpu_rd_data_tmp11_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp11;
-}DPP_SE_ALG_CPU_RD_DATA_TMP11_T;
-
-typedef struct dpp_se_alg_cpu_rd_data_tmp12_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp12;
-}DPP_SE_ALG_CPU_RD_DATA_TMP12_T;
-
-typedef struct dpp_se_alg_cpu_rd_data_tmp13_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp13;
-}DPP_SE_ALG_CPU_RD_DATA_TMP13_T;
-
-typedef struct dpp_se_alg_cpu_rd_data_tmp14_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp14;
-}DPP_SE_ALG_CPU_RD_DATA_TMP14_T;
-
-typedef struct dpp_se_alg_cpu_rd_data_tmp15_t
-{
-    ZXIC_UINT32 cpu_rd_data_tmp15;
-}DPP_SE_ALG_CPU_RD_DATA_TMP15_T;
-
-typedef struct dpp_se_alg_lpm_v4_config_rgt_t
-{
-    ZXIC_UINT32 lpm_v4_shift_sel;
-    ZXIC_UINT32 lpm_v4_sram_cmp_flag;
-    ZXIC_UINT32 lpm_v4_ddr3_addr_sel;
-}DPP_SE_ALG_LPM_V4_CONFIG_RGT_T;
-
-typedef struct dpp_se_alg_lpm_v6_config_rgt_t
-{
-    ZXIC_UINT32 lpm_v6_shift_sel;
-    ZXIC_UINT32 lpm_v6_sram_cmp_flag;
-    ZXIC_UINT32 lpm_v6_ddr3_addr_sel;
-}DPP_SE_ALG_LPM_V6_CONFIG_RGT_T;
-
-typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u0_pfull_ast_t
-{
-    ZXIC_UINT32 lpm_ext_rsp_fifo_u0_pfull_ast;
-}DPP_SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_AST_T;
-
-typedef struct dpp_se_as_hash_age_pat_cfg_t
-{
-    ZXIC_UINT32 hash_age_pat_cfg;
-}DPP_SE_AS_HASH_AGE_PAT_CFG_T;
-
-typedef struct dpp_se_as_learn_rdy_cfg_t
-{
-    ZXIC_UINT32 learn_rdy_cfg;
-}DPP_SE_AS_LEARN_RDY_CFG_T;
-
-typedef struct dpp_se_kschd_kschd_as_pful_cfg_t
-{
-    ZXIC_UINT32 kschd_as_pful_cfg;
-}DPP_SE_KSCHD_KSCHD_AS_PFUL_CFG_T;
-
-typedef struct dpp_se_kschd_kschd_dir_pful_cfg_t
-{
-    ZXIC_UINT32 kschd_dir_pful_cfg;
-}DPP_SE_KSCHD_KSCHD_DIR_PFUL_CFG_T;
-
-typedef struct dpp_se_kschd_kschd_as_ept_cfg_t
-{
-    ZXIC_UINT32 kschd_as_ept_cfg;
-}DPP_SE_KSCHD_KSCHD_AS_EPT_CFG_T;
-
-typedef struct dpp_se_kschd_cpu_arbi_pful_cfg_t
-{
-    ZXIC_UINT32 cpu_arbi_pful_cfg;
-}DPP_SE_KSCHD_CPU_ARBI_PFUL_CFG_T;
-
-typedef struct dpp_se_kschd_kschd_pbu_pful_cfg_t
-{
-    ZXIC_UINT32 kschd_pbu_pful_cfg;
-}DPP_SE_KSCHD_KSCHD_PBU_PFUL_CFG_T;
-
-typedef struct dpp_se_rschd_rschd_dir_pful_cfg_t
-{
-    ZXIC_UINT32 rschd_dir_pful_cfg;
-}DPP_SE_RSCHD_RSCHD_DIR_PFUL_CFG_T;
-
-typedef struct dpp_se_rschd_rschd_dir_ept_cfg_t
-{
-    ZXIC_UINT32 rschd_dir_ept_cfg;
-}DPP_SE_RSCHD_RSCHD_DIR_EPT_CFG_T;
-
-typedef struct dpp_se_cfg_ppu_soft_rst_t
-{
-    ZXIC_UINT32 ppu_soft_rst;
-}DPP_SE_CFG_PPU_SOFT_RST_T;
-
-typedef struct dpp_se_cfg_ept_flag_t
-{
-    ZXIC_UINT32 ept_flag;
-}DPP_SE_CFG_EPT_FLAG_T;
-
-typedef struct dpp_se_cfg_ddr_key_lk0_3_t
-{
-    ZXIC_UINT32 ddr_key_lk0_3;
-}DPP_SE_CFG_DDR_KEY_LK0_3_T;
-
-typedef struct dpp_se_cfg_ddr_key_lk0_2_t
-{
-    ZXIC_UINT32 ddr_key_lk0_2;
-}DPP_SE_CFG_DDR_KEY_LK0_2_T;
-
-typedef struct dpp_se_cfg_ddr_key_lk0_1_t
-{
-    ZXIC_UINT32 ddr_key_lk0_1;
-}DPP_SE_CFG_DDR_KEY_LK0_1_T;
-
-typedef struct dpp_se_cfg_ddr_key_lk0_0_t
-{
-    ZXIC_UINT32 ddr_key_lk0_0;
-}DPP_SE_CFG_DDR_KEY_LK0_0_T;
-
-typedef struct dpp_se_cfg_ddr_key_lk1_3_t
-{
-    ZXIC_UINT32 ddr_key_lk1_3;
-}DPP_SE_CFG_DDR_KEY_LK1_3_T;
-
-typedef struct dpp_se_cfg_ddr_key_lk1_2_t
-{
-    ZXIC_UINT32 ddr_key_lk1_2;
-}DPP_SE_CFG_DDR_KEY_LK1_2_T;
-
-typedef struct dpp_se_cfg_ddr_key_lk1_1_t
-{
-    ZXIC_UINT32 ddr_key_lk1_1;
-}DPP_SE_CFG_DDR_KEY_LK1_1_T;
-
-typedef struct dpp_se_cfg_ddr_key_lk1_0_t
-{
-    ZXIC_UINT32 ddr_key_lk1_0;
-}DPP_SE_CFG_DDR_KEY_LK1_0_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_18_t
-{
-    ZXIC_UINT32 hash_key_lk0_18;
-}DPP_SE_CFG_HASH_KEY_LK0_18_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_17_t
-{
-    ZXIC_UINT32 hash_key_lk0_17;
-}DPP_SE_CFG_HASH_KEY_LK0_17_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_16_t
-{
-    ZXIC_UINT32 hash_key_lk0_16;
-}DPP_SE_CFG_HASH_KEY_LK0_16_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_15_t
-{
-    ZXIC_UINT32 hash_key_lk0_15;
-}DPP_SE_CFG_HASH_KEY_LK0_15_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_14_t
-{
-    ZXIC_UINT32 hash_key_lk0_14;
-}DPP_SE_CFG_HASH_KEY_LK0_14_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_13_t
-{
-    ZXIC_UINT32 hash_key_lk0_13;
-}DPP_SE_CFG_HASH_KEY_LK0_13_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_12_t
-{
-    ZXIC_UINT32 hash_key_lk0_12;
-}DPP_SE_CFG_HASH_KEY_LK0_12_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_11_t
-{
-    ZXIC_UINT32 hash_key_lk0_11;
-}DPP_SE_CFG_HASH_KEY_LK0_11_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_10_t
-{
-    ZXIC_UINT32 hash_key_lk0_10;
-}DPP_SE_CFG_HASH_KEY_LK0_10_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_9_t
-{
-    ZXIC_UINT32 hash_key_lk0_9;
-}DPP_SE_CFG_HASH_KEY_LK0_9_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_8_t
-{
-    ZXIC_UINT32 hash_key_lk0_8;
-}DPP_SE_CFG_HASH_KEY_LK0_8_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_7_t
-{
-    ZXIC_UINT32 hash_key_lk0_7;
-}DPP_SE_CFG_HASH_KEY_LK0_7_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_6_t
-{
-    ZXIC_UINT32 hash_key_lk0_6;
-}DPP_SE_CFG_HASH_KEY_LK0_6_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_5_t
-{
-    ZXIC_UINT32 hash_key_lk0_5;
-}DPP_SE_CFG_HASH_KEY_LK0_5_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_4_t
-{
-    ZXIC_UINT32 hash_key_lk0_4;
-}DPP_SE_CFG_HASH_KEY_LK0_4_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_3_t
-{
-    ZXIC_UINT32 hash_key_lk0_3;
-}DPP_SE_CFG_HASH_KEY_LK0_3_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_2_t
-{
-    ZXIC_UINT32 hash_key_lk0_2;
-}DPP_SE_CFG_HASH_KEY_LK0_2_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_1_t
-{
-    ZXIC_UINT32 hash_key_lk0_1;
-}DPP_SE_CFG_HASH_KEY_LK0_1_T;
-
-typedef struct dpp_se_cfg_hash_key_lk0_0_t
-{
-    ZXIC_UINT32 hash_key_lk0_0;
-}DPP_SE_CFG_HASH_KEY_LK0_0_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_18_t
-{
-    ZXIC_UINT32 hash_key_lk1_18;
-}DPP_SE_CFG_HASH_KEY_LK1_18_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_17_t
-{
-    ZXIC_UINT32 hash_key_lk1_17;
-}DPP_SE_CFG_HASH_KEY_LK1_17_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_16_t
-{
-    ZXIC_UINT32 hash_key_lk1_16;
-}DPP_SE_CFG_HASH_KEY_LK1_16_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_15_t
-{
-    ZXIC_UINT32 hash_key_lk1_15;
-}DPP_SE_CFG_HASH_KEY_LK1_15_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_14_t
-{
-    ZXIC_UINT32 hash_key_lk1_14;
-}DPP_SE_CFG_HASH_KEY_LK1_14_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_13_t
-{
-    ZXIC_UINT32 hash_key_lk1_13;
-}DPP_SE_CFG_HASH_KEY_LK1_13_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_12_t
-{
-    ZXIC_UINT32 hash_key_lk1_12;
-}DPP_SE_CFG_HASH_KEY_LK1_12_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_11_t
-{
-    ZXIC_UINT32 hash_key_lk1_11;
-}DPP_SE_CFG_HASH_KEY_LK1_11_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_10_t
-{
-    ZXIC_UINT32 hash_key_lk1_10;
-}DPP_SE_CFG_HASH_KEY_LK1_10_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_9_t
-{
-    ZXIC_UINT32 hash_key_lk1_9;
-}DPP_SE_CFG_HASH_KEY_LK1_9_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_8_t
-{
-    ZXIC_UINT32 hash_key_lk1_8;
-}DPP_SE_CFG_HASH_KEY_LK1_8_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_7_t
-{
-    ZXIC_UINT32 hash_key_lk1_7;
-}DPP_SE_CFG_HASH_KEY_LK1_7_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_6_t
-{
-    ZXIC_UINT32 hash_key_lk1_6;
-}DPP_SE_CFG_HASH_KEY_LK1_6_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_5_t
-{
-    ZXIC_UINT32 hash_key_lk1_5;
-}DPP_SE_CFG_HASH_KEY_LK1_5_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_4_t
-{
-    ZXIC_UINT32 hash_key_lk1_4;
-}DPP_SE_CFG_HASH_KEY_LK1_4_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_3_t
-{
-    ZXIC_UINT32 hash_key_lk1_3;
-}DPP_SE_CFG_HASH_KEY_LK1_3_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_2_t
-{
-    ZXIC_UINT32 hash_key_lk1_2;
-}DPP_SE_CFG_HASH_KEY_LK1_2_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_1_t
-{
-    ZXIC_UINT32 hash_key_lk1_1;
-}DPP_SE_CFG_HASH_KEY_LK1_1_T;
-
-typedef struct dpp_se_cfg_hash_key_lk1_0_t
-{
-    ZXIC_UINT32 hash_key_lk1_0;
-}DPP_SE_CFG_HASH_KEY_LK1_0_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_18_t
-{
-    ZXIC_UINT32 hash_key_lk2_18;
-}DPP_SE_CFG_HASH_KEY_LK2_18_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_17_t
-{
-    ZXIC_UINT32 hash_key_lk2_17;
-}DPP_SE_CFG_HASH_KEY_LK2_17_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_16_t
-{
-    ZXIC_UINT32 hash_key_lk2_16;
-}DPP_SE_CFG_HASH_KEY_LK2_16_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_15_t
-{
-    ZXIC_UINT32 hash_key_lk2_15;
-}DPP_SE_CFG_HASH_KEY_LK2_15_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_14_t
-{
-    ZXIC_UINT32 hash_key_lk2_14;
-}DPP_SE_CFG_HASH_KEY_LK2_14_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_13_t
-{
-    ZXIC_UINT32 hash_key_lk2_13;
-}DPP_SE_CFG_HASH_KEY_LK2_13_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_12_t
-{
-    ZXIC_UINT32 hash_key_lk2_12;
-}DPP_SE_CFG_HASH_KEY_LK2_12_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_11_t
-{
-    ZXIC_UINT32 hash_key_lk2_11;
-}DPP_SE_CFG_HASH_KEY_LK2_11_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_10_t
-{
-    ZXIC_UINT32 hash_key_lk2_10;
-}DPP_SE_CFG_HASH_KEY_LK2_10_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_9_t
-{
-    ZXIC_UINT32 hash_key_lk2_9;
-}DPP_SE_CFG_HASH_KEY_LK2_9_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_8_t
-{
-    ZXIC_UINT32 hash_key_lk2_8;
-}DPP_SE_CFG_HASH_KEY_LK2_8_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_7_t
-{
-    ZXIC_UINT32 hash_key_lk2_7;
-}DPP_SE_CFG_HASH_KEY_LK2_7_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_6_t
-{
-    ZXIC_UINT32 hash_key_lk2_6;
-}DPP_SE_CFG_HASH_KEY_LK2_6_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_5_t
-{
-    ZXIC_UINT32 hash_key_lk2_5;
-}DPP_SE_CFG_HASH_KEY_LK2_5_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_4_t
-{
-    ZXIC_UINT32 hash_key_lk2_4;
-}DPP_SE_CFG_HASH_KEY_LK2_4_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_3_t
-{
-    ZXIC_UINT32 hash_key_lk2_3;
-}DPP_SE_CFG_HASH_KEY_LK2_3_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_2_t
-{
-    ZXIC_UINT32 hash_key_lk2_2;
-}DPP_SE_CFG_HASH_KEY_LK2_2_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_1_t
-{
-    ZXIC_UINT32 hash_key_lk2_1;
-}DPP_SE_CFG_HASH_KEY_LK2_1_T;
-
-typedef struct dpp_se_cfg_hash_key_lk2_0_t
-{
-    ZXIC_UINT32 hash_key_lk2_0;
-}DPP_SE_CFG_HASH_KEY_LK2_0_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_18_t
-{
-    ZXIC_UINT32 hash_key_lk3_18;
-}DPP_SE_CFG_HASH_KEY_LK3_18_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_17_t
-{
-    ZXIC_UINT32 hash_key_lk3_17;
-}DPP_SE_CFG_HASH_KEY_LK3_17_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_16_t
-{
-    ZXIC_UINT32 hash_key_lk3_16;
-}DPP_SE_CFG_HASH_KEY_LK3_16_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_15_t
-{
-    ZXIC_UINT32 hash_key_lk3_15;
-}DPP_SE_CFG_HASH_KEY_LK3_15_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_14_t
-{
-    ZXIC_UINT32 hash_key_lk3_14;
-}DPP_SE_CFG_HASH_KEY_LK3_14_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_13_t
-{
-    ZXIC_UINT32 hash_key_lk3_13;
-}DPP_SE_CFG_HASH_KEY_LK3_13_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_12_t
-{
-    ZXIC_UINT32 hash_key_lk3_12;
-}DPP_SE_CFG_HASH_KEY_LK3_12_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_11_t
-{
-    ZXIC_UINT32 hash_key_lk3_11;
-}DPP_SE_CFG_HASH_KEY_LK3_11_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_10_t
-{
-    ZXIC_UINT32 hash_key_lk3_10;
-}DPP_SE_CFG_HASH_KEY_LK3_10_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_9_t
-{
-    ZXIC_UINT32 hash_key_lk3_9;
-}DPP_SE_CFG_HASH_KEY_LK3_9_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_8_t
-{
-    ZXIC_UINT32 hash_key_lk3_8;
-}DPP_SE_CFG_HASH_KEY_LK3_8_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_7_t
-{
-    ZXIC_UINT32 hash_key_lk3_7;
-}DPP_SE_CFG_HASH_KEY_LK3_7_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_6_t
-{
-    ZXIC_UINT32 hash_key_lk3_6;
-}DPP_SE_CFG_HASH_KEY_LK3_6_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_5_t
-{
-    ZXIC_UINT32 hash_key_lk3_5;
-}DPP_SE_CFG_HASH_KEY_LK3_5_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_4_t
-{
-    ZXIC_UINT32 hash_key_lk3_4;
-}DPP_SE_CFG_HASH_KEY_LK3_4_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_3_t
-{
-    ZXIC_UINT32 hash_key_lk3_3;
-}DPP_SE_CFG_HASH_KEY_LK3_3_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_2_t
-{
-    ZXIC_UINT32 hash_key_lk3_2;
-}DPP_SE_CFG_HASH_KEY_LK3_2_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_1_t
-{
-    ZXIC_UINT32 hash_key_lk3_1;
-}DPP_SE_CFG_HASH_KEY_LK3_1_T;
-
-typedef struct dpp_se_cfg_hash_key_lk3_0_t
-{
-    ZXIC_UINT32 hash_key_lk3_0;
-}DPP_SE_CFG_HASH_KEY_LK3_0_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk0_6_t
-{
-    ZXIC_UINT32 lpm_key_lk0_6;
-}DPP_SE_CFG_LPM_KEY_LK0_6_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk0_5_t
-{
-    ZXIC_UINT32 lpm_key_lk0_5;
-}DPP_SE_CFG_LPM_KEY_LK0_5_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk0_4_t
-{
-    ZXIC_UINT32 lpm_key_lk0_4;
-}DPP_SE_CFG_LPM_KEY_LK0_4_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk0_3_t
-{
-    ZXIC_UINT32 lpm_key_lk0_3;
-}DPP_SE_CFG_LPM_KEY_LK0_3_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk0_2_t
-{
-    ZXIC_UINT32 lpm_key_lk0_2;
-}DPP_SE_CFG_LPM_KEY_LK0_2_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk0_1_t
-{
-    ZXIC_UINT32 lpm_key_lk0_1;
-}DPP_SE_CFG_LPM_KEY_LK0_1_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk0_0_t
-{
-    ZXIC_UINT32 lpm_key_lk0_0;
-}DPP_SE_CFG_LPM_KEY_LK0_0_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk1_6_t
-{
-    ZXIC_UINT32 lpm_key_lk1_6;
-}DPP_SE_CFG_LPM_KEY_LK1_6_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk1_5_t
-{
-    ZXIC_UINT32 lpm_key_lk1_5;
-}DPP_SE_CFG_LPM_KEY_LK1_5_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk1_4_t
-{
-    ZXIC_UINT32 lpm_key_lk1_4;
-}DPP_SE_CFG_LPM_KEY_LK1_4_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk1_3_t
-{
-    ZXIC_UINT32 lpm_key_lk1_3;
-}DPP_SE_CFG_LPM_KEY_LK1_3_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk1_2_t
-{
-    ZXIC_UINT32 lpm_key_lk1_2;
-}DPP_SE_CFG_LPM_KEY_LK1_2_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk1_1_t
-{
-    ZXIC_UINT32 lpm_key_lk1_1;
-}DPP_SE_CFG_LPM_KEY_LK1_1_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk1_0_t
-{
-    ZXIC_UINT32 lpm_key_lk1_0;
-}DPP_SE_CFG_LPM_KEY_LK1_0_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk2_6_t
-{
-    ZXIC_UINT32 lpm_key_lk2_6;
-}DPP_SE_CFG_LPM_KEY_LK2_6_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk2_5_t
-{
-    ZXIC_UINT32 lpm_key_lk2_5;
-}DPP_SE_CFG_LPM_KEY_LK2_5_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk2_4_t
-{
-    ZXIC_UINT32 lpm_key_lk2_4;
-}DPP_SE_CFG_LPM_KEY_LK2_4_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk2_3_t
-{
-    ZXIC_UINT32 lpm_key_lk2_3;
-}DPP_SE_CFG_LPM_KEY_LK2_3_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk2_2_t
-{
-    ZXIC_UINT32 lpm_key_lk2_2;
-}DPP_SE_CFG_LPM_KEY_LK2_2_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk2_1_t
-{
-    ZXIC_UINT32 lpm_key_lk2_1;
-}DPP_SE_CFG_LPM_KEY_LK2_1_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk2_0_t
-{
-    ZXIC_UINT32 lpm_key_lk2_0;
-}DPP_SE_CFG_LPM_KEY_LK2_0_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk3_6_t
-{
-    ZXIC_UINT32 lpm_key_lk3_6;
-}DPP_SE_CFG_LPM_KEY_LK3_6_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk3_5_t
-{
-    ZXIC_UINT32 lpm_key_lk3_5;
-}DPP_SE_CFG_LPM_KEY_LK3_5_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk3_4_t
-{
-    ZXIC_UINT32 lpm_key_lk3_4;
-}DPP_SE_CFG_LPM_KEY_LK3_4_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk3_3_t
-{
-    ZXIC_UINT32 lpm_key_lk3_3;
-}DPP_SE_CFG_LPM_KEY_LK3_3_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk3_2_t
-{
-    ZXIC_UINT32 lpm_key_lk3_2;
-}DPP_SE_CFG_LPM_KEY_LK3_2_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk3_1_t
-{
-    ZXIC_UINT32 lpm_key_lk3_1;
-}DPP_SE_CFG_LPM_KEY_LK3_1_T;
-
-typedef struct dpp_se_cfg_lpm_key_lk3_0_t
-{
-    ZXIC_UINT32 lpm_key_lk3_0;
-}DPP_SE_CFG_LPM_KEY_LK3_0_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_22_t
-{
-    ZXIC_UINT32 etcam_key_lk0_22;
-}DPP_SE_CFG_ETCAM_KEY_LK0_22_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_21_t
-{
-    ZXIC_UINT32 etcam_key_lk0_21;
-}DPP_SE_CFG_ETCAM_KEY_LK0_21_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_20_t
-{
-    ZXIC_UINT32 etcam_key_lk0_20;
-}DPP_SE_CFG_ETCAM_KEY_LK0_20_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_19_t
-{
-    ZXIC_UINT32 etcam_key_lk0_19;
-}DPP_SE_CFG_ETCAM_KEY_LK0_19_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_18_t
-{
-    ZXIC_UINT32 etcam_key_lk0_18;
-}DPP_SE_CFG_ETCAM_KEY_LK0_18_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_17_t
-{
-    ZXIC_UINT32 etcam_key_lk0_17;
-}DPP_SE_CFG_ETCAM_KEY_LK0_17_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_16_t
-{
-    ZXIC_UINT32 etcam_key_lk0_16;
-}DPP_SE_CFG_ETCAM_KEY_LK0_16_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_15_t
-{
-    ZXIC_UINT32 etcam_key_lk0_15;
-}DPP_SE_CFG_ETCAM_KEY_LK0_15_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_14_t
-{
-    ZXIC_UINT32 etcam_key_lk0_14;
-}DPP_SE_CFG_ETCAM_KEY_LK0_14_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_13_t
-{
-    ZXIC_UINT32 etcam_key_lk0_13;
-}DPP_SE_CFG_ETCAM_KEY_LK0_13_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_12_t
-{
-    ZXIC_UINT32 etcam_key_lk0_12;
-}DPP_SE_CFG_ETCAM_KEY_LK0_12_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_11_t
-{
-    ZXIC_UINT32 etcam_key_lk0_11;
-}DPP_SE_CFG_ETCAM_KEY_LK0_11_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_10_t
-{
-    ZXIC_UINT32 etcam_key_lk0_10;
-}DPP_SE_CFG_ETCAM_KEY_LK0_10_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_9_t
-{
-    ZXIC_UINT32 etcam_key_lk0_9;
-}DPP_SE_CFG_ETCAM_KEY_LK0_9_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_8_t
-{
-    ZXIC_UINT32 etcam_key_lk0_8;
-}DPP_SE_CFG_ETCAM_KEY_LK0_8_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_7_t
-{
-    ZXIC_UINT32 etcam_key_lk0_7;
-}DPP_SE_CFG_ETCAM_KEY_LK0_7_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_6_t
-{
-    ZXIC_UINT32 etcam_key_lk0_6;
-}DPP_SE_CFG_ETCAM_KEY_LK0_6_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_5_t
-{
-    ZXIC_UINT32 etcam_key_lk0_5;
-}DPP_SE_CFG_ETCAM_KEY_LK0_5_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_4_t
-{
-    ZXIC_UINT32 etcam_key_lk0_4;
-}DPP_SE_CFG_ETCAM_KEY_LK0_4_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_3_t
-{
-    ZXIC_UINT32 etcam_key_lk0_3;
-}DPP_SE_CFG_ETCAM_KEY_LK0_3_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_2_t
-{
-    ZXIC_UINT32 etcam_key_lk0_2;
-}DPP_SE_CFG_ETCAM_KEY_LK0_2_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_1_t
-{
-    ZXIC_UINT32 etcam_key_lk0_1;
-}DPP_SE_CFG_ETCAM_KEY_LK0_1_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk0_0_t
-{
-    ZXIC_UINT32 etcam_key_lk0_0;
-}DPP_SE_CFG_ETCAM_KEY_LK0_0_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_22_t
-{
-    ZXIC_UINT32 etcam_key_lk1_22;
-}DPP_SE_CFG_ETCAM_KEY_LK1_22_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_21_t
-{
-    ZXIC_UINT32 etcam_key_lk1_21;
-}DPP_SE_CFG_ETCAM_KEY_LK1_21_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_20_t
-{
-    ZXIC_UINT32 etcam_key_lk1_20;
-}DPP_SE_CFG_ETCAM_KEY_LK1_20_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_19_t
-{
-    ZXIC_UINT32 etcam_key_lk1_19;
-}DPP_SE_CFG_ETCAM_KEY_LK1_19_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_18_t
-{
-    ZXIC_UINT32 etcam_key_lk1_18;
-}DPP_SE_CFG_ETCAM_KEY_LK1_18_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_17_t
-{
-    ZXIC_UINT32 etcam_key_lk1_17;
-}DPP_SE_CFG_ETCAM_KEY_LK1_17_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_16_t
-{
-    ZXIC_UINT32 etcam_key_lk1_16;
-}DPP_SE_CFG_ETCAM_KEY_LK1_16_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_15_t
-{
-    ZXIC_UINT32 etcam_key_lk1_15;
-}DPP_SE_CFG_ETCAM_KEY_LK1_15_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_14_t
-{
-    ZXIC_UINT32 etcam_key_lk1_14;
-}DPP_SE_CFG_ETCAM_KEY_LK1_14_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_13_t
-{
-    ZXIC_UINT32 etcam_key_lk1_13;
-}DPP_SE_CFG_ETCAM_KEY_LK1_13_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_12_t
-{
-    ZXIC_UINT32 etcam_key_lk1_12;
-}DPP_SE_CFG_ETCAM_KEY_LK1_12_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_11_t
-{
-    ZXIC_UINT32 etcam_key_lk1_11;
-}DPP_SE_CFG_ETCAM_KEY_LK1_11_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_10_t
-{
-    ZXIC_UINT32 etcam_key_lk1_10;
-}DPP_SE_CFG_ETCAM_KEY_LK1_10_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_9_t
-{
-    ZXIC_UINT32 etcam_key_lk1_9;
-}DPP_SE_CFG_ETCAM_KEY_LK1_9_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_8_t
-{
-    ZXIC_UINT32 etcam_key_lk1_8;
-}DPP_SE_CFG_ETCAM_KEY_LK1_8_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_7_t
-{
-    ZXIC_UINT32 etcam_key_lk1_7;
-}DPP_SE_CFG_ETCAM_KEY_LK1_7_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_6_t
-{
-    ZXIC_UINT32 etcam_key_lk1_6;
-}DPP_SE_CFG_ETCAM_KEY_LK1_6_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_5_t
-{
-    ZXIC_UINT32 etcam_key_lk1_5;
-}DPP_SE_CFG_ETCAM_KEY_LK1_5_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_4_t
-{
-    ZXIC_UINT32 etcam_key_lk1_4;
-}DPP_SE_CFG_ETCAM_KEY_LK1_4_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_3_t
-{
-    ZXIC_UINT32 etcam_key_lk1_3;
-}DPP_SE_CFG_ETCAM_KEY_LK1_3_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_2_t
-{
-    ZXIC_UINT32 etcam_key_lk1_2;
-}DPP_SE_CFG_ETCAM_KEY_LK1_2_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_1_t
-{
-    ZXIC_UINT32 etcam_key_lk1_1;
-}DPP_SE_CFG_ETCAM_KEY_LK1_1_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk1_0_t
-{
-    ZXIC_UINT32 etcam_key_lk1_0;
-}DPP_SE_CFG_ETCAM_KEY_LK1_0_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_22_t
-{
-    ZXIC_UINT32 etcam_key_lk2_22;
-}DPP_SE_CFG_ETCAM_KEY_LK2_22_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_21_t
-{
-    ZXIC_UINT32 etcam_key_lk2_21;
-}DPP_SE_CFG_ETCAM_KEY_LK2_21_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_20_t
-{
-    ZXIC_UINT32 etcam_key_lk2_20;
-}DPP_SE_CFG_ETCAM_KEY_LK2_20_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_19_t
-{
-    ZXIC_UINT32 etcam_key_lk2_19;
-}DPP_SE_CFG_ETCAM_KEY_LK2_19_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_18_t
-{
-    ZXIC_UINT32 etcam_key_lk2_18;
-}DPP_SE_CFG_ETCAM_KEY_LK2_18_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_17_t
-{
-    ZXIC_UINT32 etcam_key_lk2_17;
-}DPP_SE_CFG_ETCAM_KEY_LK2_17_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_16_t
-{
-    ZXIC_UINT32 etcam_key_lk2_16;
-}DPP_SE_CFG_ETCAM_KEY_LK2_16_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_15_t
-{
-    ZXIC_UINT32 etcam_key_lk2_15;
-}DPP_SE_CFG_ETCAM_KEY_LK2_15_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_14_t
-{
-    ZXIC_UINT32 etcam_key_lk2_14;
-}DPP_SE_CFG_ETCAM_KEY_LK2_14_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_13_t
-{
-    ZXIC_UINT32 etcam_key_lk2_13;
-}DPP_SE_CFG_ETCAM_KEY_LK2_13_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_12_t
-{
-    ZXIC_UINT32 etcam_key_lk2_12;
-}DPP_SE_CFG_ETCAM_KEY_LK2_12_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_11_t
-{
-    ZXIC_UINT32 etcam_key_lk2_11;
-}DPP_SE_CFG_ETCAM_KEY_LK2_11_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_10_t
-{
-    ZXIC_UINT32 etcam_key_lk2_10;
-}DPP_SE_CFG_ETCAM_KEY_LK2_10_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_9_t
-{
-    ZXIC_UINT32 etcam_key_lk2_9;
-}DPP_SE_CFG_ETCAM_KEY_LK2_9_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_8_t
-{
-    ZXIC_UINT32 etcam_key_lk2_8;
-}DPP_SE_CFG_ETCAM_KEY_LK2_8_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_7_t
-{
-    ZXIC_UINT32 etcam_key_lk2_7;
-}DPP_SE_CFG_ETCAM_KEY_LK2_7_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_6_t
-{
-    ZXIC_UINT32 etcam_key_lk2_6;
-}DPP_SE_CFG_ETCAM_KEY_LK2_6_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_5_t
-{
-    ZXIC_UINT32 etcam_key_lk2_5;
-}DPP_SE_CFG_ETCAM_KEY_LK2_5_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_4_t
-{
-    ZXIC_UINT32 etcam_key_lk2_4;
-}DPP_SE_CFG_ETCAM_KEY_LK2_4_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_3_t
-{
-    ZXIC_UINT32 etcam_key_lk2_3;
-}DPP_SE_CFG_ETCAM_KEY_LK2_3_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_2_t
-{
-    ZXIC_UINT32 etcam_key_lk2_2;
-}DPP_SE_CFG_ETCAM_KEY_LK2_2_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_1_t
-{
-    ZXIC_UINT32 etcam_key_lk2_1;
-}DPP_SE_CFG_ETCAM_KEY_LK2_1_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk2_0_t
-{
-    ZXIC_UINT32 etcam_key_lk2_0;
-}DPP_SE_CFG_ETCAM_KEY_LK2_0_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_22_t
-{
-    ZXIC_UINT32 etcam_key_lk3_22;
-}DPP_SE_CFG_ETCAM_KEY_LK3_22_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_21_t
-{
-    ZXIC_UINT32 etcam_key_lk3_21;
-}DPP_SE_CFG_ETCAM_KEY_LK3_21_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_20_t
-{
-    ZXIC_UINT32 etcam_key_lk3_20;
-}DPP_SE_CFG_ETCAM_KEY_LK3_20_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_19_t
-{
-    ZXIC_UINT32 etcam_key_lk3_19;
-}DPP_SE_CFG_ETCAM_KEY_LK3_19_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_18_t
-{
-    ZXIC_UINT32 etcam_key_lk3_18;
-}DPP_SE_CFG_ETCAM_KEY_LK3_18_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_17_t
-{
-    ZXIC_UINT32 etcam_key_lk3_17;
-}DPP_SE_CFG_ETCAM_KEY_LK3_17_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_16_t
-{
-    ZXIC_UINT32 etcam_key_lk3_16;
-}DPP_SE_CFG_ETCAM_KEY_LK3_16_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_15_t
-{
-    ZXIC_UINT32 etcam_key_lk3_15;
-}DPP_SE_CFG_ETCAM_KEY_LK3_15_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_14_t
-{
-    ZXIC_UINT32 etcam_key_lk3_14;
-}DPP_SE_CFG_ETCAM_KEY_LK3_14_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_13_t
-{
-    ZXIC_UINT32 etcam_key_lk3_13;
-}DPP_SE_CFG_ETCAM_KEY_LK3_13_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_12_t
-{
-    ZXIC_UINT32 etcam_key_lk3_12;
-}DPP_SE_CFG_ETCAM_KEY_LK3_12_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_11_t
-{
-    ZXIC_UINT32 etcam_key_lk3_11;
-}DPP_SE_CFG_ETCAM_KEY_LK3_11_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_10_t
-{
-    ZXIC_UINT32 etcam_key_lk3_10;
-}DPP_SE_CFG_ETCAM_KEY_LK3_10_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_9_t
-{
-    ZXIC_UINT32 etcam_key_lk3_9;
-}DPP_SE_CFG_ETCAM_KEY_LK3_9_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_8_t
-{
-    ZXIC_UINT32 etcam_key_lk3_8;
-}DPP_SE_CFG_ETCAM_KEY_LK3_8_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_7_t
-{
-    ZXIC_UINT32 etcam_key_lk3_7;
-}DPP_SE_CFG_ETCAM_KEY_LK3_7_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_6_t
-{
-    ZXIC_UINT32 etcam_key_lk3_6;
-}DPP_SE_CFG_ETCAM_KEY_LK3_6_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_5_t
-{
-    ZXIC_UINT32 etcam_key_lk3_5;
-}DPP_SE_CFG_ETCAM_KEY_LK3_5_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_4_t
-{
-    ZXIC_UINT32 etcam_key_lk3_4;
-}DPP_SE_CFG_ETCAM_KEY_LK3_4_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_3_t
-{
-    ZXIC_UINT32 etcam_key_lk3_3;
-}DPP_SE_CFG_ETCAM_KEY_LK3_3_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_2_t
-{
-    ZXIC_UINT32 etcam_key_lk3_2;
-}DPP_SE_CFG_ETCAM_KEY_LK3_2_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_1_t
-{
-    ZXIC_UINT32 etcam_key_lk3_1;
-}DPP_SE_CFG_ETCAM_KEY_LK3_1_T;
-
-typedef struct dpp_se_cfg_etcam_key_lk3_0_t
-{
-    ZXIC_UINT32 etcam_key_lk3_0;
-}DPP_SE_CFG_ETCAM_KEY_LK3_0_T;
-
-typedef struct dpp_se_cfg_pbu_key_lk0_3_t
-{
-    ZXIC_UINT32 pbu_key_lk0_3;
-}DPP_SE_CFG_PBU_KEY_LK0_3_T;
-
-typedef struct dpp_se_cfg_pbu_key_lk0_2_t
-{
-    ZXIC_UINT32 pbu_key_lk0_2;
-}DPP_SE_CFG_PBU_KEY_LK0_2_T;
-
-typedef struct dpp_se_cfg_pbu_key_lk0_1_t
-{
-    ZXIC_UINT32 pbu_key_lk0_1;
-}DPP_SE_CFG_PBU_KEY_LK0_1_T;
-
-typedef struct dpp_se_cfg_pbu_key_lk0_0_t
-{
-    ZXIC_UINT32 pbu_key_lk0_0;
-}DPP_SE_CFG_PBU_KEY_LK0_0_T;
-
-typedef struct dpp_se_cfg_pbu_key_lk1_3_t
-{
-    ZXIC_UINT32 pbu_key_lk1_3;
-}DPP_SE_CFG_PBU_KEY_LK1_3_T;
-
-typedef struct dpp_se_cfg_pbu_key_lk1_2_t
-{
-    ZXIC_UINT32 pbu_key_lk1_2;
-}DPP_SE_CFG_PBU_KEY_LK1_2_T;
-
-typedef struct dpp_se_cfg_pbu_key_lk1_1_t
-{
-    ZXIC_UINT32 pbu_key_lk1_1;
-}DPP_SE_CFG_PBU_KEY_LK1_1_T;
-
-typedef struct dpp_se_cfg_pbu_key_lk1_0_t
-{
-    ZXIC_UINT32 pbu_key_lk1_0;
-}DPP_SE_CFG_PBU_KEY_LK1_0_T;
-
-typedef struct dpp_se_cfg_pbu_key_lk2_3_t
-{
-    ZXIC_UINT32 pbu_key_lk2_3;
-}DPP_SE_CFG_PBU_KEY_LK2_3_T;
-
-typedef struct dpp_se_cfg_pbu_key_lk2_2_t
-{
-    ZXIC_UINT32 pbu_key_lk2_2;
-}DPP_SE_CFG_PBU_KEY_LK2_2_T;
-
-typedef struct dpp_se_cfg_pbu_key_lk2_1_t
-{
-    ZXIC_UINT32 pbu_key_lk2_1;
-}DPP_SE_CFG_PBU_KEY_LK2_1_T;
-
-typedef struct dpp_se_cfg_pbu_key_lk2_0_t
-{
-    ZXIC_UINT32 pbu_key_lk2_0;
-}DPP_SE_CFG_PBU_KEY_LK2_0_T;
-
-typedef struct dpp_se_cfg_pbu_key_lk3_3_t
-{
-    ZXIC_UINT32 pbu_key_lk3_3;
-}DPP_SE_CFG_PBU_KEY_LK3_3_T;
-
-typedef struct dpp_se_cfg_pbu_key_lk3_2_t
-{
-    ZXIC_UINT32 pbu_key_lk3_2;
-}DPP_SE_CFG_PBU_KEY_LK3_2_T;
-
-typedef struct dpp_se_cfg_pbu_key_lk3_1_t
-{
-    ZXIC_UINT32 pbu_key_lk3_1;
-}DPP_SE_CFG_PBU_KEY_LK3_1_T;
-
-typedef struct dpp_se_cfg_pbu_key_lk3_0_t
-{
-    ZXIC_UINT32 pbu_key_lk3_0;
-}DPP_SE_CFG_PBU_KEY_LK3_0_T;
-
-typedef struct dpp_se_alg_schd_learn_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 schd_learn_fifo_pfull_ast;
-}DPP_SE_ALG_SCHD_LEARN_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_schd_learn_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 schd_learn_fifo_pfull_neg;
-}DPP_SE_ALG_SCHD_LEARN_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_schd_hash0_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 schd_hash0_fifo_pfull_ast;
-}DPP_SE_ALG_SCHD_HASH0_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_schd_hash0_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 schd_hash0_fifo_pfull_neg;
-}DPP_SE_ALG_SCHD_HASH0_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_schd_hash1_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 schd_hash1_fifo_pfull_ast;
-}DPP_SE_ALG_SCHD_HASH1_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_schd_hash1_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 schd_hash1_fifo_pfull_neg;
-}DPP_SE_ALG_SCHD_HASH1_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_schd_hash2_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 schd_hash2_fifo_pfull_ast;
-}DPP_SE_ALG_SCHD_HASH2_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_schd_hash2_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 schd_hash2_fifo_pfull_neg;
-}DPP_SE_ALG_SCHD_HASH2_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_schd_hash3_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 schd_hash3_fifo_pfull_ast;
-}DPP_SE_ALG_SCHD_HASH3_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_schd_hash3_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 schd_hash3_fifo_pfull_neg;
-}DPP_SE_ALG_SCHD_HASH3_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_schd_lpm_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 schd_lpm_fifo_pfull_ast;
-}DPP_SE_ALG_SCHD_LPM_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_schd_lpm_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 schd_lpm_fifo_pfull_neg;
-}DPP_SE_ALG_SCHD_LPM_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_hash0_key_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 hash0_key_fifo_pfull_ast;
-}DPP_SE_ALG_HASH0_KEY_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_hash0_key_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 hash0_key_fifo_pfull_ast;
-}DPP_SE_ALG_HASH0_KEY_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_hash0_sreq_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 hash0_sreq_fifo_pfull_ast;
-}DPP_SE_ALG_HASH0_SREQ_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_hash0_sreq_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 hash0_sreq_fifo_pfull_neg;
-}DPP_SE_ALG_HASH0_SREQ_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_hash0_int_rsp_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 hash0_int_rsp_fifo_pfull_ast;
-}DPP_SE_ALG_HASH0_INT_RSP_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_hash0_int_rsp_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 hash0_int_rsp_fifo_pfull_neg;
-}DPP_SE_ALG_HASH0_INT_RSP_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_hash0_ext_rsp_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 hash0_ext_rsp_fifo_pfull_ast;
-}DPP_SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_hash0_ext_rsp_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 hash0_ext_rsp_fifo_pfull_neg;
-}DPP_SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_hash1_key_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 hash1_key_fifo_pfull_ast;
-}DPP_SE_ALG_HASH1_KEY_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_hash1_key_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 hash1_key_fifo_pfull_ast;
-}DPP_SE_ALG_HASH1_KEY_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_hash1_sreq_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 hash1_sreq_fifo_pfull_ast;
-}DPP_SE_ALG_HASH1_SREQ_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_hash1_sreq_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 hash1_sreq_fifo_pfull_neg;
-}DPP_SE_ALG_HASH1_SREQ_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_hash1_int_rsp_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 hash1_int_rsp_fifo_pfull_ast;
-}DPP_SE_ALG_HASH1_INT_RSP_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_hash1_int_rsp_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 hash1_int_rsp_fifo_pfull_neg;
-}DPP_SE_ALG_HASH1_INT_RSP_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_hash1_ext_rsp_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 hash1_ext_rsp_fifo_pfull_ast;
-}DPP_SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_hash1_ext_rsp_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 hash1_ext_rsp_fifo_pfull_neg;
-}DPP_SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_hash2_key_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 hash2_key_fifo_pfull_ast;
-}DPP_SE_ALG_HASH2_KEY_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_hash2_key_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 hash2_key_fifo_pfull_ast;
-}DPP_SE_ALG_HASH2_KEY_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_hash2_sreq_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 hash2_sreq_fifo_pfull_ast;
-}DPP_SE_ALG_HASH2_SREQ_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_hash2_sreq_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 hash2_sreq_fifo_pfull_neg;
-}DPP_SE_ALG_HASH2_SREQ_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_hash2_int_rsp_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 hash2_int_rsp_fifo_pfull_ast;
-}DPP_SE_ALG_HASH2_INT_RSP_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_hash2_int_rsp_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 hash2_int_rsp_fifo_pfull_neg;
-}DPP_SE_ALG_HASH2_INT_RSP_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_hash2_ext_rsp_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 hash2_ext_rsp_fifo_pfull_ast;
-}DPP_SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_hash2_ext_rsp_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 hash2_ext_rsp_fifo_pfull_neg;
-}DPP_SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_hash3_key_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 hash3_key_fifo_pfull_ast;
-}DPP_SE_ALG_HASH3_KEY_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_hash3_key_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 hash3_key_fifo_pfull_ast;
-}DPP_SE_ALG_HASH3_KEY_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_hash3_sreq_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 hash3_sreq_fifo_pfull_ast;
-}DPP_SE_ALG_HASH3_SREQ_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_hash3_sreq_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 hash3_sreq_fifo_pfull_neg;
-}DPP_SE_ALG_HASH3_SREQ_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_hash3_int_rsp_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 hash3_int_rsp_fifo_pfull_ast;
-}DPP_SE_ALG_HASH3_INT_RSP_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_hash3_int_rsp_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 hash3_int_rsp_fifo_pfull_neg;
-}DPP_SE_ALG_HASH3_INT_RSP_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_hash3_ext_rsp_fifo_pfull_ast_t
-{
-    ZXIC_UINT32 hash3_ext_rsp_fifo_pfull_ast;
-}DPP_SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_AST_T;
-
-typedef struct dpp_se_alg_hash3_ext_rsp_fifo_pfull_neg_t
-{
-    ZXIC_UINT32 hash3_ext_rsp_fifo_pfull_neg;
-}DPP_SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_lpm_as_info_t
-{
-    ZXIC_UINT32 lpm_as_type;
-    ZXIC_UINT32 lpm_as_en;
-}DPP_SE_ALG_LPM_AS_INFO_T;
-
-typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u0_pfull_neg_t
-{
-    ZXIC_UINT32 lpm_ext_rsp_fifo_u0_pfull_neg;
-}DPP_SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u2_pfull_ast_t
-{
-    ZXIC_UINT32 lpm_ext_rsp_fifo_u2_pfull_ast;
-}DPP_SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_AST_T;
-
-typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u2_pfull_neg_t
-{
-    ZXIC_UINT32 lpm_ext_rsp_fifo_u2_pfull_neg;
-}DPP_SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u3_pfull_ast_t
-{
-    ZXIC_UINT32 lpm_ext_rsp_fifo_u3_pfull_ast;
-}DPP_SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_AST_T;
-
-typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u3_pfull_neg_t
-{
-    ZXIC_UINT32 lpm_ext_rsp_fifo_u3_pfull_neg;
-}DPP_SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u4_pfull_ast_t
-{
-    ZXIC_UINT32 lpm_ext_rsp_fifo_u4_pfull_ast;
-}DPP_SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_AST_T;
-
-typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u4_pfull_neg_t
-{
-    ZXIC_UINT32 lpm_ext_rsp_fifo_u4_pfull_neg;
-}DPP_SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_lpm_as_rsp_fifo_u0_pfull_ast_t
-{
-    ZXIC_UINT32 lpm_as_rsp_fifo_u0_pfull_ast;
-}DPP_SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_AST_T;
-
-typedef struct dpp_se_alg_lpm_as_rsp_fifo_u0_pfull_neg_t
-{
-    ZXIC_UINT32 lpm_as_rsp_fifo_u0_pfull_neg;
-}DPP_SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_lpm_as_rsp_fifo_u1_pfull_ast_t
-{
-    ZXIC_UINT32 lpm_as_rsp_fifo_u1_pfull_ast;
-}DPP_SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_AST_T;
-
-typedef struct dpp_se_alg_lpm_as_rsp_fifo_u1_pfull_neg_t
-{
-    ZXIC_UINT32 lpm_as_rsp_fifo_u1_pfull_neg;
-}DPP_SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_NEG_T;
-
-typedef struct dpp_se_alg_lpm_v4_ddr3_base_addr_t
-{
-    ZXIC_UINT32 lpm_v4_ddr3_base_addr;
-}DPP_SE_ALG_LPM_V4_DDR3_BASE_ADDR_T;
-
-typedef struct dpp_se_alg_lpm_v6_ddr3_base_addr_t
-{
-    ZXIC_UINT32 lpm_v6_ddr3_base_addr;
-}DPP_SE_ALG_LPM_V6_DDR3_BASE_ADDR_T;
-
-typedef struct dpp_se_alg_debug_cnt_mode_t
-{
-    ZXIC_UINT32 cnt_rd_mode;
-    ZXIC_UINT32 cnt_overflow_mode;
-}DPP_SE_ALG_DEBUG_CNT_MODE_T;
-
-typedef struct dpp_se_alg_hash_p0_key_vld_cnt_t
-{
-    ZXIC_UINT32 hash_p0_key_vld_cnt;
-}DPP_SE_ALG_HASH_P0_KEY_VLD_CNT_T;
-
-typedef struct dpp_se_alg_hash_p1_key_vld_cnt_t
-{
-    ZXIC_UINT32 hash_p1_key_vld_cnt;
-}DPP_SE_ALG_HASH_P1_KEY_VLD_CNT_T;
-
-typedef struct dpp_se_alg_hash_p2_key_vld_cnt_t
-{
-    ZXIC_UINT32 hash_p2_key_vld_cnt;
-}DPP_SE_ALG_HASH_P2_KEY_VLD_CNT_T;
-
-typedef struct dpp_se_alg_hash_p3_key_vld_cnt_t
-{
-    ZXIC_UINT32 hash_p3_key_vld_cnt;
-}DPP_SE_ALG_HASH_P3_KEY_VLD_CNT_T;
-
-typedef struct dpp_se_alg_lpm_p0_key_vld_cnt_t
-{
-    ZXIC_UINT32 lpm_p0_key_vld_cnt;
-}DPP_SE_ALG_LPM_P0_KEY_VLD_CNT_T;
-
-typedef struct dpp_se_alg_hash_p0_rsp_vld_cnt_t
-{
-    ZXIC_UINT32 hash_p0_rsp_vld_cnt;
-}DPP_SE_ALG_HASH_P0_RSP_VLD_CNT_T;
-
-typedef struct dpp_se_alg_hash_p1_rsp_vld_cnt_t
-{
-    ZXIC_UINT32 hash_p1_rsp_vld_cnt;
-}DPP_SE_ALG_HASH_P1_RSP_VLD_CNT_T;
-
-typedef struct dpp_se_alg_hash_p2_rsp_vld_cnt_t
-{
-    ZXIC_UINT32 hash_p2_rsp_vld_cnt;
-}DPP_SE_ALG_HASH_P2_RSP_VLD_CNT_T;
-
-typedef struct dpp_se_alg_hash_p3_rsp_vld_cnt_t
-{
-    ZXIC_UINT32 hash_p3_rsp_vld_cnt;
-}DPP_SE_ALG_HASH_P3_RSP_VLD_CNT_T;
-
-typedef struct dpp_se_alg_lpm_p0_rsp_vld_cnt_t
-{
-    ZXIC_UINT32 lpm_p0_rsp_vld_cnt;
-}DPP_SE_ALG_LPM_P0_RSP_VLD_CNT_T;
-
-typedef struct dpp_se_alg_hash_p0_smf_cnt_t
-{
-    ZXIC_UINT32 hash_p0_smf_cnt;
-}DPP_SE_ALG_HASH_P0_SMF_CNT_T;
-
-typedef struct dpp_se_alg_hash_p1_smf_cnt_t
-{
-    ZXIC_UINT32 hash_p1_smf_cnt;
-}DPP_SE_ALG_HASH_P1_SMF_CNT_T;
-
-typedef struct dpp_se_alg_hash_p2_smf_cnt_t
-{
-    ZXIC_UINT32 hash_p2_smf_cnt;
-}DPP_SE_ALG_HASH_P2_SMF_CNT_T;
-
-typedef struct dpp_se_alg_hash_p3_smf_cnt_t
-{
-    ZXIC_UINT32 hash_p3_smf_cnt;
-}DPP_SE_ALG_HASH_P3_SMF_CNT_T;
-
-typedef struct dpp_se_alg_lpm_p0_smf_cnt_t
-{
-    ZXIC_UINT32 lpm_p0_smf_cnt;
-}DPP_SE_ALG_LPM_P0_SMF_CNT_T;
-
-typedef struct dpp_se_alg_hash_p0_spacevld_cnt_t
-{
-    ZXIC_UINT32 hash_p0_spacevld_cnt;
-}DPP_SE_ALG_HASH_P0_SPACEVLD_CNT_T;
-
-typedef struct dpp_se_alg_hash_p1_spacevld_cnt_t
-{
-    ZXIC_UINT32 hash_p1_spacevld_cnt;
-}DPP_SE_ALG_HASH_P1_SPACEVLD_CNT_T;
-
-typedef struct dpp_se_alg_hash_p2_spacevld_cnt_t
-{
-    ZXIC_UINT32 hash_p2_spacevld_cnt;
-}DPP_SE_ALG_HASH_P2_SPACEVLD_CNT_T;
-
-typedef struct dpp_se_alg_hash_p3_spacevld_cnt_t
-{
-    ZXIC_UINT32 hash_p3_spacevld_cnt;
-}DPP_SE_ALG_HASH_P3_SPACEVLD_CNT_T;
-
-typedef struct dpp_se_alg_smmu1_p0_req_vld_cnt_t
-{
-    ZXIC_UINT32 smmu1_p0_req_vld_cnt;
-}DPP_SE_ALG_SMMU1_P0_REQ_VLD_CNT_T;
-
-typedef struct dpp_se_alg_smmu1_p1_req_vld_cnt_t
-{
-    ZXIC_UINT32 smmu1_p1_req_vld_cnt;
-}DPP_SE_ALG_SMMU1_P1_REQ_VLD_CNT_T;
-
-typedef struct dpp_se_alg_smmu1_p2_req_vld_cnt_t
-{
-    ZXIC_UINT32 smmu1_p2_req_vld_cnt;
-}DPP_SE_ALG_SMMU1_P2_REQ_VLD_CNT_T;
-
-typedef struct dpp_se_alg_smmu1_p3_req_vld_cnt_t
-{
-    ZXIC_UINT32 smmu1_p3_req_vld_cnt;
-}DPP_SE_ALG_SMMU1_P3_REQ_VLD_CNT_T;
-
-typedef struct dpp_se_alg_smmu1_p4_req_vld_cnt_t
-{
-    ZXIC_UINT32 smmu1_p4_req_vld_cnt;
-}DPP_SE_ALG_SMMU1_P4_REQ_VLD_CNT_T;
-
-typedef struct dpp_se_alg_smmu1_p5_req_vld_cnt_t
-{
-    ZXIC_UINT32 smmu1_p5_req_vld_cnt;
-}DPP_SE_ALG_SMMU1_P5_REQ_VLD_CNT_T;
-
-typedef struct dpp_se_alg_smmu1_p0_rsp_vld_cnt_t
-{
-    ZXIC_UINT32 smmu1_p0_rsp_vld_cnt;
-}DPP_SE_ALG_SMMU1_P0_RSP_VLD_CNT_T;
-
-typedef struct dpp_se_alg_smmu1_p1_rsp_vld_cnt_t
-{
-    ZXIC_UINT32 smmu1_p1_rsp_vld_cnt;
-}DPP_SE_ALG_SMMU1_P1_RSP_VLD_CNT_T;
-
-typedef struct dpp_se_alg_smmu1_p2_rsp_vld_cnt_t
-{
-    ZXIC_UINT32 smmu1_p2_rsp_vld_cnt;
-}DPP_SE_ALG_SMMU1_P2_RSP_VLD_CNT_T;
-
-typedef struct dpp_se_alg_smmu1_p3_rsp_vld_cnt_t
-{
-    ZXIC_UINT32 smmu1_p3_rsp_vld_cnt;
-}DPP_SE_ALG_SMMU1_P3_RSP_VLD_CNT_T;
-
-typedef struct dpp_se_alg_smmu1_p4_rsp_vld_cnt_t
-{
-    ZXIC_UINT32 smmu1_p4_rsp_vld_cnt;
-}DPP_SE_ALG_SMMU1_P4_RSP_VLD_CNT_T;
-
-typedef struct dpp_se_alg_smmu1_p5_rsp_vld_cnt_t
-{
-    ZXIC_UINT32 smmu1_p5_rsp_vld_cnt;
-}DPP_SE_ALG_SMMU1_P5_RSP_VLD_CNT_T;
-
-typedef struct dpp_se_alg_schd_learn_fifo_int_cnt_t
-{
-    ZXIC_UINT32 schd_learn_fifo_int_cnt;
-}DPP_SE_ALG_SCHD_LEARN_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_schd_hash0_fifo_int_cnt_t
-{
-    ZXIC_UINT32 schd_hash0_fifo_int_cnt;
-}DPP_SE_ALG_SCHD_HASH0_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_schd_hash1_fifo_int_cnt_t
-{
-    ZXIC_UINT32 schd_hash1_fifo_int_cnt;
-}DPP_SE_ALG_SCHD_HASH1_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_schd_hash2_fifo_int_cnt_t
-{
-    ZXIC_UINT32 schd_hash2_fifo_int_cnt;
-}DPP_SE_ALG_SCHD_HASH2_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_schd_hash3_fifo_int_cnt_t
-{
-    ZXIC_UINT32 schd_hash3_fifo_int_cnt;
-}DPP_SE_ALG_SCHD_HASH3_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_schd_lpm_fifo_int_cnt_t
-{
-    ZXIC_UINT32 schd_lpm_fifo_int_cnt;
-}DPP_SE_ALG_SCHD_LPM_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_schd_learn_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 schd_learn_fifo_parity_err_cnt;
-}DPP_SE_ALG_SCHD_LEARN_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_schd_hash0_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 schd_hash0_fifo_parity_err_cnt;
-}DPP_SE_ALG_SCHD_HASH0_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_schd_hash1_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 schd_hash1_fifo_parity_err_cnt;
-}DPP_SE_ALG_SCHD_HASH1_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_schd_hash2_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 schd_hash2_fifo_parity_err_cnt;
-}DPP_SE_ALG_SCHD_HASH2_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_schd_hash3_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 schd_hash3_fifo_parity_err_cnt;
-}DPP_SE_ALG_SCHD_HASH3_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_schd_lpm_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 schd_lpm_fifo_parity_err_cnt;
-}DPP_SE_ALG_SCHD_LPM_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_rd_init_cft_cnt_t
-{
-    ZXIC_UINT32 rd_init_cft_cnt;
-}DPP_SE_ALG_RD_INIT_CFT_CNT_T;
-
-typedef struct dpp_se_alg_zgp0_zblk0_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp0_zblk0_ecc_err_cnt;
-}DPP_SE_ALG_ZGP0_ZBLK0_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp0_zblk1_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp0_zblk1_ecc_err_cnt;
-}DPP_SE_ALG_ZGP0_ZBLK1_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp0_zblk2_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp0_zblk2_ecc_err_cnt;
-}DPP_SE_ALG_ZGP0_ZBLK2_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp0_zblk3_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp0_zblk3_ecc_err_cnt;
-}DPP_SE_ALG_ZGP0_ZBLK3_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp0_zblk4_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp0_zblk4_ecc_err_cnt;
-}DPP_SE_ALG_ZGP0_ZBLK4_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp0_zblk5_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp0_zblk5_ecc_err_cnt;
-}DPP_SE_ALG_ZGP0_ZBLK5_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp0_zblk6_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp0_zblk6_ecc_err_cnt;
-}DPP_SE_ALG_ZGP0_ZBLK6_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp0_zblk7_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp0_zblk7_ecc_err_cnt;
-}DPP_SE_ALG_ZGP0_ZBLK7_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp1_zblk0_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp1_zblk0_ecc_err_cnt;
-}DPP_SE_ALG_ZGP1_ZBLK0_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp1_zblk1_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp1_zblk1_ecc_err_cnt;
-}DPP_SE_ALG_ZGP1_ZBLK1_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp1_zblk2_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp1_zblk2_ecc_err_cnt;
-}DPP_SE_ALG_ZGP1_ZBLK2_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp1_zblk3_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp1_zblk3_ecc_err_cnt;
-}DPP_SE_ALG_ZGP1_ZBLK3_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp1_zblk4_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp1_zblk4_ecc_err_cnt;
-}DPP_SE_ALG_ZGP1_ZBLK4_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp1_zblk5_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp1_zblk5_ecc_err_cnt;
-}DPP_SE_ALG_ZGP1_ZBLK5_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp1_zblk6_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp1_zblk6_ecc_err_cnt;
-}DPP_SE_ALG_ZGP1_ZBLK6_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp1_zblk7_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp1_zblk7_ecc_err_cnt;
-}DPP_SE_ALG_ZGP1_ZBLK7_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp2_zblk0_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp2_zblk0_ecc_err_cnt;
-}DPP_SE_ALG_ZGP2_ZBLK0_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp2_zblk1_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp2_zblk1_ecc_err_cnt;
-}DPP_SE_ALG_ZGP2_ZBLK1_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp2_zblk2_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp2_zblk2_ecc_err_cnt;
-}DPP_SE_ALG_ZGP2_ZBLK2_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp2_zblk3_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp2_zblk3_ecc_err_cnt;
-}DPP_SE_ALG_ZGP2_ZBLK3_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp2_zblk4_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp2_zblk4_ecc_err_cnt;
-}DPP_SE_ALG_ZGP2_ZBLK4_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp2_zblk5_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp2_zblk5_ecc_err_cnt;
-}DPP_SE_ALG_ZGP2_ZBLK5_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp2_zblk6_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp2_zblk6_ecc_err_cnt;
-}DPP_SE_ALG_ZGP2_ZBLK6_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp2_zblk7_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp2_zblk7_ecc_err_cnt;
-}DPP_SE_ALG_ZGP2_ZBLK7_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp3_zblk0_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp3_zblk0_ecc_err_cnt;
-}DPP_SE_ALG_ZGP3_ZBLK0_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp3_zblk1_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp3_zblk1_ecc_err_cnt;
-}DPP_SE_ALG_ZGP3_ZBLK1_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp3_zblk2_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp3_zblk2_ecc_err_cnt;
-}DPP_SE_ALG_ZGP3_ZBLK2_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp3_zblk3_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp3_zblk3_ecc_err_cnt;
-}DPP_SE_ALG_ZGP3_ZBLK3_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp3_zblk4_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp3_zblk4_ecc_err_cnt;
-}DPP_SE_ALG_ZGP3_ZBLK4_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp3_zblk5_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp3_zblk5_ecc_err_cnt;
-}DPP_SE_ALG_ZGP3_ZBLK5_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp3_zblk6_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp3_zblk6_ecc_err_cnt;
-}DPP_SE_ALG_ZGP3_ZBLK6_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zgp3_zblk7_ecc_err_cnt_t
-{
-    ZXIC_UINT32 zgp3_zblk7_ecc_err_cnt;
-}DPP_SE_ALG_ZGP3_ZBLK7_ECC_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zcam_hash_p0_err_cnt_t
-{
-    ZXIC_UINT32 zcam_hash_p0_err_cnt;
-}DPP_SE_ALG_ZCAM_HASH_P0_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zcam_hash_p1_err_cnt_t
-{
-    ZXIC_UINT32 zcam_hash_p1_err_cnt;
-}DPP_SE_ALG_ZCAM_HASH_P1_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zcam_hash_p2_err_cnt_t
-{
-    ZXIC_UINT32 zcam_hash_p2_err_cnt;
-}DPP_SE_ALG_ZCAM_HASH_P2_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zcam_hash_p3_err_cnt_t
-{
-    ZXIC_UINT32 zcam_hash_p3_err_cnt;
-}DPP_SE_ALG_ZCAM_HASH_P3_ERR_CNT_T;
-
-typedef struct dpp_se_alg_zcam_lpm_err_cnt_t
-{
-    ZXIC_UINT32 zcam_lpm_err_cnt;
-}DPP_SE_ALG_ZCAM_LPM_ERR_CNT_T;
-
-typedef struct dpp_se_alg_hash0_sreq_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 hash0_sreq_fifo_parity_err_cnt;
-}DPP_SE_ALG_HASH0_SREQ_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_hash0_sreq_fifo_int_cnt_t
-{
-    ZXIC_UINT32 hash0_sreq_fifo_int_cnt;
-}DPP_SE_ALG_HASH0_SREQ_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_hash0_key_fifo_int_cnt_t
-{
-    ZXIC_UINT32 hash0_key_fifo_int_cnt;
-}DPP_SE_ALG_HASH0_KEY_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_hash0_int_rsp_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 hash0_int_rsp_fifo_parity_err_cnt;
-}DPP_SE_ALG_HASH0_INT_RSP_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_hash0_ext_rsp_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 hash0_ext_rsp_fifo_parity_err_cnt;
-}DPP_SE_ALG_HASH0_EXT_RSP_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_hash0_ext_rsp_fifo_int_cnt_t
-{
-    ZXIC_UINT32 hash0_ext_rsp_fifo_int_cnt;
-}DPP_SE_ALG_HASH0_EXT_RSP_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_hash0_int_rsp_fifo_int_cnt_t
-{
-    ZXIC_UINT32 hash0_int_rsp_fifo_int_cnt;
-}DPP_SE_ALG_HASH0_INT_RSP_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_hash1_sreq_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 hash1_sreq_fifo_parity_err_cnt;
-}DPP_SE_ALG_HASH1_SREQ_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_hash1_sreq_fifo_int_cnt_t
-{
-    ZXIC_UINT32 hash1_sreq_fifo_int_cnt;
-}DPP_SE_ALG_HASH1_SREQ_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_hash1_key_fifo_int_cnt_t
-{
-    ZXIC_UINT32 hash1_key_fifo_int_cnt;
-}DPP_SE_ALG_HASH1_KEY_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_hash1_int_rsp_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 hash1_int_rsp_fifo_parity_err_cnt;
-}DPP_SE_ALG_HASH1_INT_RSP_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_hash1_ext_rsp_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 hash1_ext_rsp_fifo_parity_err_cnt;
-}DPP_SE_ALG_HASH1_EXT_RSP_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_hash1_ext_rsp_fifo_int_cnt_t
-{
-    ZXIC_UINT32 hash1_ext_rsp_fifo_int_cnt;
-}DPP_SE_ALG_HASH1_EXT_RSP_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_hash1_int_rsp_fifo_int_cnt_t
-{
-    ZXIC_UINT32 hash1_int_rsp_fifo_int_cnt;
-}DPP_SE_ALG_HASH1_INT_RSP_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_hash2_sreq_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 hash2_sreq_fifo_parity_err_cnt;
-}DPP_SE_ALG_HASH2_SREQ_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_hash2_sreq_fifo_int_cnt_t
-{
-    ZXIC_UINT32 hash2_sreq_fifo_int_cnt;
-}DPP_SE_ALG_HASH2_SREQ_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_hash2_key_fifo_int_cnt_t
-{
-    ZXIC_UINT32 hash2_key_fifo_int_cnt;
-}DPP_SE_ALG_HASH2_KEY_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_hash2_int_rsp_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 hash2_int_rsp_fifo_parity_err_cnt;
-}DPP_SE_ALG_HASH2_INT_RSP_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_hash2_ext_rsp_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 hash2_ext_rsp_fifo_parity_err_cnt;
-}DPP_SE_ALG_HASH2_EXT_RSP_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_hash2_ext_rsp_fifo_int_cnt_t
-{
-    ZXIC_UINT32 hash2_ext_rsp_fifo_int_cnt;
-}DPP_SE_ALG_HASH2_EXT_RSP_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_hash2_int_rsp_fifo_int_cnt_t
-{
-    ZXIC_UINT32 hash2_int_rsp_fifo_int_cnt;
-}DPP_SE_ALG_HASH2_INT_RSP_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_hash3_sreq_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 hash3_sreq_fifo_parity_err_cnt;
-}DPP_SE_ALG_HASH3_SREQ_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_hash3_sreq_fifo_int_cnt_t
-{
-    ZXIC_UINT32 hash3_sreq_fifo_int_cnt;
-}DPP_SE_ALG_HASH3_SREQ_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_hash3_key_fifo_int_cnt_t
-{
-    ZXIC_UINT32 hash3_key_fifo_int_cnt;
-}DPP_SE_ALG_HASH3_KEY_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_hash3_int_rsp_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 hash3_int_rsp_fifo_parity_err_cnt;
-}DPP_SE_ALG_HASH3_INT_RSP_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_hash3_ext_rsp_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 hash3_ext_rsp_fifo_parity_err_cnt;
-}DPP_SE_ALG_HASH3_EXT_RSP_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_hash3_ext_rsp_fifo_int_cnt_t
-{
-    ZXIC_UINT32 hash3_ext_rsp_fifo_int_cnt;
-}DPP_SE_ALG_HASH3_EXT_RSP_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_hash3_int_rsp_fifo_int_cnt_t
-{
-    ZXIC_UINT32 hash3_int_rsp_fifo_int_cnt;
-}DPP_SE_ALG_HASH3_INT_RSP_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_lpm_ext_rsp_fifo_int_cnt_t
-{
-    ZXIC_UINT32 lpm_ext_rsp_fifo_int_cnt;
-}DPP_SE_ALG_LPM_EXT_RSP_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_lpm_ext_v6_fifo_int_cnt_t
-{
-    ZXIC_UINT32 lpm_ext_v6_fifo_int_cnt;
-}DPP_SE_ALG_LPM_EXT_V6_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_lpm_ext_v4_fifo_int_cnt_t
-{
-    ZXIC_UINT32 lpm_ext_v4_fifo_int_cnt;
-}DPP_SE_ALG_LPM_EXT_V4_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_lpm_ext_addr_fifo_int_cnt_t
-{
-    ZXIC_UINT32 lpm_ext_addr_fifo_int_cnt;
-}DPP_SE_ALG_LPM_EXT_ADDR_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_lpm_ext_v4_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 lpm_ext_v4_fifo_parity_err_cnt;
-}DPP_SE_ALG_LPM_EXT_V4_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_lpm_ext_v6_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 lpm_ext_v6_fifo_parity_err_cnt;
-}DPP_SE_ALG_LPM_EXT_V6_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_lpm_ext_rsp_fifo_parity_err_cnt_t
-{
-    ZXIC_UINT32 lpm_ext_rsp_fifo_parity_err_cnt;
-}DPP_SE_ALG_LPM_EXT_RSP_FIFO_PARITY_ERR_CNT_T;
-
-typedef struct dpp_se_alg_lpm_as_req_fifo_int_cnt_t
-{
-    ZXIC_UINT32 lpm_as_req_fifo_int_cnt;
-}DPP_SE_ALG_LPM_AS_REQ_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_lpm_as_int_rsp_fifo_int_cnt_t
-{
-    ZXIC_UINT32 lpm_as_int_rsp_fifo_int_cnt;
-}DPP_SE_ALG_LPM_AS_INT_RSP_FIFO_INT_CNT_T;
-
-typedef struct dpp_se_alg_se_alg_int_status_t
-{
-    ZXIC_UINT32 schd_int_unmask_flag;
-    ZXIC_UINT32 zblk_ecc_int_unmask_flag;
-    ZXIC_UINT32 hash0_int_unmask_flag;
-    ZXIC_UINT32 hash1_int_unmask_flag;
-    ZXIC_UINT32 hash2_int_unmask_flag;
-    ZXIC_UINT32 hash3_int_unmask_flag;
-    ZXIC_UINT32 lpm_int_unmask_flag;
-}DPP_SE_ALG_SE_ALG_INT_STATUS_T;
-
-typedef struct dpp_se_alg_schd_int_en_t
-{
-    ZXIC_UINT32 wr_rsp_fifo_ovfl;
-    ZXIC_UINT32 init_rd_cft_en;
-    ZXIC_UINT32 schd_lpm_fifo_parity_errl;
-    ZXIC_UINT32 schd_hash3_fifo_parity_err;
-    ZXIC_UINT32 schd_hash2_fifo_parity_err;
-    ZXIC_UINT32 schd_hash1_fifo_parity_err;
-    ZXIC_UINT32 schd_hash0_fifo_parity_err;
-    ZXIC_UINT32 schd_learn_fifo_parity_err;
-    ZXIC_UINT32 schd_lpm_fifo_ovfl;
-    ZXIC_UINT32 schd_hash3_fifo_ovfl;
-    ZXIC_UINT32 schd_hash2_fifo_unfl;
-    ZXIC_UINT32 schd_hash1_fifo_ovfl;
-    ZXIC_UINT32 schd_hash0_fifo_ovfl;
-    ZXIC_UINT32 schd_learn_fifo_ovfl;
-}DPP_SE_ALG_SCHD_INT_EN_T;
-
-typedef struct dpp_se_alg_schd_int_mask_t
-{
-    ZXIC_UINT32 schd_int_mask;
-}DPP_SE_ALG_SCHD_INT_MASK_T;
-
-typedef struct dpp_se_alg_schd_int_status_t
-{
-    ZXIC_UINT32 schd_int_status;
-}DPP_SE_ALG_SCHD_INT_STATUS_T;
-
-typedef struct dpp_se_alg_zblk_ecc_int_en_t
-{
-    ZXIC_UINT32 zblk_ecc_int_en;
-}DPP_SE_ALG_ZBLK_ECC_INT_EN_T;
-
-typedef struct dpp_se_alg_zblk_ecc_int_mask_t
-{
-    ZXIC_UINT32 zblk_ecc_int_mask;
-}DPP_SE_ALG_ZBLK_ECC_INT_MASK_T;
-
-typedef struct dpp_se_alg_zblk_ecc_int_status_t
-{
-    ZXIC_UINT32 zblk_ecc_int_status;
-}DPP_SE_ALG_ZBLK_ECC_INT_STATUS_T;
-
-typedef struct dpp_se_alg_hash0_int_en_t
-{
-    ZXIC_UINT32 zcam_hash_p0_err_en;
-    ZXIC_UINT32 hash0_agree_int_fifo_ovf_en;
-    ZXIC_UINT32 hash0_agree_ext_fifo_ovf_en;
-    ZXIC_UINT32 hash0_agree_ext_fifo_parity_err_en;
-    ZXIC_UINT32 hash0_agree_int_fifo_parity_err_en;
-    ZXIC_UINT32 hash0_key_fifo_ovfl_en;
-    ZXIC_UINT32 hash0_sreq_fifo_ovfl_en;
-    ZXIC_UINT32 hash0_key_fifo_parity_err_en;
-}DPP_SE_ALG_HASH0_INT_EN_T;
-
-typedef struct dpp_se_alg_hash0_int_mask_t
-{
-    ZXIC_UINT32 hash0_int_mask;
-}DPP_SE_ALG_HASH0_INT_MASK_T;
-
-typedef struct dpp_se_alg_hash0_int_status_t
-{
-    ZXIC_UINT32 hash0_int_status;
-}DPP_SE_ALG_HASH0_INT_STATUS_T;
-
-typedef struct dpp_se_alg_hash1_int_en_t
-{
-    ZXIC_UINT32 zcam_hash_p1_err_en;
-    ZXIC_UINT32 hash1_agree_int_fifo_ovf_en;
-    ZXIC_UINT32 hash1_agree_ext_fifo_ovf_en;
-    ZXIC_UINT32 hash1_agree_ext_fifo_parity_err_en;
-    ZXIC_UINT32 hash1_agree_int_fifo_parity_err_en;
-    ZXIC_UINT32 hash1_key_fifo_ovfl_en;
-    ZXIC_UINT32 hash1_sreq_fifo_ovfl_en;
-    ZXIC_UINT32 hash1_key_fifo_parity_err_en;
-}DPP_SE_ALG_HASH1_INT_EN_T;
-
-typedef struct dpp_se_alg_hash1_int_mask_t
-{
-    ZXIC_UINT32 hash1_int_mask;
-}DPP_SE_ALG_HASH1_INT_MASK_T;
-
-typedef struct dpp_se_alg_hash1_int_status_t
-{
-    ZXIC_UINT32 hash1_int_status;
-}DPP_SE_ALG_HASH1_INT_STATUS_T;
-
-typedef struct dpp_se_alg_hash2_int_en_t
-{
-    ZXIC_UINT32 zcam_hash_p2_err_en;
-    ZXIC_UINT32 hash2_agree_int_fifo_ovf_en;
-    ZXIC_UINT32 hash2_agree_ext_fifo_ovf_en;
-    ZXIC_UINT32 hash2_agree_ext_fifo_parity_err_en;
-    ZXIC_UINT32 hash2_agree_int_fifo_parity_err_en;
-    ZXIC_UINT32 hash2_key_fifo_ovfl_en;
-    ZXIC_UINT32 hash2_sreq_fifo_ovfl_en;
-    ZXIC_UINT32 hash2_key_fifo_parity_err_en;
-}DPP_SE_ALG_HASH2_INT_EN_T;
-
-typedef struct dpp_se_alg_hash2_int_mask_t
-{
-    ZXIC_UINT32 hash2_int_mask;
-}DPP_SE_ALG_HASH2_INT_MASK_T;
-
-typedef struct dpp_se_alg_hash2_int_status_t
-{
-    ZXIC_UINT32 hash2_int_status;
-}DPP_SE_ALG_HASH2_INT_STATUS_T;
-
-typedef struct dpp_se_alg_hash3_int_en_t
-{
-    ZXIC_UINT32 zcam_hash_p3_err_en;
-    ZXIC_UINT32 hash3_agree_int_fifo_ovf_en;
-    ZXIC_UINT32 hash3_agree_ext_fifo_ovf_en;
-    ZXIC_UINT32 hash3_agree_ext_fifo_parity_err_en;
-    ZXIC_UINT32 hash3_agree_int_fifo_parity_err_en;
-    ZXIC_UINT32 hash3_key_fifo_ovfl_en;
-    ZXIC_UINT32 hash3_sreq_fifo_ovfl_en;
-    ZXIC_UINT32 hash3_key_fifo_parity_err_en;
-}DPP_SE_ALG_HASH3_INT_EN_T;
-
-typedef struct dpp_se_alg_hash3_int_mask_t
-{
-    ZXIC_UINT32 hash3_int_mask;
-}DPP_SE_ALG_HASH3_INT_MASK_T;
-
-typedef struct dpp_se_alg_hash3_int_status_t
-{
-    ZXIC_UINT32 hash3_int_status;
-}DPP_SE_ALG_HASH3_INT_STATUS_T;
-
-typedef struct dpp_se_alg_lpm_int_en_t
-{
-    ZXIC_UINT32 zcam_lpm_err_en;
-    ZXIC_UINT32 lpm_as_int_rsp_fifo_ovfl_en;
-    ZXIC_UINT32 lpm_as_req_fifo_ovfl_en;
-    ZXIC_UINT32 lpm_ext_ddr_rsp_fifo_parity_en;
-    ZXIC_UINT32 lpm_ext_v6_key_parity_en;
-    ZXIC_UINT32 lpm_ext_v4_key_parity_en;
-    ZXIC_UINT32 lpm_ext_addr_fifo_ovfl_en;
-    ZXIC_UINT32 lpm_ext_v4_fifo_ovfl_en;
-    ZXIC_UINT32 lpm_ext_v6_fifo_ovfl_en;
-    ZXIC_UINT32 lpm_ext_ddr_rsp_ovf_en;
-}DPP_SE_ALG_LPM_INT_EN_T;
-
-typedef struct dpp_se_alg_lpm_int_mask_t
-{
-    ZXIC_UINT32 lpm_int_mask;
-}DPP_SE_ALG_LPM_INT_MASK_T;
-
-typedef struct dpp_se_alg_lpm_int_status_t
-{
-    ZXIC_UINT32 lpm_int_status;
-}DPP_SE_ALG_LPM_INT_STATUS_T;
-
-typedef struct dpp_se_alg_zblock_lpm_mask0_t
-{
-    ZXIC_UINT32 vpn_id_mask;
-    ZXIC_UINT32 prefix0_mask;
-    ZXIC_UINT32 prefix1_mask;
-    ZXIC_UINT32 prefix2_mask;
-    ZXIC_UINT32 prefix3_mask;
-}DPP_SE_ALG_ZBLOCK_LPM_MASK0_T;
-
-typedef struct dpp_se_alg_zblock_lpm_mask1_t
-{
-    ZXIC_UINT32 vpn_id_mask;
-    ZXIC_UINT32 prefix0_mask;
-    ZXIC_UINT32 prefix1_mask;
-    ZXIC_UINT32 prefix2_mask;
-    ZXIC_UINT32 prefix3_mask;
-}DPP_SE_ALG_ZBLOCK_LPM_MASK1_T;
-
-typedef struct dpp_se_alg_zblock_lpm_mask2_t
-{
-    ZXIC_UINT32 vpn_id_mask;
-    ZXIC_UINT32 prefix0_mask;
-    ZXIC_UINT32 prefix1_mask;
-    ZXIC_UINT32 prefix2_mask;
-    ZXIC_UINT32 prefix3_mask;
-}DPP_SE_ALG_ZBLOCK_LPM_MASK2_T;
-
-typedef struct dpp_se_alg_zblock_lpm_mask3_t
-{
-    ZXIC_UINT32 vpn_id_mask;
-    ZXIC_UINT32 prefix0_mask;
-    ZXIC_UINT32 prefix1_mask;
-    ZXIC_UINT32 prefix2_mask;
-    ZXIC_UINT32 prefix3_mask;
-}DPP_SE_ALG_ZBLOCK_LPM_MASK3_T;
-
-typedef struct dpp_se_alg_zblock_default_route0_t
-{
-    ZXIC_UINT32 vpn_id;
-    ZXIC_UINT32 vpn_dresult;
-    ZXIC_UINT32 vpn_flag;
-    ZXIC_UINT32 vpn_vld;
-}DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE0_T;
-
-typedef struct dpp_se_alg_zblock_default_route1_t
-{
-    ZXIC_UINT32 vpn_id;
-    ZXIC_UINT32 vpn_dresult;
-    ZXIC_UINT32 vpn_flag;
-    ZXIC_UINT32 vpn_vld;
-}DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE1_T;
-
-typedef struct dpp_se_alg_zblock_default_route2_t
-{
-    ZXIC_UINT32 vpn_id;
-    ZXIC_UINT32 vpn_dresult;
-    ZXIC_UINT32 vpn_flag;
-    ZXIC_UINT32 vpn_vld;
-}DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE2_T;
-
-typedef struct dpp_se_alg_zblock_default_route3_t
-{
-    ZXIC_UINT32 vpn_id;
-    ZXIC_UINT32 vpn_dresult;
-    ZXIC_UINT32 vpn_flag;
-    ZXIC_UINT32 vpn_vld;
-}DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE3_T;
-
-typedef struct dpp_se_alg_zblock_default_route4_t
-{
-    ZXIC_UINT32 vpn_id;
-    ZXIC_UINT32 vpn_dresult;
-    ZXIC_UINT32 vpn_flag;
-    ZXIC_UINT32 vpn_vld;
-}DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE4_T;
-
-typedef struct dpp_se_alg_zblock_default_route5_t
-{
-    ZXIC_UINT32 vpn_id;
-    ZXIC_UINT32 vpn_dresult;
-    ZXIC_UINT32 vpn_flag;
-    ZXIC_UINT32 vpn_vld;
-}DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE5_T;
-
-typedef struct dpp_se_alg_zblock_default_route6_t
-{
-    ZXIC_UINT32 vpn_id;
-    ZXIC_UINT32 vpn_dresult;
-    ZXIC_UINT32 vpn_flag;
-    ZXIC_UINT32 vpn_vld;
-}DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE6_T;
-
-typedef struct dpp_se_alg_zblock_default_route7_t
-{
-    ZXIC_UINT32 vpn_id;
-    ZXIC_UINT32 vpn_dresult;
-    ZXIC_UINT32 vpn_flag;
-    ZXIC_UINT32 vpn_vld;
-}DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE7_T;
-
-typedef struct dpp_se_alg_zblock_hash_listtable_item0_t
-{
-    ZXIC_UINT32 hash_item;
-}DPP_SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM0_T;
-
-typedef struct dpp_se_alg_zblock_hash_listtable_item1_t
-{
-    ZXIC_UINT32 hash_item;
-}DPP_SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM1_T;
-
-typedef struct dpp_se_alg_zblock_hash_listtable_item2_t
-{
-    ZXIC_UINT32 hash_item;
-}DPP_SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM2_T;
-
-typedef struct dpp_se_alg_zblock_hash_listtable_item3_t
-{
-    ZXIC_UINT32 hash_item;
-}DPP_SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM3_T;
-
-typedef struct dpp_se_alg_zblock_ecc_err_status_t
-{
-    ZXIC_UINT32 sram3_ecc_err;
-    ZXIC_UINT32 sram2_ecc_err;
-    ZXIC_UINT32 sram1_ecc_err;
-    ZXIC_UINT32 sram0_ecc_err;
-}DPP_SE_ALG_ZBLOCK_ECC_ERR_STATUS_T;
-
-typedef struct dpp_se_alg_zblock_lpm_v6_sram_cmp_t
-{
-    ZXIC_UINT32 sram_cmp_flag;
-}DPP_SE_ALG_ZBLOCK_LPM_V6_SRAM_CMP_T;
-
-typedef struct dpp_se_alg_zblock_lpm_v4_sram_cmp_t
-{
-    ZXIC_UINT32 sram_cmp_flag;
-}DPP_SE_ALG_ZBLOCK_LPM_V4_SRAM_CMP_T;
-
-typedef struct dpp_se_parser_kschd_pful_cfg_t
-{
-    ZXIC_UINT32 kschd_pful_assert;
-    ZXIC_UINT32 kschd_pful_negate;
-}DPP_SE_PARSER_KSCHD_PFUL_CFG_T;
-
-typedef struct dpp_se_parser_debug_cnt_mode_t
-{
-    ZXIC_UINT32 cnt_rd_mode;
-    ZXIC_UINT32 cnt_overflow_mode;
-}DPP_SE_PARSER_DEBUG_CNT_MODE_T;
-
-typedef struct dpp_se_parser_parser_int_en_t
-{
-    ZXIC_UINT32 parser_int_en;
-}DPP_SE_PARSER_PARSER_INT_EN_T;
-
-typedef struct dpp_se_parser_parser_int_mask_t
-{
-    ZXIC_UINT32 parser_int_mask;
-}DPP_SE_PARSER_PARSER_INT_MASK_T;
-
-typedef struct dpp_se_parser_parser_int_status_t
-{
-    ZXIC_UINT32 parser_int_status;
-}DPP_SE_PARSER_PARSER_INT_STATUS_T;
-
-typedef struct dpp_se_parser_parser_int_unmask_flag_t
-{
-    ZXIC_UINT32 parser_int_unmask_flag;
-}DPP_SE_PARSER_PARSER_INT_UNMASK_FLAG_T;
-
-typedef struct dpp_se_parser_ecc_bypass_read_t
-{
-    ZXIC_UINT32 ecc_bypass_read;
-}DPP_SE_PARSER_ECC_BYPASS_READ_T;
-
-typedef struct dpp_se_parser_mex0_5_req_cnt_t
-{
-    ZXIC_UINT32 mex0_5_req_cnt;
-}DPP_SE_PARSER_MEX0_5_REQ_CNT_T;
-
-typedef struct dpp_se_parser_kschd_req0_5_cnt_t
-{
-    ZXIC_UINT32 kschd_req0_5_cnt;
-}DPP_SE_PARSER_KSCHD_REQ0_5_CNT_T;
-
-typedef struct dpp_se_parser_kschd_parser_fc0_5_cnt_t
-{
-    ZXIC_UINT32 kschd_parser_fc0_5_cnt;
-}DPP_SE_PARSER_KSCHD_PARSER_FC0_5_CNT_T;
-
-typedef struct dpp_se_parser_se_ppu_mex0_5_fc_cnt_t
-{
-    ZXIC_UINT32 se_ppu_mex0_5_fc_cnt;
-}DPP_SE_PARSER_SE_PPU_MEX0_5_FC_CNT_T;
-
-typedef struct dpp_se_parser_smmu0_marc_fc_cnt_t
-{
-    ZXIC_UINT32 smmu0_marc_fc_cnt;
-}DPP_SE_PARSER_SMMU0_MARC_FC_CNT_T;
-
-typedef struct dpp_se_parser_smmu0_marc_key_cnt_t
-{
-    ZXIC_UINT32 smmu0_marc_key_cnt;
-}DPP_SE_PARSER_SMMU0_MARC_KEY_CNT_T;
-
-typedef struct dpp_se_parser_cmmu_key_cnt_t
-{
-    ZXIC_UINT32 cmmu_key_cnt;
-}DPP_SE_PARSER_CMMU_KEY_CNT_T;
-
-typedef struct dpp_se_parser_cmmu_parser_fc_cnt_t
-{
-    ZXIC_UINT32 cmmu_parser_fc_cnt;
-}DPP_SE_PARSER_CMMU_PARSER_FC_CNT_T;
-
-typedef struct dpp_se_parser_marc_tab_type_err_mex0_5_cnt_t
-{
-    ZXIC_UINT32 marc_tab_type_err_mex0_5_cnt;
-}DPP_SE_PARSER_MARC_TAB_TYPE_ERR_MEX0_5_CNT_T;
-
-typedef struct dpp_se_parser_eram_fulladdr_drop_cnt_t
-{
-    ZXIC_UINT32 eram_fulladdr_drop_cnt;
-}DPP_SE_PARSER_ERAM_FULLADDR_DROP_CNT_T;
-
-typedef struct dpp_se_as_hash0_pful_cfg_t
-{
-    ZXIC_UINT32 hash0_pful_cfg;
-}DPP_SE_AS_HASH0_PFUL_CFG_T;
-
-typedef struct dpp_se_as_hash1_pful_cfg_t
-{
-    ZXIC_UINT32 hash1_pful_cfg;
-}DPP_SE_AS_HASH1_PFUL_CFG_T;
-
-typedef struct dpp_se_as_hash2_pful_cfg_t
-{
-    ZXIC_UINT32 hash2_pful_cfg;
-}DPP_SE_AS_HASH2_PFUL_CFG_T;
-
-typedef struct dpp_se_as_hash3_pful_cfg_t
-{
-    ZXIC_UINT32 hash3_pful_cfg;
-}DPP_SE_AS_HASH3_PFUL_CFG_T;
-
-typedef struct dpp_se_as_pbu_pful_cfg_t
-{
-    ZXIC_UINT32 pbu_pful_cfg;
-}DPP_SE_AS_PBU_PFUL_CFG_T;
-
-typedef struct dpp_se_as_lpm_pful_cfg_t
-{
-    ZXIC_UINT32 lpm_pful_cfg;
-}DPP_SE_AS_LPM_PFUL_CFG_T;
-
-typedef struct dpp_se_as_etcam_pful_cfg_t
-{
-    ZXIC_UINT32 etcam_pful_cfg;
-}DPP_SE_AS_ETCAM_PFUL_CFG_T;
-
-typedef struct dpp_se_as_as_learn0_fifo_cfg_t
-{
-    ZXIC_UINT32 as_learn1_pful_negate;
-    ZXIC_UINT32 as_learn1_pful_asert;
-    ZXIC_UINT32 as_learn0_pful_negate;
-    ZXIC_UINT32 as_learn0_pful_asert;
-}DPP_SE_AS_AS_LEARN0_FIFO_CFG_T;
-
-typedef struct dpp_se_as_as_learn1_fifo_cfg_t
-{
-    ZXIC_UINT32 as_learn3_pful_negate;
-    ZXIC_UINT32 as_learn3_pful_asert;
-    ZXIC_UINT32 as_learn2_pful_negate;
-    ZXIC_UINT32 as_learn2_pful_asert;
-}DPP_SE_AS_AS_LEARN1_FIFO_CFG_T;
-
-typedef struct dpp_se_as_as_dma_fifo_cfg_t
-{
-    ZXIC_UINT32 as_dma_fifo_cfg;
-}DPP_SE_AS_AS_DMA_FIFO_CFG_T;
-
-typedef struct dpp_se_as_age_pful_cfg_t
-{
-    ZXIC_UINT32 age_pful_cfg;
-}DPP_SE_AS_AGE_PFUL_CFG_T;
-
-typedef struct dpp_se_as_etcam_rsp_cfg_t
-{
-    ZXIC_UINT32 eram_rsp_pful_negate;
-    ZXIC_UINT32 eram_rsp_pful_assert;
-    ZXIC_UINT32 etcam_rsp_pful_negate;
-    ZXIC_UINT32 etcam_rsp_pful_assert;
-}DPP_SE_AS_ETCAM_RSP_CFG_T;
-
-typedef struct dpp_se_as_pbu_ecc_bypass_read_t
-{
-    ZXIC_UINT32 pbu_ecc_bypass_read;
-}DPP_SE_AS_PBU_ECC_BYPASS_READ_T;
-
-typedef struct dpp_se_as_etcam0_ecc_bypass_read_t
-{
-    ZXIC_UINT32 etcam0_ecc_bypass_read;
-}DPP_SE_AS_ETCAM0_ECC_BYPASS_READ_T;
-
-typedef struct dpp_se_as_etcam1_ecc_bypass_read_t
-{
-    ZXIC_UINT32 etcam1_ecc_bypass_read;
-}DPP_SE_AS_ETCAM1_ECC_BYPASS_READ_T;
-
-typedef struct dpp_se_as_lpm_ecc_bypass_read_t
-{
-    ZXIC_UINT32 lpm_ecc_bypass_read;
-}DPP_SE_AS_LPM_ECC_BYPASS_READ_T;
-
-typedef struct dpp_se_as_hash_ecc_bypass_read_t
-{
-    ZXIC_UINT32 hash3_ecc_bypass_read;
-    ZXIC_UINT32 hash2_ecc_bypass_read;
-    ZXIC_UINT32 hash1_ecc_bypass_read;
-    ZXIC_UINT32 hash0_ecc_bypass_read;
-}DPP_SE_AS_HASH_ECC_BYPASS_READ_T;
-
-typedef struct dpp_se_as_hash_learn_ecc_bypass_read_t
-{
-    ZXIC_UINT32 hash_learn_ecc_bypass_read;
-}DPP_SE_AS_HASH_LEARN_ECC_BYPASS_READ_T;
-
-typedef struct dpp_se_as_debug_cnt_mode_t
-{
-    ZXIC_UINT32 cnt_rd_mode;
-    ZXIC_UINT32 cnt_overflow_mode;
-}DPP_SE_AS_DEBUG_CNT_MODE_T;
-
-typedef struct dpp_se_as_as_int_0_en_t
-{
-    ZXIC_UINT32 as_int_0_en;
-}DPP_SE_AS_AS_INT_0_EN_T;
-
-typedef struct dpp_se_as_as_int_0_mask_t
-{
-    ZXIC_UINT32 as_int_0_mask;
-}DPP_SE_AS_AS_INT_0_MASK_T;
-
-typedef struct dpp_se_as_as_int_1_en_t
-{
-    ZXIC_UINT32 as_int_1_en;
-}DPP_SE_AS_AS_INT_1_EN_T;
-
-typedef struct dpp_se_as_as_int_1_mask_t
-{
-    ZXIC_UINT32 as_int_1_mask;
-}DPP_SE_AS_AS_INT_1_MASK_T;
-
-typedef struct dpp_se_as_as_int_2_en_t
-{
-    ZXIC_UINT32 as_int_2_en;
-}DPP_SE_AS_AS_INT_2_EN_T;
-
-typedef struct dpp_se_as_as_int_2_mask_t
-{
-    ZXIC_UINT32 as_int_2_mask;
-}DPP_SE_AS_AS_INT_2_MASK_T;
-
-typedef struct dpp_se_as_as_int_0_status_t
-{
-    ZXIC_UINT32 port0_int_status;
-}DPP_SE_AS_AS_INT_0_STATUS_T;
-
-typedef struct dpp_se_as_as_int_1_status_t
-{
-    ZXIC_UINT32 port1_int_status;
-}DPP_SE_AS_AS_INT_1_STATUS_T;
-
-typedef struct dpp_se_as_as_int_2_status_t
-{
-    ZXIC_UINT32 port2_int_status;
-}DPP_SE_AS_AS_INT_2_STATUS_T;
-
-typedef struct dpp_se_as_se_as_int_status_t
-{
-    ZXIC_UINT32 as_int_2_unmask_flag;
-    ZXIC_UINT32 as_int_1_unmask_flag;
-    ZXIC_UINT32 as_int_0_unmask_flag;
-}DPP_SE_AS_SE_AS_INT_STATUS_T;
-
-typedef struct dpp_se_as_hash0_3_wr_req_cnt_t
-{
-    ZXIC_UINT32 hash0_3_wr_req_cnt;
-}DPP_SE_AS_HASH0_3_WR_REQ_CNT_T;
-
-typedef struct dpp_se_as_smmu0_etcam0_1_fc_cnt_t
-{
-    ZXIC_UINT32 smmu0_etcam0_1_fc_cnt;
-}DPP_SE_AS_SMMU0_ETCAM0_1_FC_CNT_T;
-
-typedef struct dpp_se_as_etcam0_1_smmu0_req_cnt_t
-{
-    ZXIC_UINT32 etcam0_1_smmu0_req_cnt;
-}DPP_SE_AS_ETCAM0_1_SMMU0_REQ_CNT_T;
-
-typedef struct dpp_se_as_smmu0_etcam0_1_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu0_etcam0_1_rsp_cnt;
-}DPP_SE_AS_SMMU0_ETCAM0_1_RSP_CNT_T;
-
-typedef struct dpp_se_as_as_hla_hash_p0_3_key_cnt_t
-{
-    ZXIC_UINT32 as_hla_hash_p0_3_key_cnt;
-}DPP_SE_AS_AS_HLA_HASH_P0_3_KEY_CNT_T;
-
-typedef struct dpp_se_as_as_hla_lpm_p0_key_cnt_t
-{
-    ZXIC_UINT32 as_hla_lpm_p0_key_cnt;
-}DPP_SE_AS_AS_HLA_LPM_P0_KEY_CNT_T;
-
-typedef struct dpp_se_as_alg_as_hash_p0_3_rsp_cnt_t
-{
-    ZXIC_UINT32 alg_as_hash_p0_3_rsp_cnt;
-}DPP_SE_AS_ALG_AS_HASH_P0_3_RSP_CNT_T;
-
-typedef struct dpp_se_as_alg_as_hash_p0_3_smf_rsp_cnt_t
-{
-    ZXIC_UINT32 alg_as_hash_p0_3_smf_rsp_cnt;
-}DPP_SE_AS_ALG_AS_HASH_P0_3_SMF_RSP_CNT_T;
-
-typedef struct dpp_se_as_alg_as_lpm_p0_rsp_cnt_t
-{
-    ZXIC_UINT32 alg_as_lpm_p0_rsp_cnt;
-}DPP_SE_AS_ALG_AS_LPM_P0_RSP_CNT_T;
-
-typedef struct dpp_se_as_alg_as_lpm_p0_3_smf_rsp_cnt_t
-{
-    ZXIC_UINT32 alg_as_lpm_p0_3_smf_rsp_cnt;
-}DPP_SE_AS_ALG_AS_LPM_P0_3_SMF_RSP_CNT_T;
-
-typedef struct dpp_se_as_as_pbu_key_cnt_t
-{
-    ZXIC_UINT32 as_pbu_key_cnt;
-}DPP_SE_AS_AS_PBU_KEY_CNT_T;
-
-typedef struct dpp_se_as_pbu_se_dpi_rsp_dat_cnt_t
-{
-    ZXIC_UINT32 pbu_se_dpi_rsp_dat_cnt;
-}DPP_SE_AS_PBU_SE_DPI_RSP_DAT_CNT_T;
-
-typedef struct dpp_se_as_as_etcam_ctrl_req0_cnt_t
-{
-    ZXIC_UINT32 as_etcam_ctrl_req0_cnt;
-}DPP_SE_AS_AS_ETCAM_CTRL_REQ0_CNT_T;
-
-typedef struct dpp_se_as_etcam_ctrl_as_index0_1_cnt_t
-{
-    ZXIC_UINT32 etcam_ctrl_as_index0_1_cnt;
-}DPP_SE_AS_ETCAM_CTRL_AS_INDEX0_1_CNT_T;
-
-typedef struct dpp_se_as_etcam_ctrl_as_hit0_1_cnt_t
-{
-    ZXIC_UINT32 etcam_ctrl_as_hit0_1_cnt;
-}DPP_SE_AS_ETCAM_CTRL_AS_HIT0_1_CNT_T;
-
-typedef struct dpp_se_as_as_smmu0_req_cnt_t
-{
-    ZXIC_UINT32 as_smmu0_req_cnt;
-}DPP_SE_AS_AS_SMMU0_REQ_CNT_T;
-
-typedef struct dpp_se_as_learn_hla_wr_cnt_t
-{
-    ZXIC_UINT32 learn_hla_wr_cnt;
-}DPP_SE_AS_LEARN_HLA_WR_CNT_T;
-
-typedef struct dpp_se_as_as_smmu1_req_cnt_t
-{
-    ZXIC_UINT32 as_smmu1_req_cnt;
-}DPP_SE_AS_AS_SMMU1_REQ_CNT_T;
-
-typedef struct dpp_se_as_se_cfg_mac_dat_cnt_t
-{
-    ZXIC_UINT32 se_cfg_mac_dat_cnt;
-}DPP_SE_AS_SE_CFG_MAC_DAT_CNT_T;
-
-typedef struct dpp_se_as_alg_as_hash_p0_3_fc_cnt_t
-{
-    ZXIC_UINT32 alg_as_hash_p0_3_fc_cnt;
-}DPP_SE_AS_ALG_AS_HASH_P0_3_FC_CNT_T;
-
-typedef struct dpp_se_as_alg_as_lpm_p0_fc_cnt_t
-{
-    ZXIC_UINT32 alg_as_lpm_p0_fc_cnt;
-}DPP_SE_AS_ALG_AS_LPM_P0_FC_CNT_T;
-
-typedef struct dpp_se_as_as_alg_hash_p0_3_fc_cnt_t
-{
-    ZXIC_UINT32 as_alg_hash_p0_3_fc_cnt;
-}DPP_SE_AS_AS_ALG_HASH_P0_3_FC_CNT_T;
-
-typedef struct dpp_se_as_as_alg_lpm_p0_fc_cnt_t
-{
-    ZXIC_UINT32 as_alg_lpm_p0_fc_cnt;
-}DPP_SE_AS_AS_ALG_LPM_P0_FC_CNT_T;
-
-typedef struct dpp_se_as_as_pbu_fc_cnt_t
-{
-    ZXIC_UINT32 as_pbu_fc_cnt;
-}DPP_SE_AS_AS_PBU_FC_CNT_T;
-
-typedef struct dpp_se_as_pbu_se_dpi_key_fc_cnt_t
-{
-    ZXIC_UINT32 pbu_se_dpi_key_fc_cnt;
-}DPP_SE_AS_PBU_SE_DPI_KEY_FC_CNT_T;
-
-typedef struct dpp_se_as_as_etcam_ctrl_fc0_1_cnt_t
-{
-    ZXIC_UINT32 as_etcam_ctrl_fc0_1_cnt;
-}DPP_SE_AS_AS_ETCAM_CTRL_FC0_1_CNT_T;
-
-typedef struct dpp_se_as_etcam_ctrl_as_fc0_1_cnt_t
-{
-    ZXIC_UINT32 etcam_ctrl_as_fc0_1_cnt;
-}DPP_SE_AS_ETCAM_CTRL_AS_FC0_1_CNT_T;
-
-typedef struct dpp_se_as_smmu0_as_mac_age_fc_cnt_t
-{
-    ZXIC_UINT32 smmu0_as_mac_age_fc_cnt;
-}DPP_SE_AS_SMMU0_AS_MAC_AGE_FC_CNT_T;
-
-typedef struct dpp_se_as_alg_learn_fc_cnt_t
-{
-    ZXIC_UINT32 alg_learn_fc_cnt;
-}DPP_SE_AS_ALG_LEARN_FC_CNT_T;
-
-typedef struct dpp_se_as_smmu1_as_fc_cnt_t
-{
-    ZXIC_UINT32 smmu1_as_fc_cnt;
-}DPP_SE_AS_SMMU1_AS_FC_CNT_T;
-
-typedef struct dpp_se_as_cfg_se_mac_fc_cnt_t
-{
-    ZXIC_UINT32 cfg_se_mac_fc_cnt;
-}DPP_SE_AS_CFG_SE_MAC_FC_CNT_T;
-
-typedef struct dpp_se_kschd_kschd_cpu_rdy_t
-{
-    ZXIC_UINT32 kschd_cpu_rdy;
-}DPP_SE_KSCHD_KSCHD_CPU_RDY_T;
-
-typedef struct dpp_se_kschd_ppu0_ecc_bypass_read_t
-{
-    ZXIC_UINT32 ppu0_ecc_bypass_read;
-}DPP_SE_KSCHD_PPU0_ECC_BYPASS_READ_T;
-
-typedef struct dpp_se_kschd_pbu_ecc_bypass_read_t
-{
-    ZXIC_UINT32 pbu_ecc_bypass_read;
-}DPP_SE_KSCHD_PBU_ECC_BYPASS_READ_T;
-
-typedef struct dpp_se_kschd_smmu1_ecc_bypass_read_t
-{
-    ZXIC_UINT32 u3_smmu1_ecc_bypass_read;
-    ZXIC_UINT32 u2_smmu1_ecc_bypass_read;
-    ZXIC_UINT32 u1_smmu1_ecc_bypass_read;
-    ZXIC_UINT32 u0_smmu1_ecc_bypass_read;
-}DPP_SE_KSCHD_SMMU1_ECC_BYPASS_READ_T;
-
-typedef struct dpp_se_kschd_ass_ecc_bypass_read_t
-{
-    ZXIC_UINT32 ass_ecc_bypass_read;
-}DPP_SE_KSCHD_ASS_ECC_BYPASS_READ_T;
-
-typedef struct dpp_se_kschd_sdt_h_t
-{
-    ZXIC_UINT32 sdt_h;
-}DPP_SE_KSCHD_SDT_H_T;
-
-typedef struct dpp_se_kschd_sdt_l_t
-{
-    ZXIC_UINT32 sdt_l;
-}DPP_SE_KSCHD_SDT_L_T;
-
-typedef struct dpp_se_kschd_hash_key15_t
-{
-    ZXIC_UINT32 dma_en;
-    ZXIC_UINT32 delete_en;
-    ZXIC_UINT32 hash_key15;
-}DPP_SE_KSCHD_HASH_KEY15_T;
-
-typedef struct dpp_se_kschd_hash_key14_t
-{
-    ZXIC_UINT32 hash_key14;
-}DPP_SE_KSCHD_HASH_KEY14_T;
-
-typedef struct dpp_se_kschd_hash_key13_t
-{
-    ZXIC_UINT32 hash_key13;
-}DPP_SE_KSCHD_HASH_KEY13_T;
-
-typedef struct dpp_se_kschd_hash_key12_t
-{
-    ZXIC_UINT32 hash_key12;
-}DPP_SE_KSCHD_HASH_KEY12_T;
-
-typedef struct dpp_se_kschd_hash_key11_t
-{
-    ZXIC_UINT32 hash_key11;
-}DPP_SE_KSCHD_HASH_KEY11_T;
-
-typedef struct dpp_se_kschd_hash_key10_t
-{
-    ZXIC_UINT32 hash_key10;
-}DPP_SE_KSCHD_HASH_KEY10_T;
-
-typedef struct dpp_se_kschd_hash_key9_t
-{
-    ZXIC_UINT32 hash_key9;
-}DPP_SE_KSCHD_HASH_KEY9_T;
-
-typedef struct dpp_se_kschd_hash_key8_t
-{
-    ZXIC_UINT32 hash_key8;
-}DPP_SE_KSCHD_HASH_KEY8_T;
-
-typedef struct dpp_se_kschd_hash_key7_t
-{
-    ZXIC_UINT32 hash_key7;
-}DPP_SE_KSCHD_HASH_KEY7_T;
-
-typedef struct dpp_se_kschd_hash_key6_t
-{
-    ZXIC_UINT32 hash_key6;
-}DPP_SE_KSCHD_HASH_KEY6_T;
-
-typedef struct dpp_se_kschd_hash_key5_t
-{
-    ZXIC_UINT32 hash_key5;
-}DPP_SE_KSCHD_HASH_KEY5_T;
-
-typedef struct dpp_se_kschd_hash_key4_t
-{
-    ZXIC_UINT32 hash_key4;
-}DPP_SE_KSCHD_HASH_KEY4_T;
-
-typedef struct dpp_se_kschd_hash_key3_t
-{
-    ZXIC_UINT32 hash_key3;
-}DPP_SE_KSCHD_HASH_KEY3_T;
-
-typedef struct dpp_se_kschd_hash_key2_t
-{
-    ZXIC_UINT32 hash_key2;
-}DPP_SE_KSCHD_HASH_KEY2_T;
-
-typedef struct dpp_se_kschd_hash_key1_t
-{
-    ZXIC_UINT32 hash_key1;
-}DPP_SE_KSCHD_HASH_KEY1_T;
-
-typedef struct dpp_se_kschd_hash_key0_t
-{
-    ZXIC_UINT32 hash_key0;
-}DPP_SE_KSCHD_HASH_KEY0_T;
-
-typedef struct dpp_se_kschd_schd_int_0_en_t
-{
-    ZXIC_UINT32 port0_int_en;
-}DPP_SE_KSCHD_SCHD_INT_0_EN_T;
-
-typedef struct dpp_se_kschd_schd_int_0_mask_t
-{
-    ZXIC_UINT32 port0_int_mask;
-}DPP_SE_KSCHD_SCHD_INT_0_MASK_T;
-
-typedef struct dpp_se_kschd_schd_int_1_en_t
-{
-    ZXIC_UINT32 port1_int_en;
-}DPP_SE_KSCHD_SCHD_INT_1_EN_T;
-
-typedef struct dpp_se_kschd_schd_int_1_mask_t
-{
-    ZXIC_UINT32 port1_int_mask;
-}DPP_SE_KSCHD_SCHD_INT_1_MASK_T;
-
-typedef struct dpp_se_kschd_schd_int_2_en_t
-{
-    ZXIC_UINT32 port2_int_en;
-}DPP_SE_KSCHD_SCHD_INT_2_EN_T;
-
-typedef struct dpp_se_kschd_schd_int_2_mask_t
-{
-    ZXIC_UINT32 port2_int_mask;
-}DPP_SE_KSCHD_SCHD_INT_2_MASK_T;
-
-typedef struct dpp_se_kschd_schd_int_3_en_t
-{
-    ZXIC_UINT32 port3_int_en;
-}DPP_SE_KSCHD_SCHD_INT_3_EN_T;
-
-typedef struct dpp_se_kschd_schd_int_3_mask_t
-{
-    ZXIC_UINT32 port3_int_mask;
-}DPP_SE_KSCHD_SCHD_INT_3_MASK_T;
-
-typedef struct dpp_se_kschd_schd_int_4_en_t
-{
-    ZXIC_UINT32 port4_int_en;
-}DPP_SE_KSCHD_SCHD_INT_4_EN_T;
-
-typedef struct dpp_se_kschd_schd_int_4_mask_t
-{
-    ZXIC_UINT32 port4_int_mask;
-}DPP_SE_KSCHD_SCHD_INT_4_MASK_T;
-
-typedef struct dpp_se_kschd_schd_int_0_status_t
-{
-    ZXIC_UINT32 port0_int_status;
-}DPP_SE_KSCHD_SCHD_INT_0_STATUS_T;
-
-typedef struct dpp_se_kschd_schd_int_1_status_t
-{
-    ZXIC_UINT32 port1_int_status;
-}DPP_SE_KSCHD_SCHD_INT_1_STATUS_T;
-
-typedef struct dpp_se_kschd_schd_int_2_status_t
-{
-    ZXIC_UINT32 port2_int_status;
-}DPP_SE_KSCHD_SCHD_INT_2_STATUS_T;
-
-typedef struct dpp_se_kschd_schd_int_3_status_t
-{
-    ZXIC_UINT32 port3_int_status;
-}DPP_SE_KSCHD_SCHD_INT_3_STATUS_T;
-
-typedef struct dpp_se_kschd_schd_int_4_status_t
-{
-    ZXIC_UINT32 port4_int_status;
-}DPP_SE_KSCHD_SCHD_INT_4_STATUS_T;
-
-typedef struct dpp_se_kschd_se_kschd_int_status_t
-{
-    ZXIC_UINT32 schd_int4_unmask_flag;
-    ZXIC_UINT32 schd_int3_unmask_flag;
-    ZXIC_UINT32 schd_int2_unmask_flag;
-    ZXIC_UINT32 schd_int1_unmask_flag;
-    ZXIC_UINT32 schd_int0_unmask_flag;
-}DPP_SE_KSCHD_SE_KSCHD_INT_STATUS_T;
-
-typedef struct dpp_se_kschd_debug_cnt_mode_t
-{
-    ZXIC_UINT32 cnt_rd_mode;
-    ZXIC_UINT32 cnt_overflow_mode;
-}DPP_SE_KSCHD_DEBUG_CNT_MODE_T;
-
-typedef struct dpp_se_kschd_se_parser_kschd_key0_3_cnt_t
-{
-    ZXIC_UINT32 se_parser_kschd_key0_3_cnt;
-}DPP_SE_KSCHD_SE_PARSER_KSCHD_KEY0_3_CNT_T;
-
-typedef struct dpp_se_kschd_se_smmu1_key0_3_cnt_t
-{
-    ZXIC_UINT32 se_smmu1_key0_3_cnt;
-}DPP_SE_KSCHD_SE_SMMU1_KEY0_3_CNT_T;
-
-typedef struct dpp_se_kschd_kschd_as_key0_cnt_t
-{
-    ZXIC_UINT32 kschd_as_key0_cnt;
-}DPP_SE_KSCHD_KSCHD_AS_KEY0_CNT_T;
-
-typedef struct dpp_se_kschd_kschd_as_key1_cnt_t
-{
-    ZXIC_UINT32 kschd_as_key1_cnt;
-}DPP_SE_KSCHD_KSCHD_AS_KEY1_CNT_T;
-
-typedef struct dpp_se_kschd_kschd_as_key2_cnt_t
-{
-    ZXIC_UINT32 kschd_as_key2_cnt;
-}DPP_SE_KSCHD_KSCHD_AS_KEY2_CNT_T;
-
-typedef struct dpp_se_kschd_kschd_as_key3_cnt_t
-{
-    ZXIC_UINT32 kschd_as_key3_cnt;
-}DPP_SE_KSCHD_KSCHD_AS_KEY3_CNT_T;
-
-typedef struct dpp_se_kschd_kschd_as_key4_cnt_t
-{
-    ZXIC_UINT32 kschd_as_key4_cnt;
-}DPP_SE_KSCHD_KSCHD_AS_KEY4_CNT_T;
-
-typedef struct dpp_se_kschd_kschd_as_key5_cnt_t
-{
-    ZXIC_UINT32 kschd_as_key5_cnt;
-}DPP_SE_KSCHD_KSCHD_AS_KEY5_CNT_T;
-
-typedef struct dpp_se_kschd_kschd_as_key6_cnt_t
-{
-    ZXIC_UINT32 kschd_as_key6_cnt;
-}DPP_SE_KSCHD_KSCHD_AS_KEY6_CNT_T;
-
-typedef struct dpp_se_kschd_kschd_as_key9_cnt_t
-{
-    ZXIC_UINT32 kschd_as_key9_cnt;
-}DPP_SE_KSCHD_KSCHD_AS_KEY9_CNT_T;
-
-typedef struct dpp_se_kschd_kschd_se_parser_fc0_3_cnt_t
-{
-    ZXIC_UINT32 kschd_se_parser_fc0_3_cnt;
-}DPP_SE_KSCHD_KSCHD_SE_PARSER_FC0_3_CNT_T;
-
-typedef struct dpp_se_kschd_smmu1_se_fc0_3_cnt_t
-{
-    ZXIC_UINT32 smmu1_se_fc0_3_cnt;
-}DPP_SE_KSCHD_SMMU1_SE_FC0_3_CNT_T;
-
-typedef struct dpp_se_kschd_as_kschd_fc_cnt0_t
-{
-    ZXIC_UINT32 as_kschd_fc_cnt0;
-}DPP_SE_KSCHD_AS_KSCHD_FC_CNT0_T;
-
-typedef struct dpp_se_kschd_as_kschd_fc_cnt1_t
-{
-    ZXIC_UINT32 as_kschd_fc_cnt1;
-}DPP_SE_KSCHD_AS_KSCHD_FC_CNT1_T;
-
-typedef struct dpp_se_kschd_as_kschd_fc_cnt2_t
-{
-    ZXIC_UINT32 as_kschd_fc_cnt2;
-}DPP_SE_KSCHD_AS_KSCHD_FC_CNT2_T;
-
-typedef struct dpp_se_kschd_as_kschd_fc_cnt3_t
-{
-    ZXIC_UINT32 as_kschd_fc_cnt3;
-}DPP_SE_KSCHD_AS_KSCHD_FC_CNT3_T;
-
-typedef struct dpp_se_kschd_as_kschd_fc_cnt4_t
-{
-    ZXIC_UINT32 as_kschd_fc_cnt4;
-}DPP_SE_KSCHD_AS_KSCHD_FC_CNT4_T;
-
-typedef struct dpp_se_kschd_as_kschd_fc_cnt5_t
-{
-    ZXIC_UINT32 as_kschd_fc_cnt5;
-}DPP_SE_KSCHD_AS_KSCHD_FC_CNT5_T;
-
-typedef struct dpp_se_kschd_as_kschd_fc_cnt6_t
-{
-    ZXIC_UINT32 as_kschd_fc_cnt6;
-}DPP_SE_KSCHD_AS_KSCHD_FC_CNT6_T;
-
-typedef struct dpp_se_kschd_as_kschd_fc_cnt9_t
-{
-    ZXIC_UINT32 as_kschd_fc_cnt9;
-}DPP_SE_KSCHD_AS_KSCHD_FC_CNT9_T;
-
-typedef struct dpp_se_rschd_rschd_hash_pful_cfg_t
-{
-    ZXIC_UINT32 rschd_hash_pful_cfg;
-}DPP_SE_RSCHD_RSCHD_HASH_PFUL_CFG_T;
-
-typedef struct dpp_se_rschd_rschd_hash_ept_cfg_t
-{
-    ZXIC_UINT32 rschd_hash_ept_cfg;
-}DPP_SE_RSCHD_RSCHD_HASH_EPT_CFG_T;
-
-typedef struct dpp_se_rschd_rschd_pbu_pful_cfg_t
-{
-    ZXIC_UINT32 rschd_pbu_pful_cfg;
-}DPP_SE_RSCHD_RSCHD_PBU_PFUL_CFG_T;
-
-typedef struct dpp_se_rschd_rschd_pbu_ept_cfg_t
-{
-    ZXIC_UINT32 rschd_pbu_ept_cfg;
-}DPP_SE_RSCHD_RSCHD_PBU_EPT_CFG_T;
-
-typedef struct dpp_se_rschd_rschd_lpm_pful_cfg_t
-{
-    ZXIC_UINT32 rschd_lpm_pful_cfg;
-}DPP_SE_RSCHD_RSCHD_LPM_PFUL_CFG_T;
-
-typedef struct dpp_se_rschd_rschd_lpm_ept_cfg_t
-{
-    ZXIC_UINT32 rschd_lpm_ept_cfg;
-}DPP_SE_RSCHD_RSCHD_LPM_EPT_CFG_T;
-
-typedef struct dpp_se_rschd_rschd_etcam_pful_cfg_t
-{
-    ZXIC_UINT32 rschd_etcam_pful_cfg;
-}DPP_SE_RSCHD_RSCHD_ETCAM_PFUL_CFG_T;
-
-typedef struct dpp_se_rschd_rschd_etcam_ept_cfg_t
-{
-    ZXIC_UINT32 rschd_etcam_ept_cfg;
-}DPP_SE_RSCHD_RSCHD_ETCAM_EPT_CFG_T;
-
-typedef struct dpp_se_rschd_smmu0_wb_pful_cfg_t
-{
-    ZXIC_UINT32 smmu0_wb_pful_cfg;
-}DPP_SE_RSCHD_SMMU0_WB_PFUL_CFG_T;
-
-typedef struct dpp_se_rschd_smmu0_wb_ept_cfg_t
-{
-    ZXIC_UINT32 smmu0_wb_ept_cfg;
-}DPP_SE_RSCHD_SMMU0_WB_EPT_CFG_T;
-
-typedef struct dpp_se_rschd_smmu1_wb_pful_cfg_t
-{
-    ZXIC_UINT32 smmu1_wb_pful_cfg;
-}DPP_SE_RSCHD_SMMU1_WB_PFUL_CFG_T;
-
-typedef struct dpp_se_rschd_smmu1_wb_ept_cfg_t
-{
-    ZXIC_UINT32 smmu1_wb_ept_cfg;
-}DPP_SE_RSCHD_SMMU1_WB_EPT_CFG_T;
-
-typedef struct dpp_se_rschd_alg_wb_pful_cfg_t
-{
-    ZXIC_UINT32 alg_wb_pful_cfg;
-}DPP_SE_RSCHD_ALG_WB_PFUL_CFG_T;
-
-typedef struct dpp_se_rschd_alg_wb_ept_cfg_t
-{
-    ZXIC_UINT32 alg_wb_ept_cfg;
-}DPP_SE_RSCHD_ALG_WB_EPT_CFG_T;
-
-typedef struct dpp_se_rschd_wr_rsp_vld_en_t
-{
-    ZXIC_UINT32 wr_rsp_vld_en;
-}DPP_SE_RSCHD_WR_RSP_VLD_EN_T;
-
-typedef struct dpp_se_rschd_nppu_wb_pful_cfg_t
-{
-    ZXIC_UINT32 nppu_wb_pful_cfg;
-}DPP_SE_RSCHD_NPPU_WB_PFUL_CFG_T;
-
-typedef struct dpp_se_rschd_nppu_wb_ept_cfg_t
-{
-    ZXIC_UINT32 nppu_wb_ept_cfg;
-}DPP_SE_RSCHD_NPPU_WB_EPT_CFG_T;
-
-typedef struct dpp_se_rschd_port0_int_en_t
-{
-    ZXIC_UINT32 port0_int_en;
-}DPP_SE_RSCHD_PORT0_INT_EN_T;
-
-typedef struct dpp_se_rschd_port0_int_mask_t
-{
-    ZXIC_UINT32 port0_int_mask;
-}DPP_SE_RSCHD_PORT0_INT_MASK_T;
-
-typedef struct dpp_se_rschd_port1_int_en_t
-{
-    ZXIC_UINT32 port1_int_en;
-}DPP_SE_RSCHD_PORT1_INT_EN_T;
-
-typedef struct dpp_se_rschd_port1_int_mask_t
-{
-    ZXIC_UINT32 port1_int_mask;
-}DPP_SE_RSCHD_PORT1_INT_MASK_T;
-
-typedef struct dpp_se_rschd_port0_int_status_t
-{
-    ZXIC_UINT32 port0_int_status;
-}DPP_SE_RSCHD_PORT0_INT_STATUS_T;
-
-typedef struct dpp_se_rschd_port1_int_status_t
-{
-    ZXIC_UINT32 port1_int_status;
-}DPP_SE_RSCHD_PORT1_INT_STATUS_T;
-
-typedef struct dpp_se_rschd_se_rschd_int_status_t
-{
-    ZXIC_UINT32 port1_int_unmask_flag;
-    ZXIC_UINT32 port0_int_unmask_flag;
-}DPP_SE_RSCHD_SE_RSCHD_INT_STATUS_T;
-
-typedef struct dpp_se_rschd_debug_cnt_mode_t
-{
-    ZXIC_UINT32 cnt_rd_mode;
-    ZXIC_UINT32 cnt_overflow_mode;
-}DPP_SE_RSCHD_DEBUG_CNT_MODE_T;
-
-typedef struct dpp_se_rschd_se_ppu_mex0_5_rsp1_cnt_t
-{
-    ZXIC_UINT32 se_ppu_mex0_5_rsp1_cnt;
-}DPP_SE_RSCHD_SE_PPU_MEX0_5_RSP1_CNT_T;
-
-typedef struct dpp_se_rschd_as_rschd_rsp0_cnt_t
-{
-    ZXIC_UINT32 as_rschd_rsp0_cnt;
-}DPP_SE_RSCHD_AS_RSCHD_RSP0_CNT_T;
-
-typedef struct dpp_se_rschd_as_rschd_rsp1_cnt_t
-{
-    ZXIC_UINT32 as_rschd_rsp1_cnt;
-}DPP_SE_RSCHD_AS_RSCHD_RSP1_CNT_T;
-
-typedef struct dpp_se_rschd_as_rschd_rsp2_cnt_t
-{
-    ZXIC_UINT32 as_rschd_rsp2_cnt;
-}DPP_SE_RSCHD_AS_RSCHD_RSP2_CNT_T;
-
-typedef struct dpp_se_rschd_as_rschd_rsp3_cnt_t
-{
-    ZXIC_UINT32 as_rschd_rsp3_cnt;
-}DPP_SE_RSCHD_AS_RSCHD_RSP3_CNT_T;
-
-typedef struct dpp_se_rschd_as_rschd_rsp4_cnt_t
-{
-    ZXIC_UINT32 as_rschd_rsp4_cnt;
-}DPP_SE_RSCHD_AS_RSCHD_RSP4_CNT_T;
-
-typedef struct dpp_se_rschd_as_rschd_rsp5_cnt_t
-{
-    ZXIC_UINT32 as_rschd_rsp5_cnt;
-}DPP_SE_RSCHD_AS_RSCHD_RSP5_CNT_T;
-
-typedef struct dpp_se_rschd_as_rschd_rsp6_cnt_t
-{
-    ZXIC_UINT32 as_rschd_rsp6_cnt;
-}DPP_SE_RSCHD_AS_RSCHD_RSP6_CNT_T;
-
-typedef struct dpp_se_rschd_as_rschd_rsp9_cnt_t
-{
-    ZXIC_UINT32 as_rschd_rsp9_cnt;
-}DPP_SE_RSCHD_AS_RSCHD_RSP9_CNT_T;
-
-typedef struct dpp_se_rschd_smmu1_se_rsp0_3_cnt_t
-{
-    ZXIC_UINT32 smmu1_se_rsp0_3_cnt;
-}DPP_SE_RSCHD_SMMU1_SE_RSP0_3_CNT_T;
-
-typedef struct dpp_se_rschd_ppu_se_mex0_3_fc_cnt_t
-{
-    ZXIC_UINT32 ppu_se_mex0_3_fc_cnt;
-}DPP_SE_RSCHD_PPU_SE_MEX0_3_FC_CNT_T;
-
-typedef struct dpp_se_rschd_rschd_as_fc_cnt0_t
-{
-    ZXIC_UINT32 rschd_as_fc_cnt0;
-}DPP_SE_RSCHD_RSCHD_AS_FC_CNT0_T;
-
-typedef struct dpp_se_rschd_rschd_as_fc_cnt1_t
-{
-    ZXIC_UINT32 rschd_as_fc_cnt1;
-}DPP_SE_RSCHD_RSCHD_AS_FC_CNT1_T;
-
-typedef struct dpp_se_rschd_rschd_as_fc_cnt2_t
-{
-    ZXIC_UINT32 rschd_as_fc_cnt2;
-}DPP_SE_RSCHD_RSCHD_AS_FC_CNT2_T;
-
-typedef struct dpp_se_rschd_rschd_as_fc_cnt3_t
-{
-    ZXIC_UINT32 rschd_as_fc_cnt3;
-}DPP_SE_RSCHD_RSCHD_AS_FC_CNT3_T;
-
-typedef struct dpp_se_rschd_rschd_as_fc_cnt4_t
-{
-    ZXIC_UINT32 rschd_as_fc_cnt4;
-}DPP_SE_RSCHD_RSCHD_AS_FC_CNT4_T;
-
-typedef struct dpp_se_rschd_rschd_as_fc_cnt5_t
-{
-    ZXIC_UINT32 rschd_as_fc_cnt5;
-}DPP_SE_RSCHD_RSCHD_AS_FC_CNT5_T;
-
-typedef struct dpp_se_rschd_rschd_as_fc_cnt6_t
-{
-    ZXIC_UINT32 rschd_as_fc_cnt6;
-}DPP_SE_RSCHD_RSCHD_AS_FC_CNT6_T;
-
-typedef struct dpp_se_rschd_rschd_as_fc_cnt9_t
-{
-    ZXIC_UINT32 rschd_as_fc_cnt9;
-}DPP_SE_RSCHD_RSCHD_AS_FC_CNT9_T;
-
-typedef struct dpp_se_rschd_se_smmu1_fc0_3_cnt_t
-{
-    ZXIC_UINT32 se_smmu1_fc0_3_cnt;
-}DPP_SE_RSCHD_SE_SMMU1_FC0_3_CNT_T;
-
-typedef struct dpp_se_rschd_smmu0_se_wr_done_cnt_t
-{
-    ZXIC_UINT32 smmu0_se_wr_done_cnt;
-}DPP_SE_RSCHD_SMMU0_SE_WR_DONE_CNT_T;
-
-typedef struct dpp_se_rschd_se_smmu0_wr_done_fc_cnt_t
-{
-    ZXIC_UINT32 se_smmu0_wr_done_fc_cnt;
-}DPP_SE_RSCHD_SE_SMMU0_WR_DONE_FC_CNT_T;
-
-typedef struct dpp_se_rschd_smmu1_se_wr_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu1_se_wr_rsp_cnt;
-}DPP_SE_RSCHD_SMMU1_SE_WR_RSP_CNT_T;
-
-typedef struct dpp_se_rschd_se_smmu1_wr_rsp_fc_cnt_t
-{
-    ZXIC_UINT32 se_smmu1_wr_rsp_fc_cnt;
-}DPP_SE_RSCHD_SE_SMMU1_WR_RSP_FC_CNT_T;
-
-typedef struct dpp_se_rschd_alg_se_wr_rsp_cnt_t
-{
-    ZXIC_UINT32 alg_se_wr_rsp_cnt;
-}DPP_SE_RSCHD_ALG_SE_WR_RSP_CNT_T;
-
-typedef struct dpp_se_rschd_se_alg_wr_rsp_fc_cnt_t
-{
-    ZXIC_UINT32 se_alg_wr_rsp_fc_cnt;
-}DPP_SE_RSCHD_SE_ALG_WR_RSP_FC_CNT_T;
+typedef struct dpp_se_alg_init_ok_t {
+	ZXIC_UINT32 init_ok;
+} DPP_SE_ALG_INIT_OK_T;
 
+typedef struct dpp_se_alg_cpu_rd_rdy_t {
+	ZXIC_UINT32 cpu_rd_rdy;
+} DPP_SE_ALG_CPU_RD_RDY_T;
+
+typedef struct dpp_se_alg_cpu_rd_data_tmp0_t {
+	ZXIC_UINT32 cpu_rd_data_tmp0;
+} DPP_SE_ALG_CPU_RD_DATA_TMP0_T;
+
+typedef struct dpp_se_alg_cpu_rd_data_tmp1_t {
+	ZXIC_UINT32 cpu_rd_data_tmp1;
+} DPP_SE_ALG_CPU_RD_DATA_TMP1_T;
+
+typedef struct dpp_se_alg_cpu_rd_data_tmp2_t {
+	ZXIC_UINT32 cpu_rd_data_tmp2;
+} DPP_SE_ALG_CPU_RD_DATA_TMP2_T;
+
+typedef struct dpp_se_alg_cpu_rd_data_tmp3_t {
+	ZXIC_UINT32 cpu_rd_data_tmp3;
+} DPP_SE_ALG_CPU_RD_DATA_TMP3_T;
+
+typedef struct dpp_se_alg_cpu_rd_data_tmp4_t {
+	ZXIC_UINT32 cpu_rd_data_tmp4;
+} DPP_SE_ALG_CPU_RD_DATA_TMP4_T;
+
+typedef struct dpp_se_alg_cpu_rd_data_tmp5_t {
+	ZXIC_UINT32 cpu_rd_data_tmp5;
+} DPP_SE_ALG_CPU_RD_DATA_TMP5_T;
+
+typedef struct dpp_se_alg_cpu_rd_data_tmp6_t {
+	ZXIC_UINT32 cpu_rd_data_tmp6;
+} DPP_SE_ALG_CPU_RD_DATA_TMP6_T;
+
+typedef struct dpp_se_alg_cpu_rd_data_tmp7_t {
+	ZXIC_UINT32 cpu_rd_data_tmp7;
+} DPP_SE_ALG_CPU_RD_DATA_TMP7_T;
+
+typedef struct dpp_se_alg_cpu_rd_data_tmp8_t {
+	ZXIC_UINT32 cpu_rd_data_tmp8;
+} DPP_SE_ALG_CPU_RD_DATA_TMP8_T;
+
+typedef struct dpp_se_alg_cpu_rd_data_tmp9_t {
+	ZXIC_UINT32 cpu_rd_data_tmp9;
+} DPP_SE_ALG_CPU_RD_DATA_TMP9_T;
+
+typedef struct dpp_se_alg_cpu_rd_data_tmp10_t {
+	ZXIC_UINT32 cpu_rd_data_tmp10;
+} DPP_SE_ALG_CPU_RD_DATA_TMP10_T;
+
+typedef struct dpp_se_alg_cpu_rd_data_tmp11_t {
+	ZXIC_UINT32 cpu_rd_data_tmp11;
+} DPP_SE_ALG_CPU_RD_DATA_TMP11_T;
+
+typedef struct dpp_se_alg_cpu_rd_data_tmp12_t {
+	ZXIC_UINT32 cpu_rd_data_tmp12;
+} DPP_SE_ALG_CPU_RD_DATA_TMP12_T;
+
+typedef struct dpp_se_alg_cpu_rd_data_tmp13_t {
+	ZXIC_UINT32 cpu_rd_data_tmp13;
+} DPP_SE_ALG_CPU_RD_DATA_TMP13_T;
+
+typedef struct dpp_se_alg_cpu_rd_data_tmp14_t {
+	ZXIC_UINT32 cpu_rd_data_tmp14;
+} DPP_SE_ALG_CPU_RD_DATA_TMP14_T;
+
+typedef struct dpp_se_alg_cpu_rd_data_tmp15_t {
+	ZXIC_UINT32 cpu_rd_data_tmp15;
+} DPP_SE_ALG_CPU_RD_DATA_TMP15_T;
+
+typedef struct dpp_se_alg_lpm_v4_config_rgt_t {
+	ZXIC_UINT32 lpm_v4_shift_sel;
+	ZXIC_UINT32 lpm_v4_sram_cmp_flag;
+	ZXIC_UINT32 lpm_v4_ddr3_addr_sel;
+} DPP_SE_ALG_LPM_V4_CONFIG_RGT_T;
+
+typedef struct dpp_se_alg_lpm_v6_config_rgt_t {
+	ZXIC_UINT32 lpm_v6_shift_sel;
+	ZXIC_UINT32 lpm_v6_sram_cmp_flag;
+	ZXIC_UINT32 lpm_v6_ddr3_addr_sel;
+} DPP_SE_ALG_LPM_V6_CONFIG_RGT_T;
+
+typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u0_pfull_ast_t {
+	ZXIC_UINT32 lpm_ext_rsp_fifo_u0_pfull_ast;
+} DPP_SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_AST_T;
+
+typedef struct dpp_se_as_hash_age_pat_cfg_t {
+	ZXIC_UINT32 hash_age_pat_cfg;
+} DPP_SE_AS_HASH_AGE_PAT_CFG_T;
+
+typedef struct dpp_se_as_learn_rdy_cfg_t {
+	ZXIC_UINT32 learn_rdy_cfg;
+} DPP_SE_AS_LEARN_RDY_CFG_T;
+
+typedef struct dpp_se_kschd_kschd_as_pful_cfg_t {
+	ZXIC_UINT32 kschd_as_pful_cfg;
+} DPP_SE_KSCHD_KSCHD_AS_PFUL_CFG_T;
+
+typedef struct dpp_se_kschd_kschd_dir_pful_cfg_t {
+	ZXIC_UINT32 kschd_dir_pful_cfg;
+} DPP_SE_KSCHD_KSCHD_DIR_PFUL_CFG_T;
+
+typedef struct dpp_se_kschd_kschd_as_ept_cfg_t {
+	ZXIC_UINT32 kschd_as_ept_cfg;
+} DPP_SE_KSCHD_KSCHD_AS_EPT_CFG_T;
+
+typedef struct dpp_se_kschd_cpu_arbi_pful_cfg_t {
+	ZXIC_UINT32 cpu_arbi_pful_cfg;
+} DPP_SE_KSCHD_CPU_ARBI_PFUL_CFG_T;
+
+typedef struct dpp_se_kschd_kschd_pbu_pful_cfg_t {
+	ZXIC_UINT32 kschd_pbu_pful_cfg;
+} DPP_SE_KSCHD_KSCHD_PBU_PFUL_CFG_T;
+
+typedef struct dpp_se_rschd_rschd_dir_pful_cfg_t {
+	ZXIC_UINT32 rschd_dir_pful_cfg;
+} DPP_SE_RSCHD_RSCHD_DIR_PFUL_CFG_T;
+
+typedef struct dpp_se_rschd_rschd_dir_ept_cfg_t {
+	ZXIC_UINT32 rschd_dir_ept_cfg;
+} DPP_SE_RSCHD_RSCHD_DIR_EPT_CFG_T;
+
+typedef struct dpp_se_cfg_ppu_soft_rst_t {
+	ZXIC_UINT32 ppu_soft_rst;
+} DPP_SE_CFG_PPU_SOFT_RST_T;
+
+typedef struct dpp_se_cfg_ept_flag_t {
+	ZXIC_UINT32 ept_flag;
+} DPP_SE_CFG_EPT_FLAG_T;
+
+typedef struct dpp_se_cfg_ddr_key_lk0_3_t {
+	ZXIC_UINT32 ddr_key_lk0_3;
+} DPP_SE_CFG_DDR_KEY_LK0_3_T;
+
+typedef struct dpp_se_cfg_ddr_key_lk0_2_t {
+	ZXIC_UINT32 ddr_key_lk0_2;
+} DPP_SE_CFG_DDR_KEY_LK0_2_T;
+
+typedef struct dpp_se_cfg_ddr_key_lk0_1_t {
+	ZXIC_UINT32 ddr_key_lk0_1;
+} DPP_SE_CFG_DDR_KEY_LK0_1_T;
+
+typedef struct dpp_se_cfg_ddr_key_lk0_0_t {
+	ZXIC_UINT32 ddr_key_lk0_0;
+} DPP_SE_CFG_DDR_KEY_LK0_0_T;
+
+typedef struct dpp_se_cfg_ddr_key_lk1_3_t {
+	ZXIC_UINT32 ddr_key_lk1_3;
+} DPP_SE_CFG_DDR_KEY_LK1_3_T;
+
+typedef struct dpp_se_cfg_ddr_key_lk1_2_t {
+	ZXIC_UINT32 ddr_key_lk1_2;
+} DPP_SE_CFG_DDR_KEY_LK1_2_T;
+
+typedef struct dpp_se_cfg_ddr_key_lk1_1_t {
+	ZXIC_UINT32 ddr_key_lk1_1;
+} DPP_SE_CFG_DDR_KEY_LK1_1_T;
+
+typedef struct dpp_se_cfg_ddr_key_lk1_0_t {
+	ZXIC_UINT32 ddr_key_lk1_0;
+} DPP_SE_CFG_DDR_KEY_LK1_0_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_18_t {
+	ZXIC_UINT32 hash_key_lk0_18;
+} DPP_SE_CFG_HASH_KEY_LK0_18_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_17_t {
+	ZXIC_UINT32 hash_key_lk0_17;
+} DPP_SE_CFG_HASH_KEY_LK0_17_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_16_t {
+	ZXIC_UINT32 hash_key_lk0_16;
+} DPP_SE_CFG_HASH_KEY_LK0_16_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_15_t {
+	ZXIC_UINT32 hash_key_lk0_15;
+} DPP_SE_CFG_HASH_KEY_LK0_15_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_14_t {
+	ZXIC_UINT32 hash_key_lk0_14;
+} DPP_SE_CFG_HASH_KEY_LK0_14_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_13_t {
+	ZXIC_UINT32 hash_key_lk0_13;
+} DPP_SE_CFG_HASH_KEY_LK0_13_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_12_t {
+	ZXIC_UINT32 hash_key_lk0_12;
+} DPP_SE_CFG_HASH_KEY_LK0_12_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_11_t {
+	ZXIC_UINT32 hash_key_lk0_11;
+} DPP_SE_CFG_HASH_KEY_LK0_11_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_10_t {
+	ZXIC_UINT32 hash_key_lk0_10;
+} DPP_SE_CFG_HASH_KEY_LK0_10_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_9_t {
+	ZXIC_UINT32 hash_key_lk0_9;
+} DPP_SE_CFG_HASH_KEY_LK0_9_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_8_t {
+	ZXIC_UINT32 hash_key_lk0_8;
+} DPP_SE_CFG_HASH_KEY_LK0_8_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_7_t {
+	ZXIC_UINT32 hash_key_lk0_7;
+} DPP_SE_CFG_HASH_KEY_LK0_7_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_6_t {
+	ZXIC_UINT32 hash_key_lk0_6;
+} DPP_SE_CFG_HASH_KEY_LK0_6_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_5_t {
+	ZXIC_UINT32 hash_key_lk0_5;
+} DPP_SE_CFG_HASH_KEY_LK0_5_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_4_t {
+	ZXIC_UINT32 hash_key_lk0_4;
+} DPP_SE_CFG_HASH_KEY_LK0_4_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_3_t {
+	ZXIC_UINT32 hash_key_lk0_3;
+} DPP_SE_CFG_HASH_KEY_LK0_3_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_2_t {
+	ZXIC_UINT32 hash_key_lk0_2;
+} DPP_SE_CFG_HASH_KEY_LK0_2_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_1_t {
+	ZXIC_UINT32 hash_key_lk0_1;
+} DPP_SE_CFG_HASH_KEY_LK0_1_T;
+
+typedef struct dpp_se_cfg_hash_key_lk0_0_t {
+	ZXIC_UINT32 hash_key_lk0_0;
+} DPP_SE_CFG_HASH_KEY_LK0_0_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_18_t {
+	ZXIC_UINT32 hash_key_lk1_18;
+} DPP_SE_CFG_HASH_KEY_LK1_18_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_17_t {
+	ZXIC_UINT32 hash_key_lk1_17;
+} DPP_SE_CFG_HASH_KEY_LK1_17_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_16_t {
+	ZXIC_UINT32 hash_key_lk1_16;
+} DPP_SE_CFG_HASH_KEY_LK1_16_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_15_t {
+	ZXIC_UINT32 hash_key_lk1_15;
+} DPP_SE_CFG_HASH_KEY_LK1_15_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_14_t {
+	ZXIC_UINT32 hash_key_lk1_14;
+} DPP_SE_CFG_HASH_KEY_LK1_14_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_13_t {
+	ZXIC_UINT32 hash_key_lk1_13;
+} DPP_SE_CFG_HASH_KEY_LK1_13_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_12_t {
+	ZXIC_UINT32 hash_key_lk1_12;
+} DPP_SE_CFG_HASH_KEY_LK1_12_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_11_t {
+	ZXIC_UINT32 hash_key_lk1_11;
+} DPP_SE_CFG_HASH_KEY_LK1_11_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_10_t {
+	ZXIC_UINT32 hash_key_lk1_10;
+} DPP_SE_CFG_HASH_KEY_LK1_10_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_9_t {
+	ZXIC_UINT32 hash_key_lk1_9;
+} DPP_SE_CFG_HASH_KEY_LK1_9_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_8_t {
+	ZXIC_UINT32 hash_key_lk1_8;
+} DPP_SE_CFG_HASH_KEY_LK1_8_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_7_t {
+	ZXIC_UINT32 hash_key_lk1_7;
+} DPP_SE_CFG_HASH_KEY_LK1_7_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_6_t {
+	ZXIC_UINT32 hash_key_lk1_6;
+} DPP_SE_CFG_HASH_KEY_LK1_6_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_5_t {
+	ZXIC_UINT32 hash_key_lk1_5;
+} DPP_SE_CFG_HASH_KEY_LK1_5_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_4_t {
+	ZXIC_UINT32 hash_key_lk1_4;
+} DPP_SE_CFG_HASH_KEY_LK1_4_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_3_t {
+	ZXIC_UINT32 hash_key_lk1_3;
+} DPP_SE_CFG_HASH_KEY_LK1_3_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_2_t {
+	ZXIC_UINT32 hash_key_lk1_2;
+} DPP_SE_CFG_HASH_KEY_LK1_2_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_1_t {
+	ZXIC_UINT32 hash_key_lk1_1;
+} DPP_SE_CFG_HASH_KEY_LK1_1_T;
+
+typedef struct dpp_se_cfg_hash_key_lk1_0_t {
+	ZXIC_UINT32 hash_key_lk1_0;
+} DPP_SE_CFG_HASH_KEY_LK1_0_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_18_t {
+	ZXIC_UINT32 hash_key_lk2_18;
+} DPP_SE_CFG_HASH_KEY_LK2_18_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_17_t {
+	ZXIC_UINT32 hash_key_lk2_17;
+} DPP_SE_CFG_HASH_KEY_LK2_17_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_16_t {
+	ZXIC_UINT32 hash_key_lk2_16;
+} DPP_SE_CFG_HASH_KEY_LK2_16_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_15_t {
+	ZXIC_UINT32 hash_key_lk2_15;
+} DPP_SE_CFG_HASH_KEY_LK2_15_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_14_t {
+	ZXIC_UINT32 hash_key_lk2_14;
+} DPP_SE_CFG_HASH_KEY_LK2_14_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_13_t {
+	ZXIC_UINT32 hash_key_lk2_13;
+} DPP_SE_CFG_HASH_KEY_LK2_13_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_12_t {
+	ZXIC_UINT32 hash_key_lk2_12;
+} DPP_SE_CFG_HASH_KEY_LK2_12_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_11_t {
+	ZXIC_UINT32 hash_key_lk2_11;
+} DPP_SE_CFG_HASH_KEY_LK2_11_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_10_t {
+	ZXIC_UINT32 hash_key_lk2_10;
+} DPP_SE_CFG_HASH_KEY_LK2_10_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_9_t {
+	ZXIC_UINT32 hash_key_lk2_9;
+} DPP_SE_CFG_HASH_KEY_LK2_9_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_8_t {
+	ZXIC_UINT32 hash_key_lk2_8;
+} DPP_SE_CFG_HASH_KEY_LK2_8_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_7_t {
+	ZXIC_UINT32 hash_key_lk2_7;
+} DPP_SE_CFG_HASH_KEY_LK2_7_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_6_t {
+	ZXIC_UINT32 hash_key_lk2_6;
+} DPP_SE_CFG_HASH_KEY_LK2_6_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_5_t {
+	ZXIC_UINT32 hash_key_lk2_5;
+} DPP_SE_CFG_HASH_KEY_LK2_5_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_4_t {
+	ZXIC_UINT32 hash_key_lk2_4;
+} DPP_SE_CFG_HASH_KEY_LK2_4_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_3_t {
+	ZXIC_UINT32 hash_key_lk2_3;
+} DPP_SE_CFG_HASH_KEY_LK2_3_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_2_t {
+	ZXIC_UINT32 hash_key_lk2_2;
+} DPP_SE_CFG_HASH_KEY_LK2_2_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_1_t {
+	ZXIC_UINT32 hash_key_lk2_1;
+} DPP_SE_CFG_HASH_KEY_LK2_1_T;
+
+typedef struct dpp_se_cfg_hash_key_lk2_0_t {
+	ZXIC_UINT32 hash_key_lk2_0;
+} DPP_SE_CFG_HASH_KEY_LK2_0_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_18_t {
+	ZXIC_UINT32 hash_key_lk3_18;
+} DPP_SE_CFG_HASH_KEY_LK3_18_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_17_t {
+	ZXIC_UINT32 hash_key_lk3_17;
+} DPP_SE_CFG_HASH_KEY_LK3_17_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_16_t {
+	ZXIC_UINT32 hash_key_lk3_16;
+} DPP_SE_CFG_HASH_KEY_LK3_16_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_15_t {
+	ZXIC_UINT32 hash_key_lk3_15;
+} DPP_SE_CFG_HASH_KEY_LK3_15_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_14_t {
+	ZXIC_UINT32 hash_key_lk3_14;
+} DPP_SE_CFG_HASH_KEY_LK3_14_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_13_t {
+	ZXIC_UINT32 hash_key_lk3_13;
+} DPP_SE_CFG_HASH_KEY_LK3_13_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_12_t {
+	ZXIC_UINT32 hash_key_lk3_12;
+} DPP_SE_CFG_HASH_KEY_LK3_12_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_11_t {
+	ZXIC_UINT32 hash_key_lk3_11;
+} DPP_SE_CFG_HASH_KEY_LK3_11_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_10_t {
+	ZXIC_UINT32 hash_key_lk3_10;
+} DPP_SE_CFG_HASH_KEY_LK3_10_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_9_t {
+	ZXIC_UINT32 hash_key_lk3_9;
+} DPP_SE_CFG_HASH_KEY_LK3_9_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_8_t {
+	ZXIC_UINT32 hash_key_lk3_8;
+} DPP_SE_CFG_HASH_KEY_LK3_8_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_7_t {
+	ZXIC_UINT32 hash_key_lk3_7;
+} DPP_SE_CFG_HASH_KEY_LK3_7_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_6_t {
+	ZXIC_UINT32 hash_key_lk3_6;
+} DPP_SE_CFG_HASH_KEY_LK3_6_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_5_t {
+	ZXIC_UINT32 hash_key_lk3_5;
+} DPP_SE_CFG_HASH_KEY_LK3_5_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_4_t {
+	ZXIC_UINT32 hash_key_lk3_4;
+} DPP_SE_CFG_HASH_KEY_LK3_4_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_3_t {
+	ZXIC_UINT32 hash_key_lk3_3;
+} DPP_SE_CFG_HASH_KEY_LK3_3_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_2_t {
+	ZXIC_UINT32 hash_key_lk3_2;
+} DPP_SE_CFG_HASH_KEY_LK3_2_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_1_t {
+	ZXIC_UINT32 hash_key_lk3_1;
+} DPP_SE_CFG_HASH_KEY_LK3_1_T;
+
+typedef struct dpp_se_cfg_hash_key_lk3_0_t {
+	ZXIC_UINT32 hash_key_lk3_0;
+} DPP_SE_CFG_HASH_KEY_LK3_0_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk0_6_t {
+	ZXIC_UINT32 lpm_key_lk0_6;
+} DPP_SE_CFG_LPM_KEY_LK0_6_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk0_5_t {
+	ZXIC_UINT32 lpm_key_lk0_5;
+} DPP_SE_CFG_LPM_KEY_LK0_5_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk0_4_t {
+	ZXIC_UINT32 lpm_key_lk0_4;
+} DPP_SE_CFG_LPM_KEY_LK0_4_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk0_3_t {
+	ZXIC_UINT32 lpm_key_lk0_3;
+} DPP_SE_CFG_LPM_KEY_LK0_3_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk0_2_t {
+	ZXIC_UINT32 lpm_key_lk0_2;
+} DPP_SE_CFG_LPM_KEY_LK0_2_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk0_1_t {
+	ZXIC_UINT32 lpm_key_lk0_1;
+} DPP_SE_CFG_LPM_KEY_LK0_1_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk0_0_t {
+	ZXIC_UINT32 lpm_key_lk0_0;
+} DPP_SE_CFG_LPM_KEY_LK0_0_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk1_6_t {
+	ZXIC_UINT32 lpm_key_lk1_6;
+} DPP_SE_CFG_LPM_KEY_LK1_6_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk1_5_t {
+	ZXIC_UINT32 lpm_key_lk1_5;
+} DPP_SE_CFG_LPM_KEY_LK1_5_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk1_4_t {
+	ZXIC_UINT32 lpm_key_lk1_4;
+} DPP_SE_CFG_LPM_KEY_LK1_4_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk1_3_t {
+	ZXIC_UINT32 lpm_key_lk1_3;
+} DPP_SE_CFG_LPM_KEY_LK1_3_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk1_2_t {
+	ZXIC_UINT32 lpm_key_lk1_2;
+} DPP_SE_CFG_LPM_KEY_LK1_2_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk1_1_t {
+	ZXIC_UINT32 lpm_key_lk1_1;
+} DPP_SE_CFG_LPM_KEY_LK1_1_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk1_0_t {
+	ZXIC_UINT32 lpm_key_lk1_0;
+} DPP_SE_CFG_LPM_KEY_LK1_0_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk2_6_t {
+	ZXIC_UINT32 lpm_key_lk2_6;
+} DPP_SE_CFG_LPM_KEY_LK2_6_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk2_5_t {
+	ZXIC_UINT32 lpm_key_lk2_5;
+} DPP_SE_CFG_LPM_KEY_LK2_5_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk2_4_t {
+	ZXIC_UINT32 lpm_key_lk2_4;
+} DPP_SE_CFG_LPM_KEY_LK2_4_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk2_3_t {
+	ZXIC_UINT32 lpm_key_lk2_3;
+} DPP_SE_CFG_LPM_KEY_LK2_3_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk2_2_t {
+	ZXIC_UINT32 lpm_key_lk2_2;
+} DPP_SE_CFG_LPM_KEY_LK2_2_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk2_1_t {
+	ZXIC_UINT32 lpm_key_lk2_1;
+} DPP_SE_CFG_LPM_KEY_LK2_1_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk2_0_t {
+	ZXIC_UINT32 lpm_key_lk2_0;
+} DPP_SE_CFG_LPM_KEY_LK2_0_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk3_6_t {
+	ZXIC_UINT32 lpm_key_lk3_6;
+} DPP_SE_CFG_LPM_KEY_LK3_6_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk3_5_t {
+	ZXIC_UINT32 lpm_key_lk3_5;
+} DPP_SE_CFG_LPM_KEY_LK3_5_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk3_4_t {
+	ZXIC_UINT32 lpm_key_lk3_4;
+} DPP_SE_CFG_LPM_KEY_LK3_4_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk3_3_t {
+	ZXIC_UINT32 lpm_key_lk3_3;
+} DPP_SE_CFG_LPM_KEY_LK3_3_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk3_2_t {
+	ZXIC_UINT32 lpm_key_lk3_2;
+} DPP_SE_CFG_LPM_KEY_LK3_2_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk3_1_t {
+	ZXIC_UINT32 lpm_key_lk3_1;
+} DPP_SE_CFG_LPM_KEY_LK3_1_T;
+
+typedef struct dpp_se_cfg_lpm_key_lk3_0_t {
+	ZXIC_UINT32 lpm_key_lk3_0;
+} DPP_SE_CFG_LPM_KEY_LK3_0_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_22_t {
+	ZXIC_UINT32 etcam_key_lk0_22;
+} DPP_SE_CFG_ETCAM_KEY_LK0_22_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_21_t {
+	ZXIC_UINT32 etcam_key_lk0_21;
+} DPP_SE_CFG_ETCAM_KEY_LK0_21_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_20_t {
+	ZXIC_UINT32 etcam_key_lk0_20;
+} DPP_SE_CFG_ETCAM_KEY_LK0_20_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_19_t {
+	ZXIC_UINT32 etcam_key_lk0_19;
+} DPP_SE_CFG_ETCAM_KEY_LK0_19_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_18_t {
+	ZXIC_UINT32 etcam_key_lk0_18;
+} DPP_SE_CFG_ETCAM_KEY_LK0_18_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_17_t {
+	ZXIC_UINT32 etcam_key_lk0_17;
+} DPP_SE_CFG_ETCAM_KEY_LK0_17_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_16_t {
+	ZXIC_UINT32 etcam_key_lk0_16;
+} DPP_SE_CFG_ETCAM_KEY_LK0_16_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_15_t {
+	ZXIC_UINT32 etcam_key_lk0_15;
+} DPP_SE_CFG_ETCAM_KEY_LK0_15_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_14_t {
+	ZXIC_UINT32 etcam_key_lk0_14;
+} DPP_SE_CFG_ETCAM_KEY_LK0_14_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_13_t {
+	ZXIC_UINT32 etcam_key_lk0_13;
+} DPP_SE_CFG_ETCAM_KEY_LK0_13_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_12_t {
+	ZXIC_UINT32 etcam_key_lk0_12;
+} DPP_SE_CFG_ETCAM_KEY_LK0_12_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_11_t {
+	ZXIC_UINT32 etcam_key_lk0_11;
+} DPP_SE_CFG_ETCAM_KEY_LK0_11_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_10_t {
+	ZXIC_UINT32 etcam_key_lk0_10;
+} DPP_SE_CFG_ETCAM_KEY_LK0_10_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_9_t {
+	ZXIC_UINT32 etcam_key_lk0_9;
+} DPP_SE_CFG_ETCAM_KEY_LK0_9_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_8_t {
+	ZXIC_UINT32 etcam_key_lk0_8;
+} DPP_SE_CFG_ETCAM_KEY_LK0_8_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_7_t {
+	ZXIC_UINT32 etcam_key_lk0_7;
+} DPP_SE_CFG_ETCAM_KEY_LK0_7_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_6_t {
+	ZXIC_UINT32 etcam_key_lk0_6;
+} DPP_SE_CFG_ETCAM_KEY_LK0_6_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_5_t {
+	ZXIC_UINT32 etcam_key_lk0_5;
+} DPP_SE_CFG_ETCAM_KEY_LK0_5_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_4_t {
+	ZXIC_UINT32 etcam_key_lk0_4;
+} DPP_SE_CFG_ETCAM_KEY_LK0_4_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_3_t {
+	ZXIC_UINT32 etcam_key_lk0_3;
+} DPP_SE_CFG_ETCAM_KEY_LK0_3_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_2_t {
+	ZXIC_UINT32 etcam_key_lk0_2;
+} DPP_SE_CFG_ETCAM_KEY_LK0_2_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_1_t {
+	ZXIC_UINT32 etcam_key_lk0_1;
+} DPP_SE_CFG_ETCAM_KEY_LK0_1_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk0_0_t {
+	ZXIC_UINT32 etcam_key_lk0_0;
+} DPP_SE_CFG_ETCAM_KEY_LK0_0_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_22_t {
+	ZXIC_UINT32 etcam_key_lk1_22;
+} DPP_SE_CFG_ETCAM_KEY_LK1_22_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_21_t {
+	ZXIC_UINT32 etcam_key_lk1_21;
+} DPP_SE_CFG_ETCAM_KEY_LK1_21_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_20_t {
+	ZXIC_UINT32 etcam_key_lk1_20;
+} DPP_SE_CFG_ETCAM_KEY_LK1_20_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_19_t {
+	ZXIC_UINT32 etcam_key_lk1_19;
+} DPP_SE_CFG_ETCAM_KEY_LK1_19_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_18_t {
+	ZXIC_UINT32 etcam_key_lk1_18;
+} DPP_SE_CFG_ETCAM_KEY_LK1_18_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_17_t {
+	ZXIC_UINT32 etcam_key_lk1_17;
+} DPP_SE_CFG_ETCAM_KEY_LK1_17_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_16_t {
+	ZXIC_UINT32 etcam_key_lk1_16;
+} DPP_SE_CFG_ETCAM_KEY_LK1_16_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_15_t {
+	ZXIC_UINT32 etcam_key_lk1_15;
+} DPP_SE_CFG_ETCAM_KEY_LK1_15_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_14_t {
+	ZXIC_UINT32 etcam_key_lk1_14;
+} DPP_SE_CFG_ETCAM_KEY_LK1_14_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_13_t {
+	ZXIC_UINT32 etcam_key_lk1_13;
+} DPP_SE_CFG_ETCAM_KEY_LK1_13_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_12_t {
+	ZXIC_UINT32 etcam_key_lk1_12;
+} DPP_SE_CFG_ETCAM_KEY_LK1_12_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_11_t {
+	ZXIC_UINT32 etcam_key_lk1_11;
+} DPP_SE_CFG_ETCAM_KEY_LK1_11_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_10_t {
+	ZXIC_UINT32 etcam_key_lk1_10;
+} DPP_SE_CFG_ETCAM_KEY_LK1_10_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_9_t {
+	ZXIC_UINT32 etcam_key_lk1_9;
+} DPP_SE_CFG_ETCAM_KEY_LK1_9_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_8_t {
+	ZXIC_UINT32 etcam_key_lk1_8;
+} DPP_SE_CFG_ETCAM_KEY_LK1_8_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_7_t {
+	ZXIC_UINT32 etcam_key_lk1_7;
+} DPP_SE_CFG_ETCAM_KEY_LK1_7_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_6_t {
+	ZXIC_UINT32 etcam_key_lk1_6;
+} DPP_SE_CFG_ETCAM_KEY_LK1_6_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_5_t {
+	ZXIC_UINT32 etcam_key_lk1_5;
+} DPP_SE_CFG_ETCAM_KEY_LK1_5_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_4_t {
+	ZXIC_UINT32 etcam_key_lk1_4;
+} DPP_SE_CFG_ETCAM_KEY_LK1_4_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_3_t {
+	ZXIC_UINT32 etcam_key_lk1_3;
+} DPP_SE_CFG_ETCAM_KEY_LK1_3_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_2_t {
+	ZXIC_UINT32 etcam_key_lk1_2;
+} DPP_SE_CFG_ETCAM_KEY_LK1_2_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_1_t {
+	ZXIC_UINT32 etcam_key_lk1_1;
+} DPP_SE_CFG_ETCAM_KEY_LK1_1_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk1_0_t {
+	ZXIC_UINT32 etcam_key_lk1_0;
+} DPP_SE_CFG_ETCAM_KEY_LK1_0_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_22_t {
+	ZXIC_UINT32 etcam_key_lk2_22;
+} DPP_SE_CFG_ETCAM_KEY_LK2_22_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_21_t {
+	ZXIC_UINT32 etcam_key_lk2_21;
+} DPP_SE_CFG_ETCAM_KEY_LK2_21_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_20_t {
+	ZXIC_UINT32 etcam_key_lk2_20;
+} DPP_SE_CFG_ETCAM_KEY_LK2_20_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_19_t {
+	ZXIC_UINT32 etcam_key_lk2_19;
+} DPP_SE_CFG_ETCAM_KEY_LK2_19_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_18_t {
+	ZXIC_UINT32 etcam_key_lk2_18;
+} DPP_SE_CFG_ETCAM_KEY_LK2_18_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_17_t {
+	ZXIC_UINT32 etcam_key_lk2_17;
+} DPP_SE_CFG_ETCAM_KEY_LK2_17_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_16_t {
+	ZXIC_UINT32 etcam_key_lk2_16;
+} DPP_SE_CFG_ETCAM_KEY_LK2_16_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_15_t {
+	ZXIC_UINT32 etcam_key_lk2_15;
+} DPP_SE_CFG_ETCAM_KEY_LK2_15_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_14_t {
+	ZXIC_UINT32 etcam_key_lk2_14;
+} DPP_SE_CFG_ETCAM_KEY_LK2_14_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_13_t {
+	ZXIC_UINT32 etcam_key_lk2_13;
+} DPP_SE_CFG_ETCAM_KEY_LK2_13_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_12_t {
+	ZXIC_UINT32 etcam_key_lk2_12;
+} DPP_SE_CFG_ETCAM_KEY_LK2_12_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_11_t {
+	ZXIC_UINT32 etcam_key_lk2_11;
+} DPP_SE_CFG_ETCAM_KEY_LK2_11_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_10_t {
+	ZXIC_UINT32 etcam_key_lk2_10;
+} DPP_SE_CFG_ETCAM_KEY_LK2_10_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_9_t {
+	ZXIC_UINT32 etcam_key_lk2_9;
+} DPP_SE_CFG_ETCAM_KEY_LK2_9_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_8_t {
+	ZXIC_UINT32 etcam_key_lk2_8;
+} DPP_SE_CFG_ETCAM_KEY_LK2_8_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_7_t {
+	ZXIC_UINT32 etcam_key_lk2_7;
+} DPP_SE_CFG_ETCAM_KEY_LK2_7_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_6_t {
+	ZXIC_UINT32 etcam_key_lk2_6;
+} DPP_SE_CFG_ETCAM_KEY_LK2_6_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_5_t {
+	ZXIC_UINT32 etcam_key_lk2_5;
+} DPP_SE_CFG_ETCAM_KEY_LK2_5_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_4_t {
+	ZXIC_UINT32 etcam_key_lk2_4;
+} DPP_SE_CFG_ETCAM_KEY_LK2_4_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_3_t {
+	ZXIC_UINT32 etcam_key_lk2_3;
+} DPP_SE_CFG_ETCAM_KEY_LK2_3_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_2_t {
+	ZXIC_UINT32 etcam_key_lk2_2;
+} DPP_SE_CFG_ETCAM_KEY_LK2_2_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_1_t {
+	ZXIC_UINT32 etcam_key_lk2_1;
+} DPP_SE_CFG_ETCAM_KEY_LK2_1_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk2_0_t {
+	ZXIC_UINT32 etcam_key_lk2_0;
+} DPP_SE_CFG_ETCAM_KEY_LK2_0_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_22_t {
+	ZXIC_UINT32 etcam_key_lk3_22;
+} DPP_SE_CFG_ETCAM_KEY_LK3_22_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_21_t {
+	ZXIC_UINT32 etcam_key_lk3_21;
+} DPP_SE_CFG_ETCAM_KEY_LK3_21_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_20_t {
+	ZXIC_UINT32 etcam_key_lk3_20;
+} DPP_SE_CFG_ETCAM_KEY_LK3_20_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_19_t {
+	ZXIC_UINT32 etcam_key_lk3_19;
+} DPP_SE_CFG_ETCAM_KEY_LK3_19_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_18_t {
+	ZXIC_UINT32 etcam_key_lk3_18;
+} DPP_SE_CFG_ETCAM_KEY_LK3_18_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_17_t {
+	ZXIC_UINT32 etcam_key_lk3_17;
+} DPP_SE_CFG_ETCAM_KEY_LK3_17_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_16_t {
+	ZXIC_UINT32 etcam_key_lk3_16;
+} DPP_SE_CFG_ETCAM_KEY_LK3_16_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_15_t {
+	ZXIC_UINT32 etcam_key_lk3_15;
+} DPP_SE_CFG_ETCAM_KEY_LK3_15_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_14_t {
+	ZXIC_UINT32 etcam_key_lk3_14;
+} DPP_SE_CFG_ETCAM_KEY_LK3_14_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_13_t {
+	ZXIC_UINT32 etcam_key_lk3_13;
+} DPP_SE_CFG_ETCAM_KEY_LK3_13_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_12_t {
+	ZXIC_UINT32 etcam_key_lk3_12;
+} DPP_SE_CFG_ETCAM_KEY_LK3_12_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_11_t {
+	ZXIC_UINT32 etcam_key_lk3_11;
+} DPP_SE_CFG_ETCAM_KEY_LK3_11_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_10_t {
+	ZXIC_UINT32 etcam_key_lk3_10;
+} DPP_SE_CFG_ETCAM_KEY_LK3_10_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_9_t {
+	ZXIC_UINT32 etcam_key_lk3_9;
+} DPP_SE_CFG_ETCAM_KEY_LK3_9_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_8_t {
+	ZXIC_UINT32 etcam_key_lk3_8;
+} DPP_SE_CFG_ETCAM_KEY_LK3_8_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_7_t {
+	ZXIC_UINT32 etcam_key_lk3_7;
+} DPP_SE_CFG_ETCAM_KEY_LK3_7_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_6_t {
+	ZXIC_UINT32 etcam_key_lk3_6;
+} DPP_SE_CFG_ETCAM_KEY_LK3_6_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_5_t {
+	ZXIC_UINT32 etcam_key_lk3_5;
+} DPP_SE_CFG_ETCAM_KEY_LK3_5_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_4_t {
+	ZXIC_UINT32 etcam_key_lk3_4;
+} DPP_SE_CFG_ETCAM_KEY_LK3_4_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_3_t {
+	ZXIC_UINT32 etcam_key_lk3_3;
+} DPP_SE_CFG_ETCAM_KEY_LK3_3_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_2_t {
+	ZXIC_UINT32 etcam_key_lk3_2;
+} DPP_SE_CFG_ETCAM_KEY_LK3_2_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_1_t {
+	ZXIC_UINT32 etcam_key_lk3_1;
+} DPP_SE_CFG_ETCAM_KEY_LK3_1_T;
+
+typedef struct dpp_se_cfg_etcam_key_lk3_0_t {
+	ZXIC_UINT32 etcam_key_lk3_0;
+} DPP_SE_CFG_ETCAM_KEY_LK3_0_T;
+
+typedef struct dpp_se_cfg_pbu_key_lk0_3_t {
+	ZXIC_UINT32 pbu_key_lk0_3;
+} DPP_SE_CFG_PBU_KEY_LK0_3_T;
+
+typedef struct dpp_se_cfg_pbu_key_lk0_2_t {
+	ZXIC_UINT32 pbu_key_lk0_2;
+} DPP_SE_CFG_PBU_KEY_LK0_2_T;
+
+typedef struct dpp_se_cfg_pbu_key_lk0_1_t {
+	ZXIC_UINT32 pbu_key_lk0_1;
+} DPP_SE_CFG_PBU_KEY_LK0_1_T;
+
+typedef struct dpp_se_cfg_pbu_key_lk0_0_t {
+	ZXIC_UINT32 pbu_key_lk0_0;
+} DPP_SE_CFG_PBU_KEY_LK0_0_T;
+
+typedef struct dpp_se_cfg_pbu_key_lk1_3_t {
+	ZXIC_UINT32 pbu_key_lk1_3;
+} DPP_SE_CFG_PBU_KEY_LK1_3_T;
+
+typedef struct dpp_se_cfg_pbu_key_lk1_2_t {
+	ZXIC_UINT32 pbu_key_lk1_2;
+} DPP_SE_CFG_PBU_KEY_LK1_2_T;
+
+typedef struct dpp_se_cfg_pbu_key_lk1_1_t {
+	ZXIC_UINT32 pbu_key_lk1_1;
+} DPP_SE_CFG_PBU_KEY_LK1_1_T;
+
+typedef struct dpp_se_cfg_pbu_key_lk1_0_t {
+	ZXIC_UINT32 pbu_key_lk1_0;
+} DPP_SE_CFG_PBU_KEY_LK1_0_T;
+
+typedef struct dpp_se_cfg_pbu_key_lk2_3_t {
+	ZXIC_UINT32 pbu_key_lk2_3;
+} DPP_SE_CFG_PBU_KEY_LK2_3_T;
+
+typedef struct dpp_se_cfg_pbu_key_lk2_2_t {
+	ZXIC_UINT32 pbu_key_lk2_2;
+} DPP_SE_CFG_PBU_KEY_LK2_2_T;
+
+typedef struct dpp_se_cfg_pbu_key_lk2_1_t {
+	ZXIC_UINT32 pbu_key_lk2_1;
+} DPP_SE_CFG_PBU_KEY_LK2_1_T;
+
+typedef struct dpp_se_cfg_pbu_key_lk2_0_t {
+	ZXIC_UINT32 pbu_key_lk2_0;
+} DPP_SE_CFG_PBU_KEY_LK2_0_T;
+
+typedef struct dpp_se_cfg_pbu_key_lk3_3_t {
+	ZXIC_UINT32 pbu_key_lk3_3;
+} DPP_SE_CFG_PBU_KEY_LK3_3_T;
+
+typedef struct dpp_se_cfg_pbu_key_lk3_2_t {
+	ZXIC_UINT32 pbu_key_lk3_2;
+} DPP_SE_CFG_PBU_KEY_LK3_2_T;
+
+typedef struct dpp_se_cfg_pbu_key_lk3_1_t {
+	ZXIC_UINT32 pbu_key_lk3_1;
+} DPP_SE_CFG_PBU_KEY_LK3_1_T;
+
+typedef struct dpp_se_cfg_pbu_key_lk3_0_t {
+	ZXIC_UINT32 pbu_key_lk3_0;
+} DPP_SE_CFG_PBU_KEY_LK3_0_T;
+
+typedef struct dpp_se_alg_schd_learn_fifo_pfull_ast_t {
+	ZXIC_UINT32 schd_learn_fifo_pfull_ast;
+} DPP_SE_ALG_SCHD_LEARN_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_schd_learn_fifo_pfull_neg_t {
+	ZXIC_UINT32 schd_learn_fifo_pfull_neg;
+} DPP_SE_ALG_SCHD_LEARN_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_schd_hash0_fifo_pfull_ast_t {
+	ZXIC_UINT32 schd_hash0_fifo_pfull_ast;
+} DPP_SE_ALG_SCHD_HASH0_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_schd_hash0_fifo_pfull_neg_t {
+	ZXIC_UINT32 schd_hash0_fifo_pfull_neg;
+} DPP_SE_ALG_SCHD_HASH0_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_schd_hash1_fifo_pfull_ast_t {
+	ZXIC_UINT32 schd_hash1_fifo_pfull_ast;
+} DPP_SE_ALG_SCHD_HASH1_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_schd_hash1_fifo_pfull_neg_t {
+	ZXIC_UINT32 schd_hash1_fifo_pfull_neg;
+} DPP_SE_ALG_SCHD_HASH1_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_schd_hash2_fifo_pfull_ast_t {
+	ZXIC_UINT32 schd_hash2_fifo_pfull_ast;
+} DPP_SE_ALG_SCHD_HASH2_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_schd_hash2_fifo_pfull_neg_t {
+	ZXIC_UINT32 schd_hash2_fifo_pfull_neg;
+} DPP_SE_ALG_SCHD_HASH2_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_schd_hash3_fifo_pfull_ast_t {
+	ZXIC_UINT32 schd_hash3_fifo_pfull_ast;
+} DPP_SE_ALG_SCHD_HASH3_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_schd_hash3_fifo_pfull_neg_t {
+	ZXIC_UINT32 schd_hash3_fifo_pfull_neg;
+} DPP_SE_ALG_SCHD_HASH3_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_schd_lpm_fifo_pfull_ast_t {
+	ZXIC_UINT32 schd_lpm_fifo_pfull_ast;
+} DPP_SE_ALG_SCHD_LPM_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_schd_lpm_fifo_pfull_neg_t {
+	ZXIC_UINT32 schd_lpm_fifo_pfull_neg;
+} DPP_SE_ALG_SCHD_LPM_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_hash0_key_fifo_pfull_ast_t {
+	ZXIC_UINT32 hash0_key_fifo_pfull_ast;
+} DPP_SE_ALG_HASH0_KEY_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_hash0_key_fifo_pfull_neg_t {
+	ZXIC_UINT32 hash0_key_fifo_pfull_ast;
+} DPP_SE_ALG_HASH0_KEY_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_hash0_sreq_fifo_pfull_ast_t {
+	ZXIC_UINT32 hash0_sreq_fifo_pfull_ast;
+} DPP_SE_ALG_HASH0_SREQ_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_hash0_sreq_fifo_pfull_neg_t {
+	ZXIC_UINT32 hash0_sreq_fifo_pfull_neg;
+} DPP_SE_ALG_HASH0_SREQ_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_hash0_int_rsp_fifo_pfull_ast_t {
+	ZXIC_UINT32 hash0_int_rsp_fifo_pfull_ast;
+} DPP_SE_ALG_HASH0_INT_RSP_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_hash0_int_rsp_fifo_pfull_neg_t {
+	ZXIC_UINT32 hash0_int_rsp_fifo_pfull_neg;
+} DPP_SE_ALG_HASH0_INT_RSP_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_hash0_ext_rsp_fifo_pfull_ast_t {
+	ZXIC_UINT32 hash0_ext_rsp_fifo_pfull_ast;
+} DPP_SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_hash0_ext_rsp_fifo_pfull_neg_t {
+	ZXIC_UINT32 hash0_ext_rsp_fifo_pfull_neg;
+} DPP_SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_hash1_key_fifo_pfull_ast_t {
+	ZXIC_UINT32 hash1_key_fifo_pfull_ast;
+} DPP_SE_ALG_HASH1_KEY_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_hash1_key_fifo_pfull_neg_t {
+	ZXIC_UINT32 hash1_key_fifo_pfull_ast;
+} DPP_SE_ALG_HASH1_KEY_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_hash1_sreq_fifo_pfull_ast_t {
+	ZXIC_UINT32 hash1_sreq_fifo_pfull_ast;
+} DPP_SE_ALG_HASH1_SREQ_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_hash1_sreq_fifo_pfull_neg_t {
+	ZXIC_UINT32 hash1_sreq_fifo_pfull_neg;
+} DPP_SE_ALG_HASH1_SREQ_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_hash1_int_rsp_fifo_pfull_ast_t {
+	ZXIC_UINT32 hash1_int_rsp_fifo_pfull_ast;
+} DPP_SE_ALG_HASH1_INT_RSP_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_hash1_int_rsp_fifo_pfull_neg_t {
+	ZXIC_UINT32 hash1_int_rsp_fifo_pfull_neg;
+} DPP_SE_ALG_HASH1_INT_RSP_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_hash1_ext_rsp_fifo_pfull_ast_t {
+	ZXIC_UINT32 hash1_ext_rsp_fifo_pfull_ast;
+} DPP_SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_hash1_ext_rsp_fifo_pfull_neg_t {
+	ZXIC_UINT32 hash1_ext_rsp_fifo_pfull_neg;
+} DPP_SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_hash2_key_fifo_pfull_ast_t {
+	ZXIC_UINT32 hash2_key_fifo_pfull_ast;
+} DPP_SE_ALG_HASH2_KEY_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_hash2_key_fifo_pfull_neg_t {
+	ZXIC_UINT32 hash2_key_fifo_pfull_ast;
+} DPP_SE_ALG_HASH2_KEY_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_hash2_sreq_fifo_pfull_ast_t {
+	ZXIC_UINT32 hash2_sreq_fifo_pfull_ast;
+} DPP_SE_ALG_HASH2_SREQ_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_hash2_sreq_fifo_pfull_neg_t {
+	ZXIC_UINT32 hash2_sreq_fifo_pfull_neg;
+} DPP_SE_ALG_HASH2_SREQ_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_hash2_int_rsp_fifo_pfull_ast_t {
+	ZXIC_UINT32 hash2_int_rsp_fifo_pfull_ast;
+} DPP_SE_ALG_HASH2_INT_RSP_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_hash2_int_rsp_fifo_pfull_neg_t {
+	ZXIC_UINT32 hash2_int_rsp_fifo_pfull_neg;
+} DPP_SE_ALG_HASH2_INT_RSP_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_hash2_ext_rsp_fifo_pfull_ast_t {
+	ZXIC_UINT32 hash2_ext_rsp_fifo_pfull_ast;
+} DPP_SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_hash2_ext_rsp_fifo_pfull_neg_t {
+	ZXIC_UINT32 hash2_ext_rsp_fifo_pfull_neg;
+} DPP_SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_hash3_key_fifo_pfull_ast_t {
+	ZXIC_UINT32 hash3_key_fifo_pfull_ast;
+} DPP_SE_ALG_HASH3_KEY_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_hash3_key_fifo_pfull_neg_t {
+	ZXIC_UINT32 hash3_key_fifo_pfull_ast;
+} DPP_SE_ALG_HASH3_KEY_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_hash3_sreq_fifo_pfull_ast_t {
+	ZXIC_UINT32 hash3_sreq_fifo_pfull_ast;
+} DPP_SE_ALG_HASH3_SREQ_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_hash3_sreq_fifo_pfull_neg_t {
+	ZXIC_UINT32 hash3_sreq_fifo_pfull_neg;
+} DPP_SE_ALG_HASH3_SREQ_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_hash3_int_rsp_fifo_pfull_ast_t {
+	ZXIC_UINT32 hash3_int_rsp_fifo_pfull_ast;
+} DPP_SE_ALG_HASH3_INT_RSP_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_hash3_int_rsp_fifo_pfull_neg_t {
+	ZXIC_UINT32 hash3_int_rsp_fifo_pfull_neg;
+} DPP_SE_ALG_HASH3_INT_RSP_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_hash3_ext_rsp_fifo_pfull_ast_t {
+	ZXIC_UINT32 hash3_ext_rsp_fifo_pfull_ast;
+} DPP_SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_AST_T;
+
+typedef struct dpp_se_alg_hash3_ext_rsp_fifo_pfull_neg_t {
+	ZXIC_UINT32 hash3_ext_rsp_fifo_pfull_neg;
+} DPP_SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_lpm_as_info_t {
+	ZXIC_UINT32 lpm_as_type;
+	ZXIC_UINT32 lpm_as_en;
+} DPP_SE_ALG_LPM_AS_INFO_T;
+
+typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u0_pfull_neg_t {
+	ZXIC_UINT32 lpm_ext_rsp_fifo_u0_pfull_neg;
+} DPP_SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u2_pfull_ast_t {
+	ZXIC_UINT32 lpm_ext_rsp_fifo_u2_pfull_ast;
+} DPP_SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_AST_T;
+
+typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u2_pfull_neg_t {
+	ZXIC_UINT32 lpm_ext_rsp_fifo_u2_pfull_neg;
+} DPP_SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u3_pfull_ast_t {
+	ZXIC_UINT32 lpm_ext_rsp_fifo_u3_pfull_ast;
+} DPP_SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_AST_T;
+
+typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u3_pfull_neg_t {
+	ZXIC_UINT32 lpm_ext_rsp_fifo_u3_pfull_neg;
+} DPP_SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u4_pfull_ast_t {
+	ZXIC_UINT32 lpm_ext_rsp_fifo_u4_pfull_ast;
+} DPP_SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_AST_T;
+
+typedef struct dpp_se_alg_lpm_ext_rsp_fifo_u4_pfull_neg_t {
+	ZXIC_UINT32 lpm_ext_rsp_fifo_u4_pfull_neg;
+} DPP_SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_lpm_as_rsp_fifo_u0_pfull_ast_t {
+	ZXIC_UINT32 lpm_as_rsp_fifo_u0_pfull_ast;
+} DPP_SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_AST_T;
+
+typedef struct dpp_se_alg_lpm_as_rsp_fifo_u0_pfull_neg_t {
+	ZXIC_UINT32 lpm_as_rsp_fifo_u0_pfull_neg;
+} DPP_SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_lpm_as_rsp_fifo_u1_pfull_ast_t {
+	ZXIC_UINT32 lpm_as_rsp_fifo_u1_pfull_ast;
+} DPP_SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_AST_T;
+
+typedef struct dpp_se_alg_lpm_as_rsp_fifo_u1_pfull_neg_t {
+	ZXIC_UINT32 lpm_as_rsp_fifo_u1_pfull_neg;
+} DPP_SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_NEG_T;
+
+typedef struct dpp_se_alg_lpm_v4_ddr3_base_addr_t {
+	ZXIC_UINT32 lpm_v4_ddr3_base_addr;
+} DPP_SE_ALG_LPM_V4_DDR3_BASE_ADDR_T;
+
+typedef struct dpp_se_alg_lpm_v6_ddr3_base_addr_t {
+	ZXIC_UINT32 lpm_v6_ddr3_base_addr;
+} DPP_SE_ALG_LPM_V6_DDR3_BASE_ADDR_T;
+
+typedef struct dpp_se_alg_debug_cnt_mode_t {
+	ZXIC_UINT32 cnt_rd_mode;
+	ZXIC_UINT32 cnt_overflow_mode;
+} DPP_SE_ALG_DEBUG_CNT_MODE_T;
+
+typedef struct dpp_se_alg_hash_p0_key_vld_cnt_t {
+	ZXIC_UINT32 hash_p0_key_vld_cnt;
+} DPP_SE_ALG_HASH_P0_KEY_VLD_CNT_T;
+
+typedef struct dpp_se_alg_hash_p1_key_vld_cnt_t {
+	ZXIC_UINT32 hash_p1_key_vld_cnt;
+} DPP_SE_ALG_HASH_P1_KEY_VLD_CNT_T;
+
+typedef struct dpp_se_alg_hash_p2_key_vld_cnt_t {
+	ZXIC_UINT32 hash_p2_key_vld_cnt;
+} DPP_SE_ALG_HASH_P2_KEY_VLD_CNT_T;
+
+typedef struct dpp_se_alg_hash_p3_key_vld_cnt_t {
+	ZXIC_UINT32 hash_p3_key_vld_cnt;
+} DPP_SE_ALG_HASH_P3_KEY_VLD_CNT_T;
+
+typedef struct dpp_se_alg_lpm_p0_key_vld_cnt_t {
+	ZXIC_UINT32 lpm_p0_key_vld_cnt;
+} DPP_SE_ALG_LPM_P0_KEY_VLD_CNT_T;
+
+typedef struct dpp_se_alg_hash_p0_rsp_vld_cnt_t {
+	ZXIC_UINT32 hash_p0_rsp_vld_cnt;
+} DPP_SE_ALG_HASH_P0_RSP_VLD_CNT_T;
+
+typedef struct dpp_se_alg_hash_p1_rsp_vld_cnt_t {
+	ZXIC_UINT32 hash_p1_rsp_vld_cnt;
+} DPP_SE_ALG_HASH_P1_RSP_VLD_CNT_T;
+
+typedef struct dpp_se_alg_hash_p2_rsp_vld_cnt_t {
+	ZXIC_UINT32 hash_p2_rsp_vld_cnt;
+} DPP_SE_ALG_HASH_P2_RSP_VLD_CNT_T;
+
+typedef struct dpp_se_alg_hash_p3_rsp_vld_cnt_t {
+	ZXIC_UINT32 hash_p3_rsp_vld_cnt;
+} DPP_SE_ALG_HASH_P3_RSP_VLD_CNT_T;
+
+typedef struct dpp_se_alg_lpm_p0_rsp_vld_cnt_t {
+	ZXIC_UINT32 lpm_p0_rsp_vld_cnt;
+} DPP_SE_ALG_LPM_P0_RSP_VLD_CNT_T;
+
+typedef struct dpp_se_alg_hash_p0_smf_cnt_t {
+	ZXIC_UINT32 hash_p0_smf_cnt;
+} DPP_SE_ALG_HASH_P0_SMF_CNT_T;
+
+typedef struct dpp_se_alg_hash_p1_smf_cnt_t {
+	ZXIC_UINT32 hash_p1_smf_cnt;
+} DPP_SE_ALG_HASH_P1_SMF_CNT_T;
+
+typedef struct dpp_se_alg_hash_p2_smf_cnt_t {
+	ZXIC_UINT32 hash_p2_smf_cnt;
+} DPP_SE_ALG_HASH_P2_SMF_CNT_T;
+
+typedef struct dpp_se_alg_hash_p3_smf_cnt_t {
+	ZXIC_UINT32 hash_p3_smf_cnt;
+} DPP_SE_ALG_HASH_P3_SMF_CNT_T;
+
+typedef struct dpp_se_alg_lpm_p0_smf_cnt_t {
+	ZXIC_UINT32 lpm_p0_smf_cnt;
+} DPP_SE_ALG_LPM_P0_SMF_CNT_T;
+
+typedef struct dpp_se_alg_hash_p0_spacevld_cnt_t {
+	ZXIC_UINT32 hash_p0_spacevld_cnt;
+} DPP_SE_ALG_HASH_P0_SPACEVLD_CNT_T;
+
+typedef struct dpp_se_alg_hash_p1_spacevld_cnt_t {
+	ZXIC_UINT32 hash_p1_spacevld_cnt;
+} DPP_SE_ALG_HASH_P1_SPACEVLD_CNT_T;
+
+typedef struct dpp_se_alg_hash_p2_spacevld_cnt_t {
+	ZXIC_UINT32 hash_p2_spacevld_cnt;
+} DPP_SE_ALG_HASH_P2_SPACEVLD_CNT_T;
+
+typedef struct dpp_se_alg_hash_p3_spacevld_cnt_t {
+	ZXIC_UINT32 hash_p3_spacevld_cnt;
+} DPP_SE_ALG_HASH_P3_SPACEVLD_CNT_T;
+
+typedef struct dpp_se_alg_smmu1_p0_req_vld_cnt_t {
+	ZXIC_UINT32 smmu1_p0_req_vld_cnt;
+} DPP_SE_ALG_SMMU1_P0_REQ_VLD_CNT_T;
+
+typedef struct dpp_se_alg_smmu1_p1_req_vld_cnt_t {
+	ZXIC_UINT32 smmu1_p1_req_vld_cnt;
+} DPP_SE_ALG_SMMU1_P1_REQ_VLD_CNT_T;
+
+typedef struct dpp_se_alg_smmu1_p2_req_vld_cnt_t {
+	ZXIC_UINT32 smmu1_p2_req_vld_cnt;
+} DPP_SE_ALG_SMMU1_P2_REQ_VLD_CNT_T;
+
+typedef struct dpp_se_alg_smmu1_p3_req_vld_cnt_t {
+	ZXIC_UINT32 smmu1_p3_req_vld_cnt;
+} DPP_SE_ALG_SMMU1_P3_REQ_VLD_CNT_T;
+
+typedef struct dpp_se_alg_smmu1_p4_req_vld_cnt_t {
+	ZXIC_UINT32 smmu1_p4_req_vld_cnt;
+} DPP_SE_ALG_SMMU1_P4_REQ_VLD_CNT_T;
+
+typedef struct dpp_se_alg_smmu1_p5_req_vld_cnt_t {
+	ZXIC_UINT32 smmu1_p5_req_vld_cnt;
+} DPP_SE_ALG_SMMU1_P5_REQ_VLD_CNT_T;
+
+typedef struct dpp_se_alg_smmu1_p0_rsp_vld_cnt_t {
+	ZXIC_UINT32 smmu1_p0_rsp_vld_cnt;
+} DPP_SE_ALG_SMMU1_P0_RSP_VLD_CNT_T;
+
+typedef struct dpp_se_alg_smmu1_p1_rsp_vld_cnt_t {
+	ZXIC_UINT32 smmu1_p1_rsp_vld_cnt;
+} DPP_SE_ALG_SMMU1_P1_RSP_VLD_CNT_T;
+
+typedef struct dpp_se_alg_smmu1_p2_rsp_vld_cnt_t {
+	ZXIC_UINT32 smmu1_p2_rsp_vld_cnt;
+} DPP_SE_ALG_SMMU1_P2_RSP_VLD_CNT_T;
+
+typedef struct dpp_se_alg_smmu1_p3_rsp_vld_cnt_t {
+	ZXIC_UINT32 smmu1_p3_rsp_vld_cnt;
+} DPP_SE_ALG_SMMU1_P3_RSP_VLD_CNT_T;
+
+typedef struct dpp_se_alg_smmu1_p4_rsp_vld_cnt_t {
+	ZXIC_UINT32 smmu1_p4_rsp_vld_cnt;
+} DPP_SE_ALG_SMMU1_P4_RSP_VLD_CNT_T;
+
+typedef struct dpp_se_alg_smmu1_p5_rsp_vld_cnt_t {
+	ZXIC_UINT32 smmu1_p5_rsp_vld_cnt;
+} DPP_SE_ALG_SMMU1_P5_RSP_VLD_CNT_T;
+
+typedef struct dpp_se_alg_schd_learn_fifo_int_cnt_t {
+	ZXIC_UINT32 schd_learn_fifo_int_cnt;
+} DPP_SE_ALG_SCHD_LEARN_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_schd_hash0_fifo_int_cnt_t {
+	ZXIC_UINT32 schd_hash0_fifo_int_cnt;
+} DPP_SE_ALG_SCHD_HASH0_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_schd_hash1_fifo_int_cnt_t {
+	ZXIC_UINT32 schd_hash1_fifo_int_cnt;
+} DPP_SE_ALG_SCHD_HASH1_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_schd_hash2_fifo_int_cnt_t {
+	ZXIC_UINT32 schd_hash2_fifo_int_cnt;
+} DPP_SE_ALG_SCHD_HASH2_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_schd_hash3_fifo_int_cnt_t {
+	ZXIC_UINT32 schd_hash3_fifo_int_cnt;
+} DPP_SE_ALG_SCHD_HASH3_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_schd_lpm_fifo_int_cnt_t {
+	ZXIC_UINT32 schd_lpm_fifo_int_cnt;
+} DPP_SE_ALG_SCHD_LPM_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_schd_learn_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 schd_learn_fifo_parity_err_cnt;
+} DPP_SE_ALG_SCHD_LEARN_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_schd_hash0_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 schd_hash0_fifo_parity_err_cnt;
+} DPP_SE_ALG_SCHD_HASH0_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_schd_hash1_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 schd_hash1_fifo_parity_err_cnt;
+} DPP_SE_ALG_SCHD_HASH1_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_schd_hash2_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 schd_hash2_fifo_parity_err_cnt;
+} DPP_SE_ALG_SCHD_HASH2_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_schd_hash3_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 schd_hash3_fifo_parity_err_cnt;
+} DPP_SE_ALG_SCHD_HASH3_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_schd_lpm_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 schd_lpm_fifo_parity_err_cnt;
+} DPP_SE_ALG_SCHD_LPM_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_rd_init_cft_cnt_t {
+	ZXIC_UINT32 rd_init_cft_cnt;
+} DPP_SE_ALG_RD_INIT_CFT_CNT_T;
+
+typedef struct dpp_se_alg_zgp0_zblk0_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp0_zblk0_ecc_err_cnt;
+} DPP_SE_ALG_ZGP0_ZBLK0_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp0_zblk1_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp0_zblk1_ecc_err_cnt;
+} DPP_SE_ALG_ZGP0_ZBLK1_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp0_zblk2_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp0_zblk2_ecc_err_cnt;
+} DPP_SE_ALG_ZGP0_ZBLK2_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp0_zblk3_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp0_zblk3_ecc_err_cnt;
+} DPP_SE_ALG_ZGP0_ZBLK3_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp0_zblk4_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp0_zblk4_ecc_err_cnt;
+} DPP_SE_ALG_ZGP0_ZBLK4_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp0_zblk5_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp0_zblk5_ecc_err_cnt;
+} DPP_SE_ALG_ZGP0_ZBLK5_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp0_zblk6_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp0_zblk6_ecc_err_cnt;
+} DPP_SE_ALG_ZGP0_ZBLK6_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp0_zblk7_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp0_zblk7_ecc_err_cnt;
+} DPP_SE_ALG_ZGP0_ZBLK7_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp1_zblk0_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp1_zblk0_ecc_err_cnt;
+} DPP_SE_ALG_ZGP1_ZBLK0_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp1_zblk1_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp1_zblk1_ecc_err_cnt;
+} DPP_SE_ALG_ZGP1_ZBLK1_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp1_zblk2_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp1_zblk2_ecc_err_cnt;
+} DPP_SE_ALG_ZGP1_ZBLK2_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp1_zblk3_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp1_zblk3_ecc_err_cnt;
+} DPP_SE_ALG_ZGP1_ZBLK3_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp1_zblk4_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp1_zblk4_ecc_err_cnt;
+} DPP_SE_ALG_ZGP1_ZBLK4_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp1_zblk5_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp1_zblk5_ecc_err_cnt;
+} DPP_SE_ALG_ZGP1_ZBLK5_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp1_zblk6_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp1_zblk6_ecc_err_cnt;
+} DPP_SE_ALG_ZGP1_ZBLK6_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp1_zblk7_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp1_zblk7_ecc_err_cnt;
+} DPP_SE_ALG_ZGP1_ZBLK7_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp2_zblk0_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp2_zblk0_ecc_err_cnt;
+} DPP_SE_ALG_ZGP2_ZBLK0_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp2_zblk1_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp2_zblk1_ecc_err_cnt;
+} DPP_SE_ALG_ZGP2_ZBLK1_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp2_zblk2_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp2_zblk2_ecc_err_cnt;
+} DPP_SE_ALG_ZGP2_ZBLK2_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp2_zblk3_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp2_zblk3_ecc_err_cnt;
+} DPP_SE_ALG_ZGP2_ZBLK3_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp2_zblk4_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp2_zblk4_ecc_err_cnt;
+} DPP_SE_ALG_ZGP2_ZBLK4_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp2_zblk5_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp2_zblk5_ecc_err_cnt;
+} DPP_SE_ALG_ZGP2_ZBLK5_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp2_zblk6_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp2_zblk6_ecc_err_cnt;
+} DPP_SE_ALG_ZGP2_ZBLK6_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp2_zblk7_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp2_zblk7_ecc_err_cnt;
+} DPP_SE_ALG_ZGP2_ZBLK7_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp3_zblk0_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp3_zblk0_ecc_err_cnt;
+} DPP_SE_ALG_ZGP3_ZBLK0_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp3_zblk1_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp3_zblk1_ecc_err_cnt;
+} DPP_SE_ALG_ZGP3_ZBLK1_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp3_zblk2_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp3_zblk2_ecc_err_cnt;
+} DPP_SE_ALG_ZGP3_ZBLK2_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp3_zblk3_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp3_zblk3_ecc_err_cnt;
+} DPP_SE_ALG_ZGP3_ZBLK3_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp3_zblk4_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp3_zblk4_ecc_err_cnt;
+} DPP_SE_ALG_ZGP3_ZBLK4_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp3_zblk5_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp3_zblk5_ecc_err_cnt;
+} DPP_SE_ALG_ZGP3_ZBLK5_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp3_zblk6_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp3_zblk6_ecc_err_cnt;
+} DPP_SE_ALG_ZGP3_ZBLK6_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zgp3_zblk7_ecc_err_cnt_t {
+	ZXIC_UINT32 zgp3_zblk7_ecc_err_cnt;
+} DPP_SE_ALG_ZGP3_ZBLK7_ECC_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zcam_hash_p0_err_cnt_t {
+	ZXIC_UINT32 zcam_hash_p0_err_cnt;
+} DPP_SE_ALG_ZCAM_HASH_P0_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zcam_hash_p1_err_cnt_t {
+	ZXIC_UINT32 zcam_hash_p1_err_cnt;
+} DPP_SE_ALG_ZCAM_HASH_P1_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zcam_hash_p2_err_cnt_t {
+	ZXIC_UINT32 zcam_hash_p2_err_cnt;
+} DPP_SE_ALG_ZCAM_HASH_P2_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zcam_hash_p3_err_cnt_t {
+	ZXIC_UINT32 zcam_hash_p3_err_cnt;
+} DPP_SE_ALG_ZCAM_HASH_P3_ERR_CNT_T;
+
+typedef struct dpp_se_alg_zcam_lpm_err_cnt_t {
+	ZXIC_UINT32 zcam_lpm_err_cnt;
+} DPP_SE_ALG_ZCAM_LPM_ERR_CNT_T;
+
+typedef struct dpp_se_alg_hash0_sreq_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 hash0_sreq_fifo_parity_err_cnt;
+} DPP_SE_ALG_HASH0_SREQ_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_hash0_sreq_fifo_int_cnt_t {
+	ZXIC_UINT32 hash0_sreq_fifo_int_cnt;
+} DPP_SE_ALG_HASH0_SREQ_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_hash0_key_fifo_int_cnt_t {
+	ZXIC_UINT32 hash0_key_fifo_int_cnt;
+} DPP_SE_ALG_HASH0_KEY_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_hash0_int_rsp_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 hash0_int_rsp_fifo_parity_err_cnt;
+} DPP_SE_ALG_HASH0_INT_RSP_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_hash0_ext_rsp_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 hash0_ext_rsp_fifo_parity_err_cnt;
+} DPP_SE_ALG_HASH0_EXT_RSP_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_hash0_ext_rsp_fifo_int_cnt_t {
+	ZXIC_UINT32 hash0_ext_rsp_fifo_int_cnt;
+} DPP_SE_ALG_HASH0_EXT_RSP_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_hash0_int_rsp_fifo_int_cnt_t {
+	ZXIC_UINT32 hash0_int_rsp_fifo_int_cnt;
+} DPP_SE_ALG_HASH0_INT_RSP_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_hash1_sreq_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 hash1_sreq_fifo_parity_err_cnt;
+} DPP_SE_ALG_HASH1_SREQ_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_hash1_sreq_fifo_int_cnt_t {
+	ZXIC_UINT32 hash1_sreq_fifo_int_cnt;
+} DPP_SE_ALG_HASH1_SREQ_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_hash1_key_fifo_int_cnt_t {
+	ZXIC_UINT32 hash1_key_fifo_int_cnt;
+} DPP_SE_ALG_HASH1_KEY_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_hash1_int_rsp_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 hash1_int_rsp_fifo_parity_err_cnt;
+} DPP_SE_ALG_HASH1_INT_RSP_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_hash1_ext_rsp_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 hash1_ext_rsp_fifo_parity_err_cnt;
+} DPP_SE_ALG_HASH1_EXT_RSP_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_hash1_ext_rsp_fifo_int_cnt_t {
+	ZXIC_UINT32 hash1_ext_rsp_fifo_int_cnt;
+} DPP_SE_ALG_HASH1_EXT_RSP_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_hash1_int_rsp_fifo_int_cnt_t {
+	ZXIC_UINT32 hash1_int_rsp_fifo_int_cnt;
+} DPP_SE_ALG_HASH1_INT_RSP_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_hash2_sreq_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 hash2_sreq_fifo_parity_err_cnt;
+} DPP_SE_ALG_HASH2_SREQ_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_hash2_sreq_fifo_int_cnt_t {
+	ZXIC_UINT32 hash2_sreq_fifo_int_cnt;
+} DPP_SE_ALG_HASH2_SREQ_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_hash2_key_fifo_int_cnt_t {
+	ZXIC_UINT32 hash2_key_fifo_int_cnt;
+} DPP_SE_ALG_HASH2_KEY_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_hash2_int_rsp_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 hash2_int_rsp_fifo_parity_err_cnt;
+} DPP_SE_ALG_HASH2_INT_RSP_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_hash2_ext_rsp_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 hash2_ext_rsp_fifo_parity_err_cnt;
+} DPP_SE_ALG_HASH2_EXT_RSP_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_hash2_ext_rsp_fifo_int_cnt_t {
+	ZXIC_UINT32 hash2_ext_rsp_fifo_int_cnt;
+} DPP_SE_ALG_HASH2_EXT_RSP_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_hash2_int_rsp_fifo_int_cnt_t {
+	ZXIC_UINT32 hash2_int_rsp_fifo_int_cnt;
+} DPP_SE_ALG_HASH2_INT_RSP_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_hash3_sreq_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 hash3_sreq_fifo_parity_err_cnt;
+} DPP_SE_ALG_HASH3_SREQ_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_hash3_sreq_fifo_int_cnt_t {
+	ZXIC_UINT32 hash3_sreq_fifo_int_cnt;
+} DPP_SE_ALG_HASH3_SREQ_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_hash3_key_fifo_int_cnt_t {
+	ZXIC_UINT32 hash3_key_fifo_int_cnt;
+} DPP_SE_ALG_HASH3_KEY_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_hash3_int_rsp_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 hash3_int_rsp_fifo_parity_err_cnt;
+} DPP_SE_ALG_HASH3_INT_RSP_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_hash3_ext_rsp_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 hash3_ext_rsp_fifo_parity_err_cnt;
+} DPP_SE_ALG_HASH3_EXT_RSP_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_hash3_ext_rsp_fifo_int_cnt_t {
+	ZXIC_UINT32 hash3_ext_rsp_fifo_int_cnt;
+} DPP_SE_ALG_HASH3_EXT_RSP_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_hash3_int_rsp_fifo_int_cnt_t {
+	ZXIC_UINT32 hash3_int_rsp_fifo_int_cnt;
+} DPP_SE_ALG_HASH3_INT_RSP_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_lpm_ext_rsp_fifo_int_cnt_t {
+	ZXIC_UINT32 lpm_ext_rsp_fifo_int_cnt;
+} DPP_SE_ALG_LPM_EXT_RSP_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_lpm_ext_v6_fifo_int_cnt_t {
+	ZXIC_UINT32 lpm_ext_v6_fifo_int_cnt;
+} DPP_SE_ALG_LPM_EXT_V6_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_lpm_ext_v4_fifo_int_cnt_t {
+	ZXIC_UINT32 lpm_ext_v4_fifo_int_cnt;
+} DPP_SE_ALG_LPM_EXT_V4_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_lpm_ext_addr_fifo_int_cnt_t {
+	ZXIC_UINT32 lpm_ext_addr_fifo_int_cnt;
+} DPP_SE_ALG_LPM_EXT_ADDR_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_lpm_ext_v4_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 lpm_ext_v4_fifo_parity_err_cnt;
+} DPP_SE_ALG_LPM_EXT_V4_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_lpm_ext_v6_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 lpm_ext_v6_fifo_parity_err_cnt;
+} DPP_SE_ALG_LPM_EXT_V6_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_lpm_ext_rsp_fifo_parity_err_cnt_t {
+	ZXIC_UINT32 lpm_ext_rsp_fifo_parity_err_cnt;
+} DPP_SE_ALG_LPM_EXT_RSP_FIFO_PARITY_ERR_CNT_T;
+
+typedef struct dpp_se_alg_lpm_as_req_fifo_int_cnt_t {
+	ZXIC_UINT32 lpm_as_req_fifo_int_cnt;
+} DPP_SE_ALG_LPM_AS_REQ_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_lpm_as_int_rsp_fifo_int_cnt_t {
+	ZXIC_UINT32 lpm_as_int_rsp_fifo_int_cnt;
+} DPP_SE_ALG_LPM_AS_INT_RSP_FIFO_INT_CNT_T;
+
+typedef struct dpp_se_alg_se_alg_int_status_t {
+	ZXIC_UINT32 schd_int_unmask_flag;
+	ZXIC_UINT32 zblk_ecc_int_unmask_flag;
+	ZXIC_UINT32 hash0_int_unmask_flag;
+	ZXIC_UINT32 hash1_int_unmask_flag;
+	ZXIC_UINT32 hash2_int_unmask_flag;
+	ZXIC_UINT32 hash3_int_unmask_flag;
+	ZXIC_UINT32 lpm_int_unmask_flag;
+} DPP_SE_ALG_SE_ALG_INT_STATUS_T;
+
+typedef struct dpp_se_alg_schd_int_en_t {
+	ZXIC_UINT32 wr_rsp_fifo_ovfl;
+	ZXIC_UINT32 init_rd_cft_en;
+	ZXIC_UINT32 schd_lpm_fifo_parity_errl;
+	ZXIC_UINT32 schd_hash3_fifo_parity_err;
+	ZXIC_UINT32 schd_hash2_fifo_parity_err;
+	ZXIC_UINT32 schd_hash1_fifo_parity_err;
+	ZXIC_UINT32 schd_hash0_fifo_parity_err;
+	ZXIC_UINT32 schd_learn_fifo_parity_err;
+	ZXIC_UINT32 schd_lpm_fifo_ovfl;
+	ZXIC_UINT32 schd_hash3_fifo_ovfl;
+	ZXIC_UINT32 schd_hash2_fifo_unfl;
+	ZXIC_UINT32 schd_hash1_fifo_ovfl;
+	ZXIC_UINT32 schd_hash0_fifo_ovfl;
+	ZXIC_UINT32 schd_learn_fifo_ovfl;
+} DPP_SE_ALG_SCHD_INT_EN_T;
+
+typedef struct dpp_se_alg_schd_int_mask_t {
+	ZXIC_UINT32 schd_int_mask;
+} DPP_SE_ALG_SCHD_INT_MASK_T;
+
+typedef struct dpp_se_alg_schd_int_status_t {
+	ZXIC_UINT32 schd_int_status;
+} DPP_SE_ALG_SCHD_INT_STATUS_T;
+
+typedef struct dpp_se_alg_zblk_ecc_int_en_t {
+	ZXIC_UINT32 zblk_ecc_int_en;
+} DPP_SE_ALG_ZBLK_ECC_INT_EN_T;
+
+typedef struct dpp_se_alg_zblk_ecc_int_mask_t {
+	ZXIC_UINT32 zblk_ecc_int_mask;
+} DPP_SE_ALG_ZBLK_ECC_INT_MASK_T;
+
+typedef struct dpp_se_alg_zblk_ecc_int_status_t {
+	ZXIC_UINT32 zblk_ecc_int_status;
+} DPP_SE_ALG_ZBLK_ECC_INT_STATUS_T;
+
+typedef struct dpp_se_alg_hash0_int_en_t {
+	ZXIC_UINT32 zcam_hash_p0_err_en;
+	ZXIC_UINT32 hash0_agree_int_fifo_ovf_en;
+	ZXIC_UINT32 hash0_agree_ext_fifo_ovf_en;
+	ZXIC_UINT32 hash0_agree_ext_fifo_parity_err_en;
+	ZXIC_UINT32 hash0_agree_int_fifo_parity_err_en;
+	ZXIC_UINT32 hash0_key_fifo_ovfl_en;
+	ZXIC_UINT32 hash0_sreq_fifo_ovfl_en;
+	ZXIC_UINT32 hash0_key_fifo_parity_err_en;
+} DPP_SE_ALG_HASH0_INT_EN_T;
+
+typedef struct dpp_se_alg_hash0_int_mask_t {
+	ZXIC_UINT32 hash0_int_mask;
+} DPP_SE_ALG_HASH0_INT_MASK_T;
+
+typedef struct dpp_se_alg_hash0_int_status_t {
+	ZXIC_UINT32 hash0_int_status;
+} DPP_SE_ALG_HASH0_INT_STATUS_T;
+
+typedef struct dpp_se_alg_hash1_int_en_t {
+	ZXIC_UINT32 zcam_hash_p1_err_en;
+	ZXIC_UINT32 hash1_agree_int_fifo_ovf_en;
+	ZXIC_UINT32 hash1_agree_ext_fifo_ovf_en;
+	ZXIC_UINT32 hash1_agree_ext_fifo_parity_err_en;
+	ZXIC_UINT32 hash1_agree_int_fifo_parity_err_en;
+	ZXIC_UINT32 hash1_key_fifo_ovfl_en;
+	ZXIC_UINT32 hash1_sreq_fifo_ovfl_en;
+	ZXIC_UINT32 hash1_key_fifo_parity_err_en;
+} DPP_SE_ALG_HASH1_INT_EN_T;
+
+typedef struct dpp_se_alg_hash1_int_mask_t {
+	ZXIC_UINT32 hash1_int_mask;
+} DPP_SE_ALG_HASH1_INT_MASK_T;
+
+typedef struct dpp_se_alg_hash1_int_status_t {
+	ZXIC_UINT32 hash1_int_status;
+} DPP_SE_ALG_HASH1_INT_STATUS_T;
+
+typedef struct dpp_se_alg_hash2_int_en_t {
+	ZXIC_UINT32 zcam_hash_p2_err_en;
+	ZXIC_UINT32 hash2_agree_int_fifo_ovf_en;
+	ZXIC_UINT32 hash2_agree_ext_fifo_ovf_en;
+	ZXIC_UINT32 hash2_agree_ext_fifo_parity_err_en;
+	ZXIC_UINT32 hash2_agree_int_fifo_parity_err_en;
+	ZXIC_UINT32 hash2_key_fifo_ovfl_en;
+	ZXIC_UINT32 hash2_sreq_fifo_ovfl_en;
+	ZXIC_UINT32 hash2_key_fifo_parity_err_en;
+} DPP_SE_ALG_HASH2_INT_EN_T;
+
+typedef struct dpp_se_alg_hash2_int_mask_t {
+	ZXIC_UINT32 hash2_int_mask;
+} DPP_SE_ALG_HASH2_INT_MASK_T;
+
+typedef struct dpp_se_alg_hash2_int_status_t {
+	ZXIC_UINT32 hash2_int_status;
+} DPP_SE_ALG_HASH2_INT_STATUS_T;
+
+typedef struct dpp_se_alg_hash3_int_en_t {
+	ZXIC_UINT32 zcam_hash_p3_err_en;
+	ZXIC_UINT32 hash3_agree_int_fifo_ovf_en;
+	ZXIC_UINT32 hash3_agree_ext_fifo_ovf_en;
+	ZXIC_UINT32 hash3_agree_ext_fifo_parity_err_en;
+	ZXIC_UINT32 hash3_agree_int_fifo_parity_err_en;
+	ZXIC_UINT32 hash3_key_fifo_ovfl_en;
+	ZXIC_UINT32 hash3_sreq_fifo_ovfl_en;
+	ZXIC_UINT32 hash3_key_fifo_parity_err_en;
+} DPP_SE_ALG_HASH3_INT_EN_T;
+
+typedef struct dpp_se_alg_hash3_int_mask_t {
+	ZXIC_UINT32 hash3_int_mask;
+} DPP_SE_ALG_HASH3_INT_MASK_T;
+
+typedef struct dpp_se_alg_hash3_int_status_t {
+	ZXIC_UINT32 hash3_int_status;
+} DPP_SE_ALG_HASH3_INT_STATUS_T;
+
+typedef struct dpp_se_alg_lpm_int_en_t {
+	ZXIC_UINT32 zcam_lpm_err_en;
+	ZXIC_UINT32 lpm_as_int_rsp_fifo_ovfl_en;
+	ZXIC_UINT32 lpm_as_req_fifo_ovfl_en;
+	ZXIC_UINT32 lpm_ext_ddr_rsp_fifo_parity_en;
+	ZXIC_UINT32 lpm_ext_v6_key_parity_en;
+	ZXIC_UINT32 lpm_ext_v4_key_parity_en;
+	ZXIC_UINT32 lpm_ext_addr_fifo_ovfl_en;
+	ZXIC_UINT32 lpm_ext_v4_fifo_ovfl_en;
+	ZXIC_UINT32 lpm_ext_v6_fifo_ovfl_en;
+	ZXIC_UINT32 lpm_ext_ddr_rsp_ovf_en;
+} DPP_SE_ALG_LPM_INT_EN_T;
+
+typedef struct dpp_se_alg_lpm_int_mask_t {
+	ZXIC_UINT32 lpm_int_mask;
+} DPP_SE_ALG_LPM_INT_MASK_T;
+
+typedef struct dpp_se_alg_lpm_int_status_t {
+	ZXIC_UINT32 lpm_int_status;
+} DPP_SE_ALG_LPM_INT_STATUS_T;
+
+typedef struct dpp_se_alg_zblock_lpm_mask0_t {
+	ZXIC_UINT32 vpn_id_mask;
+	ZXIC_UINT32 prefix0_mask;
+	ZXIC_UINT32 prefix1_mask;
+	ZXIC_UINT32 prefix2_mask;
+	ZXIC_UINT32 prefix3_mask;
+} DPP_SE_ALG_ZBLOCK_LPM_MASK0_T;
+
+typedef struct dpp_se_alg_zblock_lpm_mask1_t {
+	ZXIC_UINT32 vpn_id_mask;
+	ZXIC_UINT32 prefix0_mask;
+	ZXIC_UINT32 prefix1_mask;
+	ZXIC_UINT32 prefix2_mask;
+	ZXIC_UINT32 prefix3_mask;
+} DPP_SE_ALG_ZBLOCK_LPM_MASK1_T;
+
+typedef struct dpp_se_alg_zblock_lpm_mask2_t {
+	ZXIC_UINT32 vpn_id_mask;
+	ZXIC_UINT32 prefix0_mask;
+	ZXIC_UINT32 prefix1_mask;
+	ZXIC_UINT32 prefix2_mask;
+	ZXIC_UINT32 prefix3_mask;
+} DPP_SE_ALG_ZBLOCK_LPM_MASK2_T;
+
+typedef struct dpp_se_alg_zblock_lpm_mask3_t {
+	ZXIC_UINT32 vpn_id_mask;
+	ZXIC_UINT32 prefix0_mask;
+	ZXIC_UINT32 prefix1_mask;
+	ZXIC_UINT32 prefix2_mask;
+	ZXIC_UINT32 prefix3_mask;
+} DPP_SE_ALG_ZBLOCK_LPM_MASK3_T;
+
+typedef struct dpp_se_alg_zblock_default_route0_t {
+	ZXIC_UINT32 vpn_id;
+	ZXIC_UINT32 vpn_dresult;
+	ZXIC_UINT32 vpn_flag;
+	ZXIC_UINT32 vpn_vld;
+} DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE0_T;
+
+typedef struct dpp_se_alg_zblock_default_route1_t {
+	ZXIC_UINT32 vpn_id;
+	ZXIC_UINT32 vpn_dresult;
+	ZXIC_UINT32 vpn_flag;
+	ZXIC_UINT32 vpn_vld;
+} DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE1_T;
+
+typedef struct dpp_se_alg_zblock_default_route2_t {
+	ZXIC_UINT32 vpn_id;
+	ZXIC_UINT32 vpn_dresult;
+	ZXIC_UINT32 vpn_flag;
+	ZXIC_UINT32 vpn_vld;
+} DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE2_T;
+
+typedef struct dpp_se_alg_zblock_default_route3_t {
+	ZXIC_UINT32 vpn_id;
+	ZXIC_UINT32 vpn_dresult;
+	ZXIC_UINT32 vpn_flag;
+	ZXIC_UINT32 vpn_vld;
+} DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE3_T;
+
+typedef struct dpp_se_alg_zblock_default_route4_t {
+	ZXIC_UINT32 vpn_id;
+	ZXIC_UINT32 vpn_dresult;
+	ZXIC_UINT32 vpn_flag;
+	ZXIC_UINT32 vpn_vld;
+} DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE4_T;
+
+typedef struct dpp_se_alg_zblock_default_route5_t {
+	ZXIC_UINT32 vpn_id;
+	ZXIC_UINT32 vpn_dresult;
+	ZXIC_UINT32 vpn_flag;
+	ZXIC_UINT32 vpn_vld;
+} DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE5_T;
+
+typedef struct dpp_se_alg_zblock_default_route6_t {
+	ZXIC_UINT32 vpn_id;
+	ZXIC_UINT32 vpn_dresult;
+	ZXIC_UINT32 vpn_flag;
+	ZXIC_UINT32 vpn_vld;
+} DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE6_T;
+
+typedef struct dpp_se_alg_zblock_default_route7_t {
+	ZXIC_UINT32 vpn_id;
+	ZXIC_UINT32 vpn_dresult;
+	ZXIC_UINT32 vpn_flag;
+	ZXIC_UINT32 vpn_vld;
+} DPP_SE_ALG_ZBLOCK_DEFAULT_ROUTE7_T;
+
+typedef struct dpp_se_alg_zblock_hash_listtable_item0_t {
+	ZXIC_UINT32 hash_item;
+} DPP_SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM0_T;
+
+typedef struct dpp_se_alg_zblock_hash_listtable_item1_t {
+	ZXIC_UINT32 hash_item;
+} DPP_SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM1_T;
+
+typedef struct dpp_se_alg_zblock_hash_listtable_item2_t {
+	ZXIC_UINT32 hash_item;
+} DPP_SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM2_T;
+
+typedef struct dpp_se_alg_zblock_hash_listtable_item3_t {
+	ZXIC_UINT32 hash_item;
+} DPP_SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM3_T;
+
+typedef struct dpp_se_alg_zblock_ecc_err_status_t {
+	ZXIC_UINT32 sram3_ecc_err;
+	ZXIC_UINT32 sram2_ecc_err;
+	ZXIC_UINT32 sram1_ecc_err;
+	ZXIC_UINT32 sram0_ecc_err;
+} DPP_SE_ALG_ZBLOCK_ECC_ERR_STATUS_T;
+
+typedef struct dpp_se_alg_zblock_lpm_v6_sram_cmp_t {
+	ZXIC_UINT32 sram_cmp_flag;
+} DPP_SE_ALG_ZBLOCK_LPM_V6_SRAM_CMP_T;
+
+typedef struct dpp_se_alg_zblock_lpm_v4_sram_cmp_t {
+	ZXIC_UINT32 sram_cmp_flag;
+} DPP_SE_ALG_ZBLOCK_LPM_V4_SRAM_CMP_T;
+
+typedef struct dpp_se_parser_kschd_pful_cfg_t {
+	ZXIC_UINT32 kschd_pful_assert;
+	ZXIC_UINT32 kschd_pful_negate;
+} DPP_SE_PARSER_KSCHD_PFUL_CFG_T;
+
+typedef struct dpp_se_parser_debug_cnt_mode_t {
+	ZXIC_UINT32 cnt_rd_mode;
+	ZXIC_UINT32 cnt_overflow_mode;
+} DPP_SE_PARSER_DEBUG_CNT_MODE_T;
+
+typedef struct dpp_se_parser_parser_int_en_t {
+	ZXIC_UINT32 parser_int_en;
+} DPP_SE_PARSER_PARSER_INT_EN_T;
+
+typedef struct dpp_se_parser_parser_int_mask_t {
+	ZXIC_UINT32 parser_int_mask;
+} DPP_SE_PARSER_PARSER_INT_MASK_T;
+
+typedef struct dpp_se_parser_parser_int_status_t {
+	ZXIC_UINT32 parser_int_status;
+} DPP_SE_PARSER_PARSER_INT_STATUS_T;
+
+typedef struct dpp_se_parser_parser_int_unmask_flag_t {
+	ZXIC_UINT32 parser_int_unmask_flag;
+} DPP_SE_PARSER_PARSER_INT_UNMASK_FLAG_T;
+
+typedef struct dpp_se_parser_ecc_bypass_read_t {
+	ZXIC_UINT32 ecc_bypass_read;
+} DPP_SE_PARSER_ECC_BYPASS_READ_T;
+
+typedef struct dpp_se_parser_mex0_5_req_cnt_t {
+	ZXIC_UINT32 mex0_5_req_cnt;
+} DPP_SE_PARSER_MEX0_5_REQ_CNT_T;
+
+typedef struct dpp_se_parser_kschd_req0_5_cnt_t {
+	ZXIC_UINT32 kschd_req0_5_cnt;
+} DPP_SE_PARSER_KSCHD_REQ0_5_CNT_T;
+
+typedef struct dpp_se_parser_kschd_parser_fc0_5_cnt_t {
+	ZXIC_UINT32 kschd_parser_fc0_5_cnt;
+} DPP_SE_PARSER_KSCHD_PARSER_FC0_5_CNT_T;
+
+typedef struct dpp_se_parser_se_ppu_mex0_5_fc_cnt_t {
+	ZXIC_UINT32 se_ppu_mex0_5_fc_cnt;
+} DPP_SE_PARSER_SE_PPU_MEX0_5_FC_CNT_T;
+
+typedef struct dpp_se_parser_smmu0_marc_fc_cnt_t {
+	ZXIC_UINT32 smmu0_marc_fc_cnt;
+} DPP_SE_PARSER_SMMU0_MARC_FC_CNT_T;
+
+typedef struct dpp_se_parser_smmu0_marc_key_cnt_t {
+	ZXIC_UINT32 smmu0_marc_key_cnt;
+} DPP_SE_PARSER_SMMU0_MARC_KEY_CNT_T;
+
+typedef struct dpp_se_parser_cmmu_key_cnt_t {
+	ZXIC_UINT32 cmmu_key_cnt;
+} DPP_SE_PARSER_CMMU_KEY_CNT_T;
+
+typedef struct dpp_se_parser_cmmu_parser_fc_cnt_t {
+	ZXIC_UINT32 cmmu_parser_fc_cnt;
+} DPP_SE_PARSER_CMMU_PARSER_FC_CNT_T;
+
+typedef struct dpp_se_parser_marc_tab_type_err_mex0_5_cnt_t {
+	ZXIC_UINT32 marc_tab_type_err_mex0_5_cnt;
+} DPP_SE_PARSER_MARC_TAB_TYPE_ERR_MEX0_5_CNT_T;
+
+typedef struct dpp_se_parser_eram_fulladdr_drop_cnt_t {
+	ZXIC_UINT32 eram_fulladdr_drop_cnt;
+} DPP_SE_PARSER_ERAM_FULLADDR_DROP_CNT_T;
+
+typedef struct dpp_se_as_hash0_pful_cfg_t {
+	ZXIC_UINT32 hash0_pful_cfg;
+} DPP_SE_AS_HASH0_PFUL_CFG_T;
+
+typedef struct dpp_se_as_hash1_pful_cfg_t {
+	ZXIC_UINT32 hash1_pful_cfg;
+} DPP_SE_AS_HASH1_PFUL_CFG_T;
+
+typedef struct dpp_se_as_hash2_pful_cfg_t {
+	ZXIC_UINT32 hash2_pful_cfg;
+} DPP_SE_AS_HASH2_PFUL_CFG_T;
+
+typedef struct dpp_se_as_hash3_pful_cfg_t {
+	ZXIC_UINT32 hash3_pful_cfg;
+} DPP_SE_AS_HASH3_PFUL_CFG_T;
+
+typedef struct dpp_se_as_pbu_pful_cfg_t {
+	ZXIC_UINT32 pbu_pful_cfg;
+} DPP_SE_AS_PBU_PFUL_CFG_T;
+
+typedef struct dpp_se_as_lpm_pful_cfg_t {
+	ZXIC_UINT32 lpm_pful_cfg;
+} DPP_SE_AS_LPM_PFUL_CFG_T;
+
+typedef struct dpp_se_as_etcam_pful_cfg_t {
+	ZXIC_UINT32 etcam_pful_cfg;
+} DPP_SE_AS_ETCAM_PFUL_CFG_T;
+
+typedef struct dpp_se_as_as_learn0_fifo_cfg_t {
+	ZXIC_UINT32 as_learn1_pful_negate;
+	ZXIC_UINT32 as_learn1_pful_asert;
+	ZXIC_UINT32 as_learn0_pful_negate;
+	ZXIC_UINT32 as_learn0_pful_asert;
+} DPP_SE_AS_AS_LEARN0_FIFO_CFG_T;
+
+typedef struct dpp_se_as_as_learn1_fifo_cfg_t {
+	ZXIC_UINT32 as_learn3_pful_negate;
+	ZXIC_UINT32 as_learn3_pful_asert;
+	ZXIC_UINT32 as_learn2_pful_negate;
+	ZXIC_UINT32 as_learn2_pful_asert;
+} DPP_SE_AS_AS_LEARN1_FIFO_CFG_T;
+
+typedef struct dpp_se_as_as_dma_fifo_cfg_t {
+	ZXIC_UINT32 as_dma_fifo_cfg;
+} DPP_SE_AS_AS_DMA_FIFO_CFG_T;
+
+typedef struct dpp_se_as_age_pful_cfg_t {
+	ZXIC_UINT32 age_pful_cfg;
+} DPP_SE_AS_AGE_PFUL_CFG_T;
+
+typedef struct dpp_se_as_etcam_rsp_cfg_t {
+	ZXIC_UINT32 eram_rsp_pful_negate;
+	ZXIC_UINT32 eram_rsp_pful_assert;
+	ZXIC_UINT32 etcam_rsp_pful_negate;
+	ZXIC_UINT32 etcam_rsp_pful_assert;
+} DPP_SE_AS_ETCAM_RSP_CFG_T;
+
+typedef struct dpp_se_as_pbu_ecc_bypass_read_t {
+	ZXIC_UINT32 pbu_ecc_bypass_read;
+} DPP_SE_AS_PBU_ECC_BYPASS_READ_T;
+
+typedef struct dpp_se_as_etcam0_ecc_bypass_read_t {
+	ZXIC_UINT32 etcam0_ecc_bypass_read;
+} DPP_SE_AS_ETCAM0_ECC_BYPASS_READ_T;
+
+typedef struct dpp_se_as_etcam1_ecc_bypass_read_t {
+	ZXIC_UINT32 etcam1_ecc_bypass_read;
+} DPP_SE_AS_ETCAM1_ECC_BYPASS_READ_T;
+
+typedef struct dpp_se_as_lpm_ecc_bypass_read_t {
+	ZXIC_UINT32 lpm_ecc_bypass_read;
+} DPP_SE_AS_LPM_ECC_BYPASS_READ_T;
+
+typedef struct dpp_se_as_hash_ecc_bypass_read_t {
+	ZXIC_UINT32 hash3_ecc_bypass_read;
+	ZXIC_UINT32 hash2_ecc_bypass_read;
+	ZXIC_UINT32 hash1_ecc_bypass_read;
+	ZXIC_UINT32 hash0_ecc_bypass_read;
+} DPP_SE_AS_HASH_ECC_BYPASS_READ_T;
+
+typedef struct dpp_se_as_hash_learn_ecc_bypass_read_t {
+	ZXIC_UINT32 hash_learn_ecc_bypass_read;
+} DPP_SE_AS_HASH_LEARN_ECC_BYPASS_READ_T;
+
+typedef struct dpp_se_as_debug_cnt_mode_t {
+	ZXIC_UINT32 cnt_rd_mode;
+	ZXIC_UINT32 cnt_overflow_mode;
+} DPP_SE_AS_DEBUG_CNT_MODE_T;
+
+typedef struct dpp_se_as_as_int_0_en_t {
+	ZXIC_UINT32 as_int_0_en;
+} DPP_SE_AS_AS_INT_0_EN_T;
+
+typedef struct dpp_se_as_as_int_0_mask_t {
+	ZXIC_UINT32 as_int_0_mask;
+} DPP_SE_AS_AS_INT_0_MASK_T;
+
+typedef struct dpp_se_as_as_int_1_en_t {
+	ZXIC_UINT32 as_int_1_en;
+} DPP_SE_AS_AS_INT_1_EN_T;
+
+typedef struct dpp_se_as_as_int_1_mask_t {
+	ZXIC_UINT32 as_int_1_mask;
+} DPP_SE_AS_AS_INT_1_MASK_T;
+
+typedef struct dpp_se_as_as_int_2_en_t {
+	ZXIC_UINT32 as_int_2_en;
+} DPP_SE_AS_AS_INT_2_EN_T;
+
+typedef struct dpp_se_as_as_int_2_mask_t {
+	ZXIC_UINT32 as_int_2_mask;
+} DPP_SE_AS_AS_INT_2_MASK_T;
+
+typedef struct dpp_se_as_as_int_0_status_t {
+	ZXIC_UINT32 port0_int_status;
+} DPP_SE_AS_AS_INT_0_STATUS_T;
+
+typedef struct dpp_se_as_as_int_1_status_t {
+	ZXIC_UINT32 port1_int_status;
+} DPP_SE_AS_AS_INT_1_STATUS_T;
+
+typedef struct dpp_se_as_as_int_2_status_t {
+	ZXIC_UINT32 port2_int_status;
+} DPP_SE_AS_AS_INT_2_STATUS_T;
+
+typedef struct dpp_se_as_se_as_int_status_t {
+	ZXIC_UINT32 as_int_2_unmask_flag;
+	ZXIC_UINT32 as_int_1_unmask_flag;
+	ZXIC_UINT32 as_int_0_unmask_flag;
+} DPP_SE_AS_SE_AS_INT_STATUS_T;
+
+typedef struct dpp_se_as_hash0_3_wr_req_cnt_t {
+	ZXIC_UINT32 hash0_3_wr_req_cnt;
+} DPP_SE_AS_HASH0_3_WR_REQ_CNT_T;
+
+typedef struct dpp_se_as_smmu0_etcam0_1_fc_cnt_t {
+	ZXIC_UINT32 smmu0_etcam0_1_fc_cnt;
+} DPP_SE_AS_SMMU0_ETCAM0_1_FC_CNT_T;
+
+typedef struct dpp_se_as_etcam0_1_smmu0_req_cnt_t {
+	ZXIC_UINT32 etcam0_1_smmu0_req_cnt;
+} DPP_SE_AS_ETCAM0_1_SMMU0_REQ_CNT_T;
+
+typedef struct dpp_se_as_smmu0_etcam0_1_rsp_cnt_t {
+	ZXIC_UINT32 smmu0_etcam0_1_rsp_cnt;
+} DPP_SE_AS_SMMU0_ETCAM0_1_RSP_CNT_T;
+
+typedef struct dpp_se_as_as_hla_hash_p0_3_key_cnt_t {
+	ZXIC_UINT32 as_hla_hash_p0_3_key_cnt;
+} DPP_SE_AS_AS_HLA_HASH_P0_3_KEY_CNT_T;
+
+typedef struct dpp_se_as_as_hla_lpm_p0_key_cnt_t {
+	ZXIC_UINT32 as_hla_lpm_p0_key_cnt;
+} DPP_SE_AS_AS_HLA_LPM_P0_KEY_CNT_T;
+
+typedef struct dpp_se_as_alg_as_hash_p0_3_rsp_cnt_t {
+	ZXIC_UINT32 alg_as_hash_p0_3_rsp_cnt;
+} DPP_SE_AS_ALG_AS_HASH_P0_3_RSP_CNT_T;
+
+typedef struct dpp_se_as_alg_as_hash_p0_3_smf_rsp_cnt_t {
+	ZXIC_UINT32 alg_as_hash_p0_3_smf_rsp_cnt;
+} DPP_SE_AS_ALG_AS_HASH_P0_3_SMF_RSP_CNT_T;
+
+typedef struct dpp_se_as_alg_as_lpm_p0_rsp_cnt_t {
+	ZXIC_UINT32 alg_as_lpm_p0_rsp_cnt;
+} DPP_SE_AS_ALG_AS_LPM_P0_RSP_CNT_T;
+
+typedef struct dpp_se_as_alg_as_lpm_p0_3_smf_rsp_cnt_t {
+	ZXIC_UINT32 alg_as_lpm_p0_3_smf_rsp_cnt;
+} DPP_SE_AS_ALG_AS_LPM_P0_3_SMF_RSP_CNT_T;
+
+typedef struct dpp_se_as_as_pbu_key_cnt_t {
+	ZXIC_UINT32 as_pbu_key_cnt;
+} DPP_SE_AS_AS_PBU_KEY_CNT_T;
+
+typedef struct dpp_se_as_pbu_se_dpi_rsp_dat_cnt_t {
+	ZXIC_UINT32 pbu_se_dpi_rsp_dat_cnt;
+} DPP_SE_AS_PBU_SE_DPI_RSP_DAT_CNT_T;
+
+typedef struct dpp_se_as_as_etcam_ctrl_req0_cnt_t {
+	ZXIC_UINT32 as_etcam_ctrl_req0_cnt;
+} DPP_SE_AS_AS_ETCAM_CTRL_REQ0_CNT_T;
+
+typedef struct dpp_se_as_etcam_ctrl_as_index0_1_cnt_t {
+	ZXIC_UINT32 etcam_ctrl_as_index0_1_cnt;
+} DPP_SE_AS_ETCAM_CTRL_AS_INDEX0_1_CNT_T;
+
+typedef struct dpp_se_as_etcam_ctrl_as_hit0_1_cnt_t {
+	ZXIC_UINT32 etcam_ctrl_as_hit0_1_cnt;
+} DPP_SE_AS_ETCAM_CTRL_AS_HIT0_1_CNT_T;
+
+typedef struct dpp_se_as_as_smmu0_req_cnt_t {
+	ZXIC_UINT32 as_smmu0_req_cnt;
+} DPP_SE_AS_AS_SMMU0_REQ_CNT_T;
+
+typedef struct dpp_se_as_learn_hla_wr_cnt_t {
+	ZXIC_UINT32 learn_hla_wr_cnt;
+} DPP_SE_AS_LEARN_HLA_WR_CNT_T;
+
+typedef struct dpp_se_as_as_smmu1_req_cnt_t {
+	ZXIC_UINT32 as_smmu1_req_cnt;
+} DPP_SE_AS_AS_SMMU1_REQ_CNT_T;
+
+typedef struct dpp_se_as_se_cfg_mac_dat_cnt_t {
+	ZXIC_UINT32 se_cfg_mac_dat_cnt;
+} DPP_SE_AS_SE_CFG_MAC_DAT_CNT_T;
+
+typedef struct dpp_se_as_alg_as_hash_p0_3_fc_cnt_t {
+	ZXIC_UINT32 alg_as_hash_p0_3_fc_cnt;
+} DPP_SE_AS_ALG_AS_HASH_P0_3_FC_CNT_T;
+
+typedef struct dpp_se_as_alg_as_lpm_p0_fc_cnt_t {
+	ZXIC_UINT32 alg_as_lpm_p0_fc_cnt;
+} DPP_SE_AS_ALG_AS_LPM_P0_FC_CNT_T;
+
+typedef struct dpp_se_as_as_alg_hash_p0_3_fc_cnt_t {
+	ZXIC_UINT32 as_alg_hash_p0_3_fc_cnt;
+} DPP_SE_AS_AS_ALG_HASH_P0_3_FC_CNT_T;
+
+typedef struct dpp_se_as_as_alg_lpm_p0_fc_cnt_t {
+	ZXIC_UINT32 as_alg_lpm_p0_fc_cnt;
+} DPP_SE_AS_AS_ALG_LPM_P0_FC_CNT_T;
+
+typedef struct dpp_se_as_as_pbu_fc_cnt_t {
+	ZXIC_UINT32 as_pbu_fc_cnt;
+} DPP_SE_AS_AS_PBU_FC_CNT_T;
+
+typedef struct dpp_se_as_pbu_se_dpi_key_fc_cnt_t {
+	ZXIC_UINT32 pbu_se_dpi_key_fc_cnt;
+} DPP_SE_AS_PBU_SE_DPI_KEY_FC_CNT_T;
+
+typedef struct dpp_se_as_as_etcam_ctrl_fc0_1_cnt_t {
+	ZXIC_UINT32 as_etcam_ctrl_fc0_1_cnt;
+} DPP_SE_AS_AS_ETCAM_CTRL_FC0_1_CNT_T;
+
+typedef struct dpp_se_as_etcam_ctrl_as_fc0_1_cnt_t {
+	ZXIC_UINT32 etcam_ctrl_as_fc0_1_cnt;
+} DPP_SE_AS_ETCAM_CTRL_AS_FC0_1_CNT_T;
+
+typedef struct dpp_se_as_smmu0_as_mac_age_fc_cnt_t {
+	ZXIC_UINT32 smmu0_as_mac_age_fc_cnt;
+} DPP_SE_AS_SMMU0_AS_MAC_AGE_FC_CNT_T;
+
+typedef struct dpp_se_as_alg_learn_fc_cnt_t {
+	ZXIC_UINT32 alg_learn_fc_cnt;
+} DPP_SE_AS_ALG_LEARN_FC_CNT_T;
+
+typedef struct dpp_se_as_smmu1_as_fc_cnt_t {
+	ZXIC_UINT32 smmu1_as_fc_cnt;
+} DPP_SE_AS_SMMU1_AS_FC_CNT_T;
+
+typedef struct dpp_se_as_cfg_se_mac_fc_cnt_t {
+	ZXIC_UINT32 cfg_se_mac_fc_cnt;
+} DPP_SE_AS_CFG_SE_MAC_FC_CNT_T;
+
+typedef struct dpp_se_kschd_kschd_cpu_rdy_t {
+	ZXIC_UINT32 kschd_cpu_rdy;
+} DPP_SE_KSCHD_KSCHD_CPU_RDY_T;
+
+typedef struct dpp_se_kschd_ppu0_ecc_bypass_read_t {
+	ZXIC_UINT32 ppu0_ecc_bypass_read;
+} DPP_SE_KSCHD_PPU0_ECC_BYPASS_READ_T;
+
+typedef struct dpp_se_kschd_pbu_ecc_bypass_read_t {
+	ZXIC_UINT32 pbu_ecc_bypass_read;
+} DPP_SE_KSCHD_PBU_ECC_BYPASS_READ_T;
+
+typedef struct dpp_se_kschd_smmu1_ecc_bypass_read_t {
+	ZXIC_UINT32 u3_smmu1_ecc_bypass_read;
+	ZXIC_UINT32 u2_smmu1_ecc_bypass_read;
+	ZXIC_UINT32 u1_smmu1_ecc_bypass_read;
+	ZXIC_UINT32 u0_smmu1_ecc_bypass_read;
+} DPP_SE_KSCHD_SMMU1_ECC_BYPASS_READ_T;
+
+typedef struct dpp_se_kschd_ass_ecc_bypass_read_t {
+	ZXIC_UINT32 ass_ecc_bypass_read;
+} DPP_SE_KSCHD_ASS_ECC_BYPASS_READ_T;
+
+typedef struct dpp_se_kschd_sdt_h_t {
+	ZXIC_UINT32 sdt_h;
+} DPP_SE_KSCHD_SDT_H_T;
+
+typedef struct dpp_se_kschd_sdt_l_t {
+	ZXIC_UINT32 sdt_l;
+} DPP_SE_KSCHD_SDT_L_T;
+
+typedef struct dpp_se_kschd_hash_key15_t {
+	ZXIC_UINT32 dma_en;
+	ZXIC_UINT32 delete_en;
+	ZXIC_UINT32 hash_key15;
+} DPP_SE_KSCHD_HASH_KEY15_T;
+
+typedef struct dpp_se_kschd_hash_key14_t {
+	ZXIC_UINT32 hash_key14;
+} DPP_SE_KSCHD_HASH_KEY14_T;
+
+typedef struct dpp_se_kschd_hash_key13_t {
+	ZXIC_UINT32 hash_key13;
+} DPP_SE_KSCHD_HASH_KEY13_T;
+
+typedef struct dpp_se_kschd_hash_key12_t {
+	ZXIC_UINT32 hash_key12;
+} DPP_SE_KSCHD_HASH_KEY12_T;
+
+typedef struct dpp_se_kschd_hash_key11_t {
+	ZXIC_UINT32 hash_key11;
+} DPP_SE_KSCHD_HASH_KEY11_T;
+
+typedef struct dpp_se_kschd_hash_key10_t {
+	ZXIC_UINT32 hash_key10;
+} DPP_SE_KSCHD_HASH_KEY10_T;
+
+typedef struct dpp_se_kschd_hash_key9_t {
+	ZXIC_UINT32 hash_key9;
+} DPP_SE_KSCHD_HASH_KEY9_T;
+
+typedef struct dpp_se_kschd_hash_key8_t {
+	ZXIC_UINT32 hash_key8;
+} DPP_SE_KSCHD_HASH_KEY8_T;
+
+typedef struct dpp_se_kschd_hash_key7_t {
+	ZXIC_UINT32 hash_key7;
+} DPP_SE_KSCHD_HASH_KEY7_T;
+
+typedef struct dpp_se_kschd_hash_key6_t {
+	ZXIC_UINT32 hash_key6;
+} DPP_SE_KSCHD_HASH_KEY6_T;
+
+typedef struct dpp_se_kschd_hash_key5_t {
+	ZXIC_UINT32 hash_key5;
+} DPP_SE_KSCHD_HASH_KEY5_T;
+
+typedef struct dpp_se_kschd_hash_key4_t {
+	ZXIC_UINT32 hash_key4;
+} DPP_SE_KSCHD_HASH_KEY4_T;
+
+typedef struct dpp_se_kschd_hash_key3_t {
+	ZXIC_UINT32 hash_key3;
+} DPP_SE_KSCHD_HASH_KEY3_T;
+
+typedef struct dpp_se_kschd_hash_key2_t {
+	ZXIC_UINT32 hash_key2;
+} DPP_SE_KSCHD_HASH_KEY2_T;
+
+typedef struct dpp_se_kschd_hash_key1_t {
+	ZXIC_UINT32 hash_key1;
+} DPP_SE_KSCHD_HASH_KEY1_T;
+
+typedef struct dpp_se_kschd_hash_key0_t {
+	ZXIC_UINT32 hash_key0;
+} DPP_SE_KSCHD_HASH_KEY0_T;
+
+typedef struct dpp_se_kschd_schd_int_0_en_t {
+	ZXIC_UINT32 port0_int_en;
+} DPP_SE_KSCHD_SCHD_INT_0_EN_T;
+
+typedef struct dpp_se_kschd_schd_int_0_mask_t {
+	ZXIC_UINT32 port0_int_mask;
+} DPP_SE_KSCHD_SCHD_INT_0_MASK_T;
+
+typedef struct dpp_se_kschd_schd_int_1_en_t {
+	ZXIC_UINT32 port1_int_en;
+} DPP_SE_KSCHD_SCHD_INT_1_EN_T;
+
+typedef struct dpp_se_kschd_schd_int_1_mask_t {
+	ZXIC_UINT32 port1_int_mask;
+} DPP_SE_KSCHD_SCHD_INT_1_MASK_T;
+
+typedef struct dpp_se_kschd_schd_int_2_en_t {
+	ZXIC_UINT32 port2_int_en;
+} DPP_SE_KSCHD_SCHD_INT_2_EN_T;
+
+typedef struct dpp_se_kschd_schd_int_2_mask_t {
+	ZXIC_UINT32 port2_int_mask;
+} DPP_SE_KSCHD_SCHD_INT_2_MASK_T;
+
+typedef struct dpp_se_kschd_schd_int_3_en_t {
+	ZXIC_UINT32 port3_int_en;
+} DPP_SE_KSCHD_SCHD_INT_3_EN_T;
+
+typedef struct dpp_se_kschd_schd_int_3_mask_t {
+	ZXIC_UINT32 port3_int_mask;
+} DPP_SE_KSCHD_SCHD_INT_3_MASK_T;
+
+typedef struct dpp_se_kschd_schd_int_4_en_t {
+	ZXIC_UINT32 port4_int_en;
+} DPP_SE_KSCHD_SCHD_INT_4_EN_T;
+
+typedef struct dpp_se_kschd_schd_int_4_mask_t {
+	ZXIC_UINT32 port4_int_mask;
+} DPP_SE_KSCHD_SCHD_INT_4_MASK_T;
+
+typedef struct dpp_se_kschd_schd_int_0_status_t {
+	ZXIC_UINT32 port0_int_status;
+} DPP_SE_KSCHD_SCHD_INT_0_STATUS_T;
+
+typedef struct dpp_se_kschd_schd_int_1_status_t {
+	ZXIC_UINT32 port1_int_status;
+} DPP_SE_KSCHD_SCHD_INT_1_STATUS_T;
+
+typedef struct dpp_se_kschd_schd_int_2_status_t {
+	ZXIC_UINT32 port2_int_status;
+} DPP_SE_KSCHD_SCHD_INT_2_STATUS_T;
+
+typedef struct dpp_se_kschd_schd_int_3_status_t {
+	ZXIC_UINT32 port3_int_status;
+} DPP_SE_KSCHD_SCHD_INT_3_STATUS_T;
+
+typedef struct dpp_se_kschd_schd_int_4_status_t {
+	ZXIC_UINT32 port4_int_status;
+} DPP_SE_KSCHD_SCHD_INT_4_STATUS_T;
+
+typedef struct dpp_se_kschd_se_kschd_int_status_t {
+	ZXIC_UINT32 schd_int4_unmask_flag;
+	ZXIC_UINT32 schd_int3_unmask_flag;
+	ZXIC_UINT32 schd_int2_unmask_flag;
+	ZXIC_UINT32 schd_int1_unmask_flag;
+	ZXIC_UINT32 schd_int0_unmask_flag;
+} DPP_SE_KSCHD_SE_KSCHD_INT_STATUS_T;
+
+typedef struct dpp_se_kschd_debug_cnt_mode_t {
+	ZXIC_UINT32 cnt_rd_mode;
+	ZXIC_UINT32 cnt_overflow_mode;
+} DPP_SE_KSCHD_DEBUG_CNT_MODE_T;
+
+typedef struct dpp_se_kschd_se_parser_kschd_key0_3_cnt_t {
+	ZXIC_UINT32 se_parser_kschd_key0_3_cnt;
+} DPP_SE_KSCHD_SE_PARSER_KSCHD_KEY0_3_CNT_T;
+
+typedef struct dpp_se_kschd_se_smmu1_key0_3_cnt_t {
+	ZXIC_UINT32 se_smmu1_key0_3_cnt;
+} DPP_SE_KSCHD_SE_SMMU1_KEY0_3_CNT_T;
+
+typedef struct dpp_se_kschd_kschd_as_key0_cnt_t {
+	ZXIC_UINT32 kschd_as_key0_cnt;
+} DPP_SE_KSCHD_KSCHD_AS_KEY0_CNT_T;
+
+typedef struct dpp_se_kschd_kschd_as_key1_cnt_t {
+	ZXIC_UINT32 kschd_as_key1_cnt;
+} DPP_SE_KSCHD_KSCHD_AS_KEY1_CNT_T;
+
+typedef struct dpp_se_kschd_kschd_as_key2_cnt_t {
+	ZXIC_UINT32 kschd_as_key2_cnt;
+} DPP_SE_KSCHD_KSCHD_AS_KEY2_CNT_T;
+
+typedef struct dpp_se_kschd_kschd_as_key3_cnt_t {
+	ZXIC_UINT32 kschd_as_key3_cnt;
+} DPP_SE_KSCHD_KSCHD_AS_KEY3_CNT_T;
+
+typedef struct dpp_se_kschd_kschd_as_key4_cnt_t {
+	ZXIC_UINT32 kschd_as_key4_cnt;
+} DPP_SE_KSCHD_KSCHD_AS_KEY4_CNT_T;
+
+typedef struct dpp_se_kschd_kschd_as_key5_cnt_t {
+	ZXIC_UINT32 kschd_as_key5_cnt;
+} DPP_SE_KSCHD_KSCHD_AS_KEY5_CNT_T;
+
+typedef struct dpp_se_kschd_kschd_as_key6_cnt_t {
+	ZXIC_UINT32 kschd_as_key6_cnt;
+} DPP_SE_KSCHD_KSCHD_AS_KEY6_CNT_T;
+
+typedef struct dpp_se_kschd_kschd_as_key9_cnt_t {
+	ZXIC_UINT32 kschd_as_key9_cnt;
+} DPP_SE_KSCHD_KSCHD_AS_KEY9_CNT_T;
+
+typedef struct dpp_se_kschd_kschd_se_parser_fc0_3_cnt_t {
+	ZXIC_UINT32 kschd_se_parser_fc0_3_cnt;
+} DPP_SE_KSCHD_KSCHD_SE_PARSER_FC0_3_CNT_T;
+
+typedef struct dpp_se_kschd_smmu1_se_fc0_3_cnt_t {
+	ZXIC_UINT32 smmu1_se_fc0_3_cnt;
+} DPP_SE_KSCHD_SMMU1_SE_FC0_3_CNT_T;
+
+typedef struct dpp_se_kschd_as_kschd_fc_cnt0_t {
+	ZXIC_UINT32 as_kschd_fc_cnt0;
+} DPP_SE_KSCHD_AS_KSCHD_FC_CNT0_T;
+
+typedef struct dpp_se_kschd_as_kschd_fc_cnt1_t {
+	ZXIC_UINT32 as_kschd_fc_cnt1;
+} DPP_SE_KSCHD_AS_KSCHD_FC_CNT1_T;
+
+typedef struct dpp_se_kschd_as_kschd_fc_cnt2_t {
+	ZXIC_UINT32 as_kschd_fc_cnt2;
+} DPP_SE_KSCHD_AS_KSCHD_FC_CNT2_T;
+
+typedef struct dpp_se_kschd_as_kschd_fc_cnt3_t {
+	ZXIC_UINT32 as_kschd_fc_cnt3;
+} DPP_SE_KSCHD_AS_KSCHD_FC_CNT3_T;
+
+typedef struct dpp_se_kschd_as_kschd_fc_cnt4_t {
+	ZXIC_UINT32 as_kschd_fc_cnt4;
+} DPP_SE_KSCHD_AS_KSCHD_FC_CNT4_T;
+
+typedef struct dpp_se_kschd_as_kschd_fc_cnt5_t {
+	ZXIC_UINT32 as_kschd_fc_cnt5;
+} DPP_SE_KSCHD_AS_KSCHD_FC_CNT5_T;
+
+typedef struct dpp_se_kschd_as_kschd_fc_cnt6_t {
+	ZXIC_UINT32 as_kschd_fc_cnt6;
+} DPP_SE_KSCHD_AS_KSCHD_FC_CNT6_T;
+
+typedef struct dpp_se_kschd_as_kschd_fc_cnt9_t {
+	ZXIC_UINT32 as_kschd_fc_cnt9;
+} DPP_SE_KSCHD_AS_KSCHD_FC_CNT9_T;
+
+typedef struct dpp_se_rschd_rschd_hash_pful_cfg_t {
+	ZXIC_UINT32 rschd_hash_pful_cfg;
+} DPP_SE_RSCHD_RSCHD_HASH_PFUL_CFG_T;
+
+typedef struct dpp_se_rschd_rschd_hash_ept_cfg_t {
+	ZXIC_UINT32 rschd_hash_ept_cfg;
+} DPP_SE_RSCHD_RSCHD_HASH_EPT_CFG_T;
+
+typedef struct dpp_se_rschd_rschd_pbu_pful_cfg_t {
+	ZXIC_UINT32 rschd_pbu_pful_cfg;
+} DPP_SE_RSCHD_RSCHD_PBU_PFUL_CFG_T;
+
+typedef struct dpp_se_rschd_rschd_pbu_ept_cfg_t {
+	ZXIC_UINT32 rschd_pbu_ept_cfg;
+} DPP_SE_RSCHD_RSCHD_PBU_EPT_CFG_T;
+
+typedef struct dpp_se_rschd_rschd_lpm_pful_cfg_t {
+	ZXIC_UINT32 rschd_lpm_pful_cfg;
+} DPP_SE_RSCHD_RSCHD_LPM_PFUL_CFG_T;
+
+typedef struct dpp_se_rschd_rschd_lpm_ept_cfg_t {
+	ZXIC_UINT32 rschd_lpm_ept_cfg;
+} DPP_SE_RSCHD_RSCHD_LPM_EPT_CFG_T;
+
+typedef struct dpp_se_rschd_rschd_etcam_pful_cfg_t {
+	ZXIC_UINT32 rschd_etcam_pful_cfg;
+} DPP_SE_RSCHD_RSCHD_ETCAM_PFUL_CFG_T;
+
+typedef struct dpp_se_rschd_rschd_etcam_ept_cfg_t {
+	ZXIC_UINT32 rschd_etcam_ept_cfg;
+} DPP_SE_RSCHD_RSCHD_ETCAM_EPT_CFG_T;
+
+typedef struct dpp_se_rschd_smmu0_wb_pful_cfg_t {
+	ZXIC_UINT32 smmu0_wb_pful_cfg;
+} DPP_SE_RSCHD_SMMU0_WB_PFUL_CFG_T;
+
+typedef struct dpp_se_rschd_smmu0_wb_ept_cfg_t {
+	ZXIC_UINT32 smmu0_wb_ept_cfg;
+} DPP_SE_RSCHD_SMMU0_WB_EPT_CFG_T;
+
+typedef struct dpp_se_rschd_smmu1_wb_pful_cfg_t {
+	ZXIC_UINT32 smmu1_wb_pful_cfg;
+} DPP_SE_RSCHD_SMMU1_WB_PFUL_CFG_T;
+
+typedef struct dpp_se_rschd_smmu1_wb_ept_cfg_t {
+	ZXIC_UINT32 smmu1_wb_ept_cfg;
+} DPP_SE_RSCHD_SMMU1_WB_EPT_CFG_T;
+
+typedef struct dpp_se_rschd_alg_wb_pful_cfg_t {
+	ZXIC_UINT32 alg_wb_pful_cfg;
+} DPP_SE_RSCHD_ALG_WB_PFUL_CFG_T;
+
+typedef struct dpp_se_rschd_alg_wb_ept_cfg_t {
+	ZXIC_UINT32 alg_wb_ept_cfg;
+} DPP_SE_RSCHD_ALG_WB_EPT_CFG_T;
+
+typedef struct dpp_se_rschd_wr_rsp_vld_en_t {
+	ZXIC_UINT32 wr_rsp_vld_en;
+} DPP_SE_RSCHD_WR_RSP_VLD_EN_T;
+
+typedef struct dpp_se_rschd_nppu_wb_pful_cfg_t {
+	ZXIC_UINT32 nppu_wb_pful_cfg;
+} DPP_SE_RSCHD_NPPU_WB_PFUL_CFG_T;
+
+typedef struct dpp_se_rschd_nppu_wb_ept_cfg_t {
+	ZXIC_UINT32 nppu_wb_ept_cfg;
+} DPP_SE_RSCHD_NPPU_WB_EPT_CFG_T;
+
+typedef struct dpp_se_rschd_port0_int_en_t {
+	ZXIC_UINT32 port0_int_en;
+} DPP_SE_RSCHD_PORT0_INT_EN_T;
+
+typedef struct dpp_se_rschd_port0_int_mask_t {
+	ZXIC_UINT32 port0_int_mask;
+} DPP_SE_RSCHD_PORT0_INT_MASK_T;
+
+typedef struct dpp_se_rschd_port1_int_en_t {
+	ZXIC_UINT32 port1_int_en;
+} DPP_SE_RSCHD_PORT1_INT_EN_T;
+
+typedef struct dpp_se_rschd_port1_int_mask_t {
+	ZXIC_UINT32 port1_int_mask;
+} DPP_SE_RSCHD_PORT1_INT_MASK_T;
+
+typedef struct dpp_se_rschd_port0_int_status_t {
+	ZXIC_UINT32 port0_int_status;
+} DPP_SE_RSCHD_PORT0_INT_STATUS_T;
+
+typedef struct dpp_se_rschd_port1_int_status_t {
+	ZXIC_UINT32 port1_int_status;
+} DPP_SE_RSCHD_PORT1_INT_STATUS_T;
+
+typedef struct dpp_se_rschd_se_rschd_int_status_t {
+	ZXIC_UINT32 port1_int_unmask_flag;
+	ZXIC_UINT32 port0_int_unmask_flag;
+} DPP_SE_RSCHD_SE_RSCHD_INT_STATUS_T;
+
+typedef struct dpp_se_rschd_debug_cnt_mode_t {
+	ZXIC_UINT32 cnt_rd_mode;
+	ZXIC_UINT32 cnt_overflow_mode;
+} DPP_SE_RSCHD_DEBUG_CNT_MODE_T;
+
+typedef struct dpp_se_rschd_se_ppu_mex0_5_rsp1_cnt_t {
+	ZXIC_UINT32 se_ppu_mex0_5_rsp1_cnt;
+} DPP_SE_RSCHD_SE_PPU_MEX0_5_RSP1_CNT_T;
+
+typedef struct dpp_se_rschd_as_rschd_rsp0_cnt_t {
+	ZXIC_UINT32 as_rschd_rsp0_cnt;
+} DPP_SE_RSCHD_AS_RSCHD_RSP0_CNT_T;
+
+typedef struct dpp_se_rschd_as_rschd_rsp1_cnt_t {
+	ZXIC_UINT32 as_rschd_rsp1_cnt;
+} DPP_SE_RSCHD_AS_RSCHD_RSP1_CNT_T;
+
+typedef struct dpp_se_rschd_as_rschd_rsp2_cnt_t {
+	ZXIC_UINT32 as_rschd_rsp2_cnt;
+} DPP_SE_RSCHD_AS_RSCHD_RSP2_CNT_T;
+
+typedef struct dpp_se_rschd_as_rschd_rsp3_cnt_t {
+	ZXIC_UINT32 as_rschd_rsp3_cnt;
+} DPP_SE_RSCHD_AS_RSCHD_RSP3_CNT_T;
+
+typedef struct dpp_se_rschd_as_rschd_rsp4_cnt_t {
+	ZXIC_UINT32 as_rschd_rsp4_cnt;
+} DPP_SE_RSCHD_AS_RSCHD_RSP4_CNT_T;
+
+typedef struct dpp_se_rschd_as_rschd_rsp5_cnt_t {
+	ZXIC_UINT32 as_rschd_rsp5_cnt;
+} DPP_SE_RSCHD_AS_RSCHD_RSP5_CNT_T;
+
+typedef struct dpp_se_rschd_as_rschd_rsp6_cnt_t {
+	ZXIC_UINT32 as_rschd_rsp6_cnt;
+} DPP_SE_RSCHD_AS_RSCHD_RSP6_CNT_T;
+
+typedef struct dpp_se_rschd_as_rschd_rsp9_cnt_t {
+	ZXIC_UINT32 as_rschd_rsp9_cnt;
+} DPP_SE_RSCHD_AS_RSCHD_RSP9_CNT_T;
+
+typedef struct dpp_se_rschd_smmu1_se_rsp0_3_cnt_t {
+	ZXIC_UINT32 smmu1_se_rsp0_3_cnt;
+} DPP_SE_RSCHD_SMMU1_SE_RSP0_3_CNT_T;
+
+typedef struct dpp_se_rschd_ppu_se_mex0_3_fc_cnt_t {
+	ZXIC_UINT32 ppu_se_mex0_3_fc_cnt;
+} DPP_SE_RSCHD_PPU_SE_MEX0_3_FC_CNT_T;
+
+typedef struct dpp_se_rschd_rschd_as_fc_cnt0_t {
+	ZXIC_UINT32 rschd_as_fc_cnt0;
+} DPP_SE_RSCHD_RSCHD_AS_FC_CNT0_T;
+
+typedef struct dpp_se_rschd_rschd_as_fc_cnt1_t {
+	ZXIC_UINT32 rschd_as_fc_cnt1;
+} DPP_SE_RSCHD_RSCHD_AS_FC_CNT1_T;
+
+typedef struct dpp_se_rschd_rschd_as_fc_cnt2_t {
+	ZXIC_UINT32 rschd_as_fc_cnt2;
+} DPP_SE_RSCHD_RSCHD_AS_FC_CNT2_T;
+
+typedef struct dpp_se_rschd_rschd_as_fc_cnt3_t {
+	ZXIC_UINT32 rschd_as_fc_cnt3;
+} DPP_SE_RSCHD_RSCHD_AS_FC_CNT3_T;
+
+typedef struct dpp_se_rschd_rschd_as_fc_cnt4_t {
+	ZXIC_UINT32 rschd_as_fc_cnt4;
+} DPP_SE_RSCHD_RSCHD_AS_FC_CNT4_T;
+
+typedef struct dpp_se_rschd_rschd_as_fc_cnt5_t {
+	ZXIC_UINT32 rschd_as_fc_cnt5;
+} DPP_SE_RSCHD_RSCHD_AS_FC_CNT5_T;
+
+typedef struct dpp_se_rschd_rschd_as_fc_cnt6_t {
+	ZXIC_UINT32 rschd_as_fc_cnt6;
+} DPP_SE_RSCHD_RSCHD_AS_FC_CNT6_T;
+
+typedef struct dpp_se_rschd_rschd_as_fc_cnt9_t {
+	ZXIC_UINT32 rschd_as_fc_cnt9;
+} DPP_SE_RSCHD_RSCHD_AS_FC_CNT9_T;
+
+typedef struct dpp_se_rschd_se_smmu1_fc0_3_cnt_t {
+	ZXIC_UINT32 se_smmu1_fc0_3_cnt;
+} DPP_SE_RSCHD_SE_SMMU1_FC0_3_CNT_T;
+
+typedef struct dpp_se_rschd_smmu0_se_wr_done_cnt_t {
+	ZXIC_UINT32 smmu0_se_wr_done_cnt;
+} DPP_SE_RSCHD_SMMU0_SE_WR_DONE_CNT_T;
+
+typedef struct dpp_se_rschd_se_smmu0_wr_done_fc_cnt_t {
+	ZXIC_UINT32 se_smmu0_wr_done_fc_cnt;
+} DPP_SE_RSCHD_SE_SMMU0_WR_DONE_FC_CNT_T;
+
+typedef struct dpp_se_rschd_smmu1_se_wr_rsp_cnt_t {
+	ZXIC_UINT32 smmu1_se_wr_rsp_cnt;
+} DPP_SE_RSCHD_SMMU1_SE_WR_RSP_CNT_T;
+
+typedef struct dpp_se_rschd_se_smmu1_wr_rsp_fc_cnt_t {
+	ZXIC_UINT32 se_smmu1_wr_rsp_fc_cnt;
+} DPP_SE_RSCHD_SE_SMMU1_WR_RSP_FC_CNT_T;
+
+typedef struct dpp_se_rschd_alg_se_wr_rsp_cnt_t {
+	ZXIC_UINT32 alg_se_wr_rsp_cnt;
+} DPP_SE_RSCHD_ALG_SE_WR_RSP_CNT_T;
+
+typedef struct dpp_se_rschd_se_alg_wr_rsp_fc_cnt_t {
+	ZXIC_UINT32 se_alg_wr_rsp_fc_cnt;
+} DPP_SE_RSCHD_SE_ALG_WR_RSP_FC_CNT_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu0_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu0_reg.h
index 08b7a46493fe8a3945cdcf63ca569702e4bcd013..6a2e79ba15a24d9a20bc9faed479abdf0efd514e 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu0_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu0_reg.h
@@ -3,6421 +3,6033 @@
 #define _DPP_SMMU0_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_smmu0_smmu0_init_done_t
-{
-    ZXIC_UINT32 init_done;
-}DPP_SMMU0_SMMU0_INIT_DONE_T;
-
-typedef struct dpp_smmu0_smmu0_cpu_ind_wdat0_t
-{
-    ZXIC_UINT32 cpu_ind_wdat0;
-}DPP_SMMU0_SMMU0_CPU_IND_WDAT0_T;
-
-typedef struct dpp_smmu0_smmu0_cpu_ind_wdat1_t
-{
-    ZXIC_UINT32 cpu_ind_wdat1;
-}DPP_SMMU0_SMMU0_CPU_IND_WDAT1_T;
-
-typedef struct dpp_smmu0_smmu0_cpu_ind_wdat2_t
-{
-    ZXIC_UINT32 cpu_ind_wdat2;
-}DPP_SMMU0_SMMU0_CPU_IND_WDAT2_T;
-
-typedef struct dpp_smmu0_smmu0_cpu_ind_wdat3_t
-{
-    ZXIC_UINT32 cpu_ind_wdat3;
-}DPP_SMMU0_SMMU0_CPU_IND_WDAT3_T;
-
-typedef struct dpp_smmu0_smmu0_cpu_ind_cmd_t
-{
-    ZXIC_UINT32 cpu_ind_rw;
-    ZXIC_UINT32 cpu_ind_rd_mode;
-    ZXIC_UINT32 cpu_req_mode;
-    ZXIC_UINT32 cpu_ind_addr;
-}DPP_SMMU0_SMMU0_CPU_IND_CMD_T;
-
-typedef struct dpp_smmu0_smmu0_cpu_ind_rd_done_t
-{
-    ZXIC_UINT32 cpu_ind_rd_done;
-}DPP_SMMU0_SMMU0_CPU_IND_RD_DONE_T;
-
-typedef struct dpp_smmu0_smmu0_cpu_ind_rdat0_t
-{
-    ZXIC_UINT32 cpu_ind_rdat0;
-}DPP_SMMU0_SMMU0_CPU_IND_RDAT0_T;
-
-typedef struct dpp_smmu0_smmu0_cpu_ind_rdat1_t
-{
-    ZXIC_UINT32 cpu_ind_rdat1;
-}DPP_SMMU0_SMMU0_CPU_IND_RDAT1_T;
-
-typedef struct dpp_smmu0_smmu0_cpu_ind_rdat2_t
-{
-    ZXIC_UINT32 cpu_ind_rdat2;
-}DPP_SMMU0_SMMU0_CPU_IND_RDAT2_T;
-
-typedef struct dpp_smmu0_smmu0_cpu_ind_rdat3_t
-{
-    ZXIC_UINT32 cpu_ind_rdat3;
-}DPP_SMMU0_SMMU0_CPU_IND_RDAT3_T;
-
-typedef struct dpp_smmu0_smmu0_cfg_plcr_mono_t
-{
-    ZXIC_UINT32 cfg_plcr_mono;
-}DPP_SMMU0_SMMU0_CFG_PLCR_MONO_T;
-
-typedef struct dpp_smmu0_smmu0_wr_arb_cpu_rdy_t
-{
-    ZXIC_UINT32 wr_arb_cpu_rdy;
-}DPP_SMMU0_SMMU0_WR_ARB_CPU_RDY_T;
-
-typedef struct dpp_smmu0_smmu0_tm_stat_en_cfg_t
-{
-    ZXIC_UINT32 tm_stat_en_cfg;
-}DPP_SMMU0_SMMU0_TM_STAT_EN_CFG_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_pful_cfg0_t
-{
-    ZXIC_UINT32 kschd_pful_assert0_1;
-    ZXIC_UINT32 kschd_pful_negate0_1;
-    ZXIC_UINT32 kschd_pful_assert0_0;
-    ZXIC_UINT32 kschd_pful_negate0_0;
-}DPP_SMMU0_SMMU0_KSCHD_PFUL_CFG0_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_pful_cfg1_t
-{
-    ZXIC_UINT32 kschd_pful_assert1_1;
-    ZXIC_UINT32 kschd_pful_negate1_1;
-    ZXIC_UINT32 kschd_pful_assert1_0;
-    ZXIC_UINT32 kschd_pful_negate1_0;
-}DPP_SMMU0_SMMU0_KSCHD_PFUL_CFG1_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl_pful1_cfg_t
-{
-    ZXIC_UINT32 ctrl_pful1_assert;
-    ZXIC_UINT32 ctrl_pful1_negate;
-}DPP_SMMU0_SMMU0_CTRL_PFUL1_CFG_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl_pful2_cfg_t
-{
-    ZXIC_UINT32 ctrl_pful2_assert;
-    ZXIC_UINT32 ctrl_pful2_negate;
-}DPP_SMMU0_SMMU0_CTRL_PFUL2_CFG_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl_pful3_cfg_t
-{
-    ZXIC_UINT32 ctrl_pful3_assert;
-    ZXIC_UINT32 ctrl_pful3_negate;
-}DPP_SMMU0_SMMU0_CTRL_PFUL3_CFG_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_pful_cfg_t
-{
-    ZXIC_UINT32 rschd_pful_assert;
-    ZXIC_UINT32 rschd_pful_negate;
-}DPP_SMMU0_SMMU0_RSCHD_PFUL_CFG_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_ept_cfg_t
-{
-    ZXIC_UINT32 rschd_ept_assert;
-    ZXIC_UINT32 rschd_ept_negate;
-}DPP_SMMU0_SMMU0_RSCHD_EPT_CFG_T;
-
-typedef struct dpp_smmu0_smmu0_alucmd_pful_cfg_t
-{
-    ZXIC_UINT32 alucmd_pful_assert;
-    ZXIC_UINT32 alucmd_pful_negate;
-}DPP_SMMU0_SMMU0_ALUCMD_PFUL_CFG_T;
-
-typedef struct dpp_smmu0_smmu0_aluwr_pful_cfg_t
-{
-    ZXIC_UINT32 aluwr_pful_assert;
-    ZXIC_UINT32 aluwr_pful_negate;
-}DPP_SMMU0_SMMU0_ALUWR_PFUL_CFG_T;
-
-typedef struct dpp_smmu0_smmu0_wr_arb_pful_cfg0_t
-{
-    ZXIC_UINT32 wr_arb_pful0_assert;
-    ZXIC_UINT32 wr_arb_pful0_negate;
-}DPP_SMMU0_SMMU0_WR_ARB_PFUL_CFG0_T;
-
-typedef struct dpp_smmu0_smmu0_wr_arb_pful_cfg1_t
-{
-    ZXIC_UINT32 wr_arb_pful1_assert;
-    ZXIC_UINT32 wr_arb_pful1_negate;
-}DPP_SMMU0_SMMU0_WR_ARB_PFUL_CFG1_T;
-
-typedef struct dpp_smmu0_smmu0_ord_pful_cfg_t
-{
-    ZXIC_UINT32 ord_pful_assert;
-    ZXIC_UINT32 ord_pful_negate;
-}DPP_SMMU0_SMMU0_ORD_PFUL_CFG_T;
-
-typedef struct dpp_smmu0_smmu0_cfg_dma_baddr_t
-{
-    ZXIC_UINT32 cfg_dma_baddr;
-}DPP_SMMU0_SMMU0_CFG_DMA_BADDR_T;
-
-typedef struct dpp_smmu0_smmu0_cfg_odma0_baddr_t
-{
-    ZXIC_UINT32 cfg_odma0_baddr;
-}DPP_SMMU0_SMMU0_CFG_ODMA0_BADDR_T;
-
-typedef struct dpp_smmu0_smmu0_cfg_odma1_baddr_t
-{
-    ZXIC_UINT32 cfg_odma1_baddr;
-}DPP_SMMU0_SMMU0_CFG_ODMA1_BADDR_T;
-
-typedef struct dpp_smmu0_smmu0_cfg_odma2_baddr_t
-{
-    ZXIC_UINT32 cfg_odma2_baddr;
-}DPP_SMMU0_SMMU0_CFG_ODMA2_BADDR_T;
-
-typedef struct dpp_smmu0_smmu0_cfg_odma_tdm_baddr_t
-{
-    ZXIC_UINT32 cfg_odma_tdm_baddr;
-}DPP_SMMU0_SMMU0_CFG_ODMA_TDM_BADDR_T;
-
-typedef struct dpp_smmu0_smmu0_cfg_mcast_baddr_t
-{
-    ZXIC_UINT32 cfg_mcast_baddr;
-}DPP_SMMU0_SMMU0_CFG_MCAST_BADDR_T;
-
-typedef struct dpp_smmu0_smmu0_cfg_lpm0_t
-{
-    ZXIC_UINT32 lpm0_rsp_mode;
-    ZXIC_UINT32 lpm0_baddr;
-}DPP_SMMU0_SMMU0_CFG_LPM0_T;
-
-typedef struct dpp_smmu0_smmu0_cfg_lpm1_t
-{
-    ZXIC_UINT32 lpm1_rsp_mode;
-    ZXIC_UINT32 lpm1_baddr;
-}DPP_SMMU0_SMMU0_CFG_LPM1_T;
-
-typedef struct dpp_smmu0_smmu0_cfg_lpm2_t
-{
-    ZXIC_UINT32 lpm2_rsp_mode;
-    ZXIC_UINT32 lpm2_baddr;
-}DPP_SMMU0_SMMU0_CFG_LPM2_T;
-
-typedef struct dpp_smmu0_smmu0_cfg_lpm3_t
-{
-    ZXIC_UINT32 lpm3_rsp_mode;
-    ZXIC_UINT32 lpm3_baddr;
-}DPP_SMMU0_SMMU0_CFG_LPM3_T;
-
-typedef struct dpp_smmu0_smmu0_cfg_lpm4_t
-{
-    ZXIC_UINT32 lpm4_rsp_mode;
-    ZXIC_UINT32 lpm4_baddr;
-}DPP_SMMU0_SMMU0_CFG_LPM4_T;
-
-typedef struct dpp_smmu0_smmu0_cfg_lpm5_t
-{
-    ZXIC_UINT32 lpm5_rsp_mode;
-    ZXIC_UINT32 lpm5_baddr;
-}DPP_SMMU0_SMMU0_CFG_LPM5_T;
-
-typedef struct dpp_smmu0_smmu0_cfg_lpm6_t
-{
-    ZXIC_UINT32 lpm6_rsp_mode;
-    ZXIC_UINT32 lpm6_baddr;
-}DPP_SMMU0_SMMU0_CFG_LPM6_T;
-
-typedef struct dpp_smmu0_smmu0_cfg_lpm7_t
-{
-    ZXIC_UINT32 lpm7_rsp_mode;
-    ZXIC_UINT32 lpm7_baddr;
-}DPP_SMMU0_SMMU0_CFG_LPM7_T;
-
-typedef struct dpp_smmu0_smmu0_debug_cnt_mode_t
-{
-    ZXIC_UINT32 cnt_rd_mode;
-    ZXIC_UINT32 cnt_overflow_mode;
-}DPP_SMMU0_SMMU0_DEBUG_CNT_MODE_T;
-
-typedef struct dpp_smmu0_smmu0_stat_overflow_mode_t
-{
-    ZXIC_UINT32 stat_overflow_mode;
-}DPP_SMMU0_SMMU0_STAT_OVERFLOW_MODE_T;
-
-typedef struct dpp_smmu0_smmu0_init_en_cfg_tmp_t
-{
-    ZXIC_UINT32 init_en_cfg_tmp31;
-    ZXIC_UINT32 init_en_cfg_tmp30;
-    ZXIC_UINT32 init_en_cfg_tmp29;
-    ZXIC_UINT32 init_en_cfg_tmp28;
-    ZXIC_UINT32 init_en_cfg_tmp27;
-    ZXIC_UINT32 init_en_cfg_tmp26;
-    ZXIC_UINT32 init_en_cfg_tmp25;
-    ZXIC_UINT32 init_en_cfg_tmp24;
-    ZXIC_UINT32 init_en_cfg_tmp23;
-    ZXIC_UINT32 init_en_cfg_tmp22;
-    ZXIC_UINT32 init_en_cfg_tmp21;
-    ZXIC_UINT32 init_en_cfg_tmp20;
-    ZXIC_UINT32 init_en_cfg_tmp19;
-    ZXIC_UINT32 init_en_cfg_tmp18;
-    ZXIC_UINT32 init_en_cfg_tmp17;
-    ZXIC_UINT32 init_en_cfg_tmp16;
-    ZXIC_UINT32 init_en_cfg_tmp15;
-    ZXIC_UINT32 init_en_cfg_tmp14;
-    ZXIC_UINT32 init_en_cfg_tmp13;
-    ZXIC_UINT32 init_en_cfg_tmp12;
-    ZXIC_UINT32 init_en_cfg_tmp11;
-    ZXIC_UINT32 init_en_cfg_tmp10;
-    ZXIC_UINT32 init_en_cfg_tmp9;
-    ZXIC_UINT32 init_en_cfg_tmp8;
-    ZXIC_UINT32 init_en_cfg_tmp7;
-    ZXIC_UINT32 init_en_cfg_tmp6;
-    ZXIC_UINT32 init_en_cfg_tmp5;
-    ZXIC_UINT32 init_en_cfg_tmp4;
-    ZXIC_UINT32 init_en_cfg_tmp3;
-    ZXIC_UINT32 init_en_cfg_tmp2;
-    ZXIC_UINT32 init_en_cfg_tmp1;
-    ZXIC_UINT32 init_en_cfg_tmp0;
-}DPP_SMMU0_SMMU0_INIT_EN_CFG_TMP_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int_unmask_flag_t
-{
-    ZXIC_UINT32 smmu0_int0_31_unmask_flag;
-}DPP_SMMU0_SMMU0_SMMU0_INT_UNMASK_FLAG_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int0_en_t
-{
-    ZXIC_UINT32 smmu0_int0_en31;
-    ZXIC_UINT32 smmu0_int0_en30;
-    ZXIC_UINT32 smmu0_int0_en29;
-    ZXIC_UINT32 smmu0_int0_en28;
-    ZXIC_UINT32 smmu0_int0_en27;
-    ZXIC_UINT32 smmu0_int0_en26;
-    ZXIC_UINT32 smmu0_int0_en25;
-    ZXIC_UINT32 smmu0_int0_en24;
-    ZXIC_UINT32 smmu0_int0_en23;
-    ZXIC_UINT32 smmu0_int0_en22;
-    ZXIC_UINT32 smmu0_int0_en21;
-    ZXIC_UINT32 smmu0_int0_en20;
-    ZXIC_UINT32 smmu0_int0_en19;
-    ZXIC_UINT32 smmu0_int0_en18;
-    ZXIC_UINT32 smmu0_int0_en17;
-    ZXIC_UINT32 smmu0_int0_en16;
-    ZXIC_UINT32 smmu0_int0_en15;
-    ZXIC_UINT32 smmu0_int0_en14;
-    ZXIC_UINT32 smmu0_int0_en13;
-    ZXIC_UINT32 smmu0_int0_en12;
-    ZXIC_UINT32 smmu0_int0_en11;
-    ZXIC_UINT32 smmu0_int0_en10;
-    ZXIC_UINT32 smmu0_int0_en9;
-    ZXIC_UINT32 smmu0_int0_en8;
-    ZXIC_UINT32 smmu0_int0_en7;
-    ZXIC_UINT32 smmu0_int0_en6;
-    ZXIC_UINT32 smmu0_int0_en5;
-    ZXIC_UINT32 smmu0_int0_en4;
-    ZXIC_UINT32 smmu0_int0_en3;
-    ZXIC_UINT32 smmu0_int0_en2;
-    ZXIC_UINT32 smmu0_int0_en1;
-    ZXIC_UINT32 smmu0_int0_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT0_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int0_mask_t
-{
-    ZXIC_UINT32 smmu0_int0_mask31;
-    ZXIC_UINT32 smmu0_int0_mask30;
-    ZXIC_UINT32 smmu0_int0_mask29;
-    ZXIC_UINT32 smmu0_int0_mask28;
-    ZXIC_UINT32 smmu0_int0_mask27;
-    ZXIC_UINT32 smmu0_int0_mask26;
-    ZXIC_UINT32 smmu0_int0_mask25;
-    ZXIC_UINT32 smmu0_int0_mask24;
-    ZXIC_UINT32 smmu0_int0_mask23;
-    ZXIC_UINT32 smmu0_int0_mask22;
-    ZXIC_UINT32 smmu0_int0_mask21;
-    ZXIC_UINT32 smmu0_int0_mask20;
-    ZXIC_UINT32 smmu0_int0_mask19;
-    ZXIC_UINT32 smmu0_int0_mask18;
-    ZXIC_UINT32 smmu0_int0_mask17;
-    ZXIC_UINT32 smmu0_int0_mask16;
-    ZXIC_UINT32 smmu0_int0_mask15;
-    ZXIC_UINT32 smmu0_int0_mask14;
-    ZXIC_UINT32 smmu0_int0_mask13;
-    ZXIC_UINT32 smmu0_int0_mask12;
-    ZXIC_UINT32 smmu0_int0_mask11;
-    ZXIC_UINT32 smmu0_int0_mask10;
-    ZXIC_UINT32 smmu0_int0_mask9;
-    ZXIC_UINT32 smmu0_int0_mask8;
-    ZXIC_UINT32 smmu0_int0_mask7;
-    ZXIC_UINT32 smmu0_int0_mask6;
-    ZXIC_UINT32 smmu0_int0_mask5;
-    ZXIC_UINT32 smmu0_int0_mask4;
-    ZXIC_UINT32 smmu0_int0_mask3;
-    ZXIC_UINT32 smmu0_int0_mask2;
-    ZXIC_UINT32 smmu0_int0_mask1;
-    ZXIC_UINT32 smmu0_int0_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT0_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int0_status_t
-{
-    ZXIC_UINT32 smmu0_int0_status31;
-    ZXIC_UINT32 smmu0_int0_status30;
-    ZXIC_UINT32 smmu0_int0_status29;
-    ZXIC_UINT32 smmu0_int0_status28;
-    ZXIC_UINT32 smmu0_int0_status27;
-    ZXIC_UINT32 smmu0_int0_status26;
-    ZXIC_UINT32 smmu0_int0_status25;
-    ZXIC_UINT32 smmu0_int0_status24;
-    ZXIC_UINT32 smmu0_int0_status23;
-    ZXIC_UINT32 smmu0_int0_status22;
-    ZXIC_UINT32 smmu0_int0_status21;
-    ZXIC_UINT32 smmu0_int0_status20;
-    ZXIC_UINT32 smmu0_int0_status19;
-    ZXIC_UINT32 smmu0_int0_status18;
-    ZXIC_UINT32 smmu0_int0_status17;
-    ZXIC_UINT32 smmu0_int0_status16;
-    ZXIC_UINT32 smmu0_int0_status15;
-    ZXIC_UINT32 smmu0_int0_status14;
-    ZXIC_UINT32 smmu0_int0_status13;
-    ZXIC_UINT32 smmu0_int0_status12;
-    ZXIC_UINT32 smmu0_int0_status11;
-    ZXIC_UINT32 smmu0_int0_status10;
-    ZXIC_UINT32 smmu0_int0_status9;
-    ZXIC_UINT32 smmu0_int0_status8;
-    ZXIC_UINT32 smmu0_int0_status7;
-    ZXIC_UINT32 smmu0_int0_status6;
-    ZXIC_UINT32 smmu0_int0_status5;
-    ZXIC_UINT32 smmu0_int0_status4;
-    ZXIC_UINT32 smmu0_int0_status3;
-    ZXIC_UINT32 smmu0_int0_status2;
-    ZXIC_UINT32 smmu0_int0_status1;
-    ZXIC_UINT32 smmu0_int0_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT0_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int1_en_t
-{
-    ZXIC_UINT32 smmu0_int1_en31;
-    ZXIC_UINT32 smmu0_int1_en30;
-    ZXIC_UINT32 smmu0_int1_en29;
-    ZXIC_UINT32 smmu0_int1_en28;
-    ZXIC_UINT32 smmu0_int1_en27;
-    ZXIC_UINT32 smmu0_int1_en26;
-    ZXIC_UINT32 smmu0_int1_en25;
-    ZXIC_UINT32 smmu0_int1_en24;
-    ZXIC_UINT32 smmu0_int1_en23;
-    ZXIC_UINT32 smmu0_int1_en22;
-    ZXIC_UINT32 smmu0_int1_en21;
-    ZXIC_UINT32 smmu0_int1_en20;
-    ZXIC_UINT32 smmu0_int1_en19;
-    ZXIC_UINT32 smmu0_int1_en18;
-    ZXIC_UINT32 smmu0_int1_en17;
-    ZXIC_UINT32 smmu0_int1_en16;
-    ZXIC_UINT32 smmu0_int1_en15;
-    ZXIC_UINT32 smmu0_int1_en14;
-    ZXIC_UINT32 smmu0_int1_en13;
-    ZXIC_UINT32 smmu0_int1_en12;
-    ZXIC_UINT32 smmu0_int1_en11;
-    ZXIC_UINT32 smmu0_int1_en10;
-    ZXIC_UINT32 smmu0_int1_en9;
-    ZXIC_UINT32 smmu0_int1_en8;
-    ZXIC_UINT32 smmu0_int1_en7;
-    ZXIC_UINT32 smmu0_int1_en6;
-    ZXIC_UINT32 smmu0_int1_en5;
-    ZXIC_UINT32 smmu0_int1_en4;
-    ZXIC_UINT32 smmu0_int1_en3;
-    ZXIC_UINT32 smmu0_int1_en2;
-    ZXIC_UINT32 smmu0_int1_en1;
-    ZXIC_UINT32 smmu0_int1_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT1_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int1_mask_t
-{
-    ZXIC_UINT32 smmu0_int1_mask31;
-    ZXIC_UINT32 smmu0_int1_mask30;
-    ZXIC_UINT32 smmu0_int1_mask29;
-    ZXIC_UINT32 smmu0_int1_mask28;
-    ZXIC_UINT32 smmu0_int1_mask27;
-    ZXIC_UINT32 smmu0_int1_mask26;
-    ZXIC_UINT32 smmu0_int1_mask25;
-    ZXIC_UINT32 smmu0_int1_mask24;
-    ZXIC_UINT32 smmu0_int1_mask23;
-    ZXIC_UINT32 smmu0_int1_mask22;
-    ZXIC_UINT32 smmu0_int1_mask21;
-    ZXIC_UINT32 smmu0_int1_mask20;
-    ZXIC_UINT32 smmu0_int1_mask19;
-    ZXIC_UINT32 smmu0_int1_mask18;
-    ZXIC_UINT32 smmu0_int1_mask17;
-    ZXIC_UINT32 smmu0_int1_mask16;
-    ZXIC_UINT32 smmu0_int1_mask15;
-    ZXIC_UINT32 smmu0_int1_mask14;
-    ZXIC_UINT32 smmu0_int1_mask13;
-    ZXIC_UINT32 smmu0_int1_mask12;
-    ZXIC_UINT32 smmu0_int1_mask11;
-    ZXIC_UINT32 smmu0_int1_mask10;
-    ZXIC_UINT32 smmu0_int1_mask9;
-    ZXIC_UINT32 smmu0_int1_mask8;
-    ZXIC_UINT32 smmu0_int1_mask7;
-    ZXIC_UINT32 smmu0_int1_mask6;
-    ZXIC_UINT32 smmu0_int1_mask5;
-    ZXIC_UINT32 smmu0_int1_mask4;
-    ZXIC_UINT32 smmu0_int1_mask3;
-    ZXIC_UINT32 smmu0_int1_mask2;
-    ZXIC_UINT32 smmu0_int1_mask1;
-    ZXIC_UINT32 smmu0_int1_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT1_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int1_status_t
-{
-    ZXIC_UINT32 smmu0_int1_status31;
-    ZXIC_UINT32 smmu0_int1_status30;
-    ZXIC_UINT32 smmu0_int1_status29;
-    ZXIC_UINT32 smmu0_int1_status28;
-    ZXIC_UINT32 smmu0_int1_status27;
-    ZXIC_UINT32 smmu0_int1_status26;
-    ZXIC_UINT32 smmu0_int1_status25;
-    ZXIC_UINT32 smmu0_int1_status24;
-    ZXIC_UINT32 smmu0_int1_status23;
-    ZXIC_UINT32 smmu0_int1_status22;
-    ZXIC_UINT32 smmu0_int1_status21;
-    ZXIC_UINT32 smmu0_int1_status20;
-    ZXIC_UINT32 smmu0_int1_status19;
-    ZXIC_UINT32 smmu0_int1_status18;
-    ZXIC_UINT32 smmu0_int1_status17;
-    ZXIC_UINT32 smmu0_int1_status16;
-    ZXIC_UINT32 smmu0_int1_status15;
-    ZXIC_UINT32 smmu0_int1_status14;
-    ZXIC_UINT32 smmu0_int1_status13;
-    ZXIC_UINT32 smmu0_int1_status12;
-    ZXIC_UINT32 smmu0_int1_status11;
-    ZXIC_UINT32 smmu0_int1_status10;
-    ZXIC_UINT32 smmu0_int1_status9;
-    ZXIC_UINT32 smmu0_int1_status8;
-    ZXIC_UINT32 smmu0_int1_status7;
-    ZXIC_UINT32 smmu0_int1_status6;
-    ZXIC_UINT32 smmu0_int1_status5;
-    ZXIC_UINT32 smmu0_int1_status4;
-    ZXIC_UINT32 smmu0_int1_status3;
-    ZXIC_UINT32 smmu0_int1_status2;
-    ZXIC_UINT32 smmu0_int1_status1;
-    ZXIC_UINT32 smmu0_int1_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT1_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int2_en_t
-{
-    ZXIC_UINT32 smmu0_int2_en31;
-    ZXIC_UINT32 smmu0_int2_en30;
-    ZXIC_UINT32 smmu0_int2_en29;
-    ZXIC_UINT32 smmu0_int2_en28;
-    ZXIC_UINT32 smmu0_int2_en27;
-    ZXIC_UINT32 smmu0_int2_en26;
-    ZXIC_UINT32 smmu0_int2_en25;
-    ZXIC_UINT32 smmu0_int2_en24;
-    ZXIC_UINT32 smmu0_int2_en23;
-    ZXIC_UINT32 smmu0_int2_en22;
-    ZXIC_UINT32 smmu0_int2_en21;
-    ZXIC_UINT32 smmu0_int2_en20;
-    ZXIC_UINT32 smmu0_int2_en19;
-    ZXIC_UINT32 smmu0_int2_en18;
-    ZXIC_UINT32 smmu0_int2_en17;
-    ZXIC_UINT32 smmu0_int2_en16;
-    ZXIC_UINT32 smmu0_int2_en15;
-    ZXIC_UINT32 smmu0_int2_en14;
-    ZXIC_UINT32 smmu0_int2_en13;
-    ZXIC_UINT32 smmu0_int2_en12;
-    ZXIC_UINT32 smmu0_int2_en11;
-    ZXIC_UINT32 smmu0_int2_en10;
-    ZXIC_UINT32 smmu0_int2_en9;
-    ZXIC_UINT32 smmu0_int2_en8;
-    ZXIC_UINT32 smmu0_int2_en7;
-    ZXIC_UINT32 smmu0_int2_en6;
-    ZXIC_UINT32 smmu0_int2_en5;
-    ZXIC_UINT32 smmu0_int2_en4;
-    ZXIC_UINT32 smmu0_int2_en3;
-    ZXIC_UINT32 smmu0_int2_en2;
-    ZXIC_UINT32 smmu0_int2_en1;
-    ZXIC_UINT32 smmu0_int2_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT2_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int2_mask_t
-{
-    ZXIC_UINT32 smmu0_int2_mask31;
-    ZXIC_UINT32 smmu0_int2_mask30;
-    ZXIC_UINT32 smmu0_int2_mask29;
-    ZXIC_UINT32 smmu0_int2_mask28;
-    ZXIC_UINT32 smmu0_int2_mask27;
-    ZXIC_UINT32 smmu0_int2_mask26;
-    ZXIC_UINT32 smmu0_int2_mask25;
-    ZXIC_UINT32 smmu0_int2_mask24;
-    ZXIC_UINT32 smmu0_int2_mask23;
-    ZXIC_UINT32 smmu0_int2_mask22;
-    ZXIC_UINT32 smmu0_int2_mask21;
-    ZXIC_UINT32 smmu0_int2_mask20;
-    ZXIC_UINT32 smmu0_int2_mask19;
-    ZXIC_UINT32 smmu0_int2_mask18;
-    ZXIC_UINT32 smmu0_int2_mask17;
-    ZXIC_UINT32 smmu0_int2_mask16;
-    ZXIC_UINT32 smmu0_int2_mask15;
-    ZXIC_UINT32 smmu0_int2_mask14;
-    ZXIC_UINT32 smmu0_int2_mask13;
-    ZXIC_UINT32 smmu0_int2_mask12;
-    ZXIC_UINT32 smmu0_int2_mask11;
-    ZXIC_UINT32 smmu0_int2_mask10;
-    ZXIC_UINT32 smmu0_int2_mask9;
-    ZXIC_UINT32 smmu0_int2_mask8;
-    ZXIC_UINT32 smmu0_int2_mask7;
-    ZXIC_UINT32 smmu0_int2_mask6;
-    ZXIC_UINT32 smmu0_int2_mask5;
-    ZXIC_UINT32 smmu0_int2_mask4;
-    ZXIC_UINT32 smmu0_int2_mask3;
-    ZXIC_UINT32 smmu0_int2_mask2;
-    ZXIC_UINT32 smmu0_int2_mask1;
-    ZXIC_UINT32 smmu0_int2_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT2_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int2_status_t
-{
-    ZXIC_UINT32 smmu0_int2_status31;
-    ZXIC_UINT32 smmu0_int2_status30;
-    ZXIC_UINT32 smmu0_int2_status29;
-    ZXIC_UINT32 smmu0_int2_status28;
-    ZXIC_UINT32 smmu0_int2_status27;
-    ZXIC_UINT32 smmu0_int2_status26;
-    ZXIC_UINT32 smmu0_int2_status25;
-    ZXIC_UINT32 smmu0_int2_status24;
-    ZXIC_UINT32 smmu0_int2_status23;
-    ZXIC_UINT32 smmu0_int2_status22;
-    ZXIC_UINT32 smmu0_int2_status21;
-    ZXIC_UINT32 smmu0_int2_status20;
-    ZXIC_UINT32 smmu0_int2_status19;
-    ZXIC_UINT32 smmu0_int2_status18;
-    ZXIC_UINT32 smmu0_int2_status17;
-    ZXIC_UINT32 smmu0_int2_status16;
-    ZXIC_UINT32 smmu0_int2_status15;
-    ZXIC_UINT32 smmu0_int2_status14;
-    ZXIC_UINT32 smmu0_int2_status13;
-    ZXIC_UINT32 smmu0_int2_status12;
-    ZXIC_UINT32 smmu0_int2_status11;
-    ZXIC_UINT32 smmu0_int2_status10;
-    ZXIC_UINT32 smmu0_int2_status9;
-    ZXIC_UINT32 smmu0_int2_status8;
-    ZXIC_UINT32 smmu0_int2_status7;
-    ZXIC_UINT32 smmu0_int2_status6;
-    ZXIC_UINT32 smmu0_int2_status5;
-    ZXIC_UINT32 smmu0_int2_status4;
-    ZXIC_UINT32 smmu0_int2_status3;
-    ZXIC_UINT32 smmu0_int2_status2;
-    ZXIC_UINT32 smmu0_int2_status1;
-    ZXIC_UINT32 smmu0_int2_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT2_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int3_en_t
-{
-    ZXIC_UINT32 smmu0_int3_en31;
-    ZXIC_UINT32 smmu0_int3_en30;
-    ZXIC_UINT32 smmu0_int3_en29;
-    ZXIC_UINT32 smmu0_int3_en28;
-    ZXIC_UINT32 smmu0_int3_en27;
-    ZXIC_UINT32 smmu0_int3_en26;
-    ZXIC_UINT32 smmu0_int3_en25;
-    ZXIC_UINT32 smmu0_int3_en24;
-    ZXIC_UINT32 smmu0_int3_en23;
-    ZXIC_UINT32 smmu0_int3_en22;
-    ZXIC_UINT32 smmu0_int3_en21;
-    ZXIC_UINT32 smmu0_int3_en20;
-    ZXIC_UINT32 smmu0_int3_en19;
-    ZXIC_UINT32 smmu0_int3_en18;
-    ZXIC_UINT32 smmu0_int3_en17;
-    ZXIC_UINT32 smmu0_int3_en16;
-    ZXIC_UINT32 smmu0_int3_en15;
-    ZXIC_UINT32 smmu0_int3_en14;
-    ZXIC_UINT32 smmu0_int3_en13;
-    ZXIC_UINT32 smmu0_int3_en12;
-    ZXIC_UINT32 smmu0_int3_en11;
-    ZXIC_UINT32 smmu0_int3_en10;
-    ZXIC_UINT32 smmu0_int3_en9;
-    ZXIC_UINT32 smmu0_int3_en8;
-    ZXIC_UINT32 smmu0_int3_en7;
-    ZXIC_UINT32 smmu0_int3_en6;
-    ZXIC_UINT32 smmu0_int3_en5;
-    ZXIC_UINT32 smmu0_int3_en4;
-    ZXIC_UINT32 smmu0_int3_en3;
-    ZXIC_UINT32 smmu0_int3_en2;
-    ZXIC_UINT32 smmu0_int3_en1;
-    ZXIC_UINT32 smmu0_int3_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT3_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int3_mask_t
-{
-    ZXIC_UINT32 smmu0_int3_mask31;
-    ZXIC_UINT32 smmu0_int3_mask30;
-    ZXIC_UINT32 smmu0_int3_mask29;
-    ZXIC_UINT32 smmu0_int3_mask28;
-    ZXIC_UINT32 smmu0_int3_mask27;
-    ZXIC_UINT32 smmu0_int3_mask26;
-    ZXIC_UINT32 smmu0_int3_mask25;
-    ZXIC_UINT32 smmu0_int3_mask24;
-    ZXIC_UINT32 smmu0_int3_mask23;
-    ZXIC_UINT32 smmu0_int3_mask22;
-    ZXIC_UINT32 smmu0_int3_mask21;
-    ZXIC_UINT32 smmu0_int3_mask20;
-    ZXIC_UINT32 smmu0_int3_mask19;
-    ZXIC_UINT32 smmu0_int3_mask18;
-    ZXIC_UINT32 smmu0_int3_mask17;
-    ZXIC_UINT32 smmu0_int3_mask16;
-    ZXIC_UINT32 smmu0_int3_mask15;
-    ZXIC_UINT32 smmu0_int3_mask14;
-    ZXIC_UINT32 smmu0_int3_mask13;
-    ZXIC_UINT32 smmu0_int3_mask12;
-    ZXIC_UINT32 smmu0_int3_mask11;
-    ZXIC_UINT32 smmu0_int3_mask10;
-    ZXIC_UINT32 smmu0_int3_mask9;
-    ZXIC_UINT32 smmu0_int3_mask8;
-    ZXIC_UINT32 smmu0_int3_mask7;
-    ZXIC_UINT32 smmu0_int3_mask6;
-    ZXIC_UINT32 smmu0_int3_mask5;
-    ZXIC_UINT32 smmu0_int3_mask4;
-    ZXIC_UINT32 smmu0_int3_mask3;
-    ZXIC_UINT32 smmu0_int3_mask2;
-    ZXIC_UINT32 smmu0_int3_mask1;
-    ZXIC_UINT32 smmu0_int3_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT3_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int3_status_t
-{
-    ZXIC_UINT32 smmu0_int3_status31;
-    ZXIC_UINT32 smmu0_int3_status30;
-    ZXIC_UINT32 smmu0_int3_status29;
-    ZXIC_UINT32 smmu0_int3_status28;
-    ZXIC_UINT32 smmu0_int3_status27;
-    ZXIC_UINT32 smmu0_int3_status26;
-    ZXIC_UINT32 smmu0_int3_status25;
-    ZXIC_UINT32 smmu0_int3_status24;
-    ZXIC_UINT32 smmu0_int3_status23;
-    ZXIC_UINT32 smmu0_int3_status22;
-    ZXIC_UINT32 smmu0_int3_status21;
-    ZXIC_UINT32 smmu0_int3_status20;
-    ZXIC_UINT32 smmu0_int3_status19;
-    ZXIC_UINT32 smmu0_int3_status18;
-    ZXIC_UINT32 smmu0_int3_status17;
-    ZXIC_UINT32 smmu0_int3_status16;
-    ZXIC_UINT32 smmu0_int3_status15;
-    ZXIC_UINT32 smmu0_int3_status14;
-    ZXIC_UINT32 smmu0_int3_status13;
-    ZXIC_UINT32 smmu0_int3_status12;
-    ZXIC_UINT32 smmu0_int3_status11;
-    ZXIC_UINT32 smmu0_int3_status10;
-    ZXIC_UINT32 smmu0_int3_status9;
-    ZXIC_UINT32 smmu0_int3_status8;
-    ZXIC_UINT32 smmu0_int3_status7;
-    ZXIC_UINT32 smmu0_int3_status6;
-    ZXIC_UINT32 smmu0_int3_status5;
-    ZXIC_UINT32 smmu0_int3_status4;
-    ZXIC_UINT32 smmu0_int3_status3;
-    ZXIC_UINT32 smmu0_int3_status2;
-    ZXIC_UINT32 smmu0_int3_status1;
-    ZXIC_UINT32 smmu0_int3_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT3_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int4_en_t
-{
-    ZXIC_UINT32 smmu0_int4_en31;
-    ZXIC_UINT32 smmu0_int4_en30;
-    ZXIC_UINT32 smmu0_int4_en29;
-    ZXIC_UINT32 smmu0_int4_en28;
-    ZXIC_UINT32 smmu0_int4_en27;
-    ZXIC_UINT32 smmu0_int4_en26;
-    ZXIC_UINT32 smmu0_int4_en25;
-    ZXIC_UINT32 smmu0_int4_en24;
-    ZXIC_UINT32 smmu0_int4_en23;
-    ZXIC_UINT32 smmu0_int4_en22;
-    ZXIC_UINT32 smmu0_int4_en21;
-    ZXIC_UINT32 smmu0_int4_en20;
-    ZXIC_UINT32 smmu0_int4_en19;
-    ZXIC_UINT32 smmu0_int4_en18;
-    ZXIC_UINT32 smmu0_int4_en17;
-    ZXIC_UINT32 smmu0_int4_en16;
-    ZXIC_UINT32 smmu0_int4_en15;
-    ZXIC_UINT32 smmu0_int4_en14;
-    ZXIC_UINT32 smmu0_int4_en13;
-    ZXIC_UINT32 smmu0_int4_en12;
-    ZXIC_UINT32 smmu0_int4_en11;
-    ZXIC_UINT32 smmu0_int4_en10;
-    ZXIC_UINT32 smmu0_int4_en9;
-    ZXIC_UINT32 smmu0_int4_en8;
-    ZXIC_UINT32 smmu0_int4_en7;
-    ZXIC_UINT32 smmu0_int4_en6;
-    ZXIC_UINT32 smmu0_int4_en5;
-    ZXIC_UINT32 smmu0_int4_en4;
-    ZXIC_UINT32 smmu0_int4_en3;
-    ZXIC_UINT32 smmu0_int4_en2;
-    ZXIC_UINT32 smmu0_int4_en1;
-    ZXIC_UINT32 smmu0_int4_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT4_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int4_mask_t
-{
-    ZXIC_UINT32 smmu0_int4_mask31;
-    ZXIC_UINT32 smmu0_int4_mask30;
-    ZXIC_UINT32 smmu0_int4_mask29;
-    ZXIC_UINT32 smmu0_int4_mask28;
-    ZXIC_UINT32 smmu0_int4_mask27;
-    ZXIC_UINT32 smmu0_int4_mask26;
-    ZXIC_UINT32 smmu0_int4_mask25;
-    ZXIC_UINT32 smmu0_int4_mask24;
-    ZXIC_UINT32 smmu0_int4_mask23;
-    ZXIC_UINT32 smmu0_int4_mask22;
-    ZXIC_UINT32 smmu0_int4_mask21;
-    ZXIC_UINT32 smmu0_int4_mask20;
-    ZXIC_UINT32 smmu0_int4_mask19;
-    ZXIC_UINT32 smmu0_int4_mask18;
-    ZXIC_UINT32 smmu0_int4_mask17;
-    ZXIC_UINT32 smmu0_int4_mask16;
-    ZXIC_UINT32 smmu0_int4_mask15;
-    ZXIC_UINT32 smmu0_int4_mask14;
-    ZXIC_UINT32 smmu0_int4_mask13;
-    ZXIC_UINT32 smmu0_int4_mask12;
-    ZXIC_UINT32 smmu0_int4_mask11;
-    ZXIC_UINT32 smmu0_int4_mask10;
-    ZXIC_UINT32 smmu0_int4_mask9;
-    ZXIC_UINT32 smmu0_int4_mask8;
-    ZXIC_UINT32 smmu0_int4_mask7;
-    ZXIC_UINT32 smmu0_int4_mask6;
-    ZXIC_UINT32 smmu0_int4_mask5;
-    ZXIC_UINT32 smmu0_int4_mask4;
-    ZXIC_UINT32 smmu0_int4_mask3;
-    ZXIC_UINT32 smmu0_int4_mask2;
-    ZXIC_UINT32 smmu0_int4_mask1;
-    ZXIC_UINT32 smmu0_int4_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT4_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int4_status_t
-{
-    ZXIC_UINT32 smmu0_int4_status31;
-    ZXIC_UINT32 smmu0_int4_status30;
-    ZXIC_UINT32 smmu0_int4_status29;
-    ZXIC_UINT32 smmu0_int4_status28;
-    ZXIC_UINT32 smmu0_int4_status27;
-    ZXIC_UINT32 smmu0_int4_status26;
-    ZXIC_UINT32 smmu0_int4_status25;
-    ZXIC_UINT32 smmu0_int4_status24;
-    ZXIC_UINT32 smmu0_int4_status23;
-    ZXIC_UINT32 smmu0_int4_status22;
-    ZXIC_UINT32 smmu0_int4_status21;
-    ZXIC_UINT32 smmu0_int4_status20;
-    ZXIC_UINT32 smmu0_int4_status19;
-    ZXIC_UINT32 smmu0_int4_status18;
-    ZXIC_UINT32 smmu0_int4_status17;
-    ZXIC_UINT32 smmu0_int4_status16;
-    ZXIC_UINT32 smmu0_int4_status15;
-    ZXIC_UINT32 smmu0_int4_status14;
-    ZXIC_UINT32 smmu0_int4_status13;
-    ZXIC_UINT32 smmu0_int4_status12;
-    ZXIC_UINT32 smmu0_int4_status11;
-    ZXIC_UINT32 smmu0_int4_status10;
-    ZXIC_UINT32 smmu0_int4_status9;
-    ZXIC_UINT32 smmu0_int4_status8;
-    ZXIC_UINT32 smmu0_int4_status7;
-    ZXIC_UINT32 smmu0_int4_status6;
-    ZXIC_UINT32 smmu0_int4_status5;
-    ZXIC_UINT32 smmu0_int4_status4;
-    ZXIC_UINT32 smmu0_int4_status3;
-    ZXIC_UINT32 smmu0_int4_status2;
-    ZXIC_UINT32 smmu0_int4_status1;
-    ZXIC_UINT32 smmu0_int4_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT4_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int5_en_t
-{
-    ZXIC_UINT32 smmu0_int5_en31;
-    ZXIC_UINT32 smmu0_int5_en30;
-    ZXIC_UINT32 smmu0_int5_en29;
-    ZXIC_UINT32 smmu0_int5_en28;
-    ZXIC_UINT32 smmu0_int5_en27;
-    ZXIC_UINT32 smmu0_int5_en26;
-    ZXIC_UINT32 smmu0_int5_en25;
-    ZXIC_UINT32 smmu0_int5_en24;
-    ZXIC_UINT32 smmu0_int5_en23;
-    ZXIC_UINT32 smmu0_int5_en22;
-    ZXIC_UINT32 smmu0_int5_en21;
-    ZXIC_UINT32 smmu0_int5_en20;
-    ZXIC_UINT32 smmu0_int5_en19;
-    ZXIC_UINT32 smmu0_int5_en18;
-    ZXIC_UINT32 smmu0_int5_en17;
-    ZXIC_UINT32 smmu0_int5_en16;
-    ZXIC_UINT32 smmu0_int5_en15;
-    ZXIC_UINT32 smmu0_int5_en14;
-    ZXIC_UINT32 smmu0_int5_en13;
-    ZXIC_UINT32 smmu0_int5_en12;
-    ZXIC_UINT32 smmu0_int5_en11;
-    ZXIC_UINT32 smmu0_int5_en10;
-    ZXIC_UINT32 smmu0_int5_en9;
-    ZXIC_UINT32 smmu0_int5_en8;
-    ZXIC_UINT32 smmu0_int5_en7;
-    ZXIC_UINT32 smmu0_int5_en6;
-    ZXIC_UINT32 smmu0_int5_en5;
-    ZXIC_UINT32 smmu0_int5_en4;
-    ZXIC_UINT32 smmu0_int5_en3;
-    ZXIC_UINT32 smmu0_int5_en2;
-    ZXIC_UINT32 smmu0_int5_en1;
-    ZXIC_UINT32 smmu0_int5_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT5_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int5_mask_t
-{
-    ZXIC_UINT32 smmu0_int5_mask31;
-    ZXIC_UINT32 smmu0_int5_mask30;
-    ZXIC_UINT32 smmu0_int5_mask29;
-    ZXIC_UINT32 smmu0_int5_mask28;
-    ZXIC_UINT32 smmu0_int5_mask27;
-    ZXIC_UINT32 smmu0_int5_mask26;
-    ZXIC_UINT32 smmu0_int5_mask25;
-    ZXIC_UINT32 smmu0_int5_mask24;
-    ZXIC_UINT32 smmu0_int5_mask23;
-    ZXIC_UINT32 smmu0_int5_mask22;
-    ZXIC_UINT32 smmu0_int5_mask21;
-    ZXIC_UINT32 smmu0_int5_mask20;
-    ZXIC_UINT32 smmu0_int5_mask19;
-    ZXIC_UINT32 smmu0_int5_mask18;
-    ZXIC_UINT32 smmu0_int5_mask17;
-    ZXIC_UINT32 smmu0_int5_mask16;
-    ZXIC_UINT32 smmu0_int5_mask15;
-    ZXIC_UINT32 smmu0_int5_mask14;
-    ZXIC_UINT32 smmu0_int5_mask13;
-    ZXIC_UINT32 smmu0_int5_mask12;
-    ZXIC_UINT32 smmu0_int5_mask11;
-    ZXIC_UINT32 smmu0_int5_mask10;
-    ZXIC_UINT32 smmu0_int5_mask9;
-    ZXIC_UINT32 smmu0_int5_mask8;
-    ZXIC_UINT32 smmu0_int5_mask7;
-    ZXIC_UINT32 smmu0_int5_mask6;
-    ZXIC_UINT32 smmu0_int5_mask5;
-    ZXIC_UINT32 smmu0_int5_mask4;
-    ZXIC_UINT32 smmu0_int5_mask3;
-    ZXIC_UINT32 smmu0_int5_mask2;
-    ZXIC_UINT32 smmu0_int5_mask1;
-    ZXIC_UINT32 smmu0_int5_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT5_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int5_status_t
-{
-    ZXIC_UINT32 smmu0_int5_status31;
-    ZXIC_UINT32 smmu0_int5_status30;
-    ZXIC_UINT32 smmu0_int5_status29;
-    ZXIC_UINT32 smmu0_int5_status28;
-    ZXIC_UINT32 smmu0_int5_status27;
-    ZXIC_UINT32 smmu0_int5_status26;
-    ZXIC_UINT32 smmu0_int5_status25;
-    ZXIC_UINT32 smmu0_int5_status24;
-    ZXIC_UINT32 smmu0_int5_status23;
-    ZXIC_UINT32 smmu0_int5_status22;
-    ZXIC_UINT32 smmu0_int5_status21;
-    ZXIC_UINT32 smmu0_int5_status20;
-    ZXIC_UINT32 smmu0_int5_status19;
-    ZXIC_UINT32 smmu0_int5_status18;
-    ZXIC_UINT32 smmu0_int5_status17;
-    ZXIC_UINT32 smmu0_int5_status16;
-    ZXIC_UINT32 smmu0_int5_status15;
-    ZXIC_UINT32 smmu0_int5_status14;
-    ZXIC_UINT32 smmu0_int5_status13;
-    ZXIC_UINT32 smmu0_int5_status12;
-    ZXIC_UINT32 smmu0_int5_status11;
-    ZXIC_UINT32 smmu0_int5_status10;
-    ZXIC_UINT32 smmu0_int5_status9;
-    ZXIC_UINT32 smmu0_int5_status8;
-    ZXIC_UINT32 smmu0_int5_status7;
-    ZXIC_UINT32 smmu0_int5_status6;
-    ZXIC_UINT32 smmu0_int5_status5;
-    ZXIC_UINT32 smmu0_int5_status4;
-    ZXIC_UINT32 smmu0_int5_status3;
-    ZXIC_UINT32 smmu0_int5_status2;
-    ZXIC_UINT32 smmu0_int5_status1;
-    ZXIC_UINT32 smmu0_int5_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT5_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int6_en_t
-{
-    ZXIC_UINT32 smmu0_int6_en31;
-    ZXIC_UINT32 smmu0_int6_en30;
-    ZXIC_UINT32 smmu0_int6_en29;
-    ZXIC_UINT32 smmu0_int6_en28;
-    ZXIC_UINT32 smmu0_int6_en27;
-    ZXIC_UINT32 smmu0_int6_en26;
-    ZXIC_UINT32 smmu0_int6_en25;
-    ZXIC_UINT32 smmu0_int6_en24;
-    ZXIC_UINT32 smmu0_int6_en23;
-    ZXIC_UINT32 smmu0_int6_en22;
-    ZXIC_UINT32 smmu0_int6_en21;
-    ZXIC_UINT32 smmu0_int6_en20;
-    ZXIC_UINT32 smmu0_int6_en19;
-    ZXIC_UINT32 smmu0_int6_en18;
-    ZXIC_UINT32 smmu0_int6_en17;
-    ZXIC_UINT32 smmu0_int6_en16;
-    ZXIC_UINT32 smmu0_int6_en15;
-    ZXIC_UINT32 smmu0_int6_en14;
-    ZXIC_UINT32 smmu0_int6_en13;
-    ZXIC_UINT32 smmu0_int6_en12;
-    ZXIC_UINT32 smmu0_int6_en11;
-    ZXIC_UINT32 smmu0_int6_en10;
-    ZXIC_UINT32 smmu0_int6_en9;
-    ZXIC_UINT32 smmu0_int6_en8;
-    ZXIC_UINT32 smmu0_int6_en7;
-    ZXIC_UINT32 smmu0_int6_en6;
-    ZXIC_UINT32 smmu0_int6_en5;
-    ZXIC_UINT32 smmu0_int6_en4;
-    ZXIC_UINT32 smmu0_int6_en3;
-    ZXIC_UINT32 smmu0_int6_en2;
-    ZXIC_UINT32 smmu0_int6_en1;
-    ZXIC_UINT32 smmu0_int6_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT6_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int6_mask_t
-{
-    ZXIC_UINT32 smmu0_int6_mask31;
-    ZXIC_UINT32 smmu0_int6_mask30;
-    ZXIC_UINT32 smmu0_int6_mask29;
-    ZXIC_UINT32 smmu0_int6_mask28;
-    ZXIC_UINT32 smmu0_int6_mask27;
-    ZXIC_UINT32 smmu0_int6_mask26;
-    ZXIC_UINT32 smmu0_int6_mask25;
-    ZXIC_UINT32 smmu0_int6_mask24;
-    ZXIC_UINT32 smmu0_int6_mask23;
-    ZXIC_UINT32 smmu0_int6_mask22;
-    ZXIC_UINT32 smmu0_int6_mask21;
-    ZXIC_UINT32 smmu0_int6_mask20;
-    ZXIC_UINT32 smmu0_int6_mask19;
-    ZXIC_UINT32 smmu0_int6_mask18;
-    ZXIC_UINT32 smmu0_int6_mask17;
-    ZXIC_UINT32 smmu0_int6_mask16;
-    ZXIC_UINT32 smmu0_int6_mask15;
-    ZXIC_UINT32 smmu0_int6_mask14;
-    ZXIC_UINT32 smmu0_int6_mask13;
-    ZXIC_UINT32 smmu0_int6_mask12;
-    ZXIC_UINT32 smmu0_int6_mask11;
-    ZXIC_UINT32 smmu0_int6_mask10;
-    ZXIC_UINT32 smmu0_int6_mask9;
-    ZXIC_UINT32 smmu0_int6_mask8;
-    ZXIC_UINT32 smmu0_int6_mask7;
-    ZXIC_UINT32 smmu0_int6_mask6;
-    ZXIC_UINT32 smmu0_int6_mask5;
-    ZXIC_UINT32 smmu0_int6_mask4;
-    ZXIC_UINT32 smmu0_int6_mask3;
-    ZXIC_UINT32 smmu0_int6_mask2;
-    ZXIC_UINT32 smmu0_int6_mask1;
-    ZXIC_UINT32 smmu0_int6_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT6_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int6_status_t
-{
-    ZXIC_UINT32 smmu0_int6_status31;
-    ZXIC_UINT32 smmu0_int6_status30;
-    ZXIC_UINT32 smmu0_int6_status29;
-    ZXIC_UINT32 smmu0_int6_status28;
-    ZXIC_UINT32 smmu0_int6_status27;
-    ZXIC_UINT32 smmu0_int6_status26;
-    ZXIC_UINT32 smmu0_int6_status25;
-    ZXIC_UINT32 smmu0_int6_status24;
-    ZXIC_UINT32 smmu0_int6_status23;
-    ZXIC_UINT32 smmu0_int6_status22;
-    ZXIC_UINT32 smmu0_int6_status21;
-    ZXIC_UINT32 smmu0_int6_status20;
-    ZXIC_UINT32 smmu0_int6_status19;
-    ZXIC_UINT32 smmu0_int6_status18;
-    ZXIC_UINT32 smmu0_int6_status17;
-    ZXIC_UINT32 smmu0_int6_status16;
-    ZXIC_UINT32 smmu0_int6_status15;
-    ZXIC_UINT32 smmu0_int6_status14;
-    ZXIC_UINT32 smmu0_int6_status13;
-    ZXIC_UINT32 smmu0_int6_status12;
-    ZXIC_UINT32 smmu0_int6_status11;
-    ZXIC_UINT32 smmu0_int6_status10;
-    ZXIC_UINT32 smmu0_int6_status9;
-    ZXIC_UINT32 smmu0_int6_status8;
-    ZXIC_UINT32 smmu0_int6_status7;
-    ZXIC_UINT32 smmu0_int6_status6;
-    ZXIC_UINT32 smmu0_int6_status5;
-    ZXIC_UINT32 smmu0_int6_status4;
-    ZXIC_UINT32 smmu0_int6_status3;
-    ZXIC_UINT32 smmu0_int6_status2;
-    ZXIC_UINT32 smmu0_int6_status1;
-    ZXIC_UINT32 smmu0_int6_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT6_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int7_en_t
-{
-    ZXIC_UINT32 smmu0_int7_en31;
-    ZXIC_UINT32 smmu0_int7_en30;
-    ZXIC_UINT32 smmu0_int7_en29;
-    ZXIC_UINT32 smmu0_int7_en28;
-    ZXIC_UINT32 smmu0_int7_en27;
-    ZXIC_UINT32 smmu0_int7_en26;
-    ZXIC_UINT32 smmu0_int7_en25;
-    ZXIC_UINT32 smmu0_int7_en24;
-    ZXIC_UINT32 smmu0_int7_en23;
-    ZXIC_UINT32 smmu0_int7_en22;
-    ZXIC_UINT32 smmu0_int7_en21;
-    ZXIC_UINT32 smmu0_int7_en20;
-    ZXIC_UINT32 smmu0_int7_en19;
-    ZXIC_UINT32 smmu0_int7_en18;
-    ZXIC_UINT32 smmu0_int7_en17;
-    ZXIC_UINT32 smmu0_int7_en16;
-    ZXIC_UINT32 smmu0_int7_en15;
-    ZXIC_UINT32 smmu0_int7_en14;
-    ZXIC_UINT32 smmu0_int7_en13;
-    ZXIC_UINT32 smmu0_int7_en12;
-    ZXIC_UINT32 smmu0_int7_en11;
-    ZXIC_UINT32 smmu0_int7_en10;
-    ZXIC_UINT32 smmu0_int7_en9;
-    ZXIC_UINT32 smmu0_int7_en8;
-    ZXIC_UINT32 smmu0_int7_en7;
-    ZXIC_UINT32 smmu0_int7_en6;
-    ZXIC_UINT32 smmu0_int7_en5;
-    ZXIC_UINT32 smmu0_int7_en4;
-    ZXIC_UINT32 smmu0_int7_en3;
-    ZXIC_UINT32 smmu0_int7_en2;
-    ZXIC_UINT32 smmu0_int7_en1;
-    ZXIC_UINT32 smmu0_int7_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT7_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int7_mask_t
-{
-    ZXIC_UINT32 smmu0_int7_mask31;
-    ZXIC_UINT32 smmu0_int7_mask30;
-    ZXIC_UINT32 smmu0_int7_mask29;
-    ZXIC_UINT32 smmu0_int7_mask28;
-    ZXIC_UINT32 smmu0_int7_mask27;
-    ZXIC_UINT32 smmu0_int7_mask26;
-    ZXIC_UINT32 smmu0_int7_mask25;
-    ZXIC_UINT32 smmu0_int7_mask24;
-    ZXIC_UINT32 smmu0_int7_mask23;
-    ZXIC_UINT32 smmu0_int7_mask22;
-    ZXIC_UINT32 smmu0_int7_mask21;
-    ZXIC_UINT32 smmu0_int7_mask20;
-    ZXIC_UINT32 smmu0_int7_mask19;
-    ZXIC_UINT32 smmu0_int7_mask18;
-    ZXIC_UINT32 smmu0_int7_mask17;
-    ZXIC_UINT32 smmu0_int7_mask16;
-    ZXIC_UINT32 smmu0_int7_mask15;
-    ZXIC_UINT32 smmu0_int7_mask14;
-    ZXIC_UINT32 smmu0_int7_mask13;
-    ZXIC_UINT32 smmu0_int7_mask12;
-    ZXIC_UINT32 smmu0_int7_mask11;
-    ZXIC_UINT32 smmu0_int7_mask10;
-    ZXIC_UINT32 smmu0_int7_mask9;
-    ZXIC_UINT32 smmu0_int7_mask8;
-    ZXIC_UINT32 smmu0_int7_mask7;
-    ZXIC_UINT32 smmu0_int7_mask6;
-    ZXIC_UINT32 smmu0_int7_mask5;
-    ZXIC_UINT32 smmu0_int7_mask4;
-    ZXIC_UINT32 smmu0_int7_mask3;
-    ZXIC_UINT32 smmu0_int7_mask2;
-    ZXIC_UINT32 smmu0_int7_mask1;
-    ZXIC_UINT32 smmu0_int7_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT7_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int7_status_t
-{
-    ZXIC_UINT32 smmu0_int7_status31;
-    ZXIC_UINT32 smmu0_int7_status30;
-    ZXIC_UINT32 smmu0_int7_status29;
-    ZXIC_UINT32 smmu0_int7_status28;
-    ZXIC_UINT32 smmu0_int7_status27;
-    ZXIC_UINT32 smmu0_int7_status26;
-    ZXIC_UINT32 smmu0_int7_status25;
-    ZXIC_UINT32 smmu0_int7_status24;
-    ZXIC_UINT32 smmu0_int7_status23;
-    ZXIC_UINT32 smmu0_int7_status22;
-    ZXIC_UINT32 smmu0_int7_status21;
-    ZXIC_UINT32 smmu0_int7_status20;
-    ZXIC_UINT32 smmu0_int7_status19;
-    ZXIC_UINT32 smmu0_int7_status18;
-    ZXIC_UINT32 smmu0_int7_status17;
-    ZXIC_UINT32 smmu0_int7_status16;
-    ZXIC_UINT32 smmu0_int7_status15;
-    ZXIC_UINT32 smmu0_int7_status14;
-    ZXIC_UINT32 smmu0_int7_status13;
-    ZXIC_UINT32 smmu0_int7_status12;
-    ZXIC_UINT32 smmu0_int7_status11;
-    ZXIC_UINT32 smmu0_int7_status10;
-    ZXIC_UINT32 smmu0_int7_status9;
-    ZXIC_UINT32 smmu0_int7_status8;
-    ZXIC_UINT32 smmu0_int7_status7;
-    ZXIC_UINT32 smmu0_int7_status6;
-    ZXIC_UINT32 smmu0_int7_status5;
-    ZXIC_UINT32 smmu0_int7_status4;
-    ZXIC_UINT32 smmu0_int7_status3;
-    ZXIC_UINT32 smmu0_int7_status2;
-    ZXIC_UINT32 smmu0_int7_status1;
-    ZXIC_UINT32 smmu0_int7_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT7_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int8_en_t
-{
-    ZXIC_UINT32 smmu0_int8_en31;
-    ZXIC_UINT32 smmu0_int8_en30;
-    ZXIC_UINT32 smmu0_int8_en29;
-    ZXIC_UINT32 smmu0_int8_en28;
-    ZXIC_UINT32 smmu0_int8_en27;
-    ZXIC_UINT32 smmu0_int8_en26;
-    ZXIC_UINT32 smmu0_int8_en25;
-    ZXIC_UINT32 smmu0_int8_en24;
-    ZXIC_UINT32 smmu0_int8_en23;
-    ZXIC_UINT32 smmu0_int8_en22;
-    ZXIC_UINT32 smmu0_int8_en21;
-    ZXIC_UINT32 smmu0_int8_en20;
-    ZXIC_UINT32 smmu0_int8_en19;
-    ZXIC_UINT32 smmu0_int8_en18;
-    ZXIC_UINT32 smmu0_int8_en17;
-    ZXIC_UINT32 smmu0_int8_en16;
-    ZXIC_UINT32 smmu0_int8_en15;
-    ZXIC_UINT32 smmu0_int8_en14;
-    ZXIC_UINT32 smmu0_int8_en13;
-    ZXIC_UINT32 smmu0_int8_en12;
-    ZXIC_UINT32 smmu0_int8_en11;
-    ZXIC_UINT32 smmu0_int8_en10;
-    ZXIC_UINT32 smmu0_int8_en9;
-    ZXIC_UINT32 smmu0_int8_en8;
-    ZXIC_UINT32 smmu0_int8_en7;
-    ZXIC_UINT32 smmu0_int8_en6;
-    ZXIC_UINT32 smmu0_int8_en5;
-    ZXIC_UINT32 smmu0_int8_en4;
-    ZXIC_UINT32 smmu0_int8_en3;
-    ZXIC_UINT32 smmu0_int8_en2;
-    ZXIC_UINT32 smmu0_int8_en1;
-    ZXIC_UINT32 smmu0_int8_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT8_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int8_mask_t
-{
-    ZXIC_UINT32 smmu0_int8_mask31;
-    ZXIC_UINT32 smmu0_int8_mask30;
-    ZXIC_UINT32 smmu0_int8_mask29;
-    ZXIC_UINT32 smmu0_int8_mask28;
-    ZXIC_UINT32 smmu0_int8_mask27;
-    ZXIC_UINT32 smmu0_int8_mask26;
-    ZXIC_UINT32 smmu0_int8_mask25;
-    ZXIC_UINT32 smmu0_int8_mask24;
-    ZXIC_UINT32 smmu0_int8_mask23;
-    ZXIC_UINT32 smmu0_int8_mask22;
-    ZXIC_UINT32 smmu0_int8_mask21;
-    ZXIC_UINT32 smmu0_int8_mask20;
-    ZXIC_UINT32 smmu0_int8_mask19;
-    ZXIC_UINT32 smmu0_int8_mask18;
-    ZXIC_UINT32 smmu0_int8_mask17;
-    ZXIC_UINT32 smmu0_int8_mask16;
-    ZXIC_UINT32 smmu0_int8_mask15;
-    ZXIC_UINT32 smmu0_int8_mask14;
-    ZXIC_UINT32 smmu0_int8_mask13;
-    ZXIC_UINT32 smmu0_int8_mask12;
-    ZXIC_UINT32 smmu0_int8_mask11;
-    ZXIC_UINT32 smmu0_int8_mask10;
-    ZXIC_UINT32 smmu0_int8_mask9;
-    ZXIC_UINT32 smmu0_int8_mask8;
-    ZXIC_UINT32 smmu0_int8_mask7;
-    ZXIC_UINT32 smmu0_int8_mask6;
-    ZXIC_UINT32 smmu0_int8_mask5;
-    ZXIC_UINT32 smmu0_int8_mask4;
-    ZXIC_UINT32 smmu0_int8_mask3;
-    ZXIC_UINT32 smmu0_int8_mask2;
-    ZXIC_UINT32 smmu0_int8_mask1;
-    ZXIC_UINT32 smmu0_int8_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT8_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int8_status_t
-{
-    ZXIC_UINT32 smmu0_int8_status31;
-    ZXIC_UINT32 smmu0_int8_status30;
-    ZXIC_UINT32 smmu0_int8_status29;
-    ZXIC_UINT32 smmu0_int8_status28;
-    ZXIC_UINT32 smmu0_int8_status27;
-    ZXIC_UINT32 smmu0_int8_status26;
-    ZXIC_UINT32 smmu0_int8_status25;
-    ZXIC_UINT32 smmu0_int8_status24;
-    ZXIC_UINT32 smmu0_int8_status23;
-    ZXIC_UINT32 smmu0_int8_status22;
-    ZXIC_UINT32 smmu0_int8_status21;
-    ZXIC_UINT32 smmu0_int8_status20;
-    ZXIC_UINT32 smmu0_int8_status19;
-    ZXIC_UINT32 smmu0_int8_status18;
-    ZXIC_UINT32 smmu0_int8_status17;
-    ZXIC_UINT32 smmu0_int8_status16;
-    ZXIC_UINT32 smmu0_int8_status15;
-    ZXIC_UINT32 smmu0_int8_status14;
-    ZXIC_UINT32 smmu0_int8_status13;
-    ZXIC_UINT32 smmu0_int8_status12;
-    ZXIC_UINT32 smmu0_int8_status11;
-    ZXIC_UINT32 smmu0_int8_status10;
-    ZXIC_UINT32 smmu0_int8_status9;
-    ZXIC_UINT32 smmu0_int8_status8;
-    ZXIC_UINT32 smmu0_int8_status7;
-    ZXIC_UINT32 smmu0_int8_status6;
-    ZXIC_UINT32 smmu0_int8_status5;
-    ZXIC_UINT32 smmu0_int8_status4;
-    ZXIC_UINT32 smmu0_int8_status3;
-    ZXIC_UINT32 smmu0_int8_status2;
-    ZXIC_UINT32 smmu0_int8_status1;
-    ZXIC_UINT32 smmu0_int8_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT8_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int9_en_t
-{
-    ZXIC_UINT32 smmu0_int8_en31;
-    ZXIC_UINT32 smmu0_int8_en30;
-    ZXIC_UINT32 smmu0_int8_en29;
-    ZXIC_UINT32 smmu0_int8_en28;
-    ZXIC_UINT32 smmu0_int8_en27;
-    ZXIC_UINT32 smmu0_int8_en26;
-    ZXIC_UINT32 smmu0_int8_en25;
-    ZXIC_UINT32 smmu0_int8_en24;
-    ZXIC_UINT32 smmu0_int8_en23;
-    ZXIC_UINT32 smmu0_int8_en22;
-    ZXIC_UINT32 smmu0_int8_en21;
-    ZXIC_UINT32 smmu0_int8_en20;
-    ZXIC_UINT32 smmu0_int9_en19;
-    ZXIC_UINT32 smmu0_int9_en18;
-    ZXIC_UINT32 smmu0_int9_en17;
-    ZXIC_UINT32 smmu0_int9_en16;
-    ZXIC_UINT32 smmu0_int9_en15;
-    ZXIC_UINT32 smmu0_int9_en14;
-    ZXIC_UINT32 smmu0_int9_en13;
-    ZXIC_UINT32 smmu0_int9_en12;
-    ZXIC_UINT32 smmu0_int9_en11;
-    ZXIC_UINT32 smmu0_int9_en10;
-    ZXIC_UINT32 smmu0_int9_en9;
-    ZXIC_UINT32 smmu0_int9_en8;
-    ZXIC_UINT32 smmu0_int9_en7;
-    ZXIC_UINT32 smmu0_int9_en6;
-    ZXIC_UINT32 smmu0_int9_en5;
-    ZXIC_UINT32 smmu0_int9_en4;
-    ZXIC_UINT32 smmu0_int9_en3;
-    ZXIC_UINT32 smmu0_int9_en2;
-    ZXIC_UINT32 smmu0_int9_en1;
-    ZXIC_UINT32 smmu0_int9_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT9_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int9_mask_t
-{
-    ZXIC_UINT32 smmu0_int9_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT9_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int9_status_t
-{
-    ZXIC_UINT32 smmu0_int9_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT9_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int10_en_t
-{
-    ZXIC_UINT32 smmu0_int10_en31;
-    ZXIC_UINT32 smmu0_int10_en30;
-    ZXIC_UINT32 smmu0_int10_en29;
-    ZXIC_UINT32 smmu0_int10_en28;
-    ZXIC_UINT32 smmu0_int10_en27;
-    ZXIC_UINT32 smmu0_int10_en26;
-    ZXIC_UINT32 smmu0_int10_en25;
-    ZXIC_UINT32 smmu0_int10_en24;
-    ZXIC_UINT32 smmu0_int10_en23;
-    ZXIC_UINT32 smmu0_int10_en22;
-    ZXIC_UINT32 smmu0_int10_en21;
-    ZXIC_UINT32 smmu0_int10_en20;
-    ZXIC_UINT32 smmu0_int10_en19;
-    ZXIC_UINT32 smmu0_int10_en18;
-    ZXIC_UINT32 smmu0_int10_en17;
-    ZXIC_UINT32 smmu0_int10_en16;
-    ZXIC_UINT32 smmu0_int10_en15;
-    ZXIC_UINT32 smmu0_int10_en14;
-    ZXIC_UINT32 smmu0_int10_en13;
-    ZXIC_UINT32 smmu0_int10_en12;
-    ZXIC_UINT32 smmu0_int10_en11;
-    ZXIC_UINT32 smmu0_int10_en10;
-    ZXIC_UINT32 smmu0_int10_en9;
-    ZXIC_UINT32 smmu0_int10_en8;
-    ZXIC_UINT32 smmu0_int10_en7;
-    ZXIC_UINT32 smmu0_int10_en6;
-    ZXIC_UINT32 smmu0_int10_en5;
-    ZXIC_UINT32 smmu0_int10_en4;
-    ZXIC_UINT32 smmu0_int10_en3;
-    ZXIC_UINT32 smmu0_int10_en2;
-    ZXIC_UINT32 smmu0_int10_en1;
-    ZXIC_UINT32 smmu0_int10_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT10_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int10_mask_t
-{
-    ZXIC_UINT32 smmu0_int10_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT10_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int10_status_t
-{
-    ZXIC_UINT32 smmu0_int10_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT10_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int11_en_t
-{
-    ZXIC_UINT32 smmu0_int11_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT11_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int11_mask_t
-{
-    ZXIC_UINT32 smmu0_int11_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT11_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int11_status_t
-{
-    ZXIC_UINT32 smmu0_int11_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT11_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int12_en_t
-{
-    ZXIC_UINT32 smmu0_int12_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT12_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int12_mask_t
-{
-    ZXIC_UINT32 smmu0_int12_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT12_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int12_status_t
-{
-    ZXIC_UINT32 smmu0_int12_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT12_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int13_en_t
-{
-    ZXIC_UINT32 smmu0_int13_en19;
-    ZXIC_UINT32 smmu0_int13_en18;
-    ZXIC_UINT32 smmu0_int13_en17;
-    ZXIC_UINT32 smmu0_int13_en16;
-    ZXIC_UINT32 smmu0_int13_en15;
-    ZXIC_UINT32 smmu0_int13_en14;
-    ZXIC_UINT32 smmu0_int13_en13;
-    ZXIC_UINT32 smmu0_int13_en12;
-    ZXIC_UINT32 smmu0_int13_en11;
-    ZXIC_UINT32 smmu0_int13_en10;
-    ZXIC_UINT32 smmu0_int13_en9;
-    ZXIC_UINT32 smmu0_int13_en8;
-    ZXIC_UINT32 smmu0_int13_en7;
-    ZXIC_UINT32 smmu0_int13_en6;
-    ZXIC_UINT32 smmu0_int13_en5;
-    ZXIC_UINT32 smmu0_int13_en4;
-    ZXIC_UINT32 smmu0_int13_en3;
-    ZXIC_UINT32 smmu0_int13_en2;
-    ZXIC_UINT32 smmu0_int13_en1;
-    ZXIC_UINT32 smmu0_int13_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT13_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int13_mask_t
-{
-    ZXIC_UINT32 smmu0_int13_mask19;
-    ZXIC_UINT32 smmu0_int13_mask18;
-    ZXIC_UINT32 smmu0_int13_mask17;
-    ZXIC_UINT32 smmu0_int13_mask16;
-    ZXIC_UINT32 smmu0_int13_mask15;
-    ZXIC_UINT32 smmu0_int13_mask14;
-    ZXIC_UINT32 smmu0_int13_mask13;
-    ZXIC_UINT32 smmu0_int13_mask12;
-    ZXIC_UINT32 smmu0_int13_mask11;
-    ZXIC_UINT32 smmu0_int13_mask10;
-    ZXIC_UINT32 smmu0_int13_mask9;
-    ZXIC_UINT32 smmu0_int13_mask8;
-    ZXIC_UINT32 smmu0_int13_mask7;
-    ZXIC_UINT32 smmu0_int13_mask6;
-    ZXIC_UINT32 smmu0_int13_mask5;
-    ZXIC_UINT32 smmu0_int13_mask4;
-    ZXIC_UINT32 smmu0_int13_mask3;
-    ZXIC_UINT32 smmu0_int13_mask2;
-    ZXIC_UINT32 smmu0_int13_mask1;
-    ZXIC_UINT32 smmu0_int13_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT13_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int13_status_t
-{
-    ZXIC_UINT32 smmu0_int13_status19;
-    ZXIC_UINT32 smmu0_int13_status18;
-    ZXIC_UINT32 smmu0_int13_status17;
-    ZXIC_UINT32 smmu0_int13_status16;
-    ZXIC_UINT32 smmu0_int13_status15;
-    ZXIC_UINT32 smmu0_int13_status14;
-    ZXIC_UINT32 smmu0_int13_status13;
-    ZXIC_UINT32 smmu0_int13_status12;
-    ZXIC_UINT32 smmu0_int13_status11;
-    ZXIC_UINT32 smmu0_int13_status10;
-    ZXIC_UINT32 smmu0_int13_status9;
-    ZXIC_UINT32 smmu0_int13_status8;
-    ZXIC_UINT32 smmu0_int13_status7;
-    ZXIC_UINT32 smmu0_int13_status6;
-    ZXIC_UINT32 smmu0_int13_status5;
-    ZXIC_UINT32 smmu0_int13_status4;
-    ZXIC_UINT32 smmu0_int13_status3;
-    ZXIC_UINT32 smmu0_int13_status2;
-    ZXIC_UINT32 smmu0_int13_status1;
-    ZXIC_UINT32 smmu0_int13_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT13_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int14_en_t
-{
-    ZXIC_UINT32 smmu0_int14_en16;
-    ZXIC_UINT32 smmu0_int14_en15;
-    ZXIC_UINT32 smmu0_int14_en14;
-    ZXIC_UINT32 smmu0_int14_en13;
-    ZXIC_UINT32 smmu0_int14_en12;
-    ZXIC_UINT32 smmu0_int14_en11;
-    ZXIC_UINT32 smmu0_int14_en10;
-    ZXIC_UINT32 smmu0_int14_en9;
-    ZXIC_UINT32 smmu0_int14_en8;
-    ZXIC_UINT32 smmu0_int14_en7;
-    ZXIC_UINT32 smmu0_int14_en6;
-    ZXIC_UINT32 smmu0_int14_en5;
-    ZXIC_UINT32 smmu0_int14_en4;
-    ZXIC_UINT32 smmu0_int14_en3;
-    ZXIC_UINT32 smmu0_int14_en2;
-    ZXIC_UINT32 smmu0_int14_en1;
-    ZXIC_UINT32 smmu0_int14_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT14_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int14_mask_t
-{
-    ZXIC_UINT32 smmu0_int14_mask16;
-    ZXIC_UINT32 smmu0_int14_mask15;
-    ZXIC_UINT32 smmu0_int14_mask14;
-    ZXIC_UINT32 smmu0_int14_mask13;
-    ZXIC_UINT32 smmu0_int14_mask12;
-    ZXIC_UINT32 smmu0_int14_mask11;
-    ZXIC_UINT32 smmu0_int14_mask10;
-    ZXIC_UINT32 smmu0_int14_mask9;
-    ZXIC_UINT32 smmu0_int14_mask8;
-    ZXIC_UINT32 smmu0_int14_mask7;
-    ZXIC_UINT32 smmu0_int14_mask6;
-    ZXIC_UINT32 smmu0_int14_mask5;
-    ZXIC_UINT32 smmu0_int14_mask4;
-    ZXIC_UINT32 smmu0_int14_mask3;
-    ZXIC_UINT32 smmu0_int14_mask2;
-    ZXIC_UINT32 smmu0_int14_mask1;
-    ZXIC_UINT32 smmu0_int14_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT14_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int14_status_t
-{
-    ZXIC_UINT32 smmu0_int14_status16;
-    ZXIC_UINT32 smmu0_int14_status15;
-    ZXIC_UINT32 smmu0_int14_status14;
-    ZXIC_UINT32 smmu0_int14_status13;
-    ZXIC_UINT32 smmu0_int14_status12;
-    ZXIC_UINT32 smmu0_int14_status11;
-    ZXIC_UINT32 smmu0_int14_status10;
-    ZXIC_UINT32 smmu0_int14_status9;
-    ZXIC_UINT32 smmu0_int14_status8;
-    ZXIC_UINT32 smmu0_int14_status7;
-    ZXIC_UINT32 smmu0_int14_status6;
-    ZXIC_UINT32 smmu0_int14_status5;
-    ZXIC_UINT32 smmu0_int14_status4;
-    ZXIC_UINT32 smmu0_int14_status3;
-    ZXIC_UINT32 smmu0_int14_status2;
-    ZXIC_UINT32 smmu0_int14_status1;
-    ZXIC_UINT32 smmu0_int14_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT14_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_ecc_unmask_flag_t
-{
-    ZXIC_UINT32 smmu0_int53_unmask_flag;
-    ZXIC_UINT32 smmu0_int52_unmask_flag;
-    ZXIC_UINT32 smmu0_int51_unmask_flag;
-    ZXIC_UINT32 smmu0_int50_unmask_flag;
-    ZXIC_UINT32 smmu0_int49_unmask_flag;
-    ZXIC_UINT32 smmu0_int48_unmask_flag;
-    ZXIC_UINT32 smmu0_int47_unmask_flag;
-    ZXIC_UINT32 smmu0_int46_unmask_flag;
-    ZXIC_UINT32 smmu0_int45_unmask_flag;
-    ZXIC_UINT32 smmu0_int44_unmask_flag;
-    ZXIC_UINT32 smmu0_int43_unmask_flag;
-    ZXIC_UINT32 smmu0_int42_unmask_flag;
-    ZXIC_UINT32 smmu0_int41_unmask_flag;
-    ZXIC_UINT32 smmu0_int40_unmask_flag;
-    ZXIC_UINT32 smmu0_int39_unmask_flag;
-    ZXIC_UINT32 smmu0_int38_unmask_flag;
-    ZXIC_UINT32 smmu0_int37_unmask_flag;
-    ZXIC_UINT32 smmu0_int36_unmask_flag;
-    ZXIC_UINT32 smmu0_int35_unmask_flag;
-    ZXIC_UINT32 smmu0_int34_unmask_flag;
-    ZXIC_UINT32 smmu0_int33_unmask_flag;
-    ZXIC_UINT32 smmu0_int32_unmask_flag;
-}DPP_SMMU0_SMMU0_SMMU0_ECC_UNMASK_FLAG_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int15_en_t
-{
-    ZXIC_UINT32 smmu0_int15_en31;
-    ZXIC_UINT32 smmu0_int15_en30;
-    ZXIC_UINT32 smmu0_int15_en29;
-    ZXIC_UINT32 smmu0_int15_en28;
-    ZXIC_UINT32 smmu0_int15_en27;
-    ZXIC_UINT32 smmu0_int15_en26;
-    ZXIC_UINT32 smmu0_int15_en25;
-    ZXIC_UINT32 smmu0_int15_en24;
-    ZXIC_UINT32 smmu0_int15_en23;
-    ZXIC_UINT32 smmu0_int15_en22;
-    ZXIC_UINT32 smmu0_int15_en21;
-    ZXIC_UINT32 smmu0_int15_en20;
-    ZXIC_UINT32 smmu0_int15_en19;
-    ZXIC_UINT32 smmu0_int15_en18;
-    ZXIC_UINT32 smmu0_int15_en17;
-    ZXIC_UINT32 smmu0_int15_en16;
-    ZXIC_UINT32 smmu0_int15_en15;
-    ZXIC_UINT32 smmu0_int15_en14;
-    ZXIC_UINT32 smmu0_int15_en13;
-    ZXIC_UINT32 smmu0_int15_en12;
-    ZXIC_UINT32 smmu0_int15_en11;
-    ZXIC_UINT32 smmu0_int15_en10;
-    ZXIC_UINT32 smmu0_int15_en9;
-    ZXIC_UINT32 smmu0_int15_en8;
-    ZXIC_UINT32 smmu0_int15_en7;
-    ZXIC_UINT32 smmu0_int15_en6;
-    ZXIC_UINT32 smmu0_int15_en5;
-    ZXIC_UINT32 smmu0_int15_en4;
-    ZXIC_UINT32 smmu0_int15_en3;
-    ZXIC_UINT32 smmu0_int15_en2;
-    ZXIC_UINT32 smmu0_int15_en1;
-    ZXIC_UINT32 smmu0_int15_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT15_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int15_mask_t
-{
-    ZXIC_UINT32 smmu0_int15_mask31;
-    ZXIC_UINT32 smmu0_int15_mask30;
-    ZXIC_UINT32 smmu0_int15_mask29;
-    ZXIC_UINT32 smmu0_int15_mask28;
-    ZXIC_UINT32 smmu0_int15_mask27;
-    ZXIC_UINT32 smmu0_int15_mask26;
-    ZXIC_UINT32 smmu0_int15_mask25;
-    ZXIC_UINT32 smmu0_int15_mask24;
-    ZXIC_UINT32 smmu0_int15_mask23;
-    ZXIC_UINT32 smmu0_int15_mask22;
-    ZXIC_UINT32 smmu0_int15_mask21;
-    ZXIC_UINT32 smmu0_int15_mask20;
-    ZXIC_UINT32 smmu0_int15_mask19;
-    ZXIC_UINT32 smmu0_int15_mask18;
-    ZXIC_UINT32 smmu0_int15_mask17;
-    ZXIC_UINT32 smmu0_int15_mask16;
-    ZXIC_UINT32 smmu0_int15_mask15;
-    ZXIC_UINT32 smmu0_int15_mask14;
-    ZXIC_UINT32 smmu0_int15_mask13;
-    ZXIC_UINT32 smmu0_int15_mask12;
-    ZXIC_UINT32 smmu0_int15_mask11;
-    ZXIC_UINT32 smmu0_int15_mask10;
-    ZXIC_UINT32 smmu0_int15_mask9;
-    ZXIC_UINT32 smmu0_int15_mask8;
-    ZXIC_UINT32 smmu0_int15_mask7;
-    ZXIC_UINT32 smmu0_int15_mask6;
-    ZXIC_UINT32 smmu0_int15_mask5;
-    ZXIC_UINT32 smmu0_int15_mask4;
-    ZXIC_UINT32 smmu0_int15_mask3;
-    ZXIC_UINT32 smmu0_int15_mask2;
-    ZXIC_UINT32 smmu0_int15_mask1;
-    ZXIC_UINT32 smmu0_int15_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT15_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int15_status_t
-{
-    ZXIC_UINT32 smmu0_int15_status31;
-    ZXIC_UINT32 smmu0_int15_status30;
-    ZXIC_UINT32 smmu0_int15_status29;
-    ZXIC_UINT32 smmu0_int15_status28;
-    ZXIC_UINT32 smmu0_int15_status27;
-    ZXIC_UINT32 smmu0_int15_status26;
-    ZXIC_UINT32 smmu0_int15_status25;
-    ZXIC_UINT32 smmu0_int15_status24;
-    ZXIC_UINT32 smmu0_int15_status23;
-    ZXIC_UINT32 smmu0_int15_status22;
-    ZXIC_UINT32 smmu0_int15_status21;
-    ZXIC_UINT32 smmu0_int15_status20;
-    ZXIC_UINT32 smmu0_int15_status19;
-    ZXIC_UINT32 smmu0_int15_status18;
-    ZXIC_UINT32 smmu0_int15_status17;
-    ZXIC_UINT32 smmu0_int15_status16;
-    ZXIC_UINT32 smmu0_int15_status15;
-    ZXIC_UINT32 smmu0_int15_status14;
-    ZXIC_UINT32 smmu0_int15_status13;
-    ZXIC_UINT32 smmu0_int15_status12;
-    ZXIC_UINT32 smmu0_int15_status11;
-    ZXIC_UINT32 smmu0_int15_status10;
-    ZXIC_UINT32 smmu0_int15_status9;
-    ZXIC_UINT32 smmu0_int15_status8;
-    ZXIC_UINT32 smmu0_int15_status7;
-    ZXIC_UINT32 smmu0_int15_status6;
-    ZXIC_UINT32 smmu0_int15_status5;
-    ZXIC_UINT32 smmu0_int15_status4;
-    ZXIC_UINT32 smmu0_int15_status3;
-    ZXIC_UINT32 smmu0_int15_status2;
-    ZXIC_UINT32 smmu0_int15_status1;
-    ZXIC_UINT32 smmu0_int15_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT15_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int16_en_t
-{
-    ZXIC_UINT32 smmu0_int16_en31;
-    ZXIC_UINT32 smmu0_int16_en30;
-    ZXIC_UINT32 smmu0_int16_en29;
-    ZXIC_UINT32 smmu0_int16_en28;
-    ZXIC_UINT32 smmu0_int16_en27;
-    ZXIC_UINT32 smmu0_int16_en26;
-    ZXIC_UINT32 smmu0_int16_en25;
-    ZXIC_UINT32 smmu0_int16_en24;
-    ZXIC_UINT32 smmu0_int16_en23;
-    ZXIC_UINT32 smmu0_int16_en22;
-    ZXIC_UINT32 smmu0_int16_en21;
-    ZXIC_UINT32 smmu0_int16_en20;
-    ZXIC_UINT32 smmu0_int16_en19;
-    ZXIC_UINT32 smmu0_int16_en18;
-    ZXIC_UINT32 smmu0_int16_en17;
-    ZXIC_UINT32 smmu0_int16_en16;
-    ZXIC_UINT32 smmu0_int16_en15;
-    ZXIC_UINT32 smmu0_int16_en14;
-    ZXIC_UINT32 smmu0_int16_en13;
-    ZXIC_UINT32 smmu0_int16_en12;
-    ZXIC_UINT32 smmu0_int16_en11;
-    ZXIC_UINT32 smmu0_int16_en10;
-    ZXIC_UINT32 smmu0_int16_en9;
-    ZXIC_UINT32 smmu0_int16_en8;
-    ZXIC_UINT32 smmu0_int16_en7;
-    ZXIC_UINT32 smmu0_int16_en6;
-    ZXIC_UINT32 smmu0_int16_en5;
-    ZXIC_UINT32 smmu0_int16_en4;
-    ZXIC_UINT32 smmu0_int16_en3;
-    ZXIC_UINT32 smmu0_int16_en2;
-    ZXIC_UINT32 smmu0_int16_en1;
-    ZXIC_UINT32 smmu0_int16_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT16_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int16_mask_t
-{
-    ZXIC_UINT32 smmu0_int16_mask31;
-    ZXIC_UINT32 smmu0_int16_mask30;
-    ZXIC_UINT32 smmu0_int16_mask29;
-    ZXIC_UINT32 smmu0_int16_mask28;
-    ZXIC_UINT32 smmu0_int16_mask27;
-    ZXIC_UINT32 smmu0_int16_mask26;
-    ZXIC_UINT32 smmu0_int16_mask25;
-    ZXIC_UINT32 smmu0_int16_mask24;
-    ZXIC_UINT32 smmu0_int16_mask23;
-    ZXIC_UINT32 smmu0_int16_mask22;
-    ZXIC_UINT32 smmu0_int16_mask21;
-    ZXIC_UINT32 smmu0_int16_mask20;
-    ZXIC_UINT32 smmu0_int16_mask19;
-    ZXIC_UINT32 smmu0_int16_mask18;
-    ZXIC_UINT32 smmu0_int16_mask17;
-    ZXIC_UINT32 smmu0_int16_mask16;
-    ZXIC_UINT32 smmu0_int16_mask15;
-    ZXIC_UINT32 smmu0_int16_mask14;
-    ZXIC_UINT32 smmu0_int16_mask13;
-    ZXIC_UINT32 smmu0_int16_mask12;
-    ZXIC_UINT32 smmu0_int16_mask11;
-    ZXIC_UINT32 smmu0_int16_mask10;
-    ZXIC_UINT32 smmu0_int16_mask9;
-    ZXIC_UINT32 smmu0_int16_mask8;
-    ZXIC_UINT32 smmu0_int16_mask7;
-    ZXIC_UINT32 smmu0_int16_mask6;
-    ZXIC_UINT32 smmu0_int16_mask5;
-    ZXIC_UINT32 smmu0_int16_mask4;
-    ZXIC_UINT32 smmu0_int16_mask3;
-    ZXIC_UINT32 smmu0_int16_mask2;
-    ZXIC_UINT32 smmu0_int16_mask1;
-    ZXIC_UINT32 smmu0_int16_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT16_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int16_status_t
-{
-    ZXIC_UINT32 smmu0_int16_status31;
-    ZXIC_UINT32 smmu0_int16_status30;
-    ZXIC_UINT32 smmu0_int16_status29;
-    ZXIC_UINT32 smmu0_int16_status28;
-    ZXIC_UINT32 smmu0_int16_status27;
-    ZXIC_UINT32 smmu0_int16_status26;
-    ZXIC_UINT32 smmu0_int16_status25;
-    ZXIC_UINT32 smmu0_int16_status24;
-    ZXIC_UINT32 smmu0_int16_status23;
-    ZXIC_UINT32 smmu0_int16_status22;
-    ZXIC_UINT32 smmu0_int16_status21;
-    ZXIC_UINT32 smmu0_int16_status20;
-    ZXIC_UINT32 smmu0_int16_status19;
-    ZXIC_UINT32 smmu0_int16_status18;
-    ZXIC_UINT32 smmu0_int16_status17;
-    ZXIC_UINT32 smmu0_int16_status16;
-    ZXIC_UINT32 smmu0_int16_status15;
-    ZXIC_UINT32 smmu0_int16_status14;
-    ZXIC_UINT32 smmu0_int16_status13;
-    ZXIC_UINT32 smmu0_int16_status12;
-    ZXIC_UINT32 smmu0_int16_status11;
-    ZXIC_UINT32 smmu0_int16_status10;
-    ZXIC_UINT32 smmu0_int16_status9;
-    ZXIC_UINT32 smmu0_int16_status8;
-    ZXIC_UINT32 smmu0_int16_status7;
-    ZXIC_UINT32 smmu0_int16_status6;
-    ZXIC_UINT32 smmu0_int16_status5;
-    ZXIC_UINT32 smmu0_int16_status4;
-    ZXIC_UINT32 smmu0_int16_status3;
-    ZXIC_UINT32 smmu0_int16_status2;
-    ZXIC_UINT32 smmu0_int16_status1;
-    ZXIC_UINT32 smmu0_int16_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT16_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int17_en_t
-{
-    ZXIC_UINT32 smmu0_int17_en31;
-    ZXIC_UINT32 smmu0_int17_en30;
-    ZXIC_UINT32 smmu0_int17_en29;
-    ZXIC_UINT32 smmu0_int17_en28;
-    ZXIC_UINT32 smmu0_int17_en27;
-    ZXIC_UINT32 smmu0_int17_en26;
-    ZXIC_UINT32 smmu0_int17_en25;
-    ZXIC_UINT32 smmu0_int17_en24;
-    ZXIC_UINT32 smmu0_int17_en23;
-    ZXIC_UINT32 smmu0_int17_en22;
-    ZXIC_UINT32 smmu0_int17_en21;
-    ZXIC_UINT32 smmu0_int17_en20;
-    ZXIC_UINT32 smmu0_int17_en19;
-    ZXIC_UINT32 smmu0_int17_en18;
-    ZXIC_UINT32 smmu0_int17_en17;
-    ZXIC_UINT32 smmu0_int17_en16;
-    ZXIC_UINT32 smmu0_int17_en15;
-    ZXIC_UINT32 smmu0_int17_en14;
-    ZXIC_UINT32 smmu0_int17_en13;
-    ZXIC_UINT32 smmu0_int17_en12;
-    ZXIC_UINT32 smmu0_int17_en11;
-    ZXIC_UINT32 smmu0_int17_en10;
-    ZXIC_UINT32 smmu0_int17_en9;
-    ZXIC_UINT32 smmu0_int17_en8;
-    ZXIC_UINT32 smmu0_int17_en7;
-    ZXIC_UINT32 smmu0_int17_en6;
-    ZXIC_UINT32 smmu0_int17_en5;
-    ZXIC_UINT32 smmu0_int17_en4;
-    ZXIC_UINT32 smmu0_int17_en3;
-    ZXIC_UINT32 smmu0_int17_en2;
-    ZXIC_UINT32 smmu0_int17_en1;
-    ZXIC_UINT32 smmu0_int17_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT17_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int17_mask_t
-{
-    ZXIC_UINT32 smmu0_int17_mask31;
-    ZXIC_UINT32 smmu0_int17_mask30;
-    ZXIC_UINT32 smmu0_int17_mask29;
-    ZXIC_UINT32 smmu0_int17_mask28;
-    ZXIC_UINT32 smmu0_int17_mask27;
-    ZXIC_UINT32 smmu0_int17_mask26;
-    ZXIC_UINT32 smmu0_int17_mask25;
-    ZXIC_UINT32 smmu0_int17_mask24;
-    ZXIC_UINT32 smmu0_int17_mask23;
-    ZXIC_UINT32 smmu0_int17_mask22;
-    ZXIC_UINT32 smmu0_int17_mask21;
-    ZXIC_UINT32 smmu0_int17_mask20;
-    ZXIC_UINT32 smmu0_int17_mask19;
-    ZXIC_UINT32 smmu0_int17_mask18;
-    ZXIC_UINT32 smmu0_int17_mask17;
-    ZXIC_UINT32 smmu0_int17_mask16;
-    ZXIC_UINT32 smmu0_int17_mask15;
-    ZXIC_UINT32 smmu0_int17_mask14;
-    ZXIC_UINT32 smmu0_int17_mask13;
-    ZXIC_UINT32 smmu0_int17_mask12;
-    ZXIC_UINT32 smmu0_int17_mask11;
-    ZXIC_UINT32 smmu0_int17_mask10;
-    ZXIC_UINT32 smmu0_int17_mask9;
-    ZXIC_UINT32 smmu0_int17_mask8;
-    ZXIC_UINT32 smmu0_int17_mask7;
-    ZXIC_UINT32 smmu0_int17_mask6;
-    ZXIC_UINT32 smmu0_int17_mask5;
-    ZXIC_UINT32 smmu0_int17_mask4;
-    ZXIC_UINT32 smmu0_int17_mask3;
-    ZXIC_UINT32 smmu0_int17_mask2;
-    ZXIC_UINT32 smmu0_int17_mask1;
-    ZXIC_UINT32 smmu0_int17_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT17_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int17_status_t
-{
-    ZXIC_UINT32 smmu0_int17_status31;
-    ZXIC_UINT32 smmu0_int17_status30;
-    ZXIC_UINT32 smmu0_int17_status29;
-    ZXIC_UINT32 smmu0_int17_status28;
-    ZXIC_UINT32 smmu0_int17_status27;
-    ZXIC_UINT32 smmu0_int17_status26;
-    ZXIC_UINT32 smmu0_int17_status25;
-    ZXIC_UINT32 smmu0_int17_status24;
-    ZXIC_UINT32 smmu0_int17_status23;
-    ZXIC_UINT32 smmu0_int17_status22;
-    ZXIC_UINT32 smmu0_int17_status21;
-    ZXIC_UINT32 smmu0_int17_status20;
-    ZXIC_UINT32 smmu0_int17_status19;
-    ZXIC_UINT32 smmu0_int17_status18;
-    ZXIC_UINT32 smmu0_int17_status17;
-    ZXIC_UINT32 smmu0_int17_status16;
-    ZXIC_UINT32 smmu0_int17_status15;
-    ZXIC_UINT32 smmu0_int17_status14;
-    ZXIC_UINT32 smmu0_int17_status13;
-    ZXIC_UINT32 smmu0_int17_status12;
-    ZXIC_UINT32 smmu0_int17_status11;
-    ZXIC_UINT32 smmu0_int17_status10;
-    ZXIC_UINT32 smmu0_int17_status9;
-    ZXIC_UINT32 smmu0_int17_status8;
-    ZXIC_UINT32 smmu0_int17_status7;
-    ZXIC_UINT32 smmu0_int17_status6;
-    ZXIC_UINT32 smmu0_int17_status5;
-    ZXIC_UINT32 smmu0_int17_status4;
-    ZXIC_UINT32 smmu0_int17_status3;
-    ZXIC_UINT32 smmu0_int17_status2;
-    ZXIC_UINT32 smmu0_int17_status1;
-    ZXIC_UINT32 smmu0_int17_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT17_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int18_en_t
-{
-    ZXIC_UINT32 smmu0_int18_en31;
-    ZXIC_UINT32 smmu0_int18_en30;
-    ZXIC_UINT32 smmu0_int18_en29;
-    ZXIC_UINT32 smmu0_int18_en28;
-    ZXIC_UINT32 smmu0_int18_en27;
-    ZXIC_UINT32 smmu0_int18_en26;
-    ZXIC_UINT32 smmu0_int18_en25;
-    ZXIC_UINT32 smmu0_int18_en24;
-    ZXIC_UINT32 smmu0_int18_en23;
-    ZXIC_UINT32 smmu0_int18_en22;
-    ZXIC_UINT32 smmu0_int18_en21;
-    ZXIC_UINT32 smmu0_int18_en20;
-    ZXIC_UINT32 smmu0_int18_en19;
-    ZXIC_UINT32 smmu0_int18_en18;
-    ZXIC_UINT32 smmu0_int18_en17;
-    ZXIC_UINT32 smmu0_int18_en16;
-    ZXIC_UINT32 smmu0_int18_en15;
-    ZXIC_UINT32 smmu0_int18_en14;
-    ZXIC_UINT32 smmu0_int18_en13;
-    ZXIC_UINT32 smmu0_int18_en12;
-    ZXIC_UINT32 smmu0_int18_en11;
-    ZXIC_UINT32 smmu0_int18_en10;
-    ZXIC_UINT32 smmu0_int18_en9;
-    ZXIC_UINT32 smmu0_int18_en8;
-    ZXIC_UINT32 smmu0_int18_en7;
-    ZXIC_UINT32 smmu0_int18_en6;
-    ZXIC_UINT32 smmu0_int18_en5;
-    ZXIC_UINT32 smmu0_int18_en4;
-    ZXIC_UINT32 smmu0_int18_en3;
-    ZXIC_UINT32 smmu0_int18_en2;
-    ZXIC_UINT32 smmu0_int18_en1;
-    ZXIC_UINT32 smmu0_int18_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT18_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int18_mask_t
-{
-    ZXIC_UINT32 smmu0_int18_mask31;
-    ZXIC_UINT32 smmu0_int18_mask30;
-    ZXIC_UINT32 smmu0_int18_mask29;
-    ZXIC_UINT32 smmu0_int18_mask28;
-    ZXIC_UINT32 smmu0_int18_mask27;
-    ZXIC_UINT32 smmu0_int18_mask26;
-    ZXIC_UINT32 smmu0_int18_mask25;
-    ZXIC_UINT32 smmu0_int18_mask24;
-    ZXIC_UINT32 smmu0_int18_mask23;
-    ZXIC_UINT32 smmu0_int18_mask22;
-    ZXIC_UINT32 smmu0_int18_mask21;
-    ZXIC_UINT32 smmu0_int18_mask20;
-    ZXIC_UINT32 smmu0_int18_mask19;
-    ZXIC_UINT32 smmu0_int18_mask18;
-    ZXIC_UINT32 smmu0_int18_mask17;
-    ZXIC_UINT32 smmu0_int18_mask16;
-    ZXIC_UINT32 smmu0_int18_mask15;
-    ZXIC_UINT32 smmu0_int18_mask14;
-    ZXIC_UINT32 smmu0_int18_mask13;
-    ZXIC_UINT32 smmu0_int18_mask12;
-    ZXIC_UINT32 smmu0_int18_mask11;
-    ZXIC_UINT32 smmu0_int18_mask10;
-    ZXIC_UINT32 smmu0_int18_mask9;
-    ZXIC_UINT32 smmu0_int18_mask8;
-    ZXIC_UINT32 smmu0_int18_mask7;
-    ZXIC_UINT32 smmu0_int18_mask6;
-    ZXIC_UINT32 smmu0_int18_mask5;
-    ZXIC_UINT32 smmu0_int18_mask4;
-    ZXIC_UINT32 smmu0_int18_mask3;
-    ZXIC_UINT32 smmu0_int18_mask2;
-    ZXIC_UINT32 smmu0_int18_mask1;
-    ZXIC_UINT32 smmu0_int18_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT18_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int18_status_t
-{
-    ZXIC_UINT32 smmu0_int18_status31;
-    ZXIC_UINT32 smmu0_int18_status30;
-    ZXIC_UINT32 smmu0_int18_status29;
-    ZXIC_UINT32 smmu0_int18_status28;
-    ZXIC_UINT32 smmu0_int18_status27;
-    ZXIC_UINT32 smmu0_int18_status26;
-    ZXIC_UINT32 smmu0_int18_status25;
-    ZXIC_UINT32 smmu0_int18_status24;
-    ZXIC_UINT32 smmu0_int18_status23;
-    ZXIC_UINT32 smmu0_int18_status22;
-    ZXIC_UINT32 smmu0_int18_status21;
-    ZXIC_UINT32 smmu0_int18_status20;
-    ZXIC_UINT32 smmu0_int18_status19;
-    ZXIC_UINT32 smmu0_int18_status18;
-    ZXIC_UINT32 smmu0_int18_status17;
-    ZXIC_UINT32 smmu0_int18_status16;
-    ZXIC_UINT32 smmu0_int18_status15;
-    ZXIC_UINT32 smmu0_int18_status14;
-    ZXIC_UINT32 smmu0_int18_status13;
-    ZXIC_UINT32 smmu0_int18_status12;
-    ZXIC_UINT32 smmu0_int18_status11;
-    ZXIC_UINT32 smmu0_int18_status10;
-    ZXIC_UINT32 smmu0_int18_status9;
-    ZXIC_UINT32 smmu0_int18_status8;
-    ZXIC_UINT32 smmu0_int18_status7;
-    ZXIC_UINT32 smmu0_int18_status6;
-    ZXIC_UINT32 smmu0_int18_status5;
-    ZXIC_UINT32 smmu0_int18_status4;
-    ZXIC_UINT32 smmu0_int18_status3;
-    ZXIC_UINT32 smmu0_int18_status2;
-    ZXIC_UINT32 smmu0_int18_status1;
-    ZXIC_UINT32 smmu0_int18_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT18_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int19_en_t
-{
-    ZXIC_UINT32 smmu0_int19_en31;
-    ZXIC_UINT32 smmu0_int19_en30;
-    ZXIC_UINT32 smmu0_int19_en29;
-    ZXIC_UINT32 smmu0_int19_en28;
-    ZXIC_UINT32 smmu0_int19_en27;
-    ZXIC_UINT32 smmu0_int19_en26;
-    ZXIC_UINT32 smmu0_int19_en25;
-    ZXIC_UINT32 smmu0_int19_en24;
-    ZXIC_UINT32 smmu0_int19_en23;
-    ZXIC_UINT32 smmu0_int19_en22;
-    ZXIC_UINT32 smmu0_int19_en21;
-    ZXIC_UINT32 smmu0_int19_en20;
-    ZXIC_UINT32 smmu0_int19_en19;
-    ZXIC_UINT32 smmu0_int19_en18;
-    ZXIC_UINT32 smmu0_int19_en17;
-    ZXIC_UINT32 smmu0_int19_en16;
-    ZXIC_UINT32 smmu0_int19_en15;
-    ZXIC_UINT32 smmu0_int19_en14;
-    ZXIC_UINT32 smmu0_int19_en13;
-    ZXIC_UINT32 smmu0_int19_en12;
-    ZXIC_UINT32 smmu0_int19_en11;
-    ZXIC_UINT32 smmu0_int19_en10;
-    ZXIC_UINT32 smmu0_int19_en9;
-    ZXIC_UINT32 smmu0_int19_en8;
-    ZXIC_UINT32 smmu0_int19_en7;
-    ZXIC_UINT32 smmu0_int19_en6;
-    ZXIC_UINT32 smmu0_int19_en5;
-    ZXIC_UINT32 smmu0_int19_en4;
-    ZXIC_UINT32 smmu0_int19_en3;
-    ZXIC_UINT32 smmu0_int19_en2;
-    ZXIC_UINT32 smmu0_int19_en1;
-    ZXIC_UINT32 smmu0_int19_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT19_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int19_mask_t
-{
-    ZXIC_UINT32 smmu0_int19_mask31;
-    ZXIC_UINT32 smmu0_int19_mask30;
-    ZXIC_UINT32 smmu0_int19_mask29;
-    ZXIC_UINT32 smmu0_int19_mask28;
-    ZXIC_UINT32 smmu0_int19_mask27;
-    ZXIC_UINT32 smmu0_int19_mask26;
-    ZXIC_UINT32 smmu0_int19_mask25;
-    ZXIC_UINT32 smmu0_int19_mask24;
-    ZXIC_UINT32 smmu0_int19_mask23;
-    ZXIC_UINT32 smmu0_int19_mask22;
-    ZXIC_UINT32 smmu0_int19_mask21;
-    ZXIC_UINT32 smmu0_int19_mask20;
-    ZXIC_UINT32 smmu0_int19_mask19;
-    ZXIC_UINT32 smmu0_int19_mask18;
-    ZXIC_UINT32 smmu0_int19_mask17;
-    ZXIC_UINT32 smmu0_int19_mask16;
-    ZXIC_UINT32 smmu0_int19_mask15;
-    ZXIC_UINT32 smmu0_int19_mask14;
-    ZXIC_UINT32 smmu0_int19_mask13;
-    ZXIC_UINT32 smmu0_int19_mask12;
-    ZXIC_UINT32 smmu0_int19_mask11;
-    ZXIC_UINT32 smmu0_int19_mask10;
-    ZXIC_UINT32 smmu0_int19_mask9;
-    ZXIC_UINT32 smmu0_int19_mask8;
-    ZXIC_UINT32 smmu0_int19_mask7;
-    ZXIC_UINT32 smmu0_int19_mask6;
-    ZXIC_UINT32 smmu0_int19_mask5;
-    ZXIC_UINT32 smmu0_int19_mask4;
-    ZXIC_UINT32 smmu0_int19_mask3;
-    ZXIC_UINT32 smmu0_int19_mask2;
-    ZXIC_UINT32 smmu0_int19_mask1;
-    ZXIC_UINT32 smmu0_int19_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT19_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int19_status_t
-{
-    ZXIC_UINT32 smmu0_int19_status31;
-    ZXIC_UINT32 smmu0_int19_status30;
-    ZXIC_UINT32 smmu0_int19_status29;
-    ZXIC_UINT32 smmu0_int19_status28;
-    ZXIC_UINT32 smmu0_int19_status27;
-    ZXIC_UINT32 smmu0_int19_status26;
-    ZXIC_UINT32 smmu0_int19_status25;
-    ZXIC_UINT32 smmu0_int19_status24;
-    ZXIC_UINT32 smmu0_int19_status23;
-    ZXIC_UINT32 smmu0_int19_status22;
-    ZXIC_UINT32 smmu0_int19_status21;
-    ZXIC_UINT32 smmu0_int19_status20;
-    ZXIC_UINT32 smmu0_int19_status19;
-    ZXIC_UINT32 smmu0_int19_status18;
-    ZXIC_UINT32 smmu0_int19_status17;
-    ZXIC_UINT32 smmu0_int19_status16;
-    ZXIC_UINT32 smmu0_int19_status15;
-    ZXIC_UINT32 smmu0_int19_status14;
-    ZXIC_UINT32 smmu0_int19_status13;
-    ZXIC_UINT32 smmu0_int19_status12;
-    ZXIC_UINT32 smmu0_int19_status11;
-    ZXIC_UINT32 smmu0_int19_status10;
-    ZXIC_UINT32 smmu0_int19_status9;
-    ZXIC_UINT32 smmu0_int19_status8;
-    ZXIC_UINT32 smmu0_int19_status7;
-    ZXIC_UINT32 smmu0_int19_status6;
-    ZXIC_UINT32 smmu0_int19_status5;
-    ZXIC_UINT32 smmu0_int19_status4;
-    ZXIC_UINT32 smmu0_int19_status3;
-    ZXIC_UINT32 smmu0_int19_status2;
-    ZXIC_UINT32 smmu0_int19_status1;
-    ZXIC_UINT32 smmu0_int19_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT19_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int20_en_t
-{
-    ZXIC_UINT32 smmu0_int20_en31;
-    ZXIC_UINT32 smmu0_int20_en30;
-    ZXIC_UINT32 smmu0_int20_en29;
-    ZXIC_UINT32 smmu0_int20_en28;
-    ZXIC_UINT32 smmu0_int20_en27;
-    ZXIC_UINT32 smmu0_int20_en26;
-    ZXIC_UINT32 smmu0_int20_en25;
-    ZXIC_UINT32 smmu0_int20_en24;
-    ZXIC_UINT32 smmu0_int20_en23;
-    ZXIC_UINT32 smmu0_int20_en22;
-    ZXIC_UINT32 smmu0_int20_en21;
-    ZXIC_UINT32 smmu0_int20_en20;
-    ZXIC_UINT32 smmu0_int20_en19;
-    ZXIC_UINT32 smmu0_int20_en18;
-    ZXIC_UINT32 smmu0_int20_en17;
-    ZXIC_UINT32 smmu0_int20_en16;
-    ZXIC_UINT32 smmu0_int20_en15;
-    ZXIC_UINT32 smmu0_int20_en14;
-    ZXIC_UINT32 smmu0_int20_en13;
-    ZXIC_UINT32 smmu0_int20_en12;
-    ZXIC_UINT32 smmu0_int20_en11;
-    ZXIC_UINT32 smmu0_int20_en10;
-    ZXIC_UINT32 smmu0_int20_en9;
-    ZXIC_UINT32 smmu0_int20_en8;
-    ZXIC_UINT32 smmu0_int20_en7;
-    ZXIC_UINT32 smmu0_int20_en6;
-    ZXIC_UINT32 smmu0_int20_en5;
-    ZXIC_UINT32 smmu0_int20_en4;
-    ZXIC_UINT32 smmu0_int20_en3;
-    ZXIC_UINT32 smmu0_int20_en2;
-    ZXIC_UINT32 smmu0_int20_en1;
-    ZXIC_UINT32 smmu0_int20_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT20_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int20_mask_t
-{
-    ZXIC_UINT32 smmu0_int20_mask31;
-    ZXIC_UINT32 smmu0_int20_mask30;
-    ZXIC_UINT32 smmu0_int20_mask29;
-    ZXIC_UINT32 smmu0_int20_mask28;
-    ZXIC_UINT32 smmu0_int20_mask27;
-    ZXIC_UINT32 smmu0_int20_mask26;
-    ZXIC_UINT32 smmu0_int20_mask25;
-    ZXIC_UINT32 smmu0_int20_mask24;
-    ZXIC_UINT32 smmu0_int20_mask23;
-    ZXIC_UINT32 smmu0_int20_mask22;
-    ZXIC_UINT32 smmu0_int20_mask21;
-    ZXIC_UINT32 smmu0_int20_mask20;
-    ZXIC_UINT32 smmu0_int20_mask19;
-    ZXIC_UINT32 smmu0_int20_mask18;
-    ZXIC_UINT32 smmu0_int20_mask17;
-    ZXIC_UINT32 smmu0_int20_mask16;
-    ZXIC_UINT32 smmu0_int20_mask15;
-    ZXIC_UINT32 smmu0_int20_mask14;
-    ZXIC_UINT32 smmu0_int20_mask13;
-    ZXIC_UINT32 smmu0_int20_mask12;
-    ZXIC_UINT32 smmu0_int20_mask11;
-    ZXIC_UINT32 smmu0_int20_mask10;
-    ZXIC_UINT32 smmu0_int20_mask9;
-    ZXIC_UINT32 smmu0_int20_mask8;
-    ZXIC_UINT32 smmu0_int20_mask7;
-    ZXIC_UINT32 smmu0_int20_mask6;
-    ZXIC_UINT32 smmu0_int20_mask5;
-    ZXIC_UINT32 smmu0_int20_mask4;
-    ZXIC_UINT32 smmu0_int20_mask3;
-    ZXIC_UINT32 smmu0_int20_mask2;
-    ZXIC_UINT32 smmu0_int20_mask1;
-    ZXIC_UINT32 smmu0_int20_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT20_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int20_status_t
-{
-    ZXIC_UINT32 smmu0_int20_status31;
-    ZXIC_UINT32 smmu0_int20_status30;
-    ZXIC_UINT32 smmu0_int20_status29;
-    ZXIC_UINT32 smmu0_int20_status28;
-    ZXIC_UINT32 smmu0_int20_status27;
-    ZXIC_UINT32 smmu0_int20_status26;
-    ZXIC_UINT32 smmu0_int20_status25;
-    ZXIC_UINT32 smmu0_int20_status24;
-    ZXIC_UINT32 smmu0_int20_status23;
-    ZXIC_UINT32 smmu0_int20_status22;
-    ZXIC_UINT32 smmu0_int20_status21;
-    ZXIC_UINT32 smmu0_int20_status20;
-    ZXIC_UINT32 smmu0_int20_status19;
-    ZXIC_UINT32 smmu0_int20_status18;
-    ZXIC_UINT32 smmu0_int20_status17;
-    ZXIC_UINT32 smmu0_int20_status16;
-    ZXIC_UINT32 smmu0_int20_status15;
-    ZXIC_UINT32 smmu0_int20_status14;
-    ZXIC_UINT32 smmu0_int20_status13;
-    ZXIC_UINT32 smmu0_int20_status12;
-    ZXIC_UINT32 smmu0_int20_status11;
-    ZXIC_UINT32 smmu0_int20_status10;
-    ZXIC_UINT32 smmu0_int20_status9;
-    ZXIC_UINT32 smmu0_int20_status8;
-    ZXIC_UINT32 smmu0_int20_status7;
-    ZXIC_UINT32 smmu0_int20_status6;
-    ZXIC_UINT32 smmu0_int20_status5;
-    ZXIC_UINT32 smmu0_int20_status4;
-    ZXIC_UINT32 smmu0_int20_status3;
-    ZXIC_UINT32 smmu0_int20_status2;
-    ZXIC_UINT32 smmu0_int20_status1;
-    ZXIC_UINT32 smmu0_int20_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT20_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int21_en_t
-{
-    ZXIC_UINT32 smmu0_int21_en31;
-    ZXIC_UINT32 smmu0_int21_en30;
-    ZXIC_UINT32 smmu0_int21_en29;
-    ZXIC_UINT32 smmu0_int21_en28;
-    ZXIC_UINT32 smmu0_int21_en27;
-    ZXIC_UINT32 smmu0_int21_en26;
-    ZXIC_UINT32 smmu0_int21_en25;
-    ZXIC_UINT32 smmu0_int21_en24;
-    ZXIC_UINT32 smmu0_int21_en23;
-    ZXIC_UINT32 smmu0_int21_en22;
-    ZXIC_UINT32 smmu0_int21_en21;
-    ZXIC_UINT32 smmu0_int21_en20;
-    ZXIC_UINT32 smmu0_int21_en19;
-    ZXIC_UINT32 smmu0_int21_en18;
-    ZXIC_UINT32 smmu0_int21_en17;
-    ZXIC_UINT32 smmu0_int21_en16;
-    ZXIC_UINT32 smmu0_int21_en15;
-    ZXIC_UINT32 smmu0_int21_en14;
-    ZXIC_UINT32 smmu0_int21_en13;
-    ZXIC_UINT32 smmu0_int21_en12;
-    ZXIC_UINT32 smmu0_int21_en11;
-    ZXIC_UINT32 smmu0_int21_en10;
-    ZXIC_UINT32 smmu0_int21_en9;
-    ZXIC_UINT32 smmu0_int21_en8;
-    ZXIC_UINT32 smmu0_int21_en7;
-    ZXIC_UINT32 smmu0_int21_en6;
-    ZXIC_UINT32 smmu0_int21_en5;
-    ZXIC_UINT32 smmu0_int21_en4;
-    ZXIC_UINT32 smmu0_int21_en3;
-    ZXIC_UINT32 smmu0_int21_en2;
-    ZXIC_UINT32 smmu0_int21_en1;
-    ZXIC_UINT32 smmu0_int21_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT21_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int21_mask_t
-{
-    ZXIC_UINT32 smmu0_int21_mask31;
-    ZXIC_UINT32 smmu0_int21_mask30;
-    ZXIC_UINT32 smmu0_int21_mask29;
-    ZXIC_UINT32 smmu0_int21_mask28;
-    ZXIC_UINT32 smmu0_int21_mask27;
-    ZXIC_UINT32 smmu0_int21_mask26;
-    ZXIC_UINT32 smmu0_int21_mask25;
-    ZXIC_UINT32 smmu0_int21_mask24;
-    ZXIC_UINT32 smmu0_int21_mask23;
-    ZXIC_UINT32 smmu0_int21_mask22;
-    ZXIC_UINT32 smmu0_int21_mask21;
-    ZXIC_UINT32 smmu0_int21_mask20;
-    ZXIC_UINT32 smmu0_int21_mask19;
-    ZXIC_UINT32 smmu0_int21_mask18;
-    ZXIC_UINT32 smmu0_int21_mask17;
-    ZXIC_UINT32 smmu0_int21_mask16;
-    ZXIC_UINT32 smmu0_int21_mask15;
-    ZXIC_UINT32 smmu0_int21_mask14;
-    ZXIC_UINT32 smmu0_int21_mask13;
-    ZXIC_UINT32 smmu0_int21_mask12;
-    ZXIC_UINT32 smmu0_int21_mask11;
-    ZXIC_UINT32 smmu0_int21_mask10;
-    ZXIC_UINT32 smmu0_int21_mask9;
-    ZXIC_UINT32 smmu0_int21_mask8;
-    ZXIC_UINT32 smmu0_int21_mask7;
-    ZXIC_UINT32 smmu0_int21_mask6;
-    ZXIC_UINT32 smmu0_int21_mask5;
-    ZXIC_UINT32 smmu0_int21_mask4;
-    ZXIC_UINT32 smmu0_int21_mask3;
-    ZXIC_UINT32 smmu0_int21_mask2;
-    ZXIC_UINT32 smmu0_int21_mask1;
-    ZXIC_UINT32 smmu0_int21_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT21_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int21_status_t
-{
-    ZXIC_UINT32 smmu0_int21_status31;
-    ZXIC_UINT32 smmu0_int21_status30;
-    ZXIC_UINT32 smmu0_int21_status29;
-    ZXIC_UINT32 smmu0_int21_status28;
-    ZXIC_UINT32 smmu0_int21_status27;
-    ZXIC_UINT32 smmu0_int21_status26;
-    ZXIC_UINT32 smmu0_int21_status25;
-    ZXIC_UINT32 smmu0_int21_status24;
-    ZXIC_UINT32 smmu0_int21_status23;
-    ZXIC_UINT32 smmu0_int21_status22;
-    ZXIC_UINT32 smmu0_int21_status21;
-    ZXIC_UINT32 smmu0_int21_status20;
-    ZXIC_UINT32 smmu0_int21_status19;
-    ZXIC_UINT32 smmu0_int21_status18;
-    ZXIC_UINT32 smmu0_int21_status17;
-    ZXIC_UINT32 smmu0_int21_status16;
-    ZXIC_UINT32 smmu0_int21_status15;
-    ZXIC_UINT32 smmu0_int21_status14;
-    ZXIC_UINT32 smmu0_int21_status13;
-    ZXIC_UINT32 smmu0_int21_status12;
-    ZXIC_UINT32 smmu0_int21_status11;
-    ZXIC_UINT32 smmu0_int21_status10;
-    ZXIC_UINT32 smmu0_int21_status9;
-    ZXIC_UINT32 smmu0_int21_status8;
-    ZXIC_UINT32 smmu0_int21_status7;
-    ZXIC_UINT32 smmu0_int21_status6;
-    ZXIC_UINT32 smmu0_int21_status5;
-    ZXIC_UINT32 smmu0_int21_status4;
-    ZXIC_UINT32 smmu0_int21_status3;
-    ZXIC_UINT32 smmu0_int21_status2;
-    ZXIC_UINT32 smmu0_int21_status1;
-    ZXIC_UINT32 smmu0_int21_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT21_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int22_en_t
-{
-    ZXIC_UINT32 smmu0_int22_en31;
-    ZXIC_UINT32 smmu0_int22_en30;
-    ZXIC_UINT32 smmu0_int22_en29;
-    ZXIC_UINT32 smmu0_int22_en28;
-    ZXIC_UINT32 smmu0_int22_en27;
-    ZXIC_UINT32 smmu0_int22_en26;
-    ZXIC_UINT32 smmu0_int22_en25;
-    ZXIC_UINT32 smmu0_int22_en24;
-    ZXIC_UINT32 smmu0_int22_en23;
-    ZXIC_UINT32 smmu0_int22_en22;
-    ZXIC_UINT32 smmu0_int22_en21;
-    ZXIC_UINT32 smmu0_int22_en20;
-    ZXIC_UINT32 smmu0_int22_en19;
-    ZXIC_UINT32 smmu0_int22_en18;
-    ZXIC_UINT32 smmu0_int22_en17;
-    ZXIC_UINT32 smmu0_int22_en16;
-    ZXIC_UINT32 smmu0_int22_en15;
-    ZXIC_UINT32 smmu0_int22_en14;
-    ZXIC_UINT32 smmu0_int22_en13;
-    ZXIC_UINT32 smmu0_int22_en12;
-    ZXIC_UINT32 smmu0_int22_en11;
-    ZXIC_UINT32 smmu0_int22_en10;
-    ZXIC_UINT32 smmu0_int22_en9;
-    ZXIC_UINT32 smmu0_int22_en8;
-    ZXIC_UINT32 smmu0_int22_en7;
-    ZXIC_UINT32 smmu0_int22_en6;
-    ZXIC_UINT32 smmu0_int22_en5;
-    ZXIC_UINT32 smmu0_int22_en4;
-    ZXIC_UINT32 smmu0_int22_en3;
-    ZXIC_UINT32 smmu0_int22_en2;
-    ZXIC_UINT32 smmu0_int22_en1;
-    ZXIC_UINT32 smmu0_int22_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT22_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int22_mask_t
-{
-    ZXIC_UINT32 smmu0_int22_mask31;
-    ZXIC_UINT32 smmu0_int22_mask30;
-    ZXIC_UINT32 smmu0_int22_mask29;
-    ZXIC_UINT32 smmu0_int22_mask28;
-    ZXIC_UINT32 smmu0_int22_mask27;
-    ZXIC_UINT32 smmu0_int22_mask26;
-    ZXIC_UINT32 smmu0_int22_mask25;
-    ZXIC_UINT32 smmu0_int22_mask24;
-    ZXIC_UINT32 smmu0_int22_mask23;
-    ZXIC_UINT32 smmu0_int22_mask22;
-    ZXIC_UINT32 smmu0_int22_mask21;
-    ZXIC_UINT32 smmu0_int22_mask20;
-    ZXIC_UINT32 smmu0_int22_mask19;
-    ZXIC_UINT32 smmu0_int22_mask18;
-    ZXIC_UINT32 smmu0_int22_mask17;
-    ZXIC_UINT32 smmu0_int22_mask16;
-    ZXIC_UINT32 smmu0_int22_mask15;
-    ZXIC_UINT32 smmu0_int22_mask14;
-    ZXIC_UINT32 smmu0_int22_mask13;
-    ZXIC_UINT32 smmu0_int22_mask12;
-    ZXIC_UINT32 smmu0_int22_mask11;
-    ZXIC_UINT32 smmu0_int22_mask10;
-    ZXIC_UINT32 smmu0_int22_mask9;
-    ZXIC_UINT32 smmu0_int22_mask8;
-    ZXIC_UINT32 smmu0_int22_mask7;
-    ZXIC_UINT32 smmu0_int22_mask6;
-    ZXIC_UINT32 smmu0_int22_mask5;
-    ZXIC_UINT32 smmu0_int22_mask4;
-    ZXIC_UINT32 smmu0_int22_mask3;
-    ZXIC_UINT32 smmu0_int22_mask2;
-    ZXIC_UINT32 smmu0_int22_mask1;
-    ZXIC_UINT32 smmu0_int22_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT22_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int22_status_t
-{
-    ZXIC_UINT32 smmu0_int22_status31;
-    ZXIC_UINT32 smmu0_int22_status30;
-    ZXIC_UINT32 smmu0_int22_status29;
-    ZXIC_UINT32 smmu0_int22_status28;
-    ZXIC_UINT32 smmu0_int22_status27;
-    ZXIC_UINT32 smmu0_int22_status26;
-    ZXIC_UINT32 smmu0_int22_status25;
-    ZXIC_UINT32 smmu0_int22_status24;
-    ZXIC_UINT32 smmu0_int22_status23;
-    ZXIC_UINT32 smmu0_int22_status22;
-    ZXIC_UINT32 smmu0_int22_status21;
-    ZXIC_UINT32 smmu0_int22_status20;
-    ZXIC_UINT32 smmu0_int22_status19;
-    ZXIC_UINT32 smmu0_int22_status18;
-    ZXIC_UINT32 smmu0_int22_status17;
-    ZXIC_UINT32 smmu0_int22_status16;
-    ZXIC_UINT32 smmu0_int22_status15;
-    ZXIC_UINT32 smmu0_int22_status14;
-    ZXIC_UINT32 smmu0_int22_status13;
-    ZXIC_UINT32 smmu0_int22_status12;
-    ZXIC_UINT32 smmu0_int22_status11;
-    ZXIC_UINT32 smmu0_int22_status10;
-    ZXIC_UINT32 smmu0_int22_status9;
-    ZXIC_UINT32 smmu0_int22_status8;
-    ZXIC_UINT32 smmu0_int22_status7;
-    ZXIC_UINT32 smmu0_int22_status6;
-    ZXIC_UINT32 smmu0_int22_status5;
-    ZXIC_UINT32 smmu0_int22_status4;
-    ZXIC_UINT32 smmu0_int22_status3;
-    ZXIC_UINT32 smmu0_int22_status2;
-    ZXIC_UINT32 smmu0_int22_status1;
-    ZXIC_UINT32 smmu0_int22_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT22_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int23_en_t
-{
-    ZXIC_UINT32 smmu0_int23_en31;
-    ZXIC_UINT32 smmu0_int23_en30;
-    ZXIC_UINT32 smmu0_int23_en29;
-    ZXIC_UINT32 smmu0_int23_en28;
-    ZXIC_UINT32 smmu0_int23_en27;
-    ZXIC_UINT32 smmu0_int23_en26;
-    ZXIC_UINT32 smmu0_int23_en25;
-    ZXIC_UINT32 smmu0_int23_en24;
-    ZXIC_UINT32 smmu0_int23_en23;
-    ZXIC_UINT32 smmu0_int23_en22;
-    ZXIC_UINT32 smmu0_int23_en21;
-    ZXIC_UINT32 smmu0_int23_en20;
-    ZXIC_UINT32 smmu0_int23_en19;
-    ZXIC_UINT32 smmu0_int23_en18;
-    ZXIC_UINT32 smmu0_int23_en17;
-    ZXIC_UINT32 smmu0_int23_en16;
-    ZXIC_UINT32 smmu0_int23_en15;
-    ZXIC_UINT32 smmu0_int23_en14;
-    ZXIC_UINT32 smmu0_int23_en13;
-    ZXIC_UINT32 smmu0_int23_en12;
-    ZXIC_UINT32 smmu0_int23_en11;
-    ZXIC_UINT32 smmu0_int23_en10;
-    ZXIC_UINT32 smmu0_int23_en9;
-    ZXIC_UINT32 smmu0_int23_en8;
-    ZXIC_UINT32 smmu0_int23_en7;
-    ZXIC_UINT32 smmu0_int23_en6;
-    ZXIC_UINT32 smmu0_int23_en5;
-    ZXIC_UINT32 smmu0_int23_en4;
-    ZXIC_UINT32 smmu0_int23_en3;
-    ZXIC_UINT32 smmu0_int23_en2;
-    ZXIC_UINT32 smmu0_int23_en1;
-    ZXIC_UINT32 smmu0_int23_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT23_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int23_mask_t
-{
-    ZXIC_UINT32 smmu0_int23_mask31;
-    ZXIC_UINT32 smmu0_int23_mask30;
-    ZXIC_UINT32 smmu0_int23_mask29;
-    ZXIC_UINT32 smmu0_int23_mask28;
-    ZXIC_UINT32 smmu0_int23_mask27;
-    ZXIC_UINT32 smmu0_int23_mask26;
-    ZXIC_UINT32 smmu0_int23_mask25;
-    ZXIC_UINT32 smmu0_int23_mask24;
-    ZXIC_UINT32 smmu0_int23_mask23;
-    ZXIC_UINT32 smmu0_int23_mask22;
-    ZXIC_UINT32 smmu0_int23_mask21;
-    ZXIC_UINT32 smmu0_int23_mask20;
-    ZXIC_UINT32 smmu0_int23_mask19;
-    ZXIC_UINT32 smmu0_int23_mask18;
-    ZXIC_UINT32 smmu0_int23_mask17;
-    ZXIC_UINT32 smmu0_int23_mask16;
-    ZXIC_UINT32 smmu0_int23_mask15;
-    ZXIC_UINT32 smmu0_int23_mask14;
-    ZXIC_UINT32 smmu0_int23_mask13;
-    ZXIC_UINT32 smmu0_int23_mask12;
-    ZXIC_UINT32 smmu0_int23_mask11;
-    ZXIC_UINT32 smmu0_int23_mask10;
-    ZXIC_UINT32 smmu0_int23_mask9;
-    ZXIC_UINT32 smmu0_int23_mask8;
-    ZXIC_UINT32 smmu0_int23_mask7;
-    ZXIC_UINT32 smmu0_int23_mask6;
-    ZXIC_UINT32 smmu0_int23_mask5;
-    ZXIC_UINT32 smmu0_int23_mask4;
-    ZXIC_UINT32 smmu0_int23_mask3;
-    ZXIC_UINT32 smmu0_int23_mask2;
-    ZXIC_UINT32 smmu0_int23_mask1;
-    ZXIC_UINT32 smmu0_int23_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT23_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int23_status_t
-{
-    ZXIC_UINT32 smmu0_int23_status31;
-    ZXIC_UINT32 smmu0_int23_status30;
-    ZXIC_UINT32 smmu0_int23_status29;
-    ZXIC_UINT32 smmu0_int23_status28;
-    ZXIC_UINT32 smmu0_int23_status27;
-    ZXIC_UINT32 smmu0_int23_status26;
-    ZXIC_UINT32 smmu0_int23_status25;
-    ZXIC_UINT32 smmu0_int23_status24;
-    ZXIC_UINT32 smmu0_int23_status23;
-    ZXIC_UINT32 smmu0_int23_status22;
-    ZXIC_UINT32 smmu0_int23_status21;
-    ZXIC_UINT32 smmu0_int23_status20;
-    ZXIC_UINT32 smmu0_int23_status19;
-    ZXIC_UINT32 smmu0_int23_status18;
-    ZXIC_UINT32 smmu0_int23_status17;
-    ZXIC_UINT32 smmu0_int23_status16;
-    ZXIC_UINT32 smmu0_int23_status15;
-    ZXIC_UINT32 smmu0_int23_status14;
-    ZXIC_UINT32 smmu0_int23_status13;
-    ZXIC_UINT32 smmu0_int23_status12;
-    ZXIC_UINT32 smmu0_int23_status11;
-    ZXIC_UINT32 smmu0_int23_status10;
-    ZXIC_UINT32 smmu0_int23_status9;
-    ZXIC_UINT32 smmu0_int23_status8;
-    ZXIC_UINT32 smmu0_int23_status7;
-    ZXIC_UINT32 smmu0_int23_status6;
-    ZXIC_UINT32 smmu0_int23_status5;
-    ZXIC_UINT32 smmu0_int23_status4;
-    ZXIC_UINT32 smmu0_int23_status3;
-    ZXIC_UINT32 smmu0_int23_status2;
-    ZXIC_UINT32 smmu0_int23_status1;
-    ZXIC_UINT32 smmu0_int23_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT23_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int24_en_t
-{
-    ZXIC_UINT32 smmu0_int24_en31;
-    ZXIC_UINT32 smmu0_int24_en30;
-    ZXIC_UINT32 smmu0_int24_en29;
-    ZXIC_UINT32 smmu0_int24_en28;
-    ZXIC_UINT32 smmu0_int24_en27;
-    ZXIC_UINT32 smmu0_int24_en26;
-    ZXIC_UINT32 smmu0_int24_en25;
-    ZXIC_UINT32 smmu0_int24_en24;
-    ZXIC_UINT32 smmu0_int24_en23;
-    ZXIC_UINT32 smmu0_int24_en22;
-    ZXIC_UINT32 smmu0_int24_en21;
-    ZXIC_UINT32 smmu0_int24_en20;
-    ZXIC_UINT32 smmu0_int24_en19;
-    ZXIC_UINT32 smmu0_int24_en18;
-    ZXIC_UINT32 smmu0_int24_en17;
-    ZXIC_UINT32 smmu0_int24_en16;
-    ZXIC_UINT32 smmu0_int24_en15;
-    ZXIC_UINT32 smmu0_int24_en14;
-    ZXIC_UINT32 smmu0_int24_en13;
-    ZXIC_UINT32 smmu0_int24_en12;
-    ZXIC_UINT32 smmu0_int24_en11;
-    ZXIC_UINT32 smmu0_int24_en10;
-    ZXIC_UINT32 smmu0_int24_en9;
-    ZXIC_UINT32 smmu0_int24_en8;
-    ZXIC_UINT32 smmu0_int24_en7;
-    ZXIC_UINT32 smmu0_int24_en6;
-    ZXIC_UINT32 smmu0_int24_en5;
-    ZXIC_UINT32 smmu0_int24_en4;
-    ZXIC_UINT32 smmu0_int24_en3;
-    ZXIC_UINT32 smmu0_int24_en2;
-    ZXIC_UINT32 smmu0_int24_en1;
-    ZXIC_UINT32 smmu0_int24_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT24_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int24_mask_t
-{
-    ZXIC_UINT32 smmu0_int24_mask31;
-    ZXIC_UINT32 smmu0_int24_mask30;
-    ZXIC_UINT32 smmu0_int24_mask29;
-    ZXIC_UINT32 smmu0_int24_mask28;
-    ZXIC_UINT32 smmu0_int24_mask27;
-    ZXIC_UINT32 smmu0_int24_mask26;
-    ZXIC_UINT32 smmu0_int24_mask25;
-    ZXIC_UINT32 smmu0_int24_mask24;
-    ZXIC_UINT32 smmu0_int24_mask23;
-    ZXIC_UINT32 smmu0_int24_mask22;
-    ZXIC_UINT32 smmu0_int24_mask21;
-    ZXIC_UINT32 smmu0_int24_mask20;
-    ZXIC_UINT32 smmu0_int24_mask19;
-    ZXIC_UINT32 smmu0_int24_mask18;
-    ZXIC_UINT32 smmu0_int24_mask17;
-    ZXIC_UINT32 smmu0_int24_mask16;
-    ZXIC_UINT32 smmu0_int24_mask15;
-    ZXIC_UINT32 smmu0_int24_mask14;
-    ZXIC_UINT32 smmu0_int24_mask13;
-    ZXIC_UINT32 smmu0_int24_mask12;
-    ZXIC_UINT32 smmu0_int24_mask11;
-    ZXIC_UINT32 smmu0_int24_mask10;
-    ZXIC_UINT32 smmu0_int24_mask9;
-    ZXIC_UINT32 smmu0_int24_mask8;
-    ZXIC_UINT32 smmu0_int24_mask7;
-    ZXIC_UINT32 smmu0_int24_mask6;
-    ZXIC_UINT32 smmu0_int24_mask5;
-    ZXIC_UINT32 smmu0_int24_mask4;
-    ZXIC_UINT32 smmu0_int24_mask3;
-    ZXIC_UINT32 smmu0_int24_mask2;
-    ZXIC_UINT32 smmu0_int24_mask1;
-    ZXIC_UINT32 smmu0_int24_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT24_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int24_status_t
-{
-    ZXIC_UINT32 smmu0_int24_status31;
-    ZXIC_UINT32 smmu0_int24_status30;
-    ZXIC_UINT32 smmu0_int24_status29;
-    ZXIC_UINT32 smmu0_int24_status28;
-    ZXIC_UINT32 smmu0_int24_status27;
-    ZXIC_UINT32 smmu0_int24_status26;
-    ZXIC_UINT32 smmu0_int24_status25;
-    ZXIC_UINT32 smmu0_int24_status24;
-    ZXIC_UINT32 smmu0_int24_status23;
-    ZXIC_UINT32 smmu0_int24_status22;
-    ZXIC_UINT32 smmu0_int24_status21;
-    ZXIC_UINT32 smmu0_int24_status20;
-    ZXIC_UINT32 smmu0_int24_status19;
-    ZXIC_UINT32 smmu0_int24_status18;
-    ZXIC_UINT32 smmu0_int24_status17;
-    ZXIC_UINT32 smmu0_int24_status16;
-    ZXIC_UINT32 smmu0_int24_status15;
-    ZXIC_UINT32 smmu0_int24_status14;
-    ZXIC_UINT32 smmu0_int24_status13;
-    ZXIC_UINT32 smmu0_int24_status12;
-    ZXIC_UINT32 smmu0_int24_status11;
-    ZXIC_UINT32 smmu0_int24_status10;
-    ZXIC_UINT32 smmu0_int24_status9;
-    ZXIC_UINT32 smmu0_int24_status8;
-    ZXIC_UINT32 smmu0_int24_status7;
-    ZXIC_UINT32 smmu0_int24_status6;
-    ZXIC_UINT32 smmu0_int24_status5;
-    ZXIC_UINT32 smmu0_int24_status4;
-    ZXIC_UINT32 smmu0_int24_status3;
-    ZXIC_UINT32 smmu0_int24_status2;
-    ZXIC_UINT32 smmu0_int24_status1;
-    ZXIC_UINT32 smmu0_int24_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT24_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int25_en_t
-{
-    ZXIC_UINT32 smmu0_int25_en31;
-    ZXIC_UINT32 smmu0_int25_en30;
-    ZXIC_UINT32 smmu0_int25_en29;
-    ZXIC_UINT32 smmu0_int25_en28;
-    ZXIC_UINT32 smmu0_int25_en27;
-    ZXIC_UINT32 smmu0_int25_en26;
-    ZXIC_UINT32 smmu0_int25_en25;
-    ZXIC_UINT32 smmu0_int25_en24;
-    ZXIC_UINT32 smmu0_int25_en23;
-    ZXIC_UINT32 smmu0_int25_en22;
-    ZXIC_UINT32 smmu0_int25_en21;
-    ZXIC_UINT32 smmu0_int25_en20;
-    ZXIC_UINT32 smmu0_int25_en19;
-    ZXIC_UINT32 smmu0_int25_en18;
-    ZXIC_UINT32 smmu0_int25_en17;
-    ZXIC_UINT32 smmu0_int25_en16;
-    ZXIC_UINT32 smmu0_int25_en15;
-    ZXIC_UINT32 smmu0_int25_en14;
-    ZXIC_UINT32 smmu0_int25_en13;
-    ZXIC_UINT32 smmu0_int25_en12;
-    ZXIC_UINT32 smmu0_int25_en11;
-    ZXIC_UINT32 smmu0_int25_en10;
-    ZXIC_UINT32 smmu0_int25_en9;
-    ZXIC_UINT32 smmu0_int25_en8;
-    ZXIC_UINT32 smmu0_int25_en7;
-    ZXIC_UINT32 smmu0_int25_en6;
-    ZXIC_UINT32 smmu0_int25_en5;
-    ZXIC_UINT32 smmu0_int25_en4;
-    ZXIC_UINT32 smmu0_int25_en3;
-    ZXIC_UINT32 smmu0_int25_en2;
-    ZXIC_UINT32 smmu0_int25_en1;
-    ZXIC_UINT32 smmu0_int25_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT25_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int25_mask_t
-{
-    ZXIC_UINT32 smmu0_int25_mask31;
-    ZXIC_UINT32 smmu0_int25_mask30;
-    ZXIC_UINT32 smmu0_int25_mask29;
-    ZXIC_UINT32 smmu0_int25_mask28;
-    ZXIC_UINT32 smmu0_int25_mask27;
-    ZXIC_UINT32 smmu0_int25_mask26;
-    ZXIC_UINT32 smmu0_int25_mask25;
-    ZXIC_UINT32 smmu0_int25_mask24;
-    ZXIC_UINT32 smmu0_int25_mask23;
-    ZXIC_UINT32 smmu0_int25_mask22;
-    ZXIC_UINT32 smmu0_int25_mask21;
-    ZXIC_UINT32 smmu0_int25_mask20;
-    ZXIC_UINT32 smmu0_int25_mask19;
-    ZXIC_UINT32 smmu0_int25_mask18;
-    ZXIC_UINT32 smmu0_int25_mask17;
-    ZXIC_UINT32 smmu0_int25_mask16;
-    ZXIC_UINT32 smmu0_int25_mask15;
-    ZXIC_UINT32 smmu0_int25_mask14;
-    ZXIC_UINT32 smmu0_int25_mask13;
-    ZXIC_UINT32 smmu0_int25_mask12;
-    ZXIC_UINT32 smmu0_int25_mask11;
-    ZXIC_UINT32 smmu0_int25_mask10;
-    ZXIC_UINT32 smmu0_int25_mask9;
-    ZXIC_UINT32 smmu0_int25_mask8;
-    ZXIC_UINT32 smmu0_int25_mask7;
-    ZXIC_UINT32 smmu0_int25_mask6;
-    ZXIC_UINT32 smmu0_int25_mask5;
-    ZXIC_UINT32 smmu0_int25_mask4;
-    ZXIC_UINT32 smmu0_int25_mask3;
-    ZXIC_UINT32 smmu0_int25_mask2;
-    ZXIC_UINT32 smmu0_int25_mask1;
-    ZXIC_UINT32 smmu0_int25_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT25_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int25_status_t
-{
-    ZXIC_UINT32 smmu0_int25_status31;
-    ZXIC_UINT32 smmu0_int25_status30;
-    ZXIC_UINT32 smmu0_int25_status29;
-    ZXIC_UINT32 smmu0_int25_status28;
-    ZXIC_UINT32 smmu0_int25_status27;
-    ZXIC_UINT32 smmu0_int25_status26;
-    ZXIC_UINT32 smmu0_int25_status25;
-    ZXIC_UINT32 smmu0_int25_status24;
-    ZXIC_UINT32 smmu0_int25_status23;
-    ZXIC_UINT32 smmu0_int25_status22;
-    ZXIC_UINT32 smmu0_int25_status21;
-    ZXIC_UINT32 smmu0_int25_status20;
-    ZXIC_UINT32 smmu0_int25_status19;
-    ZXIC_UINT32 smmu0_int25_status18;
-    ZXIC_UINT32 smmu0_int25_status17;
-    ZXIC_UINT32 smmu0_int25_status16;
-    ZXIC_UINT32 smmu0_int25_status15;
-    ZXIC_UINT32 smmu0_int25_status14;
-    ZXIC_UINT32 smmu0_int25_status13;
-    ZXIC_UINT32 smmu0_int25_status12;
-    ZXIC_UINT32 smmu0_int25_status11;
-    ZXIC_UINT32 smmu0_int25_status10;
-    ZXIC_UINT32 smmu0_int25_status9;
-    ZXIC_UINT32 smmu0_int25_status8;
-    ZXIC_UINT32 smmu0_int25_status7;
-    ZXIC_UINT32 smmu0_int25_status6;
-    ZXIC_UINT32 smmu0_int25_status5;
-    ZXIC_UINT32 smmu0_int25_status4;
-    ZXIC_UINT32 smmu0_int25_status3;
-    ZXIC_UINT32 smmu0_int25_status2;
-    ZXIC_UINT32 smmu0_int25_status1;
-    ZXIC_UINT32 smmu0_int25_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT25_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int26_en_t
-{
-    ZXIC_UINT32 smmu0_int26_en31;
-    ZXIC_UINT32 smmu0_int26_en30;
-    ZXIC_UINT32 smmu0_int26_en29;
-    ZXIC_UINT32 smmu0_int26_en28;
-    ZXIC_UINT32 smmu0_int26_en27;
-    ZXIC_UINT32 smmu0_int26_en26;
-    ZXIC_UINT32 smmu0_int26_en25;
-    ZXIC_UINT32 smmu0_int26_en24;
-    ZXIC_UINT32 smmu0_int26_en23;
-    ZXIC_UINT32 smmu0_int26_en22;
-    ZXIC_UINT32 smmu0_int26_en21;
-    ZXIC_UINT32 smmu0_int26_en20;
-    ZXIC_UINT32 smmu0_int26_en19;
-    ZXIC_UINT32 smmu0_int26_en18;
-    ZXIC_UINT32 smmu0_int26_en17;
-    ZXIC_UINT32 smmu0_int26_en16;
-    ZXIC_UINT32 smmu0_int26_en15;
-    ZXIC_UINT32 smmu0_int26_en14;
-    ZXIC_UINT32 smmu0_int26_en13;
-    ZXIC_UINT32 smmu0_int26_en12;
-    ZXIC_UINT32 smmu0_int26_en11;
-    ZXIC_UINT32 smmu0_int26_en10;
-    ZXIC_UINT32 smmu0_int26_en9;
-    ZXIC_UINT32 smmu0_int26_en8;
-    ZXIC_UINT32 smmu0_int26_en7;
-    ZXIC_UINT32 smmu0_int26_en6;
-    ZXIC_UINT32 smmu0_int26_en5;
-    ZXIC_UINT32 smmu0_int26_en4;
-    ZXIC_UINT32 smmu0_int26_en3;
-    ZXIC_UINT32 smmu0_int26_en2;
-    ZXIC_UINT32 smmu0_int26_en1;
-    ZXIC_UINT32 smmu0_int26_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT26_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int26_mask_t
-{
-    ZXIC_UINT32 smmu0_int26_mask31;
-    ZXIC_UINT32 smmu0_int26_mask30;
-    ZXIC_UINT32 smmu0_int26_mask29;
-    ZXIC_UINT32 smmu0_int26_mask28;
-    ZXIC_UINT32 smmu0_int26_mask27;
-    ZXIC_UINT32 smmu0_int26_mask26;
-    ZXIC_UINT32 smmu0_int26_mask25;
-    ZXIC_UINT32 smmu0_int26_mask24;
-    ZXIC_UINT32 smmu0_int26_mask23;
-    ZXIC_UINT32 smmu0_int26_mask22;
-    ZXIC_UINT32 smmu0_int26_mask21;
-    ZXIC_UINT32 smmu0_int26_mask20;
-    ZXIC_UINT32 smmu0_int26_mask19;
-    ZXIC_UINT32 smmu0_int26_mask18;
-    ZXIC_UINT32 smmu0_int26_mask17;
-    ZXIC_UINT32 smmu0_int26_mask16;
-    ZXIC_UINT32 smmu0_int26_mask15;
-    ZXIC_UINT32 smmu0_int26_mask14;
-    ZXIC_UINT32 smmu0_int26_mask13;
-    ZXIC_UINT32 smmu0_int26_mask12;
-    ZXIC_UINT32 smmu0_int26_mask11;
-    ZXIC_UINT32 smmu0_int26_mask10;
-    ZXIC_UINT32 smmu0_int26_mask9;
-    ZXIC_UINT32 smmu0_int26_mask8;
-    ZXIC_UINT32 smmu0_int26_mask7;
-    ZXIC_UINT32 smmu0_int26_mask6;
-    ZXIC_UINT32 smmu0_int26_mask5;
-    ZXIC_UINT32 smmu0_int26_mask4;
-    ZXIC_UINT32 smmu0_int26_mask3;
-    ZXIC_UINT32 smmu0_int26_mask2;
-    ZXIC_UINT32 smmu0_int26_mask1;
-    ZXIC_UINT32 smmu0_int26_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT26_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int26_status_t
-{
-    ZXIC_UINT32 smmu0_int26_status31;
-    ZXIC_UINT32 smmu0_int26_status30;
-    ZXIC_UINT32 smmu0_int26_status29;
-    ZXIC_UINT32 smmu0_int26_status28;
-    ZXIC_UINT32 smmu0_int26_status27;
-    ZXIC_UINT32 smmu0_int26_status26;
-    ZXIC_UINT32 smmu0_int26_status25;
-    ZXIC_UINT32 smmu0_int26_status24;
-    ZXIC_UINT32 smmu0_int26_status23;
-    ZXIC_UINT32 smmu0_int26_status22;
-    ZXIC_UINT32 smmu0_int26_status21;
-    ZXIC_UINT32 smmu0_int26_status20;
-    ZXIC_UINT32 smmu0_int26_status19;
-    ZXIC_UINT32 smmu0_int26_status18;
-    ZXIC_UINT32 smmu0_int26_status17;
-    ZXIC_UINT32 smmu0_int26_status16;
-    ZXIC_UINT32 smmu0_int26_status15;
-    ZXIC_UINT32 smmu0_int26_status14;
-    ZXIC_UINT32 smmu0_int26_status13;
-    ZXIC_UINT32 smmu0_int26_status12;
-    ZXIC_UINT32 smmu0_int26_status11;
-    ZXIC_UINT32 smmu0_int26_status10;
-    ZXIC_UINT32 smmu0_int26_status9;
-    ZXIC_UINT32 smmu0_int26_status8;
-    ZXIC_UINT32 smmu0_int26_status7;
-    ZXIC_UINT32 smmu0_int26_status6;
-    ZXIC_UINT32 smmu0_int26_status5;
-    ZXIC_UINT32 smmu0_int26_status4;
-    ZXIC_UINT32 smmu0_int26_status3;
-    ZXIC_UINT32 smmu0_int26_status2;
-    ZXIC_UINT32 smmu0_int26_status1;
-    ZXIC_UINT32 smmu0_int26_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT26_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int27_en_t
-{
-    ZXIC_UINT32 smmu0_int27_en31;
-    ZXIC_UINT32 smmu0_int27_en30;
-    ZXIC_UINT32 smmu0_int27_en29;
-    ZXIC_UINT32 smmu0_int27_en28;
-    ZXIC_UINT32 smmu0_int27_en27;
-    ZXIC_UINT32 smmu0_int27_en26;
-    ZXIC_UINT32 smmu0_int27_en25;
-    ZXIC_UINT32 smmu0_int27_en24;
-    ZXIC_UINT32 smmu0_int27_en23;
-    ZXIC_UINT32 smmu0_int27_en22;
-    ZXIC_UINT32 smmu0_int27_en21;
-    ZXIC_UINT32 smmu0_int27_en20;
-    ZXIC_UINT32 smmu0_int27_en19;
-    ZXIC_UINT32 smmu0_int27_en18;
-    ZXIC_UINT32 smmu0_int27_en17;
-    ZXIC_UINT32 smmu0_int27_en16;
-    ZXIC_UINT32 smmu0_int27_en15;
-    ZXIC_UINT32 smmu0_int27_en14;
-    ZXIC_UINT32 smmu0_int27_en13;
-    ZXIC_UINT32 smmu0_int27_en12;
-    ZXIC_UINT32 smmu0_int27_en11;
-    ZXIC_UINT32 smmu0_int27_en10;
-    ZXIC_UINT32 smmu0_int27_en9;
-    ZXIC_UINT32 smmu0_int27_en8;
-    ZXIC_UINT32 smmu0_int27_en7;
-    ZXIC_UINT32 smmu0_int27_en6;
-    ZXIC_UINT32 smmu0_int27_en5;
-    ZXIC_UINT32 smmu0_int27_en4;
-    ZXIC_UINT32 smmu0_int27_en3;
-    ZXIC_UINT32 smmu0_int27_en2;
-    ZXIC_UINT32 smmu0_int27_en1;
-    ZXIC_UINT32 smmu0_int27_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT27_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int27_mask_t
-{
-    ZXIC_UINT32 smmu0_int27_mask31;
-    ZXIC_UINT32 smmu0_int27_mask30;
-    ZXIC_UINT32 smmu0_int27_mask29;
-    ZXIC_UINT32 smmu0_int27_mask28;
-    ZXIC_UINT32 smmu0_int27_mask27;
-    ZXIC_UINT32 smmu0_int27_mask26;
-    ZXIC_UINT32 smmu0_int27_mask25;
-    ZXIC_UINT32 smmu0_int27_mask24;
-    ZXIC_UINT32 smmu0_int27_mask23;
-    ZXIC_UINT32 smmu0_int27_mask22;
-    ZXIC_UINT32 smmu0_int27_mask21;
-    ZXIC_UINT32 smmu0_int27_mask20;
-    ZXIC_UINT32 smmu0_int27_mask19;
-    ZXIC_UINT32 smmu0_int27_mask18;
-    ZXIC_UINT32 smmu0_int27_mask17;
-    ZXIC_UINT32 smmu0_int27_mask16;
-    ZXIC_UINT32 smmu0_int27_mask15;
-    ZXIC_UINT32 smmu0_int27_mask14;
-    ZXIC_UINT32 smmu0_int27_mask13;
-    ZXIC_UINT32 smmu0_int27_mask12;
-    ZXIC_UINT32 smmu0_int27_mask11;
-    ZXIC_UINT32 smmu0_int27_mask10;
-    ZXIC_UINT32 smmu0_int27_mask9;
-    ZXIC_UINT32 smmu0_int27_mask8;
-    ZXIC_UINT32 smmu0_int27_mask7;
-    ZXIC_UINT32 smmu0_int27_mask6;
-    ZXIC_UINT32 smmu0_int27_mask5;
-    ZXIC_UINT32 smmu0_int27_mask4;
-    ZXIC_UINT32 smmu0_int27_mask3;
-    ZXIC_UINT32 smmu0_int27_mask2;
-    ZXIC_UINT32 smmu0_int27_mask1;
-    ZXIC_UINT32 smmu0_int27_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT27_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int27_status_t
-{
-    ZXIC_UINT32 smmu0_int27_status31;
-    ZXIC_UINT32 smmu0_int27_status30;
-    ZXIC_UINT32 smmu0_int27_status29;
-    ZXIC_UINT32 smmu0_int27_status28;
-    ZXIC_UINT32 smmu0_int27_status27;
-    ZXIC_UINT32 smmu0_int27_status26;
-    ZXIC_UINT32 smmu0_int27_status25;
-    ZXIC_UINT32 smmu0_int27_status24;
-    ZXIC_UINT32 smmu0_int27_status23;
-    ZXIC_UINT32 smmu0_int27_status22;
-    ZXIC_UINT32 smmu0_int27_status21;
-    ZXIC_UINT32 smmu0_int27_status20;
-    ZXIC_UINT32 smmu0_int27_status19;
-    ZXIC_UINT32 smmu0_int27_status18;
-    ZXIC_UINT32 smmu0_int27_status17;
-    ZXIC_UINT32 smmu0_int27_status16;
-    ZXIC_UINT32 smmu0_int27_status15;
-    ZXIC_UINT32 smmu0_int27_status14;
-    ZXIC_UINT32 smmu0_int27_status13;
-    ZXIC_UINT32 smmu0_int27_status12;
-    ZXIC_UINT32 smmu0_int27_status11;
-    ZXIC_UINT32 smmu0_int27_status10;
-    ZXIC_UINT32 smmu0_int27_status9;
-    ZXIC_UINT32 smmu0_int27_status8;
-    ZXIC_UINT32 smmu0_int27_status7;
-    ZXIC_UINT32 smmu0_int27_status6;
-    ZXIC_UINT32 smmu0_int27_status5;
-    ZXIC_UINT32 smmu0_int27_status4;
-    ZXIC_UINT32 smmu0_int27_status3;
-    ZXIC_UINT32 smmu0_int27_status2;
-    ZXIC_UINT32 smmu0_int27_status1;
-    ZXIC_UINT32 smmu0_int27_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT27_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int28_en_t
-{
-    ZXIC_UINT32 smmu0_int28_en31;
-    ZXIC_UINT32 smmu0_int28_en30;
-    ZXIC_UINT32 smmu0_int28_en29;
-    ZXIC_UINT32 smmu0_int28_en28;
-    ZXIC_UINT32 smmu0_int28_en27;
-    ZXIC_UINT32 smmu0_int28_en26;
-    ZXIC_UINT32 smmu0_int28_en25;
-    ZXIC_UINT32 smmu0_int28_en24;
-    ZXIC_UINT32 smmu0_int28_en23;
-    ZXIC_UINT32 smmu0_int28_en22;
-    ZXIC_UINT32 smmu0_int28_en21;
-    ZXIC_UINT32 smmu0_int28_en20;
-    ZXIC_UINT32 smmu0_int28_en19;
-    ZXIC_UINT32 smmu0_int28_en18;
-    ZXIC_UINT32 smmu0_int28_en17;
-    ZXIC_UINT32 smmu0_int28_en16;
-    ZXIC_UINT32 smmu0_int28_en15;
-    ZXIC_UINT32 smmu0_int28_en14;
-    ZXIC_UINT32 smmu0_int28_en13;
-    ZXIC_UINT32 smmu0_int28_en12;
-    ZXIC_UINT32 smmu0_int28_en11;
-    ZXIC_UINT32 smmu0_int28_en10;
-    ZXIC_UINT32 smmu0_int28_en9;
-    ZXIC_UINT32 smmu0_int28_en8;
-    ZXIC_UINT32 smmu0_int28_en7;
-    ZXIC_UINT32 smmu0_int28_en6;
-    ZXIC_UINT32 smmu0_int28_en5;
-    ZXIC_UINT32 smmu0_int28_en4;
-    ZXIC_UINT32 smmu0_int28_en3;
-    ZXIC_UINT32 smmu0_int28_en2;
-    ZXIC_UINT32 smmu0_int28_en1;
-    ZXIC_UINT32 smmu0_int28_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT28_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int28_mask_t
-{
-    ZXIC_UINT32 smmu0_int28_mask31;
-    ZXIC_UINT32 smmu0_int28_mask30;
-    ZXIC_UINT32 smmu0_int28_mask29;
-    ZXIC_UINT32 smmu0_int28_mask28;
-    ZXIC_UINT32 smmu0_int28_mask27;
-    ZXIC_UINT32 smmu0_int28_mask26;
-    ZXIC_UINT32 smmu0_int28_mask25;
-    ZXIC_UINT32 smmu0_int28_mask24;
-    ZXIC_UINT32 smmu0_int28_mask23;
-    ZXIC_UINT32 smmu0_int28_mask22;
-    ZXIC_UINT32 smmu0_int28_mask21;
-    ZXIC_UINT32 smmu0_int28_mask20;
-    ZXIC_UINT32 smmu0_int28_mask19;
-    ZXIC_UINT32 smmu0_int28_mask18;
-    ZXIC_UINT32 smmu0_int28_mask17;
-    ZXIC_UINT32 smmu0_int28_mask16;
-    ZXIC_UINT32 smmu0_int28_mask15;
-    ZXIC_UINT32 smmu0_int28_mask14;
-    ZXIC_UINT32 smmu0_int28_mask13;
-    ZXIC_UINT32 smmu0_int28_mask12;
-    ZXIC_UINT32 smmu0_int28_mask11;
-    ZXIC_UINT32 smmu0_int28_mask10;
-    ZXIC_UINT32 smmu0_int28_mask9;
-    ZXIC_UINT32 smmu0_int28_mask8;
-    ZXIC_UINT32 smmu0_int28_mask7;
-    ZXIC_UINT32 smmu0_int28_mask6;
-    ZXIC_UINT32 smmu0_int28_mask5;
-    ZXIC_UINT32 smmu0_int28_mask4;
-    ZXIC_UINT32 smmu0_int28_mask3;
-    ZXIC_UINT32 smmu0_int28_mask2;
-    ZXIC_UINT32 smmu0_int28_mask1;
-    ZXIC_UINT32 smmu0_int28_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT28_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int28_status_t
-{
-    ZXIC_UINT32 smmu0_int28_status31;
-    ZXIC_UINT32 smmu0_int28_status30;
-    ZXIC_UINT32 smmu0_int28_status29;
-    ZXIC_UINT32 smmu0_int28_status28;
-    ZXIC_UINT32 smmu0_int28_status27;
-    ZXIC_UINT32 smmu0_int28_status26;
-    ZXIC_UINT32 smmu0_int28_status25;
-    ZXIC_UINT32 smmu0_int28_status24;
-    ZXIC_UINT32 smmu0_int28_status23;
-    ZXIC_UINT32 smmu0_int28_status22;
-    ZXIC_UINT32 smmu0_int28_status21;
-    ZXIC_UINT32 smmu0_int28_status20;
-    ZXIC_UINT32 smmu0_int28_status19;
-    ZXIC_UINT32 smmu0_int28_status18;
-    ZXIC_UINT32 smmu0_int28_status17;
-    ZXIC_UINT32 smmu0_int28_status16;
-    ZXIC_UINT32 smmu0_int28_status15;
-    ZXIC_UINT32 smmu0_int28_status14;
-    ZXIC_UINT32 smmu0_int28_status13;
-    ZXIC_UINT32 smmu0_int28_status12;
-    ZXIC_UINT32 smmu0_int28_status11;
-    ZXIC_UINT32 smmu0_int28_status10;
-    ZXIC_UINT32 smmu0_int28_status9;
-    ZXIC_UINT32 smmu0_int28_status8;
-    ZXIC_UINT32 smmu0_int28_status7;
-    ZXIC_UINT32 smmu0_int28_status6;
-    ZXIC_UINT32 smmu0_int28_status5;
-    ZXIC_UINT32 smmu0_int28_status4;
-    ZXIC_UINT32 smmu0_int28_status3;
-    ZXIC_UINT32 smmu0_int28_status2;
-    ZXIC_UINT32 smmu0_int28_status1;
-    ZXIC_UINT32 smmu0_int28_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT28_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int29_en_t
-{
-    ZXIC_UINT32 smmu0_int29_en31;
-    ZXIC_UINT32 smmu0_int29_en30;
-    ZXIC_UINT32 smmu0_int29_en29;
-    ZXIC_UINT32 smmu0_int29_en28;
-    ZXIC_UINT32 smmu0_int29_en27;
-    ZXIC_UINT32 smmu0_int29_en26;
-    ZXIC_UINT32 smmu0_int29_en25;
-    ZXIC_UINT32 smmu0_int29_en24;
-    ZXIC_UINT32 smmu0_int29_en23;
-    ZXIC_UINT32 smmu0_int29_en22;
-    ZXIC_UINT32 smmu0_int29_en21;
-    ZXIC_UINT32 smmu0_int29_en20;
-    ZXIC_UINT32 smmu0_int29_en19;
-    ZXIC_UINT32 smmu0_int29_en18;
-    ZXIC_UINT32 smmu0_int29_en17;
-    ZXIC_UINT32 smmu0_int29_en16;
-    ZXIC_UINT32 smmu0_int29_en15;
-    ZXIC_UINT32 smmu0_int29_en14;
-    ZXIC_UINT32 smmu0_int29_en13;
-    ZXIC_UINT32 smmu0_int29_en12;
-    ZXIC_UINT32 smmu0_int29_en11;
-    ZXIC_UINT32 smmu0_int29_en10;
-    ZXIC_UINT32 smmu0_int29_en9;
-    ZXIC_UINT32 smmu0_int29_en8;
-    ZXIC_UINT32 smmu0_int29_en7;
-    ZXIC_UINT32 smmu0_int29_en6;
-    ZXIC_UINT32 smmu0_int29_en5;
-    ZXIC_UINT32 smmu0_int29_en4;
-    ZXIC_UINT32 smmu0_int29_en3;
-    ZXIC_UINT32 smmu0_int29_en2;
-    ZXIC_UINT32 smmu0_int29_en1;
-    ZXIC_UINT32 smmu0_int29_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT29_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int29_mask_t
-{
-    ZXIC_UINT32 smmu0_int29_mask31;
-    ZXIC_UINT32 smmu0_int29_mask30;
-    ZXIC_UINT32 smmu0_int29_mask29;
-    ZXIC_UINT32 smmu0_int29_mask28;
-    ZXIC_UINT32 smmu0_int29_mask27;
-    ZXIC_UINT32 smmu0_int29_mask26;
-    ZXIC_UINT32 smmu0_int29_mask25;
-    ZXIC_UINT32 smmu0_int29_mask24;
-    ZXIC_UINT32 smmu0_int29_mask23;
-    ZXIC_UINT32 smmu0_int29_mask22;
-    ZXIC_UINT32 smmu0_int29_mask21;
-    ZXIC_UINT32 smmu0_int29_mask20;
-    ZXIC_UINT32 smmu0_int29_mask19;
-    ZXIC_UINT32 smmu0_int29_mask18;
-    ZXIC_UINT32 smmu0_int29_mask17;
-    ZXIC_UINT32 smmu0_int29_mask16;
-    ZXIC_UINT32 smmu0_int29_mask15;
-    ZXIC_UINT32 smmu0_int29_mask14;
-    ZXIC_UINT32 smmu0_int29_mask13;
-    ZXIC_UINT32 smmu0_int29_mask12;
-    ZXIC_UINT32 smmu0_int29_mask11;
-    ZXIC_UINT32 smmu0_int29_mask10;
-    ZXIC_UINT32 smmu0_int29_mask9;
-    ZXIC_UINT32 smmu0_int29_mask8;
-    ZXIC_UINT32 smmu0_int29_mask7;
-    ZXIC_UINT32 smmu0_int29_mask6;
-    ZXIC_UINT32 smmu0_int29_mask5;
-    ZXIC_UINT32 smmu0_int29_mask4;
-    ZXIC_UINT32 smmu0_int29_mask3;
-    ZXIC_UINT32 smmu0_int29_mask2;
-    ZXIC_UINT32 smmu0_int29_mask1;
-    ZXIC_UINT32 smmu0_int29_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT29_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int29_status_t
-{
-    ZXIC_UINT32 smmu0_int29_status31;
-    ZXIC_UINT32 smmu0_int29_status30;
-    ZXIC_UINT32 smmu0_int29_status29;
-    ZXIC_UINT32 smmu0_int29_status28;
-    ZXIC_UINT32 smmu0_int29_status27;
-    ZXIC_UINT32 smmu0_int29_status26;
-    ZXIC_UINT32 smmu0_int29_status25;
-    ZXIC_UINT32 smmu0_int29_status24;
-    ZXIC_UINT32 smmu0_int29_status23;
-    ZXIC_UINT32 smmu0_int29_status22;
-    ZXIC_UINT32 smmu0_int29_status21;
-    ZXIC_UINT32 smmu0_int29_status20;
-    ZXIC_UINT32 smmu0_int29_status19;
-    ZXIC_UINT32 smmu0_int29_status18;
-    ZXIC_UINT32 smmu0_int29_status17;
-    ZXIC_UINT32 smmu0_int29_status16;
-    ZXIC_UINT32 smmu0_int29_status15;
-    ZXIC_UINT32 smmu0_int29_status14;
-    ZXIC_UINT32 smmu0_int29_status13;
-    ZXIC_UINT32 smmu0_int29_status12;
-    ZXIC_UINT32 smmu0_int29_status11;
-    ZXIC_UINT32 smmu0_int29_status10;
-    ZXIC_UINT32 smmu0_int29_status9;
-    ZXIC_UINT32 smmu0_int29_status8;
-    ZXIC_UINT32 smmu0_int29_status7;
-    ZXIC_UINT32 smmu0_int29_status6;
-    ZXIC_UINT32 smmu0_int29_status5;
-    ZXIC_UINT32 smmu0_int29_status4;
-    ZXIC_UINT32 smmu0_int29_status3;
-    ZXIC_UINT32 smmu0_int29_status2;
-    ZXIC_UINT32 smmu0_int29_status1;
-    ZXIC_UINT32 smmu0_int29_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT29_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int30_en_t
-{
-    ZXIC_UINT32 smmu0_int30_en31;
-    ZXIC_UINT32 smmu0_int30_en30;
-    ZXIC_UINT32 smmu0_int30_en29;
-    ZXIC_UINT32 smmu0_int30_en28;
-    ZXIC_UINT32 smmu0_int30_en27;
-    ZXIC_UINT32 smmu0_int30_en26;
-    ZXIC_UINT32 smmu0_int30_en25;
-    ZXIC_UINT32 smmu0_int30_en24;
-    ZXIC_UINT32 smmu0_int30_en23;
-    ZXIC_UINT32 smmu0_int30_en22;
-    ZXIC_UINT32 smmu0_int30_en21;
-    ZXIC_UINT32 smmu0_int30_en20;
-    ZXIC_UINT32 smmu0_int30_en19;
-    ZXIC_UINT32 smmu0_int30_en18;
-    ZXIC_UINT32 smmu0_int30_en17;
-    ZXIC_UINT32 smmu0_int30_en16;
-    ZXIC_UINT32 smmu0_int30_en15;
-    ZXIC_UINT32 smmu0_int30_en14;
-    ZXIC_UINT32 smmu0_int30_en13;
-    ZXIC_UINT32 smmu0_int30_en12;
-    ZXIC_UINT32 smmu0_int30_en11;
-    ZXIC_UINT32 smmu0_int30_en10;
-    ZXIC_UINT32 smmu0_int30_en9;
-    ZXIC_UINT32 smmu0_int30_en8;
-    ZXIC_UINT32 smmu0_int30_en7;
-    ZXIC_UINT32 smmu0_int30_en6;
-    ZXIC_UINT32 smmu0_int30_en5;
-    ZXIC_UINT32 smmu0_int30_en4;
-    ZXIC_UINT32 smmu0_int30_en3;
-    ZXIC_UINT32 smmu0_int30_en2;
-    ZXIC_UINT32 smmu0_int30_en1;
-    ZXIC_UINT32 smmu0_int30_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT30_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int30_mask_t
-{
-    ZXIC_UINT32 smmu0_int30_mask31;
-    ZXIC_UINT32 smmu0_int30_mask30;
-    ZXIC_UINT32 smmu0_int30_mask29;
-    ZXIC_UINT32 smmu0_int30_mask28;
-    ZXIC_UINT32 smmu0_int30_mask27;
-    ZXIC_UINT32 smmu0_int30_mask26;
-    ZXIC_UINT32 smmu0_int30_mask25;
-    ZXIC_UINT32 smmu0_int30_mask24;
-    ZXIC_UINT32 smmu0_int30_mask23;
-    ZXIC_UINT32 smmu0_int30_mask22;
-    ZXIC_UINT32 smmu0_int30_mask21;
-    ZXIC_UINT32 smmu0_int30_mask20;
-    ZXIC_UINT32 smmu0_int30_mask19;
-    ZXIC_UINT32 smmu0_int30_mask18;
-    ZXIC_UINT32 smmu0_int30_mask17;
-    ZXIC_UINT32 smmu0_int30_mask16;
-    ZXIC_UINT32 smmu0_int30_mask15;
-    ZXIC_UINT32 smmu0_int30_mask14;
-    ZXIC_UINT32 smmu0_int30_mask13;
-    ZXIC_UINT32 smmu0_int30_mask12;
-    ZXIC_UINT32 smmu0_int30_mask11;
-    ZXIC_UINT32 smmu0_int30_mask10;
-    ZXIC_UINT32 smmu0_int30_mask9;
-    ZXIC_UINT32 smmu0_int30_mask8;
-    ZXIC_UINT32 smmu0_int30_mask7;
-    ZXIC_UINT32 smmu0_int30_mask6;
-    ZXIC_UINT32 smmu0_int30_mask5;
-    ZXIC_UINT32 smmu0_int30_mask4;
-    ZXIC_UINT32 smmu0_int30_mask3;
-    ZXIC_UINT32 smmu0_int30_mask2;
-    ZXIC_UINT32 smmu0_int30_mask1;
-    ZXIC_UINT32 smmu0_int30_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT30_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int30_status_t
-{
-    ZXIC_UINT32 smmu0_int30_status31;
-    ZXIC_UINT32 smmu0_int30_status30;
-    ZXIC_UINT32 smmu0_int30_status29;
-    ZXIC_UINT32 smmu0_int30_status28;
-    ZXIC_UINT32 smmu0_int30_status27;
-    ZXIC_UINT32 smmu0_int30_status26;
-    ZXIC_UINT32 smmu0_int30_status25;
-    ZXIC_UINT32 smmu0_int30_status24;
-    ZXIC_UINT32 smmu0_int30_status23;
-    ZXIC_UINT32 smmu0_int30_status22;
-    ZXIC_UINT32 smmu0_int30_status21;
-    ZXIC_UINT32 smmu0_int30_status20;
-    ZXIC_UINT32 smmu0_int30_status19;
-    ZXIC_UINT32 smmu0_int30_status18;
-    ZXIC_UINT32 smmu0_int30_status17;
-    ZXIC_UINT32 smmu0_int30_status16;
-    ZXIC_UINT32 smmu0_int30_status15;
-    ZXIC_UINT32 smmu0_int30_status14;
-    ZXIC_UINT32 smmu0_int30_status13;
-    ZXIC_UINT32 smmu0_int30_status12;
-    ZXIC_UINT32 smmu0_int30_status11;
-    ZXIC_UINT32 smmu0_int30_status10;
-    ZXIC_UINT32 smmu0_int30_status9;
-    ZXIC_UINT32 smmu0_int30_status8;
-    ZXIC_UINT32 smmu0_int30_status7;
-    ZXIC_UINT32 smmu0_int30_status6;
-    ZXIC_UINT32 smmu0_int30_status5;
-    ZXIC_UINT32 smmu0_int30_status4;
-    ZXIC_UINT32 smmu0_int30_status3;
-    ZXIC_UINT32 smmu0_int30_status2;
-    ZXIC_UINT32 smmu0_int30_status1;
-    ZXIC_UINT32 smmu0_int30_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT30_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int31_en_t
-{
-    ZXIC_UINT32 smmu0_int31_en31;
-    ZXIC_UINT32 smmu0_int31_en30;
-    ZXIC_UINT32 smmu0_int31_en29;
-    ZXIC_UINT32 smmu0_int31_en28;
-    ZXIC_UINT32 smmu0_int31_en27;
-    ZXIC_UINT32 smmu0_int31_en26;
-    ZXIC_UINT32 smmu0_int31_en25;
-    ZXIC_UINT32 smmu0_int31_en24;
-    ZXIC_UINT32 smmu0_int31_en23;
-    ZXIC_UINT32 smmu0_int31_en22;
-    ZXIC_UINT32 smmu0_int31_en21;
-    ZXIC_UINT32 smmu0_int31_en20;
-    ZXIC_UINT32 smmu0_int31_en19;
-    ZXIC_UINT32 smmu0_int31_en18;
-    ZXIC_UINT32 smmu0_int31_en17;
-    ZXIC_UINT32 smmu0_int31_en16;
-    ZXIC_UINT32 smmu0_int31_en15;
-    ZXIC_UINT32 smmu0_int31_en14;
-    ZXIC_UINT32 smmu0_int31_en13;
-    ZXIC_UINT32 smmu0_int31_en12;
-    ZXIC_UINT32 smmu0_int31_en11;
-    ZXIC_UINT32 smmu0_int31_en10;
-    ZXIC_UINT32 smmu0_int31_en9;
-    ZXIC_UINT32 smmu0_int31_en8;
-    ZXIC_UINT32 smmu0_int31_en7;
-    ZXIC_UINT32 smmu0_int31_en6;
-    ZXIC_UINT32 smmu0_int31_en5;
-    ZXIC_UINT32 smmu0_int31_en4;
-    ZXIC_UINT32 smmu0_int31_en3;
-    ZXIC_UINT32 smmu0_int31_en2;
-    ZXIC_UINT32 smmu0_int31_en1;
-    ZXIC_UINT32 smmu0_int31_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT31_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int31_mask_t
-{
-    ZXIC_UINT32 smmu0_int31_mask31;
-    ZXIC_UINT32 smmu0_int31_mask30;
-    ZXIC_UINT32 smmu0_int31_mask29;
-    ZXIC_UINT32 smmu0_int31_mask28;
-    ZXIC_UINT32 smmu0_int31_mask27;
-    ZXIC_UINT32 smmu0_int31_mask26;
-    ZXIC_UINT32 smmu0_int31_mask25;
-    ZXIC_UINT32 smmu0_int31_mask24;
-    ZXIC_UINT32 smmu0_int31_mask23;
-    ZXIC_UINT32 smmu0_int31_mask22;
-    ZXIC_UINT32 smmu0_int31_mask21;
-    ZXIC_UINT32 smmu0_int31_mask20;
-    ZXIC_UINT32 smmu0_int31_mask19;
-    ZXIC_UINT32 smmu0_int31_mask18;
-    ZXIC_UINT32 smmu0_int31_mask17;
-    ZXIC_UINT32 smmu0_int31_mask16;
-    ZXIC_UINT32 smmu0_int31_mask15;
-    ZXIC_UINT32 smmu0_int31_mask14;
-    ZXIC_UINT32 smmu0_int31_mask13;
-    ZXIC_UINT32 smmu0_int31_mask12;
-    ZXIC_UINT32 smmu0_int31_mask11;
-    ZXIC_UINT32 smmu0_int31_mask10;
-    ZXIC_UINT32 smmu0_int31_mask9;
-    ZXIC_UINT32 smmu0_int31_mask8;
-    ZXIC_UINT32 smmu0_int31_mask7;
-    ZXIC_UINT32 smmu0_int31_mask6;
-    ZXIC_UINT32 smmu0_int31_mask5;
-    ZXIC_UINT32 smmu0_int31_mask4;
-    ZXIC_UINT32 smmu0_int31_mask3;
-    ZXIC_UINT32 smmu0_int31_mask2;
-    ZXIC_UINT32 smmu0_int31_mask1;
-    ZXIC_UINT32 smmu0_int31_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT31_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int31_status_t
-{
-    ZXIC_UINT32 smmu0_int31_status31;
-    ZXIC_UINT32 smmu0_int31_status30;
-    ZXIC_UINT32 smmu0_int31_status29;
-    ZXIC_UINT32 smmu0_int31_status28;
-    ZXIC_UINT32 smmu0_int31_status27;
-    ZXIC_UINT32 smmu0_int31_status26;
-    ZXIC_UINT32 smmu0_int31_status25;
-    ZXIC_UINT32 smmu0_int31_status24;
-    ZXIC_UINT32 smmu0_int31_status23;
-    ZXIC_UINT32 smmu0_int31_status22;
-    ZXIC_UINT32 smmu0_int31_status21;
-    ZXIC_UINT32 smmu0_int31_status20;
-    ZXIC_UINT32 smmu0_int31_status19;
-    ZXIC_UINT32 smmu0_int31_status18;
-    ZXIC_UINT32 smmu0_int31_status17;
-    ZXIC_UINT32 smmu0_int31_status16;
-    ZXIC_UINT32 smmu0_int31_status15;
-    ZXIC_UINT32 smmu0_int31_status14;
-    ZXIC_UINT32 smmu0_int31_status13;
-    ZXIC_UINT32 smmu0_int31_status12;
-    ZXIC_UINT32 smmu0_int31_status11;
-    ZXIC_UINT32 smmu0_int31_status10;
-    ZXIC_UINT32 smmu0_int31_status9;
-    ZXIC_UINT32 smmu0_int31_status8;
-    ZXIC_UINT32 smmu0_int31_status7;
-    ZXIC_UINT32 smmu0_int31_status6;
-    ZXIC_UINT32 smmu0_int31_status5;
-    ZXIC_UINT32 smmu0_int31_status4;
-    ZXIC_UINT32 smmu0_int31_status3;
-    ZXIC_UINT32 smmu0_int31_status2;
-    ZXIC_UINT32 smmu0_int31_status1;
-    ZXIC_UINT32 smmu0_int31_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT31_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int32_en_t
-{
-    ZXIC_UINT32 smmu0_int32_en31;
-    ZXIC_UINT32 smmu0_int32_en30;
-    ZXIC_UINT32 smmu0_int32_en29;
-    ZXIC_UINT32 smmu0_int32_en28;
-    ZXIC_UINT32 smmu0_int32_en27;
-    ZXIC_UINT32 smmu0_int32_en26;
-    ZXIC_UINT32 smmu0_int32_en25;
-    ZXIC_UINT32 smmu0_int32_en24;
-    ZXIC_UINT32 smmu0_int32_en23;
-    ZXIC_UINT32 smmu0_int32_en22;
-    ZXIC_UINT32 smmu0_int32_en21;
-    ZXIC_UINT32 smmu0_int32_en20;
-    ZXIC_UINT32 smmu0_int32_en19;
-    ZXIC_UINT32 smmu0_int32_en18;
-    ZXIC_UINT32 smmu0_int32_en17;
-    ZXIC_UINT32 smmu0_int32_en16;
-    ZXIC_UINT32 smmu0_int32_en15;
-    ZXIC_UINT32 smmu0_int32_en14;
-    ZXIC_UINT32 smmu0_int32_en13;
-    ZXIC_UINT32 smmu0_int32_en12;
-    ZXIC_UINT32 smmu0_int32_en11;
-    ZXIC_UINT32 smmu0_int32_en10;
-    ZXIC_UINT32 smmu0_int32_en9;
-    ZXIC_UINT32 smmu0_int32_en8;
-    ZXIC_UINT32 smmu0_int32_en7;
-    ZXIC_UINT32 smmu0_int32_en6;
-    ZXIC_UINT32 smmu0_int32_en5;
-    ZXIC_UINT32 smmu0_int32_en4;
-    ZXIC_UINT32 smmu0_int32_en3;
-    ZXIC_UINT32 smmu0_int32_en2;
-    ZXIC_UINT32 smmu0_int32_en1;
-    ZXIC_UINT32 smmu0_int32_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT32_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int32_mask_t
-{
-    ZXIC_UINT32 smmu0_int32_mask31;
-    ZXIC_UINT32 smmu0_int32_mask30;
-    ZXIC_UINT32 smmu0_int32_mask29;
-    ZXIC_UINT32 smmu0_int32_mask28;
-    ZXIC_UINT32 smmu0_int32_mask27;
-    ZXIC_UINT32 smmu0_int32_mask26;
-    ZXIC_UINT32 smmu0_int32_mask25;
-    ZXIC_UINT32 smmu0_int32_mask24;
-    ZXIC_UINT32 smmu0_int32_mask23;
-    ZXIC_UINT32 smmu0_int32_mask22;
-    ZXIC_UINT32 smmu0_int32_mask21;
-    ZXIC_UINT32 smmu0_int32_mask20;
-    ZXIC_UINT32 smmu0_int32_mask19;
-    ZXIC_UINT32 smmu0_int32_mask18;
-    ZXIC_UINT32 smmu0_int32_mask17;
-    ZXIC_UINT32 smmu0_int32_mask16;
-    ZXIC_UINT32 smmu0_int32_mask15;
-    ZXIC_UINT32 smmu0_int32_mask14;
-    ZXIC_UINT32 smmu0_int32_mask13;
-    ZXIC_UINT32 smmu0_int32_mask12;
-    ZXIC_UINT32 smmu0_int32_mask11;
-    ZXIC_UINT32 smmu0_int32_mask10;
-    ZXIC_UINT32 smmu0_int32_mask9;
-    ZXIC_UINT32 smmu0_int32_mask8;
-    ZXIC_UINT32 smmu0_int32_mask7;
-    ZXIC_UINT32 smmu0_int32_mask6;
-    ZXIC_UINT32 smmu0_int32_mask5;
-    ZXIC_UINT32 smmu0_int32_mask4;
-    ZXIC_UINT32 smmu0_int32_mask3;
-    ZXIC_UINT32 smmu0_int32_mask2;
-    ZXIC_UINT32 smmu0_int32_mask1;
-    ZXIC_UINT32 smmu0_int32_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT32_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int32_status_t
-{
-    ZXIC_UINT32 smmu0_int32_status31;
-    ZXIC_UINT32 smmu0_int32_status30;
-    ZXIC_UINT32 smmu0_int32_status29;
-    ZXIC_UINT32 smmu0_int32_status28;
-    ZXIC_UINT32 smmu0_int32_status27;
-    ZXIC_UINT32 smmu0_int32_status26;
-    ZXIC_UINT32 smmu0_int32_status25;
-    ZXIC_UINT32 smmu0_int32_status24;
-    ZXIC_UINT32 smmu0_int32_status23;
-    ZXIC_UINT32 smmu0_int32_status22;
-    ZXIC_UINT32 smmu0_int32_status21;
-    ZXIC_UINT32 smmu0_int32_status20;
-    ZXIC_UINT32 smmu0_int32_status19;
-    ZXIC_UINT32 smmu0_int32_status18;
-    ZXIC_UINT32 smmu0_int32_status17;
-    ZXIC_UINT32 smmu0_int32_status16;
-    ZXIC_UINT32 smmu0_int32_status15;
-    ZXIC_UINT32 smmu0_int32_status14;
-    ZXIC_UINT32 smmu0_int32_status13;
-    ZXIC_UINT32 smmu0_int32_status12;
-    ZXIC_UINT32 smmu0_int32_status11;
-    ZXIC_UINT32 smmu0_int32_status10;
-    ZXIC_UINT32 smmu0_int32_status9;
-    ZXIC_UINT32 smmu0_int32_status8;
-    ZXIC_UINT32 smmu0_int32_status7;
-    ZXIC_UINT32 smmu0_int32_status6;
-    ZXIC_UINT32 smmu0_int32_status5;
-    ZXIC_UINT32 smmu0_int32_status4;
-    ZXIC_UINT32 smmu0_int32_status3;
-    ZXIC_UINT32 smmu0_int32_status2;
-    ZXIC_UINT32 smmu0_int32_status1;
-    ZXIC_UINT32 smmu0_int32_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT32_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int33_en_t
-{
-    ZXIC_UINT32 smmu0_int33_en31;
-    ZXIC_UINT32 smmu0_int33_en30;
-    ZXIC_UINT32 smmu0_int33_en29;
-    ZXIC_UINT32 smmu0_int33_en28;
-    ZXIC_UINT32 smmu0_int33_en27;
-    ZXIC_UINT32 smmu0_int33_en26;
-    ZXIC_UINT32 smmu0_int33_en25;
-    ZXIC_UINT32 smmu0_int33_en24;
-    ZXIC_UINT32 smmu0_int33_en23;
-    ZXIC_UINT32 smmu0_int33_en22;
-    ZXIC_UINT32 smmu0_int33_en21;
-    ZXIC_UINT32 smmu0_int33_en20;
-    ZXIC_UINT32 smmu0_int33_en19;
-    ZXIC_UINT32 smmu0_int33_en18;
-    ZXIC_UINT32 smmu0_int33_en17;
-    ZXIC_UINT32 smmu0_int33_en16;
-    ZXIC_UINT32 smmu0_int33_en15;
-    ZXIC_UINT32 smmu0_int33_en14;
-    ZXIC_UINT32 smmu0_int33_en13;
-    ZXIC_UINT32 smmu0_int33_en12;
-    ZXIC_UINT32 smmu0_int33_en11;
-    ZXIC_UINT32 smmu0_int33_en10;
-    ZXIC_UINT32 smmu0_int33_en9;
-    ZXIC_UINT32 smmu0_int33_en8;
-    ZXIC_UINT32 smmu0_int33_en7;
-    ZXIC_UINT32 smmu0_int33_en6;
-    ZXIC_UINT32 smmu0_int33_en5;
-    ZXIC_UINT32 smmu0_int33_en4;
-    ZXIC_UINT32 smmu0_int33_en3;
-    ZXIC_UINT32 smmu0_int33_en2;
-    ZXIC_UINT32 smmu0_int33_en1;
-    ZXIC_UINT32 smmu0_int33_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT33_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int33_mask_t
-{
-    ZXIC_UINT32 smmu0_int33_mask31;
-    ZXIC_UINT32 smmu0_int33_mask30;
-    ZXIC_UINT32 smmu0_int33_mask29;
-    ZXIC_UINT32 smmu0_int33_mask28;
-    ZXIC_UINT32 smmu0_int33_mask27;
-    ZXIC_UINT32 smmu0_int33_mask26;
-    ZXIC_UINT32 smmu0_int33_mask25;
-    ZXIC_UINT32 smmu0_int33_mask24;
-    ZXIC_UINT32 smmu0_int33_mask23;
-    ZXIC_UINT32 smmu0_int33_mask22;
-    ZXIC_UINT32 smmu0_int33_mask21;
-    ZXIC_UINT32 smmu0_int33_mask20;
-    ZXIC_UINT32 smmu0_int33_mask19;
-    ZXIC_UINT32 smmu0_int33_mask18;
-    ZXIC_UINT32 smmu0_int33_mask17;
-    ZXIC_UINT32 smmu0_int33_mask16;
-    ZXIC_UINT32 smmu0_int33_mask15;
-    ZXIC_UINT32 smmu0_int33_mask14;
-    ZXIC_UINT32 smmu0_int33_mask13;
-    ZXIC_UINT32 smmu0_int33_mask12;
-    ZXIC_UINT32 smmu0_int33_mask11;
-    ZXIC_UINT32 smmu0_int33_mask10;
-    ZXIC_UINT32 smmu0_int33_mask9;
-    ZXIC_UINT32 smmu0_int33_mask8;
-    ZXIC_UINT32 smmu0_int33_mask7;
-    ZXIC_UINT32 smmu0_int33_mask6;
-    ZXIC_UINT32 smmu0_int33_mask5;
-    ZXIC_UINT32 smmu0_int33_mask4;
-    ZXIC_UINT32 smmu0_int33_mask3;
-    ZXIC_UINT32 smmu0_int33_mask2;
-    ZXIC_UINT32 smmu0_int33_mask1;
-    ZXIC_UINT32 smmu0_int33_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT33_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int33_status_t
-{
-    ZXIC_UINT32 smmu0_int33_status31;
-    ZXIC_UINT32 smmu0_int33_status30;
-    ZXIC_UINT32 smmu0_int33_status29;
-    ZXIC_UINT32 smmu0_int33_status28;
-    ZXIC_UINT32 smmu0_int33_status27;
-    ZXIC_UINT32 smmu0_int33_status26;
-    ZXIC_UINT32 smmu0_int33_status25;
-    ZXIC_UINT32 smmu0_int33_status24;
-    ZXIC_UINT32 smmu0_int33_status23;
-    ZXIC_UINT32 smmu0_int33_status22;
-    ZXIC_UINT32 smmu0_int33_status21;
-    ZXIC_UINT32 smmu0_int33_status20;
-    ZXIC_UINT32 smmu0_int33_status19;
-    ZXIC_UINT32 smmu0_int33_status18;
-    ZXIC_UINT32 smmu0_int33_status17;
-    ZXIC_UINT32 smmu0_int33_status16;
-    ZXIC_UINT32 smmu0_int33_status15;
-    ZXIC_UINT32 smmu0_int33_status14;
-    ZXIC_UINT32 smmu0_int33_status13;
-    ZXIC_UINT32 smmu0_int33_status12;
-    ZXIC_UINT32 smmu0_int33_status11;
-    ZXIC_UINT32 smmu0_int33_status10;
-    ZXIC_UINT32 smmu0_int33_status9;
-    ZXIC_UINT32 smmu0_int33_status8;
-    ZXIC_UINT32 smmu0_int33_status7;
-    ZXIC_UINT32 smmu0_int33_status6;
-    ZXIC_UINT32 smmu0_int33_status5;
-    ZXIC_UINT32 smmu0_int33_status4;
-    ZXIC_UINT32 smmu0_int33_status3;
-    ZXIC_UINT32 smmu0_int33_status2;
-    ZXIC_UINT32 smmu0_int33_status1;
-    ZXIC_UINT32 smmu0_int33_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT33_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int34_en_t
-{
-    ZXIC_UINT32 smmu0_int34_en31;
-    ZXIC_UINT32 smmu0_int34_en30;
-    ZXIC_UINT32 smmu0_int34_en29;
-    ZXIC_UINT32 smmu0_int34_en28;
-    ZXIC_UINT32 smmu0_int34_en27;
-    ZXIC_UINT32 smmu0_int34_en26;
-    ZXIC_UINT32 smmu0_int34_en25;
-    ZXIC_UINT32 smmu0_int34_en24;
-    ZXIC_UINT32 smmu0_int34_en23;
-    ZXIC_UINT32 smmu0_int34_en22;
-    ZXIC_UINT32 smmu0_int34_en21;
-    ZXIC_UINT32 smmu0_int34_en20;
-    ZXIC_UINT32 smmu0_int34_en19;
-    ZXIC_UINT32 smmu0_int34_en18;
-    ZXIC_UINT32 smmu0_int34_en17;
-    ZXIC_UINT32 smmu0_int34_en16;
-    ZXIC_UINT32 smmu0_int34_en15;
-    ZXIC_UINT32 smmu0_int34_en14;
-    ZXIC_UINT32 smmu0_int34_en13;
-    ZXIC_UINT32 smmu0_int34_en12;
-    ZXIC_UINT32 smmu0_int34_en11;
-    ZXIC_UINT32 smmu0_int34_en10;
-    ZXIC_UINT32 smmu0_int34_en9;
-    ZXIC_UINT32 smmu0_int34_en8;
-    ZXIC_UINT32 smmu0_int34_en7;
-    ZXIC_UINT32 smmu0_int34_en6;
-    ZXIC_UINT32 smmu0_int34_en5;
-    ZXIC_UINT32 smmu0_int34_en4;
-    ZXIC_UINT32 smmu0_int34_en3;
-    ZXIC_UINT32 smmu0_int34_en2;
-    ZXIC_UINT32 smmu0_int34_en1;
-    ZXIC_UINT32 smmu0_int34_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT34_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int34_mask_t
-{
-    ZXIC_UINT32 smmu0_int34_mask31;
-    ZXIC_UINT32 smmu0_int34_mask30;
-    ZXIC_UINT32 smmu0_int34_mask29;
-    ZXIC_UINT32 smmu0_int34_mask28;
-    ZXIC_UINT32 smmu0_int34_mask27;
-    ZXIC_UINT32 smmu0_int34_mask26;
-    ZXIC_UINT32 smmu0_int34_mask25;
-    ZXIC_UINT32 smmu0_int34_mask24;
-    ZXIC_UINT32 smmu0_int34_mask23;
-    ZXIC_UINT32 smmu0_int34_mask22;
-    ZXIC_UINT32 smmu0_int34_mask21;
-    ZXIC_UINT32 smmu0_int34_mask20;
-    ZXIC_UINT32 smmu0_int34_mask19;
-    ZXIC_UINT32 smmu0_int34_mask18;
-    ZXIC_UINT32 smmu0_int34_mask17;
-    ZXIC_UINT32 smmu0_int34_mask16;
-    ZXIC_UINT32 smmu0_int34_mask15;
-    ZXIC_UINT32 smmu0_int34_mask14;
-    ZXIC_UINT32 smmu0_int34_mask13;
-    ZXIC_UINT32 smmu0_int34_mask12;
-    ZXIC_UINT32 smmu0_int34_mask11;
-    ZXIC_UINT32 smmu0_int34_mask10;
-    ZXIC_UINT32 smmu0_int34_mask9;
-    ZXIC_UINT32 smmu0_int34_mask8;
-    ZXIC_UINT32 smmu0_int34_mask7;
-    ZXIC_UINT32 smmu0_int34_mask6;
-    ZXIC_UINT32 smmu0_int34_mask5;
-    ZXIC_UINT32 smmu0_int34_mask4;
-    ZXIC_UINT32 smmu0_int34_mask3;
-    ZXIC_UINT32 smmu0_int34_mask2;
-    ZXIC_UINT32 smmu0_int34_mask1;
-    ZXIC_UINT32 smmu0_int34_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT34_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int34_status_t
-{
-    ZXIC_UINT32 smmu0_int34_status31;
-    ZXIC_UINT32 smmu0_int34_status30;
-    ZXIC_UINT32 smmu0_int34_status29;
-    ZXIC_UINT32 smmu0_int34_status28;
-    ZXIC_UINT32 smmu0_int34_status27;
-    ZXIC_UINT32 smmu0_int34_status26;
-    ZXIC_UINT32 smmu0_int34_status25;
-    ZXIC_UINT32 smmu0_int34_status24;
-    ZXIC_UINT32 smmu0_int34_status23;
-    ZXIC_UINT32 smmu0_int34_status22;
-    ZXIC_UINT32 smmu0_int34_status21;
-    ZXIC_UINT32 smmu0_int34_status20;
-    ZXIC_UINT32 smmu0_int34_status19;
-    ZXIC_UINT32 smmu0_int34_status18;
-    ZXIC_UINT32 smmu0_int34_status17;
-    ZXIC_UINT32 smmu0_int34_status16;
-    ZXIC_UINT32 smmu0_int34_status15;
-    ZXIC_UINT32 smmu0_int34_status14;
-    ZXIC_UINT32 smmu0_int34_status13;
-    ZXIC_UINT32 smmu0_int34_status12;
-    ZXIC_UINT32 smmu0_int34_status11;
-    ZXIC_UINT32 smmu0_int34_status10;
-    ZXIC_UINT32 smmu0_int34_status9;
-    ZXIC_UINT32 smmu0_int34_status8;
-    ZXIC_UINT32 smmu0_int34_status7;
-    ZXIC_UINT32 smmu0_int34_status6;
-    ZXIC_UINT32 smmu0_int34_status5;
-    ZXIC_UINT32 smmu0_int34_status4;
-    ZXIC_UINT32 smmu0_int34_status3;
-    ZXIC_UINT32 smmu0_int34_status2;
-    ZXIC_UINT32 smmu0_int34_status1;
-    ZXIC_UINT32 smmu0_int34_status0;
-}DPP_SMMU0_SMMU0_SMMU0_INT34_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int35_en_t
-{
-    ZXIC_UINT32 smmu0_int35_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT35_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int35_mask_t
-{
-    ZXIC_UINT32 smmu0_int35_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT35_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int35_status_t
-{
-    ZXIC_UINT32 smmu0_int35_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT35_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int36_en_t
-{
-    ZXIC_UINT32 smmu0_int36_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT36_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int36_mask_t
-{
-    ZXIC_UINT32 smmu0_int36_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT36_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int36_status_t
-{
-    ZXIC_UINT32 smmu0_int36_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT36_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int37_en_t
-{
-    ZXIC_UINT32 smmu0_int37_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT37_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int37_mask_t
-{
-    ZXIC_UINT32 smmu0_int37_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT37_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int37_status_t
-{
-    ZXIC_UINT32 smmu0_int37_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT37_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int38_en_t
-{
-    ZXIC_UINT32 smmu0_int38_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT38_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int38_mask_t
-{
-    ZXIC_UINT32 smmu0_int38_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT38_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int38_status_t
-{
-    ZXIC_UINT32 smmu0_int38_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT38_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int39_en_t
-{
-    ZXIC_UINT32 smmu0_int39_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT39_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int39_mask_t
-{
-    ZXIC_UINT32 smmu0_int39_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT39_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int39_status_t
-{
-    ZXIC_UINT32 smmu0_int39_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT39_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int40_en_t
-{
-    ZXIC_UINT32 smmu0_int40_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT40_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int40_mask_t
-{
-    ZXIC_UINT32 smmu0_int40_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT40_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int40_status_t
-{
-    ZXIC_UINT32 smmu0_int40_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT40_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int41_en_t
-{
-    ZXIC_UINT32 smmu0_int41_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT41_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int41_mask_t
-{
-    ZXIC_UINT32 smmu0_int41_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT41_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int41_status_t
-{
-    ZXIC_UINT32 smmu0_int41_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT41_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int42_en_t
-{
-    ZXIC_UINT32 smmu0_int42_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT42_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int42_mask_t
-{
-    ZXIC_UINT32 smmu0_int42_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT42_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int42_status_t
-{
-    ZXIC_UINT32 smmu0_int42_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT42_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int43_en_t
-{
-    ZXIC_UINT32 smmu0_int43_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT43_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int43_mask_t
-{
-    ZXIC_UINT32 smmu0_int43_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT43_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int43_status_t
-{
-    ZXIC_UINT32 smmu0_int43_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT43_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int44_en_t
-{
-    ZXIC_UINT32 smmu0_int44_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT44_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int44_mask_t
-{
-    ZXIC_UINT32 smmu0_int44_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT44_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int44_status_t
-{
-    ZXIC_UINT32 smmu0_int44_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT44_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int45_en_t
-{
-    ZXIC_UINT32 smmu0_int45_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT45_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int45_mask_t
-{
-    ZXIC_UINT32 smmu0_int45_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT45_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int45_status_t
-{
-    ZXIC_UINT32 smmu0_int45_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT45_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int46_en_t
-{
-    ZXIC_UINT32 smmu0_int46_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT46_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int46_mask_t
-{
-    ZXIC_UINT32 smmu0_int46_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT46_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int46_status_t
-{
-    ZXIC_UINT32 smmu0_int46_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT46_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int47_en_t
-{
-    ZXIC_UINT32 smmu0_int47_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT47_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int47_mask_t
-{
-    ZXIC_UINT32 smmu0_int47_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT47_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int47_status_t
-{
-    ZXIC_UINT32 smmu0_int47_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT47_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int48_en_t
-{
-    ZXIC_UINT32 smmu0_int48_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT48_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int48_mask_t
-{
-    ZXIC_UINT32 smmu0_int48_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT48_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int48_status_t
-{
-    ZXIC_UINT32 smmu0_int48_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT48_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int49_en_t
-{
-    ZXIC_UINT32 smmu0_int49_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT49_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int49_mask_t
-{
-    ZXIC_UINT32 smmu0_int49_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT49_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int49_status_t
-{
-    ZXIC_UINT32 smmu0_int49_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT49_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int50_en_t
-{
-    ZXIC_UINT32 smmu0_int50_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT50_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int50_mask_t
-{
-    ZXIC_UINT32 smmu0_int50_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT50_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int50_status_t
-{
-    ZXIC_UINT32 smmu0_int50_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT50_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int51_en_t
-{
-    ZXIC_UINT32 smmu0_int51_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT51_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int51_mask_t
-{
-    ZXIC_UINT32 smmu0_int51_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT51_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int51_status_t
-{
-    ZXIC_UINT32 smmu0_int51_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT51_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int52_en_t
-{
-    ZXIC_UINT32 smmu0_int52_en0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT52_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int52_mask_t
-{
-    ZXIC_UINT32 smmu0_int52_mask0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT52_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int52_status_t
-{
-    ZXIC_UINT32 smmu0_int52_status0_31;
-}DPP_SMMU0_SMMU0_SMMU0_INT52_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int53_en_t
-{
-    ZXIC_UINT32 smmu0_int53_en3;
-    ZXIC_UINT32 smmu0_int53_en2;
-    ZXIC_UINT32 smmu0_int53_en1;
-    ZXIC_UINT32 smmu0_int53_en0;
-}DPP_SMMU0_SMMU0_SMMU0_INT53_EN_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int53_mask_t
-{
-    ZXIC_UINT32 smmu0_int53_mask3;
-    ZXIC_UINT32 smmu0_int53_mask2;
-    ZXIC_UINT32 smmu0_int53_mask1;
-    ZXIC_UINT32 smmu0_int53_mask0;
-}DPP_SMMU0_SMMU0_SMMU0_INT53_MASK_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_int53_status_t
-{
-    ZXIC_UINT32 smmu0_int53_status15;
-    ZXIC_UINT32 smmu0_int53_status14;
-    ZXIC_UINT32 smmu0_int53_status13;
-    ZXIC_UINT32 smmu0_int53_status12;
-}DPP_SMMU0_SMMU0_SMMU0_INT53_STATUS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl0_arbiter_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_0;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_0;
-}DPP_SMMU0_SMMU0_CTRL0_ARBITER_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl2_arbiter_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_0;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_0;
-}DPP_SMMU0_SMMU0_CTRL2_ARBITER_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl4_arbiter_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_0;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_0;
-}DPP_SMMU0_SMMU0_CTRL4_ARBITER_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl6_arbiter_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_0;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_0;
-}DPP_SMMU0_SMMU0_CTRL6_ARBITER_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl8_arbiter_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_0;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_0;
-}DPP_SMMU0_SMMU0_CTRL8_ARBITER_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl10_arbiter_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_0;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_0;
-}DPP_SMMU0_SMMU0_CTRL10_ARBITER_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl12_arbiter_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_0;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_0;
-}DPP_SMMU0_SMMU0_CTRL12_ARBITER_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl14_arbiter_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_0;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_0;
-}DPP_SMMU0_SMMU0_CTRL14_ARBITER_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl16_arbiter_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_0;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_0;
-}DPP_SMMU0_SMMU0_CTRL16_ARBITER_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl18_arbiter_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_0;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_0;
-}DPP_SMMU0_SMMU0_CTRL18_ARBITER_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl20_arbiter_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_0;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_0;
-}DPP_SMMU0_SMMU0_CTRL20_ARBITER_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl22_arbiter_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_0;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_0;
-}DPP_SMMU0_SMMU0_CTRL22_ARBITER_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl24_arbiter_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_0;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_0;
-}DPP_SMMU0_SMMU0_CTRL24_ARBITER_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl26_arbiter_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_0;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_0;
-}DPP_SMMU0_SMMU0_CTRL26_ARBITER_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl28_arbiter_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_0;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_0;
-}DPP_SMMU0_SMMU0_CTRL28_ARBITER_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl30_arbiter_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_0;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_15;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_14;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_13;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_12;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_11;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_10;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_9;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_8;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_7;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_6;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_5;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_4;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_3;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_2;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_1;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_0;
-}DPP_SMMU0_SMMU0_CTRL30_ARBITER_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl_req_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl_req_ecc_bypass_0_31;
-}DPP_SMMU0_SMMU0_CTRL_REQ_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl_info_ecc_bypass_t
-{
-    ZXIC_UINT32 ctrl_info_ecc_bypass_0_31;
-}DPP_SMMU0_SMMU0_CTRL_INFO_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_rschd_ecc_bypass_t
-{
-    ZXIC_UINT32 smmu0_rschd_ecc_bypass_0_31;
-}DPP_SMMU0_SMMU0_SMMU0_RSCHD_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_wr_ecc_bypass_t
-{
-    ZXIC_UINT32 smmu0_wr_ecc_bypass1;
-    ZXIC_UINT32 smmu0_wr_ecc_bypass0;
-}DPP_SMMU0_SMMU0_SMMU0_WR_ECC_BYPASS_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl0_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl0_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL0_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl1_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl1_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL1_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl2_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl2_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL2_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl3_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl3_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL3_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl4_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl4_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL4_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl5_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl5_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL5_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl6_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl6_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL6_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl7_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl7_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL7_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl8_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl8_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL8_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl9_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl9_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL9_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl10_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl10_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL10_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl11_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl11_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL11_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl12_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl12_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL12_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl13_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl13_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL13_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl14_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl14_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL14_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl15_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl15_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL15_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl16_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl16_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL16_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl17_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl17_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL17_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl18_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl18_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL18_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl19_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl19_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL19_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl20_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl20_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL20_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl21_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl21_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL21_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl22_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl22_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL22_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl23_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl23_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL23_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl24_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl24_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL24_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl25_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl25_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL25_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl26_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl26_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL26_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl27_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl27_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL27_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl28_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl28_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL28_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl29_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl29_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL29_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl30_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl30_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL30_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl31_arbiter_ecc_err_t
-{
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_31;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_30;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_29;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_28;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_27;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_26;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_25;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_24;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_23;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_22;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_21;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_20;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_19;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_18;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_17;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_16;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_15;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_14;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_13;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_12;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_11;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_10;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_9;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_8;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_7;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_6;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_5;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_4;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_3;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_2;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_1;
-    ZXIC_UINT32 ctrl31_arbiter_ecc_err_0;
-}DPP_SMMU0_SMMU0_CTRL31_ARBITER_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl_req_ecc_single_err_t
-{
-    ZXIC_UINT32 ctrl_req_ecc_single_err_0_31;
-}DPP_SMMU0_SMMU0_CTRL_REQ_ECC_SINGLE_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl_req_ecc_double_err_t
-{
-    ZXIC_UINT32 ctrl_req_ecc_double_err_0_31;
-}DPP_SMMU0_SMMU0_CTRL_REQ_ECC_DOUBLE_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl_info_ecc_single_err_t
-{
-    ZXIC_UINT32 ctrl_info_ecc_single_err_0_31;
-}DPP_SMMU0_SMMU0_CTRL_INFO_ECC_SINGLE_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl_info_ecc_double_err_t
-{
-    ZXIC_UINT32 ctrl_info_ecc_double_err_0_31;
-}DPP_SMMU0_SMMU0_CTRL_INFO_ECC_DOUBLE_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_wr_ecc_err_t
-{
-    ZXIC_UINT32 smmu0_wr_ecc_err_3;
-    ZXIC_UINT32 smmu0_wr_ecc_err_2;
-    ZXIC_UINT32 smmu0_wr_ecc_err_1;
-    ZXIC_UINT32 smmu0_wr_ecc_err_0;
-}DPP_SMMU0_SMMU0_SMMU0_WR_ECC_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_rschd_ecc_single_err_t
-{
-    ZXIC_UINT32 smmu0_rschd_ecc_single_err_0_31;
-}DPP_SMMU0_SMMU0_SMMU0_RSCHD_ECC_SINGLE_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_rschd_ecc_double_err_t
-{
-    ZXIC_UINT32 smmu0_rschd_ecc_double_err_0_31;
-}DPP_SMMU0_SMMU0_SMMU0_RSCHD_ECC_DOUBLE_ERR_T;
-
-typedef struct dpp_smmu0_smmu0_ord_fifo_empty_t
-{
-    ZXIC_UINT32 ord_fifo_empty;
-}DPP_SMMU0_SMMU0_ORD_FIFO_EMPTY_T;
-
-typedef struct dpp_smmu0_smmu0_wr_arb_fifo_empty_t
-{
-    ZXIC_UINT32 wr_arb_fifo_empty;
-}DPP_SMMU0_SMMU0_WR_ARB_FIFO_EMPTY_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty0_t
-{
-    ZXIC_UINT32 ctrl_fifo_empty0_5;
-    ZXIC_UINT32 ctrl_fifo_empty0_4;
-    ZXIC_UINT32 ctrl_fifo_empty0_3;
-    ZXIC_UINT32 ctrl_fifo_empty0_2;
-    ZXIC_UINT32 ctrl_fifo_empty0_1;
-    ZXIC_UINT32 ctrl_fifo_empty0_0;
-}DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY0_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty1_t
-{
-    ZXIC_UINT32 ctrl_fifo_empty1_5;
-    ZXIC_UINT32 ctrl_fifo_empty1_4;
-    ZXIC_UINT32 ctrl_fifo_empty1_3;
-    ZXIC_UINT32 ctrl_fifo_empty1_2;
-    ZXIC_UINT32 ctrl_fifo_empty1_1;
-    ZXIC_UINT32 ctrl_fifo_empty1_0;
-}DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY1_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty2_t
-{
-    ZXIC_UINT32 ctrl_fifo_empty2_5;
-    ZXIC_UINT32 ctrl_fifo_empty2_4;
-    ZXIC_UINT32 ctrl_fifo_empty2_3;
-    ZXIC_UINT32 ctrl_fifo_empty2_2;
-    ZXIC_UINT32 ctrl_fifo_empty2_1;
-    ZXIC_UINT32 ctrl_fifo_empty2_0;
-}DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY2_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty3_t
-{
-    ZXIC_UINT32 ctrl_fifo_empty3_5;
-    ZXIC_UINT32 ctrl_fifo_empty3_4;
-    ZXIC_UINT32 ctrl_fifo_empty3_3;
-    ZXIC_UINT32 ctrl_fifo_empty3_2;
-    ZXIC_UINT32 ctrl_fifo_empty3_1;
-    ZXIC_UINT32 ctrl_fifo_empty3_0;
-}DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY3_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty4_t
-{
-    ZXIC_UINT32 ctrl_fifo_empty4_5;
-    ZXIC_UINT32 ctrl_fifo_empty4_4;
-    ZXIC_UINT32 ctrl_fifo_empty4_3;
-    ZXIC_UINT32 ctrl_fifo_empty4_2;
-    ZXIC_UINT32 ctrl_fifo_empty4_1;
-    ZXIC_UINT32 ctrl_fifo_empty4_0;
-}DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY4_T;
-
-typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty5_t
-{
-    ZXIC_UINT32 ctrl_fifo_empty5_1;
-    ZXIC_UINT32 ctrl_fifo_empty5_0;
-}DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY5_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty0_t
-{
-    ZXIC_UINT32 kschd_fifo_empty0;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY0_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty1_t
-{
-    ZXIC_UINT32 kschd_fifo_empty1;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY1_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty2_t
-{
-    ZXIC_UINT32 kschd_fifo_empty2;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY2_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty3_t
-{
-    ZXIC_UINT32 kschd_fifo_empty3;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY3_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty4_t
-{
-    ZXIC_UINT32 kschd_fifo_empty4;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY4_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty5_t
-{
-    ZXIC_UINT32 kschd_fifo_empty5;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY5_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty6_t
-{
-    ZXIC_UINT32 kschd_fifo_empty6;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY6_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty7_t
-{
-    ZXIC_UINT32 kschd_fifo_empty7;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY7_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty8_t
-{
-    ZXIC_UINT32 kschd_fifo_empty8;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY8_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty9_t
-{
-    ZXIC_UINT32 kschd_fifo_empty9;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY9_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty10_t
-{
-    ZXIC_UINT32 kschd_fifo_empty10;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY10_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty11_t
-{
-    ZXIC_UINT32 kschd_fifo_empty11;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY11_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty12_t
-{
-    ZXIC_UINT32 kschd_fifo_empty12;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY12_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty13_t
-{
-    ZXIC_UINT32 kschd_fifo_empty13;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY13_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty14_t
-{
-    ZXIC_UINT32 kschd_fifo_empty14;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY14_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty15_t
-{
-    ZXIC_UINT32 kschd_fifo_empty15;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY15_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty16_t
-{
-    ZXIC_UINT32 kschd_fifo_empty16;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY16_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty17_t
-{
-    ZXIC_UINT32 kschd_fifo_empty17;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY17_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty18_t
-{
-    ZXIC_UINT32 kschd_fifo_empty18;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY18_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty19_t
-{
-    ZXIC_UINT32 kschd_fifo_empty19;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY19_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty20_t
-{
-    ZXIC_UINT32 kschd_fifo_empty20;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY20_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty21_t
-{
-    ZXIC_UINT32 kschd_fifo_empty21;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY21_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty22_t
-{
-    ZXIC_UINT32 kschd_fifo_empty22;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY22_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty23_t
-{
-    ZXIC_UINT32 kschd_fifo_empty23;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY23_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty24_t
-{
-    ZXIC_UINT32 kschd_fifo_empty24;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY24_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty25_t
-{
-    ZXIC_UINT32 kschd_fifo_empty25;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY25_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty26_t
-{
-    ZXIC_UINT32 kschd_fifo_empty26;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY26_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty27_t
-{
-    ZXIC_UINT32 kschd_fifo_empty27;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY27_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty28_t
-{
-    ZXIC_UINT32 kschd_fifo_empty28;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY28_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty29_t
-{
-    ZXIC_UINT32 kschd_fifo_empty29;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY29_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty30_t
-{
-    ZXIC_UINT32 kschd_fifo_empty30;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY30_T;
-
-typedef struct dpp_smmu0_smmu0_kschd_fifo_empty31_t
-{
-    ZXIC_UINT32 kschd_fifo_empty31;
-}DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY31_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty0_t
-{
-    ZXIC_UINT32 rschd_fifo_empty0;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY0_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty1_t
-{
-    ZXIC_UINT32 rschd_fifo_empty1;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY1_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty2_t
-{
-    ZXIC_UINT32 rschd_fifo_empty2;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY2_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty3_t
-{
-    ZXIC_UINT32 rschd_fifo_empty3;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY3_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty4_t
-{
-    ZXIC_UINT32 rschd_fifo_empty4;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY4_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty5_t
-{
-    ZXIC_UINT32 rschd_fifo_empty5;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY5_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty6_t
-{
-    ZXIC_UINT32 rschd_fifo_empty6;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY6_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty7_t
-{
-    ZXIC_UINT32 rschd_fifo_empty7;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY7_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty8_t
-{
-    ZXIC_UINT32 rschd_fifo_empty8;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY8_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty9_t
-{
-    ZXIC_UINT32 rschd_fifo_empty9;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY9_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty10_t
-{
-    ZXIC_UINT32 rschd_fifo_empty10;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY10_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty11_t
-{
-    ZXIC_UINT32 rschd_fifo_empty11;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY11_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty12_t
-{
-    ZXIC_UINT32 rschd_fifo_empty12;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY12_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty13_t
-{
-    ZXIC_UINT32 rschd_fifo_empty13;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY13_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty14_t
-{
-    ZXIC_UINT32 rschd_fifo_empty14;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY14_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty15_t
-{
-    ZXIC_UINT32 rschd_fifo_empty15;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY15_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty16_t
-{
-    ZXIC_UINT32 rschd_fifo_empty16;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY16_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty17_t
-{
-    ZXIC_UINT32 rschd_fifo_empty17;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY17_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty18_t
-{
-    ZXIC_UINT32 rschd_fifo_empty18;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY18_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty19_t
-{
-    ZXIC_UINT32 rschd_fifo_empty19;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY19_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty20_t
-{
-    ZXIC_UINT32 rschd_fifo_empty20;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY20_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty21_t
-{
-    ZXIC_UINT32 rschd_fifo_empty21;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY21_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty22_t
-{
-    ZXIC_UINT32 rschd_fifo_empty22;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY22_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty23_t
-{
-    ZXIC_UINT32 rschd_fifo_empty23;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY23_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty24_t
-{
-    ZXIC_UINT32 rschd_fifo_empty24;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY24_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty25_t
-{
-    ZXIC_UINT32 rschd_fifo_empty25;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY25_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty26_t
-{
-    ZXIC_UINT32 rschd_fifo_empty26;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY26_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty27_t
-{
-    ZXIC_UINT32 rschd_fifo_empty27;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY27_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty28_t
-{
-    ZXIC_UINT32 rschd_fifo_empty28;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY28_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty29_t
-{
-    ZXIC_UINT32 rschd_fifo_empty29;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY29_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty30_t
-{
-    ZXIC_UINT32 rschd_fifo_empty30;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY30_T;
-
-typedef struct dpp_smmu0_smmu0_rschd_fifo_empty31_t
-{
-    ZXIC_UINT32 rschd_fifo_empty31;
-}DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY31_T;
-
-typedef struct dpp_smmu0_smmu0_ept_flag_t
-{
-    ZXIC_UINT32 ept_flag8;
-    ZXIC_UINT32 ept_flag7;
-    ZXIC_UINT32 ept_flag6;
-    ZXIC_UINT32 ept_flag5;
-    ZXIC_UINT32 ept_flag4;
-    ZXIC_UINT32 ept_flag3;
-    ZXIC_UINT32 ept_flag2;
-    ZXIC_UINT32 ept_flag1;
-    ZXIC_UINT32 ept_flag0;
-}DPP_SMMU0_SMMU0_EPT_FLAG_T;
-
-typedef struct dpp_smmu0_smmu0_ppu_soft_rst_t
-{
-    ZXIC_UINT32 ppu_soft_rst;
-}DPP_SMMU0_SMMU0_PPU_SOFT_RST_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_as_mac_age_fc_cnt_t
-{
-    ZXIC_UINT32 smmu0_as_mac_age_fc_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_AS_MAC_AGE_FC_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_marc_se_parser_fc_cnt_t
-{
-    ZXIC_UINT32 smmu0_marc_se_parser_fc_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_MARC_SE_PARSER_FC_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_wr_arb_cpu_fc_cnt_t
-{
-    ZXIC_UINT32 wr_arb_cpu_fc_cnt;
-}DPP_SMMU0_SMMU0_WR_ARB_CPU_FC_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_lpm_as_fc_cnt_t
-{
-    ZXIC_UINT32 smmu0_lpm_as_fc_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_LPM_AS_FC_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_lpm_as_smmu0_fc_cnt_t
-{
-    ZXIC_UINT32 lpm_as_smmu0_fc_cnt;
-}DPP_SMMU0_SMMU0_LPM_AS_SMMU0_FC_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_etcam1_0_as_fc_cnt_t
-{
-    ZXIC_UINT32 smmu0_etcam1_0_as_fc_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_FC_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_as_etcam1_0_smmu0_fc_cnt_t
-{
-    ZXIC_UINT32 as_etcam1_0_smmu0_fc_cnt;
-}DPP_SMMU0_SMMU0_AS_ETCAM1_0_SMMU0_FC_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_ppu_mcast_fc_cnt_t
-{
-    ZXIC_UINT32 smmu0_ppu_mcast_fc_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_PPU_MCAST_FC_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_ppu_smmu0_mcast_fc_cnt_t
-{
-    ZXIC_UINT32 ppu_smmu0_mcast_fc_cnt;
-}DPP_SMMU0_SMMU0_PPU_SMMU0_MCAST_FC_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_odma_smmu0_tdm_fc_rsp_fc_cnt_t
-{
-    ZXIC_UINT32 odma_smmu0_tdm_fc_rsp_fc_cnt;
-}DPP_SMMU0_SMMU0_ODMA_SMMU0_TDM_FC_RSP_FC_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_odma_tdm_fc_key_fc_cnt_t
-{
-    ZXIC_UINT32 smmu0_odma_tdm_fc_key_fc_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_ODMA_TDM_FC_KEY_FC_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_odma_fc_cnt_t
-{
-    ZXIC_UINT32 smmu0_odma_fc_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_ODMA_FC_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_cfg_tab_rd_fc_cnt_t
-{
-    ZXIC_UINT32 smmu0_cfg_tab_rd_fc_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_CFG_TAB_RD_FC_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_stat_fc15_0_cnt_t
-{
-    ZXIC_UINT32 smmu0_stat_fc15_0_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_STAT_FC15_0_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_stat_smmu0_fc15_0_cnt_t
-{
-    ZXIC_UINT32 stat_smmu0_fc15_0_cnt;
-}DPP_SMMU0_SMMU0_STAT_SMMU0_FC15_0_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_ppu_mex5_0_fc_cnt_t
-{
-    ZXIC_UINT32 smmu0_ppu_mex5_0_fc_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_PPU_MEX5_0_FC_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_ppu_smmu0_mex5_0_fc_cnt_t
-{
-    ZXIC_UINT32 ppu_smmu0_mex5_0_fc_cnt;
-}DPP_SMMU0_SMMU0_PPU_SMMU0_MEX5_0_FC_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_as_smmu0_mac_age_req_cnt_t
-{
-    ZXIC_UINT32 as_smmu0_mac_age_req_cnt;
-}DPP_SMMU0_SMMU0_AS_SMMU0_MAC_AGE_REQ_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_se_parser_smmu0_marc_key_cnt_t
-{
-    ZXIC_UINT32 se_parser_smmu0_marc_key_cnt;
-}DPP_SMMU0_SMMU0_SE_PARSER_SMMU0_MARC_KEY_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_cpu_ind_rdat_cnt_t
-{
-    ZXIC_UINT32 cpu_ind_rdat_cnt;
-}DPP_SMMU0_SMMU0_CPU_IND_RDAT_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_cpu_ind_rd_req_cnt_t
-{
-    ZXIC_UINT32 cpu_ind_rd_req_cnt;
-}DPP_SMMU0_SMMU0_CPU_IND_RD_REQ_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_cpu_ind_wr_req_cnt_t
-{
-    ZXIC_UINT32 cpu_ind_wr_req_cnt;
-}DPP_SMMU0_SMMU0_CPU_IND_WR_REQ_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_plcr_rsp0_cnt_t
-{
-    ZXIC_UINT32 smmu0_plcr_rsp0_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_PLCR_RSP0_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_plcr_smmu0_req0_cnt_t
-{
-    ZXIC_UINT32 plcr_smmu0_req0_cnt;
-}DPP_SMMU0_SMMU0_PLCR_SMMU0_REQ0_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_lpm_as_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu0_lpm_as_rsp_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_LPM_AS_RSP_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_lpm_as_smmu0_req_cnt_t
-{
-    ZXIC_UINT32 lpm_as_smmu0_req_cnt;
-}DPP_SMMU0_SMMU0_LPM_AS_SMMU0_REQ_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_etcam1_0_as_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu0_etcam1_0_as_rsp_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_RSP_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_etcam1_0_as_smmu0_req_cnt_t
-{
-    ZXIC_UINT32 etcam1_0_as_smmu0_req_cnt;
-}DPP_SMMU0_SMMU0_ETCAM1_0_AS_SMMU0_REQ_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_ppu_mcast_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu0_ppu_mcast_rsp_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_PPU_MCAST_RSP_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_ppu_smmu0_mcast_key_cnt_t
-{
-    ZXIC_UINT32 ppu_smmu0_mcast_key_cnt;
-}DPP_SMMU0_SMMU0_PPU_SMMU0_MCAST_KEY_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_odma_tdm_mc_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu0_odma_tdm_mc_rsp_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_ODMA_TDM_MC_RSP_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_odma_smmu0_tdm_mc_key_cnt_t
-{
-    ZXIC_UINT32 odma_smmu0_tdm_mc_key_cnt;
-}DPP_SMMU0_SMMU0_ODMA_SMMU0_TDM_MC_KEY_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_odma_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu0_odma_rsp_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_ODMA_RSP_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_odma_smmu0_cmd_cnt_t
-{
-    ZXIC_UINT32 odma_smmu0_cmd_cnt;
-}DPP_SMMU0_SMMU0_ODMA_SMMU0_CMD_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_cfg_tab_rdat_cnt_t
-{
-    ZXIC_UINT32 smmu0_cfg_tab_rdat_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_CFG_TAB_RDAT_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_cfg_smmu0_tab_rd_cnt_t
-{
-    ZXIC_UINT32 cfg_smmu0_tab_rd_cnt;
-}DPP_SMMU0_SMMU0_CFG_SMMU0_TAB_RD_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_stat_rsp15_0_cnt_t
-{
-    ZXIC_UINT32 smmu0_stat_rsp15_0_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_STAT_RSP15_0_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_stat_smmu0_req15_0_cnt_t
-{
-    ZXIC_UINT32 stat_smmu0_req15_0_cnt;
-}DPP_SMMU0_SMMU0_STAT_SMMU0_REQ15_0_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_smmu0_ppu_mex5_0_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu0_ppu_mex5_0_rsp_cnt;
-}DPP_SMMU0_SMMU0_SMMU0_PPU_MEX5_0_RSP_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_ppu_smmu0_mex5_0_key_cnt_t
-{
-    ZXIC_UINT32 ppu_smmu0_mex5_0_key_cnt;
-}DPP_SMMU0_SMMU0_PPU_SMMU0_MEX5_0_KEY_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_ftm_stat_smmu0_req0_cnt_t
-{
-    ZXIC_UINT32 ftm_stat_smmu0_req0_cnt;
-}DPP_SMMU0_SMMU0_FTM_STAT_SMMU0_REQ0_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_ftm_stat_smmu0_req1_cnt_t
-{
-    ZXIC_UINT32 ftm_stat_smmu0_req1_cnt;
-}DPP_SMMU0_SMMU0_FTM_STAT_SMMU0_REQ1_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_etm_stat_smmu0_req0_cnt_t
-{
-    ZXIC_UINT32 etm_stat_smmu0_req0_cnt;
-}DPP_SMMU0_SMMU0_ETM_STAT_SMMU0_REQ0_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_etm_stat_smmu0_req1_cnt_t
-{
-    ZXIC_UINT32 etm_stat_smmu0_req1_cnt;
-}DPP_SMMU0_SMMU0_ETM_STAT_SMMU0_REQ1_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_req_eram0_31_rd_cnt_t
-{
-    ZXIC_UINT32 req_eram0_31_rd_cnt;
-}DPP_SMMU0_SMMU0_REQ_ERAM0_31_RD_CNT_T;
-
-typedef struct dpp_smmu0_smmu0_req_eram0_31_wr_cnt_t
-{
-    ZXIC_UINT32 req_eram0_31_wr_cnt;
-}DPP_SMMU0_SMMU0_REQ_ERAM0_31_WR_CNT_T;
+typedef struct dpp_smmu0_smmu0_init_done_t {
+	ZXIC_UINT32 init_done;
+} DPP_SMMU0_SMMU0_INIT_DONE_T;
+
+typedef struct dpp_smmu0_smmu0_cpu_ind_wdat0_t {
+	ZXIC_UINT32 cpu_ind_wdat0;
+} DPP_SMMU0_SMMU0_CPU_IND_WDAT0_T;
+
+typedef struct dpp_smmu0_smmu0_cpu_ind_wdat1_t {
+	ZXIC_UINT32 cpu_ind_wdat1;
+} DPP_SMMU0_SMMU0_CPU_IND_WDAT1_T;
+
+typedef struct dpp_smmu0_smmu0_cpu_ind_wdat2_t {
+	ZXIC_UINT32 cpu_ind_wdat2;
+} DPP_SMMU0_SMMU0_CPU_IND_WDAT2_T;
+
+typedef struct dpp_smmu0_smmu0_cpu_ind_wdat3_t {
+	ZXIC_UINT32 cpu_ind_wdat3;
+} DPP_SMMU0_SMMU0_CPU_IND_WDAT3_T;
+
+typedef struct dpp_smmu0_smmu0_cpu_ind_cmd_t {
+	ZXIC_UINT32 cpu_ind_rw;
+	ZXIC_UINT32 cpu_ind_rd_mode;
+	ZXIC_UINT32 cpu_req_mode;
+	ZXIC_UINT32 cpu_ind_addr;
+} DPP_SMMU0_SMMU0_CPU_IND_CMD_T;
+
+typedef struct dpp_smmu0_smmu0_cpu_ind_rd_done_t {
+	ZXIC_UINT32 cpu_ind_rd_done;
+} DPP_SMMU0_SMMU0_CPU_IND_RD_DONE_T;
+
+typedef struct dpp_smmu0_smmu0_cpu_ind_rdat0_t {
+	ZXIC_UINT32 cpu_ind_rdat0;
+} DPP_SMMU0_SMMU0_CPU_IND_RDAT0_T;
+
+typedef struct dpp_smmu0_smmu0_cpu_ind_rdat1_t {
+	ZXIC_UINT32 cpu_ind_rdat1;
+} DPP_SMMU0_SMMU0_CPU_IND_RDAT1_T;
+
+typedef struct dpp_smmu0_smmu0_cpu_ind_rdat2_t {
+	ZXIC_UINT32 cpu_ind_rdat2;
+} DPP_SMMU0_SMMU0_CPU_IND_RDAT2_T;
+
+typedef struct dpp_smmu0_smmu0_cpu_ind_rdat3_t {
+	ZXIC_UINT32 cpu_ind_rdat3;
+} DPP_SMMU0_SMMU0_CPU_IND_RDAT3_T;
+
+typedef struct dpp_smmu0_smmu0_cfg_plcr_mono_t {
+	ZXIC_UINT32 cfg_plcr_mono;
+} DPP_SMMU0_SMMU0_CFG_PLCR_MONO_T;
+
+typedef struct dpp_smmu0_smmu0_wr_arb_cpu_rdy_t {
+	ZXIC_UINT32 wr_arb_cpu_rdy;
+} DPP_SMMU0_SMMU0_WR_ARB_CPU_RDY_T;
+
+typedef struct dpp_smmu0_smmu0_tm_stat_en_cfg_t {
+	ZXIC_UINT32 tm_stat_en_cfg;
+} DPP_SMMU0_SMMU0_TM_STAT_EN_CFG_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_pful_cfg0_t {
+	ZXIC_UINT32 kschd_pful_assert0_1;
+	ZXIC_UINT32 kschd_pful_negate0_1;
+	ZXIC_UINT32 kschd_pful_assert0_0;
+	ZXIC_UINT32 kschd_pful_negate0_0;
+} DPP_SMMU0_SMMU0_KSCHD_PFUL_CFG0_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_pful_cfg1_t {
+	ZXIC_UINT32 kschd_pful_assert1_1;
+	ZXIC_UINT32 kschd_pful_negate1_1;
+	ZXIC_UINT32 kschd_pful_assert1_0;
+	ZXIC_UINT32 kschd_pful_negate1_0;
+} DPP_SMMU0_SMMU0_KSCHD_PFUL_CFG1_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl_pful1_cfg_t {
+	ZXIC_UINT32 ctrl_pful1_assert;
+	ZXIC_UINT32 ctrl_pful1_negate;
+} DPP_SMMU0_SMMU0_CTRL_PFUL1_CFG_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl_pful2_cfg_t {
+	ZXIC_UINT32 ctrl_pful2_assert;
+	ZXIC_UINT32 ctrl_pful2_negate;
+} DPP_SMMU0_SMMU0_CTRL_PFUL2_CFG_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl_pful3_cfg_t {
+	ZXIC_UINT32 ctrl_pful3_assert;
+	ZXIC_UINT32 ctrl_pful3_negate;
+} DPP_SMMU0_SMMU0_CTRL_PFUL3_CFG_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_pful_cfg_t {
+	ZXIC_UINT32 rschd_pful_assert;
+	ZXIC_UINT32 rschd_pful_negate;
+} DPP_SMMU0_SMMU0_RSCHD_PFUL_CFG_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_ept_cfg_t {
+	ZXIC_UINT32 rschd_ept_assert;
+	ZXIC_UINT32 rschd_ept_negate;
+} DPP_SMMU0_SMMU0_RSCHD_EPT_CFG_T;
+
+typedef struct dpp_smmu0_smmu0_alucmd_pful_cfg_t {
+	ZXIC_UINT32 alucmd_pful_assert;
+	ZXIC_UINT32 alucmd_pful_negate;
+} DPP_SMMU0_SMMU0_ALUCMD_PFUL_CFG_T;
+
+typedef struct dpp_smmu0_smmu0_aluwr_pful_cfg_t {
+	ZXIC_UINT32 aluwr_pful_assert;
+	ZXIC_UINT32 aluwr_pful_negate;
+} DPP_SMMU0_SMMU0_ALUWR_PFUL_CFG_T;
+
+typedef struct dpp_smmu0_smmu0_wr_arb_pful_cfg0_t {
+	ZXIC_UINT32 wr_arb_pful0_assert;
+	ZXIC_UINT32 wr_arb_pful0_negate;
+} DPP_SMMU0_SMMU0_WR_ARB_PFUL_CFG0_T;
+
+typedef struct dpp_smmu0_smmu0_wr_arb_pful_cfg1_t {
+	ZXIC_UINT32 wr_arb_pful1_assert;
+	ZXIC_UINT32 wr_arb_pful1_negate;
+} DPP_SMMU0_SMMU0_WR_ARB_PFUL_CFG1_T;
+
+typedef struct dpp_smmu0_smmu0_ord_pful_cfg_t {
+	ZXIC_UINT32 ord_pful_assert;
+	ZXIC_UINT32 ord_pful_negate;
+} DPP_SMMU0_SMMU0_ORD_PFUL_CFG_T;
+
+typedef struct dpp_smmu0_smmu0_cfg_dma_baddr_t {
+	ZXIC_UINT32 cfg_dma_baddr;
+} DPP_SMMU0_SMMU0_CFG_DMA_BADDR_T;
+
+typedef struct dpp_smmu0_smmu0_cfg_odma0_baddr_t {
+	ZXIC_UINT32 cfg_odma0_baddr;
+} DPP_SMMU0_SMMU0_CFG_ODMA0_BADDR_T;
+
+typedef struct dpp_smmu0_smmu0_cfg_odma1_baddr_t {
+	ZXIC_UINT32 cfg_odma1_baddr;
+} DPP_SMMU0_SMMU0_CFG_ODMA1_BADDR_T;
+
+typedef struct dpp_smmu0_smmu0_cfg_odma2_baddr_t {
+	ZXIC_UINT32 cfg_odma2_baddr;
+} DPP_SMMU0_SMMU0_CFG_ODMA2_BADDR_T;
+
+typedef struct dpp_smmu0_smmu0_cfg_odma_tdm_baddr_t {
+	ZXIC_UINT32 cfg_odma_tdm_baddr;
+} DPP_SMMU0_SMMU0_CFG_ODMA_TDM_BADDR_T;
+
+typedef struct dpp_smmu0_smmu0_cfg_mcast_baddr_t {
+	ZXIC_UINT32 cfg_mcast_baddr;
+} DPP_SMMU0_SMMU0_CFG_MCAST_BADDR_T;
+
+typedef struct dpp_smmu0_smmu0_cfg_lpm0_t {
+	ZXIC_UINT32 lpm0_rsp_mode;
+	ZXIC_UINT32 lpm0_baddr;
+} DPP_SMMU0_SMMU0_CFG_LPM0_T;
+
+typedef struct dpp_smmu0_smmu0_cfg_lpm1_t {
+	ZXIC_UINT32 lpm1_rsp_mode;
+	ZXIC_UINT32 lpm1_baddr;
+} DPP_SMMU0_SMMU0_CFG_LPM1_T;
+
+typedef struct dpp_smmu0_smmu0_cfg_lpm2_t {
+	ZXIC_UINT32 lpm2_rsp_mode;
+	ZXIC_UINT32 lpm2_baddr;
+} DPP_SMMU0_SMMU0_CFG_LPM2_T;
+
+typedef struct dpp_smmu0_smmu0_cfg_lpm3_t {
+	ZXIC_UINT32 lpm3_rsp_mode;
+	ZXIC_UINT32 lpm3_baddr;
+} DPP_SMMU0_SMMU0_CFG_LPM3_T;
+
+typedef struct dpp_smmu0_smmu0_cfg_lpm4_t {
+	ZXIC_UINT32 lpm4_rsp_mode;
+	ZXIC_UINT32 lpm4_baddr;
+} DPP_SMMU0_SMMU0_CFG_LPM4_T;
+
+typedef struct dpp_smmu0_smmu0_cfg_lpm5_t {
+	ZXIC_UINT32 lpm5_rsp_mode;
+	ZXIC_UINT32 lpm5_baddr;
+} DPP_SMMU0_SMMU0_CFG_LPM5_T;
+
+typedef struct dpp_smmu0_smmu0_cfg_lpm6_t {
+	ZXIC_UINT32 lpm6_rsp_mode;
+	ZXIC_UINT32 lpm6_baddr;
+} DPP_SMMU0_SMMU0_CFG_LPM6_T;
+
+typedef struct dpp_smmu0_smmu0_cfg_lpm7_t {
+	ZXIC_UINT32 lpm7_rsp_mode;
+	ZXIC_UINT32 lpm7_baddr;
+} DPP_SMMU0_SMMU0_CFG_LPM7_T;
+
+typedef struct dpp_smmu0_smmu0_debug_cnt_mode_t {
+	ZXIC_UINT32 cnt_rd_mode;
+	ZXIC_UINT32 cnt_overflow_mode;
+} DPP_SMMU0_SMMU0_DEBUG_CNT_MODE_T;
+
+typedef struct dpp_smmu0_smmu0_stat_overflow_mode_t {
+	ZXIC_UINT32 stat_overflow_mode;
+} DPP_SMMU0_SMMU0_STAT_OVERFLOW_MODE_T;
+
+typedef struct dpp_smmu0_smmu0_init_en_cfg_tmp_t {
+	ZXIC_UINT32 init_en_cfg_tmp31;
+	ZXIC_UINT32 init_en_cfg_tmp30;
+	ZXIC_UINT32 init_en_cfg_tmp29;
+	ZXIC_UINT32 init_en_cfg_tmp28;
+	ZXIC_UINT32 init_en_cfg_tmp27;
+	ZXIC_UINT32 init_en_cfg_tmp26;
+	ZXIC_UINT32 init_en_cfg_tmp25;
+	ZXIC_UINT32 init_en_cfg_tmp24;
+	ZXIC_UINT32 init_en_cfg_tmp23;
+	ZXIC_UINT32 init_en_cfg_tmp22;
+	ZXIC_UINT32 init_en_cfg_tmp21;
+	ZXIC_UINT32 init_en_cfg_tmp20;
+	ZXIC_UINT32 init_en_cfg_tmp19;
+	ZXIC_UINT32 init_en_cfg_tmp18;
+	ZXIC_UINT32 init_en_cfg_tmp17;
+	ZXIC_UINT32 init_en_cfg_tmp16;
+	ZXIC_UINT32 init_en_cfg_tmp15;
+	ZXIC_UINT32 init_en_cfg_tmp14;
+	ZXIC_UINT32 init_en_cfg_tmp13;
+	ZXIC_UINT32 init_en_cfg_tmp12;
+	ZXIC_UINT32 init_en_cfg_tmp11;
+	ZXIC_UINT32 init_en_cfg_tmp10;
+	ZXIC_UINT32 init_en_cfg_tmp9;
+	ZXIC_UINT32 init_en_cfg_tmp8;
+	ZXIC_UINT32 init_en_cfg_tmp7;
+	ZXIC_UINT32 init_en_cfg_tmp6;
+	ZXIC_UINT32 init_en_cfg_tmp5;
+	ZXIC_UINT32 init_en_cfg_tmp4;
+	ZXIC_UINT32 init_en_cfg_tmp3;
+	ZXIC_UINT32 init_en_cfg_tmp2;
+	ZXIC_UINT32 init_en_cfg_tmp1;
+	ZXIC_UINT32 init_en_cfg_tmp0;
+} DPP_SMMU0_SMMU0_INIT_EN_CFG_TMP_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int_unmask_flag_t {
+	ZXIC_UINT32 smmu0_int0_31_unmask_flag;
+} DPP_SMMU0_SMMU0_SMMU0_INT_UNMASK_FLAG_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int0_en_t {
+	ZXIC_UINT32 smmu0_int0_en31;
+	ZXIC_UINT32 smmu0_int0_en30;
+	ZXIC_UINT32 smmu0_int0_en29;
+	ZXIC_UINT32 smmu0_int0_en28;
+	ZXIC_UINT32 smmu0_int0_en27;
+	ZXIC_UINT32 smmu0_int0_en26;
+	ZXIC_UINT32 smmu0_int0_en25;
+	ZXIC_UINT32 smmu0_int0_en24;
+	ZXIC_UINT32 smmu0_int0_en23;
+	ZXIC_UINT32 smmu0_int0_en22;
+	ZXIC_UINT32 smmu0_int0_en21;
+	ZXIC_UINT32 smmu0_int0_en20;
+	ZXIC_UINT32 smmu0_int0_en19;
+	ZXIC_UINT32 smmu0_int0_en18;
+	ZXIC_UINT32 smmu0_int0_en17;
+	ZXIC_UINT32 smmu0_int0_en16;
+	ZXIC_UINT32 smmu0_int0_en15;
+	ZXIC_UINT32 smmu0_int0_en14;
+	ZXIC_UINT32 smmu0_int0_en13;
+	ZXIC_UINT32 smmu0_int0_en12;
+	ZXIC_UINT32 smmu0_int0_en11;
+	ZXIC_UINT32 smmu0_int0_en10;
+	ZXIC_UINT32 smmu0_int0_en9;
+	ZXIC_UINT32 smmu0_int0_en8;
+	ZXIC_UINT32 smmu0_int0_en7;
+	ZXIC_UINT32 smmu0_int0_en6;
+	ZXIC_UINT32 smmu0_int0_en5;
+	ZXIC_UINT32 smmu0_int0_en4;
+	ZXIC_UINT32 smmu0_int0_en3;
+	ZXIC_UINT32 smmu0_int0_en2;
+	ZXIC_UINT32 smmu0_int0_en1;
+	ZXIC_UINT32 smmu0_int0_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT0_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int0_mask_t {
+	ZXIC_UINT32 smmu0_int0_mask31;
+	ZXIC_UINT32 smmu0_int0_mask30;
+	ZXIC_UINT32 smmu0_int0_mask29;
+	ZXIC_UINT32 smmu0_int0_mask28;
+	ZXIC_UINT32 smmu0_int0_mask27;
+	ZXIC_UINT32 smmu0_int0_mask26;
+	ZXIC_UINT32 smmu0_int0_mask25;
+	ZXIC_UINT32 smmu0_int0_mask24;
+	ZXIC_UINT32 smmu0_int0_mask23;
+	ZXIC_UINT32 smmu0_int0_mask22;
+	ZXIC_UINT32 smmu0_int0_mask21;
+	ZXIC_UINT32 smmu0_int0_mask20;
+	ZXIC_UINT32 smmu0_int0_mask19;
+	ZXIC_UINT32 smmu0_int0_mask18;
+	ZXIC_UINT32 smmu0_int0_mask17;
+	ZXIC_UINT32 smmu0_int0_mask16;
+	ZXIC_UINT32 smmu0_int0_mask15;
+	ZXIC_UINT32 smmu0_int0_mask14;
+	ZXIC_UINT32 smmu0_int0_mask13;
+	ZXIC_UINT32 smmu0_int0_mask12;
+	ZXIC_UINT32 smmu0_int0_mask11;
+	ZXIC_UINT32 smmu0_int0_mask10;
+	ZXIC_UINT32 smmu0_int0_mask9;
+	ZXIC_UINT32 smmu0_int0_mask8;
+	ZXIC_UINT32 smmu0_int0_mask7;
+	ZXIC_UINT32 smmu0_int0_mask6;
+	ZXIC_UINT32 smmu0_int0_mask5;
+	ZXIC_UINT32 smmu0_int0_mask4;
+	ZXIC_UINT32 smmu0_int0_mask3;
+	ZXIC_UINT32 smmu0_int0_mask2;
+	ZXIC_UINT32 smmu0_int0_mask1;
+	ZXIC_UINT32 smmu0_int0_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT0_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int0_status_t {
+	ZXIC_UINT32 smmu0_int0_status31;
+	ZXIC_UINT32 smmu0_int0_status30;
+	ZXIC_UINT32 smmu0_int0_status29;
+	ZXIC_UINT32 smmu0_int0_status28;
+	ZXIC_UINT32 smmu0_int0_status27;
+	ZXIC_UINT32 smmu0_int0_status26;
+	ZXIC_UINT32 smmu0_int0_status25;
+	ZXIC_UINT32 smmu0_int0_status24;
+	ZXIC_UINT32 smmu0_int0_status23;
+	ZXIC_UINT32 smmu0_int0_status22;
+	ZXIC_UINT32 smmu0_int0_status21;
+	ZXIC_UINT32 smmu0_int0_status20;
+	ZXIC_UINT32 smmu0_int0_status19;
+	ZXIC_UINT32 smmu0_int0_status18;
+	ZXIC_UINT32 smmu0_int0_status17;
+	ZXIC_UINT32 smmu0_int0_status16;
+	ZXIC_UINT32 smmu0_int0_status15;
+	ZXIC_UINT32 smmu0_int0_status14;
+	ZXIC_UINT32 smmu0_int0_status13;
+	ZXIC_UINT32 smmu0_int0_status12;
+	ZXIC_UINT32 smmu0_int0_status11;
+	ZXIC_UINT32 smmu0_int0_status10;
+	ZXIC_UINT32 smmu0_int0_status9;
+	ZXIC_UINT32 smmu0_int0_status8;
+	ZXIC_UINT32 smmu0_int0_status7;
+	ZXIC_UINT32 smmu0_int0_status6;
+	ZXIC_UINT32 smmu0_int0_status5;
+	ZXIC_UINT32 smmu0_int0_status4;
+	ZXIC_UINT32 smmu0_int0_status3;
+	ZXIC_UINT32 smmu0_int0_status2;
+	ZXIC_UINT32 smmu0_int0_status1;
+	ZXIC_UINT32 smmu0_int0_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT0_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int1_en_t {
+	ZXIC_UINT32 smmu0_int1_en31;
+	ZXIC_UINT32 smmu0_int1_en30;
+	ZXIC_UINT32 smmu0_int1_en29;
+	ZXIC_UINT32 smmu0_int1_en28;
+	ZXIC_UINT32 smmu0_int1_en27;
+	ZXIC_UINT32 smmu0_int1_en26;
+	ZXIC_UINT32 smmu0_int1_en25;
+	ZXIC_UINT32 smmu0_int1_en24;
+	ZXIC_UINT32 smmu0_int1_en23;
+	ZXIC_UINT32 smmu0_int1_en22;
+	ZXIC_UINT32 smmu0_int1_en21;
+	ZXIC_UINT32 smmu0_int1_en20;
+	ZXIC_UINT32 smmu0_int1_en19;
+	ZXIC_UINT32 smmu0_int1_en18;
+	ZXIC_UINT32 smmu0_int1_en17;
+	ZXIC_UINT32 smmu0_int1_en16;
+	ZXIC_UINT32 smmu0_int1_en15;
+	ZXIC_UINT32 smmu0_int1_en14;
+	ZXIC_UINT32 smmu0_int1_en13;
+	ZXIC_UINT32 smmu0_int1_en12;
+	ZXIC_UINT32 smmu0_int1_en11;
+	ZXIC_UINT32 smmu0_int1_en10;
+	ZXIC_UINT32 smmu0_int1_en9;
+	ZXIC_UINT32 smmu0_int1_en8;
+	ZXIC_UINT32 smmu0_int1_en7;
+	ZXIC_UINT32 smmu0_int1_en6;
+	ZXIC_UINT32 smmu0_int1_en5;
+	ZXIC_UINT32 smmu0_int1_en4;
+	ZXIC_UINT32 smmu0_int1_en3;
+	ZXIC_UINT32 smmu0_int1_en2;
+	ZXIC_UINT32 smmu0_int1_en1;
+	ZXIC_UINT32 smmu0_int1_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT1_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int1_mask_t {
+	ZXIC_UINT32 smmu0_int1_mask31;
+	ZXIC_UINT32 smmu0_int1_mask30;
+	ZXIC_UINT32 smmu0_int1_mask29;
+	ZXIC_UINT32 smmu0_int1_mask28;
+	ZXIC_UINT32 smmu0_int1_mask27;
+	ZXIC_UINT32 smmu0_int1_mask26;
+	ZXIC_UINT32 smmu0_int1_mask25;
+	ZXIC_UINT32 smmu0_int1_mask24;
+	ZXIC_UINT32 smmu0_int1_mask23;
+	ZXIC_UINT32 smmu0_int1_mask22;
+	ZXIC_UINT32 smmu0_int1_mask21;
+	ZXIC_UINT32 smmu0_int1_mask20;
+	ZXIC_UINT32 smmu0_int1_mask19;
+	ZXIC_UINT32 smmu0_int1_mask18;
+	ZXIC_UINT32 smmu0_int1_mask17;
+	ZXIC_UINT32 smmu0_int1_mask16;
+	ZXIC_UINT32 smmu0_int1_mask15;
+	ZXIC_UINT32 smmu0_int1_mask14;
+	ZXIC_UINT32 smmu0_int1_mask13;
+	ZXIC_UINT32 smmu0_int1_mask12;
+	ZXIC_UINT32 smmu0_int1_mask11;
+	ZXIC_UINT32 smmu0_int1_mask10;
+	ZXIC_UINT32 smmu0_int1_mask9;
+	ZXIC_UINT32 smmu0_int1_mask8;
+	ZXIC_UINT32 smmu0_int1_mask7;
+	ZXIC_UINT32 smmu0_int1_mask6;
+	ZXIC_UINT32 smmu0_int1_mask5;
+	ZXIC_UINT32 smmu0_int1_mask4;
+	ZXIC_UINT32 smmu0_int1_mask3;
+	ZXIC_UINT32 smmu0_int1_mask2;
+	ZXIC_UINT32 smmu0_int1_mask1;
+	ZXIC_UINT32 smmu0_int1_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT1_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int1_status_t {
+	ZXIC_UINT32 smmu0_int1_status31;
+	ZXIC_UINT32 smmu0_int1_status30;
+	ZXIC_UINT32 smmu0_int1_status29;
+	ZXIC_UINT32 smmu0_int1_status28;
+	ZXIC_UINT32 smmu0_int1_status27;
+	ZXIC_UINT32 smmu0_int1_status26;
+	ZXIC_UINT32 smmu0_int1_status25;
+	ZXIC_UINT32 smmu0_int1_status24;
+	ZXIC_UINT32 smmu0_int1_status23;
+	ZXIC_UINT32 smmu0_int1_status22;
+	ZXIC_UINT32 smmu0_int1_status21;
+	ZXIC_UINT32 smmu0_int1_status20;
+	ZXIC_UINT32 smmu0_int1_status19;
+	ZXIC_UINT32 smmu0_int1_status18;
+	ZXIC_UINT32 smmu0_int1_status17;
+	ZXIC_UINT32 smmu0_int1_status16;
+	ZXIC_UINT32 smmu0_int1_status15;
+	ZXIC_UINT32 smmu0_int1_status14;
+	ZXIC_UINT32 smmu0_int1_status13;
+	ZXIC_UINT32 smmu0_int1_status12;
+	ZXIC_UINT32 smmu0_int1_status11;
+	ZXIC_UINT32 smmu0_int1_status10;
+	ZXIC_UINT32 smmu0_int1_status9;
+	ZXIC_UINT32 smmu0_int1_status8;
+	ZXIC_UINT32 smmu0_int1_status7;
+	ZXIC_UINT32 smmu0_int1_status6;
+	ZXIC_UINT32 smmu0_int1_status5;
+	ZXIC_UINT32 smmu0_int1_status4;
+	ZXIC_UINT32 smmu0_int1_status3;
+	ZXIC_UINT32 smmu0_int1_status2;
+	ZXIC_UINT32 smmu0_int1_status1;
+	ZXIC_UINT32 smmu0_int1_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT1_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int2_en_t {
+	ZXIC_UINT32 smmu0_int2_en31;
+	ZXIC_UINT32 smmu0_int2_en30;
+	ZXIC_UINT32 smmu0_int2_en29;
+	ZXIC_UINT32 smmu0_int2_en28;
+	ZXIC_UINT32 smmu0_int2_en27;
+	ZXIC_UINT32 smmu0_int2_en26;
+	ZXIC_UINT32 smmu0_int2_en25;
+	ZXIC_UINT32 smmu0_int2_en24;
+	ZXIC_UINT32 smmu0_int2_en23;
+	ZXIC_UINT32 smmu0_int2_en22;
+	ZXIC_UINT32 smmu0_int2_en21;
+	ZXIC_UINT32 smmu0_int2_en20;
+	ZXIC_UINT32 smmu0_int2_en19;
+	ZXIC_UINT32 smmu0_int2_en18;
+	ZXIC_UINT32 smmu0_int2_en17;
+	ZXIC_UINT32 smmu0_int2_en16;
+	ZXIC_UINT32 smmu0_int2_en15;
+	ZXIC_UINT32 smmu0_int2_en14;
+	ZXIC_UINT32 smmu0_int2_en13;
+	ZXIC_UINT32 smmu0_int2_en12;
+	ZXIC_UINT32 smmu0_int2_en11;
+	ZXIC_UINT32 smmu0_int2_en10;
+	ZXIC_UINT32 smmu0_int2_en9;
+	ZXIC_UINT32 smmu0_int2_en8;
+	ZXIC_UINT32 smmu0_int2_en7;
+	ZXIC_UINT32 smmu0_int2_en6;
+	ZXIC_UINT32 smmu0_int2_en5;
+	ZXIC_UINT32 smmu0_int2_en4;
+	ZXIC_UINT32 smmu0_int2_en3;
+	ZXIC_UINT32 smmu0_int2_en2;
+	ZXIC_UINT32 smmu0_int2_en1;
+	ZXIC_UINT32 smmu0_int2_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT2_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int2_mask_t {
+	ZXIC_UINT32 smmu0_int2_mask31;
+	ZXIC_UINT32 smmu0_int2_mask30;
+	ZXIC_UINT32 smmu0_int2_mask29;
+	ZXIC_UINT32 smmu0_int2_mask28;
+	ZXIC_UINT32 smmu0_int2_mask27;
+	ZXIC_UINT32 smmu0_int2_mask26;
+	ZXIC_UINT32 smmu0_int2_mask25;
+	ZXIC_UINT32 smmu0_int2_mask24;
+	ZXIC_UINT32 smmu0_int2_mask23;
+	ZXIC_UINT32 smmu0_int2_mask22;
+	ZXIC_UINT32 smmu0_int2_mask21;
+	ZXIC_UINT32 smmu0_int2_mask20;
+	ZXIC_UINT32 smmu0_int2_mask19;
+	ZXIC_UINT32 smmu0_int2_mask18;
+	ZXIC_UINT32 smmu0_int2_mask17;
+	ZXIC_UINT32 smmu0_int2_mask16;
+	ZXIC_UINT32 smmu0_int2_mask15;
+	ZXIC_UINT32 smmu0_int2_mask14;
+	ZXIC_UINT32 smmu0_int2_mask13;
+	ZXIC_UINT32 smmu0_int2_mask12;
+	ZXIC_UINT32 smmu0_int2_mask11;
+	ZXIC_UINT32 smmu0_int2_mask10;
+	ZXIC_UINT32 smmu0_int2_mask9;
+	ZXIC_UINT32 smmu0_int2_mask8;
+	ZXIC_UINT32 smmu0_int2_mask7;
+	ZXIC_UINT32 smmu0_int2_mask6;
+	ZXIC_UINT32 smmu0_int2_mask5;
+	ZXIC_UINT32 smmu0_int2_mask4;
+	ZXIC_UINT32 smmu0_int2_mask3;
+	ZXIC_UINT32 smmu0_int2_mask2;
+	ZXIC_UINT32 smmu0_int2_mask1;
+	ZXIC_UINT32 smmu0_int2_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT2_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int2_status_t {
+	ZXIC_UINT32 smmu0_int2_status31;
+	ZXIC_UINT32 smmu0_int2_status30;
+	ZXIC_UINT32 smmu0_int2_status29;
+	ZXIC_UINT32 smmu0_int2_status28;
+	ZXIC_UINT32 smmu0_int2_status27;
+	ZXIC_UINT32 smmu0_int2_status26;
+	ZXIC_UINT32 smmu0_int2_status25;
+	ZXIC_UINT32 smmu0_int2_status24;
+	ZXIC_UINT32 smmu0_int2_status23;
+	ZXIC_UINT32 smmu0_int2_status22;
+	ZXIC_UINT32 smmu0_int2_status21;
+	ZXIC_UINT32 smmu0_int2_status20;
+	ZXIC_UINT32 smmu0_int2_status19;
+	ZXIC_UINT32 smmu0_int2_status18;
+	ZXIC_UINT32 smmu0_int2_status17;
+	ZXIC_UINT32 smmu0_int2_status16;
+	ZXIC_UINT32 smmu0_int2_status15;
+	ZXIC_UINT32 smmu0_int2_status14;
+	ZXIC_UINT32 smmu0_int2_status13;
+	ZXIC_UINT32 smmu0_int2_status12;
+	ZXIC_UINT32 smmu0_int2_status11;
+	ZXIC_UINT32 smmu0_int2_status10;
+	ZXIC_UINT32 smmu0_int2_status9;
+	ZXIC_UINT32 smmu0_int2_status8;
+	ZXIC_UINT32 smmu0_int2_status7;
+	ZXIC_UINT32 smmu0_int2_status6;
+	ZXIC_UINT32 smmu0_int2_status5;
+	ZXIC_UINT32 smmu0_int2_status4;
+	ZXIC_UINT32 smmu0_int2_status3;
+	ZXIC_UINT32 smmu0_int2_status2;
+	ZXIC_UINT32 smmu0_int2_status1;
+	ZXIC_UINT32 smmu0_int2_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT2_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int3_en_t {
+	ZXIC_UINT32 smmu0_int3_en31;
+	ZXIC_UINT32 smmu0_int3_en30;
+	ZXIC_UINT32 smmu0_int3_en29;
+	ZXIC_UINT32 smmu0_int3_en28;
+	ZXIC_UINT32 smmu0_int3_en27;
+	ZXIC_UINT32 smmu0_int3_en26;
+	ZXIC_UINT32 smmu0_int3_en25;
+	ZXIC_UINT32 smmu0_int3_en24;
+	ZXIC_UINT32 smmu0_int3_en23;
+	ZXIC_UINT32 smmu0_int3_en22;
+	ZXIC_UINT32 smmu0_int3_en21;
+	ZXIC_UINT32 smmu0_int3_en20;
+	ZXIC_UINT32 smmu0_int3_en19;
+	ZXIC_UINT32 smmu0_int3_en18;
+	ZXIC_UINT32 smmu0_int3_en17;
+	ZXIC_UINT32 smmu0_int3_en16;
+	ZXIC_UINT32 smmu0_int3_en15;
+	ZXIC_UINT32 smmu0_int3_en14;
+	ZXIC_UINT32 smmu0_int3_en13;
+	ZXIC_UINT32 smmu0_int3_en12;
+	ZXIC_UINT32 smmu0_int3_en11;
+	ZXIC_UINT32 smmu0_int3_en10;
+	ZXIC_UINT32 smmu0_int3_en9;
+	ZXIC_UINT32 smmu0_int3_en8;
+	ZXIC_UINT32 smmu0_int3_en7;
+	ZXIC_UINT32 smmu0_int3_en6;
+	ZXIC_UINT32 smmu0_int3_en5;
+	ZXIC_UINT32 smmu0_int3_en4;
+	ZXIC_UINT32 smmu0_int3_en3;
+	ZXIC_UINT32 smmu0_int3_en2;
+	ZXIC_UINT32 smmu0_int3_en1;
+	ZXIC_UINT32 smmu0_int3_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT3_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int3_mask_t {
+	ZXIC_UINT32 smmu0_int3_mask31;
+	ZXIC_UINT32 smmu0_int3_mask30;
+	ZXIC_UINT32 smmu0_int3_mask29;
+	ZXIC_UINT32 smmu0_int3_mask28;
+	ZXIC_UINT32 smmu0_int3_mask27;
+	ZXIC_UINT32 smmu0_int3_mask26;
+	ZXIC_UINT32 smmu0_int3_mask25;
+	ZXIC_UINT32 smmu0_int3_mask24;
+	ZXIC_UINT32 smmu0_int3_mask23;
+	ZXIC_UINT32 smmu0_int3_mask22;
+	ZXIC_UINT32 smmu0_int3_mask21;
+	ZXIC_UINT32 smmu0_int3_mask20;
+	ZXIC_UINT32 smmu0_int3_mask19;
+	ZXIC_UINT32 smmu0_int3_mask18;
+	ZXIC_UINT32 smmu0_int3_mask17;
+	ZXIC_UINT32 smmu0_int3_mask16;
+	ZXIC_UINT32 smmu0_int3_mask15;
+	ZXIC_UINT32 smmu0_int3_mask14;
+	ZXIC_UINT32 smmu0_int3_mask13;
+	ZXIC_UINT32 smmu0_int3_mask12;
+	ZXIC_UINT32 smmu0_int3_mask11;
+	ZXIC_UINT32 smmu0_int3_mask10;
+	ZXIC_UINT32 smmu0_int3_mask9;
+	ZXIC_UINT32 smmu0_int3_mask8;
+	ZXIC_UINT32 smmu0_int3_mask7;
+	ZXIC_UINT32 smmu0_int3_mask6;
+	ZXIC_UINT32 smmu0_int3_mask5;
+	ZXIC_UINT32 smmu0_int3_mask4;
+	ZXIC_UINT32 smmu0_int3_mask3;
+	ZXIC_UINT32 smmu0_int3_mask2;
+	ZXIC_UINT32 smmu0_int3_mask1;
+	ZXIC_UINT32 smmu0_int3_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT3_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int3_status_t {
+	ZXIC_UINT32 smmu0_int3_status31;
+	ZXIC_UINT32 smmu0_int3_status30;
+	ZXIC_UINT32 smmu0_int3_status29;
+	ZXIC_UINT32 smmu0_int3_status28;
+	ZXIC_UINT32 smmu0_int3_status27;
+	ZXIC_UINT32 smmu0_int3_status26;
+	ZXIC_UINT32 smmu0_int3_status25;
+	ZXIC_UINT32 smmu0_int3_status24;
+	ZXIC_UINT32 smmu0_int3_status23;
+	ZXIC_UINT32 smmu0_int3_status22;
+	ZXIC_UINT32 smmu0_int3_status21;
+	ZXIC_UINT32 smmu0_int3_status20;
+	ZXIC_UINT32 smmu0_int3_status19;
+	ZXIC_UINT32 smmu0_int3_status18;
+	ZXIC_UINT32 smmu0_int3_status17;
+	ZXIC_UINT32 smmu0_int3_status16;
+	ZXIC_UINT32 smmu0_int3_status15;
+	ZXIC_UINT32 smmu0_int3_status14;
+	ZXIC_UINT32 smmu0_int3_status13;
+	ZXIC_UINT32 smmu0_int3_status12;
+	ZXIC_UINT32 smmu0_int3_status11;
+	ZXIC_UINT32 smmu0_int3_status10;
+	ZXIC_UINT32 smmu0_int3_status9;
+	ZXIC_UINT32 smmu0_int3_status8;
+	ZXIC_UINT32 smmu0_int3_status7;
+	ZXIC_UINT32 smmu0_int3_status6;
+	ZXIC_UINT32 smmu0_int3_status5;
+	ZXIC_UINT32 smmu0_int3_status4;
+	ZXIC_UINT32 smmu0_int3_status3;
+	ZXIC_UINT32 smmu0_int3_status2;
+	ZXIC_UINT32 smmu0_int3_status1;
+	ZXIC_UINT32 smmu0_int3_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT3_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int4_en_t {
+	ZXIC_UINT32 smmu0_int4_en31;
+	ZXIC_UINT32 smmu0_int4_en30;
+	ZXIC_UINT32 smmu0_int4_en29;
+	ZXIC_UINT32 smmu0_int4_en28;
+	ZXIC_UINT32 smmu0_int4_en27;
+	ZXIC_UINT32 smmu0_int4_en26;
+	ZXIC_UINT32 smmu0_int4_en25;
+	ZXIC_UINT32 smmu0_int4_en24;
+	ZXIC_UINT32 smmu0_int4_en23;
+	ZXIC_UINT32 smmu0_int4_en22;
+	ZXIC_UINT32 smmu0_int4_en21;
+	ZXIC_UINT32 smmu0_int4_en20;
+	ZXIC_UINT32 smmu0_int4_en19;
+	ZXIC_UINT32 smmu0_int4_en18;
+	ZXIC_UINT32 smmu0_int4_en17;
+	ZXIC_UINT32 smmu0_int4_en16;
+	ZXIC_UINT32 smmu0_int4_en15;
+	ZXIC_UINT32 smmu0_int4_en14;
+	ZXIC_UINT32 smmu0_int4_en13;
+	ZXIC_UINT32 smmu0_int4_en12;
+	ZXIC_UINT32 smmu0_int4_en11;
+	ZXIC_UINT32 smmu0_int4_en10;
+	ZXIC_UINT32 smmu0_int4_en9;
+	ZXIC_UINT32 smmu0_int4_en8;
+	ZXIC_UINT32 smmu0_int4_en7;
+	ZXIC_UINT32 smmu0_int4_en6;
+	ZXIC_UINT32 smmu0_int4_en5;
+	ZXIC_UINT32 smmu0_int4_en4;
+	ZXIC_UINT32 smmu0_int4_en3;
+	ZXIC_UINT32 smmu0_int4_en2;
+	ZXIC_UINT32 smmu0_int4_en1;
+	ZXIC_UINT32 smmu0_int4_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT4_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int4_mask_t {
+	ZXIC_UINT32 smmu0_int4_mask31;
+	ZXIC_UINT32 smmu0_int4_mask30;
+	ZXIC_UINT32 smmu0_int4_mask29;
+	ZXIC_UINT32 smmu0_int4_mask28;
+	ZXIC_UINT32 smmu0_int4_mask27;
+	ZXIC_UINT32 smmu0_int4_mask26;
+	ZXIC_UINT32 smmu0_int4_mask25;
+	ZXIC_UINT32 smmu0_int4_mask24;
+	ZXIC_UINT32 smmu0_int4_mask23;
+	ZXIC_UINT32 smmu0_int4_mask22;
+	ZXIC_UINT32 smmu0_int4_mask21;
+	ZXIC_UINT32 smmu0_int4_mask20;
+	ZXIC_UINT32 smmu0_int4_mask19;
+	ZXIC_UINT32 smmu0_int4_mask18;
+	ZXIC_UINT32 smmu0_int4_mask17;
+	ZXIC_UINT32 smmu0_int4_mask16;
+	ZXIC_UINT32 smmu0_int4_mask15;
+	ZXIC_UINT32 smmu0_int4_mask14;
+	ZXIC_UINT32 smmu0_int4_mask13;
+	ZXIC_UINT32 smmu0_int4_mask12;
+	ZXIC_UINT32 smmu0_int4_mask11;
+	ZXIC_UINT32 smmu0_int4_mask10;
+	ZXIC_UINT32 smmu0_int4_mask9;
+	ZXIC_UINT32 smmu0_int4_mask8;
+	ZXIC_UINT32 smmu0_int4_mask7;
+	ZXIC_UINT32 smmu0_int4_mask6;
+	ZXIC_UINT32 smmu0_int4_mask5;
+	ZXIC_UINT32 smmu0_int4_mask4;
+	ZXIC_UINT32 smmu0_int4_mask3;
+	ZXIC_UINT32 smmu0_int4_mask2;
+	ZXIC_UINT32 smmu0_int4_mask1;
+	ZXIC_UINT32 smmu0_int4_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT4_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int4_status_t {
+	ZXIC_UINT32 smmu0_int4_status31;
+	ZXIC_UINT32 smmu0_int4_status30;
+	ZXIC_UINT32 smmu0_int4_status29;
+	ZXIC_UINT32 smmu0_int4_status28;
+	ZXIC_UINT32 smmu0_int4_status27;
+	ZXIC_UINT32 smmu0_int4_status26;
+	ZXIC_UINT32 smmu0_int4_status25;
+	ZXIC_UINT32 smmu0_int4_status24;
+	ZXIC_UINT32 smmu0_int4_status23;
+	ZXIC_UINT32 smmu0_int4_status22;
+	ZXIC_UINT32 smmu0_int4_status21;
+	ZXIC_UINT32 smmu0_int4_status20;
+	ZXIC_UINT32 smmu0_int4_status19;
+	ZXIC_UINT32 smmu0_int4_status18;
+	ZXIC_UINT32 smmu0_int4_status17;
+	ZXIC_UINT32 smmu0_int4_status16;
+	ZXIC_UINT32 smmu0_int4_status15;
+	ZXIC_UINT32 smmu0_int4_status14;
+	ZXIC_UINT32 smmu0_int4_status13;
+	ZXIC_UINT32 smmu0_int4_status12;
+	ZXIC_UINT32 smmu0_int4_status11;
+	ZXIC_UINT32 smmu0_int4_status10;
+	ZXIC_UINT32 smmu0_int4_status9;
+	ZXIC_UINT32 smmu0_int4_status8;
+	ZXIC_UINT32 smmu0_int4_status7;
+	ZXIC_UINT32 smmu0_int4_status6;
+	ZXIC_UINT32 smmu0_int4_status5;
+	ZXIC_UINT32 smmu0_int4_status4;
+	ZXIC_UINT32 smmu0_int4_status3;
+	ZXIC_UINT32 smmu0_int4_status2;
+	ZXIC_UINT32 smmu0_int4_status1;
+	ZXIC_UINT32 smmu0_int4_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT4_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int5_en_t {
+	ZXIC_UINT32 smmu0_int5_en31;
+	ZXIC_UINT32 smmu0_int5_en30;
+	ZXIC_UINT32 smmu0_int5_en29;
+	ZXIC_UINT32 smmu0_int5_en28;
+	ZXIC_UINT32 smmu0_int5_en27;
+	ZXIC_UINT32 smmu0_int5_en26;
+	ZXIC_UINT32 smmu0_int5_en25;
+	ZXIC_UINT32 smmu0_int5_en24;
+	ZXIC_UINT32 smmu0_int5_en23;
+	ZXIC_UINT32 smmu0_int5_en22;
+	ZXIC_UINT32 smmu0_int5_en21;
+	ZXIC_UINT32 smmu0_int5_en20;
+	ZXIC_UINT32 smmu0_int5_en19;
+	ZXIC_UINT32 smmu0_int5_en18;
+	ZXIC_UINT32 smmu0_int5_en17;
+	ZXIC_UINT32 smmu0_int5_en16;
+	ZXIC_UINT32 smmu0_int5_en15;
+	ZXIC_UINT32 smmu0_int5_en14;
+	ZXIC_UINT32 smmu0_int5_en13;
+	ZXIC_UINT32 smmu0_int5_en12;
+	ZXIC_UINT32 smmu0_int5_en11;
+	ZXIC_UINT32 smmu0_int5_en10;
+	ZXIC_UINT32 smmu0_int5_en9;
+	ZXIC_UINT32 smmu0_int5_en8;
+	ZXIC_UINT32 smmu0_int5_en7;
+	ZXIC_UINT32 smmu0_int5_en6;
+	ZXIC_UINT32 smmu0_int5_en5;
+	ZXIC_UINT32 smmu0_int5_en4;
+	ZXIC_UINT32 smmu0_int5_en3;
+	ZXIC_UINT32 smmu0_int5_en2;
+	ZXIC_UINT32 smmu0_int5_en1;
+	ZXIC_UINT32 smmu0_int5_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT5_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int5_mask_t {
+	ZXIC_UINT32 smmu0_int5_mask31;
+	ZXIC_UINT32 smmu0_int5_mask30;
+	ZXIC_UINT32 smmu0_int5_mask29;
+	ZXIC_UINT32 smmu0_int5_mask28;
+	ZXIC_UINT32 smmu0_int5_mask27;
+	ZXIC_UINT32 smmu0_int5_mask26;
+	ZXIC_UINT32 smmu0_int5_mask25;
+	ZXIC_UINT32 smmu0_int5_mask24;
+	ZXIC_UINT32 smmu0_int5_mask23;
+	ZXIC_UINT32 smmu0_int5_mask22;
+	ZXIC_UINT32 smmu0_int5_mask21;
+	ZXIC_UINT32 smmu0_int5_mask20;
+	ZXIC_UINT32 smmu0_int5_mask19;
+	ZXIC_UINT32 smmu0_int5_mask18;
+	ZXIC_UINT32 smmu0_int5_mask17;
+	ZXIC_UINT32 smmu0_int5_mask16;
+	ZXIC_UINT32 smmu0_int5_mask15;
+	ZXIC_UINT32 smmu0_int5_mask14;
+	ZXIC_UINT32 smmu0_int5_mask13;
+	ZXIC_UINT32 smmu0_int5_mask12;
+	ZXIC_UINT32 smmu0_int5_mask11;
+	ZXIC_UINT32 smmu0_int5_mask10;
+	ZXIC_UINT32 smmu0_int5_mask9;
+	ZXIC_UINT32 smmu0_int5_mask8;
+	ZXIC_UINT32 smmu0_int5_mask7;
+	ZXIC_UINT32 smmu0_int5_mask6;
+	ZXIC_UINT32 smmu0_int5_mask5;
+	ZXIC_UINT32 smmu0_int5_mask4;
+	ZXIC_UINT32 smmu0_int5_mask3;
+	ZXIC_UINT32 smmu0_int5_mask2;
+	ZXIC_UINT32 smmu0_int5_mask1;
+	ZXIC_UINT32 smmu0_int5_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT5_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int5_status_t {
+	ZXIC_UINT32 smmu0_int5_status31;
+	ZXIC_UINT32 smmu0_int5_status30;
+	ZXIC_UINT32 smmu0_int5_status29;
+	ZXIC_UINT32 smmu0_int5_status28;
+	ZXIC_UINT32 smmu0_int5_status27;
+	ZXIC_UINT32 smmu0_int5_status26;
+	ZXIC_UINT32 smmu0_int5_status25;
+	ZXIC_UINT32 smmu0_int5_status24;
+	ZXIC_UINT32 smmu0_int5_status23;
+	ZXIC_UINT32 smmu0_int5_status22;
+	ZXIC_UINT32 smmu0_int5_status21;
+	ZXIC_UINT32 smmu0_int5_status20;
+	ZXIC_UINT32 smmu0_int5_status19;
+	ZXIC_UINT32 smmu0_int5_status18;
+	ZXIC_UINT32 smmu0_int5_status17;
+	ZXIC_UINT32 smmu0_int5_status16;
+	ZXIC_UINT32 smmu0_int5_status15;
+	ZXIC_UINT32 smmu0_int5_status14;
+	ZXIC_UINT32 smmu0_int5_status13;
+	ZXIC_UINT32 smmu0_int5_status12;
+	ZXIC_UINT32 smmu0_int5_status11;
+	ZXIC_UINT32 smmu0_int5_status10;
+	ZXIC_UINT32 smmu0_int5_status9;
+	ZXIC_UINT32 smmu0_int5_status8;
+	ZXIC_UINT32 smmu0_int5_status7;
+	ZXIC_UINT32 smmu0_int5_status6;
+	ZXIC_UINT32 smmu0_int5_status5;
+	ZXIC_UINT32 smmu0_int5_status4;
+	ZXIC_UINT32 smmu0_int5_status3;
+	ZXIC_UINT32 smmu0_int5_status2;
+	ZXIC_UINT32 smmu0_int5_status1;
+	ZXIC_UINT32 smmu0_int5_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT5_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int6_en_t {
+	ZXIC_UINT32 smmu0_int6_en31;
+	ZXIC_UINT32 smmu0_int6_en30;
+	ZXIC_UINT32 smmu0_int6_en29;
+	ZXIC_UINT32 smmu0_int6_en28;
+	ZXIC_UINT32 smmu0_int6_en27;
+	ZXIC_UINT32 smmu0_int6_en26;
+	ZXIC_UINT32 smmu0_int6_en25;
+	ZXIC_UINT32 smmu0_int6_en24;
+	ZXIC_UINT32 smmu0_int6_en23;
+	ZXIC_UINT32 smmu0_int6_en22;
+	ZXIC_UINT32 smmu0_int6_en21;
+	ZXIC_UINT32 smmu0_int6_en20;
+	ZXIC_UINT32 smmu0_int6_en19;
+	ZXIC_UINT32 smmu0_int6_en18;
+	ZXIC_UINT32 smmu0_int6_en17;
+	ZXIC_UINT32 smmu0_int6_en16;
+	ZXIC_UINT32 smmu0_int6_en15;
+	ZXIC_UINT32 smmu0_int6_en14;
+	ZXIC_UINT32 smmu0_int6_en13;
+	ZXIC_UINT32 smmu0_int6_en12;
+	ZXIC_UINT32 smmu0_int6_en11;
+	ZXIC_UINT32 smmu0_int6_en10;
+	ZXIC_UINT32 smmu0_int6_en9;
+	ZXIC_UINT32 smmu0_int6_en8;
+	ZXIC_UINT32 smmu0_int6_en7;
+	ZXIC_UINT32 smmu0_int6_en6;
+	ZXIC_UINT32 smmu0_int6_en5;
+	ZXIC_UINT32 smmu0_int6_en4;
+	ZXIC_UINT32 smmu0_int6_en3;
+	ZXIC_UINT32 smmu0_int6_en2;
+	ZXIC_UINT32 smmu0_int6_en1;
+	ZXIC_UINT32 smmu0_int6_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT6_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int6_mask_t {
+	ZXIC_UINT32 smmu0_int6_mask31;
+	ZXIC_UINT32 smmu0_int6_mask30;
+	ZXIC_UINT32 smmu0_int6_mask29;
+	ZXIC_UINT32 smmu0_int6_mask28;
+	ZXIC_UINT32 smmu0_int6_mask27;
+	ZXIC_UINT32 smmu0_int6_mask26;
+	ZXIC_UINT32 smmu0_int6_mask25;
+	ZXIC_UINT32 smmu0_int6_mask24;
+	ZXIC_UINT32 smmu0_int6_mask23;
+	ZXIC_UINT32 smmu0_int6_mask22;
+	ZXIC_UINT32 smmu0_int6_mask21;
+	ZXIC_UINT32 smmu0_int6_mask20;
+	ZXIC_UINT32 smmu0_int6_mask19;
+	ZXIC_UINT32 smmu0_int6_mask18;
+	ZXIC_UINT32 smmu0_int6_mask17;
+	ZXIC_UINT32 smmu0_int6_mask16;
+	ZXIC_UINT32 smmu0_int6_mask15;
+	ZXIC_UINT32 smmu0_int6_mask14;
+	ZXIC_UINT32 smmu0_int6_mask13;
+	ZXIC_UINT32 smmu0_int6_mask12;
+	ZXIC_UINT32 smmu0_int6_mask11;
+	ZXIC_UINT32 smmu0_int6_mask10;
+	ZXIC_UINT32 smmu0_int6_mask9;
+	ZXIC_UINT32 smmu0_int6_mask8;
+	ZXIC_UINT32 smmu0_int6_mask7;
+	ZXIC_UINT32 smmu0_int6_mask6;
+	ZXIC_UINT32 smmu0_int6_mask5;
+	ZXIC_UINT32 smmu0_int6_mask4;
+	ZXIC_UINT32 smmu0_int6_mask3;
+	ZXIC_UINT32 smmu0_int6_mask2;
+	ZXIC_UINT32 smmu0_int6_mask1;
+	ZXIC_UINT32 smmu0_int6_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT6_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int6_status_t {
+	ZXIC_UINT32 smmu0_int6_status31;
+	ZXIC_UINT32 smmu0_int6_status30;
+	ZXIC_UINT32 smmu0_int6_status29;
+	ZXIC_UINT32 smmu0_int6_status28;
+	ZXIC_UINT32 smmu0_int6_status27;
+	ZXIC_UINT32 smmu0_int6_status26;
+	ZXIC_UINT32 smmu0_int6_status25;
+	ZXIC_UINT32 smmu0_int6_status24;
+	ZXIC_UINT32 smmu0_int6_status23;
+	ZXIC_UINT32 smmu0_int6_status22;
+	ZXIC_UINT32 smmu0_int6_status21;
+	ZXIC_UINT32 smmu0_int6_status20;
+	ZXIC_UINT32 smmu0_int6_status19;
+	ZXIC_UINT32 smmu0_int6_status18;
+	ZXIC_UINT32 smmu0_int6_status17;
+	ZXIC_UINT32 smmu0_int6_status16;
+	ZXIC_UINT32 smmu0_int6_status15;
+	ZXIC_UINT32 smmu0_int6_status14;
+	ZXIC_UINT32 smmu0_int6_status13;
+	ZXIC_UINT32 smmu0_int6_status12;
+	ZXIC_UINT32 smmu0_int6_status11;
+	ZXIC_UINT32 smmu0_int6_status10;
+	ZXIC_UINT32 smmu0_int6_status9;
+	ZXIC_UINT32 smmu0_int6_status8;
+	ZXIC_UINT32 smmu0_int6_status7;
+	ZXIC_UINT32 smmu0_int6_status6;
+	ZXIC_UINT32 smmu0_int6_status5;
+	ZXIC_UINT32 smmu0_int6_status4;
+	ZXIC_UINT32 smmu0_int6_status3;
+	ZXIC_UINT32 smmu0_int6_status2;
+	ZXIC_UINT32 smmu0_int6_status1;
+	ZXIC_UINT32 smmu0_int6_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT6_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int7_en_t {
+	ZXIC_UINT32 smmu0_int7_en31;
+	ZXIC_UINT32 smmu0_int7_en30;
+	ZXIC_UINT32 smmu0_int7_en29;
+	ZXIC_UINT32 smmu0_int7_en28;
+	ZXIC_UINT32 smmu0_int7_en27;
+	ZXIC_UINT32 smmu0_int7_en26;
+	ZXIC_UINT32 smmu0_int7_en25;
+	ZXIC_UINT32 smmu0_int7_en24;
+	ZXIC_UINT32 smmu0_int7_en23;
+	ZXIC_UINT32 smmu0_int7_en22;
+	ZXIC_UINT32 smmu0_int7_en21;
+	ZXIC_UINT32 smmu0_int7_en20;
+	ZXIC_UINT32 smmu0_int7_en19;
+	ZXIC_UINT32 smmu0_int7_en18;
+	ZXIC_UINT32 smmu0_int7_en17;
+	ZXIC_UINT32 smmu0_int7_en16;
+	ZXIC_UINT32 smmu0_int7_en15;
+	ZXIC_UINT32 smmu0_int7_en14;
+	ZXIC_UINT32 smmu0_int7_en13;
+	ZXIC_UINT32 smmu0_int7_en12;
+	ZXIC_UINT32 smmu0_int7_en11;
+	ZXIC_UINT32 smmu0_int7_en10;
+	ZXIC_UINT32 smmu0_int7_en9;
+	ZXIC_UINT32 smmu0_int7_en8;
+	ZXIC_UINT32 smmu0_int7_en7;
+	ZXIC_UINT32 smmu0_int7_en6;
+	ZXIC_UINT32 smmu0_int7_en5;
+	ZXIC_UINT32 smmu0_int7_en4;
+	ZXIC_UINT32 smmu0_int7_en3;
+	ZXIC_UINT32 smmu0_int7_en2;
+	ZXIC_UINT32 smmu0_int7_en1;
+	ZXIC_UINT32 smmu0_int7_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT7_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int7_mask_t {
+	ZXIC_UINT32 smmu0_int7_mask31;
+	ZXIC_UINT32 smmu0_int7_mask30;
+	ZXIC_UINT32 smmu0_int7_mask29;
+	ZXIC_UINT32 smmu0_int7_mask28;
+	ZXIC_UINT32 smmu0_int7_mask27;
+	ZXIC_UINT32 smmu0_int7_mask26;
+	ZXIC_UINT32 smmu0_int7_mask25;
+	ZXIC_UINT32 smmu0_int7_mask24;
+	ZXIC_UINT32 smmu0_int7_mask23;
+	ZXIC_UINT32 smmu0_int7_mask22;
+	ZXIC_UINT32 smmu0_int7_mask21;
+	ZXIC_UINT32 smmu0_int7_mask20;
+	ZXIC_UINT32 smmu0_int7_mask19;
+	ZXIC_UINT32 smmu0_int7_mask18;
+	ZXIC_UINT32 smmu0_int7_mask17;
+	ZXIC_UINT32 smmu0_int7_mask16;
+	ZXIC_UINT32 smmu0_int7_mask15;
+	ZXIC_UINT32 smmu0_int7_mask14;
+	ZXIC_UINT32 smmu0_int7_mask13;
+	ZXIC_UINT32 smmu0_int7_mask12;
+	ZXIC_UINT32 smmu0_int7_mask11;
+	ZXIC_UINT32 smmu0_int7_mask10;
+	ZXIC_UINT32 smmu0_int7_mask9;
+	ZXIC_UINT32 smmu0_int7_mask8;
+	ZXIC_UINT32 smmu0_int7_mask7;
+	ZXIC_UINT32 smmu0_int7_mask6;
+	ZXIC_UINT32 smmu0_int7_mask5;
+	ZXIC_UINT32 smmu0_int7_mask4;
+	ZXIC_UINT32 smmu0_int7_mask3;
+	ZXIC_UINT32 smmu0_int7_mask2;
+	ZXIC_UINT32 smmu0_int7_mask1;
+	ZXIC_UINT32 smmu0_int7_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT7_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int7_status_t {
+	ZXIC_UINT32 smmu0_int7_status31;
+	ZXIC_UINT32 smmu0_int7_status30;
+	ZXIC_UINT32 smmu0_int7_status29;
+	ZXIC_UINT32 smmu0_int7_status28;
+	ZXIC_UINT32 smmu0_int7_status27;
+	ZXIC_UINT32 smmu0_int7_status26;
+	ZXIC_UINT32 smmu0_int7_status25;
+	ZXIC_UINT32 smmu0_int7_status24;
+	ZXIC_UINT32 smmu0_int7_status23;
+	ZXIC_UINT32 smmu0_int7_status22;
+	ZXIC_UINT32 smmu0_int7_status21;
+	ZXIC_UINT32 smmu0_int7_status20;
+	ZXIC_UINT32 smmu0_int7_status19;
+	ZXIC_UINT32 smmu0_int7_status18;
+	ZXIC_UINT32 smmu0_int7_status17;
+	ZXIC_UINT32 smmu0_int7_status16;
+	ZXIC_UINT32 smmu0_int7_status15;
+	ZXIC_UINT32 smmu0_int7_status14;
+	ZXIC_UINT32 smmu0_int7_status13;
+	ZXIC_UINT32 smmu0_int7_status12;
+	ZXIC_UINT32 smmu0_int7_status11;
+	ZXIC_UINT32 smmu0_int7_status10;
+	ZXIC_UINT32 smmu0_int7_status9;
+	ZXIC_UINT32 smmu0_int7_status8;
+	ZXIC_UINT32 smmu0_int7_status7;
+	ZXIC_UINT32 smmu0_int7_status6;
+	ZXIC_UINT32 smmu0_int7_status5;
+	ZXIC_UINT32 smmu0_int7_status4;
+	ZXIC_UINT32 smmu0_int7_status3;
+	ZXIC_UINT32 smmu0_int7_status2;
+	ZXIC_UINT32 smmu0_int7_status1;
+	ZXIC_UINT32 smmu0_int7_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT7_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int8_en_t {
+	ZXIC_UINT32 smmu0_int8_en31;
+	ZXIC_UINT32 smmu0_int8_en30;
+	ZXIC_UINT32 smmu0_int8_en29;
+	ZXIC_UINT32 smmu0_int8_en28;
+	ZXIC_UINT32 smmu0_int8_en27;
+	ZXIC_UINT32 smmu0_int8_en26;
+	ZXIC_UINT32 smmu0_int8_en25;
+	ZXIC_UINT32 smmu0_int8_en24;
+	ZXIC_UINT32 smmu0_int8_en23;
+	ZXIC_UINT32 smmu0_int8_en22;
+	ZXIC_UINT32 smmu0_int8_en21;
+	ZXIC_UINT32 smmu0_int8_en20;
+	ZXIC_UINT32 smmu0_int8_en19;
+	ZXIC_UINT32 smmu0_int8_en18;
+	ZXIC_UINT32 smmu0_int8_en17;
+	ZXIC_UINT32 smmu0_int8_en16;
+	ZXIC_UINT32 smmu0_int8_en15;
+	ZXIC_UINT32 smmu0_int8_en14;
+	ZXIC_UINT32 smmu0_int8_en13;
+	ZXIC_UINT32 smmu0_int8_en12;
+	ZXIC_UINT32 smmu0_int8_en11;
+	ZXIC_UINT32 smmu0_int8_en10;
+	ZXIC_UINT32 smmu0_int8_en9;
+	ZXIC_UINT32 smmu0_int8_en8;
+	ZXIC_UINT32 smmu0_int8_en7;
+	ZXIC_UINT32 smmu0_int8_en6;
+	ZXIC_UINT32 smmu0_int8_en5;
+	ZXIC_UINT32 smmu0_int8_en4;
+	ZXIC_UINT32 smmu0_int8_en3;
+	ZXIC_UINT32 smmu0_int8_en2;
+	ZXIC_UINT32 smmu0_int8_en1;
+	ZXIC_UINT32 smmu0_int8_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT8_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int8_mask_t {
+	ZXIC_UINT32 smmu0_int8_mask31;
+	ZXIC_UINT32 smmu0_int8_mask30;
+	ZXIC_UINT32 smmu0_int8_mask29;
+	ZXIC_UINT32 smmu0_int8_mask28;
+	ZXIC_UINT32 smmu0_int8_mask27;
+	ZXIC_UINT32 smmu0_int8_mask26;
+	ZXIC_UINT32 smmu0_int8_mask25;
+	ZXIC_UINT32 smmu0_int8_mask24;
+	ZXIC_UINT32 smmu0_int8_mask23;
+	ZXIC_UINT32 smmu0_int8_mask22;
+	ZXIC_UINT32 smmu0_int8_mask21;
+	ZXIC_UINT32 smmu0_int8_mask20;
+	ZXIC_UINT32 smmu0_int8_mask19;
+	ZXIC_UINT32 smmu0_int8_mask18;
+	ZXIC_UINT32 smmu0_int8_mask17;
+	ZXIC_UINT32 smmu0_int8_mask16;
+	ZXIC_UINT32 smmu0_int8_mask15;
+	ZXIC_UINT32 smmu0_int8_mask14;
+	ZXIC_UINT32 smmu0_int8_mask13;
+	ZXIC_UINT32 smmu0_int8_mask12;
+	ZXIC_UINT32 smmu0_int8_mask11;
+	ZXIC_UINT32 smmu0_int8_mask10;
+	ZXIC_UINT32 smmu0_int8_mask9;
+	ZXIC_UINT32 smmu0_int8_mask8;
+	ZXIC_UINT32 smmu0_int8_mask7;
+	ZXIC_UINT32 smmu0_int8_mask6;
+	ZXIC_UINT32 smmu0_int8_mask5;
+	ZXIC_UINT32 smmu0_int8_mask4;
+	ZXIC_UINT32 smmu0_int8_mask3;
+	ZXIC_UINT32 smmu0_int8_mask2;
+	ZXIC_UINT32 smmu0_int8_mask1;
+	ZXIC_UINT32 smmu0_int8_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT8_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int8_status_t {
+	ZXIC_UINT32 smmu0_int8_status31;
+	ZXIC_UINT32 smmu0_int8_status30;
+	ZXIC_UINT32 smmu0_int8_status29;
+	ZXIC_UINT32 smmu0_int8_status28;
+	ZXIC_UINT32 smmu0_int8_status27;
+	ZXIC_UINT32 smmu0_int8_status26;
+	ZXIC_UINT32 smmu0_int8_status25;
+	ZXIC_UINT32 smmu0_int8_status24;
+	ZXIC_UINT32 smmu0_int8_status23;
+	ZXIC_UINT32 smmu0_int8_status22;
+	ZXIC_UINT32 smmu0_int8_status21;
+	ZXIC_UINT32 smmu0_int8_status20;
+	ZXIC_UINT32 smmu0_int8_status19;
+	ZXIC_UINT32 smmu0_int8_status18;
+	ZXIC_UINT32 smmu0_int8_status17;
+	ZXIC_UINT32 smmu0_int8_status16;
+	ZXIC_UINT32 smmu0_int8_status15;
+	ZXIC_UINT32 smmu0_int8_status14;
+	ZXIC_UINT32 smmu0_int8_status13;
+	ZXIC_UINT32 smmu0_int8_status12;
+	ZXIC_UINT32 smmu0_int8_status11;
+	ZXIC_UINT32 smmu0_int8_status10;
+	ZXIC_UINT32 smmu0_int8_status9;
+	ZXIC_UINT32 smmu0_int8_status8;
+	ZXIC_UINT32 smmu0_int8_status7;
+	ZXIC_UINT32 smmu0_int8_status6;
+	ZXIC_UINT32 smmu0_int8_status5;
+	ZXIC_UINT32 smmu0_int8_status4;
+	ZXIC_UINT32 smmu0_int8_status3;
+	ZXIC_UINT32 smmu0_int8_status2;
+	ZXIC_UINT32 smmu0_int8_status1;
+	ZXIC_UINT32 smmu0_int8_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT8_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int9_en_t {
+	ZXIC_UINT32 smmu0_int8_en31;
+	ZXIC_UINT32 smmu0_int8_en30;
+	ZXIC_UINT32 smmu0_int8_en29;
+	ZXIC_UINT32 smmu0_int8_en28;
+	ZXIC_UINT32 smmu0_int8_en27;
+	ZXIC_UINT32 smmu0_int8_en26;
+	ZXIC_UINT32 smmu0_int8_en25;
+	ZXIC_UINT32 smmu0_int8_en24;
+	ZXIC_UINT32 smmu0_int8_en23;
+	ZXIC_UINT32 smmu0_int8_en22;
+	ZXIC_UINT32 smmu0_int8_en21;
+	ZXIC_UINT32 smmu0_int8_en20;
+	ZXIC_UINT32 smmu0_int9_en19;
+	ZXIC_UINT32 smmu0_int9_en18;
+	ZXIC_UINT32 smmu0_int9_en17;
+	ZXIC_UINT32 smmu0_int9_en16;
+	ZXIC_UINT32 smmu0_int9_en15;
+	ZXIC_UINT32 smmu0_int9_en14;
+	ZXIC_UINT32 smmu0_int9_en13;
+	ZXIC_UINT32 smmu0_int9_en12;
+	ZXIC_UINT32 smmu0_int9_en11;
+	ZXIC_UINT32 smmu0_int9_en10;
+	ZXIC_UINT32 smmu0_int9_en9;
+	ZXIC_UINT32 smmu0_int9_en8;
+	ZXIC_UINT32 smmu0_int9_en7;
+	ZXIC_UINT32 smmu0_int9_en6;
+	ZXIC_UINT32 smmu0_int9_en5;
+	ZXIC_UINT32 smmu0_int9_en4;
+	ZXIC_UINT32 smmu0_int9_en3;
+	ZXIC_UINT32 smmu0_int9_en2;
+	ZXIC_UINT32 smmu0_int9_en1;
+	ZXIC_UINT32 smmu0_int9_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT9_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int9_mask_t {
+	ZXIC_UINT32 smmu0_int9_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT9_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int9_status_t {
+	ZXIC_UINT32 smmu0_int9_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT9_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int10_en_t {
+	ZXIC_UINT32 smmu0_int10_en31;
+	ZXIC_UINT32 smmu0_int10_en30;
+	ZXIC_UINT32 smmu0_int10_en29;
+	ZXIC_UINT32 smmu0_int10_en28;
+	ZXIC_UINT32 smmu0_int10_en27;
+	ZXIC_UINT32 smmu0_int10_en26;
+	ZXIC_UINT32 smmu0_int10_en25;
+	ZXIC_UINT32 smmu0_int10_en24;
+	ZXIC_UINT32 smmu0_int10_en23;
+	ZXIC_UINT32 smmu0_int10_en22;
+	ZXIC_UINT32 smmu0_int10_en21;
+	ZXIC_UINT32 smmu0_int10_en20;
+	ZXIC_UINT32 smmu0_int10_en19;
+	ZXIC_UINT32 smmu0_int10_en18;
+	ZXIC_UINT32 smmu0_int10_en17;
+	ZXIC_UINT32 smmu0_int10_en16;
+	ZXIC_UINT32 smmu0_int10_en15;
+	ZXIC_UINT32 smmu0_int10_en14;
+	ZXIC_UINT32 smmu0_int10_en13;
+	ZXIC_UINT32 smmu0_int10_en12;
+	ZXIC_UINT32 smmu0_int10_en11;
+	ZXIC_UINT32 smmu0_int10_en10;
+	ZXIC_UINT32 smmu0_int10_en9;
+	ZXIC_UINT32 smmu0_int10_en8;
+	ZXIC_UINT32 smmu0_int10_en7;
+	ZXIC_UINT32 smmu0_int10_en6;
+	ZXIC_UINT32 smmu0_int10_en5;
+	ZXIC_UINT32 smmu0_int10_en4;
+	ZXIC_UINT32 smmu0_int10_en3;
+	ZXIC_UINT32 smmu0_int10_en2;
+	ZXIC_UINT32 smmu0_int10_en1;
+	ZXIC_UINT32 smmu0_int10_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT10_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int10_mask_t {
+	ZXIC_UINT32 smmu0_int10_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT10_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int10_status_t {
+	ZXIC_UINT32 smmu0_int10_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT10_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int11_en_t {
+	ZXIC_UINT32 smmu0_int11_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT11_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int11_mask_t {
+	ZXIC_UINT32 smmu0_int11_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT11_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int11_status_t {
+	ZXIC_UINT32 smmu0_int11_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT11_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int12_en_t {
+	ZXIC_UINT32 smmu0_int12_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT12_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int12_mask_t {
+	ZXIC_UINT32 smmu0_int12_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT12_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int12_status_t {
+	ZXIC_UINT32 smmu0_int12_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT12_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int13_en_t {
+	ZXIC_UINT32 smmu0_int13_en19;
+	ZXIC_UINT32 smmu0_int13_en18;
+	ZXIC_UINT32 smmu0_int13_en17;
+	ZXIC_UINT32 smmu0_int13_en16;
+	ZXIC_UINT32 smmu0_int13_en15;
+	ZXIC_UINT32 smmu0_int13_en14;
+	ZXIC_UINT32 smmu0_int13_en13;
+	ZXIC_UINT32 smmu0_int13_en12;
+	ZXIC_UINT32 smmu0_int13_en11;
+	ZXIC_UINT32 smmu0_int13_en10;
+	ZXIC_UINT32 smmu0_int13_en9;
+	ZXIC_UINT32 smmu0_int13_en8;
+	ZXIC_UINT32 smmu0_int13_en7;
+	ZXIC_UINT32 smmu0_int13_en6;
+	ZXIC_UINT32 smmu0_int13_en5;
+	ZXIC_UINT32 smmu0_int13_en4;
+	ZXIC_UINT32 smmu0_int13_en3;
+	ZXIC_UINT32 smmu0_int13_en2;
+	ZXIC_UINT32 smmu0_int13_en1;
+	ZXIC_UINT32 smmu0_int13_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT13_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int13_mask_t {
+	ZXIC_UINT32 smmu0_int13_mask19;
+	ZXIC_UINT32 smmu0_int13_mask18;
+	ZXIC_UINT32 smmu0_int13_mask17;
+	ZXIC_UINT32 smmu0_int13_mask16;
+	ZXIC_UINT32 smmu0_int13_mask15;
+	ZXIC_UINT32 smmu0_int13_mask14;
+	ZXIC_UINT32 smmu0_int13_mask13;
+	ZXIC_UINT32 smmu0_int13_mask12;
+	ZXIC_UINT32 smmu0_int13_mask11;
+	ZXIC_UINT32 smmu0_int13_mask10;
+	ZXIC_UINT32 smmu0_int13_mask9;
+	ZXIC_UINT32 smmu0_int13_mask8;
+	ZXIC_UINT32 smmu0_int13_mask7;
+	ZXIC_UINT32 smmu0_int13_mask6;
+	ZXIC_UINT32 smmu0_int13_mask5;
+	ZXIC_UINT32 smmu0_int13_mask4;
+	ZXIC_UINT32 smmu0_int13_mask3;
+	ZXIC_UINT32 smmu0_int13_mask2;
+	ZXIC_UINT32 smmu0_int13_mask1;
+	ZXIC_UINT32 smmu0_int13_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT13_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int13_status_t {
+	ZXIC_UINT32 smmu0_int13_status19;
+	ZXIC_UINT32 smmu0_int13_status18;
+	ZXIC_UINT32 smmu0_int13_status17;
+	ZXIC_UINT32 smmu0_int13_status16;
+	ZXIC_UINT32 smmu0_int13_status15;
+	ZXIC_UINT32 smmu0_int13_status14;
+	ZXIC_UINT32 smmu0_int13_status13;
+	ZXIC_UINT32 smmu0_int13_status12;
+	ZXIC_UINT32 smmu0_int13_status11;
+	ZXIC_UINT32 smmu0_int13_status10;
+	ZXIC_UINT32 smmu0_int13_status9;
+	ZXIC_UINT32 smmu0_int13_status8;
+	ZXIC_UINT32 smmu0_int13_status7;
+	ZXIC_UINT32 smmu0_int13_status6;
+	ZXIC_UINT32 smmu0_int13_status5;
+	ZXIC_UINT32 smmu0_int13_status4;
+	ZXIC_UINT32 smmu0_int13_status3;
+	ZXIC_UINT32 smmu0_int13_status2;
+	ZXIC_UINT32 smmu0_int13_status1;
+	ZXIC_UINT32 smmu0_int13_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT13_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int14_en_t {
+	ZXIC_UINT32 smmu0_int14_en16;
+	ZXIC_UINT32 smmu0_int14_en15;
+	ZXIC_UINT32 smmu0_int14_en14;
+	ZXIC_UINT32 smmu0_int14_en13;
+	ZXIC_UINT32 smmu0_int14_en12;
+	ZXIC_UINT32 smmu0_int14_en11;
+	ZXIC_UINT32 smmu0_int14_en10;
+	ZXIC_UINT32 smmu0_int14_en9;
+	ZXIC_UINT32 smmu0_int14_en8;
+	ZXIC_UINT32 smmu0_int14_en7;
+	ZXIC_UINT32 smmu0_int14_en6;
+	ZXIC_UINT32 smmu0_int14_en5;
+	ZXIC_UINT32 smmu0_int14_en4;
+	ZXIC_UINT32 smmu0_int14_en3;
+	ZXIC_UINT32 smmu0_int14_en2;
+	ZXIC_UINT32 smmu0_int14_en1;
+	ZXIC_UINT32 smmu0_int14_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT14_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int14_mask_t {
+	ZXIC_UINT32 smmu0_int14_mask16;
+	ZXIC_UINT32 smmu0_int14_mask15;
+	ZXIC_UINT32 smmu0_int14_mask14;
+	ZXIC_UINT32 smmu0_int14_mask13;
+	ZXIC_UINT32 smmu0_int14_mask12;
+	ZXIC_UINT32 smmu0_int14_mask11;
+	ZXIC_UINT32 smmu0_int14_mask10;
+	ZXIC_UINT32 smmu0_int14_mask9;
+	ZXIC_UINT32 smmu0_int14_mask8;
+	ZXIC_UINT32 smmu0_int14_mask7;
+	ZXIC_UINT32 smmu0_int14_mask6;
+	ZXIC_UINT32 smmu0_int14_mask5;
+	ZXIC_UINT32 smmu0_int14_mask4;
+	ZXIC_UINT32 smmu0_int14_mask3;
+	ZXIC_UINT32 smmu0_int14_mask2;
+	ZXIC_UINT32 smmu0_int14_mask1;
+	ZXIC_UINT32 smmu0_int14_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT14_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int14_status_t {
+	ZXIC_UINT32 smmu0_int14_status16;
+	ZXIC_UINT32 smmu0_int14_status15;
+	ZXIC_UINT32 smmu0_int14_status14;
+	ZXIC_UINT32 smmu0_int14_status13;
+	ZXIC_UINT32 smmu0_int14_status12;
+	ZXIC_UINT32 smmu0_int14_status11;
+	ZXIC_UINT32 smmu0_int14_status10;
+	ZXIC_UINT32 smmu0_int14_status9;
+	ZXIC_UINT32 smmu0_int14_status8;
+	ZXIC_UINT32 smmu0_int14_status7;
+	ZXIC_UINT32 smmu0_int14_status6;
+	ZXIC_UINT32 smmu0_int14_status5;
+	ZXIC_UINT32 smmu0_int14_status4;
+	ZXIC_UINT32 smmu0_int14_status3;
+	ZXIC_UINT32 smmu0_int14_status2;
+	ZXIC_UINT32 smmu0_int14_status1;
+	ZXIC_UINT32 smmu0_int14_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT14_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_ecc_unmask_flag_t {
+	ZXIC_UINT32 smmu0_int53_unmask_flag;
+	ZXIC_UINT32 smmu0_int52_unmask_flag;
+	ZXIC_UINT32 smmu0_int51_unmask_flag;
+	ZXIC_UINT32 smmu0_int50_unmask_flag;
+	ZXIC_UINT32 smmu0_int49_unmask_flag;
+	ZXIC_UINT32 smmu0_int48_unmask_flag;
+	ZXIC_UINT32 smmu0_int47_unmask_flag;
+	ZXIC_UINT32 smmu0_int46_unmask_flag;
+	ZXIC_UINT32 smmu0_int45_unmask_flag;
+	ZXIC_UINT32 smmu0_int44_unmask_flag;
+	ZXIC_UINT32 smmu0_int43_unmask_flag;
+	ZXIC_UINT32 smmu0_int42_unmask_flag;
+	ZXIC_UINT32 smmu0_int41_unmask_flag;
+	ZXIC_UINT32 smmu0_int40_unmask_flag;
+	ZXIC_UINT32 smmu0_int39_unmask_flag;
+	ZXIC_UINT32 smmu0_int38_unmask_flag;
+	ZXIC_UINT32 smmu0_int37_unmask_flag;
+	ZXIC_UINT32 smmu0_int36_unmask_flag;
+	ZXIC_UINT32 smmu0_int35_unmask_flag;
+	ZXIC_UINT32 smmu0_int34_unmask_flag;
+	ZXIC_UINT32 smmu0_int33_unmask_flag;
+	ZXIC_UINT32 smmu0_int32_unmask_flag;
+} DPP_SMMU0_SMMU0_SMMU0_ECC_UNMASK_FLAG_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int15_en_t {
+	ZXIC_UINT32 smmu0_int15_en31;
+	ZXIC_UINT32 smmu0_int15_en30;
+	ZXIC_UINT32 smmu0_int15_en29;
+	ZXIC_UINT32 smmu0_int15_en28;
+	ZXIC_UINT32 smmu0_int15_en27;
+	ZXIC_UINT32 smmu0_int15_en26;
+	ZXIC_UINT32 smmu0_int15_en25;
+	ZXIC_UINT32 smmu0_int15_en24;
+	ZXIC_UINT32 smmu0_int15_en23;
+	ZXIC_UINT32 smmu0_int15_en22;
+	ZXIC_UINT32 smmu0_int15_en21;
+	ZXIC_UINT32 smmu0_int15_en20;
+	ZXIC_UINT32 smmu0_int15_en19;
+	ZXIC_UINT32 smmu0_int15_en18;
+	ZXIC_UINT32 smmu0_int15_en17;
+	ZXIC_UINT32 smmu0_int15_en16;
+	ZXIC_UINT32 smmu0_int15_en15;
+	ZXIC_UINT32 smmu0_int15_en14;
+	ZXIC_UINT32 smmu0_int15_en13;
+	ZXIC_UINT32 smmu0_int15_en12;
+	ZXIC_UINT32 smmu0_int15_en11;
+	ZXIC_UINT32 smmu0_int15_en10;
+	ZXIC_UINT32 smmu0_int15_en9;
+	ZXIC_UINT32 smmu0_int15_en8;
+	ZXIC_UINT32 smmu0_int15_en7;
+	ZXIC_UINT32 smmu0_int15_en6;
+	ZXIC_UINT32 smmu0_int15_en5;
+	ZXIC_UINT32 smmu0_int15_en4;
+	ZXIC_UINT32 smmu0_int15_en3;
+	ZXIC_UINT32 smmu0_int15_en2;
+	ZXIC_UINT32 smmu0_int15_en1;
+	ZXIC_UINT32 smmu0_int15_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT15_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int15_mask_t {
+	ZXIC_UINT32 smmu0_int15_mask31;
+	ZXIC_UINT32 smmu0_int15_mask30;
+	ZXIC_UINT32 smmu0_int15_mask29;
+	ZXIC_UINT32 smmu0_int15_mask28;
+	ZXIC_UINT32 smmu0_int15_mask27;
+	ZXIC_UINT32 smmu0_int15_mask26;
+	ZXIC_UINT32 smmu0_int15_mask25;
+	ZXIC_UINT32 smmu0_int15_mask24;
+	ZXIC_UINT32 smmu0_int15_mask23;
+	ZXIC_UINT32 smmu0_int15_mask22;
+	ZXIC_UINT32 smmu0_int15_mask21;
+	ZXIC_UINT32 smmu0_int15_mask20;
+	ZXIC_UINT32 smmu0_int15_mask19;
+	ZXIC_UINT32 smmu0_int15_mask18;
+	ZXIC_UINT32 smmu0_int15_mask17;
+	ZXIC_UINT32 smmu0_int15_mask16;
+	ZXIC_UINT32 smmu0_int15_mask15;
+	ZXIC_UINT32 smmu0_int15_mask14;
+	ZXIC_UINT32 smmu0_int15_mask13;
+	ZXIC_UINT32 smmu0_int15_mask12;
+	ZXIC_UINT32 smmu0_int15_mask11;
+	ZXIC_UINT32 smmu0_int15_mask10;
+	ZXIC_UINT32 smmu0_int15_mask9;
+	ZXIC_UINT32 smmu0_int15_mask8;
+	ZXIC_UINT32 smmu0_int15_mask7;
+	ZXIC_UINT32 smmu0_int15_mask6;
+	ZXIC_UINT32 smmu0_int15_mask5;
+	ZXIC_UINT32 smmu0_int15_mask4;
+	ZXIC_UINT32 smmu0_int15_mask3;
+	ZXIC_UINT32 smmu0_int15_mask2;
+	ZXIC_UINT32 smmu0_int15_mask1;
+	ZXIC_UINT32 smmu0_int15_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT15_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int15_status_t {
+	ZXIC_UINT32 smmu0_int15_status31;
+	ZXIC_UINT32 smmu0_int15_status30;
+	ZXIC_UINT32 smmu0_int15_status29;
+	ZXIC_UINT32 smmu0_int15_status28;
+	ZXIC_UINT32 smmu0_int15_status27;
+	ZXIC_UINT32 smmu0_int15_status26;
+	ZXIC_UINT32 smmu0_int15_status25;
+	ZXIC_UINT32 smmu0_int15_status24;
+	ZXIC_UINT32 smmu0_int15_status23;
+	ZXIC_UINT32 smmu0_int15_status22;
+	ZXIC_UINT32 smmu0_int15_status21;
+	ZXIC_UINT32 smmu0_int15_status20;
+	ZXIC_UINT32 smmu0_int15_status19;
+	ZXIC_UINT32 smmu0_int15_status18;
+	ZXIC_UINT32 smmu0_int15_status17;
+	ZXIC_UINT32 smmu0_int15_status16;
+	ZXIC_UINT32 smmu0_int15_status15;
+	ZXIC_UINT32 smmu0_int15_status14;
+	ZXIC_UINT32 smmu0_int15_status13;
+	ZXIC_UINT32 smmu0_int15_status12;
+	ZXIC_UINT32 smmu0_int15_status11;
+	ZXIC_UINT32 smmu0_int15_status10;
+	ZXIC_UINT32 smmu0_int15_status9;
+	ZXIC_UINT32 smmu0_int15_status8;
+	ZXIC_UINT32 smmu0_int15_status7;
+	ZXIC_UINT32 smmu0_int15_status6;
+	ZXIC_UINT32 smmu0_int15_status5;
+	ZXIC_UINT32 smmu0_int15_status4;
+	ZXIC_UINT32 smmu0_int15_status3;
+	ZXIC_UINT32 smmu0_int15_status2;
+	ZXIC_UINT32 smmu0_int15_status1;
+	ZXIC_UINT32 smmu0_int15_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT15_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int16_en_t {
+	ZXIC_UINT32 smmu0_int16_en31;
+	ZXIC_UINT32 smmu0_int16_en30;
+	ZXIC_UINT32 smmu0_int16_en29;
+	ZXIC_UINT32 smmu0_int16_en28;
+	ZXIC_UINT32 smmu0_int16_en27;
+	ZXIC_UINT32 smmu0_int16_en26;
+	ZXIC_UINT32 smmu0_int16_en25;
+	ZXIC_UINT32 smmu0_int16_en24;
+	ZXIC_UINT32 smmu0_int16_en23;
+	ZXIC_UINT32 smmu0_int16_en22;
+	ZXIC_UINT32 smmu0_int16_en21;
+	ZXIC_UINT32 smmu0_int16_en20;
+	ZXIC_UINT32 smmu0_int16_en19;
+	ZXIC_UINT32 smmu0_int16_en18;
+	ZXIC_UINT32 smmu0_int16_en17;
+	ZXIC_UINT32 smmu0_int16_en16;
+	ZXIC_UINT32 smmu0_int16_en15;
+	ZXIC_UINT32 smmu0_int16_en14;
+	ZXIC_UINT32 smmu0_int16_en13;
+	ZXIC_UINT32 smmu0_int16_en12;
+	ZXIC_UINT32 smmu0_int16_en11;
+	ZXIC_UINT32 smmu0_int16_en10;
+	ZXIC_UINT32 smmu0_int16_en9;
+	ZXIC_UINT32 smmu0_int16_en8;
+	ZXIC_UINT32 smmu0_int16_en7;
+	ZXIC_UINT32 smmu0_int16_en6;
+	ZXIC_UINT32 smmu0_int16_en5;
+	ZXIC_UINT32 smmu0_int16_en4;
+	ZXIC_UINT32 smmu0_int16_en3;
+	ZXIC_UINT32 smmu0_int16_en2;
+	ZXIC_UINT32 smmu0_int16_en1;
+	ZXIC_UINT32 smmu0_int16_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT16_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int16_mask_t {
+	ZXIC_UINT32 smmu0_int16_mask31;
+	ZXIC_UINT32 smmu0_int16_mask30;
+	ZXIC_UINT32 smmu0_int16_mask29;
+	ZXIC_UINT32 smmu0_int16_mask28;
+	ZXIC_UINT32 smmu0_int16_mask27;
+	ZXIC_UINT32 smmu0_int16_mask26;
+	ZXIC_UINT32 smmu0_int16_mask25;
+	ZXIC_UINT32 smmu0_int16_mask24;
+	ZXIC_UINT32 smmu0_int16_mask23;
+	ZXIC_UINT32 smmu0_int16_mask22;
+	ZXIC_UINT32 smmu0_int16_mask21;
+	ZXIC_UINT32 smmu0_int16_mask20;
+	ZXIC_UINT32 smmu0_int16_mask19;
+	ZXIC_UINT32 smmu0_int16_mask18;
+	ZXIC_UINT32 smmu0_int16_mask17;
+	ZXIC_UINT32 smmu0_int16_mask16;
+	ZXIC_UINT32 smmu0_int16_mask15;
+	ZXIC_UINT32 smmu0_int16_mask14;
+	ZXIC_UINT32 smmu0_int16_mask13;
+	ZXIC_UINT32 smmu0_int16_mask12;
+	ZXIC_UINT32 smmu0_int16_mask11;
+	ZXIC_UINT32 smmu0_int16_mask10;
+	ZXIC_UINT32 smmu0_int16_mask9;
+	ZXIC_UINT32 smmu0_int16_mask8;
+	ZXIC_UINT32 smmu0_int16_mask7;
+	ZXIC_UINT32 smmu0_int16_mask6;
+	ZXIC_UINT32 smmu0_int16_mask5;
+	ZXIC_UINT32 smmu0_int16_mask4;
+	ZXIC_UINT32 smmu0_int16_mask3;
+	ZXIC_UINT32 smmu0_int16_mask2;
+	ZXIC_UINT32 smmu0_int16_mask1;
+	ZXIC_UINT32 smmu0_int16_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT16_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int16_status_t {
+	ZXIC_UINT32 smmu0_int16_status31;
+	ZXIC_UINT32 smmu0_int16_status30;
+	ZXIC_UINT32 smmu0_int16_status29;
+	ZXIC_UINT32 smmu0_int16_status28;
+	ZXIC_UINT32 smmu0_int16_status27;
+	ZXIC_UINT32 smmu0_int16_status26;
+	ZXIC_UINT32 smmu0_int16_status25;
+	ZXIC_UINT32 smmu0_int16_status24;
+	ZXIC_UINT32 smmu0_int16_status23;
+	ZXIC_UINT32 smmu0_int16_status22;
+	ZXIC_UINT32 smmu0_int16_status21;
+	ZXIC_UINT32 smmu0_int16_status20;
+	ZXIC_UINT32 smmu0_int16_status19;
+	ZXIC_UINT32 smmu0_int16_status18;
+	ZXIC_UINT32 smmu0_int16_status17;
+	ZXIC_UINT32 smmu0_int16_status16;
+	ZXIC_UINT32 smmu0_int16_status15;
+	ZXIC_UINT32 smmu0_int16_status14;
+	ZXIC_UINT32 smmu0_int16_status13;
+	ZXIC_UINT32 smmu0_int16_status12;
+	ZXIC_UINT32 smmu0_int16_status11;
+	ZXIC_UINT32 smmu0_int16_status10;
+	ZXIC_UINT32 smmu0_int16_status9;
+	ZXIC_UINT32 smmu0_int16_status8;
+	ZXIC_UINT32 smmu0_int16_status7;
+	ZXIC_UINT32 smmu0_int16_status6;
+	ZXIC_UINT32 smmu0_int16_status5;
+	ZXIC_UINT32 smmu0_int16_status4;
+	ZXIC_UINT32 smmu0_int16_status3;
+	ZXIC_UINT32 smmu0_int16_status2;
+	ZXIC_UINT32 smmu0_int16_status1;
+	ZXIC_UINT32 smmu0_int16_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT16_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int17_en_t {
+	ZXIC_UINT32 smmu0_int17_en31;
+	ZXIC_UINT32 smmu0_int17_en30;
+	ZXIC_UINT32 smmu0_int17_en29;
+	ZXIC_UINT32 smmu0_int17_en28;
+	ZXIC_UINT32 smmu0_int17_en27;
+	ZXIC_UINT32 smmu0_int17_en26;
+	ZXIC_UINT32 smmu0_int17_en25;
+	ZXIC_UINT32 smmu0_int17_en24;
+	ZXIC_UINT32 smmu0_int17_en23;
+	ZXIC_UINT32 smmu0_int17_en22;
+	ZXIC_UINT32 smmu0_int17_en21;
+	ZXIC_UINT32 smmu0_int17_en20;
+	ZXIC_UINT32 smmu0_int17_en19;
+	ZXIC_UINT32 smmu0_int17_en18;
+	ZXIC_UINT32 smmu0_int17_en17;
+	ZXIC_UINT32 smmu0_int17_en16;
+	ZXIC_UINT32 smmu0_int17_en15;
+	ZXIC_UINT32 smmu0_int17_en14;
+	ZXIC_UINT32 smmu0_int17_en13;
+	ZXIC_UINT32 smmu0_int17_en12;
+	ZXIC_UINT32 smmu0_int17_en11;
+	ZXIC_UINT32 smmu0_int17_en10;
+	ZXIC_UINT32 smmu0_int17_en9;
+	ZXIC_UINT32 smmu0_int17_en8;
+	ZXIC_UINT32 smmu0_int17_en7;
+	ZXIC_UINT32 smmu0_int17_en6;
+	ZXIC_UINT32 smmu0_int17_en5;
+	ZXIC_UINT32 smmu0_int17_en4;
+	ZXIC_UINT32 smmu0_int17_en3;
+	ZXIC_UINT32 smmu0_int17_en2;
+	ZXIC_UINT32 smmu0_int17_en1;
+	ZXIC_UINT32 smmu0_int17_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT17_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int17_mask_t {
+	ZXIC_UINT32 smmu0_int17_mask31;
+	ZXIC_UINT32 smmu0_int17_mask30;
+	ZXIC_UINT32 smmu0_int17_mask29;
+	ZXIC_UINT32 smmu0_int17_mask28;
+	ZXIC_UINT32 smmu0_int17_mask27;
+	ZXIC_UINT32 smmu0_int17_mask26;
+	ZXIC_UINT32 smmu0_int17_mask25;
+	ZXIC_UINT32 smmu0_int17_mask24;
+	ZXIC_UINT32 smmu0_int17_mask23;
+	ZXIC_UINT32 smmu0_int17_mask22;
+	ZXIC_UINT32 smmu0_int17_mask21;
+	ZXIC_UINT32 smmu0_int17_mask20;
+	ZXIC_UINT32 smmu0_int17_mask19;
+	ZXIC_UINT32 smmu0_int17_mask18;
+	ZXIC_UINT32 smmu0_int17_mask17;
+	ZXIC_UINT32 smmu0_int17_mask16;
+	ZXIC_UINT32 smmu0_int17_mask15;
+	ZXIC_UINT32 smmu0_int17_mask14;
+	ZXIC_UINT32 smmu0_int17_mask13;
+	ZXIC_UINT32 smmu0_int17_mask12;
+	ZXIC_UINT32 smmu0_int17_mask11;
+	ZXIC_UINT32 smmu0_int17_mask10;
+	ZXIC_UINT32 smmu0_int17_mask9;
+	ZXIC_UINT32 smmu0_int17_mask8;
+	ZXIC_UINT32 smmu0_int17_mask7;
+	ZXIC_UINT32 smmu0_int17_mask6;
+	ZXIC_UINT32 smmu0_int17_mask5;
+	ZXIC_UINT32 smmu0_int17_mask4;
+	ZXIC_UINT32 smmu0_int17_mask3;
+	ZXIC_UINT32 smmu0_int17_mask2;
+	ZXIC_UINT32 smmu0_int17_mask1;
+	ZXIC_UINT32 smmu0_int17_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT17_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int17_status_t {
+	ZXIC_UINT32 smmu0_int17_status31;
+	ZXIC_UINT32 smmu0_int17_status30;
+	ZXIC_UINT32 smmu0_int17_status29;
+	ZXIC_UINT32 smmu0_int17_status28;
+	ZXIC_UINT32 smmu0_int17_status27;
+	ZXIC_UINT32 smmu0_int17_status26;
+	ZXIC_UINT32 smmu0_int17_status25;
+	ZXIC_UINT32 smmu0_int17_status24;
+	ZXIC_UINT32 smmu0_int17_status23;
+	ZXIC_UINT32 smmu0_int17_status22;
+	ZXIC_UINT32 smmu0_int17_status21;
+	ZXIC_UINT32 smmu0_int17_status20;
+	ZXIC_UINT32 smmu0_int17_status19;
+	ZXIC_UINT32 smmu0_int17_status18;
+	ZXIC_UINT32 smmu0_int17_status17;
+	ZXIC_UINT32 smmu0_int17_status16;
+	ZXIC_UINT32 smmu0_int17_status15;
+	ZXIC_UINT32 smmu0_int17_status14;
+	ZXIC_UINT32 smmu0_int17_status13;
+	ZXIC_UINT32 smmu0_int17_status12;
+	ZXIC_UINT32 smmu0_int17_status11;
+	ZXIC_UINT32 smmu0_int17_status10;
+	ZXIC_UINT32 smmu0_int17_status9;
+	ZXIC_UINT32 smmu0_int17_status8;
+	ZXIC_UINT32 smmu0_int17_status7;
+	ZXIC_UINT32 smmu0_int17_status6;
+	ZXIC_UINT32 smmu0_int17_status5;
+	ZXIC_UINT32 smmu0_int17_status4;
+	ZXIC_UINT32 smmu0_int17_status3;
+	ZXIC_UINT32 smmu0_int17_status2;
+	ZXIC_UINT32 smmu0_int17_status1;
+	ZXIC_UINT32 smmu0_int17_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT17_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int18_en_t {
+	ZXIC_UINT32 smmu0_int18_en31;
+	ZXIC_UINT32 smmu0_int18_en30;
+	ZXIC_UINT32 smmu0_int18_en29;
+	ZXIC_UINT32 smmu0_int18_en28;
+	ZXIC_UINT32 smmu0_int18_en27;
+	ZXIC_UINT32 smmu0_int18_en26;
+	ZXIC_UINT32 smmu0_int18_en25;
+	ZXIC_UINT32 smmu0_int18_en24;
+	ZXIC_UINT32 smmu0_int18_en23;
+	ZXIC_UINT32 smmu0_int18_en22;
+	ZXIC_UINT32 smmu0_int18_en21;
+	ZXIC_UINT32 smmu0_int18_en20;
+	ZXIC_UINT32 smmu0_int18_en19;
+	ZXIC_UINT32 smmu0_int18_en18;
+	ZXIC_UINT32 smmu0_int18_en17;
+	ZXIC_UINT32 smmu0_int18_en16;
+	ZXIC_UINT32 smmu0_int18_en15;
+	ZXIC_UINT32 smmu0_int18_en14;
+	ZXIC_UINT32 smmu0_int18_en13;
+	ZXIC_UINT32 smmu0_int18_en12;
+	ZXIC_UINT32 smmu0_int18_en11;
+	ZXIC_UINT32 smmu0_int18_en10;
+	ZXIC_UINT32 smmu0_int18_en9;
+	ZXIC_UINT32 smmu0_int18_en8;
+	ZXIC_UINT32 smmu0_int18_en7;
+	ZXIC_UINT32 smmu0_int18_en6;
+	ZXIC_UINT32 smmu0_int18_en5;
+	ZXIC_UINT32 smmu0_int18_en4;
+	ZXIC_UINT32 smmu0_int18_en3;
+	ZXIC_UINT32 smmu0_int18_en2;
+	ZXIC_UINT32 smmu0_int18_en1;
+	ZXIC_UINT32 smmu0_int18_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT18_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int18_mask_t {
+	ZXIC_UINT32 smmu0_int18_mask31;
+	ZXIC_UINT32 smmu0_int18_mask30;
+	ZXIC_UINT32 smmu0_int18_mask29;
+	ZXIC_UINT32 smmu0_int18_mask28;
+	ZXIC_UINT32 smmu0_int18_mask27;
+	ZXIC_UINT32 smmu0_int18_mask26;
+	ZXIC_UINT32 smmu0_int18_mask25;
+	ZXIC_UINT32 smmu0_int18_mask24;
+	ZXIC_UINT32 smmu0_int18_mask23;
+	ZXIC_UINT32 smmu0_int18_mask22;
+	ZXIC_UINT32 smmu0_int18_mask21;
+	ZXIC_UINT32 smmu0_int18_mask20;
+	ZXIC_UINT32 smmu0_int18_mask19;
+	ZXIC_UINT32 smmu0_int18_mask18;
+	ZXIC_UINT32 smmu0_int18_mask17;
+	ZXIC_UINT32 smmu0_int18_mask16;
+	ZXIC_UINT32 smmu0_int18_mask15;
+	ZXIC_UINT32 smmu0_int18_mask14;
+	ZXIC_UINT32 smmu0_int18_mask13;
+	ZXIC_UINT32 smmu0_int18_mask12;
+	ZXIC_UINT32 smmu0_int18_mask11;
+	ZXIC_UINT32 smmu0_int18_mask10;
+	ZXIC_UINT32 smmu0_int18_mask9;
+	ZXIC_UINT32 smmu0_int18_mask8;
+	ZXIC_UINT32 smmu0_int18_mask7;
+	ZXIC_UINT32 smmu0_int18_mask6;
+	ZXIC_UINT32 smmu0_int18_mask5;
+	ZXIC_UINT32 smmu0_int18_mask4;
+	ZXIC_UINT32 smmu0_int18_mask3;
+	ZXIC_UINT32 smmu0_int18_mask2;
+	ZXIC_UINT32 smmu0_int18_mask1;
+	ZXIC_UINT32 smmu0_int18_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT18_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int18_status_t {
+	ZXIC_UINT32 smmu0_int18_status31;
+	ZXIC_UINT32 smmu0_int18_status30;
+	ZXIC_UINT32 smmu0_int18_status29;
+	ZXIC_UINT32 smmu0_int18_status28;
+	ZXIC_UINT32 smmu0_int18_status27;
+	ZXIC_UINT32 smmu0_int18_status26;
+	ZXIC_UINT32 smmu0_int18_status25;
+	ZXIC_UINT32 smmu0_int18_status24;
+	ZXIC_UINT32 smmu0_int18_status23;
+	ZXIC_UINT32 smmu0_int18_status22;
+	ZXIC_UINT32 smmu0_int18_status21;
+	ZXIC_UINT32 smmu0_int18_status20;
+	ZXIC_UINT32 smmu0_int18_status19;
+	ZXIC_UINT32 smmu0_int18_status18;
+	ZXIC_UINT32 smmu0_int18_status17;
+	ZXIC_UINT32 smmu0_int18_status16;
+	ZXIC_UINT32 smmu0_int18_status15;
+	ZXIC_UINT32 smmu0_int18_status14;
+	ZXIC_UINT32 smmu0_int18_status13;
+	ZXIC_UINT32 smmu0_int18_status12;
+	ZXIC_UINT32 smmu0_int18_status11;
+	ZXIC_UINT32 smmu0_int18_status10;
+	ZXIC_UINT32 smmu0_int18_status9;
+	ZXIC_UINT32 smmu0_int18_status8;
+	ZXIC_UINT32 smmu0_int18_status7;
+	ZXIC_UINT32 smmu0_int18_status6;
+	ZXIC_UINT32 smmu0_int18_status5;
+	ZXIC_UINT32 smmu0_int18_status4;
+	ZXIC_UINT32 smmu0_int18_status3;
+	ZXIC_UINT32 smmu0_int18_status2;
+	ZXIC_UINT32 smmu0_int18_status1;
+	ZXIC_UINT32 smmu0_int18_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT18_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int19_en_t {
+	ZXIC_UINT32 smmu0_int19_en31;
+	ZXIC_UINT32 smmu0_int19_en30;
+	ZXIC_UINT32 smmu0_int19_en29;
+	ZXIC_UINT32 smmu0_int19_en28;
+	ZXIC_UINT32 smmu0_int19_en27;
+	ZXIC_UINT32 smmu0_int19_en26;
+	ZXIC_UINT32 smmu0_int19_en25;
+	ZXIC_UINT32 smmu0_int19_en24;
+	ZXIC_UINT32 smmu0_int19_en23;
+	ZXIC_UINT32 smmu0_int19_en22;
+	ZXIC_UINT32 smmu0_int19_en21;
+	ZXIC_UINT32 smmu0_int19_en20;
+	ZXIC_UINT32 smmu0_int19_en19;
+	ZXIC_UINT32 smmu0_int19_en18;
+	ZXIC_UINT32 smmu0_int19_en17;
+	ZXIC_UINT32 smmu0_int19_en16;
+	ZXIC_UINT32 smmu0_int19_en15;
+	ZXIC_UINT32 smmu0_int19_en14;
+	ZXIC_UINT32 smmu0_int19_en13;
+	ZXIC_UINT32 smmu0_int19_en12;
+	ZXIC_UINT32 smmu0_int19_en11;
+	ZXIC_UINT32 smmu0_int19_en10;
+	ZXIC_UINT32 smmu0_int19_en9;
+	ZXIC_UINT32 smmu0_int19_en8;
+	ZXIC_UINT32 smmu0_int19_en7;
+	ZXIC_UINT32 smmu0_int19_en6;
+	ZXIC_UINT32 smmu0_int19_en5;
+	ZXIC_UINT32 smmu0_int19_en4;
+	ZXIC_UINT32 smmu0_int19_en3;
+	ZXIC_UINT32 smmu0_int19_en2;
+	ZXIC_UINT32 smmu0_int19_en1;
+	ZXIC_UINT32 smmu0_int19_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT19_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int19_mask_t {
+	ZXIC_UINT32 smmu0_int19_mask31;
+	ZXIC_UINT32 smmu0_int19_mask30;
+	ZXIC_UINT32 smmu0_int19_mask29;
+	ZXIC_UINT32 smmu0_int19_mask28;
+	ZXIC_UINT32 smmu0_int19_mask27;
+	ZXIC_UINT32 smmu0_int19_mask26;
+	ZXIC_UINT32 smmu0_int19_mask25;
+	ZXIC_UINT32 smmu0_int19_mask24;
+	ZXIC_UINT32 smmu0_int19_mask23;
+	ZXIC_UINT32 smmu0_int19_mask22;
+	ZXIC_UINT32 smmu0_int19_mask21;
+	ZXIC_UINT32 smmu0_int19_mask20;
+	ZXIC_UINT32 smmu0_int19_mask19;
+	ZXIC_UINT32 smmu0_int19_mask18;
+	ZXIC_UINT32 smmu0_int19_mask17;
+	ZXIC_UINT32 smmu0_int19_mask16;
+	ZXIC_UINT32 smmu0_int19_mask15;
+	ZXIC_UINT32 smmu0_int19_mask14;
+	ZXIC_UINT32 smmu0_int19_mask13;
+	ZXIC_UINT32 smmu0_int19_mask12;
+	ZXIC_UINT32 smmu0_int19_mask11;
+	ZXIC_UINT32 smmu0_int19_mask10;
+	ZXIC_UINT32 smmu0_int19_mask9;
+	ZXIC_UINT32 smmu0_int19_mask8;
+	ZXIC_UINT32 smmu0_int19_mask7;
+	ZXIC_UINT32 smmu0_int19_mask6;
+	ZXIC_UINT32 smmu0_int19_mask5;
+	ZXIC_UINT32 smmu0_int19_mask4;
+	ZXIC_UINT32 smmu0_int19_mask3;
+	ZXIC_UINT32 smmu0_int19_mask2;
+	ZXIC_UINT32 smmu0_int19_mask1;
+	ZXIC_UINT32 smmu0_int19_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT19_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int19_status_t {
+	ZXIC_UINT32 smmu0_int19_status31;
+	ZXIC_UINT32 smmu0_int19_status30;
+	ZXIC_UINT32 smmu0_int19_status29;
+	ZXIC_UINT32 smmu0_int19_status28;
+	ZXIC_UINT32 smmu0_int19_status27;
+	ZXIC_UINT32 smmu0_int19_status26;
+	ZXIC_UINT32 smmu0_int19_status25;
+	ZXIC_UINT32 smmu0_int19_status24;
+	ZXIC_UINT32 smmu0_int19_status23;
+	ZXIC_UINT32 smmu0_int19_status22;
+	ZXIC_UINT32 smmu0_int19_status21;
+	ZXIC_UINT32 smmu0_int19_status20;
+	ZXIC_UINT32 smmu0_int19_status19;
+	ZXIC_UINT32 smmu0_int19_status18;
+	ZXIC_UINT32 smmu0_int19_status17;
+	ZXIC_UINT32 smmu0_int19_status16;
+	ZXIC_UINT32 smmu0_int19_status15;
+	ZXIC_UINT32 smmu0_int19_status14;
+	ZXIC_UINT32 smmu0_int19_status13;
+	ZXIC_UINT32 smmu0_int19_status12;
+	ZXIC_UINT32 smmu0_int19_status11;
+	ZXIC_UINT32 smmu0_int19_status10;
+	ZXIC_UINT32 smmu0_int19_status9;
+	ZXIC_UINT32 smmu0_int19_status8;
+	ZXIC_UINT32 smmu0_int19_status7;
+	ZXIC_UINT32 smmu0_int19_status6;
+	ZXIC_UINT32 smmu0_int19_status5;
+	ZXIC_UINT32 smmu0_int19_status4;
+	ZXIC_UINT32 smmu0_int19_status3;
+	ZXIC_UINT32 smmu0_int19_status2;
+	ZXIC_UINT32 smmu0_int19_status1;
+	ZXIC_UINT32 smmu0_int19_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT19_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int20_en_t {
+	ZXIC_UINT32 smmu0_int20_en31;
+	ZXIC_UINT32 smmu0_int20_en30;
+	ZXIC_UINT32 smmu0_int20_en29;
+	ZXIC_UINT32 smmu0_int20_en28;
+	ZXIC_UINT32 smmu0_int20_en27;
+	ZXIC_UINT32 smmu0_int20_en26;
+	ZXIC_UINT32 smmu0_int20_en25;
+	ZXIC_UINT32 smmu0_int20_en24;
+	ZXIC_UINT32 smmu0_int20_en23;
+	ZXIC_UINT32 smmu0_int20_en22;
+	ZXIC_UINT32 smmu0_int20_en21;
+	ZXIC_UINT32 smmu0_int20_en20;
+	ZXIC_UINT32 smmu0_int20_en19;
+	ZXIC_UINT32 smmu0_int20_en18;
+	ZXIC_UINT32 smmu0_int20_en17;
+	ZXIC_UINT32 smmu0_int20_en16;
+	ZXIC_UINT32 smmu0_int20_en15;
+	ZXIC_UINT32 smmu0_int20_en14;
+	ZXIC_UINT32 smmu0_int20_en13;
+	ZXIC_UINT32 smmu0_int20_en12;
+	ZXIC_UINT32 smmu0_int20_en11;
+	ZXIC_UINT32 smmu0_int20_en10;
+	ZXIC_UINT32 smmu0_int20_en9;
+	ZXIC_UINT32 smmu0_int20_en8;
+	ZXIC_UINT32 smmu0_int20_en7;
+	ZXIC_UINT32 smmu0_int20_en6;
+	ZXIC_UINT32 smmu0_int20_en5;
+	ZXIC_UINT32 smmu0_int20_en4;
+	ZXIC_UINT32 smmu0_int20_en3;
+	ZXIC_UINT32 smmu0_int20_en2;
+	ZXIC_UINT32 smmu0_int20_en1;
+	ZXIC_UINT32 smmu0_int20_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT20_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int20_mask_t {
+	ZXIC_UINT32 smmu0_int20_mask31;
+	ZXIC_UINT32 smmu0_int20_mask30;
+	ZXIC_UINT32 smmu0_int20_mask29;
+	ZXIC_UINT32 smmu0_int20_mask28;
+	ZXIC_UINT32 smmu0_int20_mask27;
+	ZXIC_UINT32 smmu0_int20_mask26;
+	ZXIC_UINT32 smmu0_int20_mask25;
+	ZXIC_UINT32 smmu0_int20_mask24;
+	ZXIC_UINT32 smmu0_int20_mask23;
+	ZXIC_UINT32 smmu0_int20_mask22;
+	ZXIC_UINT32 smmu0_int20_mask21;
+	ZXIC_UINT32 smmu0_int20_mask20;
+	ZXIC_UINT32 smmu0_int20_mask19;
+	ZXIC_UINT32 smmu0_int20_mask18;
+	ZXIC_UINT32 smmu0_int20_mask17;
+	ZXIC_UINT32 smmu0_int20_mask16;
+	ZXIC_UINT32 smmu0_int20_mask15;
+	ZXIC_UINT32 smmu0_int20_mask14;
+	ZXIC_UINT32 smmu0_int20_mask13;
+	ZXIC_UINT32 smmu0_int20_mask12;
+	ZXIC_UINT32 smmu0_int20_mask11;
+	ZXIC_UINT32 smmu0_int20_mask10;
+	ZXIC_UINT32 smmu0_int20_mask9;
+	ZXIC_UINT32 smmu0_int20_mask8;
+	ZXIC_UINT32 smmu0_int20_mask7;
+	ZXIC_UINT32 smmu0_int20_mask6;
+	ZXIC_UINT32 smmu0_int20_mask5;
+	ZXIC_UINT32 smmu0_int20_mask4;
+	ZXIC_UINT32 smmu0_int20_mask3;
+	ZXIC_UINT32 smmu0_int20_mask2;
+	ZXIC_UINT32 smmu0_int20_mask1;
+	ZXIC_UINT32 smmu0_int20_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT20_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int20_status_t {
+	ZXIC_UINT32 smmu0_int20_status31;
+	ZXIC_UINT32 smmu0_int20_status30;
+	ZXIC_UINT32 smmu0_int20_status29;
+	ZXIC_UINT32 smmu0_int20_status28;
+	ZXIC_UINT32 smmu0_int20_status27;
+	ZXIC_UINT32 smmu0_int20_status26;
+	ZXIC_UINT32 smmu0_int20_status25;
+	ZXIC_UINT32 smmu0_int20_status24;
+	ZXIC_UINT32 smmu0_int20_status23;
+	ZXIC_UINT32 smmu0_int20_status22;
+	ZXIC_UINT32 smmu0_int20_status21;
+	ZXIC_UINT32 smmu0_int20_status20;
+	ZXIC_UINT32 smmu0_int20_status19;
+	ZXIC_UINT32 smmu0_int20_status18;
+	ZXIC_UINT32 smmu0_int20_status17;
+	ZXIC_UINT32 smmu0_int20_status16;
+	ZXIC_UINT32 smmu0_int20_status15;
+	ZXIC_UINT32 smmu0_int20_status14;
+	ZXIC_UINT32 smmu0_int20_status13;
+	ZXIC_UINT32 smmu0_int20_status12;
+	ZXIC_UINT32 smmu0_int20_status11;
+	ZXIC_UINT32 smmu0_int20_status10;
+	ZXIC_UINT32 smmu0_int20_status9;
+	ZXIC_UINT32 smmu0_int20_status8;
+	ZXIC_UINT32 smmu0_int20_status7;
+	ZXIC_UINT32 smmu0_int20_status6;
+	ZXIC_UINT32 smmu0_int20_status5;
+	ZXIC_UINT32 smmu0_int20_status4;
+	ZXIC_UINT32 smmu0_int20_status3;
+	ZXIC_UINT32 smmu0_int20_status2;
+	ZXIC_UINT32 smmu0_int20_status1;
+	ZXIC_UINT32 smmu0_int20_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT20_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int21_en_t {
+	ZXIC_UINT32 smmu0_int21_en31;
+	ZXIC_UINT32 smmu0_int21_en30;
+	ZXIC_UINT32 smmu0_int21_en29;
+	ZXIC_UINT32 smmu0_int21_en28;
+	ZXIC_UINT32 smmu0_int21_en27;
+	ZXIC_UINT32 smmu0_int21_en26;
+	ZXIC_UINT32 smmu0_int21_en25;
+	ZXIC_UINT32 smmu0_int21_en24;
+	ZXIC_UINT32 smmu0_int21_en23;
+	ZXIC_UINT32 smmu0_int21_en22;
+	ZXIC_UINT32 smmu0_int21_en21;
+	ZXIC_UINT32 smmu0_int21_en20;
+	ZXIC_UINT32 smmu0_int21_en19;
+	ZXIC_UINT32 smmu0_int21_en18;
+	ZXIC_UINT32 smmu0_int21_en17;
+	ZXIC_UINT32 smmu0_int21_en16;
+	ZXIC_UINT32 smmu0_int21_en15;
+	ZXIC_UINT32 smmu0_int21_en14;
+	ZXIC_UINT32 smmu0_int21_en13;
+	ZXIC_UINT32 smmu0_int21_en12;
+	ZXIC_UINT32 smmu0_int21_en11;
+	ZXIC_UINT32 smmu0_int21_en10;
+	ZXIC_UINT32 smmu0_int21_en9;
+	ZXIC_UINT32 smmu0_int21_en8;
+	ZXIC_UINT32 smmu0_int21_en7;
+	ZXIC_UINT32 smmu0_int21_en6;
+	ZXIC_UINT32 smmu0_int21_en5;
+	ZXIC_UINT32 smmu0_int21_en4;
+	ZXIC_UINT32 smmu0_int21_en3;
+	ZXIC_UINT32 smmu0_int21_en2;
+	ZXIC_UINT32 smmu0_int21_en1;
+	ZXIC_UINT32 smmu0_int21_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT21_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int21_mask_t {
+	ZXIC_UINT32 smmu0_int21_mask31;
+	ZXIC_UINT32 smmu0_int21_mask30;
+	ZXIC_UINT32 smmu0_int21_mask29;
+	ZXIC_UINT32 smmu0_int21_mask28;
+	ZXIC_UINT32 smmu0_int21_mask27;
+	ZXIC_UINT32 smmu0_int21_mask26;
+	ZXIC_UINT32 smmu0_int21_mask25;
+	ZXIC_UINT32 smmu0_int21_mask24;
+	ZXIC_UINT32 smmu0_int21_mask23;
+	ZXIC_UINT32 smmu0_int21_mask22;
+	ZXIC_UINT32 smmu0_int21_mask21;
+	ZXIC_UINT32 smmu0_int21_mask20;
+	ZXIC_UINT32 smmu0_int21_mask19;
+	ZXIC_UINT32 smmu0_int21_mask18;
+	ZXIC_UINT32 smmu0_int21_mask17;
+	ZXIC_UINT32 smmu0_int21_mask16;
+	ZXIC_UINT32 smmu0_int21_mask15;
+	ZXIC_UINT32 smmu0_int21_mask14;
+	ZXIC_UINT32 smmu0_int21_mask13;
+	ZXIC_UINT32 smmu0_int21_mask12;
+	ZXIC_UINT32 smmu0_int21_mask11;
+	ZXIC_UINT32 smmu0_int21_mask10;
+	ZXIC_UINT32 smmu0_int21_mask9;
+	ZXIC_UINT32 smmu0_int21_mask8;
+	ZXIC_UINT32 smmu0_int21_mask7;
+	ZXIC_UINT32 smmu0_int21_mask6;
+	ZXIC_UINT32 smmu0_int21_mask5;
+	ZXIC_UINT32 smmu0_int21_mask4;
+	ZXIC_UINT32 smmu0_int21_mask3;
+	ZXIC_UINT32 smmu0_int21_mask2;
+	ZXIC_UINT32 smmu0_int21_mask1;
+	ZXIC_UINT32 smmu0_int21_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT21_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int21_status_t {
+	ZXIC_UINT32 smmu0_int21_status31;
+	ZXIC_UINT32 smmu0_int21_status30;
+	ZXIC_UINT32 smmu0_int21_status29;
+	ZXIC_UINT32 smmu0_int21_status28;
+	ZXIC_UINT32 smmu0_int21_status27;
+	ZXIC_UINT32 smmu0_int21_status26;
+	ZXIC_UINT32 smmu0_int21_status25;
+	ZXIC_UINT32 smmu0_int21_status24;
+	ZXIC_UINT32 smmu0_int21_status23;
+	ZXIC_UINT32 smmu0_int21_status22;
+	ZXIC_UINT32 smmu0_int21_status21;
+	ZXIC_UINT32 smmu0_int21_status20;
+	ZXIC_UINT32 smmu0_int21_status19;
+	ZXIC_UINT32 smmu0_int21_status18;
+	ZXIC_UINT32 smmu0_int21_status17;
+	ZXIC_UINT32 smmu0_int21_status16;
+	ZXIC_UINT32 smmu0_int21_status15;
+	ZXIC_UINT32 smmu0_int21_status14;
+	ZXIC_UINT32 smmu0_int21_status13;
+	ZXIC_UINT32 smmu0_int21_status12;
+	ZXIC_UINT32 smmu0_int21_status11;
+	ZXIC_UINT32 smmu0_int21_status10;
+	ZXIC_UINT32 smmu0_int21_status9;
+	ZXIC_UINT32 smmu0_int21_status8;
+	ZXIC_UINT32 smmu0_int21_status7;
+	ZXIC_UINT32 smmu0_int21_status6;
+	ZXIC_UINT32 smmu0_int21_status5;
+	ZXIC_UINT32 smmu0_int21_status4;
+	ZXIC_UINT32 smmu0_int21_status3;
+	ZXIC_UINT32 smmu0_int21_status2;
+	ZXIC_UINT32 smmu0_int21_status1;
+	ZXIC_UINT32 smmu0_int21_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT21_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int22_en_t {
+	ZXIC_UINT32 smmu0_int22_en31;
+	ZXIC_UINT32 smmu0_int22_en30;
+	ZXIC_UINT32 smmu0_int22_en29;
+	ZXIC_UINT32 smmu0_int22_en28;
+	ZXIC_UINT32 smmu0_int22_en27;
+	ZXIC_UINT32 smmu0_int22_en26;
+	ZXIC_UINT32 smmu0_int22_en25;
+	ZXIC_UINT32 smmu0_int22_en24;
+	ZXIC_UINT32 smmu0_int22_en23;
+	ZXIC_UINT32 smmu0_int22_en22;
+	ZXIC_UINT32 smmu0_int22_en21;
+	ZXIC_UINT32 smmu0_int22_en20;
+	ZXIC_UINT32 smmu0_int22_en19;
+	ZXIC_UINT32 smmu0_int22_en18;
+	ZXIC_UINT32 smmu0_int22_en17;
+	ZXIC_UINT32 smmu0_int22_en16;
+	ZXIC_UINT32 smmu0_int22_en15;
+	ZXIC_UINT32 smmu0_int22_en14;
+	ZXIC_UINT32 smmu0_int22_en13;
+	ZXIC_UINT32 smmu0_int22_en12;
+	ZXIC_UINT32 smmu0_int22_en11;
+	ZXIC_UINT32 smmu0_int22_en10;
+	ZXIC_UINT32 smmu0_int22_en9;
+	ZXIC_UINT32 smmu0_int22_en8;
+	ZXIC_UINT32 smmu0_int22_en7;
+	ZXIC_UINT32 smmu0_int22_en6;
+	ZXIC_UINT32 smmu0_int22_en5;
+	ZXIC_UINT32 smmu0_int22_en4;
+	ZXIC_UINT32 smmu0_int22_en3;
+	ZXIC_UINT32 smmu0_int22_en2;
+	ZXIC_UINT32 smmu0_int22_en1;
+	ZXIC_UINT32 smmu0_int22_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT22_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int22_mask_t {
+	ZXIC_UINT32 smmu0_int22_mask31;
+	ZXIC_UINT32 smmu0_int22_mask30;
+	ZXIC_UINT32 smmu0_int22_mask29;
+	ZXIC_UINT32 smmu0_int22_mask28;
+	ZXIC_UINT32 smmu0_int22_mask27;
+	ZXIC_UINT32 smmu0_int22_mask26;
+	ZXIC_UINT32 smmu0_int22_mask25;
+	ZXIC_UINT32 smmu0_int22_mask24;
+	ZXIC_UINT32 smmu0_int22_mask23;
+	ZXIC_UINT32 smmu0_int22_mask22;
+	ZXIC_UINT32 smmu0_int22_mask21;
+	ZXIC_UINT32 smmu0_int22_mask20;
+	ZXIC_UINT32 smmu0_int22_mask19;
+	ZXIC_UINT32 smmu0_int22_mask18;
+	ZXIC_UINT32 smmu0_int22_mask17;
+	ZXIC_UINT32 smmu0_int22_mask16;
+	ZXIC_UINT32 smmu0_int22_mask15;
+	ZXIC_UINT32 smmu0_int22_mask14;
+	ZXIC_UINT32 smmu0_int22_mask13;
+	ZXIC_UINT32 smmu0_int22_mask12;
+	ZXIC_UINT32 smmu0_int22_mask11;
+	ZXIC_UINT32 smmu0_int22_mask10;
+	ZXIC_UINT32 smmu0_int22_mask9;
+	ZXIC_UINT32 smmu0_int22_mask8;
+	ZXIC_UINT32 smmu0_int22_mask7;
+	ZXIC_UINT32 smmu0_int22_mask6;
+	ZXIC_UINT32 smmu0_int22_mask5;
+	ZXIC_UINT32 smmu0_int22_mask4;
+	ZXIC_UINT32 smmu0_int22_mask3;
+	ZXIC_UINT32 smmu0_int22_mask2;
+	ZXIC_UINT32 smmu0_int22_mask1;
+	ZXIC_UINT32 smmu0_int22_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT22_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int22_status_t {
+	ZXIC_UINT32 smmu0_int22_status31;
+	ZXIC_UINT32 smmu0_int22_status30;
+	ZXIC_UINT32 smmu0_int22_status29;
+	ZXIC_UINT32 smmu0_int22_status28;
+	ZXIC_UINT32 smmu0_int22_status27;
+	ZXIC_UINT32 smmu0_int22_status26;
+	ZXIC_UINT32 smmu0_int22_status25;
+	ZXIC_UINT32 smmu0_int22_status24;
+	ZXIC_UINT32 smmu0_int22_status23;
+	ZXIC_UINT32 smmu0_int22_status22;
+	ZXIC_UINT32 smmu0_int22_status21;
+	ZXIC_UINT32 smmu0_int22_status20;
+	ZXIC_UINT32 smmu0_int22_status19;
+	ZXIC_UINT32 smmu0_int22_status18;
+	ZXIC_UINT32 smmu0_int22_status17;
+	ZXIC_UINT32 smmu0_int22_status16;
+	ZXIC_UINT32 smmu0_int22_status15;
+	ZXIC_UINT32 smmu0_int22_status14;
+	ZXIC_UINT32 smmu0_int22_status13;
+	ZXIC_UINT32 smmu0_int22_status12;
+	ZXIC_UINT32 smmu0_int22_status11;
+	ZXIC_UINT32 smmu0_int22_status10;
+	ZXIC_UINT32 smmu0_int22_status9;
+	ZXIC_UINT32 smmu0_int22_status8;
+	ZXIC_UINT32 smmu0_int22_status7;
+	ZXIC_UINT32 smmu0_int22_status6;
+	ZXIC_UINT32 smmu0_int22_status5;
+	ZXIC_UINT32 smmu0_int22_status4;
+	ZXIC_UINT32 smmu0_int22_status3;
+	ZXIC_UINT32 smmu0_int22_status2;
+	ZXIC_UINT32 smmu0_int22_status1;
+	ZXIC_UINT32 smmu0_int22_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT22_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int23_en_t {
+	ZXIC_UINT32 smmu0_int23_en31;
+	ZXIC_UINT32 smmu0_int23_en30;
+	ZXIC_UINT32 smmu0_int23_en29;
+	ZXIC_UINT32 smmu0_int23_en28;
+	ZXIC_UINT32 smmu0_int23_en27;
+	ZXIC_UINT32 smmu0_int23_en26;
+	ZXIC_UINT32 smmu0_int23_en25;
+	ZXIC_UINT32 smmu0_int23_en24;
+	ZXIC_UINT32 smmu0_int23_en23;
+	ZXIC_UINT32 smmu0_int23_en22;
+	ZXIC_UINT32 smmu0_int23_en21;
+	ZXIC_UINT32 smmu0_int23_en20;
+	ZXIC_UINT32 smmu0_int23_en19;
+	ZXIC_UINT32 smmu0_int23_en18;
+	ZXIC_UINT32 smmu0_int23_en17;
+	ZXIC_UINT32 smmu0_int23_en16;
+	ZXIC_UINT32 smmu0_int23_en15;
+	ZXIC_UINT32 smmu0_int23_en14;
+	ZXIC_UINT32 smmu0_int23_en13;
+	ZXIC_UINT32 smmu0_int23_en12;
+	ZXIC_UINT32 smmu0_int23_en11;
+	ZXIC_UINT32 smmu0_int23_en10;
+	ZXIC_UINT32 smmu0_int23_en9;
+	ZXIC_UINT32 smmu0_int23_en8;
+	ZXIC_UINT32 smmu0_int23_en7;
+	ZXIC_UINT32 smmu0_int23_en6;
+	ZXIC_UINT32 smmu0_int23_en5;
+	ZXIC_UINT32 smmu0_int23_en4;
+	ZXIC_UINT32 smmu0_int23_en3;
+	ZXIC_UINT32 smmu0_int23_en2;
+	ZXIC_UINT32 smmu0_int23_en1;
+	ZXIC_UINT32 smmu0_int23_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT23_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int23_mask_t {
+	ZXIC_UINT32 smmu0_int23_mask31;
+	ZXIC_UINT32 smmu0_int23_mask30;
+	ZXIC_UINT32 smmu0_int23_mask29;
+	ZXIC_UINT32 smmu0_int23_mask28;
+	ZXIC_UINT32 smmu0_int23_mask27;
+	ZXIC_UINT32 smmu0_int23_mask26;
+	ZXIC_UINT32 smmu0_int23_mask25;
+	ZXIC_UINT32 smmu0_int23_mask24;
+	ZXIC_UINT32 smmu0_int23_mask23;
+	ZXIC_UINT32 smmu0_int23_mask22;
+	ZXIC_UINT32 smmu0_int23_mask21;
+	ZXIC_UINT32 smmu0_int23_mask20;
+	ZXIC_UINT32 smmu0_int23_mask19;
+	ZXIC_UINT32 smmu0_int23_mask18;
+	ZXIC_UINT32 smmu0_int23_mask17;
+	ZXIC_UINT32 smmu0_int23_mask16;
+	ZXIC_UINT32 smmu0_int23_mask15;
+	ZXIC_UINT32 smmu0_int23_mask14;
+	ZXIC_UINT32 smmu0_int23_mask13;
+	ZXIC_UINT32 smmu0_int23_mask12;
+	ZXIC_UINT32 smmu0_int23_mask11;
+	ZXIC_UINT32 smmu0_int23_mask10;
+	ZXIC_UINT32 smmu0_int23_mask9;
+	ZXIC_UINT32 smmu0_int23_mask8;
+	ZXIC_UINT32 smmu0_int23_mask7;
+	ZXIC_UINT32 smmu0_int23_mask6;
+	ZXIC_UINT32 smmu0_int23_mask5;
+	ZXIC_UINT32 smmu0_int23_mask4;
+	ZXIC_UINT32 smmu0_int23_mask3;
+	ZXIC_UINT32 smmu0_int23_mask2;
+	ZXIC_UINT32 smmu0_int23_mask1;
+	ZXIC_UINT32 smmu0_int23_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT23_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int23_status_t {
+	ZXIC_UINT32 smmu0_int23_status31;
+	ZXIC_UINT32 smmu0_int23_status30;
+	ZXIC_UINT32 smmu0_int23_status29;
+	ZXIC_UINT32 smmu0_int23_status28;
+	ZXIC_UINT32 smmu0_int23_status27;
+	ZXIC_UINT32 smmu0_int23_status26;
+	ZXIC_UINT32 smmu0_int23_status25;
+	ZXIC_UINT32 smmu0_int23_status24;
+	ZXIC_UINT32 smmu0_int23_status23;
+	ZXIC_UINT32 smmu0_int23_status22;
+	ZXIC_UINT32 smmu0_int23_status21;
+	ZXIC_UINT32 smmu0_int23_status20;
+	ZXIC_UINT32 smmu0_int23_status19;
+	ZXIC_UINT32 smmu0_int23_status18;
+	ZXIC_UINT32 smmu0_int23_status17;
+	ZXIC_UINT32 smmu0_int23_status16;
+	ZXIC_UINT32 smmu0_int23_status15;
+	ZXIC_UINT32 smmu0_int23_status14;
+	ZXIC_UINT32 smmu0_int23_status13;
+	ZXIC_UINT32 smmu0_int23_status12;
+	ZXIC_UINT32 smmu0_int23_status11;
+	ZXIC_UINT32 smmu0_int23_status10;
+	ZXIC_UINT32 smmu0_int23_status9;
+	ZXIC_UINT32 smmu0_int23_status8;
+	ZXIC_UINT32 smmu0_int23_status7;
+	ZXIC_UINT32 smmu0_int23_status6;
+	ZXIC_UINT32 smmu0_int23_status5;
+	ZXIC_UINT32 smmu0_int23_status4;
+	ZXIC_UINT32 smmu0_int23_status3;
+	ZXIC_UINT32 smmu0_int23_status2;
+	ZXIC_UINT32 smmu0_int23_status1;
+	ZXIC_UINT32 smmu0_int23_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT23_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int24_en_t {
+	ZXIC_UINT32 smmu0_int24_en31;
+	ZXIC_UINT32 smmu0_int24_en30;
+	ZXIC_UINT32 smmu0_int24_en29;
+	ZXIC_UINT32 smmu0_int24_en28;
+	ZXIC_UINT32 smmu0_int24_en27;
+	ZXIC_UINT32 smmu0_int24_en26;
+	ZXIC_UINT32 smmu0_int24_en25;
+	ZXIC_UINT32 smmu0_int24_en24;
+	ZXIC_UINT32 smmu0_int24_en23;
+	ZXIC_UINT32 smmu0_int24_en22;
+	ZXIC_UINT32 smmu0_int24_en21;
+	ZXIC_UINT32 smmu0_int24_en20;
+	ZXIC_UINT32 smmu0_int24_en19;
+	ZXIC_UINT32 smmu0_int24_en18;
+	ZXIC_UINT32 smmu0_int24_en17;
+	ZXIC_UINT32 smmu0_int24_en16;
+	ZXIC_UINT32 smmu0_int24_en15;
+	ZXIC_UINT32 smmu0_int24_en14;
+	ZXIC_UINT32 smmu0_int24_en13;
+	ZXIC_UINT32 smmu0_int24_en12;
+	ZXIC_UINT32 smmu0_int24_en11;
+	ZXIC_UINT32 smmu0_int24_en10;
+	ZXIC_UINT32 smmu0_int24_en9;
+	ZXIC_UINT32 smmu0_int24_en8;
+	ZXIC_UINT32 smmu0_int24_en7;
+	ZXIC_UINT32 smmu0_int24_en6;
+	ZXIC_UINT32 smmu0_int24_en5;
+	ZXIC_UINT32 smmu0_int24_en4;
+	ZXIC_UINT32 smmu0_int24_en3;
+	ZXIC_UINT32 smmu0_int24_en2;
+	ZXIC_UINT32 smmu0_int24_en1;
+	ZXIC_UINT32 smmu0_int24_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT24_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int24_mask_t {
+	ZXIC_UINT32 smmu0_int24_mask31;
+	ZXIC_UINT32 smmu0_int24_mask30;
+	ZXIC_UINT32 smmu0_int24_mask29;
+	ZXIC_UINT32 smmu0_int24_mask28;
+	ZXIC_UINT32 smmu0_int24_mask27;
+	ZXIC_UINT32 smmu0_int24_mask26;
+	ZXIC_UINT32 smmu0_int24_mask25;
+	ZXIC_UINT32 smmu0_int24_mask24;
+	ZXIC_UINT32 smmu0_int24_mask23;
+	ZXIC_UINT32 smmu0_int24_mask22;
+	ZXIC_UINT32 smmu0_int24_mask21;
+	ZXIC_UINT32 smmu0_int24_mask20;
+	ZXIC_UINT32 smmu0_int24_mask19;
+	ZXIC_UINT32 smmu0_int24_mask18;
+	ZXIC_UINT32 smmu0_int24_mask17;
+	ZXIC_UINT32 smmu0_int24_mask16;
+	ZXIC_UINT32 smmu0_int24_mask15;
+	ZXIC_UINT32 smmu0_int24_mask14;
+	ZXIC_UINT32 smmu0_int24_mask13;
+	ZXIC_UINT32 smmu0_int24_mask12;
+	ZXIC_UINT32 smmu0_int24_mask11;
+	ZXIC_UINT32 smmu0_int24_mask10;
+	ZXIC_UINT32 smmu0_int24_mask9;
+	ZXIC_UINT32 smmu0_int24_mask8;
+	ZXIC_UINT32 smmu0_int24_mask7;
+	ZXIC_UINT32 smmu0_int24_mask6;
+	ZXIC_UINT32 smmu0_int24_mask5;
+	ZXIC_UINT32 smmu0_int24_mask4;
+	ZXIC_UINT32 smmu0_int24_mask3;
+	ZXIC_UINT32 smmu0_int24_mask2;
+	ZXIC_UINT32 smmu0_int24_mask1;
+	ZXIC_UINT32 smmu0_int24_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT24_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int24_status_t {
+	ZXIC_UINT32 smmu0_int24_status31;
+	ZXIC_UINT32 smmu0_int24_status30;
+	ZXIC_UINT32 smmu0_int24_status29;
+	ZXIC_UINT32 smmu0_int24_status28;
+	ZXIC_UINT32 smmu0_int24_status27;
+	ZXIC_UINT32 smmu0_int24_status26;
+	ZXIC_UINT32 smmu0_int24_status25;
+	ZXIC_UINT32 smmu0_int24_status24;
+	ZXIC_UINT32 smmu0_int24_status23;
+	ZXIC_UINT32 smmu0_int24_status22;
+	ZXIC_UINT32 smmu0_int24_status21;
+	ZXIC_UINT32 smmu0_int24_status20;
+	ZXIC_UINT32 smmu0_int24_status19;
+	ZXIC_UINT32 smmu0_int24_status18;
+	ZXIC_UINT32 smmu0_int24_status17;
+	ZXIC_UINT32 smmu0_int24_status16;
+	ZXIC_UINT32 smmu0_int24_status15;
+	ZXIC_UINT32 smmu0_int24_status14;
+	ZXIC_UINT32 smmu0_int24_status13;
+	ZXIC_UINT32 smmu0_int24_status12;
+	ZXIC_UINT32 smmu0_int24_status11;
+	ZXIC_UINT32 smmu0_int24_status10;
+	ZXIC_UINT32 smmu0_int24_status9;
+	ZXIC_UINT32 smmu0_int24_status8;
+	ZXIC_UINT32 smmu0_int24_status7;
+	ZXIC_UINT32 smmu0_int24_status6;
+	ZXIC_UINT32 smmu0_int24_status5;
+	ZXIC_UINT32 smmu0_int24_status4;
+	ZXIC_UINT32 smmu0_int24_status3;
+	ZXIC_UINT32 smmu0_int24_status2;
+	ZXIC_UINT32 smmu0_int24_status1;
+	ZXIC_UINT32 smmu0_int24_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT24_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int25_en_t {
+	ZXIC_UINT32 smmu0_int25_en31;
+	ZXIC_UINT32 smmu0_int25_en30;
+	ZXIC_UINT32 smmu0_int25_en29;
+	ZXIC_UINT32 smmu0_int25_en28;
+	ZXIC_UINT32 smmu0_int25_en27;
+	ZXIC_UINT32 smmu0_int25_en26;
+	ZXIC_UINT32 smmu0_int25_en25;
+	ZXIC_UINT32 smmu0_int25_en24;
+	ZXIC_UINT32 smmu0_int25_en23;
+	ZXIC_UINT32 smmu0_int25_en22;
+	ZXIC_UINT32 smmu0_int25_en21;
+	ZXIC_UINT32 smmu0_int25_en20;
+	ZXIC_UINT32 smmu0_int25_en19;
+	ZXIC_UINT32 smmu0_int25_en18;
+	ZXIC_UINT32 smmu0_int25_en17;
+	ZXIC_UINT32 smmu0_int25_en16;
+	ZXIC_UINT32 smmu0_int25_en15;
+	ZXIC_UINT32 smmu0_int25_en14;
+	ZXIC_UINT32 smmu0_int25_en13;
+	ZXIC_UINT32 smmu0_int25_en12;
+	ZXIC_UINT32 smmu0_int25_en11;
+	ZXIC_UINT32 smmu0_int25_en10;
+	ZXIC_UINT32 smmu0_int25_en9;
+	ZXIC_UINT32 smmu0_int25_en8;
+	ZXIC_UINT32 smmu0_int25_en7;
+	ZXIC_UINT32 smmu0_int25_en6;
+	ZXIC_UINT32 smmu0_int25_en5;
+	ZXIC_UINT32 smmu0_int25_en4;
+	ZXIC_UINT32 smmu0_int25_en3;
+	ZXIC_UINT32 smmu0_int25_en2;
+	ZXIC_UINT32 smmu0_int25_en1;
+	ZXIC_UINT32 smmu0_int25_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT25_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int25_mask_t {
+	ZXIC_UINT32 smmu0_int25_mask31;
+	ZXIC_UINT32 smmu0_int25_mask30;
+	ZXIC_UINT32 smmu0_int25_mask29;
+	ZXIC_UINT32 smmu0_int25_mask28;
+	ZXIC_UINT32 smmu0_int25_mask27;
+	ZXIC_UINT32 smmu0_int25_mask26;
+	ZXIC_UINT32 smmu0_int25_mask25;
+	ZXIC_UINT32 smmu0_int25_mask24;
+	ZXIC_UINT32 smmu0_int25_mask23;
+	ZXIC_UINT32 smmu0_int25_mask22;
+	ZXIC_UINT32 smmu0_int25_mask21;
+	ZXIC_UINT32 smmu0_int25_mask20;
+	ZXIC_UINT32 smmu0_int25_mask19;
+	ZXIC_UINT32 smmu0_int25_mask18;
+	ZXIC_UINT32 smmu0_int25_mask17;
+	ZXIC_UINT32 smmu0_int25_mask16;
+	ZXIC_UINT32 smmu0_int25_mask15;
+	ZXIC_UINT32 smmu0_int25_mask14;
+	ZXIC_UINT32 smmu0_int25_mask13;
+	ZXIC_UINT32 smmu0_int25_mask12;
+	ZXIC_UINT32 smmu0_int25_mask11;
+	ZXIC_UINT32 smmu0_int25_mask10;
+	ZXIC_UINT32 smmu0_int25_mask9;
+	ZXIC_UINT32 smmu0_int25_mask8;
+	ZXIC_UINT32 smmu0_int25_mask7;
+	ZXIC_UINT32 smmu0_int25_mask6;
+	ZXIC_UINT32 smmu0_int25_mask5;
+	ZXIC_UINT32 smmu0_int25_mask4;
+	ZXIC_UINT32 smmu0_int25_mask3;
+	ZXIC_UINT32 smmu0_int25_mask2;
+	ZXIC_UINT32 smmu0_int25_mask1;
+	ZXIC_UINT32 smmu0_int25_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT25_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int25_status_t {
+	ZXIC_UINT32 smmu0_int25_status31;
+	ZXIC_UINT32 smmu0_int25_status30;
+	ZXIC_UINT32 smmu0_int25_status29;
+	ZXIC_UINT32 smmu0_int25_status28;
+	ZXIC_UINT32 smmu0_int25_status27;
+	ZXIC_UINT32 smmu0_int25_status26;
+	ZXIC_UINT32 smmu0_int25_status25;
+	ZXIC_UINT32 smmu0_int25_status24;
+	ZXIC_UINT32 smmu0_int25_status23;
+	ZXIC_UINT32 smmu0_int25_status22;
+	ZXIC_UINT32 smmu0_int25_status21;
+	ZXIC_UINT32 smmu0_int25_status20;
+	ZXIC_UINT32 smmu0_int25_status19;
+	ZXIC_UINT32 smmu0_int25_status18;
+	ZXIC_UINT32 smmu0_int25_status17;
+	ZXIC_UINT32 smmu0_int25_status16;
+	ZXIC_UINT32 smmu0_int25_status15;
+	ZXIC_UINT32 smmu0_int25_status14;
+	ZXIC_UINT32 smmu0_int25_status13;
+	ZXIC_UINT32 smmu0_int25_status12;
+	ZXIC_UINT32 smmu0_int25_status11;
+	ZXIC_UINT32 smmu0_int25_status10;
+	ZXIC_UINT32 smmu0_int25_status9;
+	ZXIC_UINT32 smmu0_int25_status8;
+	ZXIC_UINT32 smmu0_int25_status7;
+	ZXIC_UINT32 smmu0_int25_status6;
+	ZXIC_UINT32 smmu0_int25_status5;
+	ZXIC_UINT32 smmu0_int25_status4;
+	ZXIC_UINT32 smmu0_int25_status3;
+	ZXIC_UINT32 smmu0_int25_status2;
+	ZXIC_UINT32 smmu0_int25_status1;
+	ZXIC_UINT32 smmu0_int25_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT25_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int26_en_t {
+	ZXIC_UINT32 smmu0_int26_en31;
+	ZXIC_UINT32 smmu0_int26_en30;
+	ZXIC_UINT32 smmu0_int26_en29;
+	ZXIC_UINT32 smmu0_int26_en28;
+	ZXIC_UINT32 smmu0_int26_en27;
+	ZXIC_UINT32 smmu0_int26_en26;
+	ZXIC_UINT32 smmu0_int26_en25;
+	ZXIC_UINT32 smmu0_int26_en24;
+	ZXIC_UINT32 smmu0_int26_en23;
+	ZXIC_UINT32 smmu0_int26_en22;
+	ZXIC_UINT32 smmu0_int26_en21;
+	ZXIC_UINT32 smmu0_int26_en20;
+	ZXIC_UINT32 smmu0_int26_en19;
+	ZXIC_UINT32 smmu0_int26_en18;
+	ZXIC_UINT32 smmu0_int26_en17;
+	ZXIC_UINT32 smmu0_int26_en16;
+	ZXIC_UINT32 smmu0_int26_en15;
+	ZXIC_UINT32 smmu0_int26_en14;
+	ZXIC_UINT32 smmu0_int26_en13;
+	ZXIC_UINT32 smmu0_int26_en12;
+	ZXIC_UINT32 smmu0_int26_en11;
+	ZXIC_UINT32 smmu0_int26_en10;
+	ZXIC_UINT32 smmu0_int26_en9;
+	ZXIC_UINT32 smmu0_int26_en8;
+	ZXIC_UINT32 smmu0_int26_en7;
+	ZXIC_UINT32 smmu0_int26_en6;
+	ZXIC_UINT32 smmu0_int26_en5;
+	ZXIC_UINT32 smmu0_int26_en4;
+	ZXIC_UINT32 smmu0_int26_en3;
+	ZXIC_UINT32 smmu0_int26_en2;
+	ZXIC_UINT32 smmu0_int26_en1;
+	ZXIC_UINT32 smmu0_int26_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT26_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int26_mask_t {
+	ZXIC_UINT32 smmu0_int26_mask31;
+	ZXIC_UINT32 smmu0_int26_mask30;
+	ZXIC_UINT32 smmu0_int26_mask29;
+	ZXIC_UINT32 smmu0_int26_mask28;
+	ZXIC_UINT32 smmu0_int26_mask27;
+	ZXIC_UINT32 smmu0_int26_mask26;
+	ZXIC_UINT32 smmu0_int26_mask25;
+	ZXIC_UINT32 smmu0_int26_mask24;
+	ZXIC_UINT32 smmu0_int26_mask23;
+	ZXIC_UINT32 smmu0_int26_mask22;
+	ZXIC_UINT32 smmu0_int26_mask21;
+	ZXIC_UINT32 smmu0_int26_mask20;
+	ZXIC_UINT32 smmu0_int26_mask19;
+	ZXIC_UINT32 smmu0_int26_mask18;
+	ZXIC_UINT32 smmu0_int26_mask17;
+	ZXIC_UINT32 smmu0_int26_mask16;
+	ZXIC_UINT32 smmu0_int26_mask15;
+	ZXIC_UINT32 smmu0_int26_mask14;
+	ZXIC_UINT32 smmu0_int26_mask13;
+	ZXIC_UINT32 smmu0_int26_mask12;
+	ZXIC_UINT32 smmu0_int26_mask11;
+	ZXIC_UINT32 smmu0_int26_mask10;
+	ZXIC_UINT32 smmu0_int26_mask9;
+	ZXIC_UINT32 smmu0_int26_mask8;
+	ZXIC_UINT32 smmu0_int26_mask7;
+	ZXIC_UINT32 smmu0_int26_mask6;
+	ZXIC_UINT32 smmu0_int26_mask5;
+	ZXIC_UINT32 smmu0_int26_mask4;
+	ZXIC_UINT32 smmu0_int26_mask3;
+	ZXIC_UINT32 smmu0_int26_mask2;
+	ZXIC_UINT32 smmu0_int26_mask1;
+	ZXIC_UINT32 smmu0_int26_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT26_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int26_status_t {
+	ZXIC_UINT32 smmu0_int26_status31;
+	ZXIC_UINT32 smmu0_int26_status30;
+	ZXIC_UINT32 smmu0_int26_status29;
+	ZXIC_UINT32 smmu0_int26_status28;
+	ZXIC_UINT32 smmu0_int26_status27;
+	ZXIC_UINT32 smmu0_int26_status26;
+	ZXIC_UINT32 smmu0_int26_status25;
+	ZXIC_UINT32 smmu0_int26_status24;
+	ZXIC_UINT32 smmu0_int26_status23;
+	ZXIC_UINT32 smmu0_int26_status22;
+	ZXIC_UINT32 smmu0_int26_status21;
+	ZXIC_UINT32 smmu0_int26_status20;
+	ZXIC_UINT32 smmu0_int26_status19;
+	ZXIC_UINT32 smmu0_int26_status18;
+	ZXIC_UINT32 smmu0_int26_status17;
+	ZXIC_UINT32 smmu0_int26_status16;
+	ZXIC_UINT32 smmu0_int26_status15;
+	ZXIC_UINT32 smmu0_int26_status14;
+	ZXIC_UINT32 smmu0_int26_status13;
+	ZXIC_UINT32 smmu0_int26_status12;
+	ZXIC_UINT32 smmu0_int26_status11;
+	ZXIC_UINT32 smmu0_int26_status10;
+	ZXIC_UINT32 smmu0_int26_status9;
+	ZXIC_UINT32 smmu0_int26_status8;
+	ZXIC_UINT32 smmu0_int26_status7;
+	ZXIC_UINT32 smmu0_int26_status6;
+	ZXIC_UINT32 smmu0_int26_status5;
+	ZXIC_UINT32 smmu0_int26_status4;
+	ZXIC_UINT32 smmu0_int26_status3;
+	ZXIC_UINT32 smmu0_int26_status2;
+	ZXIC_UINT32 smmu0_int26_status1;
+	ZXIC_UINT32 smmu0_int26_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT26_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int27_en_t {
+	ZXIC_UINT32 smmu0_int27_en31;
+	ZXIC_UINT32 smmu0_int27_en30;
+	ZXIC_UINT32 smmu0_int27_en29;
+	ZXIC_UINT32 smmu0_int27_en28;
+	ZXIC_UINT32 smmu0_int27_en27;
+	ZXIC_UINT32 smmu0_int27_en26;
+	ZXIC_UINT32 smmu0_int27_en25;
+	ZXIC_UINT32 smmu0_int27_en24;
+	ZXIC_UINT32 smmu0_int27_en23;
+	ZXIC_UINT32 smmu0_int27_en22;
+	ZXIC_UINT32 smmu0_int27_en21;
+	ZXIC_UINT32 smmu0_int27_en20;
+	ZXIC_UINT32 smmu0_int27_en19;
+	ZXIC_UINT32 smmu0_int27_en18;
+	ZXIC_UINT32 smmu0_int27_en17;
+	ZXIC_UINT32 smmu0_int27_en16;
+	ZXIC_UINT32 smmu0_int27_en15;
+	ZXIC_UINT32 smmu0_int27_en14;
+	ZXIC_UINT32 smmu0_int27_en13;
+	ZXIC_UINT32 smmu0_int27_en12;
+	ZXIC_UINT32 smmu0_int27_en11;
+	ZXIC_UINT32 smmu0_int27_en10;
+	ZXIC_UINT32 smmu0_int27_en9;
+	ZXIC_UINT32 smmu0_int27_en8;
+	ZXIC_UINT32 smmu0_int27_en7;
+	ZXIC_UINT32 smmu0_int27_en6;
+	ZXIC_UINT32 smmu0_int27_en5;
+	ZXIC_UINT32 smmu0_int27_en4;
+	ZXIC_UINT32 smmu0_int27_en3;
+	ZXIC_UINT32 smmu0_int27_en2;
+	ZXIC_UINT32 smmu0_int27_en1;
+	ZXIC_UINT32 smmu0_int27_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT27_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int27_mask_t {
+	ZXIC_UINT32 smmu0_int27_mask31;
+	ZXIC_UINT32 smmu0_int27_mask30;
+	ZXIC_UINT32 smmu0_int27_mask29;
+	ZXIC_UINT32 smmu0_int27_mask28;
+	ZXIC_UINT32 smmu0_int27_mask27;
+	ZXIC_UINT32 smmu0_int27_mask26;
+	ZXIC_UINT32 smmu0_int27_mask25;
+	ZXIC_UINT32 smmu0_int27_mask24;
+	ZXIC_UINT32 smmu0_int27_mask23;
+	ZXIC_UINT32 smmu0_int27_mask22;
+	ZXIC_UINT32 smmu0_int27_mask21;
+	ZXIC_UINT32 smmu0_int27_mask20;
+	ZXIC_UINT32 smmu0_int27_mask19;
+	ZXIC_UINT32 smmu0_int27_mask18;
+	ZXIC_UINT32 smmu0_int27_mask17;
+	ZXIC_UINT32 smmu0_int27_mask16;
+	ZXIC_UINT32 smmu0_int27_mask15;
+	ZXIC_UINT32 smmu0_int27_mask14;
+	ZXIC_UINT32 smmu0_int27_mask13;
+	ZXIC_UINT32 smmu0_int27_mask12;
+	ZXIC_UINT32 smmu0_int27_mask11;
+	ZXIC_UINT32 smmu0_int27_mask10;
+	ZXIC_UINT32 smmu0_int27_mask9;
+	ZXIC_UINT32 smmu0_int27_mask8;
+	ZXIC_UINT32 smmu0_int27_mask7;
+	ZXIC_UINT32 smmu0_int27_mask6;
+	ZXIC_UINT32 smmu0_int27_mask5;
+	ZXIC_UINT32 smmu0_int27_mask4;
+	ZXIC_UINT32 smmu0_int27_mask3;
+	ZXIC_UINT32 smmu0_int27_mask2;
+	ZXIC_UINT32 smmu0_int27_mask1;
+	ZXIC_UINT32 smmu0_int27_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT27_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int27_status_t {
+	ZXIC_UINT32 smmu0_int27_status31;
+	ZXIC_UINT32 smmu0_int27_status30;
+	ZXIC_UINT32 smmu0_int27_status29;
+	ZXIC_UINT32 smmu0_int27_status28;
+	ZXIC_UINT32 smmu0_int27_status27;
+	ZXIC_UINT32 smmu0_int27_status26;
+	ZXIC_UINT32 smmu0_int27_status25;
+	ZXIC_UINT32 smmu0_int27_status24;
+	ZXIC_UINT32 smmu0_int27_status23;
+	ZXIC_UINT32 smmu0_int27_status22;
+	ZXIC_UINT32 smmu0_int27_status21;
+	ZXIC_UINT32 smmu0_int27_status20;
+	ZXIC_UINT32 smmu0_int27_status19;
+	ZXIC_UINT32 smmu0_int27_status18;
+	ZXIC_UINT32 smmu0_int27_status17;
+	ZXIC_UINT32 smmu0_int27_status16;
+	ZXIC_UINT32 smmu0_int27_status15;
+	ZXIC_UINT32 smmu0_int27_status14;
+	ZXIC_UINT32 smmu0_int27_status13;
+	ZXIC_UINT32 smmu0_int27_status12;
+	ZXIC_UINT32 smmu0_int27_status11;
+	ZXIC_UINT32 smmu0_int27_status10;
+	ZXIC_UINT32 smmu0_int27_status9;
+	ZXIC_UINT32 smmu0_int27_status8;
+	ZXIC_UINT32 smmu0_int27_status7;
+	ZXIC_UINT32 smmu0_int27_status6;
+	ZXIC_UINT32 smmu0_int27_status5;
+	ZXIC_UINT32 smmu0_int27_status4;
+	ZXIC_UINT32 smmu0_int27_status3;
+	ZXIC_UINT32 smmu0_int27_status2;
+	ZXIC_UINT32 smmu0_int27_status1;
+	ZXIC_UINT32 smmu0_int27_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT27_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int28_en_t {
+	ZXIC_UINT32 smmu0_int28_en31;
+	ZXIC_UINT32 smmu0_int28_en30;
+	ZXIC_UINT32 smmu0_int28_en29;
+	ZXIC_UINT32 smmu0_int28_en28;
+	ZXIC_UINT32 smmu0_int28_en27;
+	ZXIC_UINT32 smmu0_int28_en26;
+	ZXIC_UINT32 smmu0_int28_en25;
+	ZXIC_UINT32 smmu0_int28_en24;
+	ZXIC_UINT32 smmu0_int28_en23;
+	ZXIC_UINT32 smmu0_int28_en22;
+	ZXIC_UINT32 smmu0_int28_en21;
+	ZXIC_UINT32 smmu0_int28_en20;
+	ZXIC_UINT32 smmu0_int28_en19;
+	ZXIC_UINT32 smmu0_int28_en18;
+	ZXIC_UINT32 smmu0_int28_en17;
+	ZXIC_UINT32 smmu0_int28_en16;
+	ZXIC_UINT32 smmu0_int28_en15;
+	ZXIC_UINT32 smmu0_int28_en14;
+	ZXIC_UINT32 smmu0_int28_en13;
+	ZXIC_UINT32 smmu0_int28_en12;
+	ZXIC_UINT32 smmu0_int28_en11;
+	ZXIC_UINT32 smmu0_int28_en10;
+	ZXIC_UINT32 smmu0_int28_en9;
+	ZXIC_UINT32 smmu0_int28_en8;
+	ZXIC_UINT32 smmu0_int28_en7;
+	ZXIC_UINT32 smmu0_int28_en6;
+	ZXIC_UINT32 smmu0_int28_en5;
+	ZXIC_UINT32 smmu0_int28_en4;
+	ZXIC_UINT32 smmu0_int28_en3;
+	ZXIC_UINT32 smmu0_int28_en2;
+	ZXIC_UINT32 smmu0_int28_en1;
+	ZXIC_UINT32 smmu0_int28_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT28_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int28_mask_t {
+	ZXIC_UINT32 smmu0_int28_mask31;
+	ZXIC_UINT32 smmu0_int28_mask30;
+	ZXIC_UINT32 smmu0_int28_mask29;
+	ZXIC_UINT32 smmu0_int28_mask28;
+	ZXIC_UINT32 smmu0_int28_mask27;
+	ZXIC_UINT32 smmu0_int28_mask26;
+	ZXIC_UINT32 smmu0_int28_mask25;
+	ZXIC_UINT32 smmu0_int28_mask24;
+	ZXIC_UINT32 smmu0_int28_mask23;
+	ZXIC_UINT32 smmu0_int28_mask22;
+	ZXIC_UINT32 smmu0_int28_mask21;
+	ZXIC_UINT32 smmu0_int28_mask20;
+	ZXIC_UINT32 smmu0_int28_mask19;
+	ZXIC_UINT32 smmu0_int28_mask18;
+	ZXIC_UINT32 smmu0_int28_mask17;
+	ZXIC_UINT32 smmu0_int28_mask16;
+	ZXIC_UINT32 smmu0_int28_mask15;
+	ZXIC_UINT32 smmu0_int28_mask14;
+	ZXIC_UINT32 smmu0_int28_mask13;
+	ZXIC_UINT32 smmu0_int28_mask12;
+	ZXIC_UINT32 smmu0_int28_mask11;
+	ZXIC_UINT32 smmu0_int28_mask10;
+	ZXIC_UINT32 smmu0_int28_mask9;
+	ZXIC_UINT32 smmu0_int28_mask8;
+	ZXIC_UINT32 smmu0_int28_mask7;
+	ZXIC_UINT32 smmu0_int28_mask6;
+	ZXIC_UINT32 smmu0_int28_mask5;
+	ZXIC_UINT32 smmu0_int28_mask4;
+	ZXIC_UINT32 smmu0_int28_mask3;
+	ZXIC_UINT32 smmu0_int28_mask2;
+	ZXIC_UINT32 smmu0_int28_mask1;
+	ZXIC_UINT32 smmu0_int28_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT28_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int28_status_t {
+	ZXIC_UINT32 smmu0_int28_status31;
+	ZXIC_UINT32 smmu0_int28_status30;
+	ZXIC_UINT32 smmu0_int28_status29;
+	ZXIC_UINT32 smmu0_int28_status28;
+	ZXIC_UINT32 smmu0_int28_status27;
+	ZXIC_UINT32 smmu0_int28_status26;
+	ZXIC_UINT32 smmu0_int28_status25;
+	ZXIC_UINT32 smmu0_int28_status24;
+	ZXIC_UINT32 smmu0_int28_status23;
+	ZXIC_UINT32 smmu0_int28_status22;
+	ZXIC_UINT32 smmu0_int28_status21;
+	ZXIC_UINT32 smmu0_int28_status20;
+	ZXIC_UINT32 smmu0_int28_status19;
+	ZXIC_UINT32 smmu0_int28_status18;
+	ZXIC_UINT32 smmu0_int28_status17;
+	ZXIC_UINT32 smmu0_int28_status16;
+	ZXIC_UINT32 smmu0_int28_status15;
+	ZXIC_UINT32 smmu0_int28_status14;
+	ZXIC_UINT32 smmu0_int28_status13;
+	ZXIC_UINT32 smmu0_int28_status12;
+	ZXIC_UINT32 smmu0_int28_status11;
+	ZXIC_UINT32 smmu0_int28_status10;
+	ZXIC_UINT32 smmu0_int28_status9;
+	ZXIC_UINT32 smmu0_int28_status8;
+	ZXIC_UINT32 smmu0_int28_status7;
+	ZXIC_UINT32 smmu0_int28_status6;
+	ZXIC_UINT32 smmu0_int28_status5;
+	ZXIC_UINT32 smmu0_int28_status4;
+	ZXIC_UINT32 smmu0_int28_status3;
+	ZXIC_UINT32 smmu0_int28_status2;
+	ZXIC_UINT32 smmu0_int28_status1;
+	ZXIC_UINT32 smmu0_int28_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT28_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int29_en_t {
+	ZXIC_UINT32 smmu0_int29_en31;
+	ZXIC_UINT32 smmu0_int29_en30;
+	ZXIC_UINT32 smmu0_int29_en29;
+	ZXIC_UINT32 smmu0_int29_en28;
+	ZXIC_UINT32 smmu0_int29_en27;
+	ZXIC_UINT32 smmu0_int29_en26;
+	ZXIC_UINT32 smmu0_int29_en25;
+	ZXIC_UINT32 smmu0_int29_en24;
+	ZXIC_UINT32 smmu0_int29_en23;
+	ZXIC_UINT32 smmu0_int29_en22;
+	ZXIC_UINT32 smmu0_int29_en21;
+	ZXIC_UINT32 smmu0_int29_en20;
+	ZXIC_UINT32 smmu0_int29_en19;
+	ZXIC_UINT32 smmu0_int29_en18;
+	ZXIC_UINT32 smmu0_int29_en17;
+	ZXIC_UINT32 smmu0_int29_en16;
+	ZXIC_UINT32 smmu0_int29_en15;
+	ZXIC_UINT32 smmu0_int29_en14;
+	ZXIC_UINT32 smmu0_int29_en13;
+	ZXIC_UINT32 smmu0_int29_en12;
+	ZXIC_UINT32 smmu0_int29_en11;
+	ZXIC_UINT32 smmu0_int29_en10;
+	ZXIC_UINT32 smmu0_int29_en9;
+	ZXIC_UINT32 smmu0_int29_en8;
+	ZXIC_UINT32 smmu0_int29_en7;
+	ZXIC_UINT32 smmu0_int29_en6;
+	ZXIC_UINT32 smmu0_int29_en5;
+	ZXIC_UINT32 smmu0_int29_en4;
+	ZXIC_UINT32 smmu0_int29_en3;
+	ZXIC_UINT32 smmu0_int29_en2;
+	ZXIC_UINT32 smmu0_int29_en1;
+	ZXIC_UINT32 smmu0_int29_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT29_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int29_mask_t {
+	ZXIC_UINT32 smmu0_int29_mask31;
+	ZXIC_UINT32 smmu0_int29_mask30;
+	ZXIC_UINT32 smmu0_int29_mask29;
+	ZXIC_UINT32 smmu0_int29_mask28;
+	ZXIC_UINT32 smmu0_int29_mask27;
+	ZXIC_UINT32 smmu0_int29_mask26;
+	ZXIC_UINT32 smmu0_int29_mask25;
+	ZXIC_UINT32 smmu0_int29_mask24;
+	ZXIC_UINT32 smmu0_int29_mask23;
+	ZXIC_UINT32 smmu0_int29_mask22;
+	ZXIC_UINT32 smmu0_int29_mask21;
+	ZXIC_UINT32 smmu0_int29_mask20;
+	ZXIC_UINT32 smmu0_int29_mask19;
+	ZXIC_UINT32 smmu0_int29_mask18;
+	ZXIC_UINT32 smmu0_int29_mask17;
+	ZXIC_UINT32 smmu0_int29_mask16;
+	ZXIC_UINT32 smmu0_int29_mask15;
+	ZXIC_UINT32 smmu0_int29_mask14;
+	ZXIC_UINT32 smmu0_int29_mask13;
+	ZXIC_UINT32 smmu0_int29_mask12;
+	ZXIC_UINT32 smmu0_int29_mask11;
+	ZXIC_UINT32 smmu0_int29_mask10;
+	ZXIC_UINT32 smmu0_int29_mask9;
+	ZXIC_UINT32 smmu0_int29_mask8;
+	ZXIC_UINT32 smmu0_int29_mask7;
+	ZXIC_UINT32 smmu0_int29_mask6;
+	ZXIC_UINT32 smmu0_int29_mask5;
+	ZXIC_UINT32 smmu0_int29_mask4;
+	ZXIC_UINT32 smmu0_int29_mask3;
+	ZXIC_UINT32 smmu0_int29_mask2;
+	ZXIC_UINT32 smmu0_int29_mask1;
+	ZXIC_UINT32 smmu0_int29_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT29_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int29_status_t {
+	ZXIC_UINT32 smmu0_int29_status31;
+	ZXIC_UINT32 smmu0_int29_status30;
+	ZXIC_UINT32 smmu0_int29_status29;
+	ZXIC_UINT32 smmu0_int29_status28;
+	ZXIC_UINT32 smmu0_int29_status27;
+	ZXIC_UINT32 smmu0_int29_status26;
+	ZXIC_UINT32 smmu0_int29_status25;
+	ZXIC_UINT32 smmu0_int29_status24;
+	ZXIC_UINT32 smmu0_int29_status23;
+	ZXIC_UINT32 smmu0_int29_status22;
+	ZXIC_UINT32 smmu0_int29_status21;
+	ZXIC_UINT32 smmu0_int29_status20;
+	ZXIC_UINT32 smmu0_int29_status19;
+	ZXIC_UINT32 smmu0_int29_status18;
+	ZXIC_UINT32 smmu0_int29_status17;
+	ZXIC_UINT32 smmu0_int29_status16;
+	ZXIC_UINT32 smmu0_int29_status15;
+	ZXIC_UINT32 smmu0_int29_status14;
+	ZXIC_UINT32 smmu0_int29_status13;
+	ZXIC_UINT32 smmu0_int29_status12;
+	ZXIC_UINT32 smmu0_int29_status11;
+	ZXIC_UINT32 smmu0_int29_status10;
+	ZXIC_UINT32 smmu0_int29_status9;
+	ZXIC_UINT32 smmu0_int29_status8;
+	ZXIC_UINT32 smmu0_int29_status7;
+	ZXIC_UINT32 smmu0_int29_status6;
+	ZXIC_UINT32 smmu0_int29_status5;
+	ZXIC_UINT32 smmu0_int29_status4;
+	ZXIC_UINT32 smmu0_int29_status3;
+	ZXIC_UINT32 smmu0_int29_status2;
+	ZXIC_UINT32 smmu0_int29_status1;
+	ZXIC_UINT32 smmu0_int29_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT29_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int30_en_t {
+	ZXIC_UINT32 smmu0_int30_en31;
+	ZXIC_UINT32 smmu0_int30_en30;
+	ZXIC_UINT32 smmu0_int30_en29;
+	ZXIC_UINT32 smmu0_int30_en28;
+	ZXIC_UINT32 smmu0_int30_en27;
+	ZXIC_UINT32 smmu0_int30_en26;
+	ZXIC_UINT32 smmu0_int30_en25;
+	ZXIC_UINT32 smmu0_int30_en24;
+	ZXIC_UINT32 smmu0_int30_en23;
+	ZXIC_UINT32 smmu0_int30_en22;
+	ZXIC_UINT32 smmu0_int30_en21;
+	ZXIC_UINT32 smmu0_int30_en20;
+	ZXIC_UINT32 smmu0_int30_en19;
+	ZXIC_UINT32 smmu0_int30_en18;
+	ZXIC_UINT32 smmu0_int30_en17;
+	ZXIC_UINT32 smmu0_int30_en16;
+	ZXIC_UINT32 smmu0_int30_en15;
+	ZXIC_UINT32 smmu0_int30_en14;
+	ZXIC_UINT32 smmu0_int30_en13;
+	ZXIC_UINT32 smmu0_int30_en12;
+	ZXIC_UINT32 smmu0_int30_en11;
+	ZXIC_UINT32 smmu0_int30_en10;
+	ZXIC_UINT32 smmu0_int30_en9;
+	ZXIC_UINT32 smmu0_int30_en8;
+	ZXIC_UINT32 smmu0_int30_en7;
+	ZXIC_UINT32 smmu0_int30_en6;
+	ZXIC_UINT32 smmu0_int30_en5;
+	ZXIC_UINT32 smmu0_int30_en4;
+	ZXIC_UINT32 smmu0_int30_en3;
+	ZXIC_UINT32 smmu0_int30_en2;
+	ZXIC_UINT32 smmu0_int30_en1;
+	ZXIC_UINT32 smmu0_int30_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT30_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int30_mask_t {
+	ZXIC_UINT32 smmu0_int30_mask31;
+	ZXIC_UINT32 smmu0_int30_mask30;
+	ZXIC_UINT32 smmu0_int30_mask29;
+	ZXIC_UINT32 smmu0_int30_mask28;
+	ZXIC_UINT32 smmu0_int30_mask27;
+	ZXIC_UINT32 smmu0_int30_mask26;
+	ZXIC_UINT32 smmu0_int30_mask25;
+	ZXIC_UINT32 smmu0_int30_mask24;
+	ZXIC_UINT32 smmu0_int30_mask23;
+	ZXIC_UINT32 smmu0_int30_mask22;
+	ZXIC_UINT32 smmu0_int30_mask21;
+	ZXIC_UINT32 smmu0_int30_mask20;
+	ZXIC_UINT32 smmu0_int30_mask19;
+	ZXIC_UINT32 smmu0_int30_mask18;
+	ZXIC_UINT32 smmu0_int30_mask17;
+	ZXIC_UINT32 smmu0_int30_mask16;
+	ZXIC_UINT32 smmu0_int30_mask15;
+	ZXIC_UINT32 smmu0_int30_mask14;
+	ZXIC_UINT32 smmu0_int30_mask13;
+	ZXIC_UINT32 smmu0_int30_mask12;
+	ZXIC_UINT32 smmu0_int30_mask11;
+	ZXIC_UINT32 smmu0_int30_mask10;
+	ZXIC_UINT32 smmu0_int30_mask9;
+	ZXIC_UINT32 smmu0_int30_mask8;
+	ZXIC_UINT32 smmu0_int30_mask7;
+	ZXIC_UINT32 smmu0_int30_mask6;
+	ZXIC_UINT32 smmu0_int30_mask5;
+	ZXIC_UINT32 smmu0_int30_mask4;
+	ZXIC_UINT32 smmu0_int30_mask3;
+	ZXIC_UINT32 smmu0_int30_mask2;
+	ZXIC_UINT32 smmu0_int30_mask1;
+	ZXIC_UINT32 smmu0_int30_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT30_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int30_status_t {
+	ZXIC_UINT32 smmu0_int30_status31;
+	ZXIC_UINT32 smmu0_int30_status30;
+	ZXIC_UINT32 smmu0_int30_status29;
+	ZXIC_UINT32 smmu0_int30_status28;
+	ZXIC_UINT32 smmu0_int30_status27;
+	ZXIC_UINT32 smmu0_int30_status26;
+	ZXIC_UINT32 smmu0_int30_status25;
+	ZXIC_UINT32 smmu0_int30_status24;
+	ZXIC_UINT32 smmu0_int30_status23;
+	ZXIC_UINT32 smmu0_int30_status22;
+	ZXIC_UINT32 smmu0_int30_status21;
+	ZXIC_UINT32 smmu0_int30_status20;
+	ZXIC_UINT32 smmu0_int30_status19;
+	ZXIC_UINT32 smmu0_int30_status18;
+	ZXIC_UINT32 smmu0_int30_status17;
+	ZXIC_UINT32 smmu0_int30_status16;
+	ZXIC_UINT32 smmu0_int30_status15;
+	ZXIC_UINT32 smmu0_int30_status14;
+	ZXIC_UINT32 smmu0_int30_status13;
+	ZXIC_UINT32 smmu0_int30_status12;
+	ZXIC_UINT32 smmu0_int30_status11;
+	ZXIC_UINT32 smmu0_int30_status10;
+	ZXIC_UINT32 smmu0_int30_status9;
+	ZXIC_UINT32 smmu0_int30_status8;
+	ZXIC_UINT32 smmu0_int30_status7;
+	ZXIC_UINT32 smmu0_int30_status6;
+	ZXIC_UINT32 smmu0_int30_status5;
+	ZXIC_UINT32 smmu0_int30_status4;
+	ZXIC_UINT32 smmu0_int30_status3;
+	ZXIC_UINT32 smmu0_int30_status2;
+	ZXIC_UINT32 smmu0_int30_status1;
+	ZXIC_UINT32 smmu0_int30_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT30_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int31_en_t {
+	ZXIC_UINT32 smmu0_int31_en31;
+	ZXIC_UINT32 smmu0_int31_en30;
+	ZXIC_UINT32 smmu0_int31_en29;
+	ZXIC_UINT32 smmu0_int31_en28;
+	ZXIC_UINT32 smmu0_int31_en27;
+	ZXIC_UINT32 smmu0_int31_en26;
+	ZXIC_UINT32 smmu0_int31_en25;
+	ZXIC_UINT32 smmu0_int31_en24;
+	ZXIC_UINT32 smmu0_int31_en23;
+	ZXIC_UINT32 smmu0_int31_en22;
+	ZXIC_UINT32 smmu0_int31_en21;
+	ZXIC_UINT32 smmu0_int31_en20;
+	ZXIC_UINT32 smmu0_int31_en19;
+	ZXIC_UINT32 smmu0_int31_en18;
+	ZXIC_UINT32 smmu0_int31_en17;
+	ZXIC_UINT32 smmu0_int31_en16;
+	ZXIC_UINT32 smmu0_int31_en15;
+	ZXIC_UINT32 smmu0_int31_en14;
+	ZXIC_UINT32 smmu0_int31_en13;
+	ZXIC_UINT32 smmu0_int31_en12;
+	ZXIC_UINT32 smmu0_int31_en11;
+	ZXIC_UINT32 smmu0_int31_en10;
+	ZXIC_UINT32 smmu0_int31_en9;
+	ZXIC_UINT32 smmu0_int31_en8;
+	ZXIC_UINT32 smmu0_int31_en7;
+	ZXIC_UINT32 smmu0_int31_en6;
+	ZXIC_UINT32 smmu0_int31_en5;
+	ZXIC_UINT32 smmu0_int31_en4;
+	ZXIC_UINT32 smmu0_int31_en3;
+	ZXIC_UINT32 smmu0_int31_en2;
+	ZXIC_UINT32 smmu0_int31_en1;
+	ZXIC_UINT32 smmu0_int31_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT31_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int31_mask_t {
+	ZXIC_UINT32 smmu0_int31_mask31;
+	ZXIC_UINT32 smmu0_int31_mask30;
+	ZXIC_UINT32 smmu0_int31_mask29;
+	ZXIC_UINT32 smmu0_int31_mask28;
+	ZXIC_UINT32 smmu0_int31_mask27;
+	ZXIC_UINT32 smmu0_int31_mask26;
+	ZXIC_UINT32 smmu0_int31_mask25;
+	ZXIC_UINT32 smmu0_int31_mask24;
+	ZXIC_UINT32 smmu0_int31_mask23;
+	ZXIC_UINT32 smmu0_int31_mask22;
+	ZXIC_UINT32 smmu0_int31_mask21;
+	ZXIC_UINT32 smmu0_int31_mask20;
+	ZXIC_UINT32 smmu0_int31_mask19;
+	ZXIC_UINT32 smmu0_int31_mask18;
+	ZXIC_UINT32 smmu0_int31_mask17;
+	ZXIC_UINT32 smmu0_int31_mask16;
+	ZXIC_UINT32 smmu0_int31_mask15;
+	ZXIC_UINT32 smmu0_int31_mask14;
+	ZXIC_UINT32 smmu0_int31_mask13;
+	ZXIC_UINT32 smmu0_int31_mask12;
+	ZXIC_UINT32 smmu0_int31_mask11;
+	ZXIC_UINT32 smmu0_int31_mask10;
+	ZXIC_UINT32 smmu0_int31_mask9;
+	ZXIC_UINT32 smmu0_int31_mask8;
+	ZXIC_UINT32 smmu0_int31_mask7;
+	ZXIC_UINT32 smmu0_int31_mask6;
+	ZXIC_UINT32 smmu0_int31_mask5;
+	ZXIC_UINT32 smmu0_int31_mask4;
+	ZXIC_UINT32 smmu0_int31_mask3;
+	ZXIC_UINT32 smmu0_int31_mask2;
+	ZXIC_UINT32 smmu0_int31_mask1;
+	ZXIC_UINT32 smmu0_int31_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT31_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int31_status_t {
+	ZXIC_UINT32 smmu0_int31_status31;
+	ZXIC_UINT32 smmu0_int31_status30;
+	ZXIC_UINT32 smmu0_int31_status29;
+	ZXIC_UINT32 smmu0_int31_status28;
+	ZXIC_UINT32 smmu0_int31_status27;
+	ZXIC_UINT32 smmu0_int31_status26;
+	ZXIC_UINT32 smmu0_int31_status25;
+	ZXIC_UINT32 smmu0_int31_status24;
+	ZXIC_UINT32 smmu0_int31_status23;
+	ZXIC_UINT32 smmu0_int31_status22;
+	ZXIC_UINT32 smmu0_int31_status21;
+	ZXIC_UINT32 smmu0_int31_status20;
+	ZXIC_UINT32 smmu0_int31_status19;
+	ZXIC_UINT32 smmu0_int31_status18;
+	ZXIC_UINT32 smmu0_int31_status17;
+	ZXIC_UINT32 smmu0_int31_status16;
+	ZXIC_UINT32 smmu0_int31_status15;
+	ZXIC_UINT32 smmu0_int31_status14;
+	ZXIC_UINT32 smmu0_int31_status13;
+	ZXIC_UINT32 smmu0_int31_status12;
+	ZXIC_UINT32 smmu0_int31_status11;
+	ZXIC_UINT32 smmu0_int31_status10;
+	ZXIC_UINT32 smmu0_int31_status9;
+	ZXIC_UINT32 smmu0_int31_status8;
+	ZXIC_UINT32 smmu0_int31_status7;
+	ZXIC_UINT32 smmu0_int31_status6;
+	ZXIC_UINT32 smmu0_int31_status5;
+	ZXIC_UINT32 smmu0_int31_status4;
+	ZXIC_UINT32 smmu0_int31_status3;
+	ZXIC_UINT32 smmu0_int31_status2;
+	ZXIC_UINT32 smmu0_int31_status1;
+	ZXIC_UINT32 smmu0_int31_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT31_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int32_en_t {
+	ZXIC_UINT32 smmu0_int32_en31;
+	ZXIC_UINT32 smmu0_int32_en30;
+	ZXIC_UINT32 smmu0_int32_en29;
+	ZXIC_UINT32 smmu0_int32_en28;
+	ZXIC_UINT32 smmu0_int32_en27;
+	ZXIC_UINT32 smmu0_int32_en26;
+	ZXIC_UINT32 smmu0_int32_en25;
+	ZXIC_UINT32 smmu0_int32_en24;
+	ZXIC_UINT32 smmu0_int32_en23;
+	ZXIC_UINT32 smmu0_int32_en22;
+	ZXIC_UINT32 smmu0_int32_en21;
+	ZXIC_UINT32 smmu0_int32_en20;
+	ZXIC_UINT32 smmu0_int32_en19;
+	ZXIC_UINT32 smmu0_int32_en18;
+	ZXIC_UINT32 smmu0_int32_en17;
+	ZXIC_UINT32 smmu0_int32_en16;
+	ZXIC_UINT32 smmu0_int32_en15;
+	ZXIC_UINT32 smmu0_int32_en14;
+	ZXIC_UINT32 smmu0_int32_en13;
+	ZXIC_UINT32 smmu0_int32_en12;
+	ZXIC_UINT32 smmu0_int32_en11;
+	ZXIC_UINT32 smmu0_int32_en10;
+	ZXIC_UINT32 smmu0_int32_en9;
+	ZXIC_UINT32 smmu0_int32_en8;
+	ZXIC_UINT32 smmu0_int32_en7;
+	ZXIC_UINT32 smmu0_int32_en6;
+	ZXIC_UINT32 smmu0_int32_en5;
+	ZXIC_UINT32 smmu0_int32_en4;
+	ZXIC_UINT32 smmu0_int32_en3;
+	ZXIC_UINT32 smmu0_int32_en2;
+	ZXIC_UINT32 smmu0_int32_en1;
+	ZXIC_UINT32 smmu0_int32_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT32_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int32_mask_t {
+	ZXIC_UINT32 smmu0_int32_mask31;
+	ZXIC_UINT32 smmu0_int32_mask30;
+	ZXIC_UINT32 smmu0_int32_mask29;
+	ZXIC_UINT32 smmu0_int32_mask28;
+	ZXIC_UINT32 smmu0_int32_mask27;
+	ZXIC_UINT32 smmu0_int32_mask26;
+	ZXIC_UINT32 smmu0_int32_mask25;
+	ZXIC_UINT32 smmu0_int32_mask24;
+	ZXIC_UINT32 smmu0_int32_mask23;
+	ZXIC_UINT32 smmu0_int32_mask22;
+	ZXIC_UINT32 smmu0_int32_mask21;
+	ZXIC_UINT32 smmu0_int32_mask20;
+	ZXIC_UINT32 smmu0_int32_mask19;
+	ZXIC_UINT32 smmu0_int32_mask18;
+	ZXIC_UINT32 smmu0_int32_mask17;
+	ZXIC_UINT32 smmu0_int32_mask16;
+	ZXIC_UINT32 smmu0_int32_mask15;
+	ZXIC_UINT32 smmu0_int32_mask14;
+	ZXIC_UINT32 smmu0_int32_mask13;
+	ZXIC_UINT32 smmu0_int32_mask12;
+	ZXIC_UINT32 smmu0_int32_mask11;
+	ZXIC_UINT32 smmu0_int32_mask10;
+	ZXIC_UINT32 smmu0_int32_mask9;
+	ZXIC_UINT32 smmu0_int32_mask8;
+	ZXIC_UINT32 smmu0_int32_mask7;
+	ZXIC_UINT32 smmu0_int32_mask6;
+	ZXIC_UINT32 smmu0_int32_mask5;
+	ZXIC_UINT32 smmu0_int32_mask4;
+	ZXIC_UINT32 smmu0_int32_mask3;
+	ZXIC_UINT32 smmu0_int32_mask2;
+	ZXIC_UINT32 smmu0_int32_mask1;
+	ZXIC_UINT32 smmu0_int32_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT32_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int32_status_t {
+	ZXIC_UINT32 smmu0_int32_status31;
+	ZXIC_UINT32 smmu0_int32_status30;
+	ZXIC_UINT32 smmu0_int32_status29;
+	ZXIC_UINT32 smmu0_int32_status28;
+	ZXIC_UINT32 smmu0_int32_status27;
+	ZXIC_UINT32 smmu0_int32_status26;
+	ZXIC_UINT32 smmu0_int32_status25;
+	ZXIC_UINT32 smmu0_int32_status24;
+	ZXIC_UINT32 smmu0_int32_status23;
+	ZXIC_UINT32 smmu0_int32_status22;
+	ZXIC_UINT32 smmu0_int32_status21;
+	ZXIC_UINT32 smmu0_int32_status20;
+	ZXIC_UINT32 smmu0_int32_status19;
+	ZXIC_UINT32 smmu0_int32_status18;
+	ZXIC_UINT32 smmu0_int32_status17;
+	ZXIC_UINT32 smmu0_int32_status16;
+	ZXIC_UINT32 smmu0_int32_status15;
+	ZXIC_UINT32 smmu0_int32_status14;
+	ZXIC_UINT32 smmu0_int32_status13;
+	ZXIC_UINT32 smmu0_int32_status12;
+	ZXIC_UINT32 smmu0_int32_status11;
+	ZXIC_UINT32 smmu0_int32_status10;
+	ZXIC_UINT32 smmu0_int32_status9;
+	ZXIC_UINT32 smmu0_int32_status8;
+	ZXIC_UINT32 smmu0_int32_status7;
+	ZXIC_UINT32 smmu0_int32_status6;
+	ZXIC_UINT32 smmu0_int32_status5;
+	ZXIC_UINT32 smmu0_int32_status4;
+	ZXIC_UINT32 smmu0_int32_status3;
+	ZXIC_UINT32 smmu0_int32_status2;
+	ZXIC_UINT32 smmu0_int32_status1;
+	ZXIC_UINT32 smmu0_int32_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT32_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int33_en_t {
+	ZXIC_UINT32 smmu0_int33_en31;
+	ZXIC_UINT32 smmu0_int33_en30;
+	ZXIC_UINT32 smmu0_int33_en29;
+	ZXIC_UINT32 smmu0_int33_en28;
+	ZXIC_UINT32 smmu0_int33_en27;
+	ZXIC_UINT32 smmu0_int33_en26;
+	ZXIC_UINT32 smmu0_int33_en25;
+	ZXIC_UINT32 smmu0_int33_en24;
+	ZXIC_UINT32 smmu0_int33_en23;
+	ZXIC_UINT32 smmu0_int33_en22;
+	ZXIC_UINT32 smmu0_int33_en21;
+	ZXIC_UINT32 smmu0_int33_en20;
+	ZXIC_UINT32 smmu0_int33_en19;
+	ZXIC_UINT32 smmu0_int33_en18;
+	ZXIC_UINT32 smmu0_int33_en17;
+	ZXIC_UINT32 smmu0_int33_en16;
+	ZXIC_UINT32 smmu0_int33_en15;
+	ZXIC_UINT32 smmu0_int33_en14;
+	ZXIC_UINT32 smmu0_int33_en13;
+	ZXIC_UINT32 smmu0_int33_en12;
+	ZXIC_UINT32 smmu0_int33_en11;
+	ZXIC_UINT32 smmu0_int33_en10;
+	ZXIC_UINT32 smmu0_int33_en9;
+	ZXIC_UINT32 smmu0_int33_en8;
+	ZXIC_UINT32 smmu0_int33_en7;
+	ZXIC_UINT32 smmu0_int33_en6;
+	ZXIC_UINT32 smmu0_int33_en5;
+	ZXIC_UINT32 smmu0_int33_en4;
+	ZXIC_UINT32 smmu0_int33_en3;
+	ZXIC_UINT32 smmu0_int33_en2;
+	ZXIC_UINT32 smmu0_int33_en1;
+	ZXIC_UINT32 smmu0_int33_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT33_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int33_mask_t {
+	ZXIC_UINT32 smmu0_int33_mask31;
+	ZXIC_UINT32 smmu0_int33_mask30;
+	ZXIC_UINT32 smmu0_int33_mask29;
+	ZXIC_UINT32 smmu0_int33_mask28;
+	ZXIC_UINT32 smmu0_int33_mask27;
+	ZXIC_UINT32 smmu0_int33_mask26;
+	ZXIC_UINT32 smmu0_int33_mask25;
+	ZXIC_UINT32 smmu0_int33_mask24;
+	ZXIC_UINT32 smmu0_int33_mask23;
+	ZXIC_UINT32 smmu0_int33_mask22;
+	ZXIC_UINT32 smmu0_int33_mask21;
+	ZXIC_UINT32 smmu0_int33_mask20;
+	ZXIC_UINT32 smmu0_int33_mask19;
+	ZXIC_UINT32 smmu0_int33_mask18;
+	ZXIC_UINT32 smmu0_int33_mask17;
+	ZXIC_UINT32 smmu0_int33_mask16;
+	ZXIC_UINT32 smmu0_int33_mask15;
+	ZXIC_UINT32 smmu0_int33_mask14;
+	ZXIC_UINT32 smmu0_int33_mask13;
+	ZXIC_UINT32 smmu0_int33_mask12;
+	ZXIC_UINT32 smmu0_int33_mask11;
+	ZXIC_UINT32 smmu0_int33_mask10;
+	ZXIC_UINT32 smmu0_int33_mask9;
+	ZXIC_UINT32 smmu0_int33_mask8;
+	ZXIC_UINT32 smmu0_int33_mask7;
+	ZXIC_UINT32 smmu0_int33_mask6;
+	ZXIC_UINT32 smmu0_int33_mask5;
+	ZXIC_UINT32 smmu0_int33_mask4;
+	ZXIC_UINT32 smmu0_int33_mask3;
+	ZXIC_UINT32 smmu0_int33_mask2;
+	ZXIC_UINT32 smmu0_int33_mask1;
+	ZXIC_UINT32 smmu0_int33_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT33_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int33_status_t {
+	ZXIC_UINT32 smmu0_int33_status31;
+	ZXIC_UINT32 smmu0_int33_status30;
+	ZXIC_UINT32 smmu0_int33_status29;
+	ZXIC_UINT32 smmu0_int33_status28;
+	ZXIC_UINT32 smmu0_int33_status27;
+	ZXIC_UINT32 smmu0_int33_status26;
+	ZXIC_UINT32 smmu0_int33_status25;
+	ZXIC_UINT32 smmu0_int33_status24;
+	ZXIC_UINT32 smmu0_int33_status23;
+	ZXIC_UINT32 smmu0_int33_status22;
+	ZXIC_UINT32 smmu0_int33_status21;
+	ZXIC_UINT32 smmu0_int33_status20;
+	ZXIC_UINT32 smmu0_int33_status19;
+	ZXIC_UINT32 smmu0_int33_status18;
+	ZXIC_UINT32 smmu0_int33_status17;
+	ZXIC_UINT32 smmu0_int33_status16;
+	ZXIC_UINT32 smmu0_int33_status15;
+	ZXIC_UINT32 smmu0_int33_status14;
+	ZXIC_UINT32 smmu0_int33_status13;
+	ZXIC_UINT32 smmu0_int33_status12;
+	ZXIC_UINT32 smmu0_int33_status11;
+	ZXIC_UINT32 smmu0_int33_status10;
+	ZXIC_UINT32 smmu0_int33_status9;
+	ZXIC_UINT32 smmu0_int33_status8;
+	ZXIC_UINT32 smmu0_int33_status7;
+	ZXIC_UINT32 smmu0_int33_status6;
+	ZXIC_UINT32 smmu0_int33_status5;
+	ZXIC_UINT32 smmu0_int33_status4;
+	ZXIC_UINT32 smmu0_int33_status3;
+	ZXIC_UINT32 smmu0_int33_status2;
+	ZXIC_UINT32 smmu0_int33_status1;
+	ZXIC_UINT32 smmu0_int33_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT33_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int34_en_t {
+	ZXIC_UINT32 smmu0_int34_en31;
+	ZXIC_UINT32 smmu0_int34_en30;
+	ZXIC_UINT32 smmu0_int34_en29;
+	ZXIC_UINT32 smmu0_int34_en28;
+	ZXIC_UINT32 smmu0_int34_en27;
+	ZXIC_UINT32 smmu0_int34_en26;
+	ZXIC_UINT32 smmu0_int34_en25;
+	ZXIC_UINT32 smmu0_int34_en24;
+	ZXIC_UINT32 smmu0_int34_en23;
+	ZXIC_UINT32 smmu0_int34_en22;
+	ZXIC_UINT32 smmu0_int34_en21;
+	ZXIC_UINT32 smmu0_int34_en20;
+	ZXIC_UINT32 smmu0_int34_en19;
+	ZXIC_UINT32 smmu0_int34_en18;
+	ZXIC_UINT32 smmu0_int34_en17;
+	ZXIC_UINT32 smmu0_int34_en16;
+	ZXIC_UINT32 smmu0_int34_en15;
+	ZXIC_UINT32 smmu0_int34_en14;
+	ZXIC_UINT32 smmu0_int34_en13;
+	ZXIC_UINT32 smmu0_int34_en12;
+	ZXIC_UINT32 smmu0_int34_en11;
+	ZXIC_UINT32 smmu0_int34_en10;
+	ZXIC_UINT32 smmu0_int34_en9;
+	ZXIC_UINT32 smmu0_int34_en8;
+	ZXIC_UINT32 smmu0_int34_en7;
+	ZXIC_UINT32 smmu0_int34_en6;
+	ZXIC_UINT32 smmu0_int34_en5;
+	ZXIC_UINT32 smmu0_int34_en4;
+	ZXIC_UINT32 smmu0_int34_en3;
+	ZXIC_UINT32 smmu0_int34_en2;
+	ZXIC_UINT32 smmu0_int34_en1;
+	ZXIC_UINT32 smmu0_int34_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT34_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int34_mask_t {
+	ZXIC_UINT32 smmu0_int34_mask31;
+	ZXIC_UINT32 smmu0_int34_mask30;
+	ZXIC_UINT32 smmu0_int34_mask29;
+	ZXIC_UINT32 smmu0_int34_mask28;
+	ZXIC_UINT32 smmu0_int34_mask27;
+	ZXIC_UINT32 smmu0_int34_mask26;
+	ZXIC_UINT32 smmu0_int34_mask25;
+	ZXIC_UINT32 smmu0_int34_mask24;
+	ZXIC_UINT32 smmu0_int34_mask23;
+	ZXIC_UINT32 smmu0_int34_mask22;
+	ZXIC_UINT32 smmu0_int34_mask21;
+	ZXIC_UINT32 smmu0_int34_mask20;
+	ZXIC_UINT32 smmu0_int34_mask19;
+	ZXIC_UINT32 smmu0_int34_mask18;
+	ZXIC_UINT32 smmu0_int34_mask17;
+	ZXIC_UINT32 smmu0_int34_mask16;
+	ZXIC_UINT32 smmu0_int34_mask15;
+	ZXIC_UINT32 smmu0_int34_mask14;
+	ZXIC_UINT32 smmu0_int34_mask13;
+	ZXIC_UINT32 smmu0_int34_mask12;
+	ZXIC_UINT32 smmu0_int34_mask11;
+	ZXIC_UINT32 smmu0_int34_mask10;
+	ZXIC_UINT32 smmu0_int34_mask9;
+	ZXIC_UINT32 smmu0_int34_mask8;
+	ZXIC_UINT32 smmu0_int34_mask7;
+	ZXIC_UINT32 smmu0_int34_mask6;
+	ZXIC_UINT32 smmu0_int34_mask5;
+	ZXIC_UINT32 smmu0_int34_mask4;
+	ZXIC_UINT32 smmu0_int34_mask3;
+	ZXIC_UINT32 smmu0_int34_mask2;
+	ZXIC_UINT32 smmu0_int34_mask1;
+	ZXIC_UINT32 smmu0_int34_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT34_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int34_status_t {
+	ZXIC_UINT32 smmu0_int34_status31;
+	ZXIC_UINT32 smmu0_int34_status30;
+	ZXIC_UINT32 smmu0_int34_status29;
+	ZXIC_UINT32 smmu0_int34_status28;
+	ZXIC_UINT32 smmu0_int34_status27;
+	ZXIC_UINT32 smmu0_int34_status26;
+	ZXIC_UINT32 smmu0_int34_status25;
+	ZXIC_UINT32 smmu0_int34_status24;
+	ZXIC_UINT32 smmu0_int34_status23;
+	ZXIC_UINT32 smmu0_int34_status22;
+	ZXIC_UINT32 smmu0_int34_status21;
+	ZXIC_UINT32 smmu0_int34_status20;
+	ZXIC_UINT32 smmu0_int34_status19;
+	ZXIC_UINT32 smmu0_int34_status18;
+	ZXIC_UINT32 smmu0_int34_status17;
+	ZXIC_UINT32 smmu0_int34_status16;
+	ZXIC_UINT32 smmu0_int34_status15;
+	ZXIC_UINT32 smmu0_int34_status14;
+	ZXIC_UINT32 smmu0_int34_status13;
+	ZXIC_UINT32 smmu0_int34_status12;
+	ZXIC_UINT32 smmu0_int34_status11;
+	ZXIC_UINT32 smmu0_int34_status10;
+	ZXIC_UINT32 smmu0_int34_status9;
+	ZXIC_UINT32 smmu0_int34_status8;
+	ZXIC_UINT32 smmu0_int34_status7;
+	ZXIC_UINT32 smmu0_int34_status6;
+	ZXIC_UINT32 smmu0_int34_status5;
+	ZXIC_UINT32 smmu0_int34_status4;
+	ZXIC_UINT32 smmu0_int34_status3;
+	ZXIC_UINT32 smmu0_int34_status2;
+	ZXIC_UINT32 smmu0_int34_status1;
+	ZXIC_UINT32 smmu0_int34_status0;
+} DPP_SMMU0_SMMU0_SMMU0_INT34_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int35_en_t {
+	ZXIC_UINT32 smmu0_int35_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT35_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int35_mask_t {
+	ZXIC_UINT32 smmu0_int35_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT35_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int35_status_t {
+	ZXIC_UINT32 smmu0_int35_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT35_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int36_en_t {
+	ZXIC_UINT32 smmu0_int36_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT36_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int36_mask_t {
+	ZXIC_UINT32 smmu0_int36_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT36_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int36_status_t {
+	ZXIC_UINT32 smmu0_int36_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT36_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int37_en_t {
+	ZXIC_UINT32 smmu0_int37_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT37_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int37_mask_t {
+	ZXIC_UINT32 smmu0_int37_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT37_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int37_status_t {
+	ZXIC_UINT32 smmu0_int37_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT37_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int38_en_t {
+	ZXIC_UINT32 smmu0_int38_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT38_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int38_mask_t {
+	ZXIC_UINT32 smmu0_int38_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT38_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int38_status_t {
+	ZXIC_UINT32 smmu0_int38_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT38_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int39_en_t {
+	ZXIC_UINT32 smmu0_int39_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT39_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int39_mask_t {
+	ZXIC_UINT32 smmu0_int39_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT39_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int39_status_t {
+	ZXIC_UINT32 smmu0_int39_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT39_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int40_en_t {
+	ZXIC_UINT32 smmu0_int40_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT40_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int40_mask_t {
+	ZXIC_UINT32 smmu0_int40_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT40_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int40_status_t {
+	ZXIC_UINT32 smmu0_int40_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT40_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int41_en_t {
+	ZXIC_UINT32 smmu0_int41_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT41_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int41_mask_t {
+	ZXIC_UINT32 smmu0_int41_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT41_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int41_status_t {
+	ZXIC_UINT32 smmu0_int41_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT41_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int42_en_t {
+	ZXIC_UINT32 smmu0_int42_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT42_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int42_mask_t {
+	ZXIC_UINT32 smmu0_int42_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT42_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int42_status_t {
+	ZXIC_UINT32 smmu0_int42_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT42_STATUS_T;
 
+typedef struct dpp_smmu0_smmu0_smmu0_int43_en_t {
+	ZXIC_UINT32 smmu0_int43_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT43_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int43_mask_t {
+	ZXIC_UINT32 smmu0_int43_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT43_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int43_status_t {
+	ZXIC_UINT32 smmu0_int43_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT43_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int44_en_t {
+	ZXIC_UINT32 smmu0_int44_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT44_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int44_mask_t {
+	ZXIC_UINT32 smmu0_int44_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT44_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int44_status_t {
+	ZXIC_UINT32 smmu0_int44_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT44_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int45_en_t {
+	ZXIC_UINT32 smmu0_int45_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT45_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int45_mask_t {
+	ZXIC_UINT32 smmu0_int45_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT45_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int45_status_t {
+	ZXIC_UINT32 smmu0_int45_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT45_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int46_en_t {
+	ZXIC_UINT32 smmu0_int46_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT46_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int46_mask_t {
+	ZXIC_UINT32 smmu0_int46_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT46_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int46_status_t {
+	ZXIC_UINT32 smmu0_int46_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT46_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int47_en_t {
+	ZXIC_UINT32 smmu0_int47_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT47_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int47_mask_t {
+	ZXIC_UINT32 smmu0_int47_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT47_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int47_status_t {
+	ZXIC_UINT32 smmu0_int47_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT47_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int48_en_t {
+	ZXIC_UINT32 smmu0_int48_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT48_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int48_mask_t {
+	ZXIC_UINT32 smmu0_int48_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT48_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int48_status_t {
+	ZXIC_UINT32 smmu0_int48_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT48_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int49_en_t {
+	ZXIC_UINT32 smmu0_int49_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT49_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int49_mask_t {
+	ZXIC_UINT32 smmu0_int49_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT49_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int49_status_t {
+	ZXIC_UINT32 smmu0_int49_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT49_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int50_en_t {
+	ZXIC_UINT32 smmu0_int50_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT50_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int50_mask_t {
+	ZXIC_UINT32 smmu0_int50_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT50_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int50_status_t {
+	ZXIC_UINT32 smmu0_int50_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT50_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int51_en_t {
+	ZXIC_UINT32 smmu0_int51_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT51_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int51_mask_t {
+	ZXIC_UINT32 smmu0_int51_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT51_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int51_status_t {
+	ZXIC_UINT32 smmu0_int51_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT51_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int52_en_t {
+	ZXIC_UINT32 smmu0_int52_en0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT52_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int52_mask_t {
+	ZXIC_UINT32 smmu0_int52_mask0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT52_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int52_status_t {
+	ZXIC_UINT32 smmu0_int52_status0_31;
+} DPP_SMMU0_SMMU0_SMMU0_INT52_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int53_en_t {
+	ZXIC_UINT32 smmu0_int53_en3;
+	ZXIC_UINT32 smmu0_int53_en2;
+	ZXIC_UINT32 smmu0_int53_en1;
+	ZXIC_UINT32 smmu0_int53_en0;
+} DPP_SMMU0_SMMU0_SMMU0_INT53_EN_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int53_mask_t {
+	ZXIC_UINT32 smmu0_int53_mask3;
+	ZXIC_UINT32 smmu0_int53_mask2;
+	ZXIC_UINT32 smmu0_int53_mask1;
+	ZXIC_UINT32 smmu0_int53_mask0;
+} DPP_SMMU0_SMMU0_SMMU0_INT53_MASK_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_int53_status_t {
+	ZXIC_UINT32 smmu0_int53_status15;
+	ZXIC_UINT32 smmu0_int53_status14;
+	ZXIC_UINT32 smmu0_int53_status13;
+	ZXIC_UINT32 smmu0_int53_status12;
+} DPP_SMMU0_SMMU0_SMMU0_INT53_STATUS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl0_arbiter_ecc_bypass_t {
+	ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_bypass_0;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_bypass_0;
+} DPP_SMMU0_SMMU0_CTRL0_ARBITER_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl2_arbiter_ecc_bypass_t {
+	ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_bypass_0;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_bypass_0;
+} DPP_SMMU0_SMMU0_CTRL2_ARBITER_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl4_arbiter_ecc_bypass_t {
+	ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_bypass_0;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_bypass_0;
+} DPP_SMMU0_SMMU0_CTRL4_ARBITER_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl6_arbiter_ecc_bypass_t {
+	ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_bypass_0;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_bypass_0;
+} DPP_SMMU0_SMMU0_CTRL6_ARBITER_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl8_arbiter_ecc_bypass_t {
+	ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_bypass_0;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_bypass_0;
+} DPP_SMMU0_SMMU0_CTRL8_ARBITER_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl10_arbiter_ecc_bypass_t {
+	ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_bypass_0;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_bypass_0;
+} DPP_SMMU0_SMMU0_CTRL10_ARBITER_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl12_arbiter_ecc_bypass_t {
+	ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_bypass_0;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_bypass_0;
+} DPP_SMMU0_SMMU0_CTRL12_ARBITER_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl14_arbiter_ecc_bypass_t {
+	ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_bypass_0;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_bypass_0;
+} DPP_SMMU0_SMMU0_CTRL14_ARBITER_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl16_arbiter_ecc_bypass_t {
+	ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_bypass_0;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_bypass_0;
+} DPP_SMMU0_SMMU0_CTRL16_ARBITER_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl18_arbiter_ecc_bypass_t {
+	ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_bypass_0;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_bypass_0;
+} DPP_SMMU0_SMMU0_CTRL18_ARBITER_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl20_arbiter_ecc_bypass_t {
+	ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_bypass_0;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_bypass_0;
+} DPP_SMMU0_SMMU0_CTRL20_ARBITER_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl22_arbiter_ecc_bypass_t {
+	ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_bypass_0;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_bypass_0;
+} DPP_SMMU0_SMMU0_CTRL22_ARBITER_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl24_arbiter_ecc_bypass_t {
+	ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_bypass_0;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_bypass_0;
+} DPP_SMMU0_SMMU0_CTRL24_ARBITER_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl26_arbiter_ecc_bypass_t {
+	ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_bypass_0;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_bypass_0;
+} DPP_SMMU0_SMMU0_CTRL26_ARBITER_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl28_arbiter_ecc_bypass_t {
+	ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_bypass_0;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_bypass_0;
+} DPP_SMMU0_SMMU0_CTRL28_ARBITER_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl30_arbiter_ecc_bypass_t {
+	ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_bypass_0;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_15;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_14;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_13;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_12;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_11;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_10;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_9;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_8;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_7;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_6;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_5;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_4;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_3;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_2;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_1;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_bypass_0;
+} DPP_SMMU0_SMMU0_CTRL30_ARBITER_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl_req_ecc_bypass_t {
+	ZXIC_UINT32 ctrl_req_ecc_bypass_0_31;
+} DPP_SMMU0_SMMU0_CTRL_REQ_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl_info_ecc_bypass_t {
+	ZXIC_UINT32 ctrl_info_ecc_bypass_0_31;
+} DPP_SMMU0_SMMU0_CTRL_INFO_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_rschd_ecc_bypass_t {
+	ZXIC_UINT32 smmu0_rschd_ecc_bypass_0_31;
+} DPP_SMMU0_SMMU0_SMMU0_RSCHD_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_wr_ecc_bypass_t {
+	ZXIC_UINT32 smmu0_wr_ecc_bypass1;
+	ZXIC_UINT32 smmu0_wr_ecc_bypass0;
+} DPP_SMMU0_SMMU0_SMMU0_WR_ECC_BYPASS_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl0_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl0_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL0_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl1_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl1_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL1_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl2_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl2_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL2_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl3_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl3_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL3_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl4_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl4_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL4_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl5_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl5_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL5_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl6_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl6_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL6_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl7_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl7_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL7_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl8_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl8_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL8_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl9_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl9_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL9_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl10_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl10_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL10_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl11_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl11_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL11_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl12_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl12_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL12_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl13_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl13_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL13_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl14_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl14_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL14_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl15_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl15_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL15_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl16_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl16_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL16_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl17_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl17_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL17_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl18_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl18_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL18_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl19_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl19_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL19_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl20_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl20_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL20_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl21_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl21_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL21_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl22_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl22_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL22_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl23_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl23_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL23_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl24_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl24_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL24_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl25_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl25_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL25_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl26_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl26_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL26_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl27_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl27_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL27_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl28_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl28_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL28_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl29_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl29_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL29_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl30_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl30_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL30_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl31_arbiter_ecc_err_t {
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_31;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_30;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_29;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_28;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_27;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_26;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_25;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_24;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_23;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_22;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_21;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_20;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_19;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_18;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_17;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_16;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_15;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_14;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_13;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_12;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_11;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_10;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_9;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_8;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_7;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_6;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_5;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_4;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_3;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_2;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_1;
+	ZXIC_UINT32 ctrl31_arbiter_ecc_err_0;
+} DPP_SMMU0_SMMU0_CTRL31_ARBITER_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl_req_ecc_single_err_t {
+	ZXIC_UINT32 ctrl_req_ecc_single_err_0_31;
+} DPP_SMMU0_SMMU0_CTRL_REQ_ECC_SINGLE_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl_req_ecc_double_err_t {
+	ZXIC_UINT32 ctrl_req_ecc_double_err_0_31;
+} DPP_SMMU0_SMMU0_CTRL_REQ_ECC_DOUBLE_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl_info_ecc_single_err_t {
+	ZXIC_UINT32 ctrl_info_ecc_single_err_0_31;
+} DPP_SMMU0_SMMU0_CTRL_INFO_ECC_SINGLE_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl_info_ecc_double_err_t {
+	ZXIC_UINT32 ctrl_info_ecc_double_err_0_31;
+} DPP_SMMU0_SMMU0_CTRL_INFO_ECC_DOUBLE_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_wr_ecc_err_t {
+	ZXIC_UINT32 smmu0_wr_ecc_err_3;
+	ZXIC_UINT32 smmu0_wr_ecc_err_2;
+	ZXIC_UINT32 smmu0_wr_ecc_err_1;
+	ZXIC_UINT32 smmu0_wr_ecc_err_0;
+} DPP_SMMU0_SMMU0_SMMU0_WR_ECC_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_rschd_ecc_single_err_t {
+	ZXIC_UINT32 smmu0_rschd_ecc_single_err_0_31;
+} DPP_SMMU0_SMMU0_SMMU0_RSCHD_ECC_SINGLE_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_rschd_ecc_double_err_t {
+	ZXIC_UINT32 smmu0_rschd_ecc_double_err_0_31;
+} DPP_SMMU0_SMMU0_SMMU0_RSCHD_ECC_DOUBLE_ERR_T;
+
+typedef struct dpp_smmu0_smmu0_ord_fifo_empty_t {
+	ZXIC_UINT32 ord_fifo_empty;
+} DPP_SMMU0_SMMU0_ORD_FIFO_EMPTY_T;
+
+typedef struct dpp_smmu0_smmu0_wr_arb_fifo_empty_t {
+	ZXIC_UINT32 wr_arb_fifo_empty;
+} DPP_SMMU0_SMMU0_WR_ARB_FIFO_EMPTY_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty0_t {
+	ZXIC_UINT32 ctrl_fifo_empty0_5;
+	ZXIC_UINT32 ctrl_fifo_empty0_4;
+	ZXIC_UINT32 ctrl_fifo_empty0_3;
+	ZXIC_UINT32 ctrl_fifo_empty0_2;
+	ZXIC_UINT32 ctrl_fifo_empty0_1;
+	ZXIC_UINT32 ctrl_fifo_empty0_0;
+} DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY0_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty1_t {
+	ZXIC_UINT32 ctrl_fifo_empty1_5;
+	ZXIC_UINT32 ctrl_fifo_empty1_4;
+	ZXIC_UINT32 ctrl_fifo_empty1_3;
+	ZXIC_UINT32 ctrl_fifo_empty1_2;
+	ZXIC_UINT32 ctrl_fifo_empty1_1;
+	ZXIC_UINT32 ctrl_fifo_empty1_0;
+} DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY1_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty2_t {
+	ZXIC_UINT32 ctrl_fifo_empty2_5;
+	ZXIC_UINT32 ctrl_fifo_empty2_4;
+	ZXIC_UINT32 ctrl_fifo_empty2_3;
+	ZXIC_UINT32 ctrl_fifo_empty2_2;
+	ZXIC_UINT32 ctrl_fifo_empty2_1;
+	ZXIC_UINT32 ctrl_fifo_empty2_0;
+} DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY2_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty3_t {
+	ZXIC_UINT32 ctrl_fifo_empty3_5;
+	ZXIC_UINT32 ctrl_fifo_empty3_4;
+	ZXIC_UINT32 ctrl_fifo_empty3_3;
+	ZXIC_UINT32 ctrl_fifo_empty3_2;
+	ZXIC_UINT32 ctrl_fifo_empty3_1;
+	ZXIC_UINT32 ctrl_fifo_empty3_0;
+} DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY3_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty4_t {
+	ZXIC_UINT32 ctrl_fifo_empty4_5;
+	ZXIC_UINT32 ctrl_fifo_empty4_4;
+	ZXIC_UINT32 ctrl_fifo_empty4_3;
+	ZXIC_UINT32 ctrl_fifo_empty4_2;
+	ZXIC_UINT32 ctrl_fifo_empty4_1;
+	ZXIC_UINT32 ctrl_fifo_empty4_0;
+} DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY4_T;
+
+typedef struct dpp_smmu0_smmu0_ctrl_fifo_empty5_t {
+	ZXIC_UINT32 ctrl_fifo_empty5_1;
+	ZXIC_UINT32 ctrl_fifo_empty5_0;
+} DPP_SMMU0_SMMU0_CTRL_FIFO_EMPTY5_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty0_t {
+	ZXIC_UINT32 kschd_fifo_empty0;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY0_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty1_t {
+	ZXIC_UINT32 kschd_fifo_empty1;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY1_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty2_t {
+	ZXIC_UINT32 kschd_fifo_empty2;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY2_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty3_t {
+	ZXIC_UINT32 kschd_fifo_empty3;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY3_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty4_t {
+	ZXIC_UINT32 kschd_fifo_empty4;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY4_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty5_t {
+	ZXIC_UINT32 kschd_fifo_empty5;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY5_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty6_t {
+	ZXIC_UINT32 kschd_fifo_empty6;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY6_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty7_t {
+	ZXIC_UINT32 kschd_fifo_empty7;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY7_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty8_t {
+	ZXIC_UINT32 kschd_fifo_empty8;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY8_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty9_t {
+	ZXIC_UINT32 kschd_fifo_empty9;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY9_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty10_t {
+	ZXIC_UINT32 kschd_fifo_empty10;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY10_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty11_t {
+	ZXIC_UINT32 kschd_fifo_empty11;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY11_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty12_t {
+	ZXIC_UINT32 kschd_fifo_empty12;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY12_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty13_t {
+	ZXIC_UINT32 kschd_fifo_empty13;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY13_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty14_t {
+	ZXIC_UINT32 kschd_fifo_empty14;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY14_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty15_t {
+	ZXIC_UINT32 kschd_fifo_empty15;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY15_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty16_t {
+	ZXIC_UINT32 kschd_fifo_empty16;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY16_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty17_t {
+	ZXIC_UINT32 kschd_fifo_empty17;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY17_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty18_t {
+	ZXIC_UINT32 kschd_fifo_empty18;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY18_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty19_t {
+	ZXIC_UINT32 kschd_fifo_empty19;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY19_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty20_t {
+	ZXIC_UINT32 kschd_fifo_empty20;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY20_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty21_t {
+	ZXIC_UINT32 kschd_fifo_empty21;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY21_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty22_t {
+	ZXIC_UINT32 kschd_fifo_empty22;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY22_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty23_t {
+	ZXIC_UINT32 kschd_fifo_empty23;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY23_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty24_t {
+	ZXIC_UINT32 kschd_fifo_empty24;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY24_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty25_t {
+	ZXIC_UINT32 kschd_fifo_empty25;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY25_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty26_t {
+	ZXIC_UINT32 kschd_fifo_empty26;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY26_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty27_t {
+	ZXIC_UINT32 kschd_fifo_empty27;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY27_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty28_t {
+	ZXIC_UINT32 kschd_fifo_empty28;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY28_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty29_t {
+	ZXIC_UINT32 kschd_fifo_empty29;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY29_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty30_t {
+	ZXIC_UINT32 kschd_fifo_empty30;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY30_T;
+
+typedef struct dpp_smmu0_smmu0_kschd_fifo_empty31_t {
+	ZXIC_UINT32 kschd_fifo_empty31;
+} DPP_SMMU0_SMMU0_KSCHD_FIFO_EMPTY31_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty0_t {
+	ZXIC_UINT32 rschd_fifo_empty0;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY0_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty1_t {
+	ZXIC_UINT32 rschd_fifo_empty1;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY1_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty2_t {
+	ZXIC_UINT32 rschd_fifo_empty2;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY2_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty3_t {
+	ZXIC_UINT32 rschd_fifo_empty3;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY3_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty4_t {
+	ZXIC_UINT32 rschd_fifo_empty4;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY4_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty5_t {
+	ZXIC_UINT32 rschd_fifo_empty5;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY5_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty6_t {
+	ZXIC_UINT32 rschd_fifo_empty6;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY6_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty7_t {
+	ZXIC_UINT32 rschd_fifo_empty7;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY7_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty8_t {
+	ZXIC_UINT32 rschd_fifo_empty8;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY8_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty9_t {
+	ZXIC_UINT32 rschd_fifo_empty9;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY9_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty10_t {
+	ZXIC_UINT32 rschd_fifo_empty10;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY10_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty11_t {
+	ZXIC_UINT32 rschd_fifo_empty11;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY11_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty12_t {
+	ZXIC_UINT32 rschd_fifo_empty12;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY12_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty13_t {
+	ZXIC_UINT32 rschd_fifo_empty13;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY13_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty14_t {
+	ZXIC_UINT32 rschd_fifo_empty14;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY14_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty15_t {
+	ZXIC_UINT32 rschd_fifo_empty15;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY15_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty16_t {
+	ZXIC_UINT32 rschd_fifo_empty16;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY16_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty17_t {
+	ZXIC_UINT32 rschd_fifo_empty17;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY17_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty18_t {
+	ZXIC_UINT32 rschd_fifo_empty18;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY18_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty19_t {
+	ZXIC_UINT32 rschd_fifo_empty19;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY19_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty20_t {
+	ZXIC_UINT32 rschd_fifo_empty20;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY20_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty21_t {
+	ZXIC_UINT32 rschd_fifo_empty21;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY21_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty22_t {
+	ZXIC_UINT32 rschd_fifo_empty22;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY22_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty23_t {
+	ZXIC_UINT32 rschd_fifo_empty23;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY23_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty24_t {
+	ZXIC_UINT32 rschd_fifo_empty24;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY24_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty25_t {
+	ZXIC_UINT32 rschd_fifo_empty25;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY25_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty26_t {
+	ZXIC_UINT32 rschd_fifo_empty26;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY26_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty27_t {
+	ZXIC_UINT32 rschd_fifo_empty27;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY27_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty28_t {
+	ZXIC_UINT32 rschd_fifo_empty28;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY28_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty29_t {
+	ZXIC_UINT32 rschd_fifo_empty29;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY29_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty30_t {
+	ZXIC_UINT32 rschd_fifo_empty30;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY30_T;
+
+typedef struct dpp_smmu0_smmu0_rschd_fifo_empty31_t {
+	ZXIC_UINT32 rschd_fifo_empty31;
+} DPP_SMMU0_SMMU0_RSCHD_FIFO_EMPTY31_T;
+
+typedef struct dpp_smmu0_smmu0_ept_flag_t {
+	ZXIC_UINT32 ept_flag8;
+	ZXIC_UINT32 ept_flag7;
+	ZXIC_UINT32 ept_flag6;
+	ZXIC_UINT32 ept_flag5;
+	ZXIC_UINT32 ept_flag4;
+	ZXIC_UINT32 ept_flag3;
+	ZXIC_UINT32 ept_flag2;
+	ZXIC_UINT32 ept_flag1;
+	ZXIC_UINT32 ept_flag0;
+} DPP_SMMU0_SMMU0_EPT_FLAG_T;
+
+typedef struct dpp_smmu0_smmu0_ppu_soft_rst_t {
+	ZXIC_UINT32 ppu_soft_rst;
+} DPP_SMMU0_SMMU0_PPU_SOFT_RST_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_as_mac_age_fc_cnt_t {
+	ZXIC_UINT32 smmu0_as_mac_age_fc_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_AS_MAC_AGE_FC_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_marc_se_parser_fc_cnt_t {
+	ZXIC_UINT32 smmu0_marc_se_parser_fc_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_MARC_SE_PARSER_FC_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_wr_arb_cpu_fc_cnt_t {
+	ZXIC_UINT32 wr_arb_cpu_fc_cnt;
+} DPP_SMMU0_SMMU0_WR_ARB_CPU_FC_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_lpm_as_fc_cnt_t {
+	ZXIC_UINT32 smmu0_lpm_as_fc_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_LPM_AS_FC_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_lpm_as_smmu0_fc_cnt_t {
+	ZXIC_UINT32 lpm_as_smmu0_fc_cnt;
+} DPP_SMMU0_SMMU0_LPM_AS_SMMU0_FC_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_etcam1_0_as_fc_cnt_t {
+	ZXIC_UINT32 smmu0_etcam1_0_as_fc_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_FC_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_as_etcam1_0_smmu0_fc_cnt_t {
+	ZXIC_UINT32 as_etcam1_0_smmu0_fc_cnt;
+} DPP_SMMU0_SMMU0_AS_ETCAM1_0_SMMU0_FC_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_ppu_mcast_fc_cnt_t {
+	ZXIC_UINT32 smmu0_ppu_mcast_fc_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_PPU_MCAST_FC_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_ppu_smmu0_mcast_fc_cnt_t {
+	ZXIC_UINT32 ppu_smmu0_mcast_fc_cnt;
+} DPP_SMMU0_SMMU0_PPU_SMMU0_MCAST_FC_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_odma_smmu0_tdm_fc_rsp_fc_cnt_t {
+	ZXIC_UINT32 odma_smmu0_tdm_fc_rsp_fc_cnt;
+} DPP_SMMU0_SMMU0_ODMA_SMMU0_TDM_FC_RSP_FC_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_odma_tdm_fc_key_fc_cnt_t {
+	ZXIC_UINT32 smmu0_odma_tdm_fc_key_fc_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_ODMA_TDM_FC_KEY_FC_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_odma_fc_cnt_t {
+	ZXIC_UINT32 smmu0_odma_fc_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_ODMA_FC_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_cfg_tab_rd_fc_cnt_t {
+	ZXIC_UINT32 smmu0_cfg_tab_rd_fc_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_CFG_TAB_RD_FC_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_stat_fc15_0_cnt_t {
+	ZXIC_UINT32 smmu0_stat_fc15_0_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_STAT_FC15_0_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_stat_smmu0_fc15_0_cnt_t {
+	ZXIC_UINT32 stat_smmu0_fc15_0_cnt;
+} DPP_SMMU0_SMMU0_STAT_SMMU0_FC15_0_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_ppu_mex5_0_fc_cnt_t {
+	ZXIC_UINT32 smmu0_ppu_mex5_0_fc_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_PPU_MEX5_0_FC_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_ppu_smmu0_mex5_0_fc_cnt_t {
+	ZXIC_UINT32 ppu_smmu0_mex5_0_fc_cnt;
+} DPP_SMMU0_SMMU0_PPU_SMMU0_MEX5_0_FC_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_as_smmu0_mac_age_req_cnt_t {
+	ZXIC_UINT32 as_smmu0_mac_age_req_cnt;
+} DPP_SMMU0_SMMU0_AS_SMMU0_MAC_AGE_REQ_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_se_parser_smmu0_marc_key_cnt_t {
+	ZXIC_UINT32 se_parser_smmu0_marc_key_cnt;
+} DPP_SMMU0_SMMU0_SE_PARSER_SMMU0_MARC_KEY_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_cpu_ind_rdat_cnt_t {
+	ZXIC_UINT32 cpu_ind_rdat_cnt;
+} DPP_SMMU0_SMMU0_CPU_IND_RDAT_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_cpu_ind_rd_req_cnt_t {
+	ZXIC_UINT32 cpu_ind_rd_req_cnt;
+} DPP_SMMU0_SMMU0_CPU_IND_RD_REQ_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_cpu_ind_wr_req_cnt_t {
+	ZXIC_UINT32 cpu_ind_wr_req_cnt;
+} DPP_SMMU0_SMMU0_CPU_IND_WR_REQ_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_plcr_rsp0_cnt_t {
+	ZXIC_UINT32 smmu0_plcr_rsp0_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_PLCR_RSP0_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_plcr_smmu0_req0_cnt_t {
+	ZXIC_UINT32 plcr_smmu0_req0_cnt;
+} DPP_SMMU0_SMMU0_PLCR_SMMU0_REQ0_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_lpm_as_rsp_cnt_t {
+	ZXIC_UINT32 smmu0_lpm_as_rsp_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_LPM_AS_RSP_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_lpm_as_smmu0_req_cnt_t {
+	ZXIC_UINT32 lpm_as_smmu0_req_cnt;
+} DPP_SMMU0_SMMU0_LPM_AS_SMMU0_REQ_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_etcam1_0_as_rsp_cnt_t {
+	ZXIC_UINT32 smmu0_etcam1_0_as_rsp_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_RSP_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_etcam1_0_as_smmu0_req_cnt_t {
+	ZXIC_UINT32 etcam1_0_as_smmu0_req_cnt;
+} DPP_SMMU0_SMMU0_ETCAM1_0_AS_SMMU0_REQ_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_ppu_mcast_rsp_cnt_t {
+	ZXIC_UINT32 smmu0_ppu_mcast_rsp_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_PPU_MCAST_RSP_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_ppu_smmu0_mcast_key_cnt_t {
+	ZXIC_UINT32 ppu_smmu0_mcast_key_cnt;
+} DPP_SMMU0_SMMU0_PPU_SMMU0_MCAST_KEY_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_odma_tdm_mc_rsp_cnt_t {
+	ZXIC_UINT32 smmu0_odma_tdm_mc_rsp_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_ODMA_TDM_MC_RSP_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_odma_smmu0_tdm_mc_key_cnt_t {
+	ZXIC_UINT32 odma_smmu0_tdm_mc_key_cnt;
+} DPP_SMMU0_SMMU0_ODMA_SMMU0_TDM_MC_KEY_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_odma_rsp_cnt_t {
+	ZXIC_UINT32 smmu0_odma_rsp_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_ODMA_RSP_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_odma_smmu0_cmd_cnt_t {
+	ZXIC_UINT32 odma_smmu0_cmd_cnt;
+} DPP_SMMU0_SMMU0_ODMA_SMMU0_CMD_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_cfg_tab_rdat_cnt_t {
+	ZXIC_UINT32 smmu0_cfg_tab_rdat_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_CFG_TAB_RDAT_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_cfg_smmu0_tab_rd_cnt_t {
+	ZXIC_UINT32 cfg_smmu0_tab_rd_cnt;
+} DPP_SMMU0_SMMU0_CFG_SMMU0_TAB_RD_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_stat_rsp15_0_cnt_t {
+	ZXIC_UINT32 smmu0_stat_rsp15_0_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_STAT_RSP15_0_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_stat_smmu0_req15_0_cnt_t {
+	ZXIC_UINT32 stat_smmu0_req15_0_cnt;
+} DPP_SMMU0_SMMU0_STAT_SMMU0_REQ15_0_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_smmu0_ppu_mex5_0_rsp_cnt_t {
+	ZXIC_UINT32 smmu0_ppu_mex5_0_rsp_cnt;
+} DPP_SMMU0_SMMU0_SMMU0_PPU_MEX5_0_RSP_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_ppu_smmu0_mex5_0_key_cnt_t {
+	ZXIC_UINT32 ppu_smmu0_mex5_0_key_cnt;
+} DPP_SMMU0_SMMU0_PPU_SMMU0_MEX5_0_KEY_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_ftm_stat_smmu0_req0_cnt_t {
+	ZXIC_UINT32 ftm_stat_smmu0_req0_cnt;
+} DPP_SMMU0_SMMU0_FTM_STAT_SMMU0_REQ0_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_ftm_stat_smmu0_req1_cnt_t {
+	ZXIC_UINT32 ftm_stat_smmu0_req1_cnt;
+} DPP_SMMU0_SMMU0_FTM_STAT_SMMU0_REQ1_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_etm_stat_smmu0_req0_cnt_t {
+	ZXIC_UINT32 etm_stat_smmu0_req0_cnt;
+} DPP_SMMU0_SMMU0_ETM_STAT_SMMU0_REQ0_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_etm_stat_smmu0_req1_cnt_t {
+	ZXIC_UINT32 etm_stat_smmu0_req1_cnt;
+} DPP_SMMU0_SMMU0_ETM_STAT_SMMU0_REQ1_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_req_eram0_31_rd_cnt_t {
+	ZXIC_UINT32 req_eram0_31_rd_cnt;
+} DPP_SMMU0_SMMU0_REQ_ERAM0_31_RD_CNT_T;
+
+typedef struct dpp_smmu0_smmu0_req_eram0_31_wr_cnt_t {
+	ZXIC_UINT32 req_eram0_31_wr_cnt;
+} DPP_SMMU0_SMMU0_REQ_ERAM0_31_WR_CNT_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu14k_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu14k_reg.h
index 734cbfb99ea1e4fdb88ea0a9acc858304086c6f4..d4f524b3f1df58c23ced87beaa6da0abcf1295a2 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu14k_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu14k_reg.h
@@ -3,236 +3,202 @@
 #define _DPP_SMMU14K_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_smmu14k_se_smmu1_hash0_tbl0_cfg_t
-{
-    ZXIC_UINT32 hash0_tbl0_len;
-    ZXIC_UINT32 hash0_tbl0_ecc_en;
-    ZXIC_UINT32 hash0_tbl0_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH0_TBL0_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash0_tbl1_cfg_t
-{
-    ZXIC_UINT32 hash0_tbl1_len;
-    ZXIC_UINT32 hash0_tbl1_ecc_en;
-    ZXIC_UINT32 hash0_tbl1_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH0_TBL1_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash0_tbl2_cfg_t
-{
-    ZXIC_UINT32 hash0_tbl2_len;
-    ZXIC_UINT32 hash0_tbl2_ecc_en;
-    ZXIC_UINT32 hash0_tbl2_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH0_TBL2_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash0_tbl3_cfg_t
-{
-    ZXIC_UINT32 hash0_tbl3_len;
-    ZXIC_UINT32 hash0_tbl3_ecc_en;
-    ZXIC_UINT32 hash0_tbl3_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH0_TBL3_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash0_tbl4_cfg_t
-{
-    ZXIC_UINT32 hash0_tbl4_len;
-    ZXIC_UINT32 hash0_tbl4_ecc_en;
-    ZXIC_UINT32 hash0_tbl4_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH0_TBL4_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash0_tbl5_cfg_t
-{
-    ZXIC_UINT32 hash0_tbl5_len;
-    ZXIC_UINT32 hash0_tbl5_ecc_en;
-    ZXIC_UINT32 hash0_tbl5_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH0_TBL5_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash0_tbl6_cfg_t
-{
-    ZXIC_UINT32 hash0_tbl6_len;
-    ZXIC_UINT32 hash0_tbl6_ecc_en;
-    ZXIC_UINT32 hash0_tbl6_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH0_TBL6_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash0_tbl7_cfg_t
-{
-    ZXIC_UINT32 hash0_tbl7_len;
-    ZXIC_UINT32 hash0_tbl7_ecc_en;
-    ZXIC_UINT32 hash0_tbl7_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH0_TBL7_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash1_tbl0_cfg_t
-{
-    ZXIC_UINT32 hash1_tbl0_len;
-    ZXIC_UINT32 hash1_tbl0_ecc_en;
-    ZXIC_UINT32 hash1_tbl0_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH1_TBL0_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash1_tbl1_cfg_t
-{
-    ZXIC_UINT32 hash1_tbl1_len;
-    ZXIC_UINT32 hash1_tbl1_ecc_en;
-    ZXIC_UINT32 hash1_tbl1_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH1_TBL1_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash1_tbl2_cfg_t
-{
-    ZXIC_UINT32 hash1_tbl2_len;
-    ZXIC_UINT32 hash1_tbl2_ecc_en;
-    ZXIC_UINT32 hash1_tbl2_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH1_TBL2_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash1_tbl3_cfg_t
-{
-    ZXIC_UINT32 hash1_tbl3_len;
-    ZXIC_UINT32 hash1_tbl3_ecc_en;
-    ZXIC_UINT32 hash1_tbl3_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH1_TBL3_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash1_tbl4_cfg_t
-{
-    ZXIC_UINT32 hash1_tbl4_len;
-    ZXIC_UINT32 hash1_tbl4_ecc_en;
-    ZXIC_UINT32 hash1_tbl4_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH1_TBL4_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash1_tbl5_cfg_t
-{
-    ZXIC_UINT32 hash1_tbl5_len;
-    ZXIC_UINT32 hash1_tbl5_ecc_en;
-    ZXIC_UINT32 hash1_tbl5_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH1_TBL5_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash1_tbl6_cfg_t
-{
-    ZXIC_UINT32 hash1_tbl6_len;
-    ZXIC_UINT32 hash1_tbl6_ecc_en;
-    ZXIC_UINT32 hash1_tbl6_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH1_TBL6_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash1_tbl7_cfg_t
-{
-    ZXIC_UINT32 hash1_tbl7_len;
-    ZXIC_UINT32 hash1_tbl7_ecc_en;
-    ZXIC_UINT32 hash1_tbl7_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH1_TBL7_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash2_tbl0_cfg_t
-{
-    ZXIC_UINT32 hash2_tbl0_len;
-    ZXIC_UINT32 hash2_tbl0_ecc_en;
-    ZXIC_UINT32 hash2_tbl0_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH2_TBL0_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash2_tbl1_cfg_t
-{
-    ZXIC_UINT32 hash2_tbl1_len;
-    ZXIC_UINT32 hash2_tbl1_ecc_en;
-    ZXIC_UINT32 hash2_tbl1_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH2_TBL1_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash2_tbl2_cfg_t
-{
-    ZXIC_UINT32 hash2_tbl2_len;
-    ZXIC_UINT32 hash2_tbl2_ecc_en;
-    ZXIC_UINT32 hash2_tbl2_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH2_TBL2_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash2_tbl3_cfg_t
-{
-    ZXIC_UINT32 hash2_tbl3_len;
-    ZXIC_UINT32 hash2_tbl3_ecc_en;
-    ZXIC_UINT32 hash2_tbl3_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH2_TBL3_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash2_tbl4_cfg_t
-{
-    ZXIC_UINT32 hash2_tbl4_len;
-    ZXIC_UINT32 hash2_tbl4_ecc_en;
-    ZXIC_UINT32 hash2_tbl4_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH2_TBL4_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash2_tbl5_cfg_t
-{
-    ZXIC_UINT32 hash2_tbl5_len;
-    ZXIC_UINT32 hash2_tbl5_ecc_en;
-    ZXIC_UINT32 hash2_tbl5_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH2_TBL5_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash2_tbl6_cfg_t
-{
-    ZXIC_UINT32 hash2_tbl6_len;
-    ZXIC_UINT32 hash2_tbl6_ecc_en;
-    ZXIC_UINT32 hash2_tbl6_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH2_TBL6_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash2_tbl7_cfg_t
-{
-    ZXIC_UINT32 hash2_tbl7_len;
-    ZXIC_UINT32 hash2_tbl7_ecc_en;
-    ZXIC_UINT32 hash2_tbl7_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH2_TBL7_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash3_tbl0_cfg_t
-{
-    ZXIC_UINT32 hash3_tbl0_len;
-    ZXIC_UINT32 hash3_tbl0_ecc_en;
-    ZXIC_UINT32 hash3_tbl0_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH3_TBL0_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash3_tbl1_cfg_t
-{
-    ZXIC_UINT32 hash3_tbl1_len;
-    ZXIC_UINT32 hash3_tbl1_ecc_en;
-    ZXIC_UINT32 hash3_tbl1_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH3_TBL1_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash3_tbl2_cfg_t
-{
-    ZXIC_UINT32 hash3_tbl2_len;
-    ZXIC_UINT32 hash3_tbl2_ecc_en;
-    ZXIC_UINT32 hash3_tbl2_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH3_TBL2_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash3_tbl3_cfg_t
-{
-    ZXIC_UINT32 hash3_tbl3_len;
-    ZXIC_UINT32 hash3_tbl3_ecc_en;
-    ZXIC_UINT32 hash3_tbl3_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH3_TBL3_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash3_tbl4_cfg_t
-{
-    ZXIC_UINT32 hash3_tbl4_len;
-    ZXIC_UINT32 hash3_tbl4_ecc_en;
-    ZXIC_UINT32 hash3_tbl4_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH3_TBL4_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash3_tbl5_cfg_t
-{
-    ZXIC_UINT32 hash3_tbl5_len;
-    ZXIC_UINT32 hash3_tbl5_ecc_en;
-    ZXIC_UINT32 hash3_tbl5_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH3_TBL5_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash3_tbl6_cfg_t
-{
-    ZXIC_UINT32 hash3_tbl6_len;
-    ZXIC_UINT32 hash3_tbl6_ecc_en;
-    ZXIC_UINT32 hash3_tbl6_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH3_TBL6_CFG_T;
-
-typedef struct dpp_smmu14k_se_smmu1_hash3_tbl7_cfg_t
-{
-    ZXIC_UINT32 hash3_tbl7_len;
-    ZXIC_UINT32 hash3_tbl7_ecc_en;
-    ZXIC_UINT32 hash3_tbl7_baddr;
-}DPP_SMMU14K_SE_SMMU1_HASH3_TBL7_CFG_T;
-
+typedef struct dpp_smmu14k_se_smmu1_hash0_tbl0_cfg_t {
+	ZXIC_UINT32 hash0_tbl0_len;
+	ZXIC_UINT32 hash0_tbl0_ecc_en;
+	ZXIC_UINT32 hash0_tbl0_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH0_TBL0_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash0_tbl1_cfg_t {
+	ZXIC_UINT32 hash0_tbl1_len;
+	ZXIC_UINT32 hash0_tbl1_ecc_en;
+	ZXIC_UINT32 hash0_tbl1_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH0_TBL1_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash0_tbl2_cfg_t {
+	ZXIC_UINT32 hash0_tbl2_len;
+	ZXIC_UINT32 hash0_tbl2_ecc_en;
+	ZXIC_UINT32 hash0_tbl2_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH0_TBL2_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash0_tbl3_cfg_t {
+	ZXIC_UINT32 hash0_tbl3_len;
+	ZXIC_UINT32 hash0_tbl3_ecc_en;
+	ZXIC_UINT32 hash0_tbl3_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH0_TBL3_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash0_tbl4_cfg_t {
+	ZXIC_UINT32 hash0_tbl4_len;
+	ZXIC_UINT32 hash0_tbl4_ecc_en;
+	ZXIC_UINT32 hash0_tbl4_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH0_TBL4_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash0_tbl5_cfg_t {
+	ZXIC_UINT32 hash0_tbl5_len;
+	ZXIC_UINT32 hash0_tbl5_ecc_en;
+	ZXIC_UINT32 hash0_tbl5_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH0_TBL5_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash0_tbl6_cfg_t {
+	ZXIC_UINT32 hash0_tbl6_len;
+	ZXIC_UINT32 hash0_tbl6_ecc_en;
+	ZXIC_UINT32 hash0_tbl6_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH0_TBL6_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash0_tbl7_cfg_t {
+	ZXIC_UINT32 hash0_tbl7_len;
+	ZXIC_UINT32 hash0_tbl7_ecc_en;
+	ZXIC_UINT32 hash0_tbl7_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH0_TBL7_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash1_tbl0_cfg_t {
+	ZXIC_UINT32 hash1_tbl0_len;
+	ZXIC_UINT32 hash1_tbl0_ecc_en;
+	ZXIC_UINT32 hash1_tbl0_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH1_TBL0_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash1_tbl1_cfg_t {
+	ZXIC_UINT32 hash1_tbl1_len;
+	ZXIC_UINT32 hash1_tbl1_ecc_en;
+	ZXIC_UINT32 hash1_tbl1_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH1_TBL1_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash1_tbl2_cfg_t {
+	ZXIC_UINT32 hash1_tbl2_len;
+	ZXIC_UINT32 hash1_tbl2_ecc_en;
+	ZXIC_UINT32 hash1_tbl2_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH1_TBL2_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash1_tbl3_cfg_t {
+	ZXIC_UINT32 hash1_tbl3_len;
+	ZXIC_UINT32 hash1_tbl3_ecc_en;
+	ZXIC_UINT32 hash1_tbl3_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH1_TBL3_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash1_tbl4_cfg_t {
+	ZXIC_UINT32 hash1_tbl4_len;
+	ZXIC_UINT32 hash1_tbl4_ecc_en;
+	ZXIC_UINT32 hash1_tbl4_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH1_TBL4_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash1_tbl5_cfg_t {
+	ZXIC_UINT32 hash1_tbl5_len;
+	ZXIC_UINT32 hash1_tbl5_ecc_en;
+	ZXIC_UINT32 hash1_tbl5_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH1_TBL5_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash1_tbl6_cfg_t {
+	ZXIC_UINT32 hash1_tbl6_len;
+	ZXIC_UINT32 hash1_tbl6_ecc_en;
+	ZXIC_UINT32 hash1_tbl6_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH1_TBL6_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash1_tbl7_cfg_t {
+	ZXIC_UINT32 hash1_tbl7_len;
+	ZXIC_UINT32 hash1_tbl7_ecc_en;
+	ZXIC_UINT32 hash1_tbl7_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH1_TBL7_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash2_tbl0_cfg_t {
+	ZXIC_UINT32 hash2_tbl0_len;
+	ZXIC_UINT32 hash2_tbl0_ecc_en;
+	ZXIC_UINT32 hash2_tbl0_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH2_TBL0_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash2_tbl1_cfg_t {
+	ZXIC_UINT32 hash2_tbl1_len;
+	ZXIC_UINT32 hash2_tbl1_ecc_en;
+	ZXIC_UINT32 hash2_tbl1_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH2_TBL1_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash2_tbl2_cfg_t {
+	ZXIC_UINT32 hash2_tbl2_len;
+	ZXIC_UINT32 hash2_tbl2_ecc_en;
+	ZXIC_UINT32 hash2_tbl2_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH2_TBL2_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash2_tbl3_cfg_t {
+	ZXIC_UINT32 hash2_tbl3_len;
+	ZXIC_UINT32 hash2_tbl3_ecc_en;
+	ZXIC_UINT32 hash2_tbl3_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH2_TBL3_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash2_tbl4_cfg_t {
+	ZXIC_UINT32 hash2_tbl4_len;
+	ZXIC_UINT32 hash2_tbl4_ecc_en;
+	ZXIC_UINT32 hash2_tbl4_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH2_TBL4_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash2_tbl5_cfg_t {
+	ZXIC_UINT32 hash2_tbl5_len;
+	ZXIC_UINT32 hash2_tbl5_ecc_en;
+	ZXIC_UINT32 hash2_tbl5_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH2_TBL5_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash2_tbl6_cfg_t {
+	ZXIC_UINT32 hash2_tbl6_len;
+	ZXIC_UINT32 hash2_tbl6_ecc_en;
+	ZXIC_UINT32 hash2_tbl6_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH2_TBL6_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash2_tbl7_cfg_t {
+	ZXIC_UINT32 hash2_tbl7_len;
+	ZXIC_UINT32 hash2_tbl7_ecc_en;
+	ZXIC_UINT32 hash2_tbl7_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH2_TBL7_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash3_tbl0_cfg_t {
+	ZXIC_UINT32 hash3_tbl0_len;
+	ZXIC_UINT32 hash3_tbl0_ecc_en;
+	ZXIC_UINT32 hash3_tbl0_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH3_TBL0_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash3_tbl1_cfg_t {
+	ZXIC_UINT32 hash3_tbl1_len;
+	ZXIC_UINT32 hash3_tbl1_ecc_en;
+	ZXIC_UINT32 hash3_tbl1_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH3_TBL1_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash3_tbl2_cfg_t {
+	ZXIC_UINT32 hash3_tbl2_len;
+	ZXIC_UINT32 hash3_tbl2_ecc_en;
+	ZXIC_UINT32 hash3_tbl2_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH3_TBL2_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash3_tbl3_cfg_t {
+	ZXIC_UINT32 hash3_tbl3_len;
+	ZXIC_UINT32 hash3_tbl3_ecc_en;
+	ZXIC_UINT32 hash3_tbl3_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH3_TBL3_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash3_tbl4_cfg_t {
+	ZXIC_UINT32 hash3_tbl4_len;
+	ZXIC_UINT32 hash3_tbl4_ecc_en;
+	ZXIC_UINT32 hash3_tbl4_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH3_TBL4_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash3_tbl5_cfg_t {
+	ZXIC_UINT32 hash3_tbl5_len;
+	ZXIC_UINT32 hash3_tbl5_ecc_en;
+	ZXIC_UINT32 hash3_tbl5_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH3_TBL5_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash3_tbl6_cfg_t {
+	ZXIC_UINT32 hash3_tbl6_len;
+	ZXIC_UINT32 hash3_tbl6_ecc_en;
+	ZXIC_UINT32 hash3_tbl6_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH3_TBL6_CFG_T;
+
+typedef struct dpp_smmu14k_se_smmu1_hash3_tbl7_cfg_t {
+	ZXIC_UINT32 hash3_tbl7_len;
+	ZXIC_UINT32 hash3_tbl7_ecc_en;
+	ZXIC_UINT32 hash3_tbl7_baddr;
+} DPP_SMMU14K_SE_SMMU1_HASH3_TBL7_CFG_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu1_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu1_reg.h
index 72ddae504a12a8691e695514ce1555717911058e..966c80e7eddca8d9dfa648edcd4309fea23bb763 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu1_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_smmu1_reg.h
@@ -3,1325 +3,1074 @@
 #define _DPP_SMMU1_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_se_smmu1_ddr_wdat0_t
-{
-    ZXIC_UINT32 ddr_wdat0;
-}DPP_SE_SMMU1_DDR_WDAT0_T;
-
-typedef struct dpp_se_smmu1_dir_arbi_ser_rpful_t
-{
-    ZXIC_UINT32 dir_arbi_ser_rpful;
-}DPP_SE_SMMU1_DIR_ARBI_SER_RPFUL_T;
-
-typedef struct dpp_se_smmu1_cfg_wr_arbi_pful2_t
-{
-    ZXIC_UINT32 hash_wr_pful;
-    ZXIC_UINT32 dir_wr_pful;
-}DPP_SE_SMMU1_CFG_WR_ARBI_PFUL2_T;
-
-typedef struct dpp_se_smmu1_etm_tbl_cfg_t
-{
-    ZXIC_UINT32 etm_baddr;
-}DPP_SE_SMMU1_ETM_TBL_CFG_T;
-
-typedef struct dpp_se_smmu1_cfg_cash_addr_pful_t
-{
-    ZXIC_UINT32 cfg_cash_addr_pful;
-}DPP_SE_SMMU1_CFG_CASH_ADDR_PFUL_T;
-
-typedef struct dpp_se_smmu1_ctrl_rfifo_cfg_t
-{
-    ZXIC_UINT32 brst_fwft_fifo_prog_empty_assert;
-    ZXIC_UINT32 brst_fwft_fifo_prog_empty_negate;
-    ZXIC_UINT32 brst_fwft_fifo_prog_full_assert;
-    ZXIC_UINT32 brst_fwft_fifo_prog_full_negate;
-}DPP_SE_SMMU1_CTRL_RFIFO_CFG_T;
-
-typedef struct dpp_se_smmu1_cache_req_fifo_cfg_t
-{
-    ZXIC_UINT32 srch_fifo_pfull_assert;
-    ZXIC_UINT32 srch_fifo_pfull_negate;
-}DPP_SE_SMMU1_CACHE_REQ_FIFO_CFG_T;
-
-typedef struct dpp_se_smmu1_ddr_wdat1_t
-{
-    ZXIC_UINT32 ddr_wdat1;
-}DPP_SE_SMMU1_DDR_WDAT1_T;
-
-typedef struct dpp_se_smmu1_ddr_wdat2_t
-{
-    ZXIC_UINT32 ddr_wdat2;
-}DPP_SE_SMMU1_DDR_WDAT2_T;
-
-typedef struct dpp_se_smmu1_ddr_wdat3_t
-{
-    ZXIC_UINT32 ddr_wdat3;
-}DPP_SE_SMMU1_DDR_WDAT3_T;
-
-typedef struct dpp_se_smmu1_ddr_wdat4_t
-{
-    ZXIC_UINT32 ddr_wdat4;
-}DPP_SE_SMMU1_DDR_WDAT4_T;
-
-typedef struct dpp_se_smmu1_ddr_wdat5_t
-{
-    ZXIC_UINT32 ddr_wdat5;
-}DPP_SE_SMMU1_DDR_WDAT5_T;
-
-typedef struct dpp_se_smmu1_ddr_wdat6_t
-{
-    ZXIC_UINT32 ddr_wdat6;
-}DPP_SE_SMMU1_DDR_WDAT6_T;
-
-typedef struct dpp_se_smmu1_ddr_wdat7_t
-{
-    ZXIC_UINT32 ddr_wdat7;
-}DPP_SE_SMMU1_DDR_WDAT7_T;
-
-typedef struct dpp_se_smmu1_ddr_wdat8_t
-{
-    ZXIC_UINT32 ddr_wdat8;
-}DPP_SE_SMMU1_DDR_WDAT8_T;
-
-typedef struct dpp_se_smmu1_ddr_wdat9_t
-{
-    ZXIC_UINT32 ddr_wdat9;
-}DPP_SE_SMMU1_DDR_WDAT9_T;
-
-typedef struct dpp_se_smmu1_ddr_wdat10_t
-{
-    ZXIC_UINT32 ddr_wdat10;
-}DPP_SE_SMMU1_DDR_WDAT10_T;
-
-typedef struct dpp_se_smmu1_ddr_wdat11_t
-{
-    ZXIC_UINT32 ddr_wdat11;
-}DPP_SE_SMMU1_DDR_WDAT11_T;
-
-typedef struct dpp_se_smmu1_ddr_wdat12_t
-{
-    ZXIC_UINT32 ddr_wdat12;
-}DPP_SE_SMMU1_DDR_WDAT12_T;
-
-typedef struct dpp_se_smmu1_ddr_wdat13_t
-{
-    ZXIC_UINT32 ddr_wdat13;
-}DPP_SE_SMMU1_DDR_WDAT13_T;
-
-typedef struct dpp_se_smmu1_ddr_wdat14_t
-{
-    ZXIC_UINT32 ddr_wdat14;
-}DPP_SE_SMMU1_DDR_WDAT14_T;
-
-typedef struct dpp_se_smmu1_ddr_wdat15_t
-{
-    ZXIC_UINT32 ddr_wdat15;
-}DPP_SE_SMMU1_DDR_WDAT15_T;
-
-typedef struct dpp_se_smmu1_cnt_stat_cache_en_t
-{
-    ZXIC_UINT32 cnt_stat_cache_en;
-}DPP_SE_SMMU1_CNT_STAT_CACHE_EN_T;
-
-typedef struct dpp_se_smmu1_cnt_stat_cache_clr_t
-{
-    ZXIC_UINT32 cnt_stat_cache_clr;
-}DPP_SE_SMMU1_CNT_STAT_CACHE_CLR_T;
-
-typedef struct dpp_se_smmu1_cnt_stat_cache_req_63_32_t
-{
-    ZXIC_UINT32 cnt_stat_cache_req_63_32;
-}DPP_SE_SMMU1_CNT_STAT_CACHE_REQ_63_32_T;
-
-typedef struct dpp_se_smmu1_cnt_stat_cache_req_31_0_t
-{
-    ZXIC_UINT32 cnt_stat_cache_req_31_0;
-}DPP_SE_SMMU1_CNT_STAT_CACHE_REQ_31_0_T;
-
-typedef struct dpp_se_smmu1_cnt_stat_cache_hit_63_32_t
-{
-    ZXIC_UINT32 cnt_stat_cache_hit_63_32;
-}DPP_SE_SMMU1_CNT_STAT_CACHE_HIT_63_32_T;
-
-typedef struct dpp_se_smmu1_cnt_stat_cache_hit_31_0_t
-{
-    ZXIC_UINT32 cnt_stat_cache_hit_31_0;
-}DPP_SE_SMMU1_CNT_STAT_CACHE_HIT_31_0_T;
-
-typedef struct dpp_se_smmu1_ddr_cmd0_t
-{
-    ZXIC_UINT32 ecc_en;
-    ZXIC_UINT32 rw_len;
-    ZXIC_UINT32 baddr;
-}DPP_SE_SMMU1_DDR_CMD0_T;
-
-typedef struct dpp_se_smmu1_info_addr_t
-{
-    ZXIC_UINT32 info_addr;
-}DPP_SE_SMMU1_INFO_ADDR_T;
-
-typedef struct dpp_se_smmu1_ddr_cmd1_t
-{
-    ZXIC_UINT32 rw_flag;
-    ZXIC_UINT32 rw_addr;
-}DPP_SE_SMMU1_DDR_CMD1_T;
-
-typedef struct dpp_se_smmu1_clr_start_addr_t
-{
-    ZXIC_UINT32 clr_start_addr;
-}DPP_SE_SMMU1_CLR_START_ADDR_T;
-
-typedef struct dpp_se_smmu1_clr_end_addr_t
-{
-    ZXIC_UINT32 clr_end_addr;
-}DPP_SE_SMMU1_CLR_END_ADDR_T;
-
-typedef struct dpp_se_smmu1_clr_tbl_en_t
-{
-    ZXIC_UINT32 cfg_init_en;
-    ZXIC_UINT32 clr_tbl_en;
-}DPP_SE_SMMU1_CLR_TBL_EN_T;
-
-typedef struct dpp_se_smmu1_debug_cnt_mode_t
-{
-    ZXIC_UINT32 cnt_rd_mode;
-    ZXIC_UINT32 cnt_overflow_mode;
-}DPP_SE_SMMU1_DEBUG_CNT_MODE_T;
-
-typedef struct dpp_se_smmu1_init_done_t
-{
-    ZXIC_UINT32 cache_init_done;
-    ZXIC_UINT32 clr_done;
-    ZXIC_UINT32 init_ok;
-}DPP_SE_SMMU1_INIT_DONE_T;
-
-typedef struct dpp_se_smmu1_cpu_rsp_rd_done_t
-{
-    ZXIC_UINT32 cpu_rsp_rd_done;
-}DPP_SE_SMMU1_CPU_RSP_RD_DONE_T;
-
-typedef struct dpp_se_smmu1_ksch_oam_sp_en_t
-{
-    ZXIC_UINT32 ksch_oam_sp_en;
-}DPP_SE_SMMU1_KSCH_OAM_SP_EN_T;
-
-typedef struct dpp_se_smmu1_cfg_cache_en_t
-{
-    ZXIC_UINT32 cfg_cache_en;
-}DPP_SE_SMMU1_CFG_CACHE_EN_T;
-
-typedef struct dpp_se_smmu1_cache_age_en_t
-{
-    ZXIC_UINT32 cache_age_en;
-}DPP_SE_SMMU1_CACHE_AGE_EN_T;
-
-typedef struct dpp_se_smmu1_cpu_rdat0_t
-{
-    ZXIC_UINT32 cpu_rdat0;
-}DPP_SE_SMMU1_CPU_RDAT0_T;
-
-typedef struct dpp_se_smmu1_cpu_rdat1_t
-{
-    ZXIC_UINT32 cpu_rdat1;
-}DPP_SE_SMMU1_CPU_RDAT1_T;
-
-typedef struct dpp_se_smmu1_cpu_rdat2_t
-{
-    ZXIC_UINT32 cpu_rdat2;
-}DPP_SE_SMMU1_CPU_RDAT2_T;
-
-typedef struct dpp_se_smmu1_cpu_rdat3_t
-{
-    ZXIC_UINT32 cpu_rdat3;
-}DPP_SE_SMMU1_CPU_RDAT3_T;
-
-typedef struct dpp_se_smmu1_cpu_rdat4_t
-{
-    ZXIC_UINT32 cpu_rdat4;
-}DPP_SE_SMMU1_CPU_RDAT4_T;
-
-typedef struct dpp_se_smmu1_cpu_rdat5_t
-{
-    ZXIC_UINT32 cpu_rdat5;
-}DPP_SE_SMMU1_CPU_RDAT5_T;
-
-typedef struct dpp_se_smmu1_cpu_rdat6_t
-{
-    ZXIC_UINT32 cpu_rdat6;
-}DPP_SE_SMMU1_CPU_RDAT6_T;
-
-typedef struct dpp_se_smmu1_cpu_rdat7_t
-{
-    ZXIC_UINT32 cpu_rdat7;
-}DPP_SE_SMMU1_CPU_RDAT7_T;
-
-typedef struct dpp_se_smmu1_cpu_rdat8_t
-{
-    ZXIC_UINT32 cpu_rdat8;
-}DPP_SE_SMMU1_CPU_RDAT8_T;
-
-typedef struct dpp_se_smmu1_cpu_rdat9_t
-{
-    ZXIC_UINT32 cpu_rdat9;
-}DPP_SE_SMMU1_CPU_RDAT9_T;
-
-typedef struct dpp_se_smmu1_cpu_rdat10_t
-{
-    ZXIC_UINT32 cpu_rdat10;
-}DPP_SE_SMMU1_CPU_RDAT10_T;
-
-typedef struct dpp_se_smmu1_cpu_rdat11_t
-{
-    ZXIC_UINT32 cpu_rdat11;
-}DPP_SE_SMMU1_CPU_RDAT11_T;
-
-typedef struct dpp_se_smmu1_cpu_rdat12_t
-{
-    ZXIC_UINT32 cpu_rdat12;
-}DPP_SE_SMMU1_CPU_RDAT12_T;
-
-typedef struct dpp_se_smmu1_cpu_rdat13_t
-{
-    ZXIC_UINT32 cpu_rdat13;
-}DPP_SE_SMMU1_CPU_RDAT13_T;
-
-typedef struct dpp_se_smmu1_cpu_rdat14_t
-{
-    ZXIC_UINT32 cpu_rdat14;
-}DPP_SE_SMMU1_CPU_RDAT14_T;
-
-typedef struct dpp_se_smmu1_cpu_rdat15_t
-{
-    ZXIC_UINT32 cpu_rdat15;
-}DPP_SE_SMMU1_CPU_RDAT15_T;
-
-typedef struct dpp_se_smmu1_ctrl_cpu_rd_rdy_t
-{
-    ZXIC_UINT32 ctrl_cpu_rd_rdy;
-}DPP_SE_SMMU1_CTRL_CPU_RD_RDY_T;
-
-typedef struct dpp_se_smmu1_cpu_warbi_rdy_cfg_t
-{
-    ZXIC_UINT32 cpu_warbi_rdy_cfg;
-}DPP_SE_SMMU1_CPU_WARBI_RDY_CFG_T;
-
-typedef struct dpp_se_smmu1_dir_arbi_cpu_rpful_t
-{
-    ZXIC_UINT32 smmu1_cfg_rpful;
-    ZXIC_UINT32 smmu1_cfg_wpful;
-}DPP_SE_SMMU1_DIR_ARBI_CPU_RPFUL_T;
-
-typedef struct dpp_se_smmu1_dir_arbi_wpful_t
-{
-    ZXIC_UINT32 smmu1_ser_wdir_pful;
-    ZXIC_UINT32 smmu1_cfg_wdir_pful;
-}DPP_SE_SMMU1_DIR_ARBI_WPFUL_T;
-
-typedef struct dpp_se_smmu1_cfg_wr_arbi_pful0_t
-{
-    ZXIC_UINT32 arbi_out_pful;
-    ZXIC_UINT32 cpu_wr_pful;
-}DPP_SE_SMMU1_CFG_WR_ARBI_PFUL0_T;
-
-typedef struct dpp_se_smmu1_cfg_wr_arbi_pful1_t
-{
-    ZXIC_UINT32 tm_wr_pful;
-    ZXIC_UINT32 stat_wr_pful;
-}DPP_SE_SMMU1_CFG_WR_ARBI_PFUL1_T;
-
-typedef struct dpp_se_smmu1_smmu1_wdone_pful_cfg_t
-{
-    ZXIC_UINT32 smmu1_wdone_pful_cfg;
-}DPP_SE_SMMU1_SMMU1_WDONE_PFUL_CFG_T;
-
-typedef struct dpp_se_smmu1_stat_rate_cfg_cnt_t
-{
-    ZXIC_UINT32 stat_rate_cfg_cnt;
-}DPP_SE_SMMU1_STAT_RATE_CFG_CNT_T;
-
-typedef struct dpp_se_smmu1_ftm_rate_cfg_cnt_t
-{
-    ZXIC_UINT32 ftm_rate_cfg_cnt;
-}DPP_SE_SMMU1_FTM_RATE_CFG_CNT_T;
-
-typedef struct dpp_se_smmu1_etm_rate_cfg_cnt_t
-{
-    ZXIC_UINT32 etm_rate_cfg_cnt;
-}DPP_SE_SMMU1_ETM_RATE_CFG_CNT_T;
-
-typedef struct dpp_se_smmu1_dir_rate_cfg_cnt_t
-{
-    ZXIC_UINT32 dir_rate_cfg_cnt;
-}DPP_SE_SMMU1_DIR_RATE_CFG_CNT_T;
-
-typedef struct dpp_se_smmu1_hash_rate_cfg_cnt_t
-{
-    ZXIC_UINT32 hash_rate_cfg_cnt;
-}DPP_SE_SMMU1_HASH_RATE_CFG_CNT_T;
-
-typedef struct dpp_se_smmu1_ftm_tbl_cfg_t
-{
-    ZXIC_UINT32 ftm_baddr;
-}DPP_SE_SMMU1_FTM_TBL_CFG_T;
-
-typedef struct dpp_se_smmu1_lpm_v4_as_tbl_cfg_t
-{
-    ZXIC_UINT32 lpm_v4_as_rsp_len;
-    ZXIC_UINT32 lpm_v4_as_ecc_en;
-    ZXIC_UINT32 lpm_v4_as_baddr;
-}DPP_SE_SMMU1_LPM_V4_AS_TBL_CFG_T;
-
-typedef struct dpp_se_smmu1_lpm_v4_tbl_cfg_t
-{
-    ZXIC_UINT32 lpm_v4_len;
-    ZXIC_UINT32 lpm_v4_ecc_en;
-    ZXIC_UINT32 lpm_v4_baddr;
-}DPP_SE_SMMU1_LPM_V4_TBL_CFG_T;
-
-typedef struct dpp_se_smmu1_lpm_v6_tbl_cfg_t
-{
-    ZXIC_UINT32 lpm_v6_len;
-    ZXIC_UINT32 lpm_v6_ecc_en;
-    ZXIC_UINT32 lpm_v6_baddr;
-}DPP_SE_SMMU1_LPM_V6_TBL_CFG_T;
-
-typedef struct dpp_se_smmu1_lpm_v6_as_tbl_cfg_t
-{
-    ZXIC_UINT32 lpm_v6_as_rsp_len;
-    ZXIC_UINT32 lpm_v6_as_ecc_en;
-    ZXIC_UINT32 lpm_v6_as_baddr;
-}DPP_SE_SMMU1_LPM_V6_AS_TBL_CFG_T;
-
-typedef struct dpp_se_smmu1_dma_tbl_cfg_t
-{
-    ZXIC_UINT32 dma_baddr;
-}DPP_SE_SMMU1_DMA_TBL_CFG_T;
-
-typedef struct dpp_se_smmu1_oam_tbl_cfg_t
-{
-    ZXIC_UINT32 oam_baddr;
-}DPP_SE_SMMU1_OAM_TBL_CFG_T;
-
-typedef struct dpp_se_smmu1_ctrl_rpar_cpu_pful_t
-{
-    ZXIC_UINT32 ctrl_rpar_cpu_pful;
-}DPP_SE_SMMU1_CTRL_RPAR_CPU_PFUL_T;
-
-typedef struct dpp_se_smmu1_cfg_ksch_dir_pful_t
-{
-    ZXIC_UINT32 cfg_ksch_dir_pful;
-}DPP_SE_SMMU1_CFG_KSCH_DIR_PFUL_T;
-
-typedef struct dpp_se_smmu1_cfg_ksch_hash_pful_t
-{
-    ZXIC_UINT32 cfg_ksch_hash_pful;
-}DPP_SE_SMMU1_CFG_KSCH_HASH_PFUL_T;
-
-typedef struct dpp_se_smmu1_cfg_ksch_lpm_pful_t
-{
-    ZXIC_UINT32 cfg_ksch_lpm_pful;
-}DPP_SE_SMMU1_CFG_KSCH_LPM_PFUL_T;
-
-typedef struct dpp_se_smmu1_cfg_ksch_lpm_as_pful_t
-{
-    ZXIC_UINT32 cfg_ksch_lpm_as_pful;
-}DPP_SE_SMMU1_CFG_KSCH_LPM_AS_PFUL_T;
-
-typedef struct dpp_se_smmu1_cfg_ksch_stat_pful_t
-{
-    ZXIC_UINT32 cfg_ksch_stat_pful;
-}DPP_SE_SMMU1_CFG_KSCH_STAT_PFUL_T;
-
-typedef struct dpp_se_smmu1_cfg_ksch_tm_pful_t
-{
-    ZXIC_UINT32 cfg_ksch_tm_pful;
-}DPP_SE_SMMU1_CFG_KSCH_TM_PFUL_T;
-
-typedef struct dpp_se_smmu1_cfg_ksch_oam_pful_t
-{
-    ZXIC_UINT32 cfg_ksch_oam_pful;
-}DPP_SE_SMMU1_CFG_KSCH_OAM_PFUL_T;
-
-typedef struct dpp_se_smmu1_cfg_ksch_dma_pful_t
-{
-    ZXIC_UINT32 cfg_ksch_dma_pful;
-}DPP_SE_SMMU1_CFG_KSCH_DMA_PFUL_T;
-
-typedef struct dpp_se_smmu1_ctrl_wfifo_cfg_t
-{
-    ZXIC_UINT32 ctrl_wfifo_cfg;
-}DPP_SE_SMMU1_CTRL_WFIFO_CFG_T;
-
-typedef struct dpp_se_smmu1_rsch_hash_ptr_cfg_t
-{
-    ZXIC_UINT32 rsch_hash_ptr_cfg;
-}DPP_SE_SMMU1_RSCH_HASH_PTR_CFG_T;
-
-typedef struct dpp_se_smmu1_rsch_lpm_ptr_cfg_t
-{
-    ZXIC_UINT32 rsch_lpm_ptr_cfg;
-}DPP_SE_SMMU1_RSCH_LPM_PTR_CFG_T;
-
-typedef struct dpp_se_smmu1_rsch_lpm_as_ptr_cfg_t
-{
-    ZXIC_UINT32 rsch_lpm_as_ptr_cfg;
-}DPP_SE_SMMU1_RSCH_LPM_AS_PTR_CFG_T;
-
-typedef struct dpp_se_smmu1_rsch_stat_ptr_cfg_t
-{
-    ZXIC_UINT32 rsch_stat_ptr_cfg;
-}DPP_SE_SMMU1_RSCH_STAT_PTR_CFG_T;
-
-typedef struct dpp_se_smmu1_rsch_oam_ptr_cfg_t
-{
-    ZXIC_UINT32 rsch_oam_ptr_cfg;
-}DPP_SE_SMMU1_RSCH_OAM_PTR_CFG_T;
-
-typedef struct dpp_se_smmu1_rschd_fifo_pept_cfg_t
-{
-    ZXIC_UINT32 rschd_fifo_pept_cfg;
-}DPP_SE_SMMU1_RSCHD_FIFO_PEPT_CFG_T;
-
-typedef struct dpp_se_smmu1_dir_fifo_pful_cfg_t
-{
-    ZXIC_UINT32 dir_fifo_pful_cfg;
-}DPP_SE_SMMU1_DIR_FIFO_PFUL_CFG_T;
-
-typedef struct dpp_se_smmu1_hash_fifo_pful_cfg_t
-{
-    ZXIC_UINT32 hash_fifo_pful_cfg;
-}DPP_SE_SMMU1_HASH_FIFO_PFUL_CFG_T;
-
-typedef struct dpp_se_smmu1_lpm_fifo_pful_cfg_t
-{
-    ZXIC_UINT32 lpm_fifo_pful_cfg;
-}DPP_SE_SMMU1_LPM_FIFO_PFUL_CFG_T;
-
-typedef struct dpp_se_smmu1_lpm_as_fifo_pful_cfg_t
-{
-    ZXIC_UINT32 lpm_as_fifo_pful_cfg;
-}DPP_SE_SMMU1_LPM_AS_FIFO_PFUL_CFG_T;
-
-typedef struct dpp_se_smmu1_stat_fifo_pful_cfg_t
-{
-    ZXIC_UINT32 stat_fifo_pful_cfg;
-}DPP_SE_SMMU1_STAT_FIFO_PFUL_CFG_T;
-
-typedef struct dpp_se_smmu1_ftm_fifo_pful_cfg_t
-{
-    ZXIC_UINT32 ftm_fifo_pful_cfg;
-}DPP_SE_SMMU1_FTM_FIFO_PFUL_CFG_T;
-
-typedef struct dpp_se_smmu1_etm_fifo_pful_cfg_t
-{
-    ZXIC_UINT32 etm_fifo_pful_cfg;
-}DPP_SE_SMMU1_ETM_FIFO_PFUL_CFG_T;
-
-typedef struct dpp_se_smmu1_oam_fifo_pful_cfg_t
-{
-    ZXIC_UINT32 oam_fifo_pful_cfg;
-}DPP_SE_SMMU1_OAM_FIFO_PFUL_CFG_T;
-
-typedef struct dpp_se_smmu1_dma_fifo_pful_cfg_t
-{
-    ZXIC_UINT32 dma_fifo_pful_cfg;
-}DPP_SE_SMMU1_DMA_FIFO_PFUL_CFG_T;
-
-typedef struct dpp_se_smmu1_cache_rsp_rr_fifo_cfg_t
-{
-    ZXIC_UINT32 rr_pfull_assert0;
-    ZXIC_UINT32 rr_pfull_negate0;
-}DPP_SE_SMMU1_CACHE_RSP_RR_FIFO_CFG_T;
-
-typedef struct dpp_se_smmu1_ddr_rsp_rr_fifo_cfg_t
-{
-    ZXIC_UINT32 rr_pfull_assert1;
-    ZXIC_UINT32 rr_pfull_negate1;
-}DPP_SE_SMMU1_DDR_RSP_RR_FIFO_CFG_T;
-
-typedef struct dpp_se_smmu1_cpu_cahce_fifo_cfg_t
-{
-    ZXIC_UINT32 smmu1_cahce_fwft_fifo_pfull_assert;
-    ZXIC_UINT32 smmu1_cahce_fwft_fifo_pfull_negate;
-}DPP_SE_SMMU1_CPU_CAHCE_FIFO_CFG_T;
-
-typedef struct dpp_se_smmu1_cache_rsp_fifo_cfg_t
-{
-    ZXIC_UINT32 rschd_fifo_pfull_assert;
-    ZXIC_UINT32 rschd_fifo_pfull_negate;
-}DPP_SE_SMMU1_CACHE_RSP_FIFO_CFG_T;
-
-typedef struct dpp_se_smmu1_test_state_t
-{
-    ZXIC_UINT32 test_state;
-}DPP_SE_SMMU1_TEST_STATE_T;
-
-typedef struct dpp_se_smmu1_cache_fifo_ept_t
-{
-    ZXIC_UINT32 cache_fifo_ept;
-}DPP_SE_SMMU1_CACHE_FIFO_EPT_T;
-
-typedef struct dpp_se_smmu1_rr_fifo_ept_t
-{
-    ZXIC_UINT32 rr_fifo_ept;
-}DPP_SE_SMMU1_RR_FIFO_EPT_T;
-
-typedef struct dpp_se_smmu1_wr_fifo_ept_t
-{
-    ZXIC_UINT32 dir_arbi_ept;
-}DPP_SE_SMMU1_WR_FIFO_EPT_T;
-
-typedef struct dpp_se_smmu1_wdone_fifo_ept_t
-{
-    ZXIC_UINT32 wdone_fifo_ept;
-}DPP_SE_SMMU1_WDONE_FIFO_EPT_T;
-
-typedef struct dpp_se_smmu1_kschd_fifo_ept0_t
-{
-    ZXIC_UINT32 kschd_fifo_ept0;
-}DPP_SE_SMMU1_KSCHD_FIFO_EPT0_T;
-
-typedef struct dpp_se_smmu1_cash_fifo_ept_t
-{
-    ZXIC_UINT32 cash_fifo_ept;
-}DPP_SE_SMMU1_CASH_FIFO_EPT_T;
-
-typedef struct dpp_se_smmu1_ctrl_fifo_ept_t
-{
-    ZXIC_UINT32 ctrl_fifo_ept;
-}DPP_SE_SMMU1_CTRL_FIFO_EPT_T;
-
-typedef struct dpp_se_smmu1_smmu1_rschd_ept3_t
-{
-    ZXIC_UINT32 rschd_fifo_ept3;
-}DPP_SE_SMMU1_SMMU1_RSCHD_EPT3_T;
-
-typedef struct dpp_se_smmu1_smmu1_rschd_ept2_t
-{
-    ZXIC_UINT32 rschd_fifo_ept2;
-}DPP_SE_SMMU1_SMMU1_RSCHD_EPT2_T;
-
-typedef struct dpp_se_smmu1_smmu1_rschd_ept1_t
-{
-    ZXIC_UINT32 rschd_fifo_ept1;
-}DPP_SE_SMMU1_SMMU1_RSCHD_EPT1_T;
-
-typedef struct dpp_se_smmu1_smmu1_rschd_ept0_t
-{
-    ZXIC_UINT32 rschd_fifo_ept0;
-}DPP_SE_SMMU1_SMMU1_RSCHD_EPT0_T;
-
-typedef struct dpp_se_smmu1_cash0_ecc_err_addr_t
-{
-    ZXIC_UINT32 cash0_ecc_err_addr;
-}DPP_SE_SMMU1_CASH0_ECC_ERR_ADDR_T;
-
-typedef struct dpp_se_smmu1_arbi_cpu_wr_rdy_t
-{
-    ZXIC_UINT32 arbi_cpu_wr_rdy;
-}DPP_SE_SMMU1_ARBI_CPU_WR_RDY_T;
-
-typedef struct dpp_se_smmu1_smmu1_int_0_en_t
-{
-    ZXIC_UINT32 smmu1_int_0_en;
-}DPP_SE_SMMU1_SMMU1_INT_0_EN_T;
-
-typedef struct dpp_se_smmu1_smmu1_int_0_mask_t
-{
-    ZXIC_UINT32 smmu1_int_0_mask;
-}DPP_SE_SMMU1_SMMU1_INT_0_MASK_T;
-
-typedef struct dpp_se_smmu1_smmu1_int_1_en_t
-{
-    ZXIC_UINT32 smmu1_int_1_en;
-}DPP_SE_SMMU1_SMMU1_INT_1_EN_T;
-
-typedef struct dpp_se_smmu1_smmu1_int_1_mask_t
-{
-    ZXIC_UINT32 smmu1_int_1_mask;
-}DPP_SE_SMMU1_SMMU1_INT_1_MASK_T;
-
-typedef struct dpp_se_smmu1_smmu1_int_2_en_t
-{
-    ZXIC_UINT32 smmu1_int_2_en;
-}DPP_SE_SMMU1_SMMU1_INT_2_EN_T;
-
-typedef struct dpp_se_smmu1_smmu1_int_2_mask_t
-{
-    ZXIC_UINT32 smmu1_int_2_mask;
-}DPP_SE_SMMU1_SMMU1_INT_2_MASK_T;
-
-typedef struct dpp_se_smmu1_smmu1_int_3_en_t
-{
-    ZXIC_UINT32 smmu1_int_3_en;
-}DPP_SE_SMMU1_SMMU1_INT_3_EN_T;
-
-typedef struct dpp_se_smmu1_smmu1_int_3_mask_t
-{
-    ZXIC_UINT32 smmu1_int_3_mask;
-}DPP_SE_SMMU1_SMMU1_INT_3_MASK_T;
-
-typedef struct dpp_se_smmu1_smmu1_int_0_status_t
-{
-    ZXIC_UINT32 smmu1_int_0_status;
-}DPP_SE_SMMU1_SMMU1_INT_0_STATUS_T;
-
-typedef struct dpp_se_smmu1_smmu1_int_1_status_t
-{
-    ZXIC_UINT32 smmu1_int_1_status;
-}DPP_SE_SMMU1_SMMU1_INT_1_STATUS_T;
-
-typedef struct dpp_se_smmu1_smmu1_int_2_status_t
-{
-    ZXIC_UINT32 smmu1_int_2_status;
-}DPP_SE_SMMU1_SMMU1_INT_2_STATUS_T;
-
-typedef struct dpp_se_smmu1_smmu1_int_3_status_t
-{
-    ZXIC_UINT32 smmu1_int_3_status;
-}DPP_SE_SMMU1_SMMU1_INT_3_STATUS_T;
-
-typedef struct dpp_se_smmu1_smmu1_int_status_t
-{
-    ZXIC_UINT32 smmu1_int_status;
-}DPP_SE_SMMU1_SMMU1_INT_STATUS_T;
-
-typedef struct dpp_se_smmu1_ctrl_to_cash7_0_fc_cnt_t
-{
-    ZXIC_UINT32 ctrl_to_cash7_0_fc_cnt;
-}DPP_SE_SMMU1_CTRL_TO_CASH7_0_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_cash7_0_to_ctrl_req_cnt_t
-{
-    ZXIC_UINT32 cash7_0_to_ctrl_req_cnt;
-}DPP_SE_SMMU1_CASH7_0_TO_CTRL_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_rschd_to_cache7_fc_cnt_t
-{
-    ZXIC_UINT32 rschd_to_cache7_fc_cnt;
-}DPP_SE_SMMU1_RSCHD_TO_CACHE7_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_cash7_to_cache_rsp_cnt_t
-{
-    ZXIC_UINT32 cash7_to_cache_rsp_cnt;
-}DPP_SE_SMMU1_CASH7_TO_CACHE_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_cash7_to_ctrl_fc_cnt_t
-{
-    ZXIC_UINT32 cash7_to_ctrl_fc_cnt;
-}DPP_SE_SMMU1_CASH7_TO_CTRL_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_ctrl_to_cash7_0_rsp_cnt_t
-{
-    ZXIC_UINT32 ctrl_to_cash7_0_rsp_cnt;
-}DPP_SE_SMMU1_CTRL_TO_CASH7_0_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_kschd_to_cache7_0_req_cnt_t
-{
-    ZXIC_UINT32 kschd_to_cache7_0_req_cnt;
-}DPP_SE_SMMU1_KSCHD_TO_CACHE7_0_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_cache7_0_to_kschd_fc_cnt_t
-{
-    ZXIC_UINT32 cache7_0_to_kschd_fc_cnt;
-}DPP_SE_SMMU1_CACHE7_0_TO_KSCHD_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_dma_to_smmu1_rd_req_cnt_t
-{
-    ZXIC_UINT32 dma_to_smmu1_rd_req_cnt;
-}DPP_SE_SMMU1_DMA_TO_SMMU1_RD_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_oam_to_kschd_req_cnt_t
-{
-    ZXIC_UINT32 oam_to_kschd_req_cnt;
-}DPP_SE_SMMU1_OAM_TO_KSCHD_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_oam_rr_state_rsp_cnt_t
-{
-    ZXIC_UINT32 oam_rr_state_rsp_cnt;
-}DPP_SE_SMMU1_OAM_RR_STATE_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_oam_clash_info_cnt_t
-{
-    ZXIC_UINT32 oam_clash_info_cnt;
-}DPP_SE_SMMU1_OAM_CLASH_INFO_CNT_T;
-
-typedef struct dpp_se_smmu1_oam_to_rr_req_cnt_t
-{
-    ZXIC_UINT32 oam_to_rr_req_cnt;
-}DPP_SE_SMMU1_OAM_TO_RR_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_lpm_as_to_kschd_req_cnt_t
-{
-    ZXIC_UINT32 lpm_as_to_kschd_req_cnt;
-}DPP_SE_SMMU1_LPM_AS_TO_KSCHD_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_lpm_as_rr_state_rsp_cnt_t
-{
-    ZXIC_UINT32 lpm_as_rr_state_rsp_cnt;
-}DPP_SE_SMMU1_LPM_AS_RR_STATE_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_lpm_as_clash_info_cnt_t
-{
-    ZXIC_UINT32 lpm_as_clash_info_cnt;
-}DPP_SE_SMMU1_LPM_AS_CLASH_INFO_CNT_T;
-
-typedef struct dpp_se_smmu1_lpm_as_to_rr_req_cnt_t
-{
-    ZXIC_UINT32 lpm_as_to_rr_req_cnt;
-}DPP_SE_SMMU1_LPM_AS_TO_RR_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_lpm_to_kschd_req_cnt_t
-{
-    ZXIC_UINT32 lpm_to_kschd_req_cnt;
-}DPP_SE_SMMU1_LPM_TO_KSCHD_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_lpm_rr_state_rsp_cnt_t
-{
-    ZXIC_UINT32 lpm_rr_state_rsp_cnt;
-}DPP_SE_SMMU1_LPM_RR_STATE_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_lpm_clash_info_cnt_t
-{
-    ZXIC_UINT32 lpm_clash_info_cnt;
-}DPP_SE_SMMU1_LPM_CLASH_INFO_CNT_T;
-
-typedef struct dpp_se_smmu1_lpm_to_rr_req_cnt_t
-{
-    ZXIC_UINT32 lpm_to_rr_req_cnt;
-}DPP_SE_SMMU1_LPM_TO_RR_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_hash3_0_to_kschd_req_cnt_t
-{
-    ZXIC_UINT32 hash3_0_to_kschd_req_cnt;
-}DPP_SE_SMMU1_HASH3_0_TO_KSCHD_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_hash3_0_rr_state_rsp_cnt_t
-{
-    ZXIC_UINT32 hash3_0_rr_state_rsp_cnt;
-}DPP_SE_SMMU1_HASH3_0_RR_STATE_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_hash3_0_clash_info_cnt_t
-{
-    ZXIC_UINT32 hash3_0_clash_info_cnt;
-}DPP_SE_SMMU1_HASH3_0_CLASH_INFO_CNT_T;
-
-typedef struct dpp_se_smmu1_hash3_0_to_rr_req_cnt_t
-{
-    ZXIC_UINT32 hash3_0_to_rr_req_cnt;
-}DPP_SE_SMMU1_HASH3_0_TO_RR_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_dir3_0_to_kschd_req_cnt_t
-{
-    ZXIC_UINT32 dir3_0_to_kschd_req_cnt;
-}DPP_SE_SMMU1_DIR3_0_TO_KSCHD_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_dir3_0_clash_info_cnt_t
-{
-    ZXIC_UINT32 dir3_0_clash_info_cnt;
-}DPP_SE_SMMU1_DIR3_0_CLASH_INFO_CNT_T;
-
-typedef struct dpp_se_smmu1_dir_tbl_wr_req_cnt_t
-{
-    ZXIC_UINT32 dir_tbl_wr_req_cnt;
-}DPP_SE_SMMU1_DIR_TBL_WR_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_warbi_to_dir_tbl_warbi_fc_cnt_t
-{
-    ZXIC_UINT32 warbi_to_dir_tbl_warbi_fc_cnt;
-}DPP_SE_SMMU1_WARBI_TO_DIR_TBL_WARBI_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_dir3_0_to_bank_rr_req_cnt_t
-{
-    ZXIC_UINT32 dir3_0_to_bank_rr_req_cnt;
-}DPP_SE_SMMU1_DIR3_0_TO_BANK_RR_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_kschd_to_dir3_0_fc_cnt_t
-{
-    ZXIC_UINT32 kschd_to_dir3_0_fc_cnt;
-}DPP_SE_SMMU1_KSCHD_TO_DIR3_0_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_dir3_0_rr_state_rsp_cnt_t
-{
-    ZXIC_UINT32 dir3_0_rr_state_rsp_cnt;
-}DPP_SE_SMMU1_DIR3_0_RR_STATE_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_wr_done_to_warbi_fc_cnt_t
-{
-    ZXIC_UINT32 wr_done_to_warbi_fc_cnt;
-}DPP_SE_SMMU1_WR_DONE_TO_WARBI_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_wr_done_ptr_req_cnt_t
-{
-    ZXIC_UINT32 wr_done_ptr_req_cnt;
-}DPP_SE_SMMU1_WR_DONE_PTR_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_ctrl7_0_to_warbi_fc_cnt_t
-{
-    ZXIC_UINT32 ctrl7_0_to_warbi_fc_cnt;
-}DPP_SE_SMMU1_CTRL7_0_TO_WARBI_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_warbi_to_ctrl7_0_wr_req_cnt_t
-{
-    ZXIC_UINT32 warbi_to_ctrl7_0_wr_req_cnt;
-}DPP_SE_SMMU1_WARBI_TO_CTRL7_0_WR_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_warbi_to_cash7_0_wr_req_cnt_t
-{
-    ZXIC_UINT32 warbi_to_cash7_0_wr_req_cnt;
-}DPP_SE_SMMU1_WARBI_TO_CASH7_0_WR_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_warbi_to_cpu_wr_fc_cnt_t
-{
-    ZXIC_UINT32 warbi_to_cpu_wr_fc_cnt;
-}DPP_SE_SMMU1_WARBI_TO_CPU_WR_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_cpu_wr_req_cnt_t
-{
-    ZXIC_UINT32 cpu_wr_req_cnt;
-}DPP_SE_SMMU1_CPU_WR_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_ctrl7_0_to_cpu_rd_rsp_cnt_t
-{
-    ZXIC_UINT32 ctrl7_0_to_cpu_rd_rsp_cnt;
-}DPP_SE_SMMU1_CTRL7_0_TO_CPU_RD_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_cpu_to_ctrl7_0_rd_req_cnt_t
-{
-    ZXIC_UINT32 cpu_to_ctrl7_0_rd_req_cnt;
-}DPP_SE_SMMU1_CPU_TO_CTRL7_0_RD_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_cpu_rd_dir_tbl_rsp_cnt_t
-{
-    ZXIC_UINT32 cpu_rd_dir_tbl_rsp_cnt;
-}DPP_SE_SMMU1_CPU_RD_DIR_TBL_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_cpu_to_dir_tbl_rd_wr_req_cnt_t
-{
-    ZXIC_UINT32 cpu_to_dir_tbl_rd_wr_req_cnt;
-}DPP_SE_SMMU1_CPU_TO_DIR_TBL_RD_WR_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_mmu_7_0_rsp_fc_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_mmu_7_0_rsp_fc_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_MMU_7_0_RSP_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_mmu_7_0_to_smmu1_rd_rsp_cnt_t
-{
-    ZXIC_UINT32 mmu_7_0_to_smmu1_rd_rsp_cnt;
-}DPP_SE_SMMU1_MMU_7_0_TO_SMMU1_RD_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_mmu_7_0_to_smmu1_rd_fc_cnt_t
-{
-    ZXIC_UINT32 mmu_7_0_to_smmu1_rd_fc_cnt;
-}DPP_SE_SMMU1_MMU_7_0_TO_SMMU1_RD_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_mmu_7_rd_req_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_mmu_7_rd_req_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_MMU_7_RD_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_mmu_7_to_smmu1_wr_fc_cnt_t
-{
-    ZXIC_UINT32 mmu_7_to_smmu1_wr_fc_cnt;
-}DPP_SE_SMMU1_MMU_7_TO_SMMU1_WR_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_mmu_7_0_wr_req_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_mmu_7_0_wr_req_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_MMU_7_0_WR_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_se_to_smmu1_wr_rsp_fc_cnt_t
-{
-    ZXIC_UINT32 se_to_smmu1_wr_rsp_fc_cnt;
-}DPP_SE_SMMU1_SE_TO_SMMU1_WR_RSP_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_se_wr_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_se_wr_rsp_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_SE_WR_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_ddr7_0_wr_rsp_cnt_t
-{
-    ZXIC_UINT32 ddr7_0_wr_rsp_cnt;
-}DPP_SE_SMMU1_DDR7_0_WR_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_as_fc_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_as_fc_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_AS_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_as_to_smmu1_wr_req_cnt_t
-{
-    ZXIC_UINT32 as_to_smmu1_wr_req_cnt;
-}DPP_SE_SMMU1_AS_TO_SMMU1_WR_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_se_parser_fc_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_se_parser_fc_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_SE_PARSER_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_se_parser_to_smmu1_req_cnt_t
-{
-    ZXIC_UINT32 se_parser_to_smmu1_req_cnt;
-}DPP_SE_SMMU1_SE_PARSER_TO_SMMU1_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_etm_wr_fc_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_etm_wr_fc_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_ETM_WR_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_etm_wr_req_cnt_t
-{
-    ZXIC_UINT32 etm_wr_req_cnt;
-}DPP_SE_SMMU1_ETM_WR_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_ftm_wr_fc_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_ftm_wr_fc_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_FTM_WR_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_ftm_wr_req_cnt_t
-{
-    ZXIC_UINT32 ftm_wr_req_cnt;
-}DPP_SE_SMMU1_FTM_WR_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_state_wr_fc_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_state_wr_fc_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_STATE_WR_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_state_wr_req_cnt_t
-{
-    ZXIC_UINT32 state_wr_req_cnt;
-}DPP_SE_SMMU1_STATE_WR_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_se_to_dma_rsp_cnt_t
-{
-    ZXIC_UINT32 se_to_dma_rsp_cnt;
-}DPP_SE_SMMU1_SE_TO_DMA_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_se_to_dma_fc_cnt_t
-{
-    ZXIC_UINT32 se_to_dma_fc_cnt;
-}DPP_SE_SMMU1_SE_TO_DMA_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_oam_to_smmu1_fc_cnt_t
-{
-    ZXIC_UINT32 oam_to_smmu1_fc_cnt;
-}DPP_SE_SMMU1_OAM_TO_SMMU1_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_oam_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_oam_rsp_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_OAM_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_oam_fc_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_oam_fc_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_OAM_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_oam_to_smmu1_req_cnt_t
-{
-    ZXIC_UINT32 oam_to_smmu1_req_cnt;
-}DPP_SE_SMMU1_OAM_TO_SMMU1_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_etm_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_etm_rsp_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_ETM_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_ftm_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_ftm_rsp_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_FTM_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_etm_fc_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_etm_fc_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_ETM_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_etm_to_smmu1_req_cnt_t
-{
-    ZXIC_UINT32 etm_to_smmu1_req_cnt;
-}DPP_SE_SMMU1_ETM_TO_SMMU1_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_ftm_fc_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_ftm_fc_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_FTM_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_ftm_to_smmu1_req_cnt_t
-{
-    ZXIC_UINT32 ftm_to_smmu1_req_cnt;
-}DPP_SE_SMMU1_FTM_TO_SMMU1_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_stat_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_stat_rsp_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_STAT_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_stat_fc_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_stat_fc_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_STAT_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_stat_to_smmu1_req_cnt_t
-{
-    ZXIC_UINT32 stat_to_smmu1_req_cnt;
-}DPP_SE_SMMU1_STAT_TO_SMMU1_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_lpm_as_to_smmu1_fc_cnt_t
-{
-    ZXIC_UINT32 lpm_as_to_smmu1_fc_cnt;
-}DPP_SE_SMMU1_LPM_AS_TO_SMMU1_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_lpm_to_smmu1_fc_cnt_t
-{
-    ZXIC_UINT32 lpm_to_smmu1_fc_cnt;
-}DPP_SE_SMMU1_LPM_TO_SMMU1_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_lpm_as_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_lpm_as_rsp_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_LPM_AS_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_lpm_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_lpm_rsp_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_LPM_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_lpm_as_fc_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_lpm_as_fc_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_LPM_AS_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_lpm_fc_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_lpm_fc_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_LPM_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_lpm_as_to_smmu1_req_cnt_t
-{
-    ZXIC_UINT32 lpm_as_to_smmu1_req_cnt;
-}DPP_SE_SMMU1_LPM_AS_TO_SMMU1_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_lpm_to_smmu1_req_cnt_t
-{
-    ZXIC_UINT32 lpm_to_smmu1_req_cnt;
-}DPP_SE_SMMU1_LPM_TO_SMMU1_REQ_CNT_T;
-
-typedef struct dpp_se_smmu1_hash3_0_to_smmu1_fc_cnt_t
-{
-    ZXIC_UINT32 hash3_0_to_smmu1_fc_cnt;
-}DPP_SE_SMMU1_HASH3_0_TO_SMMU1_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_hash3_0_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_hash3_0_rsp_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_HASH3_0_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_hash3_0_fc_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_hash3_0_fc_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_HASH3_0_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_hash3_0_to_smmu1_cnt_t
-{
-    ZXIC_UINT32 hash3_0_to_smmu1_cnt;
-}DPP_SE_SMMU1_HASH3_0_TO_SMMU1_CNT_T;
-
-typedef struct dpp_se_smmu1_se_to_smmu1_dir3_0_rsp_fc_cnt_t
-{
-    ZXIC_UINT32 se_to_smmu1_dir3_0_rsp_fc_cnt;
-}DPP_SE_SMMU1_SE_TO_SMMU1_DIR3_0_RSP_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_se_dir3_0_rsp_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_se_dir3_0_rsp_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_SE_DIR3_0_RSP_CNT_T;
-
-typedef struct dpp_se_smmu1_smmu1_to_se_dir3_0_fc_cnt_t
-{
-    ZXIC_UINT32 smmu1_to_se_dir3_0_fc_cnt;
-}DPP_SE_SMMU1_SMMU1_TO_SE_DIR3_0_FC_CNT_T;
-
-typedef struct dpp_se_smmu1_se_to_smmu1_dir3_0_cnt_t
-{
-    ZXIC_UINT32 se_to_smmu1_dir3_0_cnt;
-}DPP_SE_SMMU1_SE_TO_SMMU1_DIR3_0_CNT_T;
-
-typedef struct dpp_se_smmu1_cache7_0_to_rschd_rsp_cnt_t
-{
-    ZXIC_UINT32 cache7_0_to_rschd_rsp_cnt;
-}DPP_SE_SMMU1_CACHE7_0_TO_RSCHD_RSP_CNT_T;
-
-typedef struct dpp_se_cmmu_ddr_rw_addr_t
-{
-    ZXIC_UINT32 ddr_wr;
-}DPP_SE_CMMU_DDR_RW_ADDR_T;
-
-typedef struct dpp_se_cmmu_ddr_rw_mode_t
-{
-    ZXIC_UINT32 ddr_rw_flag;
-    ZXIC_UINT32 ddr_rw_mode;
-}DPP_SE_CMMU_DDR_RW_MODE_T;
-
-typedef struct dpp_se_cmmu_cp_cmd_t
-{
-    ZXIC_UINT32 stat_tbl_baddr;
-}DPP_SE_CMMU_CP_CMD_T;
-
-typedef struct dpp_se_cmmu_cpu_ind_rd_done_t
-{
-    ZXIC_UINT32 cpu_ind_rd_done;
-}DPP_SE_CMMU_CPU_IND_RD_DONE_T;
-
-typedef struct dpp_se_cmmu_cpu_ind_rdat0_t
-{
-    ZXIC_UINT32 cpu_ind_rdat0;
-}DPP_SE_CMMU_CPU_IND_RDAT0_T;
-
-typedef struct dpp_se_cmmu_cpu_ind_rdat1_t
-{
-    ZXIC_UINT32 cpu_ind_rdat1;
-}DPP_SE_CMMU_CPU_IND_RDAT1_T;
-
-typedef struct dpp_se_cmmu_cpu_ind_rdat2_t
-{
-    ZXIC_UINT32 cpu_ind_rdat2;
-}DPP_SE_CMMU_CPU_IND_RDAT2_T;
-
-typedef struct dpp_se_cmmu_cpu_ind_rdat3_t
-{
-    ZXIC_UINT32 cpu_ind_rdat3;
-}DPP_SE_CMMU_CPU_IND_RDAT3_T;
-
-typedef struct dpp_se_cmmu_cpu_ddr_fifo_almful_t
-{
-    ZXIC_UINT32 cpu_ddr_fifo_almful;
-}DPP_SE_CMMU_CPU_DDR_FIFO_ALMFUL_T;
-
-typedef struct dpp_se_cmmu_debug_cnt_mode_t
-{
-    ZXIC_UINT32 cnt_rd_mode;
-    ZXIC_UINT32 cnt_overflow_mode;
-}DPP_SE_CMMU_DEBUG_CNT_MODE_T;
-
-typedef struct dpp_se_cmmu_cmmu_pful_cfg_t
-{
-    ZXIC_UINT32 alu_cmd_pful_negate;
-    ZXIC_UINT32 alu_cmd_pful_assert;
-}DPP_SE_CMMU_CMMU_PFUL_CFG_T;
-
-typedef struct dpp_se_cmmu_cmmu_stat_pful_cfg_t
-{
-    ZXIC_UINT32 cmmu_stat_pful_negate;
-    ZXIC_UINT32 cmmu_stat_pful_assert;
-}DPP_SE_CMMU_CMMU_STAT_PFUL_CFG_T;
-
-typedef struct dpp_se_cmmu_stat_overflow_mode_t
-{
-    ZXIC_UINT32 stat_overflow_mode;
-}DPP_SE_CMMU_STAT_OVERFLOW_MODE_T;
-
-typedef struct dpp_se_cmmu_cmmu_cp_fifo_pful_t
-{
-    ZXIC_UINT32 cmmu_cp_fifo_pful;
-}DPP_SE_CMMU_CMMU_CP_FIFO_PFUL_T;
-
-typedef struct dpp_se_cmmu_ddr_wr_dat0_t
-{
-    ZXIC_UINT32 ddr_wr_dat0;
-}DPP_SE_CMMU_DDR_WR_DAT0_T;
-
-typedef struct dpp_se_cmmu_ddr_wr_dat1_t
-{
-    ZXIC_UINT32 ddr_wr_dat1;
-}DPP_SE_CMMU_DDR_WR_DAT1_T;
-
-typedef struct dpp_se_cmmu_cmmu_int_unmask_flag_t
-{
-    ZXIC_UINT32 cmmu_int_unmask_flag;
-}DPP_SE_CMMU_CMMU_INT_UNMASK_FLAG_T;
-
-typedef struct dpp_se_cmmu_cmmu_int_en_t
-{
-    ZXIC_UINT32 cmmu_int_en12;
-    ZXIC_UINT32 cmmu_int_en11;
-    ZXIC_UINT32 cmmu_int_en10;
-    ZXIC_UINT32 cmmu_int_en9;
-    ZXIC_UINT32 cmmu_int_en8;
-    ZXIC_UINT32 cmmu_int_en7;
-    ZXIC_UINT32 cmmu_int_en6;
-    ZXIC_UINT32 cmmu_int_en5;
-    ZXIC_UINT32 cmmu_int_en4;
-    ZXIC_UINT32 cmmu_int_en3;
-    ZXIC_UINT32 cmmu_int_en2;
-    ZXIC_UINT32 cmmu_int_en1;
-    ZXIC_UINT32 cmmu_int_en0;
-}DPP_SE_CMMU_CMMU_INT_EN_T;
-
-typedef struct dpp_se_cmmu_cmmu_int_mask_t
-{
-    ZXIC_UINT32 cmmu_int_mask12;
-    ZXIC_UINT32 cmmu_int_mask11;
-    ZXIC_UINT32 cmmu_int_mask10;
-    ZXIC_UINT32 cmmu_int_mask9;
-    ZXIC_UINT32 cmmu_int_mask8;
-    ZXIC_UINT32 cmmu_int_mask7;
-    ZXIC_UINT32 cmmu_int_mask6;
-    ZXIC_UINT32 cmmu_int_mask5;
-    ZXIC_UINT32 cmmu_int_mask4;
-    ZXIC_UINT32 cmmu_int_mask3;
-    ZXIC_UINT32 cmmu_int_mask2;
-    ZXIC_UINT32 cmmu_int_mask1;
-    ZXIC_UINT32 cmmu_int_mask0;
-}DPP_SE_CMMU_CMMU_INT_MASK_T;
-
-typedef struct dpp_se_cmmu_cmmu_int_status_t
-{
-    ZXIC_UINT32 cmmu_int_status12;
-    ZXIC_UINT32 cmmu_int_status11;
-    ZXIC_UINT32 cmmu_int_status10;
-    ZXIC_UINT32 cmmu_int_status9;
-    ZXIC_UINT32 cmmu_int_status8;
-    ZXIC_UINT32 cmmu_int_status7;
-    ZXIC_UINT32 cmmu_int_status6;
-    ZXIC_UINT32 cmmu_int_status5;
-    ZXIC_UINT32 cmmu_int_status4;
-    ZXIC_UINT32 cmmu_int_status3;
-    ZXIC_UINT32 cmmu_int_status2;
-    ZXIC_UINT32 cmmu_int_status1;
-    ZXIC_UINT32 cmmu_int_status0;
-}DPP_SE_CMMU_CMMU_INT_STATUS_T;
-
-typedef struct dpp_se_cmmu_stat_cmmu_req_cnt_t
-{
-    ZXIC_UINT32 stat_cmmu_req_cnt;
-}DPP_SE_CMMU_STAT_CMMU_REQ_CNT_T;
-
-typedef struct dpp_se_cmmu_cmmu_fc0_cnt_t
-{
-    ZXIC_UINT32 cmmu_stat_rdy;
-}DPP_SE_CMMU_CMMU_FC0_CNT_T;
-
-typedef struct dpp_se_cmmu_cmmu_fc1_cnt_t
-{
-    ZXIC_UINT32 smmu1_cmmu_wr_rdy;
-}DPP_SE_CMMU_CMMU_FC1_CNT_T;
-
-typedef struct dpp_se_cmmu_cmmu_fc2_cnt_t
-{
-    ZXIC_UINT32 smmu1_cmmu_rd_rdy;
-}DPP_SE_CMMU_CMMU_FC2_CNT_T;
+typedef struct dpp_se_smmu1_ddr_wdat0_t {
+	ZXIC_UINT32 ddr_wdat0;
+} DPP_SE_SMMU1_DDR_WDAT0_T;
+
+typedef struct dpp_se_smmu1_dir_arbi_ser_rpful_t {
+	ZXIC_UINT32 dir_arbi_ser_rpful;
+} DPP_SE_SMMU1_DIR_ARBI_SER_RPFUL_T;
+
+typedef struct dpp_se_smmu1_cfg_wr_arbi_pful2_t {
+	ZXIC_UINT32 hash_wr_pful;
+	ZXIC_UINT32 dir_wr_pful;
+} DPP_SE_SMMU1_CFG_WR_ARBI_PFUL2_T;
 
+typedef struct dpp_se_smmu1_etm_tbl_cfg_t {
+	ZXIC_UINT32 etm_baddr;
+} DPP_SE_SMMU1_ETM_TBL_CFG_T;
+
+typedef struct dpp_se_smmu1_cfg_cash_addr_pful_t {
+	ZXIC_UINT32 cfg_cash_addr_pful;
+} DPP_SE_SMMU1_CFG_CASH_ADDR_PFUL_T;
+
+typedef struct dpp_se_smmu1_ctrl_rfifo_cfg_t {
+	ZXIC_UINT32 brst_fwft_fifo_prog_empty_assert;
+	ZXIC_UINT32 brst_fwft_fifo_prog_empty_negate;
+	ZXIC_UINT32 brst_fwft_fifo_prog_full_assert;
+	ZXIC_UINT32 brst_fwft_fifo_prog_full_negate;
+} DPP_SE_SMMU1_CTRL_RFIFO_CFG_T;
+
+typedef struct dpp_se_smmu1_cache_req_fifo_cfg_t {
+	ZXIC_UINT32 srch_fifo_pfull_assert;
+	ZXIC_UINT32 srch_fifo_pfull_negate;
+} DPP_SE_SMMU1_CACHE_REQ_FIFO_CFG_T;
+
+typedef struct dpp_se_smmu1_ddr_wdat1_t {
+	ZXIC_UINT32 ddr_wdat1;
+} DPP_SE_SMMU1_DDR_WDAT1_T;
+
+typedef struct dpp_se_smmu1_ddr_wdat2_t {
+	ZXIC_UINT32 ddr_wdat2;
+} DPP_SE_SMMU1_DDR_WDAT2_T;
+
+typedef struct dpp_se_smmu1_ddr_wdat3_t {
+	ZXIC_UINT32 ddr_wdat3;
+} DPP_SE_SMMU1_DDR_WDAT3_T;
+
+typedef struct dpp_se_smmu1_ddr_wdat4_t {
+	ZXIC_UINT32 ddr_wdat4;
+} DPP_SE_SMMU1_DDR_WDAT4_T;
+
+typedef struct dpp_se_smmu1_ddr_wdat5_t {
+	ZXIC_UINT32 ddr_wdat5;
+} DPP_SE_SMMU1_DDR_WDAT5_T;
+
+typedef struct dpp_se_smmu1_ddr_wdat6_t {
+	ZXIC_UINT32 ddr_wdat6;
+} DPP_SE_SMMU1_DDR_WDAT6_T;
+
+typedef struct dpp_se_smmu1_ddr_wdat7_t {
+	ZXIC_UINT32 ddr_wdat7;
+} DPP_SE_SMMU1_DDR_WDAT7_T;
+
+typedef struct dpp_se_smmu1_ddr_wdat8_t {
+	ZXIC_UINT32 ddr_wdat8;
+} DPP_SE_SMMU1_DDR_WDAT8_T;
+
+typedef struct dpp_se_smmu1_ddr_wdat9_t {
+	ZXIC_UINT32 ddr_wdat9;
+} DPP_SE_SMMU1_DDR_WDAT9_T;
+
+typedef struct dpp_se_smmu1_ddr_wdat10_t {
+	ZXIC_UINT32 ddr_wdat10;
+} DPP_SE_SMMU1_DDR_WDAT10_T;
+
+typedef struct dpp_se_smmu1_ddr_wdat11_t {
+	ZXIC_UINT32 ddr_wdat11;
+} DPP_SE_SMMU1_DDR_WDAT11_T;
+
+typedef struct dpp_se_smmu1_ddr_wdat12_t {
+	ZXIC_UINT32 ddr_wdat12;
+} DPP_SE_SMMU1_DDR_WDAT12_T;
+
+typedef struct dpp_se_smmu1_ddr_wdat13_t {
+	ZXIC_UINT32 ddr_wdat13;
+} DPP_SE_SMMU1_DDR_WDAT13_T;
+
+typedef struct dpp_se_smmu1_ddr_wdat14_t {
+	ZXIC_UINT32 ddr_wdat14;
+} DPP_SE_SMMU1_DDR_WDAT14_T;
+
+typedef struct dpp_se_smmu1_ddr_wdat15_t {
+	ZXIC_UINT32 ddr_wdat15;
+} DPP_SE_SMMU1_DDR_WDAT15_T;
+
+typedef struct dpp_se_smmu1_cnt_stat_cache_en_t {
+	ZXIC_UINT32 cnt_stat_cache_en;
+} DPP_SE_SMMU1_CNT_STAT_CACHE_EN_T;
+
+typedef struct dpp_se_smmu1_cnt_stat_cache_clr_t {
+	ZXIC_UINT32 cnt_stat_cache_clr;
+} DPP_SE_SMMU1_CNT_STAT_CACHE_CLR_T;
+
+typedef struct dpp_se_smmu1_cnt_stat_cache_req_63_32_t {
+	ZXIC_UINT32 cnt_stat_cache_req_63_32;
+} DPP_SE_SMMU1_CNT_STAT_CACHE_REQ_63_32_T;
+
+typedef struct dpp_se_smmu1_cnt_stat_cache_req_31_0_t {
+	ZXIC_UINT32 cnt_stat_cache_req_31_0;
+} DPP_SE_SMMU1_CNT_STAT_CACHE_REQ_31_0_T;
+
+typedef struct dpp_se_smmu1_cnt_stat_cache_hit_63_32_t {
+	ZXIC_UINT32 cnt_stat_cache_hit_63_32;
+} DPP_SE_SMMU1_CNT_STAT_CACHE_HIT_63_32_T;
+
+typedef struct dpp_se_smmu1_cnt_stat_cache_hit_31_0_t {
+	ZXIC_UINT32 cnt_stat_cache_hit_31_0;
+} DPP_SE_SMMU1_CNT_STAT_CACHE_HIT_31_0_T;
+
+typedef struct dpp_se_smmu1_ddr_cmd0_t {
+	ZXIC_UINT32 ecc_en;
+	ZXIC_UINT32 rw_len;
+	ZXIC_UINT32 baddr;
+} DPP_SE_SMMU1_DDR_CMD0_T;
+
+typedef struct dpp_se_smmu1_info_addr_t {
+	ZXIC_UINT32 info_addr;
+} DPP_SE_SMMU1_INFO_ADDR_T;
+
+typedef struct dpp_se_smmu1_ddr_cmd1_t {
+	ZXIC_UINT32 rw_flag;
+	ZXIC_UINT32 rw_addr;
+} DPP_SE_SMMU1_DDR_CMD1_T;
+
+typedef struct dpp_se_smmu1_clr_start_addr_t {
+	ZXIC_UINT32 clr_start_addr;
+} DPP_SE_SMMU1_CLR_START_ADDR_T;
+
+typedef struct dpp_se_smmu1_clr_end_addr_t {
+	ZXIC_UINT32 clr_end_addr;
+} DPP_SE_SMMU1_CLR_END_ADDR_T;
+
+typedef struct dpp_se_smmu1_clr_tbl_en_t {
+	ZXIC_UINT32 cfg_init_en;
+	ZXIC_UINT32 clr_tbl_en;
+} DPP_SE_SMMU1_CLR_TBL_EN_T;
+
+typedef struct dpp_se_smmu1_debug_cnt_mode_t {
+	ZXIC_UINT32 cnt_rd_mode;
+	ZXIC_UINT32 cnt_overflow_mode;
+} DPP_SE_SMMU1_DEBUG_CNT_MODE_T;
+
+typedef struct dpp_se_smmu1_init_done_t {
+	ZXIC_UINT32 cache_init_done;
+	ZXIC_UINT32 clr_done;
+	ZXIC_UINT32 init_ok;
+} DPP_SE_SMMU1_INIT_DONE_T;
+
+typedef struct dpp_se_smmu1_cpu_rsp_rd_done_t {
+	ZXIC_UINT32 cpu_rsp_rd_done;
+} DPP_SE_SMMU1_CPU_RSP_RD_DONE_T;
+
+typedef struct dpp_se_smmu1_ksch_oam_sp_en_t {
+	ZXIC_UINT32 ksch_oam_sp_en;
+} DPP_SE_SMMU1_KSCH_OAM_SP_EN_T;
+
+typedef struct dpp_se_smmu1_cfg_cache_en_t {
+	ZXIC_UINT32 cfg_cache_en;
+} DPP_SE_SMMU1_CFG_CACHE_EN_T;
+
+typedef struct dpp_se_smmu1_cache_age_en_t {
+	ZXIC_UINT32 cache_age_en;
+} DPP_SE_SMMU1_CACHE_AGE_EN_T;
+
+typedef struct dpp_se_smmu1_cpu_rdat0_t {
+	ZXIC_UINT32 cpu_rdat0;
+} DPP_SE_SMMU1_CPU_RDAT0_T;
+
+typedef struct dpp_se_smmu1_cpu_rdat1_t {
+	ZXIC_UINT32 cpu_rdat1;
+} DPP_SE_SMMU1_CPU_RDAT1_T;
+
+typedef struct dpp_se_smmu1_cpu_rdat2_t {
+	ZXIC_UINT32 cpu_rdat2;
+} DPP_SE_SMMU1_CPU_RDAT2_T;
+
+typedef struct dpp_se_smmu1_cpu_rdat3_t {
+	ZXIC_UINT32 cpu_rdat3;
+} DPP_SE_SMMU1_CPU_RDAT3_T;
+
+typedef struct dpp_se_smmu1_cpu_rdat4_t {
+	ZXIC_UINT32 cpu_rdat4;
+} DPP_SE_SMMU1_CPU_RDAT4_T;
+
+typedef struct dpp_se_smmu1_cpu_rdat5_t {
+	ZXIC_UINT32 cpu_rdat5;
+} DPP_SE_SMMU1_CPU_RDAT5_T;
+
+typedef struct dpp_se_smmu1_cpu_rdat6_t {
+	ZXIC_UINT32 cpu_rdat6;
+} DPP_SE_SMMU1_CPU_RDAT6_T;
+
+typedef struct dpp_se_smmu1_cpu_rdat7_t {
+	ZXIC_UINT32 cpu_rdat7;
+} DPP_SE_SMMU1_CPU_RDAT7_T;
+
+typedef struct dpp_se_smmu1_cpu_rdat8_t {
+	ZXIC_UINT32 cpu_rdat8;
+} DPP_SE_SMMU1_CPU_RDAT8_T;
+
+typedef struct dpp_se_smmu1_cpu_rdat9_t {
+	ZXIC_UINT32 cpu_rdat9;
+} DPP_SE_SMMU1_CPU_RDAT9_T;
+
+typedef struct dpp_se_smmu1_cpu_rdat10_t {
+	ZXIC_UINT32 cpu_rdat10;
+} DPP_SE_SMMU1_CPU_RDAT10_T;
+
+typedef struct dpp_se_smmu1_cpu_rdat11_t {
+	ZXIC_UINT32 cpu_rdat11;
+} DPP_SE_SMMU1_CPU_RDAT11_T;
+
+typedef struct dpp_se_smmu1_cpu_rdat12_t {
+	ZXIC_UINT32 cpu_rdat12;
+} DPP_SE_SMMU1_CPU_RDAT12_T;
+
+typedef struct dpp_se_smmu1_cpu_rdat13_t {
+	ZXIC_UINT32 cpu_rdat13;
+} DPP_SE_SMMU1_CPU_RDAT13_T;
+
+typedef struct dpp_se_smmu1_cpu_rdat14_t {
+	ZXIC_UINT32 cpu_rdat14;
+} DPP_SE_SMMU1_CPU_RDAT14_T;
+
+typedef struct dpp_se_smmu1_cpu_rdat15_t {
+	ZXIC_UINT32 cpu_rdat15;
+} DPP_SE_SMMU1_CPU_RDAT15_T;
+
+typedef struct dpp_se_smmu1_ctrl_cpu_rd_rdy_t {
+	ZXIC_UINT32 ctrl_cpu_rd_rdy;
+} DPP_SE_SMMU1_CTRL_CPU_RD_RDY_T;
+
+typedef struct dpp_se_smmu1_cpu_warbi_rdy_cfg_t {
+	ZXIC_UINT32 cpu_warbi_rdy_cfg;
+} DPP_SE_SMMU1_CPU_WARBI_RDY_CFG_T;
+
+typedef struct dpp_se_smmu1_dir_arbi_cpu_rpful_t {
+	ZXIC_UINT32 smmu1_cfg_rpful;
+	ZXIC_UINT32 smmu1_cfg_wpful;
+} DPP_SE_SMMU1_DIR_ARBI_CPU_RPFUL_T;
+
+typedef struct dpp_se_smmu1_dir_arbi_wpful_t {
+	ZXIC_UINT32 smmu1_ser_wdir_pful;
+	ZXIC_UINT32 smmu1_cfg_wdir_pful;
+} DPP_SE_SMMU1_DIR_ARBI_WPFUL_T;
+
+typedef struct dpp_se_smmu1_cfg_wr_arbi_pful0_t {
+	ZXIC_UINT32 arbi_out_pful;
+	ZXIC_UINT32 cpu_wr_pful;
+} DPP_SE_SMMU1_CFG_WR_ARBI_PFUL0_T;
+
+typedef struct dpp_se_smmu1_cfg_wr_arbi_pful1_t {
+	ZXIC_UINT32 tm_wr_pful;
+	ZXIC_UINT32 stat_wr_pful;
+} DPP_SE_SMMU1_CFG_WR_ARBI_PFUL1_T;
+
+typedef struct dpp_se_smmu1_smmu1_wdone_pful_cfg_t {
+	ZXIC_UINT32 smmu1_wdone_pful_cfg;
+} DPP_SE_SMMU1_SMMU1_WDONE_PFUL_CFG_T;
+
+typedef struct dpp_se_smmu1_stat_rate_cfg_cnt_t {
+	ZXIC_UINT32 stat_rate_cfg_cnt;
+} DPP_SE_SMMU1_STAT_RATE_CFG_CNT_T;
+
+typedef struct dpp_se_smmu1_ftm_rate_cfg_cnt_t {
+	ZXIC_UINT32 ftm_rate_cfg_cnt;
+} DPP_SE_SMMU1_FTM_RATE_CFG_CNT_T;
+
+typedef struct dpp_se_smmu1_etm_rate_cfg_cnt_t {
+	ZXIC_UINT32 etm_rate_cfg_cnt;
+} DPP_SE_SMMU1_ETM_RATE_CFG_CNT_T;
+
+typedef struct dpp_se_smmu1_dir_rate_cfg_cnt_t {
+	ZXIC_UINT32 dir_rate_cfg_cnt;
+} DPP_SE_SMMU1_DIR_RATE_CFG_CNT_T;
+
+typedef struct dpp_se_smmu1_hash_rate_cfg_cnt_t {
+	ZXIC_UINT32 hash_rate_cfg_cnt;
+} DPP_SE_SMMU1_HASH_RATE_CFG_CNT_T;
+
+typedef struct dpp_se_smmu1_ftm_tbl_cfg_t {
+	ZXIC_UINT32 ftm_baddr;
+} DPP_SE_SMMU1_FTM_TBL_CFG_T;
+
+typedef struct dpp_se_smmu1_lpm_v4_as_tbl_cfg_t {
+	ZXIC_UINT32 lpm_v4_as_rsp_len;
+	ZXIC_UINT32 lpm_v4_as_ecc_en;
+	ZXIC_UINT32 lpm_v4_as_baddr;
+} DPP_SE_SMMU1_LPM_V4_AS_TBL_CFG_T;
+
+typedef struct dpp_se_smmu1_lpm_v4_tbl_cfg_t {
+	ZXIC_UINT32 lpm_v4_len;
+	ZXIC_UINT32 lpm_v4_ecc_en;
+	ZXIC_UINT32 lpm_v4_baddr;
+} DPP_SE_SMMU1_LPM_V4_TBL_CFG_T;
+
+typedef struct dpp_se_smmu1_lpm_v6_tbl_cfg_t {
+	ZXIC_UINT32 lpm_v6_len;
+	ZXIC_UINT32 lpm_v6_ecc_en;
+	ZXIC_UINT32 lpm_v6_baddr;
+} DPP_SE_SMMU1_LPM_V6_TBL_CFG_T;
+
+typedef struct dpp_se_smmu1_lpm_v6_as_tbl_cfg_t {
+	ZXIC_UINT32 lpm_v6_as_rsp_len;
+	ZXIC_UINT32 lpm_v6_as_ecc_en;
+	ZXIC_UINT32 lpm_v6_as_baddr;
+} DPP_SE_SMMU1_LPM_V6_AS_TBL_CFG_T;
+
+typedef struct dpp_se_smmu1_dma_tbl_cfg_t {
+	ZXIC_UINT32 dma_baddr;
+} DPP_SE_SMMU1_DMA_TBL_CFG_T;
+
+typedef struct dpp_se_smmu1_oam_tbl_cfg_t {
+	ZXIC_UINT32 oam_baddr;
+} DPP_SE_SMMU1_OAM_TBL_CFG_T;
+
+typedef struct dpp_se_smmu1_ctrl_rpar_cpu_pful_t {
+	ZXIC_UINT32 ctrl_rpar_cpu_pful;
+} DPP_SE_SMMU1_CTRL_RPAR_CPU_PFUL_T;
+
+typedef struct dpp_se_smmu1_cfg_ksch_dir_pful_t {
+	ZXIC_UINT32 cfg_ksch_dir_pful;
+} DPP_SE_SMMU1_CFG_KSCH_DIR_PFUL_T;
+
+typedef struct dpp_se_smmu1_cfg_ksch_hash_pful_t {
+	ZXIC_UINT32 cfg_ksch_hash_pful;
+} DPP_SE_SMMU1_CFG_KSCH_HASH_PFUL_T;
+
+typedef struct dpp_se_smmu1_cfg_ksch_lpm_pful_t {
+	ZXIC_UINT32 cfg_ksch_lpm_pful;
+} DPP_SE_SMMU1_CFG_KSCH_LPM_PFUL_T;
+
+typedef struct dpp_se_smmu1_cfg_ksch_lpm_as_pful_t {
+	ZXIC_UINT32 cfg_ksch_lpm_as_pful;
+} DPP_SE_SMMU1_CFG_KSCH_LPM_AS_PFUL_T;
+
+typedef struct dpp_se_smmu1_cfg_ksch_stat_pful_t {
+	ZXIC_UINT32 cfg_ksch_stat_pful;
+} DPP_SE_SMMU1_CFG_KSCH_STAT_PFUL_T;
+
+typedef struct dpp_se_smmu1_cfg_ksch_tm_pful_t {
+	ZXIC_UINT32 cfg_ksch_tm_pful;
+} DPP_SE_SMMU1_CFG_KSCH_TM_PFUL_T;
+
+typedef struct dpp_se_smmu1_cfg_ksch_oam_pful_t {
+	ZXIC_UINT32 cfg_ksch_oam_pful;
+} DPP_SE_SMMU1_CFG_KSCH_OAM_PFUL_T;
+
+typedef struct dpp_se_smmu1_cfg_ksch_dma_pful_t {
+	ZXIC_UINT32 cfg_ksch_dma_pful;
+} DPP_SE_SMMU1_CFG_KSCH_DMA_PFUL_T;
+
+typedef struct dpp_se_smmu1_ctrl_wfifo_cfg_t {
+	ZXIC_UINT32 ctrl_wfifo_cfg;
+} DPP_SE_SMMU1_CTRL_WFIFO_CFG_T;
+
+typedef struct dpp_se_smmu1_rsch_hash_ptr_cfg_t {
+	ZXIC_UINT32 rsch_hash_ptr_cfg;
+} DPP_SE_SMMU1_RSCH_HASH_PTR_CFG_T;
+
+typedef struct dpp_se_smmu1_rsch_lpm_ptr_cfg_t {
+	ZXIC_UINT32 rsch_lpm_ptr_cfg;
+} DPP_SE_SMMU1_RSCH_LPM_PTR_CFG_T;
+
+typedef struct dpp_se_smmu1_rsch_lpm_as_ptr_cfg_t {
+	ZXIC_UINT32 rsch_lpm_as_ptr_cfg;
+} DPP_SE_SMMU1_RSCH_LPM_AS_PTR_CFG_T;
+
+typedef struct dpp_se_smmu1_rsch_stat_ptr_cfg_t {
+	ZXIC_UINT32 rsch_stat_ptr_cfg;
+} DPP_SE_SMMU1_RSCH_STAT_PTR_CFG_T;
+
+typedef struct dpp_se_smmu1_rsch_oam_ptr_cfg_t {
+	ZXIC_UINT32 rsch_oam_ptr_cfg;
+} DPP_SE_SMMU1_RSCH_OAM_PTR_CFG_T;
+
+typedef struct dpp_se_smmu1_rschd_fifo_pept_cfg_t {
+	ZXIC_UINT32 rschd_fifo_pept_cfg;
+} DPP_SE_SMMU1_RSCHD_FIFO_PEPT_CFG_T;
+
+typedef struct dpp_se_smmu1_dir_fifo_pful_cfg_t {
+	ZXIC_UINT32 dir_fifo_pful_cfg;
+} DPP_SE_SMMU1_DIR_FIFO_PFUL_CFG_T;
+
+typedef struct dpp_se_smmu1_hash_fifo_pful_cfg_t {
+	ZXIC_UINT32 hash_fifo_pful_cfg;
+} DPP_SE_SMMU1_HASH_FIFO_PFUL_CFG_T;
+
+typedef struct dpp_se_smmu1_lpm_fifo_pful_cfg_t {
+	ZXIC_UINT32 lpm_fifo_pful_cfg;
+} DPP_SE_SMMU1_LPM_FIFO_PFUL_CFG_T;
+
+typedef struct dpp_se_smmu1_lpm_as_fifo_pful_cfg_t {
+	ZXIC_UINT32 lpm_as_fifo_pful_cfg;
+} DPP_SE_SMMU1_LPM_AS_FIFO_PFUL_CFG_T;
+
+typedef struct dpp_se_smmu1_stat_fifo_pful_cfg_t {
+	ZXIC_UINT32 stat_fifo_pful_cfg;
+} DPP_SE_SMMU1_STAT_FIFO_PFUL_CFG_T;
+
+typedef struct dpp_se_smmu1_ftm_fifo_pful_cfg_t {
+	ZXIC_UINT32 ftm_fifo_pful_cfg;
+} DPP_SE_SMMU1_FTM_FIFO_PFUL_CFG_T;
+
+typedef struct dpp_se_smmu1_etm_fifo_pful_cfg_t {
+	ZXIC_UINT32 etm_fifo_pful_cfg;
+} DPP_SE_SMMU1_ETM_FIFO_PFUL_CFG_T;
+
+typedef struct dpp_se_smmu1_oam_fifo_pful_cfg_t {
+	ZXIC_UINT32 oam_fifo_pful_cfg;
+} DPP_SE_SMMU1_OAM_FIFO_PFUL_CFG_T;
+
+typedef struct dpp_se_smmu1_dma_fifo_pful_cfg_t {
+	ZXIC_UINT32 dma_fifo_pful_cfg;
+} DPP_SE_SMMU1_DMA_FIFO_PFUL_CFG_T;
+
+typedef struct dpp_se_smmu1_cache_rsp_rr_fifo_cfg_t {
+	ZXIC_UINT32 rr_pfull_assert0;
+	ZXIC_UINT32 rr_pfull_negate0;
+} DPP_SE_SMMU1_CACHE_RSP_RR_FIFO_CFG_T;
+
+typedef struct dpp_se_smmu1_ddr_rsp_rr_fifo_cfg_t {
+	ZXIC_UINT32 rr_pfull_assert1;
+	ZXIC_UINT32 rr_pfull_negate1;
+} DPP_SE_SMMU1_DDR_RSP_RR_FIFO_CFG_T;
+
+typedef struct dpp_se_smmu1_cpu_cahce_fifo_cfg_t {
+	ZXIC_UINT32 smmu1_cahce_fwft_fifo_pfull_assert;
+	ZXIC_UINT32 smmu1_cahce_fwft_fifo_pfull_negate;
+} DPP_SE_SMMU1_CPU_CAHCE_FIFO_CFG_T;
+
+typedef struct dpp_se_smmu1_cache_rsp_fifo_cfg_t {
+	ZXIC_UINT32 rschd_fifo_pfull_assert;
+	ZXIC_UINT32 rschd_fifo_pfull_negate;
+} DPP_SE_SMMU1_CACHE_RSP_FIFO_CFG_T;
+
+typedef struct dpp_se_smmu1_test_state_t {
+	ZXIC_UINT32 test_state;
+} DPP_SE_SMMU1_TEST_STATE_T;
+
+typedef struct dpp_se_smmu1_cache_fifo_ept_t {
+	ZXIC_UINT32 cache_fifo_ept;
+} DPP_SE_SMMU1_CACHE_FIFO_EPT_T;
+
+typedef struct dpp_se_smmu1_rr_fifo_ept_t {
+	ZXIC_UINT32 rr_fifo_ept;
+} DPP_SE_SMMU1_RR_FIFO_EPT_T;
+
+typedef struct dpp_se_smmu1_wr_fifo_ept_t {
+	ZXIC_UINT32 dir_arbi_ept;
+} DPP_SE_SMMU1_WR_FIFO_EPT_T;
+
+typedef struct dpp_se_smmu1_wdone_fifo_ept_t {
+	ZXIC_UINT32 wdone_fifo_ept;
+} DPP_SE_SMMU1_WDONE_FIFO_EPT_T;
+
+typedef struct dpp_se_smmu1_kschd_fifo_ept0_t {
+	ZXIC_UINT32 kschd_fifo_ept0;
+} DPP_SE_SMMU1_KSCHD_FIFO_EPT0_T;
+
+typedef struct dpp_se_smmu1_cash_fifo_ept_t {
+	ZXIC_UINT32 cash_fifo_ept;
+} DPP_SE_SMMU1_CASH_FIFO_EPT_T;
+
+typedef struct dpp_se_smmu1_ctrl_fifo_ept_t {
+	ZXIC_UINT32 ctrl_fifo_ept;
+} DPP_SE_SMMU1_CTRL_FIFO_EPT_T;
+
+typedef struct dpp_se_smmu1_smmu1_rschd_ept3_t {
+	ZXIC_UINT32 rschd_fifo_ept3;
+} DPP_SE_SMMU1_SMMU1_RSCHD_EPT3_T;
+
+typedef struct dpp_se_smmu1_smmu1_rschd_ept2_t {
+	ZXIC_UINT32 rschd_fifo_ept2;
+} DPP_SE_SMMU1_SMMU1_RSCHD_EPT2_T;
+
+typedef struct dpp_se_smmu1_smmu1_rschd_ept1_t {
+	ZXIC_UINT32 rschd_fifo_ept1;
+} DPP_SE_SMMU1_SMMU1_RSCHD_EPT1_T;
+
+typedef struct dpp_se_smmu1_smmu1_rschd_ept0_t {
+	ZXIC_UINT32 rschd_fifo_ept0;
+} DPP_SE_SMMU1_SMMU1_RSCHD_EPT0_T;
+
+typedef struct dpp_se_smmu1_cash0_ecc_err_addr_t {
+	ZXIC_UINT32 cash0_ecc_err_addr;
+} DPP_SE_SMMU1_CASH0_ECC_ERR_ADDR_T;
+
+typedef struct dpp_se_smmu1_arbi_cpu_wr_rdy_t {
+	ZXIC_UINT32 arbi_cpu_wr_rdy;
+} DPP_SE_SMMU1_ARBI_CPU_WR_RDY_T;
+
+typedef struct dpp_se_smmu1_smmu1_int_0_en_t {
+	ZXIC_UINT32 smmu1_int_0_en;
+} DPP_SE_SMMU1_SMMU1_INT_0_EN_T;
+
+typedef struct dpp_se_smmu1_smmu1_int_0_mask_t {
+	ZXIC_UINT32 smmu1_int_0_mask;
+} DPP_SE_SMMU1_SMMU1_INT_0_MASK_T;
+
+typedef struct dpp_se_smmu1_smmu1_int_1_en_t {
+	ZXIC_UINT32 smmu1_int_1_en;
+} DPP_SE_SMMU1_SMMU1_INT_1_EN_T;
+
+typedef struct dpp_se_smmu1_smmu1_int_1_mask_t {
+	ZXIC_UINT32 smmu1_int_1_mask;
+} DPP_SE_SMMU1_SMMU1_INT_1_MASK_T;
+
+typedef struct dpp_se_smmu1_smmu1_int_2_en_t {
+	ZXIC_UINT32 smmu1_int_2_en;
+} DPP_SE_SMMU1_SMMU1_INT_2_EN_T;
+
+typedef struct dpp_se_smmu1_smmu1_int_2_mask_t {
+	ZXIC_UINT32 smmu1_int_2_mask;
+} DPP_SE_SMMU1_SMMU1_INT_2_MASK_T;
+
+typedef struct dpp_se_smmu1_smmu1_int_3_en_t {
+	ZXIC_UINT32 smmu1_int_3_en;
+} DPP_SE_SMMU1_SMMU1_INT_3_EN_T;
+
+typedef struct dpp_se_smmu1_smmu1_int_3_mask_t {
+	ZXIC_UINT32 smmu1_int_3_mask;
+} DPP_SE_SMMU1_SMMU1_INT_3_MASK_T;
+
+typedef struct dpp_se_smmu1_smmu1_int_0_status_t {
+	ZXIC_UINT32 smmu1_int_0_status;
+} DPP_SE_SMMU1_SMMU1_INT_0_STATUS_T;
+
+typedef struct dpp_se_smmu1_smmu1_int_1_status_t {
+	ZXIC_UINT32 smmu1_int_1_status;
+} DPP_SE_SMMU1_SMMU1_INT_1_STATUS_T;
+
+typedef struct dpp_se_smmu1_smmu1_int_2_status_t {
+	ZXIC_UINT32 smmu1_int_2_status;
+} DPP_SE_SMMU1_SMMU1_INT_2_STATUS_T;
+
+typedef struct dpp_se_smmu1_smmu1_int_3_status_t {
+	ZXIC_UINT32 smmu1_int_3_status;
+} DPP_SE_SMMU1_SMMU1_INT_3_STATUS_T;
+
+typedef struct dpp_se_smmu1_smmu1_int_status_t {
+	ZXIC_UINT32 smmu1_int_status;
+} DPP_SE_SMMU1_SMMU1_INT_STATUS_T;
+
+typedef struct dpp_se_smmu1_ctrl_to_cash7_0_fc_cnt_t {
+	ZXIC_UINT32 ctrl_to_cash7_0_fc_cnt;
+} DPP_SE_SMMU1_CTRL_TO_CASH7_0_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_cash7_0_to_ctrl_req_cnt_t {
+	ZXIC_UINT32 cash7_0_to_ctrl_req_cnt;
+} DPP_SE_SMMU1_CASH7_0_TO_CTRL_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_rschd_to_cache7_fc_cnt_t {
+	ZXIC_UINT32 rschd_to_cache7_fc_cnt;
+} DPP_SE_SMMU1_RSCHD_TO_CACHE7_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_cash7_to_cache_rsp_cnt_t {
+	ZXIC_UINT32 cash7_to_cache_rsp_cnt;
+} DPP_SE_SMMU1_CASH7_TO_CACHE_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_cash7_to_ctrl_fc_cnt_t {
+	ZXIC_UINT32 cash7_to_ctrl_fc_cnt;
+} DPP_SE_SMMU1_CASH7_TO_CTRL_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_ctrl_to_cash7_0_rsp_cnt_t {
+	ZXIC_UINT32 ctrl_to_cash7_0_rsp_cnt;
+} DPP_SE_SMMU1_CTRL_TO_CASH7_0_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_kschd_to_cache7_0_req_cnt_t {
+	ZXIC_UINT32 kschd_to_cache7_0_req_cnt;
+} DPP_SE_SMMU1_KSCHD_TO_CACHE7_0_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_cache7_0_to_kschd_fc_cnt_t {
+	ZXIC_UINT32 cache7_0_to_kschd_fc_cnt;
+} DPP_SE_SMMU1_CACHE7_0_TO_KSCHD_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_dma_to_smmu1_rd_req_cnt_t {
+	ZXIC_UINT32 dma_to_smmu1_rd_req_cnt;
+} DPP_SE_SMMU1_DMA_TO_SMMU1_RD_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_oam_to_kschd_req_cnt_t {
+	ZXIC_UINT32 oam_to_kschd_req_cnt;
+} DPP_SE_SMMU1_OAM_TO_KSCHD_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_oam_rr_state_rsp_cnt_t {
+	ZXIC_UINT32 oam_rr_state_rsp_cnt;
+} DPP_SE_SMMU1_OAM_RR_STATE_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_oam_clash_info_cnt_t {
+	ZXIC_UINT32 oam_clash_info_cnt;
+} DPP_SE_SMMU1_OAM_CLASH_INFO_CNT_T;
+
+typedef struct dpp_se_smmu1_oam_to_rr_req_cnt_t {
+	ZXIC_UINT32 oam_to_rr_req_cnt;
+} DPP_SE_SMMU1_OAM_TO_RR_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_lpm_as_to_kschd_req_cnt_t {
+	ZXIC_UINT32 lpm_as_to_kschd_req_cnt;
+} DPP_SE_SMMU1_LPM_AS_TO_KSCHD_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_lpm_as_rr_state_rsp_cnt_t {
+	ZXIC_UINT32 lpm_as_rr_state_rsp_cnt;
+} DPP_SE_SMMU1_LPM_AS_RR_STATE_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_lpm_as_clash_info_cnt_t {
+	ZXIC_UINT32 lpm_as_clash_info_cnt;
+} DPP_SE_SMMU1_LPM_AS_CLASH_INFO_CNT_T;
+
+typedef struct dpp_se_smmu1_lpm_as_to_rr_req_cnt_t {
+	ZXIC_UINT32 lpm_as_to_rr_req_cnt;
+} DPP_SE_SMMU1_LPM_AS_TO_RR_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_lpm_to_kschd_req_cnt_t {
+	ZXIC_UINT32 lpm_to_kschd_req_cnt;
+} DPP_SE_SMMU1_LPM_TO_KSCHD_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_lpm_rr_state_rsp_cnt_t {
+	ZXIC_UINT32 lpm_rr_state_rsp_cnt;
+} DPP_SE_SMMU1_LPM_RR_STATE_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_lpm_clash_info_cnt_t {
+	ZXIC_UINT32 lpm_clash_info_cnt;
+} DPP_SE_SMMU1_LPM_CLASH_INFO_CNT_T;
+
+typedef struct dpp_se_smmu1_lpm_to_rr_req_cnt_t {
+	ZXIC_UINT32 lpm_to_rr_req_cnt;
+} DPP_SE_SMMU1_LPM_TO_RR_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_hash3_0_to_kschd_req_cnt_t {
+	ZXIC_UINT32 hash3_0_to_kschd_req_cnt;
+} DPP_SE_SMMU1_HASH3_0_TO_KSCHD_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_hash3_0_rr_state_rsp_cnt_t {
+	ZXIC_UINT32 hash3_0_rr_state_rsp_cnt;
+} DPP_SE_SMMU1_HASH3_0_RR_STATE_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_hash3_0_clash_info_cnt_t {
+	ZXIC_UINT32 hash3_0_clash_info_cnt;
+} DPP_SE_SMMU1_HASH3_0_CLASH_INFO_CNT_T;
+
+typedef struct dpp_se_smmu1_hash3_0_to_rr_req_cnt_t {
+	ZXIC_UINT32 hash3_0_to_rr_req_cnt;
+} DPP_SE_SMMU1_HASH3_0_TO_RR_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_dir3_0_to_kschd_req_cnt_t {
+	ZXIC_UINT32 dir3_0_to_kschd_req_cnt;
+} DPP_SE_SMMU1_DIR3_0_TO_KSCHD_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_dir3_0_clash_info_cnt_t {
+	ZXIC_UINT32 dir3_0_clash_info_cnt;
+} DPP_SE_SMMU1_DIR3_0_CLASH_INFO_CNT_T;
+
+typedef struct dpp_se_smmu1_dir_tbl_wr_req_cnt_t {
+	ZXIC_UINT32 dir_tbl_wr_req_cnt;
+} DPP_SE_SMMU1_DIR_TBL_WR_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_warbi_to_dir_tbl_warbi_fc_cnt_t {
+	ZXIC_UINT32 warbi_to_dir_tbl_warbi_fc_cnt;
+} DPP_SE_SMMU1_WARBI_TO_DIR_TBL_WARBI_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_dir3_0_to_bank_rr_req_cnt_t {
+	ZXIC_UINT32 dir3_0_to_bank_rr_req_cnt;
+} DPP_SE_SMMU1_DIR3_0_TO_BANK_RR_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_kschd_to_dir3_0_fc_cnt_t {
+	ZXIC_UINT32 kschd_to_dir3_0_fc_cnt;
+} DPP_SE_SMMU1_KSCHD_TO_DIR3_0_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_dir3_0_rr_state_rsp_cnt_t {
+	ZXIC_UINT32 dir3_0_rr_state_rsp_cnt;
+} DPP_SE_SMMU1_DIR3_0_RR_STATE_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_wr_done_to_warbi_fc_cnt_t {
+	ZXIC_UINT32 wr_done_to_warbi_fc_cnt;
+} DPP_SE_SMMU1_WR_DONE_TO_WARBI_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_wr_done_ptr_req_cnt_t {
+	ZXIC_UINT32 wr_done_ptr_req_cnt;
+} DPP_SE_SMMU1_WR_DONE_PTR_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_ctrl7_0_to_warbi_fc_cnt_t {
+	ZXIC_UINT32 ctrl7_0_to_warbi_fc_cnt;
+} DPP_SE_SMMU1_CTRL7_0_TO_WARBI_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_warbi_to_ctrl7_0_wr_req_cnt_t {
+	ZXIC_UINT32 warbi_to_ctrl7_0_wr_req_cnt;
+} DPP_SE_SMMU1_WARBI_TO_CTRL7_0_WR_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_warbi_to_cash7_0_wr_req_cnt_t {
+	ZXIC_UINT32 warbi_to_cash7_0_wr_req_cnt;
+} DPP_SE_SMMU1_WARBI_TO_CASH7_0_WR_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_warbi_to_cpu_wr_fc_cnt_t {
+	ZXIC_UINT32 warbi_to_cpu_wr_fc_cnt;
+} DPP_SE_SMMU1_WARBI_TO_CPU_WR_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_cpu_wr_req_cnt_t {
+	ZXIC_UINT32 cpu_wr_req_cnt;
+} DPP_SE_SMMU1_CPU_WR_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_ctrl7_0_to_cpu_rd_rsp_cnt_t {
+	ZXIC_UINT32 ctrl7_0_to_cpu_rd_rsp_cnt;
+} DPP_SE_SMMU1_CTRL7_0_TO_CPU_RD_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_cpu_to_ctrl7_0_rd_req_cnt_t {
+	ZXIC_UINT32 cpu_to_ctrl7_0_rd_req_cnt;
+} DPP_SE_SMMU1_CPU_TO_CTRL7_0_RD_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_cpu_rd_dir_tbl_rsp_cnt_t {
+	ZXIC_UINT32 cpu_rd_dir_tbl_rsp_cnt;
+} DPP_SE_SMMU1_CPU_RD_DIR_TBL_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_cpu_to_dir_tbl_rd_wr_req_cnt_t {
+	ZXIC_UINT32 cpu_to_dir_tbl_rd_wr_req_cnt;
+} DPP_SE_SMMU1_CPU_TO_DIR_TBL_RD_WR_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_mmu_7_0_rsp_fc_cnt_t {
+	ZXIC_UINT32 smmu1_to_mmu_7_0_rsp_fc_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_MMU_7_0_RSP_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_mmu_7_0_to_smmu1_rd_rsp_cnt_t {
+	ZXIC_UINT32 mmu_7_0_to_smmu1_rd_rsp_cnt;
+} DPP_SE_SMMU1_MMU_7_0_TO_SMMU1_RD_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_mmu_7_0_to_smmu1_rd_fc_cnt_t {
+	ZXIC_UINT32 mmu_7_0_to_smmu1_rd_fc_cnt;
+} DPP_SE_SMMU1_MMU_7_0_TO_SMMU1_RD_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_mmu_7_rd_req_cnt_t {
+	ZXIC_UINT32 smmu1_to_mmu_7_rd_req_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_MMU_7_RD_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_mmu_7_to_smmu1_wr_fc_cnt_t {
+	ZXIC_UINT32 mmu_7_to_smmu1_wr_fc_cnt;
+} DPP_SE_SMMU1_MMU_7_TO_SMMU1_WR_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_mmu_7_0_wr_req_cnt_t {
+	ZXIC_UINT32 smmu1_to_mmu_7_0_wr_req_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_MMU_7_0_WR_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_se_to_smmu1_wr_rsp_fc_cnt_t {
+	ZXIC_UINT32 se_to_smmu1_wr_rsp_fc_cnt;
+} DPP_SE_SMMU1_SE_TO_SMMU1_WR_RSP_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_se_wr_rsp_cnt_t {
+	ZXIC_UINT32 smmu1_to_se_wr_rsp_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_SE_WR_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_ddr7_0_wr_rsp_cnt_t {
+	ZXIC_UINT32 ddr7_0_wr_rsp_cnt;
+} DPP_SE_SMMU1_DDR7_0_WR_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_as_fc_cnt_t {
+	ZXIC_UINT32 smmu1_to_as_fc_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_AS_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_as_to_smmu1_wr_req_cnt_t {
+	ZXIC_UINT32 as_to_smmu1_wr_req_cnt;
+} DPP_SE_SMMU1_AS_TO_SMMU1_WR_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_se_parser_fc_cnt_t {
+	ZXIC_UINT32 smmu1_to_se_parser_fc_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_SE_PARSER_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_se_parser_to_smmu1_req_cnt_t {
+	ZXIC_UINT32 se_parser_to_smmu1_req_cnt;
+} DPP_SE_SMMU1_SE_PARSER_TO_SMMU1_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_etm_wr_fc_cnt_t {
+	ZXIC_UINT32 smmu1_to_etm_wr_fc_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_ETM_WR_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_etm_wr_req_cnt_t {
+	ZXIC_UINT32 etm_wr_req_cnt;
+} DPP_SE_SMMU1_ETM_WR_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_ftm_wr_fc_cnt_t {
+	ZXIC_UINT32 smmu1_to_ftm_wr_fc_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_FTM_WR_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_ftm_wr_req_cnt_t {
+	ZXIC_UINT32 ftm_wr_req_cnt;
+} DPP_SE_SMMU1_FTM_WR_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_state_wr_fc_cnt_t {
+	ZXIC_UINT32 smmu1_to_state_wr_fc_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_STATE_WR_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_state_wr_req_cnt_t {
+	ZXIC_UINT32 state_wr_req_cnt;
+} DPP_SE_SMMU1_STATE_WR_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_se_to_dma_rsp_cnt_t {
+	ZXIC_UINT32 se_to_dma_rsp_cnt;
+} DPP_SE_SMMU1_SE_TO_DMA_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_se_to_dma_fc_cnt_t {
+	ZXIC_UINT32 se_to_dma_fc_cnt;
+} DPP_SE_SMMU1_SE_TO_DMA_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_oam_to_smmu1_fc_cnt_t {
+	ZXIC_UINT32 oam_to_smmu1_fc_cnt;
+} DPP_SE_SMMU1_OAM_TO_SMMU1_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_oam_rsp_cnt_t {
+	ZXIC_UINT32 smmu1_to_oam_rsp_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_OAM_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_oam_fc_cnt_t {
+	ZXIC_UINT32 smmu1_to_oam_fc_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_OAM_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_oam_to_smmu1_req_cnt_t {
+	ZXIC_UINT32 oam_to_smmu1_req_cnt;
+} DPP_SE_SMMU1_OAM_TO_SMMU1_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_etm_rsp_cnt_t {
+	ZXIC_UINT32 smmu1_to_etm_rsp_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_ETM_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_ftm_rsp_cnt_t {
+	ZXIC_UINT32 smmu1_to_ftm_rsp_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_FTM_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_etm_fc_cnt_t {
+	ZXIC_UINT32 smmu1_to_etm_fc_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_ETM_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_etm_to_smmu1_req_cnt_t {
+	ZXIC_UINT32 etm_to_smmu1_req_cnt;
+} DPP_SE_SMMU1_ETM_TO_SMMU1_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_ftm_fc_cnt_t {
+	ZXIC_UINT32 smmu1_to_ftm_fc_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_FTM_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_ftm_to_smmu1_req_cnt_t {
+	ZXIC_UINT32 ftm_to_smmu1_req_cnt;
+} DPP_SE_SMMU1_FTM_TO_SMMU1_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_stat_rsp_cnt_t {
+	ZXIC_UINT32 smmu1_to_stat_rsp_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_STAT_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_stat_fc_cnt_t {
+	ZXIC_UINT32 smmu1_to_stat_fc_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_STAT_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_stat_to_smmu1_req_cnt_t {
+	ZXIC_UINT32 stat_to_smmu1_req_cnt;
+} DPP_SE_SMMU1_STAT_TO_SMMU1_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_lpm_as_to_smmu1_fc_cnt_t {
+	ZXIC_UINT32 lpm_as_to_smmu1_fc_cnt;
+} DPP_SE_SMMU1_LPM_AS_TO_SMMU1_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_lpm_to_smmu1_fc_cnt_t {
+	ZXIC_UINT32 lpm_to_smmu1_fc_cnt;
+} DPP_SE_SMMU1_LPM_TO_SMMU1_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_lpm_as_rsp_cnt_t {
+	ZXIC_UINT32 smmu1_to_lpm_as_rsp_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_LPM_AS_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_lpm_rsp_cnt_t {
+	ZXIC_UINT32 smmu1_to_lpm_rsp_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_LPM_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_lpm_as_fc_cnt_t {
+	ZXIC_UINT32 smmu1_to_lpm_as_fc_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_LPM_AS_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_lpm_fc_cnt_t {
+	ZXIC_UINT32 smmu1_to_lpm_fc_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_LPM_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_lpm_as_to_smmu1_req_cnt_t {
+	ZXIC_UINT32 lpm_as_to_smmu1_req_cnt;
+} DPP_SE_SMMU1_LPM_AS_TO_SMMU1_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_lpm_to_smmu1_req_cnt_t {
+	ZXIC_UINT32 lpm_to_smmu1_req_cnt;
+} DPP_SE_SMMU1_LPM_TO_SMMU1_REQ_CNT_T;
+
+typedef struct dpp_se_smmu1_hash3_0_to_smmu1_fc_cnt_t {
+	ZXIC_UINT32 hash3_0_to_smmu1_fc_cnt;
+} DPP_SE_SMMU1_HASH3_0_TO_SMMU1_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_hash3_0_rsp_cnt_t {
+	ZXIC_UINT32 smmu1_to_hash3_0_rsp_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_HASH3_0_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_hash3_0_fc_cnt_t {
+	ZXIC_UINT32 smmu1_to_hash3_0_fc_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_HASH3_0_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_hash3_0_to_smmu1_cnt_t {
+	ZXIC_UINT32 hash3_0_to_smmu1_cnt;
+} DPP_SE_SMMU1_HASH3_0_TO_SMMU1_CNT_T;
+
+typedef struct dpp_se_smmu1_se_to_smmu1_dir3_0_rsp_fc_cnt_t {
+	ZXIC_UINT32 se_to_smmu1_dir3_0_rsp_fc_cnt;
+} DPP_SE_SMMU1_SE_TO_SMMU1_DIR3_0_RSP_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_se_dir3_0_rsp_cnt_t {
+	ZXIC_UINT32 smmu1_to_se_dir3_0_rsp_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_SE_DIR3_0_RSP_CNT_T;
+
+typedef struct dpp_se_smmu1_smmu1_to_se_dir3_0_fc_cnt_t {
+	ZXIC_UINT32 smmu1_to_se_dir3_0_fc_cnt;
+} DPP_SE_SMMU1_SMMU1_TO_SE_DIR3_0_FC_CNT_T;
+
+typedef struct dpp_se_smmu1_se_to_smmu1_dir3_0_cnt_t {
+	ZXIC_UINT32 se_to_smmu1_dir3_0_cnt;
+} DPP_SE_SMMU1_SE_TO_SMMU1_DIR3_0_CNT_T;
+
+typedef struct dpp_se_smmu1_cache7_0_to_rschd_rsp_cnt_t {
+	ZXIC_UINT32 cache7_0_to_rschd_rsp_cnt;
+} DPP_SE_SMMU1_CACHE7_0_TO_RSCHD_RSP_CNT_T;
+
+typedef struct dpp_se_cmmu_ddr_rw_addr_t {
+	ZXIC_UINT32 ddr_wr;
+} DPP_SE_CMMU_DDR_RW_ADDR_T;
+
+typedef struct dpp_se_cmmu_ddr_rw_mode_t {
+	ZXIC_UINT32 ddr_rw_flag;
+	ZXIC_UINT32 ddr_rw_mode;
+} DPP_SE_CMMU_DDR_RW_MODE_T;
+
+typedef struct dpp_se_cmmu_cp_cmd_t {
+	ZXIC_UINT32 stat_tbl_baddr;
+} DPP_SE_CMMU_CP_CMD_T;
+
+typedef struct dpp_se_cmmu_cpu_ind_rd_done_t {
+	ZXIC_UINT32 cpu_ind_rd_done;
+} DPP_SE_CMMU_CPU_IND_RD_DONE_T;
+
+typedef struct dpp_se_cmmu_cpu_ind_rdat0_t {
+	ZXIC_UINT32 cpu_ind_rdat0;
+} DPP_SE_CMMU_CPU_IND_RDAT0_T;
+
+typedef struct dpp_se_cmmu_cpu_ind_rdat1_t {
+	ZXIC_UINT32 cpu_ind_rdat1;
+} DPP_SE_CMMU_CPU_IND_RDAT1_T;
+
+typedef struct dpp_se_cmmu_cpu_ind_rdat2_t {
+	ZXIC_UINT32 cpu_ind_rdat2;
+} DPP_SE_CMMU_CPU_IND_RDAT2_T;
+
+typedef struct dpp_se_cmmu_cpu_ind_rdat3_t {
+	ZXIC_UINT32 cpu_ind_rdat3;
+} DPP_SE_CMMU_CPU_IND_RDAT3_T;
+
+typedef struct dpp_se_cmmu_cpu_ddr_fifo_almful_t {
+	ZXIC_UINT32 cpu_ddr_fifo_almful;
+} DPP_SE_CMMU_CPU_DDR_FIFO_ALMFUL_T;
+
+typedef struct dpp_se_cmmu_debug_cnt_mode_t {
+	ZXIC_UINT32 cnt_rd_mode;
+	ZXIC_UINT32 cnt_overflow_mode;
+} DPP_SE_CMMU_DEBUG_CNT_MODE_T;
+
+typedef struct dpp_se_cmmu_cmmu_pful_cfg_t {
+	ZXIC_UINT32 alu_cmd_pful_negate;
+	ZXIC_UINT32 alu_cmd_pful_assert;
+} DPP_SE_CMMU_CMMU_PFUL_CFG_T;
+
+typedef struct dpp_se_cmmu_cmmu_stat_pful_cfg_t {
+	ZXIC_UINT32 cmmu_stat_pful_negate;
+	ZXIC_UINT32 cmmu_stat_pful_assert;
+} DPP_SE_CMMU_CMMU_STAT_PFUL_CFG_T;
+
+typedef struct dpp_se_cmmu_stat_overflow_mode_t {
+	ZXIC_UINT32 stat_overflow_mode;
+} DPP_SE_CMMU_STAT_OVERFLOW_MODE_T;
+
+typedef struct dpp_se_cmmu_cmmu_cp_fifo_pful_t {
+	ZXIC_UINT32 cmmu_cp_fifo_pful;
+} DPP_SE_CMMU_CMMU_CP_FIFO_PFUL_T;
+
+typedef struct dpp_se_cmmu_ddr_wr_dat0_t {
+	ZXIC_UINT32 ddr_wr_dat0;
+} DPP_SE_CMMU_DDR_WR_DAT0_T;
+
+typedef struct dpp_se_cmmu_ddr_wr_dat1_t {
+	ZXIC_UINT32 ddr_wr_dat1;
+} DPP_SE_CMMU_DDR_WR_DAT1_T;
+
+typedef struct dpp_se_cmmu_cmmu_int_unmask_flag_t {
+	ZXIC_UINT32 cmmu_int_unmask_flag;
+} DPP_SE_CMMU_CMMU_INT_UNMASK_FLAG_T;
+
+typedef struct dpp_se_cmmu_cmmu_int_en_t {
+	ZXIC_UINT32 cmmu_int_en12;
+	ZXIC_UINT32 cmmu_int_en11;
+	ZXIC_UINT32 cmmu_int_en10;
+	ZXIC_UINT32 cmmu_int_en9;
+	ZXIC_UINT32 cmmu_int_en8;
+	ZXIC_UINT32 cmmu_int_en7;
+	ZXIC_UINT32 cmmu_int_en6;
+	ZXIC_UINT32 cmmu_int_en5;
+	ZXIC_UINT32 cmmu_int_en4;
+	ZXIC_UINT32 cmmu_int_en3;
+	ZXIC_UINT32 cmmu_int_en2;
+	ZXIC_UINT32 cmmu_int_en1;
+	ZXIC_UINT32 cmmu_int_en0;
+} DPP_SE_CMMU_CMMU_INT_EN_T;
+
+typedef struct dpp_se_cmmu_cmmu_int_mask_t {
+	ZXIC_UINT32 cmmu_int_mask12;
+	ZXIC_UINT32 cmmu_int_mask11;
+	ZXIC_UINT32 cmmu_int_mask10;
+	ZXIC_UINT32 cmmu_int_mask9;
+	ZXIC_UINT32 cmmu_int_mask8;
+	ZXIC_UINT32 cmmu_int_mask7;
+	ZXIC_UINT32 cmmu_int_mask6;
+	ZXIC_UINT32 cmmu_int_mask5;
+	ZXIC_UINT32 cmmu_int_mask4;
+	ZXIC_UINT32 cmmu_int_mask3;
+	ZXIC_UINT32 cmmu_int_mask2;
+	ZXIC_UINT32 cmmu_int_mask1;
+	ZXIC_UINT32 cmmu_int_mask0;
+} DPP_SE_CMMU_CMMU_INT_MASK_T;
+
+typedef struct dpp_se_cmmu_cmmu_int_status_t {
+	ZXIC_UINT32 cmmu_int_status12;
+	ZXIC_UINT32 cmmu_int_status11;
+	ZXIC_UINT32 cmmu_int_status10;
+	ZXIC_UINT32 cmmu_int_status9;
+	ZXIC_UINT32 cmmu_int_status8;
+	ZXIC_UINT32 cmmu_int_status7;
+	ZXIC_UINT32 cmmu_int_status6;
+	ZXIC_UINT32 cmmu_int_status5;
+	ZXIC_UINT32 cmmu_int_status4;
+	ZXIC_UINT32 cmmu_int_status3;
+	ZXIC_UINT32 cmmu_int_status2;
+	ZXIC_UINT32 cmmu_int_status1;
+	ZXIC_UINT32 cmmu_int_status0;
+} DPP_SE_CMMU_CMMU_INT_STATUS_T;
+
+typedef struct dpp_se_cmmu_stat_cmmu_req_cnt_t {
+	ZXIC_UINT32 stat_cmmu_req_cnt;
+} DPP_SE_CMMU_STAT_CMMU_REQ_CNT_T;
+
+typedef struct dpp_se_cmmu_cmmu_fc0_cnt_t {
+	ZXIC_UINT32 cmmu_stat_rdy;
+} DPP_SE_CMMU_CMMU_FC0_CNT_T;
+
+typedef struct dpp_se_cmmu_cmmu_fc1_cnt_t {
+	ZXIC_UINT32 smmu1_cmmu_wr_rdy;
+} DPP_SE_CMMU_CMMU_FC1_CNT_T;
+
+typedef struct dpp_se_cmmu_cmmu_fc2_cnt_t {
+	ZXIC_UINT32 smmu1_cmmu_rd_rdy;
+} DPP_SE_CMMU_CMMU_FC2_CNT_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_stat4k_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_stat4k_reg.h
index f55a9cbc161c7b5dfe67973a15c5204a19817e4f..d30d919bcb99234d34122bbcc295bec92e5eb27d 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_stat4k_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_stat4k_reg.h
@@ -3,40 +3,35 @@
 #define _DPP_STAT4K_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_stat4k_etcam_block0_7_port_id_cfg_t
-{
-    ZXIC_UINT32 block7_port_id;
-    ZXIC_UINT32 block6_port_id;
-    ZXIC_UINT32 block5_port_id;
-    ZXIC_UINT32 block4_port_id;
-    ZXIC_UINT32 block3_port_id;
-    ZXIC_UINT32 block2_port_id;
-    ZXIC_UINT32 block1_port_id;
-    ZXIC_UINT32 block0_port_id;
-}DPP_STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFG_T;
-
-typedef struct dpp_stat4k_etcam_block0_3_base_addr_cfg_t
-{
-    ZXIC_UINT32 block3_base_addr_cfg;
-    ZXIC_UINT32 block2_base_addr_cfg;
-    ZXIC_UINT32 block1_base_addr_cfg;
-    ZXIC_UINT32 block0_base_addr_cfg;
-}DPP_STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFG_T;
-
-typedef struct dpp_stat4k_etcam_block4_7_base_addr_cfg_t
-{
-    ZXIC_UINT32 block7_base_addr_cfg;
-    ZXIC_UINT32 block6_base_addr_cfg;
-    ZXIC_UINT32 block5_base_addr_cfg;
-    ZXIC_UINT32 block4_base_addr_cfg;
-}DPP_STAT4K_ETCAM_BLOCK4_7_BASE_ADDR_CFG_T;
-
+typedef struct dpp_stat4k_etcam_block0_7_port_id_cfg_t {
+	ZXIC_UINT32 block7_port_id;
+	ZXIC_UINT32 block6_port_id;
+	ZXIC_UINT32 block5_port_id;
+	ZXIC_UINT32 block4_port_id;
+	ZXIC_UINT32 block3_port_id;
+	ZXIC_UINT32 block2_port_id;
+	ZXIC_UINT32 block1_port_id;
+	ZXIC_UINT32 block0_port_id;
+} DPP_STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFG_T;
+
+typedef struct dpp_stat4k_etcam_block0_3_base_addr_cfg_t {
+	ZXIC_UINT32 block3_base_addr_cfg;
+	ZXIC_UINT32 block2_base_addr_cfg;
+	ZXIC_UINT32 block1_base_addr_cfg;
+	ZXIC_UINT32 block0_base_addr_cfg;
+} DPP_STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFG_T;
+
+typedef struct dpp_stat4k_etcam_block4_7_base_addr_cfg_t {
+	ZXIC_UINT32 block7_base_addr_cfg;
+	ZXIC_UINT32 block6_base_addr_cfg;
+	ZXIC_UINT32 block5_base_addr_cfg;
+	ZXIC_UINT32 block4_base_addr_cfg;
+} DPP_STAT4K_ETCAM_BLOCK4_7_BASE_ADDR_CFG_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_stat_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_stat_reg.h
index 1ccb40bd0713aba1d662548f77ca847cde3d6d86..f4e474bb2db844c6a44ca4f292175ebc2831289f 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_stat_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_stat_reg.h
@@ -3,2360 +3,2062 @@
 #define _DPP_STAT_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_stat_stat_cfg_cpu_ind_eram_wdat0_t
-{
-    ZXIC_UINT32 cpu_ind_eram_wdat0;
-}DPP_STAT_STAT_CFG_CPU_IND_ERAM_WDAT0_T;
-
-typedef struct dpp_stat_stat_cfg_etm_port_sel_cfg_t
-{
-    ZXIC_UINT32 etm_port0_sel_cfg;
-    ZXIC_UINT32 etm_port1_sel_cfg;
-    ZXIC_UINT32 etm_port2_sel_cfg;
-    ZXIC_UINT32 etm_port3_sel_cfg;
-}DPP_STAT_STAT_CFG_ETM_PORT_SEL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_tm_stat_cfg_t
-{
-    ZXIC_UINT32 stat_overflow_mode;
-    ZXIC_UINT32 tm_stat_mode_cfg;
-    ZXIC_UINT32 tm_flow_control_cfg;
-}DPP_STAT_STAT_CFG_TM_STAT_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_ppu_eram_depth_t
-{
-    ZXIC_UINT32 ppu_eram_depth;
-}DPP_STAT_STAT_CFG_PPU_ERAM_DEPTH_T;
-
-typedef struct dpp_stat_stat_cfg_ppu_eram_base_addr_t
-{
-    ZXIC_UINT32 ppu_eram_base_addr;
-}DPP_STAT_STAT_CFG_PPU_ERAM_BASE_ADDR_T;
-
-typedef struct dpp_stat_stat_cfg_ppu_ddr_base_addr_t
-{
-    ZXIC_UINT32 ppu_ddr_base_addr;
-}DPP_STAT_STAT_CFG_PPU_DDR_BASE_ADDR_T;
-
-typedef struct dpp_stat_stat_cfg_plcr0_base_addr_t
-{
-    ZXIC_UINT32 plcr0_base_addr;
-}DPP_STAT_STAT_CFG_PLCR0_BASE_ADDR_T;
-
-typedef struct dpp_stat_stat_cfg_etm_stat_start_addr_cfg_t
-{
-    ZXIC_UINT32 etm_stat_start_addr_cfg;
-}DPP_STAT_STAT_CFG_ETM_STAT_START_ADDR_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_etm_stat_depth_cfg_t
-{
-    ZXIC_UINT32 etm_stat_depth_cfg;
-}DPP_STAT_STAT_CFG_ETM_STAT_DEPTH_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_cycle_mov_en_cfg_t
-{
-    ZXIC_UINT32 cycle_mov_en_cfg;
-}DPP_STAT_STAT_CFG_CYCLE_MOV_EN_CFG_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat0_t
-{
-    ZXIC_UINT32 wdat0;
-}DPP_STAT_ETCAM_CPU_IND_WDAT0_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_ctrl_tmp0_t
-{
-    ZXIC_UINT32 reg_tcam_flag;
-    ZXIC_UINT32 flush;
-    ZXIC_UINT32 rd_wr;
-    ZXIC_UINT32 wr_mode;
-    ZXIC_UINT32 dat_or_mask;
-    ZXIC_UINT32 ram_sel;
-    ZXIC_UINT32 addr;
-}DPP_STAT_ETCAM_CPU_IND_CTRL_TMP0_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_ctrl_tmp1_t
-{
-    ZXIC_UINT32 row_or_col_msk;
-    ZXIC_UINT32 vben;
-    ZXIC_UINT32 vbit;
-}DPP_STAT_ETCAM_CPU_IND_CTRL_TMP1_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_rd_done_t
-{
-    ZXIC_UINT32 cpu_ind_rd_done;
-}DPP_STAT_ETCAM_CPU_IND_RD_DONE_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat0_t
-{
-    ZXIC_UINT32 cpu_rdat0;
-}DPP_STAT_ETCAM_CPU_RDAT0_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat1_t
-{
-    ZXIC_UINT32 cpu_rdat1;
-}DPP_STAT_ETCAM_CPU_RDAT1_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat2_t
-{
-    ZXIC_UINT32 cpu_rdat2;
-}DPP_STAT_ETCAM_CPU_RDAT2_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat3_t
-{
-    ZXIC_UINT32 cpu_rdat3;
-}DPP_STAT_ETCAM_CPU_RDAT3_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat4_t
-{
-    ZXIC_UINT32 cpu_rdat4;
-}DPP_STAT_ETCAM_CPU_RDAT4_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat5_t
-{
-    ZXIC_UINT32 cpu_rdat5;
-}DPP_STAT_ETCAM_CPU_RDAT5_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat6_t
-{
-    ZXIC_UINT32 cpu_rdat6;
-}DPP_STAT_ETCAM_CPU_RDAT6_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat7_t
-{
-    ZXIC_UINT32 cpu_rdat7;
-}DPP_STAT_ETCAM_CPU_RDAT7_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat8_t
-{
-    ZXIC_UINT32 cpu_rdat8;
-}DPP_STAT_ETCAM_CPU_RDAT8_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat9_t
-{
-    ZXIC_UINT32 cpu_rdat9;
-}DPP_STAT_ETCAM_CPU_RDAT9_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat10_t
-{
-    ZXIC_UINT32 cpu_rdat10;
-}DPP_STAT_ETCAM_CPU_RDAT10_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat11_t
-{
-    ZXIC_UINT32 cpu_rdat11;
-}DPP_STAT_ETCAM_CPU_RDAT11_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat12_t
-{
-    ZXIC_UINT32 cpu_rdat12;
-}DPP_STAT_ETCAM_CPU_RDAT12_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat13_t
-{
-    ZXIC_UINT32 cpu_rdat13;
-}DPP_STAT_ETCAM_CPU_RDAT13_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat14_t
-{
-    ZXIC_UINT32 cpu_rdat14;
-}DPP_STAT_ETCAM_CPU_RDAT14_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat15_t
-{
-    ZXIC_UINT32 cpu_rdat15;
-}DPP_STAT_ETCAM_CPU_RDAT15_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat16_t
-{
-    ZXIC_UINT32 cpu_rdat16;
-}DPP_STAT_ETCAM_CPU_RDAT16_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat17_t
-{
-    ZXIC_UINT32 cpu_rdat17;
-}DPP_STAT_ETCAM_CPU_RDAT17_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat18_t
-{
-    ZXIC_UINT32 cpu_rdat18;
-}DPP_STAT_ETCAM_CPU_RDAT18_T;
-
-typedef struct dpp_stat_etcam_cpu_rdat19_t
-{
-    ZXIC_UINT32 cpu_rdat19;
-}DPP_STAT_ETCAM_CPU_RDAT19_T;
-
-typedef struct dpp_stat_etcam_qvbo_t
-{
-    ZXIC_UINT32 qvbo;
-}DPP_STAT_ETCAM_QVBO_T;
-
-typedef struct dpp_stat_etcam_cnt_overflow_mode_t
-{
-    ZXIC_UINT32 cnt_rd_mode;
-    ZXIC_UINT32 cnt_overflow_mode;
-}DPP_STAT_ETCAM_CNT_OVERFLOW_MODE_T;
-
-typedef struct dpp_stat_car0_cara_queue_ram0_159_0_t
-{
-    ZXIC_UINT32 cara_drop;
-    ZXIC_UINT32 cara_plcr_en;
-    ZXIC_UINT32 cara_profile_id;
-    ZXIC_UINT32 cara_tq_h;
-    ZXIC_UINT32 cara_tq_l;
-    ZXIC_UINT32 cara_ted;
-    ZXIC_UINT32 cara_tcd;
-    ZXIC_UINT32 cara_tei;
-    ZXIC_UINT32 cara_tci;
-}DPP_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T;
-
-typedef struct dpp_stat_car0_cara_profile_ram1_255_0_t
-{
-    ZXIC_UINT32 cara_profile_wr;
-    ZXIC_UINT32 cara_pkt_sign;
-    ZXIC_UINT32 cara_cd;
-    ZXIC_UINT32 cara_cf;
-    ZXIC_UINT32 cara_cm;
-    ZXIC_UINT32 cara_eir;
-    ZXIC_UINT32 cara_cir;
-    ZXIC_UINT32 cara_ebs_pbs;
-    ZXIC_UINT32 cara_cbs;
-    ZXIC_UINT32 cara_c_pri1;
-    ZXIC_UINT32 cara_c_pri2;
-    ZXIC_UINT32 cara_c_pri3;
-    ZXIC_UINT32 cara_c_pri4;
-    ZXIC_UINT32 cara_c_pri5;
-    ZXIC_UINT32 cara_c_pri6;
-    ZXIC_UINT32 cara_c_pri7;
-    ZXIC_UINT32 cara_e_g_pri1;
-    ZXIC_UINT32 cara_e_g_pri2;
-    ZXIC_UINT32 cara_e_g_pri3;
-    ZXIC_UINT32 cara_e_g_pri4;
-    ZXIC_UINT32 cara_e_g_pri5;
-    ZXIC_UINT32 cara_e_g_pri6;
-    ZXIC_UINT32 cara_e_g_pri7;
-    ZXIC_UINT32 cara_e_y_pri0;
-    ZXIC_UINT32 cara_e_y_pri1;
-    ZXIC_UINT32 cara_e_y_pri2;
-    ZXIC_UINT32 cara_e_y_pri3;
-    ZXIC_UINT32 cara_e_y_pri4;
-    ZXIC_UINT32 cara_e_y_pri5;
-    ZXIC_UINT32 cara_e_y_pri6;
-    ZXIC_UINT32 cara_e_y_pri7;
-}DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_T;
-
-typedef struct dpp_stat_car0_cara_qovs_ram_ram2_t
-{
-    ZXIC_UINT32 cara_qovs;
-}DPP_STAT_CAR0_CARA_QOVS_RAM_RAM2_T;
-
-typedef struct dpp_stat_car0_look_up_table1_t
-{
-    ZXIC_UINT32 cara_flow_id;
-    ZXIC_UINT32 cara_sp;
-}DPP_STAT_CAR0_LOOK_UP_TABLE1_T;
-
-typedef struct dpp_stat_car0_cara_pkt_des_i_cnt_t
-{
-    ZXIC_UINT32 cara_pkt_des_i_cnt;
-}DPP_STAT_CAR0_CARA_PKT_DES_I_CNT_T;
-
-typedef struct dpp_stat_car0_cara_green_pkt_i_cnt_t
-{
-    ZXIC_UINT32 cara_green_pkt_i_cnt;
-}DPP_STAT_CAR0_CARA_GREEN_PKT_I_CNT_T;
-
-typedef struct dpp_stat_car0_cara_yellow_pkt_i_cnt_t
-{
-    ZXIC_UINT32 cara_yellow_pkt_i_cnt;
-}DPP_STAT_CAR0_CARA_YELLOW_PKT_I_CNT_T;
-
-typedef struct dpp_stat_car0_cara_red_pkt_i_cnt_t
-{
-    ZXIC_UINT32 cara_red_pkt_i_cnt;
-}DPP_STAT_CAR0_CARA_RED_PKT_I_CNT_T;
-
-typedef struct dpp_stat_car0_cara_pkt_des_o_cnt_t
-{
-    ZXIC_UINT32 cara_pkt_des_o_cnt;
-}DPP_STAT_CAR0_CARA_PKT_DES_O_CNT_T;
-
-typedef struct dpp_stat_car0_cara_green_pkt_o_cnt_t
-{
-    ZXIC_UINT32 cara_green_pkt_o_cnt;
-}DPP_STAT_CAR0_CARA_GREEN_PKT_O_CNT_T;
-
-typedef struct dpp_stat_car0_cara_yellow_pkt_o_cnt_t
-{
-    ZXIC_UINT32 cara_yellow_pkt_o_cnt;
-}DPP_STAT_CAR0_CARA_YELLOW_PKT_O_CNT_T;
-
-typedef struct dpp_stat_car0_cara_red_pkt_o_cnt_t
-{
-    ZXIC_UINT32 cara_red_pkt_o_cnt;
-}DPP_STAT_CAR0_CARA_RED_PKT_O_CNT_T;
-
-typedef struct dpp_stat_car0_cara_pkt_des_fc_for_cfg_cnt_t
-{
-    ZXIC_UINT32 cara_pkt_des_fc_for_cfg_cnt;
-}DPP_STAT_CAR0_CARA_PKT_DES_FC_FOR_CFG_CNT_T;
-
-typedef struct dpp_stat_car0_cara_appoint_qnum_or_sp_t
-{
-    ZXIC_UINT32 cara_appoint_qnum_or_not;
-    ZXIC_UINT32 cara_appoint_sp_or_not;
-    ZXIC_UINT32 cara_plcr_stat_sp;
-    ZXIC_UINT32 cara_plcr_stat_qnum;
-}DPP_STAT_CAR0_CARA_APPOINT_QNUM_OR_SP_T;
-
-typedef struct dpp_stat_car0_cara_cfgmt_count_mode_t
-{
-    ZXIC_UINT32 cara_cfgmt_count_overflow_mode;
-    ZXIC_UINT32 cara_cfgmt_count_rd_mode;
-}DPP_STAT_CAR0_CARA_CFGMT_COUNT_MODE_T;
-
-typedef struct dpp_stat_car0_cara_pkt_size_cnt_t
-{
-    ZXIC_UINT32 cara_pkt_size_cnt;
-}DPP_STAT_CAR0_CARA_PKT_SIZE_CNT_T;
-
-typedef struct dpp_stat_car0_cara_plcr_init_dont_t
-{
-    ZXIC_UINT32 cara_plcr_init_done;
-}DPP_STAT_CAR0_CARA_PLCR_INIT_DONT_T;
-
-typedef struct dpp_stat_car0_carb_queue_ram0_159_0_t
-{
-    ZXIC_UINT32 carb_drop;
-    ZXIC_UINT32 carb_plcr_en;
-    ZXIC_UINT32 carb_profile_id;
-    ZXIC_UINT32 carb_tq_h;
-    ZXIC_UINT32 carb_tq_l;
-    ZXIC_UINT32 carb_ted;
-    ZXIC_UINT32 carb_tcd;
-    ZXIC_UINT32 carb_tei;
-    ZXIC_UINT32 carb_tci;
-}DPP_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T;
-
-typedef struct dpp_stat_car0_carb_profile_ram1_255_0_t
-{
-    ZXIC_UINT32 carb_profile_wr;
-    ZXIC_UINT32 carb_random_discard_en_e;
-    ZXIC_UINT32 carb_random_discard_en_c;
-    ZXIC_UINT32 carb_pkt_sign;
-    ZXIC_UINT32 carb_cd;
-    ZXIC_UINT32 carb_cf;
-    ZXIC_UINT32 carb_cm;
-    ZXIC_UINT32 carb_eir;
-    ZXIC_UINT32 carb_cir;
-    ZXIC_UINT32 carb_ebs_pbs;
-    ZXIC_UINT32 carb_cbs;
-    ZXIC_UINT32 carb_c_pri1;
-    ZXIC_UINT32 carb_c_pri2;
-    ZXIC_UINT32 carb_c_pri3;
-    ZXIC_UINT32 carb_c_pri4;
-    ZXIC_UINT32 carb_c_pri5;
-    ZXIC_UINT32 carb_c_pri6;
-    ZXIC_UINT32 carb_c_pri7;
-    ZXIC_UINT32 carb_e_g_pri1;
-    ZXIC_UINT32 carb_e_g_pri2;
-    ZXIC_UINT32 carb_e_g_pri3;
-    ZXIC_UINT32 carb_e_g_pri4;
-    ZXIC_UINT32 carb_e_g_pri5;
-    ZXIC_UINT32 carb_e_g_pri6;
-    ZXIC_UINT32 carb_e_g_pri7;
-    ZXIC_UINT32 carb_e_y_pri0;
-    ZXIC_UINT32 carb_e_y_pri1;
-    ZXIC_UINT32 carb_e_y_pri2;
-    ZXIC_UINT32 carb_e_y_pri3;
-    ZXIC_UINT32 carb_e_y_pri4;
-    ZXIC_UINT32 carb_e_y_pri5;
-    ZXIC_UINT32 carb_e_y_pri6;
-    ZXIC_UINT32 carb_e_y_pri7;
-}DPP_STAT_CAR0_CARB_PROFILE_RAM1_255_0_T;
-
-typedef struct dpp_stat_car0_carb_qovs_ram_ram2_t
-{
-    ZXIC_UINT32 carb_qovs;
-}DPP_STAT_CAR0_CARB_QOVS_RAM_RAM2_T;
-
-typedef struct dpp_stat_car0_look_up_table2_t
-{
-    ZXIC_UINT32 carb_flow_id;
-    ZXIC_UINT32 carb_sp;
-}DPP_STAT_CAR0_LOOK_UP_TABLE2_T;
-
-typedef struct dpp_stat_car0_carb_pkt_des_i_cnt_t
-{
-    ZXIC_UINT32 carb_pkt_des_i_cnt;
-}DPP_STAT_CAR0_CARB_PKT_DES_I_CNT_T;
-
-typedef struct dpp_stat_car0_carb_green_pkt_i_cnt_t
-{
-    ZXIC_UINT32 carb_green_pkt_i_cnt;
-}DPP_STAT_CAR0_CARB_GREEN_PKT_I_CNT_T;
-
-typedef struct dpp_stat_car0_carb_yellow_pkt_i_cnt_t
-{
-    ZXIC_UINT32 carb_yellow_pkt_i_cnt;
-}DPP_STAT_CAR0_CARB_YELLOW_PKT_I_CNT_T;
-
-typedef struct dpp_stat_car0_carb_red_pkt_i_cnt_t
-{
-    ZXIC_UINT32 carb_red_pkt_i_cnt;
-}DPP_STAT_CAR0_CARB_RED_PKT_I_CNT_T;
-
-typedef struct dpp_stat_car0_carb_pkt_des_o_cnt_t
-{
-    ZXIC_UINT32 carb_pkt_des_o_cnt;
-}DPP_STAT_CAR0_CARB_PKT_DES_O_CNT_T;
-
-typedef struct dpp_stat_car0_carb_green_pkt_o_cnt_t
-{
-    ZXIC_UINT32 carb_green_pkt_o_cnt;
-}DPP_STAT_CAR0_CARB_GREEN_PKT_O_CNT_T;
-
-typedef struct dpp_stat_car0_carb_yellow_pkt_o_cnt_t
-{
-    ZXIC_UINT32 carb_yellow_pkt_o_cnt;
-}DPP_STAT_CAR0_CARB_YELLOW_PKT_O_CNT_T;
-
-typedef struct dpp_stat_car0_carb_red_pkt_o_cnt_t
-{
-    ZXIC_UINT32 carb_red_pkt_o_cnt;
-}DPP_STAT_CAR0_CARB_RED_PKT_O_CNT_T;
-
-typedef struct dpp_stat_car0_carb_pkt_des_fc_for_cfg_cnt_t
-{
-    ZXIC_UINT32 carb_pkt_des_fc_for_cfg_cnt;
-}DPP_STAT_CAR0_CARB_PKT_DES_FC_FOR_CFG_CNT_T;
-
-typedef struct dpp_stat_car0_carb_appoint_qnum_or_sp_t
-{
-    ZXIC_UINT32 carb_appoint_qnum_or_not;
-    ZXIC_UINT32 carb_appoint_sp_or_not;
-    ZXIC_UINT32 carb_plcr_stat_sp;
-    ZXIC_UINT32 carb_plcr_stat_qnum;
-}DPP_STAT_CAR0_CARB_APPOINT_QNUM_OR_SP_T;
-
-typedef struct dpp_stat_car0_carb_cfgmt_count_mode_t
-{
-    ZXIC_UINT32 carb_cfgmt_count_overflow_mode;
-    ZXIC_UINT32 carb_cfgmt_count_rd_mode;
-}DPP_STAT_CAR0_CARB_CFGMT_COUNT_MODE_T;
-
-typedef struct dpp_stat_car0_carb_pkt_size_cnt_t
-{
-    ZXIC_UINT32 carb_pkt_size_cnt;
-}DPP_STAT_CAR0_CARB_PKT_SIZE_CNT_T;
-
-typedef struct dpp_stat_car0_carb_plcr_init_dont_t
-{
-    ZXIC_UINT32 carb_plcr_init_done;
-}DPP_STAT_CAR0_CARB_PLCR_INIT_DONT_T;
-
-typedef struct dpp_stat_car0_carc_queue_ram0_159_0_t
-{
-    ZXIC_UINT32 carc_drop;
-    ZXIC_UINT32 carc_plcr_en;
-    ZXIC_UINT32 carc_profile_id;
-    ZXIC_UINT32 carc_tq_h;
-    ZXIC_UINT32 carc_tq_l;
-    ZXIC_UINT32 carc_ted;
-    ZXIC_UINT32 carc_tcd;
-    ZXIC_UINT32 carc_tei;
-    ZXIC_UINT32 carc_tci;
-}DPP_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T;
-
-typedef struct dpp_stat_car0_carc_profile_ram1_255_0_t
-{
-    ZXIC_UINT32 carc_profile_wr;
-    ZXIC_UINT32 carc_random_discard_en_e;
-    ZXIC_UINT32 carc_random_discard_en_c;
-    ZXIC_UINT32 carc_pkt_sign;
-    ZXIC_UINT32 carc_cd;
-    ZXIC_UINT32 carc_cf;
-    ZXIC_UINT32 carc_cm;
-    ZXIC_UINT32 carc_eir;
-    ZXIC_UINT32 carc_cir;
-    ZXIC_UINT32 carc_ebs_pbs;
-    ZXIC_UINT32 carc_cbs;
-    ZXIC_UINT32 carc_c_pri1;
-    ZXIC_UINT32 carc_c_pri2;
-    ZXIC_UINT32 carc_c_pri3;
-    ZXIC_UINT32 carc_c_pri4;
-    ZXIC_UINT32 carc_c_pri5;
-    ZXIC_UINT32 carc_c_pri6;
-    ZXIC_UINT32 carc_c_pri7;
-    ZXIC_UINT32 carc_e_g_pri1;
-    ZXIC_UINT32 carc_e_g_pri2;
-    ZXIC_UINT32 carc_e_g_pri3;
-    ZXIC_UINT32 carc_e_g_pri4;
-    ZXIC_UINT32 carc_e_g_pri5;
-    ZXIC_UINT32 carc_e_g_pri6;
-    ZXIC_UINT32 carc_e_g_pri7;
-    ZXIC_UINT32 carc_e_y_pri0;
-    ZXIC_UINT32 carc_e_y_pri1;
-    ZXIC_UINT32 carc_e_y_pri2;
-    ZXIC_UINT32 carc_e_y_pri3;
-    ZXIC_UINT32 carc_e_y_pri4;
-    ZXIC_UINT32 carc_e_y_pri5;
-    ZXIC_UINT32 carc_e_y_pri6;
-    ZXIC_UINT32 carc_e_y_pri7;
-}DPP_STAT_CAR0_CARC_PROFILE_RAM1_255_0_T;
-
-typedef struct dpp_stat_car0_carc_qovs_ram_ram2_t
-{
-    ZXIC_UINT32 carc_qovs;
-}DPP_STAT_CAR0_CARC_QOVS_RAM_RAM2_T;
-
-typedef struct dpp_stat_car0_carc_pkt_des_i_cnt_t
-{
-    ZXIC_UINT32 carc_pkt_des_i_cnt;
-}DPP_STAT_CAR0_CARC_PKT_DES_I_CNT_T;
-
-typedef struct dpp_stat_car0_carc_green_pkt_i_cnt_t
-{
-    ZXIC_UINT32 carc_green_pkt_i_cnt;
-}DPP_STAT_CAR0_CARC_GREEN_PKT_I_CNT_T;
-
-typedef struct dpp_stat_car0_carc_yellow_pkt_i_cnt_t
-{
-    ZXIC_UINT32 carc_yellow_pkt_i_cnt;
-}DPP_STAT_CAR0_CARC_YELLOW_PKT_I_CNT_T;
-
-typedef struct dpp_stat_car0_carc_red_pkt_i_cnt_t
-{
-    ZXIC_UINT32 carc_red_pkt_i_cnt;
-}DPP_STAT_CAR0_CARC_RED_PKT_I_CNT_T;
-
-typedef struct dpp_stat_car0_carc_pkt_des_o_cnt_t
-{
-    ZXIC_UINT32 carc_pkt_des_o_cnt;
-}DPP_STAT_CAR0_CARC_PKT_DES_O_CNT_T;
-
-typedef struct dpp_stat_car0_carc_green_pkt_o_cnt_t
-{
-    ZXIC_UINT32 carc_green_pkt_o_cnt;
-}DPP_STAT_CAR0_CARC_GREEN_PKT_O_CNT_T;
-
-typedef struct dpp_stat_car0_carc_yellow_pkt_o_cnt_t
-{
-    ZXIC_UINT32 carc_yellow_pkt_o_cnt;
-}DPP_STAT_CAR0_CARC_YELLOW_PKT_O_CNT_T;
-
-typedef struct dpp_stat_car0_carc_red_pkt_o_cnt_t
-{
-    ZXIC_UINT32 carc_red_pkt_o_cnt;
-}DPP_STAT_CAR0_CARC_RED_PKT_O_CNT_T;
-
-typedef struct dpp_stat_car0_carc_pkt_des_fc_for_cfg_cnt_t
-{
-    ZXIC_UINT32 carc_pkt_des_fc_for_cfg_cnt;
-}DPP_STAT_CAR0_CARC_PKT_DES_FC_FOR_CFG_CNT_T;
-
-typedef struct dpp_stat_car0_carc_appoint_qnum_or_sp_t
-{
-    ZXIC_UINT32 carc_appoint_qnum_or_not;
-    ZXIC_UINT32 carc_appoint_sp_or_not;
-    ZXIC_UINT32 carc_plcr_stat_sp;
-    ZXIC_UINT32 carc_plcr_stat_qnum;
-}DPP_STAT_CAR0_CARC_APPOINT_QNUM_OR_SP_T;
-
-typedef struct dpp_stat_car0_carc_cfgmt_count_mode_t
-{
-    ZXIC_UINT32 carc_cfgmt_count_overflow_mode;
-    ZXIC_UINT32 carc_cfgmt_count_rd_mode;
-}DPP_STAT_CAR0_CARC_CFGMT_COUNT_MODE_T;
-
-typedef struct dpp_stat_car0_carc_pkt_size_cnt_t
-{
-    ZXIC_UINT32 carc_pkt_size_cnt;
-}DPP_STAT_CAR0_CARC_PKT_SIZE_CNT_T;
-
-typedef struct dpp_stat_car0_carc_plcr_init_dont_t
-{
-    ZXIC_UINT32 carc_plcr_init_done;
-}DPP_STAT_CAR0_CARC_PLCR_INIT_DONT_T;
-
-typedef struct dpp_stat_car0_carb_random_ram_t
-{
-    ZXIC_UINT32 para8_e;
-    ZXIC_UINT32 para7_e;
-    ZXIC_UINT32 para6_e;
-    ZXIC_UINT32 para5_e;
-    ZXIC_UINT32 para4_h_e;
-    ZXIC_UINT32 para4_l_e;
-    ZXIC_UINT32 para3_e;
-    ZXIC_UINT32 para2_h_e;
-    ZXIC_UINT32 para2_l_e;
-    ZXIC_UINT32 para1_e;
-    ZXIC_UINT32 para0_h_e;
-    ZXIC_UINT32 para0_l_e;
-    ZXIC_UINT32 para8_c;
-    ZXIC_UINT32 para7_c;
-    ZXIC_UINT32 para6_c;
-    ZXIC_UINT32 para5_c;
-    ZXIC_UINT32 para4_h_c;
-    ZXIC_UINT32 para4_l_c;
-    ZXIC_UINT32 para3_c;
-    ZXIC_UINT32 para2_h_c;
-    ZXIC_UINT32 para2_l_c;
-    ZXIC_UINT32 para1_c;
-    ZXIC_UINT32 para0_h_c;
-    ZXIC_UINT32 para0_l_c;
-}DPP_STAT_CAR0_CARB_RANDOM_RAM_T;
-
-typedef struct dpp_stat_car0_carc_random_ram_t
-{
-    ZXIC_UINT32 para8_e;
-    ZXIC_UINT32 para7_e;
-    ZXIC_UINT32 para6_e;
-    ZXIC_UINT32 para5_e;
-    ZXIC_UINT32 para4_h_e;
-    ZXIC_UINT32 para4_l_e;
-    ZXIC_UINT32 para3_e;
-    ZXIC_UINT32 para2_h_e;
-    ZXIC_UINT32 para2_l_e;
-    ZXIC_UINT32 para1_e;
-    ZXIC_UINT32 para0_h_e;
-    ZXIC_UINT32 para0_l_e;
-    ZXIC_UINT32 para8_c;
-    ZXIC_UINT32 para7_c;
-    ZXIC_UINT32 para6_c;
-    ZXIC_UINT32 para5_c;
-    ZXIC_UINT32 para4_h_c;
-    ZXIC_UINT32 para4_l_c;
-    ZXIC_UINT32 para3_c;
-    ZXIC_UINT32 para2_h_c;
-    ZXIC_UINT32 para2_l_c;
-    ZXIC_UINT32 para1_c;
-    ZXIC_UINT32 para0_h_c;
-    ZXIC_UINT32 para0_l_c;
-}DPP_STAT_CAR0_CARC_RANDOM_RAM_T;
-
-typedef struct dpp_stat_car0_cara_begin_flow_id_t
-{
-    ZXIC_UINT32 cara_begin_flow_id;
-}DPP_STAT_CAR0_CARA_BEGIN_FLOW_ID_T;
-
-typedef struct dpp_stat_car0_carb_begin_flow_id_t
-{
-    ZXIC_UINT32 carb_begin_flow_id;
-}DPP_STAT_CAR0_CARB_BEGIN_FLOW_ID_T;
-
-typedef struct dpp_stat_car0_carc_begin_flow_id_t
-{
-    ZXIC_UINT32 carc_begin_flow_id;
-}DPP_STAT_CAR0_CARC_BEGIN_FLOW_ID_T;
-
-typedef struct dpp_stat_car0_prog_full_assert_cfg_w_t
-{
-    ZXIC_UINT32 prog_full_assert_cfg_w;
-}DPP_STAT_CAR0_PROG_FULL_ASSERT_CFG_W_T;
-
-typedef struct dpp_stat_car0_prog_full_negate_cfg_w_t
-{
-    ZXIC_UINT32 prog_full_negate_cfg_w;
-}DPP_STAT_CAR0_PROG_FULL_NEGATE_CFG_W_T;
-
-typedef struct dpp_stat_car0_timeout_limit_t
-{
-    ZXIC_UINT32 timeout_limit;
-}DPP_STAT_CAR0_TIMEOUT_LIMIT_T;
-
-typedef struct dpp_stat_car0_pkt_des_fifo_overflow_t
-{
-    ZXIC_UINT32 pkt_des_fifo_overflow;
-}DPP_STAT_CAR0_PKT_DES_FIFO_OVERFLOW_T;
-
-typedef struct dpp_stat_car0_pkt_des_fifo_underflow_t
-{
-    ZXIC_UINT32 pkt_des_fifo_underflow;
-}DPP_STAT_CAR0_PKT_DES_FIFO_UNDERFLOW_T;
-
-typedef struct dpp_stat_car0_pkt_des_fifo_prog_full_t
-{
-    ZXIC_UINT32 pkt_des_fifo_prog_full;
-}DPP_STAT_CAR0_PKT_DES_FIFO_PROG_FULL_T;
-
-typedef struct dpp_stat_car0_pkt_des_fifo_prog_empty_t
-{
-    ZXIC_UINT32 pkt_des_fifo_prog_empty;
-}DPP_STAT_CAR0_PKT_DES_FIFO_PROG_EMPTY_T;
-
-typedef struct dpp_stat_car0_pkt_des_fifo_full_t
-{
-    ZXIC_UINT32 pkt_des_fifo_full;
-}DPP_STAT_CAR0_PKT_DES_FIFO_FULL_T;
-
-typedef struct dpp_stat_car0_pkt_des_fifo_empty_t
-{
-    ZXIC_UINT32 pkt_des_fifo_empty;
-}DPP_STAT_CAR0_PKT_DES_FIFO_EMPTY_T;
-
-typedef struct dpp_stat_car0_pkt_size_offset_t
-{
-    ZXIC_UINT32 pkt_size_offset;
-}DPP_STAT_CAR0_PKT_SIZE_OFFSET_T;
-
-typedef struct dpp_stat_car0_car_plcr_init_dont_t
-{
-    ZXIC_UINT32 plcr_init_done;
-}DPP_STAT_CAR0_CAR_PLCR_INIT_DONT_T;
-
-typedef struct dpp_stat_car0_max_pkt_size_a_t
-{
-    ZXIC_UINT32 max_pkt_size_a;
-}DPP_STAT_CAR0_MAX_PKT_SIZE_A_T;
-
-typedef struct dpp_stat_car0_max_pkt_size_b_t
-{
-    ZXIC_UINT32 max_pkt_size_b;
-}DPP_STAT_CAR0_MAX_PKT_SIZE_B_T;
-
-typedef struct dpp_stat_car0_max_pkt_size_c_t
-{
-    ZXIC_UINT32 max_pkt_size_c;
-}DPP_STAT_CAR0_MAX_PKT_SIZE_C_T;
-
-typedef struct dpp_stat_car0_car_hierarchy_mode_t
-{
-    ZXIC_UINT32 car_hierarchy_mode;
-}DPP_STAT_CAR0_CAR_HIERARCHY_MODE_T;
-
-typedef struct dpp_stat_car0_prog_empty_assert_cfg_w_t
-{
-    ZXIC_UINT32 prog_empty_assert_cfg_w;
-}DPP_STAT_CAR0_PROG_EMPTY_ASSERT_CFG_W_T;
-
-typedef struct dpp_stat_car0_prog_empty_negate_cfg_w_t
-{
-    ZXIC_UINT32 prog_empty_negate_cfg_w;
-}DPP_STAT_CAR0_PROG_EMPTY_NEGATE_CFG_W_T;
-
-typedef struct dpp_stat_car0_pkt_des_fifo_ovf_int_t
-{
-    ZXIC_UINT32 pkt_des_fifo_ovf_int;
-}DPP_STAT_CAR0_PKT_DES_FIFO_OVF_INT_T;
-
-typedef struct dpp_stat_car0_pkt_des_fifo_data_count_t
-{
-    ZXIC_UINT32 pkt_des_fifo_data_count;
-}DPP_STAT_CAR0_PKT_DES_FIFO_DATA_COUNT_T;
-
-typedef struct dpp_stat_car0_pkt_des_fifo_udf_int_t
-{
-    ZXIC_UINT32 pkt_des_fifo_udf_int;
-}DPP_STAT_CAR0_PKT_DES_FIFO_UDF_INT_T;
-
-typedef struct dpp_stat_car0_cara_queue_ram0_159_0_pkt_t
-{
-    ZXIC_UINT32 cara_drop;
-    ZXIC_UINT32 cara_plcr_en;
-    ZXIC_UINT32 cara_profile_id;
-    ZXIC_UINT32 cara_tq_h;
-    ZXIC_UINT32 cara_tq_l;
-    ZXIC_UINT32 cara_dc_high;
-    ZXIC_UINT32 cara_dc_low;
-    ZXIC_UINT32 cara_tc;
-}DPP_STAT_CAR0_CARA_QUEUE_RAM0_159_0_PKT_T;
-
-typedef struct dpp_stat_car0_cara_profile_ram1_255_0_pkt_t
-{
-    ZXIC_UINT32 cara_profile_wr;
-    ZXIC_UINT32 cara_pkt_sign;
-    ZXIC_UINT32 cara_pkt_cir;
-    ZXIC_UINT32 cara_pkt_cbs;
-    ZXIC_UINT32 cara_pri0;
-    ZXIC_UINT32 cara_pri1;
-    ZXIC_UINT32 cara_pri2;
-    ZXIC_UINT32 cara_pri3;
-    ZXIC_UINT32 cara_pri4;
-    ZXIC_UINT32 cara_pri5;
-    ZXIC_UINT32 cara_pri6;
-    ZXIC_UINT32 cara_pri7;
-}DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKT_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_eram_wdat1_t
-{
-    ZXIC_UINT32 cpu_ind_eram_wdat1;
-}DPP_STAT_STAT_CFG_CPU_IND_ERAM_WDAT1_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_eram_wdat2_t
-{
-    ZXIC_UINT32 cpu_ind_eram_wdat2;
-}DPP_STAT_STAT_CFG_CPU_IND_ERAM_WDAT2_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_eram_wdat3_t
-{
-    ZXIC_UINT32 cpu_ind_eram_wdat3;
-}DPP_STAT_STAT_CFG_CPU_IND_ERAM_WDAT3_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_eram_req_info_t
-{
-    ZXIC_UINT32 rw_mode;
-    ZXIC_UINT32 read_mode;
-    ZXIC_UINT32 tm_cs;
-    ZXIC_UINT32 queue_cs;
-    ZXIC_UINT32 rw_addr;
-}DPP_STAT_STAT_CFG_CPU_IND_ERAM_REQ_INFO_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_eram_rd_done_t
-{
-    ZXIC_UINT32 cpu_ind_eram_rd_done;
-}DPP_STAT_STAT_CFG_CPU_IND_ERAM_RD_DONE_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_eram_rdat0_t
-{
-    ZXIC_UINT32 cpu_ind_eram_rdat0;
-}DPP_STAT_STAT_CFG_CPU_IND_ERAM_RDAT0_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_eram_rdat1_t
-{
-    ZXIC_UINT32 cpu_ind_eram_rdat1;
-}DPP_STAT_STAT_CFG_CPU_IND_ERAM_RDAT1_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_eram_rdat2_t
-{
-    ZXIC_UINT32 cpu_ind_eram_rdat2;
-}DPP_STAT_STAT_CFG_CPU_IND_ERAM_RDAT2_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_eram_rdat3_t
-{
-    ZXIC_UINT32 cpu_ind_eram_rdat3;
-}DPP_STAT_STAT_CFG_CPU_IND_ERAM_RDAT3_T;
-
-typedef struct dpp_stat_stat_cfg_tm_alu_eram_cpu_rdy_t
-{
-    ZXIC_UINT32 tm_alu_eram_cpu_rdy;
-}DPP_STAT_STAT_CFG_TM_ALU_ERAM_CPU_RDY_T;
-
-typedef struct dpp_stat_stat_cfg_oam_stat_cfg_t
-{
-    ZXIC_UINT32 oam_flow_control_cfg;
-    ZXIC_UINT32 oam_lm_flow_control_cfg;
-    ZXIC_UINT32 oam_in_eram_cfg;
-}DPP_STAT_STAT_CFG_OAM_STAT_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_ftm_port_sel_cfg_t
-{
-    ZXIC_UINT32 ftm_port0_sel_cfg;
-    ZXIC_UINT32 ftm_port1_sel_cfg;
-    ZXIC_UINT32 ftm_port2_sel_cfg;
-    ZXIC_UINT32 ftm_port3_sel_cfg;
-}DPP_STAT_STAT_CFG_FTM_PORT_SEL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_oam_eram_base_addr_t
-{
-    ZXIC_UINT32 oam_eram_base_addr;
-}DPP_STAT_STAT_CFG_OAM_ERAM_BASE_ADDR_T;
-
-typedef struct dpp_stat_stat_cfg_oam_lm_eram_base_addr_t
-{
-    ZXIC_UINT32 oam_lm_eram_base_addr;
-}DPP_STAT_STAT_CFG_OAM_LM_ERAM_BASE_ADDR_T;
-
-typedef struct dpp_stat_stat_cfg_oam_ddr_base_addr_t
-{
-    ZXIC_UINT32 oam_ddr_base_addr;
-}DPP_STAT_STAT_CFG_OAM_DDR_BASE_ADDR_T;
-
-typedef struct dpp_stat_stat_cfg_plcr0_schd_pful_cfg_t
-{
-    ZXIC_UINT32 plcr0_schd_pful_assert;
-    ZXIC_UINT32 plcr0_schd_pful_negate;
-}DPP_STAT_STAT_CFG_PLCR0_SCHD_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_oam_lm_ord_pful_cfg_t
-{
-    ZXIC_UINT32 oam_lm_ord_pful_assert;
-    ZXIC_UINT32 oam_lm_ord_pful_negate;
-}DPP_STAT_STAT_CFG_OAM_LM_ORD_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_ddr_schd_pful_cfg_t
-{
-    ZXIC_UINT32 ddr_schd_pful_assert;
-    ZXIC_UINT32 ddr_schd_pful_negate;
-}DPP_STAT_STAT_CFG_DDR_SCHD_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_eram_schd_pful_cfg_t
-{
-    ZXIC_UINT32 eram_schd_pful_assert;
-    ZXIC_UINT32 eram_schd_pful_negate;
-}DPP_STAT_STAT_CFG_ERAM_SCHD_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_eram_schd_pept_cfg_t
-{
-    ZXIC_UINT32 eram_schd_pept_assert;
-    ZXIC_UINT32 eram_schd_pept_negate;
-}DPP_STAT_STAT_CFG_ERAM_SCHD_PEPT_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_eram_schd_oam_pful_cfg_t
-{
-    ZXIC_UINT32 eram_schd_oam_pful_assert;
-    ZXIC_UINT32 eram_schd_oam_pful_negate;
-}DPP_STAT_STAT_CFG_ERAM_SCHD_OAM_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_eram_schd_oam_pept_cfg_t
-{
-    ZXIC_UINT32 eram_schd_oam_pept_assert;
-    ZXIC_UINT32 eram_schd_oam_pept_negate;
-}DPP_STAT_STAT_CFG_ERAM_SCHD_OAM_PEPT_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_eram_schd_oam_lm_pful_cfg_t
-{
-    ZXIC_UINT32 eram_schd_oam_lm_pful_assert;
-    ZXIC_UINT32 eram_schd_oam_lm_pful_negate;
-}DPP_STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_eram_schd_oam_lm_pept_cfg_t
-{
-    ZXIC_UINT32 eram_schd_oam_lm_pept_assert;
-    ZXIC_UINT32 eram_schd_oam_lm_pept_negate;
-}DPP_STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PEPT_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_rschd_pful_cfg_t
-{
-    ZXIC_UINT32 rschd_pful_assert;
-    ZXIC_UINT32 rschd_pful_negate;
-}DPP_STAT_STAT_CFG_RSCHD_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_rschd_pept_cfg_t
-{
-    ZXIC_UINT32 rschd_pept_assert;
-    ZXIC_UINT32 rschd_pept_negate;
-}DPP_STAT_STAT_CFG_RSCHD_PEPT_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_rschd_plcr_pful_cfg_t
-{
-    ZXIC_UINT32 rschd_plcr_pful_assert;
-    ZXIC_UINT32 rschd_plcr_pful_negate;
-}DPP_STAT_STAT_CFG_RSCHD_PLCR_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_rschd_plcr_pept_cfg_t
-{
-    ZXIC_UINT32 rschd_plcr_pept_assert;
-    ZXIC_UINT32 rschd_plcr_pept_negate;
-}DPP_STAT_STAT_CFG_RSCHD_PLCR_PEPT_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_rschd_plcr_info_pful_cfg_t
-{
-    ZXIC_UINT32 rschd_plcr_info_pful_assert;
-    ZXIC_UINT32 rschd_plcr_info_pful_negate;
-}DPP_STAT_STAT_CFG_RSCHD_PLCR_INFO_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_alu_arb_cpu_pful_cfg_t
-{
-    ZXIC_UINT32 alu_arb_cpu_pful_assert;
-    ZXIC_UINT32 alu_arb_cpu_pful_negate;
-}DPP_STAT_STAT_CFG_ALU_ARB_CPU_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_alu_arb_user_pful_cfg_t
-{
-    ZXIC_UINT32 alu_arb_user_pful_assert;
-    ZXIC_UINT32 alu_arb_user_pful_negate;
-}DPP_STAT_STAT_CFG_ALU_ARB_USER_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_alu_arb_stat_pful_cfg_t
-{
-    ZXIC_UINT32 alu_arb_stat_pful_assert;
-    ZXIC_UINT32 alu_arb_stat_pful_negate;
-}DPP_STAT_STAT_CFG_ALU_ARB_STAT_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_cycmov_dat_pful_cfg_t
-{
-    ZXIC_UINT32 cycmov_dat_pful_assert;
-    ZXIC_UINT32 cycmov_dat_pful_negate;
-}DPP_STAT_STAT_CFG_CYCMOV_DAT_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_ddr_opr_pful_cfg_t
-{
-    ZXIC_UINT32 ddr_opr_pful_assert;
-    ZXIC_UINT32 ddr_opr_pful_negate;
-}DPP_STAT_STAT_CFG_DDR_OPR_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_cycle_mov_pful_cfg_t
-{
-    ZXIC_UINT32 cycle_mov_pful_assert;
-    ZXIC_UINT32 cycle_mov_pful_negate;
-}DPP_STAT_STAT_CFG_CYCLE_MOV_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_cntovf_pful_cfg_t
-{
-    ZXIC_UINT32 cntovf_pful_assert;
-    ZXIC_UINT32 cntovf_pful_negate;
-}DPP_STAT_STAT_CFG_CNTOVF_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_eram_schd_plcr_pful_cfg_t
-{
-    ZXIC_UINT32 eram_schd_plcr_pful_assert;
-    ZXIC_UINT32 eram_schd_plcr_pful_negate;
-}DPP_STAT_STAT_CFG_ERAM_SCHD_PLCR_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_eram_schd_plcr_pept_cfg_t
-{
-    ZXIC_UINT32 eram_schd_plcr_pept_assert;
-    ZXIC_UINT32 eram_schd_plcr_pept_negate;
-}DPP_STAT_STAT_CFG_ERAM_SCHD_PLCR_PEPT_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_debug_cnt_mode_t
-{
-    ZXIC_UINT32 cnt_rd_mode;
-    ZXIC_UINT32 cnt_overflow_mode;
-}DPP_STAT_STAT_CFG_DEBUG_CNT_MODE_T;
-
-typedef struct dpp_stat_stat_cfg_tm_mov_period_cfg_t
-{
-    ZXIC_UINT32 etm_mov_period_cfg;
-    ZXIC_UINT32 ftm_mov_period_cfg;
-}DPP_STAT_STAT_CFG_TM_MOV_PERIOD_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_alu_ddr_cpu_req_pful_cfg_t
-{
-    ZXIC_UINT32 alu_ddr_cpu_req_pful_assert;
-    ZXIC_UINT32 alu_ddr_cpu_req_pful_negate;
-}DPP_STAT_STAT_CFG_ALU_DDR_CPU_REQ_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_cycmov_addr_pful_cfg_t
-{
-    ZXIC_UINT32 cycmov_addr_pful_assert;
-    ZXIC_UINT32 cycmov_addr_pful_negate;
-}DPP_STAT_STAT_CFG_CYCMOV_ADDR_PFUL_CFG_T;
-
-typedef struct dpp_stat_stat_cfg_ord_ddr_plcr_fifo_empty_t
-{
-    ZXIC_UINT32 ord_oam_lm_empty;
-    ZXIC_UINT32 ddr_schd_fifo_empty;
-    ZXIC_UINT32 plcr0_schd_fifo_empty;
-}DPP_STAT_STAT_CFG_ORD_DDR_PLCR_FIFO_EMPTY_T;
-
-typedef struct dpp_stat_stat_cfg_tm_stat_fifo_empty_t
-{
-    ZXIC_UINT32 tm_stat_fifo_empty;
-}DPP_STAT_STAT_CFG_TM_STAT_FIFO_EMPTY_T;
-
-typedef struct dpp_stat_stat_cfg_eram_schd_fifo_empty_0_1_t
-{
-    ZXIC_UINT32 eram_schd_fifo_empty1;
-    ZXIC_UINT32 eram_schd_fifo_empty0;
-}DPP_STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_0_1_T;
-
-typedef struct dpp_stat_stat_cfg_eram_schd_fifo_empty_2_3_t
-{
-    ZXIC_UINT32 eram_schd_fifo_empty3;
-    ZXIC_UINT32 eram_schd_fifo_empty2;
-}DPP_STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_2_3_T;
-
-typedef struct dpp_stat_stat_cfg_eram_schd_fifo_empty_4_5_t
-{
-    ZXIC_UINT32 eram_schd_fifo_empty5;
-    ZXIC_UINT32 eram_schd_fifo_empty4;
-}DPP_STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_4_5_T;
-
-typedef struct dpp_stat_stat_cfg_eram_schd_fifo_empty_6_7_t
-{
-    ZXIC_UINT32 eram_schd_fifo_empty7;
-    ZXIC_UINT32 eram_schd_fifo_empty6;
-}DPP_STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_6_7_T;
-
-typedef struct dpp_stat_stat_cfg_eram_schd_fifo_empty_free_8_t
-{
-    ZXIC_UINT32 eram_schd_free_fifo_empty8;
-    ZXIC_UINT32 eram_schd_free_fifo_empty7;
-    ZXIC_UINT32 eram_schd_free_fifo_empty6;
-    ZXIC_UINT32 eram_schd_free_fifo_empty5;
-    ZXIC_UINT32 eram_schd_free_fifo_empty4;
-    ZXIC_UINT32 eram_schd_free_fifo_empty3;
-    ZXIC_UINT32 eram_schd_free_fifo_empty2;
-    ZXIC_UINT32 eram_schd_free_fifo_empty1;
-    ZXIC_UINT32 eram_schd_free_fifo_empty0;
-    ZXIC_UINT32 eram_schd_fifo_empty8;
-}DPP_STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_FREE_8_T;
-
-typedef struct dpp_stat_stat_cfg_rschd_fifo_empty_0_3_t
-{
-    ZXIC_UINT32 rschd_fifo_empty3;
-    ZXIC_UINT32 rschd_fifo_empty2;
-    ZXIC_UINT32 rschd_fifo_empty1;
-    ZXIC_UINT32 rschd_fifo_empty0;
-}DPP_STAT_STAT_CFG_RSCHD_FIFO_EMPTY_0_3_T;
-
-typedef struct dpp_stat_stat_cfg_rschd_fifo_empty_4_7_t
-{
-    ZXIC_UINT32 rschd_fifo_empty7;
-    ZXIC_UINT32 rschd_fifo_empty6;
-    ZXIC_UINT32 rschd_fifo_empty5;
-    ZXIC_UINT32 rschd_fifo_empty4;
-}DPP_STAT_STAT_CFG_RSCHD_FIFO_EMPTY_4_7_T;
-
-typedef struct dpp_stat_stat_cfg_rschd_fifo_empty_8_11_t
-{
-    ZXIC_UINT32 rschd_fifo_empty11;
-    ZXIC_UINT32 rschd_fifo_empty10;
-    ZXIC_UINT32 rschd_fifo_empty9;
-    ZXIC_UINT32 rschd_fifo_empty8;
-}DPP_STAT_STAT_CFG_RSCHD_FIFO_EMPTY_8_11_T;
-
-typedef struct dpp_stat_stat_cfg_rschd_fifo_empty_12_15_t
-{
-    ZXIC_UINT32 rschd_fifo_empty15;
-    ZXIC_UINT32 rschd_fifo_empty14;
-    ZXIC_UINT32 rschd_fifo_empty13;
-    ZXIC_UINT32 rschd_fifo_empty12;
-}DPP_STAT_STAT_CFG_RSCHD_FIFO_EMPTY_12_15_T;
-
-typedef struct dpp_stat_stat_cfg_rschd_fifo_empty_plcr_16_17_t
-{
-    ZXIC_UINT32 rschd_fifo_empty_plcr;
-    ZXIC_UINT32 rschd_fifo_empty17;
-    ZXIC_UINT32 rschd_fifo_empty16;
-}DPP_STAT_STAT_CFG_RSCHD_FIFO_EMPTY_PLCR_16_17_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int_unmask_flag_t
-{
-    ZXIC_UINT32 stat_int5_unmask_flag;
-    ZXIC_UINT32 stat_int4_unmask_flag;
-    ZXIC_UINT32 stat_int3_unmask_flag;
-    ZXIC_UINT32 stat_int2_unmask_flag;
-    ZXIC_UINT32 stat_int1_unmask_flag;
-    ZXIC_UINT32 stat_int0_unmask_flag;
-}DPP_STAT_STAT_CFG_STAT_INT_UNMASK_FLAG_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int0_en_t
-{
-    ZXIC_UINT32 stat_int0_en31;
-    ZXIC_UINT32 stat_int0_en30;
-    ZXIC_UINT32 stat_int0_en29;
-    ZXIC_UINT32 stat_int0_en28;
-    ZXIC_UINT32 stat_int0_en27;
-    ZXIC_UINT32 stat_int0_en26;
-    ZXIC_UINT32 stat_int0_en25;
-    ZXIC_UINT32 stat_int0_en24;
-    ZXIC_UINT32 stat_int0_en23;
-    ZXIC_UINT32 stat_int0_en22;
-    ZXIC_UINT32 stat_int0_en21;
-    ZXIC_UINT32 stat_int0_en20;
-    ZXIC_UINT32 stat_int0_en19;
-    ZXIC_UINT32 stat_int0_en18;
-    ZXIC_UINT32 stat_int0_en17;
-    ZXIC_UINT32 stat_int0_en16;
-    ZXIC_UINT32 stat_int0_en15;
-    ZXIC_UINT32 stat_int0_en14;
-    ZXIC_UINT32 stat_int0_en13;
-    ZXIC_UINT32 stat_int0_en12;
-    ZXIC_UINT32 stat_int0_en11;
-    ZXIC_UINT32 stat_int0_en10;
-    ZXIC_UINT32 stat_int0_en9;
-    ZXIC_UINT32 stat_int0_en8;
-    ZXIC_UINT32 stat_int0_en7;
-    ZXIC_UINT32 stat_int0_en6;
-    ZXIC_UINT32 stat_int0_en5;
-    ZXIC_UINT32 stat_int0_en4;
-    ZXIC_UINT32 stat_int0_en3;
-    ZXIC_UINT32 stat_int0_en2;
-    ZXIC_UINT32 stat_int0_en1;
-    ZXIC_UINT32 stat_int0_en0;
-}DPP_STAT_STAT_CFG_STAT_INT0_EN_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int0_mask_t
-{
-    ZXIC_UINT32 stat_int0_mask31;
-    ZXIC_UINT32 stat_int0_mask30;
-    ZXIC_UINT32 stat_int0_mask29;
-    ZXIC_UINT32 stat_int0_mask28;
-    ZXIC_UINT32 stat_int0_mask27;
-    ZXIC_UINT32 stat_int0_mask26;
-    ZXIC_UINT32 stat_int0_mask25;
-    ZXIC_UINT32 stat_int0_mask24;
-    ZXIC_UINT32 stat_int0_mask23;
-    ZXIC_UINT32 stat_int0_mask22;
-    ZXIC_UINT32 stat_int0_mask21;
-    ZXIC_UINT32 stat_int0_mask20;
-    ZXIC_UINT32 stat_int0_mask19;
-    ZXIC_UINT32 stat_int0_mask18;
-    ZXIC_UINT32 stat_int0_mask17;
-    ZXIC_UINT32 stat_int0_mask16;
-    ZXIC_UINT32 stat_int0_mask15;
-    ZXIC_UINT32 stat_int0_mask14;
-    ZXIC_UINT32 stat_int0_mask13;
-    ZXIC_UINT32 stat_int0_mask12;
-    ZXIC_UINT32 stat_int0_mask11;
-    ZXIC_UINT32 stat_int0_mask10;
-    ZXIC_UINT32 stat_int0_mask9;
-    ZXIC_UINT32 stat_int0_mask8;
-    ZXIC_UINT32 stat_int0_mask7;
-    ZXIC_UINT32 stat_int0_mask6;
-    ZXIC_UINT32 stat_int0_mask5;
-    ZXIC_UINT32 stat_int0_mask4;
-    ZXIC_UINT32 stat_int0_mask3;
-    ZXIC_UINT32 stat_int0_mask2;
-    ZXIC_UINT32 stat_int0_mask1;
-    ZXIC_UINT32 stat_int0_mask0;
-}DPP_STAT_STAT_CFG_STAT_INT0_MASK_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int0_status_t
-{
-    ZXIC_UINT32 stat_int0_status31;
-    ZXIC_UINT32 stat_int0_status30;
-    ZXIC_UINT32 stat_int0_status29;
-    ZXIC_UINT32 stat_int0_status28;
-    ZXIC_UINT32 stat_int0_status27;
-    ZXIC_UINT32 stat_int0_status26;
-    ZXIC_UINT32 stat_int0_status25;
-    ZXIC_UINT32 stat_int0_status24;
-    ZXIC_UINT32 stat_int0_status23;
-    ZXIC_UINT32 stat_int0_status22;
-    ZXIC_UINT32 stat_int0_status21;
-    ZXIC_UINT32 stat_int0_status20;
-    ZXIC_UINT32 stat_int0_status19;
-    ZXIC_UINT32 stat_int0_status18;
-    ZXIC_UINT32 stat_int0_status17;
-    ZXIC_UINT32 stat_int0_status16;
-    ZXIC_UINT32 stat_int0_status15;
-    ZXIC_UINT32 stat_int0_status14;
-    ZXIC_UINT32 stat_int0_status13;
-    ZXIC_UINT32 stat_int0_status12;
-    ZXIC_UINT32 stat_int0_status11;
-    ZXIC_UINT32 stat_int0_status10;
-    ZXIC_UINT32 stat_int0_status9;
-    ZXIC_UINT32 stat_int0_status8;
-    ZXIC_UINT32 stat_int0_status7;
-    ZXIC_UINT32 stat_int0_status6;
-    ZXIC_UINT32 stat_int0_status5;
-    ZXIC_UINT32 stat_int0_status4;
-    ZXIC_UINT32 stat_int0_status3;
-    ZXIC_UINT32 stat_int0_status2;
-    ZXIC_UINT32 stat_int0_status1;
-    ZXIC_UINT32 stat_int0_status0;
-}DPP_STAT_STAT_CFG_STAT_INT0_STATUS_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int1_en_t
-{
-    ZXIC_UINT32 stat_int1_en31;
-    ZXIC_UINT32 stat_int1_en30;
-    ZXIC_UINT32 stat_int1_en29;
-    ZXIC_UINT32 stat_int1_en28;
-    ZXIC_UINT32 stat_int1_en27;
-    ZXIC_UINT32 stat_int1_en26;
-    ZXIC_UINT32 stat_int1_en25;
-    ZXIC_UINT32 stat_int1_en24;
-    ZXIC_UINT32 stat_int1_en23;
-    ZXIC_UINT32 stat_int1_en22;
-    ZXIC_UINT32 stat_int1_en21;
-    ZXIC_UINT32 stat_int1_en20;
-    ZXIC_UINT32 stat_int1_en19;
-    ZXIC_UINT32 stat_int1_en18;
-    ZXIC_UINT32 stat_int1_en17;
-    ZXIC_UINT32 stat_int1_en16;
-    ZXIC_UINT32 stat_int1_en15;
-    ZXIC_UINT32 stat_int1_en14;
-    ZXIC_UINT32 stat_int1_en13;
-    ZXIC_UINT32 stat_int1_en12;
-    ZXIC_UINT32 stat_int1_en11;
-    ZXIC_UINT32 stat_int1_en10;
-    ZXIC_UINT32 stat_int1_en9;
-    ZXIC_UINT32 stat_int1_en8;
-    ZXIC_UINT32 stat_int1_en7;
-    ZXIC_UINT32 stat_int1_en6;
-    ZXIC_UINT32 stat_int1_en5;
-    ZXIC_UINT32 stat_int1_en4;
-    ZXIC_UINT32 stat_int1_en3;
-    ZXIC_UINT32 stat_int1_en2;
-    ZXIC_UINT32 stat_int1_en1;
-    ZXIC_UINT32 stat_int1_en0;
-}DPP_STAT_STAT_CFG_STAT_INT1_EN_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int1_mask_t
-{
-    ZXIC_UINT32 stat_int1_mask31;
-    ZXIC_UINT32 stat_int1_mask30;
-    ZXIC_UINT32 stat_int1_mask29;
-    ZXIC_UINT32 stat_int1_mask28;
-    ZXIC_UINT32 stat_int1_mask27;
-    ZXIC_UINT32 stat_int1_mask26;
-    ZXIC_UINT32 stat_int1_mask25;
-    ZXIC_UINT32 stat_int1_mask24;
-    ZXIC_UINT32 stat_int1_mask23;
-    ZXIC_UINT32 stat_int1_mask22;
-    ZXIC_UINT32 stat_int1_mask21;
-    ZXIC_UINT32 stat_int1_mask20;
-    ZXIC_UINT32 stat_int1_mask19;
-    ZXIC_UINT32 stat_int1_mask18;
-    ZXIC_UINT32 stat_int1_mask17;
-    ZXIC_UINT32 stat_int1_mask16;
-    ZXIC_UINT32 stat_int1_mask15;
-    ZXIC_UINT32 stat_int1_mask14;
-    ZXIC_UINT32 stat_int1_mask13;
-    ZXIC_UINT32 stat_int1_mask12;
-    ZXIC_UINT32 stat_int1_mask11;
-    ZXIC_UINT32 stat_int1_mask10;
-    ZXIC_UINT32 stat_int1_mask9;
-    ZXIC_UINT32 stat_int1_mask8;
-    ZXIC_UINT32 stat_int1_mask7;
-    ZXIC_UINT32 stat_int1_mask6;
-    ZXIC_UINT32 stat_int1_mask5;
-    ZXIC_UINT32 stat_int1_mask4;
-    ZXIC_UINT32 stat_int1_mask3;
-    ZXIC_UINT32 stat_int1_mask2;
-    ZXIC_UINT32 stat_int1_mask1;
-    ZXIC_UINT32 stat_int1_mask0;
-}DPP_STAT_STAT_CFG_STAT_INT1_MASK_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int1_status_t
-{
-    ZXIC_UINT32 stat_int1_status31;
-    ZXIC_UINT32 stat_int1_status30;
-    ZXIC_UINT32 stat_int1_status29;
-    ZXIC_UINT32 stat_int1_status28;
-    ZXIC_UINT32 stat_int1_status27;
-    ZXIC_UINT32 stat_int1_status26;
-    ZXIC_UINT32 stat_int1_status25;
-    ZXIC_UINT32 stat_int1_status24;
-    ZXIC_UINT32 stat_int1_status23;
-    ZXIC_UINT32 stat_int1_status22;
-    ZXIC_UINT32 stat_int1_status21;
-    ZXIC_UINT32 stat_int1_status20;
-    ZXIC_UINT32 stat_int1_status19;
-    ZXIC_UINT32 stat_int1_status18;
-    ZXIC_UINT32 stat_int1_status17;
-    ZXIC_UINT32 stat_int1_status16;
-    ZXIC_UINT32 stat_int1_status15;
-    ZXIC_UINT32 stat_int1_status14;
-    ZXIC_UINT32 stat_int1_status13;
-    ZXIC_UINT32 stat_int1_status12;
-    ZXIC_UINT32 stat_int1_status11;
-    ZXIC_UINT32 stat_int1_status10;
-    ZXIC_UINT32 stat_int1_status9;
-    ZXIC_UINT32 stat_int1_status8;
-    ZXIC_UINT32 stat_int1_status7;
-    ZXIC_UINT32 stat_int1_status6;
-    ZXIC_UINT32 stat_int1_status5;
-    ZXIC_UINT32 stat_int1_status4;
-    ZXIC_UINT32 stat_int1_status3;
-    ZXIC_UINT32 stat_int1_status2;
-    ZXIC_UINT32 stat_int1_status1;
-    ZXIC_UINT32 stat_int1_status0;
-}DPP_STAT_STAT_CFG_STAT_INT1_STATUS_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int2_en_t
-{
-    ZXIC_UINT32 stat_int2_en31;
-    ZXIC_UINT32 stat_int2_en30;
-    ZXIC_UINT32 stat_int2_en29;
-    ZXIC_UINT32 stat_int2_en28;
-    ZXIC_UINT32 stat_int2_en27;
-    ZXIC_UINT32 stat_int2_en26;
-    ZXIC_UINT32 stat_int2_en25;
-    ZXIC_UINT32 stat_int2_en24;
-    ZXIC_UINT32 stat_int2_en23;
-    ZXIC_UINT32 stat_int2_en22;
-    ZXIC_UINT32 stat_int2_en21;
-    ZXIC_UINT32 stat_int2_en20;
-    ZXIC_UINT32 stat_int2_en19;
-    ZXIC_UINT32 stat_int2_en18;
-    ZXIC_UINT32 stat_int2_en17;
-    ZXIC_UINT32 stat_int2_en16;
-    ZXIC_UINT32 stat_int2_en15;
-    ZXIC_UINT32 stat_int2_en14;
-    ZXIC_UINT32 stat_int2_en13;
-    ZXIC_UINT32 stat_int2_en12;
-    ZXIC_UINT32 stat_int2_en11;
-    ZXIC_UINT32 stat_int2_en10;
-    ZXIC_UINT32 stat_int2_en9;
-    ZXIC_UINT32 stat_int2_en8;
-    ZXIC_UINT32 stat_int2_en7;
-    ZXIC_UINT32 stat_int2_en6;
-    ZXIC_UINT32 stat_int2_en5;
-    ZXIC_UINT32 stat_int2_en4;
-    ZXIC_UINT32 stat_int2_en3;
-    ZXIC_UINT32 stat_int2_en2;
-    ZXIC_UINT32 stat_int2_en1;
-    ZXIC_UINT32 stat_int2_en0;
-}DPP_STAT_STAT_CFG_STAT_INT2_EN_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int2_mask_t
-{
-    ZXIC_UINT32 stat_int2_mask31;
-    ZXIC_UINT32 stat_int2_mask30;
-    ZXIC_UINT32 stat_int2_mask29;
-    ZXIC_UINT32 stat_int2_mask28;
-    ZXIC_UINT32 stat_int2_mask27;
-    ZXIC_UINT32 stat_int2_mask26;
-    ZXIC_UINT32 stat_int2_mask25;
-    ZXIC_UINT32 stat_int2_mask24;
-    ZXIC_UINT32 stat_int2_mask23;
-    ZXIC_UINT32 stat_int2_mask22;
-    ZXIC_UINT32 stat_int2_mask21;
-    ZXIC_UINT32 stat_int2_mask20;
-    ZXIC_UINT32 stat_int2_mask19;
-    ZXIC_UINT32 stat_int2_mask18;
-    ZXIC_UINT32 stat_int2_mask17;
-    ZXIC_UINT32 stat_int2_mask16;
-    ZXIC_UINT32 stat_int2_mask15;
-    ZXIC_UINT32 stat_int2_mask14;
-    ZXIC_UINT32 stat_int2_mask13;
-    ZXIC_UINT32 stat_int2_mask12;
-    ZXIC_UINT32 stat_int2_mask11;
-    ZXIC_UINT32 stat_int2_mask10;
-    ZXIC_UINT32 stat_int2_mask9;
-    ZXIC_UINT32 stat_int2_mask8;
-    ZXIC_UINT32 stat_int2_mask7;
-    ZXIC_UINT32 stat_int2_mask6;
-    ZXIC_UINT32 stat_int2_mask5;
-    ZXIC_UINT32 stat_int2_mask4;
-    ZXIC_UINT32 stat_int2_mask3;
-    ZXIC_UINT32 stat_int2_mask2;
-    ZXIC_UINT32 stat_int2_mask1;
-    ZXIC_UINT32 stat_int2_mask0;
-}DPP_STAT_STAT_CFG_STAT_INT2_MASK_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int2_status_t
-{
-    ZXIC_UINT32 stat_int2_status31;
-    ZXIC_UINT32 stat_int2_status30;
-    ZXIC_UINT32 stat_int2_status29;
-    ZXIC_UINT32 stat_int2_status28;
-    ZXIC_UINT32 stat_int2_status27;
-    ZXIC_UINT32 stat_int2_status26;
-    ZXIC_UINT32 stat_int2_status25;
-    ZXIC_UINT32 stat_int2_status24;
-    ZXIC_UINT32 stat_int2_status23;
-    ZXIC_UINT32 stat_int2_status22;
-    ZXIC_UINT32 stat_int2_status21;
-    ZXIC_UINT32 stat_int2_status20;
-    ZXIC_UINT32 stat_int2_status19;
-    ZXIC_UINT32 stat_int2_status18;
-    ZXIC_UINT32 stat_int2_status17;
-    ZXIC_UINT32 stat_int2_status16;
-    ZXIC_UINT32 stat_int2_status15;
-    ZXIC_UINT32 stat_int2_status14;
-    ZXIC_UINT32 stat_int2_status13;
-    ZXIC_UINT32 stat_int2_status12;
-    ZXIC_UINT32 stat_int2_status11;
-    ZXIC_UINT32 stat_int2_status10;
-    ZXIC_UINT32 stat_int2_status9;
-    ZXIC_UINT32 stat_int2_status8;
-    ZXIC_UINT32 stat_int2_status7;
-    ZXIC_UINT32 stat_int2_status6;
-    ZXIC_UINT32 stat_int2_status5;
-    ZXIC_UINT32 stat_int2_status4;
-    ZXIC_UINT32 stat_int2_status3;
-    ZXIC_UINT32 stat_int2_status2;
-    ZXIC_UINT32 stat_int2_status1;
-    ZXIC_UINT32 stat_int2_status0;
-}DPP_STAT_STAT_CFG_STAT_INT2_STATUS_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int3_en_t
-{
-    ZXIC_UINT32 stat_int3_en31;
-    ZXIC_UINT32 stat_int3_en30;
-    ZXIC_UINT32 stat_int3_en29;
-    ZXIC_UINT32 stat_int3_en28;
-    ZXIC_UINT32 stat_int3_en27;
-    ZXIC_UINT32 stat_int3_en26;
-    ZXIC_UINT32 stat_int3_en25;
-    ZXIC_UINT32 stat_int3_en24;
-    ZXIC_UINT32 stat_int3_en23;
-    ZXIC_UINT32 stat_int3_en22;
-    ZXIC_UINT32 stat_int3_en21;
-    ZXIC_UINT32 stat_int3_en20;
-    ZXIC_UINT32 stat_int3_en19;
-    ZXIC_UINT32 stat_int3_en18;
-    ZXIC_UINT32 stat_int3_en17;
-    ZXIC_UINT32 stat_int3_en16;
-    ZXIC_UINT32 stat_int3_en15;
-    ZXIC_UINT32 stat_int3_en14;
-    ZXIC_UINT32 stat_int3_en13;
-    ZXIC_UINT32 stat_int3_en12;
-    ZXIC_UINT32 stat_int3_en11;
-    ZXIC_UINT32 stat_int3_en10;
-    ZXIC_UINT32 stat_int3_en9;
-    ZXIC_UINT32 stat_int3_en8;
-    ZXIC_UINT32 stat_int3_en7;
-    ZXIC_UINT32 stat_int3_en6;
-    ZXIC_UINT32 stat_int3_en5;
-    ZXIC_UINT32 stat_int3_en4;
-    ZXIC_UINT32 stat_int3_en3;
-    ZXIC_UINT32 stat_int3_en2;
-    ZXIC_UINT32 stat_int3_en1;
-    ZXIC_UINT32 stat_int3_en0;
-}DPP_STAT_STAT_CFG_STAT_INT3_EN_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int3_mask_t
-{
-    ZXIC_UINT32 stat_int3_mask31;
-    ZXIC_UINT32 stat_int3_mask30;
-    ZXIC_UINT32 stat_int3_mask29;
-    ZXIC_UINT32 stat_int3_mask28;
-    ZXIC_UINT32 stat_int3_mask27;
-    ZXIC_UINT32 stat_int3_mask26;
-    ZXIC_UINT32 stat_int3_mask25;
-    ZXIC_UINT32 stat_int3_mask24;
-    ZXIC_UINT32 stat_int3_mask23;
-    ZXIC_UINT32 stat_int3_mask22;
-    ZXIC_UINT32 stat_int3_mask21;
-    ZXIC_UINT32 stat_int3_mask20;
-    ZXIC_UINT32 stat_int3_mask19;
-    ZXIC_UINT32 stat_int3_mask18;
-    ZXIC_UINT32 stat_int3_mask17;
-    ZXIC_UINT32 stat_int3_mask16;
-    ZXIC_UINT32 stat_int3_mask15;
-    ZXIC_UINT32 stat_int3_mask14;
-    ZXIC_UINT32 stat_int3_mask13;
-    ZXIC_UINT32 stat_int3_mask12;
-    ZXIC_UINT32 stat_int3_mask11;
-    ZXIC_UINT32 stat_int3_mask10;
-    ZXIC_UINT32 stat_int3_mask9;
-    ZXIC_UINT32 stat_int3_mask8;
-    ZXIC_UINT32 stat_int3_mask7;
-    ZXIC_UINT32 stat_int3_mask6;
-    ZXIC_UINT32 stat_int3_mask5;
-    ZXIC_UINT32 stat_int3_mask4;
-    ZXIC_UINT32 stat_int3_mask3;
-    ZXIC_UINT32 stat_int3_mask2;
-    ZXIC_UINT32 stat_int3_mask1;
-    ZXIC_UINT32 stat_int3_mask0;
-}DPP_STAT_STAT_CFG_STAT_INT3_MASK_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int3_status_t
-{
-    ZXIC_UINT32 stat_int3_status31;
-    ZXIC_UINT32 stat_int3_status30;
-    ZXIC_UINT32 stat_int3_status29;
-    ZXIC_UINT32 stat_int3_status28;
-    ZXIC_UINT32 stat_int3_status27;
-    ZXIC_UINT32 stat_int3_status26;
-    ZXIC_UINT32 stat_int3_status25;
-    ZXIC_UINT32 stat_int3_status24;
-    ZXIC_UINT32 stat_int3_status23;
-    ZXIC_UINT32 stat_int3_status22;
-    ZXIC_UINT32 stat_int3_status21;
-    ZXIC_UINT32 stat_int3_status20;
-    ZXIC_UINT32 stat_int3_status19;
-    ZXIC_UINT32 stat_int3_status18;
-    ZXIC_UINT32 stat_int3_status17;
-    ZXIC_UINT32 stat_int3_status16;
-    ZXIC_UINT32 stat_int3_status15;
-    ZXIC_UINT32 stat_int3_status14;
-    ZXIC_UINT32 stat_int3_status13;
-    ZXIC_UINT32 stat_int3_status12;
-    ZXIC_UINT32 stat_int3_status11;
-    ZXIC_UINT32 stat_int3_status10;
-    ZXIC_UINT32 stat_int3_status9;
-    ZXIC_UINT32 stat_int3_status8;
-    ZXIC_UINT32 stat_int3_status7;
-    ZXIC_UINT32 stat_int3_status6;
-    ZXIC_UINT32 stat_int3_status5;
-    ZXIC_UINT32 stat_int3_status4;
-    ZXIC_UINT32 stat_int3_status3;
-    ZXIC_UINT32 stat_int3_status2;
-    ZXIC_UINT32 stat_int3_status1;
-    ZXIC_UINT32 stat_int3_status0;
-}DPP_STAT_STAT_CFG_STAT_INT3_STATUS_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int4_en_t
-{
-    ZXIC_UINT32 stat_int4_en_18;
-    ZXIC_UINT32 stat_int4_en_17;
-    ZXIC_UINT32 stat_int4_en_16;
-    ZXIC_UINT32 stat_int4_en_15;
-    ZXIC_UINT32 stat_int4_en_14;
-    ZXIC_UINT32 stat_int4_en_13;
-    ZXIC_UINT32 stat_int4_en_12;
-    ZXIC_UINT32 stat_int4_en_11;
-    ZXIC_UINT32 stat_int4_en_10;
-    ZXIC_UINT32 stat_int4_en_9;
-    ZXIC_UINT32 stat_int4_en_8;
-    ZXIC_UINT32 stat_int4_en_7;
-    ZXIC_UINT32 stat_int4_en_6;
-    ZXIC_UINT32 stat_int4_en_5;
-    ZXIC_UINT32 stat_int4_en_4;
-    ZXIC_UINT32 stat_int4_en_3;
-    ZXIC_UINT32 stat_int4_en_2;
-    ZXIC_UINT32 stat_int4_en_1;
-    ZXIC_UINT32 stat_int4_en_0;
-}DPP_STAT_STAT_CFG_STAT_INT4_EN_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int4_mask_t
-{
-    ZXIC_UINT32 stat_int4_mask_18;
-    ZXIC_UINT32 stat_int4_mask_17;
-    ZXIC_UINT32 stat_int4_mask_16;
-    ZXIC_UINT32 stat_int4_mask_15;
-    ZXIC_UINT32 stat_int4_mask_14;
-    ZXIC_UINT32 stat_int4_mask_13;
-    ZXIC_UINT32 stat_int4_mask_12;
-    ZXIC_UINT32 stat_int4_mask_11;
-    ZXIC_UINT32 stat_int4_mask_10;
-    ZXIC_UINT32 stat_int4_mask_9;
-    ZXIC_UINT32 stat_int4_mask_8;
-    ZXIC_UINT32 stat_int4_mask_7;
-    ZXIC_UINT32 stat_int4_mask_6;
-    ZXIC_UINT32 stat_int4_mask_5;
-    ZXIC_UINT32 stat_int4_mask_4;
-    ZXIC_UINT32 stat_int4_mask_3;
-    ZXIC_UINT32 stat_int4_mask_2;
-    ZXIC_UINT32 stat_int4_mask_1;
-    ZXIC_UINT32 stat_int4_mask_0;
-}DPP_STAT_STAT_CFG_STAT_INT4_MASK_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int4_status_t
-{
-    ZXIC_UINT32 stat_int4_mask_18;
-    ZXIC_UINT32 stat_int4_mask_17;
-    ZXIC_UINT32 stat_int4_mask_16;
-    ZXIC_UINT32 stat_int4_mask_15;
-    ZXIC_UINT32 stat_int4_mask_14;
-    ZXIC_UINT32 stat_int4_mask_13;
-    ZXIC_UINT32 stat_int4_mask_12;
-    ZXIC_UINT32 stat_int4_mask_11;
-    ZXIC_UINT32 stat_int4_mask_10;
-    ZXIC_UINT32 stat_int4_mask_9;
-    ZXIC_UINT32 stat_int4_mask_8;
-    ZXIC_UINT32 stat_int4_mask_7;
-    ZXIC_UINT32 stat_int4_mask_6;
-    ZXIC_UINT32 stat_int4_mask_5;
-    ZXIC_UINT32 stat_int4_mask_4;
-    ZXIC_UINT32 stat_int4_mask_3;
-    ZXIC_UINT32 stat_int4_mask_2;
-    ZXIC_UINT32 stat_int4_mask_1;
-    ZXIC_UINT32 stat_int4_mask_0;
-}DPP_STAT_STAT_CFG_STAT_INT4_STATUS_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int5_en_t
-{
-    ZXIC_UINT32 stat_int5_en_18;
-    ZXIC_UINT32 stat_int5_en_17;
-    ZXIC_UINT32 stat_int5_en_16;
-    ZXIC_UINT32 stat_int5_en_15;
-    ZXIC_UINT32 stat_int5_en_14;
-    ZXIC_UINT32 stat_int5_en_13;
-    ZXIC_UINT32 stat_int5_en_12;
-    ZXIC_UINT32 stat_int5_en_11;
-    ZXIC_UINT32 stat_int5_en_10;
-    ZXIC_UINT32 stat_int5_en_9;
-    ZXIC_UINT32 stat_int5_en_8;
-    ZXIC_UINT32 stat_int5_en_7;
-    ZXIC_UINT32 stat_int5_en_6;
-    ZXIC_UINT32 stat_int5_en_5;
-    ZXIC_UINT32 stat_int5_en_4;
-    ZXIC_UINT32 stat_int5_en_3;
-    ZXIC_UINT32 stat_int5_en_2;
-    ZXIC_UINT32 stat_int5_en_1;
-    ZXIC_UINT32 stat_int5_en_0;
-}DPP_STAT_STAT_CFG_STAT_INT5_EN_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int5_mask_t
-{
-    ZXIC_UINT32 stat_int5_mask_18;
-    ZXIC_UINT32 stat_int5_mask_17;
-    ZXIC_UINT32 stat_int5_mask_16;
-    ZXIC_UINT32 stat_int5_mask_15;
-    ZXIC_UINT32 stat_int5_mask_14;
-    ZXIC_UINT32 stat_int5_mask_13;
-    ZXIC_UINT32 stat_int5_mask_12;
-    ZXIC_UINT32 stat_int5_mask_11;
-    ZXIC_UINT32 stat_int5_mask_10;
-    ZXIC_UINT32 stat_int5_mask_9;
-    ZXIC_UINT32 stat_int5_mask_8;
-    ZXIC_UINT32 stat_int5_mask_7;
-    ZXIC_UINT32 stat_int5_mask_6;
-    ZXIC_UINT32 stat_int5_mask_5;
-    ZXIC_UINT32 stat_int5_mask_4;
-    ZXIC_UINT32 stat_int5_mask_3;
-    ZXIC_UINT32 stat_int5_mask_2;
-    ZXIC_UINT32 stat_int5_mask_1;
-    ZXIC_UINT32 stat_int5_mask_0;
-}DPP_STAT_STAT_CFG_STAT_INT5_MASK_T;
-
-typedef struct dpp_stat_stat_cfg_stat_int5_status_t
-{
-    ZXIC_UINT32 stat_int5_mask_18;
-    ZXIC_UINT32 stat_int5_mask_17;
-    ZXIC_UINT32 stat_int5_mask_16;
-    ZXIC_UINT32 stat_int5_mask_15;
-    ZXIC_UINT32 stat_int5_mask_14;
-    ZXIC_UINT32 stat_int5_mask_13;
-    ZXIC_UINT32 stat_int5_mask_12;
-    ZXIC_UINT32 stat_int5_mask_11;
-    ZXIC_UINT32 stat_int5_mask_10;
-    ZXIC_UINT32 stat_int5_mask_9;
-    ZXIC_UINT32 stat_int5_mask_8;
-    ZXIC_UINT32 stat_int5_mask_7;
-    ZXIC_UINT32 stat_int5_mask_6;
-    ZXIC_UINT32 stat_int5_mask_5;
-    ZXIC_UINT32 stat_int5_mask_4;
-    ZXIC_UINT32 stat_int5_mask_3;
-    ZXIC_UINT32 stat_int5_mask_2;
-    ZXIC_UINT32 stat_int5_mask_1;
-    ZXIC_UINT32 stat_int5_mask_0;
-}DPP_STAT_STAT_CFG_STAT_INT5_STATUS_T;
-
-typedef struct dpp_stat_stat_cfg_rschd_ecc_bypass_t
-{
-    ZXIC_UINT32 rschd_ecc_bypass_18;
-    ZXIC_UINT32 rschd_ecc_bypass_17;
-    ZXIC_UINT32 rschd_ecc_bypass_16;
-    ZXIC_UINT32 rschd_ecc_bypass_15;
-    ZXIC_UINT32 rschd_ecc_bypass_14;
-    ZXIC_UINT32 rschd_ecc_bypass_13;
-    ZXIC_UINT32 rschd_ecc_bypass_12;
-    ZXIC_UINT32 rschd_ecc_bypass_11;
-    ZXIC_UINT32 rschd_ecc_bypass_10;
-    ZXIC_UINT32 rschd_ecc_bypass_9;
-    ZXIC_UINT32 rschd_ecc_bypass_8;
-    ZXIC_UINT32 rschd_ecc_bypass_7;
-    ZXIC_UINT32 rschd_ecc_bypass_6;
-    ZXIC_UINT32 rschd_ecc_bypass_5;
-    ZXIC_UINT32 rschd_ecc_bypass_4;
-    ZXIC_UINT32 rschd_ecc_bypass_3;
-    ZXIC_UINT32 rschd_ecc_bypass_2;
-    ZXIC_UINT32 rschd_ecc_bypass_1;
-    ZXIC_UINT32 rschd_ecc_bypass_0;
-}DPP_STAT_STAT_CFG_RSCHD_ECC_BYPASS_T;
-
-typedef struct dpp_stat_stat_cfg_rschd_ecc_single_err_t
-{
-    ZXIC_UINT32 rschd_ecc_single_err_18;
-    ZXIC_UINT32 rschd_ecc_single_err_17;
-    ZXIC_UINT32 rschd_ecc_single_err_16;
-    ZXIC_UINT32 rschd_ecc_single_err_15;
-    ZXIC_UINT32 rschd_ecc_single_err_14;
-    ZXIC_UINT32 rschd_ecc_single_err_13;
-    ZXIC_UINT32 rschd_ecc_single_err_12;
-    ZXIC_UINT32 rschd_ecc_single_err_11;
-    ZXIC_UINT32 rschd_ecc_single_err_10;
-    ZXIC_UINT32 rschd_ecc_single_err_9;
-    ZXIC_UINT32 rschd_ecc_single_err_8;
-    ZXIC_UINT32 rschd_ecc_single_err_7;
-    ZXIC_UINT32 rschd_ecc_single_err_6;
-    ZXIC_UINT32 rschd_ecc_single_err_5;
-    ZXIC_UINT32 rschd_ecc_single_err_4;
-    ZXIC_UINT32 rschd_ecc_single_err_3;
-    ZXIC_UINT32 rschd_ecc_single_err_2;
-    ZXIC_UINT32 rschd_ecc_single_err_1;
-    ZXIC_UINT32 rschd_ecc_single_err_0;
-}DPP_STAT_STAT_CFG_RSCHD_ECC_SINGLE_ERR_T;
-
-typedef struct dpp_stat_stat_cfg_rschd_ecc_double_err_t
-{
-    ZXIC_UINT32 rschd_ecc_double_err_18;
-    ZXIC_UINT32 rschd_ecc_double_err_17;
-    ZXIC_UINT32 rschd_ecc_double_err_16;
-    ZXIC_UINT32 rschd_ecc_double_err_15;
-    ZXIC_UINT32 rschd_ecc_double_err_14;
-    ZXIC_UINT32 rschd_ecc_double_err_13;
-    ZXIC_UINT32 rschd_ecc_double_err_12;
-    ZXIC_UINT32 rschd_ecc_double_err_11;
-    ZXIC_UINT32 rschd_ecc_double_err_10;
-    ZXIC_UINT32 rschd_ecc_double_err_9;
-    ZXIC_UINT32 rschd_ecc_double_err_8;
-    ZXIC_UINT32 rschd_ecc_double_err_7;
-    ZXIC_UINT32 rschd_ecc_double_err_6;
-    ZXIC_UINT32 rschd_ecc_double_err_5;
-    ZXIC_UINT32 rschd_ecc_double_err_4;
-    ZXIC_UINT32 rschd_ecc_double_err_3;
-    ZXIC_UINT32 rschd_ecc_double_err_2;
-    ZXIC_UINT32 rschd_ecc_double_err_1;
-    ZXIC_UINT32 rschd_ecc_double_err_0;
-}DPP_STAT_STAT_CFG_RSCHD_ECC_DOUBLE_ERR_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat0_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_wdat0;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT0_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat1_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_wdat1;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT1_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat2_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_wdat2;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT2_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat3_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_wdat3;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT3_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat4_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_wdat4;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT4_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat5_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_wdat5;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT5_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat6_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_wdat6;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT6_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat7_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_wdat7;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT7_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat8_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_wdat8;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT8_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat9_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_wdat9;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT9_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat10_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_wdat10;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT10_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat11_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_wdat11;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT11_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat12_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_wdat12;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT12_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat13_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_wdat13;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT13_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat14_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_wdat14;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT14_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat15_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_wdat15;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT15_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_req_info_t
-{
-    ZXIC_UINT32 rw_mode;
-    ZXIC_UINT32 read_mode;
-    ZXIC_UINT32 tm_cs;
-    ZXIC_UINT32 rw_addr;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_REQ_INFO_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rd_done_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rd_done;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RD_DONE_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat0_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rdat0;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT0_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat1_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rdat1;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT1_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat2_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rdat2;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT2_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat3_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rdat3;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT3_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat4_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rdat4;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT4_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat5_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rdat5;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT5_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat6_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rdat6;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT6_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat7_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rdat7;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT7_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat8_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rdat8;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT8_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat9_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rdat9;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT9_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat10_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rdat10;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT10_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat11_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rdat11;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT11_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat12_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rdat12;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT12_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat13_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rdat13;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT13_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat14_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rdat14;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT14_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat15_t
-{
-    ZXIC_UINT32 cpu_ind_ddr_rdat15;
-}DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT15_T;
-
-typedef struct dpp_stat_stat_cfg_tm_alu_ddr_cpu_rdy_t
-{
-    ZXIC_UINT32 tm_alu_ddr_cpu_rdy;
-}DPP_STAT_STAT_CFG_TM_ALU_DDR_CPU_RDY_T;
-
-typedef struct dpp_stat_stat_cfg_ept_flag_t
-{
-    ZXIC_UINT32 ept_flag;
-}DPP_STAT_STAT_CFG_EPT_FLAG_T;
-
-typedef struct dpp_stat_stat_cfg_ppu_soft_rst_t
-{
-    ZXIC_UINT32 ppu_soft_rst;
-}DPP_STAT_STAT_CFG_PPU_SOFT_RST_T;
-
-typedef struct dpp_stat_stat_cfg_stat_smmu0_fc15_0_cnt_t
-{
-    ZXIC_UINT32 stat_smmu0_fc15_0_cnt;
-}DPP_STAT_STAT_CFG_STAT_SMMU0_FC15_0_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_smmu0_stat_fc15_0_cnt_t
-{
-    ZXIC_UINT32 smmu0_stat_fc15_0_cnt;
-}DPP_STAT_STAT_CFG_SMMU0_STAT_FC15_0_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_smmu0_stat_rsp15_0_cnt_t
-{
-    ZXIC_UINT32 smmu0_stat_rsp15_0_cnt;
-}DPP_STAT_STAT_CFG_SMMU0_STAT_RSP15_0_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_stat_smmu0_req15_0_cnt_t
-{
-    ZXIC_UINT32 stat_smmu0_req15_0_cnt;
-}DPP_STAT_STAT_CFG_STAT_SMMU0_REQ15_0_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_ppu_stat_mec5_0_rsp_fc_cnt_t
-{
-    ZXIC_UINT32 ppu_stat_mec5_0_rsp_fc_cnt;
-}DPP_STAT_STAT_CFG_PPU_STAT_MEC5_0_RSP_FC_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_stat_ppu_mec5_0_key_fc_cnt_t
-{
-    ZXIC_UINT32 stat_ppu_mec5_0_key_fc_cnt;
-}DPP_STAT_STAT_CFG_STAT_PPU_MEC5_0_KEY_FC_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_stat_ppu_mec5_0_rsp_cnt_t
-{
-    ZXIC_UINT32 stat_ppu_mec5_0_rsp_cnt;
-}DPP_STAT_STAT_CFG_STAT_PPU_MEC5_0_RSP_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_ppu_stat_mec5_0_key_cnt_t
-{
-    ZXIC_UINT32 ppu_stat_mec5_0_key_cnt;
-}DPP_STAT_STAT_CFG_PPU_STAT_MEC5_0_KEY_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_ppu5_0_no_exist_opcd_ex_cnt_t
-{
-    ZXIC_UINT32 ppu5_0_no_exist_opcd_ex_cnt;
-}DPP_STAT_STAT_CFG_PPU5_0_NO_EXIST_OPCD_EX_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_se_etm_stat_wr_fc_cnt_t
-{
-    ZXIC_UINT32 se_etm_stat_wr_fc_cnt;
-}DPP_STAT_STAT_CFG_SE_ETM_STAT_WR_FC_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_se_etm_stat_rd_fc_cnt_t
-{
-    ZXIC_UINT32 se_etm_stat_rd_fc_cnt;
-}DPP_STAT_STAT_CFG_SE_ETM_STAT_RD_FC_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_stat_etm_deq_fc_cnt_t
-{
-    ZXIC_UINT32 stat_etm_deq_fc_cnt;
-}DPP_STAT_STAT_CFG_STAT_ETM_DEQ_FC_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_stat_etm_enq_fc_cnt_t
-{
-    ZXIC_UINT32 stat_etm_enq_fc_cnt;
-}DPP_STAT_STAT_CFG_STAT_ETM_ENQ_FC_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_stat_oam_lm_fc_cnt_t
-{
-    ZXIC_UINT32 stat_oam_lm_fc_cnt;
-}DPP_STAT_STAT_CFG_STAT_OAM_LM_FC_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_oam_stat_lm_fc_cnt_t
-{
-    ZXIC_UINT32 oam_stat_lm_fc_cnt;
-}DPP_STAT_STAT_CFG_OAM_STAT_LM_FC_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_stat_oam_fc_cnt_t
-{
-    ZXIC_UINT32 stat_oam_fc_cnt;
-}DPP_STAT_STAT_CFG_STAT_OAM_FC_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_cmmu_stat_fc_cnt_t
-{
-    ZXIC_UINT32 cmmu_stat_fc_cnt;
-}DPP_STAT_STAT_CFG_CMMU_STAT_FC_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_stat_cmmu_req_cnt_t
-{
-    ZXIC_UINT32 stat_cmmu_req_cnt;
-}DPP_STAT_STAT_CFG_STAT_CMMU_REQ_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_smmu0_plcr_rsp0_cnt_t
-{
-    ZXIC_UINT32 smmu0_plcr_rsp0_cnt;
-}DPP_STAT_STAT_CFG_SMMU0_PLCR_RSP0_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_plcr_smmu0_req0_cnt_t
-{
-    ZXIC_UINT32 plcr_smmu0_req0_cnt;
-}DPP_STAT_STAT_CFG_PLCR_SMMU0_REQ0_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_stat_oam_lm_rsp_cnt_t
-{
-    ZXIC_UINT32 stat_oam_lm_rsp_cnt;
-}DPP_STAT_STAT_CFG_STAT_OAM_LM_RSP_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_oam_stat_lm_req_cnt_t
-{
-    ZXIC_UINT32 oam_stat_lm_req_cnt;
-}DPP_STAT_STAT_CFG_OAM_STAT_LM_REQ_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_oam_stat_req_cnt_t
-{
-    ZXIC_UINT32 oam_stat_req_cnt;
-}DPP_STAT_STAT_CFG_OAM_STAT_REQ_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_se_etm_stat_rsp_cnt_t
-{
-    ZXIC_UINT32 se_etm_stat_rsp_cnt;
-}DPP_STAT_STAT_CFG_SE_ETM_STAT_RSP_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_etm_stat_se_wr_req_cnt_t
-{
-    ZXIC_UINT32 etm_stat_se_wr_req_cnt;
-}DPP_STAT_STAT_CFG_ETM_STAT_SE_WR_REQ_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_etm_stat_se_rd_req_cnt_t
-{
-    ZXIC_UINT32 etm_stat_se_rd_req_cnt;
-}DPP_STAT_STAT_CFG_ETM_STAT_SE_RD_REQ_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_etm_stat_smmu0_req_cnt0_t
-{
-    ZXIC_UINT32 etm_stat_smmu0_req_cnt0;
-}DPP_STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT0_T;
-
-typedef struct dpp_stat_stat_cfg_etm_stat_smmu0_req_cnt1_t
-{
-    ZXIC_UINT32 etm_stat_smmu0_req_cnt1;
-}DPP_STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT1_T;
-
-typedef struct dpp_stat_stat_cfg_tm_stat_eram_cpu_rsp_cnt_t
-{
-    ZXIC_UINT32 tm_stat_eram_cpu_rsp_cnt;
-}DPP_STAT_STAT_CFG_TM_STAT_ERAM_CPU_RSP_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_rd_eram_req_cnt_t
-{
-    ZXIC_UINT32 cpu_rd_eram_req_cnt;
-}DPP_STAT_STAT_CFG_CPU_RD_ERAM_REQ_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_wr_eram_req_cnt_t
-{
-    ZXIC_UINT32 cpu_wr_eram_req_cnt;
-}DPP_STAT_STAT_CFG_CPU_WR_ERAM_REQ_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_tm_stat_ddr_cpu_rsp_cnt_t
-{
-    ZXIC_UINT32 tm_stat_ddr_cpu_rsp_cnt;
-}DPP_STAT_STAT_CFG_TM_STAT_DDR_CPU_RSP_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_rd_ddr_req_cnt_t
-{
-    ZXIC_UINT32 cpu_rd_ddr_req_cnt;
-}DPP_STAT_STAT_CFG_CPU_RD_DDR_REQ_CNT_T;
-
-typedef struct dpp_stat_stat_cfg_cpu_wr_ddr_req_cnt_t
-{
-    ZXIC_UINT32 cpu_wr_ddr_req_cnt;
-}DPP_STAT_STAT_CFG_CPU_WR_DDR_REQ_CNT_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat1_t
-{
-    ZXIC_UINT32 wdat1;
-}DPP_STAT_ETCAM_CPU_IND_WDAT1_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat2_t
-{
-    ZXIC_UINT32 wdat2;
-}DPP_STAT_ETCAM_CPU_IND_WDAT2_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat3_t
-{
-    ZXIC_UINT32 wdat3;
-}DPP_STAT_ETCAM_CPU_IND_WDAT3_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat4_t
-{
-    ZXIC_UINT32 wdat4;
-}DPP_STAT_ETCAM_CPU_IND_WDAT4_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat5_t
-{
-    ZXIC_UINT32 wdat5;
-}DPP_STAT_ETCAM_CPU_IND_WDAT5_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat6_t
-{
-    ZXIC_UINT32 wdat6;
-}DPP_STAT_ETCAM_CPU_IND_WDAT6_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat7_t
-{
-    ZXIC_UINT32 wdat7;
-}DPP_STAT_ETCAM_CPU_IND_WDAT7_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat8_t
-{
-    ZXIC_UINT32 wdat8;
-}DPP_STAT_ETCAM_CPU_IND_WDAT8_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat9_t
-{
-    ZXIC_UINT32 wdat9;
-}DPP_STAT_ETCAM_CPU_IND_WDAT9_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat10_t
-{
-    ZXIC_UINT32 wdat10;
-}DPP_STAT_ETCAM_CPU_IND_WDAT10_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat11_t
-{
-    ZXIC_UINT32 wdat11;
-}DPP_STAT_ETCAM_CPU_IND_WDAT11_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat12_t
-{
-    ZXIC_UINT32 wdat12;
-}DPP_STAT_ETCAM_CPU_IND_WDAT12_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat13_t
-{
-    ZXIC_UINT32 wdat13;
-}DPP_STAT_ETCAM_CPU_IND_WDAT13_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat14_t
-{
-    ZXIC_UINT32 wdat14;
-}DPP_STAT_ETCAM_CPU_IND_WDAT14_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat15_t
-{
-    ZXIC_UINT32 wdat15;
-}DPP_STAT_ETCAM_CPU_IND_WDAT15_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat16_t
-{
-    ZXIC_UINT32 wdat16;
-}DPP_STAT_ETCAM_CPU_IND_WDAT16_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat17_t
-{
-    ZXIC_UINT32 wdat17;
-}DPP_STAT_ETCAM_CPU_IND_WDAT17_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat18_t
-{
-    ZXIC_UINT32 wdat18;
-}DPP_STAT_ETCAM_CPU_IND_WDAT18_T;
-
-typedef struct dpp_stat_etcam_cpu_ind_wdat19_t
-{
-    ZXIC_UINT32 wdat19;
-}DPP_STAT_ETCAM_CPU_IND_WDAT19_T;
-
-typedef struct dpp_stat_etcam_t_strwc_cfg_t
-{
-    ZXIC_UINT32 t_strwc_cfg;
-}DPP_STAT_ETCAM_T_STRWC_CFG_T;
-
-typedef struct dpp_stat_etcam_etcam_int_unmask_flag_t
-{
-    ZXIC_UINT32 etcam_int_unmask_flag;
-}DPP_STAT_ETCAM_ETCAM_INT_UNMASK_FLAG_T;
-
-typedef struct dpp_stat_etcam_etcam_int_en0_t
-{
-    ZXIC_UINT32 etcam_int_en17;
-    ZXIC_UINT32 etcam_int_en16;
-    ZXIC_UINT32 etcam_int_en15;
-    ZXIC_UINT32 etcam_int_en14;
-    ZXIC_UINT32 etcam_int_en13;
-    ZXIC_UINT32 etcam_int_en12;
-    ZXIC_UINT32 etcam_int_en11;
-    ZXIC_UINT32 etcam_int_en10;
-    ZXIC_UINT32 etcam_int_en9;
-    ZXIC_UINT32 etcam_int_en8;
-    ZXIC_UINT32 etcam_int_en7;
-    ZXIC_UINT32 etcam_int_en6;
-    ZXIC_UINT32 etcam_int_en5;
-    ZXIC_UINT32 etcam_int_en4;
-    ZXIC_UINT32 etcam_int_en3;
-    ZXIC_UINT32 etcam_int_en2;
-    ZXIC_UINT32 etcam_int_en1;
-    ZXIC_UINT32 etcam_int_en0;
-}DPP_STAT_ETCAM_ETCAM_INT_EN0_T;
-
-typedef struct dpp_stat_etcam_etcam_int_mask0_t
-{
-    ZXIC_UINT32 etcam_int_mask17;
-    ZXIC_UINT32 etcam_int_mask16;
-    ZXIC_UINT32 etcam_int_mask15;
-    ZXIC_UINT32 etcam_int_mask14;
-    ZXIC_UINT32 etcam_int_mask13;
-    ZXIC_UINT32 etcam_int_mask12;
-    ZXIC_UINT32 etcam_int_mask11;
-    ZXIC_UINT32 etcam_int_mask10;
-    ZXIC_UINT32 etcam_int_mask9;
-    ZXIC_UINT32 etcam_int_mask8;
-    ZXIC_UINT32 etcam_int_mask7;
-    ZXIC_UINT32 etcam_int_mask6;
-    ZXIC_UINT32 etcam_int_mask5;
-    ZXIC_UINT32 etcam_int_mask4;
-    ZXIC_UINT32 etcam_int_mask3;
-    ZXIC_UINT32 etcam_int_mask2;
-    ZXIC_UINT32 etcam_int_mask1;
-    ZXIC_UINT32 etcam_int_mask0;
-}DPP_STAT_ETCAM_ETCAM_INT_MASK0_T;
-
-typedef struct dpp_stat_etcam_etcam_int_status_t
-{
-    ZXIC_UINT32 etcam_int_status17;
-    ZXIC_UINT32 etcam_int_status16;
-    ZXIC_UINT32 etcam_int_status15;
-    ZXIC_UINT32 etcam_int_status14;
-    ZXIC_UINT32 etcam_int_status13;
-    ZXIC_UINT32 etcam_int_status12;
-    ZXIC_UINT32 etcam_int_status11;
-    ZXIC_UINT32 etcam_int_status10;
-    ZXIC_UINT32 etcam_int_status9;
-    ZXIC_UINT32 etcam_int_status8;
-    ZXIC_UINT32 etcam_int_status7;
-    ZXIC_UINT32 etcam_int_status6;
-    ZXIC_UINT32 etcam_int_status5;
-    ZXIC_UINT32 etcam_int_status4;
-    ZXIC_UINT32 etcam_int_status3;
-    ZXIC_UINT32 etcam_int_status2;
-    ZXIC_UINT32 etcam_int_status1;
-    ZXIC_UINT32 etcam_int_status0;
-}DPP_STAT_ETCAM_ETCAM_INT_STATUS_T;
-
-typedef struct dpp_stat_etcam_int_tb_ini_ok_t
-{
-    ZXIC_UINT32 int_tb_ini_ok;
-}DPP_STAT_ETCAM_INT_TB_INI_OK_T;
-
-typedef struct dpp_stat_etcam_etcam_clk_en_t
-{
-    ZXIC_UINT32 etcam_clk_en;
-}DPP_STAT_ETCAM_ETCAM_CLK_EN_T;
-
-typedef struct dpp_stat_etcam_as_etcam_req0_cnt_t
-{
-    ZXIC_UINT32 as_etcam_req0_cnt;
-}DPP_STAT_ETCAM_AS_ETCAM_REQ0_CNT_T;
-
-typedef struct dpp_stat_etcam_as_etcam_req1_cnt_t
-{
-    ZXIC_UINT32 as_etcam_req1_cnt;
-}DPP_STAT_ETCAM_AS_ETCAM_REQ1_CNT_T;
-
-typedef struct dpp_stat_etcam_etcam_as_index0_cnt_t
-{
-    ZXIC_UINT32 etcam_as_index0_cnt;
-}DPP_STAT_ETCAM_ETCAM_AS_INDEX0_CNT_T;
-
-typedef struct dpp_stat_etcam_etcam_as_index1_cnt_t
-{
-    ZXIC_UINT32 etcam_as_index1_cnt;
-}DPP_STAT_ETCAM_ETCAM_AS_INDEX1_CNT_T;
-
-typedef struct dpp_stat_etcam_etcam_not_hit0_cnt_t
-{
-    ZXIC_UINT32 etcam_not_hit0_cnt;
-}DPP_STAT_ETCAM_ETCAM_NOT_HIT0_CNT_T;
-
-typedef struct dpp_stat_etcam_etcam_not_hit1_cnt_t
-{
-    ZXIC_UINT32 etcam_not_hit1_cnt;
-}DPP_STAT_ETCAM_ETCAM_NOT_HIT1_CNT_T;
-
-typedef struct dpp_stat_etcam_table_id_not_match_cnt_t
-{
-    ZXIC_UINT32 table_id_not_match_cnt;
-}DPP_STAT_ETCAM_TABLE_ID_NOT_MATCH_CNT_T;
-
-typedef struct dpp_stat_etcam_table_id_clash01_cnt_t
-{
-    ZXIC_UINT32 table_id_clash01_cnt;
-}DPP_STAT_ETCAM_TABLE_ID_CLASH01_CNT_T;
-
-typedef struct dpp_stat_etcam_etcam_cpu_fl_t
-{
-    ZXIC_UINT32 etcam_cpu_fl;
-}DPP_STAT_ETCAM_ETCAM_CPU_FL_T;
-
-typedef struct dpp_stat_etcam_etcam_arb_empty_t
-{
-    ZXIC_UINT32 etcam_arb_empty;
-}DPP_STAT_ETCAM_ETCAM_ARB_EMPTY_T;
+typedef struct dpp_stat_stat_cfg_cpu_ind_eram_wdat0_t {
+	ZXIC_UINT32 cpu_ind_eram_wdat0;
+} DPP_STAT_STAT_CFG_CPU_IND_ERAM_WDAT0_T;
+
+typedef struct dpp_stat_stat_cfg_etm_port_sel_cfg_t {
+	ZXIC_UINT32 etm_port0_sel_cfg;
+	ZXIC_UINT32 etm_port1_sel_cfg;
+	ZXIC_UINT32 etm_port2_sel_cfg;
+	ZXIC_UINT32 etm_port3_sel_cfg;
+} DPP_STAT_STAT_CFG_ETM_PORT_SEL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_tm_stat_cfg_t {
+	ZXIC_UINT32 stat_overflow_mode;
+	ZXIC_UINT32 tm_stat_mode_cfg;
+	ZXIC_UINT32 tm_flow_control_cfg;
+} DPP_STAT_STAT_CFG_TM_STAT_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_ppu_eram_depth_t {
+	ZXIC_UINT32 ppu_eram_depth;
+} DPP_STAT_STAT_CFG_PPU_ERAM_DEPTH_T;
+
+typedef struct dpp_stat_stat_cfg_ppu_eram_base_addr_t {
+	ZXIC_UINT32 ppu_eram_base_addr;
+} DPP_STAT_STAT_CFG_PPU_ERAM_BASE_ADDR_T;
+
+typedef struct dpp_stat_stat_cfg_ppu_ddr_base_addr_t {
+	ZXIC_UINT32 ppu_ddr_base_addr;
+} DPP_STAT_STAT_CFG_PPU_DDR_BASE_ADDR_T;
+
+typedef struct dpp_stat_stat_cfg_plcr0_base_addr_t {
+	ZXIC_UINT32 plcr0_base_addr;
+} DPP_STAT_STAT_CFG_PLCR0_BASE_ADDR_T;
+
+typedef struct dpp_stat_stat_cfg_etm_stat_start_addr_cfg_t {
+	ZXIC_UINT32 etm_stat_start_addr_cfg;
+} DPP_STAT_STAT_CFG_ETM_STAT_START_ADDR_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_etm_stat_depth_cfg_t {
+	ZXIC_UINT32 etm_stat_depth_cfg;
+} DPP_STAT_STAT_CFG_ETM_STAT_DEPTH_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_cycle_mov_en_cfg_t {
+	ZXIC_UINT32 cycle_mov_en_cfg;
+} DPP_STAT_STAT_CFG_CYCLE_MOV_EN_CFG_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat0_t {
+	ZXIC_UINT32 wdat0;
+} DPP_STAT_ETCAM_CPU_IND_WDAT0_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_ctrl_tmp0_t {
+	ZXIC_UINT32 reg_tcam_flag;
+	ZXIC_UINT32 flush;
+	ZXIC_UINT32 rd_wr;
+	ZXIC_UINT32 wr_mode;
+	ZXIC_UINT32 dat_or_mask;
+	ZXIC_UINT32 ram_sel;
+	ZXIC_UINT32 addr;
+} DPP_STAT_ETCAM_CPU_IND_CTRL_TMP0_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_ctrl_tmp1_t {
+	ZXIC_UINT32 row_or_col_msk;
+	ZXIC_UINT32 vben;
+	ZXIC_UINT32 vbit;
+} DPP_STAT_ETCAM_CPU_IND_CTRL_TMP1_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_rd_done_t {
+	ZXIC_UINT32 cpu_ind_rd_done;
+} DPP_STAT_ETCAM_CPU_IND_RD_DONE_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat0_t {
+	ZXIC_UINT32 cpu_rdat0;
+} DPP_STAT_ETCAM_CPU_RDAT0_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat1_t {
+	ZXIC_UINT32 cpu_rdat1;
+} DPP_STAT_ETCAM_CPU_RDAT1_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat2_t {
+	ZXIC_UINT32 cpu_rdat2;
+} DPP_STAT_ETCAM_CPU_RDAT2_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat3_t {
+	ZXIC_UINT32 cpu_rdat3;
+} DPP_STAT_ETCAM_CPU_RDAT3_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat4_t {
+	ZXIC_UINT32 cpu_rdat4;
+} DPP_STAT_ETCAM_CPU_RDAT4_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat5_t {
+	ZXIC_UINT32 cpu_rdat5;
+} DPP_STAT_ETCAM_CPU_RDAT5_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat6_t {
+	ZXIC_UINT32 cpu_rdat6;
+} DPP_STAT_ETCAM_CPU_RDAT6_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat7_t {
+	ZXIC_UINT32 cpu_rdat7;
+} DPP_STAT_ETCAM_CPU_RDAT7_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat8_t {
+	ZXIC_UINT32 cpu_rdat8;
+} DPP_STAT_ETCAM_CPU_RDAT8_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat9_t {
+	ZXIC_UINT32 cpu_rdat9;
+} DPP_STAT_ETCAM_CPU_RDAT9_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat10_t {
+	ZXIC_UINT32 cpu_rdat10;
+} DPP_STAT_ETCAM_CPU_RDAT10_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat11_t {
+	ZXIC_UINT32 cpu_rdat11;
+} DPP_STAT_ETCAM_CPU_RDAT11_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat12_t {
+	ZXIC_UINT32 cpu_rdat12;
+} DPP_STAT_ETCAM_CPU_RDAT12_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat13_t {
+	ZXIC_UINT32 cpu_rdat13;
+} DPP_STAT_ETCAM_CPU_RDAT13_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat14_t {
+	ZXIC_UINT32 cpu_rdat14;
+} DPP_STAT_ETCAM_CPU_RDAT14_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat15_t {
+	ZXIC_UINT32 cpu_rdat15;
+} DPP_STAT_ETCAM_CPU_RDAT15_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat16_t {
+	ZXIC_UINT32 cpu_rdat16;
+} DPP_STAT_ETCAM_CPU_RDAT16_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat17_t {
+	ZXIC_UINT32 cpu_rdat17;
+} DPP_STAT_ETCAM_CPU_RDAT17_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat18_t {
+	ZXIC_UINT32 cpu_rdat18;
+} DPP_STAT_ETCAM_CPU_RDAT18_T;
+
+typedef struct dpp_stat_etcam_cpu_rdat19_t {
+	ZXIC_UINT32 cpu_rdat19;
+} DPP_STAT_ETCAM_CPU_RDAT19_T;
+
+typedef struct dpp_stat_etcam_qvbo_t {
+	ZXIC_UINT32 qvbo;
+} DPP_STAT_ETCAM_QVBO_T;
+
+typedef struct dpp_stat_etcam_cnt_overflow_mode_t {
+	ZXIC_UINT32 cnt_rd_mode;
+	ZXIC_UINT32 cnt_overflow_mode;
+} DPP_STAT_ETCAM_CNT_OVERFLOW_MODE_T;
+
+typedef struct dpp_stat_car0_cara_queue_ram0_159_0_t {
+	ZXIC_UINT32 cara_drop;
+	ZXIC_UINT32 cara_plcr_en;
+	ZXIC_UINT32 cara_profile_id;
+	ZXIC_UINT32 cara_tq_h;
+	ZXIC_UINT32 cara_tq_l;
+	ZXIC_UINT32 cara_ted;
+	ZXIC_UINT32 cara_tcd;
+	ZXIC_UINT32 cara_tei;
+	ZXIC_UINT32 cara_tci;
+} DPP_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T;
+
+typedef struct dpp_stat_car0_cara_profile_ram1_255_0_t {
+	ZXIC_UINT32 cara_profile_wr;
+	ZXIC_UINT32 cara_pkt_sign;
+	ZXIC_UINT32 cara_cd;
+	ZXIC_UINT32 cara_cf;
+	ZXIC_UINT32 cara_cm;
+	ZXIC_UINT32 cara_eir;
+	ZXIC_UINT32 cara_cir;
+	ZXIC_UINT32 cara_ebs_pbs;
+	ZXIC_UINT32 cara_cbs;
+	ZXIC_UINT32 cara_c_pri1;
+	ZXIC_UINT32 cara_c_pri2;
+	ZXIC_UINT32 cara_c_pri3;
+	ZXIC_UINT32 cara_c_pri4;
+	ZXIC_UINT32 cara_c_pri5;
+	ZXIC_UINT32 cara_c_pri6;
+	ZXIC_UINT32 cara_c_pri7;
+	ZXIC_UINT32 cara_e_g_pri1;
+	ZXIC_UINT32 cara_e_g_pri2;
+	ZXIC_UINT32 cara_e_g_pri3;
+	ZXIC_UINT32 cara_e_g_pri4;
+	ZXIC_UINT32 cara_e_g_pri5;
+	ZXIC_UINT32 cara_e_g_pri6;
+	ZXIC_UINT32 cara_e_g_pri7;
+	ZXIC_UINT32 cara_e_y_pri0;
+	ZXIC_UINT32 cara_e_y_pri1;
+	ZXIC_UINT32 cara_e_y_pri2;
+	ZXIC_UINT32 cara_e_y_pri3;
+	ZXIC_UINT32 cara_e_y_pri4;
+	ZXIC_UINT32 cara_e_y_pri5;
+	ZXIC_UINT32 cara_e_y_pri6;
+	ZXIC_UINT32 cara_e_y_pri7;
+} DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_T;
+
+typedef struct dpp_stat_car0_cara_qovs_ram_ram2_t {
+	ZXIC_UINT32 cara_qovs;
+} DPP_STAT_CAR0_CARA_QOVS_RAM_RAM2_T;
+
+typedef struct dpp_stat_car0_look_up_table1_t {
+	ZXIC_UINT32 cara_flow_id;
+	ZXIC_UINT32 cara_sp;
+} DPP_STAT_CAR0_LOOK_UP_TABLE1_T;
+
+typedef struct dpp_stat_car0_cara_pkt_des_i_cnt_t {
+	ZXIC_UINT32 cara_pkt_des_i_cnt;
+} DPP_STAT_CAR0_CARA_PKT_DES_I_CNT_T;
+
+typedef struct dpp_stat_car0_cara_green_pkt_i_cnt_t {
+	ZXIC_UINT32 cara_green_pkt_i_cnt;
+} DPP_STAT_CAR0_CARA_GREEN_PKT_I_CNT_T;
+
+typedef struct dpp_stat_car0_cara_yellow_pkt_i_cnt_t {
+	ZXIC_UINT32 cara_yellow_pkt_i_cnt;
+} DPP_STAT_CAR0_CARA_YELLOW_PKT_I_CNT_T;
+
+typedef struct dpp_stat_car0_cara_red_pkt_i_cnt_t {
+	ZXIC_UINT32 cara_red_pkt_i_cnt;
+} DPP_STAT_CAR0_CARA_RED_PKT_I_CNT_T;
+
+typedef struct dpp_stat_car0_cara_pkt_des_o_cnt_t {
+	ZXIC_UINT32 cara_pkt_des_o_cnt;
+} DPP_STAT_CAR0_CARA_PKT_DES_O_CNT_T;
+
+typedef struct dpp_stat_car0_cara_green_pkt_o_cnt_t {
+	ZXIC_UINT32 cara_green_pkt_o_cnt;
+} DPP_STAT_CAR0_CARA_GREEN_PKT_O_CNT_T;
+
+typedef struct dpp_stat_car0_cara_yellow_pkt_o_cnt_t {
+	ZXIC_UINT32 cara_yellow_pkt_o_cnt;
+} DPP_STAT_CAR0_CARA_YELLOW_PKT_O_CNT_T;
+
+typedef struct dpp_stat_car0_cara_red_pkt_o_cnt_t {
+	ZXIC_UINT32 cara_red_pkt_o_cnt;
+} DPP_STAT_CAR0_CARA_RED_PKT_O_CNT_T;
+
+typedef struct dpp_stat_car0_cara_pkt_des_fc_for_cfg_cnt_t {
+	ZXIC_UINT32 cara_pkt_des_fc_for_cfg_cnt;
+} DPP_STAT_CAR0_CARA_PKT_DES_FC_FOR_CFG_CNT_T;
+
+typedef struct dpp_stat_car0_cara_appoint_qnum_or_sp_t {
+	ZXIC_UINT32 cara_appoint_qnum_or_not;
+	ZXIC_UINT32 cara_appoint_sp_or_not;
+	ZXIC_UINT32 cara_plcr_stat_sp;
+	ZXIC_UINT32 cara_plcr_stat_qnum;
+} DPP_STAT_CAR0_CARA_APPOINT_QNUM_OR_SP_T;
+
+typedef struct dpp_stat_car0_cara_cfgmt_count_mode_t {
+	ZXIC_UINT32 cara_cfgmt_count_overflow_mode;
+	ZXIC_UINT32 cara_cfgmt_count_rd_mode;
+} DPP_STAT_CAR0_CARA_CFGMT_COUNT_MODE_T;
+
+typedef struct dpp_stat_car0_cara_pkt_size_cnt_t {
+	ZXIC_UINT32 cara_pkt_size_cnt;
+} DPP_STAT_CAR0_CARA_PKT_SIZE_CNT_T;
+
+typedef struct dpp_stat_car0_cara_plcr_init_dont_t {
+	ZXIC_UINT32 cara_plcr_init_done;
+} DPP_STAT_CAR0_CARA_PLCR_INIT_DONT_T;
+
+typedef struct dpp_stat_car0_carb_queue_ram0_159_0_t {
+	ZXIC_UINT32 carb_drop;
+	ZXIC_UINT32 carb_plcr_en;
+	ZXIC_UINT32 carb_profile_id;
+	ZXIC_UINT32 carb_tq_h;
+	ZXIC_UINT32 carb_tq_l;
+	ZXIC_UINT32 carb_ted;
+	ZXIC_UINT32 carb_tcd;
+	ZXIC_UINT32 carb_tei;
+	ZXIC_UINT32 carb_tci;
+} DPP_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T;
+
+typedef struct dpp_stat_car0_carb_profile_ram1_255_0_t {
+	ZXIC_UINT32 carb_profile_wr;
+	ZXIC_UINT32 carb_random_discard_en_e;
+	ZXIC_UINT32 carb_random_discard_en_c;
+	ZXIC_UINT32 carb_pkt_sign;
+	ZXIC_UINT32 carb_cd;
+	ZXIC_UINT32 carb_cf;
+	ZXIC_UINT32 carb_cm;
+	ZXIC_UINT32 carb_eir;
+	ZXIC_UINT32 carb_cir;
+	ZXIC_UINT32 carb_ebs_pbs;
+	ZXIC_UINT32 carb_cbs;
+	ZXIC_UINT32 carb_c_pri1;
+	ZXIC_UINT32 carb_c_pri2;
+	ZXIC_UINT32 carb_c_pri3;
+	ZXIC_UINT32 carb_c_pri4;
+	ZXIC_UINT32 carb_c_pri5;
+	ZXIC_UINT32 carb_c_pri6;
+	ZXIC_UINT32 carb_c_pri7;
+	ZXIC_UINT32 carb_e_g_pri1;
+	ZXIC_UINT32 carb_e_g_pri2;
+	ZXIC_UINT32 carb_e_g_pri3;
+	ZXIC_UINT32 carb_e_g_pri4;
+	ZXIC_UINT32 carb_e_g_pri5;
+	ZXIC_UINT32 carb_e_g_pri6;
+	ZXIC_UINT32 carb_e_g_pri7;
+	ZXIC_UINT32 carb_e_y_pri0;
+	ZXIC_UINT32 carb_e_y_pri1;
+	ZXIC_UINT32 carb_e_y_pri2;
+	ZXIC_UINT32 carb_e_y_pri3;
+	ZXIC_UINT32 carb_e_y_pri4;
+	ZXIC_UINT32 carb_e_y_pri5;
+	ZXIC_UINT32 carb_e_y_pri6;
+	ZXIC_UINT32 carb_e_y_pri7;
+} DPP_STAT_CAR0_CARB_PROFILE_RAM1_255_0_T;
+
+typedef struct dpp_stat_car0_carb_qovs_ram_ram2_t {
+	ZXIC_UINT32 carb_qovs;
+} DPP_STAT_CAR0_CARB_QOVS_RAM_RAM2_T;
+
+typedef struct dpp_stat_car0_look_up_table2_t {
+	ZXIC_UINT32 carb_flow_id;
+	ZXIC_UINT32 carb_sp;
+} DPP_STAT_CAR0_LOOK_UP_TABLE2_T;
+
+typedef struct dpp_stat_car0_carb_pkt_des_i_cnt_t {
+	ZXIC_UINT32 carb_pkt_des_i_cnt;
+} DPP_STAT_CAR0_CARB_PKT_DES_I_CNT_T;
+
+typedef struct dpp_stat_car0_carb_green_pkt_i_cnt_t {
+	ZXIC_UINT32 carb_green_pkt_i_cnt;
+} DPP_STAT_CAR0_CARB_GREEN_PKT_I_CNT_T;
+
+typedef struct dpp_stat_car0_carb_yellow_pkt_i_cnt_t {
+	ZXIC_UINT32 carb_yellow_pkt_i_cnt;
+} DPP_STAT_CAR0_CARB_YELLOW_PKT_I_CNT_T;
+
+typedef struct dpp_stat_car0_carb_red_pkt_i_cnt_t {
+	ZXIC_UINT32 carb_red_pkt_i_cnt;
+} DPP_STAT_CAR0_CARB_RED_PKT_I_CNT_T;
+
+typedef struct dpp_stat_car0_carb_pkt_des_o_cnt_t {
+	ZXIC_UINT32 carb_pkt_des_o_cnt;
+} DPP_STAT_CAR0_CARB_PKT_DES_O_CNT_T;
+
+typedef struct dpp_stat_car0_carb_green_pkt_o_cnt_t {
+	ZXIC_UINT32 carb_green_pkt_o_cnt;
+} DPP_STAT_CAR0_CARB_GREEN_PKT_O_CNT_T;
+
+typedef struct dpp_stat_car0_carb_yellow_pkt_o_cnt_t {
+	ZXIC_UINT32 carb_yellow_pkt_o_cnt;
+} DPP_STAT_CAR0_CARB_YELLOW_PKT_O_CNT_T;
+
+typedef struct dpp_stat_car0_carb_red_pkt_o_cnt_t {
+	ZXIC_UINT32 carb_red_pkt_o_cnt;
+} DPP_STAT_CAR0_CARB_RED_PKT_O_CNT_T;
+
+typedef struct dpp_stat_car0_carb_pkt_des_fc_for_cfg_cnt_t {
+	ZXIC_UINT32 carb_pkt_des_fc_for_cfg_cnt;
+} DPP_STAT_CAR0_CARB_PKT_DES_FC_FOR_CFG_CNT_T;
+
+typedef struct dpp_stat_car0_carb_appoint_qnum_or_sp_t {
+	ZXIC_UINT32 carb_appoint_qnum_or_not;
+	ZXIC_UINT32 carb_appoint_sp_or_not;
+	ZXIC_UINT32 carb_plcr_stat_sp;
+	ZXIC_UINT32 carb_plcr_stat_qnum;
+} DPP_STAT_CAR0_CARB_APPOINT_QNUM_OR_SP_T;
+
+typedef struct dpp_stat_car0_carb_cfgmt_count_mode_t {
+	ZXIC_UINT32 carb_cfgmt_count_overflow_mode;
+	ZXIC_UINT32 carb_cfgmt_count_rd_mode;
+} DPP_STAT_CAR0_CARB_CFGMT_COUNT_MODE_T;
+
+typedef struct dpp_stat_car0_carb_pkt_size_cnt_t {
+	ZXIC_UINT32 carb_pkt_size_cnt;
+} DPP_STAT_CAR0_CARB_PKT_SIZE_CNT_T;
+
+typedef struct dpp_stat_car0_carb_plcr_init_dont_t {
+	ZXIC_UINT32 carb_plcr_init_done;
+} DPP_STAT_CAR0_CARB_PLCR_INIT_DONT_T;
+
+typedef struct dpp_stat_car0_carc_queue_ram0_159_0_t {
+	ZXIC_UINT32 carc_drop;
+	ZXIC_UINT32 carc_plcr_en;
+	ZXIC_UINT32 carc_profile_id;
+	ZXIC_UINT32 carc_tq_h;
+	ZXIC_UINT32 carc_tq_l;
+	ZXIC_UINT32 carc_ted;
+	ZXIC_UINT32 carc_tcd;
+	ZXIC_UINT32 carc_tei;
+	ZXIC_UINT32 carc_tci;
+} DPP_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T;
+
+typedef struct dpp_stat_car0_carc_profile_ram1_255_0_t {
+	ZXIC_UINT32 carc_profile_wr;
+	ZXIC_UINT32 carc_random_discard_en_e;
+	ZXIC_UINT32 carc_random_discard_en_c;
+	ZXIC_UINT32 carc_pkt_sign;
+	ZXIC_UINT32 carc_cd;
+	ZXIC_UINT32 carc_cf;
+	ZXIC_UINT32 carc_cm;
+	ZXIC_UINT32 carc_eir;
+	ZXIC_UINT32 carc_cir;
+	ZXIC_UINT32 carc_ebs_pbs;
+	ZXIC_UINT32 carc_cbs;
+	ZXIC_UINT32 carc_c_pri1;
+	ZXIC_UINT32 carc_c_pri2;
+	ZXIC_UINT32 carc_c_pri3;
+	ZXIC_UINT32 carc_c_pri4;
+	ZXIC_UINT32 carc_c_pri5;
+	ZXIC_UINT32 carc_c_pri6;
+	ZXIC_UINT32 carc_c_pri7;
+	ZXIC_UINT32 carc_e_g_pri1;
+	ZXIC_UINT32 carc_e_g_pri2;
+	ZXIC_UINT32 carc_e_g_pri3;
+	ZXIC_UINT32 carc_e_g_pri4;
+	ZXIC_UINT32 carc_e_g_pri5;
+	ZXIC_UINT32 carc_e_g_pri6;
+	ZXIC_UINT32 carc_e_g_pri7;
+	ZXIC_UINT32 carc_e_y_pri0;
+	ZXIC_UINT32 carc_e_y_pri1;
+	ZXIC_UINT32 carc_e_y_pri2;
+	ZXIC_UINT32 carc_e_y_pri3;
+	ZXIC_UINT32 carc_e_y_pri4;
+	ZXIC_UINT32 carc_e_y_pri5;
+	ZXIC_UINT32 carc_e_y_pri6;
+	ZXIC_UINT32 carc_e_y_pri7;
+} DPP_STAT_CAR0_CARC_PROFILE_RAM1_255_0_T;
+
+typedef struct dpp_stat_car0_carc_qovs_ram_ram2_t {
+	ZXIC_UINT32 carc_qovs;
+} DPP_STAT_CAR0_CARC_QOVS_RAM_RAM2_T;
+
+typedef struct dpp_stat_car0_carc_pkt_des_i_cnt_t {
+	ZXIC_UINT32 carc_pkt_des_i_cnt;
+} DPP_STAT_CAR0_CARC_PKT_DES_I_CNT_T;
+
+typedef struct dpp_stat_car0_carc_green_pkt_i_cnt_t {
+	ZXIC_UINT32 carc_green_pkt_i_cnt;
+} DPP_STAT_CAR0_CARC_GREEN_PKT_I_CNT_T;
+
+typedef struct dpp_stat_car0_carc_yellow_pkt_i_cnt_t {
+	ZXIC_UINT32 carc_yellow_pkt_i_cnt;
+} DPP_STAT_CAR0_CARC_YELLOW_PKT_I_CNT_T;
+
+typedef struct dpp_stat_car0_carc_red_pkt_i_cnt_t {
+	ZXIC_UINT32 carc_red_pkt_i_cnt;
+} DPP_STAT_CAR0_CARC_RED_PKT_I_CNT_T;
+
+typedef struct dpp_stat_car0_carc_pkt_des_o_cnt_t {
+	ZXIC_UINT32 carc_pkt_des_o_cnt;
+} DPP_STAT_CAR0_CARC_PKT_DES_O_CNT_T;
+
+typedef struct dpp_stat_car0_carc_green_pkt_o_cnt_t {
+	ZXIC_UINT32 carc_green_pkt_o_cnt;
+} DPP_STAT_CAR0_CARC_GREEN_PKT_O_CNT_T;
+
+typedef struct dpp_stat_car0_carc_yellow_pkt_o_cnt_t {
+	ZXIC_UINT32 carc_yellow_pkt_o_cnt;
+} DPP_STAT_CAR0_CARC_YELLOW_PKT_O_CNT_T;
+
+typedef struct dpp_stat_car0_carc_red_pkt_o_cnt_t {
+	ZXIC_UINT32 carc_red_pkt_o_cnt;
+} DPP_STAT_CAR0_CARC_RED_PKT_O_CNT_T;
+
+typedef struct dpp_stat_car0_carc_pkt_des_fc_for_cfg_cnt_t {
+	ZXIC_UINT32 carc_pkt_des_fc_for_cfg_cnt;
+} DPP_STAT_CAR0_CARC_PKT_DES_FC_FOR_CFG_CNT_T;
+
+typedef struct dpp_stat_car0_carc_appoint_qnum_or_sp_t {
+	ZXIC_UINT32 carc_appoint_qnum_or_not;
+	ZXIC_UINT32 carc_appoint_sp_or_not;
+	ZXIC_UINT32 carc_plcr_stat_sp;
+	ZXIC_UINT32 carc_plcr_stat_qnum;
+} DPP_STAT_CAR0_CARC_APPOINT_QNUM_OR_SP_T;
+
+typedef struct dpp_stat_car0_carc_cfgmt_count_mode_t {
+	ZXIC_UINT32 carc_cfgmt_count_overflow_mode;
+	ZXIC_UINT32 carc_cfgmt_count_rd_mode;
+} DPP_STAT_CAR0_CARC_CFGMT_COUNT_MODE_T;
+
+typedef struct dpp_stat_car0_carc_pkt_size_cnt_t {
+	ZXIC_UINT32 carc_pkt_size_cnt;
+} DPP_STAT_CAR0_CARC_PKT_SIZE_CNT_T;
+
+typedef struct dpp_stat_car0_carc_plcr_init_dont_t {
+	ZXIC_UINT32 carc_plcr_init_done;
+} DPP_STAT_CAR0_CARC_PLCR_INIT_DONT_T;
+
+typedef struct dpp_stat_car0_carb_random_ram_t {
+	ZXIC_UINT32 para8_e;
+	ZXIC_UINT32 para7_e;
+	ZXIC_UINT32 para6_e;
+	ZXIC_UINT32 para5_e;
+	ZXIC_UINT32 para4_h_e;
+	ZXIC_UINT32 para4_l_e;
+	ZXIC_UINT32 para3_e;
+	ZXIC_UINT32 para2_h_e;
+	ZXIC_UINT32 para2_l_e;
+	ZXIC_UINT32 para1_e;
+	ZXIC_UINT32 para0_h_e;
+	ZXIC_UINT32 para0_l_e;
+	ZXIC_UINT32 para8_c;
+	ZXIC_UINT32 para7_c;
+	ZXIC_UINT32 para6_c;
+	ZXIC_UINT32 para5_c;
+	ZXIC_UINT32 para4_h_c;
+	ZXIC_UINT32 para4_l_c;
+	ZXIC_UINT32 para3_c;
+	ZXIC_UINT32 para2_h_c;
+	ZXIC_UINT32 para2_l_c;
+	ZXIC_UINT32 para1_c;
+	ZXIC_UINT32 para0_h_c;
+	ZXIC_UINT32 para0_l_c;
+} DPP_STAT_CAR0_CARB_RANDOM_RAM_T;
+
+typedef struct dpp_stat_car0_carc_random_ram_t {
+	ZXIC_UINT32 para8_e;
+	ZXIC_UINT32 para7_e;
+	ZXIC_UINT32 para6_e;
+	ZXIC_UINT32 para5_e;
+	ZXIC_UINT32 para4_h_e;
+	ZXIC_UINT32 para4_l_e;
+	ZXIC_UINT32 para3_e;
+	ZXIC_UINT32 para2_h_e;
+	ZXIC_UINT32 para2_l_e;
+	ZXIC_UINT32 para1_e;
+	ZXIC_UINT32 para0_h_e;
+	ZXIC_UINT32 para0_l_e;
+	ZXIC_UINT32 para8_c;
+	ZXIC_UINT32 para7_c;
+	ZXIC_UINT32 para6_c;
+	ZXIC_UINT32 para5_c;
+	ZXIC_UINT32 para4_h_c;
+	ZXIC_UINT32 para4_l_c;
+	ZXIC_UINT32 para3_c;
+	ZXIC_UINT32 para2_h_c;
+	ZXIC_UINT32 para2_l_c;
+	ZXIC_UINT32 para1_c;
+	ZXIC_UINT32 para0_h_c;
+	ZXIC_UINT32 para0_l_c;
+} DPP_STAT_CAR0_CARC_RANDOM_RAM_T;
+
+typedef struct dpp_stat_car0_cara_begin_flow_id_t {
+	ZXIC_UINT32 cara_begin_flow_id;
+} DPP_STAT_CAR0_CARA_BEGIN_FLOW_ID_T;
+
+typedef struct dpp_stat_car0_carb_begin_flow_id_t {
+	ZXIC_UINT32 carb_begin_flow_id;
+} DPP_STAT_CAR0_CARB_BEGIN_FLOW_ID_T;
+
+typedef struct dpp_stat_car0_carc_begin_flow_id_t {
+	ZXIC_UINT32 carc_begin_flow_id;
+} DPP_STAT_CAR0_CARC_BEGIN_FLOW_ID_T;
+
+typedef struct dpp_stat_car0_prog_full_assert_cfg_w_t {
+	ZXIC_UINT32 prog_full_assert_cfg_w;
+} DPP_STAT_CAR0_PROG_FULL_ASSERT_CFG_W_T;
+
+typedef struct dpp_stat_car0_prog_full_negate_cfg_w_t {
+	ZXIC_UINT32 prog_full_negate_cfg_w;
+} DPP_STAT_CAR0_PROG_FULL_NEGATE_CFG_W_T;
+
+typedef struct dpp_stat_car0_timeout_limit_t {
+	ZXIC_UINT32 timeout_limit;
+} DPP_STAT_CAR0_TIMEOUT_LIMIT_T;
+
+typedef struct dpp_stat_car0_pkt_des_fifo_overflow_t {
+	ZXIC_UINT32 pkt_des_fifo_overflow;
+} DPP_STAT_CAR0_PKT_DES_FIFO_OVERFLOW_T;
+
+typedef struct dpp_stat_car0_pkt_des_fifo_underflow_t {
+	ZXIC_UINT32 pkt_des_fifo_underflow;
+} DPP_STAT_CAR0_PKT_DES_FIFO_UNDERFLOW_T;
+
+typedef struct dpp_stat_car0_pkt_des_fifo_prog_full_t {
+	ZXIC_UINT32 pkt_des_fifo_prog_full;
+} DPP_STAT_CAR0_PKT_DES_FIFO_PROG_FULL_T;
+
+typedef struct dpp_stat_car0_pkt_des_fifo_prog_empty_t {
+	ZXIC_UINT32 pkt_des_fifo_prog_empty;
+} DPP_STAT_CAR0_PKT_DES_FIFO_PROG_EMPTY_T;
+
+typedef struct dpp_stat_car0_pkt_des_fifo_full_t {
+	ZXIC_UINT32 pkt_des_fifo_full;
+} DPP_STAT_CAR0_PKT_DES_FIFO_FULL_T;
+
+typedef struct dpp_stat_car0_pkt_des_fifo_empty_t {
+	ZXIC_UINT32 pkt_des_fifo_empty;
+} DPP_STAT_CAR0_PKT_DES_FIFO_EMPTY_T;
+
+typedef struct dpp_stat_car0_pkt_size_offset_t {
+	ZXIC_UINT32 pkt_size_offset;
+} DPP_STAT_CAR0_PKT_SIZE_OFFSET_T;
+
+typedef struct dpp_stat_car0_car_plcr_init_dont_t {
+	ZXIC_UINT32 plcr_init_done;
+} DPP_STAT_CAR0_CAR_PLCR_INIT_DONT_T;
+
+typedef struct dpp_stat_car0_max_pkt_size_a_t {
+	ZXIC_UINT32 max_pkt_size_a;
+} DPP_STAT_CAR0_MAX_PKT_SIZE_A_T;
+
+typedef struct dpp_stat_car0_max_pkt_size_b_t {
+	ZXIC_UINT32 max_pkt_size_b;
+} DPP_STAT_CAR0_MAX_PKT_SIZE_B_T;
+
+typedef struct dpp_stat_car0_max_pkt_size_c_t {
+	ZXIC_UINT32 max_pkt_size_c;
+} DPP_STAT_CAR0_MAX_PKT_SIZE_C_T;
+
+typedef struct dpp_stat_car0_car_hierarchy_mode_t {
+	ZXIC_UINT32 car_hierarchy_mode;
+} DPP_STAT_CAR0_CAR_HIERARCHY_MODE_T;
+
+typedef struct dpp_stat_car0_prog_empty_assert_cfg_w_t {
+	ZXIC_UINT32 prog_empty_assert_cfg_w;
+} DPP_STAT_CAR0_PROG_EMPTY_ASSERT_CFG_W_T;
+
+typedef struct dpp_stat_car0_prog_empty_negate_cfg_w_t {
+	ZXIC_UINT32 prog_empty_negate_cfg_w;
+} DPP_STAT_CAR0_PROG_EMPTY_NEGATE_CFG_W_T;
+
+typedef struct dpp_stat_car0_pkt_des_fifo_ovf_int_t {
+	ZXIC_UINT32 pkt_des_fifo_ovf_int;
+} DPP_STAT_CAR0_PKT_DES_FIFO_OVF_INT_T;
+
+typedef struct dpp_stat_car0_pkt_des_fifo_data_count_t {
+	ZXIC_UINT32 pkt_des_fifo_data_count;
+} DPP_STAT_CAR0_PKT_DES_FIFO_DATA_COUNT_T;
+
+typedef struct dpp_stat_car0_pkt_des_fifo_udf_int_t {
+	ZXIC_UINT32 pkt_des_fifo_udf_int;
+} DPP_STAT_CAR0_PKT_DES_FIFO_UDF_INT_T;
+
+typedef struct dpp_stat_car0_cara_queue_ram0_159_0_pkt_t {
+	ZXIC_UINT32 cara_drop;
+	ZXIC_UINT32 cara_plcr_en;
+	ZXIC_UINT32 cara_profile_id;
+	ZXIC_UINT32 cara_tq_h;
+	ZXIC_UINT32 cara_tq_l;
+	ZXIC_UINT32 cara_dc_high;
+	ZXIC_UINT32 cara_dc_low;
+	ZXIC_UINT32 cara_tc;
+} DPP_STAT_CAR0_CARA_QUEUE_RAM0_159_0_PKT_T;
+
+typedef struct dpp_stat_car0_cara_profile_ram1_255_0_pkt_t {
+	ZXIC_UINT32 cara_profile_wr;
+	ZXIC_UINT32 cara_pkt_sign;
+	ZXIC_UINT32 cara_pkt_cir;
+	ZXIC_UINT32 cara_pkt_cbs;
+	ZXIC_UINT32 cara_pri0;
+	ZXIC_UINT32 cara_pri1;
+	ZXIC_UINT32 cara_pri2;
+	ZXIC_UINT32 cara_pri3;
+	ZXIC_UINT32 cara_pri4;
+	ZXIC_UINT32 cara_pri5;
+	ZXIC_UINT32 cara_pri6;
+	ZXIC_UINT32 cara_pri7;
+} DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKT_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_eram_wdat1_t {
+	ZXIC_UINT32 cpu_ind_eram_wdat1;
+} DPP_STAT_STAT_CFG_CPU_IND_ERAM_WDAT1_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_eram_wdat2_t {
+	ZXIC_UINT32 cpu_ind_eram_wdat2;
+} DPP_STAT_STAT_CFG_CPU_IND_ERAM_WDAT2_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_eram_wdat3_t {
+	ZXIC_UINT32 cpu_ind_eram_wdat3;
+} DPP_STAT_STAT_CFG_CPU_IND_ERAM_WDAT3_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_eram_req_info_t {
+	ZXIC_UINT32 rw_mode;
+	ZXIC_UINT32 read_mode;
+	ZXIC_UINT32 tm_cs;
+	ZXIC_UINT32 queue_cs;
+	ZXIC_UINT32 rw_addr;
+} DPP_STAT_STAT_CFG_CPU_IND_ERAM_REQ_INFO_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_eram_rd_done_t {
+	ZXIC_UINT32 cpu_ind_eram_rd_done;
+} DPP_STAT_STAT_CFG_CPU_IND_ERAM_RD_DONE_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_eram_rdat0_t {
+	ZXIC_UINT32 cpu_ind_eram_rdat0;
+} DPP_STAT_STAT_CFG_CPU_IND_ERAM_RDAT0_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_eram_rdat1_t {
+	ZXIC_UINT32 cpu_ind_eram_rdat1;
+} DPP_STAT_STAT_CFG_CPU_IND_ERAM_RDAT1_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_eram_rdat2_t {
+	ZXIC_UINT32 cpu_ind_eram_rdat2;
+} DPP_STAT_STAT_CFG_CPU_IND_ERAM_RDAT2_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_eram_rdat3_t {
+	ZXIC_UINT32 cpu_ind_eram_rdat3;
+} DPP_STAT_STAT_CFG_CPU_IND_ERAM_RDAT3_T;
+
+typedef struct dpp_stat_stat_cfg_tm_alu_eram_cpu_rdy_t {
+	ZXIC_UINT32 tm_alu_eram_cpu_rdy;
+} DPP_STAT_STAT_CFG_TM_ALU_ERAM_CPU_RDY_T;
+
+typedef struct dpp_stat_stat_cfg_oam_stat_cfg_t {
+	ZXIC_UINT32 oam_flow_control_cfg;
+	ZXIC_UINT32 oam_lm_flow_control_cfg;
+	ZXIC_UINT32 oam_in_eram_cfg;
+} DPP_STAT_STAT_CFG_OAM_STAT_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_ftm_port_sel_cfg_t {
+	ZXIC_UINT32 ftm_port0_sel_cfg;
+	ZXIC_UINT32 ftm_port1_sel_cfg;
+	ZXIC_UINT32 ftm_port2_sel_cfg;
+	ZXIC_UINT32 ftm_port3_sel_cfg;
+} DPP_STAT_STAT_CFG_FTM_PORT_SEL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_oam_eram_base_addr_t {
+	ZXIC_UINT32 oam_eram_base_addr;
+} DPP_STAT_STAT_CFG_OAM_ERAM_BASE_ADDR_T;
+
+typedef struct dpp_stat_stat_cfg_oam_lm_eram_base_addr_t {
+	ZXIC_UINT32 oam_lm_eram_base_addr;
+} DPP_STAT_STAT_CFG_OAM_LM_ERAM_BASE_ADDR_T;
+
+typedef struct dpp_stat_stat_cfg_oam_ddr_base_addr_t {
+	ZXIC_UINT32 oam_ddr_base_addr;
+} DPP_STAT_STAT_CFG_OAM_DDR_BASE_ADDR_T;
+
+typedef struct dpp_stat_stat_cfg_plcr0_schd_pful_cfg_t {
+	ZXIC_UINT32 plcr0_schd_pful_assert;
+	ZXIC_UINT32 plcr0_schd_pful_negate;
+} DPP_STAT_STAT_CFG_PLCR0_SCHD_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_oam_lm_ord_pful_cfg_t {
+	ZXIC_UINT32 oam_lm_ord_pful_assert;
+	ZXIC_UINT32 oam_lm_ord_pful_negate;
+} DPP_STAT_STAT_CFG_OAM_LM_ORD_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_ddr_schd_pful_cfg_t {
+	ZXIC_UINT32 ddr_schd_pful_assert;
+	ZXIC_UINT32 ddr_schd_pful_negate;
+} DPP_STAT_STAT_CFG_DDR_SCHD_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_eram_schd_pful_cfg_t {
+	ZXIC_UINT32 eram_schd_pful_assert;
+	ZXIC_UINT32 eram_schd_pful_negate;
+} DPP_STAT_STAT_CFG_ERAM_SCHD_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_eram_schd_pept_cfg_t {
+	ZXIC_UINT32 eram_schd_pept_assert;
+	ZXIC_UINT32 eram_schd_pept_negate;
+} DPP_STAT_STAT_CFG_ERAM_SCHD_PEPT_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_eram_schd_oam_pful_cfg_t {
+	ZXIC_UINT32 eram_schd_oam_pful_assert;
+	ZXIC_UINT32 eram_schd_oam_pful_negate;
+} DPP_STAT_STAT_CFG_ERAM_SCHD_OAM_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_eram_schd_oam_pept_cfg_t {
+	ZXIC_UINT32 eram_schd_oam_pept_assert;
+	ZXIC_UINT32 eram_schd_oam_pept_negate;
+} DPP_STAT_STAT_CFG_ERAM_SCHD_OAM_PEPT_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_eram_schd_oam_lm_pful_cfg_t {
+	ZXIC_UINT32 eram_schd_oam_lm_pful_assert;
+	ZXIC_UINT32 eram_schd_oam_lm_pful_negate;
+} DPP_STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_eram_schd_oam_lm_pept_cfg_t {
+	ZXIC_UINT32 eram_schd_oam_lm_pept_assert;
+	ZXIC_UINT32 eram_schd_oam_lm_pept_negate;
+} DPP_STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PEPT_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_rschd_pful_cfg_t {
+	ZXIC_UINT32 rschd_pful_assert;
+	ZXIC_UINT32 rschd_pful_negate;
+} DPP_STAT_STAT_CFG_RSCHD_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_rschd_pept_cfg_t {
+	ZXIC_UINT32 rschd_pept_assert;
+	ZXIC_UINT32 rschd_pept_negate;
+} DPP_STAT_STAT_CFG_RSCHD_PEPT_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_rschd_plcr_pful_cfg_t {
+	ZXIC_UINT32 rschd_plcr_pful_assert;
+	ZXIC_UINT32 rschd_plcr_pful_negate;
+} DPP_STAT_STAT_CFG_RSCHD_PLCR_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_rschd_plcr_pept_cfg_t {
+	ZXIC_UINT32 rschd_plcr_pept_assert;
+	ZXIC_UINT32 rschd_plcr_pept_negate;
+} DPP_STAT_STAT_CFG_RSCHD_PLCR_PEPT_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_rschd_plcr_info_pful_cfg_t {
+	ZXIC_UINT32 rschd_plcr_info_pful_assert;
+	ZXIC_UINT32 rschd_plcr_info_pful_negate;
+} DPP_STAT_STAT_CFG_RSCHD_PLCR_INFO_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_alu_arb_cpu_pful_cfg_t {
+	ZXIC_UINT32 alu_arb_cpu_pful_assert;
+	ZXIC_UINT32 alu_arb_cpu_pful_negate;
+} DPP_STAT_STAT_CFG_ALU_ARB_CPU_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_alu_arb_user_pful_cfg_t {
+	ZXIC_UINT32 alu_arb_user_pful_assert;
+	ZXIC_UINT32 alu_arb_user_pful_negate;
+} DPP_STAT_STAT_CFG_ALU_ARB_USER_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_alu_arb_stat_pful_cfg_t {
+	ZXIC_UINT32 alu_arb_stat_pful_assert;
+	ZXIC_UINT32 alu_arb_stat_pful_negate;
+} DPP_STAT_STAT_CFG_ALU_ARB_STAT_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_cycmov_dat_pful_cfg_t {
+	ZXIC_UINT32 cycmov_dat_pful_assert;
+	ZXIC_UINT32 cycmov_dat_pful_negate;
+} DPP_STAT_STAT_CFG_CYCMOV_DAT_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_ddr_opr_pful_cfg_t {
+	ZXIC_UINT32 ddr_opr_pful_assert;
+	ZXIC_UINT32 ddr_opr_pful_negate;
+} DPP_STAT_STAT_CFG_DDR_OPR_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_cycle_mov_pful_cfg_t {
+	ZXIC_UINT32 cycle_mov_pful_assert;
+	ZXIC_UINT32 cycle_mov_pful_negate;
+} DPP_STAT_STAT_CFG_CYCLE_MOV_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_cntovf_pful_cfg_t {
+	ZXIC_UINT32 cntovf_pful_assert;
+	ZXIC_UINT32 cntovf_pful_negate;
+} DPP_STAT_STAT_CFG_CNTOVF_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_eram_schd_plcr_pful_cfg_t {
+	ZXIC_UINT32 eram_schd_plcr_pful_assert;
+	ZXIC_UINT32 eram_schd_plcr_pful_negate;
+} DPP_STAT_STAT_CFG_ERAM_SCHD_PLCR_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_eram_schd_plcr_pept_cfg_t {
+	ZXIC_UINT32 eram_schd_plcr_pept_assert;
+	ZXIC_UINT32 eram_schd_plcr_pept_negate;
+} DPP_STAT_STAT_CFG_ERAM_SCHD_PLCR_PEPT_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_debug_cnt_mode_t {
+	ZXIC_UINT32 cnt_rd_mode;
+	ZXIC_UINT32 cnt_overflow_mode;
+} DPP_STAT_STAT_CFG_DEBUG_CNT_MODE_T;
+
+typedef struct dpp_stat_stat_cfg_tm_mov_period_cfg_t {
+	ZXIC_UINT32 etm_mov_period_cfg;
+	ZXIC_UINT32 ftm_mov_period_cfg;
+} DPP_STAT_STAT_CFG_TM_MOV_PERIOD_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_alu_ddr_cpu_req_pful_cfg_t {
+	ZXIC_UINT32 alu_ddr_cpu_req_pful_assert;
+	ZXIC_UINT32 alu_ddr_cpu_req_pful_negate;
+} DPP_STAT_STAT_CFG_ALU_DDR_CPU_REQ_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_cycmov_addr_pful_cfg_t {
+	ZXIC_UINT32 cycmov_addr_pful_assert;
+	ZXIC_UINT32 cycmov_addr_pful_negate;
+} DPP_STAT_STAT_CFG_CYCMOV_ADDR_PFUL_CFG_T;
+
+typedef struct dpp_stat_stat_cfg_ord_ddr_plcr_fifo_empty_t {
+	ZXIC_UINT32 ord_oam_lm_empty;
+	ZXIC_UINT32 ddr_schd_fifo_empty;
+	ZXIC_UINT32 plcr0_schd_fifo_empty;
+} DPP_STAT_STAT_CFG_ORD_DDR_PLCR_FIFO_EMPTY_T;
+
+typedef struct dpp_stat_stat_cfg_tm_stat_fifo_empty_t {
+	ZXIC_UINT32 tm_stat_fifo_empty;
+} DPP_STAT_STAT_CFG_TM_STAT_FIFO_EMPTY_T;
+
+typedef struct dpp_stat_stat_cfg_eram_schd_fifo_empty_0_1_t {
+	ZXIC_UINT32 eram_schd_fifo_empty1;
+	ZXIC_UINT32 eram_schd_fifo_empty0;
+} DPP_STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_0_1_T;
+
+typedef struct dpp_stat_stat_cfg_eram_schd_fifo_empty_2_3_t {
+	ZXIC_UINT32 eram_schd_fifo_empty3;
+	ZXIC_UINT32 eram_schd_fifo_empty2;
+} DPP_STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_2_3_T;
+
+typedef struct dpp_stat_stat_cfg_eram_schd_fifo_empty_4_5_t {
+	ZXIC_UINT32 eram_schd_fifo_empty5;
+	ZXIC_UINT32 eram_schd_fifo_empty4;
+} DPP_STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_4_5_T;
+
+typedef struct dpp_stat_stat_cfg_eram_schd_fifo_empty_6_7_t {
+	ZXIC_UINT32 eram_schd_fifo_empty7;
+	ZXIC_UINT32 eram_schd_fifo_empty6;
+} DPP_STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_6_7_T;
+
+typedef struct dpp_stat_stat_cfg_eram_schd_fifo_empty_free_8_t {
+	ZXIC_UINT32 eram_schd_free_fifo_empty8;
+	ZXIC_UINT32 eram_schd_free_fifo_empty7;
+	ZXIC_UINT32 eram_schd_free_fifo_empty6;
+	ZXIC_UINT32 eram_schd_free_fifo_empty5;
+	ZXIC_UINT32 eram_schd_free_fifo_empty4;
+	ZXIC_UINT32 eram_schd_free_fifo_empty3;
+	ZXIC_UINT32 eram_schd_free_fifo_empty2;
+	ZXIC_UINT32 eram_schd_free_fifo_empty1;
+	ZXIC_UINT32 eram_schd_free_fifo_empty0;
+	ZXIC_UINT32 eram_schd_fifo_empty8;
+} DPP_STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_FREE_8_T;
+
+typedef struct dpp_stat_stat_cfg_rschd_fifo_empty_0_3_t {
+	ZXIC_UINT32 rschd_fifo_empty3;
+	ZXIC_UINT32 rschd_fifo_empty2;
+	ZXIC_UINT32 rschd_fifo_empty1;
+	ZXIC_UINT32 rschd_fifo_empty0;
+} DPP_STAT_STAT_CFG_RSCHD_FIFO_EMPTY_0_3_T;
+
+typedef struct dpp_stat_stat_cfg_rschd_fifo_empty_4_7_t {
+	ZXIC_UINT32 rschd_fifo_empty7;
+	ZXIC_UINT32 rschd_fifo_empty6;
+	ZXIC_UINT32 rschd_fifo_empty5;
+	ZXIC_UINT32 rschd_fifo_empty4;
+} DPP_STAT_STAT_CFG_RSCHD_FIFO_EMPTY_4_7_T;
+
+typedef struct dpp_stat_stat_cfg_rschd_fifo_empty_8_11_t {
+	ZXIC_UINT32 rschd_fifo_empty11;
+	ZXIC_UINT32 rschd_fifo_empty10;
+	ZXIC_UINT32 rschd_fifo_empty9;
+	ZXIC_UINT32 rschd_fifo_empty8;
+} DPP_STAT_STAT_CFG_RSCHD_FIFO_EMPTY_8_11_T;
+
+typedef struct dpp_stat_stat_cfg_rschd_fifo_empty_12_15_t {
+	ZXIC_UINT32 rschd_fifo_empty15;
+	ZXIC_UINT32 rschd_fifo_empty14;
+	ZXIC_UINT32 rschd_fifo_empty13;
+	ZXIC_UINT32 rschd_fifo_empty12;
+} DPP_STAT_STAT_CFG_RSCHD_FIFO_EMPTY_12_15_T;
+
+typedef struct dpp_stat_stat_cfg_rschd_fifo_empty_plcr_16_17_t {
+	ZXIC_UINT32 rschd_fifo_empty_plcr;
+	ZXIC_UINT32 rschd_fifo_empty17;
+	ZXIC_UINT32 rschd_fifo_empty16;
+} DPP_STAT_STAT_CFG_RSCHD_FIFO_EMPTY_PLCR_16_17_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int_unmask_flag_t {
+	ZXIC_UINT32 stat_int5_unmask_flag;
+	ZXIC_UINT32 stat_int4_unmask_flag;
+	ZXIC_UINT32 stat_int3_unmask_flag;
+	ZXIC_UINT32 stat_int2_unmask_flag;
+	ZXIC_UINT32 stat_int1_unmask_flag;
+	ZXIC_UINT32 stat_int0_unmask_flag;
+} DPP_STAT_STAT_CFG_STAT_INT_UNMASK_FLAG_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int0_en_t {
+	ZXIC_UINT32 stat_int0_en31;
+	ZXIC_UINT32 stat_int0_en30;
+	ZXIC_UINT32 stat_int0_en29;
+	ZXIC_UINT32 stat_int0_en28;
+	ZXIC_UINT32 stat_int0_en27;
+	ZXIC_UINT32 stat_int0_en26;
+	ZXIC_UINT32 stat_int0_en25;
+	ZXIC_UINT32 stat_int0_en24;
+	ZXIC_UINT32 stat_int0_en23;
+	ZXIC_UINT32 stat_int0_en22;
+	ZXIC_UINT32 stat_int0_en21;
+	ZXIC_UINT32 stat_int0_en20;
+	ZXIC_UINT32 stat_int0_en19;
+	ZXIC_UINT32 stat_int0_en18;
+	ZXIC_UINT32 stat_int0_en17;
+	ZXIC_UINT32 stat_int0_en16;
+	ZXIC_UINT32 stat_int0_en15;
+	ZXIC_UINT32 stat_int0_en14;
+	ZXIC_UINT32 stat_int0_en13;
+	ZXIC_UINT32 stat_int0_en12;
+	ZXIC_UINT32 stat_int0_en11;
+	ZXIC_UINT32 stat_int0_en10;
+	ZXIC_UINT32 stat_int0_en9;
+	ZXIC_UINT32 stat_int0_en8;
+	ZXIC_UINT32 stat_int0_en7;
+	ZXIC_UINT32 stat_int0_en6;
+	ZXIC_UINT32 stat_int0_en5;
+	ZXIC_UINT32 stat_int0_en4;
+	ZXIC_UINT32 stat_int0_en3;
+	ZXIC_UINT32 stat_int0_en2;
+	ZXIC_UINT32 stat_int0_en1;
+	ZXIC_UINT32 stat_int0_en0;
+} DPP_STAT_STAT_CFG_STAT_INT0_EN_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int0_mask_t {
+	ZXIC_UINT32 stat_int0_mask31;
+	ZXIC_UINT32 stat_int0_mask30;
+	ZXIC_UINT32 stat_int0_mask29;
+	ZXIC_UINT32 stat_int0_mask28;
+	ZXIC_UINT32 stat_int0_mask27;
+	ZXIC_UINT32 stat_int0_mask26;
+	ZXIC_UINT32 stat_int0_mask25;
+	ZXIC_UINT32 stat_int0_mask24;
+	ZXIC_UINT32 stat_int0_mask23;
+	ZXIC_UINT32 stat_int0_mask22;
+	ZXIC_UINT32 stat_int0_mask21;
+	ZXIC_UINT32 stat_int0_mask20;
+	ZXIC_UINT32 stat_int0_mask19;
+	ZXIC_UINT32 stat_int0_mask18;
+	ZXIC_UINT32 stat_int0_mask17;
+	ZXIC_UINT32 stat_int0_mask16;
+	ZXIC_UINT32 stat_int0_mask15;
+	ZXIC_UINT32 stat_int0_mask14;
+	ZXIC_UINT32 stat_int0_mask13;
+	ZXIC_UINT32 stat_int0_mask12;
+	ZXIC_UINT32 stat_int0_mask11;
+	ZXIC_UINT32 stat_int0_mask10;
+	ZXIC_UINT32 stat_int0_mask9;
+	ZXIC_UINT32 stat_int0_mask8;
+	ZXIC_UINT32 stat_int0_mask7;
+	ZXIC_UINT32 stat_int0_mask6;
+	ZXIC_UINT32 stat_int0_mask5;
+	ZXIC_UINT32 stat_int0_mask4;
+	ZXIC_UINT32 stat_int0_mask3;
+	ZXIC_UINT32 stat_int0_mask2;
+	ZXIC_UINT32 stat_int0_mask1;
+	ZXIC_UINT32 stat_int0_mask0;
+} DPP_STAT_STAT_CFG_STAT_INT0_MASK_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int0_status_t {
+	ZXIC_UINT32 stat_int0_status31;
+	ZXIC_UINT32 stat_int0_status30;
+	ZXIC_UINT32 stat_int0_status29;
+	ZXIC_UINT32 stat_int0_status28;
+	ZXIC_UINT32 stat_int0_status27;
+	ZXIC_UINT32 stat_int0_status26;
+	ZXIC_UINT32 stat_int0_status25;
+	ZXIC_UINT32 stat_int0_status24;
+	ZXIC_UINT32 stat_int0_status23;
+	ZXIC_UINT32 stat_int0_status22;
+	ZXIC_UINT32 stat_int0_status21;
+	ZXIC_UINT32 stat_int0_status20;
+	ZXIC_UINT32 stat_int0_status19;
+	ZXIC_UINT32 stat_int0_status18;
+	ZXIC_UINT32 stat_int0_status17;
+	ZXIC_UINT32 stat_int0_status16;
+	ZXIC_UINT32 stat_int0_status15;
+	ZXIC_UINT32 stat_int0_status14;
+	ZXIC_UINT32 stat_int0_status13;
+	ZXIC_UINT32 stat_int0_status12;
+	ZXIC_UINT32 stat_int0_status11;
+	ZXIC_UINT32 stat_int0_status10;
+	ZXIC_UINT32 stat_int0_status9;
+	ZXIC_UINT32 stat_int0_status8;
+	ZXIC_UINT32 stat_int0_status7;
+	ZXIC_UINT32 stat_int0_status6;
+	ZXIC_UINT32 stat_int0_status5;
+	ZXIC_UINT32 stat_int0_status4;
+	ZXIC_UINT32 stat_int0_status3;
+	ZXIC_UINT32 stat_int0_status2;
+	ZXIC_UINT32 stat_int0_status1;
+	ZXIC_UINT32 stat_int0_status0;
+} DPP_STAT_STAT_CFG_STAT_INT0_STATUS_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int1_en_t {
+	ZXIC_UINT32 stat_int1_en31;
+	ZXIC_UINT32 stat_int1_en30;
+	ZXIC_UINT32 stat_int1_en29;
+	ZXIC_UINT32 stat_int1_en28;
+	ZXIC_UINT32 stat_int1_en27;
+	ZXIC_UINT32 stat_int1_en26;
+	ZXIC_UINT32 stat_int1_en25;
+	ZXIC_UINT32 stat_int1_en24;
+	ZXIC_UINT32 stat_int1_en23;
+	ZXIC_UINT32 stat_int1_en22;
+	ZXIC_UINT32 stat_int1_en21;
+	ZXIC_UINT32 stat_int1_en20;
+	ZXIC_UINT32 stat_int1_en19;
+	ZXIC_UINT32 stat_int1_en18;
+	ZXIC_UINT32 stat_int1_en17;
+	ZXIC_UINT32 stat_int1_en16;
+	ZXIC_UINT32 stat_int1_en15;
+	ZXIC_UINT32 stat_int1_en14;
+	ZXIC_UINT32 stat_int1_en13;
+	ZXIC_UINT32 stat_int1_en12;
+	ZXIC_UINT32 stat_int1_en11;
+	ZXIC_UINT32 stat_int1_en10;
+	ZXIC_UINT32 stat_int1_en9;
+	ZXIC_UINT32 stat_int1_en8;
+	ZXIC_UINT32 stat_int1_en7;
+	ZXIC_UINT32 stat_int1_en6;
+	ZXIC_UINT32 stat_int1_en5;
+	ZXIC_UINT32 stat_int1_en4;
+	ZXIC_UINT32 stat_int1_en3;
+	ZXIC_UINT32 stat_int1_en2;
+	ZXIC_UINT32 stat_int1_en1;
+	ZXIC_UINT32 stat_int1_en0;
+} DPP_STAT_STAT_CFG_STAT_INT1_EN_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int1_mask_t {
+	ZXIC_UINT32 stat_int1_mask31;
+	ZXIC_UINT32 stat_int1_mask30;
+	ZXIC_UINT32 stat_int1_mask29;
+	ZXIC_UINT32 stat_int1_mask28;
+	ZXIC_UINT32 stat_int1_mask27;
+	ZXIC_UINT32 stat_int1_mask26;
+	ZXIC_UINT32 stat_int1_mask25;
+	ZXIC_UINT32 stat_int1_mask24;
+	ZXIC_UINT32 stat_int1_mask23;
+	ZXIC_UINT32 stat_int1_mask22;
+	ZXIC_UINT32 stat_int1_mask21;
+	ZXIC_UINT32 stat_int1_mask20;
+	ZXIC_UINT32 stat_int1_mask19;
+	ZXIC_UINT32 stat_int1_mask18;
+	ZXIC_UINT32 stat_int1_mask17;
+	ZXIC_UINT32 stat_int1_mask16;
+	ZXIC_UINT32 stat_int1_mask15;
+	ZXIC_UINT32 stat_int1_mask14;
+	ZXIC_UINT32 stat_int1_mask13;
+	ZXIC_UINT32 stat_int1_mask12;
+	ZXIC_UINT32 stat_int1_mask11;
+	ZXIC_UINT32 stat_int1_mask10;
+	ZXIC_UINT32 stat_int1_mask9;
+	ZXIC_UINT32 stat_int1_mask8;
+	ZXIC_UINT32 stat_int1_mask7;
+	ZXIC_UINT32 stat_int1_mask6;
+	ZXIC_UINT32 stat_int1_mask5;
+	ZXIC_UINT32 stat_int1_mask4;
+	ZXIC_UINT32 stat_int1_mask3;
+	ZXIC_UINT32 stat_int1_mask2;
+	ZXIC_UINT32 stat_int1_mask1;
+	ZXIC_UINT32 stat_int1_mask0;
+} DPP_STAT_STAT_CFG_STAT_INT1_MASK_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int1_status_t {
+	ZXIC_UINT32 stat_int1_status31;
+	ZXIC_UINT32 stat_int1_status30;
+	ZXIC_UINT32 stat_int1_status29;
+	ZXIC_UINT32 stat_int1_status28;
+	ZXIC_UINT32 stat_int1_status27;
+	ZXIC_UINT32 stat_int1_status26;
+	ZXIC_UINT32 stat_int1_status25;
+	ZXIC_UINT32 stat_int1_status24;
+	ZXIC_UINT32 stat_int1_status23;
+	ZXIC_UINT32 stat_int1_status22;
+	ZXIC_UINT32 stat_int1_status21;
+	ZXIC_UINT32 stat_int1_status20;
+	ZXIC_UINT32 stat_int1_status19;
+	ZXIC_UINT32 stat_int1_status18;
+	ZXIC_UINT32 stat_int1_status17;
+	ZXIC_UINT32 stat_int1_status16;
+	ZXIC_UINT32 stat_int1_status15;
+	ZXIC_UINT32 stat_int1_status14;
+	ZXIC_UINT32 stat_int1_status13;
+	ZXIC_UINT32 stat_int1_status12;
+	ZXIC_UINT32 stat_int1_status11;
+	ZXIC_UINT32 stat_int1_status10;
+	ZXIC_UINT32 stat_int1_status9;
+	ZXIC_UINT32 stat_int1_status8;
+	ZXIC_UINT32 stat_int1_status7;
+	ZXIC_UINT32 stat_int1_status6;
+	ZXIC_UINT32 stat_int1_status5;
+	ZXIC_UINT32 stat_int1_status4;
+	ZXIC_UINT32 stat_int1_status3;
+	ZXIC_UINT32 stat_int1_status2;
+	ZXIC_UINT32 stat_int1_status1;
+	ZXIC_UINT32 stat_int1_status0;
+} DPP_STAT_STAT_CFG_STAT_INT1_STATUS_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int2_en_t {
+	ZXIC_UINT32 stat_int2_en31;
+	ZXIC_UINT32 stat_int2_en30;
+	ZXIC_UINT32 stat_int2_en29;
+	ZXIC_UINT32 stat_int2_en28;
+	ZXIC_UINT32 stat_int2_en27;
+	ZXIC_UINT32 stat_int2_en26;
+	ZXIC_UINT32 stat_int2_en25;
+	ZXIC_UINT32 stat_int2_en24;
+	ZXIC_UINT32 stat_int2_en23;
+	ZXIC_UINT32 stat_int2_en22;
+	ZXIC_UINT32 stat_int2_en21;
+	ZXIC_UINT32 stat_int2_en20;
+	ZXIC_UINT32 stat_int2_en19;
+	ZXIC_UINT32 stat_int2_en18;
+	ZXIC_UINT32 stat_int2_en17;
+	ZXIC_UINT32 stat_int2_en16;
+	ZXIC_UINT32 stat_int2_en15;
+	ZXIC_UINT32 stat_int2_en14;
+	ZXIC_UINT32 stat_int2_en13;
+	ZXIC_UINT32 stat_int2_en12;
+	ZXIC_UINT32 stat_int2_en11;
+	ZXIC_UINT32 stat_int2_en10;
+	ZXIC_UINT32 stat_int2_en9;
+	ZXIC_UINT32 stat_int2_en8;
+	ZXIC_UINT32 stat_int2_en7;
+	ZXIC_UINT32 stat_int2_en6;
+	ZXIC_UINT32 stat_int2_en5;
+	ZXIC_UINT32 stat_int2_en4;
+	ZXIC_UINT32 stat_int2_en3;
+	ZXIC_UINT32 stat_int2_en2;
+	ZXIC_UINT32 stat_int2_en1;
+	ZXIC_UINT32 stat_int2_en0;
+} DPP_STAT_STAT_CFG_STAT_INT2_EN_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int2_mask_t {
+	ZXIC_UINT32 stat_int2_mask31;
+	ZXIC_UINT32 stat_int2_mask30;
+	ZXIC_UINT32 stat_int2_mask29;
+	ZXIC_UINT32 stat_int2_mask28;
+	ZXIC_UINT32 stat_int2_mask27;
+	ZXIC_UINT32 stat_int2_mask26;
+	ZXIC_UINT32 stat_int2_mask25;
+	ZXIC_UINT32 stat_int2_mask24;
+	ZXIC_UINT32 stat_int2_mask23;
+	ZXIC_UINT32 stat_int2_mask22;
+	ZXIC_UINT32 stat_int2_mask21;
+	ZXIC_UINT32 stat_int2_mask20;
+	ZXIC_UINT32 stat_int2_mask19;
+	ZXIC_UINT32 stat_int2_mask18;
+	ZXIC_UINT32 stat_int2_mask17;
+	ZXIC_UINT32 stat_int2_mask16;
+	ZXIC_UINT32 stat_int2_mask15;
+	ZXIC_UINT32 stat_int2_mask14;
+	ZXIC_UINT32 stat_int2_mask13;
+	ZXIC_UINT32 stat_int2_mask12;
+	ZXIC_UINT32 stat_int2_mask11;
+	ZXIC_UINT32 stat_int2_mask10;
+	ZXIC_UINT32 stat_int2_mask9;
+	ZXIC_UINT32 stat_int2_mask8;
+	ZXIC_UINT32 stat_int2_mask7;
+	ZXIC_UINT32 stat_int2_mask6;
+	ZXIC_UINT32 stat_int2_mask5;
+	ZXIC_UINT32 stat_int2_mask4;
+	ZXIC_UINT32 stat_int2_mask3;
+	ZXIC_UINT32 stat_int2_mask2;
+	ZXIC_UINT32 stat_int2_mask1;
+	ZXIC_UINT32 stat_int2_mask0;
+} DPP_STAT_STAT_CFG_STAT_INT2_MASK_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int2_status_t {
+	ZXIC_UINT32 stat_int2_status31;
+	ZXIC_UINT32 stat_int2_status30;
+	ZXIC_UINT32 stat_int2_status29;
+	ZXIC_UINT32 stat_int2_status28;
+	ZXIC_UINT32 stat_int2_status27;
+	ZXIC_UINT32 stat_int2_status26;
+	ZXIC_UINT32 stat_int2_status25;
+	ZXIC_UINT32 stat_int2_status24;
+	ZXIC_UINT32 stat_int2_status23;
+	ZXIC_UINT32 stat_int2_status22;
+	ZXIC_UINT32 stat_int2_status21;
+	ZXIC_UINT32 stat_int2_status20;
+	ZXIC_UINT32 stat_int2_status19;
+	ZXIC_UINT32 stat_int2_status18;
+	ZXIC_UINT32 stat_int2_status17;
+	ZXIC_UINT32 stat_int2_status16;
+	ZXIC_UINT32 stat_int2_status15;
+	ZXIC_UINT32 stat_int2_status14;
+	ZXIC_UINT32 stat_int2_status13;
+	ZXIC_UINT32 stat_int2_status12;
+	ZXIC_UINT32 stat_int2_status11;
+	ZXIC_UINT32 stat_int2_status10;
+	ZXIC_UINT32 stat_int2_status9;
+	ZXIC_UINT32 stat_int2_status8;
+	ZXIC_UINT32 stat_int2_status7;
+	ZXIC_UINT32 stat_int2_status6;
+	ZXIC_UINT32 stat_int2_status5;
+	ZXIC_UINT32 stat_int2_status4;
+	ZXIC_UINT32 stat_int2_status3;
+	ZXIC_UINT32 stat_int2_status2;
+	ZXIC_UINT32 stat_int2_status1;
+	ZXIC_UINT32 stat_int2_status0;
+} DPP_STAT_STAT_CFG_STAT_INT2_STATUS_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int3_en_t {
+	ZXIC_UINT32 stat_int3_en31;
+	ZXIC_UINT32 stat_int3_en30;
+	ZXIC_UINT32 stat_int3_en29;
+	ZXIC_UINT32 stat_int3_en28;
+	ZXIC_UINT32 stat_int3_en27;
+	ZXIC_UINT32 stat_int3_en26;
+	ZXIC_UINT32 stat_int3_en25;
+	ZXIC_UINT32 stat_int3_en24;
+	ZXIC_UINT32 stat_int3_en23;
+	ZXIC_UINT32 stat_int3_en22;
+	ZXIC_UINT32 stat_int3_en21;
+	ZXIC_UINT32 stat_int3_en20;
+	ZXIC_UINT32 stat_int3_en19;
+	ZXIC_UINT32 stat_int3_en18;
+	ZXIC_UINT32 stat_int3_en17;
+	ZXIC_UINT32 stat_int3_en16;
+	ZXIC_UINT32 stat_int3_en15;
+	ZXIC_UINT32 stat_int3_en14;
+	ZXIC_UINT32 stat_int3_en13;
+	ZXIC_UINT32 stat_int3_en12;
+	ZXIC_UINT32 stat_int3_en11;
+	ZXIC_UINT32 stat_int3_en10;
+	ZXIC_UINT32 stat_int3_en9;
+	ZXIC_UINT32 stat_int3_en8;
+	ZXIC_UINT32 stat_int3_en7;
+	ZXIC_UINT32 stat_int3_en6;
+	ZXIC_UINT32 stat_int3_en5;
+	ZXIC_UINT32 stat_int3_en4;
+	ZXIC_UINT32 stat_int3_en3;
+	ZXIC_UINT32 stat_int3_en2;
+	ZXIC_UINT32 stat_int3_en1;
+	ZXIC_UINT32 stat_int3_en0;
+} DPP_STAT_STAT_CFG_STAT_INT3_EN_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int3_mask_t {
+	ZXIC_UINT32 stat_int3_mask31;
+	ZXIC_UINT32 stat_int3_mask30;
+	ZXIC_UINT32 stat_int3_mask29;
+	ZXIC_UINT32 stat_int3_mask28;
+	ZXIC_UINT32 stat_int3_mask27;
+	ZXIC_UINT32 stat_int3_mask26;
+	ZXIC_UINT32 stat_int3_mask25;
+	ZXIC_UINT32 stat_int3_mask24;
+	ZXIC_UINT32 stat_int3_mask23;
+	ZXIC_UINT32 stat_int3_mask22;
+	ZXIC_UINT32 stat_int3_mask21;
+	ZXIC_UINT32 stat_int3_mask20;
+	ZXIC_UINT32 stat_int3_mask19;
+	ZXIC_UINT32 stat_int3_mask18;
+	ZXIC_UINT32 stat_int3_mask17;
+	ZXIC_UINT32 stat_int3_mask16;
+	ZXIC_UINT32 stat_int3_mask15;
+	ZXIC_UINT32 stat_int3_mask14;
+	ZXIC_UINT32 stat_int3_mask13;
+	ZXIC_UINT32 stat_int3_mask12;
+	ZXIC_UINT32 stat_int3_mask11;
+	ZXIC_UINT32 stat_int3_mask10;
+	ZXIC_UINT32 stat_int3_mask9;
+	ZXIC_UINT32 stat_int3_mask8;
+	ZXIC_UINT32 stat_int3_mask7;
+	ZXIC_UINT32 stat_int3_mask6;
+	ZXIC_UINT32 stat_int3_mask5;
+	ZXIC_UINT32 stat_int3_mask4;
+	ZXIC_UINT32 stat_int3_mask3;
+	ZXIC_UINT32 stat_int3_mask2;
+	ZXIC_UINT32 stat_int3_mask1;
+	ZXIC_UINT32 stat_int3_mask0;
+} DPP_STAT_STAT_CFG_STAT_INT3_MASK_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int3_status_t {
+	ZXIC_UINT32 stat_int3_status31;
+	ZXIC_UINT32 stat_int3_status30;
+	ZXIC_UINT32 stat_int3_status29;
+	ZXIC_UINT32 stat_int3_status28;
+	ZXIC_UINT32 stat_int3_status27;
+	ZXIC_UINT32 stat_int3_status26;
+	ZXIC_UINT32 stat_int3_status25;
+	ZXIC_UINT32 stat_int3_status24;
+	ZXIC_UINT32 stat_int3_status23;
+	ZXIC_UINT32 stat_int3_status22;
+	ZXIC_UINT32 stat_int3_status21;
+	ZXIC_UINT32 stat_int3_status20;
+	ZXIC_UINT32 stat_int3_status19;
+	ZXIC_UINT32 stat_int3_status18;
+	ZXIC_UINT32 stat_int3_status17;
+	ZXIC_UINT32 stat_int3_status16;
+	ZXIC_UINT32 stat_int3_status15;
+	ZXIC_UINT32 stat_int3_status14;
+	ZXIC_UINT32 stat_int3_status13;
+	ZXIC_UINT32 stat_int3_status12;
+	ZXIC_UINT32 stat_int3_status11;
+	ZXIC_UINT32 stat_int3_status10;
+	ZXIC_UINT32 stat_int3_status9;
+	ZXIC_UINT32 stat_int3_status8;
+	ZXIC_UINT32 stat_int3_status7;
+	ZXIC_UINT32 stat_int3_status6;
+	ZXIC_UINT32 stat_int3_status5;
+	ZXIC_UINT32 stat_int3_status4;
+	ZXIC_UINT32 stat_int3_status3;
+	ZXIC_UINT32 stat_int3_status2;
+	ZXIC_UINT32 stat_int3_status1;
+	ZXIC_UINT32 stat_int3_status0;
+} DPP_STAT_STAT_CFG_STAT_INT3_STATUS_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int4_en_t {
+	ZXIC_UINT32 stat_int4_en_18;
+	ZXIC_UINT32 stat_int4_en_17;
+	ZXIC_UINT32 stat_int4_en_16;
+	ZXIC_UINT32 stat_int4_en_15;
+	ZXIC_UINT32 stat_int4_en_14;
+	ZXIC_UINT32 stat_int4_en_13;
+	ZXIC_UINT32 stat_int4_en_12;
+	ZXIC_UINT32 stat_int4_en_11;
+	ZXIC_UINT32 stat_int4_en_10;
+	ZXIC_UINT32 stat_int4_en_9;
+	ZXIC_UINT32 stat_int4_en_8;
+	ZXIC_UINT32 stat_int4_en_7;
+	ZXIC_UINT32 stat_int4_en_6;
+	ZXIC_UINT32 stat_int4_en_5;
+	ZXIC_UINT32 stat_int4_en_4;
+	ZXIC_UINT32 stat_int4_en_3;
+	ZXIC_UINT32 stat_int4_en_2;
+	ZXIC_UINT32 stat_int4_en_1;
+	ZXIC_UINT32 stat_int4_en_0;
+} DPP_STAT_STAT_CFG_STAT_INT4_EN_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int4_mask_t {
+	ZXIC_UINT32 stat_int4_mask_18;
+	ZXIC_UINT32 stat_int4_mask_17;
+	ZXIC_UINT32 stat_int4_mask_16;
+	ZXIC_UINT32 stat_int4_mask_15;
+	ZXIC_UINT32 stat_int4_mask_14;
+	ZXIC_UINT32 stat_int4_mask_13;
+	ZXIC_UINT32 stat_int4_mask_12;
+	ZXIC_UINT32 stat_int4_mask_11;
+	ZXIC_UINT32 stat_int4_mask_10;
+	ZXIC_UINT32 stat_int4_mask_9;
+	ZXIC_UINT32 stat_int4_mask_8;
+	ZXIC_UINT32 stat_int4_mask_7;
+	ZXIC_UINT32 stat_int4_mask_6;
+	ZXIC_UINT32 stat_int4_mask_5;
+	ZXIC_UINT32 stat_int4_mask_4;
+	ZXIC_UINT32 stat_int4_mask_3;
+	ZXIC_UINT32 stat_int4_mask_2;
+	ZXIC_UINT32 stat_int4_mask_1;
+	ZXIC_UINT32 stat_int4_mask_0;
+} DPP_STAT_STAT_CFG_STAT_INT4_MASK_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int4_status_t {
+	ZXIC_UINT32 stat_int4_mask_18;
+	ZXIC_UINT32 stat_int4_mask_17;
+	ZXIC_UINT32 stat_int4_mask_16;
+	ZXIC_UINT32 stat_int4_mask_15;
+	ZXIC_UINT32 stat_int4_mask_14;
+	ZXIC_UINT32 stat_int4_mask_13;
+	ZXIC_UINT32 stat_int4_mask_12;
+	ZXIC_UINT32 stat_int4_mask_11;
+	ZXIC_UINT32 stat_int4_mask_10;
+	ZXIC_UINT32 stat_int4_mask_9;
+	ZXIC_UINT32 stat_int4_mask_8;
+	ZXIC_UINT32 stat_int4_mask_7;
+	ZXIC_UINT32 stat_int4_mask_6;
+	ZXIC_UINT32 stat_int4_mask_5;
+	ZXIC_UINT32 stat_int4_mask_4;
+	ZXIC_UINT32 stat_int4_mask_3;
+	ZXIC_UINT32 stat_int4_mask_2;
+	ZXIC_UINT32 stat_int4_mask_1;
+	ZXIC_UINT32 stat_int4_mask_0;
+} DPP_STAT_STAT_CFG_STAT_INT4_STATUS_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int5_en_t {
+	ZXIC_UINT32 stat_int5_en_18;
+	ZXIC_UINT32 stat_int5_en_17;
+	ZXIC_UINT32 stat_int5_en_16;
+	ZXIC_UINT32 stat_int5_en_15;
+	ZXIC_UINT32 stat_int5_en_14;
+	ZXIC_UINT32 stat_int5_en_13;
+	ZXIC_UINT32 stat_int5_en_12;
+	ZXIC_UINT32 stat_int5_en_11;
+	ZXIC_UINT32 stat_int5_en_10;
+	ZXIC_UINT32 stat_int5_en_9;
+	ZXIC_UINT32 stat_int5_en_8;
+	ZXIC_UINT32 stat_int5_en_7;
+	ZXIC_UINT32 stat_int5_en_6;
+	ZXIC_UINT32 stat_int5_en_5;
+	ZXIC_UINT32 stat_int5_en_4;
+	ZXIC_UINT32 stat_int5_en_3;
+	ZXIC_UINT32 stat_int5_en_2;
+	ZXIC_UINT32 stat_int5_en_1;
+	ZXIC_UINT32 stat_int5_en_0;
+} DPP_STAT_STAT_CFG_STAT_INT5_EN_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int5_mask_t {
+	ZXIC_UINT32 stat_int5_mask_18;
+	ZXIC_UINT32 stat_int5_mask_17;
+	ZXIC_UINT32 stat_int5_mask_16;
+	ZXIC_UINT32 stat_int5_mask_15;
+	ZXIC_UINT32 stat_int5_mask_14;
+	ZXIC_UINT32 stat_int5_mask_13;
+	ZXIC_UINT32 stat_int5_mask_12;
+	ZXIC_UINT32 stat_int5_mask_11;
+	ZXIC_UINT32 stat_int5_mask_10;
+	ZXIC_UINT32 stat_int5_mask_9;
+	ZXIC_UINT32 stat_int5_mask_8;
+	ZXIC_UINT32 stat_int5_mask_7;
+	ZXIC_UINT32 stat_int5_mask_6;
+	ZXIC_UINT32 stat_int5_mask_5;
+	ZXIC_UINT32 stat_int5_mask_4;
+	ZXIC_UINT32 stat_int5_mask_3;
+	ZXIC_UINT32 stat_int5_mask_2;
+	ZXIC_UINT32 stat_int5_mask_1;
+	ZXIC_UINT32 stat_int5_mask_0;
+} DPP_STAT_STAT_CFG_STAT_INT5_MASK_T;
+
+typedef struct dpp_stat_stat_cfg_stat_int5_status_t {
+	ZXIC_UINT32 stat_int5_mask_18;
+	ZXIC_UINT32 stat_int5_mask_17;
+	ZXIC_UINT32 stat_int5_mask_16;
+	ZXIC_UINT32 stat_int5_mask_15;
+	ZXIC_UINT32 stat_int5_mask_14;
+	ZXIC_UINT32 stat_int5_mask_13;
+	ZXIC_UINT32 stat_int5_mask_12;
+	ZXIC_UINT32 stat_int5_mask_11;
+	ZXIC_UINT32 stat_int5_mask_10;
+	ZXIC_UINT32 stat_int5_mask_9;
+	ZXIC_UINT32 stat_int5_mask_8;
+	ZXIC_UINT32 stat_int5_mask_7;
+	ZXIC_UINT32 stat_int5_mask_6;
+	ZXIC_UINT32 stat_int5_mask_5;
+	ZXIC_UINT32 stat_int5_mask_4;
+	ZXIC_UINT32 stat_int5_mask_3;
+	ZXIC_UINT32 stat_int5_mask_2;
+	ZXIC_UINT32 stat_int5_mask_1;
+	ZXIC_UINT32 stat_int5_mask_0;
+} DPP_STAT_STAT_CFG_STAT_INT5_STATUS_T;
+
+typedef struct dpp_stat_stat_cfg_rschd_ecc_bypass_t {
+	ZXIC_UINT32 rschd_ecc_bypass_18;
+	ZXIC_UINT32 rschd_ecc_bypass_17;
+	ZXIC_UINT32 rschd_ecc_bypass_16;
+	ZXIC_UINT32 rschd_ecc_bypass_15;
+	ZXIC_UINT32 rschd_ecc_bypass_14;
+	ZXIC_UINT32 rschd_ecc_bypass_13;
+	ZXIC_UINT32 rschd_ecc_bypass_12;
+	ZXIC_UINT32 rschd_ecc_bypass_11;
+	ZXIC_UINT32 rschd_ecc_bypass_10;
+	ZXIC_UINT32 rschd_ecc_bypass_9;
+	ZXIC_UINT32 rschd_ecc_bypass_8;
+	ZXIC_UINT32 rschd_ecc_bypass_7;
+	ZXIC_UINT32 rschd_ecc_bypass_6;
+	ZXIC_UINT32 rschd_ecc_bypass_5;
+	ZXIC_UINT32 rschd_ecc_bypass_4;
+	ZXIC_UINT32 rschd_ecc_bypass_3;
+	ZXIC_UINT32 rschd_ecc_bypass_2;
+	ZXIC_UINT32 rschd_ecc_bypass_1;
+	ZXIC_UINT32 rschd_ecc_bypass_0;
+} DPP_STAT_STAT_CFG_RSCHD_ECC_BYPASS_T;
+
+typedef struct dpp_stat_stat_cfg_rschd_ecc_single_err_t {
+	ZXIC_UINT32 rschd_ecc_single_err_18;
+	ZXIC_UINT32 rschd_ecc_single_err_17;
+	ZXIC_UINT32 rschd_ecc_single_err_16;
+	ZXIC_UINT32 rschd_ecc_single_err_15;
+	ZXIC_UINT32 rschd_ecc_single_err_14;
+	ZXIC_UINT32 rschd_ecc_single_err_13;
+	ZXIC_UINT32 rschd_ecc_single_err_12;
+	ZXIC_UINT32 rschd_ecc_single_err_11;
+	ZXIC_UINT32 rschd_ecc_single_err_10;
+	ZXIC_UINT32 rschd_ecc_single_err_9;
+	ZXIC_UINT32 rschd_ecc_single_err_8;
+	ZXIC_UINT32 rschd_ecc_single_err_7;
+	ZXIC_UINT32 rschd_ecc_single_err_6;
+	ZXIC_UINT32 rschd_ecc_single_err_5;
+	ZXIC_UINT32 rschd_ecc_single_err_4;
+	ZXIC_UINT32 rschd_ecc_single_err_3;
+	ZXIC_UINT32 rschd_ecc_single_err_2;
+	ZXIC_UINT32 rschd_ecc_single_err_1;
+	ZXIC_UINT32 rschd_ecc_single_err_0;
+} DPP_STAT_STAT_CFG_RSCHD_ECC_SINGLE_ERR_T;
+
+typedef struct dpp_stat_stat_cfg_rschd_ecc_double_err_t {
+	ZXIC_UINT32 rschd_ecc_double_err_18;
+	ZXIC_UINT32 rschd_ecc_double_err_17;
+	ZXIC_UINT32 rschd_ecc_double_err_16;
+	ZXIC_UINT32 rschd_ecc_double_err_15;
+	ZXIC_UINT32 rschd_ecc_double_err_14;
+	ZXIC_UINT32 rschd_ecc_double_err_13;
+	ZXIC_UINT32 rschd_ecc_double_err_12;
+	ZXIC_UINT32 rschd_ecc_double_err_11;
+	ZXIC_UINT32 rschd_ecc_double_err_10;
+	ZXIC_UINT32 rschd_ecc_double_err_9;
+	ZXIC_UINT32 rschd_ecc_double_err_8;
+	ZXIC_UINT32 rschd_ecc_double_err_7;
+	ZXIC_UINT32 rschd_ecc_double_err_6;
+	ZXIC_UINT32 rschd_ecc_double_err_5;
+	ZXIC_UINT32 rschd_ecc_double_err_4;
+	ZXIC_UINT32 rschd_ecc_double_err_3;
+	ZXIC_UINT32 rschd_ecc_double_err_2;
+	ZXIC_UINT32 rschd_ecc_double_err_1;
+	ZXIC_UINT32 rschd_ecc_double_err_0;
+} DPP_STAT_STAT_CFG_RSCHD_ECC_DOUBLE_ERR_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat0_t {
+	ZXIC_UINT32 cpu_ind_ddr_wdat0;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT0_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat1_t {
+	ZXIC_UINT32 cpu_ind_ddr_wdat1;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT1_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat2_t {
+	ZXIC_UINT32 cpu_ind_ddr_wdat2;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT2_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat3_t {
+	ZXIC_UINT32 cpu_ind_ddr_wdat3;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT3_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat4_t {
+	ZXIC_UINT32 cpu_ind_ddr_wdat4;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT4_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat5_t {
+	ZXIC_UINT32 cpu_ind_ddr_wdat5;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT5_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat6_t {
+	ZXIC_UINT32 cpu_ind_ddr_wdat6;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT6_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat7_t {
+	ZXIC_UINT32 cpu_ind_ddr_wdat7;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT7_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat8_t {
+	ZXIC_UINT32 cpu_ind_ddr_wdat8;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT8_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat9_t {
+	ZXIC_UINT32 cpu_ind_ddr_wdat9;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT9_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat10_t {
+	ZXIC_UINT32 cpu_ind_ddr_wdat10;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT10_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat11_t {
+	ZXIC_UINT32 cpu_ind_ddr_wdat11;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT11_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat12_t {
+	ZXIC_UINT32 cpu_ind_ddr_wdat12;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT12_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat13_t {
+	ZXIC_UINT32 cpu_ind_ddr_wdat13;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT13_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat14_t {
+	ZXIC_UINT32 cpu_ind_ddr_wdat14;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT14_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_wdat15_t {
+	ZXIC_UINT32 cpu_ind_ddr_wdat15;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_WDAT15_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_req_info_t {
+	ZXIC_UINT32 rw_mode;
+	ZXIC_UINT32 read_mode;
+	ZXIC_UINT32 tm_cs;
+	ZXIC_UINT32 rw_addr;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_REQ_INFO_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rd_done_t {
+	ZXIC_UINT32 cpu_ind_ddr_rd_done;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RD_DONE_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat0_t {
+	ZXIC_UINT32 cpu_ind_ddr_rdat0;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT0_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat1_t {
+	ZXIC_UINT32 cpu_ind_ddr_rdat1;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT1_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat2_t {
+	ZXIC_UINT32 cpu_ind_ddr_rdat2;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT2_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat3_t {
+	ZXIC_UINT32 cpu_ind_ddr_rdat3;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT3_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat4_t {
+	ZXIC_UINT32 cpu_ind_ddr_rdat4;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT4_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat5_t {
+	ZXIC_UINT32 cpu_ind_ddr_rdat5;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT5_T;
 
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat6_t {
+	ZXIC_UINT32 cpu_ind_ddr_rdat6;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT6_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat7_t {
+	ZXIC_UINT32 cpu_ind_ddr_rdat7;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT7_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat8_t {
+	ZXIC_UINT32 cpu_ind_ddr_rdat8;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT8_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat9_t {
+	ZXIC_UINT32 cpu_ind_ddr_rdat9;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT9_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat10_t {
+	ZXIC_UINT32 cpu_ind_ddr_rdat10;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT10_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat11_t {
+	ZXIC_UINT32 cpu_ind_ddr_rdat11;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT11_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat12_t {
+	ZXIC_UINT32 cpu_ind_ddr_rdat12;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT12_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat13_t {
+	ZXIC_UINT32 cpu_ind_ddr_rdat13;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT13_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat14_t {
+	ZXIC_UINT32 cpu_ind_ddr_rdat14;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT14_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_ind_ddr_rdat15_t {
+	ZXIC_UINT32 cpu_ind_ddr_rdat15;
+} DPP_STAT_STAT_CFG_CPU_IND_DDR_RDAT15_T;
+
+typedef struct dpp_stat_stat_cfg_tm_alu_ddr_cpu_rdy_t {
+	ZXIC_UINT32 tm_alu_ddr_cpu_rdy;
+} DPP_STAT_STAT_CFG_TM_ALU_DDR_CPU_RDY_T;
+
+typedef struct dpp_stat_stat_cfg_ept_flag_t {
+	ZXIC_UINT32 ept_flag;
+} DPP_STAT_STAT_CFG_EPT_FLAG_T;
+
+typedef struct dpp_stat_stat_cfg_ppu_soft_rst_t {
+	ZXIC_UINT32 ppu_soft_rst;
+} DPP_STAT_STAT_CFG_PPU_SOFT_RST_T;
+
+typedef struct dpp_stat_stat_cfg_stat_smmu0_fc15_0_cnt_t {
+	ZXIC_UINT32 stat_smmu0_fc15_0_cnt;
+} DPP_STAT_STAT_CFG_STAT_SMMU0_FC15_0_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_smmu0_stat_fc15_0_cnt_t {
+	ZXIC_UINT32 smmu0_stat_fc15_0_cnt;
+} DPP_STAT_STAT_CFG_SMMU0_STAT_FC15_0_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_smmu0_stat_rsp15_0_cnt_t {
+	ZXIC_UINT32 smmu0_stat_rsp15_0_cnt;
+} DPP_STAT_STAT_CFG_SMMU0_STAT_RSP15_0_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_stat_smmu0_req15_0_cnt_t {
+	ZXIC_UINT32 stat_smmu0_req15_0_cnt;
+} DPP_STAT_STAT_CFG_STAT_SMMU0_REQ15_0_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_ppu_stat_mec5_0_rsp_fc_cnt_t {
+	ZXIC_UINT32 ppu_stat_mec5_0_rsp_fc_cnt;
+} DPP_STAT_STAT_CFG_PPU_STAT_MEC5_0_RSP_FC_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_stat_ppu_mec5_0_key_fc_cnt_t {
+	ZXIC_UINT32 stat_ppu_mec5_0_key_fc_cnt;
+} DPP_STAT_STAT_CFG_STAT_PPU_MEC5_0_KEY_FC_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_stat_ppu_mec5_0_rsp_cnt_t {
+	ZXIC_UINT32 stat_ppu_mec5_0_rsp_cnt;
+} DPP_STAT_STAT_CFG_STAT_PPU_MEC5_0_RSP_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_ppu_stat_mec5_0_key_cnt_t {
+	ZXIC_UINT32 ppu_stat_mec5_0_key_cnt;
+} DPP_STAT_STAT_CFG_PPU_STAT_MEC5_0_KEY_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_ppu5_0_no_exist_opcd_ex_cnt_t {
+	ZXIC_UINT32 ppu5_0_no_exist_opcd_ex_cnt;
+} DPP_STAT_STAT_CFG_PPU5_0_NO_EXIST_OPCD_EX_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_se_etm_stat_wr_fc_cnt_t {
+	ZXIC_UINT32 se_etm_stat_wr_fc_cnt;
+} DPP_STAT_STAT_CFG_SE_ETM_STAT_WR_FC_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_se_etm_stat_rd_fc_cnt_t {
+	ZXIC_UINT32 se_etm_stat_rd_fc_cnt;
+} DPP_STAT_STAT_CFG_SE_ETM_STAT_RD_FC_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_stat_etm_deq_fc_cnt_t {
+	ZXIC_UINT32 stat_etm_deq_fc_cnt;
+} DPP_STAT_STAT_CFG_STAT_ETM_DEQ_FC_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_stat_etm_enq_fc_cnt_t {
+	ZXIC_UINT32 stat_etm_enq_fc_cnt;
+} DPP_STAT_STAT_CFG_STAT_ETM_ENQ_FC_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_stat_oam_lm_fc_cnt_t {
+	ZXIC_UINT32 stat_oam_lm_fc_cnt;
+} DPP_STAT_STAT_CFG_STAT_OAM_LM_FC_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_oam_stat_lm_fc_cnt_t {
+	ZXIC_UINT32 oam_stat_lm_fc_cnt;
+} DPP_STAT_STAT_CFG_OAM_STAT_LM_FC_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_stat_oam_fc_cnt_t {
+	ZXIC_UINT32 stat_oam_fc_cnt;
+} DPP_STAT_STAT_CFG_STAT_OAM_FC_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_cmmu_stat_fc_cnt_t {
+	ZXIC_UINT32 cmmu_stat_fc_cnt;
+} DPP_STAT_STAT_CFG_CMMU_STAT_FC_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_stat_cmmu_req_cnt_t {
+	ZXIC_UINT32 stat_cmmu_req_cnt;
+} DPP_STAT_STAT_CFG_STAT_CMMU_REQ_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_smmu0_plcr_rsp0_cnt_t {
+	ZXIC_UINT32 smmu0_plcr_rsp0_cnt;
+} DPP_STAT_STAT_CFG_SMMU0_PLCR_RSP0_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_plcr_smmu0_req0_cnt_t {
+	ZXIC_UINT32 plcr_smmu0_req0_cnt;
+} DPP_STAT_STAT_CFG_PLCR_SMMU0_REQ0_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_stat_oam_lm_rsp_cnt_t {
+	ZXIC_UINT32 stat_oam_lm_rsp_cnt;
+} DPP_STAT_STAT_CFG_STAT_OAM_LM_RSP_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_oam_stat_lm_req_cnt_t {
+	ZXIC_UINT32 oam_stat_lm_req_cnt;
+} DPP_STAT_STAT_CFG_OAM_STAT_LM_REQ_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_oam_stat_req_cnt_t {
+	ZXIC_UINT32 oam_stat_req_cnt;
+} DPP_STAT_STAT_CFG_OAM_STAT_REQ_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_se_etm_stat_rsp_cnt_t {
+	ZXIC_UINT32 se_etm_stat_rsp_cnt;
+} DPP_STAT_STAT_CFG_SE_ETM_STAT_RSP_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_etm_stat_se_wr_req_cnt_t {
+	ZXIC_UINT32 etm_stat_se_wr_req_cnt;
+} DPP_STAT_STAT_CFG_ETM_STAT_SE_WR_REQ_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_etm_stat_se_rd_req_cnt_t {
+	ZXIC_UINT32 etm_stat_se_rd_req_cnt;
+} DPP_STAT_STAT_CFG_ETM_STAT_SE_RD_REQ_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_etm_stat_smmu0_req_cnt0_t {
+	ZXIC_UINT32 etm_stat_smmu0_req_cnt0;
+} DPP_STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT0_T;
+
+typedef struct dpp_stat_stat_cfg_etm_stat_smmu0_req_cnt1_t {
+	ZXIC_UINT32 etm_stat_smmu0_req_cnt1;
+} DPP_STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT1_T;
+
+typedef struct dpp_stat_stat_cfg_tm_stat_eram_cpu_rsp_cnt_t {
+	ZXIC_UINT32 tm_stat_eram_cpu_rsp_cnt;
+} DPP_STAT_STAT_CFG_TM_STAT_ERAM_CPU_RSP_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_rd_eram_req_cnt_t {
+	ZXIC_UINT32 cpu_rd_eram_req_cnt;
+} DPP_STAT_STAT_CFG_CPU_RD_ERAM_REQ_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_wr_eram_req_cnt_t {
+	ZXIC_UINT32 cpu_wr_eram_req_cnt;
+} DPP_STAT_STAT_CFG_CPU_WR_ERAM_REQ_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_tm_stat_ddr_cpu_rsp_cnt_t {
+	ZXIC_UINT32 tm_stat_ddr_cpu_rsp_cnt;
+} DPP_STAT_STAT_CFG_TM_STAT_DDR_CPU_RSP_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_rd_ddr_req_cnt_t {
+	ZXIC_UINT32 cpu_rd_ddr_req_cnt;
+} DPP_STAT_STAT_CFG_CPU_RD_DDR_REQ_CNT_T;
+
+typedef struct dpp_stat_stat_cfg_cpu_wr_ddr_req_cnt_t {
+	ZXIC_UINT32 cpu_wr_ddr_req_cnt;
+} DPP_STAT_STAT_CFG_CPU_WR_DDR_REQ_CNT_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat1_t {
+	ZXIC_UINT32 wdat1;
+} DPP_STAT_ETCAM_CPU_IND_WDAT1_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat2_t {
+	ZXIC_UINT32 wdat2;
+} DPP_STAT_ETCAM_CPU_IND_WDAT2_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat3_t {
+	ZXIC_UINT32 wdat3;
+} DPP_STAT_ETCAM_CPU_IND_WDAT3_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat4_t {
+	ZXIC_UINT32 wdat4;
+} DPP_STAT_ETCAM_CPU_IND_WDAT4_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat5_t {
+	ZXIC_UINT32 wdat5;
+} DPP_STAT_ETCAM_CPU_IND_WDAT5_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat6_t {
+	ZXIC_UINT32 wdat6;
+} DPP_STAT_ETCAM_CPU_IND_WDAT6_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat7_t {
+	ZXIC_UINT32 wdat7;
+} DPP_STAT_ETCAM_CPU_IND_WDAT7_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat8_t {
+	ZXIC_UINT32 wdat8;
+} DPP_STAT_ETCAM_CPU_IND_WDAT8_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat9_t {
+	ZXIC_UINT32 wdat9;
+} DPP_STAT_ETCAM_CPU_IND_WDAT9_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat10_t {
+	ZXIC_UINT32 wdat10;
+} DPP_STAT_ETCAM_CPU_IND_WDAT10_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat11_t {
+	ZXIC_UINT32 wdat11;
+} DPP_STAT_ETCAM_CPU_IND_WDAT11_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat12_t {
+	ZXIC_UINT32 wdat12;
+} DPP_STAT_ETCAM_CPU_IND_WDAT12_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat13_t {
+	ZXIC_UINT32 wdat13;
+} DPP_STAT_ETCAM_CPU_IND_WDAT13_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat14_t {
+	ZXIC_UINT32 wdat14;
+} DPP_STAT_ETCAM_CPU_IND_WDAT14_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat15_t {
+	ZXIC_UINT32 wdat15;
+} DPP_STAT_ETCAM_CPU_IND_WDAT15_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat16_t {
+	ZXIC_UINT32 wdat16;
+} DPP_STAT_ETCAM_CPU_IND_WDAT16_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat17_t {
+	ZXIC_UINT32 wdat17;
+} DPP_STAT_ETCAM_CPU_IND_WDAT17_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat18_t {
+	ZXIC_UINT32 wdat18;
+} DPP_STAT_ETCAM_CPU_IND_WDAT18_T;
+
+typedef struct dpp_stat_etcam_cpu_ind_wdat19_t {
+	ZXIC_UINT32 wdat19;
+} DPP_STAT_ETCAM_CPU_IND_WDAT19_T;
+
+typedef struct dpp_stat_etcam_t_strwc_cfg_t {
+	ZXIC_UINT32 t_strwc_cfg;
+} DPP_STAT_ETCAM_T_STRWC_CFG_T;
+
+typedef struct dpp_stat_etcam_etcam_int_unmask_flag_t {
+	ZXIC_UINT32 etcam_int_unmask_flag;
+} DPP_STAT_ETCAM_ETCAM_INT_UNMASK_FLAG_T;
+
+typedef struct dpp_stat_etcam_etcam_int_en0_t {
+	ZXIC_UINT32 etcam_int_en17;
+	ZXIC_UINT32 etcam_int_en16;
+	ZXIC_UINT32 etcam_int_en15;
+	ZXIC_UINT32 etcam_int_en14;
+	ZXIC_UINT32 etcam_int_en13;
+	ZXIC_UINT32 etcam_int_en12;
+	ZXIC_UINT32 etcam_int_en11;
+	ZXIC_UINT32 etcam_int_en10;
+	ZXIC_UINT32 etcam_int_en9;
+	ZXIC_UINT32 etcam_int_en8;
+	ZXIC_UINT32 etcam_int_en7;
+	ZXIC_UINT32 etcam_int_en6;
+	ZXIC_UINT32 etcam_int_en5;
+	ZXIC_UINT32 etcam_int_en4;
+	ZXIC_UINT32 etcam_int_en3;
+	ZXIC_UINT32 etcam_int_en2;
+	ZXIC_UINT32 etcam_int_en1;
+	ZXIC_UINT32 etcam_int_en0;
+} DPP_STAT_ETCAM_ETCAM_INT_EN0_T;
+
+typedef struct dpp_stat_etcam_etcam_int_mask0_t {
+	ZXIC_UINT32 etcam_int_mask17;
+	ZXIC_UINT32 etcam_int_mask16;
+	ZXIC_UINT32 etcam_int_mask15;
+	ZXIC_UINT32 etcam_int_mask14;
+	ZXIC_UINT32 etcam_int_mask13;
+	ZXIC_UINT32 etcam_int_mask12;
+	ZXIC_UINT32 etcam_int_mask11;
+	ZXIC_UINT32 etcam_int_mask10;
+	ZXIC_UINT32 etcam_int_mask9;
+	ZXIC_UINT32 etcam_int_mask8;
+	ZXIC_UINT32 etcam_int_mask7;
+	ZXIC_UINT32 etcam_int_mask6;
+	ZXIC_UINT32 etcam_int_mask5;
+	ZXIC_UINT32 etcam_int_mask4;
+	ZXIC_UINT32 etcam_int_mask3;
+	ZXIC_UINT32 etcam_int_mask2;
+	ZXIC_UINT32 etcam_int_mask1;
+	ZXIC_UINT32 etcam_int_mask0;
+} DPP_STAT_ETCAM_ETCAM_INT_MASK0_T;
+
+typedef struct dpp_stat_etcam_etcam_int_status_t {
+	ZXIC_UINT32 etcam_int_status17;
+	ZXIC_UINT32 etcam_int_status16;
+	ZXIC_UINT32 etcam_int_status15;
+	ZXIC_UINT32 etcam_int_status14;
+	ZXIC_UINT32 etcam_int_status13;
+	ZXIC_UINT32 etcam_int_status12;
+	ZXIC_UINT32 etcam_int_status11;
+	ZXIC_UINT32 etcam_int_status10;
+	ZXIC_UINT32 etcam_int_status9;
+	ZXIC_UINT32 etcam_int_status8;
+	ZXIC_UINT32 etcam_int_status7;
+	ZXIC_UINT32 etcam_int_status6;
+	ZXIC_UINT32 etcam_int_status5;
+	ZXIC_UINT32 etcam_int_status4;
+	ZXIC_UINT32 etcam_int_status3;
+	ZXIC_UINT32 etcam_int_status2;
+	ZXIC_UINT32 etcam_int_status1;
+	ZXIC_UINT32 etcam_int_status0;
+} DPP_STAT_ETCAM_ETCAM_INT_STATUS_T;
+
+typedef struct dpp_stat_etcam_int_tb_ini_ok_t {
+	ZXIC_UINT32 int_tb_ini_ok;
+} DPP_STAT_ETCAM_INT_TB_INI_OK_T;
+
+typedef struct dpp_stat_etcam_etcam_clk_en_t {
+	ZXIC_UINT32 etcam_clk_en;
+} DPP_STAT_ETCAM_ETCAM_CLK_EN_T;
+
+typedef struct dpp_stat_etcam_as_etcam_req0_cnt_t {
+	ZXIC_UINT32 as_etcam_req0_cnt;
+} DPP_STAT_ETCAM_AS_ETCAM_REQ0_CNT_T;
+
+typedef struct dpp_stat_etcam_as_etcam_req1_cnt_t {
+	ZXIC_UINT32 as_etcam_req1_cnt;
+} DPP_STAT_ETCAM_AS_ETCAM_REQ1_CNT_T;
+
+typedef struct dpp_stat_etcam_etcam_as_index0_cnt_t {
+	ZXIC_UINT32 etcam_as_index0_cnt;
+} DPP_STAT_ETCAM_ETCAM_AS_INDEX0_CNT_T;
+
+typedef struct dpp_stat_etcam_etcam_as_index1_cnt_t {
+	ZXIC_UINT32 etcam_as_index1_cnt;
+} DPP_STAT_ETCAM_ETCAM_AS_INDEX1_CNT_T;
+
+typedef struct dpp_stat_etcam_etcam_not_hit0_cnt_t {
+	ZXIC_UINT32 etcam_not_hit0_cnt;
+} DPP_STAT_ETCAM_ETCAM_NOT_HIT0_CNT_T;
+
+typedef struct dpp_stat_etcam_etcam_not_hit1_cnt_t {
+	ZXIC_UINT32 etcam_not_hit1_cnt;
+} DPP_STAT_ETCAM_ETCAM_NOT_HIT1_CNT_T;
+
+typedef struct dpp_stat_etcam_table_id_not_match_cnt_t {
+	ZXIC_UINT32 table_id_not_match_cnt;
+} DPP_STAT_ETCAM_TABLE_ID_NOT_MATCH_CNT_T;
+
+typedef struct dpp_stat_etcam_table_id_clash01_cnt_t {
+	ZXIC_UINT32 table_id_clash01_cnt;
+} DPP_STAT_ETCAM_TABLE_ID_CLASH01_CNT_T;
+
+typedef struct dpp_stat_etcam_etcam_cpu_fl_t {
+	ZXIC_UINT32 etcam_cpu_fl;
+} DPP_STAT_ETCAM_ETCAM_CPU_FL_T;
+
+typedef struct dpp_stat_etcam_etcam_arb_empty_t {
+	ZXIC_UINT32 etcam_arb_empty;
+} DPP_STAT_ETCAM_ETCAM_ARB_EMPTY_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_trpg_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_trpg_reg.h
index aaed0254a8dbdc80e2a47c9693e4af81a1ba9392..4730b8e07d97ea96ee3ef969fd06a747a64d35a5 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_trpg_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_trpg_reg.h
@@ -3,342 +3,274 @@
 #define _DPP_TRPG_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_ms_en_t
-{
-    ZXIC_UINT32 cpu_trpgrx_ms_en;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_MS_EN_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_port_en_t
-{
-    ZXIC_UINT32 cpu_trpgrx_port_en;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_PORT_EN_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_look_en_t
-{
-    ZXIC_UINT32 cpu_trpgrx_look_en;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_LOOK_EN_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_ram_almost_full_t
-{
-    ZXIC_UINT32 cpu_trpgrx_ram_almost_full;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_ALMOST_FULL_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_ram_test_en_t
-{
-    ZXIC_UINT32 cpu_trpgrx_ram_test_en;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_TEST_EN_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_inmod_pfc_rdy_en_t
-{
-    ZXIC_UINT32 cpu_trpgrx_inmod_pfc_rdy_en;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_INMOD_PFC_RDY_EN_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_h_t
-{
-    ZXIC_UINT32 cpu_trpgrx_pkt_num_h;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_H_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_l_t
-{
-    ZXIC_UINT32 cpu_trpgrx_pkt_num_l;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_L_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_h_t
-{
-    ZXIC_UINT32 cpu_trpgrx_pkt_byte_num_h;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_H_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_l_t
-{
-    ZXIC_UINT32 cpu_trpgrx_pkt_byte_num_l;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_L_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_cnt_clr_t
-{
-    ZXIC_UINT32 cpu_trpgrx_pkt_cnt_clr;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_CNT_CLR_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_fc_clk_freq_t
-{
-    ZXIC_UINT32 cpu_trpgrx_fc_clk_freq;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_CLK_FREQ_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_fc_en_t
-{
-    ZXIC_UINT32 cpu_trpgrx_fc_en;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_EN_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_fc_token_add_num_t
-{
-    ZXIC_UINT32 cpu_trpgrx_fc_token_add_num;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_ADD_NUM_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_fc_token_max_num_t
-{
-    ZXIC_UINT32 cpu_trpgrx_fc_token_max_num;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_MAX_NUM_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_port_state_info_t
-{
-    ZXIC_UINT32 cpu_trpgrx_port_state_info;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PORT_STATE_INFO_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_t
-{
-    ZXIC_UINT32 cpu_trpgrx_ram_past_max_dep;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEP_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_clr_t
-{
-    ZXIC_UINT32 cpu_trpgrx_ram_past_max_dep_clr;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEP_CLR_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_t
-{
-    ZXIC_UINT32 cpu_trpgrx_pkt_past_max_len;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LEN_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_clr_t
-{
-    ZXIC_UINT32 cpu_trpgrx_pkt_past_max_len_clr;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LEN_CLR_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_t
-{
-    ZXIC_UINT32 cpu_trpgrx_pkt_past_min_len;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LEN_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_clr_t
-{
-    ZXIC_UINT32 cpu_trpgrx_pkt_past_min_len_clr;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LEN_CLR_T;
-
-typedef struct dpp_trpg_trpg_rx_ram_trpg_rx_data_ram_t
-{
-    ZXIC_UINT32 trpg_rx_data_ram;
-}DPP_TRPG_TRPG_RX_RAM_TRPG_RX_DATA_RAM_T;
-
-typedef struct dpp_trpg_trpg_rx_ram_trpg_rx_info_ram_t
-{
-    ZXIC_UINT32 trpg_rx_info_ram;
-}DPP_TRPG_TRPG_RX_RAM_TRPG_RX_INFO_RAM_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_ms_en_t
-{
-    ZXIC_UINT32 cpu_trpgtx_ms_en;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_MS_EN_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_port_en_t
-{
-    ZXIC_UINT32 cpu_trpgtx_port_en;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_PORT_EN_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_look_en_t
-{
-    ZXIC_UINT32 cpu_trpgtx_look_en;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_LOOK_EN_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_ram_almost_full_t
-{
-    ZXIC_UINT32 cpu_trpgtx_ram_almost_full;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_ALMOST_FULL_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_ram_test_en_t
-{
-    ZXIC_UINT32 cpu_trpgtx_ram_test_en;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_TEST_EN_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_h_t
-{
-    ZXIC_UINT32 cpu_trpgtx_pkt_num_h;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_H_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_l_t
-{
-    ZXIC_UINT32 cpu_trpgtx_pkt_num_l;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_L_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_h_t
-{
-    ZXIC_UINT32 cpu_trpgtx_pkt_byte_num_h;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_H_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_l_t
-{
-    ZXIC_UINT32 cpu_trpgtx_pkt_byte_num_l;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_L_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_cnt_clr_t
-{
-    ZXIC_UINT32 cpu_trpgtx_pkt_cnt_clr;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_CNT_CLR_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_fc_clk_freq_t
-{
-    ZXIC_UINT32 cpu_trpgtx_fc_clk_freq;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_CLK_FREQ_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_fc_en_t
-{
-    ZXIC_UINT32 cpu_trpgtx_fc_en;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_EN_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_fc_token_add_num_t
-{
-    ZXIC_UINT32 cpu_trpgtx_fc_token_add_num;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_ADD_NUM_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_fc_token_max_num_t
-{
-    ZXIC_UINT32 cpu_trpgtx_fc_token_max_num;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_MAX_NUM_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_port_state_info_t
-{
-    ZXIC_UINT32 cpu_trpgtx_port_state_info;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PORT_STATE_INFO_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_t
-{
-    ZXIC_UINT32 cpu_trpgtx_ram_past_max_dep;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEP_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_clr_t
-{
-    ZXIC_UINT32 cpu_trpgtx_ram_past_max_dep_clr;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEP_CLR_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_t
-{
-    ZXIC_UINT32 cpu_trpgtx_pkt_past_max_len;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LEN_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_clr_t
-{
-    ZXIC_UINT32 cpu_trpgtx_pkt_past_max_len_clr;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LEN_CLR_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_t
-{
-    ZXIC_UINT32 cpu_trpgtx_pkt_past_min_len;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LEN_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_clr_t
-{
-    ZXIC_UINT32 cpu_trpgtx_pkt_past_min_len_clr;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LEN_CLR_T;
-
-typedef struct dpp_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_almost_full_t
-{
-    ZXIC_UINT32 cpu_trpgtx_etm_ram_almost_full;
-}DPP_TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_ALMOST_FULL_T;
-
-typedef struct dpp_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_test_en_t
-{
-    ZXIC_UINT32 cpu_trpgtx_etm_ram_test_en;
-}DPP_TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_TEST_EN_T;
-
-typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_update_int_mask_t
-{
-    ZXIC_UINT32 cpu_todtime_update_int_mask;
-}DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_MASK_T;
-
-typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_update_int_clr_t
-{
-    ZXIC_UINT32 cpu_todtime_update_int_clr;
-}DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_CLR_T;
-
-typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_ram_test_en_t
-{
-    ZXIC_UINT32 cpu_todtime_ram_test_en;
-}DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_RAM_TEST_EN_T;
-
-typedef struct dpp_trpg_trpg_tx_ram_trpg_tx_data_ram_t
-{
-    ZXIC_UINT32 trpg_tx_data_ram;
-}DPP_TRPG_TRPG_TX_RAM_TRPG_TX_DATA_RAM_T;
-
-typedef struct dpp_trpg_trpg_tx_ram_trpg_tx_info_ram_t
-{
-    ZXIC_UINT32 trpg_tx_info_ram;
-}DPP_TRPG_TRPG_TX_RAM_TRPG_TX_INFO_RAM_T;
-
-typedef struct dpp_trpg_trpg_tx_etm_ram_trpg_tx_etm_data_ram_t
-{
-    ZXIC_UINT32 trpg_tx_etm_data_ram;
-}DPP_TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_DATA_RAM_T;
-
-typedef struct dpp_trpg_trpg_tx_etm_ram_trpg_tx_etm_info_ram_t
-{
-    ZXIC_UINT32 trpg_tx_etm_info_ram;
-}DPP_TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_INFO_RAM_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_ms_st_t
-{
-    ZXIC_UINT32 cpu_trpgrx_ms_st;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_MS_ST_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_ms_ind_t
-{
-    ZXIC_UINT32 cpu_trpgrx_ms_ind;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_MS_IND_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_ms_slave_ind_t
-{
-    ZXIC_UINT32 cpu_trpgrx_ms_slave_ind;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_MS_SLAVE_IND_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_up_water_level_t
-{
-    ZXIC_UINT32 cpu_trpgrx_up_water_level;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_UP_WATER_LEVEL_T;
-
-typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_low_water_level_t
-{
-    ZXIC_UINT32 cpu_trpgrx_low_water_level;
-}DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_LOW_WATER_LEVEL_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_ms_st_t
-{
-    ZXIC_UINT32 cpu_trpgtx_ms_st;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_MS_ST_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_ms_ind_t
-{
-    ZXIC_UINT32 cpu_trpgtx_ms_ind;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_MS_IND_T;
-
-typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_ms_slave_ind_t
-{
-    ZXIC_UINT32 cpu_trpgtx_ms_slave_ind;
-}DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_MS_SLAVE_IND_T;
-
-typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_update_int_event_t
-{
-    ZXIC_UINT32 cpu_todtime_update_int_event;
-}DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_EVENT_T;
-
-typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_update_int_test_t
-{
-    ZXIC_UINT32 cpu_todtime_update_int_test;
-}DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_TEST_T;
-
-typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_update_int_addr_t
-{
-    ZXIC_UINT32 cpu_todtime_update_int_addr;
-}DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_ADDR_T;
-
-typedef struct dpp_trpg_trpg_tx_todtime_ram_trpg_tx_todtime_ram_t
-{
-    ZXIC_UINT32 trpg_tx_todtime_ram;
-}DPP_TRPG_TRPG_TX_TODTIME_RAM_TRPG_TX_TODTIME_RAM_T;
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_ms_en_t {
+	ZXIC_UINT32 cpu_trpgrx_ms_en;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_MS_EN_T;
 
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_port_en_t {
+	ZXIC_UINT32 cpu_trpgrx_port_en;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_PORT_EN_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_look_en_t {
+	ZXIC_UINT32 cpu_trpgrx_look_en;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_LOOK_EN_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_ram_almost_full_t {
+	ZXIC_UINT32 cpu_trpgrx_ram_almost_full;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_ALMOST_FULL_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_ram_test_en_t {
+	ZXIC_UINT32 cpu_trpgrx_ram_test_en;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_TEST_EN_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_inmod_pfc_rdy_en_t {
+	ZXIC_UINT32 cpu_trpgrx_inmod_pfc_rdy_en;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_INMOD_PFC_RDY_EN_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_h_t {
+	ZXIC_UINT32 cpu_trpgrx_pkt_num_h;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_H_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_l_t {
+	ZXIC_UINT32 cpu_trpgrx_pkt_num_l;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_L_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_h_t {
+	ZXIC_UINT32 cpu_trpgrx_pkt_byte_num_h;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_H_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_l_t {
+	ZXIC_UINT32 cpu_trpgrx_pkt_byte_num_l;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_L_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_cnt_clr_t {
+	ZXIC_UINT32 cpu_trpgrx_pkt_cnt_clr;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_CNT_CLR_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_fc_clk_freq_t {
+	ZXIC_UINT32 cpu_trpgrx_fc_clk_freq;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_CLK_FREQ_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_fc_en_t {
+	ZXIC_UINT32 cpu_trpgrx_fc_en;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_EN_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_fc_token_add_num_t {
+	ZXIC_UINT32 cpu_trpgrx_fc_token_add_num;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_ADD_NUM_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_fc_token_max_num_t {
+	ZXIC_UINT32 cpu_trpgrx_fc_token_max_num;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_MAX_NUM_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_port_state_info_t {
+	ZXIC_UINT32 cpu_trpgrx_port_state_info;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PORT_STATE_INFO_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_t {
+	ZXIC_UINT32 cpu_trpgrx_ram_past_max_dep;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEP_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_clr_t {
+	ZXIC_UINT32 cpu_trpgrx_ram_past_max_dep_clr;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEP_CLR_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_t {
+	ZXIC_UINT32 cpu_trpgrx_pkt_past_max_len;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LEN_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_clr_t {
+	ZXIC_UINT32 cpu_trpgrx_pkt_past_max_len_clr;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LEN_CLR_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_t {
+	ZXIC_UINT32 cpu_trpgrx_pkt_past_min_len;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LEN_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_clr_t {
+	ZXIC_UINT32 cpu_trpgrx_pkt_past_min_len_clr;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LEN_CLR_T;
+
+typedef struct dpp_trpg_trpg_rx_ram_trpg_rx_data_ram_t {
+	ZXIC_UINT32 trpg_rx_data_ram;
+} DPP_TRPG_TRPG_RX_RAM_TRPG_RX_DATA_RAM_T;
+
+typedef struct dpp_trpg_trpg_rx_ram_trpg_rx_info_ram_t {
+	ZXIC_UINT32 trpg_rx_info_ram;
+} DPP_TRPG_TRPG_RX_RAM_TRPG_RX_INFO_RAM_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_ms_en_t {
+	ZXIC_UINT32 cpu_trpgtx_ms_en;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_MS_EN_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_port_en_t {
+	ZXIC_UINT32 cpu_trpgtx_port_en;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_PORT_EN_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_look_en_t {
+	ZXIC_UINT32 cpu_trpgtx_look_en;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_LOOK_EN_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_ram_almost_full_t {
+	ZXIC_UINT32 cpu_trpgtx_ram_almost_full;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_ALMOST_FULL_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_ram_test_en_t {
+	ZXIC_UINT32 cpu_trpgtx_ram_test_en;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_TEST_EN_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_h_t {
+	ZXIC_UINT32 cpu_trpgtx_pkt_num_h;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_H_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_l_t {
+	ZXIC_UINT32 cpu_trpgtx_pkt_num_l;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_L_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_h_t {
+	ZXIC_UINT32 cpu_trpgtx_pkt_byte_num_h;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_H_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_l_t {
+	ZXIC_UINT32 cpu_trpgtx_pkt_byte_num_l;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_L_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_cnt_clr_t {
+	ZXIC_UINT32 cpu_trpgtx_pkt_cnt_clr;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_CNT_CLR_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_fc_clk_freq_t {
+	ZXIC_UINT32 cpu_trpgtx_fc_clk_freq;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_CLK_FREQ_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_fc_en_t {
+	ZXIC_UINT32 cpu_trpgtx_fc_en;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_EN_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_fc_token_add_num_t {
+	ZXIC_UINT32 cpu_trpgtx_fc_token_add_num;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_ADD_NUM_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_fc_token_max_num_t {
+	ZXIC_UINT32 cpu_trpgtx_fc_token_max_num;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_MAX_NUM_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_port_state_info_t {
+	ZXIC_UINT32 cpu_trpgtx_port_state_info;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PORT_STATE_INFO_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_t {
+	ZXIC_UINT32 cpu_trpgtx_ram_past_max_dep;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEP_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_clr_t {
+	ZXIC_UINT32 cpu_trpgtx_ram_past_max_dep_clr;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEP_CLR_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_t {
+	ZXIC_UINT32 cpu_trpgtx_pkt_past_max_len;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LEN_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_clr_t {
+	ZXIC_UINT32 cpu_trpgtx_pkt_past_max_len_clr;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LEN_CLR_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_t {
+	ZXIC_UINT32 cpu_trpgtx_pkt_past_min_len;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LEN_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_clr_t {
+	ZXIC_UINT32 cpu_trpgtx_pkt_past_min_len_clr;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LEN_CLR_T;
+
+typedef struct dpp_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_almost_full_t {
+	ZXIC_UINT32 cpu_trpgtx_etm_ram_almost_full;
+} DPP_TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_ALMOST_FULL_T;
+
+typedef struct dpp_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_test_en_t {
+	ZXIC_UINT32 cpu_trpgtx_etm_ram_test_en;
+} DPP_TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_TEST_EN_T;
+
+typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_update_int_mask_t {
+	ZXIC_UINT32 cpu_todtime_update_int_mask;
+} DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_MASK_T;
+
+typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_update_int_clr_t {
+	ZXIC_UINT32 cpu_todtime_update_int_clr;
+} DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_CLR_T;
+
+typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_ram_test_en_t {
+	ZXIC_UINT32 cpu_todtime_ram_test_en;
+} DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_RAM_TEST_EN_T;
+
+typedef struct dpp_trpg_trpg_tx_ram_trpg_tx_data_ram_t {
+	ZXIC_UINT32 trpg_tx_data_ram;
+} DPP_TRPG_TRPG_TX_RAM_TRPG_TX_DATA_RAM_T;
+
+typedef struct dpp_trpg_trpg_tx_ram_trpg_tx_info_ram_t {
+	ZXIC_UINT32 trpg_tx_info_ram;
+} DPP_TRPG_TRPG_TX_RAM_TRPG_TX_INFO_RAM_T;
+
+typedef struct dpp_trpg_trpg_tx_etm_ram_trpg_tx_etm_data_ram_t {
+	ZXIC_UINT32 trpg_tx_etm_data_ram;
+} DPP_TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_DATA_RAM_T;
+
+typedef struct dpp_trpg_trpg_tx_etm_ram_trpg_tx_etm_info_ram_t {
+	ZXIC_UINT32 trpg_tx_etm_info_ram;
+} DPP_TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_INFO_RAM_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_ms_st_t {
+	ZXIC_UINT32 cpu_trpgrx_ms_st;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_MS_ST_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_ms_ind_t {
+	ZXIC_UINT32 cpu_trpgrx_ms_ind;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_MS_IND_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpg_ms_slave_ind_t {
+	ZXIC_UINT32 cpu_trpgrx_ms_slave_ind;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPG_MS_SLAVE_IND_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_up_water_level_t {
+	ZXIC_UINT32 cpu_trpgrx_up_water_level;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_UP_WATER_LEVEL_T;
+
+typedef struct dpp_trpg_trpg_rx_port_cpu_trpgrx_low_water_level_t {
+	ZXIC_UINT32 cpu_trpgrx_low_water_level;
+} DPP_TRPG_TRPG_RX_PORT_CPU_TRPGRX_LOW_WATER_LEVEL_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_ms_st_t {
+	ZXIC_UINT32 cpu_trpgtx_ms_st;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_MS_ST_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_ms_ind_t {
+	ZXIC_UINT32 cpu_trpgtx_ms_ind;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_MS_IND_T;
+
+typedef struct dpp_trpg_trpg_tx_port_cpu_trpg_ms_slave_ind_t {
+	ZXIC_UINT32 cpu_trpgtx_ms_slave_ind;
+} DPP_TRPG_TRPG_TX_PORT_CPU_TRPG_MS_SLAVE_IND_T;
+
+typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_update_int_event_t {
+	ZXIC_UINT32 cpu_todtime_update_int_event;
+} DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_EVENT_T;
+
+typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_update_int_test_t {
+	ZXIC_UINT32 cpu_todtime_update_int_test;
+} DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_TEST_T;
+
+typedef struct dpp_trpg_trpg_tx_glb_cpu_todtime_update_int_addr_t {
+	ZXIC_UINT32 cpu_todtime_update_int_addr;
+} DPP_TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_ADDR_T;
+
+typedef struct dpp_trpg_trpg_tx_todtime_ram_trpg_tx_todtime_ram_t {
+	ZXIC_UINT32 trpg_tx_todtime_ram;
+} DPP_TRPG_TRPG_TX_TODTIME_RAM_TRPG_TX_TODTIME_RAM_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_tsn_reg.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_tsn_reg.h
index 2fc65426d30b3f8e6593cedaa9fa3200e65fd2c1..e90b4c774b8d34f37d03bae27110d96d8e43d1a6 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_tsn_reg.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/dev/reg/dpp_tsn_reg.h
@@ -3,122 +3,99 @@
 #define _DPP_TSN_REG_H_
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
-typedef struct dpp_tsn_tsn_port_cfg_tsn_test_reg_t
-{
-    ZXIC_UINT32 cfg_tsn_test_reg;
-}DPP_TSN_TSN_PORT_CFG_TSN_TEST_REG_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_port_qbv_enable_t
-{
-    ZXIC_UINT32 cfg_tsn_port_qbv_enable;
-}DPP_TSN_TSN_PORT_CFG_TSN_PORT_QBV_ENABLE_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_phy_port_sel_t
-{
-    ZXIC_UINT32 cfg_tsn_phy_port_sel;
-}DPP_TSN_TSN_PORT_CFG_TSN_PHY_PORT_SEL_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_port_time_sel_t
-{
-    ZXIC_UINT32 cfg_tsn_port_time_sel;
-}DPP_TSN_TSN_PORT_CFG_TSN_PORT_TIME_SEL_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_clk_freq_t
-{
-    ZXIC_UINT32 en;
-    ZXIC_UINT32 cfg_tsn_clk_freq;
-}DPP_TSN_TSN_PORT_CFG_TSN_CLK_FREQ_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_read_ram_n_t
-{
-    ZXIC_UINT32 cfg_tsn_data;
-    ZXIC_UINT32 cfg_tsn_read_status;
-    ZXIC_UINT32 cfg_tsn_read_ram_n;
-}DPP_TSN_TSN_PORT_CFG_TSN_READ_RAM_N_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_exe_time_t
-{
-    ZXIC_UINT32 cfg_tsn_exe_time;
-}DPP_TSN_TSN_PORT_CFG_TSN_EXE_TIME_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_port_itr_shift_t
-{
-    ZXIC_UINT32 cfg_tsn_port_itr_shift;
-}DPP_TSN_TSN_PORT_CFG_TSN_PORT_ITR_SHIFT_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_port_base_time_h_t
-{
-    ZXIC_UINT32 cfg_tsn_port_base_time_h;
-}DPP_TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_H_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_port_base_time_l_t
-{
-    ZXIC_UINT32 cfg_tsn_port_base_time_l;
-}DPP_TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_L_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_port_cycle_time_h_t
-{
-    ZXIC_UINT32 cfg_tsn_port_cycle_time_h;
-}DPP_TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_H_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_port_cycle_time_l_t
-{
-    ZXIC_UINT32 cfg_tsn_port_cycle_time_l;
-}DPP_TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_L_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_port_guard_band_time_t
-{
-    ZXIC_UINT32 cfg_tsn_port_guard_band_time;
-}DPP_TSN_TSN_PORT_CFG_TSN_PORT_GUARD_BAND_TIME_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_port_default_gate_en_t
-{
-    ZXIC_UINT32 cfg_tsn_port_default_gate_en;
-}DPP_TSN_TSN_PORT_CFG_TSN_PORT_DEFAULT_GATE_EN_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_port_change_gate_en_t
-{
-    ZXIC_UINT32 cfg_tsn_port_change_gate_en;
-}DPP_TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_GATE_EN_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_port_init_finish_t
-{
-    ZXIC_UINT32 cfg_tsn_port_init_finish;
-}DPP_TSN_TSN_PORT_CFG_TSN_PORT_INIT_FINISH_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_port_change_en_t
-{
-    ZXIC_UINT32 cfg_tsn_port_change_en;
-}DPP_TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_EN_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_port_gcl_num0_t
-{
-    ZXIC_UINT32 cfg_tsn_port_gcl_num0;
-}DPP_TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM0_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_port_gcl_num1_t
-{
-    ZXIC_UINT32 cfg_tsn_port_gcl_num1;
-}DPP_TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM1_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_port_gcl_value0_t
-{
-    ZXIC_UINT32 cfg_tsn_port_gcl_gate_control0;
-    ZXIC_UINT32 cfg_tsn_port_gcl_interval_time0;
-}DPP_TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE0_T;
-
-typedef struct dpp_tsn_tsn_port_cfg_tsn_port_gcl_value1_t
-{
-    ZXIC_UINT32 cfg_tsn_port_gcl_gate_control1;
-    ZXIC_UINT32 cfg_tsn_port_gcl_interval_time1;
-}DPP_TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE1_T;
+typedef struct dpp_tsn_tsn_port_cfg_tsn_test_reg_t {
+	ZXIC_UINT32 cfg_tsn_test_reg;
+} DPP_TSN_TSN_PORT_CFG_TSN_TEST_REG_T;
 
+typedef struct dpp_tsn_tsn_port_cfg_tsn_port_qbv_enable_t {
+	ZXIC_UINT32 cfg_tsn_port_qbv_enable;
+} DPP_TSN_TSN_PORT_CFG_TSN_PORT_QBV_ENABLE_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_phy_port_sel_t {
+	ZXIC_UINT32 cfg_tsn_phy_port_sel;
+} DPP_TSN_TSN_PORT_CFG_TSN_PHY_PORT_SEL_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_port_time_sel_t {
+	ZXIC_UINT32 cfg_tsn_port_time_sel;
+} DPP_TSN_TSN_PORT_CFG_TSN_PORT_TIME_SEL_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_clk_freq_t {
+	ZXIC_UINT32 en;
+	ZXIC_UINT32 cfg_tsn_clk_freq;
+} DPP_TSN_TSN_PORT_CFG_TSN_CLK_FREQ_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_read_ram_n_t {
+	ZXIC_UINT32 cfg_tsn_data;
+	ZXIC_UINT32 cfg_tsn_read_status;
+	ZXIC_UINT32 cfg_tsn_read_ram_n;
+} DPP_TSN_TSN_PORT_CFG_TSN_READ_RAM_N_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_exe_time_t {
+	ZXIC_UINT32 cfg_tsn_exe_time;
+} DPP_TSN_TSN_PORT_CFG_TSN_EXE_TIME_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_port_itr_shift_t {
+	ZXIC_UINT32 cfg_tsn_port_itr_shift;
+} DPP_TSN_TSN_PORT_CFG_TSN_PORT_ITR_SHIFT_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_port_base_time_h_t {
+	ZXIC_UINT32 cfg_tsn_port_base_time_h;
+} DPP_TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_H_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_port_base_time_l_t {
+	ZXIC_UINT32 cfg_tsn_port_base_time_l;
+} DPP_TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_L_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_port_cycle_time_h_t {
+	ZXIC_UINT32 cfg_tsn_port_cycle_time_h;
+} DPP_TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_H_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_port_cycle_time_l_t {
+	ZXIC_UINT32 cfg_tsn_port_cycle_time_l;
+} DPP_TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_L_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_port_guard_band_time_t {
+	ZXIC_UINT32 cfg_tsn_port_guard_band_time;
+} DPP_TSN_TSN_PORT_CFG_TSN_PORT_GUARD_BAND_TIME_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_port_default_gate_en_t {
+	ZXIC_UINT32 cfg_tsn_port_default_gate_en;
+} DPP_TSN_TSN_PORT_CFG_TSN_PORT_DEFAULT_GATE_EN_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_port_change_gate_en_t {
+	ZXIC_UINT32 cfg_tsn_port_change_gate_en;
+} DPP_TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_GATE_EN_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_port_init_finish_t {
+	ZXIC_UINT32 cfg_tsn_port_init_finish;
+} DPP_TSN_TSN_PORT_CFG_TSN_PORT_INIT_FINISH_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_port_change_en_t {
+	ZXIC_UINT32 cfg_tsn_port_change_en;
+} DPP_TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_EN_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_port_gcl_num0_t {
+	ZXIC_UINT32 cfg_tsn_port_gcl_num0;
+} DPP_TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM0_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_port_gcl_num1_t {
+	ZXIC_UINT32 cfg_tsn_port_gcl_num1;
+} DPP_TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM1_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_port_gcl_value0_t {
+	ZXIC_UINT32 cfg_tsn_port_gcl_gate_control0;
+	ZXIC_UINT32 cfg_tsn_port_gcl_interval_time0;
+} DPP_TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE0_T;
+
+typedef struct dpp_tsn_tsn_port_cfg_tsn_port_gcl_value1_t {
+	ZXIC_UINT32 cfg_tsn_port_gcl_gate_control1;
+	ZXIC_UINT32 cfg_tsn_port_gcl_interval_time1;
+} DPP_TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE1_T;
 
 #ifdef __cplusplus
 }
 #endif
 #endif
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/diag/dpp_se_diag.h b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/diag/dpp_se_diag.h
old mode 100755
new mode 100644
index b6dd4697580dfb95d82ae583b7097730ac4efdc1..bb5901737047ea7ab66636321fc7f49479c48457
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/diag/dpp_se_diag.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/include/diag/dpp_se_diag.h
@@ -1,37 +1,36 @@
-/**************************************************************
-* ��Ȩ���� (C)2013-2015, ����������ͨѶ�ɷ����޹�˾
-* �ļ����� : dpp_se_diag.h
-* �ļ���ʶ :
-* ����ժҪ :
-* ����˵�� :
-* ��ǰ�汾 :
-* ��    �� : XXX
-* ������� : 2016/01/14
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* �޸ļ�¼1:
-* �޸�����:
-* �� �� ��:
-* �� �� ��:
-* �޸�����:
-***************************************************************/
-#ifndef _DPP_SE_DIAG_H_
-#define _DPP_SE_DIAG_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum diag_dpp_etcam_no_as_rsp_mode_e
-{
-    DPP_ETCAM_NO_AS_RSP_MODE_32  = 0,
-    DPP_ETCAM_NO_AS_RSP_MODE_64  = 1,
-    DPP_ETCAM_NO_AS_RSP_MODE_128 = 2,
-} DPP_DIAG_ETCAM_NO_AS_RSP_MODE_E;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/**************************************************************
+* ��Ȩ���� (C)2013-2015, ����������ͨѶ�ɷ����޹�˾
+* �ļ����� : dpp_se_diag.h
+* �ļ���ʶ :
+* ����ժҪ :
+* ����˵�� :
+* ��ǰ�汾 :
+* ��    �� : XXX
+* ������� : 2016/01/14
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* �޸ļ�¼1:
+* �޸�����:
+* �� �� ��:
+* �� �� ��:
+* �޸�����:
+***************************************************************/
+#ifndef _DPP_SE_DIAG_H_
+#define _DPP_SE_DIAG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum diag_dpp_etcam_no_as_rsp_mode_e {
+	DPP_ETCAM_NO_AS_RSP_MODE_32 = 0,
+	DPP_ETCAM_NO_AS_RSP_MODE_64 = 1,
+	DPP_ETCAM_NO_AS_RSP_MODE_128 = 2,
+} DPP_DIAG_ETCAM_NO_AS_RSP_MODE_E;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/dpp_dev.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/dpp_dev.c
old mode 100755
new mode 100644
index 95155dc18d529ab5cbfc9a81043375ee685f4a00..73fe412a8e454244db5f53f7f90dffbd6f965d86
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/dpp_dev.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/dpp_dev.c
@@ -1,1083 +1,1045 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_dev.c
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : 王春雷
-* 完成日期 : 2014/02/10
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1: 代码规范性修改
-* 修改日期:  2014/02/10
-* 版 本 号:
-* 修 改 人:  丁金凤
-* 修改内容:
-***************************************************************/
-
-#include "zxic_common.h"
-#include "dpp_module.h"
-#include "dpp_pci.h"
-#include "dpp_dev.h"
-#include "dpp_type_api.h"
-#include "dh_cmd.h"
-
-static DPP_DEV_MGR_T g_dev_mgr = {0};
-
-#define DPP_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id])
-
-/***********************************************************/
-/** 初始化设备管理模块
-* @param   ZXIC_VOID
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/03/06
-************************************************************/
-DPP_STATUS dpp_dev_init(ZXIC_VOID)
-{
-    if (g_dev_mgr.is_init)
-    {
-        ZXIC_COMM_TRACE_ERROR("Dev is already initialized.\n");
-        return DPP_OK;
-    }
-
-    g_dev_mgr.device_num = 0;
-    g_dev_mgr.is_init    = 1;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2014/02/14
-************************************************************/
-DPP_DEV_MGR_T *dpp_dev_mgr_get(ZXIC_VOID)
-{
-    if (!g_dev_mgr.is_init)
-    {
-        ZXIC_COMM_TRACE_ERROR("Error: dev_mgr is not init.\n");
-        ZXIC_COMM_ASSERT(0);
-        return NULL;
-    }
-
-    return &g_dev_mgr;
-}
-
-/***********************************************************/
-/** 添加新设备实例，并初始化
-* @param   dev_id         新增设备的设备号
-* @param   dev_type          设备类型，取值参照DPP_DEV_TYPE_E的定义
-* @param   access_type       设备访问类型，取值参照DPP_DEV_ACCESS_TYPE_E的定义
-* @param   pcie_addr         PCIe映射地址
-* @param   riscv_addr         RISCV映射地址
-* @param   dma_vir_addr      DMA映射地址
-* @param   dma_phy_addr      DMA内存物理地址
-* @param   p_pcie_write_fun  PCIe硬件写回调函数
-* @param   p_pcie_read_fun   PCIe硬件读回调函数
-* @param   p_riscv_write_fun  RISCV硬件写回调函数
-* @param   p_riscv_read_fun   RISCV硬件读回调函数
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/03/06
-************************************************************/
-DPP_STATUS dpp_dev_add(ZXIC_UINT32  dev_id,
-                       DPP_DEV_TYPE_E dev_type,
-                       DPP_DEV_ACCESS_TYPE_E  access_type,
-                       ZXIC_ADDR_T  pcie_addr,
-                       ZXIC_ADDR_T  riscv_addr,
-                       ZXIC_ADDR_T  dma_vir_addr,
-                       ZXIC_ADDR_T  dma_phy_addr,
-                       DPP_DEV_WRITE_FUNC p_pcie_write_fun,
-                       DPP_DEV_READ_FUNC  p_pcie_read_fun,
-                       DPP_DEV_WRITE_FUNC p_riscv_write_fun,
-                       DPP_DEV_READ_FUNC  p_riscv_read_fun)
-{
-    DPP_STATUS rtn = DPP_OK;
-    DPP_DEV_CFG_T *p_dev_info = NULL;
-    DPP_DEV_MGR_T *p_dev_mgr  = NULL;
-    ZXIC_UINT32     i = 0;
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1);
-
-    p_dev_mgr = dpp_dev_mgr_get();
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
-    if (!p_dev_mgr->is_init)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: Device Manager is not init!!!\n",
-                                 DPP_RC_DEV_MGR_NOT_INIT);
-        return DPP_RC_DEV_MGR_NOT_INIT;
-    }
-
-    if (p_dev_mgr->p_dev_array[dev_id] != NULL)
-    {
-        /* device is already exist. */
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Device is added again!!!\n");
-        p_dev_info = p_dev_mgr->p_dev_array[dev_id];
-    }
-    else
-    {
-        /* device is new. */
-        p_dev_info = (DPP_DEV_CFG_T *)ZXIC_COMM_MALLOC(sizeof(DPP_DEV_CFG_T));
-        ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info);
-        p_dev_mgr->p_dev_array[dev_id] = p_dev_info;
-        p_dev_mgr->device_num++;
-    }
-
-    p_dev_info->device_id   = dev_id;
-    p_dev_info->dev_type    = dev_type;
-    p_dev_info->access_type = access_type;
-    p_dev_info->pcie_addr   = pcie_addr;
-    p_dev_info->riscv_addr   = riscv_addr;
-    p_dev_info->dma_vir_addr = dma_vir_addr;
-    p_dev_info->dma_phy_addr = dma_phy_addr;
-    p_dev_info->p_riscv_write_fun = NULL;
-    p_dev_info->p_riscv_read_fun  = NULL;
-    p_dev_info->p_pcie_write_fun = dpp_dev_pcie_default_write;
-    p_dev_info->p_pcie_read_fun  = dpp_dev_pcie_default_read;
-
-    if(p_riscv_write_fun)
-    {
-        p_dev_info->p_riscv_write_fun  = p_riscv_write_fun;
-    }
-
-    if(p_riscv_read_fun)
-    {
-        p_dev_info->p_riscv_read_fun  = p_riscv_read_fun;
-    }
-
-    if (p_pcie_write_fun)
-    {
-        p_dev_info->p_pcie_write_fun = p_pcie_write_fun;
-    }
-
-    if (p_pcie_read_fun)
-    {
-        p_dev_info->p_pcie_read_fun  = p_pcie_read_fun;
-    }
-
-    if (dev_type == DPP_DEV_TYPE_CHIP)
-    {
-        p_dev_info->chip_ver = dpp_dev_chip_version_get(dev_id);
-    }
-    else if ((dev_type == DPP_DEV_TYPE_SIM) || (dev_type == DPP_DEV_TYPE_VCS))
-    {
-        //p_dev_info->chip_ver = dpp_vpci_get_chip_version();
-    }
-
-    ZXIC_COMM_MEMSET(p_dev_info->pcie_channel, 0x00, sizeof(p_dev_info->pcie_channel));
-
-    rtn = zxic_comm_mutex_create(&p_dev_info->reg_opr_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-
-    rtn = zxic_comm_mutex_create(&p_dev_info->oam_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-
-    rtn = zxic_comm_mutex_create(&p_dev_info->etm_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-
-    rtn = zxic_comm_mutex_create(&p_dev_info->ddr_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-
-    rtn = zxic_comm_mutex_create(&p_dev_info->ind_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-
-    rtn = zxic_comm_mutex_create(&p_dev_info->etcam_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-
-    rtn = zxic_comm_mutex_create(&p_dev_info->car0_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-
-    rtn = zxic_comm_mutex_create(&p_dev_info->alg_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-
-    rtn = zxic_comm_mutex_create(&p_dev_info->nppu_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-
-    rtn = zxic_comm_mutex_create(&p_dev_info->smmu0_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-
-    rtn = zxic_comm_mutex_create(&p_dev_info->smmu1_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-
-    rtn = zxic_comm_mutex_create(&p_dev_info->etm_2nd_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-
-    rtn = zxic_comm_mutex_create(&p_dev_info->lpm_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-
-    rtn = zxic_comm_mutex_create(&p_dev_info->crm_temp_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-
-    rtn = zxic_comm_mutex_create(&p_dev_info->sim_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-
-    rtn = zxic_comm_mutex_create(&p_dev_info->dtb_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-
-    for (i = 0; i < DPP_DTB_QUEUE_MAX; i++)
-    {
-        rtn = zxic_comm_mutex_create(&p_dev_info->dtb_queue_mutex[i]);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 删除设备实例
-* @param   dev_id  设备号
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/05/20
-************************************************************/
-DPP_STATUS dpp_dev_del(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS rtn = DPP_OK;
-    DPP_DEV_CFG_T *p_dev_info = NULL;
-    DPP_DEV_MGR_T *p_dev_mgr  = NULL;
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1);
-
-    p_dev_mgr = dpp_dev_mgr_get();
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
-    p_dev_info = p_dev_mgr->p_dev_array[dev_id];
-
-    if (p_dev_info != NULL)
-    {
-        rtn = zxic_comm_mutex_destroy(&p_dev_info->reg_opr_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
-
-        rtn = zxic_comm_mutex_destroy(&p_dev_info->oam_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
-
-        rtn = zxic_comm_mutex_destroy(&p_dev_info->etm_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
-
-        rtn = zxic_comm_mutex_destroy(&p_dev_info->ddr_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
-
-        rtn = zxic_comm_mutex_destroy(&p_dev_info->ind_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
-
-        rtn = zxic_comm_mutex_destroy(&p_dev_info->etcam_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
-
-        rtn = zxic_comm_mutex_destroy(&p_dev_info->car0_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
-
-        rtn = zxic_comm_mutex_destroy(&p_dev_info->alg_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
-
-        rtn = zxic_comm_mutex_destroy(&p_dev_info->nppu_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
-
-        rtn = zxic_comm_mutex_destroy(&p_dev_info->smmu0_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
-
-        rtn = zxic_comm_mutex_destroy(&p_dev_info->smmu1_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
-
-        rtn = zxic_comm_mutex_destroy(&p_dev_info->etm_2nd_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
-
-        rtn = zxic_comm_mutex_destroy(&p_dev_info->lpm_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
-
-        rtn = zxic_comm_mutex_destroy(&p_dev_info->crm_temp_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
-
-
-        ZXIC_COMM_FREE(p_dev_info);
-        p_dev_mgr->p_dev_array[dev_id] = NULL;
-        ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, p_dev_mgr->device_num, 1);
-        p_dev_mgr->device_num--;
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取 DPP_DEV_T
-* @param   dev_id
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/05/20
-************************************************************/
-DPP_STATUS dpp_dev_get(ZXIC_UINT32 dev_id, DPP_PF_INFO_T* pf_info, DPP_DEV_T *dev)
-{
-    ZXIC_UINT16 slot = 0;
-    ZXIC_UINT16 channel_id = 0;
-
-    DPP_DEV_CFG_T *p_dev_info = NULL;
-    DPP_DEV_MGR_T *p_dev_mgr  = NULL;
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, pf_info);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, dev);
-
-    slot = pf_info->slot;
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, slot, 0, DPP_PCIE_SLOT_MAX - 1);
-
-    channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
-
-    p_dev_mgr = dpp_dev_mgr_get();
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
-    if (!p_dev_mgr->is_init)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: Device Manager is not init!!!\n",
-                                                                     DPP_RC_DEV_MGR_NOT_INIT);
-        return DPP_RC_DEV_MGR_NOT_INIT;
-    }
-    p_dev_info = p_dev_mgr->p_dev_array[dev_id];
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info);
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info->pcie_channel[slot][channel_id].device);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info->pcie_channel[slot][channel_id].oper_mutex);
-
-    dev->device_id = p_dev_info->device_id;
-    dev->pcie_channel.slot = p_dev_info->pcie_channel[slot][channel_id].slot;
-    dev->pcie_channel.vport = p_dev_info->pcie_channel[slot][channel_id].vport;
-    dev->pcie_channel.pcie_id = p_dev_info->pcie_channel[slot][channel_id].pcie_id;
-    dev->pcie_channel.device = p_dev_info->pcie_channel[slot][channel_id].device;
-    dev->pcie_channel.base_addr = p_dev_info->pcie_channel[slot][channel_id].base_addr;
-    dev->pcie_channel.offset_addr = p_dev_info->pcie_channel[slot][channel_id].offset_addr;
-    dev->pcie_channel.oper_mutex = p_dev_info->pcie_channel[slot][channel_id].oper_mutex;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 
-* @param   dev_id         设备的设备号
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/03/06
-************************************************************/
-DPP_STATUS dpp_dev_pcie_channel_add(ZXIC_UINT32 dev_id, DPP_PF_INFO_T* pf_info, struct pci_dev* p_dev)
-{
-    DPP_STATUS rc = 0;
-    ZXIC_VOID* base_addr = 0;
-    ZXIC_UINT8  type = 0;
-    ZXIC_UINT32 post = 0;
-    ZXIC_UINT16 pcie_id = 0;
-    ZXIC_UINT16 slot = 0;
-    ZXIC_UINT16 channel_id = 0;
-    DPP_DEV_CFG_T *p_dev_info = NULL;
-    DPP_DEV_MGR_T *p_dev_mgr  = NULL;
-
-#ifdef DPP_FLOW_HW_INIT
-    struct bar_offset_res res;
-    struct bar_offset_params paras;
-#endif
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, pf_info);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev);
-
-    slot = pf_info->slot;
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, slot, 0, DPP_PCIE_SLOT_MAX - 1);
-
-    channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
-
-    p_dev_mgr = dpp_dev_mgr_get();
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
-    if (!p_dev_mgr->is_init)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: Device Manager is not init!!!\n",
-                                                                     DPP_RC_DEV_MGR_NOT_INIT);
-        return DPP_RC_DEV_MGR_NOT_INIT;
-    }
-    p_dev_info = p_dev_mgr->p_dev_array[dev_id];
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info);
-
-    if (p_dev_info->pcie_channel[slot][channel_id].device != NULL)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: pcie slot %u vport 0x%04x already init.\n",
-                                                         DPP_RC_DEV_PARA_INVALID, slot, pf_info->vport);
-        return DPP_RC_DEV_PARA_INVALID;
-    }
-
-    base_addr = ioremap(pci_resource_start(p_dev, 0), pci_resource_len(p_dev, 0));
-    if (IS_ERR_OR_NULL(base_addr))
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: pcie slot %u vport 0x%04x ioremap failed.\n",
-                                                           DPP_RC_DEV_PARA_INVALID, slot, pf_info->vport);
-        return DPP_RC_DEV_PARA_INVALID;
-    }
-
-    for (post = pci_find_capability(p_dev, PCI_CAP_ID_VNDR);
-         post > 0; post = pci_find_next_capability(p_dev, post, PCI_CAP_ID_VNDR))
-    {
-        pci_read_config_byte(p_dev, post + 3, &type);
-
-        if (type == 5)
-        {
-            pci_read_config_word(p_dev, post + 6, &pcie_id);
-        }
-    }
-
-    if (pcie_id == 0)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: pcie slot %u vport 0x%04x get pcieid failed.\n",
-                                                              DPP_RC_DEV_PARA_INVALID, slot, pf_info->vport);
-        return DPP_RC_DEV_PARA_INVALID;
-    }
-
-#ifdef DPP_FLOW_HW_INIT
-    paras.type = URI_NP;
-    paras.pcie_id = pcie_id;
-    paras.virt_addr = ZXIC_COMM_PTR_TO_VAL(base_addr) + DEV_PCIE_MSG_OFFSET_ADDR;
-    if (zxdh_get_bar_offset(&paras, &res) != BAR_MSG_OK)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: pcie slot %u vport 0x%04x get bar offset failed.\n",
-                                                                  DPP_RC_DEV_PARA_INVALID, slot, pf_info->vport);
-        return DPP_RC_DEV_PARA_INVALID;
-    }
-#endif
-    p_dev_info->pcie_channel[slot][channel_id].slot      = slot;
-    p_dev_info->pcie_channel[slot][channel_id].vport     = pf_info->vport;
-    p_dev_info->pcie_channel[slot][channel_id].pcie_id   = pcie_id;
-    p_dev_info->pcie_channel[slot][channel_id].device    = p_dev;
-    p_dev_info->pcie_channel[slot][channel_id].base_addr = ZXIC_COMM_PTR_TO_VAL(base_addr);
-
-#ifdef DPP_FLOW_HW_INIT
-    p_dev_info->pcie_channel[slot][channel_id].offset_addr = res.bar_offset;
-#else
-    p_dev_info->pcie_channel[slot][channel_id].offset_addr = 0x6000;
-#endif
-
-    p_dev_info->pcie_channel[slot][channel_id].oper_mutex = ZXIC_COMM_MALLOC(sizeof(ZXIC_MUTEX_T));
-    rc = zxic_comm_mutex_create(p_dev_info->pcie_channel[slot][channel_id].oper_mutex);
-    ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE(dev_id, rc, "zxic_comm_mutex_create",
-                                            p_dev_info->pcie_channel[slot][channel_id].oper_mutex);
-
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x base_addr: 0x%llx success.\n",
-                                                 __FUNCTION__, slot, pf_info->vport, ZXIC_COMM_PTR_TO_VAL(base_addr));
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x pcie_id: 0x%04x offset_addr: 0x%llx success.\n",
-                                                 __FUNCTION__, slot, pf_info->vport, pcie_id,
-                                         p_dev_info->pcie_channel[slot][channel_id].offset_addr);
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 
-* @param   dev_id         设备的设备号
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/03/06
-************************************************************/
-DPP_STATUS dpp_dev_pcie_channel_del(ZXIC_UINT32 dev_id, DPP_PF_INFO_T* pf_info)
-{
-    DPP_STATUS rc = 0;
-    ZXIC_UINT16 slot = 0;
-    ZXIC_UINT16 channel_id = 0;
-    DPP_DEV_CFG_T *p_dev_info = NULL;
-    DPP_DEV_MGR_T *p_dev_mgr  = NULL;
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, pf_info);
-
-    slot = pf_info->slot;
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, slot, 0, DPP_PCIE_SLOT_MAX - 1);
-
-    channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
-
-    p_dev_mgr = dpp_dev_mgr_get();
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
-    if (!p_dev_mgr->is_init)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: Device Manager is not init!!!\n",
-                                                                     DPP_RC_DEV_MGR_NOT_INIT);
-        return DPP_RC_DEV_MGR_NOT_INIT;
-    }
-    p_dev_info = p_dev_mgr->p_dev_array[dev_id];
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info);
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info->pcie_channel[slot][channel_id].device);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info->pcie_channel[slot][channel_id].oper_mutex);
-
-    rc = zxic_comm_mutex_destroy(p_dev_info->pcie_channel[slot][channel_id].oper_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_mutex_destroy");
-    ZXIC_COMM_FREE(p_dev_info->pcie_channel[slot][channel_id].oper_mutex);
-
-    iounmap((ZXIC_VOID*)p_dev_info->pcie_channel[slot][channel_id].base_addr);
-
-    p_dev_info->pcie_channel[slot][channel_id].device = NULL;
-    p_dev_info->pcie_channel[slot][channel_id].slot = 0;
-    p_dev_info->pcie_channel[slot][channel_id].vport = 0;
-    p_dev_info->pcie_channel[slot][channel_id].pcie_id = 0;
-    p_dev_info->pcie_channel[slot][channel_id].base_addr = 0;
-    p_dev_info->pcie_channel[slot][channel_id].offset_addr = 0;
-
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, slot, pf_info->vport);
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取设备类型
-* @param   dev_id  设备号
-*
-* @return  设备类型，参考DPP_DEV_TYPE_E的定义
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/03/06
-************************************************************/
-ZXIC_UINT32 dpp_dev_get_dev_type(ZXIC_UINT32 dev_id)
-{
-    DPP_DEV_MGR_T *p_dev_mgr = NULL;
-    DPP_DEV_CFG_T *p_dev_info = NULL;
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
-
-    p_dev_mgr = dpp_dev_mgr_get();
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
-
-    p_dev_info = p_dev_mgr->p_dev_array[dev_id];
-
-    if (NULL == p_dev_info)
-    {
-        return DPP_DEV_TYPE_INVALID;
-    }
-
-    return (p_dev_info->dev_type);
-}
-
-/***********************************************************/
-/** 获取芯片类型
-* @param   dev_id
-*
-* @return
-* @remark  无
-* @see
-* @author  lfq      @date  2014/03/05
-************************************************************/
-ZXIC_UINT32 dpp_dev_chip_version_get(ZXIC_UINT32 dev_id)
-{
-    // ZXIC_UINT32 device_no  = 0;
-    ZXIC_UINT32 chip_ver   = 0;
-
-    // ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1);
-
-    // if (device_no == DPP_CHIP_DPP)
-    // {
-    //     chip_ver = DPP_CHIP_VERSION_DPP_P;
-    // }
-    // else
-    // {
-        // ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Device id [0x%08x] is wrong\n", device_no);
-    // }
-
-    return chip_ver;
-}
-
-/***********************************************************/
-/** 每个模块的初始化标记设置接口
-* @param   dev_id    设备号
-* @param   module_id 模块ID, 见MODULE_INIT_E
-* @param   flag      31bit代表整体初始化状态(1:完成 0:未完成或未开始)，其余31bit自由利用，可以按子模块的初始化状态赋值
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  初始化标记主要用于记录本模块的初始化状态
-* @see
-* @author  xjw      @date  2019/10/30
-************************************************************/
-DPP_STATUS dpp_dev_init_flag_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 flag)
-{
-    DPP_DEV_CFG_T *p_dev_info = NULL;
-    DPP_DEV_MGR_T *p_dev_mgr  = NULL;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, module_id, MODULE_INIT_NPPU, MODULE_INIT_MAX - 1);
-
-    p_dev_mgr = dpp_dev_mgr_get();
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
-    p_dev_info = p_dev_mgr->p_dev_array[dev_id];
-
-    if (NULL == p_dev_info)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: Device CFG is not init!!!\n",
-                                 DPP_RC_DEV_CFG_NOT_INIT);
-        return DPP_RC_DEV_CFG_NOT_INIT;
-    }
-
-    p_dev_info->init_flags[module_id] = flag;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 每个模块的初始化标记获取接口
-* @param   dev_id    设备号
-* @param   module_id 模块ID, 见MODULE_INIT_E
-* @param   p_flag    按ZXIC_UINT32返回，bit处理各模块自行完成
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  初始化标记主要用于记录本模块的初始化状态
-* @see
-* @author  xjw      @date  2019/10/30
-************************************************************/
-DPP_STATUS dpp_dev_init_flag_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 *p_flag)
-{
-    DPP_DEV_CFG_T *p_dev_info = NULL;
-    DPP_DEV_MGR_T *p_dev_mgr  = NULL;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, module_id, MODULE_INIT_NPPU, MODULE_INIT_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_flag);
-
-    p_dev_mgr = dpp_dev_mgr_get();
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
-    p_dev_info = p_dev_mgr->p_dev_array[dev_id];
-
-    if (NULL == p_dev_info)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[ 0x%x]: Device CFG is not init!!!\n",
-                                 DPP_RC_DEV_CFG_NOT_INIT);
-        return DPP_RC_DEV_CFG_NOT_INIT;
-    }
-
-    *p_flag = p_dev_info->init_flags[module_id];
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 根据类型获取互斥锁
-* @param   dev_id    设备号
-* @param   type         互斥锁类型，取值参照DPP_DEV_MUTEX_TYPE_E的定义
-* @param   p_mutex_out  返回的互斥锁指针地址
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/10/10
-************************************************************/
-DPP_STATUS dpp_dev_opr_mutex_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 type, ZXIC_MUTEX_T **p_mutex_out)
-{
-    //DPP_STATUS rc = 0;
-    DPP_DEV_MGR_T *p_dev_mgr = NULL;
-    DPP_DEV_CFG_T *p_dev_info = NULL;
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(type, DPP_DEV_MUTEX_T_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_mutex_out);
-
-    p_dev_mgr = dpp_dev_mgr_get();
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
-    p_dev_info = p_dev_mgr->p_dev_array[dev_id];
-
-    if (NULL == p_dev_info)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Get dev_info[ %d ] fail!\n", dev_id);
-        return DPP_DEV_TYPE_INVALID;
-    }
-
-    switch (type)
-    {
-        case DPP_DEV_MUTEX_T_REG:
-        {
-            *p_mutex_out = &(p_dev_info->reg_opr_mutex);
-        }
-        break;
-
-        case DPP_DEV_MUTEX_T_OAM:
-        {
-            *p_mutex_out = &(p_dev_info->oam_mutex);
-        }
-        break;
-
-        case DPP_DEV_MUTEX_T_ETM:
-        {
-            *p_mutex_out = &(p_dev_info->etm_mutex);
-        }
-        break;
-
-        case DPP_DEV_MUTEX_T_DDR:
-        {
-            *p_mutex_out = &(p_dev_info->ddr_mutex);
-        }
-        break;
-
-        case DPP_DEV_MUTEX_T_IND:
-        {
-            *p_mutex_out = &(p_dev_info->ind_mutex);
-        }
-        break;
-
-        case DPP_DEV_MUTEX_T_ETCAM:
-        {
-            *p_mutex_out = &(p_dev_info->etcam_mutex);
-        }
-        break;
-
-        case DPP_DEV_MUTEX_T_CAR0:
-        {
-            *p_mutex_out = &(p_dev_info->car0_mutex);
-        }
-        break;
-
-        case DPP_DEV_MUTEX_T_ALG:
-        {
-            *p_mutex_out = &(p_dev_info->alg_mutex);
-        }
-        break;
-
-        case DPP_DEV_MUTEX_T_NPPU:
-        {
-            *p_mutex_out = &(p_dev_info->nppu_mutex);
-        }
-        break;
-
-        case DPP_DEV_MUTEX_T_SMMU0:
-        {
-            *p_mutex_out = &(p_dev_info->smmu0_mutex);
-        }
-        break;
-
-        case DPP_DEV_MUTEX_T_SMMU1:
-        {
-            *p_mutex_out = &(p_dev_info->smmu1_mutex);
-        }
-        break;
-
-        case DPP_DEV_MUTEX_T_ETM_2ND:
-        {
-            *p_mutex_out = &(p_dev_info->etm_2nd_mutex);
-        }
-        break;
-
-        case DPP_DEV_MUTEX_T_LPM:
-        {
-            *p_mutex_out = &(p_dev_info->lpm_mutex);
-        }
-        break;
-
-        case DPP_DEV_MUTEX_T_CRM_TEMP:
-        {
-            *p_mutex_out = &(p_dev_info->crm_temp_mutex);
-        }
-        break;
-
-        case DPP_DEV_MUTEX_T_SIM:
-        {
-            *p_mutex_out = &(p_dev_info->sim_mutex); 
-        }
-        break;
-
-        case DPP_DEV_MUTEX_T_DTB:
-        {
-            *p_mutex_out = &(p_dev_info->dtb_mutex); 
-        }
-        break;
-
-        default:
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "mutex type is invalid!\n");
-            return DPP_ERR;
-        }
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 根据index获取dtb对应队列的互斥锁
-* @param   dev_id    设备号
-* @param   type         互斥锁类型，取值参照DPP_DEV_MUTEX_TYPE_E的定义
-* @param   p_mutex_out  返回的互斥锁指针地址
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/10/10
-************************************************************/
-DPP_STATUS dpp_dev_dtb_opr_mutex_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 type, ZXIC_UINT32 index, ZXIC_MUTEX_T **p_mutex_out)
-{
-    //DPP_STATUS rc = 0;
-    DPP_DEV_MGR_T *p_dev_mgr = NULL;
-    DPP_DEV_CFG_T *p_dev_info = NULL;
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(type, DPP_DEV_MUTEX_T_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_mutex_out);
-
-    p_dev_mgr = dpp_dev_mgr_get();
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
-    p_dev_info = p_dev_mgr->p_dev_array[dev_id];
-
-    if (NULL == p_dev_info)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Get dev_info[ %d ] fail!\n", dev_id);
-        return DPP_DEV_TYPE_INVALID;
-    }
-
-    switch (type)
-    {
-        case DPP_DEV_MUTEX_T_DTB:
-        {
-            *p_mutex_out = &(p_dev_info->dtb_queue_mutex[index]);
-        }
-        break;
-
-        default:
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "mutex type is invalid!\n");
-            return DPP_ERR;
-        }
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** PCIE 默认读接口
-* @param   dev_id
-* @param   addr
-* @param   size
-* @param   p_data
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2018/05/02
-************************************************************/
-DPP_STATUS dpp_dev_pcie_default_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data)
-{
-    DPP_STATUS rc = 0;
-    ZXIC_UINT32 i;
-    ZXIC_ADDR_T abs_addr = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-
-    abs_addr = DEV_PCIE_REG_ADDR(dev);
-
-#ifdef MACRO_CPU64
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64_NO_ASSERT(DEV_ID(dev), abs_addr, (ZXIC_ADDR_T)addr);
-#else
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), abs_addr, (ZXIC_ADDR_T)addr);
-#endif
-
-#ifdef DPP_FOR_AARCH64
-    addr = addr - (SYS_NP_BASE_ADDR1 - DEV_PCIE_OFFSET_ADDR(dev));
-    addr = X86_ADDR_2_ARRCH64(addr);
-    addr = addr + (SYS_NP_BASE_ADDR1 - DEV_PCIE_OFFSET_ADDR(dev));
-#endif
-
-    abs_addr += addr;
-    ZXIC_COMM_TRACE_DEBUG("dpp_dev_pcie_default_write: write abs_addr:0x%llx\n", abs_addr);
-
-    for (i = 0; i < size; i++)
-    {
-        
-#ifdef MACRO_CPU64
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64_NO_ASSERT(DEV_ID(dev), abs_addr, (ZXIC_ADDR_T)(4 * ((ZXIC_ADDR_T)(i))));
-#else
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), abs_addr, (ZXIC_ADDR_T)(4 * ((ZXIC_ADDR_T)(i))));
-#endif
-
-        rc = dpp_pci_write32(dev, abs_addr + (ZXIC_ADDR_T)(4 * ((ZXIC_ADDR_T)(i))), p_data + i);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_pci_write32");
-        ZXIC_COMM_TRACE_DEBUG("dpp_dev_pcie_default_write: write Addr:0x%llx ,Value 0x%x\n", (abs_addr + (ZXIC_ADDR_T)(4 * ((ZXIC_ADDR_T)(i)))), *(p_data + i));
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** PCIE 默认写接口
-* @param   dev_id
-* @param   addr
-* @param   size
-* @param   p_data
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2018/05/02
-************************************************************/
-DPP_STATUS dpp_dev_pcie_default_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data)
-{
-    DPP_STATUS rc = 0;
-    ZXIC_UINT32 i;
-    ZXIC_ADDR_T abs_addr = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-
-    abs_addr = DEV_PCIE_REG_ADDR(dev);
-
-#ifdef MACRO_CPU64
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64_NO_ASSERT(DEV_ID(dev), abs_addr, (ZXIC_ADDR_T)(addr));
-#else
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), abs_addr, (ZXIC_ADDR_T)(addr));
-#endif
-
-#ifdef DPP_FOR_AARCH64
-    addr = addr - (SYS_NP_BASE_ADDR1 - DEV_PCIE_OFFSET_ADDR(dev));
-    addr = X86_ADDR_2_ARRCH64(addr);
-    addr = addr + (SYS_NP_BASE_ADDR1 - DEV_PCIE_OFFSET_ADDR(dev));
-#endif
-
-    abs_addr += addr;
-
-    for (i = 0; i < size; i++)
-    {
-        rc = dpp_pci_read32(dev, abs_addr + (ZXIC_ADDR_T)(4 * ((ZXIC_ADDR_T)(i))), p_data + i);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_pci_read32");
-
-        ZXIC_COMM_TRACE_DEBUG("dpp_dev_pcie_default_read: Read Addr:0x%llx ,Value 0x%x\n", (abs_addr + (ZXIC_ADDR_T)(4 * ((ZXIC_ADDR_T)(i)))), *(p_data + i));
-    }
-
-    return DPP_OK;
-}
-
-#ifndef ES_FOR_LLT
-/***********************************************************/
-/** 写设备底层接口
-* @param   dev_id  设备号
-* @param   addr       单个设备内部的相对地址
-* @param   size       数据的长度，以32bit为单位
-* @param   p_data     数据
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/05/15
-************************************************************/
-DPP_STATUS dpp_dev_write_channel(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data)
-{
-    /*ZXIC_UINT32     i = 0;*/
-    DPP_STATUS rtn      = 0;
-#if DPP_HW_OPR_EN
-    DPP_DEV_CFG_T *p_dev_info = NULL;
-#endif
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-    
-#ifdef DPP_FOR_LLT
-    rtn = dpp_stump_reg_rb_debug_wr(DEV_ID(dev), 
-                                    addr,
-                                    size,
-                                    p_data);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_stump_reg_rb_debug_wr");
-    return DPP_OK;
-#endif
-
-#if DPP_HW_OPR_EN
-    p_dev_info = DPP_DEV_INFO_GET(DEV_ID(dev));
-
-    if (p_dev_info == NULL)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Error: Channel[%d] dev is not exist!\n ", DEV_ID(dev));
-        return DPP_ERR;
-    }
-    else
-    {
-        if (p_dev_info->access_type == DPP_DEV_ACCESS_TYPE_PCIE)
-        {
-            ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dev_info->p_pcie_write_fun);
-            rtn = p_dev_info->p_pcie_write_fun(dev, addr, size, p_data);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "p_dev_info->p_pcie_write_fun");
-        }
-        else
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Dev access type[ %d ] is invalid!\n", p_dev_info->access_type);
-            return DPP_ERR;
-        }
-    }
-
-#endif
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读设备底层接口
-* @param   dev_id  设备号
-* @param   addr       单个设备内部的相对地址
-* @param   size       数据的长度，以32bit为单位
-* @param   p_data     数据
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/05/15
-************************************************************/
-DPP_STATUS dpp_dev_read_channel(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 size, ZXIC_UINT32 *p_data)
-{
-    DPP_STATUS rtn = 0;
-#if DPP_HW_OPR_EN
-    DPP_DEV_CFG_T *p_dev_info = NULL;
-#endif
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-
-#ifdef DPP_FOR_LLT
-    rtn = dpp_stump_reg_rb_debug_rd(DEV_ID(dev), 
-                                    addr,
-                                    size,
-                                    p_data);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_stump_reg_rb_debug_rd");
-    return DPP_OK;
-#endif
-
-#if DPP_HW_OPR_EN
-    p_dev_info = DPP_DEV_INFO_GET(DEV_ID(dev));
-
-    if (p_dev_info == NULL)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Error: Channel[%d] dev is not exist!\n ", DEV_ID(dev));
-        return DPP_ERR;
-    }
-    else
-    {
-        if (p_dev_info->access_type == DPP_DEV_ACCESS_TYPE_PCIE)
-        {
-            ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dev_info->p_pcie_read_fun);
-            rtn = p_dev_info->p_pcie_read_fun(dev, addr, size, p_data);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "p_dev_info->p_pcie_read_fun");
-        }
-        else
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Dev access type[ %d ] is invalid!\n", p_dev_info->access_type);
-            return DPP_ERR;
-        }
-    }
-
-#else
-
-    for (ZXIC_UINT32 i = 0; i < size; i++)
-    {
-        p_data[i] = 0xffffffff;
-    }
-
-#endif
-
-    return DPP_OK;
-}
-#endif /* ES_FOR_LLT */
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_dev.c
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2014/02/10
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1: 代码规范性修改
+* 修改日期:  2014/02/10
+* 版 本 号:
+* 修 改 人:  丁金凤
+* 修改内容:
+***************************************************************/
+
+#include "zxic_common.h"
+#include "dpp_module.h"
+#include "dpp_pci.h"
+#include "dpp_dev.h"
+#include "dpp_type_api.h"
+#include "dh_cmd.h"
+
+static DPP_DEV_MGR_T g_dev_mgr = { 0 };
+
+#define DPP_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id])
+
+/***********************************************************/
+/** 初始化设备管理模块
+ * @param   ZXIC_VOID
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/03/06
+ ************************************************************/
+DPP_STATUS dpp_dev_init(ZXIC_VOID)
+{
+	if (g_dev_mgr.is_init) {
+		ZXIC_COMM_TRACE_ERROR("Dev is already initialized.\n");
+		return DPP_OK;
+	}
+
+	g_dev_mgr.device_num = 0;
+	g_dev_mgr.is_init = 1;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**
+ * @return
+ * @remark  无
+ * @see
+ * @author  XXX      @date  2014/02/14
+ ************************************************************/
+DPP_DEV_MGR_T *dpp_dev_mgr_get(ZXIC_VOID)
+{
+	if (!g_dev_mgr.is_init) {
+		ZXIC_COMM_TRACE_ERROR("Error: dev_mgr is not init.\n");
+		ZXIC_COMM_ASSERT(0);
+		return NULL;
+	}
+
+	return &g_dev_mgr;
+}
+
+/***********************************************************/
+/** 添加新设备实例，并初始化
+ * @param   dev_id         新增设备的设备号
+ * @param   dev_type          设备类型，取值参照DPP_DEV_TYPE_E的定义
+ * @param   access_type       设备访问类型，取值参照DPP_DEV_ACCESS_TYPE_E的定义
+ * @param   pcie_addr         PCIe映射地址
+ * @param   riscv_addr         RISCV映射地址
+ * @param   dma_vir_addr      DMA映射地址
+ * @param   dma_phy_addr      DMA内存物理地址
+ * @param   p_pcie_write_fun  PCIe硬件写回调函数
+ * @param   p_pcie_read_fun   PCIe硬件读回调函数
+ * @param   p_riscv_write_fun  RISCV硬件写回调函数
+ * @param   p_riscv_read_fun   RISCV硬件读回调函数
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/03/06
+ ************************************************************/
+DPP_STATUS dpp_dev_add(ZXIC_UINT32 dev_id, DPP_DEV_TYPE_E dev_type,
+					   DPP_DEV_ACCESS_TYPE_E access_type, ZXIC_ADDR_T pcie_addr,
+					   ZXIC_ADDR_T riscv_addr, ZXIC_ADDR_T dma_vir_addr,
+					   ZXIC_ADDR_T dma_phy_addr,
+					   DPP_DEV_WRITE_FUNC p_pcie_write_fun,
+					   DPP_DEV_READ_FUNC p_pcie_read_fun,
+					   DPP_DEV_WRITE_FUNC p_riscv_write_fun,
+					   DPP_DEV_READ_FUNC p_riscv_read_fun)
+{
+	DPP_STATUS rtn = DPP_OK;
+	DPP_DEV_CFG_T *p_dev_info = NULL;
+	DPP_DEV_MGR_T *p_dev_mgr = NULL;
+	ZXIC_UINT32 i = 0;
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+
+	p_dev_mgr = dpp_dev_mgr_get();
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
+	if (!p_dev_mgr->is_init) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id, "ErrorCode[ 0x%x]: Device Manager is not init!!!\n",
+				DPP_RC_DEV_MGR_NOT_INIT);
+		return DPP_RC_DEV_MGR_NOT_INIT;
+	}
+
+	if (p_dev_mgr->p_dev_array[dev_id] != NULL) {
+		/* device is already exist. */
+		ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Device is added again!!!\n");
+		p_dev_info = p_dev_mgr->p_dev_array[dev_id];
+	} else {
+		/* device is new. */
+		p_dev_info = (DPP_DEV_CFG_T *)ZXIC_COMM_MALLOC(sizeof(DPP_DEV_CFG_T));
+		ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info);
+		p_dev_mgr->p_dev_array[dev_id] = p_dev_info;
+		p_dev_mgr->device_num++;
+	}
+
+	p_dev_info->device_id = dev_id;
+	p_dev_info->dev_type = dev_type;
+	p_dev_info->access_type = access_type;
+	p_dev_info->pcie_addr = pcie_addr;
+	p_dev_info->riscv_addr = riscv_addr;
+	p_dev_info->dma_vir_addr = dma_vir_addr;
+	p_dev_info->dma_phy_addr = dma_phy_addr;
+	p_dev_info->p_riscv_write_fun = NULL;
+	p_dev_info->p_riscv_read_fun = NULL;
+	p_dev_info->p_pcie_write_fun = dpp_dev_pcie_default_write;
+	p_dev_info->p_pcie_read_fun = dpp_dev_pcie_default_read;
+
+	if (p_riscv_write_fun) {
+		p_dev_info->p_riscv_write_fun = p_riscv_write_fun;
+	}
+
+	if (p_riscv_read_fun) {
+		p_dev_info->p_riscv_read_fun = p_riscv_read_fun;
+	}
+
+	if (p_pcie_write_fun) {
+		p_dev_info->p_pcie_write_fun = p_pcie_write_fun;
+	}
+
+	if (p_pcie_read_fun) {
+		p_dev_info->p_pcie_read_fun = p_pcie_read_fun;
+	}
+
+	if (dev_type == DPP_DEV_TYPE_CHIP) {
+		p_dev_info->chip_ver = dpp_dev_chip_version_get(dev_id);
+	} else if ((dev_type == DPP_DEV_TYPE_SIM) ||
+			   (dev_type == DPP_DEV_TYPE_VCS)) {
+		// p_dev_info->chip_ver = dpp_vpci_get_chip_version();
+	}
+
+	ZXIC_COMM_MEMSET(p_dev_info->pcie_channel, 0x00,
+					 sizeof(p_dev_info->pcie_channel));
+
+	rtn = zxic_comm_mutex_create(&p_dev_info->reg_opr_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+
+	rtn = zxic_comm_mutex_create(&p_dev_info->oam_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+
+	rtn = zxic_comm_mutex_create(&p_dev_info->etm_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+
+	rtn = zxic_comm_mutex_create(&p_dev_info->ddr_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+
+	rtn = zxic_comm_mutex_create(&p_dev_info->ind_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+
+	rtn = zxic_comm_mutex_create(&p_dev_info->etcam_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+
+	rtn = zxic_comm_mutex_create(&p_dev_info->car0_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+
+	rtn = zxic_comm_mutex_create(&p_dev_info->alg_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+
+	rtn = zxic_comm_mutex_create(&p_dev_info->nppu_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+
+	rtn = zxic_comm_mutex_create(&p_dev_info->smmu0_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+
+	rtn = zxic_comm_mutex_create(&p_dev_info->smmu1_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+
+	rtn = zxic_comm_mutex_create(&p_dev_info->etm_2nd_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+
+	rtn = zxic_comm_mutex_create(&p_dev_info->lpm_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+
+	rtn = zxic_comm_mutex_create(&p_dev_info->crm_temp_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+
+	rtn = zxic_comm_mutex_create(&p_dev_info->sim_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+
+	rtn = zxic_comm_mutex_create(&p_dev_info->dtb_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+
+	for (i = 0; i < DPP_DTB_QUEUE_MAX; i++) {
+		rtn = zxic_comm_mutex_create(&p_dev_info->dtb_queue_mutex[i]);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_create");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 删除设备实例
+ * @param   dev_id  设备号
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/05/20
+ ************************************************************/
+DPP_STATUS dpp_dev_del(ZXIC_UINT32 dev_id)
+{
+	DPP_STATUS rtn = DPP_OK;
+	DPP_DEV_CFG_T *p_dev_info = NULL;
+	DPP_DEV_MGR_T *p_dev_mgr = NULL;
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+
+	p_dev_mgr = dpp_dev_mgr_get();
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
+	p_dev_info = p_dev_mgr->p_dev_array[dev_id];
+
+	if (p_dev_info != NULL) {
+		rtn = zxic_comm_mutex_destroy(&p_dev_info->reg_opr_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
+
+		rtn = zxic_comm_mutex_destroy(&p_dev_info->oam_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
+
+		rtn = zxic_comm_mutex_destroy(&p_dev_info->etm_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
+
+		rtn = zxic_comm_mutex_destroy(&p_dev_info->ddr_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
+
+		rtn = zxic_comm_mutex_destroy(&p_dev_info->ind_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
+
+		rtn = zxic_comm_mutex_destroy(&p_dev_info->etcam_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
+
+		rtn = zxic_comm_mutex_destroy(&p_dev_info->car0_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
+
+		rtn = zxic_comm_mutex_destroy(&p_dev_info->alg_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
+
+		rtn = zxic_comm_mutex_destroy(&p_dev_info->nppu_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
+
+		rtn = zxic_comm_mutex_destroy(&p_dev_info->smmu0_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
+
+		rtn = zxic_comm_mutex_destroy(&p_dev_info->smmu1_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
+
+		rtn = zxic_comm_mutex_destroy(&p_dev_info->etm_2nd_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
+
+		rtn = zxic_comm_mutex_destroy(&p_dev_info->lpm_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
+
+		rtn = zxic_comm_mutex_destroy(&p_dev_info->crm_temp_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "zxic_comm_mutex_destroy");
+
+		ZXIC_COMM_FREE(p_dev_info);
+		p_dev_mgr->p_dev_array[dev_id] = NULL;
+		ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(
+				dev_id, p_dev_mgr->device_num, 1);
+		p_dev_mgr->device_num--;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取 DPP_DEV_T
+ * @param   dev_id
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/05/20
+ ************************************************************/
+DPP_STATUS dpp_dev_get(ZXIC_UINT32 dev_id, DPP_PF_INFO_T *pf_info,
+					   DPP_DEV_T *dev)
+{
+	ZXIC_UINT16 slot = 0;
+	ZXIC_UINT16 channel_id = 0;
+
+	DPP_DEV_CFG_T *p_dev_info = NULL;
+	DPP_DEV_MGR_T *p_dev_mgr = NULL;
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, pf_info);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, dev);
+
+	slot = pf_info->slot;
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, slot, 0, DPP_PCIE_SLOT_MAX - 1);
+
+	channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
+
+	p_dev_mgr = dpp_dev_mgr_get();
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
+	if (!p_dev_mgr->is_init) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id, "ErrorCode[ 0x%x]: Device Manager is not init!!!\n",
+				DPP_RC_DEV_MGR_NOT_INIT);
+		return DPP_RC_DEV_MGR_NOT_INIT;
+	}
+	p_dev_info = p_dev_mgr->p_dev_array[dev_id];
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info);
+
+	ZXIC_COMM_CHECK_DEV_POINT(
+			dev_id, p_dev_info->pcie_channel[slot][channel_id].device);
+	ZXIC_COMM_CHECK_DEV_POINT(
+			dev_id, p_dev_info->pcie_channel[slot][channel_id].oper_mutex);
+
+	dev->device_id = p_dev_info->device_id;
+	dev->pcie_channel.slot = p_dev_info->pcie_channel[slot][channel_id].slot;
+	dev->pcie_channel.vport = p_dev_info->pcie_channel[slot][channel_id].vport;
+	dev->pcie_channel.pcie_id =
+			p_dev_info->pcie_channel[slot][channel_id].pcie_id;
+	dev->pcie_channel.device =
+			p_dev_info->pcie_channel[slot][channel_id].device;
+	dev->pcie_channel.base_addr =
+			p_dev_info->pcie_channel[slot][channel_id].base_addr;
+	dev->pcie_channel.offset_addr =
+			p_dev_info->pcie_channel[slot][channel_id].offset_addr;
+	dev->pcie_channel.oper_mutex =
+			p_dev_info->pcie_channel[slot][channel_id].oper_mutex;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**
+ * @param   dev_id         设备的设备号
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/03/06
+ ************************************************************/
+DPP_STATUS dpp_dev_pcie_channel_add(ZXIC_UINT32 dev_id, DPP_PF_INFO_T *pf_info,
+									struct pci_dev *p_dev)
+{
+	DPP_STATUS rc = 0;
+	ZXIC_VOID *base_addr = 0;
+	ZXIC_UINT8 type = 0;
+	ZXIC_UINT32 post = 0;
+	ZXIC_UINT16 pcie_id = 0;
+	ZXIC_UINT16 slot = 0;
+	ZXIC_UINT16 channel_id = 0;
+	DPP_DEV_CFG_T *p_dev_info = NULL;
+	DPP_DEV_MGR_T *p_dev_mgr = NULL;
+
+#ifdef DPP_FLOW_HW_INIT
+	struct bar_offset_res res;
+	struct bar_offset_params paras;
+#endif
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, pf_info);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev);
+
+	slot = pf_info->slot;
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, slot, 0, DPP_PCIE_SLOT_MAX - 1);
+
+	channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
+
+	p_dev_mgr = dpp_dev_mgr_get();
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
+	if (!p_dev_mgr->is_init) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id, "ErrorCode[ 0x%x]: Device Manager is not init!!!\n",
+				DPP_RC_DEV_MGR_NOT_INIT);
+		return DPP_RC_DEV_MGR_NOT_INIT;
+	}
+	p_dev_info = p_dev_mgr->p_dev_array[dev_id];
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info);
+
+	if (p_dev_info->pcie_channel[slot][channel_id].device != NULL) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id,
+				"ErrorCode[ 0x%x]: pcie slot %u vport 0x%04x already init.\n",
+				DPP_RC_DEV_PARA_INVALID, slot, pf_info->vport);
+		return DPP_RC_DEV_PARA_INVALID;
+	}
+
+	base_addr =
+			ioremap(pci_resource_start(p_dev, 0), pci_resource_len(p_dev, 0));
+	if (IS_ERR_OR_NULL(base_addr)) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id,
+				"ErrorCode[ 0x%x]: pcie slot %u vport 0x%04x ioremap failed.\n",
+				DPP_RC_DEV_PARA_INVALID, slot, pf_info->vport);
+		return DPP_RC_DEV_PARA_INVALID;
+	}
+
+	for (post = pci_find_capability(p_dev, PCI_CAP_ID_VNDR); post > 0;
+		 post = pci_find_next_capability(p_dev, post, PCI_CAP_ID_VNDR)) {
+		pci_read_config_byte(p_dev, post + 3, &type);
+
+		if (type == 5) {
+			pci_read_config_word(p_dev, post + 6, &pcie_id);
+		}
+	}
+
+	if (pcie_id == 0) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id,
+				"ErrorCode[ 0x%x]: pcie slot %u vport 0x%04x get pcieid failed.\n",
+				DPP_RC_DEV_PARA_INVALID, slot, pf_info->vport);
+		return DPP_RC_DEV_PARA_INVALID;
+	}
+
+#ifdef DPP_FLOW_HW_INIT
+	paras.type = URI_NP;
+	paras.pcie_id = pcie_id;
+	paras.virt_addr =
+			ZXIC_COMM_PTR_TO_VAL(base_addr) + DEV_PCIE_MSG_OFFSET_ADDR;
+	if (zxdh_get_bar_offset(&paras, &res) != BAR_MSG_OK) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id,
+				"ErrorCode[ 0x%x]: pcie slot %u vport 0x%04x get bar offset failed.\n",
+				DPP_RC_DEV_PARA_INVALID, slot, pf_info->vport);
+		return DPP_RC_DEV_PARA_INVALID;
+	}
+#endif
+	p_dev_info->pcie_channel[slot][channel_id].slot = slot;
+	p_dev_info->pcie_channel[slot][channel_id].vport = pf_info->vport;
+	p_dev_info->pcie_channel[slot][channel_id].pcie_id = pcie_id;
+	p_dev_info->pcie_channel[slot][channel_id].device = p_dev;
+	p_dev_info->pcie_channel[slot][channel_id].base_addr =
+			ZXIC_COMM_PTR_TO_VAL(base_addr);
+
+#ifdef DPP_FLOW_HW_INIT
+	p_dev_info->pcie_channel[slot][channel_id].offset_addr = res.bar_offset;
+#else
+	p_dev_info->pcie_channel[slot][channel_id].offset_addr = 0x6000;
+#endif
+
+	p_dev_info->pcie_channel[slot][channel_id].oper_mutex =
+			ZXIC_COMM_MALLOC(sizeof(ZXIC_MUTEX_T));
+	rc = zxic_comm_mutex_create(
+			p_dev_info->pcie_channel[slot][channel_id].oper_mutex);
+	ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE(
+			dev_id, rc, "zxic_comm_mutex_create",
+			p_dev_info->pcie_channel[slot][channel_id].oper_mutex);
+
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x base_addr: 0x%llx success.\n",
+					__FUNCTION__, slot, pf_info->vport, base_addr);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x pcie_id: 0x%04x offset_addr: 0x%llx success.\n",
+			__FUNCTION__, slot, pf_info->vport, pcie_id,
+			p_dev_info->pcie_channel[slot][channel_id].offset_addr);
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**
+ * @param   dev_id         设备的设备号
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/03/06
+ ************************************************************/
+DPP_STATUS dpp_dev_pcie_channel_del(ZXIC_UINT32 dev_id, DPP_PF_INFO_T *pf_info)
+{
+	DPP_STATUS rc = 0;
+	ZXIC_UINT16 slot = 0;
+	ZXIC_UINT16 channel_id = 0;
+	DPP_DEV_CFG_T *p_dev_info = NULL;
+	DPP_DEV_MGR_T *p_dev_mgr = NULL;
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, pf_info);
+
+	slot = pf_info->slot;
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, slot, 0, DPP_PCIE_SLOT_MAX - 1);
+
+	channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
+
+	p_dev_mgr = dpp_dev_mgr_get();
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
+	if (!p_dev_mgr->is_init) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id, "ErrorCode[ 0x%x]: Device Manager is not init!!!\n",
+				DPP_RC_DEV_MGR_NOT_INIT);
+		return DPP_RC_DEV_MGR_NOT_INIT;
+	}
+	p_dev_info = p_dev_mgr->p_dev_array[dev_id];
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_info);
+
+	ZXIC_COMM_CHECK_DEV_POINT(
+			dev_id, p_dev_info->pcie_channel[slot][channel_id].device);
+	ZXIC_COMM_CHECK_DEV_POINT(
+			dev_id, p_dev_info->pcie_channel[slot][channel_id].oper_mutex);
+
+	rc = zxic_comm_mutex_destroy(
+			p_dev_info->pcie_channel[slot][channel_id].oper_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_mutex_destroy");
+	ZXIC_COMM_FREE(p_dev_info->pcie_channel[slot][channel_id].oper_mutex);
+
+	iounmap((ZXIC_VOID *)p_dev_info->pcie_channel[slot][channel_id].base_addr);
+
+	p_dev_info->pcie_channel[slot][channel_id].device = NULL;
+	p_dev_info->pcie_channel[slot][channel_id].slot = 0;
+	p_dev_info->pcie_channel[slot][channel_id].vport = 0;
+	p_dev_info->pcie_channel[slot][channel_id].pcie_id = 0;
+	p_dev_info->pcie_channel[slot][channel_id].base_addr = 0;
+	p_dev_info->pcie_channel[slot][channel_id].offset_addr = 0;
+
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					slot, pf_info->vport);
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取设备类型
+ * @param   dev_id  设备号
+ *
+ * @return  设备类型，参考DPP_DEV_TYPE_E的定义
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/03/06
+ ************************************************************/
+ZXIC_UINT32 dpp_dev_get_dev_type(ZXIC_UINT32 dev_id)
+{
+	DPP_DEV_MGR_T *p_dev_mgr = NULL;
+	DPP_DEV_CFG_T *p_dev_info = NULL;
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+
+	p_dev_mgr = dpp_dev_mgr_get();
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
+
+	p_dev_info = p_dev_mgr->p_dev_array[dev_id];
+
+	if (NULL == p_dev_info) {
+		return DPP_DEV_TYPE_INVALID;
+	}
+
+	return (p_dev_info->dev_type);
+}
+
+/***********************************************************/
+/** 获取芯片类型
+ * @param   dev_id
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  lfq      @date  2014/03/05
+ ************************************************************/
+ZXIC_UINT32 dpp_dev_chip_version_get(ZXIC_UINT32 dev_id)
+{
+	ZXIC_UINT32 device_no = 0;
+	ZXIC_UINT32 chip_ver = 0;
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+
+	if (device_no == DPP_CHIP_DPP) {
+		chip_ver = DPP_CHIP_VERSION_DPP_P;
+	} else {
+		// ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Device id [0x%08x] is wrong\n", device_no);
+	}
+
+	return chip_ver;
+}
+
+/***********************************************************/
+/** 每个模块的初始化标记设置接口
+ * @param   dev_id    设备号
+ * @param   module_id 模块ID, 见MODULE_INIT_E
+ * @param   flag      31bit代表整体初始化状态(1:完成 0:未完成或未开始)，其余31bit自由利用，可以按子模块的初始化状态赋值
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  初始化标记主要用于记录本模块的初始化状态
+ * @see
+ * @author  xjw      @date  2019/10/30
+ ************************************************************/
+DPP_STATUS dpp_dev_init_flag_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id,
+								 ZXIC_UINT32 flag)
+{
+	DPP_DEV_CFG_T *p_dev_info = NULL;
+	DPP_DEV_MGR_T *p_dev_mgr = NULL;
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, module_id, MODULE_INIT_NPPU,
+							  MODULE_INIT_MAX - 1);
+
+	p_dev_mgr = dpp_dev_mgr_get();
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
+	p_dev_info = p_dev_mgr->p_dev_array[dev_id];
+
+	if (NULL == p_dev_info) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id, "ErrorCode[ 0x%x]: Device CFG is not init!!!\n",
+				DPP_RC_DEV_CFG_NOT_INIT);
+		return DPP_RC_DEV_CFG_NOT_INIT;
+	}
+
+	p_dev_info->init_flags[module_id] = flag;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 每个模块的初始化标记获取接口
+ * @param   dev_id    设备号
+ * @param   module_id 模块ID, 见MODULE_INIT_E
+ * @param   p_flag    按ZXIC_UINT32返回，bit处理各模块自行完成
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  初始化标记主要用于记录本模块的初始化状态
+ * @see
+ * @author  xjw      @date  2019/10/30
+ ************************************************************/
+DPP_STATUS dpp_dev_init_flag_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id,
+								 ZXIC_UINT32 *p_flag)
+{
+	DPP_DEV_CFG_T *p_dev_info = NULL;
+	DPP_DEV_MGR_T *p_dev_mgr = NULL;
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, module_id, MODULE_INIT_NPPU,
+							  MODULE_INIT_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_flag);
+
+	p_dev_mgr = dpp_dev_mgr_get();
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
+	p_dev_info = p_dev_mgr->p_dev_array[dev_id];
+
+	if (NULL == p_dev_info) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id, "ErrorCode[ 0x%x]: Device CFG is not init!!!\n",
+				DPP_RC_DEV_CFG_NOT_INIT);
+		return DPP_RC_DEV_CFG_NOT_INIT;
+	}
+
+	*p_flag = p_dev_info->init_flags[module_id];
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 根据类型获取互斥锁
+ * @param   dev_id    设备号
+ * @param   type         互斥锁类型，取值参照DPP_DEV_MUTEX_TYPE_E的定义
+ * @param   p_mutex_out  返回的互斥锁指针地址
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/10/10
+ ************************************************************/
+DPP_STATUS dpp_dev_opr_mutex_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 type,
+								 ZXIC_MUTEX_T **p_mutex_out)
+{
+	// DPP_STATUS rc = 0;
+	DPP_DEV_MGR_T *p_dev_mgr = NULL;
+	DPP_DEV_CFG_T *p_dev_info = NULL;
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(type, DPP_DEV_MUTEX_T_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_mutex_out);
+
+	p_dev_mgr = dpp_dev_mgr_get();
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
+	p_dev_info = p_dev_mgr->p_dev_array[dev_id];
+
+	if (NULL == p_dev_info) {
+		ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Get dev_info[ %d ] fail!\n", dev_id);
+		return DPP_DEV_TYPE_INVALID;
+	}
+
+	switch (type) {
+	case DPP_DEV_MUTEX_T_REG: {
+		*p_mutex_out = &(p_dev_info->reg_opr_mutex);
+	} break;
+
+	case DPP_DEV_MUTEX_T_OAM: {
+		*p_mutex_out = &(p_dev_info->oam_mutex);
+	} break;
+
+	case DPP_DEV_MUTEX_T_ETM: {
+		*p_mutex_out = &(p_dev_info->etm_mutex);
+	} break;
+
+	case DPP_DEV_MUTEX_T_DDR: {
+		*p_mutex_out = &(p_dev_info->ddr_mutex);
+	} break;
+
+	case DPP_DEV_MUTEX_T_IND: {
+		*p_mutex_out = &(p_dev_info->ind_mutex);
+	} break;
+
+	case DPP_DEV_MUTEX_T_ETCAM: {
+		*p_mutex_out = &(p_dev_info->etcam_mutex);
+	} break;
+
+	case DPP_DEV_MUTEX_T_CAR0: {
+		*p_mutex_out = &(p_dev_info->car0_mutex);
+	} break;
+
+	case DPP_DEV_MUTEX_T_ALG: {
+		*p_mutex_out = &(p_dev_info->alg_mutex);
+	} break;
+
+	case DPP_DEV_MUTEX_T_NPPU: {
+		*p_mutex_out = &(p_dev_info->nppu_mutex);
+	} break;
+
+	case DPP_DEV_MUTEX_T_SMMU0: {
+		*p_mutex_out = &(p_dev_info->smmu0_mutex);
+	} break;
+
+	case DPP_DEV_MUTEX_T_SMMU1: {
+		*p_mutex_out = &(p_dev_info->smmu1_mutex);
+	} break;
+
+	case DPP_DEV_MUTEX_T_ETM_2ND: {
+		*p_mutex_out = &(p_dev_info->etm_2nd_mutex);
+	} break;
+
+	case DPP_DEV_MUTEX_T_LPM: {
+		*p_mutex_out = &(p_dev_info->lpm_mutex);
+	} break;
+
+	case DPP_DEV_MUTEX_T_CRM_TEMP: {
+		*p_mutex_out = &(p_dev_info->crm_temp_mutex);
+	} break;
+
+	case DPP_DEV_MUTEX_T_SIM: {
+		*p_mutex_out = &(p_dev_info->sim_mutex);
+	} break;
+
+	case DPP_DEV_MUTEX_T_DTB: {
+		*p_mutex_out = &(p_dev_info->dtb_mutex);
+	} break;
+
+	default: {
+		ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "mutex type is invalid!\n");
+		return DPP_ERR;
+	}
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 根据index获取dtb对应队列的互斥锁
+ * @param   dev_id    设备号
+ * @param   type         互斥锁类型，取值参照DPP_DEV_MUTEX_TYPE_E的定义
+ * @param   p_mutex_out  返回的互斥锁指针地址
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/10/10
+ ************************************************************/
+DPP_STATUS dpp_dev_dtb_opr_mutex_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 type,
+									 ZXIC_UINT32 index,
+									 ZXIC_MUTEX_T **p_mutex_out)
+{
+	// DPP_STATUS rc = 0;
+	DPP_DEV_MGR_T *p_dev_mgr = NULL;
+	DPP_DEV_CFG_T *p_dev_info = NULL;
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(type, DPP_DEV_MUTEX_T_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_mutex_out);
+
+	p_dev_mgr = dpp_dev_mgr_get();
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dev_mgr);
+	p_dev_info = p_dev_mgr->p_dev_array[dev_id];
+
+	if (NULL == p_dev_info) {
+		ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Get dev_info[ %d ] fail!\n", dev_id);
+		return DPP_DEV_TYPE_INVALID;
+	}
+
+	switch (type) {
+	case DPP_DEV_MUTEX_T_DTB: {
+		*p_mutex_out = &(p_dev_info->dtb_queue_mutex[index]);
+	} break;
+
+	default: {
+		ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "mutex type is invalid!\n");
+		return DPP_ERR;
+	}
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** PCIE 默认读接口
+ * @param   dev_id
+ * @param   addr
+ * @param   size
+ * @param   p_data
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XXX      @date  2018/05/02
+ ************************************************************/
+DPP_STATUS dpp_dev_pcie_default_write(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+									  ZXIC_UINT32 size, ZXIC_UINT32 *p_data)
+{
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 i;
+	ZXIC_ADDR_T abs_addr = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+
+	abs_addr = DEV_PCIE_REG_ADDR(dev);
+
+#ifdef MACRO_CPU64
+	ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64_NO_ASSERT(DEV_ID(dev), abs_addr,
+														addr);
+#else
+	ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), abs_addr,
+													 addr);
+#endif
+
+#ifdef DPP_FOR_AARCH64
+	addr = addr - (SYS_NP_BASE_ADDR1 - DEV_PCIE_OFFSET_ADDR(dev));
+	addr = X86_ADDR_2_ARRCH64(addr);
+	addr = addr + (SYS_NP_BASE_ADDR1 - DEV_PCIE_OFFSET_ADDR(dev));
+#endif
+
+	abs_addr += addr;
+	ZXIC_COMM_TRACE_DEBUG("dpp_dev_pcie_default_write: write abs_addr:0x%llx\n",
+						  abs_addr);
+
+	for (i = 0; i < size; i++) {
+#ifdef MACRO_CPU64
+		ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64_NO_ASSERT(DEV_ID(dev),
+															abs_addr, 4 * i);
+#else
+		ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), abs_addr,
+														 4 * i);
+#endif
+
+		rc = dpp_pci_write32(dev, abs_addr + 4 * i, p_data + i);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_pci_write32");
+		ZXIC_COMM_TRACE_DEBUG(
+				"dpp_dev_pcie_default_write: write Addr:0x%llx ,Value 0x%x\n",
+				(abs_addr + 4 * i), *(p_data + i));
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** PCIE 默认写接口
+ * @param   dev_id
+ * @param   addr
+ * @param   size
+ * @param   p_data
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XXX      @date  2018/05/02
+ ************************************************************/
+DPP_STATUS dpp_dev_pcie_default_read(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+									 ZXIC_UINT32 size, ZXIC_UINT32 *p_data)
+{
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 i;
+	ZXIC_ADDR_T abs_addr = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+
+	abs_addr = DEV_PCIE_REG_ADDR(dev);
+
+#ifdef MACRO_CPU64
+	ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_64_NO_ASSERT(DEV_ID(dev), abs_addr,
+														addr);
+#else
+	ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), abs_addr,
+													 addr);
+#endif
+
+#ifdef DPP_FOR_AARCH64
+	addr = addr - (SYS_NP_BASE_ADDR1 - DEV_PCIE_OFFSET_ADDR(dev));
+	addr = X86_ADDR_2_ARRCH64(addr);
+	addr = addr + (SYS_NP_BASE_ADDR1 - DEV_PCIE_OFFSET_ADDR(dev));
+#endif
+
+	abs_addr += addr;
+
+	for (i = 0; i < size; i++) {
+		rc = dpp_pci_read32(dev, abs_addr + 4 * i, p_data + i);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_pci_read32");
+
+		ZXIC_COMM_TRACE_DEBUG(
+				"dpp_dev_pcie_default_read: Read Addr:0x%llx ,Value 0x%x\n",
+				(abs_addr + 4 * i), *(p_data + i));
+	}
+
+	return DPP_OK;
+}
+
+#ifndef ES_FOR_LLT
+/***********************************************************/
+/** 写设备底层接口
+ * @param   dev_id  设备号
+ * @param   addr       单个设备内部的相对地址
+ * @param   size       数据的长度，以32bit为单位
+ * @param   p_data     数据
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/05/15
+ ************************************************************/
+DPP_STATUS dpp_dev_write_channel(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+								 ZXIC_UINT32 size, ZXIC_UINT32 *p_data)
+{
+	/*ZXIC_UINT32     i = 0;*/
+	DPP_STATUS rtn = 0;
+#if DPP_HW_OPR_EN
+	DPP_DEV_CFG_T *p_dev_info = NULL;
+#endif
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+
+#if DPP_HW_OPR_EN
+	p_dev_info = DPP_DEV_INFO_GET(DEV_ID(dev));
+
+	if (p_dev_info == NULL) {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+								  "Error: Channel[%d] dev is not exist!\n ",
+								  DEV_ID(dev));
+		return DPP_ERR;
+	} else {
+		if (p_dev_info->access_type == DPP_DEV_ACCESS_TYPE_PCIE) {
+			ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev),
+									  p_dev_info->p_pcie_write_fun);
+			rtn = p_dev_info->p_pcie_write_fun(dev, addr, size, p_data);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn,
+								   "p_dev_info->p_pcie_write_fun");
+		} else {
+			ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+									  "Dev access type[ %d ] is invalid!\n",
+									  p_dev_info->access_type);
+			return DPP_ERR;
+		}
+	}
+
+#endif
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读设备底层接口
+ * @param   dev_id  设备号
+ * @param   addr       单个设备内部的相对地址
+ * @param   size       数据的长度，以32bit为单位
+ * @param   p_data     数据
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/05/15
+ ************************************************************/
+DPP_STATUS dpp_dev_read_channel(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+								ZXIC_UINT32 size, ZXIC_UINT32 *p_data)
+{
+	DPP_STATUS rtn = 0;
+#if DPP_HW_OPR_EN
+	DPP_DEV_CFG_T *p_dev_info = NULL;
+#endif
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+
+#if DPP_HW_OPR_EN
+	p_dev_info = DPP_DEV_INFO_GET(DEV_ID(dev));
+
+	if (p_dev_info == NULL) {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+								  "Error: Channel[%d] dev is not exist!\n ",
+								  DEV_ID(dev));
+		return DPP_ERR;
+	} else {
+		if (p_dev_info->access_type == DPP_DEV_ACCESS_TYPE_PCIE) {
+			ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dev_info->p_pcie_read_fun);
+			rtn = p_dev_info->p_pcie_read_fun(dev, addr, size, p_data);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn,
+								   "p_dev_info->p_pcie_read_fun");
+		} else {
+			ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+									  "Dev access type[ %d ] is invalid!\n",
+									  p_dev_info->access_type);
+			return DPP_ERR;
+		}
+	}
+
+#else
+
+	for (ZXIC_UINT32 i = 0; i < size; i++) {
+		p_data[i] = 0xffffffff;
+	}
+
+#endif
+
+	return DPP_OK;
+}
+#endif /* ES_FOR_LLT */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/dpp_init.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/dpp_init.c
old mode 100755
new mode 100644
index 918d463e7171821591f37d5add53c674a0e1d494..32ad9a1520af20211928ca0720ec959de281591a
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/dpp_init.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/chip/dpp_init.c
@@ -1,73 +1,67 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_init.c
-* 文件标识 :
-* 内容摘要 : 芯片初始化源文件
-* 其它说明 :
-* 当前版本 :
-* 作    者 : 王春雷
-* 完成日期 : 2015/03/17
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-
-#include "zxic_common.h"
-#include "dpp_module.h"
-#include "dpp_dev.h"
-#include "dpp_ppu.h"
-#include "dpp_se.h"
-#include "dpp_dtb.h"
-#include "dpp_init.h"
-
-/***********************************************************/
-/** 芯片上电初始，完整版本
-* @param   dev_id    设备号
-* @param   p_init_ctrl  系统初始化控制数据结构，由用户完成实例化和成员赋值
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/03/26
-************************************************************/
-DPP_STATUS dpp_init(ZXIC_UINT32 dev_id, DPP_SYS_INIT_CTRL_T *p_init_ctrl)
-{
-    DPP_STATUS rt = 0;
-    ZXIC_UINT32 access_type = 0;
-    ZXIC_UINT32 dev_id_array[DPP_DEV_CHANNEL_MAX] = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_init_ctrl);
-
-    /* 初始化设备管理模块 */
-    rt = dpp_dev_init();
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rt, "dpp_dev_init");
-
-    rt = dpp_dev_add(dev_id,
-                     p_init_ctrl->device_type,
-                     access_type,
-                     p_init_ctrl->pcie_vir_baddr,
-                     p_init_ctrl->riscv_vir_baddr,
-                     p_init_ctrl->dma_vir_baddr,
-                     p_init_ctrl->dma_phy_baddr,
-                     p_init_ctrl->pcie_write_fun,
-                     p_init_ctrl->pcie_read_fun,
-                     p_init_ctrl->riscv_write_fun,
-                     p_init_ctrl->riscv_read_fun);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rt, "dpp_dev_add");
-
-    /* 初始化table模块软件部分 */
-    dev_id_array[0] = dev_id;
-    rt = dpp_sdt_init(1, dev_id_array);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rt, "dpp_sdt_init");
-
-    rt = dpp_ppu_parse_cls_bitmap(dev_id, DPP_PPU_CLS_ALL_START);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rt, "dpp_ppu_parse_cls_bitmap");
-    
-    return DPP_OK;
-}
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_init.c
+* 文件标识 :
+* 内容摘要 : 芯片初始化源文件
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2015/03/17
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#include "zxic_common.h"
+#include "dpp_module.h"
+#include "dpp_dev.h"
+#include "dpp_ppu.h"
+#include "dpp_se.h"
+#include "dpp_dtb.h"
+#include "dpp_init.h"
+
+/***********************************************************/
+/** 芯片上电初始，完整版本
+ * @param   dev_id    设备号
+ * @param   p_init_ctrl  系统初始化控制数据结构，由用户完成实例化和成员赋值
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/03/26
+ ************************************************************/
+DPP_STATUS dpp_init(ZXIC_UINT32 dev_id, DPP_SYS_INIT_CTRL_T *p_init_ctrl)
+{
+	DPP_STATUS rt = 0;
+	ZXIC_UINT32 access_type = 0;
+	ZXIC_UINT32 dev_id_array[DPP_DEV_CHANNEL_MAX] = { 0 };
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_init_ctrl);
+
+	/* 初始化设备管理模块 */
+	rt = dpp_dev_init();
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rt, "dpp_dev_init");
+
+	rt = dpp_dev_add(dev_id, p_init_ctrl->device_type, access_type,
+					 p_init_ctrl->pcie_vir_baddr, p_init_ctrl->riscv_vir_baddr,
+					 p_init_ctrl->dma_vir_baddr, p_init_ctrl->dma_phy_baddr,
+					 p_init_ctrl->pcie_write_fun, p_init_ctrl->pcie_read_fun,
+					 p_init_ctrl->riscv_write_fun, p_init_ctrl->riscv_read_fun);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rt, "dpp_dev_add");
+
+	/* 初始化table模块软件部分 */
+	dev_id_array[0] = dev_id;
+	rt = dpp_sdt_init(1, dev_id_array);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rt, "dpp_sdt_init");
+
+	rt = dpp_ppu_parse_cls_bitmap(dev_id, DPP_PPU_CLS_ALL_START);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rt, "dpp_ppu_parse_cls_bitmap");
+
+	return DPP_OK;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/init/dpp_kernel_init.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/init/dpp_kernel_init.c
index 0e8b05b2bd95ab6577fae4bba5b48e159144d9f8..700f171eceb9d802b9348a9af5eaaf7b1ace5c8b 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/init/dpp_kernel_init.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/init/dpp_kernel_init.c
@@ -1,233 +1,246 @@
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/vmalloc.h>
-#include <linux/dma-mapping.h>
-#include <linux/pci.h>
-#include "zxic_common.h"
-#include "dpp_dtb_cfg.h"
-#include "dpp_kernel_init.h"
-#include "dpp_dtb_table_api.h"
-
-/*hash dma地址信息*/
-typedef struct hash_dma_addr_info
-{
-    ZXIC_UINT32 slot_id;            /*np所在的槽位号*/ 
-    ZXIC_UINT32 dma_size;           /*hash申请的dma大小*/
-    dma_addr_t dma_phy_addr;        /* dma 物理地址*/
-    ZXIC_VOID *dma_vir_addr;        /* dma 内核虚拟地址*/
-}HASH_DMA_ADDR_INFO;
-
-/*DMA空间信息*/
-typedef struct dpp_dma_info
-{
-    DTB_QUEUE_DMA_ADDR_INFO dtb_queue_info[DPP_DTB_QUEUE_NUM_MAX];   /*dtb队列*/
-    HASH_DMA_ADDR_INFO hash_dma_info;                                /*hash上送*/
-}DPP_KERNEL_DMA_INFO;
-
-static DPP_KERNEL_DMA_INFO g_dpp_dma_info[DPP_PCIE_SLOT_MAX] = {0};
-static ZXIC_UINT32 queue_used_flag[DPP_PCIE_SLOT_MAX][4] = {0};
-
-static ZXIC_VOID dpp_dtb_queue_dma_flag_set(ZXIC_UINT32 slot_id, ZXIC_UINT32 queue_id)
-{
-    ZXIC_UINT32 bit_shift = 0;
-    ZXIC_UINT32 reg_shift = 0;
-
-    reg_shift = queue_id / 32;
-    bit_shift = queue_id % 32;
-
-    queue_used_flag[slot_id][reg_shift] =  queue_used_flag[slot_id][reg_shift] | (0x1 << bit_shift);
-}
-
-static ZXIC_VOID dpp_dtb_queue_dma_flag_clear(ZXIC_UINT32 slot_id, ZXIC_UINT32 queue_id)
-{
-    ZXIC_UINT32 bit_shift = 0;
-    ZXIC_UINT32 reg_shift = 0;
-
-    reg_shift = queue_id / 32;
-    bit_shift = queue_id % 32;
-
-    queue_used_flag[slot_id][reg_shift] =  queue_used_flag[slot_id][reg_shift] & ~(0x1 << bit_shift);
-}
-
-static ZXIC_UINT32 dpp_dtb_queue_dma_flag_get(ZXIC_UINT32 slot_id, ZXIC_UINT32 queue_id)
-{
-    ZXIC_UINT32 bit_shift = 0;
-    ZXIC_UINT32 reg_shift = 0;
-
-    ZXIC_UINT32 flag = 0;
-
-    reg_shift = queue_id / 32;
-    bit_shift = queue_id % 32;
-
-    flag = (queue_used_flag[slot_id][reg_shift] >> bit_shift) & 0x1;
-
-    ZXIC_COMM_PRINT("[dpp_dtb_queue_dma_flag_get]:slot %d queue %d flag %d!\n", slot_id, queue_id, flag);
-
-    return flag;
-}
-
-//申请队列DMA空间，通过传入DMA队列号，返回申请到DMA内存的物理地址
-ZXIC_SINT32 dpp_dtb_queue_dma_mem_alloc(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 size)
-{
-    dma_addr_t dma_handle;
-    ZXIC_VOID* cpu_addr = NULL;
-    ZXIC_UINT32 slot_id = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    slot_id = (ZXIC_UINT32)DEV_PCIE_SLOT(dev);
-    ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_DEV_SLOT_MAX - 1);
-
-    if (queue_id > (DPP_DTB_QUEUE_NUM_MAX - 1))
-    {
-        return -ENOMEM;
-    }
-
-    cpu_addr = dma_alloc_coherent(&(DEV_PCIE_DEV(dev)->dev), size, &dma_handle, GFP_KERNEL);
-
-    if(!cpu_addr)
-    {
-        dev_err(&(DEV_PCIE_DEV(dev)->dev),"dpp_dtb_queue_dma_mem_alloc buff allocation failed\n");
-        return -ENOMEM;
-    }
-
-    g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].slot_id = slot_id;
-    g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].queue_id = queue_id;
-    g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_vir_addr = ZXIC_COMM_PTR_TO_VAL(cpu_addr);
-    g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_phy_addr = dma_handle;
-    g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_size = size;
-
-    ZXIC_COMM_PRINT("[dpp_dtb_queue_dma_mem_alloc]:slot %d queue %d kernel phy addr :0x%016llx !\n",
-                                                                slot_id, queue_id, dma_handle);
-    ZXIC_COMM_PRINT("[dpp_dtb_queue_dma_mem_alloc]:slot %d queue %d kernel vir addr :0x%016llx !\n",
-                                                                slot_id, queue_id, ZXIC_COMM_PTR_TO_VAL(cpu_addr));
-
-    dpp_dtb_queue_dma_flag_set(slot_id, queue_id);
-    dpp_dtb_queue_dma_flag_get(slot_id, queue_id);
-
-    return DPP_OK;
-}
-
-ZXIC_SINT32 dpp_dtb_queue_dma_mem_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, DTB_QUEUE_DMA_ADDR_INFO *dmaAddrInfo)
-{
-    ZXIC_UINT32 slot_id = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    slot_id = (ZXIC_UINT32)DEV_PCIE_SLOT(dev);
-    ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_DEV_SLOT_MAX - 1);
-
-    if(queue_id > (DPP_DTB_QUEUE_NUM_MAX - 1))
-    {
-        ZXIC_COMM_PRINT("[dpp_dtb_queue_dma_mem_get]:queue id max.\n");
-        return -1;
-    }
-
-    if (g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].queue_id != queue_id)
-    {
-        ZXIC_COMM_PRINT("[dpp_dtb_queue_dma_mem_get]:slot %d queue %d error !\n", slot_id, queue_id);
-        return -1;
-    }
-    dmaAddrInfo->dma_phy_addr = g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_phy_addr;
-    dmaAddrInfo->dma_vir_addr = g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_vir_addr;
-    dmaAddrInfo->dma_size = g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_size;
-    dmaAddrInfo->queue_id = queue_id;
-    dmaAddrInfo->slot_id = slot_id;
-
-    return DPP_OK;
-}
-
-/*dtb队列dma内存释放，通过传入dtb队列号，在维护的队列地址中找到对应的虚拟地址和物理地址，进行释放*/
-ZXIC_SINT32 dpp_dtb_queue_dma_mem_release(DPP_DEV_T *dev, ZXIC_UINT32 queue_id)
-{
-    dma_addr_t dma_handle = 0;
-    ZXIC_VOID* cpu_addr = NULL;
-    ZXIC_UINT32 dma_size = 0;
-    ZXIC_UINT32 slot_id = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    slot_id = (ZXIC_UINT32)DEV_PCIE_SLOT(dev);
-    ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_DEV_SLOT_MAX - 1);
-
-    if(queue_id > (DPP_DTB_QUEUE_NUM_MAX - 1))
-    {
-        ZXIC_COMM_PRINT("[dpp_dtb_dma_mem_release]:queue id max.\n");
-        return -1;
-    }
-
-    if (g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].queue_id != queue_id)
-    {
-        ZXIC_COMM_PRINT("[dpp_dtb_dma_mem_release]:slot %d queue %d error !\n", slot_id, queue_id);
-        return -1;
-    }
-    
-    dma_handle = g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_phy_addr;
-    cpu_addr = ZXIC_COMM_VAL_TO_PTR(g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_vir_addr);
-    dma_size = g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_size;
-
-    if (!dma_handle)
-    {
-        return -EFAULT;
-    }
-
-    dma_free_coherent(&(DEV_PCIE_DEV(dev)->dev), dma_size, cpu_addr, dma_handle);
-
-    ZXIC_COMM_PRINT("[dpp_dtb_dma_mem_release]:slot %d queue %d release success!\n", slot_id, queue_id);
-
-    g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].slot_id = 0;
-    g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].queue_id = 0;
-    g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_phy_addr = 0;
-    g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_vir_addr = 0;
-    g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_size = 0;
-
-    dpp_dtb_queue_dma_flag_clear(slot_id, queue_id);
-    dpp_dtb_queue_dma_flag_get(slot_id, queue_id);
-
-    return 0;
-}
-
-ZXIC_SINT32 dtb_sdt_dump_dma_alloc(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 dma_size, 
-                                   ZXIC_UINT64 * p_dma_phy_addr, 
-                                   ZXIC_UINT64 * p_dma_vir_addr)
-{
-    int rc = 0;
-
-    dma_addr_t dma_handle;
-    ZXIC_VOID* cpu_addr = NULL;
-
-    cpu_addr = dma_alloc_coherent(&(DEV_PCIE_DEV(dev)->dev), dma_size, &dma_handle, GFP_KERNEL);
-
-    if(!cpu_addr)
-    {
-        dev_err(&(DEV_PCIE_DEV(dev)->dev),"dtb_sdt_dump_dma_alloc buff allocation failed\n");
-        return -ENOMEM;
-    }
-
-    *p_dma_phy_addr = (ZXIC_UINT64)dma_handle;
-    *p_dma_vir_addr = (ZXIC_UINT64)(ZXIC_COMM_PTR_TO_VAL(cpu_addr));
-
-    return rc;
-}
-
-ZXIC_SINT32 dtb_sdt_dump_dma_release(DPP_DEV_T *dev,
-                            ZXIC_UINT32 dma_size, 
-                            ZXIC_UINT64 dma_phy_addr, 
-                            ZXIC_UINT64 dma_vir_addr)
-{
-    dma_addr_t dma_handle = 0;
-    ZXIC_VOID* cpu_addr = NULL;
-
-    dma_handle = (dma_addr_t)dma_phy_addr;
-    cpu_addr = ZXIC_COMM_VAL_TO_PTR(dma_vir_addr);
-
-    if (!dma_handle)
-    {
-        return -EFAULT;
-    }
-
-    dma_free_coherent(&(DEV_PCIE_DEV(dev)->dev), dma_size, cpu_addr, dma_handle);
-
-    return 0;
-}
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/dma-mapping.h>
+#include <linux/pci.h>
+#include "zxic_common.h"
+#include "dpp_dtb_cfg.h"
+#include "dpp_kernel_init.h"
+#include "dpp_dtb_table_api.h"
+
+/*hash dma地址信息*/
+typedef struct hash_dma_addr_info {
+	ZXIC_UINT32 slot_id; /*np所在的槽位号*/
+	ZXIC_UINT32 dma_size; /*hash申请的dma大小*/
+	dma_addr_t dma_phy_addr; /* dma 物理地址*/
+	ZXIC_VOID *dma_vir_addr; /* dma 内核虚拟地址*/
+} HASH_DMA_ADDR_INFO;
+
+/*DMA空间信息*/
+typedef struct dpp_dma_info {
+	DTB_QUEUE_DMA_ADDR_INFO dtb_queue_info[DPP_DTB_QUEUE_NUM_MAX]; /*dtb队列*/
+	HASH_DMA_ADDR_INFO hash_dma_info; /*hash上送*/
+} DPP_KERNEL_DMA_INFO;
+
+static DPP_KERNEL_DMA_INFO g_dpp_dma_info[DPP_PCIE_SLOT_MAX] = { 0 };
+static ZXIC_UINT32 queue_used_flag[DPP_PCIE_SLOT_MAX][4] = { 0 };
+
+static ZXIC_VOID dpp_dtb_queue_dma_flag_set(ZXIC_UINT32 slot_id,
+											ZXIC_UINT32 queue_id)
+{
+	ZXIC_UINT32 bit_shift = 0;
+	ZXIC_UINT32 reg_shift = 0;
+
+	reg_shift = queue_id / 32;
+	bit_shift = queue_id % 32;
+
+	queue_used_flag[slot_id][reg_shift] = queue_used_flag[slot_id][reg_shift] |
+										  (0x1 << bit_shift);
+}
+
+static ZXIC_VOID dpp_dtb_queue_dma_flag_clear(ZXIC_UINT32 slot_id,
+											  ZXIC_UINT32 queue_id)
+{
+	ZXIC_UINT32 bit_shift = 0;
+	ZXIC_UINT32 reg_shift = 0;
+
+	reg_shift = queue_id / 32;
+	bit_shift = queue_id % 32;
+
+	queue_used_flag[slot_id][reg_shift] = queue_used_flag[slot_id][reg_shift] &
+										  ~(0x1 << bit_shift);
+}
+
+static ZXIC_UINT32 dpp_dtb_queue_dma_flag_get(ZXIC_UINT32 slot_id,
+											  ZXIC_UINT32 queue_id)
+{
+	ZXIC_UINT32 bit_shift = 0;
+	ZXIC_UINT32 reg_shift = 0;
+
+	ZXIC_UINT32 flag = 0;
+
+	reg_shift = queue_id / 32;
+	bit_shift = queue_id % 32;
+
+	flag = (queue_used_flag[slot_id][reg_shift] >> bit_shift) & 0x1;
+
+	ZXIC_COMM_PRINT("[dpp_dtb_queue_dma_flag_get]:slot %d queue %d flag %d!\n",
+					slot_id, queue_id, flag);
+
+	return flag;
+}
+
+//申请队列DMA空间，通过传入DMA队列号，返回申请到DMA内存的物理地址
+ZXIC_SINT32 dpp_dtb_queue_dma_mem_alloc(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+										ZXIC_UINT32 size)
+{
+	dma_addr_t dma_handle;
+	ZXIC_VOID *cpu_addr = NULL;
+	ZXIC_UINT32 slot_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	slot_id = (ZXIC_UINT32)DEV_PCIE_SLOT(dev);
+	ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_DEV_SLOT_MAX - 1);
+
+	if (queue_id > DPP_DTB_QUEUE_NUM_MAX - 1) {
+		return -ENOMEM;
+	}
+
+	cpu_addr = dma_alloc_coherent(&(DEV_PCIE_DEV(dev)->dev), size, &dma_handle,
+								  GFP_KERNEL);
+
+	if (!cpu_addr) {
+		dev_err(&(DEV_PCIE_DEV(dev)->dev),
+				"dpp_dtb_queue_dma_mem_alloc buff allocation failed\n");
+		return -ENOMEM;
+	}
+
+	g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].slot_id = slot_id;
+	g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].queue_id = queue_id;
+	g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_vir_addr =
+			ZXIC_COMM_PTR_TO_VAL(cpu_addr);
+	g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_phy_addr = dma_handle;
+	g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_size = size;
+
+	ZXIC_COMM_PRINT(
+			"[dpp_dtb_queue_dma_mem_alloc]:slot %d queue %d kernel phy addr :0x%016llx !\n",
+			slot_id, queue_id, dma_handle);
+	ZXIC_COMM_PRINT(
+			"[dpp_dtb_queue_dma_mem_alloc]:slot %d queue %d kernel vir addr :0x%016llx !\n",
+			slot_id, queue_id, cpu_addr);
+
+	dpp_dtb_queue_dma_flag_set(slot_id, queue_id);
+	dpp_dtb_queue_dma_flag_get(slot_id, queue_id);
+
+	return DPP_OK;
+}
+
+ZXIC_SINT32 dpp_dtb_queue_dma_mem_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									  DTB_QUEUE_DMA_ADDR_INFO *dmaAddrInfo)
+{
+	ZXIC_UINT32 slot_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	slot_id = (ZXIC_UINT32)DEV_PCIE_SLOT(dev);
+	ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_DEV_SLOT_MAX - 1);
+
+	if (queue_id > DPP_DTB_QUEUE_NUM_MAX - 1) {
+		ZXIC_COMM_PRINT("[dpp_dtb_queue_dma_mem_get]:queue id max.\n");
+		return -1;
+	}
+
+	if (g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].queue_id != queue_id) {
+		ZXIC_COMM_PRINT(
+				"[dpp_dtb_queue_dma_mem_get]:slot %d queue %d error !\n",
+				slot_id, queue_id);
+		return -1;
+	}
+	dmaAddrInfo->dma_phy_addr =
+			g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_phy_addr;
+	dmaAddrInfo->dma_vir_addr =
+			g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_vir_addr;
+	dmaAddrInfo->dma_size =
+			g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_size;
+	dmaAddrInfo->queue_id = queue_id;
+	dmaAddrInfo->slot_id = slot_id;
+
+	return DPP_OK;
+}
+
+/*dtb队列dma内存释放，通过传入dtb队列号，在维护的队列地址中找到对应的虚拟地址和物理地址，进行释放*/
+ZXIC_SINT32 dpp_dtb_queue_dma_mem_release(DPP_DEV_T *dev, ZXIC_UINT32 queue_id)
+{
+	dma_addr_t dma_handle = 0;
+	ZXIC_VOID *cpu_addr = NULL;
+	ZXIC_UINT32 dma_size = 0;
+	ZXIC_UINT32 slot_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	slot_id = (ZXIC_UINT32)DEV_PCIE_SLOT(dev);
+	ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_DEV_SLOT_MAX - 1);
+
+	if (queue_id > DPP_DTB_QUEUE_NUM_MAX - 1) {
+		ZXIC_COMM_PRINT("[dpp_dtb_dma_mem_release]:queue id max.\n");
+		return -1;
+	}
+
+	if (g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].queue_id != queue_id) {
+		ZXIC_COMM_PRINT("[dpp_dtb_dma_mem_release]:slot %d queue %d error !\n",
+						slot_id, queue_id);
+		return -1;
+	}
+
+	dma_handle = g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_phy_addr;
+	cpu_addr = ZXIC_COMM_VAL_TO_PTR(
+			g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_vir_addr);
+	dma_size = g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_size;
+
+	if (!dma_handle) {
+		return -EFAULT;
+	}
+
+	dma_free_coherent(&(DEV_PCIE_DEV(dev)->dev), dma_size, cpu_addr,
+					  dma_handle);
+
+	ZXIC_COMM_PRINT(
+			"[dpp_dtb_dma_mem_release]:slot %d queue %d release success!\n",
+			slot_id, queue_id);
+
+	g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].slot_id = 0;
+	g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].queue_id = 0;
+	g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_phy_addr = 0;
+	g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_vir_addr = 0;
+	g_dpp_dma_info[slot_id].dtb_queue_info[queue_id].dma_size = 0;
+
+	dpp_dtb_queue_dma_flag_clear(slot_id, queue_id);
+	dpp_dtb_queue_dma_flag_get(slot_id, queue_id);
+
+	return 0;
+}
+
+ZXIC_SINT32 dtb_sdt_dump_dma_alloc(DPP_DEV_T *dev, ZXIC_UINT32 dma_size,
+								   ZXIC_UINT64 *p_dma_phy_addr,
+								   ZXIC_UINT64 *p_dma_vir_addr)
+{
+	int rc = 0;
+
+	dma_addr_t dma_handle;
+	ZXIC_VOID *cpu_addr = NULL;
+
+	cpu_addr = dma_alloc_coherent(&(DEV_PCIE_DEV(dev)->dev), dma_size,
+								  &dma_handle, GFP_KERNEL);
+
+	if (!cpu_addr) {
+		dev_err(&(DEV_PCIE_DEV(dev)->dev),
+				"dtb_sdt_dump_dma_alloc buff allocation failed\n");
+		return -ENOMEM;
+	}
+
+	*p_dma_phy_addr = (ZXIC_UINT64)dma_handle;
+	*p_dma_vir_addr = (ZXIC_UINT64)(ZXIC_COMM_PTR_TO_VAL(cpu_addr));
+
+	return rc;
+}
+
+ZXIC_SINT32 dtb_sdt_dump_dma_release(DPP_DEV_T *dev, ZXIC_UINT32 dma_size,
+									 ZXIC_UINT64 dma_phy_addr,
+									 ZXIC_UINT64 dma_vir_addr)
+{
+	dma_addr_t dma_handle = 0;
+	ZXIC_VOID *cpu_addr = NULL;
+
+	dma_handle = (dma_addr_t)dma_phy_addr;
+	cpu_addr = ZXIC_COMM_VAL_TO_PTR(dma_vir_addr);
+
+	if (!dma_handle) {
+		return -EFAULT;
+	}
+
+	dma_free_coherent(&(DEV_PCIE_DEV(dev)->dev), dma_size, cpu_addr,
+					  dma_handle);
+
+	return 0;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/dpp_dtb.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/dpp_dtb.c
old mode 100755
new mode 100644
index 9d64e63feec1b48d33525bd3be939d0b7225200a..99a372f740f8ceccd340b676dd01e3d9754dd806
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/dpp_dtb.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/dpp_dtb.c
@@ -1,2183 +1,2254 @@
-/**************************************************************
-* 版权所有(C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_dtb.c
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : zab
-* 完成日期 : 2022/08/26
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-#include "zxic_common.h"
-#include "dpp_dev.h"
-#include "dpp_type_api.h"
-#include "dpp_dtb_cfg.h"
-#include "dpp_dtb.h"
-#include "dpp_dtb_table.h"
-#include "dpp_hash.h"
-#include "dpp_dtb_reg.h"
-#include "dpp_reg_api.h"
-#include "dpp_reg_info.h"
-#include "dpp_se_api.h"
-
-#if ZXIC_REAL("DTB")
-
-ZXIC_CHAR *g_dpp_dtb_name[] =
-{
-    "DOWN TAB",
-    "UP TAB",
-};
-
-DPP_DTB_MGR_T *p_dpp_dtb_mgr[DPP_PCIE_SLOT_MAX][DPP_DEV_CHANNEL_MAX]   = {{NULL}};
-
-/**dtb超时时间 单位us*/
-static ZXIC_UINT32 g_dtb_down_overtime = 2*1000;
-static ZXIC_UINT32 g_dtb_dump_overtime = 5*1000*1000;
-
-/*配置dtb调试函数*/
-static ZXIC_UINT32 g_dtb_debug_fun_en = 0;
-static ZXIC_UINT32 g_dtb_print_en = 0;
-static ZXIC_UINT32 g_dtb_soft_perf_test = 0;
-static ZXIC_UINT32 g_dtb_hardware_perf_test = 0;
-
-/**使能dtb调试函数*/
-ZXIC_UINT32 dpp_dtb_debug_fun_enable(ZXIC_VOID)
-{
-    g_dtb_debug_fun_en = 1;
-    return 0;
-}
-
-/**去使能dtb调试函数*/
-ZXIC_UINT32 dpp_dtb_debug_fun_disable(ZXIC_VOID)
-{
-    g_dtb_debug_fun_en = 0;
-    return 0;
-}
-
-/**获取dtb调试函数*/
-ZXIC_UINT32 dpp_dtb_debug_fun_get(ZXIC_VOID)
-{
-    return g_dtb_debug_fun_en;
-}
-
-/**使能dtb打印函数*/
-ZXIC_UINT32 dpp_dtb_prt_enable(ZXIC_VOID)
-{
-    g_dtb_print_en = 1;
-    return 0;
-}
-
-/**去使能dtb打印函数*/
-ZXIC_UINT32 dpp_dtb_prt_disable(ZXIC_VOID)
-{
-    g_dtb_print_en = 0;
-    return 0;
-}
-
-/**获取dtb打印函数*/
-ZXIC_UINT32 dpp_dtb_prt_get(ZXIC_VOID)
-{
-    return g_dtb_print_en;
-}
-
-ZXIC_UINT32 dpp_dtb_soft_perf_test_set(ZXIC_UINT32 value)
-{
-    g_dtb_soft_perf_test = value;
-    return 0;
-}
-
-ZXIC_UINT32 dpp_dtb_soft_perf_test_get(ZXIC_VOID)
-{
-    return g_dtb_soft_perf_test;
-}
-
-ZXIC_UINT32 dpp_dtb_hardware_perf_test_set(ZXIC_UINT32 value)
-{
-    g_dtb_hardware_perf_test = value;
-    return 0;
-}
-
-ZXIC_UINT32 dpp_dtb_hardware_perf_test_get(ZXIC_VOID)
-{
-    return g_dtb_hardware_perf_test;
-}
-
-ZXIC_UINT32 dpp_dtb_down_table_overtime_set(ZXIC_UINT32 times_s)
-{
-    g_dtb_down_overtime = times_s;
-    return 0;
-}
-
-ZXIC_UINT32 dpp_dtb_down_table_overtime_get(ZXIC_VOID)
-{
-    return g_dtb_down_overtime;
-}
-
-ZXIC_UINT32 dpp_dtb_dump_table_overtime_set(ZXIC_UINT32 times_s)
-{
-    g_dtb_dump_overtime = times_s;
-    return 0;
-}
-
-ZXIC_UINT32 dpp_dtb_dump_table_overtime_get(ZXIC_VOID)
-{
-    return g_dtb_dump_overtime;
-}
-
-#if ZXIC_REAL("MGR")
-/***********************************************************/
-/** 创建DTB的管理结构
-* @param   dev_id       设备号，支持多芯片  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_mgr_create(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id)
-{
-    ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_PCIE_SLOT_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    
-    if (p_dpp_dtb_mgr[slot_id][dev_id] != ZXIC_NULL)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n", slot_id, DPP_RC_DTB_MGR_NOT_EXIST);
-        return DPP_RC_DTB_MGR_EXIST;
-    }
-    
-    p_dpp_dtb_mgr[slot_id][dev_id] = (DPP_DTB_MGR_T *)ZXIC_COMM_MALLOC(sizeof(DPP_DTB_MGR_T));
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dpp_dtb_mgr[slot_id][dev_id]);
-    
-    ZXIC_COMM_MEMSET(p_dpp_dtb_mgr[slot_id][dev_id], 0, sizeof(DPP_DTB_MGR_T));
-
-    ZXIC_COMM_PRINT("dpp_dtb_mgr_create:slot %d dev %d done!!!", slot_id, dev_id);
-    
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 注销DTB的管理结构
-* @param   dev_id       设备号，支持多芯片   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_mgr_destory_all(ZXIC_VOID)
-{
-    ZXIC_UINT32 slot_id = 0;
-    ZXIC_UINT32 dev_id = 0;
-    
-    for(slot_id = 0; slot_id < DPP_DEV_SLOT_MAX; slot_id++)
-    {
-        for(dev_id = 0; dev_id < DPP_DEV_CHANNEL_MAX; dev_id++)
-        {
-            dpp_dtb_mgr_destory(slot_id, dev_id);
-        }
-    }
-    
-    return DPP_OK;
-}
-
-ZXIC_UINT32 dpp_dtb_mgr_destory(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id)
-{
-    ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_PCIE_SLOT_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    
-    if (p_dpp_dtb_mgr[slot_id][dev_id] != ZXIC_NULL)
-    {
-        ZXIC_COMM_FREE(p_dpp_dtb_mgr[slot_id][dev_id]);
-        p_dpp_dtb_mgr[slot_id][dev_id] = ZXIC_NULL;
-        ZXIC_COMM_PRINT("dpp_dtb_mgr_destory:slot %d dev %d done!!!", slot_id, dev_id);
-    }
-    
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 重置DTB管理结构
-* @param   dev_id       设备号，支持多芯片   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_mgr_reset(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id)
-{
-    ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_PCIE_SLOT_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    
-    if (p_dpp_dtb_mgr[slot_id][dev_id] == ZXIC_NULL)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "slot %d ErrorCode[0x%x]: dtb manager is not exist!!!\n", slot_id, DPP_RC_DTB_MGR_NOT_EXIST);
-        return DPP_RC_DTB_MGR_NOT_EXIST;
-    }
-
-    ZXIC_COMM_MEMSET(p_dpp_dtb_mgr[slot_id][dev_id], 0, sizeof(DPP_DTB_MGR_T));
-    
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取DMA管理结构
-* @param   dev_id               设备号，支持多芯片
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-DPP_DTB_MGR_T *dpp_dtb_mgr_get(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id)
-{
-    if ((slot_id >= DPP_PCIE_SLOT_MAX) ||  (dev_id >= DPP_DEV_CHANNEL_MAX))
-    {
-        return ZXIC_NULL;
-    }
-    else
-    {
-        return p_dpp_dtb_mgr[slot_id][dev_id];
-    }
-}
-#endif
-
-#if ZXIC_REAL("QUEUE_ADDR")
-/***********************************************************/
-/** 获得下表队列中某元素的物理地址
-* @param   dev_id                         设备号，支持多芯片  
-* @param   queue_id                       队列号0-127
-* @param   element_id                     队列中元素号0-31
-* @param   p_element_start_addr_h         元素起始高32位地址
-* @param   p_element_start_addr_l         元素起始低32位地址
-* @param   p_element_table_addr_h         下表内容开始高32位地址
-* @param   p_element_table_addr_l         下表内容开始低32位地址
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_down_table_elemet_addr_get(DPP_DEV_T *dev, 
-                                              ZXIC_UINT32 queue_id, 
-                                              ZXIC_UINT32 element_id,
-                                              ZXIC_UINT32 *p_element_start_addr_h,
-                                              ZXIC_UINT32 *p_element_start_addr_l,
-                                              ZXIC_UINT32 *p_element_table_addr_h,
-                                              ZXIC_UINT32 *p_element_table_addr_l)
-{
-    ZXIC_UINT32 addr_h = 0;
-    ZXIC_UINT32 addr_l = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), element_id, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
-
-    addr_h = (DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, element_id) >> 32) & 0xffffffff;
-    addr_l = DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, element_id) & 0xffffffff;
-
-    *p_element_start_addr_h = addr_h;
-    *p_element_start_addr_l = addr_l;
-
-    addr_h = ((DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, element_id) + DPP_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff;
-    addr_l = (DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, element_id) + DPP_DTB_ITEM_ACK_SIZE) & 0xffffffff;
-
-    *p_element_table_addr_h = addr_h;
-    *p_element_table_addr_l = addr_l;
-
-    return DPP_OK;
-} 
-
-/***********************************************************/
-/** 获得队列中某元素dump的物理地址
-* @param   dev_id                         设备号，支持多芯片  
-* @param   queue_id                       队列号0-127
-* @param   element_id                     队列中元素号0-31
-* @param   p_element_start_addr_h         元素起始高32位地址
-* @param   p_element_start_addr_l         元素起始低32位地址
-* @param   p_element_dump_addr_h          dump描述符开始高32位地址
-* @param   p_element_dump_addr_l          dump描述符开始低32位地址
-* @param   p_element_table_info_addr_h    表内容开始高32位地址
-* @param   p_element_table_info_addr_l    表内容开始低32位地址
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_dump_table_elemet_addr_get(DPP_DEV_T *dev, 
-                                               ZXIC_UINT32 queue_id, 
-                                               ZXIC_UINT32 element_id,
-                                               ZXIC_UINT32 *p_element_start_addr_h,
-                                               ZXIC_UINT32 *p_element_start_addr_l,
-                                               ZXIC_UINT32 *p_element_dump_addr_h,
-                                               ZXIC_UINT32 *p_element_dump_addr_l,
-                                               ZXIC_UINT32 *p_element_table_info_addr_h,
-                                               ZXIC_UINT32 *p_element_table_info_addr_l)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 addr_h = 0;
-    ZXIC_UINT32 addr_l = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), element_id, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
-
-    addr_h = ((DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, element_id)) >> 32) & 0xffffffff;
-    addr_l = (DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, element_id)) & 0xffffffff;
-
-    *p_element_start_addr_h = addr_h;
-    *p_element_start_addr_l = addr_l;
-
-    addr_h = ((DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, element_id)+ DPP_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff;
-    addr_l = (DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, element_id)+ DPP_DTB_ITEM_ACK_SIZE) & 0xffffffff;
-
-    *p_element_dump_addr_h = addr_h;
-    *p_element_dump_addr_l = addr_l;
-
-    rc = dpp_dtb_tab_up_item_addr_get(dev, queue_id, element_id, p_element_table_info_addr_h, p_element_table_info_addr_l);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get");
-
-    return DPP_OK;
-}
-
-#endif
-
-#if ZXIC_REAL("MEM_RW")
-/***********************************************************/
-/** 内存32bits写入函数
-* @param   dev_id           设备号，支持多芯片  
-* @param   addr             地址偏移
-* @param   data             写入数据
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_wr32(DPP_DEV_T *dev, 
-                        ZXIC_ADDR_T addr, 
-                        ZXIC_UINT32 data)  
-{
-    ZXIC_UINT32 value = data;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), data, 0, ZXIC_UINT32_MAX);
-
-    if (!zxic_comm_is_big_endian()) 
-    {
-        value = ZXIC_COMM_CONVERT32(value);
-    }
-    
-    *((ZXIC_VOL ZXIC_UINT32 *)(addr)) = value;
-    
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 内存32bits读取函数
-* @param   dev_id           设备号，支持多芯片  
-* @param   addr             读取地址
-* @param   p_data           读取数据
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_rd32(DPP_DEV_T *dev,
-                        ZXIC_ADDR_T addr, 
-                        ZXIC_UINT32 *p_data)      
-{
-    ZXIC_UINT32 value = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-
-    // dpp_flush_cache();//片内DDR使用
-
-    value = *((ZXIC_VOL ZXIC_UINT32 *)(addr));
-
-    if (!zxic_comm_is_big_endian())
-    {
-        value = ZXIC_COMM_CONVERT32(value);
-    }
-
-    *p_data = value;
-
-    return DPP_OK;
-}
-#endif
-
-#if ZXIC_REAL("ACK_RW")
-/***********************************************************/
-/** 读取BD表条目信息
-* @param   dev_id       芯片的id号  
-* @param   queue_id     队列号,范围0-127
-* @param   dir_flag     方向,1-上送表项,0-下发表项    
-* @param   index        条目索引,范围0-31 
-* @param   pos          一个item里面的4个32位，pos对应的是第几个ZXICP_WORD32，
-*                       取值为0，1，2，3      
-* @param   p_data       读取的数据,大端格式  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2019/11/2
-************************************************************/
-ZXIC_UINT32 dpp_dtb_item_ack_rd(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 dir_flag,
-                    ZXIC_UINT32 index, 
-                    ZXIC_UINT32 pos,
-                    ZXIC_UINT32 *p_data)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_ADDR_T addr = 0;
-    ZXIC_UINT32 val = 0;
-    
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), dir_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pos, 0, 3);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-
-    if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0)
-    {
-        ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id);
-        return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
-    }
-
-    if (dir_flag == DPP_DTB_DIR_UP_TYPE)
-    {
-        addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) + pos * 4;
-    }
-    else
-    {
-        addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev),DEV_ID(dev), queue_id, index) + pos * 4;
-    }
-    
-    rc = dpp_dtb_rd32(dev, addr, &val);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_rd32");
-
-    *p_data = val;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 向BD表条目指定位置写入值
-* @param   dev_id       芯片的id号  
-* @param   queue_id     队列号,范围0-127
-* @param   dir_flag     方向,1-上送表项,0-下发表项  
-* @param   index        条目索引,范围0-31 
-* @param   pos          一个item里面的4个32位，pos对应的是第几个ZXICP_WORD32，
-*                       取值为0，1，2，3      
-* @param   data         读取的数据,大端格式 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2019/11/2
-************************************************************/
-ZXIC_UINT32 dpp_dtb_item_ack_wr(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 dir_flag,
-                    ZXIC_UINT32 index, 
-                    ZXIC_UINT32 pos,
-                    ZXIC_UINT32 data)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_ADDR_T addr = 0;
-    
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), dir_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pos, 0, 3);
-
-    if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0)
-    {
-        ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id);
-        return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
-    }
-
-    if (dir_flag == DPP_DTB_DIR_UP_TYPE)
-    {
-        addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) + pos * 4;
-    }
-    else
-    {
-        addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) + pos * 4;
-    }
-
-    rc = dpp_dtb_wr32(dev, addr, data);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_wr32");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 打印队列指定条目ACK信息
-* @param   dev_id       芯片的id号  
-* @param   queue_id     队列号，范围0-127  
-* @param   dir_flag     方向,0-down,1-up    
-* @param   index        条目索引 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2022/08/30
-************************************************************/
-ZXIC_UINT32 dpp_dtb_item_ack_prt(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 dir_flag,
-                    ZXIC_UINT32 index)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 ack_data[4] = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), dir_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX -1);
-
-    for (i = 0; i < DPP_DTB_ITEM_ACK_SIZE / 4; i++)
-    {
-         rc = dpp_dtb_item_ack_rd(dev, queue_id, dir_flag, index, i, ack_data + i);
-         ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd");
-    }
-    
-    ZXIC_COMM_PRINT("\n=====> [%s] BD INFO:", g_dpp_dtb_name[dir_flag]);
-    ZXIC_COMM_PRINT("\n[ index : %u] : 0x%08x 0x%08x 0x%08x 0x%08x \n", index, ack_data[0], ack_data[1], ack_data[2], ack_data[3]);
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 打印队列指定条目BUFF的数据
-* @param   dev_id       芯片的id号  
-* @param   queue_id     队列号，范围0-127   
-* @param   dir_flag     方向,0-down,1-up    
-* @param   index        条目索引  
-* @param   len          读取数据长度 4字节为单位 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2022/08/30
-************************************************************/
-ZXIC_UINT32 dpp_dtb_item_buff_prt(DPP_DEV_T *dev,
-                                  ZXIC_UINT32 queue_id,
-                                  ZXIC_UINT32 dir_flag,
-                                  ZXIC_UINT32 index, 
-                                  ZXIC_UINT32 len)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 *p_item_buff = ZXIC_NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), dir_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX -1);
-
-    p_item_buff = ZXIC_COMM_MALLOC((len * sizeof(ZXIC_UINT32)) % ZXIC_COMM_WORD32_MASK);
-    if (p_item_buff == ZXIC_NULL)
-    {
-        ZXIC_COMM_PRINT("Alloc dtb item buffer faild!!!\n");
-        return DPP_RC_DTB_MEMORY_ALLOC_ERR;
-    }
-
-    ZXIC_COMM_MEMSET(p_item_buff, 0, len * sizeof(ZXIC_UINT32));
-
-    rc = dpp_dtb_item_buff_rd(dev, queue_id, dir_flag, index, 0, len, p_item_buff);
-    ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE(DEV_ID(dev), rc, "dpp_dtb_item_buff_rd", p_item_buff);
-    
-    ZXIC_COMM_PRINT("\n=====> [%s] BUFF INFO:", g_dpp_dtb_name[dir_flag]);
-    for(i = 0, j = 0; i < len; i++, j++)
-    {
-        if(j % 4 == 0)
-        { 
-            ZXIC_COMM_PRINT("\n0x%08x ", (*(p_item_buff + i)));                                   
-        }
-        else
-        {
-            ZXIC_COMM_PRINT("0x%08x ", (*(p_item_buff + i)));
-        }
-    }
-    ZXIC_COMM_PRINT("\n");
-
-    ZXIC_COMM_FREE(p_item_buff);
-
-    return DPP_OK;
-}
-
-#endif
-
-
-#if ZXIC_REAL("BUFF_RW")
-
-/***********************************************************/
-/** 读取dtb条目指向BUFF的数据
-* @param   dev_id       芯片的id号  
-* @param   queue_id     队列号,范围0-127
-* @param   dir_flag     方向,1-上送表项,0-下发表项  
-* @param   index        条目索引,范围0-31 
-* @param   pos          相对BUFF起始地址的偏移,单位32bit;      
-* @param   p_data       读取的数据,大端格式 
-* @param   len          读取数据长度,单位32bit; 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2019/11/2
-************************************************************/
-ZXIC_UINT32 dpp_dtb_item_buff_rd(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 dir_flag,
-                    ZXIC_UINT32 index, 
-                    ZXIC_UINT32 pos,
-                    ZXIC_UINT32 len,
-                    ZXIC_UINT32 *p_data)
-{
-    ZXIC_ADDR_T addr = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), dir_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pos, 0, 3);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-
-    if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0)
-    {
-        ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id);
-        return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
-    }
-
-    if (dir_flag == DPP_DTB_DIR_UP_TYPE)
-    {
-        if (DPP_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) == DPP_DTB_TAB_UP_USER_ADDR_TYPE)
-        {
-            addr = DPP_DTB_TAB_UP_USER_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) + pos * 4;
-            DPP_DTB_TAB_UP_USER_ADDR_FLAG_SET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index, 0);//为什么设置为0？
-        }
-        else
-        {
-            addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) + DPP_DTB_ITEM_ACK_SIZE + pos * 4;
-        }
-    }
-    else
-    {
-        addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) + DPP_DTB_ITEM_ACK_SIZE + pos * 4;
-    }
-
-    ZXIC_COMM_MEMCPY_S(p_data, len * 4, (ZXIC_UINT8 *)(addr), len * 4);
-
-    zxic_comm_swap((ZXIC_UINT8*)p_data, len * 4);
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 向BD表条目指向的BUFF指定位置写入值
-* @param   dev_id       芯片的id号  
-* @param   queue_id     队列号,范围0-127
-* @param   dir_flag     方向,1-上送表项,0-下发表项  
-* @param   index        条目索引,范围0-31   
-* @param   pos          相对BUFF起始地址的偏移,单位32bit;       
-* @param   p_data       读取的数据,大端格式 
-* @param   len          写入数据长度,单位32bit; 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2019/11/2
-************************************************************/
-ZXIC_UINT32 dpp_dtb_item_buff_wr(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 dir_flag,
-                    ZXIC_UINT32 index, 
-                    ZXIC_UINT32 pos,
-                    ZXIC_UINT32 len,
-                    ZXIC_UINT32 *p_data)
-{
-    ZXIC_ADDR_T addr = 0;
-    
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), dir_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pos, 0, 3);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-
-    if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0)
-    {
-        ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id);
-        return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
-    }
-
-    if (dir_flag == DPP_DTB_DIR_UP_TYPE)
-    {
-        addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) + DPP_DTB_ITEM_ACK_SIZE + pos * 4;
-    }
-    else
-    {
-        addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) + DPP_DTB_ITEM_ACK_SIZE + pos * 4;
-    }
-
-    ZXIC_COMM_MEMCPY_S((ZXIC_UINT8 *)(addr), len * 4, p_data, len * 4);
-
-    // dpp_flush_cache();//片内ddr使用
-
-    return DPP_OK;
-}
-#endif
-
-#if ZXIC_REAL("API")
-#if ZXIC_REAL("TAB_DOWN")
-
-/** dtb info print*/
-ZXIC_UINT32 dpp_dtb_info_print(DPP_DEV_T *dev, 
-                               ZXIC_UINT32 queue_id, 
-                               ZXIC_UINT32 item_index,
-                               DPP_DTB_QUEUE_ITEM_INFO_T *item_info)
-{
-    ZXIC_ADDR_T element_start_addr = 0;
-    ZXIC_ADDR_T ack_start_addr = 0;
-    ZXIC_ADDR_T data_addr = 0;
-    ZXIC_UINT32 data = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    ZXIC_COMM_PRINT("dpp_dtb_info_print: slot %d queue: %d, element:%d,  %s table info is:\n", DEV_PCIE_SLOT(dev), queue_id, item_index,
-                                        (item_info->cmd_type) ? "up" : "down");
-    ZXIC_COMM_PRINT("cmd_vld    : %d\n", item_info->cmd_vld);
-    ZXIC_COMM_PRINT("cmd_type   : %s\n", (item_info->cmd_type) ? "up" : "down");
-    ZXIC_COMM_PRINT("int_en     : %d\n", item_info->int_en);
-    ZXIC_COMM_PRINT("data_len   : %d\n", item_info->data_len);
-    ZXIC_COMM_PRINT("data_hddr  : 0x%08x\n", item_info->data_hddr);
-    ZXIC_COMM_PRINT("data_laddr : 0x%08x\n", item_info->data_laddr);
-
-    if (item_info->cmd_type == DPP_DTB_DIR_UP_TYPE)
-    {
-        if (DPP_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) == DPP_DTB_TAB_UP_USER_ADDR_TYPE)
-        {
-            ack_start_addr = DPP_DTB_TAB_UP_USER_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index);
-        }
-        ack_start_addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index);
-        element_start_addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) + DPP_DTB_ITEM_ACK_SIZE;
-    }
-    else
-    {
-        ack_start_addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index);
-        element_start_addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) + DPP_DTB_ITEM_ACK_SIZE;
-    }
-    ZXIC_COMM_PRINT("dtb data:\n");
-
-    ZXIC_COMM_PRINT("ack info:\n");
-    for(j = 0; j < 4; j++)
-    {
-        data  = ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(ack_start_addr + 4 * j)));
-        
-        ZXIC_COMM_PRINT("0x%08x  ",data);
-    }
-    ZXIC_COMM_PRINT("\n");
-    
-    for (i = 0; i < item_info->data_len; i++)
-    { 
-        data_addr = element_start_addr + 16 * i;//16字节为一行
-
-        ZXIC_COMM_PRINT("row_%d:", i);
-
-        for(j = 0; j < 4; j++)
-        {
-            data  = ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(data_addr + 4 * j)));
-            
-            ZXIC_COMM_PRINT("0x%08x  ",data);
-        }
-
-        ZXIC_COMM_PRINT("\n");
-    }
-
-    ZXIC_COMM_PRINT("dpp dtb info print end.\n");
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置下发配置数据信息
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列号，范围0-31 
-* @param   int_flag             中断标志，0-无，1-有 
-* @param   data_len             数据长度，单位32bit;
-* @param   p_data               待下发数据 
-* @param   p_item_index         返回使用的条目编号 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_down_info_set(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 int_flag,
-                    ZXIC_UINT32 data_len,
-                    ZXIC_UINT32 *p_data,
-                    ZXIC_UINT32 *p_item_index)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 queue_en = 0;
-    ZXIC_UINT32 ack_vale = 0;
-    ZXIC_UINT32 item_index = 0;
-    ZXIC_UINT32 unused_item_num = 0;
-    DPP_DTB_QUEUE_ITEM_INFO_T item_info = {0};
-    ZXIC_MUTEX_T *p_mutex = NULL;
-    
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), int_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), data_len, 4, 0xffc);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_item_index);
-
-    rc = dpp_dev_dtb_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_DTB, queue_id, &p_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_dtb_opr_mutex_get");
-
-    rc = zxic_comm_mutex_lock(p_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_lock");
-
-    /*
-     * 流程
-     * 0.检测队列是否使能
-     * 1.检测当前队列是否已初始化;
-     * 2.获取硬件队列剩余情况，大于0正常下发，等于0返回失败；
-     * 3.获取软件缓存空闲情况；
-     * 4.将下表配置数据填入buff中；
-     * 5.将ack字段填入0x11111100;
-     * 6.将数据信息填入硬件触发寄存器中;
-     *
-     */
-#if 0
-    if(dpp_dtb_mode_is_debug(dev))
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "the queue %d is open debug mode!", queue_id);
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
-        return DPP_RC_DTB_OPEN_DEBUG_MODE;
-    }
-#endif
-
-    rc = dpp_dtb_queue_enable_get(dev, queue_id, &queue_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_queue_enable_get", p_mutex);
-    if(!queue_en)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "the slot %d queue %d is not enable!", DEV_PCIE_SLOT(dev), queue_id);
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-        return DPP_RC_DTB_QUEUE_NOT_ENABLE;
-    }
-
-    if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0)
-    {
-        ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id);
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-        return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
-    }
-
-    if (data_len % 4 != 0)
-    {   
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-        /* 硬件规定数据必须是16字节为单位 */
-        return DPP_RC_DTB_PARA_INVALID;
-    }
-
-    rc = dpp_dtb_queue_unused_item_num_get(dev, queue_id, &unused_item_num);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_queue_unused_item_num_get", p_mutex);
-
-    if (unused_item_num == 0)
-    {
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-        return DPP_RC_DTB_QUEUE_ITEM_HW_EMPTY;
-    }
-
-    for (i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++)
-    {
-        item_index = DPP_DTB_TAB_DOWN_WR_INDEX_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) % DPP_DTB_QUEUE_ITEM_NUM_MAX;
-            
-        rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, item_index, 0, &ack_vale);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd", p_mutex);
-
-        DPP_DTB_TAB_DOWN_WR_INDEX_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id)++;
-
-        if ((ack_vale >> 8) == DPP_DTB_TAB_ACK_UNUSED_MASK)
-        {
-            break;
-        }
-    }
-
-    if (i == DPP_DTB_QUEUE_ITEM_NUM_MAX)
-    {
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-        return DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY;
-    }
-    
-    rc = dpp_dtb_item_buff_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, item_index, 0, data_len, p_data);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_item_buff_wr", p_mutex);
-
-    rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, item_index, 0, DPP_DTB_TAB_ACK_IS_USING_MASK);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr", p_mutex);
-
-    item_info.cmd_vld = 1;
-    item_info.cmd_type = DPP_DTB_DIR_DOWN_TYPE;
-    item_info.int_en = int_flag;
-    item_info.data_len = data_len / 4;
-    item_info.data_hddr = ((DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index)>>4)>>32) & 0xffffffff;
-    item_info.data_laddr = (DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index)>>4) & 0xffffffff;
-
-    if(item_info.data_len < DPP_DTB_LEN_MIN || item_info.data_len > DPP_DTB_DOWN_LEN)
-    {
-        ZXIC_COMM_PRINT("DTB DATA_LEN :0x%08x.\n",item_info.data_len);
-        rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, item_index, 0, DPP_DTB_TAB_ACK_UNUSED_MASK);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-        return DPP_RC_DTB_PARA_INVALID;
-    }
-
-    if(dpp_dtb_prt_get())
-    {
-        dpp_dtb_info_print(dev, queue_id, item_index,  &item_info);
-    }
-    
-    if(DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev)))
-    {
-        *p_item_index = item_index;
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-        return DPP_OK;
-    }
-
-    if(dpp_dtb_soft_perf_test_get())
-    {
-        *p_item_index = item_index;
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-        return DPP_OK;
-    }
-
-    rc = dpp_dtb_queue_item_info_set(dev, queue_id, &item_info);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_queue_item_info_set", p_mutex);
-    *p_item_index = item_index;
-
-    rc = zxic_comm_mutex_unlock(p_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-    
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 打印下表队列中指定元素的地址、ACK及下表中前768bit的数据
-* @param   dev_id       芯片的id号  
-* @param   queue_id     队列号，范围0-127    
-* @param   element_id   元素号，范围0-31  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2022/08/30
-************************************************************/
-ZXIC_UINT32 dpp_dtb_down_table_element_info_prt(DPP_DEV_T *dev,
-                                                ZXIC_UINT32 queue_id,
-                                                ZXIC_UINT32 element_id)
-{
-    ZXIC_UINT32 rc = 0;
-
-    ZXIC_UINT32 element_start_addr_h = 0;
-    ZXIC_UINT32 element_start_addr_l = 0;
-    ZXIC_UINT32 element_table_addr_h = 0;
-    ZXIC_UINT32 element_table_addr_l = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), element_id, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
-
-    rc = dpp_dtb_down_table_elemet_addr_get(dev, 
-                                queue_id, 
-                                element_id, 
-                                &element_start_addr_h, 
-                                &element_start_addr_l,
-                                &element_table_addr_h, 
-                                &element_table_addr_l);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_elemet_addr_get");
-
-    ZXIC_COMM_DBGCNT32_PRINT("slot_id", DEV_PCIE_SLOT(dev));
-    ZXIC_COMM_DBGCNT32_PRINT("queue_id", queue_id);
-    ZXIC_COMM_DBGCNT32_PRINT("element_id", element_id);
-    ZXIC_COMM_DBGCNT32_PRINT("element_start_addr_h", element_start_addr_h);
-    ZXIC_COMM_DBGCNT32_PRINT("element_start_addr_l", element_start_addr_l);
-    ZXIC_COMM_DBGCNT32_PRINT("element_table_addr_h", element_table_addr_h);
-    ZXIC_COMM_DBGCNT32_PRINT("element_table_addr_l", element_table_addr_l);
-    
-    /*打印element ack*/
-    rc = dpp_dtb_item_ack_prt(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_item_ack_prt");
-
-    rc = dpp_dtb_item_buff_prt(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id, 24);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_item_buff_prt");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 一个元素down成功状态检查
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列号，范围0-31 
-* @param   element_id           条目编号 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_down_success_status_check(DPP_DEV_T *dev,
-                                                  ZXIC_UINT32 queue_id,
-                                                  ZXIC_UINT32 element_id)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 rd_cnt = 0;
-    ZXIC_UINT32 ack_value = 0;
-    ZXIC_UINT32 success_flag = 0;
-    ZXIC_UINT32 dtb_interrupt_status = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), element_id, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
-
-    dtb_interrupt_status = dpp_dtb_interrupt_status_get();
-
-    if(DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev)))
-    {
-        rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
-        return rc;
-    }
-
-    if(dpp_dtb_soft_perf_test_get() || dpp_dtb_hardware_perf_test_get())
-    {
-        rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
-        return rc;
-    }
-    
-    if(dpp_dtb_debug_fun_get())
-    {
-        return DPP_OK;
-    }
-
-    while(!success_flag)
-    {
-        rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id, 0, &ack_value);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd");
-
-        ZXIC_COMM_TRACE_DEBUG("dpp_dtb_item_ack_rd ack_value:0x%08x\n", ack_value);
-
-        if (((ack_value >> 8) & 0xffffff) == DPP_DTB_TAB_DOWN_ACK_VLD_MASK)
-        {
-            success_flag = 1;
-            break;
-        }
-
-        if (rd_cnt > dpp_dtb_down_table_overtime_get())
-        {
-            ZXIC_COMM_TRACE_ERROR("Error!!! dpp dtb down slot [%d] vport [0x%x] queue [%d] item [%d] ack success is overtime!\n", DEV_PCIE_SLOT(dev), DEV_PCIE_VPORT(dev), queue_id, element_id);
-
-            ZXIC_COMM_PRINT("-------------------------------------------------------------------\n");
-            ZXIC_COMM_PRINT("                     dtb down table info                           \n");
-            ZXIC_COMM_PRINT("-------------------------------------------------------------------\n");
-            rc = dpp_dtb_down_table_element_info_prt(dev, queue_id, element_id);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_down_table_element_info_prt");
-
-            rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
-
-            ZXIC_COMM_PRINT("-------------------------------------------------------------------\n");
-            ZXIC_COMM_PRINT("                          dtb reg info                             \n");
-            ZXIC_COMM_PRINT("-------------------------------------------------------------------\n");
-
-            rc = diag_dpp_dtb_axi_last_operate_info_prt(dev);
-            ZXIC_COMM_CHECK_DEV_RC(0, rc, "diag_dpp_dtb_axi_last_operate_info_prt");
-
-            rc = diag_dpp_dtb_channels_state_info_prt(dev);
-            ZXIC_COMM_CHECK_DEV_RC(0, rc, "diag_dpp_dtb_channels_state_info_prt");
-
-            rc = diag_dpp_dtb_channels_axi_resp_err_cnt_prt(dev);
-            ZXIC_COMM_CHECK_DEV_RC(0, rc, "diag_dpp_dtb_channels_axi_resp_err_cnt_prt");
-
-            return DPP_RC_DTB_OVER_TIME;
-        }
-
-        rd_cnt++;
-        zxic_comm_udelay(1);
-    }
-
-    if (dtb_interrupt_status)
-    {
-        /*清中断*/
-        rc = dpp_dtb_finish_interrupt_event_state_clr(dev, queue_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_finish_interrupt_event_state_clr");
-    }
-
-    if ((ack_value & 0xff) != DPP_DTB_TAB_ACK_SUCCESS_MASK)
-    {
-        rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
-        return ack_value & 0xff;
-    }
-
-    rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
-
-    return rc;
-}
-
-#endif
-#if ZXIC_REAL("TAB_UP")
-/***********************************************************/
-/** dump队列空闲条目获取
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列号，范围0-31 
-* @param   p_item_index         返回使用的条目编号 
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_up_free_item_get(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 *p_item_index)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 ack_vale = 0;
-    ZXIC_UINT32 item_index = 0;
-    ZXIC_UINT32 unused_item_num = 0;
-    ZXIC_MUTEX_T *p_mutex = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_item_index);
-
-    rc = dpp_dev_dtb_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_DTB, queue_id, &p_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_dtb_opr_mutex_get");
-
-    rc = zxic_comm_mutex_lock(p_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_lock");
-
-    /*
-     * 流程
-     * 1.获取硬件队列剩余情况，大于0正常上送，等于0返回失败；
-     * 2.获取软件缓存空闲情况；
-     *
-     */
-    if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0)
-    {
-        ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id);
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-        return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
-    }
-    
-    rc = dpp_dtb_queue_unused_item_num_get(dev, queue_id, &unused_item_num);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_queue_unused_item_num_get", p_mutex);
-
-    if (unused_item_num == 0)
-    {
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-        return DPP_RC_DTB_QUEUE_ITEM_HW_EMPTY;
-    }
-
-    for (i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++)
-    {
-        item_index = DPP_DTB_TAB_UP_WR_INDEX_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) % DPP_DTB_QUEUE_ITEM_NUM_MAX;
-        
-        rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_UP_TYPE, item_index, 0, &ack_vale);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd", p_mutex);
-
-        DPP_DTB_TAB_UP_WR_INDEX_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id)++;
-
-        if ((ack_vale >> 8) == DPP_DTB_TAB_ACK_UNUSED_MASK)
-        {
-            break;
-        }
-    }
-
-    if (i == DPP_DTB_QUEUE_ITEM_NUM_MAX)
-    {
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-        return DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY;
-    }
-
-    rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, item_index, 0, DPP_DTB_TAB_ACK_IS_USING_MASK);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_item_buff_wr", p_mutex);
-
-    *p_item_index = item_index;
-
-    rc = zxic_comm_mutex_unlock(p_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-    
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取dump指定条目物理地址
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列编号,范围:0-127  
-* @param   item_index           条目编号,范围0-31  
-* @param   p_phy_haddr          物理地址高32bit  
-* @param   p_phy_laddr          物理地址低32bit  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_up_item_addr_get(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 item_index,
-                    ZXIC_UINT32 *p_phy_haddr,
-                    ZXIC_UINT32 *p_phy_laddr)
-{
-    ZXIC_ADDR_T addr = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_phy_haddr);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_phy_laddr);
-
-    if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0)
-    {
-        ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id);
-        return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
-    }
-    
-    if (DPP_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) == DPP_DTB_TAB_UP_USER_ADDR_TYPE)
-    {
-        addr = DPP_DTB_TAB_UP_USER_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index);
-    }
-    else
-    {
-        addr = DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) + DPP_DTB_ITEM_ACK_SIZE;
-    }
-    
-    
-    /*将地址转换成16字节为单位*/
-    // addr = addr >> 4;
-
-    *p_phy_haddr = (addr >> 32) & 0xffffffff;
-    *p_phy_laddr = addr & 0xffffffff;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取指定dump条目一定地址偏移的物理地址
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列编号,范围:0-127  
-* @param   item_index           条目编号,范围0-31  
-* @param   p_phy_haddr          物理地址高32bit  
-* @param   p_phy_laddr          物理地址低32bit  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_up_item_offset_addr_get(DPP_DEV_T *dev,
-                                                ZXIC_UINT32 queue_id,
-                                                ZXIC_UINT32 item_index,
-                                                ZXIC_UINT32 addr_offset,
-                                                ZXIC_UINT32 *p_phy_haddr,
-                                                ZXIC_UINT32 *p_phy_laddr)
-{
-    ZXIC_ADDR_T addr = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_phy_haddr);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_phy_laddr);
-
-    if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0)
-    {
-        ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id);
-        return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
-    }
-    
-    if (DPP_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) == DPP_DTB_TAB_UP_USER_ADDR_TYPE)
-    {
-        addr = DPP_DTB_TAB_UP_USER_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index);
-    }
-    else
-    {
-        addr = DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) + DPP_DTB_ITEM_ACK_SIZE;
-    }
-
-    addr = addr + addr_offset;
-
-    *p_phy_haddr = (addr >> 32) & 0xffffffff;
-    *p_phy_laddr = addr & 0xffffffff;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 设置dump指定条目空间地址，用于用户自定义空间传输
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列编号,范围:0-127  
-* @param   item_index           条目编号,范围0-31  
-* @param   phy_haddr            物理地址高  
-* @param   vir_laddr            虚拟地址低  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_up_item_user_addr_set(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 item_index,
-                    ZXIC_ADDR_T phy_addr,
-                    ZXIC_ADDR_T vir_addr)
-{
-    DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
-
-    p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev));
-    if (p_dtb_mgr == ZXIC_NULL)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n", DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST);
-        return DPP_RC_DTB_MGR_NOT_EXIST;
-    }
-    
-    if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0)
-    {
-        ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id);
-        return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
-    }
-
-    p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].phy_addr = phy_addr;
-    p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].vir_addr = vir_addr;
-    p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].user_flag = DPP_DTB_TAB_UP_USER_ADDR_TYPE;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 清除用户dump指定条目空间地址
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列编号,范围:0-127  
-* @param   item_index           条目编号,范围0-31   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_up_item_user_addr_clr(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 item_index)
-{
-    DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
-
-    p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev));
-    if (p_dtb_mgr == ZXIC_NULL)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n", DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST);
-        return DPP_RC_DTB_MGR_NOT_EXIST;
-    }
-    
-    if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0)
-    {
-        ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id);
-        return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
-    }
-
-    p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].phy_addr = 0;
-    p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].vir_addr = 0;
-    p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].user_flag = DPP_DTB_TAB_UP_NOUSER_ADDR_TYPE;
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** dump配置描述符信息设置
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列号，范围0-31 
-* @param   item_index           返回使用的条目编号 
-* @param   int_flag             中断标志，0-无，1-有 
-* @param   data_len             数据长度，单位32bit;
-* @param   desc_len             描述符长度，单位32bit;
-* @param   p_desc_data          待下发描述符 
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_up_info_set(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 item_index,
-                    ZXIC_UINT32 int_flag,
-                    ZXIC_UINT32 data_len,
-                    ZXIC_UINT32 desc_len,
-                    ZXIC_UINT32 *p_desc_data)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 queue_en = 0;
-    DPP_DTB_QUEUE_ITEM_INFO_T item_info = {0};
-    ZXIC_MUTEX_T *p_mutex = NULL;
-    
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), desc_len, 0, 0x400);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), int_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_desc_data);
-
-    rc = dpp_dev_dtb_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_DTB, queue_id, &p_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_dtb_opr_mutex_get");
-
-    rc = zxic_comm_mutex_lock(p_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_lock");
-
-    /*
-     * 流程
-     * 0.检测队列是否使能
-     * 1.获取硬件队列剩余情况，大于0正常下发，等于0返回失败；
-     * 2.获取软件缓存空闲情况；
-     * 3.将dump描述符写入buff中;
-     * 4.将ack字段填入0x11111100;
-     * 5.将数据信息填入硬件触发寄存器中;
-     *
-     */
-#if 0
-    if(dpp_dtb_mode_is_debug(dev))
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "the queue %d is open debug mode!", queue_id);
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
-        return DPP_RC_DTB_OPEN_DEBUG_MODE;
-    }
-#endif
-
-    rc = dpp_dtb_queue_enable_get(dev, queue_id, &queue_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_queue_enable_get", p_mutex);
-    if(!queue_en)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "the slot %d queue %d is not enable!", DEV_PCIE_SLOT(dev), queue_id);
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "the queue %d is not enable!", queue_id);
-        return DPP_RC_DTB_QUEUE_NOT_ENABLE;
-    }
-
-    if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0)
-    {
-        ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id);
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-        return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
-    }
-
-    if (desc_len % 4 != 0)
-    {   
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-        /* 硬件规定数据必须是16字节为单位 */
-        return DPP_RC_DTB_PARA_INVALID;
-    }
-
-    rc = dpp_dtb_item_buff_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, item_index, 0, desc_len, p_desc_data);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_item_buff_wr", p_mutex);
-
-
-    rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, item_index, 0, DPP_DTB_TAB_ACK_IS_USING_MASK);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr", p_mutex);
-
-
-    DPP_DTB_TAB_UP_DATA_LEN_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) = data_len;
-
-    item_info.cmd_vld = 1;
-    item_info.cmd_type = DPP_DTB_DIR_UP_TYPE;
-    item_info.int_en = int_flag;
-    item_info.data_len = desc_len / 4;
-    item_info.data_hddr = ((DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index)>>4) >> 32) & 0xffffffff;
-    item_info.data_laddr = (DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index)>>4) & 0xffffffff;
-
-    if(dpp_dtb_prt_get())
-    {
-        dpp_dtb_info_print(dev, queue_id, item_index,  &item_info);
-    }
-
-    if(DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev)))
-    {
-        rc = zxic_comm_mutex_unlock(p_mutex);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-        return DPP_OK;
-    }
-    
-    rc = dpp_dtb_queue_item_info_set(dev, queue_id, &item_info);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_dtb_queue_item_info_set", p_mutex);
-
-    rc = zxic_comm_mutex_unlock(p_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"zxic_comm_mutex_unlock");
-    
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 打印队列中指定元素的dump地址、ACK及下表中前768bit的数据
-* @param   dev_id       芯片的id号  
-* @param   queue_id     队列号，范围0-127    
-* @param   element_id   元素号，范围0-31  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2022/08/30
-************************************************************/
-ZXIC_UINT32 dpp_dtb_dump_table_element_info_prt(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 element_id)
-{
-    ZXIC_UINT32 rc = 0;
-
-    ZXIC_UINT32 element_start_addr_h = 0;
-    ZXIC_UINT32 element_start_addr_l = 0;
-    ZXIC_UINT32 element_dump_addr_h = 0;
-    ZXIC_UINT32 element_dump_addr_l = 0;
-    ZXIC_UINT32 element_table_info_addr_h = 0;
-    ZXIC_UINT32 element_table_info_addr_l = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), element_id, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
-
-    rc = dpp_dtb_dump_table_elemet_addr_get(dev, 
-                                            queue_id, 
-                                            element_id,
-                                            &element_start_addr_h,
-                                            &element_start_addr_l,
-                                            &element_dump_addr_h,
-                                            &element_dump_addr_l,
-                                            &element_table_info_addr_h,
-                                            &element_table_info_addr_l);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_dump_table_elemet_addr_get");
-    
-    ZXIC_COMM_DBGCNT32_PRINT("slot_id", DEV_PCIE_SLOT(dev));
-    ZXIC_COMM_DBGCNT32_PRINT("queue_id", queue_id);
-    ZXIC_COMM_DBGCNT32_PRINT("element_id", element_id);
-    ZXIC_COMM_DBGCNT32_PRINT("element_start_addr_h", element_start_addr_h);
-    ZXIC_COMM_DBGCNT32_PRINT("element_start_addr_l", element_start_addr_l);
-    ZXIC_COMM_DBGCNT32_PRINT("element_dump_addr_h", element_dump_addr_h);
-    ZXIC_COMM_DBGCNT32_PRINT("element_dump_addr_l", element_dump_addr_l);
-    ZXIC_COMM_DBGCNT32_PRINT("element_table_info_addr_h", element_table_info_addr_h);
-    ZXIC_COMM_DBGCNT32_PRINT("element_table_info_addr_l", element_table_info_addr_l);
-
-    /*打印element ack*/
-    rc = dpp_dtb_item_ack_prt(dev, queue_id, DPP_DTB_DIR_UP_TYPE, element_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_item_ack_prt");
-
-    rc = dpp_dtb_item_buff_prt(dev, queue_id, DPP_DTB_DIR_UP_TYPE, element_id, 32);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_item_buff_prt");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 一个元素dump成功状态检查
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列号，范围0-31 
-* @param   element_id           条目编号 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_up_success_status_check(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 element_id)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 rd_cnt = 0;
-    ZXIC_UINT32 ack_value = 0;
-    ZXIC_UINT32 success_flag = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), element_id, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
-
-    if(DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev)))
-    {
-        return rc;
-    }
-
-    if(dpp_dtb_soft_perf_test_get() || dpp_dtb_hardware_perf_test_get())
-    {
-        return rc;
-    }
-
-    while(!success_flag)
-    {
-        rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_UP_TYPE, element_id, 0, &ack_value);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd");
-
-        if ((((ack_value >> 8) & 0xffffff) == DPP_DTB_TAB_UP_ACK_VLD_MASK) && 
-             ((ack_value & 0xff) == DPP_DTB_TAB_ACK_SUCCESS_MASK))
-        {
-            success_flag = 1;
-            break;
-        }
-
-        if (rd_cnt > dpp_dtb_dump_table_overtime_get())
-        {
-            ZXIC_COMM_TRACE_ERROR("Error!!! dpp dtb dump slot [%d] vport [0x%x] queue [%d] item [%d] ack success is overtime!\n", DEV_PCIE_SLOT(dev), DEV_PCIE_VPORT(dev), queue_id, element_id);
-
-            ZXIC_COMM_PRINT("-------------------------------------------------------------------\n");
-            ZXIC_COMM_PRINT("                     dtb dump table info                           \n");
-            ZXIC_COMM_PRINT("-------------------------------------------------------------------\n");
-            rc = dpp_dtb_dump_table_element_info_prt(dev, queue_id, element_id);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_dump_table_element_info_prt");
-
-            rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
-
-            ZXIC_COMM_PRINT("-------------------------------------------------------------------\n");
-            ZXIC_COMM_PRINT("                          dtb reg info                             \n");
-            ZXIC_COMM_PRINT("-------------------------------------------------------------------\n");
-
-            rc = diag_dpp_dtb_axi_last_operate_info_prt(dev);
-            ZXIC_COMM_CHECK_DEV_RC(0, rc, "diag_dpp_dtb_axi_last_operate_info_prt");
-
-            rc = diag_dpp_dtb_channels_state_info_prt(dev);
-            ZXIC_COMM_CHECK_DEV_RC(0, rc, "diag_dpp_dtb_channels_state_info_prt");
-
-            rc = diag_dpp_dtb_channels_axi_resp_err_cnt_prt(dev);
-            ZXIC_COMM_CHECK_DEV_RC(0, rc, "diag_dpp_dtb_channels_axi_resp_err_cnt_prt");
-            
-            return DPP_ERR;
-        }
-
-        rd_cnt++;
-        zxic_comm_udelay(1);
-    }
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取dump数据
-* @param   dev_id               设备号，支持多芯片
-* @param   queue_id             队列号，范围0-31 
-* @param   item_index           数据对应的的条目编号 
-* @param   data_len             数据长度，单位32bit; 
-* @param   p_data               dump数据 
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_tab_up_data_get(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    ZXIC_UINT32 item_index,
-                    ZXIC_UINT32 data_len,
-                    ZXIC_UINT32 *p_data)
-{
-    ZXIC_UINT32 rc = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0, DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-
-    if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) == 0)
-    {
-        ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n", DEV_PCIE_SLOT(dev), queue_id);
-        return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
-    }
-
-    if(dpp_dtb_hardware_perf_test_get())
-    {
-        return rc;
-    }
-
-    rc = dpp_dtb_item_buff_rd(dev, 
-                    queue_id, 
-                    DPP_DTB_DIR_UP_TYPE, 
-                    item_index, 
-                    0, 
-                    data_len, 
-                    p_data);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_buff_rd");
-
-    if(dpp_dtb_debug_fun_get())
-    {
-        return DPP_OK;
-    }
-
-    rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, item_index, 0, DPP_DTB_TAB_ACK_UNUSED_MASK);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
-    
-    return DPP_OK;
-}
-
-#endif
-/***********************************************************/
-/** dtb队列down初始化
-* @param   dev_id           设备号，支持多芯片 
-* @param   queue_id         队列号
-* @param   p_queue_cfg      队列配置参数，具体见DPP_DTB_QUEUE_CFG_T结构体类型
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_down_init(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    DPP_DTB_QUEUE_CFG_T *p_queue_cfg)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 ack_vale = 0;
-    ZXIC_UINT32 tab_down_item_size = 0;
-    DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL;
-    
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_queue_cfg);
-
-    p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev));
-    if (p_dtb_mgr == ZXIC_NULL)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n", DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST);
-        return DPP_RC_DTB_MGR_NOT_EXIST;
-    }
-
-    /*
-     * 流程：
-     * 1.寻找空闲队列；
-     * 2.若找到：
-     *      1）配置硬件信息；
-     *      2）配置软件缓存信息；
-     *      3）初始化条目ack缓存信息,空闲约定:up-0x000000XX,down-0x000000XX；
-     *                            忙约定:up-0x111111XX,down-0x111111XX;
-     *                            完成约定:up-0x555555XX,down-0x5a5a5aXX;
-     * 3.若未找到：返回错误信息；
-     */
-
-    p_dtb_mgr->queue_info[queue_id].init_flag = 1;
-    p_dtb_mgr->queue_info[queue_id].slot_id = DEV_PCIE_SLOT(dev);
-    p_dtb_mgr->queue_info[queue_id].vport = DEV_PCIE_VPORT(dev);
-
-    tab_down_item_size = (p_queue_cfg->down_item_size == 0) ? DPP_DTB_ITEM_SIZE : p_queue_cfg->down_item_size;
-    
-    p_dtb_mgr->queue_info[queue_id].tab_down.item_size = tab_down_item_size;
-    p_dtb_mgr->queue_info[queue_id].tab_down.start_phy_addr = p_queue_cfg->down_start_phy_addr;
-    p_dtb_mgr->queue_info[queue_id].tab_down.start_vir_addr = p_queue_cfg->down_start_vir_addr;
-    p_dtb_mgr->queue_info[queue_id].tab_down.wr_index = 0;
-    p_dtb_mgr->queue_info[queue_id].tab_down.rd_index = 0;
-
-    for (i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++)
-    {
-        rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, i, 0, DPP_DTB_TAB_ACK_CHECK_VALUE);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
-    }
-
-    for(i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++)
-    {
-        rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, i, 0, &ack_vale);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd");
-        if(ack_vale != DPP_DTB_TAB_ACK_CHECK_VALUE)
-        {
-            ZXIC_COMM_PRINT("dtb slot [%d] queue [%d] down init faild, mem err!!!\n", DEV_PCIE_SLOT(dev), queue_id);
-            return DPP_RC_DTB_MEMORY_ALLOC_ERR;
-        }
-    }
-
-    ZXIC_COMM_PRINT("dtb slot [%d] queue [%d] down init success!!!\n", DEV_PCIE_SLOT(dev), queue_id);
-
-    ZXIC_COMM_MEMSET((ZXIC_UINT8 *)(p_queue_cfg->down_start_vir_addr), 0, tab_down_item_size * DPP_DTB_QUEUE_ITEM_NUM_MAX);
-    
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** dtb队列dump初始化
-* @param   dev_id           设备号，支持多芯片 
-* @param   queue_id         队列号
-* @param   p_queue_cfg      队列配置参数，具体见DPP_DTB_QUEUE_CFG_T结构体类型
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_dump_init(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id,
-                    DPP_DTB_QUEUE_CFG_T *p_queue_cfg)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 ack_vale = 0;
-    ZXIC_UINT32 tab_up_item_size = 0;
-    DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL;
-    ZXIC_UINT32 slot_id = 0;
-    
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_queue_cfg);
-
-    slot_id = (ZXIC_UINT32)DEV_PCIE_SLOT(dev);
-    ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_DEV_SLOT_MAX - 1);
-
-    p_dtb_mgr = dpp_dtb_mgr_get(slot_id, DEV_ID(dev));
-    if (p_dtb_mgr == ZXIC_NULL)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n", DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST);
-        return DPP_RC_DTB_MGR_NOT_EXIST;
-    }
-
-    /*
-     * 流程：
-     * 1.寻找空闲队列；
-     * 2.若找到：
-     *      1）配置硬件信息；
-     *      2）配置软件缓存信息；
-     *      3）初始化条目ack缓存信息,空闲约定:up-0x000000XX,down-0x000000XX；
-     *                            忙约定:up-0x111111XX,down-0x111111XX;
-     *                            完成约定:up-0x555555XX,down-0x5a5a5aXX;
-     * 3.若未找到：返回错误信息；
-     */
-
-    p_dtb_mgr->queue_info[queue_id].init_flag = 1;
-    p_dtb_mgr->queue_info[queue_id].slot_id = DEV_PCIE_SLOT(dev);
-    p_dtb_mgr->queue_info[queue_id].vport = DEV_PCIE_VPORT(dev);
-
-    tab_up_item_size = (p_queue_cfg->up_item_size == 0) ? DPP_DTB_ITEM_SIZE : p_queue_cfg->up_item_size;
-    
-    p_dtb_mgr->queue_info[queue_id].tab_up.item_size = tab_up_item_size;
-    p_dtb_mgr->queue_info[queue_id].tab_up.start_phy_addr = p_queue_cfg->up_start_phy_addr;
-    p_dtb_mgr->queue_info[queue_id].tab_up.start_vir_addr = p_queue_cfg->up_start_vir_addr;
-    p_dtb_mgr->queue_info[queue_id].tab_up.wr_index = 0;
-    p_dtb_mgr->queue_info[queue_id].tab_up.rd_index = 0;
-
-    for (i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++)
-    {
-        rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, i, 0, DPP_DTB_TAB_ACK_CHECK_VALUE);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
-    }
-
-    for(i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++)
-    {
-        rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_UP_TYPE, i, 0, &ack_vale);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd");
-        if(ack_vale != DPP_DTB_TAB_ACK_CHECK_VALUE)
-        {
-            ZXIC_COMM_PRINT("dtb slot [%d] queue [%d] init faild, mem err!!!\n", DEV_PCIE_SLOT(dev), queue_id);
-            return DPP_RC_DTB_MEMORY_ALLOC_ERR;
-        }
-    }
-
-    ZXIC_COMM_PRINT("dtb slot [%d] queue [%d] up init success!!!\n", DEV_PCIE_SLOT(dev), queue_id);
-
-    ZXIC_COMM_MEMSET((ZXIC_UINT8 *)(p_queue_cfg->up_start_vir_addr), 0, tab_up_item_size * DPP_DTB_QUEUE_ITEM_NUM_MAX);
-    
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** dtb队列down 空间地址配置
-* @param   channelId    dtb通道号 
-* @param   phyAddr      down物理地址
-* @param   virAddr      down虚拟地址
-* @param   size         空间大小 0:使用系统默认值16K+16
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_down_channel_addr_set(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 channelId, 
-                                          ZXIC_UINT64 phyAddr, 
-                                          ZXIC_UINT64 virAddr, 
-                                          ZXIC_UINT32 size)
-{
-    ZXIC_UINT32 rc = 0;
-
-    DPP_DTB_QUEUE_CFG_T down_queue_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-
-    down_queue_cfg.down_start_phy_addr = phyAddr;
-    down_queue_cfg.down_start_vir_addr = virAddr;
-    down_queue_cfg.down_item_size = size;
-
-   rc = dpp_dtb_queue_down_init(dev,
-                                channelId,
-                                &down_queue_cfg);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_down_init");
-
-    return rc;
-}
-
-/***********************************************************/
-/** dtb队列dump 空间地址配置
-* @param   channelId    dtb通道号 
-* @param   phyAddr      dump物理地址
-* @param   virAddr      dump虚拟地址
-* @param   size         空间大小
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_dump_channel_addr_set(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 channelId, 
-                                          ZXIC_UINT64 phyAddr, 
-                                          ZXIC_UINT64 virAddr, 
-                                          ZXIC_UINT32 size)
-{
-    ZXIC_UINT32 rc = 0;
-
-    DPP_DTB_QUEUE_CFG_T dump_queue_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-
-    dump_queue_cfg.up_start_phy_addr = phyAddr;
-    dump_queue_cfg.up_start_vir_addr = virAddr;
-    dump_queue_cfg.up_item_size = size;
-
-    rc = dpp_dtb_queue_dump_init(dev,
-                                 channelId,
-                                 &dump_queue_cfg);
-
-    return rc;
-}
-
-/***********************************************************/
-/** 释放队列资源
-* @param   dev_id           设备号，支持多芯片  
-* @param   queue_id         分配到的队列号;
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2021/02/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_id_free(DPP_DEV_T *dev,
-                    ZXIC_UINT32 queue_id)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 item_num = 0;
-    DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL;
-    
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev),queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-
-    p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev));
-    if (p_dtb_mgr == ZXIC_NULL)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n", DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST);
-        return DPP_RC_DTB_MGR_NOT_EXIST;
-    }
-
-    rc = dpp_dtb_queue_unused_item_num_get(dev, queue_id, &item_num);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_queue_unused_item_num_get");
-    
-    if (item_num != DPP_DTB_QUEUE_ITEM_NUM_MAX)
-    {
-        return DPP_RC_DTB_QUEUE_IS_WORKING;
-    }
-
-    p_dtb_mgr->queue_info[queue_id].init_flag = 0;
-
-    ZXIC_COMM_MEMSET(&(p_dtb_mgr->queue_info[queue_id].tab_up), 0, sizeof(DPP_DTB_TAB_UP_INFO_T));
-    ZXIC_COMM_MEMSET(&(p_dtb_mgr->queue_info[queue_id].tab_down), 0, sizeof(DPP_DTB_TAB_DOWN_INFO_T));
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** dtb初始化
-* @param   dev_id       设备号，支持多芯片   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  zab      @date  2022/08/30
-************************************************************/
-ZXIC_UINT32 dpp_dtb_init(DPP_DEV_T *dev)
-{
-    ZXIC_UINT32 rc = 0;
-    DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev));
-    if (p_dtb_mgr == ZXIC_NULL)
-    {
-        rc = dpp_dtb_mgr_create(DEV_PCIE_SLOT(dev), DEV_ID(dev));
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_mgr_create");
-
-        p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev));
-        if (p_dtb_mgr == ZXIC_NULL)
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n", DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST);
-            return DPP_RC_DTB_MGR_NOT_EXIST;
-        }
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 根据vport查找相应的队列号
-* @param   dev_id       设备号，支持多芯片   
-* @param   vport        vport信息
-* @param   p_queue_arr 找到到队列数组
-* @param   p_num          找到的队列个数
-* @return  
-* @remark  无
-* @see     
-* @author  cbb      @date  2023/09/13
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_id_search_by_vport(DPP_DEV_T *dev,
-                                             ZXIC_UINT32 *p_queue_arr,
-                                             ZXIC_UINT32 *p_num)
-{
-    ZXIC_UINT32 queue_id = 0;
-    ZXIC_UINT32 count = 0;
-
-    DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL;
-
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_queue_arr);
-
-    p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev));
-    if (p_dtb_mgr == ZXIC_NULL)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n", DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST);
-        return DPP_RC_DTB_MGR_NOT_EXIST;
-    }
-
-    for(queue_id = 0; queue_id < DPP_DTB_QUEUE_NUM_MAX; queue_id++)
-    {
-        if(DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id) != 0)
-        {
-            if(DEV_PCIE_VPORT(dev) == DPP_DTB_QUEUE_VPORT_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id))
-            {
-                p_queue_arr[count] = queue_id;
-                count++;
-            }
-        }
-    }
-
-    if (count == 0)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "slot %d ErrorCode[0x%x]: vport 0x%04x no queue not found!!!\n", 
-                                                   DEV_PCIE_SLOT(dev), DPP_RC_DTB_QUEUE_NOT_ALLOC, DEV_PCIE_VPORT(dev));
-        return DPP_RC_DTB_QUEUE_NOT_ALLOC;
-    }
-
-    *p_num = count;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 根据vport查找相应的队列号
-* @param   dev_id       设备号，支持多芯片   
-* @param   vport        vport信息
-* @param   p_queue_arr 找到到队列数组
-* @param   p_num          找到的队列个数
-* @return  
-* @remark  无
-* @see     
-* @author  cbb      @date  2023/09/13
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_id_get(ZXIC_UINT32 dev_id, DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *queue)
-{
-    DPP_DEV_T dev = {0};
-
-    ZXIC_UINT32 num    = 0;
-    ZXIC_UINT32 rc     = DPP_OK;
-
-    ZXIC_UINT32 queue_arr[DPP_DTB_QUEUE_NUM_MAX] = {0};
-
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(pf_info);
-
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
-
-    rc = dpp_dtb_queue_id_search_by_vport(&dev, queue_arr, &num);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_id_search_by_vport");
-
-    *queue = queue_arr[0];
-
-    return DPP_OK;
-}
-
-#endif
-#endif
+/**************************************************************
+* 版权所有(C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_dtb.c
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : zab
+* 完成日期 : 2022/08/26
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+#include "zxic_common.h"
+#include "dpp_dev.h"
+#include "dpp_type_api.h"
+#include "dpp_dtb_cfg.h"
+#include "dpp_dtb.h"
+#include "dpp_dtb_table.h"
+#include "dpp_hash.h"
+#include "dpp_dtb_reg.h"
+#include "dpp_reg_api.h"
+#include "dpp_reg_info.h"
+#include "dpp_se_api.h"
+
+#if ZXIC_REAL("DTB")
+
+ZXIC_CHAR *g_dpp_dtb_name[] = {
+	"DOWN TAB",
+	"UP TAB",
+};
+
+DPP_DTB_MGR_T *p_dpp_dtb_mgr[DPP_PCIE_SLOT_MAX][DPP_DEV_CHANNEL_MAX] = {
+	{ NULL }
+};
+
+/**dtb超时时间 单位s*/
+static ZXIC_UINT32 g_dtb_down_overtime = 10 * 200;
+static ZXIC_UINT32 g_dtb_dump_overtime = 6 * 60 * 200;
+
+/*配置dtb调试函数*/
+static ZXIC_UINT32 g_dtb_debug_fun_en;
+static ZXIC_UINT32 g_dtb_print_en;
+static ZXIC_UINT32 g_dtb_soft_perf_test;
+static ZXIC_UINT32 g_dtb_hardware_perf_test;
+
+/**使能dtb调试函数*/
+ZXIC_UINT32 dpp_dtb_debug_fun_enable(ZXIC_VOID)
+{
+	g_dtb_debug_fun_en = 1;
+	return 0;
+}
+
+/**去使能dtb调试函数*/
+ZXIC_UINT32 dpp_dtb_debug_fun_disable(ZXIC_VOID)
+{
+	g_dtb_debug_fun_en = 0;
+	return 0;
+}
+
+/**获取dtb调试函数*/
+ZXIC_UINT32 dpp_dtb_debug_fun_get(ZXIC_VOID)
+{
+	return g_dtb_debug_fun_en;
+}
+
+/**使能dtb打印函数*/
+ZXIC_UINT32 dpp_dtb_prt_enable(ZXIC_VOID)
+{
+	g_dtb_print_en = 1;
+	return 0;
+}
+
+/**去使能dtb打印函数*/
+ZXIC_UINT32 dpp_dtb_prt_disable(ZXIC_VOID)
+{
+	g_dtb_print_en = 0;
+	return 0;
+}
+
+/**获取dtb打印函数*/
+ZXIC_UINT32 dpp_dtb_prt_get(ZXIC_VOID)
+{
+	return g_dtb_print_en;
+}
+
+ZXIC_UINT32 dpp_dtb_soft_perf_test_set(ZXIC_UINT32 value)
+{
+	g_dtb_soft_perf_test = value;
+	return 0;
+}
+
+ZXIC_UINT32 dpp_dtb_soft_perf_test_get(ZXIC_VOID)
+{
+	return g_dtb_soft_perf_test;
+}
+
+ZXIC_UINT32 dpp_dtb_hardware_perf_test_set(ZXIC_UINT32 value)
+{
+	g_dtb_hardware_perf_test = value;
+	return 0;
+}
+
+ZXIC_UINT32 dpp_dtb_hardware_perf_test_get(ZXIC_VOID)
+{
+	return g_dtb_hardware_perf_test;
+}
+
+ZXIC_UINT32 dpp_dtb_down_table_overtime_set(ZXIC_UINT32 times_s)
+{
+	g_dtb_down_overtime = times_s;
+	return 0;
+}
+
+ZXIC_UINT32 dpp_dtb_down_table_overtime_get(ZXIC_VOID)
+{
+	return g_dtb_down_overtime;
+}
+
+ZXIC_UINT32 dpp_dtb_dump_table_overtime_set(ZXIC_UINT32 times_s)
+{
+	g_dtb_dump_overtime = times_s;
+	return 0;
+}
+
+ZXIC_UINT32 dpp_dtb_dump_table_overtime_get(ZXIC_VOID)
+{
+	return g_dtb_dump_overtime;
+}
+
+#if ZXIC_REAL("MGR")
+/***********************************************************/
+/** 创建DTB的管理结构
+ * @param   dev_id       设备号，支持多芯片
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_mgr_create(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id)
+{
+	ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_PCIE_SLOT_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+
+	if (p_dpp_dtb_mgr[slot_id][dev_id] != ZXIC_NULL) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id,
+				"slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n",
+				slot_id, DPP_RC_DTB_MGR_NOT_EXIST);
+		return DPP_RC_DTB_MGR_EXIST;
+	}
+
+	p_dpp_dtb_mgr[slot_id][dev_id] =
+			(DPP_DTB_MGR_T *)ZXIC_COMM_MALLOC(sizeof(DPP_DTB_MGR_T));
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_dpp_dtb_mgr[slot_id][dev_id]);
+
+	ZXIC_COMM_MEMSET(p_dpp_dtb_mgr[slot_id][dev_id], 0, sizeof(DPP_DTB_MGR_T));
+
+	ZXIC_COMM_PRINT("dpp_dtb_mgr_create:slot %d dev %d done!!!", slot_id,
+					dev_id);
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 注销DTB的管理结构
+ * @param   dev_id       设备号，支持多芯片
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_mgr_destory_all(ZXIC_VOID)
+{
+	ZXIC_UINT32 slot_id = 0;
+	ZXIC_UINT32 dev_id = 0;
+
+	for (slot_id = 0; slot_id < DPP_DEV_SLOT_MAX; slot_id++) {
+		for (dev_id = 0; dev_id < DPP_DEV_CHANNEL_MAX; dev_id++) {
+			dpp_dtb_mgr_destory(slot_id, dev_id);
+		}
+	}
+
+	return DPP_OK;
+}
+
+ZXIC_UINT32 dpp_dtb_mgr_destory(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id)
+{
+	ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_PCIE_SLOT_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+
+	if (p_dpp_dtb_mgr[slot_id][dev_id] != ZXIC_NULL) {
+		ZXIC_COMM_FREE(p_dpp_dtb_mgr[slot_id][dev_id]);
+		p_dpp_dtb_mgr[slot_id][dev_id] = ZXIC_NULL;
+		ZXIC_COMM_PRINT("dpp_dtb_mgr_destory:slot %d dev %d done!!!", slot_id,
+						dev_id);
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 重置DTB管理结构
+ * @param   dev_id       设备号，支持多芯片
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_mgr_reset(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id)
+{
+	ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_PCIE_SLOT_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+
+	if (p_dpp_dtb_mgr[slot_id][dev_id] == ZXIC_NULL) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id,
+				"slot %d ErrorCode[0x%x]: dtb manager is not exist!!!\n",
+				slot_id, DPP_RC_DTB_MGR_NOT_EXIST);
+		return DPP_RC_DTB_MGR_NOT_EXIST;
+	}
+
+	ZXIC_COMM_MEMSET(p_dpp_dtb_mgr[slot_id][dev_id], 0, sizeof(DPP_DTB_MGR_T));
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取DMA管理结构
+ * @param   dev_id               设备号，支持多芯片
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+DPP_DTB_MGR_T *dpp_dtb_mgr_get(ZXIC_UINT32 slot_id, ZXIC_UINT32 dev_id)
+{
+	if ((slot_id >= DPP_PCIE_SLOT_MAX) || (dev_id >= DPP_DEV_CHANNEL_MAX)) {
+		return ZXIC_NULL;
+	} else {
+		return p_dpp_dtb_mgr[slot_id][dev_id];
+	}
+}
+#endif
+
+#if ZXIC_REAL("QUEUE_ADDR")
+/***********************************************************/
+/** 获得下表队列中某元素的物理地址
+ * @param   dev_id                         设备号，支持多芯片
+ * @param   queue_id                       队列号0-127
+ * @param   element_id                     队列中元素号0-31
+ * @param   p_element_start_addr_h         元素起始高32位地址
+ * @param   p_element_start_addr_l         元素起始低32位地址
+ * @param   p_element_table_addr_h         下表内容开始高32位地址
+ * @param   p_element_table_addr_l         下表内容开始低32位地址
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32
+dpp_dtb_down_table_elemet_addr_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								   ZXIC_UINT32 element_id,
+								   ZXIC_UINT32 *p_element_start_addr_h,
+								   ZXIC_UINT32 *p_element_start_addr_l,
+								   ZXIC_UINT32 *p_element_table_addr_h,
+								   ZXIC_UINT32 *p_element_table_addr_l)
+{
+	ZXIC_UINT32 addr_h = 0;
+	ZXIC_UINT32 addr_l = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0,
+										DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), element_id, 0,
+										DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+
+	addr_h = (DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+											queue_id, element_id) >>
+			  32) &
+			 0xffffffff;
+	addr_l = DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+										   queue_id, element_id) &
+			 0xffffffff;
+
+	*p_element_start_addr_h = addr_h;
+	*p_element_start_addr_l = addr_l;
+
+	addr_h = ((DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+											 queue_id, element_id) +
+			   DPP_DTB_ITEM_ACK_SIZE) >>
+			  32) &
+			 0xffffffff;
+	addr_l = (DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+											queue_id, element_id) +
+			  DPP_DTB_ITEM_ACK_SIZE) &
+			 0xffffffff;
+
+	*p_element_table_addr_h = addr_h;
+	*p_element_table_addr_l = addr_l;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获得队列中某元素dump的物理地址
+ * @param   dev_id                         设备号，支持多芯片
+ * @param   queue_id                       队列号0-127
+ * @param   element_id                     队列中元素号0-31
+ * @param   p_element_start_addr_h         元素起始高32位地址
+ * @param   p_element_start_addr_l         元素起始低32位地址
+ * @param   p_element_dump_addr_h          dump描述符开始高32位地址
+ * @param   p_element_dump_addr_l          dump描述符开始低32位地址
+ * @param   p_element_table_info_addr_h    表内容开始高32位地址
+ * @param   p_element_table_info_addr_l    表内容开始低32位地址
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_dump_table_elemet_addr_get(
+		DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 element_id,
+		ZXIC_UINT32 *p_element_start_addr_h,
+		ZXIC_UINT32 *p_element_start_addr_l, ZXIC_UINT32 *p_element_dump_addr_h,
+		ZXIC_UINT32 *p_element_dump_addr_l,
+		ZXIC_UINT32 *p_element_table_info_addr_h,
+		ZXIC_UINT32 *p_element_table_info_addr_l)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 addr_h = 0;
+	ZXIC_UINT32 addr_l = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0,
+										DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), element_id, 0,
+										DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+
+	addr_h = ((DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+										   queue_id, element_id)) >>
+			  32) &
+			 0xffffffff;
+	addr_l = (DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+										  queue_id, element_id)) &
+			 0xffffffff;
+
+	*p_element_start_addr_h = addr_h;
+	*p_element_start_addr_l = addr_l;
+
+	addr_h = ((DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+										   queue_id, element_id) +
+			   DPP_DTB_ITEM_ACK_SIZE) >>
+			  32) &
+			 0xffffffff;
+	addr_l = (DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+										  queue_id, element_id) +
+			  DPP_DTB_ITEM_ACK_SIZE) &
+			 0xffffffff;
+
+	*p_element_dump_addr_h = addr_h;
+	*p_element_dump_addr_l = addr_l;
+
+	rc = dpp_dtb_tab_up_item_addr_get(dev, queue_id, element_id,
+									  p_element_table_info_addr_h,
+									  p_element_table_info_addr_l);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get");
+
+	return DPP_OK;
+}
+
+#endif
+
+#if ZXIC_REAL("MEM_RW")
+/***********************************************************/
+/** 内存32bits写入函数
+ * @param   dev_id           设备号，支持多芯片
+ * @param   addr             地址偏移
+ * @param   data             写入数据
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_wr32(DPP_DEV_T *dev, ZXIC_ADDR_T addr, ZXIC_UINT32 data)
+{
+	ZXIC_UINT32 value = data;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), data, 0, ZXIC_UINT32_MAX);
+
+	if (!zxic_comm_is_big_endian()) {
+		value = ZXIC_COMM_CONVERT32(value);
+	}
+
+	*((ZXIC_VOL ZXIC_UINT32 *)(addr)) = value;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 内存32bits读取函数
+ * @param   dev_id           设备号，支持多芯片
+ * @param   addr             读取地址
+ * @param   p_data           读取数据
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_rd32(DPP_DEV_T *dev, ZXIC_ADDR_T addr, ZXIC_UINT32 *p_data)
+{
+	ZXIC_UINT32 value = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+
+	// dpp_flush_cache();//片内DDR使用
+
+	value = *((ZXIC_VOL ZXIC_UINT32 *)(addr));
+
+	if (!zxic_comm_is_big_endian()) {
+		value = ZXIC_COMM_CONVERT32(value);
+	}
+
+	*p_data = value;
+
+	return DPP_OK;
+}
+#endif
+
+#if ZXIC_REAL("ACK_RW")
+/***********************************************************/
+/** 读取BD表条目信息
+ * @param   dev_id       芯片的id号
+ * @param   queue_id     队列号,范围0-127
+ * @param   dir_flag     方向,1-上送表项,0-下发表项
+ * @param   index        条目索引,范围0-31
+ * @param   pos          一个item里面的4个32位，pos对应的是第几个ZXICP_WORD32，
+ *                       取值为0，1，2，3
+ * @param   p_data       读取的数据,大端格式
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2019/11/2
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_item_ack_rd(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								ZXIC_UINT32 dir_flag, ZXIC_UINT32 index,
+								ZXIC_UINT32 pos, ZXIC_UINT32 *p_data)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_ADDR_T addr = 0;
+	ZXIC_UINT32 val = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), dir_flag, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), index, 0,
+							  DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pos, 0, 3);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+
+	if (DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+									queue_id) == 0) {
+		ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n",
+							  DEV_PCIE_SLOT(dev), queue_id);
+		return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
+	}
+
+	if (dir_flag == DPP_DTB_DIR_UP_TYPE) {
+		addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+										   queue_id, index) +
+			   pos * 4;
+	} else {
+		addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+											 queue_id, index) +
+			   pos * 4;
+	}
+
+	rc = dpp_dtb_rd32(dev, addr, &val);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_rd32");
+
+	*p_data = val;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 向BD表条目指定位置写入值
+ * @param   dev_id       芯片的id号
+ * @param   queue_id     队列号,范围0-127
+ * @param   dir_flag     方向,1-上送表项,0-下发表项
+ * @param   index        条目索引,范围0-31
+ * @param   pos          一个item里面的4个32位，pos对应的是第几个ZXICP_WORD32，
+ *                       取值为0，1，2，3
+ * @param   data         读取的数据,大端格式
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2019/11/2
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_item_ack_wr(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								ZXIC_UINT32 dir_flag, ZXIC_UINT32 index,
+								ZXIC_UINT32 pos, ZXIC_UINT32 data)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_ADDR_T addr = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), dir_flag, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), index, 0,
+							  DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pos, 0, 3);
+
+	if (DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+									queue_id) == 0) {
+		ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n",
+							  DEV_PCIE_SLOT(dev), queue_id);
+		return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
+	}
+
+	if (dir_flag == DPP_DTB_DIR_UP_TYPE) {
+		addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+										   queue_id, index) +
+			   pos * 4;
+	} else {
+		addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+											 queue_id, index) +
+			   pos * 4;
+	}
+
+	rc = dpp_dtb_wr32(dev, addr, data);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_wr32");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 打印队列指定条目ACK信息
+ * @param   dev_id       芯片的id号
+ * @param   queue_id     队列号，范围0-127
+ * @param   dir_flag     方向,0-down,1-up
+ * @param   index        条目索引
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2022/08/30
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_item_ack_prt(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								 ZXIC_UINT32 dir_flag, ZXIC_UINT32 index)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 ack_data[4] = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0,
+										DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), dir_flag, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), index, 0,
+										DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+
+	for (i = 0; i < DPP_DTB_ITEM_ACK_SIZE / 4; i++) {
+		rc = dpp_dtb_item_ack_rd(dev, queue_id, dir_flag, index, i,
+								 ack_data + i);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_dtb_item_ack_rd");
+	}
+
+	ZXIC_COMM_PRINT("\n=====> [%s] BD INFO:", g_dpp_dtb_name[dir_flag]);
+	ZXIC_COMM_PRINT("\n[ index : %u] : 0x%08x 0x%08x 0x%08x 0x%08x \n", index,
+					ack_data[0], ack_data[1], ack_data[2], ack_data[3]);
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 打印队列指定条目BUFF的数据
+ * @param   dev_id       芯片的id号
+ * @param   queue_id     队列号，范围0-127
+ * @param   dir_flag     方向,0-down,1-up
+ * @param   index        条目索引
+ * @param   len          读取数据长度 4字节为单位
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2022/08/30
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_item_buff_prt(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								  ZXIC_UINT32 dir_flag, ZXIC_UINT32 index,
+								  ZXIC_UINT32 len)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 j = 0;
+	ZXIC_UINT32 *p_item_buff = ZXIC_NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0,
+										DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), dir_flag, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), index, 0,
+										DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+
+	p_item_buff = ZXIC_COMM_MALLOC((len * sizeof(ZXIC_UINT32)) %
+								   ZXIC_COMM_WORD32_MASK);
+	if (p_item_buff == ZXIC_NULL) {
+		ZXIC_COMM_PRINT("Alloc dtb item buffer faild!!!\n");
+		return DPP_RC_DTB_MEMORY_ALLOC_ERR;
+	}
+
+	ZXIC_COMM_MEMSET(p_item_buff, 0, len * sizeof(ZXIC_UINT32));
+
+	rc = dpp_dtb_item_buff_rd(dev, queue_id, dir_flag, index, 0, len,
+							  p_item_buff);
+	ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE(DEV_ID(dev), rc, "dpp_dtb_item_buff_rd",
+									   p_item_buff);
+
+	ZXIC_COMM_PRINT("\n=====> [%s] BUFF INFO:", g_dpp_dtb_name[dir_flag]);
+	for (i = 0, j = 0; i < len; i++, j++) {
+		if (j % 4 == 0) {
+			ZXIC_COMM_PRINT("\n0x%08x ", (*(p_item_buff + i)));
+		} else {
+			ZXIC_COMM_PRINT("0x%08x ", (*(p_item_buff + i)));
+		}
+	}
+	ZXIC_COMM_PRINT("\n");
+
+	ZXIC_COMM_FREE(p_item_buff);
+
+	return DPP_OK;
+}
+
+#endif
+
+#if ZXIC_REAL("BUFF_RW")
+
+/***********************************************************/
+/** 读取dtb条目指向BUFF的数据
+ * @param   dev_id       芯片的id号
+ * @param   queue_id     队列号,范围0-127
+ * @param   dir_flag     方向,1-上送表项,0-下发表项
+ * @param   index        条目索引,范围0-31
+ * @param   pos          相对BUFF起始地址的偏移,单位32bit;
+ * @param   p_data       读取的数据,大端格式
+ * @param   len          读取数据长度,单位32bit;
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2019/11/2
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_item_buff_rd(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								 ZXIC_UINT32 dir_flag, ZXIC_UINT32 index,
+								 ZXIC_UINT32 pos, ZXIC_UINT32 len,
+								 ZXIC_UINT32 *p_data)
+{
+	ZXIC_ADDR_T addr = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), dir_flag, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), index, 0,
+							  DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pos, 0, 3);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+
+	if (DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+									queue_id) == 0) {
+		ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n",
+							  DEV_PCIE_SLOT(dev), queue_id);
+		return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
+	}
+
+	if (dir_flag == DPP_DTB_DIR_UP_TYPE) {
+		if (DPP_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(
+					DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) ==
+			DPP_DTB_TAB_UP_USER_ADDR_TYPE) {
+			addr = DPP_DTB_TAB_UP_USER_VIR_ADDR_GET(
+						   DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, index) +
+				   pos * 4;
+			DPP_DTB_TAB_UP_USER_ADDR_FLAG_SET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+											  queue_id, index,
+											  0); //为什么设置为0？
+		} else {
+			addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+											   queue_id, index) +
+				   DPP_DTB_ITEM_ACK_SIZE + pos * 4;
+		}
+	} else {
+		addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+											 queue_id, index) +
+			   DPP_DTB_ITEM_ACK_SIZE + pos * 4;
+	}
+
+	ZXIC_COMM_MEMCPY_S(p_data, len * 4, (ZXIC_UINT8 *)(addr), len * 4);
+
+	zxic_comm_swap((ZXIC_UINT8 *)p_data, len * 4);
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 向BD表条目指向的BUFF指定位置写入值
+ * @param   dev_id       芯片的id号
+ * @param   queue_id     队列号,范围0-127
+ * @param   dir_flag     方向,1-上送表项,0-下发表项
+ * @param   index        条目索引,范围0-31
+ * @param   pos          相对BUFF起始地址的偏移,单位32bit;
+ * @param   p_data       读取的数据,大端格式
+ * @param   len          写入数据长度,单位32bit;
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2019/11/2
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_item_buff_wr(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								 ZXIC_UINT32 dir_flag, ZXIC_UINT32 index,
+								 ZXIC_UINT32 pos, ZXIC_UINT32 len,
+								 ZXIC_UINT32 *p_data)
+{
+	ZXIC_ADDR_T addr = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), dir_flag, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), index, 0,
+							  DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pos, 0, 3);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+
+	if (DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+									queue_id) == 0) {
+		ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n",
+							  DEV_PCIE_SLOT(dev), queue_id);
+		return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
+	}
+
+	if (dir_flag == DPP_DTB_DIR_UP_TYPE) {
+		addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+										   queue_id, index) +
+			   DPP_DTB_ITEM_ACK_SIZE + pos * 4;
+	} else {
+		addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+											 queue_id, index) +
+			   DPP_DTB_ITEM_ACK_SIZE + pos * 4;
+	}
+
+	ZXIC_COMM_MEMCPY_S((ZXIC_UINT8 *)(addr), len * 4, p_data, len * 4);
+
+	// dpp_flush_cache();//片内ddr使用
+
+	return DPP_OK;
+}
+#endif
+
+#if ZXIC_REAL("API")
+#if ZXIC_REAL("TAB_DOWN")
+
+/** dtb info print*/
+ZXIC_UINT32 dpp_dtb_info_print(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+							   ZXIC_UINT32 item_index,
+							   DPP_DTB_QUEUE_ITEM_INFO_T *item_info)
+{
+	ZXIC_ADDR_T element_start_addr = 0;
+	ZXIC_ADDR_T ack_start_addr = 0;
+	ZXIC_ADDR_T data_addr = 0;
+	ZXIC_UINT32 data = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 j = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	ZXIC_COMM_PRINT(
+			"dpp_dtb_info_print: slot %d queue: %d, element:%d,  %s table info is:\n",
+			DEV_PCIE_SLOT(dev), queue_id, item_index,
+			(item_info->cmd_type) ? "up" : "down");
+	ZXIC_COMM_PRINT("cmd_vld    : %d\n", item_info->cmd_vld);
+	ZXIC_COMM_PRINT("cmd_type   : %s\n", (item_info->cmd_type) ? "up" : "down");
+	ZXIC_COMM_PRINT("int_en     : %d\n", item_info->int_en);
+	ZXIC_COMM_PRINT("data_len   : %d\n", item_info->data_len);
+	ZXIC_COMM_PRINT("data_hddr  : 0x%llx\n", item_info->data_hddr);
+	ZXIC_COMM_PRINT("data_laddr : 0x%llx\n", item_info->data_laddr);
+
+	if (item_info->cmd_type == DPP_DTB_DIR_UP_TYPE) {
+		if (DPP_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(
+					DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index) ==
+			DPP_DTB_TAB_UP_USER_ADDR_TYPE) {
+			ack_start_addr = DPP_DTB_TAB_UP_USER_VIR_ADDR_GET(
+					DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index);
+		}
+		ack_start_addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(
+				DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index);
+		element_start_addr = DPP_DTB_TAB_UP_VIR_ADDR_GET(DEV_PCIE_SLOT(dev),
+														 DEV_ID(dev), queue_id,
+														 item_index) +
+							 DPP_DTB_ITEM_ACK_SIZE;
+	} else {
+		ack_start_addr = DPP_DTB_TAB_DOWN_VIR_ADDR_GET(
+				DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id, item_index);
+		element_start_addr =
+				DPP_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+											  queue_id, item_index) +
+				DPP_DTB_ITEM_ACK_SIZE;
+	}
+	ZXIC_COMM_PRINT("dtb data:\n");
+
+	ZXIC_COMM_PRINT("ack info:\n");
+	for (j = 0; j < 4; j++) {
+		data = ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(ack_start_addr + 4 * j)));
+
+		ZXIC_COMM_PRINT("0x%08x  ", data);
+	}
+	ZXIC_COMM_PRINT("\n");
+
+	for (i = 0; i < item_info->data_len; i++) {
+		data_addr = element_start_addr + 16 * i; // 16字节为一行
+
+		ZXIC_COMM_PRINT("row_%d:", i);
+
+		for (j = 0; j < 4; j++) {
+			data = ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(data_addr + 4 * j)));
+
+			ZXIC_COMM_PRINT("0x%08x  ", data);
+		}
+
+		ZXIC_COMM_PRINT("\n");
+	}
+
+	ZXIC_COMM_PRINT("dpp dtb info print end.\n");
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置下发配置数据信息
+ * @param   dev_id               设备号，支持多芯片
+ * @param   queue_id             队列号，范围0-31
+ * @param   int_flag             中断标志，0-无，1-有
+ * @param   data_len             数据长度，单位32bit;
+ * @param   p_data               待下发数据
+ * @param   p_item_index         返回使用的条目编号
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_down_info_set(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									  ZXIC_UINT32 int_flag,
+									  ZXIC_UINT32 data_len, ZXIC_UINT32 *p_data,
+									  ZXIC_UINT32 *p_item_index)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 queue_en = 0;
+	ZXIC_UINT32 ack_vale = 0;
+	ZXIC_UINT32 item_index = 0;
+	ZXIC_UINT32 unused_item_num = 0;
+	DPP_DTB_QUEUE_ITEM_INFO_T item_info = { 0 };
+	ZXIC_MUTEX_T *p_mutex = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), int_flag, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), data_len, 4, 0xffc);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_item_index);
+
+	rc = dpp_dev_dtb_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_DTB, queue_id,
+								   &p_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_dtb_opr_mutex_get");
+
+	rc = zxic_comm_mutex_lock(p_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_lock");
+
+	/*
+     * 流程
+     * 0.检测队列是否使能
+     * 1.检测当前队列是否已初始化;
+     * 2.获取硬件队列剩余情况，大于0正常下发，等于0返回失败；
+     * 3.获取软件缓存空闲情况；
+     * 4.将下表配置数据填入buff中；
+     * 5.将ack字段填入0x11111100;
+     * 6.将数据信息填入硬件触发寄存器中;
+     *
+     */
+
+	rc = dpp_dtb_queue_enable_get(dev, queue_id, &queue_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+			DEV_ID(dev), rc, "dpp_dtb_queue_enable_get", p_mutex);
+	if (!queue_en) {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+								  "the slot %d queue %d is not enable!",
+								  DEV_PCIE_SLOT(dev), queue_id);
+		rc = zxic_comm_mutex_unlock(p_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+		return DPP_RC_DTB_QUEUE_NOT_ENABLE;
+	}
+
+	if (DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+									queue_id) == 0) {
+		ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n",
+							  DEV_PCIE_SLOT(dev), queue_id);
+		rc = zxic_comm_mutex_unlock(p_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+		return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
+	}
+
+	if (data_len % 4 != 0) {
+		rc = zxic_comm_mutex_unlock(p_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+		/* 硬件规定数据必须是16字节为单位 */
+		return DPP_RC_DTB_PARA_INVALID;
+	}
+
+	rc = dpp_dtb_queue_unused_item_num_get(dev, queue_id, &unused_item_num);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+			DEV_ID(dev), rc, "dpp_dtb_queue_unused_item_num_get", p_mutex);
+
+	if (unused_item_num == 0) {
+		rc = zxic_comm_mutex_unlock(p_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+		return DPP_RC_DTB_QUEUE_ITEM_HW_EMPTY;
+	}
+
+	for (i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++) {
+		item_index = DPP_DTB_TAB_DOWN_WR_INDEX_GET(DEV_PCIE_SLOT(dev),
+												   DEV_ID(dev), queue_id) %
+					 DPP_DTB_QUEUE_ITEM_NUM_MAX;
+
+		rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE,
+								 item_index, 0, &ack_vale);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc,
+												"dpp_dtb_item_ack_rd", p_mutex);
+
+		DPP_DTB_TAB_DOWN_WR_INDEX_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id)
+		++;
+
+		if ((ack_vale >> 8) == DPP_DTB_TAB_ACK_UNUSED_MASK) {
+			break;
+		}
+	}
+
+	if (i == DPP_DTB_QUEUE_ITEM_NUM_MAX) {
+		rc = zxic_comm_mutex_unlock(p_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+		return DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY;
+	}
+
+	rc = dpp_dtb_item_buff_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, item_index,
+							  0, data_len, p_data);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc,
+											"dpp_dtb_item_buff_wr", p_mutex);
+
+	rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, item_index,
+							 0, DPP_DTB_TAB_ACK_IS_USING_MASK);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc,
+											"dpp_dtb_item_ack_wr", p_mutex);
+
+	item_info.cmd_vld = 1;
+	item_info.cmd_type = DPP_DTB_DIR_DOWN_TYPE;
+	item_info.int_en = int_flag;
+	item_info.data_len = data_len / 4;
+	item_info.data_hddr =
+			((DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+											queue_id, item_index) >>
+			  4) >>
+			 32) &
+			0xffffffff;
+	item_info.data_laddr =
+			(DPP_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+										   queue_id, item_index) >>
+			 4) &
+			0xffffffff;
+
+	if (item_info.data_len < DPP_DTB_LEN_MIN ||
+		item_info.data_len > DPP_DTB_DOWN_LEN) {
+		ZXIC_COMM_PRINT("DTB DATA_LEN :0x%08x.\n", item_info.data_len);
+		rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE,
+								 item_index, 0, DPP_DTB_TAB_ACK_UNUSED_MASK);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
+		rc = zxic_comm_mutex_unlock(p_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+		return DPP_RC_DTB_PARA_INVALID;
+	}
+
+	if (dpp_dtb_prt_get()) {
+		dpp_dtb_info_print(dev, queue_id, item_index, &item_info);
+	}
+
+	if (DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev))) {
+		*p_item_index = item_index;
+		rc = zxic_comm_mutex_unlock(p_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+		return DPP_OK;
+	}
+
+	if (dpp_dtb_soft_perf_test_get()) {
+		*p_item_index = item_index;
+		rc = zxic_comm_mutex_unlock(p_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+		return DPP_OK;
+	}
+
+	rc = dpp_dtb_queue_item_info_set(dev, queue_id, &item_info);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+			DEV_ID(dev), rc, "dpp_dtb_queue_item_info_set", p_mutex);
+	*p_item_index = item_index;
+
+	rc = zxic_comm_mutex_unlock(p_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 打印下表队列中指定元素的地址、ACK及下表中前768bit的数据
+ * @param   dev_id       芯片的id号
+ * @param   queue_id     队列号，范围0-127
+ * @param   element_id   元素号，范围0-31
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2022/08/30
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_down_table_element_info_prt(DPP_DEV_T *dev,
+												ZXIC_UINT32 queue_id,
+												ZXIC_UINT32 element_id)
+{
+	ZXIC_UINT32 rc = 0;
+
+	ZXIC_UINT32 element_start_addr_h = 0;
+	ZXIC_UINT32 element_start_addr_l = 0;
+	ZXIC_UINT32 element_table_addr_h = 0;
+	ZXIC_UINT32 element_table_addr_l = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0,
+										DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), element_id, 0,
+										DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+
+	rc = dpp_dtb_down_table_elemet_addr_get(dev, queue_id, element_id,
+											&element_start_addr_h,
+											&element_start_addr_l,
+											&element_table_addr_h,
+											&element_table_addr_l);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_dtb_elemet_addr_get");
+
+	ZXIC_COMM_DBGCNT32_PRINT("slot_id", DEV_PCIE_SLOT(dev));
+	ZXIC_COMM_DBGCNT32_PRINT("queue_id", queue_id);
+	ZXIC_COMM_DBGCNT32_PRINT("element_id", element_id);
+	ZXIC_COMM_DBGCNT32_PRINT("element_start_addr_h", element_start_addr_h);
+	ZXIC_COMM_DBGCNT32_PRINT("element_start_addr_l", element_start_addr_l);
+	ZXIC_COMM_DBGCNT32_PRINT("element_table_addr_h", element_table_addr_h);
+	ZXIC_COMM_DBGCNT32_PRINT("element_table_addr_l", element_table_addr_l);
+
+	/*打印element ack*/
+	rc = dpp_dtb_item_ack_prt(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_item_ack_prt");
+
+	rc = dpp_dtb_item_buff_prt(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id,
+							   24);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_item_buff_prt");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 一个元素down成功状态检查
+ * @param   dev_id               设备号，支持多芯片
+ * @param   queue_id             队列号，范围0-31
+ * @param   element_id           条目编号
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_down_success_status_check(DPP_DEV_T *dev,
+												  ZXIC_UINT32 queue_id,
+												  ZXIC_UINT32 element_id)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 rd_cnt = 0;
+	ZXIC_UINT32 ack_value = 0;
+	ZXIC_UINT32 success_flag = 0;
+	ZXIC_UINT32 dtb_interrupt_status = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), element_id, 0,
+							  DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+
+	dtb_interrupt_status = dpp_dtb_interrupt_status_get();
+
+	if (DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev))) {
+		rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE,
+								 element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
+		return rc;
+	}
+
+	if (dpp_dtb_soft_perf_test_get() || dpp_dtb_hardware_perf_test_get()) {
+		rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE,
+								 element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
+		return rc;
+	}
+
+	if (dpp_dtb_debug_fun_get()) {
+		return DPP_OK;
+	}
+
+	while (!success_flag) {
+		rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE,
+								 element_id, 0, &ack_value);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd");
+
+		ZXIC_COMM_TRACE_DEBUG("dpp_dtb_item_ack_rd ack_value:0x%08x\n",
+							  ack_value);
+
+		if (((ack_value >> 8) & 0xffffff) == DPP_DTB_TAB_DOWN_ACK_VLD_MASK) {
+			success_flag = 1;
+			break;
+		}
+
+		if (rd_cnt > dpp_dtb_down_table_overtime_get()) {
+			ZXIC_COMM_TRACE_ERROR(
+					"Error!!! dpp dtb down slot [%d] vport [0x%x] queue [%d] item [%d] ack success is overtime!\n",
+					DEV_PCIE_SLOT(dev), DEV_PCIE_VPORT(dev), queue_id,
+					element_id);
+
+			rc = dpp_dtb_down_table_element_info_prt(dev, queue_id, element_id);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+								   "dpp_dtb_down_table_element_info_prt");
+
+			rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE,
+									 element_id, 0,
+									 DPP_DTB_TAB_ACK_UNUSED_MASK);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
+
+			return DPP_ERR;
+		}
+
+		rd_cnt++;
+		zxic_comm_delay(5);
+	}
+
+	if (dtb_interrupt_status) {
+		/*清中断*/
+		rc = dpp_dtb_finish_interrupt_event_state_clr(dev, queue_id);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(
+				DEV_ID(dev), rc, "dpp_dtb_finish_interrupt_event_state_clr");
+	}
+
+	if ((ack_value & 0xff) != DPP_DTB_TAB_ACK_SUCCESS_MASK) {
+		rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE,
+								 element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
+		return ack_value & 0xff;
+	}
+
+	rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, element_id,
+							 0, DPP_DTB_TAB_ACK_UNUSED_MASK);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
+
+	return rc;
+}
+
+#endif
+#if ZXIC_REAL("TAB_UP")
+/***********************************************************/
+/** dump队列空闲条目获取
+ * @param   dev_id               设备号，支持多芯片
+ * @param   queue_id             队列号，范围0-31
+ * @param   p_item_index         返回使用的条目编号
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_up_free_item_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+										 ZXIC_UINT32 *p_item_index)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 ack_vale = 0;
+	ZXIC_UINT32 item_index = 0;
+	ZXIC_UINT32 unused_item_num = 0;
+	ZXIC_MUTEX_T *p_mutex = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_item_index);
+
+	rc = dpp_dev_dtb_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_DTB, queue_id,
+								   &p_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_dtb_opr_mutex_get");
+
+	rc = zxic_comm_mutex_lock(p_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_lock");
+
+	/*
+     * 流程
+     * 1.获取硬件队列剩余情况，大于0正常上送，等于0返回失败；
+     * 2.获取软件缓存空闲情况；
+     *
+     */
+	if (DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+									queue_id) == 0) {
+		ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n",
+							  DEV_PCIE_SLOT(dev), queue_id);
+		rc = zxic_comm_mutex_unlock(p_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+		return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
+	}
+
+	rc = dpp_dtb_queue_unused_item_num_get(dev, queue_id, &unused_item_num);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+			DEV_ID(dev), rc, "dpp_dtb_queue_unused_item_num_get", p_mutex);
+
+	if (unused_item_num == 0) {
+		rc = zxic_comm_mutex_unlock(p_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+		return DPP_RC_DTB_QUEUE_ITEM_HW_EMPTY;
+	}
+
+	for (i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++) {
+		item_index = DPP_DTB_TAB_UP_WR_INDEX_GET(DEV_PCIE_SLOT(dev),
+												 DEV_ID(dev), queue_id) %
+					 DPP_DTB_QUEUE_ITEM_NUM_MAX;
+
+		rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_UP_TYPE, item_index,
+								 0, &ack_vale);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc,
+												"dpp_dtb_item_ack_rd", p_mutex);
+
+		DPP_DTB_TAB_UP_WR_INDEX_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id)
+		++;
+
+		if ((ack_vale >> 8) == DPP_DTB_TAB_ACK_UNUSED_MASK) {
+			break;
+		}
+	}
+
+	if (i == DPP_DTB_QUEUE_ITEM_NUM_MAX) {
+		rc = zxic_comm_mutex_unlock(p_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+		return DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY;
+	}
+
+	rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, item_index, 0,
+							 DPP_DTB_TAB_ACK_IS_USING_MASK);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc,
+											"dpp_dtb_item_buff_wr", p_mutex);
+
+	*p_item_index = item_index;
+
+	rc = zxic_comm_mutex_unlock(p_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取dump指定条目物理地址
+ * @param   dev_id               设备号，支持多芯片
+ * @param   queue_id             队列编号,范围:0-127
+ * @param   item_index           条目编号,范围0-31
+ * @param   p_phy_haddr          物理地址高32bit
+ * @param   p_phy_laddr          物理地址低32bit
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_up_item_addr_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+										 ZXIC_UINT32 item_index,
+										 ZXIC_UINT32 *p_phy_haddr,
+										 ZXIC_UINT32 *p_phy_laddr)
+{
+	ZXIC_ADDR_T addr = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0,
+							  DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_phy_haddr);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_phy_laddr);
+
+	if (DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+									queue_id) == 0) {
+		ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n",
+							  DEV_PCIE_SLOT(dev), queue_id);
+		return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
+	}
+
+	if (DPP_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+											  queue_id, item_index) ==
+		DPP_DTB_TAB_UP_USER_ADDR_TYPE) {
+		addr = DPP_DTB_TAB_UP_USER_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+												queue_id, item_index);
+	} else {
+		addr = DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+										   queue_id, item_index) +
+			   DPP_DTB_ITEM_ACK_SIZE;
+	}
+
+	/*将地址转换成16字节为单位*/
+	// addr = addr >> 4;
+
+	*p_phy_haddr = (addr >> 32) & 0xffffffff;
+	*p_phy_laddr = addr & 0xffffffff;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取指定dump条目一定地址偏移的物理地址
+ * @param   dev_id               设备号，支持多芯片
+ * @param   queue_id             队列编号,范围:0-127
+ * @param   item_index           条目编号,范围0-31
+ * @param   p_phy_haddr          物理地址高32bit
+ * @param   p_phy_laddr          物理地址低32bit
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_up_item_offset_addr_get(DPP_DEV_T *dev,
+												ZXIC_UINT32 queue_id,
+												ZXIC_UINT32 item_index,
+												ZXIC_UINT32 addr_offset,
+												ZXIC_UINT32 *p_phy_haddr,
+												ZXIC_UINT32 *p_phy_laddr)
+{
+	ZXIC_ADDR_T addr = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0,
+							  DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_phy_haddr);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_phy_laddr);
+
+	if (DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+									queue_id) == 0) {
+		ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n",
+							  DEV_PCIE_SLOT(dev), queue_id);
+		return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
+	}
+
+	if (DPP_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+											  queue_id, item_index) ==
+		DPP_DTB_TAB_UP_USER_ADDR_TYPE) {
+		addr = DPP_DTB_TAB_UP_USER_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+												queue_id, item_index);
+	} else {
+		addr = DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+										   queue_id, item_index) +
+			   DPP_DTB_ITEM_ACK_SIZE;
+	}
+
+	addr = addr + addr_offset;
+
+	*p_phy_haddr = (addr >> 32) & 0xffffffff;
+	*p_phy_laddr = addr & 0xffffffff;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 设置dump指定条目空间地址，用于用户自定义空间传输
+ * @param   dev_id               设备号，支持多芯片
+ * @param   queue_id             队列编号,范围:0-127
+ * @param   item_index           条目编号,范围0-31
+ * @param   phy_haddr            物理地址高
+ * @param   vir_laddr            虚拟地址低
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_up_item_user_addr_set(DPP_DEV_T *dev,
+											  ZXIC_UINT32 queue_id,
+											  ZXIC_UINT32 item_index,
+											  ZXIC_ADDR_T phy_addr,
+											  ZXIC_ADDR_T vir_addr)
+{
+	DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0,
+							  DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+
+	p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev));
+	if (p_dtb_mgr == ZXIC_NULL) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev),
+				"slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n",
+				DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST);
+		return DPP_RC_DTB_MGR_NOT_EXIST;
+	}
+
+	if (DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+									queue_id) == 0) {
+		ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n",
+							  DEV_PCIE_SLOT(dev), queue_id);
+		return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
+	}
+
+	p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].phy_addr =
+			phy_addr;
+	p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].vir_addr =
+			vir_addr;
+	p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].user_flag =
+			DPP_DTB_TAB_UP_USER_ADDR_TYPE;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 清除用户dump指定条目空间地址
+ * @param   dev_id               设备号，支持多芯片
+ * @param   queue_id             队列编号,范围:0-127
+ * @param   item_index           条目编号,范围0-31
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_up_item_user_addr_clr(DPP_DEV_T *dev,
+											  ZXIC_UINT32 queue_id,
+											  ZXIC_UINT32 item_index)
+{
+	DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0,
+							  DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+
+	p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev));
+	if (p_dtb_mgr == ZXIC_NULL) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev),
+				"slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n",
+				DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST);
+		return DPP_RC_DTB_MGR_NOT_EXIST;
+	}
+
+	if (DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+									queue_id) == 0) {
+		ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n",
+							  DEV_PCIE_SLOT(dev), queue_id);
+		return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
+	}
+
+	p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].phy_addr = 0;
+	p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].vir_addr = 0;
+	p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].user_flag =
+			DPP_DTB_TAB_UP_NOUSER_ADDR_TYPE;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** dump配置描述符信息设置
+ * @param   dev_id               设备号，支持多芯片
+ * @param   queue_id             队列号，范围0-31
+ * @param   item_index           返回使用的条目编号
+ * @param   int_flag             中断标志，0-无，1-有
+ * @param   data_len             数据长度，单位32bit;
+ * @param   desc_len             描述符长度，单位32bit;
+ * @param   p_desc_data          待下发描述符
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_up_info_set(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									ZXIC_UINT32 item_index,
+									ZXIC_UINT32 int_flag, ZXIC_UINT32 data_len,
+									ZXIC_UINT32 desc_len,
+									ZXIC_UINT32 *p_desc_data)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 queue_en = 0;
+	DPP_DTB_QUEUE_ITEM_INFO_T item_info = { 0 };
+	ZXIC_MUTEX_T *p_mutex = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0,
+							  DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), desc_len, 0, 0x400);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), int_flag, 0, 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_desc_data);
+
+	rc = dpp_dev_dtb_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_DTB, queue_id,
+								   &p_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_dtb_opr_mutex_get");
+
+	rc = zxic_comm_mutex_lock(p_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_lock");
+
+	/*
+     * 流程
+     * 0.检测队列是否使能
+     * 1.获取硬件队列剩余情况，大于0正常下发，等于0返回失败；
+     * 2.获取软件缓存空闲情况；
+     * 3.将dump描述符写入buff中;
+     * 4.将ack字段填入0x11111100;
+     * 5.将数据信息填入硬件触发寄存器中;
+     *
+     */
+
+	rc = dpp_dtb_queue_enable_get(dev, queue_id, &queue_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+			DEV_ID(dev), rc, "dpp_dtb_queue_enable_get", p_mutex);
+	if (!queue_en) {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+								  "the slot %d queue %d is not enable!",
+								  DEV_PCIE_SLOT(dev), queue_id);
+		rc = zxic_comm_mutex_unlock(p_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "the queue %d is not enable!",
+								  queue_id);
+		return DPP_RC_DTB_QUEUE_NOT_ENABLE;
+	}
+
+	if (DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+									queue_id) == 0) {
+		ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n",
+							  DEV_PCIE_SLOT(dev), queue_id);
+		rc = zxic_comm_mutex_unlock(p_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+		return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
+	}
+
+	if (desc_len % 4 != 0) {
+		rc = zxic_comm_mutex_unlock(p_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+		/* 硬件规定数据必须是16字节为单位 */
+		return DPP_RC_DTB_PARA_INVALID;
+	}
+
+	rc = dpp_dtb_item_buff_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, item_index, 0,
+							  desc_len, p_desc_data);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc,
+											"dpp_dtb_item_buff_wr", p_mutex);
+
+	rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, item_index, 0,
+							 DPP_DTB_TAB_ACK_IS_USING_MASK);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc,
+											"dpp_dtb_item_ack_wr", p_mutex);
+
+	DPP_DTB_TAB_UP_DATA_LEN_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev), queue_id,
+								item_index) = data_len;
+
+	item_info.cmd_vld = 1;
+	item_info.cmd_type = DPP_DTB_DIR_UP_TYPE;
+	item_info.int_en = int_flag;
+	item_info.data_len = desc_len / 4;
+	item_info.data_hddr =
+			((DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+										  queue_id, item_index) >>
+			  4) >>
+			 32) &
+			0xffffffff;
+	item_info.data_laddr =
+			(DPP_DTB_TAB_UP_PHY_ADDR_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+										 queue_id, item_index) >>
+			 4) &
+			0xffffffff;
+
+	if (dpp_dtb_prt_get()) {
+		dpp_dtb_info_print(dev, queue_id, item_index, &item_info);
+	}
+
+	if (DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev))) {
+		rc = zxic_comm_mutex_unlock(p_mutex);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+		return DPP_OK;
+	}
+
+	rc = dpp_dtb_queue_item_info_set(dev, queue_id, &item_info);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+			DEV_ID(dev), rc, "dpp_dtb_queue_item_info_set", p_mutex);
+
+	rc = zxic_comm_mutex_unlock(p_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 打印队列中指定元素的dump地址、ACK及下表中前768bit的数据
+ * @param   dev_id       芯片的id号
+ * @param   queue_id     队列号，范围0-127
+ * @param   element_id   元素号，范围0-31
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2022/08/30
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_dump_table_element_info_prt(DPP_DEV_T *dev,
+												ZXIC_UINT32 queue_id,
+												ZXIC_UINT32 element_id)
+{
+	ZXIC_UINT32 rc = 0;
+
+	ZXIC_UINT32 element_start_addr_h = 0;
+	ZXIC_UINT32 element_start_addr_l = 0;
+	ZXIC_UINT32 element_dump_addr_h = 0;
+	ZXIC_UINT32 element_dump_addr_l = 0;
+	ZXIC_UINT32 element_table_info_addr_h = 0;
+	ZXIC_UINT32 element_table_info_addr_l = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0,
+										DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), element_id, 0,
+										DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+
+	rc = dpp_dtb_dump_table_elemet_addr_get(
+			dev, queue_id, element_id, &element_start_addr_h,
+			&element_start_addr_l, &element_dump_addr_h, &element_dump_addr_l,
+			&element_table_info_addr_h, &element_table_info_addr_l);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_dtb_dump_table_elemet_addr_get");
+
+	ZXIC_COMM_DBGCNT32_PRINT("slot_id", DEV_PCIE_SLOT(dev));
+	ZXIC_COMM_DBGCNT32_PRINT("queue_id", queue_id);
+	ZXIC_COMM_DBGCNT32_PRINT("element_id", element_id);
+	ZXIC_COMM_DBGCNT32_PRINT("element_start_addr_h", element_start_addr_h);
+	ZXIC_COMM_DBGCNT32_PRINT("element_start_addr_l", element_start_addr_l);
+	ZXIC_COMM_DBGCNT32_PRINT("element_dump_addr_h", element_dump_addr_h);
+	ZXIC_COMM_DBGCNT32_PRINT("element_dump_addr_l", element_dump_addr_l);
+	ZXIC_COMM_DBGCNT32_PRINT("element_table_info_addr_h",
+							 element_table_info_addr_h);
+	ZXIC_COMM_DBGCNT32_PRINT("element_table_info_addr_l",
+							 element_table_info_addr_l);
+
+	/*打印element ack*/
+	rc = dpp_dtb_item_ack_prt(dev, queue_id, DPP_DTB_DIR_UP_TYPE, element_id);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_item_ack_prt");
+
+	rc = dpp_dtb_item_buff_prt(dev, queue_id, DPP_DTB_DIR_UP_TYPE, element_id,
+							   32);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_item_buff_prt");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 一个元素dump成功状态检查
+ * @param   dev_id               设备号，支持多芯片
+ * @param   queue_id             队列号，范围0-31
+ * @param   element_id           条目编号
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_up_success_status_check(DPP_DEV_T *dev,
+												ZXIC_UINT32 queue_id,
+												ZXIC_UINT32 element_id)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 rd_cnt = 0;
+	ZXIC_UINT32 ack_value = 0;
+	ZXIC_UINT32 success_flag = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), element_id, 0,
+							  DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+
+	if (DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev))) {
+		return rc;
+	}
+
+	if (dpp_dtb_soft_perf_test_get() || dpp_dtb_hardware_perf_test_get()) {
+		return rc;
+	}
+
+	while (!success_flag) {
+		rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_UP_TYPE, element_id,
+								 0, &ack_value);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd");
+
+		if ((((ack_value >> 8) & 0xffffff) == DPP_DTB_TAB_UP_ACK_VLD_MASK) &&
+			((ack_value & 0xff) == DPP_DTB_TAB_ACK_SUCCESS_MASK)) {
+			success_flag = 1;
+			break;
+		}
+
+		if (rd_cnt > dpp_dtb_dump_table_overtime_get()) {
+			ZXIC_COMM_TRACE_ERROR(
+					"Error!!! dpp dtb dump slot [%d] vport [0x%x] queue [%d] item [%d] ack success is overtime!\n",
+					DEV_PCIE_SLOT(dev), DEV_PCIE_VPORT(dev), queue_id,
+					element_id);
+
+			rc = dpp_dtb_dump_table_element_info_prt(dev, queue_id, element_id);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+								   "dpp_dtb_dump_table_element_info_prt");
+
+			rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE,
+									 element_id, 0,
+									 DPP_DTB_TAB_ACK_UNUSED_MASK);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
+
+			return DPP_ERR;
+		}
+
+		rd_cnt++;
+		zxic_comm_delay(5);
+	}
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取dump数据
+ * @param   dev_id               设备号，支持多芯片
+ * @param   queue_id             队列号，范围0-31
+ * @param   item_index           数据对应的的条目编号
+ * @param   data_len             数据长度，单位32bit;
+ * @param   p_data               dump数据
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_tab_up_data_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									ZXIC_UINT32 item_index,
+									ZXIC_UINT32 data_len, ZXIC_UINT32 *p_data)
+{
+	ZXIC_UINT32 rc = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), item_index, 0,
+							  DPP_DTB_QUEUE_ITEM_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+
+	if (DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+									queue_id) == 0) {
+		ZXIC_COMM_TRACE_ERROR("dtb slot %d queue %d is not init.\n",
+							  DEV_PCIE_SLOT(dev), queue_id);
+		return DPP_RC_DTB_QUEUE_IS_NOT_INIT;
+	}
+
+	if (dpp_dtb_hardware_perf_test_get()) {
+		return rc;
+	}
+
+	rc = dpp_dtb_item_buff_rd(dev, queue_id, DPP_DTB_DIR_UP_TYPE, item_index, 0,
+							  data_len, p_data);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_buff_rd");
+
+	if (dpp_dtb_debug_fun_get()) {
+		return DPP_OK;
+	}
+
+	rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, item_index, 0,
+							 DPP_DTB_TAB_ACK_UNUSED_MASK);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
+
+	return DPP_OK;
+}
+
+#endif
+/***********************************************************/
+/** dtb队列down初始化
+ * @param   dev_id           设备号，支持多芯片
+ * @param   queue_id         队列号
+ * @param   p_queue_cfg      队列配置参数，具体见DPP_DTB_QUEUE_CFG_T结构体类型
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_down_init(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									DPP_DTB_QUEUE_CFG_T *p_queue_cfg)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 ack_vale = 0;
+	ZXIC_UINT32 tab_down_item_size = 0;
+	DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_queue_cfg);
+
+	p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev));
+	if (p_dtb_mgr == ZXIC_NULL) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev),
+				"slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n",
+				DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST);
+		return DPP_RC_DTB_MGR_NOT_EXIST;
+	}
+
+	/*
+     * 流程：
+     * 1.寻找空闲队列；
+     * 2.若找到：
+     *      1）配置硬件信息；
+     *      2）配置软件缓存信息；
+     *      3）初始化条目ack缓存信息,空闲约定:up-0x000000XX,down-0x000000XX；
+     *                            忙约定:up-0x111111XX,down-0x111111XX;
+     *                            完成约定:up-0x555555XX,down-0x5a5a5aXX;
+     * 3.若未找到：返回错误信息；
+     */
+
+	p_dtb_mgr->queue_info[queue_id].init_flag = 1;
+	p_dtb_mgr->queue_info[queue_id].slot_id = DEV_PCIE_SLOT(dev);
+	p_dtb_mgr->queue_info[queue_id].vport = DEV_PCIE_VPORT(dev);
+
+	tab_down_item_size = (p_queue_cfg->down_item_size == 0) ?
+								   DPP_DTB_ITEM_SIZE :
+								   p_queue_cfg->down_item_size;
+
+	p_dtb_mgr->queue_info[queue_id].tab_down.item_size = tab_down_item_size;
+	p_dtb_mgr->queue_info[queue_id].tab_down.start_phy_addr =
+			p_queue_cfg->down_start_phy_addr;
+	p_dtb_mgr->queue_info[queue_id].tab_down.start_vir_addr =
+			p_queue_cfg->down_start_vir_addr;
+	p_dtb_mgr->queue_info[queue_id].tab_down.wr_index = 0;
+	p_dtb_mgr->queue_info[queue_id].tab_down.rd_index = 0;
+
+	for (i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++) {
+		rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, i, 0,
+								 DPP_DTB_TAB_ACK_CHECK_VALUE);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
+	}
+
+	for (i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++) {
+		rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_DOWN_TYPE, i, 0,
+								 &ack_vale);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd");
+		if (ack_vale != DPP_DTB_TAB_ACK_CHECK_VALUE) {
+			ZXIC_COMM_PRINT(
+					"dtb slot [%d] queue [%d] down init faild, mem err!!!\n",
+					DEV_PCIE_SLOT(dev), queue_id);
+			return DPP_RC_DTB_MEMORY_ALLOC_ERR;
+		}
+	}
+
+	ZXIC_COMM_PRINT("dtb slot [%d] queue [%d] down init success!!!\n",
+					DEV_PCIE_SLOT(dev), queue_id);
+
+	ZXIC_COMM_MEMSET((ZXIC_UINT8 *)(p_queue_cfg->down_start_vir_addr), 0,
+					 tab_down_item_size * DPP_DTB_QUEUE_ITEM_NUM_MAX);
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** dtb队列dump初始化
+ * @param   dev_id           设备号，支持多芯片
+ * @param   queue_id         队列号
+ * @param   p_queue_cfg      队列配置参数，具体见DPP_DTB_QUEUE_CFG_T结构体类型
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_dump_init(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									DPP_DTB_QUEUE_CFG_T *p_queue_cfg)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 ack_vale = 0;
+	ZXIC_UINT32 tab_up_item_size = 0;
+	DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL;
+	ZXIC_UINT32 slot_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_queue_cfg);
+
+	slot_id = (ZXIC_UINT32)DEV_PCIE_SLOT(dev);
+	ZXIC_COMM_CHECK_INDEX(slot_id, 0, DPP_DEV_SLOT_MAX - 1);
+
+	p_dtb_mgr = dpp_dtb_mgr_get(slot_id, DEV_ID(dev));
+	if (p_dtb_mgr == ZXIC_NULL) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev),
+				"slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n",
+				DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST);
+		return DPP_RC_DTB_MGR_NOT_EXIST;
+	}
+
+	/*
+     * 流程：
+     * 1.寻找空闲队列；
+     * 2.若找到：
+     *      1）配置硬件信息；
+     *      2）配置软件缓存信息；
+     *      3）初始化条目ack缓存信息,空闲约定:up-0x000000XX,down-0x000000XX；
+     *                            忙约定:up-0x111111XX,down-0x111111XX;
+     *                            完成约定:up-0x555555XX,down-0x5a5a5aXX;
+     * 3.若未找到：返回错误信息；
+     */
+
+	p_dtb_mgr->queue_info[queue_id].init_flag = 1;
+	p_dtb_mgr->queue_info[queue_id].slot_id = DEV_PCIE_SLOT(dev);
+	p_dtb_mgr->queue_info[queue_id].vport = DEV_PCIE_VPORT(dev);
+
+	tab_up_item_size = (p_queue_cfg->up_item_size == 0) ?
+								 DPP_DTB_ITEM_SIZE :
+								 p_queue_cfg->up_item_size;
+
+	p_dtb_mgr->queue_info[queue_id].tab_up.item_size = tab_up_item_size;
+	p_dtb_mgr->queue_info[queue_id].tab_up.start_phy_addr =
+			p_queue_cfg->up_start_phy_addr;
+	p_dtb_mgr->queue_info[queue_id].tab_up.start_vir_addr =
+			p_queue_cfg->up_start_vir_addr;
+	p_dtb_mgr->queue_info[queue_id].tab_up.wr_index = 0;
+	p_dtb_mgr->queue_info[queue_id].tab_up.rd_index = 0;
+
+	for (i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++) {
+		rc = dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, i, 0,
+								 DPP_DTB_TAB_ACK_CHECK_VALUE);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_wr");
+	}
+
+	for (i = 0; i < DPP_DTB_QUEUE_ITEM_NUM_MAX; i++) {
+		rc = dpp_dtb_item_ack_rd(dev, queue_id, DPP_DTB_DIR_UP_TYPE, i, 0,
+								 &ack_vale);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_item_ack_rd");
+		if (ack_vale != DPP_DTB_TAB_ACK_CHECK_VALUE) {
+			ZXIC_COMM_PRINT("dtb slot [%d] queue [%d] init faild, mem err!!!\n",
+							DEV_PCIE_SLOT(dev), queue_id);
+			return DPP_RC_DTB_MEMORY_ALLOC_ERR;
+		}
+	}
+
+	ZXIC_COMM_PRINT("dtb slot [%d] queue [%d] up init success!!!\n",
+					DEV_PCIE_SLOT(dev), queue_id);
+
+	ZXIC_COMM_MEMSET((ZXIC_UINT8 *)(p_queue_cfg->up_start_vir_addr), 0,
+					 tab_up_item_size * DPP_DTB_QUEUE_ITEM_NUM_MAX);
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** dtb队列down 空间地址配置
+ * @param   channelId    dtb通道号
+ * @param   phyAddr      down物理地址
+ * @param   virAddr      down虚拟地址
+ * @param   size         空间大小 0:使用系统默认值16K+16
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_down_channel_addr_set(DPP_DEV_T *dev, ZXIC_UINT32 channelId,
+										  ZXIC_UINT64 phyAddr,
+										  ZXIC_UINT64 virAddr, ZXIC_UINT32 size)
+{
+	ZXIC_UINT32 rc = 0;
+
+	DPP_DTB_QUEUE_CFG_T down_queue_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+
+	down_queue_cfg.down_start_phy_addr = phyAddr;
+	down_queue_cfg.down_start_vir_addr = virAddr;
+	down_queue_cfg.down_item_size = size;
+
+	rc = dpp_dtb_queue_down_init(dev, channelId, &down_queue_cfg);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_down_init");
+
+	return rc;
+}
+
+/***********************************************************/
+/** dtb队列dump 空间地址配置
+ * @param   channelId    dtb通道号
+ * @param   phyAddr      dump物理地址
+ * @param   virAddr      dump虚拟地址
+ * @param   size         空间大小
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_dump_channel_addr_set(DPP_DEV_T *dev, ZXIC_UINT32 channelId,
+										  ZXIC_UINT64 phyAddr,
+										  ZXIC_UINT64 virAddr, ZXIC_UINT32 size)
+{
+	ZXIC_UINT32 rc = 0;
+
+	DPP_DTB_QUEUE_CFG_T dump_queue_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+
+	dump_queue_cfg.up_start_phy_addr = phyAddr;
+	dump_queue_cfg.up_start_vir_addr = virAddr;
+	dump_queue_cfg.up_item_size = size;
+
+	rc = dpp_dtb_queue_dump_init(dev, channelId, &dump_queue_cfg);
+
+	return rc;
+}
+
+/***********************************************************/
+/** 释放队列资源
+ * @param   dev_id           设备号，支持多芯片
+ * @param   queue_id         分配到的队列号;
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2021/02/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_id_free(DPP_DEV_T *dev, ZXIC_UINT32 queue_id)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 item_num = 0;
+	DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+
+	p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev));
+	if (p_dtb_mgr == ZXIC_NULL) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev),
+				"slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n",
+				DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST);
+		return DPP_RC_DTB_MGR_NOT_EXIST;
+	}
+
+	rc = dpp_dtb_queue_unused_item_num_get(dev, queue_id, &item_num);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+						   "dpp_dtb_queue_unused_item_num_get");
+
+	if (item_num != DPP_DTB_QUEUE_ITEM_NUM_MAX) {
+		return DPP_RC_DTB_QUEUE_IS_WORKING;
+	}
+
+	p_dtb_mgr->queue_info[queue_id].init_flag = 0;
+
+	ZXIC_COMM_MEMSET(&(p_dtb_mgr->queue_info[queue_id].tab_up), 0,
+					 sizeof(DPP_DTB_TAB_UP_INFO_T));
+	ZXIC_COMM_MEMSET(&(p_dtb_mgr->queue_info[queue_id].tab_down), 0,
+					 sizeof(DPP_DTB_TAB_DOWN_INFO_T));
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** dtb初始化
+ * @param   dev_id       设备号，支持多芯片
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2022/08/30
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_init(DPP_DEV_T *dev)
+{
+	ZXIC_UINT32 rc = 0;
+	DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev));
+	if (p_dtb_mgr == ZXIC_NULL) {
+		rc = dpp_dtb_mgr_create(DEV_PCIE_SLOT(dev), DEV_ID(dev));
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_mgr_create");
+
+		p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev));
+		if (p_dtb_mgr == ZXIC_NULL) {
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					DEV_ID(dev),
+					"slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n",
+					DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST);
+			return DPP_RC_DTB_MGR_NOT_EXIST;
+		}
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 根据vport查找相应的队列号
+ * @param   dev_id       设备号，支持多芯片
+ * @param   vport        vport信息
+ * @param   p_queue_arr 找到到队列数组
+ * @param   p_num          找到的队列个数
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/09/13
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_id_search_by_vport(DPP_DEV_T *dev,
+											 ZXIC_UINT32 *p_queue_arr,
+											 ZXIC_UINT32 *p_num)
+{
+	ZXIC_UINT32 queue_id = 0;
+	ZXIC_UINT32 count = 0;
+
+	DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL;
+
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_queue_arr);
+
+	p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev));
+	if (p_dtb_mgr == ZXIC_NULL) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev),
+				"slot %d ErrorCode[0x%x]: DTB Manager is not exist!!!\n",
+				DEV_PCIE_SLOT(dev), DPP_RC_DTB_MGR_NOT_EXIST);
+		return DPP_RC_DTB_MGR_NOT_EXIST;
+	}
+
+	for (queue_id = 0; queue_id < DPP_DTB_QUEUE_NUM_MAX; queue_id++) {
+		if (DPP_DTB_QUEUE_INIT_FLAG_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+										queue_id) != 0) {
+			if (DEV_PCIE_VPORT(dev) ==
+				DPP_DTB_QUEUE_VPORT_GET(DEV_PCIE_SLOT(dev), DEV_ID(dev),
+										queue_id)) {
+				p_queue_arr[count] = queue_id;
+				count++;
+			}
+		}
+	}
+
+	if (count == 0) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev),
+				"slot %d ErrorCode[0x%x]: vport 0x%04x no queue not found!!!\n",
+				DEV_PCIE_SLOT(dev), DPP_RC_DTB_QUEUE_NOT_ALLOC,
+				DEV_PCIE_VPORT(dev));
+		return DPP_RC_DTB_QUEUE_NOT_ALLOC;
+	}
+
+	*p_num = count;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 根据vport查找相应的队列号
+ * @param   dev_id       设备号，支持多芯片
+ * @param   vport        vport信息
+ * @param   p_queue_arr 找到到队列数组
+ * @param   p_num          找到的队列个数
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/09/13
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_id_get(ZXIC_UINT32 dev_id, DPP_PF_INFO_T *pf_info,
+								 ZXIC_UINT32 *queue)
+{
+	DPP_DEV_T dev = { 0 };
+
+	ZXIC_UINT32 num = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	ZXIC_UINT32 queue_arr[DPP_DTB_QUEUE_NUM_MAX] = { 0 };
+
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(pf_info);
+
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+
+	rc = dpp_dtb_queue_id_search_by_vport(&dev, queue_arr, &num);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_id_search_by_vport");
+
+	*queue = queue_arr[0];
+
+	return DPP_OK;
+}
+
+#endif
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/dpp_dtb_cfg.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/dpp_dtb_cfg.c
old mode 100755
new mode 100644
index f49b81c276df65774308c33ff6e04a0deafa7c9e..daa2c5d6df20b5bb480b4c9f5bab751c35f35957
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/dpp_dtb_cfg.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/dma/dpp_dtb_cfg.c
@@ -1,1079 +1,379 @@
-/**************************************************************
-* 版权所有(C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_dtb_cfg.c
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : zab
-* 完成日期 : 2022/08/23
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-
-#include "zxic_common.h"
-#include "dpp_type_api.h"
-#include "dpp_cfg_reg.h"
-#include "dpp_dev.h"
-#include "dpp_dtb.h"
-#include "dpp_reg.h"
-#include "dpp_reg_info.h"
-#include "dpp_dtb_cfg.h"
-#include "dpp_dtb4k_reg.h"
-#include "dpp_dtb_reg.h"
-
-#define DTB_DEBUG_VALUE (0x5A)
-
-#if ZXIC_REAL("DTB_CFG")
-/***********************************************************/
-/** DTB队列元素信息配置
-* @param   dev_id           芯片id
-* @param   queue_id         队列ID，范围0-127
-* @param   p_item_info      队列元素配置信息
-*
-* @return
-* @remark  无
-* @see
-* @author  zab      @date  2018/08/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_item_info_set(DPP_DEV_T *dev, 
-                        ZXIC_UINT32 queue_id,
-                        DPP_DTB_QUEUE_ITEM_INFO_T *p_item_info)
-{
-    ZXIC_UINT32 rc = 0;
-    DPP_DTB4K_DTB_ENQ_CFG_QUEUE_DTB_LEN_0_127_T dtb_len = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_item_info);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_item_info->cmd_vld, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_item_info->cmd_type, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_item_info->int_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_item_info->data_len, DPP_DTB_LEN_MIN, DPP_DTB_DOWN_LEN);
-
-    rc = dpp_reg_write(dev, DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_H_0_127r, 0, queue_id, &(p_item_info->data_hddr));
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-    
-    rc = dpp_reg_write(dev, DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_L_0_127r, 0, queue_id, &(p_item_info->data_laddr));
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    dtb_len.cfg_dtb_cmd_type = p_item_info->cmd_type;
-    dtb_len.cfg_dtb_cmd_int_en = p_item_info->int_en;
-    dtb_len.cfg_queue_dtb_len = p_item_info->data_len;
-
-    rc = dpp_reg_write(dev, DTB4K_DTB_ENQ_CFG_QUEUE_DTB_LEN_0_127r, 0, queue_id, &dtb_len);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取DTB队列中剩余未使用的条目数量
-* @param   dev_id               芯片id
-* @param   queue_id             队列ID，范围0-127
-* @param   p_item_num           剩余未使用条目数量
-*
-* @return
-* @remark  无
-* @see
-* @author  zab      @date  2018/08/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_unused_item_num_get(DPP_DEV_T *dev,
-                        ZXIC_UINT32 queue_id,
-                        ZXIC_UINT32 *p_item_num)
-{
-    ZXIC_UINT32 rc = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_item_num);
-
-    if(DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev)))
-    {
-        *p_item_num = 32;
-        return DPP_OK;
-    }
-    
-    rc = dpp_reg_read(dev, DTB4K_DTB_ENQ_INFO_QUEUE_BUF_SPACE_LEFT_0_127r, 0, queue_id, p_item_num);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    
-    return DPP_OK;        
-}
-
-/***********************************************************/
-/** 配置队列VM相关信息
-* @param   dev_id               芯片id
-* @param   queue_id             队列ID，范围0-127
-* @param   p_vm_info            VM配置信息
-*
-* @return
-* @remark  无
-* @see
-* @author  zab      @date  2018/08/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_vm_info_set(DPP_DEV_T *dev,
-                        ZXIC_UINT32 queue_id,
-                        DPP_DTB_QUEUE_VM_INFO_T *p_vm_info)
-{
-    ZXIC_UINT32 rc = 0;
-    DPP_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T vm_info = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_vm_info);
-
-    vm_info.dbi_en = p_vm_info->dbi_en;
-    vm_info.queue_en = p_vm_info->queue_en;
-    vm_info.cfg_epid = p_vm_info->epid;
-    vm_info.cfg_vector = p_vm_info->vector;
-    vm_info.cfg_vfunc_num = p_vm_info->vfunc_num;
-    vm_info.cfg_func_num = p_vm_info->func_num;
-    vm_info.cfg_vfunc_active = p_vm_info->vfunc_active;
-    
-    rc = dpp_reg_write(dev, DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127r, 0, queue_id, &vm_info);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-    
-    return DPP_OK;        
-}
-
-/***********************************************************/
-/** 获取队列VM配置信息
-* @param   dev_id               оƬid
-* @param   queue_id             队列ID，范围0-127
-* @param   p_vm_info            VM配置信息
-*
-* @return
-* @remark  无
-* @see
-* @author  zab      @date  2018/08/23
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_vm_info_get(DPP_DEV_T *dev,
-                        ZXIC_UINT32 queue_id,
-                        DPP_DTB_QUEUE_VM_INFO_T *p_vm_info)
-{
-    ZXIC_UINT32 rc = 0;
-    DPP_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T vm_info = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_vm_info);
-
-    rc = dpp_reg_read(dev, DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127r, 0, queue_id, &vm_info);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    p_vm_info->dbi_en = vm_info.dbi_en;
-    p_vm_info->queue_en = vm_info.queue_en;
-    p_vm_info->epid = vm_info.cfg_epid;
-    p_vm_info->vector = vm_info.cfg_vector;
-    p_vm_info->vfunc_num = vm_info.cfg_vfunc_num;
-    p_vm_info->func_num = vm_info.cfg_func_num;
-    p_vm_info->vfunc_active = vm_info.cfg_vfunc_active;
-    
-    return DPP_OK;        
-}
-
-/***********************************************************/
-/** 配置队列使能
-* @param   dev_id               芯片id
-* @param   queue_id             队列ID，范围0-127
-* @param   enable               1:队列使能,0:队列去使能
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/09/27
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_enable_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 queue_id,
-                                     ZXIC_UINT32 enable)
-{
-    ZXIC_UINT32 rc = DPP_OK;
-    DPP_DTB_QUEUE_VM_INFO_T vm_info = {0};
-
-    rc = dpp_dtb_queue_vm_info_get(dev, queue_id, &vm_info);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_vm_info_get");
-
-    vm_info.queue_en = enable;
-    rc = dpp_dtb_queue_vm_info_set(dev, queue_id, &vm_info);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_vm_info_set");
-
-    ZXIC_COMM_TRACE_INFO("dtb queue [%d] enable_set [%d] success.\n", queue_id, enable);
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取队列使能状态
-* @param   dev_id               芯片id
-* @param   queue_id             队列ID，范围0-127
-* @param   enable               1:队列使能,0:队列去使能
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/09/27
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_enable_get(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 queue_id,
-                                     ZXIC_UINT32 *enable)
-{
-    ZXIC_UINT32 rc = DPP_OK;
-    DPP_DTB_QUEUE_VM_INFO_T vm_info = {0};
-
-    rc = dpp_dtb_queue_vm_info_get(dev, queue_id, &vm_info);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_vm_info_get");
-
-    *enable = vm_info.queue_en;
-
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_queue_enable_get queue %d enable: %d success.\n", queue_id, *enable);
-
-    return rc;
-}
-
-/***********************************************************/
-/** 配置 dtb 完成中断事件状态
-* @param   dev_id               芯片id
-* @param   queue_id             队列ID，范围0-127
-* @param   state                中断事件状态，1-发生中断，0-无中断发生
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/12
-************************************************************/
-ZXIC_UINT32 dpp_dtb_finish_interrupt_event_state_set(DPP_DEV_T *dev,
-                        ZXIC_UINT32 queue_id,
-                        ZXIC_UINT32 state)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 bit_shift = 0;
-    ZXIC_UINT32 reg_shift = 0;
-    ZXIC_UINT32 rd_value = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), state, 0, 1);
-
-    reg_shift = queue_id / 32;
-    bit_shift = queue_id % 32;
-
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_CFG_FINISH_INT_EVENT0r + reg_shift, 0, 0, &rd_value);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    ZXIC_COMM_UINT32_WRITE_BITS(rd_value, state, bit_shift, 1);
-
-    rc = dpp_reg_write(dev, DTB_DTB_CFG_CFG_FINISH_INT_EVENT0r + reg_shift, 0, 0, &rd_value);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 清除 dtb 完成中断事件状态
-* @param   dev_id               芯片id
-* @param   queue_id             队列ID，范围0-127
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/12
-************************************************************/
-ZXIC_UINT32 dpp_dtb_finish_interrupt_event_state_clr(DPP_DEV_T *dev,
-                                                    ZXIC_UINT32 queue_id)
-{
-    ZXIC_UINT32 rc = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-
-    rc = dpp_dtb_finish_interrupt_event_state_set(dev, queue_id, 1);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_finish_interrupt_event_state_set");
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取DTB debug模式配置
-* @param   dev_id           芯片id
-* @param   p_debug_mode       调试模式 当为0x5a时，dtb的ram均可读写
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_debug_mode_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_debug_mode) 
-{
-    ZXIC_UINT32 rc = 0;
-    DPP_DTB_DTB_CFG_CFG_DTB_DEBUG_MODE_EN_T dtb_debug_mode = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_debug_mode);
-
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_CFG_DTB_DEBUG_MODE_ENr, 0, 0, &dtb_debug_mode);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_debug_mode = dtb_debug_mode.cfg_dtb_debug_mode_en;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 判断dtb是否在debug模式
-* @param   dev_id       芯片的id号  
-*
-* @return  1:DTB为debug模式; 0:非debug模式
-* @remark  无
-* @see     
-* @author  cbb      @date  2023/6/10
-************************************************************/
-ZXIC_UINT32 dpp_dtb_mode_is_debug(DPP_DEV_T *dev) 
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 dtb_mode = 0;  
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    rc = dpp_dtb_debug_mode_get(dev, &dtb_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_debug_mode_get");
-
-    if(DTB_DEBUG_VALUE == dtb_mode)
-    {
-        return 1;
-    }
-
-    return 0;
-}
-
-#if ZXIC_REAL("AXIM_READ_TABLE_DEBUG")
-
-/***********************************************************/
-/** 读取axi 最近一次读表相关信息
-* @param   dev_id           芯片id
-* @param   p_last_rd_table_addr_h      axim最近一次读表高地址
-* @param   p_last_rd_table_addr_l      axim最近一次读表低地址
-* @param   p_last_rd_table_len         axim最近一次读表长度
-* @param   p_last_rd_table_user        axim最近一次读表USER信号
-* @param   p_last_rd_table_onload_cnt  axim最近一次读表在线计数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_last_rd_table_info_get(DPP_DEV_T *dev, 
-                                               ZXIC_UINT32 *p_last_rd_table_addr_h,
-                                               ZXIC_UINT32 *p_last_rd_table_addr_l,
-                                               ZXIC_UINT32 *p_last_rd_table_len,
-                                               ZXIC_UINT32 *p_last_rd_table_user,
-                                               ZXIC_UINT32 *p_last_rd_table_onload_cnt
-                                               ) 
-{
-    ZXIC_UINT32 rc = 0;
-
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_HIGH_T rd_table_addr_high = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_LOW_T  rd_table_addr_low = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_LEN_T       rd_table_len = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T      rd_table_user = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ONLOAD_CNT_T rd_table_onload_cnt = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_table_addr_h);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_table_addr_l);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_table_len);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_table_user);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_table_onload_cnt);
-
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_HIGHr, 0, 0, &rd_table_addr_high);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_LOWr, 0, 0, &rd_table_addr_low);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_LENr, 0, 0, &rd_table_len);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USERr, 0, 0, &rd_table_user);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ONLOAD_CNTr, 0, 0, &rd_table_onload_cnt);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_last_rd_table_addr_h = rd_table_addr_high.info_axi_last_rd_table_addr_high;
-    *p_last_rd_table_addr_l = rd_table_addr_low.info_axi_last_rd_table_addr_low;
-    *p_last_rd_table_len = rd_table_len.info_axi_last_rd_table_len;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T*)p_last_rd_table_user)).info_rd_table_user_en = rd_table_user.info_rd_table_user_en;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T*)p_last_rd_table_user)).info_rd_table_epid = rd_table_user.info_rd_table_epid;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T*)p_last_rd_table_user)).info_rd_table_vfunc_num = rd_table_user.info_rd_table_vfunc_num;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T*)p_last_rd_table_user)).info_rd_table_func_num = rd_table_user.info_rd_table_func_num;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T*)p_last_rd_table_user)).info_rd_table_vfunc_active = rd_table_user.info_rd_table_vfunc_active;
-    *p_last_rd_table_onload_cnt = rd_table_onload_cnt.info_axi_last_rd_table_onload_cnt;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读表通道错误次数统计
-* @param   dev_id           芯片id
-* @param   p_axi_rd_table_resp_err_cnt      读表通道返回错误次数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_rd_table_resp_err_cnt_get(DPP_DEV_T *dev, 
-                                                  ZXIC_UINT32 *p_axi_rd_table_resp_err_cnt
-                                                  ) 
-{
-    ZXIC_UINT32 rc = 0;
-
-    DPP_DTB_DTB_CFG_CNT_AXI_RD_TABLE_RESP_ERR_T rd_table_resp_err_cnt= {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_axi_rd_table_resp_err_cnt);
-
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_CNT_AXI_RD_TABLE_RESP_ERRr, 0, 0, &rd_table_resp_err_cnt);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_axi_rd_table_resp_err_cnt = rd_table_resp_err_cnt.cnt_axi_rd_table_resp_err;
-
-    return DPP_OK;
-}
-#endif
-
-#if ZXIC_REAL("AXIM_READ_PD_DEBUG")
-/***********************************************************/
-/** 读取axi 最近一次读PD相关信息
-* @param   dev_id           芯片id
-* @param   p_last_rd_pd_addr_h      axim最近一次读PD高地址
-* @param   p_last_rd_pd_addr_l      axim最近一次读PD低地址
-* @param   p_last_rd_pd_len         axim最近一次读PD长度
-* @param   p_last_rd_pd_user        axim最近一次读PD USER信号
-* @param   p_last_rd_pd_onload_cnt  axim最近一次读PD在线计数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_last_rd_pd_info_get(DPP_DEV_T *dev, 
-                                            ZXIC_UINT32 *p_last_rd_pd_addr_h,
-                                            ZXIC_UINT32 *p_last_rd_pd_addr_l,
-                                            ZXIC_UINT32 *p_last_rd_pd_len,
-                                            ZXIC_UINT32 *p_last_rd_pd_user,
-                                            ZXIC_UINT32 *p_last_rd_pd_onload_cnt
-                                            ) 
-{
-    ZXIC_UINT32 rc = 0;
-
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_HIGH_T rd_pd_addr_high = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_LOW_T  rd_pd_addr_low = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_LEN_T       rd_pd_len = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T      rd_pd_user = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ONLOAD_CNT_T rd_pd_onload_cnt = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_pd_addr_h);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_pd_addr_l);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_pd_len);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_pd_user);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_rd_pd_onload_cnt);
-
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_HIGHr, 0, 0, &rd_pd_addr_high);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_LOWr, 0, 0, &rd_pd_addr_low);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_LENr, 0, 0, &rd_pd_len);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USERr, 0, 0, &rd_pd_user);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ONLOAD_CNTr, 0, 0, &rd_pd_onload_cnt);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_last_rd_pd_addr_h = rd_pd_addr_high.info_axi_last_rd_pd_addr_high;
-    *p_last_rd_pd_addr_l = rd_pd_addr_low.info_axi_last_rd_pd_addr_low;
-    *p_last_rd_pd_len = rd_pd_len.info_axi_last_rd_pd_len;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T*)p_last_rd_pd_user)).info_rd_pd_user_en = rd_pd_user.info_rd_pd_user_en;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T*)p_last_rd_pd_user)).info_rd_pd_epid = rd_pd_user.info_rd_pd_epid;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T*)p_last_rd_pd_user)).info_rd_pd_vfunc_num = rd_pd_user.info_rd_pd_vfunc_num;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T*)p_last_rd_pd_user)).info_rd_pd_func_num = rd_pd_user.info_rd_pd_func_num;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T*)p_last_rd_pd_user)).info_rd_pd_vfunc_active = rd_pd_user.info_rd_pd_vfunc_active;
-    *p_last_rd_pd_onload_cnt = rd_pd_onload_cnt.info_axi_last_rd_pd_onload_cnt;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读PD通道错误次数统计
-* @param   dev_id           芯片id
-* @param   p_axi_rd_pd_resp_err_cnt      读PD通道返回错误次数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_rd_pd_resp_err_cnt_get(DPP_DEV_T *dev,
-                                               ZXIC_UINT32 *p_axi_rd_pd_resp_err_cnt
-                                                ) 
-{
-    ZXIC_UINT32 rc = 0;
-
-    DPP_DTB_DTB_CFG_CNT_AXI_RD_PD_RESP_ERR_T rd_pd_resp_err_cnt= {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_axi_rd_pd_resp_err_cnt);
-
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_CNT_AXI_RD_PD_RESP_ERRr, 0, 0, &rd_pd_resp_err_cnt);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_axi_rd_pd_resp_err_cnt = rd_pd_resp_err_cnt.cnt_axi_rd_pd_resp_err;
-
-    return DPP_OK;
-}
-
-#endif
-
-#if ZXIC_REAL("AXI_WRITE_CTRL_DEBUG")
-
-/***********************************************************/
-/** 读取axim 最近一次写控制相关信息
-* @param   dev_id           芯片id
-* @param   p_last_wr_ctrl_addr_h      axim最近一次写控制高地址
-* @param   p_last_wr_ctrl_addr_l      axim最近一次写控制低地址
-* @param   p_last_wr_ctrl_len         axim最近一次写控制长度
-* @param   p_last_wr_ctrl_user        axim最近一次写控制 USER信号
-* @param   p_last_wr_ctrl_onload_cnt  axim最近一次写控制在线计数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_last_wr_ctrl_info_get(DPP_DEV_T *dev, 
-                                              ZXIC_UINT32 *p_last_wr_ctrl_addr_h,
-                                              ZXIC_UINT32 *p_last_wr_ctrl_addr_l,
-                                              ZXIC_UINT32 *p_last_wr_ctrl_len,
-                                              ZXIC_UINT32 *p_last_wr_ctrl_user,
-                                              ZXIC_UINT32 *p_last_wr_ctrl_onload_cnt
-                                             ) 
-{
-    ZXIC_UINT32 rc = 0;
-
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_HIGH_T wr_ctrl_addr_high = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_LOW_T  wr_ctrl_addr_low = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_LEN_T       wr_ctrl_len = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T      wr_ctrl_user = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ONLOAD_CNT_T wr_ctrl_onload_cnt = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ctrl_addr_h);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ctrl_addr_l);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ctrl_len);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ctrl_user);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ctrl_onload_cnt);
-
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_HIGHr, 0, 0, &wr_ctrl_addr_high);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_LOWr, 0, 0, &wr_ctrl_addr_low);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_LENr, 0, 0, &wr_ctrl_len);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USERr, 0, 0, &wr_ctrl_user);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ONLOAD_CNTr, 0, 0, &wr_ctrl_onload_cnt);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_last_wr_ctrl_addr_h = wr_ctrl_addr_high.info_axi_last_wr_ctrl_addr_high;
-    *p_last_wr_ctrl_addr_l = wr_ctrl_addr_low.info_axi_last_wr_ctrl_addr_low;
-    *p_last_wr_ctrl_len = wr_ctrl_len.info_axi_last_wr_ctrl_len;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T*)p_last_wr_ctrl_user)).info_wr_ctrl_user_en = wr_ctrl_user.info_wr_ctrl_user_en;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T*)p_last_wr_ctrl_user)).info_wr_ctrl_epid = wr_ctrl_user.info_wr_ctrl_epid;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T*)p_last_wr_ctrl_user)).info_wr_ctrl_vfunc_num = wr_ctrl_user.info_wr_ctrl_vfunc_num;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T*)p_last_wr_ctrl_user)).info_wr_ctrl_func_num = wr_ctrl_user.info_wr_ctrl_func_num;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T*)p_last_wr_ctrl_user)).info_wr_ctrl_vfunc_active = wr_ctrl_user.info_wr_ctrl_vfunc_active;
-    *p_last_wr_ctrl_onload_cnt = wr_ctrl_onload_cnt.info_axi_last_wr_ctrl_onload_cnt;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取写控制通道错误次数统计
-* @param   dev_id           芯片id
-* @param   p_axi_wr_ctrl_resp_err_cnt      写控制通道返回错误次数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_wr_ctrl_resp_err_cnt_get(DPP_DEV_T *dev,
-                                                ZXIC_UINT32 *p_axi_wr_ctrl_resp_err_cnt
-                                                ) 
-{
-    ZXIC_UINT32 rc = 0;
-
-    DPP_DTB_DTB_CFG_CNT_AXI_WR_CTRL_RESP_ERR_T wr_ctrl_resp_err_cnt= {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_axi_wr_ctrl_resp_err_cnt);
-
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_CNT_AXI_WR_CTRL_RESP_ERRr, 0, 0, &wr_ctrl_resp_err_cnt);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_axi_wr_ctrl_resp_err_cnt = wr_ctrl_resp_err_cnt.cnt_axi_wr_ctrl_resp_err;
-
-    return DPP_OK;
-}
-
-#endif
-
-#if ZXIC_REAL("AXI_WRITE_DDR_DEBUG")
-/***********************************************************/
-/** 读取axim 最近一次写DDR相关信息
-* @param   dev_id           芯片id
-* @param   p_last_wr_ddr_addr_h      axim最近一次写控制高地址
-* @param   p_last_wr_ddr_addr_l      axim最近一次写控制低地址
-* @param   p_last_wr_ddr_len         axim最近一次写控制长度
-* @param   p_last_wr_ddr_user        axim最近一次写控制 USER信号
-* @param   p_last_wr_ddr_onload_cnt  axim最近一次写控制在线计数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_last_wr_ddr_info_get(DPP_DEV_T *dev,
-                                            ZXIC_UINT32 *p_last_wr_ddr_addr_h,
-                                            ZXIC_UINT32 *p_last_wr_ddr_addr_l,
-                                            ZXIC_UINT32 *p_last_wr_ddr_len,
-                                            ZXIC_UINT32 *p_last_wr_ddr_user,
-                                            ZXIC_UINT32 *p_last_wr_ddr_onload_cnt
-                                            ) 
-{
-    ZXIC_UINT32 rc = 0;
-
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_HIGH_T wr_ddr_addr_high = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_LOW_T  wr_ddr_addr_low = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_LEN_T       wr_ddr_len = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T      wr_ddr_user = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ONLOAD_CNT_T wr_ddr_onload_cnt = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ddr_addr_h);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ddr_addr_l);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ddr_len);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ddr_user);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_ddr_onload_cnt);
-
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_HIGHr, 0, 0, &wr_ddr_addr_high);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_LOWr, 0, 0, &wr_ddr_addr_low);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_LENr, 0, 0, &wr_ddr_len);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USERr, 0, 0, &wr_ddr_user);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ONLOAD_CNTr, 0, 0, &wr_ddr_onload_cnt);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_last_wr_ddr_addr_h = wr_ddr_addr_high.info_axi_last_wr_ddr_addr_high;
-    *p_last_wr_ddr_addr_l = wr_ddr_addr_low.info_axi_last_wr_ddr_addr_low;
-    *p_last_wr_ddr_len = wr_ddr_len.info_axi_last_wr_ddr_len;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T*)p_last_wr_ddr_user)).info_wr_ddr_user_en = wr_ddr_user.info_wr_ddr_user_en;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T*)p_last_wr_ddr_user)).info_wr_ddr_epid = wr_ddr_user.info_wr_ddr_epid;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T*)p_last_wr_ddr_user)).info_wr_ddr_vfunc_num = wr_ddr_user.info_wr_ddr_vfunc_num;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T*)p_last_wr_ddr_user)).info_wr_ddr_func_num = wr_ddr_user.info_wr_ddr_func_num;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T*)p_last_wr_ddr_user)).info_wr_ddr_vfunc_active = wr_ddr_user.info_wr_ddr_vfunc_active;
-    *p_last_wr_ddr_onload_cnt = wr_ddr_onload_cnt.info_axi_last_wr_ddr_onload_cnt;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取写DDR通道错误次数统计
-* @param   dev_id           芯片id
-* @param   p_axi_wr_ddr_resp_err_cnt      写DDR通道返回错误次数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_wr_ddr_resp_err_cnt_get(DPP_DEV_T *dev,
-                                                ZXIC_UINT32 *p_axi_wr_ddr_resp_err_cnt
-                                                ) 
-{
-    ZXIC_UINT32 rc = 0;
-
-    DPP_DTB_DTB_CFG_CNT_AXI_WR_DDR_RESP_ERR_T wr_ddr_resp_err_cnt= {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_axi_wr_ddr_resp_err_cnt);
-
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_CNT_AXI_WR_DDR_RESP_ERRr, 0, 0, &wr_ddr_resp_err_cnt);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_axi_wr_ddr_resp_err_cnt = wr_ddr_resp_err_cnt.cnt_axi_wr_ddr_resp_err;
-
-    return DPP_OK;
-}
-
-#endif
-
-#if ZXIC_REAL("AXIM_WRITE_FINISH_DEBUG")
-
-/***********************************************************/
-/** 读取axim 最近一次写完成相关信息
-* @param   dev_id           芯片id
-* @param   p_last_wr_fin_addr_h      axim最近一次写控制高地址
-* @param   p_last_wr_fin_addr_l      axim最近一次写控制低地址
-* @param   p_last_wr_fin_len         axim最近一次写控制长度
-* @param   p_last_wr_fin_user        axim最近一次写控制 USER信号
-* @param   p_last_wr_fin_onload_cnt  axim最近一次写控制在线计数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_last_wr_fin_info_get(DPP_DEV_T *dev, 
-                                             ZXIC_UINT32 *p_last_wr_fin_addr_h,
-                                             ZXIC_UINT32 *p_last_wr_fin_addr_l,
-                                             ZXIC_UINT32 *p_last_wr_fin_len,
-                                             ZXIC_UINT32 *p_last_wr_fin_user,
-                                             ZXIC_UINT32 *p_last_wr_fin_onload_cnt
-                                            ) 
-{
-    ZXIC_UINT32 rc = 0;
-
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_HIGH_T wr_fin_addr_high = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_LOW_T  wr_fin_addr_low = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_LEN_T       wr_fin_len = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T      wr_fin_user = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ONLOAD_CNT_T wr_fin_onload_cnt = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_fin_addr_h);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_fin_addr_l);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_fin_len);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_fin_user);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_wr_fin_onload_cnt);
-
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_HIGHr, 0, 0, &wr_fin_addr_high);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_LOWr, 0, 0, &wr_fin_addr_low);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_LENr, 0, 0, &wr_fin_len);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USERr, 0, 0, &wr_fin_user);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ONLOAD_CNTr, 0, 0, &wr_fin_onload_cnt);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_last_wr_fin_addr_h = wr_fin_addr_high.info_axi_last_wr_fin_addr_high;
-    *p_last_wr_fin_addr_l = wr_fin_addr_low.info_axi_last_wr_fin_addr_low;
-    *p_last_wr_fin_len = wr_fin_len.info_axi_last_wr_fin_len;
-
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T*)p_last_wr_fin_user)).info_wr_fin_user_en = wr_fin_user.info_wr_fin_user_en;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T*)p_last_wr_fin_user)).info_wr_fin_epid = wr_fin_user.info_wr_fin_epid;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T*)p_last_wr_fin_user)).info_wr_fin_vfunc_num = wr_fin_user.info_wr_fin_vfunc_num;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T*)p_last_wr_fin_user)).info_wr_fin_func_num = wr_fin_user.info_wr_fin_func_num;
-    (*((DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T*)p_last_wr_fin_user)).info_wr_fin_vfunc_active = wr_fin_user.info_wr_fin_vfunc_active;
-    *p_last_wr_fin_onload_cnt = wr_fin_onload_cnt.info_axi_last_wr_fin_onload_cnt;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取写完成通道错误次数统计
-* @param   dev_id           芯片id
-* @param   p_axi_wr_fin_resp_err_cnt      写完成通道返回错误次数
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_axi_wr_fin_resp_err_cnt_get(DPP_DEV_T *dev,
-                                                ZXIC_UINT32 *p_axi_wr_fin_resp_err_cnt
-                                                ) 
-{
-    ZXIC_UINT32 rc = 0;
-
-    DPP_DTB_DTB_CFG_CNT_AXI_WR_FIN_RESP_ERR_T wr_fin_resp_err_cnt= {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_axi_wr_fin_resp_err_cnt);
-
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_CNT_AXI_WR_FIN_RESP_ERRr, 0, 0, &wr_fin_resp_err_cnt);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_axi_wr_fin_resp_err_cnt = wr_fin_resp_err_cnt.cnt_axi_wr_fin_resp_err;
-
-    return DPP_OK;
-}
-
-#endif
-
-#if ZXIC_REAL("DTB_STATE")
-
-/***********************************************************/
-/** 读取 DTB 各通道状态机
-* @param   dev_id           芯片id
-* @param   p_wr_ctrl_state_info     写控制状态机
-* @param   p_rd_table_state_info    读表状态机
-* @param   p_rd_pd_state_info       读描述符数据状态机
-* @param   p_wr_ddr_state_info      写数据到ddr的状态机
-* @param   p_wr_fin_state_info      写结束标志的状态机
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/11/09
-************************************************************/
-ZXIC_UINT32 dpp_dtb_state_info_get(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 *p_wr_ctrl_state_info,
-                                   ZXIC_UINT32 *p_rd_table_state_info,
-                                   ZXIC_UINT32 *p_rd_pd_state_info,
-                                   ZXIC_UINT32 *p_wr_ddr_state_info,
-                                   ZXIC_UINT32 *p_dump_cmd_state_info
-                                   )
-{
-
-    ZXIC_UINT32 rc = 0;
-
-    DPP_DTB_DTB_CFG_INFO_WR_CTRL_STATE_T   wr_ctrl_state = {0};
-    DPP_DTB_DTB_CFG_INFO_RD_TABLE_STATE_T    rd_table_state = {0};
-    DPP_DTB_DTB_CFG_INFO_RD_PD_STATE_T   rd_pd_state = {0};
-    DPP_DTB_DTB_CFG_INFO_WR_DDR_STATE_T    wr_ddr_state = {0};
-    DPP_DTB_DTB_CFG_INFO_DUMP_CMD_STATE_T    dump_cmd_state = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_wr_ctrl_state_info);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_rd_table_state_info);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_rd_pd_state_info);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_wr_ddr_state_info);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_cmd_state_info);
-
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_WR_CTRL_STATEr, 0, 0, &wr_ctrl_state);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_RD_TABLE_STATEr, 0, 0, &rd_table_state);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_RD_PD_STATEr, 0, 0, &rd_pd_state);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_WR_DDR_STATEr, 0, 0, &wr_ddr_state);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    rc = dpp_reg_read(dev, DTB_DTB_CFG_INFO_DUMP_CMD_STATEr, 0, 0, &dump_cmd_state);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_wr_ctrl_state_info = wr_ctrl_state.info_wr_ctrl_state;
-    *p_rd_table_state_info = rd_table_state.info_rd_table_state;
-    *p_rd_pd_state_info = rd_pd_state.info_rd_pd_state;
-    *p_wr_ddr_state_info = wr_ddr_state.info_wr_ddr_state;
-    *p_dump_cmd_state_info = dump_cmd_state.info_dump_cmd_state;
-
-    return DPP_OK;
-} 
-
-#endif
-
-/***********************************************************/
-/** 各通道错误统计打印
-* @param   dev_id       芯片的id号  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  cbb      @date  2022/11/11
-************************************************************/
-ZXIC_UINT32 diag_dpp_dtb_channels_axi_resp_err_cnt_prt(DPP_DEV_T *dev)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 rd_value = 0;  
-
-    ZXIC_COMM_PRINT("\n --------------- DTB CHANNEL ERR STAT INFO --------------- \n");
-
-    ZXIC_COMM_PRINT("********** dtb down table err cnt **********\n"); 
-
-    rc = dpp_dtb_axi_rd_table_resp_err_cnt_get(dev, &rd_value);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_rd_table_resp_err_cnt_get");
-
-    ZXIC_COMM_DBGCNT32_PRINT("cnt_axi_rd_table_resp_err", rd_value);
-
-    rc = dpp_dtb_axi_wr_ctrl_resp_err_cnt_get(dev, &rd_value);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_wr_ctrl_resp_err_cnt_get");
-
-    ZXIC_COMM_DBGCNT32_PRINT("cnt_axi_wr_ctrl_resp_err", rd_value);
-
-    ZXIC_COMM_PRINT("********** dtb dump table err cnt **********\n"); 
-
-    rc = dpp_dtb_axi_rd_pd_resp_err_cnt_get(dev, &rd_value);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_rd_pd_resp_err_cnt_get");
-
-    ZXIC_COMM_DBGCNT32_PRINT("cnt_axi_rd_pd_resp_err", rd_value);
-
-    rc = dpp_dtb_axi_wr_ddr_resp_err_cnt_get(dev, &rd_value);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_wr_ddr_resp_err_cnt_get");
-
-    ZXIC_COMM_DBGCNT32_PRINT("cnt_axi_wr_ddr_resp_err", rd_value);
-
-    rc = dpp_dtb_axi_wr_fin_resp_err_cnt_get(dev, &rd_value);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_wr_fin_resp_err_cnt_get");
-
-    ZXIC_COMM_DBGCNT32_PRINT("cnt_axi_wr_fin_resp_err", rd_value);
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** AXIM最近一次操作信息记录打印
-* @param   dev_id       芯片的id号  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  cbb      @date  2022/11/11
-************************************************************/
-ZXIC_UINT32 diag_dpp_dtb_axi_last_operate_info_prt(DPP_DEV_T *dev)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 addr_high = 0; 
-    ZXIC_UINT32 addr_low = 0;  
-    ZXIC_UINT32 len = 0; 
-    ZXIC_UINT32 onload_cnt = 0; 
-
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USER_T rd_table_user = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USER_T rd_pd_user = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USER_T wr_ctrl_user = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USER_T wr_ddr_user = {0};
-    DPP_DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USER_T wr_fin_user = {0};
-    ZXIC_COMM_PRINT("\n------------------ DTB DOWN TABLE LAST INFO ------------------\n"); 
-    rc = dpp_dtb_axi_last_rd_table_info_get( dev, &addr_high, &addr_low, &len, (ZXIC_UINT32 *)&rd_table_user, &onload_cnt);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_last_rd_table_info_get");
-    ZXIC_COMM_PRINT("**********axim last read table info***********\n"); 
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_addr_high", addr_high);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_addr_low", addr_low);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_len", len);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_user_en", rd_table_user.info_rd_table_user_en);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_epid", rd_table_user.info_rd_table_epid);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_vfunc_num", rd_table_user.info_rd_table_vfunc_num);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_func_num", rd_table_user.info_rd_table_func_num);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_vfunc_active", rd_table_user.info_rd_table_vfunc_active);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_table_onload_cnt", onload_cnt);
-
-    rc = dpp_dtb_axi_last_wr_ctrl_info_get( dev, &addr_high, &addr_low, &len, (ZXIC_UINT32 *)&wr_ctrl_user, &onload_cnt);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_last_wr_ctrl_info_get");
-    ZXIC_COMM_PRINT("**********axim last write ctrl info***********\n"); 
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_addr_high", addr_high);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_addr_low", addr_low);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_len", len);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_user_en", wr_ctrl_user.info_wr_ctrl_user_en);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_epid", wr_ctrl_user.info_wr_ctrl_epid);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_vfunc_num", wr_ctrl_user.info_wr_ctrl_vfunc_num);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_func_num", wr_ctrl_user.info_wr_ctrl_func_num);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_vfunc_active", wr_ctrl_user.info_wr_ctrl_vfunc_active);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ctrl_onload_cnt", onload_cnt);
-
-    ZXIC_COMM_PRINT("\n------------------ DTB DUMP TABLE LAST INFO ------------------\n"); 
-    rc = dpp_dtb_axi_last_rd_pd_info_get( dev, &addr_high, &addr_low, &len, (ZXIC_UINT32*)&rd_pd_user, &onload_cnt);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_last_rd_pd_info_get");
-    ZXIC_COMM_PRINT("**********axim last read pd info***********\n"); 
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_addr_high", addr_high);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_addr_low", addr_low);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_len", len);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_user_en", rd_pd_user.info_rd_pd_user_en);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_epid", rd_pd_user.info_rd_pd_epid);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_vfunc_num", rd_pd_user.info_rd_pd_vfunc_num);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_func_num", rd_pd_user.info_rd_pd_func_num);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_vfunc_active", rd_pd_user.info_rd_pd_vfunc_active);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_rd_pd_onload_cnt", onload_cnt);
-
-    rc = dpp_dtb_axi_last_wr_ddr_info_get( dev, &addr_high, &addr_low, &len, (ZXIC_UINT32 *)&wr_ddr_user, &onload_cnt);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_last_wr_ddr_info_get");
-    ZXIC_COMM_PRINT("**********axim last write ddr info***********\n"); 
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_addr_high", addr_high);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_addr_low", addr_low);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_len", len);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_user_en", wr_ddr_user.info_wr_ddr_user_en);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_epid", wr_ddr_user.info_wr_ddr_epid);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_vfunc_num", wr_ddr_user.info_wr_ddr_vfunc_num);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_func_num", wr_ddr_user.info_wr_ddr_func_num);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_vfunc_active", wr_ddr_user.info_wr_ddr_vfunc_active);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_ddr_onload_cnt", onload_cnt);
-
-    rc = dpp_dtb_axi_last_wr_fin_info_get( dev, &addr_high, &addr_low, &len, (ZXIC_UINT32 *)&wr_fin_user, &onload_cnt);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_axi_wr_fin_resp_err_cnt_get");
-    ZXIC_COMM_PRINT("**********axim last write final info***********\n"); 
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_addr_high", addr_high);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_addr_low", addr_low);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_len", len);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_user_en", wr_fin_user.info_wr_fin_user_en);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_epid", wr_fin_user.info_wr_fin_epid);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_vfunc_num", wr_fin_user.info_wr_fin_vfunc_num);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_func_num", wr_fin_user.info_wr_fin_func_num);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_vfunc_active", wr_fin_user.info_wr_fin_vfunc_active);
-    ZXIC_COMM_DBGCNT32_PRINT("info_axi_last_wr_fin_onload_cnt", onload_cnt);
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** DTB 各通道状态机信息获取
-* @param   dev_id       芯片的id号  
-*
-* @return  
-* @remark  无
-* @see     
-* @author  cbb      @date  2022/11/11
-************************************************************/
-ZXIC_UINT32 diag_dpp_dtb_channels_state_info_prt(DPP_DEV_T *dev)
-{
-    ZXIC_UINT32 rc = 0;
-
-    ZXIC_UINT32 wr_ctrl_state = 0; 
-    ZXIC_UINT32 rd_table_state = 0; 
-    ZXIC_UINT32 rd_pd_state = 0; 
-    ZXIC_UINT32 wr_ddr_state = 0; 
-    ZXIC_UINT32 dump_cmd_state = 0; 
-
-    rc = dpp_dtb_state_info_get(dev,
-                               &wr_ctrl_state,
-                               &rd_table_state,
-                               &rd_pd_state,
-                               &wr_ddr_state,
-                               &dump_cmd_state);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_stat_info_get");
-
-    ZXIC_COMM_PRINT("\n-------------- DTB CHANNEL STATE INFO  ----------------- \n");
-    ZXIC_COMM_PRINT("----- REG ------------------- CURRENT  ------- CORRECT ----- \n");
-    ZXIC_COMM_PRINT("info_wr_ctrl_state           0x%08x       0x00000005 \n", wr_ctrl_state);
-    ZXIC_COMM_PRINT("info_rd_table_state          0x%08x       0x00080004 \n", rd_table_state);
-    ZXIC_COMM_PRINT("info_rd_pd_state             0x%08x       0x00020020 \n", rd_pd_state);
-    ZXIC_COMM_PRINT("info_wr_ddr_state            0x%08x       0x00000001 \n", wr_ddr_state);
-    ZXIC_COMM_PRINT("info_dump_cmd_state          0x%08x       0x0000002a \n", dump_cmd_state);
-
-    return DPP_OK;
-}
-
-#endif
+/**************************************************************
+* 版权所有(C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_dtb_cfg.c
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : zab
+* 完成日期 : 2022/08/23
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#include "zxic_common.h"
+#include "dpp_type_api.h"
+#include "dpp_cfg_reg.h"
+#include "dpp_dev.h"
+#include "dpp_dtb.h"
+#include "dpp_reg.h"
+#include "dpp_reg_info.h"
+#include "dpp_dtb_cfg.h"
+#include "dpp_dtb4k_reg.h"
+#include "dpp_dtb_reg.h"
+
+#define DTB_DEBUG_VALUE (0x5A)
+
+#if ZXIC_REAL("DTB_CFG")
+/***********************************************************/
+/** DTB队列元素信息配置
+ * @param   dev_id           芯片id
+ * @param   queue_id         队列ID，范围0-127
+ * @param   p_item_info      队列元素配置信息
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2018/08/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_item_info_set(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+										DPP_DTB_QUEUE_ITEM_INFO_T *p_item_info)
+{
+	ZXIC_UINT32 rc = 0;
+	DPP_DTB4K_DTB_ENQ_CFG_QUEUE_DTB_LEN_0_127_T dtb_len = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_item_info);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_item_info->cmd_vld, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_item_info->cmd_type, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_item_info->int_en, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_item_info->data_len,
+							  DPP_DTB_LEN_MIN, DPP_DTB_DOWN_LEN);
+
+	rc = dpp_reg_write(dev, DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_H_0_127r, 0,
+					   queue_id, &(p_item_info->data_hddr));
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	rc = dpp_reg_write(dev, DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_L_0_127r, 0,
+					   queue_id, &(p_item_info->data_laddr));
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	dtb_len.cfg_dtb_cmd_type = p_item_info->cmd_type;
+	dtb_len.cfg_dtb_cmd_int_en = p_item_info->int_en;
+	dtb_len.cfg_queue_dtb_len = p_item_info->data_len;
+
+	rc = dpp_reg_write(dev, DTB4K_DTB_ENQ_CFG_QUEUE_DTB_LEN_0_127r, 0, queue_id,
+					   &dtb_len);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取DTB队列中剩余未使用的条目数量
+ * @param   dev_id               芯片id
+ * @param   queue_id             队列ID，范围0-127
+ * @param   p_item_num           剩余未使用条目数量
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2018/08/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_unused_item_num_get(DPP_DEV_T *dev,
+											  ZXIC_UINT32 queue_id,
+											  ZXIC_UINT32 *p_item_num)
+{
+	ZXIC_UINT32 rc = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_item_num);
+
+	if (DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev))) {
+		*p_item_num = 32;
+		return DPP_OK;
+	}
+
+	rc = dpp_reg_read(dev, DTB4K_DTB_ENQ_INFO_QUEUE_BUF_SPACE_LEFT_0_127r, 0,
+					  queue_id, p_item_num);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置队列VM相关信息
+ * @param   dev_id               芯片id
+ * @param   queue_id             队列ID，范围0-127
+ * @param   p_vm_info            VM配置信息
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2018/08/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_vm_info_set(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									  DPP_DTB_QUEUE_VM_INFO_T *p_vm_info)
+{
+	ZXIC_UINT32 rc = 0;
+	DPP_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T vm_info = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_vm_info);
+
+	vm_info.dbi_en = p_vm_info->dbi_en;
+	vm_info.queue_en = p_vm_info->queue_en;
+	vm_info.cfg_epid = p_vm_info->epid;
+	vm_info.cfg_vector = p_vm_info->vector;
+	vm_info.cfg_vfunc_num = p_vm_info->vfunc_num;
+	vm_info.cfg_func_num = p_vm_info->func_num;
+	vm_info.cfg_vfunc_active = p_vm_info->vfunc_active;
+
+	rc = dpp_reg_write(dev, DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127r, 0,
+					   queue_id, &vm_info);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取队列VM配置信息
+ * @param   dev_id               оƬid
+ * @param   queue_id             队列ID，范围0-127
+ * @param   p_vm_info            VM配置信息
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  zab      @date  2018/08/23
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_vm_info_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									  DPP_DTB_QUEUE_VM_INFO_T *p_vm_info)
+{
+	ZXIC_UINT32 rc = 0;
+	DPP_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T vm_info = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_vm_info);
+
+	rc = dpp_reg_read(dev, DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127r, 0,
+					  queue_id, &vm_info);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	p_vm_info->dbi_en = vm_info.dbi_en;
+	p_vm_info->queue_en = vm_info.queue_en;
+	p_vm_info->epid = vm_info.cfg_epid;
+	p_vm_info->vector = vm_info.cfg_vector;
+	p_vm_info->vfunc_num = vm_info.cfg_vfunc_num;
+	p_vm_info->func_num = vm_info.cfg_func_num;
+	p_vm_info->vfunc_active = vm_info.cfg_vfunc_active;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置队列使能
+ * @param   dev_id               芯片id
+ * @param   queue_id             队列ID，范围0-127
+ * @param   enable               1:队列使能,0:队列去使能
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/09/27
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_enable_set(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									 ZXIC_UINT32 enable)
+{
+	ZXIC_UINT32 rc = DPP_OK;
+	DPP_DTB_QUEUE_VM_INFO_T vm_info = { 0 };
+
+	rc = dpp_dtb_queue_vm_info_get(dev, queue_id, &vm_info);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_vm_info_get");
+
+	vm_info.queue_en = enable;
+	rc = dpp_dtb_queue_vm_info_set(dev, queue_id, &vm_info);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_vm_info_set");
+
+	ZXIC_COMM_TRACE_INFO("dtb queue [%d] enable_set [%d] success.\n", queue_id,
+						 enable);
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取队列使能状态
+ * @param   dev_id               芯片id
+ * @param   queue_id             队列ID，范围0-127
+ * @param   enable               1:队列使能,0:队列去使能
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/09/27
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_enable_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									 ZXIC_UINT32 *enable)
+{
+	ZXIC_UINT32 rc = DPP_OK;
+	DPP_DTB_QUEUE_VM_INFO_T vm_info = { 0 };
+
+	rc = dpp_dtb_queue_vm_info_get(dev, queue_id, &vm_info);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_vm_info_get");
+
+	*enable = vm_info.queue_en;
+
+	ZXIC_COMM_TRACE_INFO(
+			"dpp_dtb_queue_enable_get queue %d enable: %d success.\n", queue_id,
+			*enable);
+
+	return rc;
+}
+
+/***********************************************************/
+/** 配置 dtb 完成中断事件状态
+ * @param   dev_id               芯片id
+ * @param   queue_id             队列ID，范围0-127
+ * @param   state                中断事件状态，1-发生中断，0-无中断发生
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/11/12
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_finish_interrupt_event_state_set(DPP_DEV_T *dev,
+													 ZXIC_UINT32 queue_id,
+													 ZXIC_UINT32 state)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 bit_shift = 0;
+	ZXIC_UINT32 reg_shift = 0;
+	ZXIC_UINT32 rd_value = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0,
+							  DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), state, 0, 1);
+
+	reg_shift = queue_id / 32;
+	bit_shift = queue_id % 32;
+
+	rc = dpp_reg_read(dev, DTB_DTB_CFG_CFG_FINISH_INT_EVENT0r + reg_shift, 0, 0,
+					  &rd_value);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	ZXIC_COMM_UINT32_WRITE_BITS(rd_value, state, bit_shift, 1);
+
+	rc = dpp_reg_write(dev, DTB_DTB_CFG_CFG_FINISH_INT_EVENT0r + reg_shift, 0,
+					   0, &rd_value);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 清除 dtb 完成中断事件状态
+ * @param   dev_id               芯片id
+ * @param   queue_id             队列ID，范围0-127
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/11/12
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_finish_interrupt_event_state_clr(DPP_DEV_T *dev,
+													 ZXIC_UINT32 queue_id)
+{
+	ZXIC_UINT32 rc = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0,
+										DPP_DTB_QUEUE_NUM_MAX - 1);
+
+	rc = dpp_dtb_finish_interrupt_event_state_set(dev, queue_id, 1);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc,
+								 "dpp_dtb_finish_interrupt_event_state_set");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取DTB debug模式配置
+ * @param   dev_id           芯片id
+ * @param   p_debug_mode       调试模式 当为0x5a时，dtb的ram均可读写
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/11/09
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_debug_mode_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_debug_mode)
+{
+	ZXIC_UINT32 rc = 0;
+	DPP_DTB_DTB_CFG_CFG_DTB_DEBUG_MODE_EN_T dtb_debug_mode = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_debug_mode);
+
+	rc = dpp_reg_read(dev, DTB_DTB_CFG_CFG_DTB_DEBUG_MODE_ENr, 0, 0,
+					  &dtb_debug_mode);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_debug_mode = dtb_debug_mode.cfg_dtb_debug_mode_en;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 判断dtb是否在debug模式
+ * @param   dev_id       芯片的id号
+ *
+ * @return  1:DTB为debug模式; 0:非debug模式
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/6/10
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_mode_is_debug(DPP_DEV_T *dev)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 dtb_mode = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	rc = dpp_dtb_debug_mode_get(dev, &dtb_mode);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_debug_mode_get");
+
+	if (DTB_DEBUG_VALUE == dtb_mode) {
+		return 1;
+	}
+
+	return 0;
+}
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/nppu/dpp_pbu.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/nppu/dpp_pbu.c
old mode 100755
new mode 100644
index 962c73db87da636e231bf6f161f2b1f1cf0d2b0d..76e0cb5b65e64d55a68d2f5583e5d9be14f53196
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/nppu/dpp_pbu.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/nppu/dpp_pbu.c
@@ -1,225 +1,215 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_pbu.c
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : djf
-* 完成日期 : 2014/04/14
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-
-/******************************************************************************
- *                       START: 头文件                       *
- *****************************************************************************/
-#include "zxic_common.h"
-#include "dpp_type_api.h"
-#include "dpp_reg.h"
-#include "dpp_pbu_api.h"
-#include "dpp_pbu.h"
-#include "dpp_dev.h"
-/******************************************************************************
- *                       END: 头文件                       *
- *****************************************************************************/
-
-
-/******************************************************************************
- *                       START: 常量定义                       *
- *****************************************************************************/
-
-/******************************************************************************
- *                       END: 常量定义                       *
- *****************************************************************************/
-#define MF_MAX_BIT (4095)
-#define MF_START_BIT (2047)
-#define PKT_MAX_BIT (2047)
-#define CAP_MAX_NUM (64)
-#define PKT_BUFF_NUM (128)
-#define PKT_BUF_SIZE (32)
-
-
-/***********************************************************/
-/** 配置端口的阈值
-* @param   dev_id   设备编号
-* @param   port_id   端口号
-* @param   p_para   端口阈值
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/07/09
-************************************************************/
-DPP_STATUS dpp_pbu_port_th_set(DPP_DEV_T *dev,
-                               ZXIC_UINT32 port_id,
-                               DPP_PBU_PORT_TH_PARA_T *p_para)
-{
-    DPP_STATUS  rc = 0;
-    ZXIC_UINT32 *p_data = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), port_id, 0, DPP_PBU_PORT_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->lif_th, 0, DPP_PBU_PORT_TH_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->lif_prv, 0, DPP_PBU_PORT_TH_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_prv, 0, DPP_PBU_PORT_TH_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos7, 0, DPP_PBU_PORT_TH_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos6, 0, p_para->idma_th_cos7);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos5, 0, p_para->idma_th_cos6);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos4, 0, p_para->idma_th_cos5);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos3, 0, p_para->idma_th_cos4);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos2, 0, p_para->idma_th_cos3);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos1, 0, p_para->idma_th_cos2);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos0, 0, p_para->idma_th_cos1);
-
-
-    p_data = (ZXIC_UINT32*)p_para;
-
-    rc = dpp_reg_write(dev,
-                       NPPU_PBU_CFG_MEMID_0_PBU_FC_IDMATH_RAMr,
-                       0,
-                       port_id,
-                       p_data);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取端口的阈值
-* @param   dev_id   设备编号
-* @param   port_id   端口号
-* @param   p_para   端口阈值
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/07/09
-************************************************************/
-DPP_STATUS dpp_pbu_port_th_get(DPP_DEV_T *dev,
-                               ZXIC_UINT32 port_id,
-                               DPP_PBU_PORT_TH_PARA_T *p_para)
-{
-    DPP_STATUS  rc = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), port_id, 0, DPP_PBU_PORT_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para);
-
-    rc = dpp_reg_read(dev, NPPU_PBU_CFG_MEMID_0_PBU_FC_IDMATH_RAMr, 0, port_id, (ZXIC_UINT32*)p_para);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置指定端口按cos优先级起pfc流控的优先级流控指针阈值，仅对lif0的48个通道有效
-* @param   dev_id   设备编号
-* @param   port_id   端口号
-* @param   p_para   cos阈值，要求高优先级的阈值不小于低优先级的阈值
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/07/09
-************************************************************/
-DPP_STATUS dpp_pbu_port_cos_th_set(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 port_id,
-                                   DPP_PBU_PORT_COS_TH_PARA_T *p_para)
-{
-    DPP_STATUS  rc = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 tmp_index = 0;
-    ZXIC_UINT32 *p_data = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), port_id, 0, DPP_PBU_PORT_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para);
-
-    if (port_id < DPP_PBU_LIF1_PORT_NUM)
-    {
-        tmp_index = port_id;
-
-    }
-    else if (port_id == DPP_PBU_TM_LOOP_PORT_NUM)
-    {
-        tmp_index = 56;
-
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_pbu_port_cos_th_set: please check input port:%d !!!!!!\n", port_id);
-        return DPP_OK;
-    }
-
-    for (i = 0; i < DPP_PBU_COS_NUM; i++)
-    {
-        if (0 == i)
-        {
-            ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->cos_th[i], 0, DPP_PBU_PORT_COS_MAX_TH );
-        }
-        else
-        {
-            ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->cos_th[i], p_para->cos_th[i - 1], DPP_PBU_PORT_COS_MAX_TH);
-        }
-    }
-
-    p_data = (ZXIC_UINT32*)p_para;
-
-    rc = dpp_reg_write(dev, NPPU_PBU_CFG_MEMID_1_PBU_FC_MACTH_RAMr, 0, tmp_index, p_data );
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 读取指定端口中各cos的优先级流控指针阈值，仅对lif0的48个通道有效
-* @param   dev_id   设备编号
-* @param   port_id   端口号
-* @param   p_para   cos阈值，要求高优先级的阈值不小于低优先级的阈值
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/07/09
-************************************************************/
-DPP_STATUS dpp_pbu_port_cos_th_get(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 port_id,
-                                   DPP_PBU_PORT_COS_TH_PARA_T *p_para)
-{
-    DPP_STATUS  rc = 0;
-    ZXIC_UINT32 tmp_index = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), port_id, 0, DPP_PBU_PORT_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para);
-
-    if (port_id < DPP_PBU_LIF1_PORT_NUM)
-    {
-        tmp_index = port_id;
-
-    }
-    else if (port_id == DPP_PBU_TM_LOOP_PORT_NUM)
-    {
-        tmp_index = 56;
-
-    }
-    else
-    {
-        return DPP_OK;
-    }
-
-    rc = dpp_reg_read(dev, NPPU_PBU_CFG_MEMID_1_PBU_FC_MACTH_RAMr, 0, tmp_index, (ZXIC_UINT32*)p_para);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    return DPP_OK;
-}
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_pbu.c
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : djf
+* 完成日期 : 2014/04/14
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+/******************************************************************************
+ *                       START: 头文件                       *
+ *****************************************************************************/
+#include "zxic_common.h"
+#include "dpp_type_api.h"
+#include "dpp_reg.h"
+#include "dpp_pbu_api.h"
+#include "dpp_pbu.h"
+#include "dpp_dev.h"
+/******************************************************************************
+ *                       END: 头文件                       *
+ *****************************************************************************/
+
+/******************************************************************************
+ *                       START: 常量定义                       *
+ *****************************************************************************/
+
+/******************************************************************************
+ *                       END: 常量定义                       *
+ *****************************************************************************/
+#define MF_MAX_BIT (4095)
+#define MF_START_BIT (2047)
+#define PKT_MAX_BIT (2047)
+#define CAP_MAX_NUM (64)
+#define PKT_BUFF_NUM (128)
+#define PKT_BUF_SIZE (32)
+
+/***********************************************************/
+/** 配置端口的阈值
+ * @param   dev_id   设备编号
+ * @param   port_id   端口号
+ * @param   p_para   端口阈值
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/07/09
+ ************************************************************/
+DPP_STATUS dpp_pbu_port_th_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+							   DPP_PBU_PORT_TH_PARA_T *p_para)
+{
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 *p_data = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), port_id, 0, DPP_PBU_PORT_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->lif_th, 0,
+							  DPP_PBU_PORT_TH_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->lif_prv, 0,
+							  DPP_PBU_PORT_TH_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_prv, 0,
+							  DPP_PBU_PORT_TH_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos7, 0,
+							  DPP_PBU_PORT_TH_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos6, 0,
+							  p_para->idma_th_cos7);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos5, 0,
+							  p_para->idma_th_cos6);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos4, 0,
+							  p_para->idma_th_cos5);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos3, 0,
+							  p_para->idma_th_cos4);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos2, 0,
+							  p_para->idma_th_cos3);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos1, 0,
+							  p_para->idma_th_cos2);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->idma_th_cos0, 0,
+							  p_para->idma_th_cos1);
+
+	p_data = (ZXIC_UINT32 *)p_para;
+
+	rc = dpp_reg_write(dev, NPPU_PBU_CFG_MEMID_0_PBU_FC_IDMATH_RAMr, 0, port_id,
+					   p_data);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取端口的阈值
+ * @param   dev_id   设备编号
+ * @param   port_id   端口号
+ * @param   p_para   端口阈值
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/07/09
+ ************************************************************/
+DPP_STATUS dpp_pbu_port_th_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+							   DPP_PBU_PORT_TH_PARA_T *p_para)
+{
+	DPP_STATUS rc = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), port_id, 0, DPP_PBU_PORT_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para);
+
+	rc = dpp_reg_read(dev, NPPU_PBU_CFG_MEMID_0_PBU_FC_IDMATH_RAMr, 0, port_id,
+					  (ZXIC_UINT32 *)p_para);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置指定端口按cos优先级起pfc流控的优先级流控指针阈值，仅对lif0的48个通道有效
+ * @param   dev_id   设备编号
+ * @param   port_id   端口号
+ * @param   p_para   cos阈值，要求高优先级的阈值不小于低优先级的阈值
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/07/09
+ ************************************************************/
+DPP_STATUS dpp_pbu_port_cos_th_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+								   DPP_PBU_PORT_COS_TH_PARA_T *p_para)
+{
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 tmp_index = 0;
+	ZXIC_UINT32 *p_data = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), port_id, 0, DPP_PBU_PORT_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para);
+
+	if (port_id < DPP_PBU_LIF1_PORT_NUM) {
+		tmp_index = port_id;
+	} else if (port_id == DPP_PBU_TM_LOOP_PORT_NUM) {
+		tmp_index = 56;
+	} else {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev),
+				"dpp_pbu_port_cos_th_set: please check input port:%d !!!!!!\n",
+				port_id);
+		return DPP_OK;
+	}
+
+	for (i = 0; i < DPP_PBU_COS_NUM; i++) {
+		if (0 == i) {
+			ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->cos_th[i], 0,
+									  DPP_PBU_PORT_COS_MAX_TH);
+		} else {
+			ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_para->cos_th[i],
+									  p_para->cos_th[i - 1],
+									  DPP_PBU_PORT_COS_MAX_TH);
+		}
+	}
+
+	p_data = (ZXIC_UINT32 *)p_para;
+
+	rc = dpp_reg_write(dev, NPPU_PBU_CFG_MEMID_1_PBU_FC_MACTH_RAMr, 0,
+					   tmp_index, p_data);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取指定端口中各cos的优先级流控指针阈值，仅对lif0的48个通道有效
+ * @param   dev_id   设备编号
+ * @param   port_id   端口号
+ * @param   p_para   cos阈值，要求高优先级的阈值不小于低优先级的阈值
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/07/09
+ ************************************************************/
+DPP_STATUS dpp_pbu_port_cos_th_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+								   DPP_PBU_PORT_COS_TH_PARA_T *p_para)
+{
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 tmp_index = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), port_id, 0, DPP_PBU_PORT_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para);
+
+	if (port_id < DPP_PBU_LIF1_PORT_NUM) {
+		tmp_index = port_id;
+	} else if (port_id == DPP_PBU_TM_LOOP_PORT_NUM) {
+		tmp_index = 56;
+	} else {
+		return DPP_OK;
+	}
+
+	rc = dpp_reg_read(dev, NPPU_PBU_CFG_MEMID_1_PBU_FC_MACTH_RAMr, 0, tmp_index,
+					  (ZXIC_UINT32 *)p_para);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	return DPP_OK;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/ppu/dpp_ppu.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/ppu/dpp_ppu.c
old mode 100755
new mode 100644
index 699b8eaf9f19fe78815e27b8e87e0a8b8adf91db..97c64368bc42ebfe68b75692070c99c3f22d5ae9
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/ppu/dpp_ppu.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/ppu/dpp_ppu.c
@@ -1,339 +1,283 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_ppu.c
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : 王春雷
-* 完成日期 : 2014/03/18
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-
-#include "zxic_common.h"
-#include "dpp_reg.h"
-#include "dpp_dev.h"
-#include "dpp_ppu_api.h"
-#include "dpp_ppu.h"
-#include "dpp_ppu4k_reg.h"
-
-#define OPR_WRITE                (0)
-#define OPR_READ                 (1)
-
-DPP_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[DPP_DEV_CHANNEL_MAX];
-
-#if ZXIC_REAL("INIT")
-
-ZXIC_UINT32 dpp_ppu_cls_use_set(ZXIC_UINT32 dev_id,
-                           ZXIC_UINT32 cluster_id,
-                           ZXIC_UINT32 flag)
-{
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, cluster_id, 0, DPP_PPU_CLUSTER_NUM - 1);
-    g_ppu_cls_bit_map[dev_id].cls_use[cluster_id] = flag;
-
-    return DPP_OK;
-}
-
-ZXIC_UINT32 dpp_ppu_cls_use_get(ZXIC_UINT32 dev_id,
-                           ZXIC_UINT32 cluster_id)
-{
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, cluster_id, 0, DPP_PPU_CLUSTER_NUM - 1);
-
-    return g_ppu_cls_bit_map[dev_id].cls_use[cluster_id];
-}
-
-ZXIC_UINT32 dpp_ppu_instr_mem_set(ZXIC_UINT32 dev_id,
-                             ZXIC_UINT32 mem_id,
-                             ZXIC_UINT32 flag)
-{
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, mem_id, 0, PPU_INSTR_MEM_NUM - 1);
-    g_ppu_cls_bit_map[dev_id].instr_mem[mem_id] = flag;
-
-    return DPP_OK;
-}
-
-#define DPP_PPU_CLS_USE_CHECK(dev_id,cls_id) \
-    do{ \
-       if (!dpp_ppu_cls_use_get(dev_id, cls_id))\
-         {\
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n %s:%d[Error:cluster %d stop] ! FUNCTION : %s!\n",__FILE__,__LINE__,cls_id,__FUNCTION__);\
-            ZXIC_COMM_ASSERT(0);\
-            return DPP_ERR;\
-         }\
-    }while (0)
-
-ZXIC_UINT32 dpp_ppu_parse_cls_bitmap(ZXIC_UINT32 dev_id,
-                                ZXIC_UINT32 bitmap)
-{
-    ZXIC_UINT32 cls_id = 0;
-    ZXIC_UINT32 mem_id = 0;
-
-    ZXIC_UINT32 cls_use = 0;
-    ZXIC_UINT32 instr_mem = 0;
-
-    /*cluster 使用标记必须保证至少有一个cluster是打开的使用的*/
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, bitmap, 0, DPP_PPU_CLS_ALL_START);
-
-    for (cls_id = 0; cls_id < DPP_PPU_CLUSTER_NUM; cls_id++)
-    {
-        cls_use = (bitmap >> cls_id) & 0x1;
-
-        dpp_ppu_cls_use_set(dev_id, cls_id, cls_use);
-    }
-
-    for (mem_id = 0; mem_id < PPU_INSTR_MEM_NUM; mem_id++)
-    {
-        instr_mem = (bitmap >> (mem_id * 2)) & 0x3;
-
-        dpp_ppu_instr_mem_set(dev_id, mem_id, ((instr_mem > 0) ? 1 : 0));
-    }
-
-    return DPP_OK;
-}
-
-#endif
-
-#if ZXIC_REAL("TABEL_CFG")
-/***********************************************************/
-/** 配置SDT表
-* @param   dev_id   设备号，范围0~3
-* @param   cluster_id  me cluster编号，范围0~7
-* @param   index       地址，即sdt表号，范围0~255
-* @param   p_sdt_data  sdt表数据
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/03/18
-************************************************************/
-DPP_STATUS dpp_ppu_sdt_tbl_write(DPP_DEV_T *dev, ZXIC_UINT32 cluster_id, ZXIC_UINT32 index, DPP_SDT_TBL_DATA_T *p_sdt_data)
-{
-    DPP_STATUS rtn = DPP_OK;
-    DPP_PPU4K_CLUSTER_WR_HIGH_DATA_R_MEX_T high_data = {0};
-    DPP_PPU4K_CLUSTER_WR_LOW_DATA_R_MEX_T  low_data  = {0};
-    DPP_PPU4K_CLUSTER_ADDR_R_MEX_T         sdt_cmd   = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), index, PPU_SDT_IDX_MIN, PPU_SDT_IDX_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_sdt_data);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), cluster_id, 0, DPP_PPU_CLUSTER_NUM - 1);
-    DPP_PPU_CLS_USE_CHECK(DEV_ID(dev), cluster_id);
-
-    /* write data reg*/
-    high_data.wr_high_data_r_mex = p_sdt_data->data_high32;
-    low_data.wr_low_data_r_mex   = p_sdt_data->data_low32;
-    rtn = dpp_reg_write(dev,
-                        PPU4K_CLUSTER_WR_HIGH_DATA_R_MEXr,
-                        cluster_id,
-                        0,
-                        &high_data);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
-
-    rtn = dpp_reg_write(dev,
-                         PPU4K_CLUSTER_WR_LOW_DATA_R_MEXr,
-                         cluster_id,
-                         0,
-                         &low_data);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
-
-    /* write cmd reg*/
-    sdt_cmd.operate_type = OPR_WRITE;
-    sdt_cmd.addr_r_mex   = index;
-
-    rtn = dpp_reg_write(dev,
-                        PPU4K_CLUSTER_ADDR_R_MEXr,
-                        cluster_id,
-                        0,
-                        &sdt_cmd);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
-
-    return DPP_OK;
-}
-#endif
-
-#if ZXIC_REAL("PPU_STATICS")
-
-/***********************************************************/
-/**配置协处理器哈希计算密钥
-* @param   dev_id     设备号
-* @param   DPP_PPU_PPU_COP_THASH_RSK_T 
-*
-* @return
-* @remark  无
-* @see
-* @author  yangmy      @date  2022/09/09
-************************************************************/
-DPP_STATUS dpp_ppu_ppu_cop_thash_rsk_set(DPP_DEV_T *dev, DPP_PPU_PPU_COP_THASH_RSK_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_PPU_PPU_COP_THASH_RSK_031_000_T     rsk_031_000 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_063_032_T     rsk_063_032 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_095_064_T     rsk_095_064 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_127_096_T     rsk_127_096 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_159_128_T     rsk_159_128 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_191_160_T     rsk_191_160 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_223_192_T     rsk_223_192 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_255_224_T     rsk_255_224 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_287_256_T     rsk_287_256 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_319_288_T     rsk_319_288 = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para);
-
-
-
-    rsk_031_000.rsk_031_000 = p_para->rsk_031_000;
-    rsk_063_032.rsk_063_032 = p_para->rsk_063_032;
-    rsk_095_064.rsk_095_064 = p_para->rsk_095_064;
-    rsk_127_096.rsk_127_096 = p_para->rsk_127_096;
-    rsk_159_128.rsk_159_128 = p_para->rsk_159_128;
-    rsk_191_160.rsk_191_160 = p_para->rsk_191_160;
-    rsk_223_192.rsk_223_192 = p_para->rsk_223_192;
-    rsk_255_224.rsk_255_224 = p_para->rsk_255_224;
-    rsk_287_256.rsk_287_256 = p_para->rsk_287_256;
-    rsk_319_288.rsk_319_288 = p_para->rsk_319_288;
-
-
-    rc  = dpp_reg_write(dev,
-                        PPU_PPU_COP_THASH_RSK_031_000r,
-                        0,
-                        0,
-                        &rsk_031_000);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    rc  = dpp_reg_write(dev,
-                        PPU_PPU_COP_THASH_RSK_063_032r,
-                        0,
-                        0,
-                        &rsk_063_032);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    rc  = dpp_reg_write(dev,
-                        PPU_PPU_COP_THASH_RSK_095_064r,
-                        0,
-                        0,
-                        &rsk_095_064);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    rc  = dpp_reg_write(dev,
-                        PPU_PPU_COP_THASH_RSK_127_096r,
-                        0,
-                        0,
-                        &rsk_127_096);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    rc  = dpp_reg_write(dev,
-                        PPU_PPU_COP_THASH_RSK_159_128r,
-                        0,
-                        0,
-                        &rsk_159_128);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    rc  = dpp_reg_write(dev,
-                        PPU_PPU_COP_THASH_RSK_191_160r,
-                        0,
-                        0,
-                        &rsk_191_160);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-        rc  = dpp_reg_write(dev,
-                        PPU_PPU_COP_THASH_RSK_223_192r,
-                        0,
-                        0,
-                        &rsk_223_192);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-
-        rc  = dpp_reg_write(dev,
-                        PPU_PPU_COP_THASH_RSK_255_224r,
-                        0,
-                        0,
-                        &rsk_255_224);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-
-        rc  = dpp_reg_write(dev,
-                        PPU_PPU_COP_THASH_RSK_287_256r,
-                        0,
-                        0,
-                        &rsk_287_256);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-
-        rc  = dpp_reg_write(dev,
-                        PPU_PPU_COP_THASH_RSK_319_288r,
-                        0,
-                        0,
-                        &rsk_319_288);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-    return DPP_OK;
-}
-
-DPP_STATUS dpp_ppu_ppu_cop_thash_rsk_get(DPP_DEV_T *dev, DPP_PPU_PPU_COP_THASH_RSK_T *p_ppu_cop_thash_rsk)
-{
-    DPP_STATUS rtn = DPP_OK;
-
-    DPP_PPU_PPU_COP_THASH_RSK_031_000_T     rsk_031_000 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_063_032_T     rsk_063_032 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_095_064_T     rsk_095_064 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_127_096_T     rsk_127_096 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_159_128_T     rsk_159_128 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_191_160_T     rsk_191_160 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_223_192_T     rsk_223_192 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_255_224_T     rsk_255_224 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_287_256_T     rsk_287_256 = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_319_288_T     rsk_319_288 = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ppu_cop_thash_rsk);
-
-    rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_031_000r, 0, 0, &rsk_031_000);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
-    rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_063_032r, 0, 0, &rsk_063_032);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
-    rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_095_064r, 0, 0, &rsk_095_064);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
-    rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_127_096r, 0, 0, &rsk_127_096);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
-    rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_159_128r, 0, 0, &rsk_159_128);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
-    rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_191_160r, 0, 0, &rsk_191_160);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
-    rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_223_192r, 0, 0, &rsk_223_192);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
-    rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_255_224r, 0, 0, &rsk_255_224);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
-    rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_287_256r, 0, 0, &rsk_287_256);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
-    rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_319_288r, 0, 0, &rsk_319_288);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
-
-
-    p_ppu_cop_thash_rsk->rsk_031_000  = rsk_031_000.rsk_031_000;
-    p_ppu_cop_thash_rsk->rsk_063_032  = rsk_063_032.rsk_063_032;
-    p_ppu_cop_thash_rsk->rsk_095_064  = rsk_095_064.rsk_095_064;
-    p_ppu_cop_thash_rsk->rsk_127_096  = rsk_127_096.rsk_127_096;
-    p_ppu_cop_thash_rsk->rsk_159_128  = rsk_159_128.rsk_159_128;
-    p_ppu_cop_thash_rsk->rsk_191_160  = rsk_191_160.rsk_191_160;
-    p_ppu_cop_thash_rsk->rsk_223_192  = rsk_223_192.rsk_223_192;
-    p_ppu_cop_thash_rsk->rsk_255_224  = rsk_255_224.rsk_255_224;
-    p_ppu_cop_thash_rsk->rsk_287_256  = rsk_287_256.rsk_287_256;
-    p_ppu_cop_thash_rsk->rsk_319_288  = rsk_319_288.rsk_319_288;
-
-
-    return DPP_OK;
-
-}
-
-#endif
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_ppu.c
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2014/03/18
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#include "zxic_common.h"
+#include "dpp_reg.h"
+#include "dpp_dev.h"
+#include "dpp_ppu_api.h"
+#include "dpp_ppu.h"
+#include "dpp_ppu4k_reg.h"
+
+#define OPR_WRITE (0)
+#define OPR_READ (1)
+
+DPP_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[DPP_DEV_CHANNEL_MAX];
+
+#if ZXIC_REAL("INIT")
+
+ZXIC_UINT32 dpp_ppu_cls_use_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 cluster_id,
+								ZXIC_UINT32 flag)
+{
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, cluster_id, 0, DPP_PPU_CLUSTER_NUM - 1);
+	g_ppu_cls_bit_map[dev_id].cls_use[cluster_id] = flag;
+
+	return DPP_OK;
+}
+
+ZXIC_UINT32 dpp_ppu_cls_use_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 cluster_id)
+{
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, cluster_id, 0, DPP_PPU_CLUSTER_NUM - 1);
+
+	return g_ppu_cls_bit_map[dev_id].cls_use[cluster_id];
+}
+
+ZXIC_UINT32 dpp_ppu_instr_mem_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 mem_id,
+								  ZXIC_UINT32 flag)
+{
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, mem_id, 0, PPU_INSTR_MEM_NUM - 1);
+	g_ppu_cls_bit_map[dev_id].instr_mem[mem_id] = flag;
+
+	return DPP_OK;
+}
+
+#define DPP_PPU_CLS_USE_CHECK(dev_id, cls_id)                             \
+	do {                                                                  \
+		if (!dpp_ppu_cls_use_get(dev_id, cls_id)) {                       \
+			ZXIC_COMM_TRACE_DEV_ERROR(                                    \
+					dev_id,                                               \
+					"\n %s:%d[Error:cluster %d stop] ! FUNCTION : %s!\n", \
+					__FILE__, __LINE__, cls_id, __FUNCTION__);            \
+			ZXIC_COMM_ASSERT(0);                                          \
+			return DPP_ERR;                                               \
+		}                                                                 \
+	} while (0)
+
+ZXIC_UINT32 dpp_ppu_parse_cls_bitmap(ZXIC_UINT32 dev_id, ZXIC_UINT32 bitmap)
+{
+	ZXIC_UINT32 cls_id = 0;
+	ZXIC_UINT32 mem_id = 0;
+
+	ZXIC_UINT32 cls_use = 0;
+	ZXIC_UINT32 instr_mem = 0;
+
+	/*cluster 使用标记必须保证至少有一个cluster是打开的使用的*/
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, bitmap, 0, DPP_PPU_CLS_ALL_START);
+
+	for (cls_id = 0; cls_id < DPP_PPU_CLUSTER_NUM; cls_id++) {
+		cls_use = (bitmap >> cls_id) & 0x1;
+
+		dpp_ppu_cls_use_set(dev_id, cls_id, cls_use);
+	}
+
+	for (mem_id = 0; mem_id < PPU_INSTR_MEM_NUM; mem_id++) {
+		instr_mem = (bitmap >> (mem_id * 2)) & 0x3;
+
+		dpp_ppu_instr_mem_set(dev_id, mem_id, ((instr_mem > 0) ? 1 : 0));
+	}
+
+	return DPP_OK;
+}
+
+#endif
+
+#if ZXIC_REAL("TABEL_CFG")
+/***********************************************************/
+/** 配置SDT表
+ * @param   dev_id   设备号，范围0~3
+ * @param   cluster_id  me cluster编号，范围0~7
+ * @param   index       地址，即sdt表号，范围0~255
+ * @param   p_sdt_data  sdt表数据
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/03/18
+ ************************************************************/
+DPP_STATUS dpp_ppu_sdt_tbl_write(DPP_DEV_T *dev, ZXIC_UINT32 cluster_id,
+								 ZXIC_UINT32 index,
+								 DPP_SDT_TBL_DATA_T *p_sdt_data)
+{
+	DPP_STATUS rtn = DPP_OK;
+	DPP_PPU4K_CLUSTER_WR_HIGH_DATA_R_MEX_T high_data = { 0 };
+	DPP_PPU4K_CLUSTER_WR_LOW_DATA_R_MEX_T low_data = { 0 };
+	DPP_PPU4K_CLUSTER_ADDR_R_MEX_T sdt_cmd = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), index, PPU_SDT_IDX_MIN,
+							  PPU_SDT_IDX_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_sdt_data);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), cluster_id, 0,
+							  DPP_PPU_CLUSTER_NUM - 1);
+	DPP_PPU_CLS_USE_CHECK(DEV_ID(dev), cluster_id);
+
+	/* write data reg*/
+	high_data.wr_high_data_r_mex = p_sdt_data->data_high32;
+	low_data.wr_low_data_r_mex = p_sdt_data->data_low32;
+	rtn = dpp_reg_write(dev, PPU4K_CLUSTER_WR_HIGH_DATA_R_MEXr, cluster_id, 0,
+						&high_data);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
+
+	rtn = dpp_reg_write(dev, PPU4K_CLUSTER_WR_LOW_DATA_R_MEXr, cluster_id, 0,
+						&low_data);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
+
+	/* write cmd reg*/
+	sdt_cmd.operate_type = OPR_WRITE;
+	sdt_cmd.addr_r_mex = index;
+
+	rtn = dpp_reg_write(dev, PPU4K_CLUSTER_ADDR_R_MEXr, cluster_id, 0,
+						&sdt_cmd);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
+
+	return DPP_OK;
+}
+#endif
+
+#if ZXIC_REAL("PPU_STATICS")
+
+/***********************************************************/
+/**配置协处理器哈希计算密钥
+ * @param   dev_id     设备号
+ * @param   DPP_PPU_PPU_COP_THASH_RSK_T
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  yangmy      @date  2022/09/09
+ ************************************************************/
+DPP_STATUS dpp_ppu_ppu_cop_thash_rsk_set(DPP_DEV_T *dev,
+										 DPP_PPU_PPU_COP_THASH_RSK_T *p_para)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_PPU_PPU_COP_THASH_RSK_031_000_T rsk_031_000 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_063_032_T rsk_063_032 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_095_064_T rsk_095_064 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_127_096_T rsk_127_096 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_159_128_T rsk_159_128 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_191_160_T rsk_191_160 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_223_192_T rsk_223_192 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_255_224_T rsk_255_224 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_287_256_T rsk_287_256 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_319_288_T rsk_319_288 = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para);
+
+	rsk_031_000.rsk_031_000 = p_para->rsk_031_000;
+	rsk_063_032.rsk_063_032 = p_para->rsk_063_032;
+	rsk_095_064.rsk_095_064 = p_para->rsk_095_064;
+	rsk_127_096.rsk_127_096 = p_para->rsk_127_096;
+	rsk_159_128.rsk_159_128 = p_para->rsk_159_128;
+	rsk_191_160.rsk_191_160 = p_para->rsk_191_160;
+	rsk_223_192.rsk_223_192 = p_para->rsk_223_192;
+	rsk_255_224.rsk_255_224 = p_para->rsk_255_224;
+	rsk_287_256.rsk_287_256 = p_para->rsk_287_256;
+	rsk_319_288.rsk_319_288 = p_para->rsk_319_288;
+
+	rc = dpp_reg_write(dev, PPU_PPU_COP_THASH_RSK_031_000r, 0, 0, &rsk_031_000);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	rc = dpp_reg_write(dev, PPU_PPU_COP_THASH_RSK_063_032r, 0, 0, &rsk_063_032);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	rc = dpp_reg_write(dev, PPU_PPU_COP_THASH_RSK_095_064r, 0, 0, &rsk_095_064);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	rc = dpp_reg_write(dev, PPU_PPU_COP_THASH_RSK_127_096r, 0, 0, &rsk_127_096);
+
+	rc = dpp_reg_write(dev, PPU_PPU_COP_THASH_RSK_159_128r, 0, 0, &rsk_159_128);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	rc = dpp_reg_write(dev, PPU_PPU_COP_THASH_RSK_191_160r, 0, 0, &rsk_191_160);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	rc = dpp_reg_write(dev, PPU_PPU_COP_THASH_RSK_223_192r, 0, 0, &rsk_223_192);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	rc = dpp_reg_write(dev, PPU_PPU_COP_THASH_RSK_255_224r, 0, 0, &rsk_255_224);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	rc = dpp_reg_write(dev, PPU_PPU_COP_THASH_RSK_287_256r, 0, 0, &rsk_287_256);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	rc = dpp_reg_write(dev, PPU_PPU_COP_THASH_RSK_319_288r, 0, 0, &rsk_319_288);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+	return DPP_OK;
+}
+
+DPP_STATUS
+dpp_ppu_ppu_cop_thash_rsk_get(DPP_DEV_T *dev,
+							  DPP_PPU_PPU_COP_THASH_RSK_T *p_ppu_cop_thash_rsk)
+{
+	DPP_STATUS rtn = DPP_OK;
+
+	DPP_PPU_PPU_COP_THASH_RSK_031_000_T rsk_031_000 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_063_032_T rsk_063_032 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_095_064_T rsk_095_064 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_127_096_T rsk_127_096 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_159_128_T rsk_159_128 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_191_160_T rsk_191_160 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_223_192_T rsk_223_192 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_255_224_T rsk_255_224 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_287_256_T rsk_287_256 = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_319_288_T rsk_319_288 = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ppu_cop_thash_rsk);
+
+	rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_031_000r, 0, 0, &rsk_031_000);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
+	rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_063_032r, 0, 0, &rsk_063_032);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
+	rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_095_064r, 0, 0, &rsk_095_064);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
+	rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_127_096r, 0, 0, &rsk_127_096);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
+	rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_159_128r, 0, 0, &rsk_159_128);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
+	rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_191_160r, 0, 0, &rsk_191_160);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
+	rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_223_192r, 0, 0, &rsk_223_192);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
+	rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_255_224r, 0, 0, &rsk_255_224);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
+	rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_287_256r, 0, 0, &rsk_287_256);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
+	rtn = dpp_reg_read(dev, PPU_PPU_COP_THASH_RSK_319_288r, 0, 0, &rsk_319_288);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
+
+	p_ppu_cop_thash_rsk->rsk_031_000 = rsk_031_000.rsk_031_000;
+	p_ppu_cop_thash_rsk->rsk_063_032 = rsk_063_032.rsk_063_032;
+	p_ppu_cop_thash_rsk->rsk_095_064 = rsk_095_064.rsk_095_064;
+	p_ppu_cop_thash_rsk->rsk_127_096 = rsk_127_096.rsk_127_096;
+	p_ppu_cop_thash_rsk->rsk_159_128 = rsk_159_128.rsk_159_128;
+	p_ppu_cop_thash_rsk->rsk_191_160 = rsk_191_160.rsk_191_160;
+	p_ppu_cop_thash_rsk->rsk_223_192 = rsk_223_192.rsk_223_192;
+	p_ppu_cop_thash_rsk->rsk_255_224 = rsk_255_224.rsk_255_224;
+	p_ppu_cop_thash_rsk->rsk_287_256 = rsk_287_256.rsk_287_256;
+	p_ppu_cop_thash_rsk->rsk_319_288 = rsk_319_288.rsk_319_288;
+
+	return DPP_OK;
+}
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_etcam.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_etcam.c
index f92a6fec7642ab58c6b261bb6a30e166118ce534..ed7565a36affc763bda6e1457f7e97c5f1dd48f4 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_etcam.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_etcam.c
@@ -25,282 +25,259 @@
 #include "dpp_dev.h"
 #include "dpp_stat4k_reg.h"
 
-#define DPP_ETCAM_OPR_WR            (1)
-#define DPP_ETCAM_OPR_RD            (2)
-#define DPP_ETCAM_OPR_UNLOAD        (3)
-#define DPP_ETCAM_OPR_VBIT          (4)
+#define DPP_ETCAM_OPR_WR (1)
+#define DPP_ETCAM_OPR_RD (2)
+#define DPP_ETCAM_OPR_UNLOAD (3)
+#define DPP_ETCAM_OPR_VBIT (4)
 
-#define TBLID_CFG_SETP          (8)
-#define BADDR_CFG_SETP          (4)
+#define TBLID_CFG_SETP (8)
+#define BADDR_CFG_SETP (4)
 
 /** 当前etcam 条目vld信息 */
-DPP_ETCAM_ENTRY_VLD_T g_etcam_vld_info[DPP_DEV_CHANNEL_MAX][DPP_ETCAM_BLOCK_NUM][DPP_ETCAM_RAM_DEPTH] = {{{{0}}}};
-#define GET_ETCAM_VLD_INFO(dev_id,block_id,block_index)     (g_etcam_vld_info[dev_id][block_id] + block_index)
+DPP_ETCAM_ENTRY_VLD_T g_etcam_vld_info[DPP_DEV_CHANNEL_MAX][DPP_ETCAM_BLOCK_NUM]
+									  [DPP_ETCAM_RAM_DEPTH] = { { { { 0 } } } };
+#define GET_ETCAM_VLD_INFO(dev_id, block_id, block_index) \
+	(g_etcam_vld_info[dev_id][block_id] + block_index)
 
 #if ZXIC_REAL("IN_FUNC")
 /***********************************************************/
 /** 将用户输入的D/M格式的数据转换为写硬件需要的X/Y数据
-* @param   p_dm
-* @param   p_xy
-* @param   len
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/04/03
-************************************************************/
-DPP_STATUS dpp_etcam_dm_to_xy(DPP_ETCAM_ENTRY_T *p_dm,
-                              DPP_ETCAM_ENTRY_T *p_xy,
-                              ZXIC_UINT32 len)
+ * @param   p_dm
+ * @param   p_xy
+ * @param   len
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/04/03
+ ************************************************************/
+DPP_STATUS dpp_etcam_dm_to_xy(DPP_ETCAM_ENTRY_T *p_dm, DPP_ETCAM_ENTRY_T *p_xy,
+							  ZXIC_UINT32 len)
 {
-    ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 i = 0;
 
-    ZXIC_COMM_CHECK_POINT(p_dm);
-    ZXIC_COMM_CHECK_POINT(p_xy);
-    ZXIC_COMM_CHECK_INDEX(len, 0, DPP_ETCAM_WIDTH_MAX / 8);
-    ZXIC_COMM_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data && p_xy->p_mask);
+	ZXIC_COMM_CHECK_POINT(p_dm);
+	ZXIC_COMM_CHECK_POINT(p_xy);
+	ZXIC_COMM_CHECK_INDEX(len, 0, DPP_ETCAM_WIDTH_MAX / 8);
+	ZXIC_COMM_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data &&
+					 p_xy->p_mask);
 
-    for (i = 0; i < len; i++)
-    {
-        p_xy->p_data[i] = ZXIC_COMM_DM_TO_X(p_dm->p_data[i], p_dm->p_mask[i]);
-        p_xy->p_mask[i] = ZXIC_COMM_DM_TO_Y(p_dm->p_data[i], p_dm->p_mask[i]);
-    }
+	for (i = 0; i < len; i++) {
+		p_xy->p_data[i] = ZXIC_COMM_DM_TO_X(p_dm->p_data[i], p_dm->p_mask[i]);
+		p_xy->p_mask[i] = ZXIC_COMM_DM_TO_Y(p_dm->p_data[i], p_dm->p_mask[i]);
+	}
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 将从硬件读到的X/Y格式的数据转换为用户需要的D/M数据
-* @param   p_xy
-* @param   p_dm
-* @param   len
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/04/03
-************************************************************/
-DPP_STATUS dpp_etcam_xy_to_dm(DPP_ETCAM_ENTRY_T *p_dm,
-                              DPP_ETCAM_ENTRY_T *p_xy,
-                              ZXIC_UINT32 len)
+ * @param   p_xy
+ * @param   p_dm
+ * @param   len
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/04/03
+ ************************************************************/
+DPP_STATUS dpp_etcam_xy_to_dm(DPP_ETCAM_ENTRY_T *p_dm, DPP_ETCAM_ENTRY_T *p_xy,
+							  ZXIC_UINT32 len)
 {
-    ZXIC_UINT32 i = 0;
-
-    ZXIC_COMM_CHECK_POINT(p_dm);
-    ZXIC_COMM_CHECK_POINT(p_xy);
-    ZXIC_COMM_CHECK_INDEX(len, 0, DPP_ETCAM_WIDTH_MAX / 8);
-    ZXIC_COMM_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data && p_xy->p_mask);
-
-    for (i = 0; i < len; i++)
-    {
-        p_dm->p_data[i] = ZXIC_COMM_XY_TO_DATA(p_xy->p_data[i], p_xy->p_mask[i]); /* valid only when mask is 0 */
-        p_dm->p_mask[i] = ZXIC_COMM_XY_TO_MASK(p_xy->p_data[i], p_xy->p_mask[i]);
-    }
-
-    return DPP_OK;
+	ZXIC_UINT32 i = 0;
+
+	ZXIC_COMM_CHECK_POINT(p_dm);
+	ZXIC_COMM_CHECK_POINT(p_xy);
+	ZXIC_COMM_CHECK_INDEX(len, 0, DPP_ETCAM_WIDTH_MAX / 8);
+	ZXIC_COMM_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data &&
+					 p_xy->p_mask);
+
+	for (i = 0; i < len; i++) {
+		p_dm->p_data[i] = ZXIC_COMM_XY_TO_DATA(
+				p_xy->p_data[i],
+				p_xy->p_mask[i]); /* valid only when mask is 0 */
+		p_dm->p_mask[i] =
+				ZXIC_COMM_XY_TO_MASK(p_xy->p_data[i], p_xy->p_mask[i]);
+	}
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 根据读写模式，获取需要操作的间接寄存器掩码
-* @param   mask  block RAM操作位图，共8比特，每比特对应一个block RAM行的80bit
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/03/31
-************************************************************/
+ * @param   mask  block RAM操作位图，共8比特，每比特对应一个block RAM行的80bit
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/03/31
+ ************************************************************/
 ZXIC_UINT32 dpp_etcam_ind_data_reg_opr_mask_get(ZXIC_UINT32 mask)
 {
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 reg_mask = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 reg_mask = 0;
 
-    ZXIC_COMM_CHECK_INDEX(mask, 0, 0xff);
+	ZXIC_COMM_CHECK_INDEX(mask, 0, 0xff);
 
-    for (i = 0; i < DPP_ETCAM_RAM_NUM; i++)
-    {
-        if ((mask >> i) & 0x1)
-        {
-            reg_mask |= ((ZXIC_UINT32)0x7 << ((i / 2) * 5 + (i % 2) * 2));
-        }
-    }
+	for (i = 0; i < DPP_ETCAM_RAM_NUM; i++) {
+		if ((mask >> i) & 0x1) {
+			reg_mask |= ((ZXIC_UINT32)0x7 << ((i / 2) * 5 + (i % 2) * 2));
+		}
+	}
 
-    return reg_mask;
+	return reg_mask;
 }
 
 /***********************************************************/
 /** 写eTcam表项数据
-* @param   dev_id
-* @param   wr_mask
-* @param   p_data
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/03/31
-************************************************************/
-DPP_STATUS dpp_etcam_ind_data_set(DPP_DEV_T *dev, ZXIC_UINT32 wr_mask, ZXIC_UINT8 *p_data)
+ * @param   dev_id
+ * @param   wr_mask
+ * @param   p_data
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/03/31
+ ************************************************************/
+DPP_STATUS dpp_etcam_ind_data_set(DPP_DEV_T *dev, ZXIC_UINT32 wr_mask,
+								  ZXIC_UINT8 *p_data)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 offset = 0;
-    ZXIC_UINT32 reg_mask = 0;
-    ZXIC_UINT8 *p_temp = NULL;
-    ZXIC_UINT8  buff[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mask, 0, DPP_ETCAM_WR_MASK_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-
-    p_temp = p_data;
-
-    /* 160bit key: high 80bit in tcam_ram1, low 80bit in tcam_ram0, and so on. */
-    for (i = 0; i < DPP_ETCAM_RAM_NUM; i++)
-    {
-        offset = i * ((ZXIC_UINT32)DPP_ETCAM_WIDTH_MIN / 8);
-
-        if ((wr_mask >> (DPP_ETCAM_RAM_NUM - 1 - i)) & 0x1)
-        {
-            ZXIC_COMM_MEMCPY(buff + offset, p_temp, DPP_ETCAM_WIDTH_MIN / 8);
-            p_temp += DPP_ETCAM_WIDTH_MIN / 8;
-        }
-    }
-
-    zxic_comm_swap(buff, DPP_ETCAM_WIDTH_MAX / 8);
-
-    /* get ind data reg operate mask, 20bit */
-    reg_mask = dpp_etcam_ind_data_reg_opr_mask_get(wr_mask);
-
-    /* cpu_ind_wdat0 reg is for lowest 32bit data. */
-    for (i = 0; i < (DPP_ETCAM_WIDTH_MAX / 32); i++)
-    {
-        if ((reg_mask >> (DPP_ETCAM_WIDTH_MAX / 32 - 1 - i)) & 0x1)
-        {
-            rc = dpp_reg_write(dev,
-                               STAT_ETCAM_CPU_IND_WDAT19r - i,
-                               0,
-                               0,
-                               (buff + i * sizeof(ZXIC_UINT32)));
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-        }
-    }
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 offset = 0;
+	ZXIC_UINT32 reg_mask = 0;
+	ZXIC_UINT8 *p_temp = NULL;
+	ZXIC_UINT8 buff[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mask, 0, DPP_ETCAM_WR_MASK_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+
+	p_temp = p_data;
+
+	/* 160bit key: high 80bit in tcam_ram1, low 80bit in tcam_ram0, and so on. */
+	for (i = 0; i < DPP_ETCAM_RAM_NUM; i++) {
+		offset = i * ((ZXIC_UINT32)DPP_ETCAM_WIDTH_MIN / 8);
+
+		if ((wr_mask >> (DPP_ETCAM_RAM_NUM - 1 - i)) & 0x1) {
+			ZXIC_COMM_MEMCPY(buff + offset, p_temp, DPP_ETCAM_WIDTH_MIN / 8);
+			p_temp += DPP_ETCAM_WIDTH_MIN / 8;
+		}
+	}
+
+	zxic_comm_swap(buff, DPP_ETCAM_WIDTH_MAX / 8);
+
+	/* get ind data reg operate mask, 20bit */
+	reg_mask = dpp_etcam_ind_data_reg_opr_mask_get(wr_mask);
+
+	/* cpu_ind_wdat0 reg is for lowest 32bit data. */
+	for (i = 0; i < (DPP_ETCAM_WIDTH_MAX / 32); i++) {
+		if ((reg_mask >> (DPP_ETCAM_WIDTH_MAX / 32 - 1 - i)) & 0x1) {
+			rc = dpp_reg_write(dev, STAT_ETCAM_CPU_IND_WDAT19r - i, 0, 0,
+							   (buff + i * sizeof(ZXIC_UINT32)));
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+		}
+	}
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 写eTcam间接命令寄存器
-* @param   dev_id
-* @param   addr            etcam地址(0-511)
-* @param   block_idx       block索引(0-15)
-* @param   data_or_mask    1：写X(data), 0:写Y(mask)
-* @param   wr_mask         写入掩码, 最高8bit, 对应bit为1代表对应的80bit数据
-* @param   opr_type        1-write, 2-read, 3-unload
-* @param   tacm_reg_flag   1：配置内部row_col_mask寄存器 还是0：读写tcam
-* @param   row_mask_flag   1: write row_mask reg, 0: write col_mask reg
-* @param   vben            enable the valid bit addressed by addr
-* @param   vbit            valid bit input
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷         @date  2014/03/29
-* @modify  YXH         @date  2018/11/29
-************************************************************/
-DPP_STATUS dpp_etcam_ind_cmd_set(DPP_DEV_T *dev,
-                                 ZXIC_UINT32 addr,
-                                 ZXIC_UINT32 block_idx,
-                                 ZXIC_UINT32 data_or_mask,
-                                 ZXIC_UINT32 wr_mask,
-                                 ZXIC_UINT32 opr_type,
-                                 ZXIC_UINT32 tacm_reg_flag,
-                                 ZXIC_UINT32 row_mask_flag,
-                                 ZXIC_UINT32 vben,
-                                 ZXIC_UINT32 vbit)
+ * @param   dev_id
+ * @param   addr            etcam地址(0-511)
+ * @param   block_idx       block索引(0-15)
+ * @param   data_or_mask    1：写X(data), 0:写Y(mask)
+ * @param   wr_mask         写入掩码, 最高8bit, 对应bit为1代表对应的80bit数据
+ * @param   opr_type        1-write, 2-read, 3-unload
+ * @param   tacm_reg_flag   1：配置内部row_col_mask寄存器 还是0：读写tcam
+ * @param   row_mask_flag   1: write row_mask reg, 0: write col_mask reg
+ * @param   vben            enable the valid bit addressed by addr
+ * @param   vbit            valid bit input
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷         @date  2014/03/29
+ * @modify  YXH         @date  2018/11/29
+ ************************************************************/
+DPP_STATUS dpp_etcam_ind_cmd_set(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+								 ZXIC_UINT32 block_idx,
+								 ZXIC_UINT32 data_or_mask, ZXIC_UINT32 wr_mask,
+								 ZXIC_UINT32 opr_type,
+								 ZXIC_UINT32 tacm_reg_flag,
+								 ZXIC_UINT32 row_mask_flag, ZXIC_UINT32 vben,
+								 ZXIC_UINT32 vbit)
 {
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_ETCAM_CPU_IND_CTRL_TMP0_T ind_cmd = {0};
-    DPP_STAT_ETCAM_CPU_IND_CTRL_TMP1_T ind_cmd_1 = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), addr, 0, DPP_ETCAM_RAM_DEPTH - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), data_or_mask, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mask, 0, DPP_ETCAM_WR_MASK_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), opr_type, 1, 4);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), tacm_reg_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), row_mask_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), vben, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), vbit, 0, 0xff);
-
-    /* 一定要先配置 配置寄存器1,再配置 配置寄存器0 */
-    ind_cmd_1.row_or_col_msk = row_mask_flag;
-    ind_cmd_1.vben = vben;
-    ind_cmd_1.vbit = vbit;
-
-    rc = dpp_reg_write(dev,
-                       STAT_ETCAM_CPU_IND_CTRL_TMP1r,
-                       0,
-                       0,
-                       &ind_cmd_1);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    /* opr_type: 1-write, 2-read, 3-unload */
-    switch (opr_type)
-    {
-        case DPP_ETCAM_OPR_RD:
-        {
-            ind_cmd.rd_wr = 1;
-        }
-        break;
-
-        case DPP_ETCAM_OPR_WR:
-        {
-            ind_cmd.rd_wr = 0;
-            ind_cmd.wr_mode = wr_mask;
-        }
-        break;
-
-        case DPP_ETCAM_OPR_UNLOAD:
-        {
-            /* 掩码表，决定哪些条目删除,8bit */
-            ind_cmd.flush = wr_mask;
-        }
-        break;
-
-        case DPP_ETCAM_OPR_VBIT:
-        {
-            /* 获取该地址的vbit valid位状态 */
-            ind_cmd.rd_wr = 1;
-            ind_cmd.wr_mode = wr_mask;
-        }
-        break;
-
-        default:
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Invalid opr_type!\n");
-            ZXIC_COMM_ASSERT(0);
-            return DPP_ERR;
-        }
-    }
-
-    ind_cmd.dat_or_mask = data_or_mask;
-    ind_cmd.ram_sel = block_idx;
-    ind_cmd.addr = addr;
-
-    ZXIC_COMM_TRACE_DEBUG("data_or_mask:%d\n", ind_cmd.dat_or_mask);
-    ZXIC_COMM_TRACE_DEBUG("block_idx:%d\n", ind_cmd.ram_sel);
-    ZXIC_COMM_TRACE_DEBUG("addr:0x%08x\n", ind_cmd.addr);
-
-    rc = dpp_reg_write(dev,
-                       STAT_ETCAM_CPU_IND_CTRL_TMP0r,
-                       0,
-                       0,
-                       &ind_cmd);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_ETCAM_CPU_IND_CTRL_TMP0_T ind_cmd = { 0 };
+	DPP_STAT_ETCAM_CPU_IND_CTRL_TMP1_T ind_cmd_1 = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), addr, 0, DPP_ETCAM_RAM_DEPTH - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0,
+							  DPP_ETCAM_BLOCK_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), data_or_mask, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mask, 0, DPP_ETCAM_WR_MASK_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), opr_type, 1, 4);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), tacm_reg_flag, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), row_mask_flag, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), vben, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), vbit, 0, 0xff);
+
+	/* 一定要先配置 配置寄存器1,再配置 配置寄存器0 */
+	ind_cmd_1.row_or_col_msk = row_mask_flag;
+	ind_cmd_1.vben = vben;
+	ind_cmd_1.vbit = vbit;
+
+	rc = dpp_reg_write(dev, STAT_ETCAM_CPU_IND_CTRL_TMP1r, 0, 0, &ind_cmd_1);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	/* opr_type: 1-write, 2-read, 3-unload */
+	switch (opr_type) {
+	case DPP_ETCAM_OPR_RD: {
+		ind_cmd.rd_wr = 1;
+	} break;
+
+	case DPP_ETCAM_OPR_WR: {
+		ind_cmd.rd_wr = 0;
+		ind_cmd.wr_mode = wr_mask;
+	} break;
+
+	case DPP_ETCAM_OPR_UNLOAD: {
+		/* 掩码表，决定哪些条目删除,8bit */
+		ind_cmd.flush = wr_mask;
+	} break;
+
+	case DPP_ETCAM_OPR_VBIT: {
+		/* 获取该地址的vbit valid位状态 */
+		ind_cmd.rd_wr = 1;
+		ind_cmd.wr_mode = wr_mask;
+	} break;
+
+	default: {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Invalid opr_type!\n");
+		ZXIC_COMM_ASSERT(0);
+		return DPP_ERR;
+	}
+	}
+
+	ind_cmd.dat_or_mask = data_or_mask;
+	ind_cmd.ram_sel = block_idx;
+	ind_cmd.addr = addr;
+
+	ZXIC_COMM_TRACE_DEBUG("data_or_mask:%d\n", ind_cmd.dat_or_mask);
+	ZXIC_COMM_TRACE_DEBUG("block_idx:%d\n", ind_cmd.ram_sel);
+	ZXIC_COMM_TRACE_DEBUG("addr:0x%08x\n", ind_cmd.addr);
+
+	rc = dpp_reg_write(dev, STAT_ETCAM_CPU_IND_CTRL_TMP0r, 0, 0, &ind_cmd);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
 }
 
 #endif
@@ -308,507 +285,481 @@ DPP_STATUS dpp_etcam_ind_cmd_set(DPP_DEV_T *dev,
 #if ZXIC_REAL("EX_FUNC")
 /***********************************************************/
 /** 获取etcam中每个block的cpu操作fifo将满信号，若将满则cpu不能再操作当前block
-* @param   dev_id      设备号
-* @param   block_idx   etcam中的block编号，范围0~15
-* @param   p_cpu_afull
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/02/07
-************************************************************/
-DPP_STATUS dpp_etcam_cpu_afull_get(DPP_DEV_T *dev, ZXIC_UINT32 block_idx, ZXIC_UINT32 *p_cpu_afull)
+ * @param   dev_id      设备号
+ * @param   block_idx   etcam中的block编号，范围0~15
+ * @param   p_cpu_afull
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/02/07
+ ************************************************************/
+DPP_STATUS dpp_etcam_cpu_afull_get(DPP_DEV_T *dev, ZXIC_UINT32 block_idx,
+								   ZXIC_UINT32 *p_cpu_afull)
 {
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_ETCAM_ETCAM_CPU_FL_T cpu_fl = {0};
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_ETCAM_ETCAM_CPU_FL_T cpu_fl = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cpu_afull);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0,
+							  DPP_ETCAM_BLOCK_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cpu_afull);
 
-    rc = dpp_reg_read(dev, STAT_ETCAM_ETCAM_CPU_FLr, 0, 0, &cpu_fl);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+	rc = dpp_reg_read(dev, STAT_ETCAM_ETCAM_CPU_FLr, 0, 0, &cpu_fl);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
 
-    *p_cpu_afull = (cpu_fl.etcam_cpu_fl >> block_idx) & 0x1;
+	*p_cpu_afull = (cpu_fl.etcam_cpu_fl >> block_idx) & 0x1;
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 校验etcam中每个block的cpu操作fifo将满信号，若将满则cpu不能再操作当前block
-* @param   dev_id      设备号
-* @param   block_idx   etcam中的block编号，范围0~7
-*
-* @return
-* @remark  无
-* @see
-* @author  wll      @date  2019/04/15
-************************************************************/
+ * @param   dev_id      设备号
+ * @param   block_idx   etcam中的block编号，范围0~7
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wll      @date  2019/04/15
+ ************************************************************/
 DPP_STATUS dpp_etcam_cpu_afull_check(DPP_DEV_T *dev, ZXIC_UINT32 block_idx)
 {
-    ZXIC_UINT32 read_cnt = 0;
-    ZXIC_UINT32 cpu_afull = 1;
-    DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 read_cnt = 0;
+	ZXIC_UINT32 cpu_afull = 1;
+	DPP_STATUS rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0,
+							  DPP_ETCAM_BLOCK_NUM - 1);
 
-    while (cpu_afull)
-    {
-        rc = dpp_etcam_cpu_afull_get(dev, block_idx, &cpu_afull);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_etcam_cpu_afull_get");
+	while (cpu_afull) {
+		rc = dpp_etcam_cpu_afull_get(dev, block_idx, &cpu_afull);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_etcam_cpu_afull_get");
 
-        if (!cpu_afull)
-        {
-            break;
-        }
+		if (!cpu_afull) {
+			break;
+		}
 
-        read_cnt++;
+		read_cnt++;
 
-        if (read_cnt > DPP_RD_CNT_MAX * DPP_RD_CNT_MAX)
-        {
-            ZXIC_COMM_TRACE_ERROR("Error!!! dpp_etcam_cpu_afull_check is overtime!\n");
-            return DPP_ERR;
-        }
+		if (read_cnt > DPP_RD_CNT_MAX * DPP_RD_CNT_MAX) {
+			ZXIC_COMM_TRACE_ERROR(
+					"Error!!! dpp_etcam_cpu_afull_check is overtime!\n");
+			return DPP_ERR;
+		}
 
-        /* zxic_comm_usleep(100); */
-    } 
+		/* zxic_comm_usleep(100); */
+	}
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 添加eTcam表条目
-* @param   dev_id     设备号
-* @param   addr       每个block中的ram地址，位宽为8*80bit
-* @param   block_idx  block编号，范围0~7
-* @param   wr_mask    写表掩码，共8bit，每bit控制ram中对应位置的80bit数据是否有效
-* @param   opr_type   etcam操作类型，详见 DPP_ETCAM_OPR_TYPE_E
-* @param   p_entry    条目数据，data和mask
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/04/03
-************************************************************/
-DPP_STATUS dpp_etcam_entry_add(DPP_DEV_T *dev,
-                               ZXIC_UINT32 addr,
-                               ZXIC_UINT32 block_idx,
-                               ZXIC_UINT32 wr_mask,
-                               ZXIC_UINT32 opr_type,
-                               DPP_ETCAM_ENTRY_T *p_entry)
+ * @param   dev_id     设备号
+ * @param   addr       每个block中的ram地址，位宽为8*80bit
+ * @param   block_idx  block编号，范围0~7
+ * @param   wr_mask    写表掩码，共8bit，每bit控制ram中对应位置的80bit数据是否有效
+ * @param   opr_type   etcam操作类型，详见 DPP_ETCAM_OPR_TYPE_E
+ * @param   p_entry    条目数据，data和mask
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/04/03
+ ************************************************************/
+DPP_STATUS dpp_etcam_entry_add(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+							   ZXIC_UINT32 block_idx, ZXIC_UINT32 wr_mask,
+							   ZXIC_UINT32 opr_type, DPP_ETCAM_ENTRY_T *p_entry)
 {
-    DPP_STATUS rc = DPP_OK;
-    // ZXIC_UINT32 i = 0;
-    // ZXIC_UINT32 tbl_id = 0;
-    // ZXIC_UINT32 handle_row = 0;
-    // ZXIC_UINT32 handle = 0;
-    // ZXIC_UINT32 basea_addr = 0;
-    ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    ZXIC_MUTEX_T *p_etcam_mutex = NULL;
-    DPP_ETCAM_ENTRY_T entry_xy = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), addr, 0, DPP_ETCAM_RAM_DEPTH - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mask, 0, DPP_ETCAM_WR_MASK_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), opr_type, DPP_ETCAM_OPR_DM, DPP_ETCAM_OPR_XY);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry);
-
-    rc = dpp_dev_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_ETCAM, &p_etcam_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_opr_mutex_get");
-
-    rc = zxic_comm_mutex_lock(p_etcam_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_lock");
-
-    /* check cpu fifo is afull */
-    rc = dpp_etcam_cpu_afull_check(dev, block_idx);
-    ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_cpu_afull_check", p_etcam_mutex);
-
-    ZXIC_COMM_ASSERT(p_entry->p_data && p_entry->p_mask);
-
-    entry_xy.p_data = temp_data;
-    entry_xy.p_mask = temp_mask;
-
-    if (opr_type == DPP_ETCAM_OPR_DM)
-    {
-        /* convert user D/M data to X/Y */
-        rc = dpp_etcam_dm_to_xy(p_entry, &entry_xy, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));
-        ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_dm_to_xy", p_etcam_mutex);
-    }
-    else
-    {
-        ZXIC_COMM_MEMCPY(entry_xy.p_data, p_entry->p_data, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));
-        ZXIC_COMM_MEMCPY(entry_xy.p_mask, p_entry->p_mask, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));
-    }
-
-    /* write data X */
-    rc = dpp_etcam_ind_data_set(dev, wr_mask, entry_xy.p_data);
-    ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_data_set", p_etcam_mutex);
-
-    rc = dpp_etcam_ind_cmd_set(dev,
-                               addr,
-                               block_idx,
-                               DPP_ETCAM_DTYPE_DATA,
-                               wr_mask,
-                               DPP_ETCAM_OPR_WR,
-                               0,
-                               0,
-                               1,
-                               0);
-    ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_cmd_set", p_etcam_mutex);
-
-    /* write mask Y */
-    rc = dpp_etcam_ind_data_set(dev, wr_mask, entry_xy.p_mask);
-    ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_data_set", p_etcam_mutex);
-
-    rc = dpp_etcam_ind_cmd_set(dev,
-                               addr,
-                               block_idx,
-                               DPP_ETCAM_DTYPE_MASK,
-                               wr_mask,
-                               DPP_ETCAM_OPR_WR,
-                               0,
-                               0,
-                               1,
-                               0xFF);
-    ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_cmd_set", p_etcam_mutex);
-
-    rc = zxic_comm_mutex_unlock(p_etcam_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	// ZXIC_UINT32 i = 0;
+	// ZXIC_UINT32 tbl_id = 0;
+	// ZXIC_UINT32 handle_row = 0;
+	// ZXIC_UINT32 handle = 0;
+	// ZXIC_UINT32 basea_addr = 0;
+	ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	ZXIC_MUTEX_T *p_etcam_mutex = NULL;
+	DPP_ETCAM_ENTRY_T entry_xy = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), addr, 0, DPP_ETCAM_RAM_DEPTH - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0,
+							  DPP_ETCAM_BLOCK_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mask, 0, DPP_ETCAM_WR_MASK_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), opr_type, DPP_ETCAM_OPR_DM,
+							  DPP_ETCAM_OPR_XY);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry);
+
+	rc = dpp_dev_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_ETCAM,
+							   &p_etcam_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_opr_mutex_get");
+
+	rc = zxic_comm_mutex_lock(p_etcam_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_lock");
+
+	/* check cpu fifo is afull */
+	rc = dpp_etcam_cpu_afull_check(dev, block_idx);
+	ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_cpu_afull_check",
+								  p_etcam_mutex);
+
+	ZXIC_COMM_ASSERT(p_entry->p_data && p_entry->p_mask);
+
+	entry_xy.p_data = temp_data;
+	entry_xy.p_mask = temp_mask;
+
+	if (opr_type == DPP_ETCAM_OPR_DM) {
+		/* convert user D/M data to X/Y */
+		rc = dpp_etcam_dm_to_xy(p_entry, &entry_xy,
+								DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));
+		ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_dm_to_xy",
+									  p_etcam_mutex);
+	} else {
+		ZXIC_COMM_MEMCPY(entry_xy.p_data, p_entry->p_data,
+						 DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));
+		ZXIC_COMM_MEMCPY(entry_xy.p_mask, p_entry->p_mask,
+						 DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));
+	}
+
+	/* write data X */
+	rc = dpp_etcam_ind_data_set(dev, wr_mask, entry_xy.p_data);
+	ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_data_set",
+								  p_etcam_mutex);
+
+	rc = dpp_etcam_ind_cmd_set(dev, addr, block_idx, DPP_ETCAM_DTYPE_DATA,
+							   wr_mask, DPP_ETCAM_OPR_WR, 0, 0, 1, 0);
+	ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_cmd_set",
+								  p_etcam_mutex);
+
+	/* write mask Y */
+	rc = dpp_etcam_ind_data_set(dev, wr_mask, entry_xy.p_mask);
+	ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_data_set",
+								  p_etcam_mutex);
+
+	rc = dpp_etcam_ind_cmd_set(dev, addr, block_idx, DPP_ETCAM_DTYPE_MASK,
+							   wr_mask, DPP_ETCAM_OPR_WR, 0, 0, 1, 0xFF);
+	ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_cmd_set",
+								  p_etcam_mutex);
+
+	rc = zxic_comm_mutex_unlock(p_etcam_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 删除eTcam表项条目
-* @param   dev_id     设备号
-* @param   addr       每个block中的ram地址，位宽为8*80bit
-* @param   block_idx  block的编号，范围0~7
-* @param   wr_mask    写表掩码，共8bit，每bit控制ram中对应位置的80bit数据是否有效
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/04/03
-************************************************************/
-DPP_STATUS dpp_etcam_entry_del(DPP_DEV_T *dev,
-                               ZXIC_UINT32 addr,
-                               ZXIC_UINT32 block_idx,
-                               ZXIC_UINT32 wr_mask)
+ * @param   dev_id     设备号
+ * @param   addr       每个block中的ram地址，位宽为8*80bit
+ * @param   block_idx  block的编号，范围0~7
+ * @param   wr_mask    写表掩码，共8bit，每bit控制ram中对应位置的80bit数据是否有效
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/04/03
+ ************************************************************/
+DPP_STATUS dpp_etcam_entry_del(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+							   ZXIC_UINT32 block_idx, ZXIC_UINT32 wr_mask)
 {
-    DPP_STATUS rc = DPP_OK;
-    // ZXIC_UINT32 i = 0;
-    // ZXIC_UINT32 tbl_id = 0;
-    // ZXIC_UINT32 handle_row = 0;
-    // ZXIC_UINT32 handle = 0;
-    // ZXIC_UINT32 basea_addr = 0;
-
-    ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {0xff,};
-    ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0,};
-    ZXIC_MUTEX_T *p_etcam_mutex = NULL;
-    DPP_ETCAM_ENTRY_T entry_xy = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), addr, 0, DPP_ETCAM_RAM_DEPTH - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mask, 0, DPP_ETCAM_WR_MASK_MAX);
-
-    ZXIC_COMM_MEMSET(temp_data, 0xff, DPP_ETCAM_WIDTH_MAX / 8);
-    ZXIC_COMM_MEMSET(temp_mask, 0, DPP_ETCAM_WIDTH_MAX / 8);
-
-    entry_xy.p_data = temp_data;
-    entry_xy.p_mask = temp_mask;
-
-    rc = dpp_dev_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_ETCAM, &p_etcam_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_opr_mutex_get");
-
-    rc = zxic_comm_mutex_lock(p_etcam_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_lock");
-
-    /* check cpu fifo is afull */
-    rc = dpp_etcam_cpu_afull_check(dev, block_idx);
-    ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_cpu_afull_check", p_etcam_mutex);
-
-    /* write data X */
-    rc = dpp_etcam_ind_data_set(dev, wr_mask, entry_xy.p_data);
-    ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_data_set", p_etcam_mutex);
-
-    rc = dpp_etcam_ind_cmd_set(dev,
-                               addr,
-                               block_idx,
-                               DPP_ETCAM_DTYPE_DATA,
-                               wr_mask,
-                               DPP_ETCAM_OPR_WR,
-                               0,
-                               0,
-                               1,
-                               0xFF);
-    ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_cmd_set", p_etcam_mutex);
-
-    /* write mask Y */
-    rc = dpp_etcam_ind_data_set(dev, wr_mask, entry_xy.p_mask);
-    ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_data_set", p_etcam_mutex);
-
-    rc = dpp_etcam_ind_cmd_set(dev,
-                               addr,
-                               block_idx,
-                               DPP_ETCAM_DTYPE_MASK,
-                               wr_mask,
-                               DPP_ETCAM_OPR_WR,
-                               0,
-                               0,
-                               1,
-                               0xFF);
-    ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_cmd_set", p_etcam_mutex);
-
-    rc = zxic_comm_mutex_unlock(p_etcam_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	// ZXIC_UINT32 i = 0;
+	// ZXIC_UINT32 tbl_id = 0;
+	// ZXIC_UINT32 handle_row = 0;
+	// ZXIC_UINT32 handle = 0;
+	// ZXIC_UINT32 basea_addr = 0;
+
+	ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {
+		0xff,
+	};
+	ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {
+		0,
+	};
+	ZXIC_MUTEX_T *p_etcam_mutex = NULL;
+	DPP_ETCAM_ENTRY_T entry_xy = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), addr, 0, DPP_ETCAM_RAM_DEPTH - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0,
+							  DPP_ETCAM_BLOCK_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mask, 0, DPP_ETCAM_WR_MASK_MAX);
+
+	ZXIC_COMM_MEMSET(temp_data, 0xff, DPP_ETCAM_WIDTH_MAX / 8);
+	ZXIC_COMM_MEMSET(temp_mask, 0, DPP_ETCAM_WIDTH_MAX / 8);
+
+	entry_xy.p_data = temp_data;
+	entry_xy.p_mask = temp_mask;
+
+	rc = dpp_dev_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_ETCAM,
+							   &p_etcam_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_opr_mutex_get");
+
+	rc = zxic_comm_mutex_lock(p_etcam_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_lock");
+
+	/* check cpu fifo is afull */
+	rc = dpp_etcam_cpu_afull_check(dev, block_idx);
+	ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_cpu_afull_check",
+								  p_etcam_mutex);
+
+	/* write data X */
+	rc = dpp_etcam_ind_data_set(dev, wr_mask, entry_xy.p_data);
+	ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_data_set",
+								  p_etcam_mutex);
+
+	rc = dpp_etcam_ind_cmd_set(dev, addr, block_idx, DPP_ETCAM_DTYPE_DATA,
+							   wr_mask, DPP_ETCAM_OPR_WR, 0, 0, 1, 0xFF);
+	ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_cmd_set",
+								  p_etcam_mutex);
+
+	/* write mask Y */
+	rc = dpp_etcam_ind_data_set(dev, wr_mask, entry_xy.p_mask);
+	ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_data_set",
+								  p_etcam_mutex);
+
+	rc = dpp_etcam_ind_cmd_set(dev, addr, block_idx, DPP_ETCAM_DTYPE_MASK,
+							   wr_mask, DPP_ETCAM_OPR_WR, 0, 0, 1, 0xFF);
+	ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_etcam_ind_cmd_set",
+								  p_etcam_mutex);
+
+	rc = zxic_comm_mutex_unlock(p_etcam_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 比较一组data/mask和一组X/Y数据内容是否相异
-* @param   p_entry_dm   待比较的data/mask数据
-* @param   p_entry_xy   待比较的一组X/Y组合数据
-*
-* @return  1-不同，0-相同
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/04/23
-************************************************************/
-ZXIC_UINT32 dpp_etcam_entry_cmp(DPP_ETCAM_ENTRY_T *p_entry_dm, DPP_ETCAM_ENTRY_T *p_entry_xy)
+ * @param   p_entry_dm   待比较的data/mask数据
+ * @param   p_entry_xy   待比较的一组X/Y组合数据
+ *
+ * @return  1-不同，0-相同
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/04/23
+ ************************************************************/
+ZXIC_UINT32 dpp_etcam_entry_cmp(DPP_ETCAM_ENTRY_T *p_entry_dm,
+								DPP_ETCAM_ENTRY_T *p_entry_xy)
 {
-    DPP_STATUS rc = 0;
-    ZXIC_UINT32 data_len = 0;
-    ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    DPP_ETCAM_ENTRY_T entry_xy_temp = {0};
-
-    ZXIC_COMM_CHECK_POINT(p_entry_dm);
-    ZXIC_COMM_CHECK_POINT(p_entry_xy);
-
-    entry_xy_temp.mode = p_entry_dm->mode;
-    entry_xy_temp.p_data = temp_data;
-    entry_xy_temp.p_mask = temp_mask;
-    data_len = DPP_ETCAM_ENTRY_SIZE_GET(entry_xy_temp.mode);
-
-    if(data_len > 80)
-    {
-        return 1;
-    }
-
-    ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_ASSERT(3U, entry_xy_temp.mode);
-    rc = dpp_etcam_dm_to_xy(p_entry_dm, &entry_xy_temp, data_len);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_etcam_dm_to_xy");
-
-    if ((ZXIC_COMM_MEMCMP(entry_xy_temp.p_data, p_entry_xy->p_data, data_len) != 0) ||
-        (ZXIC_COMM_MEMCMP(entry_xy_temp.p_mask, p_entry_xy->p_mask, data_len) != 0))
-    {
-        return 1;
-    }
-
-    return 0;
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 data_len = 0;
+	ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	DPP_ETCAM_ENTRY_T entry_xy_temp = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(p_entry_dm);
+	ZXIC_COMM_CHECK_POINT(p_entry_xy);
+
+	entry_xy_temp.mode = p_entry_dm->mode;
+	entry_xy_temp.p_data = temp_data;
+	entry_xy_temp.p_mask = temp_mask;
+	data_len = DPP_ETCAM_ENTRY_SIZE_GET(entry_xy_temp.mode);
+
+	if (data_len > 80) {
+		return 1;
+	}
+
+	ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_ASSERT(3U, entry_xy_temp.mode);
+	rc = dpp_etcam_dm_to_xy(p_entry_dm, &entry_xy_temp, data_len);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_etcam_dm_to_xy");
+
+	if ((ZXIC_COMM_MEMCMP(entry_xy_temp.p_data, p_entry_xy->p_data, data_len) !=
+		 0) ||
+		(ZXIC_COMM_MEMCMP(entry_xy_temp.p_mask, p_entry_xy->p_mask, data_len) !=
+		 0)) {
+		return 1;
+	}
+
+	return 0;
 }
 
 /***********************************************************/
 /** 配置block的业务号，table_id
-* @param   dev_id       设备号
-* @param   block_idx    block的索引值。范围[0~7]
-* @param   tbl_id       表号，范围[0~7]
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/04/08
-************************************************************/
-DPP_STATUS dpp_etcam_block_tbl_id_set(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 block_idx,
-                                      ZXIC_UINT32 tbl_id)
+ * @param   dev_id       设备号
+ * @param   block_idx    block的索引值。范围[0~7]
+ * @param   tbl_id       表号，范围[0~7]
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/04/08
+ ************************************************************/
+DPP_STATUS dpp_etcam_block_tbl_id_set(DPP_DEV_T *dev, ZXIC_UINT32 block_idx,
+									  ZXIC_UINT32 tbl_id)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 reg_offset = 0;
-    ZXIC_UINT32 bit_offset = 0;
-    ZXIC_UINT32 *p_temp = 0;
-    DPP_STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFG_T block_tbl_id = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), tbl_id, 0, DPP_ETCAM_TBLID_NUM - 1);
-
-    /*reg_offset 表示第几个寄存器进行配置，共四组配置寄存器*/
-    reg_offset = block_idx / TBLID_CFG_SETP;
-    /*bit_offset 一个寄存器可以配置四组port_id,本位表示寄存器内配置的偏移*/
-    bit_offset = block_idx % TBLID_CFG_SETP;
-
-    /*取出当前的配置*/
-    rc = dpp_reg_read(dev,
-                      STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFGr + reg_offset,
-                      0,
-                      0,
-                      &block_tbl_id);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-    /*计算出来配置当前的port_id所处的地址*/
-    p_temp = (ZXIC_UINT32 *)(&block_tbl_id) + 7 - bit_offset;
-
-    *p_temp = tbl_id;
-
-    rc = dpp_reg_write(dev,
-                       STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFGr + reg_offset,
-                       0,
-                       0,
-                       &block_tbl_id);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 reg_offset = 0;
+	ZXIC_UINT32 bit_offset = 0;
+	ZXIC_UINT32 *p_temp = 0;
+	DPP_STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFG_T block_tbl_id = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0,
+							  DPP_ETCAM_BLOCK_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), tbl_id, 0, DPP_ETCAM_TBLID_NUM - 1);
+
+	/*reg_offset 表示第几个寄存器进行配置，共四组配置寄存器*/
+	reg_offset = block_idx / TBLID_CFG_SETP;
+	/*bit_offset 一个寄存器可以配置四组port_id,本位表示寄存器内配置的偏移*/
+	bit_offset = block_idx % TBLID_CFG_SETP;
+
+	/*取出当前的配置*/
+	rc = dpp_reg_read(dev, STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFGr + reg_offset, 0,
+					  0, &block_tbl_id);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+	/*计算出来配置当前的port_id所处的地址*/
+	p_temp = (ZXIC_UINT32 *)(&block_tbl_id) + 7 - bit_offset;
+
+	*p_temp = tbl_id;
+
+	rc = dpp_reg_write(dev, STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFGr + reg_offset, 0,
+					   0, &block_tbl_id);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 获取block的业务号，table_id
-* @param   dev_id
-* @param   block_idx
-* @param   p_tbl_id
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/04/08
-************************************************************/
-DPP_STATUS dpp_etcam_block_tbl_id_get(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 block_idx,
-                                      ZXIC_UINT32 *p_tbl_id)
+ * @param   dev_id
+ * @param   block_idx
+ * @param   p_tbl_id
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/04/08
+ ************************************************************/
+DPP_STATUS dpp_etcam_block_tbl_id_get(DPP_DEV_T *dev, ZXIC_UINT32 block_idx,
+									  ZXIC_UINT32 *p_tbl_id)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 reg_offset = 0;
-    ZXIC_UINT32 bit_offset = 0;
-    ZXIC_UINT32 *p_temp = 0;
-    DPP_STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFG_T block_tbl_id = {0};
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 reg_offset = 0;
+	ZXIC_UINT32 bit_offset = 0;
+	ZXIC_UINT32 *p_temp = 0;
+	DPP_STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFG_T block_tbl_id = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_tbl_id);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0,
+							  DPP_ETCAM_BLOCK_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_tbl_id);
 
-    reg_offset = block_idx / TBLID_CFG_SETP;
-    bit_offset = block_idx % TBLID_CFG_SETP;
+	reg_offset = block_idx / TBLID_CFG_SETP;
+	bit_offset = block_idx % TBLID_CFG_SETP;
 
-    rc = dpp_reg_read(dev,
-                      STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFGr + reg_offset,
-                      0,
-                      0,
-                      &block_tbl_id);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+	rc = dpp_reg_read(dev, STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFGr + reg_offset, 0,
+					  0, &block_tbl_id);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
 
-    p_temp = (ZXIC_UINT32 *)(&block_tbl_id) + TBLID_CFG_SETP - 1 - bit_offset;
+	p_temp = (ZXIC_UINT32 *)(&block_tbl_id) + TBLID_CFG_SETP - 1 - bit_offset;
 
-    *p_tbl_id = *p_temp;
+	*p_tbl_id = *p_temp;
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-
 /***********************************************************/
 /** 配置block的基地址。
-* @param   dev_id      设备号
-* @param   block_idx   block编号
-* @param   base_addr   基地址。
-*          配置规则:每个寄存器寄存器位宽是7bit，逻辑实现为{base_addr[6:0],9'b0},
-*                   80 bit键值模式下，base_addr格式遵循{base_addr[6,3],3'0}
-*                   160bit键值模式下，base_addr格式遵循{1'b0,base_addr[5,2],2'0}
-*                   320bit键值模式下，base_addr格式遵循{2'b0,base_addr[4,1],1'0}
-*                   640bit键值模式下，base_addr格式遵循{3'b0,base_addr[3,0]}
-* @return
-* @remark  无
-* @see     共有8组配置寄存器，每组寄存器支持两组block基地址的配置
-*          其中第0组支持0和1号block基地址配置，第1组支持1和2号block基地址配置 ，依次类推
-* @author  王春雷      @date  2014/04/08
-************************************************************/
-DPP_STATUS dpp_etcam_block_baddr_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 block_idx,
-                                     ZXIC_UINT32 base_addr)
+ * @param   dev_id      设备号
+ * @param   block_idx   block编号
+ * @param   base_addr   基地址。
+ *          配置规则:每个寄存器寄存器位宽是7bit，逻辑实现为{base_addr[6:0],9'b0},
+ *                   80 bit键值模式下，base_addr格式遵循{base_addr[6,3],3'0}
+ *                   160bit键值模式下，base_addr格式遵循{1'b0,base_addr[5,2],2'0}
+ *                   320bit键值模式下，base_addr格式遵循{2'b0,base_addr[4,1],1'0}
+ *                   640bit键值模式下，base_addr格式遵循{3'b0,base_addr[3,0]}
+ * @return
+ * @remark  无
+ * @see     共有8组配置寄存器，每组寄存器支持两组block基地址的配置
+ *          其中第0组支持0和1号block基地址配置，第1组支持1和2号block基地址配置 ，依次类推
+ * @author  王春雷      @date  2014/04/08
+ ************************************************************/
+DPP_STATUS dpp_etcam_block_baddr_set(DPP_DEV_T *dev, ZXIC_UINT32 block_idx,
+									 ZXIC_UINT32 base_addr)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 reg_offset = 0;
-    ZXIC_UINT32 bit_offset = 0;
-    ZXIC_UINT32 *p_temp = 0;
-    DPP_STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFG_T block_baddr = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1);
-
-    reg_offset = block_idx / BADDR_CFG_SETP;
-    bit_offset = block_idx % BADDR_CFG_SETP;
-
-    rc = dpp_reg_read(dev,
-                      STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFGr + reg_offset,
-                      0,
-                      0,
-                      &block_baddr);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    p_temp = (ZXIC_UINT32 *)(&block_baddr) + 3 - bit_offset;
-
-    *p_temp = base_addr;
-
-    rc = dpp_reg_write(dev,
-                       STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFGr + reg_offset,
-                       0,
-                       0,
-                       &block_baddr);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 reg_offset = 0;
+	ZXIC_UINT32 bit_offset = 0;
+	ZXIC_UINT32 *p_temp = 0;
+	DPP_STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFG_T block_baddr = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0,
+							  DPP_ETCAM_BLOCK_NUM - 1);
+
+	reg_offset = block_idx / BADDR_CFG_SETP;
+	bit_offset = block_idx % BADDR_CFG_SETP;
+
+	rc = dpp_reg_read(dev, STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFGr + reg_offset, 0,
+					  0, &block_baddr);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	p_temp = (ZXIC_UINT32 *)(&block_baddr) + 3 - bit_offset;
+
+	*p_temp = base_addr;
+
+	rc = dpp_reg_write(dev, STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFGr + reg_offset,
+					   0, 0, &block_baddr);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 获取block的基地址
-* @param   dev_id
-* @param   block_idx
-* @param   p_base_addr
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/04/08
-************************************************************/
-DPP_STATUS dpp_etcam_block_baddr_get(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 block_idx,
-                                     ZXIC_UINT32 *p_base_addr)
+ * @param   dev_id
+ * @param   block_idx
+ * @param   p_base_addr
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/04/08
+ ************************************************************/
+DPP_STATUS dpp_etcam_block_baddr_get(DPP_DEV_T *dev, ZXIC_UINT32 block_idx,
+									 ZXIC_UINT32 *p_base_addr)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 reg_offset = 0;
-    ZXIC_UINT32 bit_offset = 0;
-    ZXIC_UINT32 *p_temp = 0;
-    DPP_STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFG_T block_baddr = {0};
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 reg_offset = 0;
+	ZXIC_UINT32 bit_offset = 0;
+	ZXIC_UINT32 *p_temp = 0;
+	DPP_STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFG_T block_baddr = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_base_addr);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0,
+							  DPP_ETCAM_BLOCK_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_base_addr);
 
-    reg_offset = block_idx / BADDR_CFG_SETP;
-    bit_offset = block_idx % BADDR_CFG_SETP;
+	reg_offset = block_idx / BADDR_CFG_SETP;
+	bit_offset = block_idx % BADDR_CFG_SETP;
 
-    rc = dpp_reg_read(dev,
-                      STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFGr + reg_offset,
-                      0,
-                      0,
-                      &block_baddr);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+	rc = dpp_reg_read(dev, STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFGr + reg_offset, 0,
+					  0, &block_baddr);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
 
-    p_temp = (ZXIC_UINT32 *)&block_baddr + BADDR_CFG_SETP - 1 - bit_offset;
+	p_temp = (ZXIC_UINT32 *)&block_baddr + BADDR_CFG_SETP - 1 - bit_offset;
 
-    *p_base_addr = *p_temp;
+	*p_base_addr = *p_temp;
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_se.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_se.c
old mode 100755
new mode 100644
index 2dc9dd631a4ea71e1ce4ed022947c98714c190c0..1281576e0bfc03ad012c325eb8313c11698c1418
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_se.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_se.c
@@ -1,1084 +1,985 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_se.c
-* 文件标识 :
-* 内容摘要 : 芯片se模块基本接口函数实现
-* 其它说明 :
-* 当前版本 :
-* 作    者 : 王春雷
-* 完成日期 : 2014/03/11
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-
-#include "zxic_common.h"
-#include "dpp_type_api.h"
-#include "dpp_reg.h"
-#include "dpp_se_api.h"
-#include "dpp_etcam.h"
-#include "dpp_se.h"
-#include "dpp_dev.h"
-#include "dpp_se_cfg.h"
-#include "dpp_sdt.h"
-#include "dpp_smmu14k_reg.h"
-#include "dpp_se4k_reg.h"
-
-#define SE_OPR_WR         (0)
-#define SE_OPR_RD         (1)
-#define SE_CLS_MAX        (8)
-#define SE_SMMU1_PAGE_MAX (5)
-#define SE_LPMID_OFF      (4)
-
-static SMMU1_KSCHD_HASH_DDR_CFG_T g_smmu1_kschd_hash[DPP_DEV_CHANNEL_MAX][DPP_HASH_ID_NUM][HASH_BULK_NUM] = {{{{0}}}};
-
-ZXIC_UINT32 g_lpm_dat_wr_type_flag = 2; /* 1:开启DMA 2:REG mode */
-ZXIC_UINT8 g_lpm_hw_dat_buf[LPM_HW_DAT_BUFF_SIZE_MAX] = {0};
-ZXIC_UINT32 g_lpm_hw_dat_offset = 0;
-
-#define GET_SMMU1_KSCHD_HASH_CFG(dev_id,hash_id,bulk_id) (&g_smmu1_kschd_hash[dev_id][hash_id][bulk_id])
-
-#define SMMU1_WDAT0_R      (SYS_SE_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0)
-#define SMMU1_CMD0_R       (SYS_SE_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x40)
-#define SMMU1_CMD1_R       (SYS_SE_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x44)
-#define SMMU1_CMD0_F_ADDR_START          (30)
-#define SMMU1_CMD0_F_ADDR_WIDTH          (2)
-#define SMMU1_CMD0_F_ECC_EN_START        (5)
-#define SMMU1_CMD0_F_ECC_EN_WIDTH        (1)
-#define SMMU1_CMD0_F_DDR_MODE_START      (3)
-#define SMMU1_CMD0_F_DDR_MODE_WIDTH      (2)
-#define SMMU1_CMD0_F_BK_INFO_START       (0)
-#define SMMU1_CMD0_F_BK_INFO_WIDTH       (3)
-
-#define SMMU1_CMD1_F_DDR_WR_START        (30)
-#define SMMU1_CMD1_F_DDR_WR_WIDTH        (1)
-#define SMMU1_CMD1_F_ADDR_START          (0)
-#define SMMU1_CMD1_F_ADDR_WIDTH          (30)
-
-
-#if ZXIC_REAL("SMMU0")
-/***********************************************************/
-/** SE通用完成状态检查
-* @param   dev_id    设备号
-* @param   reg_no    寄存器编号
-* @param   pos       所要读的寄存器的done_flag的位置(只支持1bit)
-*
-* @return
-* @remark  无
-* @see
-* @author  wyt      @date  2018/07/09
-************************************************************/
-DPP_STATUS dpp_se_done_status_check(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 pos)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 data = 0;
-    ZXIC_UINT32 rd_cnt = 0;
-    ZXIC_UINT32 done_flag = 0;
-
-    /* 打桩使用 */
-#ifdef  DPP_FOR_LLT   
-    ZXIC_UINT32 done_sig = 0xffffffff;
-    
-    rc = dpp_reg_write32(dev_id, reg_no, done_sig);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write32");
-#endif
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
-
-    while (!done_flag)
-    {
-        rc = dpp_reg_read32(dev, reg_no, 0, 0, &data);
-        if(ZXIC_OK != rc)
-        {
-           ZXIC_COMM_TRACE_ERROR("\n [ErrorCode:0x%x] !-- dpp_reg_read32 Fail!\n", rc);
-           return rc;
-        }
-
-        done_flag = (data >> pos) & 0x1;
-
-        if (done_flag)
-        {
-            break;
-        }
-
-        if (rd_cnt > DPP_RD_CNT_MAX * DPP_RD_CNT_MAX)
-        {
-            ZXIC_COMM_TRACE_ERROR("Error!!! dpp se rd reg_no [%d] is overtime!\n", reg_no);
-            return DPP_ERR;
-        }
-
-        rd_cnt++;
-        /*zxic_comm_usleep(1000);*/
-    }
-
-    return rc;
-}
-
-/***********************************************************/
-/** 读eRam
-* @param   dev_id       设备号
-* @param   base_addr    基地址，以128bit为单位
-* @param   index        条目索引,支持128、64、32和1bit的索引值
-* @param   rd_mode      读eRam模式, 取值参照ERAM128_OPR_MODE_E定义，读清模式下不支持1bit模式
-* @param   rd_clr_mode  eRam读清模式, 取值参照ERAM128_RD_CLR_MODE_E定义
-* @param   p_data       返回数据缓存的指针
-*
-* @return
-* @remark  无
-* @see
-* @author  wcl      @date  2015/01/30
-************************************************************/
-DPP_STATUS dpp_se_smmu0_ind_read(DPP_DEV_T *dev,
-                                 ZXIC_UINT32 base_addr,
-                                 ZXIC_UINT32 index,
-                                 ZXIC_UINT32 rd_mode,
-                                 ZXIC_UINT32 rd_clr_mode,
-                                 ZXIC_UINT32 *p_data)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 row_index = 0;
-    ZXIC_UINT32 col_index = 0;
-    ZXIC_UINT32 temp_data[4] = {0};
-    ZXIC_UINT32 *p_temp_data = NULL;
-
-    DPP_SMMU0_SMMU0_CPU_IND_CMD_T cpu_ind_cmd = {0};
-
-    ZXIC_MUTEX_T *p_ind_mutex = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_clr_mode, RD_MODE_HOLD, RD_MODE_CLEAR);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_mode, ERAM128_OPR_128b, ERAM128_OPR_32b);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), base_addr, 0, SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1);
-
-    rc = dpp_dev_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_SMMU0, &p_ind_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_opr_mutex_get");
-
-    rc = zxic_comm_mutex_lock(p_ind_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_lock");
-
-    rc = dpp_se_done_status_check(dev, SMMU0_SMMU0_WR_ARB_CPU_RDYr, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "time_out", p_ind_mutex);
-
-    /**  正常模式读数据，仅能以128bit读出数据，软件提取数据*/
-    if (RD_MODE_HOLD == rd_clr_mode)
-    {
-        cpu_ind_cmd.cpu_ind_rw = SE_OPR_RD;
-        cpu_ind_cmd.cpu_ind_rd_mode = RD_MODE_HOLD;
-        cpu_ind_cmd.cpu_req_mode = ERAM128_OPR_128b;
-
-        /* 先以128bit模式读出数据 */
-        switch (rd_mode)
-        {
-            case ERAM128_OPR_128b:
-            {
-                if((0xFFFFFFFF - (base_addr)) < (index))
-                {
-                   zxic_comm_mutex_unlock(p_ind_mutex);
-                   ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),  "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, base_addr, index, __FUNCTION__);
-                   return ZXIC_PAR_CHK_INVALID_INDEX;
-                }
-                if (base_addr + index > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1)
-                {
-                    ZXIC_COMM_PRINT("dpp_se_smmu0_ind_read : index out of range !\n");
-                    zxic_comm_mutex_unlock(p_ind_mutex);
-                    return DPP_ERR;
-                }
-
-                row_index = (index << 7) & DPP_ERAM128_BADDR_MASK;
-                break;
-            }
-
-            case ERAM128_OPR_64b:
-            {
-                if ((base_addr + (index >> 1)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1)
-                {
-                    ZXIC_COMM_PRINT("dpp_se_smmu0_ind_read : index out of range !\n");
-                    zxic_comm_mutex_unlock(p_ind_mutex);
-                    return DPP_ERR;
-                }
-
-                row_index = (index << 6) & DPP_ERAM128_BADDR_MASK;
-                col_index = index & 0x1;
-                break;
-            }
-
-            case ERAM128_OPR_32b:
-            {
-                if ((base_addr + (index >> 2)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1)
-                {
-                    ZXIC_COMM_PRINT("dpp_se_smmu0_ind_read : index out of range !\n");
-                    zxic_comm_mutex_unlock(p_ind_mutex);
-                    return DPP_ERR;
-                }
-
-                row_index = (index << 5) & DPP_ERAM128_BADDR_MASK;
-                col_index = index & 0x3;
-                break;
-            }
-
-            case ERAM128_OPR_1b:
-            {
-                if ((base_addr + (index >> 7)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1)
-                {
-                    ZXIC_COMM_PRINT("dpp_se_smmu0_ind_read : index out of range !\n");
-                    zxic_comm_mutex_unlock(p_ind_mutex);
-                    return DPP_ERR;
-                }
-
-                row_index = index & DPP_ERAM128_BADDR_MASK;
-                col_index = index & 0x7F;
-                break;
-            }
-        }
-
-        cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & DPP_ERAM128_BADDR_MASK) + row_index;
-    }
-    /** 读清模式*/
-    else
-    {
-        cpu_ind_cmd.cpu_ind_rw = SE_OPR_RD;
-        cpu_ind_cmd.cpu_ind_rd_mode = RD_MODE_CLEAR;
-
-        switch (rd_mode)
-        {
-            case ERAM128_OPR_128b:
-            {
-                if((0xFFFFFFFF - (base_addr)) < (index))
-                {
-                    ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),  "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, base_addr, index, __FUNCTION__);
-                    zxic_comm_mutex_unlock(p_ind_mutex);
-                    return ZXIC_PAR_CHK_INVALID_INDEX;
-                }
-                if (base_addr + index > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1)
-                {
-                    ZXIC_COMM_PRINT("dpp_se_smmu0_ind_read : index out of range !\n");
-                    zxic_comm_mutex_unlock(p_ind_mutex);
-                    return DPP_ERR;
-                }
-
-                row_index = (index << 7);
-                cpu_ind_cmd.cpu_req_mode = ERAM128_OPR_128b;
-                break;
-            }
-
-            case ERAM128_OPR_64b:
-            {
-                if ((base_addr + (index >> 1)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1)
-                {
-                    ZXIC_COMM_PRINT("dpp_se_smmu0_ind_read : index out of range !\n");
-                    zxic_comm_mutex_unlock(p_ind_mutex);
-                    return DPP_ERR;
-                }
-
-                row_index = (index << 6);
-                cpu_ind_cmd.cpu_req_mode = 2;
-                break;
-            }
-
-            case ERAM128_OPR_32b:
-            {
-                if ((base_addr + (index >> 2)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1)
-                {
-                    ZXIC_COMM_PRINT("dpp_se_smmu0_ind_read : index out of range !\n");
-                    zxic_comm_mutex_unlock(p_ind_mutex);
-                    return DPP_ERR;
-                }
-
-                row_index = (index << 5);
-                cpu_ind_cmd.cpu_req_mode = 1;
-                break;
-            }
-
-            /** 1bit读清模式硬件不支持 */
-            case ERAM128_OPR_1b:
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Param Error! rd_clr_mode[%d] or rd_mode[%d] error!\n ", rd_clr_mode, rd_mode);
-                zxic_comm_mutex_unlock(p_ind_mutex);
-                ZXIC_COMM_ASSERT(0);
-                return DPP_ERR;
-            }
-        }
-
-        cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & DPP_ERAM128_BADDR_MASK) + row_index;
-    }
-
-    rc = dpp_reg_write(dev,
-                       SMMU0_SMMU0_CPU_IND_CMDr,
-                       0,
-                       0,
-                       &cpu_ind_cmd);
-    ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_reg_write", p_ind_mutex);
-
-    rc = dpp_se_done_status_check(dev, SMMU0_SMMU0_CPU_IND_RD_DONEr, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "time_out", p_ind_mutex);
-
-    p_temp_data = temp_data;
-    for (i = 0; i < 4; i++)
-    {
-/*
-        rc = dpp_reg_read(dev_id,
-                          SMMU0_SMMU0_CPU_IND_RDAT0r + i,
-                          0,
-                          0,
-                          temp_data + 3 - i);
-        ZXIC_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, "dpp_reg_read", p_ind_mutex);
-*/
-        rc = dpp_reg_read(dev,
-                          SMMU0_SMMU0_CPU_IND_RDAT0r + i,
-                          0,
-                          0,
-                          p_temp_data + 3 - i);
-        ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_reg_read", p_ind_mutex);
-    }
-
-    /**  正常模式读数据，仅能以128bit读出数据，软件提取数据*/
-    if (RD_MODE_HOLD == rd_clr_mode)
-    {
-        switch (rd_mode)
-        {
-            case ERAM128_OPR_128b:
-            {
-                /* ZXIC_COMM_MEMCPY(p_data, &temp_data[0], (128 / 8)); */
-                /* modify by ghm for coverity @20200714 */
-                ZXIC_COMM_MEMCPY(p_data, p_temp_data, (128 / 8));
-                break;
-            }
-
-            case ERAM128_OPR_64b:
-            {
-                /* ZXIC_COMM_MEMCPY(p_data, &temp_data[(1 - col_index) << 1], (64 / 8)); */
-                /* modify by ghm for coverity @20200714 */
-                ZXIC_COMM_MEMCPY(p_data, p_temp_data + ((1 - col_index) << 1), (64 / 8));
-                break;
-            }
-
-            case ERAM128_OPR_32b:
-            {
-                /* ZXIC_COMM_MEMCPY(p_data, &temp_data[(3 - col_index)], (32 / 8)); */
-                /* modify by ghm for coverity @20200714 */
-                ZXIC_COMM_MEMCPY(p_data, p_temp_data + ((3 - col_index)), (32 / 8));
-                break;
-            }
-
-            case ERAM128_OPR_1b:
-            {
-                /* ZXIC_COMM_UINT32_GET_BITS(p_data[0], temp_data[3 - col_index / 32], (col_index % 32), 1); */
-                /* modify by ghm for coverity @20200714 */
-                ZXIC_COMM_UINT32_GET_BITS(p_data[0], *(p_temp_data + (3 - col_index / 32)), (col_index % 32), 1);
-                break;
-            }
-        }
-    }
-    else /** 读清模式*/
-    {
-        switch (rd_mode)
-        {
-            case ERAM128_OPR_128b:
-            {
-                /* ZXIC_COMM_MEMCPY(p_data, temp_data, (128 / 8)); */
-                /* modify by ghm for coverity @20200714 */
-                ZXIC_COMM_MEMCPY(p_data, p_temp_data, (128 / 8));
-                break;
-            }
-
-            case ERAM128_OPR_64b:
-            {
-                /* ZXIC_COMM_MEMCPY(p_data, temp_data, (64 / 8)); */
-                /* modify by ghm for coverity @20200714 */
-                ZXIC_COMM_MEMCPY(p_data, p_temp_data, (64 / 8));
-                break;
-            }
-
-            case ERAM128_OPR_32b:
-            {
-                /* ZXIC_COMM_MEMCPY(p_data, temp_data, (32 / 8)); */
-                /* modify by ghm for coverity @20200714 */
-                ZXIC_COMM_MEMCPY(p_data, p_temp_data, (64 / 8));
-                break;
-            }
-        }
-    }
-
-    rc = zxic_comm_mutex_unlock(p_ind_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
-
-    return rc;
-}
-
-
-
-#endif
-
-#if ZXIC_REAL("SMMU1")
-/***********************************************************/
-/** dpp hash的smmu1属性设置
-* @param   dev_id    设备号
-* @param   hash_id      hash引擎号
-* @param   tbl_id       hash表号
-* @param   ecc_en       ecc使能
-* @param   baddr        ddr基地址
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/12
-************************************************************/
-DPP_STATUS dpp_se_smmu1_hash_tbl_cfg_set(DPP_DEV_T *dev,
-                                         ZXIC_UINT32 hash_id,
-                                         ZXIC_UINT32 tbl_id,
-                                         ZXIC_UINT32 ecc_en,
-                                         ZXIC_UINT32 baddr)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    DPP_SMMU14K_SE_SMMU1_HASH0_TBL0_CFG_T hash_tbl_cfg = {0};
-
-    SMMU1_KSCHD_HASH_DDR_CFG_T *p_hash_ddr_cfg = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(hash_id,DPP_HASH_ID_MAX);
-    ZXIC_COMM_CHECK_INDEX_UPPER(tbl_id,HASH_BULK_ID_MAX);
-    ZXIC_COMM_CHECK_INDEX_UPPER(ecc_en,1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(baddr,DPP_SE_SMMU1_MAX_BADDR_NO_SHARE);
-
-    /* save to soft buffer */
-    p_hash_ddr_cfg = GET_SMMU1_KSCHD_HASH_CFG(DEV_ID(dev), hash_id, tbl_id);
-    p_hash_ddr_cfg->baddr = baddr;
-    p_hash_ddr_cfg->crcen = ecc_en;
-    p_hash_ddr_cfg->mode = SMMU1_DDR_SRH_256b; /* alg search ddr mode, not write mode */
-
-    hash_tbl_cfg.hash0_tbl0_ecc_en = ecc_en;
-    hash_tbl_cfg.hash0_tbl0_baddr = baddr;
-
-#ifdef DPP_FLOW_HW_INIT
-    rc = dpp_reg_write(dev,
-                       SMMU14K_SE_SMMU1_HASH0_TBL0_CFGr + hash_id * HASH_BULK_NUM + tbl_id,
-                       0,
-                       0,
-                       &hash_tbl_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-#endif
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取hash算法访问DDR空间的属性，从软件获取(待优化)
-* @param   dev_id    设备号
-* @param   hash_id      hash引擎号
-* @param   bulk_id      Hash引擎存储资源划分块数的ID号
-* @param   p_ecc_en     使能ECC校验
-* @param   p_base_addr  DDR空间基地址
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  tf      @date  2016/06/15
-************************************************************/
-DPP_STATUS dpp_se_smmu1_hash_tbl_soft_cfg_get(DPP_DEV_T *dev,
-                                              ZXIC_UINT32 hash_id,
-                                              ZXIC_UINT32 bulk_id,
-                                              ZXIC_UINT32 *p_ecc_en,
-                                              ZXIC_UINT32 *p_base_addr)
-{
-
-    SMMU1_KSCHD_HASH_DDR_CFG_T *p_schd_hash = NULL;
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(hash_id,DPP_HASH_ID_MAX);
-    ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id,HASH_BULK_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_base_addr);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ecc_en);
-
-    /* read from soft buffer */
-    p_schd_hash = GET_SMMU1_KSCHD_HASH_CFG(DEV_ID(dev), hash_id, bulk_id);
-    *p_base_addr = p_schd_hash->baddr;
-    *p_ecc_en = p_schd_hash->crcen;
-
-    return DPP_OK;
-}
-
-#endif
-
-#if ZXIC_REAL("ALG")
-/***********************************************************/
-/** 设置zblock service信息
-* @param   dev_id
-* @param   zblk_idx   zblock索引(2bit zgroup + 3bit zblock)
-* @param   serv_sel   0-lpm, 1-hash
-* @param   hash_id    zblock对应的hash_id, lpm不关心此字段
-* @param   enable     业务表使能标志
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/07/26
-************************************************************/
-DPP_STATUS dpp_se_zblk_serv_cfg_set(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 zblk_idx,
-                                    ZXIC_UINT32 serv_sel,
-                                    ZXIC_UINT32 hash_id,
-                                    ZXIC_UINT32 enable)
-{
-    DPP_STATUS rtn = DPP_OK;
-
-    DPP_SE4K_SE_ALG_ZBLOCK_SERVICE_CONFIGURE_T zblk_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-
-    zblk_cfg.hash_channel_sel = hash_id;
-    zblk_cfg.service_sel = serv_sel;
-    zblk_cfg.st_en = enable;
-    rtn = dpp_reg_write(dev,
-                         SE4K_SE_ALG_ZBLOCK_SERVICE_CONFIGUREr,
-                        ((ZBLK_ADDR_CONV(zblk_idx) >> 3) & 0x3),
-                        (ZBLK_ADDR_CONV(zblk_idx) & 0x7),
-                        &zblk_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 设置业务表独占的zcell
-* @param   dev_id
-* @param   zblk_idx           zblock索引(2bit zgroup + 3bit zblock)
-* @param   zcell0_bulk_id      独占zcell0的业务表号
-* @param   zcell0_mono_flag   zcell0被独占的标志
-* @param   zcell1_bulk_id      独占zcell1的业务表号
-* @param   zcell1_mono_flag   zcell1被独占的标志
-* @param   zcell2_bulk_id      独占zcell2的业务表号
-* @param   zcell2_mono_flag   zcell2被独占的标志
-* @param   zcell3_bulk_id      独占zcell3的业务表号
-* @param   zcell3_mono_flag   zcell3被独占的标志
-*
-* @return
-* @remark  无
-* @see
-* @author  tf      @date  2016/04/26
-************************************************************/
-DPP_STATUS dpp_se_zcell_mono_cfg_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 zblk_idx,
-                                     ZXIC_UINT32 zcell0_bulk_id,
-                                     ZXIC_UINT32 zcell0_mono_flag,
-                                     ZXIC_UINT32 zcell1_bulk_id,
-                                     ZXIC_UINT32 zcell1_mono_flag,
-                                     ZXIC_UINT32 zcell2_bulk_id,
-                                     ZXIC_UINT32 zcell2_mono_flag,
-                                     ZXIC_UINT32 zcell3_bulk_id,
-                                     ZXIC_UINT32 zcell3_mono_flag)
-{
-    DPP_STATUS rtn = DPP_OK;
-
-    DPP_SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONO_T zblk_zcell_mono_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-
-    zblk_zcell_mono_cfg.ha_zcell0_tbl_id = zcell0_bulk_id;
-    zblk_zcell_mono_cfg.ha_zcell0_mono_flag = zcell0_mono_flag;
-    zblk_zcell_mono_cfg.ha_zcell1_tbl_id = zcell1_bulk_id;
-    zblk_zcell_mono_cfg.ha_zcell1_mono_flag = zcell1_mono_flag;
-    zblk_zcell_mono_cfg.ha_zcell2_tbl_id = zcell2_bulk_id;
-    zblk_zcell_mono_cfg.ha_zcell2_mono_flag = zcell2_mono_flag;
-    zblk_zcell_mono_cfg.ha_zcell3_tbl_id = zcell3_bulk_id;
-    zblk_zcell_mono_cfg.ha_zcell3_mono_flag = zcell3_mono_flag;
-
-    rtn = dpp_reg_write(dev,
-                        SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONOr,
-                        ((ZBLK_ADDR_CONV(zblk_idx) >> 3) & 0x3),
-                        (ZBLK_ADDR_CONV(zblk_idx) & 0x7),
-                        &zblk_zcell_mono_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取业务表独占的zcell
-* @param   dev_id
-* @param   zblk_idx
-* @param   *zcell0_bulk_id
-* @param   *zcell0_mono_flag
-* @param   *zcell1_bulk_id
-* @param   *zcell1_mono_flag
-* @param   *zcell2_bulk_id
-* @param   *zcell2_mono_flag
-* @param   *zcell3_bulk_id
-* @param   *zcell3_mono_flag
-*
-* @return
-* @remark  无
-* @see
-* @author  tf      @date  2016/04/26
-************************************************************/
-DPP_STATUS dpp_se_zcell_mono_cfg_get(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 zblk_idx,
-                                     ZXIC_UINT32 *zcell0_bulk_id,
-                                     ZXIC_UINT32 *zcell0_mono_flag,
-                                     ZXIC_UINT32 *zcell1_bulk_id,
-                                     ZXIC_UINT32 *zcell1_mono_flag,
-                                     ZXIC_UINT32 *zcell2_bulk_id,
-                                     ZXIC_UINT32 *zcell2_mono_flag,
-                                     ZXIC_UINT32 *zcell3_bulk_id,
-                                     ZXIC_UINT32 *zcell3_mono_flag)
-{
-    DPP_STATUS rtn = DPP_OK;
-
-    DPP_SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONO_T zblk_zcell_mono_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell0_bulk_id);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell0_mono_flag);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell1_bulk_id);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell1_mono_flag);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell2_bulk_id);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell2_mono_flag);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell3_bulk_id);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell3_mono_flag);
-
-    rtn = dpp_reg_read(dev,
-                       SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONOr,
-                       ((ZBLK_ADDR_CONV(zblk_idx) >> 3) & 0x3),
-                       (ZBLK_ADDR_CONV(zblk_idx) & 0x7),
-                       &zblk_zcell_mono_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
-
-    *zcell0_bulk_id = zblk_zcell_mono_cfg.ha_zcell0_tbl_id;
-    *zcell0_mono_flag = zblk_zcell_mono_cfg.ha_zcell0_mono_flag;
-    *zcell1_bulk_id = zblk_zcell_mono_cfg.ha_zcell1_tbl_id;
-    *zcell1_mono_flag = zblk_zcell_mono_cfg.ha_zcell1_mono_flag;
-    *zcell2_bulk_id = zblk_zcell_mono_cfg.ha_zcell2_tbl_id;
-    *zcell2_mono_flag = zblk_zcell_mono_cfg.ha_zcell2_mono_flag;
-    *zcell3_bulk_id = zblk_zcell_mono_cfg.ha_zcell3_tbl_id;
-    *zcell3_mono_flag = zblk_zcell_mono_cfg.ha_zcell3_mono_flag;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 设置业务表独占的zreg
-* @param   dev_id
-* @param   zblk_idx          zblock索引(2bit zgroup + 3bit zblock)
-* @param   zreg0_bulk_id      独占zreg0的业务表号
-* @param   zreg0_mono_flag   zreg0被独占的标志
-* @param   zreg1_bulk_id      独占zreg1的业务表号
-* @param   zreg1_mono_flag   zreg1被独占的标志
-* @param   zreg2_bulk_id      独占zreg2的业务表号
-* @param   zreg2_mono_flag   zreg2被独占的标志
-* @param   zreg3_bulk_id      独占zreg3的业务表号
-* @param   zreg3_mono_flag   zreg3被独占的标志
-*
-* @return
-* @remark  无
-* @see
-* @author  tf      @date  2016/04/27
-************************************************************/
-DPP_STATUS dpp_se_zreg_mono_cfg_set(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 zblk_idx,
-                                    ZXIC_UINT32 zreg0_bulk_id,
-                                    ZXIC_UINT32 zreg0_mono_flag,
-                                    ZXIC_UINT32 zreg1_bulk_id,
-                                    ZXIC_UINT32 zreg1_mono_flag,
-                                    ZXIC_UINT32 zreg2_bulk_id,
-                                    ZXIC_UINT32 zreg2_mono_flag,
-                                    ZXIC_UINT32 zreg3_bulk_id,
-                                    ZXIC_UINT32 zreg3_mono_flag)
-{
-    DPP_STATUS rtn = DPP_OK;
-
-    DPP_SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONO_T zblk_zreg_mono_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-
-    zblk_zreg_mono_cfg.ha_zreg0_tbl_id = zreg0_bulk_id;
-    zblk_zreg_mono_cfg.ha_zreg0_mono_flag = zreg0_mono_flag;
-    zblk_zreg_mono_cfg.ha_zreg1_tbl_id = zreg1_bulk_id;
-    zblk_zreg_mono_cfg.ha_zreg1_mono_flag = zreg1_mono_flag;
-    zblk_zreg_mono_cfg.ha_zreg2_tbl_id = zreg2_bulk_id;
-    zblk_zreg_mono_cfg.ha_zreg2_mono_flag = zreg2_mono_flag;
-    zblk_zreg_mono_cfg.ha_zreg3_tbl_id = zreg3_bulk_id;
-    zblk_zreg_mono_cfg.ha_zreg3_mono_flag = zreg3_mono_flag;
-
-    rtn = dpp_reg_write(dev,
-                        SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONOr,
-                        ((ZBLK_ADDR_CONV(zblk_idx) >> 3) & 0x3),
-                        (ZBLK_ADDR_CONV(zblk_idx) & 0x7),
-                        &zblk_zreg_mono_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取业务表独占的zcell
-* @param   dev_id
-* @param   zblk_idx
-* @param   *zreg0_bulk_id
-* @param   *zreg0_mono_flag
-* @param   *zreg1_bulk_id
-* @param   *zreg1_mono_flag
-* @param   *zreg2_bulk_id
-* @param   *zreg2_mono_flag
-* @param   *zreg3_bulk_id
-* @param   *zreg3_mono_flag
-*
-* @return
-* @remark  无
-* @see
-* @author  tf      @date  2016/04/27
-************************************************************/
-DPP_STATUS dpp_se_zreg_mono_cfg_get(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 zblk_idx,
-                                    ZXIC_UINT32 *zreg0_bulk_id,
-                                    ZXIC_UINT32 *zreg0_mono_flag,
-                                    ZXIC_UINT32 *zreg1_bulk_id,
-                                    ZXIC_UINT32 *zreg1_mono_flag,
-                                    ZXIC_UINT32 *zreg2_bulk_id,
-                                    ZXIC_UINT32 *zreg2_mono_flag,
-                                    ZXIC_UINT32 *zreg3_bulk_id,
-                                    ZXIC_UINT32 *zreg3_mono_flag)
-{
-    DPP_STATUS rtn = DPP_OK;
-
-    DPP_SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONO_T zblk_zreg_mono_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg0_bulk_id);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg0_mono_flag);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg1_bulk_id);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg1_mono_flag);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg2_bulk_id);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg2_mono_flag);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg3_bulk_id);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg3_mono_flag);
-
-    rtn = dpp_reg_read(dev,
-                       SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONOr,
-                       ((ZBLK_ADDR_CONV(zblk_idx) >> 3) & 0x3),
-                       (ZBLK_ADDR_CONV(zblk_idx) & 0x7),
-                       &zblk_zreg_mono_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
-
-    *zreg0_bulk_id = zblk_zreg_mono_cfg.ha_zreg0_tbl_id;
-    *zreg0_mono_flag = zblk_zreg_mono_cfg.ha_zreg0_mono_flag;
-    *zreg1_bulk_id = zblk_zreg_mono_cfg.ha_zreg1_tbl_id;
-    *zreg1_mono_flag = zblk_zreg_mono_cfg.ha_zreg1_mono_flag;
-    *zreg2_bulk_id = zblk_zreg_mono_cfg.ha_zreg2_tbl_id;
-    *zreg2_mono_flag = zblk_zreg_mono_cfg.ha_zreg2_mono_flag;
-    *zreg3_bulk_id = zblk_zreg_mono_cfg.ha_zreg3_tbl_id;
-    *zreg3_mono_flag = zblk_zreg_mono_cfg.ha_zreg3_mono_flag;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 设置hash访问片外DDR的属性
-* @param   dev_id
-* @param   hash0_mono_flag
-* @param   hash1_mono_flag
-* @param   hash2_mono_flag
-* @param   hash3_mono_flag
-*
-* @return
-* @remark  无
-* @see
-* @author  tf      @date  2016/05/7
-************************************************************/
-DPP_STATUS dpp_se_hash_zcam_mono_flags_set(DPP_DEV_T *dev,
-                                           ZXIC_UINT32 hash0_mono_flag,
-                                           ZXIC_UINT32 hash1_mono_flag,
-                                           ZXIC_UINT32 hash2_mono_flag,
-                                           ZXIC_UINT32 hash3_mono_flag)
-{
-    DPP_STATUS rtn = DPP_OK;
-
-    DPP_SE4K_SE_ALG_HASH_MONO_FLAG_T hash_mono_flag = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-
-    hash_mono_flag.hash0_mono_flag = hash0_mono_flag;
-    hash_mono_flag.hash1_mono_flag = hash1_mono_flag;
-    hash_mono_flag.hash2_mono_flag = hash2_mono_flag;
-    hash_mono_flag.hash3_mono_flag = hash3_mono_flag;
-
-    rtn = dpp_reg_write(dev,
-                        SE4K_SE_ALG_HASH_MONO_FLAGr,
-                        0,
-                        0,
-                        &hash_mono_flag);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 设置hash访问片外DDR的属性
-* @param   dev_id
-* @param   hash0_mono_flag
-* @param   hash1_mono_flag
-* @param   hash2_mono_flag
-* @param   hash3_mono_flag
-*
-* @return
-* @remark  无
-* @see
-* @author  tf      @date  2016/05/7
-************************************************************/
-DPP_STATUS dpp_se_hash_zcam_mono_flags_get(DPP_DEV_T *dev,
-                                           ZXIC_UINT32 *hash0_mono_flag,
-                                           ZXIC_UINT32 *hash1_mono_flag,
-                                           ZXIC_UINT32 *hash2_mono_flag,
-                                           ZXIC_UINT32 *hash3_mono_flag)
-{
-    DPP_STATUS rtn = DPP_OK;
-
-    DPP_SE4K_SE_ALG_HASH_MONO_FLAG_T hash_mono_flag = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash0_mono_flag);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash1_mono_flag);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash2_mono_flag);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash3_mono_flag);
-
-    rtn = dpp_reg_read(dev,
-                       SE4K_SE_ALG_HASH_MONO_FLAGr,
-                       0,
-                       0,
-                       &hash_mono_flag);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
-
-    *hash0_mono_flag = hash_mono_flag.hash0_mono_flag;
-    *hash1_mono_flag = hash_mono_flag.hash1_mono_flag;
-    *hash2_mono_flag = hash_mono_flag.hash2_mono_flag;
-    *hash3_mono_flag = hash_mono_flag.hash3_mono_flag;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 设置hash访问片外DDR的属性
-* @param   dev_id
-* @param   hash_id
-* @param   ext_mode
-* @param   flag
-*
-* @return
-* @remark  无
-* @see
-* @author  wcl      @date  2014/07/26
-************************************************************/
-DPP_STATUS dpp_se_hash_ext_cfg_set(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 hash_id,
-                                   ZXIC_UINT32 ext_mode,
-                                   ZXIC_UINT32 flag)
-{
-    DPP_STATUS rtn = DPP_OK;
-
-    DPP_SE4K_SE_ALG_HASH0_EXT_CFG_RGT_T hash_ext_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(hash_id,DPP_HASH_ID_MAX);
-
-    hash_ext_cfg.hash0_ext_flag = flag;
-    hash_ext_cfg.hash0_ext_mode = ext_mode;
-
-    rtn = dpp_reg_write(dev,
-                        SE4K_SE_ALG_HASH0_EXT_CFG_RGTr + hash_id,
-                        0,
-                        0,
-                        &hash_ext_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取hash访问片外DDR的属性
-* @param   dev_id           设备号
-* @param   hash_id          hash引擎，范围0~3
-* @param   p_content_type   每个hash表项读一次ddr3还是两次；1-读512b的宽度，读两次 0-读256宽度，读一次
-* @param   p_flag           片外ddr3是否存储hash表，1-片外存储hash表 0-片外不存储hash表
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/07/26
-************************************************************/
-DPP_STATUS dpp_se_hash_ext_cfg_get(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 hash_id,
-                                   ZXIC_UINT32 *p_content_type,
-                                   ZXIC_UINT32 *p_flag)
-{
-    DPP_STATUS rtn = DPP_OK;
-
-    DPP_SE4K_SE_ALG_HASH0_EXT_CFG_RGT_T hash_ext_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(hash_id,DPP_HASH_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_content_type);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_flag);
-
-    rtn = dpp_reg_read(dev,
-                       SE4K_SE_ALG_HASH0_EXT_CFG_RGTr + hash_id,
-                       0,
-                       0,
-                       &hash_ext_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
-
-    *p_content_type = hash_ext_cfg.hash0_ext_mode;
-    *p_flag = hash_ext_cfg.hash0_ext_flag;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 设置hash业务表深度
-* @param   dev_id
-* @param   hash_id
-* @param   depth_bit
-* @param   content_type
-* @param   flag
-*
-* @return
-* @remark  无
-* @see
-* @author  tf      @date  2016/01/28
-************************************************************/
-DPP_STATUS dpp_se_hash_tbl_depth_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 hash_id,
-                                     ZXIC_UINT32 hash_tbl0_depth,
-                                     ZXIC_UINT32 hash_tbl1_depth,
-                                     ZXIC_UINT32 hash_tbl2_depth,
-                                     ZXIC_UINT32 hash_tbl3_depth,
-                                     ZXIC_UINT32 hash_tbl4_depth,
-                                     ZXIC_UINT32 hash_tbl5_depth,
-                                     ZXIC_UINT32 hash_tbl6_depth,
-                                     ZXIC_UINT32 hash_tbl7_depth)
-
-{
-    DPP_STATUS rtn = DPP_OK;
-
-    DPP_SE4K_SE_ALG_HASH0_TBL30_DEPTH_T hash_tbl30_depth = {0};
-    DPP_SE4K_SE_ALG_HASH0_TBL74_DEPTH_T hash_tbl74_depth = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(hash_id,DPP_HASH_ID_MAX);
-
-    hash_tbl30_depth.hash0_tbl0_depth = hash_tbl0_depth;
-    hash_tbl30_depth.hash0_tbl1_depth = hash_tbl1_depth;
-    hash_tbl30_depth.hash0_tbl2_depth = hash_tbl2_depth;
-    hash_tbl30_depth.hash0_tbl3_depth = hash_tbl3_depth;
-    hash_tbl74_depth.hash0_tbl4_depth = hash_tbl4_depth;
-    hash_tbl74_depth.hash0_tbl5_depth = hash_tbl5_depth;
-    hash_tbl74_depth.hash0_tbl6_depth = hash_tbl6_depth;
-    hash_tbl74_depth.hash0_tbl7_depth = hash_tbl7_depth;
-
-    rtn = dpp_reg_write(dev,
-                        SE4K_SE_ALG_HASH0_TBL30_DEPTHr + 2 * hash_id,
-                        0,
-                        0,
-                        &hash_tbl30_depth);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
-
-    rtn = dpp_reg_write(dev,
-                        SE4K_SE_ALG_HASH0_TBL74_DEPTHr + 2 * hash_id,
-                        0,
-                        0,
-                        &hash_tbl74_depth);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取hash业务表深度
-* @param   dev_id
-* @param   hash_id
-* @param   p_content_type
-* @param   p_flag
-*
-* @return
-* @remark  无
-* @see
-* @author  tf      @date  2016/01/28
-************************************************************/
-DPP_STATUS dpp_se_hash_tbl_depth_get(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 hash_id,
-                                     ZXIC_UINT32 *hash_tbl0_depth,
-                                     ZXIC_UINT32 *hash_tbl1_depth,
-                                     ZXIC_UINT32 *hash_tbl2_depth,
-                                     ZXIC_UINT32 *hash_tbl3_depth,
-                                     ZXIC_UINT32 *hash_tbl4_depth,
-                                     ZXIC_UINT32 *hash_tbl5_depth,
-                                     ZXIC_UINT32 *hash_tbl6_depth,
-                                     ZXIC_UINT32 *hash_tbl7_depth)
-
-{
-    DPP_STATUS rtn = DPP_OK;
-
-    DPP_SE4K_SE_ALG_HASH0_TBL30_DEPTH_T hash_tbl30_depth = {0};
-    DPP_SE4K_SE_ALG_HASH0_TBL74_DEPTH_T hash_tbl74_depth = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(hash_id,DPP_HASH_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl0_depth);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl1_depth);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl2_depth);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl3_depth);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl4_depth);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl5_depth);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl6_depth);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl7_depth);
-
-    rtn = dpp_reg_read(dev,
-                       SE4K_SE_ALG_HASH0_TBL30_DEPTHr + 2 * hash_id,
-                       0,
-                       0,
-                       &hash_tbl30_depth);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
-
-    rtn = dpp_reg_read(dev,
-                       SE4K_SE_ALG_HASH0_TBL74_DEPTHr + 2 * hash_id,
-                       0,
-                       0,
-                       &hash_tbl74_depth);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
-
-    *hash_tbl0_depth = hash_tbl30_depth.hash0_tbl0_depth;
-    *hash_tbl1_depth = hash_tbl30_depth.hash0_tbl1_depth;
-    *hash_tbl2_depth = hash_tbl30_depth.hash0_tbl2_depth;
-    *hash_tbl3_depth = hash_tbl30_depth.hash0_tbl3_depth;
-    *hash_tbl4_depth = hash_tbl74_depth.hash0_tbl4_depth;
-    *hash_tbl5_depth = hash_tbl74_depth.hash0_tbl5_depth;
-    *hash_tbl6_depth = hash_tbl74_depth.hash0_tbl6_depth;
-    *hash_tbl7_depth = hash_tbl74_depth.hash0_tbl7_depth;
-
-    return DPP_OK;
-}
-
-#endif
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_se.c
+* 文件标识 :
+* 内容摘要 : 芯片se模块基本接口函数实现
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2014/03/11
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#include "zxic_common.h"
+#include "dpp_type_api.h"
+#include "dpp_reg.h"
+#include "dpp_se_api.h"
+#include "dpp_etcam.h"
+#include "dpp_se.h"
+#include "dpp_dev.h"
+#include "dpp_se_cfg.h"
+#include "dpp_sdt.h"
+#include "dpp_smmu14k_reg.h"
+#include "dpp_se4k_reg.h"
+
+#define SE_OPR_WR (0)
+#define SE_OPR_RD (1)
+#define SE_CLS_MAX (8)
+#define SE_SMMU1_PAGE_MAX (5)
+#define SE_LPMID_OFF (4)
+
+static SMMU1_KSCHD_HASH_DDR_CFG_T
+		g_smmu1_kschd_hash[DPP_DEV_CHANNEL_MAX][DPP_HASH_ID_NUM]
+						  [HASH_BULK_NUM] = { { { { 0 } } } };
+
+ZXIC_UINT32 g_lpm_dat_wr_type_flag = 2; /* 1:开启DMA 2:REG mode */
+ZXIC_UINT8 g_lpm_hw_dat_buf[LPM_HW_DAT_BUFF_SIZE_MAX] = { 0 };
+ZXIC_UINT32 g_lpm_hw_dat_offset;
+
+#define GET_SMMU1_KSCHD_HASH_CFG(dev_id, hash_id, bulk_id) \
+	(&g_smmu1_kschd_hash[dev_id][hash_id][bulk_id])
+
+#define SMMU1_WDAT0_R (SYS_SE_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0)
+#define SMMU1_CMD0_R (SYS_SE_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x40)
+#define SMMU1_CMD1_R (SYS_SE_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x44)
+#define SMMU1_CMD0_F_ADDR_START (30)
+#define SMMU1_CMD0_F_ADDR_WIDTH (2)
+#define SMMU1_CMD0_F_ECC_EN_START (5)
+#define SMMU1_CMD0_F_ECC_EN_WIDTH (1)
+#define SMMU1_CMD0_F_DDR_MODE_START (3)
+#define SMMU1_CMD0_F_DDR_MODE_WIDTH (2)
+#define SMMU1_CMD0_F_BK_INFO_START (0)
+#define SMMU1_CMD0_F_BK_INFO_WIDTH (3)
+
+#define SMMU1_CMD1_F_DDR_WR_START (30)
+#define SMMU1_CMD1_F_DDR_WR_WIDTH (1)
+#define SMMU1_CMD1_F_ADDR_START (0)
+#define SMMU1_CMD1_F_ADDR_WIDTH (30)
+
+#if ZXIC_REAL("SMMU0")
+/***********************************************************/
+/** SE通用完成状态检查
+ * @param   dev_id    设备号
+ * @param   reg_no    寄存器编号
+ * @param   pos       所要读的寄存器的done_flag的位置(只支持1bit)
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wyt      @date  2018/07/09
+ ************************************************************/
+DPP_STATUS dpp_se_done_status_check(DPP_DEV_T *dev, ZXIC_UINT32 reg_no,
+									ZXIC_UINT32 pos)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 data = 0;
+	ZXIC_UINT32 rd_cnt = 0;
+	ZXIC_UINT32 done_flag = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+
+	while (!done_flag) {
+		rc = dpp_reg_read32(dev, reg_no, 0, 0, &data);
+		if (ZXIC_OK != rc) {
+			ZXIC_COMM_TRACE_ERROR(
+					"\n [ErrorCode:0x%x] !-- dpp_reg_read32 Fail!\n", rc);
+			return rc;
+		}
+
+		done_flag = (data >> pos) & 0x1;
+
+		if (done_flag) {
+			break;
+		}
+
+		if (rd_cnt > DPP_RD_CNT_MAX * DPP_RD_CNT_MAX) {
+			ZXIC_COMM_TRACE_ERROR(
+					"Error!!! dpp se rd reg_no [%d] is overtime!\n", reg_no);
+			return DPP_ERR;
+		}
+
+		rd_cnt++;
+		/*zxic_comm_usleep(1000);*/
+	}
+
+	return rc;
+}
+
+/***********************************************************/
+/** 读eRam
+ * @param   dev_id       设备号
+ * @param   base_addr    基地址，以128bit为单位
+ * @param   index        条目索引,支持128、64、32和1bit的索引值
+ * @param   rd_mode      读eRam模式, 取值参照ERAM128_OPR_MODE_E定义，读清模式下不支持1bit模式
+ * @param   rd_clr_mode  eRam读清模式, 取值参照ERAM128_RD_CLR_MODE_E定义
+ * @param   p_data       返回数据缓存的指针
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/01/30
+ ************************************************************/
+DPP_STATUS dpp_se_smmu0_ind_read(DPP_DEV_T *dev, ZXIC_UINT32 base_addr,
+								 ZXIC_UINT32 index, ZXIC_UINT32 rd_mode,
+								 ZXIC_UINT32 rd_clr_mode, ZXIC_UINT32 *p_data)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 row_index = 0;
+	ZXIC_UINT32 col_index = 0;
+	ZXIC_UINT32 temp_data[4] = { 0 };
+	ZXIC_UINT32 *p_temp_data = NULL;
+
+	DPP_SMMU0_SMMU0_CPU_IND_CMD_T cpu_ind_cmd = { 0 };
+
+	ZXIC_MUTEX_T *p_ind_mutex = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_clr_mode, RD_MODE_HOLD,
+							  RD_MODE_CLEAR);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_mode, ERAM128_OPR_128b,
+							  ERAM128_OPR_32b);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), base_addr, 0,
+							  SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1);
+
+	rc = dpp_dev_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_SMMU0,
+							   &p_ind_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dev_opr_mutex_get");
+
+	rc = zxic_comm_mutex_lock(p_ind_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_lock");
+
+	rc = dpp_se_done_status_check(dev, SMMU0_SMMU0_WR_ARB_CPU_RDYr, 0);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "time_out",
+											p_ind_mutex);
+
+	/**  正常模式读数据，仅能以128bit读出数据，软件提取数据*/
+	if (RD_MODE_HOLD == rd_clr_mode) {
+		cpu_ind_cmd.cpu_ind_rw = SE_OPR_RD;
+		cpu_ind_cmd.cpu_ind_rd_mode = RD_MODE_HOLD;
+		cpu_ind_cmd.cpu_req_mode = ERAM128_OPR_128b;
+
+		/* 先以128bit模式读出数据 */
+		switch (rd_mode) {
+		case ERAM128_OPR_128b: {
+			if ((0xFFFFFFFF - (base_addr)) < (index)) {
+				zxic_comm_mutex_unlock(p_ind_mutex);
+				ZXIC_COMM_TRACE_DEV_ERROR(
+						DEV_ID(dev),
+						"ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n",
+						__FILE__, __LINE__, base_addr, index, __FUNCTION__);
+				return ZXIC_PAR_CHK_INVALID_INDEX;
+			}
+			if (base_addr + index > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
+				ZXIC_COMM_PRINT(
+						"dpp_se_smmu0_ind_read : index out of range !\n");
+				zxic_comm_mutex_unlock(p_ind_mutex);
+				return DPP_ERR;
+			}
+
+			row_index = (index << 7) & DPP_ERAM128_BADDR_MASK;
+			break;
+		}
+
+		case ERAM128_OPR_64b: {
+			if ((base_addr + (index >> 1)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
+				ZXIC_COMM_PRINT(
+						"dpp_se_smmu0_ind_read : index out of range !\n");
+				zxic_comm_mutex_unlock(p_ind_mutex);
+				return DPP_ERR;
+			}
+
+			row_index = (index << 6) & DPP_ERAM128_BADDR_MASK;
+			col_index = index & 0x1;
+			break;
+		}
+
+		case ERAM128_OPR_32b: {
+			if ((base_addr + (index >> 2)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
+				ZXIC_COMM_PRINT(
+						"dpp_se_smmu0_ind_read : index out of range !\n");
+				zxic_comm_mutex_unlock(p_ind_mutex);
+				return DPP_ERR;
+			}
+
+			row_index = (index << 5) & DPP_ERAM128_BADDR_MASK;
+			col_index = index & 0x3;
+			break;
+		}
+
+		case ERAM128_OPR_1b: {
+			if ((base_addr + (index >> 7)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
+				ZXIC_COMM_PRINT(
+						"dpp_se_smmu0_ind_read : index out of range !\n");
+				zxic_comm_mutex_unlock(p_ind_mutex);
+				return DPP_ERR;
+			}
+
+			row_index = index & DPP_ERAM128_BADDR_MASK;
+			col_index = index & 0x7F;
+			break;
+		}
+		}
+
+		cpu_ind_cmd.cpu_ind_addr =
+				((base_addr << 7) & DPP_ERAM128_BADDR_MASK) + row_index;
+	}
+	/** 读清模式*/
+	else {
+		cpu_ind_cmd.cpu_ind_rw = SE_OPR_RD;
+		cpu_ind_cmd.cpu_ind_rd_mode = RD_MODE_CLEAR;
+
+		switch (rd_mode) {
+		case ERAM128_OPR_128b: {
+			if ((0xFFFFFFFF - (base_addr)) < (index)) {
+				ZXIC_COMM_TRACE_DEV_ERROR(
+						DEV_ID(dev),
+						"ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n",
+						__FILE__, __LINE__, base_addr, index, __FUNCTION__);
+				zxic_comm_mutex_unlock(p_ind_mutex);
+				return ZXIC_PAR_CHK_INVALID_INDEX;
+			}
+			if (base_addr + index > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
+				ZXIC_COMM_PRINT(
+						"dpp_se_smmu0_ind_read : index out of range !\n");
+				zxic_comm_mutex_unlock(p_ind_mutex);
+				return DPP_ERR;
+			}
+
+			row_index = (index << 7);
+			cpu_ind_cmd.cpu_req_mode = ERAM128_OPR_128b;
+			break;
+		}
+
+		case ERAM128_OPR_64b: {
+			if ((base_addr + (index >> 1)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
+				ZXIC_COMM_PRINT(
+						"dpp_se_smmu0_ind_read : index out of range !\n");
+				zxic_comm_mutex_unlock(p_ind_mutex);
+				return DPP_ERR;
+			}
+
+			row_index = (index << 6);
+			cpu_ind_cmd.cpu_req_mode = 2;
+			break;
+		}
+
+		case ERAM128_OPR_32b: {
+			if ((base_addr + (index >> 2)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
+				ZXIC_COMM_PRINT(
+						"dpp_se_smmu0_ind_read : index out of range !\n");
+				zxic_comm_mutex_unlock(p_ind_mutex);
+				return DPP_ERR;
+			}
+
+			row_index = (index << 5);
+			cpu_ind_cmd.cpu_req_mode = 1;
+			break;
+		}
+
+		/** 1bit读清模式硬件不支持 */
+		case ERAM128_OPR_1b: {
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					DEV_ID(dev),
+					"Param Error! rd_clr_mode[%d] or rd_mode[%d] error!\n ",
+					rd_clr_mode, rd_mode);
+			zxic_comm_mutex_unlock(p_ind_mutex);
+			ZXIC_COMM_ASSERT(0);
+			return DPP_ERR;
+		}
+		}
+
+		cpu_ind_cmd.cpu_ind_addr =
+				((base_addr << 7) & DPP_ERAM128_BADDR_MASK) + row_index;
+	}
+
+	rc = dpp_reg_write(dev, SMMU0_SMMU0_CPU_IND_CMDr, 0, 0, &cpu_ind_cmd);
+	ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_reg_write",
+								  p_ind_mutex);
+
+	rc = dpp_se_done_status_check(dev, SMMU0_SMMU0_CPU_IND_RD_DONEr, 0);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "time_out",
+											p_ind_mutex);
+
+	p_temp_data = temp_data;
+	for (i = 0; i < 4; i++) {
+		rc = dpp_reg_read(dev, SMMU0_SMMU0_CPU_IND_RDAT0r + i, 0, 0,
+						  p_temp_data + 3 - i);
+		ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rc, "dpp_reg_read",
+									  p_ind_mutex);
+	}
+
+	/**  正常模式读数据，仅能以128bit读出数据，软件提取数据*/
+	if (RD_MODE_HOLD == rd_clr_mode) {
+		switch (rd_mode) {
+		case ERAM128_OPR_128b: {
+			/* ZXIC_COMM_MEMCPY(p_data, &temp_data[0], (128 / 8)); */
+			/* modify by ghm for coverity @20200714 */
+			ZXIC_COMM_MEMCPY(p_data, p_temp_data, (128 / 8));
+			break;
+		}
+
+		case ERAM128_OPR_64b: {
+			/* ZXIC_COMM_MEMCPY(p_data, &temp_data[(1 - col_index) << 1], (64 / 8)); */
+			/* modify by ghm for coverity @20200714 */
+			ZXIC_COMM_MEMCPY(p_data, p_temp_data + ((1 - col_index) << 1),
+							 (64 / 8));
+			break;
+		}
+
+		case ERAM128_OPR_32b: {
+			/* ZXIC_COMM_MEMCPY(p_data, &temp_data[(3 - col_index)], (32 / 8)); */
+			/* modify by ghm for coverity @20200714 */
+			ZXIC_COMM_MEMCPY(p_data, p_temp_data + ((3 - col_index)), (32 / 8));
+			break;
+		}
+
+		case ERAM128_OPR_1b: {
+			/* ZXIC_COMM_UINT32_GET_BITS(p_data[0], temp_data[3 - col_index / 32], (col_index % 32), 1); */
+			/* modify by ghm for coverity @20200714 */
+			ZXIC_COMM_UINT32_GET_BITS(p_data[0],
+									  *(p_temp_data + (3 - col_index / 32)),
+									  (col_index % 32), 1);
+			break;
+		}
+		}
+	} else { /** 读清模式*/
+		switch (rd_mode) {
+		case ERAM128_OPR_128b: {
+			/* ZXIC_COMM_MEMCPY(p_data, temp_data, (128 / 8)); */
+			/* modify by ghm for coverity @20200714 */
+			ZXIC_COMM_MEMCPY(p_data, p_temp_data, (128 / 8));
+			break;
+		}
+
+		case ERAM128_OPR_64b: {
+			/* ZXIC_COMM_MEMCPY(p_data, temp_data, (64 / 8)); */
+			/* modify by ghm for coverity @20200714 */
+			ZXIC_COMM_MEMCPY(p_data, p_temp_data, (64 / 8));
+			break;
+		}
+
+		case ERAM128_OPR_32b: {
+			/* ZXIC_COMM_MEMCPY(p_data, temp_data, (32 / 8)); */
+			/* modify by ghm for coverity @20200714 */
+			ZXIC_COMM_MEMCPY(p_data, p_temp_data, (64 / 8));
+			break;
+		}
+		}
+	}
+
+	rc = zxic_comm_mutex_unlock(p_ind_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+
+	return rc;
+}
+
+#endif
+
+#if ZXIC_REAL("SMMU1")
+/***********************************************************/
+/** dpp hash的smmu1属性设置
+ * @param   dev_id    设备号
+ * @param   hash_id      hash引擎号
+ * @param   tbl_id       hash表号
+ * @param   ecc_en       ecc使能
+ * @param   baddr        ddr基地址
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/12
+ ************************************************************/
+DPP_STATUS dpp_se_smmu1_hash_tbl_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 hash_id,
+										 ZXIC_UINT32 tbl_id, ZXIC_UINT32 ecc_en,
+										 ZXIC_UINT32 baddr)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_SMMU14K_SE_SMMU1_HASH0_TBL0_CFG_T hash_tbl_cfg = { 0 };
+
+	SMMU1_KSCHD_HASH_DDR_CFG_T *p_hash_ddr_cfg = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(hash_id, DPP_HASH_ID_MAX);
+	ZXIC_COMM_CHECK_INDEX_UPPER(tbl_id, HASH_BULK_ID_MAX);
+	ZXIC_COMM_CHECK_INDEX_UPPER(ecc_en, 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(baddr, DPP_SE_SMMU1_MAX_BADDR_NO_SHARE);
+
+	/* save to soft buffer */
+	p_hash_ddr_cfg = GET_SMMU1_KSCHD_HASH_CFG(DEV_ID(dev), hash_id, tbl_id);
+	p_hash_ddr_cfg->baddr = baddr;
+	p_hash_ddr_cfg->crcen = ecc_en;
+	p_hash_ddr_cfg->mode =
+			SMMU1_DDR_SRH_256b; /* alg search ddr mode, not write mode */
+
+	hash_tbl_cfg.hash0_tbl0_ecc_en = ecc_en;
+	hash_tbl_cfg.hash0_tbl0_baddr = baddr;
+
+#ifdef DPP_FLOW_HW_INIT
+	rc = dpp_reg_write(dev,
+					   SMMU14K_SE_SMMU1_HASH0_TBL0_CFGr +
+							   hash_id * HASH_BULK_NUM + tbl_id,
+					   0, 0, &hash_tbl_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+#endif
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取hash算法访问DDR空间的属性，从软件获取(待优化)
+ * @param   dev_id    设备号
+ * @param   hash_id      hash引擎号
+ * @param   bulk_id      Hash引擎存储资源划分块数的ID号
+ * @param   p_ecc_en     使能ECC校验
+ * @param   p_base_addr  DDR空间基地址
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  tf      @date  2016/06/15
+ ************************************************************/
+DPP_STATUS dpp_se_smmu1_hash_tbl_soft_cfg_get(DPP_DEV_T *dev,
+											  ZXIC_UINT32 hash_id,
+											  ZXIC_UINT32 bulk_id,
+											  ZXIC_UINT32 *p_ecc_en,
+											  ZXIC_UINT32 *p_base_addr)
+{
+	SMMU1_KSCHD_HASH_DDR_CFG_T *p_schd_hash = NULL;
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(hash_id, DPP_HASH_ID_MAX);
+	ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id, HASH_BULK_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_base_addr);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ecc_en);
+
+	/* read from soft buffer */
+	p_schd_hash = GET_SMMU1_KSCHD_HASH_CFG(DEV_ID(dev), hash_id, bulk_id);
+	*p_base_addr = p_schd_hash->baddr;
+	*p_ecc_en = p_schd_hash->crcen;
+
+	return DPP_OK;
+}
+
+#endif
+
+#if ZXIC_REAL("ALG")
+/***********************************************************/
+/** 设置zblock service信息
+ * @param   dev_id
+ * @param   zblk_idx   zblock索引(2bit zgroup + 3bit zblock)
+ * @param   serv_sel   0-lpm, 1-hash
+ * @param   hash_id    zblock对应的hash_id, lpm不关心此字段
+ * @param   enable     业务表使能标志
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/07/26
+ ************************************************************/
+DPP_STATUS dpp_se_zblk_serv_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 zblk_idx,
+									ZXIC_UINT32 serv_sel, ZXIC_UINT32 hash_id,
+									ZXIC_UINT32 enable)
+{
+	DPP_STATUS rtn = DPP_OK;
+
+	DPP_SE4K_SE_ALG_ZBLOCK_SERVICE_CONFIGURE_T zblk_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+
+	zblk_cfg.hash_channel_sel = hash_id;
+	zblk_cfg.service_sel = serv_sel;
+	zblk_cfg.st_en = enable;
+	rtn = dpp_reg_write(dev, SE4K_SE_ALG_ZBLOCK_SERVICE_CONFIGUREr,
+						((ZBLK_ADDR_CONV(zblk_idx) >> 3) & 0x3),
+						(ZBLK_ADDR_CONV(zblk_idx) & 0x7), &zblk_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 设置业务表独占的zcell
+ * @param   dev_id
+ * @param   zblk_idx           zblock索引(2bit zgroup + 3bit zblock)
+ * @param   zcell0_bulk_id      独占zcell0的业务表号
+ * @param   zcell0_mono_flag   zcell0被独占的标志
+ * @param   zcell1_bulk_id      独占zcell1的业务表号
+ * @param   zcell1_mono_flag   zcell1被独占的标志
+ * @param   zcell2_bulk_id      独占zcell2的业务表号
+ * @param   zcell2_mono_flag   zcell2被独占的标志
+ * @param   zcell3_bulk_id      独占zcell3的业务表号
+ * @param   zcell3_mono_flag   zcell3被独占的标志
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  tf      @date  2016/04/26
+ ************************************************************/
+DPP_STATUS dpp_se_zcell_mono_cfg_set(
+		DPP_DEV_T *dev, ZXIC_UINT32 zblk_idx, ZXIC_UINT32 zcell0_bulk_id,
+		ZXIC_UINT32 zcell0_mono_flag, ZXIC_UINT32 zcell1_bulk_id,
+		ZXIC_UINT32 zcell1_mono_flag, ZXIC_UINT32 zcell2_bulk_id,
+		ZXIC_UINT32 zcell2_mono_flag, ZXIC_UINT32 zcell3_bulk_id,
+		ZXIC_UINT32 zcell3_mono_flag)
+{
+	DPP_STATUS rtn = DPP_OK;
+
+	DPP_SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONO_T zblk_zcell_mono_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+
+	zblk_zcell_mono_cfg.ha_zcell0_tbl_id = zcell0_bulk_id;
+	zblk_zcell_mono_cfg.ha_zcell0_mono_flag = zcell0_mono_flag;
+	zblk_zcell_mono_cfg.ha_zcell1_tbl_id = zcell1_bulk_id;
+	zblk_zcell_mono_cfg.ha_zcell1_mono_flag = zcell1_mono_flag;
+	zblk_zcell_mono_cfg.ha_zcell2_tbl_id = zcell2_bulk_id;
+	zblk_zcell_mono_cfg.ha_zcell2_mono_flag = zcell2_mono_flag;
+	zblk_zcell_mono_cfg.ha_zcell3_tbl_id = zcell3_bulk_id;
+	zblk_zcell_mono_cfg.ha_zcell3_mono_flag = zcell3_mono_flag;
+
+	rtn = dpp_reg_write(dev, SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONOr,
+						((ZBLK_ADDR_CONV(zblk_idx) >> 3) & 0x3),
+						(ZBLK_ADDR_CONV(zblk_idx) & 0x7), &zblk_zcell_mono_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取业务表独占的zcell
+ * @param   dev_id
+ * @param   zblk_idx
+ * @param   *zcell0_bulk_id
+ * @param   *zcell0_mono_flag
+ * @param   *zcell1_bulk_id
+ * @param   *zcell1_mono_flag
+ * @param   *zcell2_bulk_id
+ * @param   *zcell2_mono_flag
+ * @param   *zcell3_bulk_id
+ * @param   *zcell3_mono_flag
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  tf      @date  2016/04/26
+ ************************************************************/
+DPP_STATUS dpp_se_zcell_mono_cfg_get(
+		DPP_DEV_T *dev, ZXIC_UINT32 zblk_idx, ZXIC_UINT32 *zcell0_bulk_id,
+		ZXIC_UINT32 *zcell0_mono_flag, ZXIC_UINT32 *zcell1_bulk_id,
+		ZXIC_UINT32 *zcell1_mono_flag, ZXIC_UINT32 *zcell2_bulk_id,
+		ZXIC_UINT32 *zcell2_mono_flag, ZXIC_UINT32 *zcell3_bulk_id,
+		ZXIC_UINT32 *zcell3_mono_flag)
+{
+	DPP_STATUS rtn = DPP_OK;
+
+	DPP_SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONO_T zblk_zcell_mono_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell0_bulk_id);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell0_mono_flag);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell1_bulk_id);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell1_mono_flag);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell2_bulk_id);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell2_mono_flag);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell3_bulk_id);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zcell3_mono_flag);
+
+	rtn = dpp_reg_read(dev, SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONOr,
+					   ((ZBLK_ADDR_CONV(zblk_idx) >> 3) & 0x3),
+					   (ZBLK_ADDR_CONV(zblk_idx) & 0x7), &zblk_zcell_mono_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
+
+	*zcell0_bulk_id = zblk_zcell_mono_cfg.ha_zcell0_tbl_id;
+	*zcell0_mono_flag = zblk_zcell_mono_cfg.ha_zcell0_mono_flag;
+	*zcell1_bulk_id = zblk_zcell_mono_cfg.ha_zcell1_tbl_id;
+	*zcell1_mono_flag = zblk_zcell_mono_cfg.ha_zcell1_mono_flag;
+	*zcell2_bulk_id = zblk_zcell_mono_cfg.ha_zcell2_tbl_id;
+	*zcell2_mono_flag = zblk_zcell_mono_cfg.ha_zcell2_mono_flag;
+	*zcell3_bulk_id = zblk_zcell_mono_cfg.ha_zcell3_tbl_id;
+	*zcell3_mono_flag = zblk_zcell_mono_cfg.ha_zcell3_mono_flag;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 设置业务表独占的zreg
+ * @param   dev_id
+ * @param   zblk_idx          zblock索引(2bit zgroup + 3bit zblock)
+ * @param   zreg0_bulk_id      独占zreg0的业务表号
+ * @param   zreg0_mono_flag   zreg0被独占的标志
+ * @param   zreg1_bulk_id      独占zreg1的业务表号
+ * @param   zreg1_mono_flag   zreg1被独占的标志
+ * @param   zreg2_bulk_id      独占zreg2的业务表号
+ * @param   zreg2_mono_flag   zreg2被独占的标志
+ * @param   zreg3_bulk_id      独占zreg3的业务表号
+ * @param   zreg3_mono_flag   zreg3被独占的标志
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  tf      @date  2016/04/27
+ ************************************************************/
+DPP_STATUS
+dpp_se_zreg_mono_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 zblk_idx,
+						 ZXIC_UINT32 zreg0_bulk_id, ZXIC_UINT32 zreg0_mono_flag,
+						 ZXIC_UINT32 zreg1_bulk_id, ZXIC_UINT32 zreg1_mono_flag,
+						 ZXIC_UINT32 zreg2_bulk_id, ZXIC_UINT32 zreg2_mono_flag,
+						 ZXIC_UINT32 zreg3_bulk_id, ZXIC_UINT32 zreg3_mono_flag)
+{
+	DPP_STATUS rtn = DPP_OK;
+
+	DPP_SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONO_T zblk_zreg_mono_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+
+	zblk_zreg_mono_cfg.ha_zreg0_tbl_id = zreg0_bulk_id;
+	zblk_zreg_mono_cfg.ha_zreg0_mono_flag = zreg0_mono_flag;
+	zblk_zreg_mono_cfg.ha_zreg1_tbl_id = zreg1_bulk_id;
+	zblk_zreg_mono_cfg.ha_zreg1_mono_flag = zreg1_mono_flag;
+	zblk_zreg_mono_cfg.ha_zreg2_tbl_id = zreg2_bulk_id;
+	zblk_zreg_mono_cfg.ha_zreg2_mono_flag = zreg2_mono_flag;
+	zblk_zreg_mono_cfg.ha_zreg3_tbl_id = zreg3_bulk_id;
+	zblk_zreg_mono_cfg.ha_zreg3_mono_flag = zreg3_mono_flag;
+
+	rtn = dpp_reg_write(dev, SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONOr,
+						((ZBLK_ADDR_CONV(zblk_idx) >> 3) & 0x3),
+						(ZBLK_ADDR_CONV(zblk_idx) & 0x7), &zblk_zreg_mono_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取业务表独占的zcell
+ * @param   dev_id
+ * @param   zblk_idx
+ * @param   *zreg0_bulk_id
+ * @param   *zreg0_mono_flag
+ * @param   *zreg1_bulk_id
+ * @param   *zreg1_mono_flag
+ * @param   *zreg2_bulk_id
+ * @param   *zreg2_mono_flag
+ * @param   *zreg3_bulk_id
+ * @param   *zreg3_mono_flag
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  tf      @date  2016/04/27
+ ************************************************************/
+DPP_STATUS dpp_se_zreg_mono_cfg_get(
+		DPP_DEV_T *dev, ZXIC_UINT32 zblk_idx, ZXIC_UINT32 *zreg0_bulk_id,
+		ZXIC_UINT32 *zreg0_mono_flag, ZXIC_UINT32 *zreg1_bulk_id,
+		ZXIC_UINT32 *zreg1_mono_flag, ZXIC_UINT32 *zreg2_bulk_id,
+		ZXIC_UINT32 *zreg2_mono_flag, ZXIC_UINT32 *zreg3_bulk_id,
+		ZXIC_UINT32 *zreg3_mono_flag)
+{
+	DPP_STATUS rtn = DPP_OK;
+
+	DPP_SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONO_T zblk_zreg_mono_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg0_bulk_id);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg0_mono_flag);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg1_bulk_id);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg1_mono_flag);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg2_bulk_id);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg2_mono_flag);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg3_bulk_id);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), zreg3_mono_flag);
+
+	rtn = dpp_reg_read(dev, SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONOr,
+					   ((ZBLK_ADDR_CONV(zblk_idx) >> 3) & 0x3),
+					   (ZBLK_ADDR_CONV(zblk_idx) & 0x7), &zblk_zreg_mono_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
+
+	*zreg0_bulk_id = zblk_zreg_mono_cfg.ha_zreg0_tbl_id;
+	*zreg0_mono_flag = zblk_zreg_mono_cfg.ha_zreg0_mono_flag;
+	*zreg1_bulk_id = zblk_zreg_mono_cfg.ha_zreg1_tbl_id;
+	*zreg1_mono_flag = zblk_zreg_mono_cfg.ha_zreg1_mono_flag;
+	*zreg2_bulk_id = zblk_zreg_mono_cfg.ha_zreg2_tbl_id;
+	*zreg2_mono_flag = zblk_zreg_mono_cfg.ha_zreg2_mono_flag;
+	*zreg3_bulk_id = zblk_zreg_mono_cfg.ha_zreg3_tbl_id;
+	*zreg3_mono_flag = zblk_zreg_mono_cfg.ha_zreg3_mono_flag;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 设置hash访问片外DDR的属性
+ * @param   dev_id
+ * @param   hash0_mono_flag
+ * @param   hash1_mono_flag
+ * @param   hash2_mono_flag
+ * @param   hash3_mono_flag
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  tf      @date  2016/05/7
+ ************************************************************/
+DPP_STATUS dpp_se_hash_zcam_mono_flags_set(DPP_DEV_T *dev,
+										   ZXIC_UINT32 hash0_mono_flag,
+										   ZXIC_UINT32 hash1_mono_flag,
+										   ZXIC_UINT32 hash2_mono_flag,
+										   ZXIC_UINT32 hash3_mono_flag)
+{
+	DPP_STATUS rtn = DPP_OK;
+
+	DPP_SE4K_SE_ALG_HASH_MONO_FLAG_T hash_mono_flag = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+
+	hash_mono_flag.hash0_mono_flag = hash0_mono_flag;
+	hash_mono_flag.hash1_mono_flag = hash1_mono_flag;
+	hash_mono_flag.hash2_mono_flag = hash2_mono_flag;
+	hash_mono_flag.hash3_mono_flag = hash3_mono_flag;
+
+	rtn = dpp_reg_write(dev, SE4K_SE_ALG_HASH_MONO_FLAGr, 0, 0,
+						&hash_mono_flag);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 设置hash访问片外DDR的属性
+ * @param   dev_id
+ * @param   hash0_mono_flag
+ * @param   hash1_mono_flag
+ * @param   hash2_mono_flag
+ * @param   hash3_mono_flag
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  tf      @date  2016/05/7
+ ************************************************************/
+DPP_STATUS dpp_se_hash_zcam_mono_flags_get(DPP_DEV_T *dev,
+										   ZXIC_UINT32 *hash0_mono_flag,
+										   ZXIC_UINT32 *hash1_mono_flag,
+										   ZXIC_UINT32 *hash2_mono_flag,
+										   ZXIC_UINT32 *hash3_mono_flag)
+{
+	DPP_STATUS rtn = DPP_OK;
+
+	DPP_SE4K_SE_ALG_HASH_MONO_FLAG_T hash_mono_flag = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash0_mono_flag);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash1_mono_flag);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash2_mono_flag);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash3_mono_flag);
+
+	rtn = dpp_reg_read(dev, SE4K_SE_ALG_HASH_MONO_FLAGr, 0, 0, &hash_mono_flag);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
+
+	*hash0_mono_flag = hash_mono_flag.hash0_mono_flag;
+	*hash1_mono_flag = hash_mono_flag.hash1_mono_flag;
+	*hash2_mono_flag = hash_mono_flag.hash2_mono_flag;
+	*hash3_mono_flag = hash_mono_flag.hash3_mono_flag;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 设置hash访问片外DDR的属性
+ * @param   dev_id
+ * @param   hash_id
+ * @param   ext_mode
+ * @param   flag
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2014/07/26
+ ************************************************************/
+DPP_STATUS dpp_se_hash_ext_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 hash_id,
+								   ZXIC_UINT32 ext_mode, ZXIC_UINT32 flag)
+{
+	DPP_STATUS rtn = DPP_OK;
+
+	DPP_SE4K_SE_ALG_HASH0_EXT_CFG_RGT_T hash_ext_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(hash_id, DPP_HASH_ID_MAX);
+
+	hash_ext_cfg.hash0_ext_flag = flag;
+	hash_ext_cfg.hash0_ext_mode = ext_mode;
+
+	rtn = dpp_reg_write(dev, SE4K_SE_ALG_HASH0_EXT_CFG_RGTr + hash_id, 0, 0,
+						&hash_ext_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取hash访问片外DDR的属性
+ * @param   dev_id           设备号
+ * @param   hash_id          hash引擎，范围0~3
+ * @param   p_content_type   每个hash表项读一次ddr3还是两次；1-读512b的宽度，读两次 0-读256宽度，读一次
+ * @param   p_flag           片外ddr3是否存储hash表，1-片外存储hash表 0-片外不存储hash表
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/07/26
+ ************************************************************/
+DPP_STATUS dpp_se_hash_ext_cfg_get(DPP_DEV_T *dev, ZXIC_UINT32 hash_id,
+								   ZXIC_UINT32 *p_content_type,
+								   ZXIC_UINT32 *p_flag)
+{
+	DPP_STATUS rtn = DPP_OK;
+
+	DPP_SE4K_SE_ALG_HASH0_EXT_CFG_RGT_T hash_ext_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(hash_id, DPP_HASH_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_content_type);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_flag);
+
+	rtn = dpp_reg_read(dev, SE4K_SE_ALG_HASH0_EXT_CFG_RGTr + hash_id, 0, 0,
+					   &hash_ext_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
+
+	*p_content_type = hash_ext_cfg.hash0_ext_mode;
+	*p_flag = hash_ext_cfg.hash0_ext_flag;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 设置hash业务表深度
+ * @param   dev_id
+ * @param   hash_id
+ * @param   depth_bit
+ * @param   content_type
+ * @param   flag
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  tf      @date  2016/01/28
+ ************************************************************/
+DPP_STATUS dpp_se_hash_tbl_depth_set(
+		DPP_DEV_T *dev, ZXIC_UINT32 hash_id, ZXIC_UINT32 hash_tbl0_depth,
+		ZXIC_UINT32 hash_tbl1_depth, ZXIC_UINT32 hash_tbl2_depth,
+		ZXIC_UINT32 hash_tbl3_depth, ZXIC_UINT32 hash_tbl4_depth,
+		ZXIC_UINT32 hash_tbl5_depth, ZXIC_UINT32 hash_tbl6_depth,
+		ZXIC_UINT32 hash_tbl7_depth)
+
+{
+	DPP_STATUS rtn = DPP_OK;
+
+	DPP_SE4K_SE_ALG_HASH0_TBL30_DEPTH_T hash_tbl30_depth = { 0 };
+	DPP_SE4K_SE_ALG_HASH0_TBL74_DEPTH_T hash_tbl74_depth = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(hash_id, DPP_HASH_ID_MAX);
+
+	hash_tbl30_depth.hash0_tbl0_depth = hash_tbl0_depth;
+	hash_tbl30_depth.hash0_tbl1_depth = hash_tbl1_depth;
+	hash_tbl30_depth.hash0_tbl2_depth = hash_tbl2_depth;
+	hash_tbl30_depth.hash0_tbl3_depth = hash_tbl3_depth;
+	hash_tbl74_depth.hash0_tbl4_depth = hash_tbl4_depth;
+	hash_tbl74_depth.hash0_tbl5_depth = hash_tbl5_depth;
+	hash_tbl74_depth.hash0_tbl6_depth = hash_tbl6_depth;
+	hash_tbl74_depth.hash0_tbl7_depth = hash_tbl7_depth;
+
+	rtn = dpp_reg_write(dev, SE4K_SE_ALG_HASH0_TBL30_DEPTHr + 2 * hash_id, 0, 0,
+						&hash_tbl30_depth);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
+
+	rtn = dpp_reg_write(dev, SE4K_SE_ALG_HASH0_TBL74_DEPTHr + 2 * hash_id, 0, 0,
+						&hash_tbl74_depth);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取hash业务表深度
+ * @param   dev_id
+ * @param   hash_id
+ * @param   p_content_type
+ * @param   p_flag
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  tf      @date  2016/01/28
+ ************************************************************/
+DPP_STATUS dpp_se_hash_tbl_depth_get(
+		DPP_DEV_T *dev, ZXIC_UINT32 hash_id, ZXIC_UINT32 *hash_tbl0_depth,
+		ZXIC_UINT32 *hash_tbl1_depth, ZXIC_UINT32 *hash_tbl2_depth,
+		ZXIC_UINT32 *hash_tbl3_depth, ZXIC_UINT32 *hash_tbl4_depth,
+		ZXIC_UINT32 *hash_tbl5_depth, ZXIC_UINT32 *hash_tbl6_depth,
+		ZXIC_UINT32 *hash_tbl7_depth)
+
+{
+	DPP_STATUS rtn = DPP_OK;
+
+	DPP_SE4K_SE_ALG_HASH0_TBL30_DEPTH_T hash_tbl30_depth = { 0 };
+	DPP_SE4K_SE_ALG_HASH0_TBL74_DEPTH_T hash_tbl74_depth = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(hash_id, DPP_HASH_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl0_depth);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl1_depth);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl2_depth);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl3_depth);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl4_depth);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl5_depth);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl6_depth);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_tbl7_depth);
+
+	rtn = dpp_reg_read(dev, SE4K_SE_ALG_HASH0_TBL30_DEPTHr + 2 * hash_id, 0, 0,
+					   &hash_tbl30_depth);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
+
+	rtn = dpp_reg_read(dev, SE4K_SE_ALG_HASH0_TBL74_DEPTHr + 2 * hash_id, 0, 0,
+					   &hash_tbl74_depth);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_reg_read");
+
+	*hash_tbl0_depth = hash_tbl30_depth.hash0_tbl0_depth;
+	*hash_tbl1_depth = hash_tbl30_depth.hash0_tbl1_depth;
+	*hash_tbl2_depth = hash_tbl30_depth.hash0_tbl2_depth;
+	*hash_tbl3_depth = hash_tbl30_depth.hash0_tbl3_depth;
+	*hash_tbl4_depth = hash_tbl74_depth.hash0_tbl4_depth;
+	*hash_tbl5_depth = hash_tbl74_depth.hash0_tbl5_depth;
+	*hash_tbl6_depth = hash_tbl74_depth.hash0_tbl6_depth;
+	*hash_tbl7_depth = hash_tbl74_depth.hash0_tbl7_depth;
+
+	return DPP_OK;
+}
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_stat_car.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_stat_car.c
old mode 100755
new mode 100644
index 93ac7d60b988899183119195217c6c42541cb0c2..55954101766650fdecbde10b77b2c4ec29d586d8
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_stat_car.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_stat_car.c
@@ -1,4545 +1,2929 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_stat_car.c
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : XXX
-* 完成日期 : 2017/02/09
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-
-#include "zxic_common.h"
-#include "dpp_type_api.h"
-#include "dpp_reg.h"
-// #include "dpp_devmng_api.h"
-#include "dpp_stat_car.h"
-#include "dpp_stat_api.h"
-
-#if ZXIC_REAL("Global Variable")
-
-
-/** 软复位相关 */
-static DPP_CAR_SOFT_RESET_DATA_T g_car_store_data[DPP_DEV_CHANNEL_MAX] = {{{0}}};
-
-#define GET_DPP_CAR_SOFT_RESET_INFO(dev_id) (&g_car_store_data[dev_id])
-
-#define DPP_CAR1_REG_OFFSET (0)
-
-#endif
-
-#if 0
-/***********************************************************/
-/** car 模块初始化
-* @param   dev_id       设备号
-* @param   p_car_cfg    CAR配置信息
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/05/05
-************************************************************/
-DPP_STATUS dpp_stat_car_init(ZXIC_UINT32 dev_id, DPP_CAR_CFG_T *p_car_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 car_type = 0;
-    ZXIC_UINT32 car_mono_mode = 0;
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_cfg);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, p_car_cfg->car0_mono_mode[dev_id], CAR_SMMU0_MONO_MODE_NONE, CAR_SMMU0_MONO_MODE_MAX - 1);
-    /* 已经初始化完成，待后添加重新初始化的代码 */
-    if (p_car_cfg->is_init[dev_id])
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error! CAR cfg has been initialized!\n");
-    }
- 
-    car_mono_mode = p_car_cfg->car0_mono_mode[dev_id];
-
-    for (car_type = STAT_CAR_A_TYPE; car_type < STAT_CAR_MAX_TYPE; car_type++)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_stat_car_hardware_init(car_type[%d]) begin\n", car_type);
-        rc = dpp_stat_car_hardware_init(dev_id,
-                                        car_type,
-                                        car_mono_mode);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_car_hardware_init");
-    }
-
-    p_car_cfg->is_init[dev_id] = 1;
-
-    /* 软复位相关 */
-    ZXIC_COMM_MEMSET(&g_car_store_data[dev_id], 0, sizeof(DPP_CAR_SOFT_RESET_DATA_T));
-    g_car_store_data[dev_id].is_init = 1;
-
-    return rc;
-}
-#endif
-#if ZXIC_REAL("Basic Reg Operation ")
-/***********************************************************/
-/** car A的流设置
-* @param   dev_id           设备号           car编号
-* @param   flow_id          流号
-* @param   drop_flag        丢弃标志
-* @param   plcr_en          监管使能
-* @param   profile_id       监管模板号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_cara_queue_cfg_set(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 flow_id,
-                                       ZXIC_UINT32 drop_flag,
-                                       ZXIC_UINT32 plcr_en,
-                                       ZXIC_UINT32 profile_id)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    DPP_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T queue_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), drop_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), plcr_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX);
-
-    queue_cfg.cara_drop = drop_flag;
-    queue_cfg.cara_plcr_en = plcr_en;
-    queue_cfg.cara_profile_id = profile_id;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_CARA_QUEUE_RAM0_159_0r ,
-                       0,
-                       flow_id,
-                       &queue_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取car A的流设置
-* @param   dev_id               设备号
-* @param   flow_id              流号
-* @param   p_cara_queue_cfg     car A流配置信息
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_cara_queue_cfg_get(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 flow_id,
-                                       DPP_STAT_CAR_A_QUEUE_CFG_T *p_cara_queue_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    DPP_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T  queue_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_queue_cfg);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_CARA_QUEUE_RAM0_159_0r ,
-                      0,
-                      flow_id,
-                      &queue_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    p_cara_queue_cfg->flow_id       = flow_id;
-    p_cara_queue_cfg->drop_flag     = queue_cfg.cara_drop;
-    p_cara_queue_cfg->plcr_en       = queue_cfg.cara_plcr_en;
-    p_cara_queue_cfg->profile_id    = queue_cfg.cara_profile_id;
-
-    p_cara_queue_cfg->tq = ZXIC_COMM_COUNTER64_BUILD(queue_cfg.cara_tq_h, queue_cfg.cara_tq_l);
-
-    p_cara_queue_cfg->ted = queue_cfg.cara_ted;
-    p_cara_queue_cfg->tcd = queue_cfg.cara_tcd;
-    p_cara_queue_cfg->tei = queue_cfg.cara_tei;
-    p_cara_queue_cfg->tci = queue_cfg.cara_tci;
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取car A 包长监管流配置
-* @param   dev_id               设备号
-* @param   flow_id              流号
-* @param   p_cara_queue_cfg     car A流配置信息
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_cara_pkt_queue_cfg_get(DPP_DEV_T *dev,
-                                           ZXIC_UINT32 flow_id,
-                                           DPP_STAT_CAR_A_PKT_QUEUE_CFG_T *p_cara_queue_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    DPP_STAT_CAR0_CARA_QUEUE_RAM0_159_0_PKT_T  queue_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_queue_cfg);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_CARA_QUEUE_RAM0_159_0_PKTr ,
-                      0,
-                      flow_id,
-                      &queue_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    p_cara_queue_cfg->flow_id = flow_id;
-    p_cara_queue_cfg->plcr_en = queue_cfg.cara_plcr_en;
-    p_cara_queue_cfg->profile_id = queue_cfg.cara_profile_id;
-
-    p_cara_queue_cfg->tq = ZXIC_COMM_COUNTER64_BUILD(queue_cfg.cara_tq_h, queue_cfg.cara_tq_l);
-
-    p_cara_queue_cfg->dc = ZXIC_COMM_COUNTER64_BUILD(queue_cfg.cara_dc_high, queue_cfg.cara_dc_low);
-    p_cara_queue_cfg->tc = queue_cfg.cara_tc;
-
-    return rc;
-}
-
-
-/***********************************************************/
-/** car A 字节限速监管模板设定
-* @param   dev_id               设备号
-* @param   profile_id           监管模板号
-* @param   p_cara_profile_cfg   监管模板配置
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_cara_profile_cfg_set(DPP_DEV_T *dev,
-                                         ZXIC_UINT32 profile_id,
-                                         DPP_STAT_CAR_PROFILE_CFG_T *p_cara_profile_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-
-    DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_T profile_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_profile_cfg);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->pkt_sign, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cf, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cm, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cd, CAR_CD_MODE_SRTCM, CAR_CD_MODE_INVALID - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cir, 0, DPP_CAR_MAX_CIR_VALUE);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->eir, 0, DPP_CAR_MAX_EIR_VALUE);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cbs, 0, DPP_CAR_MAX_CBS_VALUE);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->ebs, 0, DPP_CAR_MAX_EBS_VALUE);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->random_disc_e, 0, 0xffffffff);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->random_disc_c, 0, 0xffffffff);
-
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->e_yellow_pri[0], 0, DPP_CAR_MAX_PRI_VALUE);
-
-    for (i = 1; i < DPP_CAR_PRI_MAX; i++)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->c_pri[i],        0, DPP_CAR_MAX_PRI_VALUE);
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->e_green_pri[i],  0, DPP_CAR_MAX_PRI_VALUE);
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->e_yellow_pri[i], 0, DPP_CAR_MAX_PRI_VALUE);
-    }
-    ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "==> dpp_stat_cara_profile_cfg_set profile_id[%d]: \n",  profile_id);
-    ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| -------------------------------------------------------------- | \n");
-    ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| %-5s | %-5s | %-5s | %-10s | %-10s | %-10s | %-10s | \n", "cd", "cf", "cm", "cir", "cbs", "eir", "ebs");
-    ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| %-5d | %-5d | %-5d | %-10d | %-10d | %-10d | %-10d | \n", p_cara_profile_cfg->cd,
-                                                                                                   p_cara_profile_cfg->cf,
-                                                                                                   p_cara_profile_cfg->cm,
-                                                                                                   p_cara_profile_cfg->cir,
-                                                                                                   p_cara_profile_cfg->cbs,
-                                                                                                   p_cara_profile_cfg->eir,
-                                                                                                   p_cara_profile_cfg->ebs);
-    ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| ----- | ----- | ----- | ---------- | ---------- | ---------- | ---------- | \n");
-
-    profile_cfg.cara_e_y_pri7 = p_cara_profile_cfg->e_yellow_pri[7];
-    profile_cfg.cara_e_y_pri6 = p_cara_profile_cfg->e_yellow_pri[6];
-    profile_cfg.cara_e_y_pri5 = p_cara_profile_cfg->e_yellow_pri[5];
-    profile_cfg.cara_e_y_pri4 = p_cara_profile_cfg->e_yellow_pri[4];
-    profile_cfg.cara_e_y_pri3 = p_cara_profile_cfg->e_yellow_pri[3];
-    profile_cfg.cara_e_y_pri2 = p_cara_profile_cfg->e_yellow_pri[2];
-    profile_cfg.cara_e_y_pri1 = p_cara_profile_cfg->e_yellow_pri[1];
-    profile_cfg.cara_e_y_pri0 = p_cara_profile_cfg->e_yellow_pri[0];
-
-    profile_cfg.cara_e_g_pri7 = p_cara_profile_cfg->e_green_pri[7];
-    profile_cfg.cara_e_g_pri6 = p_cara_profile_cfg->e_green_pri[6];
-    profile_cfg.cara_e_g_pri5 = p_cara_profile_cfg->e_green_pri[5];
-    profile_cfg.cara_e_g_pri4 = p_cara_profile_cfg->e_green_pri[4];
-    profile_cfg.cara_e_g_pri3 = p_cara_profile_cfg->e_green_pri[3];
-    profile_cfg.cara_e_g_pri2 = p_cara_profile_cfg->e_green_pri[2];
-    profile_cfg.cara_e_g_pri1 = p_cara_profile_cfg->e_green_pri[1];
-
-    profile_cfg.cara_c_pri7 = p_cara_profile_cfg->c_pri[7];
-    profile_cfg.cara_c_pri6 = p_cara_profile_cfg->c_pri[6];
-    profile_cfg.cara_c_pri5 = p_cara_profile_cfg->c_pri[5];
-    profile_cfg.cara_c_pri4 = p_cara_profile_cfg->c_pri[4];
-    profile_cfg.cara_c_pri3 = p_cara_profile_cfg->c_pri[3];
-    profile_cfg.cara_c_pri2 = p_cara_profile_cfg->c_pri[2];
-    profile_cfg.cara_c_pri1 = p_cara_profile_cfg->c_pri[1];
-
-    profile_cfg.cara_cbs = p_cara_profile_cfg->cbs;
-    profile_cfg.cara_ebs_pbs = p_cara_profile_cfg->ebs;
-    profile_cfg.cara_cir = p_cara_profile_cfg->cir;
-    profile_cfg.cara_eir = p_cara_profile_cfg->eir;
-
-    profile_cfg.cara_cd = p_cara_profile_cfg->cd;
-    profile_cfg.cara_cf = p_cara_profile_cfg->cf;
-    profile_cfg.cara_cm = p_cara_profile_cfg->cm;
-    profile_cfg.cara_pkt_sign = p_cara_profile_cfg->pkt_sign;
-
-    profile_cfg.cara_profile_wr = 0;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_CARA_PROFILE_RAM1_255_0r ,
-                       0,
-                       profile_id,
-                       &profile_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-
-/***********************************************************/
-/** 获取car A包的监管模板配置
-* @param   dev_id               设备号
-* @param   profile_id           监管模板号
-* @param   p_cara_profile_cfg   监管模板配置
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_cara_profile_cfg_get(DPP_DEV_T *dev,
-                                         ZXIC_UINT32 profile_id,
-                                         DPP_STAT_CAR_PROFILE_CFG_T *p_cara_profile_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_T profile_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_profile_cfg);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_CARA_PROFILE_RAM1_255_0r,
-                      0,
-                      profile_id,
-                      &profile_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    p_cara_profile_cfg->profile_id = profile_id;
-    p_cara_profile_cfg->pkt_sign = profile_cfg.cara_pkt_sign;
-    p_cara_profile_cfg->cd = profile_cfg.cara_cd;
-    p_cara_profile_cfg->cf = profile_cfg.cara_cf;
-    p_cara_profile_cfg->cm = profile_cfg.cara_cm;
-    p_cara_profile_cfg->eir = profile_cfg.cara_eir;
-    p_cara_profile_cfg->cir = profile_cfg.cara_cir;
-    p_cara_profile_cfg->ebs = profile_cfg.cara_ebs_pbs;
-    p_cara_profile_cfg->cbs = profile_cfg.cara_cbs;
-
-    p_cara_profile_cfg->c_pri[1] = profile_cfg.cara_c_pri1;
-    p_cara_profile_cfg->c_pri[2] = profile_cfg.cara_c_pri2;
-    p_cara_profile_cfg->c_pri[3] = profile_cfg.cara_c_pri3;
-    p_cara_profile_cfg->c_pri[4] = profile_cfg.cara_c_pri4;
-    p_cara_profile_cfg->c_pri[5] = profile_cfg.cara_c_pri5;
-    p_cara_profile_cfg->c_pri[6] = profile_cfg.cara_c_pri6;
-    p_cara_profile_cfg->c_pri[7] = profile_cfg.cara_c_pri7;
-
-    p_cara_profile_cfg->e_green_pri[1] = profile_cfg.cara_e_g_pri1;
-    p_cara_profile_cfg->e_green_pri[2] = profile_cfg.cara_e_g_pri2;
-    p_cara_profile_cfg->e_green_pri[3] = profile_cfg.cara_e_g_pri3;
-    p_cara_profile_cfg->e_green_pri[4] = profile_cfg.cara_e_g_pri4;
-    p_cara_profile_cfg->e_green_pri[5] = profile_cfg.cara_e_g_pri5;
-    p_cara_profile_cfg->e_green_pri[6] = profile_cfg.cara_e_g_pri6;
-    p_cara_profile_cfg->e_green_pri[7] = profile_cfg.cara_e_g_pri7;
-
-    p_cara_profile_cfg->e_yellow_pri[0] = profile_cfg.cara_e_y_pri0;
-    p_cara_profile_cfg->e_yellow_pri[1] = profile_cfg.cara_e_y_pri1;
-    p_cara_profile_cfg->e_yellow_pri[2] = profile_cfg.cara_e_y_pri2;
-    p_cara_profile_cfg->e_yellow_pri[3] = profile_cfg.cara_e_y_pri3;
-    p_cara_profile_cfg->e_yellow_pri[4] = profile_cfg.cara_e_y_pri4;
-    p_cara_profile_cfg->e_yellow_pri[5] = profile_cfg.cara_e_y_pri5;
-    p_cara_profile_cfg->e_yellow_pri[6] = profile_cfg.cara_e_y_pri6;
-    p_cara_profile_cfg->e_yellow_pri[7] = profile_cfg.cara_e_y_pri7;
-
-    return rc;
-}
-
-
-/***********************************************************/
-/** car A包限速监管模板设定
-* @param   dev_id               设备号
-* @param   profile_id           监管模板号
-* @param   p_cara_profile_cfg   监管模板配置
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_cara_pkt_profile_cfg_set(DPP_DEV_T *dev,
-                                             ZXIC_UINT32 profile_id,
-                                             DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_cara_profile_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-
-    DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKT_T profile_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_profile_cfg);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->pkt_sign, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cir, 0, DPP_CAR_MAX_CIR_VALUE);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cbs, 0, DPP_CAR_MAX_CBS_VALUE);
-
-    for (i = 0; i < DPP_CAR_PRI_MAX; i++)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->pri[i], 0, DPP_CAR_MAX_PRI_VALUE);
-    }
-
-    profile_cfg.cara_pri7 = p_cara_profile_cfg->pri[7];
-    profile_cfg.cara_pri6 = p_cara_profile_cfg->pri[6];
-    profile_cfg.cara_pri5 = p_cara_profile_cfg->pri[5];
-    profile_cfg.cara_pri4 = p_cara_profile_cfg->pri[4];
-    profile_cfg.cara_pri3 = p_cara_profile_cfg->pri[3];
-    profile_cfg.cara_pri2 = p_cara_profile_cfg->pri[2];
-    profile_cfg.cara_pri1 = p_cara_profile_cfg->pri[1];
-    profile_cfg.cara_pri0 = p_cara_profile_cfg->pri[0];
-
-    profile_cfg.cara_pkt_cbs = p_cara_profile_cfg->cbs;
-    profile_cfg.cara_pkt_cir = p_cara_profile_cfg->cir;
-    profile_cfg.cara_pkt_sign = p_cara_profile_cfg->pkt_sign;
-
-    profile_cfg.cara_profile_wr = 0;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKTr,
-                       0,
-                       profile_id,
-                       &profile_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-
-/***********************************************************/
-/** 获取car A包长监管模板配置
-* @param   dev_id               设备号
-* @param   profile_id           监管模板号
-* @param   p_cara_profile_cfg   监管模板配置
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_cara_pkt_profile_cfg_get(DPP_DEV_T *dev,
-                                             ZXIC_UINT32 profile_id,
-                                             DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_cara_profile_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKT_T profile_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_profile_cfg);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKTr ,
-                      0,
-                      profile_id,
-                      &profile_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    p_cara_profile_cfg->profile_id = profile_id;
-    p_cara_profile_cfg->pkt_sign = profile_cfg.cara_pkt_sign;
-    p_cara_profile_cfg->cir = profile_cfg.cara_pkt_cir;
-    p_cara_profile_cfg->cbs = profile_cfg.cara_pkt_cbs;
-
-    p_cara_profile_cfg->pri[0] = profile_cfg.cara_pri0;
-    p_cara_profile_cfg->pri[1] = profile_cfg.cara_pri1;
-    p_cara_profile_cfg->pri[2] = profile_cfg.cara_pri2;
-    p_cara_profile_cfg->pri[3] = profile_cfg.cara_pri3;
-    p_cara_profile_cfg->pri[4] = profile_cfg.cara_pri4;
-    p_cara_profile_cfg->pri[5] = profile_cfg.cara_pri5;
-    p_cara_profile_cfg->pri[6] = profile_cfg.cara_pri6;
-    p_cara_profile_cfg->pri[7] = profile_cfg.cara_pri7;
-
-    return rc;
-}
-
-/***********************************************************/
-/** 配置car A的qvos溢出模式
-* @param   dev_id           设备号
-* @param   flow_id          流号
-* @param   qvos_mode        溢出模式，参见DPP_CAR_QVOS_MODE_E
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_cara_queue_qvos_set(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 flow_id,
-                                        ZXIC_UINT32 qvos_mode)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARA_QOVS_RAM_RAM2_T qvos_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), qvos_mode, CAR_QVOS_MODE_OVERFLOW_0, CAR_QVOS_MODE_OVERFLOW_MAX - 1);
-
-    qvos_cfg.cara_qovs = qvos_mode;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_CARA_QOVS_RAM_RAM2r ,
-                       0,
-                       flow_id,
-                       &qvos_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取car A的qvos溢出模式
-* @param   dev_id           设备号
-* @param   flow_id          流号
-* @param   p_qvos_mode      qvos溢出模式
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_cara_queue_qvos_get(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 flow_id,
-                                        ZXIC_UINT32 *p_qvos_mode)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARA_QOVS_RAM_RAM2_T qvos_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qvos_mode);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_CARA_QOVS_RAM_RAM2r ,
-                      0,
-                      flow_id,
-                      &qvos_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_qvos_mode = qvos_cfg.cara_qovs;
-
-    return rc;
-}
-
-
-/***********************************************************/
-/** 设置第一级的映射关系
-* @param   dev_id           设备号
-* @param   flow_id          流号
-* @param   map_flow_id      映射的流号
-* @param   map_sp           映射的优先级
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_cara_queue_map_set(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 flow_id,
-                                       ZXIC_UINT32 map_flow_id,
-                                       ZXIC_UINT32 map_sp)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_LOOK_UP_TABLE1_T map_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_sp, DPP_CAR_PRI0, DPP_CAR_PRI_MAX - 1);
-
-    map_cfg.cara_flow_id = map_flow_id;
-    map_cfg.cara_sp = map_sp;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_LOOK_UP_TABLE1r ,
-                       0,
-                       flow_id,
-                       &map_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取第一级的映射关系
-* @param   dev_id           设备号
-* @param   flow_id          流号
-* @param   p_map_flow_id    映射流号
-* @param   p_map_sp         映射优先级
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_cara_queue_map_get(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 flow_id,
-                                       ZXIC_UINT32 *p_map_flow_id,
-                                       ZXIC_UINT32 *p_map_sp)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_LOOK_UP_TABLE1_T map_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_flow_id);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_sp);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_LOOK_UP_TABLE1r,
-                      0,
-                      flow_id,
-                      &map_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_map_flow_id = map_cfg.cara_flow_id;
-    *p_map_sp = map_cfg.cara_sp;
-
-    return rc;
-}
-
-/***********************************************************/
-/** car A指定队列模式配置，仅用于调试
-* @param   dev_id           设备号
-* @param   global_en        全局队列使能，0-不使能，1-使能
-* @param   sp_en            优先级队列使能，0-不使能，1-使能
-* @param   appoint_sp       指定的优先级
-* @param   appoint_queue    指定的队列号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_cara_queue_appoint_mode_set(DPP_DEV_T *dev,
-                                                ZXIC_UINT32 global_en,
-                                                ZXIC_UINT32 sp_en,
-                                                ZXIC_UINT32 appoint_sp,
-                                                ZXIC_UINT32 appoint_queue)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARA_APPOINT_QNUM_OR_SP_T appoint_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), global_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sp_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), appoint_sp, DPP_CAR_PRI0, DPP_CAR_PRI_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), appoint_queue, 0, DPP_CAR_A_FLOW_ID_MAX);
-
-    appoint_cfg.cara_appoint_qnum_or_not = global_en;
-    appoint_cfg.cara_appoint_sp_or_not = sp_en;
-    appoint_cfg.cara_plcr_stat_sp = appoint_sp;
-    appoint_cfg.cara_plcr_stat_qnum = appoint_queue;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_CARA_APPOINT_QNUM_OR_SPr ,
-                       0,
-                       0,
-                       &appoint_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取car A指定队列模式的配置
-* @param   dev_id           设备号
-* @param   p_global_en      全局队列使能，0-不使能，1-使能
-* @param   p_sp_en          优先级队列使能，0-不使能，1-使能
-* @param   p_appoint_sp     指定的优先级
-* @param   p_appoint_queue  指定的队列号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/07
-************************************************************/
-DPP_STATUS dpp_stat_cara_queue_appoint_mode_get(DPP_DEV_T *dev,
-                                                ZXIC_UINT32 *p_global_en,
-                                                ZXIC_UINT32 *p_sp_en,
-                                                ZXIC_UINT32 *p_appoint_sp,
-                                                ZXIC_UINT32 *p_appoint_queue)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARA_APPOINT_QNUM_OR_SP_T appoint_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_global_en);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_sp_en);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_appoint_sp);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_appoint_queue);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_CARA_APPOINT_QNUM_OR_SPr,
-                      0,
-                      0,
-                      &appoint_cfg);
-
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_global_en = appoint_cfg.cara_appoint_qnum_or_not;
-    *p_sp_en = appoint_cfg.cara_appoint_sp_or_not;
-    *p_appoint_sp = appoint_cfg.cara_plcr_stat_sp;
-    *p_appoint_queue = appoint_cfg.cara_plcr_stat_qnum;
-
-    return rc;
-}
-
-
-/***********************************************************/
-/** car A 调试计数读取模式配置
-* @param   dev_id           设备号
-* @param   overflow_mode    溢出模式，0-计数最大保持，1-计数最大翻转
-* @param   rd_mode          读取模式，0-不读清，1-读清模式
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_cara_dbg_cnt_mode_set(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 overflow_mode,
-                                          ZXIC_UINT32 rd_mode)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARA_CFGMT_COUNT_MODE_T cnt_mode_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), overflow_mode, CAR_KEEP_COUNT, CAR_RE_COUNT);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_mode, CAR_READ_NOT_CLEAR, CAR_READ_AND_CLEAR);
-
-    cnt_mode_cfg.cara_cfgmt_count_overflow_mode = overflow_mode;
-    cnt_mode_cfg.cara_cfgmt_count_rd_mode = rd_mode;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_CARA_CFGMT_COUNT_MODEr ,
-                       0,
-                       0,
-                       &cnt_mode_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** car A 调试计数读取模式获取
-* @param   dev_id           设备号
-* @param   p_overflow_mode
-* @param   p_rd_mode
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_cara_dbg_cnt_mode_get(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 *p_overflow_mode,
-                                          ZXIC_UINT32 *p_rd_mode)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARA_CFGMT_COUNT_MODE_T cnt_mode_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_overflow_mode);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_rd_mode);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_CARA_CFGMT_COUNT_MODEr,
-                      0,
-                      0,
-                      &cnt_mode_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_overflow_mode = cnt_mode_cfg.cara_cfgmt_count_overflow_mode;
-    *p_rd_mode = cnt_mode_cfg.cara_cfgmt_count_rd_mode;
-
-    return rc;
-}
-
-#if 0
-/***********************************************************/
-/** car a 的调试计数获取
-* @param   dev_id
-* @param   p_car_dbg_cnt
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/09/27
-************************************************************/
-DPP_STATUS dpp_stat_cara_dbg_cnt_get(ZXIC_UINT32 dev_id,
-                                     DPP_STAT_CAR_DBG_CNT_T *p_car_dbg_cnt)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARA_PKT_DES_I_CNT_T cara_pkt_in_total_cnt_cfg = {0};
-    DPP_STAT_CAR0_CARA_PKT_SIZE_CNT_T  cara_pkt_size_cnt_cfg = {0};
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 size = 0;
-    ZXIC_UINT32 *p_tmp_cnt = NULL;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_dbg_cnt);
-
-    size = sizeof(DPP_STAT_CAR_DBG_CNT_T) / sizeof(ZXIC_UINT32) - 1;
-    p_tmp_cnt = (ZXIC_UINT32 *)p_car_dbg_cnt;
-
-    for (i = 0; i < size; i++)
-    {
-        rc = dpp_reg_read(dev_id,
-                          STAT_CAR0_CARA_PKT_DES_I_CNTr + i,
-                          0,
-                          0,
-                          &cara_pkt_in_total_cnt_cfg);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read");
-
-        ZXIC_COMM_MEMCPY(p_tmp_cnt + i, &(cara_pkt_in_total_cnt_cfg.cara_pkt_des_i_cnt), sizeof(ZXIC_UINT32));
-    }
-
-    /* STAT_CAR0_CARA_PKT_SIZE_CNTr 不连续，单独读取 */
-    rc = dpp_reg_read(dev_id,
-                      STAT_CAR0_CARA_PKT_SIZE_CNTr,
-                      0,
-                      0,
-                      &cara_pkt_size_cnt_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read");
-
-    p_car_dbg_cnt->pkt_size_cnt = cara_pkt_size_cnt_cfg.cara_pkt_size_cnt;
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取car A的初始化状态
-* @param   dev_id           设备号
-* @param   p_init_done      初始化完成使能
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_cara_init_done_get(ZXIC_UINT32 dev_id,
-                                       ZXIC_UINT32 *p_init_done)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARA_PLCR_INIT_DONT_T cara_init_done_cfg = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_init_done);
-
-    rc = dpp_reg_read(dev_id,
-                      STAT_CAR0_CARA_PLCR_INIT_DONTr,
-                      0,
-                      0,
-                      &cara_init_done_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read");
-
-    *p_init_done = cara_init_done_cfg.cara_plcr_init_done;
-
-    return rc;
-}
-
-#endif
-/***********************************************************/
-/** car B的流设置
-* @param   dev_id           设备号
-* @param   flow_id          流号
-* @param   drop_flag        丢弃标志
-* @param   plcr_en          监管使能
-* @param   profile_id       监管模板号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_carb_queue_cfg_set(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 flow_id,
-                                       ZXIC_UINT32 drop_flag,
-                                       ZXIC_UINT32 plcr_en,
-                                       ZXIC_UINT32 profile_id)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    DPP_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T queue_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), drop_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), plcr_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_MAX);
-
-    queue_cfg.carb_drop = drop_flag;
-    queue_cfg.carb_plcr_en = plcr_en;
-    queue_cfg.carb_profile_id = profile_id;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_CARB_QUEUE_RAM0_159_0r ,
-                       0,
-                       flow_id,
-                       &queue_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取car B的流设置
-* @param   dev_id               设备号
-* @param   flow_id              流号
-* @param   p_carb_queue_cfg     car A流配置信息
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_carb_queue_cfg_get(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 flow_id,
-                                       DPP_STAT_CAR_B_QUEUE_CFG_T *p_carb_queue_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    DPP_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T queue_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carb_queue_cfg);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_CARB_QUEUE_RAM0_159_0r,
-                      0,
-                      flow_id,
-                      &queue_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    p_carb_queue_cfg->flow_id = flow_id;
-    p_carb_queue_cfg->drop_flag = queue_cfg.carb_drop;
-    p_carb_queue_cfg->plcr_en = queue_cfg.carb_plcr_en;
-    p_carb_queue_cfg->profile_id = queue_cfg.carb_profile_id;
-
-    p_carb_queue_cfg->tq = ZXIC_COMM_COUNTER64_BUILD(queue_cfg.carb_tq_h, queue_cfg.carb_tq_l);
-
-    p_carb_queue_cfg->tce_flag = queue_cfg.carb_ted;
-    p_carb_queue_cfg->tce = queue_cfg.carb_tcd;
-    p_carb_queue_cfg->te = queue_cfg.carb_tei;
-    p_carb_queue_cfg->tc = queue_cfg.carb_tci;
-
-    return rc;
-}
-
-/***********************************************************/
-/** car B监管模板设定
-* @param   dev_id               设备号
-* @param   profile_id           监管模板号
-* @param   p_carb_profile_cfg   监管模板配置
-*          pkt_sign 包限速标记写死成0，防止用户在carB包限速
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_carb_profile_cfg_set(DPP_DEV_T *dev,
-                                         ZXIC_UINT32 profile_id,
-                                         DPP_STAT_CAR_PROFILE_CFG_T *p_carb_profile_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-
-    DPP_STAT_CAR0_CARB_PROFILE_RAM1_255_0_T profile_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carb_profile_cfg);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->pkt_sign, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->cf, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->cm, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->random_disc_e, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->random_disc_c, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->cd, CAR_CD_MODE_SRTCM, CAR_CD_MODE_INVALID - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->cir, 0, DPP_CAR_MAX_CIR_VALUE);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->eir, 0, DPP_CAR_MAX_EIR_VALUE);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->cbs, 0, DPP_CAR_MAX_CBS_VALUE);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->ebs, 0, DPP_CAR_MAX_EBS_VALUE);
-
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->e_yellow_pri[0], 0, DPP_CAR_MAX_PRI_VALUE);
-
-    for (i = 1; i < DPP_CAR_PRI_MAX; i++)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->c_pri[i], 0, DPP_CAR_MAX_PRI_VALUE);
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->e_green_pri[i], 0, DPP_CAR_MAX_PRI_VALUE);
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->e_yellow_pri[i], 0, DPP_CAR_MAX_PRI_VALUE);
-    }
-
-    profile_cfg.carb_e_y_pri7 = p_carb_profile_cfg->e_yellow_pri[7];
-    profile_cfg.carb_e_y_pri6 = p_carb_profile_cfg->e_yellow_pri[6];
-    profile_cfg.carb_e_y_pri5 = p_carb_profile_cfg->e_yellow_pri[5];
-    profile_cfg.carb_e_y_pri4 = p_carb_profile_cfg->e_yellow_pri[4];
-    profile_cfg.carb_e_y_pri3 = p_carb_profile_cfg->e_yellow_pri[3];
-    profile_cfg.carb_e_y_pri2 = p_carb_profile_cfg->e_yellow_pri[2];
-    profile_cfg.carb_e_y_pri1 = p_carb_profile_cfg->e_yellow_pri[1];
-    profile_cfg.carb_e_y_pri0 = p_carb_profile_cfg->e_yellow_pri[0];
-
-    profile_cfg.carb_e_g_pri7 = p_carb_profile_cfg->e_green_pri[7];
-    profile_cfg.carb_e_g_pri6 = p_carb_profile_cfg->e_green_pri[6];
-    profile_cfg.carb_e_g_pri5 = p_carb_profile_cfg->e_green_pri[5];
-    profile_cfg.carb_e_g_pri4 = p_carb_profile_cfg->e_green_pri[4];
-    profile_cfg.carb_e_g_pri3 = p_carb_profile_cfg->e_green_pri[3];
-    profile_cfg.carb_e_g_pri2 = p_carb_profile_cfg->e_green_pri[2];
-    profile_cfg.carb_e_g_pri1 = p_carb_profile_cfg->e_green_pri[1];
-
-    profile_cfg.carb_c_pri7 = p_carb_profile_cfg->c_pri[7];
-    profile_cfg.carb_c_pri6 = p_carb_profile_cfg->c_pri[6];
-    profile_cfg.carb_c_pri5 = p_carb_profile_cfg->c_pri[5];
-    profile_cfg.carb_c_pri4 = p_carb_profile_cfg->c_pri[4];
-    profile_cfg.carb_c_pri3 = p_carb_profile_cfg->c_pri[3];
-    profile_cfg.carb_c_pri2 = p_carb_profile_cfg->c_pri[2];
-    profile_cfg.carb_c_pri1 = p_carb_profile_cfg->c_pri[1];
-
-    profile_cfg.carb_cbs = p_carb_profile_cfg->cbs;
-    profile_cfg.carb_ebs_pbs = p_carb_profile_cfg->ebs;
-    profile_cfg.carb_cir = p_carb_profile_cfg->cir;
-    profile_cfg.carb_eir = p_carb_profile_cfg->eir;
-
-    profile_cfg.carb_cd = p_carb_profile_cfg->cd;
-    profile_cfg.carb_cf = p_carb_profile_cfg->cf;
-    profile_cfg.carb_cm = p_carb_profile_cfg->cm;
-
-    profile_cfg.carb_random_discard_en_e = p_carb_profile_cfg->random_disc_e;
-    profile_cfg.carb_random_discard_en_c = p_carb_profile_cfg->random_disc_c;
-    /* B级car包限速标记写死为0，以免用户配置成1对CARB进行包限速 */
-    profile_cfg.carb_pkt_sign = 0;
-
-    profile_cfg.carb_profile_wr = 0;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_CARB_PROFILE_RAM1_255_0r,
-                       0,
-                       profile_id,
-                       &profile_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-
-/***********************************************************/
-/** 获取car B的监管模板配置
-* @param   dev_id               设备号
-* @param   profile_id           监管模板号
-* @param   p_carb_profile_cfg   监管模板配置
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_carb_profile_cfg_get(DPP_DEV_T *dev,
-                                         ZXIC_UINT32 profile_id,
-                                         DPP_STAT_CAR_PROFILE_CFG_T *p_carb_profile_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    DPP_STAT_CAR0_CARB_PROFILE_RAM1_255_0_T profile_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carb_profile_cfg);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_CARB_PROFILE_RAM1_255_0r,
-                      0,
-                      profile_id,
-                      &profile_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    p_carb_profile_cfg->profile_id = profile_id;
-    p_carb_profile_cfg->pkt_sign = profile_cfg.carb_pkt_sign;
-    p_carb_profile_cfg->cd = profile_cfg.carb_cd;
-    p_carb_profile_cfg->cf = profile_cfg.carb_cf;
-    p_carb_profile_cfg->cm = profile_cfg.carb_cm;
-    p_carb_profile_cfg->eir = profile_cfg.carb_eir;
-    p_carb_profile_cfg->cir = profile_cfg.carb_cir;
-    p_carb_profile_cfg->ebs = profile_cfg.carb_ebs_pbs;
-    p_carb_profile_cfg->cbs = profile_cfg.carb_cbs;
-    p_carb_profile_cfg->random_disc_e = profile_cfg.carb_random_discard_en_e;
-    p_carb_profile_cfg->random_disc_c = profile_cfg.carb_random_discard_en_c;
-
-    p_carb_profile_cfg->c_pri[1] = profile_cfg.carb_c_pri1;
-    p_carb_profile_cfg->c_pri[2] = profile_cfg.carb_c_pri2;
-    p_carb_profile_cfg->c_pri[3] = profile_cfg.carb_c_pri3;
-    p_carb_profile_cfg->c_pri[4] = profile_cfg.carb_c_pri4;
-    p_carb_profile_cfg->c_pri[5] = profile_cfg.carb_c_pri5;
-    p_carb_profile_cfg->c_pri[6] = profile_cfg.carb_c_pri6;
-    p_carb_profile_cfg->c_pri[7] = profile_cfg.carb_c_pri7;
-
-    p_carb_profile_cfg->e_green_pri[1] = profile_cfg.carb_e_g_pri1;
-    p_carb_profile_cfg->e_green_pri[2] = profile_cfg.carb_e_g_pri2;
-    p_carb_profile_cfg->e_green_pri[3] = profile_cfg.carb_e_g_pri3;
-    p_carb_profile_cfg->e_green_pri[4] = profile_cfg.carb_e_g_pri4;
-    p_carb_profile_cfg->e_green_pri[5] = profile_cfg.carb_e_g_pri5;
-    p_carb_profile_cfg->e_green_pri[6] = profile_cfg.carb_e_g_pri6;
-    p_carb_profile_cfg->e_green_pri[7] = profile_cfg.carb_e_g_pri7;
-
-    p_carb_profile_cfg->e_yellow_pri[0] = profile_cfg.carb_e_y_pri0;
-    p_carb_profile_cfg->e_yellow_pri[1] = profile_cfg.carb_e_y_pri1;
-    p_carb_profile_cfg->e_yellow_pri[2] = profile_cfg.carb_e_y_pri2;
-    p_carb_profile_cfg->e_yellow_pri[3] = profile_cfg.carb_e_y_pri3;
-    p_carb_profile_cfg->e_yellow_pri[4] = profile_cfg.carb_e_y_pri4;
-    p_carb_profile_cfg->e_yellow_pri[5] = profile_cfg.carb_e_y_pri5;
-    p_carb_profile_cfg->e_yellow_pri[6] = profile_cfg.carb_e_y_pri6;
-    p_carb_profile_cfg->e_yellow_pri[7] = profile_cfg.carb_e_y_pri7;
-
-    return rc;
-}
-
-/***********************************************************/
-/** 配置car B的qvos溢出模式
-* @param   dev_id           设备号
-* @param   flow_id          流号
-* @param   qvos_mode        溢出模式，参见DPP_CAR_QVOS_MODE_E
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carb_queue_qvos_set(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 flow_id,
-                                        ZXIC_UINT32 qvos_mode)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARB_QOVS_RAM_RAM2_T qvos_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), qvos_mode, CAR_QVOS_MODE_OVERFLOW_0, CAR_QVOS_MODE_OVERFLOW_MAX - 1);
-
-    qvos_cfg.carb_qovs = qvos_mode;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_CARB_QOVS_RAM_RAM2r,
-                       0,
-                       flow_id,
-                       &qvos_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-/***********************************************************/
-/** 获取car B的qvos溢出模式
-* @param   dev_id           设备号
-* @param   flow_id          流号
-* @param   p_qvos_mode      qvos溢出模式
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carb_queue_qvos_get(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 flow_id,
-                                        ZXIC_UINT32 *p_qvos_mode)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARB_QOVS_RAM_RAM2_T qvos_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qvos_mode);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_CARB_QOVS_RAM_RAM2r ,
-                      0,
-                      flow_id,
-                      &qvos_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_qvos_mode = qvos_cfg.carb_qovs;
-
-    return rc;
-}
-
-/***********************************************************/
-/** 设置第二级的映射关系
-* @param   dev_id           设备号
-* @param   flow_id          流号
-* @param   map_flow_id      映射的流号
-* @param   map_sp           映射的优先级
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carb_queue_map_set(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 flow_id,
-                                       ZXIC_UINT32 map_flow_id,
-                                       ZXIC_UINT32 map_sp)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_LOOK_UP_TABLE2_T map_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_flow_id, 0, DPP_CAR_C_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_sp, DPP_CAR_PRI0, DPP_CAR_PRI_MAX - 1);
-
-    map_cfg.carb_flow_id = map_flow_id;
-    map_cfg.carb_sp = map_sp;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_LOOK_UP_TABLE2r ,
-                       0,
-                       flow_id,
-                       &map_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取第二级的映射关系
-* @param   dev_id           设备号
-* @param   flow_id          流号
-* @param   p_map_flow_id    映射流号
-* @param   p_map_sp         映射优先级
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carb_queue_map_get(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 flow_id,
-                                       ZXIC_UINT32 *p_map_flow_id,
-                                       ZXIC_UINT32 *p_map_sp)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_LOOK_UP_TABLE2_T map_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_flow_id);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_sp);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_LOOK_UP_TABLE2r ,
-                      0,
-                      flow_id,
-                      &map_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_map_flow_id = map_cfg.carb_flow_id;
-    *p_map_sp      = map_cfg.carb_sp;
-
-    return rc;
-}
-
-#if 0
-/***********************************************************/
-/** car B指定队列模式配置，仅用于调试
-* @param   dev_id           设备号
-* @param   global_en        全局队列使能，0-不使能，1-使能
-* @param   sp_en            优先级队列使能，0-不使能，1-使能
-* @param   appoint_sp       指定的优先级
-* @param   appoint_queue    指定的队列号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carb_queue_appoint_mode_set(ZXIC_UINT32 dev_id,
-                                                ZXIC_UINT32 global_en,
-                                                ZXIC_UINT32 sp_en,
-                                                ZXIC_UINT32 appoint_sp,
-                                                ZXIC_UINT32 appoint_queue)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARB_APPOINT_QNUM_OR_SP_T appoint_cfg = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, global_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sp_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, appoint_sp, DPP_CAR_PRI0, DPP_CAR_PRI_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, appoint_queue, 0, DPP_CAR_B_FLOW_ID_MAX);
-
-    appoint_cfg.carb_appoint_qnum_or_not = global_en;
-    appoint_cfg.carb_appoint_sp_or_not = sp_en;
-    appoint_cfg.carb_plcr_stat_sp = appoint_sp;
-    appoint_cfg.carb_plcr_stat_qnum = appoint_queue;
-
-    rc = dpp_reg_write(dev_id,
-                       STAT_CAR0_CARB_APPOINT_QNUM_OR_SPr,
-                       0,
-                       0,
-                       &appoint_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取car B指定队列模式的配置
-* @param   dev_id           设备号
-* @param   p_global_en      全局队列使能，0-不使能，1-使能
-* @param   p_sp_en          优先级队列使能，0-不使能，1-使能
-* @param   p_appoint_sp     指定的优先级
-* @param   p_appoint_queue  指定的队列号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/07
-************************************************************/
-DPP_STATUS dpp_stat_carb_queue_appoint_mode_get(ZXIC_UINT32 dev_id,
-                                                ZXIC_UINT32 *p_global_en,
-                                                ZXIC_UINT32 *p_sp_en,
-                                                ZXIC_UINT32 *p_appoint_sp,
-                                                ZXIC_UINT32 *p_appoint_queue)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARB_APPOINT_QNUM_OR_SP_T appoint_cfg = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_global_en);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_sp_en);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_appoint_sp);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_appoint_queue);
-
-    rc = dpp_reg_read(dev_id,
-                      STAT_CAR0_CARB_APPOINT_QNUM_OR_SPr,
-                      0,
-                      0,
-                      &appoint_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read");
-
-    *p_global_en = appoint_cfg.carb_appoint_qnum_or_not;
-    *p_sp_en = appoint_cfg.carb_appoint_sp_or_not;
-    *p_appoint_sp = appoint_cfg.carb_plcr_stat_sp;
-    *p_appoint_queue = appoint_cfg.carb_plcr_stat_qnum;
-
-    return rc;
-}
-
-/***********************************************************/
-/** car B 调试计数读取模式配置
-* @param   dev_id           设备号
-* @param   overflow_mode    溢出模式，0-计数最大保持，1-计数最大翻转
-* @param   rd_mode          读取模式，0-不读清，1-读清模式
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carb_dbg_cnt_mode_set(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 overflow_mode,
-                                          ZXIC_UINT32 rd_mode)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARB_CFGMT_COUNT_MODE_T cnt_mode_cfg = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, overflow_mode, CAR_KEEP_COUNT, CAR_RE_COUNT);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, rd_mode, CAR_READ_NOT_CLEAR, CAR_READ_AND_CLEAR);
-
-    cnt_mode_cfg.carb_cfgmt_count_overflow_mode = overflow_mode;
-    cnt_mode_cfg.carb_cfgmt_count_rd_mode = rd_mode;
-
-    rc = dpp_reg_write(dev_id,
-                       STAT_CAR0_CARB_CFGMT_COUNT_MODEr,
-                       0,
-                       0,
-                       &cnt_mode_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/**
-* @param   dev_id
-* @param   p_overflow_mode
-* @param   p_rd_mode
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carb_dbg_cnt_mode_get(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 *p_overflow_mode,
-                                          ZXIC_UINT32 *p_rd_mode)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARB_CFGMT_COUNT_MODE_T cnt_mode_cfg = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_overflow_mode);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rd_mode);
-
-    rc = dpp_reg_read(dev_id,
-                      STAT_CAR0_CARB_CFGMT_COUNT_MODEr,
-                      0,
-                      0,
-                      &cnt_mode_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read");
-
-    *p_overflow_mode = cnt_mode_cfg.carb_cfgmt_count_overflow_mode;
-    *p_rd_mode = cnt_mode_cfg.carb_cfgmt_count_rd_mode;
-
-    return rc;
-}
-
-/***********************************************************/
-/** car b 的调试计数获取
-* @param   dev_id
-* @param   p_car_dbg_cnt
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/09/27
-************************************************************/
-DPP_STATUS dpp_stat_carb_dbg_cnt_get(ZXIC_UINT32 dev_id,
-                                     DPP_STAT_CAR_DBG_CNT_T *p_car_dbg_cnt)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 size = 0;
-    ZXIC_UINT32 *p_tmp_cnt = NULL;
-
-    DPP_STAT_CAR0_CARB_PKT_SIZE_CNT_T carb_pkt_size_cnt_cfg = {0};
-    DPP_STAT_CAR0_CARB_PKT_DES_I_CNT_T carb_pkt_in_total_cnt_cfg = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_dbg_cnt);
-
-    size = sizeof(DPP_STAT_CAR_DBG_CNT_T) / sizeof(ZXIC_UINT32) - 1;
-    p_tmp_cnt = (ZXIC_UINT32 *)p_car_dbg_cnt;
-
-    for (i = 0; i < size; i++)
-    {
-        rc = dpp_reg_read(dev_id,
-                          STAT_CAR0_CARB_PKT_DES_I_CNTr + i,
-                          0,
-                          0,
-                          &carb_pkt_in_total_cnt_cfg);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read");
-
-        ZXIC_COMM_MEMCPY(p_tmp_cnt + i, &(carb_pkt_in_total_cnt_cfg.carb_pkt_des_i_cnt), sizeof(ZXIC_UINT32));
-    }
-
-    rc = dpp_reg_read(dev_id,
-                      STAT_CAR0_CARB_PKT_SIZE_CNTr,
-                      0,
-                      0,
-                      &carb_pkt_size_cnt_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read");
-
-    p_car_dbg_cnt->pkt_size_cnt = carb_pkt_size_cnt_cfg.carb_pkt_size_cnt;
-
-    return rc;
-}
-
-
-/***********************************************************/
-/** 获取car B的初始化状态
-* @param   dev_id           设备号           car编号
-* @param   p_init_done      初始化完成使能
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carb_init_done_get(ZXIC_UINT32 dev_id,
-                                       ZXIC_UINT32 *p_init_done)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARB_PLCR_INIT_DONT_T carb_init_done_cfg = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_init_done);
-
-    rc = dpp_reg_read(dev_id,
-                      STAT_CAR0_CARB_PLCR_INIT_DONTr ,
-                      0,
-                      0,
-                      &carb_init_done_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read");
-
-    *p_init_done = carb_init_done_cfg.carb_plcr_init_done;
-
-    return rc;
-}
-
-#endif
-/***********************************************************/
-/** 
-* @param   dev_id
-* @param   profile_id
-* @param   p_random_ram
-*
-* @return  
-* @remark  无
-* @see     
-* @author  YXH      @date  2019/04/01
-************************************************************/
-DPP_STATUS dpp_stat_carb_random_ram_set(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 profile_id,
-                                        DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
-                                        DPP_CAR_RANDOM_RAM_T *p_random_ram_c)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT64 para0_temp = 0;
-    ZXIC_UINT64 para2_temp = 0;
-    ZXIC_UINT64 para4_temp = 0;
-    DPP_STAT_CAR0_CARB_RANDOM_RAM_T carb_random_ram_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p1, 0, 100);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p2, 0, 100);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p3, 0, 100);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p1, 0, 100);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p2, 0, 100);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p3, 0, 100);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_RANDOM_MAX);
-
-    para0_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->t2)) - ((ZXIC_UINT64)(p_random_ram_e->t1))) * ((ZXIC_UINT64)(p_random_ram_e->p1))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-    carb_random_ram_cfg.para0_l_e = (para0_temp & 0xFFFFFFFF);
-    carb_random_ram_cfg.para0_h_e = (para0_temp >> 32) & 0xFFFFFFFF;
-
-    carb_random_ram_cfg.para1_e = ((p_random_ram_e->p2 - p_random_ram_e->p1) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-
-    para2_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->t3)) - ((ZXIC_UINT64)(p_random_ram_e->t2))) * ((ZXIC_UINT64)(p_random_ram_e->p2))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-    carb_random_ram_cfg.para2_l_e = (para2_temp & 0xFFFFFFFF);
-    carb_random_ram_cfg.para2_h_e = (para2_temp >> 32) & 0xFFFFFFFF;
-
-    carb_random_ram_cfg.para3_e = ((p_random_ram_e->p3 - p_random_ram_e->p2) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-
-    para4_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->tc)) - ((ZXIC_UINT64)(p_random_ram_e->t3))) * ((ZXIC_UINT64)(p_random_ram_e->p3))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-    carb_random_ram_cfg.para4_l_e = (para4_temp & 0xFFFFFFFF);
-    carb_random_ram_cfg.para4_h_e = (para4_temp >> 32) & 0xFFFFFFFF;
-
-    carb_random_ram_cfg.para5_e = ((100 - p_random_ram_e->p3) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-    carb_random_ram_cfg.para6_e = p_random_ram_e->t1;
-    carb_random_ram_cfg.para7_e = p_random_ram_e->t2;
-    carb_random_ram_cfg.para8_e = p_random_ram_e->t3;
-
-    /* para0_temp = 0;
-    para2_temp = 0;
-    para4_temp = 0; */
-
-    para0_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->t2)) - ((ZXIC_UINT64)(p_random_ram_c->t1))) * ((ZXIC_UINT64)(p_random_ram_c->p1))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-    carb_random_ram_cfg.para0_l_c = (para0_temp & 0xFFFFFFFF);
-    carb_random_ram_cfg.para0_h_c = (para0_temp >> 32) & 0xFFFFFFFF;
-
-    carb_random_ram_cfg.para1_c = ((p_random_ram_c->p2 - p_random_ram_c->p1) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-
-    para2_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->t3)) - ((ZXIC_UINT64)(p_random_ram_c->t2))) * ((ZXIC_UINT64)(p_random_ram_c->p2))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-    carb_random_ram_cfg.para2_l_c = (para2_temp & 0xFFFFFFFF);
-    carb_random_ram_cfg.para2_h_c = (para2_temp >> 32) & 0xFFFFFFFF;
-
-    carb_random_ram_cfg.para3_c = ((p_random_ram_c->p3 - p_random_ram_c->p2) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-
-    para4_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->tc)) - ((ZXIC_UINT64)(p_random_ram_c->t3))) * ((ZXIC_UINT64)(p_random_ram_c->p3))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-    carb_random_ram_cfg.para4_l_c = (para4_temp & 0xFFFFFFFF);
-    carb_random_ram_cfg.para4_h_c = (para4_temp >> 32) & 0xFFFFFFFF;
-
-    carb_random_ram_cfg.para5_c = ((100 - p_random_ram_c->p3) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-    carb_random_ram_cfg.para6_c = p_random_ram_c->t1;
-    carb_random_ram_cfg.para7_c = p_random_ram_c->t2;
-    carb_random_ram_cfg.para8_c = p_random_ram_c->t3;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_CARB_RANDOM_RAMr ,
-                       0,
-                       profile_id,
-                       &carb_random_ram_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** 
-* @param   dev_id
-* @param   p_random_ram
-*
-* @return
-* @remark  无
-* @see
-* @author  YXH      @date  2019/04/01
-************************************************************/
-DPP_STATUS dpp_stat_carb_random_ram_get(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 profile_id,
-                                        DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
-                                        DPP_CAR_RANDOM_RAM_T *p_random_ram_c)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARB_RANDOM_RAM_T carb_random_ram_cfg = {0};
-    ZXIC_UINT32 tmp_val = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_RANDOM_MAX);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_CARB_RANDOM_RAMr ,
-                      0,
-                      profile_id,
-                      &carb_random_ram_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    p_random_ram_e->t1 = carb_random_ram_cfg.para6_e;
-    p_random_ram_e->t2 = carb_random_ram_cfg.para7_e;
-    p_random_ram_e->t3 = carb_random_ram_cfg.para8_e;
-    tmp_val = (carb_random_ram_cfg.para5_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
-    p_random_ram_e->p3 = 100 - tmp_val;
-    tmp_val = (carb_random_ram_cfg.para3_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
-    p_random_ram_e->p2 = p_random_ram_e->p3 - tmp_val;
-    tmp_val = (carb_random_ram_cfg.para1_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
-    p_random_ram_e->p1 = p_random_ram_e->p2 - tmp_val;
-
-    p_random_ram_c->t1 = carb_random_ram_cfg.para6_c;
-    p_random_ram_c->t2 = carb_random_ram_cfg.para7_c;
-    p_random_ram_c->t3 = carb_random_ram_cfg.para8_c;
-    tmp_val = (carb_random_ram_cfg.para5_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
-    p_random_ram_c->p3 = 100 - tmp_val;
-    tmp_val = (carb_random_ram_cfg.para3_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
-    p_random_ram_c->p2 = p_random_ram_c->p3 - tmp_val;
-    tmp_val = (carb_random_ram_cfg.para1_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
-    p_random_ram_c->p1 = p_random_ram_c->p2 - tmp_val;
-
-    return rc;
-}
-
-/***********************************************************/
-/** car C的流设置
-* @param   dev_id           设备号           car编号
-* @param   flow_id          流号
-* @param   drop_flag        丢弃标志
-* @param   plcr_en          监管使能
-* @param   profile_id       监管模板号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_carc_queue_cfg_set(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 flow_id,
-                                       ZXIC_UINT32 drop_flag,
-                                       ZXIC_UINT32 plcr_en,
-                                       ZXIC_UINT32 profile_id)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    DPP_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T queue_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), drop_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), plcr_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_MAX);
-
-    queue_cfg.carc_drop = drop_flag;
-    queue_cfg.carc_plcr_en = plcr_en;
-    queue_cfg.carc_profile_id = profile_id;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_CARC_QUEUE_RAM0_159_0r ,
-                       0,
-                       flow_id,
-                       &queue_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取car C的流设置
-* @param   dev_id               设备号               car编号
-* @param   flow_id              流号
-* @param   p_carc_queue_cfg     car c流配置信息
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_carc_queue_cfg_get(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 flow_id,
-                                       DPP_STAT_CAR_C_QUEUE_CFG_T *p_carc_queue_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    DPP_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T queue_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carc_queue_cfg);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_CARC_QUEUE_RAM0_159_0r,
-                      0,
-                      flow_id,
-                      &queue_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    p_carc_queue_cfg->flow_id = flow_id;
-    p_carc_queue_cfg->drop_flag = queue_cfg.carc_drop;
-    p_carc_queue_cfg->plcr_en = queue_cfg.carc_plcr_en;
-    p_carc_queue_cfg->profile_id = queue_cfg.carc_profile_id;
-
-    p_carc_queue_cfg->tq = ZXIC_COMM_COUNTER64_BUILD(queue_cfg.carc_tq_h, queue_cfg.carc_tq_l);
-
-    p_carc_queue_cfg->tce_flag = queue_cfg.carc_ted;
-    p_carc_queue_cfg->tce = queue_cfg.carc_tcd;
-    p_carc_queue_cfg->te = queue_cfg.carc_tei;
-    p_carc_queue_cfg->tc = queue_cfg.carc_tci;
-
-    return rc;
-}
-
-/***********************************************************/
-/** car C监管模板设定
-* @param   dev_id               设备号               car编号
-* @param   profile_id           监管模板号
-* @param   p_carc_profile_cfg   监管模板配置
-*          pkt_sign 包限速标记写死成0，防止用户在carC包限速
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_carc_profile_cfg_set(DPP_DEV_T *dev,
-                                         ZXIC_UINT32 profile_id,
-                                         DPP_STAT_CAR_PROFILE_CFG_T *p_carc_profile_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-
-    DPP_STAT_CAR0_CARC_PROFILE_RAM1_255_0_T profile_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carc_profile_cfg);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->pkt_sign, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->cf, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->cm, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->random_disc_e, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->random_disc_c, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->cd, CAR_CD_MODE_SRTCM, CAR_CD_MODE_INVALID - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->cir, 0, DPP_CAR_MAX_CIR_VALUE);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->eir, 0, DPP_CAR_MAX_EIR_VALUE);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->cbs, 0, DPP_CAR_MAX_CBS_VALUE);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->ebs, 0, DPP_CAR_MAX_EBS_VALUE);
-
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->e_yellow_pri[0], 0, DPP_CAR_MAX_PRI_VALUE);
-
-    for (i = 1; i < DPP_CAR_PRI_MAX; i++)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->c_pri[i], 0, DPP_CAR_MAX_PRI_VALUE);
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->e_green_pri[i], 0, DPP_CAR_MAX_PRI_VALUE);
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->e_yellow_pri[i], 0, DPP_CAR_MAX_PRI_VALUE);
-    }
-
-    profile_cfg.carc_e_y_pri7 = p_carc_profile_cfg->e_yellow_pri[7];
-    profile_cfg.carc_e_y_pri6 = p_carc_profile_cfg->e_yellow_pri[6];
-    profile_cfg.carc_e_y_pri5 = p_carc_profile_cfg->e_yellow_pri[5];
-    profile_cfg.carc_e_y_pri4 = p_carc_profile_cfg->e_yellow_pri[4];
-    profile_cfg.carc_e_y_pri3 = p_carc_profile_cfg->e_yellow_pri[3];
-    profile_cfg.carc_e_y_pri2 = p_carc_profile_cfg->e_yellow_pri[2];
-    profile_cfg.carc_e_y_pri1 = p_carc_profile_cfg->e_yellow_pri[1];
-    profile_cfg.carc_e_y_pri0 = p_carc_profile_cfg->e_yellow_pri[0];
-
-    profile_cfg.carc_e_g_pri7 = p_carc_profile_cfg->e_green_pri[7];
-    profile_cfg.carc_e_g_pri6 = p_carc_profile_cfg->e_green_pri[6];
-    profile_cfg.carc_e_g_pri5 = p_carc_profile_cfg->e_green_pri[5];
-    profile_cfg.carc_e_g_pri4 = p_carc_profile_cfg->e_green_pri[4];
-    profile_cfg.carc_e_g_pri3 = p_carc_profile_cfg->e_green_pri[3];
-    profile_cfg.carc_e_g_pri2 = p_carc_profile_cfg->e_green_pri[2];
-    profile_cfg.carc_e_g_pri1 = p_carc_profile_cfg->e_green_pri[1];
-
-    profile_cfg.carc_c_pri7 = p_carc_profile_cfg->c_pri[7];
-    profile_cfg.carc_c_pri6 = p_carc_profile_cfg->c_pri[6];
-    profile_cfg.carc_c_pri5 = p_carc_profile_cfg->c_pri[5];
-    profile_cfg.carc_c_pri4 = p_carc_profile_cfg->c_pri[4];
-    profile_cfg.carc_c_pri3 = p_carc_profile_cfg->c_pri[3];
-    profile_cfg.carc_c_pri2 = p_carc_profile_cfg->c_pri[2];
-    profile_cfg.carc_c_pri1 = p_carc_profile_cfg->c_pri[1];
-
-    profile_cfg.carc_cbs = p_carc_profile_cfg->cbs;
-    profile_cfg.carc_ebs_pbs = p_carc_profile_cfg->ebs;
-    profile_cfg.carc_cir = p_carc_profile_cfg->cir;
-    profile_cfg.carc_eir = p_carc_profile_cfg->eir;
-
-    profile_cfg.carc_cd = p_carc_profile_cfg->cd;
-    profile_cfg.carc_cf = p_carc_profile_cfg->cf;
-    profile_cfg.carc_cm = p_carc_profile_cfg->cm;
-    profile_cfg.carc_random_discard_en_e = p_carc_profile_cfg->random_disc_e;
-    profile_cfg.carc_random_discard_en_c = p_carc_profile_cfg->random_disc_c;
-    /* C级car包限速标记写死为0，以免用户配置成1对CARC进行包限速 */
-    profile_cfg.carc_pkt_sign = 0;
-
-    profile_cfg.carc_profile_wr = 0;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_CARC_PROFILE_RAM1_255_0r ,
-                       0,
-                       profile_id,
-                       &profile_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-
-/***********************************************************/
-/** 获取car C的监管模板配置
-* @param   dev_id               设备号               car编号
-* @param   profile_id           监管模板号
-* @param   p_carc_profile_cfg   监管模板配置
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/05
-************************************************************/
-DPP_STATUS dpp_stat_carc_profile_cfg_get(DPP_DEV_T *dev,
-                                         ZXIC_UINT32 profile_id,
-                                         DPP_STAT_CAR_PROFILE_CFG_T *p_carc_profile_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARC_PROFILE_RAM1_255_0_T profile_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carc_profile_cfg);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_CARC_PROFILE_RAM1_255_0r,
-                      0,
-                      profile_id,
-                      &profile_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    p_carc_profile_cfg->profile_id = profile_id;
-    p_carc_profile_cfg->pkt_sign = profile_cfg.carc_pkt_sign;
-    p_carc_profile_cfg->cd = profile_cfg.carc_cd;
-    p_carc_profile_cfg->cf = profile_cfg.carc_cf;
-    p_carc_profile_cfg->cm = profile_cfg.carc_cm;
-
-    p_carc_profile_cfg->eir = profile_cfg.carc_eir;
-    p_carc_profile_cfg->cir = profile_cfg.carc_cir;
-    p_carc_profile_cfg->ebs = profile_cfg.carc_ebs_pbs;
-    p_carc_profile_cfg->cbs = profile_cfg.carc_cbs;
-
-    p_carc_profile_cfg->random_disc_e = profile_cfg.carc_random_discard_en_e;
-    p_carc_profile_cfg->random_disc_c = profile_cfg.carc_random_discard_en_c;
-
-    p_carc_profile_cfg->c_pri[1] = profile_cfg.carc_c_pri1;
-    p_carc_profile_cfg->c_pri[2] = profile_cfg.carc_c_pri2;
-    p_carc_profile_cfg->c_pri[3] = profile_cfg.carc_c_pri3;
-    p_carc_profile_cfg->c_pri[4] = profile_cfg.carc_c_pri4;
-    p_carc_profile_cfg->c_pri[5] = profile_cfg.carc_c_pri5;
-    p_carc_profile_cfg->c_pri[6] = profile_cfg.carc_c_pri6;
-    p_carc_profile_cfg->c_pri[7] = profile_cfg.carc_c_pri7;
-
-    p_carc_profile_cfg->e_green_pri[1] = profile_cfg.carc_e_g_pri1;
-    p_carc_profile_cfg->e_green_pri[2] = profile_cfg.carc_e_g_pri2;
-    p_carc_profile_cfg->e_green_pri[3] = profile_cfg.carc_e_g_pri3;
-    p_carc_profile_cfg->e_green_pri[4] = profile_cfg.carc_e_g_pri4;
-    p_carc_profile_cfg->e_green_pri[5] = profile_cfg.carc_e_g_pri5;
-    p_carc_profile_cfg->e_green_pri[6] = profile_cfg.carc_e_g_pri6;
-    p_carc_profile_cfg->e_green_pri[7] = profile_cfg.carc_e_g_pri7;
-
-    p_carc_profile_cfg->e_yellow_pri[0] = profile_cfg.carc_e_y_pri0;
-    p_carc_profile_cfg->e_yellow_pri[1] = profile_cfg.carc_e_y_pri1;
-    p_carc_profile_cfg->e_yellow_pri[2] = profile_cfg.carc_e_y_pri2;
-    p_carc_profile_cfg->e_yellow_pri[3] = profile_cfg.carc_e_y_pri3;
-    p_carc_profile_cfg->e_yellow_pri[4] = profile_cfg.carc_e_y_pri4;
-    p_carc_profile_cfg->e_yellow_pri[5] = profile_cfg.carc_e_y_pri5;
-    p_carc_profile_cfg->e_yellow_pri[6] = profile_cfg.carc_e_y_pri6;
-    p_carc_profile_cfg->e_yellow_pri[7] = profile_cfg.carc_e_y_pri7;
-
-    return rc;
-}
-
-/***********************************************************/
-/** 配置car C的qvos溢出模式
-* @param   dev_id           设备号           car编号
-* @param   flow_id          流号
-* @param   qvos_mode        溢出模式，参见DPP_CAR_QVOS_MODE_E
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carc_queue_qvos_set(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 flow_id,
-                                        ZXIC_UINT32 qvos_mode)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARC_QOVS_RAM_RAM2_T qvos_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), qvos_mode, CAR_QVOS_MODE_OVERFLOW_0, CAR_QVOS_MODE_OVERFLOW_MAX - 1);
-
-    qvos_cfg.carc_qovs = qvos_mode;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_CARC_QOVS_RAM_RAM2r,
-                       0,
-                       flow_id,
-                       &qvos_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-/***********************************************************/
-/** 获取car C的qvos溢出模式
-* @param   dev_id           设备号           car编号
-* @param   flow_id          流号
-* @param   p_qvos_mode      qvos溢出模式
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carc_queue_qvos_get(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 flow_id,
-                                        ZXIC_UINT32 *p_qvos_mode)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARC_QOVS_RAM_RAM2_T qvos_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qvos_mode);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_CARC_QOVS_RAM_RAM2r ,
-                      0,
-                      flow_id,
-                      &qvos_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_qvos_mode = qvos_cfg.carc_qovs;
-
-    return rc;
-}
-
-#if 0
-/***********************************************************/
-/** car C指定队列模式配置，仅用于调试
-* @param   dev_id           设备号           car编号
-* @param   global_en        全局队列使能，0-不使能，1-使能
-* @param   sp_en            优先级队列使能，0-不使能，1-使能
-* @param   appoint_sp       指定的优先级
-* @param   appoint_queue    指定的队列号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carc_queue_appoint_mode_set(ZXIC_UINT32 dev_id,
-                                                ZXIC_UINT32 global_en,
-                                                ZXIC_UINT32 sp_en,
-                                                ZXIC_UINT32 appoint_sp,
-                                                ZXIC_UINT32 appoint_queue)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARC_APPOINT_QNUM_OR_SP_T appoint_cfg = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, global_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sp_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, appoint_sp, DPP_CAR_PRI0, DPP_CAR_PRI_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, appoint_queue, 0, DPP_CAR_C_FLOW_ID_MAX);
-
-    appoint_cfg.carc_appoint_qnum_or_not = global_en;
-    appoint_cfg.carc_appoint_sp_or_not = sp_en;
-    appoint_cfg.carc_plcr_stat_sp = appoint_sp;
-    appoint_cfg.carc_plcr_stat_qnum = appoint_queue;
-
-    rc = dpp_reg_write(dev_id,
-                       STAT_CAR0_CARC_APPOINT_QNUM_OR_SPr ,
-                       0,
-                       0,
-                       &appoint_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取car C指定队列模式的配置
-* @param   dev_id           设备号           car编号
-* @param   p_global_en      全局队列使能，0-不使能，1-使能
-* @param   p_sp_en          优先级队列使能，0-不使能，1-使能
-* @param   p_appoint_sp     指定的优先级
-* @param   p_appoint_queue  指定的队列号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/07
-************************************************************/
-DPP_STATUS dpp_stat_carc_queue_appoint_mode_get(ZXIC_UINT32 dev_id,
-                                                ZXIC_UINT32 *p_global_en,
-                                                ZXIC_UINT32 *p_sp_en,
-                                                ZXIC_UINT32 *p_appoint_sp,
-                                                ZXIC_UINT32 *p_appoint_queue)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    DPP_STAT_CAR0_CARC_APPOINT_QNUM_OR_SP_T appoint_cfg = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_global_en);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_sp_en);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_appoint_sp);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_appoint_queue);
-
-    rc = dpp_reg_read(dev_id,
-                      STAT_CAR0_CARC_APPOINT_QNUM_OR_SPr ,
-                      0,
-                      0,
-                      &appoint_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read");
-
-    *p_global_en = appoint_cfg.carc_appoint_qnum_or_not;
-    *p_sp_en = appoint_cfg.carc_appoint_sp_or_not;
-    *p_appoint_sp = appoint_cfg.carc_plcr_stat_sp;
-    *p_appoint_queue = appoint_cfg.carc_plcr_stat_qnum;
-
-    return rc;
-}
-
-/***********************************************************/
-/** car C 调试计数读取模式配置
-* @param   dev_id           设备号           car编号
-* @param   overflow_mode    溢出模式，0-计数最大保持，1-计数最大翻转
-* @param   rd_mode          读取模式，0-不读清，1-读清模式
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carc_dbg_cnt_mode_set(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 overflow_mode,
-                                          ZXIC_UINT32 rd_mode)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARC_CFGMT_COUNT_MODE_T cnt_mode_cfg = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, overflow_mode, CAR_KEEP_COUNT, CAR_RE_COUNT);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, rd_mode, CAR_READ_NOT_CLEAR, CAR_READ_AND_CLEAR);
-
-    cnt_mode_cfg.carc_cfgmt_count_overflow_mode = overflow_mode;
-    cnt_mode_cfg.carc_cfgmt_count_rd_mode = rd_mode;
-
-    rc = dpp_reg_write(dev_id,
-                       STAT_CAR0_CARC_CFGMT_COUNT_MODEr ,
-                       0,
-                       0,
-                       &cnt_mode_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** car C 调试计数读取模式获取
-* @param   dev_id           设备号           car编号
-* @param   p_overflow_mode  溢出模式，0-计数最大保持，1-计数最大翻转
-* @param   p_rd_mode        读清模式，0-不读清，1-读清模式
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carc_dbg_cnt_mode_get(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 *p_overflow_mode,
-                                          ZXIC_UINT32 *p_rd_mode)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARC_CFGMT_COUNT_MODE_T cnt_mode_cfg = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_overflow_mode);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rd_mode);
-
-    rc = dpp_reg_read(dev_id,
-                      STAT_CAR0_CARC_CFGMT_COUNT_MODEr ,
-                      0,
-                      0,
-                      &cnt_mode_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read");
-
-    *p_overflow_mode = cnt_mode_cfg.carc_cfgmt_count_overflow_mode;
-    *p_rd_mode = cnt_mode_cfg.carc_cfgmt_count_rd_mode;
-
-    return rc;
-}
-
-/***********************************************************/
-/** car b 的调试计数获取
-* @param   dev_id
-* @param   p_car_dbg_cnt
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/09/27
-************************************************************/
-DPP_STATUS dpp_stat_carc_dbg_cnt_get(ZXIC_UINT32 dev_id,
-                                     DPP_STAT_CAR_DBG_CNT_T *p_car_dbg_cnt)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 size = 0;
-    ZXIC_UINT32 *p_tmp_cnt = NULL;
-
-    DPP_STAT_CAR0_CARC_PKT_SIZE_CNT_T  carc_pkt_size_cnt_cfg = {0};
-    DPP_STAT_CAR0_CARC_PKT_DES_I_CNT_T carc_pkt_in_total_cnt_cfg = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_dbg_cnt);
-
-    size = sizeof(DPP_STAT_CAR_DBG_CNT_T) / sizeof(ZXIC_UINT32) - 1;
-    p_tmp_cnt = (ZXIC_UINT32 *)p_car_dbg_cnt;
-
-    for (i = 0; i < size; i++)
-    {
-        rc = dpp_reg_read(dev_id,
-                          STAT_CAR0_CARC_PKT_DES_I_CNTr + i,
-                          0,
-                          0,
-                          &carc_pkt_in_total_cnt_cfg);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read");
-
-        ZXIC_COMM_MEMCPY(p_tmp_cnt + i, &(carc_pkt_in_total_cnt_cfg.carc_pkt_des_i_cnt), sizeof(ZXIC_UINT32));
-    }
-
-    rc = dpp_reg_read(dev_id,
-                      STAT_CAR0_CARC_PKT_SIZE_CNTr,
-                      0,
-                      0,
-                      &carc_pkt_size_cnt_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read");
-
-    p_car_dbg_cnt->pkt_size_cnt = carc_pkt_size_cnt_cfg.carc_pkt_size_cnt;
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取car C的初始化状态
-* @param   dev_id           设备号           car编号
-* @param   p_init_done      初始化完成使能
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/06
-************************************************************/
-DPP_STATUS dpp_stat_carc_init_done_get(ZXIC_UINT32 dev_id,
-                                       ZXIC_UINT32 *p_init_done)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARC_PLCR_INIT_DONT_T carc_init_done_cfg = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_init_done);
-
-    rc = dpp_reg_read(dev_id,
-                      STAT_CAR0_CARC_PLCR_INIT_DONTr ,
-                      0,
-                      0,
-                      &carc_init_done_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read");
-
-    *p_init_done = carc_init_done_cfg.carc_plcr_init_done;
-
-    return rc;
-}
-
-#endif
-/***********************************************************/
-/** 
-* @param   dev_id      
-* @param   profile_id   
-* @param   p_random_ram   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  YXH      @date  2019/04/01
-************************************************************/
-DPP_STATUS dpp_stat_carc_random_ram_set(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 profile_id,
-                                        DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
-                                        DPP_CAR_RANDOM_RAM_T *p_random_ram_c)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT64 para0_temp = 0;
-    ZXIC_UINT64 para2_temp = 0;
-    ZXIC_UINT64 para4_temp = 0;
-    DPP_STAT_CAR0_CARC_RANDOM_RAM_T carc_random_ram_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p1, 0, 100);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p2, 0, 100);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p3, 0, 100);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p1, 0, 100);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p2, 0, 100);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p3, 0, 100);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_RANDOM_MAX);
-
-    para0_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->t2)) - ((ZXIC_UINT64)(p_random_ram_e->t1))) * ((ZXIC_UINT64)(p_random_ram_e->p1))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-    carc_random_ram_cfg.para0_l_e = (para0_temp & 0xFFFFFFFF);
-    carc_random_ram_cfg.para0_h_e = (para0_temp >> 32) & 0xFFFFFFFF;
-
-    carc_random_ram_cfg.para1_e = ((p_random_ram_e->p2 - p_random_ram_e->p1) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-
-    para2_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->t3)) - ((ZXIC_UINT64)(p_random_ram_e->t2))) * ((ZXIC_UINT64)(p_random_ram_e->p2))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-    carc_random_ram_cfg.para2_l_e = (para2_temp & 0xFFFFFFFF);
-    carc_random_ram_cfg.para2_h_e = (para2_temp >> 32) & 0xFFFFFFFF;
-
-    carc_random_ram_cfg.para3_e = ((p_random_ram_e->p3 - p_random_ram_e->p2) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-
-    para4_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->tc)) - ((ZXIC_UINT64)(p_random_ram_e->t3))) * ((ZXIC_UINT64)(p_random_ram_e->p3))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-    carc_random_ram_cfg.para4_l_e = (para4_temp & 0xFFFFFFFF);
-    carc_random_ram_cfg.para4_h_e = (para4_temp >> 32) & 0xFFFFFFFF;
-
-    carc_random_ram_cfg.para5_e = ((100 - p_random_ram_e->p3) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-    carc_random_ram_cfg.para6_e = p_random_ram_e->t1;
-    carc_random_ram_cfg.para7_e = p_random_ram_e->t2;
-    carc_random_ram_cfg.para8_e = p_random_ram_e->t3;
-
-	/* para0_temp = 0;
-	para2_temp = 0;
-	para4_temp = 0; */
-
-    para0_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->t2)) - ((ZXIC_UINT64)(p_random_ram_c->t1))) * ((ZXIC_UINT64)(p_random_ram_c->p1))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-    carc_random_ram_cfg.para0_l_c = (para0_temp & 0xFFFFFFFF);
-    carc_random_ram_cfg.para0_h_c = (para0_temp >> 32) & 0xFFFFFFFF;
-
-    carc_random_ram_cfg.para1_c = ((p_random_ram_c->p2 - p_random_ram_c->p1) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-
-    para2_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->t3)) - ((ZXIC_UINT64)(p_random_ram_c->t2))) * ((ZXIC_UINT64)(p_random_ram_c->p2))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-    carc_random_ram_cfg.para2_l_c = (para2_temp & 0xFFFFFFFF);
-    carc_random_ram_cfg.para2_h_c = (para2_temp >> 32) & 0xFFFFFFFF;
-
-    carc_random_ram_cfg.para3_c = ((p_random_ram_c->p3 - p_random_ram_c->p2) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-
-    para4_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->tc)) - ((ZXIC_UINT64)(p_random_ram_c->t3))) * ((ZXIC_UINT64)(p_random_ram_c->p3))) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-    carc_random_ram_cfg.para4_l_c = (para4_temp & 0xFFFFFFFF);
-    carc_random_ram_cfg.para4_h_c = (para4_temp >> 32) & 0xFFFFFFFF;
-
-    carc_random_ram_cfg.para5_c = ((100 - p_random_ram_c->p3) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
-    carc_random_ram_cfg.para6_c = p_random_ram_c->t1;
-    carc_random_ram_cfg.para7_c = p_random_ram_c->t2;
-    carc_random_ram_cfg.para8_c = p_random_ram_c->t3;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_CARC_RANDOM_RAMr ,
-                       0,
-                       profile_id,
-                       &carc_random_ram_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** 
-* @param   dev_id   
-* @param   p_random_ram   
-*
-* @return  
-* @remark  无
-* @see     
-* @author  YXH      @date  2019/04/01
-************************************************************/
-DPP_STATUS dpp_stat_carc_random_ram_get(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 profile_id,
-                                        DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
-                                        DPP_CAR_RANDOM_RAM_T *p_random_ram_c)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CARB_RANDOM_RAM_T carc_random_ram_cfg = {0};
-    ZXIC_UINT32 tmp_val = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_RANDOM_MAX);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_CARC_RANDOM_RAMr ,
-                      0,
-                      profile_id,
-                      &carc_random_ram_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    p_random_ram_e->t1 = carc_random_ram_cfg.para6_e;
-    p_random_ram_e->t2 = carc_random_ram_cfg.para7_e;
-    p_random_ram_e->t3 = carc_random_ram_cfg.para8_e;
-    tmp_val = (carc_random_ram_cfg.para5_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
-    p_random_ram_e->p3 = 100 - tmp_val;
-    tmp_val = (carc_random_ram_cfg.para3_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
-    p_random_ram_e->p2 = p_random_ram_e->p3 - tmp_val;
-    tmp_val = (carc_random_ram_cfg.para1_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
-    p_random_ram_e->p1 = p_random_ram_e->p2 - tmp_val;
-
-    p_random_ram_c->t1 = carc_random_ram_cfg.para6_c;
-    p_random_ram_c->t2 = carc_random_ram_cfg.para7_c;
-    p_random_ram_c->t3 = carc_random_ram_cfg.para8_c;
-    tmp_val = (carc_random_ram_cfg.para5_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
-    p_random_ram_c->p3 = 100 - tmp_val;
-    tmp_val = (carc_random_ram_cfg.para3_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
-    p_random_ram_c->p2 = p_random_ram_c->p3 - tmp_val;
-    tmp_val = (carc_random_ram_cfg.para1_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
-    p_random_ram_c->p1 = p_random_ram_c->p2 - tmp_val;
-
-    return rc;
-}
-
-/***********************************************************/
-/** 配置car的层级模式
-* @param   dev_id
-* @param   mode   2 - 三级car, 第一级支持16K
-*                 1 - 两级car, 第一级扩展为17K
-*                 0 - 一级car, 第一级扩展为21K
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/09/28
-************************************************************/
-DPP_STATUS dpp_stat_car_en_mode_set(DPP_DEV_T *dev, ZXIC_UINT32 mode)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CAR_HIERARCHY_MODE_T car_en_mode_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), mode, DPP_CAR_EN_MODE_BOTH_EN, DPP_CAR_EN_MODE_INVALID - 1);
-
-    car_en_mode_cfg.car_hierarchy_mode = mode;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_CAR_HIERARCHY_MODEr ,
-                       0,
-                       0,
-                       &car_en_mode_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/**
-* @param   dev_id
-* @param   p_mode
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/09/28
-************************************************************/
-DPP_STATUS dpp_stat_car_en_mode_get(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 *p_mode)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_CAR_HIERARCHY_MODE_T car_en_mode_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mode);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_CAR_HIERARCHY_MODEr ,
-                      0,
-                      0,
-                      &car_en_mode_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_mode = car_en_mode_cfg.car_hierarchy_mode;
-
-    return rc;
-}
-
-/***********************************************************/
-/** 配置car的包长偏移
-* @param   dev_id
-* @param   pkt_size_off
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_car_pkt_size_offset_set(DPP_DEV_T *dev,
-                                            ZXIC_UINT32 pkt_size_off)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_PKT_SIZE_OFFSET_T car_pkt_size_offset = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pkt_size_off, 0, 0xffffffff);
-
-    car_pkt_size_offset.pkt_size_offset = pkt_size_off;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_PKT_SIZE_OFFSETr,
-                       0,
-                       0,
-                       &car_pkt_size_offset);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取car的包长偏移
-* @param   dev_id
-* @param   p_pkt_size_off
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_car_pkt_size_offset_get(DPP_DEV_T *dev,
-                                            ZXIC_UINT32 *p_pkt_size_off)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_PKT_SIZE_OFFSET_T car_pkt_size_offset = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_pkt_size_off);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_PKT_SIZE_OFFSETr,
-                      0,
-                      0,
-                      &car_pkt_size_offset);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_pkt_size_off = car_pkt_size_offset.pkt_size_offset;
-
-    return rc;
-}
-
-/***********************************************************/
-/** 配置cara的最大包长
-* @param   dev_id
-* @param   max_pkt_size
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_cara_max_pkt_size_set(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 max_pkt_size)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_MAX_PKT_SIZE_A_T car_max_pkt_size = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), max_pkt_size, 0, 0x3fff);
-
-    car_max_pkt_size.max_pkt_size_a = max_pkt_size;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_MAX_PKT_SIZE_Ar ,
-                       0,
-                       0,
-                       &car_max_pkt_size);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取cara的最大包长
-* @param   dev_id
-* @param   p_max_pkt_size
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_cara_max_pkt_size_get(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 *p_max_pkt_size)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_MAX_PKT_SIZE_A_T car_max_pkt_size = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_max_pkt_size);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_MAX_PKT_SIZE_Ar ,
-                      0,
-                      0,
-                      &car_max_pkt_size);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_max_pkt_size = car_max_pkt_size.max_pkt_size_a;
-
-    return rc;
-}
-
-/***********************************************************/
-/** 配置carb的最大包长
-* @param   dev_id
-* @param   max_pkt_size
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_carb_max_pkt_size_set(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 max_pkt_size)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_MAX_PKT_SIZE_B_T car_max_pkt_size = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), max_pkt_size, 0, 0x3fff);
-
-    car_max_pkt_size.max_pkt_size_b = max_pkt_size;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_MAX_PKT_SIZE_Br,
-                       0,
-                       0,
-                       &car_max_pkt_size);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取carb的最大包长
-* @param   dev_id
-* @param   p_max_pkt_size
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_carb_max_pkt_size_get(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 *p_max_pkt_size)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_MAX_PKT_SIZE_B_T car_max_pkt_size = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_max_pkt_size);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_MAX_PKT_SIZE_Br,
-                      0,
-                      0,
-                      &car_max_pkt_size);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_max_pkt_size = car_max_pkt_size.max_pkt_size_b;
-
-    return rc;
-}
-
-/***********************************************************/
-/** 配置carc的最大包长
-* @param   dev_id
-* @param   max_pkt_size
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_carc_max_pkt_size_set(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 max_pkt_size)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_MAX_PKT_SIZE_C_T car_max_pkt_size = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), max_pkt_size, 0, 0x3fff);
-
-    car_max_pkt_size.max_pkt_size_c = max_pkt_size;
-
-    rc = dpp_reg_write(dev,
-                       STAT_CAR0_MAX_PKT_SIZE_Cr ,
-                       0,
-                       0,
-                       &car_max_pkt_size);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取carc的最大包长
-* @param   dev_id
-* @param   p_max_pkt_size
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_carc_max_pkt_size_get(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 *p_max_pkt_size)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR0_MAX_PKT_SIZE_C_T car_max_pkt_size = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_max_pkt_size);
-
-    rc = dpp_reg_read(dev,
-                      STAT_CAR0_MAX_PKT_SIZE_Cr,
-                      0,
-                      0,
-                      &car_max_pkt_size);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_max_pkt_size = car_max_pkt_size.max_pkt_size_c;
-
-    return rc;
-}
-
-#endif
-
-#if ZXIC_REAL("Advanced Function")
-#if 0
-/***********************************************************/
-/** car硬件初始化
-* @param   dev_id        设备号        car编号
-* @param   car_type      car模式，参见STAT_CAR_TYPE_E
-* @param   car_mono_mode car独占mono模式
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/04/27
-************************************************************/
-DPP_STATUS dpp_stat_car_hardware_init(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 car_type,
-                                      ZXIC_UINT32 car_mono_mode)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 init_done = 0;
-
-    DPP_STAT_CAR_A_QUEUE_CFG_T car_a_queue_cfg = {0};
-    DPP_STAT_CAR_B_QUEUE_CFG_T car_b_queue_cfg = {0};
-    DPP_STAT_CAR_C_QUEUE_CFG_T car_c_queue_cfg = {0};
-    DPP_STAT_CAR_PROFILE_CFG_T car_profile_cfg = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, car_mono_mode, CAR_SMMU0_MONO_MODE_NONE, CAR_SMMU0_MONO_MODE_MAX - 1);
-
-    ZXIC_COMM_MEMSET(&car_profile_cfg, 0, sizeof(DPP_STAT_CAR_PROFILE_CFG_T));
-
-    rc = dpp_se_smmu0_cfg_car_mono_set(dev_id, car_mono_mode);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_smmu0_cfg_car_mono_set");
-
-    switch (car_type)
-    {
-        case STAT_CAR_A_TYPE:
-        {
-            rc = dpp_stat_cara_init_done_get(dev_id, &init_done);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_cara_init_done_get");
-
-            if (0 == init_done)
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error! Get car_a init done fail!\n");
-                return DPP_RC_CAR_INIT_FAIL;
-            }
-
-            ZXIC_COMM_MEMSET(&car_a_queue_cfg, 0, sizeof(DPP_STAT_CAR_A_QUEUE_CFG_T));
-
-            /** 清空queue的配置 和绑定队列号配置 稍后补全 */
-            for (i = 0; i <= DPP_CAR_A_FLOW_ID_MAX; i++)
-            {
-                rc = dpp_stat_cara_queue_cfg_set(dev_id,
-                                                 i,
-                                                 0,
-                                                 0,
-                                                 0);
-                ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_cara_queue_cfg_set");
-            }
-
-            /** 清空profile的配置 */
-            for (i = 0; i <= DPP_CAR_A_PROFILE_ID_MAX; i++)
-            {
-                rc = dpp_stat_cara_profile_cfg_set(dev_id,
-                                                   i,
-                                                   &car_profile_cfg);
-                ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_cara_profile_cfg_set");
-            }
-        }
-        break;
-
-        case STAT_CAR_B_TYPE:
-        {
-            rc = dpp_stat_carb_init_done_get(dev_id, &init_done);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carb_init_done_get");
-
-            if (0 == init_done)
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error! Get car_b init done fail!\n");
-                return DPP_RC_CAR_INIT_FAIL;
-            }
-
-            ZXIC_COMM_MEMSET(&car_b_queue_cfg, 0, sizeof(DPP_STAT_CAR_B_QUEUE_CFG_T));
-
-            /** 清空queue的配置 和绑定队列号配置 稍后补全 */
-
-            for (i = 0; i <= DPP_CAR_B_FLOW_ID_MAX; i++)
-            {
-                rc = dpp_stat_carb_queue_cfg_set(dev_id,
-                                                 i,
-                                                 0,
-                                                 0,
-                                                 0);
-                ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_cara_queue_cfg_set");
-            }
-
-            /** 清空profile的配置 */
-            for (i = 0; i <= DPP_CAR_B_PROFILE_ID_MAX; i++)
-            {
-                rc = dpp_stat_carb_profile_cfg_set(dev_id,
-                                                   i,
-                                                   &car_profile_cfg);
-                ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carb_profile_cfg_set");
-            }
-        }
-        break;
-
-        case STAT_CAR_C_TYPE:
-        {
-            rc = dpp_stat_carc_init_done_get(dev_id,
-                                             &init_done);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carc_init_done_get");
-
-            if (0 == init_done)
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error! Get car_c init done fail!\n");
-                return DPP_RC_CAR_INIT_FAIL;
-            }
-
-            ZXIC_COMM_MEMSET(&car_c_queue_cfg, 0, sizeof(DPP_STAT_CAR_C_QUEUE_CFG_T));
-
-            /** 清空queue的配置 和绑定队列号配置 稍后补全 */
-
-            for (i = 0; i <= DPP_CAR_C_FLOW_ID_MAX; i++)
-            {
-                rc = dpp_stat_carc_queue_cfg_set(dev_id,
-                                                 i,
-                                                 0,
-                                                 0,
-                                                 0);
-                ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carc_queue_cfg_set");
-            }
-
-            /** 清空profile的配置 */
-            for (i = 0; i <= DPP_CAR_C_PROFILE_ID_MAX; i++)
-            {
-                rc = dpp_stat_carc_profile_cfg_set(dev_id,
-                                                   i,
-                                                   &car_profile_cfg);
-                ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carc_profile_cfg_set");
-            }
-        }
-        break;
-
-        default:
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "car_type[%d] error!\n", car_type);
-            return DPP_ERR;
-        }
-    }
-
-    return rc;
-}
-#endif
-/***********************************************************/
-/** car 模块流配置
-* @param   dev_id       设备号
-* @param   car_type     car模式，参见STAT_CAR_TYPE_E
-* @param   flow_id      队列号
-* @param   drop_flag    丢弃标志
-* @param   plcr_en      限速使能
-* @param   profile_id   模板编号
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/05/06
-************************************************************/
-DPP_STATUS dpp_stat_car_queue_cfg_set(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 car_type,
-                                      ZXIC_UINT32 flow_id,
-                                      ZXIC_UINT32 drop_flag,
-                                      ZXIC_UINT32 plcr_en,
-                                      ZXIC_UINT32 profile_id)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 flow_num = 0;
-
-    DPP_CAR_SOFT_RESET_DATA_T *p_restore_data = NULL; /* 软复位相关 */
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1);
-
-    if (STAT_CAR_A_TYPE == car_type)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX);
-    }
-    else if (STAT_CAR_B_TYPE == car_type)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_MAX);
-    }
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX);
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_MAX);
-    }
-
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), drop_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), plcr_en, 0, 1);
-
-    p_restore_data = GET_DPP_CAR_SOFT_RESET_INFO(DEV_ID(dev)); /* 软复位相关 */
-
-    switch (car_type)
-    {
-        case STAT_CAR_A_TYPE:
-        {
-            rc = dpp_stat_cara_queue_cfg_set(dev,
-                                             flow_id,
-                                             drop_flag,
-                                             plcr_en,
-                                             profile_id);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_queue_cfg_set");
-
-            /* 软复位相关 */
-            flow_num = p_restore_data->cara_flow_num;
-            p_restore_data->cara_item[flow_num].flow_id = flow_id;
-            p_restore_data->cara_item[flow_num].profile_id = profile_id;
-            ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW(DEV_ID(dev), p_restore_data->cara_flow_num, 1);
-            p_restore_data->cara_flow_num++;
-        }
-        break;
-
-        case STAT_CAR_B_TYPE:
-        {
-            rc = dpp_stat_carb_queue_cfg_set(dev,
-                                             flow_id,
-                                             drop_flag,
-                                             plcr_en,
-                                             profile_id);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_queue_cfg_set");
-
-            /* 软复位相关 */
-            flow_num = p_restore_data->carb_flow_num;
-            p_restore_data->carb_item[flow_num].flow_id = flow_id;
-            p_restore_data->carb_item[flow_num].profile_id = profile_id;
-            ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW(DEV_ID(dev), p_restore_data->carb_flow_num, 1);
-            p_restore_data->carb_flow_num++;
-        }
-        break;
-
-        case STAT_CAR_C_TYPE:
-        {
-            rc = dpp_stat_carc_queue_cfg_set(dev,
-                                             flow_id,
-                                             drop_flag,
-                                             plcr_en,
-                                             profile_id);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_queue_cfg_set");
-
-            /* 软复位相关 */
-            flow_num = p_restore_data->carc_flow_num;
-            p_restore_data->carc_item[flow_num].flow_id = flow_id;
-            p_restore_data->carc_item[flow_num].profile_id = profile_id;
-            ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), p_restore_data->carc_flow_num, 1);
-            p_restore_data->carc_flow_num++;
-        }
-        break;
-    }
-
-    return rc;
-}
-
-/***********************************************************/
-/**队列设置参数获取
-* @param   dev_id   设备号   car编号
-* @param   car_type car模式，参见STAT_CAR_TYPE_E
-* @param   pkt_sign 限速标志，1-包限速，0-字节限速
-* @param   flow_id  队列号
-* @param   p_data   获取队列配置信息
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/09/27
-************************************************************/
-DPP_STATUS dpp_stat_car_queue_get(DPP_DEV_T *dev,
-                                  ZXIC_UINT32 car_type,
-                                  ZXIC_UINT32 pkt_sign,
-                                  ZXIC_UINT32 flow_id,
-                                  ZXIC_VOID *p_data)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1);
-
-    if (STAT_CAR_A_TYPE == car_type)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pkt_sign, 0, 1);
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
-    }
-    else if (STAT_CAR_B_TYPE == car_type)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
-    }
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX);
-    }
-
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-
-    switch (car_type)
-    {
-        case STAT_CAR_A_TYPE:
-        {
-            if (0 == pkt_sign)
-            {
-                rc = dpp_stat_cara_queue_cfg_get(dev,
-                                                 flow_id,
-                                                 (DPP_STAT_CAR_A_QUEUE_CFG_T *)p_data);
-                ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_queue_cfg_get");
-            }
-            else
-            {
-                rc = dpp_stat_cara_pkt_queue_cfg_get(dev,
-                                                     flow_id,
-                                                     (DPP_STAT_CAR_A_PKT_QUEUE_CFG_T *) p_data);
-                ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_pkt_queue_cfg_get");
-            }
-
-        }
-        break;
-
-        case STAT_CAR_B_TYPE:
-        {
-            rc = dpp_stat_carb_queue_cfg_get(dev,
-                                             flow_id,
-                                             (DPP_STAT_CAR_B_QUEUE_CFG_T *)p_data);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_queue_cfg_get");
-        }
-        break;
-
-        case STAT_CAR_C_TYPE:
-        {
-            rc = dpp_stat_carc_queue_cfg_get(dev,
-                                             flow_id,
-                                             (DPP_STAT_CAR_C_QUEUE_CFG_T *)p_data);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_queue_cfg_get");
-        }
-        break;
-    }
-
-    return rc;
-}
-
-/***********************************************************/
-/** car 模块流配置获取
-* @param   dev_id       设备号
-* @param   car_type     car模式，参见STAT_CAR_TYPE_E
-* @param   flow_id      队列号
-* @param   p_drop_flag  drop标记
-* @param   p_plcr_en    监管使能信号
-* @param   p_profile_id 模板id
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/08/19
-************************************************************/
-DPP_STATUS dpp_stat_car_queue_cfg_get(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 car_type,
-                                      ZXIC_UINT32 flow_id,
-                                      ZXIC_UINT32 *p_drop_flag,
-                                      ZXIC_UINT32 *p_plcr_en,
-                                      ZXIC_UINT32 *p_profile_id)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR_A_QUEUE_CFG_T car_a_queue_cfg = {0};
-    DPP_STAT_CAR_B_QUEUE_CFG_T car_b_queue_cfg = {0};
-    DPP_STAT_CAR_C_QUEUE_CFG_T car_c_queue_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1);
-
-    if (STAT_CAR_A_TYPE == car_type)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
-    }
-    else if (STAT_CAR_B_TYPE == car_type)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
-    }
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX);
-    }
-
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_drop_flag);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_plcr_en);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_profile_id);
-
-    switch (car_type)
-    {
-        case STAT_CAR_A_TYPE:
-        {
-            rc = dpp_stat_cara_queue_cfg_get(dev,
-                                             flow_id,
-                                             &car_a_queue_cfg);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_queue_cfg_get");
-
-            *p_profile_id = car_a_queue_cfg.profile_id;
-            *p_plcr_en    = car_a_queue_cfg.plcr_en;
-            *p_drop_flag  = car_a_queue_cfg.drop_flag;
-        }
-        break;
-
-        case STAT_CAR_B_TYPE:
-        {
-            rc = dpp_stat_carb_queue_cfg_get(dev,
-                                             flow_id,
-                                             &car_b_queue_cfg);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_queue_cfg_get");
-
-            *p_profile_id = car_b_queue_cfg.profile_id;
-            *p_plcr_en    = car_b_queue_cfg.plcr_en;
-            *p_drop_flag  = car_b_queue_cfg.drop_flag;
-        }
-        break;
-
-        case STAT_CAR_C_TYPE:
-        {
-            rc = dpp_stat_carc_queue_cfg_get(dev,
-                                             flow_id,
-                                             &car_c_queue_cfg);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_queue_cfg_get");
-
-            *p_profile_id = car_c_queue_cfg.profile_id;
-            *p_plcr_en    = car_c_queue_cfg.plcr_en;
-            *p_drop_flag  = car_c_queue_cfg.drop_flag;
-        }
-        break;
-    }
-
-    return rc;
-}
-
-/***********************************************************/
-/** car profile硬件写入
-* @param   dev_id               设备号               car编号
-* @param   car_type             car模式，参见STAT_CAR_TYPE_E
-* @param   pkt_sign             限速模式，1-包限速，0-字节限速
-* @param   profile_id           模板号
-* @param   p_car_profile_cfg    模板配置信息
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/05/06
-************************************************************/
-DPP_STATUS dpp_stat_car_profile_cfg_set(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 car_type,
-                                        ZXIC_UINT32 pkt_sign,
-                                        ZXIC_UINT32 profile_id,
-                                        ZXIC_VOID *p_car_profile_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    DPP_CAR_SOFT_RESET_DATA_T *p_restore_data = NULL; /* 软复位相关 */
-    DPP_STAT_CAR_PROFILE_CFG_T *p_stat_car_profile_cfg = NULL;
-    DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_stat_pkt_car_profile_cfg = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pkt_sign, 0, 1);
-
-    if (STAT_CAR_A_TYPE == car_type)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX);
-    }
-    else if (STAT_CAR_B_TYPE == car_type)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_MAX);
-    }
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_MAX);
-    }
-
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_car_profile_cfg);
-
-    p_restore_data = GET_DPP_CAR_SOFT_RESET_INFO(DEV_ID(dev)); /* 软复位相关 */
-
-    if ((STAT_CAR_A_TYPE == car_type) && (1 == pkt_sign))
-    {
-        p_stat_pkt_car_profile_cfg = (DPP_STAT_CAR_PKT_PROFILE_CFG_T *)p_car_profile_cfg;
-
-        rc = dpp_stat_cara_pkt_profile_cfg_set(dev,
-                                               profile_id,
-                                               p_stat_pkt_car_profile_cfg);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_pkt_profile_cfg_set");
-
-        /* 软复位相关 */
-        p_restore_data->car_pkt_sign[profile_id] = ZXIC_TRUE;
-
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), p_restore_data->car0_pkt_num, 1);
-        p_restore_data->car0_pkt_num++;
-    }
-    else
-    {
-        p_stat_car_profile_cfg = (DPP_STAT_CAR_PROFILE_CFG_T *)p_car_profile_cfg;
-        ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "==> dpp_stat_car_profile_cfg_set : \n");
-        ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| %-10s | %-10s | %-10s | %-10s | \n", "profile_id", "car_id", "car_type", "pkt_sign");
-        ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| %-10d | %-10d | %-10d | 0x%-8x | \n", profile_id, 0, car_type, pkt_sign);
-        ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| ------------------------------------------------- | \n");
-        ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| %-5s | %-5s | %-5s | %-10s | %-10s | %-10s | %-10s | \n", "cd", "cf", "cm", "cir", "cbs", "eir", "ebs");
-        ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "| %-5d | %-5d | %-5d | %-10d | %-10d | %-10d | %-10d | \n", p_stat_car_profile_cfg->cd,
-                                                                                                       p_stat_car_profile_cfg->cf,
-                                                                                                       p_stat_car_profile_cfg->cm,
-                                                                                                       p_stat_car_profile_cfg->cir,
-                                                                                                       p_stat_car_profile_cfg->cbs,
-                                                                                                       p_stat_car_profile_cfg->eir,
-                                                                                                       p_stat_car_profile_cfg->ebs);
-
-        if (STAT_CAR_A_TYPE == car_type)
-        {
-            rc = dpp_stat_cara_profile_cfg_set(dev,
-                                               profile_id,
-                                               p_stat_car_profile_cfg);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_profile_cfg_set");
-
-            /* 软复位相关 */
-            if (ZXIC_TRUE == p_restore_data->car_pkt_sign[profile_id])
-            {
-                p_restore_data->car0_pkt_num--;
-                p_restore_data->car_pkt_sign[profile_id] = ZXIC_FALSE;
-            }
-        }
-        else if (STAT_CAR_B_TYPE == car_type)
-        {
-            rc = dpp_stat_carb_profile_cfg_set(dev,
-                                               profile_id,
-                                               p_stat_car_profile_cfg);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_profile_cfg_set");
-        }
-        else
-        {
-            rc = dpp_stat_carc_profile_cfg_set(dev,
-                                               profile_id,
-                                               p_stat_car_profile_cfg);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_profile_cfg_set");
-        }
-    }
-
-    return rc;
-
-}
-
-/***********************************************************/
-/**获取监管模板配置
-* @param   dev_id               设备号
-* @param   car_type             car模式类型，参见STAT_CAR_TYPE_E
-* @param   pkt_sign             限速模式，1-包限速，0-字节限速
-* @param   profile_id           监管模板id
-* @param   p_car_profile_cfg    模板配置信息
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/08/29
-************************************************************/
-DPP_STATUS dpp_stat_car_profile_cfg_get(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 car_type,
-                                        ZXIC_UINT32 pkt_sign,
-                                        ZXIC_UINT32 profile_id,
-                                        ZXIC_VOID *p_car_profile_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_CAR_PROFILE_CFG_T *p_stat_car_profile_cfg = NULL;
-    DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_stat_pkt_car_profile_cfg = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pkt_sign, 0, 1);
-
-    if (STAT_CAR_A_TYPE == car_type)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_A_PROFILE_ID_MAX);
-    }
-    else if (STAT_CAR_B_TYPE == car_type)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_MAX);
-    }
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_MAX);
-    }
-
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_car_profile_cfg);
-
-    if ((STAT_CAR_A_TYPE == car_type) && (1 == pkt_sign))
-    {
-        p_stat_pkt_car_profile_cfg = (DPP_STAT_CAR_PKT_PROFILE_CFG_T *)p_car_profile_cfg;
-        rc = dpp_stat_cara_pkt_profile_cfg_get(dev,
-                                               profile_id,
-                                               p_stat_pkt_car_profile_cfg);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_pkt_profile_cfg_get");
-    }
-    else
-    {
-        p_stat_car_profile_cfg = (DPP_STAT_CAR_PROFILE_CFG_T *)p_car_profile_cfg;
-
-        if (STAT_CAR_A_TYPE == car_type)
-        {
-            rc = dpp_stat_cara_profile_cfg_get(dev,
-                                               profile_id,
-                                               p_stat_car_profile_cfg);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_profile_cfg_get");
-        }
-        else if (STAT_CAR_B_TYPE == car_type)
-        {
-            rc = dpp_stat_carb_profile_cfg_get(dev,
-                                               profile_id,
-                                               p_stat_car_profile_cfg);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_profile_cfg_get");
-        }
-        else
-        {
-            rc = dpp_stat_carc_profile_cfg_get(dev,
-                                               profile_id,
-                                               p_stat_car_profile_cfg);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_profile_cfg_get");
-        }
-    }
-
-    return rc;
-}
-
-/***********************************************************/
-/** car 队列映射关系配置
-* @param   dev_id       设备号
-* @param   car_type     car模式类型，参见STAT_CAR_TYPE_E
-* @param   flow_id      队列号
-* @param   map_flow_id  映射队列号
-* @param   map_sp       映射sp
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/09/27
-************************************************************/
-DPP_STATUS dpp_stat_car_queue_map_set(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 car_type,
-                                      ZXIC_UINT32 flow_id,
-                                      ZXIC_UINT32 map_flow_id,
-                                      ZXIC_UINT32 map_sp)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_B_TYPE);
-
-    if (STAT_CAR_A_TYPE == car_type)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_sp, DPP_CAR_PRI0, DPP_CAR_PRI_MAX - 1);
-        rc = dpp_stat_cara_queue_map_set(dev,
-                                         flow_id,
-                                         map_flow_id,
-                                         map_sp);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_queue_map_set");
-    }
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_flow_id, 0, DPP_CAR_C_FLOW_ID_MAX);
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_sp, DPP_CAR_PRI0, DPP_CAR_PRI_MAX - 1);
-        rc = dpp_stat_carb_queue_map_set(dev,
-                                         flow_id,
-                                         map_flow_id,
-                                         map_sp);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_queue_map_set");
-    }
-
-    return rc;
-}
-
-/***********************************************************/
-/** 获取 car 流号的绑定关系
-* @param   dev_id         设备号
-* @param   car_type       car模式类型，参见STAT_CAR_TYPE_E
-* @param   flow_id        队列号
-* @param   p_map_flow_id  映射队列号
-* @param   p_map_sp       映射sp
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/09/27
-************************************************************/
-DPP_STATUS dpp_stat_car_queue_map_get(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 car_type,
-                                      ZXIC_UINT32 flow_id,
-                                      ZXIC_UINT32 *p_map_flow_id,
-                                      ZXIC_UINT32 *p_map_sp)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_B_TYPE);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_flow_id);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_sp);
-
-    if (STAT_CAR_A_TYPE == car_type)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
-        rc = dpp_stat_cara_queue_map_get(dev,
-                                         flow_id,
-                                         p_map_flow_id,
-                                         p_map_sp);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_queue_map_get");
-    }
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
-        rc = dpp_stat_carb_queue_map_get(dev,
-                                         flow_id,
-                                         p_map_flow_id,
-                                         p_map_sp);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_queue_map_get");
-    }
-
-    return rc;
-}
-
-/***********************************************************/
-/** 
-* @param   dev_id         设备ID
-* @param   profile_id     模板ID
-* @param   p_random_ram_e E桶概率丢弃配置参数
-* @param   p_random_ram_c C桶概率丢弃配置参数
-*
-* @return  
-* @remark  无
-* @see     
-* @author  YXH      @date  2019/04/01
-************************************************************/
-DPP_STATUS dpp_stat_car_random_ram_set(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 car_type,
-                                       ZXIC_UINT32 profile_id,
-                                       DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
-                                       DPP_CAR_RANDOM_RAM_T *p_random_ram_c)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_B_TYPE, STAT_CAR_C_TYPE);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c);
-
-    if (STAT_CAR_B_TYPE == car_type)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_RANDOM_MAX);
-        rc = dpp_stat_carb_random_ram_set(dev,
-                                          profile_id,
-                                          p_random_ram_e,
-                                          p_random_ram_c);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_random_ram_set");
-    }
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_RANDOM_MAX);
-        rc = dpp_stat_carc_random_ram_set(dev,
-                                          profile_id,
-                                          p_random_ram_e,
-                                          p_random_ram_c);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_random_ram_set");
-    }
-
-    return rc;
-}
-
-/***********************************************************/
-/** 
-* @param   dev_id         设备ID
-* @param   profile_id     模板ID
-* @param   p_random_ram_e E桶概率丢弃配置参数
-* @param   p_random_ram_c C桶概率丢弃配置参数
-*
-* @return  
-* @remark  无
-* @see     
-* @author  YXH      @date  2019/04/01
-************************************************************/
-DPP_STATUS dpp_stat_car_random_ram_get(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 car_type,
-                                       ZXIC_UINT32 profile_id,
-                                       DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
-                                       DPP_CAR_RANDOM_RAM_T *p_random_ram_c)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_B_TYPE, STAT_CAR_C_TYPE);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c);
-
-    if (STAT_CAR_B_TYPE == car_type)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_B_PROFILE_ID_RANDOM_MAX);
-        rc = dpp_stat_carb_random_ram_get(dev,
-                                          profile_id,
-                                          p_random_ram_e,
-                                          p_random_ram_c);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_random_ram_get");
-    }
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0, DPP_CAR_C_PROFILE_ID_RANDOM_MAX);
-        rc = dpp_stat_carc_random_ram_get(dev,
-                                          profile_id,
-                                          p_random_ram_e,
-                                          p_random_ram_c);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_random_ram_get");
-    }
-
-    return rc;
-}
-
-#if 0
-/***********************************************************/
-/**car模块dbg计数模式设置
-* @param   dev_id           设备号
-* @param   car_type         car模式类型，参见STAT_CAR_TYPE_E
-* @param   overflow_mode    溢出模式，0-计数最大保持，1-计数最大翻转
-* @param   rd_mode          读取模式，0-不读清，1-读清模式
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/09/27
-************************************************************/
-DPP_STATUS dpp_stat_car_dbg_cnt_mode_set(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 car_type,
-                                         ZXIC_UINT32 overflow_mode,
-                                         ZXIC_UINT32 rd_mode)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, overflow_mode, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, rd_mode, 0, 1);
-
-    switch (car_type)
-    {
-        case STAT_CAR_A_TYPE:
-        {
-            rc = dpp_stat_cara_dbg_cnt_mode_set(dev_id,
-                                                overflow_mode,
-                                                rd_mode);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_cara_dbg_cnt_mode_set");
-        }
-        break;
-
-        case STAT_CAR_B_TYPE:
-        {
-            rc = dpp_stat_carb_dbg_cnt_mode_set(dev_id,
-                                                overflow_mode,
-                                                rd_mode);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carb_dbg_cnt_mode_set");
-        }
-        break;
-
-        case STAT_CAR_C_TYPE:
-        {
-            rc = dpp_stat_carc_dbg_cnt_mode_set(dev_id,
-                                                overflow_mode,
-                                                rd_mode);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carc_dbg_cnt_mode_set");
-        }
-        break;
-    }
-
-    return rc;
-}
-
-/***********************************************************/
-/**car模块dbg计数模式获取
-* @param   dev_id             设备号
-* @param   car_type           car模式类型，参见STAT_CAR_TYPE_E
-* @param   p_overflow_mode    溢出模式，0-计数最大保持，1-计数最大翻转
-* @param   p_rd_mode          读取模式，0-不读清，1-读清模式
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/09/27
-************************************************************/
-DPP_STATUS dpp_stat_car_dbg_cnt_mode_get(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 car_type,
-                                         ZXIC_UINT32 *p_overflow_mode,
-                                         ZXIC_UINT32 *p_rd_mode)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_overflow_mode);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rd_mode);
-
-    switch (car_type)
-    {
-        case STAT_CAR_A_TYPE:
-        {
-            rc = dpp_stat_cara_dbg_cnt_mode_get(dev_id,
-                                                p_overflow_mode,
-                                                p_rd_mode);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_cara_dbg_cnt_mode_get");
-        }
-        break;
-
-        case STAT_CAR_B_TYPE:
-        {
-            rc = dpp_stat_carb_dbg_cnt_mode_get(dev_id,
-                                                p_overflow_mode,
-                                                p_rd_mode);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carb_dbg_cnt_mode_get");
-        }
-        break;
-
-        case STAT_CAR_C_TYPE:
-        {
-            rc = dpp_stat_carc_dbg_cnt_mode_get(dev_id,
-                                                p_overflow_mode,
-                                                p_rd_mode);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carc_dbg_cnt_mode_get");
-        }
-        break;
-    }
-
-    return rc;
-}
-
-/***********************************************************/
-/** car 模块调试计数 获取
-* @param   dev_id          设备号
-* @param   car_type        car模式类型，参见STAT_CAR_TYPE_E
-* @param   p_car_dbg_cnt   dbg计数信息
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/09/27
-************************************************************/
-DPP_STATUS dpp_stat_car_dbg_cnt_get(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 car_type,
-                                    DPP_STAT_CAR_DBG_CNT_T *p_car_dbg_cnt)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_dbg_cnt);
-
-    switch (car_type)
-    {
-        case STAT_CAR_A_TYPE:
-        {
-            rc = dpp_stat_cara_dbg_cnt_get(dev_id,
-                                           p_car_dbg_cnt);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_cara_dbg_cnt_get");
-        }
-        break;
-
-        case STAT_CAR_B_TYPE:
-        {
-            rc = dpp_stat_carb_dbg_cnt_get(dev_id,
-                                           p_car_dbg_cnt);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carb_dbg_cnt_get");
-        }
-        break;
-
-        case STAT_CAR_C_TYPE:
-        {
-            rc = dpp_stat_carc_dbg_cnt_get(dev_id,
-                                           p_car_dbg_cnt);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_carc_dbg_cnt_get");
-        }
-        break;
-    }
-
-    return rc;
-}
-#endif
-/***********************************************************/
-/** 获取最大包长
-* @param   dev_id
-* @param   car_type
-* @param   p_max_pkt_len
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_car_max_pkt_size_get(DPP_DEV_T *dev,
-                                         ZXIC_UINT32 car_type,
-                                         ZXIC_UINT32 *p_max_pkt_len)
-{
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 pkt_len = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_max_pkt_len);
-
-    switch (car_type)
-    {
-        case STAT_CAR_A_TYPE:
-        {
-            rc = dpp_stat_cara_max_pkt_size_get(dev,
-                                                &pkt_len);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_max_pkt_size_get");
-        }
-        break;
-
-        case STAT_CAR_B_TYPE:
-        {
-            rc = dpp_stat_carb_max_pkt_size_get(dev,
-                                                &pkt_len);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_max_pkt_size_get");
-        }
-        break;
-
-        case STAT_CAR_C_TYPE:
-        {
-            rc = dpp_stat_carc_max_pkt_size_get(dev,
-                                                &pkt_len);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_max_pkt_size_get");
-        }
-        break;
-    }
-
-    *p_max_pkt_len = pkt_len;
-
-    return rc;
-}
-
-/***********************************************************/
-/** 配置最大包长
-* @param   dev_id
-* @param   car_type
-* @param   max_pkt_size
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  wll      @date  2019/06/06
-************************************************************/
-DPP_STATUS dpp_stat_car_max_pkt_size_set(DPP_DEV_T *dev,
-                                         ZXIC_UINT32 car_type,
-                                         ZXIC_UINT32 max_pkt_size)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE, STAT_CAR_MAX_TYPE - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), max_pkt_size, 0, 0x3fff);
-
-    switch (car_type)
-    {
-        case STAT_CAR_A_TYPE:
-        {
-            rc = dpp_stat_cara_max_pkt_size_set(dev,
-                                                max_pkt_size);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_max_pkt_size_set");
-        }
-        break;
-
-        case STAT_CAR_B_TYPE:
-        {
-            rc = dpp_stat_carb_max_pkt_size_set(dev,
-                                                max_pkt_size);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_max_pkt_size_set");
-        }
-        break;
-
-        case STAT_CAR_C_TYPE:
-        {
-            rc = dpp_stat_carc_max_pkt_size_set(dev,
-                                                max_pkt_size);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_max_pkt_size_set");
-        }
-        break;
-    }
-
-    return rc;
-}
-
-
-/***********************************************************/
-/** STAT CAR复位获取全局变量大小函数
-* @param   dev_id
-* @param   p_size
-*
-* @return
-* @remark  无
-* @see
-* @author  yxh      @date  2018/06/26
-************************************************************/
-DPP_STATUS dpp_stat_car_glb_size_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_size)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 queue_num = 0;
-    ZXIC_UINT32 profile_num = 0;
-    ZXIC_UINT32 pkt_profile_num = 0;
-
-    DPP_CAR_SOFT_RESET_DATA_T *p_g_restore_data = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_size);
-
-    p_g_restore_data = GET_DPP_CAR_SOFT_RESET_INFO(DEV_ID(dev));
-
-    if (0 == p_g_restore_data->is_init)
-    {
-        ZXIC_COMM_PRINT("Not init!!!\n");
-        *p_size = sizeof(ZXIC_UINT32);
-    }
-    else
-    {
-        /* CAR A */
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), queue_num, p_g_restore_data->cara_flow_num);
-        queue_num += p_g_restore_data->cara_flow_num;
-
-        /* CAR B */
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), queue_num, p_g_restore_data->carb_flow_num);
-        queue_num += p_g_restore_data->carb_flow_num;
-
-        /* CAR C */
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), queue_num, p_g_restore_data->carc_flow_num);
-        queue_num += p_g_restore_data->carc_flow_num;
-
-        pkt_profile_num = p_g_restore_data->car0_pkt_num;
-        ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(DEV_ID(dev), (DPP_CAR_A_PROFILE_ID_MAX + DPP_CAR_B_PROFILE_ID_MAX + DPP_CAR_C_PROFILE_ID_MAX + 3), pkt_profile_num);
-        profile_num = DPP_CAR_A_PROFILE_ID_MAX + DPP_CAR_B_PROFILE_ID_MAX + DPP_CAR_C_PROFILE_ID_MAX + 3 - pkt_profile_num;
-        /**占用的格式如下:
-        (ZXIC_UINT32)  (ZXIC_UINT32)               (ZXIC_UINT32)(CAR0)   (ZXIC_UINT32)(CAR1)                    (ZXIC_UINT32)
-         is_init  queue_num  queue_info  pkt_profile_num  pkt_profile_num  pkt_profile_cfg  profile_num  profile_cfg
-        */
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), queue_num, ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T)));
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), pkt_profile_num, ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T)));
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), profile_num, ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PROFILE_CFG_T)));
-        *p_size = ((ZXIC_UINT32)ZXIC_SIZEOF(ZXIC_UINT32)) * 5 + queue_num * ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T))
-                  + pkt_profile_num * ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T))
-                  + profile_num * ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PROFILE_CFG_T));
-        ZXIC_COMM_PRINT("glb_size = %d!!!\n", *p_size);
-    }
-
-    return rc;
-}
-
-#if 0
-/***********************************************************/
-/** STAT CAR复位设置全局变量函数
-* @param   dev_id           设备号
-* @param   size             大小，字节数
-* @param   p_data_buff      全局变量数据
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  yxh      @date  2018/06/26
-************************************************************/
-DPP_STATUS dpp_stat_car_glb_mgr_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 size, ZXIC_UINT8 *p_data_buff)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 is_init = 0;
-    ZXIC_UINT32 queue_num = 0;
-    ZXIC_UINT32 profile_num = 0;
-    ZXIC_UINT32 cara_profile_num = 0;
-    ZXIC_UINT32 car0_pkt_profile_num = 0;
-    ZXIC_UINT32 buff_offset = 0;
-    ZXIC_UINT32 size_of_stat_car = 0;
-
-    DPP_CAR_SOFT_RESET_QUEUE_T *p_car_glb_queue_info = NULL;
-    DPP_STAT_CAR_PROFILE_CFG_T *p_car_glb_profile_info = NULL;
-    DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_car_glb_pkt_profile_info = NULL;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data_buff);
-
-    rc = dpp_stat_car_glb_size_get(dev_id, &size_of_stat_car);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_car_glb_size_get");
-
-    if (size < size_of_stat_car)
-    {
-        ZXIC_COMM_TRACE_ERROR("dpp stat car glb mgr recovery, size of buffer is smaller than defaultss\n");
-        return DPP_ERR;
-    }
-
-    ZXIC_COMM_MEMCPY(&is_init, p_data_buff, size);
-    buff_offset = sizeof(ZXIC_UINT32);
-
-    if (0 == is_init)
-    {
-        ZXIC_COMM_PRINT("Not init!!!\n");
-    }
-    else
-    {
-        /* 获取queue的数目 */
-        ZXIC_COMM_MEMCPY(&queue_num, p_data_buff + buff_offset, sizeof(ZXIC_UINT32));
-        buff_offset += sizeof(ZXIC_UINT32);
-        p_car_glb_queue_info = (DPP_CAR_SOFT_RESET_QUEUE_T *)(p_data_buff + buff_offset);
-
-        /* 设置flow_id的信息 */
-        for (i = 0; i < queue_num; i++)
-        {
-            rc = dpp_stat_car_queue_cfg_set(dev_id,
-                                            p_car_glb_queue_info->car_type,
-                                            p_car_glb_queue_info->flow_id,
-                                            p_car_glb_queue_info->drop_flag,
-                                            p_car_glb_queue_info->plcr_en,
-                                            p_car_glb_queue_info->profile_id);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_car_queue_cfg_set");
-        }
-
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, buff_offset, queue_num * ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T));
-        buff_offset += (queue_num * ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T)) & 0xffffffff;
-
-        ZXIC_COMM_MEMCPY(&car0_pkt_profile_num, p_data_buff + buff_offset, sizeof(ZXIC_UINT32));
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, buff_offset, sizeof(ZXIC_UINT32));
-        buff_offset += sizeof(ZXIC_UINT32);
-
-        /* 设置pkt_frofile的信息 */
-        p_car_glb_pkt_profile_info = (DPP_STAT_CAR_PKT_PROFILE_CFG_T *)(p_data_buff + buff_offset);
-
-        for (i = 0; i < car0_pkt_profile_num; i++)
-        {
-            rc = dpp_stat_car_profile_cfg_set(dev_id,
-                                              STAT_CAR_A_TYPE,
-                                              ZXIC_TRUE,
-                                              p_car_glb_pkt_profile_info->profile_id,
-                                              p_car_glb_pkt_profile_info);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_car_profile_cfg_set");
-            p_car_glb_pkt_profile_info++;
-        }
-
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, buff_offset, car0_pkt_profile_num * ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T));
-        buff_offset += (car0_pkt_profile_num  * ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T)) & 0xffffffff;
-
-        ZXIC_COMM_MEMCPY(&profile_num, p_data_buff + buff_offset, sizeof(ZXIC_UINT32));
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, buff_offset, sizeof(ZXIC_UINT32));
-        buff_offset += sizeof(ZXIC_UINT32);
-
-        /* 设置profile的信息 */
-        p_car_glb_profile_info = (DPP_STAT_CAR_PROFILE_CFG_T *)(p_data_buff + buff_offset);
-
-        cara_profile_num = DPP_CAR_PKT_PROFILE_ID_MAX - car0_pkt_profile_num;
-
-        ZXIC_COMM_PRINT(">>>>>>>>>>> Set CAR_A_PROFILE info start!\n");
-
-        for (j = 0; j < cara_profile_num; j++)
-        {
-            rc = dpp_stat_car_profile_cfg_set(dev_id,
-                                                STAT_CAR_A_TYPE,
-                                                ZXIC_FALSE,
-                                                p_car_glb_profile_info->profile_id,
-                                                p_car_glb_profile_info);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_car_profile_cfg_set");
-            p_car_glb_profile_info++;
-        }
-
-        ZXIC_COMM_PRINT(">>>>>>>>>>> Set car CAR_B_PROFILE info start!\n");
-
-        for (j = 0; j <= DPP_CAR_B_PROFILE_ID_MAX; j++)
-        {
-            rc = dpp_stat_car_profile_cfg_set(dev_id,
-                                                STAT_CAR_B_TYPE,
-                                                ZXIC_FALSE,
-                                                p_car_glb_profile_info->profile_id,
-                                                p_car_glb_profile_info);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_car_profile_cfg_set");
-            p_car_glb_profile_info++;
-        }
-
-        ZXIC_COMM_PRINT(">>>>>>>>>>> Set car CAR_C_PROFILE info start!\n");
-
-        for (j = 0; j <= DPP_CAR_C_PROFILE_ID_MAX; j++)
-        {
-            rc = dpp_stat_car_profile_cfg_set(dev_id,
-                                                STAT_CAR_C_TYPE,
-                                                ZXIC_FALSE,
-                                                p_car_glb_profile_info->profile_id,
-                                                p_car_glb_profile_info);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_stat_car_profile_cfg_set");
-            p_car_glb_profile_info++;
-        }
-
-    }/*  end (1 == is_init) */
-
-    return rc;
-}
-
-/***********************************************************/
-/** STAT CAR复位获取全局变量函数
-* @param   dev_id               设备号
-* @param   p_flag               释放使能，1-需要手动free，0-不需要手动free
-* @param   p_size               数据大小
-* @param   pp_data_buff         全局变量数据
-*
-* @return  NPE_OK-成功，NPE_ERR-失败
-* @remark  无
-* @see
-* @author  yxh      @date  2018/06/26
-************************************************************/
-DPP_STATUS dpp_stat_car_glb_mgr_get(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 *p_flag,
-                                    ZXIC_UINT32 *p_size,
-                                    ZXIC_UINT8 **pp_data_buff)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 is_init = 0;
-    ZXIC_UINT32 flow_num = 0;
-    ZXIC_UINT32 flow_num_total = 0;
-    ZXIC_UINT32 plcr_en = 0;
-    ZXIC_UINT32 drop_flag = 0;
-    ZXIC_UINT32 profile_id = 0;
-    ZXIC_UINT32 profile_num_total = 0;
-    ZXIC_UINT32 profile_pkt_total = 0;
-    ZXIC_UINT32 buff_offset = 0;
-    ZXIC_UINT32 size = 0;
-    DPP_CAR_SOFT_RESET_DATA_T *p_g_restore_data = NULL;
-    DPP_CAR_SOFT_RESET_QUEUE_T *p_car_glb_queue_info = NULL;
-    DPP_CAR_SOFT_RESET_QUEUE_T *p_car_glb_queue_info_temp = NULL;
-    DPP_STAT_CAR_PROFILE_CFG_T *p_car_glb_profile_info = NULL;
-    DPP_STAT_CAR_PROFILE_CFG_T *p_car_glb_profile_info_temp = NULL;
-    DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_car_glb_pkt_profile_info = NULL;
-    DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_car_glb_pkt_profile_info_temp = NULL;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_size);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_flag);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, pp_data_buff);
-
-    p_g_restore_data = GET_DPP_CAR_SOFT_RESET_INFO(dev_id);
-
-    is_init = p_g_restore_data->is_init;
-
-    if (0 == is_init)
-    {
-        *p_size = sizeof(ZXIC_UINT32);
-        *p_flag = ZXIC_TRUE;
-
-        ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: No init\n");
-
-        *pp_data_buff = ZXIC_COMM_MALLOC(*p_size);
-        ZXIC_COMM_CHECK_DEV_POINT(dev_id, *pp_data_buff);
-        ZXIC_COMM_MEMSET(*pp_data_buff, 0, *p_size);
-
-        ZXIC_COMM_MEMCPY(*pp_data_buff, &is_init, sizeof(ZXIC_UINT32));
-    }
-    else
-    {
-        ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: Inited\n");
-
-        /** queue 绑定的信息 */
-        /* CAR A */
-        flow_num = p_g_restore_data->cara_flow_num;
-        ZXIC_COMM_TRACE_DEV_INFO(dev_id, "[dpp_stat_car_glb_mgr_get] cara_queue_num     : 0x%08x\n", flow_num);
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, flow_num_total, flow_num);
-        flow_num_total += flow_num;
-
-        /* CAR B */
-        flow_num = p_g_restore_data->carb_flow_num;
-        ZXIC_COMM_TRACE_DEV_INFO(dev_id, "[dpp_stat_car_glb_mgr_get] carb_queue_num     : 0x%08x\n", flow_num);
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, flow_num_total, flow_num);
-        flow_num_total += flow_num;
-
-        /* CAR C */
-        flow_num = p_g_restore_data->carc_flow_num;
-        ZXIC_COMM_TRACE_DEV_INFO(dev_id, "[dpp_stat_car_glb_mgr_get] carc_queue_num     : 0x%08x\n", flow_num);
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, flow_num_total, flow_num);
-        flow_num_total += flow_num;
-
-        profile_pkt_total = p_g_restore_data->car0_pkt_num;
-        ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, DPP_CAR_PROFILE_ID_TOTAL, profile_pkt_total);
-        profile_num_total = DPP_CAR_PROFILE_ID_TOTAL - profile_pkt_total;
-
-        /**占用的格式如下:
-        (ZXIC_UINT32)  (ZXIC_UINT32)               (ZXIC_UINT32)(CAR0)   (ZXIC_UINT32)(CAR1)                    (ZXIC_UINT32)
-         is_init  queue_num  queue_info  pkt_profile_num  pkt_profile_num  pkt_profile_cfg  profile_num  profile_cfg
-        */
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, flow_num_total, ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T)));
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, profile_pkt_total, ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T)));
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, profile_num_total, ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PROFILE_CFG_T)));
-        *p_size = ((ZXIC_UINT32)ZXIC_SIZEOF(ZXIC_UINT32)) * 5 + flow_num_total * ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T))
-                  + profile_pkt_total * ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T))
-                  + profile_num_total * ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PROFILE_CFG_T));
-
-        /* 存放init_flag */
-        *pp_data_buff = ZXIC_COMM_MALLOC(*p_size);
-        ZXIC_COMM_CHECK_DEV_POINT(dev_id, *pp_data_buff);
-        ZXIC_COMM_MEMSET(*pp_data_buff, 0, *p_size);
-        ZXIC_COMM_MEMCPY(*pp_data_buff, &is_init, sizeof(ZXIC_UINT32));
-        buff_offset = sizeof(ZXIC_UINT32);
-
-        /* 存放queue_num */
-        ZXIC_COMM_MEMCPY(*pp_data_buff + buff_offset, &flow_num_total, sizeof(ZXIC_UINT32));
-        buff_offset += sizeof(ZXIC_UINT32);
-
-        /* 获取、存放queue 绑定的信息 */
-        if (0 != flow_num_total)
-        {
-            ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: Get queue info start!\n");
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, flow_num_total, ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T)));
-            p_car_glb_queue_info = (DPP_CAR_SOFT_RESET_QUEUE_T *)ZXIC_COMM_MALLOC(flow_num_total * ((ZXIC_UINT32)ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T)));
-            ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_car_glb_queue_info);
-            ZXIC_COMM_MEMSET(p_car_glb_queue_info, 0, flow_num_total * sizeof(DPP_CAR_SOFT_RESET_QUEUE_T));
-            p_car_glb_queue_info_temp = p_car_glb_queue_info;
-
-            /* CAR A */
-            flow_num = p_g_restore_data->cara_flow_num;
-
-            for (j = 0; j < flow_num; j++)
-            {
-                rc = dpp_stat_car_queue_cfg_get(dev_id,
-                                                STAT_CAR_A_TYPE,
-                                                p_g_restore_data->cara_item[j].flow_id,
-                                                &drop_flag,
-                                                &plcr_en,
-                                                &profile_id);
-                if (DPP_OK != rc)
-                {
-                    ZXIC_COMM_FREE(p_car_glb_queue_info);
-                    ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_stat_car_queue_cfg_get");
-                    return rc;
-                }
-
-                p_car_glb_queue_info_temp->car_type = STAT_CAR_A_TYPE;
-                p_car_glb_queue_info_temp->flow_id = p_g_restore_data->cara_item[j].flow_id;
-                p_car_glb_queue_info_temp->drop_flag = drop_flag;
-                p_car_glb_queue_info_temp->plcr_en = plcr_en;
-                p_car_glb_queue_info_temp->profile_id = profile_id;
-                p_car_glb_queue_info_temp++;
-                ZXIC_COMM_TRACE_DEV_INFO(dev_id, "carA used flow_id[%d]     : 0x%08x\n", j, p_g_restore_data->cara_item[j].flow_id);
-            }
-
-            /* CAR B */
-            flow_num = p_g_restore_data->carb_flow_num;
-
-            for (j = 0; j < flow_num; j++)
-            {
-                rc = dpp_stat_car_queue_cfg_get(dev_id,
-                                                STAT_CAR_B_TYPE,
-                                                p_g_restore_data->carb_item[j].flow_id,
-                                                &drop_flag,
-                                                &plcr_en,
-                                                &profile_id);
-                if (DPP_OK != rc)
-                {
-                    ZXIC_COMM_FREE(p_car_glb_queue_info);
-                    ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_stat_car_queue_cfg_get");
-                    return rc;
-                }
-
-                p_car_glb_queue_info_temp->car_type = STAT_CAR_B_TYPE;
-                p_car_glb_queue_info_temp->flow_id = p_g_restore_data->carb_item[j].flow_id;
-                p_car_glb_queue_info_temp->drop_flag = drop_flag;
-                p_car_glb_queue_info_temp->plcr_en = plcr_en;
-                p_car_glb_queue_info_temp->profile_id = profile_id;
-                p_car_glb_queue_info_temp++;
-                ZXIC_COMM_TRACE_DEV_INFO(dev_id, "carB used flow_id[%d]     : 0x%08x\n", j, p_g_restore_data->carb_item[j].flow_id);
-            }
-
-            /* CAR C */
-            flow_num = p_g_restore_data->carc_flow_num;
-
-            for (j = 0; j < flow_num; j++)
-            {
-                rc = dpp_stat_car_queue_cfg_get(dev_id,
-                                                STAT_CAR_C_TYPE,
-                                                p_g_restore_data->carc_item[j].flow_id,
-                                                &drop_flag,
-                                                &plcr_en,
-                                                &profile_id);
-                if (DPP_OK != rc)
-                {
-                    ZXIC_COMM_FREE(p_car_glb_queue_info);
-                    ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_stat_car_queue_cfg_get");
-                    return rc;
-                }
-
-                p_car_glb_queue_info_temp->car_type = STAT_CAR_C_TYPE;
-                p_car_glb_queue_info_temp->flow_id = p_g_restore_data->carc_item[j].flow_id;
-                p_car_glb_queue_info_temp->drop_flag = drop_flag;
-                p_car_glb_queue_info_temp->plcr_en = plcr_en;
-                p_car_glb_queue_info_temp->profile_id = profile_id;
-                p_car_glb_queue_info_temp++;
-                ZXIC_COMM_TRACE_DEV_INFO(dev_id, "carC used flow_id[%d]     : 0x%08x\n", j, p_g_restore_data->carb_item[j].flow_id);
-            }
-
-            ZXIC_COMM_MEMCPY(*pp_data_buff + buff_offset, p_car_glb_queue_info, flow_num_total * sizeof(DPP_CAR_SOFT_RESET_QUEUE_T));
-            if((0xFFFFFFFF - (buff_offset)) < (flow_num_total * ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T)))
-            {
-                ZXIC_COMM_FREE(p_car_glb_queue_info);
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id,  "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, buff_offset, flow_num_total * ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T), __FUNCTION__);
-                return ZXIC_PAR_CHK_INVALID_INDEX;
-            }
-            buff_offset += (flow_num_total * ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T)) % 0xffffffff;
-        }
-
-        ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: total flow_num = %d !\n", flow_num_total);
-
-        /** profile 的信息 */
-        if (0 != profile_pkt_total)
-        {
-            p_car_glb_pkt_profile_info = (DPP_STAT_CAR_PKT_PROFILE_CFG_T *)ZXIC_COMM_MALLOC(profile_pkt_total * ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T));
-            if (NULL == (p_car_glb_pkt_profile_info))
-            {
-                ZXIC_COMM_FREE(p_car_glb_queue_info);
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);
-                return ZXIC_PAR_CHK_POINT_NULL;
-            }
-
-            ZXIC_COMM_MEMSET(p_car_glb_pkt_profile_info, 0, profile_pkt_total * sizeof(DPP_STAT_CAR_PKT_PROFILE_CFG_T));
-            p_car_glb_pkt_profile_info_temp = p_car_glb_pkt_profile_info;
-        }
-        size = ZXIC_SIZEOF(DPP_STAT_CAR_PROFILE_CFG_T);
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, profile_num_total, size);
-        p_car_glb_profile_info = (DPP_STAT_CAR_PROFILE_CFG_T *)ZXIC_COMM_MALLOC(profile_num_total * size);
-        if (NULL == (p_car_glb_profile_info))
-        {
-            ZXIC_COMM_FREE(p_car_glb_queue_info);
-            ZXIC_COMM_FREE(p_car_glb_pkt_profile_info);
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);
-            return ZXIC_PAR_CHK_POINT_NULL;
-        }
-
-        ZXIC_COMM_MEMSET(p_car_glb_profile_info, 0, profile_num_total * sizeof(DPP_STAT_CAR_PROFILE_CFG_T));
-        p_car_glb_profile_info_temp = p_car_glb_profile_info;
-
-        ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: Get profile info start!\n");
-        ZXIC_COMM_PRINT(">>>>>>>>>>> Get car CAR_A_PROFILE info start!\n");
-
-        for (j = 0; j <= DPP_CAR_A_PROFILE_ID_MAX; j++)
-        {
-            /* (0 != profile_pkt_total) -- Coverity err : 递增 null 指针 p_car_glb_pkt_profile_info_temp */
-            if ((0 != profile_pkt_total) && (ZXIC_TRUE == p_g_restore_data->car_pkt_sign[j]))
-            {
-                ZXIC_COMM_TRACE_DEV_INFO(dev_id, "car profile_id[%d] is pkt_profile!!!!\n", j);
-                rc = dpp_stat_car_profile_cfg_get(dev_id,
-                                                    STAT_CAR_A_TYPE,
-                                                    ZXIC_TRUE,
-                                                    j,
-                                                    p_car_glb_pkt_profile_info_temp);
-                if (DPP_OK != rc)
-                {
-                    ZXIC_COMM_FREE(p_car_glb_queue_info);
-                    ZXIC_COMM_FREE(p_car_glb_pkt_profile_info);
-                    ZXIC_COMM_FREE(p_car_glb_profile_info);
-                    ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_stat_car_profile_cfg_get");
-                    return rc;
-                }
-
-                p_car_glb_pkt_profile_info_temp++;
-            }
-        }
-
-        for (j = 0; j <= DPP_CAR_A_PROFILE_ID_MAX; j++)
-        {
-            if (ZXIC_TRUE != p_g_restore_data->car_pkt_sign[j])
-            {
-                rc = dpp_stat_car_profile_cfg_get(dev_id,
-                                                    STAT_CAR_A_TYPE,
-                                                    ZXIC_FALSE,
-                                                    j,
-                                                    p_car_glb_profile_info_temp);
-                if (DPP_OK != rc)
-                {
-                    ZXIC_COMM_FREE(p_car_glb_queue_info);
-                    ZXIC_COMM_FREE(p_car_glb_pkt_profile_info);
-                    ZXIC_COMM_FREE(p_car_glb_profile_info);
-                    ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_stat_car_profile_cfg_get");
-                    return rc;
-                }
-
-                p_car_glb_profile_info_temp++;
-            }
-        }
-
-        ZXIC_COMM_PRINT(">>>>>>>>>>> Get car CAR_B_PROFILE info start!\n");
-
-        for (j = 0; j <= DPP_CAR_B_PROFILE_ID_MAX; j++)
-        {
-            rc = dpp_stat_car_profile_cfg_get(dev_id,
-                                                STAT_CAR_B_TYPE,
-                                                ZXIC_FALSE,
-                                                j,
-                                                p_car_glb_profile_info_temp);
-        if (DPP_OK != rc)
-        {
-            ZXIC_COMM_FREE(p_car_glb_queue_info);
-            ZXIC_COMM_FREE(p_car_glb_pkt_profile_info);
-            ZXIC_COMM_FREE(p_car_glb_profile_info);
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_stat_car_profile_cfg_get");
-            return rc;
-        }
-
-            p_car_glb_profile_info_temp++;
-        }
-
-        ZXIC_COMM_PRINT(">>>>>>>>>>> Get car CAR_C_PROFILE info start!\n");
-
-        for (j = 0; j <= DPP_CAR_C_PROFILE_ID_MAX; j++)
-        {
-            rc = dpp_stat_car_profile_cfg_get(dev_id,
-                                                STAT_CAR_C_TYPE,
-                                                ZXIC_FALSE,
-                                                j,
-                                                p_car_glb_profile_info_temp);
-        if (DPP_OK != rc)
-        {
-            ZXIC_COMM_FREE(p_car_glb_queue_info);
-            ZXIC_COMM_FREE(p_car_glb_pkt_profile_info);
-            ZXIC_COMM_FREE(p_car_glb_profile_info);
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_stat_car_profile_cfg_get");
-            return rc;
-        }
-            p_car_glb_profile_info_temp++;
-        }
-
-        ZXIC_COMM_MEMCPY(*pp_data_buff + buff_offset, &(p_g_restore_data->car0_pkt_num), sizeof(ZXIC_UINT32));
-        buff_offset += sizeof(ZXIC_UINT32);
-
-        if((0xFFFFFFFF - (buff_offset)) < (sizeof(ZXIC_UINT32)))
-        {
-            ZXIC_COMM_FREE(p_car_glb_queue_info);
-            ZXIC_COMM_FREE(p_car_glb_profile_info);
-            ZXIC_COMM_FREE(p_car_glb_pkt_profile_info);
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,  "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, buff_offset, sizeof(ZXIC_UINT32), __FUNCTION__);
-            return ZXIC_PAR_CHK_INVALID_INDEX;
-        }
-        buff_offset += sizeof(ZXIC_UINT32);
-
-        if (0 != profile_pkt_total)
-        {
-            ZXIC_COMM_MEMCPY(*pp_data_buff + buff_offset, p_car_glb_pkt_profile_info, profile_pkt_total * sizeof(DPP_STAT_CAR_PKT_PROFILE_CFG_T));
-            buff_offset += profile_pkt_total * ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T);
-        }
-
-        ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: total pkt_profile = %d !\n", profile_pkt_total);
-
-        ZXIC_COMM_MEMCPY(*pp_data_buff + buff_offset, &profile_num_total, sizeof(ZXIC_UINT32));
-        if((0xFFFFFFFF - (buff_offset)) < (sizeof(ZXIC_UINT32)))
-        {
-           ZXIC_COMM_FREE(p_car_glb_queue_info);
-		   ZXIC_COMM_FREE(p_car_glb_profile_info);
-		   ZXIC_COMM_FREE(p_car_glb_pkt_profile_info);
-           ZXIC_COMM_TRACE_DEV_ERROR(dev_id,  "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, buff_offset, sizeof(ZXIC_UINT32), __FUNCTION__);
-           return ZXIC_PAR_CHK_INVALID_INDEX;
-        }
-        buff_offset += sizeof(ZXIC_UINT32);
-
-        if (0 != profile_num_total)
-        {
-            ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: total profile = %d !\n", profile_num_total);
-            ZXIC_COMM_MEMCPY(*pp_data_buff + buff_offset, p_car_glb_profile_info, profile_num_total * sizeof(DPP_STAT_CAR_PROFILE_CFG_T));
-            buff_offset += profile_num_total * ZXIC_SIZEOF(DPP_STAT_CAR_PROFILE_CFG_T);
-        }
-
-        ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: total profile = %d !\n", profile_num_total);
-        ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: buff_offset= %d !\n", buff_offset);
-
-        *p_flag = ZXIC_TRUE;
-
-        ZXIC_COMM_FREE(p_car_glb_queue_info);
-
-        if (0 != profile_pkt_total)
-        {
-            ZXIC_COMM_FREE(p_car_glb_pkt_profile_info);
-        }
-
-        ZXIC_COMM_FREE(p_car_glb_profile_info);
-    }
-
-    ZXIC_COMM_PRINT(">>>>>>>>>>>[dpp_stat_car_glb_mgr_get]: END! total size = %d !\n", *p_size);
-
-    return rc;
-}
-
-#endif
-#endif
-
-#if ZXIC_REAL("TEST")
-
-#if 0
-/***********************************************************/
-/**
-* @param   p_rb_cfg
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2017/10/31
-************************************************************/
-DPP_STATUS dpp_stat_queue_rb_root_prt(ZXIC_RB_CFG *p_rb_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 dev_id = 0;
-
-    DPP_CAR_QUEUE_RB_KEY_T *p_tmp_car_queue_rb_key = NULL;
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rb_cfg);
-
-    if (NULL != p_rb_cfg->p_root)
-    {
-        p_tmp_car_queue_rb_key = (DPP_CAR_QUEUE_RB_KEY_T *)p_rb_cfg->p_root->p_key;
-
-        if (NULL != p_tmp_car_queue_rb_key)
-        {
-            ZXIC_COMM_PRINT("dpp_stat_queue_rb_root_prt[GET] car_queue_cfg:\n");
-
-            for (i = 0; i < DPP_CAR_QUEUE_CFG_ZXIC_UINT8; i++)
-            {
-                ZXIC_COMM_PRINT("%02x\t", p_tmp_car_queue_rb_key->profile_cfg[i]);
-
-                if (0 ==  (i + 1) % 4)
-                {
-                    ZXIC_COMM_PRINT("\n");
-                }
-            }
-
-            ZXIC_COMM_PRINT("\n");
-
-        }
-
-    }
-
-    return rc;
-}
-
-/***********************************************************/
-/**
-* @param   p_rb_cfg
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2017/10/31
-************************************************************/
-DPP_STATUS dpp_stat_car_profile_id_rb_root_prt(ZXIC_UINT32 dev_id, ZXIC_RB_CFG *p_rb_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-
-    DPP_CAR_PROFILE_ID_RB_KEY_T *p_tmp_car_profile_id_rb_key = NULL;
-    ZXIC_RB_TN                   *p_car_rb_node               = NULL;
-    DPP_CAR_PROFILE_RB_KEY_T    *p_car_profile_rb_key        = NULL;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rb_cfg);
-
-    if (NULL != p_rb_cfg->p_root)
-    {
-        p_tmp_car_profile_id_rb_key = (DPP_CAR_PROFILE_ID_RB_KEY_T *)p_rb_cfg->p_root->p_key;
-
-        if (NULL != p_tmp_car_profile_id_rb_key)
-        {
-            /* ZXIC_COMM_PRINT("dpp_stat_car_profile_id_rb_root_prt pp_car_node ADDRESS: 0x%08x\n", (ZXIC_UINT32)p_tmp_car_profile_id_rb_key->p_car_node); */
-            p_car_rb_node = (ZXIC_RB_TN * )p_tmp_car_profile_id_rb_key->p_car_node;
-
-            if (NULL != p_car_rb_node)
-            {
-                p_car_profile_rb_key = (DPP_CAR_PROFILE_RB_KEY_T *)p_car_rb_node->p_key;
-
-                if (NULL != p_car_profile_rb_key)
-                {
-                    for (i = 0; i < DPP_CAR_PROFILE_CFG_ZXIC_UINT32; i++)
-                    {
-                        ZXIC_COMM_PRINT("%08x\t", p_car_profile_rb_key->profile_cfg[i]);
-
-                        if (0 == (i + 1) % 4)
-                        {
-                            ZXIC_COMM_PRINT("\n");
-                        }
-                    }
-
-                    ZXIC_COMM_PRINT("\n");
-                }
-            }
-        }
-    }
-
-    return rc;
-}
-
-#endif
-#endif
-
-
-
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_stat_car.c
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : XXX
+* 完成日期 : 2017/02/09
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#include "zxic_common.h"
+#include "dpp_type_api.h"
+#include "dpp_reg.h"
+// #include "dpp_devmng_api.h"
+#include "dpp_stat_car.h"
+#include "dpp_stat_api.h"
+
+#if ZXIC_REAL("Global Variable")
+
+/** 软复位相关 */
+static DPP_CAR_SOFT_RESET_DATA_T g_car_store_data[DPP_DEV_CHANNEL_MAX] = {
+	{ { 0 } }
+};
+
+#define GET_DPP_CAR_SOFT_RESET_INFO(dev_id) (&g_car_store_data[dev_id])
+
+#define DPP_CAR1_REG_OFFSET (0)
+
+#endif
+
+#if ZXIC_REAL("Basic Reg Operation ")
+/***********************************************************/
+/** car A的流设置
+ * @param   dev_id           设备号           car编号
+ * @param   flow_id          流号
+ * @param   drop_flag        丢弃标志
+ * @param   plcr_en          监管使能
+ * @param   profile_id       监管模板号
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS dpp_stat_cara_queue_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									   ZXIC_UINT32 drop_flag,
+									   ZXIC_UINT32 plcr_en,
+									   ZXIC_UINT32 profile_id)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T queue_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), drop_flag, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), plcr_en, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+							  DPP_CAR_A_PROFILE_ID_MAX);
+
+	queue_cfg.cara_drop = drop_flag;
+	queue_cfg.cara_plcr_en = plcr_en;
+	queue_cfg.cara_profile_id = profile_id;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_CARA_QUEUE_RAM0_159_0r, 0, flow_id,
+					   &queue_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取car A的流设置
+ * @param   dev_id               设备号
+ * @param   flow_id              流号
+ * @param   p_cara_queue_cfg     car A流配置信息
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS
+dpp_stat_cara_queue_cfg_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+							DPP_STAT_CAR_A_QUEUE_CFG_T *p_cara_queue_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T queue_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_queue_cfg);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_CARA_QUEUE_RAM0_159_0r, 0, flow_id,
+					  &queue_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	p_cara_queue_cfg->flow_id = flow_id;
+	p_cara_queue_cfg->drop_flag = queue_cfg.cara_drop;
+	p_cara_queue_cfg->plcr_en = queue_cfg.cara_plcr_en;
+	p_cara_queue_cfg->profile_id = queue_cfg.cara_profile_id;
+
+	p_cara_queue_cfg->tq =
+			ZXIC_COMM_COUNTER64_BUILD(queue_cfg.cara_tq_h, queue_cfg.cara_tq_l);
+
+	p_cara_queue_cfg->ted = queue_cfg.cara_ted;
+	p_cara_queue_cfg->tcd = queue_cfg.cara_tcd;
+	p_cara_queue_cfg->tei = queue_cfg.cara_tei;
+	p_cara_queue_cfg->tci = queue_cfg.cara_tci;
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取car A 包长监管流配置
+ * @param   dev_id               设备号
+ * @param   flow_id              流号
+ * @param   p_cara_queue_cfg     car A流配置信息
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS dpp_stat_cara_pkt_queue_cfg_get(
+		DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+		DPP_STAT_CAR_A_PKT_QUEUE_CFG_T *p_cara_queue_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_STAT_CAR0_CARA_QUEUE_RAM0_159_0_PKT_T queue_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_queue_cfg);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_CARA_QUEUE_RAM0_159_0_PKTr, 0, flow_id,
+					  &queue_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	p_cara_queue_cfg->flow_id = flow_id;
+	p_cara_queue_cfg->plcr_en = queue_cfg.cara_plcr_en;
+	p_cara_queue_cfg->profile_id = queue_cfg.cara_profile_id;
+
+	p_cara_queue_cfg->tq =
+			ZXIC_COMM_COUNTER64_BUILD(queue_cfg.cara_tq_h, queue_cfg.cara_tq_l);
+
+	p_cara_queue_cfg->dc = ZXIC_COMM_COUNTER64_BUILD(queue_cfg.cara_dc_high,
+													 queue_cfg.cara_dc_low);
+	p_cara_queue_cfg->tc = queue_cfg.cara_tc;
+
+	return rc;
+}
+
+/***********************************************************/
+/** car A 字节限速监管模板设定
+ * @param   dev_id               设备号
+ * @param   profile_id           监管模板号
+ * @param   p_cara_profile_cfg   监管模板配置
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS
+dpp_stat_cara_profile_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+							  DPP_STAT_CAR_PROFILE_CFG_T *p_cara_profile_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 i = 0;
+
+	DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_T profile_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+							  DPP_CAR_A_PROFILE_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_profile_cfg);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->profile_id, 0,
+							  DPP_CAR_A_PROFILE_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->pkt_sign, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cf, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cm, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cd,
+							  CAR_CD_MODE_SRTCM, CAR_CD_MODE_INVALID - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cir, 0,
+							  DPP_CAR_MAX_CIR_VALUE);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->eir, 0,
+							  DPP_CAR_MAX_EIR_VALUE);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cbs, 0,
+							  DPP_CAR_MAX_CBS_VALUE);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->ebs, 0,
+							  DPP_CAR_MAX_EBS_VALUE);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->random_disc_e, 0,
+							  0xffffffff);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->random_disc_c, 0,
+							  0xffffffff);
+
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->e_yellow_pri[0],
+							  0, DPP_CAR_MAX_PRI_VALUE);
+
+	for (i = 1; i < DPP_CAR_PRI_MAX; i++) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->c_pri[i], 0,
+								  DPP_CAR_MAX_PRI_VALUE);
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev),
+								  p_cara_profile_cfg->e_green_pri[i], 0,
+								  DPP_CAR_MAX_PRI_VALUE);
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev),
+								  p_cara_profile_cfg->e_yellow_pri[i], 0,
+								  DPP_CAR_MAX_PRI_VALUE);
+	}
+	ZXIC_COMM_TRACE_DEV_INFO(
+			DEV_ID(dev), "==> dpp_stat_cara_profile_cfg_set profile_id[%d]: \n",
+			profile_id);
+	ZXIC_COMM_TRACE_DEV_INFO(
+			DEV_ID(dev),
+			"| -------------------------------------------------------------- | \n");
+	ZXIC_COMM_TRACE_DEV_INFO(
+			DEV_ID(dev),
+			"| %-5s | %-5s | %-5s | %-10s | %-10s | %-10s | %-10s | \n", "cd",
+			"cf", "cm", "cir", "cbs", "eir", "ebs");
+	ZXIC_COMM_TRACE_DEV_INFO(
+			DEV_ID(dev),
+			"| %-5d | %-5d | %-5d | %-10d | %-10d | %-10d | %-10d | \n",
+			p_cara_profile_cfg->cd, p_cara_profile_cfg->cf,
+			p_cara_profile_cfg->cm, p_cara_profile_cfg->cir,
+			p_cara_profile_cfg->cbs, p_cara_profile_cfg->eir,
+			p_cara_profile_cfg->ebs);
+	ZXIC_COMM_TRACE_DEV_INFO(
+			DEV_ID(dev),
+			"| ----- | ----- | ----- | ---------- | ---------- | ---------- | ---------- | \n");
+
+	profile_cfg.cara_e_y_pri7 = p_cara_profile_cfg->e_yellow_pri[7];
+	profile_cfg.cara_e_y_pri6 = p_cara_profile_cfg->e_yellow_pri[6];
+	profile_cfg.cara_e_y_pri5 = p_cara_profile_cfg->e_yellow_pri[5];
+	profile_cfg.cara_e_y_pri4 = p_cara_profile_cfg->e_yellow_pri[4];
+	profile_cfg.cara_e_y_pri3 = p_cara_profile_cfg->e_yellow_pri[3];
+	profile_cfg.cara_e_y_pri2 = p_cara_profile_cfg->e_yellow_pri[2];
+	profile_cfg.cara_e_y_pri1 = p_cara_profile_cfg->e_yellow_pri[1];
+	profile_cfg.cara_e_y_pri0 = p_cara_profile_cfg->e_yellow_pri[0];
+
+	profile_cfg.cara_e_g_pri7 = p_cara_profile_cfg->e_green_pri[7];
+	profile_cfg.cara_e_g_pri6 = p_cara_profile_cfg->e_green_pri[6];
+	profile_cfg.cara_e_g_pri5 = p_cara_profile_cfg->e_green_pri[5];
+	profile_cfg.cara_e_g_pri4 = p_cara_profile_cfg->e_green_pri[4];
+	profile_cfg.cara_e_g_pri3 = p_cara_profile_cfg->e_green_pri[3];
+	profile_cfg.cara_e_g_pri2 = p_cara_profile_cfg->e_green_pri[2];
+	profile_cfg.cara_e_g_pri1 = p_cara_profile_cfg->e_green_pri[1];
+
+	profile_cfg.cara_c_pri7 = p_cara_profile_cfg->c_pri[7];
+	profile_cfg.cara_c_pri6 = p_cara_profile_cfg->c_pri[6];
+	profile_cfg.cara_c_pri5 = p_cara_profile_cfg->c_pri[5];
+	profile_cfg.cara_c_pri4 = p_cara_profile_cfg->c_pri[4];
+	profile_cfg.cara_c_pri3 = p_cara_profile_cfg->c_pri[3];
+	profile_cfg.cara_c_pri2 = p_cara_profile_cfg->c_pri[2];
+	profile_cfg.cara_c_pri1 = p_cara_profile_cfg->c_pri[1];
+
+	profile_cfg.cara_cbs = p_cara_profile_cfg->cbs;
+	profile_cfg.cara_ebs_pbs = p_cara_profile_cfg->ebs;
+	profile_cfg.cara_cir = p_cara_profile_cfg->cir;
+	profile_cfg.cara_eir = p_cara_profile_cfg->eir;
+
+	profile_cfg.cara_cd = p_cara_profile_cfg->cd;
+	profile_cfg.cara_cf = p_cara_profile_cfg->cf;
+	profile_cfg.cara_cm = p_cara_profile_cfg->cm;
+	profile_cfg.cara_pkt_sign = p_cara_profile_cfg->pkt_sign;
+
+	profile_cfg.cara_profile_wr = 0;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_CARA_PROFILE_RAM1_255_0r, 0, profile_id,
+					   &profile_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取car A包的监管模板配置
+ * @param   dev_id               设备号
+ * @param   profile_id           监管模板号
+ * @param   p_cara_profile_cfg   监管模板配置
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS
+dpp_stat_cara_profile_cfg_get(DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+							  DPP_STAT_CAR_PROFILE_CFG_T *p_cara_profile_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_T profile_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+							  DPP_CAR_A_PROFILE_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_profile_cfg);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_CARA_PROFILE_RAM1_255_0r, 0, profile_id,
+					  &profile_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	p_cara_profile_cfg->profile_id = profile_id;
+	p_cara_profile_cfg->pkt_sign = profile_cfg.cara_pkt_sign;
+	p_cara_profile_cfg->cd = profile_cfg.cara_cd;
+	p_cara_profile_cfg->cf = profile_cfg.cara_cf;
+	p_cara_profile_cfg->cm = profile_cfg.cara_cm;
+	p_cara_profile_cfg->eir = profile_cfg.cara_eir;
+	p_cara_profile_cfg->cir = profile_cfg.cara_cir;
+	p_cara_profile_cfg->ebs = profile_cfg.cara_ebs_pbs;
+	p_cara_profile_cfg->cbs = profile_cfg.cara_cbs;
+
+	p_cara_profile_cfg->c_pri[1] = profile_cfg.cara_c_pri1;
+	p_cara_profile_cfg->c_pri[2] = profile_cfg.cara_c_pri2;
+	p_cara_profile_cfg->c_pri[3] = profile_cfg.cara_c_pri3;
+	p_cara_profile_cfg->c_pri[4] = profile_cfg.cara_c_pri4;
+	p_cara_profile_cfg->c_pri[5] = profile_cfg.cara_c_pri5;
+	p_cara_profile_cfg->c_pri[6] = profile_cfg.cara_c_pri6;
+	p_cara_profile_cfg->c_pri[7] = profile_cfg.cara_c_pri7;
+
+	p_cara_profile_cfg->e_green_pri[1] = profile_cfg.cara_e_g_pri1;
+	p_cara_profile_cfg->e_green_pri[2] = profile_cfg.cara_e_g_pri2;
+	p_cara_profile_cfg->e_green_pri[3] = profile_cfg.cara_e_g_pri3;
+	p_cara_profile_cfg->e_green_pri[4] = profile_cfg.cara_e_g_pri4;
+	p_cara_profile_cfg->e_green_pri[5] = profile_cfg.cara_e_g_pri5;
+	p_cara_profile_cfg->e_green_pri[6] = profile_cfg.cara_e_g_pri6;
+	p_cara_profile_cfg->e_green_pri[7] = profile_cfg.cara_e_g_pri7;
+
+	p_cara_profile_cfg->e_yellow_pri[0] = profile_cfg.cara_e_y_pri0;
+	p_cara_profile_cfg->e_yellow_pri[1] = profile_cfg.cara_e_y_pri1;
+	p_cara_profile_cfg->e_yellow_pri[2] = profile_cfg.cara_e_y_pri2;
+	p_cara_profile_cfg->e_yellow_pri[3] = profile_cfg.cara_e_y_pri3;
+	p_cara_profile_cfg->e_yellow_pri[4] = profile_cfg.cara_e_y_pri4;
+	p_cara_profile_cfg->e_yellow_pri[5] = profile_cfg.cara_e_y_pri5;
+	p_cara_profile_cfg->e_yellow_pri[6] = profile_cfg.cara_e_y_pri6;
+	p_cara_profile_cfg->e_yellow_pri[7] = profile_cfg.cara_e_y_pri7;
+
+	return rc;
+}
+
+/***********************************************************/
+/** car A包限速监管模板设定
+ * @param   dev_id               设备号
+ * @param   profile_id           监管模板号
+ * @param   p_cara_profile_cfg   监管模板配置
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS dpp_stat_cara_pkt_profile_cfg_set(
+		DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+		DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_cara_profile_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 i = 0;
+
+	DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKT_T profile_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+							  DPP_CAR_A_PROFILE_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_profile_cfg);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->pkt_sign, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cir, 0,
+							  DPP_CAR_MAX_CIR_VALUE);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->cbs, 0,
+							  DPP_CAR_MAX_CBS_VALUE);
+
+	for (i = 0; i < DPP_CAR_PRI_MAX; i++) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_cara_profile_cfg->pri[i], 0,
+								  DPP_CAR_MAX_PRI_VALUE);
+	}
+
+	profile_cfg.cara_pri7 = p_cara_profile_cfg->pri[7];
+	profile_cfg.cara_pri6 = p_cara_profile_cfg->pri[6];
+	profile_cfg.cara_pri5 = p_cara_profile_cfg->pri[5];
+	profile_cfg.cara_pri4 = p_cara_profile_cfg->pri[4];
+	profile_cfg.cara_pri3 = p_cara_profile_cfg->pri[3];
+	profile_cfg.cara_pri2 = p_cara_profile_cfg->pri[2];
+	profile_cfg.cara_pri1 = p_cara_profile_cfg->pri[1];
+	profile_cfg.cara_pri0 = p_cara_profile_cfg->pri[0];
+
+	profile_cfg.cara_pkt_cbs = p_cara_profile_cfg->cbs;
+	profile_cfg.cara_pkt_cir = p_cara_profile_cfg->cir;
+	profile_cfg.cara_pkt_sign = p_cara_profile_cfg->pkt_sign;
+
+	profile_cfg.cara_profile_wr = 0;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKTr, 0,
+					   profile_id, &profile_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取car A包长监管模板配置
+ * @param   dev_id               设备号
+ * @param   profile_id           监管模板号
+ * @param   p_cara_profile_cfg   监管模板配置
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS dpp_stat_cara_pkt_profile_cfg_get(
+		DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+		DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_cara_profile_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKT_T profile_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+							  DPP_CAR_A_PROFILE_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_cara_profile_cfg);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKTr, 0,
+					  profile_id, &profile_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	p_cara_profile_cfg->profile_id = profile_id;
+	p_cara_profile_cfg->pkt_sign = profile_cfg.cara_pkt_sign;
+	p_cara_profile_cfg->cir = profile_cfg.cara_pkt_cir;
+	p_cara_profile_cfg->cbs = profile_cfg.cara_pkt_cbs;
+
+	p_cara_profile_cfg->pri[0] = profile_cfg.cara_pri0;
+	p_cara_profile_cfg->pri[1] = profile_cfg.cara_pri1;
+	p_cara_profile_cfg->pri[2] = profile_cfg.cara_pri2;
+	p_cara_profile_cfg->pri[3] = profile_cfg.cara_pri3;
+	p_cara_profile_cfg->pri[4] = profile_cfg.cara_pri4;
+	p_cara_profile_cfg->pri[5] = profile_cfg.cara_pri5;
+	p_cara_profile_cfg->pri[6] = profile_cfg.cara_pri6;
+	p_cara_profile_cfg->pri[7] = profile_cfg.cara_pri7;
+
+	return rc;
+}
+
+/***********************************************************/
+/** 配置car A的qvos溢出模式
+ * @param   dev_id           设备号
+ * @param   flow_id          流号
+ * @param   qvos_mode        溢出模式，参见DPP_CAR_QVOS_MODE_E
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/06
+ ************************************************************/
+DPP_STATUS dpp_stat_cara_queue_qvos_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+										ZXIC_UINT32 qvos_mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_CARA_QOVS_RAM_RAM2_T qvos_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), qvos_mode, CAR_QVOS_MODE_OVERFLOW_0,
+							  CAR_QVOS_MODE_OVERFLOW_MAX - 1);
+
+	qvos_cfg.cara_qovs = qvos_mode;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_CARA_QOVS_RAM_RAM2r, 0, flow_id,
+					   &qvos_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取car A的qvos溢出模式
+ * @param   dev_id           设备号
+ * @param   flow_id          流号
+ * @param   p_qvos_mode      qvos溢出模式
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/06
+ ************************************************************/
+DPP_STATUS dpp_stat_cara_queue_qvos_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+										ZXIC_UINT32 *p_qvos_mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_CARA_QOVS_RAM_RAM2_T qvos_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qvos_mode);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_CARA_QOVS_RAM_RAM2r, 0, flow_id,
+					  &qvos_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_qvos_mode = qvos_cfg.cara_qovs;
+
+	return rc;
+}
+
+/***********************************************************/
+/** 设置第一级的映射关系
+ * @param   dev_id           设备号
+ * @param   flow_id          流号
+ * @param   map_flow_id      映射的流号
+ * @param   map_sp           映射的优先级
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/06
+ ************************************************************/
+DPP_STATUS dpp_stat_cara_queue_map_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									   ZXIC_UINT32 map_flow_id,
+									   ZXIC_UINT32 map_sp)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_LOOK_UP_TABLE1_T map_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_flow_id, 0,
+							  DPP_CAR_B_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_sp, DPP_CAR_PRI0,
+							  DPP_CAR_PRI_MAX - 1);
+
+	map_cfg.cara_flow_id = map_flow_id;
+	map_cfg.cara_sp = map_sp;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_LOOK_UP_TABLE1r, 0, flow_id, &map_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取第一级的映射关系
+ * @param   dev_id           设备号
+ * @param   flow_id          流号
+ * @param   p_map_flow_id    映射流号
+ * @param   p_map_sp         映射优先级
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/06
+ ************************************************************/
+DPP_STATUS dpp_stat_cara_queue_map_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									   ZXIC_UINT32 *p_map_flow_id,
+									   ZXIC_UINT32 *p_map_sp)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_LOOK_UP_TABLE1_T map_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_A_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_flow_id);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_sp);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_LOOK_UP_TABLE1r, 0, flow_id, &map_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_map_flow_id = map_cfg.cara_flow_id;
+	*p_map_sp = map_cfg.cara_sp;
+
+	return rc;
+}
+
+/***********************************************************/
+/** car A指定队列模式配置，仅用于调试
+ * @param   dev_id           设备号
+ * @param   global_en        全局队列使能，0-不使能，1-使能
+ * @param   sp_en            优先级队列使能，0-不使能，1-使能
+ * @param   appoint_sp       指定的优先级
+ * @param   appoint_queue    指定的队列号
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/06
+ ************************************************************/
+DPP_STATUS dpp_stat_cara_queue_appoint_mode_set(DPP_DEV_T *dev,
+												ZXIC_UINT32 global_en,
+												ZXIC_UINT32 sp_en,
+												ZXIC_UINT32 appoint_sp,
+												ZXIC_UINT32 appoint_queue)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_CARA_APPOINT_QNUM_OR_SP_T appoint_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), global_en, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sp_en, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), appoint_sp, DPP_CAR_PRI0,
+							  DPP_CAR_PRI_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), appoint_queue, 0,
+							  DPP_CAR_A_FLOW_ID_MAX);
+
+	appoint_cfg.cara_appoint_qnum_or_not = global_en;
+	appoint_cfg.cara_appoint_sp_or_not = sp_en;
+	appoint_cfg.cara_plcr_stat_sp = appoint_sp;
+	appoint_cfg.cara_plcr_stat_qnum = appoint_queue;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_CARA_APPOINT_QNUM_OR_SPr, 0, 0,
+					   &appoint_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取car A指定队列模式的配置
+ * @param   dev_id           设备号
+ * @param   p_global_en      全局队列使能，0-不使能，1-使能
+ * @param   p_sp_en          优先级队列使能，0-不使能，1-使能
+ * @param   p_appoint_sp     指定的优先级
+ * @param   p_appoint_queue  指定的队列号
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/07
+ ************************************************************/
+DPP_STATUS dpp_stat_cara_queue_appoint_mode_get(DPP_DEV_T *dev,
+												ZXIC_UINT32 *p_global_en,
+												ZXIC_UINT32 *p_sp_en,
+												ZXIC_UINT32 *p_appoint_sp,
+												ZXIC_UINT32 *p_appoint_queue)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_CARA_APPOINT_QNUM_OR_SP_T appoint_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_global_en);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_sp_en);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_appoint_sp);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_appoint_queue);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_CARA_APPOINT_QNUM_OR_SPr, 0, 0,
+					  &appoint_cfg);
+
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_global_en = appoint_cfg.cara_appoint_qnum_or_not;
+	*p_sp_en = appoint_cfg.cara_appoint_sp_or_not;
+	*p_appoint_sp = appoint_cfg.cara_plcr_stat_sp;
+	*p_appoint_queue = appoint_cfg.cara_plcr_stat_qnum;
+
+	return rc;
+}
+
+/***********************************************************/
+/** car A 调试计数读取模式配置
+ * @param   dev_id           设备号
+ * @param   overflow_mode    溢出模式，0-计数最大保持，1-计数最大翻转
+ * @param   rd_mode          读取模式，0-不读清，1-读清模式
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/06
+ ************************************************************/
+DPP_STATUS dpp_stat_cara_dbg_cnt_mode_set(DPP_DEV_T *dev,
+										  ZXIC_UINT32 overflow_mode,
+										  ZXIC_UINT32 rd_mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_CARA_CFGMT_COUNT_MODE_T cnt_mode_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), overflow_mode, CAR_KEEP_COUNT,
+							  CAR_RE_COUNT);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_mode, CAR_READ_NOT_CLEAR,
+							  CAR_READ_AND_CLEAR);
+
+	cnt_mode_cfg.cara_cfgmt_count_overflow_mode = overflow_mode;
+	cnt_mode_cfg.cara_cfgmt_count_rd_mode = rd_mode;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_CARA_CFGMT_COUNT_MODEr, 0, 0,
+					   &cnt_mode_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/** car A 调试计数读取模式获取
+ * @param   dev_id           设备号
+ * @param   p_overflow_mode
+ * @param   p_rd_mode
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/06
+ ************************************************************/
+DPP_STATUS dpp_stat_cara_dbg_cnt_mode_get(DPP_DEV_T *dev,
+										  ZXIC_UINT32 *p_overflow_mode,
+										  ZXIC_UINT32 *p_rd_mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_CARA_CFGMT_COUNT_MODE_T cnt_mode_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_overflow_mode);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_rd_mode);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_CARA_CFGMT_COUNT_MODEr, 0, 0,
+					  &cnt_mode_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_overflow_mode = cnt_mode_cfg.cara_cfgmt_count_overflow_mode;
+	*p_rd_mode = cnt_mode_cfg.cara_cfgmt_count_rd_mode;
+
+	return rc;
+}
+/***********************************************************/
+/** car B的流设置
+ * @param   dev_id           设备号
+ * @param   flow_id          流号
+ * @param   drop_flag        丢弃标志
+ * @param   plcr_en          监管使能
+ * @param   profile_id       监管模板号
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS dpp_stat_carb_queue_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									   ZXIC_UINT32 drop_flag,
+									   ZXIC_UINT32 plcr_en,
+									   ZXIC_UINT32 profile_id)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T queue_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), drop_flag, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), plcr_en, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+							  DPP_CAR_B_PROFILE_ID_MAX);
+
+	queue_cfg.carb_drop = drop_flag;
+	queue_cfg.carb_plcr_en = plcr_en;
+	queue_cfg.carb_profile_id = profile_id;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_CARB_QUEUE_RAM0_159_0r, 0, flow_id,
+					   &queue_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取car B的流设置
+ * @param   dev_id               设备号
+ * @param   flow_id              流号
+ * @param   p_carb_queue_cfg     car A流配置信息
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS
+dpp_stat_carb_queue_cfg_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+							DPP_STAT_CAR_B_QUEUE_CFG_T *p_carb_queue_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T queue_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carb_queue_cfg);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_CARB_QUEUE_RAM0_159_0r, 0, flow_id,
+					  &queue_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	p_carb_queue_cfg->flow_id = flow_id;
+	p_carb_queue_cfg->drop_flag = queue_cfg.carb_drop;
+	p_carb_queue_cfg->plcr_en = queue_cfg.carb_plcr_en;
+	p_carb_queue_cfg->profile_id = queue_cfg.carb_profile_id;
+
+	p_carb_queue_cfg->tq =
+			ZXIC_COMM_COUNTER64_BUILD(queue_cfg.carb_tq_h, queue_cfg.carb_tq_l);
+
+	p_carb_queue_cfg->tce_flag = queue_cfg.carb_ted;
+	p_carb_queue_cfg->tce = queue_cfg.carb_tcd;
+	p_carb_queue_cfg->te = queue_cfg.carb_tei;
+	p_carb_queue_cfg->tc = queue_cfg.carb_tci;
+
+	return rc;
+}
+
+/***********************************************************/
+/** car B监管模板设定
+ * @param   dev_id               设备号
+ * @param   profile_id           监管模板号
+ * @param   p_carb_profile_cfg   监管模板配置
+ *          pkt_sign 包限速标记写死成0，防止用户在carB包限速
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS
+dpp_stat_carb_profile_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+							  DPP_STAT_CAR_PROFILE_CFG_T *p_carb_profile_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 i = 0;
+
+	DPP_STAT_CAR0_CARB_PROFILE_RAM1_255_0_T profile_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+							  DPP_CAR_B_PROFILE_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carb_profile_cfg);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->pkt_sign, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->cf, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->cm, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->random_disc_e, 0,
+							  1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->random_disc_c, 0,
+							  1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->cd,
+							  CAR_CD_MODE_SRTCM, CAR_CD_MODE_INVALID - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->cir, 0,
+							  DPP_CAR_MAX_CIR_VALUE);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->eir, 0,
+							  DPP_CAR_MAX_EIR_VALUE);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->cbs, 0,
+							  DPP_CAR_MAX_CBS_VALUE);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->ebs, 0,
+							  DPP_CAR_MAX_EBS_VALUE);
+
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->e_yellow_pri[0],
+							  0, DPP_CAR_MAX_PRI_VALUE);
+
+	for (i = 1; i < DPP_CAR_PRI_MAX; i++) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carb_profile_cfg->c_pri[i], 0,
+								  DPP_CAR_MAX_PRI_VALUE);
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev),
+								  p_carb_profile_cfg->e_green_pri[i], 0,
+								  DPP_CAR_MAX_PRI_VALUE);
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev),
+								  p_carb_profile_cfg->e_yellow_pri[i], 0,
+								  DPP_CAR_MAX_PRI_VALUE);
+	}
+
+	profile_cfg.carb_e_y_pri7 = p_carb_profile_cfg->e_yellow_pri[7];
+	profile_cfg.carb_e_y_pri6 = p_carb_profile_cfg->e_yellow_pri[6];
+	profile_cfg.carb_e_y_pri5 = p_carb_profile_cfg->e_yellow_pri[5];
+	profile_cfg.carb_e_y_pri4 = p_carb_profile_cfg->e_yellow_pri[4];
+	profile_cfg.carb_e_y_pri3 = p_carb_profile_cfg->e_yellow_pri[3];
+	profile_cfg.carb_e_y_pri2 = p_carb_profile_cfg->e_yellow_pri[2];
+	profile_cfg.carb_e_y_pri1 = p_carb_profile_cfg->e_yellow_pri[1];
+	profile_cfg.carb_e_y_pri0 = p_carb_profile_cfg->e_yellow_pri[0];
+
+	profile_cfg.carb_e_g_pri7 = p_carb_profile_cfg->e_green_pri[7];
+	profile_cfg.carb_e_g_pri6 = p_carb_profile_cfg->e_green_pri[6];
+	profile_cfg.carb_e_g_pri5 = p_carb_profile_cfg->e_green_pri[5];
+	profile_cfg.carb_e_g_pri4 = p_carb_profile_cfg->e_green_pri[4];
+	profile_cfg.carb_e_g_pri3 = p_carb_profile_cfg->e_green_pri[3];
+	profile_cfg.carb_e_g_pri2 = p_carb_profile_cfg->e_green_pri[2];
+	profile_cfg.carb_e_g_pri1 = p_carb_profile_cfg->e_green_pri[1];
+
+	profile_cfg.carb_c_pri7 = p_carb_profile_cfg->c_pri[7];
+	profile_cfg.carb_c_pri6 = p_carb_profile_cfg->c_pri[6];
+	profile_cfg.carb_c_pri5 = p_carb_profile_cfg->c_pri[5];
+	profile_cfg.carb_c_pri4 = p_carb_profile_cfg->c_pri[4];
+	profile_cfg.carb_c_pri3 = p_carb_profile_cfg->c_pri[3];
+	profile_cfg.carb_c_pri2 = p_carb_profile_cfg->c_pri[2];
+	profile_cfg.carb_c_pri1 = p_carb_profile_cfg->c_pri[1];
+
+	profile_cfg.carb_cbs = p_carb_profile_cfg->cbs;
+	profile_cfg.carb_ebs_pbs = p_carb_profile_cfg->ebs;
+	profile_cfg.carb_cir = p_carb_profile_cfg->cir;
+	profile_cfg.carb_eir = p_carb_profile_cfg->eir;
+
+	profile_cfg.carb_cd = p_carb_profile_cfg->cd;
+	profile_cfg.carb_cf = p_carb_profile_cfg->cf;
+	profile_cfg.carb_cm = p_carb_profile_cfg->cm;
+
+	profile_cfg.carb_random_discard_en_e = p_carb_profile_cfg->random_disc_e;
+	profile_cfg.carb_random_discard_en_c = p_carb_profile_cfg->random_disc_c;
+	/* B级car包限速标记写死为0，以免用户配置成1对CARB进行包限速 */
+	profile_cfg.carb_pkt_sign = 0;
+
+	profile_cfg.carb_profile_wr = 0;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_CARB_PROFILE_RAM1_255_0r, 0, profile_id,
+					   &profile_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取car B的监管模板配置
+ * @param   dev_id               设备号
+ * @param   profile_id           监管模板号
+ * @param   p_carb_profile_cfg   监管模板配置
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS
+dpp_stat_carb_profile_cfg_get(DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+							  DPP_STAT_CAR_PROFILE_CFG_T *p_carb_profile_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_STAT_CAR0_CARB_PROFILE_RAM1_255_0_T profile_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+							  DPP_CAR_B_PROFILE_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carb_profile_cfg);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_CARB_PROFILE_RAM1_255_0r, 0, profile_id,
+					  &profile_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	p_carb_profile_cfg->profile_id = profile_id;
+	p_carb_profile_cfg->pkt_sign = profile_cfg.carb_pkt_sign;
+	p_carb_profile_cfg->cd = profile_cfg.carb_cd;
+	p_carb_profile_cfg->cf = profile_cfg.carb_cf;
+	p_carb_profile_cfg->cm = profile_cfg.carb_cm;
+	p_carb_profile_cfg->eir = profile_cfg.carb_eir;
+	p_carb_profile_cfg->cir = profile_cfg.carb_cir;
+	p_carb_profile_cfg->ebs = profile_cfg.carb_ebs_pbs;
+	p_carb_profile_cfg->cbs = profile_cfg.carb_cbs;
+	p_carb_profile_cfg->random_disc_e = profile_cfg.carb_random_discard_en_e;
+	p_carb_profile_cfg->random_disc_c = profile_cfg.carb_random_discard_en_c;
+
+	p_carb_profile_cfg->c_pri[1] = profile_cfg.carb_c_pri1;
+	p_carb_profile_cfg->c_pri[2] = profile_cfg.carb_c_pri2;
+	p_carb_profile_cfg->c_pri[3] = profile_cfg.carb_c_pri3;
+	p_carb_profile_cfg->c_pri[4] = profile_cfg.carb_c_pri4;
+	p_carb_profile_cfg->c_pri[5] = profile_cfg.carb_c_pri5;
+	p_carb_profile_cfg->c_pri[6] = profile_cfg.carb_c_pri6;
+	p_carb_profile_cfg->c_pri[7] = profile_cfg.carb_c_pri7;
+
+	p_carb_profile_cfg->e_green_pri[1] = profile_cfg.carb_e_g_pri1;
+	p_carb_profile_cfg->e_green_pri[2] = profile_cfg.carb_e_g_pri2;
+	p_carb_profile_cfg->e_green_pri[3] = profile_cfg.carb_e_g_pri3;
+	p_carb_profile_cfg->e_green_pri[4] = profile_cfg.carb_e_g_pri4;
+	p_carb_profile_cfg->e_green_pri[5] = profile_cfg.carb_e_g_pri5;
+	p_carb_profile_cfg->e_green_pri[6] = profile_cfg.carb_e_g_pri6;
+	p_carb_profile_cfg->e_green_pri[7] = profile_cfg.carb_e_g_pri7;
+
+	p_carb_profile_cfg->e_yellow_pri[0] = profile_cfg.carb_e_y_pri0;
+	p_carb_profile_cfg->e_yellow_pri[1] = profile_cfg.carb_e_y_pri1;
+	p_carb_profile_cfg->e_yellow_pri[2] = profile_cfg.carb_e_y_pri2;
+	p_carb_profile_cfg->e_yellow_pri[3] = profile_cfg.carb_e_y_pri3;
+	p_carb_profile_cfg->e_yellow_pri[4] = profile_cfg.carb_e_y_pri4;
+	p_carb_profile_cfg->e_yellow_pri[5] = profile_cfg.carb_e_y_pri5;
+	p_carb_profile_cfg->e_yellow_pri[6] = profile_cfg.carb_e_y_pri6;
+	p_carb_profile_cfg->e_yellow_pri[7] = profile_cfg.carb_e_y_pri7;
+
+	return rc;
+}
+
+/***********************************************************/
+/** 配置car B的qvos溢出模式
+ * @param   dev_id           设备号
+ * @param   flow_id          流号
+ * @param   qvos_mode        溢出模式，参见DPP_CAR_QVOS_MODE_E
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/06
+ ************************************************************/
+DPP_STATUS dpp_stat_carb_queue_qvos_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+										ZXIC_UINT32 qvos_mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_CARB_QOVS_RAM_RAM2_T qvos_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), qvos_mode, CAR_QVOS_MODE_OVERFLOW_0,
+							  CAR_QVOS_MODE_OVERFLOW_MAX - 1);
+
+	qvos_cfg.carb_qovs = qvos_mode;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_CARB_QOVS_RAM_RAM2r, 0, flow_id,
+					   &qvos_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+/***********************************************************/
+/** 获取car B的qvos溢出模式
+ * @param   dev_id           设备号
+ * @param   flow_id          流号
+ * @param   p_qvos_mode      qvos溢出模式
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/06
+ ************************************************************/
+DPP_STATUS dpp_stat_carb_queue_qvos_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+										ZXIC_UINT32 *p_qvos_mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_CARB_QOVS_RAM_RAM2_T qvos_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qvos_mode);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_CARB_QOVS_RAM_RAM2r, 0, flow_id,
+					  &qvos_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_qvos_mode = qvos_cfg.carb_qovs;
+
+	return rc;
+}
+
+/***********************************************************/
+/** 设置第二级的映射关系
+ * @param   dev_id           设备号
+ * @param   flow_id          流号
+ * @param   map_flow_id      映射的流号
+ * @param   map_sp           映射的优先级
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/06
+ ************************************************************/
+DPP_STATUS dpp_stat_carb_queue_map_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									   ZXIC_UINT32 map_flow_id,
+									   ZXIC_UINT32 map_sp)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_LOOK_UP_TABLE2_T map_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_flow_id, 0,
+							  DPP_CAR_C_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_sp, DPP_CAR_PRI0,
+							  DPP_CAR_PRI_MAX - 1);
+
+	map_cfg.carb_flow_id = map_flow_id;
+	map_cfg.carb_sp = map_sp;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_LOOK_UP_TABLE2r, 0, flow_id, &map_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取第二级的映射关系
+ * @param   dev_id           设备号
+ * @param   flow_id          流号
+ * @param   p_map_flow_id    映射流号
+ * @param   p_map_sp         映射优先级
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/06
+ ************************************************************/
+DPP_STATUS dpp_stat_carb_queue_map_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									   ZXIC_UINT32 *p_map_flow_id,
+									   ZXIC_UINT32 *p_map_sp)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_LOOK_UP_TABLE2_T map_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_B_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_flow_id);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_sp);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_LOOK_UP_TABLE2r, 0, flow_id, &map_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_map_flow_id = map_cfg.carb_flow_id;
+	*p_map_sp = map_cfg.carb_sp;
+
+	return rc;
+}
+/***********************************************************/
+/**
+ * @param   dev_id
+ * @param   profile_id
+ * @param   p_random_ram
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  YXH      @date  2019/04/01
+ ************************************************************/
+DPP_STATUS dpp_stat_carb_random_ram_set(DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+										DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
+										DPP_CAR_RANDOM_RAM_T *p_random_ram_c)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT64 para0_temp = 0;
+	ZXIC_UINT64 para2_temp = 0;
+	ZXIC_UINT64 para4_temp = 0;
+	DPP_STAT_CAR0_CARB_RANDOM_RAM_T carb_random_ram_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p1, 0, 100);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p2, 0, 100);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p3, 0, 100);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p1, 0, 100);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p2, 0, 100);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p3, 0, 100);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+							  DPP_CAR_B_PROFILE_ID_RANDOM_MAX);
+
+	para0_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->t2)) -
+								 ((ZXIC_UINT64)(p_random_ram_e->t1))) *
+								((ZXIC_UINT64)(p_random_ram_e->p1)))
+				  << DPP_CAR_RANDOM_OFFSET_VAL) /
+				 100;
+	carb_random_ram_cfg.para0_l_e = (para0_temp & 0xFFFFFFFF);
+	carb_random_ram_cfg.para0_h_e = (para0_temp >> 32) & 0xFFFFFFFF;
+
+	carb_random_ram_cfg.para1_e = ((p_random_ram_e->p2 - p_random_ram_e->p1)
+								   << DPP_CAR_RANDOM_OFFSET_VAL) /
+								  100;
+
+	para2_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->t3)) -
+								 ((ZXIC_UINT64)(p_random_ram_e->t2))) *
+								((ZXIC_UINT64)(p_random_ram_e->p2)))
+				  << DPP_CAR_RANDOM_OFFSET_VAL) /
+				 100;
+	carb_random_ram_cfg.para2_l_e = (para2_temp & 0xFFFFFFFF);
+	carb_random_ram_cfg.para2_h_e = (para2_temp >> 32) & 0xFFFFFFFF;
+
+	carb_random_ram_cfg.para3_e = ((p_random_ram_e->p3 - p_random_ram_e->p2)
+								   << DPP_CAR_RANDOM_OFFSET_VAL) /
+								  100;
+
+	para4_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->tc)) -
+								 ((ZXIC_UINT64)(p_random_ram_e->t3))) *
+								((ZXIC_UINT64)(p_random_ram_e->p3)))
+				  << DPP_CAR_RANDOM_OFFSET_VAL) /
+				 100;
+	carb_random_ram_cfg.para4_l_e = (para4_temp & 0xFFFFFFFF);
+	carb_random_ram_cfg.para4_h_e = (para4_temp >> 32) & 0xFFFFFFFF;
+
+	carb_random_ram_cfg.para5_e =
+			((100 - p_random_ram_e->p3) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
+	carb_random_ram_cfg.para6_e = p_random_ram_e->t1;
+	carb_random_ram_cfg.para7_e = p_random_ram_e->t2;
+	carb_random_ram_cfg.para8_e = p_random_ram_e->t3;
+
+	/* para0_temp = 0;
+    para2_temp = 0;
+    para4_temp = 0; */
+
+	para0_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->t2)) -
+								 ((ZXIC_UINT64)(p_random_ram_c->t1))) *
+								((ZXIC_UINT64)(p_random_ram_c->p1)))
+				  << DPP_CAR_RANDOM_OFFSET_VAL) /
+				 100;
+	carb_random_ram_cfg.para0_l_c = (para0_temp & 0xFFFFFFFF);
+	carb_random_ram_cfg.para0_h_c = (para0_temp >> 32) & 0xFFFFFFFF;
+
+	carb_random_ram_cfg.para1_c = ((p_random_ram_c->p2 - p_random_ram_c->p1)
+								   << DPP_CAR_RANDOM_OFFSET_VAL) /
+								  100;
+
+	para2_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->t3)) -
+								 ((ZXIC_UINT64)(p_random_ram_c->t2))) *
+								((ZXIC_UINT64)(p_random_ram_c->p2)))
+				  << DPP_CAR_RANDOM_OFFSET_VAL) /
+				 100;
+	carb_random_ram_cfg.para2_l_c = (para2_temp & 0xFFFFFFFF);
+	carb_random_ram_cfg.para2_h_c = (para2_temp >> 32) & 0xFFFFFFFF;
+
+	carb_random_ram_cfg.para3_c = ((p_random_ram_c->p3 - p_random_ram_c->p2)
+								   << DPP_CAR_RANDOM_OFFSET_VAL) /
+								  100;
+
+	para4_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->tc)) -
+								 ((ZXIC_UINT64)(p_random_ram_c->t3))) *
+								((ZXIC_UINT64)(p_random_ram_c->p3)))
+				  << DPP_CAR_RANDOM_OFFSET_VAL) /
+				 100;
+	carb_random_ram_cfg.para4_l_c = (para4_temp & 0xFFFFFFFF);
+	carb_random_ram_cfg.para4_h_c = (para4_temp >> 32) & 0xFFFFFFFF;
+
+	carb_random_ram_cfg.para5_c =
+			((100 - p_random_ram_c->p3) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
+	carb_random_ram_cfg.para6_c = p_random_ram_c->t1;
+	carb_random_ram_cfg.para7_c = p_random_ram_c->t2;
+	carb_random_ram_cfg.para8_c = p_random_ram_c->t3;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_CARB_RANDOM_RAMr, 0, profile_id,
+					   &carb_random_ram_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/**
+ * @param   dev_id
+ * @param   p_random_ram
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  YXH      @date  2019/04/01
+ ************************************************************/
+DPP_STATUS dpp_stat_carb_random_ram_get(DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+										DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
+										DPP_CAR_RANDOM_RAM_T *p_random_ram_c)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_CARB_RANDOM_RAM_T carb_random_ram_cfg = { 0 };
+	ZXIC_UINT32 tmp_val = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+							  DPP_CAR_B_PROFILE_ID_RANDOM_MAX);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_CARB_RANDOM_RAMr, 0, profile_id,
+					  &carb_random_ram_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	p_random_ram_e->t1 = carb_random_ram_cfg.para6_e;
+	p_random_ram_e->t2 = carb_random_ram_cfg.para7_e;
+	p_random_ram_e->t3 = carb_random_ram_cfg.para8_e;
+	tmp_val = (carb_random_ram_cfg.para5_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
+	p_random_ram_e->p3 = 100 - tmp_val;
+	tmp_val = (carb_random_ram_cfg.para3_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
+	p_random_ram_e->p2 = p_random_ram_e->p3 - tmp_val;
+	tmp_val = (carb_random_ram_cfg.para1_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
+	p_random_ram_e->p1 = p_random_ram_e->p2 - tmp_val;
+
+	p_random_ram_c->t1 = carb_random_ram_cfg.para6_c;
+	p_random_ram_c->t2 = carb_random_ram_cfg.para7_c;
+	p_random_ram_c->t3 = carb_random_ram_cfg.para8_c;
+	tmp_val = (carb_random_ram_cfg.para5_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
+	p_random_ram_c->p3 = 100 - tmp_val;
+	tmp_val = (carb_random_ram_cfg.para3_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
+	p_random_ram_c->p2 = p_random_ram_c->p3 - tmp_val;
+	tmp_val = (carb_random_ram_cfg.para1_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
+	p_random_ram_c->p1 = p_random_ram_c->p2 - tmp_val;
+
+	return rc;
+}
+
+/***********************************************************/
+/** car C的流设置
+ * @param   dev_id           设备号           car编号
+ * @param   flow_id          流号
+ * @param   drop_flag        丢弃标志
+ * @param   plcr_en          监管使能
+ * @param   profile_id       监管模板号
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS dpp_stat_carc_queue_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									   ZXIC_UINT32 drop_flag,
+									   ZXIC_UINT32 plcr_en,
+									   ZXIC_UINT32 profile_id)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T queue_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), drop_flag, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), plcr_en, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+							  DPP_CAR_C_PROFILE_ID_MAX);
+
+	queue_cfg.carc_drop = drop_flag;
+	queue_cfg.carc_plcr_en = plcr_en;
+	queue_cfg.carc_profile_id = profile_id;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_CARC_QUEUE_RAM0_159_0r, 0, flow_id,
+					   &queue_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取car C的流设置
+ * @param   dev_id               设备号               car编号
+ * @param   flow_id              流号
+ * @param   p_carc_queue_cfg     car c流配置信息
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS
+dpp_stat_carc_queue_cfg_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+							DPP_STAT_CAR_C_QUEUE_CFG_T *p_carc_queue_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T queue_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carc_queue_cfg);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_CARC_QUEUE_RAM0_159_0r, 0, flow_id,
+					  &queue_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	p_carc_queue_cfg->flow_id = flow_id;
+	p_carc_queue_cfg->drop_flag = queue_cfg.carc_drop;
+	p_carc_queue_cfg->plcr_en = queue_cfg.carc_plcr_en;
+	p_carc_queue_cfg->profile_id = queue_cfg.carc_profile_id;
+
+	p_carc_queue_cfg->tq =
+			ZXIC_COMM_COUNTER64_BUILD(queue_cfg.carc_tq_h, queue_cfg.carc_tq_l);
+
+	p_carc_queue_cfg->tce_flag = queue_cfg.carc_ted;
+	p_carc_queue_cfg->tce = queue_cfg.carc_tcd;
+	p_carc_queue_cfg->te = queue_cfg.carc_tei;
+	p_carc_queue_cfg->tc = queue_cfg.carc_tci;
+
+	return rc;
+}
+
+/***********************************************************/
+/** car C监管模板设定
+ * @param   dev_id               设备号               car编号
+ * @param   profile_id           监管模板号
+ * @param   p_carc_profile_cfg   监管模板配置
+ *          pkt_sign 包限速标记写死成0，防止用户在carC包限速
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS
+dpp_stat_carc_profile_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+							  DPP_STAT_CAR_PROFILE_CFG_T *p_carc_profile_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 i = 0;
+
+	DPP_STAT_CAR0_CARC_PROFILE_RAM1_255_0_T profile_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+							  DPP_CAR_C_PROFILE_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carc_profile_cfg);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->pkt_sign, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->cf, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->cm, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->random_disc_e, 0,
+							  1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->random_disc_c, 0,
+							  1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->cd,
+							  CAR_CD_MODE_SRTCM, CAR_CD_MODE_INVALID - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->cir, 0,
+							  DPP_CAR_MAX_CIR_VALUE);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->eir, 0,
+							  DPP_CAR_MAX_EIR_VALUE);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->cbs, 0,
+							  DPP_CAR_MAX_CBS_VALUE);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->ebs, 0,
+							  DPP_CAR_MAX_EBS_VALUE);
+
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->e_yellow_pri[0],
+							  0, DPP_CAR_MAX_PRI_VALUE);
+
+	for (i = 1; i < DPP_CAR_PRI_MAX; i++) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_carc_profile_cfg->c_pri[i], 0,
+								  DPP_CAR_MAX_PRI_VALUE);
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev),
+								  p_carc_profile_cfg->e_green_pri[i], 0,
+								  DPP_CAR_MAX_PRI_VALUE);
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev),
+								  p_carc_profile_cfg->e_yellow_pri[i], 0,
+								  DPP_CAR_MAX_PRI_VALUE);
+	}
+
+	profile_cfg.carc_e_y_pri7 = p_carc_profile_cfg->e_yellow_pri[7];
+	profile_cfg.carc_e_y_pri6 = p_carc_profile_cfg->e_yellow_pri[6];
+	profile_cfg.carc_e_y_pri5 = p_carc_profile_cfg->e_yellow_pri[5];
+	profile_cfg.carc_e_y_pri4 = p_carc_profile_cfg->e_yellow_pri[4];
+	profile_cfg.carc_e_y_pri3 = p_carc_profile_cfg->e_yellow_pri[3];
+	profile_cfg.carc_e_y_pri2 = p_carc_profile_cfg->e_yellow_pri[2];
+	profile_cfg.carc_e_y_pri1 = p_carc_profile_cfg->e_yellow_pri[1];
+	profile_cfg.carc_e_y_pri0 = p_carc_profile_cfg->e_yellow_pri[0];
+
+	profile_cfg.carc_e_g_pri7 = p_carc_profile_cfg->e_green_pri[7];
+	profile_cfg.carc_e_g_pri6 = p_carc_profile_cfg->e_green_pri[6];
+	profile_cfg.carc_e_g_pri5 = p_carc_profile_cfg->e_green_pri[5];
+	profile_cfg.carc_e_g_pri4 = p_carc_profile_cfg->e_green_pri[4];
+	profile_cfg.carc_e_g_pri3 = p_carc_profile_cfg->e_green_pri[3];
+	profile_cfg.carc_e_g_pri2 = p_carc_profile_cfg->e_green_pri[2];
+	profile_cfg.carc_e_g_pri1 = p_carc_profile_cfg->e_green_pri[1];
+
+	profile_cfg.carc_c_pri7 = p_carc_profile_cfg->c_pri[7];
+	profile_cfg.carc_c_pri6 = p_carc_profile_cfg->c_pri[6];
+	profile_cfg.carc_c_pri5 = p_carc_profile_cfg->c_pri[5];
+	profile_cfg.carc_c_pri4 = p_carc_profile_cfg->c_pri[4];
+	profile_cfg.carc_c_pri3 = p_carc_profile_cfg->c_pri[3];
+	profile_cfg.carc_c_pri2 = p_carc_profile_cfg->c_pri[2];
+	profile_cfg.carc_c_pri1 = p_carc_profile_cfg->c_pri[1];
+
+	profile_cfg.carc_cbs = p_carc_profile_cfg->cbs;
+	profile_cfg.carc_ebs_pbs = p_carc_profile_cfg->ebs;
+	profile_cfg.carc_cir = p_carc_profile_cfg->cir;
+	profile_cfg.carc_eir = p_carc_profile_cfg->eir;
+
+	profile_cfg.carc_cd = p_carc_profile_cfg->cd;
+	profile_cfg.carc_cf = p_carc_profile_cfg->cf;
+	profile_cfg.carc_cm = p_carc_profile_cfg->cm;
+	profile_cfg.carc_random_discard_en_e = p_carc_profile_cfg->random_disc_e;
+	profile_cfg.carc_random_discard_en_c = p_carc_profile_cfg->random_disc_c;
+	/* C级car包限速标记写死为0，以免用户配置成1对CARC进行包限速 */
+	profile_cfg.carc_pkt_sign = 0;
+
+	profile_cfg.carc_profile_wr = 0;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_CARC_PROFILE_RAM1_255_0r, 0, profile_id,
+					   &profile_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取car C的监管模板配置
+ * @param   dev_id               设备号               car编号
+ * @param   profile_id           监管模板号
+ * @param   p_carc_profile_cfg   监管模板配置
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/05
+ ************************************************************/
+DPP_STATUS
+dpp_stat_carc_profile_cfg_get(DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+							  DPP_STAT_CAR_PROFILE_CFG_T *p_carc_profile_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_CARC_PROFILE_RAM1_255_0_T profile_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+							  DPP_CAR_C_PROFILE_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_carc_profile_cfg);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_CARC_PROFILE_RAM1_255_0r, 0, profile_id,
+					  &profile_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	p_carc_profile_cfg->profile_id = profile_id;
+	p_carc_profile_cfg->pkt_sign = profile_cfg.carc_pkt_sign;
+	p_carc_profile_cfg->cd = profile_cfg.carc_cd;
+	p_carc_profile_cfg->cf = profile_cfg.carc_cf;
+	p_carc_profile_cfg->cm = profile_cfg.carc_cm;
+
+	p_carc_profile_cfg->eir = profile_cfg.carc_eir;
+	p_carc_profile_cfg->cir = profile_cfg.carc_cir;
+	p_carc_profile_cfg->ebs = profile_cfg.carc_ebs_pbs;
+	p_carc_profile_cfg->cbs = profile_cfg.carc_cbs;
+
+	p_carc_profile_cfg->random_disc_e = profile_cfg.carc_random_discard_en_e;
+	p_carc_profile_cfg->random_disc_c = profile_cfg.carc_random_discard_en_c;
+
+	p_carc_profile_cfg->c_pri[1] = profile_cfg.carc_c_pri1;
+	p_carc_profile_cfg->c_pri[2] = profile_cfg.carc_c_pri2;
+	p_carc_profile_cfg->c_pri[3] = profile_cfg.carc_c_pri3;
+	p_carc_profile_cfg->c_pri[4] = profile_cfg.carc_c_pri4;
+	p_carc_profile_cfg->c_pri[5] = profile_cfg.carc_c_pri5;
+	p_carc_profile_cfg->c_pri[6] = profile_cfg.carc_c_pri6;
+	p_carc_profile_cfg->c_pri[7] = profile_cfg.carc_c_pri7;
+
+	p_carc_profile_cfg->e_green_pri[1] = profile_cfg.carc_e_g_pri1;
+	p_carc_profile_cfg->e_green_pri[2] = profile_cfg.carc_e_g_pri2;
+	p_carc_profile_cfg->e_green_pri[3] = profile_cfg.carc_e_g_pri3;
+	p_carc_profile_cfg->e_green_pri[4] = profile_cfg.carc_e_g_pri4;
+	p_carc_profile_cfg->e_green_pri[5] = profile_cfg.carc_e_g_pri5;
+	p_carc_profile_cfg->e_green_pri[6] = profile_cfg.carc_e_g_pri6;
+	p_carc_profile_cfg->e_green_pri[7] = profile_cfg.carc_e_g_pri7;
+
+	p_carc_profile_cfg->e_yellow_pri[0] = profile_cfg.carc_e_y_pri0;
+	p_carc_profile_cfg->e_yellow_pri[1] = profile_cfg.carc_e_y_pri1;
+	p_carc_profile_cfg->e_yellow_pri[2] = profile_cfg.carc_e_y_pri2;
+	p_carc_profile_cfg->e_yellow_pri[3] = profile_cfg.carc_e_y_pri3;
+	p_carc_profile_cfg->e_yellow_pri[4] = profile_cfg.carc_e_y_pri4;
+	p_carc_profile_cfg->e_yellow_pri[5] = profile_cfg.carc_e_y_pri5;
+	p_carc_profile_cfg->e_yellow_pri[6] = profile_cfg.carc_e_y_pri6;
+	p_carc_profile_cfg->e_yellow_pri[7] = profile_cfg.carc_e_y_pri7;
+
+	return rc;
+}
+
+/***********************************************************/
+/** 配置car C的qvos溢出模式
+ * @param   dev_id           设备号           car编号
+ * @param   flow_id          流号
+ * @param   qvos_mode        溢出模式，参见DPP_CAR_QVOS_MODE_E
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/06
+ ************************************************************/
+DPP_STATUS dpp_stat_carc_queue_qvos_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+										ZXIC_UINT32 qvos_mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_CARC_QOVS_RAM_RAM2_T qvos_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), qvos_mode, CAR_QVOS_MODE_OVERFLOW_0,
+							  CAR_QVOS_MODE_OVERFLOW_MAX - 1);
+
+	qvos_cfg.carc_qovs = qvos_mode;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_CARC_QOVS_RAM_RAM2r, 0, flow_id,
+					   &qvos_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+/***********************************************************/
+/** 获取car C的qvos溢出模式
+ * @param   dev_id           设备号           car编号
+ * @param   flow_id          流号
+ * @param   p_qvos_mode      qvos溢出模式
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/04/06
+ ************************************************************/
+DPP_STATUS dpp_stat_carc_queue_qvos_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+										ZXIC_UINT32 *p_qvos_mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_CARC_QOVS_RAM_RAM2_T qvos_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0, DPP_CAR_C_FLOW_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qvos_mode);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_CARC_QOVS_RAM_RAM2r, 0, flow_id,
+					  &qvos_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_qvos_mode = qvos_cfg.carc_qovs;
+
+	return rc;
+}
+/***********************************************************/
+/**
+ * @param   dev_id
+ * @param   profile_id
+ * @param   p_random_ram
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  YXH      @date  2019/04/01
+ ************************************************************/
+DPP_STATUS dpp_stat_carc_random_ram_set(DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+										DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
+										DPP_CAR_RANDOM_RAM_T *p_random_ram_c)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT64 para0_temp = 0;
+	ZXIC_UINT64 para2_temp = 0;
+	ZXIC_UINT64 para4_temp = 0;
+	DPP_STAT_CAR0_CARC_RANDOM_RAM_T carc_random_ram_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p1, 0, 100);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p2, 0, 100);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_e->p3, 0, 100);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p1, 0, 100);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p2, 0, 100);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_random_ram_c->p3, 0, 100);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+							  DPP_CAR_C_PROFILE_ID_RANDOM_MAX);
+
+	para0_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->t2)) -
+								 ((ZXIC_UINT64)(p_random_ram_e->t1))) *
+								((ZXIC_UINT64)(p_random_ram_e->p1)))
+				  << DPP_CAR_RANDOM_OFFSET_VAL) /
+				 100;
+	carc_random_ram_cfg.para0_l_e = (para0_temp & 0xFFFFFFFF);
+	carc_random_ram_cfg.para0_h_e = (para0_temp >> 32) & 0xFFFFFFFF;
+
+	carc_random_ram_cfg.para1_e = ((p_random_ram_e->p2 - p_random_ram_e->p1)
+								   << DPP_CAR_RANDOM_OFFSET_VAL) /
+								  100;
+
+	para2_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->t3)) -
+								 ((ZXIC_UINT64)(p_random_ram_e->t2))) *
+								((ZXIC_UINT64)(p_random_ram_e->p2)))
+				  << DPP_CAR_RANDOM_OFFSET_VAL) /
+				 100;
+	carc_random_ram_cfg.para2_l_e = (para2_temp & 0xFFFFFFFF);
+	carc_random_ram_cfg.para2_h_e = (para2_temp >> 32) & 0xFFFFFFFF;
+
+	carc_random_ram_cfg.para3_e = ((p_random_ram_e->p3 - p_random_ram_e->p2)
+								   << DPP_CAR_RANDOM_OFFSET_VAL) /
+								  100;
+
+	para4_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_e->tc)) -
+								 ((ZXIC_UINT64)(p_random_ram_e->t3))) *
+								((ZXIC_UINT64)(p_random_ram_e->p3)))
+				  << DPP_CAR_RANDOM_OFFSET_VAL) /
+				 100;
+	carc_random_ram_cfg.para4_l_e = (para4_temp & 0xFFFFFFFF);
+	carc_random_ram_cfg.para4_h_e = (para4_temp >> 32) & 0xFFFFFFFF;
+
+	carc_random_ram_cfg.para5_e =
+			((100 - p_random_ram_e->p3) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
+	carc_random_ram_cfg.para6_e = p_random_ram_e->t1;
+	carc_random_ram_cfg.para7_e = p_random_ram_e->t2;
+	carc_random_ram_cfg.para8_e = p_random_ram_e->t3;
+
+	/* para0_temp = 0;
+    para2_temp = 0;
+    para4_temp = 0; */
+
+	para0_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->t2)) -
+								 ((ZXIC_UINT64)(p_random_ram_c->t1))) *
+								((ZXIC_UINT64)(p_random_ram_c->p1)))
+				  << DPP_CAR_RANDOM_OFFSET_VAL) /
+				 100;
+	carc_random_ram_cfg.para0_l_c = (para0_temp & 0xFFFFFFFF);
+	carc_random_ram_cfg.para0_h_c = (para0_temp >> 32) & 0xFFFFFFFF;
+
+	carc_random_ram_cfg.para1_c = ((p_random_ram_c->p2 - p_random_ram_c->p1)
+								   << DPP_CAR_RANDOM_OFFSET_VAL) /
+								  100;
+
+	para2_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->t3)) -
+								 ((ZXIC_UINT64)(p_random_ram_c->t2))) *
+								((ZXIC_UINT64)(p_random_ram_c->p2)))
+				  << DPP_CAR_RANDOM_OFFSET_VAL) /
+				 100;
+	carc_random_ram_cfg.para2_l_c = (para2_temp & 0xFFFFFFFF);
+	carc_random_ram_cfg.para2_h_c = (para2_temp >> 32) & 0xFFFFFFFF;
+
+	carc_random_ram_cfg.para3_c = ((p_random_ram_c->p3 - p_random_ram_c->p2)
+								   << DPP_CAR_RANDOM_OFFSET_VAL) /
+								  100;
+
+	para4_temp = ((ZXIC_UINT64)((((ZXIC_UINT64)(p_random_ram_c->tc)) -
+								 ((ZXIC_UINT64)(p_random_ram_c->t3))) *
+								((ZXIC_UINT64)(p_random_ram_c->p3)))
+				  << DPP_CAR_RANDOM_OFFSET_VAL) /
+				 100;
+	carc_random_ram_cfg.para4_l_c = (para4_temp & 0xFFFFFFFF);
+	carc_random_ram_cfg.para4_h_c = (para4_temp >> 32) & 0xFFFFFFFF;
+
+	carc_random_ram_cfg.para5_c =
+			((100 - p_random_ram_c->p3) << DPP_CAR_RANDOM_OFFSET_VAL) / 100;
+	carc_random_ram_cfg.para6_c = p_random_ram_c->t1;
+	carc_random_ram_cfg.para7_c = p_random_ram_c->t2;
+	carc_random_ram_cfg.para8_c = p_random_ram_c->t3;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_CARC_RANDOM_RAMr, 0, profile_id,
+					   &carc_random_ram_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/**
+ * @param   dev_id
+ * @param   p_random_ram
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  YXH      @date  2019/04/01
+ ************************************************************/
+DPP_STATUS dpp_stat_carc_random_ram_get(DPP_DEV_T *dev, ZXIC_UINT32 profile_id,
+										DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
+										DPP_CAR_RANDOM_RAM_T *p_random_ram_c)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_CARB_RANDOM_RAM_T carc_random_ram_cfg = { 0 };
+	ZXIC_UINT32 tmp_val = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+							  DPP_CAR_C_PROFILE_ID_RANDOM_MAX);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_CARC_RANDOM_RAMr, 0, profile_id,
+					  &carc_random_ram_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	p_random_ram_e->t1 = carc_random_ram_cfg.para6_e;
+	p_random_ram_e->t2 = carc_random_ram_cfg.para7_e;
+	p_random_ram_e->t3 = carc_random_ram_cfg.para8_e;
+	tmp_val = (carc_random_ram_cfg.para5_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
+	p_random_ram_e->p3 = 100 - tmp_val;
+	tmp_val = (carc_random_ram_cfg.para3_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
+	p_random_ram_e->p2 = p_random_ram_e->p3 - tmp_val;
+	tmp_val = (carc_random_ram_cfg.para1_e * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
+	p_random_ram_e->p1 = p_random_ram_e->p2 - tmp_val;
+
+	p_random_ram_c->t1 = carc_random_ram_cfg.para6_c;
+	p_random_ram_c->t2 = carc_random_ram_cfg.para7_c;
+	p_random_ram_c->t3 = carc_random_ram_cfg.para8_c;
+	tmp_val = (carc_random_ram_cfg.para5_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
+	p_random_ram_c->p3 = 100 - tmp_val;
+	tmp_val = (carc_random_ram_cfg.para3_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
+	p_random_ram_c->p2 = p_random_ram_c->p3 - tmp_val;
+	tmp_val = (carc_random_ram_cfg.para1_c * 100) >> DPP_CAR_RANDOM_OFFSET_VAL;
+	p_random_ram_c->p1 = p_random_ram_c->p2 - tmp_val;
+
+	return rc;
+}
+
+/***********************************************************/
+/** 配置car的层级模式
+ * @param   dev_id
+ * @param   mode   2 - 三级car, 第一级支持16K
+ *                 1 - 两级car, 第一级扩展为17K
+ *                 0 - 一级car, 第一级扩展为21K
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/09/28
+ ************************************************************/
+DPP_STATUS dpp_stat_car_en_mode_set(DPP_DEV_T *dev, ZXIC_UINT32 mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_CAR_HIERARCHY_MODE_T car_en_mode_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), mode, DPP_CAR_EN_MODE_BOTH_EN,
+							  DPP_CAR_EN_MODE_INVALID - 1);
+
+	car_en_mode_cfg.car_hierarchy_mode = mode;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_CAR_HIERARCHY_MODEr, 0, 0,
+					   &car_en_mode_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/**
+ * @param   dev_id
+ * @param   p_mode
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/09/28
+ ************************************************************/
+DPP_STATUS dpp_stat_car_en_mode_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_CAR_HIERARCHY_MODE_T car_en_mode_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mode);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_CAR_HIERARCHY_MODEr, 0, 0,
+					  &car_en_mode_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_mode = car_en_mode_cfg.car_hierarchy_mode;
+
+	return rc;
+}
+
+/***********************************************************/
+/** 配置car的包长偏移
+ * @param   dev_id
+ * @param   pkt_size_off
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wll      @date  2019/06/06
+ ************************************************************/
+DPP_STATUS dpp_stat_car_pkt_size_offset_set(DPP_DEV_T *dev,
+											ZXIC_UINT32 pkt_size_off)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_PKT_SIZE_OFFSET_T car_pkt_size_offset = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pkt_size_off, 0, 0xffffffff);
+
+	car_pkt_size_offset.pkt_size_offset = pkt_size_off;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_PKT_SIZE_OFFSETr, 0, 0,
+					   &car_pkt_size_offset);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取car的包长偏移
+ * @param   dev_id
+ * @param   p_pkt_size_off
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wll      @date  2019/06/06
+ ************************************************************/
+DPP_STATUS dpp_stat_car_pkt_size_offset_get(DPP_DEV_T *dev,
+											ZXIC_UINT32 *p_pkt_size_off)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_PKT_SIZE_OFFSET_T car_pkt_size_offset = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_pkt_size_off);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_PKT_SIZE_OFFSETr, 0, 0,
+					  &car_pkt_size_offset);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_pkt_size_off = car_pkt_size_offset.pkt_size_offset;
+
+	return rc;
+}
+
+/***********************************************************/
+/** 配置cara的最大包长
+ * @param   dev_id
+ * @param   max_pkt_size
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wll      @date  2019/06/06
+ ************************************************************/
+DPP_STATUS dpp_stat_cara_max_pkt_size_set(DPP_DEV_T *dev,
+										  ZXIC_UINT32 max_pkt_size)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_MAX_PKT_SIZE_A_T car_max_pkt_size = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), max_pkt_size, 0, 0x3fff);
+
+	car_max_pkt_size.max_pkt_size_a = max_pkt_size;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_MAX_PKT_SIZE_Ar, 0, 0, &car_max_pkt_size);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取cara的最大包长
+ * @param   dev_id
+ * @param   p_max_pkt_size
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wll      @date  2019/06/06
+ ************************************************************/
+DPP_STATUS dpp_stat_cara_max_pkt_size_get(DPP_DEV_T *dev,
+										  ZXIC_UINT32 *p_max_pkt_size)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_MAX_PKT_SIZE_A_T car_max_pkt_size = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_max_pkt_size);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_MAX_PKT_SIZE_Ar, 0, 0, &car_max_pkt_size);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_max_pkt_size = car_max_pkt_size.max_pkt_size_a;
+
+	return rc;
+}
+
+/***********************************************************/
+/** 配置carb的最大包长
+ * @param   dev_id
+ * @param   max_pkt_size
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wll      @date  2019/06/06
+ ************************************************************/
+DPP_STATUS dpp_stat_carb_max_pkt_size_set(DPP_DEV_T *dev,
+										  ZXIC_UINT32 max_pkt_size)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_MAX_PKT_SIZE_B_T car_max_pkt_size = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), max_pkt_size, 0, 0x3fff);
+
+	car_max_pkt_size.max_pkt_size_b = max_pkt_size;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_MAX_PKT_SIZE_Br, 0, 0, &car_max_pkt_size);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取carb的最大包长
+ * @param   dev_id
+ * @param   p_max_pkt_size
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wll      @date  2019/06/06
+ ************************************************************/
+DPP_STATUS dpp_stat_carb_max_pkt_size_get(DPP_DEV_T *dev,
+										  ZXIC_UINT32 *p_max_pkt_size)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_MAX_PKT_SIZE_B_T car_max_pkt_size = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_max_pkt_size);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_MAX_PKT_SIZE_Br, 0, 0, &car_max_pkt_size);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_max_pkt_size = car_max_pkt_size.max_pkt_size_b;
+
+	return rc;
+}
+
+/***********************************************************/
+/** 配置carc的最大包长
+ * @param   dev_id
+ * @param   max_pkt_size
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wll      @date  2019/06/06
+ ************************************************************/
+DPP_STATUS dpp_stat_carc_max_pkt_size_set(DPP_DEV_T *dev,
+										  ZXIC_UINT32 max_pkt_size)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_MAX_PKT_SIZE_C_T car_max_pkt_size = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), max_pkt_size, 0, 0x3fff);
+
+	car_max_pkt_size.max_pkt_size_c = max_pkt_size;
+
+	rc = dpp_reg_write(dev, STAT_CAR0_MAX_PKT_SIZE_Cr, 0, 0, &car_max_pkt_size);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取carc的最大包长
+ * @param   dev_id
+ * @param   p_max_pkt_size
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wll      @date  2019/06/06
+ ************************************************************/
+DPP_STATUS dpp_stat_carc_max_pkt_size_get(DPP_DEV_T *dev,
+										  ZXIC_UINT32 *p_max_pkt_size)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR0_MAX_PKT_SIZE_C_T car_max_pkt_size = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_max_pkt_size);
+
+	rc = dpp_reg_read(dev, STAT_CAR0_MAX_PKT_SIZE_Cr, 0, 0, &car_max_pkt_size);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_max_pkt_size = car_max_pkt_size.max_pkt_size_c;
+
+	return rc;
+}
+
+#endif
+
+#if ZXIC_REAL("Advanced Function")
+/***********************************************************/
+/** car 模块流配置
+ * @param   dev_id       设备号
+ * @param   car_type     car模式，参见STAT_CAR_TYPE_E
+ * @param   flow_id      队列号
+ * @param   drop_flag    丢弃标志
+ * @param   plcr_en      限速使能
+ * @param   profile_id   模板编号
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/05/06
+ ************************************************************/
+DPP_STATUS dpp_stat_car_queue_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+									  ZXIC_UINT32 flow_id,
+									  ZXIC_UINT32 drop_flag,
+									  ZXIC_UINT32 plcr_en,
+									  ZXIC_UINT32 profile_id)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 flow_num = 0;
+
+	DPP_CAR_SOFT_RESET_DATA_T *p_restore_data = NULL; /* 软复位相关 */
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE,
+							  STAT_CAR_MAX_TYPE - 1);
+
+	if (STAT_CAR_A_TYPE == car_type) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0,
+								  DPP_CAR_A_FLOW_ID_MAX);
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+								  DPP_CAR_A_PROFILE_ID_MAX);
+	} else if (STAT_CAR_B_TYPE == car_type) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0,
+								  DPP_CAR_B_FLOW_ID_MAX);
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+								  DPP_CAR_B_PROFILE_ID_MAX);
+	} else {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0,
+								  DPP_CAR_C_FLOW_ID_MAX);
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+								  DPP_CAR_C_PROFILE_ID_MAX);
+	}
+
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), drop_flag, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), plcr_en, 0, 1);
+
+	p_restore_data = GET_DPP_CAR_SOFT_RESET_INFO(DEV_ID(dev)); /* 软复位相关 */
+
+	switch (car_type) {
+	case STAT_CAR_A_TYPE: {
+		rc = dpp_stat_cara_queue_cfg_set(dev, flow_id, drop_flag, plcr_en,
+										 profile_id);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_queue_cfg_set");
+
+		/* 软复位相关 */
+		flow_num = p_restore_data->cara_flow_num;
+		p_restore_data->cara_item[flow_num].flow_id = flow_id;
+		p_restore_data->cara_item[flow_num].profile_id = profile_id;
+		ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW(
+				DEV_ID(dev), p_restore_data->cara_flow_num, 1);
+		p_restore_data->cara_flow_num++;
+	} break;
+
+	case STAT_CAR_B_TYPE: {
+		rc = dpp_stat_carb_queue_cfg_set(dev, flow_id, drop_flag, plcr_en,
+										 profile_id);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_queue_cfg_set");
+
+		/* 软复位相关 */
+		flow_num = p_restore_data->carb_flow_num;
+		p_restore_data->carb_item[flow_num].flow_id = flow_id;
+		p_restore_data->carb_item[flow_num].profile_id = profile_id;
+		ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW(
+				DEV_ID(dev), p_restore_data->carb_flow_num, 1);
+		p_restore_data->carb_flow_num++;
+	} break;
+
+	case STAT_CAR_C_TYPE: {
+		rc = dpp_stat_carc_queue_cfg_set(dev, flow_id, drop_flag, plcr_en,
+										 profile_id);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_queue_cfg_set");
+
+		/* 软复位相关 */
+		flow_num = p_restore_data->carc_flow_num;
+		p_restore_data->carc_item[flow_num].flow_id = flow_id;
+		p_restore_data->carc_item[flow_num].profile_id = profile_id;
+		ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(
+				DEV_ID(dev), p_restore_data->carc_flow_num, 1);
+		p_restore_data->carc_flow_num++;
+	} break;
+	}
+
+	return rc;
+}
+
+/***********************************************************/
+/**队列设置参数获取
+ * @param   dev_id   设备号   car编号
+ * @param   car_type car模式，参见STAT_CAR_TYPE_E
+ * @param   pkt_sign 限速标志，1-包限速，0-字节限速
+ * @param   flow_id  队列号
+ * @param   p_data   获取队列配置信息
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/09/27
+ ************************************************************/
+DPP_STATUS dpp_stat_car_queue_get(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+								  ZXIC_UINT32 pkt_sign, ZXIC_UINT32 flow_id,
+								  ZXIC_VOID *p_data)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE,
+							  STAT_CAR_MAX_TYPE - 1);
+
+	if (STAT_CAR_A_TYPE == car_type) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pkt_sign, 0, 1);
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0,
+								  DPP_CAR_A_FLOW_ID_MAX);
+	} else if (STAT_CAR_B_TYPE == car_type) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0,
+								  DPP_CAR_B_FLOW_ID_MAX);
+	} else {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0,
+								  DPP_CAR_C_FLOW_ID_MAX);
+	}
+
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+
+	switch (car_type) {
+	case STAT_CAR_A_TYPE: {
+		if (0 == pkt_sign) {
+			rc = dpp_stat_cara_queue_cfg_get(
+					dev, flow_id, (DPP_STAT_CAR_A_QUEUE_CFG_T *)p_data);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+								   "dpp_stat_cara_queue_cfg_get");
+		} else {
+			rc = dpp_stat_cara_pkt_queue_cfg_get(
+					dev, flow_id, (DPP_STAT_CAR_A_PKT_QUEUE_CFG_T *)p_data);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+								   "dpp_stat_cara_pkt_queue_cfg_get");
+		}
+	} break;
+
+	case STAT_CAR_B_TYPE: {
+		rc = dpp_stat_carb_queue_cfg_get(dev, flow_id,
+										 (DPP_STAT_CAR_B_QUEUE_CFG_T *)p_data);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_queue_cfg_get");
+	} break;
+
+	case STAT_CAR_C_TYPE: {
+		rc = dpp_stat_carc_queue_cfg_get(dev, flow_id,
+										 (DPP_STAT_CAR_C_QUEUE_CFG_T *)p_data);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_queue_cfg_get");
+	} break;
+	}
+
+	return rc;
+}
+
+/***********************************************************/
+/** car 模块流配置获取
+ * @param   dev_id       设备号
+ * @param   car_type     car模式，参见STAT_CAR_TYPE_E
+ * @param   flow_id      队列号
+ * @param   p_drop_flag  drop标记
+ * @param   p_plcr_en    监管使能信号
+ * @param   p_profile_id 模板id
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/08/19
+ ************************************************************/
+DPP_STATUS dpp_stat_car_queue_cfg_get(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+									  ZXIC_UINT32 flow_id,
+									  ZXIC_UINT32 *p_drop_flag,
+									  ZXIC_UINT32 *p_plcr_en,
+									  ZXIC_UINT32 *p_profile_id)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR_A_QUEUE_CFG_T car_a_queue_cfg = { 0 };
+	DPP_STAT_CAR_B_QUEUE_CFG_T car_b_queue_cfg = { 0 };
+	DPP_STAT_CAR_C_QUEUE_CFG_T car_c_queue_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE,
+							  STAT_CAR_MAX_TYPE - 1);
+
+	if (STAT_CAR_A_TYPE == car_type) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0,
+								  DPP_CAR_A_FLOW_ID_MAX);
+	} else if (STAT_CAR_B_TYPE == car_type) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0,
+								  DPP_CAR_B_FLOW_ID_MAX);
+	} else {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0,
+								  DPP_CAR_C_FLOW_ID_MAX);
+	}
+
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_drop_flag);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_plcr_en);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_profile_id);
+
+	switch (car_type) {
+	case STAT_CAR_A_TYPE: {
+		rc = dpp_stat_cara_queue_cfg_get(dev, flow_id, &car_a_queue_cfg);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_queue_cfg_get");
+
+		*p_profile_id = car_a_queue_cfg.profile_id;
+		*p_plcr_en = car_a_queue_cfg.plcr_en;
+		*p_drop_flag = car_a_queue_cfg.drop_flag;
+	} break;
+
+	case STAT_CAR_B_TYPE: {
+		rc = dpp_stat_carb_queue_cfg_get(dev, flow_id, &car_b_queue_cfg);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_queue_cfg_get");
+
+		*p_profile_id = car_b_queue_cfg.profile_id;
+		*p_plcr_en = car_b_queue_cfg.plcr_en;
+		*p_drop_flag = car_b_queue_cfg.drop_flag;
+	} break;
+
+	case STAT_CAR_C_TYPE: {
+		rc = dpp_stat_carc_queue_cfg_get(dev, flow_id, &car_c_queue_cfg);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_queue_cfg_get");
+
+		*p_profile_id = car_c_queue_cfg.profile_id;
+		*p_plcr_en = car_c_queue_cfg.plcr_en;
+		*p_drop_flag = car_c_queue_cfg.drop_flag;
+	} break;
+	}
+
+	return rc;
+}
+
+/***********************************************************/
+/** car profile硬件写入
+ * @param   dev_id               设备号               car编号
+ * @param   car_type             car模式，参见STAT_CAR_TYPE_E
+ * @param   pkt_sign             限速模式，1-包限速，0-字节限速
+ * @param   profile_id           模板号
+ * @param   p_car_profile_cfg    模板配置信息
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/05/06
+ ************************************************************/
+DPP_STATUS dpp_stat_car_profile_cfg_set(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+										ZXIC_UINT32 pkt_sign,
+										ZXIC_UINT32 profile_id,
+										ZXIC_VOID *p_car_profile_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_CAR_SOFT_RESET_DATA_T *p_restore_data = NULL; /* 软复位相关 */
+	DPP_STAT_CAR_PROFILE_CFG_T *p_stat_car_profile_cfg = NULL;
+	DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_stat_pkt_car_profile_cfg = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE,
+							  STAT_CAR_MAX_TYPE - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pkt_sign, 0, 1);
+
+	if (STAT_CAR_A_TYPE == car_type) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+								  DPP_CAR_A_PROFILE_ID_MAX);
+	} else if (STAT_CAR_B_TYPE == car_type) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+								  DPP_CAR_B_PROFILE_ID_MAX);
+	} else {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+								  DPP_CAR_C_PROFILE_ID_MAX);
+	}
+
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_car_profile_cfg);
+
+	p_restore_data = GET_DPP_CAR_SOFT_RESET_INFO(DEV_ID(dev)); /* 软复位相关 */
+
+	if ((STAT_CAR_A_TYPE == car_type) && (1 == pkt_sign)) {
+		p_stat_pkt_car_profile_cfg =
+				(DPP_STAT_CAR_PKT_PROFILE_CFG_T *)p_car_profile_cfg;
+
+		rc = dpp_stat_cara_pkt_profile_cfg_set(dev, profile_id,
+											   p_stat_pkt_car_profile_cfg);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+							   "dpp_stat_cara_pkt_profile_cfg_set");
+
+		/* 软复位相关 */
+		p_restore_data->car_pkt_sign[profile_id] = ZXIC_TRUE;
+
+		ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(
+				DEV_ID(dev), p_restore_data->car0_pkt_num, 1);
+		p_restore_data->car0_pkt_num++;
+	} else {
+		p_stat_car_profile_cfg =
+				(DPP_STAT_CAR_PROFILE_CFG_T *)p_car_profile_cfg;
+		ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev),
+								 "==> dpp_stat_car_profile_cfg_set : \n");
+		ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev),
+								 "| %-10s | %-10s | %-10s | %-10s | \n",
+								 "profile_id", "car_id", "car_type",
+								 "pkt_sign");
+		ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev),
+								 "| %-10d | %-10d | %-10d | 0x%-8x | \n",
+								 profile_id, 0, car_type, pkt_sign);
+		ZXIC_COMM_TRACE_DEV_INFO(
+				DEV_ID(dev),
+				"| ------------------------------------------------- | \n");
+		ZXIC_COMM_TRACE_DEV_INFO(
+				DEV_ID(dev),
+				"| %-5s | %-5s | %-5s | %-10s | %-10s | %-10s | %-10s | \n",
+				"cd", "cf", "cm", "cir", "cbs", "eir", "ebs");
+		ZXIC_COMM_TRACE_DEV_INFO(
+				DEV_ID(dev),
+				"| %-5d | %-5d | %-5d | %-10d | %-10d | %-10d | %-10d | \n",
+				p_stat_car_profile_cfg->cd, p_stat_car_profile_cfg->cf,
+				p_stat_car_profile_cfg->cm, p_stat_car_profile_cfg->cir,
+				p_stat_car_profile_cfg->cbs, p_stat_car_profile_cfg->eir,
+				p_stat_car_profile_cfg->ebs);
+
+		if (STAT_CAR_A_TYPE == car_type) {
+			rc = dpp_stat_cara_profile_cfg_set(dev, profile_id,
+											   p_stat_car_profile_cfg);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+								   "dpp_stat_cara_profile_cfg_set");
+
+			/* 软复位相关 */
+			if (ZXIC_TRUE == p_restore_data->car_pkt_sign[profile_id]) {
+				p_restore_data->car0_pkt_num--;
+				p_restore_data->car_pkt_sign[profile_id] = ZXIC_FALSE;
+			}
+		} else if (STAT_CAR_B_TYPE == car_type) {
+			rc = dpp_stat_carb_profile_cfg_set(dev, profile_id,
+											   p_stat_car_profile_cfg);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+								   "dpp_stat_carb_profile_cfg_set");
+		} else {
+			rc = dpp_stat_carc_profile_cfg_set(dev, profile_id,
+											   p_stat_car_profile_cfg);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+								   "dpp_stat_carc_profile_cfg_set");
+		}
+	}
+
+	return rc;
+}
+
+/***********************************************************/
+/**获取监管模板配置
+ * @param   dev_id               设备号
+ * @param   car_type             car模式类型，参见STAT_CAR_TYPE_E
+ * @param   pkt_sign             限速模式，1-包限速，0-字节限速
+ * @param   profile_id           监管模板id
+ * @param   p_car_profile_cfg    模板配置信息
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/08/29
+ ************************************************************/
+DPP_STATUS dpp_stat_car_profile_cfg_get(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+										ZXIC_UINT32 pkt_sign,
+										ZXIC_UINT32 profile_id,
+										ZXIC_VOID *p_car_profile_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_CAR_PROFILE_CFG_T *p_stat_car_profile_cfg = NULL;
+	DPP_STAT_CAR_PKT_PROFILE_CFG_T *p_stat_pkt_car_profile_cfg = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE,
+							  STAT_CAR_MAX_TYPE - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), pkt_sign, 0, 1);
+
+	if (STAT_CAR_A_TYPE == car_type) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+								  DPP_CAR_A_PROFILE_ID_MAX);
+	} else if (STAT_CAR_B_TYPE == car_type) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+								  DPP_CAR_B_PROFILE_ID_MAX);
+	} else {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+								  DPP_CAR_C_PROFILE_ID_MAX);
+	}
+
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_car_profile_cfg);
+
+	if ((STAT_CAR_A_TYPE == car_type) && (1 == pkt_sign)) {
+		p_stat_pkt_car_profile_cfg =
+				(DPP_STAT_CAR_PKT_PROFILE_CFG_T *)p_car_profile_cfg;
+		rc = dpp_stat_cara_pkt_profile_cfg_get(dev, profile_id,
+											   p_stat_pkt_car_profile_cfg);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+							   "dpp_stat_cara_pkt_profile_cfg_get");
+	} else {
+		p_stat_car_profile_cfg =
+				(DPP_STAT_CAR_PROFILE_CFG_T *)p_car_profile_cfg;
+
+		if (STAT_CAR_A_TYPE == car_type) {
+			rc = dpp_stat_cara_profile_cfg_get(dev, profile_id,
+											   p_stat_car_profile_cfg);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+								   "dpp_stat_cara_profile_cfg_get");
+		} else if (STAT_CAR_B_TYPE == car_type) {
+			rc = dpp_stat_carb_profile_cfg_get(dev, profile_id,
+											   p_stat_car_profile_cfg);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+								   "dpp_stat_carb_profile_cfg_get");
+		} else {
+			rc = dpp_stat_carc_profile_cfg_get(dev, profile_id,
+											   p_stat_car_profile_cfg);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+								   "dpp_stat_carc_profile_cfg_get");
+		}
+	}
+
+	return rc;
+}
+
+/***********************************************************/
+/** car 队列映射关系配置
+ * @param   dev_id       设备号
+ * @param   car_type     car模式类型，参见STAT_CAR_TYPE_E
+ * @param   flow_id      队列号
+ * @param   map_flow_id  映射队列号
+ * @param   map_sp       映射sp
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/09/27
+ ************************************************************/
+DPP_STATUS dpp_stat_car_queue_map_set(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+									  ZXIC_UINT32 flow_id,
+									  ZXIC_UINT32 map_flow_id,
+									  ZXIC_UINT32 map_sp)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE,
+							  STAT_CAR_B_TYPE);
+
+	if (STAT_CAR_A_TYPE == car_type) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0,
+								  DPP_CAR_A_FLOW_ID_MAX);
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_flow_id, 0,
+								  DPP_CAR_B_FLOW_ID_MAX);
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_sp, DPP_CAR_PRI0,
+								  DPP_CAR_PRI_MAX - 1);
+		rc = dpp_stat_cara_queue_map_set(dev, flow_id, map_flow_id, map_sp);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_queue_map_set");
+	} else {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0,
+								  DPP_CAR_B_FLOW_ID_MAX);
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_flow_id, 0,
+								  DPP_CAR_C_FLOW_ID_MAX);
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), map_sp, DPP_CAR_PRI0,
+								  DPP_CAR_PRI_MAX - 1);
+		rc = dpp_stat_carb_queue_map_set(dev, flow_id, map_flow_id, map_sp);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_queue_map_set");
+	}
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取 car 流号的绑定关系
+ * @param   dev_id         设备号
+ * @param   car_type       car模式类型，参见STAT_CAR_TYPE_E
+ * @param   flow_id        队列号
+ * @param   p_map_flow_id  映射队列号
+ * @param   p_map_sp       映射sp
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/09/27
+ ************************************************************/
+DPP_STATUS dpp_stat_car_queue_map_get(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+									  ZXIC_UINT32 flow_id,
+									  ZXIC_UINT32 *p_map_flow_id,
+									  ZXIC_UINT32 *p_map_sp)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE,
+							  STAT_CAR_B_TYPE);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_flow_id);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_map_sp);
+
+	if (STAT_CAR_A_TYPE == car_type) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0,
+								  DPP_CAR_A_FLOW_ID_MAX);
+		rc = dpp_stat_cara_queue_map_get(dev, flow_id, p_map_flow_id, p_map_sp);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_cara_queue_map_get");
+	} else {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flow_id, 0,
+								  DPP_CAR_B_FLOW_ID_MAX);
+		rc = dpp_stat_carb_queue_map_get(dev, flow_id, p_map_flow_id, p_map_sp);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_queue_map_get");
+	}
+
+	return rc;
+}
+
+/***********************************************************/
+/**
+ * @param   dev_id         设备ID
+ * @param   profile_id     模板ID
+ * @param   p_random_ram_e E桶概率丢弃配置参数
+ * @param   p_random_ram_c C桶概率丢弃配置参数
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  YXH      @date  2019/04/01
+ ************************************************************/
+DPP_STATUS dpp_stat_car_random_ram_set(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+									   ZXIC_UINT32 profile_id,
+									   DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
+									   DPP_CAR_RANDOM_RAM_T *p_random_ram_c)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_B_TYPE,
+							  STAT_CAR_C_TYPE);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c);
+
+	if (STAT_CAR_B_TYPE == car_type) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+								  DPP_CAR_B_PROFILE_ID_RANDOM_MAX);
+		rc = dpp_stat_carb_random_ram_set(dev, profile_id, p_random_ram_e,
+										  p_random_ram_c);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_random_ram_set");
+	} else {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+								  DPP_CAR_C_PROFILE_ID_RANDOM_MAX);
+		rc = dpp_stat_carc_random_ram_set(dev, profile_id, p_random_ram_e,
+										  p_random_ram_c);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_random_ram_set");
+	}
+
+	return rc;
+}
+
+/***********************************************************/
+/**
+ * @param   dev_id         设备ID
+ * @param   profile_id     模板ID
+ * @param   p_random_ram_e E桶概率丢弃配置参数
+ * @param   p_random_ram_c C桶概率丢弃配置参数
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  YXH      @date  2019/04/01
+ ************************************************************/
+DPP_STATUS dpp_stat_car_random_ram_get(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+									   ZXIC_UINT32 profile_id,
+									   DPP_CAR_RANDOM_RAM_T *p_random_ram_e,
+									   DPP_CAR_RANDOM_RAM_T *p_random_ram_c)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_B_TYPE,
+							  STAT_CAR_C_TYPE);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_e);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_random_ram_c);
+
+	if (STAT_CAR_B_TYPE == car_type) {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+								  DPP_CAR_B_PROFILE_ID_RANDOM_MAX);
+		rc = dpp_stat_carb_random_ram_get(dev, profile_id, p_random_ram_e,
+										  p_random_ram_c);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carb_random_ram_get");
+	} else {
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), profile_id, 0,
+								  DPP_CAR_C_PROFILE_ID_RANDOM_MAX);
+		rc = dpp_stat_carc_random_ram_get(dev, profile_id, p_random_ram_e,
+										  p_random_ram_c);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_carc_random_ram_get");
+	}
+
+	return rc;
+}
+
+/***********************************************************/
+/** 获取最大包长
+ * @param   dev_id
+ * @param   car_type
+ * @param   p_max_pkt_len
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wll      @date  2019/06/06
+ ************************************************************/
+DPP_STATUS dpp_stat_car_max_pkt_size_get(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+										 ZXIC_UINT32 *p_max_pkt_len)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 pkt_len = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE,
+							  STAT_CAR_MAX_TYPE - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_max_pkt_len);
+
+	switch (car_type) {
+	case STAT_CAR_A_TYPE: {
+		rc = dpp_stat_cara_max_pkt_size_get(dev, &pkt_len);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+							   "dpp_stat_cara_max_pkt_size_get");
+	} break;
+
+	case STAT_CAR_B_TYPE: {
+		rc = dpp_stat_carb_max_pkt_size_get(dev, &pkt_len);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+							   "dpp_stat_carb_max_pkt_size_get");
+	} break;
+
+	case STAT_CAR_C_TYPE: {
+		rc = dpp_stat_carc_max_pkt_size_get(dev, &pkt_len);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+							   "dpp_stat_carc_max_pkt_size_get");
+	} break;
+	}
+
+	*p_max_pkt_len = pkt_len;
+
+	return rc;
+}
+
+/***********************************************************/
+/** 配置最大包长
+ * @param   dev_id
+ * @param   car_type
+ * @param   max_pkt_size
+ *
+ * @return  NPE_OK-成功，NPE_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wll      @date  2019/06/06
+ ************************************************************/
+DPP_STATUS dpp_stat_car_max_pkt_size_set(DPP_DEV_T *dev, ZXIC_UINT32 car_type,
+										 ZXIC_UINT32 max_pkt_size)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), car_type, STAT_CAR_A_TYPE,
+							  STAT_CAR_MAX_TYPE - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), max_pkt_size, 0, 0x3fff);
+
+	switch (car_type) {
+	case STAT_CAR_A_TYPE: {
+		rc = dpp_stat_cara_max_pkt_size_set(dev, max_pkt_size);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+							   "dpp_stat_cara_max_pkt_size_set");
+	} break;
+
+	case STAT_CAR_B_TYPE: {
+		rc = dpp_stat_carb_max_pkt_size_set(dev, max_pkt_size);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+							   "dpp_stat_carb_max_pkt_size_set");
+	} break;
+
+	case STAT_CAR_C_TYPE: {
+		rc = dpp_stat_carc_max_pkt_size_set(dev, max_pkt_size);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+							   "dpp_stat_carc_max_pkt_size_set");
+	} break;
+	}
+
+	return rc;
+}
+
+/***********************************************************/
+/** STAT CAR复位获取全局变量大小函数
+ * @param   dev_id
+ * @param   p_size
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  yxh      @date  2018/06/26
+ ************************************************************/
+DPP_STATUS dpp_stat_car_glb_size_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_size)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 queue_num = 0;
+	ZXIC_UINT32 profile_num = 0;
+	ZXIC_UINT32 pkt_profile_num = 0;
+
+	DPP_CAR_SOFT_RESET_DATA_T *p_g_restore_data = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_size);
+
+	p_g_restore_data = GET_DPP_CAR_SOFT_RESET_INFO(DEV_ID(dev));
+
+	if (0 == p_g_restore_data->is_init) {
+		ZXIC_COMM_PRINT("Not init!!!\n");
+		*p_size = sizeof(ZXIC_UINT32);
+	} else {
+		/* CAR A */
+		ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(
+				DEV_ID(dev), queue_num, p_g_restore_data->cara_flow_num);
+		queue_num += p_g_restore_data->cara_flow_num;
+
+		/* CAR B */
+		ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(
+				DEV_ID(dev), queue_num, p_g_restore_data->carb_flow_num);
+		queue_num += p_g_restore_data->carb_flow_num;
+
+		/* CAR C */
+		ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(
+				DEV_ID(dev), queue_num, p_g_restore_data->carc_flow_num);
+		queue_num += p_g_restore_data->carc_flow_num;
+
+		pkt_profile_num = p_g_restore_data->car0_pkt_num;
+		ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(
+				DEV_ID(dev),
+				(DPP_CAR_A_PROFILE_ID_MAX + DPP_CAR_B_PROFILE_ID_MAX +
+				 DPP_CAR_C_PROFILE_ID_MAX + 3),
+				pkt_profile_num);
+		profile_num = DPP_CAR_A_PROFILE_ID_MAX + DPP_CAR_B_PROFILE_ID_MAX +
+					  DPP_CAR_C_PROFILE_ID_MAX + 3 - pkt_profile_num;
+		ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(
+				DEV_ID(dev), queue_num,
+				((ZXIC_UINT32)ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T)));
+		ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(
+				DEV_ID(dev), pkt_profile_num,
+				((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PKT_PROFILE_CFG_T)));
+		ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(
+				DEV_ID(dev), profile_num,
+				((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PROFILE_CFG_T)));
+		*p_size =
+				((ZXIC_UINT32)ZXIC_SIZEOF(ZXIC_UINT32)) * 5 +
+				queue_num *
+						((ZXIC_UINT32)ZXIC_SIZEOF(DPP_CAR_SOFT_RESET_QUEUE_T)) +
+				pkt_profile_num * ((ZXIC_UINT32)ZXIC_SIZEOF(
+										  DPP_STAT_CAR_PKT_PROFILE_CFG_T)) +
+				profile_num *
+						((ZXIC_UINT32)ZXIC_SIZEOF(DPP_STAT_CAR_PROFILE_CFG_T));
+		ZXIC_COMM_PRINT("glb_size = %d!!!\n", *p_size);
+	}
+
+	return rc;
+}
+
+#endif
+
+#if ZXIC_REAL("TEST")
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_stat_cfg.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_stat_cfg.c
old mode 100755
new mode 100644
index 5187c93d1efc991a1f10015eba3d36f7d92ab467..c06a782caf424d954de9c27296d7ee3f77decb72
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_stat_cfg.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se/dpp_stat_cfg.c
@@ -1,310 +1,287 @@
-/**************************************************************
-* ��Ȩ���� (C)2013-2015, ����������ͨѶ�ɷ����޹�˾
-* �ļ����� : dpp_stat_cfg.c
-* �ļ���ʶ :
-* ����ժҪ :
-* ����˵�� :
-* ��ǰ�汾 :
-* ��    �� : ls
-* ������� : 2016/03/29
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* �޸ļ�¼1:
-* �޸�����:
-* �� �� ��:
-* �� �� ��:
-* �޸�����:
-***************************************************************/
-#include "zxic_common.h"
-#include "dpp_type_api.h"
-#include "dpp_dev.h"
-#include "dpp_stat_reg.h"
-#include "dpp_stat_cfg.h"
-#include "dpp_stat_api.h"
-#include "dpp_se_api.h"
-#include "dpp_se.h"
-#include "dpp_reg_api.h"
-#include "dpp_reg_info.h"
-
-PPU_STAT_CFG_T g_ppu_stat_cfg = {0};
-
-#if ZXIC_REAL("Basic Reg Operation")
-
-/***********************************************************/
-/** ��ȡppuͳ��Ƭ�����
-* @param   dev_id               �豸��
-* @param   p_ppu_eram_depth     ppuͳ��Ƭ�����
-*
-* @return  NPE_OK-�ɹ���NPE_ERR-ʧ��
-* @remark  ��
-* @see
-* @author  ls      @date  2016/03/31
-************************************************************/
-DPP_STATUS dpp_stat_ppu_eram_depth_get(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 *p_ppu_eram_depth)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_STAT_CFG_PPU_ERAM_DEPTH_T ppu_eram_depth_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ppu_eram_depth);
-
-    rc = dpp_reg_read(dev,
-                      STAT_STAT_CFG_PPU_ERAM_DEPTHr,
-                      0,
-                      0,
-                      &ppu_eram_depth_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_ppu_eram_depth = ppu_eram_depth_cfg.ppu_eram_depth;
-
-    return rc;
-}
-
-/***********************************************************/
-/** ��ȡppuͳ�� ERAM����ַ
-* @param   dev_id               �豸��
-* @param   p_ppu_eram_baddr     ppuͳ��Ƭ�ڻ���ַ
-*
-* @return  NPE_OK-�ɹ���NPE_ERR-ʧ��
-* @remark  ��
-* @see
-* @author  ls      @date  2016/03/31
-************************************************************/
-DPP_STATUS dpp_stat_ppu_eram_baddr_get(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 *p_ppu_eram_baddr)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_STAT_CFG_PPU_ERAM_BASE_ADDR_T ppu_eram_baddr_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ppu_eram_baddr);
-
-    rc = dpp_reg_read(dev,
-                      STAT_STAT_CFG_PPU_ERAM_BASE_ADDRr,
-                      0,
-                      0,
-                      &ppu_eram_baddr_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_ppu_eram_baddr = ppu_eram_baddr_cfg.ppu_eram_base_addr;
-
-    return rc;
-}
-
-/***********************************************************/
-/** ��ȡppuͳ�� ddr����ַ
-* @param   dev_id              �豸��
-* @param   p_ppu_ddr_baddr     ppuͳ��Ƭ�����ַ
-*
-* @return  NPE_OK-�ɹ���NPE_ERR-ʧ��
-* @remark  ��
-* @see
-* @author  ls      @date  2016/03/31
-************************************************************/
-DPP_STATUS dpp_stat_ppu_ddr_baddr_get(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 *p_ppu_ddr_baddr)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_STAT_CFG_PPU_DDR_BASE_ADDR_T ppu_ddr_baddr_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ppu_ddr_baddr);
-
-    rc = dpp_reg_read(dev,
-                      STAT_STAT_CFG_PPU_DDR_BASE_ADDRr,
-                      0,
-                      0,
-                      &ppu_ddr_baddr_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_ppu_ddr_baddr = ppu_ddr_baddr_cfg.ppu_ddr_base_addr;
-
-    return rc;
-}
-#endif
-
-#if ZXIC_REAL("Advanced Function")
-/***********************************************************/
-/** ppu����ֵ��ȡ
-* @param   dev_id           �豸��
-* @param   rd_mode          ��ȡλ��ģʽ���μ�STAT_CNT_MODE_E��0-64bit��1-128bit
-* @param   index            ����������λ���μ�rd_mode
-* @param   clr_mode         ����ģʽ���μ�STAT_RD_CLR_MODE_E��0-�����壬1-����
-* @param   p_data           ���Σ���ȡ������
-*
-* @return  NPE_OK-�ɹ���NPE_ERR-ʧ��
-* @remark  ��
-* @see
-* @author  ls      @date  2016/07/11
-************************************************************/
-DPP_STATUS dpp_stat_ppu_cnt_get(DPP_DEV_T *dev,
-                                STAT_CNT_MODE_E rd_mode,
-                                ZXIC_UINT32 index,
-                                ZXIC_UINT32 clr_mode,
-                                ZXIC_UINT32 *p_data)
-{
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 ppu_eram_baddr = 0;
-    ZXIC_UINT32 ppu_eram_depth = 0;
-    ZXIC_UINT32 ppu_ddr_baddr  = 0;
-    ZXIC_UINT32 eram_rd_mode   = 0;
-    ZXIC_UINT32 eram_clr_mode  = 0;
-    // ZXIC_UINT32 ddr_rd_mode    = 0;
-    // ZXIC_UINT32 ddr_clr_mode   = 0;
-    // ZXIC_UINT32 ddr_index      = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_mode, STAT_64_MODE, STAT_MAX_MODE - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), clr_mode, STAT_RD_CLR_MODE_UNCLR, STAT_RD_CLR_MODE_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-
-    rc = dpp_stat_ppu_eram_depth_get(dev,
-                                     &ppu_eram_depth);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_ppu_eram_depth_get");
-
-    rc = dpp_stat_ppu_eram_baddr_get(dev,
-                                     &ppu_eram_baddr);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_ppu_eram_baddr_get");
-
-    rc = dpp_stat_ppu_ddr_baddr_get(dev,
-                                    &ppu_ddr_baddr);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_ppu_ddr_baddr_get");
-
-    /** Ƭ�ڴ洢 */
-    if ((index >> (STAT_128_MODE - rd_mode)) < ppu_eram_depth)
-    {
-        if (STAT_128_MODE == rd_mode)
-        {
-            eram_rd_mode = ERAM128_OPR_128b;
-        }
-        else
-        {
-            eram_rd_mode = ERAM128_OPR_64b;
-        }
-
-        if (STAT_RD_CLR_MODE_UNCLR == clr_mode)
-        {
-            eram_clr_mode = RD_MODE_HOLD;
-        }
-        else
-        {
-            eram_clr_mode = RD_MODE_CLEAR;
-        }
-
-        rc = dpp_se_smmu0_ind_read(dev,
-                                   ppu_eram_baddr,
-                                   index,
-                                   eram_rd_mode,
-                                   eram_clr_mode,
-                                   p_data);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_smmu0_ind_read");
-    }
-    /** Ƭ��洢 */
-    else
-    {
-        // if (STAT_128_MODE == rd_mode)
-        // {
-        //     ddr_rd_mode = CMMU_RD_MODE_128;
-        // }
-        // else
-        // {
-        //     ddr_rd_mode = CMMU_RD_MODE_64;
-        // }
-
-        // if (STAT_RD_CLR_MODE_UNCLR == clr_mode)
-        // {
-        //     ddr_clr_mode = CMMU_RD_CLR_MODE_UNCLR;
-        // }
-        // else
-        // {
-        //     ddr_clr_mode = CMMU_RD_CLR_MODE_CLR;
-        // }
-
-        // ddr_index = index - (ppu_eram_depth << (STAT_128_MODE - rd_mode));
-
-        // rc = dpp_se_cmmu_ddr_read(dev_id,
-        //                           ppu_ddr_baddr,
-        //                           ddr_rd_mode,
-        //                           ddr_clr_mode,
-        //                           ddr_index,
-        //                           p_data);
-        // ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_cmmu_ddr_read");
-    }
-
-    return rc;
-}
-
-/***********************************************************/
-/** ����ppuͳ��Ƭ�����
-* @param   dev_id           �豸��
-* @param   ppu_eram_depth   ppuͳ��Ƭ�����,128bitΪ��λ
-*
-* @return  NPE_OK-�ɹ���NPE_ERR-ʧ��
-* @remark  ��
-* @see
-* @author  ls      @date  2016/03/31
-************************************************************/
-DPP_STATUS dpp_stat_ppu_eram_depth_set(DPP_DEV_T *dev, ZXIC_UINT32 ppu_eram_depth)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_STAT_CFG_PPU_ERAM_DEPTH_T ppu_eram_depth_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), ppu_eram_depth, 0, DPP_STAT_PPU_ERAM_DEPTH_MAX);
-
-    ppu_eram_depth_cfg.ppu_eram_depth = ppu_eram_depth;
-
-    rc = dpp_reg_write(dev,
-                       STAT_STAT_CFG_PPU_ERAM_DEPTHr,
-                       0,
-                       0,
-                       &ppu_eram_depth_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    g_ppu_stat_cfg.eram_depth = ppu_eram_depth;
-
-    return rc;
-}
-
-/***********************************************************/
-/** ����ppuͳ�� ERAM����ַ
-* @param   dev_id           �豸��
-* @param   ppu_eram_baddr   ppuͳ��eRam����ַ,128bitΪ��λ
-*
-* @return  NPE_OK-�ɹ���NPE_ERR-ʧ��
-* @remark  ��
-* @see
-* @author  ls      @date  2016/03/31
-************************************************************/
-DPP_STATUS dpp_stat_ppu_eram_baddr_set(DPP_DEV_T *dev, ZXIC_UINT32 ppu_eram_baddr)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_STAT_STAT_CFG_PPU_ERAM_BASE_ADDR_T ppu_eram_baddr_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), ppu_eram_baddr, 0, DPP_STAT_PPU_ERAM_BADDR_MAX);
-
-    ppu_eram_baddr_cfg.ppu_eram_base_addr = ppu_eram_baddr;
-
-    rc = dpp_reg_write(dev,
-                       STAT_STAT_CFG_PPU_ERAM_BASE_ADDRr,
-                       0,
-                       0,
-                       &ppu_eram_baddr_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
-
-    g_ppu_stat_cfg.eram_baddr = ppu_eram_baddr;
-
-    return rc;
-}
-
-#endif
+/**************************************************************
+* ��Ȩ���� (C)2013-2015, ����������ͨѶ�ɷ����޹�˾
+* �ļ����� : dpp_stat_cfg.c
+* �ļ���ʶ :
+* ����ժҪ :
+* ����˵�� :
+* ��ǰ�汾 :
+* ��    �� : ls
+* ������� : 2016/03/29
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* �޸ļ�¼1:
+* �޸�����:
+* �� �� ��:
+* �� �� ��:
+* �޸�����:
+***************************************************************/
+#include "zxic_common.h"
+#include "dpp_type_api.h"
+#include "dpp_dev.h"
+#include "dpp_stat_reg.h"
+#include "dpp_stat_cfg.h"
+#include "dpp_stat_api.h"
+#include "dpp_se_api.h"
+#include "dpp_se.h"
+#include "dpp_reg_api.h"
+#include "dpp_reg_info.h"
+
+PPU_STAT_CFG_T g_ppu_stat_cfg = { 0 };
+
+#if ZXIC_REAL("Basic Reg Operation")
+
+/***********************************************************/
+/** ��ȡppuͳ��Ƭ�����
+ * @param   dev_id               �豸��
+ * @param   p_ppu_eram_depth     ppuͳ��Ƭ�����
+ *
+ * @return  NPE_OK-�ɹ���NPE_ERR-ʧ��
+ * @remark  ��
+ * @see
+ * @author  ls      @date  2016/03/31
+ ************************************************************/
+DPP_STATUS dpp_stat_ppu_eram_depth_get(DPP_DEV_T *dev,
+									   ZXIC_UINT32 *p_ppu_eram_depth)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_STAT_CFG_PPU_ERAM_DEPTH_T ppu_eram_depth_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ppu_eram_depth);
+
+	rc = dpp_reg_read(dev, STAT_STAT_CFG_PPU_ERAM_DEPTHr, 0, 0,
+					  &ppu_eram_depth_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_ppu_eram_depth = ppu_eram_depth_cfg.ppu_eram_depth;
+
+	return rc;
+}
+
+/***********************************************************/
+/** ��ȡppuͳ�� ERAM����ַ
+ * @param   dev_id               �豸��
+ * @param   p_ppu_eram_baddr     ppuͳ��Ƭ�ڻ���ַ
+ *
+ * @return  NPE_OK-�ɹ���NPE_ERR-ʧ��
+ * @remark  ��
+ * @see
+ * @author  ls      @date  2016/03/31
+ ************************************************************/
+DPP_STATUS dpp_stat_ppu_eram_baddr_get(DPP_DEV_T *dev,
+									   ZXIC_UINT32 *p_ppu_eram_baddr)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_STAT_CFG_PPU_ERAM_BASE_ADDR_T ppu_eram_baddr_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ppu_eram_baddr);
+
+	rc = dpp_reg_read(dev, STAT_STAT_CFG_PPU_ERAM_BASE_ADDRr, 0, 0,
+					  &ppu_eram_baddr_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_ppu_eram_baddr = ppu_eram_baddr_cfg.ppu_eram_base_addr;
+
+	return rc;
+}
+
+/***********************************************************/
+/** ��ȡppuͳ�� ddr����ַ
+ * @param   dev_id              �豸��
+ * @param   p_ppu_ddr_baddr     ppuͳ��Ƭ�����ַ
+ *
+ * @return  NPE_OK-�ɹ���NPE_ERR-ʧ��
+ * @remark  ��
+ * @see
+ * @author  ls      @date  2016/03/31
+ ************************************************************/
+DPP_STATUS dpp_stat_ppu_ddr_baddr_get(DPP_DEV_T *dev,
+									  ZXIC_UINT32 *p_ppu_ddr_baddr)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_STAT_CFG_PPU_DDR_BASE_ADDR_T ppu_ddr_baddr_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ppu_ddr_baddr);
+
+	rc = dpp_reg_read(dev, STAT_STAT_CFG_PPU_DDR_BASE_ADDRr, 0, 0,
+					  &ppu_ddr_baddr_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_ppu_ddr_baddr = ppu_ddr_baddr_cfg.ppu_ddr_base_addr;
+
+	return rc;
+}
+#endif
+
+#if ZXIC_REAL("Advanced Function")
+/***********************************************************/
+/** ppu����ֵ��ȡ
+ * @param   dev_id           �豸��
+ * @param   rd_mode          ��ȡλ��ģʽ���μ�STAT_CNT_MODE_E��0-64bit��1-128bit
+ * @param   index            ����������λ���μ�rd_mode
+ * @param   clr_mode         ����ģʽ���μ�STAT_RD_CLR_MODE_E��0-�����壬1-����
+ * @param   p_data           ���Σ���ȡ������
+ *
+ * @return  NPE_OK-�ɹ���NPE_ERR-ʧ��
+ * @remark  ��
+ * @see
+ * @author  ls      @date  2016/07/11
+ ************************************************************/
+DPP_STATUS dpp_stat_ppu_cnt_get(DPP_DEV_T *dev, STAT_CNT_MODE_E rd_mode,
+								ZXIC_UINT32 index, ZXIC_UINT32 clr_mode,
+								ZXIC_UINT32 *p_data)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 ppu_eram_baddr = 0;
+	ZXIC_UINT32 ppu_eram_depth = 0;
+	ZXIC_UINT32 ppu_ddr_baddr = 0;
+	ZXIC_UINT32 eram_rd_mode = 0;
+	ZXIC_UINT32 eram_clr_mode = 0;
+	// ZXIC_UINT32 ddr_rd_mode    = 0;
+	// ZXIC_UINT32 ddr_clr_mode   = 0;
+	// ZXIC_UINT32 ddr_index      = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_mode, STAT_64_MODE,
+							  STAT_MAX_MODE - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), clr_mode, STAT_RD_CLR_MODE_UNCLR,
+							  STAT_RD_CLR_MODE_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+
+	rc = dpp_stat_ppu_eram_depth_get(dev, &ppu_eram_depth);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_ppu_eram_depth_get");
+
+	rc = dpp_stat_ppu_eram_baddr_get(dev, &ppu_eram_baddr);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_ppu_eram_baddr_get");
+
+	rc = dpp_stat_ppu_ddr_baddr_get(dev, &ppu_ddr_baddr);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stat_ppu_ddr_baddr_get");
+
+	/** Ƭ�ڴ洢 */
+	if ((index >> (STAT_128_MODE - rd_mode)) < ppu_eram_depth) {
+		if (STAT_128_MODE == rd_mode) {
+			eram_rd_mode = ERAM128_OPR_128b;
+		} else {
+			eram_rd_mode = ERAM128_OPR_64b;
+		}
+
+		if (STAT_RD_CLR_MODE_UNCLR == clr_mode) {
+			eram_clr_mode = RD_MODE_HOLD;
+		} else {
+			eram_clr_mode = RD_MODE_CLEAR;
+		}
+
+		rc = dpp_se_smmu0_ind_read(dev, ppu_eram_baddr, index, eram_rd_mode,
+								   eram_clr_mode, p_data);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_smmu0_ind_read");
+	}
+	/** Ƭ��洢 */
+	else {
+		// if (STAT_128_MODE == rd_mode)
+		// {
+		//     ddr_rd_mode = CMMU_RD_MODE_128;
+		// }
+		// else
+		// {
+		//     ddr_rd_mode = CMMU_RD_MODE_64;
+		// }
+
+		// if (STAT_RD_CLR_MODE_UNCLR == clr_mode)
+		// {
+		//     ddr_clr_mode = CMMU_RD_CLR_MODE_UNCLR;
+		// }
+		// else
+		// {
+		//     ddr_clr_mode = CMMU_RD_CLR_MODE_CLR;
+		// }
+
+		// ddr_index = index - (ppu_eram_depth << (STAT_128_MODE - rd_mode));
+
+		// rc = dpp_se_cmmu_ddr_read(dev_id,
+		//                           ppu_ddr_baddr,
+		//                           ddr_rd_mode,
+		//                           ddr_clr_mode,
+		//                           ddr_index,
+		//                           p_data);
+		// ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_cmmu_ddr_read");
+	}
+
+	return rc;
+}
+
+/***********************************************************/
+/** ����ppuͳ��Ƭ�����
+ * @param   dev_id           �豸��
+ * @param   ppu_eram_depth   ppuͳ��Ƭ�����,128bitΪ��λ
+ *
+ * @return  NPE_OK-�ɹ���NPE_ERR-ʧ��
+ * @remark  ��
+ * @see
+ * @author  ls      @date  2016/03/31
+ ************************************************************/
+DPP_STATUS dpp_stat_ppu_eram_depth_set(DPP_DEV_T *dev,
+									   ZXIC_UINT32 ppu_eram_depth)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_STAT_CFG_PPU_ERAM_DEPTH_T ppu_eram_depth_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), ppu_eram_depth, 0,
+							  DPP_STAT_PPU_ERAM_DEPTH_MAX);
+
+	ppu_eram_depth_cfg.ppu_eram_depth = ppu_eram_depth;
+
+	rc = dpp_reg_write(dev, STAT_STAT_CFG_PPU_ERAM_DEPTHr, 0, 0,
+					   &ppu_eram_depth_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	g_ppu_stat_cfg.eram_depth = ppu_eram_depth;
+
+	return rc;
+}
+
+/***********************************************************/
+/** ����ppuͳ�� ERAM����ַ
+ * @param   dev_id           �豸��
+ * @param   ppu_eram_baddr   ppuͳ��eRam����ַ,128bitΪ��λ
+ *
+ * @return  NPE_OK-�ɹ���NPE_ERR-ʧ��
+ * @remark  ��
+ * @see
+ * @author  ls      @date  2016/03/31
+ ************************************************************/
+DPP_STATUS dpp_stat_ppu_eram_baddr_set(DPP_DEV_T *dev,
+									   ZXIC_UINT32 ppu_eram_baddr)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_STAT_STAT_CFG_PPU_ERAM_BASE_ADDR_T ppu_eram_baddr_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), ppu_eram_baddr, 0,
+							  DPP_STAT_PPU_ERAM_BADDR_MAX);
+
+	ppu_eram_baddr_cfg.ppu_eram_base_addr = ppu_eram_baddr;
+
+	rc = dpp_reg_write(dev, STAT_STAT_CFG_PPU_ERAM_BASE_ADDRr, 0, 0,
+					   &ppu_eram_baddr_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_reg_write");
+
+	g_ppu_stat_cfg.eram_baddr = ppu_eram_baddr;
+
+	return rc;
+}
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_acl.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_acl.c
index 0da04a1bc82a4d35732544cb1d9c6b861377cff6..0c33c4f83c20dbf1d3a0b073d2e7535148f0a48a 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_acl.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_acl.c
@@ -22,124 +22,121 @@
 #include "dpp_acl.h"
 #include "dpp_dtb_table.h"
 
-static DPP_ACL_CFG_EX_T g_apt_acl_cfg = {0};
+static DPP_ACL_CFG_EX_T g_apt_acl_cfg = { 0 };
 
 /***********************************************************/
 /** acl资源初始化
-* @param   dev_id  设备号 
-* @param   tbl_num     etcam对应的sdt表个数
-* @param   pAclTblRes  acl表资源信息，包括SDT配置信息，acl资源(条目数，存放方式和占用的block)和结构体码流转换回调函数
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_acl_res_init(DPP_DEV_T *dev,ZXIC_UINT32 tbl_num,DPP_APT_ACL_TABLE_T *pAclTblRes)
+ * @param   dev_id  设备号
+ * @param   tbl_num     etcam对应的sdt表个数
+ * @param   pAclTblRes  acl表资源信息，包括SDT配置信息，acl资源(条目数，存放方式和占用的block)和结构体码流转换回调函数
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_acl_res_init(DPP_DEV_T *dev, ZXIC_UINT32 tbl_num,
+								DPP_APT_ACL_TABLE_T *pAclTblRes)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT8 index = 0;
-    DPP_APT_ACL_TABLE_T *pTempAclTbl = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(tbl_num, DPP_ETCAM_TBLID_NUM);
-    ZXIC_COMM_CHECK_POINT(pAclTblRes);
-
-    rc = dpp_acl_cfg_init_ex(dev, &g_apt_acl_cfg,
-                        (ZXIC_VOID *)ZXIC_COMM_VAL_TO_PTR(DEV_ID(dev)),
-                        DPP_ACL_FLAG_ETCAM0_EN,
-                        NULL);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_acl_cfg_init_ex");
-
-    for(index = 0;index < tbl_num;index++)
-    {
-        pTempAclTbl = pAclTblRes + index;
-        rc = dpp_sdt_tbl_write(dev,
-                        pTempAclTbl->sdtNo,
-                        pTempAclTbl->aclSdt.table_type,
-                        &(pTempAclTbl->aclSdt),
-                        SDT_OPER_ADD);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_sdt_tbl_write");
-
-         rc = dpp_acl_tbl_init_ex(&g_apt_acl_cfg,
-                                    pTempAclTbl->aclSdt.etcam_table_id,
-                                    pTempAclTbl->aclSdt.as_en,
-                                    pTempAclTbl->aclRes.entry_num,
-                                    pTempAclTbl->aclRes.pri_mode,
-                                    pTempAclTbl->aclSdt.etcam_key_mode,
-                                    pTempAclTbl->aclSdt.as_rsp_mode,
-                                    pTempAclTbl->aclSdt.as_eram_baddr,
-                                    pTempAclTbl->aclRes.block_num,
-                                    pTempAclTbl->aclRes.block_index);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_acl_tbl_init_ex");
-
-        rc = dpp_apt_set_callback(DEV_ID(dev),
-                        pTempAclTbl->sdtNo,
-                        pTempAclTbl->aclSdt.table_type,
-                        (ZXIC_VOID *)pTempAclTbl);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_apt_set_callback");
-
-    }
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT8 index = 0;
+	DPP_APT_ACL_TABLE_T *pTempAclTbl = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(tbl_num, DPP_ETCAM_TBLID_NUM);
+	ZXIC_COMM_CHECK_POINT(pAclTblRes);
+
+	rc = dpp_acl_cfg_init_ex(dev, &g_apt_acl_cfg,
+							 (ZXIC_VOID *)ZXIC_COMM_VAL_TO_PTR(DEV_ID(dev)),
+							 DPP_ACL_FLAG_ETCAM0_EN, NULL);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_acl_cfg_init_ex");
+
+	for (index = 0; index < tbl_num; index++) {
+		pTempAclTbl = pAclTblRes + index;
+		rc = dpp_sdt_tbl_write(dev, pTempAclTbl->sdtNo,
+							   pTempAclTbl->aclSdt.table_type,
+							   &(pTempAclTbl->aclSdt), SDT_OPER_ADD);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_sdt_tbl_write");
+
+		rc = dpp_acl_tbl_init_ex(
+				&g_apt_acl_cfg, pTempAclTbl->aclSdt.etcam_table_id,
+				pTempAclTbl->aclSdt.as_en, pTempAclTbl->aclRes.entry_num,
+				pTempAclTbl->aclRes.pri_mode,
+				pTempAclTbl->aclSdt.etcam_key_mode,
+				pTempAclTbl->aclSdt.as_rsp_mode,
+				pTempAclTbl->aclSdt.as_eram_baddr,
+				pTempAclTbl->aclRes.block_num, pTempAclTbl->aclRes.block_index);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_acl_tbl_init_ex");
+
+		rc = dpp_apt_set_callback(DEV_ID(dev), pTempAclTbl->sdtNo,
+								  pTempAclTbl->aclSdt.table_type,
+								  (ZXIC_VOID *)pTempAclTbl);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_apt_set_callback");
+	}
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** acl表项插入/更新
-* @param   dev_id  设备号 
-* @param   sdt_no  sdt号 0~255
-* @param   pData   业务插入表项内容，具体结构体由业务确定(结构体的第一个字段必须为index)，SDK不感知
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_dtb_acl_entry_insert(DPP_DEV_T *dev,ZXIC_UINT32 queue_id, ZXIC_UINT32 sdt_no, void *pData)
+ * @param   dev_id  设备号
+ * @param   sdt_no  sdt号 0~255
+ * @param   pData   业务插入表项内容，具体结构体由业务确定(结构体的第一个字段必须为index)，SDK不感知
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_dtb_acl_entry_insert(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+										ZXIC_UINT32 sdt_no, void *pData)
 {
-    ZXIC_UINT8 data[DPP_ETCAM_WIDTH_MAX/8] = {0};   /*640bit*/
-    ZXIC_UINT8 mask[DPP_ETCAM_WIDTH_MAX/8] = {0};   /*640bit*/
-    ZXIC_UINT8 rst[16] = {0};   /*128bit*/
-    ZXIC_UINT32 element_id = 0;
-    ZXIC_UINT32 rc = DPP_OK;
-
-    DPP_ACL_ENTRY_EX_T aclEntry = {0};
-    DPP_DTB_ACL_ENTRY_INFO_T tDtbAclEntry = {0};
-    DPP_SDTTBL_ETCAM_T sdt_acl_info = {0};  /*SDT内容*/
-    SE_APT_CALLBACK_T *pAptCallback = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_POINT(pData);
-
-    ZXIC_COMM_MEMSET(data, 0x0, sizeof(data));
-    ZXIC_COMM_MEMSET(mask, 0x0, sizeof(mask));
-    ZXIC_COMM_MEMSET(rst, 0x0, sizeof(rst));
-    ZXIC_COMM_MEMSET(&aclEntry, 0x0, sizeof(DPP_ACL_ENTRY_EX_T));
-    ZXIC_COMM_MEMSET(&tDtbAclEntry, 0x0, sizeof(DPP_DTB_ACL_ENTRY_INFO_T));
-
-    aclEntry.key_data = data;
-    aclEntry.key_mask = mask;
-    aclEntry.p_as_rslt = rst;
-
-    //从sdt_no中获取SDT配置
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_acl_info);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
-    
-    pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback->se_func_info.aclFunc.acl_set_func);
-
-    rc = pAptCallback->se_func_info.aclFunc.acl_set_func((void *)pData, &aclEntry);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "acl_entry_func");
-
-    tDtbAclEntry.handle = aclEntry.pri;
-    tDtbAclEntry.key_data = aclEntry.key_data;
-    tDtbAclEntry.key_mask = aclEntry.key_mask;
-    tDtbAclEntry.p_as_rslt = aclEntry.p_as_rslt;
-
-    rc = dpp_dtb_acl_dma_insert(dev, queue_id, sdt_no, 1, &tDtbAclEntry, &element_id);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_acl_dma_insert");
-
-    return rc;
+	ZXIC_UINT8 data[DPP_ETCAM_WIDTH_MAX / 8] = { 0 }; /*640bit*/
+	ZXIC_UINT8 mask[DPP_ETCAM_WIDTH_MAX / 8] = { 0 }; /*640bit*/
+	ZXIC_UINT8 rst[16] = { 0 }; /*128bit*/
+	ZXIC_UINT32 element_id = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	DPP_ACL_ENTRY_EX_T aclEntry = { 0 };
+	DPP_DTB_ACL_ENTRY_INFO_T tDtbAclEntry = { 0 };
+	DPP_SDTTBL_ETCAM_T sdt_acl_info = { 0 }; /*SDT内容*/
+	SE_APT_CALLBACK_T *pAptCallback = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(pData);
+
+	ZXIC_COMM_MEMSET(data, 0x0, sizeof(data));
+	ZXIC_COMM_MEMSET(mask, 0x0, sizeof(mask));
+	ZXIC_COMM_MEMSET(rst, 0x0, sizeof(rst));
+	ZXIC_COMM_MEMSET(&aclEntry, 0x0, sizeof(DPP_ACL_ENTRY_EX_T));
+	ZXIC_COMM_MEMSET(&tDtbAclEntry, 0x0, sizeof(DPP_DTB_ACL_ENTRY_INFO_T));
+
+	aclEntry.key_data = data;
+	aclEntry.key_mask = mask;
+	aclEntry.p_as_rslt = rst;
+
+	//从sdt_no中获取SDT配置
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_acl_info);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
+
+	pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev),
+							  pAptCallback->se_func_info.aclFunc.acl_set_func);
+
+	rc = pAptCallback->se_func_info.aclFunc.acl_set_func((void *)pData,
+														 &aclEntry);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "acl_entry_func");
+
+	tDtbAclEntry.handle = aclEntry.pri;
+	tDtbAclEntry.key_data = aclEntry.key_data;
+	tDtbAclEntry.key_mask = aclEntry.key_mask;
+	tDtbAclEntry.p_as_rslt = aclEntry.p_as_rslt;
+
+	rc = dpp_dtb_acl_dma_insert(dev, queue_id, sdt_no, 1, &tDtbAclEntry,
+								&element_id);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_acl_dma_insert");
+
+	return rc;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_comm.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_comm.c
index 6b55c52e8612fa16af03ba606eeadc05e0964c70..5418652544b5701f5213269e9afb33dbddfb41a3 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_comm.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_comm.c
@@ -26,290 +26,311 @@
 
 #define DTB_QUEUE_ACK_SIZE (16)
 #define DTB_QUEUE_ELEMENT_NUM (32)
-#define DTB_QUEUE_ELEMENT_DATA_SIZE (16*1024 + DTB_QUEUE_ACK_SIZE)//16k+16
-#define DTB_QUEUE_DATA_SIZE (DTB_QUEUE_ELEMENT_DATA_SIZE *  DTB_QUEUE_ELEMENT_NUM)
-#define DTB_QUEUE_ELEMENT_DUMP_SIZE (16*1024 + DTB_QUEUE_ACK_SIZE)//16K+16
-#define DTB_QUEUE_DUMP_SIZE (DTB_QUEUE_ELEMENT_DUMP_SIZE * DTB_QUEUE_ELEMENT_NUM)
+#define DTB_QUEUE_ELEMENT_DATA_SIZE (16 * 1024 + DTB_QUEUE_ACK_SIZE) // 16k+16
+#define DTB_QUEUE_DATA_SIZE \
+	(DTB_QUEUE_ELEMENT_DATA_SIZE * DTB_QUEUE_ELEMENT_NUM)
+#define DTB_QUEUE_ELEMENT_DUMP_SIZE (16 * 1024 + DTB_QUEUE_ACK_SIZE) // 16K+16
+#define DTB_QUEUE_DUMP_SIZE \
+	(DTB_QUEUE_ELEMENT_DUMP_SIZE * DTB_QUEUE_ELEMENT_NUM)
 #define DTB_QUEUE_DMA_SIZE (DTB_QUEUE_DATA_SIZE + DTB_QUEUE_DUMP_SIZE)
 
-
-SE_APT_CALLBACK_T  g_apt_se_callback[DPP_DEV_CHANNEL_MAX][DPP_DEV_SDT_ID_MAX] = {{{0}}};
+SE_APT_CALLBACK_T g_apt_se_callback[DPP_DEV_CHANNEL_MAX][DPP_DEV_SDT_ID_MAX] = {
+	{ { 0 } }
+};
 
 /***********************************************************/
 /** 根据设备id和sdt号获取指针
-* @param   p_new_key      新键值
-* @param   p_old_key      旧键值
-* @param   key_len        键值长度
-* @return  比较结果
-* @remark  无
-* @see
-* @author  chenqin00181032      @date  2023/02/24
-************************************************************/
-ZXIC_SINT32 dpp_apt_table_key_cmp(void *p_new_key, void *p_old_key, ZXIC_UINT32 key_len)
+ * @param   p_new_key      新键值
+ * @param   p_old_key      旧键值
+ * @param   key_len        键值长度
+ * @return  比较结果
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/24
+ ************************************************************/
+ZXIC_SINT32 dpp_apt_table_key_cmp(void *p_new_key, void *p_old_key,
+								  ZXIC_UINT32 key_len)
 {
-    ZXIC_COMM_CHECK_POINT(p_new_key);
-    ZXIC_COMM_CHECK_POINT(p_old_key);
-    /* 仅比较index */
-    ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_ASSERT(key_len, (ZXIC_UINT32)ZXIC_SIZEOF(ZXIC_UINT32));
-    return ZXIC_COMM_MEMCMP((ZXIC_UINT32 *)p_new_key, (ZXIC_UINT32 *)p_old_key,ZXIC_SIZEOF(ZXIC_UINT32));
+	ZXIC_COMM_CHECK_POINT(p_new_key);
+	ZXIC_COMM_CHECK_POINT(p_old_key);
+	/* 仅比较index */
+	ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_ASSERT(key_len,
+												 ZXIC_SIZEOF(ZXIC_UINT32));
+	return ZXIC_COMM_MEMCMP((ZXIC_UINT32 *)p_new_key, (ZXIC_UINT32 *)p_old_key,
+							ZXIC_SIZEOF(ZXIC_UINT32));
 }
 
 /***********************************************************/
 /** 根据设备id和sdt号获取指针
-* @param   dev_id      设备号
-* @param   sdt_no      业务表对应的sdt号
-* @return  
-* @remark  无
-* @see
-* @author  chenqin00181032      @date  2023/02/24
-************************************************************/
-SE_APT_CALLBACK_T *dpp_apt_get_func(ZXIC_UINT32 dev_id,ZXIC_UINT32 sdt_no)
+ * @param   dev_id      设备号
+ * @param   sdt_no      业务表对应的sdt号
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/24
+ ************************************************************/
+SE_APT_CALLBACK_T *dpp_apt_get_func(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no)
 {
-    ZXIC_COMM_CHECK_INDEX_RETURN_NULL_NO_ASSERT(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_RETURN_NULL_NO_ASSERT(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_RETURN_NULL_NO_ASSERT(dev_id, 0,
+												DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_RETURN_NULL_NO_ASSERT(sdt_no, 0,
+												DPP_DEV_SDT_ID_MAX - 1);
 
-    return &g_apt_se_callback[dev_id][sdt_no];
+	return &g_apt_se_callback[dev_id][sdt_no];
 }
 
 /***********************************************************/
 /** 保存回调参数信息
-* @param   dev_id      设备号
-* @param   sdt_no      业务表对应的sdt号
-* @param   table_type  SDT属性中的表类型，取值参考DPP_SDT_TABLE_TYPE_E的定义(仅添加操作时有效)
-* @param   pData       需保存的回调信息，由table_type确定此ZXIC_VOID型指针对应的数据结果
-* @return  
-* @remark  无
-* @see
-* @author  chenqin00181032      @date  2023/02/24
-************************************************************/
-DPP_STATUS dpp_apt_set_callback(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, ZXIC_UINT32 table_type,ZXIC_VOID *pData)
+ * @param   dev_id      设备号
+ * @param   sdt_no      业务表对应的sdt号
+ * @param   table_type  SDT属性中的表类型，取值参考DPP_SDT_TABLE_TYPE_E的定义(仅添加操作时有效)
+ * @param   pData       需保存的回调信息，由table_type确定此ZXIC_VOID型指针对应的数据结果
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/24
+ ************************************************************/
+DPP_STATUS dpp_apt_set_callback(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no,
+								ZXIC_UINT32 table_type, ZXIC_VOID *pData)
 {
-    SE_APT_CALLBACK_T *aptFunc = NULL;
-
-    aptFunc = dpp_apt_get_func(dev_id,sdt_no);
-    ZXIC_COMM_CHECK_POINT(aptFunc);
-
-    aptFunc->sdtNo = sdt_no;
-    aptFunc->table_type = table_type;
-
-    switch (table_type)
-    {
-        case DPP_SDT_TBLT_eRAM:
-        {
-            aptFunc->se_func_info.eramFunc.opr_mode = ((DPP_APT_ERAM_TABLE_T *)pData)->opr_mode;
-            aptFunc->se_func_info.eramFunc.rd_mode = ((DPP_APT_ERAM_TABLE_T *)pData)->rd_mode;
-            aptFunc->se_func_info.eramFunc.eram_set_func = ((DPP_APT_ERAM_TABLE_T *)pData)->eram_set_func;
-            aptFunc->se_func_info.eramFunc.eram_get_func = ((DPP_APT_ERAM_TABLE_T *)pData)->eram_get_func;
-            break;
-        } 
-		case DPP_SDT_TBLT_DDR3:
-        {
-            aptFunc->se_func_info.ddrFunc.ddr_tbl_depth = ((DPP_APT_DDR_TABLE_T *)pData)->ddr_table_depth;
-            aptFunc->se_func_info.ddrFunc.ddr_set_func = ((DPP_APT_DDR_TABLE_T *)pData)->ddr_set_func;
-            aptFunc->se_func_info.ddrFunc.ddr_get_func = ((DPP_APT_DDR_TABLE_T *)pData)->ddr_get_func;
-            break;
-        }
-        case DPP_SDT_TBLT_HASH:
-        {
-            aptFunc->se_func_info.hashFunc.hash_set_func = ((DPP_APT_HASH_TABLE_T *)pData)->hash_set_func;
-            aptFunc->se_func_info.hashFunc.hash_get_func = ((DPP_APT_HASH_TABLE_T *)pData)->hash_get_func;
-            break;
-        }
-        case DPP_SDT_TBLT_eTCAM:
-        {
-            aptFunc->se_func_info.aclFunc.acl_set_func = ((DPP_APT_ACL_TABLE_T *)pData)->acl_set_func;
-            aptFunc->se_func_info.aclFunc.acl_get_func = ((DPP_APT_ACL_TABLE_T *)pData)->acl_get_func;
-            break;
-        }
-        default:
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_apt_se_set_callback table_type[ %d ] is invalid!\n", table_type);
-            return DPP_ERR;
-        }
-    }
-
-    return DPP_OK;
+	SE_APT_CALLBACK_T *aptFunc = NULL;
+
+	aptFunc = dpp_apt_get_func(dev_id, sdt_no);
+	ZXIC_COMM_CHECK_POINT(aptFunc);
+
+	aptFunc->sdtNo = sdt_no;
+	aptFunc->table_type = table_type;
+
+	switch (table_type) {
+	case DPP_SDT_TBLT_eRAM: {
+		aptFunc->se_func_info.eramFunc.opr_mode =
+				((DPP_APT_ERAM_TABLE_T *)pData)->opr_mode;
+		aptFunc->se_func_info.eramFunc.rd_mode =
+				((DPP_APT_ERAM_TABLE_T *)pData)->rd_mode;
+		aptFunc->se_func_info.eramFunc.eram_set_func =
+				((DPP_APT_ERAM_TABLE_T *)pData)->eram_set_func;
+		aptFunc->se_func_info.eramFunc.eram_get_func =
+				((DPP_APT_ERAM_TABLE_T *)pData)->eram_get_func;
+		break;
+	}
+	case DPP_SDT_TBLT_DDR3: {
+		aptFunc->se_func_info.ddrFunc.ddr_tbl_depth =
+				((DPP_APT_DDR_TABLE_T *)pData)->ddr_table_depth;
+		aptFunc->se_func_info.ddrFunc.ddr_set_func =
+				((DPP_APT_DDR_TABLE_T *)pData)->ddr_set_func;
+		aptFunc->se_func_info.ddrFunc.ddr_get_func =
+				((DPP_APT_DDR_TABLE_T *)pData)->ddr_get_func;
+		break;
+	}
+	case DPP_SDT_TBLT_HASH: {
+		aptFunc->se_func_info.hashFunc.hash_set_func =
+				((DPP_APT_HASH_TABLE_T *)pData)->hash_set_func;
+		aptFunc->se_func_info.hashFunc.hash_get_func =
+				((DPP_APT_HASH_TABLE_T *)pData)->hash_get_func;
+		break;
+	}
+	case DPP_SDT_TBLT_eTCAM: {
+		aptFunc->se_func_info.aclFunc.acl_set_func =
+				((DPP_APT_ACL_TABLE_T *)pData)->acl_set_func;
+		aptFunc->se_func_info.aclFunc.acl_get_func =
+				((DPP_APT_ACL_TABLE_T *)pData)->acl_get_func;
+		break;
+	}
+	default: {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id,
+				"dpp_apt_se_set_callback table_type[ %d ] is invalid!\n",
+				table_type);
+		return DPP_ERR;
+	}
+	}
+
+	return DPP_OK;
 }
 
-DPP_STATUS dpp_apt_sw_list_insert(ZXIC_RB_CFG *rb_cfg,void *pData,ZXIC_UINT32 len)
+DPP_STATUS dpp_apt_sw_list_insert(ZXIC_RB_CFG *rb_cfg, void *pData,
+								  ZXIC_UINT32 len)
 {
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT8 *p_rb_key          = NULL;
-    ZXIC_RB_TN *p_rb_new     = NULL;
-    ZXIC_RB_TN *p_rb_rtn     = NULL;
-    ZXIC_UINT32 rc               = DPP_OK;
-
-    ZXIC_COMM_CHECK_POINT(rb_cfg);
-    ZXIC_COMM_CHECK_POINT(pData);
-
-    p_rb_key = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(len);
-    ZXIC_COMM_CHECK_POINT(p_rb_key);
-    ZXIC_COMM_MEMSET(p_rb_key,0x0,len);
-    ZXIC_COMM_MEMCPY(p_rb_key,pData,len);
-
-    p_rb_new = (ZXIC_RB_TN*)ZXIC_COMM_MALLOC(sizeof(ZXIC_RB_TN));
-    if (NULL == (p_rb_new))
-    {
-        ZXIC_COMM_FREE(p_rb_key);
-        ZXIC_COMM_TRACE_ERROR("\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", __FILE__, __LINE__, __FUNCTION__);
-        return ZXIC_PAR_CHK_POINT_NULL;
-    }
-    ZXIC_COMM_MEMSET(p_rb_new, 0, ZXIC_SIZEOF(ZXIC_RB_TN));
-    INIT_RBT_TN(p_rb_new, p_rb_key);
-
-    rc = zxic_comm_rb_insert(rb_cfg, p_rb_new, &p_rb_rtn);
-    if(rc == ZXIC_RBT_RC_UPDATE)
-    {
-        ZXIC_COMM_CHECK_POINT(p_rb_rtn);
-        ZXIC_COMM_MEMCPY(p_rb_rtn->p_key,pData,len);
-        ZXIC_COMM_FREE(p_rb_new);
-        ZXIC_COMM_FREE(p_rb_key);
-        ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "update exist entry!\n");
-        return DPP_OK;
-    }
-
-    return rc;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT8 *p_rb_key = NULL;
+	ZXIC_RB_TN *p_rb_new = NULL;
+	ZXIC_RB_TN *p_rb_rtn = NULL;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(rb_cfg);
+	ZXIC_COMM_CHECK_POINT(pData);
+
+	p_rb_key = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(len);
+	ZXIC_COMM_CHECK_POINT(p_rb_key);
+	ZXIC_COMM_MEMSET(p_rb_key, 0x0, len);
+	ZXIC_COMM_MEMCPY(p_rb_key, pData, len);
+
+	p_rb_new = (ZXIC_RB_TN *)ZXIC_COMM_MALLOC(sizeof(ZXIC_RB_TN));
+	if (NULL == (p_rb_new)) {
+		ZXIC_COMM_FREE(p_rb_key);
+		ZXIC_COMM_TRACE_ERROR(
+				"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", __FILE__,
+				__LINE__, __FUNCTION__);
+		return ZXIC_PAR_CHK_POINT_NULL;
+	}
+	ZXIC_COMM_MEMSET(p_rb_new, 0, ZXIC_SIZEOF(ZXIC_RB_TN));
+	INIT_RBT_TN(p_rb_new, p_rb_key);
+
+	rc = zxic_comm_rb_insert(rb_cfg, p_rb_new, &p_rb_rtn);
+	if (rc == ZXIC_RBT_RC_UPDATE) {
+		ZXIC_COMM_CHECK_POINT(p_rb_rtn);
+		ZXIC_COMM_MEMCPY(p_rb_rtn->p_key, pData, len);
+		ZXIC_COMM_FREE(p_rb_new);
+		ZXIC_COMM_FREE(p_rb_key);
+		ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "update exist entry!\n");
+		return DPP_OK;
+	}
+
+	return rc;
 }
 
-DPP_STATUS dpp_apt_sw_list_search(ZXIC_RB_CFG *rb_cfg,void *pData,ZXIC_UINT32 len)
+DPP_STATUS dpp_apt_sw_list_search(ZXIC_RB_CFG *rb_cfg, void *pData,
+								  ZXIC_UINT32 len)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-    ZXIC_RB_TN *p_rb_rtn     = NULL;
-
-    ZXIC_COMM_CHECK_POINT(rb_cfg);
-    
-    rc = zxic_comm_rb_search(rb_cfg,pData,&p_rb_rtn);
-    if(DPP_OK != rc)
-    {
-        return rc;
-    }
-    //ZXIC_COMM_CHECK_RC_NO_ASSERT( rc, "zxic_comm_rb_search");
-
-    ZXIC_COMM_MEMCPY(pData,p_rb_rtn->p_key,len);
-    return rc;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_RB_TN *p_rb_rtn = NULL;
+
+	ZXIC_COMM_CHECK_POINT(rb_cfg);
+
+	rc = zxic_comm_rb_search(rb_cfg, pData, &p_rb_rtn);
+	if (DPP_OK != rc) {
+		return rc;
+	}
+	// ZXIC_COMM_CHECK_RC_NO_ASSERT( rc, "zxic_comm_rb_search");
+
+	ZXIC_COMM_MEMCPY(pData, p_rb_rtn->p_key, len);
+	return rc;
 }
 
-DPP_STATUS dpp_apt_sw_list_delete(ZXIC_RB_CFG *rb_cfg,void *pData,ZXIC_UINT32 len)
+DPP_STATUS dpp_apt_sw_list_delete(ZXIC_RB_CFG *rb_cfg, void *pData,
+								  ZXIC_UINT32 len)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-    ZXIC_RB_TN *p_rb_rtn     = NULL;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_RB_TN *p_rb_rtn = NULL;
 
-    ZXIC_COMM_CHECK_POINT(rb_cfg);
+	ZXIC_COMM_CHECK_POINT(rb_cfg);
 
-    rc = zxic_comm_rb_delete(rb_cfg,pData,&p_rb_rtn);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_rb_delete");
-    ZXIC_COMM_FREE(p_rb_rtn->p_key);
-    ZXIC_COMM_FREE(p_rb_rtn);
+	rc = zxic_comm_rb_delete(rb_cfg, pData, &p_rb_rtn);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_rb_delete");
+	ZXIC_COMM_FREE(p_rb_rtn->p_key);
+	ZXIC_COMM_FREE(p_rb_rtn);
 
-    return rc;
+	return rc;
 }
 
-DPP_STATUS dpp_apt_get_zblock_index(ZXIC_UINT32 zblock_bitmap,ZXIC_UINT32 *zblk_idx)
+DPP_STATUS dpp_apt_get_zblock_index(ZXIC_UINT32 zblock_bitmap,
+									ZXIC_UINT32 *zblk_idx)
 {
-    ZXIC_UINT32 index0 = 0;
-    ZXIC_UINT32 index1 = 0;
+	ZXIC_UINT32 index0 = 0;
+	ZXIC_UINT32 index1 = 0;
 
-    ZXIC_COMM_CHECK_POINT(zblk_idx);
+	ZXIC_COMM_CHECK_POINT(zblk_idx);
 
-    for (index0 = 0; index0 < 32;index0++)
-    {
-        if((zblock_bitmap>>index0)&0x1)
-        {
-            *(zblk_idx + index1) = index0;
-            index1++;
-        }
-    }
+	for (index0 = 0; index0 < 32; index0++) {
+		if ((zblock_bitmap >> index0) & 0x1) {
+			*(zblk_idx + index1) = index0;
+			index1++;
+		}
+	}
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 DPP_STATUS dpp_apt_dtb_res_init(DPP_DEV_T *dev)
 {
-    ZXIC_UINT32 rc                       = DPP_OK;
-    ZXIC_UINT32 queue_id                 = 0;
-    ZXIC_UINT32 dma_size                 = 2 * DTB_QUEUE_DMA_SIZE;
-    ZXIC_UINT16 vport                    = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT8 *pf_name = "pf";
+	ZXIC_UINT32 queue_id = 0;
+	ZXIC_UINT32 dma_size = 2 * DTB_QUEUE_DMA_SIZE;
+	ZXIC_UINT16 vport = 0;
 
-    DTB_QUEUE_DMA_ADDR_INFO tDmaAddrInfo = {0};
+	DTB_QUEUE_DMA_ADDR_INFO tDmaAddrInfo = { 0 };
 
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
 
-    vport = DEV_PCIE_VPORT(dev);
+	vport = DEV_PCIE_VPORT(dev);
 
-    // 申请队列
-    rc = dpp_dtb_queue_requst(dev, "pf", vport, &queue_id);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_requst");
+	// 申请队列
+	rc = dpp_dtb_queue_requst(dev, pf_name, vport, &queue_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_requst");
 
-    /*分配下表DMA内存*/
-    ZXIC_COMM_MEMSET(&tDmaAddrInfo, 0x00, sizeof(DTB_QUEUE_DMA_ADDR_INFO));
-    rc = dpp_dtb_queue_dma_mem_alloc(dev, queue_id, dma_size);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_dma_mem_alloc");
+	/*分配下表DMA内存*/
+	ZXIC_COMM_MEMSET(&tDmaAddrInfo, 0x00, sizeof(DTB_QUEUE_DMA_ADDR_INFO));
+	rc = dpp_dtb_queue_dma_mem_alloc(dev, queue_id, dma_size);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_dma_mem_alloc");
 
-    rc = dpp_dtb_queue_dma_mem_get(dev, queue_id, &tDmaAddrInfo);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_dma_mem_get");
+	rc = dpp_dtb_queue_dma_mem_get(dev, queue_id, &tDmaAddrInfo);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_dma_mem_get");
 
-    // 配置下表地址空间
-    rc = dpp_dtb_queue_down_table_addr_set(dev, queue_id, 
-                    tDmaAddrInfo.dma_phy_addr, tDmaAddrInfo.dma_vir_addr);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_down_table_addr_set");
+	// 配置下表地址空间
+	rc = dpp_dtb_queue_down_table_addr_set(dev, queue_id,
+										   tDmaAddrInfo.dma_phy_addr,
+										   tDmaAddrInfo.dma_vir_addr);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_down_table_addr_set");
 
-    // 配置dump表地址空间
-    rc = dpp_dtb_queue_dump_table_addr_set(dev, queue_id,
-                                           tDmaAddrInfo.dma_phy_addr + DTB_QUEUE_DMA_SIZE,
-                                           tDmaAddrInfo.dma_vir_addr + DTB_QUEUE_DMA_SIZE);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_dump_table_addr_set");
+	// 配置dump表地址空间
+	rc = dpp_dtb_queue_dump_table_addr_set(
+			dev, queue_id, tDmaAddrInfo.dma_phy_addr + DTB_QUEUE_DMA_SIZE,
+			tDmaAddrInfo.dma_vir_addr + DTB_QUEUE_DMA_SIZE);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_dump_table_addr_set");
 
-    rc = dpp_dtb_user_info_set(dev, queue_id, vport, 0);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_user_info_set");
+	rc = dpp_dtb_user_info_set(dev, queue_id, vport, 0);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_user_info_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 根据设备id对表项公共参数初始化
-* @param   dev_id      设备号
-* @return  
-* @remark  无
-* @see
-* @author  cq      @date  2023/11/09
-************************************************************/
+ * @param   dev_id      设备号
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/11/09
+ ************************************************************/
 DPP_STATUS dpp_apt_se_callback_init(ZXIC_UINT32 dev_id)
 {
-    ZXIC_UINT32 sdt_no = 0;
+	ZXIC_UINT32 sdt_no = 0;
 
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
 
-    for(sdt_no=0;sdt_no<DPP_DEV_SDT_ID_MAX;sdt_no++)
-    {
-        ZXIC_COMM_MEMSET(&g_apt_se_callback[dev_id][sdt_no],0x0,sizeof(SE_APT_CALLBACK_T));
-    }
+	for (sdt_no = 0; sdt_no < DPP_DEV_SDT_ID_MAX; sdt_no++) {
+		ZXIC_COMM_MEMSET(&g_apt_se_callback[dev_id][sdt_no], 0x0,
+						 sizeof(SE_APT_CALLBACK_T));
+	}
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 释放sdt资源以及适配资源
-* @param   dev_id      设备号
-* @param   sdt_no      sdt号
-* @return  
-* @remark  无
-* @see
-* @author  cq      @date  2023/11/09
-************************************************************/
+ * @param   dev_id      设备号
+ * @param   sdt_no      sdt号
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/11/09
+ ************************************************************/
 DPP_STATUS dpp_apt_sdt_res_deinit(DPP_DEV_T *dev, ZXIC_UINT32 sdt_no)
 {
-    DPP_STATUS rc = DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	/*sdt资源初始化，包括硬件和软件*/
+	rc = dpp_sdt_tbl_write(dev, sdt_no, 0, NULL, 1);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_sdt_tbl_write");
 
-    /*sdt资源初始化，包括硬件和软件*/
-    rc = dpp_sdt_tbl_write(dev,sdt_no,0,NULL,1);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_sdt_tbl_write"); 
+	/*适配资源初始化*/
+	ZXIC_COMM_MEMSET(&g_apt_se_callback[DEV_ID(dev)][sdt_no], 0x0,
+					 sizeof(SE_APT_CALLBACK_T));
 
-    /*适配资源初始化*/
-    ZXIC_COMM_MEMSET(&g_apt_se_callback[DEV_ID(dev)][sdt_no],0x0,sizeof(SE_APT_CALLBACK_T));
-    
-    return DPP_OK;
+	return DPP_OK;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_ddr.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_ddr.c
index f2427f829ad8381f0bdb983ca054bf4b30e43e69..6ee23400f35ccedce7e62f729befb046a16aacc6 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_ddr.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_ddr.c
@@ -22,41 +22,38 @@
 
 /***********************************************************/
 /** DDR表资源初始化
-* @param   dev_id  设备号 
-* @param   tbl_num  需初始化的DDR表个数
-* @param   pDdrTbl  ddr资源信息，包括SDT配置信息，直接表读取位宽和结构体码流转换回调函数
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/07/26
-************************************************************/
-DPP_STATUS dpp_apt_ddr_res_init(DPP_DEV_T *dev,ZXIC_UINT32 tbl_num,DPP_APT_DDR_TABLE_T *pDdrTbl)
+ * @param   dev_id  设备号
+ * @param   tbl_num  需初始化的DDR表个数
+ * @param   pDdrTbl  ddr资源信息，包括SDT配置信息，直接表读取位宽和结构体码流转换回调函数
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/07/26
+ ************************************************************/
+DPP_STATUS dpp_apt_ddr_res_init(DPP_DEV_T *dev, ZXIC_UINT32 tbl_num,
+								DPP_APT_DDR_TABLE_T *pDdrTbl)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT8 index = 0;
-    DPP_APT_DDR_TABLE_T *pTempDdrTbl = NULL;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT8 index = 0;
+	DPP_APT_DDR_TABLE_T *pTempDdrTbl = NULL;
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(tbl_num, DPP_DEV_SDT_ID_MAX);
-    ZXIC_COMM_CHECK_POINT(pDdrTbl);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(tbl_num, DPP_DEV_SDT_ID_MAX);
+	ZXIC_COMM_CHECK_POINT(pDdrTbl);
 
-    for(index = 0;index < tbl_num;index++)
-    {
-        pTempDdrTbl = pDdrTbl + index;
-        rc = dpp_sdt_tbl_write(dev,
-                        pTempDdrTbl->sdtNo,
-                        pTempDdrTbl->eDdrSdt.table_type,
-                        &(pTempDdrTbl->eDdrSdt),
-                        SDT_OPER_ADD);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_sdt_tbl_write");
-        
-        rc = dpp_apt_set_callback(DEV_ID(dev),
-                        pTempDdrTbl->sdtNo,
-                        pTempDdrTbl->eDdrSdt.table_type,
-                        (ZXIC_VOID *)pTempDdrTbl);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_apt_set_callback");
-    }
+	for (index = 0; index < tbl_num; index++) {
+		pTempDdrTbl = pDdrTbl + index;
+		rc = dpp_sdt_tbl_write(dev, pTempDdrTbl->sdtNo,
+							   pTempDdrTbl->eDdrSdt.table_type,
+							   &(pTempDdrTbl->eDdrSdt), SDT_OPER_ADD);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_sdt_tbl_write");
 
-    return DPP_OK;
+		rc = dpp_apt_set_callback(DEV_ID(dev), pTempDdrTbl->sdtNo,
+								  pTempDdrTbl->eDdrSdt.table_type,
+								  (ZXIC_VOID *)pTempDdrTbl);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_apt_set_callback");
+	}
+
+	return DPP_OK;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_eram.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_eram.c
index 80ac8153b69011798ace2a8885a9624595943f0c..ddedf748a8d69cdbd5fce4b1c3b4dae7959d59f2 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_eram.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_eram.c
@@ -25,192 +25,188 @@
 
 /***********************************************************/
 /** eram表资源初始化
-* @param   dev_id  设备号 
-* @param   tbl_num  需初始化的eram表个数
-* @param   pEramTbl  eram资源信息，包括SDT配置信息，直接表读取位宽和结构体码流转换回调函数
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_eram_res_init(DPP_DEV_T *dev,ZXIC_UINT32 tbl_num,DPP_APT_ERAM_TABLE_T *pEramTbl)
+ * @param   dev_id  设备号
+ * @param   tbl_num  需初始化的eram表个数
+ * @param   pEramTbl  eram资源信息，包括SDT配置信息，直接表读取位宽和结构体码流转换回调函数
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_eram_res_init(DPP_DEV_T *dev, ZXIC_UINT32 tbl_num,
+								 DPP_APT_ERAM_TABLE_T *pEramTbl)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT8 index = 0;
-    DPP_APT_ERAM_TABLE_T *pTempEramTbl = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(tbl_num, DPP_DEV_SDT_ID_MAX);
-    ZXIC_COMM_CHECK_POINT(pEramTbl);
-
-    for(index = 0;index < tbl_num;index++)
-    {
-        pTempEramTbl = pEramTbl + index;
-        rc = dpp_sdt_tbl_write(dev,
-                        pTempEramTbl->sdtNo,
-                        pTempEramTbl->eRamSdt.table_type,
-                        &(pTempEramTbl->eRamSdt),
-                        SDT_OPER_ADD);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_sdt_tbl_write");
-
-        rc = dpp_apt_set_callback(DEV_ID(dev),
-                        pTempEramTbl->sdtNo,
-                        pTempEramTbl->eRamSdt.table_type,
-                        (ZXIC_VOID *)pTempEramTbl);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_apt_set_callback");
-    }
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT8 index = 0;
+	DPP_APT_ERAM_TABLE_T *pTempEramTbl = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(tbl_num, DPP_DEV_SDT_ID_MAX);
+	ZXIC_COMM_CHECK_POINT(pEramTbl);
+
+	for (index = 0; index < tbl_num; index++) {
+		pTempEramTbl = pEramTbl + index;
+		rc = dpp_sdt_tbl_write(dev, pTempEramTbl->sdtNo,
+							   pTempEramTbl->eRamSdt.table_type,
+							   &(pTempEramTbl->eRamSdt), SDT_OPER_ADD);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_sdt_tbl_write");
+
+		rc = dpp_apt_set_callback(DEV_ID(dev), pTempEramTbl->sdtNo,
+								  pTempEramTbl->eRamSdt.table_type,
+								  (ZXIC_VOID *)pTempEramTbl);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_apt_set_callback");
+	}
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** dtb eram表项插入/更新
-* @param   dev_id  设备号 
-* @param   sdt_no  SDT号 0~255
-* @param   index   条目index，索引范围随wrt_mode模式不同
-* @param   pData   插入表项内容，由业务确定
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_dtb_eram_insert(DPP_DEV_T *dev,ZXIC_UINT32 queue_id,ZXIC_UINT32 sdt_no,ZXIC_UINT32 index,void *pData)
+ * @param   dev_id  设备号
+ * @param   sdt_no  SDT号 0~255
+ * @param   index   条目index，索引范围随wrt_mode模式不同
+ * @param   pData   插入表项内容，由业务确定
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_dtb_eram_insert(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								   ZXIC_UINT32 sdt_no, ZXIC_UINT32 index,
+								   void *pData)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-    ZXIC_UINT32 element_id = 0;
-    ZXIC_UINT32 dump_data[4] = {0};
-    
-    SE_APT_CALLBACK_T *pAptCallback = NULL;
-    DPP_DTB_ERAM_ENTRY_INFO_T dtb_eram_entry = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-
-    ZXIC_COMM_MEMSET(dump_data, 0x00, sizeof(dump_data));
-
-    pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback);
-
-    rc = pAptCallback->se_func_info.eramFunc.eram_set_func(pData, dump_data);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "eram_set_func");
-
-    //dtb配表
-    dtb_eram_entry.index = index;
-    dtb_eram_entry.p_data = dump_data;
-    rc = dpp_dtb_eram_dma_write(dev, 
-                                      queue_id, 
-                                      sdt_no, 
-                                      1, 
-                                      &dtb_eram_entry,
-                                      &element_id);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_eram_dma_write");
-
-    return rc;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 element_id = 0;
+	ZXIC_UINT32 dump_data[4] = { 0 };
+
+	SE_APT_CALLBACK_T *pAptCallback = NULL;
+	DPP_DTB_ERAM_ENTRY_INFO_T dtb_eram_entry = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+
+	ZXIC_COMM_MEMSET(dump_data, 0x00, sizeof(dump_data));
+
+	pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback);
+
+	rc = pAptCallback->se_func_info.eramFunc.eram_set_func(pData, dump_data);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "eram_set_func");
+
+	// dtb配表
+	dtb_eram_entry.index = index;
+	dtb_eram_entry.p_data = dump_data;
+	rc = dpp_dtb_eram_dma_write(dev, queue_id, sdt_no, 1, &dtb_eram_entry,
+								&element_id);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_eram_dma_write");
+
+	return rc;
 }
 
 /***********************************************************/
 /** eram表项数据获取,从软件缓存中获取
-* @param   dev_id  设备号 
-* @param   sdt_no  SDT号 0~255
-* @param   index   条目index，索引范围随wrt_mode模式不同
-* @param   pData   出参，返回业务表项内容
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_dtb_eram_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 sdt_no, ZXIC_UINT32 index, void *pData)
+ * @param   dev_id  设备号
+ * @param   sdt_no  SDT号 0~255
+ * @param   index   条目index，索引范围随wrt_mode模式不同
+ * @param   pData   出参，返回业务表项内容
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_dtb_eram_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								ZXIC_UINT32 sdt_no, ZXIC_UINT32 index,
+								void *pData)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-    ZXIC_UINT32 dump_data[4] = {0};
-    SE_APT_CALLBACK_T *pAptCallback = NULL;
-    DPP_DTB_ERAM_ENTRY_INFO_T dump_eram_entry = {0};
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 dump_data[4] = { 0 };
+	SE_APT_CALLBACK_T *pAptCallback = NULL;
+	DPP_DTB_ERAM_ENTRY_INFO_T dump_eram_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
 
-    ZXIC_COMM_MEMSET(dump_data, 0x00, sizeof(dump_data));
+	ZXIC_COMM_MEMSET(dump_data, 0x00, sizeof(dump_data));
 
-    pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback);
+	pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback);
 
-    dump_eram_entry.index = index;
-    dump_eram_entry.p_data = dump_data;
-    rc = dpp_dtb_eram_data_get(dev, queue_id, sdt_no, &dump_eram_entry);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT( rc, "dpp_dtb_eram_data_get");
+	dump_eram_entry.index = index;
+	dump_eram_entry.p_data = dump_data;
+	rc = dpp_dtb_eram_data_get(dev, queue_id, sdt_no, &dump_eram_entry);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get");
 
-    rc = pAptCallback->se_func_info.eramFunc.eram_get_func(pData, dump_eram_entry.p_data);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "eram_get_func");
+	rc = pAptCallback->se_func_info.eramFunc.eram_get_func(
+			pData, dump_eram_entry.p_data);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "eram_get_func");
 
-    return rc;
+	return rc;
 }
 
 /***********************************************************/
 /** eram表项删除,软件维护删除
-* @param   dev_id  设备号 
-* @param   sdt_no  SDT号 0~255
-* @param   index   条目index，索引范围随wrt_mode模式不同
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_dtb_eram_clear(DPP_DEV_T *dev,ZXIC_UINT32 queue_id,ZXIC_UINT32 sdt_no,ZXIC_UINT32 index)
+ * @param   dev_id  设备号
+ * @param   sdt_no  SDT号 0~255
+ * @param   index   条目index，索引范围随wrt_mode模式不同
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_dtb_eram_clear(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								  ZXIC_UINT32 sdt_no, ZXIC_UINT32 index)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-    ZXIC_UINT32 element_id = 0;
-    ZXIC_UINT32 dump_data[4] = {0};
-
-    SE_APT_CALLBACK_T *pAptCallback = NULL;
-    DPP_DTB_ERAM_ENTRY_INFO_T dtb_eram_entry = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-
-    ZXIC_COMM_MEMSET(dump_data, 0x00, sizeof(dump_data));
-
-    pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback);
-
-    //dtb配表
-    dtb_eram_entry.index = index;
-    dtb_eram_entry.p_data = dump_data;
-    rc = dpp_dtb_eram_dma_write(dev, 
-                                      queue_id, 
-                                      sdt_no, 
-                                      1, 
-                                      &dtb_eram_entry,
-                                      &element_id);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_eram_dma_write");
-
-    return rc;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 element_id = 0;
+	ZXIC_UINT32 dump_data[4] = { 0 };
+
+	SE_APT_CALLBACK_T *pAptCallback = NULL;
+	DPP_DTB_ERAM_ENTRY_INFO_T dtb_eram_entry = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+
+	ZXIC_COMM_MEMSET(dump_data, 0x00, sizeof(dump_data));
+
+	pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback);
+
+	// dtb配表
+	dtb_eram_entry.index = index;
+	dtb_eram_entry.p_data = dump_data;
+	rc = dpp_dtb_eram_dma_write(dev, queue_id, sdt_no, 1, &dtb_eram_entry,
+								&element_id);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_eram_dma_write");
+
+	return rc;
 }
 
 /***********************************************************/
 /** eram表项flush
-* @param   dev_id  设备号 
-* @param   sdt_no  SDT号 0~255
-* @param   index   条目index，索引范围随wrt_mode模式不同
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_dtb_eram_flush(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 sdt_no)
+ * @param   dev_id  设备号
+ * @param   sdt_no  SDT号 0~255
+ * @param   index   条目index，索引范围随wrt_mode模式不同
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_dtb_eram_flush(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								  ZXIC_UINT32 sdt_no)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
 
-    rc = dpp_dtb_eram_table_flush(dev, queue_id, sdt_no);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_table_flush");
-    ZXIC_COMM_TRACE_ERROR("dpp_apt_dtb_eram_flush sdt_no %d done.\n", sdt_no);
+	rc = dpp_dtb_eram_table_flush(dev, queue_id, sdt_no);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_table_flush");
+	ZXIC_COMM_TRACE_ERROR("dpp_apt_dtb_eram_flush sdt_no %d done.\n", sdt_no);
 
-    return rc;
+	return rc;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_hash.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_hash.c
index 90969157c54295f5e12db51b7909e4f874938dfd..a15bc12ae76d31ed480c82e950a10122d9771de9 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_hash.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/se_apt/dpp_apt_se_hash.c
@@ -24,303 +24,298 @@
 #include "dpp_dtb_table.h"
 #include "dpp_dtb_table_api.h"
 
-static DPP_SE_CFG g_apt_se_cfg = {{{0}}};
+static DPP_SE_CFG g_apt_se_cfg = { { { 0 } } };
 
 /***********************************************************/
 /** hash表全局资源初始化
-* @param   dev_id  设备号 
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
+ * @param   dev_id  设备号
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
 DPP_STATUS dpp_apt_hash_global_res_init(DPP_DEV_T *dev)
 {
-    DPP_STATUS rc = DPP_OK;
+	DPP_STATUS rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
 
-    rc = dpp_se_init(dev, &g_apt_se_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_init");
+	rc = dpp_se_init(dev, &g_apt_se_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_init");
 
-    rc = dpp_se_client_init(&g_apt_se_cfg, ZXIC_COMM_VAL_TO_PTR(DEV_ID(dev)));
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_client_init");
+	rc = dpp_se_client_init(&g_apt_se_cfg, ZXIC_COMM_VAL_TO_PTR(DEV_ID(dev)));
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_client_init");
 
-    return rc;
+	return rc;
 }
 
 /***********************************************************/
 /** hash引擎初始化
-* @param   dev_id  设备号 
-* @param   func_num     需初始化的hash引擎个数 1~4
-* @param   pHashFuncRes  每个hash引擎分配的zblock个数和编号，以及分配模式(混合模式或者纯片内模式)
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_hash_func_res_init(ZXIC_UINT32 dev_id,ZXIC_UINT32 func_num,DPP_APT_HASH_FUNC_RES_T *pHashFuncRes)
+ * @param   dev_id  设备号
+ * @param   func_num     需初始化的hash引擎个数 1~4
+ * @param   pHashFuncRes  每个hash引擎分配的zblock个数和编号，以及分配模式(混合模式或者纯片内模式)
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_hash_func_res_init(ZXIC_UINT32 dev_id, ZXIC_UINT32 func_num,
+									  DPP_APT_HASH_FUNC_RES_T *pHashFuncRes)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT32 zblk_idx[32] = {0};
-    DPP_APT_HASH_FUNC_RES_T *pHashFuncResTemp = NULL;
-
-    ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(func_num, HASH_FUNC_ID_NUM);
-    ZXIC_COMM_CHECK_POINT(pHashFuncRes);
-
-    for (index = 0; index < func_num;index++)
-    {
-        ZXIC_COMM_MEMSET(zblk_idx,0x0,sizeof(zblk_idx));
-        pHashFuncResTemp = pHashFuncRes+index;
-        rc = dpp_apt_get_zblock_index(pHashFuncResTemp->zblk_bitmap,zblk_idx);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_apt_get_zblock_index");
-
-        rc = dpp_hash_init(&g_apt_se_cfg, 
-                            pHashFuncResTemp->func_id, 
-                            pHashFuncResTemp->zblk_num, 
-                            zblk_idx, 
-                            pHashFuncResTemp->ddr_dis);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_init");
-    }
-
-    return rc;
-
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 zblk_idx[32] = { 0 };
+	DPP_APT_HASH_FUNC_RES_T *pHashFuncResTemp = NULL;
+
+	ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(func_num, HASH_FUNC_ID_NUM);
+	ZXIC_COMM_CHECK_POINT(pHashFuncRes);
+
+	for (index = 0; index < func_num; index++) {
+		ZXIC_COMM_MEMSET(zblk_idx, 0x0, sizeof(zblk_idx));
+		pHashFuncResTemp = pHashFuncRes + index;
+		rc = dpp_apt_get_zblock_index(pHashFuncResTemp->zblk_bitmap, zblk_idx);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_apt_get_zblock_index");
+
+		rc = dpp_hash_init(&g_apt_se_cfg, pHashFuncResTemp->func_id,
+						   pHashFuncResTemp->zblk_num, zblk_idx,
+						   pHashFuncResTemp->ddr_dis);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_init");
+	}
+
+	return rc;
 }
 
 /***********************************************************/
 /** hash引擎初始化(删除硬件数据)
-* @param   dev_id  设备号 
-* @param   func_num     需初始化的hash引擎个数 1~4
-* @param   pHashFuncRes  每个hash引擎分配的zblock个数和编号，以及分配模式(混合模式或者纯片内模式)
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_hash_func_flush_hardware_all(DPP_DEV_T *dev, 
-                                            ZXIC_UINT32 func_num, 
-                                            DPP_APT_HASH_FUNC_RES_T *pHashFuncRes, 
-                                            ZXIC_UINT32 queue_id)
+ * @param   dev_id  设备号
+ * @param   func_num     需初始化的hash引擎个数 1~4
+ * @param   pHashFuncRes  每个hash引擎分配的zblock个数和编号，以及分配模式(混合模式或者纯片内模式)
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS
+dpp_apt_hash_func_flush_hardware_all(DPP_DEV_T *dev, ZXIC_UINT32 func_num,
+									 DPP_APT_HASH_FUNC_RES_T *pHashFuncRes,
+									 ZXIC_UINT32 queue_id)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 index = 0;
-    DPP_APT_HASH_FUNC_RES_T *pHashFuncResTemp = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(func_num, HASH_FUNC_ID_NUM);
-    for (index = 0; index < func_num; index++)
-    {
-        pHashFuncResTemp = pHashFuncRes + index;
-
-        rc = dpp_dtb_zcam_space_clr(dev, &g_apt_se_cfg, queue_id, pHashFuncResTemp->func_id);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_zcam_space_clr");
-    }
-
-    return rc;
-    
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 index = 0;
+	DPP_APT_HASH_FUNC_RES_T *pHashFuncResTemp = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(func_num, HASH_FUNC_ID_NUM);
+	for (index = 0; index < func_num; index++) {
+		pHashFuncResTemp = pHashFuncRes + index;
+
+		rc = dpp_dtb_zcam_space_clr(dev, &g_apt_se_cfg, queue_id,
+									pHashFuncResTemp->func_id);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_zcam_space_clr");
+	}
+
+	return rc;
 }
 
 /***********************************************************/
 /** hash引擎bulk空间初始化
-* @param   dev_id  设备号 
-* @param   bulk_num     需初始化的bulk表个数 1~32
-* @param   pBulkRes  zcell和zreg资源占用信息，如果是混合模式，需进行DDR资源分配
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_hash_bulk_res_init(ZXIC_UINT32 dev_id,ZXIC_UINT32 bulk_num,DPP_APT_HASH_BULK_RES_T *pBulkRes)
+ * @param   dev_id  设备号
+ * @param   bulk_num     需初始化的bulk表个数 1~32
+ * @param   pBulkRes  zcell和zreg资源占用信息，如果是混合模式，需进行DDR资源分配
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_hash_bulk_res_init(ZXIC_UINT32 dev_id, ZXIC_UINT32 bulk_num,
+									  DPP_APT_HASH_BULK_RES_T *pBulkRes)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 index = 0;
-    DPP_APT_HASH_BULK_RES_T *pHashBulkResTemp = NULL;
-    DPP_HASH_DDR_RESC_CFG_T ddr_resc_cfg = {0};
-
-    ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(bulk_num, HASH_FUNC_ID_NUM*HASH_BULK_NUM);
-    ZXIC_COMM_CHECK_POINT(pBulkRes);
-
-    for (index = 0; index < bulk_num;index++)
-    {
-        ZXIC_COMM_MEMSET(&ddr_resc_cfg,0x0,sizeof(DPP_HASH_DDR_RESC_CFG_T));
-        pHashBulkResTemp = pBulkRes+index;
-        
-        ddr_resc_cfg.ddr_baddr = pHashBulkResTemp->ddr_baddr;
-        ddr_resc_cfg.ddr_item_num = pHashBulkResTemp->ddr_item_num;
-        ddr_resc_cfg.ddr_width_mode = pHashBulkResTemp->ddr_width_mode;
-        ddr_resc_cfg.ddr_crc_sel = pHashBulkResTemp->ddr_crc_sel;
-        ddr_resc_cfg.ddr_ecc_en = pHashBulkResTemp->ddr_ecc_en;
-        
-        rc = dpp_hash_bulk_init(&g_apt_se_cfg,
-                            pHashBulkResTemp->func_id,
-                            pHashBulkResTemp->bulk_id,
-                            &ddr_resc_cfg,
-                            pHashBulkResTemp->zcell_num,
-                            pHashBulkResTemp->zreg_num);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_bulk_init");
-    }
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 index = 0;
+	DPP_APT_HASH_BULK_RES_T *pHashBulkResTemp = NULL;
+	DPP_HASH_DDR_RESC_CFG_T ddr_resc_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(bulk_num, HASH_FUNC_ID_NUM * HASH_BULK_NUM);
+	ZXIC_COMM_CHECK_POINT(pBulkRes);
+
+	for (index = 0; index < bulk_num; index++) {
+		ZXIC_COMM_MEMSET(&ddr_resc_cfg, 0x0, sizeof(DPP_HASH_DDR_RESC_CFG_T));
+		pHashBulkResTemp = pBulkRes + index;
+
+		ddr_resc_cfg.ddr_baddr = pHashBulkResTemp->ddr_baddr;
+		ddr_resc_cfg.ddr_item_num = pHashBulkResTemp->ddr_item_num;
+		ddr_resc_cfg.ddr_width_mode = pHashBulkResTemp->ddr_width_mode;
+		ddr_resc_cfg.ddr_crc_sel = pHashBulkResTemp->ddr_crc_sel;
+		ddr_resc_cfg.ddr_ecc_en = pHashBulkResTemp->ddr_ecc_en;
+
+		rc = dpp_hash_bulk_init(&g_apt_se_cfg, pHashBulkResTemp->func_id,
+								pHashBulkResTemp->bulk_id, &ddr_resc_cfg,
+								pHashBulkResTemp->zcell_num,
+								pHashBulkResTemp->zreg_num);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_bulk_init");
+	}
+
+	return rc;
 }
 
 /***********************************************************/
 /** hash业务表属性初始化
-* @param   dev_id  设备号 
-* @param   tbl_num     需初始化的业务表表个数 1~128
-* @param   pHashTbl  sdt配置信息，初始化标记和业务结构体码流转换函数
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_hash_tbl_res_init(DPP_DEV_T *dev,ZXIC_UINT32 tbl_num,DPP_APT_HASH_TABLE_T *pHashTbl)
+ * @param   dev_id  设备号
+ * @param   tbl_num     需初始化的业务表表个数 1~128
+ * @param   pHashTbl  sdt配置信息，初始化标记和业务结构体码流转换函数
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_hash_tbl_res_init(DPP_DEV_T *dev, ZXIC_UINT32 tbl_num,
+									 DPP_APT_HASH_TABLE_T *pHashTbl)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 index = 0;
-    DPP_APT_HASH_TABLE_T *pHashTblTemp = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(tbl_num, HASH_FUNC_ID_NUM*HASH_TBL_ID_NUM);
-    ZXIC_COMM_CHECK_POINT(pHashTbl);
-
-    for (index = 0; index < tbl_num;index++)
-    {
-        pHashTblTemp = pHashTbl+ index;
-        rc = dpp_sdt_tbl_write(dev,
-                                   pHashTblTemp->sdtNo,
-                                   pHashTblTemp->hashSdt.table_type,
-                                   &pHashTblTemp->hashSdt,
-                                   SDT_OPER_ADD);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_sdt_tbl_write");
-
-        rc = dpp_hash_tbl_id_info_init(&g_apt_se_cfg,
-                                           pHashTblTemp->hashSdt.hash_id,
-                                           pHashTblTemp->hashSdt.hash_table_id,
-                                           pHashTblTemp->tbl_flag,
-                                           pHashTblTemp->hashSdt.hash_table_width,
-                                           pHashTblTemp->hashSdt.key_size);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_tbl_id_info_init_ex");
-
-        rc = dpp_apt_set_callback(DEV_ID(dev),
-                        pHashTblTemp->sdtNo,
-                        pHashTblTemp->hashSdt.table_type,
-                        (ZXIC_VOID *)pHashTblTemp);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_apt_set_callback");
-    }
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 index = 0;
+	DPP_APT_HASH_TABLE_T *pHashTblTemp = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(tbl_num, HASH_FUNC_ID_NUM * HASH_TBL_ID_NUM);
+	ZXIC_COMM_CHECK_POINT(pHashTbl);
+
+	for (index = 0; index < tbl_num; index++) {
+		pHashTblTemp = pHashTbl + index;
+		rc = dpp_sdt_tbl_write(dev, pHashTblTemp->sdtNo,
+							   pHashTblTemp->hashSdt.table_type,
+							   &pHashTblTemp->hashSdt, SDT_OPER_ADD);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_sdt_tbl_write");
+
+		rc = dpp_hash_tbl_id_info_init(&g_apt_se_cfg,
+									   pHashTblTemp->hashSdt.hash_id,
+									   pHashTblTemp->hashSdt.hash_table_id,
+									   pHashTblTemp->tbl_flag,
+									   pHashTblTemp->hashSdt.hash_table_width,
+									   pHashTblTemp->hashSdt.key_size);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_tbl_id_info_init_ex");
+
+		rc = dpp_apt_set_callback(DEV_ID(dev), pHashTblTemp->sdtNo,
+								  pHashTblTemp->hashSdt.table_type,
+								  (ZXIC_VOID *)pHashTblTemp);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_apt_set_callback");
+	}
+
+	return rc;
 }
 
 /***********************************************************/
 /** dtb hash表项插入/更新
-* @param   dev_id  设备号 
-* @param   sdt_no  sdt号 0~255
-* @param   pData   插入hash表项信息,由业务确定
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_dtb_hash_insert(DPP_DEV_T *dev,ZXIC_UINT32 queue_id,ZXIC_UINT32 sdt_no,void *pData)
+ * @param   dev_id  设备号
+ * @param   sdt_no  sdt号 0~255
+ * @param   pData   插入hash表项信息,由业务确定
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_dtb_hash_insert(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								   ZXIC_UINT32 sdt_no, void *pData)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT8 key_valid = 1;
-    DPP_HASH_ENTRY entry = {0};
-    DPP_SDTTBL_HASH_T sdt_hash_info = {0};  /*SDT内容*/
-    ZXIC_UINT8 aucKey[HASH_KEY_MAX] = {0};
-    ZXIC_UINT8 aucRst[HASH_RST_MAX] = {0};
-    SE_APT_CALLBACK_T *pAptCallback = NULL;
-    DPP_DTB_HASH_ENTRY_INFO_T tDtbHashEntry = {0};
-    ZXIC_UINT32 element_id = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-
-    //从sdt_no中获取SDT配置
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
-    
-    pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback);
-
-    entry.p_key = aucKey;
-    entry.p_rst = aucRst;
-    ZXIC_COMM_MEMSET(entry.p_key,0x0,sizeof(aucKey));
-    ZXIC_COMM_MEMSET(entry.p_rst,0x0,sizeof(aucRst));
-    entry.p_key[0] = DPP_GET_HASH_KEY_CTRL(key_valid, 
-                                            sdt_hash_info.hash_table_width, 
-                                            sdt_hash_info.hash_table_id);
-    rc = pAptCallback->se_func_info.hashFunc.hash_set_func(pData,&entry);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "hash_set_func");
-
-    tDtbHashEntry.p_actu_key = &entry.p_key[1];
-    tDtbHashEntry.p_rst = entry.p_rst;
-
-    rc = dpp_dtb_hash_dma_insert(dev, queue_id,sdt_no,1,&tDtbHashEntry,&element_id);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_hash_dma_insert");
-                                   
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT8 key_valid = 1;
+	DPP_HASH_ENTRY entry = { 0 };
+	DPP_SDTTBL_HASH_T sdt_hash_info = { 0 }; /*SDT内容*/
+	ZXIC_UINT8 aucKey[HASH_KEY_MAX] = { 0 };
+	ZXIC_UINT8 aucRst[HASH_RST_MAX] = { 0 };
+	SE_APT_CALLBACK_T *pAptCallback = NULL;
+	DPP_DTB_HASH_ENTRY_INFO_T tDtbHashEntry = { 0 };
+	ZXIC_UINT32 element_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+
+	//从sdt_no中获取SDT配置
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
+
+	pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback);
+
+	entry.p_key = aucKey;
+	entry.p_rst = aucRst;
+	ZXIC_COMM_MEMSET(entry.p_key, 0x0, sizeof(aucKey));
+	ZXIC_COMM_MEMSET(entry.p_rst, 0x0, sizeof(aucRst));
+	entry.p_key[0] = DPP_GET_HASH_KEY_CTRL(key_valid,
+										   sdt_hash_info.hash_table_width,
+										   sdt_hash_info.hash_table_id);
+	rc = pAptCallback->se_func_info.hashFunc.hash_set_func(pData, &entry);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "hash_set_func");
+
+	tDtbHashEntry.p_actu_key = &entry.p_key[1];
+	tDtbHashEntry.p_rst = entry.p_rst;
+
+	rc = dpp_dtb_hash_dma_insert(dev, queue_id, sdt_no, 1, &tDtbHashEntry,
+								 &element_id);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_hash_dma_insert");
+
+	return rc;
 }
 
 /***********************************************************/
 /** dtb hash表项删除
-* @param   dev_id  设备号 
-* @param   sdt_no  sdt号 0~255
-* @param   pData   删除hash表项信息,由业务传入
-* @return  
-* @remark  无
-* @see     
-* @author  chenqin00181032      @date  2023/02/22
-************************************************************/
-DPP_STATUS dpp_apt_dtb_hash_delete(DPP_DEV_T *dev,ZXIC_UINT32 queue_id,ZXIC_UINT32 sdt_no,void *pData)
+ * @param   dev_id  设备号
+ * @param   sdt_no  sdt号 0~255
+ * @param   pData   删除hash表项信息,由业务传入
+ * @return
+ * @remark  无
+ * @see
+ * @author  chenqin00181032      @date  2023/02/22
+ ************************************************************/
+DPP_STATUS dpp_apt_dtb_hash_delete(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								   ZXIC_UINT32 sdt_no, void *pData)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT8 key_valid = 1;
-    DPP_HASH_ENTRY entry = {0};
-    DPP_SDTTBL_HASH_T sdt_hash_info = {0};  /*SDT内容*/
-    ZXIC_UINT8 aucKey[HASH_KEY_MAX] = {0}; 
-    ZXIC_UINT8 aucRst[HASH_RST_MAX] = {0};
-    SE_APT_CALLBACK_T *pAptCallback = NULL;
-    DPP_DTB_HASH_ENTRY_INFO_T tDtbHashEntry = {0};
-    // ZXIC_UINT32 queue_id = 0;
-    ZXIC_UINT32 element_id = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-
-    //从sdt_no中获取SDT配置
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
-    
-    pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback);
-
-    entry.p_key = aucKey;
-    entry.p_rst = aucRst;
-    ZXIC_COMM_MEMSET(entry.p_key,0x0,sizeof(aucKey));
-    ZXIC_COMM_MEMSET(entry.p_rst,0x0,sizeof(aucRst));
-    entry.p_key[0] = DPP_GET_HASH_KEY_CTRL(key_valid, 
-                                            sdt_hash_info.hash_table_width, 
-                                            sdt_hash_info.hash_table_id);
-    rc = pAptCallback->se_func_info.hashFunc.hash_set_func(pData,&entry);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "hash_set_func");
-    
-    ZXIC_COMM_MEMSET(&tDtbHashEntry,0x0,sizeof(DPP_DTB_HASH_ENTRY_INFO_T));
-    ZXIC_COMM_MEMSET(entry.p_rst,0x0,sizeof(aucRst));
-    tDtbHashEntry.p_actu_key = &entry.p_key[1];
-    tDtbHashEntry.p_rst = entry.p_rst;
-    rc = dpp_dtb_hash_dma_delete(dev, queue_id,sdt_no,1,&tDtbHashEntry,&element_id);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_hash_dma_delete");
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT8 key_valid = 1;
+	DPP_HASH_ENTRY entry = { 0 };
+	DPP_SDTTBL_HASH_T sdt_hash_info = { 0 }; /*SDT内容*/
+	ZXIC_UINT8 aucKey[HASH_KEY_MAX] = { 0 };
+	ZXIC_UINT8 aucRst[HASH_RST_MAX] = { 0 };
+	SE_APT_CALLBACK_T *pAptCallback = NULL;
+	DPP_DTB_HASH_ENTRY_INFO_T tDtbHashEntry = { 0 };
+	// ZXIC_UINT32 queue_id = 0;
+	ZXIC_UINT32 element_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+
+	//从sdt_no中获取SDT配置
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
+
+	pAptCallback = dpp_apt_get_func(DEV_ID(dev), sdt_no);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pAptCallback);
+
+	entry.p_key = aucKey;
+	entry.p_rst = aucRst;
+	ZXIC_COMM_MEMSET(entry.p_key, 0x0, sizeof(aucKey));
+	ZXIC_COMM_MEMSET(entry.p_rst, 0x0, sizeof(aucRst));
+	entry.p_key[0] = DPP_GET_HASH_KEY_CTRL(key_valid,
+										   sdt_hash_info.hash_table_width,
+										   sdt_hash_info.hash_table_id);
+	rc = pAptCallback->se_func_info.hashFunc.hash_set_func(pData, &entry);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "hash_set_func");
+
+	ZXIC_COMM_MEMSET(&tDtbHashEntry, 0x0, sizeof(DPP_DTB_HASH_ENTRY_INFO_T));
+	ZXIC_COMM_MEMSET(entry.p_rst, 0x0, sizeof(aucRst));
+	tDtbHashEntry.p_actu_key = &entry.p_key[1];
+	tDtbHashEntry.p_rst = entry.p_rst;
+	rc = dpp_dtb_hash_dma_delete(dev, queue_id, sdt_no, 1, &tDtbHashEntry,
+								 &element_id);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_hash_dma_delete");
+
+	return rc;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/dpp_sdt.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/dpp_sdt.c
old mode 100755
new mode 100644
index b71bcdf9f873feab0c445cdc484cad33fcb414fe..685ade75aeb5716752d84700159b2eefb7424cbb
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/dpp_sdt.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/dpp_sdt.c
@@ -1,469 +1,620 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_sdt.c
-* 文件标识 : sdt配置接口实现文件
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : 王春雷
-* 完成日期 : 2015/06/25
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-
-#include "zxic_common.h"
-
-#include "dpp_dev.h"
-#include "dpp_se.h"
-#include "dpp_sdt_def.h"
-#include "dpp_sdt_mgr.h"
-#include "dpp_sdt.h"
-
-/* 全局变量*/
-ZXIC_UINT32 g_table_type[DPP_DEV_CHANNEL_MAX][DPP_DEV_SDT_ID_MAX] = {{0}};
-DPP_SDT_TBL_DATA_T  g_sdt_info[DPP_DEV_CHANNEL_MAX][DPP_DEV_SDT_ID_MAX] = {{{0}}};
-
-/** 获取低n位数据 */
-#define DPP_SDT_GET_LOW_DATA(source_value, low_width)        (source_value &((1<<low_width)-1))
-
-#if ZXIC_REAL("function for FCM_FTM ")
-/***********************************************************/
-/** 初始化SDT表配置管理
-* @param   dev_num       设备数目
-* @param   dev_id_array  设备dev_id数组
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/07/13
-************************************************************/
-DPP_STATUS dpp_sdt_init(ZXIC_UINT32 dev_num, ZXIC_UINT32 *dev_id_array)
-{
-    DPP_STATUS rc = 0;
-    ZXIC_UINT32 i = 0;
-
-    ZXIC_COMM_CHECK_INDEX(dev_num, 1, DPP_DEV_CHANNEL_MAX);
-    ZXIC_COMM_CHECK_POINT(dev_id_array);
-
-    for (i = 0; i < dev_num; i++)
-    {  
-        ZXIC_COMM_CHECK_INDEX(*(dev_id_array + i), 0, DPP_DEV_CHANNEL_MAX - 1);
-    }
-
-    dpp_sdt_mgr_init();
-
-    for (i = 0; i < dev_num; i++)
-    {
-        rc = dpp_sdt_mgr_create(dev_id_array[i]);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_sdt_mgr_create");
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 解析从硬件读取的64bit SDT属性
-* @param   sdt_hig32   硬件表中存储的SDT属性高32bit
-* @param   sdt_low32   硬件表中存储的SDT属性低32bit
-* @param   p_sdt_info  解析之后的SDT属性，根据SDT属性中的table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n
-*                      DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR3_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、\n
-*                      DPP_SDTTBL_ETCAM_T、DPP_SDTTBL_PORTTBL_T。
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/07/13
-************************************************************/
-DPP_STATUS dpp_sdt_tbl_data_parser(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_hig32, ZXIC_UINT32 sdt_low32, ZXIC_VOID *p_sdt_info)
-{
-    ZXIC_UINT32 tmp = 0;
-    ZXIC_UINT32 tbl_type = 0;
-    ZXIC_UINT32 clutch_en = 0;
-
-    DPP_SDTTBL_ERAM_T *p_sdt_eram = NULL;
-    DPP_SDTTBL_DDR3_T *p_sdt_ddr3 = NULL;
-    DPP_SDTTBL_HASH_T *p_sdt_hash = NULL;
-    DPP_SDTTBL_LPM_T *p_sdt_lpm = NULL;
-    DPP_SDTTBL_ETCAM_T *p_sdt_etcam = NULL;
-    DPP_SDTTBL_PORTTBL_T *p_sdt_porttbl = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_sdt_info);
-
-    ZXIC_COMM_UINT32_GET_BITS(tbl_type,  sdt_hig32, DPP_SDT_H_TBL_TYPE_BT_POS,     DPP_SDT_H_TBL_TYPE_BT_LEN);
-    ZXIC_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, DPP_SDT_L_CLUTCH_EN_BT_POS,    DPP_SDT_L_CLUTCH_EN_BT_LEN);
-
-    /* 根据表类型解析数据 */
-    switch (tbl_type)
-    {
-        case DPP_SDT_TBLT_eRAM:
-        {
-            p_sdt_eram = (DPP_SDTTBL_ERAM_T *)p_sdt_info;
-            p_sdt_eram->table_type = tbl_type;
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_eram->eram_mode,          sdt_hig32, DPP_SDT_H_ERAM_MODE_BT_POS,          DPP_SDT_H_ERAM_MODE_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_eram->eram_base_addr,     sdt_hig32, DPP_SDT_H_ERAM_BASE_ADDR_BT_POS,     DPP_SDT_H_ERAM_BASE_ADDR_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_eram->eram_table_depth,   sdt_low32, DPP_SDT_L_ERAM_TABLE_DEPTH_BT_POS,   DPP_SDT_L_ERAM_TABLE_DEPTH_BT_LEN);
-            p_sdt_eram->eram_clutch_en = clutch_en;
-            break;
-        }
-
-        case DPP_SDT_TBLT_DDR3:
-        {
-            p_sdt_ddr3 = (DPP_SDTTBL_DDR3_T *)p_sdt_info;
-            p_sdt_ddr3->table_type = tbl_type;
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_ddr3->ddr3_base_addr,     sdt_hig32, DPP_SDT_H_DDR3_BASE_ADDR_BT_POS,   DPP_SDT_H_DDR3_BASE_ADDR_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_ddr3->ddr3_share_type,    sdt_hig32, DPP_SDT_H_DDR3_SHARE_TYPE_BT_POS,  DPP_SDT_H_DDR3_SHARE_TYPE_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_ddr3->ddr3_rw_len,        sdt_hig32, DPP_SDT_H_DDR3_RW_LEN_BT_POS,      DPP_SDT_H_DDR3_RW_LEN_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(tmp,                            sdt_hig32, DPP_SDT_H_DDR3_SDT_NUM_BT_POS,     DPP_SDT_H_DDR3_SDT_NUM_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_ddr3->ddr3_sdt_num,       sdt_low32, DPP_SDT_L_DDR3_SDT_NUM_BT_POS,     DPP_SDT_L_DDR3_SDT_NUM_BT_LEN);
-            p_sdt_ddr3->ddr3_sdt_num += (tmp << DPP_SDT_L_DDR3_SDT_NUM_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_ddr3->ddr3_ecc_en,        sdt_low32, DPP_SDT_L_DDR3_ECC_EN_BT_POS,      DPP_SDT_L_DDR3_ECC_EN_BT_LEN);
-            p_sdt_ddr3->ddr3_clutch_en = clutch_en;
-            break;
-        }
-
-        case DPP_SDT_TBLT_HASH:
-        {
-            p_sdt_hash = (DPP_SDTTBL_HASH_T *)p_sdt_info;
-            p_sdt_hash->table_type = tbl_type;
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->hash_id,            sdt_hig32, DPP_SDT_H_HASH_ID_BT_POS,            DPP_SDT_H_HASH_ID_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->hash_table_width,   sdt_hig32, DPP_SDT_H_HASH_TABLE_WIDTH_BT_POS,   DPP_SDT_H_HASH_TABLE_WIDTH_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->key_size,           sdt_hig32, DPP_SDT_H_HASH_KEY_SIZE_BT_POS,      DPP_SDT_H_HASH_KEY_SIZE_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->hash_table_id,      sdt_hig32, DPP_SDT_H_HASH_TABLE_ID_BT_POS,      DPP_SDT_H_HASH_TABLE_ID_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->learn_en,           sdt_hig32, DPP_SDT_H_LEARN_EN_BT_POS,           DPP_SDT_H_LEARN_EN_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->keep_alive,         sdt_hig32, DPP_SDT_H_KEEP_ALIVE_BT_POS,         DPP_SDT_H_KEEP_ALIVE_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(tmp,                            sdt_hig32, DPP_SDT_H_KEEP_ALIVE_BADDR_BT_POS,   DPP_SDT_H_KEEP_ALIVE_BADDR_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->keep_alive_baddr,   sdt_low32, DPP_SDT_L_KEEP_ALIVE_BADDR_BT_POS,   DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN);
-            p_sdt_hash->keep_alive_baddr += (tmp << DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->rsp_mode,           sdt_low32, DPP_SDT_L_RSP_MODE_BT_POS,           DPP_SDT_L_RSP_MODE_BT_LEN);
-            p_sdt_hash->hash_clutch_en = clutch_en;
-            break;
-        }
-
-        case DPP_SDT_TBLT_LPM:
-        {
-            p_sdt_lpm = (DPP_SDTTBL_LPM_T *)p_sdt_info;
-            p_sdt_lpm->table_type = tbl_type;
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_lpm->lpm_v46_id,          sdt_hig32, DPP_SDT_H_LPM_V46ID_BT_POS,         DPP_SDT_H_LPM_V46ID_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_lpm->rsp_mode,            sdt_hig32, DPP_SDT_H_LPM_RSP_MODE_BT_POS,      DPP_SDT_H_LPM_RSP_MODE_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_lpm->lpm_table_depth,     sdt_low32, DPP_SDT_L_LPM_TABLE_DEPTH_BT_POS,   DPP_SDT_L_LPM_TABLE_DEPTH_BT_LEN);
-            p_sdt_lpm->lpm_clutch_en = clutch_en;
-            break;
-        }
-
-        case DPP_SDT_TBLT_eTCAM:
-        {
-            p_sdt_etcam = (DPP_SDTTBL_ETCAM_T *)p_sdt_info;
-            p_sdt_etcam->table_type = tbl_type;
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_id,          sdt_hig32, DPP_SDT_H_ETCAM_ID_BT_POS,              DPP_SDT_H_ETCAM_ID_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_key_mode,    sdt_hig32, DPP_SDT_H_ETCAM_KEY_MODE_BT_POS,        DPP_SDT_H_ETCAM_KEY_MODE_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_table_id,    sdt_hig32, DPP_SDT_H_ETCAM_TABLE_ID_BT_POS,        DPP_SDT_H_ETCAM_TABLE_ID_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->no_as_rsp_mode,    sdt_hig32, DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS,   DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->as_en,             sdt_hig32, DPP_SDT_H_ETCAM_AS_EN_BT_POS,           DPP_SDT_H_ETCAM_AS_EN_BT_LEN);
-
-            ZXIC_COMM_UINT32_GET_BITS(tmp,                            sdt_hig32, DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS,     DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->as_eram_baddr,     sdt_low32, DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS,     DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN);
-            ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(p_sdt_etcam->as_eram_baddr, (tmp << DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN));
-            p_sdt_etcam->as_eram_baddr += (tmp << DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN);
-
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->as_rsp_mode,       sdt_low32, DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_POS,     DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN);
-            ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_table_depth, sdt_low32, DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_POS,     DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN);
-            p_sdt_etcam->etcam_clutch_en = clutch_en;
-            break;
-        }
-
-        case DPP_SDT_TBLT_PORTTBL:
-        {
-            p_sdt_porttbl = (DPP_SDTTBL_PORTTBL_T *)p_sdt_info;
-            p_sdt_porttbl->table_type = tbl_type;
-            p_sdt_porttbl->porttbl_clutch_en = clutch_en;
-            break;
-        }
-
-        default:
-        {
-            ZXIC_COMM_TRACE_ERROR("SDT table_type[ %d ] is invalid!\n", tbl_type);
-            ZXIC_COMM_ASSERT(0);
-            return DPP_ERR;
-        }
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 从软件缓存中获取table data信息
-* @param   dev_id      设备号
-* @param   sdt_no      业务表对应的sdt号,0-255
-* @param   p_sdt_data  sdt表信息
-*
-* @return  
-* @remark  无
-* @see
-* @author  lim      @date  2020/04/16
-************************************************************/
-DPP_STATUS dpp_sdt_tbl_data_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, DPP_SDT_TBL_DATA_T *p_sdt_data)
-{
-    DPP_STATUS rc   = 0;
-
-    ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-
-    p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32;
-    p_sdt_data->data_low32  = g_sdt_info[dev_id][sdt_no].data_low32;
-
-    return rc;
-}
-
-/***********************************************************/
-/** 将sdt信息保存在软件缓存中
-* @param   dev_id      设备号
-* @param   sdt_no      业务表对应的sdt号
-* @param   table_type  SDT属性中的表类型，取值参考DPP_SDT_TABLE_TYPE_E的定义
-* @param   p_sdt_info  写入的SDT表信息。
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lim      @date  2020/04/16
-************************************************************/
-DPP_STATUS dpp_soft_sdt_tbl_set(ZXIC_UINT32 dev_id, 
-                                ZXIC_UINT32 sdt_no, 
-                                ZXIC_UINT32 table_type, 
-                                DPP_SDT_TBL_DATA_T *p_sdt_info)
-{
-    DPP_STATUS rc   = 0;
-
-    ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_POINT(p_sdt_info);
-
-    /* 将table_type存储到软件缓存中 */
-    g_table_type[dev_id][sdt_no] = table_type;
-
-    /* 保存sdt信息 */
-    g_sdt_info[dev_id][sdt_no].data_high32 = p_sdt_info->data_high32;
-    g_sdt_info[dev_id][sdt_no].data_low32  = p_sdt_info->data_low32;
-
-    return rc;
-}
-
-/***********************************************************/
-/** 从软件缓存中获取sdt信息
-* @param   device_id   设备号
-* @param   sdt_no      业务表对应的sdt号
-* @param   p_sdt_info  写入的SDT属性。由table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n
-*                      DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、
-*                      DPP_SDTTBL_ETCAM_T。
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lim      @date  2020/04/16
-************************************************************/
-DPP_STATUS dpp_soft_sdt_tbl_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, ZXIC_VOID *p_sdt_info)
-{
-    DPP_STATUS  rc       = 0;
-
-    DPP_SDT_TBL_DATA_T sdt_tbl = {0};
-
-    ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_POINT(p_sdt_info);
-
-    /** 从软件缓存读取sdt信息 */
-    rc = dpp_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_sdt_tbl_data_get");
-
-    rc = dpp_sdt_tbl_data_parser(dev_id, sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_sdt_tbl_data_parser");
-        
-    return rc;
-}
-
-/***********************************************************/
-/** 写SDT属性表条目到硬件表，同时向8个cluster写入
-* @param   dev_id   设备号
-* @param   sdt_no      业务表对应的sdt号
-* @param   table_type  SDT属性中的表类型，取值参考DPP_SDT_TABLE_TYPE_E的定义(仅添加操作时有效)
-* @param   p_sdt_info  写入的SDT属性(仅添加操作时有效)。由table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n
-*                      DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、\n
-*                      DPP_SDTTBL_ETCAM_T、DPP_SDTTBL_PORTTBL_T。
-* @param   opr_type    操作类型: 0-添加条目，1-删除条目.
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/07/11
-************************************************************/
-DPP_STATUS dpp_sdt_tbl_write(DPP_DEV_T *dev,
-                             ZXIC_UINT32 sdt_no,
-                             ZXIC_UINT32 table_type,
-                             ZXIC_VOID *p_sdt_info,
-                             ZXIC_UINT32 opr_type)
-{
-#ifdef DPP_FLOW_HW_INIT
-    ZXIC_UINT32 i = 0;
-#endif
-    DPP_STATUS rtn = 0;
-    DPP_SDT_TBL_DATA_T sdt_tbl = {0};
-    DPP_SDTTBL_ERAM_T *p_sdt_eram = NULL;
-    DPP_SDTTBL_DDR3_T *p_sdt_ddr3 = NULL;
-    DPP_SDTTBL_HASH_T *p_sdt_hash = NULL;
-    DPP_SDTTBL_LPM_T *p_sdt_lpm = NULL;
-    DPP_SDTTBL_ETCAM_T *p_sdt_etcam = NULL;
-    DPP_SDTTBL_PORTTBL_T *p_sdt_porttbl = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-
-    /* 根据表类型解析数据 */
-    if (opr_type)
-    {
-        /* delete sdt item */
-        rtn = dpp_sdt_mgr_sdt_item_del(DEV_ID(dev), sdt_no);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_sdt_mgr_sdt_item_del");
-    }
-    else
-    {
-        /* add sdt item*/
-        ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_sdt_info);
-        ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), table_type, DPP_SDT_TBLT_eRAM, DPP_SDT_TBLT_PORTTBL);
-
-        switch (table_type)
-        {
-            case DPP_SDT_TBLT_eRAM:
-            {
-                p_sdt_eram = (DPP_SDTTBL_ERAM_T *)p_sdt_info;
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_eram->eram_mode,           DPP_SDT_H_ERAM_MODE_BT_POS,             DPP_SDT_H_ERAM_MODE_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_eram->eram_base_addr,      DPP_SDT_H_ERAM_BASE_ADDR_BT_POS,        DPP_SDT_H_ERAM_BASE_ADDR_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,  p_sdt_eram->eram_table_depth,    DPP_SDT_L_ERAM_TABLE_DEPTH_BT_POS,      DPP_SDT_L_ERAM_TABLE_DEPTH_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,  p_sdt_eram->eram_clutch_en,      DPP_SDT_L_CLUTCH_EN_BT_POS,             DPP_SDT_L_CLUTCH_EN_BT_LEN);
-                break;
-            }
-
-            case DPP_SDT_TBLT_DDR3:
-            {
-                p_sdt_ddr3 = (DPP_SDTTBL_DDR3_T *)p_sdt_info;
-
-                /** 添加操作必须保证sdt号和ddr存储的sdt号一致 */
-                ZXIC_COMM_ASSERT(sdt_no == p_sdt_ddr3->ddr3_sdt_num );
-
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_ddr3->ddr3_base_addr,      DPP_SDT_H_DDR3_BASE_ADDR_BT_POS,        DPP_SDT_H_DDR3_BASE_ADDR_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_ddr3->ddr3_share_type,     DPP_SDT_H_DDR3_SHARE_TYPE_BT_POS,       DPP_SDT_H_DDR3_SHARE_TYPE_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_ddr3->ddr3_rw_len,         DPP_SDT_H_DDR3_RW_LEN_BT_POS,           DPP_SDT_H_DDR3_RW_LEN_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
-                                      ((p_sdt_ddr3->ddr3_sdt_num) >> DPP_SDT_L_DDR3_SDT_NUM_BT_LEN),
-                                      DPP_SDT_H_DDR3_SDT_NUM_BT_POS,
-                                      DPP_SDT_H_DDR3_SDT_NUM_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,
-                                      DPP_SDT_GET_LOW_DATA((p_sdt_ddr3->ddr3_sdt_num),      DPP_SDT_L_DDR3_SDT_NUM_BT_LEN),
-                                      DPP_SDT_L_DDR3_SDT_NUM_BT_POS,
-                                      DPP_SDT_L_DDR3_SDT_NUM_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,  p_sdt_ddr3->ddr3_ecc_en,         DPP_SDT_L_DDR3_ECC_EN_BT_POS,           DPP_SDT_L_DDR3_ECC_EN_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,  p_sdt_ddr3->ddr3_clutch_en,      DPP_SDT_L_CLUTCH_EN_BT_POS,             DPP_SDT_L_CLUTCH_EN_BT_LEN);
-                break;
-            }
-
-            case DPP_SDT_TBLT_HASH:
-            {
-                p_sdt_hash = (DPP_SDTTBL_HASH_T *)p_sdt_info;
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_hash->hash_id,             DPP_SDT_H_HASH_ID_BT_POS,               DPP_SDT_H_HASH_ID_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_hash->hash_table_width,    DPP_SDT_H_HASH_TABLE_WIDTH_BT_POS,      DPP_SDT_H_HASH_TABLE_WIDTH_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_hash->key_size,            DPP_SDT_H_HASH_KEY_SIZE_BT_POS,         DPP_SDT_H_HASH_KEY_SIZE_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_hash->hash_table_id,       DPP_SDT_H_HASH_TABLE_ID_BT_POS,         DPP_SDT_H_HASH_TABLE_ID_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_hash->learn_en,            DPP_SDT_H_LEARN_EN_BT_POS,              DPP_SDT_H_LEARN_EN_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_hash->keep_alive,          DPP_SDT_H_KEEP_ALIVE_BT_POS,            DPP_SDT_H_KEEP_ALIVE_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
-                                      ((p_sdt_hash->keep_alive_baddr) >> DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN),
-                                      DPP_SDT_H_KEEP_ALIVE_BADDR_BT_POS,
-                                      DPP_SDT_H_KEEP_ALIVE_BADDR_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,
-                                      DPP_SDT_GET_LOW_DATA((p_sdt_hash->keep_alive_baddr), DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN),
-                                      DPP_SDT_L_KEEP_ALIVE_BADDR_BT_POS,
-                                      DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,   p_sdt_hash->rsp_mode,           DPP_SDT_L_RSP_MODE_BT_POS,              DPP_SDT_L_RSP_MODE_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,  p_sdt_hash->hash_clutch_en,      DPP_SDT_L_CLUTCH_EN_BT_POS,             DPP_SDT_L_CLUTCH_EN_BT_LEN);
-                break;
-            }
-
-            case DPP_SDT_TBLT_LPM:
-            {
-                p_sdt_lpm = (DPP_SDTTBL_LPM_T *)p_sdt_info;
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_lpm->lpm_v46_id,           DPP_SDT_H_LPM_V46ID_BT_POS,             DPP_SDT_H_LPM_V46ID_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_lpm->rsp_mode,             DPP_SDT_H_LPM_RSP_MODE_BT_POS,          DPP_SDT_H_LPM_RSP_MODE_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,  p_sdt_lpm->lpm_table_depth,      DPP_SDT_L_LPM_TABLE_DEPTH_BT_POS,       DPP_SDT_L_LPM_TABLE_DEPTH_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,  p_sdt_lpm->lpm_clutch_en,        DPP_SDT_L_CLUTCH_EN_BT_POS,             DPP_SDT_L_CLUTCH_EN_BT_LEN);
-                break;
-            }
-
-            case DPP_SDT_TBLT_eTCAM:
-            {
-                p_sdt_etcam = (DPP_SDTTBL_ETCAM_T *)p_sdt_info;
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_etcam->etcam_id,           DPP_SDT_H_ETCAM_ID_BT_POS,              DPP_SDT_H_ETCAM_ID_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_etcam->etcam_key_mode,     DPP_SDT_H_ETCAM_KEY_MODE_BT_POS,        DPP_SDT_H_ETCAM_KEY_MODE_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_etcam->etcam_table_id,     DPP_SDT_H_ETCAM_TABLE_ID_BT_POS,        DPP_SDT_H_ETCAM_TABLE_ID_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_etcam->no_as_rsp_mode,     DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS,   DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_etcam->as_en,              DPP_SDT_H_ETCAM_AS_EN_BT_POS,           DPP_SDT_H_ETCAM_AS_EN_BT_LEN);
-
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
-                                      ((p_sdt_etcam->as_eram_baddr) >> DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN),
-                                      DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS,
-                                      DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,
-                                      DPP_SDT_GET_LOW_DATA((p_sdt_etcam->as_eram_baddr), DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN),
-                                      DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS,
-                                      DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN);
-
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_etcam->as_rsp_mode,         DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_POS,     DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,  p_sdt_etcam->etcam_table_depth,  DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_POS,     DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN);
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,  p_sdt_etcam->etcam_clutch_en,    DPP_SDT_L_CLUTCH_EN_BT_POS,             DPP_SDT_L_CLUTCH_EN_BT_LEN);
-                break;
-            }
-
-            case DPP_SDT_TBLT_PORTTBL:
-            {
-                p_sdt_porttbl = (DPP_SDTTBL_PORTTBL_T *)p_sdt_info;
-                ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,  p_sdt_porttbl->porttbl_clutch_en, DPP_SDT_L_CLUTCH_EN_BT_POS,             DPP_SDT_L_CLUTCH_EN_BT_LEN);
-                break;
-            }
-
-            default:
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "SDT table_type[ %d ] is invalid!\n", table_type);
-                return DPP_ERR;
-            }
-        }
-
-        ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, table_type, DPP_SDT_H_TBL_TYPE_BT_POS, DPP_SDT_H_TBL_TYPE_BT_LEN);
-
-        /* 将sdt信息存储到软件缓存中 */
-        dpp_soft_sdt_tbl_set(DEV_ID(dev), sdt_no, table_type, &sdt_tbl);
-
-        /* 缓存到软件 */
-        rtn = dpp_sdt_mgr_sdt_item_add(DEV_ID(dev), sdt_no, sdt_tbl.data_high32, sdt_tbl.data_low32);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_sdt_mgr_sdt_item_add");
-    }
-#ifdef DPP_FLOW_HW_INIT
-    for (i = 0; i < DPP_PPU_CLUSTER_NUM; i++)
-    {
-        /*cluster 未启用,不需要配置该cluster相关的寄存器*/
-        if (!dpp_ppu_cls_use_get(DEV_ID(dev), i))
-        {
-            continue;
-        }
-
-        rtn = dpp_ppu_sdt_tbl_write(dev, i, sdt_no, &sdt_tbl);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_ppu_sdt_tbl_write");
-    }
-#endif
-    return DPP_OK;
-}
-
-#endif
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_sdt.c
+* 文件标识 : sdt配置接口实现文件
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2015/06/25
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#include "zxic_common.h"
+
+#include "dpp_dev.h"
+#include "dpp_se.h"
+#include "dpp_sdt_def.h"
+#include "dpp_sdt_mgr.h"
+#include "dpp_sdt.h"
+
+/* 全局变量*/
+ZXIC_UINT32 g_table_type[DPP_DEV_CHANNEL_MAX][DPP_DEV_SDT_ID_MAX] = { { 0 } };
+DPP_SDT_TBL_DATA_T g_sdt_info[DPP_DEV_CHANNEL_MAX][DPP_DEV_SDT_ID_MAX] = {
+	{ { 0 } }
+};
+
+/** 获取低n位数据 */
+#define DPP_SDT_GET_LOW_DATA(source_value, low_width) \
+	(source_value & ((1 << low_width) - 1))
+
+#if ZXIC_REAL("function for FCM_FTM ")
+/***********************************************************/
+/** 初始化SDT表配置管理
+ * @param   dev_num       设备数目
+ * @param   dev_id_array  设备dev_id数组
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/07/13
+ ************************************************************/
+DPP_STATUS dpp_sdt_init(ZXIC_UINT32 dev_num, ZXIC_UINT32 *dev_id_array)
+{
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 i = 0;
+
+	ZXIC_COMM_CHECK_INDEX(dev_num, 1, DPP_DEV_CHANNEL_MAX);
+	ZXIC_COMM_CHECK_POINT(dev_id_array);
+
+	for (i = 0; i < dev_num; i++) {
+		ZXIC_COMM_CHECK_INDEX(*(dev_id_array + i), 0, DPP_DEV_CHANNEL_MAX - 1);
+	}
+
+	dpp_sdt_mgr_init();
+
+	for (i = 0; i < dev_num; i++) {
+		rc = dpp_sdt_mgr_create(dev_id_array[i]);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_sdt_mgr_create");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 解析从硬件读取的64bit SDT属性
+ * @param   sdt_hig32   硬件表中存储的SDT属性高32bit
+ * @param   sdt_low32   硬件表中存储的SDT属性低32bit
+ * @param   p_sdt_info  解析之后的SDT属性，根据SDT属性中的table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n
+ *                      DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR3_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、\n
+ *                      DPP_SDTTBL_ETCAM_T、DPP_SDTTBL_PORTTBL_T。
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/07/13
+ ************************************************************/
+DPP_STATUS dpp_sdt_tbl_data_parser(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_hig32,
+								   ZXIC_UINT32 sdt_low32, ZXIC_VOID *p_sdt_info)
+{
+	ZXIC_UINT32 tmp = 0;
+	ZXIC_UINT32 tbl_type = 0;
+	ZXIC_UINT32 clutch_en = 0;
+
+	DPP_SDTTBL_ERAM_T *p_sdt_eram = NULL;
+	DPP_SDTTBL_DDR3_T *p_sdt_ddr3 = NULL;
+	DPP_SDTTBL_HASH_T *p_sdt_hash = NULL;
+	DPP_SDTTBL_LPM_T *p_sdt_lpm = NULL;
+	DPP_SDTTBL_ETCAM_T *p_sdt_etcam = NULL;
+	DPP_SDTTBL_PORTTBL_T *p_sdt_porttbl = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_sdt_info);
+
+	ZXIC_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32, DPP_SDT_H_TBL_TYPE_BT_POS,
+							  DPP_SDT_H_TBL_TYPE_BT_LEN);
+	ZXIC_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, DPP_SDT_L_CLUTCH_EN_BT_POS,
+							  DPP_SDT_L_CLUTCH_EN_BT_LEN);
+
+	/* 根据表类型解析数据 */
+	switch (tbl_type) {
+	case DPP_SDT_TBLT_eRAM: {
+		p_sdt_eram = (DPP_SDTTBL_ERAM_T *)p_sdt_info;
+		p_sdt_eram->table_type = tbl_type;
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_eram->eram_mode, sdt_hig32,
+								  DPP_SDT_H_ERAM_MODE_BT_POS,
+								  DPP_SDT_H_ERAM_MODE_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_eram->eram_base_addr, sdt_hig32,
+								  DPP_SDT_H_ERAM_BASE_ADDR_BT_POS,
+								  DPP_SDT_H_ERAM_BASE_ADDR_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_eram->eram_table_depth, sdt_low32,
+								  DPP_SDT_L_ERAM_TABLE_DEPTH_BT_POS,
+								  DPP_SDT_L_ERAM_TABLE_DEPTH_BT_LEN);
+		p_sdt_eram->eram_clutch_en = clutch_en;
+		break;
+	}
+
+	case DPP_SDT_TBLT_DDR3: {
+		p_sdt_ddr3 = (DPP_SDTTBL_DDR3_T *)p_sdt_info;
+		p_sdt_ddr3->table_type = tbl_type;
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_ddr3->ddr3_base_addr, sdt_hig32,
+								  DPP_SDT_H_DDR3_BASE_ADDR_BT_POS,
+								  DPP_SDT_H_DDR3_BASE_ADDR_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_ddr3->ddr3_share_type, sdt_hig32,
+								  DPP_SDT_H_DDR3_SHARE_TYPE_BT_POS,
+								  DPP_SDT_H_DDR3_SHARE_TYPE_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_ddr3->ddr3_rw_len, sdt_hig32,
+								  DPP_SDT_H_DDR3_RW_LEN_BT_POS,
+								  DPP_SDT_H_DDR3_RW_LEN_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(tmp, sdt_hig32, DPP_SDT_H_DDR3_SDT_NUM_BT_POS,
+								  DPP_SDT_H_DDR3_SDT_NUM_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_ddr3->ddr3_sdt_num, sdt_low32,
+								  DPP_SDT_L_DDR3_SDT_NUM_BT_POS,
+								  DPP_SDT_L_DDR3_SDT_NUM_BT_LEN);
+		p_sdt_ddr3->ddr3_sdt_num += (tmp << DPP_SDT_L_DDR3_SDT_NUM_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_ddr3->ddr3_ecc_en, sdt_low32,
+								  DPP_SDT_L_DDR3_ECC_EN_BT_POS,
+								  DPP_SDT_L_DDR3_ECC_EN_BT_LEN);
+		p_sdt_ddr3->ddr3_clutch_en = clutch_en;
+		break;
+	}
+
+	case DPP_SDT_TBLT_HASH: {
+		p_sdt_hash = (DPP_SDTTBL_HASH_T *)p_sdt_info;
+		p_sdt_hash->table_type = tbl_type;
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->hash_id, sdt_hig32,
+								  DPP_SDT_H_HASH_ID_BT_POS,
+								  DPP_SDT_H_HASH_ID_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->hash_table_width, sdt_hig32,
+								  DPP_SDT_H_HASH_TABLE_WIDTH_BT_POS,
+								  DPP_SDT_H_HASH_TABLE_WIDTH_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->key_size, sdt_hig32,
+								  DPP_SDT_H_HASH_KEY_SIZE_BT_POS,
+								  DPP_SDT_H_HASH_KEY_SIZE_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->hash_table_id, sdt_hig32,
+								  DPP_SDT_H_HASH_TABLE_ID_BT_POS,
+								  DPP_SDT_H_HASH_TABLE_ID_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->learn_en, sdt_hig32,
+								  DPP_SDT_H_LEARN_EN_BT_POS,
+								  DPP_SDT_H_LEARN_EN_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->keep_alive, sdt_hig32,
+								  DPP_SDT_H_KEEP_ALIVE_BT_POS,
+								  DPP_SDT_H_KEEP_ALIVE_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(tmp, sdt_hig32,
+								  DPP_SDT_H_KEEP_ALIVE_BADDR_BT_POS,
+								  DPP_SDT_H_KEEP_ALIVE_BADDR_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->keep_alive_baddr, sdt_low32,
+								  DPP_SDT_L_KEEP_ALIVE_BADDR_BT_POS,
+								  DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN);
+		p_sdt_hash->keep_alive_baddr +=
+				(tmp << DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_hash->rsp_mode, sdt_low32,
+								  DPP_SDT_L_RSP_MODE_BT_POS,
+								  DPP_SDT_L_RSP_MODE_BT_LEN);
+		p_sdt_hash->hash_clutch_en = clutch_en;
+		break;
+	}
+
+	case DPP_SDT_TBLT_LPM: {
+		p_sdt_lpm = (DPP_SDTTBL_LPM_T *)p_sdt_info;
+		p_sdt_lpm->table_type = tbl_type;
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_lpm->lpm_v46_id, sdt_hig32,
+								  DPP_SDT_H_LPM_V46ID_BT_POS,
+								  DPP_SDT_H_LPM_V46ID_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_lpm->rsp_mode, sdt_hig32,
+								  DPP_SDT_H_LPM_RSP_MODE_BT_POS,
+								  DPP_SDT_H_LPM_RSP_MODE_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_lpm->lpm_table_depth, sdt_low32,
+								  DPP_SDT_L_LPM_TABLE_DEPTH_BT_POS,
+								  DPP_SDT_L_LPM_TABLE_DEPTH_BT_LEN);
+		p_sdt_lpm->lpm_clutch_en = clutch_en;
+		break;
+	}
+
+	case DPP_SDT_TBLT_eTCAM: {
+		p_sdt_etcam = (DPP_SDTTBL_ETCAM_T *)p_sdt_info;
+		p_sdt_etcam->table_type = tbl_type;
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_id, sdt_hig32,
+								  DPP_SDT_H_ETCAM_ID_BT_POS,
+								  DPP_SDT_H_ETCAM_ID_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_key_mode, sdt_hig32,
+								  DPP_SDT_H_ETCAM_KEY_MODE_BT_POS,
+								  DPP_SDT_H_ETCAM_KEY_MODE_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_table_id, sdt_hig32,
+								  DPP_SDT_H_ETCAM_TABLE_ID_BT_POS,
+								  DPP_SDT_H_ETCAM_TABLE_ID_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->no_as_rsp_mode, sdt_hig32,
+								  DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS,
+								  DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->as_en, sdt_hig32,
+								  DPP_SDT_H_ETCAM_AS_EN_BT_POS,
+								  DPP_SDT_H_ETCAM_AS_EN_BT_LEN);
+
+		ZXIC_COMM_UINT32_GET_BITS(tmp, sdt_hig32,
+								  DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS,
+								  DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->as_eram_baddr, sdt_low32,
+								  DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS,
+								  DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN);
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(
+				p_sdt_etcam->as_eram_baddr,
+				(tmp << DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN));
+		p_sdt_etcam->as_eram_baddr +=
+				(tmp << DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN);
+
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->as_rsp_mode, sdt_low32,
+								  DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_POS,
+								  DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN);
+		ZXIC_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_table_depth, sdt_low32,
+								  DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_POS,
+								  DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN);
+		p_sdt_etcam->etcam_clutch_en = clutch_en;
+		break;
+	}
+
+	case DPP_SDT_TBLT_PORTTBL: {
+		p_sdt_porttbl = (DPP_SDTTBL_PORTTBL_T *)p_sdt_info;
+		p_sdt_porttbl->table_type = tbl_type;
+		p_sdt_porttbl->porttbl_clutch_en = clutch_en;
+		break;
+	}
+
+	default: {
+		ZXIC_COMM_TRACE_ERROR("SDT table_type[ %d ] is invalid!\n", tbl_type);
+		ZXIC_COMM_ASSERT(0);
+		return DPP_ERR;
+	}
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 从软件缓存中获取table data信息
+ * @param   dev_id      设备号
+ * @param   sdt_no      业务表对应的sdt号,0-255
+ * @param   p_sdt_data  sdt表信息
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  lim      @date  2020/04/16
+ ************************************************************/
+DPP_STATUS dpp_sdt_tbl_data_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no,
+								DPP_SDT_TBL_DATA_T *p_sdt_data)
+{
+	DPP_STATUS rc = 0;
+
+	ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+
+	p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32;
+	p_sdt_data->data_low32 = g_sdt_info[dev_id][sdt_no].data_low32;
+
+	return rc;
+}
+
+/***********************************************************/
+/** 将sdt信息保存在软件缓存中
+ * @param   dev_id      设备号
+ * @param   sdt_no      业务表对应的sdt号
+ * @param   table_type  SDT属性中的表类型，取值参考DPP_SDT_TABLE_TYPE_E的定义
+ * @param   p_sdt_info  写入的SDT表信息。
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  lim      @date  2020/04/16
+ ************************************************************/
+DPP_STATUS dpp_soft_sdt_tbl_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no,
+								ZXIC_UINT32 table_type,
+								DPP_SDT_TBL_DATA_T *p_sdt_info)
+{
+	DPP_STATUS rc = 0;
+
+	ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(p_sdt_info);
+
+	/* 将table_type存储到软件缓存中 */
+	g_table_type[dev_id][sdt_no] = table_type;
+
+	/* 保存sdt信息 */
+	g_sdt_info[dev_id][sdt_no].data_high32 = p_sdt_info->data_high32;
+	g_sdt_info[dev_id][sdt_no].data_low32 = p_sdt_info->data_low32;
+
+	return rc;
+}
+
+/***********************************************************/
+/** 从软件缓存中获取sdt信息
+ * @param   device_id   设备号
+ * @param   sdt_no      业务表对应的sdt号
+ * @param   p_sdt_info  写入的SDT属性。由table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n
+ *                      DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、
+ *                      DPP_SDTTBL_ETCAM_T。
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  lim      @date  2020/04/16
+ ************************************************************/
+DPP_STATUS dpp_soft_sdt_tbl_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no,
+								ZXIC_VOID *p_sdt_info)
+{
+	DPP_STATUS rc = 0;
+
+	DPP_SDT_TBL_DATA_T sdt_tbl = { 0 };
+
+	ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(p_sdt_info);
+
+	/** 从软件缓存读取sdt信息 */
+	rc = dpp_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_sdt_tbl_data_get");
+
+	rc = dpp_sdt_tbl_data_parser(dev_id, sdt_tbl.data_high32,
+								 sdt_tbl.data_low32, p_sdt_info);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_sdt_tbl_data_parser");
+
+	return rc;
+}
+
+/***********************************************************/
+/** 写SDT属性表条目到硬件表，同时向8个cluster写入
+ * @param   dev_id   设备号
+ * @param   sdt_no      业务表对应的sdt号
+ * @param   table_type  SDT属性中的表类型，取值参考DPP_SDT_TABLE_TYPE_E的定义(仅添加操作时有效)
+ * @param   p_sdt_info  写入的SDT属性(仅添加操作时有效)。由table_type确定此ZXIC_VOID型指针对应的数据结构, 包括: \n
+ *                      DPP_SDTTBL_ERAM_T、DPP_SDTTBL_DDR_T、DPP_SDTTBL_HASH_T、DPP_SDTTBL_LPM_T、\n
+ *                      DPP_SDTTBL_ETCAM_T、DPP_SDTTBL_PORTTBL_T。
+ * @param   opr_type    操作类型: 0-添加条目，1-删除条目.
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/07/11
+ ************************************************************/
+DPP_STATUS dpp_sdt_tbl_write(DPP_DEV_T *dev, ZXIC_UINT32 sdt_no,
+							 ZXIC_UINT32 table_type, ZXIC_VOID *p_sdt_info,
+							 ZXIC_UINT32 opr_type)
+{
+#ifdef DPP_FLOW_HW_INIT
+	ZXIC_UINT32 i = 0;
+#endif
+	DPP_STATUS rtn = 0;
+	DPP_SDT_TBL_DATA_T sdt_tbl = { 0 };
+	DPP_SDTTBL_ERAM_T *p_sdt_eram = NULL;
+	DPP_SDTTBL_DDR3_T *p_sdt_ddr3 = NULL;
+	DPP_SDTTBL_HASH_T *p_sdt_hash = NULL;
+	DPP_SDTTBL_LPM_T *p_sdt_lpm = NULL;
+	DPP_SDTTBL_ETCAM_T *p_sdt_etcam = NULL;
+	DPP_SDTTBL_PORTTBL_T *p_sdt_porttbl = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+
+	/* 根据表类型解析数据 */
+	if (opr_type) {
+		/* delete sdt item */
+		rtn = dpp_sdt_mgr_sdt_item_del(DEV_ID(dev), sdt_no);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_sdt_mgr_sdt_item_del");
+	} else {
+		/* add sdt item*/
+		ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_sdt_info);
+		ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), table_type, DPP_SDT_TBLT_eRAM,
+								  DPP_SDT_TBLT_PORTTBL);
+
+		switch (table_type) {
+		case DPP_SDT_TBLT_eRAM: {
+			p_sdt_eram = (DPP_SDTTBL_ERAM_T *)p_sdt_info;
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_eram->eram_mode,
+										DPP_SDT_H_ERAM_MODE_BT_POS,
+										DPP_SDT_H_ERAM_MODE_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_eram->eram_base_addr,
+										DPP_SDT_H_ERAM_BASE_ADDR_BT_POS,
+										DPP_SDT_H_ERAM_BASE_ADDR_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,
+										p_sdt_eram->eram_table_depth,
+										DPP_SDT_L_ERAM_TABLE_DEPTH_BT_POS,
+										DPP_SDT_L_ERAM_TABLE_DEPTH_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,
+										p_sdt_eram->eram_clutch_en,
+										DPP_SDT_L_CLUTCH_EN_BT_POS,
+										DPP_SDT_L_CLUTCH_EN_BT_LEN);
+			break;
+		}
+
+		case DPP_SDT_TBLT_DDR3: {
+			p_sdt_ddr3 = (DPP_SDTTBL_DDR3_T *)p_sdt_info;
+
+			/** 添加操作必须保证sdt号和ddr存储的sdt号一致 */
+			ZXIC_COMM_ASSERT(sdt_no == p_sdt_ddr3->ddr3_sdt_num);
+
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_ddr3->ddr3_base_addr,
+										DPP_SDT_H_DDR3_BASE_ADDR_BT_POS,
+										DPP_SDT_H_DDR3_BASE_ADDR_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_ddr3->ddr3_share_type,
+										DPP_SDT_H_DDR3_SHARE_TYPE_BT_POS,
+										DPP_SDT_H_DDR3_SHARE_TYPE_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_ddr3->ddr3_rw_len,
+										DPP_SDT_H_DDR3_RW_LEN_BT_POS,
+										DPP_SDT_H_DDR3_RW_LEN_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										((p_sdt_ddr3->ddr3_sdt_num) >>
+										 DPP_SDT_L_DDR3_SDT_NUM_BT_LEN),
+										DPP_SDT_H_DDR3_SDT_NUM_BT_POS,
+										DPP_SDT_H_DDR3_SDT_NUM_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(
+					sdt_tbl.data_low32,
+					DPP_SDT_GET_LOW_DATA((p_sdt_ddr3->ddr3_sdt_num),
+										 DPP_SDT_L_DDR3_SDT_NUM_BT_LEN),
+					DPP_SDT_L_DDR3_SDT_NUM_BT_POS,
+					DPP_SDT_L_DDR3_SDT_NUM_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,
+										p_sdt_ddr3->ddr3_ecc_en,
+										DPP_SDT_L_DDR3_ECC_EN_BT_POS,
+										DPP_SDT_L_DDR3_ECC_EN_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,
+										p_sdt_ddr3->ddr3_clutch_en,
+										DPP_SDT_L_CLUTCH_EN_BT_POS,
+										DPP_SDT_L_CLUTCH_EN_BT_LEN);
+			break;
+		}
+
+		case DPP_SDT_TBLT_HASH: {
+			p_sdt_hash = (DPP_SDTTBL_HASH_T *)p_sdt_info;
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_hash->hash_id,
+										DPP_SDT_H_HASH_ID_BT_POS,
+										DPP_SDT_H_HASH_ID_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_hash->hash_table_width,
+										DPP_SDT_H_HASH_TABLE_WIDTH_BT_POS,
+										DPP_SDT_H_HASH_TABLE_WIDTH_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_hash->key_size,
+										DPP_SDT_H_HASH_KEY_SIZE_BT_POS,
+										DPP_SDT_H_HASH_KEY_SIZE_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_hash->hash_table_id,
+										DPP_SDT_H_HASH_TABLE_ID_BT_POS,
+										DPP_SDT_H_HASH_TABLE_ID_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_hash->learn_en,
+										DPP_SDT_H_LEARN_EN_BT_POS,
+										DPP_SDT_H_LEARN_EN_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_hash->keep_alive,
+										DPP_SDT_H_KEEP_ALIVE_BT_POS,
+										DPP_SDT_H_KEEP_ALIVE_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										((p_sdt_hash->keep_alive_baddr) >>
+										 DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN),
+										DPP_SDT_H_KEEP_ALIVE_BADDR_BT_POS,
+										DPP_SDT_H_KEEP_ALIVE_BADDR_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(
+					sdt_tbl.data_low32,
+					DPP_SDT_GET_LOW_DATA((p_sdt_hash->keep_alive_baddr),
+										 DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN),
+					DPP_SDT_L_KEEP_ALIVE_BADDR_BT_POS,
+					DPP_SDT_L_KEEP_ALIVE_BADDR_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,
+										p_sdt_hash->rsp_mode,
+										DPP_SDT_L_RSP_MODE_BT_POS,
+										DPP_SDT_L_RSP_MODE_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,
+										p_sdt_hash->hash_clutch_en,
+										DPP_SDT_L_CLUTCH_EN_BT_POS,
+										DPP_SDT_L_CLUTCH_EN_BT_LEN);
+			break;
+		}
+
+		case DPP_SDT_TBLT_LPM: {
+			p_sdt_lpm = (DPP_SDTTBL_LPM_T *)p_sdt_info;
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_lpm->lpm_v46_id,
+										DPP_SDT_H_LPM_V46ID_BT_POS,
+										DPP_SDT_H_LPM_V46ID_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_lpm->rsp_mode,
+										DPP_SDT_H_LPM_RSP_MODE_BT_POS,
+										DPP_SDT_H_LPM_RSP_MODE_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,
+										p_sdt_lpm->lpm_table_depth,
+										DPP_SDT_L_LPM_TABLE_DEPTH_BT_POS,
+										DPP_SDT_L_LPM_TABLE_DEPTH_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,
+										p_sdt_lpm->lpm_clutch_en,
+										DPP_SDT_L_CLUTCH_EN_BT_POS,
+										DPP_SDT_L_CLUTCH_EN_BT_LEN);
+			break;
+		}
+
+		case DPP_SDT_TBLT_eTCAM: {
+			p_sdt_etcam = (DPP_SDTTBL_ETCAM_T *)p_sdt_info;
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_etcam->etcam_id,
+										DPP_SDT_H_ETCAM_ID_BT_POS,
+										DPP_SDT_H_ETCAM_ID_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_etcam->etcam_key_mode,
+										DPP_SDT_H_ETCAM_KEY_MODE_BT_POS,
+										DPP_SDT_H_ETCAM_KEY_MODE_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_etcam->etcam_table_id,
+										DPP_SDT_H_ETCAM_TABLE_ID_BT_POS,
+										DPP_SDT_H_ETCAM_TABLE_ID_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										p_sdt_etcam->no_as_rsp_mode,
+										DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS,
+										DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, p_sdt_etcam->as_en,
+										DPP_SDT_H_ETCAM_AS_EN_BT_POS,
+										DPP_SDT_H_ETCAM_AS_EN_BT_LEN);
+
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32,
+										((p_sdt_etcam->as_eram_baddr) >>
+										 DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN),
+										DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS,
+										DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(
+					sdt_tbl.data_low32,
+					DPP_SDT_GET_LOW_DATA((p_sdt_etcam->as_eram_baddr),
+										 DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN),
+					DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS,
+					DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN);
+
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,
+										p_sdt_etcam->as_rsp_mode,
+										DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_POS,
+										DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,
+										p_sdt_etcam->etcam_table_depth,
+										DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_POS,
+										DPP_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN);
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,
+										p_sdt_etcam->etcam_clutch_en,
+										DPP_SDT_L_CLUTCH_EN_BT_POS,
+										DPP_SDT_L_CLUTCH_EN_BT_LEN);
+			break;
+		}
+
+		case DPP_SDT_TBLT_PORTTBL: {
+			p_sdt_porttbl = (DPP_SDTTBL_PORTTBL_T *)p_sdt_info;
+			ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32,
+										p_sdt_porttbl->porttbl_clutch_en,
+										DPP_SDT_L_CLUTCH_EN_BT_POS,
+										DPP_SDT_L_CLUTCH_EN_BT_LEN);
+			break;
+		}
+
+		default: {
+			ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+									  "SDT table_type[ %d ] is invalid!\n",
+									  table_type);
+			return DPP_ERR;
+		}
+		}
+
+		ZXIC_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, table_type,
+									DPP_SDT_H_TBL_TYPE_BT_POS,
+									DPP_SDT_H_TBL_TYPE_BT_LEN);
+
+		/* 将sdt信息存储到软件缓存中 */
+		dpp_soft_sdt_tbl_set(DEV_ID(dev), sdt_no, table_type, &sdt_tbl);
+
+		/* 缓存到软件 */
+		rtn = dpp_sdt_mgr_sdt_item_add(DEV_ID(dev), sdt_no, sdt_tbl.data_high32,
+									   sdt_tbl.data_low32);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_sdt_mgr_sdt_item_add");
+	}
+#ifdef DPP_FLOW_HW_INIT
+	for (i = 0; i < DPP_PPU_CLUSTER_NUM; i++) {
+		/*cluster 未启用,不需要配置该cluster相关的寄存器*/
+		if (!dpp_ppu_cls_use_get(DEV_ID(dev), i)) {
+			continue;
+		}
+
+		rtn = dpp_ppu_sdt_tbl_write(dev, i, sdt_no, &sdt_tbl);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_ppu_sdt_tbl_write");
+	}
+#endif
+	return DPP_OK;
+}
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/dpp_sdt_mgr.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/dpp_sdt_mgr.c
old mode 100755
new mode 100644
index 1fb381c78f93579ce5f198508baa661ea78c9e50..823177d8eb53d27ece5748bf5635506d03d0361c
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/dpp_sdt_mgr.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/sdt/dpp_sdt_mgr.c
@@ -1,739 +1,805 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_sdt_mgr.c
-* 文件标识 :
-* 内容摘要 : SDT属性软件缓存，以及接收上层配置并下发给底层设备
-* 其它说明 :
-* 当前版本 :
-* 作    者 : 王春雷
-* 完成日期 : 2015/06/25
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-
-#include "zxic_common.h"
-
-#include "dpp_dev.h"
-#include "dpp_sdt_def.h"
-#include "dpp_sdt.h"
-#include "dpp_sdt_mgr.h"
-#include "dpp_se_api.h"
-
-static DPP_SDT_MGR_T g_sdt_mgr = {0};
-
-static ZXIC_UINT32 g_sdt_mgr_debug = 1;
-
-#define DPP_SDT_MGR_PTR_GET()    (&g_sdt_mgr)
-
-#define DPP_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id])
-
-ZXIC_UINT32 dpp_sdt_mgr_init(ZXIC_VOID)
-{
-    if (!g_sdt_mgr.is_init)
-    {
-        g_sdt_mgr.channel_num = 0;
-        g_sdt_mgr.is_init = 1;
-        // g_sdt_mgr.p_sdt_mgr_smmu0_mux = dpp_tbl_dir_sdt_smmu0_mux;
-        // g_sdt_mgr.p_sdt_mgr_smmu1_mux = dpp_tbl_dir_sdt_smmu1_mux;
-        // g_sdt_mgr.p_sdt_mgr_hash_mux = dpp_tbl_dir_sdt_hash_mux;
-        // g_sdt_mgr.p_sdt_mgr_lpm_mux = dpp_tbl_dir_sdt_lpm_mux;
-        // g_sdt_mgr.p_sdt_mgr_etcam_mux = dpp_tbl_dir_sdt_etcam_mux;
-        ZXIC_COMM_MEMSET(g_sdt_mgr.sdt_tbl_array, 0, DPP_DEV_CHANNEL_MAX * sizeof(DPP_SDT_SOFT_TABLE_T *));
-    }
-
-    return DPP_OK;
-}
-
-ZXIC_UINT32 dpp_sdt_mgr_create(ZXIC_UINT32 dev_id)
-{
-    DPP_SDT_SOFT_TABLE_T *p_sdt_tbl_temp = NULL;
-    DPP_SDT_MGR_T *p_sdt_mgr = NULL;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-
-    p_sdt_mgr = DPP_SDT_MGR_PTR_GET();
-
-    if (DPP_SDT_SOFT_TBL_GET(dev_id) == NULL)
-    {
-        p_sdt_tbl_temp = ZXIC_COMM_MALLOC(sizeof(DPP_SDT_SOFT_TABLE_T));
-        ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_sdt_tbl_temp);      /* mod for KW_0411 # 474 */
-
-        p_sdt_tbl_temp->device_id = dev_id;
-        ZXIC_COMM_MEMSET(p_sdt_tbl_temp->sdt_array, 0, DPP_DEV_SDT_ID_MAX * sizeof(DPP_SDT_ITEM_T));
-
-        DPP_SDT_SOFT_TBL_GET(dev_id) = p_sdt_tbl_temp;
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, p_sdt_mgr->channel_num, 1);
-        p_sdt_mgr->channel_num++;
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error: dpp_sdt_mgr_create for dev[%d] is called repeatedly!\n", dev_id);
-    }
-
-    return DPP_OK;
-}
-
-ZXIC_UINT32 dpp_sdt_mgr_destroy(ZXIC_UINT32 dev_id)
-{
-    DPP_SDT_SOFT_TABLE_T *p_sdt_tbl_temp = NULL;
-    DPP_SDT_MGR_T *p_sdt_mgr = NULL;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-
-    p_sdt_tbl_temp = DPP_SDT_SOFT_TBL_GET(dev_id);
-    p_sdt_mgr = DPP_SDT_MGR_PTR_GET();
-
-    if (NULL != p_sdt_tbl_temp)
-    {
-        ZXIC_COMM_FREE(p_sdt_tbl_temp);
-    }
-
-    DPP_SDT_SOFT_TBL_GET(dev_id) = NULL;
-
-    ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, p_sdt_mgr->channel_num, 1);
-    p_sdt_mgr->channel_num--;
-
-    return DPP_OK;
-}
-
-
-#if 1
-/***********************************************************/
-/** 向软件缓存中添加SDT表条目
-* @param   dev_id  设备号
-* @param   sdt_no     业务表对应的sdt号
-* @param   sdt_hig32  SDT属性高32bit
-* @param   sdt_low32  SDT属性低32bit
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/07/13
-************************************************************/
-DPP_STATUS dpp_sdt_mgr_sdt_item_add(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, ZXIC_UINT32 sdt_hig32, ZXIC_UINT32 sdt_low32)
-{
-    DPP_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL;
-    DPP_SDT_ITEM_T *p_sdt_item = NULL;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no,    0, DPP_DEV_SDT_ID_MAX - 1);
-
-    p_sdt_soft_tbl = DPP_SDT_SOFT_TBL_GET(dev_id);
-
-    if (NULL == p_sdt_soft_tbl)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error: dpp_sdt_mgr_sdt_item_add soft sdt table not Init! \n");
-        ZXIC_COMM_ASSERT(0);
-        return DPP_RC_TABLE_SDT_MGR_INVALID;
-    }
-
-    if (dev_id != p_sdt_soft_tbl->device_id)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error: dpp_sdt_mgr_sdt_item_add soft sdt table Item Invalid! \n");
-        ZXIC_COMM_ASSERT(0);
-        return DPP_RC_TABLE_PARA_INVALID;
-    }
-
-    /*添加SDT表项*/
-    p_sdt_item = &(p_sdt_soft_tbl->sdt_array[sdt_no]);
-    p_sdt_item->valid = DPP_SDT_VALID;
-    p_sdt_item->table_cfg[0] = sdt_hig32; /* hig32 */
-    p_sdt_item->table_cfg[1] = sdt_low32; /* low32 */
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "dpp_sdt_mgr_sdt_item_add 0x%08x 0x%08x \n", p_sdt_item->table_cfg[0], p_sdt_item->table_cfg[1]);
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 从软件缓存中读取SDT表条目
-* @param   dev_id    设备号
-* @param   sdt_no       业务表对应的sdt号
-* @param   p_sdt_hig32  SDT属性高32bit
-* @param   p_sdt_low32  SDT属性低32bit
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/07/13
-************************************************************/
-DPP_STATUS dpp_sdt_mgr_sdt_item_srh(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, ZXIC_UINT32 *p_sdt_hig32, ZXIC_UINT32 *p_sdt_low32)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL;
-    DPP_SDT_ITEM_T *p_sdt_item = NULL;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no,  0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_sdt_hig32);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_sdt_low32);
-
-    p_sdt_soft_tbl = DPP_SDT_SOFT_TBL_GET(dev_id);
-
-    if (NULL == p_sdt_soft_tbl)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error: dpp_sdt_mgr_sdt_item_srh Soft Table not Init! \n");
-        ZXIC_COMM_ASSERT(0);
-        return DPP_RC_TABLE_SDT_MGR_INVALID;
-    }
-
-    if (dev_id != p_sdt_soft_tbl->device_id)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error: dpp_sdt_mgr_sdt_item_srh Soft Table Item Invalid ! \n");
-        ZXIC_COMM_ASSERT(0);
-        return DPP_RC_TABLE_PARA_INVALID;
-    }
-
-    /* 获取SDT表项 */
-    p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no];
-
-    if (DPP_SDT_VALID == p_sdt_item->valid)
-    {
-        *p_sdt_hig32 = p_sdt_item->table_cfg[0];
-        *p_sdt_low32 = p_sdt_item->table_cfg[1];
-    }
-    else
-    {
-        *p_sdt_hig32 = 0xFFFFFFFF;
-        *p_sdt_low32 = 0xFFFFFFFF;
-    }
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "dpp_sdt_mgr_sdt_item_srh is %s: sdt_no: 0x%08x sdt_hig32:0x%08x sdt_low32:0x%08x \n", ((DPP_SDT_VALID == p_sdt_item->valid) ? ("success") : ("fail")), sdt_no, *p_sdt_hig32, *p_sdt_low32);
-
-    return rc;
-}
-
-/***********************************************************/
-/** 从软件缓存中删除SDT表条目
-* @param   dev_id  设备号
-* @param   sdt_no     业务表对应的sdt号
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/07/13
-************************************************************/
-DPP_STATUS dpp_sdt_mgr_sdt_item_del(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no)
-{
-    DPP_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL;
-    DPP_SDT_ITEM_T *p_sdt_item = NULL;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no,  0, DPP_DEV_SDT_ID_MAX - 1);
-
-    p_sdt_soft_tbl = DPP_SDT_SOFT_TBL_GET(dev_id);
-
-    if (NULL != p_sdt_soft_tbl)
-    {
-        if (dev_id != p_sdt_soft_tbl->device_id)
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Error: dpp_sdt_mgr_sdt_item_del Soft Table Item Invalid ! \n");
-            ZXIC_COMM_ASSERT(0);
-            return DPP_RC_TABLE_PARA_INVALID;
-        }
-
-        p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no];
-        p_sdt_item->valid = DPP_SDT_INVALID;
-        p_sdt_item->table_cfg[0] = 0;
-        p_sdt_item->table_cfg[1] = 0;
-    }
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "dpp_sdt_mgr_sdt_item_del sdt_no: 0x%08x  \n", sdt_no);
-    return DPP_OK;
-}
-
-#endif
-
-
-#if 1
-/*********************************************************************
- * 函数名称：NpeSdtMgr_GetTblType
- *
- * 功能描述:
- *
- * 输入参数：
- * 输出参数：
- * 返 回 值：
- * 全局变量：
- * 注    释：
- ============================================================
- * 修改记录:
- * 修改日期      版本号      修改人       修改内容
- * 20120327      v1.0        石金锋       创建
- ============================================================
- *
- *********************************************************************/
-DPP_TBL_TYPE_E dpp_sdt_mgr_get_tbl_type(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no)
-{
-    ZXIC_UINT32 rtn = 0;
-    DPP_TBL_TYPE_E   table_type = 0;
-    ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN] = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-
-    rtn = dpp_sdt_mgr_sdt_item_srh(dev_id, sdt_no, &(table_cfg[0]), &(table_cfg[1]));
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_sdt_mgr_sdt_item_srh");
-
-    table_type = (DPP_TBL_TYPE_E)((table_cfg[0] >> 29) & 0x7);
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "dpp_sdt_mgr_get_tbl_type: dev_id: %d, sdt_no: %d, table_type: %d. \n", dev_id, sdt_no, table_type);
-
-    return table_type;
-}
-
-/*********************************************************************
- * 函数名称：NpeDriver_GetAsTableEn
- *
- * 功能描述:
- *
- * 输入参数：
- * 输出参数：
- * 返 回 值：
- * 全局变量：
- * 注    释：
- ============================================================
- * 修改记录:
- * 修改日期      版本号      修改人       修改内容
- * 20120829      v1.8        徐东伟       创建
- ============================================================
- *
- *********************************************************************/
-ZXIC_UINT32 dpp_sdt_mgr_get_as_table_en(ZXIC_UINT32 *table_cfg, ZXIC_UINT32 *p_as_en)
-{
-    ZXIC_COMM_CHECK_POINT(table_cfg);
-    ZXIC_COMM_CHECK_POINT(p_as_en);
-
-    *p_as_en = (table_cfg[0] & 0x00004000) >> 14;
-
-    return DPP_OK;
-}
-
-/*********************************************************************
- * 函数名称：NpeDriver_GetAsTableType
- *
- * 功能描述:
- *
- * 输入参数：
- * 输出参数：
- * 返 回 值：
- * 全局变量：
- * 注    释：
- ============================================================
- * 修改记录:
- * 修改日期      版本号      修改人       修改内容
- * 20120829      v1.8        徐东伟       创建
- ============================================================
- *
- *********************************************************************/
-ZXIC_UINT32 dpp_sdt_mgr_get_as_table_type(ZXIC_UINT32 *table_cfg, DPP_TBL_TYPE_E *p_as_type)
-{
-    ZXIC_COMM_CHECK_POINT(table_cfg);
-    ZXIC_COMM_CHECK_POINT(p_as_type);
-
-    *p_as_type = (DPP_TBL_TYPE_E)((table_cfg[0] & 0x00003000) >> 12);
-
-    return DPP_OK;
-}
-
-/*********************************************************************
- * 函数名称：NpeDriver_GetDDR3Page
- *
- * 功能描述:
- *
- * 输入参数：
- * 输出参数：
- * 返 回 值：
- * 全局变量：
- * 注    释：
- ============================================================
- * 修改记录:
- * 修改日期      版本号      修改人       修改内容
- * 20120829      v1.8        徐东伟       创建
- ============================================================
- *
- *********************************************************************/
-ZXIC_UINT32 dpp_sdt_mgr_get_ddr3_page(ZXIC_UINT32 copy_type, ZXIC_UINT32 copy_position, ZXIC_UINT32 *p_page)
-{
-    ZXIC_COMM_CHECK_POINT(p_page);
-
-    return DPP_OK;
-}
-
-/*********************************************************************
- * 函数名称：NpeSdtMgr_SdtSmmu0Print
- *
- * 功能描述:
- *
- * 输入参数：
- * 输出参数：
- * 返 回 值：
- * 全局变量：
- * 注    释：
- ============================================================
- * 修改记录:
- * 修改日期      版本号      修改人       修改内容
- * 20120327      v1.0        石金锋       创建
- ============================================================
- *
- *********************************************************************/
-ZXIC_VOID dpp_sdt_mgr_sdt_smmu0_print(DPP_SDT_SMMU0_T *p_sdt_smmu0)
-{
-    if (NULL == p_sdt_smmu0)
-    {
-        ZXIC_COMM_TRACE_DEBUG("Error: dpp_sdt_mgr_sdt_smmu0_print Input Parameter Invalid !\n");
-        return;
-    }
-
-    if (g_sdt_mgr_debug)
-    {
-        ZXIC_COMM_TRACE_DEBUG("wr_rd_flag:   0x%x\n", p_sdt_smmu0->wr_rd_flag);
-        ZXIC_COMM_TRACE_DEBUG("tbl_index:    0x%x\n", p_sdt_smmu0->tbl_index);
-        ZXIC_COMM_TRACE_DEBUG("mode:         0x%x\n", p_sdt_smmu0->mode);
-        ZXIC_COMM_TRACE_DEBUG("tbl_base_addr:0x%x\n", p_sdt_smmu0->tbl_base_addr);
-        ZXIC_COMM_TRACE_DEBUG("tbl_depth:    0x%x\n", p_sdt_smmu0->tbl_depth);
-        ZXIC_COMM_TRACE_DEBUG("p_data:       0x%08x 0x%08x 0x%08x 0x%08x\n", *((ZXIC_UINT32 *)p_sdt_smmu0->p_data + 0),
-                             *((ZXIC_UINT32 *)p_sdt_smmu0->p_data + 1),
-                             *((ZXIC_UINT32 *)p_sdt_smmu0->p_data + 2),
-                             *((ZXIC_UINT32 *)p_sdt_smmu0->p_data + 3));
-    }
-
-    return;
-}
-
-/*********************************************************************
- * 函数名称：NpeSdtMgr_SdtSmmu1Print
- *
- * 功能描述:
- *
- * 输入参数：
- * 输出参数：
- * 返 回 值：
- * 全局变量：
- * 注    释：
- ============================================================
- * 修改记录:
- * 修改日期      版本号      修改人       修改内容
- * 20120327      v1.0        石金锋       创建
- ============================================================
- *
- *********************************************************************/
-ZXIC_VOID dpp_sdt_mgr_sdt_smmu1_print(DPP_SDT_SMMU1_T *p_sdt_smmu1)
-{
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 mode = 4;
-
-    if (NULL == p_sdt_smmu1)
-    {
-        ZXIC_COMM_TRACE_DEBUG("Error: dpp_sdt_mgr_sdt_smmu1_print Input Parameter Invalid !\n");
-        return;
-    }
-
-    if (g_sdt_mgr_debug)
-    {
-        ZXIC_COMM_TRACE_DEBUG("dwdwCrcChkEn:     0x%x\n", p_sdt_smmu1->crc_chk_en);
-        ZXIC_COMM_TRACE_DEBUG("wr_rd_flag:       0x%x\n", p_sdt_smmu1->wr_rd_flag);
-        ZXIC_COMM_TRACE_DEBUG("tbl_index:        0x%x\n", p_sdt_smmu1->tbl_index);
-        ZXIC_COMM_TRACE_DEBUG("tbl_base_addr:    0x%x\n", p_sdt_smmu1->tbl_base_addr);
-        ZXIC_COMM_TRACE_DEBUG("ddr_share_type:   0x%x\n", p_sdt_smmu1->ddr_share_type);
-        ZXIC_COMM_TRACE_DEBUG("ddr_mode:         0x%x\n", p_sdt_smmu1->ddr_mode);
-
-        ZXIC_COMM_TRACE_DEBUG("p_data:");
-
-        if (0 != p_sdt_smmu1->ddr_mode)
-        {
-            mode = 8;
-        }
-
-        for (i = 0; i < mode; i++)
-        {
-            ZXIC_COMM_TRACE_DEBUG("0x%08x ", *((ZXIC_UINT32 *)p_sdt_smmu1->p_data + i));
-        }
-
-        ZXIC_COMM_TRACE_DEBUG("\n");
-    }
-
-    return;
-}
-
-/*********************************************************************
- * 函数名称：NpeSdtMgr_SdtHashPrint
- *
- * 功能描述:
- *
- * 输入参数：
- * 输出参数：
- * 返 回 值：
- * 全局变量：
- * 注    释：
- ============================================================
- * 修改记录:
- * 修改日期      版本号      修改人       修改内容
- * 20120327      v1.0        石金锋       创建
- ============================================================
- *
- *********************************************************************/
-ZXIC_VOID dpp_sdt_mgr_sdt_hash_print(DPP_SDT_HASH_T *p_sdt_hash)
-{
-    ZXIC_UINT32 i = 0;
-
-    if (NULL == p_sdt_hash)
-    {
-        ZXIC_COMM_TRACE_DEBUG("Error: dpp_sdt_mgr_sdt_hash_print Input Parameter Invalid !\n");
-        return;
-    }
-
-    if (g_sdt_mgr_debug)
-    {
-        ZXIC_COMM_TRACE_DEBUG("addr:0x%x\n", p_sdt_hash->addr);
-        ZXIC_COMM_TRACE_DEBUG("length:%d\n",   p_sdt_hash->length);
-        ZXIC_COMM_TRACE_DEBUG("hash_id:%d\n",   p_sdt_hash->id);
-        ZXIC_COMM_TRACE_DEBUG("table_id:%d\n",   p_sdt_hash->tbl_id);
-        ZXIC_COMM_TRACE_DEBUG("hash_tbl_width:%d\n",  p_sdt_hash->key_type);
-        ZXIC_COMM_TRACE_DEBUG("hash_key_size:%d\n",   p_sdt_hash->key_size);
-        ZXIC_COMM_TRACE_DEBUG("rsp_mode:%d\n",   p_sdt_hash->rsp_mode);
-
-        ZXIC_COMM_TRACE_DEBUG("p_data:");
-
-        for (i = 0; i < p_sdt_hash->length; i++)
-        {
-            ZXIC_COMM_TRACE_DEBUG("0x%08x ", *((ZXIC_UINT32 *)p_sdt_hash->p_data + i));
-        }
-
-        ZXIC_COMM_TRACE_DEBUG("\n");
-    }
-
-    return;
-}
-
-/***********************************************************/
-/**
-* @param   p_sdt_lpm
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/06/16
-************************************************************/
-ZXIC_VOID dpp_sdt_mgr_sdt_etcam_print(DPP_SDT_ETCAM_T *p_sdt_etcam)
-{
-    ZXIC_UINT32 i = 0;
-
-    if (NULL == p_sdt_etcam)
-    {
-        ZXIC_COMM_TRACE_DEBUG("Error: dpp_sdt_mgr_sdt_etcam_print Input Parameter Invalid !\n");
-        return;
-    }
-
-    if (g_sdt_mgr_debug)
-    {
-        ZXIC_COMM_TRACE_DEBUG("table_id      :0x%x\n", p_sdt_etcam->tbl_id);
-        ZXIC_COMM_TRACE_DEBUG("addr          :0x%x\n", p_sdt_etcam->addr);
-        ZXIC_COMM_TRACE_DEBUG("key_mode      :%d\n",   p_sdt_etcam->key_mode);
-        ZXIC_COMM_TRACE_DEBUG("rsp_mode      :%d\n",   p_sdt_etcam->rsp_mode);
-        ZXIC_COMM_TRACE_DEBUG("length        :%d\n",   p_sdt_etcam->length);
-        ZXIC_COMM_TRACE_DEBUG("as_en         :%d\n",   p_sdt_etcam->as_en);
-        ZXIC_COMM_TRACE_DEBUG("as_eram_baddr :0x%x\n", p_sdt_etcam->as_eram_baddr);
-        ZXIC_COMM_TRACE_DEBUG("as_rsp_mode   :%d\n",   p_sdt_etcam->as_rsp_mode);
-        ZXIC_COMM_TRACE_DEBUG("p_data   :");
-
-        for (i = 0; i < p_sdt_etcam->length; i++)
-        {
-            ZXIC_COMM_TRACE_DEBUG("0x%08x ", *((ZXIC_UINT32 *)p_sdt_etcam->p_data + i));
-        }
-
-        ZXIC_COMM_TRACE_DEBUG("\n");
-    }
-
-    return;
-}
-
-/*********************************************************************
- * 函数名称：NpeDriver_GetEram128Params
- *
- * 功能描述:
- *
- * 输入参数：
- * 输出参数：
- * 返 回 值：
- * 全局变量：
- * 注    释：
- ============================================================
- * 修改记录:
- * 修改日期      版本号      修改人             修改内容
- * 20120924      v1.0        石金锋/徐东伟       创建
- ============================================================
- *
- *********************************************************************/
-ZXIC_UINT32 dpp_sdt_mgr_get_eram128_params(ZXIC_UINT32 dev_id, ZXIC_UINT32 table_id, DPP_ERAM128_PARAMS_T *p_eram128_params)
-{
-    ZXIC_UINT32 rtn = 0;
-    ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN] = {0};
-    DPP_ERAM128_MODE_E e128Mode = 0;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, table_id,   0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_eram128_params);
-
-    rtn = dpp_sdt_mgr_sdt_item_srh(dev_id, table_id, &(table_cfg[0]), &(table_cfg[1]));
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_sdt_mgr_sdt_item_srh");
-
-    /** modify By LiuShuo @2016年2月25日10:01:31*/
-    e128Mode = (DPP_ERAM128_MODE_E)((table_cfg[0] & 0x1c000000) >> 26);
-    p_eram128_params->tbl_base_addr = ((table_cfg[0] & 0x003FFFF80) >> 7);
-    p_eram128_params->tbl_depth = ((table_cfg[1] & 0x00007FFFE) >> 1);
-    p_eram128_params->eram128_mode = e128Mode;
-
-    switch (p_eram128_params->eram128_mode)
-    {
-        case Eram128Mode_1BITS:
-        case Eram128Mode_2BITS:
-        case Eram128Mode_4BITS:
-        case Eram128Mode_8BITS:
-        case Eram128Mode_16BITS:
-        case Eram128Mode_32BITS:
-        {
-            p_eram128_params->count = 1;
-            break;
-        }
-
-        case Eram128Mode_64BITS:
-        {
-            p_eram128_params->count = 2;
-            break;
-        }
-
-        default:
-        {
-            p_eram128_params->count = 4; /* eRam默认写4个32bit */
-        }
-    }
-
-    return DPP_OK;
-}
-
-/*********************************************************************
- * 函数名称：NpeSdtMgr_GetDDR3Params
- *
- * 功能描述:
- *
- * 输入参数：
- * 输出参数：
- * 返 回 值：
- * 全局变量：
- * 注    释：
- ============================================================
- * 修改记录:
- * 修改日期      版本号      修改人       修改内容
- * 20120911      v1.8        徐东伟       创建
- ============================================================
- *
- *********************************************************************/
-ZXIC_UINT32 dpp_sdt_mgr_get_ddr3_params(ZXIC_UINT32 dev_id, ZXIC_UINT32 table_id, DPP_DDR3_PARAMS_T *p_ddr3_params)
-{
-    ZXIC_UINT32 rtn = 0;
-    ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN] = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, table_id, 0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_ddr3_params);
-
-    rtn = dpp_sdt_mgr_sdt_item_srh(dev_id, table_id, &(table_cfg[0]), &(table_cfg[1]));
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_sdt_mgr_sdt_item_srh");
-
-    p_ddr3_params->base_addr = ((table_cfg[0] & 0x1FFFFE00) >> 9);
-    p_ddr3_params->tbl_share_mode = ((table_cfg[0] & 0x00000180) >> 7);
-    p_ddr3_params->ddr3_mode = ((table_cfg[0] & 0x00000060) >> 5);
-    p_ddr3_params->crc_check = ((table_cfg[1] & 0x10000000) >> 28);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, p_ddr3_params->ddr3_mode, DDR3Mode_128BITS, DDR3Mode_512BITS);
-    p_ddr3_params->wr_rd_count = 4U << p_ddr3_params->ddr3_mode; /* 根据DDR3模式计算有效数据长度，以4字节为单位 */
-
-    return DPP_OK;
-}
-
-/*********************************************************************
- * 函数名称：NpeDriver_GetHashParams
- *
- * 功能描述:
- *
- * 输入参数：
- * 输出参数：
- * 返 回 值：
- * 全局变量：
- * 注    释：
- ============================================================
- * 修改记录:
- * 修改日期      版本号      修改人             修改内容
- * 20120924      v1.0        石金锋/徐东伟       创建
- ============================================================
- *
- *********************************************************************/
-ZXIC_UINT32 dpp_sdt_mgr_get_hash_params(ZXIC_UINT32 dev_id, ZXIC_UINT32 table_id, DPP_HASH_PARAMS_T *p_hash_params)
-{
-    ZXIC_UINT32 rtn = 0;
-    ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN] = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, table_id, 0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_hash_params);
-
-    rtn = dpp_sdt_mgr_sdt_item_srh(dev_id, table_id, &(table_cfg[0]), &(table_cfg[1]));
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_sdt_mgr_sdt_item_srh");
-
-    ZXIC_COMM_UINT32_GET_BITS(p_hash_params->hash_id,       table_cfg[0], DPP_SDT_H_HASH_ID_BT_POS,           DPP_SDT_H_HASH_ID_BT_LEN);
-    ZXIC_COMM_UINT32_GET_BITS(p_hash_params->key_tbl_width, table_cfg[0], DPP_SDT_H_HASH_TABLE_WIDTH_BT_POS,  DPP_SDT_H_HASH_TABLE_WIDTH_BT_LEN);
-    ZXIC_COMM_UINT32_GET_BITS(p_hash_params->key_size,      table_cfg[0], DPP_SDT_H_HASH_KEY_SIZE_BT_POS,     DPP_SDT_H_HASH_KEY_SIZE_BT_LEN);
-    ZXIC_COMM_UINT32_GET_BITS(p_hash_params->table_id,      table_cfg[0], DPP_SDT_H_HASH_TABLE_ID_BT_POS,     DPP_SDT_H_HASH_TABLE_ID_BT_LEN);
-    ZXIC_COMM_UINT32_GET_BITS(p_hash_params->rsp_mode,      table_cfg[1], DPP_SDT_L_RSP_MODE_BT_POS,           DPP_SDT_L_RSP_MODE_BT_LEN);
-    return DPP_OK;
-}
-
-/*********************************************************************
- * 函数名称：NpeDriver_GetTcamParams
- *
- * 功能描述:
- *
- * 输入参数：
- * 输出参数：
- * 返 回 值：
- * 全局变量：
- * 注    释：
- ============================================================
- * 修改记录:
- * 修改日期      版本号      修改人             修改内容
- * 20120924      v1.0        石金锋/徐东伟       创建
- ============================================================
- *
- *********************************************************************/
-ZXIC_UINT32 dpp_sdt_mgr_get_etcam_params(ZXIC_UINT32 dev_id, ZXIC_UINT32 table_id, DPP_ETCAM_PARAMS_T *p_etcam_params)
-{
-    ZXIC_UINT32 rtn = 0;
-    ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN] = {0};
-    ZXIC_UINT32 temp = 0;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, table_id,   0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_etcam_params);
-
-    rtn = dpp_sdt_mgr_sdt_item_srh(dev_id, table_id, &(table_cfg[0]), &(table_cfg[1]));
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_sdt_mgr_sdt_item_srh");
-
-    ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->id,          table_cfg[0], DPP_SDT_H_ETCAM_ID_BT_POS,              DPP_SDT_H_ETCAM_ID_BT_LEN);
-    ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->key_mode,    table_cfg[0], DPP_SDT_H_ETCAM_KEY_MODE_BT_POS,        DPP_SDT_H_ETCAM_KEY_MODE_BT_LEN);
-    ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->table_id,    table_cfg[0], DPP_SDT_H_ETCAM_TABLE_ID_BT_POS,        DPP_SDT_H_ETCAM_TABLE_ID_BT_LEN);
-    ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->rsp_mode,    table_cfg[0], DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS,   DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN);
-    ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->as_en,       table_cfg[0], DPP_SDT_H_ETCAM_AS_EN_BT_POS,           DPP_SDT_H_ETCAM_AS_EN_BT_LEN);
-    ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->as_baddr,    table_cfg[0], DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS,   DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN);
-    ZXIC_COMM_UINT32_GET_BITS(temp,                        table_cfg[1], DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS,   DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN);
-    p_etcam_params->as_baddr = (p_etcam_params->as_baddr << DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN) + temp;
-    ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->as_rsp_mode, table_cfg[1], DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_POS,     DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN);
-
-    return DPP_OK;
-}
-
-#endif
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_sdt_mgr.c
+* 文件标识 :
+* 内容摘要 : SDT属性软件缓存，以及接收上层配置并下发给底层设备
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2015/06/25
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#include "zxic_common.h"
+
+#include "dpp_dev.h"
+#include "dpp_sdt_def.h"
+#include "dpp_sdt.h"
+#include "dpp_sdt_mgr.h"
+#include "dpp_se_api.h"
+
+static DPP_SDT_MGR_T g_sdt_mgr = { 0 };
+
+static ZXIC_UINT32 g_sdt_mgr_debug = 1;
+
+#define DPP_SDT_MGR_PTR_GET() (&g_sdt_mgr)
+
+#define DPP_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id])
+
+ZXIC_UINT32 dpp_sdt_mgr_init(ZXIC_VOID)
+{
+	if (!g_sdt_mgr.is_init) {
+		g_sdt_mgr.channel_num = 0;
+		g_sdt_mgr.is_init = 1;
+		// g_sdt_mgr.p_sdt_mgr_smmu0_mux = dpp_tbl_dir_sdt_smmu0_mux;
+		// g_sdt_mgr.p_sdt_mgr_smmu1_mux = dpp_tbl_dir_sdt_smmu1_mux;
+		// g_sdt_mgr.p_sdt_mgr_hash_mux = dpp_tbl_dir_sdt_hash_mux;
+		// g_sdt_mgr.p_sdt_mgr_lpm_mux = dpp_tbl_dir_sdt_lpm_mux;
+		// g_sdt_mgr.p_sdt_mgr_etcam_mux = dpp_tbl_dir_sdt_etcam_mux;
+		ZXIC_COMM_MEMSET(g_sdt_mgr.sdt_tbl_array, 0,
+						 DPP_DEV_CHANNEL_MAX * sizeof(DPP_SDT_SOFT_TABLE_T *));
+	}
+
+	return DPP_OK;
+}
+
+ZXIC_UINT32 dpp_sdt_mgr_create(ZXIC_UINT32 dev_id)
+{
+	DPP_SDT_SOFT_TABLE_T *p_sdt_tbl_temp = NULL;
+	DPP_SDT_MGR_T *p_sdt_mgr = NULL;
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+
+	p_sdt_mgr = DPP_SDT_MGR_PTR_GET();
+
+	if (DPP_SDT_SOFT_TBL_GET(dev_id) == NULL) {
+		p_sdt_tbl_temp = ZXIC_COMM_MALLOC(sizeof(DPP_SDT_SOFT_TABLE_T));
+		ZXIC_COMM_CHECK_DEV_POINT(dev_id,
+								  p_sdt_tbl_temp); /* mod for KW_0411 # 474 */
+
+		p_sdt_tbl_temp->device_id = dev_id;
+		ZXIC_COMM_MEMSET(p_sdt_tbl_temp->sdt_array, 0,
+						 DPP_DEV_SDT_ID_MAX * sizeof(DPP_SDT_ITEM_T));
+
+		DPP_SDT_SOFT_TBL_GET(dev_id) = p_sdt_tbl_temp;
+		ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(
+				dev_id, p_sdt_mgr->channel_num, 1);
+		p_sdt_mgr->channel_num++;
+	} else {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id,
+				"Error: dpp_sdt_mgr_create for dev[%d] is called repeatedly!\n",
+				dev_id);
+	}
+
+	return DPP_OK;
+}
+
+ZXIC_UINT32 dpp_sdt_mgr_destroy(ZXIC_UINT32 dev_id)
+{
+	DPP_SDT_SOFT_TABLE_T *p_sdt_tbl_temp = NULL;
+	DPP_SDT_MGR_T *p_sdt_mgr = NULL;
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+
+	p_sdt_tbl_temp = DPP_SDT_SOFT_TBL_GET(dev_id);
+	p_sdt_mgr = DPP_SDT_MGR_PTR_GET();
+
+	if (NULL != p_sdt_tbl_temp) {
+		ZXIC_COMM_FREE(p_sdt_tbl_temp);
+	}
+
+	DPP_SDT_SOFT_TBL_GET(dev_id) = NULL;
+
+	ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id,
+													 p_sdt_mgr->channel_num, 1);
+	p_sdt_mgr->channel_num--;
+
+	return DPP_OK;
+}
+
+#if 1
+/***********************************************************/
+/** 向软件缓存中添加SDT表条目
+ * @param   dev_id  设备号
+ * @param   sdt_no     业务表对应的sdt号
+ * @param   sdt_hig32  SDT属性高32bit
+ * @param   sdt_low32  SDT属性低32bit
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/07/13
+ ************************************************************/
+DPP_STATUS dpp_sdt_mgr_sdt_item_add(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no,
+									ZXIC_UINT32 sdt_hig32,
+									ZXIC_UINT32 sdt_low32)
+{
+	DPP_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL;
+	DPP_SDT_ITEM_T *p_sdt_item = NULL;
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+
+	p_sdt_soft_tbl = DPP_SDT_SOFT_TBL_GET(dev_id);
+
+	if (NULL == p_sdt_soft_tbl) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id,
+				"Error: dpp_sdt_mgr_sdt_item_add soft sdt table not Init! \n");
+		ZXIC_COMM_ASSERT(0);
+		return DPP_RC_TABLE_SDT_MGR_INVALID;
+	}
+
+	if (dev_id != p_sdt_soft_tbl->device_id) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id,
+				"Error: dpp_sdt_mgr_sdt_item_add soft sdt table Item Invalid! \n");
+		ZXIC_COMM_ASSERT(0);
+		return DPP_RC_TABLE_PARA_INVALID;
+	}
+
+	/*添加SDT表项*/
+	p_sdt_item = &(p_sdt_soft_tbl->sdt_array[sdt_no]);
+	p_sdt_item->valid = DPP_SDT_VALID;
+	p_sdt_item->table_cfg[0] = sdt_hig32; /* hig32 */
+	p_sdt_item->table_cfg[1] = sdt_low32; /* low32 */
+
+	ZXIC_COMM_TRACE_DEV_DEBUG(dev_id,
+							  "dpp_sdt_mgr_sdt_item_add 0x%08x 0x%08x \n",
+							  p_sdt_item->table_cfg[0],
+							  p_sdt_item->table_cfg[1]);
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 从软件缓存中读取SDT表条目
+ * @param   dev_id    设备号
+ * @param   sdt_no       业务表对应的sdt号
+ * @param   p_sdt_hig32  SDT属性高32bit
+ * @param   p_sdt_low32  SDT属性低32bit
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/07/13
+ ************************************************************/
+DPP_STATUS dpp_sdt_mgr_sdt_item_srh(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no,
+									ZXIC_UINT32 *p_sdt_hig32,
+									ZXIC_UINT32 *p_sdt_low32)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL;
+	DPP_SDT_ITEM_T *p_sdt_item = NULL;
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_sdt_hig32);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_sdt_low32);
+
+	p_sdt_soft_tbl = DPP_SDT_SOFT_TBL_GET(dev_id);
+
+	if (NULL == p_sdt_soft_tbl) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id,
+				"Error: dpp_sdt_mgr_sdt_item_srh Soft Table not Init! \n");
+		ZXIC_COMM_ASSERT(0);
+		return DPP_RC_TABLE_SDT_MGR_INVALID;
+	}
+
+	if (dev_id != p_sdt_soft_tbl->device_id) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id,
+				"Error: dpp_sdt_mgr_sdt_item_srh Soft Table Item Invalid ! \n");
+		ZXIC_COMM_ASSERT(0);
+		return DPP_RC_TABLE_PARA_INVALID;
+	}
+
+	/* 获取SDT表项 */
+	p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no];
+
+	if (DPP_SDT_VALID == p_sdt_item->valid) {
+		*p_sdt_hig32 = p_sdt_item->table_cfg[0];
+		*p_sdt_low32 = p_sdt_item->table_cfg[1];
+	} else {
+		*p_sdt_hig32 = 0xFFFFFFFF;
+		*p_sdt_low32 = 0xFFFFFFFF;
+	}
+
+	ZXIC_COMM_TRACE_DEV_DEBUG(
+			dev_id,
+			"dpp_sdt_mgr_sdt_item_srh is %s: sdt_no: 0x%08x sdt_hig32:0x%08x sdt_low32:0x%08x \n",
+			((DPP_SDT_VALID == p_sdt_item->valid) ? ("success") : ("fail")),
+			sdt_no, *p_sdt_hig32, *p_sdt_low32);
+
+	return rc;
+}
+
+/***********************************************************/
+/** 从软件缓存中删除SDT表条目
+ * @param   dev_id  设备号
+ * @param   sdt_no     业务表对应的sdt号
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/07/13
+ ************************************************************/
+DPP_STATUS dpp_sdt_mgr_sdt_item_del(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no)
+{
+	DPP_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL;
+	DPP_SDT_ITEM_T *p_sdt_item = NULL;
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+
+	p_sdt_soft_tbl = DPP_SDT_SOFT_TBL_GET(dev_id);
+
+	if (NULL != p_sdt_soft_tbl) {
+		if (dev_id != p_sdt_soft_tbl->device_id) {
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					dev_id,
+					"Error: dpp_sdt_mgr_sdt_item_del Soft Table Item Invalid ! \n");
+			ZXIC_COMM_ASSERT(0);
+			return DPP_RC_TABLE_PARA_INVALID;
+		}
+
+		p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no];
+		p_sdt_item->valid = DPP_SDT_INVALID;
+		p_sdt_item->table_cfg[0] = 0;
+		p_sdt_item->table_cfg[1] = 0;
+	}
+	ZXIC_COMM_TRACE_DEV_DEBUG(
+			dev_id, "dpp_sdt_mgr_sdt_item_del sdt_no: 0x%08x  \n", sdt_no);
+	return DPP_OK;
+}
+
+#endif
+
+#if 1
+/*********************************************************************
+ * 函数名称：NpeSdtMgr_GetTblType
+ *
+ * 功能描述:
+ *
+ * 输入参数：
+ * 输出参数：
+ * 返 回 值：
+ * 全局变量：
+ * 注    释：
+ ============================================================
+ * 修改记录:
+ * 修改日期      版本号      修改人       修改内容
+ * 20120327      v1.0        石金锋       创建
+ ============================================================
+ *
+ *********************************************************************/
+DPP_TBL_TYPE_E dpp_sdt_mgr_get_tbl_type(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no)
+{
+	ZXIC_UINT32 rtn = 0;
+	DPP_TBL_TYPE_E table_type = 0;
+	ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN] = { 0 };
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+
+	rtn = dpp_sdt_mgr_sdt_item_srh(dev_id, sdt_no, &(table_cfg[0]),
+								   &(table_cfg[1]));
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_sdt_mgr_sdt_item_srh");
+
+	table_type = (DPP_TBL_TYPE_E)((table_cfg[0] >> 29) & 0x7);
+
+	ZXIC_COMM_TRACE_DEV_DEBUG(
+			dev_id,
+			"dpp_sdt_mgr_get_tbl_type: dev_id: %d, sdt_no: %d, table_type: %d. \n",
+			dev_id, sdt_no, table_type);
+
+	return table_type;
+}
+
+/*********************************************************************
+ * 函数名称：NpeDriver_GetAsTableEn
+ *
+ * 功能描述:
+ *
+ * 输入参数：
+ * 输出参数：
+ * 返 回 值：
+ * 全局变量：
+ * 注    释：
+ ============================================================
+ * 修改记录:
+ * 修改日期      版本号      修改人       修改内容
+ * 20120829      v1.8        徐东伟       创建
+ ============================================================
+ *
+ *********************************************************************/
+ZXIC_UINT32 dpp_sdt_mgr_get_as_table_en(ZXIC_UINT32 *table_cfg,
+										ZXIC_UINT32 *p_as_en)
+{
+	ZXIC_COMM_CHECK_POINT(table_cfg);
+	ZXIC_COMM_CHECK_POINT(p_as_en);
+
+	*p_as_en = (table_cfg[0] & 0x00004000) >> 14;
+
+	return DPP_OK;
+}
+
+/*********************************************************************
+ * 函数名称：NpeDriver_GetAsTableType
+ *
+ * 功能描述:
+ *
+ * 输入参数：
+ * 输出参数：
+ * 返 回 值：
+ * 全局变量：
+ * 注    释：
+ ============================================================
+ * 修改记录:
+ * 修改日期      版本号      修改人       修改内容
+ * 20120829      v1.8        徐东伟       创建
+ ============================================================
+ *
+ *********************************************************************/
+ZXIC_UINT32 dpp_sdt_mgr_get_as_table_type(ZXIC_UINT32 *table_cfg,
+										  DPP_TBL_TYPE_E *p_as_type)
+{
+	ZXIC_COMM_CHECK_POINT(table_cfg);
+	ZXIC_COMM_CHECK_POINT(p_as_type);
+
+	*p_as_type = (DPP_TBL_TYPE_E)((table_cfg[0] & 0x00003000) >> 12);
+
+	return DPP_OK;
+}
+
+/*********************************************************************
+ * 函数名称：NpeDriver_GetDDR3Page
+ *
+ * 功能描述:
+ *
+ * 输入参数：
+ * 输出参数：
+ * 返 回 值：
+ * 全局变量：
+ * 注    释：
+ ============================================================
+ * 修改记录:
+ * 修改日期      版本号      修改人       修改内容
+ * 20120829      v1.8        徐东伟       创建
+ ============================================================
+ *
+ *********************************************************************/
+ZXIC_UINT32 dpp_sdt_mgr_get_ddr3_page(ZXIC_UINT32 copy_type,
+									  ZXIC_UINT32 copy_position,
+									  ZXIC_UINT32 *p_page)
+{
+	ZXIC_COMM_CHECK_POINT(p_page);
+
+	return DPP_OK;
+}
+
+/*********************************************************************
+ * 函数名称：NpeSdtMgr_SdtSmmu0Print
+ *
+ * 功能描述:
+ *
+ * 输入参数：
+ * 输出参数：
+ * 返 回 值：
+ * 全局变量：
+ * 注    释：
+ ============================================================
+ * 修改记录:
+ * 修改日期      版本号      修改人       修改内容
+ * 20120327      v1.0        石金锋       创建
+ ============================================================
+ *
+ *********************************************************************/
+ZXIC_VOID dpp_sdt_mgr_sdt_smmu0_print(DPP_SDT_SMMU0_T *p_sdt_smmu0)
+{
+	if (NULL == p_sdt_smmu0) {
+		ZXIC_COMM_TRACE_DEBUG(
+				"Error: dpp_sdt_mgr_sdt_smmu0_print Input Parameter Invalid !\n");
+		return;
+	}
+
+	if (g_sdt_mgr_debug) {
+		ZXIC_COMM_TRACE_DEBUG("wr_rd_flag:   0x%x\n", p_sdt_smmu0->wr_rd_flag);
+		ZXIC_COMM_TRACE_DEBUG("tbl_index:    0x%x\n", p_sdt_smmu0->tbl_index);
+		ZXIC_COMM_TRACE_DEBUG("mode:         0x%x\n", p_sdt_smmu0->mode);
+		ZXIC_COMM_TRACE_DEBUG("tbl_base_addr:0x%x\n",
+							  p_sdt_smmu0->tbl_base_addr);
+		ZXIC_COMM_TRACE_DEBUG("tbl_depth:    0x%x\n", p_sdt_smmu0->tbl_depth);
+		ZXIC_COMM_TRACE_DEBUG("p_data:       0x%08x 0x%08x 0x%08x 0x%08x\n",
+							  *((ZXIC_UINT32 *)p_sdt_smmu0->p_data + 0),
+							  *((ZXIC_UINT32 *)p_sdt_smmu0->p_data + 1),
+							  *((ZXIC_UINT32 *)p_sdt_smmu0->p_data + 2),
+							  *((ZXIC_UINT32 *)p_sdt_smmu0->p_data + 3));
+	}
+
+	return;
+}
+
+/*********************************************************************
+ * 函数名称：NpeSdtMgr_SdtSmmu1Print
+ *
+ * 功能描述:
+ *
+ * 输入参数：
+ * 输出参数：
+ * 返 回 值：
+ * 全局变量：
+ * 注    释：
+ ============================================================
+ * 修改记录:
+ * 修改日期      版本号      修改人       修改内容
+ * 20120327      v1.0        石金锋       创建
+ ============================================================
+ *
+ *********************************************************************/
+ZXIC_VOID dpp_sdt_mgr_sdt_smmu1_print(DPP_SDT_SMMU1_T *p_sdt_smmu1)
+{
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 mode = 4;
+
+	if (NULL == p_sdt_smmu1) {
+		ZXIC_COMM_TRACE_DEBUG(
+				"Error: dpp_sdt_mgr_sdt_smmu1_print Input Parameter Invalid !\n");
+		return;
+	}
+
+	if (g_sdt_mgr_debug) {
+		ZXIC_COMM_TRACE_DEBUG("dwdwCrcChkEn:     0x%x\n",
+							  p_sdt_smmu1->crc_chk_en);
+		ZXIC_COMM_TRACE_DEBUG("wr_rd_flag:       0x%x\n",
+							  p_sdt_smmu1->wr_rd_flag);
+		ZXIC_COMM_TRACE_DEBUG("tbl_index:        0x%x\n",
+							  p_sdt_smmu1->tbl_index);
+		ZXIC_COMM_TRACE_DEBUG("tbl_base_addr:    0x%x\n",
+							  p_sdt_smmu1->tbl_base_addr);
+		ZXIC_COMM_TRACE_DEBUG("ddr_share_type:   0x%x\n",
+							  p_sdt_smmu1->ddr_share_type);
+		ZXIC_COMM_TRACE_DEBUG("ddr_mode:         0x%x\n",
+							  p_sdt_smmu1->ddr_mode);
+
+		ZXIC_COMM_TRACE_DEBUG("p_data:");
+
+		if (0 != p_sdt_smmu1->ddr_mode) {
+			mode = 8;
+		}
+
+		for (i = 0; i < mode; i++) {
+			ZXIC_COMM_TRACE_DEBUG("0x%08x ",
+								  *((ZXIC_UINT32 *)p_sdt_smmu1->p_data + i));
+		}
+
+		ZXIC_COMM_TRACE_DEBUG("\n");
+	}
+
+	return;
+}
+
+/*********************************************************************
+ * 函数名称：NpeSdtMgr_SdtHashPrint
+ *
+ * 功能描述:
+ *
+ * 输入参数：
+ * 输出参数：
+ * 返 回 值：
+ * 全局变量：
+ * 注    释：
+ ============================================================
+ * 修改记录:
+ * 修改日期      版本号      修改人       修改内容
+ * 20120327      v1.0        石金锋       创建
+ ============================================================
+ *
+ *********************************************************************/
+ZXIC_VOID dpp_sdt_mgr_sdt_hash_print(DPP_SDT_HASH_T *p_sdt_hash)
+{
+	ZXIC_UINT32 i = 0;
+
+	if (NULL == p_sdt_hash) {
+		ZXIC_COMM_TRACE_DEBUG(
+				"Error: dpp_sdt_mgr_sdt_hash_print Input Parameter Invalid !\n");
+		return;
+	}
+
+	if (g_sdt_mgr_debug) {
+		ZXIC_COMM_TRACE_DEBUG("addr:0x%x\n", p_sdt_hash->addr);
+		ZXIC_COMM_TRACE_DEBUG("length:%d\n", p_sdt_hash->length);
+		ZXIC_COMM_TRACE_DEBUG("hash_id:%d\n", p_sdt_hash->id);
+		ZXIC_COMM_TRACE_DEBUG("table_id:%d\n", p_sdt_hash->tbl_id);
+		ZXIC_COMM_TRACE_DEBUG("hash_tbl_width:%d\n", p_sdt_hash->key_type);
+		ZXIC_COMM_TRACE_DEBUG("hash_key_size:%d\n", p_sdt_hash->key_size);
+		ZXIC_COMM_TRACE_DEBUG("rsp_mode:%d\n", p_sdt_hash->rsp_mode);
+
+		ZXIC_COMM_TRACE_DEBUG("p_data:");
+
+		for (i = 0; i < p_sdt_hash->length; i++) {
+			ZXIC_COMM_TRACE_DEBUG("0x%08x ",
+								  *((ZXIC_UINT32 *)p_sdt_hash->p_data + i));
+		}
+
+		ZXIC_COMM_TRACE_DEBUG("\n");
+	}
+
+	return;
+}
+
+/***********************************************************/
+/**
+ * @param   p_sdt_lpm
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/06/16
+ ************************************************************/
+ZXIC_VOID dpp_sdt_mgr_sdt_etcam_print(DPP_SDT_ETCAM_T *p_sdt_etcam)
+{
+	ZXIC_UINT32 i = 0;
+
+	if (NULL == p_sdt_etcam) {
+		ZXIC_COMM_TRACE_DEBUG(
+				"Error: dpp_sdt_mgr_sdt_etcam_print Input Parameter Invalid !\n");
+		return;
+	}
+
+	if (g_sdt_mgr_debug) {
+		ZXIC_COMM_TRACE_DEBUG("table_id      :0x%x\n", p_sdt_etcam->tbl_id);
+		ZXIC_COMM_TRACE_DEBUG("addr          :0x%x\n", p_sdt_etcam->addr);
+		ZXIC_COMM_TRACE_DEBUG("key_mode      :%d\n", p_sdt_etcam->key_mode);
+		ZXIC_COMM_TRACE_DEBUG("rsp_mode      :%d\n", p_sdt_etcam->rsp_mode);
+		ZXIC_COMM_TRACE_DEBUG("length        :%d\n", p_sdt_etcam->length);
+		ZXIC_COMM_TRACE_DEBUG("as_en         :%d\n", p_sdt_etcam->as_en);
+		ZXIC_COMM_TRACE_DEBUG("as_eram_baddr :0x%x\n",
+							  p_sdt_etcam->as_eram_baddr);
+		ZXIC_COMM_TRACE_DEBUG("as_rsp_mode   :%d\n", p_sdt_etcam->as_rsp_mode);
+		ZXIC_COMM_TRACE_DEBUG("p_data   :");
+
+		for (i = 0; i < p_sdt_etcam->length; i++) {
+			ZXIC_COMM_TRACE_DEBUG("0x%08x ",
+								  *((ZXIC_UINT32 *)p_sdt_etcam->p_data + i));
+		}
+
+		ZXIC_COMM_TRACE_DEBUG("\n");
+	}
+
+	return;
+}
+
+/*********************************************************************
+ * 函数名称：NpeDriver_GetEram128Params
+ *
+ * 功能描述:
+ *
+ * 输入参数：
+ * 输出参数：
+ * 返 回 值：
+ * 全局变量：
+ * 注    释：
+ ============================================================
+ * 修改记录:
+ * 修改日期      版本号      修改人             修改内容
+ * 20120924      v1.0        石金锋/徐东伟       创建
+ ============================================================
+ *
+ *********************************************************************/
+ZXIC_UINT32
+dpp_sdt_mgr_get_eram128_params(ZXIC_UINT32 dev_id, ZXIC_UINT32 table_id,
+							   DPP_ERAM128_PARAMS_T *p_eram128_params)
+{
+	ZXIC_UINT32 rtn = 0;
+	ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN] = { 0 };
+	DPP_ERAM128_MODE_E e128Mode = 0;
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, table_id, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_eram128_params);
+
+	rtn = dpp_sdt_mgr_sdt_item_srh(dev_id, table_id, &(table_cfg[0]),
+								   &(table_cfg[1]));
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_sdt_mgr_sdt_item_srh");
+
+	/** modify By LiuShuo @2016年2月25日10:01:31*/
+	e128Mode = (DPP_ERAM128_MODE_E)((table_cfg[0] & 0x1c000000) >> 26);
+	p_eram128_params->tbl_base_addr = ((table_cfg[0] & 0x003FFFF80) >> 7);
+	p_eram128_params->tbl_depth = ((table_cfg[1] & 0x00007FFFE) >> 1);
+	p_eram128_params->eram128_mode = e128Mode;
+
+	switch (p_eram128_params->eram128_mode) {
+	case Eram128Mode_1BITS:
+	case Eram128Mode_2BITS:
+	case Eram128Mode_4BITS:
+	case Eram128Mode_8BITS:
+	case Eram128Mode_16BITS:
+	case Eram128Mode_32BITS: {
+		p_eram128_params->count = 1;
+		break;
+	}
+
+	case Eram128Mode_64BITS: {
+		p_eram128_params->count = 2;
+		break;
+	}
+
+	default: {
+		p_eram128_params->count = 4; /* eRam默认写4个32bit */
+	}
+	}
+
+	return DPP_OK;
+}
+
+/*********************************************************************
+ * 函数名称：NpeSdtMgr_GetDDR3Params
+ *
+ * 功能描述:
+ *
+ * 输入参数：
+ * 输出参数：
+ * 返 回 值：
+ * 全局变量：
+ * 注    释：
+ ============================================================
+ * 修改记录:
+ * 修改日期      版本号      修改人       修改内容
+ * 20120911      v1.8        徐东伟       创建
+ ============================================================
+ *
+ *********************************************************************/
+ZXIC_UINT32 dpp_sdt_mgr_get_ddr3_params(ZXIC_UINT32 dev_id,
+										ZXIC_UINT32 table_id,
+										DPP_DDR3_PARAMS_T *p_ddr3_params)
+{
+	ZXIC_UINT32 rtn = 0;
+	ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN] = { 0 };
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, table_id, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_ddr3_params);
+
+	rtn = dpp_sdt_mgr_sdt_item_srh(dev_id, table_id, &(table_cfg[0]),
+								   &(table_cfg[1]));
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_sdt_mgr_sdt_item_srh");
+
+	p_ddr3_params->base_addr = ((table_cfg[0] & 0x1FFFFE00) >> 9);
+	p_ddr3_params->tbl_share_mode = ((table_cfg[0] & 0x00000180) >> 7);
+	p_ddr3_params->ddr3_mode = ((table_cfg[0] & 0x00000060) >> 5);
+	p_ddr3_params->crc_check = ((table_cfg[1] & 0x10000000) >> 28);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, p_ddr3_params->ddr3_mode,
+							  DDR3Mode_128BITS, DDR3Mode_512BITS);
+	p_ddr3_params->wr_rd_count =
+			4U
+			<< p_ddr3_params
+					   ->ddr3_mode; /* 根据DDR3模式计算有效数据长度，以4字节为单位 */
+
+	return DPP_OK;
+}
+
+/*********************************************************************
+ * 函数名称：NpeDriver_GetHashParams
+ *
+ * 功能描述:
+ *
+ * 输入参数：
+ * 输出参数：
+ * 返 回 值：
+ * 全局变量：
+ * 注    释：
+ ============================================================
+ * 修改记录:
+ * 修改日期      版本号      修改人             修改内容
+ * 20120924      v1.0        石金锋/徐东伟       创建
+ ============================================================
+ *
+ *********************************************************************/
+ZXIC_UINT32 dpp_sdt_mgr_get_hash_params(ZXIC_UINT32 dev_id,
+										ZXIC_UINT32 table_id,
+										DPP_HASH_PARAMS_T *p_hash_params)
+{
+	ZXIC_UINT32 rtn = 0;
+	ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN] = { 0 };
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, table_id, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_hash_params);
+
+	rtn = dpp_sdt_mgr_sdt_item_srh(dev_id, table_id, &(table_cfg[0]),
+								   &(table_cfg[1]));
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_sdt_mgr_sdt_item_srh");
+
+	ZXIC_COMM_UINT32_GET_BITS(p_hash_params->hash_id, table_cfg[0],
+							  DPP_SDT_H_HASH_ID_BT_POS,
+							  DPP_SDT_H_HASH_ID_BT_LEN);
+	ZXIC_COMM_UINT32_GET_BITS(p_hash_params->key_tbl_width, table_cfg[0],
+							  DPP_SDT_H_HASH_TABLE_WIDTH_BT_POS,
+							  DPP_SDT_H_HASH_TABLE_WIDTH_BT_LEN);
+	ZXIC_COMM_UINT32_GET_BITS(p_hash_params->key_size, table_cfg[0],
+							  DPP_SDT_H_HASH_KEY_SIZE_BT_POS,
+							  DPP_SDT_H_HASH_KEY_SIZE_BT_LEN);
+	ZXIC_COMM_UINT32_GET_BITS(p_hash_params->table_id, table_cfg[0],
+							  DPP_SDT_H_HASH_TABLE_ID_BT_POS,
+							  DPP_SDT_H_HASH_TABLE_ID_BT_LEN);
+	ZXIC_COMM_UINT32_GET_BITS(p_hash_params->rsp_mode, table_cfg[1],
+							  DPP_SDT_L_RSP_MODE_BT_POS,
+							  DPP_SDT_L_RSP_MODE_BT_LEN);
+	return DPP_OK;
+}
+
+/*********************************************************************
+ * 函数名称：NpeDriver_GetTcamParams
+ *
+ * 功能描述:
+ *
+ * 输入参数：
+ * 输出参数：
+ * 返 回 值：
+ * 全局变量：
+ * 注    释：
+ ============================================================
+ * 修改记录:
+ * 修改日期      版本号      修改人             修改内容
+ * 20120924      v1.0        石金锋/徐东伟       创建
+ ============================================================
+ *
+ *********************************************************************/
+ZXIC_UINT32 dpp_sdt_mgr_get_etcam_params(ZXIC_UINT32 dev_id,
+										 ZXIC_UINT32 table_id,
+										 DPP_ETCAM_PARAMS_T *p_etcam_params)
+{
+	ZXIC_UINT32 rtn = 0;
+	ZXIC_UINT32 table_cfg[DPP_SDT_CFG_LEN] = { 0 };
+	ZXIC_UINT32 temp = 0;
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, table_id, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_etcam_params);
+
+	rtn = dpp_sdt_mgr_sdt_item_srh(dev_id, table_id, &(table_cfg[0]),
+								   &(table_cfg[1]));
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_sdt_mgr_sdt_item_srh");
+
+	ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->id, table_cfg[0],
+							  DPP_SDT_H_ETCAM_ID_BT_POS,
+							  DPP_SDT_H_ETCAM_ID_BT_LEN);
+	ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->key_mode, table_cfg[0],
+							  DPP_SDT_H_ETCAM_KEY_MODE_BT_POS,
+							  DPP_SDT_H_ETCAM_KEY_MODE_BT_LEN);
+	ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->table_id, table_cfg[0],
+							  DPP_SDT_H_ETCAM_TABLE_ID_BT_POS,
+							  DPP_SDT_H_ETCAM_TABLE_ID_BT_LEN);
+	ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->rsp_mode, table_cfg[0],
+							  DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS,
+							  DPP_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN);
+	ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->as_en, table_cfg[0],
+							  DPP_SDT_H_ETCAM_AS_EN_BT_POS,
+							  DPP_SDT_H_ETCAM_AS_EN_BT_LEN);
+	ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->as_baddr, table_cfg[0],
+							  DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS,
+							  DPP_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN);
+	ZXIC_COMM_UINT32_GET_BITS(temp, table_cfg[1],
+							  DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS,
+							  DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN);
+	p_etcam_params->as_baddr =
+			(p_etcam_params->as_baddr << DPP_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN) +
+			temp;
+	ZXIC_COMM_UINT32_GET_BITS(p_etcam_params->as_rsp_mode, table_cfg[1],
+							  DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_POS,
+							  DPP_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN);
+
+	return DPP_OK;
+}
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_acl.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_acl.c
old mode 100755
new mode 100644
index 0150762f0435f41aecbfd8d4aa7564f6d4fb9934..f3c6c0f531e26e861c83a188cf81cb324666690b
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_acl.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_acl.c
@@ -1,611 +1,641 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_acl.c
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : 王春雷
-* 完成日期 : 2014/12/17
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-
-#include "zxic_common.h"
-
-#include "dpp_dev.h"
-#include "dpp_acl.h"
-#include "dpp_etcam.h"
-#include "dpp_se.h"
-#include "dpp_se_reg.h"
-#include "dpp_reg_api.h"
-#include "dpp_reg_info.h"
-
-#define BLOCK_IDXBASE_BIT_OFF (9)
-#define BLOCK_IDXBASE_BIT_MASK (0x7f)
-#define ACL_AS_IDX_OFFSET_MAX (32 * 1024)
-#define ACL_IMPLICIT_PRI (0)
-
-#define DPP_ACL_KEYSIZE_GET(key_mode) (2 * DPP_ETCAM_ENTRY_SIZE_GET(key_mode))
-#define DPP_ACL_ENTRY_WRMODE_GET(key_mode, entry_pos) \
-    ((((1U << (8U >> (key_mode))) - 1) << ((8U >> (key_mode)) * (entry_pos))) & 0xFF)
-
-#define DPP_ACL_AS_RSLT_INFO_GET(buff_base, index, size) \
-    (((ZXIC_UINT8 *)(buff_base) + (index) * (size)))
-
-#define MEM_OFF_NOT_NULL(type,member) \
-    (ZXIC_COMM_PTR_TO_VAL(&(((type*)4)->member)) - ZXIC_COMM_PTR_TO_VAL(((type*)4)))
-
-/*根据当前双链表的指针，找到本节点的指针*/
-#define GET_STRUCT_ENTRY_POINT(ptr, type, member) \
-    ((type *)(ZXIC_COMM_PTR_TO_VAL(ptr)-MEM_OFF_NOT_NULL(type,member)))
-
-static DPP_ACL_CFG_EX_T *g_p_acl_ex_cfg = NULL;
-
-/***********************************************************/
-/** 根据业务表总条目数计数需要的block数
-* @param   entry_num
-* @param   key_mode
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/12/23
-************************************************************/
-ZXIC_UINT32 dpp_acl_entrynum_to_blocknum(ZXIC_UINT32 entry_num, ZXIC_UINT32 key_mode)
-{
-    ZXIC_UINT32 value = 0;
-
-    ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(DPP_ETCAM_RAM_DEPTH, ((ZXIC_UINT32)1 << key_mode));
-    value = entry_num % (DPP_ETCAM_RAM_DEPTH * ((ZXIC_UINT32)1 << key_mode));
-
-    if (value == 0)
-    {
-        return (entry_num / (DPP_ETCAM_RAM_DEPTH * ((ZXIC_UINT32)1 << key_mode)));
-    }
-    else
-    {
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(entry_num / (DPP_ETCAM_RAM_DEPTH * ((ZXIC_UINT32)1 << key_mode)), 1);
-        return (entry_num / (DPP_ETCAM_RAM_DEPTH * ((ZXIC_UINT32)1 << key_mode)) + 1);
-    }
-}
-
-/***********************************************************/
-/** 优先级比较函数，用于显示优先级模式比较优先级
-* @param   p_new_key
-* @param   p_old_key
-* @param   key_len
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/12/24
-************************************************************/
-ZXIC_SINT32 dpp_acl_entry_pri_cmp(void *p_new_key, void *p_old_key, ZXIC_UINT32 key_len)
-{
-    if ((*(ZXIC_UINT32 *)p_new_key) > (*(ZXIC_UINT32 *)p_old_key))
-    {
-        return 1;
-    }
-    else if ((*(ZXIC_UINT32 *)p_new_key) < (*(ZXIC_UINT32 *)p_old_key))
-    {
-        return -1;
-    }
-
-    return 0;
-}
-
-/***********************************************************/
-/** 本地缓存acl键值比较，用于rb树回调
-* @param   p_new_key
-* @param   p_old_key
-* @param   key_len
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/12/23
-************************************************************/
-ZXIC_SINT32 dpp_acl_key_cmp(void *p_new_key, void *p_old_key, ZXIC_UINT32 key_len)
-{
-    ZXIC_COMM_CHECK_POINT(p_new_key);
-    ZXIC_COMM_CHECK_POINT(p_old_key);
-    /* 相同data+mask，但优先级不同，则为两个不同条目，因此软件需要比较pri+data+mask, handle不参与比较 */
-    ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_ASSERT(key_len, (ZXIC_UINT32)ZXIC_SIZEOF(ZXIC_UINT32));
-    return ZXIC_COMM_MEMCMP(&(((DPP_ACL_KEY_INFO_T *)p_new_key)->pri), &(((DPP_ACL_KEY_INFO_T *)p_old_key)->pri), key_len - ZXIC_SIZEOF(ZXIC_UINT32));
-}
-
-/***********************************************************/
-/** 根据业务条目索引计算写etcam硬件的地址
-* @param   p_tbl_cfg
-* @param   handle
-* @param   p_block_idx
-* @param   p_addr
-* @param   p_wr_mask
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/12/23
-************************************************************/
-DPP_STATUS dpp_acl_hdw_addr_get(DPP_ACL_TBL_CFG_T *p_tbl_cfg, ZXIC_UINT32 handle, ZXIC_UINT32 *p_block_idx, ZXIC_UINT32 *p_addr, ZXIC_UINT32 *p_wr_mask)
-{
-    ZXIC_UINT32 block_entry_num = 0;
-    ZXIC_UINT32 entry_pos = 0;
-    ZXIC_COMM_CHECK_POINT(p_tbl_cfg);
-    ZXIC_COMM_CHECK_POINT(p_block_idx);
-    ZXIC_COMM_CHECK_POINT(p_addr);
-    ZXIC_COMM_CHECK_POINT(p_wr_mask);
-
-    block_entry_num = DPP_ACL_ENTRY_MAX_GET(p_tbl_cfg->key_mode, 1);
-    *p_block_idx = p_tbl_cfg->block_array[handle / block_entry_num];
-    *p_addr = (handle % block_entry_num) / (1U << p_tbl_cfg->key_mode);
-    entry_pos = (handle % block_entry_num) % (1U << p_tbl_cfg->key_mode);
-    ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(entry_pos, 8);
-    *p_wr_mask = DPP_ACL_ENTRY_WRMODE_GET(p_tbl_cfg->key_mode, entry_pos);
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**
-* @param   p_tbl_cfg
-* @param   handle
-* @param   p_block_idx
-* @param   p_addr
-* @param   p_wr_mask
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2019/08/03
-************************************************************/
-DPP_STATUS dpp_acl_hdw_addr_get_ex(DPP_ACL_TBL_CFG_T *p_tbl_cfg, ZXIC_UINT32 handle, ZXIC_UINT32 *p_block_idx, ZXIC_UINT32 *p_addr, ZXIC_UINT32 *p_wr_mask)
-{
-    ZXIC_UINT32 block_entry_num = 0;
-    ZXIC_UINT32 entry_pos = 0;
-    DPP_STATUS rc = DPP_OK;
-
-    if (0 == (p_tbl_cfg && p_block_idx && p_addr && p_wr_mask))
-    {
-        ZXIC_COMM_TRACE_ERROR("\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", __FILE__, __LINE__, __FUNCTION__);
-        rc = ZXIC_PAR_CHK_POINT_NULL;
-        return rc;
-    }
-    block_entry_num = DPP_ACL_ENTRY_MAX_GET(p_tbl_cfg->key_mode, 1);
-    *p_block_idx = p_tbl_cfg->block_array[handle / block_entry_num];
-    *p_addr = (handle % block_entry_num) / (1U << p_tbl_cfg->key_mode);
-    entry_pos = (handle % block_entry_num) % (1U << p_tbl_cfg->key_mode);
-    ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(entry_pos, 8);
-    *p_wr_mask = DPP_ACL_ENTRY_WRMODE_GET(p_tbl_cfg->key_mode, entry_pos);
-    return rc;
-}
-
-/***********************************************************/
-/** acl重排写硬件回调函数
-* @param   old_index
-* @param   new_index
-* @param   p_cfg
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/12/23
-************************************************************/
-DPP_STATUS dpp_acl_entry_swap(ZXIC_UINT32 old_index, ZXIC_UINT32 new_index, ZXIC_VOID *p_cfg)
-{
-    DPP_STATUS rc = 0;
-    ZXIC_UINT32 block_idx = 0;
-    ZXIC_UINT32 ram_addr = 0;
-    ZXIC_UINT32 wr_mask = 0;
-    ZXIC_UINT8 *p_old_rslt_temp = NULL;
-    ZXIC_UINT8 *p_new_rslt_temp = NULL;
-    ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    DPP_ACL_CFG_T *p_acl_cfg = NULL;
-    DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL;
-    DPP_ACL_KEY_INFO_T *p_acl_key = NULL;
-    DPP_ETCAM_ENTRY_T etcam_entry = {0};
-
-    ZXIC_COMM_CHECK_POINT(p_cfg);
-
-    p_tbl_cfg = STRUCT_ENTRY_POINT(p_cfg, DPP_ACL_TBL_CFG_T, index_mng);
-    ZXIC_COMM_CHECK_INDEX(p_tbl_cfg->table_id, 0, DPP_ACL_TBL_ID_NUM - 1);    /* modify coverity yinxh 2021.03.10*/
-    p_acl_cfg = GET_STRUCT_ENTRY_POINT(p_tbl_cfg, DPP_ACL_CFG_T, acl_tbls[p_tbl_cfg->table_id]);
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(old_index, p_tbl_cfg->entry_num);    /* modify coverity yinxh 2021.03.10*/
-    p_acl_key = p_tbl_cfg->acl_key_buff[old_index];
-
-    etcam_entry.p_data = temp_data;
-    etcam_entry.p_mask = temp_mask;
-    etcam_entry.mode = p_tbl_cfg->key_mode;
-    ZXIC_COMM_CHECK_DEV_INDEX(p_acl_cfg->dev_id, p_tbl_cfg->key_mode, DPP_ACL_KEY_640b, DPP_ACL_KEY_INVALID - 1);    /* modify coverity yinxh 2021.03.10*/
-    ZXIC_COMM_MEMCPY(etcam_entry.p_data, p_acl_key->key, DPP_ETCAM_ENTRY_SIZE_GET(p_tbl_cfg->key_mode));
-    ZXIC_COMM_MEMCPY(etcam_entry.p_mask, p_acl_key->key + DPP_ETCAM_ENTRY_SIZE_GET(p_tbl_cfg->key_mode), DPP_ETCAM_ENTRY_SIZE_GET(p_tbl_cfg->key_mode));
-
-    /* update new as result */
-    if (p_tbl_cfg->as_enable)
-    {
-        /* eTcam result table as to eRam. */
-        ZXIC_COMM_CHECK_DEV_INDEX(p_acl_cfg->dev_id, p_tbl_cfg->as_mode, DPP_ACL_AS_MODE_16b, DPP_ACL_AS_MODE_INVALID - 1);
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(p_acl_cfg->dev_id, old_index, (2U << (p_tbl_cfg->as_mode)));
-        p_old_rslt_temp = DPP_ACL_AS_RSLT_INFO_GET(p_tbl_cfg->as_rslt_buff, old_index, DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode));
-        rc = p_acl_cfg->p_as_rslt_write_fun(p_acl_cfg->dev_id,
-                                            p_tbl_cfg->as_eRam_base + p_tbl_cfg->as_idx_base,
-                                            new_index,
-                                            p_tbl_cfg->as_mode,
-                                            p_old_rslt_temp);
-        ZXIC_COMM_CHECK_RC(rc, "acl_as_rslt_write_fun");
-
-        /* update result buffer */
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(p_acl_cfg->dev_id, new_index, 2U << p_tbl_cfg->as_mode);
-        p_new_rslt_temp = DPP_ACL_AS_RSLT_INFO_GET(p_tbl_cfg->as_rslt_buff, new_index, DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode));
-        ZXIC_COMM_MEMCPY(p_new_rslt_temp, p_old_rslt_temp, (ZXIC_UINT32)DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode));
-    }
-    else if (p_tbl_cfg->is_as_ddr)
-    {
-        /* eTcam result table as to DDR. */
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(p_acl_cfg->dev_id, old_index, 2U << p_tbl_cfg->as_mode);
-        p_old_rslt_temp = DPP_ACL_AS_RSLT_INFO_GET(p_tbl_cfg->as_rslt_buff, old_index, DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode));
-
-        rc = p_tbl_cfg->p_as_ddr_wr_fun(p_acl_cfg->dev_id,
-                                        p_tbl_cfg->tbl_type,
-                                        p_tbl_cfg->table_id,
-                                        p_tbl_cfg->dir_tbl_share_type,
-                                        p_tbl_cfg->ddr_baddr,
-                                        p_tbl_cfg->ddr_ecc_en,
-                                        p_tbl_cfg->idx_offset,
-                                        p_tbl_cfg->as_mode,
-                                        p_old_rslt_temp);
-        ZXIC_COMM_CHECK_RC(rc, "acl_as_ddr_rslt_writ_fun");
-
-        /* update result buffer */
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(p_acl_cfg->dev_id, new_index, 2U << p_tbl_cfg->as_mode);
-        p_new_rslt_temp = DPP_ACL_AS_RSLT_INFO_GET(p_tbl_cfg->as_rslt_buff, new_index, DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode));
-        ZXIC_COMM_MEMCPY(p_new_rslt_temp, p_old_rslt_temp, (ZXIC_UINT32)DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode));
-    }
-
-    /* add new entry */
-    rc = dpp_acl_hdw_addr_get_ex(p_tbl_cfg, new_index, &block_idx, &ram_addr, &wr_mask);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_acl_hdw_addr_get_ex");
-
-#ifdef DPP_FLOW_HW_INIT
-    rc = dpp_etcam_entry_add(p_acl_cfg->dev, ram_addr, block_idx, wr_mask, DPP_ETCAM_OPR_DM, &etcam_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_etcam_entry_add");
-#endif
-
-    /* delete old entry */
-    rc = dpp_acl_hdw_addr_get_ex(p_tbl_cfg, old_index, &block_idx, &ram_addr, &wr_mask);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_acl_hdw_addr_get_ex");
-
-#ifdef DPP_FLOW_HW_INIT
-    rc = dpp_etcam_entry_del(p_acl_cfg->dev, ram_addr, block_idx, wr_mask);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_etcam_entry_del");
-#endif
-
-    p_acl_key->handle = new_index;
-    p_tbl_cfg->acl_key_buff[new_index] = p_acl_key;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取ACL全局配置
-* @param   p_acl_cfg   ACL公共管理数据结构指针
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-************************************************************/
-DPP_STATUS dpp_acl_cfg_get(DPP_ACL_CFG_EX_T **p_acl_cfg)
-{
-    DPP_STATUS rc = 0;
-
-    if(NULL == g_p_acl_ex_cfg)
-    {
-        ZXIC_COMM_TRACE_ERROR("dpp_acl_cfg_get fail, etcam_is not init!\n");
-        ZXIC_COMM_ASSERT(0);
-        return DPP_ACL_RC_ETCAMID_NOT_INIT;
-    }
-
-    *p_acl_cfg = g_p_acl_ex_cfg;
-
-    return rc;
-}
-
-#if ZXIC_REAL("init_ex MUL_PRI")
-
-/***********************************************************/
-/**
-* @param   p_acl_cfg
-* @param   p_client
-* @param   flags
-* @param   p_as_wrt_fun
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wcl      @date  2015/12/29
-************************************************************/
-DPP_STATUS dpp_acl_cfg_init_ex(DPP_DEV_T *dev,
-                               DPP_ACL_CFG_EX_T *p_acl_cfg,
-                               ZXIC_VOID *p_client,
-                               ZXIC_UINT32 flags,
-                               ACL_AS_RSLT_WRT_FUNCTION p_as_wrt_fun)
-{
-    DPP_STATUS rc = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_acl_cfg);
-
-    ZXIC_COMM_MEMSET(p_acl_cfg, 0, ZXIC_SIZEOF(DPP_ACL_CFG_EX_T));
-
-    g_p_acl_ex_cfg = p_acl_cfg;
-
-    p_acl_cfg->p_client = p_client;
-    // p_acl_cfg->dev_id = (ZXIC_UINT32)(ZXIC_COMM_PTR_TO_VAL(p_acl_cfg->p_client) & 0xFFFFFFFF);
-    p_acl_cfg->dev_id = DEV_ID(dev);
-    p_acl_cfg->dev = dev;
-    p_acl_cfg->flags = flags;
-
-    if (flags & DPP_ACL_FLAG_ETCAM0_EN)
-    {
-        p_acl_cfg->acl_etcamids.is_valid = 1;
-
-        /*        if (flags & DPP_ACL_FLAG_ETCAM0_AS)*/
-        /*        {*/
-        /*            p_acl_cfg->acl_etcamids[0].as_enable    = 1;*/
-        p_acl_cfg->acl_etcamids.as_eRam_base = 0;
-        /*        }*/
-
-        rc = zxic_comm_double_link_init(DPP_ACL_TBL_ID_NUM, &(p_acl_cfg->acl_etcamids.tbl_list));
-        ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_init");
-    }
-
-    if (p_as_wrt_fun == NULL)
-    {
-        // p_acl_cfg->p_as_rslt_write_fun = dpp_acl_as_rslt_write;
-        // p_acl_cfg->p_as_rslt_read_fun = dpp_acl_as_rslt_read;
-    }
-    else
-    {
-        p_acl_cfg->p_as_rslt_write_fun = p_as_wrt_fun;
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** acl业务表初始化，注意分配给一个table的多个block_idx
-    必须按从小到大的顺序给定。支持多个优先级模式，暂不对外开放。
-* @param   p_acl_cfg
-* @param   table_id
-* @param   as_enable
-* @param   entry_num
-* @param   pri_mode
-* @param   key_mode
-* @param   as_mode
-* @param   block_num
-* @param   p_block_idx
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/12/23
-************************************************************/
-DPP_STATUS dpp_acl_tbl_init_ex(DPP_ACL_CFG_EX_T *p_acl_cfg,
-                               ZXIC_UINT32 table_id,
-                               ZXIC_UINT32 as_enable,
-                               ZXIC_UINT32 entry_num,
-                               DPP_ACL_PRI_MODE_E pri_mode,
-                               ZXIC_UINT32 key_mode,
-                               DPP_ACL_AS_MODE_E as_mode,
-                               ZXIC_UINT32 as_baddr,
-                               ZXIC_UINT32 block_num,
-                               ZXIC_UINT32 *p_block_idx)
-{
-    DPP_STATUS rc = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 acl_key_buff_size = 0;
-    /*    ZXIC_UINT32 as_idx_base = 0;*/
-
-    ZXIC_COMM_CHECK_POINT(p_acl_cfg);
-    ZXIC_COMM_CHECK_INDEX(table_id, DPP_ACL_TBL_ID_MIN, DPP_ACL_TBL_ID_MAX);
-    ZXIC_COMM_CHECK_INDEX(as_enable, 0, 1);
-    ZXIC_COMM_CHECK_INDEX(pri_mode, DPP_ACL_PRI_EXPLICIT, DPP_ACL_PRI_SPECIFY);
-    ZXIC_COMM_CHECK_INDEX(key_mode, DPP_ACL_KEY_640b, DPP_ACL_KEY_80b);
-    ZXIC_COMM_CHECK_INDEX(as_mode, DPP_ACL_AS_MODE_16b, DPP_ACL_AS_MODE_128b);
-    ZXIC_COMM_CHECK_INDEX(block_num, 0, DPP_ETCAM_BLOCK_NUM);
-    ZXIC_COMM_CHECK_POINT(p_block_idx);
-
-    g_p_acl_ex_cfg = p_acl_cfg;
-
-    if (p_acl_cfg->acl_tbls[table_id].is_used)
-    {
-        ZXIC_COMM_TRACE_ERROR("table_id[ %d ] is already used!\n", table_id);
-        ZXIC_COMM_ASSERT(0);
-        return DPP_ACL_RC_INVALID_TBLID;
-    }
-
-    if (!p_acl_cfg->acl_etcamids.is_valid)
-    {
-        ZXIC_COMM_TRACE_ERROR("etcam is not init!\n");
-        ZXIC_COMM_ASSERT(0);
-        return DPP_ACL_RC_ETCAMID_NOT_INIT;
-    }
-
-    if (dpp_acl_entrynum_to_blocknum(entry_num, key_mode) > block_num)
-    {
-        ZXIC_COMM_TRACE_ERROR("key_mode[ %d ], the etcam block_num[ %d ] is not enough for entry_num[ 0x%x ].\n",
-                             key_mode, block_num, entry_num);
-        ZXIC_COMM_ASSERT(0);
-        return DPP_ACL_RC_INVALID_BLOCKNUM;
-    }
-    else if (dpp_acl_entrynum_to_blocknum(entry_num, key_mode) < block_num)
-    {
-        ZXIC_COMM_TRACE_DEBUG("key_mode[ %d ], the etcam block_num[ %d ] is more than entry_num[ 0x%x ], better to reduce block_num in order to match with entry_num.\n",
-                             key_mode, block_num, entry_num);
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEBUG("key_mode[ %d ], the etcam block_num[ %d ] is match with entry_num[ 0x%x ].\n",
-                             key_mode, block_num, entry_num);
-    }
-
-    p_acl_cfg->acl_tbls[table_id].as_enable = as_enable;
-
-    /*
-        if ((!p_acl_cfg->acl_etcamids[etcam_id].as_enable && as_enable) ||
-            (p_acl_cfg->acl_etcamids[etcam_id].as_enable && !as_enable))
-        {
-             ZXIC_COMM_TRACE_ERROR( "tbl's as_enable is not according to ETCAM_id's.\n");
-            ZXIC_COMM_ASSERT(0);
-            return DPP_ACL_RC_INVALID_PARA;
-        }
-    */
-
-    if (as_enable)
-    {
-        p_acl_cfg->acl_tbls[table_id].as_idx_base = as_baddr;
-        p_acl_cfg->acl_tbls[table_id].as_rslt_buff = ZXIC_COMM_MALLOC(entry_num * DPP_ACL_AS_RSLT_SIZE_GET_EX(as_mode));
-        ZXIC_COMM_CHECK_POINT(p_acl_cfg->acl_tbls[table_id].as_rslt_buff);
-    }
-
-    if ((pri_mode == DPP_ACL_PRI_EXPLICIT) || (pri_mode == DPP_ACL_PRI_IMPLICIT))
-    {
-        rc = (DPP_STATUS)zxic_comm_indexfill_init(&(p_acl_cfg->acl_tbls[table_id].index_mng),
-                                            entry_num,
-                                            dpp_acl_entry_pri_cmp,
-                                            dpp_acl_entry_swap,
-                                            ZXIC_SIZEOF(ZXIC_UINT32));
-        ZXIC_COMM_CHECK_RC(rc, "zxic_comm_indexfill_init");
-
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(p_acl_cfg->dev_id, entry_num, (ZXIC_UINT32)ZXIC_SIZEOF(DPP_ACL_KEY_INFO_T *));
-        acl_key_buff_size = (entry_num * ZXIC_SIZEOF(DPP_ACL_KEY_INFO_T *)) & 0xffffffff;
-        p_acl_cfg->acl_tbls[table_id].acl_key_buff = (DPP_ACL_KEY_INFO_T **)ZXIC_COMM_MALLOC(acl_key_buff_size);
-        ZXIC_COMM_CHECK_POINT(p_acl_cfg->acl_tbls[table_id].acl_key_buff);
-    }
-
-    rc = (DPP_STATUS)zxic_comm_rb_init(&(p_acl_cfg->acl_tbls[table_id].acl_rb), 0, ZXIC_SIZEOF(DPP_ACL_KEY_INFO_T) + DPP_ACL_KEYSIZE_GET(key_mode), dpp_acl_key_cmp);
-    ZXIC_COMM_CHECK_RC(rc, "zxic_comm_rb_init");
-
-    p_acl_cfg->acl_tbls[table_id].table_id = table_id;
-    p_acl_cfg->acl_tbls[table_id].pri_mode = pri_mode;
-    p_acl_cfg->acl_tbls[table_id].key_mode = key_mode;
-    p_acl_cfg->acl_tbls[table_id].entry_num = entry_num;
-    p_acl_cfg->acl_tbls[table_id].as_mode = as_mode;
-    p_acl_cfg->acl_tbls[table_id].is_used = 1;
-
-    // ZXIC_COMM_TRACE_ERROR("p_acl_cfg->acl_tbls[%u].table_id [%d]\n", table_id, p_acl_cfg->acl_tbls[table_id].table_id);
-    // ZXIC_COMM_TRACE_ERROR("p_acl_cfg->acl_tbls[%u].pri_mode [%d]\n", table_id, p_acl_cfg->acl_tbls[table_id].pri_mode);
-    // ZXIC_COMM_TRACE_ERROR("p_acl_cfg->acl_tbls[%u].key_mode [%d]\n", table_id, p_acl_cfg->acl_tbls[table_id].key_mode);
-    // ZXIC_COMM_TRACE_ERROR("p_acl_cfg->acl_tbls[%u].entry_num [%d]\n", table_id, p_acl_cfg->acl_tbls[table_id].entry_num);
-    // ZXIC_COMM_TRACE_ERROR("p_acl_cfg->acl_tbls[%u].as_mode [%d]\n", table_id, p_acl_cfg->acl_tbls[table_id].as_mode);
-
-    INIT_D_NODE(&(p_acl_cfg->acl_tbls[table_id].entry_dn), &(p_acl_cfg->acl_tbls[table_id]));
-    rc = (DPP_STATUS)zxic_comm_double_link_insert_last(&(p_acl_cfg->acl_tbls[table_id].entry_dn), &(p_acl_cfg->acl_etcamids.tbl_list));
-    ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_insert_last");
-
-    p_acl_cfg->acl_tbls[table_id].block_num = block_num;
-    p_acl_cfg->acl_tbls[table_id].block_array = ZXIC_COMM_MALLOC(block_num * ZXIC_SIZEOF(ZXIC_UINT32));
-    ZXIC_COMM_CHECK_POINT(p_acl_cfg->acl_tbls[table_id].block_array);
-
-    for (i = 0; i < block_num; i++)
-    {
-        if (p_acl_cfg->acl_blocks[p_block_idx[i]].is_used)
-        {
-            ZXIC_COMM_TRACE_ERROR("the block[ %d ] is already used by table[ %d ]!\n", p_block_idx[i], p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id);
-            ZXIC_COMM_ASSERT(0);
-            return DPP_ACL_RC_INVALID_BLOCKID;
-        }
-
-        p_acl_cfg->acl_tbls[table_id].block_array[i] = p_block_idx[i];
-        p_acl_cfg->acl_blocks[p_block_idx[i]].is_used = 1;
-        p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id = table_id;
-        p_acl_cfg->acl_blocks[p_block_idx[i]].idx_base = ((DPP_ACL_ENTRY_MAX_GET(key_mode, i)) >> BLOCK_IDXBASE_BIT_OFF) & BLOCK_IDXBASE_BIT_MASK;
-
-#ifdef DPP_FLOW_HW_INIT
-        /* cfg block table_id */
-        rc = dpp_etcam_block_tbl_id_set(p_acl_cfg->dev, p_block_idx[i], table_id);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_etcam_block_tbl_id_set");
-
-        /* cfg block base_addr */
-        rc = dpp_etcam_block_baddr_set(p_acl_cfg->dev, p_block_idx[i], p_acl_cfg->acl_blocks[p_block_idx[i]].idx_base);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_etcam_block_baddr_set");
-#endif
-
-    }
-
-    return DPP_OK;
-}
-
-DPP_STATUS dpp_acl_res_destroy(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 table_id = 0;
-    ZXIC_UINT32 as_enable = 0;
-    ZXIC_UINT32 pri_mode = 0;
-    DPP_ACL_CFG_EX_T *p_acl_cfg = NULL;
-    DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL;
-
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-
-    rc = dpp_acl_cfg_get(&p_acl_cfg);//获取ACL表资源配置
-    ZXIC_COMM_CHECK_POINT(p_acl_cfg);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_acl_cfg_get");
-
-    if(!p_acl_cfg->acl_etcamids.is_valid)
-    {
-        ZXIC_COMM_TRACE_ERROR("etcam is not init!\n");
-        return DPP_ACL_RC_ETCAMID_NOT_INIT;
-    }
-
-    for(table_id=DPP_ACL_TBL_ID_MIN;table_id<=DPP_ACL_TBL_ID_MAX;table_id++)
-    {
-        p_tbl_cfg = p_acl_cfg->acl_tbls + table_id;
-        if (!p_tbl_cfg->is_used)
-        {
-            ZXIC_COMM_TRACE_DEBUG("table_id[ %d ] is not used!\n", table_id);
-            continue;
-        }
-
-        rc = (DPP_STATUS)zxic_comm_rb_destroy(&(p_tbl_cfg->acl_rb));
-        ZXIC_COMM_CHECK_RC(rc, "zxic_comm_rb_destroy");
-
-        rc = zxic_comm_indexfill_destroy(&(p_tbl_cfg->index_mng));
-        ZXIC_COMM_CHECK_RC(rc, "zxic_comm_indexfill_destroy");
-        
-        as_enable = p_tbl_cfg->as_enable;
-        if(as_enable)
-        {
-            if(p_tbl_cfg->as_rslt_buff)
-            {
-                ZXIC_COMM_FREE(p_tbl_cfg->as_rslt_buff);
-                p_tbl_cfg->as_rslt_buff = NULL;
-            }
-        }
-
-        pri_mode = p_tbl_cfg->pri_mode;
-        if ((pri_mode == DPP_ACL_PRI_EXPLICIT) || (pri_mode == DPP_ACL_PRI_IMPLICIT))
-        {
-            if(p_tbl_cfg->acl_key_buff)
-            {
-                ZXIC_COMM_FREE(p_tbl_cfg->acl_key_buff);
-                p_tbl_cfg->acl_key_buff = NULL;
-            }
-        }
-
-        if(p_tbl_cfg->block_array)
-        {
-            ZXIC_COMM_FREE(p_tbl_cfg->block_array);
-            p_tbl_cfg->block_array = NULL;
-        }
-    }
-
-    return DPP_OK;
-}
-
-#endif
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_acl.c
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2014/12/17
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#include "zxic_common.h"
+
+#include "dpp_dev.h"
+#include "dpp_acl.h"
+#include "dpp_etcam.h"
+#include "dpp_se.h"
+#include "dpp_se_reg.h"
+#include "dpp_reg_api.h"
+#include "dpp_reg_info.h"
+
+#define BLOCK_IDXBASE_BIT_OFF (9)
+#define BLOCK_IDXBASE_BIT_MASK (0x7f)
+#define ACL_AS_IDX_OFFSET_MAX (32 * 1024)
+#define ACL_IMPLICIT_PRI (0)
+
+#define DPP_ACL_KEYSIZE_GET(key_mode) (2 * DPP_ETCAM_ENTRY_SIZE_GET(key_mode))
+#define DPP_ACL_ENTRY_WRMODE_GET(key_mode, entry_pos) \
+	((((1U << (8U >> (key_mode))) - 1)                \
+	  << ((8U >> (key_mode)) * (entry_pos))) &        \
+	 0xFF)
+
+#define DPP_ACL_AS_RSLT_INFO_GET(buff_base, index, size) \
+	(((ZXIC_UINT8 *)(buff_base) + (index) * (size)))
+
+#define MEM_OFF_NOT_NULL(type, member)              \
+	(ZXIC_COMM_PTR_TO_VAL(&(((type *)4)->member)) - \
+	 ZXIC_COMM_PTR_TO_VAL(((type *)4)))
+
+/*根据当前双链表的指针，找到本节点的指针*/
+#define GET_STRUCT_ENTRY_POINT(ptr, type, member) \
+	((type *)(ZXIC_COMM_PTR_TO_VAL(ptr) - MEM_OFF_NOT_NULL(type, member)))
+
+static DPP_ACL_CFG_EX_T *g_p_acl_ex_cfg;
+
+/***********************************************************/
+/** 根据业务表总条目数计数需要的block数
+ * @param   entry_num
+ * @param   key_mode
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/12/23
+ ************************************************************/
+ZXIC_UINT32 dpp_acl_entrynum_to_blocknum(ZXIC_UINT32 entry_num,
+										 ZXIC_UINT32 key_mode)
+{
+	ZXIC_UINT32 value = 0;
+
+	ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(DPP_ETCAM_RAM_DEPTH,
+												 ((ZXIC_UINT32)1 << key_mode));
+	value = entry_num % (DPP_ETCAM_RAM_DEPTH * ((ZXIC_UINT32)1 << key_mode));
+
+	if (value == 0) {
+		return (entry_num /
+				(DPP_ETCAM_RAM_DEPTH * ((ZXIC_UINT32)1 << key_mode)));
+	} else {
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(
+				entry_num /
+						(DPP_ETCAM_RAM_DEPTH * ((ZXIC_UINT32)1 << key_mode)),
+				1);
+		return (entry_num /
+						(DPP_ETCAM_RAM_DEPTH * ((ZXIC_UINT32)1 << key_mode)) +
+				1);
+	}
+}
+
+/***********************************************************/
+/** 优先级比较函数，用于显示优先级模式比较优先级
+ * @param   p_new_key
+ * @param   p_old_key
+ * @param   key_len
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/12/24
+ ************************************************************/
+ZXIC_SINT32 dpp_acl_entry_pri_cmp(void *p_new_key, void *p_old_key,
+								  ZXIC_UINT32 key_len)
+{
+	if ((*(ZXIC_UINT32 *)p_new_key) > (*(ZXIC_UINT32 *)p_old_key)) {
+		return 1;
+	} else if ((*(ZXIC_UINT32 *)p_new_key) < (*(ZXIC_UINT32 *)p_old_key)) {
+		return -1;
+	}
+
+	return 0;
+}
+
+/***********************************************************/
+/** 本地缓存acl键值比较，用于rb树回调
+ * @param   p_new_key
+ * @param   p_old_key
+ * @param   key_len
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/12/23
+ ************************************************************/
+ZXIC_SINT32 dpp_acl_key_cmp(void *p_new_key, void *p_old_key,
+							ZXIC_UINT32 key_len)
+{
+	ZXIC_COMM_CHECK_POINT(p_new_key);
+	ZXIC_COMM_CHECK_POINT(p_old_key);
+	/* 相同data+mask，但优先级不同，则为两个不同条目，因此软件需要比较pri+data+mask, handle不参与比较 */
+	ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW_NO_ASSERT(key_len,
+												 ZXIC_SIZEOF(ZXIC_UINT32));
+	return ZXIC_COMM_MEMCMP(&(((DPP_ACL_KEY_INFO_T *)p_new_key)->pri),
+							&(((DPP_ACL_KEY_INFO_T *)p_old_key)->pri),
+							key_len - ZXIC_SIZEOF(ZXIC_UINT32));
+}
+
+/***********************************************************/
+/** 根据业务条目索引计算写etcam硬件的地址
+ * @param   p_tbl_cfg
+ * @param   handle
+ * @param   p_block_idx
+ * @param   p_addr
+ * @param   p_wr_mask
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/12/23
+ ************************************************************/
+DPP_STATUS dpp_acl_hdw_addr_get(DPP_ACL_TBL_CFG_T *p_tbl_cfg,
+								ZXIC_UINT32 handle, ZXIC_UINT32 *p_block_idx,
+								ZXIC_UINT32 *p_addr, ZXIC_UINT32 *p_wr_mask)
+{
+	ZXIC_UINT32 block_entry_num = 0;
+	ZXIC_UINT32 entry_pos = 0;
+	ZXIC_COMM_CHECK_POINT(p_tbl_cfg);
+	ZXIC_COMM_CHECK_POINT(p_block_idx);
+	ZXIC_COMM_CHECK_POINT(p_addr);
+	ZXIC_COMM_CHECK_POINT(p_wr_mask);
+
+	block_entry_num = DPP_ACL_ENTRY_MAX_GET(p_tbl_cfg->key_mode, 1);
+	*p_block_idx = p_tbl_cfg->block_array[handle / block_entry_num];
+	*p_addr = (handle % block_entry_num) / (1U << p_tbl_cfg->key_mode);
+	entry_pos = (handle % block_entry_num) % (1U << p_tbl_cfg->key_mode);
+	ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(entry_pos, 8);
+	*p_wr_mask = DPP_ACL_ENTRY_WRMODE_GET(p_tbl_cfg->key_mode, entry_pos);
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**
+ * @param   p_tbl_cfg
+ * @param   handle
+ * @param   p_block_idx
+ * @param   p_addr
+ * @param   p_wr_mask
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XXX      @date  2019/08/03
+ ************************************************************/
+DPP_STATUS dpp_acl_hdw_addr_get_ex(DPP_ACL_TBL_CFG_T *p_tbl_cfg,
+								   ZXIC_UINT32 handle, ZXIC_UINT32 *p_block_idx,
+								   ZXIC_UINT32 *p_addr, ZXIC_UINT32 *p_wr_mask)
+{
+	ZXIC_UINT32 block_entry_num = 0;
+	ZXIC_UINT32 entry_pos = 0;
+	DPP_STATUS rc = DPP_OK;
+
+	if (0 == (p_tbl_cfg && p_block_idx && p_addr && p_wr_mask)) {
+		ZXIC_COMM_TRACE_ERROR(
+				"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", __FILE__,
+				__LINE__, __FUNCTION__);
+		rc = ZXIC_PAR_CHK_POINT_NULL;
+		return rc;
+	}
+	block_entry_num = DPP_ACL_ENTRY_MAX_GET(p_tbl_cfg->key_mode, 1);
+	*p_block_idx = p_tbl_cfg->block_array[handle / block_entry_num];
+	*p_addr = (handle % block_entry_num) / (1U << p_tbl_cfg->key_mode);
+	entry_pos = (handle % block_entry_num) % (1U << p_tbl_cfg->key_mode);
+	ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(entry_pos, 8);
+	*p_wr_mask = DPP_ACL_ENTRY_WRMODE_GET(p_tbl_cfg->key_mode, entry_pos);
+	return rc;
+}
+
+/***********************************************************/
+/** acl重排写硬件回调函数
+ * @param   old_index
+ * @param   new_index
+ * @param   p_cfg
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/12/23
+ ************************************************************/
+DPP_STATUS dpp_acl_entry_swap(ZXIC_UINT32 old_index, ZXIC_UINT32 new_index,
+							  ZXIC_VOID *p_cfg)
+{
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 block_idx = 0;
+	ZXIC_UINT32 ram_addr = 0;
+	ZXIC_UINT32 wr_mask = 0;
+	ZXIC_UINT8 *p_old_rslt_temp = NULL;
+	ZXIC_UINT8 *p_new_rslt_temp = NULL;
+	ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	DPP_ACL_CFG_T *p_acl_cfg = NULL;
+	DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL;
+	DPP_ACL_KEY_INFO_T *p_acl_key = NULL;
+	DPP_ETCAM_ENTRY_T etcam_entry = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(p_cfg);
+
+	p_tbl_cfg = STRUCT_ENTRY_POINT(p_cfg, DPP_ACL_TBL_CFG_T, index_mng);
+	ZXIC_COMM_CHECK_INDEX(p_tbl_cfg->table_id, 0,
+						  DPP_ACL_TBL_ID_NUM -
+								  1); /* modify coverity yinxh 2021.03.10*/
+	p_acl_cfg = GET_STRUCT_ENTRY_POINT(p_tbl_cfg, DPP_ACL_CFG_T,
+									   acl_tbls[p_tbl_cfg->table_id]);
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(
+			old_index,
+			p_tbl_cfg->entry_num); /* modify coverity yinxh 2021.03.10*/
+	p_acl_key = p_tbl_cfg->acl_key_buff[old_index];
+
+	etcam_entry.p_data = temp_data;
+	etcam_entry.p_mask = temp_mask;
+	etcam_entry.mode = p_tbl_cfg->key_mode;
+	ZXIC_COMM_CHECK_DEV_INDEX(
+			p_acl_cfg->dev_id, p_tbl_cfg->key_mode, DPP_ACL_KEY_640b,
+			DPP_ACL_KEY_INVALID - 1); /* modify coverity yinxh 2021.03.10*/
+	ZXIC_COMM_MEMCPY(etcam_entry.p_data, p_acl_key->key,
+					 DPP_ETCAM_ENTRY_SIZE_GET(p_tbl_cfg->key_mode));
+	ZXIC_COMM_MEMCPY(etcam_entry.p_mask,
+					 p_acl_key->key +
+							 DPP_ETCAM_ENTRY_SIZE_GET(p_tbl_cfg->key_mode),
+					 DPP_ETCAM_ENTRY_SIZE_GET(p_tbl_cfg->key_mode));
+
+	/* update new as result */
+	if (p_tbl_cfg->as_enable) {
+		/* eTcam result table as to eRam. */
+		ZXIC_COMM_CHECK_DEV_INDEX(p_acl_cfg->dev_id, p_tbl_cfg->as_mode,
+								  DPP_ACL_AS_MODE_16b,
+								  DPP_ACL_AS_MODE_INVALID - 1);
+		ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(
+				p_acl_cfg->dev_id, old_index, (2U << (p_tbl_cfg->as_mode)));
+		p_old_rslt_temp = DPP_ACL_AS_RSLT_INFO_GET(
+				p_tbl_cfg->as_rslt_buff, old_index,
+				DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode));
+		rc = p_acl_cfg->p_as_rslt_write_fun(
+				p_acl_cfg->dev_id,
+				p_tbl_cfg->as_eRam_base + p_tbl_cfg->as_idx_base, new_index,
+				p_tbl_cfg->as_mode, p_old_rslt_temp);
+		ZXIC_COMM_CHECK_RC(rc, "acl_as_rslt_write_fun");
+
+		/* update result buffer */
+		ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(
+				p_acl_cfg->dev_id, new_index, 2U << p_tbl_cfg->as_mode);
+		p_new_rslt_temp = DPP_ACL_AS_RSLT_INFO_GET(
+				p_tbl_cfg->as_rslt_buff, new_index,
+				DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode));
+		ZXIC_COMM_MEMCPY(
+				p_new_rslt_temp, p_old_rslt_temp,
+				(ZXIC_UINT32)DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode));
+	} else if (p_tbl_cfg->is_as_ddr) {
+		/* eTcam result table as to DDR. */
+		ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(
+				p_acl_cfg->dev_id, old_index, 2U << p_tbl_cfg->as_mode);
+		p_old_rslt_temp = DPP_ACL_AS_RSLT_INFO_GET(
+				p_tbl_cfg->as_rslt_buff, old_index,
+				DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode));
+
+		rc = p_tbl_cfg->p_as_ddr_wr_fun(
+				p_acl_cfg->dev_id, p_tbl_cfg->tbl_type, p_tbl_cfg->table_id,
+				p_tbl_cfg->dir_tbl_share_type, p_tbl_cfg->ddr_baddr,
+				p_tbl_cfg->ddr_ecc_en, p_tbl_cfg->idx_offset,
+				p_tbl_cfg->as_mode, p_old_rslt_temp);
+		ZXIC_COMM_CHECK_RC(rc, "acl_as_ddr_rslt_writ_fun");
+
+		/* update result buffer */
+		ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(
+				p_acl_cfg->dev_id, new_index, 2U << p_tbl_cfg->as_mode);
+		p_new_rslt_temp = DPP_ACL_AS_RSLT_INFO_GET(
+				p_tbl_cfg->as_rslt_buff, new_index,
+				DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode));
+		ZXIC_COMM_MEMCPY(
+				p_new_rslt_temp, p_old_rslt_temp,
+				(ZXIC_UINT32)DPP_ACL_AS_RSLT_SIZE_GET_EX(p_tbl_cfg->as_mode));
+	}
+
+	/* add new entry */
+	rc = dpp_acl_hdw_addr_get_ex(p_tbl_cfg, new_index, &block_idx, &ram_addr,
+								 &wr_mask);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_acl_hdw_addr_get_ex");
+
+#ifdef DPP_FLOW_HW_INIT
+	rc = dpp_etcam_entry_add(p_acl_cfg->dev, ram_addr, block_idx, wr_mask,
+							 DPP_ETCAM_OPR_DM, &etcam_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_etcam_entry_add");
+#endif
+
+	/* delete old entry */
+	rc = dpp_acl_hdw_addr_get_ex(p_tbl_cfg, old_index, &block_idx, &ram_addr,
+								 &wr_mask);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_acl_hdw_addr_get_ex");
+
+#ifdef DPP_FLOW_HW_INIT
+	rc = dpp_etcam_entry_del(p_acl_cfg->dev, ram_addr, block_idx, wr_mask);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_etcam_entry_del");
+#endif
+
+	p_acl_key->handle = new_index;
+	p_tbl_cfg->acl_key_buff[new_index] = p_acl_key;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取ACL全局配置
+ * @param   p_acl_cfg   ACL公共管理数据结构指针
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ ************************************************************/
+DPP_STATUS dpp_acl_cfg_get(DPP_ACL_CFG_EX_T **p_acl_cfg)
+{
+	DPP_STATUS rc = 0;
+
+	if (NULL == g_p_acl_ex_cfg) {
+		ZXIC_COMM_TRACE_ERROR("dpp_acl_cfg_get fail, etcam_is not init!\n");
+		ZXIC_COMM_ASSERT(0);
+		return DPP_ACL_RC_ETCAMID_NOT_INIT;
+	}
+
+	*p_acl_cfg = g_p_acl_ex_cfg;
+
+	return rc;
+}
+
+#if ZXIC_REAL("init_ex MUL_PRI")
+
+/***********************************************************/
+/**
+ * @param   p_acl_cfg
+ * @param   p_client
+ * @param   flags
+ * @param   p_as_wrt_fun
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/12/29
+ ************************************************************/
+DPP_STATUS dpp_acl_cfg_init_ex(DPP_DEV_T *dev, DPP_ACL_CFG_EX_T *p_acl_cfg,
+							   ZXIC_VOID *p_client, ZXIC_UINT32 flags,
+							   ACL_AS_RSLT_WRT_FUNCTION p_as_wrt_fun)
+{
+	DPP_STATUS rc = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_acl_cfg);
+
+	ZXIC_COMM_MEMSET(p_acl_cfg, 0, ZXIC_SIZEOF(DPP_ACL_CFG_EX_T));
+
+	g_p_acl_ex_cfg = p_acl_cfg;
+
+	p_acl_cfg->p_client = p_client;
+	// p_acl_cfg->dev_id = (ZXIC_UINT32)(ZXIC_COMM_PTR_TO_VAL(p_acl_cfg->p_client) & 0xFFFFFFFF);
+	p_acl_cfg->dev_id = DEV_ID(dev);
+	p_acl_cfg->dev = dev;
+	p_acl_cfg->flags = flags;
+
+	if (flags & DPP_ACL_FLAG_ETCAM0_EN) {
+		p_acl_cfg->acl_etcamids.is_valid = 1;
+
+		/*        if (flags & DPP_ACL_FLAG_ETCAM0_AS)*/
+		/*        {*/
+		/*            p_acl_cfg->acl_etcamids[0].as_enable    = 1;*/
+		p_acl_cfg->acl_etcamids.as_eRam_base = 0;
+		/*        }*/
+
+		rc = zxic_comm_double_link_init(DPP_ACL_TBL_ID_NUM,
+										&(p_acl_cfg->acl_etcamids.tbl_list));
+		ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_init");
+	}
+
+	if (p_as_wrt_fun == NULL) {
+		// p_acl_cfg->p_as_rslt_write_fun = dpp_acl_as_rslt_write;
+		// p_acl_cfg->p_as_rslt_read_fun = dpp_acl_as_rslt_read;
+	} else {
+		p_acl_cfg->p_as_rslt_write_fun = p_as_wrt_fun;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** acl业务表初始化，注意分配给一个table的多个block_idx
+    必须按从小到大的顺序给定。支持多个优先级模式，暂不对外开放。
+* @param   p_acl_cfg
+* @param   table_id
+* @param   as_enable
+* @param   entry_num
+* @param   pri_mode
+* @param   key_mode
+* @param   as_mode
+* @param   block_num
+* @param   p_block_idx
+*
+* @return
+* @remark  无
+* @see
+* @author  王春雷      @date  2014/12/23
+************************************************************/
+DPP_STATUS dpp_acl_tbl_init_ex(DPP_ACL_CFG_EX_T *p_acl_cfg,
+							   ZXIC_UINT32 table_id, ZXIC_UINT32 as_enable,
+							   ZXIC_UINT32 entry_num,
+							   DPP_ACL_PRI_MODE_E pri_mode,
+							   ZXIC_UINT32 key_mode, DPP_ACL_AS_MODE_E as_mode,
+							   ZXIC_UINT32 as_baddr, ZXIC_UINT32 block_num,
+							   ZXIC_UINT32 *p_block_idx)
+{
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 acl_key_buff_size = 0;
+	/*    ZXIC_UINT32 as_idx_base = 0;*/
+
+	ZXIC_COMM_CHECK_POINT(p_acl_cfg);
+	ZXIC_COMM_CHECK_INDEX(table_id, DPP_ACL_TBL_ID_MIN, DPP_ACL_TBL_ID_MAX);
+	ZXIC_COMM_CHECK_INDEX(as_enable, 0, 1);
+	ZXIC_COMM_CHECK_INDEX(pri_mode, DPP_ACL_PRI_EXPLICIT, DPP_ACL_PRI_SPECIFY);
+	ZXIC_COMM_CHECK_INDEX(key_mode, DPP_ACL_KEY_640b, DPP_ACL_KEY_80b);
+	ZXIC_COMM_CHECK_INDEX(as_mode, DPP_ACL_AS_MODE_16b, DPP_ACL_AS_MODE_128b);
+	ZXIC_COMM_CHECK_INDEX(block_num, 0, DPP_ETCAM_BLOCK_NUM);
+	ZXIC_COMM_CHECK_POINT(p_block_idx);
+
+	g_p_acl_ex_cfg = p_acl_cfg;
+
+	if (p_acl_cfg->acl_tbls[table_id].is_used) {
+		ZXIC_COMM_TRACE_ERROR("table_id[ %d ] is already used!\n", table_id);
+		ZXIC_COMM_ASSERT(0);
+		return DPP_ACL_RC_INVALID_TBLID;
+	}
+
+	if (!p_acl_cfg->acl_etcamids.is_valid) {
+		ZXIC_COMM_TRACE_ERROR("etcam is not init!\n");
+		ZXIC_COMM_ASSERT(0);
+		return DPP_ACL_RC_ETCAMID_NOT_INIT;
+	}
+
+	if (dpp_acl_entrynum_to_blocknum(entry_num, key_mode) > block_num) {
+		ZXIC_COMM_TRACE_ERROR(
+				"key_mode[ %d ], the etcam block_num[ %d ] is not enough for entry_num[ 0x%x ].\n",
+				key_mode, block_num, entry_num);
+		ZXIC_COMM_ASSERT(0);
+		return DPP_ACL_RC_INVALID_BLOCKNUM;
+	} else if (dpp_acl_entrynum_to_blocknum(entry_num, key_mode) < block_num) {
+		ZXIC_COMM_TRACE_DEBUG(
+				"key_mode[ %d ], the etcam block_num[ %d ] is more than entry_num[ 0x%x ], better to "
+				"reduce block_num in order to match with entry_num.\n",
+				key_mode, block_num, entry_num);
+	} else {
+		ZXIC_COMM_TRACE_DEBUG(
+				"key_mode[ %d ], the etcam block_num[ %d ] is match with entry_num[ 0x%x ].\n",
+				key_mode, block_num, entry_num);
+	}
+
+	p_acl_cfg->acl_tbls[table_id].as_enable = as_enable;
+
+	if (as_enable) {
+		p_acl_cfg->acl_tbls[table_id].as_idx_base = as_baddr;
+		p_acl_cfg->acl_tbls[table_id].as_rslt_buff = ZXIC_COMM_MALLOC(
+				entry_num * DPP_ACL_AS_RSLT_SIZE_GET_EX(as_mode));
+		ZXIC_COMM_CHECK_POINT(p_acl_cfg->acl_tbls[table_id].as_rslt_buff);
+	}
+
+	if ((pri_mode == DPP_ACL_PRI_EXPLICIT) ||
+		(pri_mode == DPP_ACL_PRI_IMPLICIT)) {
+		rc = (DPP_STATUS)zxic_comm_indexfill_init(
+				&(p_acl_cfg->acl_tbls[table_id].index_mng), entry_num,
+				dpp_acl_entry_pri_cmp, dpp_acl_entry_swap,
+				ZXIC_SIZEOF(ZXIC_UINT32));
+		ZXIC_COMM_CHECK_RC(rc, "zxic_comm_indexfill_init");
+
+		ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(
+				p_acl_cfg->dev_id, entry_num,
+				ZXIC_SIZEOF(DPP_ACL_KEY_INFO_T *));
+		acl_key_buff_size = (entry_num * ZXIC_SIZEOF(DPP_ACL_KEY_INFO_T *)) &
+							0xffffffff;
+		p_acl_cfg->acl_tbls[table_id].acl_key_buff =
+				(DPP_ACL_KEY_INFO_T **)ZXIC_COMM_MALLOC(acl_key_buff_size);
+		ZXIC_COMM_CHECK_POINT(p_acl_cfg->acl_tbls[table_id].acl_key_buff);
+	}
+
+	rc = (DPP_STATUS)zxic_comm_rb_init(
+			&(p_acl_cfg->acl_tbls[table_id].acl_rb), 0,
+			ZXIC_SIZEOF(DPP_ACL_KEY_INFO_T) + DPP_ACL_KEYSIZE_GET(key_mode),
+			dpp_acl_key_cmp);
+	ZXIC_COMM_CHECK_RC(rc, "zxic_comm_rb_init");
+
+	p_acl_cfg->acl_tbls[table_id].table_id = table_id;
+	p_acl_cfg->acl_tbls[table_id].pri_mode = pri_mode;
+	p_acl_cfg->acl_tbls[table_id].key_mode = key_mode;
+	p_acl_cfg->acl_tbls[table_id].entry_num = entry_num;
+	p_acl_cfg->acl_tbls[table_id].as_mode = as_mode;
+	p_acl_cfg->acl_tbls[table_id].is_used = 1;
+
+	// ZXIC_COMM_TRACE_ERROR("p_acl_cfg->acl_tbls[%u].table_id [%d]\n", table_id,
+	// p_acl_cfg->acl_tbls[table_id].table_id); ZXIC_COMM_TRACE_ERROR("p_acl_cfg->acl_tbls[%u].pri_mode [%d]\n",
+	// table_id, p_acl_cfg->acl_tbls[table_id].pri_mode); ZXIC_COMM_TRACE_ERROR("p_acl_cfg->acl_tbls[%u].key_mode
+	// [%d]\n", table_id, p_acl_cfg->acl_tbls[table_id].key_mode);
+	// ZXIC_COMM_TRACE_ERROR("p_acl_cfg->acl_tbls[%u].entry_num [%d]\n", table_id,
+	// p_acl_cfg->acl_tbls[table_id].entry_num); ZXIC_COMM_TRACE_ERROR("p_acl_cfg->acl_tbls[%u].as_mode [%d]\n",
+	// table_id, p_acl_cfg->acl_tbls[table_id].as_mode);
+
+	INIT_D_NODE(&(p_acl_cfg->acl_tbls[table_id].entry_dn),
+				&(p_acl_cfg->acl_tbls[table_id]));
+	rc = (DPP_STATUS)zxic_comm_double_link_insert_last(
+			&(p_acl_cfg->acl_tbls[table_id].entry_dn),
+			&(p_acl_cfg->acl_etcamids.tbl_list));
+	ZXIC_COMM_CHECK_RC(rc, "zxic_comm_double_link_insert_last");
+
+	p_acl_cfg->acl_tbls[table_id].block_num = block_num;
+	p_acl_cfg->acl_tbls[table_id].block_array =
+			ZXIC_COMM_MALLOC(block_num * ZXIC_SIZEOF(ZXIC_UINT32));
+	ZXIC_COMM_CHECK_POINT(p_acl_cfg->acl_tbls[table_id].block_array);
+
+	for (i = 0; i < block_num; i++) {
+		if (p_acl_cfg->acl_blocks[p_block_idx[i]].is_used) {
+			ZXIC_COMM_TRACE_ERROR(
+					"the block[ %d ] is already used by table[ %d ]!\n",
+					p_block_idx[i],
+					p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id);
+			ZXIC_COMM_ASSERT(0);
+			return DPP_ACL_RC_INVALID_BLOCKID;
+		}
+
+		p_acl_cfg->acl_tbls[table_id].block_array[i] = p_block_idx[i];
+		p_acl_cfg->acl_blocks[p_block_idx[i]].is_used = 1;
+		p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id = table_id;
+		p_acl_cfg->acl_blocks[p_block_idx[i]].idx_base =
+				((DPP_ACL_ENTRY_MAX_GET(key_mode, i)) >>
+				 BLOCK_IDXBASE_BIT_OFF) &
+				BLOCK_IDXBASE_BIT_MASK;
+
+#ifdef DPP_FLOW_HW_INIT
+		/* cfg block table_id */
+		rc = dpp_etcam_block_tbl_id_set(p_acl_cfg->dev, p_block_idx[i],
+										table_id);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_etcam_block_tbl_id_set");
+
+		/* cfg block base_addr */
+		rc = dpp_etcam_block_baddr_set(
+				p_acl_cfg->dev, p_block_idx[i],
+				p_acl_cfg->acl_blocks[p_block_idx[i]].idx_base);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_etcam_block_baddr_set");
+#endif
+	}
+
+	return DPP_OK;
+}
+
+DPP_STATUS dpp_acl_res_destroy(ZXIC_UINT32 dev_id)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 table_id = 0;
+	ZXIC_UINT32 as_enable = 0;
+	ZXIC_UINT32 pri_mode = 0;
+	DPP_ACL_CFG_EX_T *p_acl_cfg = NULL;
+	DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL;
+
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+
+	rc = dpp_acl_cfg_get(&p_acl_cfg); //获取ACL表资源配置
+	ZXIC_COMM_CHECK_POINT(p_acl_cfg);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_acl_cfg_get");
+
+	if (!p_acl_cfg->acl_etcamids.is_valid) {
+		ZXIC_COMM_TRACE_ERROR("etcam is not init!\n");
+		return DPP_ACL_RC_ETCAMID_NOT_INIT;
+	}
+
+	for (table_id = DPP_ACL_TBL_ID_MIN; table_id <= DPP_ACL_TBL_ID_MAX;
+		 table_id++) {
+		p_tbl_cfg = p_acl_cfg->acl_tbls + table_id;
+		if (!p_tbl_cfg->is_used) {
+			ZXIC_COMM_TRACE_DEBUG("table_id[ %d ] is not used!\n", table_id);
+			continue;
+		}
+
+		rc = (DPP_STATUS)zxic_comm_rb_destroy(&(p_tbl_cfg->acl_rb));
+		ZXIC_COMM_CHECK_RC(rc, "zxic_comm_rb_destroy");
+
+		rc = zxic_comm_indexfill_destroy(&(p_tbl_cfg->index_mng));
+		ZXIC_COMM_CHECK_RC(rc, "zxic_comm_indexfill_destroy");
+
+		as_enable = p_tbl_cfg->as_enable;
+		if (as_enable) {
+			if (p_tbl_cfg->as_rslt_buff) {
+				ZXIC_COMM_FREE(p_tbl_cfg->as_rslt_buff);
+				p_tbl_cfg->as_rslt_buff = NULL;
+			}
+		}
+
+		pri_mode = p_tbl_cfg->pri_mode;
+		if ((pri_mode == DPP_ACL_PRI_EXPLICIT) ||
+			(pri_mode == DPP_ACL_PRI_IMPLICIT)) {
+			if (p_tbl_cfg->acl_key_buff) {
+				ZXIC_COMM_FREE(p_tbl_cfg->acl_key_buff);
+				p_tbl_cfg->acl_key_buff = NULL;
+			}
+		}
+
+		if (p_tbl_cfg->block_array) {
+			ZXIC_COMM_FREE(p_tbl_cfg->block_array);
+			p_tbl_cfg->block_array = NULL;
+		}
+	}
+
+	return DPP_OK;
+}
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_dtb_table.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_dtb_table.c
index 36f36e224631889a64a133ec158f443b8c4369e2..c8c8d5d0b1216a051fd47f104c40c86b19dac448 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_dtb_table.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_dtb_table.c
@@ -20,3363 +20,3115 @@
 extern ZXIC_UINT32 g_lpm_hw_dat_buf[LPM_HW_DAT_BUFF_SIZE_MAX];
 extern ZXIC_UINT32 g_lpm_hw_dat_offset;
 
-DPP_DTB_MIXED_TABLE_T *p_dtb_mixed_table_mgr = NULL;
+DPP_DTB_MIXED_TABLE_T *p_dtb_mixed_table_mgr;
 
-ZXIC_UINT32 g_dpp_dtb_int_enable =  DISABLE;//默认中断不使能
+ZXIC_UINT32 g_dpp_dtb_int_enable; //默认中断不使能
 ZXIC_UINT32 g_dtb_srh_mode = 1; //默认硬件模式 0：软件查找 1：硬件查找
 
-static ZXIC_UINT32 g_dtb_cmd_endian = 0; //0:小端 1：大端
+static ZXIC_UINT32 g_dtb_cmd_endian; // 0:小端 1：大端
 
-
-DPP_DTB_FIELD_T g_dtb_ddr_table_cmd_info[] = 
-{
-    {"valid", 127, 1},
-    {"type_mode", 126, 3},
-    {"rw_len", 123, 2},
-    {"v46_flag", 121, 1},
-    {"lpm_wr_vld", 120, 1},
-    {"baddr", 119, 20},
-    {"ecc_en", 99, 1},
-    {"rw_addr", 29, 30},
+DPP_DTB_FIELD_T g_dtb_ddr_table_cmd_info[] = {
+	{ "valid", 127, 1 },	{ "type_mode", 126, 3 },  { "rw_len", 123, 2 },
+	{ "v46_flag", 121, 1 }, { "lpm_wr_vld", 120, 1 }, { "baddr", 119, 20 },
+	{ "ecc_en", 99, 1 },	{ "rw_addr", 29, 30 },
 };
 
-DPP_DTB_FIELD_T g_dtb_eram_table_cmd_1_info[] = 
-{
-    {"valid", 127, 1},
-    {"type_mode", 126, 3},
-    {"data_mode",123, 2},
-    {"cpu_wr", 121, 1},
-    {"cpu_rd", 120, 1},
-    {"cpu_rd_mode", 119, 1},
-    {"addr", 113, 26},
-    {"data_h",0,1},
+DPP_DTB_FIELD_T g_dtb_eram_table_cmd_1_info[] = {
+	{ "valid", 127, 1 },  { "type_mode", 126, 3 }, { "data_mode", 123, 2 },
+	{ "cpu_wr", 121, 1 }, { "cpu_rd", 120, 1 },	   { "cpu_rd_mode", 119, 1 },
+	{ "addr", 113, 26 },  { "data_h", 0, 1 },
 };
 
-DPP_DTB_FIELD_T g_dtb_eram_table_cmd_64_info[] = 
-{
-    {"valid", 127, 1},
-    {"type_mode", 126, 3},
-    {"data_mode",123, 2},
-    {"cpu_wr", 121, 1},
-    {"cpu_rd", 120, 1},
-    {"cpu_rd_mode", 119, 1},
-    {"addr", 113, 26},
-    {"data_h",63,32},
-    {"data_l",31,32},
+DPP_DTB_FIELD_T g_dtb_eram_table_cmd_64_info[] = {
+	{ "valid", 127, 1 },  { "type_mode", 126, 3 }, { "data_mode", 123, 2 },
+	{ "cpu_wr", 121, 1 }, { "cpu_rd", 120, 1 },	   { "cpu_rd_mode", 119, 1 },
+	{ "addr", 113, 26 },  { "data_h", 63, 32 },	   { "data_l", 31, 32 },
 };
 
-DPP_DTB_FIELD_T g_dtb_eram_table_cmd_128_info[] = 
-{
-    {"valid", 127, 1},
-    {"type_mode", 126, 3},
-    {"data_mode",123, 2},
-    {"cpu_wr", 121, 1},
-    {"cpu_rd", 120, 1},
-    {"cpu_rd_mode", 119, 1},
-    {"addr", 113, 26},
+DPP_DTB_FIELD_T g_dtb_eram_table_cmd_128_info[] = {
+	{ "valid", 127, 1 },  { "type_mode", 126, 3 }, { "data_mode", 123, 2 },
+	{ "cpu_wr", 121, 1 }, { "cpu_rd", 120, 1 },	   { "cpu_rd_mode", 119, 1 },
+	{ "addr", 113, 26 },
 };
 
-DPP_DTB_FIELD_T g_dtb_zcam_table_cmd_info[] = 
-{
-    {"valid", 127, 1},
-    {"type_mode", 126, 3},
-    {"ram_reg_flag",123, 1},
-    {"zgroup_id", 122, 2},
-    {"zblock_id", 120, 3},
-    {"zcell_id", 117, 2},
-    {"mask", 115, 4},
-    {"sram_addr", 111, 9},
+DPP_DTB_FIELD_T g_dtb_zcam_table_cmd_info[] = {
+	{ "valid", 127, 1 },		{ "type_mode", 126, 3 },
+	{ "ram_reg_flag", 123, 1 }, { "zgroup_id", 122, 2 },
+	{ "zblock_id", 120, 3 },	{ "zcell_id", 117, 2 },
+	{ "mask", 115, 4 },			{ "sram_addr", 111, 9 },
 };
 
-DPP_DTB_FIELD_T g_dtb_etcam_table_cmd_info[] = 
-{
-    {"valid", 127, 1},
-    {"type_mode", 126, 3},
-    {"block_sel",123, 3},
-    {"init_en", 120, 1},
-    {"row_or_col_msk", 119, 1},
-    {"vben", 118, 1},
-    {"reg_tcam_flag", 117, 1},
-    {"uload", 116, 8},
-    {"rd_wr",108, 1},
-    {"wr_mode", 107, 8},
-    {"data_or_mask", 99, 1},
-    {"addr", 98, 9},
-    {"vbit", 89, 8},
+DPP_DTB_FIELD_T g_dtb_etcam_table_cmd_info[] = {
+	{ "valid", 127, 1 },
+	{ "type_mode", 126, 3 },
+	{ "block_sel", 123, 3 },
+	{ "init_en", 120, 1 },
+	{ "row_or_col_msk", 119, 1 },
+	{ "vben", 118, 1 },
+	{ "reg_tcam_flag", 117, 1 },
+	{ "uload", 116, 8 },
+	{ "rd_wr", 108, 1 },
+	{ "wr_mode", 107, 8 },
+	{ "data_or_mask", 99, 1 },
+	{ "addr", 98, 9 },
+	{ "vbit", 89, 8 },
 };
 
-DPP_DTB_FIELD_T g_dtb_mc_hash_table_cmd_info[] = 
-{
-    {"valid", 127, 1},
-    {"type_mode", 126, 3},
-    {"std_h", 63, 32},
-    {"std_l", 31, 32},
+DPP_DTB_FIELD_T g_dtb_mc_hash_table_cmd_info[] = {
+	{ "valid", 127, 1 },
+	{ "type_mode", 126, 3 },
+	{ "std_h", 63, 32 },
+	{ "std_l", 31, 32 },
 };
 
-
-DPP_DTB_TABLE_T g_dpp_dtb_table_info[] = 
-{
-    {
-        "ddr",
-        DTB_TABLE_DDR,
-        8,
-        g_dtb_ddr_table_cmd_info,
-    },
-    {
-        "eram 1 bit",
-        DTB_TABLE_ERAM_1,
-        8,
-        g_dtb_eram_table_cmd_1_info,
-    },
-    {
-        "eram 64 bit",
-        DTB_TABLE_ERAM_64,
-        9,
-        g_dtb_eram_table_cmd_64_info,
-    },
-    {
-        "eram 128 bit",
-        DTB_TABLE_ERAM_128,
-        7,
-        g_dtb_eram_table_cmd_128_info,
-    },
-    {
-        "zcam",
-        DTB_TABLE_ZCAM,
-        8,
-        g_dtb_zcam_table_cmd_info,
-    },
-    {
-        "etcam",
-        DTB_TABLE_ETCAM,
-        13,
-        g_dtb_etcam_table_cmd_info,
-    },
-    {
-        "mc_hash",
-        DTB_TABLE_MC_HASH,
-        4,
-        g_dtb_mc_hash_table_cmd_info
-    },
+DPP_DTB_TABLE_T g_dpp_dtb_table_info[] = {
+	{
+			"ddr",
+			DTB_TABLE_DDR,
+			8,
+			g_dtb_ddr_table_cmd_info,
+	},
+	{
+			"eram 1 bit",
+			DTB_TABLE_ERAM_1,
+			8,
+			g_dtb_eram_table_cmd_1_info,
+	},
+	{
+			"eram 64 bit",
+			DTB_TABLE_ERAM_64,
+			9,
+			g_dtb_eram_table_cmd_64_info,
+	},
+	{
+			"eram 128 bit",
+			DTB_TABLE_ERAM_128,
+			7,
+			g_dtb_eram_table_cmd_128_info,
+	},
+	{
+			"zcam",
+			DTB_TABLE_ZCAM,
+			8,
+			g_dtb_zcam_table_cmd_info,
+	},
+	{
+			"etcam",
+			DTB_TABLE_ETCAM,
+			13,
+			g_dtb_etcam_table_cmd_info,
+	},
+	{ "mc_hash", DTB_TABLE_MC_HASH, 4, g_dtb_mc_hash_table_cmd_info },
 };
 
-
-DPP_DTB_FIELD_T g_dtb_eram_dump_cmd_info[] = 
-{
-    {"valid", 127, 1},
-    {"up_type", 126, 2},
-    {"base_addr", 106, 19},
-    {"tb_depth", 83, 20},
-    {"tb_dst_addr_h", 63, 32},
-    {"tb_dst_addr_l", 31, 32},
+DPP_DTB_FIELD_T g_dtb_eram_dump_cmd_info[] = {
+	{ "valid", 127, 1 },		 { "up_type", 126, 2 },
+	{ "base_addr", 106, 19 },	 { "tb_depth", 83, 20 },
+	{ "tb_dst_addr_h", 63, 32 }, { "tb_dst_addr_l", 31, 32 },
 };
 
-DPP_DTB_FIELD_T g_dtb_ddr_dump_cmd_info[] = 
-{
-    {"valid", 127, 1},
-    {"up_type", 126, 2},
-    {"base_addr", 117, 30},
-    {"tb_depth", 83, 20},
-    {"tb_dst_addr_h", 63, 32},
-    {"tb_dst_addr_l", 31, 32},
+DPP_DTB_FIELD_T g_dtb_ddr_dump_cmd_info[] = {
+	{ "valid", 127, 1 },		 { "up_type", 126, 2 },
+	{ "base_addr", 117, 30 },	 { "tb_depth", 83, 20 },
+	{ "tb_dst_addr_h", 63, 32 }, { "tb_dst_addr_l", 31, 32 },
 
 };
 
-DPP_DTB_FIELD_T g_dtb_zcam_dump_cmd_info[] = 
-{
-    {"valid", 127, 1},
-    {"up_type", 126, 2},
-    {"zgroup_id", 124, 2},
-    {"zblock_id", 122, 3},
-    {"ram_reg_flag", 119, 1},
-    {"z_reg_cell_id", 118, 2},
-    {"sram_addr", 116, 9},
-    {"tb_depth", 97, 10},
-    {"tb_width", 65, 2},
-    {"tb_dst_addr_h", 63, 32},
-    {"tb_dst_addr_l", 31, 32},
+DPP_DTB_FIELD_T g_dtb_zcam_dump_cmd_info[] = {
+	{ "valid", 127, 1 },		 { "up_type", 126, 2 },
+	{ "zgroup_id", 124, 2 },	 { "zblock_id", 122, 3 },
+	{ "ram_reg_flag", 119, 1 },	 { "z_reg_cell_id", 118, 2 },
+	{ "sram_addr", 116, 9 },	 { "tb_depth", 97, 10 },
+	{ "tb_width", 65, 2 },		 { "tb_dst_addr_h", 63, 32 },
+	{ "tb_dst_addr_l", 31, 32 },
 
 };
 
-DPP_DTB_FIELD_T g_dtb_etcam_dump_cmd_info[] = 
-{
-    {"valid", 127, 1},
-    {"up_type", 126, 2},
-    {"block_sel", 124, 3},
-    {"addr", 121, 9},
-    {"rd_mode", 112, 8},
-    {"data_or_mask", 104, 1},
-    {"tb_depth", 91, 10},
-    {"tb_width", 81, 2},
-    {"tb_dst_addr_h", 63, 32},
-    {"tb_dst_addr_l", 31, 32},
+DPP_DTB_FIELD_T g_dtb_etcam_dump_cmd_info[] = {
+	{ "valid", 127, 1 },		 { "up_type", 126, 2 },
+	{ "block_sel", 124, 3 },	 { "addr", 121, 9 },
+	{ "rd_mode", 112, 8 },		 { "data_or_mask", 104, 1 },
+	{ "tb_depth", 91, 10 },		 { "tb_width", 81, 2 },
+	{ "tb_dst_addr_h", 63, 32 }, { "tb_dst_addr_l", 31, 32 },
 
 };
 
-
-DPP_DTB_TABLE_T g_dpp_dtb_dump_info[] = 
-{
-    {
-        "eram",
-        DTB_DUMP_ERAM,
-        6,
-        g_dtb_eram_dump_cmd_info,
-    },
-    {
-        "ddr",
-        DTB_DUMP_DDR,
-        6,
-        g_dtb_ddr_dump_cmd_info,
-    },
-    {
-        "zcam",
-        DTB_DUMP_ZCAM,
-        11,
-        g_dtb_zcam_dump_cmd_info,
-    },
-    {
-        "etcam",
-        DTB_DUMP_ETCAM,
-        10,
-        g_dtb_etcam_dump_cmd_info,
-    },
+DPP_DTB_TABLE_T g_dpp_dtb_dump_info[] = {
+	{
+			"eram",
+			DTB_DUMP_ERAM,
+			6,
+			g_dtb_eram_dump_cmd_info,
+	},
+	{
+			"ddr",
+			DTB_DUMP_DDR,
+			6,
+			g_dtb_ddr_dump_cmd_info,
+	},
+	{
+			"zcam",
+			DTB_DUMP_ZCAM,
+			11,
+			g_dtb_zcam_dump_cmd_info,
+	},
+	{
+			"etcam",
+			DTB_DUMP_ETCAM,
+			10,
+			g_dtb_etcam_dump_cmd_info,
+	},
 };
 
 /** dtb 中断配置
-* @param   int_enable  中断使能
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
+ * @param   int_enable  中断使能
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
 DPP_STATUS dpp_dtb_interrupt_status_set(ZXIC_UINT32 int_enable)
 {
-    g_dpp_dtb_int_enable = int_enable;
-    
-    return DPP_OK;
+	g_dpp_dtb_int_enable = int_enable;
+
+	return DPP_OK;
 }
 
 /** dtb 中断获取
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
 ZXIC_UINT32 dpp_dtb_interrupt_status_get(ZXIC_VOID)
 {
-   return g_dpp_dtb_int_enable;
+	return g_dpp_dtb_int_enable;
 }
 
 /** dtb cmd 大小端设置
-* @param   int_enable  中断使能
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
+ * @param   int_enable  中断使能
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
 DPP_STATUS dpp_dtb_cmd_endian_status_set(ZXIC_UINT32 endian)
 {
-    g_dtb_cmd_endian = endian;
-    
-    return DPP_OK;
+	g_dtb_cmd_endian = endian;
+
+	return DPP_OK;
 }
 
 /** dtb cmd 大小端获取
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
 DPP_STATUS dpp_dtb_cmd_endian_status_get(ZXIC_VOID)
-{   
-    return g_dtb_cmd_endian;
+{
+	return g_dtb_cmd_endian;
 }
 
 /***********************************************************/
 /** 获取 DTB 表属性信息
-* @param   table_type  DTB表类型
-*
-* @return  
-* @remark  无
-* @see
-* @author  cbb      @date  2022/09/02
-************************************************************/
+ * @param   table_type  DTB表类型
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/09/02
+ ************************************************************/
 DPP_DTB_TABLE_T *dpp_table_info_get(ZXIC_UINT32 table_type)
 {
-    ZXIC_COMM_CHECK_INDEX_RETURN_NULL(table_type, 0, DTB_TABLE_ENUM_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_RETURN_NULL(table_type, 0, DTB_TABLE_ENUM_MAX - 1);
 
-    return (&g_dpp_dtb_table_info[table_type]);
+	return ((DPP_DTB_TABLE_T *)&(g_dpp_dtb_table_info[table_type]));
 }
 
 /***********************************************************/
 /** 获取 DTB dump表属性信息
-* @param   up_type  DTB表类型
-*
-* @return  
-* @remark  无
-* @see
-* @author  cbb      @date  2022/09/02
-************************************************************/
+ * @param   up_type  DTB表类型
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/09/02
+ ************************************************************/
 DPP_DTB_TABLE_T *dpp_dump_info_get(ZXIC_UINT32 up_type)
 {
-    ZXIC_COMM_CHECK_INDEX_RETURN_NULL(up_type, 0, DTB_DUMP_ENUM_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_RETURN_NULL(up_type, 0, DTB_DUMP_ENUM_MAX - 1);
 
-    return (&g_dpp_dtb_dump_info[up_type]);
+	return ((DPP_DTB_TABLE_T *)&g_dpp_dtb_dump_info[up_type]);
 }
 
 /*组装128bit数据格式接口*/
 /** dtb写下表128bit格式数据
-* @param   dev_id    设备号
-* @param   table_type  dtb表类型
-* @param   p_cmd_data  表格式命令数据
-* @param   p_cmd_buff  表格式命令数据缓存
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_write_table_cmd(ZXIC_UINT32 dev_id, 
-                                   DPP_DTB_TABLE_INFO_E table_type, 
-                                   ZXIC_VOID *p_cmd_data,
-                                   ZXIC_VOID *p_cmd_buff
-                                   )
+ * @param   dev_id    设备号
+ * @param   table_type  dtb表类型
+ * @param   p_cmd_data  表格式命令数据
+ * @param   p_cmd_buff  表格式命令数据缓存
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_write_table_cmd(ZXIC_UINT32 dev_id,
+								   DPP_DTB_TABLE_INFO_E table_type,
+								   ZXIC_VOID *p_cmd_data, ZXIC_VOID *p_cmd_buff)
 {
-    DPP_STATUS          rc = DPP_OK;
-    ZXIC_UINT32         field_cnt = 0;
-    
-    DPP_DTB_TABLE_T     *p_table_info;
-    DPP_DTB_FIELD_T     *p_field_info = NULL;
-    ZXIC_UINT32         temp_data = 0;
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, table_type, 0, DTB_TABLE_ENUM_MAX - 1);
-    ZXIC_COMM_CHECK_POINT(p_cmd_data);
-    ZXIC_COMM_CHECK_POINT(p_cmd_buff);
-
-    p_table_info = dpp_table_info_get(table_type);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_table_info);
-    p_field_info = p_table_info->p_fields;
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_field_info);
-
-    /* 提取各字段数据，按各字段实际bit位宽进行拼装 */
-    for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++)
-    {
-        temp_data = *((ZXIC_UINT32 *)p_cmd_data + field_cnt) & ZXIC_COMM_GET_BIT_MASK(ZXIC_UINT32,  p_field_info[field_cnt].len);
-
-        rc = zxic_comm_write_bits_ex((ZXIC_UINT8 *)p_cmd_buff,
-                                DTB_TABLE_CMD_SIZE_BIT,
-                                temp_data,
-                                p_field_info[field_cnt].lsb_pos,
-                                p_field_info[field_cnt].len);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_write_bits");
-    }
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 field_cnt = 0;
+
+	DPP_DTB_TABLE_T *p_table_info;
+	DPP_DTB_FIELD_T *p_field_info = NULL;
+	ZXIC_UINT32 temp_data = 0;
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, table_type, 0, DTB_TABLE_ENUM_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(p_cmd_data);
+	ZXIC_COMM_CHECK_POINT(p_cmd_buff);
+
+	p_table_info = dpp_table_info_get(table_type);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_table_info);
+	p_field_info = p_table_info->p_fields;
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_field_info);
+
+	/* 提取各字段数据，按各字段实际bit位宽进行拼装 */
+	for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++) {
+		temp_data = *((ZXIC_UINT32 *)p_cmd_data + field_cnt) &
+					ZXIC_COMM_GET_BIT_MASK(ZXIC_UINT32,
+										   p_field_info[field_cnt].len);
+
+		rc = zxic_comm_write_bits_ex((ZXIC_UINT8 *)p_cmd_buff,
+									 DTB_TABLE_CMD_SIZE_BIT, temp_data,
+									 p_field_info[field_cnt].lsb_pos,
+									 p_field_info[field_cnt].len);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_write_bits");
+	}
+
+	return DPP_OK;
 }
 
 /** dtb写dump表128bit格式数据
-* @param   dev_id    设备号
-* @param   dump_type  dtb dump表类型
-* @param   p_cmd_data  dump表格式命令数据
-* @param   p_cmd_buff  dump表格式命令数据缓存
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_write_dump_cmd(ZXIC_UINT32 dev_id, 
-                                   DPP_DTB_DUMP_INFO_E dump_type, 
-                                   ZXIC_VOID *p_cmd_data,
-                                   ZXIC_VOID *p_cmd_buff)
+ * @param   dev_id    设备号
+ * @param   dump_type  dtb dump表类型
+ * @param   p_cmd_data  dump表格式命令数据
+ * @param   p_cmd_buff  dump表格式命令数据缓存
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_write_dump_cmd(ZXIC_UINT32 dev_id,
+								  DPP_DTB_DUMP_INFO_E dump_type,
+								  ZXIC_VOID *p_cmd_data, ZXIC_VOID *p_cmd_buff)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32         field_cnt = 0;
-    
-    DPP_DTB_TABLE_T     *p_table_info;
-    DPP_DTB_FIELD_T     *p_field_info = NULL;
-    ZXIC_UINT32         temp_data = 0;
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dump_type, 0, DTB_DUMP_ENUM_MAX - 1);
-    ZXIC_COMM_CHECK_POINT(p_cmd_data);
-    ZXIC_COMM_CHECK_POINT(p_cmd_buff);
-
-    p_table_info = dpp_dump_info_get(dump_type);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_table_info);
-    p_field_info = p_table_info->p_fields;
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_field_info);
-
-    /* 提取各字段数据，按各字段实际bit位宽进行拼装 */
-    for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++)
-    {
-
-        temp_data = *((ZXIC_UINT32 *)p_cmd_data + field_cnt) & ZXIC_COMM_GET_BIT_MASK(ZXIC_UINT32,  p_field_info[field_cnt].len);
-
-        rc = zxic_comm_write_bits_ex((ZXIC_UINT8 *)p_cmd_buff,
-                        DTB_TABLE_CMD_SIZE_BIT,
-                        temp_data,
-                        p_field_info[field_cnt].lsb_pos,
-                        p_field_info[field_cnt].len);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_write_bits");
-    }
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 field_cnt = 0;
+
+	DPP_DTB_TABLE_T *p_table_info;
+	DPP_DTB_FIELD_T *p_field_info = NULL;
+	ZXIC_UINT32 temp_data = 0;
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dump_type, 0, DTB_DUMP_ENUM_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(p_cmd_data);
+	ZXIC_COMM_CHECK_POINT(p_cmd_buff);
+
+	p_table_info = dpp_dump_info_get(dump_type);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_table_info);
+	p_field_info = p_table_info->p_fields;
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_field_info);
+
+	/* 提取各字段数据，按各字段实际bit位宽进行拼装 */
+	for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++) {
+		temp_data = *((ZXIC_UINT32 *)p_cmd_data + field_cnt) &
+					ZXIC_COMM_GET_BIT_MASK(ZXIC_UINT32,
+										   p_field_info[field_cnt].len);
+
+		rc = zxic_comm_write_bits_ex((ZXIC_UINT8 *)p_cmd_buff,
+									 DTB_TABLE_CMD_SIZE_BIT, temp_data,
+									 p_field_info[field_cnt].lsb_pos,
+									 p_field_info[field_cnt].len);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_write_bits");
+	}
+
+	return DPP_OK;
 }
 
-
 /** 将下表格式+数据写入缓存中
  * entry，data_in_cmd_flag，如果为1，直接拷贝cmd，不拷贝data
-* @param   p_data_buff    存放数据的buff头指针
-* @param   addr_offset  当前数据要写入的位置（相对于buff头的偏移）
-* @param   entry  要写入缓存的数据指针
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30/
-************************************************************/
-DPP_STATUS dpp_dtb_data_write(ZXIC_UINT8 * p_data_buff, 
-                              ZXIC_UINT32 addr_offset, 
-                              DPP_DTB_ENTRY_T *entry)
+ * @param   p_data_buff    存放数据的buff头指针
+ * @param   addr_offset  当前数据要写入的位置（相对于buff头的偏移）
+ * @param   entry  要写入缓存的数据指针
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30/
+ ************************************************************/
+DPP_STATUS dpp_dtb_data_write(ZXIC_UINT8 *p_data_buff, ZXIC_UINT32 addr_offset,
+							  DPP_DTB_ENTRY_T *entry)
 {
-    ZXIC_UINT8*  p_cmd = p_data_buff + addr_offset;
-    ZXIC_UINT32 cmd_size = DTB_TABLE_CMD_SIZE_BIT / 8;
+	ZXIC_UINT8 *p_cmd = p_data_buff + addr_offset;
+	ZXIC_UINT32 cmd_size = DTB_TABLE_CMD_SIZE_BIT / 8;
 
-    ZXIC_UINT8* p_data = p_cmd + cmd_size;
-    ZXIC_UINT32 data_size = entry->data_size;
+	ZXIC_UINT8 *p_data = p_cmd + cmd_size;
+	ZXIC_UINT32 data_size = entry->data_size;
 
-    ZXIC_UINT8 * cmd = (ZXIC_UINT8 *)entry->cmd;
-    ZXIC_UINT8 * data = (ZXIC_UINT8 *)entry->data;
+	ZXIC_UINT8 *cmd = (ZXIC_UINT8 *)entry->cmd;
+	ZXIC_UINT8 *data = (ZXIC_UINT8 *)entry->data;
 
-    ZXIC_COMM_CHECK_POINT(p_data_buff);
-    ZXIC_COMM_CHECK_POINT(entry);
+	ZXIC_COMM_CHECK_POINT(p_data_buff);
+	ZXIC_COMM_CHECK_POINT(entry);
 
-    /*写入命令数据*/
-    ZXIC_COMM_MEMCPY_S(p_cmd, cmd_size , cmd, cmd_size);
+	/*写入命令数据*/
+	ZXIC_COMM_MEMCPY_S(p_cmd, cmd_size, cmd, cmd_size);
 
-    /*写入数据*/
-    if(!entry->data_in_cmd_flag)
-    {
-        zxic_comm_swap(data, data_size);
-        ZXIC_COMM_MEMCPY_S(p_data, data_size, data, data_size);
-    }
+	/*写入数据*/
+	if (!entry->data_in_cmd_flag) {
+		zxic_comm_swap(data, data_size);
+		ZXIC_COMM_MEMCPY_S(p_data, data_size, data, data_size);
+	}
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 /** 下表数据写入命令寄存器
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   down_table_len   数据长度,单位:字节;
-* @param   p_down_table_buff 下表数据缓存
-* @param   p_element_id   返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_write_down_table_data(DPP_DEV_T *dev, 
-                                      ZXIC_UINT32 queue_id, 
-                                      ZXIC_UINT32 down_table_len,
-                                      ZXIC_UINT8* p_down_table_buff,
-                                      ZXIC_UINT32 *p_element_id
-                                      )
+ * @param   dev_id    设备号
+ * @param   queue_id  队列号
+ * @param   down_table_len   数据长度,单位:字节;
+ * @param   p_down_table_buff 下表数据缓存
+ * @param   p_element_id   返回下表使用的元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_write_down_table_data(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+										 ZXIC_UINT32 down_table_len,
+										 ZXIC_UINT8 *p_down_table_buff,
+										 ZXIC_UINT32 *p_element_id)
 {
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 dtb_interrupt_status = 0;
-    ZXIC_UINT32 dtb_down_check_times = 2;
-    ZXIC_UINT32 element_id = 0;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 dtb_interrupt_status = 0;
 
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
 
-    dtb_interrupt_status = dpp_dtb_interrupt_status_get();
+	dtb_interrupt_status = dpp_dtb_interrupt_status_get();
 
-    while(dtb_down_check_times)
-    {
-        rc = dpp_dtb_tab_down_info_set(dev, 
-                                       queue_id, 
-                                       dtb_interrupt_status, 
-                                       down_table_len / 4, 
-                                       (ZXIC_UINT32 *)p_down_table_buff, 
-                                       &element_id);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc,"dpp_dtb_tab_down_info_set");
+	rc = dpp_dtb_tab_down_info_set(dev, queue_id, dtb_interrupt_status,
+								   down_table_len / 4,
+								   (ZXIC_UINT32 *)p_down_table_buff,
+								   p_element_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_down_info_set");
+	ZXIC_COMM_TRACE_INFO("down slot: %d, queue_id: %d, element id: %d\n",
+						 DEV_PCIE_SLOT(dev), queue_id, *p_element_id);
 
-        rc = dpp_dtb_tab_down_success_status_check(dev, queue_id, element_id);
-        
-        if(rc != DPP_RC_DTB_OVER_TIME)
-        {
-            break;
-        }
+	return DPP_OK;
+}
+
+/** 计算eram 128bit为单位的index
+ * @param   dev_id        设备号
+ * @param   eram_mode     eram 位宽模式
+ * @param   index         以eram_mode为单位的index
+ * @param   p_row_index   出参，行
+ * @param   p_col_index   出参，列
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dtb_eram_index_cal(DPP_DEV_T *dev, ZXIC_UINT32 eram_mode,
+							  ZXIC_UINT32 index, ZXIC_UINT32 *p_row_index,
+							  ZXIC_UINT32 *p_col_index)
+{
+	DPP_STATUS rc = DPP_OK;
 
-        dtb_down_check_times --;
+	ZXIC_UINT32 row_index = 0;
+	ZXIC_UINT32 col_index = 0;
 
-        if(dtb_down_check_times > 0)
-        {
-            ZXIC_COMM_PRINT("DTB DOWN TABLE OVERTIME, DOWN TABLE AGAIN----%d!\n", dtb_down_check_times);
-        }
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_row_index);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_col_index);
 
-    }
+	switch (eram_mode) {
+	case ERAM128_TBL_128b: {
+		row_index = index;
+		break;
+	}
 
-    *p_element_id = element_id;
+	case ERAM128_TBL_64b: {
+		row_index = (index >> 1);
+		col_index = index & 0x1;
+		break;
+	}
 
-    ZXIC_COMM_TRACE_INFO("down slot: %d, queue_id: %d, element id: %d\n", DEV_PCIE_SLOT(dev), queue_id, *p_element_id);
+	case ERAM128_TBL_1b: {
+		row_index = (index >> 7);
+		col_index = index & 0x7F;
+		break;
+	}
+	}
 
-    return DPP_OK;
-}
+	*p_row_index = row_index;
+	*p_col_index = col_index;
 
-/** 计算eram 128bit为单位的index
-* @param   dev_id        设备号
-* @param   eram_mode     eram 位宽模式
-* @param   index         以eram_mode为单位的index
-* @param   p_row_index   出参，行
-* @param   p_col_index   出参，列
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dtb_eram_index_cal(DPP_DEV_T *dev, 
-                              ZXIC_UINT32 eram_mode, 
-                              ZXIC_UINT32 index,
-                              ZXIC_UINT32 *p_row_index, 
-                              ZXIC_UINT32* p_col_index)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    ZXIC_UINT32 row_index = 0;
-    ZXIC_UINT32 col_index = 0;
-
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_row_index);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_col_index);
-
-    switch (eram_mode)
-    {
-        case ERAM128_TBL_128b:
-        {
-            row_index = index;
-            break;
-        }
-
-        case ERAM128_TBL_64b:
-        {
-            row_index = (index >> 1);
-            col_index = index & 0x1;
-            break;
-        }
-
-        case ERAM128_TBL_1b:
-        {
-            row_index = (index >> 7);
-            col_index = index & 0x7F;
-            break;
-        }
-    }
-
-    *p_row_index = row_index;
-    *p_col_index = col_index;
-
-    return rc;
+	return rc;
 }
 
 #if ZXIC_REAL("DTB BASE INTERFACE")
 
 /** smmu0数据组装函数,输入格式字段和数据，输出一个entry
-* @param   dev_id    芯片id
-* @param   mode  位宽模式
-* @param   addr  1bit为单位的索引
-* @param   p_data  要写入数据
-* @param   p_entry  组装好的条目(已分配好空间)
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30/
-************************************************************/
-DPP_STATUS dpp_dtb_smmu0_write_entry_data(DPP_DEV_T *dev, 
-                                            ZXIC_UINT32 mode, 
-                                            ZXIC_UINT32 addr, 
-                                            ZXIC_UINT32 *p_data, 
-                                            DPP_DTB_ENTRY_T *p_entry)
+ * @param   dev_id    芯片id
+ * @param   mode  位宽模式
+ * @param   addr  1bit为单位的索引
+ * @param   p_data  要写入数据
+ * @param   p_entry  组装好的条目(已分配好空间)
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30/
+ ************************************************************/
+DPP_STATUS dpp_dtb_smmu0_write_entry_data(DPP_DEV_T *dev, ZXIC_UINT32 mode,
+										  ZXIC_UINT32 addr, ZXIC_UINT32 *p_data,
+										  DPP_DTB_ENTRY_T *p_entry)
 {
-
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32  i = 0;
-    DPP_DTB_ERAM_TABLE_FORM_T dtb_eram_form_info = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), mode, ERAM128_OPR_128b, ERAM128_OPR_32b);
-
-    dtb_eram_form_info.valid = DTB_TABLE_VALID;
-    dtb_eram_form_info.type_mode = DTB_TABLE_MODE_ERAM;
-    dtb_eram_form_info.data_mode = mode;
-    dtb_eram_form_info.cpu_wr = 1;
-    dtb_eram_form_info.addr = addr;
-    dtb_eram_form_info.cpu_rd = 0;
-    dtb_eram_form_info.cpu_rd_mode = 0;
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dpp eram form info: \n");
-        ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_eram_form_info.valid);
-        ZXIC_COMM_DBGCNT32_PRINT("type_mode", dtb_eram_form_info.type_mode);
-        ZXIC_COMM_DBGCNT32_PRINT("data_mode", dtb_eram_form_info.data_mode);
-        ZXIC_COMM_DBGCNT32_PRINT("cpu_wr", dtb_eram_form_info.cpu_wr);
-        ZXIC_COMM_DBGCNT32_PRINT("addr", dtb_eram_form_info.addr);
-        ZXIC_COMM_DBGCNT32_PRINT("cpu_rd", dtb_eram_form_info.cpu_rd);
-        ZXIC_COMM_DBGCNT32_PRINT("cpu_rd_mode", dtb_eram_form_info.cpu_rd_mode);
-    }
-
-    /*清空p_entry中数据*/
-    if(ERAM128_OPR_128b == mode)
-    {
-        p_entry->data_in_cmd_flag = 0;
-        p_entry->data_size = 128 / 8;
-
-        rc = dpp_dtb_write_table_cmd(DEV_ID(dev), DTB_TABLE_ERAM_128, &dtb_eram_form_info, p_entry->cmd);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd");
-
-        ZXIC_COMM_MEMCPY(p_entry->data, p_data,128 / 8);
-    }
-    else if(ERAM128_OPR_64b == mode)
-    {
-        p_entry->data_in_cmd_flag = 1;
-        p_entry->data_size  = 64 / 8;
-        dtb_eram_form_info.data_l = *(p_data + 1);
-        dtb_eram_form_info.data_h = *(p_data);
-
-        rc = dpp_dtb_write_table_cmd(DEV_ID(dev), DTB_TABLE_ERAM_64, &dtb_eram_form_info, p_entry->cmd);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd");
-
-    }else if(ERAM128_OPR_1b == mode)
-    {
-        p_entry->data_in_cmd_flag = 1;
-        p_entry->data_size  = 1;
-        dtb_eram_form_info.data_h = *(p_data);
-
-        rc = dpp_dtb_write_table_cmd(DEV_ID(dev), DTB_TABLE_ERAM_1, &dtb_eram_form_info, p_entry->cmd);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd");
-    }
-
-    //打印出cmd buff中内容128bit
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("table type: %d\n", DTB_TABLE_MODE_ERAM);
-        ZXIC_COMM_PRINT("cmd: ");
-        for(i = 0; i < 4; i++)
-        {
-            ZXIC_COMM_PRINT("0x%08x  ", ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(p_entry->cmd + 4 * i))));//转换成大端显示
-        }
-
-        if(p_entry->data_in_cmd_flag == 0)
-        {
-            if(p_entry->data)
-            {
-                ZXIC_COMM_PRINT("\ndata:");
-                for(i = 0; i < 4; i++)
-                {
-                    ZXIC_COMM_PRINT("0x%08x  ", *((ZXIC_UINT32 *)(p_entry->data + 4 * i)));
-                }
-                ZXIC_COMM_PRINT("\n");
-            }
-        }
-
-    }
-    
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+	DPP_DTB_ERAM_TABLE_FORM_T dtb_eram_form_info = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), mode, ERAM128_OPR_128b,
+							  ERAM128_OPR_32b);
+
+	dtb_eram_form_info.valid = DTB_TABLE_VALID;
+	dtb_eram_form_info.type_mode = DTB_TABLE_MODE_ERAM;
+	dtb_eram_form_info.data_mode = mode;
+	dtb_eram_form_info.cpu_wr = 1;
+	dtb_eram_form_info.addr = addr;
+	dtb_eram_form_info.cpu_rd = 0;
+	dtb_eram_form_info.cpu_rd_mode = 0;
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dpp eram form info: \n");
+		ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_eram_form_info.valid);
+		ZXIC_COMM_DBGCNT32_PRINT("type_mode", dtb_eram_form_info.type_mode);
+		ZXIC_COMM_DBGCNT32_PRINT("data_mode", dtb_eram_form_info.data_mode);
+		ZXIC_COMM_DBGCNT32_PRINT("cpu_wr", dtb_eram_form_info.cpu_wr);
+		ZXIC_COMM_DBGCNT32_PRINT("addr", dtb_eram_form_info.addr);
+		ZXIC_COMM_DBGCNT32_PRINT("cpu_rd", dtb_eram_form_info.cpu_rd);
+		ZXIC_COMM_DBGCNT32_PRINT("cpu_rd_mode", dtb_eram_form_info.cpu_rd_mode);
+	}
+
+	/*清空p_entry中数据*/
+	if (ERAM128_OPR_128b == mode) {
+		p_entry->data_in_cmd_flag = 0;
+		p_entry->data_size = 128 / 8;
+
+		rc = dpp_dtb_write_table_cmd(DEV_ID(dev), DTB_TABLE_ERAM_128,
+									 &dtb_eram_form_info, p_entry->cmd);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd");
+
+		ZXIC_COMM_MEMCPY(p_entry->data, p_data, 128 / 8);
+	} else if (ERAM128_OPR_64b == mode) {
+		p_entry->data_in_cmd_flag = 1;
+		p_entry->data_size = 64 / 8;
+		dtb_eram_form_info.data_l = *(p_data + 1);
+		dtb_eram_form_info.data_h = *(p_data);
+
+		rc = dpp_dtb_write_table_cmd(DEV_ID(dev), DTB_TABLE_ERAM_64,
+									 &dtb_eram_form_info, p_entry->cmd);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd");
+	} else if (ERAM128_OPR_1b == mode) {
+		p_entry->data_in_cmd_flag = 1;
+		p_entry->data_size = 1;
+		dtb_eram_form_info.data_h = *(p_data);
+
+		rc = dpp_dtb_write_table_cmd(DEV_ID(dev), DTB_TABLE_ERAM_1,
+									 &dtb_eram_form_info, p_entry->cmd);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd");
+	}
+
+	//打印出cmd buff中内容128bit
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("table type: %d\n", DTB_TABLE_MODE_ERAM);
+		ZXIC_COMM_PRINT("cmd: ");
+		for (i = 0; i < 4; i++) {
+			ZXIC_COMM_PRINT("0x%08x  ",
+							ZXIC_COMM_CONVERT32(*(
+									(ZXIC_UINT32 *)(p_entry->cmd +
+													4 * i)))); //转换成大端显示
+		}
+
+		if (p_entry->data_in_cmd_flag == 0) {
+			if (p_entry->data) {
+				ZXIC_COMM_PRINT("\ndata:");
+				for (i = 0; i < 4; i++) {
+					ZXIC_COMM_PRINT("0x%08x  ",
+									*((ZXIC_UINT32 *)(p_entry->data + 4 * i)));
+				}
+				ZXIC_COMM_PRINT("\n");
+			}
+		}
+	}
+
+	return DPP_OK;
 }
 
 /** smmu1数据组装函数,输入格式字段和数据，输出一个entry
-* @param   dev_id    芯片id
-* @param   rw_len  位宽 0-128bit, 1-256bit, 2-384bit, 3-512bit
-* @param   v46_flag  ipv4,ipv6flag 
-* @param   lpm_wr_vld  lpm表写标识 lpm表数据时为1
-* @param   base_addr  基地址 以4K*128为单位
-* @param   index  以位宽为单位的索引
-* @param   ecc_en  ecc使能
-* @param   p_data  要写入数据
-* @param   p_entry  组装好的条目(已分配好空间) data空间大小为512bit
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30/
-************************************************************/
-DPP_STATUS dpp_dtb_smmu1_write_entry_data(ZXIC_UINT32 dev_id, 
-                                        ZXIC_UINT32 rw_len,
-                                        ZXIC_UINT32 v46_flag,
-                                        ZXIC_UINT32 lpm_wr_vld,
-                                        ZXIC_UINT32 base_addr,
-                                        ZXIC_UINT32 index,
-                                        ZXIC_UINT32 ecc_en,
-                                        ZXIC_UINT8 *p_data, 
-                                        DPP_DTB_ENTRY_T *p_entry)
+ * @param   dev_id    芯片id
+ * @param   rw_len  位宽 0-128bit, 1-256bit, 2-384bit, 3-512bit
+ * @param   v46_flag  ipv4,ipv6flag
+ * @param   lpm_wr_vld  lpm表写标识 lpm表数据时为1
+ * @param   base_addr  基地址 以4K*128为单位
+ * @param   index  以位宽为单位的索引
+ * @param   ecc_en  ecc使能
+ * @param   p_data  要写入数据
+ * @param   p_entry  组装好的条目(已分配好空间) data空间大小为512bit
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30/
+ ************************************************************/
+DPP_STATUS dpp_dtb_smmu1_write_entry_data(
+		ZXIC_UINT32 dev_id, ZXIC_UINT32 rw_len, ZXIC_UINT32 v46_flag,
+		ZXIC_UINT32 lpm_wr_vld, ZXIC_UINT32 base_addr, ZXIC_UINT32 index,
+		ZXIC_UINT32 ecc_en, ZXIC_UINT8 *p_data, DPP_DTB_ENTRY_T *p_entry)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32  i = 0;
-    ZXIC_UINT32  j = 0;
-
-    DPP_DTB_DDR_TABLE_FORM_T dtb_ddr_form_info = {0}; /*DDR表格式*/
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(rw_len,SMMU1_DDR_WRT_512b);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_entry);
-
-        /*DTB下表格式内容填充*/
-    dtb_ddr_form_info.valid = DTB_TABLE_VALID;
-    dtb_ddr_form_info.type_mode = DTB_TABLE_MODE_DDR;
-    dtb_ddr_form_info.rw_len = rw_len;
-    dtb_ddr_form_info.v46_flag = v46_flag;
-    dtb_ddr_form_info.lpm_wr_vld = lpm_wr_vld;
-    dtb_ddr_form_info.baddr = base_addr;
-    dtb_ddr_form_info.ecc_en = ecc_en;
-    dtb_ddr_form_info.rw_addr = index;
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dtb_ddr_form_info:\n");
-        ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_ddr_form_info.valid);
-        ZXIC_COMM_DBGCNT32_PRINT("type_mode", dtb_ddr_form_info.type_mode);
-        ZXIC_COMM_DBGCNT32_PRINT("rw_len", dtb_ddr_form_info.rw_len);
-        ZXIC_COMM_DBGCNT32_PRINT("v46_flag", dtb_ddr_form_info.v46_flag);
-        ZXIC_COMM_DBGCNT32_PRINT("lpm_wr_vld", dtb_ddr_form_info.lpm_wr_vld);
-        ZXIC_COMM_DBGCNT32_PRINT("baddr",  dtb_ddr_form_info.baddr);
-        ZXIC_COMM_DBGCNT32_PRINT("ecc_en", dtb_ddr_form_info.ecc_en);
-        ZXIC_COMM_DBGCNT32_PRINT("rw_addr", dtb_ddr_form_info.rw_addr);
-    }
-
-    p_entry->data_in_cmd_flag = 0;
-    p_entry->data_size = DTB_LEN_POS_SETP * (rw_len + 1);
-
-    rc = dpp_dtb_write_table_cmd(dev_id, DTB_TABLE_DDR, &dtb_ddr_form_info, p_entry->cmd);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd");
-
-    ZXIC_COMM_MEMCPY(p_entry->data, p_data, DTB_LEN_POS_SETP * (rw_len + 1));
-
-    //打印出cmd buff中内容128bit
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("table type: %d\n", DTB_TABLE_MODE_DDR);
-        ZXIC_COMM_PRINT("cmd: ");
-        for(i = 0; i < 4; i++)
-        {
-            ZXIC_COMM_PRINT("0x%08x  ", ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(p_entry->cmd + 4 * i))));//转换成大端显示
-        }
-
-        if(p_entry->data)
-        {
-            ZXIC_COMM_PRINT("\ndata:");
-            for(j = 0; j < rw_len + 1; j++)
-            {
-                for(i = 0; i < 4; i++)
-                {
-                    ZXIC_COMM_PRINT("0x%08x  ", *((ZXIC_UINT32 *)(p_entry->data + 16 * j + 4 * i)));
-                }
-                ZXIC_COMM_PRINT("\n");
-            }
-        }
-    }
-    
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 j = 0;
+
+	DPP_DTB_DDR_TABLE_FORM_T dtb_ddr_form_info = { 0 }; /*DDR表格式*/
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(rw_len, SMMU1_DDR_WRT_512b);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_entry);
+
+	/*DTB下表格式内容填充*/
+	dtb_ddr_form_info.valid = DTB_TABLE_VALID;
+	dtb_ddr_form_info.type_mode = DTB_TABLE_MODE_DDR;
+	dtb_ddr_form_info.rw_len = rw_len;
+	dtb_ddr_form_info.v46_flag = v46_flag;
+	dtb_ddr_form_info.lpm_wr_vld = lpm_wr_vld;
+	dtb_ddr_form_info.baddr = base_addr;
+	dtb_ddr_form_info.ecc_en = ecc_en;
+	dtb_ddr_form_info.rw_addr = index;
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dtb_ddr_form_info:\n");
+		ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_ddr_form_info.valid);
+		ZXIC_COMM_DBGCNT32_PRINT("type_mode", dtb_ddr_form_info.type_mode);
+		ZXIC_COMM_DBGCNT32_PRINT("rw_len", dtb_ddr_form_info.rw_len);
+		ZXIC_COMM_DBGCNT32_PRINT("v46_flag", dtb_ddr_form_info.v46_flag);
+		ZXIC_COMM_DBGCNT32_PRINT("lpm_wr_vld", dtb_ddr_form_info.lpm_wr_vld);
+		ZXIC_COMM_DBGCNT32_PRINT("baddr", dtb_ddr_form_info.baddr);
+		ZXIC_COMM_DBGCNT32_PRINT("ecc_en", dtb_ddr_form_info.ecc_en);
+		ZXIC_COMM_DBGCNT32_PRINT("rw_addr", dtb_ddr_form_info.rw_addr);
+	}
+
+	p_entry->data_in_cmd_flag = 0;
+	p_entry->data_size = DTB_LEN_POS_SETP * (rw_len + 1);
+
+	rc = dpp_dtb_write_table_cmd(dev_id, DTB_TABLE_DDR, &dtb_ddr_form_info,
+								 p_entry->cmd);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd");
+
+	ZXIC_COMM_MEMCPY(p_entry->data, p_data, DTB_LEN_POS_SETP * (rw_len + 1));
+
+	//打印出cmd buff中内容128bit
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("table type: %d\n", DTB_TABLE_MODE_DDR);
+		ZXIC_COMM_PRINT("cmd: ");
+		for (i = 0; i < 4; i++) {
+			ZXIC_COMM_PRINT("0x%08x  ",
+							ZXIC_COMM_CONVERT32(*(
+									(ZXIC_UINT32 *)(p_entry->cmd +
+													4 * i)))); //转换成大端显示
+		}
+
+		if (p_entry->data) {
+			ZXIC_COMM_PRINT("\ndata:");
+			for (j = 0; j < rw_len + 1; j++) {
+				for (i = 0; i < 4; i++) {
+					ZXIC_COMM_PRINT(
+							"0x%08x  ",
+							*((ZXIC_UINT32 *)(p_entry->data + 16 * j + 4 * i)));
+				}
+				ZXIC_COMM_PRINT("\n");
+			}
+		}
+	}
+
+	return DPP_OK;
 }
 
-
 /** zcam数据组装函数,输入格式字段和数据，输出一个entry
-* @param   dev_id    芯片id
-* @param   reg_sram_flag  读写ZCAM寄存器/sram标志位：1'b1：读写寄存器 1'b0：读写sram
-* @param   zgroup_id  
-* @param   zblock_id  
-* @param   zcell_id  
-* @param   sram_addr  512bit为单位的地址
-* @param   mask  写掩码：mask[3:0]分别对应CPU写数据的4个128-bit
-*                       mask[0]对应[127:0],1'b0为不写该128-bit，1'b1为写；
-*                       mask[1]对应[255:128]；
-*                       mask[2]对应[383:256]；
-*                       mask[3]对应[512:384]
-* @param   p_data  要写入数据
-* @param   p_entry  组装好的条目(已分配好空间) data空间大小为512bit
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30/
-************************************************************/
-DPP_STATUS dpp_dtb_zcam_write_entry_data(ZXIC_UINT32 dev_id, 
-                                        ZXIC_UINT32 reg_sram_flag,
-                                        ZXIC_UINT32 zgroup_id,
-                                        ZXIC_UINT32 zblock_id,
-                                        ZXIC_UINT32 zcell_id,
-                                        ZXIC_UINT32 sram_addr,
-                                        ZXIC_UINT32 mask,
-                                        ZXIC_UINT8 *p_data, 
-                                        DPP_DTB_ENTRY_T *p_entry)
+ * @param   dev_id    芯片id
+ * @param   reg_sram_flag  读写ZCAM寄存器/sram标志位：1'b1：读写寄存器 1'b0：读写sram
+ * @param   zgroup_id
+ * @param   zblock_id
+ * @param   zcell_id
+ * @param   sram_addr  512bit为单位的地址
+ * @param   mask  写掩码：mask[3:0]分别对应CPU写数据的4个128-bit
+ *                       mask[0]对应[127:0],1'b0为不写该128-bit，1'b1为写；
+ *                       mask[1]对应[255:128]；
+ *                       mask[2]对应[383:256]；
+ *                       mask[3]对应[512:384]
+ * @param   p_data  要写入数据
+ * @param   p_entry  组装好的条目(已分配好空间) data空间大小为512bit
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30/
+ ************************************************************/
+DPP_STATUS dpp_dtb_zcam_write_entry_data(
+		ZXIC_UINT32 dev_id, ZXIC_UINT32 reg_sram_flag, ZXIC_UINT32 zgroup_id,
+		ZXIC_UINT32 zblock_id, ZXIC_UINT32 zcell_id, ZXIC_UINT32 sram_addr,
+		ZXIC_UINT32 mask, ZXIC_UINT8 *p_data, DPP_DTB_ENTRY_T *p_entry)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32  i = 0;
-    ZXIC_UINT32  j = 0;
-
-    DPP_DTB_ZCAM_TABLE_FORM_T dtb_zcam_form_info = {0}; /*ZCAM表格式*/
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zgroup_id, 0, SE_ZGRP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zblock_id, 0, ZBLK_NUM_PER_ZGRP - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zcell_id, 0, SE_ZCELL_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_entry);
-
-    dtb_zcam_form_info.valid = DTB_TABLE_VALID;
-    dtb_zcam_form_info.type_mode = DTB_TABLE_MODE_ZCAM;
-    dtb_zcam_form_info.ram_reg_flag = reg_sram_flag;
-    dtb_zcam_form_info.zgroup_id = zgroup_id;
-    dtb_zcam_form_info.zblock_id = zblock_id;
-    dtb_zcam_form_info.zcell_id = zcell_id;
-    dtb_zcam_form_info.mask = mask;
-    dtb_zcam_form_info.sram_addr = sram_addr & 0x1FF;
-
-    p_entry->data_in_cmd_flag = 0;
-    p_entry->data_size = DTB_LEN_POS_SETP * (DTB_ZCAM_LEN_SIZE - 1);
-
-    rc = dpp_dtb_write_table_cmd(dev_id, DTB_TABLE_ZCAM, &dtb_zcam_form_info, p_entry->cmd);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd");
-
-    ZXIC_COMM_MEMCPY(p_entry->data, p_data, DTB_LEN_POS_SETP * (DTB_ZCAM_LEN_SIZE - 1));
-
-    //打印出cmd buff中内容128bit
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("table type: %d\n", DTB_TABLE_MODE_ZCAM);
-        ZXIC_COMM_PRINT("cmd: ");
-        for(i = 0; i < 4; i++)
-        {
-            ZXIC_COMM_PRINT("0x%08x  ", ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(p_entry->cmd + 4 * i))));//转换成小端显示
-        }
-
-        if(p_entry->data)
-        {
-            ZXIC_COMM_PRINT("\ndata:");
-            for(j = 0; j < DTB_ZCAM_LEN_SIZE-1; j++)
-            {
-                for(i = 0; i < 4; i++)
-                {
-                    ZXIC_COMM_PRINT("0x%08x  ", *((ZXIC_UINT32 *)(p_entry->data + 16 * j + 4 * i)));
-                }
-                ZXIC_COMM_PRINT("\n");
-            }
-        }
-    }
-    
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 j = 0;
+
+	DPP_DTB_ZCAM_TABLE_FORM_T dtb_zcam_form_info = { 0 }; /*ZCAM表格式*/
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zgroup_id, 0, SE_ZGRP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zblock_id, 0, ZBLK_NUM_PER_ZGRP - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zcell_id, 0, SE_ZCELL_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_entry);
+
+	dtb_zcam_form_info.valid = DTB_TABLE_VALID;
+	dtb_zcam_form_info.type_mode = DTB_TABLE_MODE_ZCAM;
+	dtb_zcam_form_info.ram_reg_flag = reg_sram_flag;
+	dtb_zcam_form_info.zgroup_id = zgroup_id;
+	dtb_zcam_form_info.zblock_id = zblock_id;
+	dtb_zcam_form_info.zcell_id = zcell_id;
+	dtb_zcam_form_info.mask = mask;
+	dtb_zcam_form_info.sram_addr = sram_addr & 0x1FF;
+
+	p_entry->data_in_cmd_flag = 0;
+	p_entry->data_size = DTB_LEN_POS_SETP * (DTB_ZCAM_LEN_SIZE - 1);
+
+	rc = dpp_dtb_write_table_cmd(dev_id, DTB_TABLE_ZCAM, &dtb_zcam_form_info,
+								 p_entry->cmd);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd");
+
+	ZXIC_COMM_MEMCPY(p_entry->data, p_data,
+					 DTB_LEN_POS_SETP * (DTB_ZCAM_LEN_SIZE - 1));
+
+	//打印出cmd buff中内容128bit
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("table type: %d\n", DTB_TABLE_MODE_ZCAM);
+		ZXIC_COMM_PRINT("cmd: ");
+		for (i = 0; i < 4; i++) {
+			ZXIC_COMM_PRINT("0x%08x  ",
+							ZXIC_COMM_CONVERT32(*(
+									(ZXIC_UINT32 *)(p_entry->cmd +
+													4 * i)))); //转换成小端显示
+		}
+
+		if (p_entry->data) {
+			ZXIC_COMM_PRINT("\ndata:");
+			for (j = 0; j < DTB_ZCAM_LEN_SIZE - 1; j++) {
+				for (i = 0; i < 4; i++) {
+					ZXIC_COMM_PRINT(
+							"0x%08x  ",
+							*((ZXIC_UINT32 *)(p_entry->data + 16 * j + 4 * i)));
+				}
+				ZXIC_COMM_PRINT("\n");
+			}
+		}
+	}
+
+	return DPP_OK;
 }
 
-
 /** etcam数据组装函数,输入格式字段和数据，输出一个entry
-* @param   dev_id    芯片id
-* @param   block_idx         block索引 0 - 7
-* @param   row_or_col_msk    1 write row mask reg  0:write col mask reg
-* @param   vben              enable the valid bit addressed by addr
-* @param   reg_tcam_flag     1:配置内部row_col_mask寄存器 0：读写tcam
-* @param   flush             使能标识删除对应addr的表项条目，（80bit为单位，含义与wr_mode一一对应）
-* @param   rd_wr             读写标志 0写 1读
-* @param   wr_mode           写入掩码，最高8bit，对应bit为1代表对应的80bit的数据
-* @param   data_or_mask      数据或掩码标志 1：写x(data),0:写y(mask)
-* @param   ram_addr              etcam地址（0-511）
-* @param   vbit              valid bit input
-* @param   p_data            要写入数据
-* @param   p_entry           组装好的条目(已分配好空间) data空间大小为640bit
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30/
-************************************************************/
-DPP_STATUS dpp_dtb_etcam_write_entry_data(DPP_DEV_T *dev, 
-                                        ZXIC_UINT32 block_idx,
-                                        ZXIC_UINT32 row_or_col_msk,
-                                        ZXIC_UINT32 vben,
-                                        ZXIC_UINT32 reg_tcam_flag,
-                                        ZXIC_UINT32 flush,
-                                        ZXIC_UINT32 rd_wr,
-                                        ZXIC_UINT32 wr_mode,
-                                        ZXIC_UINT32 data_or_mask,
-                                        ZXIC_UINT32 ram_addr,
-                                        ZXIC_UINT32 vbit,
-                                        ZXIC_UINT8 *p_data, 
-                                        DPP_DTB_ENTRY_T *p_entry)
+ * @param   dev_id    芯片id
+ * @param   block_idx         block索引 0 - 7
+ * @param   row_or_col_msk    1 write row mask reg  0:write col mask reg
+ * @param   vben              enable the valid bit addressed by addr
+ * @param   reg_tcam_flag     1:配置内部row_col_mask寄存器 0：读写tcam
+ * @param   flush             使能标识删除对应addr的表项条目，（80bit为单位，含义与wr_mode一一对应）
+ * @param   rd_wr             读写标志 0写 1读
+ * @param   wr_mode           写入掩码，最高8bit，对应bit为1代表对应的80bit的数据
+ * @param   data_or_mask      数据或掩码标志 1：写x(data),0:写y(mask)
+ * @param   ram_addr              etcam地址（0-511）
+ * @param   vbit              valid bit input
+ * @param   p_data            要写入数据
+ * @param   p_entry           组装好的条目(已分配好空间) data空间大小为640bit
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30/
+ ************************************************************/
+DPP_STATUS dpp_dtb_etcam_write_entry_data(
+		DPP_DEV_T *dev, ZXIC_UINT32 block_idx, ZXIC_UINT32 row_or_col_msk,
+		ZXIC_UINT32 vben, ZXIC_UINT32 reg_tcam_flag, ZXIC_UINT32 flush,
+		ZXIC_UINT32 rd_wr, ZXIC_UINT32 wr_mode, ZXIC_UINT32 data_or_mask,
+		ZXIC_UINT32 ram_addr, ZXIC_UINT32 vbit, ZXIC_UINT8 *p_data,
+		DPP_DTB_ENTRY_T *p_entry)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 offset = 0;
-    ZXIC_UINT8 *p_temp = NULL;
-
-    ZXIC_UINT8  buff[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    DPP_DTB_ETCAM_TABLE_FORM_T dtb_etcam_form_info = {0}; /*etcam表格式*/
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), row_or_col_msk, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), vben, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), reg_tcam_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flush, 0, DPP_ETCAM_WR_MASK_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_wr, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mode, 0, DPP_ETCAM_WR_MASK_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), data_or_mask, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), ram_addr, 0, DPP_ETCAM_RAM_DEPTH - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), vbit, 0, 0xff);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry);
-
-    /*data etcam 下表格式内容填充*/
-    dtb_etcam_form_info.valid = DTB_TABLE_VALID;
-    dtb_etcam_form_info.type_mode = DTB_TABLE_MODE_ETCAM;
-    dtb_etcam_form_info.block_sel = block_idx;
-    dtb_etcam_form_info.init_en  = 0;
-    dtb_etcam_form_info.row_or_col_msk = row_or_col_msk;
-    dtb_etcam_form_info.vben = vben;
-    dtb_etcam_form_info.reg_tcam_flag = reg_tcam_flag;
-    dtb_etcam_form_info.uload = flush;
-    dtb_etcam_form_info.rd_wr = rd_wr;//0:写;1读
-    dtb_etcam_form_info.wr_mode = wr_mode;
-    dtb_etcam_form_info.data_or_mask = data_or_mask;
-    dtb_etcam_form_info.addr = ram_addr;
-    dtb_etcam_form_info.vbit = vbit;
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dpp etcam form info: \n");
-        ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_etcam_form_info.valid);
-        ZXIC_COMM_DBGCNT32_PRINT("type_mode", dtb_etcam_form_info.type_mode);
-        ZXIC_COMM_DBGCNT32_PRINT("block_sel", dtb_etcam_form_info.block_sel);
-        ZXIC_COMM_DBGCNT32_PRINT("init_en", dtb_etcam_form_info.init_en);
-        ZXIC_COMM_DBGCNT32_PRINT("row_or_col_msk", dtb_etcam_form_info.row_or_col_msk);
-        ZXIC_COMM_DBGCNT32_PRINT("vben", dtb_etcam_form_info.vben);
-        ZXIC_COMM_DBGCNT32_PRINT("reg_tcam_flag", dtb_etcam_form_info.reg_tcam_flag);
-        ZXIC_COMM_DBGCNT32_PRINT("uload", dtb_etcam_form_info.uload);
-        ZXIC_COMM_DBGCNT32_PRINT("rd_wr", dtb_etcam_form_info.rd_wr);
-        ZXIC_COMM_DBGCNT32_PRINT("wr_mode", dtb_etcam_form_info.wr_mode);
-        ZXIC_COMM_DBGCNT32_PRINT("data_or_mask", dtb_etcam_form_info.data_or_mask);
-        ZXIC_COMM_DBGCNT32_PRINT("addr", dtb_etcam_form_info.addr);
-        ZXIC_COMM_DBGCNT32_PRINT("vbit", dtb_etcam_form_info.vbit);
-    }
-
-    p_entry->data_in_cmd_flag = 0;
-    p_entry->data_size = DTB_LEN_POS_SETP * (DTB_ETCAM_LEN_SIZE - 1);
-
-    rc = dpp_dtb_write_table_cmd(DEV_ID(dev), DTB_TABLE_ETCAM, &dtb_etcam_form_info, p_entry->cmd);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd");
-
-    p_temp = p_data;
-
-    /*将数据写入ETCAM表项处理*/
-    /* 160bit key: high 80bit in tcam_ram1, low 80bit in tcam_ram0, and so on. */
-    for (i = 0; i < DPP_ETCAM_RAM_NUM; i++)
-    {
-        offset = i * ((ZXIC_UINT32)DPP_ETCAM_WIDTH_MIN / 8);
-
-        if ((wr_mode >> (DPP_ETCAM_RAM_NUM - 1 - i)) & 0x1)
-        {
-            ZXIC_COMM_MEMCPY(buff + offset, p_temp, DPP_ETCAM_WIDTH_MIN / 8);
-            p_temp += DPP_ETCAM_WIDTH_MIN / 8;
-        }
-    }
-
-    zxic_comm_swap((ZXIC_UINT8 *)buff, DTB_LEN_POS_SETP * (DTB_ETCAM_LEN_SIZE - 1));
-
-    ZXIC_COMM_MEMCPY(p_entry->data, buff, DTB_LEN_POS_SETP * (DTB_ETCAM_LEN_SIZE - 1));
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dpp_dtb_etcam_write_entry_data: \n");
-        ZXIC_COMM_PRINT("wr_mode:0x%08x\n", wr_mode);
-        for(i = 0; i < 20; i++)
-        {
-            ZXIC_COMM_PRINT("0x%08x ",*((ZXIC_UINT32*)(buff + 4 * i)));
-        }
-        ZXIC_COMM_PRINT("\n");
-    }
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 offset = 0;
+	ZXIC_UINT8 *p_temp = NULL;
+
+	ZXIC_UINT8 buff[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	DPP_DTB_ETCAM_TABLE_FORM_T dtb_etcam_form_info = { 0 }; /*etcam表格式*/
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0,
+							  DPP_ETCAM_BLOCK_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), row_or_col_msk, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), vben, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), reg_tcam_flag, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), flush, 0, DPP_ETCAM_WR_MASK_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_wr, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mode, 0, DPP_ETCAM_WR_MASK_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), data_or_mask, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), ram_addr, 0,
+							  DPP_ETCAM_RAM_DEPTH - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), vbit, 0, 0xff);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry);
+
+	/*data etcam 下表格式内容填充*/
+	dtb_etcam_form_info.valid = DTB_TABLE_VALID;
+	dtb_etcam_form_info.type_mode = DTB_TABLE_MODE_ETCAM;
+	dtb_etcam_form_info.block_sel = block_idx;
+	dtb_etcam_form_info.init_en = 0;
+	dtb_etcam_form_info.row_or_col_msk = row_or_col_msk;
+	dtb_etcam_form_info.vben = vben;
+	dtb_etcam_form_info.reg_tcam_flag = reg_tcam_flag;
+	dtb_etcam_form_info.uload = flush;
+	dtb_etcam_form_info.rd_wr = rd_wr; // 0:写;1读
+	dtb_etcam_form_info.wr_mode = wr_mode;
+	dtb_etcam_form_info.data_or_mask = data_or_mask;
+	dtb_etcam_form_info.addr = ram_addr;
+	dtb_etcam_form_info.vbit = vbit;
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dpp etcam form info: \n");
+		ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_etcam_form_info.valid);
+		ZXIC_COMM_DBGCNT32_PRINT("type_mode", dtb_etcam_form_info.type_mode);
+		ZXIC_COMM_DBGCNT32_PRINT("block_sel", dtb_etcam_form_info.block_sel);
+		ZXIC_COMM_DBGCNT32_PRINT("init_en", dtb_etcam_form_info.init_en);
+		ZXIC_COMM_DBGCNT32_PRINT("row_or_col_msk",
+								 dtb_etcam_form_info.row_or_col_msk);
+		ZXIC_COMM_DBGCNT32_PRINT("vben", dtb_etcam_form_info.vben);
+		ZXIC_COMM_DBGCNT32_PRINT("reg_tcam_flag",
+								 dtb_etcam_form_info.reg_tcam_flag);
+		ZXIC_COMM_DBGCNT32_PRINT("uload", dtb_etcam_form_info.uload);
+		ZXIC_COMM_DBGCNT32_PRINT("rd_wr", dtb_etcam_form_info.rd_wr);
+		ZXIC_COMM_DBGCNT32_PRINT("wr_mode", dtb_etcam_form_info.wr_mode);
+		ZXIC_COMM_DBGCNT32_PRINT("data_or_mask",
+								 dtb_etcam_form_info.data_or_mask);
+		ZXIC_COMM_DBGCNT32_PRINT("addr", dtb_etcam_form_info.addr);
+		ZXIC_COMM_DBGCNT32_PRINT("vbit", dtb_etcam_form_info.vbit);
+	}
+
+	p_entry->data_in_cmd_flag = 0;
+	p_entry->data_size = DTB_LEN_POS_SETP * (DTB_ETCAM_LEN_SIZE - 1);
+
+	rc = dpp_dtb_write_table_cmd(DEV_ID(dev), DTB_TABLE_ETCAM,
+								 &dtb_etcam_form_info, p_entry->cmd);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_table_cmd");
+
+	p_temp = p_data;
+
+	/*将数据写入ETCAM表项处理*/
+	/* 160bit key: high 80bit in tcam_ram1, low 80bit in tcam_ram0, and so on. */
+	for (i = 0; i < DPP_ETCAM_RAM_NUM; i++) {
+		offset = i * ((ZXIC_UINT32)DPP_ETCAM_WIDTH_MIN / 8);
+
+		if ((wr_mode >> (DPP_ETCAM_RAM_NUM - 1 - i)) & 0x1) {
+			ZXIC_COMM_MEMCPY(buff + offset, p_temp, DPP_ETCAM_WIDTH_MIN / 8);
+			p_temp += DPP_ETCAM_WIDTH_MIN / 8;
+		}
+	}
+
+	zxic_comm_swap((ZXIC_UINT8 *)buff,
+				   DTB_LEN_POS_SETP * (DTB_ETCAM_LEN_SIZE - 1));
+
+	ZXIC_COMM_MEMCPY(p_entry->data, buff,
+					 DTB_LEN_POS_SETP * (DTB_ETCAM_LEN_SIZE - 1));
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dpp_dtb_etcam_write_entry_data: \n");
+		ZXIC_COMM_PRINT("wr_mode:0x%08x\n", wr_mode);
+		for (i = 0; i < 20; i++) {
+			ZXIC_COMM_PRINT("0x%08x ", *((ZXIC_UINT32 *)(buff + 4 * i)));
+		}
+		ZXIC_COMM_PRINT("\n");
+	}
+
+	return DPP_OK;
 }
 
 /** 写eram，输出一个entry
-* @param   dev_id     芯片id
-* @param   base_addr  基地址，以128bit为单位
-* @param   index      条目索引，以mode为单位
-* @param   wr_mode    数据位宽模式,支持0：128bit 1：64bit  2:1bit
-* @param   p_data     待写入的数据
-* @param   p_entry    组装好的数据
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30/
-************************************************************/
-DPP_STATUS dpp_dtb_se_smmu0_ind_write(DPP_DEV_T *dev,
-                                  ZXIC_UINT32 base_addr,
-                                  ZXIC_UINT32 index,
-                                  ZXIC_UINT32 wrt_mode,
-                                  ZXIC_UINT32 *p_data,
-                                  DPP_DTB_ENTRY_T *p_entry)
+ * @param   dev_id     芯片id
+ * @param   base_addr  基地址，以128bit为单位
+ * @param   index      条目索引，以mode为单位
+ * @param   wr_mode    数据位宽模式,支持0：128bit 1：64bit  2:1bit
+ * @param   p_data     待写入的数据
+ * @param   p_entry    组装好的数据
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30/
+ ************************************************************/
+DPP_STATUS dpp_dtb_se_smmu0_ind_write(DPP_DEV_T *dev, ZXIC_UINT32 base_addr,
+									  ZXIC_UINT32 index, ZXIC_UINT32 wrt_mode,
+									  ZXIC_UINT32 *p_data,
+									  DPP_DTB_ENTRY_T *p_entry)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 temp_idx = 0;
-    ZXIC_UINT32 dtb_ind_addr = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wrt_mode, ERAM128_OPR_128b, ERAM128_OPR_1b);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), base_addr, 0, SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1);
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dpp_dtb_se_smmu0_ind_write: \n");
-        ZXIC_COMM_PRINT("base addr: 0x%08x\n",base_addr);
-        ZXIC_COMM_PRINT("index: 0x%08x\n",index);
-        ZXIC_COMM_PRINT("write mode: %d 0-128bit 1-64bit  2-1bit\n",wrt_mode);
-    }
-
-    switch (wrt_mode)
-    {
-        case ERAM128_OPR_128b:
-        {
-            if((0xFFFFFFFF - (base_addr)) < (index))
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),  "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, base_addr, index, __FUNCTION__);
-
-                return ZXIC_PAR_CHK_INVALID_INDEX;
-            }
-            if (base_addr + index > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1)
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),  "dpp_dtb_se_smmu0_ind_write : index out of range !\n");
-                return DPP_ERR;
-            }
-
-            temp_idx = index << 7;
-
-            break;
-        }
-
-        case ERAM128_OPR_64b:
-        {
-            if ((base_addr + (index >> 1)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1)
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),  "dpp_dtb_se_smmu0_ind_write : index out of range !\n");
-                return DPP_ERR;
-            }
-
-            temp_idx = index << 6;
-
-            break;
-        }
-
-        case ERAM128_OPR_1b:
-        {
-            if ((base_addr + (index >> 7)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1)
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),  "dpp_dtb_se_smmu0_ind_write : index out of range !\n");
-                return DPP_ERR;
-            }
-
-            temp_idx = index;
-        }
-    }
-
-    if((0xFFFFFFFF - (temp_idx)) < ((base_addr << 7) & DPP_ERAM128_BADDR_MASK))
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),  "ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n", __FILE__, __LINE__, temp_idx, ((base_addr << 7) & DPP_ERAM128_BADDR_MASK), __FUNCTION__);
-        return ZXIC_PAR_CHK_INVALID_INDEX;
-    }
-
-    dtb_ind_addr = ((base_addr << 7) & DPP_ERAM128_BADDR_MASK) + temp_idx;
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_DBGCNT32_PRINT(" dtb eram item 1bit addr", dtb_ind_addr);
-    }
-    
-    rc = dpp_dtb_smmu0_write_entry_data(dev, 
-                          wrt_mode, 
-                          dtb_ind_addr,  
-                          p_data,  
-                          p_entry);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_write_entry_data");
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 temp_idx = 0;
+	ZXIC_UINT32 dtb_ind_addr = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wrt_mode, ERAM128_OPR_128b,
+							  ERAM128_OPR_1b);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), base_addr, 0,
+							  SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1);
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dpp_dtb_se_smmu0_ind_write: \n");
+		ZXIC_COMM_PRINT("base addr: 0x%08x\n", base_addr);
+		ZXIC_COMM_PRINT("index: 0x%08x\n", index);
+		ZXIC_COMM_PRINT("write mode: %d 0-128bit 1-64bit  2-1bit\n", wrt_mode);
+	}
+
+	switch (wrt_mode) {
+	case ERAM128_OPR_128b: {
+		if ((0xFFFFFFFF - (base_addr)) < (index)) {
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					DEV_ID(dev),
+					"ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n",
+					__FILE__, __LINE__, base_addr, index, __FUNCTION__);
+
+			return ZXIC_PAR_CHK_INVALID_INDEX;
+		}
+		if (base_addr + index > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					DEV_ID(dev),
+					"dpp_dtb_se_smmu0_ind_write : index out of range !\n");
+			return DPP_ERR;
+		}
+
+		temp_idx = index << 7;
+
+		break;
+	}
+
+	case ERAM128_OPR_64b: {
+		if ((base_addr + (index >> 1)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					DEV_ID(dev),
+					"dpp_dtb_se_smmu0_ind_write : index out of range !\n");
+			return DPP_ERR;
+		}
+
+		temp_idx = index << 6;
+
+		break;
+	}
+
+	case ERAM128_OPR_1b: {
+		if ((base_addr + (index >> 7)) > SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					DEV_ID(dev),
+					"dpp_dtb_se_smmu0_ind_write : index out of range !\n");
+			return DPP_ERR;
+		}
+
+		temp_idx = index;
+	}
+	}
+
+	if ((0xFFFFFFFF - (temp_idx)) <
+		((base_addr << 7) & DPP_ERAM128_BADDR_MASK)) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev),
+				"ICM %s:%d[Error:VALUE[val0=0x%x] INVALID] [val1=0x%x] ! FUNCTION :%s !\n",
+				__FILE__, __LINE__, temp_idx,
+				((base_addr << 7) & DPP_ERAM128_BADDR_MASK), __FUNCTION__);
+		return ZXIC_PAR_CHK_INVALID_INDEX;
+	}
+
+	dtb_ind_addr = ((base_addr << 7) & DPP_ERAM128_BADDR_MASK) + temp_idx;
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_DBGCNT32_PRINT(" dtb eram item 1bit addr", dtb_ind_addr);
+	}
+
+	rc = dpp_dtb_smmu0_write_entry_data(dev, wrt_mode, dtb_ind_addr, p_data,
+										p_entry);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_write_entry_data");
+
+	return DPP_OK;
 }
 
 /** dtb写smmu0中的数据，数据长度在16K范围内
-* @param   dev_id          设备号
-* @param   queue_id        队列号
-* @param   smmu0_base_addr smmu0基地址，以128bit为单位
-* @param   smmu0_wr_mode   smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式
-* @param   entry_num       下发的条目数
-* @param   p_entry_arr     待下发表项内容结构体数组指针
-* @param   element_id      返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2024/01/04
-************************************************************/
-DPP_STATUS dpp_dtb_smmu0_data_write_cycle(DPP_DEV_T *dev,
-                                         ZXIC_UINT32 queue_id,
-                                         ZXIC_UINT32 smmu0_base_addr,
-                                         ZXIC_UINT32 smmu0_wr_mode,
-                                         ZXIC_UINT32 entry_num,
-                                         DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr,
-                                         ZXIC_UINT32 *element_id)
+ * @param   dev_id          设备号
+ * @param   queue_id        队列号
+ * @param   smmu0_base_addr smmu0基地址，以128bit为单位
+ * @param   smmu0_wr_mode   smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式
+ * @param   entry_num       下发的条目数
+ * @param   p_entry_arr     待下发表项内容结构体数组指针
+ * @param   element_id      返回下表使用的元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2024/01/04
+ ************************************************************/
+DPP_STATUS dpp_dtb_smmu0_data_write_cycle(
+		DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 smmu0_base_addr,
+		ZXIC_UINT32 smmu0_wr_mode, ZXIC_UINT32 entry_num,
+		DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr, ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS  rc = DPP_OK;
-
-    ZXIC_UINT32 item_cnt = 0;
-    ZXIC_UINT32 addr_offset = 0;
-    ZXIC_UINT32 dtb_len = 0;
-    ZXIC_UINT32 index = 0;
-
-    ZXIC_UINT32 *p_entry_data = NULL;
-    ZXIC_UINT8 *table_data_buff = NULL;
-    ZXIC_UINT32 entry_data_buff[4] = {0};
-    ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0};
-    DPP_DTB_ENTRY_T   dtb_one_entry = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_arr);
-
-    //分配下表数据缓存 16K
-    table_data_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), table_data_buff);
-    ZXIC_COMM_MEMSET(table_data_buff, 0, DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
-
-    dtb_one_entry.cmd = cmd_buff;
-    dtb_one_entry.data = (ZXIC_UINT8 *)entry_data_buff;
-
-    for(item_cnt = 0; item_cnt < entry_num; ++item_cnt)
-    {
-        p_entry_data = (ZXIC_UINT32 *)p_entry_arr[item_cnt].p_data;
-        ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(p_entry_data, table_data_buff);
-        index = p_entry_arr[item_cnt].index;
-        
-        //将一个数据写入entry
-        rc = dpp_dtb_se_smmu0_ind_write(dev,
-                                        smmu0_base_addr, 
-                                        index, 
-                                        smmu0_wr_mode,
-                                        p_entry_data,
-                                        &dtb_one_entry);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_se_smmu0_ind_write", table_data_buff);
-
-        switch (smmu0_wr_mode)
-        {
-            case ERAM128_OPR_128b:
-            {
-                dtb_len += 2; 
-                addr_offset = item_cnt * DTB_LEN_POS_SETP * 2;
-                break;
-            }
-
-            case ERAM128_OPR_64b:
-            {
-                dtb_len += 1; 
-                addr_offset = item_cnt * DTB_LEN_POS_SETP;
-                break;
-            }
-
-            case ERAM128_OPR_1b:
-            {
-                dtb_len += 1;
-                addr_offset = item_cnt * DTB_LEN_POS_SETP;
-                break;
-            }
-        }
-
-        /*将表格式和数据写入缓存buff中*/
-        rc = dpp_dtb_data_write(table_data_buff, addr_offset, &dtb_one_entry);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", table_data_buff);
-        ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
-        ZXIC_COMM_MEMSET(entry_data_buff, 0, 4 * sizeof(ZXIC_UINT32));
-    }
-
-    if(dpp_dtb_prt_get())
-    {
-        dpp_data_buff_print(table_data_buff, dtb_len * 16);
-        ZXIC_COMM_PRINT("start down table to dtb : queue_id: %d, down_data_len: %d\n", queue_id, dtb_len * 16);
-    }
-     
-    rc = dpp_dtb_write_down_table_data(dev,  
-                                       queue_id, 
-                                       dtb_len * 16,
-                                       table_data_buff,
-                                       element_id);
-    ZXIC_COMM_FREE(table_data_buff);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_down_table_data");
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 item_cnt = 0;
+	ZXIC_UINT32 addr_offset = 0;
+	ZXIC_UINT32 dtb_len = 0;
+	ZXIC_UINT32 index = 0;
+
+	ZXIC_UINT32 *p_entry_data = NULL;
+	ZXIC_UINT8 *table_data_buff = NULL;
+	ZXIC_UINT32 entry_data_buff[4] = { 0 };
+	ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = { 0 };
+	DPP_DTB_ENTRY_T dtb_one_entry = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_arr);
+
+	//分配下表数据缓存 16K
+	table_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(
+			DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), table_data_buff);
+	ZXIC_COMM_MEMSET(table_data_buff, 0,
+					 DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
+
+	dtb_one_entry.cmd = cmd_buff;
+	dtb_one_entry.data = (ZXIC_UINT8 *)entry_data_buff;
+
+	for (item_cnt = 0; item_cnt < entry_num; ++item_cnt) {
+		p_entry_data = (ZXIC_UINT32 *)p_entry_arr[item_cnt].p_data;
+		ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(p_entry_data,
+													table_data_buff);
+		index = p_entry_arr[item_cnt].index;
+
+		//将一个数据写入entry
+		rc = dpp_dtb_se_smmu0_ind_write(dev, smmu0_base_addr, index,
+										smmu0_wr_mode, p_entry_data,
+										&dtb_one_entry);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+				rc, "dpp_dtb_se_smmu0_ind_write", table_data_buff);
+
+		switch (smmu0_wr_mode) {
+		case ERAM128_OPR_128b: {
+			dtb_len += 2;
+			addr_offset = item_cnt * DTB_LEN_POS_SETP * 2;
+			break;
+		}
+
+		case ERAM128_OPR_64b: {
+			dtb_len += 1;
+			addr_offset = item_cnt * DTB_LEN_POS_SETP;
+			break;
+		}
+
+		case ERAM128_OPR_1b: {
+			dtb_len += 1;
+			addr_offset = item_cnt * DTB_LEN_POS_SETP;
+			break;
+		}
+		}
+
+		/*将表格式和数据写入缓存buff中*/
+		rc = dpp_dtb_data_write(table_data_buff, addr_offset, &dtb_one_entry);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",
+												 table_data_buff);
+		ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
+		ZXIC_COMM_MEMSET(entry_data_buff, 0, 4 * sizeof(ZXIC_UINT32));
+	}
+
+	if (dpp_dtb_prt_get()) {
+		dpp_data_buff_print(table_data_buff, dtb_len * 16);
+		ZXIC_COMM_PRINT(
+				"start down table to dtb : queue_id: %d, down_data_len: %d\n",
+				queue_id, dtb_len * 16);
+	}
+
+	rc = dpp_dtb_write_down_table_data(dev, queue_id, dtb_len * 16,
+									   table_data_buff, element_id);
+	ZXIC_COMM_FREE(table_data_buff);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_down_table_data");
+
+	rc = dpp_dtb_tab_down_success_status_check(dev, queue_id, *element_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_down_success_status_check");
+
+	return DPP_OK;
 }
 
 /** dtb写smmu0中的数据，数据长度不限
-* @param   dev_id          设备号
-* @param   queue_id        队列号
-* @param   smmu0_base_addr smmu0基地址，以128bit为单位
-* @param   smmu0_wr_mode   smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式
-* @param   entry_num       下发的条目数
-* @param   p_entry_arr     待下发表项内容结构体数组指针
-* @param   element_id      返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2024/01/04
-************************************************************/
-DPP_STATUS dpp_dtb_smmu0_data_write(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 queue_id,
-                                    ZXIC_UINT32 smmu0_base_addr,
-                                    ZXIC_UINT32 smmu0_wr_mode,
-                                    ZXIC_UINT32 entry_num,
-                                    DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr,
-                                    ZXIC_UINT32 *element_id)
+ * @param   dev_id          设备号
+ * @param   queue_id        队列号
+ * @param   smmu0_base_addr smmu0基地址，以128bit为单位
+ * @param   smmu0_wr_mode   smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式
+ * @param   entry_num       下发的条目数
+ * @param   p_entry_arr     待下发表项内容结构体数组指针
+ * @param   element_id      返回下表使用的元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2024/01/04
+ ************************************************************/
+DPP_STATUS dpp_dtb_smmu0_data_write(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									ZXIC_UINT32 smmu0_base_addr,
+									ZXIC_UINT32 smmu0_wr_mode,
+									ZXIC_UINT32 entry_num,
+									DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr,
+									ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS  rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 entry_num_max = 0;
-    ZXIC_UINT32 entry_cycle = 0;
-    ZXIC_UINT32 entry_remains = 0;
-
-    DPP_DTB_ERAM_ENTRY_INFO_T *p_entry = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_entry_arr);
-
-    switch (smmu0_wr_mode)
-    {
-        case ERAM128_OPR_128b:
-        {
-            entry_num_max = 0x1ff;
-            break;
-        }
-
-        case ERAM128_OPR_64b:
-        {
-            entry_num_max = 0x3ff;
-            break;
-        }
-
-        case ERAM128_OPR_1b:
-        {
-            entry_num_max = 0x3ff;
-            break;
-        }
-    }
-
-    ZXIC_COMM_CHECK_INDEX_EQUAL(entry_num_max, 0);
-    entry_cycle = entry_num / entry_num_max;
-    entry_remains = entry_num % entry_num_max;
-
-    for(i = 0; i < entry_cycle; ++i)
-    {
-        p_entry = p_entry_arr + entry_num_max * i;
-        rc = dpp_dtb_smmu0_data_write_cycle(dev,
-                                            queue_id,
-                                            smmu0_base_addr,
-                                            smmu0_wr_mode,
-                                            entry_num_max,
-                                            p_entry,
-                                            element_id);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_data_write_cycle");
-
-        ZXIC_COMM_TRACE_INFO("dpp_dtb_smmu0_data_write_cycle[%d]: element_id = %d\n", i, *element_id);
-    }
-
-    if(entry_remains)
-    {
-        p_entry = p_entry_arr + entry_num_max * entry_cycle;
-        rc = dpp_dtb_smmu0_data_write_cycle(dev,
-                                            queue_id,
-                                            smmu0_base_addr,
-                                            smmu0_wr_mode,
-                                            entry_remains,
-                                            p_entry,
-                                            element_id);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_data_write_cycle");
-
-        ZXIC_COMM_TRACE_INFO("dpp_dtb_smmu0_data_write_cycle: element_id = %d\n", *element_id);
-    }
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 entry_num_max = 0;
+	ZXIC_UINT32 entry_cycle = 0;
+	ZXIC_UINT32 entry_remains = 0;
+
+	DPP_DTB_ERAM_ENTRY_INFO_T *p_entry = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_entry_arr);
+
+	switch (smmu0_wr_mode) {
+	case ERAM128_OPR_128b: {
+		entry_num_max = 0x1ff;
+		break;
+	}
+
+	case ERAM128_OPR_64b: {
+		entry_num_max = 0x3ff;
+		break;
+	}
+
+	case ERAM128_OPR_1b: {
+		entry_num_max = 0x3ff;
+		break;
+	}
+	}
+
+	ZXIC_COMM_CHECK_INDEX_EQUAL(entry_num_max, 0);
+	entry_cycle = entry_num / entry_num_max;
+	entry_remains = entry_num % entry_num_max;
+
+	for (i = 0; i < entry_cycle; ++i) {
+		p_entry = p_entry_arr + entry_num_max * i;
+		rc = dpp_dtb_smmu0_data_write_cycle(dev, queue_id, smmu0_base_addr,
+											smmu0_wr_mode, entry_num_max,
+											p_entry, element_id);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_data_write_cycle");
+
+		ZXIC_COMM_TRACE_INFO(
+				"dpp_dtb_smmu0_data_write_cycle[%d]: element_id = %d\n", i,
+				*element_id);
+	}
+
+	if (entry_remains) {
+		p_entry = p_entry_arr + entry_num_max * entry_cycle;
+		rc = dpp_dtb_smmu0_data_write_cycle(dev, queue_id, smmu0_base_addr,
+											smmu0_wr_mode, entry_remains,
+											p_entry, element_id);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_data_write_cycle");
+
+		ZXIC_COMM_TRACE_INFO(
+				"dpp_dtb_smmu0_data_write_cycle: element_id = %d\n",
+				*element_id);
+	}
+
+	return DPP_OK;
 }
 
 /** dtb flush smmu0中的数据，数据长度16K以内
-* @param   dev_id          设备号
-* @param   queue_id        队列号
-* @param   smmu0_base_addr smmu0基地址，以128bit为单位
-* @param   smmu0_wr_mode   smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式
-* @param   start_index     flush开始的条目
-* @param   entry_num       下发的条目数
-* @param   element_id      返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2024/01/04
-************************************************************/
-DPP_STATUS dpp_dtb_smmu0_flush_cycle(DPP_DEV_T *dev, 
-                                     ZXIC_UINT32 queue_id,
-                                     ZXIC_UINT32 smmu0_base_addr,
-                                     ZXIC_UINT32 smmu0_wr_mode,
-                                     ZXIC_UINT32 start_index,
-                                     ZXIC_UINT32 entry_num,
-                                     ZXIC_UINT32 *element_id)
+ * @param   dev_id          设备号
+ * @param   queue_id        队列号
+ * @param   smmu0_base_addr smmu0基地址，以128bit为单位
+ * @param   smmu0_wr_mode   smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式
+ * @param   start_index     flush开始的条目
+ * @param   entry_num       下发的条目数
+ * @param   element_id      返回下表使用的元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2024/01/04
+ ************************************************************/
+DPP_STATUS dpp_dtb_smmu0_flush_cycle(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									 ZXIC_UINT32 smmu0_base_addr,
+									 ZXIC_UINT32 smmu0_wr_mode,
+									 ZXIC_UINT32 start_index,
+									 ZXIC_UINT32 entry_num,
+									 ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS  rc = DPP_OK;
-
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT32 current_index = 0;
-    ZXIC_UINT32 entry_data_buff[4] = {0};
-    DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    p_entry_arr = (DPP_DTB_ERAM_ENTRY_INFO_T *)ZXIC_COMM_MALLOC(entry_num * sizeof(DPP_DTB_ERAM_ENTRY_INFO_T));
-    ZXIC_COMM_CHECK_POINT(p_entry_arr);
-    ZXIC_COMM_MEMSET(p_entry_arr, 0, entry_num * sizeof(DPP_DTB_ERAM_ENTRY_INFO_T));
-
-    for(index = 0; index < entry_num; index++)
-    {
-        current_index = start_index + index;
-
-        p_entry_arr[index].index = current_index;
-        p_entry_arr[index].p_data = entry_data_buff;
-    }
-
-    rc = dpp_dtb_smmu0_data_write_cycle(dev,
-                                        queue_id,
-                                        smmu0_base_addr,
-                                        smmu0_wr_mode,
-                                        entry_num,
-                                        p_entry_arr,
-                                        element_id); 
-    ZXIC_COMM_FREE(p_entry_arr);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_data_write_cycle");
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 current_index = 0;
+	ZXIC_UINT32 entry_data_buff[4] = { 0 };
+	DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	p_entry_arr = (DPP_DTB_ERAM_ENTRY_INFO_T *)ZXIC_COMM_MALLOC(
+			entry_num * sizeof(DPP_DTB_ERAM_ENTRY_INFO_T));
+	ZXIC_COMM_CHECK_POINT(p_entry_arr);
+	ZXIC_COMM_MEMSET(p_entry_arr, 0,
+					 entry_num * sizeof(DPP_DTB_ERAM_ENTRY_INFO_T));
+
+	for (index = 0; index < entry_num; index++) {
+		current_index = start_index + index;
+
+		p_entry_arr[index].index = current_index;
+		p_entry_arr[index].p_data = entry_data_buff;
+	}
+
+	rc = dpp_dtb_smmu0_data_write_cycle(dev, queue_id, smmu0_base_addr,
+										smmu0_wr_mode, entry_num, p_entry_arr,
+										element_id);
+	ZXIC_COMM_FREE(p_entry_arr);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_data_write_cycle");
+
+	return rc;
 }
 
 /** dtb flush smmu0中的数据,大数据量
-* @param   dev_id          设备号
-* @param   queue_id        队列号
-* @param   smmu0_base_addr smmu0基地址，以128bit为单位
-* @param   smmu0_wr_mode   smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式
-* @param   start_index     flush开始的条目
-* @param   entry_num       下发的条目数
-* @param   element_id      返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2024/01/04
-************************************************************/
-DPP_STATUS dpp_dtb_smmu0_flush(DPP_DEV_T *dev,
-                               ZXIC_UINT32 queue_id,
-                               ZXIC_UINT32 smmu0_base_addr,
-                               ZXIC_UINT32 smmu0_wr_mode,
-                               ZXIC_UINT32 start_index,
-                               ZXIC_UINT32 entry_num,
-                               ZXIC_UINT32 *element_id)
+ * @param   dev_id          设备号
+ * @param   queue_id        队列号
+ * @param   smmu0_base_addr smmu0基地址，以128bit为单位
+ * @param   smmu0_wr_mode   smmu0写模式，参考DPP_ERAM128_OPR_MODE_E，仅支持128bit、64bit、1bit模式
+ * @param   start_index     flush开始的条目
+ * @param   entry_num       下发的条目数
+ * @param   element_id      返回下表使用的元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2024/01/04
+ ************************************************************/
+DPP_STATUS dpp_dtb_smmu0_flush(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+							   ZXIC_UINT32 smmu0_base_addr,
+							   ZXIC_UINT32 smmu0_wr_mode,
+							   ZXIC_UINT32 start_index, ZXIC_UINT32 entry_num,
+							   ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 entry_num_max = 0;
-    ZXIC_UINT32 entry_cycle = 0;
-    ZXIC_UINT32 entry_remains = 0;
-    ZXIC_UINT32 temp_start_index = 0;
-    ZXIC_UINT32 i = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    switch (smmu0_wr_mode)
-    {
-        case ERAM128_OPR_128b:
-        {
-            entry_num_max = 0x1ff;
-            break;
-        }
-
-        case ERAM128_OPR_64b:
-        {
-            entry_num_max = 0x3ff;
-            break;
-        }
-
-        case ERAM128_OPR_1b:
-        {
-            entry_num_max = 0x3ff;
-            break;
-        }
-    }
-
-    ZXIC_COMM_CHECK_INDEX_EQUAL(entry_num_max, 0);
-    entry_cycle = entry_num / entry_num_max;
-    entry_remains = entry_num % entry_num_max;
-
-    for(i = 0; i < entry_cycle; ++i)
-    {
-        temp_start_index = entry_num_max * i + start_index;
-
-        rc = dpp_dtb_smmu0_flush_cycle(dev, 
-                                       queue_id, 
-                                       smmu0_base_addr, 
-                                       smmu0_wr_mode, 
-                                       temp_start_index,
-                                       entry_num_max, 
-                                       element_id);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_flush_cycle");
-
-        ZXIC_COMM_TRACE_INFO("dpp_dtb_smmu0_flush_cycle[%d] element_id = %d\n",i,*element_id);
-    }
-
-    if(entry_remains)
-    {
-        temp_start_index = entry_num_max * entry_cycle + start_index;
-        rc = dpp_dtb_smmu0_flush_cycle(dev, 
-                                       queue_id, 
-                                       smmu0_base_addr, 
-                                       smmu0_wr_mode, 
-                                       temp_start_index,
-                                       entry_remains, 
-                                       element_id);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_flush_cycle");
-
-        ZXIC_COMM_TRACE_INFO("dpp_dtb_smmu0_flush_cycle: element_id = %d\n",*element_id);
-    }
-
-    return 0;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 entry_num_max = 0;
+	ZXIC_UINT32 entry_cycle = 0;
+	ZXIC_UINT32 entry_remains = 0;
+	ZXIC_UINT32 temp_start_index = 0;
+	ZXIC_UINT32 i = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	switch (smmu0_wr_mode) {
+	case ERAM128_OPR_128b: {
+		entry_num_max = 0x1ff;
+		break;
+	}
+
+	case ERAM128_OPR_64b: {
+		entry_num_max = 0x3ff;
+		break;
+	}
+
+	case ERAM128_OPR_1b: {
+		entry_num_max = 0x3ff;
+		break;
+	}
+	}
+
+	ZXIC_COMM_CHECK_INDEX_EQUAL(entry_num_max, 0);
+	entry_cycle = entry_num / entry_num_max;
+	entry_remains = entry_num % entry_num_max;
+
+	for (i = 0; i < entry_cycle; ++i) {
+		temp_start_index = entry_num_max * i + start_index;
+
+		rc = dpp_dtb_smmu0_flush_cycle(dev, queue_id, smmu0_base_addr,
+									   smmu0_wr_mode, temp_start_index,
+									   entry_num_max, element_id);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_flush_cycle");
+
+		ZXIC_COMM_TRACE_INFO("dpp_dtb_smmu0_flush_cycle[%d] element_id = %d\n",
+							 i, *element_id);
+	}
+
+	if (entry_remains) {
+		temp_start_index = entry_num_max * entry_cycle + start_index;
+		rc = dpp_dtb_smmu0_flush_cycle(dev, queue_id, smmu0_base_addr,
+									   smmu0_wr_mode, temp_start_index,
+									   entry_remains, element_id);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_flush_cycle");
+
+		ZXIC_COMM_TRACE_INFO("dpp_dtb_smmu0_flush_cycle: element_id = %d\n",
+							 *element_id);
+	}
+
+	return 0;
 }
 
 /** ddr直接表 写数据
-* @param   dev_id    芯片id
-* @param   base_addr  基地址，以4K*128bit为单位
-* @param   rw_len  数据位宽模式，位宽 0-128bit, 1-256bit, 2-384bit, 3-512bit,取值参考SMMU1_DDR_WRT_MODE_E的定义
-* @param   index   条目索引，以mode为单位
-* @param   ecc_en   直接表ECC使能位
-* @param   p_data   待写入的数据指针
-* @param   p_entry   组装好的条目(已分配好空间)
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30/
-************************************************************/
-DPP_STATUS dpp_dtb_ddr_dir_table_data_write(ZXIC_UINT32 dev_id, 
-                                        ZXIC_UINT32 base_addr,
-                                        ZXIC_UINT32 rw_len,
-                                        ZXIC_UINT32 index,
-                                        ZXIC_UINT32 ecc_en,
-                                        ZXIC_UINT8 *p_data, 
-                                        DPP_DTB_ENTRY_T *p_entry)
+ * @param   dev_id    芯片id
+ * @param   base_addr  基地址，以4K*128bit为单位
+ * @param   rw_len  数据位宽模式，位宽 0-128bit, 1-256bit, 2-384bit, 3-512bit,取值参考SMMU1_DDR_WRT_MODE_E的定义
+ * @param   index   条目索引，以mode为单位
+ * @param   ecc_en   直接表ECC使能位
+ * @param   p_data   待写入的数据指针
+ * @param   p_entry   组装好的条目(已分配好空间)
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30/
+ ************************************************************/
+DPP_STATUS
+dpp_dtb_ddr_dir_table_data_write(ZXIC_UINT32 dev_id, ZXIC_UINT32 base_addr,
+								 ZXIC_UINT32 rw_len, ZXIC_UINT32 index,
+								 ZXIC_UINT32 ecc_en, ZXIC_UINT8 *p_data,
+								 DPP_DTB_ENTRY_T *p_entry)
 {
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 ipv4_v6_flag = 0;
-    ZXIC_UINT32 lpm_vld = 0;
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(rw_len,SMMU1_DDR_WRT_512b);
-    ZXIC_COMM_CHECK_INDEX_UPPER(ecc_en,1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data);
-
-    rc =  dpp_dtb_smmu1_write_entry_data(dev_id, 
-                                        rw_len,
-                                        ipv4_v6_flag,
-                                        lpm_vld,
-                                        base_addr,
-                                        index,
-                                        ecc_en,
-                                        p_data, 
-                                        p_entry);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_write_entry_data");
-
-    return DPP_OK;
-}
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 ipv4_v6_flag = 0;
+	ZXIC_UINT32 lpm_vld = 0;
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(rw_len, SMMU1_DDR_WRT_512b);
+	ZXIC_COMM_CHECK_INDEX_UPPER(ecc_en, 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data);
 
+	rc = dpp_dtb_smmu1_write_entry_data(dev_id, rw_len, ipv4_v6_flag, lpm_vld,
+										base_addr, index, ecc_en, p_data,
+										p_entry);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_write_entry_data");
+
+	return DPP_OK;
+}
 
 /** ddr直接表 写数据
-* @param   dev_id    芯片id
-* @param   base_addr  基地址，以4K*128bit为单位
-* @param   rw_len  数据位宽模式，位宽 0-128bit, 1-256bit, 2-384bit, 3-512bit,取值参考SMMU1_DDR_WRT_MODE_E的定义
-* @param   index   条目索引，以mode为单位
-* @param   ecc_en   ecc是否使能
-* @param   p_data   待写入的数据指针
-* @param   p_entry   组装好的条目(已分配好空间)
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30/
-************************************************************/
-DPP_STATUS dpp_dtb_ddr_hash_table_data_write(ZXIC_UINT32 dev_id, 
-                                        ZXIC_UINT32 base_addr,
-                                        ZXIC_UINT32 rw_len,
-                                        ZXIC_UINT32 index,
-                                        ZXIC_UINT32 ecc_en,
-                                        ZXIC_UINT8 *p_data, 
-                                        DPP_DTB_ENTRY_T *p_entry)
+ * @param   dev_id    芯片id
+ * @param   base_addr  基地址，以4K*128bit为单位
+ * @param   rw_len  数据位宽模式，位宽 0-128bit, 1-256bit, 2-384bit, 3-512bit,取值参考SMMU1_DDR_WRT_MODE_E的定义
+ * @param   index   条目索引，以mode为单位
+ * @param   ecc_en   ecc是否使能
+ * @param   p_data   待写入的数据指针
+ * @param   p_entry   组装好的条目(已分配好空间)
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30/
+ ************************************************************/
+DPP_STATUS
+dpp_dtb_ddr_hash_table_data_write(ZXIC_UINT32 dev_id, ZXIC_UINT32 base_addr,
+								  ZXIC_UINT32 rw_len, ZXIC_UINT32 index,
+								  ZXIC_UINT32 ecc_en, ZXIC_UINT8 *p_data,
+								  DPP_DTB_ENTRY_T *p_entry)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 ipv4_v6_flag = 0;
-    ZXIC_UINT32 lpm_vld = 0;
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(rw_len,SMMU1_DDR_WRT_512b);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_entry);
-
-    rc =  dpp_dtb_smmu1_write_entry_data(dev_id, 
-                                        rw_len,
-                                        ipv4_v6_flag,
-                                        lpm_vld,
-                                        base_addr,
-                                        index,
-                                        ecc_en,
-                                        p_data, 
-                                        p_entry);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_write_entry_data");
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 ipv4_v6_flag = 0;
+	ZXIC_UINT32 lpm_vld = 0;
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(rw_len, SMMU1_DDR_WRT_512b);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_entry);
+
+	rc = dpp_dtb_smmu1_write_entry_data(dev_id, rw_len, ipv4_v6_flag, lpm_vld,
+										base_addr, index, ecc_en, p_data,
+										p_entry);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_write_entry_data");
+
+	return DPP_OK;
 }
 
 /** dtb 通道 se alg间接写zcam空间
-* @param   dev_id    芯片id
-* @param   addr  基地址，以4K*128bit为单位
-* @param   p_data   待写入的数据指针
-* @param   p_entry   组装好的条目(已分配好空间)
-*
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30/
-************************************************************/
-DPP_STATUS dpp_dtb_se_alg_zcam_data_write(ZXIC_UINT32 dev_id, 
-                                        ZXIC_UINT32 addr,
-                                        ZXIC_UINT8 *p_data, 
-                                        DPP_DTB_ENTRY_T *p_entry)
+ * @param   dev_id    芯片id
+ * @param   addr  基地址，以4K*128bit为单位
+ * @param   p_data   待写入的数据指针
+ * @param   p_entry   组装好的条目(已分配好空间)
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30/
+ ************************************************************/
+DPP_STATUS dpp_dtb_se_alg_zcam_data_write(ZXIC_UINT32 dev_id, ZXIC_UINT32 addr,
+										  ZXIC_UINT8 *p_data,
+										  DPP_DTB_ENTRY_T *p_entry)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 reg_sram_flag = 0;
-    ZXIC_UINT32 zgroup_id = 0;
-    ZXIC_UINT32 zblock_id = 0;
-    ZXIC_UINT32 zcell_id = 0;
-    ZXIC_UINT32 mask = 0;
-    ZXIC_UINT32 sram_addr = 0;
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_entry);
-
-    mask = (addr >> 17) & 0xF;
-    reg_sram_flag = (addr >> 16) & 0x1;
-    zgroup_id = (addr >> 14) & 0x3;
-    zblock_id = (addr >> 11) & 0x7;
-    zcell_id = (addr >> 9) & 0x3;
-    sram_addr = addr & 0x1FF;
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dpp_dtb_se_alg_zcam_data_write: \n");
-        ZXIC_COMM_DBGCNT32_PRINT("addr", addr);
-        ZXIC_COMM_DBGCNT32_PRINT("mask", mask);
-        ZXIC_COMM_DBGCNT32_PRINT("reg_sram_flag", reg_sram_flag);
-        ZXIC_COMM_DBGCNT32_PRINT("zgroup_id", zgroup_id);
-        ZXIC_COMM_DBGCNT32_PRINT("zblock_id", zblock_id);
-        ZXIC_COMM_DBGCNT32_PRINT("zcell_id", zcell_id);
-        ZXIC_COMM_DBGCNT32_PRINT("sram_addr", sram_addr);
-    }
-
-    rc = dpp_dtb_zcam_write_entry_data(dev_id, 
-                                         reg_sram_flag,
-                                         zgroup_id,
-                                         zblock_id,
-                                         zcell_id,
-                                         sram_addr,
-                                         mask,
-                                         p_data, 
-                                         p_entry);
-
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_zcam_write_entry_data");
-
-    return DPP_OK;       
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 reg_sram_flag = 0;
+	ZXIC_UINT32 zgroup_id = 0;
+	ZXIC_UINT32 zblock_id = 0;
+	ZXIC_UINT32 zcell_id = 0;
+	ZXIC_UINT32 mask = 0;
+	ZXIC_UINT32 sram_addr = 0;
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_entry);
+
+	mask = (addr >> 17) & 0xF;
+	reg_sram_flag = (addr >> 16) & 0x1;
+	zgroup_id = (addr >> 14) & 0x3;
+	zblock_id = (addr >> 11) & 0x7;
+	zcell_id = (addr >> 9) & 0x3;
+	sram_addr = addr & 0x1FF;
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dpp_dtb_se_alg_zcam_data_write: \n");
+		ZXIC_COMM_DBGCNT32_PRINT("addr", addr);
+		ZXIC_COMM_DBGCNT32_PRINT("mask", mask);
+		ZXIC_COMM_DBGCNT32_PRINT("reg_sram_flag", reg_sram_flag);
+		ZXIC_COMM_DBGCNT32_PRINT("zgroup_id", zgroup_id);
+		ZXIC_COMM_DBGCNT32_PRINT("zblock_id", zblock_id);
+		ZXIC_COMM_DBGCNT32_PRINT("zcell_id", zcell_id);
+		ZXIC_COMM_DBGCNT32_PRINT("sram_addr", sram_addr);
+	}
+
+	rc = dpp_dtb_zcam_write_entry_data(dev_id, reg_sram_flag, zgroup_id,
+									   zblock_id, zcell_id, sram_addr, mask,
+									   p_data, p_entry);
+
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_zcam_write_entry_data");
+
+	return DPP_OK;
 }
 
 #endif
 
 #if ZXIC_REAL("DOWN_TABLE")
 /** 将HASH表数据格式写入form_buff中
-* @param   p_hash_cfg    hash表配置指针
-* @param   p_rbkey_rtn   红黑树新节点信息指针
-* @param   entry_data    条目数据缓存缓存
-* 
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_hash_form_write(DPP_HASH_CFG *p_hash_cfg, 
-                               DPP_HASH_RBKEY_INFO *p_rbkey_new,
-                               ZXIC_UINT32 actu_key_size,
-                               DPP_DTB_ENTRY_T *p_entry)
+ * @param   p_hash_cfg    hash表配置指针
+ * @param   p_rbkey_rtn   红黑树新节点信息指针
+ * @param   entry_data    条目数据缓存缓存
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_hash_form_write(DPP_HASH_CFG *p_hash_cfg,
+								   DPP_HASH_RBKEY_INFO *p_rbkey_new,
+								   ZXIC_UINT32 actu_key_size,
+								   DPP_DTB_ENTRY_T *p_entry)
 {
-    ZXIC_UINT8 table_id = 0;
-    ZXIC_UINT32 key_type = 0;
-    ZXIC_UINT32 key_by_size = 0;
-    ZXIC_UINT32 rst_by_size = 0;
-    ZXIC_UINT32 byte_offset = 0;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT32 bulk_id = 0;
-    ZXIC_UINT32 temp_mask = 0;
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 ddr_wr_mode = 0;
-    ZXIC_UINT32 addr;
-
-    D_NODE *p_entry_dn = NULL;
-    HASH_DDR_CFG *p_ddr_cfg = NULL;
-    SE_ITEM_CFG *p_item_info = NULL;
-    DPP_HASH_RBKEY_INFO *p_rbkey = NULL;
-    ZXIC_UINT8 entry_data[SE_ENTRY_WIDTH_MAX] = {0};
-
-    ZXIC_COMM_CHECK_POINT(p_hash_cfg);
-    ZXIC_COMM_CHECK_POINT(p_rbkey_new);
-
-    dev_id = p_hash_cfg->p_se_info->dev_id;
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1);
-
-    ZXIC_COMM_MEMSET(entry_data,0x0,sizeof(entry_data));
-    p_item_info = p_rbkey_new->p_item_info;
-    ZXIC_COMM_CHECK_POINT(p_item_info);
-
-    if (p_item_info->item_type == ITEM_DDR_256 || p_item_info->item_type == ITEM_DDR_512)//hash条目存在DDR中
-    {
-        table_id = DPP_GET_HASH_TBL_ID(p_rbkey_new->key);
-        bulk_id = ((table_id >> 2) & 0x7);
-        ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id,HASH_BULK_NUM - 1);
-        p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id];
-        key_type = DPP_GET_HASH_KEY_TYPE(p_rbkey_new->key);
-        key_by_size = DPP_GET_KEY_SIZE(actu_key_size);
-
-        switch (key_type)
-        {
-            case HASH_KEY_128b:
-            {
-                rst_by_size = 16U - DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) - HASH_KEY_CTR_SIZE;
-                break;
-            }
-            case HASH_KEY_256b:
-            {
-                rst_by_size = 32U - DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) - HASH_KEY_CTR_SIZE;
-                break;
-            }
-            case HASH_KEY_512b:
-            {
-                rst_by_size = 64U - DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) - HASH_KEY_CTR_SIZE;
-                break;
-            }
-            default:
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n ErrorCode[%x]: Invalid key type.", DPP_HASH_RC_INVALID_KEY_TYPE);
-                return DPP_HASH_RC_INVALID_KEY_TYPE;
-            }
-
-        }
-
-        /* 计算index */
-        if (DDR_WIDTH_256b == p_ddr_cfg->width_mode)
-        {
-            if (HASH_KEY_128b == key_type)
-            {
-                index = (p_item_info->hw_addr << 1) + p_rbkey_new->entry_pos;
-            }
-            else if (HASH_KEY_256b == key_type)
-            {
-                index = p_item_info->hw_addr;
-            }
-        }
-        else if (DDR_WIDTH_512b == p_ddr_cfg->width_mode)
-        {
-            if (HASH_KEY_128b == key_type)
-            {
-                index = (p_item_info->hw_addr << 2) + p_rbkey_new->entry_pos;
-            }
-            else if (HASH_KEY_256b == key_type)
-            {
-                index = (p_item_info->hw_addr << 2) + p_rbkey_new->entry_pos;
-                index = index >> 1;
-            }
-            else
-            {
-                index = p_item_info->hw_addr;
-            }
-        }
-
-        ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "ddr index(unit by key_type) is 0x%x \n", index);
-        
-        ddr_wr_mode = DPP_GET_DDR_WR_MODE(key_type);
-        
-        /*将数据组合成一个数组中并写入缓存中进行保存*/
-        ZXIC_COMM_MEMCPY(entry_data, p_rbkey_new->key, key_by_size);
-        ZXIC_COMM_MEMCPY(entry_data + key_by_size, p_rbkey_new->rst, ((rst_by_size > HASH_RST_MAX) ? HASH_RST_MAX : rst_by_size));
-        zxic_comm_swap(entry_data, SE_ENTRY_WIDTH_MAX);
-        dpp_dtb_ddr_hash_table_data_write(dev_id,
-                                          p_ddr_cfg->ddr_baddr,
-                                          ddr_wr_mode,
-                                          index,
-                                          p_ddr_cfg->ddr_ecc_en,
-                                          entry_data,
-                                          p_entry); 
-        ZXIC_COMM_TRACE_DEBUG("entry_data is:");
-
-        for (i = 0; i < SE_ENTRY_WIDTH_MAX; i++)
-        {
-            ZXIC_COMM_TRACE_DEBUG("0x%02x ", entry_data[i]);
-        }
-
-        ZXIC_COMM_TRACE_DEBUG("\n");
-
-    }
-    else /* hash条目存在zcam上*/
-    {
-        /*写ZCAM表格式*/
-        ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "zcam p_item_info->hw_addr is 0x%x \n", p_item_info->hw_addr);
-        addr = p_item_info->hw_addr;
- 
-        /*将数据组合成一个数组中并写入缓存中进行保存*/
-        p_entry_dn = p_item_info->item_list.p_next;
-
-        while (p_entry_dn)
-        {
-            p_rbkey = (DPP_HASH_RBKEY_INFO *)(p_entry_dn->data);
-            // table_id = DPP_GET_HASH_TBL_ID(p_rbkey->key);
-            key_type = DPP_GET_HASH_KEY_TYPE(p_rbkey->key);
-            key_by_size = DPP_GET_KEY_SIZE(actu_key_size);
-            ZXIC_COMM_CHECK_INDEX_UPPER(key_by_size,HASH_KEY_MAX);
-            rst_by_size = DPP_GET_RST_SIZE(key_type, actu_key_size);
-
-            byte_offset = p_rbkey->entry_pos * HASH_ENTRY_POS_STEP;
-            ZXIC_COMM_MEMCPY(entry_data + byte_offset, p_rbkey->key, key_by_size);
-            ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, byte_offset, key_by_size);
-            byte_offset += key_by_size;
-            ZXIC_COMM_MEMCPY(entry_data + byte_offset, p_rbkey->rst, ((rst_by_size > HASH_RST_MAX) ? HASH_RST_MAX : rst_by_size));
-
-            temp_mask |=  ((((1U << (p_rbkey->entry_size/16U)) - 1U) << (4U - p_rbkey->entry_size/16U - p_rbkey->entry_pos)) & 0xF);//计算掩码
-
-            p_entry_dn = p_entry_dn->next;
-        }
-
-        zxic_comm_swap(entry_data, SE_ENTRY_WIDTH_MAX);
-
-        dpp_dtb_se_alg_zcam_data_write(dev_id,
-                                       addr,
-                                       entry_data,
-                                       p_entry);
-
-        ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "zcam_item_data is:");
-
-        for (i = 0; i < SE_ITEM_WIDTH_MAX; i++)
-        {
-            ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "0x%02x ", entry_data[i]);
-        }
-
-        ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "\n");
-    }
-
-    return DPP_OK;
+	ZXIC_UINT8 table_id = 0;
+	ZXIC_UINT32 key_type = 0;
+	ZXIC_UINT32 key_by_size = 0;
+	ZXIC_UINT32 rst_by_size = 0;
+	ZXIC_UINT32 byte_offset = 0;
+
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 bulk_id = 0;
+	ZXIC_UINT32 temp_mask = 0;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 ddr_wr_mode = 0;
+	ZXIC_UINT32 addr;
+
+	D_NODE *p_entry_dn = NULL;
+	HASH_DDR_CFG *p_ddr_cfg = NULL;
+	SE_ITEM_CFG *p_item_info = NULL;
+	DPP_HASH_RBKEY_INFO *p_rbkey = NULL;
+	ZXIC_UINT8 entry_data[SE_ENTRY_WIDTH_MAX] = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(p_hash_cfg);
+	ZXIC_COMM_CHECK_POINT(p_rbkey_new);
+
+	dev_id = p_hash_cfg->p_se_info->dev_id;
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+
+	ZXIC_COMM_MEMSET(entry_data, 0x0, sizeof(entry_data));
+	p_item_info = p_rbkey_new->p_item_info;
+	ZXIC_COMM_CHECK_POINT(p_item_info);
+
+	if (p_item_info->item_type == ITEM_DDR_256 ||
+		p_item_info->item_type == ITEM_DDR_512) { // hash条目存在DDR中
+		table_id = DPP_GET_HASH_TBL_ID(p_rbkey_new->key);
+		bulk_id = ((table_id >> 2) & 0x7);
+		ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id, HASH_BULK_NUM - 1);
+		p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id];
+		key_type = DPP_GET_HASH_KEY_TYPE(p_rbkey_new->key);
+		key_by_size = DPP_GET_KEY_SIZE(actu_key_size);
+
+		switch (key_type) {
+		case HASH_KEY_128b: {
+			rst_by_size = 16U - DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) -
+						  HASH_KEY_CTR_SIZE;
+			break;
+		}
+		case HASH_KEY_256b: {
+			rst_by_size = 32U - DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) -
+						  HASH_KEY_CTR_SIZE;
+			break;
+		}
+		case HASH_KEY_512b: {
+			rst_by_size = 64U - DPP_GET_ACTU_KEY_BY_SIZE(actu_key_size) -
+						  HASH_KEY_CTR_SIZE;
+			break;
+		}
+		default: {
+			ZXIC_COMM_TRACE_DEV_ERROR(dev_id,
+									  "\n ErrorCode[%x]: Invalid key type.",
+									  DPP_HASH_RC_INVALID_KEY_TYPE);
+			return DPP_HASH_RC_INVALID_KEY_TYPE;
+		}
+		}
+
+		/* 计算index */
+		if (DDR_WIDTH_256b == p_ddr_cfg->width_mode) {
+			if (HASH_KEY_128b == key_type) {
+				index = (p_item_info->hw_addr << 1) + p_rbkey_new->entry_pos;
+			} else if (HASH_KEY_256b == key_type) {
+				index = p_item_info->hw_addr;
+			}
+		} else if (DDR_WIDTH_512b == p_ddr_cfg->width_mode) {
+			if (HASH_KEY_128b == key_type) {
+				index = (p_item_info->hw_addr << 2) + p_rbkey_new->entry_pos;
+			} else if (HASH_KEY_256b == key_type) {
+				index = (p_item_info->hw_addr << 2) + p_rbkey_new->entry_pos;
+				index = index >> 1;
+			} else {
+				index = p_item_info->hw_addr;
+			}
+		}
+
+		ZXIC_COMM_TRACE_DEV_DEBUG(
+				dev_id, "ddr index(unit by key_type) is 0x%x \n", index);
+
+		ddr_wr_mode = DPP_GET_DDR_WR_MODE(key_type);
+
+		/*将数据组合成一个数组中并写入缓存中进行保存*/
+		ZXIC_COMM_MEMCPY(entry_data, p_rbkey_new->key, key_by_size);
+		ZXIC_COMM_MEMCPY(entry_data + key_by_size, p_rbkey_new->rst,
+						 ((rst_by_size > HASH_RST_MAX) ? HASH_RST_MAX :
+														   rst_by_size));
+		zxic_comm_swap(entry_data, SE_ENTRY_WIDTH_MAX);
+		dpp_dtb_ddr_hash_table_data_write(dev_id, p_ddr_cfg->ddr_baddr,
+										  ddr_wr_mode, index,
+										  p_ddr_cfg->ddr_ecc_en, entry_data,
+										  p_entry);
+		ZXIC_COMM_TRACE_DEBUG("entry_data is:");
+
+		for (i = 0; i < SE_ENTRY_WIDTH_MAX; i++) {
+			ZXIC_COMM_TRACE_DEBUG("0x%02x ", entry_data[i]);
+		}
+
+		ZXIC_COMM_TRACE_DEBUG("\n");
+	} else { /* hash条目存在zcam上*/
+		/*写ZCAM表格式*/
+		ZXIC_COMM_TRACE_DEV_DEBUG(dev_id,
+								  "zcam p_item_info->hw_addr is 0x%x \n",
+								  p_item_info->hw_addr);
+		addr = p_item_info->hw_addr;
+
+		/*将数据组合成一个数组中并写入缓存中进行保存*/
+		p_entry_dn = p_item_info->item_list.p_next;
+
+		while (p_entry_dn) {
+			p_rbkey = (DPP_HASH_RBKEY_INFO *)(p_entry_dn->data);
+			table_id = DPP_GET_HASH_TBL_ID(p_rbkey->key);
+			key_type = DPP_GET_HASH_KEY_TYPE(p_rbkey->key);
+			key_by_size = DPP_GET_KEY_SIZE(actu_key_size);
+			ZXIC_COMM_CHECK_INDEX_UPPER(key_by_size, HASH_KEY_MAX);
+			rst_by_size = DPP_GET_RST_SIZE(key_type, actu_key_size);
+
+			byte_offset = p_rbkey->entry_pos * HASH_ENTRY_POS_STEP;
+			ZXIC_COMM_MEMCPY(entry_data + byte_offset, p_rbkey->key,
+							 key_by_size);
+			ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(
+					dev_id, byte_offset, key_by_size);
+			byte_offset += key_by_size;
+			ZXIC_COMM_MEMCPY(entry_data + byte_offset, p_rbkey->rst,
+							 ((rst_by_size > HASH_RST_MAX) ? HASH_RST_MAX :
+															   rst_by_size));
+
+			temp_mask |= ((((1U << (p_rbkey->entry_size / 16U)) - 1U)
+						   << (4U - p_rbkey->entry_size / 16U -
+							   p_rbkey->entry_pos)) &
+						  0xF); //计算掩码
+
+			p_entry_dn = p_entry_dn->next;
+		}
+
+		zxic_comm_swap(entry_data, SE_ENTRY_WIDTH_MAX);
+
+		dpp_dtb_se_alg_zcam_data_write(dev_id, addr, entry_data, p_entry);
+
+		ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "zcam_item_data is:");
+
+		for (i = 0; i < SE_ITEM_WIDTH_MAX; i++) {
+			ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "0x%02x ", entry_data[i]);
+		}
+
+		ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "\n");
+	}
+
+	return DPP_OK;
 }
 
-
 /** 增加hash表条目时写buff函数
-* @param   dev_id              设备号
-* @param   p_hash_entry_cfg    该hash条目的格式内容信息
-* @param   p_data_buff         保存用于dtb下表数据的buff
-* @param   index               该hash条目的编号
-* @param   p_dtb_len           下发完该hash表条目后dtb数据的长度
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/06/03
-************************************************************/
+ * @param   dev_id              设备号
+ * @param   p_hash_entry_cfg    该hash条目的格式内容信息
+ * @param   p_data_buff         保存用于dtb下表数据的buff
+ * @param   index               该hash条目的编号
+ * @param   p_dtb_len           下发完该hash表条目后dtb数据的长度
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/06/03
+ ************************************************************/
 DPP_STATUS dpp_dtb_add_hash_buf_write(ZXIC_UINT32 dev_id,
-                               HASH_ENTRY_CFG *p_hash_entry_cfg,
-                               ZXIC_UINT8 *p_data_buff,
-                               ZXIC_UINT32 index,
-                               ZXIC_UINT32 *p_dtb_len)
+									  HASH_ENTRY_CFG *p_hash_entry_cfg,
+									  ZXIC_UINT8 *p_data_buff,
+									  ZXIC_UINT32 index, ZXIC_UINT32 *p_dtb_len)
 {
-    DPP_STATUS rc = DPP_OK;
-    SE_ITEM_CFG *p_item_info = NULL;
-    ZXIC_UINT32 ddr_wr_mode = 0;
-    ZXIC_UINT32 addr_offset = 0;
-    DPP_DTB_ENTRY_T dtb_one_entry = {0};  /*条目结构*/
-    ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0};  /*命令格式缓存*/
-    ZXIC_UINT8 hash_entry_data[SE_ENTRY_WIDTH_MAX] = {0}; 
-
-    ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg->p_rbkey_new);
-    ZXIC_COMM_CHECK_POINT(p_dtb_len);
-
-    ZXIC_COMM_MEMSET(cmd_buff,0x0,sizeof(cmd_buff));
-    ZXIC_COMM_MEMSET(hash_entry_data,0x0,sizeof(hash_entry_data));
-    dtb_one_entry.cmd = cmd_buff;
-    dtb_one_entry.data = hash_entry_data;
-
-     /*将位置信息和数据信息写入buff中*/
-    rc = dpp_dtb_hash_form_write(p_hash_entry_cfg->p_hash_cfg, 
-                                 p_hash_entry_cfg->p_rbkey_new, 
-                                 p_hash_entry_cfg->actu_key_size, 
-                                 &dtb_one_entry); /*计算一个条目的位置信息，并保存起来*/
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_dtb_hash_form_write");
-    
-    p_item_info = p_hash_entry_cfg->p_rbkey_new->p_item_info;
-    ZXIC_COMM_CHECK_POINT(p_item_info);
-    ddr_wr_mode = DPP_GET_DDR_WR_MODE(p_hash_entry_cfg->key_type);
-
-    /*将数据写入缓存中，并更新长度统计*/
-    if(p_item_info->item_type == ITEM_DDR_256 || p_item_info->item_type == ITEM_DDR_512)
-    {
-        dtb_one_entry.data_size = DTB_LEN_POS_SETP * (ddr_wr_mode + 1);
-        addr_offset = index * (ddr_wr_mode + 2) * DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/
-        (*p_dtb_len) += (ddr_wr_mode + 2);//dtb长度进行计数
-    }
-    else/*ram or reg*/
-    {
-        dtb_one_entry.data_size = DTB_LEN_POS_SETP * (DTB_ZCAM_LEN_SIZE - 1);
-        addr_offset = index * DTB_ZCAM_LEN_SIZE * DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/
-        (*p_dtb_len) += DTB_ZCAM_LEN_SIZE;//dtb长度进行计数
-    }
-
-    rc = dpp_dtb_data_write(p_data_buff, addr_offset, &dtb_one_entry);  /*将数据写入缓存中*/
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_data_write");
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+	SE_ITEM_CFG *p_item_info = NULL;
+	ZXIC_UINT32 ddr_wr_mode = 0;
+	ZXIC_UINT32 addr_offset = 0;
+	DPP_DTB_ENTRY_T dtb_one_entry = { 0 }; /*条目结构*/
+	ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = { 0 }; /*命令格式缓存*/
+	ZXIC_UINT8 hash_entry_data[SE_ENTRY_WIDTH_MAX] = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg->p_rbkey_new);
+	ZXIC_COMM_CHECK_POINT(p_dtb_len);
+
+	ZXIC_COMM_MEMSET(cmd_buff, 0x0, sizeof(cmd_buff));
+	ZXIC_COMM_MEMSET(hash_entry_data, 0x0, sizeof(hash_entry_data));
+	dtb_one_entry.cmd = cmd_buff;
+	dtb_one_entry.data = hash_entry_data;
+
+	/*将位置信息和数据信息写入buff中*/
+	rc = dpp_dtb_hash_form_write(
+			p_hash_entry_cfg->p_hash_cfg, p_hash_entry_cfg->p_rbkey_new,
+			p_hash_entry_cfg->actu_key_size,
+			&dtb_one_entry); /*计算一个条目的位置信息，并保存起来*/
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_dtb_hash_form_write");
+
+	p_item_info = p_hash_entry_cfg->p_rbkey_new->p_item_info;
+	ZXIC_COMM_CHECK_POINT(p_item_info);
+	ddr_wr_mode = DPP_GET_DDR_WR_MODE(p_hash_entry_cfg->key_type);
+
+	/*将数据写入缓存中，并更新长度统计*/
+	if (p_item_info->item_type == ITEM_DDR_256 ||
+		p_item_info->item_type == ITEM_DDR_512) {
+		dtb_one_entry.data_size = DTB_LEN_POS_SETP * (ddr_wr_mode + 1);
+		addr_offset = index * (ddr_wr_mode + 2) *
+					  DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/
+		(*p_dtb_len) += (ddr_wr_mode + 2); // dtb长度进行计数
+	} else {/*ram or reg*/
+		dtb_one_entry.data_size = DTB_LEN_POS_SETP * (DTB_ZCAM_LEN_SIZE - 1);
+		addr_offset = index * DTB_ZCAM_LEN_SIZE *
+					  DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/
+		(*p_dtb_len) += DTB_ZCAM_LEN_SIZE; // dtb长度进行计数
+	}
+
+	rc = dpp_dtb_data_write(p_data_buff, addr_offset,
+							&dtb_one_entry); /*将数据写入缓存中*/
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_data_write");
+
+	return rc;
 }
 
 /** 删除hash表条目时写buff函数
-* @param   dev_id              设备号
-* @param   p_hash_entry_cfg    该hash条目的格式内容信息
-* @param   p_data_buff         保存用于dtb下表数据的buff
-* @param   index               该hash条目的编号
-* @param   p_dtb_len           下发完该hash表条目后dtb数据的长度
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/06/03
-************************************************************/
+ * @param   dev_id              设备号
+ * @param   p_hash_entry_cfg    该hash条目的格式内容信息
+ * @param   p_data_buff         保存用于dtb下表数据的buff
+ * @param   index               该hash条目的编号
+ * @param   p_dtb_len           下发完该hash表条目后dtb数据的长度
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/06/03
+ ************************************************************/
 DPP_STATUS dpp_dtb_delete_hash_buf_write(ZXIC_UINT32 dev_id,
-                               HASH_ENTRY_CFG *p_hash_entry_cfg,
-                               ZXIC_UINT8 *p_data_buff,
-                               ZXIC_UINT32 index,
-                               ZXIC_UINT32 *p_dtb_len)
+										 HASH_ENTRY_CFG *p_hash_entry_cfg,
+										 ZXIC_UINT8 *p_data_buff,
+										 ZXIC_UINT32 index,
+										 ZXIC_UINT32 *p_dtb_len)
 {
-    DPP_STATUS rc = DPP_OK;
-    SE_ITEM_CFG *p_item_info = NULL;
-    ZXIC_UINT32 ddr_wr_mode = 0;
-    ZXIC_UINT32 addr_offset = 0;
-    DPP_DTB_ENTRY_T dtb_one_entry = {0};  /*条目结构*/
-    ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0};  /*命令格式缓存*/
-    ZXIC_UINT8 hash_entry_data[SE_ENTRY_WIDTH_MAX] = {0}; 
-
-    ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg->p_rbkey_new);
-    ZXIC_COMM_CHECK_POINT(p_dtb_len);
-
-    ZXIC_COMM_MEMSET(cmd_buff,0x0,sizeof(cmd_buff));
-    ZXIC_COMM_MEMSET(hash_entry_data,0x0,sizeof(hash_entry_data));
-    dtb_one_entry.cmd = cmd_buff;
-    dtb_one_entry.data = hash_entry_data;
-
-     /*将位置信息和数据信息写入buff中*/
-    rc = dpp_dtb_hash_form_write(p_hash_entry_cfg->p_hash_cfg, 
-                                 p_hash_entry_cfg->p_rbkey_new, 
-                                 p_hash_entry_cfg->actu_key_size, 
-                                 &dtb_one_entry); /*计算一个条目的位置信息，并保存起来*/
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_dtb_hash_form_write");
-    
-    p_item_info = p_hash_entry_cfg->p_rbkey_new->p_item_info;
-    ZXIC_COMM_CHECK_POINT(p_item_info);
-    ddr_wr_mode = DPP_GET_DDR_WR_MODE(p_hash_entry_cfg->key_type);
-
-    /*将数据写入缓存中，并更新长度统计*/
-    if(p_item_info->item_type == ITEM_DDR_256 || p_item_info->item_type == ITEM_DDR_512)
-    {
-        dtb_one_entry.data_size = DTB_LEN_POS_SETP * (ddr_wr_mode + 1);
-        addr_offset = index * (ddr_wr_mode + 2) * DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/
-        (*p_dtb_len) += (ddr_wr_mode + 2);//dtb长度进行计数
-    }
-    else/*ram or reg*/
-    {
-        dtb_one_entry.data_size = DTB_LEN_POS_SETP * (DTB_ZCAM_LEN_SIZE - 1);
-        addr_offset = index * DTB_ZCAM_LEN_SIZE * DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/
-        (*p_dtb_len) += DTB_ZCAM_LEN_SIZE;//dtb长度进行计数
-    }
-
-    ZXIC_COMM_MEMSET(dtb_one_entry.data, 0x0, dtb_one_entry.data_size);//清除下表数据
-
-    rc = dpp_dtb_data_write(p_data_buff, addr_offset, &dtb_one_entry);  /*将数据写入缓存中*/
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_data_write");
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+	SE_ITEM_CFG *p_item_info = NULL;
+	ZXIC_UINT32 ddr_wr_mode = 0;
+	ZXIC_UINT32 addr_offset = 0;
+	DPP_DTB_ENTRY_T dtb_one_entry = { 0 }; /*条目结构*/
+	ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = { 0 }; /*命令格式缓存*/
+	ZXIC_UINT8 hash_entry_data[SE_ENTRY_WIDTH_MAX] = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg->p_rbkey_new);
+	ZXIC_COMM_CHECK_POINT(p_dtb_len);
+
+	ZXIC_COMM_MEMSET(cmd_buff, 0x0, sizeof(cmd_buff));
+	ZXIC_COMM_MEMSET(hash_entry_data, 0x0, sizeof(hash_entry_data));
+	dtb_one_entry.cmd = cmd_buff;
+	dtb_one_entry.data = hash_entry_data;
+
+	/*将位置信息和数据信息写入buff中*/
+	rc = dpp_dtb_hash_form_write(
+			p_hash_entry_cfg->p_hash_cfg, p_hash_entry_cfg->p_rbkey_new,
+			p_hash_entry_cfg->actu_key_size,
+			&dtb_one_entry); /*计算一个条目的位置信息，并保存起来*/
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_dtb_hash_form_write");
+
+	p_item_info = p_hash_entry_cfg->p_rbkey_new->p_item_info;
+	ZXIC_COMM_CHECK_POINT(p_item_info);
+	ddr_wr_mode = DPP_GET_DDR_WR_MODE(p_hash_entry_cfg->key_type);
+
+	/*将数据写入缓存中，并更新长度统计*/
+	if (p_item_info->item_type == ITEM_DDR_256 ||
+		p_item_info->item_type == ITEM_DDR_512) {
+		dtb_one_entry.data_size = DTB_LEN_POS_SETP * (ddr_wr_mode + 1);
+		addr_offset = index * (ddr_wr_mode + 2) *
+					  DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/
+		(*p_dtb_len) += (ddr_wr_mode + 2); // dtb长度进行计数
+	} else {/*ram or reg*/
+		dtb_one_entry.data_size = DTB_LEN_POS_SETP * (DTB_ZCAM_LEN_SIZE - 1);
+		addr_offset = index * DTB_ZCAM_LEN_SIZE *
+					  DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/
+		(*p_dtb_len) += DTB_ZCAM_LEN_SIZE; // dtb长度进行计数
+	}
+
+	ZXIC_COMM_MEMSET(dtb_one_entry.data, 0x0,
+					 dtb_one_entry.data_size); //清除下表数据
+
+	rc = dpp_dtb_data_write(p_data_buff, addr_offset,
+							&dtb_one_entry); /*将数据写入缓存中*/
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_data_write");
+
+	return rc;
 }
 
-
-
 /***********************************************************/
 /** dtb 添加eTcam表条目,将etcam条目内容写入到entry中
-* @param   dev_id     设备号
-* @param   addr       每个block中的ram地址，位宽为8*80bit
-* @param   block_idx  block编号，范围0~7
-* @param   wr_mask    写表掩码，共8bit，每bit控制ram中对应位置的80bit数据是否有效
-* @param   opr_type   etcam操作类型，详见 DPP_ETCAM_OPR_TYPE_E
-* @param   p_entry    条目数据，data和mask
-* @param   p_entry_data   组装好的数据条目(已分配好空间)
-* @param   p_entry_mask   组装好的掩码条目(已分配好空间)
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/04/03
-************************************************************/
-DPP_STATUS dpp_dtb_etcam_entry_add(DPP_DEV_T *dev, 
-                               ZXIC_UINT32 addr,
-                               ZXIC_UINT32 block_idx,
-                               ZXIC_UINT32 wr_mask,
-                               ZXIC_UINT32 opr_type,
-                               DPP_ETCAM_ENTRY_T *p_entry,
-                               DPP_DTB_ENTRY_T *p_entry_data,
-                               DPP_DTB_ENTRY_T *p_entry_mask
-                               )
+ * @param   dev_id     设备号
+ * @param   addr       每个block中的ram地址，位宽为8*80bit
+ * @param   block_idx  block编号，范围0~7
+ * @param   wr_mask    写表掩码，共8bit，每bit控制ram中对应位置的80bit数据是否有效
+ * @param   opr_type   etcam操作类型，详见 DPP_ETCAM_OPR_TYPE_E
+ * @param   p_entry    条目数据，data和mask
+ * @param   p_entry_data   组装好的数据条目(已分配好空间)
+ * @param   p_entry_mask   组装好的掩码条目(已分配好空间)
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/04/03
+ ************************************************************/
+DPP_STATUS dpp_dtb_etcam_entry_add(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+								   ZXIC_UINT32 block_idx, ZXIC_UINT32 wr_mask,
+								   ZXIC_UINT32 opr_type,
+								   DPP_ETCAM_ENTRY_T *p_entry,
+								   DPP_DTB_ENTRY_T *p_entry_data,
+								   DPP_DTB_ENTRY_T *p_entry_mask)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    DPP_ETCAM_ENTRY_T entry_xy = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), addr, 0, DPP_ETCAM_RAM_DEPTH - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mask, 0, DPP_ETCAM_WR_MASK_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), opr_type, DPP_ETCAM_OPR_DM, DPP_ETCAM_OPR_XY);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_data);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_mask);
-
-    ZXIC_COMM_ASSERT(p_entry->p_data && p_entry->p_mask);
-
-    entry_xy.p_data = temp_data;
-    entry_xy.p_mask = temp_mask;
-
-    if (opr_type == DPP_ETCAM_OPR_DM)
-    {
-        /* convert user D/M data to X/Y */
-        rc = dpp_etcam_dm_to_xy(p_entry, &entry_xy, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_etcam_dm_to_xy"); 
-    }
-    else
-    {
-        ZXIC_COMM_MEMCPY(entry_xy.p_data, p_entry->p_data, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));//复制出实际的数据
-        ZXIC_COMM_MEMCPY(entry_xy.p_mask, p_entry->p_mask, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));
-    }
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("etcam xy:/n");
-        dpp_acl_data_print(entry_xy.p_data, entry_xy.p_mask, p_entry->mode);
-    }
-
-    /*组装data格式*/
-    rc = dpp_dtb_etcam_write_entry_data(dev, 
-                                        block_idx,
-                                        0,
-                                        1,
-                                        0,
-                                        0,
-                                        0,//0:写;1读
-                                        wr_mask,
-                                        DPP_ETCAM_DTYPE_DATA,
-                                        addr,
-                                        0,
-                                        entry_xy.p_data, 
-                                        p_entry_data);
-
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_etcam_write_entry_data"); 
-
-       /*组装mask格式*/
-    rc =  dpp_dtb_etcam_write_entry_data(dev, 
-                                        block_idx,
-                                        0,
-                                        1,
-                                        0,
-                                        0,
-                                        0,
-                                        wr_mask ,
-                                        DPP_ETCAM_DTYPE_MASK ,
-                                        addr ,
-                                        0xFF,
-                                        entry_xy.p_mask, 
-                                        p_entry_mask);
-
-   ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_etcam_write_entry_data"); 
-
-   return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	DPP_ETCAM_ENTRY_T entry_xy = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), addr, 0, DPP_ETCAM_RAM_DEPTH - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0,
+							  DPP_ETCAM_BLOCK_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), wr_mask, 0, DPP_ETCAM_WR_MASK_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), opr_type, DPP_ETCAM_OPR_DM,
+							  DPP_ETCAM_OPR_XY);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_data);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_mask);
+
+	ZXIC_COMM_ASSERT(p_entry->p_data && p_entry->p_mask);
+
+	entry_xy.p_data = temp_data;
+	entry_xy.p_mask = temp_mask;
+
+	if (opr_type == DPP_ETCAM_OPR_DM) {
+		/* convert user D/M data to X/Y */
+		rc = dpp_etcam_dm_to_xy(p_entry, &entry_xy,
+								DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));
+	} else {
+		ZXIC_COMM_MEMCPY(
+				entry_xy.p_data, p_entry->p_data,
+				DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); //复制出实际的数据
+		ZXIC_COMM_MEMCPY(entry_xy.p_mask, p_entry->p_mask,
+						 DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));
+	}
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("etcam xy:/n");
+		dpp_acl_data_print(entry_xy.p_data, entry_xy.p_mask, p_entry->mode);
+	}
+
+	/*组装data格式*/
+	rc = dpp_dtb_etcam_write_entry_data(dev, block_idx, 0, 1, 0, 0,
+										0, // 0:写;1读
+										wr_mask, DPP_ETCAM_DTYPE_DATA, addr, 0,
+										entry_xy.p_data, p_entry_data);
+
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_etcam_write_entry_data");
+
+	/*组装mask格式*/
+	rc = dpp_dtb_etcam_write_entry_data(dev, block_idx, 0, 1, 0, 0, 0, wr_mask,
+										DPP_ETCAM_DTYPE_MASK, addr, 0xFF,
+										entry_xy.p_mask, p_entry_mask);
+
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_etcam_write_entry_data");
+
+	return DPP_OK;
 }
 
 /** dtb写eRam表
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   sdt_no    eram表sdt表号
-* @param   entry_cnt 下发的条目数
-* @param   p_entry_arr   待下发表项内容结构体数组指针
-* @param   element_id   返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_eram_dma_write_cycle(DPP_DEV_T *dev, 
-                                      ZXIC_UINT32 queue_id, 
-                                      ZXIC_UINT32 sdt_no, 
-                                      ZXIC_UINT32 entry_num, 
-                                      DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr,
-                                      ZXIC_UINT32 *element_id
-                                      )
+ * @param   dev_id    设备号
+ * @param   queue_id  队列号
+ * @param   sdt_no    eram表sdt表号
+ * @param   entry_cnt 下发的条目数
+ * @param   p_entry_arr   待下发表项内容结构体数组指针
+ * @param   element_id   返回下表使用的元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_eram_dma_write_cycle(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+										ZXIC_UINT32 sdt_no,
+										ZXIC_UINT32 entry_num,
+										DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr,
+										ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS  rc = DPP_OK;
-    
-    ZXIC_UINT32 wrt_mode;
-    ZXIC_UINT32 base_addr;
-    ZXIC_UINT32 index;
-    ZXIC_UINT32 item_cnt = 0;
-    ZXIC_UINT32 addr_offset = 0;
-    ZXIC_UINT32 *p_entry_data = NULL;
-    ZXIC_UINT32 dtb_len = 0;
-
-    ZXIC_UINT8 *table_data_buff = NULL;
-    ZXIC_UINT32 entry_data_buff[4] = {0};
-    ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0};
-
-    DPP_SDTTBL_ERAM_T sdt_eram_info = {0};
-    DPP_DTB_ENTRY_T   dtb_one_entry = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_arr);
-
-    //分配下表数据缓存 16K
-    table_data_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), table_data_buff);
-    ZXIC_COMM_MEMSET(table_data_buff, 0, DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
-
-    dtb_one_entry.cmd = cmd_buff;
-    dtb_one_entry.data = (ZXIC_UINT8 *)entry_data_buff;
-
-    //从sdt_no中获取SDT配置
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_eram_info);
-    ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get", table_data_buff);
-    base_addr = sdt_eram_info.eram_base_addr;
-    wrt_mode = sdt_eram_info.eram_mode;//3:128
-
-    switch (wrt_mode)
-    {
-        case ERAM128_TBL_128b:
-        {
-            wrt_mode = ERAM128_OPR_128b;
-            break;
-        }
-
-        case ERAM128_TBL_64b:
-        {
-            wrt_mode = ERAM128_OPR_64b;
-            break;
-        }
-
-        case ERAM128_TBL_1b:
-        {
-            wrt_mode = ERAM128_OPR_1b;
-            break;
-        }
-    }
-
-    for(item_cnt = 0; item_cnt < entry_num; ++item_cnt)
-    {
-        p_entry_data = (ZXIC_UINT32 *)p_entry_arr[item_cnt].p_data;
-        ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE(DEV_ID(dev), p_entry_data, table_data_buff);
-        index = p_entry_arr[item_cnt].index;
-
-        if(dpp_dtb_prt_get())
-        {
-            ZXIC_COMM_PRINT("dpp_dtb_eram_dma_write_cycle : the item index is %d !\n", index);
-        }
-        
-        //将一个数据写入entry
-        rc = dpp_dtb_se_smmu0_ind_write(dev,
-                                   base_addr, 
-                                   index, 
-                                   wrt_mode,
-                                   p_entry_data,
-                                   &dtb_one_entry);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_se_smmu0_ind_write", table_data_buff);
-
-        switch (wrt_mode)
-        {
-            case ERAM128_OPR_128b:
-            {
-                dtb_len += 2; 
-                addr_offset = item_cnt * DTB_LEN_POS_SETP * 2;
-                break;
-            }
-
-            case ERAM128_OPR_64b:
-            {
-                dtb_len += 1; 
-                addr_offset = item_cnt * DTB_LEN_POS_SETP;
-                break;
-            }
-
-            case ERAM128_OPR_1b:
-            {
-                dtb_len += 1;
-                addr_offset = item_cnt * DTB_LEN_POS_SETP;
-                break;
-            }
-        }
-
-        /*将表格式和数据写入缓存buff中*/
-        rc = dpp_dtb_data_write(table_data_buff, addr_offset, &dtb_one_entry);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", table_data_buff);
-        ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
-        ZXIC_COMM_MEMSET(entry_data_buff, 0, 4 * sizeof(ZXIC_UINT32));
-    }
-
-    if(dpp_dtb_prt_get())
-    {
-        dpp_data_buff_print(table_data_buff, dtb_len * 16);
-        ZXIC_COMM_PRINT("start down table to dtb : queue_id: %d, down_data_len: %d\n", queue_id, dtb_len * 16);
-    }
-     
-    rc = dpp_dtb_write_down_table_data(dev,  
-                                     queue_id, 
-                                     dtb_len * 16,
-                                     table_data_buff,
-                                      element_id
-                                      );
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_write_down_table_data", table_data_buff);
-     
-    ZXIC_COMM_FREE(table_data_buff);
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 wrt_mode;
+	ZXIC_UINT32 base_addr;
+	ZXIC_UINT32 index;
+	ZXIC_UINT32 item_cnt = 0;
+	ZXIC_UINT32 addr_offset = 0;
+	ZXIC_UINT32 *p_entry_data = NULL;
+	ZXIC_UINT32 dtb_len = 0;
+
+	ZXIC_UINT8 *table_data_buff = NULL;
+	ZXIC_UINT32 entry_data_buff[4] = { 0 };
+	ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = { 0 };
+
+	DPP_SDTTBL_ERAM_T sdt_eram_info = { 0 };
+	DPP_DTB_ENTRY_T dtb_one_entry = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_arr);
+
+	//分配下表数据缓存 16K
+	table_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(
+			DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), table_data_buff);
+	ZXIC_COMM_MEMSET(table_data_buff, 0,
+					 DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
+
+	dtb_one_entry.cmd = cmd_buff;
+	dtb_one_entry.data = (ZXIC_UINT8 *)entry_data_buff;
+
+	//从sdt_no中获取SDT配置
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_eram_info);
+	ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get",
+									   table_data_buff);
+	base_addr = sdt_eram_info.eram_base_addr;
+	wrt_mode = sdt_eram_info.eram_mode; // 3:128
+
+	switch (wrt_mode) {
+	case ERAM128_TBL_128b: {
+		wrt_mode = ERAM128_OPR_128b;
+		break;
+	}
+
+	case ERAM128_TBL_64b: {
+		wrt_mode = ERAM128_OPR_64b;
+		break;
+	}
+
+	case ERAM128_TBL_1b: {
+		wrt_mode = ERAM128_OPR_1b;
+		break;
+	}
+	}
+
+	for (item_cnt = 0; item_cnt < entry_num; ++item_cnt) {
+		p_entry_data = (ZXIC_UINT32 *)p_entry_arr[item_cnt].p_data;
+		ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE(DEV_ID(dev), p_entry_data,
+											  table_data_buff);
+		index = p_entry_arr[item_cnt].index;
+
+		if (dpp_dtb_prt_get()) {
+			ZXIC_COMM_PRINT(
+					"dpp_dtb_eram_dma_write_cycle : the item index is %d !\n",
+					index);
+		}
+
+		//将一个数据写入entry
+		rc = dpp_dtb_se_smmu0_ind_write(dev, base_addr, index, wrt_mode,
+										p_entry_data, &dtb_one_entry);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+				rc, "dpp_dtb_se_smmu0_ind_write", table_data_buff);
+
+		switch (wrt_mode) {
+		case ERAM128_OPR_128b: {
+			dtb_len += 2;
+			addr_offset = item_cnt * DTB_LEN_POS_SETP * 2;
+			break;
+		}
+
+		case ERAM128_OPR_64b: {
+			dtb_len += 1;
+			addr_offset = item_cnt * DTB_LEN_POS_SETP;
+			break;
+		}
+
+		case ERAM128_OPR_1b: {
+			dtb_len += 1;
+			addr_offset = item_cnt * DTB_LEN_POS_SETP;
+			break;
+		}
+		}
+
+		/*将表格式和数据写入缓存buff中*/
+		rc = dpp_dtb_data_write(table_data_buff, addr_offset, &dtb_one_entry);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",
+												 table_data_buff);
+		ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
+		ZXIC_COMM_MEMSET(entry_data_buff, 0, 4 * sizeof(ZXIC_UINT32));
+	}
+
+	if (dpp_dtb_prt_get()) {
+		dpp_data_buff_print(table_data_buff, dtb_len * 16);
+		ZXIC_COMM_PRINT(
+				"start down table to dtb : queue_id: %d, down_data_len: %d\n",
+				queue_id, dtb_len * 16);
+	}
+
+	rc = dpp_dtb_write_down_table_data(dev, queue_id, dtb_len * 16,
+									   table_data_buff, element_id);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+			rc, "dpp_dtb_write_down_table_data", table_data_buff);
+
+	ZXIC_COMM_FREE(table_data_buff);
+
+	rc = dpp_dtb_tab_down_success_status_check(dev, queue_id, *element_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_down_success_status_check");
+
+	return DPP_OK;
 }
 
-
 /** dtb写ddr中的数据，数据长度在16K范围内
-* @param   dev_id          设备号
-* @param   queue_id        队列号
-* @param   ddr_base_addr   ddr基地址，以4K*128bit为单位
-* @param   ddr_wr_mode     ddr写模式 0-128bit, 1-256bit, 2-384bit, 3-512bit,取值参考SMMU1_DDR_WRT_MODE_E的定义
-* @param   ddr_ecc_en      ddr ECC使能
-* @param   entry_num       下发的条目数
-* @param   p_entry_arr     待下发表项内容结构体数组指针
-* @param   element_id      返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_smmu1_data_write_cycle(DPP_DEV_T *dev, 
-                                          ZXIC_UINT32 queue_id, 
-                                          ZXIC_UINT32 ddr_base_addr, 
-                                          ZXIC_UINT32 ddr_wr_mode, 
-                                          ZXIC_UINT32 ddr_ecc_en,
-                                          ZXIC_UINT32 entry_num, 
-                                          DPP_DTB_DDR_ENTRY_INFO_T *p_entry_arr,
-                                          ZXIC_UINT32 *element_id)
+ * @param   dev_id          设备号
+ * @param   queue_id        队列号
+ * @param   ddr_base_addr   ddr基地址，以4K*128bit为单位
+ * @param   ddr_wr_mode     ddr写模式 0-128bit, 1-256bit, 2-384bit, 3-512bit,取值参考SMMU1_DDR_WRT_MODE_E的定义
+ * @param   ddr_ecc_en      ddr ECC使能
+ * @param   entry_num       下发的条目数
+ * @param   p_entry_arr     待下发表项内容结构体数组指针
+ * @param   element_id      返回下表使用的元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_smmu1_data_write_cycle(
+		DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 ddr_base_addr,
+		ZXIC_UINT32 ddr_wr_mode, ZXIC_UINT32 ddr_ecc_en, ZXIC_UINT32 entry_num,
+		DPP_DTB_DDR_ENTRY_INFO_T *p_entry_arr, ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS  rc = DPP_OK;
-    
-    ZXIC_UINT32 index;
-    ZXIC_UINT32 item_cnt = 0;
-    ZXIC_UINT32 addr_offset = 0;
-    ZXIC_UINT32 *p_entry_data = NULL;
-    ZXIC_UINT32 dtb_len = 0;
-    ZXIC_UINT8 *table_data_buff = NULL;
-    ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0};  /*命令格式缓存*/
-    ZXIC_UINT32 entry_data_buff[DPP_DIR_TBL_BUF_MAX_NUM] = {0};
-
-    DPP_DTB_ENTRY_T   dtb_one_entry = {0};  /*条目结构*/
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_arr);
-
-    //分配下表数据缓存 16K
-    table_data_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), table_data_buff);
-    ZXIC_COMM_MEMSET(table_data_buff, 0, DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
-
-    dtb_one_entry.cmd = cmd_buff;
-    dtb_one_entry.data = (ZXIC_UINT8 *)entry_data_buff;
-
-     /*对每一个条目进行处理*/
-    for(item_cnt = 0; item_cnt < entry_num; ++item_cnt)
-    {
-        p_entry_data = (ZXIC_UINT32 *)p_entry_arr[item_cnt].p_data;
-        ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(p_entry_data, table_data_buff);
-
-        index = p_entry_arr[item_cnt].index;
-
-        //将一个数据写入entry
-        rc = dpp_dtb_ddr_dir_table_data_write(DEV_ID(dev), 
-                                        ddr_base_addr,
-                                        ddr_wr_mode,
-                                        index,
-                                        ddr_ecc_en,
-                                        (ZXIC_UINT8 *)p_entry_data, 
-                                        &dtb_one_entry);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_ddr_dir_table_data_write", table_data_buff);
-
-        dtb_len += (ddr_wr_mode + 2);
-        addr_offset = item_cnt * (ddr_wr_mode + 2) * DTB_LEN_POS_SETP;
-
-        /*数据写入缓存中*/
-        rc = dpp_dtb_data_write(table_data_buff, addr_offset, &dtb_one_entry);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", table_data_buff);
-        ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
-        ZXIC_COMM_MEMSET(entry_data_buff, 0, DPP_DIR_TBL_BUF_MAX_NUM * sizeof(ZXIC_UINT32));
-    }
-
-    if(dpp_dtb_prt_get())
-    {
-        dpp_data_buff_print(table_data_buff, dtb_len * 16);
-        ZXIC_COMM_PRINT("start down table to dtb : queue_id: %d, down_data_len: %d\n", queue_id, dtb_len * 16);
-    }
-    
-    rc = dpp_dtb_write_down_table_data(dev,  
-                                      queue_id, 
-                                      dtb_len * 16,
-                                      table_data_buff,
-                                      element_id
-                                      );
-    ZXIC_COMM_FREE(table_data_buff);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_down_table_data");
-    
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 index;
+	ZXIC_UINT32 item_cnt = 0;
+	ZXIC_UINT32 addr_offset = 0;
+	ZXIC_UINT32 *p_entry_data = NULL;
+	ZXIC_UINT32 dtb_len = 0;
+	ZXIC_UINT8 *table_data_buff = NULL;
+	ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = { 0 }; /*命令格式缓存*/
+	ZXIC_UINT32 entry_data_buff[DPP_DIR_TBL_BUF_MAX_NUM] = { 0 };
+
+	DPP_DTB_ENTRY_T dtb_one_entry = { 0 }; /*条目结构*/
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_arr);
+
+	//分配下表数据缓存 16K
+	table_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(
+			DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), table_data_buff);
+	ZXIC_COMM_MEMSET(table_data_buff, 0,
+					 DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
+
+	dtb_one_entry.cmd = cmd_buff;
+	dtb_one_entry.data = (ZXIC_UINT8 *)entry_data_buff;
+
+	/*对每一个条目进行处理*/
+	for (item_cnt = 0; item_cnt < entry_num; ++item_cnt) {
+		p_entry_data = (ZXIC_UINT32 *)p_entry_arr[item_cnt].p_data;
+		ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(p_entry_data,
+													table_data_buff);
+
+		index = p_entry_arr[item_cnt].index;
+
+		//将一个数据写入entry
+		rc = dpp_dtb_ddr_dir_table_data_write(DEV_ID(dev), ddr_base_addr,
+											  ddr_wr_mode, index, ddr_ecc_en,
+											  (ZXIC_UINT8 *)p_entry_data,
+											  &dtb_one_entry);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+				rc, "dpp_dtb_ddr_dir_table_data_write", table_data_buff);
+
+		dtb_len += (ddr_wr_mode + 2);
+		addr_offset = item_cnt * (ddr_wr_mode + 2) * DTB_LEN_POS_SETP;
+
+		/*数据写入缓存中*/
+		rc = dpp_dtb_data_write(table_data_buff, addr_offset, &dtb_one_entry);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",
+												 table_data_buff);
+		ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
+		ZXIC_COMM_MEMSET(entry_data_buff, 0,
+						 DPP_DIR_TBL_BUF_MAX_NUM * sizeof(ZXIC_UINT32));
+	}
+
+	if (dpp_dtb_prt_get()) {
+		dpp_data_buff_print(table_data_buff, dtb_len * 16);
+		ZXIC_COMM_PRINT(
+				"start down table to dtb : queue_id: %d, down_data_len: %d\n",
+				queue_id, dtb_len * 16);
+	}
+
+	rc = dpp_dtb_write_down_table_data(dev, queue_id, dtb_len * 16,
+									   table_data_buff, element_id);
+	ZXIC_COMM_FREE(table_data_buff);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_down_table_data");
+
+	rc = dpp_dtb_tab_down_success_status_check(dev, queue_id, *element_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_down_success_status_check");
+
+	return DPP_OK;
 }
 
 /** dtb写HASH表,在插入条目时如果冲突，则对冲突条目进行记录
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   sdt_no    hash表sdt表号
-* @param   entry_cnt 下发的条目数
-* @param   p_entry_arr   待下发表项内容结构体数组指针
-* @param   element_id   返回下表使用的元素id
-* @return
-* @remark  无 是否是有一个写不成功就返回，还是继续进行下一个条目并记录错误的条目
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_hash_dma_insert_cycle(DPP_DEV_T *dev, 
-                                   ZXIC_UINT32 queue_id, 
-                                   ZXIC_UINT32 sdt_no, 
-                                   ZXIC_UINT32 entry_num, 
-                                   DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry,
-                                   ZXIC_UINT32 *element_id)
+ * @param   dev_id    设备号
+ * @param   queue_id  队列号
+ * @param   sdt_no    hash表sdt表号
+ * @param   entry_cnt 下发的条目数
+ * @param   p_entry_arr   待下发表项内容结构体数组指针
+ * @param   element_id   返回下表使用的元素id
+ * @return
+ * @remark  无 是否是有一个写不成功就返回，还是继续进行下一个条目并记录错误的条目
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS
+dpp_dtb_hash_dma_insert_cycle(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+							  ZXIC_UINT32 sdt_no, ZXIC_UINT32 entry_num,
+							  DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry,
+							  ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT8 temp_key[HASH_KEY_MAX] = {0};
-    ZXIC_UINT8 end_flag = 0;
-    ZXIC_UINT32 ddr_wr_mode = 0;
-    ZXIC_UINT32 item_cnt = 0;
-    ZXIC_UINT8  key_valid = 1;
-    ZXIC_UINT32 dtb_len = 0;
-    ZXIC_UINT8 key[HASH_KEY_MAX] = {0};
-    ZXIC_UINT8 rst[HASH_RST_MAX] = {0};
-
-    DPP_SE_CFG *p_se_cfg = NULL;
-    ZXIC_RB_TN *p_rb_tn_new = NULL;
-    ZXIC_RB_TN *p_rb_tn_rtn = NULL;
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    DPP_HASH_RBKEY_INFO *p_rbkey_new = NULL;
-    FUNC_ID_INFO *p_func_info = NULL;
-    HASH_ENTRY_CFG  hash_entry_cfg = {0}; 
-    DPP_SDTTBL_HASH_T sdt_hash_info = {0};  /*SDT内容*/
-    DPP_HASH_ENTRY entry = {0}; /* hash条目结构体*/
-    ZXIC_UINT8 *p_data_buff = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_arr_hash_entry);
-
-    //从sdt_no中获取SDT配置
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_read");
-
-    hash_entry_cfg.fun_id   = sdt_hash_info.hash_id; /*hash引擎*/
-    ZXIC_COMM_CHECK_INDEX(hash_entry_cfg.fun_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1);
-    hash_entry_cfg.table_id = sdt_hash_info.hash_table_id; /*hash表号*/
-    ZXIC_COMM_CHECK_INDEX_UPPER(hash_entry_cfg.table_id,HASH_TBL_ID_NUM - 1);
-    hash_entry_cfg.bulk_id = ((hash_entry_cfg.table_id >> 2) & 0x7);
-    ZXIC_COMM_CHECK_INDEX_UPPER(hash_entry_cfg.bulk_id,HASH_BULK_NUM - 1);
-    hash_entry_cfg.key_type = sdt_hash_info.hash_table_width; /*表宽度*/
-    ZXIC_COMM_CHECK_INDEX(hash_entry_cfg.key_type, HASH_KEY_128b, HASH_KEY_512b);
-    hash_entry_cfg.actu_key_size = sdt_hash_info.key_size; /*业务表键值长度*/
-    ZXIC_COMM_CHECK_INDEX(hash_entry_cfg.actu_key_size, HASH_ACTU_KEY_MIN, HASH_ACTU_KEY_MAX);
-    hash_entry_cfg.key_by_size = DPP_GET_KEY_SIZE(hash_entry_cfg.actu_key_size);
-    hash_entry_cfg.rst_by_size = DPP_GET_RST_SIZE(hash_entry_cfg.key_type, hash_entry_cfg.actu_key_size);
-
-     /* 取出se配置 */
-    rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_cfg_get");
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg);
-    p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_entry_cfg.fun_id);
-    DPP_SE_CHECK_FUN(p_func_info, hash_entry_cfg.fun_id, FUN_HASH);
-    hash_entry_cfg.p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
-
-     /*条目数上限检查*/
-    ddr_wr_mode = DPP_GET_DDR_WR_MODE(hash_entry_cfg.key_type);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), entry_num, 1, DTB_DATA_SIZE_BIT / ( (ddr_wr_mode + 2) * DTB_TABLE_CMD_SIZE_BIT));
-
-    entry.p_key = key;
-    entry.p_rst = rst;
-    entry.p_key[0] = (ZXIC_UINT8)(((key_valid & 0x1) << 7) | ((hash_entry_cfg.key_type & 0x3) << 5) | (hash_entry_cfg.table_id & 0x1f));
-    
-    p_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data_buff);
-    ZXIC_COMM_MEMSET(p_data_buff,0x0,DPP_DTB_TABLE_DATA_BUFF_SIZE);
-
-    /*对每一个条目进行处理*/
-    for(item_cnt = 0; item_cnt < entry_num; ++item_cnt)
-    {
-        end_flag = 0;
-         /*组装数据*/
-        ZXIC_COMM_MEMCPY(&entry.p_key[1], p_arr_hash_entry[item_cnt].p_actu_key, hash_entry_cfg.actu_key_size);
-        ZXIC_COMM_MEMCPY(&entry.p_rst[0], p_arr_hash_entry[item_cnt].p_rst, ((hash_entry_cfg.rst_by_size > HASH_RST_MAX) ? HASH_RST_MAX : hash_entry_cfg.rst_by_size));
-     
-        rc = dpp_hash_red_black_node_alloc(dev,&p_rb_tn_new,&p_rbkey_new);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc,"dpp_hash_red_black_node_alloc",p_data_buff);
-        ZXIC_COMM_MEMCPY(p_rbkey_new->key, entry.p_key, hash_entry_cfg.key_by_size);
-        hash_entry_cfg.p_rbkey_new = p_rbkey_new; 
-        hash_entry_cfg.p_rb_tn_new = p_rb_tn_new;
-        
-        rc = dpp_hash_rb_insert(dev,&hash_entry_cfg,&entry);
-        if(DPP_OK != rc)
-        {
-            if(DPP_HASH_RC_ADD_UPDATE == rc)
-            {
-                /*将位置信息和数据信息写入buff中*/
-                rc = dpp_dtb_add_hash_buf_write(DEV_ID(dev),&hash_entry_cfg,p_data_buff,item_cnt,&dtb_len);
-                ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_hash_form_write",p_data_buff);
-            }
-            continue;
-        }
-    
-        /*insert new hash item*/
-        /*1 first form the new key(calc crc)*/
-        rc = dpp_hash_set_crc_key(dev,&hash_entry_cfg,&entry,temp_key);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc,"hash_set_crc_key",p_data_buff);
-
-        /*2 if DDR is valid, first insert into DDR.*/
-        p_hash_cfg = hash_entry_cfg.p_hash_cfg;
-        if (p_hash_cfg->ddr_valid)
-        {
-            rc = dpp_hash_insert_ddr(dev,&hash_entry_cfg,temp_key,&end_flag);
-            ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc,"hash_insert_ddr",p_data_buff);
-        }
-
-        /*3 if insert into DDR is fail, insert into ZCAM. */
-        if (!end_flag)
-        {
-            rc = dpp_hash_insert_zcell(dev,p_se_cfg,&hash_entry_cfg,temp_key,&end_flag);
-            ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc,"hash_insert_zcell",p_data_buff);
-        }
-
-        /*4 if insert into ZCAM is fail, insert into ZBLK Reg. */
-        if (!end_flag)
-        {
-            rc = dpp_hash_insert_zreg(dev,&hash_entry_cfg,temp_key,&end_flag);
-            ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc,"hash_insert_zreg",p_data_buff);
-        }
-
-        if (!end_flag)
-        {
-            p_hash_cfg->hash_stat.insert_fail++;
-            /* recycle rb tree node */
-            ZXIC_COMM_MEMCPY(temp_key, entry.p_key, hash_entry_cfg.key_by_size);
-            rc = zxic_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey_new, &p_rb_tn_rtn);
-            ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "zxic_comm_rb_delete",p_data_buff);
-            ZXIC_COMM_ASSERT(p_rb_tn_new == p_rb_tn_rtn);
-            ZXIC_COMM_FREE(p_rbkey_new);
-            ZXIC_COMM_FREE(p_rb_tn_rtn); 
-            ZXIC_COMM_FREE(p_data_buff); 
-            dpp_dtb_data_print(temp_key, hash_entry_cfg.key_by_size);
-            ZXIC_COMM_TRACE_ERROR("DPP_HASH_RC_TBL_FULL.\n");
-            return DPP_RC_DTB_DOWN_HASH_CONFLICT;
-        }
-
-        /*将位置信息和数据信息写入buff中*/
-        rc = dpp_dtb_add_hash_buf_write(DEV_ID(dev),&hash_entry_cfg,p_data_buff,item_cnt,&dtb_len);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_hash_form_write",p_data_buff);
-        
-        p_hash_cfg->hash_stat.insert_ok++;
-    }
-
-    if(dpp_dtb_prt_get())
-    {
-        dpp_data_buff_print(p_data_buff, dtb_len * 16);
-    }
-    
-    rc = dpp_dtb_write_down_table_data(dev,  
-                                     queue_id, 
-                                     dtb_len * 16,
-                                     p_data_buff,
-                                     element_id);
-    ZXIC_COMM_FREE(p_data_buff);                                   
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_down_table_data");
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT8 temp_key[HASH_KEY_MAX] = { 0 };
+	ZXIC_UINT8 end_flag = 0;
+	ZXIC_UINT32 ddr_wr_mode = 0;
+	ZXIC_UINT32 item_cnt = 0;
+	ZXIC_UINT8 key_valid = 1;
+	ZXIC_UINT32 dtb_len = 0;
+	ZXIC_UINT8 key[HASH_KEY_MAX] = { 0 };
+	ZXIC_UINT8 rst[HASH_RST_MAX] = { 0 };
+
+	DPP_SE_CFG *p_se_cfg = NULL;
+	ZXIC_RB_TN *p_rb_tn_new = NULL;
+	ZXIC_RB_TN *p_rb_tn_rtn = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	DPP_HASH_RBKEY_INFO *p_rbkey_new = NULL;
+	FUNC_ID_INFO *p_func_info = NULL;
+	HASH_ENTRY_CFG hash_entry_cfg = { 0 };
+	DPP_SDTTBL_HASH_T sdt_hash_info = { 0 }; /*SDT内容*/
+	DPP_HASH_ENTRY entry = { 0 }; /* hash条目结构体*/
+	ZXIC_UINT8 *p_data_buff = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_arr_hash_entry);
+
+	//从sdt_no中获取SDT配置
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_read");
+
+	hash_entry_cfg.fun_id = sdt_hash_info.hash_id; /*hash引擎*/
+	ZXIC_COMM_CHECK_INDEX(hash_entry_cfg.fun_id, HASH_FUNC_ID_MIN,
+						  HASH_FUNC_ID_NUM - 1);
+	hash_entry_cfg.table_id = sdt_hash_info.hash_table_id; /*hash表号*/
+	ZXIC_COMM_CHECK_INDEX_UPPER(hash_entry_cfg.table_id, HASH_TBL_ID_NUM - 1);
+	hash_entry_cfg.bulk_id = ((hash_entry_cfg.table_id >> 2) & 0x7);
+	ZXIC_COMM_CHECK_INDEX_UPPER(hash_entry_cfg.bulk_id, HASH_BULK_NUM - 1);
+	hash_entry_cfg.key_type = sdt_hash_info.hash_table_width; /*表宽度*/
+	ZXIC_COMM_CHECK_INDEX(hash_entry_cfg.key_type, HASH_KEY_128b,
+						  HASH_KEY_512b);
+	hash_entry_cfg.actu_key_size = sdt_hash_info.key_size; /*业务表键值长度*/
+	ZXIC_COMM_CHECK_INDEX(hash_entry_cfg.actu_key_size, HASH_ACTU_KEY_MIN,
+						  HASH_ACTU_KEY_MAX);
+	hash_entry_cfg.key_by_size = DPP_GET_KEY_SIZE(hash_entry_cfg.actu_key_size);
+	hash_entry_cfg.rst_by_size = DPP_GET_RST_SIZE(hash_entry_cfg.key_type,
+												  hash_entry_cfg.actu_key_size);
+
+	/* 取出se配置 */
+	rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_cfg_get");
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg);
+	p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_entry_cfg.fun_id);
+	DPP_SE_CHECK_FUN(p_func_info, hash_entry_cfg.fun_id, FUN_HASH);
+	hash_entry_cfg.p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
+
+	/*条目数上限检查*/
+	ddr_wr_mode = DPP_GET_DDR_WR_MODE(hash_entry_cfg.key_type);
+	ZXIC_COMM_CHECK_DEV_INDEX(
+			DEV_ID(dev), entry_num, 1,
+			DTB_DATA_SIZE_BIT / ((ddr_wr_mode + 2) * DTB_TABLE_CMD_SIZE_BIT));
+
+	entry.p_key = key;
+	entry.p_rst = rst;
+	entry.p_key[0] = (ZXIC_UINT8)(((key_valid & 0x1) << 7) |
+								  ((hash_entry_cfg.key_type & 0x3) << 5) |
+								  (hash_entry_cfg.table_id & 0x1f));
+
+	p_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data_buff);
+	ZXIC_COMM_MEMSET(p_data_buff, 0x0, DPP_DTB_TABLE_DATA_BUFF_SIZE);
+
+	/*对每一个条目进行处理*/
+	for (item_cnt = 0; item_cnt < entry_num; ++item_cnt) {
+		end_flag = 0;
+		/*组装数据*/
+		ZXIC_COMM_MEMCPY(&entry.p_key[1], p_arr_hash_entry[item_cnt].p_actu_key,
+						 hash_entry_cfg.actu_key_size);
+		ZXIC_COMM_MEMCPY(&entry.p_rst[0], p_arr_hash_entry[item_cnt].p_rst,
+						 ((hash_entry_cfg.rst_by_size > HASH_RST_MAX) ?
+									HASH_RST_MAX :
+									hash_entry_cfg.rst_by_size));
+
+		rc = dpp_hash_red_black_node_alloc(dev, &p_rb_tn_new, &p_rbkey_new);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+				rc, "dpp_hash_red_black_node_alloc", p_data_buff);
+		ZXIC_COMM_MEMCPY(p_rbkey_new->key, entry.p_key,
+						 hash_entry_cfg.key_by_size);
+		hash_entry_cfg.p_rbkey_new = p_rbkey_new;
+		hash_entry_cfg.p_rb_tn_new = p_rb_tn_new;
+
+		rc = dpp_hash_rb_insert(dev, &hash_entry_cfg, &entry);
+		if (DPP_OK != rc) {
+			if (DPP_HASH_RC_ADD_UPDATE == rc) {
+				/*将位置信息和数据信息写入buff中*/
+				rc = dpp_dtb_add_hash_buf_write(DEV_ID(dev), &hash_entry_cfg,
+												p_data_buff, item_cnt,
+												&dtb_len);
+				ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+						rc, "dpp_dtb_hash_form_write", p_data_buff);
+			}
+			continue;
+		}
+
+		/*insert new hash item*/
+		/*1 first form the new key(calc crc)*/
+		rc = dpp_hash_set_crc_key(dev, &hash_entry_cfg, &entry, temp_key);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "hash_set_crc_key",
+												 p_data_buff);
+
+		/*2 if DDR is valid, first insert into DDR.*/
+		p_hash_cfg = hash_entry_cfg.p_hash_cfg;
+		if (p_hash_cfg->ddr_valid) {
+			rc = dpp_hash_insert_ddr(dev, &hash_entry_cfg, temp_key, &end_flag);
+			ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "hash_insert_ddr",
+													 p_data_buff);
+		}
+
+		/*3 if insert into DDR is fail, insert into ZCAM. */
+		if (!end_flag) {
+			rc = dpp_hash_insert_zcell(dev, p_se_cfg, &hash_entry_cfg, temp_key,
+									   &end_flag);
+			ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "hash_insert_zcell",
+													 p_data_buff);
+		}
+
+		/*4 if insert into ZCAM is fail, insert into ZBLK Reg. */
+		if (!end_flag) {
+			rc = dpp_hash_insert_zreg(dev, &hash_entry_cfg, temp_key,
+									  &end_flag);
+			ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "hash_insert_zreg",
+													 p_data_buff);
+		}
+
+		if (!end_flag) {
+			p_hash_cfg->hash_stat.insert_fail++;
+			/* recycle rb tree node */
+			ZXIC_COMM_MEMCPY(temp_key, entry.p_key, hash_entry_cfg.key_by_size);
+			rc = zxic_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey_new,
+									 &p_rb_tn_rtn);
+			ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "zxic_comm_rb_delete",
+													 p_data_buff);
+			ZXIC_COMM_ASSERT(p_rb_tn_new == p_rb_tn_rtn);
+			ZXIC_COMM_FREE(p_rbkey_new);
+			ZXIC_COMM_FREE(p_rb_tn_rtn);
+			ZXIC_COMM_FREE(p_data_buff);
+			dpp_dtb_data_print(temp_key, hash_entry_cfg.key_by_size);
+			ZXIC_COMM_TRACE_ERROR("DPP_HASH_RC_TBL_FULL.\n");
+			return DPP_RC_DTB_DOWN_HASH_CONFLICT;
+		}
+
+		/*将位置信息和数据信息写入buff中*/
+		rc = dpp_dtb_add_hash_buf_write(DEV_ID(dev), &hash_entry_cfg,
+										p_data_buff, item_cnt, &dtb_len);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_hash_form_write",
+												 p_data_buff);
+
+		p_hash_cfg->hash_stat.insert_ok++;
+	}
+
+	if (dpp_dtb_prt_get()) {
+		dpp_data_buff_print(p_data_buff, dtb_len * 16);
+	}
+
+	rc = dpp_dtb_write_down_table_data(dev, queue_id, dtb_len * 16, p_data_buff,
+									   element_id);
+	ZXIC_COMM_FREE(p_data_buff);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_down_table_data");
+
+	rc = dpp_dtb_tab_down_success_status_check(dev, queue_id, *element_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_down_success_status_check");
+
+	return DPP_OK;
 }
 
-
 /** dtb写ACL表 （SPECIFY模式，条目中指定handle，支持级联64bit/128bit）
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   sdt_no    ACL表sdt表号
-* @param   entry_cnt 下发的条目数
-* @param   p_entry_arr   待下发表项内容结构体数组指针
-* @param   element_id    返回下表使用的元素id
-* @return
-* @remark  无 是否是有一个写不成功就返回，还是继续进行下一个条目并记录错误的条目
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_acl_dma_insert_cycle(DPP_DEV_T *dev, 
-                                      ZXIC_UINT32 queue_id, 
-                                      ZXIC_UINT32 sdt_no, 
-                                      ZXIC_UINT32 entry_num, 
-                                      DPP_DTB_ACL_ENTRY_INFO_T *p_acl_entry_arr,
-                                      ZXIC_UINT32 *element_id
-                                      )
+ * @param   dev_id    设备号
+ * @param   queue_id  队列号
+ * @param   sdt_no    ACL表sdt表号
+ * @param   entry_cnt 下发的条目数
+ * @param   p_entry_arr   待下发表项内容结构体数组指针
+ * @param   element_id    返回下表使用的元素id
+ * @return
+ * @remark  无 是否是有一个写不成功就返回，还是继续进行下一个条目并记录错误的条目
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS
+dpp_dtb_acl_dma_insert_cycle(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+							 ZXIC_UINT32 sdt_no, ZXIC_UINT32 entry_num,
+							 DPP_DTB_ACL_ENTRY_INFO_T *p_acl_entry_arr,
+							 ZXIC_UINT32 *element_id)
 {
-    /*
+	/*
     1、条目的handle值是指定的；
     2、根据级联配置在etcam中保存级联结果值
     */
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 etcam_key_mode;
-    ZXIC_UINT32 as_eram_baddr;
-    ZXIC_UINT32 as_enable;
-    ZXIC_UINT32 etcam_table_id;
-    ZXIC_UINT32 etcam_as_mode;
-    ZXIC_UINT32 block_idx = 0;
-    ZXIC_UINT32 ram_addr = 0;
-    ZXIC_UINT32 etcam_wr_mode = 0;
-    ZXIC_UINT32 eram_wrt_mode = 0;
-    ZXIC_UINT32 eram_index;
-
-    ZXIC_UINT32 item_cnt = 0;
-    ZXIC_UINT32 addr_offset_bk = 0;
-    ZXIC_UINT32 dtb_len = 0;
-    ZXIC_UINT32 as_addr_offset = 0;
-    ZXIC_UINT32 as_dtb_len = 0;
-
-    DPP_ACL_CFG_EX_T *p_acl_cfg = NULL;
-    DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL;
-    DPP_DTB_ACL_ENTRY_INFO_T *p_acl_entry = NULL;
-    ZXIC_UINT32 *p_as_eram_data = NULL;
-    ZXIC_UINT8 *table_data_buff = NULL;
-    DPP_ETCAM_ENTRY_T etcam_entry = {0};
-
-    ZXIC_UINT8 entry_data_buff[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    ZXIC_UINT8 entry_mask_buff[DPP_ETCAM_WIDTH_MAX / 8] = {0}; 
-    ZXIC_UINT32 as_eram_data_buff[4] = {0};   
-    ZXIC_UINT8 entry_data_cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0};
-    ZXIC_UINT8 entry_mask_cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0};
-    ZXIC_UINT8 as_eram_cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0};
-
-    DPP_SDTTBL_ETCAM_T sdt_etcam_info = {0}; 
-    DPP_DTB_ENTRY_T entry_data = {0};
-    DPP_DTB_ENTRY_T entry_mask = {0};
-    DPP_DTB_ENTRY_T dtb_as_data_entry = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_acl_entry_arr);
-
-    entry_data.cmd = entry_data_cmd_buff;
-    entry_data.data = (ZXIC_UINT8 *)entry_data_buff;
-
-    entry_mask.cmd = entry_mask_cmd_buff;
-    entry_mask.data = (ZXIC_UINT8 *)entry_mask_buff;
-
-    dtb_as_data_entry.cmd = as_eram_cmd_buff;
-    dtb_as_data_entry.data = (ZXIC_UINT8 *)as_eram_data_buff;
-
-    //分配下表数据缓存 16K
-    table_data_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), table_data_buff);
-    ZXIC_COMM_MEMSET(table_data_buff, 0, DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
-
-    //从sdt_no中获取SDT配置
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info);
-    ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get", table_data_buff);
-    etcam_key_mode = sdt_etcam_info.etcam_key_mode;
-    ZXIC_COMM_CHECK_INDEX_MEMORY_FREE_NO_ASSERT(etcam_key_mode, DPP_ACL_KEY_640b, DPP_ACL_KEY_80b, table_data_buff);
-    etcam_as_mode = sdt_etcam_info.as_rsp_mode;
-    ZXIC_COMM_CHECK_INDEX_MEMORY_FREE_NO_ASSERT(etcam_as_mode, DPP_ACL_AS_MODE_64b, DPP_ACL_AS_MODE_INVALID - 1, table_data_buff);
-    etcam_table_id = sdt_etcam_info.etcam_table_id;
-    ZXIC_COMM_CHECK_INDEX_MEMORY_FREE_NO_ASSERT(etcam_table_id, DPP_ACL_TBL_ID_MIN, DPP_ACL_TBL_ID_MAX, table_data_buff);
-    as_enable = sdt_etcam_info.as_en;
-    as_eram_baddr = sdt_etcam_info.as_eram_baddr;
-
-    //级联数据下发
-    if(as_enable)
-    {
-        //mode转换
-        switch (etcam_as_mode)
-        {
-            case ERAM128_TBL_128b:
-            {
-                eram_wrt_mode = ERAM128_OPR_128b;
-                break;
-            }
-
-            case ERAM128_TBL_64b:
-            {
-                eram_wrt_mode = ERAM128_OPR_64b;
-                break;
-            }
-
-            case ERAM128_TBL_1b:
-            {
-                eram_wrt_mode = ERAM128_OPR_1b;
-                break;
-            }
-        }
-    }    
-
-    dpp_acl_cfg_get(&p_acl_cfg);//获取ACL表资源配置
-    ZXIC_COMM_CHECK_POINT_MEMORY_FREE(p_acl_cfg, table_data_buff);
-
-    p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id;//得到该acl表的资源配置
-
-    if (!p_tbl_cfg->is_used)
-    {
-        ZXIC_COMM_TRACE_ERROR("table[ %d ] is not init!\n", etcam_table_id);
-        ZXIC_COMM_FREE(table_data_buff);
-        ZXIC_COMM_ASSERT(0);
-        return DPP_ACL_RC_TBL_NOT_INIT;
-    }
-
-    /*对每一个条目进行处理*/
-    for(item_cnt = 0; item_cnt < entry_num; ++item_cnt)
-    {
-         p_acl_entry = p_acl_entry_arr + item_cnt;
-         
-        /* write etcam key */
-        etcam_entry.mode = p_tbl_cfg->key_mode;
-        etcam_entry.p_data = p_acl_entry->key_data;
-        etcam_entry.p_mask = p_acl_entry->key_mask;
-
-        /*计算地址等信息*/
-        rc = dpp_acl_hdw_addr_get(p_tbl_cfg, p_acl_entry->handle, &block_idx, &ram_addr, &etcam_wr_mode);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE(rc, "dpp_acl_hdw_addr_get", table_data_buff);
-
-        rc = dpp_dtb_etcam_entry_add(dev,
-                               ram_addr,
-                               block_idx,
-                               etcam_wr_mode,
-                               DPP_ETCAM_OPR_DM,
-                               &etcam_entry,
-                               &entry_data,
-                               &entry_mask
-                               );
-
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_etcam_entry_add", table_data_buff);
-
-        /*data数据写入缓存*/
-        dtb_len += DTB_ETCAM_LEN_SIZE;
-        dpp_dtb_data_write(table_data_buff, addr_offset_bk, &entry_data);  /*将数据写入缓存中*/
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", table_data_buff);
-        ZXIC_COMM_MEMSET(entry_data_cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
-        ZXIC_COMM_MEMSET(entry_data_buff, 0, DPP_ETCAM_WIDTH_MAX / 8);
-        addr_offset_bk = addr_offset_bk + DTB_ETCAM_LEN_SIZE * DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/
-
-        /*mask数据写入缓存*/
-        dtb_len += DTB_ETCAM_LEN_SIZE;
-        rc = dpp_dtb_data_write(table_data_buff, addr_offset_bk, &entry_mask);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", table_data_buff);
-        ZXIC_COMM_MEMSET(entry_mask_cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
-        ZXIC_COMM_MEMSET(entry_mask_buff, 0, 640/8);
-        addr_offset_bk = addr_offset_bk + DTB_ETCAM_LEN_SIZE * DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/ 
-        
-        //处理级联数据
-        if(as_enable)
-        {
-            p_as_eram_data = (ZXIC_UINT32 *)(p_acl_entry->p_as_rslt);
-            ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE_NO_ASSERT(DEV_ID(dev), p_as_eram_data, table_data_buff);
-            eram_index = p_acl_entry->handle;
-            rc = dpp_dtb_se_smmu0_ind_write(dev,
-                            as_eram_baddr, 
-                            eram_index, 
-                            eram_wrt_mode,
-                            p_as_eram_data,
-                            &dtb_as_data_entry);
-            ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_se_smmu0_ind_write", table_data_buff);
-
-            switch (eram_wrt_mode)
-            {
-                case ERAM128_OPR_128b:
-                {
-                    as_dtb_len = 2;
-                    as_addr_offset = DTB_LEN_POS_SETP * 2;
-                    break;
-                }
-
-                case ERAM128_OPR_64b:
-                {
-                    as_dtb_len = 1;
-                    as_addr_offset = DTB_LEN_POS_SETP;
-                    break;
-                }
-
-                case ERAM128_OPR_1b:
-                {
-                    as_dtb_len = 1;
-                    as_addr_offset = DTB_LEN_POS_SETP;
-                    break;
-                }
-            }
-
-            /*将表格式和数据写入缓存buff中*/
-            rc = dpp_dtb_data_write(table_data_buff, addr_offset_bk, &dtb_as_data_entry);
-            addr_offset_bk = addr_offset_bk + as_addr_offset; /*在缓存中相对于0的offset*/
-            dtb_len += as_dtb_len;
-            ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", table_data_buff);
-            ZXIC_COMM_MEMSET(as_eram_cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
-            ZXIC_COMM_MEMSET(as_eram_data_buff, 0, 4 * sizeof(ZXIC_UINT32));
-        }
-    }
-
-    if(dpp_dtb_prt_get())
-    {
-        dpp_data_buff_print(table_data_buff, dtb_len * 16);
-    }
-
-    rc = dpp_dtb_write_down_table_data(dev,  
-                                    queue_id, 
-                                    dtb_len * 16,
-                                    table_data_buff,
-                                    element_id
-                                    );
-    ZXIC_COMM_FREE(table_data_buff);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_down_table_data");
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 etcam_key_mode;
+	ZXIC_UINT32 as_eram_baddr;
+	ZXIC_UINT32 as_enable;
+	ZXIC_UINT32 etcam_table_id;
+	ZXIC_UINT32 etcam_as_mode;
+	ZXIC_UINT32 block_idx = 0;
+	ZXIC_UINT32 ram_addr = 0;
+	ZXIC_UINT32 etcam_wr_mode = 0;
+	ZXIC_UINT32 eram_wrt_mode = 0;
+	ZXIC_UINT32 eram_index;
+
+	ZXIC_UINT32 item_cnt = 0;
+	ZXIC_UINT32 addr_offset_bk = 0;
+	ZXIC_UINT32 dtb_len = 0;
+	ZXIC_UINT32 as_addr_offset = 0;
+	ZXIC_UINT32 as_dtb_len = 0;
+
+	DPP_ACL_CFG_EX_T *p_acl_cfg = NULL;
+	DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL;
+	DPP_DTB_ACL_ENTRY_INFO_T *p_acl_entry = NULL;
+	ZXIC_UINT32 *p_as_eram_data = NULL;
+	ZXIC_UINT8 *table_data_buff = NULL;
+	DPP_ETCAM_ENTRY_T etcam_entry = { 0 };
+
+	ZXIC_UINT8 entry_data_buff[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	ZXIC_UINT8 entry_mask_buff[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	ZXIC_UINT32 as_eram_data_buff[4] = { 0 };
+	ZXIC_UINT8 entry_data_cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = { 0 };
+	ZXIC_UINT8 entry_mask_cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = { 0 };
+	ZXIC_UINT8 as_eram_cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = { 0 };
+
+	DPP_SDTTBL_ETCAM_T sdt_etcam_info = { 0 };
+	DPP_DTB_ENTRY_T entry_data = { 0 };
+	DPP_DTB_ENTRY_T entry_mask = { 0 };
+	DPP_DTB_ENTRY_T dtb_as_data_entry = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_acl_entry_arr);
+
+	entry_data.cmd = entry_data_cmd_buff;
+	entry_data.data = (ZXIC_UINT8 *)entry_data_buff;
+
+	entry_mask.cmd = entry_mask_cmd_buff;
+	entry_mask.data = (ZXIC_UINT8 *)entry_mask_buff;
+
+	dtb_as_data_entry.cmd = as_eram_cmd_buff;
+	dtb_as_data_entry.data = (ZXIC_UINT8 *)as_eram_data_buff;
+
+	//分配下表数据缓存 16K
+	table_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(
+			DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), table_data_buff);
+	ZXIC_COMM_MEMSET(table_data_buff, 0,
+					 DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
+
+	//从sdt_no中获取SDT配置
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info);
+	ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get",
+									   table_data_buff);
+	etcam_key_mode = sdt_etcam_info.etcam_key_mode;
+	ZXIC_COMM_CHECK_INDEX_MEMORY_FREE_NO_ASSERT(
+			etcam_key_mode, DPP_ACL_KEY_640b, DPP_ACL_KEY_80b, table_data_buff);
+	etcam_as_mode = sdt_etcam_info.as_rsp_mode;
+	ZXIC_COMM_CHECK_INDEX_MEMORY_FREE_NO_ASSERT(etcam_as_mode,
+												DPP_ACL_AS_MODE_64b,
+												DPP_ACL_AS_MODE_INVALID - 1,
+												table_data_buff);
+	etcam_table_id = sdt_etcam_info.etcam_table_id;
+	ZXIC_COMM_CHECK_INDEX_MEMORY_FREE_NO_ASSERT(etcam_table_id,
+												DPP_ACL_TBL_ID_MIN,
+												DPP_ACL_TBL_ID_MAX,
+												table_data_buff);
+	as_enable = sdt_etcam_info.as_en;
+	as_eram_baddr = sdt_etcam_info.as_eram_baddr;
+
+	//级联数据下发
+	if (as_enable) {
+		// mode转换
+		switch (etcam_as_mode) {
+		case ERAM128_TBL_128b: {
+			eram_wrt_mode = ERAM128_OPR_128b;
+			break;
+		}
+
+		case ERAM128_TBL_64b: {
+			eram_wrt_mode = ERAM128_OPR_64b;
+			break;
+		}
+
+		case ERAM128_TBL_1b: {
+			eram_wrt_mode = ERAM128_OPR_1b;
+			break;
+		}
+		}
+	}
+
+	dpp_acl_cfg_get(&p_acl_cfg); //获取ACL表资源配置
+	ZXIC_COMM_CHECK_POINT_MEMORY_FREE(p_acl_cfg, table_data_buff);
+
+	p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; //得到该acl表的资源配置
+
+	if (!p_tbl_cfg->is_used) {
+		ZXIC_COMM_TRACE_ERROR("table[ %d ] is not init!\n", etcam_table_id);
+		ZXIC_COMM_FREE(table_data_buff);
+		ZXIC_COMM_ASSERT(0);
+		return DPP_ACL_RC_TBL_NOT_INIT;
+	}
+
+	/*对每一个条目进行处理*/
+	for (item_cnt = 0; item_cnt < entry_num; ++item_cnt) {
+		p_acl_entry = p_acl_entry_arr + item_cnt;
+
+		/* write etcam key */
+		etcam_entry.mode = p_tbl_cfg->key_mode;
+		etcam_entry.p_data = p_acl_entry->key_data;
+		etcam_entry.p_mask = p_acl_entry->key_mask;
+
+		/*计算地址等信息*/
+		rc = dpp_acl_hdw_addr_get(p_tbl_cfg, p_acl_entry->handle, &block_idx,
+								  &ram_addr, &etcam_wr_mode);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE(rc, "dpp_acl_hdw_addr_get",
+									   table_data_buff);
+
+		rc = dpp_dtb_etcam_entry_add(dev, ram_addr, block_idx, etcam_wr_mode,
+									 DPP_ETCAM_OPR_DM, &etcam_entry,
+									 &entry_data, &entry_mask);
+
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_etcam_entry_add",
+												 table_data_buff);
+
+		/*data数据写入缓存*/
+		dtb_len += DTB_ETCAM_LEN_SIZE;
+		dpp_dtb_data_write(table_data_buff, addr_offset_bk,
+						   &entry_data); /*将数据写入缓存中*/
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",
+												 table_data_buff);
+		ZXIC_COMM_MEMSET(entry_data_cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
+		ZXIC_COMM_MEMSET(entry_data_buff, 0, DPP_ETCAM_WIDTH_MAX / 8);
+		addr_offset_bk = addr_offset_bk +
+						 DTB_ETCAM_LEN_SIZE *
+								 DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/
+
+		/*mask数据写入缓存*/
+		dtb_len += DTB_ETCAM_LEN_SIZE;
+		rc = dpp_dtb_data_write(table_data_buff, addr_offset_bk, &entry_mask);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",
+												 table_data_buff);
+		ZXIC_COMM_MEMSET(entry_mask_cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
+		ZXIC_COMM_MEMSET(entry_mask_buff, 0, 640 / 8);
+		addr_offset_bk = addr_offset_bk +
+						 DTB_ETCAM_LEN_SIZE *
+								 DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/
+
+		//处理级联数据
+		if (as_enable) {
+			p_as_eram_data = (ZXIC_UINT32 *)(p_acl_entry->p_as_rslt);
+			ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE_NO_ASSERT(
+					DEV_ID(dev), p_as_eram_data, table_data_buff);
+			eram_index = p_acl_entry->handle;
+			rc = dpp_dtb_se_smmu0_ind_write(dev, as_eram_baddr, eram_index,
+											eram_wrt_mode, p_as_eram_data,
+											&dtb_as_data_entry);
+			ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+					rc, "dpp_dtb_se_smmu0_ind_write", table_data_buff);
+
+			switch (eram_wrt_mode) {
+			case ERAM128_OPR_128b: {
+				as_dtb_len = 2;
+				as_addr_offset = DTB_LEN_POS_SETP * 2;
+				break;
+			}
+
+			case ERAM128_OPR_64b: {
+				as_dtb_len = 1;
+				as_addr_offset = DTB_LEN_POS_SETP;
+				break;
+			}
+
+			case ERAM128_OPR_1b: {
+				as_dtb_len = 1;
+				as_addr_offset = DTB_LEN_POS_SETP;
+				break;
+			}
+			}
+
+			/*将表格式和数据写入缓存buff中*/
+			rc = dpp_dtb_data_write(table_data_buff, addr_offset_bk,
+									&dtb_as_data_entry);
+			addr_offset_bk =
+					addr_offset_bk + as_addr_offset; /*在缓存中相对于0的offset*/
+			dtb_len += as_dtb_len;
+			ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",
+													 table_data_buff);
+			ZXIC_COMM_MEMSET(as_eram_cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
+			ZXIC_COMM_MEMSET(as_eram_data_buff, 0, 4 * sizeof(ZXIC_UINT32));
+		}
+	}
+
+	if (dpp_dtb_prt_get()) {
+		dpp_data_buff_print(table_data_buff, dtb_len * 16);
+	}
+
+	rc = dpp_dtb_write_down_table_data(dev, queue_id, dtb_len * 16,
+									   table_data_buff, element_id);
+	ZXIC_COMM_FREE(table_data_buff);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_down_table_data");
+
+	rc = dpp_dtb_tab_down_success_status_check(dev, queue_id, *element_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_down_success_status_check");
+
+	return DPP_OK;
 }
 
 #endif /*DTB BASE INTERFACE*/
 
 #if ZXIC_REAL("DTB_DOWN_INTERFACE")
 /** dtb写eRam表--支持大数据量
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   sdt_no    eram表sdt表号
-* @param   entry_cnt 下发的条目数
-* @param   p_entry_arr   待下发表项内容结构体数组指针
-* @param   element_id   返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_eram_dma_write(DPP_DEV_T *dev, 
-                                      ZXIC_UINT32 queue_id, 
-                                      ZXIC_UINT32 sdt_no, 
-                                      ZXIC_UINT32 entry_num, 
-                                      DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr,
-                                      ZXIC_UINT32 *element_id
-                                      )
+ * @param   dev_id    设备号
+ * @param   queue_id  队列号
+ * @param   sdt_no    eram表sdt表号
+ * @param   entry_cnt 下发的条目数
+ * @param   p_entry_arr   待下发表项内容结构体数组指针
+ * @param   element_id   返回下表使用的元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_eram_dma_write(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								  ZXIC_UINT32 sdt_no, ZXIC_UINT32 entry_num,
+								  DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr,
+								  ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 wrt_mode;
-    ZXIC_UINT32 entry_num_max = 0;
-    ZXIC_UINT32 entry_cycle = 0;
-    ZXIC_UINT32 entry_remains = 0;
-    ZXIC_UINT32 i = 0;
-    DPP_DTB_ERAM_ENTRY_INFO_T *p_entry = NULL;
-
-    DPP_SDTTBL_ERAM_T sdt_eram_info = {0};
-
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_eram_info);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get");
-
-    wrt_mode = sdt_eram_info.eram_mode;//3:128
-
-    switch (wrt_mode)
-    {
-        case ERAM128_TBL_128b:
-        {
-            entry_num_max = 0x1ff;
-            break;
-        }
-
-        case ERAM128_TBL_64b:
-        {
-            entry_num_max = 0x3ff;
-            break;
-        }
-
-        case ERAM128_TBL_1b:
-        {
-            entry_num_max = 0x3ff;
-            break;
-        }
-    }
-
-    ZXIC_COMM_CHECK_INDEX_EQUAL(entry_num_max, 0);
-    entry_cycle = entry_num / entry_num_max;
-    entry_remains = entry_num % entry_num_max;
-
-    for(i = 0; i < entry_cycle; ++i)
-    {
-        p_entry = p_entry_arr + entry_num_max * i;
-        rc = dpp_dtb_eram_dma_write_cycle(dev,
-                                     queue_id,
-                                     sdt_no,
-                                     entry_num_max,
-                                     p_entry,
-                                     element_id);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_dma_write_cycle");
-
-        ZXIC_COMM_TRACE_INFO("dpp_dtb_eram_dma_write_cycle: slot [%d] queue [%d] element_id [%d] done.\n",DEV_PCIE_SLOT(dev), queue_id, *element_id);
-    }
-
-    if(entry_remains)
-    {
-        p_entry = p_entry_arr + entry_num_max * entry_cycle;
-        rc = dpp_dtb_eram_dma_write_cycle(dev,
-                                     queue_id,
-                                     sdt_no,
-                                     entry_remains,
-                                     p_entry,
-                                     element_id);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_dma_write_cycle");
-
-        ZXIC_COMM_TRACE_INFO("dpp_dtb_eram_dma_write_cycle: slot [%d] queue [%d] element_id [%d] done.\n",DEV_PCIE_SLOT(dev), queue_id, *element_id);
-
-    }
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 wrt_mode;
+	ZXIC_UINT32 entry_num_max = 0;
+	ZXIC_UINT32 entry_cycle = 0;
+	ZXIC_UINT32 entry_remains = 0;
+	ZXIC_UINT32 i = 0;
+	DPP_DTB_ERAM_ENTRY_INFO_T *p_entry = NULL;
+
+	DPP_SDTTBL_ERAM_T sdt_eram_info = { 0 };
+
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_eram_info);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get");
+
+	wrt_mode = sdt_eram_info.eram_mode; // 3:128
+
+	switch (wrt_mode) {
+	case ERAM128_TBL_128b: {
+		entry_num_max = 0x1ff;
+		break;
+	}
+
+	case ERAM128_TBL_64b: {
+		entry_num_max = 0x3ff;
+		break;
+	}
+
+	case ERAM128_TBL_1b: {
+		entry_num_max = 0x3ff;
+		break;
+	}
+	}
+
+	ZXIC_COMM_CHECK_INDEX_EQUAL(entry_num_max, 0);
+	entry_cycle = entry_num / entry_num_max;
+	entry_remains = entry_num % entry_num_max;
+
+	for (i = 0; i < entry_cycle; ++i) {
+		p_entry = p_entry_arr + entry_num_max * i;
+		rc = dpp_dtb_eram_dma_write_cycle(dev, queue_id, sdt_no, entry_num_max,
+										  p_entry, element_id);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_dma_write_cycle");
+
+		ZXIC_COMM_TRACE_INFO(
+				"dpp_dtb_eram_dma_write_cycle: slot [%d] queue [%d] element_id [%d] done.\n",
+				DEV_PCIE_SLOT(dev), queue_id, *element_id);
+	}
+
+	if (entry_remains) {
+		p_entry = p_entry_arr + entry_num_max * entry_cycle;
+		rc = dpp_dtb_eram_dma_write_cycle(dev, queue_id, sdt_no, entry_remains,
+										  p_entry, element_id);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_dma_write_cycle");
+
+		ZXIC_COMM_TRACE_INFO(
+				"dpp_dtb_eram_dma_write_cycle: slot [%d] queue [%d] element_id [%d] done.\n",
+				DEV_PCIE_SLOT(dev), queue_id, *element_id);
+	}
+
+	return DPP_OK;
 }
 
-DPP_STATUS dpp_dtb_hash_dma_insert(DPP_DEV_T *dev, 
-                                   ZXIC_UINT32 queue_id, 
-                                   ZXIC_UINT32 sdt_no, 
-                                   ZXIC_UINT32 entry_num, 
-                                   DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry,
-                                   ZXIC_UINT32 *element_id)
+DPP_STATUS dpp_dtb_hash_dma_insert(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								   ZXIC_UINT32 sdt_no, ZXIC_UINT32 entry_num,
+								   DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry,
+								   ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 entry_num_max = 0;
-    ZXIC_UINT32 entry_cycle = 0;
-    ZXIC_UINT32 entry_remains = 0;
-    ZXIC_UINT32 i = 0;
-    DPP_DTB_HASH_ENTRY_INFO_T *p_entry = NULL;
-
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-
-    entry_num_max = 0xcc;//按512bit数据进行计算
-
-    entry_cycle = entry_num / entry_num_max;
-    entry_remains = entry_num % entry_num_max;
-
-    for(i = 0; i < entry_cycle; ++i)
-    {
-        p_entry = p_arr_hash_entry + entry_num_max * i;
-        rc = dpp_dtb_hash_dma_insert_cycle(dev,
-                                     queue_id,
-                                     sdt_no,
-                                     entry_num_max,
-                                     p_entry,
-                                     element_id);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_dma_insert_cycle");
-        ZXIC_COMM_TRACE_INFO("dpp_dtb_hash_dma_insert_cycle: slot [%d] queue [%d] element_id [%d] done.\n",DEV_PCIE_SLOT(dev), queue_id, *element_id);
-    }
-
-    if(entry_remains)
-    {
-        p_entry = p_arr_hash_entry + entry_num_max * entry_cycle;
-        rc = dpp_dtb_hash_dma_insert_cycle(dev,
-                                     queue_id,
-                                     sdt_no,
-                                     entry_remains,
-                                     p_entry,
-                                     element_id);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_dma_insert_cycle");
-        ZXIC_COMM_TRACE_INFO("dpp_dtb_hash_dma_insert_cycle: slot [%d] queue [%d] element_id [%d] done.\n",DEV_PCIE_SLOT(dev), queue_id, *element_id);
-    }
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 entry_num_max = 0;
+	ZXIC_UINT32 entry_cycle = 0;
+	ZXIC_UINT32 entry_remains = 0;
+	ZXIC_UINT32 i = 0;
+	DPP_DTB_HASH_ENTRY_INFO_T *p_entry = NULL;
+
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+
+	entry_num_max = 0xcc; //按512bit数据进行计算
+
+	entry_cycle = entry_num / entry_num_max;
+	entry_remains = entry_num % entry_num_max;
+
+	for (i = 0; i < entry_cycle; ++i) {
+		p_entry = p_arr_hash_entry + entry_num_max * i;
+		rc = dpp_dtb_hash_dma_insert_cycle(dev, queue_id, sdt_no, entry_num_max,
+										   p_entry, element_id);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_dma_insert_cycle");
+		ZXIC_COMM_TRACE_INFO(
+				"dpp_dtb_hash_dma_insert_cycle: slot [%d] queue [%d] element_id [%d] done.\n",
+				DEV_PCIE_SLOT(dev), queue_id, *element_id);
+	}
+
+	if (entry_remains) {
+		p_entry = p_arr_hash_entry + entry_num_max * entry_cycle;
+		rc = dpp_dtb_hash_dma_insert_cycle(dev, queue_id, sdt_no, entry_remains,
+										   p_entry, element_id);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_dma_insert_cycle");
+		ZXIC_COMM_TRACE_INFO(
+				"dpp_dtb_hash_dma_insert_cycle: slot [%d] queue [%d] element_id [%d] done.\n",
+				DEV_PCIE_SLOT(dev), queue_id, *element_id);
+	}
+
+	return DPP_OK;
 }
 
 /** dtb删除HASH表
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   sdt_no    hash表sdt表号
-* @param   entry_cnt 删除的条目数
-* @param   p_entry_arr   待下发表项内容结构体数组指针
-* @param   element_id   返回下表使用的元素id
-* @return
-* @remark  无 
-* @see
-* @author        @date  2023/03/14
-************************************************************/
-DPP_STATUS dpp_dtb_hash_dma_delete(DPP_DEV_T *dev, 
-                                   ZXIC_UINT32 queue_id, 
-                                   ZXIC_UINT32 sdt_no, 
-                                   ZXIC_UINT32 entry_num, 
-                                   DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry,
-                                   ZXIC_UINT32 *element_id)
+ * @param   dev_id    设备号
+ * @param   queue_id  队列号
+ * @param   sdt_no    hash表sdt表号
+ * @param   entry_cnt 删除的条目数
+ * @param   p_entry_arr   待下发表项内容结构体数组指针
+ * @param   element_id   返回下表使用的元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author        @date  2023/03/14
+ ************************************************************/
+DPP_STATUS dpp_dtb_hash_dma_delete(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								   ZXIC_UINT32 sdt_no, ZXIC_UINT32 entry_num,
+								   DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry,
+								   ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT8 key_valid = 1;
-    ZXIC_UINT32 item_cnt = 0;
-    ZXIC_UINT32 ddr_wr_mode = 0;
-    ZXIC_UINT32 dtb_len = 0;
-    
-    SE_ITEM_CFG *p_item = NULL;
-    ZXIC_RB_TN *p_rb_tn_rtn = NULL;
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    DPP_HASH_RBKEY_INFO *p_rbkey_rtn = NULL;
-    DPP_HASH_RBKEY_INFO temp_rbkey = {{0}};
-    ZXIC_UINT8 *p_data_buff = NULL;
-
-    HASH_ENTRY_CFG  hash_entry_cfg = {0}; 
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_arr_hash_entry);
-
-    //从sdt_no中获取hash配置
-    rc = dpp_hash_get_hash_info_from_sdt(DEV_ID(dev), sdt_no, &hash_entry_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_hash_get_hash_info_from_sdt");
-
-    p_hash_cfg = hash_entry_cfg.p_hash_cfg;
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg);
-
-     /*条目数上限检查*/
-    ddr_wr_mode = DPP_GET_DDR_WR_MODE(hash_entry_cfg.key_type);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), entry_num, 1, DTB_DATA_SIZE_BIT / ( (ddr_wr_mode + 2) * DTB_TABLE_CMD_SIZE_BIT));
-
-    p_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data_buff);
-    ZXIC_COMM_MEMSET(p_data_buff,0x0,DPP_DTB_TABLE_DATA_BUFF_SIZE);
-    
-      /*对每一个条目进行处理*/
-    for(item_cnt = 0; item_cnt < entry_num; ++item_cnt)
-    {
-        ZXIC_COMM_MEMSET(&temp_rbkey,0x0,sizeof(DPP_HASH_RBKEY_INFO));
-        temp_rbkey.key[0] = (ZXIC_UINT8)(((key_valid & 0x1) << 7) | ((hash_entry_cfg.key_type & 0x3) << 5) | (hash_entry_cfg.table_id & 0x1f));
-        ZXIC_COMM_MEMCPY(&temp_rbkey.key[1], p_arr_hash_entry[item_cnt].p_actu_key, hash_entry_cfg.actu_key_size);
-        rc = zxic_comm_rb_delete(&p_hash_cfg->hash_rb, &temp_rbkey, &p_rb_tn_rtn);
-        if (ZXIC_RBT_RC_SRHFAIL == rc)
-        {
-            p_hash_cfg->hash_stat.delete_fail++;
-            ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "Error!there is not item in hash!\n");
-            continue;
-        }
-
-        ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(p_rb_tn_rtn,p_data_buff);
-
-        p_rbkey_rtn = (DPP_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key);
-        ZXIC_COMM_MEMSET(p_rbkey_rtn->rst,0x0,sizeof(p_rbkey_rtn->rst));
-        hash_entry_cfg.p_rbkey_new = p_rbkey_rtn;
-        hash_entry_cfg.p_rb_tn_new = p_rb_tn_rtn;
-
-        p_item = p_rbkey_rtn->p_item_info;
-        rc = zxic_comm_double_link_del(&(p_rbkey_rtn->entry_dn), &(p_item->item_list));
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "zxic_comm_double_link_del",p_data_buff);
-        p_item->wrt_mask &= ~(DPP_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, p_rbkey_rtn->entry_pos)) & 0xF;
-
-        /*将位置信息和数据信息写入buff中*/
-        rc = dpp_dtb_delete_hash_buf_write(DEV_ID(dev),&hash_entry_cfg,p_data_buff,item_cnt,&dtb_len);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_hash_form_write",p_data_buff);
-
-        if (0 == p_item->item_list.used)
-        {
-            if ((ITEM_DDR_256 == p_item->item_type) || (ITEM_DDR_512 == p_item->item_type))
-            {
-                /* modify coverity by yinxh 2021.03.10*,以256bit为单位。暂不考虑512bit的情况*/
-                ZXIC_COMM_CHECK_INDEX_UPPER_MEMORY_FREE(
-                                         p_item->item_index, 
-                                         p_hash_cfg->p_bulk_ddr_info[hash_entry_cfg.bulk_id]->item_num,
-                                         p_data_buff);
-                p_hash_cfg->p_bulk_ddr_info[hash_entry_cfg.bulk_id]->p_item_array[p_item->item_index] = NULL;
-                ZXIC_COMM_FREE(p_item);
-            }
-            else
-            {
-                p_item->valid = 0;
-            }
-        }
-
-        ZXIC_COMM_FREE(p_rbkey_rtn);
-        ZXIC_COMM_FREE(p_rb_tn_rtn);
-
-        p_hash_cfg->hash_stat.delete_ok++;
-    }
-    
-    if(dtb_len)
-    {
-        rc = dpp_dtb_write_down_table_data(dev,  
-                                     queue_id, 
-                                     dtb_len * 16,
-                                     p_data_buff,
-                                     element_id);                               
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_write_down_table_data",p_data_buff);
-    }
-    ZXIC_COMM_FREE(p_data_buff);  
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT8 key_valid = 1;
+	ZXIC_UINT32 item_cnt = 0;
+	ZXIC_UINT32 ddr_wr_mode = 0;
+	ZXIC_UINT32 dtb_len = 0;
+
+	SE_ITEM_CFG *p_item = NULL;
+	ZXIC_RB_TN *p_rb_tn_rtn = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	DPP_HASH_RBKEY_INFO *p_rbkey_rtn = NULL;
+	DPP_HASH_RBKEY_INFO temp_rbkey = { { 0 } };
+	ZXIC_UINT8 *p_data_buff = NULL;
+
+	HASH_ENTRY_CFG hash_entry_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_LOWER(DEV_ID(dev), entry_num, 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_arr_hash_entry);
+
+	//从sdt_no中获取hash配置
+	rc = dpp_hash_get_hash_info_from_sdt(DEV_ID(dev), sdt_no, &hash_entry_cfg);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_hash_get_hash_info_from_sdt");
+
+	p_hash_cfg = hash_entry_cfg.p_hash_cfg;
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg);
+
+	/*条目数上限检查*/
+	ddr_wr_mode = DPP_GET_DDR_WR_MODE(hash_entry_cfg.key_type);
+	ZXIC_COMM_CHECK_DEV_INDEX(
+			DEV_ID(dev), entry_num, 1,
+			DTB_DATA_SIZE_BIT / ((ddr_wr_mode + 2) * DTB_TABLE_CMD_SIZE_BIT));
+
+	p_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data_buff);
+	ZXIC_COMM_MEMSET(p_data_buff, 0x0, DPP_DTB_TABLE_DATA_BUFF_SIZE);
+
+	/*对每一个条目进行处理*/
+	for (item_cnt = 0; item_cnt < entry_num; ++item_cnt) {
+		ZXIC_COMM_MEMSET(&temp_rbkey, 0x0, sizeof(DPP_HASH_RBKEY_INFO));
+		temp_rbkey.key[0] =
+				(ZXIC_UINT8)(((key_valid & 0x1) << 7) |
+							 ((hash_entry_cfg.key_type & 0x3) << 5) |
+							 (hash_entry_cfg.table_id & 0x1f));
+		ZXIC_COMM_MEMCPY(&temp_rbkey.key[1],
+						 p_arr_hash_entry[item_cnt].p_actu_key,
+						 hash_entry_cfg.actu_key_size);
+		rc = zxic_comm_rb_delete(&p_hash_cfg->hash_rb, &temp_rbkey,
+								 &p_rb_tn_rtn);
+		if (ZXIC_RBT_RC_SRHFAIL == rc) {
+			p_hash_cfg->hash_stat.delete_fail++;
+			ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev),
+									  "Error!there is not item in hash!\n");
+			continue;
+		}
+
+		ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(p_rb_tn_rtn, p_data_buff);
+
+		p_rbkey_rtn = (DPP_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key);
+		ZXIC_COMM_MEMSET(p_rbkey_rtn->rst, 0x0, sizeof(p_rbkey_rtn->rst));
+		hash_entry_cfg.p_rbkey_new = p_rbkey_rtn;
+		hash_entry_cfg.p_rb_tn_new = p_rb_tn_rtn;
+
+		p_item = p_rbkey_rtn->p_item_info;
+		rc = zxic_comm_double_link_del(&(p_rbkey_rtn->entry_dn),
+									   &(p_item->item_list));
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+				rc, "zxic_comm_double_link_del", p_data_buff);
+		p_item->wrt_mask &= ~(DPP_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size,
+													  p_rbkey_rtn->entry_pos)) &
+							0xF;
+
+		/*将位置信息和数据信息写入buff中*/
+		rc = dpp_dtb_delete_hash_buf_write(DEV_ID(dev), &hash_entry_cfg,
+										   p_data_buff, item_cnt, &dtb_len);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_hash_form_write",
+												 p_data_buff);
+
+		if (0 == p_item->item_list.used) {
+			if ((ITEM_DDR_256 == p_item->item_type) ||
+				(ITEM_DDR_512 == p_item->item_type)) {
+				/* modify coverity by yinxh 2021.03.10*,以256bit为单位。暂不考虑512bit的情况*/
+				ZXIC_COMM_CHECK_INDEX_UPPER_MEMORY_FREE(
+						p_item->item_index,
+						p_hash_cfg->p_bulk_ddr_info[hash_entry_cfg.bulk_id]
+								->item_num,
+						p_data_buff);
+				p_hash_cfg->p_bulk_ddr_info[hash_entry_cfg.bulk_id]
+						->p_item_array[p_item->item_index] = NULL;
+				ZXIC_COMM_FREE(p_item);
+			} else {
+				p_item->valid = 0;
+			}
+		}
+
+		ZXIC_COMM_FREE(p_rbkey_rtn);
+		ZXIC_COMM_FREE(p_rb_tn_rtn);
+
+		p_hash_cfg->hash_stat.delete_ok++;
+	}
+
+	if (dtb_len) {
+		rc = dpp_dtb_write_down_table_data(dev, queue_id, dtb_len * 16,
+										   p_data_buff, element_id);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+				rc, "dpp_dtb_write_down_table_data", p_data_buff);
+
+		rc = dpp_dtb_tab_down_success_status_check(dev, queue_id, *element_id);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+				rc, "dpp_dtb_tab_down_success_status_check", p_data_buff);
+	}
+	ZXIC_COMM_FREE(p_data_buff);
+
+	return DPP_OK;
 }
 
 /** dtb删除所有的HASH表(硬件查找，硬件删除)
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   sdt_no    hash表sdt表号
-* @param   entry_cnt 删除的条目数
-* @param   p_entry_arr   待下发表项内容结构体数组指针
-* @param   element_id   返回下表使用的元素id
-* @return
-* @remark  无 
-* @see
-* @author   cq     @date  2023/12/02
-************************************************************/
-DPP_STATUS dpp_dtb_hash_dma_delete_hardware(DPP_DEV_T *dev, 
-                                   ZXIC_UINT32 queue_id, 
-                                   ZXIC_UINT32 sdt_no, 
-                                   ZXIC_UINT32 entry_num, 
-                                   DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry,
-                                   ZXIC_UINT32 *element_id)
+ * @param   dev_id    设备号
+ * @param   queue_id  队列号
+ * @param   sdt_no    hash表sdt表号
+ * @param   entry_cnt 删除的条目数
+ * @param   p_entry_arr   待下发表项内容结构体数组指针
+ * @param   element_id   返回下表使用的元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author   cq     @date  2023/12/02
+ ************************************************************/
+DPP_STATUS
+dpp_dtb_hash_dma_delete_hardware(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								 ZXIC_UINT32 sdt_no, ZXIC_UINT32 entry_num,
+								 DPP_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry,
+								 ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS rc = DPP_OK;
-    //ZXIC_UINT32 ddr_wr_mode = 0;
-    ZXIC_UINT32 item_cnt = 0;
-    ZXIC_UINT32 dtb_len = 0;
-    ZXIC_UINT8 srh_succ = 0;
-    ZXIC_UINT8 key[HASH_KEY_MAX] = {0};
-    ZXIC_UINT8 rst[HASH_RST_MAX] = {0};
-    ZXIC_UINT8 entry_cmd[DTB_TABLE_CMD_SIZE_BIT / 8] = {0};
-    ZXIC_UINT8 entry_data[DPP_ETCAM_WIDTH_MAX/8] = {0};   /*兼容所有表项，按照最大位宽分配，acl最大为640bit(80B)*/
-    ZXIC_UINT8 *p_data_buff = NULL;
-    ZXIC_UINT32 dev_id = 0;
-
-    DPP_HASH_ENTRY  entry = {0};
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    DPP_DTB_ENTRY_T   dtb_one_entry = {0};
-    HASH_ENTRY_CFG  hash_entry_cfg = {0}; 
-
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-    dev_id = DEV_ID(dev);
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_arr_hash_entry);
-
-    dtb_one_entry.cmd = entry_cmd;
-    dtb_one_entry.data = entry_data;
-    entry.p_key = key;
-    entry.p_rst = rst;
-
-    //从sdt_no中获取hash配置
-    rc = dpp_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_get_hash_info_from_sdt");
-
-    p_hash_cfg = hash_entry_cfg.p_hash_cfg;
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg);
-    
-     /*条目数上限检查*/
-    //ddr_wr_mode = DPP_GET_DDR_WR_MODE(hash_entry_cfg.key_type);
-    //ZXIC_COMM_CHECK_DEV_INDEX(dev_id, entry_num, 1, DTB_DATA_SIZE_BIT / ( (ddr_wr_mode + 2) * DTB_TABLE_CMD_SIZE_BIT));
-
-    p_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data_buff);
-    ZXIC_COMM_MEMSET(p_data_buff,0x0,DPP_DTB_TABLE_DATA_BUFF_SIZE);
-    
-      /*对每一个条目进行处理*/
-    for(item_cnt = 0; item_cnt < entry_num; ++item_cnt)
-    {
-        srh_succ = 0;
-        ZXIC_COMM_MEMSET(key,0x0,sizeof(key));
-        ZXIC_COMM_MEMSET(rst,0x0,sizeof(rst));
-        ZXIC_COMM_MEMSET(entry_cmd,0x0,sizeof(entry_cmd));
-        ZXIC_COMM_MEMSET(entry_data,0x0,sizeof(entry_data));
-        ZXIC_COMM_MEMCPY(entry.p_key, p_arr_hash_entry[item_cnt].p_actu_key, hash_entry_cfg.key_by_size);
-
-        rc = dpp_dtb_hash_zcam_delete_hardware(dev, 
-                                                  queue_id,
-                                                  &hash_entry_cfg,
-                                                  &entry,
-                                                  &dtb_one_entry,
-                                                  &srh_succ);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_hash_zcam_delete_hardware",p_data_buff);
-
-        if(srh_succ)
-        {
-            rc = dpp_dtb_data_write(p_data_buff, 0, &dtb_one_entry);
-            ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",p_data_buff); 
-            dtb_len = dtb_one_entry.data_size/DTB_LEN_POS_SETP + 1;
-
-            rc = dpp_dtb_write_down_table_data(dev,  
-                                     queue_id, 
-                                     dtb_len * DTB_LEN_POS_SETP,
-                                     p_data_buff,
-                                     element_id);                               
-            ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_write_down_table_data",p_data_buff);
-        }
-    }
-
-    ZXIC_COMM_FREE(p_data_buff);  
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	// ZXIC_UINT32 ddr_wr_mode = 0;
+	ZXIC_UINT32 item_cnt = 0;
+	ZXIC_UINT32 dtb_len = 0;
+	ZXIC_UINT8 srh_succ = 0;
+	ZXIC_UINT8 key[HASH_KEY_MAX] = { 0 };
+	ZXIC_UINT8 rst[HASH_RST_MAX] = { 0 };
+	ZXIC_UINT8 entry_cmd[DTB_TABLE_CMD_SIZE_BIT / 8] = { 0 };
+	ZXIC_UINT8 entry_data[DPP_ETCAM_WIDTH_MAX / 8] = {
+		0
+	}; /*兼容所有表项，按照最大位宽分配，acl最大为640bit(80B)*/
+	ZXIC_UINT8 *p_data_buff = NULL;
+	ZXIC_UINT32 dev_id = 0;
+
+	DPP_HASH_ENTRY entry = { 0 };
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	DPP_DTB_ENTRY_T dtb_one_entry = { 0 };
+	HASH_ENTRY_CFG hash_entry_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+	dev_id = DEV_ID(dev);
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_arr_hash_entry);
+
+	dtb_one_entry.cmd = entry_cmd;
+	dtb_one_entry.data = entry_data;
+	entry.p_key = key;
+	entry.p_rst = rst;
+
+	//从sdt_no中获取hash配置
+	rc = dpp_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_get_hash_info_from_sdt");
+
+	p_hash_cfg = hash_entry_cfg.p_hash_cfg;
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg);
+
+	/*条目数上限检查*/
+	// ddr_wr_mode = DPP_GET_DDR_WR_MODE(hash_entry_cfg.key_type);
+	// ZXIC_COMM_CHECK_DEV_INDEX(dev_id, entry_num, 1, DTB_DATA_SIZE_BIT / ( (ddr_wr_mode + 2) *
+	// DTB_TABLE_CMD_SIZE_BIT));
+
+	p_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data_buff);
+	ZXIC_COMM_MEMSET(p_data_buff, 0x0, DPP_DTB_TABLE_DATA_BUFF_SIZE);
+
+	/*对每一个条目进行处理*/
+	for (item_cnt = 0; item_cnt < entry_num; ++item_cnt) {
+		srh_succ = 0;
+		ZXIC_COMM_MEMSET(key, 0x0, sizeof(key));
+		ZXIC_COMM_MEMSET(rst, 0x0, sizeof(rst));
+		ZXIC_COMM_MEMSET(entry_cmd, 0x0, sizeof(entry_cmd));
+		ZXIC_COMM_MEMSET(entry_data, 0x0, sizeof(entry_data));
+		ZXIC_COMM_MEMCPY(entry.p_key, p_arr_hash_entry[item_cnt].p_actu_key,
+						 hash_entry_cfg.key_by_size);
+
+		rc = dpp_dtb_hash_zcam_delete_hardware(dev, queue_id, &hash_entry_cfg,
+											   &entry, &dtb_one_entry,
+											   &srh_succ);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+				rc, "dpp_dtb_hash_zcam_delete_hardware", p_data_buff);
+
+		if (srh_succ) {
+			rc = dpp_dtb_data_write(p_data_buff, 0, &dtb_one_entry);
+			ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",
+													 p_data_buff);
+			dtb_len = dtb_one_entry.data_size / DTB_LEN_POS_SETP + 1;
+
+			rc = dpp_dtb_write_down_table_data(dev, queue_id,
+											   dtb_len * DTB_LEN_POS_SETP,
+											   p_data_buff, element_id);
+			ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+					rc, "dpp_dtb_write_down_table_data", p_data_buff);
+
+			rc = dpp_dtb_tab_down_success_status_check(dev, queue_id,
+													   *element_id);
+			ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+					rc, "dpp_dtb_tab_down_success_status_check", p_data_buff);
+		}
+	}
+
+	ZXIC_COMM_FREE(p_data_buff);
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 将hash表DDR存储位宽(按照256bit/512bit划分)转换为hash在DDR中的实际位置(按照128/256/512bit划分)
-* @param   index          hash表DDR存储位宽索引(按照256bit/512bit划分)
-* @param   width_mode     DDR位宽(256bit/512bit)
-* @param   key_type       hash表项位宽DPP_HASH_KEY_TYPE
-* @param   byte_offset    hash表项在一个DDR存储位宽(256bit/512bit)里的偏移,单位为字节
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-ZXIC_UINT32 dpp_ddr_index_calc(ZXIC_UINT32 index,
-                               ZXIC_UINT32 width_mode,
-                               ZXIC_UINT32 key_type,
-                               ZXIC_UINT32 byte_offset)
+ * @param   index          hash表DDR存储位宽索引(按照256bit/512bit划分)
+ * @param   width_mode     DDR位宽(256bit/512bit)
+ * @param   key_type       hash表项位宽DPP_HASH_KEY_TYPE
+ * @param   byte_offset    hash表项在一个DDR存储位宽(256bit/512bit)里的偏移,单位为字节
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/02
+ ************************************************************/
+ZXIC_UINT32 dpp_ddr_index_calc(ZXIC_UINT32 index, ZXIC_UINT32 width_mode,
+							   ZXIC_UINT32 key_type, ZXIC_UINT32 byte_offset)
 {
-    ZXIC_UINT32 ddr_index = 0;      /*按照hash位宽128/256/512bit进行划分*/
-    ZXIC_UINT32 entry_size = 0;
-    
-    entry_size = DPP_GET_HASH_ENTRY_SIZE(key_type);
-    if(0==entry_size)
-    {
-        return ddr_index;
-    }
-
-    if(DDR_WIDTH_256b==width_mode)
-    {
-        if (HASH_KEY_128b == key_type)
-        {
-            ddr_index = (index<<1) + ((byte_offset/entry_size)&0x1);
-        }
-        else if (HASH_KEY_256b == key_type)
-        {
-            ddr_index = index;
-        }
-    }
-    else if(DDR_WIDTH_512b==width_mode)
-    {
-        if (HASH_KEY_128b == key_type)
-        {
-            ddr_index = (index<<2) + ((byte_offset/entry_size)&0x3);
-        }
-        else if (HASH_KEY_256b == key_type)
-        {
-            ddr_index = (index<<1) + ((byte_offset/entry_size)&0x1);
-        }
-        else if (HASH_KEY_512b == key_type)
-        {
-            ddr_index = index;
-        }
-    }
-
-    return ddr_index;
+	ZXIC_UINT32 ddr_index = 0; /*按照hash位宽128/256/512bit进行划分*/
+	ZXIC_UINT32 entry_size = 0;
+
+	entry_size = DPP_GET_HASH_ENTRY_SIZE(key_type);
+	if (0 == entry_size) {
+		return ddr_index;
+	}
+
+	if (DDR_WIDTH_256b == width_mode) {
+		if (HASH_KEY_128b == key_type) {
+			ddr_index = (index << 1) + ((byte_offset / entry_size) & 0x1);
+		} else if (HASH_KEY_256b == key_type) {
+			ddr_index = index;
+		}
+	} else if (DDR_WIDTH_512b == width_mode) {
+		if (HASH_KEY_128b == key_type) {
+			ddr_index = (index << 2) + ((byte_offset / entry_size) & 0x3);
+		} else if (HASH_KEY_256b == key_type) {
+			ddr_index = (index << 1) + ((byte_offset / entry_size) & 0x1);
+		} else if (HASH_KEY_512b == key_type) {
+			ddr_index = index;
+		}
+	}
+
+	return ddr_index;
 }
 
 /***********************************************************/
 /** 查找存储在ZCAM空间的hash表项并删除(硬件处理)
-* @param   dev_id       设备号，支持多芯片 
-* @param   queue_id     队列id 
-* @param   p_hash_entry_cfg hash表项配置信息
-* @param   p_hash_entry    查找键值信息
-* @param   p_entry         dtb描述符
-* @param   p_srh_succ      出参，查找是否成功
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-ZXIC_UINT32 dpp_dtb_hash_zcam_delete_hardware(DPP_DEV_T *dev, 
-                                 ZXIC_UINT32 queue_id,
-                                 HASH_ENTRY_CFG  *p_hash_entry_cfg,
-                                 DPP_HASH_ENTRY  *p_hash_entry,
-                                 DPP_DTB_ENTRY_T *p_entry,
-                                 ZXIC_UINT8 *p_srh_succ)
+ * @param   dev_id       设备号，支持多芯片
+ * @param   queue_id     队列id
+ * @param   p_hash_entry_cfg hash表项配置信息
+ * @param   p_hash_entry    查找键值信息
+ * @param   p_entry         dtb描述符
+ * @param   p_srh_succ      出参，查找是否成功
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/02
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_hash_zcam_delete_hardware(DPP_DEV_T *dev,
+											  ZXIC_UINT32 queue_id,
+											  HASH_ENTRY_CFG *p_hash_entry_cfg,
+											  DPP_HASH_ENTRY *p_hash_entry,
+											  DPP_DTB_ENTRY_T *p_entry,
+											  ZXIC_UINT8 *p_srh_succ)
 {
-    DPP_STATUS rc = DPP_OK;
-    DPP_HASH_RBKEY_INFO srh_rbkey = {0};
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    SE_ZCELL_CFG *p_zcell = NULL;
-    SE_ZBLK_CFG *p_zblk = NULL;
-
-    ZXIC_UINT32 zblk_idx = 0;
-    ZXIC_UINT32 pre_zblk_idx = 0xFFFFFFFF;/* -1; */
-    ZXIC_UINT16 crc16_value = 0;
-    ZXIC_UINT32 zcell_id = 0;
-    ZXIC_UINT32 item_idx = 0;
-    ZXIC_UINT32 element_id = 0;
-    ZXIC_UINT8 byte_offset = 0;
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 addr = 0;
-    ZXIC_UINT32 i    = 0;
-    ZXIC_UINT8 srh_succ     = 0;
-    ZXIC_UINT8 temp_key[HASH_KEY_MAX] = {0};
-    ZXIC_UINT8  rd_buff[SE_ITEM_WIDTH_MAX]   = {0};
-
-    D_NODE *p_zblk_dn = NULL;
-    D_NODE *p_zcell_dn = NULL;
-    DPP_SE_CFG *p_se_cfg = NULL;
-
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-    dev_id = DEV_ID(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
-    ZXIC_COMM_CHECK_POINT(p_srh_succ);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry->p_key);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry->p_rst);
-
-    ZXIC_COMM_MEMSET(rd_buff,0x0,sizeof(rd_buff));
-    ZXIC_COMM_MEMSET(&srh_rbkey,0x0,sizeof(DPP_HASH_RBKEY_INFO));
-    ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->key_by_size, HASH_KEY_MAX);
-    ZXIC_COMM_MEMCPY(srh_rbkey.key,p_hash_entry->p_key,p_hash_entry_cfg->key_by_size);
-   
-    p_hash_cfg = p_hash_entry_cfg->p_hash_cfg;
-    ZXIC_COMM_CHECK_POINT(p_hash_cfg);
-    
-    /* 取出se配置 */
-    rc = dpp_se_cfg_get(dev_id, &p_se_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_cfg_get");
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg);
-    
-    ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->key_by_size, HASH_KEY_MAX);
-    rc = dpp_hash_set_crc_key(dev,p_hash_entry_cfg,p_hash_entry,temp_key);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id,rc,"hash_set_crc_key");
-
-    /*查找所有的zcell*/
-    p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next;
-    while (p_zcell_dn)
-    {
-        p_zcell = (SE_ZCELL_CFG *)p_zcell_dn->data;
-        zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx);
-        ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zblk_idx, 0, SE_ZBLK_NUM - 1);
-        p_zblk = &(p_se_cfg->zblk_info[zblk_idx]);
-
-        if (zblk_idx != pre_zblk_idx)
-        {
-            pre_zblk_idx = zblk_idx;
-            crc16_value = p_hash_cfg->p_hash16_fun(temp_key, p_hash_entry_cfg->key_by_size, p_zblk->hash_arg);
-        }
-
-        zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx);
-        item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc16_value);
-        ZXIC_COMM_CHECK_DEV_INDEX(dev_id, item_idx, 0, SE_RAM_DEPTH - 1);
-        addr = ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx);
-        rc =  dpp_dtb_se_zcam_dma_dump(dev, 
-                                       queue_id, 
-                                       addr, 
-                                       DTB_DUMP_ZCAM_512b, 
-                                       1,
-                                       (ZXIC_UINT32 *)rd_buff, 
-                                       &element_id);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_se_zcam_dma_dump");
-        zxic_comm_swap(rd_buff,sizeof(rd_buff));
-        
-        rc = dpp_dtb_hash_data_parse(ITEM_RAM,p_hash_entry_cfg->key_by_size,p_hash_entry,rd_buff,&byte_offset);
-        if(DPP_OK == rc)
-        {
-            ZXIC_COMM_TRACE_DEBUG("Hash search hardware succ in zcell. \n");
-            srh_succ = 1;
-            p_hash_cfg->hash_stat.search_ok++;
-            break;
-        }
-        
-        p_zcell_dn = p_zcell_dn->next;
-    }
-
-    /*zcell查找失败，则查找所有的zreg*/
-    if(0==srh_succ)
-    {
-        p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next;
-        while (p_zblk_dn)
-        {
-            p_zblk = (SE_ZBLK_CFG *)p_zblk_dn->data;
-            zblk_idx = p_zblk->zblk_idx;
-
-            for (i = 0; i < SE_ZREG_NUM; i++)
-            {
-                item_idx = i;
-                addr = ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, item_idx);
-                rc =  dpp_dtb_se_zcam_dma_dump(dev, 
-                                       queue_id, 
-                                       addr, 
-                                       DTB_DUMP_ZCAM_512b, 
-                                       1,
-                                       (ZXIC_UINT32 *)rd_buff, 
-                                       &element_id);
-                ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_se_zcam_dma_dump");
-                zxic_comm_swap(rd_buff,sizeof(rd_buff));
-
-                rc = dpp_dtb_hash_data_parse(ITEM_RAM,p_hash_entry_cfg->key_by_size,p_hash_entry,rd_buff,&byte_offset);
-                if(DPP_OK == rc)
-                {
-                    ZXIC_COMM_TRACE_DEBUG("Hash search hardware succ in zreg. \n");
-                    srh_succ = 1;
-                    p_hash_cfg->hash_stat.search_ok++;
-                    break;
-                }
-            }
-            p_zblk_dn = p_zblk_dn->next;
-        }
-    }
-
-    /*查找成功，则将对应表项删除*/
-    if(srh_succ)
-    {
-        ZXIC_COMM_MEMSET(rd_buff+byte_offset,0x0,DPP_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type));
-        zxic_comm_swap(rd_buff,sizeof(rd_buff));
-        rc = dpp_dtb_se_alg_zcam_data_write(dev_id,
-                                       addr,
-                                       rd_buff,
-                                       p_entry);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id,rc,"dpp_dtb_se_alg_zcam_data_write");
-        p_hash_cfg->hash_stat.delete_ok++;
-    }
-
-    *p_srh_succ = srh_succ;
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	DPP_HASH_RBKEY_INFO srh_rbkey = { 0 };
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	SE_ZCELL_CFG *p_zcell = NULL;
+	SE_ZBLK_CFG *p_zblk = NULL;
+
+	ZXIC_UINT32 zblk_idx = 0;
+	ZXIC_UINT32 pre_zblk_idx = 0xFFFFFFFF; /* -1; */
+	ZXIC_UINT16 crc16_value = 0;
+	ZXIC_UINT32 zcell_id = 0;
+	ZXIC_UINT32 item_idx = 0;
+	ZXIC_UINT32 element_id = 0;
+	ZXIC_UINT8 byte_offset = 0;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 addr = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT8 srh_succ = 0;
+	ZXIC_UINT8 temp_key[HASH_KEY_MAX] = { 0 };
+	ZXIC_UINT8 rd_buff[SE_ITEM_WIDTH_MAX] = { 0 };
+
+	D_NODE *p_zblk_dn = NULL;
+	D_NODE *p_zcell_dn = NULL;
+	DPP_SE_CFG *p_se_cfg = NULL;
+
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+	dev_id = DEV_ID(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
+	ZXIC_COMM_CHECK_POINT(p_srh_succ);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry->p_key);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry->p_rst);
+
+	ZXIC_COMM_MEMSET(rd_buff, 0x0, sizeof(rd_buff));
+	ZXIC_COMM_MEMSET(&srh_rbkey, 0x0, sizeof(DPP_HASH_RBKEY_INFO));
+	ZXIC_COMM_MEMCPY(srh_rbkey.key, p_hash_entry->p_key,
+					 p_hash_entry_cfg->key_by_size);
+
+	p_hash_cfg = p_hash_entry_cfg->p_hash_cfg;
+	ZXIC_COMM_CHECK_POINT(p_hash_cfg);
+
+	/* 取出se配置 */
+	rc = dpp_se_cfg_get(dev_id, &p_se_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_cfg_get");
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg);
+
+	rc = dpp_hash_set_crc_key(dev, p_hash_entry_cfg, p_hash_entry, temp_key);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "hash_set_crc_key");
+
+	/*查找所有的zcell*/
+	p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next;
+	while (p_zcell_dn) {
+		p_zcell = (SE_ZCELL_CFG *)p_zcell_dn->data;
+		zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx);
+		ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zblk_idx, 0, SE_ZBLK_NUM - 1);
+		p_zblk = &(p_se_cfg->zblk_info[zblk_idx]);
+
+		if (zblk_idx != pre_zblk_idx) {
+			pre_zblk_idx = zblk_idx;
+			crc16_value = p_hash_cfg->p_hash16_fun(
+					temp_key, p_hash_entry_cfg->key_by_size, p_zblk->hash_arg);
+		}
+
+		zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx);
+		item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc16_value);
+		ZXIC_COMM_CHECK_DEV_INDEX(dev_id, item_idx, 0, SE_RAM_DEPTH - 1);
+		addr = ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx);
+		rc = dpp_dtb_se_zcam_dma_dump(dev, queue_id, addr, DTB_DUMP_ZCAM_512b,
+									  1, (ZXIC_UINT32 *)rd_buff, &element_id);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_se_zcam_dma_dump");
+		zxic_comm_swap(rd_buff, sizeof(rd_buff));
+
+		rc = dpp_dtb_hash_data_parse(ITEM_RAM, p_hash_entry_cfg->key_by_size,
+									 p_hash_entry, rd_buff, &byte_offset);
+		if (DPP_OK == rc) {
+			ZXIC_COMM_TRACE_DEBUG("Hash search hardware succ in zcell. \n");
+			srh_succ = 1;
+			p_hash_cfg->hash_stat.search_ok++;
+			break;
+		}
+
+		p_zcell_dn = p_zcell_dn->next;
+	}
+
+	/*zcell查找失败，则查找所有的zreg*/
+	if (0 == srh_succ) {
+		p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next;
+		while (p_zblk_dn) {
+			p_zblk = (SE_ZBLK_CFG *)p_zblk_dn->data;
+			zblk_idx = p_zblk->zblk_idx;
+
+			for (i = 0; i < SE_ZREG_NUM; i++) {
+				item_idx = i;
+				addr = ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, item_idx);
+				rc = dpp_dtb_se_zcam_dma_dump(dev, queue_id, addr,
+											  DTB_DUMP_ZCAM_512b, 1,
+											  (ZXIC_UINT32 *)rd_buff,
+											  &element_id);
+				ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_se_zcam_dma_dump");
+				zxic_comm_swap(rd_buff, sizeof(rd_buff));
+
+				rc = dpp_dtb_hash_data_parse(ITEM_RAM,
+											 p_hash_entry_cfg->key_by_size,
+											 p_hash_entry, rd_buff,
+											 &byte_offset);
+				if (DPP_OK == rc) {
+					ZXIC_COMM_TRACE_DEBUG(
+							"Hash search hardware succ in zreg. \n");
+					srh_succ = 1;
+					p_hash_cfg->hash_stat.search_ok++;
+					break;
+				}
+			}
+			p_zblk_dn = p_zblk_dn->next;
+		}
+	}
+
+	/*查找成功，则将对应表项删除*/
+	if (srh_succ) {
+		ZXIC_COMM_MEMSET(rd_buff + byte_offset, 0x0,
+						 DPP_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type));
+		zxic_comm_swap(rd_buff, sizeof(rd_buff));
+		rc = dpp_dtb_se_alg_zcam_data_write(dev_id, addr, rd_buff, p_entry);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_dtb_se_alg_zcam_data_write");
+		p_hash_cfg->hash_stat.delete_ok++;
+	}
+
+	*p_srh_succ = srh_succ;
+
+	return DPP_OK;
 }
 
 /** dtb写ACL表 （SPECIFY模式，条目中指定handle，支持级联64bit/128bit）
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   sdt_no    ACL表sdt表号
-* @param   entry_num 下发的条目数
-* @param   p_acl_entry_arr   待下发表项内容结构体数组指针
-* @param   element_id    返回下表使用的元素id
-* @return
-* @remark  无 是否是有一个写不成功就返回，还是继续进行下一个条目并记录错误的条目
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_acl_dma_insert(DPP_DEV_T *dev,  
-                                      ZXIC_UINT32 queue_id, 
-                                      ZXIC_UINT32 sdt_no, 
-                                      ZXIC_UINT32 entry_num, 
-                                      DPP_DTB_ACL_ENTRY_INFO_T *p_acl_entry_arr,
-                                      ZXIC_UINT32 *element_id
-                                      )
+ * @param   dev_id    设备号
+ * @param   queue_id  队列号
+ * @param   sdt_no    ACL表sdt表号
+ * @param   entry_num 下发的条目数
+ * @param   p_acl_entry_arr   待下发表项内容结构体数组指针
+ * @param   element_id    返回下表使用的元素id
+ * @return
+ * @remark  无 是否是有一个写不成功就返回，还是继续进行下一个条目并记录错误的条目
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_acl_dma_insert(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								  ZXIC_UINT32 sdt_no, ZXIC_UINT32 entry_num,
+								  DPP_DTB_ACL_ENTRY_INFO_T *p_acl_entry_arr,
+								  ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 as_enable;
-    ZXIC_UINT32 etcam_as_mode;
-    ZXIC_UINT32 entry_num_max = 0;
-    ZXIC_UINT32 entry_cycle = 0;
-    ZXIC_UINT32 entry_remains = 0;
-    ZXIC_UINT32 i = 0;
-    DPP_DTB_ACL_ENTRY_INFO_T *p_entry = NULL;
-
-    DPP_SDTTBL_ETCAM_T sdt_etcam_info = {0};  /*SDT内容*/
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get");
-
-    as_enable = sdt_etcam_info.as_en;
-    etcam_as_mode = sdt_etcam_info.as_rsp_mode;
-
-    if(!as_enable)
-    {
-        entry_num_max = 0x55;
-    }else 
-    {
-        if(etcam_as_mode == ERAM128_TBL_128b)
-        {
-            entry_num_max = 0x49;
-        }else
-        {
-            entry_num_max = 0x4e;
-        }
-    }
-
-    entry_cycle = entry_num / entry_num_max;
-    entry_remains = entry_num % entry_num_max;
-
-    for(i = 0; i < entry_cycle; ++i)
-    {
-        p_entry = p_acl_entry_arr + entry_num_max * i;
-        rc = dpp_dtb_acl_dma_insert_cycle(dev,
-                                     queue_id,
-                                     sdt_no,
-                                     entry_num_max,
-                                     p_entry,
-                                     element_id);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_acl_dma_insert_cycle");
-
-        ZXIC_COMM_TRACE_INFO("dpp_dtb_acl_dma_insert_cycle[%d]: element_id = %d\n", i, *element_id);
-    }
-
-    if(entry_remains)
-    {
-        p_entry = p_acl_entry_arr + entry_num_max * entry_cycle;
-        rc = dpp_dtb_acl_dma_insert_cycle(dev,
-                                     queue_id,
-                                     sdt_no,
-                                     entry_remains,
-                                     p_entry,
-                                     element_id);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_acl_dma_insert_cycle");
-
-        ZXIC_COMM_TRACE_INFO("dpp_dtb_acl_dma_insert_cycle: element_id = %d\n", *element_id);
-    }
-
-    return DPP_OK;   
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 as_enable;
+	ZXIC_UINT32 etcam_as_mode;
+	ZXIC_UINT32 entry_num_max = 0;
+	ZXIC_UINT32 entry_cycle = 0;
+	ZXIC_UINT32 entry_remains = 0;
+	ZXIC_UINT32 i = 0;
+	DPP_DTB_ACL_ENTRY_INFO_T *p_entry = NULL;
+
+	DPP_SDTTBL_ETCAM_T sdt_etcam_info = { 0 }; /*SDT内容*/
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get");
+
+	as_enable = sdt_etcam_info.as_en;
+	etcam_as_mode = sdt_etcam_info.as_rsp_mode;
+
+	if (!as_enable) {
+		entry_num_max = 0x55;
+	} else {
+		if (etcam_as_mode == ERAM128_TBL_128b) {
+			entry_num_max = 0x49;
+		} else {
+			entry_num_max = 0x4e;
+		}
+	}
+
+	entry_cycle = entry_num / entry_num_max;
+	entry_remains = entry_num % entry_num_max;
+
+	for (i = 0; i < entry_cycle; ++i) {
+		p_entry = p_acl_entry_arr + entry_num_max * i;
+		rc = dpp_dtb_acl_dma_insert_cycle(dev, queue_id, sdt_no, entry_num_max,
+										  p_entry, element_id);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_acl_dma_insert_cycle");
+
+		ZXIC_COMM_TRACE_INFO(
+				"dpp_dtb_acl_dma_insert_cycle[%d]: element_id = %d\n", i,
+				*element_id);
+	}
+
+	if (entry_remains) {
+		p_entry = p_acl_entry_arr + entry_num_max * entry_cycle;
+		rc = dpp_dtb_acl_dma_insert_cycle(dev, queue_id, sdt_no, entry_remains,
+										  p_entry, element_id);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_acl_dma_insert_cycle");
+
+		ZXIC_COMM_TRACE_INFO("dpp_dtb_acl_dma_insert_cycle: element_id = %d\n",
+							 *element_id);
+	}
+
+	return DPP_OK;
 }
 
 #endif
@@ -3384,724 +3136,719 @@ DPP_STATUS dpp_dtb_acl_dma_insert(DPP_DEV_T *dev,
 #if ZXIC_REAL("DTB DUMP BASE")
 
 /** smmu0 组装dump描述符函数
-* @param   dev_id         设备号
-* @param   base_addr      smmu0空间基地址，以128bit为单位
-* @param   depth          dump的深度以128bit为单位
-* @param   addr_high32    dump缓存地址高32bit
-* @param   addr_low32     dump缓存地址低32bit
-* @param   p_dump_info    dump描述符指针（已分配好空间128bit）
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_smmu0_dump_info_write(DPP_DEV_T *dev,  
-                                      ZXIC_UINT32 base_addr, 
-                                      ZXIC_UINT32 depth,
-                                      ZXIC_UINT32 addr_high32,
-                                      ZXIC_UINT32 addr_low32,
-                                      ZXIC_UINT32 *p_dump_info)
+ * @param   dev_id         设备号
+ * @param   base_addr      smmu0空间基地址，以128bit为单位
+ * @param   depth          dump的深度以128bit为单位
+ * @param   addr_high32    dump缓存地址高32bit
+ * @param   addr_low32     dump缓存地址低32bit
+ * @param   p_dump_info    dump描述符指针（已分配好空间128bit）
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_smmu0_dump_info_write(DPP_DEV_T *dev, ZXIC_UINT32 base_addr,
+										 ZXIC_UINT32 depth,
+										 ZXIC_UINT32 addr_high32,
+										 ZXIC_UINT32 addr_low32,
+										 ZXIC_UINT32 *p_dump_info)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32  i = 0;
-
-    DPP_DTB_ERAM_DUMP_FORM_T dtb_eram_dump_form_info = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_dump_info); 
-
-    //组装dump描述符
-    dtb_eram_dump_form_info.valid = DTB_TABLE_VALID;
-    dtb_eram_dump_form_info.up_type = DTB_DUMP_MODE_ERAM;
-    dtb_eram_dump_form_info.base_addr = base_addr;
-    dtb_eram_dump_form_info.tb_depth = depth;
-    dtb_eram_dump_form_info.tb_dst_addr_h = addr_high32;
-    dtb_eram_dump_form_info.tb_dst_addr_l = addr_low32;
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dpp_dtb_smmu0_dump_info_write: \n");
-        ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_eram_dump_form_info.valid);
-        ZXIC_COMM_DBGCNT32_PRINT("up_type", dtb_eram_dump_form_info.up_type);
-        ZXIC_COMM_DBGCNT32_PRINT("base_addr", dtb_eram_dump_form_info.base_addr);
-        ZXIC_COMM_DBGCNT32_PRINT("tb_depth",  dtb_eram_dump_form_info.tb_depth);
-        ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_h", dtb_eram_dump_form_info.tb_dst_addr_h);
-        ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_l", dtb_eram_dump_form_info.tb_dst_addr_l); 
-    }
-
-    /*组装dump描述符*/
-    rc = dpp_dtb_write_dump_cmd(DEV_ID(dev), DTB_DUMP_ERAM, &dtb_eram_dump_form_info, p_dump_info);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_cmd");
-
-    //打印出cmd buff中内容128bit
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dump type: %d\n", DTB_DUMP_MODE_ERAM);
-        ZXIC_COMM_PRINT("cmd: ");
-        for(i = 0; i < 4; i++)
-        {
-            ZXIC_COMM_PRINT("0x%08x  ", ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(p_dump_info + i))));//转换成大端显示
-        }
-        ZXIC_COMM_PRINT("\n");
-    }
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+
+	DPP_DTB_ERAM_DUMP_FORM_T dtb_eram_dump_form_info = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_dump_info);
+
+	//组装dump描述符
+	dtb_eram_dump_form_info.valid = DTB_TABLE_VALID;
+	dtb_eram_dump_form_info.up_type = DTB_DUMP_MODE_ERAM;
+	dtb_eram_dump_form_info.base_addr = base_addr;
+	dtb_eram_dump_form_info.tb_depth = depth;
+	dtb_eram_dump_form_info.tb_dst_addr_h = addr_high32;
+	dtb_eram_dump_form_info.tb_dst_addr_l = addr_low32;
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dpp_dtb_smmu0_dump_info_write: \n");
+		ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_eram_dump_form_info.valid);
+		ZXIC_COMM_DBGCNT32_PRINT("up_type", dtb_eram_dump_form_info.up_type);
+		ZXIC_COMM_DBGCNT32_PRINT("base_addr",
+								 dtb_eram_dump_form_info.base_addr);
+		ZXIC_COMM_DBGCNT32_PRINT("tb_depth", dtb_eram_dump_form_info.tb_depth);
+		ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_h",
+								 dtb_eram_dump_form_info.tb_dst_addr_h);
+		ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_l",
+								 dtb_eram_dump_form_info.tb_dst_addr_l);
+	}
+
+	/*组装dump描述符*/
+	rc = dpp_dtb_write_dump_cmd(DEV_ID(dev), DTB_DUMP_ERAM,
+								&dtb_eram_dump_form_info, p_dump_info);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_cmd");
+
+	//打印出cmd buff中内容128bit
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dump type: %d\n", DTB_DUMP_MODE_ERAM);
+		ZXIC_COMM_PRINT("cmd: ");
+		for (i = 0; i < 4; i++) {
+			ZXIC_COMM_PRINT(
+					"0x%08x  ",
+					ZXIC_COMM_CONVERT32(*((
+							ZXIC_UINT32 *)(p_dump_info + i)))); //转换成大端显示
+		}
+		ZXIC_COMM_PRINT("\n");
+	}
+	return rc;
 }
 
 /** smmu1 组装dump描述符函数
-* @param   dev_id         设备号
-* @param   base_addr      dump基地址，以512it为单位
-* @param   depth          dump的深度以512bit为单位
-* @param   addr_high32    dump缓存地址高32bit
-* @param   addr_low32     dump缓存地址低32bit
-* @param   p_dump_info    dump描述符指针（已分配好空间128bit）
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_smmu1_dump_info_write(DPP_DEV_T *dev, 
-                                      ZXIC_UINT32 base_addr, 
-                                      ZXIC_UINT32 depth,
-                                      ZXIC_UINT32 addr_high32,
-                                      ZXIC_UINT32 addr_low32,
-                                      ZXIC_UINT32 *p_dump_info
-                                      )
+ * @param   dev_id         设备号
+ * @param   base_addr      dump基地址，以512it为单位
+ * @param   depth          dump的深度以512bit为单位
+ * @param   addr_high32    dump缓存地址高32bit
+ * @param   addr_low32     dump缓存地址低32bit
+ * @param   p_dump_info    dump描述符指针（已分配好空间128bit）
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_smmu1_dump_info_write(DPP_DEV_T *dev, ZXIC_UINT32 base_addr,
+										 ZXIC_UINT32 depth,
+										 ZXIC_UINT32 addr_high32,
+										 ZXIC_UINT32 addr_low32,
+										 ZXIC_UINT32 *p_dump_info)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32  i = 0;
-
-    DPP_DTB_DDR_DUMP_FORM_T dtb_ddr_dump_form_info = {0}; 
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_dump_info); 
-
-    //组装dump描述符
-    dtb_ddr_dump_form_info.valid = DTB_TABLE_VALID;
-    dtb_ddr_dump_form_info.up_type = DTB_DUMP_MODE_DDR;
-    dtb_ddr_dump_form_info.base_addr = base_addr;
-    dtb_ddr_dump_form_info.tb_depth = depth;
-    dtb_ddr_dump_form_info.tb_dst_addr_h = addr_high32;
-    dtb_ddr_dump_form_info.tb_dst_addr_l = addr_low32;
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dpp_dtb_smmu1_dump_info_write: \n");
-        ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_ddr_dump_form_info.valid);
-        ZXIC_COMM_DBGCNT32_PRINT("up_type", dtb_ddr_dump_form_info.up_type);
-        ZXIC_COMM_DBGCNT32_PRINT("base_addr", dtb_ddr_dump_form_info.base_addr);
-        ZXIC_COMM_DBGCNT32_PRINT("tb_depth",  dtb_ddr_dump_form_info.tb_depth);
-        ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_h", dtb_ddr_dump_form_info.tb_dst_addr_h);
-        ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_l", dtb_ddr_dump_form_info.tb_dst_addr_l); 
-    }
-
-    /*组装dump描述符*/
-    rc = dpp_dtb_write_dump_cmd(DEV_ID(dev), DTB_DUMP_DDR, &dtb_ddr_dump_form_info, p_dump_info);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_cmd");
-
-    //打印出cmd buff中内容128bit
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dump type: %d\n", DTB_DUMP_MODE_ERAM);
-        ZXIC_COMM_PRINT("cmd: ");
-        for(i = 0; i < 4; i++)
-        {
-            ZXIC_COMM_PRINT("0x%08x  ", ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(p_dump_info + i))));//转换成大端显示
-        }
-        ZXIC_COMM_PRINT("\n");
-    }
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+
+	DPP_DTB_DDR_DUMP_FORM_T dtb_ddr_dump_form_info = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_dump_info);
+
+	//组装dump描述符
+	dtb_ddr_dump_form_info.valid = DTB_TABLE_VALID;
+	dtb_ddr_dump_form_info.up_type = DTB_DUMP_MODE_DDR;
+	dtb_ddr_dump_form_info.base_addr = base_addr;
+	dtb_ddr_dump_form_info.tb_depth = depth;
+	dtb_ddr_dump_form_info.tb_dst_addr_h = addr_high32;
+	dtb_ddr_dump_form_info.tb_dst_addr_l = addr_low32;
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dpp_dtb_smmu1_dump_info_write: \n");
+		ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_ddr_dump_form_info.valid);
+		ZXIC_COMM_DBGCNT32_PRINT("up_type", dtb_ddr_dump_form_info.up_type);
+		ZXIC_COMM_DBGCNT32_PRINT("base_addr", dtb_ddr_dump_form_info.base_addr);
+		ZXIC_COMM_DBGCNT32_PRINT("tb_depth", dtb_ddr_dump_form_info.tb_depth);
+		ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_h",
+								 dtb_ddr_dump_form_info.tb_dst_addr_h);
+		ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_l",
+								 dtb_ddr_dump_form_info.tb_dst_addr_l);
+	}
+
+	/*组装dump描述符*/
+	rc = dpp_dtb_write_dump_cmd(DEV_ID(dev), DTB_DUMP_DDR,
+								&dtb_ddr_dump_form_info, p_dump_info);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_cmd");
+
+	//打印出cmd buff中内容128bit
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dump type: %d\n", DTB_DUMP_MODE_ERAM);
+		ZXIC_COMM_PRINT("cmd: ");
+		for (i = 0; i < 4; i++) {
+			ZXIC_COMM_PRINT(
+					"0x%08x  ",
+					ZXIC_COMM_CONVERT32(*((
+							ZXIC_UINT32 *)(p_dump_info + i)))); //转换成大端显示
+		}
+		ZXIC_COMM_PRINT("\n");
+	}
+
+	return rc;
 }
 
 /** zcam 组装dump描述符函数
-* @param   dev_id         设备号
-* @param   addr           zcam内部ram地址，包括掩码(512bit为单位)
-* @param   tb_width       dump数据的宽度 00:128bit 01:256bit 10:512bit
-* @param   depth          dump的深度以512bit为单位
-* @param   addr_high32    dump缓存地址高32bit
-* @param   addr_low32     dump缓存地址低32bit
-* @param   p_dump_info    dump描述符指针（已分配好空间128bit）
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_zcam_dump_info_write(DPP_DEV_T *dev, 
-                                      ZXIC_UINT32 addr, 
-                                      ZXIC_UINT32 tb_width,
-                                      ZXIC_UINT32 depth,
-                                      ZXIC_UINT32 addr_high32,
-                                      ZXIC_UINT32 addr_low32,
-                                      ZXIC_UINT32 *p_dump_info
-                                      )
+ * @param   dev_id         设备号
+ * @param   addr           zcam内部ram地址，包括掩码(512bit为单位)
+ * @param   tb_width       dump数据的宽度 00:128bit 01:256bit 10:512bit
+ * @param   depth          dump的深度以512bit为单位
+ * @param   addr_high32    dump缓存地址高32bit
+ * @param   addr_low32     dump缓存地址低32bit
+ * @param   p_dump_info    dump描述符指针（已分配好空间128bit）
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_zcam_dump_info_write(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+										ZXIC_UINT32 tb_width, ZXIC_UINT32 depth,
+										ZXIC_UINT32 addr_high32,
+										ZXIC_UINT32 addr_low32,
+										ZXIC_UINT32 *p_dump_info)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32  i = 0;
-
-    DPP_DTB_ZCAM_DUMP_FORM_T dtb_zcam_dump_form_info = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_dump_info); 
-
-    //组装dump描述符
-    dtb_zcam_dump_form_info.valid = DTB_TABLE_VALID;
-    dtb_zcam_dump_form_info.up_type = DTB_DUMP_MODE_ZCAM;
-    dtb_zcam_dump_form_info.tb_width = tb_width;
-    dtb_zcam_dump_form_info.sram_addr = addr & 0x1FF;//512bit为单位
-    dtb_zcam_dump_form_info.ram_reg_flag = (addr >> 16) & 0x1;
-    dtb_zcam_dump_form_info.z_reg_cell_id = (addr >> 9) & 0x3;
-    dtb_zcam_dump_form_info.zblock_id = (addr >> 11) & 0x7;
-    dtb_zcam_dump_form_info.zgroup_id = (addr >> 14) & 0x3;
-    dtb_zcam_dump_form_info.tb_depth = depth;
-    dtb_zcam_dump_form_info.tb_dst_addr_h = addr_high32;
-    dtb_zcam_dump_form_info.tb_dst_addr_l = addr_low32;
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dpp_dtb_zcam_dump_info_write: \n");
-        ZXIC_COMM_DBGCNT32_PRINT("addr", addr);
-        ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_zcam_dump_form_info.valid);
-        ZXIC_COMM_DBGCNT32_PRINT("up_type", dtb_zcam_dump_form_info.up_type);
-        ZXIC_COMM_DBGCNT32_PRINT("zgroup_id", dtb_zcam_dump_form_info.zgroup_id);
-        ZXIC_COMM_DBGCNT32_PRINT("zblock_id", dtb_zcam_dump_form_info.zblock_id);
-        ZXIC_COMM_DBGCNT32_PRINT("reg_sram_flag", dtb_zcam_dump_form_info.ram_reg_flag);
-        ZXIC_COMM_DBGCNT32_PRINT("zcell_id", dtb_zcam_dump_form_info.z_reg_cell_id);
-        ZXIC_COMM_DBGCNT32_PRINT("tb_width", dtb_zcam_dump_form_info.tb_width);
-        ZXIC_COMM_DBGCNT32_PRINT("sram_addr", dtb_zcam_dump_form_info.sram_addr);
-        ZXIC_COMM_DBGCNT32_PRINT("tb_depth", dtb_zcam_dump_form_info.tb_depth);
-        ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_h", dtb_zcam_dump_form_info.tb_dst_addr_h);
-        ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_l", dtb_zcam_dump_form_info.tb_dst_addr_l); 
-    }
-
-    //将描述符写入dump缓存中
-    rc = dpp_dtb_write_dump_cmd(DEV_ID(dev), DTB_DUMP_ZCAM, &dtb_zcam_dump_form_info, p_dump_info);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_cmd");
-
-    //打印出cmd buff中内容128bit
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dump type: %d\n", DTB_DUMP_MODE_ERAM);
-        ZXIC_COMM_PRINT("cmd: ");
-        for(i = 0; i < 4; i++)
-        {
-            ZXIC_COMM_PRINT("0x%08x  ", ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(p_dump_info + i))));//转换成大端显示
-        }
-        ZXIC_COMM_PRINT("\n");
-    }
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+
+	DPP_DTB_ZCAM_DUMP_FORM_T dtb_zcam_dump_form_info = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_dump_info);
+
+	//组装dump描述符
+	dtb_zcam_dump_form_info.valid = DTB_TABLE_VALID;
+	dtb_zcam_dump_form_info.up_type = DTB_DUMP_MODE_ZCAM;
+	dtb_zcam_dump_form_info.tb_width = tb_width;
+	dtb_zcam_dump_form_info.sram_addr = addr & 0x1FF; // 512bit为单位
+	dtb_zcam_dump_form_info.ram_reg_flag = (addr >> 16) & 0x1;
+	dtb_zcam_dump_form_info.z_reg_cell_id = (addr >> 9) & 0x3;
+	dtb_zcam_dump_form_info.zblock_id = (addr >> 11) & 0x7;
+	dtb_zcam_dump_form_info.zgroup_id = (addr >> 14) & 0x3;
+	dtb_zcam_dump_form_info.tb_depth = depth;
+	dtb_zcam_dump_form_info.tb_dst_addr_h = addr_high32;
+	dtb_zcam_dump_form_info.tb_dst_addr_l = addr_low32;
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dpp_dtb_zcam_dump_info_write: \n");
+		ZXIC_COMM_DBGCNT32_PRINT("addr", addr);
+		ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_zcam_dump_form_info.valid);
+		ZXIC_COMM_DBGCNT32_PRINT("up_type", dtb_zcam_dump_form_info.up_type);
+		ZXIC_COMM_DBGCNT32_PRINT("zgroup_id",
+								 dtb_zcam_dump_form_info.zgroup_id);
+		ZXIC_COMM_DBGCNT32_PRINT("zblock_id",
+								 dtb_zcam_dump_form_info.zblock_id);
+		ZXIC_COMM_DBGCNT32_PRINT("reg_sram_flag",
+								 dtb_zcam_dump_form_info.ram_reg_flag);
+		ZXIC_COMM_DBGCNT32_PRINT("zcell_id",
+								 dtb_zcam_dump_form_info.z_reg_cell_id);
+		ZXIC_COMM_DBGCNT32_PRINT("tb_width", dtb_zcam_dump_form_info.tb_width);
+		ZXIC_COMM_DBGCNT32_PRINT("sram_addr",
+								 dtb_zcam_dump_form_info.sram_addr);
+		ZXIC_COMM_DBGCNT32_PRINT("tb_depth", dtb_zcam_dump_form_info.tb_depth);
+		ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_h",
+								 dtb_zcam_dump_form_info.tb_dst_addr_h);
+		ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_l",
+								 dtb_zcam_dump_form_info.tb_dst_addr_l);
+	}
+
+	//将描述符写入dump缓存中
+	rc = dpp_dtb_write_dump_cmd(DEV_ID(dev), DTB_DUMP_ZCAM,
+								&dtb_zcam_dump_form_info, p_dump_info);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_cmd");
+
+	//打印出cmd buff中内容128bit
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dump type: %d\n", DTB_DUMP_MODE_ERAM);
+		ZXIC_COMM_PRINT("cmd: ");
+		for (i = 0; i < 4; i++) {
+			ZXIC_COMM_PRINT(
+					"0x%08x  ",
+					ZXIC_COMM_CONVERT32(*((
+							ZXIC_UINT32 *)(p_dump_info + i)))); //转换成大端显示
+		}
+		ZXIC_COMM_PRINT("\n");
+	}
+
+	return rc;
 }
 
 /** etcam 组装dump描述符函数
-* @param   dev_id         设备号
-* @param   p_etcam_dump_info      etcam dump内容信息
-* @param   addr_high32    dump缓存地址高32bit
-* @param   addr_low32     dump缓存地址低32bit
-* @param   p_dump_info    dump描述符指针（已分配好空间128bit）
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_etcam_dump_info_write(DPP_DEV_T *dev,  
-                                      ETCAM_DUMP_INFO_T *p_etcam_dump_info,
-                                      ZXIC_UINT32 addr_high32,
-                                      ZXIC_UINT32 addr_low32,
-                                      ZXIC_UINT32 *p_dump_info
-                                      )
+ * @param   dev_id         设备号
+ * @param   p_etcam_dump_info      etcam dump内容信息
+ * @param   addr_high32    dump缓存地址高32bit
+ * @param   addr_low32     dump缓存地址低32bit
+ * @param   p_dump_info    dump描述符指针（已分配好空间128bit）
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_etcam_dump_info_write(DPP_DEV_T *dev,
+										 ETCAM_DUMP_INFO_T *p_etcam_dump_info,
+										 ZXIC_UINT32 addr_high32,
+										 ZXIC_UINT32 addr_low32,
+										 ZXIC_UINT32 *p_dump_info)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32  i = 0;
-
-    DPP_DTB_ETCAM_DUMP_FORM_T dtb_etcam_dump_form_info = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_dump_info); 
-    ZXIC_COMM_CHECK_POINT(p_etcam_dump_info); 
-
-    //组装dump描述符
-    dtb_etcam_dump_form_info.valid = DTB_TABLE_VALID;
-    dtb_etcam_dump_form_info.up_type = DTB_DUMP_MODE_ETCAM;
-    dtb_etcam_dump_form_info.block_sel = p_etcam_dump_info->block_sel;
-    dtb_etcam_dump_form_info.addr = p_etcam_dump_info->addr;
-    dtb_etcam_dump_form_info.rd_mode = p_etcam_dump_info->rd_mode;
-    dtb_etcam_dump_form_info.data_or_mask = p_etcam_dump_info->data_or_mask;
-    dtb_etcam_dump_form_info.tb_depth = p_etcam_dump_info->tb_depth;
-    dtb_etcam_dump_form_info.tb_width = p_etcam_dump_info->tb_width;//00:80bit 01:160bit 10:320bit 11:640bit
-    dtb_etcam_dump_form_info.tb_dst_addr_h = addr_high32;
-    dtb_etcam_dump_form_info.tb_dst_addr_l = addr_low32;
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dpp_dtb_etcam_dump_info_write: \n");
-        ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_etcam_dump_form_info.valid);
-        ZXIC_COMM_DBGCNT32_PRINT("up_type", dtb_etcam_dump_form_info.up_type);
-        ZXIC_COMM_DBGCNT32_PRINT("block_sel", dtb_etcam_dump_form_info.block_sel);
-        ZXIC_COMM_DBGCNT32_PRINT("addr",  dtb_etcam_dump_form_info.addr);
-        ZXIC_COMM_DBGCNT32_PRINT("rd_mode", dtb_etcam_dump_form_info.rd_mode);
-        ZXIC_COMM_DBGCNT32_PRINT("data_or_mask", dtb_etcam_dump_form_info.data_or_mask);
-        ZXIC_COMM_DBGCNT32_PRINT("tb_depth", dtb_etcam_dump_form_info.tb_depth);
-        ZXIC_COMM_DBGCNT32_PRINT("tb_width",  dtb_etcam_dump_form_info.tb_width);
-        ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_h", dtb_etcam_dump_form_info.tb_dst_addr_h);
-        ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_l", dtb_etcam_dump_form_info.tb_dst_addr_l); 
-    }
-
-    //将描述符写入dump缓存中
-    rc = dpp_dtb_write_dump_cmd(DEV_ID(dev), DTB_DUMP_ETCAM, &dtb_etcam_dump_form_info, p_dump_info);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_cmd");
-
-    //打印出cmd buff中内容128bit
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dump type: %d\n", DTB_DUMP_MODE_ERAM);
-        ZXIC_COMM_PRINT("cmd: ");
-        for(i = 0; i < 4; i++)
-        {
-            ZXIC_COMM_PRINT("0x%08x  ", ZXIC_COMM_CONVERT32(*((ZXIC_UINT32 *)(p_dump_info + i))));//转换成大端显示
-        }
-        ZXIC_COMM_PRINT("\n");
-    }
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+
+	DPP_DTB_ETCAM_DUMP_FORM_T dtb_etcam_dump_form_info = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_dump_info);
+	ZXIC_COMM_CHECK_POINT(p_etcam_dump_info);
+
+	//组装dump描述符
+	dtb_etcam_dump_form_info.valid = DTB_TABLE_VALID;
+	dtb_etcam_dump_form_info.up_type = DTB_DUMP_MODE_ETCAM;
+	dtb_etcam_dump_form_info.block_sel = p_etcam_dump_info->block_sel;
+	dtb_etcam_dump_form_info.addr = p_etcam_dump_info->addr;
+	dtb_etcam_dump_form_info.rd_mode = p_etcam_dump_info->rd_mode;
+	dtb_etcam_dump_form_info.data_or_mask = p_etcam_dump_info->data_or_mask;
+	dtb_etcam_dump_form_info.tb_depth = p_etcam_dump_info->tb_depth;
+	dtb_etcam_dump_form_info.tb_width =
+			p_etcam_dump_info
+					->tb_width; // 00:80bit 01:160bit 10:320bit 11:640bit
+	dtb_etcam_dump_form_info.tb_dst_addr_h = addr_high32;
+	dtb_etcam_dump_form_info.tb_dst_addr_l = addr_low32;
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dpp_dtb_etcam_dump_info_write: \n");
+		ZXIC_COMM_DBGCNT32_PRINT("valid", dtb_etcam_dump_form_info.valid);
+		ZXIC_COMM_DBGCNT32_PRINT("up_type", dtb_etcam_dump_form_info.up_type);
+		ZXIC_COMM_DBGCNT32_PRINT("block_sel",
+								 dtb_etcam_dump_form_info.block_sel);
+		ZXIC_COMM_DBGCNT32_PRINT("addr", dtb_etcam_dump_form_info.addr);
+		ZXIC_COMM_DBGCNT32_PRINT("rd_mode", dtb_etcam_dump_form_info.rd_mode);
+		ZXIC_COMM_DBGCNT32_PRINT("data_or_mask",
+								 dtb_etcam_dump_form_info.data_or_mask);
+		ZXIC_COMM_DBGCNT32_PRINT("tb_depth", dtb_etcam_dump_form_info.tb_depth);
+		ZXIC_COMM_DBGCNT32_PRINT("tb_width", dtb_etcam_dump_form_info.tb_width);
+		ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_h",
+								 dtb_etcam_dump_form_info.tb_dst_addr_h);
+		ZXIC_COMM_DBGCNT32_PRINT("tb_dst_addr_l",
+								 dtb_etcam_dump_form_info.tb_dst_addr_l);
+	}
+
+	//将描述符写入dump缓存中
+	rc = dpp_dtb_write_dump_cmd(DEV_ID(dev), DTB_DUMP_ETCAM,
+								&dtb_etcam_dump_form_info, p_dump_info);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_cmd");
+
+	//打印出cmd buff中内容128bit
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dump type: %d\n", DTB_DUMP_MODE_ERAM);
+		ZXIC_COMM_PRINT("cmd: ");
+		for (i = 0; i < 4; i++) {
+			ZXIC_COMM_PRINT(
+					"0x%08x  ",
+					ZXIC_COMM_CONVERT32(*((
+							ZXIC_UINT32 *)(p_dump_info + i)))); //转换成大端显示
+		}
+		ZXIC_COMM_PRINT("\n");
+	}
+
+	return rc;
 }
 
 /** eram 生成dump entry，输入dump描述符，输出一个entry
-* @param   dev_id         设备号
-* @param   base_addr      smmu0空间基地址，以128bit为单位
-* @param   depth          dump的深度以128bit为单位
-* @param   addr_high32    dump缓存地址高32bit
-* @param   addr_low32     dump缓存地址低32bit
-* @param   p_entry        entry指针（已分配好cmd空间128bit,用来存放dump描述符）
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_smmu0_dump_entry(DPP_DEV_T *dev,  
-                                    ZXIC_UINT32 base_addr, 
-                                    ZXIC_UINT32 depth,
-                                    ZXIC_UINT32 addr_high32,
-                                    ZXIC_UINT32 addr_low32,
-                                    DPP_DTB_ENTRY_T *p_entry)
+ * @param   dev_id         设备号
+ * @param   base_addr      smmu0空间基地址，以128bit为单位
+ * @param   depth          dump的深度以128bit为单位
+ * @param   addr_high32    dump缓存地址高32bit
+ * @param   addr_low32     dump缓存地址低32bit
+ * @param   p_entry        entry指针（已分配好cmd空间128bit,用来存放dump描述符）
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_smmu0_dump_entry(DPP_DEV_T *dev, ZXIC_UINT32 base_addr,
+									ZXIC_UINT32 depth, ZXIC_UINT32 addr_high32,
+									ZXIC_UINT32 addr_low32,
+									DPP_DTB_ENTRY_T *p_entry)
 {
-    DPP_STATUS rc = DPP_OK;
+	DPP_STATUS rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_entry);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_entry);
 
-    rc = dpp_dtb_smmu0_dump_info_write(dev, 
-                                       base_addr, 
-                                       depth,
-                                       addr_high32,
-                                       addr_low32,
-                                       (ZXIC_UINT32 *)p_entry->cmd);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_dump_info_write");
-    p_entry->data_in_cmd_flag = 1;
+	rc = dpp_dtb_smmu0_dump_info_write(dev, base_addr, depth, addr_high32,
+									   addr_low32, (ZXIC_UINT32 *)p_entry->cmd);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_dump_info_write");
+	p_entry->data_in_cmd_flag = 1;
 
-    return rc;
+	return rc;
 }
 
 /** smmu1生成dump entry，输入dump描述符，输出一个entry
-* @param   dev_id         设备号
-* @param   base_addr      dump基地址，以128bit为单位
-* @param   depth          dump的深度以512bit为单位
-* @param   addr_high32    dump缓存地址高32bit
-* @param   addr_low32     dump缓存地址低32bit
-* @param   p_entry    entry指针（已分配好cmd空间128bit,用来存放dump描述符）
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_smmu1_dump_entry(DPP_DEV_T *dev, 
-                                    ZXIC_UINT32 base_addr, 
-                                    ZXIC_UINT32 depth,
-                                    ZXIC_UINT32 addr_high32,
-                                    ZXIC_UINT32 addr_low32,
-                                    DPP_DTB_ENTRY_T *p_entry)
+ * @param   dev_id         设备号
+ * @param   base_addr      dump基地址，以128bit为单位
+ * @param   depth          dump的深度以512bit为单位
+ * @param   addr_high32    dump缓存地址高32bit
+ * @param   addr_low32     dump缓存地址低32bit
+ * @param   p_entry    entry指针（已分配好cmd空间128bit,用来存放dump描述符）
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_smmu1_dump_entry(DPP_DEV_T *dev, ZXIC_UINT32 base_addr,
+									ZXIC_UINT32 depth, ZXIC_UINT32 addr_high32,
+									ZXIC_UINT32 addr_low32,
+									DPP_DTB_ENTRY_T *p_entry)
 {
-    DPP_STATUS rc = DPP_OK;
+	DPP_STATUS rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_entry);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_entry);
 
-    rc = dpp_dtb_smmu1_dump_info_write(dev, 
-                                       base_addr, 
-                                       depth,
-                                       addr_high32,
-                                       addr_low32,
-                                       (ZXIC_UINT32 *)p_entry->cmd);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_dump_info_write");
-    p_entry->data_in_cmd_flag = 1;
+	rc = dpp_dtb_smmu1_dump_info_write(dev, base_addr, depth, addr_high32,
+									   addr_low32, (ZXIC_UINT32 *)p_entry->cmd);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_dump_info_write");
+	p_entry->data_in_cmd_flag = 1;
 
-    return rc;
+	return rc;
 }
 
 /** zcam 组装dump描述符函数
-* @param   dev_id         设备号
-* @param   addr           zcam内部ram地址，包括掩码(512bit为单位)
-* @param   tb_width       dump数据的宽度 00:128bit 01:256bit 10:512bit
-* @param   depth          dump的深度以512bit为单位
-* @param   addr_high32    dump缓存地址高32bit
-* @param   addr_low32     dump缓存地址低32bit
-* @param   p_entry    entry指针（已分配好cmd空间128bit,用来存放dump描述符）
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_zcam_dump_entry(DPP_DEV_T *dev, 
-                                   ZXIC_UINT32 addr, 
-                                   ZXIC_UINT32 tb_width,
-                                   ZXIC_UINT32 depth,
-                                   ZXIC_UINT32 addr_high32,
-                                   ZXIC_UINT32 addr_low32,
-                                   DPP_DTB_ENTRY_T *p_entry)
+ * @param   dev_id         设备号
+ * @param   addr           zcam内部ram地址，包括掩码(512bit为单位)
+ * @param   tb_width       dump数据的宽度 00:128bit 01:256bit 10:512bit
+ * @param   depth          dump的深度以512bit为单位
+ * @param   addr_high32    dump缓存地址高32bit
+ * @param   addr_low32     dump缓存地址低32bit
+ * @param   p_entry    entry指针（已分配好cmd空间128bit,用来存放dump描述符）
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_zcam_dump_entry(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+								   ZXIC_UINT32 tb_width, ZXIC_UINT32 depth,
+								   ZXIC_UINT32 addr_high32,
+								   ZXIC_UINT32 addr_low32,
+								   DPP_DTB_ENTRY_T *p_entry)
 {
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_entry);
-
-    rc = dpp_dtb_zcam_dump_info_write(dev, 
-                                      addr,
-                                      tb_width, 
-                                      depth,
-                                      addr_high32,
-                                      addr_low32,
-                                      (ZXIC_UINT32 *)p_entry->cmd);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_zcam_dump_info_write");
-    p_entry->data_in_cmd_flag = 1;
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_entry);
+
+	rc = dpp_dtb_zcam_dump_info_write(dev, addr, tb_width, depth, addr_high32,
+									  addr_low32, (ZXIC_UINT32 *)p_entry->cmd);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_zcam_dump_info_write");
+	p_entry->data_in_cmd_flag = 1;
+
+	return rc;
 }
 
 /** etcam 生成dump entry，输入dump描述符，输出一个entry
-* @param   dev_id         设备号
-* @param   p_etcam_dump_info      etcam dump内容信息
-* @param   addr_high32    dump缓存地址高32bit
-* @param   addr_low32     dump缓存地址低32bit
-* @param   p_entry        entry指针（已分配好cmd空间128bit,用来存放dump描述符）
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_etcam_dump_entry(DPP_DEV_T *dev,   
-                                    ETCAM_DUMP_INFO_T *p_etcam_dump_info,
-                                    ZXIC_UINT32 addr_high32,
-                                    ZXIC_UINT32 addr_low32,
-                                    DPP_DTB_ENTRY_T *p_entry)
+ * @param   dev_id         设备号
+ * @param   p_etcam_dump_info      etcam dump内容信息
+ * @param   addr_high32    dump缓存地址高32bit
+ * @param   addr_low32     dump缓存地址低32bit
+ * @param   p_entry        entry指针（已分配好cmd空间128bit,用来存放dump描述符）
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_etcam_dump_entry(DPP_DEV_T *dev,
+									ETCAM_DUMP_INFO_T *p_etcam_dump_info,
+									ZXIC_UINT32 addr_high32,
+									ZXIC_UINT32 addr_low32,
+									DPP_DTB_ENTRY_T *p_entry)
 {
-    DPP_STATUS rc = DPP_OK;
+	DPP_STATUS rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_entry);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_entry);
 
-    rc = dpp_dtb_etcam_dump_info_write(dev,
-                                       p_etcam_dump_info,
-                                       addr_high32,
-                                       addr_low32,
-                                       (ZXIC_UINT32 *)p_entry->cmd);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_etcam_dump_info_write");
-    p_entry->data_in_cmd_flag = 1;
+	rc = dpp_dtb_etcam_dump_info_write(dev, p_etcam_dump_info, addr_high32,
+									   addr_low32, (ZXIC_UINT32 *)p_entry->cmd);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_etcam_dump_info_write");
+	p_entry->data_in_cmd_flag = 1;
 
-    return rc;
+	return rc;
 }
 
-
-/** 下发dump描述符，dump出数据 
-* @param   dev_id       设备号
-* @param   queue_id     队列号
-* @param   queue_element_id   元素编号
-* @param   p_dump_info  dump描述符
-* @param   data_len     dump出数据的长度(32bit为单位)
-* @param   desc_len     dump描述符的长度(32bit为单位)
-* @param   p_dump_data  dump出的数据缓存
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_write_dump_desc_info(DPP_DEV_T *dev,
-                                ZXIC_UINT32 queue_id, 
-                                ZXIC_UINT32 queue_element_id,
-                                ZXIC_UINT32 *p_dump_info,
-                                ZXIC_UINT32 data_len,
-                                ZXIC_UINT32 desc_len,
-                                ZXIC_UINT32 *p_dump_data )
+/** 下发dump描述符，dump出数据
+ * @param   dev_id       设备号
+ * @param   queue_id     队列号
+ * @param   queue_element_id   元素编号
+ * @param   p_dump_info  dump描述符
+ * @param   data_len     dump出数据的长度(32bit为单位)
+ * @param   desc_len     dump描述符的长度(32bit为单位)
+ * @param   p_dump_data  dump出的数据缓存
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_write_dump_desc_info(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+										ZXIC_UINT32 queue_element_id,
+										ZXIC_UINT32 *p_dump_info,
+										ZXIC_UINT32 data_len,
+										ZXIC_UINT32 desc_len,
+										ZXIC_UINT32 *p_dump_data)
 {
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 dtb_interrupt_status = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    /*获取中断配置*/
-    dtb_interrupt_status = dpp_dtb_interrupt_status_get();
-    
-    /*下发dump描述符*/
-    rc = dpp_dtb_tab_up_info_set(dev,
-                                    queue_id,
-                                    queue_element_id,
-                                    dtb_interrupt_status,
-                                    data_len,
-                                    desc_len,
-                                    p_dump_info);
-    if(DPP_OK != rc)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "the queue %d element id %d dump info set failed!", queue_id, queue_element_id);
-        dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE, queue_element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_tab_up_info_set");
-    }
-
-    /*查询是否dump完成，完成后取出数据 需要在dpp_dtb.c中补充查询一个元素ack是否成功函数*/
-   if(!dtb_interrupt_status)
-   {
-
-        rc = dpp_dtb_tab_up_success_status_check(dev, queue_id, queue_element_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_tab_up_success_status_check");
- 
-        /*取出数据*/
-        rc = dpp_dtb_tab_up_data_get(dev, queue_id, queue_element_id, data_len, p_dump_data);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_tab_up_data_get");
-   }else
-   {
-        rc = dpp_dtb_tab_up_success_status_check(dev, queue_id, queue_element_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_tab_up_success_status_check");
-
-        /*取出数据*/
-        rc = dpp_dtb_tab_up_data_get(dev, queue_id, queue_element_id, data_len, p_dump_data);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_tab_up_data_get");
-        /*清中断*/
-        dpp_dtb_finish_interrupt_event_state_clr(dev, queue_id);
-   }
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 dtb_interrupt_status = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	/*获取中断配置*/
+	dtb_interrupt_status = dpp_dtb_interrupt_status_get();
+
+	/*下发dump描述符*/
+	rc = dpp_dtb_tab_up_info_set(dev, queue_id, queue_element_id,
+								 dtb_interrupt_status, data_len, desc_len,
+								 p_dump_info);
+	if (DPP_OK != rc) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev), "the queue %d element id %d dump info set failed!",
+				queue_id, queue_element_id);
+		dpp_dtb_item_ack_wr(dev, queue_id, DPP_DTB_DIR_UP_TYPE,
+							queue_element_id, 0, DPP_DTB_TAB_ACK_UNUSED_MASK);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_dtb_tab_up_info_set");
+	}
+
+	/*查询是否dump完成，完成后取出数据 需要在dpp_dtb.c中补充查询一个元素ack是否成功函数*/
+	if (!dtb_interrupt_status) {
+		rc = dpp_dtb_tab_up_success_status_check(dev, queue_id,
+												 queue_element_id);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_dtb_tab_up_success_status_check");
+
+		/*取出数据*/
+		rc = dpp_dtb_tab_up_data_get(dev, queue_id, queue_element_id, data_len,
+									 p_dump_data);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_dtb_tab_up_data_get");
+	} else {
+		rc = dpp_dtb_tab_up_success_status_check(dev, queue_id,
+												 queue_element_id);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_dtb_tab_up_success_status_check");
+
+		/*取出数据*/
+		rc = dpp_dtb_tab_up_data_get(dev, queue_id, queue_element_id, data_len,
+									 p_dump_data);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_dtb_tab_up_data_get");
+		/*清中断*/
+		dpp_dtb_finish_interrupt_event_state_clr(dev, queue_id);
+	}
+
+	return DPP_OK;
 }
 
-
 /** smmu0 dump 只写一个dump描述符的接口
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   base_addr 要dump的内容的基地址，以128bit为单位
-* @param   depth     dump的深度以128bit为单位
-* @param   p_data    dump出数据缓存(128bit * depth)
-* @param   element_id   返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_se_smmu0_dma_dump(DPP_DEV_T *dev, 
-                                      ZXIC_UINT32 queue_id, 
-                                      ZXIC_UINT32 base_addr, 
-                                      ZXIC_UINT32 depth,
-                                      ZXIC_UINT32 *p_data,
-                                      ZXIC_UINT32 *element_id
-                                      )
+ * @param   dev_id    设备号
+ * @param   queue_id  队列号
+ * @param   base_addr 要dump的内容的基地址，以128bit为单位
+ * @param   depth     dump的深度以128bit为单位
+ * @param   p_data    dump出数据缓存(128bit * depth)
+ * @param   element_id   返回下表使用的元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_se_smmu0_dma_dump(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									 ZXIC_UINT32 base_addr, ZXIC_UINT32 depth,
+									 ZXIC_UINT32 *p_data,
+									 ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 dump_dst_phy_haddr = 0;
-    ZXIC_UINT32 dump_dst_phy_laddr = 0;
-    ZXIC_UINT32 queue_item_index = 0;
-    ZXIC_UINT32 data_len = 0;
-    ZXIC_UINT32 desc_len = 0;
-
-    ZXIC_UINT8 form_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_LOWER(depth, 1);
-
-    /*获取队列中可用的元素编号*/
-    rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &queue_item_index);
-    if(rc != DPP_OK)
-    {
-        ZXIC_COMM_TRACE_ERROR("dpp_dtb_tab_up_free_item_get failed!\n");
-        return DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY;
-    }
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dump smmu0:queue %d,item_index: %d\n",queue_id, queue_item_index);
-    }
-
-    *element_id = queue_item_index;//保存获取的item_index
-    
-    /*获取地址*/
-    rc = dpp_dtb_tab_up_item_addr_get(dev, queue_id, queue_item_index, &dump_dst_phy_haddr, &dump_dst_phy_laddr);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get");
-    
-    rc = dpp_dtb_smmu0_dump_info_write(dev,
-                                       base_addr,
-                                       depth,
-                                       dump_dst_phy_haddr,
-                                       dump_dst_phy_laddr,
-                                       (ZXIC_UINT32 *)form_buff);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_dump_info_write");
-    
-    /*组装下表命令格式*/
-
-    data_len = depth * 128 / 32;
-    desc_len = DTB_LEN_POS_SETP / 4;
-
-    rc = dpp_dtb_write_dump_desc_info(dev, queue_id, queue_item_index, (ZXIC_UINT32 *)form_buff, data_len, desc_len, p_data);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_desc_info");
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 dump_dst_phy_haddr = 0;
+	ZXIC_UINT32 dump_dst_phy_laddr = 0;
+	ZXIC_UINT32 queue_item_index = 0;
+	ZXIC_UINT32 data_len = 0;
+	ZXIC_UINT32 desc_len = 0;
+
+	ZXIC_UINT8 form_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_LOWER(depth, 1);
+
+	/*获取队列中可用的元素编号*/
+	rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &queue_item_index);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_free_item_get");
+
+	ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev),
+							  "table up item queue_element_id is: %d.\n",
+							  queue_item_index);
+	if (rc != DPP_OK) {
+		return DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY;
+	}
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dump smmu0:queue %d,item_index: %d\n", queue_id,
+						queue_item_index);
+	}
+
+	*element_id = queue_item_index; //保存获取的item_index
+
+	/*获取地址*/
+	rc = dpp_dtb_tab_up_item_addr_get(dev, queue_id, queue_item_index,
+									  &dump_dst_phy_haddr, &dump_dst_phy_laddr);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get");
+
+	rc = dpp_dtb_smmu0_dump_info_write(dev, base_addr, depth,
+									   dump_dst_phy_haddr, dump_dst_phy_laddr,
+									   (ZXIC_UINT32 *)form_buff);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_dump_info_write");
+
+	/*组装下表命令格式*/
+
+	data_len = depth * 128 / 32;
+	desc_len = DTB_LEN_POS_SETP / 4;
+
+	rc = dpp_dtb_write_dump_desc_info(dev, queue_id, queue_item_index,
+									  (ZXIC_UINT32 *)form_buff, data_len,
+									  desc_len, p_data);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_desc_info");
+
+	return DPP_OK;
 }
 
 /** dtb dump DDR表项内容 返回内容以512bit为单位
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   base_addr dump基地址，以512bit为单位
-* @param   depth     dump的深度以512bit为单位
-* @param   p_data    dump出数据缓存(512bit * depth)
-* @param   element_id   返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_se_smmu1_dma_dump(DPP_DEV_T *dev,  
-                                      ZXIC_UINT32 queue_id, 
-                                      ZXIC_UINT32 base_addr, 
-                                      ZXIC_UINT32 depth,
-                                      ZXIC_UINT32 *p_data,
-                                      ZXIC_UINT32 *element_id)
+ * @param   dev_id    设备号
+ * @param   queue_id  队列号
+ * @param   base_addr dump基地址，以512bit为单位
+ * @param   depth     dump的深度以512bit为单位
+ * @param   p_data    dump出数据缓存(512bit * depth)
+ * @param   element_id   返回下表使用的元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_se_smmu1_dma_dump(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									 ZXIC_UINT32 base_addr, ZXIC_UINT32 depth,
+									 ZXIC_UINT32 *p_data,
+									 ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 dump_dst_phy_haddr = 0;
-    ZXIC_UINT32 dump_dst_phy_laddr = 0;
-
-    ZXIC_UINT32 queue_item_index = 0;
-    ZXIC_UINT32 data_len = 0;
-    ZXIC_UINT32 desc_len = 0;
-
-    ZXIC_UINT8 form_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX_LOWER(depth, 1);
-
-    /*获取队列元素*/
-    rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &queue_item_index);
-    if(rc != DPP_OK)
-    {
-        ZXIC_COMM_TRACE_ERROR("dpp_dtb_tab_up_free_item_get failed!\n");
-        return DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY;
-    }
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dump smmu1:queue %d,item_index: %d\n",queue_id, queue_item_index);
-    }
-
-    *element_id = queue_item_index;//保存获取的item_index
-    
-    /*获取dump dma phy地址*/
-    rc = dpp_dtb_tab_up_item_addr_get(dev, queue_id, queue_item_index, &dump_dst_phy_haddr, &dump_dst_phy_laddr);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get");
-
-    rc = dpp_dtb_smmu1_dump_info_write(dev,
-                                       base_addr,
-                                       depth,
-                                       dump_dst_phy_haddr,
-                                       dump_dst_phy_laddr,
-                                       (ZXIC_UINT32 *)form_buff);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_dump_info_write"); 
-
-    /*组装下表命令格式*/
-    data_len = depth * 512 / 32;//要提取的数据长度，以32bit为单位
-    desc_len = DTB_LEN_POS_SETP / 4;//描述符长度，以32bit为单位
-
-    rc = dpp_dtb_write_dump_desc_info(dev, queue_id, queue_item_index, (ZXIC_UINT32 *)form_buff, data_len, desc_len, p_data);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_desc_info");
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 dump_dst_phy_haddr = 0;
+	ZXIC_UINT32 dump_dst_phy_laddr = 0;
+
+	ZXIC_UINT32 queue_item_index = 0;
+	ZXIC_UINT32 data_len = 0;
+	ZXIC_UINT32 desc_len = 0;
+
+	ZXIC_UINT8 form_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX_LOWER(depth, 1);
+
+	/*获取队列元素*/
+	rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &queue_item_index);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_free_item_get");
+	ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev),
+							  "table up item queue_element_id is: %d.\n",
+							  queue_item_index);
+	if (rc != DPP_OK) {
+		return DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY;
+	}
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dump smmu1:queue %d,item_index: %d\n", queue_id,
+						queue_item_index);
+	}
+
+	*element_id = queue_item_index; //保存获取的item_index
+
+	/*获取dump dma phy地址*/
+	rc = dpp_dtb_tab_up_item_addr_get(dev, queue_id, queue_item_index,
+									  &dump_dst_phy_haddr, &dump_dst_phy_laddr);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get");
+
+	rc = dpp_dtb_smmu1_dump_info_write(dev, base_addr, depth,
+									   dump_dst_phy_haddr, dump_dst_phy_laddr,
+									   (ZXIC_UINT32 *)form_buff);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_dump_info_write");
+
+	/*组装下表命令格式*/
+	data_len = depth * 512 / 32; //要提取的数据长度，以32bit为单位
+	desc_len = DTB_LEN_POS_SETP / 4; //描述符长度，以32bit为单位
+
+	rc = dpp_dtb_write_dump_desc_info(dev, queue_id, queue_item_index,
+									  (ZXIC_UINT32 *)form_buff, data_len,
+									  desc_len, p_data);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_desc_info");
+
+	return DPP_OK;
 }
 
 /** dtb dump zcam表项内容
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   addr      zcam内部ram地址，包括掩码
-* @param   tb_width  dump数据的宽度
-* @param   depth     dump的深度以tb_width为单位
-* @param   p_data    dump出数据缓存(tb_width * depth)
-* @param   element_id   返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_se_zcam_dma_dump(DPP_DEV_T *dev, 
-                                      ZXIC_UINT32 queue_id, 
-                                      ZXIC_UINT32 addr, 
-                                      ZXIC_UINT32 tb_width,
-                                      ZXIC_UINT32 depth,
-                                      ZXIC_UINT32 *p_data,
-                                      ZXIC_UINT32 *element_id)
+ * @param   dev_id    设备号
+ * @param   queue_id  队列号
+ * @param   addr      zcam内部ram地址，包括掩码
+ * @param   tb_width  dump数据的宽度
+ * @param   depth     dump的深度以tb_width为单位
+ * @param   p_data    dump出数据缓存(tb_width * depth)
+ * @param   element_id   返回下表使用的元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_se_zcam_dma_dump(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									ZXIC_UINT32 addr, ZXIC_UINT32 tb_width,
+									ZXIC_UINT32 depth, ZXIC_UINT32 *p_data,
+									ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 dump_dst_phy_haddr = 0;
-    ZXIC_UINT32 dump_dst_phy_laddr = 0;
-
-    ZXIC_UINT32 queue_item_index = 0;
-    ZXIC_UINT32 data_len = 0;
-    ZXIC_UINT32 desc_len = 0;
-    ZXIC_UINT32 tb_width_len = 0;
-
-    ZXIC_UINT8 form_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), tb_width, DTB_DUMP_ZCAM_128b, DTB_DUMP_ZCAM_RSV - 1);
-    ZXIC_COMM_CHECK_INDEX_LOWER(depth, 1);
-
-    /*获取队列元素*/
-    rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &queue_item_index);
-    if(rc != DPP_OK)
-    {
-        ZXIC_COMM_TRACE_ERROR("dpp_dtb_tab_up_free_item_get failed!\n");
-        return DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY;
-    }
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dump smmu0:queue %d,item_index: %d\n",queue_id, queue_item_index);
-    }
-
-    *element_id = queue_item_index;//保存获取的item_index
-    
-    /*获取dump dma phy地址*/
-    rc = dpp_dtb_tab_up_item_addr_get(dev, queue_id, queue_item_index, &dump_dst_phy_haddr, &dump_dst_phy_laddr);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get");
-
-    rc = dpp_dtb_zcam_dump_info_write(dev,
-                                      addr,
-                                      tb_width,
-                                      depth,
-                                      dump_dst_phy_haddr,
-                                      dump_dst_phy_laddr,
-                                      (ZXIC_UINT32 *)form_buff);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_zcam_dump_info_write");
-
-    /*组装下表命令格式*/
-    tb_width_len = DTB_LEN_POS_SETP << tb_width;
-    data_len = depth * tb_width_len / 4;//要提取的数据长度，以32bit为单位
-    desc_len = DTB_LEN_POS_SETP / 4;//描述符长度，以32bit为单位
-
-    rc = dpp_dtb_write_dump_desc_info(dev, queue_id, queue_item_index, (ZXIC_UINT32 *)form_buff, data_len, desc_len, p_data);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_desc_info");
-
-    return DPP_OK;
-
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 dump_dst_phy_haddr = 0;
+	ZXIC_UINT32 dump_dst_phy_laddr = 0;
+
+	ZXIC_UINT32 queue_item_index = 0;
+	ZXIC_UINT32 data_len = 0;
+	ZXIC_UINT32 desc_len = 0;
+	ZXIC_UINT32 tb_width_len = 0;
+
+	ZXIC_UINT8 form_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), tb_width, DTB_DUMP_ZCAM_128b,
+							  DTB_DUMP_ZCAM_RSV - 1);
+	ZXIC_COMM_CHECK_INDEX_LOWER(depth, 1);
+
+	/*获取队列元素*/
+	rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &queue_item_index);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_free_item_get");
+	ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev),
+							  "table up item queue_element_id is: %d.\n",
+							  queue_item_index);
+	if (rc != DPP_OK) {
+		return DPP_RC_DTB_QUEUE_ITEM_SW_EMPTY;
+	}
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dump smmu0:queue %d,item_index: %d\n", queue_id,
+						queue_item_index);
+	}
+
+	*element_id = queue_item_index; //保存获取的item_index
+
+	/*获取dump dma phy地址*/
+	rc = dpp_dtb_tab_up_item_addr_get(dev, queue_id, queue_item_index,
+									  &dump_dst_phy_haddr, &dump_dst_phy_laddr);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get");
+
+	rc = dpp_dtb_zcam_dump_info_write(dev, addr, tb_width, depth,
+									  dump_dst_phy_haddr, dump_dst_phy_laddr,
+									  (ZXIC_UINT32 *)form_buff);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_zcam_dump_info_write");
+
+	/*组装下表命令格式*/
+	tb_width_len = DTB_LEN_POS_SETP << tb_width;
+	data_len = depth * tb_width_len / 4; //要提取的数据长度，以32bit为单位
+	desc_len = DTB_LEN_POS_SETP / 4; //描述符长度，以32bit为单位
+
+	rc = dpp_dtb_write_dump_desc_info(dev, queue_id, queue_item_index,
+									  (ZXIC_UINT32 *)form_buff, data_len,
+									  desc_len, p_data);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_desc_info");
+
+	return DPP_OK;
 }
 
 #endif
@@ -4109,2314 +3856,2233 @@ DPP_STATUS dpp_dtb_se_zcam_dma_dump(DPP_DEV_T *dev,
 #if ZXIC_REAL("DTB GET")
 /***********************************************************/
 /** 配置数据获取模式
-* @param   srh_mode   0:软件获取  1:硬件获取
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
+ * @param   srh_mode   0:软件获取  1:硬件获取
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/02
+ ************************************************************/
 ZXIC_VOID dpp_dtb_srh_mode_set(ZXIC_UINT32 srh_mode)
 {
-    g_dtb_srh_mode = srh_mode;
+	g_dtb_srh_mode = srh_mode;
 }
 
 /***********************************************************/
 /** 获取查找方式
-* @param   
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
+ * @param
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/02
+ ************************************************************/
 ZXIC_UINT32 dpp_dtb_srh_mode_get(ZXIC_VOID)
 {
-    return g_dtb_srh_mode;
+	return g_dtb_srh_mode;
 }
 
 /***********************************************************/
 /** hash表项查找校验(软件获取数据)
-* @param   p_entry         入参：hash表项键值 出参：hash表项结果
-* @param   key_by_size     键值大小 
-* @param   rst_by_size     返回值大小
-* @param   p_item_info     512bit单元数据
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
+ * @param   p_entry         入参：hash表项键值 出参：hash表项结果
+ * @param   key_by_size     键值大小
+ * @param   rst_by_size     返回值大小
+ * @param   p_item_info     512bit单元数据
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/02
+ ************************************************************/
 DPP_STATUS dpp_dtb_hash_software_item_check(DPP_HASH_ENTRY *p_entry,
-                                        ZXIC_UINT32 key_by_size,
-                                        ZXIC_UINT32 rst_by_size,
-                                        SE_ITEM_CFG *p_item_info)
+											ZXIC_UINT32 key_by_size,
+											ZXIC_UINT32 rst_by_size,
+											SE_ITEM_CFG *p_item_info)
 {
-    ZXIC_UINT8 srh_succ = 0;
-    ZXIC_UINT8 temp_key_type = 0;
-    ZXIC_UINT8 srh_key_type = 0;
-    D_NODE *p_entry_dn = NULL;
-    DPP_HASH_RBKEY_INFO *p_rbkey = NULL;
-
-    ZXIC_COMM_CHECK_INDEX(key_by_size, 0, HASH_KEY_MAX);
-    ZXIC_COMM_CHECK_POINT(p_entry);
-    ZXIC_COMM_CHECK_POINT(p_entry->p_key);
-    ZXIC_COMM_CHECK_POINT(p_entry->p_rst);
-    ZXIC_COMM_CHECK_POINT(p_item_info);
-    
-    srh_key_type = DPP_GET_HASH_KEY_TYPE(p_entry->p_key);
-    p_entry_dn = p_item_info->item_list.p_next;
-    while (p_entry_dn)
-    {
-        p_rbkey = (DPP_HASH_RBKEY_INFO *)p_entry_dn->data;
-        ZXIC_COMM_CHECK_POINT(p_rbkey);
-        ZXIC_COMM_CHECK_POINT(p_rbkey->key);
-        ZXIC_COMM_CHECK_POINT(p_rbkey->rst);
-
-        ZXIC_COMM_ASSERT(p_rbkey->p_item_info == p_item_info);
-
-        temp_key_type = DPP_GET_HASH_KEY_TYPE(p_rbkey->key);
-
-        if (DPP_GET_HASH_KEY_VALID(p_rbkey->key) && (srh_key_type == temp_key_type))
-        {
-            if (0 == ZXIC_COMM_MEMCMP(p_entry->p_key, p_rbkey->key, key_by_size))
-            {
-                srh_succ = 1;
-                break;
-            }
-        }
-
-        p_entry_dn = p_entry_dn->next;
-    }
-
-    if (NULL == p_rbkey)
-    {
-        return ZXIC_PAR_CHK_POINT_NULL;
-    }
-
-    if(!srh_succ)
-    {
-        ZXIC_COMM_TRACE_DEBUG("dpp_dtb_hash_software_item_check fail!\n");
-        return DPP_HASH_RC_MATCH_ITEM_FAIL;
-    }
-
-    /* copy result */
-    ZXIC_COMM_MEMCPY(p_entry->p_rst, p_rbkey->rst, (rst_by_size > HASH_RST_MAX) ? HASH_RST_MAX : rst_by_size);
-
-    return DPP_OK;
+	ZXIC_UINT8 srh_succ = 0;
+	ZXIC_UINT8 temp_key_type = 0;
+	ZXIC_UINT8 srh_key_type = 0;
+	D_NODE *p_entry_dn = NULL;
+	DPP_HASH_RBKEY_INFO *p_rbkey = NULL;
+
+	ZXIC_COMM_CHECK_INDEX(key_by_size, 0, HASH_KEY_MAX);
+	ZXIC_COMM_CHECK_POINT(p_entry);
+	ZXIC_COMM_CHECK_POINT(p_entry->p_key);
+	ZXIC_COMM_CHECK_POINT(p_entry->p_rst);
+	ZXIC_COMM_CHECK_POINT(p_item_info);
+
+	srh_key_type = DPP_GET_HASH_KEY_TYPE(p_entry->p_key);
+	p_entry_dn = p_item_info->item_list.p_next;
+	while (p_entry_dn) {
+		p_rbkey = (DPP_HASH_RBKEY_INFO *)p_entry_dn->data;
+		ZXIC_COMM_CHECK_POINT(p_rbkey);
+		ZXIC_COMM_CHECK_POINT(p_rbkey->key);
+		ZXIC_COMM_CHECK_POINT(p_rbkey->rst);
+
+		ZXIC_COMM_ASSERT(p_rbkey->p_item_info == p_item_info);
+
+		temp_key_type = DPP_GET_HASH_KEY_TYPE(p_rbkey->key);
+
+		if (DPP_GET_HASH_KEY_VALID(p_rbkey->key) &&
+			(srh_key_type == temp_key_type)) {
+			if (0 ==
+				ZXIC_COMM_MEMCMP(p_entry->p_key, p_rbkey->key, key_by_size)) {
+				srh_succ = 1;
+				break;
+			}
+		}
+
+		p_entry_dn = p_entry_dn->next;
+	}
+
+	if (NULL == p_rbkey) {
+		return ZXIC_PAR_CHK_POINT_NULL;
+	}
+
+	if (!srh_succ) {
+		ZXIC_COMM_TRACE_DEBUG("dpp_dtb_hash_software_item_check fail!\n");
+		return DPP_HASH_RC_MATCH_ITEM_FAIL;
+	}
+
+	/* copy result */
+	ZXIC_COMM_MEMCPY(p_entry->p_rst, p_rbkey->rst,
+					 (rst_by_size > HASH_RST_MAX) ? HASH_RST_MAX : rst_by_size);
+
+	return DPP_OK;
 }
 
 /** hash表项解析，在512bit存储单元里查找并比对
-* @param   item_type        
-* @param   key_by_size     键值大小 
-* @param   p_entry         入参：hash表项键值 出参：hash表项结果
-* @param   p_item_data    查找键值信息
-* @param   p_data_offset    查找键值在512bit里的偏移位置,单位为字节
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-ZXIC_UINT32 dpp_dtb_hash_data_parse(ZXIC_UINT32 item_type, 
-                                   ZXIC_UINT32 key_by_size,
-                                   DPP_HASH_ENTRY *p_entry,
-                                   ZXIC_UINT8  *p_item_data,
-                                   ZXIC_UINT8  *p_data_offset)
+ * @param   item_type
+ * @param   key_by_size     键值大小
+ * @param   p_entry         入参：hash表项键值 出参：hash表项结果
+ * @param   p_item_data    查找键值信息
+ * @param   p_data_offset    查找键值在512bit里的偏移位置,单位为字节
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/02
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_hash_data_parse(ZXIC_UINT32 item_type,
+									ZXIC_UINT32 key_by_size,
+									DPP_HASH_ENTRY *p_entry,
+									ZXIC_UINT8 *p_item_data,
+									ZXIC_UINT8 *p_data_offset)
 {
-    ZXIC_UINT32 data_offset = 0;
-    ZXIC_UINT8 temp_key_valid = 0;
-    ZXIC_UINT8 temp_key_type = 0;
-    ZXIC_UINT32 temp_entry_size = 0;
-    ZXIC_UINT8 srh_key_type = 0;
-    ZXIC_UINT32 srh_entry_size = 0;
-    ZXIC_UINT32 rst_by_size = 0;
-    ZXIC_UINT8 srh_succ = 0;
-    ZXIC_UINT32 item_width = SE_ITEM_WIDTH_MAX;
-    ZXIC_UINT8 *p_srh_key = NULL;
-    ZXIC_UINT8 *p_temp_key = NULL;
-    ZXIC_UINT32 i = 0;
-    
-    ZXIC_COMM_CHECK_POINT(p_item_data);
-    ZXIC_COMM_CHECK_POINT(p_entry);
-    ZXIC_COMM_CHECK_POINT(p_entry->p_key);
-
-    if (ITEM_DDR_256 == item_type)
-    {
-        item_width = item_width / 2;
-    }
-
-    p_temp_key = p_item_data;
-    p_srh_key = p_entry->p_key;
-    srh_key_type = DPP_GET_HASH_KEY_TYPE(p_srh_key);
-    srh_entry_size = DPP_GET_HASH_ENTRY_SIZE(srh_key_type);
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("srh_key:0x");
-
-        for(i = 0; i < key_by_size; i++)
-        {
-            ZXIC_COMM_PRINT("%02x ", p_srh_key[i]);
-        }
-        ZXIC_COMM_PRINT("\n");
-    }
-
-    while (data_offset < item_width)
-    {
-        temp_key_valid = DPP_GET_HASH_KEY_VALID(p_temp_key);
-        temp_key_type = DPP_GET_HASH_KEY_TYPE(p_temp_key);
-
-        if (temp_key_valid && (srh_key_type == temp_key_type))
-        {
-            if (0 == ZXIC_COMM_MEMCMP(p_srh_key, p_temp_key, key_by_size))
-            {
-                ZXIC_COMM_TRACE_DEBUG("Hash search hardware successfully. \n");
-                srh_succ = 1;
-                break;
-            }
-
-            data_offset += srh_entry_size;
-        }
-        else if (temp_key_valid && (srh_key_type != temp_key_type))
-        {
-            temp_entry_size = DPP_GET_HASH_ENTRY_SIZE(temp_key_type);
-            ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(data_offset, temp_entry_size);
-            data_offset += temp_entry_size;
-        }
-        else
-        {
-            data_offset += 16;/* 偏移最小的步长128bit */
-        }
-
-        p_temp_key = p_item_data;
-        p_temp_key += data_offset;
-    }
-
-    if(!srh_succ)
-    {
-        ZXIC_COMM_TRACE_DEBUG("Hash search hardware fail. \n");
-        return DPP_HASH_RC_MATCH_ITEM_FAIL;
-    }
-
-    /* copy result */
-    rst_by_size = srh_entry_size - key_by_size;
-    ZXIC_COMM_MEMCPY(p_entry->p_rst, p_temp_key + key_by_size, (rst_by_size > HASH_RST_MAX) ? HASH_RST_MAX : rst_by_size);
-    *p_data_offset = data_offset;
-
-    return DPP_OK;
+	ZXIC_UINT32 data_offset = 0;
+	ZXIC_UINT8 temp_key_valid = 0;
+	ZXIC_UINT8 temp_key_type = 0;
+	ZXIC_UINT32 temp_entry_size = 0;
+	ZXIC_UINT8 srh_key_type = 0;
+	ZXIC_UINT32 srh_entry_size = 0;
+	ZXIC_UINT32 rst_by_size = 0;
+	ZXIC_UINT8 srh_succ = 0;
+	ZXIC_UINT32 item_width = SE_ITEM_WIDTH_MAX;
+	ZXIC_UINT8 *p_srh_key = NULL;
+	ZXIC_UINT8 *p_temp_key = NULL;
+	ZXIC_UINT32 i = 0;
+
+	ZXIC_COMM_CHECK_POINT(p_item_data);
+	ZXIC_COMM_CHECK_POINT(p_entry);
+	ZXIC_COMM_CHECK_POINT(p_entry->p_key);
+
+	if (ITEM_DDR_256 == item_type) {
+		item_width = item_width / 2;
+	}
+
+	p_temp_key = p_item_data;
+	p_srh_key = p_entry->p_key;
+	srh_key_type = DPP_GET_HASH_KEY_TYPE(p_srh_key);
+	srh_entry_size = DPP_GET_HASH_ENTRY_SIZE(srh_key_type);
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("srh_key:0x");
+
+		for (i = 0; i < key_by_size; i++) {
+			ZXIC_COMM_PRINT("%02x ", p_srh_key[i]);
+		}
+		ZXIC_COMM_PRINT("\n");
+	}
+
+	while (data_offset < item_width) {
+		temp_key_valid = DPP_GET_HASH_KEY_VALID(p_temp_key);
+		temp_key_type = DPP_GET_HASH_KEY_TYPE(p_temp_key);
+
+		if (temp_key_valid && (srh_key_type == temp_key_type)) {
+			if (0 == ZXIC_COMM_MEMCMP(p_srh_key, p_temp_key, key_by_size)) {
+				ZXIC_COMM_TRACE_DEBUG("Hash search hardware successfully. \n");
+				srh_succ = 1;
+				break;
+			}
+
+			data_offset += srh_entry_size;
+		} else if (temp_key_valid && (srh_key_type != temp_key_type)) {
+			temp_entry_size = DPP_GET_HASH_ENTRY_SIZE(temp_key_type);
+			ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(data_offset,
+														 temp_entry_size);
+			data_offset += temp_entry_size;
+		} else {
+			data_offset += 16; /* 偏移最小的步长128bit */
+		}
+
+		p_temp_key = p_item_data;
+		p_temp_key += data_offset;
+	}
+
+	if (!srh_succ) {
+		ZXIC_COMM_TRACE_DEBUG("Hash search hardware fail. \n");
+		return DPP_HASH_RC_MATCH_ITEM_FAIL;
+	}
+
+	/* copy result */
+	rst_by_size = srh_entry_size - key_by_size;
+	ZXIC_COMM_MEMCPY(p_entry->p_rst, p_temp_key + key_by_size,
+					 (rst_by_size > HASH_RST_MAX) ? HASH_RST_MAX : rst_by_size);
+	*p_data_offset = data_offset;
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 查找存储在DDR空间的hash表项
-* @param   dev_id       设备号，支持多芯片 
-* @param   queue_id     队列id 
-* @param   p_hash_entry_cfg hash表项配置信息
-* @param   p_hash_entry    查找键值信息
-* @param   p_srh_succ      出参，查找是否成功
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-ZXIC_UINT32 dpp_dtb_hash_ddr_get(DPP_DEV_T *dev, 
-                                 ZXIC_UINT32 queue_id,
-                                 HASH_ENTRY_CFG  *p_hash_entry_cfg,
-                                 DPP_HASH_ENTRY  *p_hash_entry,
-                                 ZXIC_UINT8 *p_srh_succ)
+ * @param   dev_id       设备号，支持多芯片
+ * @param   queue_id     队列id
+ * @param   p_hash_entry_cfg hash表项配置信息
+ * @param   p_hash_entry    查找键值信息
+ * @param   p_srh_succ      出参，查找是否成功
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/02
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_hash_ddr_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								 HASH_ENTRY_CFG *p_hash_entry_cfg,
+								 DPP_HASH_ENTRY *p_hash_entry,
+								 ZXIC_UINT8 *p_srh_succ)
 {
-    DPP_STATUS           rc           = DPP_OK;   
-    ZXIC_UINT32          item_idx     = 0xFFFFFFFF;/* -1 */
-    ZXIC_UINT32          item_type    = 0;
-    ZXIC_UINT32          crc_value    = 0;
-    ZXIC_UINT32          index        = 0;
-    ZXIC_UINT32          index_offset = 0;
-    ZXIC_UINT32          hw_addr      = 0;  /*单位512bit*/
-    ZXIC_UINT32          base_addr    = 0;  /*单位2k*256bit*/ 
-    ZXIC_UINT32          ecc_en       = 0;
-    ZXIC_UINT32          element_id   = 0;
-    ZXIC_UINT32          byte_len     = 0;
-    ZXIC_UINT8           byte_offset  = 0;
-    ZXIC_UINT8 temp_key[HASH_KEY_MAX] = {0};
-    HASH_DDR_CFG         *p_ddr_cfg   = NULL;
-    DPP_HASH_CFG         *p_hash_cfg = NULL;
-    ZXIC_UINT32          rd_buff[DPP_DIR_TBL_BUF_MAX_NUM]   = {0};
-    ZXIC_UINT8           temp_data[DPP_DIR_TBL_BUF_MAX_NUM*4] = {0};
-    SE_ITEM_CFG *p_item = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry);
-    ZXIC_COMM_CHECK_POINT(p_srh_succ);
-
-    ZXIC_COMM_MEMSET((ZXIC_UINT8 *)rd_buff,0x0,sizeof(rd_buff));
-    ZXIC_COMM_MEMSET(temp_data,0x0,sizeof(temp_data));
-
-    rc = dpp_se_smmu1_hash_tbl_soft_cfg_get(dev,
-                                            p_hash_entry_cfg->fun_id,
-                                            p_hash_entry_cfg->bulk_id,
-                                            &ecc_en,
-                                            &base_addr);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_smmu1_hash_tbl_soft_cfg_get");
-
-    p_hash_cfg = p_hash_entry_cfg->p_hash_cfg;
-    ZXIC_COMM_CHECK_POINT(p_hash_cfg);
-    ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->bulk_id,HASH_BULK_ID_MAX);
-    p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[p_hash_entry_cfg->bulk_id];
-    ZXIC_COMM_CHECK_POINT(p_ddr_cfg);
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->key_by_size, HASH_KEY_MAX);
-    rc = dpp_hash_set_crc_key(dev,p_hash_entry_cfg,p_hash_entry,temp_key);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev),rc,"hash_set_crc_key");
-
-    crc_value = p_hash_cfg->p_hash32_fun(temp_key, p_hash_entry_cfg->key_by_size, p_ddr_cfg->hash_ddr_arg);
-    item_idx = crc_value % p_ddr_cfg->item_num;
-    index = p_ddr_cfg->hw_baddr + item_idx;
-    if (DDR_WIDTH_512b == p_ddr_cfg->width_mode)
-    {
-        item_type = ITEM_DDR_512;
-        hw_addr = (base_addr<<10) + index;
-        index_offset = 0;
-        byte_len = 512/8;
-    }
-    else
-    {
-        item_type = ITEM_DDR_256;
-        hw_addr = (base_addr<<10) + (index>>1);
-        index_offset = index & 0x1;
-        byte_len = 256/8;
-    }
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), 
-               "Hash search in ITEM_DDR_%s, CRC32 index is: 0x%x.\n", ((item_type == ITEM_DDR_256) ? "256" : "512"), 
-                item_idx);
-    if(dpp_dtb_srh_mode_get())
-    {
-        rc = dpp_dtb_se_smmu1_dma_dump(dev, 
-                                   queue_id, 
-                                   hw_addr, 
-                                   1,
-                                   rd_buff,
-                                   &element_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,"dpp_dtb_se_smmu1_dma_dump");
-
-        zxic_comm_swap((ZXIC_UINT8 *)(rd_buff+index_offset*8), byte_len);
-        ZXIC_COMM_MEMCPY(temp_data, rd_buff+index_offset*8, byte_len);
-
-        rc = dpp_dtb_hash_data_parse(item_type,p_hash_entry_cfg->key_by_size,p_hash_entry,temp_data,&byte_offset);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_hash_data_parse");
-   
-        ZXIC_COMM_TRACE_DEBUG("Hash search hardware succ in ddr. \n"); 
-    }
-    else
-    {
-        ZXIC_COMM_CHECK_INDEX_UPPER(item_idx, p_ddr_cfg->item_num - 1);
-        p_item = p_ddr_cfg->p_item_array[item_idx];
-        ZXIC_COMM_CHECK_POINT_NO_ASSERT(p_item);
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), p_ddr_cfg->hw_baddr, item_idx);
-        p_item->hw_addr = p_ddr_cfg->hw_baddr+item_idx;
-        p_item->item_type = item_type;
-        p_item->item_index = item_idx;
-    
-        rc = dpp_dtb_hash_software_item_check(p_hash_entry,
-                                    p_hash_entry_cfg->key_by_size,
-                                    p_hash_entry_cfg->rst_by_size,
-                                    p_item);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_software_item_check");
-    }
-
-    *p_srh_succ = 1;
-    p_hash_cfg->hash_stat.search_ok++;
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 item_idx = 0xFFFFFFFF; /* -1 */
+	ZXIC_UINT32 item_type = 0;
+	ZXIC_UINT32 crc_value = 0;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 index_offset = 0;
+	ZXIC_UINT32 hw_addr = 0; /*单位512bit*/
+	ZXIC_UINT32 base_addr = 0; /*单位2k*256bit*/
+	ZXIC_UINT32 ecc_en = 0;
+	ZXIC_UINT32 element_id = 0;
+	ZXIC_UINT32 byte_len = 0;
+	ZXIC_UINT8 byte_offset = 0;
+	ZXIC_UINT8 temp_key[HASH_KEY_MAX] = { 0 };
+	HASH_DDR_CFG *p_ddr_cfg = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	ZXIC_UINT32 rd_buff[DPP_DIR_TBL_BUF_MAX_NUM] = { 0 };
+	ZXIC_UINT8 temp_data[DPP_DIR_TBL_BUF_MAX_NUM * 4] = { 0 };
+	SE_ITEM_CFG *p_item = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry);
+	ZXIC_COMM_CHECK_POINT(p_srh_succ);
+
+	ZXIC_COMM_MEMSET((ZXIC_UINT8 *)rd_buff, 0x0, sizeof(rd_buff));
+	ZXIC_COMM_MEMSET(temp_data, 0x0, sizeof(temp_data));
+
+	rc = dpp_se_smmu1_hash_tbl_soft_cfg_get(dev, p_hash_entry_cfg->fun_id,
+											p_hash_entry_cfg->bulk_id, &ecc_en,
+											&base_addr);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+						   "dpp_se_smmu1_hash_tbl_soft_cfg_get");
+
+	p_hash_cfg = p_hash_entry_cfg->p_hash_cfg;
+	ZXIC_COMM_CHECK_POINT(p_hash_cfg);
+	ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->bulk_id, HASH_BULK_ID_MAX);
+	p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[p_hash_entry_cfg->bulk_id];
+	ZXIC_COMM_CHECK_POINT(p_ddr_cfg);
+
+	rc = dpp_hash_set_crc_key(dev, p_hash_entry_cfg, p_hash_entry, temp_key);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "hash_set_crc_key");
+
+	crc_value = p_hash_cfg->p_hash32_fun(
+			temp_key, p_hash_entry_cfg->key_by_size, p_ddr_cfg->hash_ddr_arg);
+	item_idx = crc_value % p_ddr_cfg->item_num;
+	index = p_ddr_cfg->hw_baddr + item_idx;
+	if (DDR_WIDTH_512b == p_ddr_cfg->width_mode) {
+		item_type = ITEM_DDR_512;
+		hw_addr = (base_addr << 10) + index;
+		index_offset = 0;
+		byte_len = 512 / 8;
+	} else {
+		item_type = ITEM_DDR_256;
+		hw_addr = (base_addr << 10) + (index >> 1);
+		index_offset = index & 0x1;
+		byte_len = 256 / 8;
+	}
+
+	ZXIC_COMM_TRACE_DEV_DEBUG(
+			DEV_ID(dev), "Hash search in ITEM_DDR_%s, CRC32 index is: 0x%x.\n",
+			((item_type == ITEM_DDR_256) ? "256" : "512"), item_idx);
+	if (dpp_dtb_srh_mode_get()) {
+		rc = dpp_dtb_se_smmu1_dma_dump(dev, queue_id, hw_addr, 1, rd_buff,
+									   &element_id);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_dtb_se_smmu1_dma_dump");
+
+		zxic_comm_swap((ZXIC_UINT8 *)(rd_buff + index_offset * 8), byte_len);
+		ZXIC_COMM_MEMCPY(temp_data, rd_buff + index_offset * 8, byte_len);
+
+		rc = dpp_dtb_hash_data_parse(item_type, p_hash_entry_cfg->key_by_size,
+									 p_hash_entry, temp_data, &byte_offset);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_dtb_hash_data_parse");
+
+		ZXIC_COMM_TRACE_DEBUG("Hash search hardware succ in ddr. \n");
+	} else {
+		ZXIC_COMM_CHECK_INDEX_UPPER(item_idx, p_ddr_cfg->item_num - 1);
+		p_item = p_ddr_cfg->p_item_array[item_idx];
+		ZXIC_COMM_CHECK_POINT_NO_ASSERT(p_item);
+		ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(
+				DEV_ID(dev), p_ddr_cfg->hw_baddr, item_idx);
+		p_item->hw_addr = p_ddr_cfg->hw_baddr + item_idx;
+		p_item->item_type = item_type;
+		p_item->item_index = item_idx;
+
+		rc = dpp_dtb_hash_software_item_check(p_hash_entry,
+											  p_hash_entry_cfg->key_by_size,
+											  p_hash_entry_cfg->rst_by_size,
+											  p_item);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_software_item_check");
+	}
+
+	*p_srh_succ = 1;
+	p_hash_cfg->hash_stat.search_ok++;
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 查找存储在ZCAM空间的hash表项
-* @param   dev_id       设备号，支持多芯片 
-* @param   queue_id     队列id 
-* @param   p_hash_entry_cfg hash表项配置信息
-* @param   p_hash_entry    查找键值信息
-* @param   p_srh_succ      出参，查找是否成功
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-ZXIC_UINT32 dpp_dtb_hash_zcam_get(DPP_DEV_T *dev, 
-                                 ZXIC_UINT32 queue_id,
-                                 HASH_ENTRY_CFG  *p_hash_entry_cfg,
-                                 DPP_HASH_ENTRY  *p_hash_entry,
-                                 ZXIC_UINT8 *p_srh_succ)
+ * @param   dev_id       设备号，支持多芯片
+ * @param   queue_id     队列id
+ * @param   p_hash_entry_cfg hash表项配置信息
+ * @param   p_hash_entry    查找键值信息
+ * @param   p_srh_succ      出参，查找是否成功
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/02
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_hash_zcam_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								  HASH_ENTRY_CFG *p_hash_entry_cfg,
+								  DPP_HASH_ENTRY *p_hash_entry,
+								  ZXIC_UINT8 *p_srh_succ)
 {
-    DPP_STATUS rc = DPP_OK;
-    DPP_HASH_RBKEY_INFO srh_rbkey = {0};
-    ZXIC_RB_TN *p_rb_tn_rtn = NULL;
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    DPP_HASH_RBKEY_INFO *p_rbkey = NULL;
-    SE_ITEM_CFG *p_item = NULL;
-    ZXIC_UINT32 element_id = 0;
-    ZXIC_UINT8  rd_buff[SE_ITEM_WIDTH_MAX]   = {0};
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT8  byte_offset = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev),DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
-    ZXIC_COMM_CHECK_POINT(p_srh_succ);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry->p_key);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry->p_rst);
-
-    ZXIC_COMM_MEMSET(rd_buff,0x0,sizeof(rd_buff));
-    ZXIC_COMM_MEMSET(&srh_rbkey,0x0,sizeof(DPP_HASH_RBKEY_INFO));
-    ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->key_by_size, HASH_KEY_MAX);
-    ZXIC_COMM_MEMCPY(srh_rbkey.key,p_hash_entry->p_key,p_hash_entry_cfg->key_by_size);
-
-    p_hash_cfg = p_hash_entry_cfg->p_hash_cfg;
-    ZXIC_COMM_CHECK_POINT(p_hash_cfg);
-
-    rc = zxic_comm_rb_search(&p_hash_cfg->hash_rb, (ZXIC_VOID *)&srh_rbkey, (ZXIC_VOID *)(&p_rb_tn_rtn));
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_rb_search hash fail");
-    ZXIC_COMM_CHECK_POINT(p_rb_tn_rtn);
-    p_rbkey = p_rb_tn_rtn->p_key;
-
-    ZXIC_COMM_CHECK_POINT(p_rbkey);
-    p_item = p_rbkey->p_item_info;
-    ZXIC_COMM_CHECK_POINT(p_item);
-
-    if(dpp_dtb_srh_mode_get())
-    {
-        rc =  dpp_dtb_se_zcam_dma_dump(dev, queue_id, p_item->hw_addr, DTB_DUMP_ZCAM_512b, 1,(ZXIC_UINT32 *)rd_buff, &element_id);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_se_zcam_dma_dump");
-        zxic_comm_swap(rd_buff,sizeof(rd_buff));
-
-        if(dpp_dtb_prt_get())
-        {
-            ZXIC_COMM_PRINT("dump data:\n");
-
-            for(i = 0; i < SE_ITEM_WIDTH_MAX; i++)
-            {
-                ZXIC_COMM_PRINT("%02x ", rd_buff[i]);
-                if((i + 1) % 16 == 0)
-                {
-                    ZXIC_COMM_PRINT("\n");
-                }
-            }
-            ZXIC_COMM_PRINT("\n");
-        }
-
-        rc = dpp_dtb_hash_data_parse(ITEM_RAM,p_hash_entry_cfg->key_by_size,p_hash_entry,rd_buff,&byte_offset);
-        if(DPP_OK == rc)
-        {
-            ZXIC_COMM_TRACE_DEBUG("Hash search hardware succ in zcam. \n");
-            *p_srh_succ = 1;
-            p_hash_cfg->hash_stat.search_ok++;
-        }
-        else
-        {
-            ZXIC_COMM_TRACE_DEBUG("Hash search hardware fail in zcam. \n");
-        }
-    }
-    else
-    {
-        rc = dpp_dtb_hash_software_item_check(p_hash_entry,
-                                        p_hash_entry_cfg->key_by_size,
-                                        p_hash_entry_cfg->rst_by_size,
-                                        p_item);
-        if(DPP_OK == rc)
-        {
-            ZXIC_COMM_TRACE_DEBUG("Hash search software succ in zcell. \n");
-            *p_srh_succ = 1;
-            p_hash_cfg->hash_stat.search_ok++;
-        }
-    }
-
-    return DPP_OK;
-
+	DPP_STATUS rc = DPP_OK;
+	DPP_HASH_RBKEY_INFO srh_rbkey = { 0 };
+	ZXIC_RB_TN *p_rb_tn_rtn = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	DPP_HASH_RBKEY_INFO *p_rbkey = NULL;
+	SE_ITEM_CFG *p_item = NULL;
+	ZXIC_UINT32 element_id = 0;
+	ZXIC_UINT8 rd_buff[SE_ITEM_WIDTH_MAX] = { 0 };
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT8 byte_offset = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
+	ZXIC_COMM_CHECK_POINT(p_srh_succ);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry->p_key);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry->p_rst);
+
+	ZXIC_COMM_MEMSET(rd_buff, 0x0, sizeof(rd_buff));
+	ZXIC_COMM_MEMSET(&srh_rbkey, 0x0, sizeof(DPP_HASH_RBKEY_INFO));
+	ZXIC_COMM_MEMCPY(srh_rbkey.key, p_hash_entry->p_key,
+					 p_hash_entry_cfg->key_by_size);
+
+	p_hash_cfg = p_hash_entry_cfg->p_hash_cfg;
+	ZXIC_COMM_CHECK_POINT(p_hash_cfg);
+
+	rc = zxic_comm_rb_search(&p_hash_cfg->hash_rb, (ZXIC_VOID *)&srh_rbkey,
+							 (ZXIC_VOID *)(&p_rb_tn_rtn));
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "zxic_comm_rb_search hash fail");
+	ZXIC_COMM_CHECK_POINT(p_rb_tn_rtn);
+	p_rbkey = p_rb_tn_rtn->p_key;
+
+	ZXIC_COMM_CHECK_POINT(p_rbkey);
+	p_item = p_rbkey->p_item_info;
+	ZXIC_COMM_CHECK_POINT(p_item);
+
+	if (dpp_dtb_srh_mode_get()) {
+		rc = dpp_dtb_se_zcam_dma_dump(dev, queue_id, p_item->hw_addr,
+									  DTB_DUMP_ZCAM_512b, 1,
+									  (ZXIC_UINT32 *)rd_buff, &element_id);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_se_zcam_dma_dump");
+		zxic_comm_swap(rd_buff, sizeof(rd_buff));
+
+		if (dpp_dtb_prt_get()) {
+			ZXIC_COMM_PRINT("dump data:\n");
+
+			for (i = 0; i < SE_ITEM_WIDTH_MAX; i++) {
+				ZXIC_COMM_PRINT("%02x ", rd_buff[i]);
+				if ((i + 1) % 16 == 0) {
+					ZXIC_COMM_PRINT("\n");
+				}
+			}
+			ZXIC_COMM_PRINT("\n");
+		}
+
+		rc = dpp_dtb_hash_data_parse(ITEM_RAM, p_hash_entry_cfg->key_by_size,
+									 p_hash_entry, rd_buff, &byte_offset);
+		if (DPP_OK == rc) {
+			ZXIC_COMM_TRACE_DEBUG("Hash search hardware succ in zcam. \n");
+			*p_srh_succ = 1;
+			p_hash_cfg->hash_stat.search_ok++;
+		} else {
+			ZXIC_COMM_TRACE_DEBUG("Hash search hardware fail in zcam. \n");
+		}
+	} else {
+		rc = dpp_dtb_hash_software_item_check(p_hash_entry,
+											  p_hash_entry_cfg->key_by_size,
+											  p_hash_entry_cfg->rst_by_size,
+											  p_item);
+		if (DPP_OK == rc) {
+			ZXIC_COMM_TRACE_DEBUG("Hash search software succ in zcell. \n");
+			*p_srh_succ = 1;
+			p_hash_cfg->hash_stat.search_ok++;
+		}
+	}
+
+	return DPP_OK;
 }
 
-
 /** dtb根据etcam key计算dump出数据占用的数据长度
-* @param   dev_id                 设备号
-* @param   etcam_key_mode         etcam条目位宽，参照DPP_ETCAM_ENTRY_MODE_E定义
-* @param   p_etcam_dump_len       dtb dump出etcam的数据长度(单位:字节)
-* @param   p_etcam_dump_inerval   dump出etcam数据的间隔数据长度(单位：字节)
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dtb_etcam_dump_data_len(DPP_DEV_T *dev, 
-                                   ZXIC_UINT32 etcam_key_mode, 
-                                   ZXIC_UINT32 *p_etcam_dump_len, 
-                                   ZXIC_UINT32* p_etcam_dump_inerval)
+ * @param   dev_id                 设备号
+ * @param   etcam_key_mode         etcam条目位宽，参照DPP_ETCAM_ENTRY_MODE_E定义
+ * @param   p_etcam_dump_len       dtb dump出etcam的数据长度(单位:字节)
+ * @param   p_etcam_dump_inerval   dump出etcam数据的间隔数据长度(单位：字节)
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dtb_etcam_dump_data_len(DPP_DEV_T *dev, ZXIC_UINT32 etcam_key_mode,
+								   ZXIC_UINT32 *p_etcam_dump_len,
+								   ZXIC_UINT32 *p_etcam_dump_inerval)
 {
-    ZXIC_UINT32 dump_data_len = 0;
-    ZXIC_UINT8 etcam_dump_inerval = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_etcam_dump_len);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_etcam_dump_inerval);
-
-    if(DPP_ETCAM_KEY_640b == etcam_key_mode)
-    {
-        dump_data_len = 5 * DTB_LEN_POS_SETP;
-        etcam_dump_inerval = 0;
-    }
-    else if(DPP_ETCAM_KEY_320b == etcam_key_mode)
-    {
-        dump_data_len = 3 * DTB_LEN_POS_SETP;
-        etcam_dump_inerval = 8;
-    }
-    else if(DPP_ETCAM_KEY_160b == etcam_key_mode)
-    {
-        dump_data_len = 2 * DTB_LEN_POS_SETP;
-        etcam_dump_inerval = 12;
-    }
-    else if(DPP_ETCAM_KEY_80b == etcam_key_mode)
-    {
-        dump_data_len = 1 * DTB_LEN_POS_SETP;
-        etcam_dump_inerval = 6;
-    }
-
-    *p_etcam_dump_len = dump_data_len;
-    *p_etcam_dump_inerval = etcam_dump_inerval;
-
-    return DPP_OK;
+	ZXIC_UINT32 dump_data_len = 0;
+	ZXIC_UINT8 etcam_dump_inerval = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_etcam_dump_len);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_etcam_dump_inerval);
+
+	if (DPP_ETCAM_KEY_640b == etcam_key_mode) {
+		dump_data_len = 5 * DTB_LEN_POS_SETP;
+		etcam_dump_inerval = 0;
+	} else if (DPP_ETCAM_KEY_320b == etcam_key_mode) {
+		dump_data_len = 3 * DTB_LEN_POS_SETP;
+		etcam_dump_inerval = 8;
+	} else if (DPP_ETCAM_KEY_160b == etcam_key_mode) {
+		dump_data_len = 2 * DTB_LEN_POS_SETP;
+		etcam_dump_inerval = 12;
+	} else if (DPP_ETCAM_KEY_80b == etcam_key_mode) {
+		dump_data_len = 1 * DTB_LEN_POS_SETP;
+		etcam_dump_inerval = 6;
+	}
+
+	*p_etcam_dump_len = dump_data_len;
+	*p_etcam_dump_inerval = etcam_dump_inerval;
+
+	return DPP_OK;
 }
 
 /** dtb 从dump数据中提取到xy数据
-* @param   dev_id                 设备号
-* @param   p_data                 dump出的etcam data 指针
-* @param   p_mask                 dump出的etcam mask 指针
-* @param   p_etcam_dump_len       dtb dump出etcam的数据长度(单位:字节)
-* @param   p_etcam_dump_inerval   dump出etcam数据的间隔数据长度(单位：字节)
-* @param   p_entry_xy             保存etcam xy数据（已分配内存）
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_get_etcam_xy_from_dump_data(DPP_DEV_T *dev, 
-                                               ZXIC_UINT8 *p_data, 
-                                               ZXIC_UINT8 *p_mask, 
-                                               ZXIC_UINT32 etcam_dump_len,
-                                               ZXIC_UINT32 etcam_dump_inerval, 
-                                               DPP_ETCAM_ENTRY_T *p_entry_xy)
+ * @param   dev_id                 设备号
+ * @param   p_data                 dump出的etcam data 指针
+ * @param   p_mask                 dump出的etcam mask 指针
+ * @param   p_etcam_dump_len       dtb dump出etcam的数据长度(单位:字节)
+ * @param   p_etcam_dump_inerval   dump出etcam数据的间隔数据长度(单位：字节)
+ * @param   p_entry_xy             保存etcam xy数据（已分配内存）
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_get_etcam_xy_from_dump_data(DPP_DEV_T *dev,
+											   ZXIC_UINT8 *p_data,
+											   ZXIC_UINT8 *p_mask,
+											   ZXIC_UINT32 etcam_dump_len,
+											   ZXIC_UINT32 etcam_dump_inerval,
+											   DPP_ETCAM_ENTRY_T *p_entry_xy)
 {
-    ZXIC_UINT8 *p_entry_data = NULL;
-    ZXIC_UINT8 *p_entry_mask = NULL;
+	ZXIC_UINT8 *p_entry_data = NULL;
+	ZXIC_UINT8 *p_entry_mask = NULL;
 
-    //先对数据进行翻转再进行数据的截取，最后进行数据的复制
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mask);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_xy);
+	//先对数据进行翻转再进行数据的截取，最后进行数据的复制
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mask);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_xy);
 
-    zxic_comm_swap(p_data, etcam_dump_len);
-    zxic_comm_swap(p_mask, etcam_dump_len);
+	zxic_comm_swap(p_data, etcam_dump_len);
+	zxic_comm_swap(p_mask, etcam_dump_len);
 
-    p_entry_data = p_data + etcam_dump_inerval;
-    p_entry_mask = p_mask + etcam_dump_inerval;
+	p_entry_data = p_data + etcam_dump_inerval;
+	p_entry_mask = p_mask + etcam_dump_inerval;
 
-    ZXIC_COMM_MEMCPY(p_entry_xy->p_data, p_entry_data, DPP_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode));
-    ZXIC_COMM_MEMCPY(p_entry_xy->p_mask, p_entry_mask, DPP_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode));
+	ZXIC_COMM_MEMCPY(p_entry_xy->p_data, p_entry_data,
+					 DPP_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode));
+	ZXIC_COMM_MEMCPY(p_entry_xy->p_mask, p_entry_mask,
+					 DPP_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode));
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 /** dtb dump etcam直接表表项内容 级联eram支持64bit/128bit
-* @param   dev_id             设备号
-* @param   p_in_data          长度为640bit的输入数据
-* @param   rd_mode            读模式
-* @param   p_out_data         按照读模式读出的数据
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_etcam_ind_data_get(DPP_DEV_T *dev, ZXIC_UINT8 *p_in_data, ZXIC_UINT32 rd_mode, ZXIC_UINT8 *p_out_data)
+ * @param   dev_id             设备号
+ * @param   p_in_data          长度为640bit的输入数据
+ * @param   rd_mode            读模式
+ * @param   p_out_data         按照读模式读出的数据
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_etcam_ind_data_get(DPP_DEV_T *dev, ZXIC_UINT8 *p_in_data,
+									  ZXIC_UINT32 rd_mode,
+									  ZXIC_UINT8 *p_out_data)
 {
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT8 *p_temp = NULL;
-    ZXIC_UINT32 offset = 0;
-    ZXIC_UINT8  buff[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_in_data);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_out_data);
-    
-    p_temp = p_out_data;
-    ZXIC_COMM_MEMCPY(buff, p_in_data, DPP_ETCAM_WIDTH_MAX / 8);
-
-    zxic_comm_swap(buff, DPP_ETCAM_WIDTH_MAX / 8);
-
-    for (i = 0; i < DPP_ETCAM_RAM_NUM; i++)
-    {
-        offset = i * (DPP_ETCAM_WIDTH_MIN / 8);
-
-        if ((rd_mode >> (DPP_ETCAM_RAM_NUM - 1 - i)) & 0x1)
-        {
-            ZXIC_COMM_MEMCPY(p_temp, buff + offset, DPP_ETCAM_WIDTH_MIN / 8);
-            p_temp += DPP_ETCAM_WIDTH_MIN / 8;
-        }
-    }
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT8 *p_temp = NULL;
+	ZXIC_UINT32 offset = 0;
+	ZXIC_UINT8 buff[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_in_data);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_out_data);
+
+	p_temp = p_out_data;
+	ZXIC_COMM_MEMCPY(buff, p_in_data, DPP_ETCAM_WIDTH_MAX / 8);
+
+	zxic_comm_swap(buff, DPP_ETCAM_WIDTH_MAX / 8);
+
+	for (i = 0; i < DPP_ETCAM_RAM_NUM; i++) {
+		offset = i * (DPP_ETCAM_WIDTH_MIN / 8);
+
+		if ((rd_mode >> (DPP_ETCAM_RAM_NUM - 1 - i)) & 0x1) {
+			ZXIC_COMM_MEMCPY(p_temp, buff + offset, DPP_ETCAM_WIDTH_MIN / 8);
+			p_temp += DPP_ETCAM_WIDTH_MIN / 8;
+		}
+	}
+
+	return rc;
 }
 
 /** dtb dump etcam表项内容
-* @param   dev_id           设备号
-* @param   queue_id         队列号
-* @param   block_idx        block的索引，范围0-7
-* @param   addr             单个block中的RAM地址，范围0~511
-* @param   rd_mode          读block RAM行的位图，共8bit，每比特表示一个RAM中的80bit
-* @param   opr_type         读取的数据类型，0:data/mask格式，1：xy格式     
-* @param   as_en            级联eram使能
-* @param   as_eram_baddr    级联eram基地址
-* @param   as_eram_index    级联eram 条目index
-* @param   as_rsp_mode      级联返回位宽，参见DPP_DIAG_ERAM_MODE_E
-* @param   p_entry          读取的etcam数据
-* @param   p_as_rslt        读取的级联数据(分配128bit存储空间)
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_etcam_entry_get(DPP_DEV_T *dev, 
-                                   ZXIC_UINT32 queue_id,
-                                   ZXIC_UINT32 block_idx, 
-                                   ZXIC_UINT32 addr,
-                                   ZXIC_UINT32 rd_mode,
-                                   ZXIC_UINT32 opr_type, 
-                                   ZXIC_UINT32 as_en,
-                                   ZXIC_UINT32 as_eram_baddr,
-                                   ZXIC_UINT32 as_eram_index,
-                                   ZXIC_UINT32 as_rsp_mode,//128:3   64:2
-                                   DPP_ETCAM_ENTRY_T *p_entry,
-                                   ZXIC_UINT8    *p_as_rslt)
+ * @param   dev_id           设备号
+ * @param   queue_id         队列号
+ * @param   block_idx        block的索引，范围0-7
+ * @param   addr             单个block中的RAM地址，范围0~511
+ * @param   rd_mode          读block RAM行的位图，共8bit，每比特表示一个RAM中的80bit
+ * @param   opr_type         读取的数据类型，0:data/mask格式，1：xy格式
+ * @param   as_en            级联eram使能
+ * @param   as_eram_baddr    级联eram基地址
+ * @param   as_eram_index    级联eram 条目index
+ * @param   as_rsp_mode      级联返回位宽，参见DPP_DIAG_ERAM_MODE_E
+ * @param   p_entry          读取的etcam数据
+ * @param   p_as_rslt        读取的级联数据(分配128bit存储空间)
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_etcam_entry_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								   ZXIC_UINT32 block_idx, ZXIC_UINT32 addr,
+								   ZXIC_UINT32 rd_mode, ZXIC_UINT32 opr_type,
+								   ZXIC_UINT32 as_en, ZXIC_UINT32 as_eram_baddr,
+								   ZXIC_UINT32 as_eram_index,
+								   ZXIC_UINT32 as_rsp_mode, // 128:3   64:2
+								   DPP_ETCAM_ENTRY_T *p_entry,
+								   ZXIC_UINT8 *p_as_rslt)
 {
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 etcam_key_mode = 0;
-
-    ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    DPP_ETCAM_ENTRY_T entry_xy = {0};
-
-    ZXIC_UINT32 etcam_data_dst_phy_haddr = 0;
-    ZXIC_UINT32 etcam_data_dst_phy_laddr = 0;
-    ZXIC_UINT32 etcam_mask_dst_phy_haddr = 0;
-    ZXIC_UINT32 etcam_mask_dst_phy_laddr = 0;
-    ZXIC_UINT32 as_rst_dst_phy_haddr = 0;
-    ZXIC_UINT32 as_rst_dst_phy_laddr = 0;
-
-    ZXIC_UINT32 dump_element_id = 0;
-    ZXIC_UINT32 etcam_dump_one_data_len = 0;
-    ZXIC_UINT32 etcam_dump_inerval = 0;
-    ZXIC_UINT32 dtb_desc_addr_offset = 0;
-    ZXIC_UINT32 dump_data_len = 0;
-    ZXIC_UINT32 dtb_desc_len = 0;
-
-    ZXIC_UINT32 eram_dump_base_addr = 0;
-    ZXIC_UINT32 row_index = 0;
-    ZXIC_UINT32 col_index = 0;
-
-    ZXIC_UINT8 *p_data = NULL;
-    ZXIC_UINT8 *p_mask = NULL;
-    ZXIC_UINT8 *p_rst = NULL;
-    ZXIC_UINT8  *temp_dump_out_data = NULL;
-    ZXIC_UINT8 *dump_info_buff = NULL;
-    ETCAM_DUMP_INFO_T etcam_dump_info = {0};
-    DPP_DTB_ENTRY_T   dtb_dump_entry = {0};
-    ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), addr, 0, DPP_ETCAM_RAM_DEPTH - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0, DPP_ETCAM_BLOCK_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_mode, 0, DPP_ETCAM_WR_MASK_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), opr_type, DPP_ETCAM_OPR_DM, DPP_ETCAM_OPR_XY);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry);
-
-    dump_info_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8));
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dump_info_buff);
-    ZXIC_COMM_MEMSET(dump_info_buff, 0, DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8));
-
-    dtb_dump_entry.cmd = cmd_buff;
-
-    entry_xy.p_data = temp_data;
-    entry_xy.p_mask = temp_mask;
-
-    etcam_key_mode = p_entry->mode;
-
-    etcam_dump_info.block_sel = block_idx;
-    etcam_dump_info.addr = addr;
-    etcam_dump_info.tb_width = 3 - etcam_key_mode;
-    etcam_dump_info.rd_mode = rd_mode;
-    etcam_dump_info.tb_depth = 1;
-
-    rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &dump_element_id);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_free_item_get", dump_info_buff);
-    ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "table up item queue_element_id is: %d.\n",dump_element_id);
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dump etcam:queue %d,element id: %d\n",queue_id, dump_element_id);
-    }
-
-    rc = dtb_etcam_dump_data_len(dev, etcam_key_mode, &etcam_dump_one_data_len, &etcam_dump_inerval);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dtb_etcam_dump_data_len", dump_info_buff);
-
-    //etcam data dump描述符
-    etcam_dump_info.data_or_mask = DPP_ETCAM_DTYPE_DATA;
-    rc = dpp_dtb_tab_up_item_offset_addr_get(dev,
-                                             queue_id,
-                                             dump_element_id,
-                                             dump_data_len,
-                                             &etcam_data_dst_phy_haddr,
-                                             &etcam_data_dst_phy_laddr);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff);
-    rc = dpp_dtb_etcam_dump_entry(dev,
-                                  &etcam_dump_info,
-                                  etcam_data_dst_phy_haddr,
-                                  etcam_data_dst_phy_laddr,
-                                  &dtb_dump_entry);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_etcam_dump_entry", dump_info_buff);
-
-    rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", dump_info_buff);
-    ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
-    dtb_desc_len += 1;
-    dtb_desc_addr_offset += DTB_LEN_POS_SETP;
-    dump_data_len += etcam_dump_one_data_len;
-
-    //etcam mask dump描述符
-    etcam_dump_info.data_or_mask = DPP_ETCAM_DTYPE_MASK;
-    rc = dpp_dtb_tab_up_item_offset_addr_get(dev,
-                                             queue_id,
-                                             dump_element_id,
-                                             dump_data_len,
-                                             &etcam_mask_dst_phy_haddr,
-                                             &etcam_mask_dst_phy_laddr);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff);
-    rc = dpp_dtb_etcam_dump_entry(dev,
-                                  &etcam_dump_info,
-                                  etcam_mask_dst_phy_haddr,
-                                  etcam_mask_dst_phy_laddr,
-                                  &dtb_dump_entry);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_etcam_dump_entry", dump_info_buff);
-    rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", dump_info_buff);
-    ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
-    dtb_desc_len += 1;
-    dtb_desc_addr_offset += DTB_LEN_POS_SETP;
-    dump_data_len += etcam_dump_one_data_len;
-
-    //级联数据dump描述符生成
-    if(as_en)
-    {
-        rc = dtb_eram_index_cal(dev, as_rsp_mode, as_eram_index, &row_index, &col_index);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dtb_eram_index_cal", dump_info_buff);
-
-        eram_dump_base_addr = as_eram_baddr + row_index;
-        ZXIC_COMM_TRACE_INFO("eram_dump_base_addr : 0x%x\n",eram_dump_base_addr);
-        rc = dpp_dtb_tab_up_item_offset_addr_get(dev,
-                                             queue_id,
-                                             dump_element_id,
-                                             dump_data_len,
-                                             &as_rst_dst_phy_haddr,
-                                             &as_rst_dst_phy_laddr);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff);
-
-        rc = dpp_dtb_smmu0_dump_entry(dev, 
-                                      eram_dump_base_addr, 
-                                      1,
-                                      as_rst_dst_phy_haddr,
-                                      as_rst_dst_phy_laddr,
-                                      &dtb_dump_entry);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_smmu0_dump_entry", dump_info_buff);
-        rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", dump_info_buff);
-        ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
-        dtb_desc_len += 1;
-        dtb_desc_addr_offset += DTB_LEN_POS_SETP;
-        dump_data_len += DTB_LEN_POS_SETP;
-    }
-
-    //申请data空间
-    temp_dump_out_data = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(dump_data_len * sizeof(ZXIC_UINT8));
-    ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(temp_dump_out_data, dump_info_buff);
-    ZXIC_COMM_MEMSET(temp_dump_out_data, 0, dump_data_len * sizeof(ZXIC_UINT8));
-    p_data = temp_dump_out_data;
-    /*下发dump描述符*/
-    rc = dpp_dtb_write_dump_desc_info(dev,
-                                      queue_id,
-                                      dump_element_id,
-                                      (ZXIC_UINT32 *)dump_info_buff,
-                                      dump_data_len / 4,
-                                      dtb_desc_len * 4,
-                                      (ZXIC_UINT32 *)temp_dump_out_data);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE2PTR_NO_ASSERT(rc,"dpp_dtb_write_dump_desc_info", dump_info_buff, temp_dump_out_data);
-
-    //解析数据
-    p_data = temp_dump_out_data;
-    p_mask = p_data + etcam_dump_one_data_len;
-
-    rc = dpp_dtb_get_etcam_xy_from_dump_data(dev, 
-                                             p_data, 
-                                             p_mask, 
-                                             etcam_dump_one_data_len,
-                                             etcam_dump_inerval, 
-                                             &entry_xy);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE2PTR_NO_ASSERT(rc, "dpp_dtb_get_etcam_xy_from_dump_data", dump_info_buff, temp_dump_out_data);
-
-    if (opr_type == DPP_ETCAM_OPR_DM)
-    {
-        /* convert hardware data X/Y to user D/M  */
-        rc = dpp_etcam_xy_to_dm(p_entry, &entry_xy, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE2PTR_NO_ASSERT(rc, "dpp_etcam_xy_to_dm", dump_info_buff, temp_dump_out_data);
-    }
-    else
-    {
-        ZXIC_COMM_MEMCPY(p_entry->p_data, entry_xy.p_data, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));
-        ZXIC_COMM_MEMCPY(p_entry->p_mask, entry_xy.p_mask, DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));
-    }
-
-    if(as_en)
-    {
-        //解析dump数据
-        p_rst = p_mask + etcam_dump_one_data_len;
-        ZXIC_COMM_MEMCPY(p_as_rslt, p_rst, (128 / 8));
-    }
-
-    ZXIC_COMM_FREE(dump_info_buff);
-    ZXIC_COMM_FREE(temp_dump_out_data);
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 etcam_key_mode = 0;
+
+	ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	DPP_ETCAM_ENTRY_T entry_xy = { 0 };
+
+	ZXIC_UINT32 etcam_data_dst_phy_haddr = 0;
+	ZXIC_UINT32 etcam_data_dst_phy_laddr = 0;
+	ZXIC_UINT32 etcam_mask_dst_phy_haddr = 0;
+	ZXIC_UINT32 etcam_mask_dst_phy_laddr = 0;
+	ZXIC_UINT32 as_rst_dst_phy_haddr = 0;
+	ZXIC_UINT32 as_rst_dst_phy_laddr = 0;
+
+	ZXIC_UINT32 dump_element_id = 0;
+	ZXIC_UINT32 etcam_dump_one_data_len = 0;
+	ZXIC_UINT32 etcam_dump_inerval = 0;
+	ZXIC_UINT32 dtb_desc_addr_offset = 0;
+	ZXIC_UINT32 dump_data_len = 0;
+	ZXIC_UINT32 dtb_desc_len = 0;
+
+	ZXIC_UINT32 eram_dump_base_addr = 0;
+	ZXIC_UINT32 row_index = 0;
+	ZXIC_UINT32 col_index = 0;
+
+	ZXIC_UINT8 *p_data = NULL;
+	ZXIC_UINT8 *p_mask = NULL;
+	ZXIC_UINT8 *p_rst = NULL;
+	ZXIC_UINT8 *temp_dump_out_data = NULL;
+	ZXIC_UINT8 *dump_info_buff = NULL;
+	ETCAM_DUMP_INFO_T etcam_dump_info = { 0 };
+	DPP_DTB_ENTRY_T dtb_dump_entry = { 0 };
+	ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), addr, 0, DPP_ETCAM_RAM_DEPTH - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), block_idx, 0,
+							  DPP_ETCAM_BLOCK_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), rd_mode, 0, DPP_ETCAM_WR_MASK_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), opr_type, DPP_ETCAM_OPR_DM,
+							  DPP_ETCAM_OPR_XY);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry);
+
+	dump_info_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(
+			DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8));
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dump_info_buff);
+	ZXIC_COMM_MEMSET(dump_info_buff, 0,
+					 DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8));
+
+	dtb_dump_entry.cmd = cmd_buff;
+
+	entry_xy.p_data = temp_data;
+	entry_xy.p_mask = temp_mask;
+
+	etcam_key_mode = p_entry->mode;
+
+	etcam_dump_info.block_sel = block_idx;
+	etcam_dump_info.addr = addr;
+	etcam_dump_info.tb_width = 3 - etcam_key_mode;
+	etcam_dump_info.rd_mode = rd_mode;
+	etcam_dump_info.tb_depth = 1;
+
+	rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &dump_element_id);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_free_item_get",
+											 dump_info_buff);
+	ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev),
+							  "table up item queue_element_id is: %d.\n",
+							  dump_element_id);
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dump etcam:queue %d,element id: %d\n", queue_id,
+						dump_element_id);
+	}
+
+	rc = dtb_etcam_dump_data_len(dev, etcam_key_mode, &etcam_dump_one_data_len,
+								 &etcam_dump_inerval);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dtb_etcam_dump_data_len",
+											 dump_info_buff);
+
+	// etcam data dump描述符
+	etcam_dump_info.data_or_mask = DPP_ETCAM_DTYPE_DATA;
+	rc = dpp_dtb_tab_up_item_offset_addr_get(dev, queue_id, dump_element_id,
+											 dump_data_len,
+											 &etcam_data_dst_phy_haddr,
+											 &etcam_data_dst_phy_laddr);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+			rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff);
+	rc = dpp_dtb_etcam_dump_entry(dev, &etcam_dump_info,
+								  etcam_data_dst_phy_haddr,
+								  etcam_data_dst_phy_laddr, &dtb_dump_entry);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_etcam_dump_entry",
+											 dump_info_buff);
+
+	rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset,
+							&dtb_dump_entry);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",
+											 dump_info_buff);
+	ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
+	dtb_desc_len += 1;
+	dtb_desc_addr_offset += DTB_LEN_POS_SETP;
+	dump_data_len += etcam_dump_one_data_len;
+
+	// etcam mask dump描述符
+	etcam_dump_info.data_or_mask = DPP_ETCAM_DTYPE_MASK;
+	rc = dpp_dtb_tab_up_item_offset_addr_get(dev, queue_id, dump_element_id,
+											 dump_data_len,
+											 &etcam_mask_dst_phy_haddr,
+											 &etcam_mask_dst_phy_laddr);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+			rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff);
+	rc = dpp_dtb_etcam_dump_entry(dev, &etcam_dump_info,
+								  etcam_mask_dst_phy_haddr,
+								  etcam_mask_dst_phy_laddr, &dtb_dump_entry);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_etcam_dump_entry",
+											 dump_info_buff);
+	rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset,
+							&dtb_dump_entry);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",
+											 dump_info_buff);
+	ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
+	dtb_desc_len += 1;
+	dtb_desc_addr_offset += DTB_LEN_POS_SETP;
+	dump_data_len += etcam_dump_one_data_len;
+
+	//级联数据dump描述符生成
+	if (as_en) {
+		rc = dtb_eram_index_cal(dev, as_rsp_mode, as_eram_index, &row_index,
+								&col_index);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dtb_eram_index_cal",
+												 dump_info_buff);
+
+		eram_dump_base_addr = as_eram_baddr + row_index;
+		ZXIC_COMM_TRACE_INFO("eram_dump_base_addr : 0x%x\n",
+							 eram_dump_base_addr);
+		rc = dpp_dtb_tab_up_item_offset_addr_get(dev, queue_id, dump_element_id,
+												 dump_data_len,
+												 &as_rst_dst_phy_haddr,
+												 &as_rst_dst_phy_laddr);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+				rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff);
+
+		rc = dpp_dtb_smmu0_dump_entry(dev, eram_dump_base_addr, 1,
+									  as_rst_dst_phy_haddr,
+									  as_rst_dst_phy_laddr, &dtb_dump_entry);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_smmu0_dump_entry",
+												 dump_info_buff);
+		rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset,
+								&dtb_dump_entry);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",
+												 dump_info_buff);
+		ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
+		dtb_desc_len += 1;
+		dtb_desc_addr_offset += DTB_LEN_POS_SETP;
+		dump_data_len += DTB_LEN_POS_SETP;
+	}
+
+	//申请data空间
+	temp_dump_out_data =
+			(ZXIC_UINT8 *)ZXIC_COMM_MALLOC(dump_data_len * sizeof(ZXIC_UINT8));
+	ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(temp_dump_out_data,
+												dump_info_buff);
+	ZXIC_COMM_MEMSET(temp_dump_out_data, 0, dump_data_len * sizeof(ZXIC_UINT8));
+	p_data = temp_dump_out_data;
+	/*下发dump描述符*/
+	rc = dpp_dtb_write_dump_desc_info(dev, queue_id, dump_element_id,
+									  (ZXIC_UINT32 *)dump_info_buff,
+									  dump_data_len / 4, dtb_desc_len * 4,
+									  (ZXIC_UINT32 *)temp_dump_out_data);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE2PTR_NO_ASSERT(rc,
+												 "dpp_dtb_write_dump_desc_info",
+												 dump_info_buff,
+												 temp_dump_out_data);
+
+	//解析数据
+	p_data = temp_dump_out_data;
+	p_mask = p_data + etcam_dump_one_data_len;
+
+	rc = dpp_dtb_get_etcam_xy_from_dump_data(dev, p_data, p_mask,
+											 etcam_dump_one_data_len,
+											 etcam_dump_inerval, &entry_xy);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE2PTR_NO_ASSERT(
+			rc, "dpp_dtb_get_etcam_xy_from_dump_data", dump_info_buff,
+			temp_dump_out_data);
+
+	if (opr_type == DPP_ETCAM_OPR_DM) {
+		/* convert hardware data X/Y to user D/M  */
+		rc = dpp_etcam_xy_to_dm(p_entry, &entry_xy,
+								DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE2PTR_NO_ASSERT(
+				rc, "dpp_etcam_xy_to_dm", dump_info_buff, temp_dump_out_data);
+	} else {
+		ZXIC_COMM_MEMCPY(p_entry->p_data, entry_xy.p_data,
+						 DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));
+		ZXIC_COMM_MEMCPY(p_entry->p_mask, entry_xy.p_mask,
+						 DPP_ETCAM_ENTRY_SIZE_GET(p_entry->mode));
+	}
+
+	if (as_en) {
+		//解析dump数据
+		p_rst = p_mask + etcam_dump_one_data_len;
+		ZXIC_COMM_MEMCPY(p_as_rslt, p_rst, (128 / 8));
+	}
+
+	ZXIC_COMM_FREE(dump_info_buff);
+	ZXIC_COMM_FREE(temp_dump_out_data);
+
+	return rc;
 }
 #endif
 
 #if ZXIC_REAL("DTB GET INTERFACE")
 /** dtb dump eram直接表表项内容
-* @param   dev_id       设备号
-* @param   queue_id     队列号
-* @param   sdt_no       eram表sdt表号
-* @param   p_dump_eram_entry  eram数据结构，数据已分配相应内存
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_eram_data_get(DPP_DEV_T *dev, 
-                                 ZXIC_UINT32 queue_id, 
-                                 ZXIC_UINT32 sdt_no, 
-                                 DPP_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry)
+ * @param   dev_id       设备号
+ * @param   queue_id     队列号
+ * @param   sdt_no       eram表sdt表号
+ * @param   p_dump_eram_entry  eram数据结构，数据已分配相应内存
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_eram_data_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								 ZXIC_UINT32 sdt_no,
+								 DPP_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry)
 {
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 rd_mode = 0;
-    ZXIC_UINT32 eram_base_addr = 0;
-    ZXIC_UINT32 eram_table_depth = 0;
-    ZXIC_UINT32 eram_dump_base_addr = 0;
-    ZXIC_UINT32 row_index = 0;
-    ZXIC_UINT32 col_index = 0;
-    ZXIC_UINT32 temp_data[4] = {0};
-    ZXIC_UINT32 element_id = 0;
-
-    ZXIC_UINT32 index = p_dump_eram_entry->index;
-    ZXIC_UINT32 *p_data = p_dump_eram_entry->p_data;
-
-    DPP_SDTTBL_ERAM_T sdt_eram_info = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-
-    //从sdt_no中获取SDT配置
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_eram_info);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
-    eram_base_addr = sdt_eram_info.eram_base_addr;
-    rd_mode = sdt_eram_info.eram_mode;//0:1bit;2:64bit;3:128,
-    eram_table_depth = sdt_eram_info.eram_table_depth;
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), index, 0, eram_table_depth - 1);
-
-    rc = dtb_eram_index_cal(dev, rd_mode, index, &row_index, &col_index);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal");
-
-    eram_dump_base_addr = eram_base_addr + row_index;
-
-    rc = dpp_dtb_se_smmu0_dma_dump(dev, 
-                                queue_id, 
-                                eram_dump_base_addr, 
-                                1,
-                                temp_data,
-                                &element_id);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_se_smmu0_dma_dump");
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dtb dump eram done, the element id is %d.\n", element_id);
-    }
-
-    //提取数据
-    switch (rd_mode)
-    {
-        case ERAM128_TBL_128b:
-        {
-            ZXIC_COMM_MEMCPY(p_data, temp_data, (128 / 8));
-            break;
-        }
-
-        case ERAM128_TBL_64b:
-        {
-            ZXIC_COMM_MEMCPY(p_data, temp_data + ((1 - col_index) << 1), (64 / 8));
-            break;
-        }
-
-        case ERAM128_TBL_1b:
-        {
-            ZXIC_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + (3 - col_index / 32)), (col_index % 32), 1);
-            break;
-        }
-    }
-
-    return rc;
-
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 rd_mode = 0;
+	ZXIC_UINT32 eram_base_addr = 0;
+	ZXIC_UINT32 eram_table_depth = 0;
+	ZXIC_UINT32 eram_dump_base_addr = 0;
+	ZXIC_UINT32 row_index = 0;
+	ZXIC_UINT32 col_index = 0;
+	ZXIC_UINT32 temp_data[4] = { 0 };
+	ZXIC_UINT32 element_id = 0;
+
+	ZXIC_UINT32 index = p_dump_eram_entry->index;
+	ZXIC_UINT32 *p_data = p_dump_eram_entry->p_data;
+
+	DPP_SDTTBL_ERAM_T sdt_eram_info = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+
+	//从sdt_no中获取SDT配置
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_eram_info);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
+	eram_base_addr = sdt_eram_info.eram_base_addr;
+	rd_mode = sdt_eram_info.eram_mode; // 0:1bit;2:64bit;3:128,
+	eram_table_depth = sdt_eram_info.eram_table_depth;
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), index, 0,
+										eram_table_depth - 1);
+
+	rc = dtb_eram_index_cal(dev, rd_mode, index, &row_index, &col_index);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal");
+
+	eram_dump_base_addr = eram_base_addr + row_index;
+
+	rc = dpp_dtb_se_smmu0_dma_dump(dev, queue_id, eram_dump_base_addr, 1,
+								   temp_data, &element_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_se_smmu0_dma_dump");
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dtb dump eram done, the element id is %d.\n",
+						element_id);
+	}
+
+	//提取数据
+	switch (rd_mode) {
+	case ERAM128_TBL_128b: {
+		ZXIC_COMM_MEMCPY(p_data, temp_data, (128 / 8));
+		break;
+	}
+
+	case ERAM128_TBL_64b: {
+		ZXIC_COMM_MEMCPY(p_data, temp_data + ((1 - col_index) << 1), (64 / 8));
+		break;
+	}
+
+	case ERAM128_TBL_1b: {
+		ZXIC_COMM_UINT32_GET_BITS(p_data[0],
+								  *(temp_data + (3 - col_index / 32)),
+								  (col_index % 32), 1);
+		break;
+	}
+	}
+
+	return rc;
 }
 
 /** dtb dump eram直接表表项内容
-* @param   dev_id       设备号
-* @param   queue_id     队列号
-* @param   sdt_no       eram表sdt表号
-* @param   p_dump_eram_entry  eram数据结构，数据已分配相应内存
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_eram_stat_data_get(DPP_DEV_T *dev, 
-                                      ZXIC_UINT32 queue_id, 
-                                      ZXIC_UINT32 base_addr, 
-                                      ZXIC_UINT32 rd_mode, 
-                                      ZXIC_UINT32 index,
-                                      ZXIC_UINT32 *p_data)
+ * @param   dev_id       设备号
+ * @param   queue_id     队列号
+ * @param   sdt_no       eram表sdt表号
+ * @param   p_dump_eram_entry  eram数据结构，数据已分配相应内存
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_eram_stat_data_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									  ZXIC_UINT32 base_addr,
+									  ZXIC_UINT32 rd_mode, ZXIC_UINT32 index,
+									  ZXIC_UINT32 *p_data)
 {
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 eram_dump_base_addr = 0;
-    ZXIC_UINT32 row_index = 0;
-    ZXIC_UINT32 col_index = 0;
-    ZXIC_UINT32 temp_data[4] = {0};
-    ZXIC_UINT32 element_id = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev),p_data);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
-
-    rc = dtb_eram_index_cal(dev, rd_mode, index, &row_index, &col_index);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal");
-
-    eram_dump_base_addr = base_addr + row_index;
-
-    rc = dpp_dtb_se_smmu0_dma_dump(dev, 
-                                queue_id, 
-                                eram_dump_base_addr, 
-                                1,
-                                temp_data,
-                                &element_id);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_se_smmu0_dma_dump");
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dtb dump eram done, the element id is %d.\n", element_id);
-    }
-
-    //提取数据
-    switch (rd_mode)
-    {
-        case ERAM128_TBL_128b:
-        {
-            ZXIC_COMM_MEMCPY(p_data, temp_data, (128 / 8));
-            break;
-        }
-
-        case ERAM128_TBL_64b:
-        {
-            ZXIC_COMM_MEMCPY(p_data, temp_data + ((1 - col_index) << 1), (64 / 8));
-            break;
-        }
-
-        case ERAM128_TBL_1b:
-        {
-            ZXIC_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + (3 - col_index / 32)), (col_index % 32), 1);
-            break;
-        }
-    }
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 eram_dump_base_addr = 0;
+	ZXIC_UINT32 row_index = 0;
+	ZXIC_UINT32 col_index = 0;
+	ZXIC_UINT32 temp_data[4] = { 0 };
+	ZXIC_UINT32 element_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
+
+	rc = dtb_eram_index_cal(dev, rd_mode, index, &row_index, &col_index);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal");
+
+	eram_dump_base_addr = base_addr + row_index;
+
+	rc = dpp_dtb_se_smmu0_dma_dump(dev, queue_id, eram_dump_base_addr, 1,
+								   temp_data, &element_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_se_smmu0_dma_dump");
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dtb dump eram done, the element id is %d.\n",
+						element_id);
+	}
+
+	//提取数据
+	switch (rd_mode) {
+	case ERAM128_TBL_128b: {
+		ZXIC_COMM_MEMCPY(p_data, temp_data, (128 / 8));
+		break;
+	}
+
+	case ERAM128_TBL_64b: {
+		ZXIC_COMM_MEMCPY(p_data, temp_data + ((1 - col_index) << 1), (64 / 8));
+		break;
+	}
+
+	case ERAM128_TBL_1b: {
+		ZXIC_COMM_UINT32_GET_BITS(p_data[0],
+								  *(temp_data + (3 - col_index / 32)),
+								  (col_index % 32), 1);
+		break;
+	}
+	}
+
+	return rc;
 }
 
 /** dtb dump ddr直接表表项内容
-* @param   dev_id       设备号
-* @param   queue_id     队列号
-* @param   sdt_no       eram表sdt表号
-* @param   p_dump_ddr_entry  ddr 数据结构，数据已分配相应内存
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_ddr_data_get(DPP_DEV_T *dev, 
-                                 ZXIC_UINT32 queue_id, 
-                                 ZXIC_UINT32 sdt_no, 
-                                 DPP_DTB_DDR_ENTRY_INFO_T *p_dump_ddr_entry)
+ * @param   dev_id       设备号
+ * @param   queue_id     队列号
+ * @param   sdt_no       eram表sdt表号
+ * @param   p_dump_ddr_entry  ddr 数据结构，数据已分配相应内存
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_ddr_data_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								ZXIC_UINT32 sdt_no,
+								DPP_DTB_DDR_ENTRY_INFO_T *p_dump_ddr_entry)
 {
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 rd_mode = 0;
-    ZXIC_UINT32 ddr_base_addr = 0;
-    ZXIC_UINT32 ddr_dump_base_addr_512bit = 0;
-    ZXIC_UINT32 row_index = 0;
-    ZXIC_UINT32 col_index = 0;
-    ZXIC_UINT32 rd_buff[DPP_DIR_TBL_BUF_MAX_NUM] = {0};
-    ZXIC_UINT32 element_id = 0;
-
-    ZXIC_UINT32 index = p_dump_ddr_entry->index;
-    ZXIC_UINT32 *p_data = p_dump_ddr_entry->p_data;
-
-    DPP_SDTTBL_DDR3_T sdt_ddr_info = {0};  /*SDT内容*/
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_dump_ddr_entry);
-
-    //从sdt_no中获取SDT配置
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_ddr_info);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get");
-    ddr_base_addr = sdt_ddr_info.ddr3_base_addr;
-    ZXIC_COMM_CHECK_INDEX_UPPER(ddr_base_addr,DPP_SMMU1_TOTAL_MAX_BADDR);
-    rd_mode = sdt_ddr_info.ddr3_rw_len;
-
-    if(SMMU1_DDR_SRH_128b == rd_mode)
-    {
-        row_index = index >> 2;
-        col_index = ((index & 0x3)) << 2;
-    }
-    else if(SMMU1_DDR_SRH_256b == rd_mode)
-    {
-        row_index = index >> 1;
-        col_index = ((index & 0x1)) << 3;
-    }
-    else if(SMMU1_DDR_SRH_512b == rd_mode)
-    {
-        row_index = index;
-        col_index = 0;
-    }
-
-    ddr_dump_base_addr_512bit = (ddr_base_addr << 10) + row_index;/**转换成512bit为单位的地址*/
-
-    rc = dpp_dtb_se_smmu1_dma_dump(dev, 
-                                  queue_id, 
-                                  ddr_dump_base_addr_512bit, 
-                                  1,
-                                  rd_buff,
-                                  &element_id);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc,"dpp_dtb_se_smmu1_dma_dump");
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("dump ddr done ,the element is is %d\n",element_id);
-    }
-
-    ZXIC_COMM_MEMCPY((ZXIC_UINT8 *)p_data, rd_buff+col_index, DTB_LEN_POS_SETP << rd_mode);
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 rd_mode = 0;
+	ZXIC_UINT32 ddr_base_addr = 0;
+	ZXIC_UINT32 ddr_dump_base_addr_512bit = 0;
+	ZXIC_UINT32 row_index = 0;
+	ZXIC_UINT32 col_index = 0;
+	ZXIC_UINT32 rd_buff[DPP_DIR_TBL_BUF_MAX_NUM] = { 0 };
+	ZXIC_UINT32 element_id = 0;
+
+	ZXIC_UINT32 index = p_dump_ddr_entry->index;
+	ZXIC_UINT32 *p_data = p_dump_ddr_entry->p_data;
+
+	DPP_SDTTBL_DDR3_T sdt_ddr_info = { 0 }; /*SDT内容*/
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_dump_ddr_entry);
+
+	//从sdt_no中获取SDT配置
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_ddr_info);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get");
+	ddr_base_addr = sdt_ddr_info.ddr3_base_addr;
+	ZXIC_COMM_CHECK_INDEX_UPPER(ddr_base_addr, DPP_SMMU1_TOTAL_MAX_BADDR);
+	rd_mode = sdt_ddr_info.ddr3_rw_len;
+
+	if (SMMU1_DDR_SRH_128b == rd_mode) {
+		row_index = index >> 2;
+		col_index = ((index & 0x3)) << 2;
+	} else if (SMMU1_DDR_SRH_256b == rd_mode) {
+		row_index = index >> 1;
+		col_index = ((index & 0x1)) << 3;
+	} else if (SMMU1_DDR_SRH_512b == rd_mode) {
+		row_index = index;
+		col_index = 0;
+	}
+
+	ddr_dump_base_addr_512bit =
+			(ddr_base_addr << 10) + row_index; /**转换成512bit为单位的地址*/
+
+	rc = dpp_dtb_se_smmu1_dma_dump(dev, queue_id, ddr_dump_base_addr_512bit, 1,
+								   rd_buff, &element_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_se_smmu1_dma_dump");
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("dump ddr done ,the element is is %d\n", element_id);
+	}
+
+	ZXIC_COMM_MEMCPY((ZXIC_UINT8 *)p_data, rd_buff + col_index,
+					 DTB_LEN_POS_SETP << rd_mode);
+
+	return rc;
 }
 
-
 /** 根据键值查找hash表
-* @param   dev_id       设备号，支持多芯片 
-* @param   queue_id     队列id 
-* @param   sdt_no       0~255 
-* @param   p_dtb_hash_entry    出参，返回描述符信息
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-ZXIC_UINT32 dpp_dtb_hash_data_get(DPP_DEV_T *dev, 
-                                ZXIC_UINT32 queue_id,
-                                ZXIC_UINT32 sdt_no,
-                                DPP_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry)
+ * @param   dev_id       设备号，支持多芯片
+ * @param   queue_id     队列id
+ * @param   sdt_no       0~255
+ * @param   p_dtb_hash_entry    出参，返回描述符信息
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/02
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_hash_data_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								  ZXIC_UINT32 sdt_no,
+								  DPP_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT8 srh_succ = 0;
-    ZXIC_UINT8 key_valid = 1;
-    DPP_SE_CFG *p_se_cfg = NULL;
-    FUNC_ID_INFO *p_func_info = NULL;
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    HASH_ENTRY_CFG  hash_entry_cfg = {0}; 
-    DPP_SDTTBL_HASH_T sdt_hash_info = {0};  /*SDT内容*/
-    DPP_HASH_ENTRY hash_entry = {0};
-    ZXIC_UINT8 aucKey[HASH_KEY_MAX] = {0};
-    ZXIC_UINT8 aucRst[HASH_RST_MAX] = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_POINT(p_dtb_hash_entry);
-    ZXIC_COMM_CHECK_POINT(p_dtb_hash_entry->p_actu_key);
-    ZXIC_COMM_CHECK_POINT(p_dtb_hash_entry->p_rst);
-
-    ZXIC_COMM_MEMSET(&hash_entry,0x0,sizeof(DPP_HASH_ENTRY));
-
-    //从sdt_no中获取SDT配置
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
-
-    hash_entry_cfg.fun_id   = sdt_hash_info.hash_id; /*hash引擎*/
-    hash_entry_cfg.table_id = sdt_hash_info.hash_table_id; /*hash表号*/
-    hash_entry_cfg.bulk_id = ((hash_entry_cfg.table_id >> 2) & 0x7);
-    hash_entry_cfg.key_type = sdt_hash_info.hash_table_width; /*表宽度*/
-    hash_entry_cfg.actu_key_size = sdt_hash_info.key_size; /*业务表键值长度*/
-    hash_entry_cfg.key_by_size = DPP_GET_KEY_SIZE(hash_entry_cfg.actu_key_size);
-    hash_entry_cfg.rst_by_size = DPP_GET_RST_SIZE(hash_entry_cfg.key_type, hash_entry_cfg.actu_key_size);
-
-     /* 取出se配置 */
-    rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_cfg_get");
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg);
-    p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_entry_cfg.fun_id);
-    DPP_SE_CHECK_FUN(p_func_info, hash_entry_cfg.fun_id, FUN_HASH);
-    hash_entry_cfg.p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_entry_cfg.p_hash_cfg);
-    p_hash_cfg = hash_entry_cfg.p_hash_cfg;
-    ZXIC_COMM_CHECK_POINT(p_hash_cfg);
-
-    hash_entry.p_key = aucKey;
-    hash_entry.p_rst = aucRst;
-    ZXIC_COMM_MEMSET(hash_entry.p_key,0x0,sizeof(aucKey));
-    ZXIC_COMM_MEMSET(hash_entry.p_rst,0x0,sizeof(aucRst));
-    hash_entry.p_key[0] = DPP_GET_HASH_KEY_CTRL(key_valid, 
-                                            hash_entry_cfg.key_type, 
-                                            hash_entry_cfg.table_id);
-    ZXIC_COMM_MEMCPY(&hash_entry.p_key[1],p_dtb_hash_entry->p_actu_key,hash_entry_cfg.actu_key_size);
-   
-    if(p_hash_cfg->ddr_valid)
-    {
-        rc  = dpp_dtb_hash_ddr_get(dev,queue_id,&hash_entry_cfg,&hash_entry,&srh_succ);  
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_hash_ddr_get");
-    }
-
-    if(!srh_succ)
-    {
-        rc  = dpp_dtb_hash_zcam_get(dev,queue_id,&hash_entry_cfg,&hash_entry,&srh_succ);  
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_dtb_hash_zcam_get"); 
-    }
-
-    if(!srh_succ)
-    {
-        p_hash_cfg->hash_stat.search_fail++;
-        ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "Hash search key fail!\n");
-        return DPP_HASH_RC_SRH_FAIL;
-    }
-
-    ZXIC_COMM_MEMCPY(p_dtb_hash_entry->p_rst,hash_entry.p_rst,1<<(sdt_hash_info.rsp_mode + 2));
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT8 srh_succ = 0;
+	ZXIC_UINT8 key_valid = 1;
+	DPP_SE_CFG *p_se_cfg = NULL;
+	FUNC_ID_INFO *p_func_info = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	HASH_ENTRY_CFG hash_entry_cfg = { 0 };
+	DPP_SDTTBL_HASH_T sdt_hash_info = { 0 }; /*SDT内容*/
+	DPP_HASH_ENTRY hash_entry = { 0 };
+	ZXIC_UINT8 aucKey[HASH_KEY_MAX] = { 0 };
+	ZXIC_UINT8 aucRst[HASH_RST_MAX] = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(p_dtb_hash_entry);
+	ZXIC_COMM_CHECK_POINT(p_dtb_hash_entry->p_actu_key);
+	ZXIC_COMM_CHECK_POINT(p_dtb_hash_entry->p_rst);
+
+	ZXIC_COMM_MEMSET(&hash_entry, 0x0, sizeof(DPP_HASH_ENTRY));
+
+	//从sdt_no中获取SDT配置
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
+
+	hash_entry_cfg.fun_id = sdt_hash_info.hash_id; /*hash引擎*/
+	hash_entry_cfg.table_id = sdt_hash_info.hash_table_id; /*hash表号*/
+	hash_entry_cfg.bulk_id = ((hash_entry_cfg.table_id >> 2) & 0x7);
+	hash_entry_cfg.key_type = sdt_hash_info.hash_table_width; /*表宽度*/
+	hash_entry_cfg.actu_key_size = sdt_hash_info.key_size; /*业务表键值长度*/
+	hash_entry_cfg.key_by_size = DPP_GET_KEY_SIZE(hash_entry_cfg.actu_key_size);
+	hash_entry_cfg.rst_by_size = DPP_GET_RST_SIZE(hash_entry_cfg.key_type,
+												  hash_entry_cfg.actu_key_size);
+
+	/* 取出se配置 */
+	rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_cfg_get");
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg);
+	p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_entry_cfg.fun_id);
+	DPP_SE_CHECK_FUN(p_func_info, hash_entry_cfg.fun_id, FUN_HASH);
+	hash_entry_cfg.p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), hash_entry_cfg.p_hash_cfg);
+	p_hash_cfg = hash_entry_cfg.p_hash_cfg;
+	ZXIC_COMM_CHECK_POINT(p_hash_cfg);
+
+	hash_entry.p_key = aucKey;
+	hash_entry.p_rst = aucRst;
+	ZXIC_COMM_MEMSET(hash_entry.p_key, 0x0, sizeof(aucKey));
+	ZXIC_COMM_MEMSET(hash_entry.p_rst, 0x0, sizeof(aucRst));
+	hash_entry.p_key[0] = DPP_GET_HASH_KEY_CTRL(
+			key_valid, hash_entry_cfg.key_type, hash_entry_cfg.table_id);
+	ZXIC_COMM_MEMCPY(&hash_entry.p_key[1], p_dtb_hash_entry->p_actu_key,
+					 hash_entry_cfg.actu_key_size);
+
+	if (p_hash_cfg->ddr_valid) {
+		rc = dpp_dtb_hash_ddr_get(dev, queue_id, &hash_entry_cfg, &hash_entry,
+								  &srh_succ);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_dtb_hash_ddr_get");
+	}
+
+	if (!srh_succ) {
+		rc = dpp_dtb_hash_zcam_get(dev, queue_id, &hash_entry_cfg, &hash_entry,
+								   &srh_succ);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_dtb_hash_zcam_get");
+	}
+
+	if (!srh_succ) {
+		p_hash_cfg->hash_stat.search_fail++;
+		ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "Hash search key fail!\n");
+		return DPP_HASH_RC_SRH_FAIL;
+	}
+
+	ZXIC_COMM_MEMCPY(p_dtb_hash_entry->p_rst, hash_entry.p_rst,
+					 1 << (sdt_hash_info.rsp_mode + 2));
+
+	return DPP_OK;
 }
 
 /** dtb 通过key和mask获取ACL表级联结果
-* @param   dev_id       设备号
-* @param   queue_id     队列号
-* @param   sdt_no       eram表sdt表号
-* @param   p_dump_acl_entry  etcam 数据结构，数据已分配相应内存,需要输入key和mask
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_acl_data_get(DPP_DEV_T *dev,
-                                ZXIC_UINT32 queue_id, 
-                                ZXIC_UINT32 sdt_no, 
-                                DPP_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry)
+ * @param   dev_id       设备号
+ * @param   queue_id     队列号
+ * @param   sdt_no       eram表sdt表号
+ * @param   p_dump_acl_entry  etcam 数据结构，数据已分配相应内存,需要输入key和mask
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_acl_data_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								ZXIC_UINT32 sdt_no,
+								DPP_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry)
 {
-    DPP_STATUS  rc = DPP_OK;
-
-    ZXIC_UINT32 block_idx = 0;
-    ZXIC_UINT32 ram_addr = 0;
-    ZXIC_UINT32 etcam_wr_mode = 0;
-
-    ZXIC_UINT32 etcam_key_mode = 0;
-    ZXIC_UINT32 etcam_table_id = 0;
-    ZXIC_UINT32 as_enable = 0;
-    ZXIC_UINT32 as_eram_baddr = 0;
-    ZXIC_UINT32 etcam_as_mode = 0;
-
-    ZXIC_UINT32 row_index = 0;
-    ZXIC_UINT32 col_index = 0;
-
-    DPP_ETCAM_ENTRY_T etcam_entry_dm = {0};
-    DPP_ETCAM_ENTRY_T etcam_entry_xy = {0};
-    ZXIC_UINT32 as_eram_data[4] = {0};
-    ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-
-    DPP_ACL_CFG_EX_T *p_acl_cfg = NULL;
-    DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL;
-
-    DPP_SDTTBL_ETCAM_T sdt_etcam_info = {0};  /*SDT内容*/
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->key_data);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->key_mask);
-
-    //从sdt_no中获取SDT配置
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get");
-    etcam_key_mode = sdt_etcam_info.etcam_key_mode;
-    etcam_as_mode = sdt_etcam_info.as_rsp_mode;
-    etcam_table_id = sdt_etcam_info.etcam_table_id;
-    as_enable = sdt_etcam_info.as_en;
-    as_eram_baddr = sdt_etcam_info.as_eram_baddr;
-
-    if(as_enable)
-    {
-        ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->p_as_rslt); 
-    }
-
-    etcam_entry_xy.mode = etcam_key_mode;
-    etcam_entry_xy.p_data = temp_data;
-    etcam_entry_xy.p_mask = temp_mask;
-    etcam_entry_dm.mode = etcam_key_mode;
-    etcam_entry_dm.p_data = p_dump_acl_entry->key_data;
-    etcam_entry_dm.p_mask = p_dump_acl_entry->key_mask;
-
-    if(dpp_dtb_prt_get())
-    {
-        ZXIC_COMM_PRINT("acl get DM:/n");
-        dpp_acl_data_print(etcam_entry_dm.p_data, etcam_entry_dm.p_mask,  etcam_entry_dm.mode);
-    }
-
-    dpp_acl_cfg_get(&p_acl_cfg);//获取ACL表资源配置
-    ZXIC_COMM_CHECK_POINT(p_acl_cfg);
-
-    p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id;//得到该acl表的资源配置
-
-    if (!p_tbl_cfg->is_used)
-    {
-        ZXIC_COMM_TRACE_ERROR("table[ %d ] is not init!\n", etcam_table_id);
-        ZXIC_COMM_ASSERT(0);
-        return DPP_ACL_RC_TBL_NOT_INIT;
-    }
-
-    /*计算地址等信息*/
-    rc = dpp_acl_hdw_addr_get(p_tbl_cfg, p_dump_acl_entry->handle, &block_idx, &ram_addr, &etcam_wr_mode);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_acl_hdw_addr_get");
-
-    rc = dpp_dtb_etcam_entry_get(dev, 
-                                 queue_id,
-                                 block_idx, 
-                                 ram_addr,
-                                 etcam_wr_mode,
-                                 DPP_ETCAM_OPR_XY, 
-                                 as_enable,
-                                 as_eram_baddr,
-                                 p_dump_acl_entry->handle,
-                                 etcam_as_mode,//128:3   64:2
-                                 &etcam_entry_xy,
-                                 (ZXIC_UINT8 *)as_eram_data);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_etcam_entry_get");
-
-    if (dpp_etcam_entry_cmp(&etcam_entry_dm, &etcam_entry_xy) == 0)
-    {
-        ZXIC_COMM_PRINT("Acl table[ %d ] search in hardware success: handle[ 0x%x ], block[ %d ], ram_addr[ %d ], rd_mode[ %x ].\n",
-                    p_tbl_cfg->table_id, p_dump_acl_entry->handle, block_idx, ram_addr, etcam_wr_mode);
-    }
-    else
-    {
-        ZXIC_COMM_PRINT("Acl table[ %d ] search in hardware fail: handle[ 0x%x ], block[ %d ], ram_addr[ %d ], rd_mode[ %x ].\n",
-                    p_tbl_cfg->table_id, p_dump_acl_entry->handle, block_idx, ram_addr, etcam_wr_mode);
-
-        return DPP_ERR;
-    }
-
-    if(as_enable)
-    {
-        rc = dtb_eram_index_cal(dev, etcam_as_mode, p_dump_acl_entry->handle, &row_index, &col_index);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal");
-        switch (etcam_as_mode)
-        {
-            case ERAM128_TBL_128b:
-            {
-                ZXIC_COMM_MEMCPY(p_dump_acl_entry->p_as_rslt, as_eram_data, (128 / 8));
-                break;
-            }
-
-            case ERAM128_TBL_64b:
-            {
-                ZXIC_COMM_MEMCPY(p_dump_acl_entry->p_as_rslt, as_eram_data + ((1 - col_index) << 1), (64 / 8));
-                break;
-            }
-
-            case ERAM128_TBL_1b:
-            {
-                ZXIC_COMM_UINT32_GET_BITS(*(ZXIC_UINT32 *)p_dump_acl_entry->p_as_rslt, *(as_eram_data + (3 - col_index / 32)), (col_index % 32), 1);
-                break;
-            }
-        }
-    }
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 block_idx = 0;
+	ZXIC_UINT32 ram_addr = 0;
+	ZXIC_UINT32 etcam_wr_mode = 0;
+
+	ZXIC_UINT32 etcam_key_mode = 0;
+	ZXIC_UINT32 etcam_table_id = 0;
+	ZXIC_UINT32 as_enable = 0;
+	ZXIC_UINT32 as_eram_baddr = 0;
+	ZXIC_UINT32 etcam_as_mode = 0;
+
+	ZXIC_UINT32 row_index = 0;
+	ZXIC_UINT32 col_index = 0;
+
+	DPP_ETCAM_ENTRY_T etcam_entry_dm = { 0 };
+	DPP_ETCAM_ENTRY_T etcam_entry_xy = { 0 };
+	ZXIC_UINT32 as_eram_data[4] = { 0 };
+	ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+
+	DPP_ACL_CFG_EX_T *p_acl_cfg = NULL;
+	DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL;
+
+	DPP_SDTTBL_ETCAM_T sdt_etcam_info = { 0 }; /*SDT内容*/
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->key_data);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->key_mask);
+
+	//从sdt_no中获取SDT配置
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get");
+	etcam_key_mode = sdt_etcam_info.etcam_key_mode;
+	etcam_as_mode = sdt_etcam_info.as_rsp_mode;
+	etcam_table_id = sdt_etcam_info.etcam_table_id;
+	as_enable = sdt_etcam_info.as_en;
+	as_eram_baddr = sdt_etcam_info.as_eram_baddr;
+
+	if (as_enable) {
+		ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->p_as_rslt);
+	}
+
+	etcam_entry_xy.mode = etcam_key_mode;
+	etcam_entry_xy.p_data = temp_data;
+	etcam_entry_xy.p_mask = temp_mask;
+	etcam_entry_dm.mode = etcam_key_mode;
+	etcam_entry_dm.p_data = p_dump_acl_entry->key_data;
+	etcam_entry_dm.p_mask = p_dump_acl_entry->key_mask;
+
+	if (dpp_dtb_prt_get()) {
+		ZXIC_COMM_PRINT("acl get DM:/n");
+		dpp_acl_data_print(etcam_entry_dm.p_data, etcam_entry_dm.p_mask,
+						   etcam_entry_dm.mode);
+	}
+
+	dpp_acl_cfg_get(&p_acl_cfg); //获取ACL表资源配置
+	ZXIC_COMM_CHECK_POINT(p_acl_cfg);
+
+	p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; //得到该acl表的资源配置
+
+	if (!p_tbl_cfg->is_used) {
+		ZXIC_COMM_TRACE_ERROR("table[ %d ] is not init!\n", etcam_table_id);
+		ZXIC_COMM_ASSERT(0);
+		return DPP_ACL_RC_TBL_NOT_INIT;
+	}
+
+	/*计算地址等信息*/
+	rc = dpp_acl_hdw_addr_get(p_tbl_cfg, p_dump_acl_entry->handle, &block_idx,
+							  &ram_addr, &etcam_wr_mode);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_acl_hdw_addr_get");
+
+	rc = dpp_dtb_etcam_entry_get(dev, queue_id, block_idx, ram_addr,
+								 etcam_wr_mode, DPP_ETCAM_OPR_XY, as_enable,
+								 as_eram_baddr, p_dump_acl_entry->handle,
+								 etcam_as_mode, // 128:3   64:2
+								 &etcam_entry_xy, (ZXIC_UINT8 *)as_eram_data);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_etcam_entry_get");
+
+	if (dpp_etcam_entry_cmp(&etcam_entry_dm, &etcam_entry_xy) == 0) {
+		ZXIC_COMM_PRINT(
+				"Acl table[ %d ] search in hardware success: handle[ 0x%x ], block[ %d ], ram_addr[ %d ], rd_mode[ %x ].\n",
+				p_tbl_cfg->table_id, p_dump_acl_entry->handle, block_idx,
+				ram_addr, etcam_wr_mode);
+	} else {
+		ZXIC_COMM_PRINT(
+				"Acl table[ %d ] search in hardware fail: handle[ 0x%x ], block[ %d ], ram_addr[ %d ], rd_mode[ %x ].\n",
+				p_tbl_cfg->table_id, p_dump_acl_entry->handle, block_idx,
+				ram_addr, etcam_wr_mode);
+
+		return DPP_ERR;
+	}
+
+	if (as_enable) {
+		rc = dtb_eram_index_cal(dev, etcam_as_mode, p_dump_acl_entry->handle,
+								&row_index, &col_index);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal");
+		switch (etcam_as_mode) {
+		case ERAM128_TBL_128b: {
+			ZXIC_COMM_MEMCPY(p_dump_acl_entry->p_as_rslt, as_eram_data,
+							 (128 / 8));
+			break;
+		}
+
+		case ERAM128_TBL_64b: {
+			ZXIC_COMM_MEMCPY(p_dump_acl_entry->p_as_rslt,
+							 as_eram_data + ((1 - col_index) << 1), (64 / 8));
+			break;
+		}
+
+		case ERAM128_TBL_1b: {
+			ZXIC_COMM_UINT32_GET_BITS(
+					*(ZXIC_UINT32 *)p_dump_acl_entry->p_as_rslt,
+					*(as_eram_data + (3 - col_index / 32)), (col_index % 32),
+					1);
+			break;
+		}
+		}
+	}
+
+	return rc;
 }
 
 /** dtb etcam 数据get接口，通过handle值获取etcam数据
-* @param   dev_id       设备号
-* @param   queue_id     队列号
-* @param   sdt_no       eram表sdt表号
-* @param   p_dump_acl_entry  etcam 数据结构，数据已分配相应内存
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_etcam_data_get(DPP_DEV_T *dev,
-                                  ZXIC_UINT32 queue_id, 
-                                  ZXIC_UINT32 sdt_no, 
-                                  DPP_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry)
+ * @param   dev_id       设备号
+ * @param   queue_id     队列号
+ * @param   sdt_no       eram表sdt表号
+ * @param   p_dump_acl_entry  etcam 数据结构，数据已分配相应内存
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_etcam_data_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								  ZXIC_UINT32 sdt_no,
+								  DPP_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry)
 {
-    DPP_STATUS  rc = DPP_OK;
-
-    ZXIC_UINT32 block_idx = 0;
-    ZXIC_UINT32 ram_addr = 0;
-    ZXIC_UINT32 etcam_wr_mode = 0;
-
-    ZXIC_UINT32 etcam_key_mode = 0;
-    ZXIC_UINT32 etcam_table_id = 0;
-    ZXIC_UINT32 as_enable = 0;
-    ZXIC_UINT32 as_eram_baddr = 0;
-    ZXIC_UINT32 etcam_as_mode = 0;
-
-    ZXIC_UINT32 row_index = 0;
-    ZXIC_UINT32 col_index = 0;
-
-    DPP_ETCAM_ENTRY_T etcam_entry_dm = {0};
-    ZXIC_UINT32 as_eram_data[4] = {0};
-
-    ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-
-    DPP_ACL_CFG_EX_T *p_acl_cfg = NULL;
-    DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL;
-
-    DPP_SDTTBL_ETCAM_T sdt_etcam_info = {0};  /*SDT内容*/
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->key_data);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->key_mask);
-
-    //从sdt_no中获取SDT配置
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get");
-    etcam_key_mode = sdt_etcam_info.etcam_key_mode;
-    etcam_as_mode = sdt_etcam_info.as_rsp_mode;
-    etcam_table_id = sdt_etcam_info.etcam_table_id;
-    as_enable = sdt_etcam_info.as_en;
-    as_eram_baddr = sdt_etcam_info.as_eram_baddr;
-
-    if(as_enable)
-    {
-        ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->p_as_rslt); 
-    }
-
-    etcam_entry_dm.mode = etcam_key_mode;
-    etcam_entry_dm.p_data = temp_data;
-    etcam_entry_dm.p_mask = temp_mask;
-
-    dpp_acl_cfg_get(&p_acl_cfg);//获取ACL表资源配置
-    ZXIC_COMM_CHECK_POINT(p_acl_cfg);
-
-    p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id;//得到该acl表的资源配置
-
-    if (!p_tbl_cfg->is_used)
-    {
-        ZXIC_COMM_TRACE_ERROR("table[ %d ] is not init!\n", etcam_table_id);
-        ZXIC_COMM_ASSERT(0);
-        return DPP_ACL_RC_TBL_NOT_INIT;
-    }
-
-    /*计算地址等信息*/
-    rc = dpp_acl_hdw_addr_get(p_tbl_cfg, p_dump_acl_entry->handle, &block_idx, &ram_addr, &etcam_wr_mode);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_acl_hdw_addr_get");
-
-    rc = dpp_dtb_etcam_entry_get(dev, 
-                                 queue_id,
-                                 block_idx, 
-                                 ram_addr,
-                                 etcam_wr_mode,
-                                 DPP_ETCAM_OPR_DM, 
-                                 as_enable,
-                                 as_eram_baddr,
-                                 p_dump_acl_entry->handle,
-                                 etcam_as_mode,//128:3   64:2
-                                 &etcam_entry_dm,
-                                 (ZXIC_UINT8 *)as_eram_data);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_etcam_entry_get");
-
-    ZXIC_COMM_MEMCPY(p_dump_acl_entry->key_data, etcam_entry_dm.p_data, DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode));
-    ZXIC_COMM_MEMCPY(p_dump_acl_entry->key_mask, etcam_entry_dm.p_mask, DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode));
-
-    if(as_enable)
-    {
-        rc = dtb_eram_index_cal(dev, etcam_as_mode, p_dump_acl_entry->handle, &row_index, &col_index);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal");
-        switch (etcam_as_mode)
-        {
-            case ERAM128_TBL_128b:
-            {
-                ZXIC_COMM_MEMCPY(p_dump_acl_entry->p_as_rslt, as_eram_data, (128 / 8));
-                break;
-            }
-
-            case ERAM128_TBL_64b:
-            {
-                ZXIC_COMM_MEMCPY(p_dump_acl_entry->p_as_rslt, as_eram_data + ((1 - col_index) << 1), (64 / 8));
-                break;
-            }
-
-            case ERAM128_TBL_1b:
-            {
-                ZXIC_COMM_UINT32_GET_BITS(*(ZXIC_UINT32 *)p_dump_acl_entry->p_as_rslt, *(as_eram_data + (3 - col_index / 32)), (col_index % 32), 1);
-                break;
-            }
-        }
-    }
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 block_idx = 0;
+	ZXIC_UINT32 ram_addr = 0;
+	ZXIC_UINT32 etcam_wr_mode = 0;
+
+	ZXIC_UINT32 etcam_key_mode = 0;
+	ZXIC_UINT32 etcam_table_id = 0;
+	ZXIC_UINT32 as_enable = 0;
+	ZXIC_UINT32 as_eram_baddr = 0;
+	ZXIC_UINT32 etcam_as_mode = 0;
+
+	ZXIC_UINT32 row_index = 0;
+	ZXIC_UINT32 col_index = 0;
+
+	DPP_ETCAM_ENTRY_T etcam_entry_dm = { 0 };
+	ZXIC_UINT32 as_eram_data[4] = { 0 };
+
+	ZXIC_UINT8 temp_data[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	ZXIC_UINT8 temp_mask[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+
+	DPP_ACL_CFG_EX_T *p_acl_cfg = NULL;
+	DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL;
+
+	DPP_SDTTBL_ETCAM_T sdt_etcam_info = { 0 }; /*SDT内容*/
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->key_data);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->key_mask);
+
+	//从sdt_no中获取SDT配置
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get");
+	etcam_key_mode = sdt_etcam_info.etcam_key_mode;
+	etcam_as_mode = sdt_etcam_info.as_rsp_mode;
+	etcam_table_id = sdt_etcam_info.etcam_table_id;
+	as_enable = sdt_etcam_info.as_en;
+	as_eram_baddr = sdt_etcam_info.as_eram_baddr;
+
+	if (as_enable) {
+		ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_dump_acl_entry->p_as_rslt);
+	}
+
+	etcam_entry_dm.mode = etcam_key_mode;
+	etcam_entry_dm.p_data = temp_data;
+	etcam_entry_dm.p_mask = temp_mask;
+
+	dpp_acl_cfg_get(&p_acl_cfg); //获取ACL表资源配置
+	ZXIC_COMM_CHECK_POINT(p_acl_cfg);
+
+	p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; //得到该acl表的资源配置
+
+	if (!p_tbl_cfg->is_used) {
+		ZXIC_COMM_TRACE_ERROR("table[ %d ] is not init!\n", etcam_table_id);
+		ZXIC_COMM_ASSERT(0);
+		return DPP_ACL_RC_TBL_NOT_INIT;
+	}
+
+	/*计算地址等信息*/
+	rc = dpp_acl_hdw_addr_get(p_tbl_cfg, p_dump_acl_entry->handle, &block_idx,
+							  &ram_addr, &etcam_wr_mode);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_acl_hdw_addr_get");
+
+	rc = dpp_dtb_etcam_entry_get(dev, queue_id, block_idx, ram_addr,
+								 etcam_wr_mode, DPP_ETCAM_OPR_DM, as_enable,
+								 as_eram_baddr, p_dump_acl_entry->handle,
+								 etcam_as_mode, // 128:3   64:2
+								 &etcam_entry_dm, (ZXIC_UINT8 *)as_eram_data);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_etcam_entry_get");
+
+	ZXIC_COMM_MEMCPY(p_dump_acl_entry->key_data, etcam_entry_dm.p_data,
+					 DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode));
+	ZXIC_COMM_MEMCPY(p_dump_acl_entry->key_mask, etcam_entry_dm.p_mask,
+					 DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode));
+
+	if (as_enable) {
+		rc = dtb_eram_index_cal(dev, etcam_as_mode, p_dump_acl_entry->handle,
+								&row_index, &col_index);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal");
+		switch (etcam_as_mode) {
+		case ERAM128_TBL_128b: {
+			ZXIC_COMM_MEMCPY(p_dump_acl_entry->p_as_rslt, as_eram_data,
+							 (128 / 8));
+			break;
+		}
+
+		case ERAM128_TBL_64b: {
+			ZXIC_COMM_MEMCPY(p_dump_acl_entry->p_as_rslt,
+							 as_eram_data + ((1 - col_index) << 1), (64 / 8));
+			break;
+		}
+
+		case ERAM128_TBL_1b: {
+			ZXIC_COMM_UINT32_GET_BITS(
+					*(ZXIC_UINT32 *)p_dump_acl_entry->p_as_rslt,
+					*(as_eram_data + (3 - col_index / 32)), (col_index % 32),
+					1);
+			break;
+		}
+		}
+	}
+
+	return rc;
 }
 
-
 #endif /**DTB GET INTERFACE*/
 
 #if ZXIC_REAL("DTB FLUSH INTERFACE")
 
 /***********************************************************/
-/** DTB dd  整个流表清空Flush 
-* @param   dev_id          设备号
-* @param   queue_id        队列号
-* @param   ddr_base_addr   ddr基地址，以4K*128bit为单位
-* @param   ddr_wr_mode     ddr写模式 0-128bit, 1-256bit, 2-384bit, 3-512bit,取值参考SMMU1_DDR_WRT_MODE_E的定义
-* @param   ddr_ecc_en      ddr ECC使能
-* @param   start_index     flush开始的条目
-* @param   entry_num       下发的条目数
-* @param   element_id      返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/  
-DPP_STATUS dpp_dtb_smmu1_flush_cycle(DPP_DEV_T *dev, 
-                                     ZXIC_UINT32 queue_id, 
-                                     ZXIC_UINT32 ddr_base_addr, 
-                                     ZXIC_UINT32 ddr_wr_mode, 
-                                     ZXIC_UINT32 ddr_ecc_en,
-                                     ZXIC_UINT32 start_index,
-                                     ZXIC_UINT32 entry_num, 
-                                     ZXIC_UINT32 *element_id)
+/** DTB dd  整个流表清空Flush
+ * @param   dev_id          设备号
+ * @param   queue_id        队列号
+ * @param   ddr_base_addr   ddr基地址，以4K*128bit为单位
+ * @param   ddr_wr_mode     ddr写模式 0-128bit, 1-256bit, 2-384bit, 3-512bit,取值参考SMMU1_DDR_WRT_MODE_E的定义
+ * @param   ddr_ecc_en      ddr ECC使能
+ * @param   start_index     flush开始的条目
+ * @param   entry_num       下发的条目数
+ * @param   element_id      返回下表使用的元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/07/03
+ ************************************************************/
+DPP_STATUS
+dpp_dtb_smmu1_flush_cycle(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+						  ZXIC_UINT32 ddr_base_addr, ZXIC_UINT32 ddr_wr_mode,
+						  ZXIC_UINT32 ddr_ecc_en, ZXIC_UINT32 start_index,
+						  ZXIC_UINT32 entry_num, ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS  rc = DPP_OK;
+	DPP_STATUS rc = DPP_OK;
 
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT32 current_index = 0;
-    ZXIC_UINT32 ddr_entry_len = 0;
-    ZXIC_UINT32 *data_buff = NULL;
-    DPP_DTB_DDR_ENTRY_INFO_T *p_entry_arr = NULL;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 current_index = 0;
+	ZXIC_UINT32 ddr_entry_len = 0;
+	ZXIC_UINT32 *data_buff = NULL;
+	DPP_DTB_DDR_ENTRY_INFO_T *p_entry_arr = NULL;
 
-    ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(dev);
 
-    ddr_entry_len = 4 * (ddr_wr_mode + 1);//计算数据长度
+	ddr_entry_len = 4 * (ddr_wr_mode + 1); //计算数据长度
 
-    p_entry_arr = (DPP_DTB_DDR_ENTRY_INFO_T *)ZXIC_COMM_MALLOC(entry_num * sizeof(DPP_DTB_DDR_ENTRY_INFO_T));
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_arr);
+	p_entry_arr = (DPP_DTB_DDR_ENTRY_INFO_T *)ZXIC_COMM_MALLOC(
+			entry_num * sizeof(DPP_DTB_DDR_ENTRY_INFO_T));
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_arr);
 
-    data_buff = (ZXIC_UINT32 *)ZXIC_COMM_MALLOC(ddr_entry_len * sizeof(ZXIC_UINT32));
-    ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE_NO_ASSERT(DEV_ID(dev), data_buff, p_entry_arr);
+	data_buff = (ZXIC_UINT32 *)ZXIC_COMM_MALLOC(ddr_entry_len *
+												sizeof(ZXIC_UINT32));
+	ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE_NO_ASSERT(DEV_ID(dev), data_buff,
+													p_entry_arr);
 
-    ZXIC_COMM_MEMSET(data_buff, 0, ddr_entry_len * sizeof(ZXIC_UINT32));
+	ZXIC_COMM_MEMSET(data_buff, 0, ddr_entry_len * sizeof(ZXIC_UINT32));
 
-    // 下表数据准备
-    for(index = 0; index < entry_num; index++)
-    {
-        current_index = start_index + index;
+	// 下表数据准备
+	for (index = 0; index < entry_num; index++) {
+		current_index = start_index + index;
 
-        p_entry_arr[index].index = current_index;
-        p_entry_arr[index].p_data = data_buff;
-    }
+		p_entry_arr[index].index = current_index;
+		p_entry_arr[index].p_data = data_buff;
+	}
 
-    rc = dpp_dtb_smmu1_data_write_cycle(dev, 
-                                        queue_id, 
-                                        ddr_base_addr, 
-                                        ddr_wr_mode, 
-                                        ddr_ecc_en,
-                                        entry_num, 
-                                        p_entry_arr,
-                                        element_id);
-    ZXIC_COMM_FREE(data_buff);
-    ZXIC_COMM_FREE(p_entry_arr);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_data_write_cycle");
+	rc = dpp_dtb_smmu1_data_write_cycle(dev, queue_id, ddr_base_addr,
+										ddr_wr_mode, ddr_ecc_en, entry_num,
+										p_entry_arr, element_id);
+	ZXIC_COMM_FREE(data_buff);
+	ZXIC_COMM_FREE(p_entry_arr);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_data_write_cycle");
 
-    return rc;
+	return rc;
 }
 
 /***********************************************************/
-/** DTB dd  整个流表清空Flush 
-* @param   dev_id          设备号
-* @param   queue_id        队列号
-* @param   ddr_base_addr   ddr基地址，以4K*128bit为单位
-* @param   ddr_wr_mode     ddr写模式 0-128bit, 1-256bit, 2-384bit, 3-512bit,取值参考SMMU1_DDR_WRT_MODE_E的定义
-* @param   ddr_ecc_en      ddr ECC使能
-* @param   start_index     flush开始的条目
-* @param   entry_num       下发的条目数
-* @param   element_id      返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/  
-DPP_STATUS dpp_dtb_smmu1_flush(DPP_DEV_T *dev,
-                               ZXIC_UINT32 queue_id, 
-                               ZXIC_UINT32 ddr_base_addr, 
-                               ZXIC_UINT32 ddr_wr_mode, 
-                               ZXIC_UINT32 ddr_ecc_en,
-                               ZXIC_UINT32 entry_num, 
-                               ZXIC_UINT32 *element_id)
+/** DTB dd  整个流表清空Flush
+ * @param   dev_id          设备号
+ * @param   queue_id        队列号
+ * @param   ddr_base_addr   ddr基地址，以4K*128bit为单位
+ * @param   ddr_wr_mode     ddr写模式 0-128bit, 1-256bit, 2-384bit, 3-512bit,取值参考SMMU1_DDR_WRT_MODE_E的定义
+ * @param   ddr_ecc_en      ddr ECC使能
+ * @param   start_index     flush开始的条目
+ * @param   entry_num       下发的条目数
+ * @param   element_id      返回下表使用的元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/07/03
+ ************************************************************/
+DPP_STATUS dpp_dtb_smmu1_flush(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+							   ZXIC_UINT32 ddr_base_addr,
+							   ZXIC_UINT32 ddr_wr_mode, ZXIC_UINT32 ddr_ecc_en,
+							   ZXIC_UINT32 entry_num, ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 entry_num_max = 0;
-    ZXIC_UINT32 entry_cycle = 0;
-    ZXIC_UINT32 entry_remains = 0;
-    ZXIC_UINT32 start_index = 0;
-    ZXIC_UINT32 i = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_base_addr is %d.\n", __FUNCTION__,__LINE__,ddr_base_addr);
-    ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_wr_mode is %d.\n", __FUNCTION__,__LINE__,ddr_wr_mode);
-    ZXIC_COMM_TRACE_INFO("%s--[%d]:entry_num is %d.\n", __FUNCTION__,__LINE__,entry_num);
-
-    switch (ddr_wr_mode)
-    {
-        case SMMU1_DDR_WRT_128b://128bit
-        {
-            entry_num_max = 0x1ff;
-            break;
-        }
-
-        case SMMU1_DDR_WRT_256b://256bit
-        {
-            entry_num_max = 0x155;
-            break;
-        }
-
-        case SMMU1_DDR_WRT_384b://384bit
-        {
-            entry_num_max = 0xcc;
-            break;
-        }
-
-        case SMMU1_DDR_WRT_512b://512bit
-        {
-            entry_num_max = 0xcc;
-            break;
-        }
-    }
-
-    ZXIC_COMM_CHECK_INDEX_EQUAL(entry_num_max, 0);
-    entry_cycle = entry_num / entry_num_max;
-    entry_remains = entry_num % entry_num_max;
-
-    for(i = 0; i < entry_cycle; ++i)
-    {
-        start_index = entry_num_max * i;
-
-        rc = dpp_dtb_smmu1_flush_cycle(dev, 
-                                       queue_id, 
-                                       ddr_base_addr, 
-                                       ddr_wr_mode, 
-                                       ddr_ecc_en,
-                                       start_index,
-                                       entry_num_max, 
-                                       element_id);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_flush_cycle");
-
-        ZXIC_COMM_TRACE_INFO("dpp_dtb_smmu1_flush_cycle[%d] element_id = %d\n",i,*element_id);
-    }
-
-    if(entry_remains)
-    {
-        start_index = entry_num_max * entry_cycle;
-        rc = dpp_dtb_smmu1_flush_cycle(dev, 
-                                       queue_id, 
-                                       ddr_base_addr, 
-                                       ddr_wr_mode, 
-                                       ddr_ecc_en,
-                                       start_index,
-                                       entry_remains, 
-                                       element_id);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_flush_cycle");
-
-        ZXIC_COMM_TRACE_INFO("dpp_dtb_smmu1_flush_cycle: element_id = %d\n",*element_id);
-    }
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 entry_num_max = 0;
+	ZXIC_UINT32 entry_cycle = 0;
+	ZXIC_UINT32 entry_remains = 0;
+	ZXIC_UINT32 start_index = 0;
+	ZXIC_UINT32 i = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_base_addr is %d.\n", __FUNCTION__,
+						 __LINE__, ddr_base_addr);
+	ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_wr_mode is %d.\n", __FUNCTION__,
+						 __LINE__, ddr_wr_mode);
+	ZXIC_COMM_TRACE_INFO("%s--[%d]:entry_num is %d.\n", __FUNCTION__, __LINE__,
+						 entry_num);
+
+	switch (ddr_wr_mode) {
+	case SMMU1_DDR_WRT_128b: // 128bit
+	{
+		entry_num_max = 0x1ff;
+		break;
+	}
+
+	case SMMU1_DDR_WRT_256b: // 256bit
+	{
+		entry_num_max = 0x155;
+		break;
+	}
+
+	case SMMU1_DDR_WRT_384b: // 384bit
+	{
+		entry_num_max = 0xcc;
+		break;
+	}
+
+	case SMMU1_DDR_WRT_512b: // 512bit
+	{
+		entry_num_max = 0xcc;
+		break;
+	}
+	}
+
+	ZXIC_COMM_CHECK_INDEX_EQUAL(entry_num_max, 0);
+	entry_cycle = entry_num / entry_num_max;
+	entry_remains = entry_num % entry_num_max;
+
+	for (i = 0; i < entry_cycle; ++i) {
+		start_index = entry_num_max * i;
+
+		rc = dpp_dtb_smmu1_flush_cycle(dev, queue_id, ddr_base_addr,
+									   ddr_wr_mode, ddr_ecc_en, start_index,
+									   entry_num_max, element_id);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_flush_cycle");
+
+		ZXIC_COMM_TRACE_INFO("dpp_dtb_smmu1_flush_cycle[%d] element_id = %d\n",
+							 i, *element_id);
+	}
+
+	if (entry_remains) {
+		start_index = entry_num_max * entry_cycle;
+		rc = dpp_dtb_smmu1_flush_cycle(dev, queue_id, ddr_base_addr,
+									   ddr_wr_mode, ddr_ecc_en, start_index,
+									   entry_remains, element_id);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu1_flush_cycle");
+
+		ZXIC_COMM_TRACE_INFO("dpp_dtb_smmu1_flush_cycle: element_id = %d\n",
+							 *element_id);
+	}
+
+	return DPP_OK;
 }
 
-
 /***********************************************************/
 /** flush指定ZCELL指定范围空间
-* @param   dev_id      设备id
-* @param   queue_id    队列id
-* @param   zcell_id    zcell id 0~127
-* @param   start_index 起始索引 0~511
-* @param   num         条目数
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-DPP_STATUS dpp_dtb_hash_zcell_range_clr(DPP_DEV_T *dev, 
-                                        ZXIC_UINT32 queue_id, 
-                                        ZXIC_UINT32 zcell_id, 
-                                        ZXIC_UINT32 start_index, 
-                                        ZXIC_UINT32 num)
+ * @param   dev_id      设备id
+ * @param   queue_id    队列id
+ * @param   zcell_id    zcell id 0~127
+ * @param   start_index 起始索引 0~511
+ * @param   num         条目数
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/02
+ ************************************************************/
+DPP_STATUS dpp_dtb_hash_zcell_range_clr(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+										ZXIC_UINT32 zcell_id,
+										ZXIC_UINT32 start_index,
+										ZXIC_UINT32 num)
 {
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 zcdep = 0;
-    ZXIC_UINT32 addr = 0;
-    ZXIC_UINT32 addr_offset = 0;
-    ZXIC_UINT32 dtb_len = 0;
-    ZXIC_UINT32 data[512 / 32] = {0};
-    DPP_DTB_ENTRY_T entry = {0};
-    ZXIC_UINT32 entry_data_buff[512 / 32] = {0};
-    ZXIC_UINT8 entry_cmd_buff[DTB_TABLE_CMD_SIZE_BYTE] = {0};
-    ZXIC_UINT8 *p_data_buff = NULL;
-    ZXIC_UINT32 element_id = 0;
-    ZXIC_UINT32 end_index = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), zcell_id, 0, SE_ZCELL_TOTAL_NUM - 1);
-    ZXIC_COMM_CHECK_INDEX_UPPER(start_index,SE_RAM_DEPTH - 1);
-
-    entry.cmd = entry_cmd_buff;
-    entry.data = (ZXIC_UINT8 *)entry_data_buff;
-    ZXIC_COMM_MEMSET(entry_cmd_buff, 0, sizeof(entry_cmd_buff));
-    ZXIC_COMM_MEMSET(entry_data_buff, 0, sizeof(entry_data_buff));
-    ZXIC_COMM_MEMSET(data, 0, sizeof(data));
-
-    p_data_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data_buff);
-    ZXIC_COMM_MEMSET(p_data_buff, 0, DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
-
-    end_index = start_index+num;
-    end_index = (end_index>SE_RAM_DEPTH) ? SE_RAM_DEPTH:end_index;
-    
-    for(zcdep=start_index;zcdep<end_index;zcdep++)
-    {
-        addr = ZBLK_ITEM_ADDR_CALC(zcell_id, zcdep);
-        rc = dpp_dtb_se_alg_zcam_data_write(DEV_ID(dev), addr, (ZXIC_UINT8 *)data, &entry);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_se_alg_zcam_data_write", p_data_buff);
-
-        dtb_len += DTB_ZCAM_LEN_SIZE;
-        addr_offset = (zcdep-start_index) * DTB_ZCAM_LEN_SIZE * DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/
-        rc = dpp_dtb_data_write(p_data_buff, addr_offset, &entry);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", p_data_buff);
-        ZXIC_COMM_MEMSET(entry_cmd_buff, 0x0, sizeof(entry_cmd_buff));
-        ZXIC_COMM_MEMSET(entry_data_buff, 0x0, sizeof(entry_data_buff));
-    }
-
-    rc = dpp_dtb_write_down_table_data(dev,  
-                                     queue_id, 
-                                     dtb_len * 16,
-                                     p_data_buff,
-                                     &element_id);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_write_down_table_data", p_data_buff);
-
-    ZXIC_COMM_FREE(p_data_buff);
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 zcdep = 0;
+	ZXIC_UINT32 addr = 0;
+	ZXIC_UINT32 addr_offset = 0;
+	ZXIC_UINT32 dtb_len = 0;
+	ZXIC_UINT32 data[512 / 32] = { 0 };
+	DPP_DTB_ENTRY_T entry = { 0 };
+	ZXIC_UINT32 entry_data_buff[512 / 32] = { 0 };
+	ZXIC_UINT8 entry_cmd_buff[DTB_TABLE_CMD_SIZE_BYTE] = { 0 };
+	ZXIC_UINT8 *p_data_buff = NULL;
+	ZXIC_UINT32 element_id = 0;
+	ZXIC_UINT32 end_index = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), zcell_id, 0, SE_ZCELL_TOTAL_NUM - 1);
+	ZXIC_COMM_CHECK_INDEX_UPPER(start_index, SE_RAM_DEPTH - 1);
+
+	entry.cmd = entry_cmd_buff;
+	entry.data = (ZXIC_UINT8 *)entry_data_buff;
+	ZXIC_COMM_MEMSET(entry_cmd_buff, 0, sizeof(entry_cmd_buff));
+	ZXIC_COMM_MEMSET(entry_data_buff, 0, sizeof(entry_data_buff));
+	ZXIC_COMM_MEMSET(data, 0, sizeof(data));
+
+	p_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE *
+												 sizeof(ZXIC_UINT8));
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data_buff);
+	ZXIC_COMM_MEMSET(p_data_buff, 0,
+					 DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
+
+	end_index = start_index + num;
+	end_index = (end_index > SE_RAM_DEPTH) ? SE_RAM_DEPTH : end_index;
+
+	for (zcdep = start_index; zcdep < end_index; zcdep++) {
+		addr = ZBLK_ITEM_ADDR_CALC(zcell_id, zcdep);
+		rc = dpp_dtb_se_alg_zcam_data_write(DEV_ID(dev), addr,
+											(ZXIC_UINT8 *)data, &entry);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+				rc, "dpp_dtb_se_alg_zcam_data_write", p_data_buff);
+
+		dtb_len += DTB_ZCAM_LEN_SIZE;
+		addr_offset = (zcdep - start_index) * DTB_ZCAM_LEN_SIZE *
+					  DTB_LEN_POS_SETP; /*在缓存中相对于0的offset*/
+		rc = dpp_dtb_data_write(p_data_buff, addr_offset, &entry);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",
+												 p_data_buff);
+		ZXIC_COMM_MEMSET(entry_cmd_buff, 0x0, sizeof(entry_cmd_buff));
+		ZXIC_COMM_MEMSET(entry_data_buff, 0x0, sizeof(entry_data_buff));
+	}
+
+	rc = dpp_dtb_write_down_table_data(dev, queue_id, dtb_len * 16, p_data_buff,
+									   &element_id);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+			rc, "dpp_dtb_write_down_table_data", p_data_buff);
+
+	rc = dpp_dtb_tab_down_success_status_check(dev, queue_id, element_id);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+			rc, "dpp_dtb_tab_down_success_status_check", p_data_buff);
+
+	ZXIC_COMM_FREE(p_data_buff);
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** flush指定ZCELL空间
-* @param   dev_id     设备id
-* @param   queue_id   队列id
-* @param   zcell_id   zcell id 0~127
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-DPP_STATUS dpp_dtb_hash_zcell_clr(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 zcell_id)
+ * @param   dev_id     设备id
+ * @param   queue_id   队列id
+ * @param   zcell_id   zcell id 0~127
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/02
+ ************************************************************/
+DPP_STATUS dpp_dtb_hash_zcell_clr(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								  ZXIC_UINT32 zcell_id)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 max_num = 0xcc;
-    ZXIC_UINT32 start_index = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), zcell_id, 0, SE_ZCELL_TOTAL_NUM - 1);
-    ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
-
-    start_index = 0;
-    rc = dpp_dtb_hash_zcell_range_clr(dev, 
-                                      queue_id, 
-                                      zcell_id, 
-                                      start_index, 
-                                      max_num);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_zcell_range_clr");
-    
-    start_index = max_num;
-    rc = dpp_dtb_hash_zcell_range_clr(dev, 
-                                      queue_id, 
-                                      zcell_id, 
-                                      start_index, 
-                                      max_num);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_zcell_range_clr");
-    
-    start_index = max_num*2;
-    rc = dpp_dtb_hash_zcell_range_clr(dev, 
-                                      queue_id, 
-                                      zcell_id, 
-                                      start_index, 
-                                      max_num);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_zcell_range_clr");
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 max_num = 0xcc;
+	ZXIC_UINT32 start_index = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), zcell_id, 0, SE_ZCELL_TOTAL_NUM - 1);
+	ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
+
+	start_index = 0;
+	rc = dpp_dtb_hash_zcell_range_clr(dev, queue_id, zcell_id, start_index,
+									  max_num);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_zcell_range_clr");
+
+	start_index = max_num;
+	rc = dpp_dtb_hash_zcell_range_clr(dev, queue_id, zcell_id, start_index,
+									  max_num);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_zcell_range_clr");
+
+	start_index = max_num * 2;
+	rc = dpp_dtb_hash_zcell_range_clr(dev, queue_id, zcell_id, start_index,
+									  max_num);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_zcell_range_clr");
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** flush指定ZREG空间
-* @param   dev_id     设备id
-* @param   queue_id   队列id
-* @param   zblk_id    zblock id 0~31
-* @param   zreg_id    zreg id 0~3
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-DPP_STATUS dpp_dtb_hash_zreg_clr(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 zblk_id, ZXIC_UINT32 zreg_id)
+ * @param   dev_id     设备id
+ * @param   queue_id   队列id
+ * @param   zblk_id    zblock id 0~31
+ * @param   zreg_id    zreg id 0~3
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/02
+ ************************************************************/
+DPP_STATUS dpp_dtb_hash_zreg_clr(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								 ZXIC_UINT32 zblk_id, ZXIC_UINT32 zreg_id)
 {
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 addr = 0;
-    ZXIC_UINT32 wr_data[16] = {0};
-    ZXIC_UINT32 dtb_len = 0;
-
-    DPP_DTB_ENTRY_T entry = {0};
-    ZXIC_UINT32 entry_data_buff[512 / 32] = {0};
-    ZXIC_UINT8 entry_cmd_buff[DTB_TABLE_CMD_SIZE_BYTE] = {0};
-    ZXIC_UINT8 *p_data_buff = NULL;
-    ZXIC_UINT32 element_id = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), zblk_id, 0, SE_ZBLK_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), zreg_id, 0, SE_ZREG_NUM - 1);
-    ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
-
-    entry.cmd = entry_cmd_buff;
-    entry.data = (ZXIC_UINT8 *)entry_data_buff;
-    ZXIC_COMM_MEMSET(entry_cmd_buff, 0, sizeof(entry_cmd_buff));
-    ZXIC_COMM_MEMSET(entry_data_buff, 0, sizeof(entry_data_buff));
-    ZXIC_COMM_MEMSET(wr_data,0x0,sizeof(wr_data));
-
-    addr = ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_id, zreg_id);
-    rc = dpp_dtb_se_alg_zcam_data_write(DEV_ID(dev), addr, (ZXIC_UINT8 *)wr_data, &entry);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_se_alg_zcam_data_write");
-
-    p_data_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data_buff);
-    ZXIC_COMM_MEMSET(p_data_buff, 0x0, DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
-
-    dtb_len += DTB_ZCAM_LEN_SIZE;
-    rc = dpp_dtb_data_write(p_data_buff, 0, &entry);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",p_data_buff);
-
-    rc = dpp_dtb_write_down_table_data(dev,  
-                                     queue_id, 
-                                     dtb_len * 16,
-                                     p_data_buff,
-                                     &element_id);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_write_down_table_data",p_data_buff);
-
-    ZXIC_COMM_FREE(p_data_buff);
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 addr = 0;
+	ZXIC_UINT32 wr_data[16] = { 0 };
+	ZXIC_UINT32 dtb_len = 0;
+
+	DPP_DTB_ENTRY_T entry = { 0 };
+	ZXIC_UINT32 entry_data_buff[512 / 32] = { 0 };
+	ZXIC_UINT8 entry_cmd_buff[DTB_TABLE_CMD_SIZE_BYTE] = { 0 };
+	ZXIC_UINT8 *p_data_buff = NULL;
+	ZXIC_UINT32 element_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), zblk_id, 0, SE_ZBLK_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), zreg_id, 0, SE_ZREG_NUM - 1);
+	ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
+
+	entry.cmd = entry_cmd_buff;
+	entry.data = (ZXIC_UINT8 *)entry_data_buff;
+	ZXIC_COMM_MEMSET(entry_cmd_buff, 0, sizeof(entry_cmd_buff));
+	ZXIC_COMM_MEMSET(entry_data_buff, 0, sizeof(entry_data_buff));
+	ZXIC_COMM_MEMSET(wr_data, 0x0, sizeof(wr_data));
+
+	addr = ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_id, zreg_id);
+	rc = dpp_dtb_se_alg_zcam_data_write(DEV_ID(dev), addr,
+										(ZXIC_UINT8 *)wr_data, &entry);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_se_alg_zcam_data_write");
+
+	p_data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DATA_BUFF_SIZE *
+												 sizeof(ZXIC_UINT8));
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data_buff);
+	ZXIC_COMM_MEMSET(p_data_buff, 0x0,
+					 DPP_DTB_TABLE_DATA_BUFF_SIZE * sizeof(ZXIC_UINT8));
+
+	dtb_len += DTB_ZCAM_LEN_SIZE;
+	rc = dpp_dtb_data_write(p_data_buff, 0, &entry);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",
+											 p_data_buff);
+
+	rc = dpp_dtb_write_down_table_data(dev, queue_id, dtb_len * 16, p_data_buff,
+									   &element_id);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+			rc, "dpp_dtb_write_down_table_data", p_data_buff);
+
+	rc = dpp_dtb_tab_down_success_status_check(dev, queue_id, element_id);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+			rc, "dpp_dtb_tab_down_success_status_check", p_data_buff);
+
+	ZXIC_COMM_FREE(p_data_buff);
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** flush指定ZCAM空间(独占模式)
-* @param   p_se_cfg   全局数据结构
-* @param   queue_id   队列id
-* @param   fun_id     hash引擎0~3
-* @param   bulk_id    bulk id 0~7
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-DPP_STATUS dpp_dtb_specify_zcam_space_clr(DPP_DEV_T *dev,
-                                           DPP_SE_CFG *p_se_cfg,
-                                           ZXIC_UINT32 queue_id,
-                                           ZXIC_UINT32 fun_id,
-                                           ZXIC_UINT32 bulk_id)
+ * @param   p_se_cfg   全局数据结构
+ * @param   queue_id   队列id
+ * @param   fun_id     hash引擎0~3
+ * @param   bulk_id    bulk id 0~7
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/02
+ ************************************************************/
+DPP_STATUS dpp_dtb_specify_zcam_space_clr(DPP_DEV_T *dev, DPP_SE_CFG *p_se_cfg,
+										  ZXIC_UINT32 queue_id,
+										  ZXIC_UINT32 fun_id,
+										  ZXIC_UINT32 bulk_id)
 {
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 zblock_id = 0;
-
-    D_NODE *p_zblk_dn = NULL;
-    SE_ZBLK_CFG *p_zblk = NULL;
-    SE_ZREG_CFG *p_zreg = NULL;
-    SE_ZCELL_CFG *p_zcell = NULL;
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    FUNC_ID_INFO *p_func_info = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev),p_se_cfg);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), fun_id, 0, HASH_FUNC_ID_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), bulk_id, 0, HASH_BULK_NUM - 1);
-    ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
-    
-    // dev_id = p_se_cfg->dev_id;
-    p_func_info = DPP_GET_FUN_INFO(p_se_cfg, fun_id);
-    DPP_SE_CHECK_FUN(p_func_info, fun_id, FUN_HASH);
-    p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev),p_hash_cfg);
-    p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next;
-    
-    while (p_zblk_dn)
-    {
-        p_zblk = (SE_ZBLK_CFG *)p_zblk_dn->data;
-        zblock_id = p_zblk->zblk_idx;
-
-        for (i = 0; i < SE_ZCELL_NUM; i++)
-        {
-            p_zcell = &(p_zblk->zcell_info[i]);
-            if ((p_zcell->flag & DPP_ZCELL_FLAG_IS_MONO) && (p_zcell->bulk_id == bulk_id))
-            {
-                rc = dpp_dtb_hash_zcell_clr(dev, queue_id, p_zcell->zcell_idx);
-                ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_hash_zcell_clr");
-                ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "the Zblock[%d]'s Mono Zcell_id :%d \n", zblock_id, p_zcell->zcell_idx);
-            }
-        }
-
-        for (i = 0; i < SE_ZREG_NUM; i++)
-        {
-            p_zreg = &(p_zblk->zreg_info[i]);
-            if ((p_zreg->flag & DPP_ZREG_FLAG_IS_MONO) && (p_zreg->bulk_id == bulk_id))
-            {
-                rc = dpp_dtb_hash_zreg_clr(dev, queue_id, zblock_id, i);
-                ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "npe_hash_zreg_clr");
-                ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "the Zblock[%d]'s Mono Zreg_id :%d \n", zblock_id, i);
-            }
-        }
-
-        p_zblk_dn = p_zblk_dn->next;
-    }
-    
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 zblock_id = 0;
+
+	D_NODE *p_zblk_dn = NULL;
+	SE_ZBLK_CFG *p_zblk = NULL;
+	SE_ZREG_CFG *p_zreg = NULL;
+	SE_ZCELL_CFG *p_zcell = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	FUNC_ID_INFO *p_func_info = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), fun_id, 0, HASH_FUNC_ID_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), bulk_id, 0, HASH_BULK_NUM - 1);
+	ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
+
+	// dev_id = p_se_cfg->dev_id;
+	p_func_info = DPP_GET_FUN_INFO(p_se_cfg, fun_id);
+	DPP_SE_CHECK_FUN(p_func_info, fun_id, FUN_HASH);
+	p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg);
+	p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next;
+
+	while (p_zblk_dn) {
+		p_zblk = (SE_ZBLK_CFG *)p_zblk_dn->data;
+		zblock_id = p_zblk->zblk_idx;
+
+		for (i = 0; i < SE_ZCELL_NUM; i++) {
+			p_zcell = &(p_zblk->zcell_info[i]);
+			if ((p_zcell->flag & DPP_ZCELL_FLAG_IS_MONO) &&
+				(p_zcell->bulk_id == bulk_id)) {
+				rc = dpp_dtb_hash_zcell_clr(dev, queue_id, p_zcell->zcell_idx);
+				ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+									   "dpp_dtb_hash_zcell_clr");
+				ZXIC_COMM_TRACE_DEV_INFO(
+						DEV_ID(dev), "the Zblock[%d]'s Mono Zcell_id :%d \n",
+						zblock_id, p_zcell->zcell_idx);
+			}
+		}
+
+		for (i = 0; i < SE_ZREG_NUM; i++) {
+			p_zreg = &(p_zblk->zreg_info[i]);
+			if ((p_zreg->flag & DPP_ZREG_FLAG_IS_MONO) &&
+				(p_zreg->bulk_id == bulk_id)) {
+				rc = dpp_dtb_hash_zreg_clr(dev, queue_id, zblock_id, i);
+				ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "npe_hash_zreg_clr");
+				ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev),
+										 "the Zblock[%d]'s Mono Zreg_id :%d \n",
+										 zblock_id, i);
+			}
+		}
+
+		p_zblk_dn = p_zblk_dn->next;
+	}
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** flush当前hash引擎占用的ZCAM空间
-* @param   p_se_cfg   全局数据结构
-* @param   queue_id   队列id
-* @param   fun_id     hash引擎0~3
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-DPP_STATUS dpp_dtb_zcam_space_clr(DPP_DEV_T *dev,
-                                  DPP_SE_CFG *p_se_cfg,
-                                  ZXIC_UINT32 queue_id,
-                                  ZXIC_UINT32 fun_id)
+ * @param   p_se_cfg   全局数据结构
+ * @param   queue_id   队列id
+ * @param   fun_id     hash引擎0~3
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/02
+ ************************************************************/
+DPP_STATUS dpp_dtb_zcam_space_clr(DPP_DEV_T *dev, DPP_SE_CFG *p_se_cfg,
+								  ZXIC_UINT32 queue_id, ZXIC_UINT32 fun_id)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT32 zblock_id = 0;
-
-    D_NODE *p_zblk_dn = NULL;
-    SE_ZBLK_CFG *p_zblk = NULL;
-    SE_ZCELL_CFG *p_zcell = NULL;
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    FUNC_ID_INFO *p_func_info = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev),p_se_cfg);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), fun_id, 0, HASH_FUNC_ID_NUM - 1);
-    ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
-
-    // dev_id = p_se_cfg->dev_id;
-    p_func_info = DPP_GET_FUN_INFO(p_se_cfg, fun_id);
-    DPP_SE_CHECK_FUN(p_func_info, fun_id, FUN_HASH);
-    p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev),p_hash_cfg);
-    p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next;
-    
-    while (p_zblk_dn)
-    {
-        p_zblk = (SE_ZBLK_CFG *)p_zblk_dn->data;
-        zblock_id = p_zblk->zblk_idx;
-        for (index = 0; index < SE_ZCELL_NUM; index++)
-        {
-            p_zcell = &(p_zblk->zcell_info[index]);
-            rc = dpp_dtb_hash_zcell_clr(dev, queue_id, p_zcell->zcell_idx);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_hash_zcell_clr");
-        }
-
-        for (index = 0; index < SE_ZREG_NUM; index++)
-        {
-            rc = dpp_dtb_hash_zreg_clr(dev, queue_id, zblock_id, index);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_hash_zreg_clr");
-        }
-        p_zblk_dn = p_zblk_dn->next;
-    }
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 zblock_id = 0;
+
+	D_NODE *p_zblk_dn = NULL;
+	SE_ZBLK_CFG *p_zblk = NULL;
+	SE_ZCELL_CFG *p_zcell = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	FUNC_ID_INFO *p_func_info = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), fun_id, 0, HASH_FUNC_ID_NUM - 1);
+	ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
+
+	// dev_id = p_se_cfg->dev_id;
+	p_func_info = DPP_GET_FUN_INFO(p_se_cfg, fun_id);
+	DPP_SE_CHECK_FUN(p_func_info, fun_id, FUN_HASH);
+	p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg);
+	p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next;
+
+	while (p_zblk_dn) {
+		p_zblk = (SE_ZBLK_CFG *)p_zblk_dn->data;
+		zblock_id = p_zblk->zblk_idx;
+		for (index = 0; index < SE_ZCELL_NUM; index++) {
+			p_zcell = &(p_zblk->zcell_info[index]);
+			rc = dpp_dtb_hash_zcell_clr(dev, queue_id, p_zcell->zcell_idx);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_hash_zcell_clr");
+		}
+
+		for (index = 0; index < SE_ZREG_NUM; index++) {
+			rc = dpp_dtb_hash_zreg_clr(dev, queue_id, zblock_id, index);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_hash_zreg_clr");
+		}
+		p_zblk_dn = p_zblk_dn->next;
+	}
+
+	return DPP_OK;
 }
 
-
 /***********************************************************/
 /** 清除指定空间的hash表项(清除软件配置)
-* @param   p_se_cfg
-* @param   hash_id
-* @param   bulk_id
-*
-* @return
-* @remark  无
-* @see
-* @author  cq      @date  2023/08/18
-************************************************************/
-DPP_STATUS dpp_hash_specify_entry_delete(DPP_SE_CFG *p_se_cfg,ZXIC_UINT32 hash_id, ZXIC_UINT32 bulk_id)
+ * @param   p_se_cfg
+ * @param   hash_id
+ * @param   bulk_id
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/18
+ ************************************************************/
+DPP_STATUS dpp_hash_specify_entry_delete(DPP_SE_CFG *p_se_cfg,
+										 ZXIC_UINT32 hash_id,
+										 ZXIC_UINT32 bulk_id)
 {
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT8 key_valid = 0;
-    ZXIC_UINT32 table_id = 0;
-    ZXIC_UINT32 temp_bulk_id = 0;
-
-    D_NODE *p_node = NULL;
-    ZXIC_RB_TN *p_rb_tn = NULL;
-    D_HEAD *p_head_hash_rb = NULL;
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    FUNC_ID_INFO *p_func_info = NULL;
-    DPP_HASH_RBKEY_INFO *p_rbkey = NULL;
-    DPP_HASH_RBKEY_INFO *p_rbkey_rtn = NULL;
-    ZXIC_RB_TN *p_rb_tn_rtn = NULL;
-    SE_ITEM_CFG *p_item = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
-    ZXIC_COMM_CHECK_INDEX(hash_id, 0, HASH_FUNC_ID_NUM - 1);
-    ZXIC_COMM_CHECK_INDEX(bulk_id, 0, HASH_BULK_NUM - 1);
-
-    dev_id = p_se_cfg->dev_id;
-    p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_id);
-    DPP_SE_CHECK_FUN(p_func_info, hash_id, FUN_HASH);
-
-    p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
-    p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list;
-
-    p_node = p_head_hash_rb->p_next;
-    while(p_node)
-    {
-        p_rb_tn = (ZXIC_RB_TN *)p_node->data;
-        p_rbkey = (DPP_HASH_RBKEY_INFO *)p_rb_tn->p_key;
-        key_valid = DPP_GET_HASH_KEY_VALID(p_rbkey->key);
-        table_id = DPP_GET_HASH_TBL_ID(p_rbkey->key);
-        temp_bulk_id = ((table_id >> 2) & 0x7);
-        if((!key_valid) || (temp_bulk_id != bulk_id))
-        {
-            p_node = p_node->next; 
-            continue;
-        }
-        
-        p_node = p_node->next;           /*zxic_comm_rb_delete删除操作之前执行*/
-        rc = zxic_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey, &p_rb_tn_rtn);
-        if (ZXIC_RBT_RC_SRHFAIL == rc)
-        {
-            p_hash_cfg->hash_stat.delete_fail++;
-            ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "Error!there is not item in hash!\n");
-            return DPP_HASH_RC_DEL_SRHFAIL;
-        }
-
-        ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn);
-        p_rbkey_rtn = (DPP_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key);
-        p_item = p_rbkey_rtn->p_item_info;
-        
-        rc = zxic_comm_double_link_del(&(p_rbkey_rtn->entry_dn), &(p_item->item_list));
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_del");
-        p_item->wrt_mask &= ~(DPP_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, p_rbkey_rtn->entry_pos)) & 0xF;
-
-        if (0 == p_item->item_list.used)
-        {
-            if ((ITEM_DDR_256 == p_item->item_type) || (ITEM_DDR_512 == p_item->item_type))
-            {
-                /* modify coverity by yinxh 2021.03.10*,以256bit为单位。暂不考虑512bit的情况*/
-                ZXIC_COMM_CHECK_INDEX_UPPER(p_item->item_index, p_hash_cfg->p_bulk_ddr_info[bulk_id]->item_num);
-                p_hash_cfg->p_bulk_ddr_info[bulk_id]->p_item_array[p_item->item_index] = NULL;
-                ZXIC_COMM_FREE(p_item);
-            }
-            else
-            {
-                p_item->valid = 0;
-            }
-        }
-
-        ZXIC_COMM_FREE(p_rbkey_rtn);
-        ZXIC_COMM_FREE(p_rb_tn_rtn);
-        p_hash_cfg->hash_stat.delete_ok++;
-    }
-
-    return DPP_OK;
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT8 key_valid = 0;
+	ZXIC_UINT32 table_id = 0;
+	ZXIC_UINT32 temp_bulk_id = 0;
+
+	D_NODE *p_node = NULL;
+	ZXIC_RB_TN *p_rb_tn = NULL;
+	D_HEAD *p_head_hash_rb = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	FUNC_ID_INFO *p_func_info = NULL;
+	DPP_HASH_RBKEY_INFO *p_rbkey = NULL;
+	DPP_HASH_RBKEY_INFO *p_rbkey_rtn = NULL;
+	ZXIC_RB_TN *p_rb_tn_rtn = NULL;
+	SE_ITEM_CFG *p_item = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	ZXIC_COMM_CHECK_INDEX(hash_id, 0, HASH_FUNC_ID_NUM - 1);
+	ZXIC_COMM_CHECK_INDEX(bulk_id, 0, HASH_BULK_NUM - 1);
+
+	dev_id = p_se_cfg->dev_id;
+	p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_id);
+	DPP_SE_CHECK_FUN(p_func_info, hash_id, FUN_HASH);
+
+	p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
+	p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list;
+
+	p_node = p_head_hash_rb->p_next;
+	while (p_node) {
+		p_rb_tn = (ZXIC_RB_TN *)p_node->data;
+		p_rbkey = (DPP_HASH_RBKEY_INFO *)p_rb_tn->p_key;
+		key_valid = DPP_GET_HASH_KEY_VALID(p_rbkey->key);
+		table_id = DPP_GET_HASH_TBL_ID(p_rbkey->key);
+		temp_bulk_id = ((table_id >> 2) & 0x7);
+		if ((!key_valid) || (temp_bulk_id != bulk_id)) {
+			p_node = p_node->next;
+			continue;
+		}
+
+		p_node = p_node->next; /*zxic_comm_rb_delete删除操作之前执行*/
+		rc = zxic_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey, &p_rb_tn_rtn);
+		if (ZXIC_RBT_RC_SRHFAIL == rc) {
+			p_hash_cfg->hash_stat.delete_fail++;
+			ZXIC_COMM_TRACE_DEV_DEBUG(dev_id,
+									  "Error!there is not item in hash!\n");
+			return DPP_HASH_RC_DEL_SRHFAIL;
+		}
+
+		ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn);
+		p_rbkey_rtn = (DPP_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key);
+		p_item = p_rbkey_rtn->p_item_info;
+
+		rc = zxic_comm_double_link_del(&(p_rbkey_rtn->entry_dn),
+									   &(p_item->item_list));
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_del");
+		p_item->wrt_mask &= ~(DPP_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size,
+													  p_rbkey_rtn->entry_pos)) &
+							0xF;
+
+		if (0 == p_item->item_list.used) {
+			if ((ITEM_DDR_256 == p_item->item_type) ||
+				(ITEM_DDR_512 == p_item->item_type)) {
+				/* modify coverity by yinxh 2021.03.10*,以256bit为单位。暂不考虑512bit的情况*/
+				ZXIC_COMM_CHECK_INDEX_UPPER(
+						p_item->item_index,
+						p_hash_cfg->p_bulk_ddr_info[bulk_id]->item_num);
+				p_hash_cfg->p_bulk_ddr_info[bulk_id]
+						->p_item_array[p_item->item_index] = NULL;
+				ZXIC_COMM_FREE(p_item);
+			} else {
+				p_item->valid = 0;
+			}
+		}
+
+		ZXIC_COMM_FREE(p_rbkey_rtn);
+		ZXIC_COMM_FREE(p_rb_tn_rtn);
+		p_hash_cfg->hash_stat.delete_ok++;
+	}
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** flush指定eram空间
-* @param   dev_id     设备id
-* @param   queue_id   队列id
-* @param   sdt_no     sdt号
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-DPP_STATUS dpp_dtb_eram_table_flush(DPP_DEV_T *dev,
-                               ZXIC_UINT32 queue_id,
-                               ZXIC_UINT32 sdt_no)
+ * @param   dev_id     设备id
+ * @param   queue_id   队列id
+ * @param   sdt_no     sdt号
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/02
+ ************************************************************/
+DPP_STATUS dpp_dtb_eram_table_flush(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									ZXIC_UINT32 sdt_no)
 {
-    DPP_STATUS rc         = DPP_OK;
-    ZXIC_UINT32 eram_depth = 0;
-    ZXIC_UINT32 element_id = 0;
-    ZXIC_UINT32 index      = 0;
-    ZXIC_UINT8 *pBuff      = NULL;
-    DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr = NULL;
-    DPP_DTB_ERAM_ENTRY_INFO_T *p_temp_entry_arr = NULL;
-    DPP_SDTTBL_ERAM_T sdt_eram           = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev),sdt_no,&sdt_eram);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
-
-    eram_depth = sdt_eram.eram_table_depth;
-    p_entry_arr = (DPP_DTB_ERAM_ENTRY_INFO_T *)ZXIC_COMM_MALLOC(eram_depth*sizeof(DPP_DTB_ERAM_ENTRY_INFO_T));
-    ZXIC_COMM_CHECK_POINT(p_entry_arr);
-    pBuff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(eram_depth*4*sizeof(ZXIC_UINT32));
-    ZXIC_COMM_CHECK_POINT_MEMORY_FREE(pBuff,p_entry_arr);
-    ZXIC_COMM_MEMSET((ZXIC_UINT8 *)p_entry_arr,0x0,eram_depth*sizeof(DPP_DTB_ERAM_ENTRY_INFO_T));
-    ZXIC_COMM_MEMSET(pBuff,0x0,eram_depth*4*sizeof(ZXIC_UINT32));
-    for(index=0;index<eram_depth;index++)
-    {
-        p_temp_entry_arr = p_entry_arr+index;
-        p_temp_entry_arr->index = index;
-        p_temp_entry_arr->p_data = (ZXIC_UINT32 *)(pBuff + (index * 4 * sizeof(ZXIC_UINT32)));
-    }
-
-    rc = dpp_dtb_eram_dma_write(dev, 
-                                queue_id,
-                                sdt_no, 
-                                eram_depth, 
-                                p_entry_arr,
-                                &element_id);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE2PTR_NO_ASSERT(rc, "dpp_dtb_eram_dma_write",pBuff,p_entry_arr);
-
-    ZXIC_COMM_FREE(pBuff);
-    ZXIC_COMM_FREE(p_entry_arr);
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 eram_depth = 0;
+	ZXIC_UINT32 element_id = 0;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT8 *pBuff = NULL;
+	DPP_DTB_ERAM_ENTRY_INFO_T *p_entry_arr = NULL;
+	DPP_DTB_ERAM_ENTRY_INFO_T *p_temp_entry_arr = NULL;
+	DPP_SDTTBL_ERAM_T sdt_eram = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_eram);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
+
+	eram_depth = sdt_eram.eram_table_depth;
+	p_entry_arr = (DPP_DTB_ERAM_ENTRY_INFO_T *)ZXIC_COMM_MALLOC(
+			eram_depth * sizeof(DPP_DTB_ERAM_ENTRY_INFO_T));
+	ZXIC_COMM_CHECK_POINT(p_entry_arr);
+	pBuff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(eram_depth * 4 *
+										   sizeof(ZXIC_UINT32));
+	ZXIC_COMM_CHECK_POINT_MEMORY_FREE(pBuff, p_entry_arr);
+	ZXIC_COMM_MEMSET((ZXIC_UINT8 *)p_entry_arr, 0x0,
+					 eram_depth * sizeof(DPP_DTB_ERAM_ENTRY_INFO_T));
+	ZXIC_COMM_MEMSET(pBuff, 0x0, eram_depth * 4 * sizeof(ZXIC_UINT32));
+	for (index = 0; index < eram_depth; index++) {
+		p_temp_entry_arr = p_entry_arr + index;
+		p_temp_entry_arr->index = index;
+		p_temp_entry_arr->p_data =
+				(ZXIC_UINT32 *)(pBuff + (index * 4 * sizeof(ZXIC_UINT32)));
+	}
+
+	rc = dpp_dtb_eram_dma_write(dev, queue_id, sdt_no, eram_depth, p_entry_arr,
+								&element_id);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE2PTR_NO_ASSERT(rc, "dpp_dtb_eram_dma_write",
+												 pBuff, p_entry_arr);
+
+	ZXIC_COMM_FREE(pBuff);
+	ZXIC_COMM_FREE(p_entry_arr);
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** flush指定hash空间(DDR/ZCAM)
-* @param   dev_id     设备id
-* @param   queue_id   队列id
-* @param   sdt_no     sdt号
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/08/02
-************************************************************/
-DPP_STATUS dpp_dtb_hash_table_flush(DPP_DEV_T *dev,
-                               ZXIC_UINT32 queue_id,
-                               ZXIC_UINT32 sdt_no)
+ * @param   dev_id     设备id
+ * @param   queue_id   队列id
+ * @param   sdt_no     sdt号
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/02
+ ************************************************************/
+DPP_STATUS dpp_dtb_hash_table_flush(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									ZXIC_UINT32 sdt_no)
 {
-    DPP_STATUS rc         = DPP_OK;
-    ZXIC_UINT8 bulk_id    = 0;
-    ZXIC_UINT8 table_id   = 0;
-    ZXIC_UINT32 ddr_baddr = 0;
-    ZXIC_UINT32 ddr_item_num = 0;
-    ZXIC_UINT32 ddr_tbl_wr_mode = 0;
-    ZXIC_UINT32 element_id = 0;
-
-    DPP_SE_CFG *p_se_cfg = NULL;
-    FUNC_ID_INFO *p_func_info = NULL;
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    HASH_DDR_CFG *p_ddr_cfg = NULL;
-    DPP_SDTTBL_HASH_T sdt_hash           = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev),sdt_no,&sdt_hash);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
-
-     /* 取出se配置 */
-    rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_cfg_get");
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg);
-    p_func_info = DPP_GET_FUN_INFO(p_se_cfg, sdt_hash.hash_id);
-    DPP_SE_CHECK_FUN(p_func_info, sdt_hash.hash_id, FUN_HASH);
-
-    p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg);
-    table_id = sdt_hash.hash_table_id;
-    bulk_id = ((table_id >> 2) & 0x7);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), bulk_id, 0, HASH_BULK_NUM - 1);
-    
-    /*独占模式下才执行flush操作*/
-    if(!p_hash_cfg->bulk_ram_mono[bulk_id])
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "fush error:hash[%u] bulk[%u] is not monopolize!\n", sdt_hash.hash_id, bulk_id);
-        return DPP_HASH_RC_INVALID_PARA;
-    }
-    
-    /*混合模式，先清除DDR空间*/
-    if(p_hash_cfg->ddr_valid)
-    {
-        p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id];
-        ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ddr_cfg);
-        ddr_baddr = p_ddr_cfg->ddr_baddr;
-        ddr_item_num = p_ddr_cfg->item_num;/*ddr存储单元数目，以DDR位宽为单位*/
-        ddr_tbl_wr_mode = SMMU1_DDR_WRT_256b;
-        if(DDR_WIDTH_512b == p_ddr_cfg->width_mode)
-        {
-           ddr_tbl_wr_mode =  SMMU1_DDR_WRT_512b;
-        }
-
-        ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_baddr is %d.\n", __FUNCTION__,__LINE__,ddr_baddr);
-        ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_item_num is %d.\n", __FUNCTION__,__LINE__,ddr_item_num);
-        ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_tbl_wr_mode is %d.\n", __FUNCTION__,__LINE__,ddr_tbl_wr_mode);
-       
-        rc = dpp_dtb_smmu1_flush(dev, 
-                             queue_id, 
-                             ddr_baddr, 
-                             ddr_tbl_wr_mode, 
-                             p_ddr_cfg->ddr_ecc_en,
-                             ddr_item_num, 
-                             &element_id);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_smmu1_flush");
-    }
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_hash_table_flush: DDR DONE!!!\n");
-    
-    /*清除zcam空间*/
-    rc = dpp_dtb_specify_zcam_space_clr(dev, p_se_cfg,queue_id,sdt_hash.hash_id,bulk_id);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_specify_zcam_space_clr");
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_specify_zcam_space_clr DONE!!!\n");
-
-    /*软件删除表项*/
-    rc = dpp_hash_specify_entry_delete(p_se_cfg,sdt_hash.hash_id,bulk_id);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_specify_entry_delete");
-    ZXIC_COMM_TRACE_INFO("dpp_hash_specify_entry_delete DONE!!!\n");
-    
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT8 bulk_id = 0;
+	ZXIC_UINT8 table_id = 0;
+	ZXIC_UINT32 ddr_baddr = 0;
+	ZXIC_UINT32 ddr_item_num = 0;
+	ZXIC_UINT32 ddr_tbl_wr_mode = 0;
+	ZXIC_UINT32 element_id = 0;
+
+	DPP_SE_CFG *p_se_cfg = NULL;
+	FUNC_ID_INFO *p_func_info = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	HASH_DDR_CFG *p_ddr_cfg = NULL;
+	DPP_SDTTBL_HASH_T sdt_hash = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
+
+	/* 取出se配置 */
+	rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_cfg_get");
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg);
+	p_func_info = DPP_GET_FUN_INFO(p_se_cfg, sdt_hash.hash_id);
+	DPP_SE_CHECK_FUN(p_func_info, sdt_hash.hash_id, FUN_HASH);
+
+	p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg);
+	table_id = sdt_hash.hash_table_id;
+	bulk_id = ((table_id >> 2) & 0x7);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), bulk_id, 0, HASH_BULK_NUM - 1);
+
+	/*独占模式下才执行flush操作*/
+	if (!p_hash_cfg->bulk_ram_mono[bulk_id]) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev),
+				"fush error:hash[%u] bulk[%u] is not monopolize!\n",
+				sdt_hash.hash_id, bulk_id);
+		return DPP_HASH_RC_INVALID_PARA;
+	}
+
+	/*混合模式，先清除DDR空间*/
+	if (p_hash_cfg->ddr_valid) {
+		p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id];
+		ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ddr_cfg);
+		ddr_baddr = p_ddr_cfg->ddr_baddr;
+		ddr_item_num = p_ddr_cfg->item_num; /*ddr存储单元数目，以DDR位宽为单位*/
+		ddr_tbl_wr_mode = SMMU1_DDR_WRT_256b;
+		if (DDR_WIDTH_512b == p_ddr_cfg->width_mode) {
+			ddr_tbl_wr_mode = SMMU1_DDR_WRT_512b;
+		}
+
+		ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_baddr is %d.\n", __FUNCTION__,
+							 __LINE__, ddr_baddr);
+		ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_item_num is %d.\n", __FUNCTION__,
+							 __LINE__, ddr_item_num);
+		ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_tbl_wr_mode is %d.\n", __FUNCTION__,
+							 __LINE__, ddr_tbl_wr_mode);
+
+		rc = dpp_dtb_smmu1_flush(dev, queue_id, ddr_baddr, ddr_tbl_wr_mode,
+								 p_ddr_cfg->ddr_ecc_en, ddr_item_num,
+								 &element_id);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_smmu1_flush");
+	}
+	ZXIC_COMM_TRACE_INFO("dpp_dtb_hash_table_flush: DDR DONE!!!\n");
+
+	/*清除zcam空间*/
+	rc = dpp_dtb_specify_zcam_space_clr(dev, p_se_cfg, queue_id,
+										sdt_hash.hash_id, bulk_id);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_specify_zcam_space_clr");
+	ZXIC_COMM_TRACE_INFO("dpp_dtb_specify_zcam_space_clr DONE!!!\n");
+
+	/*软件删除表项*/
+	rc = dpp_hash_specify_entry_delete(p_se_cfg, sdt_hash.hash_id, bulk_id);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_specify_entry_delete");
+	ZXIC_COMM_TRACE_INFO("dpp_hash_specify_entry_delete DONE!!!\n");
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 清除hash表资源(硬件和软件，硬件通过dtb方式清除)
-* @param   dev_id     设备id
-* @param   queue_id   队列id
-* @param   hash_id    hash引擎 0~3
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/09/26
-************************************************************/
-DPP_STATUS dpp_dtb_hash_all_entry_delete(DPP_DEV_T *dev, ZXIC_UINT32 queue_id, ZXIC_UINT32 hash_id)
+ * @param   dev_id     设备id
+ * @param   queue_id   队列id
+ * @param   hash_id    hash引擎 0~3
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/09/26
+ ************************************************************/
+DPP_STATUS dpp_dtb_hash_all_entry_delete(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+										 ZXIC_UINT32 hash_id)
 {
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 bulk_id = 0;
-    ZXIC_UINT32 ddr_baddr = 0;
-    ZXIC_UINT32 ddr_item_num = 0;
-    ZXIC_UINT32 ddr_tbl_wr_mode = 0;
-    ZXIC_UINT32 element_id = 0;
-
-    DPP_SE_CFG *p_se_cfg = NULL;
-    FUNC_ID_INFO *p_func_info = NULL;
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    HASH_DDR_CFG *p_ddr_cfg = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(hash_id, 0, HASH_FUNC_ID_NUM - 1);
-
-    /* 取出se配置 */
-    rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_cfg_get");
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg);
-    p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_id);
-    DPP_SE_CHECK_FUN(p_func_info, hash_id, FUN_HASH);
-
-    p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg);
-
-    /*混合模式，先清除DDR空间*/
-    if(p_hash_cfg->ddr_valid)
-    {
-        for(bulk_id = 0; bulk_id < HASH_BULK_NUM; bulk_id++)
-        {
-            p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id];
-            if(NULL==p_ddr_cfg)
-            {
-                continue;
-            }
-            ddr_baddr = p_ddr_cfg->ddr_baddr;
-            ddr_item_num = p_ddr_cfg->item_num;/*ddr存储单元数目，以DDR位宽为单位*/
-            ddr_tbl_wr_mode = SMMU1_DDR_WRT_256b;
-            if(DDR_WIDTH_512b == p_ddr_cfg->width_mode)
-            {
-               ddr_tbl_wr_mode =  SMMU1_DDR_WRT_512b;
-            }
-
-            ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_baddr is %d.\n", __FUNCTION__,__LINE__,ddr_baddr);
-            ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_item_num is %d.\n", __FUNCTION__,__LINE__,ddr_item_num);
-            ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_tbl_wr_mode is %d.\n", __FUNCTION__,__LINE__,ddr_tbl_wr_mode);
-       
-            rc = dpp_dtb_smmu1_flush(dev, 
-                             queue_id, 
-                             ddr_baddr, 
-                             ddr_tbl_wr_mode, 
-                             p_ddr_cfg->ddr_ecc_en,
-                             ddr_item_num, 
-                             &element_id);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_smmu1_flush");
-        }
-    }
-
-    /*清除hash引擎占用的整个zcam空间*/
-    rc = dpp_dtb_zcam_space_clr(dev, p_se_cfg, queue_id, hash_id);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_specify_zcam_space_clr");
-    ZXIC_COMM_PRINT("dpp_dtb_zcam_space_clr hash id: %d DONE!!!\n", hash_id);
-
-    /*软件删除表项*/
-    rc = dpp_hash_soft_all_entry_delete(p_se_cfg, hash_id);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_soft_all_entry_delete");
-    ZXIC_COMM_PRINT("dpp_hash_soft_all_entry_delete hash id %d DONE!!!\n", hash_id);
-    
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 bulk_id = 0;
+	ZXIC_UINT32 ddr_baddr = 0;
+	ZXIC_UINT32 ddr_item_num = 0;
+	ZXIC_UINT32 ddr_tbl_wr_mode = 0;
+	ZXIC_UINT32 element_id = 0;
+
+	DPP_SE_CFG *p_se_cfg = NULL;
+	FUNC_ID_INFO *p_func_info = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	HASH_DDR_CFG *p_ddr_cfg = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(hash_id, 0, HASH_FUNC_ID_NUM - 1);
+
+	/* 取出se配置 */
+	rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_se_cfg_get");
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg);
+	p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_id);
+	DPP_SE_CHECK_FUN(p_func_info, hash_id, FUN_HASH);
+
+	p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg);
+
+	/*混合模式，先清除DDR空间*/
+	if (p_hash_cfg->ddr_valid) {
+		for (bulk_id = 0; bulk_id < HASH_BULK_NUM; bulk_id++) {
+			p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id];
+			if (NULL == p_ddr_cfg) {
+				continue;
+			}
+			ddr_baddr = p_ddr_cfg->ddr_baddr;
+			ddr_item_num =
+					p_ddr_cfg->item_num; /*ddr存储单元数目，以DDR位宽为单位*/
+			ddr_tbl_wr_mode = SMMU1_DDR_WRT_256b;
+			if (DDR_WIDTH_512b == p_ddr_cfg->width_mode) {
+				ddr_tbl_wr_mode = SMMU1_DDR_WRT_512b;
+			}
+
+			ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_baddr is %d.\n", __FUNCTION__,
+								 __LINE__, ddr_baddr);
+			ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_item_num is %d.\n", __FUNCTION__,
+								 __LINE__, ddr_item_num);
+			ZXIC_COMM_TRACE_INFO("%s--[%d]:ddr_tbl_wr_mode is %d.\n",
+								 __FUNCTION__, __LINE__, ddr_tbl_wr_mode);
+
+			rc = dpp_dtb_smmu1_flush(dev, queue_id, ddr_baddr, ddr_tbl_wr_mode,
+									 p_ddr_cfg->ddr_ecc_en, ddr_item_num,
+									 &element_id);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_smmu1_flush");
+		}
+	}
+
+	/*清除hash引擎占用的整个zcam空间*/
+	rc = dpp_dtb_zcam_space_clr(dev, p_se_cfg, queue_id, hash_id);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_specify_zcam_space_clr");
+	ZXIC_COMM_PRINT("dpp_dtb_zcam_space_clr hash id: %d DONE!!!\n", hash_id);
+
+	/*软件删除表项*/
+	rc = dpp_hash_soft_all_entry_delete(p_se_cfg, hash_id);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_soft_all_entry_delete");
+	ZXIC_COMM_PRINT("dpp_hash_soft_all_entry_delete hash id %d DONE!!!\n",
+					hash_id);
+
+	return DPP_OK;
 }
 
 /***********************************************************/
-/** DTB etcam 整个流表清空Flush 
-* @param   devId      NP设备号
-* @param   queueId    DTB队列编号
-* @param   sdtNo      流表std号
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/  
-DPP_STATUS dpp_dtb_etcam_table_flush(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 queue_id,
-                                     ZXIC_UINT32 sdt_no)
-{   
-    // 按照std 号的深度进行etcam的内容的清理；
-    DPP_STATUS  rc = DPP_OK;
-
-    ZXIC_UINT32 data_byte_size = 0;
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT32 etcam_key_mode = 0;
-    ZXIC_UINT32 as_enable = 0;
-    ZXIC_UINT32 etcam_table_depth = 0;
-    ZXIC_UINT32 element_id = 0;
-
-    DPP_SDTTBL_ETCAM_T sdt_etcam_info = {0};  /*SDT内容*/
-
-    ZXIC_UINT8 *data_buff = NULL;
-    ZXIC_UINT8 *mask_buff = NULL;
-    ZXIC_UINT32 *eram_buff = NULL;
-    DPP_DTB_ACL_ENTRY_INFO_T *p_entry_arr = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get");
-
-    etcam_key_mode = sdt_etcam_info.etcam_key_mode;
-    as_enable = sdt_etcam_info.as_en;
-    etcam_table_depth = sdt_etcam_info.etcam_table_depth;
-
-    data_byte_size = DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode);//80/40
-
-    //组装数据
-    p_entry_arr = (DPP_DTB_ACL_ENTRY_INFO_T *)ZXIC_COMM_MALLOC(etcam_table_depth * sizeof(DPP_DTB_ACL_ENTRY_INFO_T));
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_arr);
-    ZXIC_COMM_MEMSET(p_entry_arr, 0, etcam_table_depth * sizeof(DPP_DTB_ACL_ENTRY_INFO_T));
-
-    data_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(data_byte_size * sizeof(ZXIC_UINT8));
-    ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE_NO_ASSERT(DEV_ID(dev), data_buff, p_entry_arr);
-    ZXIC_COMM_MEMSET(data_buff, 0, data_byte_size * sizeof(ZXIC_UINT8));
-
-    mask_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(data_byte_size * sizeof(ZXIC_UINT8));
-    ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE2PTR_NO_ASSERT(DEV_ID(dev), mask_buff, p_entry_arr, data_buff);
-    ZXIC_COMM_MEMSET(mask_buff, 0, data_byte_size * sizeof(ZXIC_UINT8));
-
-    if(as_enable)
-    {
-        eram_buff = (ZXIC_UINT32 *)ZXIC_COMM_MALLOC(4 * sizeof(ZXIC_UINT32));
-        ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE3PTR_NO_ASSERT(0, eram_buff, mask_buff, p_entry_arr, data_buff);
-        ZXIC_COMM_MEMSET(eram_buff, 0, 4 * sizeof(ZXIC_UINT32));
-    }
-
-    for(index = 0; index < etcam_table_depth; index++)
-    {
-        p_entry_arr[index].handle = index;
-        p_entry_arr[index].key_data = data_buff;
-        p_entry_arr[index].key_mask = mask_buff;
-
-        if(as_enable)
-        {
-            p_entry_arr[index].p_as_rslt = (ZXIC_UINT8 *)eram_buff;
-        }
-    }
-
-    rc = dpp_dtb_acl_dma_insert(dev,
-                            queue_id,
-                            sdt_no,
-                            etcam_table_depth,
-                            p_entry_arr,
-                            &element_id);
-    ZXIC_COMM_FREE(data_buff);
-    ZXIC_COMM_FREE(mask_buff);
-    if(eram_buff)
-    {
-        ZXIC_COMM_FREE(eram_buff);
-    }
-    ZXIC_COMM_FREE(p_entry_arr);
-    ZXIC_COMM_CHECK_DEV_RC(0, rc, "dpp_dtb_acl_dma_insert");
-    
-    return rc;
+/** DTB etcam 整个流表清空Flush
+ * @param   devId      NP设备号
+ * @param   queueId    DTB队列编号
+ * @param   sdtNo      流表std号
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/07/03
+ ************************************************************/
+DPP_STATUS dpp_dtb_etcam_table_flush(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									 ZXIC_UINT32 sdt_no)
+{
+	// 按照std 号的深度进行etcam的内容的清理；
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 data_byte_size = 0;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 etcam_key_mode = 0;
+	ZXIC_UINT32 as_enable = 0;
+	ZXIC_UINT32 etcam_table_depth = 0;
+	ZXIC_UINT32 element_id = 0;
+
+	DPP_SDTTBL_ETCAM_T sdt_etcam_info = { 0 }; /*SDT内容*/
+
+	ZXIC_UINT8 *data_buff = NULL;
+	ZXIC_UINT8 *mask_buff = NULL;
+	ZXIC_UINT32 *eram_buff = NULL;
+	DPP_DTB_ACL_ENTRY_INFO_T *p_entry_arr = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get");
+
+	etcam_key_mode = sdt_etcam_info.etcam_key_mode;
+	as_enable = sdt_etcam_info.as_en;
+	etcam_table_depth = sdt_etcam_info.etcam_table_depth;
+
+	data_byte_size = DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode); // 80/40
+
+	//组装数据
+	p_entry_arr = (DPP_DTB_ACL_ENTRY_INFO_T *)ZXIC_COMM_MALLOC(
+			etcam_table_depth * sizeof(DPP_DTB_ACL_ENTRY_INFO_T));
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_entry_arr);
+	ZXIC_COMM_MEMSET(p_entry_arr, 0,
+					 etcam_table_depth * sizeof(DPP_DTB_ACL_ENTRY_INFO_T));
+
+	data_buff =
+			(ZXIC_UINT8 *)ZXIC_COMM_MALLOC(data_byte_size * sizeof(ZXIC_UINT8));
+	ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE_NO_ASSERT(DEV_ID(dev), data_buff,
+													p_entry_arr);
+	ZXIC_COMM_MEMSET(data_buff, 0, data_byte_size * sizeof(ZXIC_UINT8));
+
+	mask_buff =
+			(ZXIC_UINT8 *)ZXIC_COMM_MALLOC(data_byte_size * sizeof(ZXIC_UINT8));
+	ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE2PTR_NO_ASSERT(DEV_ID(dev), mask_buff,
+														p_entry_arr, data_buff);
+	ZXIC_COMM_MEMSET(mask_buff, 0, data_byte_size * sizeof(ZXIC_UINT8));
+
+	if (as_enable) {
+		eram_buff = (ZXIC_UINT32 *)ZXIC_COMM_MALLOC(4 * sizeof(ZXIC_UINT32));
+		ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE3PTR_NO_ASSERT(
+				0, eram_buff, mask_buff, p_entry_arr, data_buff);
+		ZXIC_COMM_MEMSET(eram_buff, 0, 4 * sizeof(ZXIC_UINT32));
+	}
+
+	for (index = 0; index < etcam_table_depth; index++) {
+		p_entry_arr[index].handle = index;
+		p_entry_arr[index].key_data = data_buff;
+		p_entry_arr[index].key_mask = mask_buff;
+
+		if (as_enable) {
+			p_entry_arr[index].p_as_rslt = (ZXIC_UINT8 *)eram_buff;
+		}
+	}
+
+	rc = dpp_dtb_acl_dma_insert(dev, queue_id, sdt_no, etcam_table_depth,
+								p_entry_arr, &element_id);
+	ZXIC_COMM_FREE(data_buff);
+	ZXIC_COMM_FREE(mask_buff);
+	if (eram_buff) {
+		ZXIC_COMM_FREE(eram_buff);
+	}
+	ZXIC_COMM_FREE(p_entry_arr);
+	ZXIC_COMM_CHECK_DEV_RC(0, rc, "dpp_dtb_acl_dma_insert");
+
+	return rc;
 }
 
 #endif
@@ -6425,954 +6091,967 @@ DPP_STATUS dpp_dtb_etcam_table_flush(DPP_DEV_T *dev,
 
 /***********************************************************/
 /** 根据队列号和sdt号分配元素id和dma地址
-* @param   dev_id         设备id   
-* @param   queue_id       队列id 0~127
-* @param   sdt_no         sdt号  0~255
-* @param   element_id     出参，元素id
-* @return
-* @remark  无
-* @see
-* @author  cq      @date  2023/08/22
-************************************************************/  
-DPP_STATUS dpp_dtb_dump_addr_set(DPP_DEV_T *dev,
-                                 ZXIC_UINT32 queue_id,
-                                 ZXIC_UINT32 sdt_no, 
-                                 ZXIC_UINT32 *element_id)
+ * @param   dev_id         设备id
+ * @param   queue_id       队列id 0~127
+ * @param   sdt_no         sdt号  0~255
+ * @param   element_id     出参，元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/22
+ ************************************************************/
+DPP_STATUS dpp_dtb_dump_addr_set(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								 ZXIC_UINT32 sdt_no, ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 dump_element_id = 0;
-    ZXIC_UINT64 phy_addr = 0;
-    ZXIC_UINT64 vir_addr = 0;
-    ZXIC_UINT32 size     = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-
-    /*获取dump目的地址*/
-    rc = dpp_dtb_dump_sdt_addr_get( dev,
-                                    queue_id,  
-                                    sdt_no, 
-                                    &phy_addr, 
-                                    &vir_addr, 
-                                    &size);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_sdt_addr_get");
-    ZXIC_COMM_MEMSET((ZXIC_UINT8 *)vir_addr, 0, size);
-    
-    /*获取队列可用元素*/
-    rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &dump_element_id);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_free_item_get");
-    ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "table up item queue_element_id is: %d.\n",dump_element_id);
-
-    /*在相应队列的元素上配置用户dma地址信息*/
-    rc = dpp_dtb_tab_up_item_user_addr_set(dev,
-                                           queue_id,
-                                           dump_element_id,
-                                           phy_addr,
-                                           vir_addr);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_set"); 
-
-    *element_id = dump_element_id;
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 dump_element_id = 0;
+	ZXIC_UINT64 phy_addr = 0;
+	ZXIC_UINT64 vir_addr = 0;
+	ZXIC_UINT32 size = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+
+	/*获取dump目的地址*/
+	rc = dpp_dtb_dump_sdt_addr_get(dev, queue_id, sdt_no, &phy_addr, &vir_addr,
+								   &size);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_sdt_addr_get");
+	ZXIC_COMM_MEMSET((ZXIC_UINT8 *)vir_addr, 0, size);
+
+	/*获取队列可用元素*/
+	rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &dump_element_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_free_item_get");
+	ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev),
+							 "table up item queue_element_id is: %d.\n",
+							 dump_element_id);
+
+	/*在相应队列的元素上配置用户dma地址信息*/
+	rc = dpp_dtb_tab_up_item_user_addr_set(dev, queue_id, dump_element_id,
+										   phy_addr, vir_addr);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_set");
+
+	*element_id = dump_element_id;
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 将dump数据解析为hash条目格式
-* @param   p_hash_entry_cfg  hash配置参数   
-* @param   item_type         条目类型,见枚举SE_ITEM_TYPE
-* @param   pdata             dump数据
-* @param   dump_len          dump有效长度
-* @param   pOutData          出参，连续内存，hash条目信息DPP_HASH_ENTRY
-* @param   p_item_num        出参，解析出的hash有效条目数
-* @return
-* @remark  无
-* @see
-* @author  cq      @date  2023/08/22
-************************************************************/  
+ * @param   p_hash_entry_cfg  hash配置参数
+ * @param   item_type         条目类型,见枚举SE_ITEM_TYPE
+ * @param   pdata             dump数据
+ * @param   dump_len          dump有效长度
+ * @param   pOutData          出参，连续内存，hash条目信息DPP_HASH_ENTRY
+ * @param   p_item_num        出参，解析出的hash有效条目数
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/22
+ ************************************************************/
 DPP_STATUS dpp_dtb_dump_hash_parse(HASH_ENTRY_CFG *p_hash_entry_cfg,
-                                    ZXIC_UINT32 item_type,
-                                    ZXIC_UINT8 *pdata,
-                                    ZXIC_UINT32 dump_len,
-                                    ZXIC_UINT8 *pOutData,
-                                    ZXIC_UINT32 *p_item_num)
+								   ZXIC_UINT32 item_type, ZXIC_UINT8 *pdata,
+								   ZXIC_UINT32 dump_len, ZXIC_UINT8 *pOutData,
+								   ZXIC_UINT32 *p_item_num)
 {
-    ZXIC_UINT32 item_num = 0;
-    ZXIC_UINT32 data_offset = 0;
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT8 temp_key_valid = 0;
-    ZXIC_UINT8 temp_key_type = 0;
-    ZXIC_UINT8 temp_tbl_id   = 0;
-    ZXIC_UINT32 srh_entry_size = 0;
-    ZXIC_UINT32 item_width = SE_ITEM_WIDTH_MAX;
-    ZXIC_UINT8 *p_temp_key = NULL;
-    ZXIC_UINT8 *p_hash_item = NULL;
-    DPP_HASH_ENTRY  *p_dtb_hash_entry = NULL;
-    DPP_HASH_ENTRY  *p_temp_entry = NULL;
-    
-    ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
-    ZXIC_COMM_CHECK_POINT(pdata);
-    ZXIC_COMM_CHECK_POINT(pOutData);
-    ZXIC_COMM_CHECK_POINT(p_item_num);
-
-    if (ITEM_DDR_256 == item_type)
-    {
-        item_width = item_width / 2;
-    }
-
-    p_dtb_hash_entry = (DPP_HASH_ENTRY *)pOutData;
-    srh_entry_size = DPP_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type);
-    
-    for(index = 0; index < (dump_len / item_width); index++)
-    {
-        data_offset = 0;
-        p_hash_item = pdata + index * item_width;
-        while(data_offset < item_width)
-        {
-            p_temp_key = p_hash_item + data_offset;
-            temp_key_valid = DPP_GET_HASH_KEY_VALID(p_temp_key);
-            temp_key_type = DPP_GET_HASH_KEY_TYPE(p_temp_key);
-            temp_tbl_id = DPP_GET_HASH_TBL_ID(p_temp_key);
-            p_temp_entry = p_dtb_hash_entry + item_num;
-            ZXIC_COMM_CHECK_POINT(p_temp_entry);
-            ZXIC_COMM_CHECK_POINT(p_temp_entry->p_key);
-            ZXIC_COMM_CHECK_POINT(p_temp_entry->p_rst);
-            if(temp_key_valid && (temp_key_type == p_hash_entry_cfg->key_type) 
-               && (temp_tbl_id == p_hash_entry_cfg->table_id))
-            {
-                ZXIC_COMM_MEMCPY(p_temp_entry->p_key, p_temp_key, p_hash_entry_cfg->key_by_size + 1); 
-                ZXIC_COMM_MEMCPY(p_temp_entry->p_rst, p_temp_key + 1 + p_hash_entry_cfg->key_by_size, p_hash_entry_cfg->rst_by_size);
-                item_num++;
-            }
-            
-            data_offset += srh_entry_size;
-        }
-    }
-
-    *p_item_num = item_num;
-    return DPP_OK;
+	ZXIC_UINT32 item_num = 0;
+	ZXIC_UINT32 data_offset = 0;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT8 temp_key_valid = 0;
+	ZXIC_UINT8 temp_key_type = 0;
+	ZXIC_UINT8 temp_tbl_id = 0;
+	ZXIC_UINT32 srh_entry_size = 0;
+	ZXIC_UINT32 item_width = SE_ITEM_WIDTH_MAX;
+	ZXIC_UINT8 *p_temp_key = NULL;
+	ZXIC_UINT8 *p_hash_item = NULL;
+	DPP_HASH_ENTRY *p_dtb_hash_entry = NULL;
+	DPP_HASH_ENTRY *p_temp_entry = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
+	ZXIC_COMM_CHECK_POINT(pdata);
+	ZXIC_COMM_CHECK_POINT(pOutData);
+	ZXIC_COMM_CHECK_POINT(p_item_num);
+
+	if (ITEM_DDR_256 == item_type) {
+		item_width = item_width / 2;
+	}
+
+	p_dtb_hash_entry = (DPP_HASH_ENTRY *)pOutData;
+	srh_entry_size = DPP_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type);
+
+	for (index = 0; index < (dump_len / item_width); index++) {
+		data_offset = 0;
+		p_hash_item = pdata + index * item_width;
+		while (data_offset < item_width) {
+			p_temp_key = p_hash_item + data_offset;
+			temp_key_valid = DPP_GET_HASH_KEY_VALID(p_temp_key);
+			temp_key_type = DPP_GET_HASH_KEY_TYPE(p_temp_key);
+			temp_tbl_id = DPP_GET_HASH_TBL_ID(p_temp_key);
+			p_temp_entry = p_dtb_hash_entry + item_num;
+			ZXIC_COMM_CHECK_POINT(p_temp_entry);
+			ZXIC_COMM_CHECK_POINT(p_temp_entry->p_key);
+			ZXIC_COMM_CHECK_POINT(p_temp_entry->p_rst);
+			if (temp_key_valid &&
+				(temp_key_type == p_hash_entry_cfg->key_type) &&
+				(temp_tbl_id == p_hash_entry_cfg->table_id)) {
+				ZXIC_COMM_MEMCPY(p_temp_entry->p_key, p_temp_key,
+								 p_hash_entry_cfg->key_by_size + 1);
+				ZXIC_COMM_MEMCPY(p_temp_entry->p_rst,
+								 p_temp_key + 1 + p_hash_entry_cfg->key_by_size,
+								 p_hash_entry_cfg->rst_by_size);
+				item_num++;
+			}
+
+			data_offset += srh_entry_size;
+		}
+	}
+
+	*p_item_num = item_num;
+	return DPP_OK;
 }
 
 /** dtb dump eram整个表项内容 输入128bit单位index，输出128bit为单位的数据
-* @param   dev_id      设备号
-* @param   queue_id    队列号
-* @param   sdt_no      eram表sdt表号
-* @param   start_index 要dump的起始index 单位是128bit
-* @param   depth       dump的深度以128bit为单位
-* @param   p_data      dump出数据缓存(大小128bit * depth)
-* @param   element_id   返回下表使用的元素id
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
-DPP_STATUS dpp_dtb_sdt_eram_table_dump(DPP_DEV_T *dev, 
-                                      ZXIC_UINT32 queue_id, 
-                                      ZXIC_UINT32 sdt_no, 
-                                      ZXIC_UINT32 start_index, 
-                                      ZXIC_UINT32 depth,
-                                      ZXIC_UINT32 *p_data,
-                                      ZXIC_UINT32 *element_id
-                                      )
+ * @param   dev_id      设备号
+ * @param   queue_id    队列号
+ * @param   sdt_no      eram表sdt表号
+ * @param   start_index 要dump的起始index 单位是128bit
+ * @param   depth       dump的深度以128bit为单位
+ * @param   p_data      dump出数据缓存(大小128bit * depth)
+ * @param   element_id   返回下表使用的元素id
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_sdt_eram_table_dump(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									   ZXIC_UINT32 sdt_no,
+									   ZXIC_UINT32 start_index,
+									   ZXIC_UINT32 depth, ZXIC_UINT32 *p_data,
+									   ZXIC_UINT32 *element_id)
 {
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 eram_base_addr  = 0;
-    ZXIC_UINT32 dump_addr_128bit = 0;
-    ZXIC_UINT32 dump_item_index = 0;
-    ZXIC_UINT32 dump_data_len = 0;
-    ZXIC_UINT32 dump_desc_len = 0;
-
-    ZXIC_ADDR_T dump_sdt_phy_addr = 0;
-    ZXIC_ADDR_T dump_sdt_vir_addr = 0;
-    ZXIC_UINT32 dump_addr_size = 0;
-
-    ZXIC_UINT32 dump_dst_phy_haddr = 0;
-    ZXIC_UINT32 dump_dst_phy_laddr = 0;
-
-    ZXIC_UINT8 form_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0};
-
-    /*获取sdt信息*/
-    DPP_SDTTBL_ERAM_T sdt_eram    = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), element_id);
-
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_eram);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
-
-    eram_base_addr = sdt_eram.eram_base_addr;
-    dump_addr_128bit = eram_base_addr + start_index;
-
-    //获取dump目的地址
-    rc = dpp_dtb_dump_sdt_addr_get( dev,
-                                    queue_id,  
-                                    sdt_no, 
-                                    &dump_sdt_phy_addr, 
-                                    &dump_sdt_vir_addr, 
-                                    &dump_addr_size);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_sdt_addr_get"); 
-
-    ZXIC_COMM_MEMSET((ZXIC_UINT8 *)dump_sdt_vir_addr, 0, dump_addr_size);
-
-    rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &dump_item_index);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_free_item_get");
-    ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "dump queue id %d, element_id is: %d.\n",queue_id, dump_item_index);
-
-    *element_id = dump_item_index;//保存获取的item_index
-
-    ZXIC_COMM_TRACE_INFO("eram dump eram_base_addr %x\n",eram_base_addr);
-    ZXIC_COMM_TRACE_INFO("eram dump start_index %x\n",start_index);
-    ZXIC_COMM_TRACE_INFO("eram dump queue %d,item_index: %d\n",queue_id, dump_item_index);
-
-    //在相应队列的元素上配置用户dma地址信息
-    rc = dpp_dtb_tab_up_item_user_addr_set(dev,
-                                           queue_id,
-                                           dump_item_index,
-                                           dump_sdt_phy_addr,
-                                           dump_sdt_vir_addr);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_set"); 
-
-    /*获取地址*/
-    rc = dpp_dtb_tab_up_item_addr_get(dev, queue_id, dump_item_index, &dump_dst_phy_haddr, &dump_dst_phy_laddr);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get");
-    
-    rc = dpp_dtb_smmu0_dump_info_write(dev,
-                                       dump_addr_128bit,
-                                       depth,
-                                       dump_dst_phy_haddr,
-                                       dump_dst_phy_laddr,
-                                       (ZXIC_UINT32 *)form_buff);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_dump_info_write");
-
-    /*组装下表命令格式*/
-    dump_data_len = depth * 128 / 32;
-    dump_desc_len = DTB_LEN_POS_SETP / 4;
-
-    if(dump_data_len * 4 > dump_addr_size)
-    {
-        ZXIC_COMM_TRACE_ERROR("eram dump size is too small!\n");
-        return DPP_RC_DTB_DUMP_SIZE_SMALL;
-    }
-
-    rc = dpp_dtb_write_dump_desc_info(dev, queue_id, dump_item_index, (ZXIC_UINT32 *)form_buff, dump_data_len, dump_desc_len, p_data);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_desc_info");
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 eram_base_addr = 0;
+	ZXIC_UINT32 dump_addr_128bit = 0;
+	ZXIC_UINT32 dump_item_index = 0;
+	ZXIC_UINT32 dump_data_len = 0;
+	ZXIC_UINT32 dump_desc_len = 0;
+
+	ZXIC_ADDR_T dump_sdt_phy_addr = 0;
+	ZXIC_ADDR_T dump_sdt_vir_addr = 0;
+	ZXIC_UINT32 dump_addr_size = 0;
+
+	ZXIC_UINT32 dump_dst_phy_haddr = 0;
+	ZXIC_UINT32 dump_dst_phy_laddr = 0;
+
+	ZXIC_UINT8 form_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = { 0 };
+
+	/*获取sdt信息*/
+	DPP_SDTTBL_ERAM_T sdt_eram = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), element_id);
+
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_eram);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
+
+	eram_base_addr = sdt_eram.eram_base_addr;
+	dump_addr_128bit = eram_base_addr + start_index;
+
+	//获取dump目的地址
+	rc = dpp_dtb_dump_sdt_addr_get(dev, queue_id, sdt_no, &dump_sdt_phy_addr,
+								   &dump_sdt_vir_addr, &dump_addr_size);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_sdt_addr_get");
+
+	ZXIC_COMM_MEMSET((ZXIC_UINT8 *)dump_sdt_vir_addr, 0, dump_addr_size);
+
+	rc = dpp_dtb_tab_up_free_item_get(dev, queue_id, &dump_item_index);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_free_item_get");
+	ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev),
+							  "dump queue id %d, element_id is: %d.\n",
+							  queue_id, dump_item_index);
+
+	*element_id = dump_item_index; //保存获取的item_index
+
+	ZXIC_COMM_TRACE_INFO("eram dump eram_base_addr %x\n", eram_base_addr);
+	ZXIC_COMM_TRACE_INFO("eram dump start_index %x\n", start_index);
+	ZXIC_COMM_TRACE_INFO("eram dump queue %d,item_index: %d\n", queue_id,
+						 dump_item_index);
+
+	//在相应队列的元素上配置用户dma地址信息
+	rc = dpp_dtb_tab_up_item_user_addr_set(dev, queue_id, dump_item_index,
+										   dump_sdt_phy_addr,
+										   dump_sdt_vir_addr);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_set");
+
+	/*获取地址*/
+	rc = dpp_dtb_tab_up_item_addr_get(dev, queue_id, dump_item_index,
+									  &dump_dst_phy_haddr, &dump_dst_phy_laddr);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get");
+
+	rc = dpp_dtb_smmu0_dump_info_write(dev, dump_addr_128bit, depth,
+									   dump_dst_phy_haddr, dump_dst_phy_laddr,
+									   (ZXIC_UINT32 *)form_buff);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_smmu0_dump_info_write");
+
+	/*组装下表命令格式*/
+	dump_data_len = depth * 128 / 32;
+	dump_desc_len = DTB_LEN_POS_SETP / 4;
+
+	if (dump_data_len * 4 > dump_addr_size) {
+		ZXIC_COMM_TRACE_ERROR("eram dump size is too small!\n");
+		return DPP_RC_DTB_DUMP_SIZE_SMALL;
+	}
+
+	rc = dpp_dtb_write_dump_desc_info(dev, queue_id, dump_item_index,
+									  (ZXIC_UINT32 *)form_buff, dump_data_len,
+									  dump_desc_len, p_data);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_write_dump_desc_info");
+
+	return DPP_OK;
 }
 
 /** dtb dump eram直接表表项内容 支持64bit/128bit
-* @param   dev_id    设备号
-* @param   queue_id  队列号
-* @param   sdt_no    eram表sdt表号
-* @param   start_index 要dump的起始index，单位是sdt_no该表的mode
-* @param   p_dump_data_arr 本次dump出的数据，数据格式与下表格式相同
-* @param   entry_num       本次dump实际的条目数
-* @param   next_start_index  下次dump是开始的index  
-* @param   finish_flag       整个表dump完成标志，1表示完成，0表示未完成
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
- DPP_STATUS dpp_dtb_eram_table_dump(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 queue_id,
-                                    ZXIC_UINT32 sdt_no,
-                                    DPP_DTB_DUMP_INDEX_T start_index,
-                                    DPP_DTB_ERAM_ENTRY_INFO_T* p_dump_data_arr,
-                                    ZXIC_UINT32 *entry_num,
-                                    DPP_DTB_DUMP_INDEX_T *next_start_index,
-                                    ZXIC_UINT32 *finish_flag)
+ * @param   dev_id    设备号
+ * @param   queue_id  队列号
+ * @param   sdt_no    eram表sdt表号
+ * @param   start_index 要dump的起始index，单位是sdt_no该表的mode
+ * @param   p_dump_data_arr 本次dump出的数据，数据格式与下表格式相同
+ * @param   entry_num       本次dump实际的条目数
+ * @param   next_start_index  下次dump是开始的index
+ * @param   finish_flag       整个表dump完成标志，1表示完成，0表示未完成
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_eram_table_dump(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								   ZXIC_UINT32 sdt_no,
+								   DPP_DTB_DUMP_INDEX_T start_index,
+								   DPP_DTB_ERAM_ENTRY_INFO_T *p_dump_data_arr,
+								   ZXIC_UINT32 *entry_num,
+								   DPP_DTB_DUMP_INDEX_T *next_start_index,
+								   ZXIC_UINT32 *finish_flag)
 {
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 dump_mode = 0;
-    ZXIC_UINT32 eram_table_depth = 0;
-    ZXIC_UINT32 start_index_128bit = 0;
-    ZXIC_UINT32 row_index = 0;
-    ZXIC_UINT32 col_index = 0;
-    ZXIC_UINT32 dump_depth_128bit = 0;
-    ZXIC_UINT32 dump_depth = 0;
-    ZXIC_UINT32 element_id = 0;
-    ZXIC_UINT8* dump_data_buff = NULL;
-    ZXIC_UINT8* temp_data = NULL;
-    ZXIC_UINT32 remain = 0;
-    ZXIC_UINT32 *buff = NULL;
-
-    DPP_DTB_ERAM_ENTRY_INFO_T* p_dump_user_data = NULL;
-    DPP_SDTTBL_ERAM_T sdt_eram    = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_eram);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
-
-    dump_mode = sdt_eram.eram_mode;//0:1bit;2:64bit;3:128,
-    eram_table_depth = sdt_eram.eram_table_depth;
-
-    rc = dtb_eram_index_cal(dev, dump_mode, eram_table_depth, &dump_depth_128bit, &col_index);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal");
-
-    rc = dtb_eram_index_cal(dev, dump_mode, start_index.index, &start_index_128bit, &col_index);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal");
-
-    dump_depth = dump_depth_128bit - start_index_128bit;
-    
-    dump_data_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(dump_depth * DTB_LEN_POS_SETP);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), dump_data_buff);
-    ZXIC_COMM_MEMSET(dump_data_buff, 0, dump_depth * DTB_LEN_POS_SETP);
-
-    rc = dpp_dtb_sdt_eram_table_dump(dev, 
-                                queue_id, 
-                                sdt_no, 
-                                start_index_128bit, 
-                                dump_depth, 
-                                (ZXIC_UINT32 *)dump_data_buff, 
-                                &element_id);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_sdt_eram_table_dump", dump_data_buff);
-    ZXIC_COMM_TRACE_INFO(" dpp_dtb_sdt_eram_table_dump done queue %d element %d.\n", queue_id, element_id);
-
-    if (dump_mode == ERAM128_TBL_128b)
-    {
-        for(i = 0; i < dump_depth; i++)
-        {
-            p_dump_user_data = p_dump_data_arr + i;
-            temp_data = dump_data_buff + i * DTB_LEN_POS_SETP;
-            if ((p_dump_user_data == NULL) || (p_dump_user_data->p_data == NULL))
-            {
-                ZXIC_COMM_TRACE_ERROR("eram index 0x%x data user buff is NULL!\n",start_index.index + i);
-                ZXIC_COMM_FREE(dump_data_buff);
-                return DPP_ERR;
-            }
-            
-            p_dump_user_data->index = start_index.index + i;
-            ZXIC_COMM_MEMCPY(p_dump_user_data->p_data, temp_data, (128 / 8));
-        }
-    }
-    else if(dump_mode == ERAM128_TBL_64b)
-    {
-        remain =  start_index.index % 2;
-        for(i = 0; i < eram_table_depth - start_index.index; i++)
-        {
-            rc = dtb_eram_index_cal(dev, dump_mode, remain, &row_index, &col_index);
-            ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dtb_eram_index_cal", dump_data_buff);
-            temp_data = dump_data_buff + row_index * DTB_LEN_POS_SETP;
-
-            buff = (ZXIC_UINT32*)temp_data;
-            p_dump_user_data = p_dump_data_arr + i;
-            if (p_dump_user_data->p_data == NULL)
-            {
-                ZXIC_COMM_TRACE_ERROR("eram index 0x%x data point is NULL!\n",start_index.index + i);
-                ZXIC_COMM_FREE(dump_data_buff);
-                return DPP_ERR;
-            }
-
-            p_dump_user_data->index = start_index.index + i;
-            ZXIC_COMM_MEMCPY(p_dump_user_data->p_data, buff + ((1 - col_index) << 1), (64 / 8));
-
-            remain ++;
-        }
-    }
-    
-    *entry_num = eram_table_depth - start_index.index;
-    *finish_flag = 1;
-    ZXIC_COMM_TRACE_INFO(" eram table dump entry num %d, finish flag %d\n\n", *entry_num, *finish_flag);
-
-    ZXIC_COMM_FREE(dump_data_buff);
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 dump_mode = 0;
+	ZXIC_UINT32 eram_table_depth = 0;
+	ZXIC_UINT32 start_index_128bit = 0;
+	ZXIC_UINT32 row_index = 0;
+	ZXIC_UINT32 col_index = 0;
+	ZXIC_UINT32 dump_depth_128bit = 0;
+	ZXIC_UINT32 dump_depth = 0;
+	ZXIC_UINT32 element_id = 0;
+	ZXIC_UINT8 *dump_data_buff = NULL;
+	ZXIC_UINT8 *temp_data = NULL;
+	ZXIC_UINT32 remain = 0;
+	ZXIC_UINT32 *buff = NULL;
+
+	DPP_DTB_ERAM_ENTRY_INFO_T *p_dump_user_data = NULL;
+	DPP_SDTTBL_ERAM_T sdt_eram = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_eram);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
+
+	dump_mode = sdt_eram.eram_mode; // 0:1bit;2:64bit;3:128,
+	eram_table_depth = sdt_eram.eram_table_depth;
+
+	rc = dtb_eram_index_cal(dev, dump_mode, eram_table_depth,
+							&dump_depth_128bit, &col_index);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal");
+
+	rc = dtb_eram_index_cal(dev, dump_mode, start_index.index,
+							&start_index_128bit, &col_index);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dtb_eram_index_cal");
+
+	dump_depth = dump_depth_128bit - start_index_128bit;
+
+	dump_data_buff =
+			(ZXIC_UINT8 *)ZXIC_COMM_MALLOC(dump_depth * DTB_LEN_POS_SETP);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), dump_data_buff);
+	ZXIC_COMM_MEMSET(dump_data_buff, 0, dump_depth * DTB_LEN_POS_SETP);
+
+	rc = dpp_dtb_sdt_eram_table_dump(dev, queue_id, sdt_no, start_index_128bit,
+									 dump_depth, (ZXIC_UINT32 *)dump_data_buff,
+									 &element_id);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_sdt_eram_table_dump",
+											 dump_data_buff);
+	ZXIC_COMM_TRACE_INFO(
+			" dpp_dtb_sdt_eram_table_dump done queue %d element %d.\n",
+			queue_id, element_id);
+
+	if (dump_mode == ERAM128_TBL_128b) {
+		for (i = 0; i < dump_depth; i++) {
+			p_dump_user_data = p_dump_data_arr + i;
+			temp_data = dump_data_buff + i * DTB_LEN_POS_SETP;
+			if ((p_dump_user_data == NULL) ||
+				(p_dump_user_data->p_data == NULL)) {
+				ZXIC_COMM_TRACE_ERROR(
+						"eram index 0x%x data user buff is NULL!\n",
+						start_index.index + i);
+				ZXIC_COMM_FREE(dump_data_buff);
+				return DPP_ERR;
+			}
+
+			p_dump_user_data->index = start_index.index + i;
+			ZXIC_COMM_MEMCPY(p_dump_user_data->p_data, temp_data, (128 / 8));
+		}
+	} else if (dump_mode == ERAM128_TBL_64b) {
+		remain = start_index.index % 2;
+		for (i = 0; i < eram_table_depth - start_index.index; i++) {
+			rc = dtb_eram_index_cal(dev, dump_mode, remain, &row_index,
+									&col_index);
+			ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dtb_eram_index_cal",
+													 dump_data_buff);
+			temp_data = dump_data_buff + row_index * DTB_LEN_POS_SETP;
+
+			buff = (ZXIC_UINT32 *)temp_data;
+			p_dump_user_data = p_dump_data_arr + i;
+
+			if (p_dump_user_data == NULL) {
+				ZXIC_COMM_TRACE_ERROR(
+						"eram index 0x%x data user buff is NULL!\n",
+						start_index.index + i);
+				ZXIC_COMM_FREE(dump_data_buff);
+				return DPP_ERR;
+			}
+
+			if (p_dump_user_data->p_data == NULL) {
+				ZXIC_COMM_TRACE_ERROR("eram index 0x%x data point is NULL!\n",
+									  start_index.index + i);
+				ZXIC_COMM_FREE(dump_data_buff);
+				return DPP_ERR;
+			}
+
+			p_dump_user_data->index = start_index.index + i;
+			ZXIC_COMM_MEMCPY(p_dump_user_data->p_data,
+							 buff + ((1 - col_index) << 1), (64 / 8));
+
+			remain++;
+		}
+	}
+
+	*entry_num = eram_table_depth - start_index.index;
+	*finish_flag = 1;
+	ZXIC_COMM_TRACE_INFO(" eram table dump entry num %d, finish flag %d\n\n",
+						 *entry_num, *finish_flag);
+
+	ZXIC_COMM_FREE(dump_data_buff);
+
+	return DPP_OK;
 }
 
-
 /***********************************************************/
 /** dump指定hash表占用的zcam数据
-* @param   dev_id         设备id   
-* @param   queue_id       队列id 0~127
-* @param   sdt_no         sdt号  0~255
-* @param   fun_id         需dump的zblock个数
-* @param   bulk_id        zblock索引
-* @param   p_data         出参，dump数据
-* @param   p_dump_len     出参，dump长度
-* @return
-* @remark  无
-* @see
-* @author  cq      @date  2023/08/22
-************************************************************/  
-DPP_STATUS dpp_dtb_sdt_hash_zcam_mono_space_dump(DPP_DEV_T *dev,
-                                                ZXIC_UINT32 queue_id,
-                                                ZXIC_UINT32 sdt_no, 
-                                                ZXIC_UINT32 fun_id,
-                                                ZXIC_UINT32 bulk_id,
-                                                ZXIC_UINT8  *p_data,
-                                                ZXIC_UINT32 *p_dump_len)
+ * @param   dev_id         设备id
+ * @param   queue_id       队列id 0~127
+ * @param   sdt_no         sdt号  0~255
+ * @param   fun_id         需dump的zblock个数
+ * @param   bulk_id        zblock索引
+ * @param   p_data         出参，dump数据
+ * @param   p_dump_len     出参，dump长度
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/22
+ ************************************************************/
+DPP_STATUS
+dpp_dtb_sdt_hash_zcam_mono_space_dump(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									  ZXIC_UINT32 sdt_no, ZXIC_UINT32 fun_id,
+									  ZXIC_UINT32 bulk_id, ZXIC_UINT8 *p_data,
+									  ZXIC_UINT32 *p_dump_len)
 {
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 zblock_id = 0;
-    ZXIC_UINT32 zcell_id   = 0;
-    ZXIC_UINT32 start_addr  = 0;
-    ZXIC_UINT32 dtb_desc_len = 0;
-    ZXIC_UINT32 dump_pa_h   = 0;
-    ZXIC_UINT32 dump_pa_l   = 0;
-    ZXIC_UINT32 dma_addr_offset = 0;
-    ZXIC_UINT32 desc_addr_offset = 0;
-    ZXIC_UINT32 element_id  = 0;
-    ZXIC_UINT8  *p_dump_desc_buf = NULL;
-
-    DPP_SE_CFG *p_se_cfg = NULL;
-    D_NODE *p_zblk_dn = NULL;
-    SE_ZBLK_CFG *p_zblk = NULL;
-    SE_ZREG_CFG *p_zreg = NULL;
-    SE_ZCELL_CFG *p_zcell = NULL;
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    FUNC_ID_INFO *p_func_info = NULL;
-
-    DPP_DTB_ENTRY_T   dtb_dump_entry = {0};
-    ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), fun_id, 0, HASH_FUNC_ID_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), bulk_id, 0, HASH_BULK_NUM - 1);
-    ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_POINT(p_data);
-    ZXIC_COMM_CHECK_POINT(p_dump_len);
-
-    rc = dpp_dtb_dump_addr_set(dev, queue_id, sdt_no, &element_id);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_addr_set");
-
-    p_dump_desc_buf = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8));
-    ZXIC_COMM_CHECK_POINT(p_dump_desc_buf);
-    ZXIC_COMM_MEMSET(p_dump_desc_buf, 0, DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8));
-
-    dtb_dump_entry.cmd = cmd_buff;
-
-    rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE_NO_ASSERT(DEV_ID(dev), rc, "dpp_se_cfg_get", p_dump_desc_buf);
-    ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE_NO_ASSERT(DEV_ID(dev), p_se_cfg, p_dump_desc_buf);
-    
-    p_func_info = DPP_GET_FUN_INFO(p_se_cfg, fun_id);
-    DPP_SE_CHECK_FUN_MEMORY_FREE(p_func_info, fun_id, FUN_HASH, p_dump_desc_buf);
-    p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg);
-    p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next;
-
-    while (p_zblk_dn)
-    {
-        p_zblk = (SE_ZBLK_CFG *)p_zblk_dn->data;
-        zblock_id = p_zblk->zblk_idx;
-
-        //mono zcell dump
-        for (i = 0; i < SE_ZCELL_NUM; i++)
-        {
-            p_zcell = &(p_zblk->zcell_info[i]);
-
-            if ((p_zcell->flag & DPP_ZCELL_FLAG_IS_MONO) && (p_zcell->bulk_id == bulk_id))
-            {
-                zcell_id = p_zcell->zcell_idx;
-
-                start_addr = ZBLK_ITEM_ADDR_CALC(zcell_id, 0);
-
-                /*获取dma上送指定条目的物理地址*/
-                rc = dpp_dtb_tab_up_item_offset_addr_get(dev,
-                                                         queue_id,
-                                                         element_id,
-                                                         dma_addr_offset,
-                                                         &dump_pa_h,
-                                                         &dump_pa_l);
-                ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_item_offset_addr_get",p_dump_desc_buf);
-
-                rc = dpp_dtb_zcam_dump_entry(dev, start_addr, DTB_DUMP_ZCAM_512b, SE_RAM_DEPTH, dump_pa_h, dump_pa_l, &dtb_dump_entry);
-                ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_zcam_dump_entry",p_dump_desc_buf);
-
-                rc = dpp_dtb_data_write(p_dump_desc_buf, desc_addr_offset, &dtb_dump_entry);
-                ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_zcam_dump_entry",p_dump_desc_buf);
-
-                dtb_desc_len++;
-                dma_addr_offset += SE_RAM_DEPTH * 512 / 8;
-                desc_addr_offset += DTB_LEN_POS_SETP;
-
-                ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "the Zblock[%d]'s bulk_id:%d Mono Zcell_id :%d \n", zblock_id, bulk_id, zcell_id);
-            }
-        }
-
-        //mono zreg dump
-        for (i = 0; i < SE_ZREG_NUM; i++)
-        {
-            p_zreg = &(p_zblk->zreg_info[i]);
-
-            if ((p_zreg->flag & DPP_ZREG_FLAG_IS_MONO) && (p_zreg->bulk_id == bulk_id))
-            {   
-                start_addr = ZBLK_HASH_LIST_REG_ADDR_CALC(zblock_id, i);
-
-                rc = dpp_dtb_tab_up_item_offset_addr_get(dev,
-                                                        queue_id,
-                                                        element_id,
-                                                        dma_addr_offset,
-                                                        &dump_pa_h,
-                                                        &dump_pa_l);
-                ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_item_offset_addr_get",p_dump_desc_buf);
-
-                rc = dpp_dtb_zcam_dump_entry(dev, start_addr, DTB_DUMP_ZCAM_512b, 1, dump_pa_h, dump_pa_l, &dtb_dump_entry);
-                ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_zcam_dump_entry",p_dump_desc_buf);
-
-                rc = dpp_dtb_data_write(p_dump_desc_buf, desc_addr_offset, &dtb_dump_entry);
-                ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_zcam_dump_entry",p_dump_desc_buf);
-
-                dtb_desc_len++;
-                dma_addr_offset += 512 / 8;
-                desc_addr_offset += DTB_LEN_POS_SETP;
-
-                ZXIC_COMM_TRACE_DEV_INFO(DEV_ID(dev), "the Zblock[%d]'s bulk_id:%d Mono Zreg_id :%d \n", zblock_id, p_zreg->bulk_id, i);
-            }
-        }
-
-        p_zblk_dn = p_zblk_dn->next;
-    }
-
-    rc = dpp_dtb_write_dump_desc_info(dev,
-                                      queue_id,
-                                      element_id,
-                                      (ZXIC_UINT32 *)p_dump_desc_buf,
-                                      dma_addr_offset / 4,
-                                      dtb_desc_len * 4,
-                                      (ZXIC_UINT32 *)p_data);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc,"dpp_dtb_write_dump_desc_info",p_dump_desc_buf);
-    ZXIC_COMM_TRACE_INFO(" dpp_dtb_hash_table_zcam_dump done queue %d element %d.\n", queue_id, element_id);
-    
-    zxic_comm_swap(p_data, dma_addr_offset);
-    ZXIC_COMM_FREE(p_dump_desc_buf);
-    
-    *p_dump_len = dma_addr_offset;
-    
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 zblock_id = 0;
+	ZXIC_UINT32 zcell_id = 0;
+	ZXIC_UINT32 start_addr = 0;
+	ZXIC_UINT32 dtb_desc_len = 0;
+	ZXIC_UINT32 dump_pa_h = 0;
+	ZXIC_UINT32 dump_pa_l = 0;
+	ZXIC_UINT32 dma_addr_offset = 0;
+	ZXIC_UINT32 desc_addr_offset = 0;
+	ZXIC_UINT32 element_id = 0;
+	ZXIC_UINT8 *p_dump_desc_buf = NULL;
+
+	DPP_SE_CFG *p_se_cfg = NULL;
+	D_NODE *p_zblk_dn = NULL;
+	SE_ZBLK_CFG *p_zblk = NULL;
+	SE_ZREG_CFG *p_zreg = NULL;
+	SE_ZCELL_CFG *p_zcell = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	FUNC_ID_INFO *p_func_info = NULL;
+
+	DPP_DTB_ENTRY_T dtb_dump_entry = { 0 };
+	ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), fun_id, 0, HASH_FUNC_ID_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), bulk_id, 0, HASH_BULK_NUM - 1);
+	ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(p_data);
+	ZXIC_COMM_CHECK_POINT(p_dump_len);
+
+	rc = dpp_dtb_dump_addr_set(dev, queue_id, sdt_no, &element_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_addr_set");
+
+	p_dump_desc_buf = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(
+			DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8));
+	ZXIC_COMM_CHECK_POINT(p_dump_desc_buf);
+	ZXIC_COMM_MEMSET(p_dump_desc_buf, 0,
+					 DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8));
+
+	dtb_dump_entry.cmd = cmd_buff;
+
+	rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg);
+	ZXIC_COMM_CHECK_DEV_RC_MEMORY_FREE_NO_ASSERT(
+			DEV_ID(dev), rc, "dpp_se_cfg_get", p_dump_desc_buf);
+	ZXIC_COMM_CHECK_DEV_POINT_MEMORY_FREE_NO_ASSERT(DEV_ID(dev), p_se_cfg,
+													p_dump_desc_buf);
+
+	p_func_info = DPP_GET_FUN_INFO(p_se_cfg, fun_id);
+	DPP_SE_CHECK_FUN_MEMORY_FREE(p_func_info, fun_id, FUN_HASH,
+								 p_dump_desc_buf);
+	p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg);
+	p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next;
+
+	while (p_zblk_dn) {
+		p_zblk = (SE_ZBLK_CFG *)p_zblk_dn->data;
+		zblock_id = p_zblk->zblk_idx;
+
+		// mono zcell dump
+		for (i = 0; i < SE_ZCELL_NUM; i++) {
+			p_zcell = &(p_zblk->zcell_info[i]);
+
+			if ((p_zcell->flag & DPP_ZCELL_FLAG_IS_MONO) &&
+				(p_zcell->bulk_id == bulk_id)) {
+				zcell_id = p_zcell->zcell_idx;
+
+				start_addr = ZBLK_ITEM_ADDR_CALC(zcell_id, 0);
+
+				/*获取dma上送指定条目的物理地址*/
+				rc = dpp_dtb_tab_up_item_offset_addr_get(
+						dev, queue_id, element_id, dma_addr_offset, &dump_pa_h,
+						&dump_pa_l);
+				ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+						rc, "dpp_dtb_tab_up_item_offset_addr_get",
+						p_dump_desc_buf);
+
+				rc = dpp_dtb_zcam_dump_entry(dev, start_addr,
+											 DTB_DUMP_ZCAM_512b, SE_RAM_DEPTH,
+											 dump_pa_h, dump_pa_l,
+											 &dtb_dump_entry);
+				ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+						rc, "dpp_dtb_zcam_dump_entry", p_dump_desc_buf);
+
+				rc = dpp_dtb_data_write(p_dump_desc_buf, desc_addr_offset,
+										&dtb_dump_entry);
+				ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+						rc, "dpp_dtb_zcam_dump_entry", p_dump_desc_buf);
+
+				dtb_desc_len++;
+				dma_addr_offset += SE_RAM_DEPTH * 512 / 8;
+				desc_addr_offset += DTB_LEN_POS_SETP;
+
+				ZXIC_COMM_TRACE_DEV_INFO(
+						DEV_ID(dev),
+						"the Zblock[%d]'s bulk_id:%d Mono Zcell_id :%d \n",
+						zblock_id, bulk_id, zcell_id);
+			}
+		}
+
+		// mono zreg dump
+		for (i = 0; i < SE_ZREG_NUM; i++) {
+			p_zreg = &(p_zblk->zreg_info[i]);
+
+			if ((p_zreg->flag & DPP_ZREG_FLAG_IS_MONO) &&
+				(p_zreg->bulk_id == bulk_id)) {
+				start_addr = ZBLK_HASH_LIST_REG_ADDR_CALC(zblock_id, i);
+
+				rc = dpp_dtb_tab_up_item_offset_addr_get(
+						dev, queue_id, element_id, dma_addr_offset, &dump_pa_h,
+						&dump_pa_l);
+				ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+						rc, "dpp_dtb_tab_up_item_offset_addr_get",
+						p_dump_desc_buf);
+
+				rc = dpp_dtb_zcam_dump_entry(dev, start_addr,
+											 DTB_DUMP_ZCAM_512b, 1, dump_pa_h,
+											 dump_pa_l, &dtb_dump_entry);
+				ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+						rc, "dpp_dtb_zcam_dump_entry", p_dump_desc_buf);
+
+				rc = dpp_dtb_data_write(p_dump_desc_buf, desc_addr_offset,
+										&dtb_dump_entry);
+				ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+						rc, "dpp_dtb_zcam_dump_entry", p_dump_desc_buf);
+
+				dtb_desc_len++;
+				dma_addr_offset += 512 / 8;
+				desc_addr_offset += DTB_LEN_POS_SETP;
+
+				ZXIC_COMM_TRACE_DEV_INFO(
+						DEV_ID(dev),
+						"the Zblock[%d]'s bulk_id:%d Mono Zreg_id :%d \n",
+						zblock_id, p_zreg->bulk_id, i);
+			}
+		}
+
+		p_zblk_dn = p_zblk_dn->next;
+	}
+
+	rc = dpp_dtb_write_dump_desc_info(dev, queue_id, element_id,
+									  (ZXIC_UINT32 *)p_dump_desc_buf,
+									  dma_addr_offset / 4, dtb_desc_len * 4,
+									  (ZXIC_UINT32 *)p_data);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_write_dump_desc_info",
+											 p_dump_desc_buf);
+	ZXIC_COMM_TRACE_INFO(
+			" dpp_dtb_hash_table_zcam_dump done queue %d element %d.\n",
+			queue_id, element_id);
+
+	zxic_comm_swap(p_data, dma_addr_offset);
+	ZXIC_COMM_FREE(p_dump_desc_buf);
+
+	*p_dump_len = dma_addr_offset;
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 只dump hash表的zcam内容
-* @param   dev_id         设备id   
-* @param   queue_id       队列id 0~127
-* @param   sdt_no         sdt号  0~255
-* @param   pDumpData      出参，dump数据，内存由用户分配，结构体DPP_HASH_ENTRY
-* @param   entryNum       出参，dump出的有效hash条目
-* @return
-* @remark  无
-* @see
-* @author  cq      @date  2023/08/22
-************************************************************/  
+ * @param   dev_id         设备id
+ * @param   queue_id       队列id 0~127
+ * @param   sdt_no         sdt号  0~255
+ * @param   pDumpData      出参，dump数据，内存由用户分配，结构体DPP_HASH_ENTRY
+ * @param   entryNum       出参，dump出的有效hash条目
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/22
+ ************************************************************/
 DPP_STATUS dpp_dtb_hash_table_only_zcam_dump(DPP_DEV_T *dev,
-                                            ZXIC_UINT32 queue_id,
-                                            ZXIC_UINT32 sdt_no,
-                                            ZXIC_UINT8* pDumpData,
-                                            ZXIC_UINT32 *entryNum)
+											 ZXIC_UINT32 queue_id,
+											 ZXIC_UINT32 sdt_no,
+											 ZXIC_UINT8 *pDumpData,
+											 ZXIC_UINT32 *entryNum)
 {
-    DPP_STATUS  rc = DPP_OK;
-
-    ZXIC_UINT8 *p_data = NULL;
-    ZXIC_UINT32 data_len = 0;
-    ZXIC_UINT32 entry_num = 0;
-    ZXIC_UINT32 bulk_id = 0;
-    DPP_SE_CFG *p_se_cfg = NULL;
-    FUNC_ID_INFO *p_func_info = NULL;
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    DPP_SDTTBL_HASH_T sdt_hash           = {0};
-    HASH_ENTRY_CFG  hash_entry_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_POINT(pDumpData);
-    ZXIC_COMM_CHECK_POINT(entryNum);
-
-    ZXIC_COMM_TRACE_INFO("dump hash sdt no: %d\n", sdt_no);
-
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
-
-     /* 取出se配置 */
-    rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_se_cfg_get");
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg);
-    p_func_info = DPP_GET_FUN_INFO(p_se_cfg, sdt_hash.hash_id);
-    DPP_SE_CHECK_FUN(p_func_info, sdt_hash.hash_id, FUN_HASH);
-    p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg);
-
-    ZXIC_COMM_MEMSET(&hash_entry_cfg, 0x0, sizeof(HASH_ENTRY_CFG));
-    hash_entry_cfg.key_by_size = sdt_hash.key_size;
-    hash_entry_cfg.key_type = sdt_hash.hash_table_width;
-    hash_entry_cfg.rst_by_size = 1 << (sdt_hash.rsp_mode + 2);
-    hash_entry_cfg.table_id = sdt_hash.hash_table_id;
-    bulk_id = ((hash_entry_cfg.table_id >> 2) & 0x7);
-    ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id, HASH_BULK_NUM - 1);
-
-    //申请data空间
-    p_data = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(DTB_DMUP_DATA_MAX);
-    ZXIC_COMM_CHECK_POINT(p_data);
-    ZXIC_COMM_MEMSET(p_data, 0, DTB_DMUP_DATA_MAX);
-
-    rc = dpp_dtb_sdt_hash_zcam_mono_space_dump(dev,
-                                                queue_id,
-                                                sdt_no, 
-                                                sdt_hash.hash_id,
-                                                bulk_id,
-                                                p_data,
-                                                &data_len);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_sdt_hash_zcam_mono_space_dump", p_data);
-
-    rc = dpp_dtb_dump_hash_parse(&hash_entry_cfg,
-                                ITEM_RAM,
-                                p_data,
-                                data_len,
-                                pDumpData,
-                                &entry_num);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_dump_hash_parse",p_data);
-
-    *entryNum = entry_num;
-
-    ZXIC_COMM_TRACE_INFO("hash table dump entry num %d end.\n\n", *entryNum);
-
-    ZXIC_COMM_FREE(p_data);
-
-    return rc;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT8 *p_data = NULL;
+	ZXIC_UINT32 data_len = 0;
+	ZXIC_UINT32 entry_num = 0;
+	ZXIC_UINT32 bulk_id = 0;
+	DPP_SE_CFG *p_se_cfg = NULL;
+	FUNC_ID_INFO *p_func_info = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	DPP_SDTTBL_HASH_T sdt_hash = { 0 };
+	HASH_ENTRY_CFG hash_entry_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(pDumpData);
+	ZXIC_COMM_CHECK_POINT(entryNum);
+
+	ZXIC_COMM_TRACE_INFO("dump hash sdt no: %d\n", sdt_no);
+
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
+
+	/* 取出se配置 */
+	rc = dpp_se_cfg_get(DEV_ID(dev), &p_se_cfg);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_se_cfg_get");
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_cfg);
+	p_func_info = DPP_GET_FUN_INFO(p_se_cfg, sdt_hash.hash_id);
+	DPP_SE_CHECK_FUN(p_func_info, sdt_hash.hash_id, FUN_HASH);
+	p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_hash_cfg);
+
+	ZXIC_COMM_MEMSET(&hash_entry_cfg, 0x0, sizeof(HASH_ENTRY_CFG));
+	hash_entry_cfg.key_by_size = sdt_hash.key_size;
+	hash_entry_cfg.key_type = sdt_hash.hash_table_width;
+	hash_entry_cfg.rst_by_size = 1 << (sdt_hash.rsp_mode + 2);
+	hash_entry_cfg.table_id = sdt_hash.hash_table_id;
+	bulk_id = ((hash_entry_cfg.table_id >> 2) & 0x7);
+	ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id, HASH_BULK_NUM - 1);
+
+	//申请data空间
+	p_data = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(DTB_DMUP_DATA_MAX);
+	ZXIC_COMM_CHECK_POINT(p_data);
+	ZXIC_COMM_MEMSET(p_data, 0, DTB_DMUP_DATA_MAX);
+
+	rc = dpp_dtb_sdt_hash_zcam_mono_space_dump(dev, queue_id, sdt_no,
+											   sdt_hash.hash_id, bulk_id,
+											   p_data, &data_len);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+			rc, "dpp_dtb_sdt_hash_zcam_mono_space_dump", p_data);
+
+	rc = dpp_dtb_dump_hash_parse(&hash_entry_cfg, ITEM_RAM, p_data, data_len,
+								 pDumpData, &entry_num);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_dump_hash_parse",
+											 p_data);
+
+	*entryNum = entry_num;
+
+	ZXIC_COMM_TRACE_INFO("hash table dump entry num %d end.\n\n", *entryNum);
+
+	ZXIC_COMM_FREE(p_data);
+
+	return rc;
 }
 
 /** dtb dump etcam直接表表项内容 级联eram支持64bit/128bit
-* @param   dev_id             设备号
-* @param   queue_id           队列号
-* @param   sdt_no             acl表sdt表号
-* @param   start_index        要dump的起始index，单位是sdt_no该表的mode
-* @param   p_dump_data_arr    本次dump出的数据，数据格式与下表格式相同
-* @param   entry_num          本次dump实际的条目数
-* @param   next_start_index   下次dump是开始的index  
-* @param   finish_flag        整个表dump完成标志，1表示完成，0表示未完成
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2022/08/30
-************************************************************/
- DPP_STATUS dpp_dtb_acl_table_dump(DPP_DEV_T *dev,
-                               ZXIC_UINT32 queue_id,
-                               ZXIC_UINT32 sdt_no,
-                               DPP_DTB_DUMP_INDEX_T start_index,
-                               DPP_DTB_ACL_ENTRY_INFO_T* p_dump_data_arr,
-                               ZXIC_UINT32 *entry_num,
-                               DPP_DTB_DUMP_INDEX_T *next_start_index,
-                               ZXIC_UINT32 *finish_flag)
+ * @param   dev_id             设备号
+ * @param   queue_id           队列号
+ * @param   sdt_no             acl表sdt表号
+ * @param   start_index        要dump的起始index，单位是sdt_no该表的mode
+ * @param   p_dump_data_arr    本次dump出的数据，数据格式与下表格式相同
+ * @param   entry_num          本次dump实际的条目数
+ * @param   next_start_index   下次dump是开始的index
+ * @param   finish_flag        整个表dump完成标志，1表示完成，0表示未完成
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2022/08/30
+ ************************************************************/
+DPP_STATUS dpp_dtb_acl_table_dump(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+								  ZXIC_UINT32 sdt_no,
+								  DPP_DTB_DUMP_INDEX_T start_index,
+								  DPP_DTB_ACL_ENTRY_INFO_T *p_dump_data_arr,
+								  ZXIC_UINT32 *entry_num,
+								  DPP_DTB_DUMP_INDEX_T *next_start_index,
+								  ZXIC_UINT32 *finish_flag)
 {
-    DPP_STATUS  rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 handle = 0;
-
-    ZXIC_UINT32 dump_element_id = 0;
-
-    ZXIC_UINT8 *temp_dump_out_data = NULL;
-    ZXIC_UINT8 *dump_info_buff = NULL;
-    ZXIC_UINT8 *p_data_start = NULL;
-    ZXIC_UINT8 *p_data_640bit = NULL;
-    ZXIC_UINT8 *p_mask_start = NULL;
-    ZXIC_UINT8 *p_mask_640bit = NULL;
-    ZXIC_UINT8 *p_rst_start = NULL;
-    ZXIC_UINT8 *p_rst_128bit = NULL;
-    ZXIC_UINT32 *eram_buff = NULL;
-
-
-    ZXIC_UINT32 addr_640bit = 0;
-    ZXIC_UINT32 rd_mask = 0;
-    ZXIC_UINT32 dump_eram_depth_128bit = 0;
-    ZXIC_UINT32 eram_row_index = 0;
-    ZXIC_UINT32 eram_col_index = 0;
-
-    ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = {0};
-    ZXIC_UINT8 xy_data[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    ZXIC_UINT8 xy_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    ZXIC_UINT8 dm_data[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    ZXIC_UINT8 dm_mask[DPP_ETCAM_WIDTH_MAX / 8] = {0};
-    DPP_ETCAM_ENTRY_T entry_xy = {0};
-    DPP_ETCAM_ENTRY_T entry_dm = {0};
-    DPP_DTB_ACL_ENTRY_INFO_T* p_dump_user_data = NULL;
-
-    ZXIC_UINT32 block_num = 0;
-    ZXIC_UINT32 etcam_key_mode = 0;
-    ZXIC_UINT32 etcam_table_id = 0;
-    ZXIC_UINT32 as_enable = 0;
-    ZXIC_UINT32 as_eram_baddr = 0;
-    ZXIC_UINT32 etcam_as_mode = 0;
-    ZXIC_UINT32 etcam_table_depth = 0;
-    ZXIC_UINT32 block_idx = 0;
-
-    ZXIC_UINT32 etcam_data_dst_phy_haddr = 0;
-    ZXIC_UINT32 etcam_data_dst_phy_laddr = 0;
-    ZXIC_UINT32 etcam_mask_dst_phy_haddr = 0;
-    ZXIC_UINT32 etcam_mask_dst_phy_laddr = 0;
-    ZXIC_UINT32 as_rst_dst_phy_haddr = 0;
-    ZXIC_UINT32 as_rst_dst_phy_laddr = 0;
-
-    ZXIC_UINT32 dtb_desc_addr_offset = 0;
-    ZXIC_UINT32 dump_data_len = 0;
-    ZXIC_UINT32 dtb_desc_len = 0;
-
-    ZXIC_UINT32 etcam_data_len_offset = 0;
-    ZXIC_UINT32 etcam_mask_len_offset = 0;
-
-    DPP_ACL_CFG_EX_T *p_acl_cfg = NULL;
-    DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL;
-
-    DPP_SDTTBL_ETCAM_T sdt_etcam_info = {0};  /*SDT内容*/
-    ETCAM_DUMP_INFO_T etcam_dump_info = {0};
-    DPP_DTB_ENTRY_T   dtb_dump_entry = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    dtb_dump_entry.cmd = cmd_buff;
-    entry_xy.p_data = xy_data;
-    entry_xy.p_mask = xy_mask;
-    entry_dm.p_data = dm_data;
-    entry_dm.p_mask = dm_mask;
-
-    //从sdt_no中获取SDT配置
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get");
-    etcam_key_mode = sdt_etcam_info.etcam_key_mode;
-    etcam_as_mode = sdt_etcam_info.as_rsp_mode;
-    etcam_table_id = sdt_etcam_info.etcam_table_id;
-    as_enable = sdt_etcam_info.as_en;
-    as_eram_baddr = sdt_etcam_info.as_eram_baddr;
-    etcam_table_depth = sdt_etcam_info.etcam_table_depth;
-
-    dpp_acl_cfg_get(&p_acl_cfg);//获取ACL表资源配置
-    ZXIC_COMM_CHECK_POINT(p_acl_cfg);
-
-    p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id;//得到该acl表的资源配置
-
-    if (!p_tbl_cfg->is_used)
-    {
-        ZXIC_COMM_TRACE_ERROR("table[ %d ] is not init!\n", etcam_table_id);
-        ZXIC_COMM_ASSERT(0);
-        return DPP_ACL_RC_TBL_NOT_INIT;
-    }
-
-    block_num = p_tbl_cfg->block_num;
-
-    rc = dpp_dtb_dump_addr_set(dev, queue_id, sdt_no, &dump_element_id);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_addr_set");
-
-    ZXIC_COMM_TRACE_INFO("etcam_key_mode: 0x%x\n", etcam_key_mode);
-    ZXIC_COMM_TRACE_INFO("etcam_table_id: 0x%x\n", etcam_table_id);
-    ZXIC_COMM_TRACE_INFO("as_enable: 0x%x\n", as_enable);
-    ZXIC_COMM_TRACE_INFO("as_eram_baddr: 0x%x\n", as_eram_baddr);
-    ZXIC_COMM_TRACE_INFO("etcam_as_mode: 0x%x\n", etcam_as_mode);
-    ZXIC_COMM_TRACE_INFO("block_num: 0x%x\n", block_num);
-    ZXIC_COMM_TRACE_INFO("dump_element_id: 0x%x\n", dump_element_id);
-
-    dump_info_buff = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8));
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dump_info_buff);
-    ZXIC_COMM_MEMSET(dump_info_buff, 0, DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8));
-
-    //etcam  data dump描述符，以block为单位，深度是512 起始地址是0  rd_mode = 0xff
-    for(i = 0; i < block_num; i++)
-    {
-        block_idx = p_tbl_cfg->block_array[i];
-
-        ZXIC_COMM_TRACE_INFO("block_idx: %d\n", block_idx);
-
-        etcam_dump_info.block_sel = block_idx;
-        etcam_dump_info.addr = 0;
-        etcam_dump_info.tb_width = 3;
-        etcam_dump_info.rd_mode = 0xFF;
-        etcam_dump_info.tb_depth = DPP_ETCAM_RAM_DEPTH;
-        etcam_dump_info.data_or_mask = DPP_ETCAM_DTYPE_DATA;
-
-        rc = dpp_dtb_tab_up_item_offset_addr_get(dev,
-                                             queue_id,
-                                             dump_element_id,
-                                             dump_data_len,
-                                             &etcam_data_dst_phy_haddr,
-                                             &etcam_data_dst_phy_laddr);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff);
-        rc = dpp_dtb_etcam_dump_entry(dev,
-                                    &etcam_dump_info,
-                                    etcam_data_dst_phy_haddr,
-                                    etcam_data_dst_phy_laddr,
-                                    &dtb_dump_entry);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_etcam_dump_entry", dump_info_buff);
-        rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", dump_info_buff);
-        ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
-
-        dtb_desc_len += 1;
-        dtb_desc_addr_offset += DTB_LEN_POS_SETP;
-        dump_data_len += DPP_ETCAM_RAM_DEPTH * 640 / 8;
-    }
-
-    etcam_data_len_offset = dump_data_len;
-    // etcam mask dump描述符，以block为单位，深度是512 起始地址是0  rd_mode = 0xff
-    for(i = 0; i < block_num; i++)
-    {
-        block_idx = p_tbl_cfg->block_array[i];
-
-        ZXIC_COMM_TRACE_INFO("mask: block_idx: %d\n", block_idx);
-
-        etcam_dump_info.block_sel = block_idx;
-        etcam_dump_info.addr = 0;
-        etcam_dump_info.tb_width = 3;
-        etcam_dump_info.rd_mode = 0xFF;
-        etcam_dump_info.tb_depth = DPP_ETCAM_RAM_DEPTH;
-        etcam_dump_info.data_or_mask = DPP_ETCAM_DTYPE_MASK;
-
-        rc = dpp_dtb_tab_up_item_offset_addr_get(dev,
-                                                queue_id,
-                                                dump_element_id,
-                                                dump_data_len,
-                                                &etcam_mask_dst_phy_haddr,
-                                                &etcam_mask_dst_phy_laddr);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff);
-        rc = dpp_dtb_etcam_dump_entry(dev,
-                                    &etcam_dump_info,
-                                    etcam_mask_dst_phy_haddr,
-                                    etcam_mask_dst_phy_laddr,
-                                    &dtb_dump_entry);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_etcam_dump_entry", dump_info_buff);
-        rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", dump_info_buff);
-        ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
-
-        dtb_desc_len += 1;
-        dtb_desc_addr_offset += DTB_LEN_POS_SETP;
-        dump_data_len += DPP_ETCAM_RAM_DEPTH * 640 / 8;
-    }
-    etcam_mask_len_offset = dump_data_len;
-
-    //补充级联描述符
-    if(as_enable)
-    {
-        rc = dtb_eram_index_cal(dev, etcam_as_mode, etcam_table_depth, &dump_eram_depth_128bit, &eram_col_index);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dtb_eram_index_cal", dump_info_buff);
-
-        rc = dpp_dtb_tab_up_item_offset_addr_get(dev,
-                                                 queue_id,
-                                                 dump_element_id,
-                                                 dump_data_len,
-                                                 &as_rst_dst_phy_haddr,
-                                                 &as_rst_dst_phy_laddr);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff);
-
-        rc = dpp_dtb_smmu0_dump_entry(dev, 
-                                as_eram_baddr, 
-                                dump_eram_depth_128bit,
-                                as_rst_dst_phy_haddr,
-                                as_rst_dst_phy_laddr,
-                                &dtb_dump_entry);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_smmu0_dump_entry", dump_info_buff);
-        rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write", dump_info_buff);
-        ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
-        dtb_desc_len += 1;
-        dtb_desc_addr_offset += DTB_LEN_POS_SETP;
-        dump_data_len += dump_eram_depth_128bit * 128 / 8;
-    }
-
-    ZXIC_COMM_TRACE_INFO("dtb_desc_len: 0x%x\n", dtb_desc_len);
-    ZXIC_COMM_TRACE_INFO("dtb_desc_addr_offset: 0x%x\n", dtb_desc_addr_offset);
-    ZXIC_COMM_TRACE_INFO("dump_data_len: 0x%x\n", dump_data_len);
-
-    //申请data空间
-    temp_dump_out_data = (ZXIC_UINT8 *) ZXIC_COMM_MALLOC(dump_data_len * sizeof(ZXIC_UINT8));
-    ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(temp_dump_out_data, dump_info_buff);
-    ZXIC_COMM_MEMSET(temp_dump_out_data, 0, dump_data_len * sizeof(ZXIC_UINT8));
-
-    /*下发dump描述符*/
-    rc = dpp_dtb_write_dump_desc_info(dev,
-                                      queue_id,
-                                      dump_element_id,
-                                      (ZXIC_UINT32 *)dump_info_buff,
-                                      dump_data_len / 4,
-                                      dtb_desc_len * 4,
-                                      (ZXIC_UINT32 *)temp_dump_out_data);
-    ZXIC_COMM_FREE(dump_info_buff);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc,"dpp_dtb_write_dump_desc_info", temp_dump_out_data);
-
-    //解析数据
-    p_data_start = temp_dump_out_data;
-    p_mask_start = temp_dump_out_data + etcam_data_len_offset;
-    if(as_enable)
-    {
-        p_rst_start = temp_dump_out_data + etcam_mask_len_offset;
-    }
-
-    for (handle = 0; handle < etcam_table_depth; handle++)
-    {
-        p_dump_user_data = p_dump_data_arr + handle;
-
-        if ((p_dump_user_data == NULL) || (p_dump_user_data->key_data == NULL) || (p_dump_user_data->key_mask == NULL))
-        {
-            ZXIC_COMM_TRACE_ERROR("etcam handle 0x%x data user buff is NULL!\n", handle);
-            ZXIC_COMM_FREE(temp_dump_out_data);
-            return DPP_ERR;
-        }
-
-        if(as_enable)
-        {
-            if(p_dump_user_data->p_as_rslt == NULL)
-            {
-                ZXIC_COMM_TRACE_ERROR("etcam handle 0x%x as data buff is NULL!\n", handle);
-                ZXIC_COMM_FREE(temp_dump_out_data);
-                return DPP_ERR;
-            }
-        }
-
-        p_dump_user_data->handle = handle;
-
-        addr_640bit = handle / (1U << etcam_key_mode);
-        rd_mask = (((1U << (8U >> etcam_key_mode)) - 1) << ((8U >> etcam_key_mode) * (handle % (1U << etcam_key_mode)))) & 0xFF;
-
-        p_data_640bit = p_data_start + addr_640bit * 640 / 8;
-        p_mask_640bit = p_mask_start + addr_640bit * 640 / 8;
-
-        dpp_dtb_etcam_ind_data_get(dev, p_data_640bit, rd_mask, entry_xy.p_data);
-        dpp_dtb_etcam_ind_data_get(dev, p_mask_640bit, rd_mask, entry_xy.p_mask);
-
-        rc = dpp_etcam_xy_to_dm(&entry_dm, &entry_xy, DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode));
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_etcam_xy_to_dm", temp_dump_out_data);
-
-        ZXIC_COMM_MEMCPY(p_dump_user_data->key_data, entry_dm.p_data, DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode));
-        ZXIC_COMM_MEMCPY(p_dump_user_data->key_mask, entry_dm.p_mask, DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode));
-
-        if(as_enable)
-        {
-            rc = dtb_eram_index_cal(dev, etcam_as_mode, handle, &eram_row_index, &eram_col_index);
-            ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dtb_eram_index_cal", temp_dump_out_data);
-            p_rst_128bit = p_rst_start + eram_row_index * DTB_LEN_POS_SETP;
-
-            eram_buff = (ZXIC_UINT32*)p_rst_128bit;
-            
-            if(etcam_as_mode == ERAM128_TBL_128b)
-            {   
-                ZXIC_COMM_MEMCPY(p_dump_user_data->p_as_rslt, eram_buff, (128 / 8));
-            }
-            else if(etcam_as_mode == ERAM128_TBL_64b)
-            {   
-                ZXIC_COMM_MEMCPY(p_dump_user_data->p_as_rslt, eram_buff + ((1 - eram_col_index) << 1), (64 / 8));
-            }
-        }
-
-    }
-   
-    *entry_num = etcam_table_depth;
-    *finish_flag = 1;
-    ZXIC_COMM_TRACE_INFO(" etcam table dump entry num %d, finish flag %d\n\n", *entry_num, *finish_flag);
-
-    ZXIC_COMM_FREE(temp_dump_out_data);
-
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 handle = 0;
+
+	ZXIC_UINT32 dump_element_id = 0;
+
+	ZXIC_UINT8 *temp_dump_out_data = NULL;
+	ZXIC_UINT8 *dump_info_buff = NULL;
+	ZXIC_UINT8 *p_data_start = NULL;
+	ZXIC_UINT8 *p_data_640bit = NULL;
+	ZXIC_UINT8 *p_mask_start = NULL;
+	ZXIC_UINT8 *p_mask_640bit = NULL;
+	ZXIC_UINT8 *p_rst_start = NULL;
+	ZXIC_UINT8 *p_rst_128bit = NULL;
+	ZXIC_UINT32 *eram_buff = NULL;
+
+	ZXIC_UINT32 addr_640bit = 0;
+	ZXIC_UINT32 rd_mask = 0;
+	ZXIC_UINT32 dump_eram_depth_128bit = 0;
+	ZXIC_UINT32 eram_row_index = 0;
+	ZXIC_UINT32 eram_col_index = 0;
+
+	ZXIC_UINT8 cmd_buff[DTB_TABLE_CMD_SIZE_BIT / 8] = { 0 };
+	ZXIC_UINT8 xy_data[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	ZXIC_UINT8 xy_mask[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	ZXIC_UINT8 dm_data[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	ZXIC_UINT8 dm_mask[DPP_ETCAM_WIDTH_MAX / 8] = { 0 };
+	DPP_ETCAM_ENTRY_T entry_xy = { 0 };
+	DPP_ETCAM_ENTRY_T entry_dm = { 0 };
+	DPP_DTB_ACL_ENTRY_INFO_T *p_dump_user_data = NULL;
+
+	ZXIC_UINT32 block_num = 0;
+	ZXIC_UINT32 etcam_key_mode = 0;
+	ZXIC_UINT32 etcam_table_id = 0;
+	ZXIC_UINT32 as_enable = 0;
+	ZXIC_UINT32 as_eram_baddr = 0;
+	ZXIC_UINT32 etcam_as_mode = 0;
+	ZXIC_UINT32 etcam_table_depth = 0;
+	ZXIC_UINT32 block_idx = 0;
+
+	ZXIC_UINT32 etcam_data_dst_phy_haddr = 0;
+	ZXIC_UINT32 etcam_data_dst_phy_laddr = 0;
+	ZXIC_UINT32 etcam_mask_dst_phy_haddr = 0;
+	ZXIC_UINT32 etcam_mask_dst_phy_laddr = 0;
+	ZXIC_UINT32 as_rst_dst_phy_haddr = 0;
+	ZXIC_UINT32 as_rst_dst_phy_laddr = 0;
+
+	ZXIC_UINT32 dtb_desc_addr_offset = 0;
+	ZXIC_UINT32 dump_data_len = 0;
+	ZXIC_UINT32 dtb_desc_len = 0;
+
+	ZXIC_UINT32 etcam_data_len_offset = 0;
+	ZXIC_UINT32 etcam_mask_len_offset = 0;
+
+	DPP_ACL_CFG_EX_T *p_acl_cfg = NULL;
+	DPP_ACL_TBL_CFG_T *p_tbl_cfg = NULL;
+
+	DPP_SDTTBL_ETCAM_T sdt_etcam_info = { 0 }; /*SDT内容*/
+	ETCAM_DUMP_INFO_T etcam_dump_info = { 0 };
+	DPP_DTB_ENTRY_T dtb_dump_entry = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	dtb_dump_entry.cmd = cmd_buff;
+	entry_xy.p_data = xy_data;
+	entry_xy.p_mask = xy_mask;
+	entry_dm.p_data = dm_data;
+	entry_dm.p_mask = dm_mask;
+
+	//从sdt_no中获取SDT配置
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_etcam_info);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_soft_sdt_tbl_get");
+	etcam_key_mode = sdt_etcam_info.etcam_key_mode;
+	etcam_as_mode = sdt_etcam_info.as_rsp_mode;
+	etcam_table_id = sdt_etcam_info.etcam_table_id;
+	as_enable = sdt_etcam_info.as_en;
+	as_eram_baddr = sdt_etcam_info.as_eram_baddr;
+	etcam_table_depth = sdt_etcam_info.etcam_table_depth;
+
+	dpp_acl_cfg_get(&p_acl_cfg); //获取ACL表资源配置
+	ZXIC_COMM_CHECK_POINT(p_acl_cfg);
+
+	p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; //得到该acl表的资源配置
+
+	if (!p_tbl_cfg->is_used) {
+		ZXIC_COMM_TRACE_ERROR("table[ %d ] is not init!\n", etcam_table_id);
+		ZXIC_COMM_ASSERT(0);
+		return DPP_ACL_RC_TBL_NOT_INIT;
+	}
+
+	block_num = p_tbl_cfg->block_num;
+
+	rc = dpp_dtb_dump_addr_set(dev, queue_id, sdt_no, &dump_element_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_addr_set");
+
+	ZXIC_COMM_TRACE_INFO("etcam_key_mode: 0x%x\n", etcam_key_mode);
+	ZXIC_COMM_TRACE_INFO("etcam_table_id: 0x%x\n", etcam_table_id);
+	ZXIC_COMM_TRACE_INFO("as_enable: 0x%x\n", as_enable);
+	ZXIC_COMM_TRACE_INFO("as_eram_baddr: 0x%x\n", as_eram_baddr);
+	ZXIC_COMM_TRACE_INFO("etcam_as_mode: 0x%x\n", etcam_as_mode);
+	ZXIC_COMM_TRACE_INFO("block_num: 0x%x\n", block_num);
+	ZXIC_COMM_TRACE_INFO("dump_element_id: 0x%x\n", dump_element_id);
+
+	dump_info_buff = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(
+			DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8));
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dump_info_buff);
+	ZXIC_COMM_MEMSET(dump_info_buff, 0,
+					 DPP_DTB_TABLE_DUMP_INFO_BUFF_SIZE * sizeof(ZXIC_UINT8));
+
+	// etcam  data dump描述符，以block为单位，深度是512 起始地址是0  rd_mode = 0xff
+	for (i = 0; i < block_num; i++) {
+		block_idx = p_tbl_cfg->block_array[i];
+
+		ZXIC_COMM_TRACE_INFO("block_idx: %d\n", block_idx);
+
+		etcam_dump_info.block_sel = block_idx;
+		etcam_dump_info.addr = 0;
+		etcam_dump_info.tb_width = 3;
+		etcam_dump_info.rd_mode = 0xFF;
+		etcam_dump_info.tb_depth = DPP_ETCAM_RAM_DEPTH;
+		etcam_dump_info.data_or_mask = DPP_ETCAM_DTYPE_DATA;
+
+		rc = dpp_dtb_tab_up_item_offset_addr_get(dev, queue_id, dump_element_id,
+												 dump_data_len,
+												 &etcam_data_dst_phy_haddr,
+												 &etcam_data_dst_phy_laddr);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+				rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff);
+		rc = dpp_dtb_etcam_dump_entry(dev, &etcam_dump_info,
+									  etcam_data_dst_phy_haddr,
+									  etcam_data_dst_phy_laddr,
+									  &dtb_dump_entry);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_etcam_dump_entry",
+												 dump_info_buff);
+		rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset,
+								&dtb_dump_entry);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",
+												 dump_info_buff);
+		ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
+
+		dtb_desc_len += 1;
+		dtb_desc_addr_offset += DTB_LEN_POS_SETP;
+		dump_data_len += DPP_ETCAM_RAM_DEPTH * 640 / 8;
+	}
+
+	etcam_data_len_offset = dump_data_len;
+	// etcam mask dump描述符，以block为单位，深度是512 起始地址是0  rd_mode = 0xff
+	for (i = 0; i < block_num; i++) {
+		block_idx = p_tbl_cfg->block_array[i];
+
+		ZXIC_COMM_TRACE_INFO("mask: block_idx: %d\n", block_idx);
+
+		etcam_dump_info.block_sel = block_idx;
+		etcam_dump_info.addr = 0;
+		etcam_dump_info.tb_width = 3;
+		etcam_dump_info.rd_mode = 0xFF;
+		etcam_dump_info.tb_depth = DPP_ETCAM_RAM_DEPTH;
+		etcam_dump_info.data_or_mask = DPP_ETCAM_DTYPE_MASK;
+
+		rc = dpp_dtb_tab_up_item_offset_addr_get(dev, queue_id, dump_element_id,
+												 dump_data_len,
+												 &etcam_mask_dst_phy_haddr,
+												 &etcam_mask_dst_phy_laddr);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+				rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff);
+		rc = dpp_dtb_etcam_dump_entry(dev, &etcam_dump_info,
+									  etcam_mask_dst_phy_haddr,
+									  etcam_mask_dst_phy_laddr,
+									  &dtb_dump_entry);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_etcam_dump_entry",
+												 dump_info_buff);
+		rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset,
+								&dtb_dump_entry);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",
+												 dump_info_buff);
+		ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
+
+		dtb_desc_len += 1;
+		dtb_desc_addr_offset += DTB_LEN_POS_SETP;
+		dump_data_len += DPP_ETCAM_RAM_DEPTH * 640 / 8;
+	}
+	etcam_mask_len_offset = dump_data_len;
+
+	//补充级联描述符
+	if (as_enable) {
+		rc = dtb_eram_index_cal(dev, etcam_as_mode, etcam_table_depth,
+								&dump_eram_depth_128bit, &eram_col_index);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dtb_eram_index_cal",
+												 dump_info_buff);
+
+		rc = dpp_dtb_tab_up_item_offset_addr_get(dev, queue_id, dump_element_id,
+												 dump_data_len,
+												 &as_rst_dst_phy_haddr,
+												 &as_rst_dst_phy_laddr);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+				rc, "dpp_dtb_tab_up_item_offset_addr_get", dump_info_buff);
+
+		rc = dpp_dtb_smmu0_dump_entry(dev, as_eram_baddr,
+									  dump_eram_depth_128bit,
+									  as_rst_dst_phy_haddr,
+									  as_rst_dst_phy_laddr, &dtb_dump_entry);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_smmu0_dump_entry",
+												 dump_info_buff);
+		rc = dpp_dtb_data_write(dump_info_buff, dtb_desc_addr_offset,
+								&dtb_dump_entry);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_data_write",
+												 dump_info_buff);
+		ZXIC_COMM_MEMSET(cmd_buff, 0, DTB_TABLE_CMD_SIZE_BIT / 8);
+		dtb_desc_len += 1;
+		dtb_desc_addr_offset += DTB_LEN_POS_SETP;
+		dump_data_len += dump_eram_depth_128bit * 128 / 8;
+	}
+
+	ZXIC_COMM_TRACE_INFO("dtb_desc_len: 0x%x\n", dtb_desc_len);
+	ZXIC_COMM_TRACE_INFO("dtb_desc_addr_offset: 0x%x\n", dtb_desc_addr_offset);
+	ZXIC_COMM_TRACE_INFO("dump_data_len: 0x%x\n", dump_data_len);
+
+	//申请data空间
+	temp_dump_out_data =
+			(ZXIC_UINT8 *)ZXIC_COMM_MALLOC(dump_data_len * sizeof(ZXIC_UINT8));
+	ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(temp_dump_out_data,
+												dump_info_buff);
+	ZXIC_COMM_MEMSET(temp_dump_out_data, 0, dump_data_len * sizeof(ZXIC_UINT8));
+
+	/*下发dump描述符*/
+	rc = dpp_dtb_write_dump_desc_info(dev, queue_id, dump_element_id,
+									  (ZXIC_UINT32 *)dump_info_buff,
+									  dump_data_len / 4, dtb_desc_len * 4,
+									  (ZXIC_UINT32 *)temp_dump_out_data);
+	ZXIC_COMM_FREE(dump_info_buff);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_dtb_write_dump_desc_info",
+											 temp_dump_out_data);
+
+	//解析数据
+	p_data_start = temp_dump_out_data;
+	p_mask_start = temp_dump_out_data + etcam_data_len_offset;
+	if (as_enable) {
+		p_rst_start = temp_dump_out_data + etcam_mask_len_offset;
+	}
+
+	for (handle = 0; handle < etcam_table_depth; handle++) {
+		p_dump_user_data = p_dump_data_arr + handle;
+
+		if ((p_dump_user_data == NULL) ||
+			(p_dump_user_data->key_data == NULL) ||
+			(p_dump_user_data->key_mask == NULL)) {
+			ZXIC_COMM_TRACE_ERROR("etcam handle 0x%x data user buff is NULL!\n",
+								  handle);
+			ZXIC_COMM_FREE(temp_dump_out_data);
+			return DPP_ERR;
+		}
+
+		if (as_enable) {
+			if (p_dump_user_data->p_as_rslt == NULL) {
+				ZXIC_COMM_TRACE_ERROR(
+						"etcam handle 0x%x as data buff is NULL!\n", handle);
+				ZXIC_COMM_FREE(temp_dump_out_data);
+				return DPP_ERR;
+			}
+		}
+
+		p_dump_user_data->handle = handle;
+
+		addr_640bit = handle / (1U << etcam_key_mode);
+		rd_mask = (((1U << (8U >> etcam_key_mode)) - 1)
+				   << ((8U >> etcam_key_mode) *
+					   (handle % (1U << etcam_key_mode)))) &
+				  0xFF;
+
+		p_data_640bit = p_data_start + addr_640bit * 640 / 8;
+		p_mask_640bit = p_mask_start + addr_640bit * 640 / 8;
+
+		dpp_dtb_etcam_ind_data_get(dev, p_data_640bit, rd_mask,
+								   entry_xy.p_data);
+		dpp_dtb_etcam_ind_data_get(dev, p_mask_640bit, rd_mask,
+								   entry_xy.p_mask);
+
+		rc = dpp_etcam_xy_to_dm(&entry_dm, &entry_xy,
+								DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode));
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_etcam_xy_to_dm",
+												 temp_dump_out_data);
+
+		ZXIC_COMM_MEMCPY(p_dump_user_data->key_data, entry_dm.p_data,
+						 DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode));
+		ZXIC_COMM_MEMCPY(p_dump_user_data->key_mask, entry_dm.p_mask,
+						 DPP_ETCAM_ENTRY_SIZE_GET(etcam_key_mode));
+
+		if (as_enable) {
+			rc = dtb_eram_index_cal(dev, etcam_as_mode, handle, &eram_row_index,
+									&eram_col_index);
+			ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dtb_eram_index_cal",
+													 temp_dump_out_data);
+			p_rst_128bit = p_rst_start + eram_row_index * DTB_LEN_POS_SETP;
+
+			eram_buff = (ZXIC_UINT32 *)p_rst_128bit;
+
+			if (etcam_as_mode == ERAM128_TBL_128b) {
+				ZXIC_COMM_MEMCPY(p_dump_user_data->p_as_rslt, eram_buff,
+								 (128 / 8));
+			} else if (etcam_as_mode == ERAM128_TBL_64b) {
+				ZXIC_COMM_MEMCPY(p_dump_user_data->p_as_rslt,
+								 eram_buff + ((1 - eram_col_index) << 1),
+								 (64 / 8));
+			}
+		}
+	}
+
+	*entry_num = etcam_table_depth;
+	*finish_flag = 1;
+	ZXIC_COMM_TRACE_INFO(" etcam table dump entry num %d, finish flag %d\n\n",
+						 *entry_num, *finish_flag);
+
+	ZXIC_COMM_FREE(temp_dump_out_data);
+
+	return DPP_OK;
 }
 
 #endif
@@ -7382,84 +7061,77 @@ DPP_STATUS dpp_dtb_hash_table_only_zcam_dump(DPP_DEV_T *dev,
 /*打印buff中数据，size 单位 字节*/
 ZXIC_VOID dpp_data_buff_print(ZXIC_UINT8 *buff, ZXIC_UINT32 size)
 {
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 j = 0;
+	ZXIC_UINT8 *temp_buff = NULL;
 
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT8 *temp_buff = NULL;
+	ZXIC_COMM_PRINT("buff data is:\n");
 
-    ZXIC_COMM_PRINT("buff data is:\n");
+	for (i = 0; i < size / 4 / 4; i++) {
+		temp_buff = buff + 16 * i;
+		for (j = 0; j < 4; j++) {
+			ZXIC_COMM_PRINT("0x%08x  ", *((ZXIC_UINT32 *)(temp_buff + 4 * j)));
+		}
+		ZXIC_COMM_PRINT("\n");
+	}
 
-    for (i = 0; i < size / 4 / 4; i++)
-    {
-        temp_buff = buff + 16 * i;
-        for(j = 0; j < 4; j++)
-        {
-            ZXIC_COMM_PRINT("0x%08x  ", *((ZXIC_UINT32*)(temp_buff + 4 * j)));
-        } 
-        ZXIC_COMM_PRINT("\n");
-    }
-
-    ZXIC_COMM_PRINT("\n");
+	ZXIC_COMM_PRINT("\n");
 }
 
-ZXIC_VOID dpp_acl_data_print(ZXIC_UINT8 *p_data, ZXIC_UINT8 *p_mask, ZXIC_UINT32 etcam_mode)
-{ 
-        int i = 0;
-        int data_len = 0;
+ZXIC_VOID dpp_acl_data_print(ZXIC_UINT8 *p_data, ZXIC_UINT8 *p_mask,
+							 ZXIC_UINT32 etcam_mode)
+{
+	int i = 0;
+	int data_len = 0;
 
-        data_len = DPP_ETCAM_ENTRY_SIZE_GET(etcam_mode);
+	data_len = DPP_ETCAM_ENTRY_SIZE_GET(etcam_mode);
 
-        if(data_len > 80)
-        {
-            return;
-        }
+	if (data_len > 80) {
+		return;
+	}
 
-        ZXIC_COMM_PRINT("%s:", "data");
+	ZXIC_COMM_PRINT("%s:", "data");
 
-        for (i = 0; i < data_len; i++)
-        {
-            if ((i % 10) == 0)
-            {
-                ZXIC_COMM_PRINT("\n");
-            }
+	for (i = 0; i < data_len; i++) {
+		if ((i % 10) == 0) {
+			ZXIC_COMM_PRINT("\n");
+		}
 
-            ZXIC_COMM_PRINT("%02x", p_data[i]);
-        }
+		ZXIC_COMM_PRINT("%02x", p_data[i]);
+	}
 
-        ZXIC_COMM_PRINT("\n");
+	ZXIC_COMM_PRINT("\n");
 
-        ZXIC_COMM_PRINT("%s:", "mask");
+	ZXIC_COMM_PRINT("%s:", "mask");
 
-        for (i = 0; i < data_len; i++)
-        {
-            if ((i % 10) == 0)
-            {
-                ZXIC_COMM_PRINT("\n");
-            }
+	for (i = 0; i < data_len; i++) {
+		if ((i % 10) == 0) {
+			ZXIC_COMM_PRINT("\n");
+		}
 
-            ZXIC_COMM_PRINT("%02x", p_mask[i]);
-        }
-        ZXIC_COMM_PRINT("\n");
+		ZXIC_COMM_PRINT("%02x", p_mask[i]);
+	}
+	ZXIC_COMM_PRINT("\n");
 }
 
 ZXIC_VOID dpp_dtb_data_print(ZXIC_UINT8 *p_data, ZXIC_UINT32 len)
 {
-    int i = 0;
-    int cycle = len / 4;
-    int remain = len % 4;
-
-    ZXIC_COMM_PRINT("%s:", "data:\n");
-
-    for(i = 0; i < cycle; i++)
-    {
-        ZXIC_COMM_PRINT("0x%02x %02x %02x %02x \n", p_data[4 * i],  p_data[4 * i + 1],  p_data[4 * i + 2],  p_data[4 * i + 3]);
-    }
-
-    for(i = 0; i < remain; i++)
-    {
-        ZXIC_COMM_PRINT("0x%02x", p_data[cycle * 4 + i]);
-    }
-    ZXIC_COMM_PRINT("\n");
+	int i = 0;
+	int cycle = len / 4;
+	int remain = len % 4;
+
+	ZXIC_COMM_PRINT("%s:", "data:\n");
+
+	for (i = 0; i < cycle; i++) {
+		ZXIC_COMM_PRINT("0x%02x %02x %02x %02x \n", p_data[4 * i],
+						p_data[4 * i + 1], p_data[4 * i + 2],
+						p_data[4 * i + 3]);
+	}
+
+	for (i = 0; i < remain; i++) {
+		ZXIC_COMM_PRINT("0x%02x", p_data[cycle * 4 + i]);
+	}
+	ZXIC_COMM_PRINT("\n");
 }
 
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_dtb_table_api.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_dtb_table_api.c
index fcffc01e6133e10f492a6e575592f808d6340610..7b5beca00c44065c1e18bd5262b4d7e9ff583298 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_dtb_table_api.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_dtb_table_api.c
@@ -11,633 +11,666 @@
 #include "dpp_kernel_init.h"
 
 #define EP_NUM (5)
-static ZXIC_UINT32 msix_interrupt_mode = 1;//1为dbi中断，0为match中断
-static ZXIC_RB_CFG g_dtb_queue_dump_addr_rb[DPP_DEV_SLOT_MAX][DPP_DEV_CHANNEL_MAX][DPP_DTB_QUEUE_NUM_MAX] = {{{{0}}}};
-static ZXIC_UINT32 hardware_ep_id[EP_NUM] = {5, 6, 7, 8, 9};
-
-typedef struct dpp_dtb_dump_addr_info_t
-{
-    ZXIC_UINT32 sdt_no;
-    ZXIC_UINT64 phyAddr;
-    ZXIC_UINT64 virAddr; 
-    ZXIC_UINT32 size;
-}DPP_DTB_DUMP_ADDR_INFO_T;
+static ZXIC_UINT32 msix_interrupt_mode = 1; // 1为dbi中断，0为match中断
+static ZXIC_RB_CFG
+		g_dtb_queue_dump_addr_rb[DPP_DEV_SLOT_MAX][DPP_DEV_CHANNEL_MAX]
+								[DPP_DTB_QUEUE_NUM_MAX] = { { { { 0 } } } };
+static ZXIC_UINT32 hardware_ep_id[EP_NUM] = { 5, 6, 7, 8, 9 };
+
+typedef struct dpp_dtb_dump_addr_info_t {
+	ZXIC_UINT32 sdt_no;
+	ZXIC_UINT64 phyAddr;
+	ZXIC_UINT64 virAddr;
+	ZXIC_UINT32 size;
+} DPP_DTB_DUMP_ADDR_INFO_T;
 
 ZXIC_UINT32 dpp_dtb_ep_id_get(ZXIC_UINT32 soft_ep_id)
 {
-    return hardware_ep_id[soft_ep_id];
+	return hardware_ep_id[soft_ep_id];
 }
 
-ZXIC_RB_CFG* dpp_dtb_dump_addr_rb_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id)
+ZXIC_RB_CFG *dpp_dtb_dump_addr_rb_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id)
 {
-    ZXIC_COMM_CHECK_POINT_RETURN_NULL(dev);
-    ZXIC_COMM_CHECK_INDEX_RETURN_NULL(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_RETURN_NULL(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    return &g_dtb_queue_dump_addr_rb[DEV_PCIE_SLOT(dev)][DEV_ID(dev)][queue_id];
+	ZXIC_COMM_CHECK_POINT_RETURN_NULL(dev);
+	ZXIC_COMM_CHECK_INDEX_RETURN_NULL(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_RETURN_NULL(DEV_ID(dev), queue_id, 0,
+										  DPP_DTB_QUEUE_NUM_MAX - 1);
+	return &g_dtb_queue_dump_addr_rb[DEV_PCIE_SLOT(dev)][DEV_ID(dev)][queue_id];
 }
 
 ZXIC_UINT32 dpp_dtb_dump_addr_rb_init(DPP_DEV_T *dev, ZXIC_UINT32 queue_id)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-    ZXIC_RB_CFG *p_dtb_dump_addr_rb = NULL;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_RB_CFG *p_dtb_dump_addr_rb = NULL;
 
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0,
+										DPP_DTB_QUEUE_NUM_MAX - 1);
 
-    p_dtb_dump_addr_rb = dpp_dtb_dump_addr_rb_get(dev, queue_id);
+	p_dtb_dump_addr_rb = dpp_dtb_dump_addr_rb_get(dev, queue_id);
 
-    rc = zxic_comm_rb_init(p_dtb_dump_addr_rb, 0, ZXIC_SIZEOF(DPP_DTB_DUMP_ADDR_INFO_T), dpp_apt_table_key_cmp);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_rb_init");
+	rc = zxic_comm_rb_init(p_dtb_dump_addr_rb, 0,
+						   ZXIC_SIZEOF(DPP_DTB_DUMP_ADDR_INFO_T),
+						   dpp_apt_table_key_cmp);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_rb_init");
 
-    return rc;
+	return rc;
 }
 
 ZXIC_UINT32 dpp_dtb_dump_addr_rb_destroy(DPP_DEV_T *dev, ZXIC_UINT32 queue_id)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-
-    D_NODE *p_node = NULL;
-    ZXIC_RB_TN *p_rb_tn = NULL;
-    DPP_DTB_DUMP_ADDR_INFO_T *p_rbkey = NULL;
-    D_HEAD *p_head_dtb_rb = NULL;
-    ZXIC_RB_CFG *p_dtb_dump_addr_rb = NULL;
-
-    ZXIC_UINT32 sdt_no = 0;
-
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-
-    p_dtb_dump_addr_rb = dpp_dtb_dump_addr_rb_get(dev, queue_id);
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(p_dtb_dump_addr_rb);
-
-    p_head_dtb_rb = &p_dtb_dump_addr_rb->tn_list;
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(p_head_dtb_rb);
-
-    while(p_head_dtb_rb->used)
-    {
-        p_node = p_head_dtb_rb->p_next;
-        p_rb_tn = (ZXIC_RB_TN *)p_node->data;
-        p_rbkey = (DPP_DTB_DUMP_ADDR_INFO_T *)p_rb_tn->p_key;
-
-        sdt_no = p_rbkey->sdt_no;
-        rc = dpp_dtb_dump_sdt_addr_clear(dev, queue_id, sdt_no);
-        if (DPP_HASH_RC_DEL_SRHFAIL == rc)
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dtb dump delete key is not exist, std:%d\n", sdt_no);
-        }
-        else
-        {
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_dtb_dump_sdt_addr_clear");
-        }
-    }
-
-    rc  =  zxic_comm_rb_destroy(p_dtb_dump_addr_rb);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_rb_init");
-
-    return rc;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	D_NODE *p_node = NULL;
+	ZXIC_RB_TN *p_rb_tn = NULL;
+	DPP_DTB_DUMP_ADDR_INFO_T *p_rbkey = NULL;
+	D_HEAD *p_head_dtb_rb = NULL;
+	ZXIC_RB_CFG *p_dtb_dump_addr_rb = NULL;
+
+	ZXIC_UINT32 sdt_no = 0;
+
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0,
+										DPP_DTB_QUEUE_NUM_MAX - 1);
+
+	p_dtb_dump_addr_rb = dpp_dtb_dump_addr_rb_get(dev, queue_id);
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(p_dtb_dump_addr_rb);
+
+	p_head_dtb_rb = &p_dtb_dump_addr_rb->tn_list;
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(p_head_dtb_rb);
+
+	while (p_head_dtb_rb->used) {
+		p_node = p_head_dtb_rb->p_next;
+		p_rb_tn = (ZXIC_RB_TN *)p_node->data;
+		p_rbkey = (DPP_DTB_DUMP_ADDR_INFO_T *)p_rb_tn->p_key;
+
+		sdt_no = p_rbkey->sdt_no;
+		rc = dpp_dtb_dump_sdt_addr_clear(dev, queue_id, sdt_no);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_sdt_addr_clear");
+
+		if (DPP_HASH_RC_DEL_SRHFAIL == rc) {
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					DEV_ID(dev), "dtb dump delete key is not exist, std:%d\n",
+					sdt_no);
+		} else {
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+								   "dpp_dtb_dump_sdt_addr_clear");
+		}
+	}
+
+	rc = zxic_comm_rb_destroy(p_dtb_dump_addr_rb);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_rb_init");
+
+	return rc;
 }
 
 /*dump地址信息获取*/
-ZXIC_UINT32 dpp_dtb_dump_sdt_addr_get(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 queue_id,  
-                                      ZXIC_UINT32 sdt_no, 
-                                      ZXIC_UINT64 *phy_addr, 
-                                      ZXIC_UINT64 *vir_addr, 
-                                      ZXIC_UINT32 *size)
+ZXIC_UINT32 dpp_dtb_dump_sdt_addr_get(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									  ZXIC_UINT32 sdt_no, ZXIC_UINT64 *phy_addr,
+									  ZXIC_UINT64 *vir_addr, ZXIC_UINT32 *size)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-
-    DPP_DTB_DUMP_ADDR_INFO_T dtb_dump_addr_info = {0};
-    ZXIC_RB_CFG *p_dtb_dump_addr_rb = NULL;
-
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-
-    dtb_dump_addr_info.sdt_no = sdt_no;
-    p_dtb_dump_addr_rb = dpp_dtb_dump_addr_rb_get(dev, queue_id);
-    rc = dpp_apt_sw_list_search(p_dtb_dump_addr_rb, &dtb_dump_addr_info, sizeof(DPP_DTB_DUMP_ADDR_INFO_T));
-    if (rc == DPP_OK)
-    {
-        ZXIC_COMM_TRACE_INFO("search sdt_no %d success.\n", sdt_no);
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_ERROR("search sdt_no %d fail.\n", sdt_no);
-        return rc;
-    }
-
-    *phy_addr = dtb_dump_addr_info.phyAddr;
-    *vir_addr = dtb_dump_addr_info.virAddr;
-    *size = dtb_dump_addr_info.size;
-
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_get: queue    :%d\n", queue_id); 
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_get: sdt_no   :%d\n", sdt_no); 
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_get: phyAddr  :0x%016llx\n", dtb_dump_addr_info.phyAddr); 
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_get: vir_addr :0x%016llx\n", dtb_dump_addr_info.virAddr); 
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_get: size     :0x%x\n", dtb_dump_addr_info.size); 
-
-    return rc;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	DPP_DTB_DUMP_ADDR_INFO_T dtb_dump_addr_info = { 0 };
+	ZXIC_RB_CFG *p_dtb_dump_addr_rb = NULL;
+
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queue_id, 0,
+										DPP_DTB_QUEUE_NUM_MAX - 1);
+
+	dtb_dump_addr_info.sdt_no = sdt_no;
+	p_dtb_dump_addr_rb = dpp_dtb_dump_addr_rb_get(dev, queue_id);
+	rc = dpp_apt_sw_list_search(p_dtb_dump_addr_rb, &dtb_dump_addr_info,
+								sizeof(DPP_DTB_DUMP_ADDR_INFO_T));
+	if (rc == DPP_OK) {
+		ZXIC_COMM_TRACE_INFO("search sdt_no %d success.\n", sdt_no);
+	} else {
+		ZXIC_COMM_TRACE_ERROR("search sdt_no %d fail.\n", sdt_no);
+		return rc;
+	}
+
+	*phy_addr = dtb_dump_addr_info.phyAddr;
+	*vir_addr = dtb_dump_addr_info.virAddr;
+	*size = dtb_dump_addr_info.size;
+
+	ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_get: queue    :%d\n", queue_id);
+	ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_get: sdt_no   :%d\n", sdt_no);
+	ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_get: phyAddr  :0x%016llx\n",
+						 dtb_dump_addr_info.phyAddr);
+	ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_get: vir_addr :0x%016llx\n",
+						 dtb_dump_addr_info.virAddr);
+	ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_get: size     :0x%x\n",
+						 dtb_dump_addr_info.size);
+
+	return rc;
 }
 
 /***********************************************************/
 /** DTB通道申请
-* @param   devId       NP设备号
-* @param   pName       申请DTB通道的唯一设备名(最大32字符)
-* @param   pQueueId    申请到的DTB通道编号
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_requst(DPP_DEV_T *dev, ZXIC_CONST ZXIC_UINT8* pName, 
-                                 ZXIC_UINT16 vPort, 
-                                 ZXIC_UINT32 *pQueueId)
+ * @param   devId       NP设备号
+ * @param   pName       申请DTB通道的唯一设备名(最大32字符)
+ * @param   pQueueId    申请到的DTB通道编号
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/07/03
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_requst(DPP_DEV_T *dev, ZXIC_UINT8 *pName,
+								 ZXIC_UINT16 vPort, ZXIC_UINT32 *pQueueId)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-    ZXIC_UINT32 queue_id = 0;
-    ZXIC_MUTEX_T *p_dtb_mutex = NULL;
-    DPP_DEV_MUTEX_TYPE_E mutex = 0;
-    ZXIC_UINT32 vport_info = (ZXIC_UINT32)vPort;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 queue_id = 0;
+	ZXIC_MUTEX_T *p_dtb_mutex = NULL;
+	DPP_DEV_MUTEX_TYPE_E mutex = 0;
+	ZXIC_UINT32 vport_info = (ZXIC_UINT32)vPort;
 
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pName);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pQueueId);
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pName);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pQueueId);
 
-    //使用代理通道要加锁
-    mutex = DPP_DEV_MUTEX_T_DTB;
-    rc = dpp_dev_opr_mutex_get(DEV_ID(dev), (ZXIC_UINT32)mutex, &p_dtb_mutex);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dev_opr_mutex_get");
+	//使用代理通道要加锁
+	mutex = DPP_DEV_MUTEX_T_DTB;
+	rc = dpp_dev_opr_mutex_get(DEV_ID(dev), (ZXIC_UINT32)mutex, &p_dtb_mutex);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dev_opr_mutex_get");
 
-    rc = zxic_comm_mutex_lock(p_dtb_mutex);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_mutex_lock");
+	rc = zxic_comm_mutex_lock(p_dtb_mutex);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_mutex_lock");
 
-    rc = dpp_agent_channel_dtb_queue_request(dev, pName, vport_info, &queue_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_agent_channel_dtb_queue_request", p_dtb_mutex);
+	rc = dpp_agent_channel_dtb_queue_request(dev, pName, vport_info, &queue_id);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+			DEV_ID(dev), rc, "dpp_agent_channel_dtb_queue_request",
+			p_dtb_mutex);
 
-    rc = zxic_comm_mutex_unlock(p_dtb_mutex);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_mutex_unlock");
+	rc = zxic_comm_mutex_unlock(p_dtb_mutex);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_mutex_unlock");
 
-    rc = dpp_dtb_dump_addr_rb_init(dev, queue_id);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_addr_rb_init");
+	rc = dpp_dtb_dump_addr_rb_init(dev, queue_id);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_addr_rb_init");
 
-    *pQueueId = queue_id;
+	*pQueueId = queue_id;
 
-    ZXIC_COMM_PRINT("dpp_dtb_queue_requst:slot %d name %s vport 0x%x queue_id %d\n", DEV_PCIE_SLOT(dev), pName, vport_info, queue_id);
+	ZXIC_COMM_PRINT(
+			"dpp_dtb_queue_requst:slot %d name %s vport 0x%x queue_id %d\n",
+			DEV_PCIE_SLOT(dev), pName, vport_info, queue_id);
 
-    return rc;
+	return rc;
 }
 
 /***********************************************************/
 /** DTB通道释放
-* @param   devId       NP设备号
-* @param   pName       要释放DTB通道的唯一设备名(最大32字符)
-* @param   pQueueId    要释放的DTB通道编号
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/
-ZXIC_UINT32 dpp_dtb_queue_release(DPP_DEV_T *dev, ZXIC_CONST ZXIC_UINT8* pName, 
-                                  ZXIC_UINT32 queueId)
+ * @param   devId       NP设备号
+ * @param   pName       要释放DTB通道的唯一设备名(最大32字符)
+ * @param   pQueueId    要释放的DTB通道编号
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/07/03
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_queue_release(DPP_DEV_T *dev, ZXIC_UINT8 *pName,
+								  ZXIC_UINT32 queueId)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-    ZXIC_MUTEX_T *p_dtb_mutex = NULL;
-    DPP_DEV_MUTEX_TYPE_E mutex = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_MUTEX_T *p_dtb_mutex = NULL;
+	DPP_DEV_MUTEX_TYPE_E mutex = 0;
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pName);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0,
+										DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pName);
 
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_queue_release:queue_id %d\n", queueId);
+	ZXIC_COMM_TRACE_INFO("dpp_dtb_queue_release:queue_id %d\n", queueId);
 
-    //使用代理通道要加锁
-    mutex = DPP_DEV_MUTEX_T_DTB;
-    rc = dpp_dev_opr_mutex_get(DEV_ID(dev), (ZXIC_UINT32)mutex, &p_dtb_mutex);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dev_opr_mutex_get");
+	//使用代理通道要加锁
+	mutex = DPP_DEV_MUTEX_T_DTB;
+	rc = dpp_dev_opr_mutex_get(DEV_ID(dev), (ZXIC_UINT32)mutex, &p_dtb_mutex);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dev_opr_mutex_get");
 
-    rc = zxic_comm_mutex_lock(p_dtb_mutex);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_mutex_lock");
+	rc = zxic_comm_mutex_lock(p_dtb_mutex);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_mutex_lock");
 
-    rc = dpp_agent_channel_dtb_queue_release(dev, pName, queueId);
+	rc = dpp_agent_channel_dtb_queue_release(dev, pName, queueId);
 
-    if(rc == DPP_RC_DTB_QUEUE_NOT_ALLOC)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dtb slot %d queue id %d not request. \n", DEV_PCIE_SLOT(dev), queueId);
-    }
+	if (rc == DPP_RC_DTB_QUEUE_NOT_ALLOC) {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+								  "dtb slot %d queue id %d not request. \n",
+								  DEV_PCIE_SLOT(dev), queueId);
+	}
 
-    if(rc == DPP_RC_DTB_QUEUE_NAME_ERROR)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dtb slot %d queue %d name error. \n", DEV_PCIE_SLOT(dev), queueId);
-    }
+	if (rc == DPP_RC_DTB_QUEUE_NAME_ERROR) {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+								  "dtb slot %d queue %d name error. \n",
+								  DEV_PCIE_SLOT(dev), queueId);
+	}
 
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_agent_channel_dtb_queue_release", p_dtb_mutex);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+			DEV_ID(dev), rc, "dpp_agent_channel_dtb_queue_release",
+			p_dtb_mutex);
 
-    rc = zxic_comm_mutex_unlock(p_dtb_mutex);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_mutex_unlock");
+	rc = zxic_comm_mutex_unlock(p_dtb_mutex);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_mutex_unlock");
 
-    rc =  dpp_dtb_dump_addr_rb_destroy(dev, queueId);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_addr_rb_destroy");
+	rc = dpp_dtb_dump_addr_rb_destroy(dev, queueId);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_addr_rb_destroy");
 
-    rc = dpp_dtb_queue_id_free(dev, queueId);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_id_free");
+	rc = dpp_dtb_queue_id_free(dev, queueId);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_id_free");
 
-    ZXIC_COMM_PRINT("dpp_dtb_queue_release:slot %d name %s queue_id %d\n", DEV_PCIE_SLOT(dev), pName, queueId);
+	ZXIC_COMM_PRINT("dpp_dtb_queue_release:slot %d name %s queue_id %d\n",
+					DEV_PCIE_SLOT(dev), pName, queueId);
 
-    return rc;
+	return rc;
 }
 
 /***********************************************************/
 /** DTB通道用户信息配置
-* @param   devId      NP设备号
-* @param   queueId    DTB通道编号
-* @param   vPort      vport信息
-* @param   vector     中断号
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/
-ZXIC_UINT32 dpp_dtb_user_info_set(DPP_DEV_T *dev,
-                                  ZXIC_UINT32 queueId, 
-                                  ZXIC_UINT16 vPort, 
-                                  ZXIC_UINT32 vector)
+ * @param   devId      NP设备号
+ * @param   queueId    DTB通道编号
+ * @param   vPort      vport信息
+ * @param   vector     中断号
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/07/03
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_user_info_set(DPP_DEV_T *dev, ZXIC_UINT32 queueId,
+								  ZXIC_UINT16 vPort, ZXIC_UINT32 vector)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-
-    ZXIC_UINT32 temp_epid;
-    ZXIC_UINT32 temp_func_active;
-    ZXIC_UINT32 temp_func_num;
-    ZXIC_UINT32 temp_vfunc_num;
-    ZXIC_UINT32 virtioPort = (ZXIC_UINT32)vPort;
-
-    DPP_DTB_QUEUE_VM_INFO_T vm_info = {0};
-    DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL;
-
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-
-    p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev));
-    if (p_dtb_mgr == ZXIC_NULL)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "ErrorCode[0x%x]: DTB Manager is not exist!!!\n", DPP_RC_DTB_MGR_NOT_EXIST);
-        return DPP_RC_DTB_MGR_NOT_EXIST;
-    }
-
-    ZXIC_COMM_UINT32_GET_BITS(temp_epid, virtioPort, VPORT_EPID_BT_START, VPORT_EPID_BT_LEN);
-    ZXIC_COMM_UINT32_GET_BITS(temp_func_active, virtioPort, VPORT_FUNC_ACTIVE_BT_START, VPORT_FUNC_ACTIVE_BT_LEN);
-    ZXIC_COMM_UINT32_GET_BITS(temp_func_num, virtioPort, VPORT_FUNC_NUM_BT_START, VPORT_FUNC_NUM_BT_LEN);
-    ZXIC_COMM_UINT32_GET_BITS(temp_vfunc_num, virtioPort, VPORT_VFUNC_NUM_BT_START, VPORT_VFUNC_NUM_BT_LEN);
-
-    rc = dpp_dtb_queue_vm_info_get(dev, queueId, &vm_info);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_vm_info_get");
-
-    vm_info.dbi_en = msix_interrupt_mode;
-    vm_info.epid = dpp_dtb_ep_id_get(temp_epid);
-    vm_info.vfunc_num = temp_vfunc_num;
-    vm_info.func_num = temp_func_num;
-    vm_info.vfunc_active = temp_func_active;
-    vm_info.vector = vector;
-
-    ZXIC_COMM_PRINT("dpp_dtb_user_info_set:queue %d vport 0x%x, vector:%x\n", queueId, vPort, vector);
-    ZXIC_COMM_PRINT("dpp_dtb_user_info_set:dbi_en 0x%x\n", vm_info.dbi_en);
-    ZXIC_COMM_PRINT("dpp_dtb_user_info_set:epid 0x%x\n", vm_info.epid);
-    ZXIC_COMM_PRINT("dpp_dtb_user_info_set:vfunc_num 0x%x\n", vm_info.vfunc_num);
-    ZXIC_COMM_PRINT("dpp_dtb_user_info_set:func_num 0x%x\n", vm_info.func_num);
-    ZXIC_COMM_PRINT("dpp_dtb_user_info_set:vfunc_active 0x%x\n", vm_info.vfunc_active);
-
-    p_dtb_mgr->queue_info[queueId].vport = vPort;
-    p_dtb_mgr->queue_info[queueId].vector = vector;
-
-    rc = dpp_dtb_queue_vm_info_set(dev, queueId, &vm_info);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_vm_info_set");
-
-    return rc;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	ZXIC_UINT32 temp_epid;
+	ZXIC_UINT32 temp_func_active;
+	ZXIC_UINT32 temp_func_num;
+	ZXIC_UINT32 temp_vfunc_num;
+	ZXIC_UINT32 virtioPort = (ZXIC_UINT32)vPort;
+
+	DPP_DTB_QUEUE_VM_INFO_T vm_info = { 0 };
+	DPP_DTB_MGR_T *p_dtb_mgr = ZXIC_NULL;
+
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0,
+										DPP_DTB_QUEUE_NUM_MAX - 1);
+
+	p_dtb_mgr = dpp_dtb_mgr_get(DEV_PCIE_SLOT(dev), DEV_ID(dev));
+	if (p_dtb_mgr == ZXIC_NULL) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev), "ErrorCode[0x%x]: DTB Manager is not exist!!!\n",
+				DPP_RC_DTB_MGR_NOT_EXIST);
+		return DPP_RC_DTB_MGR_NOT_EXIST;
+	}
+
+	ZXIC_COMM_UINT32_GET_BITS(temp_epid, virtioPort, VPORT_EPID_BT_START,
+							  VPORT_EPID_BT_LEN);
+	ZXIC_COMM_UINT32_GET_BITS(temp_func_active, virtioPort,
+							  VPORT_FUNC_ACTIVE_BT_START,
+							  VPORT_FUNC_ACTIVE_BT_LEN);
+	ZXIC_COMM_UINT32_GET_BITS(temp_func_num, virtioPort,
+							  VPORT_FUNC_NUM_BT_START, VPORT_FUNC_NUM_BT_LEN);
+	ZXIC_COMM_UINT32_GET_BITS(temp_vfunc_num, virtioPort,
+							  VPORT_VFUNC_NUM_BT_START, VPORT_VFUNC_NUM_BT_LEN);
+
+	rc = dpp_dtb_queue_vm_info_get(dev, queueId, &vm_info);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_vm_info_get");
+
+	vm_info.dbi_en = msix_interrupt_mode;
+	vm_info.epid = dpp_dtb_ep_id_get(temp_epid);
+	vm_info.vfunc_num = temp_vfunc_num;
+	vm_info.func_num = temp_func_num;
+	vm_info.vfunc_active = temp_func_active;
+	vm_info.vector = vector;
+
+	ZXIC_COMM_PRINT("dpp_dtb_user_info_set:queue %d vport 0x%x, vector:%x\n",
+					queueId, vPort, vector);
+	ZXIC_COMM_PRINT("dpp_dtb_user_info_set:dbi_en 0x%x\n", vm_info.dbi_en);
+	ZXIC_COMM_PRINT("dpp_dtb_user_info_set:epid 0x%x\n", vm_info.epid);
+	ZXIC_COMM_PRINT("dpp_dtb_user_info_set:vfunc_num 0x%x\n",
+					vm_info.vfunc_num);
+	ZXIC_COMM_PRINT("dpp_dtb_user_info_set:func_num 0x%x\n", vm_info.func_num);
+	ZXIC_COMM_PRINT("dpp_dtb_user_info_set:vfunc_active 0x%x\n",
+					vm_info.vfunc_active);
+
+	p_dtb_mgr->queue_info[queueId].vport = vPort;
+	p_dtb_mgr->queue_info[queueId].vector = vector;
+
+	rc = dpp_dtb_queue_vm_info_set(dev, queueId, &vm_info);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_queue_vm_info_set");
+
+	return rc;
 }
 
 /***********************************************************/
 /** DTB通道下表空间地址设置,空间大小[32*(16+16*1024)B]
-* @param   devId      NP设备号
-* @param   queueId    DTB通道编号
-* @param   phyAddr    物理地址
-* @param   virAddr    虚拟地址
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/
+ * @param   devId      NP设备号
+ * @param   queueId    DTB通道编号
+ * @param   phyAddr    物理地址
+ * @param   virAddr    虚拟地址
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/07/03
+ ************************************************************/
 ZXIC_UINT32 dpp_dtb_queue_down_table_addr_set(DPP_DEV_T *dev,
-                                              ZXIC_UINT32 queueId, 
-                                              ZXIC_UINT64 phyAddr, 
-                                              ZXIC_UINT64 virAddr)
+											  ZXIC_UINT32 queueId,
+											  ZXIC_UINT64 phyAddr,
+											  ZXIC_UINT64 virAddr)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0,
+										DPP_DTB_QUEUE_NUM_MAX - 1);
 
-    ZXIC_COMM_PRINT("dpp_dtb_queue_down_table_addr_set:slot %d queue %d phyAddr 0x%llx\n", DEV_PCIE_SLOT(dev), queueId, phyAddr);
-    ZXIC_COMM_PRINT("dpp_dtb_queue_down_table_addr_set:slot %d queue %d virAddr 0x%llx\n", DEV_PCIE_SLOT(dev), queueId, virAddr);
+	ZXIC_COMM_PRINT(
+			"dpp_dtb_queue_down_table_addr_set:slot %d queue %d phyAddr 0x%llx\n",
+			DEV_PCIE_SLOT(dev), queueId, phyAddr);
+	ZXIC_COMM_PRINT(
+			"dpp_dtb_queue_down_table_addr_set:slot %d queue %d virAddr 0x%llx\n",
+			DEV_PCIE_SLOT(dev), queueId, virAddr);
 
-    rc = dpp_dtb_down_channel_addr_set(dev, 
-                                       queueId,
-                                       phyAddr,
-                                       virAddr,
-                                       0);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_down_channel_addr_set");
+	rc = dpp_dtb_down_channel_addr_set(dev, queueId, phyAddr, virAddr, 0);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_down_channel_addr_set");
 
-    return rc;
+	return rc;
 }
 
 /***********************************************************/
 /** DTB通道dump空间地址设置,空间大小[32*(16+16*1024)B]
-* @param   devId      NP设备号
-* @param   pName      要释放DTB通道的设备名
-* @param   phyAddr    物理地址
-* @param   virAddr    虚拟地址
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/
+ * @param   devId      NP设备号
+ * @param   pName      要释放DTB通道的设备名
+ * @param   phyAddr    物理地址
+ * @param   virAddr    虚拟地址
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/07/03
+ ************************************************************/
 ZXIC_UINT32 dpp_dtb_queue_dump_table_addr_set(DPP_DEV_T *dev,
-                                              ZXIC_UINT32 queueId, 
-                                              ZXIC_UINT64 phyAddr, 
-                                              ZXIC_UINT64 virAddr)
+											  ZXIC_UINT32 queueId,
+											  ZXIC_UINT64 phyAddr,
+											  ZXIC_UINT64 virAddr)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0,
+										DPP_DTB_QUEUE_NUM_MAX - 1);
 
-    ZXIC_COMM_PRINT("dpp_dtb_queue_dump_table_addr_set:slot %d queue %d phyAddr 0x%llx\n", DEV_PCIE_SLOT(dev), queueId, phyAddr);
-    ZXIC_COMM_PRINT("dpp_dtb_queue_dump_table_addr_set:slot %d queue %d virAddr 0x%llx\n", DEV_PCIE_SLOT(dev), queueId, virAddr);
+	ZXIC_COMM_PRINT(
+			"dpp_dtb_queue_dump_table_addr_set:slot %d queue %d phyAddr 0x%llx\n",
+			DEV_PCIE_SLOT(dev), queueId, phyAddr);
+	ZXIC_COMM_PRINT(
+			"dpp_dtb_queue_dump_table_addr_set:slot %d queue %d virAddr 0x%llx\n",
+			DEV_PCIE_SLOT(dev), queueId, virAddr);
 
-    rc = dpp_dtb_dump_channel_addr_set(dev, 
-                                       queueId, 
-                                       phyAddr, 
-                                       virAddr, 
-                                       0);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_channel_addr_set");
+	rc = dpp_dtb_dump_channel_addr_set(dev, queueId, phyAddr, virAddr, 0);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_dump_channel_addr_set");
 
-    return rc;
+	return rc;
 }
 
 /***********************************************************/
 /** 大批量dump一个流表使用的地址空间配置
-* @param   devId       NP设备号
-* @param   queueId     DTB队列编号
-* @param   sdtNo       流表std号
-* @param   phyAddr     物理地址
-* @param   virAddr     虚拟地址
-* @param   size        (最大64MB)
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/
-ZXIC_UINT32 dpp_dtb_dump_sdt_addr_set(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 queueId,  
-                                      ZXIC_UINT32 sdtNo, 
-                                      ZXIC_UINT64 phyAddr, 
-                                      ZXIC_UINT64 virAddr, 
-                                      ZXIC_UINT32 size)
+ * @param   devId       NP设备号
+ * @param   queueId     DTB队列编号
+ * @param   sdtNo       流表std号
+ * @param   phyAddr     物理地址
+ * @param   virAddr     虚拟地址
+ * @param   size        (最大64MB)
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/07/03
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_dump_sdt_addr_set(DPP_DEV_T *dev, ZXIC_UINT32 queueId,
+									  ZXIC_UINT32 sdtNo, ZXIC_UINT64 phyAddr,
+									  ZXIC_UINT64 virAddr, ZXIC_UINT32 size)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-
-    DPP_DTB_DUMP_ADDR_INFO_T dtb_dump_addr_info = {0};
-    ZXIC_RB_CFG *p_dtb_dump_addr_rb = NULL;
-
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
-
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: slotId :0x%x\n", DEV_PCIE_SLOT(dev));
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: queueId :0x%x\n", queueId);
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: sdtNo :0x%x\n", sdtNo);
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: phyAddr  :0x%016llx\n", phyAddr); 
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: virAddr :0x%016llx\n", virAddr);
-    ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: size :0x%x\n", size);
-
-    dtb_dump_addr_info.sdt_no = sdtNo;
-    dtb_dump_addr_info.phyAddr = phyAddr;
-    dtb_dump_addr_info.virAddr = virAddr;
-    dtb_dump_addr_info.size = size;
-
-    p_dtb_dump_addr_rb = dpp_dtb_dump_addr_rb_get(dev, queueId);
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(p_dtb_dump_addr_rb);
-    ZXIC_COMM_CHECK_INDEX_UPPER_NO_ASSERT(p_dtb_dump_addr_rb->key_size, (ZXIC_UINT32)sizeof(DPP_DTB_DUMP_ADDR_INFO_T));
-
-    rc = dpp_apt_sw_list_insert(p_dtb_dump_addr_rb, &dtb_dump_addr_info, sizeof(DPP_DTB_DUMP_ADDR_INFO_T));
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_apt_sw_list_insert");
-
-    return rc;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	DPP_DTB_DUMP_ADDR_INFO_T dtb_dump_addr_info = { 0 };
+	ZXIC_RB_CFG *p_dtb_dump_addr_rb = NULL;
+
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0,
+										DPP_DTB_QUEUE_NUM_MAX - 1);
+
+	ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: slotId :0x%x\n",
+						 DEV_PCIE_SLOT(dev));
+	ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: queueId :0x%x\n", queueId);
+	ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: sdtNo :0x%x\n", sdtNo);
+	ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: phyAddr  :0x%016llx\n",
+						 phyAddr);
+	ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: virAddr :0x%016llx\n",
+						 virAddr);
+	ZXIC_COMM_TRACE_INFO("dpp_dtb_dump_sdt_addr_set: size :0x%x\n", size);
+
+	dtb_dump_addr_info.sdt_no = sdtNo;
+	dtb_dump_addr_info.phyAddr = phyAddr;
+	dtb_dump_addr_info.virAddr = virAddr;
+	dtb_dump_addr_info.size = size;
+
+	p_dtb_dump_addr_rb = dpp_dtb_dump_addr_rb_get(dev, queueId);
+	rc = dpp_apt_sw_list_insert(p_dtb_dump_addr_rb, &dtb_dump_addr_info,
+								sizeof(DPP_DTB_DUMP_ADDR_INFO_T));
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_apt_sw_list_insert");
+
+	return rc;
 }
 
 /***********************************************************/
 /** 清除大批量dump一个流表使用的地址空间配置
-* @param   devId        NP设备号
-* @param   queueId      DTB队列编号
-* @param   sdtNo        流表std号
-* @return
-* @remark  无
-* @see
-* @author  cbb      @date  2023/07/03
-************************************************************/
-ZXIC_UINT32 dpp_dtb_dump_sdt_addr_clear(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 queueId, 
-                                        ZXIC_UINT32 sdtNo)
+ * @param   devId        NP设备号
+ * @param   queueId      DTB队列编号
+ * @param   sdtNo        流表std号
+ * @return
+ * @remark  无
+ * @see
+ * @author  cbb      @date  2023/07/03
+ ************************************************************/
+ZXIC_UINT32 dpp_dtb_dump_sdt_addr_clear(DPP_DEV_T *dev, ZXIC_UINT32 queueId,
+										ZXIC_UINT32 sdtNo)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    DPP_DTB_DUMP_ADDR_INFO_T dtb_dump_addr_info = {0};
-    ZXIC_RB_CFG *p_dtb_dump_addr_rb = NULL;
+	DPP_DTB_DUMP_ADDR_INFO_T dtb_dump_addr_info = { 0 };
+	ZXIC_RB_CFG *p_dtb_dump_addr_rb = NULL;
 
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0, DPP_DTB_QUEUE_NUM_MAX - 1);
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), queueId, 0,
+										DPP_DTB_QUEUE_NUM_MAX - 1);
 
-    dtb_dump_addr_info.sdt_no = sdtNo;
+	dtb_dump_addr_info.sdt_no = sdtNo;
 
-    p_dtb_dump_addr_rb = dpp_dtb_dump_addr_rb_get(dev, queueId);
-    rc = dpp_apt_sw_list_delete(p_dtb_dump_addr_rb, &dtb_dump_addr_info, sizeof(DPP_DTB_DUMP_ADDR_INFO_T));
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_apt_sw_list_delete");
+	p_dtb_dump_addr_rb = dpp_dtb_dump_addr_rb_get(dev, queueId);
+	rc = dpp_apt_sw_list_delete(p_dtb_dump_addr_rb, &dtb_dump_addr_info,
+								sizeof(DPP_DTB_DUMP_ADDR_INFO_T));
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_apt_sw_list_delete");
 
-    return rc;
+	return rc;
 }
 
 /***********************************************************/
 /** 释放当前sdt下的所有流表(硬件方式)
-* (适用于进程启动后，仅配置流表资源，软件未配置流表，但需要删除硬件上已配置流表的场景) 
-* @param   dev  
-* @param   queue_id  队列号
-* @param   sdt_no  sdt号 
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/12/04
-************************************************************/
-DPP_STATUS dpp_dtb_hash_offline_delete(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 queue_id,
-                                        ZXIC_UINT32 sdt_no)
+ * (适用于进程启动后，仅配置流表资源，软件未配置流表，但需要删除硬件上已配置流表的场景)
+ * @param   dev
+ * @param   queue_id  队列号
+ * @param   sdt_no  sdt号
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/12/04
+ ************************************************************/
+DPP_STATUS dpp_dtb_hash_offline_delete(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									   ZXIC_UINT32 sdt_no)
 
 {
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 entryNum = 0;
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT32 max_item_num = DTB_DUMP_MULTICAST_MAC_DUMP_NUM;
-    ZXIC_UINT8* pDumpData = NULL;
-    ZXIC_UINT8 *pKey = NULL;
-    ZXIC_UINT8 *pRst = NULL;
-    ZXIC_UINT32 element_id = 0;
-
-    ZXIC_UINT32 dma_size  = 0;
-    ZXIC_UINT64 dma_phy_addr = 0;
-    ZXIC_UINT64 dma_vir_addr = 0;
-    
-    DPP_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry = NULL;
-    DPP_DTB_HASH_ENTRY_INFO_T *p_temp_entry = NULL;
-    DPP_SDTTBL_HASH_T sdt_hash_info = {0};  /*SDT内容*/
-
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-    ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-
-    //从sdt_no中获取SDT配置
-    rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
-
-    pDumpData = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num*sizeof(DPP_DTB_HASH_ENTRY_INFO_T));
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(pDumpData);
-    pKey = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_KEY_MAX);
-    ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(pKey, pDumpData);
-    pRst = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_RST_MAX);
-    ZXIC_COMM_CHECK_POINT_MEMORY_FREE2PTR_NO_ASSERT(pRst, pKey, pDumpData);
-
-    ZXIC_COMM_MEMSET(pDumpData,0x0,max_item_num*sizeof(DPP_DTB_HASH_ENTRY_INFO_T));
-    ZXIC_COMM_MEMSET(pKey,0x0,max_item_num*HASH_KEY_MAX);
-    ZXIC_COMM_MEMSET(pRst,0x0,max_item_num*HASH_RST_MAX);
-
-    p_dtb_hash_entry = (DPP_DTB_HASH_ENTRY_INFO_T *)pDumpData;
-    for(index = 0;index<max_item_num;index++)
-    {
-        p_temp_entry = p_dtb_hash_entry + index;
-        p_temp_entry->p_actu_key = pKey + index * HASH_KEY_MAX;
-        p_temp_entry->p_rst = pRst + index * HASH_RST_MAX;
-    }
-
-    rc = dtb_sdt_dump_dma_alloc(dev, DTB_SDT_DUMP_SIZE, &dma_phy_addr, &dma_vir_addr);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, "dtb_sdt_dump_dma_alloc", pRst, pKey, pDumpData);
-
-    rc = dpp_dtb_dump_sdt_addr_set(dev, queue_id, sdt_no, dma_phy_addr, dma_vir_addr, DTB_SDT_DUMP_SIZE);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, "dpp_dtb_dump_sdt_addr_set", pRst, pKey, pDumpData);
-
-    rc = dpp_dtb_hash_table_only_zcam_dump(dev, queue_id, sdt_no, pDumpData, &entryNum);
-
-    dpp_dtb_dump_sdt_addr_get(dev, queue_id, sdt_no, &dma_phy_addr, &dma_vir_addr, &dma_size);
-    dtb_sdt_dump_dma_release(dev, dma_size, dma_phy_addr, dma_vir_addr);
-    dpp_dtb_dump_sdt_addr_clear(dev, queue_id, sdt_no);
-
-    if(DPP_OK != rc)
-    {
-        ZXIC_COMM_TRACE_ERROR("dpp_dtb_hash_table_only_zcam_dump: sdt :0x%x fail\n", sdt_no);
-        ZXIC_COMM_FREE(p_dtb_hash_entry);
-        ZXIC_COMM_FREE(pKey);
-        ZXIC_COMM_FREE(pRst);
-        return rc;
-    }
-
-    ZXIC_COMM_PRINT("dpp_dtb_hash_table_only_zcam_dump valid entry num is %u\n",entryNum);
-
-    for(index = 0; index < entryNum; index++)
-    {
-        p_temp_entry = p_dtb_hash_entry + index;
-        // //打印数据
-        dpp_dtb_data_print(p_temp_entry->p_actu_key, DPP_GET_ACTU_KEY_BY_SIZE(sdt_hash_info.key_size) + 1);
-        dpp_dtb_data_print(p_temp_entry->p_rst, 4 * (0x1 << sdt_hash_info.rsp_mode));
-    }
-
-    rc = dpp_dtb_hash_dma_delete_hardware(dev, queue_id, sdt_no, entryNum, p_dtb_hash_entry, &element_id);
-    ZXIC_COMM_FREE(p_dtb_hash_entry);
-    ZXIC_COMM_FREE(pKey);
-    ZXIC_COMM_FREE(pRst);
-    ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_dma_delete_hardware"); 
-               
-    return DPP_OK;
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 entryNum = 0;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 max_item_num = DTB_DUMP_MULTICAST_MAC_DUMP_NUM;
+	ZXIC_UINT8 *pDumpData = NULL;
+	ZXIC_UINT8 *pKey = NULL;
+	ZXIC_UINT8 *pRst = NULL;
+	ZXIC_UINT32 element_id = 0;
+
+	ZXIC_UINT32 dma_size = 0;
+	ZXIC_UINT64 dma_phy_addr = 0;
+	ZXIC_UINT64 dma_vir_addr = 0;
+
+	DPP_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry = NULL;
+	DPP_DTB_HASH_ENTRY_INFO_T *p_temp_entry = NULL;
+	DPP_SDTTBL_HASH_T sdt_hash_info = { 0 }; /*SDT内容*/
+
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+	ZXIC_COMM_CHECK_INDEX_NO_ASSERT(DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
+
+	//从sdt_no中获取SDT配置
+	rc = dpp_soft_sdt_tbl_get(DEV_ID(dev), sdt_no, &sdt_hash_info);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_soft_sdt_tbl_get");
+
+	pDumpData = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(
+			max_item_num * sizeof(DPP_DTB_HASH_ENTRY_INFO_T));
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(pDumpData);
+	pKey = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_KEY_MAX);
+	ZXIC_COMM_CHECK_POINT_MEMORY_FREE_NO_ASSERT(pKey, pDumpData);
+	pRst = (ZXIC_UINT8 *)ZXIC_COMM_MALLOC(max_item_num * HASH_RST_MAX);
+	ZXIC_COMM_CHECK_POINT_MEMORY_FREE2PTR_NO_ASSERT(pRst, pKey, pDumpData);
+
+	ZXIC_COMM_MEMSET(pDumpData, 0x0,
+					 max_item_num * sizeof(DPP_DTB_HASH_ENTRY_INFO_T));
+	ZXIC_COMM_MEMSET(pKey, 0x0, max_item_num * HASH_KEY_MAX);
+	ZXIC_COMM_MEMSET(pRst, 0x0, max_item_num * HASH_RST_MAX);
+
+	p_dtb_hash_entry = (DPP_DTB_HASH_ENTRY_INFO_T *)pDumpData;
+	for (index = 0; index < max_item_num; index++) {
+		p_temp_entry = p_dtb_hash_entry + index;
+		p_temp_entry->p_actu_key = pKey + index * HASH_KEY_MAX;
+		p_temp_entry->p_rst = pRst + index * HASH_RST_MAX;
+	}
+
+	rc = dtb_sdt_dump_dma_alloc(dev, DTB_SDT_DUMP_SIZE, &dma_phy_addr,
+								&dma_vir_addr);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(rc, "dtb_sdt_dump_dma_alloc",
+												 pRst, pKey, pDumpData);
+
+	rc = dpp_dtb_dump_sdt_addr_set(dev, queue_id, sdt_no, dma_phy_addr,
+								   dma_vir_addr, DTB_SDT_DUMP_SIZE);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE3PTR_NO_ASSERT(
+			rc, "dpp_dtb_dump_sdt_addr_set", pRst, pKey, pDumpData);
+
+	rc = dpp_dtb_hash_table_only_zcam_dump(dev, queue_id, sdt_no, pDumpData,
+										   &entryNum);
+
+	dpp_dtb_dump_sdt_addr_get(dev, queue_id, sdt_no, &dma_phy_addr,
+							  &dma_vir_addr, &dma_size);
+	dtb_sdt_dump_dma_release(dev, dma_size, dma_phy_addr, dma_vir_addr);
+	dpp_dtb_dump_sdt_addr_clear(dev, queue_id, sdt_no);
+
+	if (DPP_OK != rc) {
+		ZXIC_COMM_TRACE_ERROR(
+				"dpp_dtb_hash_table_only_zcam_dump: sdt :0x%x fail\n", sdt_no);
+		ZXIC_COMM_FREE(p_dtb_hash_entry);
+		ZXIC_COMM_FREE(pKey);
+		ZXIC_COMM_FREE(pRst);
+		return rc;
+	}
+
+	ZXIC_COMM_PRINT("dpp_dtb_hash_table_only_zcam_dump valid entry num is %u\n",
+					entryNum);
+
+	for (index = 0; index < entryNum; index++) {
+		p_temp_entry = p_dtb_hash_entry + index;
+		// //打印数据
+		dpp_dtb_data_print(p_temp_entry->p_actu_key,
+						   DPP_GET_ACTU_KEY_BY_SIZE(sdt_hash_info.key_size) +
+								   1);
+		dpp_dtb_data_print(p_temp_entry->p_rst,
+						   4 * (0x1 << sdt_hash_info.rsp_mode));
+	}
+
+	rc = dpp_dtb_hash_dma_delete_hardware(dev, queue_id, sdt_no, entryNum,
+										  p_dtb_hash_entry, &element_id);
+	ZXIC_COMM_FREE(p_dtb_hash_entry);
+	ZXIC_COMM_FREE(pKey);
+	ZXIC_COMM_FREE(pRst);
+	ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_hash_dma_delete_hardware");
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 在线释放当前sdt下的所有流表表项
-* (适用于进程正常退出前删除表项，软件上有存储表项)
-* @param   dev_id  设备号 
-* @param   queue_id  队列号
-* @param   sdt_no  sdt号 
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/12/04
-************************************************************/
-DPP_STATUS dpp_dtb_hash_online_delete(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 queue_id,
-                                        ZXIC_UINT32 sdt_no)
+ * (适用于进程正常退出前删除表项，软件上有存储表项)
+ * @param   dev_id  设备号
+ * @param   queue_id  队列号
+ * @param   sdt_no  sdt号
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/12/04
+ ************************************************************/
+DPP_STATUS dpp_dtb_hash_online_delete(DPP_DEV_T *dev, ZXIC_UINT32 queue_id,
+									  ZXIC_UINT32 sdt_no)
 {
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT8 key_valid = 0;
-    ZXIC_UINT32 table_id = 0;
-    ZXIC_UINT32 key_type = 0;
-    ZXIC_UINT32 element_id = 0;
-
-    D_NODE *p_node = NULL;
-    ZXIC_RB_TN *p_rb_tn = NULL;
-    D_HEAD *p_head_hash_rb = NULL;
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    DPP_HASH_RBKEY_INFO *p_rbkey = NULL;
-    HASH_ENTRY_CFG  hash_entry_cfg = {0}; 
-    DPP_DTB_HASH_ENTRY_INFO_T hashEntry = {0};
-    
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
-    dev_id = DEV_ID(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, queue_id, 0, DTB_QUEUE_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-
-    //从sdt_no中获取hash配置
-    rc = dpp_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_hash_get_hash_info_from_sdt");
-
-    p_hash_cfg = hash_entry_cfg.p_hash_cfg;
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg);
-
-    p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list;
-    p_node = p_head_hash_rb->p_next;
-    while(p_node)
-    {
-        p_rb_tn = (ZXIC_RB_TN *)p_node->data;
-        p_rbkey = (DPP_HASH_RBKEY_INFO *)p_rb_tn->p_key;
-        hashEntry.p_actu_key = p_rbkey->key+1;
-        hashEntry.p_rst = p_rbkey->key;
-
-        key_valid = DPP_GET_HASH_KEY_VALID(p_rbkey->key);
-        table_id = DPP_GET_HASH_TBL_ID(p_rbkey->key);
-        key_type = DPP_GET_HASH_KEY_TYPE(p_rbkey->key);
-        if((!key_valid) 
-            || (table_id != hash_entry_cfg.table_id)
-            || (key_type != hash_entry_cfg.key_type))
-        {
-            p_node = p_node->next; 
-            continue;
-        }
-        p_node = p_node->next;   
-
-        rc = dpp_dtb_hash_dma_delete(dev, queue_id,sdt_no,1,&hashEntry,&element_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_dtb_hash_dma_delete");
-    }
-
-    return DPP_OK;
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT8 key_valid = 0;
+	ZXIC_UINT32 table_id = 0;
+	ZXIC_UINT32 key_type = 0;
+	ZXIC_UINT32 element_id = 0;
+
+	D_NODE *p_node = NULL;
+	ZXIC_RB_TN *p_rb_tn = NULL;
+	D_HEAD *p_head_hash_rb = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	DPP_HASH_RBKEY_INFO *p_rbkey = NULL;
+	HASH_ENTRY_CFG hash_entry_cfg = { 0 };
+	DPP_DTB_HASH_ENTRY_INFO_T hashEntry = { 0 };
+
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(dev);
+	dev_id = DEV_ID(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, queue_id, 0, DTB_QUEUE_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+
+	//从sdt_no中获取hash配置
+	rc = dpp_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc,
+									 "dpp_hash_get_hash_info_from_sdt");
+
+	p_hash_cfg = hash_entry_cfg.p_hash_cfg;
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg);
+
+	p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list;
+	p_node = p_head_hash_rb->p_next;
+	while (p_node) {
+		p_rb_tn = (ZXIC_RB_TN *)p_node->data;
+		p_rbkey = (DPP_HASH_RBKEY_INFO *)p_rb_tn->p_key;
+		hashEntry.p_actu_key = p_rbkey->key + 1;
+		hashEntry.p_rst = p_rbkey->key;
+
+		key_valid = DPP_GET_HASH_KEY_VALID(p_rbkey->key);
+		table_id = DPP_GET_HASH_TBL_ID(p_rbkey->key);
+		key_type = DPP_GET_HASH_KEY_TYPE(p_rbkey->key);
+		if ((!key_valid) || (table_id != hash_entry_cfg.table_id) ||
+			(key_type != hash_entry_cfg.key_type)) {
+			p_node = p_node->next;
+			continue;
+		}
+		p_node = p_node->next;
+
+		rc = dpp_dtb_hash_dma_delete(dev, queue_id, sdt_no, 1, &hashEntry,
+									 &element_id);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_dtb_hash_dma_delete");
+	}
+
+	return DPP_OK;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_hash.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_hash.c
old mode 100755
new mode 100644
index cc620f855dda362267cc216b57dc0a055bb02bf6..aed556437da90fcb0030b5ca178b0b9a5a98f7a8
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_hash.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_hash.c
@@ -1,2960 +1,2277 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_hash.c
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : wcl
-* 完成日期 : 2014/02/08
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-
-#include "zxic_common.h"
-
-#include "dpp_dev.h"
-#include "dpp_module.h"
-#include "dpp_se_cfg.h"
-#include "dpp_hash_crc.h"
-#include "dpp_hash.h"
-#include "dpp_se.h"
-#include "dpp_se_reg.h"
-#include "dpp_reg_api.h"
-#include "dpp_reg_info.h"
-#include "dpp_se4k_reg.h"
-#include "dpp_sdt.h"
-
-#define HASH_CMP_ZCELL     (1)
-#define HASH_CMP_ZBLK      (2)
-
-#define HASH_ENTRY_STAT
-
-/* 全局变量定义区 */
-static ZXIC_UINT32 g_ddr_hash_arg[HASH_DDR_CRC_NUM] = {
-    0x04C11DB7, 0xF4ACFB13, 0x20044009, 0x00210801
-};
-
-static DPP_HASH_TBL_ID_INFO g_tbl_id_info[DPP_DEV_CHANNEL_MAX][HASH_FUNC_ID_NUM][HASH_TBL_ID_NUM] = {{{{0}}}};
-
-/** 4个hash引擎，每个最多使用32个zblock */
-static ZXIC_UINT32 g_hash_zblk_idx[DPP_DEV_CHANNEL_MAX][HASH_FUNC_ID_NUM][HASH_TBL_ID_NUM] = {{{0}}};
-
-static DPP_HASH_SOFT_RESET_STOR_DAT g_hash_store_dat[DPP_DEV_CHANNEL_MAX] = {{{0}}};
-
-static ZXIC_UINT64 g_se_cfg_point = 0;
-
-#if DPP_WRITE_FILE_EN
-static DPP_HASH_FILE_REG_T g_hash_file_reg = {
-    {0x55550000, 0xffffaaaa}, {1, 1, 1, 1},
-    {
-        {0x12121212, 0x12121212}, {0x12121212, 0x12121212},
-        {0x12121212, 0x12121212}, {0x12121212, 0x12121212}
-    },
-    0,
-    0xffff,
-    0,
-    {0},
-    {0}
-};
-#endif
-/* 宏函数定义区 */
-#define GET_DDR_HASH_ARG(ddr_crc_sel)              (g_ddr_hash_arg[ddr_crc_sel])
-#define GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id)       (&g_tbl_id_info[dev_id][fun_id][tbl_id])
-#define GET_ACTU_KEY_SIZE_BY_TBLID(dev_id,fun_id, tbl_id) (g_tbl_id_info[dev_id][fun_id][tbl_id].actu_key_size)
-
-#define HASH_TBL_ID_INFO_CHECK(dev_id,fun_id, tbl_id, key_type) \
-    do{\
-        if (!g_tbl_id_info[dev_id][fun_id][tbl_id].is_init || \
-            (g_tbl_id_info[dev_id][fun_id][tbl_id].key_type != key_type)) \
-        { \
-            ZXIC_COMM_PRINT("init [%d], config ketype[%d] parameter key_type[%d].\n",\
-                      g_tbl_id_info[dev_id][fun_id][tbl_id].is_init, \
-                      g_tbl_id_info[dev_id][fun_id][tbl_id].key_type, \
-                      key_type);\
-            ZXIC_COMM_ASSERT(0); \
-            return DPP_HASH_RC_INVALID_TBL_ID_INFO; \
-        } \
-    }while (0)
-
-
-#define GET_HASH_DDR_HW_ADDR(base_addr, item_idx) \
-    ((base_addr) + (item_idx))
-
-/* 9:zcell depth */
-#define GET_HASH_ZCAM_HW_ADDR(base_addr, zblk_idx, item_idx) \
-    ((base_addr) + ((zblk_idx) << 9) + (item_idx))
-
-#define DPP_GET_HASH_FILE_REG() (&g_hash_file_reg)
-
-/* 局部函数声明区 */
-
-/* 函数实现区 */
-
-#if ZXIC_REAL("inter func.")
-/***********************************************************/
-/** zblock资源链表排序比较函数
-* @param   data1        待比较的数据1
-* @param   data2        待比较的数据2
-* @param   data         排序比较的类型，1-zcell比较，2-zblock比较
-*
-* @return  1-data1比data2的索引大
-           0-data1和data2索引相同
-          -1-data1比data2的索引小
-* @remark  无
-* @see
-* @author  wcl      @date  2014/11/10
-************************************************************/
-ZXIC_SINT32 dpp_hash_list_cmp(D_NODE *data1, D_NODE *data2, void *data)
-{
-    ZXIC_UINT32 flag = 0;
-    ZXIC_UINT32 data_new = 0;
-    ZXIC_UINT32 data_pre = 0;
-
-    ZXIC_COMM_CHECK_POINT(data1);
-    ZXIC_COMM_CHECK_POINT(data2);
-    ZXIC_COMM_CHECK_POINT(data);
-
-    flag = *(ZXIC_UINT32 *)data;
-
-    if (flag == HASH_CMP_ZCELL)
-    {
-        data_new = ((SE_ZCELL_CFG *)data1->data)->zcell_idx;
-        data_pre = ((SE_ZCELL_CFG *)data2->data)->zcell_idx;
-    }
-    else if (flag == HASH_CMP_ZBLK)
-    {
-        data_new = ((SE_ZBLK_CFG *)data1->data)->zblk_idx;
-        data_pre = ((SE_ZBLK_CFG *)data2->data)->zblk_idx;
-    }
-
-    if (data_new > data_pre)
-    {
-        return 1;
-    }
-    else if (data_new == data_pre)
-    {
-        return 0;
-    }
-    else
-    {
-        return -1;
-    }
-}
-
-/***********************************************************/
-/** hash键值红黑树插入比较函数
-* @param   p_new
-* @param   p_old
-* @param   key_size
-*
-* @return
-* @remark  无
-* @see
-* @author  wcl      @date  2014/11/10
-************************************************************/
-ZXIC_SINT32 dpp_hash_rb_key_cmp(ZXIC_VOID *p_new, ZXIC_VOID *p_old, ZXIC_UINT32 key_size)
-{
-    DPP_HASH_RBKEY_INFO *p_rbkey_new = NULL;
-    DPP_HASH_RBKEY_INFO *p_rbkey_old = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_new);
-    ZXIC_COMM_CHECK_POINT(p_old);
-    p_rbkey_new = (DPP_HASH_RBKEY_INFO *)(p_new);
-    p_rbkey_old = (DPP_HASH_RBKEY_INFO *)(p_old);
-
-    return ZXIC_COMM_MEMCMP(p_rbkey_new->key, p_rbkey_old->key, HASH_KEY_MAX);
-}
-
-/***********************************************************/
-/** hash键值红黑树插入比较函数
-* @param   p_new
-* @param   p_old
-* @param   key_size
-*
-* @return
-* @remark  无
-* @see
-* @author  tf      @date  2016/03/26
-************************************************************/
-ZXIC_SINT32 dpp_hash_ddr_cfg_rb_key_cmp(ZXIC_VOID *p_new, ZXIC_VOID *p_old, ZXIC_UINT32 key_size)
-{
-    HASH_DDR_CFG *p_rbkey_new = NULL;
-    HASH_DDR_CFG *p_rbkey_old = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_new);
-    ZXIC_COMM_CHECK_POINT(p_old);
-    p_rbkey_new = (HASH_DDR_CFG *)(p_new);
-    p_rbkey_old = (HASH_DDR_CFG *)(p_old);
-
-    return ZXIC_COMM_MEMCMP(&p_rbkey_new->ddr_baddr, &p_rbkey_old->ddr_baddr, sizeof(ZXIC_UINT32));
-}
-
-/***********************************************************/
-/** 获取位宽
-* @param   ddr_item_num
-*
-* @return
-* @remark  无
-* @see
-* @author  wcl      @date  2014/11/10
-************************************************************/
-ZXIC_UINT32 dpp_hash_ddr_depth_conv(ZXIC_UINT32 ddr_item_num)
-{
-    ZXIC_UINT32 count = 0;
-
-    while (ddr_item_num > ((ZXIC_UINT32)1 << count))
-    {
-        count++;
-    }
-
-    return count;
-}
-
-/***********************************************************/
-/** 片内资源初始化
-* @param   p_hash_cfg
-* @param   zblk_num
-* @param   zblk_idx_array
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wcl      @date  2015/10/13
-************************************************************/
-DPP_STATUS dpp_hash_zcam_resource_init(DPP_HASH_CFG *p_hash_cfg, ZXIC_UINT32 zblk_num, ZXIC_UINT32 *zblk_idx_array)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 cmp_type = 0;
-    ZXIC_UINT32 zblk_idx = 0;
-    ZXIC_UINT32 zcell_idx = 0;
-    ZXIC_UINT32 dev_id = 0;
-
-    D_HEAD *p_zblk_list = NULL;
-    D_HEAD *p_zcell_free = NULL;
-    SE_ZBLK_CFG *p_zblk_cfg = NULL;
-    SE_ZCELL_CFG *p_zcell_cfg = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_hash_cfg);
-    ZXIC_COMM_CHECK_INDEX(zblk_num, 0, SE_ZBLK_NUM);
-    ZXIC_COMM_CHECK_POINT(zblk_idx_array);
-
-    dev_id = p_hash_cfg->p_se_info->dev_id;
-
-    /* init zblock list */
-    p_zblk_list = &p_hash_cfg->hash_shareram.zblk_list;
-    rc = zxic_comm_double_link_init(SE_ZBLK_NUM, p_zblk_list);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_init");
-
-    /* init zcell list */
-    p_zcell_free = &p_hash_cfg->hash_shareram.zcell_free_list;
-    rc = zxic_comm_double_link_init(SE_ZBLK_NUM * SE_ZCELL_NUM, p_zcell_free);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_init");
-
-    for (i = 0; i < zblk_num; i++)
-    {
-        zblk_idx = zblk_idx_array[i];
-        /* debug start */
-        //ZXIC_COMM_PRINT("zblk_idx is [%d]\n", zblk_idx); /* t */
-        /* debug end */
-        ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zblk_idx, 0, SE_ZBLK_NUM - 1);
-        p_zblk_cfg = DPP_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, zblk_idx);
-
-        if (p_zblk_cfg->is_used)
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode:[0x%x], ZBlock[%d] is already used by other function!\n", \
-                                     DPP_HASH_RC_INVALID_ZBLCK, zblk_idx);
-            ZXIC_COMM_ASSERT(0);
-            return DPP_HASH_RC_INVALID_ZBLCK;
-        }
-
-        for (j = 0; j < SE_ZCELL_NUM; j++)
-        {
-            zcell_idx = p_zblk_cfg->zcell_info[j].zcell_idx;
-            p_zcell_cfg = DPP_SE_GET_ZCELL_CFG(p_hash_cfg->p_se_info, zcell_idx);
-
-            if (p_zcell_cfg->is_used)
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode:[0x%x], ZBlk[%d], ZCell[%d] is already used by other function!\n", \
-                                         DPP_HASH_RC_INVALID_ZCELL, zblk_idx, zcell_idx);
-                ZXIC_COMM_ASSERT(0);
-                return DPP_HASH_RC_INVALID_ZCELL;
-            }
-
-            p_zcell_cfg->is_used = 1;
-
-            /* insert to free zcell free list */
-            cmp_type = HASH_CMP_ZCELL;
-            rc = zxic_comm_double_link_insert_sort(&p_zcell_cfg->zcell_dn, p_zcell_free, dpp_hash_list_cmp, &cmp_type);
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_insert_sort");
-        }
-
-        /* insert to zblock list */
-        p_zblk_cfg->is_used = 1;
-        cmp_type = HASH_CMP_ZBLK;
-        rc = zxic_comm_double_link_insert_sort(&p_zblk_cfg->zblk_dn, p_zblk_list, dpp_hash_list_cmp, &cmp_type);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_insert_last");
-
-        /* config zblock */
-        rc = dpp_hash_zblkcfg_write(p_hash_cfg->p_se_info, p_hash_cfg->fun_id, p_zblk_cfg);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_zblkcfg_write");
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**
-* @param   p_hash_cfg
-*
-* @return
-* @remark  无
-* @see
-* @author  XCX      @date  2018/03/22
-************************************************************/
-DPP_STATUS dpp_hash_zcam_resource_deinit(DPP_HASH_CFG *p_hash_cfg)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 dev_id = 0;
-
-    D_NODE *p_node = NULL;
-    D_HEAD *p_head = NULL;
-    SE_ZBLK_CFG *p_zblk_cfg = NULL;
-    SE_ZCELL_CFG *p_zcell_cfg = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_hash_cfg);
-
-    dev_id = p_hash_cfg->p_se_info->dev_id;
-
-    /*delete zcell node*/
-    p_head = &p_hash_cfg->hash_shareram.zcell_free_list;
-
-    while (p_head->used)
-    {
-        p_node = p_head->p_next;
-
-        rc = zxic_comm_double_link_del(p_node, p_head);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_del");
-        p_zcell_cfg = (SE_ZCELL_CFG *)p_node->data;
-        p_zcell_cfg->is_used = 0;
-    }
-
-    /*delete zblk node*/
-    p_head = &p_hash_cfg->hash_shareram.zblk_list;
-
-    while (p_head->used)
-    {
-        p_node = p_head->p_next;
-
-        rc = zxic_comm_double_link_del(p_node, p_head);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_del");
-
-        ZXIC_COMM_CHECK_DEV_INDEX(dev_id, ((SE_ZBLK_CFG *)p_node->data)->zblk_idx, 0, HASH_ZBLK_ID_MAX);
-        p_zblk_cfg = DPP_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, ((SE_ZBLK_CFG *)p_node->data)->zblk_idx);
-        p_zblk_cfg->is_used = 0;
-
-        /*clear zblk config*/
-        /* dpp_hash_zblkcfg_clr(p_hash_cfg->p_se_info, p_hash_cfg->fun_id, p_zblk_cfg); */
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**
-* @param   item_entry_max
-* @param   wrt_mask
-* @param   entry_size
-*
-* @return
-* @remark  无
-* @see
-* @author  XCX      @date  2018/03/22
-************************************************************/
-ZXIC_UINT32 dpp_hash_get_item_free_pos(ZXIC_UINT32 item_entry_max, ZXIC_UINT32 wrt_mask, ZXIC_UINT32 entry_size)
-{
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 pos = 0xFFFFFFFF;/* -1; */
-    ZXIC_UINT32 mask = 0;
-
-    for (i = 0; i < item_entry_max; i += entry_size / HASH_ENTRY_POS_STEP)
-    {
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(i, entry_size / HASH_ENTRY_POS_STEP);
-        mask = DPP_GET_HASH_ENTRY_MASK(entry_size, i);
-
-        if (0 == (mask & wrt_mask))
-        {
-            pos = i;
-            break;
-        }
-    }
-
-    return pos;
-}
-
-/***********************************************************/
-/**
-* @param   p_hash_cfg
-* @param   p_rbkey
-* @param   p_item
-* @param   item_idx
-* @param   item_type
-* @param   insrt_key_type
-*
-* @return
-* @remark  无
-* @see
-* @author  XCX      @date  2018/03/22
-************************************************************/
-DPP_STATUS dpp_hash_insrt_to_item(DPP_HASH_CFG *p_hash_cfg,
-                                  DPP_HASH_RBKEY_INFO *p_rbkey,
-                                  SE_ITEM_CFG *p_item,
-                                  ZXIC_UINT32 item_idx,
-                                  ZXIC_UINT32 item_type,
-                                  ZXIC_UINT32 insrt_key_type)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 free_pos = 0;
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 item_entry_max = ITEM_ENTRY_NUM_4;
-
-    ZXIC_COMM_CHECK_POINT(p_hash_cfg);
-    ZXIC_COMM_CHECK_POINT(p_rbkey);
-    ZXIC_COMM_CHECK_POINT(p_item);
-
-    dev_id = p_hash_cfg->p_se_info->dev_id;
-
-    if (ITEM_DDR_256 == item_type)
-    {
-        item_entry_max = ITEM_ENTRY_NUM_2;
-    }
-
-    if (!p_item->valid) /* item is not used */
-    {
-        rc = zxic_comm_double_link_init(item_entry_max, &p_item->item_list);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_init");
-
-        p_rbkey->entry_pos = HASH_ITEM_POS_0;
-        p_item->wrt_mask = DPP_GET_HASH_ENTRY_MASK(p_rbkey->entry_size, p_rbkey->entry_pos);
-        p_item->item_index = item_idx;
-        p_item->item_type = item_type;
-        p_item->valid = 1;
-    }
-    else
-    {
-        free_pos = dpp_hash_get_item_free_pos(item_entry_max, p_item->wrt_mask, p_rbkey->entry_size);
-
-        if (0xFFFFFFFF == free_pos)
-        {
-            return DPP_HASH_RC_ITEM_FULL;
-        }
-        else
-        {
-            p_rbkey->entry_pos = free_pos;
-            p_item->wrt_mask   |= DPP_GET_HASH_ENTRY_MASK(p_rbkey->entry_size, p_rbkey->entry_pos);
-        }
-    }
-
-    /* debug*/
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "Entry in item pos is: [%d], entry size is: [%d].\n", free_pos, p_rbkey->entry_size);
-
-    rc = zxic_comm_double_link_insert_last(&p_rbkey->entry_dn, &p_item->item_list);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_insert_last");
-
-    p_rbkey->p_item_info = p_item;
-
-    return DPP_OK;
-}
-
-#endif
-
-#if ZXIC_REAL("External Func.")
-/***********************************************************/
-/** 单个hash引擎初始化
-* @param   p_se_cfg      算法模块公共管理数据结构指针
-* @param   fun_id        hash引擎号
-* @param   zblk_num      分配给此hash引擎的zblock数目
-* @param   zblk_idx      分配给此hash引擎的zblock编号
-* @param   ddr_dis       DDR关闭位，0-不关闭片外DDR, 1-关闭片外DDR
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wcl      @date  2015/05/15
-************************************************************/
-DPP_STATUS dpp_hash_init(DPP_SE_CFG *p_se_cfg,
-                         ZXIC_UINT32 fun_id,
-                         ZXIC_UINT32 zblk_num,
-                         ZXIC_UINT32 *zblk_idx,
-                         ZXIC_UINT32 ddr_dis)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 dev_id = 0;
-
-    FUNC_ID_INFO *p_func_info = NULL;
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
-    ZXIC_COMM_CHECK_POINT(zblk_idx);
-    ZXIC_COMM_CHECK_INDEX(fun_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1);
-    ZXIC_COMM_CHECK_INDEX(zblk_num, 0, SE_ZBLK_NUM);
-    ZXIC_COMM_CHECK_INDEX(ddr_dis, 0, 1);
-
-    dev_id = p_se_cfg->dev_id;
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1);
-
-    rc = dpp_se_fun_init(p_se_cfg, (fun_id & 0xff), FUN_HASH);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_fun_init");
-
-    p_func_info = DPP_GET_FUN_INFO(p_se_cfg, fun_id);
-    p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
-    p_hash_cfg->fun_id = fun_id;
-    p_hash_cfg->p_hash32_fun = dpp_crc32_calc;
-    p_hash_cfg->p_hash16_fun = dpp_crc16_calc;
-    p_hash_cfg->p_se_info = p_se_cfg;
-
-    /*    判定hash引擎是片内模式还是混合模式*/
-    if (ddr_dis == 1)
-    {
-        /* disable ddr */
-        p_hash_cfg->ddr_valid = 0;
-
-#ifdef DPP_FLOW_HW_INIT
-        rc = dpp_hash_ext_cfg_clr(p_se_cfg, fun_id);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_ddrcfg_clr");
-
-        rc = dpp_hash_tbl_depth_clr(p_se_cfg, fun_id);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_tbl_depth_clr");
-#endif
-
-    }
-    else
-    {
-        p_hash_cfg->ddr_valid = 1;
-
-    }
-
-    /*    zcam初始化*/
-    p_hash_cfg->hash_stat.zblock_num = zblk_num;
-    rc = dpp_hash_zcam_resource_init(p_hash_cfg, zblk_num, zblk_idx);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_zcam_resource_init");
-
-    /* 将zblock_id记录在软件缓存中 */
-    for(i = 0; i < zblk_num; i++)
-    {
-        p_hash_cfg->hash_stat.zblock_array[i] = zblk_idx[i];
-    }
-
-    /* dynamic alloc rb_tree node by user. */
-    rc = (DPP_STATUS)zxic_comm_rb_init(&p_hash_cfg->hash_rb,
-                                 0,
-                                 sizeof(DPP_HASH_RBKEY_INFO),
-                                 dpp_hash_rb_key_cmp);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_rb_init");
-
-    /* dynamic alloc rb_tree node by user. */
-    rc = (DPP_STATUS)zxic_comm_rb_init(&p_hash_cfg->ddr_cfg_rb,
-                                 0,
-                                 sizeof(HASH_DDR_CFG),
-                                 dpp_hash_ddr_cfg_rb_key_cmp);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_rb_init");
-
-    /** for 软复位 */
-    /** 保存zblock内容 */
-    for (i = 0; i < zblk_num; i++)
-    {
-        g_hash_zblk_idx[dev_id][fun_id][i] = zblk_idx[i];
-    }
-
-    g_hash_store_dat[dev_id].ddr_dis_flag[fun_id] = ddr_dis;
-    g_hash_store_dat[dev_id].zblk_num[fun_id] = zblk_num;
-    g_hash_store_dat[dev_id].zblk_idx_start[fun_id] = g_hash_zblk_idx[dev_id][fun_id];
-    g_hash_store_dat[dev_id].hash_id_valid |= (ZXIC_UINT32)((1U << fun_id) & 0xffffffff);
-
-    /** for diag */
-    g_se_cfg_point = ZXIC_COMM_PTR_TO_VAL(p_se_cfg);
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 初始化单个hash引擎内的某个业务表，此接口支持为该业务表分配独占的zcell。
-*     必须先初始化hash引擎，再初始化业务表。
-* @param   p_se_cfg        算法模块公共管理数据结构指针
-* @param   fun_id          hash引擎号
-* @param   bulk_id         每个Hash引擎资源划分的空间ID号
-* @param   p_ddr_resc_cfg  分配给hash引擎此资源空间的ddr资源属性
-* @param   zcell_num       分配给hash引擎此资源空间的zcell数量
-* @param   zreg_num        分配给hash引擎此资源空间的zreg数量
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wcl      @date  2015/05/15
-************************************************************/
-DPP_STATUS dpp_hash_bulk_init(DPP_SE_CFG *p_se_cfg,
-                              ZXIC_UINT32 fun_id,
-                              ZXIC_UINT32 bulk_id,
-                              DPP_HASH_DDR_RESC_CFG_T *p_ddr_resc_cfg,
-                              ZXIC_UINT32 zcell_num,
-                              ZXIC_UINT32 zreg_num)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 zblk_idx = 0;
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 ddr_item_num = 0;
-
-    D_NODE *p_zblk_dn = NULL;
-    D_NODE *p_zcell_dn = NULL;
-    ZXIC_RB_TN *p_rb_tn_new = NULL;
-    ZXIC_RB_TN *p_rb_tn_rtn = NULL;
-    SE_ZBLK_CFG *p_zblk_cfg = NULL;
-    SE_ZREG_CFG *p_zreg_cfg = NULL;
-    HASH_DDR_CFG *p_ddr_cfg = NULL;
-    HASH_DDR_CFG *p_rbkey_new = NULL;
-    HASH_DDR_CFG *p_rbkey_rtn = NULL;
-    SE_ZCELL_CFG *p_zcell_cfg = NULL;
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    FUNC_ID_INFO *p_func_info = NULL;
-    SE_ITEM_CFG **p_item_array = NULL;
-    DPP_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono = NULL;
-    /*    D_HEAD *p_zcell_free = NULL;*/
-    /*    D_HEAD *p_zblk_free = NULL;*/
-
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
-    ZXIC_COMM_CHECK_POINT(p_ddr_resc_cfg);
-    ZXIC_COMM_CHECK_INDEX(p_ddr_resc_cfg->ddr_crc_sel, 0, HASH_DDR_CRC_NUM - 1);
-    ZXIC_COMM_CHECK_INDEX(fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX);
-    ZXIC_COMM_CHECK_INDEX(bulk_id, HASH_BULK_ID_MIN, HASH_BULK_ID_MAX);
-    ZXIC_COMM_CHECK_INDEX(zcell_num, 0, SE_ZBLK_NUM * SE_ZCELL_NUM);
-    ZXIC_COMM_CHECK_INDEX(zreg_num, 0, SE_ZBLK_NUM * SE_ZREG_NUM);
-
-    dev_id = p_se_cfg->dev_id;
-
-    p_func_info = DPP_GET_FUN_INFO(p_se_cfg, fun_id);
-    p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
-    ZXIC_COMM_CHECK_POINT(p_hash_cfg);
-
-    ZXIC_COMM_TRACE_INFO("p_hash_cfg->ddr_valid = %d!\n", p_hash_cfg->ddr_valid);
-
-    if (1 == p_hash_cfg->ddr_valid)
-    {
-        /* [a long time ago] hash存储深度不能超过26bit，不然会导致硬件逻辑crc index不一致，微码查表不中 */
-        ZXIC_COMM_CHECK_DEV_INDEX(dev_id, p_ddr_resc_cfg->ddr_item_num, HASH_DDR_ITEM_MIN, HASH_DDR_ITEM_MAX);
-
-        ddr_item_num = p_ddr_resc_cfg->ddr_item_num;
-
-        if (DDR_WIDTH_512b == p_ddr_resc_cfg->ddr_width_mode)
-        {
-            ddr_item_num = p_ddr_resc_cfg->ddr_item_num >> 1;
-            ZXIC_COMM_CHECK_DEV_INDEX(dev_id, ddr_item_num, HASH_DDR_ITEM_MIN, HASH_DDR_ITEM_MAX);   /* 512bit存储时，hash存储深度不能少于14bit */
-        }
-
-        /** red&black key*/
-        p_rbkey_new = (HASH_DDR_CFG *)ZXIC_COMM_MALLOC(sizeof(HASH_DDR_CFG));
-        ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rbkey_new);
-        ZXIC_COMM_MEMSET(p_rbkey_new, 0, sizeof(HASH_DDR_CFG));
-
-        p_rbkey_new->ddr_baddr = p_ddr_resc_cfg->ddr_baddr;
-
-        /** red&black tree node*/
-        p_rb_tn_new = (ZXIC_RB_TN *)ZXIC_COMM_MALLOC(sizeof(ZXIC_RB_TN));
-        if (NULL == (p_rb_tn_new))
-        {
-            ZXIC_COMM_FREE(p_rbkey_new);
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);
-            return ZXIC_PAR_CHK_POINT_NULL;
-        }
-        INIT_RBT_TN(p_rb_tn_new, p_rbkey_new);
-
-        rc = zxic_comm_rb_insert(&p_hash_cfg->ddr_cfg_rb, (ZXIC_VOID *)p_rb_tn_new, (ZXIC_VOID *)(&p_rb_tn_rtn));
-        if (ZXIC_RBT_RC_FULL == rc)
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "The red black tree is full!\n");
-            ZXIC_COMM_FREE(p_rbkey_new);
-            ZXIC_COMM_FREE(p_rb_tn_new);
-            ZXIC_COMM_ASSERT(0);
-            return DPP_HASH_RC_RB_TREE_FULL;
-        }
-        else if (ZXIC_RBT_RC_UPDATE == rc)
-        {
-            ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "some bulk_id share one bulk!\n");
-
-            ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn);
-            p_rbkey_rtn = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key);
-            ZXIC_COMM_CHECK_DEV_INDEX(dev_id, p_rbkey_rtn->bulk_id, 0, HASH_BULK_NUM - 1);
-            p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id];  /* 已经初始化过的ddr_bulk_id属性 */
-
-            if (p_ddr_cfg->hash_ddr_arg != GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel) ||
-                p_ddr_cfg->width_mode   != p_ddr_resc_cfg->ddr_width_mode ||
-                p_ddr_cfg->ddr_ecc_en   != p_ddr_resc_cfg->ddr_ecc_en     ||
-                p_ddr_cfg->item_num     != ddr_item_num)
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "The base address is same but other ddr attribute is different\n");
-                ZXIC_COMM_FREE(p_rbkey_new);
-                ZXIC_COMM_FREE(p_rb_tn_new);
-                ZXIC_COMM_ASSERT(0);
-                return DPP_HASH_RC_INVALID_PARA;
-            }
-
-            p_hash_cfg->p_bulk_ddr_info[bulk_id] = p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id];
-
-            ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "bulk id init bulk_ddr_cfg ptr is:");
-
-            for (i = 0; i < HASH_BULK_NUM; i++)
-            {
-                ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "%p ", p_hash_cfg->p_bulk_ddr_info[i]);
-            }
-
-            ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "\n");
-
-            ZXIC_COMM_FREE(p_rbkey_new);
-            ZXIC_COMM_FREE(p_rb_tn_new);
-        }
-        else
-        {
-            p_item_array = (SE_ITEM_CFG **)ZXIC_COMM_MALLOC(ddr_item_num * sizeof(SE_ITEM_CFG *));
-            if (NULL == (p_item_array))
-            {
-                ZXIC_COMM_FREE(p_rbkey_new);
-                ZXIC_COMM_FREE(p_rb_tn_new);
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);
-                return ZXIC_PAR_CHK_POINT_NULL;
-            }
-            ZXIC_COMM_MEMSET(p_item_array, 0, ddr_item_num * sizeof(SE_ITEM_CFG *));
-
-            p_rbkey_new->p_item_array = p_item_array;
-            p_rbkey_new->bulk_id = bulk_id;
-            p_rbkey_new->hw_baddr = 0;
-            p_rbkey_new->width_mode = p_ddr_resc_cfg->ddr_width_mode;
-            p_rbkey_new->item_num = ddr_item_num;
-            p_rbkey_new->ddr_ecc_en = p_ddr_resc_cfg->ddr_ecc_en;
-            p_rbkey_new->hash_ddr_arg = GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel);
-            p_rbkey_new->bulk_use = 1;
-            p_rbkey_new->zcell_num = zcell_num;
-            p_rbkey_new->zreg_num = zreg_num;
-            p_hash_cfg->p_bulk_ddr_info[bulk_id] = p_rbkey_new;
-
-            ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "one new ddr_bulk init!\n");
-        }
-#ifdef DPP_FLOW_HW_INIT
-        rc = dpp_hash_tbl_crc_poly_write(p_hash_cfg->p_se_info, p_hash_cfg->fun_id, bulk_id, p_ddr_resc_cfg->ddr_crc_sel);
-        if (DPP_OK != rc)
-        {
-            ZXIC_COMM_FREE(p_rbkey_new);
-            ZXIC_COMM_FREE(p_rb_tn_new);
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_hash_tbl_crc_poly_write");
-            return rc;
-        }
-
-        rc = dpp_hash_ext_cfg_write(p_hash_cfg->p_se_info, p_hash_cfg->fun_id, bulk_id, p_hash_cfg->p_bulk_ddr_info[bulk_id]);
-        if (DPP_OK != rc)
-        {
-            ZXIC_COMM_FREE(p_rbkey_new);
-            ZXIC_COMM_FREE(p_rb_tn_new);
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_hash_ext_cfg_write");
-            return rc;
-        }
-        rc = dpp_hash_tbl_depth_write(p_hash_cfg->p_se_info,
-                                      p_hash_cfg->fun_id,
-                                      bulk_id,
-                                      p_hash_cfg->p_bulk_ddr_info[bulk_id]);
-        if (DPP_OK != rc)
-        {
-            ZXIC_COMM_FREE(p_rbkey_new);
-            ZXIC_COMM_FREE(p_rb_tn_new);
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_hash_tbl_depth_write");
-            return rc;
-        }
-#endif
-        rc = dpp_se_smmu1_hash_tbl_cfg_set(p_se_cfg->dev, p_hash_cfg->fun_id, bulk_id, p_ddr_resc_cfg->ddr_ecc_en, p_ddr_resc_cfg->ddr_baddr);
-        if (DPP_OK != rc)
-        {
-            ZXIC_COMM_FREE(p_rbkey_new);
-            ZXIC_COMM_FREE(p_rb_tn_new);
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_se_smmu1_hash_tbl_cfg_set");
-            return rc;
-        }
-
-    }
-
-    p_bulk_zcam_mono = (DPP_HASH_BULK_ZCAM_STAT *)ZXIC_COMM_MALLOC(sizeof(DPP_HASH_BULK_ZCAM_STAT));
-    if (NULL == (p_bulk_zcam_mono))
-    {
-        ZXIC_COMM_FREE(p_rbkey_new);
-        ZXIC_COMM_FREE(p_rb_tn_new);
-        ZXIC_COMM_FREE(p_item_array);
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);
-        return ZXIC_PAR_CHK_POINT_NULL;
-    }
-    ZXIC_COMM_MEMSET(p_bulk_zcam_mono, 0, sizeof(DPP_HASH_BULK_ZCAM_STAT));
-    (&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[bulk_id] = p_bulk_zcam_mono;
-
-    for (i = 0; i < SE_ZBLK_NUM * SE_ZCELL_NUM; i++)
-    {
-        p_bulk_zcam_mono->zcell_mono_idx[i] = 0xffffffff;
-    }
-
-    for (i = 0; i < SE_ZBLK_NUM; i++)
-    {
-        for (j = 0; j < SE_ZREG_NUM; j++)
-        {
-            p_bulk_zcam_mono->zreg_mono_id[i][j].zblk_id = 0xffffffff;
-            p_bulk_zcam_mono->zreg_mono_id[i][j].zreg_id = 0xffffffff;
-        }
-    }
-
-    if (zcell_num > 0)
-    {
-        p_hash_cfg->bulk_ram_mono[bulk_id] = 1;
-
-#ifdef DPP_FLOW_HW_INIT
-        rc = dpp_hash_bulk_mono_flags_write(p_se_cfg, fun_id, bulk_id);
-        if (DPP_OK != rc)
-        {
-            ZXIC_COMM_FREE(p_rbkey_new);
-            ZXIC_COMM_FREE(p_rb_tn_new);
-            ZXIC_COMM_FREE(p_item_array);
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_hash_bulk_mono_flags_write");
-            return rc;
-        }
-#endif
-
-        /* 初始分配此业务表独占的zcell，只能在非独占的zcell中分配 */
-        /* p_zcell_free = &(p_hash_cfg->hash_shareram.zcell_free_list);*/
-        p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next;
-
-        i = 0;
-
-        while (p_zcell_dn)
-        {
-            p_zcell_cfg = (SE_ZCELL_CFG *)p_zcell_dn->data;
-
-            if (p_zcell_cfg->is_used)
-            {
-                if (!(p_zcell_cfg->flag & DPP_ZCELL_FLAG_IS_MONO))
-                {
-                    p_zcell_cfg->flag     |= DPP_ZCELL_FLAG_IS_MONO;
-                    p_zcell_cfg->bulk_id = bulk_id;
-
-#ifdef DPP_FLOW_HW_INIT
-                    rc = dpp_hash_zcell_mono_write(p_se_cfg, p_zcell_cfg);   /* 写入硬件 */
-                    if (DPP_OK != rc)
-                    {
-                        ZXIC_COMM_FREE(p_rbkey_new);
-                        ZXIC_COMM_FREE(p_rb_tn_new);
-                        ZXIC_COMM_FREE(p_item_array);
-                        ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_hash_zcell_mono_write");
-                        return rc;
-                    }
-#endif
-
-                    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, p_zcell_cfg->zcell_idx, 0, SE_ZCELL_TOTAL_NUM - 1);
-                    p_bulk_zcam_mono->zcell_mono_idx[p_zcell_cfg->zcell_idx] = p_zcell_cfg->zcell_idx;  /* 统计独占的zcell */
-
-                    if (++i >= zcell_num)
-                    {
-                        break;
-                    }
-                }
-            }
-            else
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "zcell[ %d ] is not init before used!\n", p_zcell_cfg->zcell_idx);
-                ZXIC_COMM_ASSERT(0);
-                return DPP_HASH_RC_INVALID_PARA;
-            }
-
-            p_zcell_dn = p_zcell_dn->next;
-        }
-
-        if (i < zcell_num)
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Input param 'zcell_num' is [ %d ], actually bulk[ %d ]monopolize zcells is [ %d ]!\n", zcell_num, bulk_id, i);
-        }
-    }
-
-    if (zreg_num > 0)
-    {
-        p_hash_cfg->bulk_ram_mono[bulk_id] = 1;
-
-#ifdef DPP_FLOW_HW_INIT
-        rc = dpp_hash_bulk_mono_flags_write(p_se_cfg, fun_id, bulk_id);
-        if (DPP_OK != rc)
-        {
-            ZXIC_COMM_FREE(p_rbkey_new);
-            ZXIC_COMM_FREE(p_rb_tn_new);
-            ZXIC_COMM_FREE(p_item_array);
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_hash_bulk_mono_flags_write");
-            return rc;
-        }
-#endif
-        /*        p_tbl_id_info->zreg_num= zreg_num;*/
-
-        /* 初始分配此业务表独占的zreg，只能在非独占的zreg中分配 */
-        /*        p_zblk_free = &(p_hash_cfg->hash_shareram.zblk_list);*/
-        p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next;
-        j = 0;
-
-        while (p_zblk_dn)
-        {
-            p_zblk_cfg = (SE_ZBLK_CFG *)p_zblk_dn->data;
-            zblk_idx = p_zblk_cfg->zblk_idx;
-            ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zblk_idx, 0, SE_ZBLK_NUM - 1);
-
-            if (p_zblk_cfg->is_used)
-            {
-                for (i = 0; i < SE_ZREG_NUM; i++)
-                {
-                    p_zreg_cfg = &(p_zblk_cfg->zreg_info[i]);
-
-                    if (!(p_zreg_cfg->flag & DPP_ZREG_FLAG_IS_MONO))
-                    {
-                        p_zreg_cfg->flag = DPP_ZREG_FLAG_IS_MONO;
-                        p_zreg_cfg->bulk_id = bulk_id;
-#ifdef DPP_FLOW_HW_INIT
-                        rc = dpp_hash_zreg_mono_write(p_se_cfg, bulk_id, zblk_idx, i); /* 写入硬件 */
-                        if (DPP_OK != rc)
-                        {
-                            ZXIC_COMM_FREE(p_rbkey_new);
-                            ZXIC_COMM_FREE(p_rb_tn_new);
-                            ZXIC_COMM_FREE(p_item_array);
-                            ZXIC_COMM_TRACE_DEV_ERROR(dev_id,"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",__FILE__,__LINE__,rc,__FUNCTION__,"dpp_hash_zreg_mono_write");
-                            return rc;
-                        }
-#endif
-                        p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zblk_id = zblk_idx;
-                        p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zreg_id = i;
-
-                        if (++j >= zreg_num)
-                        {
-                            break;
-                        }
-                    }
-                }
-
-                if (j >= zreg_num)
-                {
-                    break;
-                }
-            }
-            else
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "zblk [ %d ] is not init before used!\n", p_zblk_cfg->zblk_idx);
-                ZXIC_COMM_ASSERT(0);
-                return DPP_HASH_RC_INVALID_PARA;
-            }
-
-            p_zblk_dn = p_zblk_dn->next;
-        }
-
-        if (j < zreg_num)
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Input param 'zreg_num' is [ %d ], actually bulk[ %d ]monopolize zregs is [ %d ]!\n", zreg_num, bulk_id, j);
-        }
-    }
-
-    /** for 软复位 */
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(fun_id, 0, 3);
-    ZXIC_COMM_CHECK_INDEX(bulk_id, 0, 7);
-    g_hash_store_dat[dev_id].ddr_item_num[fun_id][bulk_id] = p_ddr_resc_cfg->ddr_item_num;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 初始化单个hash引擎内的某个业务表，此接口支持为该业务表分配独占的zcell。
-*   必须先初始化hash引擎，如果是片内+片外模式还必须先初始化dpp_hash_ddr_bulk_init，
-*   再初始化业务表。
-* @param   p_se_cfg        算法模块公共管理数据结构指针
-* @param   fun_id          hash引擎号
-* @param   tbl_id          业务表
-* @param   tbl_flag        初始化标记, bitmap的形式使用，如:HASH_TBL_FLAG_AGE等
-* @param   key_type        hash条目类型，取值参照DPP_HASH_KEY_TYPE的定义
-* @param   actu_key_size   业务键值有效长度: 8bit*N，N=1~48
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wcl      @date  2015/05/15
-************************************************************/
-DPP_STATUS dpp_hash_tbl_id_info_init(DPP_SE_CFG *p_se_cfg,
-                                     ZXIC_UINT32 fun_id,
-                                     ZXIC_UINT32 tbl_id,
-                                     ZXIC_UINT32 tbl_flag,
-                                     ZXIC_UINT32 key_type,
-                                     ZXIC_UINT32 actu_key_size)
-{
-    ZXIC_UINT32 key_by_size = 0;
-    ZXIC_UINT32 entry_size = 0;
-
-    ZXIC_UINT32 dev_id = 0;
-
-    DPP_HASH_TBL_ID_INFO *p_tbl_id_info = NULL;
-
-    ZXIC_COMM_CHECK_INDEX(tbl_id, 0, HASH_TBL_ID_NUM - 1);
-    ZXIC_COMM_CHECK_INDEX(fun_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1);
-    ZXIC_COMM_CHECK_INDEX(actu_key_size, HASH_ACTU_KEY_MIN, HASH_ACTU_KEY_MAX);
-    ZXIC_COMM_CHECK_INDEX(key_type, HASH_KEY_128b, HASH_KEY_512b);
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
-
-    dev_id = p_se_cfg->dev_id;
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1);
-    key_by_size = DPP_GET_KEY_SIZE(actu_key_size);
-    entry_size = DPP_GET_HASH_ENTRY_SIZE(key_type);
-
-    if (key_by_size > entry_size)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrorCode[%x]: actu_key_size[%d] not match to key_type[%d].\n",
-                                 DPP_HASH_RC_INVALID_PARA,
-                                 key_by_size,
-                                 entry_size);
-        ZXIC_COMM_ASSERT(0);
-        return DPP_HASH_RC_INVALID_PARA;
-    }
-
-    p_tbl_id_info = GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id);
-
-    if (p_tbl_id_info->is_init)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "fun_id[%d],table_id[%d] is already init, do not init again!\n", fun_id, tbl_id);
-        return DPP_HASH_RC_REPEAT_INIT;
-    }
-
-    p_tbl_id_info->fun_id = fun_id;
-    p_tbl_id_info->actu_key_size = actu_key_size;
-    p_tbl_id_info->key_type = key_type;
-    p_tbl_id_info->is_init = 1;
-
-    if (tbl_flag & HASH_TBL_FLAG_AGE)
-    {
-        p_tbl_id_info->is_age = 1;
-    }
-
-    if (tbl_flag & HASH_TBL_FLAG_LEARN)
-    {
-        p_tbl_id_info->is_lrn = 1;
-    }
-
-    if (tbl_flag & HASH_TBL_FLAG_MC_WRT)
-    {
-        p_tbl_id_info->is_mc_wrt = 1;
-    }
-
-    return DPP_OK;
-}
-
-DPP_STATUS dpp_hash_red_black_node_alloc(DPP_DEV_T *dev,ZXIC_RB_TN **p_rb_tn_new,DPP_HASH_RBKEY_INFO **p_rbkey_new)
-{
-    ZXIC_RB_TN *p_rb_tn_new_temp = NULL;
-    DPP_HASH_RBKEY_INFO *p_rbkey_new_temp = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    /** red&black key*/
-    p_rbkey_new_temp = (DPP_HASH_RBKEY_INFO *)ZXIC_COMM_MALLOC(sizeof(DPP_HASH_RBKEY_INFO));
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_rbkey_new_temp);
-    ZXIC_COMM_MEMSET(p_rbkey_new_temp, 0, sizeof(DPP_HASH_RBKEY_INFO));
-    
-    /** red&black tree node*/
-    p_rb_tn_new_temp = (ZXIC_RB_TN *)ZXIC_COMM_MALLOC(sizeof(ZXIC_RB_TN));
-    if (NULL == p_rb_tn_new_temp)
-    {
-        ZXIC_COMM_FREE(p_rbkey_new_temp);
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",__FILE__,__LINE__,__FUNCTION__);
-        return ZXIC_PAR_CHK_POINT_NULL;
-    }
-
-    INIT_RBT_TN(p_rb_tn_new_temp, p_rbkey_new_temp);
-
-    *p_rb_tn_new = p_rb_tn_new_temp;
-    *p_rbkey_new = p_rbkey_new_temp;
-
-    return DPP_OK;
-}
-
-DPP_STATUS dpp_hash_get_hash_info_from_sdt(ZXIC_UINT32 dev_id, ZXIC_UINT32 sdt_no, HASH_ENTRY_CFG *p_hash_entry_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-    FUNC_ID_INFO *p_func_info = NULL;
-    DPP_SE_CFG *p_se_cfg = NULL;
-
-    DPP_SDTTBL_HASH_T sdt_hash_info = {0};  /*SDT内容*/
-    
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_hash_entry_cfg);
-
-    //从sdt_no中获取SDT配置
-    rc = dpp_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash_info);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_read");
-
-    p_hash_entry_cfg->fun_id   = sdt_hash_info.hash_id; /*hash引擎*/
-    ZXIC_COMM_CHECK_INDEX(p_hash_entry_cfg->fun_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1);
-
-    p_hash_entry_cfg->table_id = sdt_hash_info.hash_table_id; /*hash表号*/
-    ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->table_id,HASH_TBL_ID_NUM - 1);
-
-    p_hash_entry_cfg->bulk_id = ((p_hash_entry_cfg->table_id >> 2) & 0x7);
-    ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->bulk_id,HASH_BULK_NUM - 1);
-
-    p_hash_entry_cfg->key_type = sdt_hash_info.hash_table_width; /*表宽度*/
-    ZXIC_COMM_CHECK_INDEX(p_hash_entry_cfg->key_type, HASH_KEY_128b, HASH_KEY_512b);
-
-    p_hash_entry_cfg->actu_key_size = sdt_hash_info.key_size; /*业务表键值长度*/
-    ZXIC_COMM_CHECK_INDEX(p_hash_entry_cfg->actu_key_size, HASH_ACTU_KEY_MIN, HASH_ACTU_KEY_MAX);
-    p_hash_entry_cfg->key_by_size = DPP_GET_KEY_SIZE(p_hash_entry_cfg->actu_key_size);
-    p_hash_entry_cfg->rst_by_size = DPP_GET_RST_SIZE(p_hash_entry_cfg->key_type, p_hash_entry_cfg->actu_key_size);
-
-     /* 取出se配置 */
-    rc = dpp_se_cfg_get(dev_id, &p_se_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_cfg_get");
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg);
-    p_hash_entry_cfg->p_se_cfg = p_se_cfg;
-
-    p_func_info = DPP_GET_FUN_INFO(p_se_cfg, p_hash_entry_cfg->fun_id);
-    DPP_SE_CHECK_FUN(p_func_info, p_hash_entry_cfg->fun_id, FUN_HASH);
-
-    p_hash_entry_cfg->p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_hash_entry_cfg->p_hash_cfg);
-    
-    return DPP_OK;
-}
-
-DPP_STATUS dpp_hash_rb_insert(DPP_DEV_T *dev,HASH_ENTRY_CFG *p_hash_entry_cfg,DPP_HASH_ENTRY *p_entry)
-{
-    ZXIC_UINT32         rc              = DPP_OK;
-    DPP_HASH_RBKEY_INFO *p_rbkey_rtn    = NULL;
-    DPP_HASH_CFG        *p_hash_cfg     = NULL;
-    DPP_HASH_RBKEY_INFO *p_rbkey_new    = NULL;
-    ZXIC_RB_TN          *p_rb_tn_new    = NULL;
-    ZXIC_RB_TN          *p_rb_tn_rtn    = NULL;
-    ZXIC_UINT32         rst_actual_size = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg->p_hash_cfg);
-    ZXIC_COMM_CHECK_POINT(p_entry);
-    ZXIC_COMM_CHECK_POINT(p_entry->p_rst);
-
-    p_rbkey_new = p_hash_entry_cfg->p_rbkey_new;
-    p_rb_tn_new = p_hash_entry_cfg->p_rb_tn_new;
-    p_hash_cfg = p_hash_entry_cfg->p_hash_cfg;
-    rst_actual_size = ((p_hash_entry_cfg->rst_by_size) > HASH_RST_MAX) ? HASH_RST_MAX : p_hash_entry_cfg->rst_by_size;
-    rc = zxic_comm_rb_insert(&p_hash_cfg->hash_rb, (ZXIC_VOID *)p_rb_tn_new, (ZXIC_VOID *)(&p_rb_tn_rtn));
-    if (ZXIC_RBT_RC_FULL == rc)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "The red black tree is full!\n");
-        ZXIC_COMM_FREE(p_rbkey_new);
-        ZXIC_COMM_FREE(p_rb_tn_new);
-        ZXIC_COMM_ASSERT(0);
-        return DPP_HASH_RC_RB_TREE_FULL;
-    }
-    else if (ZXIC_RBT_RC_UPDATE == rc)
-    {
-        p_hash_cfg->hash_stat.insert_same++;
-        ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "Hash update exist entry!\n");
-
-        ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_rb_tn_rtn);
-        p_rbkey_rtn = (DPP_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key);
-
-        /* when the result is more than 256bit, get first 256bit valid data. */
-        ZXIC_COMM_MEMCPY(p_rbkey_rtn->rst, p_entry->p_rst, rst_actual_size);
-
-        ZXIC_COMM_FREE(p_rbkey_new);
-        ZXIC_COMM_FREE(p_rb_tn_new);
-        p_hash_entry_cfg->p_rbkey_new = p_rbkey_rtn;
-        p_hash_entry_cfg->p_rb_tn_new = p_rb_tn_rtn;
-
-        /* 仿真器使用 */
-        if(DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev)))
-        {
-            /*dpp_se_simulator_insert_delete_hash(DEV_ID(dev), 
-                                                p_hash_entry_cfg->fun_id, 
-                                                p_hash_entry_cfg->table_id, 
-                                                p_hash_entry_cfg->key_by_size, 
-                                                p_hash_entry_cfg->rst_by_size, 
-                                                0, 
-                                                p_entry);*/
-        }
-
-        return DPP_HASH_RC_ADD_UPDATE;
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "Hash insert new entry!\n");
-        /* 仿真器使用 */
-        if(DPP_DEV_TYPE_SIM == dpp_dev_get_dev_type(DEV_ID(dev)))
-        {
-            /*dpp_se_simulator_insert_delete_hash(DEV_ID(dev), 
-                                                p_hash_entry_cfg->fun_id, 
-                                                p_hash_entry_cfg->table_id, 
-                                                p_hash_entry_cfg->key_by_size, 
-                                                p_hash_entry_cfg->rst_by_size, 
-                                                0, 
-                                                p_entry);*/
-        }
-
-        /* when the result is more than 256bit, get first 256bit valid data. */
-        ZXIC_COMM_MEMCPY(p_rbkey_new->rst, p_entry->p_rst, rst_actual_size);
-        p_rbkey_new->entry_size = DPP_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type);
-        INIT_D_NODE(&p_rbkey_new->entry_dn, p_rbkey_new);
-    }
-
-    return DPP_OK;
-}
-
-DPP_STATUS dpp_hash_set_crc_key(DPP_DEV_T *dev,HASH_ENTRY_CFG *p_hash_entry_cfg,DPP_HASH_ENTRY *p_entry,ZXIC_UINT8 *p_temp_key)
-{
-    ZXIC_UINT32 key_by_size = 0;    
-    ZXIC_UINT8 temp_tbl_id  = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
-    ZXIC_COMM_CHECK_POINT(p_entry);
-    ZXIC_COMM_CHECK_POINT(p_entry->p_key);
-    ZXIC_COMM_CHECK_POINT(p_temp_key);
-
-    key_by_size = p_hash_entry_cfg->key_by_size;
-    ZXIC_COMM_MEMCPY(p_temp_key, p_entry->p_key, key_by_size);
-
-    /* 约定: 参与CRC运算的key, 需要将tbl_id的前面补3bit的0，然后放到actu_key的后面. */
-    temp_tbl_id = (*p_temp_key) & 0x1F;
-    memmove(p_temp_key, p_temp_key+1, key_by_size - HASH_KEY_CTR_SIZE);
-    ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(DEV_ID(dev), key_by_size, HASH_KEY_CTR_SIZE);
-    p_temp_key[key_by_size - HASH_KEY_CTR_SIZE] = temp_tbl_id;
-
-    return DPP_OK;
-}
-
-DPP_STATUS dpp_hash_insert_ddr(DPP_DEV_T *dev,HASH_ENTRY_CFG *p_hash_entry_cfg,ZXIC_UINT8 *p_temp_key,ZXIC_UINT8 *p_end_flag)
-{
-    DPP_HASH_CFG        *p_hash_cfg   = NULL;
-    ZXIC_UINT8           bulk_id      = 0;
-    ZXIC_UINT8           key_type     = 0;
-    ZXIC_UINT8           table_id     = 0;
-    ZXIC_UINT32          key_by_size  = 0;
-    ZXIC_UINT32          crc_value    = 0;
-    ZXIC_UINT32          item_idx     = 0xFFFFFFFF;/* -1 */
-    ZXIC_UINT32          item_type    = 0;
-    HASH_DDR_CFG         *p_ddr_cfg   = NULL;
-    SE_ITEM_CFG          *p_item      = NULL;
-    DPP_HASH_RBKEY_INFO  *p_rbkey_new = NULL;
-    ZXIC_UINT32          rc           = DPP_OK;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
-    ZXIC_COMM_CHECK_POINT(p_temp_key);
-    ZXIC_COMM_CHECK_POINT(p_end_flag);
-
-    p_hash_cfg = p_hash_entry_cfg->p_hash_cfg;
-    ZXIC_COMM_CHECK_POINT(p_hash_cfg);
-    bulk_id = p_hash_entry_cfg->bulk_id;
-    ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id,HASH_BULK_NUM - 1);
-    p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id];
-    ZXIC_COMM_CHECK_POINT(p_ddr_cfg);
-    table_id = p_hash_entry_cfg->table_id;
-    ZXIC_COMM_CHECK_INDEX_UPPER(table_id,HASH_TBL_ID_NUM - 1);
-    p_rbkey_new = p_hash_entry_cfg->p_rbkey_new;
-    ZXIC_COMM_CHECK_POINT(p_rbkey_new);
-
-    key_type = p_hash_entry_cfg->key_type;
-    if ((HASH_KEY_512b == key_type) && (DDR_WIDTH_256b == p_ddr_cfg->width_mode))
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "ErrorCode[0x%x]: Hash DDR width mode is not match to the key type.\n", DPP_HASH_RC_DDR_WIDTH_MODE_ERR);
-        return DPP_HASH_RC_DDR_WIDTH_MODE_ERR;
-    }
-    
-    key_by_size = p_hash_entry_cfg->key_by_size;
-    crc_value = p_hash_cfg->p_hash32_fun(p_temp_key, key_by_size, p_ddr_cfg->hash_ddr_arg);
-    ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "hash ddr arg is: 0x%x.crc_value is 0x%x\n", p_ddr_cfg->hash_ddr_arg, crc_value); /* t */
-    item_idx = crc_value % p_ddr_cfg->item_num; /*按照256bit进行划分*/
-    item_type = ITEM_DDR_256;
-    if (DDR_WIDTH_512b == p_ddr_cfg->width_mode)
-    {
-        item_idx = crc_value % p_ddr_cfg->item_num;/* 512b模式时，item_num已经在bulk初始化做过转换 ，按照512bit进行划分*/
-        item_type = ITEM_DDR_512;
-    }
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "Hash insert in ITEM_DDR_%s, item_idx is: 0x%x.\n", ((item_type == ITEM_DDR_256) ? "256" : "512"), item_idx);
-
-    ZXIC_COMM_CHECK_INDEX_UPPER(item_idx, p_ddr_cfg->item_num);    /* modify coverity yinxh 2021.03.10*/
-    p_item = p_ddr_cfg->p_item_array[item_idx];
-    if (NULL == p_item)
-    {
-        p_item = (SE_ITEM_CFG *)ZXIC_COMM_MALLOC(sizeof(SE_ITEM_CFG));
-        ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_item);
-        ZXIC_COMM_MEMSET(p_item, 0, sizeof(SE_ITEM_CFG));
-        p_ddr_cfg->p_item_array[item_idx] = p_item;
-    }
-
-    rc = dpp_hash_insrt_to_item(p_hash_cfg,
-                                    p_hash_entry_cfg->p_rbkey_new,
-                                    p_item,
-                                    item_idx,
-                                    item_type,
-                                    key_type);
-
-    if (DPP_HASH_RC_ITEM_FULL != rc)
-    {
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_insrt_to_item");
-        *p_end_flag = 1;
-#ifdef HASH_ENTRY_STAT
-        p_hash_cfg->hash_stat.insert_ddr++;
-        p_hash_cfg->hash_stat.insert_table[table_id].ddr++;
-#endif
-        /* calc the item hardware address in DDR */
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), p_ddr_cfg->hw_baddr, item_idx);
-        p_item->hw_addr = GET_HASH_DDR_HW_ADDR(p_ddr_cfg->hw_baddr, item_idx);
-        p_item->bulk_id = p_hash_entry_cfg->bulk_id;
-    }
-
-#if OBTAIN_CONFLICT_KEY
-    /* debug start 获取冲突键值*/
-    if (DPP_HASH_RC_ITEM_FULL == rc)
-    {
-        p_item->hw_addr = GET_HASH_DDR_HW_ADDR(p_ddr_cfg->hw_baddr, item_idx);
-        ZXIC_COMM_PRINT("ddr conflict item_idx is:0x%x,p_item->hw_addr is:0x%x\n", item_idx, p_item->hw_addr);
-        ZXIC_COMM_PRINT("ddr conflict key is:");
-
-        for (index = 0; index < 10; index++)
-        {
-            ZXIC_COMM_PRINT("0x%02x ", p_rbkey_new->key[index]);
-        }
-
-        ZXIC_COMM_PRINT("\n");
-    }
-
-    /*        debug end*/
-#endif
-
-    return DPP_OK;
-}
-
-DPP_STATUS dpp_hash_insert_zcell(DPP_DEV_T *dev,DPP_SE_CFG *p_se_cfg,HASH_ENTRY_CFG *p_hash_entry_cfg,ZXIC_UINT8 *p_temp_key,ZXIC_UINT8 *p_end_flag)
-{
-    ZXIC_UINT8   bulk_id      = 0;
-    D_NODE       *p_zcell_dn  = NULL;
-    SE_ZCELL_CFG *p_zcell     = NULL;
-    ZXIC_UINT32  zblk_idx     = 0;
-    ZXIC_UINT32  zcell_id     = 0;
-    ZXIC_UINT32  pre_zblk_idx = 0xFFFFFFFF;/* -1; */
-    SE_ITEM_CFG *p_item       = NULL;
-    ZXIC_UINT32  item_idx     = 0xFFFFFFFF;/* -1 */
-    ZXIC_UINT32  item_type    = 0;
-    ZXIC_UINT32  rc           = DPP_OK;
-    ZXIC_UINT32  crc_value    = 0;
-    ZXIC_UINT8   table_id     = 0;
-    DPP_HASH_CFG *p_hash_cfg  = NULL;
-    SE_ZBLK_CFG  *p_zblk      = NULL;
-    
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
-    ZXIC_COMM_CHECK_POINT(p_temp_key);
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
-    ZXIC_COMM_CHECK_POINT(p_end_flag);
-
-    /* if insert into DDR is fail, insert into ZCAM. */
-    ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "insert zcell start\n");  
-    bulk_id = p_hash_entry_cfg->bulk_id;
-    ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id,HASH_BULK_NUM - 1);
-    table_id = p_hash_entry_cfg->table_id;
-    ZXIC_COMM_CHECK_INDEX_UPPER(table_id,HASH_TBL_ID_NUM - 1);
-    p_hash_cfg = p_hash_entry_cfg->p_hash_cfg;
-    ZXIC_COMM_CHECK_POINT(p_hash_cfg);
-    p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next;
-    
-    while (p_zcell_dn)
-    {
-        p_zcell = (SE_ZCELL_CFG *)p_zcell_dn->data;
-        ZXIC_COMM_CHECK_POINT(p_zcell);
-
-        /* 只在hash引擎开启zcell独占模式下，才进行相关的处理 */
-        if (((p_zcell->flag & DPP_ZCELL_FLAG_IS_MONO) && (p_zcell->bulk_id != bulk_id)) 
-             ||((!(p_zcell->flag & DPP_ZCELL_FLAG_IS_MONO)) && (p_hash_cfg->bulk_ram_mono[bulk_id])))
-        {
-            p_zcell_dn = p_zcell_dn->next;
-            continue;
-        }
-
-        zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx);
-        ZXIC_COMM_CHECK_INDEX_UPPER(zblk_idx,SE_ZBLK_NUM - 1);
-        p_zblk = &(p_se_cfg->zblk_info[zblk_idx]);
-        if (zblk_idx != pre_zblk_idx)
-        {
-            pre_zblk_idx = zblk_idx;
-            crc_value = p_hash_cfg->p_hash16_fun(p_temp_key, p_hash_entry_cfg->key_by_size, p_zblk->hash_arg);
-        }
-
-        ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "zblk_idx is [0x%x],p_zblk->hash_arg is [0x%x],crc_value is [0x%x]\n", zblk_idx, p_zblk->hash_arg, crc_value); /* t */
-
-        zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx);
-        item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc_value);
-        ZXIC_COMM_CHECK_INDEX_UPPER(item_idx,SE_RAM_DEPTH - 1);
-        p_item = &(p_zcell->item_info[item_idx]);
-        item_type = ITEM_RAM;
-
-        ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "zcell_id is [0x%x],item_idx is [0x%x]\n", zcell_id, item_idx); /* t */
-
-        rc = dpp_hash_insrt_to_item(p_hash_cfg,
-                                        p_hash_entry_cfg->p_rbkey_new,
-                                        p_item,
-                                        item_idx,
-                                        item_type,
-                                        p_hash_entry_cfg->key_type);
-
-        if (DPP_HASH_RC_ITEM_FULL == rc)
-        {
-            ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "The item is full, check next. \n");
-#if OBTAIN_CONFLICT_KEY
-
-            /*                debug start 获取冲突键值*/
-            if (DPP_HASH_RC_ITEM_FULL == rc)
-            {
-                p_item->hw_addr = ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx);
-                ZXIC_COMM_PRINT("zcell conflict item_idx is:0x%x,p_item->hw_addr is:0x%x\n", item_idx, p_item->hw_addr);
-                ZXIC_COMM_PRINT("zcell conflict key is:");
-
-                for (index = 0; index < 10; index++)
-                {
-                    ZXIC_COMM_PRINT("0x%x ", p_rbkey_new->key[index]);
-                }
-
-                ZXIC_COMM_PRINT("\n");
-            }
-
-            /*                debug end*/
-#endif
-        }
-        else
-        {
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_insrt_to_item");
-            *p_end_flag = 1;
-#ifdef HASH_ENTRY_STAT
-            p_hash_cfg->hash_stat.insert_zcell++;
-            p_hash_cfg->hash_stat.insert_table[table_id].zcell++;
-#endif
-
-            /* calc the item hardware address in ZCAM. */
-            p_item->hw_addr = ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx);
-            /*                debug start 获取冲突键值*/
-            /*                ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "ZCAM hw_addr is [0x%x]\n", p_item->hw_addr); t*/
-            /*                ZXIC_COMM_PRINT("after ddr conflict item_idx is:%d,p_item->hw_addr is:%d \n", item_idx, p_item->hw_addr);*/
-            /*                ZXIC_COMM_PRINT("after ddr conflict zcell_id is [0x%x],zblk_idx is [0x%x]\n", zcell_id, zblk_idx); t;*/
-            /*                debug end*/
-            break;
-        }
-
-        p_zcell_dn = p_zcell_dn->next;
-    }
-    
-    return DPP_OK;
-}
-
-DPP_STATUS dpp_hash_insert_zreg(DPP_DEV_T *dev,HASH_ENTRY_CFG *p_hash_entry_cfg,ZXIC_UINT8 *p_temp_key,ZXIC_UINT8 *p_end_flag)
-{
-    DPP_HASH_CFG *p_hash_cfg  = NULL;
-    D_NODE       *p_zblk_dn   = NULL;
-    SE_ZBLK_CFG  *p_zblk      = NULL;
-    SE_ZREG_CFG  *p_zreg      = NULL;
-    SE_ITEM_CFG  *p_item      = NULL;
-    ZXIC_UINT8   reg_index    = 0;
-    ZXIC_UINT32  zblk_idx     = 0;
-    ZXIC_UINT32  rc           = DPP_OK;
-    ZXIC_UINT8   bulk_id      = 0;
-    ZXIC_UINT32  item_idx     = 0xFFFFFFFF;/* -1; */
-    ZXIC_UINT32  item_type    = 0;
-    ZXIC_UINT32  table_id     = 0;
-    DPP_HASH_RBKEY_INFO *p_rbkey_new = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
-    ZXIC_COMM_CHECK_POINT(p_temp_key);
-    ZXIC_COMM_CHECK_POINT(p_end_flag);
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "insert zreg start\n");  /* t */
-    bulk_id = p_hash_entry_cfg->bulk_id;
-    ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id,HASH_BULK_NUM - 1);
-    table_id = p_hash_entry_cfg->table_id;
-    ZXIC_COMM_CHECK_INDEX_UPPER(table_id,HASH_TBL_ID_NUM - 1);
-    p_rbkey_new = p_hash_entry_cfg->p_rbkey_new;
-    ZXIC_COMM_CHECK_POINT(p_rbkey_new);
-
-    p_hash_cfg = p_hash_entry_cfg->p_hash_cfg;
-    p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next;
-    while (p_zblk_dn)
-    {
-        p_zblk = (SE_ZBLK_CFG *)p_zblk_dn->data;
-        zblk_idx = p_zblk->zblk_idx;
-
-        for (reg_index = 0; reg_index < SE_ZREG_NUM; reg_index++)
-        {
-            p_zreg = &(p_zblk->zreg_info[reg_index]);
-
-            if (((p_zreg->flag & DPP_ZREG_FLAG_IS_MONO) && (p_zreg->bulk_id != bulk_id)) ||
-                ((!(p_zreg->flag & DPP_ZREG_FLAG_IS_MONO)) && (p_hash_cfg->bulk_ram_mono[bulk_id])))
-            {
-                continue;
-            }
-
-            p_item = &(p_zblk->zreg_info[reg_index].item_info);
-            item_type = ITEM_REG;
-            item_idx = reg_index;
-            rc = dpp_hash_insrt_to_item(p_hash_cfg,
-                                        p_hash_entry_cfg->p_rbkey_new,
-                                        p_item,
-                                        item_idx,
-                                        item_type,
-                                        p_hash_entry_cfg->key_type);
-
-            if (DPP_HASH_RC_ITEM_FULL == rc)
-            {
-                ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "The item is full, check next. \n");
-#if OBTAIN_CONFLICT_KEY
-                /*                    debug start 获取冲突键值*/
-                ZXIC_COMM_PRINT("zreg_mono conflict,not inserted,reg_num is:0x%x,zblk_idx is:0x%x,p_item->hw_addr is:0x%x\n", reg_index, zblk_idx, p_item->hw_addr);
-                ZXIC_COMM_PRINT("zreg_mono conflict,key is:");
-
-                for (index = 0; index < 8; index++)
-                {
-                    ZXIC_COMM_PRINT("0x%x ", p_rbkey_new->key[index]);
-                }
-
-                ZXIC_COMM_PRINT("\n");
-                /*                    debug end*/
-#endif
-            }
-            else
-            {
-                ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_insrt_to_item");
-                *p_end_flag = 1;
-#ifdef HASH_ENTRY_STAT
-                p_hash_cfg->hash_stat.insert_zreg++;
-                p_hash_cfg->hash_stat.insert_table[table_id].zreg++;
-#endif
-
-                /* calc the item hardware address in ZBLK Reg. */
-                p_item->hw_addr = ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, reg_index);
-#if OBTAIN_CONFLICT_KEY
-                /*                    debug start 获取冲突键值*/
-                ZXIC_COMM_PRINT("zreg_mono conflict,inserted,reg_num is:0x%x,zblk_idx is:0x%x,p_item->hw_addr is:0x%x\n", reg_index, zblk_idx, p_item->hw_addr);
-                ZXIC_COMM_PRINT("zreg_mono conflict,key is:");
-
-                for (index = 0; index < 8; index++)
-                {
-                    ZXIC_COMM_PRINT("0x%x ", p_rbkey_new->key[index]);
-                }
-
-                ZXIC_COMM_PRINT("\n");
-                /*                    debug end*/
-#endif
-                break;
-            }
-        }
-
-        if (*p_end_flag)
-        {
-            break;
-        }
-
-        p_zblk_dn = p_zblk_dn->next;
-    } 
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**
-* @param   p_se_cfg  算法模块公共管理数据结构指针
-* @param   fun_id      hash引擎号
-* @param   p_zblk_cfg
-*
-* @return
-* @remark  无
-* @see
-* @author  XCX      @date  2017/03/27
-************************************************************/
-DPP_STATUS dpp_hash_zblkcfg_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id, SE_ZBLK_CFG *p_zblk_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT8 ram_buf[SE_RAM_WIDTH / 8] = {0};
-
-    ZXIC_UINT32 dev_id = 0;
-
-#if DPP_WRITE_FILE_EN
-    ZXIC_UINT32 hw_addr = 0;
-#endif
-
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
-    ZXIC_COMM_CHECK_POINT(p_zblk_cfg);
-    ZXIC_COMM_CHECK_INDEX(fun_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1);
-
-    dev_id = p_se_cfg->dev_id;
-
-    /* write hash type*/
-    rc = zxic_comm_write_bits_ex(ram_buf,
-                           SE_RAM_WIDTH,
-                           1,
-                           DPP_SE_ZBLK_SERVICE_TYPE_START,
-                           DPP_SE_ZBLK_SERVICE_TYPE_START - DPP_SE_ZBLK_SERVICE_TYPE_END + 1);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_write_bits_ex");
-
-    /* write hash channel*/
-    rc = zxic_comm_write_bits_ex(ram_buf,
-                           SE_RAM_WIDTH,
-                           fun_id,
-                           DPP_SE_ZBLK_HASH_CHAN_START,
-                           DPP_SE_ZBLK_HASH_CHAN_START - DPP_SE_ZBLK_HASH_CHAN_END + 1);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_write_bits_ex");
-
-    /* write enable flag*/
-    rc = zxic_comm_write_bits_ex(ram_buf,
-                           SE_RAM_WIDTH,
-                           1,
-                           DPP_SE_ZBLK_HW_POS_EN_START,
-                           DPP_SE_ZBLK_HW_POS_EN_START - DPP_SE_ZBLK_HW_POS_EN_END + 1);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_write_bits_ex");
-
-#if DPP_WRITE_FILE_EN
-    hw_addr = ZBLK_REG_ADDR_CALC(p_zblk_cfg->zblk_idx, 0);
-
-    rc = dpp_data_w2f(hw_addr, ram_buf, FILE_TYPE_ZBLK_CFG);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_data_w2f");
-#endif
-
-#ifdef DPP_FLOW_HW_INIT
-    rc = dpp_se_zblk_serv_cfg_set(p_se_cfg->dev,
-                                  p_zblk_cfg->zblk_idx,
-                                  ALG_ZBLK_SERV_HASH,
-                                  fun_id,
-                                  1);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_zblk_serv_cfg_set");
-#endif
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**
-* @param   p_se_cfg  算法模块公共管理数据结构指针
-* @param   hash_id   hash引擎号
-* @param   bulk_id
-*
-* @return
-* @remark  无
-* @see
-* @author  XCX      @date  2017/03/27
-************************************************************/
-DPP_STATUS dpp_hash_bulk_mono_flags_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 hash_id, ZXIC_UINT32 bulk_id)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 hash0_mono_flag = 0;
-    ZXIC_UINT32 hash1_mono_flag = 0;
-    ZXIC_UINT32 hash2_mono_flag = 0;
-    ZXIC_UINT32 hash3_mono_flag = 0;
-
-#if DPP_WRITE_FILE_EN
-    ZXIC_UINT32 hash0_mono_flag_file = 0;
-    ZXIC_UINT32 hash1_mono_flag_file = 0;
-    ZXIC_UINT32 hash2_mono_flag_file = 0;
-    ZXIC_UINT32 hash3_mono_flag_file = 0;
-    ZXIC_UINT32 hash_mono_flags_file_reg = 0;
-    ZXIC_UINT32 hash_mono_flags_file_reg_addr = 0;
-    DPP_HASH_FILE_REG_T *p_hash_file_reg = NULL;
-#endif
-
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
-    ZXIC_COMM_CHECK_INDEX(hash_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1);
-    ZXIC_COMM_CHECK_INDEX(bulk_id, HASH_BULK_ID_MIN, HASH_BULK_ID_MAX);
-
-    dev_id = p_se_cfg->dev_id;
-
-    rc = dpp_se_hash_zcam_mono_flags_get(p_se_cfg->dev,
-                                         &hash0_mono_flag,
-                                         &hash1_mono_flag,
-                                         &hash2_mono_flag,
-                                         &hash3_mono_flag);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_zcam_mono_flags_get");
-
-    switch (hash_id)
-    {
-        case 0:
-        {
-            hash0_mono_flag |= (1U << bulk_id);
-            break;
-        }
-
-        case 1:
-        {
-            hash1_mono_flag |= (1U << bulk_id);
-            break;
-        }
-
-        case 2:
-        {
-            hash2_mono_flag |= (1U << bulk_id);
-            break;
-        }
-
-        case 3:
-        {
-            hash3_mono_flag |= (1U << bulk_id);
-            break;
-        }
-
-        default:
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n hash id is out of rang.");
-            ZXIC_COMM_ASSERT(0);
-        }
-    }
-
-    rc = dpp_se_hash_zcam_mono_flags_set(p_se_cfg->dev,
-                                         hash0_mono_flag,
-                                         hash1_mono_flag,
-                                         hash2_mono_flag,
-                                         hash3_mono_flag);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_zcam_mono_flags_set");
-
-#if DPP_WRITE_FILE_EN
-    hash_mono_flags_file_reg_addr = 0x1c4;
-
-    p_hash_file_reg = DPP_GET_HASH_FILE_REG();
-    hash_mono_flags_file_reg = p_hash_file_reg->hash_mono_flags_file_reg;
-
-    ZXIC_COMM_UINT32_GET_BITS(hash0_mono_flag_file, hash_mono_flags_file_reg, HASH0_MONO_FLAG_BT_START, HASH0_MONO_FLAG_BT_WIDTH);
-    ZXIC_COMM_UINT32_GET_BITS(hash1_mono_flag_file, hash_mono_flags_file_reg, HASH1_MONO_FLAG_BT_START, HASH1_MONO_FLAG_BT_WIDTH);
-    ZXIC_COMM_UINT32_GET_BITS(hash2_mono_flag_file, hash_mono_flags_file_reg, HASH2_MONO_FLAG_BT_START, HASH2_MONO_FLAG_BT_WIDTH);
-    ZXIC_COMM_UINT32_GET_BITS(hash3_mono_flag_file, hash_mono_flags_file_reg, HASH3_MONO_FLAG_BT_START, HASH3_MONO_FLAG_BT_WIDTH);
-
-    switch (hash_id)
-    {
-        case 0:
-        {
-            hash0_mono_flag_file |= (1U << bulk_id);
-            break;
-        }
-
-        case 1:
-        {
-            hash1_mono_flag_file |= (1U << bulk_id);
-            break;
-        }
-
-        case 2:
-        {
-            hash2_mono_flag_file |= (1U << bulk_id);
-            break;
-        }
-
-        case 3:
-        {
-            hash3_mono_flag_file |= (1U << bulk_id);
-            break;
-        }
-
-        default:
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n hash id is out of rang.");
-            ZXIC_COMM_ASSERT(0);
-        }
-    }
-
-    ZXIC_COMM_UINT32_WRITE_BITS(hash_mono_flags_file_reg,
-                          hash0_mono_flag_file,
-                          HASH0_MONO_FLAG_BT_START,
-                          HASH0_MONO_FLAG_BT_WIDTH);
-    ZXIC_COMM_UINT32_WRITE_BITS(hash_mono_flags_file_reg,
-                          hash1_mono_flag_file,
-                          HASH1_MONO_FLAG_BT_START,
-                          HASH1_MONO_FLAG_BT_WIDTH);
-    ZXIC_COMM_UINT32_WRITE_BITS(hash_mono_flags_file_reg,
-                          hash2_mono_flag_file,
-                          HASH2_MONO_FLAG_BT_START,
-                          HASH2_MONO_FLAG_BT_WIDTH);
-    ZXIC_COMM_UINT32_WRITE_BITS(hash_mono_flags_file_reg,
-                          hash3_mono_flag_file,
-                          HASH3_MONO_FLAG_BT_START,
-                          HASH3_MONO_FLAG_BT_WIDTH);
-
-    p_hash_file_reg->hash_mono_flags_file_reg = hash_mono_flags_file_reg;
-
-    rc = dpp_data_w2f(p_se_cfg->reg_base + hash_mono_flags_file_reg_addr, &p_hash_file_reg->hash_mono_flags_file_reg, FILE_TYPE_REG);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_data_w2f");
-#endif
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**
-* @param   p_se_cfg  算法模块公共管理数据结构指针
-* @param   p_zcell_cfg
-*
-* @return
-* @remark  无
-* @see
-* @author  XCX      @date  2017/03/27
-************************************************************/
-DPP_STATUS dpp_hash_zcell_mono_write(DPP_SE_CFG *p_se_cfg, SE_ZCELL_CFG *p_zcell_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 zblk_idx = 0;
-    ZXIC_UINT32 zcell_id = 0;
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 zcell0_bulk_id = 0;
-    ZXIC_UINT32 zcell0_mono_flag = 0;
-    ZXIC_UINT32 zcell1_bulk_id = 0;
-    ZXIC_UINT32 zcell1_mono_flag = 0;
-    ZXIC_UINT32 zcell2_bulk_id = 0;
-    ZXIC_UINT32 zcell2_mono_flag = 0;
-    ZXIC_UINT32 zcell3_bulk_id = 0;
-    ZXIC_UINT32 zcell3_mono_flag = 0;
-
-#if DPP_WRITE_FILE_EN
-    ZXIC_UINT32 zcell0_bulk_id_file = 0;
-    ZXIC_UINT32 zcell0_mono_flag_file = 0;
-    ZXIC_UINT32 zcell1_bulk_id_file = 0;
-    ZXIC_UINT32 zcell1_mono_flag_file = 0;
-    ZXIC_UINT32 zcell2_bulk_id_file = 0;
-    ZXIC_UINT32 zcell2_mono_flag_file = 0;
-    ZXIC_UINT32 zcell3_bulk_id_file = 0;
-    ZXIC_UINT32 zcell3_mono_flag_file = 0;
-    ZXIC_UINT32 zcell_mono_file_ram_addr = 0;
-
-    ZXIC_UINT8 *zcell_mono_file_ram = NULL;
-    DPP_HASH_FILE_REG_T *p_hash_file_reg = NULL;
-#endif
-
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
-    ZXIC_COMM_CHECK_POINT(p_zcell_cfg);
-
-    dev_id = p_se_cfg->dev_id;
-
-    zblk_idx = GET_ZBLK_IDX(p_zcell_cfg->zcell_idx);
-    zcell_id = p_zcell_cfg->zcell_idx & 0x3;
-    rc = dpp_se_zcell_mono_cfg_get(p_se_cfg->dev,
-                                   zblk_idx,
-                                   &zcell0_bulk_id,
-                                   &zcell0_mono_flag,
-                                   &zcell1_bulk_id,
-                                   &zcell1_mono_flag,
-                                   &zcell2_bulk_id,
-                                   &zcell2_mono_flag,
-                                   &zcell3_bulk_id,
-                                   &zcell3_mono_flag);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_zcell_mono_cfg_get");
-
-    switch (zcell_id)
-    {
-        case 0:
-        {
-            zcell0_bulk_id = p_zcell_cfg->bulk_id;
-            zcell0_mono_flag = 1;
-            break;
-        }
-
-        case 1:
-        {
-            zcell1_bulk_id = p_zcell_cfg->bulk_id;
-            zcell1_mono_flag = 1;
-            break;
-        }
-
-        case 2:
-        {
-            zcell2_bulk_id = p_zcell_cfg->bulk_id;
-            zcell2_mono_flag = 1;
-            break;
-        }
-
-        case 3:
-        {
-            zcell3_bulk_id = p_zcell_cfg->bulk_id;
-            zcell3_mono_flag = 1;
-            break;
-        }
-
-    }
-
-    rc = dpp_se_zcell_mono_cfg_set(p_se_cfg->dev,
-                                   zblk_idx,
-                                   zcell0_bulk_id,
-                                   zcell0_mono_flag,
-                                   zcell1_bulk_id,
-                                   zcell1_mono_flag,
-                                   zcell2_bulk_id,
-                                   zcell2_mono_flag,
-                                   zcell3_bulk_id,
-                                   zcell3_mono_flag);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_zcell_mono_cfg_set");
-
-#if DPP_WRITE_FILE_EN
-    zcell_mono_file_ram_addr = ZBLK_REG_ADDR_CALC(zblk_idx, 0x14);
-
-    p_hash_file_reg = DPP_GET_HASH_FILE_REG();
-    zcell_mono_file_ram = p_hash_file_reg->zcell_mono_file_ram;
-
-    if (0 == zcell_id)
-    {
-        ZXIC_COMM_MEMSET(zcell_mono_file_ram, 0, (SE_RAM_WIDTH / 8));
-    }
-
-    zxic_comm_read_bits_ex(zcell_mono_file_ram, SE_RAM_WIDTH, &zcell0_bulk_id_file,   ZCELL0_BULK_ID_BT_START,   ZCELL0_BULK_ID_BT_WIDTH);
-    zxic_comm_read_bits_ex(zcell_mono_file_ram, SE_RAM_WIDTH, &zcell0_mono_flag_file, ZCELL0_MONO_FLAG_BT_START, ZCELL0_MONO_FLAG_BT_WIDTH);
-    zxic_comm_read_bits_ex(zcell_mono_file_ram, SE_RAM_WIDTH, &zcell1_bulk_id_file,   ZCELL1_BULK_ID_BT_START,   ZCELL1_BULK_ID_BT_WIDTH);
-    zxic_comm_read_bits_ex(zcell_mono_file_ram, SE_RAM_WIDTH, &zcell1_mono_flag_file, ZCELL1_MONO_FLAG_BT_START, ZCELL1_MONO_FLAG_BT_WIDTH);
-    zxic_comm_read_bits_ex(zcell_mono_file_ram, SE_RAM_WIDTH, &zcell2_bulk_id_file,   ZCELL2_BULK_ID_BT_START,   ZCELL2_BULK_ID_BT_WIDTH);
-    zxic_comm_read_bits_ex(zcell_mono_file_ram, SE_RAM_WIDTH, &zcell2_mono_flag_file, ZCELL2_MONO_FLAG_BT_START, ZCELL2_MONO_FLAG_BT_WIDTH);
-    zxic_comm_read_bits_ex(zcell_mono_file_ram, SE_RAM_WIDTH, &zcell3_bulk_id_file,   ZCELL3_BULK_ID_BT_START,   ZCELL3_BULK_ID_BT_WIDTH);
-    zxic_comm_read_bits_ex(zcell_mono_file_ram, SE_RAM_WIDTH, &zcell3_mono_flag_file, ZCELL3_MONO_FLAG_BT_START, ZCELL3_MONO_FLAG_BT_WIDTH);
-
-    switch (zcell_id)
-    {
-        case 0:
-        {
-            zcell0_bulk_id_file = p_zcell_cfg->bulk_id;
-            zcell0_mono_flag_file = 1;
-            break;
-        }
-
-        case 1:
-        {
-            zcell1_bulk_id_file = p_zcell_cfg->bulk_id;
-            zcell1_mono_flag_file = 1;
-            break;
-        }
-
-        case 2:
-        {
-            zcell2_bulk_id_file = p_zcell_cfg->bulk_id;
-            zcell2_mono_flag_file = 1;
-            break;
-        }
-
-        case 3:
-        {
-            zcell3_bulk_id_file = p_zcell_cfg->bulk_id;
-            zcell3_mono_flag_file = 1;
-            break;
-        }
-
-        default:
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n zcell id is out of rang.");
-            ZXIC_COMM_ASSERT(0);
-        }
-    }
-
-    zxic_comm_write_bits_ex(zcell_mono_file_ram,
-                      SE_RAM_WIDTH,
-                      zcell0_bulk_id_file,
-                      ZCELL0_BULK_ID_BT_START,
-                      ZCELL0_BULK_ID_BT_WIDTH);
-    zxic_comm_write_bits_ex(zcell_mono_file_ram,
-                      SE_RAM_WIDTH,
-                      zcell0_mono_flag_file,
-                      ZCELL0_MONO_FLAG_BT_START,
-                      ZCELL0_MONO_FLAG_BT_WIDTH);
-    zxic_comm_write_bits_ex(zcell_mono_file_ram,
-                      SE_RAM_WIDTH,
-                      zcell1_bulk_id_file,
-                      ZCELL1_BULK_ID_BT_START,
-                      ZCELL1_BULK_ID_BT_WIDTH);
-    zxic_comm_write_bits_ex(zcell_mono_file_ram,
-                      SE_RAM_WIDTH,
-                      zcell1_mono_flag_file,
-                      ZCELL1_MONO_FLAG_BT_START,
-                      ZCELL1_MONO_FLAG_BT_WIDTH);
-    zxic_comm_write_bits_ex(zcell_mono_file_ram,
-                      SE_RAM_WIDTH,
-                      zcell2_bulk_id_file,
-                      ZCELL2_BULK_ID_BT_START,
-                      ZCELL2_BULK_ID_BT_WIDTH);
-    zxic_comm_write_bits_ex(zcell_mono_file_ram,
-                      SE_RAM_WIDTH,
-                      zcell2_mono_flag_file,
-                      ZCELL2_MONO_FLAG_BT_START,
-                      ZCELL2_MONO_FLAG_BT_WIDTH);
-    zxic_comm_write_bits_ex(zcell_mono_file_ram,
-                      SE_RAM_WIDTH,
-                      zcell3_bulk_id_file,
-                      ZCELL3_BULK_ID_BT_START,
-                      ZCELL3_BULK_ID_BT_WIDTH);
-    zxic_comm_write_bits_ex(zcell_mono_file_ram,
-                      SE_RAM_WIDTH,
-                      zcell3_mono_flag_file,
-                      ZCELL3_MONO_FLAG_BT_START,
-                      ZCELL3_MONO_FLAG_BT_WIDTH);
-
-    rc = dpp_data_w2f(zcell_mono_file_ram_addr, &p_hash_file_reg->zcell_mono_file_ram, FILE_TYPE_ZBLK_CFG);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_data_w2f");
-#endif
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**
-* @param   p_se_cfg  算法模块公共管理数据结构指针
-* @param   bulk_id
-* @param   zblk_idx
-* @param   zreg_id
-*
-* @return
-* @remark  无
-* @see
-* @author  XCX      @date  2017/03/27
-************************************************************/
-DPP_STATUS dpp_hash_zreg_mono_write(DPP_SE_CFG *p_se_cfg,
-                                    ZXIC_UINT32 bulk_id,
-                                    ZXIC_UINT32 zblk_idx,
-                                    ZXIC_UINT32 zreg_id)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 zreg0_bulk_id = 0;
-    ZXIC_UINT32 zreg0_mono_flag = 0;
-    ZXIC_UINT32 zreg1_bulk_id = 0;
-    ZXIC_UINT32 zreg1_mono_flag = 0;
-    ZXIC_UINT32 zreg2_bulk_id = 0;
-    ZXIC_UINT32 zreg2_mono_flag = 0;
-    ZXIC_UINT32 zreg3_bulk_id = 0;
-    ZXIC_UINT32 zreg3_mono_flag = 0;
-
-#if DPP_WRITE_FILE_EN
-    ZXIC_UINT32 zreg0_bulk_id_file = 0;
-    ZXIC_UINT32 zreg0_mono_flag_file = 0;
-    ZXIC_UINT32 zreg1_bulk_id_file = 0;
-    ZXIC_UINT32 zreg1_mono_flag_file = 0;
-    ZXIC_UINT32 zreg2_bulk_id_file = 0;
-    ZXIC_UINT32 zreg2_mono_flag_file = 0;
-    ZXIC_UINT32 zreg3_bulk_id_file = 0;
-    ZXIC_UINT32 zreg3_mono_flag_file = 0;
-    ZXIC_UINT8 *zreg_mono_file_ram = NULL;
-    ZXIC_UINT32 zreg_mono_file_ram_addr = 0;
-    DPP_HASH_FILE_REG_T *p_hash_file_reg = NULL;
-#endif
-
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
-
-    dev_id = p_se_cfg->dev_id;
-
-    rc = dpp_se_zreg_mono_cfg_get(p_se_cfg->dev,
-                                  zblk_idx,
-                                  &zreg0_bulk_id,
-                                  &zreg0_mono_flag,
-                                  &zreg1_bulk_id,
-                                  &zreg1_mono_flag,
-                                  &zreg2_bulk_id,
-                                  &zreg2_mono_flag,
-                                  &zreg3_bulk_id,
-                                  &zreg3_mono_flag);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_zreg_mono_cfg_get");
-
-    switch (zreg_id)
-    {
-        case 0:
-        {
-            zreg0_bulk_id = bulk_id;
-            zreg0_mono_flag = 1;
-            break;
-        }
-
-        case 1:
-        {
-            zreg1_bulk_id = bulk_id;
-            zreg1_mono_flag = 1;
-            break;
-        }
-
-        case 2:
-        {
-            zreg2_bulk_id = bulk_id;
-            zreg2_mono_flag = 1;
-            break;
-        }
-
-        case 3:
-        {
-            zreg3_bulk_id = bulk_id;
-            zreg3_mono_flag = 1;
-            break;
-        }
-
-        default:
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n zreg id is out of rang.");
-            ZXIC_COMM_ASSERT(0);
-        }
-    }
-
-    rc = dpp_se_zreg_mono_cfg_set(p_se_cfg->dev,
-                                  zblk_idx,
-                                  zreg0_bulk_id,
-                                  zreg0_mono_flag,
-                                  zreg1_bulk_id,
-                                  zreg1_mono_flag,
-                                  zreg2_bulk_id,
-                                  zreg2_mono_flag,
-                                  zreg3_bulk_id,
-                                  zreg3_mono_flag);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_zreg_mono_cfg_set");
-
-#if DPP_WRITE_FILE_EN
-    zreg_mono_file_ram_addr = ZBLK_REG_ADDR_CALC(zblk_idx, 0x15);
-
-    p_hash_file_reg = DPP_GET_HASH_FILE_REG();
-    zreg_mono_file_ram = p_hash_file_reg->zreg_mono_file_ram;
-
-    if (0 == zreg_id)
-    {
-        ZXIC_COMM_MEMSET(zreg_mono_file_ram, 0, (SE_RAM_WIDTH / 8));
-    }
-
-    zxic_comm_read_bits_ex(zreg_mono_file_ram,
-                     SE_RAM_WIDTH,
-                     &zreg0_bulk_id_file,
-                     ZREG0_BULK_ID_BT_START,
-                     ZREG0_BULK_ID_BT_WIDTH);
-    zxic_comm_read_bits_ex(zreg_mono_file_ram,
-                     SE_RAM_WIDTH,
-                     &zreg0_mono_flag_file,
-                     ZREG0_MONO_FLAG_BT_START,
-                     ZREG0_MONO_FLAG_BT_WIDTH);
-    zxic_comm_read_bits_ex(zreg_mono_file_ram,
-                     SE_RAM_WIDTH,
-                     &zreg1_bulk_id_file,
-                     ZREG1_BULK_ID_BT_START,
-                     ZREG1_BULK_ID_BT_WIDTH);
-    zxic_comm_read_bits_ex(zreg_mono_file_ram,
-                     SE_RAM_WIDTH,
-                     &zreg1_mono_flag_file,
-                     ZREG1_MONO_FLAG_BT_START,
-                     ZREG1_MONO_FLAG_BT_WIDTH);
-    zxic_comm_read_bits_ex(zreg_mono_file_ram,
-                     SE_RAM_WIDTH,
-                     &zreg2_bulk_id_file,
-                     ZREG2_BULK_ID_BT_START,
-                     ZREG2_BULK_ID_BT_WIDTH);
-    zxic_comm_read_bits_ex(zreg_mono_file_ram,
-                     SE_RAM_WIDTH,
-                     &zreg2_mono_flag_file,
-                     ZREG2_MONO_FLAG_BT_START,
-                     ZREG2_MONO_FLAG_BT_WIDTH);
-    zxic_comm_read_bits_ex(zreg_mono_file_ram,
-                     SE_RAM_WIDTH,
-                     &zreg3_bulk_id_file,
-                     ZREG3_BULK_ID_BT_START,
-                     ZREG3_BULK_ID_BT_WIDTH);
-    zxic_comm_read_bits_ex(zreg_mono_file_ram,
-                     SE_RAM_WIDTH,
-                     &zreg3_mono_flag_file,
-                     ZREG3_MONO_FLAG_BT_START,
-                     ZREG3_MONO_FLAG_BT_WIDTH);
-
-    switch (zreg_id)
-    {
-        case 0:
-        {
-            zreg0_bulk_id_file = bulk_id;
-            zreg0_mono_flag_file = 1;
-            break;
-        }
-
-        case 1:
-        {
-            zreg1_bulk_id_file = bulk_id;
-            zreg1_mono_flag_file = 1;
-            break;
-        }
-
-        case 2:
-        {
-            zreg2_bulk_id_file = bulk_id;
-            zreg2_mono_flag_file = 1;
-            break;
-        }
-
-        case 3:
-        {
-            zreg3_bulk_id_file = bulk_id;
-            zreg3_mono_flag_file = 1;
-            break;
-        }
-
-        default:
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n zcell id is out of rang.");
-            ZXIC_COMM_ASSERT(0);
-        }
-    }
-
-    zxic_comm_write_bits_ex(zreg_mono_file_ram,
-                      SE_RAM_WIDTH,
-                      zreg0_bulk_id_file,
-                      ZREG0_BULK_ID_BT_START,
-                      ZREG0_BULK_ID_BT_WIDTH);
-    zxic_comm_write_bits_ex(zreg_mono_file_ram,
-                      SE_RAM_WIDTH,
-                      zreg0_mono_flag_file,
-                      ZREG0_MONO_FLAG_BT_START,
-                      ZREG0_MONO_FLAG_BT_WIDTH);
-    zxic_comm_write_bits_ex(zreg_mono_file_ram,
-                      SE_RAM_WIDTH,
-                      zreg1_bulk_id_file,
-                      ZREG1_BULK_ID_BT_START,
-                      ZREG1_BULK_ID_BT_WIDTH);
-    zxic_comm_write_bits_ex(zreg_mono_file_ram,
-                      SE_RAM_WIDTH,
-                      zreg1_mono_flag_file,
-                      ZREG1_MONO_FLAG_BT_START,
-                      ZREG1_MONO_FLAG_BT_WIDTH);
-    zxic_comm_write_bits_ex(zreg_mono_file_ram,
-                      SE_RAM_WIDTH,
-                      zreg2_bulk_id_file,
-                      ZREG2_BULK_ID_BT_START,
-                      ZREG2_BULK_ID_BT_WIDTH);
-    zxic_comm_write_bits_ex(zreg_mono_file_ram,
-                      SE_RAM_WIDTH,
-                      zreg2_mono_flag_file,
-                      ZREG2_MONO_FLAG_BT_START,
-                      ZREG2_MONO_FLAG_BT_WIDTH);
-    zxic_comm_write_bits_ex(zreg_mono_file_ram,
-                      SE_RAM_WIDTH,
-                      zreg3_bulk_id_file,
-                      ZREG3_BULK_ID_BT_START,
-                      ZREG3_BULK_ID_BT_WIDTH);
-    zxic_comm_write_bits_ex(zreg_mono_file_ram,
-                      SE_RAM_WIDTH,
-                      zreg3_mono_flag_file,
-                      ZREG3_MONO_FLAG_BT_START,
-                      ZREG3_MONO_FLAG_BT_WIDTH);
-
-    rc = dpp_data_w2f(zreg_mono_file_ram_addr, &p_hash_file_reg->zreg_mono_file_ram, FILE_TYPE_ZBLK_CFG);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_data_w2f");
-#endif
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** hash ddr参数配置
-* @param   p_se_cfg  算法模块公共管理数据结构指针
-* @param   fun_id    hash引擎号
-* @param   bulk_id
-* @param   p_ddr_cfg
-*
-* @return
-* @remark  无
-* @see
-* @author  wcl      @date  2014/07/31
-************************************************************/
-DPP_STATUS dpp_hash_ext_cfg_write(DPP_SE_CFG *p_se_cfg,
-                                  ZXIC_UINT32 fun_id,
-                                  ZXIC_UINT32 bulk_id,
-                                  HASH_DDR_CFG *p_ddr_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 ext_mode = 0;
-    ZXIC_UINT32 ext_flag = 0;
-    ZXIC_UINT32 dev_id = 0;
-
-#if DPP_WRITE_FILE_EN
-    ZXIC_UINT32 ext_mode_file = 0;
-    ZXIC_UINT32 ext_flag_file = 0;
-    ZXIC_UINT32 ext_cfg_file_reg = 0;
-    ZXIC_UINT32 ext_cfg_file_reg_addr = 0;
-    DPP_HASH_FILE_REG_T *p_hash_file_reg = NULL;
-#endif
-
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
-    ZXIC_COMM_CHECK_POINT(p_ddr_cfg);
-    ZXIC_COMM_CHECK_INDEX(fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX);
-    ZXIC_COMM_CHECK_INDEX(bulk_id, HASH_BULK_ID_MIN, HASH_BULK_ID_MAX);
-
-    dev_id = p_se_cfg->dev_id;
-
-    rc = dpp_se_hash_ext_cfg_get(p_se_cfg->dev, fun_id, &ext_mode, &ext_flag);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_ext_cfg_get");
-
-    ext_flag = 1;
-
-    if (p_ddr_cfg->width_mode == DDR_WIDTH_256b)
-    {
-        ext_mode = (ext_mode & (~(1U << bulk_id)));
-    }
-    else if (p_ddr_cfg->width_mode == DDR_WIDTH_512b)
-    {
-        ext_mode = (ext_mode | (1U << bulk_id));
-    }
-
-#if DPP_WRITE_FILE_EN
-    ext_cfg_file_reg_addr = 0xbc + fun_id * 4;
-
-    p_hash_file_reg = DPP_GET_HASH_FILE_REG();
-    ext_cfg_file_reg = p_hash_file_reg->ext_cfg_file_reg[fun_id];
-
-    ZXIC_COMM_UINT32_GET_BITS(ext_mode_file,
-                        ext_cfg_file_reg,
-                        HASH_EXT_MODE_BT_START,
-                        HASH_EXT_MODE_BT_WIDTH);
-    ZXIC_COMM_UINT32_GET_BITS(ext_flag_file,
-                        ext_cfg_file_reg,
-                        HASH_EXT_FLAG_BT_START,
-                        HASH_EXT_FLAG_BT_WIDTH);
-
-    ext_flag_file = 1;
-
-    if (DDR_WIDTH_256b == p_ddr_cfg->width_mode)
-    {
-        ext_mode_file = (ext_mode_file & (~(1U << bulk_id)));
-    }
-    else if (p_ddr_cfg->width_mode == DDR_WIDTH_512b)
-    {
-        ext_mode_file = (ext_mode_file | (1U << bulk_id));
-    }
-
-    ZXIC_COMM_UINT32_WRITE_BITS(ext_cfg_file_reg,
-                          ext_mode_file,
-                          HASH_EXT_MODE_BT_START,
-                          HASH_EXT_MODE_BT_WIDTH);
-    ZXIC_COMM_UINT32_WRITE_BITS(ext_cfg_file_reg,
-                          ext_flag_file,
-                          HASH_EXT_FLAG_BT_START,
-                          HASH_EXT_FLAG_BT_WIDTH);
-
-    p_hash_file_reg->ext_cfg_file_reg[fun_id] = ext_cfg_file_reg;
-
-    rc = dpp_data_w2f(p_se_cfg->reg_base + ext_cfg_file_reg_addr, &p_hash_file_reg->ext_cfg_file_reg[fun_id], FILE_TYPE_REG);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_data_w2f");
-#endif
-
-    rc = dpp_se_hash_ext_cfg_set(p_se_cfg->dev, fun_id, ext_mode, ext_flag);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_ext_cfg_set");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**
-* @param   p_se_cfg  算法模块公共管理数据结构指针
-* @param   fun_id    hash引擎号
-*
-* @return
-* @remark  无
-* @see
-* @author  wcl      @date  2014/07/31
-************************************************************/
-DPP_STATUS dpp_hash_ext_cfg_clr(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 ext_mode = 0;
-    ZXIC_UINT32 ext_flag = 0;
-    ZXIC_UINT32 dev_id = 0;
-
-#if DPP_WRITE_FILE_EN
-    ZXIC_UINT32 ddr_cfg_dat = 0;
-    ZXIC_UINT32 ext_cfg_reg_addr = 0;
-#endif
-
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
-    ZXIC_COMM_CHECK_INDEX(fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX);
-
-    dev_id = p_se_cfg->dev_id;
-
-#if DPP_WRITE_FILE_EN
-    ext_cfg_reg_addr = 0xbc + fun_id * 4;
-
-    rc = dpp_data_w2f(p_se_cfg->reg_base + ext_cfg_reg_addr, &ddr_cfg_dat, FILE_TYPE_REG);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_data_w2f");
-#endif
-
-    rc = dpp_se_hash_ext_cfg_set(p_se_cfg->dev,
-                                 fun_id,
-                                 ext_mode,
-                                 ext_flag);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_ext_cfg_set");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** hash 业务表ddr深度配置
-* @param   p_se_cfg  算法模块公共管理数据结构指针
-* @param   fun_id    hash引擎号
-* @param   bulk_id
-* @param   p_ddr_cfg
-*
-* @return
-* @remark  无
-* @see
-* @author  tf      @date  2016/01/28
-************************************************************/
-DPP_STATUS dpp_hash_tbl_depth_write(DPP_SE_CFG *p_se_cfg,
-                                    ZXIC_UINT32 fun_id,
-                                    ZXIC_UINT32 bulk_id,
-                                    HASH_DDR_CFG *p_ddr_cfg)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 ext_depth = 0;
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 hash_tbl0_depth = 0;
-    ZXIC_UINT32 hash_tbl1_depth = 0;
-    ZXIC_UINT32 hash_tbl2_depth = 0;
-    ZXIC_UINT32 hash_tbl3_depth = 0;
-    ZXIC_UINT32 hash_tbl4_depth = 0;
-    ZXIC_UINT32 hash_tbl5_depth = 0;
-    ZXIC_UINT32 hash_tbl6_depth = 0;
-    ZXIC_UINT32 hash_tbl7_depth = 0;
-
-#if DPP_WRITE_FILE_EN
-    ZXIC_UINT32 hash_tbl0_depth_file = 0;
-    ZXIC_UINT32 hash_tbl1_depth_file = 0;
-    ZXIC_UINT32 hash_tbl2_depth_file = 0;
-    ZXIC_UINT32 hash_tbl3_depth_file = 0;
-    ZXIC_UINT32 hash_tbl4_depth_file = 0;
-    ZXIC_UINT32 hash_tbl5_depth_file = 0;
-    ZXIC_UINT32 hash_tbl6_depth_file = 0;
-    ZXIC_UINT32 hash_tbl7_depth_file = 0;
-    ZXIC_UINT32 tbl03_depth_file_reg = 0;
-    ZXIC_UINT32 tbl47_depth_file_reg = 0;
-    ZXIC_UINT32 hash_tbl_depth_file_reg_addr = 0;
-    DPP_HASH_FILE_REG_T *p_hash_file_reg = NULL;
-#endif
-
-    ZXIC_UINT32 hash_tbl_depth_array[HASH_BULK_NUM] = {0};
-
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
-    ZXIC_COMM_CHECK_POINT(p_ddr_cfg);
-    ZXIC_COMM_CHECK_INDEX(fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX);
-    ZXIC_COMM_CHECK_INDEX(bulk_id, HASH_BULK_ID_MIN, HASH_BULK_ID_MAX);
-
-    dev_id = p_se_cfg->dev_id;
-
-    ext_depth = dpp_hash_ddr_depth_conv(p_ddr_cfg->item_num);
-
-    if (((ZXIC_UINT32)1 << ext_depth) != p_ddr_cfg->item_num)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ErrCode[ 0x%x ]: Hash DDR item num:[ %d ] is not N power of 2.\n",
-                                 DPP_HASH_RC_INVALID_PARA,
-                                 p_ddr_cfg->item_num);
-        ZXIC_COMM_ASSERT(0);
-        return DPP_HASH_RC_INVALID_PARA;
-    }
-
-    rc = dpp_se_hash_tbl_depth_get(p_se_cfg->dev,
-                                   fun_id,
-                                   &hash_tbl0_depth,
-                                   &hash_tbl1_depth,
-                                   &hash_tbl2_depth,
-                                   &hash_tbl3_depth,
-                                   &hash_tbl4_depth,
-                                   &hash_tbl5_depth,
-                                   &hash_tbl6_depth,
-                                   &hash_tbl7_depth);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_tbl_depth_get");
-
-    hash_tbl_depth_array[0] = hash_tbl0_depth;
-    hash_tbl_depth_array[1] = hash_tbl1_depth;
-    hash_tbl_depth_array[2] = hash_tbl2_depth;
-    hash_tbl_depth_array[3] = hash_tbl3_depth;
-    hash_tbl_depth_array[4] = hash_tbl4_depth;
-    hash_tbl_depth_array[5] = hash_tbl5_depth;
-    hash_tbl_depth_array[6] = hash_tbl6_depth;
-    hash_tbl_depth_array[7] = hash_tbl7_depth;
-
-
-    hash_tbl_depth_array[bulk_id] = ext_depth;
-
-    hash_tbl0_depth = hash_tbl_depth_array[0];
-    hash_tbl1_depth = hash_tbl_depth_array[1];
-    hash_tbl2_depth = hash_tbl_depth_array[2];
-    hash_tbl3_depth = hash_tbl_depth_array[3];
-    hash_tbl4_depth = hash_tbl_depth_array[4];
-    hash_tbl5_depth = hash_tbl_depth_array[5];
-    hash_tbl6_depth = hash_tbl_depth_array[6];
-    hash_tbl7_depth = hash_tbl_depth_array[7];
-
-#if DPP_WRITE_FILE_EN
-    hash_tbl_depth_file_reg_addr = 0x01a4 + fun_id * 8;
-
-    p_hash_file_reg = DPP_GET_HASH_FILE_REG();
-    tbl03_depth_file_reg = p_hash_file_reg->hash_depth_file_regs[fun_id].tbl03_depth_file_reg;
-    tbl47_depth_file_reg = p_hash_file_reg->hash_depth_file_regs[fun_id].tbl47_depth_file_reg;
-
-    ZXIC_COMM_UINT32_GET_BITS(hash_tbl0_depth_file, tbl03_depth_file_reg, HASH_TBL0_DEPTH_BT_START, HASH_TBL0_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_GET_BITS(hash_tbl1_depth_file, tbl03_depth_file_reg, HASH_TBL1_DEPTH_BT_START, HASH_TBL1_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_GET_BITS(hash_tbl2_depth_file, tbl03_depth_file_reg, HASH_TBL2_DEPTH_BT_START, HASH_TBL2_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_GET_BITS(hash_tbl3_depth_file, tbl03_depth_file_reg, HASH_TBL3_DEPTH_BT_START, HASH_TBL3_DEPTH_BT_WIDTH);
-
-    ZXIC_COMM_UINT32_GET_BITS(hash_tbl4_depth_file, tbl47_depth_file_reg, HASH_TBL4_DEPTH_BT_START, HASH_TBL4_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_GET_BITS(hash_tbl5_depth_file, tbl47_depth_file_reg, HASH_TBL5_DEPTH_BT_START, HASH_TBL5_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_GET_BITS(hash_tbl6_depth_file, tbl47_depth_file_reg, HASH_TBL6_DEPTH_BT_START, HASH_TBL6_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_GET_BITS(hash_tbl7_depth_file, tbl47_depth_file_reg, HASH_TBL7_DEPTH_BT_START, HASH_TBL7_DEPTH_BT_WIDTH);
-
-    hash_tbl_depth_array[0] = hash_tbl0_depth_file;
-    hash_tbl_depth_array[1] = hash_tbl1_depth_file;
-    hash_tbl_depth_array[2] = hash_tbl2_depth_file;
-    hash_tbl_depth_array[3] = hash_tbl3_depth_file;
-    hash_tbl_depth_array[4] = hash_tbl4_depth_file;
-    hash_tbl_depth_array[5] = hash_tbl5_depth_file;
-    hash_tbl_depth_array[6] = hash_tbl6_depth_file;
-    hash_tbl_depth_array[7] = hash_tbl7_depth_file;
-
-
-    hash_tbl_depth_array[bulk_id] = ext_depth;
-
-    hash_tbl0_depth_file = hash_tbl_depth_array[0];
-    hash_tbl1_depth_file = hash_tbl_depth_array[1];
-    hash_tbl2_depth_file = hash_tbl_depth_array[2];
-    hash_tbl3_depth_file = hash_tbl_depth_array[3];
-    hash_tbl4_depth_file = hash_tbl_depth_array[4];
-    hash_tbl5_depth_file = hash_tbl_depth_array[5];
-    hash_tbl6_depth_file = hash_tbl_depth_array[6];
-    hash_tbl7_depth_file = hash_tbl_depth_array[7];
-
-    ZXIC_COMM_UINT32_WRITE_BITS(tbl03_depth_file_reg, hash_tbl0_depth_file, HASH_TBL0_DEPTH_BT_START, HASH_TBL0_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_WRITE_BITS(tbl03_depth_file_reg, hash_tbl1_depth_file, HASH_TBL1_DEPTH_BT_START, HASH_TBL1_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_WRITE_BITS(tbl03_depth_file_reg, hash_tbl2_depth_file, HASH_TBL2_DEPTH_BT_START, HASH_TBL2_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_WRITE_BITS(tbl03_depth_file_reg, hash_tbl3_depth_file, HASH_TBL3_DEPTH_BT_START, HASH_TBL3_DEPTH_BT_WIDTH);
-
-    ZXIC_COMM_UINT32_WRITE_BITS(tbl47_depth_file_reg, hash_tbl4_depth_file, HASH_TBL4_DEPTH_BT_START, HASH_TBL4_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_WRITE_BITS(tbl47_depth_file_reg, hash_tbl5_depth_file, HASH_TBL5_DEPTH_BT_START, HASH_TBL5_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_WRITE_BITS(tbl47_depth_file_reg, hash_tbl6_depth_file, HASH_TBL6_DEPTH_BT_START, HASH_TBL6_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_WRITE_BITS(tbl47_depth_file_reg, hash_tbl7_depth_file, HASH_TBL7_DEPTH_BT_START, HASH_TBL7_DEPTH_BT_WIDTH);
-
-    p_hash_file_reg->hash_depth_file_regs[fun_id].tbl03_depth_file_reg = tbl03_depth_file_reg;
-    p_hash_file_reg->hash_depth_file_regs[fun_id].tbl47_depth_file_reg = tbl47_depth_file_reg;
-
-    rc = dpp_data_w2f(p_se_cfg->reg_base + hash_tbl_depth_file_reg_addr,     &tbl03_depth_file_reg, FILE_TYPE_REG);
-    rc = dpp_data_w2f(p_se_cfg->reg_base + hash_tbl_depth_file_reg_addr + 4, &tbl47_depth_file_reg, FILE_TYPE_REG) + rc;
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_data_w2f");
-#endif
-
-    rc = dpp_se_hash_tbl_depth_set(p_se_cfg->dev,
-                                   fun_id,
-                                   hash_tbl0_depth,
-                                   hash_tbl1_depth,
-                                   hash_tbl2_depth,
-                                   hash_tbl3_depth,
-                                   hash_tbl4_depth,
-                                   hash_tbl5_depth,
-                                   hash_tbl6_depth,
-                                   hash_tbl7_depth);
-
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_tbl_depth_set");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** hash 业务表ddr深度恢复默认值
-* @param   p_se_cfg  算法模块公共管理数据结构指针
-* @param   fun_id    hash引擎号
-*
-* @return
-* @remark  无
-* @see
-* @author  tf      @date  2016/01/28
-************************************************************/
-DPP_STATUS dpp_hash_tbl_depth_clr(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 hash_tbl0_depth = 0x12;
-    ZXIC_UINT32 hash_tbl1_depth = 0x12;
-    ZXIC_UINT32 hash_tbl2_depth = 0x12;
-    ZXIC_UINT32 hash_tbl3_depth = 0x12;
-    ZXIC_UINT32 hash_tbl4_depth = 0x12;
-    ZXIC_UINT32 hash_tbl5_depth = 0x12;
-    ZXIC_UINT32 hash_tbl6_depth = 0x12;
-    ZXIC_UINT32 hash_tbl7_depth = 0x12;
-
-#if DPP_WRITE_FILE_EN
-    ZXIC_UINT32 hash_tbl_depth_reg_file_addr = 0;
-    ZXIC_UINT32 hash_tbl03_depth_reg_file_dat = 0;
-    ZXIC_UINT32 hash_tbl47_depth_reg_file_dat = 0;
-#endif
-
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
-    ZXIC_COMM_CHECK_INDEX(fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX);
-
-    dev_id = p_se_cfg->dev_id;
-
-#if DPP_WRITE_FILE_EN
-    hash_tbl_depth_reg_file_addr = 0x01a4 + fun_id * 8;
-
-    ZXIC_COMM_UINT32_WRITE_BITS(hash_tbl03_depth_reg_file_dat, hash_tbl0_depth, HASH_TBL0_DEPTH_BT_START, HASH_TBL0_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_WRITE_BITS(hash_tbl03_depth_reg_file_dat, hash_tbl1_depth, HASH_TBL1_DEPTH_BT_START, HASH_TBL1_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_WRITE_BITS(hash_tbl03_depth_reg_file_dat, hash_tbl2_depth, HASH_TBL2_DEPTH_BT_START, HASH_TBL2_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_WRITE_BITS(hash_tbl03_depth_reg_file_dat, hash_tbl3_depth, HASH_TBL3_DEPTH_BT_START, HASH_TBL3_DEPTH_BT_WIDTH);
-
-    ZXIC_COMM_UINT32_WRITE_BITS(hash_tbl47_depth_reg_file_dat, hash_tbl4_depth, HASH_TBL4_DEPTH_BT_START, HASH_TBL4_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_WRITE_BITS(hash_tbl47_depth_reg_file_dat, hash_tbl5_depth, HASH_TBL5_DEPTH_BT_START, HASH_TBL5_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_WRITE_BITS(hash_tbl47_depth_reg_file_dat, hash_tbl6_depth, HASH_TBL6_DEPTH_BT_START, HASH_TBL6_DEPTH_BT_WIDTH);
-    ZXIC_COMM_UINT32_WRITE_BITS(hash_tbl47_depth_reg_file_dat, hash_tbl7_depth, HASH_TBL7_DEPTH_BT_START, HASH_TBL7_DEPTH_BT_WIDTH);
-
-    rc = dpp_data_w2f(p_se_cfg->reg_base + hash_tbl_depth_reg_file_addr, &hash_tbl03_depth_reg_file_dat, FILE_TYPE_REG);
-    rc = dpp_data_w2f(p_se_cfg->reg_base + hash_tbl_depth_reg_file_addr + 4, &hash_tbl47_depth_reg_file_dat, FILE_TYPE_REG) + rc;
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_data_w2f");
-#endif
-
-    rc = dpp_se_hash_tbl_depth_set(p_se_cfg->dev,
-                                   fun_id,
-                                   hash_tbl0_depth,
-                                   hash_tbl1_depth,
-                                   hash_tbl2_depth,
-                                   hash_tbl3_depth,
-                                   hash_tbl4_depth,
-                                   hash_tbl5_depth,
-                                   hash_tbl6_depth,
-                                   hash_tbl7_depth);
-
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_tbl_depth_set");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** hash CRC多项式选择
-* @param   fun_id    hash引擎号
-* @param   crc_sel
-*
-* @return
-* @remark  无
-* @see
-* @author  tf      @date  2016/01/28
-************************************************************/
-DPP_STATUS dpp_hash_tbl_crc_poly_write(DPP_SE_CFG *p_se_cfg,
-                                       ZXIC_UINT32 fun_id,
-                                       ZXIC_UINT32 bulk_id,
-                                       ZXIC_UINT32 crc_sel)
-{
-    DPP_STATUS rtn = DPP_OK;
-
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 hash_tbl_crc_cfg_bt_start = 0;
-    ZXIC_UINT32 hash_tbl_crc_cfg_bt_width = 2;
-    DPP_SE4K_SE_ALG_HASH10_EXT_CRC_CFG_T  hash01_ext_crc_cfg = {0};
-    DPP_SE4K_SE_ALG_HASH32_EXT_CRC_CFG_T  hash23_ext_crc_cfg = {0};
-
-#if DPP_WRITE_FILE_EN
-    ZXIC_UINT32 ext_crc_cfg_file_reg = 0;
-    ZXIC_UINT32 ext_crc_cfg_file_reg_addr = 0;
-    DPP_HASH_FILE_REG_T *p_hash_file_reg = NULL;
-#endif
-
-    ZXIC_COMM_ASSERT(p_se_cfg);
-
-    dev_id = p_se_cfg->dev_id;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX(dev_id, bulk_id, HASH_BULK_ID_MIN, HASH_BULK_ID_MAX);
-
-    hash_tbl_crc_cfg_bt_start = bulk_id * 2;
-
-    if (fun_id == 0 || fun_id == 1)
-    {
-        rtn = dpp_reg_read(p_se_cfg->dev, SE4K_SE_ALG_HASH10_EXT_CRC_CFGr, 0, 0, &hash01_ext_crc_cfg);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_reg_read");
-
-        if (fun_id == 0)
-        {
-            ZXIC_COMM_UINT32_WRITE_BITS(hash01_ext_crc_cfg.hash0_crc_cfg, crc_sel, hash_tbl_crc_cfg_bt_start, hash_tbl_crc_cfg_bt_width);
-        }
-        else
-        {
-            ZXIC_COMM_UINT32_WRITE_BITS(hash01_ext_crc_cfg.hash1_crc_cfg, crc_sel, hash_tbl_crc_cfg_bt_start, hash_tbl_crc_cfg_bt_width);
-        }
-
-        rtn = dpp_reg_write(p_se_cfg->dev, SE4K_SE_ALG_HASH10_EXT_CRC_CFGr, 0, 0, &hash01_ext_crc_cfg);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_reg_write");
-
-    }
-    else
-    {
-        rtn = dpp_reg_read(p_se_cfg->dev, SE4K_SE_ALG_HASH32_EXT_CRC_CFGr, 0, 0, &hash23_ext_crc_cfg);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_reg_read");
-
-        if (fun_id == 2)
-        {
-            ZXIC_COMM_UINT32_WRITE_BITS(hash23_ext_crc_cfg.hash2_crc_cfg, crc_sel, hash_tbl_crc_cfg_bt_start, hash_tbl_crc_cfg_bt_width);
-        }
-        else
-        {
-            ZXIC_COMM_UINT32_WRITE_BITS(hash23_ext_crc_cfg.hash3_crc_cfg, crc_sel, hash_tbl_crc_cfg_bt_start, hash_tbl_crc_cfg_bt_width);
-        }
-
-        rtn = dpp_reg_write(p_se_cfg->dev, SE4K_SE_ALG_HASH32_EXT_CRC_CFGr, 0, 0, &hash23_ext_crc_cfg);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_reg_write");
-    }
-
-#if DPP_WRITE_FILE_EN
-    p_hash_file_reg = DPP_GET_HASH_FILE_REG();
-
-    if (fun_id == 0 || fun_id == 1)
-    {
-        ext_crc_cfg_file_reg_addr = 0x01cc;
-
-        hash_tbl_crc_cfg_bt_start = fun_id * 16 + bulk_id * 2;
-
-        ext_crc_cfg_file_reg = p_hash_file_reg->ext_crc_cfg_file_reg[0];
-        ZXIC_COMM_UINT32_WRITE_BITS(ext_crc_cfg_file_reg, crc_sel, hash_tbl_crc_cfg_bt_start, hash_tbl_crc_cfg_bt_width);
-
-        p_hash_file_reg->ext_crc_cfg_file_reg[0] = ext_crc_cfg_file_reg;
-
-        rtn = dpp_data_w2f(p_se_cfg->reg_base + ext_crc_cfg_file_reg_addr, &p_hash_file_reg->ext_crc_cfg_file_reg[0], FILE_TYPE_REG);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_data_w2f");
-
-    }
-    else
-    {
-        ext_crc_cfg_file_reg_addr = 0x01d0;
-
-        hash_tbl_crc_cfg_bt_start = (fun_id - 2) * 16 + bulk_id * 2;
-
-        ext_crc_cfg_file_reg = p_hash_file_reg->ext_crc_cfg_file_reg[1];
-        ZXIC_COMM_UINT32_WRITE_BITS(ext_crc_cfg_file_reg, crc_sel, hash_tbl_crc_cfg_bt_start, hash_tbl_crc_cfg_bt_width);
-
-        p_hash_file_reg->ext_crc_cfg_file_reg[1] = ext_crc_cfg_file_reg;
-
-        rtn = dpp_data_w2f(p_se_cfg->reg_base + ext_crc_cfg_file_reg_addr, &p_hash_file_reg->ext_crc_cfg_file_reg[1], FILE_TYPE_REG);
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_data_w2f");
-    }
-
-#endif
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 清除hash引擎的所有hash表项(清除软件配置)
-* @param   p_se_cfg
-* @param   hash_id
-* @param   bulk_id
-*
-* @return
-* @remark  无
-* @see
-* @author  cq      @date  2023/08/18
-************************************************************/
-DPP_STATUS dpp_hash_soft_all_entry_delete(DPP_SE_CFG *p_se_cfg,ZXIC_UINT32 hash_id)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT8 table_id = 0;
-    ZXIC_UINT32 bulk_id = 0;
-
-    D_NODE *p_node = NULL;
-    ZXIC_RB_TN *p_rb_tn = NULL;
-    ZXIC_RB_TN *p_rb_tn_rtn = NULL;
-    D_HEAD *p_head_hash_rb = NULL;
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    FUNC_ID_INFO *p_func_info = NULL;
-    DPP_HASH_RBKEY_INFO *p_rbkey = NULL;
-    DPP_HASH_RBKEY_INFO *p_rbkey_rtn = NULL;
-    SE_ITEM_CFG *p_item = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
-    ZXIC_COMM_CHECK_INDEX(hash_id, 0, HASH_FUNC_ID_NUM - 1);
-
-    dev_id = p_se_cfg->dev_id;
-
-    p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_id);
-    DPP_SE_CHECK_FUN(p_func_info, hash_id, FUN_HASH);
-
-    p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
-    p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list;
-
-    while (p_head_hash_rb->used)
-    {
-        p_node = p_head_hash_rb->p_next;
-        p_rb_tn = (ZXIC_RB_TN *)p_node->data;
-        p_rbkey = (DPP_HASH_RBKEY_INFO *)p_rb_tn->p_key;
-        table_id = DPP_GET_HASH_TBL_ID(p_rbkey->key);
-        bulk_id = ((table_id >> 2) & 0x7);
-        ZXIC_COMM_CHECK_DEV_INDEX(dev_id, bulk_id, 0, HASH_BULK_NUM - 1);
-
-        rc = zxic_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey, &p_rb_tn_rtn);
-        if (ZXIC_RBT_RC_SRHFAIL == rc)
-        {
-            p_hash_cfg->hash_stat.delete_fail++;
-            ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "Error!there is not item in hash!\n");
-            return DPP_HASH_RC_DEL_SRHFAIL;
-        }
-
-        ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn);
-        p_rbkey_rtn = (DPP_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key);
-        p_item = p_rbkey_rtn->p_item_info;
-        
-        rc = zxic_comm_double_link_del(&(p_rbkey_rtn->entry_dn), &(p_item->item_list));
-        ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_del");
-        p_item->wrt_mask &= ~(DPP_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, p_rbkey_rtn->entry_pos)) & 0xF;
-
-        if (0 == p_item->item_list.used)
-        {
-            if ((ITEM_DDR_256 == p_item->item_type) || (ITEM_DDR_512 == p_item->item_type))
-            {
-                /* modify coverity by yinxh 2021.03.10*,以256bit为单位。暂不考虑512bit的情况*/
-                ZXIC_COMM_CHECK_INDEX_UPPER(p_item->item_index, p_hash_cfg->p_bulk_ddr_info[bulk_id]->item_num);
-                p_hash_cfg->p_bulk_ddr_info[bulk_id]->p_item_array[p_item->item_index] = NULL;
-                ZXIC_COMM_FREE(p_item);
-            }
-            else
-            {
-                p_item->valid = 0;
-            }
-        }
-
-        ZXIC_COMM_FREE(p_rbkey_rtn);
-        ZXIC_COMM_FREE(p_rb_tn_rtn);
-        p_hash_cfg->hash_stat.delete_ok++;
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 卸载软件上分配的hash资源(主要针对malloc释放)
-* @param   dev_id  设备号 
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/12/20
-************************************************************/
-DPP_STATUS dpp_hash_soft_uninstall(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc       = DPP_OK;
-    ZXIC_UINT32 hash_id  = 0;
-
-    ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-
-    for(hash_id=0;hash_id<HASH_FUNC_ID_NUM;hash_id++)
-    {
-        rc = dpp_one_hash_soft_uninstall(dev_id,hash_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_one_hash_soft_uninstall");
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 卸载指定hashid上软件分配的hash资源(主要针对malloc释放)
-* @param   dev_id  设备号 
-* @param   hash_id  hash id 0~3
-* @return  
-* @remark  无
-* @see     
-* @author  cq      @date  2023/12/20
-************************************************************/
-DPP_STATUS dpp_one_hash_soft_uninstall(ZXIC_UINT32 dev_id,ZXIC_UINT32 hash_id)
-{
-    ZXIC_UINT32 rc = 0;
-    ZXIC_UINT32 i = 0;
-
-    D_NODE *p_node = NULL;
-    DPP_SE_CFG *p_se_cfg = NULL;
-    ZXIC_RB_TN *p_rb_tn = NULL;
-    ZXIC_RB_TN *p_rb_tn_rtn = NULL;
-    HASH_DDR_CFG *p_rbkey = NULL;
-    DPP_HASH_CFG *p_hash_cfg = NULL;
-    FUNC_ID_INFO *p_func_info = NULL;
-    D_HEAD *p_head_ddr_cfg_rb = NULL;
-    HASH_DDR_CFG *p_temp_rbkey = NULL;
-
-    ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_INDEX(hash_id, 0, HASH_FUNC_ID_NUM - 1);
-
-    /* 取出se配置 */
-    rc = dpp_se_cfg_get(dev_id, &p_se_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_cfg_get");
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg);
-    p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_id);
-    if (0 == p_func_info->is_used)
-    {
-        ZXIC_COMM_TRACE_DEBUG("Error[0x%x], fun_id [%d] is not init\n!", DPP_SE_RC_FUN_INVALID, hash_id);
-        return DPP_OK;
-    }
-
-    /*软件删除表项,删除红黑树节点*/
-    rc = dpp_hash_soft_all_entry_delete(p_se_cfg,hash_id);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_soft_all_entry_delete");
-
-    /*释放独占标识内存*/
-    p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
-    for (i = 0; i < HASH_BULK_NUM; i++)
-    {
-        if ((&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i] != NULL)
-        {
-            ZXIC_COMM_FREE((&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i]);
-            (&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i] = NULL;
-        }
-    }
-
-    /*释放DDR分配的所有内存*/
-    p_head_ddr_cfg_rb = &p_hash_cfg->ddr_cfg_rb.tn_list;
-    while (p_head_ddr_cfg_rb->used)
-    {
-        p_node = p_head_ddr_cfg_rb->p_next;
-
-        p_rb_tn = (ZXIC_RB_TN *)p_node->data;
-        p_rbkey = p_rb_tn->p_key;
-
-        rc = zxic_comm_rb_delete(&p_hash_cfg->ddr_cfg_rb, p_rbkey, &p_rb_tn_rtn);
-
-        if (ZXIC_RBT_RC_SRHFAIL == rc)
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ddr_cfg_rb delete key is not exist, key: 0x");
-        }
-        else
-        {
-            ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_rb_delete");
-        }
-
-        ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn);
-        p_temp_rbkey = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key);
-        ZXIC_COMM_FREE(p_temp_rbkey->p_item_array);
-        p_temp_rbkey->p_item_array = NULL;
-        ZXIC_COMM_FREE(p_temp_rbkey);
-        ZXIC_COMM_FREE(p_rb_tn_rtn);
-    }
-
-    rc = dpp_hash_zcam_resource_deinit(p_hash_cfg);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_zcam_resource_deinit");
-
-    rc = dpp_se_fun_deinit(p_se_cfg, (hash_id & 0xff), FUN_HASH);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_fun_deinit");
-
-    ZXIC_COMM_MEMSET(g_tbl_id_info[dev_id][hash_id], 0, HASH_TBL_ID_NUM * sizeof(DPP_HASH_TBL_ID_INFO));
-
-    return DPP_OK;
-}
-
-#endif
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_hash.c
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : wcl
+* 完成日期 : 2014/02/08
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#include "zxic_common.h"
+
+#include "dpp_dev.h"
+#include "dpp_module.h"
+#include "dpp_se_cfg.h"
+#include "dpp_hash_crc.h"
+#include "dpp_hash.h"
+#include "dpp_se.h"
+#include "dpp_se_reg.h"
+#include "dpp_reg_api.h"
+#include "dpp_reg_info.h"
+#include "dpp_se4k_reg.h"
+#include "dpp_sdt.h"
+
+#define HASH_CMP_ZCELL (1)
+#define HASH_CMP_ZBLK (2)
+
+#define HASH_ENTRY_STAT
+
+/* 全局变量定义区 */
+static ZXIC_UINT32 g_ddr_hash_arg[HASH_DDR_CRC_NUM] = { 0x04C11DB7, 0xF4ACFB13,
+														0x20044009,
+														0x00210801 };
+
+static DPP_HASH_TBL_ID_INFO g_tbl_id_info[DPP_DEV_CHANNEL_MAX][HASH_FUNC_ID_NUM]
+										 [HASH_TBL_ID_NUM] = { { { { 0 } } } };
+
+/** 4个hash引擎，每个最多使用32个zblock */
+static ZXIC_UINT32 g_hash_zblk_idx[DPP_DEV_CHANNEL_MAX][HASH_FUNC_ID_NUM]
+								  [HASH_TBL_ID_NUM] = { { { 0 } } };
+
+static DPP_HASH_SOFT_RESET_STOR_DAT g_hash_store_dat[DPP_DEV_CHANNEL_MAX] = {
+	{ { 0 } }
+};
+
+static ZXIC_UINT64 g_se_cfg_point;
+
+/* 宏函数定义区 */
+#define GET_DDR_HASH_ARG(ddr_crc_sel) (g_ddr_hash_arg[ddr_crc_sel])
+#define GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id) \
+	(&g_tbl_id_info[dev_id][fun_id][tbl_id])
+#define GET_ACTU_KEY_SIZE_BY_TBLID(dev_id, fun_id, tbl_id) \
+	(g_tbl_id_info[dev_id][fun_id][tbl_id].actu_key_size)
+
+#define HASH_TBL_ID_INFO_CHECK(dev_id, fun_id, tbl_id, key_type)               \
+	do {                                                                       \
+		if (!g_tbl_id_info[dev_id][fun_id][tbl_id].is_init ||                  \
+			(g_tbl_id_info[dev_id][fun_id][tbl_id].key_type != key_type)) {    \
+			ZXIC_COMM_PRINT(                                                   \
+					"init [%d], config ketype[%d] parameter key_type[%d].\n",  \
+					g_tbl_id_info[dev_id][fun_id][tbl_id].is_init,             \
+					g_tbl_id_info[dev_id][fun_id][tbl_id].key_type, key_type); \
+			ZXIC_COMM_ASSERT(0);                                               \
+			return DPP_HASH_RC_INVALID_TBL_ID_INFO;                            \
+		}                                                                      \
+	} while (0)
+
+#define GET_HASH_DDR_HW_ADDR(base_addr, item_idx) ((base_addr) + (item_idx))
+
+/* 9:zcell depth */
+#define GET_HASH_ZCAM_HW_ADDR(base_addr, zblk_idx, item_idx) \
+	((base_addr) + ((zblk_idx) << 9) + (item_idx))
+
+#define DPP_GET_HASH_FILE_REG() (&g_hash_file_reg)
+
+/* 局部函数声明区 */
+
+/* 函数实现区 */
+
+#if ZXIC_REAL("inter func.")
+/***********************************************************/
+/** zblock资源链表排序比较函数
+* @param   data1        待比较的数据1
+* @param   data2        待比较的数据2
+* @param   data         排序比较的类型，1-zcell比较，2-zblock比较
+*
+* @return  1-data1比data2的索引大
+*           0-data1和data2索引相同
+*          -1-data1比data2的索引小
+* @remark  无
+* @see
+* @author  wcl      @date  2014/11/10
+************************************************************/
+ZXIC_SINT32 dpp_hash_list_cmp(D_NODE *data1, D_NODE *data2, void *data)
+{
+	ZXIC_UINT32 flag = 0;
+	ZXIC_UINT32 data_new = 0;
+	ZXIC_UINT32 data_pre = 0;
+
+	ZXIC_COMM_CHECK_POINT(data1);
+	ZXIC_COMM_CHECK_POINT(data2);
+	ZXIC_COMM_CHECK_POINT(data);
+
+	flag = *(ZXIC_UINT32 *)data;
+
+	if (flag == HASH_CMP_ZCELL) {
+		data_new = ((SE_ZCELL_CFG *)data1->data)->zcell_idx;
+		data_pre = ((SE_ZCELL_CFG *)data2->data)->zcell_idx;
+	} else if (flag == HASH_CMP_ZBLK) {
+		data_new = ((SE_ZBLK_CFG *)data1->data)->zblk_idx;
+		data_pre = ((SE_ZBLK_CFG *)data2->data)->zblk_idx;
+	}
+
+	if (data_new > data_pre) {
+		return 1;
+	} else if (data_new == data_pre) {
+		return 0;
+	} else {
+		return -1;
+	}
+}
+
+/***********************************************************/
+/** hash键值红黑树插入比较函数
+ * @param   p_new
+ * @param   p_old
+ * @param   key_size
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2014/11/10
+ ************************************************************/
+ZXIC_SINT32 dpp_hash_rb_key_cmp(ZXIC_VOID *p_new, ZXIC_VOID *p_old,
+								ZXIC_UINT32 key_size)
+{
+	DPP_HASH_RBKEY_INFO *p_rbkey_new = NULL;
+	DPP_HASH_RBKEY_INFO *p_rbkey_old = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_new);
+	ZXIC_COMM_CHECK_POINT(p_old);
+	p_rbkey_new = (DPP_HASH_RBKEY_INFO *)(p_new);
+	p_rbkey_old = (DPP_HASH_RBKEY_INFO *)(p_old);
+
+	return ZXIC_COMM_MEMCMP(p_rbkey_new->key, p_rbkey_old->key, HASH_KEY_MAX);
+}
+
+/***********************************************************/
+/** hash键值红黑树插入比较函数
+ * @param   p_new
+ * @param   p_old
+ * @param   key_size
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  tf      @date  2016/03/26
+ ************************************************************/
+ZXIC_SINT32 dpp_hash_ddr_cfg_rb_key_cmp(ZXIC_VOID *p_new, ZXIC_VOID *p_old,
+										ZXIC_UINT32 key_size)
+{
+	HASH_DDR_CFG *p_rbkey_new = NULL;
+	HASH_DDR_CFG *p_rbkey_old = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_new);
+	ZXIC_COMM_CHECK_POINT(p_old);
+	p_rbkey_new = (HASH_DDR_CFG *)(p_new);
+	p_rbkey_old = (HASH_DDR_CFG *)(p_old);
+
+	return ZXIC_COMM_MEMCMP(&p_rbkey_new->ddr_baddr, &p_rbkey_old->ddr_baddr,
+							sizeof(ZXIC_UINT32));
+}
+
+/***********************************************************/
+/** 获取位宽
+ * @param   ddr_item_num
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2014/11/10
+ ************************************************************/
+ZXIC_UINT32 dpp_hash_ddr_depth_conv(ZXIC_UINT32 ddr_item_num)
+{
+	ZXIC_UINT32 count = 0;
+
+	while (ddr_item_num > ((ZXIC_UINT32)1 << count)) {
+		count++;
+	}
+
+	return count;
+}
+
+/***********************************************************/
+/** 片内资源初始化
+ * @param   p_hash_cfg
+ * @param   zblk_num
+ * @param   zblk_idx_array
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/10/13
+ ************************************************************/
+DPP_STATUS dpp_hash_zcam_resource_init(DPP_HASH_CFG *p_hash_cfg,
+									   ZXIC_UINT32 zblk_num,
+									   ZXIC_UINT32 *zblk_idx_array)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 j = 0;
+	ZXIC_UINT32 cmp_type = 0;
+	ZXIC_UINT32 zblk_idx = 0;
+	ZXIC_UINT32 zcell_idx = 0;
+	ZXIC_UINT32 dev_id = 0;
+
+	D_HEAD *p_zblk_list = NULL;
+	D_HEAD *p_zcell_free = NULL;
+	SE_ZBLK_CFG *p_zblk_cfg = NULL;
+	SE_ZCELL_CFG *p_zcell_cfg = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_hash_cfg);
+	ZXIC_COMM_CHECK_INDEX(zblk_num, 0, SE_ZBLK_NUM);
+	ZXIC_COMM_CHECK_POINT(zblk_idx_array);
+
+	dev_id = p_hash_cfg->p_se_info->dev_id;
+
+	/* init zblock list */
+	p_zblk_list = &p_hash_cfg->hash_shareram.zblk_list;
+	rc = zxic_comm_double_link_init(SE_ZBLK_NUM, p_zblk_list);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_init");
+
+	/* init zcell list */
+	p_zcell_free = &p_hash_cfg->hash_shareram.zcell_free_list;
+	rc = zxic_comm_double_link_init(SE_ZBLK_NUM * SE_ZCELL_NUM, p_zcell_free);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_init");
+
+	for (i = 0; i < zblk_num; i++) {
+		zblk_idx = zblk_idx_array[i];
+		/* debug start */
+		// ZXIC_COMM_PRINT("zblk_idx is [%d]\n", zblk_idx); /* t */
+		/* debug end */
+		ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zblk_idx, 0, SE_ZBLK_NUM - 1);
+		p_zblk_cfg = DPP_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, zblk_idx);
+
+		if (p_zblk_cfg->is_used) {
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					dev_id,
+					"ErrorCode:[0x%x], ZBlock[%d] is already used by other function!\n",
+					DPP_HASH_RC_INVALID_ZBLCK, zblk_idx);
+			ZXIC_COMM_ASSERT(0);
+			return DPP_HASH_RC_INVALID_ZBLCK;
+		}
+
+		for (j = 0; j < SE_ZCELL_NUM; j++) {
+			zcell_idx = p_zblk_cfg->zcell_info[j].zcell_idx;
+			p_zcell_cfg =
+					DPP_SE_GET_ZCELL_CFG(p_hash_cfg->p_se_info, zcell_idx);
+
+			if (p_zcell_cfg->is_used) {
+				ZXIC_COMM_TRACE_DEV_ERROR(
+						dev_id,
+						"ErrorCode:[0x%x], ZBlk[%d], ZCell[%d] is already used by other function!\n",
+						DPP_HASH_RC_INVALID_ZCELL, zblk_idx, zcell_idx);
+				ZXIC_COMM_ASSERT(0);
+				return DPP_HASH_RC_INVALID_ZCELL;
+			}
+
+			p_zcell_cfg->is_used = 1;
+
+			/* insert to free zcell free list */
+			cmp_type = HASH_CMP_ZCELL;
+			rc = zxic_comm_double_link_insert_sort(&p_zcell_cfg->zcell_dn,
+												   p_zcell_free,
+												   dpp_hash_list_cmp,
+												   &cmp_type);
+			ZXIC_COMM_CHECK_DEV_RC(dev_id, rc,
+								   "zxic_comm_double_link_insert_sort");
+		}
+
+		/* insert to zblock list */
+		p_zblk_cfg->is_used = 1;
+		cmp_type = HASH_CMP_ZBLK;
+		rc = zxic_comm_double_link_insert_sort(&p_zblk_cfg->zblk_dn,
+											   p_zblk_list, dpp_hash_list_cmp,
+											   &cmp_type);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_insert_last");
+
+		/* config zblock */
+		rc = dpp_hash_zblkcfg_write(p_hash_cfg->p_se_info, p_hash_cfg->fun_id,
+									p_zblk_cfg);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_zblkcfg_write");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**
+ * @param   p_hash_cfg
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XCX      @date  2018/03/22
+ ************************************************************/
+DPP_STATUS dpp_hash_zcam_resource_deinit(DPP_HASH_CFG *p_hash_cfg)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 dev_id = 0;
+
+	D_NODE *p_node = NULL;
+	D_HEAD *p_head = NULL;
+	SE_ZBLK_CFG *p_zblk_cfg = NULL;
+	SE_ZCELL_CFG *p_zcell_cfg = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_hash_cfg);
+
+	dev_id = p_hash_cfg->p_se_info->dev_id;
+
+	/*delete zcell node*/
+	p_head = &p_hash_cfg->hash_shareram.zcell_free_list;
+
+	while (p_head->used) {
+		p_node = p_head->p_next;
+
+		rc = zxic_comm_double_link_del(p_node, p_head);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_del");
+		p_zcell_cfg = (SE_ZCELL_CFG *)p_node->data;
+		p_zcell_cfg->is_used = 0;
+	}
+
+	/*delete zblk node*/
+	p_head = &p_hash_cfg->hash_shareram.zblk_list;
+
+	while (p_head->used) {
+		p_node = p_head->p_next;
+
+		rc = zxic_comm_double_link_del(p_node, p_head);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_del");
+
+		ZXIC_COMM_CHECK_DEV_INDEX(dev_id,
+								  ((SE_ZBLK_CFG *)p_node->data)->zblk_idx, 0,
+								  HASH_ZBLK_ID_MAX);
+		p_zblk_cfg = DPP_SE_GET_ZBLK_CFG(
+				p_hash_cfg->p_se_info, ((SE_ZBLK_CFG *)p_node->data)->zblk_idx);
+		p_zblk_cfg->is_used = 0;
+
+		/*clear zblk config*/
+		/* dpp_hash_zblkcfg_clr(p_hash_cfg->p_se_info, p_hash_cfg->fun_id, p_zblk_cfg); */
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**
+ * @param   item_entry_max
+ * @param   wrt_mask
+ * @param   entry_size
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XCX      @date  2018/03/22
+ ************************************************************/
+ZXIC_UINT32 dpp_hash_get_item_free_pos(ZXIC_UINT32 item_entry_max,
+									   ZXIC_UINT32 wrt_mask,
+									   ZXIC_UINT32 entry_size)
+{
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 pos = 0xFFFFFFFF; /* -1; */
+	ZXIC_UINT32 mask = 0;
+
+	for (i = 0; i < item_entry_max; i += entry_size / HASH_ENTRY_POS_STEP) {
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(
+				i, entry_size / HASH_ENTRY_POS_STEP);
+		mask = DPP_GET_HASH_ENTRY_MASK(entry_size, i);
+
+		if (0 == (mask & wrt_mask)) {
+			pos = i;
+			break;
+		}
+	}
+
+	return pos;
+}
+
+/***********************************************************/
+/**
+ * @param   p_hash_cfg
+ * @param   p_rbkey
+ * @param   p_item
+ * @param   item_idx
+ * @param   item_type
+ * @param   insrt_key_type
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XCX      @date  2018/03/22
+ ************************************************************/
+DPP_STATUS dpp_hash_insrt_to_item(DPP_HASH_CFG *p_hash_cfg,
+								  DPP_HASH_RBKEY_INFO *p_rbkey,
+								  SE_ITEM_CFG *p_item, ZXIC_UINT32 item_idx,
+								  ZXIC_UINT32 item_type,
+								  ZXIC_UINT32 insrt_key_type)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 free_pos = 0;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 item_entry_max = ITEM_ENTRY_NUM_4;
+
+	ZXIC_COMM_CHECK_POINT(p_hash_cfg);
+	ZXIC_COMM_CHECK_POINT(p_rbkey);
+	ZXIC_COMM_CHECK_POINT(p_item);
+
+	dev_id = p_hash_cfg->p_se_info->dev_id;
+
+	if (ITEM_DDR_256 == item_type) {
+		item_entry_max = ITEM_ENTRY_NUM_2;
+	}
+
+	if (!p_item->valid) { /* item is not used */
+		rc = zxic_comm_double_link_init(item_entry_max, &p_item->item_list);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_init");
+
+		p_rbkey->entry_pos = HASH_ITEM_POS_0;
+		p_item->wrt_mask = DPP_GET_HASH_ENTRY_MASK(p_rbkey->entry_size,
+												   p_rbkey->entry_pos);
+		p_item->item_index = item_idx;
+		p_item->item_type = item_type;
+		p_item->valid = 1;
+	} else {
+		free_pos = dpp_hash_get_item_free_pos(item_entry_max, p_item->wrt_mask,
+											  p_rbkey->entry_size);
+
+		if (0xFFFFFFFF == free_pos) {
+			return DPP_HASH_RC_ITEM_FULL;
+		} else {
+			p_rbkey->entry_pos = free_pos;
+			p_item->wrt_mask |= DPP_GET_HASH_ENTRY_MASK(p_rbkey->entry_size,
+														p_rbkey->entry_pos);
+		}
+	}
+
+	/* debug*/
+	ZXIC_COMM_TRACE_DEV_DEBUG(
+			dev_id, "Entry in item pos is: [%d], entry size is: [%d].\n",
+			free_pos, p_rbkey->entry_size);
+
+	rc = zxic_comm_double_link_insert_last(&p_rbkey->entry_dn,
+										   &p_item->item_list);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_insert_last");
+
+	p_rbkey->p_item_info = p_item;
+
+	return DPP_OK;
+}
+
+#endif
+
+#if ZXIC_REAL("External Func.")
+/***********************************************************/
+/** 单个hash引擎初始化
+ * @param   p_se_cfg      算法模块公共管理数据结构指针
+ * @param   fun_id        hash引擎号
+ * @param   zblk_num      分配给此hash引擎的zblock数目
+ * @param   zblk_idx      分配给此hash引擎的zblock编号
+ * @param   ddr_dis       DDR关闭位，0-不关闭片外DDR, 1-关闭片外DDR
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/05/15
+ ************************************************************/
+DPP_STATUS dpp_hash_init(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id,
+						 ZXIC_UINT32 zblk_num, ZXIC_UINT32 *zblk_idx,
+						 ZXIC_UINT32 ddr_dis)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 dev_id = 0;
+
+	FUNC_ID_INFO *p_func_info = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	ZXIC_COMM_CHECK_POINT(zblk_idx);
+	ZXIC_COMM_CHECK_INDEX(fun_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1);
+	ZXIC_COMM_CHECK_INDEX(zblk_num, 0, SE_ZBLK_NUM);
+	ZXIC_COMM_CHECK_INDEX(ddr_dis, 0, 1);
+
+	dev_id = p_se_cfg->dev_id;
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+
+	rc = dpp_se_fun_init(p_se_cfg, (fun_id & 0xff), FUN_HASH);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_fun_init");
+
+	p_func_info = DPP_GET_FUN_INFO(p_se_cfg, fun_id);
+	p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
+	p_hash_cfg->fun_id = fun_id;
+	p_hash_cfg->p_hash32_fun = dpp_crc32_calc;
+	p_hash_cfg->p_hash16_fun = dpp_crc16_calc;
+	p_hash_cfg->p_se_info = p_se_cfg;
+
+	/*    判定hash引擎是片内模式还是混合模式*/
+	if (ddr_dis == 1) {
+		/* disable ddr */
+		p_hash_cfg->ddr_valid = 0;
+
+#ifdef DPP_FLOW_HW_INIT
+		rc = dpp_hash_ext_cfg_clr(p_se_cfg, fun_id);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_ddrcfg_clr");
+
+		rc = dpp_hash_tbl_depth_clr(p_se_cfg, fun_id);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_tbl_depth_clr");
+#endif
+	} else {
+		p_hash_cfg->ddr_valid = 1;
+	}
+
+	/*    zcam初始化*/
+	p_hash_cfg->hash_stat.zblock_num = zblk_num;
+	rc = dpp_hash_zcam_resource_init(p_hash_cfg, zblk_num, zblk_idx);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_zcam_resource_init");
+
+	/* 将zblock_id记录在软件缓存中 */
+	for (i = 0; i < zblk_num; i++) {
+		p_hash_cfg->hash_stat.zblock_array[i] = zblk_idx[i];
+	}
+
+	/* dynamic alloc rb_tree node by user. */
+	rc = (DPP_STATUS)zxic_comm_rb_init(&p_hash_cfg->hash_rb, 0,
+									   sizeof(DPP_HASH_RBKEY_INFO),
+									   dpp_hash_rb_key_cmp);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_rb_init");
+
+	/* dynamic alloc rb_tree node by user. */
+	rc = (DPP_STATUS)zxic_comm_rb_init(&p_hash_cfg->ddr_cfg_rb, 0,
+									   sizeof(HASH_DDR_CFG),
+									   dpp_hash_ddr_cfg_rb_key_cmp);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_rb_init");
+
+	/** for 软复位 */
+	/** 保存zblock内容 */
+	for (i = 0; i < zblk_num; i++) {
+		g_hash_zblk_idx[dev_id][fun_id][i] = zblk_idx[i];
+	}
+
+	g_hash_store_dat[dev_id].ddr_dis_flag[fun_id] = ddr_dis;
+	g_hash_store_dat[dev_id].zblk_num[fun_id] = zblk_num;
+	g_hash_store_dat[dev_id].zblk_idx_start[fun_id] =
+			g_hash_zblk_idx[dev_id][fun_id];
+	g_hash_store_dat[dev_id].hash_id_valid |=
+			(ZXIC_UINT32)((1U << fun_id) & 0xffffffff);
+
+	/** for diag */
+	g_se_cfg_point = ZXIC_COMM_PTR_TO_VAL(p_se_cfg);
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 初始化单个hash引擎内的某个业务表，此接口支持为该业务表分配独占的zcell。
+ *     必须先初始化hash引擎，再初始化业务表。
+ * @param   p_se_cfg        算法模块公共管理数据结构指针
+ * @param   fun_id          hash引擎号
+ * @param   bulk_id         每个Hash引擎资源划分的空间ID号
+ * @param   p_ddr_resc_cfg  分配给hash引擎此资源空间的ddr资源属性
+ * @param   zcell_num       分配给hash引擎此资源空间的zcell数量
+ * @param   zreg_num        分配给hash引擎此资源空间的zreg数量
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/05/15
+ ************************************************************/
+DPP_STATUS dpp_hash_bulk_init(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id,
+							  ZXIC_UINT32 bulk_id,
+							  DPP_HASH_DDR_RESC_CFG_T *p_ddr_resc_cfg,
+							  ZXIC_UINT32 zcell_num, ZXIC_UINT32 zreg_num)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 j = 0;
+	ZXIC_UINT32 zblk_idx = 0;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 ddr_item_num = 0;
+
+	D_NODE *p_zblk_dn = NULL;
+	D_NODE *p_zcell_dn = NULL;
+	ZXIC_RB_TN *p_rb_tn_new = NULL;
+	ZXIC_RB_TN *p_rb_tn_rtn = NULL;
+	SE_ZBLK_CFG *p_zblk_cfg = NULL;
+	SE_ZREG_CFG *p_zreg_cfg = NULL;
+	HASH_DDR_CFG *p_ddr_cfg = NULL;
+	HASH_DDR_CFG *p_rbkey_new = NULL;
+	HASH_DDR_CFG *p_rbkey_rtn = NULL;
+	SE_ZCELL_CFG *p_zcell_cfg = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	FUNC_ID_INFO *p_func_info = NULL;
+	SE_ITEM_CFG **p_item_array = NULL;
+	DPP_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono = NULL;
+	/*    D_HEAD *p_zcell_free = NULL;*/
+	/*    D_HEAD *p_zblk_free = NULL;*/
+
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	ZXIC_COMM_CHECK_POINT(p_ddr_resc_cfg);
+	ZXIC_COMM_CHECK_INDEX(p_ddr_resc_cfg->ddr_crc_sel, 0, HASH_DDR_CRC_NUM - 1);
+	ZXIC_COMM_CHECK_INDEX(fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX);
+	ZXIC_COMM_CHECK_INDEX(bulk_id, HASH_BULK_ID_MIN, HASH_BULK_ID_MAX);
+	ZXIC_COMM_CHECK_INDEX(zcell_num, 0, SE_ZBLK_NUM * SE_ZCELL_NUM);
+	ZXIC_COMM_CHECK_INDEX(zreg_num, 0, SE_ZBLK_NUM * SE_ZREG_NUM);
+
+	dev_id = p_se_cfg->dev_id;
+
+	p_func_info = DPP_GET_FUN_INFO(p_se_cfg, fun_id);
+	p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
+	ZXIC_COMM_CHECK_POINT(p_hash_cfg);
+
+	ZXIC_COMM_TRACE_INFO("p_hash_cfg->ddr_valid = %d!\n",
+						 p_hash_cfg->ddr_valid);
+
+	if (1 == p_hash_cfg->ddr_valid) {
+		/* [a long time ago] hash存储深度不能超过26bit，不然会导致硬件逻辑crc index不一致，微码查表不中 */
+		ZXIC_COMM_CHECK_DEV_INDEX(dev_id, p_ddr_resc_cfg->ddr_item_num,
+								  HASH_DDR_ITEM_MIN, HASH_DDR_ITEM_MAX);
+
+		ddr_item_num = p_ddr_resc_cfg->ddr_item_num;
+
+		if (DDR_WIDTH_512b == p_ddr_resc_cfg->ddr_width_mode) {
+			ddr_item_num = p_ddr_resc_cfg->ddr_item_num >> 1;
+			ZXIC_COMM_CHECK_DEV_INDEX(
+					dev_id, ddr_item_num, HASH_DDR_ITEM_MIN,
+					HASH_DDR_ITEM_MAX); /* 512bit存储时，hash存储深度不能少于14bit */
+		}
+
+		/** red&black key*/
+		p_rbkey_new = (HASH_DDR_CFG *)ZXIC_COMM_MALLOC(sizeof(HASH_DDR_CFG));
+		ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rbkey_new);
+		ZXIC_COMM_MEMSET(p_rbkey_new, 0, sizeof(HASH_DDR_CFG));
+
+		p_rbkey_new->ddr_baddr = p_ddr_resc_cfg->ddr_baddr;
+
+		/** red&black tree node*/
+		p_rb_tn_new = (ZXIC_RB_TN *)ZXIC_COMM_MALLOC(sizeof(ZXIC_RB_TN));
+		if (NULL == (p_rb_tn_new)) {
+			ZXIC_COMM_FREE(p_rbkey_new);
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					dev_id, "\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",
+					__FILE__, __LINE__, __FUNCTION__);
+			return ZXIC_PAR_CHK_POINT_NULL;
+		}
+		INIT_RBT_TN(p_rb_tn_new, p_rbkey_new);
+
+		rc = zxic_comm_rb_insert(&p_hash_cfg->ddr_cfg_rb,
+								 (ZXIC_VOID *)p_rb_tn_new,
+								 (ZXIC_VOID *)(&p_rb_tn_rtn));
+		if (ZXIC_RBT_RC_FULL == rc) {
+			ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "The red black tree is full!\n");
+			ZXIC_COMM_FREE(p_rbkey_new);
+			ZXIC_COMM_FREE(p_rb_tn_new);
+			ZXIC_COMM_ASSERT(0);
+			return DPP_HASH_RC_RB_TREE_FULL;
+		} else if (ZXIC_RBT_RC_UPDATE == rc) {
+			ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "some bulk_id share one bulk!\n");
+
+			ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn);
+			p_rbkey_rtn = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key);
+			ZXIC_COMM_CHECK_DEV_INDEX(dev_id, p_rbkey_rtn->bulk_id, 0,
+									  HASH_BULK_NUM - 1);
+			p_ddr_cfg =
+					p_hash_cfg->p_bulk_ddr_info
+							[p_rbkey_rtn->bulk_id]; /* 已经初始化过的ddr_bulk_id属性 */
+
+			if (p_ddr_cfg->hash_ddr_arg !=
+						GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel) ||
+				p_ddr_cfg->width_mode != p_ddr_resc_cfg->ddr_width_mode ||
+				p_ddr_cfg->ddr_ecc_en != p_ddr_resc_cfg->ddr_ecc_en ||
+				p_ddr_cfg->item_num != ddr_item_num) {
+				ZXIC_COMM_TRACE_DEV_ERROR(
+						dev_id,
+						"The base address is same but other ddr attribute is different\n");
+				ZXIC_COMM_FREE(p_rbkey_new);
+				ZXIC_COMM_FREE(p_rb_tn_new);
+				ZXIC_COMM_ASSERT(0);
+				return DPP_HASH_RC_INVALID_PARA;
+			}
+
+			p_hash_cfg->p_bulk_ddr_info[bulk_id] =
+					p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id];
+
+			ZXIC_COMM_TRACE_DEV_DEBUG(dev_id,
+									  "bulk id init bulk_ddr_cfg ptr is:");
+
+			for (i = 0; i < HASH_BULK_NUM; i++) {
+				ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "%p ",
+										  p_hash_cfg->p_bulk_ddr_info[i]);
+			}
+
+			ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "\n");
+
+			ZXIC_COMM_FREE(p_rbkey_new);
+			ZXIC_COMM_FREE(p_rb_tn_new);
+		} else {
+			p_item_array = (SE_ITEM_CFG **)ZXIC_COMM_MALLOC(
+					ddr_item_num * sizeof(SE_ITEM_CFG *));
+			if (NULL == (p_item_array)) {
+				ZXIC_COMM_FREE(p_rbkey_new);
+				ZXIC_COMM_FREE(p_rb_tn_new);
+				ZXIC_COMM_TRACE_DEV_ERROR(
+						dev_id,
+						"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",
+						__FILE__, __LINE__, __FUNCTION__);
+				return ZXIC_PAR_CHK_POINT_NULL;
+			}
+			ZXIC_COMM_MEMSET(p_item_array, 0,
+							 ddr_item_num * sizeof(SE_ITEM_CFG *));
+
+			p_rbkey_new->p_item_array = p_item_array;
+			p_rbkey_new->bulk_id = bulk_id;
+			p_rbkey_new->hw_baddr = 0;
+			p_rbkey_new->width_mode = p_ddr_resc_cfg->ddr_width_mode;
+			p_rbkey_new->item_num = ddr_item_num;
+			p_rbkey_new->ddr_ecc_en = p_ddr_resc_cfg->ddr_ecc_en;
+			p_rbkey_new->hash_ddr_arg =
+					GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel);
+			p_rbkey_new->bulk_use = 1;
+			p_rbkey_new->zcell_num = zcell_num;
+			p_rbkey_new->zreg_num = zreg_num;
+			p_hash_cfg->p_bulk_ddr_info[bulk_id] = p_rbkey_new;
+
+			ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "one new ddr_bulk init!\n");
+		}
+#ifdef DPP_FLOW_HW_INIT
+		rc = dpp_hash_tbl_crc_poly_write(p_hash_cfg->p_se_info,
+										 p_hash_cfg->fun_id, bulk_id,
+										 p_ddr_resc_cfg->ddr_crc_sel);
+		if (DPP_OK != rc) {
+			ZXIC_COMM_FREE(p_rbkey_new);
+			ZXIC_COMM_FREE(p_rb_tn_new);
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					dev_id,
+					"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",
+					__FILE__, __LINE__, rc, __FUNCTION__,
+					"dpp_hash_tbl_crc_poly_write");
+			return rc;
+		}
+
+		rc = dpp_hash_ext_cfg_write(p_hash_cfg->p_se_info, p_hash_cfg->fun_id,
+									bulk_id,
+									p_hash_cfg->p_bulk_ddr_info[bulk_id]);
+		if (DPP_OK != rc) {
+			ZXIC_COMM_FREE(p_rbkey_new);
+			ZXIC_COMM_FREE(p_rb_tn_new);
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					dev_id,
+					"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",
+					__FILE__, __LINE__, rc, __FUNCTION__,
+					"dpp_hash_ext_cfg_write");
+			return rc;
+		}
+		rc = dpp_hash_tbl_depth_write(p_hash_cfg->p_se_info, p_hash_cfg->fun_id,
+									  bulk_id,
+									  p_hash_cfg->p_bulk_ddr_info[bulk_id]);
+		if (DPP_OK != rc) {
+			ZXIC_COMM_FREE(p_rbkey_new);
+			ZXIC_COMM_FREE(p_rb_tn_new);
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					dev_id,
+					"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",
+					__FILE__, __LINE__, rc, __FUNCTION__,
+					"dpp_hash_tbl_depth_write");
+			return rc;
+		}
+#endif
+		rc = dpp_se_smmu1_hash_tbl_cfg_set(p_se_cfg->dev, p_hash_cfg->fun_id,
+										   bulk_id, p_ddr_resc_cfg->ddr_ecc_en,
+										   p_ddr_resc_cfg->ddr_baddr);
+		if (DPP_OK != rc) {
+			ZXIC_COMM_FREE(p_rbkey_new);
+			ZXIC_COMM_FREE(p_rb_tn_new);
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					dev_id,
+					"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",
+					__FILE__, __LINE__, rc, __FUNCTION__,
+					"dpp_se_smmu1_hash_tbl_cfg_set");
+			return rc;
+		}
+	}
+
+	p_bulk_zcam_mono = (DPP_HASH_BULK_ZCAM_STAT *)ZXIC_COMM_MALLOC(
+			sizeof(DPP_HASH_BULK_ZCAM_STAT));
+	if (NULL == (p_bulk_zcam_mono)) {
+		ZXIC_COMM_FREE(p_rbkey_new);
+		ZXIC_COMM_FREE(p_rb_tn_new);
+		ZXIC_COMM_FREE(p_item_array);
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id, "\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n",
+				__FILE__, __LINE__, __FUNCTION__);
+		return ZXIC_PAR_CHK_POINT_NULL;
+	}
+	ZXIC_COMM_MEMSET(p_bulk_zcam_mono, 0, sizeof(DPP_HASH_BULK_ZCAM_STAT));
+	(&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[bulk_id] = p_bulk_zcam_mono;
+
+	for (i = 0; i < SE_ZBLK_NUM * SE_ZCELL_NUM; i++) {
+		p_bulk_zcam_mono->zcell_mono_idx[i] = 0xffffffff;
+	}
+
+	for (i = 0; i < SE_ZBLK_NUM; i++) {
+		for (j = 0; j < SE_ZREG_NUM; j++) {
+			p_bulk_zcam_mono->zreg_mono_id[i][j].zblk_id = 0xffffffff;
+			p_bulk_zcam_mono->zreg_mono_id[i][j].zreg_id = 0xffffffff;
+		}
+	}
+
+	if (zcell_num > 0) {
+		p_hash_cfg->bulk_ram_mono[bulk_id] = 1;
+
+#ifdef DPP_FLOW_HW_INIT
+		rc = dpp_hash_bulk_mono_flags_write(p_se_cfg, fun_id, bulk_id);
+		if (DPP_OK != rc) {
+			ZXIC_COMM_FREE(p_rbkey_new);
+			ZXIC_COMM_FREE(p_rb_tn_new);
+			ZXIC_COMM_FREE(p_item_array);
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					dev_id,
+					"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",
+					__FILE__, __LINE__, rc, __FUNCTION__,
+					"dpp_hash_bulk_mono_flags_write");
+			return rc;
+		}
+#endif
+
+		/* 初始分配此业务表独占的zcell，只能在非独占的zcell中分配 */
+		/* p_zcell_free = &(p_hash_cfg->hash_shareram.zcell_free_list);*/
+		p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next;
+
+		i = 0;
+
+		while (p_zcell_dn) {
+			p_zcell_cfg = (SE_ZCELL_CFG *)p_zcell_dn->data;
+
+			if (p_zcell_cfg->is_used) {
+				if (!(p_zcell_cfg->flag & DPP_ZCELL_FLAG_IS_MONO)) {
+					p_zcell_cfg->flag |= DPP_ZCELL_FLAG_IS_MONO;
+					p_zcell_cfg->bulk_id = bulk_id;
+
+#ifdef DPP_FLOW_HW_INIT
+					rc = dpp_hash_zcell_mono_write(p_se_cfg,
+												   p_zcell_cfg); /* 写入硬件 */
+					if (DPP_OK != rc) {
+						ZXIC_COMM_FREE(p_rbkey_new);
+						ZXIC_COMM_FREE(p_rb_tn_new);
+						ZXIC_COMM_FREE(p_item_array);
+						ZXIC_COMM_TRACE_DEV_ERROR(
+								dev_id,
+								"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",
+								__FILE__, __LINE__, rc, __FUNCTION__,
+								"dpp_hash_zcell_mono_write");
+						return rc;
+					}
+#endif
+
+					ZXIC_COMM_CHECK_DEV_INDEX(dev_id, p_zcell_cfg->zcell_idx, 0,
+											  SE_ZCELL_TOTAL_NUM - 1);
+					p_bulk_zcam_mono->zcell_mono_idx[p_zcell_cfg->zcell_idx] =
+							p_zcell_cfg->zcell_idx; /* 统计独占的zcell */
+
+					if (++i >= zcell_num) {
+						break;
+					}
+				}
+			} else {
+				ZXIC_COMM_TRACE_DEV_ERROR(
+						dev_id, "zcell[ %d ] is not init before used!\n",
+						p_zcell_cfg->zcell_idx);
+				ZXIC_COMM_ASSERT(0);
+				return DPP_HASH_RC_INVALID_PARA;
+			}
+
+			p_zcell_dn = p_zcell_dn->next;
+		}
+
+		if (i < zcell_num) {
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					dev_id,
+					"Input param 'zcell_num' is [ %d ], actually bulk[ %d ]monopolize zcells is [ %d ]!\n",
+					zcell_num, bulk_id, i);
+		}
+	}
+
+	if (zreg_num > 0) {
+		p_hash_cfg->bulk_ram_mono[bulk_id] = 1;
+
+#ifdef DPP_FLOW_HW_INIT
+		rc = dpp_hash_bulk_mono_flags_write(p_se_cfg, fun_id, bulk_id);
+		if (DPP_OK != rc) {
+			ZXIC_COMM_FREE(p_rbkey_new);
+			ZXIC_COMM_FREE(p_rb_tn_new);
+			ZXIC_COMM_FREE(p_item_array);
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					dev_id,
+					"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",
+					__FILE__, __LINE__, rc, __FUNCTION__,
+					"dpp_hash_bulk_mono_flags_write");
+			return rc;
+		}
+#endif
+		/*        p_tbl_id_info->zreg_num= zreg_num;*/
+
+		/* 初始分配此业务表独占的zreg，只能在非独占的zreg中分配 */
+		/*        p_zblk_free = &(p_hash_cfg->hash_shareram.zblk_list);*/
+		p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next;
+		j = 0;
+
+		while (p_zblk_dn) {
+			p_zblk_cfg = (SE_ZBLK_CFG *)p_zblk_dn->data;
+			zblk_idx = p_zblk_cfg->zblk_idx;
+			ZXIC_COMM_CHECK_DEV_INDEX(dev_id, zblk_idx, 0, SE_ZBLK_NUM - 1);
+
+			if (p_zblk_cfg->is_used) {
+				for (i = 0; i < SE_ZREG_NUM; i++) {
+					p_zreg_cfg = &(p_zblk_cfg->zreg_info[i]);
+
+					if (!(p_zreg_cfg->flag & DPP_ZREG_FLAG_IS_MONO)) {
+						p_zreg_cfg->flag = DPP_ZREG_FLAG_IS_MONO;
+						p_zreg_cfg->bulk_id = bulk_id;
+#ifdef DPP_FLOW_HW_INIT
+						rc = dpp_hash_zreg_mono_write(
+								p_se_cfg, bulk_id, zblk_idx, i); /* 写入硬件 */
+						if (DPP_OK != rc) {
+							ZXIC_COMM_FREE(p_rbkey_new);
+							ZXIC_COMM_FREE(p_rb_tn_new);
+							ZXIC_COMM_FREE(p_item_array);
+							ZXIC_COMM_TRACE_DEV_ERROR(
+									dev_id,
+									"\n ICM  %s:%d [ErrorCode:0x%x] !-- %s Call %s Fail!\n",
+									__FILE__, __LINE__, rc, __FUNCTION__,
+									"dpp_hash_zreg_mono_write");
+							return rc;
+						}
+#endif
+						p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zblk_id =
+								zblk_idx;
+						p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zreg_id = i;
+
+						if (++j >= zreg_num) {
+							break;
+						}
+					}
+				}
+
+				if (j >= zreg_num) {
+					break;
+				}
+			} else {
+				ZXIC_COMM_TRACE_DEV_ERROR(
+						dev_id, "zblk [ %d ] is not init before used!\n",
+						p_zblk_cfg->zblk_idx);
+				ZXIC_COMM_ASSERT(0);
+				return DPP_HASH_RC_INVALID_PARA;
+			}
+
+			p_zblk_dn = p_zblk_dn->next;
+		}
+
+		if (j < zreg_num) {
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					dev_id,
+					"Input param 'zreg_num' is [ %d ], actually bulk[ %d ]monopolize zregs is [ %d ]!\n",
+					zreg_num, bulk_id, j);
+		}
+	}
+
+	/** for 软复位 */
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(fun_id, 0, 3);
+	ZXIC_COMM_CHECK_INDEX(bulk_id, 0, 7);
+	g_hash_store_dat[dev_id].ddr_item_num[fun_id][bulk_id] =
+			p_ddr_resc_cfg->ddr_item_num;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 初始化单个hash引擎内的某个业务表，此接口支持为该业务表分配独占的zcell。
+ *   必须先初始化hash引擎，如果是片内+片外模式还必须先初始化dpp_hash_ddr_bulk_init，
+ *   再初始化业务表。
+ * @param   p_se_cfg        算法模块公共管理数据结构指针
+ * @param   fun_id          hash引擎号
+ * @param   tbl_id          业务表
+ * @param   tbl_flag        初始化标记, bitmap的形式使用，如:HASH_TBL_FLAG_AGE等
+ * @param   key_type        hash条目类型，取值参照DPP_HASH_KEY_TYPE的定义
+ * @param   actu_key_size   业务键值有效长度: 8bit*N，N=1~48
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2015/05/15
+ ************************************************************/
+DPP_STATUS dpp_hash_tbl_id_info_init(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id,
+									 ZXIC_UINT32 tbl_id, ZXIC_UINT32 tbl_flag,
+									 ZXIC_UINT32 key_type,
+									 ZXIC_UINT32 actu_key_size)
+{
+	ZXIC_UINT32 key_by_size = 0;
+	ZXIC_UINT32 entry_size = 0;
+
+	ZXIC_UINT32 dev_id = 0;
+
+	DPP_HASH_TBL_ID_INFO *p_tbl_id_info = NULL;
+
+	ZXIC_COMM_CHECK_INDEX(tbl_id, 0, HASH_TBL_ID_NUM - 1);
+	ZXIC_COMM_CHECK_INDEX(fun_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1);
+	ZXIC_COMM_CHECK_INDEX(actu_key_size, HASH_ACTU_KEY_MIN, HASH_ACTU_KEY_MAX);
+	ZXIC_COMM_CHECK_INDEX(key_type, HASH_KEY_128b, HASH_KEY_512b);
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
+
+	dev_id = p_se_cfg->dev_id;
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
+	key_by_size = DPP_GET_KEY_SIZE(actu_key_size);
+	entry_size = DPP_GET_HASH_ENTRY_SIZE(key_type);
+
+	if (key_by_size > entry_size) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id,
+				"ErrorCode[%x]: actu_key_size[%d] not match to key_type[%d].\n",
+				DPP_HASH_RC_INVALID_PARA, key_by_size, entry_size);
+		ZXIC_COMM_ASSERT(0);
+		return DPP_HASH_RC_INVALID_PARA;
+	}
+
+	p_tbl_id_info = GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id);
+
+	if (p_tbl_id_info->is_init) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id,
+				"fun_id[%d],table_id[%d] is already init, do not init again!\n",
+				fun_id, tbl_id);
+		return DPP_HASH_RC_REPEAT_INIT;
+	}
+
+	p_tbl_id_info->fun_id = fun_id;
+	p_tbl_id_info->actu_key_size = actu_key_size;
+	p_tbl_id_info->key_type = key_type;
+	p_tbl_id_info->is_init = 1;
+
+	if (tbl_flag & HASH_TBL_FLAG_AGE) {
+		p_tbl_id_info->is_age = 1;
+	}
+
+	if (tbl_flag & HASH_TBL_FLAG_LEARN) {
+		p_tbl_id_info->is_lrn = 1;
+	}
+
+	if (tbl_flag & HASH_TBL_FLAG_MC_WRT) {
+		p_tbl_id_info->is_mc_wrt = 1;
+	}
+
+	return DPP_OK;
+}
+
+DPP_STATUS dpp_hash_red_black_node_alloc(DPP_DEV_T *dev,
+										 ZXIC_RB_TN **p_rb_tn_new,
+										 DPP_HASH_RBKEY_INFO **p_rbkey_new)
+{
+	ZXIC_RB_TN *p_rb_tn_new_temp = NULL;
+	DPP_HASH_RBKEY_INFO *p_rbkey_new_temp = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	/** red&black key*/
+	p_rbkey_new_temp = (DPP_HASH_RBKEY_INFO *)ZXIC_COMM_MALLOC(
+			sizeof(DPP_HASH_RBKEY_INFO));
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_rbkey_new_temp);
+	ZXIC_COMM_MEMSET(p_rbkey_new_temp, 0, sizeof(DPP_HASH_RBKEY_INFO));
+
+	/** red&black tree node*/
+	p_rb_tn_new_temp = (ZXIC_RB_TN *)ZXIC_COMM_MALLOC(sizeof(ZXIC_RB_TN));
+	if (NULL == p_rb_tn_new_temp) {
+		ZXIC_COMM_FREE(p_rbkey_new_temp);
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev),
+				"\n ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!\n", __FILE__,
+				__LINE__, __FUNCTION__);
+		return ZXIC_PAR_CHK_POINT_NULL;
+	}
+
+	INIT_RBT_TN(p_rb_tn_new_temp, p_rbkey_new_temp);
+
+	*p_rb_tn_new = p_rb_tn_new_temp;
+	*p_rbkey_new = p_rbkey_new_temp;
+
+	return DPP_OK;
+}
+
+DPP_STATUS dpp_hash_get_hash_info_from_sdt(ZXIC_UINT32 dev_id,
+										   ZXIC_UINT32 sdt_no,
+										   HASH_ENTRY_CFG *p_hash_entry_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+	FUNC_ID_INFO *p_func_info = NULL;
+	DPP_SE_CFG *p_se_cfg = NULL;
+
+	DPP_SDTTBL_HASH_T sdt_hash_info = { 0 }; /*SDT内容*/
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, sdt_no, 0, DPP_DEV_SDT_ID_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_hash_entry_cfg);
+
+	//从sdt_no中获取SDT配置
+	rc = dpp_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash_info);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_read");
+
+	p_hash_entry_cfg->fun_id = sdt_hash_info.hash_id; /*hash引擎*/
+	ZXIC_COMM_CHECK_INDEX(p_hash_entry_cfg->fun_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1);
+
+	p_hash_entry_cfg->table_id = sdt_hash_info.hash_table_id; /*hash表号*/
+	ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->table_id, HASH_TBL_ID_NUM - 1);
+
+	p_hash_entry_cfg->bulk_id = ((p_hash_entry_cfg->table_id >> 2) & 0x7);
+	ZXIC_COMM_CHECK_INDEX_UPPER(p_hash_entry_cfg->bulk_id, HASH_BULK_NUM - 1);
+
+	p_hash_entry_cfg->key_type = sdt_hash_info.hash_table_width; /*表宽度*/
+	ZXIC_COMM_CHECK_INDEX(p_hash_entry_cfg->key_type, HASH_KEY_128b, HASH_KEY_512b);
+
+	p_hash_entry_cfg->actu_key_size = sdt_hash_info.key_size; /*业务表键值长度*/
+	ZXIC_COMM_CHECK_INDEX(p_hash_entry_cfg->actu_key_size, HASH_ACTU_KEY_MIN, HASH_ACTU_KEY_MAX);
+	p_hash_entry_cfg->key_by_size = DPP_GET_KEY_SIZE(p_hash_entry_cfg->actu_key_size);
+	p_hash_entry_cfg->rst_by_size = DPP_GET_RST_SIZE(p_hash_entry_cfg->key_type, p_hash_entry_cfg->actu_key_size);
+
+	/* 取出se配置 */
+	rc = dpp_se_cfg_get(dev_id, &p_se_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_cfg_get");
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg);
+	p_hash_entry_cfg->p_se_cfg = p_se_cfg;
+
+	p_func_info = DPP_GET_FUN_INFO(p_se_cfg, p_hash_entry_cfg->fun_id);
+	DPP_SE_CHECK_FUN(p_func_info, p_hash_entry_cfg->fun_id, FUN_HASH);
+
+	p_hash_entry_cfg->p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_hash_entry_cfg->p_hash_cfg);
+
+	return DPP_OK;
+}
+
+DPP_STATUS dpp_hash_rb_insert(DPP_DEV_T *dev, HASH_ENTRY_CFG *p_hash_entry_cfg,
+							  DPP_HASH_ENTRY *p_entry)
+{
+	ZXIC_UINT32 rc = DPP_OK;
+	DPP_HASH_RBKEY_INFO *p_rbkey_rtn = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	DPP_HASH_RBKEY_INFO *p_rbkey_new = NULL;
+	ZXIC_RB_TN *p_rb_tn_new = NULL;
+	ZXIC_RB_TN *p_rb_tn_rtn = NULL;
+	ZXIC_UINT32 rst_actual_size = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg->p_hash_cfg);
+	ZXIC_COMM_CHECK_POINT(p_entry);
+	ZXIC_COMM_CHECK_POINT(p_entry->p_rst);
+
+	p_rbkey_new = p_hash_entry_cfg->p_rbkey_new;
+	p_rb_tn_new = p_hash_entry_cfg->p_rb_tn_new;
+	p_hash_cfg = p_hash_entry_cfg->p_hash_cfg;
+	rst_actual_size = ((p_hash_entry_cfg->rst_by_size) > HASH_RST_MAX) ?
+	HASH_RST_MAX :
+	p_hash_entry_cfg->rst_by_size;
+	rc = zxic_comm_rb_insert(&p_hash_cfg->hash_rb, (ZXIC_VOID *)p_rb_tn_new,
+	(ZXIC_VOID *)(&p_rb_tn_rtn));
+	if (ZXIC_RBT_RC_FULL == rc) {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "The red black tree is full!\n");
+		ZXIC_COMM_FREE(p_rbkey_new);
+		ZXIC_COMM_FREE(p_rb_tn_new);
+		ZXIC_COMM_ASSERT(0);
+		return DPP_HASH_RC_RB_TREE_FULL;
+	} else if (ZXIC_RBT_RC_UPDATE == rc) {
+		p_hash_cfg->hash_stat.insert_same++;
+		ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "Hash update exist entry!\n");
+
+		ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_rb_tn_rtn);
+		p_rbkey_rtn = (DPP_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key);
+
+		/* when the result is more than 256bit, get first 256bit valid data. */
+		ZXIC_COMM_MEMCPY(p_rbkey_rtn->rst, p_entry->p_rst, rst_actual_size);
+
+		ZXIC_COMM_FREE(p_rbkey_new);
+		ZXIC_COMM_FREE(p_rb_tn_new);
+		p_hash_entry_cfg->p_rbkey_new = p_rbkey_rtn;
+		p_hash_entry_cfg->p_rb_tn_new = p_rb_tn_rtn;
+
+		return DPP_HASH_RC_ADD_UPDATE;
+	} else {
+		ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "Hash insert new entry!\n");
+		/* when the result is more than 256bit, get first 256bit valid data. */
+		ZXIC_COMM_MEMCPY(p_rbkey_new->rst, p_entry->p_rst, rst_actual_size);
+		p_rbkey_new->entry_size = DPP_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type);
+		INIT_D_NODE(&p_rbkey_new->entry_dn, p_rbkey_new);
+	}
+
+	return DPP_OK;
+}
+
+DPP_STATUS dpp_hash_set_crc_key(DPP_DEV_T *dev,
+								HASH_ENTRY_CFG *p_hash_entry_cfg,
+								DPP_HASH_ENTRY *p_entry, ZXIC_UINT8 *p_temp_key)
+{
+	ZXIC_UINT32 key_by_size = 0;
+	ZXIC_UINT8 temp_tbl_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
+	ZXIC_COMM_CHECK_POINT(p_entry);
+	ZXIC_COMM_CHECK_POINT(p_entry->p_key);
+	ZXIC_COMM_CHECK_POINT(p_temp_key);
+
+	key_by_size = p_hash_entry_cfg->key_by_size;
+	ZXIC_COMM_MEMCPY(p_temp_key, p_entry->p_key, key_by_size);
+
+	/* 约定: 参与CRC运算的key, 需要将tbl_id的前面补3bit的0，然后放到actu_key的后面. */
+	temp_tbl_id = (*p_temp_key) & 0x1F;
+	memmove(p_temp_key, p_temp_key + 1, key_by_size - HASH_KEY_CTR_SIZE);
+	ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(DEV_ID(dev), key_by_size, HASH_KEY_CTR_SIZE);
+	p_temp_key[key_by_size - HASH_KEY_CTR_SIZE] = temp_tbl_id;
+
+	return DPP_OK;
+}
+
+DPP_STATUS dpp_hash_insert_ddr(DPP_DEV_T *dev, HASH_ENTRY_CFG *p_hash_entry_cfg,
+							   ZXIC_UINT8 *p_temp_key, ZXIC_UINT8 *p_end_flag)
+{
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	ZXIC_UINT8 bulk_id = 0;
+	ZXIC_UINT8 key_type = 0;
+	ZXIC_UINT8 table_id = 0;
+	ZXIC_UINT32 key_by_size = 0;
+	ZXIC_UINT32 crc_value = 0;
+	ZXIC_UINT32 item_idx = 0xFFFFFFFF; /* -1 */
+	ZXIC_UINT32 item_type = 0;
+	HASH_DDR_CFG *p_ddr_cfg = NULL;
+	SE_ITEM_CFG *p_item = NULL;
+	DPP_HASH_RBKEY_INFO *p_rbkey_new = NULL;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
+	ZXIC_COMM_CHECK_POINT(p_temp_key);
+	ZXIC_COMM_CHECK_POINT(p_end_flag);
+
+	p_hash_cfg = p_hash_entry_cfg->p_hash_cfg;
+	ZXIC_COMM_CHECK_POINT(p_hash_cfg);
+	bulk_id = p_hash_entry_cfg->bulk_id;
+	ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id, HASH_BULK_NUM - 1);
+	p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id];
+	ZXIC_COMM_CHECK_POINT(p_ddr_cfg);
+	table_id = p_hash_entry_cfg->table_id;
+	ZXIC_COMM_CHECK_INDEX_UPPER(table_id, HASH_TBL_ID_NUM - 1);
+	p_rbkey_new = p_hash_entry_cfg->p_rbkey_new;
+	ZXIC_COMM_CHECK_POINT(p_rbkey_new);
+
+	key_type = p_hash_entry_cfg->key_type;
+	if ((HASH_KEY_512b == key_type) &&
+		(DDR_WIDTH_256b == p_ddr_cfg->width_mode)) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev),
+				"ErrorCode[0x%x]: Hash DDR width mode is not match to the key type.\n",
+				DPP_HASH_RC_DDR_WIDTH_MODE_ERR);
+		return DPP_HASH_RC_DDR_WIDTH_MODE_ERR;
+	}
+
+	key_by_size = p_hash_entry_cfg->key_by_size;
+	crc_value = p_hash_cfg->p_hash32_fun(p_temp_key, key_by_size,
+	p_ddr_cfg->hash_ddr_arg);
+	ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev),
+	"hash ddr arg is: 0x%x.crc_value is 0x%x\n",
+	p_ddr_cfg->hash_ddr_arg, crc_value); /* t */
+	item_idx = crc_value % p_ddr_cfg->item_num; /*按照256bit进行划分*/
+	item_type = ITEM_DDR_256;
+	if (DDR_WIDTH_512b == p_ddr_cfg->width_mode) {
+		item_idx = crc_value%p_ddr_cfg->item_num; /* 512b模式时，item_num已经在bulk初始化做过转换 ，按照512bit进行划分*/
+		item_type = ITEM_DDR_512;
+	}
+
+	ZXIC_COMM_TRACE_DEV_DEBUG(
+			DEV_ID(dev), "Hash insert in ITEM_DDR_%s, item_idx is: 0x%x.\n",
+			((item_type == ITEM_DDR_256) ? "256" : "512"), item_idx);
+
+	ZXIC_COMM_CHECK_INDEX_UPPER(
+	item_idx,
+	p_ddr_cfg->item_num); /* modify coverity yinxh 2021.03.10*/
+	p_item = p_ddr_cfg->p_item_array[item_idx];
+	if (NULL == p_item) {
+		p_item = (SE_ITEM_CFG *)ZXIC_COMM_MALLOC(sizeof(SE_ITEM_CFG));
+		ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_item);
+		ZXIC_COMM_MEMSET(p_item, 0, sizeof(SE_ITEM_CFG));
+		p_ddr_cfg->p_item_array[item_idx] = p_item;
+	}
+
+	rc = dpp_hash_insrt_to_item(p_hash_cfg, p_hash_entry_cfg->p_rbkey_new,
+								p_item, item_idx, item_type, key_type);
+
+	if (DPP_HASH_RC_ITEM_FULL != rc) {
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_insrt_to_item");
+		*p_end_flag = 1;
+#ifdef HASH_ENTRY_STAT
+		p_hash_cfg->hash_stat.insert_ddr++;
+		p_hash_cfg->hash_stat.insert_table[table_id].ddr++;
+#endif
+		/* calc the item hardware address in DDR */
+		ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), p_ddr_cfg->hw_baddr, item_idx);
+		p_item->hw_addr = GET_HASH_DDR_HW_ADDR(p_ddr_cfg->hw_baddr, item_idx);
+		p_item->bulk_id = p_hash_entry_cfg->bulk_id;
+	}
+
+	return DPP_OK;
+}
+
+DPP_STATUS dpp_hash_insert_zcell(DPP_DEV_T *dev, DPP_SE_CFG *p_se_cfg,
+								 HASH_ENTRY_CFG *p_hash_entry_cfg,
+								 ZXIC_UINT8 *p_temp_key, ZXIC_UINT8 *p_end_flag)
+{
+	ZXIC_UINT8 bulk_id = 0;
+	D_NODE *p_zcell_dn = NULL;
+	SE_ZCELL_CFG *p_zcell = NULL;
+	ZXIC_UINT32 zblk_idx = 0;
+	ZXIC_UINT32 zcell_id = 0;
+	ZXIC_UINT32 pre_zblk_idx = 0xFFFFFFFF; /* -1; */
+	SE_ITEM_CFG *p_item = NULL;
+	ZXIC_UINT32 item_idx = 0xFFFFFFFF; /* -1 */
+	ZXIC_UINT32 item_type = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 crc_value = 0;
+	ZXIC_UINT8 table_id = 0;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	SE_ZBLK_CFG *p_zblk = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
+	ZXIC_COMM_CHECK_POINT(p_temp_key);
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	ZXIC_COMM_CHECK_POINT(p_end_flag);
+
+	/* if insert into DDR is fail, insert into ZCAM. */
+	ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "insert zcell start\n");
+	bulk_id = p_hash_entry_cfg->bulk_id;
+	ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id, HASH_BULK_NUM - 1);
+	table_id = p_hash_entry_cfg->table_id;
+	ZXIC_COMM_CHECK_INDEX_UPPER(table_id, HASH_TBL_ID_NUM - 1);
+	p_hash_cfg = p_hash_entry_cfg->p_hash_cfg;
+	ZXIC_COMM_CHECK_POINT(p_hash_cfg);
+	p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next;
+
+	while (p_zcell_dn) {
+		p_zcell = (SE_ZCELL_CFG *)p_zcell_dn->data;
+		ZXIC_COMM_CHECK_POINT(p_zcell);
+
+		/* 只在hash引擎开启zcell独占模式下，才进行相关的处理 */
+		if (((p_zcell->flag & DPP_ZCELL_FLAG_IS_MONO) &&
+			 (p_zcell->bulk_id != bulk_id)) ||
+			((!(p_zcell->flag & DPP_ZCELL_FLAG_IS_MONO)) &&
+			 (p_hash_cfg->bulk_ram_mono[bulk_id]))) {
+			p_zcell_dn = p_zcell_dn->next;
+			continue;
+		}
+
+		zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx);
+		ZXIC_COMM_CHECK_INDEX_UPPER(zblk_idx, SE_ZBLK_NUM - 1);
+		p_zblk = &(p_se_cfg->zblk_info[zblk_idx]);
+		if (zblk_idx != pre_zblk_idx) {
+			pre_zblk_idx = zblk_idx;
+			crc_value = p_hash_cfg->p_hash16_fun(p_temp_key,
+												 p_hash_entry_cfg->key_by_size,
+												 p_zblk->hash_arg);
+		}
+
+		ZXIC_COMM_TRACE_DEV_DEBUG(
+				DEV_ID(dev),
+				"zblk_idx is [0x%x],p_zblk->hash_arg is [0x%x],crc_value is [0x%x]\n",
+				zblk_idx, p_zblk->hash_arg, crc_value); /* t */
+
+		zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx);
+		item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc_value);
+		ZXIC_COMM_CHECK_INDEX_UPPER(item_idx, SE_RAM_DEPTH - 1);
+		p_item = &(p_zcell->item_info[item_idx]);
+		item_type = ITEM_RAM;
+
+		ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev),
+								  "zcell_id is [0x%x],item_idx is [0x%x]\n",
+								  zcell_id, item_idx); /* t */
+
+		rc = dpp_hash_insrt_to_item(p_hash_cfg, p_hash_entry_cfg->p_rbkey_new,
+									p_item, item_idx, item_type,
+									p_hash_entry_cfg->key_type);
+
+		if (DPP_HASH_RC_ITEM_FULL == rc) {
+			ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev),
+									  "The item is full, check next. \n");
+		} else {
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_hash_insrt_to_item");
+			*p_end_flag = 1;
+#ifdef HASH_ENTRY_STAT
+			p_hash_cfg->hash_stat.insert_zcell++;
+			p_hash_cfg->hash_stat.insert_table[table_id].zcell++;
+#endif
+
+			/* calc the item hardware address in ZCAM. */
+			p_item->hw_addr = ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx);
+			/*                debug start 获取冲突键值*/
+			/*                ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "ZCAM hw_addr is [0x%x]\n", p_item->hw_addr); t*/
+			/*                ZXIC_COMM_PRINT("after ddr conflict item_idx is:%d,p_item->hw_addr is:%d \n", item_idx,
+	* p_item->hw_addr);*/
+			/*                ZXIC_COMM_PRINT("after ddr conflict zcell_id is [0x%x],zblk_idx is [0x%x]\n", zcell_id,
+	* zblk_idx); t;*/
+			/*                debug end*/
+			break;
+		}
+
+		p_zcell_dn = p_zcell_dn->next;
+	}
+
+	return DPP_OK;
+}
+
+DPP_STATUS dpp_hash_insert_zreg(DPP_DEV_T *dev,
+								HASH_ENTRY_CFG *p_hash_entry_cfg,
+								ZXIC_UINT8 *p_temp_key, ZXIC_UINT8 *p_end_flag)
+{
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	D_NODE *p_zblk_dn = NULL;
+	SE_ZBLK_CFG *p_zblk = NULL;
+	SE_ZREG_CFG *p_zreg = NULL;
+	SE_ITEM_CFG *p_item = NULL;
+	ZXIC_UINT8 reg_index = 0;
+	ZXIC_UINT32 zblk_idx = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT8 bulk_id = 0;
+	ZXIC_UINT32 item_idx = 0xFFFFFFFF; /* -1; */
+	ZXIC_UINT32 item_type = 0;
+	ZXIC_UINT32 table_id = 0;
+	DPP_HASH_RBKEY_INFO *p_rbkey_new = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_hash_entry_cfg);
+	ZXIC_COMM_CHECK_POINT(p_temp_key);
+	ZXIC_COMM_CHECK_POINT(p_end_flag);
+
+	ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "insert zreg start\n"); /* t */
+	bulk_id = p_hash_entry_cfg->bulk_id;
+	ZXIC_COMM_CHECK_INDEX_UPPER(bulk_id, HASH_BULK_NUM - 1);
+	table_id = p_hash_entry_cfg->table_id;
+	ZXIC_COMM_CHECK_INDEX_UPPER(table_id, HASH_TBL_ID_NUM - 1);
+	p_rbkey_new = p_hash_entry_cfg->p_rbkey_new;
+	ZXIC_COMM_CHECK_POINT(p_rbkey_new);
+
+	p_hash_cfg = p_hash_entry_cfg->p_hash_cfg;
+	p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next;
+	while (p_zblk_dn) {
+		p_zblk = (SE_ZBLK_CFG *)p_zblk_dn->data;
+		zblk_idx = p_zblk->zblk_idx;
+
+		for (reg_index = 0; reg_index < SE_ZREG_NUM; reg_index++) {
+			p_zreg = &(p_zblk->zreg_info[reg_index]);
+
+			if (((p_zreg->flag & DPP_ZREG_FLAG_IS_MONO) &&
+				 (p_zreg->bulk_id != bulk_id)) ||
+				((!(p_zreg->flag & DPP_ZREG_FLAG_IS_MONO)) &&
+				 (p_hash_cfg->bulk_ram_mono[bulk_id]))) {
+				continue;
+			}
+
+			p_item = &(p_zblk->zreg_info[reg_index].item_info);
+			item_type = ITEM_REG;
+			item_idx = reg_index;
+			rc = dpp_hash_insrt_to_item(p_hash_cfg,
+										p_hash_entry_cfg->p_rbkey_new, p_item,
+										item_idx, item_type,
+										p_hash_entry_cfg->key_type);
+
+			if (DPP_HASH_RC_ITEM_FULL == rc) {
+				ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev),
+										  "The item is full, check next. \n");
+			} else {
+				ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+									   "dpp_hash_insrt_to_item");
+				*p_end_flag = 1;
+#ifdef HASH_ENTRY_STAT
+				p_hash_cfg->hash_stat.insert_zreg++;
+				p_hash_cfg->hash_stat.insert_table[table_id].zreg++;
+#endif
+
+				/* calc the item hardware address in ZBLK Reg. */
+				p_item->hw_addr =
+						ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, reg_index);
+				break;
+			}
+		}
+
+		if (*p_end_flag) {
+			break;
+		}
+
+		p_zblk_dn = p_zblk_dn->next;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**
+ * @param   p_se_cfg  算法模块公共管理数据结构指针
+ * @param   fun_id      hash引擎号
+ * @param   p_zblk_cfg
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XCX      @date  2017/03/27
+ ************************************************************/
+DPP_STATUS dpp_hash_zblkcfg_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id,
+								  SE_ZBLK_CFG *p_zblk_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT8 ram_buf[SE_RAM_WIDTH / 8] = { 0 };
+
+	ZXIC_UINT32 dev_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	ZXIC_COMM_CHECK_POINT(p_zblk_cfg);
+	ZXIC_COMM_CHECK_INDEX(fun_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1);
+
+	dev_id = p_se_cfg->dev_id;
+
+	/* write hash type*/
+	rc = zxic_comm_write_bits_ex(
+			ram_buf, SE_RAM_WIDTH, 1, DPP_SE_ZBLK_SERVICE_TYPE_START,
+			DPP_SE_ZBLK_SERVICE_TYPE_START - DPP_SE_ZBLK_SERVICE_TYPE_END + 1);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_write_bits_ex");
+
+	/* write hash channel*/
+	rc = zxic_comm_write_bits_ex(
+			ram_buf, SE_RAM_WIDTH, fun_id, DPP_SE_ZBLK_HASH_CHAN_START,
+			DPP_SE_ZBLK_HASH_CHAN_START - DPP_SE_ZBLK_HASH_CHAN_END + 1);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_write_bits_ex");
+
+	/* write enable flag*/
+	rc = zxic_comm_write_bits_ex(
+			ram_buf, SE_RAM_WIDTH, 1, DPP_SE_ZBLK_HW_POS_EN_START,
+			DPP_SE_ZBLK_HW_POS_EN_START - DPP_SE_ZBLK_HW_POS_EN_END + 1);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_write_bits_ex");
+
+#ifdef DPP_FLOW_HW_INIT
+	rc = dpp_se_zblk_serv_cfg_set(p_se_cfg->dev, p_zblk_cfg->zblk_idx,
+								  ALG_ZBLK_SERV_HASH, fun_id, 1);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_zblk_serv_cfg_set");
+#endif
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**
+ * @param   p_se_cfg  算法模块公共管理数据结构指针
+ * @param   hash_id   hash引擎号
+ * @param   bulk_id
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XCX      @date  2017/03/27
+ ************************************************************/
+DPP_STATUS dpp_hash_bulk_mono_flags_write(DPP_SE_CFG *p_se_cfg,
+										  ZXIC_UINT32 hash_id,
+										  ZXIC_UINT32 bulk_id)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 hash0_mono_flag = 0;
+	ZXIC_UINT32 hash1_mono_flag = 0;
+	ZXIC_UINT32 hash2_mono_flag = 0;
+	ZXIC_UINT32 hash3_mono_flag = 0;
+
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	ZXIC_COMM_CHECK_INDEX(hash_id, HASH_FUNC_ID_MIN, HASH_FUNC_ID_NUM - 1);
+	ZXIC_COMM_CHECK_INDEX(bulk_id, HASH_BULK_ID_MIN, HASH_BULK_ID_MAX);
+
+	dev_id = p_se_cfg->dev_id;
+
+	rc = dpp_se_hash_zcam_mono_flags_get(p_se_cfg->dev, &hash0_mono_flag,
+										 &hash1_mono_flag, &hash2_mono_flag,
+										 &hash3_mono_flag);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_zcam_mono_flags_get");
+
+	switch (hash_id) {
+	case 0: {
+		hash0_mono_flag |= (1U << bulk_id);
+		break;
+	}
+
+	case 1: {
+		hash1_mono_flag |= (1U << bulk_id);
+		break;
+	}
+
+	case 2: {
+		hash2_mono_flag |= (1U << bulk_id);
+		break;
+	}
+
+	case 3: {
+		hash3_mono_flag |= (1U << bulk_id);
+		break;
+	}
+
+	default: {
+		ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n hash id is out of rang.");
+		ZXIC_COMM_ASSERT(0);
+	}
+	}
+
+	rc = dpp_se_hash_zcam_mono_flags_set(p_se_cfg->dev, hash0_mono_flag,
+										 hash1_mono_flag, hash2_mono_flag,
+										 hash3_mono_flag);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_zcam_mono_flags_set");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**
+ * @param   p_se_cfg  算法模块公共管理数据结构指针
+ * @param   p_zcell_cfg
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XCX      @date  2017/03/27
+ ************************************************************/
+DPP_STATUS dpp_hash_zcell_mono_write(DPP_SE_CFG *p_se_cfg,
+									 SE_ZCELL_CFG *p_zcell_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 zblk_idx = 0;
+	ZXIC_UINT32 zcell_id = 0;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 zcell0_bulk_id = 0;
+	ZXIC_UINT32 zcell0_mono_flag = 0;
+	ZXIC_UINT32 zcell1_bulk_id = 0;
+	ZXIC_UINT32 zcell1_mono_flag = 0;
+	ZXIC_UINT32 zcell2_bulk_id = 0;
+	ZXIC_UINT32 zcell2_mono_flag = 0;
+	ZXIC_UINT32 zcell3_bulk_id = 0;
+	ZXIC_UINT32 zcell3_mono_flag = 0;
+
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	ZXIC_COMM_CHECK_POINT(p_zcell_cfg);
+
+	dev_id = p_se_cfg->dev_id;
+
+	zblk_idx = GET_ZBLK_IDX(p_zcell_cfg->zcell_idx);
+	zcell_id = p_zcell_cfg->zcell_idx & 0x3;
+	rc = dpp_se_zcell_mono_cfg_get(p_se_cfg->dev, zblk_idx, &zcell0_bulk_id,
+								   &zcell0_mono_flag, &zcell1_bulk_id,
+								   &zcell1_mono_flag, &zcell2_bulk_id,
+								   &zcell2_mono_flag, &zcell3_bulk_id,
+								   &zcell3_mono_flag);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_zcell_mono_cfg_get");
+
+	switch (zcell_id) {
+	case 0: {
+		zcell0_bulk_id = p_zcell_cfg->bulk_id;
+		zcell0_mono_flag = 1;
+		break;
+	}
+
+	case 1: {
+		zcell1_bulk_id = p_zcell_cfg->bulk_id;
+		zcell1_mono_flag = 1;
+		break;
+	}
+
+	case 2: {
+		zcell2_bulk_id = p_zcell_cfg->bulk_id;
+		zcell2_mono_flag = 1;
+		break;
+	}
+
+	case 3: {
+		zcell3_bulk_id = p_zcell_cfg->bulk_id;
+		zcell3_mono_flag = 1;
+		break;
+	}
+	}
+
+	rc = dpp_se_zcell_mono_cfg_set(p_se_cfg->dev, zblk_idx, zcell0_bulk_id,
+								   zcell0_mono_flag, zcell1_bulk_id,
+								   zcell1_mono_flag, zcell2_bulk_id,
+								   zcell2_mono_flag, zcell3_bulk_id,
+								   zcell3_mono_flag);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_zcell_mono_cfg_set");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**
+ * @param   p_se_cfg  算法模块公共管理数据结构指针
+ * @param   bulk_id
+ * @param   zblk_idx
+ * @param   zreg_id
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  XCX      @date  2017/03/27
+ ************************************************************/
+DPP_STATUS dpp_hash_zreg_mono_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 bulk_id,
+									ZXIC_UINT32 zblk_idx, ZXIC_UINT32 zreg_id)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 zreg0_bulk_id = 0;
+	ZXIC_UINT32 zreg0_mono_flag = 0;
+	ZXIC_UINT32 zreg1_bulk_id = 0;
+	ZXIC_UINT32 zreg1_mono_flag = 0;
+	ZXIC_UINT32 zreg2_bulk_id = 0;
+	ZXIC_UINT32 zreg2_mono_flag = 0;
+	ZXIC_UINT32 zreg3_bulk_id = 0;
+	ZXIC_UINT32 zreg3_mono_flag = 0;
+
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
+
+	dev_id = p_se_cfg->dev_id;
+
+	rc = dpp_se_zreg_mono_cfg_get(p_se_cfg->dev, zblk_idx, &zreg0_bulk_id,
+								  &zreg0_mono_flag, &zreg1_bulk_id,
+								  &zreg1_mono_flag, &zreg2_bulk_id,
+								  &zreg2_mono_flag, &zreg3_bulk_id,
+								  &zreg3_mono_flag);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_zreg_mono_cfg_get");
+
+	switch (zreg_id) {
+	case 0: {
+		zreg0_bulk_id = bulk_id;
+		zreg0_mono_flag = 1;
+		break;
+	}
+
+	case 1: {
+		zreg1_bulk_id = bulk_id;
+		zreg1_mono_flag = 1;
+		break;
+	}
+
+	case 2: {
+		zreg2_bulk_id = bulk_id;
+		zreg2_mono_flag = 1;
+		break;
+	}
+
+	case 3: {
+		zreg3_bulk_id = bulk_id;
+		zreg3_mono_flag = 1;
+		break;
+	}
+
+	default: {
+		ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "\n zreg id is out of rang.");
+		ZXIC_COMM_ASSERT(0);
+	}
+	}
+
+	rc = dpp_se_zreg_mono_cfg_set(p_se_cfg->dev, zblk_idx, zreg0_bulk_id,
+								  zreg0_mono_flag, zreg1_bulk_id,
+								  zreg1_mono_flag, zreg2_bulk_id,
+								  zreg2_mono_flag, zreg3_bulk_id,
+								  zreg3_mono_flag);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_zreg_mono_cfg_set");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** hash ddr参数配置
+ * @param   p_se_cfg  算法模块公共管理数据结构指针
+ * @param   fun_id    hash引擎号
+ * @param   bulk_id
+ * @param   p_ddr_cfg
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2014/07/31
+ ************************************************************/
+DPP_STATUS dpp_hash_ext_cfg_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id,
+								  ZXIC_UINT32 bulk_id, HASH_DDR_CFG *p_ddr_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 ext_mode = 0;
+	ZXIC_UINT32 ext_flag = 0;
+	ZXIC_UINT32 dev_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	ZXIC_COMM_CHECK_POINT(p_ddr_cfg);
+	ZXIC_COMM_CHECK_INDEX(fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX);
+	ZXIC_COMM_CHECK_INDEX(bulk_id, HASH_BULK_ID_MIN, HASH_BULK_ID_MAX);
+
+	dev_id = p_se_cfg->dev_id;
+
+	rc = dpp_se_hash_ext_cfg_get(p_se_cfg->dev, fun_id, &ext_mode, &ext_flag);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_ext_cfg_get");
+
+	ext_flag = 1;
+
+	if (p_ddr_cfg->width_mode == DDR_WIDTH_256b) {
+		ext_mode = (ext_mode & (~(1U << bulk_id)));
+	} else if (p_ddr_cfg->width_mode == DDR_WIDTH_512b) {
+		ext_mode = (ext_mode | (1U << bulk_id));
+	}
+
+	rc = dpp_se_hash_ext_cfg_set(p_se_cfg->dev, fun_id, ext_mode, ext_flag);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_ext_cfg_set");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**
+ * @param   p_se_cfg  算法模块公共管理数据结构指针
+ * @param   fun_id    hash引擎号
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  wcl      @date  2014/07/31
+ ************************************************************/
+DPP_STATUS dpp_hash_ext_cfg_clr(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 ext_mode = 0;
+	ZXIC_UINT32 ext_flag = 0;
+	ZXIC_UINT32 dev_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	ZXIC_COMM_CHECK_INDEX(fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX);
+
+	dev_id = p_se_cfg->dev_id;
+
+	rc = dpp_se_hash_ext_cfg_set(p_se_cfg->dev, fun_id, ext_mode, ext_flag);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_ext_cfg_set");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** hash 业务表ddr深度配置
+ * @param   p_se_cfg  算法模块公共管理数据结构指针
+ * @param   fun_id    hash引擎号
+ * @param   bulk_id
+ * @param   p_ddr_cfg
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  tf      @date  2016/01/28
+ ************************************************************/
+DPP_STATUS dpp_hash_tbl_depth_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id,
+									ZXIC_UINT32 bulk_id,
+									HASH_DDR_CFG *p_ddr_cfg)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 ext_depth = 0;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 hash_tbl0_depth = 0;
+	ZXIC_UINT32 hash_tbl1_depth = 0;
+	ZXIC_UINT32 hash_tbl2_depth = 0;
+	ZXIC_UINT32 hash_tbl3_depth = 0;
+	ZXIC_UINT32 hash_tbl4_depth = 0;
+	ZXIC_UINT32 hash_tbl5_depth = 0;
+	ZXIC_UINT32 hash_tbl6_depth = 0;
+	ZXIC_UINT32 hash_tbl7_depth = 0;
+
+	ZXIC_UINT32 hash_tbl_depth_array[HASH_BULK_NUM] = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	ZXIC_COMM_CHECK_POINT(p_ddr_cfg);
+	ZXIC_COMM_CHECK_INDEX(fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX);
+	ZXIC_COMM_CHECK_INDEX(bulk_id, HASH_BULK_ID_MIN, HASH_BULK_ID_MAX);
+
+	dev_id = p_se_cfg->dev_id;
+
+	ext_depth = dpp_hash_ddr_depth_conv(p_ddr_cfg->item_num);
+
+	if (((ZXIC_UINT32)1 << ext_depth) != p_ddr_cfg->item_num) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				dev_id,
+				"ErrCode[ 0x%x ]: Hash DDR item num:[ %d ] is not N power of 2.\n",
+				DPP_HASH_RC_INVALID_PARA, p_ddr_cfg->item_num);
+		ZXIC_COMM_ASSERT(0);
+		return DPP_HASH_RC_INVALID_PARA;
+	}
+
+	rc = dpp_se_hash_tbl_depth_get(p_se_cfg->dev, fun_id, &hash_tbl0_depth,
+								   &hash_tbl1_depth, &hash_tbl2_depth,
+								   &hash_tbl3_depth, &hash_tbl4_depth,
+								   &hash_tbl5_depth, &hash_tbl6_depth,
+								   &hash_tbl7_depth);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_tbl_depth_get");
+
+	hash_tbl_depth_array[0] = hash_tbl0_depth;
+	hash_tbl_depth_array[1] = hash_tbl1_depth;
+	hash_tbl_depth_array[2] = hash_tbl2_depth;
+	hash_tbl_depth_array[3] = hash_tbl3_depth;
+	hash_tbl_depth_array[4] = hash_tbl4_depth;
+	hash_tbl_depth_array[5] = hash_tbl5_depth;
+	hash_tbl_depth_array[6] = hash_tbl6_depth;
+	hash_tbl_depth_array[7] = hash_tbl7_depth;
+
+	hash_tbl_depth_array[bulk_id] = ext_depth;
+
+	hash_tbl0_depth = hash_tbl_depth_array[0];
+	hash_tbl1_depth = hash_tbl_depth_array[1];
+	hash_tbl2_depth = hash_tbl_depth_array[2];
+	hash_tbl3_depth = hash_tbl_depth_array[3];
+	hash_tbl4_depth = hash_tbl_depth_array[4];
+	hash_tbl5_depth = hash_tbl_depth_array[5];
+	hash_tbl6_depth = hash_tbl_depth_array[6];
+	hash_tbl7_depth = hash_tbl_depth_array[7];
+
+	rc = dpp_se_hash_tbl_depth_set(p_se_cfg->dev, fun_id, hash_tbl0_depth,
+								   hash_tbl1_depth, hash_tbl2_depth,
+								   hash_tbl3_depth, hash_tbl4_depth,
+								   hash_tbl5_depth, hash_tbl6_depth,
+								   hash_tbl7_depth);
+
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_tbl_depth_set");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** hash 业务表ddr深度恢复默认值
+ * @param   p_se_cfg  算法模块公共管理数据结构指针
+ * @param   fun_id    hash引擎号
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  tf      @date  2016/01/28
+ ************************************************************/
+DPP_STATUS dpp_hash_tbl_depth_clr(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 hash_tbl0_depth = 0x12;
+	ZXIC_UINT32 hash_tbl1_depth = 0x12;
+	ZXIC_UINT32 hash_tbl2_depth = 0x12;
+	ZXIC_UINT32 hash_tbl3_depth = 0x12;
+	ZXIC_UINT32 hash_tbl4_depth = 0x12;
+	ZXIC_UINT32 hash_tbl5_depth = 0x12;
+	ZXIC_UINT32 hash_tbl6_depth = 0x12;
+	ZXIC_UINT32 hash_tbl7_depth = 0x12;
+
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	ZXIC_COMM_CHECK_INDEX(fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX);
+
+	dev_id = p_se_cfg->dev_id;
+
+	rc = dpp_se_hash_tbl_depth_set(p_se_cfg->dev, fun_id, hash_tbl0_depth,
+								   hash_tbl1_depth, hash_tbl2_depth,
+								   hash_tbl3_depth, hash_tbl4_depth,
+								   hash_tbl5_depth, hash_tbl6_depth,
+								   hash_tbl7_depth);
+
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_hash_tbl_depth_set");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** hash CRC多项式选择
+ * @param   fun_id    hash引擎号
+ * @param   crc_sel
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  tf      @date  2016/01/28
+ ************************************************************/
+DPP_STATUS dpp_hash_tbl_crc_poly_write(DPP_SE_CFG *p_se_cfg, ZXIC_UINT32 fun_id,
+									   ZXIC_UINT32 bulk_id, ZXIC_UINT32 crc_sel)
+{
+	DPP_STATUS rtn = DPP_OK;
+
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 hash_tbl_crc_cfg_bt_start = 0;
+	ZXIC_UINT32 hash_tbl_crc_cfg_bt_width = 2;
+	DPP_SE4K_SE_ALG_HASH10_EXT_CRC_CFG_T hash01_ext_crc_cfg = { 0 };
+	DPP_SE4K_SE_ALG_HASH32_EXT_CRC_CFG_T hash23_ext_crc_cfg = { 0 };
+
+	ZXIC_COMM_ASSERT(p_se_cfg);
+
+	dev_id = p_se_cfg->dev_id;
+
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, fun_id, DPP_HASH_ID_MIN, DPP_HASH_ID_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX(dev_id, bulk_id, HASH_BULK_ID_MIN,
+							  HASH_BULK_ID_MAX);
+
+	hash_tbl_crc_cfg_bt_start = bulk_id * 2;
+
+	if (fun_id == 0 || fun_id == 1) {
+		rtn = dpp_reg_read(p_se_cfg->dev, SE4K_SE_ALG_HASH10_EXT_CRC_CFGr, 0, 0,
+						   &hash01_ext_crc_cfg);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_reg_read");
+
+		if (fun_id == 0) {
+			ZXIC_COMM_UINT32_WRITE_BITS(hash01_ext_crc_cfg.hash0_crc_cfg,
+										crc_sel, hash_tbl_crc_cfg_bt_start,
+										hash_tbl_crc_cfg_bt_width);
+		} else {
+			ZXIC_COMM_UINT32_WRITE_BITS(hash01_ext_crc_cfg.hash1_crc_cfg,
+										crc_sel, hash_tbl_crc_cfg_bt_start,
+										hash_tbl_crc_cfg_bt_width);
+		}
+
+		rtn = dpp_reg_write(p_se_cfg->dev, SE4K_SE_ALG_HASH10_EXT_CRC_CFGr, 0,
+							0, &hash01_ext_crc_cfg);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_reg_write");
+	} else {
+		rtn = dpp_reg_read(p_se_cfg->dev, SE4K_SE_ALG_HASH32_EXT_CRC_CFGr, 0, 0,
+						   &hash23_ext_crc_cfg);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_reg_read");
+
+		if (fun_id == 2) {
+			ZXIC_COMM_UINT32_WRITE_BITS(hash23_ext_crc_cfg.hash2_crc_cfg,
+										crc_sel, hash_tbl_crc_cfg_bt_start,
+										hash_tbl_crc_cfg_bt_width);
+		} else {
+			ZXIC_COMM_UINT32_WRITE_BITS(hash23_ext_crc_cfg.hash3_crc_cfg,
+										crc_sel, hash_tbl_crc_cfg_bt_start,
+										hash_tbl_crc_cfg_bt_width);
+		}
+
+		rtn = dpp_reg_write(p_se_cfg->dev, SE4K_SE_ALG_HASH32_EXT_CRC_CFGr, 0,
+							0, &hash23_ext_crc_cfg);
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rtn, "dpp_reg_write");
+	}
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 清除hash引擎的所有hash表项(清除软件配置)
+ * @param   p_se_cfg
+ * @param   hash_id
+ * @param   bulk_id
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/08/18
+ ************************************************************/
+DPP_STATUS dpp_hash_soft_all_entry_delete(DPP_SE_CFG *p_se_cfg,
+										  ZXIC_UINT32 hash_id)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT8 table_id = 0;
+	ZXIC_UINT32 bulk_id = 0;
+
+	D_NODE *p_node = NULL;
+	ZXIC_RB_TN *p_rb_tn = NULL;
+	ZXIC_RB_TN *p_rb_tn_rtn = NULL;
+	D_HEAD *p_head_hash_rb = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	FUNC_ID_INFO *p_func_info = NULL;
+	DPP_HASH_RBKEY_INFO *p_rbkey = NULL;
+	DPP_HASH_RBKEY_INFO *p_rbkey_rtn = NULL;
+	SE_ITEM_CFG *p_item = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	ZXIC_COMM_CHECK_INDEX(hash_id, 0, HASH_FUNC_ID_NUM - 1);
+
+	dev_id = p_se_cfg->dev_id;
+
+	p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_id);
+	DPP_SE_CHECK_FUN(p_func_info, hash_id, FUN_HASH);
+
+	p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
+	p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list;
+
+	while (p_head_hash_rb->used) {
+		p_node = p_head_hash_rb->p_next;
+		p_rb_tn = (ZXIC_RB_TN *)p_node->data;
+		p_rbkey = (DPP_HASH_RBKEY_INFO *)p_rb_tn->p_key;
+		table_id = DPP_GET_HASH_TBL_ID(p_rbkey->key);
+		bulk_id = ((table_id >> 2) & 0x7);
+		ZXIC_COMM_CHECK_DEV_INDEX(dev_id, bulk_id, 0, HASH_BULK_NUM - 1);
+
+		rc = zxic_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey, &p_rb_tn_rtn);
+		if (ZXIC_RBT_RC_SRHFAIL == rc) {
+			p_hash_cfg->hash_stat.delete_fail++;
+			ZXIC_COMM_TRACE_DEV_DEBUG(dev_id,
+									  "Error!there is not item in hash!\n");
+			return DPP_HASH_RC_DEL_SRHFAIL;
+		}
+
+		ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn);
+		p_rbkey_rtn = (DPP_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key);
+		p_item = p_rbkey_rtn->p_item_info;
+
+		rc = zxic_comm_double_link_del(&(p_rbkey_rtn->entry_dn),
+									   &(p_item->item_list));
+		ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_double_link_del");
+		p_item->wrt_mask &= ~(DPP_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size,
+													  p_rbkey_rtn->entry_pos)) &
+							0xF;
+
+		if (0 == p_item->item_list.used) {
+			if ((ITEM_DDR_256 == p_item->item_type) ||
+				(ITEM_DDR_512 == p_item->item_type)) {
+				/* modify coverity by yinxh 2021.03.10*,以256bit为单位。暂不考虑512bit的情况*/
+				ZXIC_COMM_CHECK_INDEX_UPPER(
+						p_item->item_index,
+						p_hash_cfg->p_bulk_ddr_info[bulk_id]->item_num);
+				p_hash_cfg->p_bulk_ddr_info[bulk_id]
+						->p_item_array[p_item->item_index] = NULL;
+				ZXIC_COMM_FREE(p_item);
+			} else {
+				p_item->valid = 0;
+			}
+		}
+
+		ZXIC_COMM_FREE(p_rbkey_rtn);
+		ZXIC_COMM_FREE(p_rb_tn_rtn);
+		p_hash_cfg->hash_stat.delete_ok++;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 卸载软件上分配的hash资源(主要针对malloc释放)
+ * @param   dev_id  设备号
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/12/20
+ ************************************************************/
+DPP_STATUS dpp_hash_soft_uninstall(ZXIC_UINT32 dev_id)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 hash_id = 0;
+
+	ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+
+	for (hash_id = 0; hash_id < HASH_FUNC_ID_NUM; hash_id++) {
+		rc = dpp_one_hash_soft_uninstall(dev_id, hash_id);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc,
+										 "dpp_one_hash_soft_uninstall");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 卸载指定hashid上软件分配的hash资源(主要针对malloc释放)
+ * @param   dev_id  设备号
+ * @param   hash_id  hash id 0~3
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/12/20
+ ************************************************************/
+DPP_STATUS dpp_one_hash_soft_uninstall(ZXIC_UINT32 dev_id, ZXIC_UINT32 hash_id)
+{
+	ZXIC_UINT32 rc = 0;
+	ZXIC_UINT32 i = 0;
+
+	D_NODE *p_node = NULL;
+	DPP_SE_CFG *p_se_cfg = NULL;
+	ZXIC_RB_TN *p_rb_tn = NULL;
+	ZXIC_RB_TN *p_rb_tn_rtn = NULL;
+	HASH_DDR_CFG *p_rbkey = NULL;
+	DPP_HASH_CFG *p_hash_cfg = NULL;
+	FUNC_ID_INFO *p_func_info = NULL;
+	D_HEAD *p_head_ddr_cfg_rb = NULL;
+	HASH_DDR_CFG *p_temp_rbkey = NULL;
+
+	ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(hash_id, 0, HASH_FUNC_ID_NUM - 1);
+
+	/* 取出se配置 */
+	rc = dpp_se_cfg_get(dev_id, &p_se_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_cfg_get");
+	ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg);
+	p_func_info = DPP_GET_FUN_INFO(p_se_cfg, hash_id);
+	if (0 == p_func_info->is_used) {
+		ZXIC_COMM_TRACE_DEBUG("Error[0x%x], fun_id [%d] is not init\n!",
+							  DPP_SE_RC_FUN_INVALID, hash_id);
+		return DPP_OK;
+	}
+
+	/*软件删除表项,删除红黑树节点*/
+	rc = dpp_hash_soft_all_entry_delete(p_se_cfg, hash_id);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_soft_all_entry_delete");
+
+	/*释放独占标识内存*/
+	p_hash_cfg = (DPP_HASH_CFG *)p_func_info->fun_ptr;
+	for (i = 0; i < HASH_BULK_NUM; i++) {
+		if ((&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i] != NULL) {
+			ZXIC_COMM_FREE((&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i]);
+			(&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i] = NULL;
+		}
+	}
+
+	/*释放DDR分配的所有内存*/
+	p_head_ddr_cfg_rb = &p_hash_cfg->ddr_cfg_rb.tn_list;
+	while (p_head_ddr_cfg_rb->used) {
+		p_node = p_head_ddr_cfg_rb->p_next;
+
+		p_rb_tn = (ZXIC_RB_TN *)p_node->data;
+		p_rbkey = p_rb_tn->p_key;
+
+		rc = zxic_comm_rb_delete(&p_hash_cfg->ddr_cfg_rb, p_rbkey,
+								 &p_rb_tn_rtn);
+
+		if (ZXIC_RBT_RC_SRHFAIL == rc) {
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					dev_id, "ddr_cfg_rb delete key is not exist, key: 0x");
+		} else {
+			ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "zxic_comm_rb_delete");
+		}
+
+		ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn);
+		p_temp_rbkey = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key);
+		ZXIC_COMM_FREE(p_temp_rbkey->p_item_array);
+		p_temp_rbkey->p_item_array = NULL;
+		ZXIC_COMM_FREE(p_temp_rbkey);
+		ZXIC_COMM_FREE(p_rb_tn_rtn);
+	}
+
+	rc = dpp_hash_zcam_resource_deinit(p_hash_cfg);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_hash_zcam_resource_deinit");
+
+	rc = dpp_se_fun_deinit(p_se_cfg, (hash_id & 0xff), FUN_HASH);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_se_fun_deinit");
+
+	ZXIC_COMM_MEMSET(g_tbl_id_info[dev_id][hash_id], 0,
+					 HASH_TBL_ID_NUM * sizeof(DPP_HASH_TBL_ID_INFO));
+
+	return DPP_OK;
+}
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_hash_crc.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_hash_crc.c
old mode 100755
new mode 100644
index 5dc4ef1ab20539f13f6acf2f300306d60978c3ff..75e1d57bf7619bf0dbc2530912cf5c9612b34286
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_hash_crc.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_hash_crc.c
@@ -1,381 +1,374 @@
-#include "zxic_common.h"
-#include "dpp_hash_crc.h"
-
-ZXIC_UINT16 g_crc16_rst[256][8] = {
-    {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-    {0x1021, 0x8005, 0x3d65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b},
-    {0x2042, 0x800f, 0x7aca, 0xfdc9, 0x68a6, 0x06ae, 0x0b12, 0xe07d},
-    {0x3063, 0x000a, 0x47af, 0x568e, 0x5cf5, 0x05f9, 0x0e9b, 0x4056},
-    {0x4084, 0x801b, 0xf594, 0x50d5, 0xd14c, 0x0d5c, 0x1624, 0x60d1},
-    {0x50a5, 0x001e, 0xc8f1, 0xfb92, 0xe51f, 0x0e0b, 0x13ad, 0xc0fa},
-    {0x60c6, 0x0014, 0x8f5e, 0xad1c, 0xb9ea, 0x0bf2, 0x1d36, 0x80ac},
-    {0x70e7, 0x8011, 0xb23b, 0x065b, 0x8db9, 0x08a5, 0x18bf, 0x2087},
-    {0x8108, 0x8033, 0xd64d, 0xa1aa, 0x96cb, 0x1ab8, 0x2c48, 0xc1a2},
-    {0x9129, 0x0036, 0xeb28, 0x0aed, 0xa298, 0x19ef, 0x29c1, 0x6189},
-    {0xa14a, 0x003c, 0xac87, 0x5c63, 0xfe6d, 0x1c16, 0x275a, 0x21df},
-    {0xb16b, 0x8039, 0x91e2, 0xf724, 0xca3e, 0x1f41, 0x22d3, 0x81f4},
-    {0xc18c, 0x0028, 0x23d9, 0xf17f, 0x4787, 0x17e4, 0x3a6c, 0xa173},
-    {0xd1ad, 0x802d, 0x1ebc, 0x5a38, 0x73d4, 0x14b3, 0x3fe5, 0x0158},
-    {0xe1ce, 0x8027, 0x5913, 0x0cb6, 0x2f21, 0x114a, 0x317e, 0x410e},
-    {0xf1ef, 0x0022, 0x6476, 0xa7f1, 0x1b72, 0x121d, 0x34f7, 0xe125},
-    {0x1231, 0x8063, 0x91ff, 0xe813, 0x19c5, 0x3570, 0x5890, 0x236f},
-    {0x0210, 0x0066, 0xac9a, 0x4354, 0x2d96, 0x3627, 0x5d19, 0x8344},
-    {0x3273, 0x006c, 0xeb35, 0x15da, 0x7163, 0x33de, 0x5382, 0xc312},
-    {0x2252, 0x8069, 0xd650, 0xbe9d, 0x4530, 0x3089, 0x560b, 0x6339},
-    {0x52b5, 0x0078, 0x646b, 0xb8c6, 0xc889, 0x382c, 0x4eb4, 0x43be},
-    {0x4294, 0x807d, 0x590e, 0x1381, 0xfcda, 0x3b7b, 0x4b3d, 0xe395},
-    {0x72f7, 0x8077, 0x1ea1, 0x450f, 0xa02f, 0x3e82, 0x45a6, 0xa3c3},
-    {0x62d6, 0x0072, 0x23c4, 0xee48, 0x947c, 0x3dd5, 0x402f, 0x03e8},
-    {0x9339, 0x0050, 0x47b2, 0x49b9, 0x8f0e, 0x2fc8, 0x74d8, 0xe2cd},
-    {0x8318, 0x8055, 0x7ad7, 0xe2fe, 0xbb5d, 0x2c9f, 0x7151, 0x42e6},
-    {0xb37b, 0x805f, 0x3d78, 0xb470, 0xe7a8, 0x2966, 0x7fca, 0x02b0},
-    {0xa35a, 0x005a, 0x001d, 0x1f37, 0xd3fb, 0x2a31, 0x7a43, 0xa29b},
-    {0xd3bd, 0x804b, 0xb226, 0x196c, 0x5e42, 0x2294, 0x62fc, 0x821c},
-    {0xc39c, 0x004e, 0x8f43, 0xb22b, 0x6a11, 0x21c3, 0x6775, 0x2237},
-    {0xf3ff, 0x0044, 0xc8ec, 0xe4a5, 0x36e4, 0x243a, 0x69ee, 0x6261},
-    {0xe3de, 0x8041, 0xf589, 0x4fe2, 0x02b7, 0x276d, 0x6c67, 0xc24a},
-    {0x2462, 0x80c3, 0x1e9b, 0x7b61, 0x338a, 0x6ae0, 0xb120, 0x46de},
-    {0x3443, 0x00c6, 0x23fe, 0xd026, 0x07d9, 0x69b7, 0xb4a9, 0xe6f5},
-    {0x0420, 0x00cc, 0x6451, 0x86a8, 0x5b2c, 0x6c4e, 0xba32, 0xa6a3},
-    {0x1401, 0x80c9, 0x5934, 0x2def, 0x6f7f, 0x6f19, 0xbfbb, 0x0688},
-    {0x64e6, 0x00d8, 0xeb0f, 0x2bb4, 0xe2c6, 0x67bc, 0xa704, 0x260f},
-    {0x74c7, 0x80dd, 0xd66a, 0x80f3, 0xd695, 0x64eb, 0xa28d, 0x8624},
-    {0x44a4, 0x80d7, 0x91c5, 0xd67d, 0x8a60, 0x6112, 0xac16, 0xc672},
-    {0x5485, 0x00d2, 0xaca0, 0x7d3a, 0xbe33, 0x6245, 0xa99f, 0x6659},
-    {0xa56a, 0x00f0, 0xc8d6, 0xdacb, 0xa541, 0x7058, 0x9d68, 0x877c},
-    {0xb54b, 0x80f5, 0xf5b3, 0x718c, 0x9112, 0x730f, 0x98e1, 0x2757},
-    {0x8528, 0x80ff, 0xb21c, 0x2702, 0xcde7, 0x76f6, 0x967a, 0x6701},
-    {0x9509, 0x00fa, 0x8f79, 0x8c45, 0xf9b4, 0x75a1, 0x93f3, 0xc72a},
-    {0xe5ee, 0x80eb, 0x3d42, 0x8a1e, 0x740d, 0x7d04, 0x8b4c, 0xe7ad},
-    {0xf5cf, 0x00ee, 0x0027, 0x2159, 0x405e, 0x7e53, 0x8ec5, 0x4786},
-    {0xc5ac, 0x00e4, 0x4788, 0x77d7, 0x1cab, 0x7baa, 0x805e, 0x07d0},
-    {0xd58d, 0x80e1, 0x7aed, 0xdc90, 0x28f8, 0x78fd, 0x85d7, 0xa7fb},
-    {0x3653, 0x00a0, 0x8f64, 0x9372, 0x2a4f, 0x5f90, 0xe9b0, 0x65b1},
-    {0x2672, 0x80a5, 0xb201, 0x3835, 0x1e1c, 0x5cc7, 0xec39, 0xc59a},
-    {0x1611, 0x80af, 0xf5ae, 0x6ebb, 0x42e9, 0x593e, 0xe2a2, 0x85cc},
-    {0x0630, 0x00aa, 0xc8cb, 0xc5fc, 0x76ba, 0x5a69, 0xe72b, 0x25e7},
-    {0x76d7, 0x80bb, 0x7af0, 0xc3a7, 0xfb03, 0x52cc, 0xff94, 0x0560},
-    {0x66f6, 0x00be, 0x4795, 0x68e0, 0xcf50, 0x519b, 0xfa1d, 0xa54b},
-    {0x5695, 0x00b4, 0x003a, 0x3e6e, 0x93a5, 0x5462, 0xf486, 0xe51d},
-    {0x46b4, 0x80b1, 0x3d5f, 0x9529, 0xa7f6, 0x5735, 0xf10f, 0x4536},
-    {0xb75b, 0x8093, 0x5929, 0x32d8, 0xbc84, 0x4528, 0xc5f8, 0xa413},
-    {0xa77a, 0x0096, 0x644c, 0x999f, 0x88d7, 0x467f, 0xc071, 0x0438},
-    {0x9719, 0x009c, 0x23e3, 0xcf11, 0xd422, 0x4386, 0xceea, 0x446e},
-    {0x8738, 0x8099, 0x1e86, 0x6456, 0xe071, 0x40d1, 0xcb63, 0xe445},
-    {0xf7df, 0x0088, 0xacbd, 0x620d, 0x6dc8, 0x4874, 0xd3dc, 0xc4c2},
-    {0xe7fe, 0x808d, 0x91d8, 0xc94a, 0x599b, 0x4b23, 0xd655, 0x64e9},
-    {0xd79d, 0x8087, 0xd677, 0x9fc4, 0x056e, 0x4eda, 0xd8ce, 0x24bf},
-    {0xc7bc, 0x0082, 0xeb12, 0x3483, 0x313d, 0x4d8d, 0xdd47, 0x8494},
-    {0x48c4, 0x8183, 0x3d36, 0xf6c2, 0x6714, 0xd5c0, 0x67c9, 0x8dbc},
-    {0x58e5, 0x0186, 0x0053, 0x5d85, 0x5347, 0xd697, 0x6240, 0x2d97},
-    {0x6886, 0x018c, 0x47fc, 0x0b0b, 0x0fb2, 0xd36e, 0x6cdb, 0x6dc1},
-    {0x78a7, 0x8189, 0x7a99, 0xa04c, 0x3be1, 0xd039, 0x6952, 0xcdea},
-    {0x0840, 0x0198, 0xc8a2, 0xa617, 0xb658, 0xd89c, 0x71ed, 0xed6d},
-    {0x1861, 0x819d, 0xf5c7, 0x0d50, 0x820b, 0xdbcb, 0x7464, 0x4d46},
-    {0x2802, 0x8197, 0xb268, 0x5bde, 0xdefe, 0xde32, 0x7aff, 0x0d10},
-    {0x3823, 0x0192, 0x8f0d, 0xf099, 0xeaad, 0xdd65, 0x7f76, 0xad3b},
-    {0xc9cc, 0x01b0, 0xeb7b, 0x5768, 0xf1df, 0xcf78, 0x4b81, 0x4c1e},
-    {0xd9ed, 0x81b5, 0xd61e, 0xfc2f, 0xc58c, 0xcc2f, 0x4e08, 0xec35},
-    {0xe98e, 0x81bf, 0x91b1, 0xaaa1, 0x9979, 0xc9d6, 0x4093, 0xac63},
-    {0xf9af, 0x01ba, 0xacd4, 0x01e6, 0xad2a, 0xca81, 0x451a, 0x0c48},
-    {0x8948, 0x81ab, 0x1eef, 0x07bd, 0x2093, 0xc224, 0x5da5, 0x2ccf},
-    {0x9969, 0x01ae, 0x238a, 0xacfa, 0x14c0, 0xc173, 0x582c, 0x8ce4},
-    {0xa90a, 0x01a4, 0x6425, 0xfa74, 0x4835, 0xc48a, 0x56b7, 0xccb2},
-    {0xb92b, 0x81a1, 0x5940, 0x5133, 0x7c66, 0xc7dd, 0x533e, 0x6c99},
-    {0x5af5, 0x01e0, 0xacc9, 0x1ed1, 0x7ed1, 0xe0b0, 0x3f59, 0xaed3},
-    {0x4ad4, 0x81e5, 0x91ac, 0xb596, 0x4a82, 0xe3e7, 0x3ad0, 0x0ef8},
-    {0x7ab7, 0x81ef, 0xd603, 0xe318, 0x1677, 0xe61e, 0x344b, 0x4eae},
-    {0x6a96, 0x01ea, 0xeb66, 0x485f, 0x2224, 0xe549, 0x31c2, 0xee85},
-    {0x1a71, 0x81fb, 0x595d, 0x4e04, 0xaf9d, 0xedec, 0x297d, 0xce02},
-    {0x0a50, 0x01fe, 0x6438, 0xe543, 0x9bce, 0xeebb, 0x2cf4, 0x6e29},
-    {0x3a33, 0x01f4, 0x2397, 0xb3cd, 0xc73b, 0xeb42, 0x226f, 0x2e7f},
-    {0x2a12, 0x81f1, 0x1ef2, 0x188a, 0xf368, 0xe815, 0x27e6, 0x8e54},
-    {0xdbfd, 0x81d3, 0x7a84, 0xbf7b, 0xe81a, 0xfa08, 0x1311, 0x6f71},
-    {0xcbdc, 0x01d6, 0x47e1, 0x143c, 0xdc49, 0xf95f, 0x1698, 0xcf5a},
-    {0xfbbf, 0x01dc, 0x004e, 0x42b2, 0x80bc, 0xfca6, 0x1803, 0x8f0c},
-    {0xeb9e, 0x81d9, 0x3d2b, 0xe9f5, 0xb4ef, 0xfff1, 0x1d8a, 0x2f27},
-    {0x9b79, 0x01c8, 0x8f10, 0xefae, 0x3956, 0xf754, 0x0535, 0x0fa0},
-    {0x8b58, 0x81cd, 0xb275, 0x44e9, 0x0d05, 0xf403, 0x00bc, 0xaf8b},
-    {0xbb3b, 0x81c7, 0xf5da, 0x1267, 0x51f0, 0xf1fa, 0x0e27, 0xefdd},
-    {0xab1a, 0x01c2, 0xc8bf, 0xb920, 0x65a3, 0xf2ad, 0x0bae, 0x4ff6},
-    {0x6ca6, 0x0140, 0x23ad, 0x8da3, 0x549e, 0xbf20, 0xd6e9, 0xcb62},
-    {0x7c87, 0x8145, 0x1ec8, 0x26e4, 0x60cd, 0xbc77, 0xd360, 0x6b49},
-    {0x4ce4, 0x814f, 0x5967, 0x706a, 0x3c38, 0xb98e, 0xddfb, 0x2b1f},
-    {0x5cc5, 0x014a, 0x6402, 0xdb2d, 0x086b, 0xbad9, 0xd872, 0x8b34},
-    {0x2c22, 0x815b, 0xd639, 0xdd76, 0x85d2, 0xb27c, 0xc0cd, 0xabb3},
-    {0x3c03, 0x015e, 0xeb5c, 0x7631, 0xb181, 0xb12b, 0xc544, 0x0b98},
-    {0x0c60, 0x0154, 0xacf3, 0x20bf, 0xed74, 0xb4d2, 0xcbdf, 0x4bce},
-    {0x1c41, 0x8151, 0x9196, 0x8bf8, 0xd927, 0xb785, 0xce56, 0xebe5},
-    {0xedae, 0x8173, 0xf5e0, 0x2c09, 0xc255, 0xa598, 0xfaa1, 0x0ac0},
-    {0xfd8f, 0x0176, 0xc885, 0x874e, 0xf606, 0xa6cf, 0xff28, 0xaaeb},
-    {0xcdec, 0x017c, 0x8f2a, 0xd1c0, 0xaaf3, 0xa336, 0xf1b3, 0xeabd},
-    {0xddcd, 0x8179, 0xb24f, 0x7a87, 0x9ea0, 0xa061, 0xf43a, 0x4a96},
-    {0xad2a, 0x0168, 0x0074, 0x7cdc, 0x1319, 0xa8c4, 0xec85, 0x6a11},
-    {0xbd0b, 0x816d, 0x3d11, 0xd79b, 0x274a, 0xab93, 0xe90c, 0xca3a},
-    {0x8d68, 0x8167, 0x7abe, 0x8115, 0x7bbf, 0xae6a, 0xe797, 0x8a6c},
-    {0x9d49, 0x0162, 0x47db, 0x2a52, 0x4fec, 0xad3d, 0xe21e, 0x2a47},
-    {0x7e97, 0x8123, 0xb252, 0x65b0, 0x4d5b, 0x8a50, 0x8e79, 0xe80d},
-    {0x6eb6, 0x0126, 0x8f37, 0xcef7, 0x7908, 0x8907, 0x8bf0, 0x4826},
-    {0x5ed5, 0x012c, 0xc898, 0x9879, 0x25fd, 0x8cfe, 0x856b, 0x0870},
-    {0x4ef4, 0x8129, 0xf5fd, 0x333e, 0x11ae, 0x8fa9, 0x80e2, 0xa85b},
-    {0x3e13, 0x0138, 0x47c6, 0x3565, 0x9c17, 0x870c, 0x985d, 0x88dc},
-    {0x2e32, 0x813d, 0x7aa3, 0x9e22, 0xa844, 0x845b, 0x9dd4, 0x28f7},
-    {0x1e51, 0x8137, 0x3d0c, 0xc8ac, 0xf4b1, 0x81a2, 0x934f, 0x68a1},
-    {0x0e70, 0x0132, 0x0069, 0x63eb, 0xc0e2, 0x82f5, 0x96c6, 0xc88a},
-    {0xff9f, 0x0110, 0x641f, 0xc41a, 0xdb90, 0x90e8, 0xa231, 0x29af},
-    {0xefbe, 0x8115, 0x597a, 0x6f5d, 0xefc3, 0x93bf, 0xa7b8, 0x8984},
-    {0xdfdd, 0x811f, 0x1ed5, 0x39d3, 0xb336, 0x9646, 0xa923, 0xc9d2},
-    {0xcffc, 0x011a, 0x23b0, 0x9294, 0x8765, 0x9511, 0xacaa, 0x69f9},
-    {0xbf1b, 0x810b, 0x918b, 0x94cf, 0x0adc, 0x9db4, 0xb415, 0x497e},
-    {0xaf3a, 0x010e, 0xacee, 0x3f88, 0x3e8f, 0x9ee3, 0xb19c, 0xe955},
-    {0x9f59, 0x0104, 0xeb41, 0x6906, 0x627a, 0x9b1a, 0xbf07, 0xa903},
-    {0x8f78, 0x8101, 0xd624, 0xc241, 0x5629, 0x984d, 0xba8e, 0x0928},
-    {0x9188, 0x8303, 0x7a6c, 0x46c3, 0xce28, 0xa8d7, 0xcf92, 0xbb53},
-    {0x81a9, 0x0306, 0x4709, 0xed84, 0xfa7b, 0xab80, 0xca1b, 0x1b78},
-    {0xb1ca, 0x030c, 0x00a6, 0xbb0a, 0xa68e, 0xae79, 0xc480, 0x5b2e},
-    {0xa1eb, 0x8309, 0x3dc3, 0x104d, 0x92dd, 0xad2e, 0xc109, 0xfb05},
-    {0xd10c, 0x0318, 0x8ff8, 0x1616, 0x1f64, 0xa58b, 0xd9b6, 0xdb82},
-    {0xc12d, 0x831d, 0xb29d, 0xbd51, 0x2b37, 0xa6dc, 0xdc3f, 0x7ba9},
-    {0xf14e, 0x8317, 0xf532, 0xebdf, 0x77c2, 0xa325, 0xd2a4, 0x3bff},
-    {0xe16f, 0x0312, 0xc857, 0x4098, 0x4391, 0xa072, 0xd72d, 0x9bd4},
-    {0x1080, 0x0330, 0xac21, 0xe769, 0x58e3, 0xb26f, 0xe3da, 0x7af1},
-    {0x00a1, 0x8335, 0x9144, 0x4c2e, 0x6cb0, 0xb138, 0xe653, 0xdada},
-    {0x30c2, 0x833f, 0xd6eb, 0x1aa0, 0x3045, 0xb4c1, 0xe8c8, 0x9a8c},
-    {0x20e3, 0x033a, 0xeb8e, 0xb1e7, 0x0416, 0xb796, 0xed41, 0x3aa7},
-    {0x5004, 0x832b, 0x59b5, 0xb7bc, 0x89af, 0xbf33, 0xf5fe, 0x1a20},
-    {0x4025, 0x032e, 0x64d0, 0x1cfb, 0xbdfc, 0xbc64, 0xf077, 0xba0b},
-    {0x7046, 0x0324, 0x237f, 0x4a75, 0xe109, 0xb99d, 0xfeec, 0xfa5d},
-    {0x6067, 0x8321, 0x1e1a, 0xe132, 0xd55a, 0xbaca, 0xfb65, 0x5a76},
-    {0x83b9, 0x0360, 0xeb93, 0xaed0, 0xd7ed, 0x9da7, 0x9702, 0x983c},
-    {0x9398, 0x8365, 0xd6f6, 0x0597, 0xe3be, 0x9ef0, 0x928b, 0x3817},
-    {0xa3fb, 0x836f, 0x9159, 0x5319, 0xbf4b, 0x9b09, 0x9c10, 0x7841},
-    {0xb3da, 0x036a, 0xac3c, 0xf85e, 0x8b18, 0x985e, 0x9999, 0xd86a},
-    {0xc33d, 0x837b, 0x1e07, 0xfe05, 0x06a1, 0x90fb, 0x8126, 0xf8ed},
-    {0xd31c, 0x037e, 0x2362, 0x5542, 0x32f2, 0x93ac, 0x84af, 0x58c6},
-    {0xe37f, 0x0374, 0x64cd, 0x03cc, 0x6e07, 0x9655, 0x8a34, 0x1890},
-    {0xf35e, 0x8371, 0x59a8, 0xa88b, 0x5a54, 0x9502, 0x8fbd, 0xb8bb},
-    {0x02b1, 0x8353, 0x3dde, 0x0f7a, 0x4126, 0x871f, 0xbb4a, 0x599e},
-    {0x1290, 0x0356, 0x00bb, 0xa43d, 0x7575, 0x8448, 0xbec3, 0xf9b5},
-    {0x22f3, 0x035c, 0x4714, 0xf2b3, 0x2980, 0x81b1, 0xb058, 0xb9e3},
-    {0x32d2, 0x8359, 0x7a71, 0x59f4, 0x1dd3, 0x82e6, 0xb5d1, 0x19c8},
-    {0x4235, 0x0348, 0xc84a, 0x5faf, 0x906a, 0x8a43, 0xad6e, 0x394f},
-    {0x5214, 0x834d, 0xf52f, 0xf4e8, 0xa439, 0x8914, 0xa8e7, 0x9964},
-    {0x6277, 0x8347, 0xb280, 0xa266, 0xf8cc, 0x8ced, 0xa67c, 0xd932},
-    {0x7256, 0x0342, 0x8fe5, 0x0921, 0xcc9f, 0x8fba, 0xa3f5, 0x7919},
-    {0xb5ea, 0x03c0, 0x64f7, 0x3da2, 0xfda2, 0xc237, 0x7eb2, 0xfd8d},
-    {0xa5cb, 0x83c5, 0x5992, 0x96e5, 0xc9f1, 0xc160, 0x7b3b, 0x5da6},
-    {0x95a8, 0x83cf, 0x1e3d, 0xc06b, 0x9504, 0xc499, 0x75a0, 0x1df0},
-    {0x8589, 0x03ca, 0x2358, 0x6b2c, 0xa157, 0xc7ce, 0x7029, 0xbddb},
-    {0xf56e, 0x83db, 0x9163, 0x6d77, 0x2cee, 0xcf6b, 0x6896, 0x9d5c},
-    {0xe54f, 0x03de, 0xac06, 0xc630, 0x18bd, 0xcc3c, 0x6d1f, 0x3d77},
-    {0xd52c, 0x03d4, 0xeba9, 0x90be, 0x4448, 0xc9c5, 0x6384, 0x7d21},
-    {0xc50d, 0x83d1, 0xd6cc, 0x3bf9, 0x701b, 0xca92, 0x660d, 0xdd0a},
-    {0x34e2, 0x83f3, 0xb2ba, 0x9c08, 0x6b69, 0xd88f, 0x52fa, 0x3c2f},
-    {0x24c3, 0x03f6, 0x8fdf, 0x374f, 0x5f3a, 0xdbd8, 0x5773, 0x9c04},
-    {0x14a0, 0x03fc, 0xc870, 0x61c1, 0x03cf, 0xde21, 0x59e8, 0xdc52},
-    {0x0481, 0x83f9, 0xf515, 0xca86, 0x379c, 0xdd76, 0x5c61, 0x7c79},
-    {0x7466, 0x03e8, 0x472e, 0xccdd, 0xba25, 0xd5d3, 0x44de, 0x5cfe},
-    {0x6447, 0x83ed, 0x7a4b, 0x679a, 0x8e76, 0xd684, 0x4157, 0xfcd5},
-    {0x5424, 0x83e7, 0x3de4, 0x3114, 0xd283, 0xd37d, 0x4fcc, 0xbc83},
-    {0x4405, 0x03e2, 0x0081, 0x9a53, 0xe6d0, 0xd02a, 0x4a45, 0x1ca8},
-    {0xa7db, 0x83a3, 0xf508, 0xd5b1, 0xe467, 0xf747, 0x2622, 0xdee2},
-    {0xb7fa, 0x03a6, 0xc86d, 0x7ef6, 0xd034, 0xf410, 0x23ab, 0x7ec9},
-    {0x8799, 0x03ac, 0x8fc2, 0x2878, 0x8cc1, 0xf1e9, 0x2d30, 0x3e9f},
-    {0x97b8, 0x83a9, 0xb2a7, 0x833f, 0xb892, 0xf2be, 0x28b9, 0x9eb4},
-    {0xe75f, 0x03b8, 0x009c, 0x8564, 0x352b, 0xfa1b, 0x3006, 0xbe33},
-    {0xf77e, 0x83bd, 0x3df9, 0x2e23, 0x0178, 0xf94c, 0x358f, 0x1e18},
-    {0xc71d, 0x83b7, 0x7a56, 0x78ad, 0x5d8d, 0xfcb5, 0x3b14, 0x5e4e},
-    {0xd73c, 0x03b2, 0x4733, 0xd3ea, 0x69de, 0xffe2, 0x3e9d, 0xfe65},
-    {0x26d3, 0x0390, 0x2345, 0x741b, 0x72ac, 0xedff, 0x0a6a, 0x1f40},
-    {0x36f2, 0x8395, 0x1e20, 0xdf5c, 0x46ff, 0xeea8, 0x0fe3, 0xbf6b},
-    {0x0691, 0x839f, 0x598f, 0x89d2, 0x1a0a, 0xeb51, 0x0178, 0xff3d},
-    {0x16b0, 0x039a, 0x64ea, 0x2295, 0x2e59, 0xe806, 0x04f1, 0x5f16},
-    {0x6657, 0x838b, 0xd6d1, 0x24ce, 0xa3e0, 0xe0a3, 0x1c4e, 0x7f91},
-    {0x7676, 0x038e, 0xebb4, 0x8f89, 0x97b3, 0xe3f4, 0x19c7, 0xdfba},
-    {0x4615, 0x0384, 0xac1b, 0xd907, 0xcb46, 0xe60d, 0x175c, 0x9fec},
-    {0x5634, 0x8381, 0x917e, 0x7240, 0xff15, 0xe55a, 0x12d5, 0x3fc7},
-    {0xd94c, 0x0280, 0x475a, 0xb001, 0xa93c, 0x7d17, 0xa85b, 0x36ef},
-    {0xc96d, 0x8285, 0x7a3f, 0x1b46, 0x9d6f, 0x7e40, 0xadd2, 0x96c4},
-    {0xf90e, 0x828f, 0x3d90, 0x4dc8, 0xc19a, 0x7bb9, 0xa349, 0xd692},
-    {0xe92f, 0x028a, 0x00f5, 0xe68f, 0xf5c9, 0x78ee, 0xa6c0, 0x76b9},
-    {0x99c8, 0x829b, 0xb2ce, 0xe0d4, 0x7870, 0x704b, 0xbe7f, 0x563e},
-    {0x89e9, 0x029e, 0x8fab, 0x4b93, 0x4c23, 0x731c, 0xbbf6, 0xf615},
-    {0xb98a, 0x0294, 0xc804, 0x1d1d, 0x10d6, 0x76e5, 0xb56d, 0xb643},
-    {0xa9ab, 0x8291, 0xf561, 0xb65a, 0x2485, 0x75b2, 0xb0e4, 0x1668},
-    {0x5844, 0x82b3, 0x9117, 0x11ab, 0x3ff7, 0x67af, 0x8413, 0xf74d},
-    {0x4865, 0x02b6, 0xac72, 0xbaec, 0x0ba4, 0x64f8, 0x819a, 0x5766},
-    {0x7806, 0x02bc, 0xebdd, 0xec62, 0x5751, 0x6101, 0x8f01, 0x1730},
-    {0x6827, 0x82b9, 0xd6b8, 0x4725, 0x6302, 0x6256, 0x8a88, 0xb71b},
-    {0x18c0, 0x02a8, 0x6483, 0x417e, 0xeebb, 0x6af3, 0x9237, 0x979c},
-    {0x08e1, 0x82ad, 0x59e6, 0xea39, 0xdae8, 0x69a4, 0x97be, 0x37b7},
-    {0x3882, 0x82a7, 0x1e49, 0xbcb7, 0x861d, 0x6c5d, 0x9925, 0x77e1},
-    {0x28a3, 0x02a2, 0x232c, 0x17f0, 0xb24e, 0x6f0a, 0x9cac, 0xd7ca},
-    {0xcb7d, 0x82e3, 0xd6a5, 0x5812, 0xb0f9, 0x4867, 0xf0cb, 0x1580},
-    {0xdb5c, 0x02e6, 0xebc0, 0xf355, 0x84aa, 0x4b30, 0xf542, 0xb5ab},
-    {0xeb3f, 0x02ec, 0xac6f, 0xa5db, 0xd85f, 0x4ec9, 0xfbd9, 0xf5fd},
-    {0xfb1e, 0x82e9, 0x910a, 0x0e9c, 0xec0c, 0x4d9e, 0xfe50, 0x55d6},
-    {0x8bf9, 0x02f8, 0x2331, 0x08c7, 0x61b5, 0x453b, 0xe6ef, 0x7551},
-    {0x9bd8, 0x82fd, 0x1e54, 0xa380, 0x55e6, 0x466c, 0xe366, 0xd57a},
-    {0xabbb, 0x82f7, 0x59fb, 0xf50e, 0x0913, 0x4395, 0xedfd, 0x952c},
-    {0xbb9a, 0x02f2, 0x649e, 0x5e49, 0x3d40, 0x40c2, 0xe874, 0x3507},
-    {0x4a75, 0x02d0, 0x00e8, 0xf9b8, 0x2632, 0x52df, 0xdc83, 0xd422},
-    {0x5a54, 0x82d5, 0x3d8d, 0x52ff, 0x1261, 0x5188, 0xd90a, 0x7409},
-    {0x6a37, 0x82df, 0x7a22, 0x0471, 0x4e94, 0x5471, 0xd791, 0x345f},
-    {0x7a16, 0x02da, 0x4747, 0xaf36, 0x7ac7, 0x5726, 0xd218, 0x9474},
-    {0x0af1, 0x82cb, 0xf57c, 0xa96d, 0xf77e, 0x5f83, 0xcaa7, 0xb4f3},
-    {0x1ad0, 0x02ce, 0xc819, 0x022a, 0xc32d, 0x5cd4, 0xcf2e, 0x14d8},
-    {0x2ab3, 0x02c4, 0x8fb6, 0x54a4, 0x9fd8, 0x592d, 0xc1b5, 0x548e},
-    {0x3a92, 0x82c1, 0xb2d3, 0xffe3, 0xab8b, 0x5a7a, 0xc43c, 0xf4a5},
-    {0xfd2e, 0x8243, 0x59c1, 0xcb60, 0x9ab6, 0x17f7, 0x197b, 0x7031},
-    {0xed0f, 0x0246, 0x64a4, 0x6027, 0xaee5, 0x14a0, 0x1cf2, 0xd01a},
-    {0xdd6c, 0x024c, 0x230b, 0x36a9, 0xf210, 0x1159, 0x1269, 0x904c},
-    {0xcd4d, 0x8249, 0x1e6e, 0x9dee, 0xc643, 0x120e, 0x17e0, 0x3067},
-    {0xbdaa, 0x0258, 0xac55, 0x9bb5, 0x4bfa, 0x1aab, 0x0f5f, 0x10e0},
-    {0xad8b, 0x825d, 0x9130, 0x30f2, 0x7fa9, 0x19fc, 0x0ad6, 0xb0cb},
-    {0x9de8, 0x8257, 0xd69f, 0x667c, 0x235c, 0x1c05, 0x044d, 0xf09d},
-    {0x8dc9, 0x0252, 0xebfa, 0xcd3b, 0x170f, 0x1f52, 0x01c4, 0x50b6},
-    {0x7c26, 0x0270, 0x8f8c, 0x6aca, 0x0c7d, 0x0d4f, 0x3533, 0xb193},
-    {0x6c07, 0x8275, 0xb2e9, 0xc18d, 0x382e, 0x0e18, 0x30ba, 0x11b8},
-    {0x5c64, 0x827f, 0xf546, 0x9703, 0x64db, 0x0be1, 0x3e21, 0x51ee},
-    {0x4c45, 0x027a, 0xc823, 0x3c44, 0x5088, 0x08b6, 0x3ba8, 0xf1c5},
-    {0x3ca2, 0x826b, 0x7a18, 0x3a1f, 0xdd31, 0x0013, 0x2317, 0xd142},
-    {0x2c83, 0x026e, 0x477d, 0x9158, 0xe962, 0x0344, 0x269e, 0x7169},
-    {0x1ce0, 0x0264, 0x00d2, 0xc7d6, 0xb597, 0x06bd, 0x2805, 0x313f},
-    {0x0cc1, 0x8261, 0x3db7, 0x6c91, 0x81c4, 0x05ea, 0x2d8c, 0x9114},
-    {0xef1f, 0x0220, 0xc83e, 0x2373, 0x8373, 0x2287, 0x41eb, 0x535e},
-    {0xff3e, 0x8225, 0xf55b, 0x8834, 0xb720, 0x21d0, 0x4462, 0xf375},
-    {0xcf5d, 0x822f, 0xb2f4, 0xdeba, 0xebd5, 0x2429, 0x4af9, 0xb323},
-    {0xdf7c, 0x022a, 0x8f91, 0x75fd, 0xdf86, 0x277e, 0x4f70, 0x1308},
-    {0xaf9b, 0x823b, 0x3daa, 0x73a6, 0x523f, 0x2fdb, 0x57cf, 0x338f},
-    {0xbfba, 0x023e, 0x00cf, 0xd8e1, 0x666c, 0x2c8c, 0x5246, 0x93a4},
-    {0x8fd9, 0x0234, 0x4760, 0x8e6f, 0x3a99, 0x2975, 0x5cdd, 0xd3f2},
-    {0x9ff8, 0x8231, 0x7a05, 0x2528, 0x0eca, 0x2a22, 0x5954, 0x73d9},
-    {0x6e17, 0x8213, 0x1e73, 0x82d9, 0x15b8, 0x383f, 0x6da3, 0x92fc},
-    {0x7e36, 0x0216, 0x2316, 0x299e, 0x21eb, 0x3b68, 0x682a, 0x32d7},
-    {0x4e55, 0x021c, 0x64b9, 0x7f10, 0x7d1e, 0x3e91, 0x66b1, 0x7281},
-    {0x5e74, 0x8219, 0x59dc, 0xd457, 0x494d, 0x3dc6, 0x6338, 0xd2aa},
-    {0x2e93, 0x0208, 0xebe7, 0xd20c, 0xc4f4, 0x3563, 0x7b87, 0xf22d},
-    {0x3eb2, 0x820d, 0xd682, 0x794b, 0xf0a7, 0x3634, 0x7e0e, 0x5206},
-    {0x0ed1, 0x8207, 0x912d, 0x2fc5, 0xac52, 0x33cd, 0x7095, 0x1250},
-    {0x1ef0, 0x0202, 0xac48, 0x8482, 0x9801, 0x309a, 0x751c, 0xb27b},
-};
-
-ZXIC_UINT32 dpp_crc32_calc(ZXIC_UINT8 *pInputKey, ZXIC_UINT32 dwByteNum, ZXIC_UINT32 dwCrcPoly)
-{
-    ZXIC_UINT32 dwResult = 0;
-    ZXIC_UINT32 dwDataType = 0;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-
-    while (i < dwByteNum)
-    {
-        dwDataType = (ZXIC_UINT32)((dwResult & 0xff000000) ^ (pInputKey[i] << 24));
-        for (j = 0; j < 8; j++)
-        {
-            if (dwDataType & 0x80000000)
-            {
-                dwDataType <<= 1;
-                dwDataType ^= dwCrcPoly;
-            }
-            else
-            {
-                dwDataType <<= 1;
-            }
-        }
-        dwResult <<= 8;
-        dwResult ^= dwDataType;
-
-        i++;
-    }
-
-    return dwResult;
-}
-
-ZXIC_UINT16 dpp_crc16_calc(ZXIC_UINT8 *pInputKey, ZXIC_UINT32 dwByteNum, ZXIC_UINT16 dwCrcPoly)
-{
-    ZXIC_UINT16 dwResult = 0;
-    ZXIC_UINT16 dwDataType = 0;
-
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-
-    while (i < dwByteNum)
-    {
-        dwDataType = (ZXIC_UINT16)(((dwResult & 0xff00) ^ (pInputKey[i] << 8)) & 0xFFFF);
-        for (j = 0; j < 8; j++)
-        {
-            if (dwDataType & 0x8000)
-            {
-                dwDataType <<= 1;
-                dwDataType ^= dwCrcPoly;
-            }
-            else
-            {
-                dwDataType <<= 1;
-            }
-        }
-        dwResult <<= 8;
-        dwResult ^= dwDataType;
-
-        i++;
-    }
-
-    return dwResult;
-}
-
-ZXIC_UINT16 dpp_crc16_get_idx(ZXIC_UINT16 crc_val)
-{
-    switch (crc_val)
-    {
-    case 0x1021:
-        return 0;
-    case 0x8005:
-        return 1;
-    case 0x3d65:
-        return 2;
-    case 0xab47:
-        return 3;
-    case 0x3453:
-        return 4;
-    case 0x0357:
-        return 5;
-    case 0x0589:
-        return 6;
-    case 0xa02b:
-        return 7;
-    default:
-        return 0xFFFF;
-    }
-}
-
-//查表法
-ZXIC_UINT16 dpp_crc16_table_lookup(ZXIC_UINT8 *pInputKey, ZXIC_UINT32 dwByteNum, ZXIC_UINT16 dwCrcPoly)
-{
-    ZXIC_UINT16 dwResult = 0;
-    ZXIC_UINT16 dwDataType = 0;
-    ZXIC_UINT16 tmp_index = 0;
-    ZXIC_UINT32 i = 0;
-
-    ZXIC_UINT32 crc_idx = dpp_crc16_get_idx(dwCrcPoly);
-
-    ZXIC_COMM_CHECK_INDEX(crc_idx, 0, 7);
-
-    while (i < dwByteNum)
-    {
-        dwDataType = ((dwResult & 0xff00) ^ (pInputKey[i] << 8)) & 0xFFFF;
-
-        tmp_index = dwDataType >> 8;
-        tmp_index = tmp_index & 0xff;
-        ZXIC_COMM_CHECK_INDEX(tmp_index, 0, 255);
-        ZXIC_COMM_CHECK_INDEX(crc_idx, 0, 7);
-        dwDataType = g_crc16_rst[tmp_index][crc_idx];
-
-        dwResult <<= 8;
-        dwResult ^= dwDataType;
-
-        i++;
-    }
-
-    return dwResult;
-}
+#include "zxic_common.h"
+#include "dpp_hash_crc.h"
+
+ZXIC_UINT16 g_crc16_rst[256][8] = {
+	{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0x1021, 0x8005, 0x3d65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b },
+	{ 0x2042, 0x800f, 0x7aca, 0xfdc9, 0x68a6, 0x06ae, 0x0b12, 0xe07d },
+	{ 0x3063, 0x000a, 0x47af, 0x568e, 0x5cf5, 0x05f9, 0x0e9b, 0x4056 },
+	{ 0x4084, 0x801b, 0xf594, 0x50d5, 0xd14c, 0x0d5c, 0x1624, 0x60d1 },
+	{ 0x50a5, 0x001e, 0xc8f1, 0xfb92, 0xe51f, 0x0e0b, 0x13ad, 0xc0fa },
+	{ 0x60c6, 0x0014, 0x8f5e, 0xad1c, 0xb9ea, 0x0bf2, 0x1d36, 0x80ac },
+	{ 0x70e7, 0x8011, 0xb23b, 0x065b, 0x8db9, 0x08a5, 0x18bf, 0x2087 },
+	{ 0x8108, 0x8033, 0xd64d, 0xa1aa, 0x96cb, 0x1ab8, 0x2c48, 0xc1a2 },
+	{ 0x9129, 0x0036, 0xeb28, 0x0aed, 0xa298, 0x19ef, 0x29c1, 0x6189 },
+	{ 0xa14a, 0x003c, 0xac87, 0x5c63, 0xfe6d, 0x1c16, 0x275a, 0x21df },
+	{ 0xb16b, 0x8039, 0x91e2, 0xf724, 0xca3e, 0x1f41, 0x22d3, 0x81f4 },
+	{ 0xc18c, 0x0028, 0x23d9, 0xf17f, 0x4787, 0x17e4, 0x3a6c, 0xa173 },
+	{ 0xd1ad, 0x802d, 0x1ebc, 0x5a38, 0x73d4, 0x14b3, 0x3fe5, 0x0158 },
+	{ 0xe1ce, 0x8027, 0x5913, 0x0cb6, 0x2f21, 0x114a, 0x317e, 0x410e },
+	{ 0xf1ef, 0x0022, 0x6476, 0xa7f1, 0x1b72, 0x121d, 0x34f7, 0xe125 },
+	{ 0x1231, 0x8063, 0x91ff, 0xe813, 0x19c5, 0x3570, 0x5890, 0x236f },
+	{ 0x0210, 0x0066, 0xac9a, 0x4354, 0x2d96, 0x3627, 0x5d19, 0x8344 },
+	{ 0x3273, 0x006c, 0xeb35, 0x15da, 0x7163, 0x33de, 0x5382, 0xc312 },
+	{ 0x2252, 0x8069, 0xd650, 0xbe9d, 0x4530, 0x3089, 0x560b, 0x6339 },
+	{ 0x52b5, 0x0078, 0x646b, 0xb8c6, 0xc889, 0x382c, 0x4eb4, 0x43be },
+	{ 0x4294, 0x807d, 0x590e, 0x1381, 0xfcda, 0x3b7b, 0x4b3d, 0xe395 },
+	{ 0x72f7, 0x8077, 0x1ea1, 0x450f, 0xa02f, 0x3e82, 0x45a6, 0xa3c3 },
+	{ 0x62d6, 0x0072, 0x23c4, 0xee48, 0x947c, 0x3dd5, 0x402f, 0x03e8 },
+	{ 0x9339, 0x0050, 0x47b2, 0x49b9, 0x8f0e, 0x2fc8, 0x74d8, 0xe2cd },
+	{ 0x8318, 0x8055, 0x7ad7, 0xe2fe, 0xbb5d, 0x2c9f, 0x7151, 0x42e6 },
+	{ 0xb37b, 0x805f, 0x3d78, 0xb470, 0xe7a8, 0x2966, 0x7fca, 0x02b0 },
+	{ 0xa35a, 0x005a, 0x001d, 0x1f37, 0xd3fb, 0x2a31, 0x7a43, 0xa29b },
+	{ 0xd3bd, 0x804b, 0xb226, 0x196c, 0x5e42, 0x2294, 0x62fc, 0x821c },
+	{ 0xc39c, 0x004e, 0x8f43, 0xb22b, 0x6a11, 0x21c3, 0x6775, 0x2237 },
+	{ 0xf3ff, 0x0044, 0xc8ec, 0xe4a5, 0x36e4, 0x243a, 0x69ee, 0x6261 },
+	{ 0xe3de, 0x8041, 0xf589, 0x4fe2, 0x02b7, 0x276d, 0x6c67, 0xc24a },
+	{ 0x2462, 0x80c3, 0x1e9b, 0x7b61, 0x338a, 0x6ae0, 0xb120, 0x46de },
+	{ 0x3443, 0x00c6, 0x23fe, 0xd026, 0x07d9, 0x69b7, 0xb4a9, 0xe6f5 },
+	{ 0x0420, 0x00cc, 0x6451, 0x86a8, 0x5b2c, 0x6c4e, 0xba32, 0xa6a3 },
+	{ 0x1401, 0x80c9, 0x5934, 0x2def, 0x6f7f, 0x6f19, 0xbfbb, 0x0688 },
+	{ 0x64e6, 0x00d8, 0xeb0f, 0x2bb4, 0xe2c6, 0x67bc, 0xa704, 0x260f },
+	{ 0x74c7, 0x80dd, 0xd66a, 0x80f3, 0xd695, 0x64eb, 0xa28d, 0x8624 },
+	{ 0x44a4, 0x80d7, 0x91c5, 0xd67d, 0x8a60, 0x6112, 0xac16, 0xc672 },
+	{ 0x5485, 0x00d2, 0xaca0, 0x7d3a, 0xbe33, 0x6245, 0xa99f, 0x6659 },
+	{ 0xa56a, 0x00f0, 0xc8d6, 0xdacb, 0xa541, 0x7058, 0x9d68, 0x877c },
+	{ 0xb54b, 0x80f5, 0xf5b3, 0x718c, 0x9112, 0x730f, 0x98e1, 0x2757 },
+	{ 0x8528, 0x80ff, 0xb21c, 0x2702, 0xcde7, 0x76f6, 0x967a, 0x6701 },
+	{ 0x9509, 0x00fa, 0x8f79, 0x8c45, 0xf9b4, 0x75a1, 0x93f3, 0xc72a },
+	{ 0xe5ee, 0x80eb, 0x3d42, 0x8a1e, 0x740d, 0x7d04, 0x8b4c, 0xe7ad },
+	{ 0xf5cf, 0x00ee, 0x0027, 0x2159, 0x405e, 0x7e53, 0x8ec5, 0x4786 },
+	{ 0xc5ac, 0x00e4, 0x4788, 0x77d7, 0x1cab, 0x7baa, 0x805e, 0x07d0 },
+	{ 0xd58d, 0x80e1, 0x7aed, 0xdc90, 0x28f8, 0x78fd, 0x85d7, 0xa7fb },
+	{ 0x3653, 0x00a0, 0x8f64, 0x9372, 0x2a4f, 0x5f90, 0xe9b0, 0x65b1 },
+	{ 0x2672, 0x80a5, 0xb201, 0x3835, 0x1e1c, 0x5cc7, 0xec39, 0xc59a },
+	{ 0x1611, 0x80af, 0xf5ae, 0x6ebb, 0x42e9, 0x593e, 0xe2a2, 0x85cc },
+	{ 0x0630, 0x00aa, 0xc8cb, 0xc5fc, 0x76ba, 0x5a69, 0xe72b, 0x25e7 },
+	{ 0x76d7, 0x80bb, 0x7af0, 0xc3a7, 0xfb03, 0x52cc, 0xff94, 0x0560 },
+	{ 0x66f6, 0x00be, 0x4795, 0x68e0, 0xcf50, 0x519b, 0xfa1d, 0xa54b },
+	{ 0x5695, 0x00b4, 0x003a, 0x3e6e, 0x93a5, 0x5462, 0xf486, 0xe51d },
+	{ 0x46b4, 0x80b1, 0x3d5f, 0x9529, 0xa7f6, 0x5735, 0xf10f, 0x4536 },
+	{ 0xb75b, 0x8093, 0x5929, 0x32d8, 0xbc84, 0x4528, 0xc5f8, 0xa413 },
+	{ 0xa77a, 0x0096, 0x644c, 0x999f, 0x88d7, 0x467f, 0xc071, 0x0438 },
+	{ 0x9719, 0x009c, 0x23e3, 0xcf11, 0xd422, 0x4386, 0xceea, 0x446e },
+	{ 0x8738, 0x8099, 0x1e86, 0x6456, 0xe071, 0x40d1, 0xcb63, 0xe445 },
+	{ 0xf7df, 0x0088, 0xacbd, 0x620d, 0x6dc8, 0x4874, 0xd3dc, 0xc4c2 },
+	{ 0xe7fe, 0x808d, 0x91d8, 0xc94a, 0x599b, 0x4b23, 0xd655, 0x64e9 },
+	{ 0xd79d, 0x8087, 0xd677, 0x9fc4, 0x056e, 0x4eda, 0xd8ce, 0x24bf },
+	{ 0xc7bc, 0x0082, 0xeb12, 0x3483, 0x313d, 0x4d8d, 0xdd47, 0x8494 },
+	{ 0x48c4, 0x8183, 0x3d36, 0xf6c2, 0x6714, 0xd5c0, 0x67c9, 0x8dbc },
+	{ 0x58e5, 0x0186, 0x0053, 0x5d85, 0x5347, 0xd697, 0x6240, 0x2d97 },
+	{ 0x6886, 0x018c, 0x47fc, 0x0b0b, 0x0fb2, 0xd36e, 0x6cdb, 0x6dc1 },
+	{ 0x78a7, 0x8189, 0x7a99, 0xa04c, 0x3be1, 0xd039, 0x6952, 0xcdea },
+	{ 0x0840, 0x0198, 0xc8a2, 0xa617, 0xb658, 0xd89c, 0x71ed, 0xed6d },
+	{ 0x1861, 0x819d, 0xf5c7, 0x0d50, 0x820b, 0xdbcb, 0x7464, 0x4d46 },
+	{ 0x2802, 0x8197, 0xb268, 0x5bde, 0xdefe, 0xde32, 0x7aff, 0x0d10 },
+	{ 0x3823, 0x0192, 0x8f0d, 0xf099, 0xeaad, 0xdd65, 0x7f76, 0xad3b },
+	{ 0xc9cc, 0x01b0, 0xeb7b, 0x5768, 0xf1df, 0xcf78, 0x4b81, 0x4c1e },
+	{ 0xd9ed, 0x81b5, 0xd61e, 0xfc2f, 0xc58c, 0xcc2f, 0x4e08, 0xec35 },
+	{ 0xe98e, 0x81bf, 0x91b1, 0xaaa1, 0x9979, 0xc9d6, 0x4093, 0xac63 },
+	{ 0xf9af, 0x01ba, 0xacd4, 0x01e6, 0xad2a, 0xca81, 0x451a, 0x0c48 },
+	{ 0x8948, 0x81ab, 0x1eef, 0x07bd, 0x2093, 0xc224, 0x5da5, 0x2ccf },
+	{ 0x9969, 0x01ae, 0x238a, 0xacfa, 0x14c0, 0xc173, 0x582c, 0x8ce4 },
+	{ 0xa90a, 0x01a4, 0x6425, 0xfa74, 0x4835, 0xc48a, 0x56b7, 0xccb2 },
+	{ 0xb92b, 0x81a1, 0x5940, 0x5133, 0x7c66, 0xc7dd, 0x533e, 0x6c99 },
+	{ 0x5af5, 0x01e0, 0xacc9, 0x1ed1, 0x7ed1, 0xe0b0, 0x3f59, 0xaed3 },
+	{ 0x4ad4, 0x81e5, 0x91ac, 0xb596, 0x4a82, 0xe3e7, 0x3ad0, 0x0ef8 },
+	{ 0x7ab7, 0x81ef, 0xd603, 0xe318, 0x1677, 0xe61e, 0x344b, 0x4eae },
+	{ 0x6a96, 0x01ea, 0xeb66, 0x485f, 0x2224, 0xe549, 0x31c2, 0xee85 },
+	{ 0x1a71, 0x81fb, 0x595d, 0x4e04, 0xaf9d, 0xedec, 0x297d, 0xce02 },
+	{ 0x0a50, 0x01fe, 0x6438, 0xe543, 0x9bce, 0xeebb, 0x2cf4, 0x6e29 },
+	{ 0x3a33, 0x01f4, 0x2397, 0xb3cd, 0xc73b, 0xeb42, 0x226f, 0x2e7f },
+	{ 0x2a12, 0x81f1, 0x1ef2, 0x188a, 0xf368, 0xe815, 0x27e6, 0x8e54 },
+	{ 0xdbfd, 0x81d3, 0x7a84, 0xbf7b, 0xe81a, 0xfa08, 0x1311, 0x6f71 },
+	{ 0xcbdc, 0x01d6, 0x47e1, 0x143c, 0xdc49, 0xf95f, 0x1698, 0xcf5a },
+	{ 0xfbbf, 0x01dc, 0x004e, 0x42b2, 0x80bc, 0xfca6, 0x1803, 0x8f0c },
+	{ 0xeb9e, 0x81d9, 0x3d2b, 0xe9f5, 0xb4ef, 0xfff1, 0x1d8a, 0x2f27 },
+	{ 0x9b79, 0x01c8, 0x8f10, 0xefae, 0x3956, 0xf754, 0x0535, 0x0fa0 },
+	{ 0x8b58, 0x81cd, 0xb275, 0x44e9, 0x0d05, 0xf403, 0x00bc, 0xaf8b },
+	{ 0xbb3b, 0x81c7, 0xf5da, 0x1267, 0x51f0, 0xf1fa, 0x0e27, 0xefdd },
+	{ 0xab1a, 0x01c2, 0xc8bf, 0xb920, 0x65a3, 0xf2ad, 0x0bae, 0x4ff6 },
+	{ 0x6ca6, 0x0140, 0x23ad, 0x8da3, 0x549e, 0xbf20, 0xd6e9, 0xcb62 },
+	{ 0x7c87, 0x8145, 0x1ec8, 0x26e4, 0x60cd, 0xbc77, 0xd360, 0x6b49 },
+	{ 0x4ce4, 0x814f, 0x5967, 0x706a, 0x3c38, 0xb98e, 0xddfb, 0x2b1f },
+	{ 0x5cc5, 0x014a, 0x6402, 0xdb2d, 0x086b, 0xbad9, 0xd872, 0x8b34 },
+	{ 0x2c22, 0x815b, 0xd639, 0xdd76, 0x85d2, 0xb27c, 0xc0cd, 0xabb3 },
+	{ 0x3c03, 0x015e, 0xeb5c, 0x7631, 0xb181, 0xb12b, 0xc544, 0x0b98 },
+	{ 0x0c60, 0x0154, 0xacf3, 0x20bf, 0xed74, 0xb4d2, 0xcbdf, 0x4bce },
+	{ 0x1c41, 0x8151, 0x9196, 0x8bf8, 0xd927, 0xb785, 0xce56, 0xebe5 },
+	{ 0xedae, 0x8173, 0xf5e0, 0x2c09, 0xc255, 0xa598, 0xfaa1, 0x0ac0 },
+	{ 0xfd8f, 0x0176, 0xc885, 0x874e, 0xf606, 0xa6cf, 0xff28, 0xaaeb },
+	{ 0xcdec, 0x017c, 0x8f2a, 0xd1c0, 0xaaf3, 0xa336, 0xf1b3, 0xeabd },
+	{ 0xddcd, 0x8179, 0xb24f, 0x7a87, 0x9ea0, 0xa061, 0xf43a, 0x4a96 },
+	{ 0xad2a, 0x0168, 0x0074, 0x7cdc, 0x1319, 0xa8c4, 0xec85, 0x6a11 },
+	{ 0xbd0b, 0x816d, 0x3d11, 0xd79b, 0x274a, 0xab93, 0xe90c, 0xca3a },
+	{ 0x8d68, 0x8167, 0x7abe, 0x8115, 0x7bbf, 0xae6a, 0xe797, 0x8a6c },
+	{ 0x9d49, 0x0162, 0x47db, 0x2a52, 0x4fec, 0xad3d, 0xe21e, 0x2a47 },
+	{ 0x7e97, 0x8123, 0xb252, 0x65b0, 0x4d5b, 0x8a50, 0x8e79, 0xe80d },
+	{ 0x6eb6, 0x0126, 0x8f37, 0xcef7, 0x7908, 0x8907, 0x8bf0, 0x4826 },
+	{ 0x5ed5, 0x012c, 0xc898, 0x9879, 0x25fd, 0x8cfe, 0x856b, 0x0870 },
+	{ 0x4ef4, 0x8129, 0xf5fd, 0x333e, 0x11ae, 0x8fa9, 0x80e2, 0xa85b },
+	{ 0x3e13, 0x0138, 0x47c6, 0x3565, 0x9c17, 0x870c, 0x985d, 0x88dc },
+	{ 0x2e32, 0x813d, 0x7aa3, 0x9e22, 0xa844, 0x845b, 0x9dd4, 0x28f7 },
+	{ 0x1e51, 0x8137, 0x3d0c, 0xc8ac, 0xf4b1, 0x81a2, 0x934f, 0x68a1 },
+	{ 0x0e70, 0x0132, 0x0069, 0x63eb, 0xc0e2, 0x82f5, 0x96c6, 0xc88a },
+	{ 0xff9f, 0x0110, 0x641f, 0xc41a, 0xdb90, 0x90e8, 0xa231, 0x29af },
+	{ 0xefbe, 0x8115, 0x597a, 0x6f5d, 0xefc3, 0x93bf, 0xa7b8, 0x8984 },
+	{ 0xdfdd, 0x811f, 0x1ed5, 0x39d3, 0xb336, 0x9646, 0xa923, 0xc9d2 },
+	{ 0xcffc, 0x011a, 0x23b0, 0x9294, 0x8765, 0x9511, 0xacaa, 0x69f9 },
+	{ 0xbf1b, 0x810b, 0x918b, 0x94cf, 0x0adc, 0x9db4, 0xb415, 0x497e },
+	{ 0xaf3a, 0x010e, 0xacee, 0x3f88, 0x3e8f, 0x9ee3, 0xb19c, 0xe955 },
+	{ 0x9f59, 0x0104, 0xeb41, 0x6906, 0x627a, 0x9b1a, 0xbf07, 0xa903 },
+	{ 0x8f78, 0x8101, 0xd624, 0xc241, 0x5629, 0x984d, 0xba8e, 0x0928 },
+	{ 0x9188, 0x8303, 0x7a6c, 0x46c3, 0xce28, 0xa8d7, 0xcf92, 0xbb53 },
+	{ 0x81a9, 0x0306, 0x4709, 0xed84, 0xfa7b, 0xab80, 0xca1b, 0x1b78 },
+	{ 0xb1ca, 0x030c, 0x00a6, 0xbb0a, 0xa68e, 0xae79, 0xc480, 0x5b2e },
+	{ 0xa1eb, 0x8309, 0x3dc3, 0x104d, 0x92dd, 0xad2e, 0xc109, 0xfb05 },
+	{ 0xd10c, 0x0318, 0x8ff8, 0x1616, 0x1f64, 0xa58b, 0xd9b6, 0xdb82 },
+	{ 0xc12d, 0x831d, 0xb29d, 0xbd51, 0x2b37, 0xa6dc, 0xdc3f, 0x7ba9 },
+	{ 0xf14e, 0x8317, 0xf532, 0xebdf, 0x77c2, 0xa325, 0xd2a4, 0x3bff },
+	{ 0xe16f, 0x0312, 0xc857, 0x4098, 0x4391, 0xa072, 0xd72d, 0x9bd4 },
+	{ 0x1080, 0x0330, 0xac21, 0xe769, 0x58e3, 0xb26f, 0xe3da, 0x7af1 },
+	{ 0x00a1, 0x8335, 0x9144, 0x4c2e, 0x6cb0, 0xb138, 0xe653, 0xdada },
+	{ 0x30c2, 0x833f, 0xd6eb, 0x1aa0, 0x3045, 0xb4c1, 0xe8c8, 0x9a8c },
+	{ 0x20e3, 0x033a, 0xeb8e, 0xb1e7, 0x0416, 0xb796, 0xed41, 0x3aa7 },
+	{ 0x5004, 0x832b, 0x59b5, 0xb7bc, 0x89af, 0xbf33, 0xf5fe, 0x1a20 },
+	{ 0x4025, 0x032e, 0x64d0, 0x1cfb, 0xbdfc, 0xbc64, 0xf077, 0xba0b },
+	{ 0x7046, 0x0324, 0x237f, 0x4a75, 0xe109, 0xb99d, 0xfeec, 0xfa5d },
+	{ 0x6067, 0x8321, 0x1e1a, 0xe132, 0xd55a, 0xbaca, 0xfb65, 0x5a76 },
+	{ 0x83b9, 0x0360, 0xeb93, 0xaed0, 0xd7ed, 0x9da7, 0x9702, 0x983c },
+	{ 0x9398, 0x8365, 0xd6f6, 0x0597, 0xe3be, 0x9ef0, 0x928b, 0x3817 },
+	{ 0xa3fb, 0x836f, 0x9159, 0x5319, 0xbf4b, 0x9b09, 0x9c10, 0x7841 },
+	{ 0xb3da, 0x036a, 0xac3c, 0xf85e, 0x8b18, 0x985e, 0x9999, 0xd86a },
+	{ 0xc33d, 0x837b, 0x1e07, 0xfe05, 0x06a1, 0x90fb, 0x8126, 0xf8ed },
+	{ 0xd31c, 0x037e, 0x2362, 0x5542, 0x32f2, 0x93ac, 0x84af, 0x58c6 },
+	{ 0xe37f, 0x0374, 0x64cd, 0x03cc, 0x6e07, 0x9655, 0x8a34, 0x1890 },
+	{ 0xf35e, 0x8371, 0x59a8, 0xa88b, 0x5a54, 0x9502, 0x8fbd, 0xb8bb },
+	{ 0x02b1, 0x8353, 0x3dde, 0x0f7a, 0x4126, 0x871f, 0xbb4a, 0x599e },
+	{ 0x1290, 0x0356, 0x00bb, 0xa43d, 0x7575, 0x8448, 0xbec3, 0xf9b5 },
+	{ 0x22f3, 0x035c, 0x4714, 0xf2b3, 0x2980, 0x81b1, 0xb058, 0xb9e3 },
+	{ 0x32d2, 0x8359, 0x7a71, 0x59f4, 0x1dd3, 0x82e6, 0xb5d1, 0x19c8 },
+	{ 0x4235, 0x0348, 0xc84a, 0x5faf, 0x906a, 0x8a43, 0xad6e, 0x394f },
+	{ 0x5214, 0x834d, 0xf52f, 0xf4e8, 0xa439, 0x8914, 0xa8e7, 0x9964 },
+	{ 0x6277, 0x8347, 0xb280, 0xa266, 0xf8cc, 0x8ced, 0xa67c, 0xd932 },
+	{ 0x7256, 0x0342, 0x8fe5, 0x0921, 0xcc9f, 0x8fba, 0xa3f5, 0x7919 },
+	{ 0xb5ea, 0x03c0, 0x64f7, 0x3da2, 0xfda2, 0xc237, 0x7eb2, 0xfd8d },
+	{ 0xa5cb, 0x83c5, 0x5992, 0x96e5, 0xc9f1, 0xc160, 0x7b3b, 0x5da6 },
+	{ 0x95a8, 0x83cf, 0x1e3d, 0xc06b, 0x9504, 0xc499, 0x75a0, 0x1df0 },
+	{ 0x8589, 0x03ca, 0x2358, 0x6b2c, 0xa157, 0xc7ce, 0x7029, 0xbddb },
+	{ 0xf56e, 0x83db, 0x9163, 0x6d77, 0x2cee, 0xcf6b, 0x6896, 0x9d5c },
+	{ 0xe54f, 0x03de, 0xac06, 0xc630, 0x18bd, 0xcc3c, 0x6d1f, 0x3d77 },
+	{ 0xd52c, 0x03d4, 0xeba9, 0x90be, 0x4448, 0xc9c5, 0x6384, 0x7d21 },
+	{ 0xc50d, 0x83d1, 0xd6cc, 0x3bf9, 0x701b, 0xca92, 0x660d, 0xdd0a },
+	{ 0x34e2, 0x83f3, 0xb2ba, 0x9c08, 0x6b69, 0xd88f, 0x52fa, 0x3c2f },
+	{ 0x24c3, 0x03f6, 0x8fdf, 0x374f, 0x5f3a, 0xdbd8, 0x5773, 0x9c04 },
+	{ 0x14a0, 0x03fc, 0xc870, 0x61c1, 0x03cf, 0xde21, 0x59e8, 0xdc52 },
+	{ 0x0481, 0x83f9, 0xf515, 0xca86, 0x379c, 0xdd76, 0x5c61, 0x7c79 },
+	{ 0x7466, 0x03e8, 0x472e, 0xccdd, 0xba25, 0xd5d3, 0x44de, 0x5cfe },
+	{ 0x6447, 0x83ed, 0x7a4b, 0x679a, 0x8e76, 0xd684, 0x4157, 0xfcd5 },
+	{ 0x5424, 0x83e7, 0x3de4, 0x3114, 0xd283, 0xd37d, 0x4fcc, 0xbc83 },
+	{ 0x4405, 0x03e2, 0x0081, 0x9a53, 0xe6d0, 0xd02a, 0x4a45, 0x1ca8 },
+	{ 0xa7db, 0x83a3, 0xf508, 0xd5b1, 0xe467, 0xf747, 0x2622, 0xdee2 },
+	{ 0xb7fa, 0x03a6, 0xc86d, 0x7ef6, 0xd034, 0xf410, 0x23ab, 0x7ec9 },
+	{ 0x8799, 0x03ac, 0x8fc2, 0x2878, 0x8cc1, 0xf1e9, 0x2d30, 0x3e9f },
+	{ 0x97b8, 0x83a9, 0xb2a7, 0x833f, 0xb892, 0xf2be, 0x28b9, 0x9eb4 },
+	{ 0xe75f, 0x03b8, 0x009c, 0x8564, 0x352b, 0xfa1b, 0x3006, 0xbe33 },
+	{ 0xf77e, 0x83bd, 0x3df9, 0x2e23, 0x0178, 0xf94c, 0x358f, 0x1e18 },
+	{ 0xc71d, 0x83b7, 0x7a56, 0x78ad, 0x5d8d, 0xfcb5, 0x3b14, 0x5e4e },
+	{ 0xd73c, 0x03b2, 0x4733, 0xd3ea, 0x69de, 0xffe2, 0x3e9d, 0xfe65 },
+	{ 0x26d3, 0x0390, 0x2345, 0x741b, 0x72ac, 0xedff, 0x0a6a, 0x1f40 },
+	{ 0x36f2, 0x8395, 0x1e20, 0xdf5c, 0x46ff, 0xeea8, 0x0fe3, 0xbf6b },
+	{ 0x0691, 0x839f, 0x598f, 0x89d2, 0x1a0a, 0xeb51, 0x0178, 0xff3d },
+	{ 0x16b0, 0x039a, 0x64ea, 0x2295, 0x2e59, 0xe806, 0x04f1, 0x5f16 },
+	{ 0x6657, 0x838b, 0xd6d1, 0x24ce, 0xa3e0, 0xe0a3, 0x1c4e, 0x7f91 },
+	{ 0x7676, 0x038e, 0xebb4, 0x8f89, 0x97b3, 0xe3f4, 0x19c7, 0xdfba },
+	{ 0x4615, 0x0384, 0xac1b, 0xd907, 0xcb46, 0xe60d, 0x175c, 0x9fec },
+	{ 0x5634, 0x8381, 0x917e, 0x7240, 0xff15, 0xe55a, 0x12d5, 0x3fc7 },
+	{ 0xd94c, 0x0280, 0x475a, 0xb001, 0xa93c, 0x7d17, 0xa85b, 0x36ef },
+	{ 0xc96d, 0x8285, 0x7a3f, 0x1b46, 0x9d6f, 0x7e40, 0xadd2, 0x96c4 },
+	{ 0xf90e, 0x828f, 0x3d90, 0x4dc8, 0xc19a, 0x7bb9, 0xa349, 0xd692 },
+	{ 0xe92f, 0x028a, 0x00f5, 0xe68f, 0xf5c9, 0x78ee, 0xa6c0, 0x76b9 },
+	{ 0x99c8, 0x829b, 0xb2ce, 0xe0d4, 0x7870, 0x704b, 0xbe7f, 0x563e },
+	{ 0x89e9, 0x029e, 0x8fab, 0x4b93, 0x4c23, 0x731c, 0xbbf6, 0xf615 },
+	{ 0xb98a, 0x0294, 0xc804, 0x1d1d, 0x10d6, 0x76e5, 0xb56d, 0xb643 },
+	{ 0xa9ab, 0x8291, 0xf561, 0xb65a, 0x2485, 0x75b2, 0xb0e4, 0x1668 },
+	{ 0x5844, 0x82b3, 0x9117, 0x11ab, 0x3ff7, 0x67af, 0x8413, 0xf74d },
+	{ 0x4865, 0x02b6, 0xac72, 0xbaec, 0x0ba4, 0x64f8, 0x819a, 0x5766 },
+	{ 0x7806, 0x02bc, 0xebdd, 0xec62, 0x5751, 0x6101, 0x8f01, 0x1730 },
+	{ 0x6827, 0x82b9, 0xd6b8, 0x4725, 0x6302, 0x6256, 0x8a88, 0xb71b },
+	{ 0x18c0, 0x02a8, 0x6483, 0x417e, 0xeebb, 0x6af3, 0x9237, 0x979c },
+	{ 0x08e1, 0x82ad, 0x59e6, 0xea39, 0xdae8, 0x69a4, 0x97be, 0x37b7 },
+	{ 0x3882, 0x82a7, 0x1e49, 0xbcb7, 0x861d, 0x6c5d, 0x9925, 0x77e1 },
+	{ 0x28a3, 0x02a2, 0x232c, 0x17f0, 0xb24e, 0x6f0a, 0x9cac, 0xd7ca },
+	{ 0xcb7d, 0x82e3, 0xd6a5, 0x5812, 0xb0f9, 0x4867, 0xf0cb, 0x1580 },
+	{ 0xdb5c, 0x02e6, 0xebc0, 0xf355, 0x84aa, 0x4b30, 0xf542, 0xb5ab },
+	{ 0xeb3f, 0x02ec, 0xac6f, 0xa5db, 0xd85f, 0x4ec9, 0xfbd9, 0xf5fd },
+	{ 0xfb1e, 0x82e9, 0x910a, 0x0e9c, 0xec0c, 0x4d9e, 0xfe50, 0x55d6 },
+	{ 0x8bf9, 0x02f8, 0x2331, 0x08c7, 0x61b5, 0x453b, 0xe6ef, 0x7551 },
+	{ 0x9bd8, 0x82fd, 0x1e54, 0xa380, 0x55e6, 0x466c, 0xe366, 0xd57a },
+	{ 0xabbb, 0x82f7, 0x59fb, 0xf50e, 0x0913, 0x4395, 0xedfd, 0x952c },
+	{ 0xbb9a, 0x02f2, 0x649e, 0x5e49, 0x3d40, 0x40c2, 0xe874, 0x3507 },
+	{ 0x4a75, 0x02d0, 0x00e8, 0xf9b8, 0x2632, 0x52df, 0xdc83, 0xd422 },
+	{ 0x5a54, 0x82d5, 0x3d8d, 0x52ff, 0x1261, 0x5188, 0xd90a, 0x7409 },
+	{ 0x6a37, 0x82df, 0x7a22, 0x0471, 0x4e94, 0x5471, 0xd791, 0x345f },
+	{ 0x7a16, 0x02da, 0x4747, 0xaf36, 0x7ac7, 0x5726, 0xd218, 0x9474 },
+	{ 0x0af1, 0x82cb, 0xf57c, 0xa96d, 0xf77e, 0x5f83, 0xcaa7, 0xb4f3 },
+	{ 0x1ad0, 0x02ce, 0xc819, 0x022a, 0xc32d, 0x5cd4, 0xcf2e, 0x14d8 },
+	{ 0x2ab3, 0x02c4, 0x8fb6, 0x54a4, 0x9fd8, 0x592d, 0xc1b5, 0x548e },
+	{ 0x3a92, 0x82c1, 0xb2d3, 0xffe3, 0xab8b, 0x5a7a, 0xc43c, 0xf4a5 },
+	{ 0xfd2e, 0x8243, 0x59c1, 0xcb60, 0x9ab6, 0x17f7, 0x197b, 0x7031 },
+	{ 0xed0f, 0x0246, 0x64a4, 0x6027, 0xaee5, 0x14a0, 0x1cf2, 0xd01a },
+	{ 0xdd6c, 0x024c, 0x230b, 0x36a9, 0xf210, 0x1159, 0x1269, 0x904c },
+	{ 0xcd4d, 0x8249, 0x1e6e, 0x9dee, 0xc643, 0x120e, 0x17e0, 0x3067 },
+	{ 0xbdaa, 0x0258, 0xac55, 0x9bb5, 0x4bfa, 0x1aab, 0x0f5f, 0x10e0 },
+	{ 0xad8b, 0x825d, 0x9130, 0x30f2, 0x7fa9, 0x19fc, 0x0ad6, 0xb0cb },
+	{ 0x9de8, 0x8257, 0xd69f, 0x667c, 0x235c, 0x1c05, 0x044d, 0xf09d },
+	{ 0x8dc9, 0x0252, 0xebfa, 0xcd3b, 0x170f, 0x1f52, 0x01c4, 0x50b6 },
+	{ 0x7c26, 0x0270, 0x8f8c, 0x6aca, 0x0c7d, 0x0d4f, 0x3533, 0xb193 },
+	{ 0x6c07, 0x8275, 0xb2e9, 0xc18d, 0x382e, 0x0e18, 0x30ba, 0x11b8 },
+	{ 0x5c64, 0x827f, 0xf546, 0x9703, 0x64db, 0x0be1, 0x3e21, 0x51ee },
+	{ 0x4c45, 0x027a, 0xc823, 0x3c44, 0x5088, 0x08b6, 0x3ba8, 0xf1c5 },
+	{ 0x3ca2, 0x826b, 0x7a18, 0x3a1f, 0xdd31, 0x0013, 0x2317, 0xd142 },
+	{ 0x2c83, 0x026e, 0x477d, 0x9158, 0xe962, 0x0344, 0x269e, 0x7169 },
+	{ 0x1ce0, 0x0264, 0x00d2, 0xc7d6, 0xb597, 0x06bd, 0x2805, 0x313f },
+	{ 0x0cc1, 0x8261, 0x3db7, 0x6c91, 0x81c4, 0x05ea, 0x2d8c, 0x9114 },
+	{ 0xef1f, 0x0220, 0xc83e, 0x2373, 0x8373, 0x2287, 0x41eb, 0x535e },
+	{ 0xff3e, 0x8225, 0xf55b, 0x8834, 0xb720, 0x21d0, 0x4462, 0xf375 },
+	{ 0xcf5d, 0x822f, 0xb2f4, 0xdeba, 0xebd5, 0x2429, 0x4af9, 0xb323 },
+	{ 0xdf7c, 0x022a, 0x8f91, 0x75fd, 0xdf86, 0x277e, 0x4f70, 0x1308 },
+	{ 0xaf9b, 0x823b, 0x3daa, 0x73a6, 0x523f, 0x2fdb, 0x57cf, 0x338f },
+	{ 0xbfba, 0x023e, 0x00cf, 0xd8e1, 0x666c, 0x2c8c, 0x5246, 0x93a4 },
+	{ 0x8fd9, 0x0234, 0x4760, 0x8e6f, 0x3a99, 0x2975, 0x5cdd, 0xd3f2 },
+	{ 0x9ff8, 0x8231, 0x7a05, 0x2528, 0x0eca, 0x2a22, 0x5954, 0x73d9 },
+	{ 0x6e17, 0x8213, 0x1e73, 0x82d9, 0x15b8, 0x383f, 0x6da3, 0x92fc },
+	{ 0x7e36, 0x0216, 0x2316, 0x299e, 0x21eb, 0x3b68, 0x682a, 0x32d7 },
+	{ 0x4e55, 0x021c, 0x64b9, 0x7f10, 0x7d1e, 0x3e91, 0x66b1, 0x7281 },
+	{ 0x5e74, 0x8219, 0x59dc, 0xd457, 0x494d, 0x3dc6, 0x6338, 0xd2aa },
+	{ 0x2e93, 0x0208, 0xebe7, 0xd20c, 0xc4f4, 0x3563, 0x7b87, 0xf22d },
+	{ 0x3eb2, 0x820d, 0xd682, 0x794b, 0xf0a7, 0x3634, 0x7e0e, 0x5206 },
+	{ 0x0ed1, 0x8207, 0x912d, 0x2fc5, 0xac52, 0x33cd, 0x7095, 0x1250 },
+	{ 0x1ef0, 0x0202, 0xac48, 0x8482, 0x9801, 0x309a, 0x751c, 0xb27b },
+};
+
+ZXIC_UINT32 dpp_crc32_calc(ZXIC_UINT8 *pInputKey, ZXIC_UINT32 dwByteNum,
+						   ZXIC_UINT32 dwCrcPoly)
+{
+	ZXIC_UINT32 dwResult = 0;
+	ZXIC_UINT32 dwDataType = 0;
+
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 j = 0;
+
+	while (i < dwByteNum) {
+		dwDataType =
+				(ZXIC_UINT32)((dwResult & 0xff000000) ^ (pInputKey[i] << 24));
+		for (j = 0; j < 8; j++) {
+			if (dwDataType & 0x80000000) {
+				dwDataType <<= 1;
+				dwDataType ^= dwCrcPoly;
+			} else {
+				dwDataType <<= 1;
+			}
+		}
+		dwResult <<= 8;
+		dwResult ^= dwDataType;
+
+		i++;
+	}
+
+	return dwResult;
+}
+
+ZXIC_UINT16 dpp_crc16_calc(ZXIC_UINT8 *pInputKey, ZXIC_UINT32 dwByteNum,
+						   ZXIC_UINT16 dwCrcPoly)
+{
+	ZXIC_UINT16 dwResult = 0;
+	ZXIC_UINT16 dwDataType = 0;
+
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 j = 0;
+
+	while (i < dwByteNum) {
+		dwDataType = (ZXIC_UINT16)(((dwResult & 0xff00) ^ (pInputKey[i] << 8)) &
+								   0xFFFF);
+		for (j = 0; j < 8; j++) {
+			if (dwDataType & 0x8000) {
+				dwDataType <<= 1;
+				dwDataType ^= dwCrcPoly;
+			} else {
+				dwDataType <<= 1;
+			}
+		}
+		dwResult <<= 8;
+		dwResult ^= dwDataType;
+
+		i++;
+	}
+
+	return dwResult;
+}
+
+ZXIC_UINT16 dpp_crc16_get_idx(ZXIC_UINT16 crc_val)
+{
+	switch (crc_val) {
+	case 0x1021:
+		return 0;
+	case 0x8005:
+		return 1;
+	case 0x3d65:
+		return 2;
+	case 0xab47:
+		return 3;
+	case 0x3453:
+		return 4;
+	case 0x0357:
+		return 5;
+	case 0x0589:
+		return 6;
+	case 0xa02b:
+		return 7;
+	default:
+		return 0xFFFF;
+	}
+}
+
+//查表法
+ZXIC_UINT16 dpp_crc16_table_lookup(ZXIC_UINT8 *pInputKey, ZXIC_UINT32 dwByteNum,
+								   ZXIC_UINT16 dwCrcPoly)
+{
+	ZXIC_UINT16 dwResult = 0;
+	ZXIC_UINT16 dwDataType = 0;
+	ZXIC_UINT16 tmp_index = 0;
+	ZXIC_UINT32 i = 0;
+
+	ZXIC_UINT32 crc_idx = dpp_crc16_get_idx(dwCrcPoly);
+
+	ZXIC_COMM_CHECK_INDEX(crc_idx, 0, 7);
+
+	while (i < dwByteNum) {
+		dwDataType = ((dwResult & 0xff00) ^ (pInputKey[i] << 8)) & 0xFFFF;
+
+		tmp_index = dwDataType >> 8;
+		tmp_index = tmp_index & 0xff;
+		ZXIC_COMM_CHECK_INDEX(tmp_index, 0, 255);
+		ZXIC_COMM_CHECK_INDEX(crc_idx, 0, 7);
+		dwDataType = g_crc16_rst[tmp_index][crc_idx];
+
+		dwResult <<= 8;
+		dwResult ^= dwDataType;
+
+		i++;
+	}
+
+	return dwResult;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_se_cfg.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_se_cfg.c
old mode 100755
new mode 100644
index a9dd43bfccb89637001778b9539c49b80adc41f0..f6fc8466527433bf5387d85e774a7352df6fed3e
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_se_cfg.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/table/se/dpp_se_cfg.c
@@ -23,269 +23,223 @@
 #include "dpp_hash.h"
 #include "dpp_acl.h"
 
-DPP_SE_CFG *dpp_se_cfg[DPP_DEV_CHANNEL_MAX] = {0};
+DPP_SE_CFG *dpp_se_cfg[DPP_DEV_CHANNEL_MAX] = { 0 };
 
 static ZXIC_UINT16 g_lpm_crc[SE_ZBLK_NUM] = {
-    0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b,
-    0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b,
-    0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b,
-    0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b
+	0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b,
+	0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b,
+	0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b,
+	0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b
 };
 
-#if DPP_WRITE_FILE_EN
-static ZXIC_CHAR *prefix_str = "./dpp_se_data";
-#endif
-
 /***********************************************************/
 /** 配置g_se_cfg 的值
-* @param   p_se_cfg    算法模块公共管理数据结构指针
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yxh      @date  2019/02/22
-************************************************************/
+ * @param   p_se_cfg    算法模块公共管理数据结构指针
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yxh      @date  2019/02/22
+ ************************************************************/
 DPP_STATUS dpp_se_cfg_set(ZXIC_UINT32 dev_id, DPP_SE_CFG *p_se_cfg)
 {
-    ZXIC_UINT64 se_cfg_ptr = 0;
+	ZXIC_UINT64 se_cfg_ptr = 0;
 
-    ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
 
-    dpp_se_cfg[dev_id] = p_se_cfg;
-    ZXIC_COMM_CHECK_POINT(dpp_se_cfg[dev_id]);
+	dpp_se_cfg[dev_id] = p_se_cfg;
+	ZXIC_COMM_CHECK_POINT(dpp_se_cfg[dev_id]);
 
-    se_cfg_ptr = ZXIC_COMM_PTR_TO_VAL(p_se_cfg);
-    ZXIC_COMM_TRACE_INFO("p_se_cfg address 0x%llx.\n", se_cfg_ptr);
+	se_cfg_ptr = ZXIC_COMM_PTR_TO_VAL(p_se_cfg);
+	ZXIC_COMM_TRACE_INFO("p_se_cfg address 0x%llx.\n", se_cfg_ptr);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 获取g_se_cfg 的值
-* @param   p_se_cfg    算法模块公共管理数据结构指针
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yxh      @date  2019/02/22
-************************************************************/
+ * @param   p_se_cfg    算法模块公共管理数据结构指针
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yxh      @date  2019/02/22
+ ************************************************************/
 DPP_STATUS dpp_se_cfg_get(ZXIC_UINT32 dev_id, DPP_SE_CFG **p_se_cfg)
 {
-    ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_INDEX(dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
 
-    *p_se_cfg = dpp_se_cfg[dev_id];
-    ZXIC_COMM_CHECK_POINT(*p_se_cfg);
+	*p_se_cfg = dpp_se_cfg[dev_id];
+	ZXIC_COMM_CHECK_POINT(*p_se_cfg);
 
-    ZXIC_COMM_TRACE_DEBUG("p_se_cfg address %p.\n", (*p_se_cfg));
+	ZXIC_COMM_TRACE_DEBUG("p_se_cfg address %p.\n", (*p_se_cfg));
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 DPP_STATUS dpp_se_init(DPP_DEV_T *dev, DPP_SE_CFG *p_se_cfg)
 {
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 dev_id = 0;
-
-#if LPM_THREAD_HW_WRITE_EN
-    ZXIC_UINT32 rtn = 0;
-#endif
-
-    SE_ZBLK_CFG *p_zblk_cfg = NULL;
-    SE_ZCELL_CFG *p_zcell_cfg = NULL;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 j = 0;
+	ZXIC_UINT32 dev_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	SE_ZBLK_CFG *p_zblk_cfg = NULL;
+	SE_ZCELL_CFG *p_zcell_cfg = NULL;
 
-    // dev_id = ZXIC_COMM_PTR_TO_VAL(p_se_cfg->p_client) & 0xFFFFFFFF;
-    dev_id = DEV_ID(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(dev_id,DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
 
-    ZXIC_COMM_MEMSET(p_se_cfg, 0, sizeof(DPP_SE_CFG));
+	// dev_id = ZXIC_COMM_PTR_TO_VAL(p_se_cfg->p_client) & 0xFFFFFFFF;
+	dev_id = DEV_ID(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(dev_id, DPP_DEV_CHANNEL_MAX - 1);
 
-    p_se_cfg->dev = dev;
-    p_se_cfg->dev_id = dev_id;
-    dpp_se_cfg_set(p_se_cfg->dev_id, p_se_cfg);
+	ZXIC_COMM_MEMSET(p_se_cfg, 0, sizeof(DPP_SE_CFG));
 
-    //p_se_cfg->p_as_rslt_wrt_fun = dpp_se_lpm_as_rslt_write;
-    p_se_cfg->p_client = ZXIC_COMM_VAL_TO_PTR(dev_id);
+	p_se_cfg->dev = dev;
+	p_se_cfg->dev_id = dev_id;
+	dpp_se_cfg_set(p_se_cfg->dev_id, p_se_cfg);
 
-    for (i = 0; i < SE_ZBLK_NUM; i++)
-    {
-        p_zblk_cfg = DPP_SE_GET_ZBLK_CFG(p_se_cfg, i);
+	// p_se_cfg->p_as_rslt_wrt_fun = dpp_se_lpm_as_rslt_write;
+	p_se_cfg->p_client = ZXIC_COMM_VAL_TO_PTR(dev_id);
 
-        p_zblk_cfg->zblk_idx = i;
-        p_zblk_cfg->is_used  = 0;
-        p_zblk_cfg->hash_arg = g_lpm_crc[i];
-        p_zblk_cfg->zcell_bm = 0;
-        INIT_D_NODE(&p_zblk_cfg->zblk_dn, p_zblk_cfg);
+	for (i = 0; i < SE_ZBLK_NUM; i++) {
+		p_zblk_cfg = DPP_SE_GET_ZBLK_CFG(p_se_cfg, i);
 
-        for (j = 0; j < SE_ZCELL_NUM; j++)
-        {
-            p_zcell_cfg = &p_zblk_cfg->zcell_info[j];
+		p_zblk_cfg->zblk_idx = i;
+		p_zblk_cfg->is_used = 0;
+		p_zblk_cfg->hash_arg = g_lpm_crc[i];
+		p_zblk_cfg->zcell_bm = 0;
+		INIT_D_NODE(&p_zblk_cfg->zblk_dn, p_zblk_cfg);
 
-            p_zcell_cfg->zcell_idx = (i << 2) + j;
-            p_zcell_cfg->item_used = 0;
-            p_zcell_cfg->mask_len  = 0;
+		for (j = 0; j < SE_ZCELL_NUM; j++) {
+			p_zcell_cfg = &p_zblk_cfg->zcell_info[j];
 
-            INIT_D_NODE(&p_zcell_cfg->zcell_dn, p_zcell_cfg);
+			p_zcell_cfg->zcell_idx = (i << 2) + j;
+			p_zcell_cfg->item_used = 0;
+			p_zcell_cfg->mask_len = 0;
 
-            p_zcell_cfg->zcell_avl.p_key = p_zcell_cfg;
-        }
-    }
+			INIT_D_NODE(&p_zcell_cfg->zcell_dn, p_zcell_cfg);
 
-#if DPP_WRITE_FILE_EN
-/*    icm_trace_set_log_dir(prefix_str);*/
-    dpp_se_file_mng_init();
-#else
+			p_zcell_cfg->zcell_avl.p_key = p_zcell_cfg;
+		}
+	}
 
-#endif
-
-#if LPM_THREAD_HW_WRITE_EN
-    for (i = 0; i < MAX_ITEM_INFO_BAK_NUM; i++)
-    {
-        rtn = zxic_comm_mutex_create(&(p_se_cfg->cache_index_mutex[i]));
-        ZXIC_COMM_CHECK_RC(rtn, "zxic_comm_mutex_create");
-    }
-
-    rtn = zxic_comm_liststack_creat(MAX_ITEM_INFO_BAK_NUM, &p_se_cfg->p_thread_liststack_mng);
-    ZXIC_COMM_CHECK_RC(rtn,"zxic_comm_liststack_creat");
-#endif
-
-    return DPP_OK;
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** 初始化算法管理数据结构用户自定义的数据指针，当前仅用于传入设备号的值
-* @param   p_se_cfg  算法管理数据结构指针
-* @param   p_client  用户自定义的数据指针
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2015/05/20
-************************************************************/
+ * @param   p_se_cfg  算法管理数据结构指针
+ * @param   p_client  用户自定义的数据指针
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2015/05/20
+ ************************************************************/
 DPP_STATUS dpp_se_client_init(DPP_SE_CFG *p_se_cfg, ZXIC_VOID *p_client)
 {
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
 
-    p_se_cfg->p_client = p_client;
-    p_se_cfg->reg_base = SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR; /* 算法模块芯片内相对基地址 */
-    // p_se_cfg->p_write32_fun = dpp_se_reg_write32;
-    // p_se_cfg->p_read32_fun  = dpp_se_reg_read32;
+	p_se_cfg->p_client = p_client;
+	p_se_cfg->reg_base = SYS_SE_BASE_ADDR +
+						 MODULE_SE_ALG_BASE_ADDR; /* 算法模块芯片内相对基地址 */
+	// p_se_cfg->p_write32_fun = dpp_se_reg_write32;
+	// p_se_cfg->p_read32_fun  = dpp_se_reg_read32;
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-DPP_STATUS dpp_se_fun_init(DPP_SE_CFG *p_se_cfg,
-                           ZXIC_UINT8       id,
-                           ZXIC_UINT32     fun_type)
+DPP_STATUS dpp_se_fun_init(DPP_SE_CFG *p_se_cfg, ZXIC_UINT8 id,
+						   ZXIC_UINT32 fun_type)
 {
-    FUNC_ID_INFO  *p_fun_info = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
-    ZXIC_COMM_CHECK_INDEX(id, 0, MAX_FUN_NUM - 1);
-    ZXIC_COMM_CHECK_INDEX(fun_type, FUN_HASH, FUN_MAX - 1);
-
-    p_fun_info = DPP_GET_FUN_INFO(p_se_cfg, id);
-
-    if (p_fun_info->is_used)
-    {
-        ZXIC_COMM_TRACE_ERROR("\n Error[0x%x], fun_id [%d] is already used!", DPP_SE_RC_FUN_INVALID, id);
-        return DPP_SE_RC_FUN_INVALID;
-    }
-
-    p_fun_info->fun_id = id;
-    p_fun_info->is_used = 1;
-
-    switch (fun_type)
-    {
-        case (FUN_LPM):
-        {
-            /*
-            p_fun_info->fun_type = FUN_LPM;
-            p_fun_info->fun_ptr = ZXIC_COMM_MALLOC(sizeof(DPP_ROUTE_CFG));
-            ZXIC_COMM_CHECK_POINT(p_fun_info->fun_ptr);
-            ZXIC_COMM_MEMSET(p_fun_info->fun_ptr,0,sizeof(DPP_ROUTE_CFG));
-
-            ((DPP_ROUTE_CFG*)(p_fun_info->fun_ptr))->p_se_cfg = p_se_cfg;
-            */
-
-            //dpp_func_lpm_create(p_se_cfg, id);
-
-        }
-        break;
-
-        case (FUN_HASH):
-        {
-            p_fun_info->fun_type = FUN_HASH;
-            p_fun_info->fun_ptr = ZXIC_COMM_MALLOC(sizeof(DPP_HASH_CFG));
-            ZXIC_COMM_CHECK_POINT(p_fun_info->fun_ptr);
-            ZXIC_COMM_MEMSET(p_fun_info->fun_ptr, 0, sizeof(DPP_HASH_CFG));
-            ((DPP_HASH_CFG *)(p_fun_info->fun_ptr))->p_se_info = p_se_cfg;
-        }
-        break;
-
-        default:
-        {
-            ZXIC_COMM_TRACE_ERROR("\n Error,unrecgnized fun_type[ %d] ", fun_type);
-            ZXIC_COMM_ASSERT(0);
-            return DPP_SE_RC_BASE;
-        }
-        break;
-    }
-
-    return DPP_OK;
+	FUNC_ID_INFO *p_fun_info = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	ZXIC_COMM_CHECK_INDEX(id, 0, MAX_FUN_NUM - 1);
+	ZXIC_COMM_CHECK_INDEX(fun_type, FUN_HASH, FUN_MAX - 1);
+
+	p_fun_info = DPP_GET_FUN_INFO(p_se_cfg, id);
+
+	if (p_fun_info->is_used) {
+		ZXIC_COMM_TRACE_ERROR("\n Error[0x%x], fun_id [%d] is already used!",
+							  DPP_SE_RC_FUN_INVALID, id);
+		return DPP_SE_RC_FUN_INVALID;
+	}
+
+	p_fun_info->fun_id = id;
+	p_fun_info->is_used = 1;
+
+	switch (fun_type) {
+	case (FUN_LPM): {
+	/*
+	p_fun_info->fun_type = FUN_LPM;
+	p_fun_info->fun_ptr = ZXIC_COMM_MALLOC(sizeof(DPP_ROUTE_CFG));
+	ZXIC_COMM_CHECK_POINT(p_fun_info->fun_ptr);
+	ZXIC_COMM_MEMSET(p_fun_info->fun_ptr,0,sizeof(DPP_ROUTE_CFG));
+
+	((DPP_ROUTE_CFG*)(p_fun_info->fun_ptr))->p_se_cfg = p_se_cfg;
+	*/
+	// dpp_func_lpm_create(p_se_cfg, id);
+	} break;
+
+	case (FUN_HASH): {
+		p_fun_info->fun_type = FUN_HASH;
+		p_fun_info->fun_ptr = ZXIC_COMM_MALLOC(sizeof(DPP_HASH_CFG));
+		ZXIC_COMM_CHECK_POINT(p_fun_info->fun_ptr);
+		ZXIC_COMM_MEMSET(p_fun_info->fun_ptr, 0, sizeof(DPP_HASH_CFG));
+		((DPP_HASH_CFG *)(p_fun_info->fun_ptr))->p_se_info = p_se_cfg;
+	} break;
+
+	default: {
+		ZXIC_COMM_TRACE_ERROR("\n Error,unrecgnized fun_type[ %d] ", fun_type);
+		ZXIC_COMM_ASSERT(0);
+		return DPP_SE_RC_BASE;
+	} break;
+	}
+
+	return DPP_OK;
 }
 
-DPP_STATUS dpp_se_fun_deinit(DPP_SE_CFG *p_se_cfg,
-                             ZXIC_UINT8       id,
-                             ZXIC_UINT32     fun_type)
+DPP_STATUS dpp_se_fun_deinit(DPP_SE_CFG *p_se_cfg, ZXIC_UINT8 id,
+							 ZXIC_UINT32 fun_type)
 {
-    FUNC_ID_INFO  *p_fun_info = NULL;
-
-    ZXIC_COMM_CHECK_POINT(p_se_cfg);
-    ZXIC_COMM_CHECK_INDEX(id, 0, MAX_FUN_NUM - 1);
-    ZXIC_COMM_CHECK_INDEX(fun_type, FUN_HASH, FUN_MAX - 1);
-
-    p_fun_info = DPP_GET_FUN_INFO(p_se_cfg, id);
-
-    if (0 == p_fun_info->is_used)
-    {
-        ZXIC_COMM_TRACE_ERROR("\n Error[0x%x], fun_id [%d] is already deinit!", DPP_SE_RC_FUN_INVALID, id);
-        return DPP_SE_RC_FUN_INVALID;
-    }
-
-    switch (fun_type)
-    {
-        case (FUN_LPM):
-        {
-/*            dpp_func_lpm_destory(p_se_cfg, id);*/
-        }
-        break;
-
-        case (FUN_HASH):
-        {
-            if (p_fun_info->fun_ptr)
-            {
-                ZXIC_COMM_FREE(p_fun_info->fun_ptr);
-                p_fun_info->fun_ptr = NULL;
-            }
-        }
-        break;
-
-        default:
-        {
-            ZXIC_COMM_TRACE_ERROR("\n Error,unrecgnized fun_type[ %d] ", fun_type);
-            ZXIC_COMM_ASSERT(0);
-            return DPP_SE_RC_BASE;
-        }
-        break;
-    }
-
-    p_fun_info->fun_id = id;
-    p_fun_info->is_used = 0;
-
-    return DPP_OK;
+	FUNC_ID_INFO *p_fun_info = NULL;
+
+	ZXIC_COMM_CHECK_POINT(p_se_cfg);
+	ZXIC_COMM_CHECK_INDEX(id, 0, MAX_FUN_NUM - 1);
+	ZXIC_COMM_CHECK_INDEX(fun_type, FUN_HASH, FUN_MAX - 1);
+
+	p_fun_info = DPP_GET_FUN_INFO(p_se_cfg, id);
+
+	if (0 == p_fun_info->is_used) {
+		ZXIC_COMM_TRACE_ERROR("\n Error[0x%x], fun_id [%d] is already deinit!",
+							  DPP_SE_RC_FUN_INVALID, id);
+		return DPP_SE_RC_FUN_INVALID;
+	}
+
+	switch (fun_type) {
+	case (FUN_LPM): {
+		/*            dpp_func_lpm_destory(p_se_cfg, id);*/
+	} break;
+
+	case (FUN_HASH): {
+		if (p_fun_info->fun_ptr) {
+			ZXIC_COMM_FREE(p_fun_info->fun_ptr);
+			p_fun_info->fun_ptr = NULL;
+		}
+	} break;
+
+	default: {
+		ZXIC_COMM_TRACE_ERROR("\n Error,unrecgnized fun_type[ %d] ", fun_type);
+		ZXIC_COMM_ASSERT(0);
+		return DPP_SE_RC_BASE;
+	} break;
+	}
+
+	p_fun_info->fun_id = id;
+	p_fun_info->is_used = 0;
+
+	return DPP_OK;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/tm/dpp_tm.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/tm/dpp_tm.c
old mode 100755
new mode 100644
index c64a7e233749bc90c5a6567c431e5fe605bc54d0..5ddcba801ed972b99d76f8646de98b3285aecb2a
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/tm/dpp_tm.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/module/tm/dpp_tm.c
@@ -1,21525 +1,6300 @@
-/**************************************************************
-* 版权所有 (C)2013-2015,深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_tm.c
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : djf
-* 完成日期 : 2014/02/17
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-
-/******************************************************************************
- *                START: 头文件                                *
- *****************************************************************************/
-#include "zxic_common.h"
-#include "dpp_type_api.h"
-#include "dpp_reg_api.h"
-#include "dpp_reg_info.h"
-#include "dpp_etm_reg.h"
-#include "dpp_module.h"
-#include "dpp_tm_api.h"
-//#include "dpp_tm_diag.h"
-#include "dpp_tm.h"
-#include "dpp_dev.h"
-
-/******************************************************************************
- *                 END: 头文件                                 *
- *****************************************************************************/
-
-
-/******************************************************************************
- *               START: 常量定义                               *
- *****************************************************************************/
-
-DPP_TM_SHAPE_PARA_TABLE g_dpp_etm_shape_para_table[DPP_PCIE_SLOT_MAX][DPP_ETM_SHAP_TABEL_ID_MAX][DPP_TM_SHAP_MAP_ID_MAX] = {{{{0}}}}; /* coverity告警修改：单一变量不能超过10000字节 */
-DPP_TM_SHAPE_PARA_TABLE g_dpp_ftm_shape_para_table[DPP_DEV_CHANNEL_MAX][DPP_FTM_SHAP_TABEL_ID_MAX][DPP_TM_SHAP_MAP_ID_MAX] = {{{{0}}}};
-DPP_ETM_QMU_INIT_PARA g_dpp_etm_qmu_qlist_para = {0};
-DPP_FTM_QMU_INIT_PARA g_dpp_ftm_qmu_qlist_para = {0};
-
-/* 全局变量读写互斥锁 */
-ZXIC_MUTEX_T g_dpp_tm_global_var_rw_mutex;
-ZXIC_UINT32 g_dpp_tm_global_var_rw_mutex_flag = 0;
-// static ZXIC_UINT32 g_qmu_init_case_no = 0;
-
-
-/***********************************************************/
-/** 全局变量读写互斥锁初始化
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/23
-************************************************************/
-DPP_STATUS dpp_tm_global_var_mutex_init(ZXIC_VOID)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    if (!g_dpp_tm_global_var_rw_mutex_flag)
-    {
-        rc = zxic_comm_mutex_create(&g_dpp_tm_global_var_rw_mutex);
-        ZXIC_COMM_CHECK_RC(rc, "zxic_comm_mutex_create");
-
-        g_dpp_tm_global_var_rw_mutex_flag = 1;
-    }
-
-    return DPP_OK;
-}
-
-
-/******************************************************************************
- *                END: 常量定义                                *
- *****************************************************************************/
-
-#if ZXIC_REAL("TM_REG")
-#if 0
-/***********************************************************/
-/** 写TM寄存器
-* @param   module_id 区分TM子模块
-* @param   addr   基于子模块的地址
-* @param   data   写入的数据
-*
-* @return
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/26
-************************************************************/
-DPP_STATUS dpp_tm_wr_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 addr, ZXIC_UINT32 data)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 wr_data = 0;
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, module_id, MODULE_TM_CFGMT, MODULE_TM_MAX - 1);
-
-    wr_data = data;
-    rc = dpp_tm_write(dev_id, module_id,  addr,  &wr_data);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读TM寄存器
-* @param   tm_type   0-ETM,1-FTM
-* @param   module_id 区分TM子模块
-* @param   addr   基于子模块的地址
-* @return
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/26
-************************************************************/
-DPP_STATUS dpp_tm_rd_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 addr)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 rd_data = 0;
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, module_id, MODULE_TM_CFGMT, MODULE_TM_MAX - 1);
-
-    rc = dpp_tm_read(dev_id, module_id,  addr,  &rd_data);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_read");
-
-    ZXIC_COMM_PRINT("[0x%08x] 0x%08x \n", addr, rd_data);
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 写一片连续的TM寄存器
-* @param   module_id 区分TM子模块
-* @param   first_addr   起始寄存器的地址
-* @param   reg_num   总共读取的寄存器数
-*
-* @return
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/26
-************************************************************/
-DPP_STATUS dpp_tm_wr_more_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 first_addr, ZXIC_UINT32 first_data, ZXIC_UINT32 data_step, ZXIC_UINT32 reg_num)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 addr = 0;
-    ZXIC_UINT32 data = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, module_id, MODULE_TM_CFGMT, MODULE_TM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id,  first_addr , reg_num);
-    ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id,  data_step , reg_num);
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id,  first_data , (data_step * reg_num));     
-
-    for (i = 0; i < reg_num; i++)
-    {
-        addr = first_addr + i;
-        data = first_data + (data_step * i);
-        rc = dpp_tm_wr_reg(dev_id, module_id, addr, data);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_wr_reg");
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读一片连续的TM寄存器
-* @param   module_id 区分TM子模块
-* @param   first_addr   起始寄存器的地址
-* @param   reg_num   总共读取的寄存器数
-*
-* @return
-* @remark  无
-* @see
-* @author  yjd      @date  2017/07/26
-************************************************************/
-DPP_STATUS dpp_tm_rd_more_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 first_addr, ZXIC_UINT32 reg_num)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 addr = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, module_id, MODULE_TM_CFGMT, MODULE_TM_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id,  first_addr , reg_num);
-
-    for (i = 0; i < reg_num; i++)
-    {
-        addr = first_addr + i;
-        rc = dpp_tm_rd_reg(dev_id, module_id, addr);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_rd_reg");
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 写tm模块二层间接寄存器(仅crdt/shap模块使用)
-* @param   module_id 区分TM子模块
-* @param   addr   基于子模块的地址
-* @param   data   写入的数据
-*
-* @return
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/25
-************************************************************/
-DPP_STATUS dpp_tm_ind_wr_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 addr, ZXIC_UINT64 data)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 wr_data[2] = {0};
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, module_id, MODULE_TM_SHAP, MODULE_TM_CRDT);
-
-    wr_data[1] = (data & 0xffffffff);
-    wr_data[0] = (data >> 32)&0xffffffff;
-
-    rc = dpp_tm_ind_write(dev_id, module_id, addr, wr_data);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_ind_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读tm模块二层间接寄存器(仅crdt/shap模块使用)
-* @param   module_id 区分TM子模块
-* @param   addr   基于子模块的地址
-*
-* @return
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/25
-************************************************************/
-DPP_STATUS dpp_tm_ind_rd_reg(ZXIC_UINT32 dev_id, ZXIC_UINT32 module_id, ZXIC_UINT32 addr)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 rd_data[2] = {0};
-    ZXIC_UINT64 tmp_data = 0;
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, module_id, MODULE_TM_SHAP, MODULE_TM_CRDT);
-
-    rc = dpp_tm_ind_read(dev_id, module_id,  addr,  rd_data);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_ind_read");
-
-    tmp_data = ((tmp_data | rd_data[0]) << 32) | (rd_data[1]);
-    ZXIC_COMM_PRINT("[0x%08x] 0x%016llx \n", addr, tmp_data);
-
-    return DPP_OK;
-}
-#endif
-
-#endif
-
-
-#if ZXIC_REAL("TM_CFGMT")
-
-#if 0
-/***********************************************************/
-/** 校验子系统初始化就绪，所有子系统均初始化就绪，p_rdy值为1
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_rdy   初始化就绪标记，1-就绪，0-未就绪
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_subsystem_rdy_check(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 p_rdy = 0;    /*tm子系统是否初始化完成判断*/
-    ZXIC_UINT32 read_times = 50;
-    DPP_ETM_CFGMT_SUBSYSTEM_RDY_REG_T subsystem_rdy = {0};
-
-
-
-    /* 循环判定TM子系统是否初始化完成 */
-    do
-    {
-        rc  = dpp_reg_read(dev_id,
-                           ETM_CFGMT_SUBSYSTEM_RDY_REGr,
-                           0,
-                           0,
-                           &subsystem_rdy);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        p_rdy = (subsystem_rdy.olif_rdy)
-                && (subsystem_rdy.qmu_rdy)
-                && (subsystem_rdy.tmmu_rdy)
-                && (subsystem_rdy.cgavd_rdy)
-                && (subsystem_rdy.shap_rdy)
-                && (subsystem_rdy.crdt_rdy);
-
-        if (p_rdy)
-        {
-            rc  = dpp_tm_cfgmt_subsystem_rdy_print(dev_id);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_subsystem_rdy_print");
-            break;
-        }
-
-        read_times--;
-        zxic_comm_sleep(100);
-    }
-    while (read_times > 0);
-
-    if (read_times == 0)
-    {
-        rc  = dpp_tm_cfgmt_subsystem_rdy_print(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_subsystem_rdy_print");
-        ZXIC_COMM_PRINT("dpp_tm_cfgmt_subsystem_rdy_check：TM INIT FAILED !!\n");
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
-}
-#endif
-
-/***********************************************************/
-/** cpu读写通道验证，其读出值等于写入值。读出值不等于写入值时，返回err
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_cpu_check(DPP_DEV_T *dev)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 input = 0x5a5a5a5a;
-    ZXIC_UINT32 output = 0;
-    DPP_ETM_CFGMT_CPU_CHECK_REG_T cpu_access_input = {0};
-    DPP_ETM_CFGMT_CPU_CHECK_REG_T cpu_access_output = {0};
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    cpu_access_input.cpu_check_reg = input;
-    rc  = dpp_reg_write(dev,
-                        ETM_CFGMT_CPU_CHECK_REGr,
-                        0,
-                        0,
-                        &cpu_access_input);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CFGMT_CPU_CHECK_REGr,
-                       0,
-                       0,
-                       &cpu_access_output);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    output = cpu_access_output.cpu_check_reg;
-
-    /* 判断读出值是否等于写入值 */
-    if (input != output)
-    {
-        ZXIC_COMM_TRACE_ERROR("dpp_tm_cpu_check :input != output");
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置内置TM的工作模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   mode   配置的值，0-TM模式，1-SA模式
-*ETM仅工作在TM模式，FTM可以工作TM或SA模式
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_sa_work_mode_set(DPP_DEV_T *dev, DPP_TM_WORK_MODE_E mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_TM_SA_WORK_MODE_T tm_sa_mode = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, DPP_TM_WORK_MODE_TM, DPP_TM_WORK_MODE_TM);
-
-    tm_sa_mode.tm_sa_work_mode = mode;
-    rc  = dpp_reg_write(dev,
-                        ETM_CFGMT_TM_SA_WORK_MODEr,
-                        0,
-                        0,
-                        &tm_sa_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 读取内置TM的工作模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_mode   读取的值，0-TM模式，1-SA模式
-*ETM仅工作在TM模式，FTM可以工作TM或SA模式
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_sa_work_mode_get(DPP_DEV_T *dev, DPP_TM_WORK_MODE_E *p_mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_TM_SA_WORK_MODE_T tm_sa_mode = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mode);
-
-    *p_mode = DPP_TM_WORK_MODE_INVALID;
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CFGMT_TM_SA_WORK_MODEr,
-                       0,
-                       0,
-                       &tm_sa_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_mode = tm_sa_mode.tm_sa_work_mode;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置ddr3挂接组数，共10bit[0-9]，每bit对应1组ddr，TM最多使用其中8组
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   ddr_num   单个tm使用的ddr组：bit[0-9]每bit代表一组ddr，如使用4567组，则配置0xf0
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/06/07
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_ddr_attach_set(DPP_DEV_T *dev, ZXIC_UINT32 ddr_num)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_CFGMT_DDR_ATTACH_T ddr_attach = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), ddr_num, 0, 0x3FF);
-
-    ddr_attach.cfgmt_ddr_attach = ddr_num;
-    rc  = dpp_reg_write(dev,
-                        ETM_CFGMT_CFGMT_DDR_ATTACHr,
-                        0,
-                        0,
-                        &ddr_attach);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取ddr3挂接组数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_ddr_num   ddr组数,1-6组
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_ddr_attach_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_ddr_num)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_CFGMT_DDR_ATTACH_T ddr_attach = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ddr_num);
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CFGMT_CFGMT_DDR_ATTACHr,
-                       0,
-                       0,
-                       &ddr_attach);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    if (ddr_attach.cfgmt_ddr_attach == 1)
-    {
-        *p_ddr_num = 1;
-    }
-    else if (ddr_attach.cfgmt_ddr_attach == 3)
-    {
-        *p_ddr_num = 2;
-    }
-    else if (ddr_attach.cfgmt_ddr_attach == 7)
-    {
-        *p_ddr_num = 3;
-    }
-    else if (ddr_attach.cfgmt_ddr_attach == 15)
-    {
-        *p_ddr_num = 4;
-    }
-    else if (ddr_attach.cfgmt_ddr_attach == 31)
-    {
-        *p_ddr_num = 5;
-    }
-    else if (ddr_attach.cfgmt_ddr_attach == 63)
-    {
-        *p_ddr_num = 6;
-    }
-    else if (ddr_attach.cfgmt_ddr_attach == 127)
-    {
-        *p_ddr_num = 7;
-    }
-    else if (ddr_attach.cfgmt_ddr_attach == 255)
-    {
-        *p_ddr_num = 8;
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置QMU工作模式，0：8 block工作模式，1：16 block工作模式
-*** (即一个chunk中block个数) 影响tm总可用的缓存节点数。
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   mode   0-128/256K节点，1-256/512K节点，目前固定配1
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_qmu_work_mode_set(DPP_DEV_T *dev, DPP_TM_QMU_WORK_MODE_E mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_QMU_WORK_MODE_T qmu_mode = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, DPP_TM_QMU_WORK_MODE_2M, DPP_TM_QMU_WORK_MODE_4M);
-
-    qmu_mode.qmu_work_mode = mode;
-    rc  = dpp_reg_write(dev,
-                        ETM_CFGMT_QMU_WORK_MODEr,
-                        0,
-                        0,
-                        &qmu_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 读取QMU工作模式，0：8 block工作模式，1：16 block工作模式
-*** (即一个chunk中block个数) 影响tm总可用的缓存节点数。
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   mode   0-128/256K节点，1-256/512K节点，目前固定配1
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_qmu_work_mode_get(DPP_DEV_T *dev, DPP_TM_QMU_WORK_MODE_E *p_mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_QMU_WORK_MODE_T qmu_mode = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mode);
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CFGMT_QMU_WORK_MODEr,
-                       0,
-                       0,
-                       &qmu_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_mode = qmu_mode.qmu_work_mode;
-
-    return DPP_OK;
-}
-
-
-
-#if 0
-/***********************************************************/
-/** 配置包存储的CRC功能是否使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   配置的值，0-禁止CRC功能，1-允许CRC功能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_crc_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_CFGMT_CRC_EN_T crc_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1);
-
-    crc_en.cfgmt_crc_en = en;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CFGMT_CFGMT_CRC_ENr,
-                        0,
-                        0,
-                        &crc_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取包存储的CRC功能是否使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_en   读取的值，0-禁止CRC功能，1-允许CRC功能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_crc_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_CFGMT_CRC_EN_T crc_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en);
-
-    *p_en = 0xffffffff;
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CFGMT_CFGMT_CRC_ENr,
-                       0,
-                       0,
-                       &crc_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_en = crc_en.cfgmt_crc_en;
-
-    return DPP_OK;
-}
-#endif
-/***********************************************************/
-/** 配置block长度模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   size   block长度模式:256/512/1024
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_blk_size_set(DPP_DEV_T *dev, ZXIC_UINT32 size)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_CFGMT_BLKSIZE_T blk_size = {0};
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    switch (size)
-    {
-        case 256:
-        {
-            blk_size.cfgmt_blksize =  DPP_ETM_BLK_SIZE_256_B;
-            break;
-        }
-
-        case 512:
-        {
-            blk_size.cfgmt_blksize =  DPP_ETM_BLK_SIZE_512_B;
-            break;
-        }
-
-        case 1024:
-        {
-            blk_size.cfgmt_blksize =  DPP_ETM_BLK_SIZE_1024_B;
-            break;
-        }
-
-        default:
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_cfgmt_blk_size_set:TM set block size error!\n");
-            return DPP_ERR;
-        }
-    }
-
-    rc  = dpp_reg_write(dev,
-                        ETM_CFGMT_CFGMT_BLKSIZEr,
-                        0,
-                        0,
-                        &blk_size);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取block长度模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_size   block长度模式，256/512/1024
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_blk_size_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_size)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_CFGMT_BLKSIZE_T blk_size = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_size);
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CFGMT_CFGMT_BLKSIZEr,
-                       0,
-                       0,
-                       &blk_size);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    switch (blk_size.cfgmt_blksize)
-    {
-        case DPP_ETM_BLK_SIZE_256_B:
-        {
-            *p_size =  256;
-            break;
-        }
-
-        case DPP_ETM_BLK_SIZE_512_B:
-        {
-            *p_size =  512;
-            break;
-        }
-
-        case DPP_ETM_BLK_SIZE_1024_B:
-        {
-            *p_size =  1024;
-            break;
-        }
-
-        default:
-        {
-            *p_size =  256;
-        }
-    }
-
-    return DPP_OK;
-}
-
-#if 0
-/***********************************************************/
-/** 配置计数模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_mode   计数模式
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_cnt_mode_set(ZXIC_UINT32 dev_id, DPP_TM_CNT_MODE_T *p_mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_CNT_MODE_REG_T cnt_mode = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_mode);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_mode->fc_count_mode, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_mode->count_rd_mode, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_mode->count_overflow_mode, 0, 1);
-
-    cnt_mode.cfgmt_fc_count_mode = p_mode->fc_count_mode;
-    cnt_mode.cfgmt_count_rd_mode = p_mode->count_rd_mode;
-    cnt_mode.cfgmt_count_overflow_mode = p_mode->count_overflow_mode;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CFGMT_CNT_MODE_REGr,
-                        0,
-                        0,
-                        &cnt_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取计数模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_mode   计数模式
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_cnt_mode_get(ZXIC_UINT32 dev_id, DPP_TM_CNT_MODE_T *p_mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_CNT_MODE_REG_T cnt_mode = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_mode);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CFGMT_CNT_MODE_REGr,
-                       0,
-                       0,
-                       &cnt_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    p_mode->fc_count_mode = cnt_mode.cfgmt_fc_count_mode;
-    p_mode->count_rd_mode = cnt_mode.cfgmt_count_rd_mode;
-    p_mode->count_overflow_mode = cnt_mode.cfgmt_count_overflow_mode;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置中断屏蔽
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_para   中断屏蔽
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_int_mask_set(ZXIC_UINT32 dev_id, DPP_TM_INT_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_REG_INT_MASK_REG_T int_mask = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-
-    int_mask.shap_int_mask      = p_para->shap_int;
-    int_mask.crdt_int_mask      = p_para->crdt_int;
-    int_mask.tmmu_int_mask       = p_para->mmu_int;
-    int_mask.qmu_int_mask       = p_para->qmu_int;
-    int_mask.cgavd_int_mask     = p_para->cgavd_int;
-    int_mask.olif_int_mask      = p_para->olif_int;
-    int_mask.cfgmt_int_buf_mask = p_para->cfgmt_int;
-
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CFGMT_REG_INT_MASK_REGr,
-                        0,
-                        0,
-                        &int_mask);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 读取中断屏蔽
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_para   中断屏蔽
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_int_mask_get(ZXIC_UINT32 dev_id, DPP_TM_INT_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_REG_INT_MASK_REG_T int_mask = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CFGMT_REG_INT_MASK_REGr,
-                       0,
-                       0,
-                       &int_mask);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    p_para->shap_int  = int_mask.shap_int_mask;
-    p_para->crdt_int  = int_mask.crdt_int_mask;
-    p_para->mmu_int   = int_mask.tmmu_int_mask;
-    p_para->qmu_int   = int_mask.qmu_int_mask;
-    p_para->cgavd_int = int_mask.cgavd_int_mask;
-    p_para->olif_int  = int_mask.olif_int_mask;
-    p_para->cfgmt_int = int_mask.cfgmt_int_buf_mask;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取中断状态
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_para   中断状态
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/04/09
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_int_state_get(ZXIC_UINT32 dev_id, DPP_TM_INT_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_REG_INT_STATE_REG_T int_state = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CFGMT_REG_INT_STATE_REGr,
-                       0,
-                       0,
-                       &int_state);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    p_para->shap_int  = int_state.shap_int;
-    p_para->crdt_int  = int_state.crdt_int;
-    p_para->mmu_int   = int_state.mmu_int;
-    p_para->qmu_int   = int_state.qmu_int;
-    p_para->cgavd_int = int_state.cgavd_int;
-    p_para->olif_int  = int_state.olif_int;
-    p_para->cfgmt_int = int_state.cfgmt_int_buf;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置tm时钟门控是否使能
-* @param   dev_id   设备编号
-* @param   en   配置的值，0-禁止tm时钟门控，1-使能tm时钟门控
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lsy      @date  2022/08/22
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_clkgate_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_CLKGATE_EN_T clkgate_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1);
-
-    clkgate_en.clkgate_en = en;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CFGMT_CLKGATE_ENr,
-                        0,
-                        0,
-                        &clkgate_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取tm时钟门控是否使能
-* @param   dev_id   设备编号
-* @param   en   配置的值，0-禁止tm时钟门控，1-使能tm时钟门控
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lsy      @date  2022/08/22
-
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_clkgate_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_CLKGATE_EN_T clkgate_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en);
-
-    *p_en = 0xffffffff;
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CFGMT_CLKGATE_ENr,
-                       0,
-                       0,
-                       &clkgate_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_en = clkgate_en.clkgate_en;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置tm软复位是否使能
-* @param   dev_id   设备编号
-* @param   en   配置的值，0-禁止tm软复位，1-使能tm软复位
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lsy      @date  2022/08/22
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_softrst_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_SOFTRST_EN_T softrst_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1);
-
-    softrst_en.softrst_en = en;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CFGMT_SOFTRST_ENr,
-                        0,
-                        0,
-                        &softrst_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取tm软复位是否使能
-* @param   dev_id   设备编号
-* @param   en   配置的值，0-禁止tm软复位，1-使能tm软复位
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lsy      @date  2022/08/22
-
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_softrst_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_SOFTRST_EN_T softrst_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en);
-
-    *p_en = 0xffffffff;
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CFGMT_SOFTRST_ENr,
-                       0,
-                       0,
-                       &softrst_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_en = softrst_en.softrst_en;
-
-    return DPP_OK;
-}
-
-#endif
-#endif
-
-
-
-#if ZXIC_REAL("TM_CGAVD")
-
-#if 0
-/***********************************************************/
-/**  配置各级搬移功能使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级
-* @param   en   使能标记，0-不使能，1-使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-#ifdef ETM_REAL
-
-DPP_STATUS dpp_tm_cgavd_move_en_set(ZXIC_UINT32 dev_id,
-                                    DPP_TM_CGAVD_LEVEL_E level,
-                                    ZXIC_UINT32 en)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_ETM_CGAVD_CGAVD_CFG_MOVE_T cgavd_cfg_move = {0};
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, SYS_LEVEL);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CGAVD_CGAVD_CFG_MOVEr,
-                       0,
-                       0,
-                       &cgavd_cfg_move);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    if (QUEUE_LEVEL == level)
-    {
-        cgavd_cfg_move.cfgmt_flow_move_en = en;
-    }
-
-    else if (PP_LEVEL == level)
-    {
-        cgavd_cfg_move.cfgmt_port_move_en = en;
-    }
-
-    else if (SYS_LEVEL == level)
-    {
-        cgavd_cfg_move.cfgmt_sys_move_en = en;
-    }
-
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_CGAVD_CFG_MOVEr,
-                        0,
-                        0,
-                        &cgavd_cfg_move);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**  读取各级搬移功能使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级
-* @param   p_en   读出的使能标记，0-不使能，1-使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_move_en_get(ZXIC_UINT32 dev_id,
-                                    DPP_TM_CGAVD_LEVEL_E level,
-                                    ZXIC_UINT32 *p_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_CGAVD_CFG_MOVE_T cgavd_cfg_move = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, SYS_LEVEL);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en);
-
-    *p_en = 0xffffffff;
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CGAVD_CGAVD_CFG_MOVEr,
-                       0,
-                       0,
-                       &cgavd_cfg_move);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    if (QUEUE_LEVEL == level)
-    {
-        *p_en = cgavd_cfg_move.cfgmt_flow_move_en;
-    }
-
-    else if (PP_LEVEL == level)
-    {
-        *p_en = cgavd_cfg_move.cfgmt_port_move_en;
-    }
-
-    else if (SYS_LEVEL == level)
-    {
-        *p_en = cgavd_cfg_move.cfgmt_sys_move_en;
-    }
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置各级搬移门限
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号，系统级时，id参数无效
-* @param   value   端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B；
-                   流级时为搬移profile_id,0~15
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_move_th_set(ZXIC_UINT32 dev_id,
-                                    DPP_TM_CGAVD_LEVEL_E level,
-                                    ZXIC_UINT32 id,
-                                    ZXIC_UINT32 value)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 q_move_profile_reg_index = 0;
-    ZXIC_UINT32 pp_move_th_reg_index = 0;
-    ZXIC_UINT32 sys_move_th_reg_index = 0;
-
-    DPP_ETM_CGAVD_MOVE_FLOW_TH_PROFILE_T q_move_profile = {0};
-    DPP_ETM_CGAVD_MV_PORT_TH_T pp_move_th = {0};
-    DPP_ETM_CGAVD_CFGMT_TOTAL_TH_T sys_move_th = {0};
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, SYS_LEVEL);
-    
-
-    q_move_profile_reg_index = ETM_CGAVD_MOVE_FLOW_TH_PROFILEr;
-    pp_move_th_reg_index = ETM_CGAVD_MV_PORT_THr;
-    sys_move_th_reg_index = ETM_CGAVD_CFGMT_TOTAL_THr;
-
-
-    if (QUEUE_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, value, 0, DPP_TM_CGAVD_MOVE_PROFILE_NUM - 1);
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, DPP_ETM_Q_NUM - 1);
-
-        q_move_profile.move_drop_profile = value;
-        rc  = dpp_reg_write(dev_id,
-                            q_move_profile_reg_index,
-                            0,
-                            id,
-                            &q_move_profile);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    }
-
-    else if (PP_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, DPP_TM_PP_NUM - 1);
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, value, 0, 0x3fff);
-
-        pp_move_th.port_th = value;
-        rc  = dpp_reg_write(dev_id,
-                            pp_move_th_reg_index,
-                            0,
-                            id,
-                            &pp_move_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, value, 0, 0x3fff);
-
-        sys_move_th.cfgmt_total_th = value;
-        rc  = dpp_reg_write(dev_id,
-                            sys_move_th_reg_index,
-                            0,
-                            0,
-                            &sys_move_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 读取各级搬移门限
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号，系统级时，id参数无效
-* @param   p_value   端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B；
-                     流级时为搬移profile_id,0~15
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_move_th_get(ZXIC_UINT32 dev_id,
-                                    DPP_TM_CGAVD_LEVEL_E level,
-                                    ZXIC_UINT32 id,
-                                    ZXIC_UINT32 *p_value)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 q_move_profile_reg_index = 0;
-    ZXIC_UINT32 pp_move_th_reg_index = 0;
-    ZXIC_UINT32 sys_move_th_reg_index = 0;
-
-    DPP_ETM_CGAVD_MOVE_FLOW_TH_PROFILE_T q_move_profile = {0};
-    DPP_ETM_CGAVD_MV_PORT_TH_T pp_move_th = {0};
-    DPP_ETM_CGAVD_CFGMT_TOTAL_TH_T sys_move_th = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, SYS_LEVEL);
-    
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_value);
-
-    q_move_profile_reg_index = ETM_CGAVD_MOVE_FLOW_TH_PROFILEr;
-    pp_move_th_reg_index = ETM_CGAVD_MV_PORT_THr;
-    sys_move_th_reg_index = ETM_CGAVD_CFGMT_TOTAL_THr;
-
-
-
-    if (QUEUE_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, DPP_ETM_Q_NUM - 1);
-
-        rc  = dpp_reg_read(dev_id,
-                           q_move_profile_reg_index,
-                           0,
-                           id,
-                           &q_move_profile);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-        *p_value = q_move_profile.move_drop_profile;
-    }
-
-    else if (PP_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, DPP_TM_PP_NUM - 1);
-        rc  = dpp_reg_read(dev_id,
-                           pp_move_th_reg_index,
-                           0,
-                           id,
-                           &pp_move_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-        *p_value = pp_move_th.port_th;
-    }
-
-    else
-    {
-        rc  = dpp_reg_read(dev_id,
-                           sys_move_th_reg_index,
-                           0,
-                           0,
-                           &sys_move_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-        *p_value = sys_move_th.cfgmt_total_th;
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/**  配置flow级的搬移策略
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   move_profile  flow级的搬移门限分组索引,0~15
-* @param   th  flow级的搬移门限，单位为KB；
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_flow_move_profile_set(ZXIC_UINT32 dev_id,
-                                              ZXIC_UINT32 move_profile,
-                                              ZXIC_UINT32 th)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 flow_move_th_reg_index = 0;
-    ZXIC_UINT32 blk_size = 0;
-    ZXIC_UINT32 move_th = 0;
-    ZXIC_UINT32 cgavd_cfg_mode = 0;
-    DPP_ETM_CGAVD_MOVE_FLOW_TH_T flow_th = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, move_profile, 0, DPP_TM_CGAVD_MOVE_PROFILE_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, th , DPP_TM_CGAVD_KILO_UL);
-    move_th = th * DPP_TM_CGAVD_KILO_UL;
-
-    flow_move_th_reg_index = ETM_CGAVD_MOVE_FLOW_THr;
-
-    rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get");
-
-    if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE)
-    {
-        rc  = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get");
-
-        if (blk_size != 0)
-        {
-            move_th = (move_th / blk_size);
-            move_th = (move_th % blk_size == 0) ? (move_th ) : ((move_th) + 1);
-        }
-    }
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, move_th, 0, 0x1fffffff);
-
-    flow_th.move_drop_flow_th = move_th;
-    rc  = dpp_reg_write(dev_id,
-                        flow_move_th_reg_index,
-                        0,
-                        move_profile,
-                        &flow_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**  读取flow级的搬移策略
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   move_profile  flow级的搬移门限分组索引,0~15
-* @param   p_th  flow级的搬移门限，单位为KB；
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_flow_move_profile_get(ZXIC_UINT32 dev_id,
-                                              ZXIC_UINT32 move_profile,
-                                              ZXIC_UINT32 *p_th)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 flow_move_th_reg_index = 0;
-    ZXIC_UINT32 blk_size = 0;
-    ZXIC_UINT32 move_th = 0;
-    ZXIC_UINT32 cgavd_cfg_mode = 0;
-
-    DPP_ETM_CGAVD_MOVE_FLOW_TH_T flow_th = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, move_profile, 0, DPP_TM_CGAVD_MOVE_PROFILE_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_th);
-
-    flow_move_th_reg_index = ETM_CGAVD_MOVE_FLOW_THr;
-
-    rc  = dpp_reg_read(dev_id,
-                       flow_move_th_reg_index,
-                       0,
-                       move_profile,
-                       &flow_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    move_th = flow_th.move_drop_flow_th;
-
-    rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get");
-
-    if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE)
-    {
-        rc  = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get");
-
-        *p_th = (move_th * blk_size) / DPP_TM_CGAVD_KILO_UL;
-    }
-    else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE)
-    {
-        *p_th = (move_th / DPP_TM_CGAVD_KILO_UL);
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_cgavd_flow_move_profile_get:cgavd_cfg_mode is err!!\n");
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
-}
-#endif
-/***********************************************************/
-/**  配置端口共享的搬移门限
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   th  端口共享的搬移门限，单位为NPPU存包的单位，256B；
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_port_share_th_set(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 th)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 port_share_th_reg_index = 0;
-
-    DPP_ETM_CGAVD_CFGMT_PORT_SHARE_TH_T port_share_th = {0};
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, th, 0, 0x3fff);
-
-    port_share_th_reg_index = ETM_CGAVD_CFGMT_PORT_SHARE_THr;
-
-    port_share_th.cfgmt_port_share_th = th;
-
-    rc  = dpp_reg_write(dev_id,
-                        port_share_th_reg_index,
-                        0,
-                        0,
-                        &port_share_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**  读取端口共享的搬移门限
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_th  端口共享的搬移门限，单位为NPPU存包的单位，256B；
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_port_share_th_get(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 *p_th)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 port_share_th_reg_index = 0;
-
-    DPP_ETM_CGAVD_CFGMT_PORT_SHARE_TH_T port_share_th = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_th);
-
-    port_share_th_reg_index = ETM_CGAVD_CFGMT_PORT_SHARE_THr;
-
-    rc  = dpp_reg_read(dev_id,
-                       port_share_th_reg_index,
-                       0,
-                       0,
-                       &port_share_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    *p_th = port_share_th.cfgmt_port_share_th;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**  配置基于优先级的QMU接收NPPU数据的fifo阈值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sp  优先级0~7
-* @param   th  指定优先级的fifo阈值0~511，单位为fifo条目，fifo深度512
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_move_drop_sp_th_set(ZXIC_UINT32 dev_id,
-                                            ZXIC_UINT32 sp,
-                                            ZXIC_UINT32 th)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_ETM_CGAVD_MV_DROP_SP_TH_T sp_th = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, th, 0, 0x1ff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sp, 0, 7);
-
-    sp_th.mvdrop_sp_th = th;
-
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_MV_DROP_SP_THr,
-                        0,
-                        sp,
-                        &sp_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**  读取基于优先级的QMU接收NPPU数据的fifo阈值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sp  优先级0~7
-* @param   p_th  指定优先级的fifo阈值0~511，单位为fifo条目，fifo深度512
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2016/10/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_move_drop_sp_th_get(ZXIC_UINT32 dev_id,
-                                            ZXIC_UINT32 sp,
-                                            ZXIC_UINT32 *p_th)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_ETM_CGAVD_MV_DROP_SP_TH_T sp_th = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sp, 0, 7);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_th);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CGAVD_MV_DROP_SP_THr,
-                       0,
-                       sp,
-                       &sp_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    *p_th = sp_th.mvdrop_sp_th;
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**  配置强制片内或片外
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en      1:使能
-* @param   mode   1 :omem 强制片外  0:imem 强制片内
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2017/10/14
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_imem_omem_set(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 en,
-                                      ZXIC_UINT32 mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_CGAVD_FORCE_IMEM_OMEM_T cgavd_imem_omem_mode = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, mode, 0, 1);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CGAVD_CGAVD_FORCE_IMEM_OMEMr,
-                       0,
-                       0,
-                       &cgavd_imem_omem_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    cgavd_imem_omem_mode.choose_imem_omem = mode;
-    cgavd_imem_omem_mode.imem_omem_force_en = en;
-
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_CGAVD_FORCE_IMEM_OMEMr,
-                        0,
-                        0,
-                        &cgavd_imem_omem_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**  获取强制片内或片外
-* @param   dev_id   设备编号
-* @param   tm_type     0-ETM,1-FTM
-* @param   en          1:使能
-* @param   mode        1 :omem 强制片外  0:imem 强制片内
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2017/10/14
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_imem_omem_get(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 *p_en,
-                                      ZXIC_UINT32 *p_mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_CGAVD_FORCE_IMEM_OMEM_T cgavd_imem_omem_mode = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_mode);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CGAVD_CGAVD_FORCE_IMEM_OMEMr,
-                       0,
-                       0,
-                       &cgavd_imem_omem_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_mode = cgavd_imem_omem_mode.choose_imem_omem;
-    *p_en = cgavd_imem_omem_mode.imem_omem_force_en;
-
-    return DPP_OK;
-}
-
-#endif
-
-/***********************************************************/
-/**  配置配置cgavd模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   mode   0:block mode 1:byte mode
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/07/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_cfg_mode_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_CFGMT_BYTE_MODE_T cgavd_cfg_mode = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1);
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CGAVD_CFGMT_BYTE_MODEr,
-                       0,
-                       0,
-                       &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    cgavd_cfg_mode.cfgmt_byte_mode = mode;
-
-    rc  = dpp_reg_write(dev,
-                        ETM_CGAVD_CFGMT_BYTE_MODEr,
-                        0,
-                        0,
-                        &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**  获取cgavd模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_mode   0:block mode 1:byte mode
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/07/29
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_cfg_mode_get(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 *p_mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_CFGMT_BYTE_MODE_T cgavd_cfg_mode = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mode);
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CGAVD_CFGMT_BYTE_MODEr,
-                       0,
-                       0,
-                       &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_mode = cgavd_cfg_mode.cfgmt_byte_mode;
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**  配置各级拥塞避免功能使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级
-* @param   en   使能标记，0-不使能，1-使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_en_set(DPP_DEV_T *dev,
-                               DPP_TM_CGAVD_LEVEL_E level,
-                               ZXIC_UINT32 en)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_ETM_CGAVD_CGAVD_SUB_EN_T cgavd_sub_en = {0};
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_POINT(dev);
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SA_LEVEL);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), en, 0, 1);
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CGAVD_CGAVD_SUB_ENr,
-                       0,
-                       0,
-                       &cgavd_sub_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    if (QUEUE_LEVEL == level)
-    {
-        cgavd_sub_en.cgavd_flow_sub_en = en;
-    }
-
-    else if (PP_LEVEL == level)
-    {
-        cgavd_sub_en.cgavd_pp_sub_en = en;
-    }
-
-    else if (SYS_LEVEL == level)
-    {
-        cgavd_sub_en.cgavd_sys_sub_en = en;
-    }
-
-    rc  = dpp_reg_write(dev,
-                        ETM_CGAVD_CGAVD_SUB_ENr,
-                        0,
-                        0,
-                        &cgavd_sub_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**  读取各级拥塞避免功能使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   要读取的拥塞避免层次号，0:队列级，1:端口级，2:系统级
-* @param   p_en   读出的使能标记，0-不使能，1-使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_en_get(DPP_DEV_T *dev,
-                               DPP_TM_CGAVD_LEVEL_E level,
-                               ZXIC_UINT32 *p_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_CGAVD_SUB_EN_T cgavd_sub_en = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SA_LEVEL);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_en);
-
-    *p_en = 0xffffffff;
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CGAVD_CGAVD_SUB_ENr,
-                       0,
-                       0,
-                       &cgavd_sub_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    if (level == QUEUE_LEVEL)
-    {
-        *p_en = cgavd_sub_en.cgavd_flow_sub_en;
-    }
-
-    else if (level == PP_LEVEL)
-    {
-        *p_en = cgavd_sub_en.cgavd_pp_sub_en;
-    }
-
-    else if (level == SYS_LEVEL)
-    {
-        *p_en = cgavd_sub_en.cgavd_sys_sub_en;
-    }
-
-    else if (level == SA_LEVEL)
-    {
-        *p_en = cgavd_sub_en.cgavd_sa_sub_en;
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**  dp选取来源
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级
-* @param   dp_sel   dp选取来源，0-dp，1-tc，2-pkt_len[2:0]
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2017/03/14
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_dp_sel_set(DPP_DEV_T *dev,
-                                   DPP_TM_CGAVD_LEVEL_E level,
-                                   DPP_TM_CGAVD_DP_SEL_E dp_sel)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_CGAVD_DP_SEL_T cgavd_dp_sel = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), dp_sel, DP_SEL_DP, DP_SEL_PKT_LEN);
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CGAVD_CGAVD_DP_SELr,
-                       0,
-                       0,
-                       &cgavd_dp_sel);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    if (QUEUE_LEVEL == level)
-    {
-        if (DP_SEL_DP == dp_sel)
-        {
-            cgavd_dp_sel.flow_dp_sel_high = 0;
-            cgavd_dp_sel.flow_dp_sel_mid = 0;
-            cgavd_dp_sel.flow_dp_sel_low = 1;
-        }
-        else if (DP_SEL_TC == dp_sel)
-        {
-            cgavd_dp_sel.flow_dp_sel_high = 0;
-            cgavd_dp_sel.flow_dp_sel_mid = 1;
-            cgavd_dp_sel.flow_dp_sel_low = 0;
-        }
-        else if (DP_SEL_PKT_LEN == dp_sel)
-        {
-            cgavd_dp_sel.flow_dp_sel_high = 1;
-            cgavd_dp_sel.flow_dp_sel_mid = 0;
-            cgavd_dp_sel.flow_dp_sel_low = 0;
-        }
-    }
-
-    else if (PP_LEVEL == level)
-    {
-        if (DP_SEL_DP == dp_sel)
-        {
-            cgavd_dp_sel.pp_dp_sel_high = 0;
-            cgavd_dp_sel.pp_dp_sel_mid = 0;
-            cgavd_dp_sel.pp_dp_sel_low = 1;
-        }
-        else if (DP_SEL_TC == dp_sel)
-        {
-            cgavd_dp_sel.pp_dp_sel_high = 0;
-            cgavd_dp_sel.pp_dp_sel_mid = 1;
-            cgavd_dp_sel.pp_dp_sel_low = 0;
-        }
-        else if (DP_SEL_PKT_LEN == dp_sel)
-        {
-            cgavd_dp_sel.pp_dp_sel_high = 1;
-            cgavd_dp_sel.pp_dp_sel_mid = 0;
-            cgavd_dp_sel.pp_dp_sel_low = 0;
-        }
-    }
-
-    else if (SYS_LEVEL == level)
-    {
-        if (DP_SEL_DP == dp_sel)
-        {
-            cgavd_dp_sel.sys_dp_sel_high = 0;
-            cgavd_dp_sel.sys_dp_sel_mid = 0;
-            cgavd_dp_sel.sys_dp_sel_low = 1;
-        }
-        else if (DP_SEL_TC == dp_sel)
-        {
-            cgavd_dp_sel.sys_dp_sel_high = 0;
-            cgavd_dp_sel.sys_dp_sel_mid = 1;
-            cgavd_dp_sel.sys_dp_sel_low = 0;
-        }
-        else if (DP_SEL_PKT_LEN == dp_sel)
-        {
-            cgavd_dp_sel.sys_dp_sel_high = 1;
-            cgavd_dp_sel.sys_dp_sel_mid = 0;
-            cgavd_dp_sel.sys_dp_sel_low = 0;
-        }
-    }
-
-    rc  = dpp_reg_write(dev,
-                        ETM_CGAVD_CGAVD_DP_SELr,
-                        0,
-                        0,
-                        &cgavd_dp_sel);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置拥塞避免算法
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号，系统级时，id参数无效
-* @param   method  配置的拥塞避免算法，0:TD，1:WRED/GRED
-*          配置TD算法时，先配TD阈值，再配置TD算法
-*          配置WRED算法时,先配置流级或端口级的平均队列深度，再配置WRED算法
-*          配置GRED算法时，先配置系统级的平均队列深度，在配置成GRED算法
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark
-* @see
-* @author  taq      @date  2015/04/14
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_method_set(DPP_DEV_T *dev,
-                                   DPP_TM_CGAVD_LEVEL_E level,
-                                   ZXIC_UINT32 id,
-                                   DPP_TM_CGAVD_METHOD_E method)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 q_avg_q_len_reg_index = 0;
-    ZXIC_UINT32 q_td_th_reg_index = 0;
-    ZXIC_UINT32 q_ca_mtd_reg_index = 0;
-    ZXIC_UINT32 pp_avg_q_len_reg_index = 0;
-    ZXIC_UINT32 pp_td_th_reg_index = 0;
-    ZXIC_UINT32 pp_ca_mtd_reg_index = 0;
-    ZXIC_UINT32 sys_avg_q_len_reg_index = 0;
-    ZXIC_UINT32 sys_td_th_reg_index = 0;
-    ZXIC_UINT32 sys_ca_mtd_reg_index = 0;
-
-    DPP_ETM_CGAVD_FLOW_CA_MTD_T q_cgavd_method = {0};
-    DPP_ETM_CGAVD_PP_CA_MTD_T pp_cgavd_method = {0};
-    DPP_ETM_CGAVD_SYS_CGAVD_METD_T sys_cgavd_method = {0};
-    DPP_ETM_CGAVD_FLOW_AVG_Q_LEN_T flow_avg_q_len = {0};
-    DPP_ETM_CGAVD_PP_AVG_Q_LEN_T pp_avg_q_len = {0};
-    DPP_ETM_CGAVD_SYS_AVG_Q_LEN_T sys_avg_q_len =  {0};
-    DPP_ETM_CGAVD_FLOW_TD_TH_T q_td_th = {0};
-    DPP_ETM_CGAVD_PP_TD_TH_T pp_td_th = {0};
-    DPP_ETM_CGAVD_SYS_TD_TH_T sys_td_th = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL);
-
-    q_avg_q_len_reg_index = ETM_CGAVD_FLOW_AVG_Q_LENr;
-    q_td_th_reg_index = ETM_CGAVD_FLOW_TD_THr;
-    q_ca_mtd_reg_index = ETM_CGAVD_FLOW_CA_MTDr;
-    pp_avg_q_len_reg_index = ETM_CGAVD_PP_AVG_Q_LENr;
-    pp_td_th_reg_index = ETM_CGAVD_PP_TD_THr;
-    pp_ca_mtd_reg_index = ETM_CGAVD_PP_CA_MTDr;
-    sys_avg_q_len_reg_index = ETM_CGAVD_SYS_AVG_Q_LENr;
-    sys_td_th_reg_index = ETM_CGAVD_SYS_TD_THr;
-    sys_ca_mtd_reg_index = ETM_CGAVD_SYS_CGAVD_METDr;
-
-
-    switch (level)
-    {
-        case (QUEUE_LEVEL):
-        {
-            ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_Q_NUM - 1);
-
-            ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), method, TD_METHOD, WRED_GRED_METHOD);
-
-            if (1 == method) /* WRED算法，需要先配置平均队列深度，在选择wred算法 */
-            {
-                rc  = dpp_reg_read(dev,
-                                   q_avg_q_len_reg_index,
-                                   0,
-                                   id,
-                                   &flow_avg_q_len);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-                rc  = dpp_reg_write(dev,
-                                    q_avg_q_len_reg_index,
-                                    0,
-                                    id,
-                                    &flow_avg_q_len);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-            }
-
-            if (0 == method) /* TD算法，需要先配置尾部丢弃阈值，在选择TD算法 */
-            {
-                rc  = dpp_reg_read(dev,
-                                   q_td_th_reg_index,
-                                   0,
-                                   id,
-                                   &q_td_th);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-
-                rc  = dpp_reg_write(dev,
-                                    q_td_th_reg_index,
-                                    0,
-                                    id,
-                                    &q_td_th);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-            }
-
-            /* 寄存器写入值,0-TD,1-WRED */
-            q_cgavd_method.flow_ca_mtd = method;
-            rc  = dpp_reg_write(dev,
-                                q_ca_mtd_reg_index,
-                                0,
-                                id,
-                                &q_cgavd_method);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-            break;
-        }
-
-        case (PP_LEVEL):
-        {
-            ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_TM_PP_NUM - 1);
-            ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), method, TD_METHOD, WRED_GRED_METHOD);
-
-            if (1 == method) /* WRED算法，需要先配置平均队列深度，在选择wred算法 */
-            {
-                rc  = dpp_reg_read(dev,
-                                   pp_avg_q_len_reg_index,
-                                   0,
-                                   id,
-                                   &pp_avg_q_len);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-                rc  = dpp_reg_write(dev,
-                                    pp_avg_q_len_reg_index,
-                                    0,
-                                    id,
-                                    &pp_avg_q_len);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-            }
-
-            if (0 == method) /* TD算法，尾部丢弃阈值，在选择TD算法 */
-            {
-                rc  = dpp_reg_read(dev,
-                                   pp_td_th_reg_index,
-                                   0,
-                                   id,
-                                   &pp_td_th);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-                rc  = dpp_reg_write(dev,
-                                    pp_td_th_reg_index,
-                                    0,
-                                    id,
-                                    &pp_td_th);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-            }
-
-            /* 寄存器写入值,0-TD,1-WRED */
-            pp_cgavd_method.pp_ca_mtd = method;
-            rc  = dpp_reg_write(dev,
-                                pp_ca_mtd_reg_index,
-                                0,
-                                id,
-                                &pp_cgavd_method);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-
-            break;
-        }
-
-        case (SYS_LEVEL):
-        {
-            ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), method, TD_METHOD, WRED_GRED_METHOD);
-
-            if (1 == method) /* GRED算法，需要先配置平均队列深度，在选择gred算法 */
-            {
-                rc  = dpp_reg_read(dev,
-                                   sys_avg_q_len_reg_index,
-                                   0,
-                                   0,
-                                   &sys_avg_q_len);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-                rc  = dpp_reg_write(dev,
-                                    sys_avg_q_len_reg_index,
-                                    0,
-                                    0,
-                                    &sys_avg_q_len);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-            }
-
-            if (0 == method) /* TD算法，尾部丢弃阈值，在选择TD算法 */
-            {
-                rc  = dpp_reg_read(dev,
-                                   sys_td_th_reg_index,
-                                   0,
-                                   0,
-                                   &sys_td_th);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-                rc  = dpp_reg_write(dev,
-                                    sys_td_th_reg_index,
-                                    0,
-                                    0,
-                                    &sys_td_th);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-            }
-
-            /* 寄存器写入值,0-TD,1-GRED */
-            sys_cgavd_method.sys_cgavd_metd = method;
-            rc  = dpp_reg_write(dev,
-                                sys_ca_mtd_reg_index,
-                                0,
-                                0,
-                                &sys_cgavd_method);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-            break;
-        }
-
-        default:
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "method=%u error!\n", (method));
-            return DPP_ERR;
-        }
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 读取拥塞避免算法
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号,系统级时,id参数无效
-* @param   p_method   配置的拥塞避免算法,0:TD,1:WRED/GRED
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_method_get(DPP_DEV_T *dev,
-                                   DPP_TM_CGAVD_LEVEL_E level,
-                                   ZXIC_UINT32 id,
-                                   DPP_TM_CGAVD_METHOD_E *p_method)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 q_ca_mtd_reg_index = 0;
-    ZXIC_UINT32 pp_ca_mtd_reg_index = 0;
-    ZXIC_UINT32 sys_ca_mtd_reg_index = 0;
-
-    DPP_ETM_CGAVD_FLOW_CA_MTD_T q_cgavd_method = {0};
-    DPP_ETM_CGAVD_PP_CA_MTD_T pp_cgavd_method = {0};
-    DPP_ETM_CGAVD_SYS_CGAVD_METD_T sys_cgavd_method = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_method);
-    
-    *p_method = INVALID_METHOD;
-
-    q_ca_mtd_reg_index = ETM_CGAVD_FLOW_CA_MTDr;
-    pp_ca_mtd_reg_index = ETM_CGAVD_PP_CA_MTDr;
-    sys_ca_mtd_reg_index = ETM_CGAVD_SYS_CGAVD_METDr;
-
-    if (QUEUE_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_Q_NUM - 1);
-
-        rc  = dpp_reg_read(dev,
-                           q_ca_mtd_reg_index,
-                           0,
-                           id,
-                           &q_cgavd_method);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-        *p_method = q_cgavd_method.flow_ca_mtd;
-    }
-
-    else if (PP_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_TM_PP_NUM - 1);
-
-        rc  = dpp_reg_read(dev,
-                           pp_ca_mtd_reg_index,
-                           0,
-                           id,
-                           &pp_cgavd_method);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-        *p_method = pp_cgavd_method.pp_ca_mtd;
-    }
-
-    else
-    {
-        rc  = dpp_reg_read(dev,
-                           sys_ca_mtd_reg_index,
-                           0,
-                           0,
-                           &sys_cgavd_method);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-        *p_method = sys_cgavd_method.sys_cgavd_metd;
-    }
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** CPU设置的各级队列深度配置
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level      拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   q_len_use_cpu_set_en   0：选取RAM中读出的队列深度；
-* @param                          1：选取q_len_cpu_set值
-* @param   q_len_cpu_set    CPU设置的各级队列深度,单位为block。
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_q_len_use_cpu_set(DPP_DEV_T *dev,
-                                    DPP_TM_CGAVD_LEVEL_E level,
-                                    ZXIC_UINT32 q_len_use_cpu_set_en,
-                                    ZXIC_UINT32 q_len_cpu_set)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 rd_cpu_or_ram_reg_index = 0;
-    ZXIC_UINT32 q_cpu_set_q_len_reg_index = 0;
-    ZXIC_UINT32 pp_cpu_set_q_len_reg_index = 0;
-    ZXIC_UINT32 sys_cpu_set_q_len_reg_index = 0;
-
-    DPP_ETM_CGAVD_RD_CPU_OR_RAM_T len_use_cpu_set_en = {0};
-    DPP_ETM_CGAVD_FLOW_CPU_SET_Q_LEN_T flow_q_len_cpu_set = {0};
-    DPP_ETM_CGAVD_PP_CPU_SET_Q_LEN_T pp_q_len_cpu_set = {0};
-    DPP_ETM_CGAVD_SYS_CPU_SET_Q_LEN_T sys_q_len_cpu_set = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_len_use_cpu_set_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_len_cpu_set, 0, 0x1ffffff);
-
-    rd_cpu_or_ram_reg_index = ETM_CGAVD_RD_CPU_OR_RAMr;
-    q_cpu_set_q_len_reg_index = ETM_CGAVD_FLOW_CPU_SET_Q_LENr;
-    pp_cpu_set_q_len_reg_index = ETM_CGAVD_PP_CPU_SET_Q_LENr;
-    sys_cpu_set_q_len_reg_index = ETM_CGAVD_SYS_CPU_SET_Q_LENr;
-
-    rc  = dpp_reg_read(dev,
-                       rd_cpu_or_ram_reg_index,
-                       0,
-                       0,
-                       &len_use_cpu_set_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    switch (level)
-    {
-        case (QUEUE_LEVEL):
-        {
-            len_use_cpu_set_en.cpu_sel_flow_q_len_en = q_len_use_cpu_set_en;
-            rc  = dpp_reg_write(dev,
-                                rd_cpu_or_ram_reg_index,
-                                0,
-                                0,
-                                &len_use_cpu_set_en);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-            if (q_len_use_cpu_set_en == 1)
-            {
-                flow_q_len_cpu_set.flow_cpu_set_q_len = q_len_cpu_set;
-                rc  = dpp_reg_write(dev,
-                                    q_cpu_set_q_len_reg_index,
-                                    0,
-                                    0,
-                                    &flow_q_len_cpu_set);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-            }
-
-
-            break;
-        }
-
-        case (PP_LEVEL):
-        {
-            len_use_cpu_set_en.cpu_sel_pp_q_len_en = q_len_use_cpu_set_en;
-            rc  = dpp_reg_write(dev,
-                                rd_cpu_or_ram_reg_index,
-                                0,
-                                0,
-                                &len_use_cpu_set_en);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-            if (q_len_use_cpu_set_en == 1)
-            {
-                pp_q_len_cpu_set.pp_cpu_set_q_len = q_len_cpu_set;
-                rc  = dpp_reg_write(dev,
-                                    pp_cpu_set_q_len_reg_index,
-                                    0,
-                                    0,
-                                    &pp_q_len_cpu_set);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-            }
-
-            break;
-        }
-
-        case (SYS_LEVEL):
-        {
-            len_use_cpu_set_en.cpu_sel_sys_q_len_en = q_len_use_cpu_set_en;
-            rc  = dpp_reg_write(dev,
-                                rd_cpu_or_ram_reg_index,
-                                0,
-                                0,
-                                &len_use_cpu_set_en);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-            if (q_len_use_cpu_set_en == 1)
-            {
-                sys_q_len_cpu_set.sys_cpu_set_q_len = q_len_cpu_set;
-                rc  = dpp_reg_write(dev,
-                                    sys_cpu_set_q_len_reg_index,
-                                    0,
-                                    0,
-                                    &sys_q_len_cpu_set);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-            }
-
-            break;
-        }
-
-        default:
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "level=%u error!\n", level);
-            return DPP_ERR;
-        }
-
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** CPU设置的各级平均队列深度配置
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level      拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   q_avg_len_use_cpu_set_en   0：选取RAM中读出的队列深度；
-* @param                              1：选取q_avg_len_cpu_set值
-* @param   q_avg_len_cpu_set    CPU设置的各级平均队列深度。
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_q_avg_len_use_cpu_set(DPP_DEV_T *dev,
-                                        DPP_TM_CGAVD_LEVEL_E level,
-                                        ZXIC_UINT32 q_avg_len_use_cpu_set_en,
-                                        ZXIC_UINT32 q_avg_len_cpu_set)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 rd_cpu_or_ram_reg_index = 0;
-    ZXIC_UINT32 q_cpu_set_avg_len_reg_index = 0;
-    ZXIC_UINT32 pp_cpu_set_avg_len_reg_index = 0;
-    ZXIC_UINT32 sys_cpu_set_avg_len_reg_index = 0;
-
-    DPP_ETM_CGAVD_RD_CPU_OR_RAM_T avg_len_use_cpu_set_en = {0};
-    DPP_ETM_CGAVD_FLOW_CPU_SET_AVG_LEN_T flow_q_avg_len_cpu_set = {0};
-    DPP_ETM_CGAVD_PP_CPU_SET_AVG_Q_LEN_T pp_q_avg_len_cpu_set = {0};
-    DPP_ETM_CGAVD_SYS_CPU_SET_AVG_LEN_T  sys_q_avg_len_cpu_set = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_avg_len_use_cpu_set_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_avg_len_cpu_set, 0, 0x1ffffff);
-
-    rd_cpu_or_ram_reg_index = ETM_CGAVD_RD_CPU_OR_RAMr;
-    q_cpu_set_avg_len_reg_index = ETM_CGAVD_FLOW_CPU_SET_AVG_LENr;
-    pp_cpu_set_avg_len_reg_index = ETM_CGAVD_PP_CPU_SET_AVG_Q_LENr;
-    sys_cpu_set_avg_len_reg_index = ETM_CGAVD_SYS_CPU_SET_AVG_LENr;
-
-    rc  = dpp_reg_read(dev,
-                       rd_cpu_or_ram_reg_index,
-                       0,
-                       0,
-                       &avg_len_use_cpu_set_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    switch (level)
-    {
-        case (QUEUE_LEVEL):
-        {
-            avg_len_use_cpu_set_en.cpu_sel_flow_avg_q_len_en = q_avg_len_use_cpu_set_en;
-            rc  = dpp_reg_write(dev,
-                                rd_cpu_or_ram_reg_index,
-                                0,
-                                0,
-                                &avg_len_use_cpu_set_en);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-            if (q_avg_len_use_cpu_set_en == 1)
-            {
-                flow_q_avg_len_cpu_set.flow_cpu_set_avg_len = q_avg_len_cpu_set;
-                rc  = dpp_reg_write(dev,
-                                    q_cpu_set_avg_len_reg_index,
-                                    0,
-                                    0,
-                                    &flow_q_avg_len_cpu_set);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-            }
-
-            break;
-        }
-
-        case (PP_LEVEL):
-        {
-            avg_len_use_cpu_set_en.cpu_sel_pp_avg_q_len_en = q_avg_len_use_cpu_set_en;
-            rc  = dpp_reg_write(dev,
-                                rd_cpu_or_ram_reg_index,
-                                0,
-                                0,
-                                &avg_len_use_cpu_set_en);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-            if (q_avg_len_use_cpu_set_en == 1)
-            {
-                pp_q_avg_len_cpu_set.pp_cpu_set_avg_q_len = q_avg_len_cpu_set;
-                rc  = dpp_reg_write(dev,
-                                    pp_cpu_set_avg_len_reg_index,
-                                    0,
-                                    0,
-                                    &pp_q_avg_len_cpu_set);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-            }
-
-            break;
-        }
-
-        case (SYS_LEVEL):
-        {
-            avg_len_use_cpu_set_en.cpu_sel_sys_avg_q_len_en = q_avg_len_use_cpu_set_en;
-            rc  = dpp_reg_write(dev,
-                                rd_cpu_or_ram_reg_index,
-                                0,
-                                0,
-                                &avg_len_use_cpu_set_en);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-            if (q_avg_len_use_cpu_set_en == 1)
-            {
-                sys_q_avg_len_cpu_set.sys_cpu_set_avg_len = q_avg_len_cpu_set;
-                rc  = dpp_reg_write(dev,
-                                    sys_cpu_set_avg_len_reg_index,
-                                    0,
-                                    0,
-                                    &sys_q_avg_len_cpu_set);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-            }
-
-            break;
-        }
-
-        default:
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "level=%u error!\n", level);
-            return DPP_ERR;
-        }
-
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 流队列级队列深度的获取
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   que_id      队列号
-*          p_len       队列深度以KB为单位
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_flow_que_len_get(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 que_id,
-                                   ZXIC_UINT32 *p_len)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 blk_size = 0;
-    ZXIC_UINT32 cgavd_cfg_mode = 0;
-
-    DPP_ETM_CGAVD_FLOW_Q_LEN_T dpp_tm_flow_len = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_len);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), que_id, 0, DPP_ETM_Q_NUM - 1);
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CGAVD_FLOW_Q_LENr,
-                       0,
-                       que_id,
-                       &dpp_tm_flow_len);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    rc = dpp_tm_cgavd_cfg_mode_get(dev, &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_cfg_mode_get");
-
-    if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE)
-    {
-        rc  = dpp_tm_cfgmt_blk_size_get(dev, &blk_size);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cfgmt_blk_size_get");
-
-        *p_len = ((dpp_tm_flow_len.flow_q_len * blk_size) / DPP_TM_CGAVD_KILO_UL);
-    }
-    else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE)
-    {
-        *p_len = ((dpp_tm_flow_len.flow_q_len) / DPP_TM_CGAVD_KILO_UL);
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_flow_que_len_get:cgavd_cfg_mode is err!!\n");
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
-}
-
-#if 0
-/***********************************************************/
-/** 端口级队列深度的获取
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   pp_id      队列号
-*          pp_len       队列深度以KB为单位
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_port_que_len_get(ZXIC_UINT32 dev_id,
-                                   ZXIC_UINT32 pp_id,
-                                   ZXIC_UINT32 *pp_len)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 blk_size = 0;
-    DPP_ETM_CGAVD_PP_Q_LEN_T dpp_tm_pp_len = {0};
-    ZXIC_UINT32 cgavd_cfg_mode = 0;
-
-    
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, pp_len);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pp_id, 0, DPP_TM_PP_NUM - 1);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CGAVD_FLOW_Q_LENr,
-                       0,
-                       pp_id,
-                       &dpp_tm_pp_len);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get");
-
-    if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE)
-    {
-        rc  = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get");
-
-        *pp_len = ((dpp_tm_pp_len.pp_q_len * blk_size) / DPP_TM_CGAVD_KILO_UL);
-    }
-    else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE)
-    {
-        *pp_len = ((dpp_tm_pp_len.pp_q_len) / DPP_TM_CGAVD_KILO_UL);
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_port_que_len_get  err!!\n");
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 系统级队列深度的获取
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sys_len       系统级深度以block为单位
-*          sys_protocol_len       系统级包含协议队列深度以KB为单位
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_sys_que_len_get(ZXIC_UINT32 dev_id,
-                                  ZXIC_UINT32 *sys_len,
-                                  ZXIC_UINT32 *sys_protocol_len)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 blk_size = 0;
-    ZXIC_UINT32 sys_q_len_reg_index = 0;
-    ZXIC_UINT32 sys_q_len_l_reg_index = 0;
-    DPP_ETM_CGAVD_SYS_Q_LEN_T dpp_tm_sys_len = {0};
-    DPP_ETM_CGAVD_CGAVD_SYS_Q_LEN_L_T dpp_tm_sys_protocol_len = {0};
-    ZXIC_UINT32 cgavd_cfg_mode = 0;
-
-    
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, sys_protocol_len);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, sys_len);
-
-    sys_q_len_reg_index = ETM_CGAVD_SYS_Q_LENr;
-    sys_q_len_l_reg_index = ETM_CGAVD_CGAVD_SYS_Q_LEN_Lr;
-
-    rc  = dpp_reg_read(dev_id,
-                       sys_q_len_reg_index,
-                       0,
-                       0,
-                       &dpp_tm_sys_len);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       sys_q_len_l_reg_index,
-                       0,
-                       0,
-                       &dpp_tm_sys_protocol_len);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get");
-
-    if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE)
-    {
-        rc  = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get");
-
-        *sys_len = ((dpp_tm_sys_len.sys_q_len * blk_size) / DPP_TM_CGAVD_KILO_UL);
-        *sys_protocol_len = ((dpp_tm_sys_protocol_len.cgavd_sys_q_len_l * blk_size) / DPP_TM_CGAVD_KILO_UL);
-    }
-    else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE)
-    {
-        *sys_len = ((dpp_tm_sys_len.sys_q_len) / DPP_TM_CGAVD_KILO_UL);
-        *sys_protocol_len = ((dpp_tm_sys_protocol_len.cgavd_sys_q_len_l) / DPP_TM_CGAVD_KILO_UL);
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_sys_que_len_get  err!!\n");
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
-
-}
-
-#endif
-
-/***********************************************************/
-/** 配置TD拥塞避免模式下的丢弃门限值
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号，系统级时，id参数无效
-* @param   byte_block_th   配置的丢弃门限值，ZXIC_UINT8/BLOCK单位写入寄存器
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/07/29
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_td_byte_block_th_set(DPP_DEV_T *dev,
-                                             DPP_TM_CGAVD_LEVEL_E level,
-                                             ZXIC_UINT32 id,
-                                             ZXIC_UINT32 byte_block_th)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 q_td_th_reg_index = 0;
-    ZXIC_UINT32 q_ca_mtd_reg_index = 0;
-    ZXIC_UINT32 pp_td_th_reg_index = 0;
-    ZXIC_UINT32 pp_ca_mtd_reg_index = 0;
-    ZXIC_UINT32 sys_td_th_reg_index = 0;
-    ZXIC_UINT32 sys_ca_mtd_reg_index = 0;
-    ZXIC_UINT32 read_times = 50;
-    DPP_ETM_CGAVD_FLOW_CA_MTD_T q_cgavd_method = {0};
-    DPP_ETM_CGAVD_FLOW_TD_TH_T q_td_th = {0};
-    DPP_ETM_CGAVD_PP_CA_MTD_T pp_cgavd_method = {0};
-    DPP_ETM_CGAVD_PP_TD_TH_T pp_td_th = {0};
-    DPP_ETM_CGAVD_SYS_CGAVD_METD_T sys_cgavd_method = {0};
-    DPP_ETM_CGAVD_SYS_TD_TH_T sys_td_th = {0};
-    ZXIC_UINT32 qlist_clr_done_flag = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL);
-
-    q_td_th_reg_index = ETM_CGAVD_FLOW_TD_THr;
-    q_ca_mtd_reg_index = ETM_CGAVD_FLOW_CA_MTDr;
-    pp_td_th_reg_index = ETM_CGAVD_PP_TD_THr;
-    pp_ca_mtd_reg_index = ETM_CGAVD_PP_CA_MTDr;
-    sys_td_th_reg_index = ETM_CGAVD_SYS_TD_THr;
-    sys_ca_mtd_reg_index = ETM_CGAVD_SYS_CGAVD_METDr;
-
-    if (QUEUE_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_Q_NUM - 1);
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), byte_block_th, 0, 0x1fffffff);
-
-        q_td_th.flow_td_th = byte_block_th;
-        rc  = dpp_reg_write(dev,
-                            q_td_th_reg_index,
-                            0,
-                            id,
-                            &q_td_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-        q_cgavd_method.flow_ca_mtd = TD_METHOD;
-
-        rc  = dpp_reg_write(dev,
-                            q_ca_mtd_reg_index,
-                            0,
-                            id,
-                            &q_cgavd_method);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-        /* add by zhmy begin@20151103 */
-        if (byte_block_th == 0)
-        {
-            do
-            {
-                rc = dpp_tm_qmu_qlist_qcfg_clr_done_get(dev, &qlist_clr_done_flag);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_qmu_qlist_qcfg_clr_done_get");
-
-                read_times--;
-
-                if (1 == qlist_clr_done_flag)
-                {
-                    break;
-                }
-
-                zxic_comm_delay(10);
-            }
-            while (read_times > 0);
-
-            if (read_times == 0)
-            {
-                ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_qmu_qlist_qcfg_clr_done_get time out\n");
-                return DPP_ERR;
-            }
-
-        }
-
-        /* add by zhmy end@20151103 */
-    }
-
-    else if (PP_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_TM_PP_NUM - 1);
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), byte_block_th, 0, 0x1fffffff);
-
-        pp_td_th.pp_td_th = byte_block_th;
-        rc  = dpp_reg_write(dev,
-                            pp_td_th_reg_index,
-                            0,
-                            id,
-                            &pp_td_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-        pp_cgavd_method.pp_ca_mtd = TD_METHOD;
-        rc  = dpp_reg_write(dev,
-                            pp_ca_mtd_reg_index,
-                            0,
-                            id,
-                            &pp_cgavd_method);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-    }
-
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), byte_block_th, 0, 0x1fffffff);
-
-        sys_td_th.sys_td_th = byte_block_th;
-        rc  = dpp_reg_write(dev,
-                            sys_td_th_reg_index,
-                            0,
-                            0,
-                            &sys_td_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-        sys_cgavd_method.sys_cgavd_metd = TD_METHOD;
-
-        rc  = dpp_reg_write(dev,
-                            sys_ca_mtd_reg_index,
-                            0,
-                            0,
-                            &sys_cgavd_method);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 配置TD拥塞避免模式下的丢弃门限值
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号，系统级时，id参数无效
-* @param   td_th   配置的丢弃门限值，用户配置门限值单位为Kbyte，需要转化为Block或者ZXIC_UINT8单位写入寄存器
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/07/29
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_td_th_set(DPP_DEV_T *dev,
-                                  DPP_TM_CGAVD_LEVEL_E level,
-                                  ZXIC_UINT32 id,
-                                  ZXIC_UINT32 td_th)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 blk_size = 0;
-    ZXIC_UINT32 blk_th = 0;
-    ZXIC_UINT32 cgavd_cfg_mode = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL);
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), td_th, 0, 512*1024);
-
-    td_th = (ZXIC_UINT32)(td_th *  DPP_TM_CGAVD_KILO_UL);
-
-    rc = dpp_tm_cgavd_cfg_mode_get(dev, &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_cfg_mode_get");
-
-    if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE)
-    {
-        rc  = dpp_tm_cfgmt_blk_size_get(dev, &blk_size);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cfgmt_blk_size_get");
-
-        if (blk_size != 0)
-        {
-            blk_th = (td_th / blk_size);
-            blk_th = (td_th % blk_size == 0) ? (blk_th ) : ((blk_th) + 1);
-        }
-
-        rc = dpp_tm_cgavd_td_byte_block_th_set(dev, level, id, blk_th);        
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_td_byte_block_th_set");
-    }
-    else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE)
-    {
-        rc = dpp_tm_cgavd_td_byte_block_th_set(dev, level, id, td_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_td_byte_block_th_set");
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_cgavd_td_th_set err!!\n");
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 读取TD拥塞避免模式下的丢弃门限值
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号，系统级时，id参数无效
-* @param   p_byte_block_th   配置的丢弃门限值ZXIC_UINT8/BLOCK单位
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/07/29
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_td_byte_block_th_get(DPP_DEV_T *dev,
-                                             DPP_TM_CGAVD_LEVEL_E level,
-                                             ZXIC_UINT32 id,
-                                             ZXIC_UINT32 *p_byte_block_th)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 q_td_th_reg_index = 0;
-    ZXIC_UINT32 pp_td_th_reg_index = 0;
-    ZXIC_UINT32 sys_td_th_reg_index = 0;
-    DPP_ETM_CGAVD_FLOW_TD_TH_T q_td_th = {0};
-    DPP_ETM_CGAVD_PP_TD_TH_T pp_td_th = {0};
-    DPP_ETM_CGAVD_SYS_TD_TH_T sys_td_th = {0};
-    
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_byte_block_th);
-    
-
-    if (QUEUE_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_Q_NUM - 1);
-    }
-
-    else if (PP_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_TM_PP_NUM - 1);
-    }
-
-    else
-    {
-        ZXIC_COMM_PRINT("sys:id is not to be checked!!\n");
-    }
-
-    q_td_th_reg_index = ETM_CGAVD_FLOW_TD_THr;
-    pp_td_th_reg_index = ETM_CGAVD_PP_TD_THr;
-    sys_td_th_reg_index = ETM_CGAVD_SYS_TD_THr;
-
-    if (QUEUE_LEVEL == level)
-    {
-        rc  = dpp_reg_read(dev,
-                           q_td_th_reg_index,
-                           0,
-                           id,
-                           &q_td_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-        *p_byte_block_th = q_td_th.flow_td_th;
-    }
-
-    else if (PP_LEVEL == level)
-    {
-        rc  = dpp_reg_read(dev,
-                           pp_td_th_reg_index,
-                           0,
-                           id,
-                           &pp_td_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-        *p_byte_block_th = pp_td_th.pp_td_th;
-    }
-
-    else
-    {
-        rc  = dpp_reg_read(dev,
-                           sys_td_th_reg_index,
-                           0,
-                           0,
-                           &sys_td_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-        *p_byte_block_th = sys_td_th.sys_td_th;
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 读取TD拥塞避免模式下的丢弃门限值
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   队列号或端口号，系统级时，id参数无效
-* @param   p_td_th   配置的丢弃门限值KZXIC_UINT8单位
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/07/29
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_td_th_get(DPP_DEV_T *dev,
-                                  DPP_TM_CGAVD_LEVEL_E level,
-                                  ZXIC_UINT32 id,
-                                  ZXIC_UINT32 *p_td_th)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 cgavd_cfg_mode = 0;
-    ZXIC_UINT32 block_byte_th = 0;
-    ZXIC_UINT32 blk_size = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, SYS_LEVEL);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_td_th);
-
-    *p_td_th = 0;
-
-    if (QUEUE_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_Q_NUM - 1);
-    }
-
-    else if (PP_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_TM_PP_NUM - 1);
-    }
-
-    else
-    {
-        ZXIC_COMM_PRINT("sys:id is not to be checked!!\n");
-    }
-
-    rc = dpp_tm_cgavd_td_byte_block_th_get(dev, level, id, &block_byte_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_td_byte_block_th_get");
-
-    rc = dpp_tm_cgavd_cfg_mode_get(dev, &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_cfg_mode_get");
-
-    if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE)
-    {
-        rc  = dpp_tm_cfgmt_blk_size_get(dev, &blk_size);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cfgmt_blk_size_get");
-
-        *p_td_th = (block_byte_th * blk_size) / DPP_TM_CGAVD_KILO_UL;
-    }
-    else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE)
-    {
-        *p_td_th = (block_byte_th / DPP_TM_CGAVD_KILO_UL);
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_cgavd_td_th_get err!!\n");
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
-
-}
-
-#if 0
-/***********************************************************/
-/** 配置指定端口或队列绑定的WRED GROUP ID
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   id   队列号或端口号
-* @param   wred_id   配置的WRED GROUP ID
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_wred_id_set(ZXIC_UINT32 dev_id,
-                                    DPP_TM_CGAVD_LEVEL_E level,
-                                    ZXIC_UINT32 id,
-                                    ZXIC_UINT32 wred_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 q_wred_grp_reg_index = 0;
-    ZXIC_UINT32 pp_wrd_grp_th_en_reg_index = 0;
-
-    DPP_ETM_CGAVD_FLOW_WRED_GRP_T q_wred_group = {0};
-    DPP_ETM_CGAVD_PP_WRED_GRP_TH_EN_T pp_wred_group = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, PP_LEVEL);
-
-    q_wred_grp_reg_index = ETM_CGAVD_FLOW_WRED_GRPr;
-    pp_wrd_grp_th_en_reg_index = ETM_CGAVD_PP_WRED_GRP_TH_ENr;
-
-    if (QUEUE_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, DPP_ETM_Q_NUM - 1);
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_Q_WRED_NUM - 1);
-
-        q_wred_group.flow_wred_grp = wred_id;
-        rc  = dpp_reg_write(dev_id,
-                            q_wred_grp_reg_index,
-                            0,
-                            id,
-                            &q_wred_group);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, DPP_TM_PP_NUM - 1);
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_PP_WRED_NUM - 1);
-
-        rc  = dpp_reg_read(dev_id,
-                           pp_wrd_grp_th_en_reg_index,
-                           0,
-                           id,
-                           &pp_wred_group);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        pp_wred_group.pp_wred_grp = wred_id;
-        rc  = dpp_reg_write(dev_id,
-                            pp_wrd_grp_th_en_reg_index,
-                            0,
-                            id,
-                            &pp_wred_group);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 读取指定端口或队列绑定的WRED GROUP ID
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   id   队列号或端口号
-* @param   p_wred_id   配置的WRED GROUP ID
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_wred_id_get(ZXIC_UINT32 dev_id,
-                                    DPP_TM_CGAVD_LEVEL_E level,
-                                    ZXIC_UINT32 id,
-                                    ZXIC_UINT32 *p_wred_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 q_wred_grp_reg_index = 0;
-    ZXIC_UINT32 pp_wrd_grp_th_en_reg_index = 0;
-
-    DPP_ETM_CGAVD_FLOW_WRED_GRP_T q_wred_group = {0};
-    DPP_ETM_CGAVD_PP_WRED_GRP_TH_EN_T pp_wred_group = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, PP_LEVEL);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_wred_id);
-
-    q_wred_grp_reg_index = ETM_CGAVD_FLOW_WRED_GRPr;
-    pp_wrd_grp_th_en_reg_index = ETM_CGAVD_PP_WRED_GRP_TH_ENr;
-
-    if (QUEUE_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, DPP_ETM_Q_NUM - 1);
-        rc  = dpp_reg_read(dev_id,
-                           q_wred_grp_reg_index,
-                           0,
-                           id,
-                           &q_wred_group);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-        *p_wred_id = q_wred_group.flow_wred_grp;
-    }
-
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, DPP_TM_PP_NUM - 1);
-        rc  = dpp_reg_read(dev_id,
-                           pp_wrd_grp_th_en_reg_index,
-                           0,
-                           id,
-                           &pp_wred_group);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        *p_wred_id = pp_wred_group.pp_wred_grp;
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 配置WRED丢弃曲线对应的参数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   wred_id   队列级共支持16个WRED组0-15，端口级支持8组0-7
-* @param   dp   共支持8个dp，取值0-7
-* @param   p_para   配置的WRED组参数值，包含以下五个参数
-           max_th  平均队列深度上限阈值ZXIC_UINT8/BLOCK单位
-           min_th  平均队列深度下限阈值ZXIC_UINT8/BLOCK单位
-           max_p  最大丢弃概率
-           weight   平均队列深度计算权重
-           q_len_th 队列深度阈值ZXIC_UINT8/BLOCK单位
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy     @date  2016/08/01
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_wred_dp_line_block_byte_para_set(ZXIC_UINT32 dev_id,
-                                                         DPP_TM_CGAVD_LEVEL_E level,
-                                                         ZXIC_UINT32 wred_id,
-                                                         ZXIC_UINT32 dp,
-                                                         DPP_TM_WRED_DP_LINE_PARA_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT32 q_wred_max_th_reg_index = 0;
-    ZXIC_UINT32 q_wred_min_th_reg_index = 0;
-    ZXIC_UINT32 q_wred_cfg_para_reg_index = 0;
-    ZXIC_UINT32 q_wq_reg_index = 0;
-    ZXIC_UINT32 q_wred_len_th_reg_index = 0;
-
-    ZXIC_UINT32 pp_wred_max_th_reg_index = 0;
-    ZXIC_UINT32 pp_wred_min_th_reg_index = 0;
-    ZXIC_UINT32 pp_wred_cfg_para_reg_index = 0;
-    ZXIC_UINT32 pp_wq_reg_index = 0;
-    ZXIC_UINT32 pp_wred_len_th_reg_index = 0;
-
-    DPP_ETM_CGAVD_FLOW_WRED_MAX_TH_T q_max_th = {0};
-    DPP_ETM_CGAVD_FLOW_WRED_MIN_TH_T q_min_th = {0};
-    DPP_ETM_CGAVD_FLOW_WRED_CFG_PARA_T q_cfg_para = {0};
-    DPP_ETM_CGAVD_FLOW_WQ_T q_wq = {0};
-    DPP_ETM_CGAVD_FLOW_WRED_Q_LEN_TH_T q_len_th = {0};
-    DPP_ETM_CGAVD_PP_WRED_MAX_TH_T pp_max_th = {0};
-    DPP_ETM_CGAVD_PP_WRED_MIN_TH_T pp_min_th = {0};
-    DPP_ETM_CGAVD_PP_CFG_PARA_T pp_cfg_para = {0};
-    DPP_ETM_CGAVD_PP_WQ_T pp_wq = {0};
-    DPP_ETM_CGAVD_PP_WRED_Q_LEN_TH_T pp_len_th = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, PP_LEVEL);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->max_p, 1, DPP_TM_RED_P_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->weight, 0, DPP_TM_CGAVD_WEIGHT_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->max_th, 0, 0x1fffffff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->min_th, 0, 0x1fffffff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->q_len_th, 0, 0x1fffffff);
-
-    q_wred_max_th_reg_index = ETM_CGAVD_FLOW_WRED_MAX_THr;
-    q_wred_min_th_reg_index = ETM_CGAVD_FLOW_WRED_MIN_THr;
-    q_wred_cfg_para_reg_index = ETM_CGAVD_FLOW_WRED_CFG_PARAr;
-    q_wq_reg_index = ETM_CGAVD_FLOW_WQr;
-    q_wred_len_th_reg_index = ETM_CGAVD_FLOW_WRED_Q_LEN_THr;
-
-    pp_wred_max_th_reg_index = ETM_CGAVD_PP_WRED_MAX_THr;
-    pp_wred_min_th_reg_index = ETM_CGAVD_PP_WRED_MIN_THr;
-    pp_wred_cfg_para_reg_index = ETM_CGAVD_PP_CFG_PARAr;
-    pp_wq_reg_index = ETM_CGAVD_PP_WQr;
-    pp_wred_len_th_reg_index = ETM_CGAVD_PP_WRED_Q_LEN_THr;
-
-    ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW(wred_id, DPP_TM_DP_NUM);
-    index = wred_id * DPP_TM_DP_NUM + dp;
-
-    if (QUEUE_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_Q_WRED_NUM - 1);
-
-        /* q_max_th */
-        q_max_th.flow_wred_max_th = p_para->max_th;
-        rc  = dpp_reg_write(dev_id,
-                            q_wred_max_th_reg_index,
-                            0,
-                            index,
-                            &q_max_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        /* q_min_th */
-        q_min_th.flow_wred_min_th = p_para->min_th;
-        rc  = dpp_reg_write(dev_id,
-                            q_wred_min_th_reg_index,
-                            0,
-                            index,
-                            &q_min_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        /* q_cfg_para，乘以100用来换算百分比，用户配置的是值是1-100 */
-        if (p_para->max_p != 0)
-        {
-            ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id,   q_max_th.flow_wred_max_th+1 , q_min_th.flow_wred_min_th);   
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, 100 , (q_max_th.flow_wred_max_th - q_min_th.flow_wred_min_th));
-            q_cfg_para.flow_wred_cfg_para = (ZXIC_UINT32)(100 * (q_max_th.flow_wred_max_th - q_min_th.flow_wred_min_th) / p_para->max_p);
-        }
-        else
-        {
-            q_cfg_para.flow_wred_cfg_para = DPP_TM_Q_WRED_MAX_CFG_PARA;
-        }
-
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, q_cfg_para.flow_wred_cfg_para, 0, 0xffffffff);
-
-        rc  = dpp_reg_write(dev_id,
-                            q_wred_cfg_para_reg_index,
-                            0,
-                            index,
-                            &q_cfg_para);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        /* 必须先写q_wq */
-        q_wq.wq_flow = p_para->weight;
-        rc  = dpp_reg_write(dev_id,
-                            q_wq_reg_index,
-                            0,
-                            wred_id,
-                            &q_wq);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        /* 再写q_len_th */
-        q_len_th.flow_wred_q_len_th = p_para->q_len_th;
-        rc  = dpp_reg_write(dev_id,
-                            q_wred_len_th_reg_index,
-                            0,
-                            wred_id,
-                            &q_len_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_PP_WRED_NUM - 1);
-
-        /* pp_max_th */
-        pp_max_th.pp_wred_max_th = p_para->max_th;
-        rc  = dpp_reg_write(dev_id,
-                            pp_wred_max_th_reg_index,
-                            0,
-                            index,
-                            &pp_max_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        /* pp_min_th */
-        pp_min_th.pp_wred_min_th = p_para->min_th;
-        rc  = dpp_reg_write(dev_id,
-                            pp_wred_min_th_reg_index,
-                            0,
-                            index,
-                            &pp_min_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        /* pp_cfg_para，乘以100用来换算百分比，用户配置的是值是1-100 */
-        if (p_para->max_p != 0)
-        {
-            ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, pp_max_th.pp_wred_max_th+1 , pp_min_th.pp_wred_min_th);
-            pp_cfg_para.pp_cfg_para = (ZXIC_UINT32)(100 * (pp_max_th.pp_wred_max_th - pp_min_th.pp_wred_min_th) / p_para->max_p);
-        }
-        else
-        {
-            pp_cfg_para.pp_cfg_para = DPP_TM_PP_WRED_MAX_CFG_PARA;
-        }
-
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pp_cfg_para.pp_cfg_para, 0, 0xffffffff);
-
-        rc  = dpp_reg_write(dev_id,
-                            pp_wred_cfg_para_reg_index,
-                            0,
-                            index,
-                            &pp_cfg_para);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        /* 必须先写pp_len_th */
-        pp_len_th.pp_wred_q_len_th = p_para->q_len_th;
-        rc  = dpp_reg_write(dev_id,
-                            pp_wred_len_th_reg_index,
-                            0,
-                            wred_id,
-                            &pp_len_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        /* 再写pp_wq */
-        pp_wq.wq_pp = p_para->weight;
-        rc  = dpp_reg_write(dev_id,
-                            pp_wq_reg_index,
-                            0,
-                            wred_id,
-                            &pp_wq);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 配置WRED丢弃曲线对应的参数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   wred_id   队列级共支持16个WRED组0-15，端口级支持8组0-7
-* @param   dp   共支持8个dp，取值0-7
-* @param   p_para   配置的WRED组参数值，用户配置门限值单位为Kbyte，需要转化为Block或者ZXIC_UINT8单位写入寄存器
-            包含以下五个参数
-           max_th  平均队列深度上限阈值
-           min_th  平均队列深度下限阈值
-           max_p  最大丢弃概率
-           weight   平均队列深度计算权重
-           q_len_th 队列深度阈值
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy     @date  2016/08/01
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_wred_dp_line_para_set(ZXIC_UINT32 dev_id,
-                                              DPP_TM_CGAVD_LEVEL_E level,
-                                              ZXIC_UINT32 wred_id,
-                                              ZXIC_UINT32 dp,
-                                              DPP_TM_WRED_DP_LINE_PARA_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 cgavd_cfg_mode = 0;
-    ZXIC_UINT32 blk_size = 0;
-    DPP_TM_WRED_DP_LINE_PARA_T para = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, PP_LEVEL);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1);
-
-    if (QUEUE_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_Q_WRED_NUM - 1);
-    }
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_PP_WRED_NUM - 1);
-    }
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->max_p, 1, DPP_TM_RED_P_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->weight, 0, DPP_TM_CGAVD_WEIGHT_MAX);
-
-    p_para->max_th = p_para->max_th * DPP_TM_CGAVD_KILO_UL;
-    p_para->min_th = p_para->min_th * DPP_TM_CGAVD_KILO_UL;
-    
-    if ((p_para->q_len_th) * DPP_TM_CGAVD_KILO_UL > 0x1fffffff)
-    {
-        p_para->q_len_th = 0x1fffffff;
-    }else{
-        p_para->q_len_th = (ZXIC_UINT32)(p_para->q_len_th) * DPP_TM_CGAVD_KILO_UL;
-    }
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->max_th, p_para->min_th, 0x1fffffff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->min_th, 0, 0x1fffffff);
-
-    para.max_p = p_para->max_p;
-    para.weight = p_para->weight;
-
-    if (p_para->max_th == p_para->min_th)
-    {
-        para.weight = 0;
-    }
-
-    rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get");
-
-    if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE)
-    {
-        rc  = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get");
-
-        if (blk_size != 0)
-        {
-            para.max_th = ((p_para->max_th ) / blk_size);
-            para.max_th = ((p_para->max_th) % blk_size == 0) ? (para.max_th ) : ((para.max_th) + 1);
-            para.min_th = ((p_para->min_th ) / blk_size);
-            para.min_th = ((p_para->min_th) % blk_size == 0) ? (para.min_th ) : ((para.min_th) + 1);
-            para.q_len_th = ((p_para->q_len_th ) / blk_size);
-            para.q_len_th = ((p_para->q_len_th) % blk_size == 0) ? (para.q_len_th ) : ((para.q_len_th) + 1);
-        }
-
-    }
-    else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE)
-    {
-        para.max_th = p_para->max_th;
-        para.min_th = p_para->min_th;
-        para.q_len_th = p_para->q_len_th;
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_cgavd_wred_dp_line_para_set err!!\n");
-        return DPP_ERR;
-    }
-
-    rc = dpp_tm_cgavd_wred_dp_line_block_byte_para_set(dev_id, level, wred_id, dp, &para);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_wred_dp_line_block_byte_para_set");
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 读取WRED丢弃曲线对应的参数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   wred_id   队列级共支持16个WRED组0-15，端口级支持8组0-7
-* @param   dp   共支持8个dp，取值0-7
-* @param   p_para   配置的WRED组参数值，包含以下五个参数
-           max_th  平均队列深度上限阈值ZXIC_UINT8/BLOCK单位
-           min_th  平均队列深度下限阈值ZXIC_UINT8/BLOCK单位
-           max_p  最大丢弃概率
-           weight   平均队列深度计算权重
-           q_len_th 队列深度阈值ZXIC_UINT8/BLOCK单位
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy     @date  2016/08/01
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_wred_dp_line_block_byte_para_get(ZXIC_UINT32 dev_id,
-                                                         DPP_TM_CGAVD_LEVEL_E level,
-                                                         ZXIC_UINT32 wred_id,
-                                                         ZXIC_UINT32 dp,
-                                                         DPP_TM_WRED_DP_LINE_PARA_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT32 q_wred_max_th_reg_index = 0;
-    ZXIC_UINT32 q_wred_min_th_reg_index = 0;
-    ZXIC_UINT32 q_wred_cfg_para_reg_index = 0;
-    ZXIC_UINT32 q_wq_reg_index = 0;
-    ZXIC_UINT32 q_wred_len_th_reg_index = 0;
-
-    ZXIC_UINT32 pp_wred_max_th_reg_index = 0;
-    ZXIC_UINT32 pp_wred_min_th_reg_index = 0;
-    ZXIC_UINT32 pp_wred_cfg_para_reg_index = 0;
-    ZXIC_UINT32 pp_wq_reg_index = 0;
-    ZXIC_UINT32 pp_wred_len_th_reg_index = 0;
-
-    DPP_ETM_CGAVD_FLOW_WRED_MAX_TH_T q_max_th = {0};
-    DPP_ETM_CGAVD_FLOW_WRED_MIN_TH_T q_min_th = {0};
-    DPP_ETM_CGAVD_FLOW_WRED_CFG_PARA_T q_cfg_para = {0};
-    DPP_ETM_CGAVD_FLOW_WQ_T q_wq = {0};
-    DPP_ETM_CGAVD_FLOW_WRED_Q_LEN_TH_T q_len_th = {0};
-    DPP_ETM_CGAVD_PP_WRED_MAX_TH_T pp_max_th = {0};
-    DPP_ETM_CGAVD_PP_WRED_MIN_TH_T pp_min_th = {0};
-    DPP_ETM_CGAVD_PP_CFG_PARA_T pp_cfg_para = {0};
-    DPP_ETM_CGAVD_PP_WQ_T pp_wq = {0};
-    DPP_ETM_CGAVD_PP_WRED_Q_LEN_TH_T pp_len_th = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, PP_LEVEL);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-
-    q_wred_max_th_reg_index = ETM_CGAVD_FLOW_WRED_MAX_THr;
-    q_wred_min_th_reg_index = ETM_CGAVD_FLOW_WRED_MIN_THr;
-    q_wred_cfg_para_reg_index = ETM_CGAVD_FLOW_WRED_CFG_PARAr;
-    q_wq_reg_index = ETM_CGAVD_FLOW_WQr;
-    q_wred_len_th_reg_index = ETM_CGAVD_FLOW_WRED_Q_LEN_THr;
-
-    pp_wred_max_th_reg_index = ETM_CGAVD_PP_WRED_MAX_THr;
-    pp_wred_min_th_reg_index = ETM_CGAVD_PP_WRED_MIN_THr;
-    pp_wred_cfg_para_reg_index = ETM_CGAVD_PP_CFG_PARAr;
-    pp_wq_reg_index = ETM_CGAVD_PP_WQr;
-    pp_wred_len_th_reg_index = ETM_CGAVD_PP_WRED_Q_LEN_THr;
-
-    ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, wred_id , DPP_TM_DP_NUM);
-    index = wred_id * DPP_TM_DP_NUM + dp;
-
-    if (QUEUE_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_Q_WRED_NUM - 1);
-
-        /* q_max_th */
-        rc  = dpp_reg_read(dev_id,
-                           q_wred_max_th_reg_index,
-                           0,
-                           index,
-                           &q_max_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        /* q_min_th */
-        rc  = dpp_reg_read(dev_id,
-                           q_wred_min_th_reg_index,
-                           0,
-                           index,
-                           &q_min_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        /* q_cfg_para */
-        rc  = dpp_reg_read(dev_id,
-                           q_wred_cfg_para_reg_index,
-                           0,
-                           index,
-                           &q_cfg_para);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        /* q_wq */
-        rc  = dpp_reg_read(dev_id,
-                           q_wq_reg_index,
-                           0,
-                           wred_id,
-                           &q_wq);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        /* q_len_th */
-        rc  = dpp_reg_read(dev_id,
-                           q_wred_len_th_reg_index,
-                           0,
-                           wred_id,
-                           &q_len_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        p_para->max_th = q_max_th.flow_wred_max_th;
-        p_para->min_th = q_min_th.flow_wred_min_th;
-
-        if (q_cfg_para.flow_wred_cfg_para != 0)
-        {
-            p_para->max_p = (ZXIC_UINT32)(100 * (q_max_th.flow_wred_max_th - q_min_th.flow_wred_min_th) / q_cfg_para.flow_wred_cfg_para);
-        }
-        else
-        {
-            p_para->max_p = 0;
-        }
-
-        p_para->q_len_th = q_len_th.flow_wred_q_len_th;
-        p_para->weight = q_wq.wq_flow;
-    }
-
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_PP_WRED_NUM - 1);
-
-        /* pp_max_th */
-        rc  = dpp_reg_read(dev_id,
-                           pp_wred_max_th_reg_index,
-                           0,
-                           index,
-                           &pp_max_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        /* pp_min_th */
-        rc  = dpp_reg_read(dev_id,
-                           pp_wred_min_th_reg_index,
-                           0,
-                           index,
-                           &pp_min_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        /* pp_cfg_para */
-        rc  = dpp_reg_read(dev_id,
-                           pp_wred_cfg_para_reg_index,
-                           0,
-                           index,
-                           &pp_cfg_para);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        /* pp_wq */
-        rc  = dpp_reg_read(dev_id,
-                           pp_wq_reg_index,
-                           0,
-                           wred_id,
-                           &pp_wq);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        /* q_len_th */
-        rc  = dpp_reg_read(dev_id,
-                           pp_wred_len_th_reg_index,
-                           0,
-                           wred_id,
-                           &pp_len_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        p_para->max_th = pp_max_th.pp_wred_max_th;
-        p_para->min_th = pp_min_th.pp_wred_min_th;
-
-        if (pp_cfg_para.pp_cfg_para != 0)
-        {
-            p_para->max_p = (ZXIC_UINT32)(100 * (pp_max_th.pp_wred_max_th - pp_min_th.pp_wred_min_th) / pp_cfg_para.pp_cfg_para);
-        }
-        else
-        {
-            p_para->max_p = 0;
-        }
-
-        p_para->q_len_th = pp_len_th.pp_wred_q_len_th;
-        p_para->weight = pp_wq.wq_pp;
-    }
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 读取WRED丢弃曲线对应的参数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   wred_id   队列级共支持16个WRED组0-15，端口级支持8组0-7
-* @param   dp   共支持8个dp，取值0-7
-* @param   p_para   配置的WRED组参数值，包含以下五个参数
-           max_th  平均队列深度上限阈值
-           min_th  平均队列深度下限阈值
-           max_p  最大丢弃概率
-           weight   平均队列深度计算权重
-           q_len_th 队列深度阈值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author cy     @date  2016/08/01
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_wred_dp_line_para_get(ZXIC_UINT32 dev_id,
-                                              DPP_TM_CGAVD_LEVEL_E level,
-                                              ZXIC_UINT32 wred_id,
-                                              ZXIC_UINT32 dp,
-                                              DPP_TM_WRED_DP_LINE_PARA_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 blk_size = 0;
-    ZXIC_UINT32 cgavd_cfg_mode = 0;
-    DPP_TM_WRED_DP_LINE_PARA_T para = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, PP_LEVEL);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-
-    if (QUEUE_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_Q_WRED_NUM - 1);
-    }
-
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_PP_WRED_NUM - 1);
-    }
-
-    rc = dpp_tm_cgavd_wred_dp_line_block_byte_para_get(dev_id, level, wred_id, dp, &para);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_wred_dp_line_block_byte_para_set");
-
-    p_para->max_p = para.max_p;
-    p_para->weight = para.weight;
-
-    rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get");
-
-    if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE)
-    {
-        rc  = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get");
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, blk_size, 256, 1024);
-
-        p_para->max_th = (para.max_th * blk_size) / DPP_TM_CGAVD_KILO_UL;
-        p_para->min_th = (para.min_th * blk_size) / DPP_TM_CGAVD_KILO_UL;
-        p_para->q_len_th = (para.q_len_th * blk_size) / DPP_TM_CGAVD_KILO_UL;
-
-    }
-    else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE)
-    {
-        p_para->max_th = (para.max_th / DPP_TM_CGAVD_KILO_UL);
-        p_para->min_th = (para.min_th / DPP_TM_CGAVD_KILO_UL);
-        p_para->q_len_th = (para.q_len_th / DPP_TM_CGAVD_KILO_UL);
-
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_cgavd_wred_dp_line_para_get err!!\n");
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 配置系统级GRED丢弃曲线对应的参数
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   dp   共支持8个dp，取值0-7
-* @param   p_para  配置的GRED丢弃曲线参数值，包含以下六个参数
-           max_th  平均队列深度上限阈值ZXIC_UINT8/BLOCK单位
-           mid_th  平均队列深度中间阈值ZXIC_UINT8/BLOCK单位
-           min_th  平均队列深度下限阈值ZXIC_UINT8/BLOCK单位
-           max_p   最大丢弃概率[1-99]
-           weight   平均队列深度计算权重
-           q_len_th 队列深度阈值ZXIC_UINT8/BLOCK单位
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/08/02
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_gred_dp_line_block_byte_para_set(ZXIC_UINT32 dev_id,
-                                                         ZXIC_UINT32 dp,
-                                                         DPP_TM_GRED_DP_LINE_PARA_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 gred_max_th_reg_index = 0;
-    ZXIC_UINT32 gred_mid_th_reg_index = 0;
-    ZXIC_UINT32 gred_min_th_reg_index = 0;
-    ZXIC_UINT32 gred_cfg_para0_reg_index = 0;
-    ZXIC_UINT32 gred_cfg_para1_reg_index = 0;
-    ZXIC_UINT32 gred_cfg_para2_reg_index = 0;
-    ZXIC_UINT32 gred_sys_wfq_reg_index = 0;
-    ZXIC_UINT32 gred_sys_cfg_q_grp_para_reg_index = 0;
-
-    DPP_ETM_CGAVD_GRED_MAX_TH_T max_th = {0};
-    DPP_ETM_CGAVD_GRED_MID_TH_T mid_th = {0};
-    DPP_ETM_CGAVD_GRED_MIN_TH_T min_th = {0};
-    DPP_ETM_CGAVD_GRED_CFG_PARA0_T cfg_para0 = {0};
-    DPP_ETM_CGAVD_GRED_CFG_PARA1_T cfg_para1 = {0};
-    DPP_ETM_CGAVD_GRED_CFG_PARA2_T cfg_para2 = {0};
-    DPP_ETM_CGAVD_SYS_WQ_T sys_wq = {0};
-    DPP_ETM_CGAVD_SYS_CFG_Q_GRP_PARA_T sys_len_th = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->max_p, 1, DPP_TM_RED_P_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->weight, 0, DPP_TM_CGAVD_WEIGHT_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->max_th, 0, 0x1fffffff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->mid_th, 0, 0x1fffffff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->min_th, 0, 0x1fffffff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->q_len_th, 0, 0x1fffffff);
-
-    gred_max_th_reg_index = ETM_CGAVD_GRED_MAX_THr;
-    gred_mid_th_reg_index = ETM_CGAVD_GRED_MID_THr;
-    gred_min_th_reg_index = ETM_CGAVD_GRED_MIN_THr;
-    gred_cfg_para0_reg_index = ETM_CGAVD_GRED_CFG_PARA0r;
-    gred_cfg_para1_reg_index = ETM_CGAVD_GRED_CFG_PARA1r;
-    gred_cfg_para2_reg_index = ETM_CGAVD_GRED_CFG_PARA2r;
-    gred_sys_wfq_reg_index = ETM_CGAVD_SYS_WQr;
-    gred_sys_cfg_q_grp_para_reg_index = ETM_CGAVD_SYS_CFG_Q_GRP_PARAr;
-
-    /* max_th */
-    max_th.gred_max_th = p_para->max_th;
-    rc  = dpp_reg_write(dev_id,
-                        gred_max_th_reg_index,
-                        0,
-                        dp,
-                        &max_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    /* mid_th */
-    mid_th.gred_mid_th = p_para->mid_th;
-    rc  = dpp_reg_write(dev_id,
-                        gred_mid_th_reg_index,
-                        0,
-                        dp,
-                        &mid_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    /* min_th */
-    min_th.gred_min_th = p_para->min_th;
-    rc  = dpp_reg_write(dev_id,
-                        gred_min_th_reg_index,
-                        0,
-                        dp,
-                        &min_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    /* cfg_para0，乘以100用来换算百分比，用户配置的是值是1-100 */
-    ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, mid_th.gred_mid_th+1 , min_th.gred_min_th);
-    ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, 100 , (mid_th.gred_mid_th - min_th.gred_min_th));
-    cfg_para0.gred_cfg_para0 = (ZXIC_UINT32)(100 * (mid_th.gred_mid_th - min_th.gred_min_th) / p_para->max_p);
-
-    rc  = dpp_reg_write(dev_id,
-                        gred_cfg_para0_reg_index,
-                        0,
-                        dp,
-                        &cfg_para0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    /* cfg_para1 */
-    ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id, max_th.gred_max_th+1 , mid_th.gred_mid_th);
-    cfg_para1.gred_cfg_para1 = (ZXIC_UINT32)(100 * (max_th.gred_max_th - mid_th.gred_mid_th) / (100 - p_para->max_p));
-
-    rc  = dpp_reg_write(dev_id,
-                        gred_cfg_para1_reg_index,
-                        0,
-                        dp,
-                        &cfg_para1);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    /* cfg_para2 */
-    ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, p_para->max_p , cfg_para1.gred_cfg_para1);
-    cfg_para2.gred_cfg_para2 = (ZXIC_UINT32)(p_para->max_p * cfg_para1.gred_cfg_para1 / 100);
-
-    rc  = dpp_reg_write(dev_id,
-                        gred_cfg_para2_reg_index,
-                        0,
-                        dp,
-                        &cfg_para2);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    /* 必须先写sys_len_th */
-    sys_len_th.gred_q_len_th_sys = p_para->q_len_th;
-    rc  = dpp_reg_write(dev_id,
-                        gred_sys_cfg_q_grp_para_reg_index,
-                        0,
-                        0,
-                        &sys_len_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    /* 再写sys_wq */
-    sys_wq.wq_sys = p_para->weight;
-    rc  = dpp_reg_write(dev_id,
-                        gred_sys_wfq_reg_index,
-                        0,
-                        0,
-                        &sys_wq);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置系统级GRED丢弃曲线对应的参数
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   dp   共支持8个dp，取值0-7
-* @param   p_para  配置的GRED丢弃曲线参数值，用户配置门限值单位为Kbyte，需要转化为Block或者ZXIC_UINT8单位写入寄存器
-        包含以下六个参数
-           max_th  平均队列深度上限阈值
-           mid_th  平均队列深度中间阈值
-           min_th  平均队列深度下限阈值
-           max_p   最大丢弃概率
-           weight   平均队列深度计算权重
-           q_len_th 队列深度阈值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/08/02
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_gred_dp_line_para_set(ZXIC_UINT32 dev_id,
-                                              ZXIC_UINT32 dp,
-                                              DPP_TM_GRED_DP_LINE_PARA_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 cgavd_cfg_mode = 0;
-    ZXIC_UINT32 blk_size = 0;
-    DPP_TM_GRED_DP_LINE_PARA_T para = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->max_p, 1, DPP_TM_RED_P_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->weight, 0, DPP_TM_CGAVD_WEIGHT_MAX);
-
-    p_para->max_th = p_para->max_th * DPP_TM_CGAVD_KILO_UL;
-    p_para->mid_th = p_para->mid_th * DPP_TM_CGAVD_KILO_UL;
-    p_para->min_th = p_para->min_th * DPP_TM_CGAVD_KILO_UL;
-    if ((p_para->q_len_th) * DPP_TM_CGAVD_KILO_UL > 0x1fffffff)
-    {
-        p_para->q_len_th = 0x1fffffff;
-    }else{
-        p_para->q_len_th = (p_para->q_len_th) * DPP_TM_CGAVD_KILO_UL;
-    }
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->max_th, 0, 0x1fffffff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->mid_th, 0, 0x1fffffff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, p_para->min_th, 0, 0x1fffffff);
-    
-    para.max_p = p_para->max_p;
-    para.weight = p_para->weight;
-
-    rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get");
-
-    if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE)
-    {
-        rc  = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get");
-
-        if (blk_size != 0)
-        {
-            para.max_th = ((p_para->max_th ) / blk_size);
-            para.max_th = ((p_para->max_th) % blk_size == 0) ? (para.max_th ) : ((para.max_th) + 1);
-            para.mid_th = ((p_para->mid_th ) / blk_size);
-            para.mid_th = ((p_para->mid_th) % blk_size == 0) ? (para.mid_th ) : ((para.mid_th) + 1);
-            para.min_th = ((p_para->min_th ) / blk_size);
-            para.min_th = ((p_para->min_th) % blk_size == 0) ? (para.min_th ) : ((para.min_th) + 1);
-            para.q_len_th = ((p_para->q_len_th ) / blk_size);
-            para.q_len_th = ((p_para->q_len_th) % blk_size == 0) ? (para.q_len_th ) : ((para.q_len_th) + 1);
-        }
-
-    }
-    else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE)
-    {
-        para.max_th = p_para->max_th;
-        para.mid_th = p_para->mid_th;
-        para.min_th = p_para->min_th;
-        para.q_len_th = p_para->q_len_th;
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_cgavd_gred_dp_line_para_set err!!\n");
-        return DPP_ERR;
-    }
-
-    rc = dpp_tm_cgavd_gred_dp_line_block_byte_para_set(dev_id, dp, &para);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_gred_dp_line_block_byte_para_set");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置系统级阶梯TD 丢弃曲线对应的参数
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   dp   共支持8个dp，取值0-7
-* @param   td_th  TD 门限
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/08/02
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_ladtd_dp_line_para_set(ZXIC_UINT32 dev_id,
-                                               ZXIC_UINT32 dp,
-                                               ZXIC_UINT32 td_th)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 gred_max_th_reg_index = 0;
-    ZXIC_UINT32 gred_mid_th_reg_index = 0;
-    ZXIC_UINT32 gred_min_th_reg_index = 0;
-    ZXIC_UINT32 gred_cfg_para0_reg_index = 0;
-    ZXIC_UINT32 gred_cfg_para1_reg_index = 0;
-    ZXIC_UINT32 gred_cfg_para2_reg_index = 0;
-    ZXIC_UINT32 cgavd_cfg_mode = 0;
-    ZXIC_UINT32 blk_size = 0;
-
-    DPP_ETM_CGAVD_GRED_MAX_TH_T max_th = {0};
-    DPP_ETM_CGAVD_GRED_MID_TH_T mid_th = {0};
-    DPP_ETM_CGAVD_GRED_MIN_TH_T min_th = {0};
-    DPP_ETM_CGAVD_GRED_CFG_PARA0_T cfg_para0 = {0};
-    DPP_ETM_CGAVD_GRED_CFG_PARA1_T cfg_para1 = {0};
-    DPP_ETM_CGAVD_GRED_CFG_PARA2_T cfg_para2 = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1);
-
-    td_th = td_th * DPP_TM_CGAVD_KILO_UL;
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, td_th, 0, 0x1fffffff);
-
-    rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get");
-
-    if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE)
-    {
-        rc  = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get");
-
-        if (blk_size != 0)
-        {
-            max_th.gred_max_th = (( td_th ) / blk_size);
-            max_th.gred_max_th = ((td_th) % blk_size == 0) ? ( max_th.gred_max_th ) : (( max_th.gred_max_th) + 1);
-            mid_th.gred_mid_th = (( td_th ) / blk_size);
-            mid_th.gred_mid_th = ((td_th) % blk_size == 0) ? ( mid_th.gred_mid_th ) : (( mid_th.gred_mid_th) + 1);
-            min_th.gred_min_th = (( td_th ) / blk_size);
-            min_th.gred_min_th = ((td_th) % blk_size == 0) ? ( min_th.gred_min_th ) : (( min_th.gred_min_th) + 1);
-
-        }
-
-    }
-    else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE)
-    {
-        max_th.gred_max_th = td_th;
-        mid_th.gred_mid_th = td_th;
-        min_th.gred_min_th = td_th;
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_cgavd_gred_dp_line_para_get err!!\n");
-        return DPP_ERR;
-    }
-
-    gred_max_th_reg_index = ETM_CGAVD_GRED_MAX_THr;
-    gred_mid_th_reg_index = ETM_CGAVD_GRED_MID_THr;
-    gred_min_th_reg_index = ETM_CGAVD_GRED_MIN_THr;
-    gred_cfg_para0_reg_index = ETM_CGAVD_GRED_CFG_PARA0r;
-    gred_cfg_para1_reg_index = ETM_CGAVD_GRED_CFG_PARA1r;
-    gred_cfg_para2_reg_index = ETM_CGAVD_GRED_CFG_PARA2r;
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, td_th, 0, 0x1fffffff);
-
-
-    /* max_th */
-    rc  = dpp_reg_write(dev_id,
-                        gred_max_th_reg_index,
-                        0,
-                        dp,
-                        &max_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    /* mid_th */
-    rc  = dpp_reg_write(dev_id,
-                        gred_mid_th_reg_index,
-                        0,
-                        dp,
-                        &mid_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    /* min_th */
-    rc  = dpp_reg_write(dev_id,
-                        gred_min_th_reg_index,
-                        0,
-                        dp,
-                        &min_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    /* cfg_para0，0 */
-    cfg_para0.gred_cfg_para0 = 0;
-
-    rc  = dpp_reg_write(dev_id,
-                        gred_cfg_para0_reg_index,
-                        0,
-                        dp,
-                        &cfg_para0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    /* cfg_para1 */
-    cfg_para1.gred_cfg_para1 = 0;
-
-    rc  = dpp_reg_write(dev_id,
-                        gred_cfg_para1_reg_index,
-                        0,
-                        dp,
-                        &cfg_para1);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    /* cfg_para2 */
-    cfg_para2.gred_cfg_para2 = 0;
-
-    rc  = dpp_reg_write(dev_id,
-                        gred_cfg_para2_reg_index,
-                        0,
-                        dp,
-                        &cfg_para2);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 读取系统级GRED丢弃曲线对应的参数
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   dp   共支持8个dp，取值0-7
-* @param   p_para  配置的GRED丢弃曲线参数值，包含以下六个参数
-           max_th  平均队列深度上限阈值ZXIC_UINT8/BLOCK单位
-           mid_th  平均队列深度中间阈值ZXIC_UINT8/BLOCK单位
-           min_th  平均队列深度下限阈值ZXIC_UINT8/BLOCK单位
-           max_p   最大丢弃概率
-           weight   平均队列深度计算权重
-           q_len_th 队列深度阈值ZXIC_UINT8/BLOCK单位
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/08/02
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_gred_dp_line_block_byte_para_get(ZXIC_UINT32 dev_id,
-                                                         ZXIC_UINT32 dp,
-                                                         DPP_TM_GRED_DP_LINE_PARA_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 gred_max_th_reg_index = 0;
-    ZXIC_UINT32 gred_mid_th_reg_index = 0;
-    ZXIC_UINT32 gred_min_th_reg_index = 0;
-    ZXIC_UINT32 gred_cfg_para0_reg_index = 0;
-    ZXIC_UINT32 gred_cfg_para1_reg_index = 0;
-    ZXIC_UINT32 gred_cfg_para2_reg_index = 0;
-    ZXIC_UINT32 gred_sys_wfq_reg_index = 0;
-    ZXIC_UINT32 gred_sys_cfg_q_grp_para_reg_index = 0;
-
-    DPP_ETM_CGAVD_GRED_MAX_TH_T max_th = {0};
-    DPP_ETM_CGAVD_GRED_MID_TH_T mid_th = {0};
-    DPP_ETM_CGAVD_GRED_MIN_TH_T min_th = {0};
-    DPP_ETM_CGAVD_GRED_CFG_PARA0_T cfg_para0 = {0};
-    DPP_ETM_CGAVD_GRED_CFG_PARA1_T cfg_para1 = {0};
-    DPP_ETM_CGAVD_GRED_CFG_PARA2_T cfg_para2 = {0};
-    DPP_ETM_CGAVD_SYS_WQ_T sys_wq = {0};
-    DPP_ETM_CGAVD_SYS_CFG_Q_GRP_PARA_T sys_len_th = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-
-    gred_max_th_reg_index = ETM_CGAVD_GRED_MAX_THr;
-    gred_mid_th_reg_index = ETM_CGAVD_GRED_MID_THr;
-    gred_min_th_reg_index = ETM_CGAVD_GRED_MIN_THr;
-    gred_cfg_para0_reg_index = ETM_CGAVD_GRED_CFG_PARA0r;
-    gred_cfg_para1_reg_index = ETM_CGAVD_GRED_CFG_PARA1r;
-    gred_cfg_para2_reg_index = ETM_CGAVD_GRED_CFG_PARA2r;
-    gred_sys_wfq_reg_index = ETM_CGAVD_SYS_WQr;
-    gred_sys_cfg_q_grp_para_reg_index = ETM_CGAVD_SYS_CFG_Q_GRP_PARAr;
-
-    /* max_th */
-    rc  = dpp_reg_read(dev_id,
-                       gred_max_th_reg_index,
-                       0,
-                       dp,
-                       &max_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    /* mid_th */
-    rc  = dpp_reg_read(dev_id,
-                       gred_mid_th_reg_index,
-                       0,
-                       dp,
-                       &mid_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    /* min_th */
-    rc  = dpp_reg_read(dev_id,
-                       gred_min_th_reg_index,
-                       0,
-                       dp,
-                       &min_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    /* cfg_para0 */
-    rc  = dpp_reg_read(dev_id,
-                       gred_cfg_para0_reg_index,
-                       0,
-                       dp,
-                       &cfg_para0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    /* cfg_para1 */
-    rc  = dpp_reg_read(dev_id,
-                       gred_cfg_para1_reg_index,
-                       0,
-                       dp,
-                       &cfg_para1);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-
-    /* cfg_para2 */
-    rc  = dpp_reg_read(dev_id,
-                       gred_cfg_para2_reg_index,
-                       0,
-                       dp,
-                       &cfg_para2);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    /* sys_len_th */
-    rc  = dpp_reg_read(dev_id,
-                       gred_sys_cfg_q_grp_para_reg_index,
-                       0,
-                       0,
-                       &sys_len_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    /* sys_wq */
-    rc  = dpp_reg_read(dev_id,
-                       gred_sys_wfq_reg_index,
-                       0,
-                       0,
-                       &sys_wq);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    p_para->max_th = max_th.gred_max_th;
-    p_para->mid_th = mid_th.gred_mid_th;
-    p_para->min_th = min_th.gred_min_th;
-
-    if (cfg_para0.gred_cfg_para0)
-    {
-        p_para->max_p  = (ZXIC_UINT32)(100 * (mid_th.gred_mid_th - min_th.gred_min_th) / cfg_para0.gred_cfg_para0);
-    }
-
-    p_para->weight = sys_wq.wq_sys;
-    p_para->q_len_th = sys_len_th.gred_q_len_th_sys;
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 读取系统级GRED丢弃曲线对应的参数
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   dp   共支持8个dp，取值0-7
-* @param   p_para  配置的GRED丢弃曲线参数值，包含以下六个参数
-           max_th  平均队列深度上限阈值
-           mid_th  平均队列深度中间阈值
-           min_th  平均队列深度下限阈值
-           max_p   最大丢弃概率
-           weight   平均队列深度计算权重
-           q_len_th 队列深度阈值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/04/20
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_gred_dp_line_para_get(ZXIC_UINT32 dev_id,
-                                              ZXIC_UINT32 dp,
-                                              DPP_TM_GRED_DP_LINE_PARA_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 cgavd_cfg_mode = 0;
-    ZXIC_UINT32 blk_size = 0;
-    DPP_TM_GRED_DP_LINE_PARA_T para = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-    
-
-    rc = dpp_tm_cgavd_gred_dp_line_block_byte_para_get(dev_id, dp, &para);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_gred_dp_line_block_byte_para_get");
-
-    p_para->max_p = para.max_p;
-    p_para->weight = para.weight;
-
-    rc = dpp_tm_cgavd_cfg_mode_get(dev_id, &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_cfg_mode_get");
-
-    if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE)
-    {
-        rc  = dpp_tm_cfgmt_blk_size_get(dev_id, &blk_size);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_get");
-
-        p_para->max_th = (para.max_th * blk_size) / DPP_TM_CGAVD_KILO_UL;
-        p_para->mid_th = (para.mid_th * blk_size) / DPP_TM_CGAVD_KILO_UL;
-        p_para->min_th = (para.min_th * blk_size) / DPP_TM_CGAVD_KILO_UL;
-        p_para->q_len_th = (para.q_len_th * blk_size) / DPP_TM_CGAVD_KILO_UL;
-
-    }
-    else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE)
-    {
-        p_para->max_th = (para.max_th / DPP_TM_CGAVD_KILO_UL);
-        p_para->mid_th = (para.mid_th / DPP_TM_CGAVD_KILO_UL);
-        p_para->min_th = (para.min_th / DPP_TM_CGAVD_KILO_UL);
-        p_para->q_len_th = (para.q_len_th / DPP_TM_CGAVD_KILO_UL);
-
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_cgavd_gred_dp_line_para_get err!!\n");
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
-
-}
-
-#endif
-/***********************************************************/
-/** 配置指定端口或队列是否支持动态门限机制
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   id   队列号或端口号
-* @param   en   配置的值，0-不支持动态门限机制，1-支持动态门限机制
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_dyn_th_en_set(DPP_DEV_T *dev,
-                                      DPP_TM_CGAVD_LEVEL_E level,
-                                      ZXIC_UINT32 id,
-                                      ZXIC_UINT32 en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 q_dyn_th_en_reg_index = 0;
-    ZXIC_UINT32 pp_wrd_grp_th_en_reg_index = 0;
-
-    DPP_ETM_CGAVD_FLOW_DYNAMIC_TH_EN_T q_dyn_th_en = {0};
-    DPP_ETM_CGAVD_PP_WRED_GRP_TH_EN_T pp_dyn_th_en = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, PP_LEVEL);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), en, 0, 1);
-
-    q_dyn_th_en_reg_index = ETM_CGAVD_FLOW_DYNAMIC_TH_ENr;
-    pp_wrd_grp_th_en_reg_index = ETM_CGAVD_PP_WRED_GRP_TH_ENr;
-
-    if (QUEUE_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_Q_NUM - 1);
-
-        q_dyn_th_en.flow_dynamic_th_en = en;
-        rc  = dpp_reg_write(dev,
-                            q_dyn_th_en_reg_index,
-                            0,
-                            id,
-                            &q_dyn_th_en);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-    }
-
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_TM_PP_NUM - 1);
-
-        rc  = dpp_reg_read(dev,
-                           pp_wrd_grp_th_en_reg_index,
-                           0,
-                           id,
-                           &pp_dyn_th_en);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-        pp_dyn_th_en.pp_wred_grp_th_en = en;
-        rc  = dpp_reg_write(dev,
-                            pp_wrd_grp_th_en_reg_index,
-                            0,
-                            id,
-                            &pp_dyn_th_en);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 读取指定端口或队列是否支持动态门限机制
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   id   队列号或端口号
-* @param   p_en   读取的值，0-不支持动态门限机制，1-支持动态门限机制
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_dyn_th_en_get(DPP_DEV_T *dev,
-                                      DPP_TM_CGAVD_LEVEL_E level,
-                                      ZXIC_UINT32 id,
-                                      ZXIC_UINT32 *p_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 q_dyn_th_en_reg_index = 0;
-    ZXIC_UINT32 pp_wrd_grp_th_en_reg_index = 0;
-
-    DPP_ETM_CGAVD_FLOW_DYNAMIC_TH_EN_T q_dyn_th_en = {0};
-    DPP_ETM_CGAVD_PP_WRED_GRP_TH_EN_T pp_dyn_th_en = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, PP_LEVEL);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_en);
-
-    q_dyn_th_en_reg_index = ETM_CGAVD_FLOW_DYNAMIC_TH_ENr;
-    pp_wrd_grp_th_en_reg_index = ETM_CGAVD_PP_WRED_GRP_TH_ENr;
-
-    if (QUEUE_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_Q_NUM - 1);
-
-        rc  = dpp_reg_read(dev,
-                           q_dyn_th_en_reg_index,
-                           0,
-                           id,
-                           &q_dyn_th_en);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-        *p_en = q_dyn_th_en.flow_dynamic_th_en;
-
-    }
-
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_TM_PP_NUM - 1);
-
-        rc  = dpp_reg_read(dev,
-                           pp_wrd_grp_th_en_reg_index,
-                           0,
-                           id,
-                           &pp_dyn_th_en);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-        *p_en = pp_dyn_th_en.pp_wred_grp_th_en;
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/**  配置等价包长使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   使能标记，0-不使能，1-使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_equal_pkt_len_en_set(DPP_DEV_T *dev, ZXIC_UINT32 en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_EQUAL_PKT_LEN_EN_T equal_pkt_len_en = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), en, 0, 1);
-
-    equal_pkt_len_en.equal_pkt_len_en = en;
-    rc  = dpp_reg_write(dev,
-                        ETM_CGAVD_EQUAL_PKT_LEN_ENr,
-                        0,
-                        0,
-                        &equal_pkt_len_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**  读取等价包长使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_en   使能标记，0-不使能，1-使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_equal_pkt_len_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_EQUAL_PKT_LEN_EN_T equal_pkt_len_en = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_en);
-
-    *p_en = 0xffffffff;
-    rc  = dpp_reg_read(dev,
-                       ETM_CGAVD_EQUAL_PKT_LEN_ENr,
-                       0,
-                       0,
-                       &equal_pkt_len_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-    *p_en = equal_pkt_len_en.equal_pkt_len_en;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置等价包长
-* @param   dev_id
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_equal_pkt_len 等价包长
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_equal_pkt_len_para_set(DPP_DEV_T *dev,
-                                               DPP_ETM_EQUAL_PKT_LEN_PARA_T *p_equal_pkt_len)
-{
-    /* 返回值变量定义 */
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 i = 0;
-
-    /* 结构体变量定义 */
-    DPP_ETM_CGAVD_EQUAL_PKT_LEN0_T equal_pkt_len0 = {0};
-
-    /* 入参检查 */
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_equal_pkt_len);
-
-    for (i = 0; i < 8; i++)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), p_equal_pkt_len->equal_pkt_len[i], 0x0, 0x7fff);
-        equal_pkt_len0.equal_pkt_len0 = p_equal_pkt_len->equal_pkt_len[i];
-        rc = dpp_reg_write(dev,
-                           ETM_CGAVD_EQUAL_PKT_LEN0r + i,
-                           0,
-                           0,
-                           &equal_pkt_len0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    }
-
-    return DPP_OK;
-}
-
-
-
-/***********************************************************/
-/** 读取等价包长
-* @param   dev_id
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_equal_pkt_len 等价包长
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_equal_pkt_len_para_get(DPP_DEV_T *dev,
-                                               DPP_ETM_EQUAL_PKT_LEN_PARA_T *p_equal_pkt_len)
-{
-    /* 返回值变量定义 */
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 i = 0;
-
-    /* 结构体变量定义 */
-    DPP_ETM_CGAVD_EQUAL_PKT_LEN0_T equal_pkt_len0 = {0};
-
-    /* 入参检查 */
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_equal_pkt_len);
-
-    for (i = 0; i < 8; i++)
-    {
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_CGAVD_EQUAL_PKT_LEN0r, i);
-        rc = dpp_reg_read(dev,
-                          ETM_CGAVD_EQUAL_PKT_LEN0r + i,
-                          0,
-                          0,
-                          &equal_pkt_len0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-        p_equal_pkt_len->equal_pkt_len[i] = equal_pkt_len0.equal_pkt_len0;
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置等价包长阈值
-* @param   dev_id
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_equal_pkt_len_th 等价包长阈值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_equal_pkt_len_th_para_set(DPP_DEV_T *dev,
-                                                  DPP_ETM_EQUAL_PKT_LEN_TH_PARA_T *p_equal_pkt_len_th)
-{
-    /* 返回值变量定义 */
-    DPP_STATUS rc = 0;
-    ZXIC_UINT32 i = 0;
-
-    /* 结构体变量定义 */
-    DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH0_T equal_pkt_len_th0 = {0};
-
-    /* 入参检查 */
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_equal_pkt_len_th);
-
-    for (i = 0; i < 7; i++)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), p_equal_pkt_len_th->equal_pkt_len_th[i], 0x0, 0x7fff);
-
-        if (i <= 5 )
-        {
-            ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), p_equal_pkt_len_th->equal_pkt_len_th[i + 1], p_equal_pkt_len_th->equal_pkt_len_th[i], 0x7fff);
-        }
-
-        equal_pkt_len_th0.equal_pkt_len_th0 = p_equal_pkt_len_th->equal_pkt_len_th[i];
-        rc = dpp_reg_write(dev,
-                           ETM_CGAVD_EQUAL_PKT_LEN_TH0r + i,
-                           0,
-                           0,
-                           &equal_pkt_len_th0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-    }
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 读取等价包长阈值
-* @param   dev_id
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_equal_pkt_len_th 等价包长阈值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_equal_pkt_len_th_para_get(DPP_DEV_T *dev,
-                                                  DPP_ETM_EQUAL_PKT_LEN_TH_PARA_T *p_equal_pkt_len_th)
-{
-    /* 返回值变量定义 */
-    DPP_STATUS rc = 0;
-    ZXIC_UINT32 i = 0;
-
-    /* 结构体变量定义 */
-    DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH0_T equal_pkt_len_th0 = {0};
-
-    /* 入参检查 */
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_equal_pkt_len_th);
-
-    for (i = 0; i < 7; i++)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev),   i, ETM_CGAVD_EQUAL_PKT_LEN_TH0r);    
-        rc = dpp_reg_read(dev,
-                          ETM_CGAVD_EQUAL_PKT_LEN_TH0r + i,
-                          0,
-                          0,
-                          &equal_pkt_len_th0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-        p_equal_pkt_len_th->equal_pkt_len_th[i] = equal_pkt_len_th0.equal_pkt_len_th0;
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 动态门限放大因子参数配置
-* @param   dev_id
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_amplify_gene_para 动态门限放大因子参数
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_amplify_gene_para_set(DPP_DEV_T *dev,
-                                              DPP_ETM_AMPLIFY_GENE_PARA_T *p_amplify_gene_para)
-{
-    /* 返回值变量定义 */
-    DPP_STATUS rc = 0;
-    ZXIC_UINT32 i = 0;
-
-    /* 结构体变量定义 */
-    DPP_ETM_CGAVD_AMPLIFY_GENE0_T amplify_gene0 = {0};
-
-    /* 入参检查 */
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_amplify_gene_para);
-
-    for (i = 0; i < 16; i++)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), p_amplify_gene_para->amplify_gene[i], 0x0, 0xfff);
-        amplify_gene0.amplify_gene0 = p_amplify_gene_para->amplify_gene[i];
-        rc = dpp_reg_write(dev,
-                           ETM_CGAVD_AMPLIFY_GENE0r + i,
-                           0,
-                           0,
-                           &amplify_gene0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 动态门限放大因子参数获取
-* @param   dev_id
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_amplify_gene_para 动态门限放大因子参数
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/28
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_amplify_gene_para_get(DPP_DEV_T *dev,
-                                              DPP_ETM_AMPLIFY_GENE_PARA_T *p_amplify_gene_para)
-{
-    /* 返回值变量定义 */
-    DPP_STATUS rc = 0;
-    ZXIC_UINT32 i = 0;
-
-    /* 结构体变量定义 */
-    DPP_ETM_CGAVD_AMPLIFY_GENE0_T amplify_gene0 = {0};
-
-    /* 入参检查 */
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_amplify_gene_para);
-
-    for (i = 0; i < 16; i++)
-    {
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_CGAVD_AMPLIFY_GENE0r, i);
-        rc = dpp_reg_read(dev,
-                          ETM_CGAVD_AMPLIFY_GENE0r + i,
-                          0,
-                          0,
-                          &amplify_gene0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-        p_amplify_gene_para->amplify_gene[i] = amplify_gene0.amplify_gene0;
-    }
-
-    return DPP_OK;
-}
-
-#if 0
-/***********************************************************/
-/**  配置默认队列使能
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   配置的值，0-不使能默认队列，1-使能默认队列，
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush     @date  2016/08/16
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_default_queue_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_DEFAULT_QUEUE_EN_T default_que_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1);
-
-    default_que_en.default_queue_en = en;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_DEFAULT_QUEUE_ENr,
-                        0,
-                        0,
-                        &default_que_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**  读取默认队列使能
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_en   读取的值，0-不使能默认队列，1-使能默认队列，
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush     @date  2016/08/16
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_default_queue_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_DEFAULT_QUEUE_EN_T default_que_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CGAVD_DEFAULT_QUEUE_ENr,
-                       0,
-                       0,
-                       &default_que_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_en = default_que_en.default_queue_en;
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**  配置默认队列起始末尾
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   def_start_que  起始默认队列block/byte单位
-* @param   def_finish_que  结束默认队列block/byte单位
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush     @date  2016/08/16
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_default_queue_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 def_start_queue, ZXIC_UINT32 def_finish_queue)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_DEFAULT_START_QUEUE_T def_start_que = {0};
-    DPP_ETM_CGAVD_DEFAULT_FINISH_QUEUE_T def_finish_que = {0};
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, def_start_queue, 0, 0x1fffffff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, def_finish_queue, 0, 0x1fffffff);
-
-    def_start_que.default_start_queue = def_start_queue;
-    def_finish_que.default_finish_queue = def_finish_queue;
-
-
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_DEFAULT_START_QUEUEr,
-                        0,
-                        0,
-                        &def_start_que);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_DEFAULT_FINISH_QUEUEr,
-                        0,
-                        0,
-                        &def_finish_que);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**  读取默认队列起始末尾值
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_def_start_que   默认队列起始值block/byte单位
-* @param   p_def_finish_que   默认队列结束值block/byte单位
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2016/08/16
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_default_queue_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_def_start_queue, ZXIC_UINT32 *p_def_finish_queue)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_DEFAULT_START_QUEUE_T def_start_que = {0};
-    DPP_ETM_CGAVD_DEFAULT_FINISH_QUEUE_T def_finish_que = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_def_finish_queue);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_def_start_queue);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CGAVD_DEFAULT_START_QUEUEr,
-                       0,
-                       0,
-                       &def_start_que);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CGAVD_DEFAULT_FINISH_QUEUEr,
-                       0,
-                       0,
-                       &def_finish_que);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_def_start_queue = def_start_que.default_start_queue;
-    *p_def_finish_queue = def_finish_que.default_finish_queue;
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**  配置协议队列使能
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   配置的值，0-不使能默认队列，1-使能默认队列，
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2016/08/16
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_protocol_queue_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_PROTOCOL_QUEUE_EN_T protocol_que_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1);
-
-    protocol_que_en.protocol_queue_en = en;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_PROTOCOL_QUEUE_ENr,
-                        0,
-                        0,
-                        &protocol_que_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**  读取协议队列使能
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_en   读取的值，0-不使能通用门限，1-使能通用门限，
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2016/08/16
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_protocol_queue_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_PROTOCOL_QUEUE_EN_T protocol_que_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CGAVD_PROTOCOL_QUEUE_ENr,
-                       0,
-                       0,
-                       &protocol_que_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_en = protocol_que_en.protocol_queue_en;
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**  配置协议队列起始末尾
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   protocol_start_que  起始协议队列block/byte单位
-*@param   protocol_-finish_que 末尾协议队列block/byte单位
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2016/08/16
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_protocol_queue_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 protocol_start_que, ZXIC_UINT32 protocol_finish_que)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_PROTOCOL_START_QUEUE_T pro_start_que = {0};
-    DPP_ETM_CGAVD_PROTOCOL_FINISH_QUEUE_T pro_finish_que = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, protocol_start_que, 0, 0x1fffffff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, protocol_finish_que, 0, 0x1fffffff);
-
-    pro_start_que.protocol_start_queue = protocol_start_que;
-    pro_finish_que.protocol_finish_queue = protocol_finish_que;
-
-
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_PROTOCOL_START_QUEUEr,
-                        0,
-                        0,
-                        &pro_start_que);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_PROTOCOL_FINISH_QUEUEr,
-                        0,
-                        0,
-                        &pro_finish_que);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**  读取协议队列起始末尾值
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_protocol_start_que   协议认队列起始值block/byte单位
-* @param   p_protocol_finish_que   协议认队列末尾值block/byte单位
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush     @date  2016/08/16
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_protocol_queue_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_protocol_start_que, ZXIC_UINT32 *p_protocol_finish_que)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_PROTOCOL_START_QUEUE_T pro_start_que = {0};
-    DPP_ETM_CGAVD_PROTOCOL_FINISH_QUEUE_T pro_finish_que = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_protocol_finish_que);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_protocol_start_que);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CGAVD_PROTOCOL_START_QUEUEr,
-                       0,
-                       0,
-                       &pro_start_que);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CGAVD_PROTOCOL_FINISH_QUEUEr,
-                       0,
-                       0,
-                       &pro_finish_que);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_protocol_start_que = pro_start_que.protocol_start_queue;
-    *p_protocol_finish_que = pro_finish_que.protocol_finish_queue;
-
-    return DPP_OK;
-}
-
-#endif
-/***********************************************************/
-/**  配置通用门限使能
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   配置的值，0-不使能通用门限，1-使能通用门限，
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_uniform_th_en_set(DPP_DEV_T *dev, ZXIC_UINT32 en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_UNIFORM_TD_TH_EN_T uniform_en = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), en, 0, 1);
-
-    uniform_en.uniform_td_th_en = en;
-    rc  = dpp_reg_write(dev,
-                        ETM_CGAVD_UNIFORM_TD_TH_ENr,
-                        0,
-                        0,
-                        &uniform_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**  读取通用门限使能
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_en   读取的值，0-不使能通用门限，1-使能通用门限，
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_uniform_th_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_UNIFORM_TD_TH_EN_T uniform_en = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_en);
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CGAVD_UNIFORM_TD_TH_ENr,
-                       0,
-                       0,
-                       &uniform_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_en = uniform_en.uniform_td_th_en;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**  配置通用门限
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   byte_block_uni_th   通用门限值block/byte单位
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/08/01
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_uniform_byte_block_th_set(DPP_DEV_T *dev, ZXIC_UINT32 byte_block_uni_th)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_UNIFORM_TD_TH_T uniform_block_th = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), byte_block_uni_th, 0, 0x1fffffff);
-
-    uniform_block_th.uniform_td_th = byte_block_uni_th;
-    rc  = dpp_reg_write(dev,
-                        ETM_CGAVD_UNIFORM_TD_THr,
-                        0,
-                        0,
-                        &uniform_block_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**  配置通用门限
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   th   通用门限值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_uniform_th_set(DPP_DEV_T *dev, ZXIC_UINT32 uni_th)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 blk_size = 0;
-    ZXIC_UINT32 blk_th = 0;
-    ZXIC_UINT32 cgavd_cfg_mode = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW(DEV_ID(dev), uni_th, DPP_TM_CGAVD_KILO_UL);
-    if ((uni_th * DPP_TM_CGAVD_KILO_UL) > 0x1fffffff)
-    {
-        uni_th = 0x1fffffff;
-    }
-    else
-    {
-        uni_th = (uni_th * DPP_TM_CGAVD_KILO_UL);
-    }
-
-    rc = dpp_tm_cgavd_cfg_mode_get(dev, &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_cfg_mode_get");
-
-    if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE)
-    {
-        rc  = dpp_tm_cfgmt_blk_size_get(dev, &blk_size);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cfgmt_blk_size_get");
-
-        if (blk_size != 0)
-        {
-            blk_th = (uni_th / blk_size);
-            blk_th = (uni_th % blk_size == 0) ? (blk_th ) : ((blk_th) + 1);
-        }
-
-        rc = dpp_tm_cgavd_uniform_byte_block_th_set(dev, blk_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_uniform_byte_block_th_set");
-    }
-    else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE)
-    {
-        rc = dpp_tm_cgavd_uniform_byte_block_th_set(dev, uni_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_uniform_byte_block_th_set");
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_cgavd_uniform_th_set err!!\n");
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**  读取通用门限
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_byte_block_uni_th   通用门限值block/byte单位
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/08/01
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_uniform_byte_block_th_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_byte_block_uni_th)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_UNIFORM_TD_TH_T uniform_block_th = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_byte_block_uni_th);
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CGAVD_UNIFORM_TD_THr,
-                       0,
-                       0,
-                       &uniform_block_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_byte_block_uni_th = uniform_block_th.uniform_td_th;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**  读取通用门限
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_uni_th   通用门限值kbyte单位
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/08/01
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_uniform_th_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_uni_th)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 blk_size = 0;
-    ZXIC_UINT32 cgavd_cfg_mode = 0;
-    ZXIC_UINT32 block_byte_th = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_uni_th);
-    
-
-    rc = dpp_tm_cgavd_uniform_byte_block_th_get(dev, &block_byte_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_uniform_byte_block_th_get");
-
-    rc = dpp_tm_cgavd_cfg_mode_get(dev, &cgavd_cfg_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_cfg_mode_get");
-
-    if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE)
-    {
-        rc  = dpp_tm_cfgmt_blk_size_get(dev, &blk_size);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cfgmt_blk_size_get");
-
-        *p_uni_th = (block_byte_th * blk_size) / DPP_TM_CGAVD_KILO_UL;
-
-    }
-    else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE)
-    {
-        *p_uni_th = (block_byte_th / DPP_TM_CGAVD_KILO_UL);
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_cgavd_uniform_th_get err!!\n");
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**  配置流队列所属优先级
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   q_id   队列号
-* @param   pri   配置的优先级，0~4
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_q_pri_set(DPP_DEV_T *dev,
-                                  ZXIC_UINT32 q_id,
-                                  ZXIC_UINT32 pri)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_Q_PRI_T q_pri = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pri, 0, 4);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_id, 0, DPP_ETM_Q_NUM - 1);
-
-    q_pri.qpri_flow_cfg_din = pri;
-    rc  = dpp_reg_write(dev,
-                        ETM_CGAVD_Q_PRIr,
-                        0,
-                        q_id,
-                        &q_pri);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置TM模式下流队列挂接的端口号；SA模式下流队列映射的目的芯片ID
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   q_id   队列号
-* @param   pp_id   配置的端口号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_q_map_pp_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 q_id,
-                                     ZXIC_UINT32 pp_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_PP_NUM_T pp_num = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_id, 0, DPP_ETM_Q_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pp_id, 0, DPP_TM_PP_NUM - 1);
-
-    pp_num.pp_num = pp_id;
-    rc  = dpp_reg_write(dev,
-                        ETM_CGAVD_PP_NUMr,
-                        0,
-                        q_id,
-                        &pp_num);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取TM模式下流队列挂接的端口号；SA模式下流队列映射的目的芯片ID
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   q_id   队列号
-* @param   p_pp_id   读取的端口号
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/18
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_q_map_pp_get(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 q_id,
-                                     ZXIC_UINT32 *p_pp_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_PP_NUM_T pp_num = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_pp_id);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_id, 0, DPP_ETM_Q_NUM - 1);
-
-    *p_pp_id = 0xffffffff;
-    rc  = dpp_reg_read(dev,
-                       ETM_CGAVD_PP_NUMr,
-                       0,
-                       q_id,
-                       &pp_num);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_pp_id = pp_num.pp_num;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置TM模式tc到flow的映射
-* @param   dev_id 设备编号
-* @param   tc_id   itmd tc优先级（0~7）
-* @param   flow_id 映射的flowid号 （0~4095）
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/07/04
-************************************************************/
-DPP_STATUS dpp_tm_tc_map_flow_set(DPP_DEV_T *dev,
-                                  ZXIC_UINT32 tc_id,
-                                  ZXIC_UINT32 flow_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_CFG_TC_FLOWID_DAT_T cfg_tc_flow = {0}; 
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), tc_id, 0, DPP_TM_TC_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0, DPP_ETM_Q_NUM - 1);
-
-    cfg_tc_flow.cfg_tc_flowid_dat = flow_id;
-    rc  = dpp_reg_write(dev,
-                        ETM_CGAVD_CFG_TC_FLOWID_DATr,
-                        0,
-                        tc_id,
-                        &cfg_tc_flow);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取配置TM模式tc到flow的映射
-* @param   dev_id 设备编号
-* @param   tc_id   itmd tc优先级（0~7）
-* @param   flow_id 读取映射的flowid号 （0~4095）
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/07/04
-************************************************************/
-DPP_STATUS dpp_tm_tc_map_flow_get(DPP_DEV_T *dev,
-                                  ZXIC_UINT32 tc_id,
-                                  ZXIC_UINT32 *flow_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_CFG_TC_FLOWID_DAT_T cfg_tc_flow = {0}; 
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), flow_id);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), tc_id, 0, DPP_TM_TC_NUM - 1);
-
-    *flow_id = 0xffffffff;
-    rc  = dpp_reg_read(dev,
-                       ETM_CGAVD_CFG_TC_FLOWID_DATr,
-                       0,
-                       tc_id,
-                       &cfg_tc_flow);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *flow_id = cfg_tc_flow.cfg_tc_flowid_dat;
-
-    return DPP_OK;
-}
-
-#if 0
-/***********************************************************/
-/** 系统级缓存使用上下限阈值配置
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   th_h: 系统级缓存使用上限阈值
-* @param   th_l: 系统级缓存使用下限阈值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/03
-************************************************************/
-DPP_STATUS dpp_tm_sys_window_th_set(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 th_h,
-                                    ZXIC_UINT32 th_l)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_ETM_CGAVD_SYS_WINDOW_TH_H_T sys_window_th_h = {0};
-    DPP_ETM_CGAVD_SYS_WINDOW_TH_L_T sys_window_th_l = {0};
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, th_h, 0, 0x1fffffff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, th_l, 0, 0x1fffffff);
-
-    if (th_l > th_h)
-    {
-        ZXIC_COMM_PRINT("input error th_l > th_h");
-        return DPP_ERR;
-    }
-
-    sys_window_th_h.sys_window_th_h = th_h;
-    sys_window_th_l.sys_window_th_l = th_l;
-
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_SYS_WINDOW_TH_Hr,
-                        0,
-                        0,
-                        &sys_window_th_h);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_SYS_WINDOW_TH_Lr,
-                        0,
-                        0,
-                        &sys_window_th_l);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-#endif
-/***********************************************************/
-/** 配置QMU查询队列Qos开关
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   q_id:  队列号
-* @param   qos_sign: qos开关 0:关闭  1:开启
-* @param
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/03
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qos_sign_set(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 q_id,
-                                   ZXIC_UINT32 qos_sign)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_ETM_CGAVD_QOS_SIGN_T qmu_qos_sign = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), qos_sign, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_id, 0, DPP_ETM_Q_NUM - 1);
-
-    qmu_qos_sign.qos_sign_flow_cfg_din = qos_sign;
-
-    rc  = dpp_reg_write(dev,
-                        ETM_CGAVD_QOS_SIGNr,
-                        0,
-                        q_id,
-                        &qmu_qos_sign);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-#if 0
-/***********************************************************/
-/** 配置cgavd强制反压
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   cgavd_fc: 0:不强制反压    1:强制反压
-* @param
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/07/03
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_cfg_fc_set(ZXIC_UINT32 dev_id,
-                                   ZXIC_UINT32 cgavd_fc)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_CGAVD_CFG_FC_T cgavd_cfg_fc_t = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, cgavd_fc, 0, 1);
-
-    cgavd_cfg_fc_t.cgavd_cfg_fc = cgavd_fc;
-
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_CGAVD_CFG_FCr,
-                        0,
-                        0,
-                        &cgavd_cfg_fc_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 获取cgavd强制反压状态
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   cgavd_fc: 0:不强制反压    1:强制反压
-* @param
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/07/03
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_cfg_fc_get(ZXIC_UINT32 dev_id,
-                                   ZXIC_UINT32 *cgavd_fc)
-
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_CGAVD_CFG_FC_T cgavd_cfg_fc_t = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, cgavd_fc);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CGAVD_CGAVD_CFG_FCr,
-                       0,
-                       0,
-                       &cgavd_cfg_fc_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    *cgavd_fc = cgavd_cfg_fc_t.cgavd_cfg_fc;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置cgavd强制不反压
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   cgavd_no_fc: 0:不强制     1:强制不反压
-* @param
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/07/03
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_cfg_no_fc_set(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 cgavd_no_fc)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_CGAVD_CFG_NO_FC_T cgavd_cfg_no_fc_t = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, cgavd_no_fc, 0, 1);
-
-    cgavd_cfg_no_fc_t.cgavd_cfg_no_fc = cgavd_no_fc;
-
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_CGAVD_CFG_NO_FCr,
-                        0,
-                        0,
-                        &cgavd_cfg_no_fc_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 获取cgavd强制不反压状态
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   cgavd_no_fc: 0:不强制 1:强制不反压
-* @param
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/07/03
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_cfg_no_fc_get(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 *cgavd_no_fc)
-
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_CGAVD_CFG_NO_FC_T cgavd_cfg_no_fc_t = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, cgavd_no_fc);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CGAVD_CGAVD_CFG_NO_FCr,
-                       0,
-                       0,
-                       &cgavd_cfg_no_fc_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    *cgavd_no_fc = cgavd_cfg_no_fc_t.cgavd_cfg_no_fc;
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置cgavd平均队列深度归零
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en: 0:关闭     1:使能
-* @param
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/08/05
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_avg_qlen_return_zero_en_set(ZXIC_UINT32 dev_id,
-                                                ZXIC_UINT32 en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_AVG_QLEN_RETURN_ZERO_EN_T return_zero_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1);
-
-    return_zero_en.avg_qlen_return_zero_en = en;
-
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_AVG_QLEN_RETURN_ZERO_ENr,
-                        0,
-                        0,
-                        &return_zero_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-#endif
-#endif
-
-
-#if ZXIC_REAL("TM_QMU")
-#if 0
-/***********************************************************/
-/** QMU MMU 配置清除
-* @param   dev_id
-* @param   tm_type
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2020/04/13
-************************************************************/
-DPP_STATUS dpp_tm_qmu_mmu_cfg_clr(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_CFGMT_DDR_ATTACH_T attach = {0};
-
-    ZXIC_UINT32 bdep[64] = {0};
-    ZXIC_UINT32 bhead[64] = {0};
-    ZXIC_UINT32 btail[64] = {0};
-    ZXIC_UINT32 ddr_in_mmu[8] = {0};
-    ZXIC_UINT32 ddr_in_qmu[10] = {0};
-    ZXIC_UINT32 bank_to_mmu[64] = {0};
-    ZXIC_UINT32 bank_to_qmu[80] = {0};
-    ZXIC_UINT32 active[16] = {0};
-    ZXIC_UINT32 random_grp[64] = {0};
-    ZXIC_UINT32 random_ddr0[64] = {0};
-    ZXIC_UINT32 random_ddr1[64] = {0};
-    ZXIC_UINT32 random_ddr2[64] = {0};
-    ZXIC_UINT32 random_ddr3[64] = {0};
-    ZXIC_UINT32 random_ddr4[64] = {0};
-    ZXIC_UINT32 random_ddr5[64] = {0};
-    ZXIC_UINT32 random_ddr6[64] = {0};
-    ZXIC_UINT32 random_ddr7[64] = {0};
-    //ZXIC_UINT32 mmu_addr[128] = {0};
-
-    ZXIC_UINT32 i = 0;
-
-    ZXIC_UINT32 reg_attach = 0;
-    ZXIC_UINT32 reg_ddr_in_mmu = 0;
-    ZXIC_UINT32 reg_ddr_in_qmu = 0;
-    ZXIC_UINT32 reg_bank_to_mmu = 0;
-    ZXIC_UINT32 reg_bank_to_qmu = 0;
-    ZXIC_UINT32 reg_bdep = 0;
-    ZXIC_UINT32 reg_bhead = 0;
-    ZXIC_UINT32 reg_btail = 0;
-    ZXIC_UINT32 reg_active = 0;
-    ZXIC_UINT32 reg_random_grp = 0;
-    ZXIC_UINT32 reg_random_ddr0 = 0;
-    ZXIC_UINT32 reg_random_ddr1 = 0;
-    ZXIC_UINT32 reg_random_ddr2 = 0;
-    ZXIC_UINT32 reg_random_ddr3 = 0;
-    ZXIC_UINT32 reg_random_ddr4 = 0;
-    ZXIC_UINT32 reg_random_ddr5 = 0;
-    ZXIC_UINT32 reg_random_ddr6 = 0;
-    ZXIC_UINT32 reg_random_ddr7 = 0;
-    //ZXIC_UINT32 reg_mmu_addr = 0;
-
-    reg_attach = ETM_CFGMT_CFGMT_DDR_ATTACHr;
-    reg_ddr_in_mmu = ETM_QMU_CFGMT_DDR_IN_MMU_CFGr;
-    reg_ddr_in_qmu = ETM_QMU_CFGMT_DDR_IN_QMU_CFGr;
-    reg_bank_to_mmu = ETM_QMU_CFGMT_BANK_TO_MMU_CFGr;
-    reg_bank_to_qmu = ETM_QMU_CFGMT_BANK_TO_QMU_CFGr;
-    reg_bdep = ETM_QMU_QCFG_QLIST_BDEPr;
-    reg_bhead = ETM_QMU_QCFG_QLIST_BHEADr;
-    reg_btail = ETM_QMU_QCFG_QLIST_BTAILr;
-    reg_active = ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr;
-    reg_random_grp = ETM_QMU_QCFG_QLIST_GRPr;
-    reg_random_ddr0 = ETM_QMU_QCFG_QLIST_GRP0_BANKr;
-    reg_random_ddr1 = ETM_QMU_QCFG_QLIST_GRP1_BANKr;
-    reg_random_ddr2 = ETM_QMU_QCFG_QLIST_GRP2_BANKr;
-    reg_random_ddr3 = ETM_QMU_QCFG_QLIST_GRP3_BANKr;
-    reg_random_ddr4 = ETM_QMU_QCFG_QLIST_GRP4_BANKr;
-    reg_random_ddr5 = ETM_QMU_QCFG_QLIST_GRP5_BANKr;
-    reg_random_ddr6 = ETM_QMU_QCFG_QLIST_GRP6_BANKr;
-    reg_random_ddr7 = ETM_QMU_QCFG_QLIST_GRP7_BANKr;
-
-    rc  = dpp_reg_write(dev_id, reg_attach, 0, 0, &attach);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    for (i = 0; i < 8; i++)
-    {
-        rc  = dpp_reg_write32_bymn(dev_id, reg_ddr_in_mmu, 0, i, ddr_in_mmu[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-    }
-
-    for (i = 0; i < 10; i++)
-    {
-        rc  = dpp_reg_write32_bymn(dev_id, reg_ddr_in_qmu, 0, i, ddr_in_qmu[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-    }
-
-    for (i = 0; i < 64; i++)
-    {
-        rc  = dpp_reg_write32_bymn(dev_id, reg_bank_to_mmu, 0, i, bank_to_mmu[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-    }
-
-    for (i = 0; i < 80; i++)
-    {
-        rc  = dpp_reg_write32_bymn(dev_id, reg_bank_to_qmu, 0, i, bank_to_qmu[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-    }
-
-    for (i = 0; i < 64; i++)
-    {
-        rc  = dpp_reg_write32_bymn(dev_id, reg_bhead, 0, i, bhead[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-
-        rc  = dpp_reg_write32_bymn(dev_id, reg_btail, 0, i, btail[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-
-        rc  = dpp_reg_write32_bymn(dev_id, reg_bdep, 0, i, bdep[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-    }
-
-    for (i = 0; i < 16; i++)
-    {
-        rc  = dpp_reg_write32_bymn(dev_id, reg_active, 0, i, active[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-    }
-
-    for (i = 0; i < 64; i++)
-    {
-        rc  = dpp_reg_write32_bymn(dev_id, reg_random_grp, 0, i, random_grp[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-
-        rc  = dpp_reg_write32_bymn(dev_id, reg_random_ddr0, 0, i, random_ddr0[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-
-        rc  = dpp_reg_write32_bymn(dev_id, reg_random_ddr1, 0, i, random_ddr1[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-
-        rc  = dpp_reg_write32_bymn(dev_id, reg_random_ddr2, 0, i, random_ddr2[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-
-        rc  = dpp_reg_write32_bymn(dev_id, reg_random_ddr3, 0, i, random_ddr3[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-
-        rc  = dpp_reg_write32_bymn(dev_id, reg_random_ddr4, 0, i, random_ddr4[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-
-        rc  = dpp_reg_write32_bymn(dev_id, reg_random_ddr5, 0, i, random_ddr5[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-
-        rc  = dpp_reg_write32_bymn(dev_id, reg_random_ddr6, 0, i, random_ddr6[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-
-        rc  = dpp_reg_write32_bymn(dev_id, reg_random_ddr7, 0, i, random_ddr7[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-    }
-
-    /*for (i = 0; i < 128; i++)
-    {
-        rc  = dpp_reg_write32_bymn(dev_id, reg_mmu_addr + i, 0, 0, mmu_addr[i]);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write32_bymn");
-    }*/
-
-    return rc;
-}
-
-/***********************************************************/
-/** 配置QMU队列授权价值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   credit_value   授权价值，默认值是533Byte
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_credit_value_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 credit_value)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_QSCH_CREDIT_VALUE_T credit_val = {0};
-
-    credit_val.qcfg_qsch_credit_value = credit_value;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_QMU_QCFG_QSCH_CREDIT_VALUEr,
-                        0,
-                        0,
-                        &credit_val);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-#endif
-/***********************************************************/
-/** 读取QMU队列授权价值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_credit_value   授权价值，默认值是533Byte
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy     @date  2016/04/14
-************************************************************/
-DPP_STATUS dpp_tm_qmu_credit_value_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_credit_value)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_QSCH_CREDIT_VALUE_T credit_val = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_credit_value);
-
-    *p_credit_value = 0;
-
-    rc  = dpp_reg_read(dev,
-                       ETM_QMU_QCFG_QSCH_CREDIT_VALUEr,
-                       0,
-                       0,
-                       &credit_val);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_credit_value = credit_val.qcfg_qsch_credit_value;
-
-    return DPP_OK;
-}
-
-#if 0
-/***********************************************************/
-/** 配置授权盈余初始化值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   crbal_initial_value   授权盈余初始化值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crbal_initial_value_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crbal_initial_value)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_QSCH_CRBAL_INIT_VALUE_T crbal_init_val = {0};
-
-    crbal_init_val.qcfg_qsch_crbal_init_value = crbal_initial_value;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_QMU_QCFG_QSCH_CRBAL_INIT_VALUEr,
-                        0,
-                        0,
-                        &crbal_init_val);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-
-/***********************************************************/
-/** 配置CRS过滤使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   配置的值，0-不使能过滤，1-使能过滤
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_filter_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_QSCH_CRS_FILTER_T crs_filter_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1);
-
-    crs_filter_en.qcfg_qsch_crs_filter = en;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_QMU_QCFG_QSCH_CRS_FILTERr,
-                        0,
-                        0,
-                        &crs_filter_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置CRS发送强制使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   配置的值，0-不使能，1-使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_force_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_QSCH_CRS_FORCE_EN_T crs_force_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1);
-
-    crs_force_en.qcfg_qsch_crs_force_en = en;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_QMU_QCFG_QSCH_CRS_FORCE_ENr,
-                        0,
-                        0,
-                        &crs_force_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置CRS发送强制的队列
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   q_id   队列号
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_force_q_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 q_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_QSCH_CRS_FORCE_QNUM_T crs_force_q = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, q_id, 0, DPP_ETM_Q_NUM - 1);
-
-    crs_force_q.qcfg_qsch_crs_force_qnum = q_id;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_QMU_QCFG_QSCH_CRS_FORCE_QNUMr,
-                        0,
-                        0,
-                        &crs_force_q);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-
-/***********************************************************/
-/** 配置CRS发送强置的状态
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   crs_state   CRS发送强置的状态
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/18
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_force_state_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crs_state)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_QSCH_CRS_FORCE_CRS_T crs_force_crs = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, crs_state, 0, 1);
-
-    crs_force_crs.qcfg_qsch_crs_force_crs = crs_state;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_QCFG_QSCH_CRS_FORCE_CRSr,
-                       0,
-                       0,
-                       &crs_force_crs);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置特定队列发送特定CRS
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   队列号
-*               qcfg_qsch_crs_force_crs:CRS状态(0：off；1：normal。)
-                 qcfg_qsch_crs_force_en:CRS发送强置使能(0：不使能；1：使能。)
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qnum_crs_force(ZXIC_UINT32 dev_id,
-                                     ZXIC_UINT32 qnum,
-                                     ZXIC_UINT32 qcfg_qsch_crs_force_crs,
-                                     ZXIC_UINT32 qcfg_qsch_crs_force_en)
-
-{
-    DPP_STATUS  rc = DPP_OK;
-    
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qnum, 0, DPP_ETM_Q_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qcfg_qsch_crs_force_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qcfg_qsch_crs_force_crs, 0,  1);
-
-
-    rc = dpp_tm_qmu_crs_force_q_set(dev_id, qnum);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_crs_force_q_set");
-
-    rc = dpp_tm_qmu_crs_force_state_set(dev_id, qcfg_qsch_crs_force_crs);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_crs_force_state_set");
-
-    rc = dpp_tm_qmu_crs_force_en_set(dev_id, qcfg_qsch_crs_force_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_crs_force_en_set");
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 配置QMU空闲链表:TM独享模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   ddr_num   ddr组数，1-8组
-* @param   bank_vld   bank有效信号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/06/07
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qlist_set(ZXIC_UINT32 dev_id,
-                                ZXIC_UINT32 ddr_num,
-                                ZXIC_UINT32 bank_num_para,
-                                ZXIC_UINT32 bank_vld,
-                                ZXIC_UINT32 gene_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 reg_index = 0;
-    ZXIC_UINT32 bdep_reg_index = 0;
-    ZXIC_UINT32 bhead_reg_index = 0;
-    ZXIC_UINT32 btail_reg_index = 0;
-    ZXIC_UINT32 qmu_cfgmt_ddr_in_mmu_index = 0;
-    ZXIC_UINT32 qmu_cfgmt_ddr_in_qmu_index = 0;
-    ZXIC_UINT32 qmu_cfgmt_bank_to_mmu_index = 0;
-    ZXIC_UINT32 qmu_cfgmt_bank_to_qmu_index = 0;
-    ZXIC_UINT32 qmu_cfgmt_active_to_bank_index = 0;
-    ZXIC_UINT32 qmu_qcfg_qlist_grp0_bank_index = 0;
-    ZXIC_UINT32 qmu_qcfg_qlist_grp1_bank_index = 0;
-    ZXIC_UINT32 qlist_grp0_bank_data[8] = {1, 2, 3, 4, 5, 6, 7, 0};
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP1_BANK_T qlist_grp1_bank = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ddr_num, 1, 8);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, bank_num_para, 1, 8);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, bank_vld, 0, 1);
-
-    bdep_reg_index = ETM_QMU_QCFG_QLIST_BDEPr;
-    bhead_reg_index = ETM_QMU_QCFG_QLIST_BHEADr;
-    btail_reg_index = ETM_QMU_QCFG_QLIST_BTAILr;
-    qmu_cfgmt_ddr_in_mmu_index = ETM_QMU_CFGMT_DDR_IN_MMU_CFGr;
-    qmu_cfgmt_ddr_in_qmu_index = ETM_QMU_CFGMT_DDR_IN_QMU_CFGr;
-    qmu_cfgmt_bank_to_mmu_index = ETM_QMU_CFGMT_BANK_TO_MMU_CFGr;
-    qmu_cfgmt_bank_to_qmu_index = ETM_QMU_CFGMT_BANK_TO_QMU_CFGr;
-    qmu_cfgmt_active_to_bank_index = ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr;
-    qmu_qcfg_qlist_grp0_bank_index = ETM_QMU_QCFG_QLIST_GRP0_BANKr;
-    qmu_qcfg_qlist_grp1_bank_index = ETM_QMU_QCFG_QLIST_GRP1_BANKr;
-
-    /* cfgmt配置ddr_num组ddr */
-    rc = dpp_tm_cfgmt_ddr_attach_set(dev_id, ddr_num);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_ddr_attach_set");
-
-    /* ddr组映射:     qmu <--> mmu: ddr0~1 映射 0~1 */
-    for (i = 0; i < ddr_num; i++)
-    {
-        /* qmu --> mmu */
-        ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = i;
-        rc  = dpp_reg_write(dev_id,
-                            qmu_cfgmt_ddr_in_mmu_index,
-                            0,
-                            i,
-                            &ddr_in_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        /* mmu --> qmu */
-        ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i;
-        rc  = dpp_reg_write(dev_id,
-                            qmu_cfgmt_ddr_in_qmu_index,
-                            0,
-                            i,
-                            &ddr_in_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-
-    /* qmu链表首尾指针及bank深度配置 */
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_tm_qmu_qlist_set starting++++++\n");
-
-    for (i = 0; i < ddr_num; i++)
-    {
-        for (j = 0; j < bank_num_para; j++)
-        {
-            reg_index = (i * 8 + j);
-
-            ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ reg_index=%d ++++++\n", reg_index);
-
-            qlist_bdep.qcfg_qlist_bdep = gene_para;
-            ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ qlist_bdep.qcfg_qlist_bdep=0x%x ++++++\n", qlist_bdep.qcfg_qlist_bdep);
-            rc  = dpp_reg_write(dev_id,
-                                bdep_reg_index,
-                                0,
-                                reg_index,
-                                &qlist_bdep);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            qlist_bhead.bank_vld = bank_vld;
-            qlist_bhead.qcfg_qlist_bhead = (gene_para * (i * bank_num_para + j));
-            ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ qlist_bhead.bank_vld=0x%x ++++++\n", qlist_bhead.bank_vld);
-            ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ qlist_bhead.qcfg_qlist_bhead=0x%x ++++++\n", qlist_bhead.qcfg_qlist_bhead);
-            rc  = dpp_reg_write(dev_id,
-                                bhead_reg_index,
-                                0,
-                                reg_index,
-                                &qlist_bhead);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id,  gene_para , ((i * bank_num_para + j) + 1) );
-            ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id,  (gene_para * ((i * bank_num_para + j) + 1)) , 1 );
-            qlist_btail.qcfg_qlist_btail = ((gene_para * ((i * bank_num_para + j) + 1)) - 1);
-            ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ qlist_btail.qcfg_qlist_btail=0x%x ++++++\n", qlist_btail.qcfg_qlist_btail);
-            rc  = dpp_reg_write(dev_id,
-                                btail_reg_index,
-                                0,
-                                reg_index,
-                                &qlist_btail);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-
-        ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ j=%d ++++++\n", j);
-
-        if (j != 8 )
-        {
-            for (k = bank_num_para; k < 8; k++)
-            {
-                reg_index = (i * 8 + k);
-                ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ reg_index=%d ++++++\n", reg_index);
-                qlist_bhead.bank_vld = 0;
-                qlist_bhead.qcfg_qlist_bhead = 0;
-                ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ qlist_bhead.bank_vld=0x%x ++++++\n", qlist_bhead.bank_vld);
-                ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ qlist_bhead.qcfg_qlist_bhead=0x%x ++++++\n", qlist_bhead.qcfg_qlist_bhead);
-                rc  = dpp_reg_write(dev_id,
-                                    bhead_reg_index,
-                                    0,
-                                    reg_index,
-                                    &qlist_bhead);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-            }
-        }
-    }
-
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ i=%d ++++++\n", i);
-
-    if (i != 8 )
-    {
-        for (k = ddr_num; k < 8; k++)
-        {
-            for (j = 0; j < 8; j++)
-            {
-                reg_index = (k * 8 + j);
-                ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ reg_index=%d ++++++\n", reg_index);
-                qlist_bhead.bank_vld = 0;
-                qlist_bhead.qcfg_qlist_bhead = 0;
-                ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ qlist_bhead.bank_vld=0x%x ++++++\n", qlist_bhead.bank_vld);
-                ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++ qlist_bhead.qcfg_qlist_bhead=0x%x ++++++\n", qlist_bhead.qcfg_qlist_bhead);
-                rc  = dpp_reg_write(dev_id,
-                                    bhead_reg_index,
-                                    0,
-                                    reg_index,
-                                    &qlist_bhead);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-            }
-        }
-    }
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_tm_qmu_qlist_set end++++++\n");
-
-    /*** bank号映射：
-      qmu-->mmu: bank0~7 映射 bank0~7
-      mmu-->qmu: bank0~7 映射 bank0~7 *****/
-    for (j = 0; j < ddr_num; j++)
-    {
-        for (i = 0; i < bank_num_para; i++)
-        {
-            /* qmu-->mmu: bank0~7 映射 bank0~7 */
-            k = j * 8 + i;
-            bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = i;
-            rc  = dpp_reg_write(dev_id,
-                                qmu_cfgmt_bank_to_mmu_index,
-                                0,
-                                k,
-                                &bank_to_mmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            /* mmu-->qmu: bank0~7 映射 bank0~7 */
-            bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                qmu_cfgmt_bank_to_qmu_index,
-                                0,
-                                k,
-                                &bank_to_qmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    /* random映射ram */
-    for (j = 0; j < ddr_num; j++)
-    {
-        for (i = 0; i < bank_num_para; i++)
-        {
-            k = j * bank_num_para + i;
-
-            active_to_bank_cfg.cfgmt_active_to_bank_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                qmu_cfgmt_active_to_bank_index,
-                                0,
-                                k,
-                                &active_to_bank_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* 随机表配置，决定每组bank的轮询顺序 */
-    for (j = 0; j < ddr_num; j++)
-    {
-        for (i = 0; i < bank_num_para; i++)
-        {
-            k = j * 8 + i;
-
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i];
-
-            rc  = dpp_reg_write(dev_id,
-                                qmu_qcfg_qlist_grp0_bank_index,
-                                0,
-                                k,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    for (j = 0; j < ddr_num; j++)
-    {
-        for (i = 0; i < bank_num_para; i++)
-        {
-            k = j * 8 + i;
-
-            qlist_grp1_bank.qcfg_qlist_grp1_bank_wr = qlist_grp0_bank_data[i];
-
-            rc  = dpp_reg_write(dev_id,
-                                qmu_qcfg_qlist_grp1_bank_index,
-                                0,
-                                k,
-                                &qlist_grp1_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    /* qmu配置完成 */
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** QMU DDR随机模式时，DDR随机组配置
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   ddr_num   ddr组数，1-6组
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_ddr_rand_grp_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_num)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 bank_no[6][16] = {{0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7},
-        {0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15},
-        {0, 8, 16, 1, 9, 17, 2, 10, 18, 3, 11, 19, 4, 12, 20, 5},
-        {0, 8, 16, 24, 1, 9, 17, 25, 2, 10, 18, 26, 3, 11, 19, 27},
-        {0, 8, 16, 24, 32, 1, 9, 17, 25, 33, 2, 10, 18, 26, 34, 3},
-        {0, 8, 16, 24, 32, 40, 1, 9, 17, 25, 33, 41, 2, 10, 18, 26}
-    };
-
-    DPP_ETM_QMU_QCFG_QLIST_GRP_T grp = {0};
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T bank = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ddr_num, 1, 6);
-
-    for (i = 0; i < 64; i++)
-    {
-        grp.qcfg_qlist_grp_wr = i % ddr_num;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_GRPr,
-                            0,
-                            i,
-                            &grp);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    for (i = 0; i < 16; i++)
-    {
-        bank.cfgmt_active_to_bank_cfg = bank_no[ddr_num - 1][i];
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                            0,
-                            i,
-                            &bank);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置QMU DDR BANK随机模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   ddr_random   模式:0-轮询模式；1-随机模式
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_ddr_random_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_random)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_QLIST_DDR_RANDOM_T ddr_rand = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ddr_random, 0, 1);
-
-    ddr_rand.qcfg_qlist_ddr_random = ddr_random;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_QMU_QCFG_QLIST_DDR_RANDOMr,
-                        0,
-                        0,
-                        &ddr_rand);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置QMU DDR BANK随机模式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_ddr_random   模式:0-轮询模式；1-随机模式
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_ddr_random_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_ddr_random)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_QLIST_DDR_RANDOM_T ddr_rand = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_ddr_random);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QCFG_QLIST_DDR_RANDOMr,
-                       0,
-                       0,
-                       &ddr_rand);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    *p_ddr_random = ddr_rand.qcfg_qlist_ddr_random;
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** QMU配置完成寄存器，在QMU链表和DDR随机模式寄存器写入后，将此寄存器写1，完成QMU配置
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/05/08
-************************************************************/
-DPP_STATUS dpp_tm_qmu_cfg_done_set(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_QLIST_CFG_DONE_T cfg_done = {0};
-
-    cfg_done.qcfg_qlist_cfg_done = 1;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_QMU_QCFG_QLIST_CFG_DONEr,
-                        0,
-                        0,
-                        &cfg_done);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置CRS的e桶产生的crbal门限值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   index   crs组数：0~15
-* @param   crs_th   CRS产生的crbal门限值
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2021/02/14
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_eir_th_set(ZXIC_UINT32 dev_id,
-                                 ZXIC_UINT32 index,
-                                 ZXIC_UINT32 crs_th)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_QSCH_CRS_EIR_TH_T crs_eir_th = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, index, 0, 0xf);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, crs_th, 0, 0x3ffff);
-
-    crs_eir_th.qcfg_qsch_crs_eir_th = crs_th;
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_QCFG_QSCH_CRS_EIR_THr,
-                       0,
-                       index,
-                       &crs_eir_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置CRS产生的crbal门限值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   index   crs组数：0~15
-* @param   crs_th   CRS产生的crbal门限值
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/11
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_th_set(ZXIC_UINT32 dev_id,
-                                 ZXIC_UINT32 index,
-                                 ZXIC_UINT32 crs_th)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_QSCH_CRS_TH1_T crs_th1 = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, index, 0, 0xf);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, crs_th, 0, 0xffffffff);
-
-    crs_th1.qcfg_qsch_crs_th1 = crs_th;
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_QCFG_QSCH_CRS_TH1r,
-                       0,
-                       index,
-                       &crs_th1);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置CRS产生的空队列确保门限值
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   que_type   队列类型编号(0~15)
-* @param   empty_que_ack_th   空队列确保授权门限
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_th2_set(ZXIC_UINT32 dev_id,
-                                  ZXIC_UINT32 que_type,
-                                  ZXIC_UINT32 empty_que_ack_th)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_QSCH_CRS_TH2_T crs_th2 = {0};
-    ZXIC_UINT32 rem_bit_sum = 4;
-    ZXIC_UINT32 rem = 0;
-    ZXIC_UINT32 exp = 0;
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, que_type, 0, 15);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, empty_que_ack_th, 0, 0x78000);
-
-    rc = dpp_tm_rem_and_exp_translate(empty_que_ack_th,
-                                      rem_bit_sum,
-                                      &rem,
-                                      &exp);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    crs_th2.qcfg_qsch_crs_th2 = (rem << 4) + (exp & 0xf);
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_QCFG_QSCH_CRS_TH2r,
-                       0,
-                       que_type,
-                       &crs_th2);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置CRS发送的速率
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sent_cyc   CRS发送的间隔(单位:时钟周期)
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  szq      @date  2015/03/25
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_sent_rate_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 sent_cyc)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_ETM_QMU_CFGMT_CRS_INTERVAL_T crs_interval = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sent_cyc, 1, 0xffffffff);
-
-    crs_interval.cfgmt_crs_interval = sent_cyc;
-
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFGMT_CRS_INTERVALr,
-                       0,
-                       0,
-                       &crs_interval);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取CRS发送的速率
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_sent_cyc   CRS发送的间隔(单位:时钟周期)
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  szq      @date  2015/03/25
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_sent_rate_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_sent_cyc)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_CFGMT_CRS_INTERVAL_T crs_interval = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_sent_cyc);
-
-
-    *p_sent_cyc = 0;
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_CFGMT_CRS_INTERVALr,
-                       0,
-                       0,
-                       &crs_interval);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_sent_cyc = crs_interval.cfgmt_crs_interval;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置QMU端口间交织模式
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   pkt_blk_mode   交织模式: 1-按包交织; 0-按block交织  SA模式只能配置为1
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  szq      @date  2015/03/25
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pkt_blk_mode_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 pkt_blk_mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_CSW_PKT_BLK_MODE_T csw_pkt_blk_mode = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pkt_blk_mode, 0, 1);
-
-    csw_pkt_blk_mode.qcfg_csw_pkt_blk_mode = pkt_blk_mode;
-
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_QCFG_CSW_PKT_BLK_MODEr,
-                       0,
-                       0,
-                       &csw_pkt_blk_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取QMU端口间交织模式
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_pkt_blk_mode   交织模式: 0-按包交织 ; 1-按block交织SA模式只能配置为1
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  szq      @date  2015/03/25
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pkt_blk_mode_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_pkt_blk_mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_CSW_PKT_BLK_MODE_T csw_pkt_blk_mode = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_pkt_blk_mode);
-
-    *p_pkt_blk_mode = 0;
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QCFG_CSW_PKT_BLK_MODEr,
-                       0,
-                       0,
-                       &csw_pkt_blk_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_pkt_blk_mode = csw_pkt_blk_mode.qcfg_csw_pkt_blk_mode;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置SA模式下各个版本的授权价值
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sa_ver_id   版本号(0~7)
-* @param   sa_credit_value   授权价值
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  szq      @date  2015/03/25
-************************************************************/
-DPP_STATUS dpp_tm_qmu_sa_credit_value_set(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 sa_ver_id,
-                                          ZXIC_UINT32 sa_credit_value)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0_T qmu_sa_credit_value = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sa_ver_id, 0, 7);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sa_credit_value, 0, 0x3ffff);
-
-    qmu_sa_credit_value.cfg_qsch_sa_credit_value_0 = sa_credit_value;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0r + sa_ver_id,
-                        0,
-                        0,
-                        &qmu_sa_credit_value);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取SA模式下各个版本的授权价值
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sa_ver_id   版本号(0~7)
-* @param   p_sa_credit_value   授权价值
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  szq      @date  2015/03/25
-************************************************************/
-DPP_STATUS dpp_tm_qmu_sa_credit_value_get(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 sa_ver_id,
-                                          ZXIC_UINT32 *p_sa_credit_value)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0_T qmu_sa_credit_value = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sa_ver_id, 0, 7);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_sa_credit_value);
-
-    *p_sa_credit_value = 0;
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0r + sa_ver_id,
-                       0,
-                       0,
-                       &qmu_sa_credit_value);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_sa_credit_value = qmu_sa_credit_value.cfg_qsch_sa_credit_value_0;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置多播授权令牌添加个数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   token_add_num   令牌添加时，每次增加的令牌数目，取值范围为1~255，默认为1；禁止配置为0，配置为0时，将不会产生授权。
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_mul_token_gen_num_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 token_add_num)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFG_QSCH_MUL_TOKEN_GEN_NUM_T token_gen_num = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, token_add_num, 1, 255);
-
-    token_gen_num.cfg_qsch_mul_token_gen_num = token_add_num;
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFG_QSCH_MUL_TOKEN_GEN_NUMr,
-                       0,
-                       0,
-                       &token_gen_num);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置多播授权整形桶参数和使能参数
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   q3_lb_control_en   3号队列整形功能开启使能。0：关闭；1：开启。
-* @param   q012_lb_control_en   0～2号队列整形功能开启使能。0：关闭；1：开启。
-* @param   q3_lb_max_cnt   3号队列整形桶桶深。
-* @param   q012_lb_max_cnt   0～2号队列整形桶桶深。
-* @param   q3_lb_add_rate   3号队列令牌添加速率，时钟周期为单位。不可配置为0，配置为0整形使能时，不能产生队列3授权调度信号。
-* @param   q012_lb_add_rate   0～2号队列令牌添加速率，以时钟周期单位。不可配置为0，配置为0并整形使能时，不能产生队列0、1、2授权调度信号。
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_mul_ack_lb_set(ZXIC_UINT32 dev_id,
-                                     ZXIC_UINT32 q3_lb_control_en,
-                                     ZXIC_UINT32 q012_lb_control_en,
-                                     ZXIC_UINT32 q3_lb_max_cnt,
-                                     ZXIC_UINT32 q012_lb_max_cnt,
-                                     ZXIC_UINT32 q3_lb_add_rate,
-                                     ZXIC_UINT32 q012_lb_add_rate)
-{
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 q3_crdt_lb_ctrl_en_reg_index = 0;
-    ZXIC_UINT32 q012_crdt_lb_ctrl_en_reg_index = 0;
-    ZXIC_UINT32 q3_crdt_lb_max_cnt_reg_index = 0;
-    ZXIC_UINT32 q012_crdt_lb_max_cnt_reg_index = 0;
-    ZXIC_UINT32 q3_crdt_lb_add_rate_reg_index = 0;
-    ZXIC_UINT32 q012_crdt_lb_add_rate_reg_index = 0;
-    DPP_ETM_QMU_CFG_QSCH_Q3_CREDIT_LB_CONTROL_EN_T  q3_en = {0};
-    DPP_ETM_QMU_CFG_QSCH_Q012_CREDIT_LB_CONTROL_EN_T q012_en = {0};
-    DPP_ETM_QMU_CFG_QSCH_Q3CREDITLBMAXCNT_T q3_max_cnt = {0};
-    DPP_ETM_QMU_CFG_QSCH_Q012CREDITLBMAXCNT_T q012_max_cnt = {0};
-    DPP_ETM_QMU_CFG_QSCH_Q3LBADDRATE_T q3_rate = {0};
-    DPP_ETM_QMU_CFG_QSCH_Q012LBADDRATE_T q012_rate = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NONE(dev_id, q3_lb_control_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NONE(dev_id, q012_lb_control_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NONE(dev_id, q3_lb_max_cnt, 0, 0xff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NONE(dev_id, q012_lb_max_cnt, 0, 0xff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NONE(dev_id, q3_lb_add_rate, 0, 0xfffffff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NONE(dev_id, q012_lb_add_rate, 0, 0xfffffff);
-
-    q3_crdt_lb_ctrl_en_reg_index = ETM_QMU_CFG_QSCH_Q3_CREDIT_LB_CONTROL_ENr;
-    q012_crdt_lb_ctrl_en_reg_index = ETM_QMU_CFG_QSCH_Q012_CREDIT_LB_CONTROL_ENr;
-    q3_crdt_lb_max_cnt_reg_index = ETM_QMU_CFG_QSCH_Q3CREDITLBMAXCNTr;
-    q012_crdt_lb_max_cnt_reg_index = ETM_QMU_CFG_QSCH_Q012CREDITLBMAXCNTr;
-    q3_crdt_lb_add_rate_reg_index = ETM_QMU_CFG_QSCH_Q3LBADDRATEr;
-    q012_crdt_lb_add_rate_reg_index = ETM_QMU_CFG_QSCH_Q012LBADDRATEr;
-
-    q3_en.cfg_qsch_q3_credit_lb_control_en = q3_lb_control_en;
-    rc = dpp_reg_write(dev_id,
-                       q3_crdt_lb_ctrl_en_reg_index,
-                       0,
-                       0,
-                       &q3_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    q012_en.cfg_qsch_q012_credit_lb_control_en = q012_lb_control_en;
-    rc = dpp_reg_write(dev_id,
-                       q012_crdt_lb_ctrl_en_reg_index,
-                       0,
-                       0,
-                       &q012_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    q3_max_cnt.cfg_qsch_q3creditlbmaxcnt = q3_lb_max_cnt;
-    rc = dpp_reg_write(dev_id,
-                       q3_crdt_lb_max_cnt_reg_index,
-                       0,
-                       0,
-                       &q3_max_cnt);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    q012_max_cnt.cfg_qsch_q012creditlbmaxcnt = q012_lb_max_cnt;
-    rc = dpp_reg_write(dev_id,
-                       q012_crdt_lb_max_cnt_reg_index,
-                       0,
-                       0,
-                       &q012_max_cnt);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    q3_rate.cfg_qsch_q3lbaddrate = q3_lb_add_rate;
-    rc = dpp_reg_write(dev_id,
-                       q3_crdt_lb_add_rate_reg_index,
-                       0,
-                       0,
-                       &q3_rate);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    q012_rate.cfg_qsch_q012lbaddrate = q012_lb_add_rate;
-    rc = dpp_reg_write(dev_id,
-                       q012_crdt_lb_add_rate_reg_index,
-                       0,
-                       0,
-                       &q012_rate);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置0,1号队列挂接1或2号MCN漏桶信息
-* @param   tm_type   0-ETM,1-FTM
-* @param   dev_id   设备索引编号
-* @param   mcn_lb_sel   0：0,1号队列挂接1号MCN漏桶 1：0,1号队列挂接2号MCN漏桶
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_mcn_lb_sel_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 mcn_lb_sel)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFG_QSCH_Q01_ATTACH_EN_T q01_attach_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, mcn_lb_sel, 0, 1);
-
-    q01_attach_en.cfg_qsch_q01_attach_en = mcn_lb_sel;
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFG_QSCH_Q01_ATTACH_ENr,
-                       0,
-                       0,
-                       &q01_attach_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置多播队列0~2的授权输出SP、DWRR
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sp_or_dwrr   SP、DWRR模式选择。0：SP；1：DWRR。
-* @param   dwrr_w0   0号队列DWRR权重(0~127)
-* @param   dwrr_w1   1号队列DWRR权重(0~127)
-* @param   dwrr_w2   2号队列DWRR权重(0~127)
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_mul_sp_dwrr_set(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 sp_or_dwrr,
-                                      ZXIC_UINT32 dwrr_w0,
-                                      ZXIC_UINT32 dwrr_w1,
-                                      ZXIC_UINT32 dwrr_w2)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFG_QSCH_SP_DWRR_EN_T sp_dwrr_en = {0};
-    DPP_ETM_QMU_CFG_QSCH_W0_T qsch_w0 = {0};
-    DPP_ETM_QMU_CFG_QSCH_W1_T qsch_w1 = {0};
-    DPP_ETM_QMU_CFG_QSCH_W2_T qsch_w2 = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, sp_or_dwrr, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dwrr_w0, 0, 0x7f);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dwrr_w1, 0, 0x7f);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dwrr_w2, 0, 0x7f);
-
-    sp_dwrr_en.cfg_qsch_sp_dwrr_en = sp_or_dwrr;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFG_QSCH_SP_DWRR_ENr,
-                       0,
-                       0,
-                       &sp_dwrr_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    qsch_w0.cfg_qsch_w0 = dwrr_w0;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFG_QSCH_W0r,
-                       0,
-                       0,
-                       &qsch_w0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    qsch_w1.cfg_qsch_w1 = dwrr_w1;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFG_QSCH_W1r,
-                       0,
-                       0,
-                       &qsch_w1);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    qsch_w2.cfg_qsch_w2 = dwrr_w2;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFG_QSCH_W2r,
-                       0,
-                       0,
-                       &qsch_w2);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置分目的SA整形打开或关闭
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   shap_en   分目的SA整形使能开关 0：表示关闭 1：表示打开
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_dest_sa_shap_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 shap_en)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFGMT_QMU_SASHAP_EN_T sa_shap_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, shap_en, 0, 1);
- 
-    sa_shap_en.cfgmt_qmu_sashap_en = shap_en;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFGMT_QMU_SASHAP_ENr,
-                       0,
-                       0,
-                       &sa_shap_en);
-
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置轮转扫描使能和扫描速率
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   scan_en   轮转扫描使能。0：关闭，1：开启
-* @param   scan_rate   轮转扫描速率，配置扫描周期不得少于256个周期
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/10
-************************************************************/
-DPP_STATUS dpp_tm_qmu_scan_rate_set(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 scan_en,
-                                    ZXIC_UINT32 scan_rate)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFG_QSCH_SCAN_EN_T qsch_scan_en = {0};
-    DPP_ETM_QMU_CFG_QSCH_SCANRATE_T qsch_scanrate = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, scan_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, scan_rate, 0x100, 0xfffff);
-
-
-    qsch_scan_en.cfg_qsch_scan_en = scan_en;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFG_QSCH_SCAN_ENr,
-                       0,
-                       0,
-                       &qsch_scan_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    qsch_scanrate.cfg_qsch_scanrate = scan_rate;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFG_QSCH_SCANRATEr,
-                       0,
-                       0,
-                       &qsch_scanrate);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获得轮转扫描使能和扫描速率
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   scan_en   轮转扫描使能。0：关闭，1：开启
-* @param   scan_rate   轮转扫描速率，配置扫描周期不得少于256个周期
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/10
-************************************************************/
-DPP_STATUS dpp_tm_qmu_scan_rate_get(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 *p_scan_en,
-                                    ZXIC_UINT32 *p_scan_rate)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFG_QSCH_SCAN_EN_T qsch_scan_en = {0};
-    DPP_ETM_QMU_CFG_QSCH_SCANRATE_T qsch_scanrate = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_scan_en);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_scan_rate);
-
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_CFG_QSCH_SCAN_ENr,
-                      0,
-                      0,
-                      &qsch_scan_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    *p_scan_en = qsch_scan_en.cfg_qsch_scan_en;
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_CFG_QSCH_SCANRATEr,
-                      0,
-                      0,
-                      &qsch_scanrate);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    *p_scan_rate = qsch_scanrate.cfg_qsch_scanrate;
-
-    return DPP_OK;
-
-
-}
-
-/***********************************************************/
-/** 配置轮转扫描队列范围
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   first_que  起始队列号
-* @param   last_que   终止队列号
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/09/10
-************************************************************/
-DPP_STATUS dpp_tm_qmu_scan_que_range_set(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 first_que,
-                                         ZXIC_UINT32 last_que)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFG_QSCH_SCANFRSTQUE_T qsch_scanfirstque_t = {0};
-    DPP_ETM_QMU_CFG_QSCH_SCANLASTQUE_T qsch_scanlastque_t = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, first_que, 0, DPP_ETM_Q_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, last_que, 0, DPP_ETM_Q_NUM - 1);
-
-    qsch_scanfirstque_t.cfg_qsch_scanfrstque = first_que;
-    qsch_scanlastque_t.cfg_qsch_scanlastque = last_que;
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFG_QSCH_SCANFRSTQUEr,
-                       0,
-                       0,
-                       &qsch_scanfirstque_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFG_QSCH_SCANLASTQUEr,
-                       0,
-                       0,
-                       &qsch_scanlastque_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 获取轮转扫描队列范围
-* @param   dev_id   设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   first_que  起始队列号
-* @param   last_que   终止队列号
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/09/10
-************************************************************/
-DPP_STATUS dpp_tm_qmu_scan_que_range_get(ZXIC_UINT32 dev_id,
-                                         ZXIC_UINT32 *first_que,
-                                         ZXIC_UINT32 *last_que)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFG_QSCH_SCANFRSTQUE_T qsch_scanfirstque_t = {0};
-    DPP_ETM_QMU_CFG_QSCH_SCANLASTQUE_T qsch_scanlastque_t = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, first_que);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, last_que);
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_CFG_QSCH_SCANFRSTQUEr,
-                      0,
-                      0,
-                      &qsch_scanfirstque_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_CFG_QSCH_SCANLASTQUEr,
-                      0,
-                      0,
-                      &qsch_scanlastque_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *first_que = qsch_scanfirstque_t.cfg_qsch_scanfrstque;
-    *last_que = qsch_scanlastque_t.cfg_qsch_scanlastque;
-
-    return DPP_OK;
-
-}
-#endif
-
-/***********************************************************/
-/** 配置读命令老化使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   aged_en   读命令老化使能：0：不使能；1：使能
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/11
-************************************************************/
-DPP_STATUS dpp_tm_qmu_wr_aged_en_set(DPP_DEV_T *dev, ZXIC_UINT32 aged_en)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_CSCH_AGED_CFG_T aged_cfg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aged_en, 0, 1);
-
-
-    aged_cfg.qcfg_csch_aged_cfg = aged_en;
-
-    rc = dpp_reg_write(dev,
-                       ETM_QMU_QCFG_CSCH_AGED_CFGr,
-                       0,
-                       0,
-                       &aged_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置读命令老化速率
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   scan_time   读命令老化速率（扫描间隔时间）
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/11
-************************************************************/
-DPP_STATUS dpp_tm_qmu_wr_aged_scan_time_set(DPP_DEV_T *dev, ZXIC_UINT32 scan_time)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_CSCH_AGED_SCAN_TIME_T aged_scan_time = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), scan_time, 0, 0xffffffff);
-
-    aged_scan_time.qcfg_csch_aged_scan_time = scan_time;
-
-    rc = dpp_reg_write(dev,
-                       ETM_QMU_QCFG_CSCH_AGED_SCAN_TIMEr,
-                       0,
-                       0,
-                       &aged_scan_time);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获得读命令老化速率
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_scan_time   读命令老化速率（扫描间隔时间）
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/11
-************************************************************/
-DPP_STATUS dpp_tm_qmu_wr_aged_scan_time_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_scan_time)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_CSCH_AGED_SCAN_TIME_T aged_scan_time = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_scan_time);
-
-    rc = dpp_reg_read(dev,
-                      ETM_QMU_QCFG_CSCH_AGED_SCAN_TIMEr,
-                      0,
-                      0,
-                      &aged_scan_time);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_scan_time = aged_scan_time.qcfg_csch_aged_scan_time;
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 获取QMU清空状态
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_clr_done_flag   队列是否清空完成
-*
-* @return
-* @remark  无
-* @see
-* @author  szq      @date  2015/05/21
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qlist_qcfg_clr_done_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_clr_done_flag)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QLIST_QCFG_CLR_DONE_T clr_done_flag = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_clr_done_flag);
-
-
-    rc = dpp_reg_read(dev,
-                      ETM_QMU_QLIST_QCFG_CLR_DONEr,
-                      0,
-                      0,
-                      &clr_done_flag);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_clr_done_flag = clr_done_flag.qlist_qcfg_clr_done;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置qsch调度分端口整形速率和使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   shape_en   整形使能
-* @param   token_add_num   [23:12]:添加令牌数目
-* @param   token_gap   [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1
-* @param   token_depth 桶深，单位B,范围[0-0x1EE00]
-*公式：（1000*8*token_num）/(gap+1) = X Mbps
-*     主频= 600 MHz
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  xuhb   2020-5-15
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qsch_port_shape_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 port_id,
-                                     ZXIC_UINT32 token_add_num,
-                                     ZXIC_UINT32 token_gap,
-                                     ZXIC_UINT32 token_depth,
-                                     ZXIC_UINT32 shape_en)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_QSCH_SHAP_PARAM_T qsch_shap_param = {0};
-    DPP_ETM_QMU_QCFG_QSCH_SHAP_TOKEN_T qsch_shap_token_depth = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), shape_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_add_num, 0, 0xfff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_gap, 0, 0xfff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_depth, 0, 0x1f000);
-
-    /* 配置整形桶深 */
-    qsch_shap_token_depth.qcfg_qsch_shap_token= token_depth;
-    rc = dpp_reg_write(dev,
-                       ETM_QMU_QCFG_QSCH_SHAP_TOKENr,
-                       0,
-                       port_id,
-                       &qsch_shap_token_depth);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    qsch_shap_param.qcfg_qsch_shap_en = shape_en;
-    qsch_shap_param.qcfg_qsch_shap_param1= token_add_num ;
-    qsch_shap_param.qcfg_qsch_shap_param2= token_gap;
-    rc = dpp_reg_write(dev,
-                       ETM_QMU_QCFG_QSCH_SHAP_PARAMr,
-                       0,
-                       port_id,
-                       &qsch_shap_param);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 配置CMD_SW分端口整形速率和使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   shape_en   整形使能
-* @param   token_add_num   [23:12]:添加令牌数目
-* @param   token_gap   [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1
-* @param   token_depth 桶深，单位B,范围[0-0x1EE00]
-*公式：（1000*8*token_num）/(gap+1) = X Mbps
-*     主频= 600 MHz
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  whuashan   2020-3-17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_port_shape_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 port_id,
-                                     ZXIC_UINT32 token_add_num,
-                                     ZXIC_UINT32 token_gap,
-                                     ZXIC_UINT32 token_depth,
-                                     ZXIC_UINT32 shape_en)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_CSW_SHAP_PARAMETER_T csw_shap_param = {0};
-    DPP_ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTH_T csw_shap_token_depth = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), shape_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_add_num, 0, 0xfff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_gap, 0, 0xfff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_depth, 0, 0x1ee00);
-
-    /* 配置整形桶深 */
-    csw_shap_token_depth.qcfg_csw_shap_token_depth = token_depth;
-    rc = dpp_reg_write(dev,
-                       ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTHr,
-                       0,
-                       port_id,
-                       &csw_shap_token_depth);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    csw_shap_param.qcfg_csw_shap_en = shape_en;
-    csw_shap_param.qcfg_csw_shap_parameter = (token_add_num << 12) | token_gap;
-    rc = dpp_reg_write(dev,
-                       ETM_QMU_QCFG_CSW_SHAP_PARAMETERr,
-                       0,
-                       port_id,
-                       &csw_shap_param);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 获得CMD_SW分端口整形速率和使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_shape_en   整形使能
-* @param   p_token_add_num   [23:12]:添加令牌数目
-* @param   p_token_gap   [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1
-* @param   p_token_depth 桶深，单位B
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  whuashan   2020-3-17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_port_shape_get(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 port_id,
-                                     ZXIC_UINT32 *p_token_add_num,
-                                     ZXIC_UINT32 *p_token_gap,
-                                     ZXIC_UINT32 *p_token_depth,
-                                     ZXIC_UINT32 *p_shape_en)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_CSW_SHAP_PARAMETER_T csw_shap_param = {0};
-    DPP_ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTH_T csw_shap_token_depth = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1);
-    
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_token_add_num);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_token_gap);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_token_depth);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_shape_en);
-
-    rc = dpp_reg_read(dev,
-                      ETM_QMU_QCFG_CSW_SHAP_PARAMETERr,
-                      0,
-                      port_id,
-                      &csw_shap_param);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_shape_en = csw_shap_param.qcfg_csw_shap_en;
-    *p_token_add_num = (csw_shap_param.qcfg_csw_shap_parameter >> 12) & 0xfff;
-    *p_token_gap = csw_shap_param.qcfg_csw_shap_parameter & 0xfff;
-
-    rc = dpp_reg_read(dev,
-                      ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTHr,
-                      0,
-                      port_id,
-                      &csw_shap_token_depth);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_token_depth = csw_shap_token_depth.qcfg_csw_shap_token_depth;
-
-    return DPP_OK;
-
-}
-
-#if 0
-/***********************************************************/
-/** 配置CMD_SW分端口(qmu出端口)整形速率和使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   shape_cir 整形值，单位Mbps，范围[0-160000]
-* @param   shape_cbs 桶深， 单位B，范围[0-0x1EE00]
-* @param   shape_en   整形使能
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author   whuashan   2020-3-17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_egress_shape_set(ZXIC_UINT32 dev_id,
-                                       ZXIC_UINT32 port_id,
-                                       ZXIC_UINT32 shape_cir,
-                                       ZXIC_UINT32 shape_cbs,
-                                       ZXIC_UINT32 shape_en)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_CSW_SHAP_PARAMETER_T csw_shap_param = {0};
-    DPP_ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTH_T csw_shap_token_depth = {0};
-    QMU_PORT_SHAPE_PARA qmu_port_shape_para[100] = {{0}};
-
-    ZXIC_UINT32 token_add_num = 0;
-    ZXIC_UINT32 token_gap = 0;
-    ZXIC_UINT32 shape_value_amplified = 0;
-    ZXIC_UINT32 compare_value = 0;
-    ZXIC_UINT32 shape_para_cnt = 0;
-    ZXIC_UINT32 shape_para_final_cnt = 0;
-    ZXIC_UINT32 shape_min_value = 0;
-    ZXIC_UINT32 shape_min_value_num = 0;
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, shape_cir, 0, 400000);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, shape_cbs, 0, 0x1EE00);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, shape_en, 0, 1);
-
-    /* 获取token_add_num、token_gap */
-    for (token_gap = 10; token_gap <= 0xfff; token_gap++ )
-    {
-        for (token_add_num = 1; token_add_num <= 0xfff; token_add_num++)
-        {
-            shape_value_amplified = (1000 * 8 * token_add_num) / (token_gap + 1);
-            compare_value = (shape_value_amplified - (shape_cir * DPP_TM_QMU_PORT_SHAP_MAG));
-
-            /* 0~20的范围,避免获取token_add_num、token_gap失败 */
-            if ( (compare_value > 0) && (compare_value < 20) && (shape_para_cnt<100))
-            {
-                qmu_port_shape_para[shape_para_cnt].shape_value_amplified = shape_value_amplified;
-                qmu_port_shape_para[shape_para_cnt].token_add_num = token_add_num;
-                qmu_port_shape_para[shape_para_cnt].token_gap =  token_gap;
-                shape_para_final_cnt = shape_para_cnt + 1;
-                shape_para_cnt++;
-            }
-        }
-    }
-
-    /* 获取最小的整形值参数 */
-    shape_min_value = qmu_port_shape_para[0].shape_value_amplified;
-
-    for (shape_para_cnt = 0; shape_para_cnt < shape_para_final_cnt; shape_para_cnt++)
-    {
-        if (shape_min_value > qmu_port_shape_para[shape_para_cnt].shape_value_amplified)
-        {
-            shape_min_value = qmu_port_shape_para[shape_para_cnt].shape_value_amplified;
-            shape_min_value_num  = shape_para_cnt ;
-        }
-    }
-
-    /* 配置整形桶深 */
-    csw_shap_token_depth.qcfg_csw_shap_token_depth = shape_cbs;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTHr,
-                       0,
-                       port_id,
-                       &csw_shap_token_depth);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    /* 配置整形速率 */
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, shape_min_value_num, 0, 99);
-    csw_shap_param.qcfg_csw_shap_en = shape_en;
-    csw_shap_param.qcfg_csw_shap_parameter = (qmu_port_shape_para[shape_min_value_num].token_add_num << 12) | qmu_port_shape_para[shape_min_value_num].token_gap;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_QCFG_CSW_SHAP_PARAMETERr,
-                       0,
-                       port_id,
-                       &csw_shap_param);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 获取CMD_SW分端口整形速率和使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   shape_vlue 整形值，单位Mbps
-* @param   shape_en   整形使能
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author   zmy   @20151217
-************************************************************/
-DPP_STATUS dpp_tm_qmu_egress_shape_get(ZXIC_UINT32 dev_id,
-                                       ZXIC_UINT32 port_id,
-                                       ZXIC_UINT32 *shape_value,
-                                       ZXIC_UINT32 *shape_en)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_CSW_SHAP_PARAMETER_T csw_shap_param = {0};
-    ZXIC_UINT32 token_add_num = 0;
-    ZXIC_UINT32 token_gap = 0;
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, DPP_TM_PP_NUM - 1);
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_QCFG_CSW_SHAP_PARAMETERr,
-                      0,
-                      port_id,
-                      &csw_shap_param);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-
-    token_add_num = (csw_shap_param.qcfg_csw_shap_parameter >> 12) & 0xfff;
-    token_gap = csw_shap_param.qcfg_csw_shap_parameter & 0xfff;
-
-    *shape_value = (((600 * 8 * token_add_num) / (token_gap + 1 )) / DPP_TM_QMU_PORT_SHAP_MAG);
-
-    *shape_en = csw_shap_param.qcfg_csw_shap_en;
-
-    return DPP_OK;
-
-}
-
-#endif
-/***********************************************************/
-/** 配置需要检测的特定队列号
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   需要检测统计的特定的队列号
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/18
-************************************************************/
-DPP_STATUS dpp_tm_qmu_spec_qnum_set(DPP_DEV_T *dev, ZXIC_UINT32 qnum)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_OBSERVE_QNUM_SET_T observe_qnum = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), qnum, 0, DPP_ETM_Q_NUM - 1);
-
-    observe_qnum.observe_qnum_set = qnum;
-    rc = dpp_reg_write(dev,
-                       ETM_QMU_OBSERVE_QNUM_SETr,
-                       0,
-                       0,
-                       &observe_qnum);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 获得特定的队列号
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_qnum   需要检测统计的特定的队列号
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_spec_qnum_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_qnum)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_OBSERVE_QNUM_SET_T observe_qnum = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qnum);
-
-    rc = dpp_reg_read(dev,
-                      ETM_QMU_OBSERVE_QNUM_SETr,
-                      0,
-                      0,
-                      &observe_qnum);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_qnum = observe_qnum.observe_qnum_set;
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 配置需要检测的队列组
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   group_num   需要检测统计的特定的队列组。这里按取q的低3bit
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/18
-************************************************************/
-DPP_STATUS dpp_tm_qmu_spec_group_set(DPP_DEV_T *dev, ZXIC_UINT32 group_num)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_OBSERVE_BATCH_SET_T observe_batch = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), group_num, 0, 7);
-
-    observe_batch.observe_batch_set = group_num;
-    rc = dpp_reg_write(dev,
-                       ETM_QMU_OBSERVE_BATCH_SETr,
-                       0,
-                       0,
-                       &observe_batch);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获得需要检测的队列组
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_group_num   需要检测统计的特定的队列组。这里按取q的低3bit
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_spec_group_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_group_num)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_OBSERVE_BATCH_SET_T observe_batch = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_group_num);
-
-    rc = dpp_reg_read(dev,
-                      ETM_QMU_OBSERVE_BATCH_SETr,
-                      0,
-                      0,
-                      &observe_batch);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_group_num = observe_batch.observe_batch_set;
-
-    return DPP_OK;
-}
-
-#if 0
-/***********************************************************/
-/** 配置出队暂存使用的进程总数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   used_inall   出队暂存使用的进程总数=19-N，默认3表示使用16个进程
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/18
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pid_use_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 used_inall)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFG_PID_USE_INALL_T pid_use_inall = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, used_inall, 0, 19);
-
-    pid_use_inall.cfgmt_nod_rd_buf_0_aful_th = 19 - used_inall;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFG_PID_USE_INALLr,
-                       0,
-                       0,
-                       &pid_use_inall);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获得出队暂存使用的进程总数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_used_inall   出队暂存使用的进程总数=19-N，默认3表示使用16个进程
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pid_use_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_used_inall)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFG_PID_USE_INALL_T pid_use_inall = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_used_inall);
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_CFG_PID_USE_INALLr,
-                      0,
-                      0,
-                      &pid_use_inall);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_used_inall = 19 - pid_use_inall.cfgmt_nod_rd_buf_0_aful_th;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置出队暂存自回加进程总数阈值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   round_th   出队暂存自回加进程总数阈值=19-N，默认4表示使用15个进程就自回加
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/18
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pid_round_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 round_th)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFG_PID_ROUND_TH_T pid_round_th = {0};
-    ZXIC_COMM_CHECK_DEV_INDEX_SUB_OVERFLOW_NO_ASSERT(dev_id,  19 , round_th);    
-    pid_round_th.cfgmt_nod_rd_buf_1_aful_th = 19 - round_th;
-
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFG_PID_ROUND_THr,
-                       0,
-                       0,
-                       &pid_round_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获得出队暂存自回加进程总数阈值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_round_th   出队暂存自回加进程总数阈值=19-N，默认4表示使用15个进程就自回加
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-
-DPP_STATUS dpp_tm_qmu_pid_round_th_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_round_th)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFG_PID_ROUND_TH_T pid_round_th = {0};
-
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_CFG_PID_ROUND_THr,
-                      0,
-                      0,
-                      &pid_round_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_round_th = 19 - pid_round_th.cfgmt_nod_rd_buf_1_aful_th;
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置队列授权盈余
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   配置的队列号
-* @param   value   授权盈余
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/18
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crbal_value_set(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 qnum,
-                                      ZXIC_UINT32 value)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QSCH_RW_CRBAL_T qsch_rw_crbal = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, value, 0, 0x1ffff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qnum, 0, DPP_ETM_Q_NUM - 1);
-
-    qsch_rw_crbal.qsch_rw_crbal = value;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_QSCH_RW_CRBALr,
-                       0,
-                       qnum,
-                       &qsch_rw_crbal);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获得队列授权盈余
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   配置的队列号
-* @param   p_value   授权盈余
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crbal_value_get(ZXIC_UINT32 dev_id,
-                                      ZXIC_UINT32 qnum,
-                                      ZXIC_UINT32 *p_value)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QSCH_RW_CRBAL_T qsch_rw_crbal = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_value);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qnum, 0, DPP_ETM_Q_NUM - 1);
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_QSCH_RW_CRBALr,
-                      0,
-                      qnum,
-                      &qsch_rw_crbal);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_value = qsch_rw_crbal.qsch_rw_crbal & 0x1ffff;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置分目的SA整形桶深上、下限参数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   max_value   分目的SA整形桶深上限，必须配置为正值
-* @param   min_value   分目的SA整形桶深下限，必须配置为负值
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/18
-************************************************************/
-DPP_STATUS dpp_tm_qmu_dest_sa_shape_para_set(ZXIC_UINT32 dev_id,
-                                             ZXIC_SINT32 max_value,
-                                             ZXIC_SINT32 min_value)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFGMT_SASHAP_TOKEN_MAX_T sashap_token_max = {0};
-    DPP_ETM_QMU_CFGMT_SASHAP_TOKEN_MIN_T sashap_token_min = {0};
-
-
-    if (max_value < 0)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "[dev_id %d] max_value < 0, err!!!\n", dev_id);
-        ZXIC_COMM_ASSERT(0);
-        return DPP_ERR;
-    }
-
-    if (min_value > 0)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "[dev_id %d] min_value > 0, err!!!\n", dev_id);
-        ZXIC_COMM_ASSERT(0);
-        return DPP_ERR;
-    }
-
-    sashap_token_max.cfgmt_sashap_token_max = max_value;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFGMT_SASHAP_TOKEN_MAXr,
-                       0,
-                       0,
-                       &sashap_token_max);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    sashap_token_min.cfgmt_sashap_token_min = min_value;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFGMT_SASHAP_TOKEN_MINr,
-                       0,
-                       0,
-                       &sashap_token_min);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获得分目的SA整形桶深上、下限参数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_max_value   分目的SA整形桶深上限，必须配置为正值
-* @param   p_min_value   分目的SA整形桶深下限，必须配置为负值
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_dest_sa_shape_para_get(ZXIC_UINT32 dev_id,
-                                             ZXIC_UINT32 *p_max_value,
-                                             ZXIC_UINT32 *p_min_value)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFGMT_SASHAP_TOKEN_MAX_T sashap_token_max = {0};
-    DPP_ETM_QMU_CFGMT_SASHAP_TOKEN_MIN_T sashap_token_min = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_max_value);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_min_value);
-
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_CFGMT_SASHAP_TOKEN_MAXr,
-                      0,
-                      0,
-                      &sashap_token_max);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    *p_max_value = sashap_token_max.cfgmt_sashap_token_max;
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_CFGMT_SASHAP_TOKEN_MINr,
-                      0,
-                      0,
-                      &sashap_token_min);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    *p_min_value = sashap_token_min.cfgmt_sashap_token_min;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置CRS状态
-* @param   dev_id  设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   队列号
-* @param   state
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_state_set(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 qnum,
-                                    ZXIC_UINT32 state)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QSCH_RW_CRS_T qsch_rw_crs = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, state, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qnum, 0, DPP_ETM_Q_NUM - 1);
-
-    qsch_rw_crs.qsch_rw_crs = state;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_QSCH_RW_CRSr,
-                       0,
-                       qnum,
-                       &qsch_rw_crs);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获得CRS状态
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   队列号
-* @param   p_state
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crs_state_get(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 qnum,
-                                    ZXIC_UINT32 *p_state)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QSCH_RW_CRS_T qsch_rw_crs = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_state);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qnum, 0, DPP_ETM_Q_NUM - 1);
-
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_QSCH_RW_CRSr,
-                      0,
-                      qnum,
-                      &qsch_rw_crs);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    *p_state = qsch_rw_crs.qsch_rw_crs;
-
-    return DPP_OK;
-}
-
-#endif
-/***********************************************************/
-/** 配置自动授权队列范围
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   first_que   自授权起始队列号
-* @param   last_que   自授权终止队列号
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_qmu_auto_credit_que_set(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 first_que,
-                                          ZXIC_UINT32 last_que)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFG_QSCH_AUTOCRFRSTQUE_T qsch_autocrfrstque = {0};
-    DPP_ETM_QMU_CFG_QSCH_AUTOCRLASTQUE_T qsch_autocrlastque = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), first_que, 0, DPP_ETM_Q_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), last_que, 0, DPP_ETM_Q_NUM - 1);
-
-    if (first_que > last_que)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "[dev_id %d] first_que > last_que, err!!!\n", DEV_ID(dev));
-
-        return DPP_ERR;
-    }
-
-    qsch_autocrfrstque.cfg_qsch_autocrfrstque = first_que;
-    rc = dpp_reg_write(dev,
-                       ETM_QMU_CFG_QSCH_AUTOCRFRSTQUEr,
-                       0,
-                       0,
-                       &qsch_autocrfrstque);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    qsch_autocrlastque.cfg_qsch_autocrlastque = last_que;
-    rc = dpp_reg_write(dev,
-                       ETM_QMU_CFG_QSCH_AUTOCRLASTQUEr,
-                       0,
-                       0,
-                       &qsch_autocrlastque);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获得自动授权队列范围
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_first_que   自授权起始队列号
-* @param   p_last_que   自授权终止队列号
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_auto_credit_que_get(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 *p_first_que,
-                                          ZXIC_UINT32 *p_last_que)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFG_QSCH_AUTOCRFRSTQUE_T qsch_autocrfrstque = {0};
-    DPP_ETM_QMU_CFG_QSCH_AUTOCRLASTQUE_T qsch_autocrlastque = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_first_que);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_que);
-
-    rc = dpp_reg_read(dev,
-                      ETM_QMU_CFG_QSCH_AUTOCRFRSTQUEr,
-                      0,
-                      0,
-                      &qsch_autocrfrstque);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-    *p_first_que = qsch_autocrfrstque.cfg_qsch_autocrfrstque;
-
-    rc = dpp_reg_read(dev,
-                      ETM_QMU_CFG_QSCH_AUTOCRLASTQUEr,
-                      0,
-                      0,
-                      &qsch_autocrlastque);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-    *p_last_que = qsch_autocrlastque.cfg_qsch_autocrlastque;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置自动授权开启使能及扫描速率
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   auto_crdt_en   自动授权开启使能，默认关闭。0：关闭；1：开启
-* @param   auto_crdt_rate   自授权速率配置
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_qmu_auto_credit_rate_set(DPP_DEV_T *dev,
-                                           ZXIC_UINT32 auto_crdt_en,
-                                           ZXIC_UINT32 auto_crdt_rate)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_EN_T credit_control_en = {0};
-    DPP_ETM_QMU_CFG_QSCH_AUTOCREDITRATE_T autocredit_rate = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), auto_crdt_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), auto_crdt_rate, 0, 0xfffff);
-
-
-    credit_control_en.cfg_qsch_auto_credit_control_en = auto_crdt_en;
-    rc = dpp_reg_write(dev,
-                       ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_ENr,
-                       0,
-                       0,
-                       &credit_control_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    autocredit_rate.cfg_qsch_autocreditrate = auto_crdt_rate;
-    rc = dpp_reg_write(dev,
-                       ETM_QMU_CFG_QSCH_AUTOCREDITRATEr,
-                       0,
-                       0,
-                       &autocredit_rate);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获得自动授权开启使能及扫描速率
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_auto_crdt_en   自动授权开启使能，默认关闭。0：关闭；1：开启
-* @param   p_auto_crdt_rate   自授权速率配置
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_auto_credit_rate_get(DPP_DEV_T *dev,
-                                           ZXIC_UINT32 *p_auto_crdt_en,
-                                           ZXIC_UINT32 *p_auto_crdt_rate)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_EN_T credit_control_en = {0};
-    DPP_ETM_QMU_CFG_QSCH_AUTOCREDITRATE_T autocredit_rate = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_auto_crdt_en);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_auto_crdt_rate);
-
-    rc = dpp_reg_read(dev,
-                      ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_ENr,
-                      0,
-                      0,
-                      &credit_control_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-    *p_auto_crdt_en = credit_control_en.cfg_qsch_auto_credit_control_en;
-
-    rc = dpp_reg_read(dev,
-                      ETM_QMU_CFG_QSCH_AUTOCREDITRATEr,
-                      0,
-                      0,
-                      &autocredit_rate);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-    *p_auto_crdt_rate = autocredit_rate.cfg_qsch_autocreditrate;
-
-    return DPP_OK;
-}
-
-#if 0
-/***********************************************************/
-/** 配置授权丢弃使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   all_drop_en   所有授权丢弃使能：1：允许丢弃所有授权；0：仅允许丢弃拥塞授权
-* @param   drop_en   授权丢弃使能：1：允许丢弃授权；0：禁止丢弃授权
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crbal_drop_en_set(ZXIC_UINT32 dev_id,
-                                        ZXIC_UINT32 all_drop_en,
-                                        ZXIC_UINT32 drop_en)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFGMT_QSCH_CRBAL_DROP_EN_T crbal_drop_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, all_drop_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, drop_en, 0, 1);
-
-    crbal_drop_en.cfgmt_qsch_all_crbal_drop_en = all_drop_en;
-    crbal_drop_en.cfgmt_qsch_crbal_drop_en = drop_en;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFGMT_QSCH_CRBAL_DROP_ENr,
-                       0,
-                       0,
-                       &crbal_drop_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获得授权丢弃使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_all_drop_en   所有授权丢弃使能：1：允许丢弃所有授权；0：仅允许丢弃拥塞授权
-* @param   p_drop_en   授权丢弃使能：1：允许丢弃授权；0：禁止丢弃授权
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/23
-************************************************************/
-DPP_STATUS dpp_tm_qmu_crbal_drop_en_get(ZXIC_UINT32 dev_id,
-                                        ZXIC_UINT32 *p_all_drop_en,
-                                        ZXIC_UINT32 *p_drop_en)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CFGMT_QSCH_CRBAL_DROP_EN_T crbal_drop_en = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_all_drop_en);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_drop_en);
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_CFGMT_QSCH_CRBAL_DROP_ENr,
-                      0,
-                      0,
-                      &crbal_drop_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_all_drop_en = crbal_drop_en.cfgmt_qsch_all_crbal_drop_en;
-    *p_drop_en = crbal_drop_en.cfgmt_qsch_crbal_drop_en;
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 获取特定队列发送的crs normal的个数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   注 须先设置统计的特定队列
-* @param
-* @return
-* @remark  无
-* @see
-* @author  yjd     @date  2015/07/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_spec_q_crs_normal_cnt(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_que_crs_normal_cnt)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_SPEC_Q_CRS_NORMAL_CNT_T crs_normal_cnt;
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_SPEC_Q_CRS_NORMAL_CNTr,
-                      0,
-                      0,
-                      &crs_normal_cnt);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_que_crs_normal_cnt = crs_normal_cnt.spec_q_crs_normal_cnt;
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取特定队列发送的crs off的个数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   注 须先设置统计的特定队列
-* @param
-* @return
-* @remark  无
-* @see
-* @author  yjd     @date  2015/07/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_spec_q_crs_off_cnt(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_que_crs_off_cnt)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_SPEC_Q_CRS_OFF_CNT_T crs_off_cnt;
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_SPEC_Q_CRS_OFF_CNTr,
-                      0,
-                      0,
-                      &crs_off_cnt);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_que_crs_off_cnt = crs_off_cnt.spec_q_crs_off_cnt;
-    return DPP_OK;
-}
-
-#endif
-/***********************************************************/
-/**设置自然拥塞反压门限值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param
-* @return
-* @remark  无
-* @see
-* @author  yjd     @date  2015/07/16
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qcfg_csch_congest_th_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id, ZXIC_UINT32 qmu_congest_th)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_CSCH_CONGEST_TH_T qcfg_csch_congest_th = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), qmu_congest_th, 0, 0x1ffff);
-
-    qcfg_csch_congest_th.qcfg_csch_congest_th = qmu_congest_th;
-    rc = dpp_reg_write(dev,
-                       ETM_QMU_QCFG_CSCH_CONGEST_THr,
-                       0,
-                       port_id,
-                       &qcfg_csch_congest_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**获取自然拥塞反压门限值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param
-* @return
-* @remark  无
-* @see
-* @author  yjd     @date  2015/07/16
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qcfg_csch_congest_th_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id, ZXIC_UINT32 *p_qmu_congest_th)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_CSCH_CONGEST_TH_T qcfg_csch_congest_th = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qmu_congest_th);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1);
-
-    rc = dpp_reg_read(dev,
-                      ETM_QMU_QCFG_CSCH_CONGEST_THr,
-                      0,
-                      port_id,
-                      &qcfg_csch_congest_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_qmu_congest_th = qcfg_csch_congest_th.qcfg_csch_congest_th;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**设置CMD_SCH分优先级反压门限值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param
-* @return
-* @remark  无
-* @see
-* @author  yjd     @date  2015/07/16
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qcfg_csch_sp_fc_th_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id, ZXIC_UINT32 q_pri, ZXIC_UINT32 qmu_sp_fc_th)
-{
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 index = 0;
-    DPP_ETM_QMU_QCFG_CSCH_SP_FC_TH_T qcfg_csch_sp_fc_th = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_pri, 0, 4);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), qmu_sp_fc_th, 0, 0x1ffff);
-
-    index = port_id * 5 + q_pri;
-    qcfg_csch_sp_fc_th.qcfg_csch_sp_fc_th = qmu_sp_fc_th;
-
-    rc = dpp_reg_write(dev,
-                       ETM_QMU_QCFG_CSCH_SP_FC_THr,
-                       0,
-                       index,
-                       &qcfg_csch_sp_fc_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**获取自然拥塞反压门限值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param
-* @return
-* @remark  无
-* @see
-* @author  yjd     @date  2015/07/16
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qcfg_csch_sp_fc_th_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id, ZXIC_UINT32 q_pri, ZXIC_UINT32 *p_qmu_sp_fc_th)
-{
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 index = 0;
-    DPP_ETM_QMU_QCFG_CSCH_SP_FC_TH_T qcfg_csch_sp_fc_th = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_pri, 0, 4);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qmu_sp_fc_th);
-
-    index = port_id * 5 + q_pri;
-
-    rc = dpp_reg_read(dev,
-                      ETM_QMU_QCFG_CSCH_SP_FC_THr,
-                      0,
-                      index,
-                      &qcfg_csch_sp_fc_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_qmu_sp_fc_th = qcfg_csch_sp_fc_th.qcfg_csch_sp_fc_th;
-
-    return DPP_OK;
-}
-
-#if 0
-/***********************************************************/
-/**每隔10s获取crs状态的个数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param
-* @return
-* @remark  无
-* @see
-* @author  zmy     @date  2015/08/07
-************************************************************/
-
-DPP_STATUS dpp_tm_crs_statics(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_TM_CNT_MODE_T que_get_mode = {0};
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 q_crs_normal_cnt = 0;
-    ZXIC_UINT32 q_crs_off_cnt = 0;
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, que_id, 0, DPP_ETM_Q_NUM - 1);
-
-    rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get");
-    que_get_mode.count_rd_mode = 1;
-
-    rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set");
-
-    rc = dpp_tm_qmu_spec_qnum_set(dev_id, que_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_qnum_set");
-    rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt");
-    rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt");
-
-    for (i = 0; i <= 2; i++)
-    {
-        zxic_comm_sleep(10000);
-        rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt");
-        ZXIC_COMM_PRINT("q_crs_normal_cnt is %d\n ", q_crs_normal_cnt);
-
-        rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt");
-        ZXIC_COMM_PRINT("q_crs_off_cnt is %d\n ", q_crs_off_cnt);
-    }
-
-    rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get");
-    que_get_mode.count_rd_mode = 0;
-
-    rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set");
-
-    return DPP_OK;
-}
-
-
-
-/***********************************************************/
-/** 统计QMU发送和CRDT模块指定授权流接收的CRS计数(10s内)
-* @param   dev_id  设备编号
-* @param   que_id   QMU队列号
-* @param   ackflow_id   授权流号
-* @param   valid_flag   0:队列发送和授权流接收都统计; 1:只关注队列发送，2:只关注授权流接收。
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2017/05/12
-************************************************************/
-DPP_STATUS dpp_tm_crs_cnt_prt(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id, ZXIC_UINT32 ackflow_id, ZXIC_UINT32 valid_flag)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_TM_CNT_MODE_T que_get_mode = {0};
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 q_crs_normal_cnt = 0;
-    ZXIC_UINT32 q_crs_off_cnt = 0;
-    ZXIC_UINT32 crdt_crs_que_id_index = 0;
-    ZXIC_UINT32 all_crs_normal_cnt_index = 0;
-    ZXIC_UINT32 all_crs_off_cnt_index = 0;
-    ZXIC_UINT32 que_crs_normal_cnt_index = 0;
-    ZXIC_UINT32 que_crd_off_cnt_index = 0;
-    ZXIC_UINT32 crs_end_state_index = 0;
-
-
-
-    /* 结构体变量定义 */
-    DPP_ETM_CRDT_CRS_QUE_ID_T crdt_crs_que_id = {0};
-    DPP_ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNT_T all_crs_normal_cnt = {0};
-    DPP_ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNT_T all_crs_off_cnt = {0};
-    DPP_ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNT_T que_crs_normal_cnt = {0};
-    DPP_ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNT_T que_crd_off_cnt = {0};
-    DPP_ETM_CRDT_QMU_CRS_END_STATE_T crs_end_state = {0};
-
-    crdt_crs_que_id_index = ETM_CRDT_CRS_QUE_IDr;
-    all_crs_normal_cnt_index = ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNTr;
-    all_crs_off_cnt_index = ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNTr;
-    que_crs_normal_cnt_index = ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNTr;
-    que_crd_off_cnt_index = ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNTr;
-    crs_end_state_index = ETM_CRDT_QMU_CRS_END_STATEr;
-
-    if (0 == valid_flag)
-    {
-        /* 设置统计CRDT CRS 接收个数的队列号 */
-        crdt_crs_que_id.crs_que_id = ackflow_id;
-        rc = dpp_reg_write(dev_id,
-                           crdt_crs_que_id_index,
-                           0,
-                           0,
-                           &crdt_crs_que_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-        /* 1.先配置读清 */
-        rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get");
-        que_get_mode.count_rd_mode = 1;
-
-        rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set");
-
-        /* 队列发送crs读清 */
-
-        rc = dpp_tm_qmu_spec_qnum_set(dev_id, que_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_qnum_set");
-        rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt");
-        rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt");
-
-        /* crdt接收crs读清 */
-        rc = dpp_tm_crdt_clr_diag(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag");
-
-
-        /* 2.连读两次统计CRS发送和接收 */
-        for (i = 0; i < 2; i++)
-        {
-            zxic_comm_sleep(10000);
-
-            ZXIC_COMM_PRINT("------(%d th)qmu_send & crdt_recv crs_cnt in 10s------\n ", i + 1);
-            /* 统计CRS发送 */
-            rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt");
-            ZXIC_COMM_PRINT("que_id(0x%08x)qmu_send_crs_normal_cnt: 0x%08x\n ", que_id, q_crs_normal_cnt);
-
-            rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt");
-            ZXIC_COMM_PRINT("que_id(0x%08x)qmu_send_crs_off_cnt: 0x%08x\n ", que_id, q_crs_off_cnt);
-
-            /* 统计CRS接收 */
-
-            /* 统计CRDT接收到的CRS off总数 */
-            rc = dpp_reg_read(dev_id,
-                              all_crs_off_cnt_index,
-                              0,
-                              0,
-                              &all_crs_off_cnt);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-            /* 统计CRDT指定队列接收到的CRS off总数 */
-            rc = dpp_reg_read(dev_id,
-                              que_crd_off_cnt_index,
-                              0,
-                              0,
-                              &que_crd_off_cnt);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-            /* 统计CRDT接收到的CRS normal总数 */
-            rc = dpp_reg_read(dev_id,
-                              all_crs_normal_cnt_index,
-                              0,
-                              0,
-                              &all_crs_normal_cnt);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-
-
-            /* 统计CRDT指定队列接收到的CRS normal总数 */
-            rc = dpp_reg_read(dev_id,
-                              que_crs_normal_cnt_index,
-                              0,
-                              0,
-                              &que_crs_normal_cnt);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-
-
-            /* 统计CRDT指定队列接收到的crs最后的状态 */
-            rc = dpp_reg_read(dev_id,
-                              crs_end_state_index,
-                              0,
-                              0,
-                              &crs_end_state);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-            /* crdt接收crs读清 */
-            rc = dpp_tm_crdt_clr_diag(dev_id);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag");
-
-            /* 打印统计信息 */
-            ZXIC_COMM_PRINT("crdt_recv_all_crs_normal_cnt: 0x%08x\n ", all_crs_normal_cnt.fifo_out_all_crs_normal_cnt);
-            ZXIC_COMM_PRINT("crdt_recv_all_crs_off_cnt: 0x%08x\n ", all_crs_off_cnt.fifo_out_all_crs_off_cnt);
-            ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_normal_cnt: 0x%08x\n ", ackflow_id, que_crs_normal_cnt.fifo_out_que_crs_normal_cnt);
-            ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_off_cnt: 0x%08x\n ", ackflow_id, que_crd_off_cnt.fifo_out_que_crs_off_cnt);
-            ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_end_state: %d\n ", ackflow_id, crs_end_state.qmu_crs_end_state);
-
-        }
-
-        /* 3.配置成crs非读清 */
-        rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get");
-        que_get_mode.count_rd_mode = 0;
-
-        rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set");
-
-    }
-    else if (1 == valid_flag)
-    {
-        /* 1.先配置读清 */
-        rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get");
-        que_get_mode.count_rd_mode = 1;
-
-        rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set");
-
-        /* 队列发送crs读清 */
-
-        rc = dpp_tm_qmu_spec_qnum_set(dev_id, que_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_qnum_set");
-        rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt");
-        rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt");
-
-        /* 2.连读两次统计CRS发送和接收 */
-        for (i = 0; i < 2; i++)
-        {
-            zxic_comm_sleep(10000);
-
-            ZXIC_COMM_PRINT("------(%d th)qmu_send crs_cnt in 10s------\n ", i + 1);
-            /* 统计CRS发送 */
-            rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt");
-            ZXIC_COMM_PRINT("que_id(0x%08x)qmu_send_crs_normal_cnt: 0x%08x\n ", que_id, q_crs_normal_cnt);
-
-            rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt");
-            ZXIC_COMM_PRINT("que_id(0x%08x)qmu_send_crs_off_cnt: 0x%08x\n ", que_id, q_crs_off_cnt);
-        }
-
-        /* 3.配置成crs非读清 */
-        rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get");
-        que_get_mode.count_rd_mode = 0;
-
-        rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set");
-    }
-
-    else if (2 == valid_flag)
-    {
-
-        /* 设置统计CRDT CRS 接收个数的队列号 */
-        crdt_crs_que_id.crs_que_id = ackflow_id;
-        rc = dpp_reg_write(dev_id,
-                           crdt_crs_que_id_index,
-                           0,
-                           0,
-                           &crdt_crs_que_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-        /* 2.连读两次统计CRS发送和接收 */
-        for (i = 0; i < 2; i++)
-        {
-
-            /* crdt接收crs读清 */
-            rc = dpp_tm_crdt_clr_diag(dev_id);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag");
-
-            zxic_comm_sleep(10000);
-
-            ZXIC_COMM_PRINT("------(%d th)crdt_recv crs_cnt in 10s------\n ", i + 1);
-
-            /* 统计CRS接收 */
-            /* 统计CRDT指定队列接收到的CRS off总数 */
-            rc = dpp_reg_read(dev_id,
-                              que_crd_off_cnt_index,
-                              0,
-                              0,
-                              &que_crd_off_cnt);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-            /* 统计CRDT接收到的CRS off 总数 */
-            rc = dpp_reg_read(dev_id,
-                              all_crs_off_cnt_index,
-                              0,
-                              0,
-                              &all_crs_off_cnt);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-            /* 统计CRDT接收到的CRS normal总数 */
-            rc = dpp_reg_read(dev_id,
-                              all_crs_normal_cnt_index,
-                              0,
-                              0,
-                              &all_crs_normal_cnt);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-
-
-            /* 统计CRDT指定队列接收到的CRS normal总数 */
-            rc = dpp_reg_read(dev_id,
-                              que_crs_normal_cnt_index,
-                              0,
-                              0,
-                              &que_crs_normal_cnt);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-
-            /* 统计CRDT指定队列接收到的crs最后的状态 */
-            rc = dpp_reg_read(dev_id,
-                              crs_end_state_index,
-                              0,
-                              0,
-                              &crs_end_state);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-            /* crdt接收crs读清 */
-            rc = dpp_tm_crdt_clr_diag(dev_id);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag");
-            /* 打印统计信息 */
-            ZXIC_COMM_PRINT("crdt_recv_all_crs_normal_cnt: 0x%08x\n ", all_crs_normal_cnt.fifo_out_all_crs_normal_cnt);
-            ZXIC_COMM_PRINT("crdt_recv_all_crs_off_cnt: 0x%08x\n ", all_crs_off_cnt.fifo_out_all_crs_off_cnt);
-            ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_normal_cnt: 0x%08x\n ", ackflow_id, que_crs_normal_cnt.fifo_out_que_crs_normal_cnt);
-            ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_off_cnt: 0x%08x\n ", ackflow_id, que_crd_off_cnt.fifo_out_que_crs_off_cnt);
-            ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_end_state: %d\n ", ackflow_id, crs_end_state.qmu_crs_end_state);
-        }
-
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_crs_cnt_prt:valid_flag_error!!: 0: print crs of que and ackflow;1:print que crs only; 2:print ackflow crs only!\n");
-
-    }
-
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 带停流的统计QMU发送和CRDT模块指定授权流接收的CRS计数
-* @param   dev_id  设备编号
-* @param   que_id   QMU队列号
-* @param   ackflow_id   授权流号
-* @param   valid_flag   0:默认队列发送和授权流接收都统计,此时队列授权都在本板;
-*                       1:只关注队列发送，2:只关注授权流接收，需要与源端队列停流配合使用，
-                        先停流，运行该函数；或者直接不停流得到的是某段时间的计数。
-* @param   sleep_time   统计多长时间内的crs计数
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2017/05/12
-************************************************************/
-DPP_STATUS dpp_tm_crs_cnt_prt_1(ZXIC_UINT32 dev_id,
-                                ZXIC_UINT32 que_id,
-                                ZXIC_UINT32 ackflow_id,
-                                ZXIC_UINT32 valid_flag,
-                                ZXIC_UINT32 sleep_time)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_TM_CNT_MODE_T que_get_mode = {0};
-    ZXIC_UINT32 flow_td_th = 0;
-    ZXIC_UINT32 q_crs_normal_cnt = 0;
-    ZXIC_UINT32 q_crs_off_cnt = 0;
-    ZXIC_UINT32 crdt_crs_que_id_index = 0;
-    ZXIC_UINT32 all_crs_normal_cnt_index = 0;
-    ZXIC_UINT32 all_crs_off_cnt_index = 0;
-    ZXIC_UINT32 que_crs_normal_cnt_index = 0;
-    ZXIC_UINT32 que_crd_off_cnt_index = 0;
-    ZXIC_UINT32 crs_end_state_index = 0;
-
-    /* 结构体变量定义 */
-    DPP_ETM_CRDT_CRS_QUE_ID_T crdt_crs_que_id = {0};
-    DPP_ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNT_T all_crs_normal_cnt = {0};
-    DPP_ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNT_T all_crs_off_cnt = {0};
-    DPP_ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNT_T que_crs_normal_cnt = {0};
-    DPP_ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNT_T que_crd_off_cnt = {0};
-    DPP_ETM_CRDT_QMU_CRS_END_STATE_T crs_end_state = {0};
-
-    crdt_crs_que_id_index = ETM_CRDT_CRS_QUE_IDr;
-    all_crs_normal_cnt_index = ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNTr;
-    all_crs_off_cnt_index = ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNTr;
-    que_crs_normal_cnt_index = ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNTr;
-    que_crd_off_cnt_index = ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNTr;
-    crs_end_state_index = ETM_CRDT_QMU_CRS_END_STATEr;
-
-    rc = dpp_tm_cgavd_td_th_get(dev_id, QUEUE_LEVEL, que_id, &flow_td_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_get");
-
-    if (0 == valid_flag)
-    {
-
-
-        /* 设置统计CRDT CRS 接收个数的队列号 */
-        crdt_crs_que_id.crs_que_id = ackflow_id;
-        rc = dpp_reg_write(dev_id,
-                           crdt_crs_que_id_index,
-                           0,
-                           0,
-                           &crdt_crs_que_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        rc = dpp_tm_cgavd_td_th_set(dev_id, QUEUE_LEVEL, que_id, 0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set");
-
-        /* 1.停流配置读清 */
-        rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get");
-        que_get_mode.count_rd_mode = 1;
-
-        rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set");
-
-        /* 队列发送crs读清 */
-
-        rc = dpp_tm_qmu_spec_qnum_set(dev_id, que_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_qnum_set");
-        rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt");
-        rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt");
-
-        /* crdt接收crs读清 */
-        rc = dpp_tm_crdt_clr_diag(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag");
-
-
-        /* 2.统计CRS发送和接收 */
-        rc = dpp_tm_cgavd_td_th_set(dev_id, QUEUE_LEVEL, que_id, flow_td_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set");
-
-
-        zxic_comm_sleep(sleep_time);
-
-        rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt");
-
-        /* 统计CRDT接收到的CRS off总数 */
-        rc = dpp_reg_read(dev_id,
-                          all_crs_off_cnt_index,
-                          0,
-                          0,
-                          &all_crs_off_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-        /* 统计CRDT指定队列接收到的CRS off总数 */
-        rc = dpp_reg_read(dev_id,
-                          que_crd_off_cnt_index,
-                          0,
-                          0,
-                          &que_crd_off_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        rc = dpp_tm_cgavd_td_th_set(dev_id, QUEUE_LEVEL, que_id, 0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set");
-        zxic_comm_sleep(1000);
-
-        /* 统计CRS发送 */
-        rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt");
-        ZXIC_COMM_PRINT("que_id(0x%08x)qmu_send_crs_normal_cnt: 0x%08x\n ", que_id, q_crs_normal_cnt);
-        ZXIC_COMM_PRINT("que_id(0x%08x)qmu_send_crs_off_cnt: 0x%08x\n ", que_id, q_crs_off_cnt);
-        /* 统计CRS接收 */
-        /* 统计CRDT接收到的CRS normal总数 */
-        rc = dpp_reg_read(dev_id,
-                          all_crs_normal_cnt_index,
-                          0,
-                          0,
-                          &all_crs_normal_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        /* 统计CRDT指定队列接收到的CRS normal总数 */
-        rc = dpp_reg_read(dev_id,
-                          que_crs_normal_cnt_index,
-                          0,
-                          0,
-                          &que_crs_normal_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-
-
-        /* 统计CRDT指定队列接收到的crs最后的状态 */
-        rc = dpp_reg_read(dev_id,
-                          crs_end_state_index,
-                          0,
-                          0,
-                          &crs_end_state);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        /* crdt接收crs读清 */
-        rc = dpp_tm_crdt_clr_diag(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag");
-        /* 打印统计信息 */
-        ZXIC_COMM_PRINT("crdt_recv_all_crs_normal_cnt: 0x%08x\n", all_crs_normal_cnt.fifo_out_all_crs_normal_cnt);
-        ZXIC_COMM_PRINT("crdt_recv_all_crs_off_cnt: 0x%08x\n", all_crs_off_cnt.fifo_out_all_crs_off_cnt);
-        ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_normal_cnt: 0x%08x\n", ackflow_id, que_crs_normal_cnt.fifo_out_que_crs_normal_cnt);
-        ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_off_cnt: 0x%08x\n", ackflow_id, que_crd_off_cnt.fifo_out_que_crs_off_cnt);
-        ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_end_state: %d\n", ackflow_id, crs_end_state.qmu_crs_end_state);
-
-
-
-        /* 4.配置成crs非读清 */
-        rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get");
-        que_get_mode.count_rd_mode = 0;
-
-        rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set");
-
-        /* 5.恢复通流 */
-        rc = dpp_tm_cgavd_td_th_set(dev_id, 0, que_id, flow_td_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set");
-
-    }
-    else if (1 == valid_flag) /* 仅统计停流清零再发流该段时间发送的CRS */
-    {
-        rc = dpp_tm_cgavd_td_th_set(dev_id, QUEUE_LEVEL, que_id, 0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set");
-
-        /* 1.停流配置读清 */
-        rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get");
-        que_get_mode.count_rd_mode = 1;
-
-        rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set");
-
-        /* 队列发送crs读清 */
-
-        rc = dpp_tm_qmu_spec_qnum_set(dev_id, que_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_qnum_set");
-        rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt");
-        rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt");
-
-        /* 2.开流设定时间后停流统计CRS发送 */
-        rc = dpp_tm_cgavd_td_th_set(dev_id, QUEUE_LEVEL, que_id, flow_td_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set");
-
-
-        zxic_comm_sleep(sleep_time);
-
-        rc = dpp_tm_qmu_spec_q_crs_off_cnt(dev_id, &q_crs_off_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_off_cnt");
-
-        rc = dpp_tm_cgavd_td_th_set(dev_id, QUEUE_LEVEL, que_id, 0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set");
-        zxic_comm_sleep(1000);
-
-        /* 统计CRS发送 */
-        rc = dpp_tm_qmu_spec_q_crs_normal_cnt(dev_id, &q_crs_normal_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_spec_q_crs_normal_cnt");
-        ZXIC_COMM_PRINT("que_id(0x%08x)qmu_send_crs_normal_cnt: 0x%08x\n ", que_id, q_crs_normal_cnt);
-        ZXIC_COMM_PRINT("que_id(0x%08x)qmu_send_crs_off_cnt: 0x%08x\n ", que_id, q_crs_off_cnt);
-
-        /* 3.配置成crs非读清 */
-        rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get");
-        que_get_mode.count_rd_mode = 0;
-
-        rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set");
-
-        /* 4.恢复通流 */
-        rc = dpp_tm_cgavd_td_th_set(dev_id, QUEUE_LEVEL, que_id, flow_td_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set");
-    }
-
-    else if (2 == valid_flag) /* 仅统计接收，需要源端停流之后运行。*/
-    {
-        /* 设置统计CRDT CRS 接收个数的队列号 */
-        crdt_crs_que_id.crs_que_id = ackflow_id;
-        rc = dpp_reg_write(dev_id,
-                           crdt_crs_que_id_index,
-                           0,
-                           0,
-                           &crdt_crs_que_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        /* 1.停流配置读清 */
-        /* crdt接收crs读清 */
-        rc = dpp_tm_crdt_clr_diag(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag");
-
-        zxic_comm_sleep(sleep_time);
-
-
-        /* 统计CRDT接收到的CRS off总数 */
-        rc = dpp_reg_read(dev_id,
-                          all_crs_off_cnt_index,
-                          0,
-                          0,
-                          &all_crs_off_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-        /* 统计CRDT指定队列接收到的CRS off总数 */
-        rc = dpp_reg_read(dev_id,
-                          que_crd_off_cnt_index,
-                          0,
-                          0,
-                          &que_crd_off_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-
-        /* 统计CRS接收 */
-        /* 统计CRDT接收到的CRS normal总数 */
-        rc = dpp_reg_read(dev_id,
-                          all_crs_normal_cnt_index,
-                          0,
-                          0,
-                          &all_crs_normal_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        /* 统计CRDT指定队列接收到的CRS normal总数 */
-        rc = dpp_reg_read(dev_id,
-                          que_crs_normal_cnt_index,
-                          0,
-                          0,
-                          &que_crs_normal_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-
-
-        /* 统计CRDT指定队列接收到的crs最后的状态 */
-        rc = dpp_reg_read(dev_id,
-                          crs_end_state_index,
-                          0,
-                          0,
-                          &crs_end_state);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-        /* crdt接收crs读清 */
-        rc = dpp_tm_crdt_clr_diag(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag");
-        /* 打印统计信息 */
-        ZXIC_COMM_PRINT("crdt_recv_all_crs_normal_cnt: 0x%08x\n", all_crs_normal_cnt.fifo_out_all_crs_normal_cnt);
-        ZXIC_COMM_PRINT("crdt_recv_all_crs_off_cnt: 0x%08x\n", all_crs_off_cnt.fifo_out_all_crs_off_cnt);
-        ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_normal_cnt: 0x%08x\n", ackflow_id, que_crs_normal_cnt.fifo_out_que_crs_normal_cnt);
-        ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_off_cnt: 0x%08x\n", ackflow_id, que_crd_off_cnt.fifo_out_que_crs_off_cnt);
-        ZXIC_COMM_PRINT("ackflow_id(0x%08x)recv_crs_end_state: %d\n", ackflow_id, crs_end_state.qmu_crs_end_state);
-
-
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "dpp_tm_crs_cnt_prt_1:valid_flag_error!!: 0: print crs of que and ackflow;1:print que crs only; 2:print ackflow crs only\n");
-
-    }
-
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 读取qlist入队及出队状态监控
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2015/08/26
-************************************************************/
-DPP_STATUS dpp_tm_qmu_qlist_state_query(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_QMU_QLIST_STATE_QUERY_T  qcfg_qmu_qlist_state_query = {0};
-
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QCFG_QMU_QLIST_STATE_QUERYr,
-                       0,
-                       0,
-                       &qcfg_qmu_qlist_state_query);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    ZXIC_COMM_PRINT("pkt_age_req_fifo_afull : %d\n", qcfg_qmu_qlist_state_query.pkt_age_req_fifo_afull);
-    ZXIC_COMM_PRINT("rd_release_fwft_afull : %d\n", qcfg_qmu_qlist_state_query.rd_release_fwft_afull);
-    ZXIC_COMM_PRINT("drop_imem_fwft_afull : %d\n", qcfg_qmu_qlist_state_query.drop_imem_fwft_afull);
-    ZXIC_COMM_PRINT("pkt_age_req_fifo_empty : %d\n", qcfg_qmu_qlist_state_query.pkt_age_req_fifo_empty);
-    ZXIC_COMM_PRINT("rd_release_fwft_empty : %d\n", qcfg_qmu_qlist_state_query.rd_release_fwft_empty);
-    ZXIC_COMM_PRINT("drop_imem_fwft_empty : %d\n", qcfg_qmu_qlist_state_query.drop_imem_fwft_empty);
-    ZXIC_COMM_PRINT("mmu_qmu_sop_rd_rdy : %d\n", qcfg_qmu_qlist_state_query.mmu_qmu_sop_rd_rdy);
-    ZXIC_COMM_PRINT("big_fifo_empty : %d\n", qcfg_qmu_qlist_state_query.big_fifo_empty);
-    ZXIC_COMM_PRINT("qmu_mmu_rd_release_rdy : %d\n", qcfg_qmu_qlist_state_query.qmu_mmu_rd_release_rdy);
-    ZXIC_COMM_PRINT("xsw_qmu_crs_rdy : %d\n", qcfg_qmu_qlist_state_query.xsw_qmu_crs_rdy);
-    ZXIC_COMM_PRINT("mmu_qmu_rdy : %d\n", qcfg_qmu_qlist_state_query.mmu_qmu_rdy);
-    ZXIC_COMM_PRINT("mmu_ql_wr_rdy : %d\n", qcfg_qmu_qlist_state_query.mmu_ql_wr_rdy);
-    ZXIC_COMM_PRINT("mmu_ql_rd_rdy : %d\n", qcfg_qmu_qlist_state_query.mmu_ql_rd_rdy);
-    ZXIC_COMM_PRINT("csw_ql_rdy : %d\n", qcfg_qmu_qlist_state_query.csw_ql_rdy);
-    ZXIC_COMM_PRINT("ql_init_done : %d\n", qcfg_qmu_qlist_state_query.ql_init_done);
-    ZXIC_COMM_PRINT("free_addr_ready : %d\n", qcfg_qmu_qlist_state_query.free_addr_ready);
-    ZXIC_COMM_PRINT("bank_group_afull : %d\n", qcfg_qmu_qlist_state_query.bank_group_afull);
-    ZXIC_COMM_PRINT("pds_fwft_empty : %d\n", qcfg_qmu_qlist_state_query.pds_fwft_empty);
-    ZXIC_COMM_PRINT("enq_rpt_fwft_afull : %d\n", qcfg_qmu_qlist_state_query.enq_rpt_fwft_afull);
-
-
-    return DPP_OK;
-}
-
-#endif
-/***********************************************************/
-/** 配置QMU流控计数模式
-* @param   dev_id   设备号
-* @param   tm_type   0-ETM,1-FTM
-* @param   mode   流控模式，0-电平流控；1-边沿流控
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/05/07
-************************************************************/
-DPP_STATUS dpp_tm_qmu_fc_cnt_mode_set(DPP_DEV_T *dev, ZXIC_UINT32 mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_FC_CNT_MODE_T fc_cnt_mode_reg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1);
-
-    fc_cnt_mode_reg.fc_cnt_mode = mode;
-    rc  = dpp_reg_write(dev,
-                        ETM_QMU_FC_CNT_MODEr,
-                        0,
-                        0,
-                        &fc_cnt_mode_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取QMU流控计数模式
-* @param   dev_id   设备号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_mode   流控模式，0-电平流控；1-边沿流控
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/05/07
-************************************************************/
-DPP_STATUS dpp_tm_qmu_fc_cnt_mode_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_FC_CNT_MODE_T fc_cnt_mode_reg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mode);
-
-    rc  = dpp_reg_read(dev,
-                       ETM_QMU_FC_CNT_MODEr,
-                       0,
-                       0,
-                       &fc_cnt_mode_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *p_mode = fc_cnt_mode_reg.fc_cnt_mode;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置QMU需要检测流控的端口号
-* @param   dev_id   设备号
-* @param   tm_type   0-ETM,1-FTM
-* @param   port_id   端口号
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/05/07
-************************************************************/
-DPP_STATUS dpp_tm_qmu_observe_portfc_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_OBSERVE_PORTFC_SPEC_T observe_portfc_reg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1);
-
-
-    observe_portfc_reg.observe_portfc_spec = port_id;
-    rc  = dpp_reg_write(dev,
-                        ETM_QMU_OBSERVE_PORTFC_SPECr,
-                        0,
-                        0,
-                        &observe_portfc_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置QMU需要统计的队列号
-* @param   dev_id   设备号
-* @param   tm_type   0-ETM,1-FTM
-* @param   q_id   队列号
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/05/07
-************************************************************/
-DPP_STATUS dpp_tm_qmu_observe_qnum_set(DPP_DEV_T *dev, ZXIC_UINT32 q_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_OBSERVE_QNUM_SET_T observe_qnum_reg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_id, 0, DPP_ETM_Q_NUM - 1);
-
-    observe_qnum_reg.observe_qnum_set = q_id;
-    rc  = dpp_reg_write(dev,
-                        ETM_QMU_OBSERVE_PORTFC_SPECr,
-                        0,
-                        0,
-                        &observe_qnum_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置QMU需要统计的队列组
-* @param   dev_id   设备号
-* @param   tm_type   0-ETM,1-FTM
-* @param   batch_id   队列组
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/05/07
-************************************************************/
-DPP_STATUS dpp_tm_qmu_observe_batch_set(DPP_DEV_T *dev, ZXIC_UINT32 batch_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_OBSERVE_BATCH_SET_T observe_batch_reg = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), batch_id, 0, 7);
-
-    observe_batch_reg.observe_batch_set = batch_id;
-    rc  = dpp_reg_write(dev,
-                        ETM_QMU_OBSERVE_BATCH_SETr,
-                        0,
-                        0,
-                        &observe_batch_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/******************************************************************************
-*包老化配置
-* @param: dev_id: 设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-*           aging_en: 包老化使能：1表示包老化功能使能；0表示包老化功能关闭。
-*           aging_interval: 普通老化两次的间隔配置
-*           aging_step_interval: 普通老化的老化时间的步进配置值
-*           aging_start_qnum: 老化起始队列
-*           aging_end_qnum: 老化结束队列
-*           aging_req_aful_th: 普通老化FIFO的将满阈值
-*           aging_pkt_num: 一次老化的包个数
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/05/10
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pkt_aging_set(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 aging_en,
-                                    ZXIC_UINT32 aging_interval,
-                                    ZXIC_UINT32 aging_step_interval,
-                                    ZXIC_UINT32 aging_start_qnum,
-                                    ZXIC_UINT32 aging_end_qnum,
-                                    ZXIC_UINT32 aging_pkt_num,
-                                    ZXIC_UINT32 aging_req_aful_th)
-{
-    /* 返回值变量定义 */
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 age_pkt_num_reg_index = 0;
-    ZXIC_UINT32 age_step_interval_reg_index = 0;
-    ZXIC_UINT32 age_interval_reg_index = 0;
-    ZXIC_UINT32 age_qnum_reg_index = 0;
-    ZXIC_UINT32 age_req_aful_th_reg_index = 0;
-    ZXIC_UINT32 age_en_reg_index = 0;
-
-    /* 结构体变量定义 */
-    DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_EN_T cfg_age_en = {0};
-    DPP_ETM_QMU_CFGMT_PKT_AGE_STEP_INTERVAL_T cfg_age_step_interval = {0};
-    DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_INTERVAL_T cfg_age_interval  = {0};
-    DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_START_END_T cfg_age_qnum = {0};
-    DPP_ETM_QMU_CFGMT_PKT_AGE_REQ_AFUL_TH_T cfg_age_req_aful_th  = {0};
-    DPP_ETM_QMU_CFGMT_AGE_PKT_NUM_T cfg_age_pkt_num  = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_step_interval, 0, 0xff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_interval, 0, 0xffff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_req_aful_th, 0, 0x3f);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_pkt_num, 0, 0xf);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_start_qnum, 0, DPP_ETM_Q_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_end_qnum, 0, DPP_ETM_Q_NUM - 1);
-    age_pkt_num_reg_index = ETM_QMU_CFGMT_AGE_PKT_NUMr;
-    age_step_interval_reg_index = ETM_QMU_CFGMT_PKT_AGE_STEP_INTERVALr;
-    age_interval_reg_index = ETM_QMU_CFGMT_QMU_PKT_AGE_INTERVALr;
-    age_qnum_reg_index = ETM_QMU_CFGMT_QMU_PKT_AGE_START_ENDr;
-    age_req_aful_th_reg_index = ETM_QMU_CFGMT_PKT_AGE_REQ_AFUL_THr;
-    age_en_reg_index = ETM_QMU_CFGMT_QMU_PKT_AGE_ENr;
-
-    cfg_age_en.cfgmt_qmu_pkt_age_en = aging_en;
-    cfg_age_step_interval.cfgmt_pkt_age_step_interval = aging_step_interval;
-    cfg_age_interval.cfgmt_qmu_pkt_age_interval = aging_interval;
-    cfg_age_qnum.cfgmt_qmu_pkt_age_start = aging_start_qnum;
-    cfg_age_qnum.cfgmt_qmu_pkt_age_end = aging_end_qnum;
-    cfg_age_req_aful_th.cfgmt_pkt_age_req_aful_th = aging_req_aful_th;
-    cfg_age_pkt_num.cfgmt_age_pkt_num = aging_pkt_num;
-
-
-    rc  = dpp_reg_write(dev,
-                        age_pkt_num_reg_index,
-                        0,
-                        0,
-                        &cfg_age_pkt_num);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    rc  = dpp_reg_write(dev,
-                        age_step_interval_reg_index,
-                        0,
-                        0,
-                        &cfg_age_step_interval);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    rc  = dpp_reg_write(dev,
-                        age_interval_reg_index,
-                        0,
-                        0,
-                        &cfg_age_interval);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    rc  = dpp_reg_write(dev,
-                        age_qnum_reg_index,
-                        0,
-                        0,
-                        &cfg_age_qnum);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    rc  = dpp_reg_write(dev,
-                        age_req_aful_th_reg_index,
-                        0,
-                        0,
-                        &cfg_age_req_aful_th);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    rc  = dpp_reg_write(dev,
-                        age_en_reg_index,
-                        0,
-                        0,
-                        &cfg_age_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/******************************************************************************
-*配置老化一个包的时间，一次老化一个包，老化队列范围为可配
-* @param: dev_id: 设备索引编号
-* @param    tm_type   0: etm; 1: ftm;
-*           aging_en: 包老化使能：1表示包老化功能使能；0表示包老化功能关闭。
-*           aging_time: 老化一个包的时间，单位ms
-            aging_que_start:老化起始队列
-            aging_que_start:老化终止队列
-老化时间=2*aging_interval*step_interval*q_num
-aging_interval = (aging_time * 600000) / (2 * 1 * DPP_TM_Q_NUM);
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb     @date  2020/12/08
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pkt_age_time_set(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 aging_en,
-                                       ZXIC_UINT32 aging_time,
-                                       ZXIC_UINT32 aging_que_start,
-                                       ZXIC_UINT32 aging_que_end)
-{
-    /* 返回值变量定义 */
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 aging_interval = 0;
-    //DPP_CRM_CSR_PLL_CLK_SEL_T pll_clk_sel_t = {0};
-    // ZXIC_UINT32 sys_clk = 0;
-    // ZXIC_UINT32 sys_clk_temp[8]={200,250,300,500,600,800,1000,1200};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_en, 0, 1);
-    
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_que_start, 0, DPP_ETM_Q_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_que_end, 0, DPP_ETM_Q_NUM - 1);
-#if 0
-    rc = dpp_reg_read(dev_id,
-                      CRM_CSR_PLL_CLK_SELr,
-                      0,
-                      0,
-                      &pll_clk_sel_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, pll_clk_sel_t.sys_clk_2x_sel, CRM_SYS_CLK_200M, CRM_SYS_CLK_INVALID - 1);
-
-    sys_clk = sys_clk_temp[pll_clk_sel_t.sys_clk_2x_sel] / 2;
-    ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id,  aging_time , sys_clk );
-    ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id,  aging_time * sys_clk , DPP_TM_KILO_ULL);
-    aging_interval = (aging_time * sys_clk * DPP_TM_KILO_ULL * DPP_TM_KILO_ULL / 1000) / (2 * 1 * (aging_que_end - aging_que_start + 1));
-#endif
-
-
-    if (0 == aging_interval)
-    {
-        aging_interval = 1; /* 防止算出来的是小数，导致写入0 */
-    }
-
-    rc = dpp_tm_qmu_pkt_aging_set(dev, aging_en, aging_interval, 1, aging_que_start, aging_que_end, 1, 0xa);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_qmu_pkt_aging_set");
-
-    return DPP_OK;
-}
-
-#if 0
-/***********************************************************/
-/** 获得队列空标志查询
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   配置的队列号
-* @param   p_value   队列空标志查询
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/06/20
-************************************************************/
-DPP_STATUS dpp_tm_qlist_ept_flag_get(ZXIC_UINT32 dev_id,
-                                     ZXIC_UINT32 qnum,
-                                     ZXIC_UINT32 *p_value)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QCFG_QLIST_EPT_RD_T qcfg_qlist_ept_rd = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_value);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qnum, 0, DPP_ETM_Q_NUM - 1);
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_QCFG_QLIST_EPT_RDr,
-                      0,
-                      qnum,
-                      &qcfg_qlist_ept_rd);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_value = qcfg_qlist_ept_rd.qcfg_qlist_ept_rd;
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 获得队列深度计数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   配置的队列号
-* @param   p_value  队列深度计数
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/06/20
-************************************************************/
-DPP_STATUS dpp_tm_qlist_r_bcnt_get(ZXIC_UINT32 dev_id,
-                                   ZXIC_UINT32 qnum,
-                                   ZXIC_UINT32 *p_value)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_QLIST_R_BCNT_T qlist_r_bcnt = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_value);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qnum, 0, DPP_ETM_Q_NUM - 1);
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_QLIST_R_BCNTr,
-                      0,
-                      qnum,
-                      &qlist_r_bcnt);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_value = qlist_r_bcnt.qlist_r_bcnt;
-
-    return DPP_OK;
-}
-
-#endif
-/***********************************************************/
-/** 配置pfc使能
-* @param   dev_id   设备编号
-* @param   pfc_en   配置的值，0-不使能pfc，1-使能pfc
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lsy      @date  2022/08/22
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pfc_en_set(DPP_DEV_T *dev, ZXIC_UINT32 pfc_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_CFGMT_QMU_PFC_EN_T qmu_pfc_en = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pfc_en, 0, 1);
-
-    qmu_pfc_en.cfgmt_qmu_pfc_en = pfc_en;
-    rc  = dpp_reg_write(dev,
-                        ETM_QMU_CFGMT_QMU_PFC_ENr,
-                        0,
-                        0,
-                        &qmu_pfc_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取pfc使能
-* @param   dev_id   设备编号
-* @param   pfc_en   配置的值，0-不使能pfc，1-使能pfc
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lsy      @date  2022/08/22
-************************************************************/
-DPP_STATUS dpp_tm_qmu_pfc_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *pfc_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_CFGMT_QMU_PFC_EN_T qmu_pfc_en = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pfc_en);
-
-    *pfc_en = 0xffffffff;
-    rc  = dpp_reg_read(dev,
-                       ETM_QMU_CFGMT_QMU_PFC_ENr,
-                       0,
-                       0,
-                       &qmu_pfc_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *pfc_en = qmu_pfc_en.cfgmt_qmu_pfc_en;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置端口pfc掩码
-* @param   dev_id   设备编号
-* @param   port_id   端口号：0~63
-* @param   port_en   端口掩码配置，1pfc模式下该端口接收olif的优先级反压，
-*                                  0pfc模式下该端口不接受olif的优先级反压，并将反压信号全部置1
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lsy      @date  2022/08/22
-************************************************************/
-DPP_STATUS dpp_tm_qmu_port_pfc_make_set(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 port_id,
-                                        ZXIC_UINT32 port_en)
-{
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 value = 0;
-    DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_1_T pfc_mask_31_0 = {0};
-    DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_2_T pfc_mask_63_32 = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_en, 0, 1);
-
-    if (port_id <= 31)
-    {
-        /* port_id:[0-31] */
-        rc = dpp_reg_read(dev,
-                          ETM_QMU_CFGMT_QMU_PFC_MASK_1r,
-                          0,
-                          0,
-                          &pfc_mask_31_0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-        value = pfc_mask_31_0.cfgmt_qmu_pfc_mask_1;
-
-        if (port_en == 0)
-        {
-            value = value & (~(1u << port_id));
-        }
-        else
-        {
-            value = value | (1u << port_id);
-        }
-
-        pfc_mask_31_0.cfgmt_qmu_pfc_mask_1 = value;
-
-        rc = dpp_reg_write(dev,
-                           ETM_QMU_CFGMT_QMU_PFC_MASK_1r,
-                           0,
-                           0,
-                           &pfc_mask_31_0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-    }
-    else
-    {
-        /* port_id:[32-63] */
-        rc = dpp_reg_read(dev,
-                          ETM_QMU_CFGMT_QMU_PFC_MASK_2r,
-                          0,
-                          0,
-                          &pfc_mask_63_32);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-        value = pfc_mask_63_32.cfgmt_qmu_pfc_mask_2;
-
-        if (port_en == 0)
-        {
-            value = value & (~(1u << (port_id - 32)));
-        }
-        else
-        {
-            value = value | (1u<< (port_id - 32));
-        }
-
-        pfc_mask_63_32.cfgmt_qmu_pfc_mask_2 = value;
-
-        rc = dpp_reg_write(dev,
-                           ETM_QMU_CFGMT_QMU_PFC_MASK_2r,
-                           0,
-                           0,
-                           &pfc_mask_63_32);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获得端口pfc掩码
-* @param   dev_id   设备编号
-* @param   port_id   端口号：0~63
-* @param   port_en   端口掩码配置，1pfc模式下该端口接收olif的优先级反压，
-*                                  0pfc模式下该端口不接受olif的优先级反压，并将反压信号全部置1
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  lsy      @date  2022/08/22
-************************************************************/
-DPP_STATUS dpp_tm_qmu_port_pfc_make_get(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 port_id,
-                                        ZXIC_UINT32 *p_port_en)
-{
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 value = 0;
-    DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_1_T pfc_mask_31_0 = {0};
-    DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_2_T pfc_mask_63_32 = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_port_en);
-
-    if (port_id <= 31)
-    {
-        /* port_id:[0-31] */
-        rc = dpp_reg_read(dev,
-                          ETM_QMU_CFGMT_QMU_PFC_MASK_1r,
-                          0,
-                          0,
-                          &pfc_mask_31_0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-        value = pfc_mask_31_0.cfgmt_qmu_pfc_mask_1;
-
-        *p_port_en = 1 & (value >> port_id);
-    }
-    else
-    {
-        /* port_id:[32-63] */
-        rc = dpp_reg_read(dev,
-                          ETM_QMU_CFGMT_QMU_PFC_MASK_2r,
-                          0,
-                          0,
-                          &pfc_mask_63_32);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-        value = pfc_mask_63_32.cfgmt_qmu_pfc_mask_2;
-
-        *p_port_en = 1 & (value >> (port_id - 32));
-    }
-
-    return DPP_OK;
-}
-
-#if 0
-/***********************************************************/
-/** QMU初始化配置场景
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   case_no   QMU初始化场景编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2020/4/14
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 case_no_temp)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 case_no = 0;
-    ZXIC_UINT32 ftm_ddr_no = 0;
-    ZXIC_UINT32 etm_ddr_no = 0;
-
-    
-    g_qmu_init_case_no = case_no_temp;
-    
-    if ((case_no_temp & 0xff) == 0xef && (case_no_temp >> 8)!= 0 && (case_no_temp >> 
-    16 != 0))
-    {
-        case_no = 0xef;
-        ZXIC_COMM_PRINT("Here get in qmu init:%d case_num is %d\n", case_no);
-        /*低8-15bit作为FTM的DDR0-9中的编号,高16-23bit作为ETM的DDR0-9中的编号(only case_16 use)*/
-        ftm_ddr_no = (case_no_temp >> 8) & 0xff;
-        etm_ddr_no = (case_no_temp >> 16) & 0xff;
-    }
-    else if ((case_no_temp & 0xf) == 0xc)
-    {
-        /*etm 和ftm共享指定1组ddr 8bank,其中etm 0-3bank ftm 4-7bank*/
-        case_no = 0xc;
-    }
-    else if ((case_no_temp & 0xf) == 0xd)
-    {
-        /*一个tm独享指定4组8bank*/
-        case_no = 0xd;
-    }
-    else if(((case_no_temp & 0xf) == 0xe) || ((case_no_temp & 0xf) == 0xf) \
-           || ((case_no_temp & 0xf) == 0xb))
-    {
-        /*提取case_no_temp的低4bit作为case_no*/
-        case_no = case_no_temp & 0xf;
-        ZXIC_COMM_PRINT("Here get in qmu init:%d case_num is %d\n", case_no);
-
-        /*中间4bit作为ETM的DDR0-9中的编号,最高4bit作为FTM的DDR0-9中的编号(only case_11 14 15 use)*/
-        ftm_ddr_no = (case_no_temp >> 4) & 0xf;
-        etm_ddr_no = (case_no_temp >> 8) & 0xf;
-    }
-    else
-    {
-        case_no = case_no_temp & 0xf;
-    }
-    /**clear mmu qmu**/
-    rc = dpp_tm_qmu_mmu_cfg_clr(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_mmu_cfg_clr");
-
-
-    if (case_no == 0)
-    {
-        /**纯片内pd16k模式**/
-        //rc = dpp_tm_qmu_init_set_pd16k_2(dev_id, 64);
-        //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_pd16k_2");
-
-        rc = dpp_tm_qmu_init_set_chuk32(dev_id, 512);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_chuk32");
-    }
-    else if (case_no == 1)
-    {
-        /* 场景1：每个tm用8组*4bank，MMU实际分配ftm:0-7组(0145bank); etm:2-9组(2367bank) */
-        rc = dpp_tm_qmu_init_set_1(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_1");
-    }
-    else if (case_no == 2)
-    {
-        /* 场景2：tm独享8组ddr:ftm为0-7组ddr的0123bank，etm为0-7组ddr 4567bank */
-        rc = dpp_tm_qmu_init_set_2(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_2");
-    }
-    else if (case_no == 3)
-    {
-        /* 场景3：TM独享8组ddr:FTM为0-3组ddr的0~3bank，ETM为4-7组ddr 0~3bank */
-        rc = dpp_tm_qmu_init_set_3(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_3");
-    }
-    else if (case_no == 4)
-    {
-        /* 场景4：TM共享2组ddr:FTM为2、4组ddr的01bank，ETM为2、4组ddr 23bank */
-        /*需开启IP_rotation、mmu multi_burst,关闭mmu_rotation_en*/
-        rc = dpp_tm_qmu_init_set_4(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_4");
-    }
-    else if (case_no == 5)
-    {
-        /* 场景5：TM共享4组ddr:FTM为1234组ddr的01bank，ETM为1234组ddr 23bank */
-        /*需开启IP_rotation、mmu multi_burst,关闭mmu_rotation_en*/
-        rc = dpp_tm_qmu_init_set_5(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_5");
-    }
-    else if (case_no == 6)
-    {
-        /*场景6：4组*2bank，MMU实际分配4,6,7,9; etm使用01bank,ftm使用23bank*/
-        /*需开启IP_rotation、mmu multi_burst,关闭mmu_rotation_en*/
-        rc = dpp_tm_qmu_init_set_6(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_6");
-    }
-    else if (case_no == 7)
-    {
-        /* 关闭rotation*/
-        //rc = dpp_mmu_init(0, 0, 0, 0, 0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_init");
-        /* 场景7：每个tm用8组*4bank，MMU实际分配ftm:2-9组(0145bank); etm:2-9组(2367bank) */
-        rc = dpp_tm_qmu_init_set_7(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_7");
-    }
-    else if (case_no == 8)
-    {
-        /* 场景8：每个tm用8组*4bank，MMU实际分配ftm:2-9组(01bank); etm:2-9组(23bank) */
-        /*需开启IP_rotation、mmu multi_burst,关闭mmu_rotation_en*/
-        rc = dpp_tm_qmu_init_set_8(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_8");
-    }
-    else if (case_no == 9)
-    {
-        /*场景9：4组*2bank，MMU实际分配6,7,8,9; etm使用01bank,ftm使用23bank*/
-        /*需开启IP_rotation、mmu multi_burst,关闭mmu_rotation_en*/
-        rc = dpp_tm_qmu_init_set_9(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_9");
-    }
-    else if (case_no == 10)
-    {
-        /* 关闭rotation*/
-        //rc = dpp_mmu_init(0, 0, 0, 0, 0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_init");
-        /*场景10：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank*/
-        rc = dpp_tm_qmu_init_set_10(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_10");
-    }
-    else if (case_no == 11)
-    {
-        /*场景11：TM共享2组ddr:FTM为ddr_no1,ddr_no2组ddr的01bank，ETM为ddr_no1,ddr_no2组ddr 23bank*/
-        rc = dpp_tm_qmu_init_set_11(dev_id, ftm_ddr_no, etm_ddr_no);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_11");
-    }
-    else if (case_no == 0xc)
-    {
-        /*etm 和ftm共享指定1组ddr 8bank,其中etm 0-3bank ftm 4-7bank*/
-        rc = dpp_tm_qmu_init_set_12(dev_id, case_no_temp >> 4);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_12");
-    }
-    else if (case_no == 0xd)
-    {
-        /* 关闭rotation 配置8bank必须关掉，不然会出现crc错包*/
-        //rc = dpp_mmu_init(0, 0, 0, 0, 0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_init");
-        /*场景13：TM独享4组0-7bank,ddr编号来自传参,如0x6789 即代表独享6 7 8 
-        9组ddr的全部bank*/
-        rc = dpp_tm_qmu_init_set_13(dev_id, case_no_temp >> 4);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_13");
-    }
-    else if (case_no == 0xe)
-    {
-        /* 关闭rotation*/
-        //rc = dpp_mmu_init(dev_id, 0, 0, 0, 0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_init");
-
-        /* 场景14：每个tm只用1组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank) */
-        rc = dpp_tm_qmu_init_set_14(dev_id, etm_ddr_no, ftm_ddr_no);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_8");
-    }
-    else if (case_no == 0xf)
-    {
-        /* 场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(0123bank); etm:0-9中指定组(0123bank) */
-        rc = dpp_tm_qmu_init_set_15(dev_id, etm_ddr_no, ftm_ddr_no);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_8");
-    }
-    else/* if (case_no == 0xef)*/
-    {
-        /* 关闭rotation*/
-        //rc = dpp_mmu_init(0, 0, 0, 0, 0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_init");
-        /* 场景15：每个tm只用2组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank) */
-        rc = dpp_tm_qmu_init_set_16(dev_id, etm_ddr_no, ftm_ddr_no);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set_16");
-    }
-
-    return DPP_OK;
-}
-
-
-
-/***********************************************************/
-/** QMU/MMU初始化配置场景1：每个tm用8组*4bank，MMU实际分配ftm:0-7组(0145bank); etm:2-9组(2367bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/10/14
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_1(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 depth = 1024;
-    ZXIC_UINT32 bank_to_mmu_cfg_map[4] = {2, 3, 6, 7};
-    ZXIC_UINT32 qlist_grp0_bank_data[4] = {0, 1, 2, 3};
-
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 start========n");
-
-
-    /* ddr组从qmu到mmu映射,0~7映射成2~9 */
-    for (i = 0; i < 8; i++)
-    {
-        ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = (i + 2);
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* ddr组从mmu到qmu映射,2~9映射成0~7 */
-    for (i = 2; i < 10; i++)
-    {
-        ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = (i - 2);
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* bank号从qmu到mmu映射，每组的bank0~3映射成bank2、3、6、7 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            k = j * 8 + i;
-
-            bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i];
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_mmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* bank号从mmu到qmu映射，每组的bank2、3、6、7映射成bank0、1、2、3 */
-    for (j = 2; j < 10; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id,  j * 8 , bank_to_mmu_cfg_map[i]);
-            k = j * 8 + bank_to_mmu_cfg_map[i];
-
-            bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_qmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    /* random映射ram:配置一个chunk中，bank的轮询顺序 */
-    for (i = 0; i < 16; i++)
-    {
-
-
-        active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 4;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                            0,
-                            i,
-                            &active_to_bank_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    }
-
-
-    /* 首尾深度指针配置 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i) , depth);
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id,  (j * 4 + i + 1) , depth);
-            k = j * 8 + i;
-            qlist_bhead.bank_vld = 1;
-            qlist_bhead.qcfg_qlist_bhead = (j * 4 + i) * depth;
-            qlist_btail.qcfg_qlist_btail = ((j * 4 + i + 1) * depth - 1);
-            qlist_bdep.qcfg_qlist_bdep = depth;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BHEADr,
-                                0,
-                                k,
-                                &qlist_bhead);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BTAILr,
-                                0,
-                                k,
-                                &qlist_btail);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BDEPr,
-                                0,
-                                k,
-                                &qlist_bdep);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8);
-    /* 随机表配置，决定每组bank的轮询顺序 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 64; i++)
-        {
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 4];
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr + j,
-                                0,
-                                i,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 END=======\n");
-
-    return DPP_OK;
-}
-
-
-
-
-/***********************************************************/
-/** QMU/MMU初始化配置场景1：每个tm用8组*4bank，MMU实际分配ftm:0-7组(0145bank); etm:2-9组(2367bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/10/14
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_1(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    /* etm mmu基址配置:ddr2-9组，bank号2367，bank深度1024 */
-    //rc = dpp_mmu_bank_base_addr_set(dev_id, 0x3fc, 0xcc, 1024);
-    //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set");
-
-    rc = dpp_etm_qmu_init_set_1(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** QMU/MMU初始化配置场景二：tm独享8组ddr:ftm为0-7组ddr的0123bank，etm为0-7组ddr 4567bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/10/16
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_2(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 depth = 1024;
-    ZXIC_UINT32 qlist_grp0_bank_data[4] = {1, 2, 3, 0};
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set starting++++++\n");
-
-
-    /* ddr组从qmu到mmu映射,0~7映射成0~7 */
-    for (i = 0; i < 8; i++)
-    {
-        ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = i;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* ddr组从mmu到qmu映射,0~7映射成0~7 */
-    for (i = 0; i < 8; i++)
-    {
-        ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* bank号从qmu到mmu映射，每组bank0、1、2、3映射成bank4567，组0~7循环配置 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            k = j * 8 + i;
-            bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = (i + 4);
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_mmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* bank号从mmu到qmu映射，每组bank4567映射成bank0、1、2、3，组0~7循环配置 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 4; i < 8; i++)
-        {
-
-            k = j * 8 + i;
-            bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = (i - 4);
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_qmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    /* random映射ram:配置一个chunk中，bank的轮询顺序 */
-    for (i = 0; i < 16; i++)
-    {
-        active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 4;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                            0,
-                            i,
-                            &active_to_bank_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* 首尾深度指针配置:j为4组循环 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            k = j * 8 + i;
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i), depth);
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i + 1), depth);
-            qlist_bhead.bank_vld = 1;
-            qlist_bhead.qcfg_qlist_bhead = (j * 4 + i) * depth;
-            qlist_btail.qcfg_qlist_btail = ((j * 4 + i + 1) * depth - 1);
-            qlist_bdep.qcfg_qlist_bdep = depth;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BHEADr,
-                                0,
-                                k,
-                                &qlist_bhead);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BTAILr,
-                                0,
-                                k,
-                                &qlist_btail);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BDEPr,
-                                0,
-                                k,
-                                &qlist_bdep);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8);
-    /* 随机表配置，决定ddr内bank的轮询顺序:使用几组ddr需要配置几组 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 64; i++)
-        {
-
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 4];
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr + j,
-                                0,
-                                i,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set end++++++\n");
-
-    return DPP_OK;
-}
-
-
-
-/***********************************************************/
-/** QMU/MMU初始化配置场景二：tm独享8组ddr:ftm为0-7组ddr的0123bank，etm为0-7组ddr 4567bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/10/16
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_2(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    /* etm mmu基址配置:ddr0-7组，bank号4567，bank深度1024 */
-    //rc = dpp_mmu_bank_base_addr_set(dev_id, 0xff, 0xf0, 1024);
-    //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set");
-
-    rc = dpp_etm_qmu_init_set_2(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set");
-
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配4~7组，每组2~3,6~7bank
-*    depth=64,代表16k
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_pd16k_2(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 qlist_grp0_bank_data[4] = {1, 2, 3, 0};
-    ZXIC_UINT32 ddr_num = 4;
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP1_BANK_T qlist_grp1_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP2_BANK_T qlist_grp2_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP3_BANK_T qlist_grp3_bank = {0};
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set starting++++++\n");
-
-    /* cfgmt配置4组ddr */
-    rc = dpp_tm_cfgmt_ddr_attach_set(dev_id, ddr_num);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_ddr_attach_set");
-
-
-    /* ddr组从qmu到mmu映射,0~3映射成4~7 */
-    for (i = 0; i < 4; i++)
-    {
-        ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = (i + 4);
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* ddr组从mmu到qmu映射,4~7映射成0~3 */
-    for (i = 4; i < 8; i++)
-    {
-        ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = (i - 4);
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* bank号从qmu到mmu映射，每组bank0、1、2、3映射成bank2、3、6、7，组0~3循环配置 */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            k = j * 8 + i;
-
-            if (i < 2)
-            {
-                bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = (i + 2);
-            }
-            else
-            {
-                bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = (i + 4);
-            }
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_mmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* bank号从mmu到qmu映射，每组bank2、3、6、7映射成bank0、1、2、3，组4~7循环配置 */
-    for (j = 4; j < 8; j++)
-    {
-        for (i = 2; i < 6; i++)
-        {
-            if (i < 4)
-            {
-                k = j * 8 + i;
-            }
-            else
-            {
-                k = j * 8 + i + 2;
-            }
-
-            bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = (i - 2);
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_qmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    /* random映射ram */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            active_to_bank_cfg.cfgmt_active_to_bank_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                                0,
-                                k,
-                                &active_to_bank_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* 首尾深度指针配置:j为4组循环 */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            k = j * 8 + i;
-
-            qlist_bhead.bank_vld = 1;
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i), depth);
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i + 1), depth);
-            qlist_bhead.qcfg_qlist_bhead = (j * 4 + i) * depth;
-            qlist_btail.qcfg_qlist_btail = ((j * 4 + i + 1) * depth - 1);
-            qlist_bdep.qcfg_qlist_bdep = depth;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BHEADr,
-                                0,
-                                k,
-                                &qlist_bhead);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BTAILr,
-                                0,
-                                k,
-                                &qlist_btail);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BDEPr,
-                                0,
-                                k,
-                                &qlist_bdep);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* 随机表配置，决定每组bank的轮询顺序 */
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i];;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr,
-                                0,
-                                k,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            qlist_grp1_bank.qcfg_qlist_grp1_bank_wr = qlist_grp0_bank_data[i];;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP1_BANKr,
-                                0,
-                                k,
-                                &qlist_grp1_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            qlist_grp2_bank.qcfg_qlist_grp2_bank_wr = qlist_grp0_bank_data[i];;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP2_BANKr,
-                                0,
-                                k,
-                                &qlist_grp2_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            qlist_grp3_bank.qcfg_qlist_grp3_bank_wr = qlist_grp0_bank_data[i];;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP3_BANKr,
-                                0,
-                                k,
-                                &qlist_grp3_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set end++++++\n");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** QMU初始化配置场景二：ddr3模式，tm看到4组*4bank，对应DDR分配4~7组，每组2~3,6~7bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_pd16k_2(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    rc = dpp_etm_qmu_init_set_pd16k_2(dev_id, depth);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set");
-
-    return DPP_OK;
-}
-
-
-DPP_STATUS dpp_qmu_init_info(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 ddr_num = 0;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP1_BANK_T qlist_grp1_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP2_BANK_T qlist_grp2_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP3_BANK_T qlist_grp3_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP4_BANK_T qlist_grp4_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP5_BANK_T qlist_grp5_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP6_BANK_T qlist_grp6_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP7_BANK_T qlist_grp7_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0};
-    dpp_tm_cfgmt_ddr_attach_get(0, &ddr_num);
-    ZXIC_COMM_PRINT("dpp_tm_cfgmt_ddr_attach_get ddr_num:%d\n",ddr_num);
-
-    /* random映射ram */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            active_to_bank_cfg.cfgmt_active_to_bank_cfg = 0;
-
-            rc  = dpp_reg_read(dev_id,
-                                ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                                0,
-                                k,
-                                &active_to_bank_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-            ZXIC_COMM_PRINT("cfgmt_active_to_bank_cfg: cfgmt_active_to_bank_cfg-%d value:%d\n",k,active_to_bank_cfg.cfgmt_active_to_bank_cfg);
-        }
-    }
-
-    /* 首尾深度指针配置: */
-    for (j = 0, k = 0; j < 8; j++)
-    {
-        k = j * 8;
-        rc  = dpp_reg_read(dev_id,
-                            ETM_QMU_QCFG_QLIST_BHEADr,
-                            0,
-                            k,
-                            &qlist_bhead);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-        ZXIC_COMM_PRINT("qlist_bhead: qlist_bhead-%d bank_vld:%d qcfg_qlist_bhead:%d\n",k,qlist_bhead.bank_vld,qlist_bhead.qcfg_qlist_bhead);
-
-        rc  = dpp_reg_read(dev_id,
-                            ETM_QMU_QCFG_QLIST_BTAILr,
-                            0,
-                            k,
-                            &qlist_btail);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-        ZXIC_COMM_PRINT("qlist_btail: qlist_btail-%d qcfg_qlist_btail:%d\n",k,qlist_btail.qcfg_qlist_btail);
-
-        
-    }
-    for (j = 0; j < 64; j++)
-    {
-        
-        rc  = dpp_reg_read(dev_id,
-                            ETM_QMU_QCFG_QLIST_BDEPr,
-                            0,
-                            j,
-                            &qlist_bdep);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-        ZXIC_COMM_PRINT("qlist_bdep: qlist_bdep-%d qcfg_qlist_bdep:%d\n",j,qlist_bdep.qcfg_qlist_bdep);
-    }
-
-    /* 随机表配置，决定每组bank的轮询顺序 */
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            rc  = dpp_reg_read(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr,
-                                0,
-                                k,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-            ZXIC_COMM_PRINT("qlist_grp0_bank: qlist_grp0_bank-%d qcfg_qlist_grp0_bank_wr:%d\n",k,qlist_grp0_bank.qcfg_qlist_grp0_bank_wr);
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            rc  = dpp_reg_read(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP1_BANKr,
-                                0,
-                                k,
-                                &qlist_grp1_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-            ZXIC_COMM_PRINT("qlist_grp1_bank: qlist_grp1_bank-%d qcfg_qlist_grp1_bank_wr:%d\n",k,qlist_grp1_bank.qcfg_qlist_grp1_bank_wr);
-
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            rc  = dpp_reg_read(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP2_BANKr,
-                                0,
-                                k,
-                                &qlist_grp2_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-            ZXIC_COMM_PRINT("qlist_grp2_bank: qlist_grp2_bank-%d qcfg_qlist_grp2_bank_wr:%d\n",k,qlist_grp2_bank.qcfg_qlist_grp2_bank_wr);
-
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            rc  = dpp_reg_read(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP3_BANKr,
-                                0,
-                                k,
-                                &qlist_grp3_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-            ZXIC_COMM_PRINT("qlist_grp3_bank: qlist_grp3_bank-%d qcfg_qlist_grp3_bank_wr:%d\n",k,qlist_grp3_bank.qcfg_qlist_grp3_bank_wr);
-
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            rc  = dpp_reg_read(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP4_BANKr,
-                                0,
-                                k,
-                                &qlist_grp4_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-            ZXIC_COMM_PRINT("qlist_grp4_bank: qlist_grp4_bank-%d qcfg_qlist_grp4_bank_wr:%d\n",k,qlist_grp4_bank.qcfg_qlist_grp4_bank_wr);
-
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            rc  = dpp_reg_read(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP5_BANKr,
-                                0,
-                                k,
-                                &qlist_grp5_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-            ZXIC_COMM_PRINT("qlist_grp5_bank: qlist_grp5_bank-%d qcfg_qlist_grp5_bank_wr:%d\n",k,qlist_grp5_bank.qcfg_qlist_grp5_bank_wr);
-
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            rc  = dpp_reg_read(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP6_BANKr,
-                                0,
-                                k,
-                                &qlist_grp6_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-            ZXIC_COMM_PRINT("qlist_grp6_bank: qlist_grp6_bank-%d qcfg_qlist_grp6_bank_wr:%d\n",k,qlist_grp6_bank.qcfg_qlist_grp6_bank_wr);
-
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            rc  = dpp_reg_read(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP7_BANKr,
-                                0,
-                                k,
-                                &qlist_grp7_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-            ZXIC_COMM_PRINT("qlist_grp7_bank: qlist_grp7_bank-%d qcfg_qlist_grp7_bank_wr:%d\n",k,qlist_grp7_bank.qcfg_qlist_grp7_bank_wr);
-
-        }
-    }
-
-    for (j = 0; j < 8; j++)     
-    {
-        for (i = 0, k = 0; i < 8; i++)
-        {
-            k = j * 8 + i;
- 
-            rc  = dpp_reg_read(dev_id,
-                            ETM_QMU_QCFG_QLIST_GRPr,
-                            0,
-                            k,
-                            &qcfg_qlist_grp);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-            ZXIC_COMM_PRINT("qcfg_qlist_grp: qcfg_qlist_grp-%d qcfg_qlist_grp_wr:%d\n",k,qcfg_qlist_grp.qcfg_qlist_grp_wr);
-        }
-    }
-
-
-    return DPP_OK;
-}
-/***********************************************************/
-/** QMU初始化配置场景二：ddr3模式，8组*8bank
-*    depth=512,代表32k
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/04/12
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_chuk32(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 qlist_grp0_bank_data[8] = {0, 0, 0, 0, 0, 0, 0, 0};
-    ZXIC_UINT32 qlist_grp_bank_data[8] = {0, 1, 2, 3, 4, 5, 6, 7};
-    ZXIC_UINT32 ddr_num = 0xff;
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP1_BANK_T qlist_grp1_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP2_BANK_T qlist_grp2_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP3_BANK_T qlist_grp3_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP4_BANK_T qlist_grp4_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP5_BANK_T qlist_grp5_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP6_BANK_T qlist_grp6_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP7_BANK_T qlist_grp7_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0};
-    
-
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set starting++++++\n");
-
-    /* cfgmt配置8组ddr */
-    rc = dpp_tm_cfgmt_ddr_attach_set(dev_id, ddr_num);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_ddr_attach_set");
-
-    /* 首尾深度指针配置: */
-    for (j = 0, k = 0; j < 8; j++)
-    {
-        
-        k = j * 8;
-        qlist_bhead.bank_vld = 1;
-        qlist_bhead.qcfg_qlist_bhead = j * depth;
-        qlist_btail.qcfg_qlist_btail = 511 + j * depth;
-        
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BHEADr,
-                            0,
-                            k,
-                            &qlist_bhead);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BTAILr,
-                            0,
-                            k,
-                            &qlist_btail);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        
-    }
-    for (j = 0; j < 64; j++)
-    {
-        qlist_bdep.qcfg_qlist_bdep = depth;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BDEPr,
-                            0,
-                            j,
-                            &qlist_bdep);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* 随机表配置，决定每组bank的轮询顺序 */
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[0];
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr,
-                                0,
-                                k,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            qlist_grp1_bank.qcfg_qlist_grp1_bank_wr = qlist_grp0_bank_data[1];;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP1_BANKr,
-                                0,
-                                k,
-                                &qlist_grp1_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            qlist_grp2_bank.qcfg_qlist_grp2_bank_wr = qlist_grp0_bank_data[2];;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP2_BANKr,
-                                0,
-                                k,
-                                &qlist_grp2_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            qlist_grp3_bank.qcfg_qlist_grp3_bank_wr = qlist_grp0_bank_data[3];;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP3_BANKr,
-                                0,
-                                k,
-                                &qlist_grp3_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            qlist_grp4_bank.qcfg_qlist_grp4_bank_wr = qlist_grp0_bank_data[4];;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP4_BANKr,
-                                0,
-                                k,
-                                &qlist_grp4_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            qlist_grp5_bank.qcfg_qlist_grp5_bank_wr = qlist_grp0_bank_data[5];;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP5_BANKr,
-                                0,
-                                k,
-                                &qlist_grp5_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            qlist_grp6_bank.qcfg_qlist_grp6_bank_wr = qlist_grp0_bank_data[6];;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP6_BANKr,
-                                0,
-                                k,
-                                &qlist_grp6_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    for (j = 0; j < 16; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            k = j * 4 + i;
-
-            qlist_grp7_bank.qcfg_qlist_grp7_bank_wr = qlist_grp0_bank_data[7];;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP7_BANKr,
-                                0,
-                                k,
-                                &qlist_grp7_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    for (j = 0; j < 8; j++)     
-    {
-        for (i = 0, k = 0; i < 8; i++)
-        {
-            k = j * 8 + i;
-            qcfg_qlist_grp.qcfg_qlist_grp_wr = qlist_grp_bank_data[i];
-            rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_GRPr,
-                            0,
-                            k,
-                            &qcfg_qlist_grp);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-        /* random映射ram */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0, k = 0; i < 4; i++)
-        {
-            
-            k = j * 4 + i;
-
-            active_to_bank_cfg.cfgmt_active_to_bank_cfg = 0;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                                0,
-                                k,
-                                &active_to_bank_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-    zxic_comm_sleep(5);
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set end++++++\n");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** QMU初始化配置场景：ddr3模式，8组ddr*8bank
-* @param   dev_id   设备编号
-* @param   depth   bank depth
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/04/12
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_chuk32(ZXIC_UINT32 dev_id, ZXIC_UINT32 depth)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    rc = dpp_etm_qmu_init_set_chuk32(dev_id, depth);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** QMU初始化配置场景二：TM独享8组ddr:FTM为0-3组ddr的0~3bank，ETM为4-7组ddr 0~3bank
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_3(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 depth = 2048;
-    ZXIC_UINT32 qlist_grp0_bank_data[8] = {0, 1, 2, 3, 4, 5, 6, 7};
-
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0};
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set starting++++++\n");
-
-
-    /* ddr组从qmu到mmu映射,0~3映射成4~7 */
-    for (i = 0; i < 4; i++)
-    {
-        ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = i + 4;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* ddr组从mmu到qmu映射,4~7映射成0~3 */
-    for (i = 4; i < 8; i++)
-    {
-        ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i - 4;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* bank号从qmu到mmu映射，组0~3的bank0-3映射成bank0-3 */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            k = j * 8 + i;
-
-            bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_mmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* bank号从mmu到qmu映射，组4~7的bank0-7映射成bank0-7 */
-    for (j = 4; j < 8; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            k = j * 8 + i;
-
-            bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_qmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    /* random映射ram:配置一个chunk中，bank的轮询顺序 */
-    for (i = 0; i < 16; i++)
-    {
-        active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 4;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                            0,
-                            i,
-                            &active_to_bank_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* 首尾深度指针配置:j为8组循环 */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            k = j * 8 + i;
-
-            qlist_bhead.bank_vld = 1;
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i), depth);
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i + 1), depth);
-            qlist_bhead.qcfg_qlist_bhead = (j * 4 + i) * depth;
-            qlist_btail.qcfg_qlist_btail = ((j * 4 + i + 1) * depth - 1);
-            qlist_bdep.qcfg_qlist_bdep = depth;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BHEADr,
-                                0,
-                                k,
-                                &qlist_bhead);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BTAILr,
-                                0,
-                                k,
-                                &qlist_btail);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BDEPr,
-                                0,
-                                k,
-                                &qlist_bdep);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8);
-    /* 随机表配置，决定ddr内bank的轮询顺序:使用几组ddr需要配置几组 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 64; i++)
-        {
-
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 4];
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr + j,
-                                0,
-                                i,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    for (j = 0; j < 64; j++)
-    {
-        qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 4;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_GRPr,
-                            0,
-                            j,
-                            &qcfg_qlist_grp);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set end++++++\n");
-
-    return DPP_OK;
-}
-
-
-
-
-/***********************************************************/
-/** QMU/MMU初始化配置场景三：TM独享8组ddr:FTM为0-3组ddr的0~3bank，ETM为4-7组ddr 0~3bank
-*   MMU开启rotatjon
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_3(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_RANDOM_BYPASS_EN_T etm_bypass = {0};
-//    DPP_FTM_QMU_RANDOM_BYPASS_EN_T ftm_bypass = {0};
-
-    /* etm mmu基址配置:ddr4-7组，bank号0-3，bank深度2048 */
-    //rc = dpp_mmu_bank_base_addr_set(dev_id, 0xf0, 0xf, 2048);
-    //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set");
-
-    rc = dpp_etm_qmu_init_set_3(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set_1");
-
-    /* 关闭etm映射配置 */
-    etm_bypass.random_bypass_en = 0;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_QMU_RANDOM_BYPASS_ENr,
-                        0,
-                        0,
-                        &etm_bypass);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**场景4：TM共享2组ddr:FTM为2、4组ddr的01bank，ETM为2、4组ddr 23bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/06/06
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_4(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 depth = 8 * 1024;
-    ZXIC_UINT32 ddr_to_mmu_cfg_map[2] = {2, 4};
-    ZXIC_UINT32 bank_to_mmu_cfg_map[2] = {2, 3};
-    ZXIC_UINT32 qlist_grp0_bank_data[2] = {0, 1};
-
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0};
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_4 start========n");
-
-
-    /* ddr组从qmu到mmu映射,0~1映射成2 4 */
-    for (i = 0; i < 2; i++)
-    {
-        ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = ddr_to_mmu_cfg_map[i];
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* ddr组从mmu到qmu映射,2 4映射成0~1 */
-    for (i = 0; i < 2; i++)
-    {
-        ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-                            0,
-                            ddr_to_mmu_cfg_map[i],
-                            &ddr_in_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* bank号从qmu到mmu映射，每组的bank0~1映射成bank2、3 */
-    for (j = 0; j < 2; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            k = j * 8 + i;
-
-            bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i];
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_mmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* bank号从mmu到qmu映射，每组的bank2、3映射成bank0、1 */
-    for (j = 0; j < 2; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, ddr_to_mmu_cfg_map[j] , 8);
-            ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id,  ddr_to_mmu_cfg_map[j] * 8 , bank_to_mmu_cfg_map[i]);
-            k = ddr_to_mmu_cfg_map[j] * 8 + bank_to_mmu_cfg_map[i];
-            bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_qmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    /* random映射ram:配置一个chunk中，bank的轮询顺序 */
-    for (i = 0; i < 16; i++)
-    {
-
-
-        active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 2;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                            0,
-                            i,
-                            &active_to_bank_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    }
-
-
-    /* 首尾深度指针配置 */
-    for (j = 0; j < 2; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            k = j * 8 + i;
-
-            qlist_bhead.bank_vld = 1;
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i), depth);
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i + 1), depth);
-            qlist_bhead.qcfg_qlist_bhead = (j * 2 + i) * depth;
-            qlist_btail.qcfg_qlist_btail = ((j * 2 + i + 1) * depth - 1);
-            qlist_bdep.qcfg_qlist_bdep = depth;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BHEADr,
-                                0,
-                                k,
-                                &qlist_bhead);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BTAILr,
-                                0,
-                                k,
-                                &qlist_btail);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BDEPr,
-                                0,
-                                k,
-                                &qlist_bdep);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (i = 0; i < 64; i++)
-    {
-        qlist_bdep.qcfg_qlist_bdep = depth;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BDEPr,
-                            0,
-                            i,
-                            &qlist_bdep);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8);
-    /* 随机表配置，决定每组bank的轮询顺序 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 64; i++)
-        {
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 2];
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr + j,
-                                0,
-                                i,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (j = 0; j < 64; j++)
-    {
-        qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 2;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_GRPr,
-                            0,
-                            j,
-                            &qcfg_qlist_grp);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_4 END=======\n");
-
-    return DPP_OK;
-}
-
-
-
-
-/***********************************************************/
-/**场景4：TM共享2组ddr:FTM为2、4组ddr的01bank，ETM为2、4组ddr 23bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/06/06
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_4(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_RANDOM_BYPASS_EN_T etm_bypass = {0};
-    //DPP_FTM_QMU_RANDOM_BYPASS_EN_T ftm_bypass = {0};
-
-    /* etm mmu基址配置:ddr2、4组，bank号23，bank深度8*1024 */
-    //rc = dpp_mmu_bank_base_addr_set(dev_id, 0x14, 0xc, 8 * 1024);
-    //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set");
-
-    rc = dpp_etm_qmu_init_set_4(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set_4");
-
-    /* 关闭etm映射配置 */
-    etm_bypass.random_bypass_en = 0;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_QMU_RANDOM_BYPASS_ENr,
-                        0,
-                        0,
-                        &etm_bypass);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 场景5：TM共享4组ddr:FTM为1234组ddr的01bank，ETM为1234组ddr 23bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/06/06
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_5(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 depth = 4*1024;
-    ZXIC_UINT32 bank_to_mmu_cfg_map[2] = {2, 3};
-    ZXIC_UINT32 qlist_grp0_bank_data[2] = {0, 1};
-    ZXIC_UINT32 ddr_no[4] = {1, 2, 3, 4};
-
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0};
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_5 start========n");
-
-
-    /* ddr组从qmu到mmu映射,0~3映射成1234 */
-    for (i = 0; i < 4; i++)
-    {
-        ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = ddr_no[i];
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* ddr组从mmu到qmu映射,1234映射成0~3 */
-    for (i = 0; i < 4; i++)
-    {
-        ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-                            0,
-                            ddr_no[i],
-                            &ddr_in_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* bank号从qmu到mmu映射，每组的bank0~1映射成bank2、3 */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            k = j * 8 + i;
-
-            bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i];
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_mmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* bank号从mmu到qmu映射，每组的bank2、3映射成bank0、1 */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, ddr_no[j] , 8);
-            ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id,  ddr_no[j] * 8 , bank_to_mmu_cfg_map[i]);
-            k = ddr_no[j] * 8 + bank_to_mmu_cfg_map[i];
-            bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_qmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    /* random映射ram:配置一个chunk中，bank的轮询顺序 */
-    for (i = 0; i < 16; i++)
-    {
-
-
-        active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 2;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                            0,
-                            i,
-                            &active_to_bank_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    }
-
-
-    /* 首尾深度指针配置 */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            k = j * 8 + i;
-
-            qlist_bhead.bank_vld = 1;
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i), depth);
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i + 1), depth);
-            qlist_bhead.qcfg_qlist_bhead = (j * 2 + i) * depth;
-            qlist_btail.qcfg_qlist_btail = ((j * 2 + i + 1) * depth - 1);
-            qlist_bdep.qcfg_qlist_bdep = depth;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BHEADr,
-                                0,
-                                k,
-                                &qlist_bhead);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BTAILr,
-                                0,
-                                k,
-                                &qlist_btail);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BDEPr,
-                                0,
-                                k,
-                                &qlist_bdep);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (i = 0; i < 64; i++)
-    {
-        qlist_bdep.qcfg_qlist_bdep = depth;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BDEPr,
-                            0,
-                            i,
-                            &qlist_bdep);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8);
-    /* 随机表配置，决定每组bank的轮询顺序 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 64; i++)
-        {
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 2];
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr + j,
-                                0,
-                                i,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (j = 0; j < 64; j++)
-    {
-        qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 4;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_GRPr,
-                            0,
-                            j,
-                            &qcfg_qlist_grp);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_5 END=======\n");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 场景5：TM共享4组ddr:FTM为1234组ddr的01bank，ETM为1234组ddr 23bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/06/06
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_5(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    /* etm mmu基址配置:ddr1234组，bank号23，bank深度4*1024 */
-    //rc = dpp_mmu_bank_base_addr_set(dev_id, 0x1e, 0xc, 4*1024);
-    //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set");
-
-    rc = dpp_etm_qmu_init_set_5(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set_5");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** QMU初始化配置场景6：4组*2bank，MMU实际分配ftm:4,6,7,9组(01bank); etm:4,6,7,9组(23bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/05/13
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_6(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 depth = 4*1024;
-    ZXIC_UINT32 bank_to_mmu_cfg_map[4] = {2, 3};
-    ZXIC_UINT32 qlist_grp0_bank_data[4] = {0, 1};
-    ZXIC_UINT32 ddr_no[4] = {4, 6, 7, 9};
-
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0};
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 start========n");
-
-
-    /* ddr组从qmu到mmu映射,0~3映射成4679 */
-    for (i = 0; i < 4; i++)
-    {
-        ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = ddr_no[i];
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* ddr组从mmu到qmu映射,4679映射成0~3 */
-    for (i = 0; i < 4; i++)
-    {
-        ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-                            0,
-                            ddr_no[i],
-                            &ddr_in_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* bank号从qmu到mmu映射，每组的bank0~1映射成bank2、3 */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            k = j * 8 + i;
-
-            bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i];
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_mmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* bank号从mmu到qmu映射，每组的bank2、3映射成bank0、1 */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, ddr_no[j] , 8);
-            ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id,  ddr_no[j] * 8 , bank_to_mmu_cfg_map[i]);
-            k = ddr_no[j] * 8 + bank_to_mmu_cfg_map[i];
-            bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_qmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    /* random映射ram:配置一个chunk中，bank的轮询顺序 */
-    for (i = 0; i < 16; i++)
-    {
-
-
-        active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 2;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                            0,
-                            i,
-                            &active_to_bank_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    }
-
-
-    /* 首尾深度指针配置 */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            k = j * 8 + i;
-
-            qlist_bhead.bank_vld = 1;
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i), depth);
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i + 1), depth);
-            qlist_bhead.qcfg_qlist_bhead = (j * 2 + i) * depth;
-            qlist_btail.qcfg_qlist_btail = ((j * 2 + i + 1) * depth - 1);
-            qlist_bdep.qcfg_qlist_bdep = depth;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BHEADr,
-                                0,
-                                k,
-                                &qlist_bhead);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BTAILr,
-                                0,
-                                k,
-                                &qlist_btail);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BDEPr,
-                                0,
-                                k,
-                                &qlist_bdep);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (i = 0; i < 64; i++)
-    {
-        qlist_bdep.qcfg_qlist_bdep = depth;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BDEPr,
-                            0,
-                            i,
-                            &qlist_bdep);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8);
-    /* 随机表配置，决定每组bank的轮询顺序 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 64; i++)
-        {
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 2];
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr + j,
-                                0,
-                                i,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (j = 0; j < 64; j++)
-    {
-        qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 4;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_GRPr,
-                            0,
-                            j,
-                            &qcfg_qlist_grp);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 END=======\n");
-
-    return DPP_OK;
-}
-
-
-
-/***********************************************************/
-/** QMU初始化配置场景6：4组*2bank，MMU实际分配ftm:4,6,7,9组(01bank); etm:4,6,7,9组(23bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/05/13
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_6(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    /* etm mmu基址配置:ddr4,6,7,9组，bank号01，bank深度4*1024 */
-    //rc = dpp_mmu_bank_base_addr_set(dev_id, 0x2d0, 0xc, 4*1024);
-    //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set");
-
-    rc = dpp_etm_qmu_init_set_6(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** QMU/MMU初始化配置场景7：每个tm用8组*4bank，MMU实际分配ftm:2-9组(0145bank); etm:2-9组(2367bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/10/14
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_7(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 depth = 1024;
-    ZXIC_UINT32 bank_to_mmu_cfg_map[4] = {2, 3, 6, 7};
-    ZXIC_UINT32 qlist_grp0_bank_data[4] = {0, 1, 2, 3};
-
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0};
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 start========n");
-
-
-    /* ddr组从qmu到mmu映射,0~7映射成2~9 */
-    for (i = 0; i < 8; i++)
-    {
-        ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = (i + 2);
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* ddr组从mmu到qmu映射,2~9映射成0~7 */
-    for (i = 2; i < 10; i++)
-    {
-        ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = (i - 2);
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* bank号从qmu到mmu映射，每组的bank0~3映射成bank2、3、6、7 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            k = j * 8 + i;
-
-            bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i];
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_mmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* bank号从mmu到qmu映射，每组的bank2、3、6、7映射成bank0、1、2、3 */
-    for (j = 2; j < 10; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id,  j , 8);
-            ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id,  j* 8 , bank_to_mmu_cfg_map[i]);
-            k = j * 8 + bank_to_mmu_cfg_map[i];
-            bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_qmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    /* random映射ram:配置一个chunk中，bank的轮询顺序 */
-    for (i = 0; i < 16; i++)
-    {
-
-
-        active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 4;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                            0,
-                            i,
-                            &active_to_bank_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    }
-
-
-    /* 首尾深度指针配置 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 4; i++)
-        {
-            k = j * 8 + i;
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i), depth);
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i + 1), depth);
-            qlist_bhead.bank_vld = 1;
-            qlist_bhead.qcfg_qlist_bhead = (j * 4 + i) * depth;
-            qlist_btail.qcfg_qlist_btail = ((j * 4 + i + 1) * depth - 1);
-            qlist_bdep.qcfg_qlist_bdep = depth;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BHEADr,
-                                0,
-                                k,
-                                &qlist_bhead);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BTAILr,
-                                0,
-                                k,
-                                &qlist_btail);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BDEPr,
-                                0,
-                                k,
-                                &qlist_bdep);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (i = 0; i < 64; i++)
-    {
-        qlist_bdep.qcfg_qlist_bdep = depth;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BDEPr,
-                            0,
-                            i,
-                            &qlist_bdep);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8);
-    /* 随机表配置，决定每组bank的轮询顺序 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 64; i++)
-        {
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 4];
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr + j,
-                                0,
-                                i,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (j = 0; j < 64; j++)
-    {
-        qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 8;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_GRPr,
-                            0,
-                            j,
-                            &qcfg_qlist_grp);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 END=======\n");
-
-    return DPP_OK;
-}
-
-
-
-/***********************************************************/
-/** QMU/MMU初始化配置场景7：每个tm用8组*4bank，MMU实际分配ftm:2-9组(0145bank); etm:2-9组(2367bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/10/14
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_7(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    
-
-    /*关闭随机模式*/
-    rc = dpp_tm_qmu_ddr_random_set(dev_id, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_ddr_random_set");
-
-    /* etm mmu基址配置:ddr2-9组，bank号2367，bank深度1024 */
-    //rc = dpp_mmu_bank_base_addr_set(dev_id, 0x3fc, 0xcc, 1024);
-    //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set");
-
-    rc = dpp_etm_qmu_init_set_7(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** QMU/MMU初始化配置场景8：每个tm用8组*4bank，MMU实际分配ftm:2-9组(01bank); etm:2-9组(23bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/10/14
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_8(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 depth = 2048;
-    ZXIC_UINT32 bank_to_mmu_cfg_map[4] = {2, 3};
-    ZXIC_UINT32 qlist_grp0_bank_data[4] = {0, 1};
-
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0};
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 start========n");
-
-
-    /* ddr组从qmu到mmu映射,0~7映射成2~9 */
-    for (i = 0; i < 8; i++)
-    {
-        ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = (i + 2);
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* ddr组从mmu到qmu映射,2~9映射成0~7 */
-    for (i = 2; i < 10; i++)
-    {
-        ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = (i - 2);
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* bank号从qmu到mmu映射，每组的bank0~1映射成bank2、3 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            k = j * 8 + i;
-
-            bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i];
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_mmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* bank号从mmu到qmu映射，每组的bank2、3映射成bank0、1 */
-    for (j = 2; j < 10; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id,  j, 8);
-            ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id,  j * 8 , bank_to_mmu_cfg_map[i]);
-            k = j * 8 + bank_to_mmu_cfg_map[i];
-            bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_qmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    /* random映射ram:配置一个chunk中，bank的轮询顺序 */
-    for (i = 0; i < 16; i++)
-    {
-
-
-        active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 2;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                            0,
-                            i,
-                            &active_to_bank_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    }
-
-
-    /* 首尾深度指针配置 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            k = j * 8 + i;
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i), depth);
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i + 1), depth);
-            qlist_bhead.bank_vld = 1;
-            qlist_bhead.qcfg_qlist_bhead = (j * 2 + i) * depth;
-            qlist_btail.qcfg_qlist_btail = ((j * 2 + i + 1) * depth - 1);
-            qlist_bdep.qcfg_qlist_bdep = depth;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BHEADr,
-                                0,
-                                k,
-                                &qlist_bhead);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BTAILr,
-                                0,
-                                k,
-                                &qlist_btail);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BDEPr,
-                                0,
-                                k,
-                                &qlist_bdep);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8);
-    /* 随机表配置，决定每组bank的轮询顺序 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 64; i++)
-        {
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 2];
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr + j,
-                                0,
-                                i,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (j = 0; j < 64; j++)
-    {
-        qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 8;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_GRPr,
-                            0,
-                            j,
-                            &qcfg_qlist_grp);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 END=======\n");
-
-    return DPP_OK;
-}
-
-
-
-/***********************************************************/
-/** QMU/MMU初始化配置场景8：每个tm用8组*4bank，MMU实际分配ftm:2-9组(01bank); etm:2-9组(23bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/10/14
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_8(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    /* etm mmu基址配置:ddr2-9组，bank号23，bank深度1024 */
-    //rc = dpp_mmu_bank_base_addr_set(dev_id, 0x3fc, 0xc, 2048);
-    //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set");
-
-    rc = dpp_etm_qmu_init_set_8(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** QMU初始化配置场景9：4组*2bank，MMU实际分配ftm:6,7,8,9组(01bank); etm:6,7,8,9组(23bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/09/28
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_9(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 depth = 4*1024;
-    ZXIC_UINT32 bank_to_mmu_cfg_map[4] = {2, 3};
-    ZXIC_UINT32 qlist_grp0_bank_data[4] = {0, 1};
-    ZXIC_UINT32 ddr_no[4] = {6, 7, 8, 9};
-
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0};
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 start========n");
-
-
-    /* ddr组从qmu到mmu映射,0~3映射成4679 */
-    for (i = 0; i < 4; i++)
-    {
-        ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = ddr_no[i];
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* ddr组从mmu到qmu映射,4679映射成0~3 */
-    for (i = 0; i < 4; i++)
-    {
-        ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-                            0,
-                            ddr_no[i],
-                            &ddr_in_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* bank号从qmu到mmu映射，每组的bank0~1映射成bank2、3 */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            k = j * 8 + i;
-
-            bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i];
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_mmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* bank号从mmu到qmu映射，每组的bank2、3映射成bank0、1 */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(ddr_no[j], 8);
-            ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ddr_no[j] * 8, bank_to_mmu_cfg_map[i]);
-            k = ddr_no[j] * 8 + bank_to_mmu_cfg_map[i];
-
-            bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_qmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    /* random映射ram:配置一个chunk中，bank的轮询顺序 */
-    for (i = 0; i < 16; i++)
-    {
-
-
-        active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 2;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                            0,
-                            i,
-                            &active_to_bank_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    }
-
-
-    /* 首尾深度指针配置 */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            k = j * 8 + i;
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i), depth);
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i + 1), depth);
-            qlist_bhead.bank_vld = 1;
-            qlist_bhead.qcfg_qlist_bhead = (j * 2 + i) * depth;
-            qlist_btail.qcfg_qlist_btail = ((j * 2 + i + 1) * depth - 1);
-            qlist_bdep.qcfg_qlist_bdep = depth;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BHEADr,
-                                0,
-                                k,
-                                &qlist_bhead);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BTAILr,
-                                0,
-                                k,
-                                &qlist_btail);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BDEPr,
-                                0,
-                                k,
-                                &qlist_bdep);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (i = 0; i < 64; i++)
-    {
-        qlist_bdep.qcfg_qlist_bdep = depth;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BDEPr,
-                            0,
-                            i,
-                            &qlist_bdep);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8);
-    /* 随机表配置，决定每组bank的轮询顺序 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 64; i++)
-        {
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 2];
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr + j,
-                                0,
-                                i,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (j = 0; j < 64; j++)
-    {
-        qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 4;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_GRPr,
-                            0,
-                            j,
-                            &qcfg_qlist_grp);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 END=======\n");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** QMU/MMU初始化配置场景8：每个tm用8组*4bank，MMU实际分配ftm:2-9组(01bank); etm:2-9组(23bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/10/14
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_9(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    /* etm mmu基址配置:ddr2-9组，bank号23，bank深度1024 */
-    //rc = dpp_mmu_bank_base_addr_set(dev_id, 0x3fc, 0xc, 2048);
-    //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set");
-
-    rc = dpp_etm_qmu_init_set_8(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** QMU初始化配置场景10：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/12/16
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_10(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 depth = 2*1024;
-    ZXIC_UINT32 bank_to_mmu_cfg_map[8] = {0, 1, 2, 3, 4, 5, 6, 7};
-    ZXIC_UINT32 qlist_grp0_bank_data[8] = {0, 1, 2, 3, 4, 5, 6, 7};
-    ZXIC_UINT32 ddr_no[2] = {1,2};
-
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0};
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 start========n");
-
-
-    /* ddr组从qmu到mmu映射,0~1映射成12 */
-    for (i = 0; i < 2; i++)
-    {
-        ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = ddr_no[i];
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* ddr组从mmu到qmu映射,12映射成0~1 */
-    for (i = 0; i < 2; i++)
-    {
-        ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-                            0,
-                            ddr_no[i],
-                            &ddr_in_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* bank号从qmu到mmu映射，每组的bank0~7映射成bank0-7 */
-    for (j = 0; j < 2; j++)
-    {
-        for (i = 0; i < 8; i++)
-        {
-            k = j * 8 + i;
-
-            bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i];
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_mmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* bank号从mmu到qmu映射，每组的bank0-7映射成bank0-7 */
-    for (j = 0; j < 2; j++)
-    {
-        for (i = 0; i < 8; i++)
-        {
-            ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(ddr_no[j], 8);
-            ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ddr_no[j] * 8, bank_to_mmu_cfg_map[i]);
-            k = ddr_no[j] * 8 + bank_to_mmu_cfg_map[i];
-
-            bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_qmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    /* random映射ram:配置一个chunk中，bank的轮询顺序 */
-    for (i = 0; i < 16; i++)
-    {
-
-
-        active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 8;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                            0,
-                            i,
-                            &active_to_bank_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    }
-
-
-    /* 首尾深度指针配置 */
-    for (j = 0; j < 2; j++)
-    {
-        for (i = 0; i < 8; i++)
-        {
-            k = j * 8 + i;
-
-            qlist_bhead.bank_vld = 1;
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 8 + i), depth);
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 8 + i + 1), depth);
-            qlist_bhead.qcfg_qlist_bhead = (j * 8 + i) * depth;
-            qlist_btail.qcfg_qlist_btail = ((j * 8 + i + 1) * depth - 1);
-            qlist_bdep.qcfg_qlist_bdep = depth;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BHEADr,
-                                0,
-                                k,
-                                &qlist_bhead);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BTAILr,
-                                0,
-                                k,
-                                &qlist_btail);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BDEPr,
-                                0,
-                                k,
-                                &qlist_bdep);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (i = 0; i < 64; i++)
-    {
-        qlist_bdep.qcfg_qlist_bdep = depth;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BDEPr,
-                            0,
-                            i,
-                            &qlist_bdep);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8);
-    /* 随机表配置，决定每组bank的轮询顺序 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 64; i++)
-        {
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 8];
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr + j,
-                                0,
-                                i,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (j = 0; j < 64; j++)
-    {
-        qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 2;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_GRPr,
-                            0,
-                            j,
-                            &qcfg_qlist_grp);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 END=======\n");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** QMU初始化配置场景10：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/12/16
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_10(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    /* etm mmu基址配置:ddr1,2组，bank号0-7，bank深度2*1024 */
-    //rc = dpp_mmu_bank_base_addr_set(dev_id, 0x6, 0xff, 2*1024);
-    //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set");
-
-    rc = dpp_etm_qmu_init_set_10(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set_10");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**场景11：TM共享2组ddr:FTM为ddr_no1、ddr_no2组ddr的01bank，ETM为ddr_no1、ddr_no2组ddr 23bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/06/06
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_11(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no1, ZXIC_UINT32 ddr_no2)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 depth = 8 * 1024;
-    ZXIC_UINT32 ddr_to_mmu_cfg_map[2] = {ddr_no1, ddr_no2};
-    ZXIC_UINT32 bank_to_mmu_cfg_map[2] = {2, 3};
-    ZXIC_UINT32 qlist_grp0_bank_data[2] = {0, 1};
-
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0};
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_11 start========n");
-
-
-    /* ddr组从qmu到mmu映射,0~1映射成ddr_no1 ddr_no2 */
-    for (i = 0; i < 2; i++)
-    {
-        ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = ddr_to_mmu_cfg_map[i];
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* ddr组从mmu到qmu映射,ddr_no1 ddr_no2映射成0~1 */
-    for (i = 0; i < 2; i++)
-    { 
-        ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-                            0,
-                            ddr_to_mmu_cfg_map[i],
-                            &ddr_in_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* bank号从qmu到mmu映射，每组的bank0~1映射成bank2、3 */
-    for (j = 0; j < 2; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            k = j * 8 + i;
-
-            bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i];
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_mmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* bank号从mmu到qmu映射，每组的bank2、3映射成bank0、1 */
-    for (j = 0; j < 2; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(ddr_to_mmu_cfg_map[j], 8);
-            ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ddr_to_mmu_cfg_map[j] * 8, bank_to_mmu_cfg_map[i]);
-            k = ddr_to_mmu_cfg_map[j] * 8 + bank_to_mmu_cfg_map[i];
-
-            bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_qmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    /* random映射ram:配置一个chunk中，bank的轮询顺序 */
-    for (i = 0; i < 16; i++)
-    {
-
-
-        active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 2;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                            0,
-                            i,
-                            &active_to_bank_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    }
-
-
-    /* 首尾深度指针配置 */
-    for (j = 0; j < 2; j++)
-    {
-        for (i = 0; i < 2; i++)
-        {
-            k = j * 8 + i;
-
-            qlist_bhead.bank_vld = 1;
-            ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT((j * 2 + i), depth);
-            qlist_bhead.qcfg_qlist_bhead = (j * 2 + i) * depth;
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 2 + i), depth);
-            qlist_btail.qcfg_qlist_btail = ((j * 2 + i + 1) * depth - 1);
-            qlist_bdep.qcfg_qlist_bdep = depth;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BHEADr,
-                                0,
-                                k,
-                                &qlist_bhead);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BTAILr,
-                                0,
-                                k,
-                                &qlist_btail);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BDEPr,
-                                0,
-                                k,
-                                &qlist_bdep);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (i = 0; i < 64; i++)
-    {
-        qlist_bdep.qcfg_qlist_bdep = depth;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BDEPr,
-                            0,
-                            i,
-                            &qlist_bdep);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8);
-    /* 随机表配置，决定每组bank的轮询顺序 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 64; i++)
-        {
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 2];
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr + j,
-                                0,
-                                i,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (j = 0; j < 64; j++)
-    {
-        qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 2;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_GRPr,
-                            0,
-                            j,
-                            &qcfg_qlist_grp);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_11 END=======\n");
-
-    return DPP_OK;
-}
-
-
-
-/***********************************************************/
-/**场景4：TM共享2组ddr:FTM为ddr_no1,ddr_no2组ddr的01bank，ETM为ddr_no1,ddr_no2组ddr 23bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/06/06
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_11(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no1, ZXIC_UINT32 ddr_no2)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_RANDOM_BYPASS_EN_T etm_bypass = {0};
-    //DPP_FTM_QMU_RANDOM_BYPASS_EN_T ftm_bypass = {0};
-
-    
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT((1U<<ddr_no1), (1U<<ddr_no2));
-
-    /* etm mmu基址配置:ddr_no1,ddr_no2组，bank号23，bank深度8*1024 */
-    //rc = dpp_mmu_bank_base_addr_set(dev_id, ((1U<<ddr_no1)+(1U<<ddr_no2))&0xff, 0xc, 8 * 1024);
-    //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set");
-
-    rc = dpp_etm_qmu_init_set_11(dev_id, ddr_no1, ddr_no2);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set_11");
-
-    /* 关闭etm映射配置 */
-    etm_bypass.random_bypass_en = 0;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_QMU_RANDOM_BYPASS_ENr,
-                        0,
-                        0,
-                        &etm_bypass);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    return DPP_OK;
-}
-
-
-
-
-/***********************************************************/
-/** 
-QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(4567bank); etm:0-9中指定组(0123bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/4/14
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_12(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ddr_no, 0, 9);
-
-    /*关闭随机模式*/
-    rc = dpp_tm_qmu_ddr_random_set(dev_id, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_ddr_random_set");
-
-    /* etm mmu基址配置:ddr指定ddr_no组，bank号0123，bank深度8K */
-    //rc = dpp_mmu_bank_base_addr_set(dev_id, 1U << ddr_no, 0xf, 8 * 1024);
-    //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set");
-
-    rc = dpp_etm_qmu_init_set_15(dev_id, ddr_no);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set_15");
-
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** QMU初始化配置场景13：TM独享4组ddr:FTM为指定4组ddr的0~7bank，
-                                      ETM为指定4组ddr 0~7bank
-* @param   dev_id   设备编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_13(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 depth = 1024;
-    ZXIC_UINT32 ddr_no_data[4] = {0};
-    ZXIC_UINT32 qlist_grp0_bank_data[8] = {0, 1, 2, 3, 4, 5, 6, 7};
-
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0};
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set starting++++++\n");
-
-    /*将ddr_no中的编号取出存入数组中，如传入0x6789 依次存为 6 7 8 9*/
-    ddr_no_data[3] = ddr_no & 0xf;
-    ddr_no_data[2] = (ddr_no >> 4) & 0xf;
-    ddr_no_data[1] = (ddr_no >> 8) & 0xf;
-    ddr_no_data[0] = (ddr_no >> 12) & 0xf;
-
-    /* ddr组从qmu到mmu映射,0~3映射成ddr_no */
-    for (i = 0; i < 4; i++)
-    {
-        ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = ddr_no_data[i];
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* ddr组从mmu到qmu映射,ddr_no映射成0~3 */
-    for (i = 0; i < 4; i++)
-    {
-        ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-                            0,
-                            ddr_no_data[i],
-                            &ddr_in_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* bank号从qmu到mmu映射，组0~3的bank0-7映射成bank0-7 */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 8; i++)
-        {
-            k = j * 8 + i;
-
-            bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_mmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* bank号从mmu到qmu映射，组ddr_no的bank0-7映射成bank0-7 */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 8; i++)
-        {
-            ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(ddr_no_data[j], 8);
-            ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ddr_no_data[j] * 8, i);
-            k = ddr_no_data[j] * 8 + i;
-
-            bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_qmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    /* random映射ram:配置一个chunk中，bank的轮询顺序 */
-    for (i = 0; i < 16; i++)
-    {
-        active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 8;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                            0,
-                            i,
-                            &active_to_bank_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* 首尾深度指针配置:j为4组循环 */
-    for (j = 0; j < 4; j++)
-    {
-        for (i = 0; i < 8; i++)
-        {
-            k = j * 8 + i;
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 8 + i), depth);
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 8 + i + 1), depth);
-            qlist_bhead.bank_vld = 1;
-            qlist_bhead.qcfg_qlist_bhead = (j * 8 + i) * depth;
-            qlist_btail.qcfg_qlist_btail = ((j * 8 + i + 1) * depth - 1);
-            qlist_bdep.qcfg_qlist_bdep = depth;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BHEADr,
-                                0,
-                                k,
-                                &qlist_bhead);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BTAILr,
-                                0,
-                                k,
-                                &qlist_btail);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BDEPr,
-                                0,
-                                k,
-                                &qlist_bdep);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-    for (i = 0; i < 64; i++)
-    {
-        qlist_bdep.qcfg_qlist_bdep = depth;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BDEPr,
-                            0,
-                            i,
-                            &qlist_bdep);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8);
-    /* 随机表配置，决定ddr内bank的轮询顺序:使用几组ddr需要配置几组 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 64; i++)
-        {
-
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 8];
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr + j,
-                                0,
-                                i,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        }
-    }
-
-    for (j = 0; j < 64; j++)
-    {
-        qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 4;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_GRPr,
-                            0,
-                            j,
-                            &qcfg_qlist_grp);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "++++++dpp_etm_qmu_init_set end++++++\n");
-
-    return DPP_OK;
-}
-
-
-
-
-/***********************************************************/
-/** QMU/MMU初始化配置场景13：TM独享4组ddr:FTM为指定4组ddr的0~7bank 
-                                          ETM为指定4组ddr的0-7bank
-*   MMU开启rotatjon
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2016/11/17
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_13(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_no)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_STATUS ddr_no_temp = 0;
-    DPP_ETM_QMU_RANDOM_BYPASS_EN_T etm_bypass = {0};
-    //DPP_FTM_QMU_RANDOM_BYPASS_EN_T ftm_bypass = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ((ddr_no >> 0) & 0xfU), 0, 9);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ((ddr_no >> 4) & 0xfU), 0, 9);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ((ddr_no >> 8) & 0xfU), 0, 9);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ((ddr_no >> 12) & 0xfU), 0, 9);
-
-    ddr_no_temp = ((1U << (ddr_no & 0xfU)) + (1U << ((ddr_no >> 4) & 0xfU))+   \
-             (1U << ((ddr_no >> 8) & 0xfU)) + (1U << ((ddr_no >> 12) & 0xfU))) & 0x3ff;
-
-
-    /* etm mmu基址配置:ddr_no中的4组，bank号0-7，bank深度1024 */
-    //rc = dpp_mmu_bank_base_addr_set(dev_id, ddr_no_temp, 0xff, 1024);
-    //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set");
-
-    rc = dpp_etm_qmu_init_set_13(dev_id, ddr_no);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set_13");
-
-    /* 关闭etm映射配置 */
-    etm_bypass.random_bypass_en = 0;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_QMU_RANDOM_BYPASS_ENr,
-                        0,
-                        0,
-                        &etm_bypass);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    return DPP_OK;
-}
-
-
-
-/***********************************************************/
-/** QMU/MMU初始化配置场景14：每个tm只用1组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/4/14
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_14(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 depth = 4 * 1024;
-    ZXIC_UINT32 bank_to_mmu_cfg_map[8] = {0, 1, 2, 3, 4, 5, 6, 7};
-    ZXIC_UINT32 qlist_grp0_bank_data[8] = {0, 1, 2, 3, 4, 5, 6, 7};
-
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0};
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 start========n");
-
-
-    /* ddr组从qmu到mmu映射,将0映射成etm_ddr_no */
-    i = 0;
-    ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = etm_ddr_no;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-                       0,
-                       i,
-                       &ddr_in_mmu_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    /* ddr组从mmu到qmu映射,etm_ddr_no映射成0 */
-    i = etm_ddr_no;
-    ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = 0;
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-                       0,
-                       i,
-                       &ddr_in_qmu_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    /* bank号从qmu到mmu映射，每组的bank0-7映射成bank0-7 */
-    j = 0;
-
-    for (i = 0; i < 8; i++)
-    {
-        k = j * 8 + i;
-        bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i];
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-                            0,
-                            k,
-                            &bank_to_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* bank号从mmu到qmu映射，每组的bank0-7映射成bank0-7 */
-    j = etm_ddr_no;
-
-    for (i = 0; i < 8; i++)
-    {
-        ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(j, 8);
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(j * 8, bank_to_mmu_cfg_map[i]);
-        k = j * 8 + bank_to_mmu_cfg_map[i];
-        bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-                            0,
-                            k,
-                            &bank_to_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* random映射ram:配置一个chunk中，bank的轮询顺序 */
-    for (i = 0; i < 16; i++)
-    {
-        active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 8;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                            0,
-                            i,
-                            &active_to_bank_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* 首尾深度指针配置 */
-    j = 0;
-
-    for (i = 0; i < 8; i++)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 8 + i), depth);
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 8 + i + 1), depth);
-        k = j * 8 + i;
-        qlist_bhead.bank_vld = 1;
-        qlist_bhead.qcfg_qlist_bhead = (j * 8 + i) * depth;
-        qlist_btail.qcfg_qlist_btail = ((j * 8 + i + 1) * depth - 1);
-        qlist_bdep.qcfg_qlist_bdep = depth;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BHEADr,
-                            0,
-                            k,
-                            &qlist_bhead);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BTAILr,
-                            0,
-                            k,
-                            &qlist_btail);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BDEPr,
-                            0,
-                            k,
-                            &qlist_bdep);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    for (i = 0; i < 64; i++)
-    {
-        qlist_bdep.qcfg_qlist_bdep = depth;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BDEPr,
-                            0,
-                            i,
-                            &qlist_bdep);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8);
-    /* 随机表配置，决定每组bank的轮询顺序 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 64; i++)
-        {
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 8];
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr + j,
-                                0,
-                                i,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (j = 0; j < 64; j++)
-    {
-        qcfg_qlist_grp.qcfg_qlist_grp_wr = 0;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_GRPr,
-                            0,
-                            j,
-                            &qcfg_qlist_grp);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 END=======\n");
-
-    return DPP_OK;
-}
-
-
-
-/***********************************************************/
-/** QMU/MMU初始化配置场景14：每个tm只用1组*8bank，MMU实际分配ftm:0-9中指定组(0-7bank); etm:0-9中指定组(0-7bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/4/14
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_14(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no, ZXIC_UINT32 ftm_ddr_no)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 etm_ddr_no_temp = 0;   /*ETM使用的ddr,bit位表示*/
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, etm_ddr_no, 0, 9);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ftm_ddr_no, 0, 9);
-
-    /*etm ftm不能使用同一组ddr*/
-    if (etm_ddr_no == ftm_ddr_no)
-    {
-        ZXIC_COMM_PRINT("dpp_tm_qmu_init_set_15: etm_ddr_no can't equal to ftm_ddr_no!!!\n");
-    }
-
-    ZXIC_COMM_ASSERT(etm_ddr_no != ftm_ddr_no);
-
-    /*将etm ftm使用的ddr号转换成对应的bit位,bit[0-9]每bit代表一组ddr */
-    etm_ddr_no_temp = 0x1u << etm_ddr_no;
-
-    /*开启随机模式*/
-    rc = dpp_tm_qmu_ddr_random_set(dev_id, 1);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_ddr_random_set");
-
-    /* etm mmu基址配置:ddr指定etm_ddr_no组，bank号0-7bank，bank深度4K */
-    //rc = dpp_mmu_bank_base_addr_set(dev_id, etm_ddr_no_temp, 0xff, 4 * 1024);
-    //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set");
-
-    rc = dpp_etm_qmu_init_set_14(dev_id, etm_ddr_no);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set");
-    
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(0123bank); etm:0-9中指定组(0123bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/4/14
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_15(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 depth = 8 * 1024;
-    ZXIC_UINT32 bank_to_mmu_cfg_map[4] = {0, 1, 2, 3};
-    ZXIC_UINT32 qlist_grp0_bank_data[4] = {0, 1, 2, 3};
-
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0};
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 start========n");
-
-
-
-    /* ddr组从qmu到mmu映射,将0映射成etm_ddr_no */
-    i = 0;
-    ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = etm_ddr_no;
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-                       0,
-                       i,
-                       &ddr_in_mmu_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    /* ddr组从mmu到qmu映射,etm_ddr_no映射成0 */
-    i = etm_ddr_no;
-    ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = 0;
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-                       0,
-                       i,
-                       &ddr_in_qmu_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    /* bank号从qmu到mmu映射，每组的bank0123映射成bank0123 */
-    j = 0;
-
-    for (i = 0; i < 4; i++)
-    {
-        k = j * 8 + i;
-        bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i];
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-                            0,
-                            k,
-                            &bank_to_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* bank号从mmu到qmu映射，每组的bank0123映射成bank0123 */
-    j = etm_ddr_no;
-
-    for (i = 0; i < 4; i++)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id,  j, 8);
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id,  j * 8 , bank_to_mmu_cfg_map[i]);
-        k = j * 8 + bank_to_mmu_cfg_map[i];
-        bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-                            0,
-                            k,
-                            &bank_to_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* random映射ram:配置一个chunk中，bank的轮询顺序 */
-    for (i = 0; i < 16; i++)
-    {
-        active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 4;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                            0,
-                            i,
-                            &active_to_bank_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* 首尾深度指针配置 */
-    j = 0;
-
-    for (i = 0; i < 4; i++)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i), depth);
-        ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 4 + i + 1), depth);
-        k = j * 8 + i;
-        qlist_bhead.bank_vld = 1;
-        qlist_bhead.qcfg_qlist_bhead = (j * 4 + i) * depth;
-        qlist_btail.qcfg_qlist_btail = ((j * 4 + i + 1) * depth - 1);
-        qlist_bdep.qcfg_qlist_bdep = depth;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BHEADr,
-                            0,
-                            k,
-                            &qlist_bhead);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BTAILr,
-                            0,
-                            k,
-                            &qlist_btail);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BDEPr,
-                            0,
-                            k,
-                            &qlist_bdep);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    for (i = 0; i < 64; i++)
-    {
-        qlist_bdep.qcfg_qlist_bdep = depth;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BDEPr,
-                            0,
-                            i,
-                            &qlist_bdep);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8);
-    /* 随机表配置，决定每组bank的轮询顺序 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 64; i++)
-        {
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 4];
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr + j,
-                                0,
-                                i,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (j = 0; j < 64; j++)
-    {
-        qcfg_qlist_grp.qcfg_qlist_grp_wr = 0;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_GRPr,
-                            0,
-                            j,
-                            &qcfg_qlist_grp);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_1 END=======\n");
-
-    return DPP_OK;
-}
-
-
-
-
-/***********************************************************/
-/** QMU/MMU初始化配置场景15：每个tm只用1组*4bank，MMU实际分配ftm:0-9中指定组(0123bank); etm:0-9中指定组(0123bank)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/4/14
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_15(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no, ZXIC_UINT32 ftm_ddr_no)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 etm_ddr_no_temp = 0;   /*ETM使用的ddr,bit位表示*/
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, etm_ddr_no, 0, 9);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ftm_ddr_no, 0, 9);
-
-    /*etm ftm不能使用同一组ddr*/
-    if (etm_ddr_no == ftm_ddr_no)
-    {
-        ZXIC_COMM_PRINT("dpp_tm_qmu_init_set_15: etm_ddr_no can't equal to ftm_ddr_no!!!\n");
-    }
-
-    ZXIC_COMM_ASSERT(etm_ddr_no == ftm_ddr_no);
-
-    /*将etm ftm使用的ddr号转换成对应的bit位,bit[0-9]每bit代表一组ddr */
-    etm_ddr_no_temp = 0x1u << etm_ddr_no;
-
-    /*关闭随机模式*/
-    rc = dpp_tm_qmu_ddr_random_set(dev_id, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_ddr_random_set");
-
-    /* etm mmu基址配置:ddr指定etm_ddr_no组，bank号0123，bank深度8K */
-    //rc = dpp_mmu_bank_base_addr_set(dev_id, etm_ddr_no_temp, 0xf, 8 * 1024);
-    //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set");
-
-    rc = dpp_etm_qmu_init_set_15(dev_id, etm_ddr_no);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set");
-
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** QMU初始化配置场景16：独享2组*8bank，MMU实际分配etm_ddr_no; etm or ftm使用0-7bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/12/16
-************************************************************/
-DPP_STATUS dpp_etm_qmu_init_set_16(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 k = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    ZXIC_UINT32 depth = 2*1024;
-    ZXIC_UINT32 bank_to_mmu_cfg_map[8] = {0, 1, 2, 3, 4, 5, 6, 7};
-    ZXIC_UINT32 qlist_grp0_bank_data[8] = {0, 1, 2, 3, 4, 5, 6, 7};
-    ZXIC_UINT32 ddr_no[2] = {(etm_ddr_no>>4)&0xf, etm_ddr_no & 0xf};
-
-
-    DPP_ETM_QMU_QCFG_QLIST_BDEP_T qlist_bdep = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BHEAD_T qlist_bhead = {0};
-    DPP_ETM_QMU_QCFG_QLIST_BTAIL_T qlist_btail = {0};
-
-    DPP_ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFG_T active_to_bank_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_MMU_CFG_T ddr_in_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_DDR_IN_QMU_CFG_T ddr_in_qmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_MMU_CFG_T bank_to_mmu_cfg = {0};
-    DPP_ETM_QMU_CFGMT_BANK_TO_QMU_CFG_T bank_to_qmu_cfg = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP0_BANK_T qlist_grp0_bank = {0};
-    DPP_ETM_QMU_QCFG_QLIST_GRP_T qcfg_qlist_grp = {0};
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_16 start========n");
-
-
-    /* ddr组从qmu到mmu映射,0~1映射成12 */
-    for (i = 0; i < 2; i++)
-    {
-        ddr_in_mmu_cfg.cfgmt_ddr_in_mmu_cfg = ddr_no[i];
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-                            0,
-                            i,
-                            &ddr_in_mmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    /* ddr组从mmu到qmu映射,12映射成0~1 */
-    for (i = 0; i < 2; i++)
-    {
-        ddr_in_qmu_cfg.cfgmt_ddr_in_qmu_cfg = i;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-                            0,
-                            ddr_no[i],
-                            &ddr_in_qmu_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    /* bank号从qmu到mmu映射，每组的bank0~7映射成bank0-7 */
-    for (j = 0; j < 2; j++)
-    {
-        for (i = 0; i < 8; i++)
-        {
-            k = j * 8 + i;
-
-            bank_to_mmu_cfg.cfgmt_bank_in_mmu_cfg = bank_to_mmu_cfg_map[i];
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_mmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-
-    /* bank号从mmu到qmu映射，每组的bank0-7映射成bank0-7 */
-    for (j = 0; j < 2; j++)
-    {
-        for (i = 0; i < 8; i++)
-        {
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, ddr_no[j], 8);
-            ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ddr_no[j] * 8, bank_to_mmu_cfg_map[i]);
-            k = ddr_no[j] * 8 + bank_to_mmu_cfg_map[i];
-
-            bank_to_qmu_cfg.cfgmt_bank_in_qmu_cfg = i;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-                                0,
-                                k,
-                                &bank_to_qmu_cfg);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    /* random映射ram:配置一个chunk中，bank的轮询顺序 */
-    for (i = 0; i < 16; i++)
-    {
-
-
-        active_to_bank_cfg.cfgmt_active_to_bank_cfg = i % 8;
-
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-                            0,
-                            i,
-                            &active_to_bank_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    }
-
-
-    /* 首尾深度指针配置 */
-    for (j = 0; j < 2; j++)
-    {
-        for (i = 0; i < 8; i++)
-        {
-            k = j * 8 + i;
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 8 + i), depth);
-            ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(dev_id, (j * 8 + i + 1), depth);
-            qlist_bhead.bank_vld = 1;
-            qlist_bhead.qcfg_qlist_bhead = (j * 8 + i) * depth;
-            qlist_btail.qcfg_qlist_btail = ((j * 8 + i + 1) * depth - 1);
-            qlist_bdep.qcfg_qlist_bdep = depth;
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BHEADr,
-                                0,
-                                k,
-                                &qlist_bhead);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BTAILr,
-                                0,
-                                k,
-                                &qlist_btail);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_BDEPr,
-                                0,
-                                k,
-                                &qlist_bdep);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (i = 0; i < 64; i++)
-    {
-        qlist_bdep.qcfg_qlist_bdep = depth;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_BDEPr,
-                            0,
-                            i,
-                            &qlist_bdep);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_QMU_QCFG_QLIST_GRP0_BANKr, 8);
-    /* 随机表配置，决定每组bank的轮询顺序 */
-    for (j = 0; j < 8; j++)
-    {
-        for (i = 0; i < 64; i++)
-        {
-            qlist_grp0_bank.qcfg_qlist_grp0_bank_wr = qlist_grp0_bank_data[i % 8];
-            rc  = dpp_reg_write(dev_id,
-                                ETM_QMU_QCFG_QLIST_GRP0_BANKr + j,
-                                0,
-                                i,
-                                &qlist_grp0_bank);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-    }
-
-    for (j = 0; j < 64; j++)
-    {
-        qcfg_qlist_grp.qcfg_qlist_grp_wr = j % 2;
-        rc  = dpp_reg_write(dev_id,
-                            ETM_QMU_QCFG_QLIST_GRPr,
-                            0,
-                            j,
-                            &qcfg_qlist_grp);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-    rc = dpp_tm_qmu_cfg_done_set(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_cfg_done_set");
-
-    ZXIC_COMM_TRACE_DEV_DEBUG(dev_id, "========dpp_etm_qmu_init_set_16 END=======\n");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** QMU初始化配置场景16：独享2组*8bank，MMU实际分配1,2; etm or ftm使用0-7bank
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/12/16
-************************************************************/
-DPP_STATUS dpp_tm_qmu_init_set_16(ZXIC_UINT32 dev_id, ZXIC_UINT32 etm_ddr_no, ZXIC_UINT32 ftm_ddr_no)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, etm_ddr_no, 0, 0xff);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ftm_ddr_no, 0, 0xff);
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, (1UL<<(etm_ddr_no>>4&0xf)), (1UL<<(etm_ddr_no&0xf)));
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, (1UL<<(ftm_ddr_no>>4&0xf)), (1UL<<(ftm_ddr_no&0xf)));
-
-    /* etm mmu基址配置:ddr1,2组，bank号0-7，bank深度2*1024 */
-    //rc = dpp_mmu_bank_base_addr_set(dev_id, ((1UL<<(etm_ddr_no>>4&0xf))+(1UL<<(etm_ddr_no&0xf)))&0x3ff, 0xff, 2*1024);
-    //ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_mmu_bank_base_addr_set");
-
-    rc = dpp_etm_qmu_init_set_16(dev_id, etm_ddr_no);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_etm_qmu_init_set_16");
-
-    return DPP_OK;
-}
-
-#endif
-#endif
-
-
-#if ZXIC_REAL("TM_TMMU")
-
-#if 0
-/***********************************************************/
-/** TMMU TM纯片内模式配置
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   imem_en   1纯片内
-*
-* @return
-* @remark  说明：高有效，表示使能打开，TMMU不会再发起对MMU的读写操作，用户需要保证Cache PD全部命中。
-* @see
-* @author  wush      @date  2017/10/14
-************************************************************/
-DPP_STATUS dpp_tm_tmmu_imem_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 imem_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_ETM_TMMU_CFGMT_TM_PURE_IMEM_EN_T pure_imem_t = {0};
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, imem_en, 0, 1);
-
-    pure_imem_t.cfgmt_tm_pure_imem_en = imem_en;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_TMMU_CFGMT_TM_PURE_IMEM_ENr,
-                        0,
-                        0,
-                        &pure_imem_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** TMMU TM纯片内模式配置获取
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_imem_en  1纯片内
-*
-* @return
-* @remark  无
-* @see
-* @author  wush      @date  2017/10/14
-************************************************************/
-DPP_STATUS dpp_tm_tmmu_imem_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_imem_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_ETM_TMMU_CFGMT_TM_PURE_IMEM_EN_T pure_imem_t = {0};
-    
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_imem_en);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_TMMU_CFGMT_TM_PURE_IMEM_ENr,
-                       0,
-                       0,
-                       &pure_imem_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    *p_imem_en = pure_imem_t.cfgmt_tm_pure_imem_en;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** TMMU 强制DDR RDY配置
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   ddr_force_rdy   1、如果bit【0】配置为1，则QMU看到的DDR0 RDY一直为1。
-                           2、bit【0】代表DDR0，bit【7】代表DDR7。
-                           3、纯片内模式需要配置为8'hff，排除DDR干扰。
-*
-* @return
-* @remark
-* @see
-* @author  wush      @date  2017/10/14
-************************************************************/
-DPP_STATUS dpp_tm_tmmu_ddr_force_rdy_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ddr_force_rdy)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFG_T ddr_force_rdy_t = {0};
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, ddr_force_rdy, 0, 0x3FF);
-
-
-    ddr_force_rdy_t.cfgmt_force_ddr_rdy_cfg = ddr_force_rdy;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFGr,
-                        0,
-                        0,
-                        &ddr_force_rdy_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** TMMU 强制DDR RDY配置获取
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_ddr_force_rdy  1、如果bit【0】配置为1，则QMU看到的DDR0 RDY一直为1。
-                            2、bit【0】代表DDR0，bit【7】代表DDR7。
-                            3、纯片内模式需要配置为8'hff，排除DDR干扰。
-*
-* @return
-* @remark  无
-* @see
-* @author  wush      @date  2017/10/14
-************************************************************/
-DPP_STATUS dpp_tm_tmmu_ddr_force_rdy_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_ddr_force_rdy)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFG_T ddr_force_rdy_t = {0};
-    
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_ddr_force_rdy);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFGr,
-                       0,
-                       0,
-                       &ddr_force_rdy_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    *p_ddr_force_rdy = ddr_force_rdy_t.cfgmt_force_ddr_rdy_cfg;
-
-    return DPP_OK;
-}
-
-#endif
-#endif
-
-
-#if ZXIC_REAL("TM_CRDT")
-
-#if 0
-/***********************************************************/
-/** crdt ram初始化
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/22
-************************************************************/
-DPP_STATUS dpp_tm_crdt_ram_init(ZXIC_UINT32 dev_id)
-{
-
-
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 read_times = 0;
-    DPP_ETM_CRDT_CRDT_CFG_RAM_INIT_T crdt_ram_cfg_init_t = {0};
-    DPP_ETM_CRDT_CRDT_STA_RAM_INIT_T crdt_ram_sta_init_t = {0};
-
-    /**RAM初始化**/
-    crdt_ram_cfg_init_t.cfg_ram_init_en = 1;
-    rc = dpp_reg_write(dev_id,
-                       ETM_CRDT_CRDT_CFG_RAM_INITr,
-                       0,
-                       0,
-                       &crdt_ram_cfg_init_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    crdt_ram_sta_init_t.sta_ram_init_en = 1;
-    rc = dpp_reg_write(dev_id,
-                       ETM_CRDT_CRDT_STA_RAM_INITr,
-                       0,
-                       0,
-                       &crdt_ram_sta_init_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-
-    /**初始化done确认**/
-    do
-    {
-        rc = dpp_reg_read(dev_id,
-                          ETM_CRDT_CRDT_CFG_RAM_INITr,
-                          0,
-                          0,
-                          &crdt_ram_cfg_init_t);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        rc = dpp_reg_read(dev_id,
-                          ETM_CRDT_CRDT_STA_RAM_INITr,
-                          0,
-                          0,
-                          &crdt_ram_sta_init_t);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-        read_times++;
-        zxic_comm_usleep(100);
-
-    }
-    while (0 == crdt_ram_cfg_init_t.cfg_ram_init_done  || 0 == crdt_ram_sta_init_t.sta_ram_init_done);
-
-    ZXIC_COMM_PRINT("wait_crdt_ram_done_times=%d\n",read_times);
-    ZXIC_COMM_PRINT("crdt_ram_cfg_init_t.cfg_ram_init_done=%d, crdt_ram_sta_init_t.sta_ram_init_done=%d\n",
-            crdt_ram_cfg_init_t.cfg_ram_init_done,crdt_ram_sta_init_t.sta_ram_init_done);
-
-    return DPP_OK;
-
-}
-
-#endif
-/***********************************************************/
-/** 分配etm-FQ类型调度器资源：fq/fq2/fq4/fq8 个数，(共16K= 16384)
-* @param   dev_id   设备编号
-* @param   fq_num   FQ调度器个数，须是8的倍数
-* @param   fq2_num  FQ2调度器个数，须是4的倍数
-* @param   fq4_num  FQ4调度器个数，须是2的倍数
-* @param   fq8_num  FQ8调度器个数
-*          调度器总数不能超过：16K= 16384
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/26
-************************************************************/
-DPP_STATUS dpp_etm_crdt_fq_set(DPP_DEV_T *dev,
-                               ZXIC_UINT32 fq_num,
-                               ZXIC_UINT32 fq2_num,
-                               ZXIC_UINT32 fq4_num,
-                               ZXIC_UINT32 fq8_num)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 total_fq_num = 0;
-    DPP_ETM_CRDT_TH_WFQ_FQ_T   etm_crdt_th_wfqfq_t = {0};
-    DPP_ETM_CRDT_TH_WFQ2_FQ2_T etm_crdt_th_wfqfq2_t = {0};
-    DPP_ETM_CRDT_TH_WFQ4_FQ4_T etm_crdt_th_wfqfq4_t = {0};
-    ZXIC_UINT32 th_wfq_fq_index = ETM_CRDT_TH_WFQ_FQr;
-    ZXIC_UINT32 th_wfq_fq2_index = ETM_CRDT_TH_WFQ2_FQ2r;
-    ZXIC_UINT32 th_wfq_fq4_index = ETM_CRDT_TH_WFQ4_FQ4r;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    /* 参数合法性检查:fq调度器总数校验 */
-    ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev),  fq2_num , 2);
-    ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev),  fq4_num , 4);
-    ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev),  fq8_num , 8);
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev),  fq_num , fq2_num * 2);
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev),  fq_num + fq2_num * 2 , fq4_num * 4);
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev),  fq_num + fq2_num * 2 + fq4_num * 4 , fq8_num * 8);
-    
-    total_fq_num = (fq_num + fq2_num * 2 + fq4_num * 4 + fq8_num * 8);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), total_fq_num, 0, DPP_ETM_FQ_NUM);
-
-    /* 各调度器数整齐性校验 */
-    if ((fq_num != 0 && fq_num % 8 != 0) || (fq2_num != 0 && fq2_num % 4 != 0) || (fq4_num != 0 && fq4_num % 2 != 0))
-    {
-        //ZXIC_COMM__TRACE_ERR("Bad parameter: sp_num or wfq_num %8 != 0 !");
-        return DPP_ERR;
-    }
-
-
-    /* 开始调度器阈值配置：th_fq参数配置：th_fq = fq_num/8 */
-    rc  = dpp_reg_read(dev,
-                       th_wfq_fq_index,
-                       0,
-                       0,
-                       &etm_crdt_th_wfqfq_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    etm_crdt_th_wfqfq_t.th_fq = (fq_num / 8);
-    rc  = dpp_reg_write(dev,
-                        th_wfq_fq_index,
-                        0,
-                        0,
-                        &etm_crdt_th_wfqfq_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    /* th_fq2参数配置：th_fq2 = (th_fq + fq2_num/4) */
-    rc  = dpp_reg_read(dev,
-                       th_wfq_fq2_index,
-                       0,
-                       0,
-                       &etm_crdt_th_wfqfq2_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    etm_crdt_th_wfqfq2_t.th_fq2 = (etm_crdt_th_wfqfq_t.th_fq + fq2_num / 4);
-    rc  = dpp_reg_write(dev,
-                        th_wfq_fq2_index,
-                        0,
-                        0,
-                        &etm_crdt_th_wfqfq2_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    /* th_fq4参数配置：th_fq4 = (th_fq2 + fq4_num/2) */
-    rc  = dpp_reg_read(dev,
-                       th_wfq_fq4_index,
-                       0,
-                       0,
-                       &etm_crdt_th_wfqfq4_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    etm_crdt_th_wfqfq4_t.th_fq4 = (etm_crdt_th_wfqfq2_t.th_fq2 + fq4_num /  2);
-    rc  = dpp_reg_write(dev,
-                        th_wfq_fq4_index,
-                        0,
-                        0,
-                        &etm_crdt_th_wfqfq4_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 分配TM-SP/WFQ类型调度器资源：sp/wfq/wfq2/wfq4/wfq8 个数，（etm共9K=9216,ftm共1920个）
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   sp_num   SP调度器个数，须是8的倍数
-* @param   wfq_num  WFQ调度器个数，须是8的倍数
-* @param   wfq2_num  WFQ2调度器个数，须是4的倍数
-* @param   wfq4_num  WFQ4调度器个数，须是2的倍数
-* @param   wfq8_num  WFQ8调度器个数
-*          调度器总数不能超过：ETM= 9216; FTM= 1920
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/26
-************************************************************/
-DPP_STATUS dpp_tm_crdt_wfqsp_set(DPP_DEV_T *dev,
-                                 ZXIC_UINT32 sp_num,
-                                 ZXIC_UINT32 wfq_num,
-                                 ZXIC_UINT32 wfq2_num,
-                                 ZXIC_UINT32 wfq4_num,
-                                 ZXIC_UINT32 wfq8_num)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 total_wfqsp_num = 0;
-    DPP_ETM_CRDT_TH_SP_T       etm_crdt_th_sp_t = {0};
-    DPP_ETM_CRDT_TH_WFQ_FQ_T   etm_crdt_th_wfqfq_t = {0};
-    DPP_ETM_CRDT_TH_WFQ2_FQ2_T etm_crdt_th_wfqfq2_t = {0};
-    DPP_ETM_CRDT_TH_WFQ4_FQ4_T etm_crdt_th_wfqfq4_t = {0};
-    ZXIC_UINT32 th_sp_index = ETM_CRDT_TH_SPr;
-    ZXIC_UINT32 th_wfq_fq_index = ETM_CRDT_TH_WFQ_FQr;
-    ZXIC_UINT32 th_wfq_fq2_index = ETM_CRDT_TH_WFQ2_FQ2r;
-    ZXIC_UINT32 th_wfq_fq4_index = ETM_CRDT_TH_WFQ4_FQ4r;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    /* 参数合法性检查 */    
-    ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev),  wfq2_num , 2);
-    ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev),  wfq4_num , 4);
-    ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev),  wfq8_num , 8);
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), sp_num , wfq_num);
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), sp_num + wfq_num , wfq2_num * 2);
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), sp_num + wfq_num + wfq2_num * 2 , wfq4_num * 4);
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), sp_num + wfq_num + wfq2_num * 2 + wfq4_num * 4 , wfq8_num * 8);
-    /* 调度器总数校验 */
-    total_wfqsp_num = (sp_num + wfq_num + wfq2_num * 2 + wfq4_num * 4 + wfq8_num * 8);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), total_wfqsp_num, 0, DPP_ETM_WFQSP_NUM);
-
-    /* 各调度器数整齐性校验 */
-    if ((sp_num != 0 && sp_num % 8 != 0) || (wfq_num != 0 && wfq_num % 8 != 0) ||
-        (wfq2_num != 0 && wfq2_num % 4 != 0) || (wfq4_num != 0 && wfq4_num % 2 != 0))
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Bad parameter: sp_num or wfq_num mod 8 != 0 !\n");
-        return DPP_ERR;
-    }
-
-    th_sp_index = ETM_CRDT_TH_SPr;
-    th_wfq_fq_index = ETM_CRDT_TH_WFQ_FQr;
-    th_wfq_fq2_index = ETM_CRDT_TH_WFQ2_FQ2r;
-    th_wfq_fq4_index = ETM_CRDT_TH_WFQ4_FQ4r;
-
-    /* 开始调度器阈值配置：th_sp参数配置：th_sp=      sp_num/8 */
-    rc  = dpp_reg_read(dev,
-                       th_sp_index,
-                       0,
-                       0,
-                       &etm_crdt_th_sp_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    etm_crdt_th_sp_t.th_sp = (sp_num / 8);
-    rc  = dpp_reg_write(dev,
-                        th_sp_index,
-                        0,
-                        0,
-                        &etm_crdt_th_sp_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    /* th_wfq参数配置：th_wfq = (th_sp + wfq_num/8)       */
-    rc  = dpp_reg_read(dev,
-                       th_wfq_fq_index,
-                       0,
-                       0,
-                       &etm_crdt_th_wfqfq_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    etm_crdt_th_wfqfq_t.th_wfq = (etm_crdt_th_sp_t.th_sp + wfq_num / 8);
-    rc  = dpp_reg_write(dev,
-                        th_wfq_fq_index,
-                        0,
-                        0,
-                        &etm_crdt_th_wfqfq_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    /* th_wfq2参数配置：th_wfq2 = (th_wfq +      wfq2_num/4) */
-    rc  = dpp_reg_read(dev,
-                       th_wfq_fq2_index,
-                       0,
-                       0,
-                       &etm_crdt_th_wfqfq2_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    etm_crdt_th_wfqfq2_t.th_wfq2 = (etm_crdt_th_wfqfq_t.th_wfq + wfq2_num / 4);
-    rc  = dpp_reg_write(dev,
-                        th_wfq_fq2_index,
-                        0,
-                        0,
-                        &etm_crdt_th_wfqfq2_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    /* th_wfq4参数配置：th_wfq4 = (th_wfq2 +      wfq4_num/2) */
-    rc  = dpp_reg_read(dev,
-                       th_wfq_fq4_index,
-                       0,
-                       0,
-                       &etm_crdt_th_wfqfq4_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    etm_crdt_th_wfqfq4_t.th_wfq4 = (etm_crdt_th_wfqfq2_t.th_wfq2 + wfq4_num / 2);
-    rc  = dpp_reg_write(dev,
-                        th_wfq_fq4_index,
-                        0,
-                        0,
-                        &etm_crdt_th_wfqfq4_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 获取各调度器的起始编号（etm共25K=25600,ftm共1920个）
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_spwfq_start_num  调度器起始编号结构体
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/26
-************************************************************/
-DPP_STATUS dpp_tm_crdt_wfqsp_get(DPP_DEV_T *dev,
-                                 DPP_TM_CRDT_SPWFQ_START_NUM_T *p_spwfq_start_num)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CRDT_TH_SP_T       etm_crdt_th_sp_t = {0};
-    DPP_ETM_CRDT_TH_WFQ_FQ_T   etm_crdt_th_wfqfq_t = {0};
-    DPP_ETM_CRDT_TH_WFQ2_FQ2_T etm_crdt_th_wfqfq2_t = {0};
-    DPP_ETM_CRDT_TH_WFQ4_FQ4_T etm_crdt_th_wfqfq4_t = {0};
-    ZXIC_UINT32 th_sp_index = ETM_CRDT_TH_SPr;
-    ZXIC_UINT32 th_wfq_fq_index = ETM_CRDT_TH_WFQ_FQr;
-    ZXIC_UINT32 th_wfq_fq2_index = ETM_CRDT_TH_WFQ2_FQ2r;
-    ZXIC_UINT32 th_wfq_fq4_index = ETM_CRDT_TH_WFQ4_FQ4r;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_spwfq_start_num);
-
-    /* 读取调度器阈值配置：th_sp参数配置：th_sp=      sp_num/8 */
-    rc  = dpp_reg_read(dev,
-                       th_sp_index,
-                       0,
-                       0,
-                       &etm_crdt_th_sp_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-    /* th_wfq阈值读取：th_wfq = (th_sp + wfq_num/8)       */
-    rc  = dpp_reg_read(dev,
-                       th_wfq_fq_index,
-                       0,
-                       0,
-                       &etm_crdt_th_wfqfq_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-    /* th_wfq2阈值读取：th_wfq2 = (th_wfq +      wfq2_num/4) */
-    rc  = dpp_reg_read(dev,
-                       th_wfq_fq2_index,
-                       0,
-                       0,
-                       &etm_crdt_th_wfqfq2_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-    /* th_wfq4阈值读取：th_wfq4 = (th_wfq2 +      wfq4_num/2) */
-    rc  = dpp_reg_read(dev,
-                       th_wfq_fq4_index,
-                       0,
-                       0,
-                       &etm_crdt_th_wfqfq4_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    /* 各调度器起始编号计算 */
-    p_spwfq_start_num->start_num_fq = 0;
-    p_spwfq_start_num->start_num_fq2 = etm_crdt_th_wfqfq_t.th_fq * 8;
-    p_spwfq_start_num->start_num_fq4 = etm_crdt_th_wfqfq2_t.th_fq2 * 8;
-    p_spwfq_start_num->start_num_fq8 = etm_crdt_th_wfqfq4_t.th_fq4 * 8;
-    p_spwfq_start_num->start_num_sp = DPP_ETM_WFQSP_OFFSET;
-    p_spwfq_start_num->start_num_wfq = (DPP_ETM_WFQSP_OFFSET + etm_crdt_th_sp_t.th_sp * 8);
-    p_spwfq_start_num->start_num_wfq2 = (DPP_ETM_WFQSP_OFFSET + etm_crdt_th_wfqfq_t.th_wfq * 8);
-    p_spwfq_start_num->start_num_wfq4 = (DPP_ETM_WFQSP_OFFSET + etm_crdt_th_wfqfq2_t.th_wfq2 * 8);
-    p_spwfq_start_num->start_num_wfq8 = (DPP_ETM_WFQSP_OFFSET + etm_crdt_th_wfqfq4_t.th_wfq4 * 8);
-
-    return DPP_OK;
-
-
-}
-
-
-/***********************************************************/
-/** 获取调度器类型
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   se_id     调度器编号
-* @param   item_num  调度器中包含的子调度器个数
-* @param   sch_type_num  调度器类型编号
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/26
-************************************************************/
-DPP_STATUS dpp_tm_crdt_sch_type_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id, ZXIC_UINT32 *item_num, ZXIC_UINT32 *sch_type_num)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_TM_CRDT_SPWFQ_START_NUM_T spwfq_start_num_t = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), item_num);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-
-
-    rc = dpp_tm_crdt_wfqsp_get(dev, &spwfq_start_num_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_wfqsp_get");
-
-
-    if (se_id < spwfq_start_num_t.start_num_fq2)
-    {
-        *item_num = 1;
-        *sch_type_num = 5;
-    }
-    else if (se_id < spwfq_start_num_t.start_num_fq4)
-    {
-        *item_num = 2;
-        *sch_type_num = 6;
-    }
-    else if (se_id < spwfq_start_num_t.start_num_fq8)
-    {
-        *item_num = 4;
-        *sch_type_num = 7;
-    }
-    else if (se_id < spwfq_start_num_t.start_num_sp)
-    {
-        *item_num = 8;
-        *sch_type_num = 8;
-    }
-    else if (se_id < spwfq_start_num_t.start_num_wfq)
-    {
-        *item_num = 1;
-        *sch_type_num = 0;
-    }
-    else if (se_id < spwfq_start_num_t.start_num_wfq2)
-    {
-        *item_num = 1;
-        *sch_type_num = 1;
-    }
-    else if (se_id < spwfq_start_num_t.start_num_wfq4)
-    {
-        *item_num = 2;
-        *sch_type_num = 2;
-    }
-    else if (se_id < spwfq_start_num_t.start_num_wfq8)
-    {
-        *item_num = 4;
-        *sch_type_num = 3;
-    }
-    else
-    {
-        *item_num = 8;
-        *sch_type_num = 4;
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 获取pp->dev挂接关系
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   pp_id   0~63
-* @param   p_weight  0~127
-* @param   p_sp_mapping   0~7
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/04/20
-************************************************************/
-DPP_STATUS dpp_tm_crdt_pp_para_get(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 pp_id,
-                                   ZXIC_UINT32 *p_weight,
-                                   ZXIC_UINT32 *p_sp_mapping)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_ETM_CRDT_PP_CFG_T pp_cfg_r = {0};
-    DPP_ETM_CRDT_PP_WEIGHT_T pp_weight_r = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pp_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_weight);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_sp_mapping);
-
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CRDT_PP_WEIGHTr,
-                       0,
-                       pp_id,
-                       &pp_weight_r);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-    *p_weight = pp_weight_r.pp_weight;
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CRDT_PP_CFGr,
-                       0,
-                       pp_id,
-                       &pp_cfg_r);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-    *p_sp_mapping = pp_cfg_r.pp_cfg;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置se->pp->dev挂接关系
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   se_id   往端口挂接的调度器id
-* @param   pp_id   [0-63]
-* @param   weight  [1-511]
-* @param   sp_mapping   [0~8]
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/3/4
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_pp_link_set(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 se_id,
-                                      ZXIC_UINT32 pp_id,
-                                      ZXIC_UINT32 weight,
-                                      ZXIC_UINT32 sp_mapping)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 delay_time = 10;
-
-    DPP_ETM_CRDT_PP_CFG_T pp_cfg = {0};
-    DPP_ETM_CRDT_PP_WEIGHT_T pp_weight = {0};
-    DPP_ETM_CRDT_PP_CFG_T pp_cfg_r = {0};
-    DPP_ETM_CRDT_PP_WEIGHT_T pp_weight_r = {0};
-    DPP_TM_SCH_SE_PARA_T sch_se_para_t = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pp_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), weight, 0, DPP_TM_SCH_WEIGHT_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), sp_mapping, DPP_TM_SCH_SP_0, DPP_TM_SCH_SP_8);
-
-    /* 参数赋值:仅需端口号 ,配置调度器到端口的挂接 */
-    sch_se_para_t.se_linkid = DPP_ETM_PORT_LINKID_BASE + pp_id;
-
-    rc = dpp_tm_crdt_se_link_wr(dev, se_id, &sch_se_para_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_se_link_wr");
-
-    /* 检测CRDT寄存器是否空闲 */
-    rc  = dpp_tm_crdt_idle_check(dev);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_idle_check");
-
-    pp_weight.pp_weight = weight;
-    rc  = dpp_reg_write(dev,
-                        ETM_CRDT_PP_WEIGHTr,
-                        0,
-                        pp_id,
-                        &pp_weight);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    /* 写入后，重新读出来校验 */
-#if (ETM_WRITE_CHECK)
-    {
-        zxic_comm_delay(delay_time);
-        rc  = dpp_reg_read(dev,
-                           ETM_CRDT_PP_WEIGHTr,
-                           0,
-                           pp_id,
-                           &pp_weight_r);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-        if (pp_weight_r.pp_weight != pp_weight.pp_weight)
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_crdt_pp_para_set pp[0x%x] wt_pp_weight[0x%x] rd_pp_weight[0x%x]\n", pp_id, pp_weight.pp_weight, pp_weight_r.pp_weight);
-            return DPP_ERR;
-        }
-    }
-#endif
-
-    /* 检测CRDT寄存器是否空闲 */
-    rc  = dpp_tm_crdt_idle_check(dev);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_idle_check");
-
-    pp_cfg.pp_cfg = sp_mapping;
-    rc  = dpp_reg_write(dev,
-                        ETM_CRDT_PP_CFGr,
-                        0,
-                        pp_id,
-                        &pp_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    /* 写入后，重新读出来校验 */
-#if (ETM_WRITE_CHECK)
-    {
-        zxic_comm_delay(delay_time);
-        rc  = dpp_reg_read(dev,
-                           ETM_CRDT_PP_CFGr,
-                           0,
-                           pp_id,
-                           &pp_cfg_r);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-        if (pp_cfg_r.pp_cfg != pp_cfg.pp_cfg)
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_crdt_pp_para_set pp[0x%x] wt_pp_cfg[0x%x] rd_pp_cfg[0x%x]\n", pp_id, pp_cfg.pp_cfg, pp_cfg_r.pp_cfg);
-            return DPP_ERR;
-        }
-    }
-#endif
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置flow级流队列的挂接关系(flow到上级调度器的挂接)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id   流队列号
-* @param   c_linkid  c桶要挂接到的上级调度器id
-* @param   c_weight  c桶挂接到上级调度器的权重[1~511]
-* @param   c_sp      c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
-* @param   mode      挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可
-* @param   e_linkid  e桶要挂接到的上级调度器id
-* @param   e_weight  e桶挂接到上级调度器的权重[1~511]
-* @param   e_sp      e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_flow_link_wr(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 flow_id,
-                                    DPP_TM_SCH_FLOW_PARA_T *p_flow_para)
-
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 flow_id_e = 0;
-    ZXIC_UINT32 c_linkid;
-    ZXIC_UINT32 c_weight;
-    ZXIC_UINT32 c_sp;
-    ZXIC_UINT32 mode;
-    ZXIC_UINT32 e_linkid;
-    ZXIC_UINT32 e_weight;
-    ZXIC_UINT32 e_sp;
-    DPP_ETM_CRDT_FLOWQUE_PARA_TBL_T etm_crdt_flow_para_tbl_t = {0};
-
-    /* 取配置参数 */
-    c_linkid = p_flow_para->c_linkid;
-    c_weight = p_flow_para->c_weight;
-    c_sp = p_flow_para->c_sp;
-    mode = p_flow_para->mode;
-    e_linkid = p_flow_para->e_linkid;
-    e_weight = p_flow_para->e_weight;
-    e_sp = p_flow_para->e_sp;
-    /* 参数校验 */
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_flow_para);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), c_weight, 0, DPP_TM_SCH_WEIGHT_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), e_weight, 0, DPP_TM_SCH_WEIGHT_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), c_sp, 0, DPP_TM_SCH_SP_NUM);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), e_sp, 0, DPP_TM_SCH_SP_NUM);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0, DPP_ETM_Q_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), c_linkid, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), e_linkid, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-
-
-    /* 开始流级挂接配置 */
-
-    if (mode == 1)
-    {
-        flow_id_e = (flow_id + 0x2400);
-    }
-
-    /* c桶挂接配置 */
-    etm_crdt_flow_para_tbl_t.flowque_link = c_linkid;
-    etm_crdt_flow_para_tbl_t.flowque_w = c_weight;
-    etm_crdt_flow_para_tbl_t.flowque_pri = c_sp;
-
-    rc  = dpp_reg_write(dev,
-                        ETM_CRDT_FLOWQUE_PARA_TBLr,
-                        0,
-                        flow_id,
-                        &etm_crdt_flow_para_tbl_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    zxic_comm_delay(5);
-
-    /* mode-1 需要配置双桶挂接 */
-    if (mode == 1)
-    {
-        /* e桶挂接配置 */
-        etm_crdt_flow_para_tbl_t.flowque_link = e_linkid;
-        etm_crdt_flow_para_tbl_t.flowque_w = e_weight;
-        etm_crdt_flow_para_tbl_t.flowque_pri = e_sp;
-
-        rc  = dpp_reg_write(dev,
-                            ETM_CRDT_FLOWQUE_PARA_TBLr,
-                            0,
-                            flow_id_e,
-                            &etm_crdt_flow_para_tbl_t);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-    }
-
-    zxic_comm_delay(5);
-
-    return DPP_OK;
-
-
-}
-
-/***********************************************************/
-/** 配置flow级流队列的挂接关系(flow到上级调度器的挂接)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id   流队列号
-* @param   c_linkid  c桶要挂接到的上级调度器id
-* @param   c_weight  c桶挂接到上级调度器的权重[1~511]
-* @param   c_sp      c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
-* @param   mode      挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可
-* @param   e_linkid  e桶要挂接到的上级调度器id
-* @param   e_weight  e桶挂接到上级调度器的权重[1~511]
-* @param   e_sp      e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_flow_link_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 flow_id,
-                                     ZXIC_UINT32 c_linkid,
-                                     ZXIC_UINT32 c_weight,
-                                     ZXIC_UINT32 c_sp,
-                                     ZXIC_UINT32 mode,
-                                     ZXIC_UINT32 e_linkid,
-                                     ZXIC_UINT32 e_weight,
-                                     ZXIC_UINT32 e_sp)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_TM_SCH_FLOW_PARA_T sch_flow_para_t = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    /* 参数赋值 */
-    sch_flow_para_t.c_linkid = c_linkid;
-    sch_flow_para_t.c_weight = c_weight;
-    sch_flow_para_t.c_sp = c_sp;
-    sch_flow_para_t.mode = mode;
-    sch_flow_para_t.e_linkid = e_linkid;
-    sch_flow_para_t.e_weight = e_weight;
-    sch_flow_para_t.e_sp = e_sp;
-
-    rc = dpp_tm_crdt_flow_link_wr(dev, flow_id, &sch_flow_para_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_flow_link_wr");
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 批量配置flow级流队列的挂接关系
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id_s 起始流队列号
-* @param   flow_id_e 终止流队列号
-* @param   c_linkid  c桶要挂接到的上级调度器id
-* @param   c_weight  c桶挂接到上级调度器的权重[1~511]
-* @param   c_sp      c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
-* @param   mode      挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可
-* @param   e_linkid  e桶要挂接到的上级调度器id
-* @param   e_weight  e桶挂接到上级调度器的权重[1~511]
-* @param   e_sp      e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_flow_link_more_set(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 flow_id_s,
-                                          ZXIC_UINT32 flow_id_e,
-                                          ZXIC_UINT32 c_linkid,
-                                          ZXIC_UINT32 c_weight,
-                                          ZXIC_UINT32 c_sp,
-                                          ZXIC_UINT32 mode,
-                                          ZXIC_UINT32 e_linkid,
-                                          ZXIC_UINT32 e_weight,
-                                          ZXIC_UINT32 e_sp)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 flow_id = 0;
-    DPP_TM_SCH_FLOW_PARA_T sch_flow_para_t = {0};
-    ZXIC_COMM_CHECK_POINT(dev);
-    
-
-    if (flow_id_s > flow_id_e)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Bad parameters!  flow_id_s > flow_id_e !\n");
-        return DPP_ERR;
-    }
-
-    /* 参数赋值 */
-    sch_flow_para_t.c_linkid = c_linkid;
-    sch_flow_para_t.c_weight = c_weight;
-    sch_flow_para_t.c_sp = c_sp;
-    sch_flow_para_t.mode = mode;
-    sch_flow_para_t.e_linkid = e_linkid;
-    sch_flow_para_t.e_weight = e_weight;
-    sch_flow_para_t.e_sp = e_sp;
-
-    for (flow_id = flow_id_s; flow_id <= flow_id_e; flow_id++)
-    {
-        rc = dpp_tm_crdt_flow_link_wr(dev, flow_id, &sch_flow_para_t);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_flow_link_wr");
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 配置调度器层次化QOS的挂接关系:非优先级传递
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   se_id      本级调度器id
-*                     对于FQX/WFQX必须是调度单元中首个调度器id
-* @param   se_linkid  要挂接到的上级调度器id
-* @param   se_weight  挂接到上级调度器的权重[1~511]
-* @param   se_sp      挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
-* @param   se_insw    优先级传递使能：0-关 1-开。该参数不传递直接配0
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_link_wr(DPP_DEV_T *dev,
-                                  ZXIC_UINT32 se_id,
-                                  DPP_TM_SCH_SE_PARA_T *p_sch_se_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 se_linkid = 0;
-    ZXIC_UINT32 se_weight = 0;
-    ZXIC_UINT32 se_sp = 0;
-    ZXIC_UINT32 se_insw = 0;     /* 优先级传递关闭 */
-    ZXIC_UINT32 item_num = 0;    /* 调度单元中调度器的个数 */
-    ZXIC_UINT32 sch_type_num = 0;
-    ZXIC_UINT32 i = 0;
-    DPP_ETM_CRDT_SE_PARA_TBL_T    etm_crdt_se_para_tbl_t = {0};
-
-
-    /* 取配置参数 */
-    se_linkid = p_sch_se_para->se_linkid;
-    se_weight = p_sch_se_para->se_weight;
-    se_sp = p_sch_se_para->se_sp;
-
-
-    /* 参数校验 */
-    ZXIC_COMM_CHECK_POINT(dev);    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight, 0, DPP_TM_SCH_WEIGHT_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_sp, 0, DPP_TM_SCH_SP_NUM);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_insw, 0, 0);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-
-    if (se_linkid > DPP_ETM_FQSPWFQ_NUM)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_linkid, DPP_TM_PP_LINKID_PORT0, DPP_TM_PP_LINKID_PORT63);
-    }
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_linkid, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-    }
-
-
-    /* 开始调度器挂接配置 */
-
-    /* 先区分调度器类型：sp/fq/wfq调度器挂接方式相同，wfqx/fqx=2/4/8是另一种挂接方式 */
-    rc = dpp_tm_crdt_sch_type_get(dev, se_id, &item_num, &sch_type_num);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_sch_type_get");
-
-
-    /* 非优先级传递挂接:各调度器参数须相同 */
-    etm_crdt_se_para_tbl_t.se_link = se_linkid;
-    etm_crdt_se_para_tbl_t.se_w = se_weight;
-    etm_crdt_se_para_tbl_t.se_pri = se_sp;
-    etm_crdt_se_para_tbl_t.se_insw = se_insw;
-    etm_crdt_se_para_tbl_t.cp_token_en = 1;
-
-    for (i = 0; i < item_num; i++)
-    {
-        rc  = dpp_reg_write(dev,
-                            ETM_CRDT_SE_PARA_TBLr,
-                            0,
-                            se_id + i,
-                            &etm_crdt_se_para_tbl_t);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-    }
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置调度器层次化QOS的挂接关系:非优先级传递
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   se_id      本级调度器id
-*                     对于FQX/WFQX必须是调度单元中首个调度器id
-* @param   se_linkid  要挂接到的上级调度器id
-* @param   se_weight  挂接到上级调度器的权重[1~511]
-* @param   se_sp      挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
-* @param   se_insw    优先级传递使能：0-关 1-开. 该参数不传递直接配0
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_link_set(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 se_id,
-                                   ZXIC_UINT32 se_linkid,
-                                   ZXIC_UINT32 se_weight,
-                                   ZXIC_UINT32 se_sp)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_TM_SCH_SE_PARA_T sch_se_para_t = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    /* 参数赋值 */
-    sch_se_para_t.se_linkid = se_linkid;
-    sch_se_para_t.se_weight = se_weight;
-    sch_se_para_t.se_sp = se_sp;
-
-    rc = dpp_tm_crdt_se_link_wr(dev, se_id, &sch_se_para_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_se_link_wr");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置调度器层次化QOS的挂接关系:优先级传递
-* @param   dev_id       设备编号
-* @param   tm_type      0-ETM,1-FTM
-* @param   se_id        本级调度器id
-* @param   se_linkid    要挂接到的上级调度器id
-* @param   se_sp        挂接到上级调度器的sp优先级,有效值[0-3],最多4级，优先级按调度单元分配，
-*                       每个调度单元内部调度器优先级相同！
-* @param   se_weight0-7 WFQ8中各调度器权重值[1~511]，若是WFQ2/4 只取前面对应值，后面无效
-* @param   se_insw      优先级传递使能：0-关 1-开. 该参数不传递直接配1
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_link_insw_wr(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 se_id,
-                                       DPP_TM_SCH_SE_PARA_INSW_T *p_sch_se_para_insw)
-{
-    ZXIC_UINT32  rc = DPP_OK;
-    ZXIC_UINT32  se_linkid;          /**  要挂接到的上级调度器id */
-    ZXIC_UINT32  se_sp;              /** 挂接到上级调度器的sp优先级,有效值[0-3],共4级，优先级依次降低,优先级按调度单元分配 */
-    ZXIC_UINT32  se_weight[8] = {0}; /** WFQ8中各调度器权重值[1~511]，若是WFQ2/4 只取前面对应值，后面无效 */
-    ZXIC_UINT32  se_insw = 1;        /* 优先级传递开启 */
-    ZXIC_UINT32  item_num = 1;       /* 调度单元中调度器的个数 */
-    ZXIC_UINT32  sch_type_num = 0;
-    ZXIC_UINT32  item_num_link = 0;       /* 上级调度单元中调度器的个数 */
-    ZXIC_UINT32  sch_type_num_link = 0;
-    ZXIC_UINT32  i = 0;
-    DPP_ETM_CRDT_SE_PARA_TBL_T    etm_crdt_se_para_tbl_t = {0};
-
-    /* 取配置参数 */
-    se_linkid = p_sch_se_para_insw->se_linkid;
-    se_sp = p_sch_se_para_insw->se_sp;
-    se_weight[0] = p_sch_se_para_insw->se_weight[0];
-    se_weight[1] = p_sch_se_para_insw->se_weight[1];
-    se_weight[2] = p_sch_se_para_insw->se_weight[2];
-    se_weight[3] = p_sch_se_para_insw->se_weight[3];
-    se_weight[4] = p_sch_se_para_insw->se_weight[4];
-    se_weight[5] = p_sch_se_para_insw->se_weight[5];
-    se_weight[6] = p_sch_se_para_insw->se_weight[6];
-    se_weight[7] = p_sch_se_para_insw->se_weight[7];
-
-
-    /* 参数校验 */
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_sp, 0, DPP_TM_SCH_SP_NUM - 5);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_insw, 1, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[0], 0, DPP_TM_SCH_WEIGHT_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[1], 0, DPP_TM_SCH_WEIGHT_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[2], 0, DPP_TM_SCH_WEIGHT_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[3], 0, DPP_TM_SCH_WEIGHT_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[4], 0, DPP_TM_SCH_WEIGHT_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[5], 0, DPP_TM_SCH_WEIGHT_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[6], 0, DPP_TM_SCH_WEIGHT_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[7], 0, DPP_TM_SCH_WEIGHT_MAX);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_linkid, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-
-
-
-    /* 开始调度器挂接配置 */
-
-    /* 先区分调度器类型：sp/fq/wfq调度器挂接方式相同，wfqx/fqx=2/4/8是另一种挂接方式 */
-    rc = dpp_tm_crdt_sch_type_get(dev, se_id, &item_num, &sch_type_num);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_sch_type_get");
-    rc = dpp_tm_crdt_sch_type_get(dev, se_linkid, &item_num_link, &sch_type_num_link);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_sch_type_get");
-
-    /* 优先级传递挂接合法性检查:下级传入调度器需是首编号，且下级<=上级 */
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), item_num, 1, 8);
-
-    if (se_id % item_num != 0 || item_num > item_num_link)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "dpp_tm_crdt_se_link_insw_wr： NOT CORRECT,bad parameters!\n");
-        return DPP_ERR;
-    }
-
-
-    /* 优先级传递挂接:各调度器挂接的se_linkid依次递增1,需相邻不能错开
-                      se_weight不限，取值[1-511]
-                      se_sp:根据下级往上级挂接情况，取值[0-3]，调度单元内部须相同
-                      se_insw 写死为1 */
-    etm_crdt_se_para_tbl_t.se_pri = se_sp;
-    etm_crdt_se_para_tbl_t.se_insw = se_insw;
-    etm_crdt_se_para_tbl_t.cp_token_en = 1;
-
-    for (i = 0; i < item_num; i++)
-    {
-        etm_crdt_se_para_tbl_t.se_link = (se_linkid + i);
-        etm_crdt_se_para_tbl_t.se_w = se_weight[i];
-
-        rc  = dpp_reg_write(dev,
-                            ETM_CRDT_SE_PARA_TBLr,
-                            0,
-                            se_id + i,
-                            &etm_crdt_se_para_tbl_t);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-    }
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置调度器层次化QOS的挂接关系:优先级传递
-* @param   dev_id       设备编号
-* @param   tm_type      0-ETM,1-FTM
-* @param   se_id        本级调度器id
-* @param   se_linkid    要挂接到的上级调度器id
-* @param   se_weight    WFQ2/4/8中各调度器权重值[1~511]，取相等的值
-* @param   se_sp        挂接到上级调度器的sp优先级,有效值[0-7],共8级，优先级依次降低
-* @param   se_insw      优先级传递使能：0-关 1-开. 该参数不传递直接配1
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_link_insw_set(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 se_id,
-                                        ZXIC_UINT32 se_linkid,
-                                        ZXIC_UINT32 se_weight,
-                                        ZXIC_UINT32 se_sp)
-{
-    ZXIC_UINT32 rc = DPP_OK;
-    DPP_TM_SCH_SE_PARA_INSW_T sch_se_para_insw_t = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    /* 参数赋值 */
-    sch_se_para_insw_t.se_linkid = se_linkid;
-    sch_se_para_insw_t.se_sp = se_sp;
-    sch_se_para_insw_t.se_weight[0] = se_weight;
-    sch_se_para_insw_t.se_weight[1] = se_weight;
-    sch_se_para_insw_t.se_weight[2] = se_weight;
-    sch_se_para_insw_t.se_weight[3] = se_weight;
-    sch_se_para_insw_t.se_weight[4] = se_weight;
-    sch_se_para_insw_t.se_weight[5] = se_weight;
-    sch_se_para_insw_t.se_weight[6] = se_weight;
-    sch_se_para_insw_t.se_weight[7] = se_weight;
-
-    rc = dpp_tm_crdt_se_link_insw_wr(dev, se_id, &sch_se_para_insw_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_se_link_insw_wr");
-
-    return DPP_OK;
-
-
-}
-
-
-/***********************************************************/
-/** 配置调度器层次化QOS的挂接关系:优先级传递,单个调度器挂接
-* @param   dev_id       设备编号
-* @param   tm_type      0-ETM,1-FTM
-* @param   se_id        本级调度器id
-* @param   se_linkid    要挂接到的上级调度器id
-* @param   se_weight    WFQ8中对应调度器权重值[1~511]
-* @param   se_sp        挂接到上级调度器的sp优先级,有效值[0-7],共8级，优先级依次降低
-* @param   se_insw      优先级传递使能：0-关 1-开. 该参数不传递直接配1
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_link_insw_single_set(DPP_DEV_T *dev,
-                                               ZXIC_UINT32 se_id,
-                                               ZXIC_UINT32 se_linkid,
-                                               ZXIC_UINT32 se_weight,
-                                               ZXIC_UINT32 se_sp)
-{
-    ZXIC_UINT32  rc = DPP_OK;
-    ZXIC_UINT32  se_insw = 1;        /* 优先级传递开启 */
-    DPP_ETM_CRDT_SE_PARA_TBL_T    etm_crdt_se_para_tbl_t = {0};
-
-
-    /* 参数校验 */
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_sp, 0, DPP_TM_SCH_SP_NUM - 5);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_insw, 1, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight, 0, DPP_TM_SCH_WEIGHT_MAX);
-
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_linkid, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-
-
-    /* 开始调度器挂接配置 */
-
-    /* 优先级传递挂接:各调度器挂接的se_linkid依次递增1,需相邻不能错开
-                      se_weight不限，取值[1-511]
-                      se_sp:根据下级往上级挂接情况，取值[0-3]，调度单元内部须相同
-                      se_insw 写死为1 */
-    etm_crdt_se_para_tbl_t.se_pri = se_sp;
-    etm_crdt_se_para_tbl_t.se_insw = se_insw;
-    etm_crdt_se_para_tbl_t.cp_token_en = 1;
-    etm_crdt_se_para_tbl_t.se_link = se_linkid;
-    etm_crdt_se_para_tbl_t.se_w = se_weight;
-
-    rc  = dpp_reg_write(dev,
-                        ETM_CRDT_SE_PARA_TBLr,
-                        0,
-                        se_id,
-                        &etm_crdt_se_para_tbl_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-
-    return DPP_OK;
-
-
-}
-
-/***********************************************************/
-/** 获取调度器挂接配置参数
-* @param   dev_id      设备编号
-* @param   tm_type     0-ETM,1-FTM
-* @param   se_id       调度器编号
-* @param   p_se_para_tbl  调度器参数
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_para_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id, DPP_ETM_CRDT_SE_PARA_TBL_T *p_se_para_tbl)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    /* 参数校验 */
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_para_tbl);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-
-    rc = dpp_reg_read(dev,
-                      ETM_CRDT_SE_PARA_TBLr,
-                      0,
-                      se_id,
-                      p_se_para_tbl);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    return DPP_OK;
-
-}
-
-
-
-/***********************************************************/
-/** 获取流队列入链状态
-* @param   dev_id      设备编号
-* @param   tm_type     0-ETM,1-FTM
-* @param   flow_id     流队列号
-* @param   link_state  0-未入链     1-在调度器链表中
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_flow_link_state_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id, ZXIC_UINT32 *link_state)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_CRDT_FLOWQUE_INS_TBL_T crdt_flow_ins_tbl_t = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), link_state);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0, DPP_ETM_CRDT_NUM);
-
-    rc = dpp_reg_read(dev,
-                      ETM_CRDT_FLOWQUE_INS_TBLr,
-                      0,
-                      flow_id,
-                      &crdt_flow_ins_tbl_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *link_state = crdt_flow_ins_tbl_t.flowque_ins;
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 获取调度器入链状态
-* @param   dev_id      设备编号
-* @param   tm_type     0-ETM,1-FTM
-* @param   se_id       调度器编号
-* @param   link_state  0-未入链     1-在调度器链表中
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_link_state_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id, ZXIC_UINT32 *link_state)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_CRDT_SE_INS_TBL_T crdt_se_ins_tbl_t = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), link_state);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-
-    rc = dpp_reg_read(dev,
-                      ETM_CRDT_SE_INS_TBLr,
-                      0,
-                      se_id,
-                      &crdt_se_ins_tbl_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *link_state = crdt_se_ins_tbl_t.se_ins_flag;
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 判断crdt流删除命令是否空闲
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_del_cmd_idle(DPP_DEV_T *dev)
-{
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 read_times = 30;
-    DPP_ETM_CRDT_FLOW_DEL_CMD_T crdt_del_cmd_busy = {0};
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    do
-    {
-        rc = dpp_reg_read(dev,
-                          ETM_CRDT_FLOW_DEL_CMDr,
-                          0,
-                          0,
-                          &crdt_del_cmd_busy);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-        read_times--;
-        zxic_comm_delay(5);
-    }
-    while ((0 != (crdt_del_cmd_busy.flow_del_busy)) && (read_times > 0));
-
-    if (0 == read_times)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "CRDT Del command busy!\n");
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 删除流/调度器挂接关系(调度器编号非从0开始，需要偏移)
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   id        要删除的流号或调度器id
-*          ETM范围:0--0xABFF; FTM范围:0-0x177F
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_del_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 c_sta = 0;
-    ZXIC_UINT32 e_sta = 0;
-    ZXIC_UINT32 flow_e = 0;
-    ZXIC_UINT32 link_state = 0;      /*流或调度器入链状态*/
-    ZXIC_UINT32 read_times = 300;
-    ZXIC_UINT32 crdt_del_cmd_reg_index = 0;
-    DPP_ETM_CRDT_FLOW_DEL_CMD_T crdt_del_cmd_t = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_SCH_DEL_NUM);
-    flow_e = DPP_ETM_Q_NUM;
-
-    /* 循环判断入链状态是否为1 */
-    do
-    {
-
-        /* 判断当前流或调度器入链状态：非入链情况才能删除挂接 */
-        if (id <= DPP_ETM_CRDT_NUM)
-        {
-            /* 流入链状态 */
-            rc = dpp_tm_crdt_flow_link_state_get(dev, id, &c_sta);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_flow_link_state_get");
-
-            rc = dpp_tm_crdt_flow_link_state_get(dev, id + DPP_ETM_Q_NUM, &e_sta);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_flow_link_state_get");
-
-            link_state = c_sta || e_sta;
-        }
-        else
-        {
-            /*调度器入链状态*/
-            rc = dpp_tm_crdt_se_link_state_get(dev, id - DPP_ETM_SHAP_SEID_BASE, &link_state);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_se_link_state_get");
-           
-        }
-
-        if (0 == link_state)
-        {
-            break;
-        }
-        read_times--;
-        zxic_comm_delay(1);
-    }
-    while (read_times > 0);
-
-    if (read_times == 0)
-    {
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(id, flow_e);
-        ZXIC_COMM_TRACE_ERROR("id: 0x%08x ins_flag is always 1 (Maybe it's because cir equal zero) !!!\n", id);
-        /*此时要 继续往下走，执行强删！如果不删除队列没释放下次直接覆写问题更严重。zhaoyan*/
-    }
-
-    /*删挂接命令是否空闲*/
-    rc = dpp_tm_crdt_del_cmd_idle(dev);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_del_cmd_idle");
-
-
-    /*进行流或调度器删除操作*/
-    crdt_del_cmd_reg_index = ETM_CRDT_FLOW_DEL_CMDr;
-    crdt_del_cmd_t.flow_alt_cmd = 1;
-    crdt_del_cmd_t.flow_alt_ind = id;
-
-    /* 流删除：如果删除c桶，需要同时删除e桶 */
-    if (id < DPP_ETM_Q_NUM)
-    {
-        rc = dpp_reg_write(dev,
-                           crdt_del_cmd_reg_index,
-                           0,
-                           0,
-                           &crdt_del_cmd_t);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-        /*删挂e桶：判断命令是否空闲*/
-        rc = dpp_tm_crdt_del_cmd_idle(dev);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_del_cmd_idle");
-        crdt_del_cmd_t.flow_alt_ind = (id + DPP_ETM_Q_NUM);
-        rc = dpp_reg_write(dev,
-                           crdt_del_cmd_reg_index,
-                           0,
-                           0,
-                           &crdt_del_cmd_t);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-    }
-    else
-    {
-
-        rc = dpp_reg_write(dev,
-                           crdt_del_cmd_reg_index,
-                           0,
-                           0,
-                           &crdt_del_cmd_t);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 删除调度器挂接关系(调度器编号从0开始)：对外API
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   se_id_s   要删除的起始调度器id
-* @param   se_id_e   要删除的终止调度器id
-*          ETM范围:0--0x63FF; FTM范围:0-0x77F
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_del_se_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id_s, ZXIC_UINT32 id_e)
-{
-
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 se_id_offset = 0;
-    ZXIC_UINT32 id = 0 ;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id_s, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id_e, 0, DPP_ETM_FQSPWFQ_NUM - 1);
-    se_id_offset = DPP_ETM_SHAP_SEID_BASE;
-
-    if (id_s > id_e)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Bad parameters!  id_s > id_e!\n");
-        return DPP_ERR;
-    }
-
-    for (id = id_s; id <= id_e; id++)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), id , se_id_offset);    
-        rc = dpp_tm_crdt_del_link_set(dev, id + se_id_offset);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_del_link_set");
-    }
-
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 删除流挂接关系：对外API
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   id_s      要删除的流号或调度器起始id
-* @param   id_e      要删除的流号或调度器终止id
-*          ETM范围:0--0x47FF; FTM范围:0-0xFFF
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/02/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_del_flow_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id_s, ZXIC_UINT32 id_e)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 id = 0;
-    ZXIC_UINT32 q_td_th = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id_s, 0, DPP_ETM_CRDT_NUM);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id_e, 0, DPP_ETM_CRDT_NUM);
-
-    if (id_s > id_e)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Bad parameters!  id_s > id_e !\n");
-        return DPP_ERR;
-    }
-
-    for (id = id_s; id <= id_e; id++)
-    {
-        rc = dpp_tm_cgavd_td_th_get(dev, QUEUE_LEVEL, id, &q_td_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_td_th_get");
-
-        if (q_td_th != 0)
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "queue TD_TH is not equal 0 !  q_td_th != 0 !\n");
-            return DPP_ERR;
-        }
-    }
-
-    for (id = id_s; id <= id_e; id++)
-    {
-        rc = dpp_tm_crdt_del_link_set(dev, id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_del_link_set");
-    }
-
-    return DPP_OK;
-}
-
-#if 0
-/***********************************************************/
-/** 配置授权分发使能或者关闭
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   en   配置的值，0-关闭授权分发，1-使能授权分发
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_crdt_credit_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CRDT_CREDIT_EN_T credit_en = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1);
-
-    credit_en.credit_en = en;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CRDT_CREDIT_ENr,
-                        0,
-                        0,
-                        &credit_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取授权分发使能或者关闭
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_en   读出的值，0-关闭授权分发，1-使能授权分发
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/25
-************************************************************/
-DPP_STATUS dpp_tm_crdt_credit_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CRDT_CREDIT_EN_T credit_en = {0};
-    
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en);
-
-    *p_en = 0xffffffff;
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CRDT_CREDIT_ENr,
-                       0,
-                       0,
-                       &credit_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_en = credit_en.credit_en;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置授权产生间隔
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   crdt_space_choose  授权发送间隔 0:固定16个周期 1：查表
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/10
-************************************************************/
-DPP_STATUS dpp_tm_crdt_space_choose_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crdt_space_choose)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_CRDT_CREDIT_SPACE_SELECT_T space_select = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, crdt_space_choose, 0, 1);
-
-    space_select.credit_space_select = crdt_space_choose;
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_CRDT_CREDIT_SPACE_SELECTr,
-                       0,
-                       0,
-                       &space_select);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获得授权产生间隔
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   crdt_space_choose   授权发送间隔 0:固定16个周期 1：查表
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/10
-************************************************************/
-DPP_STATUS dpp_tm_crdt_space_choose_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_crdt_space_choose)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_CRDT_CREDIT_SPACE_SELECT_T space_select = {0};
-
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_CRDT_CREDIT_SPACE_SELECTr,
-                      0,
-                      0,
-                      &space_select);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_crdt_space_choose = space_select.credit_space_select;
-
-    return DPP_OK;
-}
-
-#endif
-/***********************************************************/
-/** 配置端口拥塞令牌桶使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   port_id   端口号：0~63
-* @param   port_en   端口拥塞令牌桶使能，1表示不使用拥塞令牌桶的授权，0表示可以使用拥塞令牌桶授权
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/03/11
-************************************************************/
-DPP_STATUS dpp_tm_crdt_port_congest_en_set(DPP_DEV_T *dev,
-                                           ZXIC_UINT32 port_id,
-                                           ZXIC_UINT32 port_en)
-{
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 value = 0;
-    DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0_T disable_31_0 = {0};
-    DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32_T disable_63_32 = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_en, 0, 1);
-
-    if (port_id <= 31)
-    {
-        /* port_id:[0-31] */
-        rc = dpp_reg_read(dev,
-                          ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0r,
-                          0,
-                          0,
-                          &disable_31_0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-        value = disable_31_0.congest_token_disable_31_0;
-
-        if (port_en == 0)
-        {
-            value = value & (~(1u << port_id));
-        }
-        else
-        {
-            value = value | (1u << port_id);
-        }
-
-        disable_31_0.congest_token_disable_31_0 = value;
-
-        rc = dpp_reg_write(dev,
-                           ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0r,
-                           0,
-                           0,
-                           &disable_31_0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-    }
-    else
-    {
-        /* port_id:[32-63] */
-        rc = dpp_reg_read(dev,
-                          ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32r,
-                          0,
-                          0,
-                          &disable_63_32);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-        value = disable_63_32.congest_token_disable_63_32;
-
-        if (port_en == 0)
-        {
-            value = value & (~(1u << (port_id - 32)));
-        }
-        else
-        {
-            value = value | (1u<< (port_id - 32));
-        }
-
-        disable_63_32.congest_token_disable_63_32 = value;
-
-        rc = dpp_reg_write(dev,
-                           ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32r,
-                           0,
-                           0,
-                           &disable_63_32);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获得端口拥塞令牌桶使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   port_id   端口号：0~120
-* @param   p_port_en   端口拥塞令牌桶使能，1表示不使用拥塞令牌桶的授权，0表示可以使用拥塞令牌桶授权
-*
-* @return
-* @remark  无
-* @see
-* @author  djf      @date  2015/03/11
-************************************************************/
-DPP_STATUS dpp_tm_crdt_port_congest_en_get(DPP_DEV_T *dev,
-                                           ZXIC_UINT32 port_id,
-                                           ZXIC_UINT32 *p_port_en)
-{
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 value = 0;
-    DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0_T disable_31_0 = {0};
-    DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32_T disable_63_32 = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_port_en);
-
-    if (port_id <= 31)
-    {
-        /* port_id:[0-31] */
-        rc = dpp_reg_read(dev,
-                          ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0r,
-                          0,
-                          0,
-                          &disable_31_0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-        value = disable_31_0.congest_token_disable_31_0;
-
-        *p_port_en = 1 & (value >> port_id);
-    }
-    else
-    {
-        /* port_id:[32-63] */
-        rc = dpp_reg_read(dev,
-                          ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32r,
-                          0,
-                          0,
-                          &disable_63_32);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-        value = disable_63_32.congest_token_disable_63_32;
-
-        *p_port_en = 1 & (value >> (port_id - 32));
-    }
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** CRDT 模块 读写是否超时检查:只有端口sp优先级的配置需检测cfg_state的状态
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-*
-* @return  DPP_OK-空闲，DPP_ERR-忙
-* @remark  无
-* @see
-* @author  szq      @date  2015/05/26
-************************************************************/
-DPP_STATUS dpp_tm_crdt_idle_check(DPP_DEV_T *dev)
-{
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 read_times = 30;
-    DPP_ETM_CRDT_CFG_STATE_T is_idle_flag = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-
-    do
-    {
-        rc = dpp_reg_read(dev,
-                          ETM_CRDT_CFG_STATEr,
-                          0,
-                          0,
-                          &is_idle_flag);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-        read_times--;
-        zxic_comm_delay(5);
-
-    }
-    while ((1 == is_idle_flag.cfg_state) && (read_times > 0));
-
-    if (0 == read_times)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "crdt rw time out\n");
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
-}
-
-#if 0
-/***********************************************************/
-/** 授权个数统计寄存器清零
-* @param   dev_id  设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_crdt_clr_diag(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_CRDT_CNT_CLR_T cnt_clr = {0};
-
-    /* 不使能CRDT */
-    rc = dpp_tm_crdt_credit_en_set(dev_id, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_credit_en_set");
-
-    /* 清零所有的授权数统计寄存器 */
-    cnt_clr.cnt_clr = 1;
-    rc = dpp_reg_write(dev_id,
-                       ETM_CRDT_CNT_CLRr,
-                       0,
-                       0,
-                       &cnt_clr);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    /* 保持所有的授权数统计寄存器值 */
-    cnt_clr.cnt_clr = 0;
-    rc = dpp_reg_write(dev_id,
-                       ETM_CRDT_CNT_CLRr,
-                       0,
-                       0,
-                       &cnt_clr);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    /* 使能CRDT */
-    rc = dpp_tm_crdt_credit_en_set(dev_id, 1);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_credit_en_set");
-
-    return DPP_OK;
-}
-
-
-
-/***********************************************************/
-/** 打印各级及指定被统计的第0~15个授权流得到的授权个数 stm模式下使用
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/06/19
-************************************************************/
-DPP_STATUS dpp_tm_crdt_ackcnt_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 delay_ms)
-{
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 credit_value = 0;
-    ZXIC_UINT32 flow_spec_id_offset = 0;
-    ZXIC_FLOAT traffic_amplified = 0.0;
-    ZXIC_FLOAT flow_spec_traffic = 0.0;
-
-    DPP_ETM_CRDT_DEV_CREDIT_CNT_T dev_crdit_cnt = {0};
-    //DPP_ETM_CRDT_PP_CREDIT_CNT_T pp_crdit_cnt = {0};
-
-    DPP_ETM_CRDT_STAT_QUE_ID_0_T stat_que_id_0 = {0};
-    DPP_ETM_CRDT_STAT_QUE_CREDIT_T que_credit = {0};
-
-    rc = dpp_tm_crdt_clr_diag(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag");
-    zxic_comm_sleep(delay_ms);
-
-
-    /* dev级接收到的授权总数 */
-    rc = dpp_reg_read(dev_id,
-                      ETM_CRDT_DEV_CREDIT_CNTr,
-                      0,
-                      0,
-                      &dev_crdit_cnt);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    /* pp级接收到的授权总数
-    rc = dpp_reg_read(dev_id,
-                      ETM_CRDT_PP_CREDIT_CNTr,
-                      0,
-                      0,
-                      &pp_crdit_cnt);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");  */
-
-
-    /* 读取credit_value */
-    rc = dpp_tm_qmu_credit_value_get(dev_id, &credit_value);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_credit_value_get");
-
-    traffic_amplified = ((ZXIC_FLOAT)delay_ms * (ZXIC_FLOAT)(1000000.0)) / ((ZXIC_FLOAT)(8.0) * (ZXIC_FLOAT)(credit_value));
-    ZXIC_COMM_PRINT("dev:   ack_cnt = 0x%08x,   traffic = %.6f.(Gb)\n", dev_crdit_cnt.dev_credit_cnt, (ZXIC_FLOAT)(dev_crdit_cnt.dev_credit_cnt) / traffic_amplified);
-    //ZXIC_COMM_PRINT("pp:    ack_cnt = 0x%08x,   traffic = %.6f.(G)\n", pp_crdit_cnt.pp_credit_cnt, (ZXIC_FLOAT)(pp_crdit_cnt.pp_credit_cnt) / traffic_amplified);
-
-    for (flow_spec_id_offset = 0; flow_spec_id_offset < 16; flow_spec_id_offset++)
-    {
-        rc = dpp_reg_read(dev_id,
-                          ETM_CRDT_STAT_QUE_ID_0r + flow_spec_id_offset,
-                          0,
-                          0,
-                          &stat_que_id_0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        rc = dpp_reg_read(dev_id,
-                          ETM_CRDT_STAT_QUE_CREDITr,
-                          0,
-                          flow_spec_id_offset,
-                          &que_credit);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        flow_spec_traffic = (ZXIC_FLOAT)(que_credit.stat_que_credit_cnt) / traffic_amplified;
-
-        ZXIC_COMM_PRINT("flow_0x%04x(%5d):   ", (stat_que_id_0.stat_que_id_0 & 0xffff), (stat_que_id_0.stat_que_id_0 & 0xffff));
-        ZXIC_COMM_PRINT("ack_cnt = 0x%08x,   ", que_credit.stat_que_credit_cnt);
-        ZXIC_COMM_PRINT("traffic = %.6f.(Gb)\n", flow_spec_traffic);
-
-    }
-
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**
-* @param   dev_id   设备编号
-* @param   tm_type  0-ETM,1-FTM
-* @param   que_id   queue id
-* @param   en       1:过滤E桶队列CRS状态为SLOW的入链请求；0:E桶队列CRS SLOW正常入链；
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2019/05/08
-************************************************************/
-DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id, ZXIC_UINT32 en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CRDT_EIR_CRS_FILTER_TBL_T eir_crs_filter = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, que_id, 0, DPP_ETM_Q_NUM - 1);
-
-    eir_crs_filter.eir_crs_filter = en;
-    rc = dpp_reg_write(dev_id,
-                       ETM_CRDT_EIR_CRS_FILTER_TBLr,
-                       0,
-                       que_id,
-                       &eir_crs_filter);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return rc;
-}
-
-/***********************************************************/
-/**
-* @param   dev_id   设备编号
-* @param   tm_type  0-ETM,1-FTM
-* @param   que_id_s 起始队列号
-* @param   que_id_e 终止队列号
-* @param   en       1:过滤E桶队列CRS状态为SLOW的入链请求；0:E桶队列CRS SLOW正常入链；
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2019/05/08
-************************************************************/
-DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_more_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id_s, ZXIC_UINT32 que_id_e, ZXIC_UINT32 en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 i = 0;
-
-    if (que_id_s > que_id_e)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "Bad parameters!  que_id_s > que_id_e !\n");
-        return DPP_ERR;
-    }
-
-    for (i = que_id_s; i <= que_id_e; i++)
-    {
-        rc = dpp_tm_crdt_eir_crs_filter_en_set(dev_id, i, en);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_eir_crs_filter_en_set");
-    }
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   que_id   queue id
-* @param   p_en
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2019/05/08
-************************************************************/
-DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id, ZXIC_UINT32 *p_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CRDT_EIR_CRS_FILTER_TBL_T eir_crs_filter = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, que_id, 0, DPP_ETM_Q_NUM - 1);
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_CRDT_EIR_CRS_FILTER_TBLr,
-                      0,
-                      que_id,
-                      &eir_crs_filter);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    *p_en = eir_crs_filter.eir_crs_filter;
-
-    return rc;
-}
-
-
-/***********************************************************/
-/**cpu配置flow_id的crs强制为normal或者off开关使能，用于检测SA模式下队列到授权流的多对一问题
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id:流号(和授权流号一一对应)
-*                en   强制配置crs的使能，0-不使能，1-使能
-*                crs_value:强制配置crs的值2'b00:off; 2'b01:low; 2'b10:normal；
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/04/25
-************************************************************/
-DPP_STATUS dpp_tm_crdt_crs_sheild_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 flow_id, ZXIC_UINT32 en, ZXIC_UINT32 crs_value)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_ETM_CRDT_CRS_SHEILD_FLOW_ID_CFG_T crs_sheild_flow_id_cfg = {0};
-    DPP_ETM_CRDT_CRS_SHEILD_EN_CFG_T crs_sheild_en_cfg = {0};
-    DPP_ETM_CRDT_CRS_SHEILD_VALUE_CFG_T crs_sheild_value_cfg = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, crs_value, 0, 2);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, flow_id, 0, DPP_ETM_Q_NUM - 1);
-
-
-    crs_sheild_flow_id_cfg.crs_sheild_flow_id_cfg = flow_id;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CRDT_CRS_SHEILD_FLOW_ID_CFGr,
-                        0,
-                        0,
-                        &crs_sheild_flow_id_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    crs_sheild_en_cfg.crs_sheild_en_cfg = en;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CRDT_CRS_SHEILD_EN_CFGr,
-                        0,
-                        0,
-                        &crs_sheild_en_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    crs_sheild_value_cfg.crs_sheild_value_cfg = crs_value;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CRDT_CRS_SHEILD_VALUE_CFGr,
-                        0,
-                        0,
-                        &crs_sheild_value_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/**获取flow_id的crs强制为normal或者off开关使能，用于检测SA模式下队列到授权流的多对一问题
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id:流号(和授权流号一一对应)
-*                en   强制配置crs的使能，0-不使能，1-使能
-*                crs_value:强制配置crs的值2'b00:off; 2'b01:low; 2'b10:normal；
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/04/25
-************************************************************/
-DPP_STATUS dpp_tm_crdt_crs_sheild_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_flow_id, ZXIC_UINT32 *p_en, ZXIC_UINT32 *p_crs_value)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_ETM_CRDT_CRS_SHEILD_FLOW_ID_CFG_T crs_sheild_flow_id_cfg = {0};
-    DPP_ETM_CRDT_CRS_SHEILD_EN_CFG_T crs_sheild_en_cfg = {0};
-    DPP_ETM_CRDT_CRS_SHEILD_VALUE_CFG_T crs_sheild_value_cfg = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_flow_id);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_en);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_crs_value);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CRDT_CRS_SHEILD_FLOW_ID_CFGr,
-                       0,
-                       0,
-                       &crs_sheild_flow_id_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    *p_flow_id = crs_sheild_flow_id_cfg.crs_sheild_flow_id_cfg;
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CRDT_CRS_SHEILD_EN_CFGr,
-                       0,
-                       0,
-                       &crs_sheild_en_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    *p_en = crs_sheild_en_cfg.crs_sheild_en_cfg;
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CRDT_CRS_SHEILD_VALUE_CFGr,
-                       0,
-                       0,
-                       &crs_sheild_value_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    *p_crs_value = crs_sheild_value_cfg.crs_sheild_value_cfg;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 控制授权速率的门限
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   index   0~6
-* @param   rci_grade_th_0_data
-*
-* @return
-* @remark  无
-* @see
-* @author  wush      @date  2017/10/17
-************************************************************/
-DPP_STATUS dpp_tm_crdt_rci_grade_th_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 index, ZXIC_UINT32 rci_grade_th_0_data)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, index, 0, 6);
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_CRDT_RCI_GRADE_TH_0_CFGr + index,
-                       0,
-                       0,
-                       &rci_grade_th_0_data);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return  DPP_OK;
-}
-
-
-DPP_STATUS dpp_tm_crdt_rci_grade_th_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 index, ZXIC_UINT32 *p_rci_grade_th_0_data)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, index, 0, 6);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rci_grade_th_0_data);
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_CRDT_RCI_GRADE_TH_0_CFGr + index,
-                      0,
-                      0,
-                      p_rci_grade_th_0_data);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    return  DPP_OK;
-}
-
-/***********************************************************/
-/** 控制授权间隔的门限，建议大于等于0XF，不可取0；
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   index   0~7
-* @param   asm_interval_0_data   控制授权间隔的门限，建议大于等于0XF，不可取0；
-*
-* @return
-* @remark  无
-* @see
-* @author  wush      @date  2017/10/17
-************************************************************/
-DPP_STATUS dpp_tm_crdt_asm_interval_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 index, ZXIC_UINT32 asm_interval_0_data)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, index, 0, 7);
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_CRDT_ASM_INTERVAL_0_CFGr + index,
-                       0,
-                       0,
-                       &asm_interval_0_data);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    return  DPP_OK;
-}
-
-DPP_STATUS dpp_tm_crdt_asm_interval_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 index, ZXIC_UINT32 *p_asm_interval_0_data)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, index, 0, 7);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_asm_interval_0_data);
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_CRDT_ASM_INTERVAL_0_CFGr + index,
-                      0,
-                      0,
-                      p_asm_interval_0_data);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    return  DPP_OK;
-}
-
-/***********************************************************/
-/** rci的级别
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_rci_grade_data
-*
-* @return
-* @remark  无
-* @see
-* @author  wush      @date  2017/10/17
-************************************************************/
-DPP_STATUS dpp_tm_crdt_rci_grade_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_rci_grade_data)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_rci_grade_data);
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_CRDT_RCI_GRADEr,
-                      0,
-                      0,
-                      p_rci_grade_data);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    return  DPP_OK;
-}
-
-DPP_STATUS dpp_tm_crdt_rci_value_r_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_crdt_rci_value_r_data)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_crdt_rci_value_r_data);
-
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_CRDT_CRDT_RCI_VALUE_Rr,
-                      0,
-                      0,
-                      p_crdt_rci_value_r_data);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    return  DPP_OK;
-}
-
-DPP_STATUS dpp_tm_crdt_interval_now_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_crdt_interval_now_data)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_crdt_interval_now_data);
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_CRDT_CRDT_INTERVAL_NOWr,
-                      0,
-                      0,
-                      p_crdt_interval_now_data);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    return  DPP_OK;
-}
-
-/***********************************************************/
-/** 配置crdt interval使能，
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   crdt_interval_en_cfg_data   授权分发间隔使能，1打开，0关闭
-*
-* @return
-* @remark  无
-* @see
-* @author  wush      @date  2017/03/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_interval_en_cfg_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 crdt_interval_en_cfg_data)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_CRDT_CRDT_INTERVAL_EN_CFGr,
-                       0,
-                       0,
-                       &crdt_interval_en_cfg_data);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return  DPP_OK;
-}
-
-/***********************************************************/
-/** 读取crdt interval使能
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   crdt_interval_en_cfg_data   授权分发间隔使能，1打开，0关闭
-*
-* @return
-* @remark  无
-* @see
-* @author  wush      @date  2017/03/27
-************************************************************/
-DPP_STATUS dpp_tm_crdt_interval_en_cfg_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_crdt_interval_en_cfg_data)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_crdt_interval_en_cfg_data);
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_CRDT_CRDT_INTERVAL_EN_CFGr,
-                      0,
-                      0,
-                      p_crdt_interval_en_cfg_data);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    return  DPP_OK;
-}
-
-/***********************************************************/
-/** 屏蔽ucn/asm_rdy的时能信号
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   ucn_rdy_shield_en   是否屏蔽ucn_rdy信号，1屏蔽，0不屏蔽
-* @param   asm_rdy_shield_en   是否屏蔽asm_rdy信号，1屏蔽，0不屏蔽
-*
-* @return
-* @remark  无
-* @see
-* @author  wush      @date  2017/10/17
-************************************************************/
-DPP_STATUS dpp_tm_crdt_ucn_asm_rdy_shield_en_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 ucn_rdy_shield_en, ZXIC_UINT32 asm_rdy_shield_en)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_CRDT_UCN_ASM_RDY_SHIELD_EN_T ucn_rdy_shield_en_data = {0};
-
-    
-
-    ucn_rdy_shield_en_data.ucn_rdy_shield_en = ucn_rdy_shield_en;
-    ucn_rdy_shield_en_data.asm_rdy_shield_en = asm_rdy_shield_en;
-
-        rc = dpp_reg_write(dev_id,
-                           ETM_CRDT_UCN_ASM_RDY_SHIELD_ENr,
-                           0,
-                           0,
-                           &ucn_rdy_shield_en_data);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return  DPP_OK;
-}
-
-DPP_STATUS dpp_tm_crdt_ucn_asm_rdy_shield_en_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_ucn_rdy_shield_en, ZXIC_UINT32 *p_asm_rdy_shield_en)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_CRDT_UCN_ASM_RDY_SHIELD_EN_T ucn_rdy_shield_en_data = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_ucn_rdy_shield_en);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_asm_rdy_shield_en);
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_CRDT_UCN_ASM_RDY_SHIELD_ENr,
-                      0,
-                      0,
-                      &ucn_rdy_shield_en_data);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_ucn_rdy_shield_en = ucn_rdy_shield_en_data.ucn_rdy_shield_en;
-    *p_asm_rdy_shield_en = ucn_rdy_shield_en_data.asm_rdy_shield_en;
-
-    return  DPP_OK;
-}
-
-#endif
-#endif
-
-
-#if ZXIC_REAL("TM_SHAPE")
-
-#if 0
-/***********************************************************/
-/** 把整数分解成(指定位长)最高有效数和(2的)指数位数的形式，data=p_remdata*2^(p_exp)
-* @param   data   需要转换前的数
-* @param   rembitsum   余数的位数
-* @param   p_remdata   余数大小
-* @param   p_exp   指数大小
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/27
-************************************************************/
-DPP_STATUS dpp_tm_rem_and_exp_translate(ZXIC_UINT32 data,
-                                        ZXIC_UINT32 rembitsum,
-                                        ZXIC_UINT32 *p_remdata,
-                                        ZXIC_UINT32 *p_exp)
-{
-    ZXIC_UINT32 i = 0;
-    ZXIC_COMM_CHECK_POINT(p_remdata);
-    ZXIC_COMM_CHECK_POINT(p_exp);
-
-    if ((0 == data) || (0 == rembitsum))
-    {
-        *p_remdata = 0;
-        *p_exp = 0;
-        return DPP_OK;
-    }
-
-    for (i = 1; i <= 32; i++)
-    {
-        /* ZXIC_UINT64位长64位，如果ZXIC_UINT32在，左移32位时会有问题 */
-        if (0 == (data & (((ZXIC_UINT64) 0xffffffff) << i)))
-        {
-            break;
-        }
-    }
-
-    if (i <= rembitsum)
-    {
-        *p_remdata = data;
-        *p_exp = 0;
-    }
-    else
-    {
-        *p_remdata = (data >> (i - rembitsum));
-        *p_exp = i - rembitsum;
-    }
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** shap ram初始化
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/22
-************************************************************/
-DPP_STATUS dpp_tm_shap_ram_init(ZXIC_UINT32 dev_id)
-{
-
-
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 read_times = 30;
-    DPP_ETM_SHAP_SHAP_CFG_INIT_CFG_T shap_ram_cfg_init_t = {0};
-    DPP_ETM_SHAP_SHAP_STA_INIT_CFG_T shap_ram_sta_init_t = {0};
-
-
-    /**RAM初始化**/
-    shap_ram_cfg_init_t.cfg_ram_init_en = 1;
-    rc = dpp_reg_write(dev_id,
-                       ETM_SHAP_SHAP_CFG_INIT_CFGr,
-                       0,
-                       0,
-                       &shap_ram_cfg_init_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    shap_ram_sta_init_t.sta_ram_init_en = 1;
-    rc = dpp_reg_write(dev_id,
-                       ETM_SHAP_SHAP_STA_INIT_CFGr,
-                       0,
-                       0,
-                       &shap_ram_sta_init_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-
-    /**初始化done确认**/
-    do
-    {
-        rc = dpp_reg_read(dev_id,
-                          ETM_SHAP_SHAP_CFG_INIT_CFGr,
-                          0,
-                          0,
-                          &shap_ram_cfg_init_t);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        rc = dpp_reg_read(dev_id,
-                          ETM_SHAP_SHAP_STA_INIT_CFGr,
-                          0,
-                          0,
-                          &shap_ram_sta_init_t);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-        read_times--;
-        zxic_comm_usleep(100);
-
-    }
-    while ((0 == shap_ram_cfg_init_t.cfg_ram_init_done  || 0 == shap_ram_sta_init_t.sta_ram_init_done ) && (read_times > 0));
-
-    if (0 == read_times)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "SHAP RAM init failed!\n");
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
-
-}
-
-#endif
-/***********************************************************/
-/** 配置流队列双桶整形使能及模式
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   db_en     双桶整形使能
-* @param   mode      0:c+e模式，1:c+p模式
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_flow_db_en_set(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 db_en,
-                                       ZXIC_UINT32 mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CRDT_DB_TOKEN_T tm_shape_db_en_t = {0};
-    DPP_ETM_SHAP_TOKEN_MODE_SWITCH_T tm_shap_db_mode_t = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), db_en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1);
-
-
-    tm_shape_db_en_t.db_token = db_en;
-    tm_shap_db_mode_t.token_mode_switch = mode;
-
-    rc = dpp_reg_write(dev,
-                       ETM_CRDT_DB_TOKENr,
-                       0,
-                       0,
-                       &tm_shape_db_en_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    rc = dpp_reg_write(dev,
-                       ETM_SHAP_TOKEN_MODE_SWITCHr,
-                       0,
-                       0,
-                       &tm_shap_db_mode_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取流队列双桶整形使能及模式
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   db_en     双桶整形使能
-* @param   mode      0:c+e模式，1:c+p模式
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_flow_db_en_get(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 *db_en,
-                                       ZXIC_UINT32 *mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CRDT_DB_TOKEN_T tm_shape_db_en_t = {0};
-    DPP_ETM_SHAP_TOKEN_MODE_SWITCH_T tm_shap_db_mode_t = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), db_en);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), mode);
-
-    rc = dpp_reg_read(dev,
-                      ETM_CRDT_DB_TOKENr,
-                      0,
-                      0,
-                      &tm_shape_db_en_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    rc = dpp_reg_read(dev,
-                      ETM_SHAP_TOKEN_MODE_SWITCHr,
-                      0,
-                      0,
-                      &tm_shap_db_mode_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *db_en = tm_shape_db_en_t.db_token;
-    *mode = tm_shap_db_mode_t.token_mode_switch;
-
-    return DPP_OK;
-}
-
-#if 0
-/***********************************************************/
-/** 配置桶深最小单位配置:共8档：0-7
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   token_grain    3’d0：最小单位为128K
-*                         3’d1：最小单位为64k
-*                         3’d2：最小单位为32k
-*                         3’d3：最小单位为16k
-*                         3’d4：最小单位为8k
-*                         3’d5：最小单位为4k
-*                         3’d6：最小单位为2k
-*                         3’d7：最小单位为1k
-*           默认为0，即128K
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_token_grain_set(ZXIC_UINT32 dev_id,
-                                        ZXIC_UINT32 token_grain)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_SHAP_TOKEN_GRAIN_T tm_shape_token_grain_t = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, token_grain, 0, 7);
-
-    tm_shape_token_grain_t.token_grain = token_grain;
-
-    rc = dpp_reg_write(dev_id,
-                       ETM_SHAP_TOKEN_GRAINr,
-                       0,
-                       0,
-                       &tm_shape_token_grain_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-
-}
-
-#endif
-/***********************************************************/
-/** 获取桶深最小单位配置:共8档：0-7
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   token_grain    3’d0：最小单位为128K
-*                         3’d1：最小单位为64k
-*                         3’d2：最小单位为32k
-*                         3’d3：最小单位为16k
-*                         3’d4：最小单位为8k
-*                         3’d5：最小单位为4k
-*                         3’d6：最小单位为2k
-*                         3’d7：最小单位为1k
-*           默认为0，即128K
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_token_grain_get(DPP_DEV_T *dev,
-                                        ZXIC_UINT32 *token_grain)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_SHAP_TOKEN_GRAIN_T tm_shape_token_grain_t = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), token_grain);
-
-
-    rc = dpp_reg_read(dev,
-                      ETM_SHAP_TOKEN_GRAINr,
-                      0,
-                      0,
-                      &tm_shape_token_grain_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *token_grain = tm_shape_token_grain_t.token_grain;
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 配置流或调度器映射到整形参数表的某个ID
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   id        流或调度器编号ETM:0-ABFF,FTM:0-177F
-* @param   profile_id    整形参数表id索引:[0-127]
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_map_table_set(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 id,
-                                      ZXIC_UINT32 profile_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_SHAP_SHAP_BUCKET_MAP_TBL_T tm_shape_map_tbl_t = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), profile_id, 0, 127);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_SCH_DEL_NUM);
-
-    tm_shape_map_tbl_t.shap_map = profile_id;
-
-    rc = dpp_reg_write(dev,
-                       ETM_SHAP_SHAP_BUCKET_MAP_TBLr,
-                       0,
-                       id,
-                       &tm_shape_map_tbl_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 获取流或调度器映射到整形参数表的配置ID
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   id        流或调度器编号ETM:0-ABFF,FTM:0-177F
-* @param   profile_id  整形参数表:[0-127]
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_map_table_get(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 id,
-                                      ZXIC_UINT32 *profile_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_SHAP_SHAP_BUCKET_MAP_TBL_T tm_shape_map_tbl_t = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), profile_id);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0, DPP_ETM_SCH_DEL_NUM);
-
-    rc = dpp_reg_read(dev,
-                      ETM_SHAP_SHAP_BUCKET_MAP_TBLr,
-                      0,
-                      id,
-                      &tm_shape_map_tbl_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    *profile_id = tm_shape_map_tbl_t.shap_map;
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 根据流或调度器id查找对应配置表中的模板id
-           找到直接进行整形配置并返回1；未找到返回0
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   id        流或调度器编号 ETM:0-ABFF,FTM:0-AFF
-* @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
-* @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
-* @return  找到：1，未找到：0
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_find_map_id(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 id,
-                                    ZXIC_UINT32 cir,
-                                    ZXIC_UINT32 cbs)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 table_id = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 2);
-    
-
-    /* 根据id计算归属哪张表：每2K对应一个128项表 */
-    table_id = id / 2048;
-
-    for (i = 1; i < 128; i++)
-    {
-        if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cir == cir &&
-            g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cbs == cbs)
-        {
-            rc = dpp_tm_shape_map_table_set(dev, id, i);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set");
-            g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num++;
-
-            return 1;
-        }
-
-    }
-
-    return 0;
-
-}
-
-/***********************************************************/
-/** 配置流级整形参数
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id   流队列号 ETM:0-9215,FTM:0-2047
-* @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
-* @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
-*                     注：cbs=0 表示关闭整形,即不限速
-* @param   db_en     双桶整形使能，0-单桶，1-双桶
-* @param   eir       eir速率，单位Kb，范围同cir
-* @param   ebs       ebs桶深，单位KB，范围同cbs
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_flow_para_set(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 flow_id,
-                                      ZXIC_UINT32 cir,
-                                      ZXIC_UINT32 cbs,
-                                      ZXIC_UINT32 db_en,
-                                      ZXIC_UINT32 eir,
-                                      ZXIC_UINT32 ebs)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    
-
-    rc = dpp_etm_shape_flow_para_set(dev, flow_id, cir, cbs, db_en, eir, ebs);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_etm_shape_flow_para_set");
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 获取流级整形参数
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id   流队列号 ETM:0-9215,FTM:0-2047
-* @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
-* @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
-*                    注：cbs=0 表示关闭整形,即不限速
-* @param   mode_e    整形模式，0-获取c桶参数，1-获取对应e桶参数
-* @param   p_para_id   整形模板索引：ETM=[0-AFF]，FTM=[0-17F]
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_flow_para_get(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 flow_id,
-                                      ZXIC_UINT32 mode,
-                                      ZXIC_UINT32 *p_para_id,
-                                      DPP_TM_SHAPE_PARA_TABLE *p_flow_para_tbl)
-{
-
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 flow_id_e = 0;
-    ZXIC_UINT32 table_id = 0;
-    ZXIC_UINT32 profile_id = 0;
-    ZXIC_UINT32 bucket_para_n = 0;
-    ZXIC_UINT32 bucket_depth = 0;  /* 实际写入寄存器的桶深，为多少个调节单位 */
-    ZXIC_UINT32 bucket_rate = 0;   /* 实际写入寄存器的速率，为每4096周期添加的字节数 */
-    ZXIC_UINT32 token_grain = 0;   /* 令牌桶调节档位 */
-    ZXIC_UINT32 token_grain_kb[8] = {128, 64, 32, 16, 8, 4, 2, 1}; /* 档位对应值 */
-    DPP_ETM_SHAP_BKT_PARA_TBL_T shap_para_tbl_t = {0};
-
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para_id);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_flow_para_tbl);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0, DPP_ETM_Q_NUM - 1);
-
-    flow_id_e = flow_id + DPP_ETM_Q_NUM;
-
-    table_id = flow_id / 2048;
-
-    /*获取流的profile_id*/
-    if (mode)
-    {
-        table_id = flow_id_e / 2048;
-        rc = dpp_tm_shape_map_table_get(dev, flow_id_e, &profile_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get");
-    }
-    else
-    {
-        rc = dpp_tm_shape_map_table_get(dev, flow_id, &profile_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get");
-
-    }
-
-    /*从寄存器读取流配置参数*/
-    bucket_para_n = table_id * 128 + profile_id;
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), bucket_para_n, 0, 0xAFF);
-
-    rc = dpp_reg_read(dev,
-                      ETM_SHAP_BKT_PARA_TBLr,
-                      0,
-                      bucket_para_n,
-                      &shap_para_tbl_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    bucket_depth = shap_para_tbl_t.bucket_depth;
-    bucket_rate = shap_para_tbl_t.bucket_rate;
-
-    /*数据转换处理*/
-    rc = dpp_tm_shape_token_grain_get(dev, &token_grain);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_token_grain_get");
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_grain, 0, 7);
-
-    *p_para_id = bucket_para_n;
-    p_flow_para_tbl->shape_cbs = bucket_depth * token_grain_kb[token_grain];
-    p_flow_para_tbl->shape_cir = (ZXIC_UINT64)bucket_rate * DPP_TM_SYS_HZ * 8 / ((ZXIC_UINT64)4096 * DPP_TM_KILO_ULL * 64);
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** etm配置流级整形参数
-* @param   dev_id    设备编号
-* @param   flow_id   流队列号 ETM:0-9215,FTM:0-2047
-* @param   cir       cir速率，单位Kb，范围[20Kb - 160Gb]
-* @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
-*                    注：cbs=0 表示关闭整形,即不限速
-* @param   db_en     双桶整形使能，0-单桶，1-双桶
-* @param   eir       eir速率，单位Kb，范围同cir
-* @param   ebs       ebs桶深，单位KB，范围同cbs
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_etm_shape_flow_para_set(DPP_DEV_T *dev,
-                                       ZXIC_UINT32 flow_id,
-                                       ZXIC_UINT32 cir,
-                                       ZXIC_UINT32 cbs,
-                                       ZXIC_UINT32 db_en,
-                                       ZXIC_UINT32 eir,
-                                       ZXIC_UINT32 ebs)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 table_id = 0;
-    ZXIC_UINT32 profile_id = 0;
-    ZXIC_UINT32 total_para_id = 0;
-    ZXIC_UINT32 get_profile_success_flag_c = 0;  /* 当前已配置表中是否找到需要的整形模板 */
-    ZXIC_UINT32 get_profile_success_flag_e = 0;  /* 当前已配置表中是否找到需要的整形模板 */
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 2);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0, DPP_ETM_Q_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cir, DPP_TM_SHAPE_CIR_MIN, DPP_TM_SHAPE_CIR_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cbs, DPP_TM_SHAPE_CBS_MIN, DPP_TM_SHAPE_CBS_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), db_en, 0, 1);
-
-    if (db_en)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), eir, DPP_TM_SHAPE_CIR_MIN, DPP_TM_SHAPE_CIR_MAX);
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), ebs, DPP_TM_SHAPE_CBS_MIN, DPP_TM_SHAPE_CBS_MAX);
-    }
-
-    rc = dpp_tm_global_var_mutex_init();
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_global_var_mutex_init");
-
-    rc = zxic_comm_mutex_lock(&g_dpp_tm_global_var_rw_mutex);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_lock");
-
-    /**双桶开关配置**/
-    rc = dpp_tm_shape_flow_db_en_set(dev, db_en, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_flow_db_en_set", &g_dpp_tm_global_var_rw_mutex);
-
-    /******STEP1:先解除原profile_id映射******/
-    /**处理c桶**/
-    rc = dpp_tm_shape_map_table_get(dev, flow_id, &profile_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get", &g_dpp_tm_global_var_rw_mutex);
-
-    if (profile_id > 0 && (profile_id < DPP_TM_SHAP_MAP_ID_MAX))
-    {
-        /***表示当前有配置整形: 根据id计算归属哪张表：每2K队列对应一个128项表***/
-        table_id = flow_id / 2048;
-
-        if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num != 0)
-        {
-            g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num--;
-
-            if (0 == g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num)
-            {
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_cbs = 0;
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_cir = 0;
-            }
-        }
-    }
-
-    /**处理e桶**/
-    rc = dpp_tm_shape_map_table_get(dev, (flow_id + DPP_ETM_Q_NUM), &profile_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get", &g_dpp_tm_global_var_rw_mutex);
-
-    if (profile_id > 0 && (profile_id < DPP_TM_SHAP_MAP_ID_MAX))
-    {
-        /*表示当前有配置整形*/
-        table_id = (flow_id + DPP_ETM_Q_NUM) / 2048;
-
-        if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num != 0)
-        {
-            g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num--;
-
-            if (0 == g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num)
-            {
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_cbs = 0;
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_cir = 0;
-            }
-        }
-    }
-
-
-    /******STEP2:整形关闭的处理******/
-    if (cbs == 0)
-    {
-        /*关闭c桶e桶整形,并返回函数*/
-        rc = dpp_tm_shape_map_table_set(dev, (flow_id), 0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex);
-        rc = dpp_tm_shape_map_table_set(dev, (flow_id + DPP_ETM_Q_NUM), 0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex);
-
-        rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
-        return DPP_OK;
-    }
-
-    if (ebs == 0 || db_en == 0)
-    {
-        /*关闭e桶整形*/
-        rc = dpp_tm_shape_map_table_set(dev, (flow_id + DPP_ETM_Q_NUM), 0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex);
-        get_profile_success_flag_e = 1;
-
-    }
-
-
-    /******STEP3:整形配置处理,先在现有模板中查找******/
-    /* 单桶整形 :c桶 */
-    if (ebs == 0)
-    {
-        /* 此时只有cbs>0，仅开启c桶整形：先查找c桶整形profile配置 */
-        rc = dpp_tm_shape_find_map_id(dev, flow_id, cir, cbs);
-
-        if (rc)
-        {
-            get_profile_success_flag_c = 1;
-        }
-        else
-        {
-            get_profile_success_flag_c = 0;
-        }
-    }
-    /* 双桶整形 :c+e桶 */
-    else
-    {
-        /* 此时cbs>0,ebs>0：先查找c桶整形profile配置 */
-        rc = dpp_tm_shape_find_map_id(dev, flow_id, cir, cbs);
-
-        if (rc)
-        {
-            get_profile_success_flag_c = 1;
-        }
-        else
-        {
-            get_profile_success_flag_c = 0;
-        }
-
-        /* 查找e桶整形profile配置 */
-        rc = dpp_tm_shape_find_map_id(dev, flow_id + DPP_ETM_Q_NUM, eir, ebs);
-
-        if (rc )
-        {
-            get_profile_success_flag_e = 1;
-        }
-        else
-        {
-            get_profile_success_flag_e = 0;
-        }
-
-    }
-
-    /******STEP4:现有整形模板中未找到所需profile******/
-    if (!get_profile_success_flag_c)
-    {
-        /* 根据id计算归属哪张表：每2K对应一个128项表 */
-        table_id = flow_id / 2048;
-
-        for (i = 1; i < 128;  i++)
-        {
-            if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num == 0)
-            {
-
-                /**********映射模板id********/
-                rc = dpp_tm_shape_map_table_set(dev, flow_id, i);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex);
-
-                /*********整形参数配置********/
-                total_para_id = table_id * 128 + i;
-                rc = dpp_tm_shape_para_set(dev, total_para_id, cir, cbs);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_para_set", &g_dpp_tm_global_var_rw_mutex);
-
-                /********同步更新全局数组******/
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cir = cir;
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cbs = cbs;
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num++;
-
-                get_profile_success_flag_c = 1;
-                break;
-            }
-
-        }
-    }
-
-    if (!get_profile_success_flag_e && ebs)
-    {
-        /* 根据id计算归属哪张表：每2K对应一个128项表 */
-        table_id = (flow_id + DPP_ETM_Q_NUM) / 2048;
-
-        for (i = 1; i < 128; i++)
-        {
-            if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num == 0)
-            {
-
-                /**********映射模板id********/
-                rc = dpp_tm_shape_map_table_set(dev, (flow_id + DPP_ETM_Q_NUM), i);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex);
-
-                /*********整形参数配置********/
-                total_para_id = table_id * 128 + i;
-                rc = dpp_tm_shape_para_set(dev, total_para_id, eir, ebs);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_para_set", &g_dpp_tm_global_var_rw_mutex);
-
-                /********同步更新全局数组******/
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cir = eir;
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cbs = ebs;
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num++;
-
-                get_profile_success_flag_e = 1;
-                break;
-            }
-
-        }
-    }
-
-
-    if (!get_profile_success_flag_c || !get_profile_success_flag_e)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Failure!  Profile resource are FULL!\n");
-        rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
-
-        return DPP_ERR;
-    }
-
-    rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** tm配置调度器整形参数
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   se_id     调度器编号号,用户看到：ETM 0-0x63FF, FTM 0-0x77F
-*                    实际：ETM:0x4800-0xABFF,FTM:0x1000-0x177F
-* @param   pir       pir总速率，单位Kb，范围同cir
-* @param   pbs       pbs总桶深，单位KB，范围同cbs
-* @param   db_en      整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效
-* @param   cir       [0-3]调度器cir速率，单位Kb，范围[64Kb - 160Gb]
-* @param   cbs       [0-3]调度器cbs桶深，单位KB，范围[1KB - 64M]
-*                    注：cbs=0 表示关闭整形,即不限速
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_se_para_set(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 se_id,
-                                    ZXIC_UINT32 pir,
-                                    ZXIC_UINT32 pbs,
-                                    ZXIC_UINT32 db_en,
-                                    ZXIC_UINT32 cir,
-                                    ZXIC_UINT32 cbs)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-
-    rc = dpp_etm_shape_se_para_set(dev, se_id, pir, pbs, db_en, cir, cbs);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_etm_shape_se_para_set");
-    
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 获取调度单元整形参数
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   se_id     调度器单元号 ETM:0-63FF,FTM:0-77F
-* @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
-* @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
-*                     注：cbs=0 表示关闭整形,即不限速
-* @param   mode    整形模式，0-获取p桶参数，1-获取对应c桶参数(仅FQ8/WFQ8支持)
-* @param   p_para_id   整形模板索引：ETM=[0-AFF]，FTM=[0-17F]
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_se_para_get(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 se_id,
-                                    ZXIC_UINT32 mode,
-                                    ZXIC_UINT32 *p_para_id,
-                                    DPP_TM_SHAPE_PARA_TABLE *p_se_para_tbl)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 real_se_id = 0;
-    ZXIC_UINT32 se_id_c = 0;
-    ZXIC_UINT32 table_id = 0;
-    ZXIC_UINT32 profile_id = 0;
-    ZXIC_UINT32 bucket_para_n = 0;
-    ZXIC_UINT32 bucket_depth = 0;  /* 实际写入寄存器的桶深，为多少个调节单位 */
-    ZXIC_UINT32 bucket_rate = 0;   /* 实际写入寄存器的速率，为每4096周期添加的字节数 */
-    ZXIC_UINT32 token_grain = 0;   /* 令牌桶调节档位 */
-    ZXIC_UINT32 token_grain_kb[8] = {128, 64, 32, 16, 8, 4, 2, 1}; /* 档位对应值 */
-    DPP_ETM_SHAP_BKT_PARA_TBL_T shap_para_tbl_t = {0};
-
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para_id);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_para_tbl);
-
-    real_se_id = (se_id + DPP_ETM_SHAP_SEID_BASE);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), real_se_id, 0, DPP_ETM_SCH_DEL_NUM);
-
-
-    se_id_c = real_se_id + 4;
-
-    table_id = real_se_id / 2048;
-
-    /*获取调度器的profile_id*/
-    if (mode)
-    {
-        rc = dpp_tm_shape_map_table_get(dev, se_id_c, &profile_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get");
-    }
-    else
-    {
-        rc = dpp_tm_shape_map_table_get(dev, real_se_id, &profile_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get");
-
-    }
-
-
-    /*从寄存器读取调度器配置参数*/
-    bucket_para_n = table_id * 128 + profile_id;
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), bucket_para_n, 0, 0xAFF);
-
-    rc = dpp_reg_read(dev,
-                      ETM_SHAP_BKT_PARA_TBLr,
-                      0,
-                      bucket_para_n,
-                      &shap_para_tbl_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    bucket_depth = shap_para_tbl_t.bucket_depth;
-    bucket_rate = shap_para_tbl_t.bucket_rate;
-
-    /*数据转换处理*/
-    rc = dpp_tm_shape_token_grain_get(dev, &token_grain);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_token_grain_get");
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_grain, 0, 7);
-
-    *p_para_id = bucket_para_n;
-    p_se_para_tbl->shape_cbs = bucket_depth * token_grain_kb[token_grain];
-    p_se_para_tbl->shape_cir = (ZXIC_UINT64)bucket_rate * DPP_TM_SYS_HZ * 8 / ((ZXIC_UINT64)4096 * DPP_TM_KILO_ULL * 64);
-
-    return DPP_OK;
-
-}
-
-
-
-
-/***********************************************************/
-/** etm配置调度器整形参数
-* @param   dev_id    设备编号
-* @param   se_id     调度器编号号 ETM 0-0x63FF, FTM 0-0x77F
-*                    实际：ETM:0x4800-0xABFF,FTM:0x1000-0x177F
-* @param   pir       pir总速率，单位Kb，范围同cir
-* @param   pbs       pbs总桶深，单位Kb，范围同cbs
-* @param   db_en     整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效
-* @param   cir       [0-3]调度器cir速率，单位Kb，范围[64Kb - 160Gb]
-* @param   cbs       [0-3]调度器cbs桶深，单位KB，范围[1KB - 64M]
-*                    注：cbs=0 表示关闭整形,即不限速
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_etm_shape_se_para_set(DPP_DEV_T *dev,
-                                     ZXIC_UINT32 se_id,
-                                     ZXIC_UINT32 pir,
-                                     ZXIC_UINT32 pbs,
-                                     ZXIC_UINT32 db_en,
-                                     ZXIC_UINT32 cir,
-                                     ZXIC_UINT32 cbs)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 i = 0;    
-    ZXIC_UINT32 real_se_id = 0;
-    ZXIC_UINT32 sch_type = 0;
-    ZXIC_UINT32 sch_type_num = 0;
-    ZXIC_UINT32 table_id = 0;
-    ZXIC_UINT32 profile_id = 0;
-    ZXIC_UINT32 total_para_id = 0;
-    ZXIC_UINT32 get_profile_success_flag_p = 0;  /* 当前已配置表中是否找到需要的p桶整形模板 */
-    ZXIC_UINT32 get_profile_success_flag_c = 0;  /* 当前已配置表中是否找到需要的c桶整形模板 */
-    DPP_ETM_CRDT_SE_PARA_TBL_T crdt_se_para_tabl_t = {0};  /*配置cp双桶模式,仅FQ8/WFQ8使用*/
-    
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 2);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0, DPP_ETM_FQSPWFQ_NUM-1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pir, DPP_TM_SHAPE_CIR_MIN, DPP_TM_SHAPE_CIR_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pbs, DPP_TM_SHAPE_CBS_MIN, DPP_TM_SHAPE_CBS_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), db_en, 0, 1);
-    
-    real_se_id = (se_id + DPP_ETM_SHAP_SEID_BASE);
-
-    if (db_en)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cir, DPP_TM_SHAPE_CIR_MIN, DPP_TM_SHAPE_CIR_MAX);
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cbs, DPP_TM_SHAPE_CBS_MIN, DPP_TM_SHAPE_CBS_MAX);
-    }
-
-    rc = dpp_tm_global_var_mutex_init();
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_global_var_mutex_init");
-
-    rc = zxic_comm_mutex_lock(&g_dpp_tm_global_var_rw_mutex);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_lock");
-
-
-    rc = dpp_tm_crdt_sch_type_get(dev, se_id, &sch_type, &sch_type_num);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_crdt_sch_type_get", &g_dpp_tm_global_var_rw_mutex);
-
-    /**双桶模式配置:crdt模块se_id不用转换**/
-    if (sch_type == 8)
-    {
-
-        for (i = 0; i < 8; i++)
-        {
-            rc = dpp_reg_read(dev,
-                              ETM_CRDT_SE_PARA_TBLr,
-                              0,
-                              se_id + i,
-                              &crdt_se_para_tabl_t);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_reg_read", &g_dpp_tm_global_var_rw_mutex);
-
-            crdt_se_para_tabl_t.cp_token_en = db_en;
-
-            rc = dpp_reg_write(dev,
-                               ETM_CRDT_SE_PARA_TBLr,
-                               0,
-                               se_id + i,
-                               &crdt_se_para_tabl_t);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_reg_write", &g_dpp_tm_global_var_rw_mutex);
-        }
-
-    }
-
-    /******STEP1:先解除原profile_id映射******/
-    /**处理p桶**/
-    rc = dpp_tm_shape_map_table_get(dev, real_se_id, &profile_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get", &g_dpp_tm_global_var_rw_mutex);
-
-    if (profile_id > 0 && (profile_id < DPP_TM_SHAP_MAP_ID_MAX))
-    {
-        /***表示当前有配置整形: 根据id计算归属哪张表：每2K队列对应一个128项表***/
-        table_id = real_se_id / 2048;
-        
-        if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num != 0)
-        {
-            g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num--;
-        }
-    }
-
-    if (sch_type == 8)
-    {
-        /**处理c桶**/
-        rc = dpp_tm_shape_map_table_get(dev, (real_se_id + 4), &profile_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get", &g_dpp_tm_global_var_rw_mutex);
-
-        if (profile_id > 0 && (profile_id < DPP_TM_SHAP_MAP_ID_MAX))
-        {
-            /*表示当前有配置整形*/
-            table_id = (real_se_id + 4) / 2048;
-
-            if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num != 0)
-            {
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_num--;
-            }
-        }
-    }
-
-
-
-    /******STEP2:整形关闭的处理******/
-    if (sch_type < 8)
-    {
-        /**非FQ8/WFQ8类型调度器：无双桶模式**/
-        if (pbs == 0 )
-        {
-            /*关闭p桶整形,并返回函数*/
-            rc = dpp_tm_shape_map_table_set(dev, (real_se_id), 0);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex);
-
-            rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
-
-            return DPP_OK;
-        }
-    }
-    else
-    {
-        /**FQ8/WFQ8类型调度器：考虑双桶**/
-        if (pbs == 0 && db_en == 0)
-        {
-            /*单桶模式：关闭p桶整形,并返回函数*/
-            rc = dpp_tm_shape_map_table_set(dev, (real_se_id), 0);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex);
-
-            rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
-
-            return DPP_OK;
-        }
-
-        if (pbs == 0 && db_en == 1 && cbs == 0)
-        {
-            /*双桶模式：关闭p+c桶整形，并返回函数*/
-            rc = dpp_tm_shape_map_table_set(dev, (real_se_id), 0);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex);
-            rc = dpp_tm_shape_map_table_set(dev, (real_se_id + 4), 0);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex);
-
-            rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
-
-            return DPP_OK;
-        }
-
-    }
-
-
-    /******STEP3:整形配置处理,先在现有模板中查找******/
-    /* 非FQ8/WFQ8类型：仅处理p桶，c桶flag直接至1 */
-    if (sch_type < 8)
-    {
-        /* 查找p桶整形profile配置 */
-        rc = dpp_tm_shape_find_map_id(dev, real_se_id, pir, pbs);
-
-        if (rc)
-        {
-            get_profile_success_flag_p = 1;
-        }
-        else
-        {
-            get_profile_success_flag_p = 0;
-        }
-
-        get_profile_success_flag_c = 1;
-    }
-    else
-    {
-        /* FQ8/WFQ8类型：p+c桶 */
-        if (db_en == 0)
-        {
-            /* 单桶模式：仅查找p桶整形profile配置 */
-            rc = dpp_tm_shape_find_map_id(dev, real_se_id, pir, pbs);
-
-            if (rc)
-            {
-                get_profile_success_flag_p = 1;
-            }
-            else
-            {
-                get_profile_success_flag_p = 0;
-            }
-
-            get_profile_success_flag_c = 1;
-        }
-        else
-        {
-
-            /* 双桶模式：先查找p桶整形profile配置 */
-            if (pbs == 0)
-            {
-                rc = dpp_tm_shape_map_table_set(dev, real_se_id, 0);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex);
-
-                get_profile_success_flag_p = 1;
-            }
-            else
-            {
-                rc = dpp_tm_shape_find_map_id(dev, real_se_id, pir, pbs);
-
-                if (rc)
-                {
-                    get_profile_success_flag_p = 1;
-                }
-                else
-                {
-                    get_profile_success_flag_p = 0;
-                }
-            }
-
-
-            /* 查找c桶整形profile配置 */
-            if (cbs == 0)
-            {
-                rc = dpp_tm_shape_map_table_set(dev, (real_se_id + 4), 0);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex);
-
-                get_profile_success_flag_c = 1;
-            }
-            else
-            {
-                rc = dpp_tm_shape_find_map_id(dev, (real_se_id + 4), cir, cbs);
-
-                if (rc )
-                {
-                    get_profile_success_flag_c = 1;
-                }
-                else
-                {
-                    get_profile_success_flag_c = 0;
-                }
-
-            }
-
-
-        }
-
-
-    }
-
-
-    /******STEP4:现有整形模板中未找到所需profile******/
-    if (!get_profile_success_flag_p)
-    {
-        /* 根据id计算归属哪张表：每2K对应一个128项表 */
-        table_id = real_se_id / 2048;
-
-        for (i = 1; i < 128;  i++)
-        {
-            if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num == 0)
-            {
-
-                /**********映射模板id********/
-                rc = dpp_tm_shape_map_table_set(dev, real_se_id, i);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex);
-
-                /*********整形参数配置********/
-                total_para_id = table_id * 128 + i;
-                rc = dpp_tm_shape_para_set(dev, total_para_id, pir, pbs);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_para_set", &g_dpp_tm_global_var_rw_mutex);
-
-                /********同步更新全局数组******/
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cir = pir;
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cbs = pbs;
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num++;
-
-                get_profile_success_flag_p = 1;
-                break;
-            }
-
-        }
-    }
-
-    if (!get_profile_success_flag_c)
-    {
-        /* 根据id计算归属哪张表：每2K对应一个128项表 */
-        table_id = (real_se_id + 4) / 2048;
-
-        for (i = 1; i < 128; i++)
-        {
-            if (g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num == 0)
-            {
-
-                /**********映射模板id********/
-                rc = dpp_tm_shape_map_table_set(dev, (real_se_id + 4), i);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_map_table_set", &g_dpp_tm_global_var_rw_mutex);
-
-                /*********整形参数配置********/
-                total_para_id = table_id * 128 + i;
-                rc = dpp_tm_shape_para_set(dev, total_para_id, cir, cbs);
-                ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc, "dpp_tm_shape_para_set", &g_dpp_tm_global_var_rw_mutex);
-
-                /********同步更新全局数组******/
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cir = cir;
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_cbs = cbs;
-                g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][i].shape_num++;
-
-                get_profile_success_flag_c = 1;
-                break;
-            }
-
-        }
-    }
-
-
-    if (!get_profile_success_flag_p || !get_profile_success_flag_c)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "Failure!  Profile resource are FULL!\n");
-
-        rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
-        return DPP_ERR;
-    }
-
-    rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 写入流/调度器整形参数配置表
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   total_para_id    整形参数表中模板索引id ETM:0-AFF,FTM:0-17F
-* @param   cir       整形速率(c/e桶统一)
-* @param   cbs       桶深
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_para_set(DPP_DEV_T *dev,
-                                 ZXIC_UINT32 total_para_id,
-                                 ZXIC_UINT32 cir,
-                                 ZXIC_UINT32 cbs)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 bucket_depth = 0;  /* 实际写入寄存器的桶深，为多少个调节单位 */
-    ZXIC_UINT32 bucket_rate = 0;   /* 实际写入寄存器的速率，为每4096周期添加的字节数 */
-    ZXIC_UINT32 token_grain = 0;   /* 令牌桶调节档位 */
-    ZXIC_UINT32 token_grain_kb[8] = {128, 64, 32, 16, 8, 4, 2, 1}; /* 档位对应值 */
-    DPP_ETM_SHAP_BKT_PARA_TBL_T shap_para_tbl_t = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cir, DPP_TM_SHAPE_CIR_MIN, DPP_TM_SHAPE_CIR_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cbs, DPP_TM_SHAPE_CBS_MIN, DPP_TM_SHAPE_CBS_MAX);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), total_para_id, 0, 0xAFF);
-
-
-    /********* 数据转换处理:Begin ********/
-
-    rc = dpp_tm_shape_token_grain_get(dev, &token_grain);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_token_grain_get");
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_grain, 0, 7);
-
-    if (cbs < token_grain_kb[token_grain] && (cbs != 0))
-    {
-        bucket_depth = 1; /* 最小为1个桶深调节单位 */
-    }
-    else
-    {
-        bucket_depth = cbs / token_grain_kb[token_grain];
-    }
-
-    /* 寄存器最大可写范围为[0-2047] */
-    if (bucket_depth > DPP_TM_SHAPE_CBS_REG_MAX)
-    {
-        bucket_depth = DPP_TM_SHAPE_CBS_REG_MAX;
-    }
-
-    /* 平均每周期添加cir*1/64bit，即每4096周期添加的字节数 */
-    //bucket_rate = (ZXIC_UINT64)4096 * cir * DPP_TM_KILO_ULL * 64 / (((ZXIC_UINT64)DPP_TM_SYS_HZ / (ZXIC_UINT64)13393) * 8);
-    bucket_rate = (ZXIC_UINT64)4096 * cir * DPP_TM_KILO_ULL * 64 / ((ZXIC_UINT64)DPP_TM_SYS_HZ * 8);
-    shap_para_tbl_t.bucket_rate = bucket_rate;
-    shap_para_tbl_t.bucket_depth = bucket_depth;
-
-    /******** 数据转换处理:End *********/
-
-    rc = dpp_reg_write(dev,
-                       ETM_SHAP_BKT_PARA_TBLr,
-                       0,
-                       total_para_id,
-                       &shap_para_tbl_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 读取流/调度器整形参数配置表
-* @param   dev_id    设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   total_para_id    整形参数表中模板索引id ETM:0-AFF,FTM:0-17F
-* @param   cir       整形速率(c/e桶统一)
-* @param   cbs       桶深
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/03/11
-************************************************************/
-DPP_STATUS dpp_tm_shape_para_get(DPP_DEV_T *dev,
-                                 ZXIC_UINT32 total_para_id,
-                                 DPP_TM_SHAPE_PARA_TABLE *p_shap_para_tbl)
-{
-
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 token_grain = 0;   /* 令牌桶调节档位 */
-    ZXIC_UINT32 token_grain_kb[8] = {128, 64, 32, 16, 8, 4, 2, 1}; /* 档位对应值 */
-    DPP_ETM_SHAP_BKT_PARA_TBL_T shap_para_tbl_t = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_shap_para_tbl);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), total_para_id, 0, 0xAFF);
-
-
-    /*读取配置*/
-    rc = dpp_reg_read(dev,
-                      ETM_SHAP_BKT_PARA_TBLr,
-                      0,
-                      total_para_id,
-                      &shap_para_tbl_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    /********* 数据转换处理: ********/
-    rc = dpp_tm_shape_token_grain_get(dev, &token_grain);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_token_grain_get");
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_grain, 0, 7);
-
-    p_shap_para_tbl->shape_cbs = shap_para_tbl_t.bucket_depth * token_grain_kb[token_grain];
-    p_shap_para_tbl->shape_cir = (ZXIC_UINT64)shap_para_tbl_t.bucket_rate * DPP_TM_SYS_HZ * 8 / ((ZXIC_UINT64)4096 * DPP_TM_KILO_ULL * 64);
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 配置端口级整形参数  更改整形转换公式
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   port_id   端口号
-* @param   p_para   整形信息:CIR/CBS/EN
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/04/15
-************************************************************/
-DPP_STATUS dpp_tm_shape_pp_para_set(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 port_id,
-                                    const DPP_TM_SHAPE_PP_PARA_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 cir = 0;/* 颗粒度的倍数 */
-    ZXIC_UINT32 cbs = 0;/* Credit的倍数 */
-    ZXIC_UINT32 qmu_credit_value = 0;
-    //ZXIC_FLOAT DPP_TM_SHAPE_CIR_STEP_TEST = 160.069565217 * 1000 * 1000 * 1000 / 0x3FFFFFE;/*测试使用 by xuhb*/
-
-    DPP_ETM_CRDT_PP_WEIGHT_RAM_T pp_weight = {0};
-    DPP_ETM_CRDT_PP_CBS_SHAPE_EN_RAM_T pp_cbs_shape_en = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), p_para->c_en, 0, 1);
-
-    if (p_para->c_en == 0)
-    {
-        rc  = dpp_reg_read(dev,
-                           ETM_CRDT_PP_CBS_SHAPE_EN_RAMr,
-                           0,
-                           port_id,
-                           &pp_cbs_shape_en);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-        pp_cbs_shape_en.pp_c_shap_en = p_para->c_en;
-        rc  = dpp_reg_write(dev,
-                            ETM_CRDT_PP_CBS_SHAPE_EN_RAMr,
-                            0,
-                            port_id,
-                            &pp_cbs_shape_en);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-    }
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), p_para->cir, DPP_TM_SHAPE_CIR_MIN, DPP_TM_SHAPE_CIR_MAX);
-
-        /* 读取授权价值 */
-        rc = dpp_tm_qmu_credit_value_get(dev, &qmu_credit_value);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_qmu_credit_value_get");
-
-        cir = p_para->cir;
-        //cir = (ZXIC_UINT32)(((ZXIC_UINT64)cir * DPP_TM_KILO_ULL) / DPP_TM_SHAPE_CIR_STEP)*(crdt_credit_value / qmu_credit_value);
-        cir = (ZXIC_UINT32)(((ZXIC_UINT64)cir * DPP_TM_KILO_ULL) / DPP_TM_SHAPE_CIR_STEP);
-
-
-
-        /* 解决160Gbps设置出错的问题add by cuiy at 2016-4-15   */
-        if (cir > 0x3FFFFFE)
-        {
-            cir = 0x3FFFFFE;
-        }
-
-        /* 检查以kbyte为单位的CBS */
-        if (qmu_credit_value != 0)
-        {
-            cbs = p_para->cbs;
-            cbs = cbs * DPP_TM_KILO_UL / qmu_credit_value;
-        }
-
-        /* 寄存器写入CBS的最小值为20，小于该值时，整形不准 */
-        if (cbs < DPP_TM_SHAPE_DEFAULT_CBS)
-        {
-            cbs = DPP_TM_SHAPE_DEFAULT_CBS;
-        }
-
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cbs, DPP_TM_SHAPE_DEFAULT_CBS, 0x1ffff);
-
-        pp_cbs_shape_en.pp_cbs = cbs;
-        pp_weight.pp_c_weight = cir;
-        pp_cbs_shape_en.pp_c_shap_en = p_para->c_en;
-
-        rc  = dpp_reg_write(dev,
-                            ETM_CRDT_PP_WEIGHT_RAMr,
-                            0,
-                            port_id,
-                            &pp_weight);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-
-        rc  = dpp_reg_write(dev,
-                            ETM_CRDT_PP_CBS_SHAPE_EN_RAMr,
-                            0,
-                            port_id,
-                            &pp_cbs_shape_en);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
-    }
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 读取端口级整形参数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   port_id   端口号
-* @param   p_para   整形信息:CIR/CBS/EN
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/04/15
-************************************************************/
-DPP_STATUS dpp_tm_shape_pp_para_get(DPP_DEV_T *dev,
-                                    ZXIC_UINT32 port_id,
-                                    DPP_TM_SHAPE_PP_PARA_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 cbs = 0;/* Credit的倍数 */
-    ZXIC_UINT32 cir = 0;/* 颗粒度的倍数 */
-    ZXIC_UINT32 qmu_credit_value = 0;
-
-    DPP_ETM_CRDT_PP_WEIGHT_RAM_T pp_weight = {0};
-    DPP_ETM_CRDT_PP_CBS_SHAPE_EN_RAM_T pp_cbs_shape_en = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1);
-
-    /* 读取授权价值 */
-    rc = dpp_tm_qmu_credit_value_get(dev, &qmu_credit_value);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_qmu_credit_value_get");
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CRDT_PP_WEIGHT_RAMr,
-                       0,
-                       port_id,
-                       &pp_weight);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev,
-                       ETM_CRDT_PP_CBS_SHAPE_EN_RAMr,
-                       0,
-                       port_id,
-                       &pp_cbs_shape_en);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
-
-    cbs = pp_cbs_shape_en.pp_cbs;
-    cir = pp_weight.pp_c_weight;
-    p_para->c_en = pp_cbs_shape_en.pp_c_shap_en;
-    p_para->cir = (ZXIC_UINT32)((ZXIC_UINT64)cir * DPP_TM_SHAPE_CIR_STEP / DPP_TM_KILO_ULL) ;
-    p_para->cbs = (cbs * qmu_credit_value / DPP_TM_KILO_UL);
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 写入端口级整形信息
-* @param   tm_type   0-ETM,1-FTM
-* @param   port_id   端口号0-63
-* @param   cir   单位Kb
-* @param   cbs   单位KB
-* @param   c_en   c桶使能
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/03
-************************************************************/
-DPP_STATUS dpp_tm_shape_pp_para_wr(DPP_DEV_T *dev,
-                                   ZXIC_UINT32 port_id,
-                                   ZXIC_UINT32 cir,
-                                   ZXIC_UINT32 cbs,
-                                   ZXIC_UINT32 c_en)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_TM_SHAPE_PP_PARA_T para = {0};
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0, DPP_TM_PP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), c_en, 0, 1);
-
-    para.cir = cir;
-    para.cbs = cbs;
-    para.c_en = c_en;
-
-    rc = dpp_tm_shape_pp_para_set(dev, port_id, &para);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_pp_para_set");
-
-    return DPP_OK;
-}
-
-#if 0
-/***********************************************************/
-/** 配置第0~15个被统计得到令牌个数的端口号
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   port_id   被统计得到令牌个数的端口号
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/3/15           STM模式下使用
-************************************************************/
-DPP_STATUS dpp_tm_shape_token_pp_cfg(ZXIC_UINT32 dev_id,
-                                     ZXIC_UINT32 port_id)
-{
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 tmp_port = 0;
-    ZXIC_UINT32 i = 0;
-    DPP_ETM_CRDT_Q_TOKEN_STAUE_CFG_T crdt_q_token_staue_cfg = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_id, 0, 63);
-
-    tmp_port = port_id;
-
-    if (tmp_port > 48)
-    {
-        tmp_port = 48;
-    }
-
-    for (i = 0; i < 16; i++)
-    {
-        crdt_q_token_staue_cfg.test_token_q_id = tmp_port + i;
-        rc = dpp_reg_write(dev_id,
-                           ETM_CRDT_Q_TOKEN_STAUE_CFGr,
-                           0,
-                           i,
-                           &crdt_q_token_staue_cfg);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    }
-
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 打印被指定统计的第0~15个端口消耗的令牌个数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  统计时间为2s，其中c桶统计1s，e桶统计1s
-* @see
-* @author  whuashan      @date  2019/03/15
-************************************************************/
-DPP_STATUS dpp_tm_shape_token_dec_cnt_diag(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 dec_num[16] = {0};
-    ZXIC_UINT32 credit_value = 0;
-    ZXIC_UINT32 port_num = 0;
-    ZXIC_FLOAT traffic_amplified = 0.0;
-    ZXIC_UINT32 shape_token_cycle_reg_index = 0;
-    ZXIC_UINT32 shape_q_token_sta_cfg_reg_index = 0;
-    ZXIC_UINT32 shape_test_token_calc_ctrl_reg_index = 0;
-    ZXIC_UINT32 shape_q_token_dec_cnt_reg_index = 0;
-
-    DPP_TM_WORK_MODE_E sa_work_mode = 0;
-    DPP_TM_CNT_MODE_T que_get_mode = {0};
-    DPP_ETM_CRDT_TEST_TOKEN_CALC_CTRL_T shap_test_token_calc_ctrl = {0};
-    DPP_ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUM_T test_token_sample_cycle_num = {0};
-    DPP_ETM_CRDT_Q_TOKEN_STAUE_CFG_T q_token_staue_cfg = {0};
-    DPP_ETM_CRDT_Q_TOKEN_DEC_CNT_T q_token_dec_cnt = {0};
-
-
-    shape_token_cycle_reg_index = ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUMr;
-    shape_q_token_sta_cfg_reg_index = ETM_CRDT_Q_TOKEN_STAUE_CFGr;
-    shape_test_token_calc_ctrl_reg_index = ETM_CRDT_TEST_TOKEN_CALC_CTRLr;
-    shape_q_token_dec_cnt_reg_index = ETM_CRDT_Q_TOKEN_DEC_CNTr;
-
-
-    /* 配置寄存器为读清模式 */
-    rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get");
-    que_get_mode.count_rd_mode = 1;
-
-    rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set");
-
-    /* 获取端口号 */
-    rc = dpp_reg_read(dev_id,
-                      shape_q_token_sta_cfg_reg_index,
-                      0,
-                      0,
-                      &q_token_staue_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    port_num = q_token_staue_cfg.test_token_q_id;
-
-    /* 配置统计的时间，单位是令牌下发周期，令牌下发频率为600M/32 */
-    test_token_sample_cycle_num.sample_cycle_num = 18750000;
-    rc = dpp_reg_write(dev_id,
-                       shape_token_cycle_reg_index,
-                       0,
-                       0,
-                       &test_token_sample_cycle_num);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    /* 启动统计功能 */
-    shap_test_token_calc_ctrl.test_token_calc_trigger = 1;
-    rc = dpp_reg_write(dev_id,
-                       shape_test_token_calc_ctrl_reg_index,
-                       0,
-                       0,
-                       &shap_test_token_calc_ctrl);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    /* 等待统计完成 */
-    rc = dpp_reg_read(dev_id,
-                      shape_test_token_calc_ctrl_reg_index,
-                      0,
-                      0,
-                      &shap_test_token_calc_ctrl);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    while (!shap_test_token_calc_ctrl.test_token_calc_state)
-    {
-        rc = dpp_reg_read(dev_id,
-                          shape_test_token_calc_ctrl_reg_index,
-                          0,
-                          0,
-                          &shap_test_token_calc_ctrl);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    }
-
-    /* 关闭统计功能 */
-    shap_test_token_calc_ctrl.test_token_calc_trigger = 0;
-    rc = dpp_reg_write(dev_id,
-                       shape_test_token_calc_ctrl_reg_index,
-                       0,
-                       0,
-                       &shap_test_token_calc_ctrl);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    /* 读取计数器的计数 */
-    for (i = 0; i < 16; i++)
-    {
-        rc = dpp_reg_read(dev_id,
-                          shape_q_token_dec_cnt_reg_index,
-                          0,
-                          i,
-                          &q_token_dec_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-        dec_num[i] = q_token_dec_cnt.q_token_dec_counter;
-
-    }
-
-
-    rc = dpp_tm_cfgmt_sa_work_mode_get(dev_id, &sa_work_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_sa_work_mode_get");
-
-    if (0 == sa_work_mode)
-    {
-        rc = dpp_tm_qmu_credit_value_get(dev_id, &credit_value);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_credit_value_get");
-    }
-    else if (1 == sa_work_mode)
-    {
-        rc = dpp_tm_qmu_sa_credit_value_get(dev_id, 4, &credit_value);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_sa_credit_value_get");
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "SA work mode error\n");
-        return DPP_ERR;
-    }
-
-
-    /* 计算各级消耗令牌速率:cnt*8*credit_value/(2*cycle_num*32/600M) */
-    traffic_amplified = (ZXIC_FLOAT)(credit_value) * (ZXIC_FLOAT)(8.0) / ( (ZXIC_FLOAT)(2.0) * (ZXIC_FLOAT)(18750000.0));
-
-    for (i = 0; i < 16; i++)
-    {
-        ZXIC_COMM_PRINT("pp_%d:            traffic = %.6f.(M)\n", (port_num + i), (ZXIC_FLOAT)(dec_num[i]) * traffic_amplified);
-    }
-
-
-    /* 配置寄存器为不读清模式 */
-    rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get");
-
-    que_get_mode.count_rd_mode = 0;
-    rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 打印被指定统计的第0~15个端口接收的令牌个数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  统计时间为2s，其中c桶统计1s，e桶统计1s
-* @see
-* @author  whuashan      @date  2019/03/15
-************************************************************/
-DPP_STATUS dpp_tm_shape_token_dist_cnt_diag(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS rc = DPP_OK;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 dist_num[16] = {0};
-    ZXIC_UINT32 credit_value = 0;
-    ZXIC_UINT32 port_num = 0;
-    ZXIC_FLOAT traffic_amplified = 0.0;
-    ZXIC_UINT32 shape_token_cycle_reg_index = 0;
-    ZXIC_UINT32 shape_q_token_sta_cfg_reg_index = 0;
-    ZXIC_UINT32 shape_test_token_calc_ctrl_reg_index = 0;
-    ZXIC_UINT32 shape_q_token_dist_cnt_reg_index = 0;
-    DPP_TM_WORK_MODE_E sa_work_mode = 0;
-    DPP_TM_CNT_MODE_T que_get_mode = {0};
-    DPP_ETM_CRDT_TEST_TOKEN_CALC_CTRL_T shap_test_token_calc_ctrl = {0};
-    DPP_ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUM_T test_token_sample_cycle_num = {0};
-    DPP_ETM_CRDT_Q_TOKEN_STAUE_CFG_T q_token_staue_cfg = {0};
-    DPP_ETM_CRDT_Q_TOKEN_DIST_CNT_T q_token_dist_cnt = {0};
-
-    shape_token_cycle_reg_index = ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUMr;
-    shape_q_token_sta_cfg_reg_index = ETM_CRDT_Q_TOKEN_STAUE_CFGr;
-    shape_test_token_calc_ctrl_reg_index = ETM_CRDT_TEST_TOKEN_CALC_CTRLr;
-    shape_q_token_dist_cnt_reg_index = ETM_CRDT_Q_TOKEN_DIST_CNTr;
-
-    /* 配置寄存器为读清模式 */
-    rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get");
-    que_get_mode.count_rd_mode = 1;
-
-    rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set");
-
-    /* 获取端口号 */
-    rc = dpp_reg_read(dev_id,
-                      shape_q_token_sta_cfg_reg_index,
-                      0,
-                      0,
-                      &q_token_staue_cfg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    port_num = q_token_staue_cfg.test_token_q_id;
-
-    /* 配置统计的时间，单位是令牌下发周期，令牌下发频率为600M/32 */
-    test_token_sample_cycle_num.sample_cycle_num = 18750000;
-    rc = dpp_reg_write(dev_id,
-                       shape_token_cycle_reg_index,
-                       0,
-                       0,
-                       &test_token_sample_cycle_num);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    /* 启动统计功能 */
-    shap_test_token_calc_ctrl.test_token_calc_trigger = 1;
-    rc = dpp_reg_write(dev_id,
-                       shape_test_token_calc_ctrl_reg_index,
-                       0,
-                       0,
-                       &shap_test_token_calc_ctrl);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-    /* 等待统计完成 */
-    rc = dpp_reg_read(dev_id,
-                      shape_test_token_calc_ctrl_reg_index,
-                      0,
-                      0,
-                      &shap_test_token_calc_ctrl);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    while (!shap_test_token_calc_ctrl.test_token_calc_state)
-    {
-        rc = dpp_reg_read(dev_id,
-                          shape_test_token_calc_ctrl_reg_index,
-                          0,
-                          0,
-                          &shap_test_token_calc_ctrl);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-    }
-
-    /* 关闭统计功能 */
-    shap_test_token_calc_ctrl.test_token_calc_trigger = 0;
-    rc = dpp_reg_write(dev_id,
-                       shape_test_token_calc_ctrl_reg_index,
-                       0,
-                       0,
-                       &shap_test_token_calc_ctrl);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    /* 读取c桶计数器的计数 */
-    for (i = 0; i < 16; i++)
-    {
-
-        rc = dpp_reg_read(dev_id,
-                          shape_q_token_dist_cnt_reg_index,
-                          0,
-                          i,
-                          &q_token_dist_cnt);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-        dist_num[i] = q_token_dist_cnt.q_token_dist_counter;
-
-    }
-
-
-    rc = dpp_tm_qmu_credit_value_get(dev_id, &credit_value);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_credit_value_get");
-    rc = dpp_tm_cfgmt_sa_work_mode_get(dev_id, &sa_work_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_sa_work_mode_get");
-
-    if (0 == sa_work_mode)
-    {
-        rc = dpp_tm_qmu_credit_value_get(dev_id, &credit_value);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_credit_value_get");
-    }
-    else if (1 == sa_work_mode)
-    {
-        rc = dpp_tm_qmu_sa_credit_value_get(dev_id, 4, &credit_value);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_sa_credit_value_get");
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "SA work mode error\n");
-        return DPP_ERR;
-    }
-
-    /* 计算各级消耗令牌速率:cnt*8*credit_value/(2*cycle_num*32/600M) */
-    traffic_amplified = (ZXIC_FLOAT)(credit_value) * (ZXIC_FLOAT)(8.0) / ( (ZXIC_FLOAT)(2.0) * (ZXIC_FLOAT)(18750000.0));
-
-    for (i = 0; i < 16; i++)
-    {
-        ZXIC_COMM_PRINT("pp_%d:            traffic = %.6f.(M)\n", (port_num + i), (ZXIC_FLOAT)(dist_num[i]) * traffic_amplified);
-    }
-
-
-    /* 配置寄存器为不读清模式 */
-    rc = dpp_tm_cfgmt_cnt_mode_get(dev_id, &que_get_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_get");
-    que_get_mode.count_rd_mode = 0;
-    rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &que_get_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 打印指定的全局数组值以及清空全局数组
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   para_x   数组index_x
-* @param   para_y   数组index_y
-* @param   clear_flag 清空shape全局数组
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark
-* @see
-* @author  xuhb      @date  2019/06/10
-************************************************************/
-DPP_STATUS dpp_tm_shape_para_array_prt(ZXIC_UINT32 dev_id, ZXIC_UINT32 para_x, ZXIC_UINT32 para_y, ZXIC_UINT32 clear_flag)
-{
-    DPP_STATUS rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 2);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, para_x, 0, 21);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, para_y, 0, 127);
-    ZXIC_COMM_PRINT("cir(kb):%d  cbs(KB):%d  num:%d\n", g_dpp_etm_shape_para_table[dev_id][para_x][para_y].shape_cir,
-              g_dpp_etm_shape_para_table[dev_id][para_x][para_y].shape_cbs,
-              g_dpp_etm_shape_para_table[dev_id][para_x][para_y].shape_num);
-
-    if (clear_flag)
-    {
-        rc = dpp_tm_clr_shape_para(dev_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_clr_shape_para");
-    }
-
-
-    return DPP_OK;
-}
-
-#endif
-/***********************************************************/
-/** 获取全局数组中用户实际配置的整形值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   flow_id   流队列号 ETM:0-9215,FTM:0-2047
-* @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
-* @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
-*                    注：cbs=0 表示关闭整形,即不限速
-* @param   mode_e    整形模式，0-获取c桶参数，1-获取对应e桶参数
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark
-* @see
-* @author  xuhb      @date  2020/09/22
-************************************************************/
-DPP_STATUS dpp_tm_shape_flow_para_array_get(DPP_DEV_T *dev,
-                                      ZXIC_UINT32 flow_id,
-                                      ZXIC_UINT32 mode,
-                                      DPP_TM_SHAPE_PARA_TABLE *p_flow_para_tbl)
-{
-
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 flow_id_e = 0;
-    ZXIC_UINT32 table_id = 0;
-    ZXIC_UINT32 profile_id = 0;
-
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_flow_para_tbl);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0, DPP_ETM_Q_NUM - 1);
-
-    flow_id_e = flow_id + DPP_ETM_Q_NUM;
-
-    table_id = flow_id / 2048;
-
-    /*获取流的profile_id*/
-    if (mode)
-    {
-        table_id = flow_id_e / 2048;
-        rc = dpp_tm_shape_map_table_get(dev, flow_id_e, &profile_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get");
-    }
-    else
-    {
-        rc = dpp_tm_shape_map_table_get(dev, flow_id, &profile_id);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_shape_map_table_get");
-
-    }
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), profile_id, 0, DPP_TM_SHAP_MAP_ID_MAX - 1);
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), table_id, 0, DPP_ETM_SHAP_TABEL_ID_MAX - 1);
-    p_flow_para_tbl->shape_cbs = g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_cbs;
-    p_flow_para_tbl->shape_cir = g_dpp_etm_shape_para_table[DEV_PCIE_SLOT(dev)][table_id][profile_id].shape_cir;
-
-    return DPP_OK;
-
-}
-
-
-
-#if 0
-/***********************************************************/
-/** 配置shap模块中 crd_grain授权价值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   credit_value   授权价值，默认值是0x5feByte
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/08/13
-************************************************************/
-DPP_STATUS dpp_tm_shap_crd_grain_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 credit_value)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_SHAP_CRD_GRAIN_T credit_val = {0};
-
-    credit_val.crd_grain = credit_value;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_SHAP_CRD_GRAINr,
-                        0,
-                        0,
-                        &credit_val);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-#endif
-#endif
-
-#if ZXIC_REAL("TM_EXTEND_API")
-
-#if 0
-/***********************************************************/
-/** 打印队列空标志查询
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   配置的队列号
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/06/20
-************************************************************/
-DPP_STATUS dpp_tm_qlist_ept_flag_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 value = 0;
-
-    rc = dpp_tm_qlist_ept_flag_get(dev_id, qnum, &value);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qlist_ept_flag_get");
-    ZXIC_COMM_PRINT("qlist_ept_flag is %d\n", value);
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 打印队列深度计数
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qnum   配置的队列号
-* @param   p_value  队列深度计数
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/06/20
-************************************************************/
-DPP_STATUS dpp_tm_qlist_r_bcnt_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 qnum)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 value = 0;
-
-    rc = dpp_tm_qlist_r_bcnt_get(dev_id, qnum, &value);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qlist_r_bcnt_get");
-    ZXIC_COMM_PRINT("qlist_r_bcnt is 0x%x\n", value);
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** CMDSCH中分端口分优先级的BLOCK计数
-* @param   dev_id   设备编号
-* @param   pri   
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/09/19
-************************************************************/
-DPP_STATUS dpp_tm_csch_r_block_cnt_get(ZXIC_UINT32 dev_id,
-                                       ZXIC_UINT32 pri,
-                                       ZXIC_UINT32 *p_value)
-{
-    DPP_STATUS rc = DPP_OK;
-    DPP_ETM_QMU_CSCH_R_BLOCK_CNT_T csch_r_block_cnt = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_value);
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_QMU_CSCH_R_BLOCK_CNTr,
-                      0,
-                      pri,
-                      &csch_r_block_cnt);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    *p_value = csch_r_block_cnt.csch_r_block_cnt;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 打印CMDSCH中分端口分优先级的BLOCK计数
-* @param   dev_id   设备编号
-* @param   port   
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/09/19
-************************************************************/
-DPP_STATUS dpp_tm_csch_r_block_cnt_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 port)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 pri = 0;
-    ZXIC_UINT32 pri_th = 0;
-    for(int i = 0; i < 8; ++i)
-    {
-        pri = port * 8 + i;
-        rc = dpp_tm_csch_r_block_cnt_get(dev_id, pri, &pri_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_csch_r_block_cnt_get");
-        ZXIC_COMM_PRINT("csch_r_block_pri 0x%x value is 0x%x\n", pri, pri_th);
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 打印队列入链状态
-* @param   dev_id   设备编号
-* @param   flow_id   
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/09/19
-************************************************************/
-DPP_STATUS dpp_tm_crdt_flow_link_state_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 flow_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 link_status = 0;
-    DPP_ETM_CRDT_FLOWQUE_INS_TBL_T crdt_flow_ins_tbl_t = {0};
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, flow_id, 0, DPP_ETM_CRDT_NUM);    
-    rc = dpp_tm_crdt_flow_link_state_get(dev_id, flow_id, &crdt_flow_ins_tbl_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_flow_link_state_get");
-
-    link_status = crdt_flow_ins_tbl_t.flowque_ins;
-    ZXIC_COMM_PRINT("flowque_ins_tbl flow 0x%x linkstatus is 0x%x\n", flow_id, link_status);
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 打印调度器入链状态
-* @param   dev_id   设备编号
-* @param   flow_id   
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/09/19
-************************************************************/
-DPP_STATUS dpp_tm_crdt_se_link_state_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 se_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 link_status = 0;
-    DPP_ETM_CRDT_SE_INS_TBL_T crdt_se_ins_tbl_t = {0};
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, se_id, 0, DPP_ETM_FQSPWFQ_NUM - 1);    
-    rc = dpp_tm_crdt_se_link_state_get(dev_id, se_id, &crdt_se_ins_tbl_t);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_se_link_state_get");
-
-    link_status = crdt_se_ins_tbl_t.se_ins_flag;
-    ZXIC_COMM_PRINT("flowque_ins_tbl se_id 0x%x linkstatus is 0x%x\n", se_id, link_status);
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 打印olif的fifo是否空状态
-* @param   dev_id   设备编号
-* @param      
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  sun      @date  2023/09/19
-************************************************************/
-DPP_STATUS dpp_tm_olif_fifo_empty_state_get_diag(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 qmu_para_fifo_empty = 0;
-    ZXIC_UINT32 emem_empty = 0;
-    ZXIC_UINT32 imem_empty = 0;
-    DPP_ETM_OLIF_OLIF_FIFO_EMPTY_STATE_T empty_status = {0};
-  
-    rc = dpp_reg_read(dev_id,
-                      ETM_OLIF_OLIF_FIFO_EMPTY_STATEr,
-                      0,
-                      0,
-                      &empty_status);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    qmu_para_fifo_empty = empty_status.qmu_para_fifo_empty;
-    emem_empty = empty_status.emem_empty;
-    imem_empty = empty_status.imem_empty;
-    ZXIC_COMM_PRINT("qmu_para_fifo_empty 0x%x, emem_empty 0x%x, imem_empty 0x%x\n", qmu_para_fifo_empty, emem_empty, imem_empty);
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**
-* @param   dev_id
-* @param   tm_type
-* @param   que_id
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2019/05/08
-************************************************************/
-DPP_STATUS dpp_tm_crdt_eir_crs_filter_en_get_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 que_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CRDT_EIR_CRS_FILTER_TBL_T eir_crs_filter = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, que_id, 0, DPP_ETM_Q_NUM - 1);
-
-    rc = dpp_reg_read(dev_id,
-                      ETM_CRDT_EIR_CRS_FILTER_TBLr,
-                      0,
-                      que_id,
-                      &eir_crs_filter);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    ZXIC_COMM_PRINT("Tm type:%d [0:ftm 1:etm] eir_crs_filter_en:%d [1:enable 0:disable]", eir_crs_filter.eir_crs_filter);
-
-    return rc;
-}
-
-
-
-/***********************************************************/
-/**  读取指定队列获得授权个数(只打印授权非零的队列号)
-* @param   dev_id   设备编号
-* @param   ackflow_start   授权起始流号
-* @param   ackflow_end   授权终止流号
-* @param   sleep_time_ms   等待时间
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2017/01/19
-************************************************************/
-DPP_STATUS dpp_etm_crdt_traffic_diag(ZXIC_UINT32 dev_id,
-                                     ZXIC_UINT32 ackflow_start,
-                                     ZXIC_UINT32 ackflow_end,
-                                     ZXIC_UINT32 sleep_time_ms)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT32 ackflow_id = 0;
-    ZXIC_UINT32 credit_value = 0;
-    ZXIC_FLOAT traffic_amplified = 0.0;
-    ZXIC_FLOAT flow_spec_traffic = 0.0;
-
-    DPP_ETM_CRDT_STAT_QUE_CREDIT_T que_credit = {0};
-    DPP_TM_WORK_MODE_E sa_work_mode = {0};
-    DPP_ETM_CRDT_STAT_QUE_ID_0_T stat_que_id_0 = {0};
-
-    if (ackflow_start > DPP_ETM_Q_NUM - 1)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ackflow_start is out of range!!!\n");
-        return DPP_ERR;
-    }
-
-    if (ackflow_end > DPP_ETM_Q_NUM - 1)
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "ackflow_end is out of range!!!\n");
-        return DPP_ERR;
-    }
-
-    rc = dpp_tm_cfgmt_sa_work_mode_get(dev_id, &sa_work_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_sa_work_mode_get");
-
-    if (0 == sa_work_mode)
-    {
-        rc = dpp_tm_qmu_credit_value_get(dev_id, &credit_value);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_credit_value_get");
-    }
-    else if (1 == sa_work_mode)
-    {
-        rc = dpp_tm_qmu_sa_credit_value_get(dev_id, 4, &credit_value);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_sa_credit_value_get");
-    }
-    else
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "SA work mode error\n");
-        return DPP_ERR;
-    }
-
-    traffic_amplified = ((ZXIC_FLOAT)sleep_time_ms * (ZXIC_FLOAT)(1000000.0)) / ((ZXIC_FLOAT)(8.0) * (ZXIC_FLOAT)(credit_value));
-
-    for (ackflow_id = ackflow_start; ackflow_id <= ackflow_end; ackflow_id += 16)
-    {
-        /* 配置16条授权流 */
-        for (index = 0; index < 16; index++)
-        {
-
-            stat_que_id_0.stat_que_id_0 = ackflow_id + index;
-            rc = dpp_reg_write(dev_id,
-                               ETM_CRDT_STAT_QUE_ID_0r + index,
-                               0,
-                               0,
-                               &stat_que_id_0);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-        }
-
-        /* 授权个数统计计数器清零 */
-        rc = dpp_tm_crdt_clr_diag(0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_clr_diag");
-
-        zxic_comm_sleep(sleep_time_ms);
-        /* 不使能CRDT */
-        rc = dpp_tm_crdt_credit_en_set(dev_id, 0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_credit_en_set");
-
-        for (index = 0; index < 16; index++)
-        {
-
-            rc = dpp_reg_read(dev_id,
-                              ETM_CRDT_STAT_QUE_ID_0r + index,
-                              0,
-                              0,
-                              &stat_que_id_0);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "DPP_reg_read");
-
-            rc = dpp_reg_read(dev_id,
-                              ETM_CRDT_STAT_QUE_CREDITr,
-                              0,
-                              index,
-                              &que_credit);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "DPP_reg_read");
-
-            flow_spec_traffic = (ZXIC_FLOAT)(que_credit.stat_que_credit_cnt) / traffic_amplified;
-
-            if (que_credit.stat_que_credit_cnt != 0)
-            {
-                ZXIC_COMM_PRINT("flow_0x%04x(%5d):   ", (stat_que_id_0.stat_que_id_0), (stat_que_id_0.stat_que_id_0));
-                ZXIC_COMM_PRINT("ack_cnt = 0x%08x,   ", que_credit.stat_que_credit_cnt);
-                ZXIC_COMM_PRINT("traffic = %.6f.(G)\n", flow_spec_traffic);
-            }
-        }
-    }
-
-    /* 使能CRDT */
-    rc = dpp_tm_crdt_credit_en_set(dev_id, 1);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_credit_en_set");
-
-    return DPP_OK;
-}
-
-
-
-/***********************************************************/
-/** 读取QMU所有队列的统计信息
-* @param   dev_id   设备编号
-* @param   p_para   获得的统计信息
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_stat_get(ZXIC_UINT32 dev_id, DPP_ETM_QMU_STAT_INFO_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_FC_CNT_MODE_T fc_cnt_mode_reg = {0};
-    DPP_ETM_QMU_MMU_QMU_WR_FC_CNT_T mmu_qmu_wr_fc_cnt_reg = {0};
-    DPP_ETM_QMU_MMU_QMU_RD_FC_CNT_T mmu_qmu_rd_fc_cnt_reg = {0};
-    DPP_ETM_QMU_QMU_CGAVD_FC_CNT_T qmu_cgavd_fc_cnt_reg = {0};
-    DPP_ETM_QMU_CGAVD_QMU_PKT_CNT_T cgavd_qmu_pkt_cnt_reg = {0};
-    DPP_ETM_QMU_CGAVD_QMU_PKTLEN_ALL_T cgavd_qmu_pktlen_all_reg = {0};
-    DPP_ETM_QMU_LAST_DROP_QNUM_GET_T last_drop_qnum_reg = {0};
-    DPP_ETM_QMU_CRDT_QMU_CREDIT_CNT_T crdt_qmu_credit_cnt_reg = {0};
-    DPP_ETM_QMU_QMU_TO_QSCH_REPORT_CNT_T qmu_to_qsch_report_cnt_reg = {0};
-    DPP_ETM_QMU_QMU_TO_CGAVD_REPORT_CNT_T qmu_to_cgavd_report_cnt_reg = {0};
-    DPP_ETM_QMU_QMU_CRDT_CRS_NORMAL_CNT_T qmu_crdt_crs_normal_cnt_reg = {0};
-    DPP_ETM_QMU_QMU_CRDT_CRS_OFF_CNT_T qmu_crdt_crs_off_cnt_reg = {0};
-    DPP_ETM_QMU_QSCH_QLIST_SHEDULE_CNT_T qsch_qlist_shedule_cnt_reg = {0};
-    DPP_ETM_QMU_QSCH_QLIST_SCH_EPT_CNT_T qsch_qlist_sch_ept_cnt_reg = {0};
-    DPP_ETM_QMU_QMU_TO_MMU_BLK_WR_CNT_T qmu_to_mmu_blk_wr_cnt_reg = {0};
-    DPP_ETM_QMU_QMU_TO_CSW_BLK_RD_CNT_T qmu_to_csw_blk_rd_cnt_reg = {0};
-    DPP_ETM_QMU_QMU_TO_MMU_SOP_WR_CNT_T qmu_to_mmu_sop_wr_cnt_reg = {0};
-    DPP_ETM_QMU_QMU_TO_MMU_EOP_WR_CNT_T qmu_to_mmu_eop_wr_cnt_reg = {0};
-    DPP_ETM_QMU_QMU_TO_MMU_DROP_WR_CNT_T qmu_to_mmu_drop_wr_cnt_reg = {0};
-    DPP_ETM_QMU_QMU_TO_CSW_SOP_RD_CNT_T qmu_to_csw_sop_rd_cnt_reg = {0};
-    DPP_ETM_QMU_QMU_TO_CSW_EOP_RD_CNT_T qmu_to_csw_eop_rd_cnt_reg = {0};
-    DPP_ETM_QMU_QMU_TO_CSW_DROP_RD_CNT_T qmu_to_csw_drop_rd_cnt_reg = {0};
-    DPP_ETM_QMU_MMU_TO_QMU_WR_RELEASE_CNT_T mmu_to_qmu_wr_release_cnt_reg = {0};
-    DPP_ETM_QMU_MMU_TO_QMU_RD_RELEASE_CNT_T mmu_to_qmu_rd_release_cnt_reg = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_FC_CNT_MODEr,
-                       0,
-                       0,
-                       &fc_cnt_mode_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_MMU_QMU_WR_FC_CNTr,
-                       0,
-                       0,
-                       &mmu_qmu_wr_fc_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_MMU_QMU_RD_FC_CNTr,
-                       0,
-                       0,
-                       &mmu_qmu_rd_fc_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QMU_CGAVD_FC_CNTr,
-                       0,
-                       0,
-                       &qmu_cgavd_fc_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_CGAVD_QMU_PKT_CNTr,
-                       0,
-                       0,
-                       &cgavd_qmu_pkt_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_CGAVD_QMU_PKTLEN_ALLr,
-                       0,
-                       0,
-                       &cgavd_qmu_pktlen_all_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_LAST_DROP_QNUM_GETr,
-                       0,
-                       0,
-                       &last_drop_qnum_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_CRDT_QMU_CREDIT_CNTr,
-                       0,
-                       0,
-                       &crdt_qmu_credit_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QMU_TO_QSCH_REPORT_CNTr,
-                       0,
-                       0,
-                       &qmu_to_qsch_report_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QMU_TO_CGAVD_REPORT_CNTr,
-                       0,
-                       0,
-                       &qmu_to_cgavd_report_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QMU_CRDT_CRS_NORMAL_CNTr,
-                       0,
-                       0,
-                       &qmu_crdt_crs_normal_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QMU_CRDT_CRS_OFF_CNTr,
-                       0,
-                       0,
-                       &qmu_crdt_crs_off_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QSCH_QLIST_SHEDULE_CNTr,
-                       0,
-                       0,
-                       &qsch_qlist_shedule_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QSCH_QLIST_SCH_EPT_CNTr,
-                       0,
-                       0,
-                       &qsch_qlist_sch_ept_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QMU_TO_MMU_BLK_WR_CNTr,
-                       0,
-                       0,
-                       &qmu_to_mmu_blk_wr_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QMU_TO_CSW_BLK_RD_CNTr,
-                       0,
-                       0,
-                       &qmu_to_csw_blk_rd_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QMU_TO_MMU_SOP_WR_CNTr,
-                       0,
-                       0,
-                       &qmu_to_mmu_sop_wr_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QMU_TO_MMU_EOP_WR_CNTr,
-                       0,
-                       0,
-                       &qmu_to_mmu_eop_wr_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QMU_TO_MMU_DROP_WR_CNTr,
-                       0,
-                       0,
-                       &qmu_to_mmu_drop_wr_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QMU_TO_CSW_SOP_RD_CNTr,
-                       0,
-                       0,
-                       &qmu_to_csw_sop_rd_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QMU_TO_CSW_EOP_RD_CNTr,
-                       0,
-                       0,
-                       &qmu_to_csw_eop_rd_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_QMU_TO_CSW_DROP_RD_CNTr,
-                       0,
-                       0,
-                       &qmu_to_csw_drop_rd_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_MMU_TO_QMU_WR_RELEASE_CNTr,
-                       0,
-                       0,
-                       &mmu_to_qmu_wr_release_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_MMU_TO_QMU_RD_RELEASE_CNTr,
-                       0,
-                       0,
-                       &mmu_to_qmu_rd_release_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    p_para->fc_cnt_mode               = fc_cnt_mode_reg.fc_cnt_mode;
-    p_para->mmu_qmu_wr_fc_cnt         = mmu_qmu_wr_fc_cnt_reg.mmu_qmu_wr_fc_cnt;
-    p_para->mmu_qmu_rd_fc_cnt         = mmu_qmu_rd_fc_cnt_reg.mmu_qmu_rd_fc_cnt;
-    p_para->qmu_cgavd_fc_cnt          = qmu_cgavd_fc_cnt_reg.qmu_cgavd_fc_cnt;
-    p_para->cgavd_qmu_pkt_cnt         = cgavd_qmu_pkt_cnt_reg.cgavd_qmu_pkt_cnt;
-    p_para->cgavd_qmu_pktlen_all      = cgavd_qmu_pktlen_all_reg.cgavd_qmu_pktlen_all;
-    p_para->cgavd_qmu_drop_tap        = last_drop_qnum_reg.cgavd_qmu_drop_tap;
-    p_para->last_drop_qnum            = last_drop_qnum_reg.last_drop_qnum;
-    p_para->crdt_qmu_credit_cnt       = crdt_qmu_credit_cnt_reg.crdt_qmu_credit_cnt;
-    p_para->qmu_to_qsch_report_cnt    = qmu_to_qsch_report_cnt_reg.qmu_to_qsch_report_cnt;
-    p_para->qmu_to_cgavd_report_cnt   = qmu_to_cgavd_report_cnt_reg.qmu_to_cgavd_report_cnt;
-    p_para->qmu_crdt_crs_normal_cnt   = qmu_crdt_crs_normal_cnt_reg.qmu_crdt_crs_normal_cnt;
-    p_para->qmu_crdt_crs_off_cnt      = qmu_crdt_crs_off_cnt_reg.qmu_crdt_crs_off_cnt;
-    p_para->qsch_qlist_shedule_cnt    = qsch_qlist_shedule_cnt_reg.qsch_qlist_shedule_cnt;
-    p_para->qsch_qlist_sch_ept_cnt    = qsch_qlist_sch_ept_cnt_reg.qsch_qlist_sch_ept_cnt;
-    p_para->qmu_to_mmu_blk_wr_cnt     = qmu_to_mmu_blk_wr_cnt_reg.qmu_to_mmu_blk_wr_cnt;
-    p_para->qmu_to_csw_blk_rd_cnt     = qmu_to_csw_blk_rd_cnt_reg.qmu_to_csw_blk_rd_cnt;
-    p_para->qmu_to_mmu_sop_wr_cnt     = qmu_to_mmu_sop_wr_cnt_reg.qmu_to_mmu_sop_wr_cnt;
-    p_para->qmu_to_mmu_eop_wr_cnt     = qmu_to_mmu_eop_wr_cnt_reg.qmu_to_mmu_eop_wr_cnt;
-    p_para->qmu_to_mmu_drop_wr_cnt    = qmu_to_mmu_drop_wr_cnt_reg.qmu_to_mmu_drop_wr_cnt;
-    p_para->qmu_to_csw_sop_rd_cnt     = qmu_to_csw_sop_rd_cnt_reg.qmu_to_csw_sop_rd_cnt;
-    p_para->qmu_to_csw_eop_rd_cnt     = qmu_to_csw_eop_rd_cnt_reg.qmu_to_csw_eop_rd_cnt;
-    p_para->qmu_to_csw_drop_rd_cnt    = qmu_to_csw_drop_rd_cnt_reg.qmu_to_csw_drop_rd_cnt;
-    p_para->mmu_to_qmu_wr_release_cnt = mmu_to_qmu_wr_release_cnt_reg.mmu_to_qmu_wr_release_cnt;
-    p_para->mmu_to_qmu_rd_release_cnt = mmu_to_qmu_rd_release_cnt_reg.mmu_to_qmu_rd_release_cnt;
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 读取QMU指定队列的计数信息
-* @param   dev_id   设备编号
-* @param   p_para   获得的统计信息
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_spec_q_stat_get(ZXIC_UINT32 dev_id, DPP_ETM_QMU_SPEC_Q_STAT_INFO_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_OBSERVE_PORTFC_SPEC_T observe_portfc_spec_reg = {0};
-    DPP_ETM_QMU_SPEC_LIF_PORTFC_COUNT_T spec_lif_portfc_count_reg = {0};
-    DPP_ETM_QMU_OBSERVE_QNUM_SET_T observe_qnum_set_reg = {0};
-    DPP_ETM_QMU_SPEC_Q_PKT_RECEIVED_T spec_q_pkt_received_reg = {0};
-    DPP_ETM_QMU_SPEC_Q_PKT_DROPPED_T spec_q_pkt_dropped_reg = {0};
-    DPP_ETM_QMU_SPEC_Q_PKT_SCHEDULED_T spec_q_pkt_scheduled_reg = {0};
-    DPP_ETM_QMU_SPEC_Q_WR_CMD_SENT_T spec_q_wr_cmd_sent_reg = {0};
-    DPP_ETM_QMU_SPEC_Q_RD_CMD_SENT_T spec_q_rd_cmd_sent_reg = {0};
-    DPP_ETM_QMU_SPEC_Q_PKT_ENQ_T spec_q_pkt_enq_reg = {0};
-    DPP_ETM_QMU_SPEC_Q_PKT_DEQ_T spec_q_pkt_deq_reg = {0};
-    DPP_ETM_QMU_SPEC_Q_CRDT_UNCON_RECEIVED_T spec_q_crdt_uncon_received_reg = {0};
-    DPP_ETM_QMU_SPEC_Q_CRDT_CONG_RECEIVED_T spec_q_crdt_cong_received_reg = {0};
-    DPP_ETM_QMU_SPEC_Q_CRS_NORMAL_CNT_T spec_q_crs_normal_cnt_reg = {0};
-    DPP_ETM_QMU_SPEC_Q_CRS_OFF_CNT_T spec_q_crs_off_cnt_reg = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_OBSERVE_PORTFC_SPECr,
-                       0,
-                       0,
-                       &observe_portfc_spec_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_LIF_PORTFC_COUNTr,
-                       0,
-                       0,
-                       &spec_lif_portfc_count_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_OBSERVE_QNUM_SETr,
-                       0,
-                       0,
-                       &observe_qnum_set_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_Q_PKT_RECEIVEDr,
-                       0,
-                       0,
-                       &spec_q_pkt_received_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_Q_PKT_DROPPEDr,
-                       0,
-                       0,
-                       &spec_q_pkt_dropped_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_Q_PKT_SCHEDULEDr,
-                       0,
-                       0,
-                       &spec_q_pkt_scheduled_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_Q_WR_CMD_SENTr,
-                       0,
-                       0,
-                       &spec_q_wr_cmd_sent_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_Q_RD_CMD_SENTr,
-                       0,
-                       0,
-                       &spec_q_rd_cmd_sent_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_Q_PKT_ENQr,
-                       0,
-                       0,
-                       &spec_q_pkt_enq_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_Q_PKT_DEQr,
-                       0,
-                       0,
-                       &spec_q_pkt_deq_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_Q_CRDT_UNCON_RECEIVEDr,
-                       0,
-                       0,
-                       &spec_q_crdt_uncon_received_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_Q_CRDT_CONG_RECEIVEDr,
-                       0,
-                       0,
-                       &spec_q_crdt_cong_received_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_Q_CRS_NORMAL_CNTr,
-                       0,
-                       0,
-                       &spec_q_crs_normal_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_Q_CRS_OFF_CNTr,
-                       0,
-                       0,
-                       &spec_q_crs_off_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    p_para->observe_portfc_spec        =  observe_portfc_spec_reg.observe_portfc_spec;
-    p_para->spec_lif_portfc_count      =  spec_lif_portfc_count_reg.spec_lif_portfc_count;
-    p_para->observe_qnum_set           =  observe_qnum_set_reg.observe_qnum_set;
-    p_para->spec_q_pkt_received        =  spec_q_pkt_received_reg.spec_q_pkt_received;
-    p_para->spec_q_pkt_dropped         =  spec_q_pkt_dropped_reg.spec_q_pkt_dropped;
-    p_para->spec_q_pkt_scheduled       =  spec_q_pkt_scheduled_reg.spec_q_pkt_scheduled;
-    p_para->spec_q_wr_cmd_sent         =  spec_q_wr_cmd_sent_reg.spec_q_wr_cmd_sent;
-    p_para->spec_q_rd_cmd_sent         =  spec_q_rd_cmd_sent_reg.spec_q_rd_cmd_sent;
-    p_para->spec_q_pkt_enq             =  spec_q_pkt_enq_reg.spec_q_pkt_enq;
-    p_para->spec_q_pkt_deq             =  spec_q_pkt_deq_reg.spec_q_pkt_deq;
-    p_para->spec_q_crdt_uncon_received =  spec_q_crdt_uncon_received_reg.spec_q_crdt_uncon_received;
-    p_para->spec_q_crdt_cong_received  =  spec_q_crdt_cong_received_reg.spec_q_crdt_cong_received;
-    p_para->spec_q_crs_normal_cnt      =  spec_q_crs_normal_cnt_reg.spec_q_crs_normal_cnt;
-    p_para->spec_q_crs_off_cnt         =  spec_q_crs_off_cnt_reg.spec_q_crs_off_cnt;
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 读取QMU指定队列组的计数信息
-* @param   dev_id   设备编号
-* @param   p_para   获得的统计信息
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/03/04
-************************************************************/
-DPP_STATUS dpp_tm_qmu_spec_bat_stat_get(ZXIC_UINT32 dev_id, DPP_ETM_QMU_SPEC_BAT_STAT_INFO_T *p_para)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_QMU_OBSERVE_BATCH_SET_T observe_batch_set_reg = {0};
-    DPP_ETM_QMU_SPEC_BAT_PKT_RECEIVED_T spec_bat_pkt_received_reg = {0};
-    DPP_ETM_QMU_SPEC_BAT_PKT_DROPPED_T spec_bat_pkt_dropped_reg = {0};
-    DPP_ETM_QMU_SPEC_BAT_BLK_SCHEDULED_T spec_bat_blk_scheduled_reg = {0};
-    DPP_ETM_QMU_SPEC_BAT_WR_CMD_SENT_T spec_bat_wr_cmd_sent_reg = {0};
-    DPP_ETM_QMU_SPEC_BAT_RD_CMD_SENT_T spec_bat_rd_cmd_sent_reg = {0};
-    DPP_ETM_QMU_SPEC_BAT_PKT_ENQ_T spec_bat_pkt_enq_reg = {0};
-    DPP_ETM_QMU_SPEC_BAT_PKT_DEQ_T spec_bat_pkt_deq_reg = {0};
-    DPP_ETM_QMU_SPEC_BAT_CRDT_UNCON_RECEIVED_T spec_bat_crdt_uncon_received_reg = {0};
-    DPP_ETM_QMU_SPEC_BAT_CRDT_CONG_RECEIVED_T spec_bat_crdt_cong_received_reg = {0};
-    DPP_ETM_QMU_SPEC_BAT_CRS_NORMAL_CNT_T spec_bat_crs_normal_cnt_reg = {0};
-    DPP_ETM_QMU_SPEC_BAT_CRS_OFF_CNT_T spec_bat_crs_off_cnt_reg = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_para);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_OBSERVE_BATCH_SETr,
-                       0,
-                       0,
-                       &observe_batch_set_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_BAT_PKT_RECEIVEDr,
-                       0,
-                       0,
-                       &spec_bat_pkt_received_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_BAT_PKT_DROPPEDr,
-                       0,
-                       0,
-                       &spec_bat_pkt_dropped_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_BAT_BLK_SCHEDULEDr,
-                       0,
-                       0,
-                       &spec_bat_blk_scheduled_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_BAT_WR_CMD_SENTr,
-                       0,
-                       0,
-                       &spec_bat_wr_cmd_sent_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_BAT_RD_CMD_SENTr,
-                       0,
-                       0,
-                       &spec_bat_rd_cmd_sent_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_BAT_PKT_ENQr,
-                       0,
-                       0,
-                       &spec_bat_pkt_enq_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_BAT_PKT_DEQr,
-                       0,
-                       0,
-                       &spec_bat_pkt_deq_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_BAT_CRDT_UNCON_RECEIVEDr,
-                       0,
-                       0,
-                       &spec_bat_crdt_uncon_received_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_BAT_CRDT_CONG_RECEIVEDr,
-                       0,
-                       0,
-                       &spec_bat_crdt_cong_received_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_BAT_CRS_NORMAL_CNTr,
-                       0,
-                       0,
-                       &spec_bat_crs_normal_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_QMU_SPEC_BAT_CRS_OFF_CNTr,
-                       0,
-                       0,
-                       &spec_bat_crs_off_cnt_reg);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-
-    p_para->observe_batch_set            =  observe_batch_set_reg.observe_batch_set;
-    p_para->spec_bat_pkt_received        =  spec_bat_pkt_received_reg.spec_bat_pkt_received;
-    p_para->spec_bat_pkt_dropped         =  spec_bat_pkt_dropped_reg.spec_bat_pkt_dropped;
-    p_para->spec_bat_blk_scheduled       =  spec_bat_blk_scheduled_reg.spec_bat_blk_scheduled;
-    p_para->spec_bat_wr_cmd_sent         =  spec_bat_wr_cmd_sent_reg.spec_bat_wr_cmd_sent;
-    p_para->spec_bat_rd_cmd_sent         =  spec_bat_rd_cmd_sent_reg.spec_bat_rd_cmd_sent;
-    p_para->spec_bat_pkt_enq             =  spec_bat_pkt_enq_reg.spec_bat_pkt_enq;
-    p_para->spec_bat_pkt_deq             =  spec_bat_pkt_deq_reg.spec_bat_pkt_deq;
-    p_para->spec_bat_crdt_uncon_received =  spec_bat_crdt_uncon_received_reg.spec_bat_crdt_uncon_received;
-    p_para->spec_bat_crdt_cong_received  =  spec_bat_crdt_cong_received_reg.spec_bat_crdt_cong_received;
-    p_para->spec_bat_crs_normal_cnt      =  spec_bat_crs_normal_cnt_reg.spec_bat_crs_normal_cnt;
-    p_para->spec_bat_crs_off_cnt         =  spec_bat_crs_off_cnt_reg.spec_bat_crs_off_cnt;
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 连续配置各级搬移门限
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   start_id 为起始 队列号或端口号，系统级时，id参数无效
-* @param   value   端口级和系统级时，为搬移门限值，单位为NPPU存包的单位，256B；
-                   流级时为搬移profile_id,0~15
-* @param  num   为队列或端口个数
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  wush      @date  2016/11/19
-************************************************************/
-#ifdef ETM_REAL
-DPP_STATUS dpp_tm_cgavd_move_th_together_wr(ZXIC_UINT32 dev_id,
-                                            DPP_TM_CGAVD_LEVEL_E level,
-                                            ZXIC_UINT32 start_id,
-                                            ZXIC_UINT32 value,
-                                            ZXIC_UINT32 num)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32  i = 0;
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, SYS_LEVEL);
-    
-
-    for (i = 0; i < num; i++)
-    {
-        ZXIC_COMM_CHECK_INDEX_SUB_OVERFLOW(start_id, i);
-        rc  = dpp_tm_cgavd_move_th_set(dev_id, level, start_id + i, value);
-        zxic_comm_usleep(100);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_move_th_set");
-
-    }
-
-    return DPP_OK;
-
-}
-#endif
-#endif
-/***********************************************************/
-/** 连续设置多个队列或端口的TD门限
-* @param   level   层次号，0:队列级，1:端口级
-* @param   tm_type   0-ETM,1-FTM
-* @param   id   起始队列号或端口号
-* @param   td_th   TD门限，单位是KB，转换为block写入寄存器
-* @param   num  需要设置的队列或端口数量
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_td_th_together_wr(DPP_DEV_T *dev,
-                                          ZXIC_UINT32 level,
-                                          ZXIC_UINT32 id,
-                                          ZXIC_UINT32 td_th,
-                                          ZXIC_UINT32 num)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32  i = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, PP_LEVEL);
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev),  id , num);
-
-    for (i = 0; i < num; i++)
-    {
-        rc  = dpp_tm_cgavd_td_th_set(dev, level, id + i, td_th);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_td_th_set");
-    }
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 连续获取多个队列或端口的TD门限
-* @param   level   层次号，0:队列级，1:端口级
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-* @param   id   起始队列号或端口号
-* @param   num  需要设置的队列或端口数量
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy      @date  2016/03/22
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_td_th_together_get(DPP_DEV_T *dev,
-                                           ZXIC_UINT32 level,
-                                           ZXIC_UINT32 id,
-                                           ZXIC_UINT32 num)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32  i = 0;
-    ZXIC_UINT32  td_th = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, PP_LEVEL);
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev),  id , num);
-
-    for (i = 0; i < num; i++)
-    {
-        rc  = dpp_tm_cgavd_td_th_get(dev, level, id + i, &td_th);
-        zxic_comm_delay(5);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_td_th_get");
-
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), id , i);
-        if (level == QUEUE_LEVEL)
-        {
-            ZXIC_COMM_PRINT("   flow_id: 0x%x,   td_th: 0x%x\n", id + i, td_th);
-        }
-        else
-        {
-            ZXIC_COMM_PRINT("   pp_id: 0x%x,   td_th: 0x%x\n", id + i, td_th);
-        }
-
-    }
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 连续配置多个队列或端口是否支持动态门限机制
-* @param   dev_id 设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   id   队列号或端口号
-* @param   en   配置的值，0-不支持动态门限机制，1-支持动态门限机制
-* @param   num   连续配置的队列数
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  djf      @date  2014/02/17
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_dyn_th_en_set_more(DPP_DEV_T *dev,
-                                           DPP_TM_CGAVD_LEVEL_E level,
-                                           ZXIC_UINT32 id,
-                                           ZXIC_UINT32 en,
-                                           ZXIC_UINT32 num)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32  i = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL, PP_LEVEL);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), en, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev),  id , num);
-
-    for (i = 0; i < num; i++)
-    {
-        rc  = dpp_tm_cgavd_dyn_th_en_set(dev, level, id + i, en);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_cgavd_dyn_th_en_set");
-
-    }
-
-    return DPP_OK;
-
-}
-
-#if 0
-/***********************************************************/
-/** 配置各级WRED丢弃曲线对应的参数
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   wred_id   队列级共支持16个WRED组0-15，端口级支持8组0-7
-* @param   dp   共支持8个dp，取值0-7
-* @param   max_th  平均队列深度上限阈值
-* @param   min_th  平均队列深度下限阈值
-* @param   max_p  最大丢弃概率
-* @param   weight   平均队列深度计算权重
-* @param   q_len_th   队列深度阈值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/04/20
-************************************************************/
-DPP_STATUS dpp_tm_wred_dp_line_para_wr(ZXIC_UINT32 dev_id,
-                                       ZXIC_UINT32 level,
-                                       ZXIC_UINT32 wred_id,
-                                       ZXIC_UINT32 dp,
-                                       ZXIC_UINT32 max_th,
-                                       ZXIC_UINT32 min_th,
-                                       ZXIC_UINT32 max_p,
-                                       ZXIC_UINT32 weight,
-                                       ZXIC_UINT32 q_len_th)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_TM_WRED_DP_LINE_PARA_T para = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, PP_LEVEL);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, max_p, 1, DPP_TM_RED_P_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, weight, 0, DPP_TM_CGAVD_WEIGHT_MAX);
-
-    if (QUEUE_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_Q_WRED_NUM - 1);
-    }
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_PP_WRED_NUM - 1);
-    }
-
-    para.max_th = max_th;
-    para.min_th = min_th;
-    para.max_p = max_p;
-    para.weight = weight;
-    para.q_len_th = q_len_th;
-
-    rc = dpp_tm_cgavd_wred_dp_line_para_set(dev_id, level, wred_id, dp, &para);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_wred_dp_line_para_set");
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 配置各级WRED丢弃曲线对应的参数
-* @param   tm_type   0-ETM,1-FTM
-* @param   level   WRED支持层次号，0:队列级，1:端口级
-* @param   wred_id   队列级共支持16个WRED组0-15，端口级支持8组0-7
-* @param   dp   共支持8个dp，取值0-7
-* @param   max_th  平均队列深度上限阈值
-* @param   min_th  平均队列深度下限阈值
-* @param   max_p  最大丢弃概率
-* @param   weight   平均队列深度计算权重
-* @param   q_len_th   队列深度阈值
-* @param   flag   忽略乘法里的当前包长和最大包长比标志位:1为忽略
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy     @date  2015/11/9
-************************************************************/
-DPP_STATUS dpp_tm_wred_dp_line_para_flag_wr(ZXIC_UINT32 dev_id,
-                                            ZXIC_UINT32 level,
-                                            ZXIC_UINT32 wred_id,
-                                            ZXIC_UINT32 dp,
-                                            ZXIC_UINT32 max_th,
-                                            ZXIC_UINT32 min_th,
-                                            ZXIC_UINT32 max_p,
-                                            ZXIC_UINT32 weight,
-                                            ZXIC_UINT32 q_len_th,
-                                            ZXIC_UINT32 flag)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_TM_WRED_DP_LINE_PARA_T para = {0};
-    DPP_ETM_CGAVD_PKE_LEN_CALC_SIGN_T cgavd_pke_len_calc_sign = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, level, QUEUE_LEVEL, PP_LEVEL);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, max_p, 1, DPP_TM_RED_P_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, weight, 0, DPP_TM_CGAVD_WEIGHT_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, flag, 0, 1);
-
-    if (QUEUE_LEVEL == level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_Q_WRED_NUM - 1);
-    }
-    else
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, wred_id, 0, DPP_TM_PP_WRED_NUM - 1);
-    }
-
-    para.max_th = max_th;
-    para.min_th = min_th;
-    para.max_p = max_p;
-    para.weight = weight;
-    para.q_len_th = q_len_th;
-
-    cgavd_pke_len_calc_sign.pke_len_calc_sign = flag;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_PKE_LEN_CALC_SIGNr,
-                        0,
-                        0,
-                        &cgavd_pke_len_calc_sign);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    rc = dpp_tm_cgavd_wred_dp_line_para_set(dev_id, level, wred_id, dp, &para);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_wred_dp_line_para_set");
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 配置CPU设置的报文长度是否参与计算丢弃概率的使能
-* @param   tm_type   0-ETM,1-FTM
-* @param   flag   忽略乘法里的当前包长和最大包长比标志位:1为忽略
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy    @date  2015/11/9
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_wred_pke_len_calc_sign_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 flag)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_ETM_CGAVD_PKE_LEN_CALC_SIGN_T cgavd_pke_len_calc_sign = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, flag, 0, 1);
-
-    cgavd_pke_len_calc_sign.pke_len_calc_sign = flag;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_PKE_LEN_CALC_SIGNr,
-                        0,
-                        0,
-                        &cgavd_pke_len_calc_sign);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-
-}
-
-
-/***********************************************************/
-/** 获取配置CPU设置的报文长度是否参与计算丢弃概率的使能
-* @param   tm_type   0-ETM,1-FTM
-* @param   flag   忽略乘法里的当前包长和最大包长比标志位:1为忽略
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cy     @date  2015/11/9
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_wred_pke_len_calc_sign_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_flag)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    DPP_ETM_CGAVD_PKE_LEN_CALC_SIGN_T cgavd_pke_len_calc_sign = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_flag);
-
-    rc  = dpp_reg_read(dev_id,
-                       ETM_CGAVD_PKE_LEN_CALC_SIGNr,
-                       0,
-                       0,
-                       &cgavd_pke_len_calc_sign);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    *p_flag = cgavd_pke_len_calc_sign.pke_len_calc_sign;
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 配置系统级GRED丢弃曲线对应的参数
-* @param   tm_type   0-ETM,1-FTM
-* @param   dp   共支持8个dp，取值0-7
-* @param   max_th  平均队列深度上限阈值
-* @param   mid_th  平均队列深度中间阈值
-* @param   min_th  平均队列深度下限阈值
-* @param   max_p   最大丢弃概率   1~99
-* @param   weight   平均队列深度计算权重
-* @param   q_len_th   队列深度阈值
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  taq      @date  2015/04/20
-************************************************************/
-DPP_STATUS dpp_tm_gred_dp_line_para_wr(ZXIC_UINT32 dev_id,
-                                       ZXIC_UINT32 dp,
-                                       ZXIC_UINT32 max_th,
-                                       ZXIC_UINT32 mid_th,
-                                       ZXIC_UINT32 min_th,
-                                       ZXIC_UINT32 max_p,
-                                       ZXIC_UINT32 weight,
-                                       ZXIC_UINT32 q_len_th)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_TM_GRED_DP_LINE_PARA_T para = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dp, 0, DPP_TM_DP_NUM - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, max_p, 1, DPP_TM_RED_P_MAX);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, weight, 0, DPP_TM_CGAVD_WEIGHT_MAX);
-
-    para.max_th = max_th;
-    para.mid_th = mid_th;
-    para.min_th = min_th;
-    para.max_p = max_p;
-
-
-    para.weight = weight;
-    para.q_len_th = q_len_th;
-
-    rc = dpp_tm_cgavd_gred_dp_line_para_set(dev_id, dp, &para);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_gred_dp_line_para_set");
-
-
-    return DPP_OK;
-
-}
-
-
-
-/***********************************************************/
-/** 配置olif统计组信息
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   id   olif统计组号
-* @param   all_or_by_port   0-统计所有，1-统计某一端口或某一dest_id
-* @param   i_or_e_sel   10-统计片外，01-统计片内，其他值-统计所有
-* @param   port_or_dest_id_sel   0-统计port，1-统计dest_id
-* @param   port_dest_id   port号或dest_id号
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  cuiy      @date  2016/04/21
-************************************************************/
-DPP_STATUS dpp_tm_olif_stat_set(ZXIC_UINT32 dev_id,
-                                ZXIC_UINT32 id,
-                                ZXIC_UINT32 all_or_by_port,
-                                ZXIC_UINT32 i_or_e_sel,
-                                ZXIC_UINT32 port_or_dest_id_sel,
-                                ZXIC_UINT32 port_dest_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_OLIF_TM_LIF_STAT_CFG_T tm_lif_stat_cft = {0};
-
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, id, 0, 15);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, all_or_by_port, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, i_or_e_sel, 0, 3);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_or_dest_id_sel, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, port_dest_id, 0, 255);
-
-
-    tm_lif_stat_cft.all_or_by_port = all_or_by_port;
-    tm_lif_stat_cft.i_or_e_sel = i_or_e_sel;
-    tm_lif_stat_cft.port_or_dest_id_sel = port_or_dest_id_sel;
-    tm_lif_stat_cft.port_dest_id = port_dest_id;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_OLIF_TM_LIF_STAT_CFGr,
-                        0,
-                        id,
-                        &tm_lif_stat_cft);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/**
-* @param   dev_id
-* @param   tm_type
-* @param   i_or_e_sel
-* @param   port_or_dest_id_sel
-* @param   start_id
-* @param   start_port_dest_id
-* @param   num
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xjw      @date  2018/02/01
-************************************************************/
-DPP_STATUS dpp_tm_olif_stat_set_mul(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 i_or_e_sel,
-                                    ZXIC_UINT32 port_or_dest_id_sel,
-                                    ZXIC_UINT32 start_id,
-                                    ZXIC_UINT32 start_port_dest_id,
-                                    ZXIC_UINT32 num)
-{
-    DPP_STATUS rt = DPP_OK;
-    ZXIC_UINT32 i = 0;
-
-    for (i = 0; i < num; i++)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id, start_port_dest_id, i);
-        ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(dev_id,  start_id , i);
-        
-        rt = dpp_tm_olif_stat_set(dev_id, start_id + i,
-                                  1, i_or_e_sel,  port_or_dest_id_sel, start_port_dest_id + i);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rt, "dpp_reg_write");
-    }
-
-    return rt;
-}
-
-DPP_STATUS dpp_tm_mr_init(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    rc = dpp_tm_qmu_qos_sign_set(dev_id, 0, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_qos_sign_set");
-    rc = dpp_tm_cgavd_q_map_pp_set(dev_id, 0, 60);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_q_map_pp_set");
-    rc = dpp_tm_cgavd_td_byte_block_th_get_diag(dev_id, 1, 60);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_byte_block_th_get_diag");
-    rc = dpp_tm_cgavd_td_byte_block_th_set(dev_id, 0, 0, 1024);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_byte_block_th_set");
-    rc = dpp_tm_cgavd_td_th_set(dev_id, 0, 0, 200);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set");
-    // rc = dpp_tm_shape_pp_para_wr(dev_id, 60, 1000000, 1000, 1);
-    // ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_shape_pp_para_wr");
-    rc = dpp_tm_qmu_port_shape_set(dev_id, 60, 4, 31, 8192, 1);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_port_shape_set");
-    
-    return rc;
-}
-
-#if 0
-/***********************************************************/
-/** 配置TM模式下初始化代码
-* @param   dev_id
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_tm_init_info    配置TM模式下初始化信息包括以下
-*              blk_size    配置qmu block大小：512B[default]/1024B
-*              case_num    QMU初始化场景编号：0/1/2/3...
-*              imem_omem;  0-片内外混合; 1-纯片内;2-纯片外
-*              mode        0-TM; 1-SA
-*
-* @return
-* @remark  无
-* @see
-* @author  whuashan      @date  2015/03/26
-************************************************************/
-DPP_STATUS dpp_tm_asic_init(ZXIC_UINT32 dev_id, DPP_TM_ASIC_INIT_INFO_T *p_tm_asic_init_info)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 case_num = 0;
-    ZXIC_UINT32 blk_size = 0;
-    ZXIC_UINT32 imem_omem = 0;
-    ZXIC_UINT32 mode = 0;
-    //ZXIC_UINT32 port_id = 0;
-    /*ZXIC_UINT32 flow_id_index = 0;*/
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT32 sys_cgavd_td = 0;
-    DPP_TM_CNT_MODE_T cfgmt_count_mode = {0};
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_tm_asic_init_info);
-    
-/*
-    if (tm_type == DPP_ETM)
-    {
-        flow_id_index = DPP_ETM_Q_NUM;
-    }
-    else if (tm_type == DPP_FTM)
-    {
-        flow_id_index = DPP_FTM_Q_NUM;
-    }
-*/
-    case_num = p_tm_asic_init_info->case_num;
-    ZXIC_COMM_PRINT("case_num =:%d TM ASIC INIT START! <======\n", case_num);
-    blk_size = p_tm_asic_init_info->blk_size;
-    imem_omem = p_tm_asic_init_info->imem_omem;
-    mode = p_tm_asic_init_info->mode;
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, mode, 0, 1);
-
-    ZXIC_COMM_PRINT("======>dev_id:%d TM ASIC INIT START! <======\n", dev_id);
-
-    /*开启tm时钟门控使能*/
-    rc  = dpp_tm_cfgmt_clkgate_en_set(dev_id, 1);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_clkgate_en_set");
-    ZXIC_COMM_PRINT("DPP tm clk enable ok\n");
-    zxic_comm_sleep(5);
-    /*开启tm软复位使能*/
-    rc  = dpp_tm_cfgmt_softrst_en_set(dev_id, 1);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_softrst_en_set");
-    ZXIC_COMM_PRINT("DPP tm softrst enable ok\n");
-    zxic_comm_sleep(5);
-
-
-    DPP_ETM_CFGMT_CLKGATE_EN_T timeout = {0};
-    timeout.clkgate_en = 0xfff;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CFGMT_TIMEOUT_LIMITr,
-                        0,
-                        0,
-                        &timeout);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-
-    /* 整包和交织模式:TM模式配置成交织模式 */
-    rc  = dpp_tm_qmu_pkt_blk_mode_set(dev_id, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_pkt_blk_mode_set");
-    ZXIC_COMM_PRINT("DPP tm mode cfg ok\n");
-
-    /* 配置block大小 */
-    rc = dpp_tm_cfgmt_blk_size_set(dev_id, blk_size);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_blk_size_set");
-
-    /* 启动包存储CRC使能 */
-    rc = dpp_tm_cfgmt_crc_en_set(dev_id, 1);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_crc_en_set");
-
-    /* 配置QMU的每chunk节点数：目前配置1chk=8 block */
-    rc = dpp_tm_cfgmt_qmu_work_mode_set(dev_id, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_qmu_work_mode_set");
-    ZXIC_COMM_PRINT("DPP tm qmu_work_mode_set ok\n");
-    /* 计数模式配置 */
-    cfgmt_count_mode.fc_count_mode = 1;  /* 翻转 */
-    cfgmt_count_mode.count_rd_mode = 0;  /* 非读清 */
-    cfgmt_count_mode.count_overflow_mode = 1; /* 允许溢出翻转 */
-    rc = dpp_tm_cfgmt_cnt_mode_set(dev_id, &cfgmt_count_mode);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_cnt_mode_set");
-
-    /* 总缓存字节数=节点数量*节点大小ftm256k etm512k:配置总缓存90% */
-    sys_cgavd_td = (512 * 1024) * blk_size;
-    sys_cgavd_td = sys_cgavd_td / 1024;
-    sys_cgavd_td = sys_cgavd_td / 100 * 90;
-    rc = dpp_tm_cgavd_td_th_set(dev_id, SYS_LEVEL, 0, sys_cgavd_td);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_td_th_set");
-
-    /* 纯片内模式 */
-    dpp_tm_tmmu_imem_en_set(dev_id, 1);
-    dpp_tm_cgavd_imem_omem_set(dev_id, 1, 0);
-    dpp_tm_tmmu_ddr_force_rdy_set(dev_id, 0x3ff);
-
-    /* QMU链表配置：保证16K配置 */
-    rc = dpp_tm_qmu_init_set(dev_id, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_init_set");
-
-    /* 空队列确保门限值配置 */
-    rc = dpp_tm_qmu_crs_th2_set(dev_id, 0, 200);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_crs_th2_set");
-
-    /*crs的e桶产生门限:每个队列可映射16种配置，
-      映射表是cgavd的流队列WRED队列策略组*/
-    for (index = 0 ; index < 16; index++)
-    {
-        rc = dpp_tm_qmu_crs_eir_th_set(dev_id, index, 0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_crs_eir_th_set");
-    }
-
-    /* CRS限速 */
-
-    /* 普通老化使能和配置 */
-    rc = dpp_tm_qmu_pkt_aging_set(dev_id, 0, 0x1ff, 0xff, 0, DPP_ETM_Q_NUM - 1, 1, 0xa);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_pkt_aging_set");
-
-    /* CRDT SHAP配置 */
-    rc  = dpp_tm_crdt_ram_init(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_ram_init");
-    rc  = dpp_tm_shap_ram_init(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_shap_ram_init");
-    /* CRDT 授权使能打开 */
-    rc  = dpp_tm_crdt_credit_en_set(dev_id, 1);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_credit_en_set");
-    ZXIC_COMM_PRINT("dev_id:%d DPP_TM crdt credit enable set success!!!\n", dev_id);
-
-    /* CRDT开启E桶CRS过滤使能(不能打开,会导致延时大) */
-    /*for (index = 0; index < flow_id_index; index++)
-    {
-        rc = dpp_tm_ind_write32(dev_id, MODULE_TM_CRDT, 0x600000 + index, 0);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_move_th_set");
-    }*/
-
-    /*打开flow db_token,配置成c+e*/
-    rc  = dpp_tm_shape_flow_db_en_set(dev_id, 1, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_shape_flow_db_en_set");
-
-    /*开启cgavd平均队列深度归零使能*/
-    rc  = dpp_tm_cgavd_avg_qlen_return_zero_en_set(dev_id, 1);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_avg_qlen_return_zero_en_set");
-
-    rc  = dpp_tm_qmu_qlist_cfgmt_ram_init_done_print(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_qlist_cfgmt_ram_init_done_print");
-
-    /*开启tm时钟门控使能*/
-    // rc  = dpp_tm_cfgmt_clkgate_en_set(dev_id, 1);
-    // ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_clkgate_en_set");
-
-    // /*开启tm软复位使能*/
-    // rc  = dpp_tm_cfgmt_softrst_en_set(dev_id, 1);
-    // ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_softrst_en_set");
-
-    /* 子系统就绪判断 */
-    rc  = dpp_tm_cfgmt_subsystem_rdy_check(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_subsystem_rdy_check");
-
-
-    ZXIC_COMM_PRINT("=====>dev_id:%d TM ASIC INIT END! <======\n", dev_id);
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置TM模式下初始化代码
-* @param   dev_id
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_tm_init_info    配置TM模式下初始化信息包括以下
-*              blk_size    配置qmu block大小：512B[default]/1024B
-*              case_num    QMU初始化场景编号：0/1/2/3...
-*              imem_omem;  0-片内外混合; 1-纯片内;2-纯片外
-*              mode        0-TM; 1-SA
-*
-* @return
-* @remark  无
-* @see
-* @author  szq      @date  2015/03/26
-************************************************************/
-DPP_STATUS dpp_tm_asic_init_diag(ZXIC_UINT32 dev_id, ZXIC_UINT32 blk_size, ZXIC_UINT32 case_num, ZXIC_UINT32 imem_omem, ZXIC_UINT32 mode)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_TM_ASIC_INIT_INFO_T tm_asic_init_info = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 1);
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, blk_size, 256, 1024);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, case_num, 0, 0x99F);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, imem_omem, 0, 2);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, mode, 0, 1);
-
-    tm_asic_init_info.blk_size = blk_size;
-    tm_asic_init_info.case_num = case_num;
-    tm_asic_init_info.imem_omem = imem_omem;
-    tm_asic_init_info.mode = mode;
-    rc = dpp_tm_asic_init(dev_id, &tm_asic_init_info);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_asic_init");
-
-    return DPP_OK;
-}
-
-#endif
-/****************************************************************************
-* 函数名称: dpp_tm_avg_que_len_get
-* 功能描述: 各级平均队列深度获取
-* 输入参数: dev_id: 设备索引编号
-* @param   tm_type   0-ETM,1-FTM
-*           cgavd_level: 拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
-*           que_id: 本级别层次内的队列编号。
-* 输出参数: p_avg_len: 平均队列深度，单位为BLOCK。
-* 返 回 值: DPP_OK-成功，DPP_ERR-失败
-* 其它说明:
-* author  cy      @date  2015/06/29
-*****************************************************************************/
-DPP_STATUS dpp_tm_avg_que_len_get(ZXIC_UINT32 dev_id,
-                                  DPP_TM_CGAVD_LEVEL_E cgavd_level,
-                                  ZXIC_UINT32 que_id,
-                                  ZXIC_UINT32 *p_avg_len)
-{
-    /* 返回值变量定义 */
-    DPP_STATUS  rc = DPP_OK;
-
-    /* 结构体变量定义 */
-    DPP_ETM_CGAVD_PP_AVG_Q_LEN_T cgavd_pp_avg_q_len = {0};
-    DPP_ETM_CGAVD_SYS_AVG_Q_LEN_T cgavd_sys_avg_q_len = {0};
-    DPP_ETM_CGAVD_FLOW_AVG_Q_LEN_T cgavd_flow_avg_q_len = {0};
-
-
-    /* 入参检查 */
-    
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, cgavd_level, QUEUE_LEVEL, SYS_LEVEL);
-
-    if (QUEUE_LEVEL == cgavd_level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, que_id, 0, DPP_ETM_Q_NUM - 1);
-    }
-    else if (PP_LEVEL == cgavd_level)
-    {
-        ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, que_id, 0, DPP_TM_PP_NUM - 1);
-    }
-    else
-    {
-  
-    }
-
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_avg_len);
-
-    switch (cgavd_level)
-    {
-        case QUEUE_LEVEL:
-        {
-            rc = dpp_reg_read(dev_id, ETM_CGAVD_FLOW_AVG_Q_LENr, 0, que_id, &cgavd_flow_avg_q_len);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-            *p_avg_len = cgavd_flow_avg_q_len.flow_avg_q_len;
-            break;
-        }
-
-        case PP_LEVEL:
-        {
-            rc = dpp_reg_read(dev_id, ETM_CGAVD_PP_AVG_Q_LENr, 0, que_id, &cgavd_pp_avg_q_len);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-            *p_avg_len = cgavd_pp_avg_q_len.pp_avg_q_len;
-            break;
-        }
-
-        case SYS_LEVEL:
-        {
-            rc = dpp_reg_read(dev_id, ETM_CGAVD_SYS_AVG_Q_LENr, 0, 0, &cgavd_sys_avg_q_len);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_read");
-            *p_avg_len = cgavd_sys_avg_q_len.sys_avg_q_len;
-            break;
-        }
-
-        default:
-        {
-            ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "[dev_id %d] cgavd_level is out of dev_id!!!\n", dev_id);
-            return DPP_ERR;
-        }
-    }
-
-    return DPP_OK;
-}
-
-#endif
-/***********************************************************/
-/** 清除整形表格里面的值
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/16
-************************************************************/
-DPP_STATUS dpp_tm_clr_shape_para(DPP_DEV_T *dev)
-{
-    /*DPP_STATUS  rc = DPP_OK;*/
-
-/*    rc = dpp_tm_global_var_mutex_init();
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_global_var_mutex_init");
-
-    rc = zxic_comm_mutex_lock(&g_dpp_tm_global_var_rw_mutex);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "zxic_comm_mutex_lock");*/
-
-    // ZXIC_COMM_CHECK_POINT(dev);
-    // ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 2);
-
-    memset(g_dpp_etm_shape_para_table[0], 0, 256 * 22 * 128 * sizeof(DPP_TM_SHAPE_PARA_TABLE));
-
-
-/*    rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "zxic_comm_mutex_unlock");*/
-    return DPP_OK;
-
-}
-
-#if 0
-/***********************************************************/
-/** 配置CFGMT中断屏蔽
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   shap_int_mask_flag  shap模块中断屏蔽位  0:不屏蔽   1:屏蔽
-* @param   crdt_int_mask_flag  crdt模块中断屏蔽位
-* @param   mmu_int_mask_flag   mmu模块中断屏蔽位
-* @param   qmu_int_mask_flag  qmu模块中断屏蔽位
-* @param   cgavd_int_mask_flag  cgavd模块中断屏蔽位
-* @param   olif_int_mask_flag  olif模块中断屏蔽位
-* @param   cfgmt_int_buf_mask_flag  cfgmt模块中断屏蔽位
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/08
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_int_mask_set_diag(ZXIC_UINT32 dev_id,
-                                          ZXIC_UINT32 shap_int_mask_flag,
-                                          ZXIC_UINT32 crdt_int_mask_flag,
-                                          ZXIC_UINT32 mmu_int_mask_flag,
-                                          ZXIC_UINT32 qmu_int_mask_flag,
-                                          ZXIC_UINT32 cgavd_int_mask_flag,
-                                          ZXIC_UINT32 olif_int_mask_flag,
-                                          ZXIC_UINT32 cfgmt_int_buf_mask_flag)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CFGMT_REG_INT_MASK_REG_T int_mask = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, shap_int_mask_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, crdt_int_mask_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, mmu_int_mask_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qmu_int_mask_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, cgavd_int_mask_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, olif_int_mask_flag, 0, 1);
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, cfgmt_int_buf_mask_flag, 0, 1);
-
-    int_mask.shap_int_mask      = shap_int_mask_flag;
-    int_mask.crdt_int_mask      = crdt_int_mask_flag;
-    int_mask.tmmu_int_mask       = mmu_int_mask_flag;
-    int_mask.qmu_int_mask       = qmu_int_mask_flag;
-    int_mask.cgavd_int_mask     = cgavd_int_mask_flag;
-    int_mask.olif_int_mask      = olif_int_mask_flag;
-    int_mask.cfgmt_int_buf_mask = cfgmt_int_buf_mask_flag;
-
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CFGMT_REG_INT_MASK_REGr,
-                        0,
-                        0,
-                        &int_mask);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取CFGMT中断状态
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_para   中断状态
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/08
-************************************************************/
-DPP_STATUS dpp_tm_cfgmt_int_state_get_diag(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    rc = dpp_reg_fields_print_with_def(dev_id, ETM_CFGMT_REG_INT_STATE_REGr, 0, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取olif中断状态
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/08
-************************************************************/
-DPP_STATUS dpp_tm_olif_int_state_get(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    rc = dpp_reg_fields_print_with_def(dev_id, ETM_OLIF_ITMHRAM_PARITY_ERR_2_INTr, 0, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def");
-
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置OLIF中断屏蔽
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   crcram_parity_err_mask    0:不屏蔽   1:屏蔽
-* @param   itmhram_parity_err_mask
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/08
-************************************************************/
-DPP_STATUS dpp_tm_olif_int_mask_set(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 olif_int_mask_flag)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_OLIF_OLIF_INT_MASK_T int_mask = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, olif_int_mask_flag, 0, 1);
-
-    int_mask.crcram_parity_err_mask = olif_int_mask_flag;
-    int_mask.emem_fifo_ecc_mask = olif_int_mask_flag;
-    int_mask.emem_fifo_ovf_mask = olif_int_mask_flag;
-    int_mask.emem_fifo_udf_mask = olif_int_mask_flag;
-    int_mask.imem_fifo_ecc_mask = olif_int_mask_flag;
-    int_mask.imem_fifo_ovf_mask = olif_int_mask_flag;
-    int_mask.imem_fifo_udf_mask = olif_int_mask_flag;
-    int_mask.itmh_ecc_double_err_mask = olif_int_mask_flag;
-    int_mask.itmh_ecc_single_err_mask = olif_int_mask_flag;
-    int_mask.order_fifo_ovf_mask = olif_int_mask_flag;
-    int_mask.order_fifo_parity_err_mask = olif_int_mask_flag;
-    int_mask.order_fifo_udf_mask = olif_int_mask_flag;
-    int_mask.para_fifo_ecc_mask = olif_int_mask_flag;
-    int_mask.para_fifo_ovf_mask = olif_int_mask_flag;
-    int_mask.para_fifo_udf_mask = olif_int_mask_flag;
-
-    rc  = dpp_reg_write(dev_id,
-                        ETM_OLIF_OLIF_INT_MASKr,
-                        0,
-                        0,
-                        &int_mask);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置cgavd中断屏蔽
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   cgavd_int_mask_flag    0:不屏蔽   1:屏蔽
-* @param   写1 屏蔽cgavd中断寄存器和cgavd_ram_err寄存器所有位
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/08
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_int_mask_set(ZXIC_UINT32 dev_id,
-                                     ZXIC_UINT32 cgavd_int_mask_flag)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CGAVD_CGAVD_INT_MASK_T cgavd_int_mask = {0};
-    DPP_ETM_CGAVD_CGAVD_RAM_ERR_INT_MASK_T cgavd_ram_err_int_mask = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, cgavd_int_mask_flag, 0, 1);
-
-
-    cgavd_int_mask.cgavd_int_mask = cgavd_int_mask_flag;
-    cgavd_ram_err_int_mask.flow_qlen_inta_mask = cgavd_int_mask_flag;
-    cgavd_ram_err_int_mask.flow_qlen_intb_mask = cgavd_int_mask_flag;
-    cgavd_ram_err_int_mask.flow_qnum_inta_mask = cgavd_int_mask_flag;
-    cgavd_ram_err_int_mask.flow_qnum_intb_mask = cgavd_int_mask_flag;
-    cgavd_ram_err_int_mask.flow_tdth_inta_mask = cgavd_int_mask_flag;
-    cgavd_ram_err_int_mask.flow_tdth_intb_mask = cgavd_int_mask_flag;
-
-    cgavd_ram_err_int_mask.pds_deal_fifo_ov_int_mask = cgavd_int_mask_flag;
-    cgavd_ram_err_int_mask.pds_deal_fifo_uv_int_mask = cgavd_int_mask_flag;
-    cgavd_ram_err_int_mask.pp_qlen_inta_mask = cgavd_int_mask_flag;
-    cgavd_ram_err_int_mask.pp_qlen_intb_mask = cgavd_int_mask_flag;
-    cgavd_ram_err_int_mask.pp_tdth_int_mask = cgavd_int_mask_flag;
-    cgavd_ram_err_int_mask.qmu_cgavd_fifo_ov_int_mask = cgavd_int_mask_flag;
-    cgavd_ram_err_int_mask.qmu_cgavd_fifo_uv_int_mask = cgavd_int_mask_flag;
-
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_CGAVD_INT_MASKr,
-                        0,
-                        0,
-                        &cgavd_int_mask);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CGAVD_CGAVD_RAM_ERR_INT_MASKr,
-                        0,
-                        0,
-                        &cgavd_ram_err_int_mask);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取cgavd中断状态
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_para   中断状态
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/08
-************************************************************/
-DPP_STATUS dpp_tm_cgavd_int_state_get(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-
-    rc = dpp_reg_fields_print_with_def(dev_id, ETM_CGAVD_CGAVD_INTr, 0, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def");
-
-    rc = dpp_reg_fields_print_with_def(dev_id, ETM_CGAVD_CGAVD_RAM_ERRr, 0, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取tmmu中断状态
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   p_para   中断状态
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/08
-************************************************************/
-DPP_STATUS dpp_tm_tmmu_int_state_get(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    rc = dpp_reg_fields_print_with_def(dev_id, ETM_TMMU_TMMU_STATES_1r, 0, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def");
-
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置crdt中断屏蔽
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   crdt_int_mask_flag    0:不屏蔽   1:屏蔽
-* @param   写1   屏蔽ETM_CGAVD_RD_CPU_OR_RAMr
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/4/10
-************************************************************/
-DPP_STATUS dpp_tm_crdt_int_mask_set(ZXIC_UINT32 dev_id,
-                                    ZXIC_UINT32 crdt_int_mask_flag)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CRDT_CRDT_INT_MASK_T crdt_int_mask = {0};
-
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, crdt_int_mask_flag, 0, 1);
-
-
-    crdt_int_mask.crdt_int_mask = crdt_int_mask_flag;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CRDT_CRDT_INT_MASKr,
-                        0,
-                        0,
-                        &crdt_int_mask);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取crdt中断状态
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/4/10
-************************************************************/
-DPP_STATUS dpp_tm_crdt_int_state_get(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-
-    rc = dpp_reg_fields_print_with_def(dev_id, ETM_CRDT_CRDT_INT_BUSr, 0, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置qmu中断屏蔽
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   qmu_int_mask_flag    0:不屏蔽   1:屏蔽
-* @param   写1  屏蔽qmu_int_mask5的所有位
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_int_mask_set(ZXIC_UINT32 dev_id,
-                                   ZXIC_UINT32 qmu_int_mask_flag)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 qmu_qsch_crbal_init_mask_reg_index = 0;
-    ZXIC_UINT32 qmu_int_mask1_reg_index = 0;
-    ZXIC_UINT32 qmu_int_mask2_reg_index = 0;
-    ZXIC_UINT32 qmu_int_mask3_reg_index = 0;
-    ZXIC_UINT32 qmu_int_mask4_reg_index = 0;
-    ZXIC_UINT32 qmu_int_mask5_reg_index = 0;
-
-    DPP_ETM_QMU_QCFG_QSCH_CRBAL_INIT_MASK_T qmu_qsch_crbal_init_mask = {0};
-    DPP_ETM_QMU_QMU_INT_MASK1_T qmu_int_mask1 = {0};
-    DPP_ETM_QMU_QMU_INT_MASK2_T qmu_int_mask2 = {0};
-    DPP_ETM_QMU_QMU_INT_MASK3_T qmu_int_mask3 = {0};
-    DPP_ETM_QMU_QMU_INT_MASK4_T qmu_int_mask4 = {0};
-    DPP_ETM_QMU_QMU_INT_MASK5_T qmu_int_mask5 = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, qmu_int_mask_flag, 0, 1);
-
-    qmu_qsch_crbal_init_mask_reg_index = ETM_QMU_QCFG_QSCH_CRBAL_INIT_MASKr;
-    qmu_int_mask1_reg_index = ETM_QMU_QMU_INT_MASK1r;
-    qmu_int_mask2_reg_index = ETM_QMU_QMU_INT_MASK2r;
-    qmu_int_mask3_reg_index = ETM_QMU_QMU_INT_MASK3r;
-    qmu_int_mask4_reg_index = ETM_QMU_QMU_INT_MASK4r;
-    qmu_int_mask5_reg_index = ETM_QMU_QMU_INT_MASK5r;
-
-    qmu_qsch_crbal_init_mask.qcfg_qsch_crbal_init_mask = qmu_int_mask_flag;
-
-    qmu_int_mask1.qmu_int_mask1 = qmu_int_mask_flag;
-    qmu_int_mask2.qmu_int_mask2 = qmu_int_mask_flag;
-    qmu_int_mask3.qmu_int_mask3 = qmu_int_mask_flag;
-    qmu_int_mask4.qmu_int_mask4 = qmu_int_mask_flag;
-    qmu_int_mask5.qmu_int_mask5 = qmu_int_mask_flag;
-
-    rc  = dpp_reg_write(dev_id,
-                        qmu_qsch_crbal_init_mask_reg_index,
-                        0,
-                        0,
-                        &qmu_qsch_crbal_init_mask);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    rc  = dpp_reg_write(dev_id,
-                        qmu_int_mask1_reg_index,
-                        0,
-                        0,
-                        &qmu_int_mask1);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    rc  = dpp_reg_write(dev_id,
-                        qmu_int_mask2_reg_index,
-                        0,
-                        0,
-                        &qmu_int_mask2);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    rc  = dpp_reg_write(dev_id,
-                        qmu_int_mask3_reg_index,
-                        0,
-                        0,
-                        &qmu_int_mask3);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    rc  = dpp_reg_write(dev_id,
-                        qmu_int_mask4_reg_index,
-                        0,
-                        0,
-                        &qmu_int_mask4);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    rc  = dpp_reg_write(dev_id,
-                        qmu_int_mask5_reg_index,
-                        0,
-                        0,
-                        &qmu_int_mask5);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 读取qmu中断状态
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/09
-************************************************************/
-DPP_STATUS dpp_tm_qmu_int_state_get(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    rc = dpp_reg_fields_print_with_def(dev_id, ETM_QMU_QLIST_CFGMT_FIFO_STATEr, 0, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def");
-    rc = dpp_reg_fields_print_with_def(dev_id, ETM_QMU_CMD_SCH_CFGMT_FIFO_STATEr, 0, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def");
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置shape中断屏蔽
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   shape_int_mask_flag    0:不屏蔽   1:屏蔽
-* @param   写1   屏蔽ETM_CGAVD_RD_CPU_OR_RAMr
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/4/10
-************************************************************/
-DPP_STATUS dpp_tm_shape_int_mask_set(ZXIC_UINT32 dev_id,
-                                     ZXIC_UINT32 shape_int_mask_flag)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CRDT_SHAP_INT_MASK_REG_T shap_int_mask = {0};
-
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, shape_int_mask_flag, 0, 1);
-
-    shap_int_mask.pp_c_token_min_int_mask = shape_int_mask_flag;
-    rc  = dpp_reg_write(dev_id,
-                        ETM_CRDT_SHAP_INT_MASK_REGr,
-                        0,
-                        0,
-                        &shap_int_mask);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_write");
-
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 读取shape中断状态
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  whuashan      @date  2019/4/10
-************************************************************/
-DPP_STATUS dpp_tm_shape_int_state_get(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-    DPP_ETM_CRDT_SHAP_INT_REG_T shap_int_reg_t = {0};
-
-    rc = dpp_reg_fields_print_with_def(dev_id, ETM_CRDT_SHAP_INT_REGr, 0, 0);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_reg_fields_print_with_def");
-
-
-    ZXIC_COMM_PRINT("pp_c_token_min_int : %d\n", shap_int_reg_t.pp_c_token_min_int);
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 配置dpp tm所有模块中断屏蔽
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   int_mask_flag    0:不屏蔽   1:屏蔽
-* @param
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/09
-************************************************************/
-DPP_STATUS dpp_tm_int_mask_set(ZXIC_UINT32 dev_id,
-                               ZXIC_UINT32 int_mask_flag)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, int_mask_flag, 0, 1);
-    
-
-    rc = dpp_tm_cfgmt_int_mask_set_diag(dev_id,
-                                        int_mask_flag,
-                                        int_mask_flag,
-                                        int_mask_flag,
-                                        int_mask_flag,
-                                        int_mask_flag,
-                                        int_mask_flag,
-                                        int_mask_flag);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_int_mask_set_diag");
-
-    rc = dpp_tm_olif_int_mask_set(dev_id, int_mask_flag);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_olif_int_mask_set");
-
-    rc = dpp_tm_cgavd_int_mask_set(dev_id, int_mask_flag);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_int_mask_set");
-
-    rc = dpp_tm_shape_int_mask_set(dev_id, int_mask_flag);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_shape_int_mask_set");
-
-    rc = dpp_tm_crdt_int_mask_set(dev_id, int_mask_flag);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_int_mask_set");
-
-    rc = dpp_tm_qmu_int_mask_set(dev_id, int_mask_flag);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_int_mask_set");
-
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 打印dpp tm所有模块中断状态
-* @param   tm_type   0-ETM,1-FTM
-* @param   dev_id   设备编号
-* @param
-* @param
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  yjd      @date  2015/07/09
-************************************************************/
-DPP_STATUS diag_dpp_tm_int(ZXIC_UINT32 dev_id)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    ZXIC_COMM_PRINT("**************************************\n");
-    ZXIC_COMM_PRINT("dpp tm cfgmt int state\n");
-    ZXIC_COMM_PRINT("**************************************\n");
-    rc = dpp_tm_cfgmt_int_state_get_diag(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cfgmt_int_state_get_diag");
-
-    ZXIC_COMM_PRINT("**************************************\n");
-    ZXIC_COMM_PRINT("dpp tm olif int state\n");
-    ZXIC_COMM_PRINT("**************************************\n");
-    rc = dpp_tm_olif_int_state_get(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_olif_int_state_get");
-
-    ZXIC_COMM_PRINT("**************************************\n");
-    ZXIC_COMM_PRINT("dpp tm cgavd int state\n");
-    ZXIC_COMM_PRINT("**************************************\n");
-    rc = dpp_tm_cgavd_int_state_get(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_cgavd_int_state_get");
-
-    ZXIC_COMM_PRINT("**************************************\n");
-    ZXIC_COMM_PRINT("dpp tm tmmu int state\n");
-    ZXIC_COMM_PRINT("**************************************\n");
-    rc = dpp_tm_tmmu_int_state_get(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_tmmu_int_state_get");
-
-    ZXIC_COMM_PRINT("**************************************\n");
-    ZXIC_COMM_PRINT("dpp tm shap int state\n");
-    ZXIC_COMM_PRINT("**************************************\n");
-    rc = dpp_tm_shape_int_state_get(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_shape_int_state_get");
-
-    ZXIC_COMM_PRINT("**************************************\n");
-    ZXIC_COMM_PRINT("dpp tm crdt int state\n");
-    ZXIC_COMM_PRINT("**************************************\n");
-    rc = dpp_tm_crdt_int_state_get(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_crdt_int_state_get");
-
-    ZXIC_COMM_PRINT("**************************************\n");
-    ZXIC_COMM_PRINT("dpp tm qmu int state\n");
-    ZXIC_COMM_PRINT("**************************************\n");
-    rc = dpp_tm_qmu_int_state_get(dev_id);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_int_state_get");
-
-    ZXIC_COMM_PRINT("**************************************\n");
-    ZXIC_COMM_PRINT("dpp tm qmu int case_no\n");
-    ZXIC_COMM_PRINT("**************************************\n");
-    ZXIC_COMM_PRINT("g_qmu_init_case_no = 0x%x\n", g_qmu_init_case_no);
-
-    return DPP_OK;
-}
-
-
-/***********************************************************/
-/** 获取tm.c中qmu_init_set中配置的case_num
-* @param   tm_type   0-ETM,1-FTM
-* @param   dev_id   设备编号
-* @param
-* @param
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/04/15
-************************************************************/
-DPP_STATUS dpp_tm_case_no_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *case_no)
-{
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, case_no);
-
-    *case_no = g_qmu_init_case_no;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 配置tm授权价值总接口,包含qmu授权价值、shap授权价值、FTM对应授权价值版本设置
-* @param   dev_id   设备编号
-* @param   tm_type   0-ETM,1-FTM
-* @param   credit_value   授权价值，默认值是0x5feByte
-*
-* @return   DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  xuhb      @date  2020/08/13
-************************************************************/
-DPP_STATUS dpp_tm_credit_value_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 credit_value)
-{
-    DPP_STATUS  rc = DPP_OK;
-
-    rc = dpp_tm_qmu_credit_value_set(dev_id, credit_value);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_qmu_credit_value_set");
-
-    rc = dpp_tm_shap_crd_grain_set(dev_id, credit_value);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "dpp_tm_shap_crd_grain_set");
-
-    return DPP_OK;
-}
-
-#endif
-#endif
-
-#if ZXIC_REAL("TM_CPU_SOFT_RESET")
-#if 0
-/***********************************************************/
-/**  设置TM的全局变量，shape_para只保存profile被使用的数量，整形相关参数从寄存器中重新读取
-* @param   dev_id
-* @param   size         data_buff的长度
-* @param   p_data_buff  需要恢复的内容
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2017/03/09
-************************************************************/
-DPP_STATUS dpp_tm_glb_mgr_set(ZXIC_UINT32 dev_id, ZXIC_UINT32 size, ZXIC_UINT8 *p_data_buff)
-{
-    DPP_STATUS  rc = DPP_OK;
-    ZXIC_UINT32 shape_table_profile_num = 128;
-    static ZXIC_UINT32 etm_shape_num[22][128] = {{0}};
-    ZXIC_UINT32 total_para_id = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-    DPP_TM_SHAPE_PARA_TABLE shap_para_tbl_t = {0};
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 2);
-    
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_data_buff);
-
-    rc = zxic_comm_mutex_lock(&g_dpp_tm_global_var_rw_mutex);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "zxic_comm_mutex_lock");
-
-    if (size != (22 * 128 * sizeof(ZXIC_UINT32)))
-    {
-        ZXIC_COMM_TRACE_DEV_ERROR(dev_id, "date is not complete.size[%d] err!!\n", size);
-        rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
-        ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "zxic_comm_mutex_unlock");
-
-        return DPP_ERR;
-    }
-
-    ZXIC_COMM_MEMCPY(etm_shape_num, p_data_buff, 22 * 128 * sizeof(ZXIC_UINT32));
-
-
-    /* ETM: set flow and se profile to cpu mem */
-    for (i = 0; i < 22; i++)
-    {
-        for (j = 0; j < shape_table_profile_num; j++)
-        {
-            total_para_id = i * shape_table_profile_num + j;
-
-            rc = dpp_tm_shape_para_get(dev_id, total_para_id, &shap_para_tbl_t);
-            ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(dev_id, rc, "dpp_tm_shape_para_get", &g_dpp_tm_global_var_rw_mutex);
-
-            g_dpp_etm_shape_para_table[dev_id][i][j].shape_num = etm_shape_num[i][j];
-            g_dpp_etm_shape_para_table[dev_id][i][j].shape_cbs = shap_para_tbl_t.shape_cbs;
-            g_dpp_etm_shape_para_table[dev_id][i][j].shape_cir = shap_para_tbl_t.shape_cir;
-
-        }
-    }
-
-
-    rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
-    ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(dev_id, rc, "zxic_comm_mutex_unlock");
-
-    return DPP_OK;
-
-}
-
-/***********************************************************/
-/** 获取TM的全局变量，shape_para只保存profile被使用的数量，整形相关参数从寄存器中重新读取
-* @param   dev_id
-* @param   p_flag           上层释放data_buff的标志，1:需要上层free,0:不需要上层free
-* @param   p_size           data_buff的长度
-* @param   pp_data_buff     二级指针(指向函数内部malloc空间的地址)
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2017/03/09
-************************************************************/
-DPP_STATUS dpp_tm_glb_mgr_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_flag, ZXIC_UINT32 *p_size, ZXIC_UINT8 **pp_data_buff)
-{
-    ZXIC_UINT32 size = 0;
-    static ZXIC_UINT32 etm_shape_num[22][128] = {{0}};
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 j = 0;
-
-    ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(dev_id, dev_id, 0, DPP_DEV_CHANNEL_MAX - 2);
-    
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_flag);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_size);
-
-    size = 22 * 128 * sizeof(ZXIC_UINT32);
-    *pp_data_buff = ZXIC_COMM_MALLOC(size);
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, *pp_data_buff);
-
-    for (i = 0; i < 22; i++)
-    {
-        for (j = 0; j < 128; j++)
-        {
-            etm_shape_num[i][j] = g_dpp_etm_shape_para_table[dev_id][i][j].shape_num;
-        }
-
-    }
-
-    ZXIC_COMM_MEMCPY(*pp_data_buff, etm_shape_num, 22 * 128 * sizeof(ZXIC_UINT32));
-
-
-    *p_flag = 1;
-    *p_size = size;
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 获取TM的全局变量大小，shape_para只保存profile被使用的数量，整形相关参数从寄存器中重新读取
-* @param   dev_id
-* @param   p_size         data_buff的长度
-*
-* @return
-* @remark  无
-* @see
-* @author  XXX      @date  2017/03/09
-************************************************************/
-DPP_STATUS dpp_tm_glb_size_get(ZXIC_UINT32 dev_id, ZXIC_UINT32 *p_size)
-{
-    
-    ZXIC_COMM_CHECK_DEV_POINT(dev_id, p_size);
-
-    *p_size = 22 * 128 * sizeof(ZXIC_UINT32);
-
-    return DPP_OK;
-}
-
-#endif
-#endif
-
-
-
-
-
-
-
-
-
-
-
-
-
+/**************************************************************
+* 版权所有 (C)2013-2015,深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_tm.c
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : djf
+* 完成日期 : 2014/02/17
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+/******************************************************************************
+ *                START: 头文件                                *
+ *****************************************************************************/
+#include "zxic_common.h"
+#include "dpp_type_api.h"
+#include "dpp_reg_api.h"
+#include "dpp_reg_info.h"
+#include "dpp_etm_reg.h"
+#include "dpp_module.h"
+#include "dpp_tm_api.h"
+//#include "dpp_tm_diag.h"
+#include "dpp_tm.h"
+#include "dpp_dev.h"
+
+/******************************************************************************
+ *                 END: 头文件                                 *
+ *****************************************************************************/
+
+/******************************************************************************
+ *               START: 常量定义                               *
+ *****************************************************************************/
+
+DPP_TM_SHAPE_PARA_TABLE g_dpp_etm_shape_para_table
+		[DPP_DEV_CHANNEL_MAX - 1][DPP_ETM_SHAP_TABEL_ID_MAX]
+		[DPP_TM_SHAP_MAP_ID_MAX] = {
+			{ { { 0 } } }
+		}; /* coverity告警修改：单一变量不能超过10000字节 */
+DPP_TM_SHAPE_PARA_TABLE g_dpp_ftm_shape_para_table[DPP_DEV_CHANNEL_MAX]
+												  [DPP_FTM_SHAP_TABEL_ID_MAX]
+												  [DPP_TM_SHAP_MAP_ID_MAX] = {
+													  { { { 0 } } }
+												  };
+DPP_ETM_QMU_INIT_PARA g_dpp_etm_qmu_qlist_para = { 0 };
+DPP_FTM_QMU_INIT_PARA g_dpp_ftm_qmu_qlist_para = { 0 };
+
+/* 全局变量读写互斥锁 */
+ZXIC_MUTEX_T g_dpp_tm_global_var_rw_mutex;
+ZXIC_UINT32 g_dpp_tm_global_var_rw_mutex_flag;
+// static ZXIC_UINT32 g_qmu_init_case_no = 0;
+
+/***********************************************************/
+/** 全局变量读写互斥锁初始化
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/07/23
+ ************************************************************/
+DPP_STATUS dpp_tm_global_var_mutex_init(ZXIC_VOID)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	if (!g_dpp_tm_global_var_rw_mutex_flag) {
+		rc = zxic_comm_mutex_create(&g_dpp_tm_global_var_rw_mutex);
+		ZXIC_COMM_CHECK_RC(rc, "zxic_comm_mutex_create");
+
+		g_dpp_tm_global_var_rw_mutex_flag = 1;
+	}
+
+	return DPP_OK;
+}
+
+/******************************************************************************
+ *                END: 常量定义                                *
+ *****************************************************************************/
+
+#if ZXIC_REAL("TM_REG")
+
+#endif
+
+#if ZXIC_REAL("TM_CFGMT")
+/***********************************************************/
+/** cpu读写通道验证，其读出值等于写入值。读出值不等于写入值时，返回err
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/04/09
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_cpu_check(DPP_DEV_T *dev)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 input = 0x5a5a5a5a;
+	ZXIC_UINT32 output = 0;
+	DPP_ETM_CFGMT_CPU_CHECK_REG_T cpu_access_input = { 0 };
+	DPP_ETM_CFGMT_CPU_CHECK_REG_T cpu_access_output = { 0 };
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	cpu_access_input.cpu_check_reg = input;
+	rc = dpp_reg_write(dev, ETM_CFGMT_CPU_CHECK_REGr, 0, 0, &cpu_access_input);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	rc = dpp_reg_read(dev, ETM_CFGMT_CPU_CHECK_REGr, 0, 0, &cpu_access_output);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	output = cpu_access_output.cpu_check_reg;
+
+	/* 判断读出值是否等于写入值 */
+	if (input != output) {
+		ZXIC_COMM_TRACE_ERROR("dpp_tm_cpu_check :input != output");
+		return DPP_ERR;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置内置TM的工作模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   mode   配置的值，0-TM模式，1-SA模式
+ *ETM仅工作在TM模式，FTM可以工作TM或SA模式
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/25
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_sa_work_mode_set(DPP_DEV_T *dev,
+										 DPP_TM_WORK_MODE_E mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CFGMT_TM_SA_WORK_MODE_T tm_sa_mode = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, DPP_TM_WORK_MODE_TM,
+										DPP_TM_WORK_MODE_TM);
+
+	tm_sa_mode.tm_sa_work_mode = mode;
+	rc = dpp_reg_write(dev, ETM_CFGMT_TM_SA_WORK_MODEr, 0, 0, &tm_sa_mode);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取内置TM的工作模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_mode   读取的值，0-TM模式，1-SA模式
+ *ETM仅工作在TM模式，FTM可以工作TM或SA模式
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/25
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_sa_work_mode_get(DPP_DEV_T *dev,
+										 DPP_TM_WORK_MODE_E *p_mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CFGMT_TM_SA_WORK_MODE_T tm_sa_mode = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mode);
+
+	*p_mode = DPP_TM_WORK_MODE_INVALID;
+
+	rc = dpp_reg_read(dev, ETM_CFGMT_TM_SA_WORK_MODEr, 0, 0, &tm_sa_mode);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_mode = tm_sa_mode.tm_sa_work_mode;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置ddr3挂接组数，共10bit[0-9]，每bit对应1组ddr，TM最多使用其中8组
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   ddr_num   单个tm使用的ddr组：bit[0-9]每bit代表一组ddr，如使用4567组，则配置0xf0
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/06/07
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_ddr_attach_set(DPP_DEV_T *dev, ZXIC_UINT32 ddr_num)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CFGMT_CFGMT_DDR_ATTACH_T ddr_attach = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), ddr_num, 0, 0x3FF);
+
+	ddr_attach.cfgmt_ddr_attach = ddr_num;
+	rc = dpp_reg_write(dev, ETM_CFGMT_CFGMT_DDR_ATTACHr, 0, 0, &ddr_attach);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取ddr3挂接组数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_ddr_num   ddr组数,1-6组
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/04/09
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_ddr_attach_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_ddr_num)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CFGMT_CFGMT_DDR_ATTACH_T ddr_attach = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_ddr_num);
+
+	rc = dpp_reg_read(dev, ETM_CFGMT_CFGMT_DDR_ATTACHr, 0, 0, &ddr_attach);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	if (ddr_attach.cfgmt_ddr_attach == 1) {
+		*p_ddr_num = 1;
+	} else if (ddr_attach.cfgmt_ddr_attach == 3) {
+		*p_ddr_num = 2;
+	} else if (ddr_attach.cfgmt_ddr_attach == 7) {
+		*p_ddr_num = 3;
+	} else if (ddr_attach.cfgmt_ddr_attach == 15) {
+		*p_ddr_num = 4;
+	} else if (ddr_attach.cfgmt_ddr_attach == 31) {
+		*p_ddr_num = 5;
+	} else if (ddr_attach.cfgmt_ddr_attach == 63) {
+		*p_ddr_num = 6;
+	} else if (ddr_attach.cfgmt_ddr_attach == 127) {
+		*p_ddr_num = 7;
+	} else if (ddr_attach.cfgmt_ddr_attach == 255) {
+		*p_ddr_num = 8;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置QMU工作模式，0：8 block工作模式，1：16 block工作模式
+*** (即一个chunk中block个数) 影响tm总可用的缓存节点数。
+* @param   dev_id   设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @param   mode   0-128/256K节点，1-256/512K节点，目前固定配1
+*
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  djf      @date  2014/02/25
+************************************************************/
+DPP_STATUS dpp_tm_cfgmt_qmu_work_mode_set(DPP_DEV_T *dev,
+										  DPP_TM_QMU_WORK_MODE_E mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CFGMT_QMU_WORK_MODE_T qmu_mode = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode,
+										DPP_TM_QMU_WORK_MODE_2M,
+										DPP_TM_QMU_WORK_MODE_4M);
+
+	qmu_mode.qmu_work_mode = mode;
+	rc = dpp_reg_write(dev, ETM_CFGMT_QMU_WORK_MODEr, 0, 0, &qmu_mode);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取QMU工作模式，0：8 block工作模式，1：16 block工作模式
+*** (即一个chunk中block个数) 影响tm总可用的缓存节点数。
+* @param   dev_id   设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @param   mode   0-128/256K节点，1-256/512K节点，目前固定配1
+*
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  djf      @date  2014/02/25
+************************************************************/
+DPP_STATUS dpp_tm_cfgmt_qmu_work_mode_get(DPP_DEV_T *dev,
+										  DPP_TM_QMU_WORK_MODE_E *p_mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CFGMT_QMU_WORK_MODE_T qmu_mode = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mode);
+
+	rc = dpp_reg_read(dev, ETM_CFGMT_QMU_WORK_MODEr, 0, 0, &qmu_mode);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_mode = qmu_mode.qmu_work_mode;
+
+	return DPP_OK;
+}
+/***********************************************************/
+/** 配置block长度模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   size   block长度模式:256/512/1024
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/04/09
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_blk_size_set(DPP_DEV_T *dev, ZXIC_UINT32 size)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CFGMT_CFGMT_BLKSIZE_T blk_size = { 0 };
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	switch (size) {
+	case 256: {
+		blk_size.cfgmt_blksize = DPP_ETM_BLK_SIZE_256_B;
+		break;
+	}
+
+	case 512: {
+		blk_size.cfgmt_blksize = DPP_ETM_BLK_SIZE_512_B;
+		break;
+	}
+
+	case 1024: {
+		blk_size.cfgmt_blksize = DPP_ETM_BLK_SIZE_1024_B;
+		break;
+	}
+
+	default: {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev),
+				"dpp_tm_cfgmt_blk_size_set:TM set block size error!\n");
+		return DPP_ERR;
+	}
+	}
+
+	rc = dpp_reg_write(dev, ETM_CFGMT_CFGMT_BLKSIZEr, 0, 0, &blk_size);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取block长度模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_size   block长度模式，256/512/1024
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/04/09
+ ************************************************************/
+DPP_STATUS dpp_tm_cfgmt_blk_size_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_size)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CFGMT_CFGMT_BLKSIZE_T blk_size = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_size);
+
+	rc = dpp_reg_read(dev, ETM_CFGMT_CFGMT_BLKSIZEr, 0, 0, &blk_size);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	switch (blk_size.cfgmt_blksize) {
+	case DPP_ETM_BLK_SIZE_256_B: {
+		*p_size = 256;
+		break;
+	}
+
+	case DPP_ETM_BLK_SIZE_512_B: {
+		*p_size = 512;
+		break;
+	}
+
+	case DPP_ETM_BLK_SIZE_1024_B: {
+		*p_size = 1024;
+		break;
+	}
+
+	default: {
+		*p_size = 256;
+	}
+	}
+
+	return DPP_OK;
+}
+#endif
+
+#if ZXIC_REAL("TM_CGAVD")
+/***********************************************************/
+/**  配置配置cgavd模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   mode   0:block mode 1:byte mode
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/07/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_cfg_mode_set(DPP_DEV_T *dev, ZXIC_UINT32 mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CGAVD_CFGMT_BYTE_MODE_T cgavd_cfg_mode = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1);
+
+	rc = dpp_reg_read(dev, ETM_CGAVD_CFGMT_BYTE_MODEr, 0, 0, &cgavd_cfg_mode);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	cgavd_cfg_mode.cfgmt_byte_mode = mode;
+
+	rc = dpp_reg_write(dev, ETM_CGAVD_CFGMT_BYTE_MODEr, 0, 0, &cgavd_cfg_mode);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**  获取cgavd模式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_mode   0:block mode 1:byte mode
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/07/29
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_cfg_mode_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CGAVD_CFGMT_BYTE_MODE_T cgavd_cfg_mode = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mode);
+
+	rc = dpp_reg_read(dev, ETM_CGAVD_CFGMT_BYTE_MODEr, 0, 0, &cgavd_cfg_mode);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_mode = cgavd_cfg_mode.cfgmt_byte_mode;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**  配置各级拥塞避免功能使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级
+ * @param   en   使能标记，0-不使能，1-使能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_en_set(DPP_DEV_T *dev, DPP_TM_CGAVD_LEVEL_E level,
+							   ZXIC_UINT32 en)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_ETM_CGAVD_CGAVD_SUB_EN_T cgavd_sub_en = { 0 };
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL,
+										SA_LEVEL);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), en, 0, 1);
+
+	rc = dpp_reg_read(dev, ETM_CGAVD_CGAVD_SUB_ENr, 0, 0, &cgavd_sub_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	if (QUEUE_LEVEL == level) {
+		cgavd_sub_en.cgavd_flow_sub_en = en;
+	}
+
+	else if (PP_LEVEL == level) {
+		cgavd_sub_en.cgavd_pp_sub_en = en;
+	}
+
+	else if (SYS_LEVEL == level) {
+		cgavd_sub_en.cgavd_sys_sub_en = en;
+	}
+
+	rc = dpp_reg_write(dev, ETM_CGAVD_CGAVD_SUB_ENr, 0, 0, &cgavd_sub_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**  读取各级拥塞避免功能使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   要读取的拥塞避免层次号，0:队列级，1:端口级，2:系统级
+ * @param   p_en   读出的使能标记，0-不使能，1-使能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_en_get(DPP_DEV_T *dev, DPP_TM_CGAVD_LEVEL_E level,
+							   ZXIC_UINT32 *p_en)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CGAVD_CGAVD_SUB_EN_T cgavd_sub_en = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL,
+										SA_LEVEL);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_en);
+
+	*p_en = 0xffffffff;
+
+	rc = dpp_reg_read(dev, ETM_CGAVD_CGAVD_SUB_ENr, 0, 0, &cgavd_sub_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	if (level == QUEUE_LEVEL) {
+		*p_en = cgavd_sub_en.cgavd_flow_sub_en;
+	}
+
+	else if (level == PP_LEVEL) {
+		*p_en = cgavd_sub_en.cgavd_pp_sub_en;
+	}
+
+	else if (level == SYS_LEVEL) {
+		*p_en = cgavd_sub_en.cgavd_sys_sub_en;
+	}
+
+	else if (level == SA_LEVEL) {
+		*p_en = cgavd_sub_en.cgavd_sa_sub_en;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**  dp选取来源
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   要配置的拥塞避免层次号，0:队列级，1:端口级，2:系统级
+ * @param   dp_sel   dp选取来源，0-dp，1-tc，2-pkt_len[2:0]
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2017/03/14
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_dp_sel_set(DPP_DEV_T *dev, DPP_TM_CGAVD_LEVEL_E level,
+								   DPP_TM_CGAVD_DP_SEL_E dp_sel)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CGAVD_CGAVD_DP_SEL_T cgavd_dp_sel = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL,
+										SYS_LEVEL);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), dp_sel, DP_SEL_DP,
+										DP_SEL_PKT_LEN);
+
+	rc = dpp_reg_read(dev, ETM_CGAVD_CGAVD_DP_SELr, 0, 0, &cgavd_dp_sel);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	if (QUEUE_LEVEL == level) {
+		if (DP_SEL_DP == dp_sel) {
+			cgavd_dp_sel.flow_dp_sel_high = 0;
+			cgavd_dp_sel.flow_dp_sel_mid = 0;
+			cgavd_dp_sel.flow_dp_sel_low = 1;
+		} else if (DP_SEL_TC == dp_sel) {
+			cgavd_dp_sel.flow_dp_sel_high = 0;
+			cgavd_dp_sel.flow_dp_sel_mid = 1;
+			cgavd_dp_sel.flow_dp_sel_low = 0;
+		} else if (DP_SEL_PKT_LEN == dp_sel) {
+			cgavd_dp_sel.flow_dp_sel_high = 1;
+			cgavd_dp_sel.flow_dp_sel_mid = 0;
+			cgavd_dp_sel.flow_dp_sel_low = 0;
+		}
+	}
+
+	else if (PP_LEVEL == level) {
+		if (DP_SEL_DP == dp_sel) {
+			cgavd_dp_sel.pp_dp_sel_high = 0;
+			cgavd_dp_sel.pp_dp_sel_mid = 0;
+			cgavd_dp_sel.pp_dp_sel_low = 1;
+		} else if (DP_SEL_TC == dp_sel) {
+			cgavd_dp_sel.pp_dp_sel_high = 0;
+			cgavd_dp_sel.pp_dp_sel_mid = 1;
+			cgavd_dp_sel.pp_dp_sel_low = 0;
+		} else if (DP_SEL_PKT_LEN == dp_sel) {
+			cgavd_dp_sel.pp_dp_sel_high = 1;
+			cgavd_dp_sel.pp_dp_sel_mid = 0;
+			cgavd_dp_sel.pp_dp_sel_low = 0;
+		}
+	}
+
+	else if (SYS_LEVEL == level) {
+		if (DP_SEL_DP == dp_sel) {
+			cgavd_dp_sel.sys_dp_sel_high = 0;
+			cgavd_dp_sel.sys_dp_sel_mid = 0;
+			cgavd_dp_sel.sys_dp_sel_low = 1;
+		} else if (DP_SEL_TC == dp_sel) {
+			cgavd_dp_sel.sys_dp_sel_high = 0;
+			cgavd_dp_sel.sys_dp_sel_mid = 1;
+			cgavd_dp_sel.sys_dp_sel_low = 0;
+		} else if (DP_SEL_PKT_LEN == dp_sel) {
+			cgavd_dp_sel.sys_dp_sel_high = 1;
+			cgavd_dp_sel.sys_dp_sel_mid = 0;
+			cgavd_dp_sel.sys_dp_sel_low = 0;
+		}
+	}
+
+	rc = dpp_reg_write(dev, ETM_CGAVD_CGAVD_DP_SELr, 0, 0, &cgavd_dp_sel);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置拥塞避免算法
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   id   队列号或端口号，系统级时，id参数无效
+ * @param   method  配置的拥塞避免算法，0:TD，1:WRED/GRED
+ *          配置TD算法时，先配TD阈值，再配置TD算法
+ *          配置WRED算法时,先配置流级或端口级的平均队列深度，再配置WRED算法
+ *          配置GRED算法时，先配置系统级的平均队列深度，在配置成GRED算法
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark
+ * @see
+ * @author  taq      @date  2015/04/14
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_method_set(DPP_DEV_T *dev, DPP_TM_CGAVD_LEVEL_E level,
+								   ZXIC_UINT32 id, DPP_TM_CGAVD_METHOD_E method)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 q_avg_q_len_reg_index = 0;
+	ZXIC_UINT32 q_td_th_reg_index = 0;
+	ZXIC_UINT32 q_ca_mtd_reg_index = 0;
+	ZXIC_UINT32 pp_avg_q_len_reg_index = 0;
+	ZXIC_UINT32 pp_td_th_reg_index = 0;
+	ZXIC_UINT32 pp_ca_mtd_reg_index = 0;
+	ZXIC_UINT32 sys_avg_q_len_reg_index = 0;
+	ZXIC_UINT32 sys_td_th_reg_index = 0;
+	ZXIC_UINT32 sys_ca_mtd_reg_index = 0;
+
+	DPP_ETM_CGAVD_FLOW_CA_MTD_T q_cgavd_method = { 0 };
+	DPP_ETM_CGAVD_PP_CA_MTD_T pp_cgavd_method = { 0 };
+	DPP_ETM_CGAVD_SYS_CGAVD_METD_T sys_cgavd_method = { 0 };
+	DPP_ETM_CGAVD_FLOW_AVG_Q_LEN_T flow_avg_q_len = { 0 };
+	DPP_ETM_CGAVD_PP_AVG_Q_LEN_T pp_avg_q_len = { 0 };
+	DPP_ETM_CGAVD_SYS_AVG_Q_LEN_T sys_avg_q_len = { 0 };
+	DPP_ETM_CGAVD_FLOW_TD_TH_T q_td_th = { 0 };
+	DPP_ETM_CGAVD_PP_TD_TH_T pp_td_th = { 0 };
+	DPP_ETM_CGAVD_SYS_TD_TH_T sys_td_th = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL,
+										SYS_LEVEL);
+
+	q_avg_q_len_reg_index = ETM_CGAVD_FLOW_AVG_Q_LENr;
+	q_td_th_reg_index = ETM_CGAVD_FLOW_TD_THr;
+	q_ca_mtd_reg_index = ETM_CGAVD_FLOW_CA_MTDr;
+	pp_avg_q_len_reg_index = ETM_CGAVD_PP_AVG_Q_LENr;
+	pp_td_th_reg_index = ETM_CGAVD_PP_TD_THr;
+	pp_ca_mtd_reg_index = ETM_CGAVD_PP_CA_MTDr;
+	sys_avg_q_len_reg_index = ETM_CGAVD_SYS_AVG_Q_LENr;
+	sys_td_th_reg_index = ETM_CGAVD_SYS_TD_THr;
+	sys_ca_mtd_reg_index = ETM_CGAVD_SYS_CGAVD_METDr;
+
+	switch (level) {
+	case (QUEUE_LEVEL): {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+											DPP_ETM_Q_NUM - 1);
+
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), method, TD_METHOD,
+											WRED_GRED_METHOD);
+
+		if (1 == method) {/* WRED算法，需要先配置平均队列深度，在选择wred算法 */
+			rc = dpp_reg_read(dev, q_avg_q_len_reg_index, 0, id,
+							  &flow_avg_q_len);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+			rc = dpp_reg_write(dev, q_avg_q_len_reg_index, 0, id,
+							   &flow_avg_q_len);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+		}
+
+		if (0 == method) {/* TD算法，需要先配置尾部丢弃阈值，在选择TD算法 */
+			rc = dpp_reg_read(dev, q_td_th_reg_index, 0, id, &q_td_th);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+			rc = dpp_reg_write(dev, q_td_th_reg_index, 0, id, &q_td_th);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+		}
+
+		/* 寄存器写入值,0-TD,1-WRED */
+		q_cgavd_method.flow_ca_mtd = method;
+		rc = dpp_reg_write(dev, q_ca_mtd_reg_index, 0, id, &q_cgavd_method);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+		break;
+	}
+
+	case (PP_LEVEL): {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+											DPP_TM_PP_NUM - 1);
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), method, TD_METHOD,
+											WRED_GRED_METHOD);
+
+		if (1 == method) {/* WRED算法，需要先配置平均队列深度，在选择wred算法 */
+			rc = dpp_reg_read(dev, pp_avg_q_len_reg_index, 0, id,
+							  &pp_avg_q_len);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+			rc = dpp_reg_write(dev, pp_avg_q_len_reg_index, 0, id,
+							   &pp_avg_q_len);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+		}
+
+		if (0 == method) {/* TD算法，尾部丢弃阈值，在选择TD算法 */
+			rc = dpp_reg_read(dev, pp_td_th_reg_index, 0, id, &pp_td_th);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+			rc = dpp_reg_write(dev, pp_td_th_reg_index, 0, id, &pp_td_th);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+		}
+
+		/* 寄存器写入值,0-TD,1-WRED */
+		pp_cgavd_method.pp_ca_mtd = method;
+		rc = dpp_reg_write(dev, pp_ca_mtd_reg_index, 0, id, &pp_cgavd_method);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+		break;
+	}
+
+	case (SYS_LEVEL): {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), method, TD_METHOD,
+											WRED_GRED_METHOD);
+
+		if (1 == method) {/* GRED算法，需要先配置平均队列深度，在选择gred算法 */
+			rc = dpp_reg_read(dev, sys_avg_q_len_reg_index, 0, 0,
+							  &sys_avg_q_len);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+			rc = dpp_reg_write(dev, sys_avg_q_len_reg_index, 0, 0,
+							   &sys_avg_q_len);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+		}
+
+		if (0 == method) {/* TD算法，尾部丢弃阈值，在选择TD算法 */
+			rc = dpp_reg_read(dev, sys_td_th_reg_index, 0, 0, &sys_td_th);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+			rc = dpp_reg_write(dev, sys_td_th_reg_index, 0, 0, &sys_td_th);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+		}
+
+		/* 寄存器写入值,0-TD,1-GRED */
+		sys_cgavd_method.sys_cgavd_metd = method;
+		rc = dpp_reg_write(dev, sys_ca_mtd_reg_index, 0, 0, &sys_cgavd_method);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+		break;
+	}
+
+	default: {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "method=%u error!\n", (method));
+		return DPP_ERR;
+	}
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取拥塞避免算法
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   id   队列号或端口号,系统级时,id参数无效
+ * @param   p_method   配置的拥塞避免算法,0:TD,1:WRED/GRED
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_method_get(DPP_DEV_T *dev, DPP_TM_CGAVD_LEVEL_E level,
+								   ZXIC_UINT32 id,
+								   DPP_TM_CGAVD_METHOD_E *p_method)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 q_ca_mtd_reg_index = 0;
+	ZXIC_UINT32 pp_ca_mtd_reg_index = 0;
+	ZXIC_UINT32 sys_ca_mtd_reg_index = 0;
+
+	DPP_ETM_CGAVD_FLOW_CA_MTD_T q_cgavd_method = { 0 };
+	DPP_ETM_CGAVD_PP_CA_MTD_T pp_cgavd_method = { 0 };
+	DPP_ETM_CGAVD_SYS_CGAVD_METD_T sys_cgavd_method = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL,
+										SYS_LEVEL);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_method);
+
+	*p_method = INVALID_METHOD;
+
+	q_ca_mtd_reg_index = ETM_CGAVD_FLOW_CA_MTDr;
+	pp_ca_mtd_reg_index = ETM_CGAVD_PP_CA_MTDr;
+	sys_ca_mtd_reg_index = ETM_CGAVD_SYS_CGAVD_METDr;
+
+	if (QUEUE_LEVEL == level) {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+											DPP_ETM_Q_NUM - 1);
+
+		rc = dpp_reg_read(dev, q_ca_mtd_reg_index, 0, id, &q_cgavd_method);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+		*p_method = q_cgavd_method.flow_ca_mtd;
+	}
+
+	else if (PP_LEVEL == level) {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+											DPP_TM_PP_NUM - 1);
+
+		rc = dpp_reg_read(dev, pp_ca_mtd_reg_index, 0, id, &pp_cgavd_method);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+		*p_method = pp_cgavd_method.pp_ca_mtd;
+	}
+
+	else {
+		rc = dpp_reg_read(dev, sys_ca_mtd_reg_index, 0, 0, &sys_cgavd_method);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+		*p_method = sys_cgavd_method.sys_cgavd_metd;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** CPU设置的各级队列深度配置
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level      拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   q_len_use_cpu_set_en   0：选取RAM中读出的队列深度；
+ * @param                          1：选取q_len_cpu_set值
+ * @param   q_len_cpu_set    CPU设置的各级队列深度,单位为block。
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/06/19
+ ************************************************************/
+DPP_STATUS dpp_tm_q_len_use_cpu_set(DPP_DEV_T *dev, DPP_TM_CGAVD_LEVEL_E level,
+									ZXIC_UINT32 q_len_use_cpu_set_en,
+									ZXIC_UINT32 q_len_cpu_set)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 rd_cpu_or_ram_reg_index = 0;
+	ZXIC_UINT32 q_cpu_set_q_len_reg_index = 0;
+	ZXIC_UINT32 pp_cpu_set_q_len_reg_index = 0;
+	ZXIC_UINT32 sys_cpu_set_q_len_reg_index = 0;
+
+	DPP_ETM_CGAVD_RD_CPU_OR_RAM_T len_use_cpu_set_en = { 0 };
+	DPP_ETM_CGAVD_FLOW_CPU_SET_Q_LEN_T flow_q_len_cpu_set = { 0 };
+	DPP_ETM_CGAVD_PP_CPU_SET_Q_LEN_T pp_q_len_cpu_set = { 0 };
+	DPP_ETM_CGAVD_SYS_CPU_SET_Q_LEN_T sys_q_len_cpu_set = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL,
+										SYS_LEVEL);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_len_use_cpu_set_en, 0,
+										1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_len_cpu_set, 0,
+										0x1ffffff);
+
+	rd_cpu_or_ram_reg_index = ETM_CGAVD_RD_CPU_OR_RAMr;
+	q_cpu_set_q_len_reg_index = ETM_CGAVD_FLOW_CPU_SET_Q_LENr;
+	pp_cpu_set_q_len_reg_index = ETM_CGAVD_PP_CPU_SET_Q_LENr;
+	sys_cpu_set_q_len_reg_index = ETM_CGAVD_SYS_CPU_SET_Q_LENr;
+
+	rc = dpp_reg_read(dev, rd_cpu_or_ram_reg_index, 0, 0, &len_use_cpu_set_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	switch (level) {
+	case (QUEUE_LEVEL): {
+		len_use_cpu_set_en.cpu_sel_flow_q_len_en = q_len_use_cpu_set_en;
+		rc = dpp_reg_write(dev, rd_cpu_or_ram_reg_index, 0, 0,
+						   &len_use_cpu_set_en);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+		if (q_len_use_cpu_set_en == 1) {
+			flow_q_len_cpu_set.flow_cpu_set_q_len = q_len_cpu_set;
+			rc = dpp_reg_write(dev, q_cpu_set_q_len_reg_index, 0, 0,
+							   &flow_q_len_cpu_set);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+		}
+
+		break;
+	}
+
+	case (PP_LEVEL): {
+		len_use_cpu_set_en.cpu_sel_pp_q_len_en = q_len_use_cpu_set_en;
+		rc = dpp_reg_write(dev, rd_cpu_or_ram_reg_index, 0, 0,
+						   &len_use_cpu_set_en);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+		if (q_len_use_cpu_set_en == 1) {
+			pp_q_len_cpu_set.pp_cpu_set_q_len = q_len_cpu_set;
+			rc = dpp_reg_write(dev, pp_cpu_set_q_len_reg_index, 0, 0,
+							   &pp_q_len_cpu_set);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+		}
+
+		break;
+	}
+
+	case (SYS_LEVEL): {
+		len_use_cpu_set_en.cpu_sel_sys_q_len_en = q_len_use_cpu_set_en;
+		rc = dpp_reg_write(dev, rd_cpu_or_ram_reg_index, 0, 0,
+						   &len_use_cpu_set_en);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+		if (q_len_use_cpu_set_en == 1) {
+			sys_q_len_cpu_set.sys_cpu_set_q_len = q_len_cpu_set;
+			rc = dpp_reg_write(dev, sys_cpu_set_q_len_reg_index, 0, 0,
+							   &sys_q_len_cpu_set);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+		}
+
+		break;
+	}
+
+	default: {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "level=%u error!\n", level);
+		return DPP_ERR;
+	}
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** CPU设置的各级平均队列深度配置
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level      拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   q_avg_len_use_cpu_set_en   0：选取RAM中读出的队列深度；
+ * @param                              1：选取q_avg_len_cpu_set值
+ * @param   q_avg_len_cpu_set    CPU设置的各级平均队列深度。
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/06/19
+ ************************************************************/
+DPP_STATUS dpp_tm_q_avg_len_use_cpu_set(DPP_DEV_T *dev,
+										DPP_TM_CGAVD_LEVEL_E level,
+										ZXIC_UINT32 q_avg_len_use_cpu_set_en,
+										ZXIC_UINT32 q_avg_len_cpu_set)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 rd_cpu_or_ram_reg_index = 0;
+	ZXIC_UINT32 q_cpu_set_avg_len_reg_index = 0;
+	ZXIC_UINT32 pp_cpu_set_avg_len_reg_index = 0;
+	ZXIC_UINT32 sys_cpu_set_avg_len_reg_index = 0;
+
+	DPP_ETM_CGAVD_RD_CPU_OR_RAM_T avg_len_use_cpu_set_en = { 0 };
+	DPP_ETM_CGAVD_FLOW_CPU_SET_AVG_LEN_T flow_q_avg_len_cpu_set = { 0 };
+	DPP_ETM_CGAVD_PP_CPU_SET_AVG_Q_LEN_T pp_q_avg_len_cpu_set = { 0 };
+	DPP_ETM_CGAVD_SYS_CPU_SET_AVG_LEN_T sys_q_avg_len_cpu_set = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL,
+										SYS_LEVEL);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_avg_len_use_cpu_set_en,
+										0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_avg_len_cpu_set, 0,
+										0x1ffffff);
+
+	rd_cpu_or_ram_reg_index = ETM_CGAVD_RD_CPU_OR_RAMr;
+	q_cpu_set_avg_len_reg_index = ETM_CGAVD_FLOW_CPU_SET_AVG_LENr;
+	pp_cpu_set_avg_len_reg_index = ETM_CGAVD_PP_CPU_SET_AVG_Q_LENr;
+	sys_cpu_set_avg_len_reg_index = ETM_CGAVD_SYS_CPU_SET_AVG_LENr;
+
+	rc = dpp_reg_read(dev, rd_cpu_or_ram_reg_index, 0, 0,
+					  &avg_len_use_cpu_set_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	switch (level) {
+	case (QUEUE_LEVEL): {
+		avg_len_use_cpu_set_en.cpu_sel_flow_avg_q_len_en =
+				q_avg_len_use_cpu_set_en;
+		rc = dpp_reg_write(dev, rd_cpu_or_ram_reg_index, 0, 0,
+						   &avg_len_use_cpu_set_en);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+		if (q_avg_len_use_cpu_set_en == 1) {
+			flow_q_avg_len_cpu_set.flow_cpu_set_avg_len = q_avg_len_cpu_set;
+			rc = dpp_reg_write(dev, q_cpu_set_avg_len_reg_index, 0, 0,
+							   &flow_q_avg_len_cpu_set);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+		}
+
+		break;
+	}
+
+	case (PP_LEVEL): {
+		avg_len_use_cpu_set_en.cpu_sel_pp_avg_q_len_en =
+				q_avg_len_use_cpu_set_en;
+		rc = dpp_reg_write(dev, rd_cpu_or_ram_reg_index, 0, 0,
+						   &avg_len_use_cpu_set_en);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+		if (q_avg_len_use_cpu_set_en == 1) {
+			pp_q_avg_len_cpu_set.pp_cpu_set_avg_q_len = q_avg_len_cpu_set;
+			rc = dpp_reg_write(dev, pp_cpu_set_avg_len_reg_index, 0, 0,
+							   &pp_q_avg_len_cpu_set);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+		}
+
+		break;
+	}
+
+	case (SYS_LEVEL): {
+		avg_len_use_cpu_set_en.cpu_sel_sys_avg_q_len_en =
+				q_avg_len_use_cpu_set_en;
+		rc = dpp_reg_write(dev, rd_cpu_or_ram_reg_index, 0, 0,
+						   &avg_len_use_cpu_set_en);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+		if (q_avg_len_use_cpu_set_en == 1) {
+			sys_q_avg_len_cpu_set.sys_cpu_set_avg_len = q_avg_len_cpu_set;
+			rc = dpp_reg_write(dev, sys_cpu_set_avg_len_reg_index, 0, 0,
+							   &sys_q_avg_len_cpu_set);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+		}
+
+		break;
+	}
+
+	default: {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "level=%u error!\n", level);
+		return DPP_ERR;
+	}
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 流队列级队列深度的获取
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   que_id      队列号
+ *          p_len       队列深度以KB为单位
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/06/19
+ ************************************************************/
+DPP_STATUS dpp_tm_flow_que_len_get(DPP_DEV_T *dev, ZXIC_UINT32 que_id,
+								   ZXIC_UINT32 *p_len)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 blk_size = 0;
+	ZXIC_UINT32 cgavd_cfg_mode = 0;
+
+	DPP_ETM_CGAVD_FLOW_Q_LEN_T dpp_tm_flow_len = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_len);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), que_id, 0,
+										DPP_ETM_Q_NUM - 1);
+
+	rc = dpp_reg_read(dev, ETM_CGAVD_FLOW_Q_LENr, 0, que_id, &dpp_tm_flow_len);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	rc = dpp_tm_cgavd_cfg_mode_get(dev, &cgavd_cfg_mode);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_cgavd_cfg_mode_get");
+
+	if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) {
+		rc = dpp_tm_cfgmt_blk_size_get(dev, &blk_size);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_cfgmt_blk_size_get");
+
+		*p_len = ((dpp_tm_flow_len.flow_q_len * blk_size) /
+				  DPP_TM_CGAVD_KILO_UL);
+	} else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) {
+		*p_len = ((dpp_tm_flow_len.flow_q_len) / DPP_TM_CGAVD_KILO_UL);
+	} else {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev),
+				"dpp_tm_flow_que_len_get:cgavd_cfg_mode is err!!\n");
+		return DPP_ERR;
+	}
+
+	return DPP_OK;
+}
+/***********************************************************/
+/** 配置TD拥塞避免模式下的丢弃门限值
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   id   队列号或端口号，系统级时，id参数无效
+ * @param   byte_block_th   配置的丢弃门限值，ZXIC_UINT8/BLOCK单位写入寄存器
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/07/29
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_td_byte_block_th_set(DPP_DEV_T *dev,
+											 DPP_TM_CGAVD_LEVEL_E level,
+											 ZXIC_UINT32 id,
+											 ZXIC_UINT32 byte_block_th)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 q_td_th_reg_index = 0;
+	ZXIC_UINT32 q_ca_mtd_reg_index = 0;
+	ZXIC_UINT32 pp_td_th_reg_index = 0;
+	ZXIC_UINT32 pp_ca_mtd_reg_index = 0;
+	ZXIC_UINT32 sys_td_th_reg_index = 0;
+	ZXIC_UINT32 sys_ca_mtd_reg_index = 0;
+	ZXIC_UINT32 read_times = 50;
+	DPP_ETM_CGAVD_FLOW_CA_MTD_T q_cgavd_method = { 0 };
+	DPP_ETM_CGAVD_FLOW_TD_TH_T q_td_th = { 0 };
+	DPP_ETM_CGAVD_PP_CA_MTD_T pp_cgavd_method = { 0 };
+	DPP_ETM_CGAVD_PP_TD_TH_T pp_td_th = { 0 };
+	DPP_ETM_CGAVD_SYS_CGAVD_METD_T sys_cgavd_method = { 0 };
+	DPP_ETM_CGAVD_SYS_TD_TH_T sys_td_th = { 0 };
+	ZXIC_UINT32 qlist_clr_done_flag = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL,
+										SYS_LEVEL);
+
+	q_td_th_reg_index = ETM_CGAVD_FLOW_TD_THr;
+	q_ca_mtd_reg_index = ETM_CGAVD_FLOW_CA_MTDr;
+	pp_td_th_reg_index = ETM_CGAVD_PP_TD_THr;
+	pp_ca_mtd_reg_index = ETM_CGAVD_PP_CA_MTDr;
+	sys_td_th_reg_index = ETM_CGAVD_SYS_TD_THr;
+	sys_ca_mtd_reg_index = ETM_CGAVD_SYS_CGAVD_METDr;
+
+	if (QUEUE_LEVEL == level) {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+											DPP_ETM_Q_NUM - 1);
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), byte_block_th, 0,
+											0x1fffffff);
+
+		q_td_th.flow_td_th = byte_block_th;
+		rc = dpp_reg_write(dev, q_td_th_reg_index, 0, id, &q_td_th);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+		q_cgavd_method.flow_ca_mtd = TD_METHOD;
+
+		rc = dpp_reg_write(dev, q_ca_mtd_reg_index, 0, id, &q_cgavd_method);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+		/* add by zhmy begin@20151103 */
+		if (byte_block_th == 0) {
+			do {
+				rc = dpp_tm_qmu_qlist_qcfg_clr_done_get(dev,
+														&qlist_clr_done_flag);
+				ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(
+						DEV_ID(dev), rc, "dpp_tm_qmu_qlist_qcfg_clr_done_get");
+
+				read_times--;
+
+				if (1 == qlist_clr_done_flag) {
+					break;
+				}
+
+				zxic_comm_delay(10);
+			} while (read_times > 0);
+
+			if (read_times == 0) {
+				ZXIC_COMM_TRACE_DEV_ERROR(
+						DEV_ID(dev),
+						"dpp_tm_qmu_qlist_qcfg_clr_done_get time out\n");
+				return DPP_ERR;
+			}
+		}
+
+		/* add by zhmy end@20151103 */
+	}
+
+	else if (PP_LEVEL == level) {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+											DPP_TM_PP_NUM - 1);
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), byte_block_th, 0,
+											0x1fffffff);
+
+		pp_td_th.pp_td_th = byte_block_th;
+		rc = dpp_reg_write(dev, pp_td_th_reg_index, 0, id, &pp_td_th);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+		pp_cgavd_method.pp_ca_mtd = TD_METHOD;
+		rc = dpp_reg_write(dev, pp_ca_mtd_reg_index, 0, id, &pp_cgavd_method);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+	}
+
+	else {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), byte_block_th, 0,
+											0x1fffffff);
+
+		sys_td_th.sys_td_th = byte_block_th;
+		rc = dpp_reg_write(dev, sys_td_th_reg_index, 0, 0, &sys_td_th);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+		sys_cgavd_method.sys_cgavd_metd = TD_METHOD;
+
+		rc = dpp_reg_write(dev, sys_ca_mtd_reg_index, 0, 0, &sys_cgavd_method);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置TD拥塞避免模式下的丢弃门限值
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   id   队列号或端口号，系统级时，id参数无效
+ * @param   td_th   配置的丢弃门限值，用户配置门限值单位为Kbyte，需要转化为Block或者ZXIC_UINT8单位写入寄存器
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/07/29
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_td_th_set(DPP_DEV_T *dev, DPP_TM_CGAVD_LEVEL_E level,
+								  ZXIC_UINT32 id, ZXIC_UINT32 td_th)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 blk_size = 0;
+	ZXIC_UINT32 blk_th = 0;
+	ZXIC_UINT32 cgavd_cfg_mode = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL,
+										SYS_LEVEL);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), td_th, 0, 512 * 1024);
+
+	td_th = (ZXIC_UINT32)(td_th * DPP_TM_CGAVD_KILO_UL);
+
+	rc = dpp_tm_cgavd_cfg_mode_get(dev, &cgavd_cfg_mode);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_cgavd_cfg_mode_get");
+
+	if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) {
+		rc = dpp_tm_cfgmt_blk_size_get(dev, &blk_size);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_cfgmt_blk_size_get");
+
+		if (blk_size != 0) {
+			blk_th = (td_th / blk_size);
+			blk_th = (td_th % blk_size == 0) ? (blk_th) : ((blk_th) + 1);
+		}
+
+		rc = dpp_tm_cgavd_td_byte_block_th_set(dev, level, id, blk_th);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_cgavd_td_byte_block_th_set");
+	} else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) {
+		rc = dpp_tm_cgavd_td_byte_block_th_set(dev, level, id, td_th);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_cgavd_td_byte_block_th_set");
+	} else {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+								  "dpp_tm_cgavd_td_th_set err!!\n");
+		return DPP_ERR;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取TD拥塞避免模式下的丢弃门限值
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   id   队列号或端口号，系统级时，id参数无效
+ * @param   p_byte_block_th   配置的丢弃门限值ZXIC_UINT8/BLOCK单位
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/07/29
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_td_byte_block_th_get(DPP_DEV_T *dev,
+											 DPP_TM_CGAVD_LEVEL_E level,
+											 ZXIC_UINT32 id,
+											 ZXIC_UINT32 *p_byte_block_th)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 q_td_th_reg_index = 0;
+	ZXIC_UINT32 pp_td_th_reg_index = 0;
+	ZXIC_UINT32 sys_td_th_reg_index = 0;
+	DPP_ETM_CGAVD_FLOW_TD_TH_T q_td_th = { 0 };
+	DPP_ETM_CGAVD_PP_TD_TH_T pp_td_th = { 0 };
+	DPP_ETM_CGAVD_SYS_TD_TH_T sys_td_th = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL,
+										SYS_LEVEL);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_byte_block_th);
+
+	if (QUEUE_LEVEL == level) {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+											DPP_ETM_Q_NUM - 1);
+	}
+
+	else if (PP_LEVEL == level) {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+											DPP_TM_PP_NUM - 1);
+	}
+
+	else {
+		ZXIC_COMM_PRINT("sys:id is not to be checked!!\n");
+	}
+
+	q_td_th_reg_index = ETM_CGAVD_FLOW_TD_THr;
+	pp_td_th_reg_index = ETM_CGAVD_PP_TD_THr;
+	sys_td_th_reg_index = ETM_CGAVD_SYS_TD_THr;
+
+	if (QUEUE_LEVEL == level) {
+		rc = dpp_reg_read(dev, q_td_th_reg_index, 0, id, &q_td_th);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+		*p_byte_block_th = q_td_th.flow_td_th;
+	}
+
+	else if (PP_LEVEL == level) {
+		rc = dpp_reg_read(dev, pp_td_th_reg_index, 0, id, &pp_td_th);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+		*p_byte_block_th = pp_td_th.pp_td_th;
+	}
+
+	else {
+		rc = dpp_reg_read(dev, sys_td_th_reg_index, 0, 0, &sys_td_th);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+		*p_byte_block_th = sys_td_th.sys_td_th;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取TD拥塞避免模式下的丢弃门限值
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   id   队列号或端口号，系统级时，id参数无效
+ * @param   p_td_th   配置的丢弃门限值KZXIC_UINT8单位
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/07/29
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_td_th_get(DPP_DEV_T *dev, DPP_TM_CGAVD_LEVEL_E level,
+								  ZXIC_UINT32 id, ZXIC_UINT32 *p_td_th)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 cgavd_cfg_mode = 0;
+	ZXIC_UINT32 block_byte_th = 0;
+	ZXIC_UINT32 blk_size = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL,
+										SYS_LEVEL);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_td_th);
+
+	*p_td_th = 0;
+
+	if (QUEUE_LEVEL == level) {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+											DPP_ETM_Q_NUM - 1);
+	}
+
+	else if (PP_LEVEL == level) {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+											DPP_TM_PP_NUM - 1);
+	}
+
+	else {
+		ZXIC_COMM_PRINT("sys:id is not to be checked!!\n");
+	}
+
+	rc = dpp_tm_cgavd_td_byte_block_th_get(dev, level, id, &block_byte_th);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_cgavd_td_byte_block_th_get");
+
+	rc = dpp_tm_cgavd_cfg_mode_get(dev, &cgavd_cfg_mode);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_cgavd_cfg_mode_get");
+
+	if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) {
+		rc = dpp_tm_cfgmt_blk_size_get(dev, &blk_size);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_cfgmt_blk_size_get");
+
+		*p_td_th = (block_byte_th * blk_size) / DPP_TM_CGAVD_KILO_UL;
+	} else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) {
+		*p_td_th = (block_byte_th / DPP_TM_CGAVD_KILO_UL);
+	} else {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+								  "dpp_tm_cgavd_td_th_get err!!\n");
+		return DPP_ERR;
+	}
+
+	return DPP_OK;
+}
+/***********************************************************/
+/** 配置指定端口或队列是否支持动态门限机制
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   WRED支持层次号，0:队列级，1:端口级
+ * @param   id   队列号或端口号
+ * @param   en   配置的值，0-不支持动态门限机制，1-支持动态门限机制
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_dyn_th_en_set(DPP_DEV_T *dev,
+									  DPP_TM_CGAVD_LEVEL_E level,
+									  ZXIC_UINT32 id, ZXIC_UINT32 en)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 q_dyn_th_en_reg_index = 0;
+	ZXIC_UINT32 pp_wrd_grp_th_en_reg_index = 0;
+
+	DPP_ETM_CGAVD_FLOW_DYNAMIC_TH_EN_T q_dyn_th_en = { 0 };
+	DPP_ETM_CGAVD_PP_WRED_GRP_TH_EN_T pp_dyn_th_en = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL,
+										PP_LEVEL);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), en, 0, 1);
+
+	q_dyn_th_en_reg_index = ETM_CGAVD_FLOW_DYNAMIC_TH_ENr;
+	pp_wrd_grp_th_en_reg_index = ETM_CGAVD_PP_WRED_GRP_TH_ENr;
+
+	if (QUEUE_LEVEL == level) {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+											DPP_ETM_Q_NUM - 1);
+
+		q_dyn_th_en.flow_dynamic_th_en = en;
+		rc = dpp_reg_write(dev, q_dyn_th_en_reg_index, 0, id, &q_dyn_th_en);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+	}
+
+	else {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+											DPP_TM_PP_NUM - 1);
+
+		rc = dpp_reg_read(dev, pp_wrd_grp_th_en_reg_index, 0, id,
+						  &pp_dyn_th_en);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+		pp_dyn_th_en.pp_wred_grp_th_en = en;
+		rc = dpp_reg_write(dev, pp_wrd_grp_th_en_reg_index, 0, id,
+						   &pp_dyn_th_en);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取指定端口或队列是否支持动态门限机制
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   WRED支持层次号，0:队列级，1:端口级
+ * @param   id   队列号或端口号
+ * @param   p_en   读取的值，0-不支持动态门限机制，1-支持动态门限机制
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_dyn_th_en_get(DPP_DEV_T *dev,
+									  DPP_TM_CGAVD_LEVEL_E level,
+									  ZXIC_UINT32 id, ZXIC_UINT32 *p_en)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 q_dyn_th_en_reg_index = 0;
+	ZXIC_UINT32 pp_wrd_grp_th_en_reg_index = 0;
+
+	DPP_ETM_CGAVD_FLOW_DYNAMIC_TH_EN_T q_dyn_th_en = { 0 };
+	DPP_ETM_CGAVD_PP_WRED_GRP_TH_EN_T pp_dyn_th_en = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL,
+										PP_LEVEL);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_en);
+
+	q_dyn_th_en_reg_index = ETM_CGAVD_FLOW_DYNAMIC_TH_ENr;
+	pp_wrd_grp_th_en_reg_index = ETM_CGAVD_PP_WRED_GRP_TH_ENr;
+
+	if (QUEUE_LEVEL == level) {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+											DPP_ETM_Q_NUM - 1);
+
+		rc = dpp_reg_read(dev, q_dyn_th_en_reg_index, 0, id, &q_dyn_th_en);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+		*p_en = q_dyn_th_en.flow_dynamic_th_en;
+	}
+
+	else {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+											DPP_TM_PP_NUM - 1);
+
+		rc = dpp_reg_read(dev, pp_wrd_grp_th_en_reg_index, 0, id,
+						  &pp_dyn_th_en);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+		*p_en = pp_dyn_th_en.pp_wred_grp_th_en;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**  配置等价包长使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   en   使能标记，0-不使能，1-使能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_equal_pkt_len_en_set(DPP_DEV_T *dev, ZXIC_UINT32 en)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CGAVD_EQUAL_PKT_LEN_EN_T equal_pkt_len_en = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), en, 0, 1);
+
+	equal_pkt_len_en.equal_pkt_len_en = en;
+	rc = dpp_reg_write(dev, ETM_CGAVD_EQUAL_PKT_LEN_ENr, 0, 0,
+					   &equal_pkt_len_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**  读取等价包长使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_en   使能标记，0-不使能，1-使能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_equal_pkt_len_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_en)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CGAVD_EQUAL_PKT_LEN_EN_T equal_pkt_len_en = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_en);
+
+	*p_en = 0xffffffff;
+	rc = dpp_reg_read(dev, ETM_CGAVD_EQUAL_PKT_LEN_ENr, 0, 0,
+					  &equal_pkt_len_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+	*p_en = equal_pkt_len_en.equal_pkt_len_en;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置等价包长
+ * @param   dev_id
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_equal_pkt_len 等价包长
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_equal_pkt_len_para_set(
+		DPP_DEV_T *dev, DPP_ETM_EQUAL_PKT_LEN_PARA_T *p_equal_pkt_len)
+{
+	/* 返回值变量定义 */
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+
+	/* 结构体变量定义 */
+	DPP_ETM_CGAVD_EQUAL_PKT_LEN0_T equal_pkt_len0 = { 0 };
+
+	/* 入参检查 */
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_equal_pkt_len);
+
+	for (i = 0; i < 8; i++) {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(
+				DEV_ID(dev), p_equal_pkt_len->equal_pkt_len[i], 0x0, 0x7fff);
+		equal_pkt_len0.equal_pkt_len0 = p_equal_pkt_len->equal_pkt_len[i];
+		rc = dpp_reg_write(dev, ETM_CGAVD_EQUAL_PKT_LEN0r + i, 0, 0,
+						   &equal_pkt_len0);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取等价包长
+ * @param   dev_id
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_equal_pkt_len 等价包长
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_equal_pkt_len_para_get(
+		DPP_DEV_T *dev, DPP_ETM_EQUAL_PKT_LEN_PARA_T *p_equal_pkt_len)
+{
+	/* 返回值变量定义 */
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+
+	/* 结构体变量定义 */
+	DPP_ETM_CGAVD_EQUAL_PKT_LEN0_T equal_pkt_len0 = { 0 };
+
+	/* 入参检查 */
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_equal_pkt_len);
+
+	for (i = 0; i < 8; i++) {
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_CGAVD_EQUAL_PKT_LEN0r,
+													 i);
+		rc = dpp_reg_read(dev, ETM_CGAVD_EQUAL_PKT_LEN0r + i, 0, 0,
+						  &equal_pkt_len0);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+		p_equal_pkt_len->equal_pkt_len[i] = equal_pkt_len0.equal_pkt_len0;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置等价包长阈值
+ * @param   dev_id
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_equal_pkt_len_th 等价包长阈值
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_equal_pkt_len_th_para_set(
+		DPP_DEV_T *dev, DPP_ETM_EQUAL_PKT_LEN_TH_PARA_T *p_equal_pkt_len_th)
+{
+	/* 返回值变量定义 */
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 i = 0;
+
+	/* 结构体变量定义 */
+	DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH0_T equal_pkt_len_th0 = { 0 };
+
+	/* 入参检查 */
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_equal_pkt_len_th);
+
+	for (i = 0; i < 7; i++) {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(
+				DEV_ID(dev), p_equal_pkt_len_th->equal_pkt_len_th[i], 0x0,
+				0x7fff);
+
+		if (i <= 5) {
+			ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(
+					DEV_ID(dev), p_equal_pkt_len_th->equal_pkt_len_th[i + 1],
+					p_equal_pkt_len_th->equal_pkt_len_th[i], 0x7fff);
+		}
+
+		equal_pkt_len_th0.equal_pkt_len_th0 =
+				p_equal_pkt_len_th->equal_pkt_len_th[i];
+		rc = dpp_reg_write(dev, ETM_CGAVD_EQUAL_PKT_LEN_TH0r + i, 0, 0,
+						   &equal_pkt_len_th0);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取等价包长阈值
+ * @param   dev_id
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_equal_pkt_len_th 等价包长阈值
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_equal_pkt_len_th_para_get(
+		DPP_DEV_T *dev, DPP_ETM_EQUAL_PKT_LEN_TH_PARA_T *p_equal_pkt_len_th)
+{
+	/* 返回值变量定义 */
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 i = 0;
+
+	/* 结构体变量定义 */
+	DPP_ETM_CGAVD_EQUAL_PKT_LEN_TH0_T equal_pkt_len_th0 = { 0 };
+
+	/* 入参检查 */
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_equal_pkt_len_th);
+
+	for (i = 0; i < 7; i++) {
+		ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(
+				DEV_ID(dev), i, ETM_CGAVD_EQUAL_PKT_LEN_TH0r);
+		rc = dpp_reg_read(dev, ETM_CGAVD_EQUAL_PKT_LEN_TH0r + i, 0, 0,
+						  &equal_pkt_len_th0);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+		p_equal_pkt_len_th->equal_pkt_len_th[i] =
+				equal_pkt_len_th0.equal_pkt_len_th0;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 动态门限放大因子参数配置
+ * @param   dev_id
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_amplify_gene_para 动态门限放大因子参数
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_amplify_gene_para_set(
+		DPP_DEV_T *dev, DPP_ETM_AMPLIFY_GENE_PARA_T *p_amplify_gene_para)
+{
+	/* 返回值变量定义 */
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 i = 0;
+
+	/* 结构体变量定义 */
+	DPP_ETM_CGAVD_AMPLIFY_GENE0_T amplify_gene0 = { 0 };
+
+	/* 入参检查 */
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_amplify_gene_para);
+
+	for (i = 0; i < 16; i++) {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(
+				DEV_ID(dev), p_amplify_gene_para->amplify_gene[i], 0x0, 0xfff);
+		amplify_gene0.amplify_gene0 = p_amplify_gene_para->amplify_gene[i];
+		rc = dpp_reg_write(dev, ETM_CGAVD_AMPLIFY_GENE0r + i, 0, 0,
+						   &amplify_gene0);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 动态门限放大因子参数获取
+ * @param   dev_id
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_amplify_gene_para 动态门限放大因子参数
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/28
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_amplify_gene_para_get(
+		DPP_DEV_T *dev, DPP_ETM_AMPLIFY_GENE_PARA_T *p_amplify_gene_para)
+{
+	/* 返回值变量定义 */
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 i = 0;
+
+	/* 结构体变量定义 */
+	DPP_ETM_CGAVD_AMPLIFY_GENE0_T amplify_gene0 = { 0 };
+
+	/* 入参检查 */
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_amplify_gene_para);
+
+	for (i = 0; i < 16; i++) {
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(ETM_CGAVD_AMPLIFY_GENE0r,
+													 i);
+		rc = dpp_reg_read(dev, ETM_CGAVD_AMPLIFY_GENE0r + i, 0, 0,
+						  &amplify_gene0);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+		p_amplify_gene_para->amplify_gene[i] = amplify_gene0.amplify_gene0;
+	}
+
+	return DPP_OK;
+}
+/***********************************************************/
+/**  配置通用门限使能
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   en   配置的值，0-不使能通用门限，1-使能通用门限，
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_uniform_th_en_set(DPP_DEV_T *dev, ZXIC_UINT32 en)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CGAVD_UNIFORM_TD_TH_EN_T uniform_en = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), en, 0, 1);
+
+	uniform_en.uniform_td_th_en = en;
+	rc = dpp_reg_write(dev, ETM_CGAVD_UNIFORM_TD_TH_ENr, 0, 0, &uniform_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**  读取通用门限使能
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_en   读取的值，0-不使能通用门限，1-使能通用门限，
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_uniform_th_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_en)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CGAVD_UNIFORM_TD_TH_EN_T uniform_en = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_en);
+
+	rc = dpp_reg_read(dev, ETM_CGAVD_UNIFORM_TD_TH_ENr, 0, 0, &uniform_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_en = uniform_en.uniform_td_th_en;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**  配置通用门限
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   byte_block_uni_th   通用门限值block/byte单位
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/08/01
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_uniform_byte_block_th_set(DPP_DEV_T *dev,
+												  ZXIC_UINT32 byte_block_uni_th)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CGAVD_UNIFORM_TD_TH_T uniform_block_th = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), byte_block_uni_th, 0,
+										0x1fffffff);
+
+	uniform_block_th.uniform_td_th = byte_block_uni_th;
+	rc = dpp_reg_write(dev, ETM_CGAVD_UNIFORM_TD_THr, 0, 0, &uniform_block_th);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**  配置通用门限
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   th   通用门限值
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_uniform_th_set(DPP_DEV_T *dev, ZXIC_UINT32 uni_th)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 blk_size = 0;
+	ZXIC_UINT32 blk_th = 0;
+	ZXIC_UINT32 cgavd_cfg_mode = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW(DEV_ID(dev), uni_th,
+										   DPP_TM_CGAVD_KILO_UL);
+	if ((uni_th * DPP_TM_CGAVD_KILO_UL) > 0x1fffffff) {
+		uni_th = 0x1fffffff;
+	} else {
+		uni_th = (uni_th * DPP_TM_CGAVD_KILO_UL);
+	}
+
+	rc = dpp_tm_cgavd_cfg_mode_get(dev, &cgavd_cfg_mode);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_cgavd_cfg_mode_get");
+
+	if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) {
+		rc = dpp_tm_cfgmt_blk_size_get(dev, &blk_size);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_cfgmt_blk_size_get");
+
+		if (blk_size != 0) {
+			blk_th = (uni_th / blk_size);
+			blk_th = (uni_th % blk_size == 0) ? (blk_th) : ((blk_th) + 1);
+		}
+
+		rc = dpp_tm_cgavd_uniform_byte_block_th_set(dev, blk_th);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(
+				DEV_ID(dev), rc, "dpp_tm_cgavd_uniform_byte_block_th_set");
+	} else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) {
+		rc = dpp_tm_cgavd_uniform_byte_block_th_set(dev, uni_th);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(
+				DEV_ID(dev), rc, "dpp_tm_cgavd_uniform_byte_block_th_set");
+	} else {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+								  "dpp_tm_cgavd_uniform_th_set err!!\n");
+		return DPP_ERR;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**  读取通用门限
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_byte_block_uni_th   通用门限值block/byte单位
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/08/01
+ ************************************************************/
+DPP_STATUS
+dpp_tm_cgavd_uniform_byte_block_th_get(DPP_DEV_T *dev,
+									   ZXIC_UINT32 *p_byte_block_uni_th)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CGAVD_UNIFORM_TD_TH_T uniform_block_th = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_byte_block_uni_th);
+
+	rc = dpp_reg_read(dev, ETM_CGAVD_UNIFORM_TD_THr, 0, 0, &uniform_block_th);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_byte_block_uni_th = uniform_block_th.uniform_td_th;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**  读取通用门限
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_uni_th   通用门限值kbyte单位
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/08/01
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_uniform_th_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_uni_th)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 blk_size = 0;
+	ZXIC_UINT32 cgavd_cfg_mode = 0;
+	ZXIC_UINT32 block_byte_th = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_uni_th);
+
+	rc = dpp_tm_cgavd_uniform_byte_block_th_get(dev, &block_byte_th);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_cgavd_uniform_byte_block_th_get");
+
+	rc = dpp_tm_cgavd_cfg_mode_get(dev, &cgavd_cfg_mode);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_cgavd_cfg_mode_get");
+
+	if (cgavd_cfg_mode == DPP_TM_CGAVD_BLOCK_MODE) {
+		rc = dpp_tm_cfgmt_blk_size_get(dev, &blk_size);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_cfgmt_blk_size_get");
+
+		*p_uni_th = (block_byte_th * blk_size) / DPP_TM_CGAVD_KILO_UL;
+	} else if (cgavd_cfg_mode == DPP_TM_CGAVD_ZXIC_UINT8_MODE) {
+		*p_uni_th = (block_byte_th / DPP_TM_CGAVD_KILO_UL);
+	} else {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+								  "dpp_tm_cgavd_uniform_th_get err!!\n");
+		return DPP_ERR;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**  配置流队列所属优先级
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   q_id   队列号
+ * @param   pri   配置的优先级，0~4
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_q_pri_set(DPP_DEV_T *dev, ZXIC_UINT32 q_id,
+								  ZXIC_UINT32 pri)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CGAVD_Q_PRI_T q_pri = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pri, 0, 4);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_id, 0,
+										DPP_ETM_Q_NUM - 1);
+
+	q_pri.qpri_flow_cfg_din = pri;
+	rc = dpp_reg_write(dev, ETM_CGAVD_Q_PRIr, 0, q_id, &q_pri);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置TM模式下流队列挂接的端口号；SA模式下流队列映射的目的芯片ID
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   q_id   队列号
+ * @param   pp_id   配置的端口号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/18
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_q_map_pp_set(DPP_DEV_T *dev, ZXIC_UINT32 q_id,
+									 ZXIC_UINT32 pp_id)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CGAVD_PP_NUM_T pp_num = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_id, 0,
+										DPP_ETM_Q_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pp_id, 0,
+										DPP_TM_PP_NUM - 1);
+
+	pp_num.pp_num = pp_id;
+	rc = dpp_reg_write(dev, ETM_CGAVD_PP_NUMr, 0, q_id, &pp_num);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取TM模式下流队列挂接的端口号；SA模式下流队列映射的目的芯片ID
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   q_id   队列号
+ * @param   p_pp_id   读取的端口号
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/18
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_q_map_pp_get(DPP_DEV_T *dev, ZXIC_UINT32 q_id,
+									 ZXIC_UINT32 *p_pp_id)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CGAVD_PP_NUM_T pp_num = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_pp_id);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_id, 0,
+										DPP_ETM_Q_NUM - 1);
+
+	*p_pp_id = 0xffffffff;
+	rc = dpp_reg_read(dev, ETM_CGAVD_PP_NUMr, 0, q_id, &pp_num);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_pp_id = pp_num.pp_num;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置TM模式tc到flow的映射
+ * @param   dev_id 设备编号
+ * @param   tc_id   itmd tc优先级（0~7）
+ * @param   flow_id 映射的flowid号 （0~4095）
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/07/04
+ ************************************************************/
+DPP_STATUS dpp_tm_tc_map_flow_set(DPP_DEV_T *dev, ZXIC_UINT32 tc_id,
+								  ZXIC_UINT32 flow_id)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CGAVD_CFG_TC_FLOWID_DAT_T cfg_tc_flow = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), tc_id, 0,
+										DPP_TM_TC_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0,
+										DPP_ETM_Q_NUM - 1);
+
+	cfg_tc_flow.cfg_tc_flowid_dat = flow_id;
+	rc = dpp_reg_write(dev, ETM_CGAVD_CFG_TC_FLOWID_DATr, 0, tc_id,
+					   &cfg_tc_flow);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取配置TM模式tc到flow的映射
+ * @param   dev_id 设备编号
+ * @param   tc_id   itmd tc优先级（0~7）
+ * @param   flow_id 读取映射的flowid号 （0~4095）
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  sun      @date  2023/07/04
+ ************************************************************/
+DPP_STATUS dpp_tm_tc_map_flow_get(DPP_DEV_T *dev, ZXIC_UINT32 tc_id,
+								  ZXIC_UINT32 *flow_id)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CGAVD_CFG_TC_FLOWID_DAT_T cfg_tc_flow = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), flow_id);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), tc_id, 0,
+										DPP_TM_TC_NUM - 1);
+
+	*flow_id = 0xffffffff;
+	rc = dpp_reg_read(dev, ETM_CGAVD_CFG_TC_FLOWID_DATr, 0, tc_id,
+					  &cfg_tc_flow);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*flow_id = cfg_tc_flow.cfg_tc_flowid_dat;
+
+	return DPP_OK;
+}
+/***********************************************************/
+/** 配置QMU查询队列Qos开关
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   q_id:  队列号
+ * @param   qos_sign: qos开关 0:关闭  1:开启
+ * @param
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  yjd      @date  2015/07/03
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_qos_sign_set(DPP_DEV_T *dev, ZXIC_UINT32 q_id,
+								   ZXIC_UINT32 qos_sign)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_ETM_CGAVD_QOS_SIGN_T qmu_qos_sign = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), qos_sign, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_id, 0,
+										DPP_ETM_Q_NUM - 1);
+
+	qmu_qos_sign.qos_sign_flow_cfg_din = qos_sign;
+
+	rc = dpp_reg_write(dev, ETM_CGAVD_QOS_SIGNr, 0, q_id, &qmu_qos_sign);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+#endif
+
+#if ZXIC_REAL("TM_QMU")
+/***********************************************************/
+/** 读取QMU队列授权价值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_credit_value   授权价值，默认值是533Byte
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy     @date  2016/04/14
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_credit_value_get(DPP_DEV_T *dev,
+									   ZXIC_UINT32 *p_credit_value)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_QCFG_QSCH_CREDIT_VALUE_T credit_val = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_credit_value);
+
+	*p_credit_value = 0;
+
+	rc = dpp_reg_read(dev, ETM_QMU_QCFG_QSCH_CREDIT_VALUEr, 0, 0, &credit_val);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_credit_value = credit_val.qcfg_qsch_credit_value;
+
+	return DPP_OK;
+}
+/***********************************************************/
+/** 配置读命令老化使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   aged_en   读命令老化使能：0：不使能；1：使能
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_wr_aged_en_set(DPP_DEV_T *dev, ZXIC_UINT32 aged_en)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_QCFG_CSCH_AGED_CFG_T aged_cfg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aged_en, 0, 1);
+
+	aged_cfg.qcfg_csch_aged_cfg = aged_en;
+
+	rc = dpp_reg_write(dev, ETM_QMU_QCFG_CSCH_AGED_CFGr, 0, 0, &aged_cfg);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置读命令老化速率
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   scan_time   读命令老化速率（扫描间隔时间）
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_wr_aged_scan_time_set(DPP_DEV_T *dev,
+											ZXIC_UINT32 scan_time)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_QCFG_CSCH_AGED_SCAN_TIME_T aged_scan_time = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), scan_time, 0, 0xffffffff);
+
+	aged_scan_time.qcfg_csch_aged_scan_time = scan_time;
+
+	rc = dpp_reg_write(dev, ETM_QMU_QCFG_CSCH_AGED_SCAN_TIMEr, 0, 0,
+					   &aged_scan_time);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获得读命令老化速率
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_scan_time   读命令老化速率（扫描间隔时间）
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_wr_aged_scan_time_get(DPP_DEV_T *dev,
+											ZXIC_UINT32 *p_scan_time)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_QCFG_CSCH_AGED_SCAN_TIME_T aged_scan_time = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_scan_time);
+
+	rc = dpp_reg_read(dev, ETM_QMU_QCFG_CSCH_AGED_SCAN_TIMEr, 0, 0,
+					  &aged_scan_time);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_scan_time = aged_scan_time.qcfg_csch_aged_scan_time;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取QMU清空状态
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_clr_done_flag   队列是否清空完成
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  szq      @date  2015/05/21
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_qlist_qcfg_clr_done_get(DPP_DEV_T *dev,
+											  ZXIC_UINT32 *p_clr_done_flag)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_QLIST_QCFG_CLR_DONE_T clr_done_flag = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_clr_done_flag);
+
+	rc = dpp_reg_read(dev, ETM_QMU_QLIST_QCFG_CLR_DONEr, 0, 0, &clr_done_flag);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_clr_done_flag = clr_done_flag.qlist_qcfg_clr_done;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置qsch调度分端口整形速率和使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   shape_en   整形使能
+ * @param   token_add_num   [23:12]:添加令牌数目
+ * @param   token_gap   [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1
+ * @param   token_depth 桶深，单位B,范围[0-0x1EE00]
+ *公式：（1000*8*token_num）/(gap+1) = X Mbps
+ *     主频= 600 MHz
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  xuhb   2020-5-15
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_qsch_port_shape_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+										  ZXIC_UINT32 token_add_num,
+										  ZXIC_UINT32 token_gap,
+										  ZXIC_UINT32 token_depth,
+										  ZXIC_UINT32 shape_en)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_QCFG_QSCH_SHAP_PARAM_T qsch_shap_param = { 0 };
+	DPP_ETM_QMU_QCFG_QSCH_SHAP_TOKEN_T qsch_shap_token_depth = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0,
+										DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), shape_en, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_add_num, 0, 0xfff);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_gap, 0, 0xfff);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_depth, 0, 0x1f000);
+
+	/* 配置整形桶深 */
+	qsch_shap_token_depth.qcfg_qsch_shap_token = token_depth;
+	rc = dpp_reg_write(dev, ETM_QMU_QCFG_QSCH_SHAP_TOKENr, 0, port_id,
+					   &qsch_shap_token_depth);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	qsch_shap_param.qcfg_qsch_shap_en = shape_en;
+	qsch_shap_param.qcfg_qsch_shap_param1 = token_add_num;
+	qsch_shap_param.qcfg_qsch_shap_param2 = token_gap;
+	rc = dpp_reg_write(dev, ETM_QMU_QCFG_QSCH_SHAP_PARAMr, 0, port_id,
+					   &qsch_shap_param);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置CMD_SW分端口整形速率和使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   shape_en   整形使能
+ * @param   token_add_num   [23:12]:添加令牌数目
+ * @param   token_gap   [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1
+ * @param   token_depth 桶深，单位B,范围[0-0x1EE00]
+ *公式：（1000*8*token_num）/(gap+1) = X Mbps
+ *     主频= 600 MHz
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  whuashan   2020-3-17
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_port_shape_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+									 ZXIC_UINT32 token_add_num,
+									 ZXIC_UINT32 token_gap,
+									 ZXIC_UINT32 token_depth,
+									 ZXIC_UINT32 shape_en)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_QCFG_CSW_SHAP_PARAMETER_T csw_shap_param = { 0 };
+	DPP_ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTH_T csw_shap_token_depth = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0,
+										DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), shape_en, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_add_num, 0, 0xfff);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_gap, 0, 0xfff);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_depth, 0, 0x1ee00);
+
+	/* 配置整形桶深 */
+	csw_shap_token_depth.qcfg_csw_shap_token_depth = token_depth;
+	rc = dpp_reg_write(dev, ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTHr, 0, port_id,
+					   &csw_shap_token_depth);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	csw_shap_param.qcfg_csw_shap_en = shape_en;
+	csw_shap_param.qcfg_csw_shap_parameter = (token_add_num << 12) | token_gap;
+	rc = dpp_reg_write(dev, ETM_QMU_QCFG_CSW_SHAP_PARAMETERr, 0, port_id,
+					   &csw_shap_param);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获得CMD_SW分端口整形速率和使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_shape_en   整形使能
+ * @param   p_token_add_num   [23:12]:添加令牌数目
+ * @param   p_token_gap   [11:0]:添加令牌间隔，其中实际间隔为配置间隔+1
+ * @param   p_token_depth 桶深，单位B
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  whuashan   2020-3-17
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_port_shape_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+									 ZXIC_UINT32 *p_token_add_num,
+									 ZXIC_UINT32 *p_token_gap,
+									 ZXIC_UINT32 *p_token_depth,
+									 ZXIC_UINT32 *p_shape_en)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_QCFG_CSW_SHAP_PARAMETER_T csw_shap_param = { 0 };
+	DPP_ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTH_T csw_shap_token_depth = { 0 };
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0,
+										DPP_TM_PP_NUM - 1);
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_token_add_num);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_token_gap);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_token_depth);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_shape_en);
+
+	rc = dpp_reg_read(dev, ETM_QMU_QCFG_CSW_SHAP_PARAMETERr, 0, port_id,
+					  &csw_shap_param);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_shape_en = csw_shap_param.qcfg_csw_shap_en;
+	*p_token_add_num = (csw_shap_param.qcfg_csw_shap_parameter >> 12) & 0xfff;
+	*p_token_gap = csw_shap_param.qcfg_csw_shap_parameter & 0xfff;
+
+	rc = dpp_reg_read(dev, ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTHr, 0, port_id,
+					  &csw_shap_token_depth);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_token_depth = csw_shap_token_depth.qcfg_csw_shap_token_depth;
+
+	return DPP_OK;
+}
+/***********************************************************/
+/** 配置需要检测的特定队列号
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   qnum   需要检测统计的特定的队列号
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/18
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_spec_qnum_set(DPP_DEV_T *dev, ZXIC_UINT32 qnum)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_OBSERVE_QNUM_SET_T observe_qnum = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), qnum, 0,
+										DPP_ETM_Q_NUM - 1);
+
+	observe_qnum.observe_qnum_set = qnum;
+	rc = dpp_reg_write(dev, ETM_QMU_OBSERVE_QNUM_SETr, 0, 0, &observe_qnum);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获得特定的队列号
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_qnum   需要检测统计的特定的队列号
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/23
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_spec_qnum_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_qnum)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_OBSERVE_QNUM_SET_T observe_qnum = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qnum);
+
+	rc = dpp_reg_read(dev, ETM_QMU_OBSERVE_QNUM_SETr, 0, 0, &observe_qnum);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_qnum = observe_qnum.observe_qnum_set;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置需要检测的队列组
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   group_num   需要检测统计的特定的队列组。这里按取q的低3bit
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/18
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_spec_group_set(DPP_DEV_T *dev, ZXIC_UINT32 group_num)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_OBSERVE_BATCH_SET_T observe_batch = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), group_num, 0, 7);
+
+	observe_batch.observe_batch_set = group_num;
+	rc = dpp_reg_write(dev, ETM_QMU_OBSERVE_BATCH_SETr, 0, 0, &observe_batch);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获得需要检测的队列组
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_group_num   需要检测统计的特定的队列组。这里按取q的低3bit
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/23
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_spec_group_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_group_num)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_OBSERVE_BATCH_SET_T observe_batch = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_group_num);
+
+	rc = dpp_reg_read(dev, ETM_QMU_OBSERVE_BATCH_SETr, 0, 0, &observe_batch);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_group_num = observe_batch.observe_batch_set;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置自动授权队列范围
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   first_que   自授权起始队列号
+ * @param   last_que   自授权终止队列号
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/19
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_auto_credit_que_set(DPP_DEV_T *dev, ZXIC_UINT32 first_que,
+										  ZXIC_UINT32 last_que)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_CFG_QSCH_AUTOCRFRSTQUE_T qsch_autocrfrstque = { 0 };
+	DPP_ETM_QMU_CFG_QSCH_AUTOCRLASTQUE_T qsch_autocrlastque = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), first_que, 0,
+										DPP_ETM_Q_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), last_que, 0,
+										DPP_ETM_Q_NUM - 1);
+
+	if (first_que > last_que) {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+								  "[dev_id %d] first_que > last_que, err!!!\n",
+								  DEV_ID(dev));
+
+		return DPP_ERR;
+	}
+
+	qsch_autocrfrstque.cfg_qsch_autocrfrstque = first_que;
+	rc = dpp_reg_write(dev, ETM_QMU_CFG_QSCH_AUTOCRFRSTQUEr, 0, 0,
+					   &qsch_autocrfrstque);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	qsch_autocrlastque.cfg_qsch_autocrlastque = last_que;
+	rc = dpp_reg_write(dev, ETM_QMU_CFG_QSCH_AUTOCRLASTQUEr, 0, 0,
+					   &qsch_autocrlastque);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获得自动授权队列范围
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_first_que   自授权起始队列号
+ * @param   p_last_que   自授权终止队列号
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/23
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_auto_credit_que_get(DPP_DEV_T *dev,
+										  ZXIC_UINT32 *p_first_que,
+										  ZXIC_UINT32 *p_last_que)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_CFG_QSCH_AUTOCRFRSTQUE_T qsch_autocrfrstque = { 0 };
+	DPP_ETM_QMU_CFG_QSCH_AUTOCRLASTQUE_T qsch_autocrlastque = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_first_que);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_last_que);
+
+	rc = dpp_reg_read(dev, ETM_QMU_CFG_QSCH_AUTOCRFRSTQUEr, 0, 0,
+					  &qsch_autocrfrstque);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+	*p_first_que = qsch_autocrfrstque.cfg_qsch_autocrfrstque;
+
+	rc = dpp_reg_read(dev, ETM_QMU_CFG_QSCH_AUTOCRLASTQUEr, 0, 0,
+					  &qsch_autocrlastque);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+	*p_last_que = qsch_autocrlastque.cfg_qsch_autocrlastque;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置自动授权开启使能及扫描速率
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   auto_crdt_en   自动授权开启使能，默认关闭。0：关闭；1：开启
+ * @param   auto_crdt_rate   自授权速率配置
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/19
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_auto_credit_rate_set(DPP_DEV_T *dev,
+										   ZXIC_UINT32 auto_crdt_en,
+										   ZXIC_UINT32 auto_crdt_rate)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_EN_T credit_control_en = { 0 };
+	DPP_ETM_QMU_CFG_QSCH_AUTOCREDITRATE_T autocredit_rate = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), auto_crdt_en, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), auto_crdt_rate, 0,
+										0xfffff);
+
+	credit_control_en.cfg_qsch_auto_credit_control_en = auto_crdt_en;
+	rc = dpp_reg_write(dev, ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_ENr, 0, 0,
+					   &credit_control_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	autocredit_rate.cfg_qsch_autocreditrate = auto_crdt_rate;
+	rc = dpp_reg_write(dev, ETM_QMU_CFG_QSCH_AUTOCREDITRATEr, 0, 0,
+					   &autocredit_rate);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获得自动授权开启使能及扫描速率
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_auto_crdt_en   自动授权开启使能，默认关闭。0：关闭；1：开启
+ * @param   p_auto_crdt_rate   自授权速率配置
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/06/23
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_auto_credit_rate_get(DPP_DEV_T *dev,
+										   ZXIC_UINT32 *p_auto_crdt_en,
+										   ZXIC_UINT32 *p_auto_crdt_rate)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_EN_T credit_control_en = { 0 };
+	DPP_ETM_QMU_CFG_QSCH_AUTOCREDITRATE_T autocredit_rate = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_auto_crdt_en);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_auto_crdt_rate);
+
+	rc = dpp_reg_read(dev, ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_ENr, 0, 0,
+					  &credit_control_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+	*p_auto_crdt_en = credit_control_en.cfg_qsch_auto_credit_control_en;
+
+	rc = dpp_reg_read(dev, ETM_QMU_CFG_QSCH_AUTOCREDITRATEr, 0, 0,
+					  &autocredit_rate);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+	*p_auto_crdt_rate = autocredit_rate.cfg_qsch_autocreditrate;
+
+	return DPP_OK;
+}
+/***********************************************************/
+/**设置自然拥塞反压门限值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param
+ * @return
+ * @remark  无
+ * @see
+ * @author  yjd     @date  2015/07/16
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_qcfg_csch_congest_th_set(DPP_DEV_T *dev,
+											   ZXIC_UINT32 port_id,
+											   ZXIC_UINT32 qmu_congest_th)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_QCFG_CSCH_CONGEST_TH_T qcfg_csch_congest_th = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0,
+										DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), qmu_congest_th, 0,
+										0x1ffff);
+
+	qcfg_csch_congest_th.qcfg_csch_congest_th = qmu_congest_th;
+	rc = dpp_reg_write(dev, ETM_QMU_QCFG_CSCH_CONGEST_THr, 0, port_id,
+					   &qcfg_csch_congest_th);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**获取自然拥塞反压门限值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param
+ * @return
+ * @remark  无
+ * @see
+ * @author  yjd     @date  2015/07/16
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_qcfg_csch_congest_th_get(DPP_DEV_T *dev,
+											   ZXIC_UINT32 port_id,
+											   ZXIC_UINT32 *p_qmu_congest_th)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_QCFG_CSCH_CONGEST_TH_T qcfg_csch_congest_th = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qmu_congest_th);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0,
+										DPP_TM_PP_NUM - 1);
+
+	rc = dpp_reg_read(dev, ETM_QMU_QCFG_CSCH_CONGEST_THr, 0, port_id,
+					  &qcfg_csch_congest_th);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_qmu_congest_th = qcfg_csch_congest_th.qcfg_csch_congest_th;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**设置CMD_SCH分优先级反压门限值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param
+ * @return
+ * @remark  无
+ * @see
+ * @author  yjd     @date  2015/07/16
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_qcfg_csch_sp_fc_th_set(DPP_DEV_T *dev,
+											 ZXIC_UINT32 port_id,
+											 ZXIC_UINT32 q_pri,
+											 ZXIC_UINT32 qmu_sp_fc_th)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 index = 0;
+	DPP_ETM_QMU_QCFG_CSCH_SP_FC_TH_T qcfg_csch_sp_fc_th = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0,
+										DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_pri, 0, 4);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), qmu_sp_fc_th, 0, 0x1ffff);
+
+	index = port_id * 5 + q_pri;
+	qcfg_csch_sp_fc_th.qcfg_csch_sp_fc_th = qmu_sp_fc_th;
+
+	rc = dpp_reg_write(dev, ETM_QMU_QCFG_CSCH_SP_FC_THr, 0, index,
+					   &qcfg_csch_sp_fc_th);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/**获取自然拥塞反压门限值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param
+ * @return
+ * @remark  无
+ * @see
+ * @author  yjd     @date  2015/07/16
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_qcfg_csch_sp_fc_th_get(DPP_DEV_T *dev,
+											 ZXIC_UINT32 port_id,
+											 ZXIC_UINT32 q_pri,
+											 ZXIC_UINT32 *p_qmu_sp_fc_th)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 index = 0;
+	DPP_ETM_QMU_QCFG_CSCH_SP_FC_TH_T qcfg_csch_sp_fc_th = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0,
+										DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_pri, 0, 4);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_qmu_sp_fc_th);
+
+	index = port_id * 5 + q_pri;
+
+	rc = dpp_reg_read(dev, ETM_QMU_QCFG_CSCH_SP_FC_THr, 0, index,
+					  &qcfg_csch_sp_fc_th);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_qmu_sp_fc_th = qcfg_csch_sp_fc_th.qcfg_csch_sp_fc_th;
+
+	return DPP_OK;
+}
+/***********************************************************/
+/** 配置QMU流控计数模式
+ * @param   dev_id   设备号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   mode   流控模式，0-电平流控；1-边沿流控
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/05/07
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_fc_cnt_mode_set(DPP_DEV_T *dev, ZXIC_UINT32 mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_FC_CNT_MODE_T fc_cnt_mode_reg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1);
+
+	fc_cnt_mode_reg.fc_cnt_mode = mode;
+	rc = dpp_reg_write(dev, ETM_QMU_FC_CNT_MODEr, 0, 0, &fc_cnt_mode_reg);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取QMU流控计数模式
+ * @param   dev_id   设备号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_mode   流控模式，0-电平流控；1-边沿流控
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/05/07
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_fc_cnt_mode_get(DPP_DEV_T *dev, ZXIC_UINT32 *p_mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_FC_CNT_MODE_T fc_cnt_mode_reg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_mode);
+
+	rc = dpp_reg_read(dev, ETM_QMU_FC_CNT_MODEr, 0, 0, &fc_cnt_mode_reg);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*p_mode = fc_cnt_mode_reg.fc_cnt_mode;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置QMU需要检测流控的端口号
+ * @param   dev_id   设备号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   port_id   端口号
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/05/07
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_observe_portfc_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_OBSERVE_PORTFC_SPEC_T observe_portfc_reg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0,
+										DPP_TM_PP_NUM - 1);
+
+	observe_portfc_reg.observe_portfc_spec = port_id;
+	rc = dpp_reg_write(dev, ETM_QMU_OBSERVE_PORTFC_SPECr, 0, 0,
+					   &observe_portfc_reg);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置QMU需要统计的队列号
+ * @param   dev_id   设备号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   q_id   队列号
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/05/07
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_observe_qnum_set(DPP_DEV_T *dev, ZXIC_UINT32 q_id)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_OBSERVE_QNUM_SET_T observe_qnum_reg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), q_id, 0,
+										DPP_ETM_Q_NUM - 1);
+
+	observe_qnum_reg.observe_qnum_set = q_id;
+	rc = dpp_reg_write(dev, ETM_QMU_OBSERVE_PORTFC_SPECr, 0, 0,
+					   &observe_qnum_reg);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置QMU需要统计的队列组
+ * @param   dev_id   设备号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   batch_id   队列组
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/05/07
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_observe_batch_set(DPP_DEV_T *dev, ZXIC_UINT32 batch_id)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_OBSERVE_BATCH_SET_T observe_batch_reg = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), batch_id, 0, 7);
+
+	observe_batch_reg.observe_batch_set = batch_id;
+	rc = dpp_reg_write(dev, ETM_QMU_OBSERVE_BATCH_SETr, 0, 0,
+					   &observe_batch_reg);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/******************************************************************************
+ *包老化配置
+ * @param: dev_id: 设备索引编号
+ * @param   tm_type   0-ETM,1-FTM
+ *           aging_en: 包老化使能：1表示包老化功能使能；0表示包老化功能关闭。
+ *           aging_interval: 普通老化两次的间隔配置
+ *           aging_step_interval: 普通老化的老化时间的步进配置值
+ *           aging_start_qnum: 老化起始队列
+ *           aging_end_qnum: 老化结束队列
+ *           aging_req_aful_th: 普通老化FIFO的将满阈值
+ *           aging_pkt_num: 一次老化的包个数
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/05/10
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_pkt_aging_set(DPP_DEV_T *dev, ZXIC_UINT32 aging_en,
+									ZXIC_UINT32 aging_interval,
+									ZXIC_UINT32 aging_step_interval,
+									ZXIC_UINT32 aging_start_qnum,
+									ZXIC_UINT32 aging_end_qnum,
+									ZXIC_UINT32 aging_pkt_num,
+									ZXIC_UINT32 aging_req_aful_th)
+{
+	/* 返回值变量定义 */
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 age_pkt_num_reg_index = 0;
+	ZXIC_UINT32 age_step_interval_reg_index = 0;
+	ZXIC_UINT32 age_interval_reg_index = 0;
+	ZXIC_UINT32 age_qnum_reg_index = 0;
+	ZXIC_UINT32 age_req_aful_th_reg_index = 0;
+	ZXIC_UINT32 age_en_reg_index = 0;
+
+	/* 结构体变量定义 */
+	DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_EN_T cfg_age_en = { 0 };
+	DPP_ETM_QMU_CFGMT_PKT_AGE_STEP_INTERVAL_T cfg_age_step_interval = { 0 };
+	DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_INTERVAL_T cfg_age_interval = { 0 };
+	DPP_ETM_QMU_CFGMT_QMU_PKT_AGE_START_END_T cfg_age_qnum = { 0 };
+	DPP_ETM_QMU_CFGMT_PKT_AGE_REQ_AFUL_TH_T cfg_age_req_aful_th = { 0 };
+	DPP_ETM_QMU_CFGMT_AGE_PKT_NUM_T cfg_age_pkt_num = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_en, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_step_interval, 0,
+										0xff);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_interval, 0, 0xffff);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_req_aful_th, 0,
+										0x3f);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_pkt_num, 0, 0xf);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_start_qnum, 0,
+										DPP_ETM_Q_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_end_qnum, 0,
+										DPP_ETM_Q_NUM - 1);
+	age_pkt_num_reg_index = ETM_QMU_CFGMT_AGE_PKT_NUMr;
+	age_step_interval_reg_index = ETM_QMU_CFGMT_PKT_AGE_STEP_INTERVALr;
+	age_interval_reg_index = ETM_QMU_CFGMT_QMU_PKT_AGE_INTERVALr;
+	age_qnum_reg_index = ETM_QMU_CFGMT_QMU_PKT_AGE_START_ENDr;
+	age_req_aful_th_reg_index = ETM_QMU_CFGMT_PKT_AGE_REQ_AFUL_THr;
+	age_en_reg_index = ETM_QMU_CFGMT_QMU_PKT_AGE_ENr;
+
+	cfg_age_en.cfgmt_qmu_pkt_age_en = aging_en;
+	cfg_age_step_interval.cfgmt_pkt_age_step_interval = aging_step_interval;
+	cfg_age_interval.cfgmt_qmu_pkt_age_interval = aging_interval;
+	cfg_age_qnum.cfgmt_qmu_pkt_age_start = aging_start_qnum;
+	cfg_age_qnum.cfgmt_qmu_pkt_age_end = aging_end_qnum;
+	cfg_age_req_aful_th.cfgmt_pkt_age_req_aful_th = aging_req_aful_th;
+	cfg_age_pkt_num.cfgmt_age_pkt_num = aging_pkt_num;
+
+	rc = dpp_reg_write(dev, age_pkt_num_reg_index, 0, 0, &cfg_age_pkt_num);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	rc = dpp_reg_write(dev, age_step_interval_reg_index, 0, 0,
+					   &cfg_age_step_interval);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	rc = dpp_reg_write(dev, age_interval_reg_index, 0, 0, &cfg_age_interval);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	rc = dpp_reg_write(dev, age_qnum_reg_index, 0, 0, &cfg_age_qnum);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	rc = dpp_reg_write(dev, age_req_aful_th_reg_index, 0, 0,
+					   &cfg_age_req_aful_th);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	rc = dpp_reg_write(dev, age_en_reg_index, 0, 0, &cfg_age_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/******************************************************************************
+*配置老化一个包的时间，一次老化一个包，老化队列范围为可配
+* @param: dev_id: 设备索引编号
+* @param    tm_type   0: etm; 1: ftm;
+*           aging_en: 包老化使能：1表示包老化功能使能；0表示包老化功能关闭。
+*           aging_time: 老化一个包的时间，单位ms
+*            aging_que_start:老化起始队列
+*             aging_que_start:老化终止队列
+老化时间=2*aging_interval*step_interval*q_num
+aging_interval = (aging_time * 600000) / (2 * 1 * DPP_TM_Q_NUM);
+* @return   DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  xuhb     @date  2020/12/08
+************************************************************/
+DPP_STATUS dpp_tm_qmu_pkt_age_time_set(DPP_DEV_T *dev, ZXIC_UINT32 aging_en,
+									   ZXIC_UINT32 aging_time,
+									   ZXIC_UINT32 aging_que_start,
+									   ZXIC_UINT32 aging_que_end)
+{
+	/* 返回值变量定义 */
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 aging_interval = 0;
+	// DPP_CRM_CSR_PLL_CLK_SEL_T pll_clk_sel_t = {0};
+	// ZXIC_UINT32 sys_clk = 0;
+	// ZXIC_UINT32 sys_clk_temp[8]={200,250,300,500,600,800,1000,1200};
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_en, 0, 1);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_que_start, 0,
+										DPP_ETM_Q_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), aging_que_end, 0,
+										DPP_ETM_Q_NUM - 1);
+
+	if (0 == aging_interval) {
+		aging_interval = 1; /* 防止算出来的是小数，导致写入0 */
+	}
+
+	rc = dpp_tm_qmu_pkt_aging_set(dev, aging_en, aging_interval, 1,
+								  aging_que_start, aging_que_end, 1, 0xa);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_qmu_pkt_aging_set");
+
+	return DPP_OK;
+}
+/***********************************************************/
+/** 配置pfc使能
+ * @param   dev_id   设备编号
+ * @param   pfc_en   配置的值，0-不使能pfc，1-使能pfc
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  lsy      @date  2022/08/22
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_pfc_en_set(DPP_DEV_T *dev, ZXIC_UINT32 pfc_en)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_CFGMT_QMU_PFC_EN_T qmu_pfc_en = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pfc_en, 0, 1);
+
+	qmu_pfc_en.cfgmt_qmu_pfc_en = pfc_en;
+	rc = dpp_reg_write(dev, ETM_QMU_CFGMT_QMU_PFC_ENr, 0, 0, &qmu_pfc_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取pfc使能
+ * @param   dev_id   设备编号
+ * @param   pfc_en   配置的值，0-不使能pfc，1-使能pfc
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  lsy      @date  2022/08/22
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_pfc_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *pfc_en)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_QMU_CFGMT_QMU_PFC_EN_T qmu_pfc_en = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), pfc_en);
+
+	*pfc_en = 0xffffffff;
+	rc = dpp_reg_read(dev, ETM_QMU_CFGMT_QMU_PFC_ENr, 0, 0, &qmu_pfc_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*pfc_en = qmu_pfc_en.cfgmt_qmu_pfc_en;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置端口pfc掩码
+ * @param   dev_id   设备编号
+ * @param   port_id   端口号：0~63
+ * @param   port_en   端口掩码配置，1pfc模式下该端口接收olif的优先级反压，
+ *                                  0pfc模式下该端口不接受olif的优先级反压，并将反压信号全部置1
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  lsy      @date  2022/08/22
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_port_pfc_make_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+										ZXIC_UINT32 port_en)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 value = 0;
+	DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_1_T pfc_mask_31_0 = { 0 };
+	DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_2_T pfc_mask_63_32 = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0,
+										DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_en, 0, 1);
+
+	if (port_id <= 31) {
+		/* port_id:[0-31] */
+		rc = dpp_reg_read(dev, ETM_QMU_CFGMT_QMU_PFC_MASK_1r, 0, 0,
+						  &pfc_mask_31_0);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+		value = pfc_mask_31_0.cfgmt_qmu_pfc_mask_1;
+
+		if (port_en == 0) {
+			value = value & (~(1u << port_id));
+		} else {
+			value = value | (1u << port_id);
+		}
+
+		pfc_mask_31_0.cfgmt_qmu_pfc_mask_1 = value;
+
+		rc = dpp_reg_write(dev, ETM_QMU_CFGMT_QMU_PFC_MASK_1r, 0, 0,
+						   &pfc_mask_31_0);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+	} else {
+		/* port_id:[32-63] */
+		rc = dpp_reg_read(dev, ETM_QMU_CFGMT_QMU_PFC_MASK_2r, 0, 0,
+						  &pfc_mask_63_32);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+		value = pfc_mask_63_32.cfgmt_qmu_pfc_mask_2;
+
+		if (port_en == 0) {
+			value = value & (~(1u << (port_id - 32)));
+		} else {
+			value = value | (1u << (port_id - 32));
+		}
+
+		pfc_mask_63_32.cfgmt_qmu_pfc_mask_2 = value;
+
+		rc = dpp_reg_write(dev, ETM_QMU_CFGMT_QMU_PFC_MASK_2r, 0, 0,
+						   &pfc_mask_63_32);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获得端口pfc掩码
+ * @param   dev_id   设备编号
+ * @param   port_id   端口号：0~63
+ * @param   port_en   端口掩码配置，1pfc模式下该端口接收olif的优先级反压，
+ *                                  0pfc模式下该端口不接受olif的优先级反压，并将反压信号全部置1
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  lsy      @date  2022/08/22
+ ************************************************************/
+DPP_STATUS dpp_tm_qmu_port_pfc_make_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+										ZXIC_UINT32 *p_port_en)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 value = 0;
+	DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_1_T pfc_mask_31_0 = { 0 };
+	DPP_ETM_QMU_CFGMT_QMU_PFC_MASK_2_T pfc_mask_63_32 = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0,
+										DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_port_en);
+
+	if (port_id <= 31) {
+		/* port_id:[0-31] */
+		rc = dpp_reg_read(dev, ETM_QMU_CFGMT_QMU_PFC_MASK_1r, 0, 0,
+						  &pfc_mask_31_0);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+		value = pfc_mask_31_0.cfgmt_qmu_pfc_mask_1;
+
+		*p_port_en = 1 & (value >> port_id);
+	} else {
+		/* port_id:[32-63] */
+		rc = dpp_reg_read(dev, ETM_QMU_CFGMT_QMU_PFC_MASK_2r, 0, 0,
+						  &pfc_mask_63_32);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+		value = pfc_mask_63_32.cfgmt_qmu_pfc_mask_2;
+
+		*p_port_en = 1 & (value >> (port_id - 32));
+	}
+
+	return DPP_OK;
+}
+#endif
+
+#if ZXIC_REAL("TM_TMMU")
+#endif
+
+#if ZXIC_REAL("TM_CRDT")
+/***********************************************************/
+/** 分配etm-FQ类型调度器资源：fq/fq2/fq4/fq8 个数，(共16K= 16384)
+ * @param   dev_id   设备编号
+ * @param   fq_num   FQ调度器个数，须是8的倍数
+ * @param   fq2_num  FQ2调度器个数，须是4的倍数
+ * @param   fq4_num  FQ4调度器个数，须是2的倍数
+ * @param   fq8_num  FQ8调度器个数
+ *          调度器总数不能超过：16K= 16384
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/26
+ ************************************************************/
+DPP_STATUS dpp_etm_crdt_fq_set(DPP_DEV_T *dev, ZXIC_UINT32 fq_num,
+							   ZXIC_UINT32 fq2_num, ZXIC_UINT32 fq4_num,
+							   ZXIC_UINT32 fq8_num)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 total_fq_num = 0;
+	DPP_ETM_CRDT_TH_WFQ_FQ_T etm_crdt_th_wfqfq_t = { 0 };
+	DPP_ETM_CRDT_TH_WFQ2_FQ2_T etm_crdt_th_wfqfq2_t = { 0 };
+	DPP_ETM_CRDT_TH_WFQ4_FQ4_T etm_crdt_th_wfqfq4_t = { 0 };
+	ZXIC_UINT32 th_wfq_fq_index = ETM_CRDT_TH_WFQ_FQr;
+	ZXIC_UINT32 th_wfq_fq2_index = ETM_CRDT_TH_WFQ2_FQ2r;
+	ZXIC_UINT32 th_wfq_fq4_index = ETM_CRDT_TH_WFQ4_FQ4r;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+	/* 参数合法性检查:fq调度器总数校验 */
+	ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), fq2_num, 2);
+	ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), fq4_num, 4);
+	ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), fq8_num, 8);
+	ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), fq_num,
+													 fq2_num * 2);
+	ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(
+			DEV_ID(dev), fq_num + fq2_num * 2, fq4_num * 4);
+	ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(
+			DEV_ID(dev), fq_num + fq2_num * 2 + fq4_num * 4, fq8_num * 8);
+
+	total_fq_num = (fq_num + fq2_num * 2 + fq4_num * 4 + fq8_num * 8);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), total_fq_num, 0,
+										DPP_ETM_FQ_NUM);
+
+	/* 各调度器数整齐性校验 */
+	if ((fq_num != 0 && fq_num % 8 != 0) ||
+		(fq2_num != 0 && fq2_num % 4 != 0) ||
+		(fq4_num != 0 && fq4_num % 2 != 0)) {
+		// ZXIC_COMM__TRACE_ERR("Bad parameter: sp_num or wfq_num %8 != 0 !");
+		return DPP_ERR;
+	}
+
+	/* 开始调度器阈值配置：th_fq参数配置：th_fq = fq_num/8 */
+	rc = dpp_reg_read(dev, th_wfq_fq_index, 0, 0, &etm_crdt_th_wfqfq_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	etm_crdt_th_wfqfq_t.th_fq = (fq_num / 8);
+	rc = dpp_reg_write(dev, th_wfq_fq_index, 0, 0, &etm_crdt_th_wfqfq_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	/* th_fq2参数配置：th_fq2 = (th_fq + fq2_num/4) */
+	rc = dpp_reg_read(dev, th_wfq_fq2_index, 0, 0, &etm_crdt_th_wfqfq2_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	etm_crdt_th_wfqfq2_t.th_fq2 = (etm_crdt_th_wfqfq_t.th_fq + fq2_num / 4);
+	rc = dpp_reg_write(dev, th_wfq_fq2_index, 0, 0, &etm_crdt_th_wfqfq2_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	/* th_fq4参数配置：th_fq4 = (th_fq2 + fq4_num/2) */
+	rc = dpp_reg_read(dev, th_wfq_fq4_index, 0, 0, &etm_crdt_th_wfqfq4_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	etm_crdt_th_wfqfq4_t.th_fq4 = (etm_crdt_th_wfqfq2_t.th_fq2 + fq4_num / 2);
+	rc = dpp_reg_write(dev, th_wfq_fq4_index, 0, 0, &etm_crdt_th_wfqfq4_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 分配TM-SP/WFQ类型调度器资源：sp/wfq/wfq2/wfq4/wfq8 个数，（etm共9K=9216,ftm共1920个）
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   sp_num   SP调度器个数，须是8的倍数
+ * @param   wfq_num  WFQ调度器个数，须是8的倍数
+ * @param   wfq2_num  WFQ2调度器个数，须是4的倍数
+ * @param   wfq4_num  WFQ4调度器个数，须是2的倍数
+ * @param   wfq8_num  WFQ8调度器个数
+ *          调度器总数不能超过：ETM= 9216; FTM= 1920
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/26
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_wfqsp_set(DPP_DEV_T *dev, ZXIC_UINT32 sp_num,
+								 ZXIC_UINT32 wfq_num, ZXIC_UINT32 wfq2_num,
+								 ZXIC_UINT32 wfq4_num, ZXIC_UINT32 wfq8_num)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 total_wfqsp_num = 0;
+	DPP_ETM_CRDT_TH_SP_T etm_crdt_th_sp_t = { 0 };
+	DPP_ETM_CRDT_TH_WFQ_FQ_T etm_crdt_th_wfqfq_t = { 0 };
+	DPP_ETM_CRDT_TH_WFQ2_FQ2_T etm_crdt_th_wfqfq2_t = { 0 };
+	DPP_ETM_CRDT_TH_WFQ4_FQ4_T etm_crdt_th_wfqfq4_t = { 0 };
+	ZXIC_UINT32 th_sp_index = ETM_CRDT_TH_SPr;
+	ZXIC_UINT32 th_wfq_fq_index = ETM_CRDT_TH_WFQ_FQr;
+	ZXIC_UINT32 th_wfq_fq2_index = ETM_CRDT_TH_WFQ2_FQ2r;
+	ZXIC_UINT32 th_wfq_fq4_index = ETM_CRDT_TH_WFQ4_FQ4r;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+	/* 参数合法性检查 */
+	ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), wfq2_num, 2);
+	ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), wfq4_num, 4);
+	ZXIC_COMM_CHECK_DEV_INDEX_MUL_OVERFLOW_NO_ASSERT(DEV_ID(dev), wfq8_num, 8);
+	ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), sp_num,
+													 wfq_num);
+	ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(
+			DEV_ID(dev), sp_num + wfq_num, wfq2_num * 2);
+	ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(
+			DEV_ID(dev), sp_num + wfq_num + wfq2_num * 2, wfq4_num * 4);
+	ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(
+			DEV_ID(dev), sp_num + wfq_num + wfq2_num * 2 + wfq4_num * 4,
+			wfq8_num * 8);
+	/* 调度器总数校验 */
+	total_wfqsp_num =
+			(sp_num + wfq_num + wfq2_num * 2 + wfq4_num * 4 + wfq8_num * 8);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), total_wfqsp_num, 0,
+										DPP_ETM_WFQSP_NUM);
+
+	/* 各调度器数整齐性校验 */
+	if ((sp_num != 0 && sp_num % 8 != 0) ||
+		(wfq_num != 0 && wfq_num % 8 != 0) ||
+		(wfq2_num != 0 && wfq2_num % 4 != 0) ||
+		(wfq4_num != 0 && wfq4_num % 2 != 0)) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev), "Bad parameter: sp_num or wfq_num mod 8 != 0 !\n");
+		return DPP_ERR;
+	}
+
+	th_sp_index = ETM_CRDT_TH_SPr;
+	th_wfq_fq_index = ETM_CRDT_TH_WFQ_FQr;
+	th_wfq_fq2_index = ETM_CRDT_TH_WFQ2_FQ2r;
+	th_wfq_fq4_index = ETM_CRDT_TH_WFQ4_FQ4r;
+
+	/* 开始调度器阈值配置：th_sp参数配置：th_sp=      sp_num/8 */
+	rc = dpp_reg_read(dev, th_sp_index, 0, 0, &etm_crdt_th_sp_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	etm_crdt_th_sp_t.th_sp = (sp_num / 8);
+	rc = dpp_reg_write(dev, th_sp_index, 0, 0, &etm_crdt_th_sp_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	/* th_wfq参数配置：th_wfq = (th_sp + wfq_num/8)       */
+	rc = dpp_reg_read(dev, th_wfq_fq_index, 0, 0, &etm_crdt_th_wfqfq_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	etm_crdt_th_wfqfq_t.th_wfq = (etm_crdt_th_sp_t.th_sp + wfq_num / 8);
+	rc = dpp_reg_write(dev, th_wfq_fq_index, 0, 0, &etm_crdt_th_wfqfq_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	/* th_wfq2参数配置：th_wfq2 = (th_wfq +      wfq2_num/4) */
+	rc = dpp_reg_read(dev, th_wfq_fq2_index, 0, 0, &etm_crdt_th_wfqfq2_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	etm_crdt_th_wfqfq2_t.th_wfq2 = (etm_crdt_th_wfqfq_t.th_wfq + wfq2_num / 4);
+	rc = dpp_reg_write(dev, th_wfq_fq2_index, 0, 0, &etm_crdt_th_wfqfq2_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	/* th_wfq4参数配置：th_wfq4 = (th_wfq2 +      wfq4_num/2) */
+	rc = dpp_reg_read(dev, th_wfq_fq4_index, 0, 0, &etm_crdt_th_wfqfq4_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	etm_crdt_th_wfqfq4_t.th_wfq4 =
+			(etm_crdt_th_wfqfq2_t.th_wfq2 + wfq4_num / 2);
+	rc = dpp_reg_write(dev, th_wfq_fq4_index, 0, 0, &etm_crdt_th_wfqfq4_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取各调度器的起始编号（etm共25K=25600,ftm共1920个）
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   p_spwfq_start_num  调度器起始编号结构体
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/26
+ ************************************************************/
+DPP_STATUS
+dpp_tm_crdt_wfqsp_get(DPP_DEV_T *dev,
+					  DPP_TM_CRDT_SPWFQ_START_NUM_T *p_spwfq_start_num)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CRDT_TH_SP_T etm_crdt_th_sp_t = { 0 };
+	DPP_ETM_CRDT_TH_WFQ_FQ_T etm_crdt_th_wfqfq_t = { 0 };
+	DPP_ETM_CRDT_TH_WFQ2_FQ2_T etm_crdt_th_wfqfq2_t = { 0 };
+	DPP_ETM_CRDT_TH_WFQ4_FQ4_T etm_crdt_th_wfqfq4_t = { 0 };
+	ZXIC_UINT32 th_sp_index = ETM_CRDT_TH_SPr;
+	ZXIC_UINT32 th_wfq_fq_index = ETM_CRDT_TH_WFQ_FQr;
+	ZXIC_UINT32 th_wfq_fq2_index = ETM_CRDT_TH_WFQ2_FQ2r;
+	ZXIC_UINT32 th_wfq_fq4_index = ETM_CRDT_TH_WFQ4_FQ4r;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_spwfq_start_num);
+
+	/* 读取调度器阈值配置：th_sp参数配置：th_sp=      sp_num/8 */
+	rc = dpp_reg_read(dev, th_sp_index, 0, 0, &etm_crdt_th_sp_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+	/* th_wfq阈值读取：th_wfq = (th_sp + wfq_num/8)       */
+	rc = dpp_reg_read(dev, th_wfq_fq_index, 0, 0, &etm_crdt_th_wfqfq_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+	/* th_wfq2阈值读取：th_wfq2 = (th_wfq +      wfq2_num/4) */
+	rc = dpp_reg_read(dev, th_wfq_fq2_index, 0, 0, &etm_crdt_th_wfqfq2_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+	/* th_wfq4阈值读取：th_wfq4 = (th_wfq2 +      wfq4_num/2) */
+	rc = dpp_reg_read(dev, th_wfq_fq4_index, 0, 0, &etm_crdt_th_wfqfq4_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	/* 各调度器起始编号计算 */
+	p_spwfq_start_num->start_num_fq = 0;
+	p_spwfq_start_num->start_num_fq2 = etm_crdt_th_wfqfq_t.th_fq * 8;
+	p_spwfq_start_num->start_num_fq4 = etm_crdt_th_wfqfq2_t.th_fq2 * 8;
+	p_spwfq_start_num->start_num_fq8 = etm_crdt_th_wfqfq4_t.th_fq4 * 8;
+	p_spwfq_start_num->start_num_sp = DPP_ETM_WFQSP_OFFSET;
+	p_spwfq_start_num->start_num_wfq =
+			(DPP_ETM_WFQSP_OFFSET + etm_crdt_th_sp_t.th_sp * 8);
+	p_spwfq_start_num->start_num_wfq2 =
+			(DPP_ETM_WFQSP_OFFSET + etm_crdt_th_wfqfq_t.th_wfq * 8);
+	p_spwfq_start_num->start_num_wfq4 =
+			(DPP_ETM_WFQSP_OFFSET + etm_crdt_th_wfqfq2_t.th_wfq2 * 8);
+	p_spwfq_start_num->start_num_wfq8 =
+			(DPP_ETM_WFQSP_OFFSET + etm_crdt_th_wfqfq4_t.th_wfq4 * 8);
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取调度器类型
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   se_id     调度器编号
+ * @param   item_num  调度器中包含的子调度器个数
+ * @param   sch_type_num  调度器类型编号
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/26
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_sch_type_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+									ZXIC_UINT32 *item_num,
+									ZXIC_UINT32 *sch_type_num)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_TM_CRDT_SPWFQ_START_NUM_T spwfq_start_num_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), item_num);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+
+	rc = dpp_tm_crdt_wfqsp_get(dev, &spwfq_start_num_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_wfqsp_get");
+
+	if (se_id < spwfq_start_num_t.start_num_fq2) {
+		*item_num = 1;
+		*sch_type_num = 5;
+	} else if (se_id < spwfq_start_num_t.start_num_fq4) {
+		*item_num = 2;
+		*sch_type_num = 6;
+	} else if (se_id < spwfq_start_num_t.start_num_fq8) {
+		*item_num = 4;
+		*sch_type_num = 7;
+	} else if (se_id < spwfq_start_num_t.start_num_sp) {
+		*item_num = 8;
+		*sch_type_num = 8;
+	} else if (se_id < spwfq_start_num_t.start_num_wfq) {
+		*item_num = 1;
+		*sch_type_num = 0;
+	} else if (se_id < spwfq_start_num_t.start_num_wfq2) {
+		*item_num = 1;
+		*sch_type_num = 1;
+	} else if (se_id < spwfq_start_num_t.start_num_wfq4) {
+		*item_num = 2;
+		*sch_type_num = 2;
+	} else if (se_id < spwfq_start_num_t.start_num_wfq8) {
+		*item_num = 4;
+		*sch_type_num = 3;
+	} else {
+		*item_num = 8;
+		*sch_type_num = 4;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取pp->dev挂接关系
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   pp_id   0~63
+ * @param   p_weight  0~127
+ * @param   p_sp_mapping   0~7
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/04/20
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_pp_para_get(DPP_DEV_T *dev, ZXIC_UINT32 pp_id,
+								   ZXIC_UINT32 *p_weight,
+								   ZXIC_UINT32 *p_sp_mapping)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	DPP_ETM_CRDT_PP_CFG_T pp_cfg_r = { 0 };
+	DPP_ETM_CRDT_PP_WEIGHT_T pp_weight_r = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pp_id, 0,
+										DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_weight);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_sp_mapping);
+
+	rc = dpp_reg_read(dev, ETM_CRDT_PP_WEIGHTr, 0, pp_id, &pp_weight_r);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+	*p_weight = pp_weight_r.pp_weight;
+
+	rc = dpp_reg_read(dev, ETM_CRDT_PP_CFGr, 0, pp_id, &pp_cfg_r);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+	*p_sp_mapping = pp_cfg_r.pp_cfg;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置se->pp->dev挂接关系
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   se_id   往端口挂接的调度器id
+ * @param   pp_id   [0-63]
+ * @param   weight  [1-511]
+ * @param   sp_mapping   [0~8]
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/3/4
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_se_pp_link_set(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+									  ZXIC_UINT32 pp_id, ZXIC_UINT32 weight,
+									  ZXIC_UINT32 sp_mapping)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 delay_time = 10;
+
+	DPP_ETM_CRDT_PP_CFG_T pp_cfg = { 0 };
+	DPP_ETM_CRDT_PP_WEIGHT_T pp_weight = { 0 };
+	DPP_ETM_CRDT_PP_CFG_T pp_cfg_r = { 0 };
+	DPP_ETM_CRDT_PP_WEIGHT_T pp_weight_r = { 0 };
+	DPP_TM_SCH_SE_PARA_T sch_se_para_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pp_id, 0,
+										DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), weight, 0,
+										DPP_TM_SCH_WEIGHT_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), sp_mapping,
+										DPP_TM_SCH_SP_0, DPP_TM_SCH_SP_8);
+
+	/* 参数赋值:仅需端口号 ,配置调度器到端口的挂接 */
+	sch_se_para_t.se_linkid = DPP_ETM_PORT_LINKID_BASE + pp_id;
+
+	rc = dpp_tm_crdt_se_link_wr(dev, se_id, &sch_se_para_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_se_link_wr");
+
+	/* 检测CRDT寄存器是否空闲 */
+	rc = dpp_tm_crdt_idle_check(dev);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_idle_check");
+
+	pp_weight.pp_weight = weight;
+	rc = dpp_reg_write(dev, ETM_CRDT_PP_WEIGHTr, 0, pp_id, &pp_weight);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	/* 写入后，重新读出来校验 */
+#if (ETM_WRITE_CHECK)
+	{
+		zxic_comm_delay(delay_time);
+		rc = dpp_reg_read(dev, ETM_CRDT_PP_WEIGHTr, 0, pp_id, &pp_weight_r);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+		if (pp_weight_r.pp_weight != pp_weight.pp_weight) {
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					DEV_ID(dev),
+					"dpp_tm_crdt_pp_para_set pp[0x%x] wt_pp_weight[0x%x] rd_pp_weight[0x%x]\n",
+					pp_id, pp_weight.pp_weight, pp_weight_r.pp_weight);
+			return DPP_ERR;
+		}
+	}
+#endif
+
+	/* 检测CRDT寄存器是否空闲 */
+	rc = dpp_tm_crdt_idle_check(dev);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_idle_check");
+
+	pp_cfg.pp_cfg = sp_mapping;
+	rc = dpp_reg_write(dev, ETM_CRDT_PP_CFGr, 0, pp_id, &pp_cfg);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	/* 写入后，重新读出来校验 */
+#if (ETM_WRITE_CHECK)
+	{
+		zxic_comm_delay(delay_time);
+		rc = dpp_reg_read(dev, ETM_CRDT_PP_CFGr, 0, pp_id, &pp_cfg_r);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+		if (pp_cfg_r.pp_cfg != pp_cfg.pp_cfg) {
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					DEV_ID(dev),
+					"dpp_tm_crdt_pp_para_set pp[0x%x] wt_pp_cfg[0x%x] rd_pp_cfg[0x%x]\n",
+					pp_id, pp_cfg.pp_cfg, pp_cfg_r.pp_cfg);
+			return DPP_ERR;
+		}
+	}
+#endif
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置flow级流队列的挂接关系(flow到上级调度器的挂接)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flow_id   流队列号
+ * @param   c_linkid  c桶要挂接到的上级调度器id
+ * @param   c_weight  c桶挂接到上级调度器的权重[1~511]
+ * @param   c_sp      c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
+ * @param   mode      挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可
+ * @param   e_linkid  e桶要挂接到的上级调度器id
+ * @param   e_weight  e桶挂接到上级调度器的权重[1~511]
+ * @param   e_sp      e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_flow_link_wr(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									DPP_TM_SCH_FLOW_PARA_T *p_flow_para)
+
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 flow_id_e = 0;
+	ZXIC_UINT32 c_linkid;
+	ZXIC_UINT32 c_weight;
+	ZXIC_UINT32 c_sp;
+	ZXIC_UINT32 mode;
+	ZXIC_UINT32 e_linkid;
+	ZXIC_UINT32 e_weight;
+	ZXIC_UINT32 e_sp;
+	DPP_ETM_CRDT_FLOWQUE_PARA_TBL_T etm_crdt_flow_para_tbl_t = { 0 };
+
+	/* 取配置参数 */
+	c_linkid = p_flow_para->c_linkid;
+	c_weight = p_flow_para->c_weight;
+	c_sp = p_flow_para->c_sp;
+	mode = p_flow_para->mode;
+	e_linkid = p_flow_para->e_linkid;
+	e_weight = p_flow_para->e_weight;
+	e_sp = p_flow_para->e_sp;
+	/* 参数校验 */
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_flow_para);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), c_weight, 0,
+										DPP_TM_SCH_WEIGHT_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), e_weight, 0,
+										DPP_TM_SCH_WEIGHT_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), c_sp, 0,
+										DPP_TM_SCH_SP_NUM);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), e_sp, 0,
+										DPP_TM_SCH_SP_NUM);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0,
+										DPP_ETM_Q_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), c_linkid, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), e_linkid, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+
+	/* 开始流级挂接配置 */
+
+	if (mode == 1) {
+		flow_id_e = (flow_id + 0x2400);
+	}
+
+	/* c桶挂接配置 */
+	etm_crdt_flow_para_tbl_t.flowque_link = c_linkid;
+	etm_crdt_flow_para_tbl_t.flowque_w = c_weight;
+	etm_crdt_flow_para_tbl_t.flowque_pri = c_sp;
+
+	rc = dpp_reg_write(dev, ETM_CRDT_FLOWQUE_PARA_TBLr, 0, flow_id,
+					   &etm_crdt_flow_para_tbl_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	zxic_comm_delay(5);
+
+	/* mode-1 需要配置双桶挂接 */
+	if (mode == 1) {
+		/* e桶挂接配置 */
+		etm_crdt_flow_para_tbl_t.flowque_link = e_linkid;
+		etm_crdt_flow_para_tbl_t.flowque_w = e_weight;
+		etm_crdt_flow_para_tbl_t.flowque_pri = e_sp;
+
+		rc = dpp_reg_write(dev, ETM_CRDT_FLOWQUE_PARA_TBLr, 0, flow_id_e,
+						   &etm_crdt_flow_para_tbl_t);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+	}
+
+	zxic_comm_delay(5);
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置flow级流队列的挂接关系(flow到上级调度器的挂接)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flow_id   流队列号
+ * @param   c_linkid  c桶要挂接到的上级调度器id
+ * @param   c_weight  c桶挂接到上级调度器的权重[1~511]
+ * @param   c_sp      c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
+ * @param   mode      挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可
+ * @param   e_linkid  e桶要挂接到的上级调度器id
+ * @param   e_weight  e桶挂接到上级调度器的权重[1~511]
+ * @param   e_sp      e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_flow_link_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									 ZXIC_UINT32 c_linkid, ZXIC_UINT32 c_weight,
+									 ZXIC_UINT32 c_sp, ZXIC_UINT32 mode,
+									 ZXIC_UINT32 e_linkid, ZXIC_UINT32 e_weight,
+									 ZXIC_UINT32 e_sp)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_TM_SCH_FLOW_PARA_T sch_flow_para_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+	/* 参数赋值 */
+	sch_flow_para_t.c_linkid = c_linkid;
+	sch_flow_para_t.c_weight = c_weight;
+	sch_flow_para_t.c_sp = c_sp;
+	sch_flow_para_t.mode = mode;
+	sch_flow_para_t.e_linkid = e_linkid;
+	sch_flow_para_t.e_weight = e_weight;
+	sch_flow_para_t.e_sp = e_sp;
+
+	rc = dpp_tm_crdt_flow_link_wr(dev, flow_id, &sch_flow_para_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_crdt_flow_link_wr");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 批量配置flow级流队列的挂接关系
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flow_id_s 起始流队列号
+ * @param   flow_id_e 终止流队列号
+ * @param   c_linkid  c桶要挂接到的上级调度器id
+ * @param   c_weight  c桶挂接到上级调度器的权重[1~511]
+ * @param   c_sp      c桶挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
+ * @param   mode      挂接模式：0-单桶 1-双桶。配置单桶时无需关注后续参数，配0即可
+ * @param   e_linkid  e桶要挂接到的上级调度器id
+ * @param   e_weight  e桶挂接到上级调度器的权重[1~511]
+ * @param   e_sp      e桶挂接到上级调度器的sp优先级，有效值[0-8],共9级，优先级依次降低
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS
+dpp_tm_crdt_flow_link_more_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id_s,
+							   ZXIC_UINT32 flow_id_e, ZXIC_UINT32 c_linkid,
+							   ZXIC_UINT32 c_weight, ZXIC_UINT32 c_sp,
+							   ZXIC_UINT32 mode, ZXIC_UINT32 e_linkid,
+							   ZXIC_UINT32 e_weight, ZXIC_UINT32 e_sp)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 flow_id = 0;
+	DPP_TM_SCH_FLOW_PARA_T sch_flow_para_t = { 0 };
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	if (flow_id_s > flow_id_e) {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+								  "Bad parameters!  flow_id_s > flow_id_e !\n");
+		return DPP_ERR;
+	}
+
+	/* 参数赋值 */
+	sch_flow_para_t.c_linkid = c_linkid;
+	sch_flow_para_t.c_weight = c_weight;
+	sch_flow_para_t.c_sp = c_sp;
+	sch_flow_para_t.mode = mode;
+	sch_flow_para_t.e_linkid = e_linkid;
+	sch_flow_para_t.e_weight = e_weight;
+	sch_flow_para_t.e_sp = e_sp;
+
+	for (flow_id = flow_id_s; flow_id <= flow_id_e; flow_id++) {
+		rc = dpp_tm_crdt_flow_link_wr(dev, flow_id, &sch_flow_para_t);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_crdt_flow_link_wr");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置调度器层次化QOS的挂接关系:非优先级传递
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   se_id      本级调度器id
+ *                     对于FQX/WFQX必须是调度单元中首个调度器id
+ * @param   se_linkid  要挂接到的上级调度器id
+ * @param   se_weight  挂接到上级调度器的权重[1~511]
+ * @param   se_sp      挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
+ * @param   se_insw    优先级传递使能：0-关 1-开。该参数不传递直接配0
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_se_link_wr(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+								  DPP_TM_SCH_SE_PARA_T *p_sch_se_para)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 se_linkid = 0;
+	ZXIC_UINT32 se_weight = 0;
+	ZXIC_UINT32 se_sp = 0;
+	ZXIC_UINT32 se_insw = 0; /* 优先级传递关闭 */
+	ZXIC_UINT32 item_num = 0; /* 调度单元中调度器的个数 */
+	ZXIC_UINT32 sch_type_num = 0;
+	ZXIC_UINT32 i = 0;
+	DPP_ETM_CRDT_SE_PARA_TBL_T etm_crdt_se_para_tbl_t = { 0 };
+
+	/* 取配置参数 */
+	se_linkid = p_sch_se_para->se_linkid;
+	se_weight = p_sch_se_para->se_weight;
+	se_sp = p_sch_se_para->se_sp;
+
+	/* 参数校验 */
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight, 0,
+										DPP_TM_SCH_WEIGHT_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_sp, 0,
+										DPP_TM_SCH_SP_NUM);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_insw, 0, 0);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+
+	if (se_linkid > DPP_ETM_FQSPWFQ_NUM) {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_linkid,
+											DPP_TM_PP_LINKID_PORT0,
+											DPP_TM_PP_LINKID_PORT63);
+	} else {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_linkid, 0,
+											DPP_ETM_FQSPWFQ_NUM - 1);
+	}
+
+	/* 开始调度器挂接配置 */
+
+	/* 先区分调度器类型：sp/fq/wfq调度器挂接方式相同，wfqx/fqx=2/4/8是另一种挂接方式 */
+	rc = dpp_tm_crdt_sch_type_get(dev, se_id, &item_num, &sch_type_num);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_crdt_sch_type_get");
+
+	/* 非优先级传递挂接:各调度器参数须相同 */
+	etm_crdt_se_para_tbl_t.se_link = se_linkid;
+	etm_crdt_se_para_tbl_t.se_w = se_weight;
+	etm_crdt_se_para_tbl_t.se_pri = se_sp;
+	etm_crdt_se_para_tbl_t.se_insw = se_insw;
+	etm_crdt_se_para_tbl_t.cp_token_en = 1;
+
+	for (i = 0; i < item_num; i++) {
+		rc = dpp_reg_write(dev, ETM_CRDT_SE_PARA_TBLr, 0, se_id + i,
+						   &etm_crdt_se_para_tbl_t);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置调度器层次化QOS的挂接关系:非优先级传递
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   se_id      本级调度器id
+ *                     对于FQX/WFQX必须是调度单元中首个调度器id
+ * @param   se_linkid  要挂接到的上级调度器id
+ * @param   se_weight  挂接到上级调度器的权重[1~511]
+ * @param   se_sp      挂接到上级调度器的sp优先级,有效值[0-8],共9级，优先级依次降低
+ * @param   se_insw    优先级传递使能：0-关 1-开. 该参数不传递直接配0
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_se_link_set(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+								   ZXIC_UINT32 se_linkid, ZXIC_UINT32 se_weight,
+								   ZXIC_UINT32 se_sp)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_TM_SCH_SE_PARA_T sch_se_para_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+	/* 参数赋值 */
+	sch_se_para_t.se_linkid = se_linkid;
+	sch_se_para_t.se_weight = se_weight;
+	sch_se_para_t.se_sp = se_sp;
+
+	rc = dpp_tm_crdt_se_link_wr(dev, se_id, &sch_se_para_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_tm_crdt_se_link_wr");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置调度器层次化QOS的挂接关系:优先级传递
+ * @param   dev_id       设备编号
+ * @param   tm_type      0-ETM,1-FTM
+ * @param   se_id        本级调度器id
+ * @param   se_linkid    要挂接到的上级调度器id
+ * @param   se_sp        挂接到上级调度器的sp优先级,有效值[0-3],最多4级，优先级按调度单元分配，
+ *                       每个调度单元内部调度器优先级相同！
+ * @param   se_weight0-7 WFQ8中各调度器权重值[1~511]，若是WFQ2/4 只取前面对应值，后面无效
+ * @param   se_insw      优先级传递使能：0-关 1-开. 该参数不传递直接配1
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS
+dpp_tm_crdt_se_link_insw_wr(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+							DPP_TM_SCH_SE_PARA_INSW_T *p_sch_se_para_insw)
+{
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 se_linkid; /**  要挂接到的上级调度器id */
+	ZXIC_UINT32
+	se_sp; /** 挂接到上级调度器的sp优先级,有效值[0-3],共4级，优先级依次降低,优先级按调度单元分配 */
+	ZXIC_UINT32 se_weight[8] = {
+		0
+	}; /** WFQ8中各调度器权重值[1~511]，若是WFQ2/4 只取前面对应值，后面无效 */
+	ZXIC_UINT32 se_insw = 1; /* 优先级传递开启 */
+	ZXIC_UINT32 item_num = 1; /* 调度单元中调度器的个数 */
+	ZXIC_UINT32 sch_type_num = 0;
+	ZXIC_UINT32 item_num_link = 0; /* 上级调度单元中调度器的个数 */
+	ZXIC_UINT32 sch_type_num_link = 0;
+	ZXIC_UINT32 i = 0;
+	DPP_ETM_CRDT_SE_PARA_TBL_T etm_crdt_se_para_tbl_t = { 0 };
+
+	/* 取配置参数 */
+	se_linkid = p_sch_se_para_insw->se_linkid;
+	se_sp = p_sch_se_para_insw->se_sp;
+	se_weight[0] = p_sch_se_para_insw->se_weight[0];
+	se_weight[1] = p_sch_se_para_insw->se_weight[1];
+	se_weight[2] = p_sch_se_para_insw->se_weight[2];
+	se_weight[3] = p_sch_se_para_insw->se_weight[3];
+	se_weight[4] = p_sch_se_para_insw->se_weight[4];
+	se_weight[5] = p_sch_se_para_insw->se_weight[5];
+	se_weight[6] = p_sch_se_para_insw->se_weight[6];
+	se_weight[7] = p_sch_se_para_insw->se_weight[7];
+
+	/* 参数校验 */
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_sp, 0,
+										DPP_TM_SCH_SP_NUM - 5);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_insw, 1, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[0], 0,
+										DPP_TM_SCH_WEIGHT_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[1], 0,
+										DPP_TM_SCH_WEIGHT_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[2], 0,
+										DPP_TM_SCH_WEIGHT_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[3], 0,
+										DPP_TM_SCH_WEIGHT_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[4], 0,
+										DPP_TM_SCH_WEIGHT_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[5], 0,
+										DPP_TM_SCH_WEIGHT_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[6], 0,
+										DPP_TM_SCH_WEIGHT_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight[7], 0,
+										DPP_TM_SCH_WEIGHT_MAX);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_linkid, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+
+	/* 开始调度器挂接配置 */
+
+	/* 先区分调度器类型：sp/fq/wfq调度器挂接方式相同，wfqx/fqx=2/4/8是另一种挂接方式 */
+	rc = dpp_tm_crdt_sch_type_get(dev, se_id, &item_num, &sch_type_num);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_crdt_sch_type_get");
+	rc = dpp_tm_crdt_sch_type_get(dev, se_linkid, &item_num_link,
+								  &sch_type_num_link);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_crdt_sch_type_get");
+
+	/* 优先级传递挂接合法性检查:下级传入调度器需是首编号，且下级<=上级 */
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), item_num, 1, 8);
+
+	if (se_id % item_num != 0 || item_num > item_num_link) {
+		ZXIC_COMM_TRACE_DEV_ERROR(
+				DEV_ID(dev),
+				"dpp_tm_crdt_se_link_insw_wr： NOT CORRECT,bad parameters!\n");
+		return DPP_ERR;
+	}
+
+	/* 优先级传递挂接:各调度器挂接的se_linkid依次递增1,需相邻不能错开
+	se_weight不限，取值[1-511]
+	se_sp:根据下级往上级挂接情况，取值[0-3]，调度单元内部须相同
+	se_insw 写死为1 */
+	etm_crdt_se_para_tbl_t.se_pri = se_sp;
+	etm_crdt_se_para_tbl_t.se_insw = se_insw;
+	etm_crdt_se_para_tbl_t.cp_token_en = 1;
+
+	for (i = 0; i < item_num; i++) {
+		etm_crdt_se_para_tbl_t.se_link = (se_linkid + i);
+		etm_crdt_se_para_tbl_t.se_w = se_weight[i];
+
+		rc = dpp_reg_write(dev, ETM_CRDT_SE_PARA_TBLr, 0, se_id + i,
+						   &etm_crdt_se_para_tbl_t);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置调度器层次化QOS的挂接关系:优先级传递
+ * @param   dev_id       设备编号
+ * @param   tm_type      0-ETM,1-FTM
+ * @param   se_id        本级调度器id
+ * @param   se_linkid    要挂接到的上级调度器id
+ * @param   se_weight    WFQ2/4/8中各调度器权重值[1~511]，取相等的值
+ * @param   se_sp        挂接到上级调度器的sp优先级,有效值[0-7],共8级，优先级依次降低
+ * @param   se_insw      优先级传递使能：0-关 1-开. 该参数不传递直接配1
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_se_link_insw_set(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+										ZXIC_UINT32 se_linkid,
+										ZXIC_UINT32 se_weight,
+										ZXIC_UINT32 se_sp)
+{
+	ZXIC_UINT32 rc = DPP_OK;
+	DPP_TM_SCH_SE_PARA_INSW_T sch_se_para_insw_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+	/* 参数赋值 */
+	sch_se_para_insw_t.se_linkid = se_linkid;
+	sch_se_para_insw_t.se_sp = se_sp;
+	sch_se_para_insw_t.se_weight[0] = se_weight;
+	sch_se_para_insw_t.se_weight[1] = se_weight;
+	sch_se_para_insw_t.se_weight[2] = se_weight;
+	sch_se_para_insw_t.se_weight[3] = se_weight;
+	sch_se_para_insw_t.se_weight[4] = se_weight;
+	sch_se_para_insw_t.se_weight[5] = se_weight;
+	sch_se_para_insw_t.se_weight[6] = se_weight;
+	sch_se_para_insw_t.se_weight[7] = se_weight;
+
+	rc = dpp_tm_crdt_se_link_insw_wr(dev, se_id, &sch_se_para_insw_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_crdt_se_link_insw_wr");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置调度器层次化QOS的挂接关系:优先级传递,单个调度器挂接
+ * @param   dev_id       设备编号
+ * @param   tm_type      0-ETM,1-FTM
+ * @param   se_id        本级调度器id
+ * @param   se_linkid    要挂接到的上级调度器id
+ * @param   se_weight    WFQ8中对应调度器权重值[1~511]
+ * @param   se_sp        挂接到上级调度器的sp优先级,有效值[0-7],共8级，优先级依次降低
+ * @param   se_insw      优先级传递使能：0-关 1-开. 该参数不传递直接配1
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_se_link_insw_single_set(DPP_DEV_T *dev,
+											   ZXIC_UINT32 se_id,
+											   ZXIC_UINT32 se_linkid,
+											   ZXIC_UINT32 se_weight,
+											   ZXIC_UINT32 se_sp)
+{
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 se_insw = 1; /* 优先级传递开启 */
+	DPP_ETM_CRDT_SE_PARA_TBL_T etm_crdt_se_para_tbl_t = { 0 };
+
+	/* 参数校验 */
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_sp, 0,
+										DPP_TM_SCH_SP_NUM - 5);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_insw, 1, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_weight, 0,
+										DPP_TM_SCH_WEIGHT_MAX);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_linkid, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+
+	/* 开始调度器挂接配置 */
+
+	/* 优先级传递挂接:各调度器挂接的se_linkid依次递增1,需相邻不能错开
+	se_weight不限，取值[1-511]
+	se_sp:根据下级往上级挂接情况，取值[0-3]，调度单元内部须相同
+	se_insw 写死为1 */
+	etm_crdt_se_para_tbl_t.se_pri = se_sp;
+	etm_crdt_se_para_tbl_t.se_insw = se_insw;
+	etm_crdt_se_para_tbl_t.cp_token_en = 1;
+	etm_crdt_se_para_tbl_t.se_link = se_linkid;
+	etm_crdt_se_para_tbl_t.se_w = se_weight;
+
+	rc = dpp_reg_write(dev, ETM_CRDT_SE_PARA_TBLr, 0, se_id,
+					   &etm_crdt_se_para_tbl_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取调度器挂接配置参数
+ * @param   dev_id      设备编号
+ * @param   tm_type     0-ETM,1-FTM
+ * @param   se_id       调度器编号
+ * @param   p_se_para_tbl  调度器参数
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_se_para_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+								   DPP_ETM_CRDT_SE_PARA_TBL_T *p_se_para_tbl)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	/* 参数校验 */
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_para_tbl);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+
+	rc = dpp_reg_read(dev, ETM_CRDT_SE_PARA_TBLr, 0, se_id, p_se_para_tbl);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取流队列入链状态
+ * @param   dev_id      设备编号
+ * @param   tm_type     0-ETM,1-FTM
+ * @param   flow_id     流队列号
+ * @param   link_state  0-未入链     1-在调度器链表中
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_flow_link_state_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+										   ZXIC_UINT32 *link_state)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CRDT_FLOWQUE_INS_TBL_T crdt_flow_ins_tbl_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), link_state);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0,
+										DPP_ETM_CRDT_NUM);
+
+	rc = dpp_reg_read(dev, ETM_CRDT_FLOWQUE_INS_TBLr, 0, flow_id,
+					  &crdt_flow_ins_tbl_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*link_state = crdt_flow_ins_tbl_t.flowque_ins;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取调度器入链状态
+ * @param   dev_id      设备编号
+ * @param   tm_type     0-ETM,1-FTM
+ * @param   se_id       调度器编号
+ * @param   link_state  0-未入链     1-在调度器链表中
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_se_link_state_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+										 ZXIC_UINT32 *link_state)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CRDT_SE_INS_TBL_T crdt_se_ins_tbl_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), link_state);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+
+	rc = dpp_reg_read(dev, ETM_CRDT_SE_INS_TBLr, 0, se_id, &crdt_se_ins_tbl_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*link_state = crdt_se_ins_tbl_t.se_ins_flag;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 判断crdt流删除命令是否空闲
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_del_cmd_idle(DPP_DEV_T *dev)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 read_times = 30;
+	DPP_ETM_CRDT_FLOW_DEL_CMD_T crdt_del_cmd_busy = { 0 };
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	do {
+		rc = dpp_reg_read(dev, ETM_CRDT_FLOW_DEL_CMDr, 0, 0,
+						  &crdt_del_cmd_busy);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+		read_times--;
+		zxic_comm_delay(5);
+	} while ((0 != (crdt_del_cmd_busy.flow_del_busy)) && (read_times > 0));
+
+	if (0 == read_times) {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "CRDT Del command busy!\n");
+		return DPP_ERR;
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 删除流/调度器挂接关系(调度器编号非从0开始，需要偏移)
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   id        要删除的流号或调度器id
+ *          ETM范围:0--0xABFF; FTM范围:0-0x177F
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_del_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 c_sta = 0;
+	ZXIC_UINT32 e_sta = 0;
+	ZXIC_UINT32 flow_e = 0;
+	ZXIC_UINT32 link_state = 0; /*流或调度器入链状态*/
+	ZXIC_UINT32 read_times = 300;
+	ZXIC_UINT32 crdt_del_cmd_reg_index = 0;
+	DPP_ETM_CRDT_FLOW_DEL_CMD_T crdt_del_cmd_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+										DPP_ETM_SCH_DEL_NUM);
+	flow_e = DPP_ETM_Q_NUM;
+
+	/* 循环判断入链状态是否为1 */
+	do {
+		/* 判断当前流或调度器入链状态：非入链情况才能删除挂接 */
+		if (id <= DPP_ETM_CRDT_NUM) {
+			/* 流入链状态 */
+			rc = dpp_tm_crdt_flow_link_state_get(dev, id, &c_sta);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+											 "dpp_tm_crdt_flow_link_state_get");
+
+			rc = dpp_tm_crdt_flow_link_state_get(dev, id + DPP_ETM_Q_NUM,
+												 &e_sta);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+											 "dpp_tm_crdt_flow_link_state_get");
+
+			link_state = c_sta || e_sta;
+		} else {
+			/*调度器入链状态*/
+			rc = dpp_tm_crdt_se_link_state_get(dev, id - DPP_ETM_SHAP_SEID_BASE,
+											   &link_state);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+											 "dpp_tm_crdt_se_link_state_get");
+		}
+
+		if (0 == link_state) {
+			break;
+		}
+		read_times--;
+		zxic_comm_delay(1);
+	} while (read_times > 0);
+
+	if (read_times == 0) {
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(id, flow_e);
+		ZXIC_COMM_TRACE_ERROR(
+				"tm_type:%d id: 0x%08x ins_flag is always 1 (Maybe it's because cir equal zero) !!!\n",
+				id);
+		/*此时要 继续往下走，执行强删！如果不删除队列没释放下次直接覆写问题更严重。zhaoyan*/
+	}
+
+	/*删挂接命令是否空闲*/
+	rc = dpp_tm_crdt_del_cmd_idle(dev);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_crdt_del_cmd_idle");
+
+	/*进行流或调度器删除操作*/
+	crdt_del_cmd_reg_index = ETM_CRDT_FLOW_DEL_CMDr;
+	crdt_del_cmd_t.flow_alt_cmd = 1;
+	crdt_del_cmd_t.flow_alt_ind = id;
+
+	/* 流删除：如果删除c桶，需要同时删除e桶 */
+	if (id < DPP_ETM_Q_NUM) {
+		rc = dpp_reg_write(dev, crdt_del_cmd_reg_index, 0, 0, &crdt_del_cmd_t);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+		/*删挂e桶：判断命令是否空闲*/
+		rc = dpp_tm_crdt_del_cmd_idle(dev);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_crdt_del_cmd_idle");
+		crdt_del_cmd_t.flow_alt_ind = (id + DPP_ETM_Q_NUM);
+		rc = dpp_reg_write(dev, crdt_del_cmd_reg_index, 0, 0, &crdt_del_cmd_t);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+	} else {
+		rc = dpp_reg_write(dev, crdt_del_cmd_reg_index, 0, 0, &crdt_del_cmd_t);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 删除调度器挂接关系(调度器编号从0开始)：对外API
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   se_id_s   要删除的起始调度器id
+ * @param   se_id_e   要删除的终止调度器id
+ *          ETM范围:0--0x63FF; FTM范围:0-0x77F
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_del_se_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id_s,
+									   ZXIC_UINT32 id_e)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 se_id_offset = 0;
+	ZXIC_UINT32 id = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id_s, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id_e, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+	se_id_offset = DPP_ETM_SHAP_SEID_BASE;
+
+	if (id_s > id_e) {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+								  "Bad parameters!  id_s > id_e!\n");
+		return DPP_ERR;
+	}
+
+	for (id = id_s; id <= id_e; id++) {
+		ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), id,
+														 se_id_offset);
+		rc = dpp_tm_crdt_del_link_set(dev, id + se_id_offset);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_crdt_del_link_set");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 删除流挂接关系：对外API
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   id_s      要删除的流号或调度器起始id
+ * @param   id_e      要删除的流号或调度器终止id
+ *          ETM范围:0--0x47FF; FTM范围:0-0xFFF
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/02/27
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_del_flow_link_set(DPP_DEV_T *dev, ZXIC_UINT32 id_s,
+										 ZXIC_UINT32 id_e)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 id = 0;
+	ZXIC_UINT32 q_td_th = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id_s, 0, DPP_ETM_CRDT_NUM);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id_e, 0, DPP_ETM_CRDT_NUM);
+
+	if (id_s > id_e) {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+								  "Bad parameters!  id_s > id_e !\n");
+		return DPP_ERR;
+	}
+
+	for (id = id_s; id <= id_e; id++) {
+		rc = dpp_tm_cgavd_td_th_get(dev, QUEUE_LEVEL, id, &q_td_th);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_cgavd_td_th_get");
+
+		if (q_td_th != 0) {
+			ZXIC_COMM_TRACE_DEV_ERROR(
+					DEV_ID(dev),
+					"queue TD_TH is not equal 0 !  q_td_th != 0 !\n");
+			return DPP_ERR;
+		}
+	}
+
+	for (id = id_s; id <= id_e; id++) {
+		rc = dpp_tm_crdt_del_link_set(dev, id);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_crdt_del_link_set");
+	}
+
+	return DPP_OK;
+}
+/***********************************************************/
+/** 配置端口拥塞令牌桶使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   port_id   端口号：0~63
+ * @param   port_en   端口拥塞令牌桶使能，1表示不使用拥塞令牌桶的授权，0表示可以使用拥塞令牌桶授权
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  taq      @date  2015/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_port_congest_en_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+										   ZXIC_UINT32 port_en)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 value = 0;
+	DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0_T disable_31_0 = { 0 };
+	DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32_T disable_63_32 = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0,
+										DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_en, 0, 1);
+
+	if (port_id <= 31) {
+		/* port_id:[0-31] */
+		rc = dpp_reg_read(dev, ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0r, 0, 0,
+						  &disable_31_0);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+		value = disable_31_0.congest_token_disable_31_0;
+
+		if (port_en == 0) {
+			value = value & (~(1u << port_id));
+		} else {
+			value = value | (1u << port_id);
+		}
+
+		disable_31_0.congest_token_disable_31_0 = value;
+
+		rc = dpp_reg_write(dev, ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0r, 0, 0,
+						   &disable_31_0);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+	} else {
+		/* port_id:[32-63] */
+		rc = dpp_reg_read(dev, ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32r, 0, 0,
+						  &disable_63_32);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+		value = disable_63_32.congest_token_disable_63_32;
+
+		if (port_en == 0) {
+			value = value & (~(1u << (port_id - 32)));
+		} else {
+			value = value | (1u << (port_id - 32));
+		}
+
+		disable_63_32.congest_token_disable_63_32 = value;
+
+		rc = dpp_reg_write(dev, ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32r, 0, 0,
+						   &disable_63_32);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获得端口拥塞令牌桶使能
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   port_id   端口号：0~120
+ * @param   p_port_en   端口拥塞令牌桶使能，1表示不使用拥塞令牌桶的授权，0表示可以使用拥塞令牌桶授权
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  djf      @date  2015/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_port_congest_en_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+										   ZXIC_UINT32 *p_port_en)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 value = 0;
+	DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0_T disable_31_0 = { 0 };
+	DPP_ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32_T disable_63_32 = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0,
+										DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_port_en);
+
+	if (port_id <= 31) {
+		/* port_id:[0-31] */
+		rc = dpp_reg_read(dev, ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0r, 0, 0,
+						  &disable_31_0);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+		value = disable_31_0.congest_token_disable_31_0;
+
+		*p_port_en = 1 & (value >> port_id);
+	} else {
+		/* port_id:[32-63] */
+		rc = dpp_reg_read(dev, ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32r, 0, 0,
+						  &disable_63_32);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+		value = disable_63_32.congest_token_disable_63_32;
+
+		*p_port_en = 1 & (value >> (port_id - 32));
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** CRDT 模块 读写是否超时检查:只有端口sp优先级的配置需检测cfg_state的状态
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ *
+ * @return  DPP_OK-空闲，DPP_ERR-忙
+ * @remark  无
+ * @see
+ * @author  szq      @date  2015/05/26
+ ************************************************************/
+DPP_STATUS dpp_tm_crdt_idle_check(DPP_DEV_T *dev)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 read_times = 30;
+	DPP_ETM_CRDT_CFG_STATE_T is_idle_flag = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+
+	do {
+		rc = dpp_reg_read(dev, ETM_CRDT_CFG_STATEr, 0, 0, &is_idle_flag);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+		read_times--;
+		zxic_comm_delay(5);
+
+	} while ((1 == is_idle_flag.cfg_state) && (read_times > 0));
+
+	if (0 == read_times) {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev), "crdt rw time out\n");
+		return DPP_ERR;
+	}
+
+	return DPP_OK;
+}
+#endif
+
+#if ZXIC_REAL("TM_SHAPE")
+/***********************************************************/
+/** 配置流队列双桶整形使能及模式
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   db_en     双桶整形使能
+ * @param   mode      0:c+e模式，1:c+p模式
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_flow_db_en_set(DPP_DEV_T *dev, ZXIC_UINT32 db_en,
+									   ZXIC_UINT32 mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CRDT_DB_TOKEN_T tm_shape_db_en_t = { 0 };
+	DPP_ETM_SHAP_TOKEN_MODE_SWITCH_T tm_shap_db_mode_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), db_en, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1);
+
+	tm_shape_db_en_t.db_token = db_en;
+	tm_shap_db_mode_t.token_mode_switch = mode;
+
+	rc = dpp_reg_write(dev, ETM_CRDT_DB_TOKENr, 0, 0, &tm_shape_db_en_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	rc = dpp_reg_write(dev, ETM_SHAP_TOKEN_MODE_SWITCHr, 0, 0,
+					   &tm_shap_db_mode_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取流队列双桶整形使能及模式
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   db_en     双桶整形使能
+ * @param   mode      0:c+e模式，1:c+p模式
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_flow_db_en_get(DPP_DEV_T *dev, ZXIC_UINT32 *db_en,
+									   ZXIC_UINT32 *mode)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_CRDT_DB_TOKEN_T tm_shape_db_en_t = { 0 };
+	DPP_ETM_SHAP_TOKEN_MODE_SWITCH_T tm_shap_db_mode_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), db_en);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), mode);
+
+	rc = dpp_reg_read(dev, ETM_CRDT_DB_TOKENr, 0, 0, &tm_shape_db_en_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	rc = dpp_reg_read(dev, ETM_SHAP_TOKEN_MODE_SWITCHr, 0, 0,
+					  &tm_shap_db_mode_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*db_en = tm_shape_db_en_t.db_token;
+	*mode = tm_shap_db_mode_t.token_mode_switch;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取桶深最小单位配置:共8档：0-7
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   token_grain    3’d0：最小单位为128K
+ *                         3’d1：最小单位为64k
+ *                         3’d2：最小单位为32k
+ *                         3’d3：最小单位为16k
+ *                         3’d4：最小单位为8k
+ *                         3’d5：最小单位为4k
+ *                         3’d6：最小单位为2k
+ *                         3’d7：最小单位为1k
+ *           默认为0，即128K
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_token_grain_get(DPP_DEV_T *dev,
+										ZXIC_UINT32 *token_grain)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_SHAP_TOKEN_GRAIN_T tm_shape_token_grain_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), token_grain);
+
+	rc = dpp_reg_read(dev, ETM_SHAP_TOKEN_GRAINr, 0, 0,
+					  &tm_shape_token_grain_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*token_grain = tm_shape_token_grain_t.token_grain;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置流或调度器映射到整形参数表的某个ID
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   id        流或调度器编号ETM:0-ABFF,FTM:0-177F
+ * @param   profile_id    整形参数表id索引:[0-127]
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_map_table_set(DPP_DEV_T *dev, ZXIC_UINT32 id,
+									  ZXIC_UINT32 profile_id)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_SHAP_SHAP_BUCKET_MAP_TBL_T tm_shape_map_tbl_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), profile_id, 0, 127);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+										DPP_ETM_SCH_DEL_NUM);
+
+	tm_shape_map_tbl_t.shap_map = profile_id;
+
+	rc = dpp_reg_write(dev, ETM_SHAP_SHAP_BUCKET_MAP_TBLr, 0, id,
+					   &tm_shape_map_tbl_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取流或调度器映射到整形参数表的配置ID
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   id        流或调度器编号ETM:0-ABFF,FTM:0-177F
+ * @param   profile_id  整形参数表:[0-127]
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_map_table_get(DPP_DEV_T *dev, ZXIC_UINT32 id,
+									  ZXIC_UINT32 *profile_id)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_ETM_SHAP_SHAP_BUCKET_MAP_TBL_T tm_shape_map_tbl_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), profile_id);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), id, 0,
+										DPP_ETM_SCH_DEL_NUM);
+
+	rc = dpp_reg_read(dev, ETM_SHAP_SHAP_BUCKET_MAP_TBLr, 0, id,
+					  &tm_shape_map_tbl_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	*profile_id = tm_shape_map_tbl_t.shap_map;
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 根据流或调度器id查找对应配置表中的模板id
+	找到直接进行整形配置并返回1；未找到返回0
+* @param   dev_id    设备编号
+* @param   tm_type   0-ETM,1-FTM
+* @param   id        流或调度器编号 ETM:0-ABFF,FTM:0-AFF
+* @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
+* @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
+* @return  找到：1，未找到：0
+* @remark  无
+* @see
+* @author  whuashan      @date  2019/03/11
+************************************************************/
+DPP_STATUS dpp_tm_shape_find_map_id(DPP_DEV_T *dev, ZXIC_UINT32 id,
+									ZXIC_UINT32 cir, ZXIC_UINT32 cbs)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 table_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 2);
+
+	/* 根据id计算归属哪张表：每2K对应一个128项表 */
+	table_id = id / 2048;
+
+	for (i = 1; i < 128; i++) {
+		if (g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_cir ==
+					cir &&
+			g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_cbs ==
+					cbs) {
+			rc = dpp_tm_shape_map_table_set(dev, id, i);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+											 "dpp_tm_shape_map_table_set");
+			g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_num++;
+
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+/***********************************************************/
+/** 配置流级整形参数
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flow_id   流队列号 ETM:0-9215,FTM:0-2047
+ * @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
+ * @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
+ *                     注：cbs=0 表示关闭整形,即不限速
+ * @param   db_en     双桶整形使能，0-单桶，1-双桶
+ * @param   eir       eir速率，单位Kb，范围同cir
+ * @param   ebs       ebs桶深，单位KB，范围同cbs
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_flow_para_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									  ZXIC_UINT32 cir, ZXIC_UINT32 cbs,
+									  ZXIC_UINT32 db_en, ZXIC_UINT32 eir,
+									  ZXIC_UINT32 ebs)
+{
+	DPP_STATUS rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+
+	rc = dpp_etm_shape_flow_para_set(dev, flow_id, cir, cbs, db_en, eir, ebs);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_etm_shape_flow_para_set");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取流级整形参数
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flow_id   流队列号 ETM:0-9215,FTM:0-2047
+ * @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
+ * @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
+ *                    注：cbs=0 表示关闭整形,即不限速
+ * @param   mode_e    整形模式，0-获取c桶参数，1-获取对应e桶参数
+ * @param   p_para_id   整形模板索引：ETM=[0-AFF]，FTM=[0-17F]
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_flow_para_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									  ZXIC_UINT32 mode, ZXIC_UINT32 *p_para_id,
+									  DPP_TM_SHAPE_PARA_TABLE *p_flow_para_tbl)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 flow_id_e = 0;
+	ZXIC_UINT32 table_id = 0;
+	ZXIC_UINT32 profile_id = 0;
+	ZXIC_UINT32 bucket_para_n = 0;
+	ZXIC_UINT32 bucket_depth = 0; /* 实际写入寄存器的桶深，为多少个调节单位 */
+	ZXIC_UINT32 bucket_rate =
+			0; /* 实际写入寄存器的速率，为每4096周期添加的字节数 */
+	ZXIC_UINT32 token_grain = 0; /* 令牌桶调节档位 */
+	ZXIC_UINT32 token_grain_kb[8] = {
+		128, 64, 32, 16, 8, 4, 2, 1
+	}; /* 档位对应值 */
+	DPP_ETM_SHAP_BKT_PARA_TBL_T shap_para_tbl_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para_id);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_flow_para_tbl);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0,
+										DPP_ETM_Q_NUM - 1);
+
+	flow_id_e = flow_id + DPP_ETM_Q_NUM;
+
+	table_id = flow_id / 2048;
+
+	/*获取流的profile_id*/
+	if (mode) {
+		table_id = flow_id_e / 2048;
+		rc = dpp_tm_shape_map_table_get(dev, flow_id_e, &profile_id);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_shape_map_table_get");
+	} else {
+		rc = dpp_tm_shape_map_table_get(dev, flow_id, &profile_id);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_shape_map_table_get");
+	}
+
+	/*从寄存器读取流配置参数*/
+	bucket_para_n = table_id * 128 + profile_id;
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), bucket_para_n, 0, 0xAFF);
+
+	rc = dpp_reg_read(dev, ETM_SHAP_BKT_PARA_TBLr, 0, bucket_para_n,
+					  &shap_para_tbl_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	bucket_depth = shap_para_tbl_t.bucket_depth;
+	bucket_rate = shap_para_tbl_t.bucket_rate;
+
+	/*数据转换处理*/
+	rc = dpp_tm_shape_token_grain_get(dev, &token_grain);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_shape_token_grain_get");
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_grain, 0, 7);
+
+	*p_para_id = bucket_para_n;
+	p_flow_para_tbl->shape_cbs = bucket_depth * token_grain_kb[token_grain];
+	p_flow_para_tbl->shape_cir = (ZXIC_UINT64)bucket_rate * DPP_TM_SYS_HZ * 8 /
+								 ((ZXIC_UINT64)4096 * DPP_TM_KILO_ULL * 64);
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** etm配置流级整形参数
+ * @param   dev_id    设备编号
+ * @param   flow_id   流队列号 ETM:0-9215,FTM:0-2047
+ * @param   cir       cir速率，单位Kb，范围[20Kb - 160Gb]
+ * @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
+ *                    注：cbs=0 表示关闭整形,即不限速
+ * @param   db_en     双桶整形使能，0-单桶，1-双桶
+ * @param   eir       eir速率，单位Kb，范围同cir
+ * @param   ebs       ebs桶深，单位KB，范围同cbs
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_etm_shape_flow_para_set(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+									   ZXIC_UINT32 cir, ZXIC_UINT32 cbs,
+									   ZXIC_UINT32 db_en, ZXIC_UINT32 eir,
+									   ZXIC_UINT32 ebs)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 table_id = 0;
+	ZXIC_UINT32 profile_id = 0;
+	ZXIC_UINT32 total_para_id = 0;
+	ZXIC_UINT32 get_profile_success_flag_c =
+			0; /* 当前已配置表中是否找到需要的整形模板 */
+	ZXIC_UINT32 get_profile_success_flag_e =
+			0; /* 当前已配置表中是否找到需要的整形模板 */
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 2);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0,
+										DPP_ETM_Q_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cir, DPP_TM_SHAPE_CIR_MIN,
+										DPP_TM_SHAPE_CIR_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cbs, DPP_TM_SHAPE_CBS_MIN,
+										DPP_TM_SHAPE_CBS_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), db_en, 0, 1);
+
+	if (db_en) {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(
+				DEV_ID(dev), eir, DPP_TM_SHAPE_CIR_MIN, DPP_TM_SHAPE_CIR_MAX);
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(
+				DEV_ID(dev), ebs, DPP_TM_SHAPE_CBS_MIN, DPP_TM_SHAPE_CBS_MAX);
+	}
+
+	rc = dpp_tm_global_var_mutex_init();
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_global_var_mutex_init");
+
+	rc = zxic_comm_mutex_lock(&g_dpp_tm_global_var_rw_mutex);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_lock");
+
+	/**双桶开关配置**/
+	rc = dpp_tm_shape_flow_db_en_set(dev, db_en, 0);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc,
+											"dpp_tm_shape_flow_db_en_set",
+											&g_dpp_tm_global_var_rw_mutex);
+
+	/******STEP1:先解除原profile_id映射******/
+	/**处理c桶**/
+	rc = dpp_tm_shape_map_table_get(dev, flow_id, &profile_id);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc,
+											"dpp_tm_shape_map_table_get",
+											&g_dpp_tm_global_var_rw_mutex);
+
+	if (profile_id > 0 && (profile_id < DPP_TM_SHAP_MAP_ID_MAX)) {
+		/***表示当前有配置整形: 根据id计算归属哪张表：每2K队列对应一个128项表***/
+		table_id = flow_id / 2048;
+
+		if (g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][profile_id]
+					.shape_num != 0) {
+			g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][profile_id]
+					.shape_num--;
+		}
+	}
+
+	/**处理e桶**/
+	rc = dpp_tm_shape_map_table_get(dev, (flow_id + DPP_ETM_Q_NUM),
+									&profile_id);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc,
+											"dpp_tm_shape_map_table_get",
+											&g_dpp_tm_global_var_rw_mutex);
+
+	if (profile_id > 0 && (profile_id < DPP_TM_SHAP_MAP_ID_MAX)) {
+		/*表示当前有配置整形*/
+		table_id = (flow_id + DPP_ETM_Q_NUM) / 2048;
+
+		if (g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][profile_id]
+					.shape_num != 0) {
+			g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][profile_id]
+					.shape_num--;
+		}
+	}
+
+	/******STEP2:整形关闭的处理******/
+	if (cbs == 0) {
+		/*关闭c桶e桶整形,并返回函数*/
+		rc = dpp_tm_shape_map_table_set(dev, (flow_id), 0);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc,
+												"dpp_tm_shape_map_table_set",
+												&g_dpp_tm_global_var_rw_mutex);
+		rc = dpp_tm_shape_map_table_set(dev, (flow_id + DPP_ETM_Q_NUM), 0);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc,
+												"dpp_tm_shape_map_table_set",
+												&g_dpp_tm_global_var_rw_mutex);
+
+		rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "zxic_comm_mutex_unlock");
+		return DPP_OK;
+	}
+
+	if (ebs == 0 || db_en == 0) {
+		/*关闭e桶整形*/
+		rc = dpp_tm_shape_map_table_set(dev, (flow_id + DPP_ETM_Q_NUM), 0);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc,
+												"dpp_tm_shape_map_table_set",
+												&g_dpp_tm_global_var_rw_mutex);
+		get_profile_success_flag_e = 1;
+	}
+
+	/******STEP3:整形配置处理,先在现有模板中查找******/
+	/* 单桶整形 :c桶 */
+	if (ebs == 0) {
+		/* 此时只有cbs>0，仅开启c桶整形：先查找c桶整形profile配置 */
+		rc = dpp_tm_shape_find_map_id(dev, flow_id, cir, cbs);
+
+		if (rc) {
+			get_profile_success_flag_c = 1;
+		} else {
+			get_profile_success_flag_c = 0;
+		}
+	}
+	/* 双桶整形 :c+e桶 */
+	else {
+		/* 此时cbs>0,ebs>0：先查找c桶整形profile配置 */
+		rc = dpp_tm_shape_find_map_id(dev, flow_id, cir, cbs);
+
+		if (rc) {
+			get_profile_success_flag_c = 1;
+		} else {
+			get_profile_success_flag_c = 0;
+		}
+
+		/* 查找e桶整形profile配置 */
+		rc = dpp_tm_shape_find_map_id(dev, flow_id + DPP_ETM_Q_NUM, eir, ebs);
+
+		if (rc) {
+			get_profile_success_flag_e = 1;
+		} else {
+			get_profile_success_flag_e = 0;
+		}
+	}
+
+	/******STEP4:现有整形模板中未找到所需profile******/
+	if (!get_profile_success_flag_c) {
+		/* 根据id计算归属哪张表：每2K对应一个128项表 */
+		table_id = flow_id / 2048;
+
+		for (i = 1; i < 128; i++) {
+			if (g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_num ==
+				0) {
+				/**********映射模板id********/
+				rc = dpp_tm_shape_map_table_set(dev, flow_id, i);
+				ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+						DEV_ID(dev), rc, "dpp_tm_shape_map_table_set",
+						&g_dpp_tm_global_var_rw_mutex);
+
+				/*********整形参数配置********/
+				total_para_id = table_id * 128 + i;
+				rc = dpp_tm_shape_para_set(dev, total_para_id, cir, cbs);
+				ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+						DEV_ID(dev), rc, "dpp_tm_shape_para_set",
+						&g_dpp_tm_global_var_rw_mutex);
+
+				/********同步更新全局数组******/
+				g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_cir =
+						cir;
+				g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_cbs =
+						cbs;
+				g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_num++;
+
+				get_profile_success_flag_c = 1;
+				break;
+			}
+		}
+	}
+
+	if (!get_profile_success_flag_e && ebs) {
+		/* 根据id计算归属哪张表：每2K对应一个128项表 */
+		table_id = (flow_id + DPP_ETM_Q_NUM) / 2048;
+
+		for (i = 1; i < 128; i++) {
+			if (g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_num ==
+				0) {
+				/**********映射模板id********/
+				rc = dpp_tm_shape_map_table_set(dev, (flow_id + DPP_ETM_Q_NUM),
+												i);
+				ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+						DEV_ID(dev), rc, "dpp_tm_shape_map_table_set",
+						&g_dpp_tm_global_var_rw_mutex);
+
+				/*********整形参数配置********/
+				total_para_id = table_id * 128 + i;
+				rc = dpp_tm_shape_para_set(dev, total_para_id, eir, ebs);
+				ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+						DEV_ID(dev), rc, "dpp_tm_shape_para_set",
+						&g_dpp_tm_global_var_rw_mutex);
+
+				/********同步更新全局数组******/
+				g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_cir =
+						eir;
+				g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_cbs =
+						ebs;
+				g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_num++;
+
+				get_profile_success_flag_e = 1;
+				break;
+			}
+		}
+	}
+
+	if (!get_profile_success_flag_c || !get_profile_success_flag_e) {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+								  "Failure!  Profile resource are FULL!\n");
+		rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "zxic_comm_mutex_unlock");
+
+		return DPP_ERR;
+	}
+
+	rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** tm配置调度器整形参数
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   se_id     调度器编号号,用户看到：ETM 0-0x63FF, FTM 0-0x77F
+ *                    实际：ETM:0x4800-0xABFF,FTM:0x1000-0x177F
+ * @param   pir       pir总速率，单位Kb，范围同cir
+ * @param   pbs       pbs总桶深，单位KB，范围同cbs
+ * @param   db_en      整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效
+ * @param   cir       [0-3]调度器cir速率，单位Kb，范围[64Kb - 160Gb]
+ * @param   cbs       [0-3]调度器cbs桶深，单位KB，范围[1KB - 64M]
+ *                    注：cbs=0 表示关闭整形,即不限速
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_se_para_set(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+									ZXIC_UINT32 pir, ZXIC_UINT32 pbs,
+									ZXIC_UINT32 db_en, ZXIC_UINT32 cir,
+									ZXIC_UINT32 cbs)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+
+	rc = dpp_etm_shape_se_para_set(dev, se_id, pir, pbs, db_en, cir, cbs);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_etm_shape_se_para_set");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取调度单元整形参数
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   se_id     调度器单元号 ETM:0-63FF,FTM:0-77F
+ * @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
+ * @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
+ *                     注：cbs=0 表示关闭整形,即不限速
+ * @param   mode    整形模式，0-获取p桶参数，1-获取对应c桶参数(仅FQ8/WFQ8支持)
+ * @param   p_para_id   整形模板索引：ETM=[0-AFF]，FTM=[0-17F]
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_se_para_get(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+									ZXIC_UINT32 mode, ZXIC_UINT32 *p_para_id,
+									DPP_TM_SHAPE_PARA_TABLE *p_se_para_tbl)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 real_se_id = 0;
+	ZXIC_UINT32 se_id_c = 0;
+	ZXIC_UINT32 table_id = 0;
+	ZXIC_UINT32 profile_id = 0;
+	ZXIC_UINT32 bucket_para_n = 0;
+	ZXIC_UINT32 bucket_depth = 0; /* 实际写入寄存器的桶深，为多少个调节单位 */
+	ZXIC_UINT32 bucket_rate =
+			0; /* 实际写入寄存器的速率，为每4096周期添加的字节数 */
+	ZXIC_UINT32 token_grain = 0; /* 令牌桶调节档位 */
+	ZXIC_UINT32 token_grain_kb[8] = {
+		128, 64, 32, 16, 8, 4, 2, 1
+	}; /* 档位对应值 */
+	DPP_ETM_SHAP_BKT_PARA_TBL_T shap_para_tbl_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para_id);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_se_para_tbl);
+
+	real_se_id = (se_id + DPP_ETM_SHAP_SEID_BASE);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), real_se_id, 0,
+										DPP_ETM_SCH_DEL_NUM);
+
+	se_id_c = real_se_id + 4;
+
+	table_id = real_se_id / 2048;
+
+	/*获取调度器的profile_id*/
+	if (mode) {
+		rc = dpp_tm_shape_map_table_get(dev, se_id_c, &profile_id);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_shape_map_table_get");
+	} else {
+		rc = dpp_tm_shape_map_table_get(dev, real_se_id, &profile_id);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_shape_map_table_get");
+	}
+
+	/*从寄存器读取调度器配置参数*/
+	bucket_para_n = table_id * 128 + profile_id;
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), bucket_para_n, 0, 0xAFF);
+
+	rc = dpp_reg_read(dev, ETM_SHAP_BKT_PARA_TBLr, 0, bucket_para_n,
+					  &shap_para_tbl_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	bucket_depth = shap_para_tbl_t.bucket_depth;
+	bucket_rate = shap_para_tbl_t.bucket_rate;
+
+	/*数据转换处理*/
+	rc = dpp_tm_shape_token_grain_get(dev, &token_grain);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_shape_token_grain_get");
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_grain, 0, 7);
+
+	*p_para_id = bucket_para_n;
+	p_se_para_tbl->shape_cbs = bucket_depth * token_grain_kb[token_grain];
+	p_se_para_tbl->shape_cir = (ZXIC_UINT64)bucket_rate * DPP_TM_SYS_HZ * 8 /
+							   ((ZXIC_UINT64)4096 * DPP_TM_KILO_ULL * 64);
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** etm配置调度器整形参数
+ * @param   dev_id    设备编号
+ * @param   se_id     调度器编号号 ETM 0-0x63FF, FTM 0-0x77F
+ *                    实际：ETM:0x4800-0xABFF,FTM:0x1000-0x177F
+ * @param   pir       pir总速率，单位Kb，范围同cir
+ * @param   pbs       pbs总桶深，单位Kb，范围同cbs
+ * @param   db_en     整形模式，0-单桶，1-双桶，仅FQ8/WFQ8有效
+ * @param   cir       [0-3]调度器cir速率，单位Kb，范围[64Kb - 160Gb]
+ * @param   cbs       [0-3]调度器cbs桶深，单位KB，范围[1KB - 64M]
+ *                    注：cbs=0 表示关闭整形,即不限速
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_etm_shape_se_para_set(DPP_DEV_T *dev, ZXIC_UINT32 se_id,
+									 ZXIC_UINT32 pir, ZXIC_UINT32 pbs,
+									 ZXIC_UINT32 db_en, ZXIC_UINT32 cir,
+									 ZXIC_UINT32 cbs)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 real_se_id = 0;
+	ZXIC_UINT32 sch_type = 0;
+	ZXIC_UINT32 sch_type_num = 0;
+	ZXIC_UINT32 table_id = 0;
+	ZXIC_UINT32 profile_id = 0;
+	ZXIC_UINT32 total_para_id = 0;
+	ZXIC_UINT32 get_profile_success_flag_p =
+			0; /* 当前已配置表中是否找到需要的p桶整形模板 */
+	ZXIC_UINT32 get_profile_success_flag_c =
+			0; /* 当前已配置表中是否找到需要的c桶整形模板 */
+	DPP_ETM_CRDT_SE_PARA_TBL_T crdt_se_para_tabl_t = {
+		0
+	}; /*配置cp双桶模式,仅FQ8/WFQ8使用*/
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 2);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), se_id, 0,
+										DPP_ETM_FQSPWFQ_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pir, DPP_TM_SHAPE_CIR_MIN,
+										DPP_TM_SHAPE_CIR_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), pbs, DPP_TM_SHAPE_CBS_MIN,
+										DPP_TM_SHAPE_CBS_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), db_en, 0, 1);
+
+	real_se_id = (se_id + DPP_ETM_SHAP_SEID_BASE);
+
+	if (db_en) {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(
+				DEV_ID(dev), cir, DPP_TM_SHAPE_CIR_MIN, DPP_TM_SHAPE_CIR_MAX);
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(
+				DEV_ID(dev), cbs, DPP_TM_SHAPE_CBS_MIN, DPP_TM_SHAPE_CBS_MAX);
+	}
+
+	rc = dpp_tm_global_var_mutex_init();
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_global_var_mutex_init");
+
+	rc = zxic_comm_mutex_lock(&g_dpp_tm_global_var_rw_mutex);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_lock");
+
+	rc = dpp_tm_crdt_sch_type_get(dev, se_id, &sch_type, &sch_type_num);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc,
+											"dpp_tm_crdt_sch_type_get",
+											&g_dpp_tm_global_var_rw_mutex);
+
+	/**双桶模式配置:crdt模块se_id不用转换**/
+	if (sch_type == 8) {
+		for (i = 0; i < 8; i++) {
+			rc = dpp_reg_read(dev, ETM_CRDT_SE_PARA_TBLr, 0, se_id + i,
+							  &crdt_se_para_tabl_t);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+					DEV_ID(dev), rc, "dpp_reg_read",
+					&g_dpp_tm_global_var_rw_mutex);
+
+			crdt_se_para_tabl_t.cp_token_en = db_en;
+
+			rc = dpp_reg_write(dev, ETM_CRDT_SE_PARA_TBLr, 0, se_id + i,
+							   &crdt_se_para_tabl_t);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+					DEV_ID(dev), rc, "dpp_reg_write",
+					&g_dpp_tm_global_var_rw_mutex);
+		}
+	}
+
+	/******STEP1:先解除原profile_id映射******/
+	/**处理p桶**/
+	rc = dpp_tm_shape_map_table_get(dev, real_se_id, &profile_id);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc,
+											"dpp_tm_shape_map_table_get",
+											&g_dpp_tm_global_var_rw_mutex);
+
+	if (profile_id > 0 && (profile_id < DPP_TM_SHAP_MAP_ID_MAX)) {
+		/***表示当前有配置整形: 根据id计算归属哪张表：每2K队列对应一个128项表***/
+		table_id = real_se_id / 2048;
+
+		if (g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][profile_id]
+					.shape_num != 0) {
+			g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][profile_id]
+					.shape_num--;
+		}
+	}
+
+	if (sch_type == 8) {
+		/**处理c桶**/
+		rc = dpp_tm_shape_map_table_get(dev, (real_se_id + 4), &profile_id);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(DEV_ID(dev), rc,
+												"dpp_tm_shape_map_table_get",
+												&g_dpp_tm_global_var_rw_mutex);
+
+		if (profile_id > 0 && (profile_id < DPP_TM_SHAP_MAP_ID_MAX)) {
+			/*表示当前有配置整形*/
+			table_id = (real_se_id + 4) / 2048;
+
+			if (g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][profile_id]
+						.shape_num != 0) {
+				g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][profile_id]
+						.shape_num--;
+			}
+		}
+	}
+
+	/******STEP2:整形关闭的处理******/
+	if (sch_type < 8) {
+		/**非FQ8/WFQ8类型调度器：无双桶模式**/
+		if (pbs == 0) {
+			/*关闭p桶整形,并返回函数*/
+			rc = dpp_tm_shape_map_table_set(dev, (real_se_id), 0);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+					DEV_ID(dev), rc, "dpp_tm_shape_map_table_set",
+					&g_dpp_tm_global_var_rw_mutex);
+
+			rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+											 "zxic_comm_mutex_unlock");
+
+			return DPP_OK;
+		}
+	} else {
+		/**FQ8/WFQ8类型调度器：考虑双桶**/
+		if (pbs == 0 && db_en == 0) {
+			/*单桶模式：关闭p桶整形,并返回函数*/
+			rc = dpp_tm_shape_map_table_set(dev, (real_se_id), 0);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+					DEV_ID(dev), rc, "dpp_tm_shape_map_table_set",
+					&g_dpp_tm_global_var_rw_mutex);
+
+			rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+											 "zxic_comm_mutex_unlock");
+
+			return DPP_OK;
+		}
+
+		if (pbs == 0 && db_en == 1 && cbs == 0) {
+			/*双桶模式：关闭p+c桶整形，并返回函数*/
+			rc = dpp_tm_shape_map_table_set(dev, (real_se_id), 0);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+					DEV_ID(dev), rc, "dpp_tm_shape_map_table_set",
+					&g_dpp_tm_global_var_rw_mutex);
+			rc = dpp_tm_shape_map_table_set(dev, (real_se_id + 4), 0);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+					DEV_ID(dev), rc, "dpp_tm_shape_map_table_set",
+					&g_dpp_tm_global_var_rw_mutex);
+
+			rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
+			ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+											 "zxic_comm_mutex_unlock");
+
+			return DPP_OK;
+		}
+	}
+
+	/******STEP3:整形配置处理,先在现有模板中查找******/
+	/* 非FQ8/WFQ8类型：仅处理p桶，c桶flag直接至1 */
+	if (sch_type < 8) {
+		/* 查找p桶整形profile配置 */
+		rc = dpp_tm_shape_find_map_id(dev, real_se_id, pir, pbs);
+
+		if (rc) {
+			get_profile_success_flag_p = 1;
+		} else {
+			get_profile_success_flag_p = 0;
+		}
+
+		get_profile_success_flag_c = 1;
+	} else {
+		/* FQ8/WFQ8类型：p+c桶 */
+		if (db_en == 0) {
+			/* 单桶模式：仅查找p桶整形profile配置 */
+			rc = dpp_tm_shape_find_map_id(dev, real_se_id, pir, pbs);
+
+			if (rc) {
+				get_profile_success_flag_p = 1;
+			} else {
+				get_profile_success_flag_p = 0;
+			}
+
+			get_profile_success_flag_c = 1;
+		} else {
+			/* 双桶模式：先查找p桶整形profile配置 */
+			if (pbs == 0) {
+				rc = dpp_tm_shape_map_table_set(dev, real_se_id, 0);
+				ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+						DEV_ID(dev), rc, "dpp_tm_shape_map_table_set",
+						&g_dpp_tm_global_var_rw_mutex);
+
+				get_profile_success_flag_p = 1;
+			} else {
+				rc = dpp_tm_shape_find_map_id(dev, real_se_id, pir, pbs);
+
+				if (rc) {
+					get_profile_success_flag_p = 1;
+				} else {
+					get_profile_success_flag_p = 0;
+				}
+			}
+
+			/* 查找c桶整形profile配置 */
+			if (cbs == 0) {
+				rc = dpp_tm_shape_map_table_set(dev, (real_se_id + 4), 0);
+				ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+						DEV_ID(dev), rc, "dpp_tm_shape_map_table_set",
+						&g_dpp_tm_global_var_rw_mutex);
+
+				get_profile_success_flag_c = 1;
+			} else {
+				rc = dpp_tm_shape_find_map_id(dev, (real_se_id + 4), cir, cbs);
+
+				if (rc) {
+					get_profile_success_flag_c = 1;
+				} else {
+					get_profile_success_flag_c = 0;
+				}
+			}
+		}
+	}
+
+	/******STEP4:现有整形模板中未找到所需profile******/
+	if (!get_profile_success_flag_p) {
+		/* 根据id计算归属哪张表：每2K对应一个128项表 */
+		table_id = real_se_id / 2048;
+
+		for (i = 1; i < 128; i++) {
+			if (g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_num ==
+				0) {
+				/**********映射模板id********/
+				rc = dpp_tm_shape_map_table_set(dev, real_se_id, i);
+				ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+						DEV_ID(dev), rc, "dpp_tm_shape_map_table_set",
+						&g_dpp_tm_global_var_rw_mutex);
+
+				/*********整形参数配置********/
+				total_para_id = table_id * 128 + i;
+				rc = dpp_tm_shape_para_set(dev, total_para_id, pir, pbs);
+				ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+						DEV_ID(dev), rc, "dpp_tm_shape_para_set",
+						&g_dpp_tm_global_var_rw_mutex);
+
+				/********同步更新全局数组******/
+				g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_cir =
+						pir;
+				g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_cbs =
+						pbs;
+				g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_num++;
+
+				get_profile_success_flag_p = 1;
+				break;
+			}
+		}
+	}
+
+	if (!get_profile_success_flag_c) {
+		/* 根据id计算归属哪张表：每2K对应一个128项表 */
+		table_id = (real_se_id + 4) / 2048;
+
+		for (i = 1; i < 128; i++) {
+			if (g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_num ==
+				0) {
+				/**********映射模板id********/
+				rc = dpp_tm_shape_map_table_set(dev, (real_se_id + 4), i);
+				ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+						DEV_ID(dev), rc, "dpp_tm_shape_map_table_set",
+						&g_dpp_tm_global_var_rw_mutex);
+
+				/*********整形参数配置********/
+				total_para_id = table_id * 128 + i;
+				rc = dpp_tm_shape_para_set(dev, total_para_id, cir, cbs);
+				ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT_UNLOCK(
+						DEV_ID(dev), rc, "dpp_tm_shape_para_set",
+						&g_dpp_tm_global_var_rw_mutex);
+
+				/********同步更新全局数组******/
+				g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_cir =
+						cir;
+				g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_cbs =
+						cbs;
+				g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][i].shape_num++;
+
+				get_profile_success_flag_c = 1;
+				break;
+			}
+		}
+	}
+
+	if (!get_profile_success_flag_p || !get_profile_success_flag_c) {
+		ZXIC_COMM_TRACE_DEV_ERROR(DEV_ID(dev),
+								  "Failure!  Profile resource are FULL!\n");
+
+		rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "zxic_comm_mutex_unlock");
+		return DPP_ERR;
+	}
+
+	rc = zxic_comm_mutex_unlock(&g_dpp_tm_global_var_rw_mutex);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "zxic_comm_mutex_unlock");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 写入流/调度器整形参数配置表
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   total_para_id    整形参数表中模板索引id ETM:0-AFF,FTM:0-17F
+ * @param   cir       整形速率(c/e桶统一)
+ * @param   cbs       桶深
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_para_set(DPP_DEV_T *dev, ZXIC_UINT32 total_para_id,
+								 ZXIC_UINT32 cir, ZXIC_UINT32 cbs)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 bucket_depth = 0; /* 实际写入寄存器的桶深，为多少个调节单位 */
+	ZXIC_UINT32 bucket_rate =
+			0; /* 实际写入寄存器的速率，为每4096周期添加的字节数 */
+	ZXIC_UINT32 token_grain = 0; /* 令牌桶调节档位 */
+	ZXIC_UINT32 token_grain_kb[8] = {
+		128, 64, 32, 16, 8, 4, 2, 1
+	}; /* 档位对应值 */
+	DPP_ETM_SHAP_BKT_PARA_TBL_T shap_para_tbl_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cir, DPP_TM_SHAPE_CIR_MIN,
+										DPP_TM_SHAPE_CIR_MAX);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cbs, DPP_TM_SHAPE_CBS_MIN,
+										DPP_TM_SHAPE_CBS_MAX);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), total_para_id, 0, 0xAFF);
+
+	/********* 数据转换处理:Begin ********/
+
+	rc = dpp_tm_shape_token_grain_get(dev, &token_grain);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_shape_token_grain_get");
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_grain, 0, 7);
+
+	if (cbs < token_grain_kb[token_grain] && (cbs != 0)) {
+		bucket_depth = 1; /* 最小为1个桶深调节单位 */
+	} else {
+		bucket_depth = cbs / token_grain_kb[token_grain];
+	}
+
+	/* 寄存器最大可写范围为[0-2047] */
+	if (bucket_depth > DPP_TM_SHAPE_CBS_REG_MAX) {
+		bucket_depth = DPP_TM_SHAPE_CBS_REG_MAX;
+	}
+
+	/* 平均每周期添加cir*1/64bit，即每4096周期添加的字节数 */
+	// bucket_rate = (ZXIC_UINT64)4096 * cir * DPP_TM_KILO_ULL * 64 / (((ZXIC_UINT64)DPP_TM_SYS_HZ / (ZXIC_UINT64)13393)
+	// * 8);
+	bucket_rate = (ZXIC_UINT64)4096 * cir * DPP_TM_KILO_ULL * 64 /
+				  ((ZXIC_UINT64)DPP_TM_SYS_HZ * 8);
+	shap_para_tbl_t.bucket_rate = bucket_rate;
+	shap_para_tbl_t.bucket_depth = bucket_depth;
+
+	/******** 数据转换处理:End *********/
+
+	rc = dpp_reg_write(dev, ETM_SHAP_BKT_PARA_TBLr, 0, total_para_id,
+					   &shap_para_tbl_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取流/调度器整形参数配置表
+ * @param   dev_id    设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   total_para_id    整形参数表中模板索引id ETM:0-AFF,FTM:0-17F
+ * @param   cir       整形速率(c/e桶统一)
+ * @param   cbs       桶深
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  whuashan      @date  2019/03/11
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_para_get(DPP_DEV_T *dev, ZXIC_UINT32 total_para_id,
+								 DPP_TM_SHAPE_PARA_TABLE *p_shap_para_tbl)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 token_grain = 0; /* 令牌桶调节档位 */
+	ZXIC_UINT32 token_grain_kb[8] = {
+		128, 64, 32, 16, 8, 4, 2, 1
+	}; /* 档位对应值 */
+	DPP_ETM_SHAP_BKT_PARA_TBL_T shap_para_tbl_t = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_shap_para_tbl);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), total_para_id, 0, 0xAFF);
+
+	/*读取配置*/
+	rc = dpp_reg_read(dev, ETM_SHAP_BKT_PARA_TBLr, 0, total_para_id,
+					  &shap_para_tbl_t);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	/********* 数据转换处理: ********/
+	rc = dpp_tm_shape_token_grain_get(dev, &token_grain);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_shape_token_grain_get");
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), token_grain, 0, 7);
+
+	p_shap_para_tbl->shape_cbs =
+			shap_para_tbl_t.bucket_depth * token_grain_kb[token_grain];
+	p_shap_para_tbl->shape_cir = (ZXIC_UINT64)shap_para_tbl_t.bucket_rate *
+								 DPP_TM_SYS_HZ * 8 /
+								 ((ZXIC_UINT64)4096 * DPP_TM_KILO_ULL * 64);
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 配置端口级整形参数  更改整形转换公式
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   port_id   端口号
+ * @param   p_para   整形信息:CIR/CBS/EN
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/04/15
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_pp_para_set(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+									const DPP_TM_SHAPE_PP_PARA_T *p_para)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 cir = 0; /* 颗粒度的倍数 */
+	ZXIC_UINT32 cbs = 0; /* Credit的倍数 */
+	ZXIC_UINT32 qmu_credit_value = 0;
+	// ZXIC_FLOAT DPP_TM_SHAPE_CIR_STEP_TEST = 160.069565217 * 1000 * 1000 * 1000 / 0x3FFFFFE;/*测试使用 by xuhb*/
+
+	DPP_ETM_CRDT_PP_WEIGHT_RAM_T pp_weight = { 0 };
+	DPP_ETM_CRDT_PP_CBS_SHAPE_EN_RAM_T pp_cbs_shape_en = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0,
+										DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), p_para->c_en, 0, 1);
+
+	if (p_para->c_en == 0) {
+		rc = dpp_reg_read(dev, ETM_CRDT_PP_CBS_SHAPE_EN_RAMr, 0, port_id,
+						  &pp_cbs_shape_en);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+		pp_cbs_shape_en.pp_c_shap_en = p_para->c_en;
+		rc = dpp_reg_write(dev, ETM_CRDT_PP_CBS_SHAPE_EN_RAMr, 0, port_id,
+						   &pp_cbs_shape_en);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+	} else {
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), p_para->cir,
+											DPP_TM_SHAPE_CIR_MIN,
+											DPP_TM_SHAPE_CIR_MAX);
+
+		/* 读取授权价值 */
+		rc = dpp_tm_qmu_credit_value_get(dev, &qmu_credit_value);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_qmu_credit_value_get");
+
+		cir = p_para->cir;
+		// cir = (ZXIC_UINT32)(((ZXIC_UINT64)cir * DPP_TM_KILO_ULL) / DPP_TM_SHAPE_CIR_STEP)*(crdt_credit_value /
+		// qmu_credit_value);
+		cir = (ZXIC_UINT32)(((ZXIC_UINT64)cir * DPP_TM_KILO_ULL) /
+							DPP_TM_SHAPE_CIR_STEP);
+
+		/* 解决160Gbps设置出错的问题add by cuiy at 2016-4-15   */
+		if (cir > 0x3FFFFFE) {
+			cir = 0x3FFFFFE;
+		}
+
+		/* 检查以kbyte为单位的CBS */
+		if (qmu_credit_value != 0) {
+			cbs = p_para->cbs;
+			cbs = cbs * DPP_TM_KILO_UL / qmu_credit_value;
+		}
+
+		/* 寄存器写入CBS的最小值为20，小于该值时，整形不准 */
+		if (cbs < DPP_TM_SHAPE_DEFAULT_CBS) {
+			cbs = DPP_TM_SHAPE_DEFAULT_CBS;
+		}
+
+		ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), cbs,
+											DPP_TM_SHAPE_DEFAULT_CBS, 0x1ffff);
+
+		pp_cbs_shape_en.pp_cbs = cbs;
+		pp_weight.pp_c_weight = cir;
+		pp_cbs_shape_en.pp_c_shap_en = p_para->c_en;
+
+		rc = dpp_reg_write(dev, ETM_CRDT_PP_WEIGHT_RAMr, 0, port_id,
+						   &pp_weight);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+
+		rc = dpp_reg_write(dev, ETM_CRDT_PP_CBS_SHAPE_EN_RAMr, 0, port_id,
+						   &pp_cbs_shape_en);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_write");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 读取端口级整形参数
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   port_id   端口号
+ * @param   p_para   整形信息:CIR/CBS/EN
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cuiy      @date  2016/04/15
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_pp_para_get(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+									DPP_TM_SHAPE_PP_PARA_T *p_para)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 cbs = 0; /* Credit的倍数 */
+	ZXIC_UINT32 cir = 0; /* 颗粒度的倍数 */
+	ZXIC_UINT32 qmu_credit_value = 0;
+
+	DPP_ETM_CRDT_PP_WEIGHT_RAM_T pp_weight = { 0 };
+	DPP_ETM_CRDT_PP_CBS_SHAPE_EN_RAM_T pp_cbs_shape_en = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_para);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0,
+										DPP_TM_PP_NUM - 1);
+
+	/* 读取授权价值 */
+	rc = dpp_tm_qmu_credit_value_get(dev, &qmu_credit_value);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_qmu_credit_value_get");
+
+	rc = dpp_reg_read(dev, ETM_CRDT_PP_WEIGHT_RAMr, 0, port_id, &pp_weight);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	rc = dpp_reg_read(dev, ETM_CRDT_PP_CBS_SHAPE_EN_RAMr, 0, port_id,
+					  &pp_cbs_shape_en);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc, "dpp_reg_read");
+
+	cbs = pp_cbs_shape_en.pp_cbs;
+	cir = pp_weight.pp_c_weight;
+	p_para->c_en = pp_cbs_shape_en.pp_c_shap_en;
+	p_para->cir = (ZXIC_UINT32)((ZXIC_UINT64)cir * DPP_TM_SHAPE_CIR_STEP /
+								DPP_TM_KILO_ULL);
+	p_para->cbs = (cbs * qmu_credit_value / DPP_TM_KILO_UL);
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 写入端口级整形信息
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   port_id   端口号0-63
+ * @param   cir   单位Kb
+ * @param   cbs   单位KB
+ * @param   c_en   c桶使能
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/03/03
+ ************************************************************/
+DPP_STATUS dpp_tm_shape_pp_para_wr(DPP_DEV_T *dev, ZXIC_UINT32 port_id,
+								   ZXIC_UINT32 cir, ZXIC_UINT32 cbs,
+								   ZXIC_UINT32 c_en)
+{
+	DPP_STATUS rc = DPP_OK;
+	DPP_TM_SHAPE_PP_PARA_T para = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), DEV_ID(dev), 0,
+										DPP_DEV_CHANNEL_MAX - 1);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), port_id, 0,
+										DPP_TM_PP_NUM - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), c_en, 0, 1);
+
+	para.cir = cir;
+	para.cbs = cbs;
+	para.c_en = c_en;
+
+	rc = dpp_tm_shape_pp_para_set(dev, port_id, &para);
+	ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+									 "dpp_tm_shape_pp_para_set");
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 获取全局数组中用户实际配置的整形值
+ * @param   dev_id   设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   flow_id   流队列号 ETM:0-9215,FTM:0-2047
+ * @param   cir       cir速率，单位Kb，范围[64Kb - 160Gb]
+ * @param   cbs       cbs桶深，单位KB，范围[1KB - 64M]
+ *                    注：cbs=0 表示关闭整形,即不限速
+ * @param   mode_e    整形模式，0-获取c桶参数，1-获取对应e桶参数
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark
+ * @see
+ * @author  xuhb      @date  2020/09/22
+ ************************************************************/
+DPP_STATUS
+dpp_tm_shape_flow_para_array_get(DPP_DEV_T *dev, ZXIC_UINT32 flow_id,
+								 ZXIC_UINT32 mode,
+								 DPP_TM_SHAPE_PARA_TABLE *p_flow_para_tbl)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 flow_id_e = 0;
+	ZXIC_UINT32 table_id = 0;
+	ZXIC_UINT32 profile_id = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), mode, 0, 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_flow_para_tbl);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), flow_id, 0,
+										DPP_ETM_Q_NUM - 1);
+
+	flow_id_e = flow_id + DPP_ETM_Q_NUM;
+
+	table_id = flow_id / 2048;
+
+	/*获取流的profile_id*/
+	if (mode) {
+		table_id = flow_id_e / 2048;
+		rc = dpp_tm_shape_map_table_get(dev, flow_id_e, &profile_id);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_shape_map_table_get");
+	} else {
+		rc = dpp_tm_shape_map_table_get(dev, flow_id, &profile_id);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_shape_map_table_get");
+	}
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), profile_id, 0,
+										DPP_TM_SHAP_MAP_ID_MAX - 1);
+
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), table_id, 0,
+										DPP_ETM_SHAP_TABEL_ID_MAX - 1);
+	p_flow_para_tbl->shape_cbs =
+			g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][profile_id]
+					.shape_cbs;
+	p_flow_para_tbl->shape_cir =
+			g_dpp_etm_shape_para_table[DEV_ID(dev)][table_id][profile_id]
+					.shape_cir;
+
+	return DPP_OK;
+}
+#endif
+
+#if ZXIC_REAL("TM_EXTEND_API")
+#endif
+/***********************************************************/
+/** 连续设置多个队列或端口的TD门限
+ * @param   level   层次号，0:队列级，1:端口级
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   id   起始队列号或端口号
+ * @param   td_th   TD门限，单位是KB，转换为block写入寄存器
+ * @param   num  需要设置的队列或端口数量
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_td_th_together_wr(DPP_DEV_T *dev, ZXIC_UINT32 level,
+										  ZXIC_UINT32 id, ZXIC_UINT32 td_th,
+										  ZXIC_UINT32 num)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL,
+										PP_LEVEL);
+	ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), id, num);
+
+	for (i = 0; i < num; i++) {
+		rc = dpp_tm_cgavd_td_th_set(dev, level, id + i, td_th);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_cgavd_td_th_set");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 连续获取多个队列或端口的TD门限
+ * @param   level   层次号，0:队列级，1:端口级
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   拥塞避免支持层次号，0:队列级，1:端口级，2:系统级
+ * @param   id   起始队列号或端口号
+ * @param   num  需要设置的队列或端口数量
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  cy      @date  2016/03/22
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_td_th_together_get(DPP_DEV_T *dev, ZXIC_UINT32 level,
+										   ZXIC_UINT32 id, ZXIC_UINT32 num)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 td_th = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL,
+										PP_LEVEL);
+	ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), id, num);
+
+	for (i = 0; i < num; i++) {
+		rc = dpp_tm_cgavd_td_th_get(dev, level, id + i, &td_th);
+		zxic_comm_delay(5);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_cgavd_td_th_get");
+
+		ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), id, i);
+		if (level == QUEUE_LEVEL) {
+			ZXIC_COMM_PRINT("   flow_id: 0x%x,   td_th: 0x%x\n", id + i, td_th);
+		} else {
+			ZXIC_COMM_PRINT("   pp_id: 0x%x,   td_th: 0x%x\n", id + i, td_th);
+		}
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 连续配置多个队列或端口是否支持动态门限机制
+ * @param   dev_id 设备编号
+ * @param   tm_type   0-ETM,1-FTM
+ * @param   level   WRED支持层次号，0:队列级，1:端口级
+ * @param   id   队列号或端口号
+ * @param   en   配置的值，0-不支持动态门限机制，1-支持动态门限机制
+ * @param   num   连续配置的队列数
+ *
+ * @return   DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  djf      @date  2014/02/17
+ ************************************************************/
+DPP_STATUS dpp_tm_cgavd_dyn_th_en_set_more(DPP_DEV_T *dev,
+										   DPP_TM_CGAVD_LEVEL_E level,
+										   ZXIC_UINT32 id, ZXIC_UINT32 en,
+										   ZXIC_UINT32 num)
+{
+	DPP_STATUS rc = DPP_OK;
+	ZXIC_UINT32 i = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), level, QUEUE_LEVEL,
+										PP_LEVEL);
+	ZXIC_COMM_CHECK_DEV_INDEX_NO_ASSERT(DEV_ID(dev), en, 0, 1);
+	ZXIC_COMM_CHECK_DEV_INDEX_ADD_OVERFLOW_NO_ASSERT(DEV_ID(dev), id, num);
+
+	for (i = 0; i < num; i++) {
+		rc = dpp_tm_cgavd_dyn_th_en_set(dev, level, id + i, en);
+		ZXIC_COMM_CHECK_DEV_RC_NO_ASSERT(DEV_ID(dev), rc,
+										 "dpp_tm_cgavd_dyn_th_en_set");
+	}
+
+	return DPP_OK;
+}
+#if ZXIC_REAL("TM_CPU_SOFT_RESET")
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_module.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_module.c
old mode 100755
new mode 100644
index 9268caf2bc4c6f5cb2ca2c22dab7dc8e1de78b94..6e7adecf09327919cbc3257b727250fb4df2ff0a
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_module.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_module.c
@@ -25,230 +25,244 @@
 
 /***********************************************************/
 /** dpp通用读寄存器函数
-* @param   dev_id   设备id
-* @param   addr        地址读地址
-* @param   p_data   返回数据
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  石金锋      @date  2014/01/28
-************************************************************/
+ * @param   dev_id   设备id
+ * @param   addr        地址读地址
+ * @param   p_data   返回数据
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  石金锋      @date  2014/01/28
+ ************************************************************/
 DPP_STATUS dpp_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data)
 {
-    return dpp_dev_read_channel(dev,
-                                addr,
-                                1,
-                                p_data);
+	return dpp_dev_read_channel(dev, addr, 1, p_data);
 }
 
 /***********************************************************/
 /** dpp通用写寄存器函数
-* @param   dev_id   设备id
-* @param   addr        地址写地址
-* @param   p_data   写入数据
-*
-* @return  0表示成功 非0表示操作失败
-* @remark  无
-* @see
-* @author  石金锋      @date  2014/01/28
-************************************************************/
+ * @param   dev_id   设备id
+ * @param   addr        地址写地址
+ * @param   p_data   写入数据
+ *
+ * @return  0表示成功 非0表示操作失败
+ * @remark  无
+ * @see
+ * @author  石金锋      @date  2014/01/28
+ ************************************************************/
 DPP_STATUS dpp_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data)
 {
-    return dpp_dev_write_channel(dev,
-                                 addr,
-                                 1,
-                                 p_data);
+	return dpp_dev_write_channel(dev, addr, 1, p_data);
 }
 
 #if ZXIC_REAL("SE")
 
 /***********************************************************/
 /** SE读接口
-* @param   dev_id   设备号
-* @param   addr        地址
-* @param   p_data      数据
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/11/15
-************************************************************/
+ * @param   dev_id   设备号
+ * @param   addr        地址
+ * @param   p_data      数据
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/11/15
+ ************************************************************/
 DPP_STATUS dpp_se_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data)
 {
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
 
-    return dpp_read(dev, addr, p_data);
+	return dpp_read(dev, addr, p_data);
 }
 
 /***********************************************************/
 /** SE写接口
-* @param   dev_id   设备号
-* @param   addr        地址
-* @param   p_data      数据
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/11/15
-************************************************************/
+ * @param   dev_id   设备号
+ * @param   addr        地址
+ * @param   p_data      数据
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/11/15
+ ************************************************************/
 DPP_STATUS dpp_se_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data)
 {
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
 
-    return dpp_write(dev, addr, p_data);
+	return dpp_write(dev, addr, p_data);
 }
 #endif
 
 #if ZXIC_REAL("SE ALG")
 /***********************************************************/
 /** se alg模块读寄存器函数
-* @param   dev_id   设备id
-* @param   addr        地址     读地址
-* @param   p_data      返回数据
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/04/03
-************************************************************/
-DPP_STATUS dpp_se_alg_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data)
+ * @param   dev_id   设备id
+ * @param   addr        地址     读地址
+ * @param   p_data      返回数据
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/04/03
+ ************************************************************/
+DPP_STATUS dpp_se_alg_read(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+						   ZXIC_UINT32 *p_data)
 {
-    DPP_STATUS rtn = DPP_OK;
-
-    ZXIC_UINT32 cpu_rd_rdy_addr = SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0048;
-    ZXIC_UINT32 ind_data0_addr = SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x004c;
-    ZXIC_UINT32 ind_cmd_addr = SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0004;
-    ZXIC_UINT32 cpu_rd_rdy_reg = 0;
-    ZXIC_UINT32 ind_data0_reg = 0;
-    ZXIC_UINT32 ind_cmd_reg = 0;
-    ZXIC_UINT32 cmd_data = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 cpu_rdy  = 0;
-    ZXIC_UINT32 read_cnt = 0;
-    ZXIC_UINT32 recheck_flag = 20;
-
-    ZXIC_MUTEX_T *p_alg_mutex = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-
-    ind_data0_reg = dpp_reg_addr_convert(DEV_ID(dev), SE4K, DPP_REG_FLAG_DIRECT,ind_data0_addr);
-    ind_cmd_reg = dpp_reg_addr_convert(DEV_ID(dev), SE4K, DPP_REG_FLAG_DIRECT,ind_cmd_addr);
-    cpu_rd_rdy_reg = dpp_reg_addr_convert(DEV_ID(dev), SE4K, DPP_REG_FLAG_DIRECT,cpu_rd_rdy_addr);
-
-    rtn = dpp_dev_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_REG, &p_alg_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_dev_opr_mutex_get");
-
-    rtn = zxic_comm_mutex_lock(p_alg_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "zxic_comm_mutex_lock");
-
-    /* dpp_module_get_se_alg_baseaddr(&base_addr); */
-
-    cmd_data = ((ZXIC_UINT32)0x1 << 31) | ((ZXIC_UINT32)0xF << 17) | addr;
-    rtn = dpp_dev_write_channel(dev, ind_cmd_reg, 1, &cmd_data);
-    ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_write_channel", p_alg_mutex);
-
-    while (!(cpu_rdy & 0x1))
-    {
-        rtn = dpp_dev_read_channel(dev, cpu_rd_rdy_reg, 1, &cpu_rdy);
-        ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_read_channel", p_alg_mutex);
-
-        read_cnt++;
-        /* zxic_comm_sleep(10); */
-
-        if (read_cnt > DPP_RD_CNT_MAX * DPP_RD_CNT_MAX)
-        {
-            if (recheck_flag > 0)
-            {
-                recheck_flag--;
-                read_cnt = 0;
-                rtn = dpp_dev_write_channel(dev, ind_cmd_reg, 1, &cmd_data);
-                ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_write_channel", p_alg_mutex);
-            }
-            else
-            {
-                ZXIC_COMM_PRINT("Error!!! dpp_se_alg_read get cpu_rd_rdone failed!!!\n");
-                zxic_comm_mutex_unlock(p_alg_mutex);
-                /* ZXIC_COMM_ASSERT(0); */     /* xjw mod for OLT to not assert because of causing reboot at 18.8.7 */
-                return DPP_ERR;
-            }
-        }
-
-        /* ZXIC_COMM_CHECK_DEV_INDEX(dev_id, read_cnt, 0, DPP_RD_CNT_MAX); */
-    }
-
-    for (i = 0; i < 16; i++)
-    {
-        rtn = dpp_dev_read_channel(dev, ind_data0_reg + 4 * i, 1, p_data + 15 - i);
-        ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_read_channel", p_alg_mutex);
-    }
-
-    rtn = zxic_comm_mutex_unlock(p_alg_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "zxic_comm_mutex_unlock");
-
-    return DPP_OK;
+	DPP_STATUS rtn = DPP_OK;
+
+	ZXIC_UINT32 cpu_rd_rdy_addr =
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0048;
+	ZXIC_UINT32 ind_data0_addr =
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x004c;
+	ZXIC_UINT32 ind_cmd_addr =
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0004;
+	ZXIC_UINT32 cpu_rd_rdy_reg = 0;
+	ZXIC_UINT32 ind_data0_reg = 0;
+	ZXIC_UINT32 ind_cmd_reg = 0;
+	ZXIC_UINT32 cmd_data = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 cpu_rdy = 0;
+	ZXIC_UINT32 read_cnt = 0;
+	ZXIC_UINT32 recheck_flag = 20;
+
+	ZXIC_MUTEX_T *p_alg_mutex = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+
+	ind_data0_reg = dpp_reg_addr_convert(DEV_ID(dev), SE4K, DPP_REG_FLAG_DIRECT,
+										 ind_data0_addr);
+	ind_cmd_reg = dpp_reg_addr_convert(DEV_ID(dev), SE4K, DPP_REG_FLAG_DIRECT,
+									   ind_cmd_addr);
+	cpu_rd_rdy_reg = dpp_reg_addr_convert(DEV_ID(dev), SE4K,
+										  DPP_REG_FLAG_DIRECT, cpu_rd_rdy_addr);
+
+	rtn = dpp_dev_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_REG, &p_alg_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_dev_opr_mutex_get");
+
+	rtn = zxic_comm_mutex_lock(p_alg_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "zxic_comm_mutex_lock");
+
+	/* dpp_module_get_se_alg_baseaddr(&base_addr); */
+
+	cmd_data = ((ZXIC_UINT32)0x1 << 31) | ((ZXIC_UINT32)0xF << 17) | addr;
+	rtn = dpp_dev_write_channel(dev, ind_cmd_reg, 1, &cmd_data);
+	ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_write_channel",
+								  p_alg_mutex);
+
+	while (!(cpu_rdy & 0x1)) {
+		rtn = dpp_dev_read_channel(dev, cpu_rd_rdy_reg, 1, &cpu_rdy);
+		ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_read_channel",
+									  p_alg_mutex);
+
+		read_cnt++;
+		/* zxic_comm_sleep(10); */
+
+		if (read_cnt > DPP_RD_CNT_MAX * DPP_RD_CNT_MAX) {
+			if (recheck_flag > 0) {
+				recheck_flag--;
+				read_cnt = 0;
+				rtn = dpp_dev_write_channel(dev, ind_cmd_reg, 1, &cmd_data);
+				ZXIC_COMM_CHECK_DEV_RC_UNLOCK(
+						DEV_ID(dev), rtn, "dpp_dev_write_channel", p_alg_mutex);
+			} else {
+				ZXIC_COMM_PRINT(
+						"Error!!! dpp_se_alg_read get cpu_rd_rdone failed!!!\n");
+				zxic_comm_mutex_unlock(p_alg_mutex);
+				/* ZXIC_COMM_ASSERT(0); */ /* xjw mod for OLT to not assert because of causing reboot at 18.8.7 */
+				return DPP_ERR;
+			}
+		}
+
+		/* ZXIC_COMM_CHECK_DEV_INDEX(dev_id, read_cnt, 0, DPP_RD_CNT_MAX); */
+	}
+
+	for (i = 0; i < 16; i++) {
+		rtn = dpp_dev_read_channel(dev, ind_data0_reg + 4 * i, 1,
+								   p_data + 15 - i);
+		ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_read_channel",
+									  p_alg_mutex);
+	}
+
+	rtn = zxic_comm_mutex_unlock(p_alg_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "zxic_comm_mutex_unlock");
+
+	return DPP_OK;
 }
 
 /***********************************************************/
 /** se alg模块写寄存器函数
-* @param   dev_id  设备id
-* @param   addr        地址    读地址
-* @param   p_data     返回数据
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/04/03
-************************************************************/
-DPP_STATUS dpp_se_alg_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data)
+ * @param   dev_id  设备id
+ * @param   addr        地址    读地址
+ * @param   p_data     返回数据
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/04/03
+ ************************************************************/
+DPP_STATUS dpp_se_alg_write(DPP_DEV_T *dev, ZXIC_UINT32 addr,
+							ZXIC_UINT32 *p_data)
 {
-    DPP_STATUS rtn = DPP_OK;
-
-    ZXIC_UINT32 ind_data0_addr = SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0008;
-    ZXIC_UINT32 cmd_data = 0;
-    ZXIC_UINT32 ind_cmd_addr = SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0004;
-    ZXIC_UINT32 ind_data0_reg = 0;
-    ZXIC_UINT32 ind_cmd_reg = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_MUTEX_T *p_alg_mutex = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0, DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
-
-    ind_data0_reg = dpp_reg_addr_convert(DEV_ID(dev), SE4K, DPP_REG_FLAG_DIRECT, ind_data0_addr);
-    ind_cmd_reg = dpp_reg_addr_convert(DEV_ID(dev), SE4K, DPP_REG_FLAG_DIRECT, ind_cmd_addr);
-
-    /* dpp_module_get_se_alg_baseaddr(&base_addr); */
-    rtn = dpp_dev_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_REG, &p_alg_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_dev_opr_mutex_get");
-
-    rtn = zxic_comm_mutex_lock(p_alg_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "zxic_comm_mutex_lock");
-
-    /* write data */
-    for (i = 0; i < 16; i++)
-    {
-        ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "dpp_se_alg_write: addr=0x%08x, data=0x%08x.\n", ind_data0_reg + 4 * i, *(p_data + 15 - i));
-        rtn = dpp_dev_write_channel(dev, ind_data0_reg + 4 * i, 1, p_data + 15 - i);
-        ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_write_channel", p_alg_mutex);
-    }
-
-    /* write cmd */
-    /* cmd_data = ((ZXIC_UINT32)0xF << 17) | addr; */
-    cmd_data = addr & 0x1fffff;  /* mod by tf */
-    ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "dpp_se_alg_write: addr=0x%08x, data=0x%08x.\n", ind_cmd_reg, cmd_data);
-    rtn = dpp_dev_write_channel(dev, ind_cmd_reg, 1, &cmd_data);
-    ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_write_channel", p_alg_mutex);
-
-    rtn = zxic_comm_mutex_unlock(p_alg_mutex);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "zxic_comm_mutex_unlock");
-
-    return DPP_OK;
+	DPP_STATUS rtn = DPP_OK;
+
+	ZXIC_UINT32 ind_data0_addr =
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0008;
+	ZXIC_UINT32 cmd_data = 0;
+	ZXIC_UINT32 ind_cmd_addr =
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0004;
+	ZXIC_UINT32 ind_data0_reg = 0;
+	ZXIC_UINT32 ind_cmd_reg = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_MUTEX_T *p_alg_mutex = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), DEV_ID(dev), 0,
+							  DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+
+	ind_data0_reg = dpp_reg_addr_convert(DEV_ID(dev), SE4K, DPP_REG_FLAG_DIRECT,
+										 ind_data0_addr);
+	ind_cmd_reg = dpp_reg_addr_convert(DEV_ID(dev), SE4K, DPP_REG_FLAG_DIRECT,
+									   ind_cmd_addr);
+
+	/* dpp_module_get_se_alg_baseaddr(&base_addr); */
+	rtn = dpp_dev_opr_mutex_get(DEV_ID(dev), DPP_DEV_MUTEX_T_REG, &p_alg_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "dpp_dev_opr_mutex_get");
+
+	rtn = zxic_comm_mutex_lock(p_alg_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "zxic_comm_mutex_lock");
+
+	/* write data */
+	for (i = 0; i < 16; i++) {
+		ZXIC_COMM_TRACE_DEV_DEBUG(
+				DEV_ID(dev), "dpp_se_alg_write: addr=0x%08x, data=0x%08x.\n",
+				ind_data0_reg + 4 * i, *(p_data + 15 - i));
+		rtn = dpp_dev_write_channel(dev, ind_data0_reg + 4 * i, 1,
+									p_data + 15 - i);
+		ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_write_channel",
+									  p_alg_mutex);
+	}
+
+	/* write cmd */
+	/* cmd_data = ((ZXIC_UINT32)0xF << 17) | addr; */
+	cmd_data = addr & 0x1fffff; /* mod by tf */
+	ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev),
+							  "dpp_se_alg_write: addr=0x%08x, data=0x%08x.\n",
+							  ind_cmd_reg, cmd_data);
+	rtn = dpp_dev_write_channel(dev, ind_cmd_reg, 1, &cmd_data);
+	ZXIC_COMM_CHECK_DEV_RC_UNLOCK(DEV_ID(dev), rtn, "dpp_dev_write_channel",
+								  p_alg_mutex);
+
+	rtn = zxic_comm_mutex_unlock(p_alg_mutex);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rtn, "zxic_comm_mutex_unlock");
+
+	return DPP_OK;
 }
 
 #endif
@@ -256,39 +270,39 @@ DPP_STATUS dpp_se_alg_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_dat
 #if ZXIC_REAL("PPU")
 /***********************************************************/
 /** PPU读接口
-* @param   dev_id   设备号
-* @param   addr        地址
-* @param   p_data      数据
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/11/15
-************************************************************/
+ * @param   dev_id   设备号
+ * @param   addr        地址
+ * @param   p_data      数据
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/11/15
+ ************************************************************/
 DPP_STATUS dpp_ppu_read(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data)
 {
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
 
-    return dpp_read(dev, addr, p_data);
+	return dpp_read(dev, addr, p_data);
 }
 
 /***********************************************************/
 /** PPU写接口
-* @param   dev_id   设备号
-* @param   addr        地址
-* @param   p_data      数据
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  ls      @date  2016/11/15
-************************************************************/
+ * @param   dev_id   设备号
+ * @param   addr        地址
+ * @param   p_data      数据
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  ls      @date  2016/11/15
+ ************************************************************/
 DPP_STATUS dpp_ppu_write(DPP_DEV_T *dev, ZXIC_UINT32 addr, ZXIC_UINT32 *p_data)
 {
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_data);
 
-    return dpp_write(dev, addr, p_data);
+	return dpp_write(dev, addr, p_data);
 }
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_pci.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_pci.c
old mode 100755
new mode 100644
index b900e3397d153b1cd0c7db9176ecfeb6cda401ed..ad2b85a6a41f2fbc89a039b528f43cb8ceda387a
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_pci.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_pci.c
@@ -23,67 +23,67 @@
 
 /***********************************************************/
 /**
-* @param   abs_addr
-* @param   p_data
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/02/14
-************************************************************/
-ZXIC_UINT32 dpp_pci_write32(DPP_DEV_T *dev, ZXIC_ADDR_T abs_addr, ZXIC_UINT32 *p_data)
+ * @param   abs_addr
+ * @param   p_data
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/02/14
+ ************************************************************/
+ZXIC_UINT32 dpp_pci_write32(DPP_DEV_T *dev, ZXIC_ADDR_T abs_addr,
+							ZXIC_UINT32 *p_data)
 {
-    /* ZXIC_UINT32 rtn  = 0; */
-    ZXIC_UINT32 data = 0;
-    ZXIC_UINT64 addr = 0;
+	/* ZXIC_UINT32 rtn  = 0; */
+	ZXIC_UINT32 data = 0;
+	ZXIC_UINT64 addr = 0;
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_data);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_data);
 
-    data = *p_data;
+	data = *p_data;
 
-    if (zxic_comm_is_big_endian())
-    {
-        data = ZXIC_COMM_CONVERT32(data);
-    }
+	if (zxic_comm_is_big_endian()) {
+		data = ZXIC_COMM_CONVERT32(data);
+	}
 
-    addr = abs_addr + SYS_VF_NP_BASE_OFFSET;
-    *((ZXIC_VOL ZXIC_UINT32 *)addr) = data;
+	addr = abs_addr + SYS_VF_NP_BASE_OFFSET;
+	*((ZXIC_VOL ZXIC_UINT32 *)addr) = data;
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 /***********************************************************/
 /**
-* @param   abs_addr
-* @param   p_data
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/02/14
-************************************************************/
-ZXIC_UINT32 dpp_pci_read32(DPP_DEV_T *dev, ZXIC_ADDR_T abs_addr, ZXIC_UINT32 *p_data)
+ * @param   abs_addr
+ * @param   p_data
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/02/14
+ ************************************************************/
+ZXIC_UINT32 dpp_pci_read32(DPP_DEV_T *dev, ZXIC_ADDR_T abs_addr,
+						   ZXIC_UINT32 *p_data)
 {
-    ZXIC_UINT32 data = 0;
-    ZXIC_UINT64 addr = 0;
+	ZXIC_UINT32 data = 0;
+	ZXIC_UINT64 addr = 0;
 
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_POINT(p_data);
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_POINT(p_data);
 
-    addr = abs_addr + SYS_VF_NP_BASE_OFFSET;
-    data = *((ZXIC_VOL ZXIC_UINT32 *)addr);
+	addr = abs_addr + SYS_VF_NP_BASE_OFFSET;
+	data = *((ZXIC_VOL ZXIC_UINT32 *)addr);
 
-    if (zxic_comm_is_big_endian())
-    {
-        data = ZXIC_COMM_CONVERT32(data);
-    }
-    *p_data = data;
+	if (zxic_comm_is_big_endian()) {
+		data = ZXIC_COMM_CONVERT32(data);
+	}
+	*p_data = data;
 
-    if (0xdadedade == *p_data)
-    {
-        ZXIC_COMM_TRACE_DEBUG("PCIE time out err happening at addr[0x%llx]\n", abs_addr);
-    }
+	if (0xdadedade == *p_data) {
+		ZXIC_COMM_TRACE_DEBUG("PCIE time out err happening at addr[0x%llx]\n",
+							  abs_addr);
+	}
 
-    return DPP_OK;
+	return DPP_OK;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_reg_api.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_reg_api.c
old mode 100755
new mode 100644
index c732daaef032c5a3e6ca87b521bb501d452a30f7..b3bfc2b3b03375fd17225415017edbe784bda1b2
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_reg_api.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_reg_api.c
@@ -1,544 +1,495 @@
-/**************************************************************
-* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
-* 文件名称 : dpp_reg.c
-* 文件标识 :
-* 内容摘要 :
-* 其它说明 :
-* 当前版本 :
-* 作    者 : 王春雷
-* 完成日期 : 2014/02/12
-* DEPARTMENT: ASIC_FPGA_R&D_Dept
-* MANUAL_PERCENT: 100%
-
-* 修改记录1:
-* 修改日期:
-* 版 本 号:
-* 修 改 人:
-* 修改内容:
-***************************************************************/
-
-#include "zxic_common.h"
-#include "dpp_type_api.h"
-#include "dpp_module.h"
-#include "dpp_dev.h"
-#include "dpp_reg_api.h"
-#include "dpp_reg_info.h"
-#include "dpp_agent_channel.h"
-#include "dpp_pci.h"
-
-#define REG_DATA_MAX      (512/32)
-
-static DPP_REG_OFFSET_ADDR g_module_offset_addr[] = 
-{
-    {DTB4K,   BAR_4K_DTB,   SYS_DTB_BASE_ADDR      + MODULE_DTB_ENQ_BASE_ADDR},
-    {STAT4K,  BAR_4K_ETCAM, SYS_STAT_BASE_ADDR     + MODULE_STAT_ETCAM_BASE_ADDR},
-    {PPU4K,   BAR_4K_CLS0,  SYS_PPU_BASE_ADDR      + MODULE_CLUSTER0_BASE_ADDR + 0x4000},
-    {SE4K,    BAR_4K_SE,    SYS_SE_BASE_ADDR       + MODULE_SE_ALG_BASE_ADDR},
-    {SMMU14K, BAR_4K_SMMU1, SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR }
-};
-
-/***********************************************************/
-/** 获取寄存器属性
-* @param   reg_no  寄存器编号
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/04/17
-************************************************************/
-DPP_REG_T *dpp_reg_info_get(ZXIC_UINT32 reg_no)
-{
-    ZXIC_COMM_CHECK_INDEX_RETURN_NULL(reg_no, 0, REG_ENUM_MAX_VALUE - 1);
-
-    return (&g_dpp_reg_info[reg_no]);
-}
-
-/***********************************************************/
-/** 根据寄存器编号获得寄存器芯片内绝对地址
-* @param   reg_no
-* @param   m_offset
-* @param   n_offset
-*
-* @return
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/03/19
-************************************************************/
-ZXIC_UINT32 dpp_reg_get_reg_addr(ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset)
-{
-    ZXIC_UINT32     addr        = 0;
-    DPP_REG_T  *p_reg_info = NULL;
-
-    ZXIC_COMM_CHECK_INDEX(reg_no, 0, REG_ENUM_MAX_VALUE - 1);
-
-    p_reg_info = dpp_reg_info_get(reg_no);
-    ZXIC_COMM_CHECK_POINT(p_reg_info); 
-
-    /* 计算写地址 */
-    addr = p_reg_info->addr;
-
-    if (p_reg_info->array_type & DPP_REG_UNI_ARRAY)
-    {
-        if (n_offset > (p_reg_info->n_size - 1))
-            ZXIC_COMM_TRACE_ERROR("reg n_offset is out of range, reg_no:%d, n:%d, size:%d\n",
-                                 reg_no, n_offset, p_reg_info->n_size - 1);
-
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(addr, n_offset * p_reg_info->n_step);
-        addr += n_offset * p_reg_info->n_step;
-    }
-    else if (p_reg_info->array_type & DPP_REG_BIN_ARRAY)
-    {
-        if ((n_offset > (p_reg_info->n_size - 1)) || (m_offset > (p_reg_info->m_size - 1)))
-            ZXIC_COMM_TRACE_ERROR("reg n_offset or m_offset is out of range, reg_no:%d, n:%d, n_size:%d, m:%d, m_size:%d,\n",
-                                 reg_no, n_offset, p_reg_info->n_size - 1, m_offset, p_reg_info->m_size - 1);
-
-        ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(m_offset, p_reg_info->m_step);
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT((m_offset * (p_reg_info->m_step)), (n_offset * (p_reg_info->n_step)));
-        ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(addr, (m_offset * (p_reg_info->m_step)) + (n_offset * (p_reg_info->n_step)));
-        addr += (m_offset * (p_reg_info->m_step)) + (n_offset * (p_reg_info->n_step));
-    }
-
-    return addr;
-}
-
-/***********************************************************/
-/** 判断是否为4K寄存器
-* @param   reg_module
-*
-* @return  
-* @remark  无
-* @see
-* @author  cq      @date  2023/11/29
-************************************************************/
-BOOLEAN dpp_4k_reg(ZXIC_UINT32 reg_module)
-{
-    if((DTB4K<=reg_module)&&(SMMU14K>=reg_module))
-    {
-        return ZXIC_TRUE;
-    }
-
-    return ZXIC_FALSE;
-}
-
-/***********************************************************/
-/** 获取NP对应模块的映射地址偏移(riscv或者非4K寄存器不做转换，host根据映射情况做转换)
-* @param   dev_id
-* @param   reg_module
-* @param   flags  标志位，DPP_REG_FLAG_INDIRECT DPP_REG_FLAG_DIRECT
-* @param   addr
-*
-* @return  映射地址
-* @remark  无
-* @see
-* @author  cq      @date  2023/11/29
-************************************************************/
-ZXIC_UINT32 dpp_reg_addr_convert(ZXIC_UINT32 dev_id, ZXIC_UINT32 reg_module,ZXIC_UINT32 flags, ZXIC_UINT32 addr)
-{
-    ZXIC_UINT32 convert_addr = addr;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 cluster_index = 0;
-    ZXIC_UINT32 index_4k = 0;
-    ZXIC_UINT32 size_4k = 4096;
-    ZXIC_UINT32 module_addr_offset = 0;
-    ZXIC_UINT32 dtb_addr_offset = SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR;
-
-    if(DPP_REG_FLAG_INDIRECT == flags)
-    {
-        return addr;
-    }
-
-    for(i=0;i<(sizeof(g_module_offset_addr)/sizeof(DPP_REG_OFFSET_ADDR));i++)
-    {
-        if(reg_module==g_module_offset_addr[i].reg_module)
-        {
-            module_addr_offset = g_module_offset_addr[i].addr_offset;
-            if(PPU4K==reg_module)
-            {
-                cluster_index = (addr-module_addr_offset)/DPP_PPU_CLUSTER_SPACE_SIZE;
-                index_4k = g_module_offset_addr[i].index_4k + cluster_index;
-                module_addr_offset += cluster_index * DPP_PPU_CLUSTER_SPACE_SIZE;
-            }
-            else
-            {
-                index_4k = g_module_offset_addr[i].index_4k;
-            }
-            convert_addr = ((addr + (size_4k * index_4k) + dtb_addr_offset)>module_addr_offset) 
-                        ? (addr + (size_4k * index_4k) + dtb_addr_offset - module_addr_offset) : addr;
-        }
-    }
-    
-    return convert_addr;
-}
-
-/***********************************************************/
-/** 通用寄存器写函数
-* @param   dev_id  设备号，支持多芯片
-* @param   reg_no 寄存器编号
-* @param   m_offset 二元寄存器的m偏移
-* @param   n_offset 一元寄存器或二元寄存器的n偏移
-* @param   p_data 数据指针
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/02/12
-************************************************************/
-DPP_STATUS dpp_reg_write(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset, ZXIC_VOID *p_data)
-{
-    DPP_STATUS rc = 0;
-    ZXIC_UINT32     i = 0;
-    ZXIC_UINT32     addr = 0;
-
-#ifdef DPP_FLOW_HW_INIT
-    ZXIC_UINT32     convert_addr = 0;
-#endif
-
-    ZXIC_UINT32     p_buff[REG_DATA_MAX] = {0};
-    ZXIC_UINT32     temp_data = 0;
-    ZXIC_UINT32     reg_type = 0;
-    ZXIC_UINT32     reg_module = 0;
-    ZXIC_UINT32     reg_width = 0;
-    DPP_REG_T *p_reg_info = NULL;
-    DPP_FIELD_T *p_field_info = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), reg_no, 0, REG_ENUM_MAX_VALUE - 1);
-    ZXIC_COMM_CHECK_POINT(p_data);
-
-    p_reg_info = dpp_reg_info_get(reg_no);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info);
-    p_field_info = p_reg_info->p_fields;
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_field_info);
-    reg_type = p_reg_info->flags;
-    reg_module = p_reg_info->module_no;
-    reg_width = p_reg_info->width;
-    ZXIC_COMM_CHECK_INDEX_UPPER(reg_width, REG_DATA_MAX*4);
-
-#ifndef ZXIC_OS_WIN
-#ifdef  DPP_FOR_LLT
-    if (dpp_stump_reg_en_check(DEV_ID(dev), reg_no) && (p_reg_info->flags == DPP_REG_FLAG_DIRECT || p_reg_info->flags == DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT))
-    {
-        rc = dpp_stump_reg_write(DEV_ID(dev),
-                                 reg_no,
-                                 m_offset,
-                                 n_offset,
-                                 p_data);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stump_reg_write");
-
-        return DPP_OK;
-    }
-#endif
-#endif
-
-    /* 提取各字段数据，按各字段实际bit位宽进行拼装 */
-    for (i = 0; i < p_reg_info->field_num; i++)
-    {
-        if (p_field_info[i].len <= 32)
-        {
-            /* lint -e64 */
-            temp_data = *((ZXIC_UINT32 *)p_data + i) & ZXIC_COMM_GET_BIT_MASK(ZXIC_UINT32,  p_field_info[i].len);
-            rc = zxic_comm_write_bits_ex((ZXIC_UINT8 *)p_buff,
-                                p_reg_info->width * 8,
-                                temp_data,
-                                p_field_info[i].msb_pos,
-                                p_field_info[i].len);
-            /* lint +e64 */
-            ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_write_bits_ex");
-        }
-    }    
-    
-    ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "zxic_comm_write_bits_ex data = 0x%08x.\n", p_buff[0]);
-    /* 若host cpu为小端字节序，则以4字节为单位对数据进行字节序转换 */
-    if(!zxic_comm_is_big_endian())
-    {
-        for (i = 0; i < ((p_reg_info->width) / 4); i++)
-        {
-            p_buff[i] = ZXIC_COMM_CONVERT32(p_buff[i]);
-
-            /* for debug */
-            ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "ZXIC_COMM_CONVERT32 data = 0x%08x.\n", p_buff[i]);
-        }
-    }
-    
-    /* 计算写地址 */
-    addr = dpp_reg_get_reg_addr(reg_no, m_offset, n_offset);/* 通过寄存器编号等三个参数获得寄存器的基地址 */
-    
-    ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "reg_no = %d. m_offset = %d n_offset = %d\n", reg_no,m_offset,n_offset);
-    ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "baseaddr = 0x%08x.\n", addr);
-
-#ifdef DPP_FLOW_HW_INIT
-    if(dpp_4k_reg(reg_module))
-    {
-        /* 调用寄存器写接口 */
-        convert_addr = dpp_reg_addr_convert(DEV_ID(dev), reg_module, reg_type, addr);
-        ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info->p_write_fun);
-        rc = p_reg_info->p_write_fun(dev, convert_addr, p_buff);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "p_reg_info->p_write_fun");
-    }
-#else
-    if(DTB4K == reg_module)
-    {
-        /* 调用寄存器写接口 */
-        ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info->p_write_fun);
-        rc = p_reg_info->p_write_fun(dev, addr, p_buff);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "p_reg_info->p_write_fun");
-    }
-#endif
-    else
-    {
-        /* 调用代理通道寄存器写接口 */
-        rc = dpp_agent_channel_reg_write(dev, reg_type, reg_no, reg_width, addr, p_buff); 
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_agent_channel_reg_write");  
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 通用寄存器读函数
-* @param   dev_id 设备号，支持多芯片
-* @param   reg_no 寄存器编号
-* @param   m_offset 二元寄存器的m偏移
-* @param   n_offset 一元寄存器或二元寄存器的n偏移
-* @param   p_data 数据指针
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  王春雷      @date  2014/02/12
-************************************************************/
-DPP_STATUS dpp_reg_read(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset, ZXIC_VOID *p_data)
-{
-    DPP_STATUS rc = 0;
-    ZXIC_UINT32     i  = 0;
-    ZXIC_UINT32     addr = 0;
-#ifdef DPP_FLOW_HW_INIT
-    ZXIC_UINT32     convert_addr = 0;
-#endif
-    ZXIC_UINT32     reg_type = 0;
-    ZXIC_UINT32     p_buff[REG_DATA_MAX] = {0};
-    ZXIC_UINT32     reg_module = 0;
-    ZXIC_UINT32     reg_width = 0;
-    DPP_REG_T *p_reg_info = NULL;
-    DPP_FIELD_T *p_field_info = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), reg_no, 0, REG_ENUM_MAX_VALUE - 1);
-    ZXIC_COMM_CHECK_POINT(p_data);
-
-    p_reg_info = dpp_reg_info_get(reg_no);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info);
-    p_field_info = p_reg_info->p_fields;
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_field_info);
-    reg_type = p_reg_info->flags;
-    reg_module = p_reg_info->module_no;
-    reg_width = p_reg_info->width;
-    ZXIC_COMM_CHECK_INDEX_UPPER(reg_width, REG_DATA_MAX*4);
-
-#ifndef ZXIC_OS_WIN 
-#ifdef DPP_FOR_LLT
-    if (dpp_stump_reg_en_check(DEV_ID(dev), reg_no) && (p_reg_info->flags == DPP_REG_FLAG_DIRECT || p_reg_info->flags == DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT))
-    {
-        rc = dpp_stump_reg_read(DEV_ID(dev),
-                                reg_no,
-                                m_offset,
-                                n_offset,
-                                p_data);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stump_reg_read");
-
-        return DPP_OK;
-    }
-#endif
-#endif
-
-    /* 计算读地址 */
-    addr = dpp_reg_get_reg_addr(reg_no, m_offset, n_offset);
-#ifdef DPP_FLOW_HW_INIT
-    if(dpp_4k_reg(reg_module))
-    {
-        /* 调用寄存器读接口 */
-        convert_addr = dpp_reg_addr_convert(DEV_ID(dev), reg_module, reg_type, addr);
-        ZXIC_COMM_CHECK_POINT(p_reg_info->p_read_fun);
-        rc = p_reg_info->p_read_fun(dev, convert_addr, p_buff);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "p_reg_info->p_read_fun");
-    }
-#else
-    if(DTB4K == reg_module)
-    {
-        /* 调用寄存器读接口 */
-        ZXIC_COMM_CHECK_POINT(p_reg_info->p_read_fun);
-        rc = p_reg_info->p_read_fun(dev, addr, p_buff);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "p_reg_info->p_read_fun");
-    }
-#endif
-    else
-    {
-        /* 调用代理通道寄存器读接口 */
-        rc = dpp_agent_channel_reg_read(dev, reg_type, reg_no, reg_width, addr, p_buff);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_agent_channel_reg_read");
-    }
-
-    /* 若host cpu为小端字节序，则以4字节为单位对数据进行字节序转换 */
-    if (!zxic_comm_is_big_endian())
-    {
-        for (i = 0; i < ((p_reg_info->width) / 4); i++)
-        {
-            /* for debug */
-            
-            //printf("dpp_reg_read data = 0x%08x.\n", p_buff[i]);
-            ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "dpp_reg_read data = 0x%08x.\n", p_buff[i]);
-
-            p_buff[i] = ZXIC_COMM_CONVERT32(p_buff[i]);
-        }
-    }
-
-    /* 提取各字段数据，每字段以ZXIC_UINT32形式返回 */
-    for (i = 0; i < p_reg_info->field_num; i++)
-    {
-        /* lint -e64 */
-        rc = zxic_comm_read_bits_ex((ZXIC_UINT8 *)p_buff,
-                              p_reg_info->width * 8,
-                              (ZXIC_UINT32 *)p_data + i,
-                              p_field_info[i].msb_pos,
-                              p_field_info[i].len);
-        ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_read_bits_ex");
-        /* lint +e64 */
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 通过寄存器编号配置寄存器，仅适用于32bit位宽
-    的常规寄存器
-* @param   dev_id  设备号
-* @param   reg_no     寄存器编号
-* @param   data       数据，32bit
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  XXX      @date  2019/07/10
-************************************************************/
-DPP_STATUS dpp_reg_write32(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 data)
-{
-    DPP_STATUS  rc  = 0;
-    ZXIC_UINT32      addr = 0;
-    DPP_REG_T   *p_reg_info   = NULL;
-    ZXIC_UINT32      value = data;
-    ZXIC_UINT32      j = 0;
-    ZXIC_UINT32      k = 0;
-    ZXIC_UINT32      m_size = 0;
-    ZXIC_UINT32      n_size = 0;
-    ZXIC_UINT32      reg_type = 0;
-    // ZXIC_UINT32      reg_module = 0;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), reg_no, 0, REG_ENUM_MAX_VALUE - 1);
-
-    p_reg_info = dpp_reg_info_get(reg_no);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info); 
-    reg_type = p_reg_info->flags;
-    // reg_module = p_reg_info->module_no;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_reg_info->width, 4, 4);       /* width must be 32bit */
-
-    m_size = (p_reg_info->m_size == 0) ? (1) : (p_reg_info->m_size);
-    n_size = (p_reg_info->n_size == 0) ? (1) : (p_reg_info->n_size);
-
-    /* 计算读地址 */
-    for (j = 0; j < m_size; j++)
-    {
-        for (k = 0; k < n_size; k++)
-        {
-#ifndef ZXIC_OS_WIN
-#ifdef  DPP_FOR_LLT
-            if (dpp_stump_reg_en_check(DEV_ID(dev), reg_no) && (p_reg_info->flags == DPP_REG_FLAG_DIRECT))
-            {
-                rc = dpp_stump_reg_write(DEV_ID(dev),
-                                         reg_no,
-                                         j,
-                                         k,
-                                         &data);
-                ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stump_reg_write");
-
-                return DPP_OK;
-            }
-#endif
-#endif
-            /* 计算写地址 */
-            addr = dpp_reg_get_reg_addr(reg_no, j, k);
-
-            /* 调用代理通道寄存器写接口 */
-            rc = dpp_agent_channel_reg_write(dev, reg_type, reg_no, 4, addr, &value);
-            ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_agent_channel_reg_write");
-        }
-    }
-
-    return DPP_OK;
-}
-
-/***********************************************************/
-/** 通过寄存器编号读取寄存器的值，仅适用于32bit位宽的常规寄存器
-* @param   dev_id   设备号
-* @param   reg_no   寄存器编号
-* @param   m_offset   二元寄存器的m偏移
-* @param   n_offset   一元寄存器或二元寄存器的n偏移
-* @param   p_data   出参，返回读取寄存器数值
-*
-* @return  DPP_OK-成功，DPP_ERR-失败
-* @remark  无
-* @see
-* @author  石金锋      @date  2015/03/09
-************************************************************/
-DPP_STATUS dpp_reg_read32(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset, ZXIC_UINT32 *p_data)
-{
-    DPP_STATUS rc = 0;
-    ZXIC_UINT32 addr = 0;
-    ZXIC_UINT32 reg_type = 0;
-    // ZXIC_UINT32 reg_module = 0;
-    ZXIC_UINT32 p_buff[REG_DATA_MAX] = {0};
-
-    DPP_REG_T *p_reg_info = NULL;
-
-    ZXIC_COMM_CHECK_POINT(dev);
-    ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), reg_no, 0, REG_ENUM_MAX_VALUE - 1);
-    ZXIC_COMM_CHECK_POINT(p_data);
-
-    p_reg_info = dpp_reg_info_get(reg_no);
-    ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info); 
-    reg_type = p_reg_info->flags;
-    // reg_module = p_reg_info->module_no;
-
-    ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_reg_info->width, 4, 4);       /* width must be 32bit */
-
-#ifndef ZXIC_OS_WIN
-#ifdef DPP_FOR_LLT
-    if (dpp_stump_reg_en_check(DEV_ID(dev), reg_no) && (p_reg_info->flags == DPP_REG_FLAG_DIRECT))
-    {
-        rc = dpp_stump_reg_read(DEV_ID(dev),
-                                reg_no,
-                                m_offset,
-                                n_offset,
-                                p_data);
-        ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_stump_reg_read");
-
-        return DPP_OK;
-    }
-#endif
-#endif
-
-    /* 计算读地址 */
-    addr = dpp_reg_get_reg_addr(reg_no, m_offset, n_offset);
-
-    /* 调用代理通道寄存器读接口 */
-    rc =dpp_agent_channel_reg_read(dev, reg_type, reg_no, 4, addr, p_buff);
-    ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_agent_channel_reg_read");
-    *p_data = p_buff[0];
-
-    return DPP_OK;
-}
+/**************************************************************
+* 版权所有 (C)2013-2015, 深圳市中兴通讯股份有限公司
+* 文件名称 : dpp_reg.c
+* 文件标识 :
+* 内容摘要 :
+* 其它说明 :
+* 当前版本 :
+* 作    者 : 王春雷
+* 完成日期 : 2014/02/12
+* DEPARTMENT: ASIC_FPGA_R&D_Dept
+* MANUAL_PERCENT: 100%
+
+* 修改记录1:
+* 修改日期:
+* 版 本 号:
+* 修 改 人:
+* 修改内容:
+***************************************************************/
+
+#include "zxic_common.h"
+#include "dpp_type_api.h"
+#include "dpp_module.h"
+#include "dpp_dev.h"
+#include "dpp_reg_api.h"
+#include "dpp_reg_info.h"
+#include "dpp_agent_channel.h"
+#include "dpp_pci.h"
+
+#define REG_DATA_MAX (512 / 32)
+
+static DPP_REG_OFFSET_ADDR g_module_offset_addr[] = {
+	{ DTB4K, BAR_4K_DTB, SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR },
+	{ STAT4K, BAR_4K_ETCAM, SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR },
+	{ PPU4K, BAR_4K_CLS0,
+	  SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4000 },
+	{ SE4K, BAR_4K_SE, SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR },
+	{ SMMU14K, BAR_4K_SMMU1,
+	  SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR }
+};
+
+/***********************************************************/
+/** 获取寄存器属性
+ * @param   reg_no  寄存器编号
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/04/17
+ ************************************************************/
+DPP_REG_T *dpp_reg_info_get(ZXIC_UINT32 reg_no)
+{
+	ZXIC_COMM_CHECK_INDEX_RETURN_NULL(reg_no, 0, REG_ENUM_MAX_VALUE - 1);
+
+	return ((DPP_REG_T *)&g_dpp_reg_info[reg_no]);
+}
+
+/***********************************************************/
+/** 根据寄存器编号获得寄存器芯片内绝对地址
+ * @param   reg_no
+ * @param   m_offset
+ * @param   n_offset
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/03/19
+ ************************************************************/
+ZXIC_UINT32 dpp_reg_get_reg_addr(ZXIC_UINT32 reg_no, ZXIC_UINT32 m_offset,
+								 ZXIC_UINT32 n_offset)
+{
+	ZXIC_UINT32 addr = 0;
+	DPP_REG_T *p_reg_info = NULL;
+
+	ZXIC_COMM_CHECK_INDEX(reg_no, 0, REG_ENUM_MAX_VALUE - 1);
+
+	p_reg_info = dpp_reg_info_get(reg_no);
+	ZXIC_COMM_CHECK_POINT(p_reg_info);
+
+	/* 计算写地址 */
+	addr = p_reg_info->addr;
+
+	if (p_reg_info->array_type & DPP_REG_UNI_ARRAY) {
+		if (n_offset > (p_reg_info->n_size - 1))
+			ZXIC_COMM_TRACE_ERROR(
+					"reg n_offset is out of range, reg_no:%d, n:%d, size:%d\n",
+					reg_no, n_offset, p_reg_info->n_size - 1);
+
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(
+				addr, n_offset * p_reg_info->n_step);
+		addr += n_offset * p_reg_info->n_step;
+	} else if (p_reg_info->array_type & DPP_REG_BIN_ARRAY) {
+		if ((n_offset > (p_reg_info->n_size - 1)) ||
+			(m_offset > (p_reg_info->m_size - 1)))
+			ZXIC_COMM_TRACE_ERROR(
+					"reg n_offset or m_offset is out of range, reg_no:%d, n:%d, n_size:%d, m:%d, m_size:%d,\n",
+					reg_no, n_offset, p_reg_info->n_size - 1, m_offset,
+					p_reg_info->m_size - 1);
+
+		ZXIC_COMM_CHECK_INDEX_MUL_OVERFLOW_NO_ASSERT(m_offset,
+													 p_reg_info->m_step);
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(
+				m_offset * p_reg_info->m_step, n_offset * p_reg_info->n_step);
+		ZXIC_COMM_CHECK_INDEX_ADD_OVERFLOW_NO_ASSERT(
+				addr,
+				m_offset * p_reg_info->m_step + n_offset * p_reg_info->n_step);
+		addr += m_offset * p_reg_info->m_step + n_offset * p_reg_info->n_step;
+	}
+
+	return addr;
+}
+
+/***********************************************************/
+/** 判断是否为4K寄存器
+ * @param   reg_module
+ *
+ * @return
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/11/29
+ ************************************************************/
+BOOLEAN dpp_4k_reg(ZXIC_UINT32 reg_module)
+{
+	if ((DTB4K <= reg_module) && (SMMU14K >= reg_module)) {
+		return ZXIC_TRUE;
+	}
+
+	return ZXIC_FALSE;
+}
+
+/***********************************************************/
+/** 获取NP对应模块的映射地址偏移(riscv或者非4K寄存器不做转换，host根据映射情况做转换)
+ * @param   dev_id
+ * @param   reg_module
+ * @param   flags  标志位，DPP_REG_FLAG_INDIRECT DPP_REG_FLAG_DIRECT
+ * @param   addr
+ *
+ * @return  映射地址
+ * @remark  无
+ * @see
+ * @author  cq      @date  2023/11/29
+ ************************************************************/
+ZXIC_UINT32 dpp_reg_addr_convert(ZXIC_UINT32 dev_id, ZXIC_UINT32 reg_module,
+								 ZXIC_UINT32 flags, ZXIC_UINT32 addr)
+{
+	ZXIC_UINT32 convert_addr = addr;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 cluster_index = 0;
+	ZXIC_UINT32 index_4k = 0;
+	ZXIC_UINT32 size_4k = 4096;
+	ZXIC_UINT32 module_addr_offset = 0;
+	ZXIC_UINT32 dtb_addr_offset = SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR;
+
+	if (DPP_REG_FLAG_INDIRECT == flags) {
+		return addr;
+	}
+
+	for (i = 0; i < sizeof(g_module_offset_addr) / sizeof(DPP_REG_OFFSET_ADDR);
+		 i++) {
+		if (reg_module == g_module_offset_addr[i].reg_module) {
+			module_addr_offset = g_module_offset_addr[i].addr_offset;
+			if (PPU4K == reg_module) {
+				cluster_index = (addr - module_addr_offset) /
+								DPP_PPU_CLUSTER_SPACE_SIZE;
+				index_4k = g_module_offset_addr[i].index_4k + cluster_index;
+				module_addr_offset +=
+						cluster_index * DPP_PPU_CLUSTER_SPACE_SIZE;
+			} else {
+				index_4k = g_module_offset_addr[i].index_4k;
+			}
+			convert_addr = ((addr + size_4k * index_4k + dtb_addr_offset) >
+							module_addr_offset) ?
+									 (addr + size_4k * index_4k +
+									dtb_addr_offset - module_addr_offset) :
+									 addr;
+		}
+	}
+
+	return convert_addr;
+}
+
+/***********************************************************/
+/** 通用寄存器写函数
+ * @param   dev_id  设备号，支持多芯片
+ * @param   reg_no 寄存器编号
+ * @param   m_offset 二元寄存器的m偏移
+ * @param   n_offset 一元寄存器或二元寄存器的n偏移
+ * @param   p_data 数据指针
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/02/12
+ ************************************************************/
+DPP_STATUS dpp_reg_write(DPP_DEV_T *dev, ZXIC_UINT32 reg_no,
+						 ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset,
+						 ZXIC_VOID *p_data)
+{
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 addr = 0;
+
+#ifdef DPP_FLOW_HW_INIT
+	ZXIC_UINT32 convert_addr = 0;
+#endif
+
+	ZXIC_UINT32 p_buff[REG_DATA_MAX] = { 0 };
+	ZXIC_UINT32 temp_data = 0;
+	ZXIC_UINT32 reg_type = 0;
+	ZXIC_UINT32 reg_module = 0;
+	ZXIC_UINT32 reg_width = 0;
+	DPP_REG_T *p_reg_info = NULL;
+	DPP_FIELD_T *p_field_info = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), reg_no, 0, REG_ENUM_MAX_VALUE - 1);
+	ZXIC_COMM_CHECK_POINT(p_data);
+
+	p_reg_info = dpp_reg_info_get(reg_no);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info);
+	p_field_info = p_reg_info->p_fields;
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_field_info);
+	reg_type = p_reg_info->flags;
+	reg_module = p_reg_info->module_no;
+	reg_width = p_reg_info->width;
+	ZXIC_COMM_CHECK_INDEX_UPPER(reg_width, REG_DATA_MAX * 4);
+
+	/* 提取各字段数据，按各字段实际bit位宽进行拼装 */
+	for (i = 0; i < p_reg_info->field_num; i++) {
+		if (p_field_info[i].len <= 32) {
+			/* lint -e64 */
+			temp_data =
+					*((ZXIC_UINT32 *)p_data + i) &
+					ZXIC_COMM_GET_BIT_MASK(ZXIC_UINT32, p_field_info[i].len);
+			rc = zxic_comm_write_bits_ex((ZXIC_UINT8 *)p_buff,
+										 p_reg_info->width * 8, temp_data,
+										 p_field_info[i].msb_pos,
+										 p_field_info[i].len);
+			/* lint +e64 */
+			ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_write_bits_ex");
+		}
+	}
+
+	ZXIC_COMM_TRACE_DEV_DEBUG(
+			DEV_ID(dev), "zxic_comm_write_bits_ex data = 0x%08x.\n", p_buff[0]);
+	/* 若host cpu为小端字节序，则以4字节为单位对数据进行字节序转换 */
+	if (!zxic_comm_is_big_endian()) {
+		for (i = 0; i < p_reg_info->width / 4; i++) {
+			p_buff[i] = ZXIC_COMM_CONVERT32(p_buff[i]);
+
+			/* for debug */
+			ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev),
+									  "ZXIC_COMM_CONVERT32 data = 0x%08x.\n",
+									  p_buff[i]);
+		}
+	}
+
+	/* 计算写地址 */
+	addr = dpp_reg_get_reg_addr(
+			reg_no, m_offset,
+			n_offset); /* 通过寄存器编号等三个参数获得寄存器的基地址 */
+
+	ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev),
+							  "reg_no = %d. m_offset = %d n_offset = %d\n",
+							  reg_no, m_offset, n_offset);
+	ZXIC_COMM_TRACE_DEV_DEBUG(DEV_ID(dev), "baseaddr = 0x%08x.\n", addr);
+
+#ifdef DPP_FLOW_HW_INIT
+	if (dpp_4k_reg(reg_module)) {
+		/* 调用寄存器写接口 */
+		convert_addr =
+				dpp_reg_addr_convert(DEV_ID(dev), reg_module, reg_type, addr);
+		ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info->p_write_fun);
+		rc = p_reg_info->p_write_fun(dev, convert_addr, p_buff);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "p_reg_info->p_write_fun");
+	}
+#else
+	if (DTB4K == reg_module) {
+		/* 调用寄存器写接口 */
+		ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info->p_write_fun);
+		rc = p_reg_info->p_write_fun(dev, addr, p_buff);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "p_reg_info->p_write_fun");
+	}
+#endif
+	else {
+		/* 调用代理通道寄存器写接口 */
+		rc = dpp_agent_channel_reg_write(dev, reg_type, reg_no, reg_width, addr,
+										 p_buff);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_agent_channel_reg_write");
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 通用寄存器读函数
+ * @param   dev_id 设备号，支持多芯片
+ * @param   reg_no 寄存器编号
+ * @param   m_offset 二元寄存器的m偏移
+ * @param   n_offset 一元寄存器或二元寄存器的n偏移
+ * @param   p_data 数据指针
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  王春雷      @date  2014/02/12
+ ************************************************************/
+DPP_STATUS dpp_reg_read(DPP_DEV_T *dev, ZXIC_UINT32 reg_no,
+						ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset,
+						ZXIC_VOID *p_data)
+{
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 addr = 0;
+#ifdef DPP_FLOW_HW_INIT
+	ZXIC_UINT32 convert_addr = 0;
+#endif
+	ZXIC_UINT32 reg_type = 0;
+	ZXIC_UINT32 p_buff[REG_DATA_MAX] = { 0 };
+	ZXIC_UINT32 reg_module = 0;
+	ZXIC_UINT32 reg_width = 0;
+	DPP_REG_T *p_reg_info = NULL;
+	DPP_FIELD_T *p_field_info = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), reg_no, 0, REG_ENUM_MAX_VALUE - 1);
+	ZXIC_COMM_CHECK_POINT(p_data);
+
+	p_reg_info = dpp_reg_info_get(reg_no);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info);
+	p_field_info = p_reg_info->p_fields;
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_field_info);
+	reg_type = p_reg_info->flags;
+	reg_module = p_reg_info->module_no;
+	reg_width = p_reg_info->width;
+	ZXIC_COMM_CHECK_INDEX_UPPER(reg_width, REG_DATA_MAX * 4);
+
+	/* 计算读地址 */
+	addr = dpp_reg_get_reg_addr(reg_no, m_offset, n_offset);
+#ifdef DPP_FLOW_HW_INIT
+	if (dpp_4k_reg(reg_module)) {
+		/* 调用寄存器读接口 */
+		convert_addr =
+				dpp_reg_addr_convert(DEV_ID(dev), reg_module, reg_type, addr);
+		ZXIC_COMM_CHECK_POINT(p_reg_info->p_read_fun);
+		rc = p_reg_info->p_read_fun(dev, convert_addr, p_buff);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "p_reg_info->p_read_fun");
+	}
+#else
+	if (DTB4K == reg_module) {
+		/* 调用寄存器读接口 */
+		ZXIC_COMM_CHECK_POINT(p_reg_info->p_read_fun);
+		rc = p_reg_info->p_read_fun(dev, addr, p_buff);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "p_reg_info->p_read_fun");
+	}
+#endif
+	else {
+		/* 调用代理通道寄存器读接口 */
+		rc = dpp_agent_channel_reg_read(dev, reg_type, reg_no, reg_width, addr,
+										p_buff);
+		ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_agent_channel_reg_read");
+	}
+
+	/* 若host cpu为小端字节序，则以4字节为单位对数据进行字节序转换 */
+	if (!zxic_comm_is_big_endian()) {
+		for (i = 0; i < p_reg_info->width / 4; i++) {
+			/* for debug */
+
+			// printf("dpp_reg_read data = 0x%08x.\n", p_buff[i]);
+			ZXIC_COMM_TRACE_DEV_DEBUG(
+					DEV_ID(dev), "dpp_reg_read data = 0x%08x.\n", p_buff[i]);
+
+			p_buff[i] = ZXIC_COMM_CONVERT32(p_buff[i]);
+		}
+	}
+
+	/* 提取各字段数据，每字段以ZXIC_UINT32形式返回 */
+	for (i = 0; i < p_reg_info->field_num; i++) {
+		/* lint -e64 */
+		rc = zxic_comm_read_bits_ex((ZXIC_UINT8 *)p_buff, p_reg_info->width * 8,
+									(ZXIC_UINT32 *)p_data + i,
+									p_field_info[i].msb_pos,
+									p_field_info[i].len);
+		ZXIC_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_read_bits_ex");
+		/* lint +e64 */
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 通过寄存器编号配置寄存器，仅适用于32bit位宽
+    的常规寄存器
+* @param   dev_id  设备号
+* @param   reg_no     寄存器编号
+* @param   data       数据，32bit
+*
+* @return  DPP_OK-成功，DPP_ERR-失败
+* @remark  无
+* @see
+* @author  XXX      @date  2019/07/10
+************************************************************/
+DPP_STATUS dpp_reg_write32(DPP_DEV_T *dev, ZXIC_UINT32 reg_no, ZXIC_UINT32 data)
+{
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 addr = 0;
+	DPP_REG_T *p_reg_info = NULL;
+	ZXIC_UINT32 value = data;
+	ZXIC_UINT32 j = 0;
+	ZXIC_UINT32 k = 0;
+	ZXIC_UINT32 m_size = 0;
+	ZXIC_UINT32 n_size = 0;
+	ZXIC_UINT32 reg_type = 0;
+	ZXIC_UINT32 reg_module = 0;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), reg_no, 0, REG_ENUM_MAX_VALUE - 1);
+
+	p_reg_info = dpp_reg_info_get(reg_no);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info);
+	reg_type = p_reg_info->flags;
+	reg_module = p_reg_info->module_no;
+
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_reg_info->width, 4,
+							  4); /* width must be 32bit */
+
+	m_size = (p_reg_info->m_size == 0) ? (1) : (p_reg_info->m_size);
+	n_size = (p_reg_info->n_size == 0) ? (1) : (p_reg_info->n_size);
+
+	/* 计算读地址 */
+	for (j = 0; j < m_size; j++) {
+		for (k = 0; k < n_size; k++) {
+			/* 计算写地址 */
+			addr = dpp_reg_get_reg_addr(reg_no, j, k);
+
+			/* 调用代理通道寄存器写接口 */
+			rc = dpp_agent_channel_reg_write(dev, reg_type, reg_no, 4, addr,
+											 &value);
+			ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc,
+								   "dpp_agent_channel_reg_write");
+		}
+	}
+
+	return DPP_OK;
+}
+
+/***********************************************************/
+/** 通过寄存器编号读取寄存器的值，仅适用于32bit位宽的常规寄存器
+ * @param   dev_id   设备号
+ * @param   reg_no   寄存器编号
+ * @param   m_offset   二元寄存器的m偏移
+ * @param   n_offset   一元寄存器或二元寄存器的n偏移
+ * @param   p_data   出参，返回读取寄存器数值
+ *
+ * @return  DPP_OK-成功，DPP_ERR-失败
+ * @remark  无
+ * @see
+ * @author  石金锋      @date  2015/03/09
+ ************************************************************/
+DPP_STATUS dpp_reg_read32(DPP_DEV_T *dev, ZXIC_UINT32 reg_no,
+						  ZXIC_UINT32 m_offset, ZXIC_UINT32 n_offset,
+						  ZXIC_UINT32 *p_data)
+{
+	DPP_STATUS rc = 0;
+	ZXIC_UINT32 addr = 0;
+	ZXIC_UINT32 reg_type = 0;
+	ZXIC_UINT32 reg_module = 0;
+	ZXIC_UINT32 p_buff[REG_DATA_MAX] = { 0 };
+
+	DPP_REG_T *p_reg_info = NULL;
+
+	ZXIC_COMM_CHECK_POINT(dev);
+	ZXIC_COMM_CHECK_INDEX_UPPER(DEV_ID(dev), DPP_DEV_CHANNEL_MAX - 1);
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), reg_no, 0, REG_ENUM_MAX_VALUE - 1);
+	ZXIC_COMM_CHECK_POINT(p_data);
+
+	p_reg_info = dpp_reg_info_get(reg_no);
+	ZXIC_COMM_CHECK_DEV_POINT(DEV_ID(dev), p_reg_info);
+	reg_type = p_reg_info->flags;
+	reg_module = p_reg_info->module_no;
+
+	ZXIC_COMM_CHECK_DEV_INDEX(DEV_ID(dev), p_reg_info->width, 4,
+							  4); /* width must be 32bit */
+	/* 计算读地址 */
+	addr = dpp_reg_get_reg_addr(reg_no, m_offset, n_offset);
+
+	/* 调用代理通道寄存器读接口 */
+	rc = dpp_agent_channel_reg_read(dev, reg_type, reg_no, 4, addr, p_buff);
+	ZXIC_COMM_CHECK_DEV_RC(DEV_ID(dev), rc, "dpp_agent_channel_reg_read");
+	*p_data = p_buff[0];
+
+	return DPP_OK;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_reg_info.c b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_reg_info.c
index 6fb5a5488c1837c5b0c8dd36d259360bf1278e2e..e4c69bb11a05cb3f99fc78c34196e585e471eba5 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_reg_info.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/sdk/source/dev/reg/dpp_reg_info.c
@@ -2,101394 +2,97906 @@
 #include "dpp_reg_struct.h"
 #include "dpp_reg_info.h"
 
-DPP_FIELD_T g_etm_cfgmt_cpu_check_reg_reg[] = 
-    {
-        {"cpu_check_reg", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_cfgmt_blksize_reg[] = 
-    {
-        {"cfgmt_blksize", DPP_FIELD_FLAG_RW, 1, 2, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_reg_int_state_reg_reg[] = 
-    {
-        {"shap_int", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"crdt_int", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"mmu_int", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"qmu_int", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"cgavd_int", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"olif_int", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"cfgmt_int_buf", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_reg_int_mask_reg_reg[] = 
-    {
-        {"shap_int_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"crdt_int_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"tmmu_int_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"qmu_int_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"cgavd_int_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"olif_int_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"cfgmt_int_buf_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_timeout_limit_reg[] = 
-    {
-        {"timeout_limit", DPP_FIELD_FLAG_RW, 15, 16, 0xfff, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_subsystem_rdy_reg_reg[] = 
-    {
-        {"olif_rdy", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"qmu_rdy", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"cgavd_rdy", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"tmmu_rdy", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"shap_rdy", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"crdt_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_subsystem_en_reg_reg[] = 
-    {
-        {"subsystem_en_buf_31_28", DPP_FIELD_FLAG_RW, 31, 4, 0x0, 0x0},
-        {"subsystem_en_buf_25_0", DPP_FIELD_FLAG_RW, 25, 26, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_cfgmt_int_reg_reg[] = 
-    {
-        {"cfgmt_int_buf", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_qmu_work_mode_reg[] = 
-    {
-        {"qmu_work_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_cfgmt_ddr_attach_reg[] = 
-    {
-        {"cfgmt_ddr_attach", DPP_FIELD_FLAG_RW, 9, 10, 0xf, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_cnt_mode_reg_reg[] = 
-    {
-        {"cfgmt_fc_count_mode", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0},
-        {"cfgmt_count_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_clkgate_en_reg[] = 
-    {
-        {"clkgate_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_softrst_en_reg[] = 
-    {
-        {"softrst_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_imem_prog_full_reg[] = 
-    {
-        {"imem_prog_full_assert", DPP_FIELD_FLAG_RW, 24, 9, 0x9c, 0x0},
-        {"imem_prog_full_negate", DPP_FIELD_FLAG_RW, 8, 9, 0x94, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_qmu_para_prog_full_reg[] = 
-    {
-        {"qmu_para_prog_full_assert", DPP_FIELD_FLAG_RW, 26, 11, 0x370, 0x0},
-        {"qmu_para_prog_full_negate", DPP_FIELD_FLAG_RW, 10, 11, 0x370, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_olif_int_mask_reg[] = 
-    {
-        {"emem_dat_sop_err_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"emem_dat_eop_err_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"imem_dat_sop_err_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"imem_dat_eop_err_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"crcram_parity_err_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"emem_fifo_ecc_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"imem_fifo_ecc_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"emem_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"emem_fifo_udf_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"imem_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"imem_fifo_udf_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"para_fifo_ecc_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"para_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"para_fifo_udf_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"itmh_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"itmh_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"order_fifo_parity_err_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"order_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"order_fifo_udf_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_itmhram_parity_err_2_int_reg[] = 
-    {
-        {"emem_dat_sop_err", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"emem_dat_eop_err", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"imem_dat_sop_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"imem_dat_eop_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"crcram_parity_err_1_int", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"emem_fifo_ecc_single_err_int", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"emem_fifo_ecc_double_err_int", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"imem_fifo_ecc_single_err_int", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"imem_fifo_ecc_double_err_int", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"emem_fifo_ovf_int", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"emem_fifo_udf_int", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"imem_fifo_ovf_int", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"imem_fifo_udf_int", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"para_fifo_ecc_single_err_int", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"para_fifo_ecc_double_err_int", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"para_fifo_ovf_int", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"para_fifo_udf_int", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"itmh_ecc_single_err_int", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"itmh_ecc_double_err_int", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"order_fifo_parity_err_int", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"order_fifo_ovf_int", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"order_fifo_udf_int", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_lif0_port_rdy_mask_h_reg[] = 
-    {
-        {"lif0_port_rdy_mask_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_lif0_port_rdy_mask_l_reg[] = 
-    {
-        {"lif0_port_rdy_mask_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_lif0_port_rdy_cfg_h_reg[] = 
-    {
-        {"lif0_port_rdy_cfg_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_lif0_port_rdy_cfg_l_reg[] = 
-    {
-        {"lif0_port_rdy_cfg_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_lif0_link_rdy_mask_cfg_reg[] = 
-    {
-        {"lif0_link_rdy_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"lif0_link_rdy_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_tm_lif_stat_cfg_reg[] = 
-    {
-        {"all_or_by_port", DPP_FIELD_FLAG_RW, 24, 1, 0x0, 0x0},
-        {"i_or_e_sel", DPP_FIELD_FLAG_RW, 17, 2, 0x0, 0x0},
-        {"port_or_dest_id_sel", DPP_FIELD_FLAG_RW, 8, 1, 0x0, 0x0},
-        {"port_dest_id", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x1},
-    };
-DPP_FIELD_T g_etm_olif_tm_lif_sop_stat_reg[] = 
-    {
-        {"tm_lif_sop_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_tm_lif_eop_stat_reg[] = 
-    {
-        {"tm_lif_eop_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_tm_lif_vld_stat_reg[] = 
-    {
-        {"tm_lif_vld_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_prog_full_assert_cfg_reg[] = 
-    {
-        {"prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 31, 16, 0xdc, 0x0},
-        {"prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 15, 16, 0xc8, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_int_reg[] = 
-    {
-        {"cgavd_int", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_ram_err_reg[] = 
-    {
-        {"flow_qnum_intb", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"flow_qnum_inta", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"pp_qlen_inta", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"pp_qlen_intb", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"pp_tdth_int", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"flow_tdth_inta", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"flow_tdth_intb", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"flow_qlen_inta", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"flow_qlen_intb", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"qmu_cgavd_fifo_uv_int", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"qmu_cgavd_fifo_ov_int", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"pds_deal_fifo_ov_int", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"pds_deal_fifo_uv_int", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_int_mask_reg[] = 
-    {
-        {"cgavd_int_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_ram_err_int_mask_reg[] = 
-    {
-        {"flow_qnum_inta_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"flow_qnum_intb_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"pp_qlen_inta_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"pp_qlen_intb_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"pp_tdth_int_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"flow_tdth_inta_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"flow_tdth_intb_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"flow_qlen_inta_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"flow_qlen_intb_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"qmu_cgavd_fifo_uv_int_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"qmu_cgavd_fifo_ov_int_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"pds_deal_fifo_ov_int_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"pds_deal_fifo_uv_int_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cfgmt_byte_mode_reg[] = 
-    {
-        {"cfgmt_byte_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_avg_qlen_return_zero_en_reg[] = 
-    {
-        {"avg_qlen_return_zero_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_wred_q_len_th_reg[] = 
-    {
-        {"flow_wred_q_len_th", DPP_FIELD_FLAG_RW, 28, 29, 0x400, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_wq_reg[] = 
-    {
-        {"wq_flow", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_wred_max_th_reg[] = 
-    {
-        {"flow_wred_max_th", DPP_FIELD_FLAG_RW, 28, 29, 0x1000, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_wred_min_th_reg[] = 
-    {
-        {"flow_wred_min_th", DPP_FIELD_FLAG_RW, 28, 29, 0x10, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_wred_cfg_para_reg[] = 
-    {
-        {"flow_wred_cfg_para", DPP_FIELD_FLAG_RW, 31, 32, 0x13ec, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_pp_avg_q_len_reg[] = 
-    {
-        {"pp_avg_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_pp_td_th_reg[] = 
-    {
-        {"pp_td_th", DPP_FIELD_FLAG_RW, 28, 29, 0x400, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_pp_ca_mtd_reg[] = 
-    {
-        {"pp_ca_mtd", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_pp_wred_grp_th_en_reg[] = 
-    {
-        {"pp_wred_grp", DPP_FIELD_FLAG_RW, 3, 3, 0x0, 0x0},
-        {"pp_wred_grp_th_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_pp_wred_q_len_th_reg[] = 
-    {
-        {"pp_wred_q_len_th", DPP_FIELD_FLAG_RW, 28, 29, 0x100000, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_pp_wq_reg[] = 
-    {
-        {"wq_pp", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_pp_wred_max_th_reg[] = 
-    {
-        {"pp_wred_max_th", DPP_FIELD_FLAG_RW, 28, 29, 0x80000, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_pp_wred_min_th_reg[] = 
-    {
-        {"pp_wred_min_th", DPP_FIELD_FLAG_RW, 28, 29, 0x800, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_pp_cfg_para_reg[] = 
-    {
-        {"pp_cfg_para", DPP_FIELD_FLAG_RW, 31, 32, 0x9f600, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_sys_avg_q_len_reg[] = 
-    {
-        {"sys_avg_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_sys_td_th_reg[] = 
-    {
-        {"sys_td_th", DPP_FIELD_FLAG_RW, 28, 29, 0x1ff00, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_sys_cgavd_metd_reg[] = 
-    {
-        {"sys_cgavd_metd", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_sys_cfg_q_grp_para_reg[] = 
-    {
-        {"gred_q_len_th_sys", DPP_FIELD_FLAG_RW, 28, 29, 0x1fffe00, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_sys_wq_reg[] = 
-    {
-        {"wq_sys", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_gred_max_th_reg[] = 
-    {
-        {"gred_max_th", DPP_FIELD_FLAG_RW, 28, 29, 0x1000000, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_gred_mid_th_reg[] = 
-    {
-        {"gred_mid_th", DPP_FIELD_FLAG_RW, 28, 29, 0x600000, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_gred_min_th_reg[] = 
-    {
-        {"gred_min_th", DPP_FIELD_FLAG_RW, 28, 29, 0x80000, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_gred_cfg_para0_reg[] = 
-    {
-        {"gred_cfg_para0", DPP_FIELD_FLAG_RW, 31, 32, 0x92aaaa, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_gred_cfg_para1_reg[] = 
-    {
-        {"gred_cfg_para1", DPP_FIELD_FLAG_RW, 31, 32, 0x1900000, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_gred_cfg_para2_reg[] = 
-    {
-        {"gred_cfg_para2", DPP_FIELD_FLAG_RW, 31, 32, 0xf00000, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_sys_window_th_h_reg[] = 
-    {
-        {"sys_window_th_h", DPP_FIELD_FLAG_RW, 28, 29, 0x1d00000, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_sys_window_th_l_reg[] = 
-    {
-        {"sys_window_th_l", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_amplify_gene0_reg[] = 
-    {
-        {"amplify_gene0", DPP_FIELD_FLAG_RW, 11, 12, 0x200, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_amplify_gene1_reg[] = 
-    {
-        {"amplify_gene1", DPP_FIELD_FLAG_RW, 11, 12, 0x82, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_amplify_gene2_reg[] = 
-    {
-        {"amplify_gene2", DPP_FIELD_FLAG_RW, 11, 12, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_amplify_gene3_reg[] = 
-    {
-        {"amplify_gene3", DPP_FIELD_FLAG_RW, 11, 12, 0x7e, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_amplify_gene4_reg[] = 
-    {
-        {"amplify_gene4", DPP_FIELD_FLAG_RW, 11, 12, 0x7c, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_amplify_gene5_reg[] = 
-    {
-        {"amplify_gene5", DPP_FIELD_FLAG_RW, 11, 12, 0x78, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_amplify_gene6_reg[] = 
-    {
-        {"amplify_gene6", DPP_FIELD_FLAG_RW, 11, 12, 0x70, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_amplify_gene7_reg[] = 
-    {
-        {"amplify_gene7", DPP_FIELD_FLAG_RW, 11, 12, 0x68, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_amplify_gene8_reg[] = 
-    {
-        {"amplify_gene8", DPP_FIELD_FLAG_RW, 11, 12, 0x60, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_amplify_gene9_reg[] = 
-    {
-        {"amplify_gene9", DPP_FIELD_FLAG_RW, 11, 12, 0x58, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_amplify_gene10_reg[] = 
-    {
-        {"amplify_gene10", DPP_FIELD_FLAG_RW, 11, 12, 0x50, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_amplify_gene11_reg[] = 
-    {
-        {"amplify_gene11", DPP_FIELD_FLAG_RW, 11, 12, 0x40, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_amplify_gene12_reg[] = 
-    {
-        {"amplify_gene12", DPP_FIELD_FLAG_RW, 11, 12, 0x20, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_amplify_gene13_reg[] = 
-    {
-        {"amplify_gene13", DPP_FIELD_FLAG_RW, 11, 12, 0x8, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_amplify_gene14_reg[] = 
-    {
-        {"amplify_gene14", DPP_FIELD_FLAG_RW, 11, 12, 0x2, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_amplify_gene15_reg[] = 
-    {
-        {"amplify_gene15", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_equal_pkt_len_en_reg[] = 
-    {
-        {"equal_pkt_len_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th0_reg[] = 
-    {
-        {"equal_pkt_len_th0", DPP_FIELD_FLAG_RW, 14, 15, 0x4, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th1_reg[] = 
-    {
-        {"equal_pkt_len_th1", DPP_FIELD_FLAG_RW, 14, 15, 0x8, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th2_reg[] = 
-    {
-        {"equal_pkt_len_th2", DPP_FIELD_FLAG_RW, 14, 15, 0x10, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th3_reg[] = 
-    {
-        {"equal_pkt_len_th3", DPP_FIELD_FLAG_RW, 14, 15, 0x18, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th4_reg[] = 
-    {
-        {"equal_pkt_len_th4", DPP_FIELD_FLAG_RW, 14, 15, 0x20, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th5_reg[] = 
-    {
-        {"equal_pkt_len_th5", DPP_FIELD_FLAG_RW, 14, 15, 0x40, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th6_reg[] = 
-    {
-        {"equal_pkt_len_th6", DPP_FIELD_FLAG_RW, 14, 15, 0x60, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_equal_pkt_len0_reg[] = 
-    {
-        {"equal_pkt_len0", DPP_FIELD_FLAG_RW, 14, 15, 0x20, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_equal_pkt_len1_reg[] = 
-    {
-        {"equal_pkt_len1", DPP_FIELD_FLAG_RW, 14, 15, 0x30, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_equal_pkt_len2_reg[] = 
-    {
-        {"equal_pkt_len2", DPP_FIELD_FLAG_RW, 14, 15, 0x40, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_equal_pkt_len3_reg[] = 
-    {
-        {"equal_pkt_len3", DPP_FIELD_FLAG_RW, 14, 15, 0x50, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_equal_pkt_len4_reg[] = 
-    {
-        {"equal_pkt_len4", DPP_FIELD_FLAG_RW, 14, 15, 0x60, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_equal_pkt_len5_reg[] = 
-    {
-        {"equal_pkt_len5", DPP_FIELD_FLAG_RW, 14, 15, 0x70, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_equal_pkt_len6_reg[] = 
-    {
-        {"equal_pkt_len6", DPP_FIELD_FLAG_RW, 14, 15, 0x78, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_equal_pkt_len7_reg[] = 
-    {
-        {"equal_pkt_len7", DPP_FIELD_FLAG_RW, 14, 15, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_cpu_set_avg_len_reg[] = 
-    {
-        {"flow_cpu_set_avg_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_cpu_set_q_len_reg[] = 
-    {
-        {"flow_cpu_set_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_pp_cpu_set_avg_q_len_reg[] = 
-    {
-        {"pp_cpu_set_avg_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_pp_cpu_set_q_len_reg[] = 
-    {
-        {"pp_cpu_set_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_sys_cpu_set_avg_len_reg[] = 
-    {
-        {"sys_cpu_set_avg_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_sys_cpu_set_q_len_reg[] = 
-    {
-        {"sys_cpu_set_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_pke_len_calc_sign_reg[] = 
-    {
-        {"pke_len_calc_sign", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_rd_cpu_or_ram_reg[] = 
-    {
-        {"cpu_sel_sys_q_len_en", DPP_FIELD_FLAG_RW, 5, 1, 0x0, 0x0},
-        {"cpu_sel_sys_avg_q_len_en", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0},
-        {"cpu_sel_pp_q_len_en", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0},
-        {"cpu_sel_pp_avg_q_len_en", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0},
-        {"cpu_sel_flow_q_len_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"cpu_sel_flow_avg_q_len_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_q_len_update_disable_reg[] = 
-    {
-        {"q_len_sys_update_en", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0},
-        {"q_len_pp_update_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"q_len_flow_update_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_dp_sel_reg[] = 
-    {
-        {"flow_dp_sel_high", DPP_FIELD_FLAG_RW, 8, 1, 0x0, 0x0},
-        {"flow_dp_sel_mid", DPP_FIELD_FLAG_RW, 7, 1, 0x0, 0x0},
-        {"flow_dp_sel_low", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"pp_dp_sel_high", DPP_FIELD_FLAG_RW, 5, 1, 0x0, 0x0},
-        {"pp_dp_sel_mid", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0},
-        {"pp_dp_sel_low", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"sys_dp_sel_high", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0},
-        {"sys_dp_sel_mid", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"sys_dp_sel_low", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_sub_en_reg[] = 
-    {
-        {"cgavd_sa_sub_en", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0},
-        {"cgavd_sys_sub_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"cgavd_pp_sub_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"cgavd_flow_sub_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_default_start_queue_reg[] = 
-    {
-        {"default_start_queue", DPP_FIELD_FLAG_RW, 13, 14, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_default_finish_queue_reg[] = 
-    {
-        {"default_finish_queue", DPP_FIELD_FLAG_RW, 13, 14, 0x1ff, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_protocol_start_queue_reg[] = 
-    {
-        {"protocol_start_queue", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_protocol_finish_queue_reg[] = 
-    {
-        {"protocol_finish_queue", DPP_FIELD_FLAG_RW, 13, 14, 0xff, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_uniform_td_th_reg[] = 
-    {
-        {"uniform_td_th", DPP_FIELD_FLAG_RW, 28, 29, 0x200, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_uniform_td_th_en_reg[] = 
-    {
-        {"uniform_td_th_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_cfg_fc_reg[] = 
-    {
-        {"cgavd_cfg_fc", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_cfg_no_fc_reg[] = 
-    {
-        {"cgavd_cfg_no_fc", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_force_imem_omem_reg[] = 
-    {
-        {"imem_omem_force_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"choose_imem_omem", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_sys_q_len_l_reg[] = 
-    {
-        {"cgavd_sys_q_len_l", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_default_queue_en_reg[] = 
-    {
-        {"default_queue_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_protocol_queue_en_reg[] = 
-    {
-        {"protocol_queue_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cfg_tc_flowid_dat_reg[] = 
-    {
-        {"cfg_tc_flowid_dat", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_td_th_reg[] = 
-    {
-        {"flow_td_th", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_ca_mtd_reg[] = 
-    {
-        {"flow_ca_mtd", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_dynamic_th_en_reg[] = 
-    {
-        {"flow_dynamic_th_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_pp_num_reg[] = 
-    {
-        {"pp_num", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_q_len_reg[] = 
-    {
-        {"flow_q_len", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_wred_grp_reg[] = 
-    {
-        {"flow_wred_grp", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_avg_q_len_reg[] = 
-    {
-        {"flow_avg_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_qos_sign_reg[] = 
-    {
-        {"qos_sign_flow_cfg_din", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_q_pri_reg[] = 
-    {
-        {"qpri_flow_cfg_din", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_odma_tm_itmd_rd_low_reg[] = 
-    {
-        {"odma_tm_itmd_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_odma_tm_itmd_rd_mid_reg[] = 
-    {
-        {"odma_tm_itmd_mid", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_odma_tm_itmd_rd_high_reg[] = 
-    {
-        {"odma_tm_itmd_high", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_stat_pkt_len_reg[] = 
-    {
-        {"expect_deq_pkt_len", DPP_FIELD_FLAG_RW, 25, 10, 0x0, 0x0},
-        {"expect_enq_pkt_len", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_stat_qnum_reg[] = 
-    {
-        {"cgavd_unexcept_qnum", DPP_FIELD_FLAG_RW, 29, 14, 0x0, 0x0},
-        {"cgavd_except_qnum", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_stat_dp_reg[] = 
-    {
-        {"cgavd_stat_dp", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_num0_reg[] = 
-    {
-        {"flow_num0", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_num1_reg[] = 
-    {
-        {"flow_num1", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_num2_reg[] = 
-    {
-        {"flow_num2", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_num3_reg[] = 
-    {
-        {"flow_num3", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow_num4_reg[] = 
-    {
-        {"flow_num4", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow0_imem_cnt_reg[] = 
-    {
-        {"flow0_imem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow1_imem_cnt_reg[] = 
-    {
-        {"flow1_imem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow2_imem_cnt_reg[] = 
-    {
-        {"flow2_imem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow3_imem_cnt_reg[] = 
-    {
-        {"flow3_imem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow4_imem_cnt_reg[] = 
-    {
-        {"flow4_imem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow0_drop_cnt_reg[] = 
-    {
-        {"flow0_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow1_drop_cnt_reg[] = 
-    {
-        {"flow1_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow2_drop_cnt_reg[] = 
-    {
-        {"flow2_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow3_drop_cnt_reg[] = 
-    {
-        {"flow3_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow4_drop_cnt_reg[] = 
-    {
-        {"flow4_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_fc_count_mode_reg[] = 
-    {
-        {"fc_count_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_qmu_cgavd_fc_num_reg[] = 
-    {
-        {"qmu_cgavd_fc_state", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0},
-        {"qmu_cgavd_fc_num", DPP_FIELD_FLAG_RO, 30, 31, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_odma_fc_num_reg[] = 
-    {
-        {"cgavd_lif_fc_state", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0},
-        {"cgavd_lif_fc_num", DPP_FIELD_FLAG_RO, 30, 31, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cfg_offset_reg[] = 
-    {
-        {"cfg_offset", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_init_done_reg[] = 
-    {
-        {"tmmu_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_int_mask_1_reg[] = 
-    {
-        {"imem_enq_rd_fifo_full_mask", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"imem_enq_rd_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"imem_enq_rd_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"imem_enq_drop_fifo_full_mask", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"imem_enq_drop_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"imem_enq_drop_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"imem_deq_rd_fifo_full_mask", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"imem_deq_rd_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"imem_deq_rd_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"imem_deq_drop_fifo_full_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"imem_deq_drop_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"imem_deq_drop_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"dma_data_fifo_full_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"dma_data_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"dma_data_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"wr_cmd_fifo_full_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"wr_cmd_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"wr_cmd_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"cached_pd_fifo_full_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"cached_pd_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"cached_pd_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"emem_pd_fifo_full_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"emem_pd_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"emem_pd_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"pd_order_fifo_full_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"pd_order_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"pd_order_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_int_mask_2_reg[] = 
-    {
-        {"dma_data_fifo_parity_err_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"imem_enq_rd_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"imem_enq_rd_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"imem_enq_drop_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"imem_enq_drop_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"imem_deq_rd_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"imem_deq_rd_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"imem_deq_drop_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"imem_deq_drop_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"wr_cmd_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"wr_cmd_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"pd_cache_ram_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"pd_cache_ram_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"cached_pd_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"cached_pd_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"emem_pd_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"emem_pd_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_tm_pure_imem_en_reg[] = 
-    {
-        {"cfgmt_tm_pure_imem_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_force_ddr_rdy_cfg_reg[] = 
-    {
-        {"cfgmt_force_ddr_rdy_cfg", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_pd_order_fifo_aful_th_reg[] = 
-    {
-        {"pd_order_fifo_aful_th", DPP_FIELD_FLAG_RW, 10, 11, 0x384, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cached_pd_fifo_aful_th_reg[] = 
-    {
-        {"cached_pd_fifo_aful_th", DPP_FIELD_FLAG_RW, 9, 10, 0x1f0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_wr_cmd_fifo_aful_th_reg[] = 
-    {
-        {"wr_cmd_fifo_aful_th", DPP_FIELD_FLAG_RW, 9, 10, 0x190, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_imem_enq_rd_fifo_aful_th_reg[] = 
-    {
-        {"imem_enq_rd_fifo_aful_th", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_imem_enq_drop_fifo_aful_th_reg[] = 
-    {
-        {"imem_enq_drop_fifo_aful_th", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_imem_deq_drop_fifo_aful_th_reg[] = 
-    {
-        {"imem_deq_drop_fifo_aful_th", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_imem_deq_rd_fifo_aful_th_reg[] = 
-    {
-        {"imem_deq_rd_fifo_aful_th", DPP_FIELD_FLAG_RW, 10, 11, 0x320, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_states_1_reg[] = 
-    {
-        {"imem_enq_rd_fifo_full", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"imem_enq_rd_fifo_overflow", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"imem_enq_rd_fifo_underflow", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"imem_enq_drop_fifo_full", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"imem_enq_drop_fifo_overflow", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"imem_enq_drop_fifo_underflow", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"imem_deq_rd_fifo_full", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"imem_deq_rd_fifo_overflow", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"imem_deq_rd_fifo_underflow", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"imem_deq_drop_fifo_full", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"imem_deq_drop_fifo_overflow", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"imem_deq_drop_fifo_underflow", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"dma_data_fifo_full", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"dma_data_fifo_overflow", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"dma_data_fifo_underflow", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"wr_cmd_fifo_full", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"wr_cmd_fifo_overflow", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"wr_cmd_fifo_underflow", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"cached_pd_fifo_full", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"cached_pd_fifo_overflow", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"cached_pd_fifo_underflow", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"emem_pd_fifo_full", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"emem_pd_fifo_overflow", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"emem_pd_fifo_underflow", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"pd_order_fifo_full", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"pd_order_fifo_overflow", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"pd_order_fifo_underflow", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_states_2_reg[] = 
-    {
-        {"dma_data_fifo_parity_err", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"imem_enq_rd_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"imem_enq_rd_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"imem_enq_drop_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"imem_enq_drop_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"imem_deq_rd_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"imem_deq_rd_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"imem_deq_drop_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"imem_deq_drop_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"wr_cmd_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"wr_cmd_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"pd_cache_ram_ecc_single_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"pd_cache_ram_ecc_double_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"cached_pd_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"cached_pd_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"emem_pd_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"emem_pd_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_shap_ind_cmd_reg[] = 
-    {
-        {"rd", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0},
-        {"mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0},
-        {"addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_shap_ind_sta_reg[] = 
-    {
-        {"indirectaccessdone", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_shap_ind_data0_reg[] = 
-    {
-        {"indirectdata0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_shap_ind_data1_reg[] = 
-    {
-        {"indirectdata1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_full_threshold_reg[] = 
-    {
-        {"full_threshold", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_empty_threshold_reg[] = 
-    {
-        {"empty_threshold", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_shap_sta_init_cfg_reg[] = 
-    {
-        {"sta_ram_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"sta_ram_init_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_shap_cfg_init_cfg_reg[] = 
-    {
-        {"cfg_ram_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"cfg_ram_init_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_token_mode_switch_reg[] = 
-    {
-        {"token_mode_switch", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_token_grain_reg[] = 
-    {
-        {"token_grain", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_crd_grain_reg[] = 
-    {
-        {"crd_grain", DPP_FIELD_FLAG_RW, 20, 21, 0x8fc, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_shap_stat_ctrl_reg[] = 
-    {
-        {"shap_stat_ctrl", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_token_stat_id_reg[] = 
-    {
-        {"token_stat_id", DPP_FIELD_FLAG_RW, 10, 11, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_token_stat_reg[] = 
-    {
-        {"token_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_shap_stat_clk_cnt_reg[] = 
-    {
-        {"shap_stat_clk_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_shap_bucket_map_tbl_reg[] = 
-    {
-        {"shap_map", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_bkt_para_tbl_reg[] = 
-    {
-        {"bucket_depth", DPP_FIELD_FLAG_RW, 35, 11, 0x0, 0x0},
-        {"bucket_rate", DPP_FIELD_FLAG_RW, 24, 25, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_credit_en_reg[] = 
-    {
-        {"credit_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crt_inter1_reg[] = 
-    {
-        {"crd_inter1", DPP_FIELD_FLAG_RW, 8, 9, 0x2d, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_db_token_reg[] = 
-    {
-        {"db_token", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crs_flt_cfg_reg[] = 
-    {
-        {"crs_flt_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_th_sp_reg[] = 
-    {
-        {"th_sp", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_th_wfq_fq_reg[] = 
-    {
-        {"th_fq", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0},
-        {"th_wfq", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_th_wfq2_fq2_reg[] = 
-    {
-        {"th_fq2", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0},
-        {"th_wfq2", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_th_wfq4_fq4_reg[] = 
-    {
-        {"th_fq4", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0},
-        {"th_wfq4", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_cfg_state_reg[] = 
-    {
-        {"cfg_state", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_ind_cmd_reg[] = 
-    {
-        {"rd", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0},
-        {"mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0},
-        {"addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_ind_sta_reg[] = 
-    {
-        {"indirectaccessdone", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_ind_data0_reg[] = 
-    {
-        {"indirectdata0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_ind_data1_reg[] = 
-    {
-        {"indirectdata1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_state_reg[] = 
-    {
-        {"crdt_int", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"crdt_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_id_0_reg[] = 
-    {
-        {"stat_que_id_0", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_id_1_reg[] = 
-    {
-        {"stat_que_id_1", DPP_FIELD_FLAG_RW, 13, 14, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_id_2_reg[] = 
-    {
-        {"stat_que_id_2", DPP_FIELD_FLAG_RW, 13, 14, 0x2, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_id_3_reg[] = 
-    {
-        {"stat_que_id_3", DPP_FIELD_FLAG_RW, 13, 14, 0x3, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_id_4_reg[] = 
-    {
-        {"stat_que_id_4", DPP_FIELD_FLAG_RW, 13, 14, 0x4, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_id_5_reg[] = 
-    {
-        {"stat_que_id_5", DPP_FIELD_FLAG_RW, 13, 14, 0x5, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_id_6_reg[] = 
-    {
-        {"stat_que_id_6", DPP_FIELD_FLAG_RW, 13, 14, 0x6, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_id_7_reg[] = 
-    {
-        {"stat_que_id_7", DPP_FIELD_FLAG_RW, 13, 14, 0x7, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_id_8_reg[] = 
-    {
-        {"stat_que_id_8", DPP_FIELD_FLAG_RW, 13, 14, 0x8, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_id_9_reg[] = 
-    {
-        {"stat_que_id_9", DPP_FIELD_FLAG_RW, 13, 14, 0x9, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_id_10_reg[] = 
-    {
-        {"stat_que_id_10", DPP_FIELD_FLAG_RW, 13, 14, 0xa, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_id_11_reg[] = 
-    {
-        {"stat_que_id_11", DPP_FIELD_FLAG_RW, 13, 14, 0xb, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_id_12_reg[] = 
-    {
-        {"stat_que_id_12", DPP_FIELD_FLAG_RW, 13, 14, 0xc, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_id_13_reg[] = 
-    {
-        {"stat_que_id_13", DPP_FIELD_FLAG_RW, 13, 14, 0xd, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_id_14_reg[] = 
-    {
-        {"stat_que_id_14", DPP_FIELD_FLAG_RW, 13, 14, 0xe, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_id_15_reg[] = 
-    {
-        {"stat_que_id_15", DPP_FIELD_FLAG_RW, 13, 14, 0xf, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_credit_reg[] = 
-    {
-        {"stat_que_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_cfg_ram_init_reg[] = 
-    {
-        {"cfg_ram_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"cfg_ram_init_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_sta_ram_init_reg[] = 
-    {
-        {"sta_ram_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"sta_ram_init_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crs_que_id_reg[] = 
-    {
-        {"crs_que_id", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_qmu_crs_end_state_reg[] = 
-    {
-        {"qmu_crs_end_state", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_shap_rdy_reg[] = 
-    {
-        {"shap_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_shap_int_reg_reg[] = 
-    {
-        {"pp_c_token_min_int", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_shap_int_mask_reg_reg[] = 
-    {
-        {"pp_c_token_min_int_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_token_state_almost_empty_th_reg[] = 
-    {
-        {"token_state_almost_empty_th", DPP_FIELD_FLAG_RW, 16, 17, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_token_state_empty_th_reg[] = 
-    {
-        {"token_state_empty_th", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_full_th_reg[] = 
-    {
-        {"token_state_full_th", DPP_FIELD_FLAG_RW, 16, 17, 0x2, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_pp_c_level_shap_en_reg[] = 
-    {
-        {"pp_c_level_shap_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_enq_token_th_reg[] = 
-    {
-        {"enq_token_th", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_pp_tokenq_level1_qstate_weight_cir_reg[] = 
-    {
-        {"pp_pp_q_state_cir", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0},
-        {"pp_pp_q_weight_wfq_l1_cir", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_pp_idle_weight_level1_cir_reg[] = 
-    {
-        {"pp_idle_q_weight_wfq_l1_cir", DPP_FIELD_FLAG_RO, 25, 26, 0x1ffffff, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_rci_grade_th_0_cfg_reg[] = 
-    {
-        {"rci_grade_th_0_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x177, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_rci_grade_th_1_cfg_reg[] = 
-    {
-        {"rci_grade_th_1_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x2ee, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_rci_grade_th_2_cfg_reg[] = 
-    {
-        {"rci_grade_th_2_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x465, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_rci_grade_th_3_cfg_reg[] = 
-    {
-        {"rci_grade_th_3_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x47e, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_rci_grade_th_4_cfg_reg[] = 
-    {
-        {"rci_grade_th_4_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x753, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_rci_grade_th_5_cfg_reg[] = 
-    {
-        {"rci_grade_th_5_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x8ca, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_rci_grade_th_6_cfg_reg[] = 
-    {
-        {"rci_grade_th_6_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0xa41, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_flow_del_cmd_reg[] = 
-    {
-        {"flow_del_busy", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0},
-        {"flow_alt_cmd", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"flow_alt_ind", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_cnt_clr_reg[] = 
-    {
-        {"cnt_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_int_bus_reg[] = 
-    {
-        {"ldstr_fifo15_ovf_int", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0},
-        {"ldstr_fifo14_ovf_int", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0},
-        {"ldstr_fifo13_ovf_int", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0},
-        {"ldstr_fifo12_ovf_int", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0},
-        {"ldstr_fifo11_ovf_int", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0},
-        {"ldstr_fifo10_ovf_int", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0},
-        {"ldstr_fifo9_ovf_int", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0},
-        {"ldstr_fifo8_ovf_int", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0},
-        {"ldstr_fifo7_ovf_int", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0},
-        {"ldstr_fifo6_ovf_int", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0},
-        {"ldstr_fifo5_ovf_int", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0},
-        {"ldstr_fifo4_ovf_int", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0},
-        {"ldstr_fifo3_ovf_int", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0},
-        {"ldstr_fifo2_ovf_int", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0},
-        {"ldstr_fifo1_ovf_int", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0},
-        {"ldstr_fifo0_ovf_int", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0},
-        {"cfg_del_err_int", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"flwin_secrs_fifo_ovf_int", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"flwin_voqcrs_fifo_ovf_int", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_int_mask_reg[] = 
-    {
-        {"crdt_int_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_cfg_weight_together_reg[] = 
-    {
-        {"cfg_weight_together", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_weight_reg[] = 
-    {
-        {"c_weight", DPP_FIELD_FLAG_RW, 22, 7, 0x0, 0x0},
-        {"e_weight", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_dev_sp_state_reg[] = 
-    {
-        {"dev_sp_state", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_dev_crs_reg[] = 
-    {
-        {"dev_crs", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_congest_token_disable_31_0_reg[] = 
-    {
-        {"congest_token_disable_31_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_congest_token_disable_63_32_reg[] = 
-    {
-        {"congest_token_disable_63_32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_interval_en_cfg_reg[] = 
-    {
-        {"crdt_interval_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_q_token_staue_cfg_reg[] = 
-    {
-        {"test_token_q_id", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_q_token_dist_cnt_reg[] = 
-    {
-        {"q_token_dist_counter", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_q_token_dec_cnt_reg[] = 
-    {
-        {"q_token_dec_counter", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_pp_weight_ram_reg[] = 
-    {
-        {"pp_c_weight", DPP_FIELD_FLAG_RW, 25, 26, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_pp_cbs_shape_en_ram_reg[] = 
-    {
-        {"pp_cbs", DPP_FIELD_FLAG_RW, 17, 17, 0x0, 0x0},
-        {"pp_c_shap_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_pp_next_pc_q_state_ram_reg[] = 
-    {
-        {"pp_next_pc", DPP_FIELD_FLAG_RO, 24, 6, 0x0, 0x0},
-        {"pp_token_num", DPP_FIELD_FLAG_RO, 18, 18, 0x20000, 0x0},
-        {"pp_q_state", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_dev_interval_reg[] = 
-    {
-        {"dev_interval", DPP_FIELD_FLAG_RW, 21, 22, 0xf, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_dev_wfq_cnt_reg[] = 
-    {
-        {"dev_wfq_cnt", DPP_FIELD_FLAG_RO, 6, 7, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_dev_wfq_state_reg[] = 
-    {
-        {"dev_wfq_state", DPP_FIELD_FLAG_RO, 6, 7, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_dev_active_head_ptr_reg[] = 
-    {
-        {"dev_active_head_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_dev_active_tail_ptr_reg[] = 
-    {
-        {"dev_active_tail_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_dev_unactive_head_ptr_reg[] = 
-    {
-        {"dev_unactive_head_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_dev_unactive_tail_ptr_reg[] = 
-    {
-        {"dev_unactive_tail_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_pp_weight_reg[] = 
-    {
-        {"pp_weight", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_pp_que_state_reg[] = 
-    {
-        {"pp_enque_flag", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0},
-        {"pp_cir", DPP_FIELD_FLAG_RO, 15, 2, 0x2, 0x0},
-        {"pp_congest_cir", DPP_FIELD_FLAG_RO, 13, 2, 0x0, 0x0},
-        {"pp_crs", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0},
-        {"dev_sp", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_pp_next_ptr_reg[] = 
-    {
-        {"pp_next_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_pp_cfg_reg[] = 
-    {
-        {"pp_cfg", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_pp_up_ptr_reg[] = 
-    {
-        {"pp_up_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_credit_drop_num_reg[] = 
-    {
-        {"credit_drop_num", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_se_id_lv0_reg[] = 
-    {
-        {"se_id_out_lv0", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_se_id_lv1_reg[] = 
-    {
-        {"se_id_out_lv1", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_se_id_lv2_reg[] = 
-    {
-        {"se_id_out_lv2", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_se_id_lv3_reg[] = 
-    {
-        {"se_id_out_lv3", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_se_id_lv4_reg[] = 
-    {
-        {"se_id_out_lv4", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_que_id_reg[] = 
-    {
-        {"que_id_out", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_se_info_lv0_reg[] = 
-    {
-        {"se_shape_lv0", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0},
-        {"se_ins_out_lv0", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0},
-        {"se_state_out_lv0", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0},
-        {"se_new_state_out_lv0", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_se_info_lv1_reg[] = 
-    {
-        {"se_shape_lv1", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0},
-        {"se_ins_out_lv1", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0},
-        {"se_state_out_lv1", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0},
-        {"se_new_state_out_lv1", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_se_info_lv2_reg[] = 
-    {
-        {"se_shape_lv2", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0},
-        {"se_ins_out_lv2", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0},
-        {"se_state_out_lv2", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0},
-        {"se_new_state_out_lv2", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_se_info_lv3_reg[] = 
-    {
-        {"se_shape_lv3", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0},
-        {"se_ins_out_lv3", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0},
-        {"se_state_out_lv3", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0},
-        {"se_new_state_out_lv3", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_se_info_lv4_reg[] = 
-    {
-        {"se_shape_lv4", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0},
-        {"se_ins_out_lv4", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0},
-        {"se_state_out_lv4", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0},
-        {"se_new_state_out_lv4", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_que_state_reg[] = 
-    {
-        {"que_state_out", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_eir_off_in_advance_reg[] = 
-    {
-        {"eir_crs_filter", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_double_level_shap_prevent_reg[] = 
-    {
-        {"double_level_shap_prevent", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_add_store_cycle_reg[] = 
-    {
-        {"add_store_cycle", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_tflag2_wr_flag_sum_reg[] = 
-    {
-        {"tflag2_wr_flag_sum", DPP_FIELD_FLAG_RO, 4, 5, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_flowque_para_tbl_reg[] = 
-    {
-        {"flowque_link", DPP_FIELD_FLAG_RW, 30, 15, 0x7fff, 0x0},
-        {"flowque_w", DPP_FIELD_FLAG_RW, 14, 11, 0x0, 0x0},
-        {"flowque_pri", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_se_para_tbl_reg[] = 
-    {
-        {"se_insw", DPP_FIELD_FLAG_RW, 33, 1, 0x0, 0x0},
-        {"se_link", DPP_FIELD_FLAG_RW, 30, 15, 0x7fff, 0x0},
-        {"cp_token_en", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0},
-        {"se_w", DPP_FIELD_FLAG_RW, 14, 11, 0x0, 0x0},
-        {"se_pri", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_flowque_ins_tbl_reg[] = 
-    {
-        {"flowque_ins", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_se_ins_tbl_reg[] = 
-    {
-        {"se_ins_flag", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"se_ins_priority", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_eir_crs_filter_tbl_reg[] = 
-    {
-        {"eir_crs_filter", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_cfg_done_reg[] = 
-    {
-        {"qcfg_qlist_cfg_done", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qsch_credit_value_reg[] = 
-    {
-        {"qcfg_qsch_credit_value", DPP_FIELD_FLAG_RW, 13, 14, 0x8fc, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qsch_crbal_init_value_reg[] = 
-    {
-        {"qcfg_qsch_crbal_init_value", DPP_FIELD_FLAG_RW, 16, 17, 0xff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qsch_crbal_init_mask_reg[] = 
-    {
-        {"qcfg_qsch_crbal_init_mask", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cmdsch_rd_cmd_aful_th_reg[] = 
-    {
-        {"cmdsch_rd_cmd_aful_th", DPP_FIELD_FLAG_RW, 9, 10, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_port_fc_interval_reg[] = 
-    {
-        {"cfg_port_fc_interval", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_csch_aged_cfg_reg[] = 
-    {
-        {"qcfg_csch_aged_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_csch_aged_scan_time_reg[] = 
-    {
-        {"qcfg_csch_aged_scan_time", DPP_FIELD_FLAG_RW, 31, 32, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qmu_qlist_state_query_reg[] = 
-    {
-        {"pkt_age_req_fifo_afull", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0},
-        {"rd_release_fwft_afull", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0},
-        {"drop_imem_fwft_afull", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0},
-        {"pkt_age_req_fifo_empty", DPP_FIELD_FLAG_RO, 24, 1, 0x1, 0x0},
-        {"rd_release_fwft_empty", DPP_FIELD_FLAG_RO, 23, 1, 0x1, 0x0},
-        {"drop_imem_fwft_empty", DPP_FIELD_FLAG_RO, 22, 1, 0x1, 0x0},
-        {"mmu_qmu_sop_rd_rdy", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0},
-        {"big_fifo_empty", DPP_FIELD_FLAG_RO, 20, 1, 0x1, 0x0},
-        {"qmu_mmu_rd_release_rdy", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0},
-        {"xsw_qmu_crs_rdy", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0},
-        {"mmu_qmu_rdy", DPP_FIELD_FLAG_RO, 17, 10, 0x0, 0x0},
-        {"mmu_ql_wr_rdy", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"mmu_ql_rd_rdy", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"csw_ql_rdy", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"ql_init_done", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"free_addr_ready", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"bank_group_afull", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"pds_fwft_empty", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0},
-        {"enq_rpt_fwft_afull", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qsch_crbal_drop_en_reg[] = 
-    {
-        {"cfgmt_qsch_all_crbal_drop_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"cfgmt_qsch_crbal_drop_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_wlist_qnum_fifo_aful_th_reg[] = 
-    {
-        {"cfgmt_wlist_qnum_fifo_aful_th", DPP_FIELD_FLAG_RW, 3, 4, 0x4, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_csw_pkt_blk_mode_reg[] = 
-    {
-        {"qcfg_csw_pkt_blk_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_ram_init_cancel_reg[] = 
-    {
-        {"qcfg_qlist_ram_init_cancel", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qsch_crbal_transfer_mode_reg[] = 
-    {
-        {"qcfg_qsch_crbal_transfer_mode", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0},
-        {"qcfg_qsch_crbal_transfer_value", DPP_FIELD_FLAG_RW, 15, 16, 0x3e8, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_qclr_interval_reg[] = 
-    {
-        {"qcfg_qlist_qclr_interval", DPP_FIELD_FLAG_RW, 31, 32, 0x400, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qsch_qclr_rate_reg[] = 
-    {
-        {"qcfg_qsch_qclr_rate", DPP_FIELD_FLAG_RW, 31, 32, 0xff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_ddr_random_reg[] = 
-    {
-        {"qcfg_qlist_ddr_random", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qlist_pds_fifo_afull_th_reg[] = 
-    {
-        {"cfgmt_qlist_pds_fifo_afull_th", DPP_FIELD_FLAG_RW, 5, 6, 0xc, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_sop_cmd_fifo_afull_th_reg[] = 
-    {
-        {"cfgmt_sop_cmd_fifo_afull_th", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_non_sop_cmd_fifo_afull_th_reg[] = 
-    {
-        {"cfgmt_non_sop_cmd_fifo_afull_th", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_mmu_data_fifo_afull_th_reg[] = 
-    {
-        {"cfgmt_mmu_data_fifo_afull_th", DPP_FIELD_FLAG_RW, 9, 10, 0xf0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_bank_ept_th_reg[] = 
-    {
-        {"qcfg_qlist_bank_ept_th", DPP_FIELD_FLAG_RW, 17, 18, 0x3, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_random_bypass_en_reg[] = 
-    {
-        {"random_bypass_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_crs_spd_bypass_reg[] = 
-    {
-        {"cfgmt_crs_spd_bypass", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_crs_interval_reg[] = 
-    {
-        {"cfgmt_crs_interval", DPP_FIELD_FLAG_RW, 31, 32, 0x8, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_auto_credit_control_en_reg[] = 
-    {
-        {"cfg_qsch_auto_credit_control_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_autocrfrstque_reg[] = 
-    {
-        {"cfg_qsch_autocrfrstque", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_autocrlastque_reg[] = 
-    {
-        {"cfg_qsch_autocrlastque", DPP_FIELD_FLAG_RW, 15, 16, 0x3ff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_autocreditrate_reg[] = 
-    {
-        {"cfg_qsch_autocreditrate", DPP_FIELD_FLAG_RW, 19, 20, 0x20, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_scanfrstque_reg[] = 
-    {
-        {"cfg_qsch_scanfrstque", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_scanlastque_reg[] = 
-    {
-        {"cfg_qsch_scanlastque", DPP_FIELD_FLAG_RW, 13, 14, 0x3ff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_scanrate_reg[] = 
-    {
-        {"cfg_qsch_scanrate", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_scan_en_reg[] = 
-    {
-        {"cfg_qsch_scan_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qsch_rd_credit_fifo_rate_reg[] = 
-    {
-        {"cfgmt_qsch_rd_credit_fifo_rate", DPP_FIELD_FLAG_RW, 23, 24, 0xa, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_bdep_reg[] = 
-    {
-        {"qcfg_qlist_bdep", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_bhead_reg[] = 
-    {
-        {"bank_vld", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0},
-        {"qcfg_qlist_bhead", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_btail_reg[] = 
-    {
-        {"qcfg_qlist_btail", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qsch_shap_param_reg[] = 
-    {
-        {"qcfg_qsch_shap_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"qcfg_qsch_shap_param1", DPP_FIELD_FLAG_RW, 23, 12, 0x0, 0x0},
-        {"qcfg_qsch_shap_param2", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qsch_shap_token_reg[] = 
-    {
-        {"qcfg_qsch_shap_token", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qsch_shap_offset_reg[] = 
-    {
-        {"qcfg_qsch_shap_offset", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_eir_th_reg[] = 
-    {
-        {"qcfg_qsch_crs_eir_th", DPP_FIELD_FLAG_RW, 18, 19, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_th1_reg[] = 
-    {
-        {"qcfg_qsch_crs_th1", DPP_FIELD_FLAG_RW, 31, 32, 0x57584c4c, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_th2_reg[] = 
-    {
-        {"qcfg_qsch_crs_th2", DPP_FIELD_FLAG_RW, 31, 32, 0x200, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_csch_congest_th_reg[] = 
-    {
-        {"qcfg_csch_congest_th", DPP_FIELD_FLAG_RW, 13, 14, 0xc8, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_csch_sp_fc_th_reg[] = 
-    {
-        {"qcfg_csch_sp_fc_th", DPP_FIELD_FLAG_RW, 13, 14, 0x12c, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_csw_shap_parameter_reg[] = 
-    {
-        {"qcfg_csw_shap_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"qcfg_csw_shap_parameter", DPP_FIELD_FLAG_RW, 23, 24, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_rd_release_aful_th_reg[] = 
-    {
-        {"cfgmt_rd_release_aful_th", DPP_FIELD_FLAG_RW, 8, 9, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_drop_imem_release_fifo_aful_th_reg[] = 
-    {
-        {"cfgmt_drop_imem_release_fifo_aful_th", DPP_FIELD_FLAG_RW, 8, 9, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_nnh_rd_buf_aful_th_reg[] = 
-    {
-        {"cfgmt_nnh_rd_buf_aful_th", DPP_FIELD_FLAG_RW, 5, 6, 0xa, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_pid_use_inall_reg[] = 
-    {
-        {"cfgmt_nod_rd_buf_0_aful_th", DPP_FIELD_FLAG_RW, 4, 5, 0x3, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_pid_round_th_reg[] = 
-    {
-        {"cfgmt_nod_rd_buf_1_aful_th", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_credit_fifo_afull_th_reg[] = 
-    {
-        {"cfgmt_credit_fifo_afull_th", DPP_FIELD_FLAG_RW, 5, 6, 0xa, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_scan_fifo_afull_th_reg[] = 
-    {
-        {"cfgmt_scan_fifo_afull_th", DPP_FIELD_FLAG_RW, 5, 6, 0xa, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_small_fifo_aful_th_reg[] = 
-    {
-        {"cfgmt_small_fifo_aful_th", DPP_FIELD_FLAG_RW, 5, 6, 0x9, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_free_addr_fifo_aful_th_reg[] = 
-    {
-        {"cfgmt_free_addr_fifo_aful_th", DPP_FIELD_FLAG_RW, 5, 6, 0x16, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_enq_rpt_fifo_aful_th_reg[] = 
-    {
-        {"cfgmt_enq_rpt_fifo_aful_th", DPP_FIELD_FLAG_RW, 9, 10, 0x3e8, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_csw_shap_token_depth_reg[] = 
-    {
-        {"qcfg_csw_shap_token_depth", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_csw_shap_offset_value_reg[] = 
-    {
-        {"qcfg_csw_shap_offset_value", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_csw_fc_offset_value_reg[] = 
-    {
-        {"qcfg_csw_fc_offset_value", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_init_done_state_reg[] = 
-    {
-        {"csch_qcfg_init_done", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"qsch_qcfg_init_done", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"qlist_qcfg_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"qcsr_ram_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csw_qcfg_port_shap_rdy_0_reg[] = 
-    {
-        {"csw_qcfg_port_shap_rdy_0", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csw_qcfg_port_shap_rdy_1_reg[] = 
-    {
-        {"csw_qcfg_port_shap_rdy_1", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qlist_cfgmt_ram_init_done_reg[] = 
-    {
-        {"qlist_qcfg_qds_ram_init_done", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"qlist_qcfg_chk_ram_init_done", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"qlist_qcfg_ept_ram_init_done", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"qlist_qcfg_cti_ram_init_done", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"qlist_qcfg_cto_ram_init_done", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"qlist_qcfg_bcnt_ram_init_done", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"qlist_qcfg_biu_ram_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"qlist_qcfg_baram_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qlist_cfgmt_ram_ecc_err_reg[] = 
-    {
-        {"qds_ram_parity_err", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"qcsr_qnum_fifo_parity_err", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"sa_id_ram_parity_err", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"enq_rpt_fifo_parity_err", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"bcnts_parity_err", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"baram_parity_err_a", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"baram_parity_err_b", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"bcntm_ram_parity_err", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"biu_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"chk_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"cmd_sch_cmd_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"cmd_sch_list_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"cmd_sch_hp_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"cmd_sch_tp_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"cmd_sch_enq_active_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"cmd_sch_deq_active_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"cmd_sch_empty_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"cmd_sch_eop_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"cmd_sch_blkcnt_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"biu_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"chk_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"cmd_sch_cmd_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"cmd_sch_list_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"cmd_sch_hp_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"cmd_sch_tp_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"cmd_sch_enq_active_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"cmd_sch_deq_active_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"cmd_sch_empty_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"cmd_sch_eop_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"cmd_sch_blkcnt_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qlist_cfgmt_ram_slot_err_reg[] = 
-    {
-        {"qds_ram_enq_rd_slot_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"qds_ram_deq_rd_slot_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"qds_ram_enq_wr_slot_err", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"qds_ram_deq_wr_slot_err", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"chk_ram_enq_rd_slot_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"chk_ram_deq_rd_slot_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"chk_ram_enq_wr_slot_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"chk_ram_deq_wr_slot_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ept_ram_enq_rd_slot_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ept_ram_deq_rd_slot_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ept_ram_enq_wr_slot_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ept_ram_deq_wr_slot_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"cti_ram_enq_rd_slot_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"cti_ram_deq_rd_slot_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"cti_ram_enq_wr_slot_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"cti_ram_deq_wr_slot_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"cto_ram_enq_rd_slot_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"cto_ram_deq_rd_slot_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"cto_ram_enq_wr_slot_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"cto_ram_deq_wr_slot_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qsch_cfgmt_ram_ecc_reg[] = 
-    {
-        {"crbal_rama_parity_error", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"crbal_ramb_parity_error", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"crs_ram_parity_error", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"wlist_flag_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"wlist_next_single_ecc_err", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"wlist_wactive_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"wlist_ractive_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"wlist_tp1_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"wlist_tp2_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"wlist_empty1_ram_single_ecc_err_a", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"wlist_empty1_ram_single_ecc_err_b", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"wlist_empty2_ram_single_ecc_err_a", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"wlist_empty2_ram_single_ecc_err_b", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"wlist_hp_ram_single_ecc_err_a", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"wlist_hp_ram_single_ecc_err_b", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"wlist_flag_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"wlist_next_double_ecc_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"wlist_wactive_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"wlist_ractive_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"wlist_tp1_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"wlist_tp2_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"wlist_empty1_ram_double_ecc_err_a", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"wlist_empty1_ram_double_ecc_err_b", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"wlist_empty2_ram_double_ecc_err_a", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"wlist_empty2_ram_double_ecc_err_b", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"wlist_hp_ram_double_ecc_err_a", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"wlist_hp_ram_double_ecc_err_b", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qlist_cfgmt_fifo_state_reg[] = 
-    {
-        {"pkt_age_req_fifo_overflow", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"pkt_age_req_fifo_underflow", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"qcsr_big_fifo_ovfl", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"qcsr_small_fifo_overflow", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"enq_rpt_fifo_overflow", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"enq_rpt_fifo_underflow", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"pds_fwft_overflow", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"pds_fwft_underflow", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"free_addr_fifo_overflow", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"free_addr_fifo_underflow", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"rd_release_fwft_overflow", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"rd_release_fwft_underflow", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"pid_free_list_overflow", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"pid_free_list_underflow", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"pid_prp_list_overflow", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"pid_prp_list_underflow", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"pid_rdy_list_overflow", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"pid_rdy_list_underflow", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"drop_imem_release_fwft_overflow", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"drop_imem_release_fwft_underflow", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"nnh_rd_buf_fifo_overflow", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"nnh_rd_buf_fifo_underflow", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"nod_rd_buf_0_fifo_overflow", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"nod_rd_buf_0_fifo_underflow", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"nod_rd_buf_1_fifo_overflow", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"nod_rd_buf_1_fifo_underflow", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qlist_qcfg_clr_done_reg[] = 
-    {
-        {"qlist_qcfg_clr_done", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_int_mask1_reg[] = 
-    {
-        {"qmu_int_mask1", DPP_FIELD_FLAG_RW, 29, 30, 0x3fffffff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_int_mask2_reg[] = 
-    {
-        {"qmu_int_mask2", DPP_FIELD_FLAG_RW, 19, 20, 0xfffff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_int_mask3_reg[] = 
-    {
-        {"qmu_int_mask3", DPP_FIELD_FLAG_RW, 26, 27, 0x7ffffff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_int_mask4_reg[] = 
-    {
-        {"qmu_int_mask4", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_int_mask5_reg[] = 
-    {
-        {"qmu_int_mask5", DPP_FIELD_FLAG_RW, 30, 31, 0x7fffffff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_int_mask6_reg[] = 
-    {
-        {"qmu_int_mask6", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cmd_sch_cfgmt_fifo_state_reg[] = 
-    {
-        {"nsop_fifo_parity_err", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"cmdsch_rd_cmd_fifo_parity_err", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"sop_fifo_afull", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"sop_fifo_empty", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"sop_fifo_overflow", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"sop_fifo_underflow", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"mmu_data_fifo_afull", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"mmu_data_fifo_empty", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"mmudat_fifo_overflow", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"mmudat_fifo_underflow", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"non_sop_fifo_afull", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"non_sop_fifo_empty", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"nsop_fifo_overflow", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"nsop_fifo_underflow", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"cmdsch_rd_cmd_fifo_afull", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"cmdsch_rd_cmd_fifo_empty", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"cmdsch_rd_cmd_fifo_overflow", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"cmdsch_rd_cmd_fifo_underflow", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"wlist_qnum_fifo_overflow", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"wlist_qnum_fifo_underflow", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"qsch_scan_fifo_overflow", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"qsch_scan_fifo_underflow", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"qsch_credit_fifo_overflow", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"qsch_credit_fifo_underflow", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"qsch_credit_fifo2_overflow", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"qsch_credit_fifo2_underflow", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qlist_r_bcnt_reg[] = 
-    {
-        {"qlist_r_bcnt", DPP_FIELD_FLAG_RO, 21, 22, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qsch_rw_crbal_reg[] = 
-    {
-        {"qsch_rw_crbal", DPP_FIELD_FLAG_RW, 16, 17, 0xff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qsch_rw_crs_reg[] = 
-    {
-        {"qsch_rw_crs", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qsch_r_wlist_empty_reg[] = 
-    {
-        {"qsch_r_wlist_empty", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_baram_rd_reg[] = 
-    {
-        {"qcfg_qlist_baram_rd", DPP_FIELD_FLAG_RO, 6, 7, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qsch_crbal_fb_rw_reg[] = 
-    {
-        {"qcfg_qlist_crbal_fb_rw", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp0_bank_reg[] = 
-    {
-        {"qcfg_qlist_grp0_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp1_bank_reg[] = 
-    {
-        {"qcfg_qlist_grp1_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp2_bank_reg[] = 
-    {
-        {"qcfg_qlist_grp2_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp3_bank_reg[] = 
-    {
-        {"qcfg_qlist_grp3_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp4_bank_reg[] = 
-    {
-        {"qcfg_qlist_grp4_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp5_bank_reg[] = 
-    {
-        {"qcfg_qlist_grp5_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp6_bank_reg[] = 
-    {
-        {"qcfg_qlist_grp6_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp7_bank_reg[] = 
-    {
-        {"qcfg_qlist_grp7_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp_reg[] = 
-    {
-        {"qcfg_qlist_grp_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_active_to_bank_cfg_reg[] = 
-    {
-        {"cfgmt_active_to_bank_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x1},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_ddr_in_mmu_cfg_reg[] = 
-    {
-        {"cfgmt_ddr_in_mmu_cfg", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x1},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_ddr_in_qmu_cfg_reg[] = 
-    {
-        {"cfgmt_ddr_in_qmu_cfg", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_bank_to_mmu_cfg_reg[] = 
-    {
-        {"cfgmt_bank_in_mmu_cfg", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x1},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_bank_to_qmu_cfg_reg[] = 
-    {
-        {"cfgmt_bank_in_qmu_cfg", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x1},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_grp_ram_n_clr_thd_reg[] = 
-    {
-        {"cfgmt_grp_ram_n_clr_thd", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_age_pkt_num_reg[] = 
-    {
-        {"cfgmt_age_pkt_num", DPP_FIELD_FLAG_RW, 3, 4, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_age_multi_interval_reg[] = 
-    {
-        {"cfgmt_age_multi_interval", DPP_FIELD_FLAG_RW, 15, 16, 0xff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pkt_age_en_reg[] = 
-    {
-        {"cfgmt_qmu_pkt_age_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pkt_age_interval_reg[] = 
-    {
-        {"cfgmt_qmu_pkt_age_interval", DPP_FIELD_FLAG_RW, 31, 32, 0xff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pkt_age_start_end_reg[] = 
-    {
-        {"cfgmt_qmu_pkt_age_end", DPP_FIELD_FLAG_RW, 31, 16, 0x23ff, 0x0},
-        {"cfgmt_qmu_pkt_age_start", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_pkt_age_req_aful_th_reg[] = 
-    {
-        {"cfgmt_pkt_age_req_aful_th", DPP_FIELD_FLAG_RW, 5, 6, 0xa, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_pkt_age_step_interval_reg[] = 
-    {
-        {"cfgmt_pkt_age_step_interval", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_age_mode_reg[] = 
-    {
-        {"cfgmt_qmu_imem_age_en", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0},
-        {"cfgmt_qmu_imem_age_qlen_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"cfgmt_qmu_imem_age_time_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_qlen_age_interval_reg[] = 
-    {
-        {"cfgmt_qmu_imem_qlen_age_interval", DPP_FIELD_FLAG_RW, 15, 16, 0xff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_time_age_interval_reg[] = 
-    {
-        {"cfgmt_qmu_imem_time_age_interval", DPP_FIELD_FLAG_RW, 31, 32, 0xff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_qlen_age_thd_reg[] = 
-    {
-        {"cfgmt_qmu_imem_qlen_age_thd", DPP_FIELD_FLAG_RW, 13, 14, 0x1000, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_imem_age_step_interval_reg[] = 
-    {
-        {"cfgmt_imem_age_step_interval", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_ecc_bypass_read_reg[] = 
-    {
-        {"cfgmt_qmu_ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_resp_stat_fc_en_reg[] = 
-    {
-        {"cfgmt_qmu_resp_stat_fc_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_bank_xoff_pds_mode_reg[] = 
-    {
-        {"cfgmt_qmu_bank_xoff_pds_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_stat_offset_reg[] = 
-    {
-        {"cfgmt_qmu_stat_offset", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_fc_cnt_mode_reg[] = 
-    {
-        {"fc_cnt_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_mmu_qmu_wr_fc_cnt_reg[] = 
-    {
-        {"mmu_qmu_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_mmu_qmu_rd_fc_cnt_reg[] = 
-    {
-        {"mmu_qmu_rd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_cgavd_fc_cnt_reg[] = 
-    {
-        {"qmu_cgavd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cgavd_qmu_pkt_cnt_reg[] = 
-    {
-        {"cgavd_qmu_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cgavd_qmu_pktlen_all_reg[] = 
-    {
-        {"cgavd_qmu_pktlen_all", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_observe_portfc_spec_reg[] = 
-    {
-        {"observe_portfc_spec", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_lif_portfc_count_reg[] = 
-    {
-        {"spec_lif_portfc_count", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pfc_en_reg[] = 
-    {
-        {"cfgmt_qmu_pfc_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pfc_mask_1_reg[] = 
-    {
-        {"cfgmt_qmu_pfc_mask_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pfc_mask_2_reg[] = 
-    {
-        {"cfgmt_qmu_pfc_mask_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_int_repeat_reg[] = 
-    {
-        {"int_repeat", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_up_size_reg[] = 
-    {
-        {"dma_up_size", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_soc_wr_time_out_thresh_reg[] = 
-    {
-        {"soc_wr_time_out_thresh", DPP_FIELD_FLAG_RW, 31, 32, 0xfa0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_cfg_shap_param_reg[] = 
-    {
-        {"shap_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"shap_rate", DPP_FIELD_FLAG_RW, 30, 31, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_cfg_shap_token_reg[] = 
-    {
-        {"cfg_shap_plen_offset", DPP_FIELD_FLAG_RW, 31, 8, 0x00, 0x0},
-        {"cfg_shap_token", DPP_FIELD_FLAG_RW, 16, 17, 0xf0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_idle_ptr_fifo_aful_th_reg[] = 
-    {
-        {"idle_ptr3_fifo_aful_th", DPP_FIELD_FLAG_RW, 31, 8, 0x5a, 0x0},
-        {"idle_ptr2_fifo_aful_th", DPP_FIELD_FLAG_RW, 23, 8, 0x5a, 0x0},
-        {"idle_ptr1_fifo_aful_th", DPP_FIELD_FLAG_RW, 15, 8, 0x5a, 0x0},
-        {"idle_ptr0_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0x5a, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos_port_cfg_reg[] = 
-    {
-        {"cos3_port_cfg", DPP_FIELD_FLAG_RW, 31, 8, 0x3f, 0x0},
-        {"cos2_port_cfg", DPP_FIELD_FLAG_RW, 23, 8, 0x3e, 0x0},
-        {"cos1_port_cfg", DPP_FIELD_FLAG_RW, 15, 8, 0x3d, 0x0},
-        {"cos0_port_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x3c, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_ind_status_reg[] = 
-    {
-        {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_ind_cmd_reg[] = 
-    {
-        {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0},
-        {"ind_mem_id", DPP_FIELD_FLAG_RW, 22, 3, 0x0, 0x0},
-        {"ind_mem_addr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_ind_data0_reg[] = 
-    {
-        {"ind_dat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_ind_data1_reg[] = 
-    {
-        {"ind_dat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_ind_data2_reg[] = 
-    {
-        {"ind_dat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_ind_data3_reg[] = 
-    {
-        {"ind_dat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_ind_data4_reg[] = 
-    {
-        {"ind_dat4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_ind_data5_reg[] = 
-    {
-        {"ind_dat5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_ind_data6_reg[] = 
-    {
-        {"ind_dat6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_ind_data7_reg[] = 
-    {
-        {"ind_dat7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_tcam_0_cmd_reg[] = 
-    {
-        {"cfg_vben", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"cfg_vbi", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"cfg_t_strwc", DPP_FIELD_FLAG_RW, 22, 2, 0x1, 0x0},
-        {"tcam0_sm", DPP_FIELD_FLAG_RW, 20, 6, 0x0, 0x0},
-        {"tcam0_smen", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0},
-        {"tcam0_rm", DPP_FIELD_FLAG_RW, 13, 2, 0x2, 0x0},
-        {"tcam0_rmen", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0},
-        {"tcam0_enable", DPP_FIELD_FLAG_RW, 10, 1, 0x0, 0x0},
-        {"tcam0_flush", DPP_FIELD_FLAG_WO, 9, 1, 0x0, 0x0},
-        {"tcam0_unload", DPP_FIELD_FLAG_WO, 8, 1, 0x0, 0x0},
-        {"tcam0_unload_addr", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_tcam_1_cmd_reg[] = 
-    {
-        {"tcam1_sm", DPP_FIELD_FLAG_RW, 20, 6, 0x0, 0x0},
-        {"tcam1_smen", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0},
-        {"tcam1_rm", DPP_FIELD_FLAG_RW, 13, 2, 0x2, 0x0},
-        {"tcam1_rmen", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0},
-        {"tcam1_enable", DPP_FIELD_FLAG_RW, 10, 1, 0x0, 0x0},
-        {"tcam1_flush", DPP_FIELD_FLAG_WO, 9, 1, 0x0, 0x0},
-        {"tcam1_unload", DPP_FIELD_FLAG_WO, 8, 1, 0x0, 0x0},
-        {"tcam1_unload_addr", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_port_en_0_reg[] = 
-    {
-        {"cfg_isch_port_en_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_port_en_1_reg[] = 
-    {
-        {"cfg_isch_port_en_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_port_en_2_reg[] = 
-    {
-        {"cfg_isch_port_en_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_port_en_3_reg[] = 
-    {
-        {"cfg_port_change_en_0", DPP_FIELD_FLAG_RW, 26, 1, 0x0, 0x0},
-        {"cfg_port_change_en_1", DPP_FIELD_FLAG_RW, 25, 1, 0x0, 0x0},
-        {"cfg_isch_port_en_3", DPP_FIELD_FLAG_RW, 22, 23, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_0_reg[] = 
-    {
-        {"cfg_port_l2_offset_mode_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_1_reg[] = 
-    {
-        {"cfg_port_l2_offset_mode_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_2_reg[] = 
-    {
-        {"cfg_port_l2_offset_mode_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_3_reg[] = 
-    {
-        {"cfg_port_l2_offset_mode_3", DPP_FIELD_FLAG_RW, 22, 23, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_0_reg[] = 
-    {
-        {"cfg_isch_fc_mode_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_1_reg[] = 
-    {
-        {"cfg_isch_fc_mode_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_2_reg[] = 
-    {
-        {"cfg_isch_fc_mode_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_3_reg[] = 
-    {
-        {"cfg_isch_fc_mode_3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_4_reg[] = 
-    {
-        {"cfg_isch_fc_mode_4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_5_reg[] = 
-    {
-        {"cfg_isch_fc_mode_5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_6_reg[] = 
-    {
-        {"cfg_isch_fc_mode_6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_7_reg[] = 
-    {
-        {"cfg_pfu_aging_en", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"cfg_isch_aging_en", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0},
-        {"cfg_isch_fc_mode_7", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_cfg_isch_aging_th_reg[] = 
-    {
-        {"cfg_pfu_delay_cycle", DPP_FIELD_FLAG_RW, 31, 16, 0x8000, 0x0},
-        {"cfg_isch_aging_th", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_isch_fifo_th_0_reg[] = 
-    {
-        {"cfg_sch_fifo3_fc_th", DPP_FIELD_FLAG_RW, 29, 6, 0x30, 0x0},
-        {"cfg_sch_fifo2_fc_th", DPP_FIELD_FLAG_RW, 21, 6, 0x30, 0x0},
-        {"cfg_sch_fifo1_fc_th", DPP_FIELD_FLAG_RW, 13, 6, 0x30, 0x0},
-        {"cfg_sch_fifo0_fc_th", DPP_FIELD_FLAG_RW, 5, 6, 0x30, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_isch_cfg_1_reg[] = 
-    {
-        {"cfg_parser_max_len_en", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"cfg_parser_max_len", DPP_FIELD_FLAG_RW, 30, 15, 0x3e80, 0x0},
-        {"cfg_parser_min_len_en", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0},
-        {"cfg_parser_min_len", DPP_FIELD_FLAG_RW, 14, 7, 0x3c, 0x0},
-        {"sp_sch_sel", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_tcam_0_vld_reg[] = 
-    {
-        {"cfg_tcam0_vld", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_tcam_1_vld_reg[] = 
-    {
-        {"cfg_tcam1_vld", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_cpu_port_en_mask_reg[] = 
-    {
-        {"cpu_port_en_mask", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg[] = 
-    {
-        {"pktrx_glbal_cfg_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_1_reg[] = 
-    {
-        {"pktrx_glbal_cfg_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_2_reg[] = 
-    {
-        {"pktrx_glbal_cfg_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_3_reg[] = 
-    {
-        {"pktrx_glbal_cfg_3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_nppu_start_reg[] = 
-    {
-        {"nppu_start", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_stat_ind_status_reg[] = 
-    {
-        {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_stat_ind_cmd_reg[] = 
-    {
-        {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0},
-        {"ind_mem_id", DPP_FIELD_FLAG_RW, 22, 3, 0x0, 0x0},
-        {"ind_mem_addr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_stat_ind_data0_reg[] = 
-    {
-        {"ind_dat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_idma_cfg_debug_cnt_ovfl_mode_reg[] = 
-    {
-        {"debug_cnt_ovfl_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_idma_stat_ind_status_reg[] = 
-    {
-        {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_idma_stat_ind_cmd_reg[] = 
-    {
-        {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0},
-        {"ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0},
-        {"ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_idma_stat_ind_data0_reg[] = 
-    {
-        {"ind_data0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_ind_status_reg[] = 
-    {
-        {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_ind_cmd_reg[] = 
-    {
-        {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0},
-        {"ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0},
-        {"ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_ind_data0_reg[] = 
-    {
-        {"ind_data0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_ind_data1_reg[] = 
-    {
-        {"ind_data1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_ind_data2_reg[] = 
-    {
-        {"ind_data2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_ind_data3_reg[] = 
-    {
-        {"ind_data3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_ind_data4_reg[] = 
-    {
-        {"ind_data4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_ind_data5_reg[] = 
-    {
-        {"ind_data5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_ind_data6_reg[] = 
-    {
-        {"ind_data6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_ind_data7_reg[] = 
-    {
-        {"ind_data7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_idma_public_th_reg[] = 
-    {
-        {"idma_public_th", DPP_FIELD_FLAG_RW, 14, 15, 0x400, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_lif_public_th_reg[] = 
-    {
-        {"lif_public_th", DPP_FIELD_FLAG_RW, 14, 15, 0x400, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_idma_total_th_reg[] = 
-    {
-        {"idma_total_th", DPP_FIELD_FLAG_RW, 14, 15, 0x3ffc, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_lif_total_th_reg[] = 
-    {
-        {"lif_total_th", DPP_FIELD_FLAG_RW, 14, 15, 0x3fa2, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_mc_total_th_reg[] = 
-    {
-        {"mc_total_th", DPP_FIELD_FLAG_RW, 14, 15, 0x400, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_mc_cos10_th_reg[] = 
-    {
-        {"mc_cos1_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"mc_cos0_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0},
-        {"mc_cos1_th", DPP_FIELD_FLAG_RW, 29, 15, 0x80, 0x0},
-        {"mc_cos0_th", DPP_FIELD_FLAG_RW, 14, 15, 0x80, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_mc_cos32_th_reg[] = 
-    {
-        {"mc_cos3_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"mc_cos2_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0},
-        {"mc_cos3_th", DPP_FIELD_FLAG_RW, 29, 15, 0x80, 0x0},
-        {"mc_cos2_th", DPP_FIELD_FLAG_RW, 14, 15, 0x80, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_mc_cos54_th_reg[] = 
-    {
-        {"mc_cos5_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"mc_cos4_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0},
-        {"mc_cos5_th", DPP_FIELD_FLAG_RW, 29, 15, 0x80, 0x0},
-        {"mc_cos4_th", DPP_FIELD_FLAG_RW, 14, 15, 0x80, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_mc_cos76_th_reg[] = 
-    {
-        {"mc_cos7_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"mc_cos6_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0},
-        {"mc_cos7_th", DPP_FIELD_FLAG_RW, 29, 15, 0x80, 0x0},
-        {"mc_cos6_th", DPP_FIELD_FLAG_RW, 14, 15, 0x80, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_debug_cnt_ovfl_mode_reg[] = 
-    {
-        {"debug_cnt_ovfl_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_se_key_aful_negate_cfg_reg[] = 
-    {
-        {"se_key_aful_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_sa_flag_reg[] = 
-    {
-        {"sa_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_ind_data_reg[] = 
-    {
-        {"ind_data", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_ind_status_reg[] = 
-    {
-        {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_ind_cmd_reg[] = 
-    {
-        {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0},
-        {"ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0},
-        {"ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_total_cnt_reg[] = 
-    {
-        {"total_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_idma_pub_cnt_reg[] = 
-    {
-        {"idma_pub_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_lif_pub_cnt_reg[] = 
-    {
-        {"lif_pub_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_mc_total_cnt_reg[] = 
-    {
-        {"mc_total_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_pbu_thram_init_done_reg[] = 
-    {
-        {"pbu_thram_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_ifb_fptr_init_done_reg[] = 
-    {
-        {"ifb_fptr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_weight_normal_uc_reg[] = 
-    {
-        {"weight_normal_uc", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_fabric_or_saip_reg[] = 
-    {
-        {"fabric_or_saip", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_ind_status_reg[] = 
-    {
-        {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_ind_cmd_reg[] = 
-    {
-        {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0},
-        {"ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0},
-        {"ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_ind_dat0_reg[] = 
-    {
-        {"ind_dat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_ind_access_done_reg[] = 
-    {
-        {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_ind_command_reg[] = 
-    {
-        {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0},
-        {"ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0},
-        {"ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_ind_dat0_reg[] = 
-    {
-        {"ind_dat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_ind_dat1_reg[] = 
-    {
-        {"ind_dat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_fabric_or_saip_reg[] = 
-    {
-        {"fabric_or_saip", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_max_pkt_len_reg[] = 
-    {
-        {"max_pkt_len", DPP_FIELD_FLAG_RW, 14, 15, 0x3f00, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_age_en_reg[] = 
-    {
-        {"age_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_age_mode_reg[] = 
-    {
-        {"age_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_age_value_time_reg[] = 
-    {
-        {"age_value_time", DPP_FIELD_FLAG_RW, 31, 32, 0xe4e1c0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_age_value_room_reg[] = 
-    {
-        {"age_value_room", DPP_FIELD_FLAG_RW, 31, 32, 0x1e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_age_out_cnt_reg[] = 
-    {
-        {"age_out_cnt", DPP_FIELD_FLAG_RW, 6, 7, 0xa, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_token_value_a_reg[] = 
-    {
-        {"token_value_a", DPP_FIELD_FLAG_RW, 31, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_token_value_b_reg[] = 
-    {
-        {"token_value_b", DPP_FIELD_FLAG_RW, 31, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_cfg_shap_en_p0_reg[] = 
-    {
-        {"cfg_shap_en_p0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_cfg_shap_en_p1_reg[] = 
-    {
-        {"cfg_shap_en_p1", DPP_FIELD_FLAG_RW, 31, 28, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_cfg_shap_en_tm_reg[] = 
-    {
-        {"cfg_shap_en_tm", DPP_FIELD_FLAG_RW, 31, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_stat_ind_status_reg[] = 
-    {
-        {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_stat_ind_cmd_reg[] = 
-    {
-        {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0},
-        {"ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0},
-        {"ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_stat_ind_data0_reg[] = 
-    {
-        {"ind_dat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_stat_debug_cnt_cfg_reg[] = 
-    {
-        {"debug_cnt_ovf_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"debug_cnt_rdclr_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0},
-        {"user_cnt_value", DPP_FIELD_FLAG_RW, 29, 4, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_bfd_firstchk_th_reg[] = 
-    {
-        {"bfd_firstchk_th", DPP_FIELD_FLAG_RW, 18, 19, 0xc350, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_memid_0_pbu_fc_idmath_ram_reg[] = 
-    {
-        {"lif_th_15", DPP_FIELD_FLAG_RW, 164, 15, 0x0, 0x0},
-        {"lif_prv_15", DPP_FIELD_FLAG_RW, 149, 15, 0x0, 0x0},
-        {"idma_prv_15", DPP_FIELD_FLAG_RW, 134, 15, 0x0, 0x0},
-        {"idma_th_cos0_15", DPP_FIELD_FLAG_RW, 119, 15, 0x0, 0x0},
-        {"idma_th_cos1_15", DPP_FIELD_FLAG_RW, 104, 15, 0x0, 0x0},
-        {"idma_th_cos2_15", DPP_FIELD_FLAG_RW, 89, 15, 0x0, 0x0},
-        {"idma_th_cos3_15", DPP_FIELD_FLAG_RW, 74, 15, 0x0, 0x0},
-        {"idma_th_cos4_15", DPP_FIELD_FLAG_RW, 59, 15, 0x0, 0x0},
-        {"idma_th_cos5_15", DPP_FIELD_FLAG_RW, 44, 15, 0x0, 0x0},
-        {"idma_th_cos6_15", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0},
-        {"idma_th_cos7_15", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_memid_1_pbu_fc_macth_ram_reg[] = 
-    {
-        {"cos7_th", DPP_FIELD_FLAG_RW, 119, 15, 0x0, 0x0},
-        {"cos6_th", DPP_FIELD_FLAG_RW, 104, 15, 0x0, 0x0},
-        {"cos5_th", DPP_FIELD_FLAG_RW, 89, 15, 0x0, 0x0},
-        {"cos4_th", DPP_FIELD_FLAG_RW, 74, 15, 0x0, 0x0},
-        {"cos3_th", DPP_FIELD_FLAG_RW, 59, 15, 0x0, 0x0},
-        {"cos2_th", DPP_FIELD_FLAG_RW, 44, 15, 0x0, 0x0},
-        {"cos1_th", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0},
-        {"cos0_th", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_1_all_kind_port_cnt_reg[] = 
-    {
-        {"peak_port_cnt", DPP_FIELD_FLAG_RO, 29, 15, 0x0, 0x0},
-        {"current_port_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_2_ppu_pbu_ifb_req_vld_cnt_reg[] = 
-    {
-        {"ppu_pbu_ifb_req_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_ifb_rsp_vld_cnt_reg[] = 
-    {
-        {"pbu_ppu_ifb_rsp_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_2_odma_pbu_recy_ptr_vld_cnt_reg[] = 
-    {
-        {"odma_pbu_recy_ptr_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_2_ppu_pbu_mcode_pf_req_cnt_reg[] = 
-    {
-        {"ppu_pbu_mcode_pf_req_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_rsp_cnt_reg[] = 
-    {
-        {"pbu_ppu_mcode_pf_rsp_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_2_ppu_pbu_logic_pf_req_cnt_reg[] = 
-    {
-        {"ppu_pbu_logic_pf_req_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_rsp_cnt_reg[] = 
-    {
-        {"pbu_ppu_logic_pf_rsp_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_2_ppu_use_ptr_pulse_cnt_reg[] = 
-    {
-        {"ppu_use_ptr_pulse_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_2_ppu_pbu_wb_vld_cnt_reg[] = 
-    {
-        {"ppu_pbu_wb_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_reorder_para_vld_cnt_reg[] = 
-    {
-        {"pbu_ppu_reorder_para_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_2_se_pbu_dpi_key_vld_cnt_reg[] = 
-    {
-        {"se_pbu_dpi_key_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_se_dpi_rsp_datvld_cnt_reg[] = 
-    {
-        {"pbu_se_dpi_rsp_datvld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd1_cnt_reg[] = 
-    {
-        {"odma_pbu_ifb_rd1_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd2_cnt_reg[] = 
-    {
-        {"odma_pbu_ifb_rd2_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_no_rsp_cnt_reg[] = 
-    {
-        {"pbu_ppu_mcode_pf_no_rsp_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_no_rsp_cnt_reg[] = 
-    {
-        {"pbu_ppu_logic_pf_no_rsp_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_3_cpu_rd_ifb_data_reg[] = 
-    {
-        {"cpu_rd_ifb_data", DPP_FIELD_FLAG_RO, 2047, 2048, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_4_mux_sel_rgt_reg[] = 
-    {
-        {"current_port_cnt", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_memid_5_port_pub_cnt_reg[] = 
-    {
-        {"port_pub_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_idma_stat_memid_1_idma_o_isu_pkt_pulse_total_cnt_reg[] = 
-    {
-        {"idma_o_isu_pkt_pulse_total_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_idma_stat_memid_1_idma_o_isu_epkt_pulse_total_cnt_reg[] = 
-    {
-        {"idma_o_isu_epkt_pulse_total_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_idma_stat_memid_1_idma_dispkt_pulse_total_cnt_reg[] = 
-    {
-        {"idma_dispkt_pulse_total_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_idma_stat_memid_0_idma_o_isu_pkt_pulse_cnt_reg[] = 
-    {
-        {"idma_o_isu_pkt_pulse_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_idma_stat_memid_0_idma_o_isu_epkt_pulse_cnt_reg[] = 
-    {
-        {"idma_o_isu_epkt_pulse_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_idma_stat_memid_0_idma_dispkt_pulse_cnt_reg[] = 
-    {
-        {"idma_dispkt_pulse_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_test_r_reg[] = 
-    {
-        {"test_r", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_debug_en_r_reg[] = 
-    {
-        {"debug_en_r", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_csr_dup_table_wr_data_reg[] = 
-    {
-        {"item_vld", DPP_FIELD_FLAG_RW, 24, 1, 0x0, 0x0},
-        {"flownum_vld", DPP_FIELD_FLAG_RW, 23, 1, 0x0, 0x0},
-        {"start_pc", DPP_FIELD_FLAG_RW, 22, 15, 0x0, 0x0},
-        {"flownum", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_csr_dup_table_rd_data_reg[] = 
-    {
-        {"item_vld", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0},
-        {"flownum_vld", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0},
-        {"start_pc", DPP_FIELD_FLAG_RO, 22, 15, 0x0, 0x0},
-        {"flownum", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_csr_dup_table_addr_reg[] = 
-    {
-        {"csr_dup_table_operation", DPP_FIELD_FLAG_WO, 6, 1, 0x0, 0x0},
-        {"csr_dup_table_addr", DPP_FIELD_FLAG_WO, 5, 6, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_debug_vld_reg[] = 
-    {
-        {"ppu_debug_vld", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_319_288_reg[] = 
-    {
-        {"rsk_319_288", DPP_FIELD_FLAG_RW, 31, 32, 0x6d5a56da, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_287_256_reg[] = 
-    {
-        {"rsk_287_256", DPP_FIELD_FLAG_RW, 31, 32, 0x255b0ec2, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_255_224_reg[] = 
-    {
-        {"rsk_255_224", DPP_FIELD_FLAG_RW, 31, 32, 0x4167253d, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_223_192_reg[] = 
-    {
-        {"rsk_223_192", DPP_FIELD_FLAG_RW, 31, 32, 0x43a38fb0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_191_160_reg[] = 
-    {
-        {"rsk_191_160", DPP_FIELD_FLAG_RW, 31, 32, 0xd0ca2bcb, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_159_128_reg[] = 
-    {
-        {"rsk_159_128", DPP_FIELD_FLAG_RW, 31, 32, 0xae7b30b4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_127_096_reg[] = 
-    {
-        {"rsk_127_096", DPP_FIELD_FLAG_RW, 31, 32, 0x77cb2da3, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_095_064_reg[] = 
-    {
-        {"rsk_095_064", DPP_FIELD_FLAG_RW, 31, 32, 0x8030f20c, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_063_032_reg[] = 
-    {
-        {"rsk_063_032", DPP_FIELD_FLAG_RW, 31, 32, 0x6a42b73b, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_031_000_reg[] = 
-    {
-        {"rsk_031_000", DPP_FIELD_FLAG_RW, 31, 32, 0xbeac01fa, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_cfg_ipv4_ipid_start_value_reg[] = 
-    {
-        {"cfg_ipv4_ipid_start_value", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_cfg_ipv4_ipid_end_value_reg[] = 
-    {
-        {"cfg_ipv4_ipid_end_value", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_cluster_mf_in_en_reg[] = 
-    {
-        {"cluster_mf_in_en", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_empty_reg[] = 
-    {
-        {"ppu_empty", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_w_addr_reg[] = 
-    {
-        {"instrmem_w_addr", DPP_FIELD_FLAG_WO, 12, 13, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_w_data_191_160_reg[] = 
-    {
-        {"instrmem_w_data_191_160", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_w_data_159_128_reg[] = 
-    {
-        {"instrmem_w_data_159_128", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_w_data_127_96_reg[] = 
-    {
-        {"instrmem_w_data_127_96", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_w_data_95_64_reg[] = 
-    {
-        {"instrmem_w_data_95_64", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_w_data_63_32_reg[] = 
-    {
-        {"instrmem_w_data_63_32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_w_data_31_0_reg[] = 
-    {
-        {"instrmem_w_data_31_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_fwft_mf_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"isu_fwft_mf_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_fwft_mf_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"isu_fwft_mf_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_int_1200m_mask_reg[] = 
-    {
-        {"me7_interrupt_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"me6_interrupt_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"me5_interrupt_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"me4_interrupt_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"me3_interrupt_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"me2_interrupt_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"me1_interrupt_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"me0_interrupt_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu4k_cluster_wr_high_data_r_mex_reg[] = 
-    {
-        {"wr_high_data_r_mex", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu4k_cluster_wr_low_data_r_mex_reg[] = 
-    {
-        {"wr_low_data_r_mex", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu4k_cluster_addr_r_mex_reg[] = 
-    {
-        {"operate_type", DPP_FIELD_FLAG_WO, 8, 1, 0x0, 0x0},
-        {"addr_r_mex", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu4k_cluster_sdt_tbl_ind_access_done_reg[] = 
-    {
-        {"rd_addr_r_mex", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu4k_cluster_rd_high_data_r_mex_reg[] = 
-    {
-        {"rd_high_data_r_mex", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu4k_cluster_rd_low_data_r_mex_reg[] = 
-    {
-        {"rd_low_data_r_mex", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_init_ok_reg[] = 
-    {
-        {"init_ok", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_rdy_reg[] = 
-    {
-        {"cpu_rd_rdy", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_data_tmp0_reg[] = 
-    {
-        {"cpu_rd_data_tmp0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_data_tmp1_reg[] = 
-    {
-        {"cpu_rd_data_tmp1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_data_tmp2_reg[] = 
-    {
-        {"cpu_rd_data_tmp2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_data_tmp3_reg[] = 
-    {
-        {"cpu_rd_data_tmp3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_data_tmp4_reg[] = 
-    {
-        {"cpu_rd_data_tmp4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_data_tmp5_reg[] = 
-    {
-        {"cpu_rd_data_tmp5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_data_tmp6_reg[] = 
-    {
-        {"cpu_rd_data_tmp6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_data_tmp7_reg[] = 
-    {
-        {"cpu_rd_data_tmp7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_data_tmp8_reg[] = 
-    {
-        {"cpu_rd_data_tmp8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_data_tmp9_reg[] = 
-    {
-        {"cpu_rd_data_tmp9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_data_tmp10_reg[] = 
-    {
-        {"cpu_rd_data_tmp10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_data_tmp11_reg[] = 
-    {
-        {"cpu_rd_data_tmp11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_data_tmp12_reg[] = 
-    {
-        {"cpu_rd_data_tmp12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_data_tmp13_reg[] = 
-    {
-        {"cpu_rd_data_tmp13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_data_tmp14_reg[] = 
-    {
-        {"cpu_rd_data_tmp14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_cpu_rd_data_tmp15_reg[] = 
-    {
-        {"cpu_rd_data_tmp15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_v4_config_rgt_reg[] = 
-    {
-        {"lpm_v4_shift_sel", DPP_FIELD_FLAG_RW, 4, 2, 0x0, 0x0},
-        {"lpm_v4_sram_cmp_flag", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0},
-        {"lpm_v4_ddr3_addr_sel", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_v6_config_rgt_reg[] = 
-    {
-        {"lpm_v6_shift_sel", DPP_FIELD_FLAG_RW, 5, 2, 0x0, 0x0},
-        {"lpm_v6_sram_cmp_flag", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0},
-        {"lpm_v6_ddr3_addr_sel", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u0_pfull_ast_reg[] = 
-    {
-        {"lpm_ext_rsp_fifo_u0_pfull_ast", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0},
-    };
-DPP_FIELD_T g_se_as_hash_age_pat_cfg_reg[] = 
-    {
-        {"hash_age_pat_cfg", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_learn_rdy_cfg_reg[] = 
-    {
-        {"learn_rdy_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_kschd_as_pful_cfg_reg[] = 
-    {
-        {"kschd_as_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1326, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_kschd_dir_pful_cfg_reg[] = 
-    {
-        {"kschd_dir_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1326, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_kschd_as_ept_cfg_reg[] = 
-    {
-        {"kschd_as_ept_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0xc18, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_cpu_arbi_pful_cfg_reg[] = 
-    {
-        {"cpu_arbi_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1326, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_kschd_pbu_pful_cfg_reg[] = 
-    {
-        {"kschd_pbu_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1326, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_dir_pful_cfg_reg[] = 
-    {
-        {"rschd_dir_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00360036, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_dir_ept_cfg_reg[] = 
-    {
-        {"rschd_dir_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x000a000a, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_cmd_rgt_reg[] = 
-    {
-        {"rd_flag", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"mask", DPP_FIELD_FLAG_RW, 20, 4, 0x0, 0x0},
-        {"reg_sram_flag", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0},
-        {"zgroup_id", DPP_FIELD_FLAG_RW, 15, 2, 0x0, 0x0},
-        {"zblock_id", DPP_FIELD_FLAG_RW, 13, 3, 0x0, 0x0},
-        {"zcell_id", DPP_FIELD_FLAG_RW, 10, 2, 0x0, 0x0},
-        {"addr", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp0_reg[] = 
-    {
-        {"cpu_wr_data_tmp0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp1_reg[] = 
-    {
-        {"cpu_wr_data_tmp1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp2_reg[] = 
-    {
-        {"cpu_wr_data_tmp2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp3_reg[] = 
-    {
-        {"cpu_wr_data_tmp3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp4_reg[] = 
-    {
-        {"cpu_wr_data_tmp4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp5_reg[] = 
-    {
-        {"cpu_wr_data_tmp5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp6_reg[] = 
-    {
-        {"cpu_wr_data_tmp6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp7_reg[] = 
-    {
-        {"cpu_wr_data_tmp7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp8_reg[] = 
-    {
-        {"cpu_wr_data_tmp8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp9_reg[] = 
-    {
-        {"cpu_wr_data_tmp9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp10_reg[] = 
-    {
-        {"cpu_wr_data_tmp10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp11_reg[] = 
-    {
-        {"cpu_wr_data_tmp11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp12_reg[] = 
-    {
-        {"cpu_wr_data_tmp12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp13_reg[] = 
-    {
-        {"cpu_wr_data_tmp13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp14_reg[] = 
-    {
-        {"cpu_wr_data_tmp14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp15_reg[] = 
-    {
-        {"cpu_wr_data_tmp15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_rdy_reg[] = 
-    {
-        {"cpu_rd_rdy", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp0_reg[] = 
-    {
-        {"cpu_rd_data_tmp0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp1_reg[] = 
-    {
-        {"cpu_rd_data_tmp1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp2_reg[] = 
-    {
-        {"cpu_rd_data_tmp2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp3_reg[] = 
-    {
-        {"cpu_rd_data_tmp3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp4_reg[] = 
-    {
-        {"cpu_rd_data_tmp4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp5_reg[] = 
-    {
-        {"cpu_rd_data_tmp5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp6_reg[] = 
-    {
-        {"cpu_rd_data_tmp6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp7_reg[] = 
-    {
-        {"cpu_rd_data_tmp7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp8_reg[] = 
-    {
-        {"cpu_rd_data_tmp8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp9_reg[] = 
-    {
-        {"cpu_rd_data_tmp9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp10_reg[] = 
-    {
-        {"cpu_rd_data_tmp10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp11_reg[] = 
-    {
-        {"cpu_rd_data_tmp11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp12_reg[] = 
-    {
-        {"cpu_rd_data_tmp12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp13_reg[] = 
-    {
-        {"cpu_rd_data_tmp13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp14_reg[] = 
-    {
-        {"cpu_rd_data_tmp14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp15_reg[] = 
-    {
-        {"cpu_rd_data_tmp15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_hash0_ext_cfg_rgt_reg[] = 
-    {
-        {"hash0_ext_mode", DPP_FIELD_FLAG_RW, 8, 8, 0x0, 0x0},
-        {"hash0_ext_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_hash1_ext_cfg_rgt_reg[] = 
-    {
-        {"hash1_ext_mode", DPP_FIELD_FLAG_RW, 8, 8, 0x0, 0x0},
-        {"hash1_ext_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_hash2_ext_cfg_rgt_reg[] = 
-    {
-        {"hash2_ext_mode", DPP_FIELD_FLAG_RW, 8, 8, 0x0, 0x0},
-        {"hash2_ext_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_hash3_ext_cfg_rgt_reg[] = 
-    {
-        {"hash3_ext_mode", DPP_FIELD_FLAG_RW, 8, 8, 0x0, 0x0},
-        {"hash3_ext_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_hash0_tbl30_depth_reg[] = 
-    {
-        {"hash0_tbl3_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0},
-        {"hash0_tbl2_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0},
-        {"hash0_tbl1_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0},
-        {"hash0_tbl0_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_hash0_tbl74_depth_reg[] = 
-    {
-        {"hash0_tbl7_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0},
-        {"hash0_tbl6_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0},
-        {"hash0_tbl5_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0},
-        {"hash0_tbl4_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_hash1_tbl30_depth_reg[] = 
-    {
-        {"hash1_tbl3_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0},
-        {"hash1_tbl2_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0},
-        {"hash1_tbl1_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0},
-        {"hash1_tbl0_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_hash1_tbl74_depth_reg[] = 
-    {
-        {"hash1_tbl7_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0},
-        {"hash1_tbl6_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0},
-        {"hash1_tbl5_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0},
-        {"hash1_tbl4_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_hash2_tbl30_depth_reg[] = 
-    {
-        {"hash2_tbl3_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0},
-        {"hash2_tbl2_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0},
-        {"hash2_tbl1_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0},
-        {"hash2_tbl0_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_hash2_tbl74_depth_reg[] = 
-    {
-        {"hash2_tbl7_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0},
-        {"hash2_tbl6_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0},
-        {"hash2_tbl5_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0},
-        {"hash2_tbl4_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_hash3_tbl30_depth_reg[] = 
-    {
-        {"hash3_tbl3_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0},
-        {"hash3_tbl2_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0},
-        {"hash3_tbl1_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0},
-        {"hash3_tbl0_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_hash3_tbl74_depth_reg[] = 
-    {
-        {"hash3_tbl7_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0},
-        {"hash3_tbl6_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0},
-        {"hash3_tbl5_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0},
-        {"hash3_tbl4_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_wr_rsp_cfg_reg[] = 
-    {
-        {"wr_rsp_fifo_cfg", DPP_FIELD_FLAG_RW, 9, 10, 0x18c, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_hash_mono_flag_reg[] = 
-    {
-        {"hash3_mono_flag", DPP_FIELD_FLAG_RW, 31, 8, 0x0, 0x0},
-        {"hash2_mono_flag", DPP_FIELD_FLAG_RW, 23, 8, 0x0, 0x0},
-        {"hash1_mono_flag", DPP_FIELD_FLAG_RW, 15, 8, 0x0, 0x0},
-        {"hash0_mono_flag", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_hash10_ext_crc_cfg_reg[] = 
-    {
-        {"hash1_crc_cfg", DPP_FIELD_FLAG_RW, 31, 16, 0x5555, 0x0},
-        {"hash0_crc_cfg", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_hash32_ext_crc_cfg_reg[] = 
-    {
-        {"hash3_crc_cfg", DPP_FIELD_FLAG_RW, 31, 16, 0xffff, 0x0},
-        {"hash2_crc_cfg", DPP_FIELD_FLAG_RW, 15, 16, 0xaaaa, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_zblock_service_configure_reg[] = 
-    {
-        {"service_sel", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0},
-        {"hash_channel_sel", DPP_FIELD_FLAG_RW, 2, 2, 0x0, 0x0},
-        {"st_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_zblock_hash_zcell_mono_reg[] = 
-    {
-        {"ha_zcell3_mono_flag", DPP_FIELD_FLAG_RW, 27, 1, 0x0, 0x0},
-        {"ha_zcell3_tbl_id", DPP_FIELD_FLAG_RW, 26, 3, 0x0, 0x0},
-        {"ha_zcell2_mono_flag", DPP_FIELD_FLAG_RW, 19, 1, 0x0, 0x0},
-        {"ha_zcell2_tbl_id", DPP_FIELD_FLAG_RW, 18, 3, 0x0, 0x0},
-        {"ha_zcell1_mono_flag", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0},
-        {"ha_zcell1_tbl_id", DPP_FIELD_FLAG_RW, 10, 3, 0x0, 0x0},
-        {"ha_zcell0_mono_flag", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0},
-        {"ha_zcell0_tbl_id", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se4k_se_alg_zlock_hash_zreg_mono_reg[] = 
-    {
-        {"ha_zreg3_mono_flag", DPP_FIELD_FLAG_RW, 27, 1, 0x0, 0x0},
-        {"ha_zreg3_tbl_id", DPP_FIELD_FLAG_RW, 26, 3, 0x0, 0x0},
-        {"ha_zreg2_mono_flag", DPP_FIELD_FLAG_RW, 19, 1, 0x0, 0x0},
-        {"ha_zreg2_tbl_id", DPP_FIELD_FLAG_RW, 18, 3, 0x0, 0x0},
-        {"ha_zreg1_mono_flag", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0},
-        {"ha_zreg1_tbl_id", DPP_FIELD_FLAG_RW, 10, 3, 0x0, 0x0},
-        {"ha_zreg0_mono_flag", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0},
-        {"ha_zreg0_tbl_id", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_init_done_reg[] = 
-    {
-        {"init_done", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cpu_ind_wdat0_reg[] = 
-    {
-        {"cpu_ind_wdat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cpu_ind_wdat1_reg[] = 
-    {
-        {"cpu_ind_wdat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cpu_ind_wdat2_reg[] = 
-    {
-        {"cpu_ind_wdat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cpu_ind_wdat3_reg[] = 
-    {
-        {"cpu_ind_wdat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = 
-    {
-        {"cpu_ind_rw", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"cpu_ind_rd_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0},
-        {"cpu_req_mode", DPP_FIELD_FLAG_RW, 27, 2, 0x0, 0x0},
-        {"cpu_ind_addr", DPP_FIELD_FLAG_RW, 25, 26, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rd_done_reg[] = 
-    {
-        {"cpu_ind_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rdat0_reg[] = 
-    {
-        {"cpu_ind_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rdat1_reg[] = 
-    {
-        {"cpu_ind_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rdat2_reg[] = 
-    {
-        {"cpu_ind_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rdat3_reg[] = 
-    {
-        {"cpu_ind_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cfg_plcr_mono_reg[] = 
-    {
-        {"cfg_plcr_mono", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_wr_arb_cpu_rdy_reg[] = 
-    {
-        {"wr_arb_cpu_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_tm_stat_en_cfg_reg[] = 
-    {
-        {"tm_stat_en_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_wdat0_reg[] = 
-    {
-        {"ddr_wdat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_dir_arbi_ser_rpful_reg[] = 
-    {
-        {"dir_arbi_ser_rpful", DPP_FIELD_FLAG_RW, 9, 10, 0x14a, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cfg_wr_arbi_pful2_reg[] = 
-    {
-        {"hash_wr_pful", DPP_FIELD_FLAG_RW, 19, 10, 0x14a, 0x0},
-        {"dir_wr_pful", DPP_FIELD_FLAG_RW, 9, 10, 0x14a, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_etm_tbl_cfg_reg[] = 
-    {
-        {"etm_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cfg_cash_addr_pful_reg[] = 
-    {
-        {"cfg_cash_addr_pful", DPP_FIELD_FLAG_RW, 19, 20, 0x7e1f8, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ctrl_rfifo_cfg_reg[] = 
-    {
-        {"brst_fwft_fifo_prog_empty_assert", DPP_FIELD_FLAG_RW, 31, 10, 0x2, 0x0},
-        {"brst_fwft_fifo_prog_empty_negate", DPP_FIELD_FLAG_RW, 21, 10, 0x2, 0x0},
-        {"brst_fwft_fifo_prog_full_assert", DPP_FIELD_FLAG_RW, 11, 6, 0x18, 0x0},
-        {"brst_fwft_fifo_prog_full_negate", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cache_req_fifo_cfg_reg[] = 
-    {
-        {"srch_fifo_pfull_assert", DPP_FIELD_FLAG_RW, 9, 5, 0xc, 0x0},
-        {"srch_fifo_pfull_negate", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_wdat0_reg[] = 
-    {
-        {"cpu_ind_eram_wdat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_etm_port_sel_cfg_reg[] = 
-    {
-        {"etm_port0_sel_cfg", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0},
-        {"etm_port1_sel_cfg", DPP_FIELD_FLAG_RW, 14, 5, 0x1, 0x0},
-        {"etm_port2_sel_cfg", DPP_FIELD_FLAG_RW, 9, 5, 0xf, 0x0},
-        {"etm_port3_sel_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_tm_stat_cfg_reg[] = 
-    {
-        {"stat_overflow_mode", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"tm_stat_mode_cfg", DPP_FIELD_FLAG_RW, 6, 3, 0x4, 0x0},
-        {"tm_flow_control_cfg", DPP_FIELD_FLAG_RW, 3, 4, 0xf, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_ppu_eram_depth_reg[] = 
-    {
-        {"ppu_eram_depth", DPP_FIELD_FLAG_RW, 18, 19, 0x38000, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_ppu_eram_base_addr_reg[] = 
-    {
-        {"ppu_eram_base_addr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_ppu_ddr_base_addr_reg[] = 
-    {
-        {"ppu_ddr_base_addr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_plcr0_base_addr_reg[] = 
-    {
-        {"plcr0_base_addr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_etm_stat_start_addr_cfg_reg[] = 
-    {
-        {"etm_stat_start_addr_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_etm_stat_depth_cfg_reg[] = 
-    {
-        {"etm_stat_depth_cfg", DPP_FIELD_FLAG_RW, 2, 3, 0x5, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cycle_mov_en_cfg_reg[] = 
-    {
-        {"cycle_mov_en_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat0_reg[] = 
-    {
-        {"wdat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_ctrl_tmp0_reg[] = 
-    {
-        {"reg_tcam_flag", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0},
-        {"flush", DPP_FIELD_FLAG_RW, 29, 8, 0x0, 0x0},
-        {"rd_wr", DPP_FIELD_FLAG_RW, 21, 1, 0x0, 0x0},
-        {"wr_mode", DPP_FIELD_FLAG_RW, 20, 8, 0x0, 0x0},
-        {"dat_or_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x0, 0x0},
-        {"ram_sel", DPP_FIELD_FLAG_RW, 11, 3, 0x0, 0x0},
-        {"addr", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_ctrl_tmp1_reg[] = 
-    {
-        {"row_or_col_msk", DPP_FIELD_FLAG_RW, 9, 1, 0x0, 0x0},
-        {"vben", DPP_FIELD_FLAG_RW, 8, 1, 0x0, 0x0},
-        {"vbit", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_rd_done_reg[] = 
-    {
-        {"cpu_ind_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat0_reg[] = 
-    {
-        {"cpu_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat1_reg[] = 
-    {
-        {"cpu_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat2_reg[] = 
-    {
-        {"cpu_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat3_reg[] = 
-    {
-        {"cpu_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat4_reg[] = 
-    {
-        {"cpu_rdat4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat5_reg[] = 
-    {
-        {"cpu_rdat5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat6_reg[] = 
-    {
-        {"cpu_rdat6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat7_reg[] = 
-    {
-        {"cpu_rdat7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat8_reg[] = 
-    {
-        {"cpu_rdat8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat9_reg[] = 
-    {
-        {"cpu_rdat9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat10_reg[] = 
-    {
-        {"cpu_rdat10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat11_reg[] = 
-    {
-        {"cpu_rdat11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat12_reg[] = 
-    {
-        {"cpu_rdat12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat13_reg[] = 
-    {
-        {"cpu_rdat13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat14_reg[] = 
-    {
-        {"cpu_rdat14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat15_reg[] = 
-    {
-        {"cpu_rdat15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat16_reg[] = 
-    {
-        {"cpu_rdat16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat17_reg[] = 
-    {
-        {"cpu_rdat17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat18_reg[] = 
-    {
-        {"cpu_rdat18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_rdat19_reg[] = 
-    {
-        {"cpu_rdat19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_qvbo_reg[] = 
-    {
-        {"qvbo", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cnt_overflow_mode_reg[] = 
-    {
-        {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = 
-    {
-        {"cara_drop", DPP_FIELD_FLAG_RW, 147, 1, 0x0, 0x0},
-        {"cara_plcr_en", DPP_FIELD_FLAG_RW, 146, 1, 0x0, 0x0},
-        {"cara_profile_id", DPP_FIELD_FLAG_RW, 145, 9, 0x0, 0x0},
-        {"cara_tq_h", DPP_FIELD_FLAG_RO, 136, 13, 0x0, 0x0},
-        {"cara_tq_l", DPP_FIELD_FLAG_RO, 123, 32, 0x0, 0x0},
-        {"cara_ted", DPP_FIELD_FLAG_RO, 91, 19, 0x0, 0x0},
-        {"cara_tcd", DPP_FIELD_FLAG_RO, 72, 19, 0x0, 0x0},
-        {"cara_tei", DPP_FIELD_FLAG_RO, 53, 27, 0x0, 0x0},
-        {"cara_tci", DPP_FIELD_FLAG_RO, 26, 27, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_profile_ram1_255_0_reg[] = 
-    {
-        {"cara_profile_wr", DPP_FIELD_FLAG_RW, 224, 1, 0x0, 0x0},
-        {"cara_pkt_sign", DPP_FIELD_FLAG_RW, 216, 1, 0x0, 0x0},
-        {"cara_cd", DPP_FIELD_FLAG_RW, 215, 2, 0x0, 0x0},
-        {"cara_cf", DPP_FIELD_FLAG_RW, 213, 1, 0x0, 0x0},
-        {"cara_cm", DPP_FIELD_FLAG_RW, 212, 1, 0x0, 0x0},
-        {"cara_eir", DPP_FIELD_FLAG_RW, 211, 24, 0x0, 0x0},
-        {"cara_cir", DPP_FIELD_FLAG_RW, 187, 24, 0x0, 0x0},
-        {"cara_ebs_pbs", DPP_FIELD_FLAG_RW, 163, 27, 0x0, 0x0},
-        {"cara_cbs", DPP_FIELD_FLAG_RW, 136, 27, 0x0, 0x0},
-        {"cara_c_pri1", DPP_FIELD_FLAG_RW, 109, 5, 0x0, 0x0},
-        {"cara_c_pri2", DPP_FIELD_FLAG_RW, 104, 5, 0x0, 0x0},
-        {"cara_c_pri3", DPP_FIELD_FLAG_RW, 99, 5, 0x0, 0x0},
-        {"cara_c_pri4", DPP_FIELD_FLAG_RW, 94, 5, 0x0, 0x0},
-        {"cara_c_pri5", DPP_FIELD_FLAG_RW, 89, 5, 0x0, 0x0},
-        {"cara_c_pri6", DPP_FIELD_FLAG_RW, 84, 5, 0x0, 0x0},
-        {"cara_c_pri7", DPP_FIELD_FLAG_RW, 79, 5, 0x0, 0x0},
-        {"cara_e_g_pri1", DPP_FIELD_FLAG_RW, 74, 5, 0x0, 0x0},
-        {"cara_e_g_pri2", DPP_FIELD_FLAG_RW, 69, 5, 0x0, 0x0},
-        {"cara_e_g_pri3", DPP_FIELD_FLAG_RW, 64, 5, 0x0, 0x0},
-        {"cara_e_g_pri4", DPP_FIELD_FLAG_RW, 59, 5, 0x0, 0x0},
-        {"cara_e_g_pri5", DPP_FIELD_FLAG_RW, 54, 5, 0x0, 0x0},
-        {"cara_e_g_pri6", DPP_FIELD_FLAG_RW, 49, 5, 0x0, 0x0},
-        {"cara_e_g_pri7", DPP_FIELD_FLAG_RW, 44, 5, 0x0, 0x0},
-        {"cara_e_y_pri0", DPP_FIELD_FLAG_RW, 39, 5, 0x0, 0x0},
-        {"cara_e_y_pri1", DPP_FIELD_FLAG_RW, 34, 5, 0x0, 0x0},
-        {"cara_e_y_pri2", DPP_FIELD_FLAG_RW, 29, 5, 0x0, 0x0},
-        {"cara_e_y_pri3", DPP_FIELD_FLAG_RW, 24, 5, 0x0, 0x0},
-        {"cara_e_y_pri4", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0},
-        {"cara_e_y_pri5", DPP_FIELD_FLAG_RW, 14, 5, 0x0, 0x0},
-        {"cara_e_y_pri6", DPP_FIELD_FLAG_RW, 9, 5, 0x0, 0x0},
-        {"cara_e_y_pri7", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_qovs_ram_ram2_reg[] = 
-    {
-        {"cara_qovs", DPP_FIELD_FLAG_RW, 1, 2, 0x2, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_look_up_table1_reg[] = 
-    {
-        {"cara_flow_id", DPP_FIELD_FLAG_RW, 14, 12, 0x0, 0x0},
-        {"cara_sp", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_pkt_des_i_cnt_reg[] = 
-    {
-        {"cara_pkt_des_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_green_pkt_i_cnt_reg[] = 
-    {
-        {"cara_green_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_yellow_pkt_i_cnt_reg[] = 
-    {
-        {"cara_yellow_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_red_pkt_i_cnt_reg[] = 
-    {
-        {"cara_red_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_pkt_des_o_cnt_reg[] = 
-    {
-        {"cara_pkt_des_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_green_pkt_o_cnt_reg[] = 
-    {
-        {"cara_green_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_yellow_pkt_o_cnt_reg[] = 
-    {
-        {"cara_yellow_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_red_pkt_o_cnt_reg[] = 
-    {
-        {"cara_red_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_pkt_des_fc_for_cfg_cnt_reg[] = 
-    {
-        {"cara_pkt_des_fc_for_cfg_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_appoint_qnum_or_sp_reg[] = 
-    {
-        {"cara_appoint_qnum_or_not", DPP_FIELD_FLAG_RW, 19, 1, 0x0, 0x0},
-        {"cara_appoint_sp_or_not", DPP_FIELD_FLAG_RW, 18, 1, 0x0, 0x0},
-        {"cara_plcr_stat_sp", DPP_FIELD_FLAG_RW, 17, 3, 0x0, 0x0},
-        {"cara_plcr_stat_qnum", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_cfgmt_count_mode_reg[] = 
-    {
-        {"cara_cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"cara_cfgmt_count_rd_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_pkt_size_cnt_reg[] = 
-    {
-        {"cara_pkt_size_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_plcr_init_dont_reg[] = 
-    {
-        {"cara_plcr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = 
-    {
-        {"carb_drop", DPP_FIELD_FLAG_RW, 147, 1, 0x0, 0x0},
-        {"carb_plcr_en", DPP_FIELD_FLAG_RW, 146, 1, 0x0, 0x0},
-        {"carb_profile_id", DPP_FIELD_FLAG_RW, 145, 9, 0x0, 0x0},
-        {"carb_tq_h", DPP_FIELD_FLAG_RO, 136, 13, 0x0, 0x0},
-        {"carb_tq_l", DPP_FIELD_FLAG_RO, 123, 32, 0x0, 0x0},
-        {"carb_ted", DPP_FIELD_FLAG_RO, 91, 19, 0x0, 0x0},
-        {"carb_tcd", DPP_FIELD_FLAG_RO, 72, 19, 0x0, 0x0},
-        {"carb_tei", DPP_FIELD_FLAG_RO, 53, 27, 0x0, 0x0},
-        {"carb_tci", DPP_FIELD_FLAG_RO, 26, 27, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_profile_ram1_255_0_reg[] = 
-    {
-        {"carb_profile_wr", DPP_FIELD_FLAG_RW, 224, 1, 0x0, 0x0},
-        {"carb_random_discard_en_e", DPP_FIELD_FLAG_RW, 218, 1, 0x0, 0x0},
-        {"carb_random_discard_en_c", DPP_FIELD_FLAG_RW, 217, 1, 0x0, 0x0},
-        {"carb_pkt_sign", DPP_FIELD_FLAG_RW, 216, 1, 0x0, 0x0},
-        {"carb_cd", DPP_FIELD_FLAG_RW, 215, 2, 0x0, 0x0},
-        {"carb_cf", DPP_FIELD_FLAG_RW, 213, 1, 0x0, 0x0},
-        {"carb_cm", DPP_FIELD_FLAG_RW, 212, 1, 0x0, 0x0},
-        {"carb_eir", DPP_FIELD_FLAG_RW, 211, 24, 0x0, 0x0},
-        {"carb_cir", DPP_FIELD_FLAG_RW, 187, 24, 0x0, 0x0},
-        {"carb_ebs_pbs", DPP_FIELD_FLAG_RW, 163, 27, 0x0, 0x0},
-        {"carb_cbs", DPP_FIELD_FLAG_RW, 136, 27, 0x0, 0x0},
-        {"carb_c_pri1", DPP_FIELD_FLAG_RW, 109, 5, 0x0, 0x0},
-        {"carb_c_pri2", DPP_FIELD_FLAG_RW, 104, 5, 0x0, 0x0},
-        {"carb_c_pri3", DPP_FIELD_FLAG_RW, 99, 5, 0x0, 0x0},
-        {"carb_c_pri4", DPP_FIELD_FLAG_RW, 94, 5, 0x0, 0x0},
-        {"carb_c_pri5", DPP_FIELD_FLAG_RW, 89, 5, 0x0, 0x0},
-        {"carb_c_pri6", DPP_FIELD_FLAG_RW, 84, 5, 0x0, 0x0},
-        {"carb_c_pri7", DPP_FIELD_FLAG_RW, 79, 5, 0x0, 0x0},
-        {"carb_e_g_pri1", DPP_FIELD_FLAG_RW, 74, 5, 0x0, 0x0},
-        {"carb_e_g_pri2", DPP_FIELD_FLAG_RW, 69, 5, 0x0, 0x0},
-        {"carb_e_g_pri3", DPP_FIELD_FLAG_RW, 64, 5, 0x0, 0x0},
-        {"carb_e_g_pri4", DPP_FIELD_FLAG_RW, 59, 5, 0x0, 0x0},
-        {"carb_e_g_pri5", DPP_FIELD_FLAG_RW, 54, 5, 0x0, 0x0},
-        {"carb_e_g_pri6", DPP_FIELD_FLAG_RW, 49, 5, 0x0, 0x0},
-        {"carb_e_g_pri7", DPP_FIELD_FLAG_RW, 44, 5, 0x0, 0x0},
-        {"carb_e_y_pri0", DPP_FIELD_FLAG_RW, 39, 5, 0x0, 0x0},
-        {"carb_e_y_pri1", DPP_FIELD_FLAG_RW, 34, 5, 0x0, 0x0},
-        {"carb_e_y_pri2", DPP_FIELD_FLAG_RW, 29, 5, 0x0, 0x0},
-        {"carb_e_y_pri3", DPP_FIELD_FLAG_RW, 24, 5, 0x0, 0x0},
-        {"carb_e_y_pri4", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0},
-        {"carb_e_y_pri5", DPP_FIELD_FLAG_RW, 14, 5, 0x0, 0x0},
-        {"carb_e_y_pri6", DPP_FIELD_FLAG_RW, 9, 5, 0x0, 0x0},
-        {"carb_e_y_pri7", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_qovs_ram_ram2_reg[] = 
-    {
-        {"carb_qovs", DPP_FIELD_FLAG_RW, 1, 2, 0x2, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_look_up_table2_reg[] = 
-    {
-        {"carb_flow_id", DPP_FIELD_FLAG_RW, 12, 10, 0x0, 0x0},
-        {"carb_sp", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_pkt_des_i_cnt_reg[] = 
-    {
-        {"carb_pkt_des_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_green_pkt_i_cnt_reg[] = 
-    {
-        {"carb_green_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_yellow_pkt_i_cnt_reg[] = 
-    {
-        {"carb_yellow_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_red_pkt_i_cnt_reg[] = 
-    {
-        {"carb_red_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_pkt_des_o_cnt_reg[] = 
-    {
-        {"carb_pkt_des_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_green_pkt_o_cnt_reg[] = 
-    {
-        {"carb_green_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_yellow_pkt_o_cnt_reg[] = 
-    {
-        {"carb_yellow_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_red_pkt_o_cnt_reg[] = 
-    {
-        {"carb_red_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_pkt_des_fc_for_cfg_cnt_reg[] = 
-    {
-        {"carb_pkt_des_fc_for_cfg_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_appoint_qnum_or_sp_reg[] = 
-    {
-        {"carb_appoint_qnum_or_not", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0},
-        {"carb_appoint_sp_or_not", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0},
-        {"carb_plcr_stat_sp", DPP_FIELD_FLAG_RW, 14, 3, 0x0, 0x0},
-        {"carb_plcr_stat_qnum", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_cfgmt_count_mode_reg[] = 
-    {
-        {"carb_cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"carb_cfgmt_count_rd_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_pkt_size_cnt_reg[] = 
-    {
-        {"carb_pkt_size_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_plcr_init_dont_reg[] = 
-    {
-        {"carb_plcr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = 
-    {
-        {"carc_drop", DPP_FIELD_FLAG_RW, 147, 1, 0x0, 0x0},
-        {"carc_plcr_en", DPP_FIELD_FLAG_RW, 146, 1, 0x0, 0x0},
-        {"carc_profile_id", DPP_FIELD_FLAG_RW, 145, 9, 0x0, 0x0},
-        {"carc_tq_h", DPP_FIELD_FLAG_RO, 136, 13, 0x0, 0x0},
-        {"carc_tq_l", DPP_FIELD_FLAG_RO, 123, 32, 0x0, 0x0},
-        {"carc_ted", DPP_FIELD_FLAG_RO, 91, 19, 0x0, 0x0},
-        {"carc_tcd", DPP_FIELD_FLAG_RO, 72, 19, 0x0, 0x0},
-        {"carc_tei", DPP_FIELD_FLAG_RO, 53, 27, 0x0, 0x0},
-        {"carc_tci", DPP_FIELD_FLAG_RO, 26, 27, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_profile_ram1_255_0_reg[] = 
-    {
-        {"carc_profile_wr", DPP_FIELD_FLAG_RW, 224, 1, 0x0, 0x0},
-        {"carc_random_discard_en_e", DPP_FIELD_FLAG_RW, 218, 1, 0x0, 0x0},
-        {"carc_random_discard_en_c", DPP_FIELD_FLAG_RW, 217, 1, 0x0, 0x0},
-        {"carc_pkt_sign", DPP_FIELD_FLAG_RW, 216, 1, 0x0, 0x0},
-        {"carc_cd", DPP_FIELD_FLAG_RW, 215, 2, 0x0, 0x0},
-        {"carc_cf", DPP_FIELD_FLAG_RW, 213, 1, 0x0, 0x0},
-        {"carc_cm", DPP_FIELD_FLAG_RW, 212, 1, 0x0, 0x0},
-        {"carc_eir", DPP_FIELD_FLAG_RW, 211, 24, 0x0, 0x0},
-        {"carc_cir", DPP_FIELD_FLAG_RW, 187, 24, 0x0, 0x0},
-        {"carc_ebs_pbs", DPP_FIELD_FLAG_RW, 163, 27, 0x0, 0x0},
-        {"carc_cbs", DPP_FIELD_FLAG_RW, 136, 27, 0x0, 0x0},
-        {"carc_c_pri1", DPP_FIELD_FLAG_RW, 109, 5, 0x0, 0x0},
-        {"carc_c_pri2", DPP_FIELD_FLAG_RW, 104, 5, 0x0, 0x0},
-        {"carc_c_pri3", DPP_FIELD_FLAG_RW, 99, 5, 0x0, 0x0},
-        {"carc_c_pri4", DPP_FIELD_FLAG_RW, 94, 5, 0x0, 0x0},
-        {"carc_c_pri5", DPP_FIELD_FLAG_RW, 89, 5, 0x0, 0x0},
-        {"carc_c_pri6", DPP_FIELD_FLAG_RW, 84, 5, 0x0, 0x0},
-        {"carc_c_pri7", DPP_FIELD_FLAG_RW, 79, 5, 0x0, 0x0},
-        {"carc_e_g_pri1", DPP_FIELD_FLAG_RW, 74, 5, 0x0, 0x0},
-        {"carc_e_g_pri2", DPP_FIELD_FLAG_RW, 69, 5, 0x0, 0x0},
-        {"carc_e_g_pri3", DPP_FIELD_FLAG_RW, 64, 5, 0x0, 0x0},
-        {"carc_e_g_pri4", DPP_FIELD_FLAG_RW, 59, 5, 0x0, 0x0},
-        {"carc_e_g_pri5", DPP_FIELD_FLAG_RW, 54, 5, 0x0, 0x0},
-        {"carc_e_g_pri6", DPP_FIELD_FLAG_RW, 49, 5, 0x0, 0x0},
-        {"carc_e_g_pri7", DPP_FIELD_FLAG_RW, 44, 5, 0x0, 0x0},
-        {"carc_e_y_pri0", DPP_FIELD_FLAG_RW, 39, 5, 0x0, 0x0},
-        {"carc_e_y_pri1", DPP_FIELD_FLAG_RW, 34, 5, 0x0, 0x0},
-        {"carc_e_y_pri2", DPP_FIELD_FLAG_RW, 29, 5, 0x0, 0x0},
-        {"carc_e_y_pri3", DPP_FIELD_FLAG_RW, 24, 5, 0x0, 0x0},
-        {"carc_e_y_pri4", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0},
-        {"carc_e_y_pri5", DPP_FIELD_FLAG_RW, 14, 5, 0x0, 0x0},
-        {"carc_e_y_pri6", DPP_FIELD_FLAG_RW, 9, 5, 0x0, 0x0},
-        {"carc_e_y_pri7", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_qovs_ram_ram2_reg[] = 
-    {
-        {"carc_qovs", DPP_FIELD_FLAG_RW, 1, 2, 0x2, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_pkt_des_i_cnt_reg[] = 
-    {
-        {"carc_pkt_des_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_green_pkt_i_cnt_reg[] = 
-    {
-        {"carc_green_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_yellow_pkt_i_cnt_reg[] = 
-    {
-        {"carc_yellow_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_red_pkt_i_cnt_reg[] = 
-    {
-        {"carc_red_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_pkt_des_o_cnt_reg[] = 
-    {
-        {"carc_pkt_des_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_green_pkt_o_cnt_reg[] = 
-    {
-        {"carc_green_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_yellow_pkt_o_cnt_reg[] = 
-    {
-        {"carc_yellow_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_red_pkt_o_cnt_reg[] = 
-    {
-        {"carc_red_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_pkt_des_fc_for_cfg_cnt_reg[] = 
-    {
-        {"carc_pkt_des_fc_for_cfg_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_appoint_qnum_or_sp_reg[] = 
-    {
-        {"carc_appoint_qnum_or_not", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0},
-        {"carc_appoint_sp_or_not", DPP_FIELD_FLAG_RW, 13, 1, 0x0, 0x0},
-        {"carc_plcr_stat_sp", DPP_FIELD_FLAG_RW, 12, 3, 0x0, 0x0},
-        {"carc_plcr_stat_qnum", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_cfgmt_count_mode_reg[] = 
-    {
-        {"carc_cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"carc_cfgmt_count_rd_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_pkt_size_cnt_reg[] = 
-    {
-        {"carc_pkt_size_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_plcr_init_dont_reg[] = 
-    {
-        {"carc_plcr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_random_ram_reg[] = 
-    {
-        {"para8_e", DPP_FIELD_FLAG_RW, 491, 27, 0x0, 0x0},
-        {"para7_e", DPP_FIELD_FLAG_RW, 464, 27, 0x0, 0x0},
-        {"para6_e", DPP_FIELD_FLAG_RW, 437, 27, 0x0, 0x0},
-        {"para5_e", DPP_FIELD_FLAG_RW, 410, 14, 0x0, 0x0},
-        {"para4_h_e", DPP_FIELD_FLAG_RW, 396, 9, 0x0, 0x0},
-        {"para4_l_e", DPP_FIELD_FLAG_RW, 387, 32, 0x0, 0x0},
-        {"para3_e", DPP_FIELD_FLAG_RW, 355, 14, 0x0, 0x0},
-        {"para2_h_e", DPP_FIELD_FLAG_RW, 341, 9, 0x0, 0x0},
-        {"para2_l_e", DPP_FIELD_FLAG_RW, 332, 32, 0x0, 0x0},
-        {"para1_e", DPP_FIELD_FLAG_RW, 300, 14, 0x0, 0x0},
-        {"para0_h_e", DPP_FIELD_FLAG_RW, 286, 9, 0x0, 0x0},
-        {"para0_l_e", DPP_FIELD_FLAG_RW, 277, 32, 0x0, 0x0},
-        {"para8_c", DPP_FIELD_FLAG_RW, 245, 27, 0x0, 0x0},
-        {"para7_c", DPP_FIELD_FLAG_RW, 218, 27, 0x0, 0x0},
-        {"para6_c", DPP_FIELD_FLAG_RW, 191, 27, 0x0, 0x0},
-        {"para5_c", DPP_FIELD_FLAG_RW, 164, 14, 0x0, 0x0},
-        {"para4_h_c", DPP_FIELD_FLAG_RW, 150, 9, 0x0, 0x0},
-        {"para4_l_c", DPP_FIELD_FLAG_RW, 141, 32, 0x0, 0x0},
-        {"para3_c", DPP_FIELD_FLAG_RW, 109, 14, 0x0, 0x0},
-        {"para2_h_c", DPP_FIELD_FLAG_RW, 95, 9, 0x0, 0x0},
-        {"para2_l_c", DPP_FIELD_FLAG_RW, 86, 32, 0x0, 0x0},
-        {"para1_c", DPP_FIELD_FLAG_RW, 54, 14, 0x0, 0x0},
-        {"para0_h_c", DPP_FIELD_FLAG_RW, 40, 9, 0x0, 0x0},
-        {"para0_l_c", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_random_ram_reg[] = 
-    {
-        {"para8_e", DPP_FIELD_FLAG_RW, 491, 27, 0x0, 0x0},
-        {"para7_e", DPP_FIELD_FLAG_RW, 464, 27, 0x0, 0x0},
-        {"para6_e", DPP_FIELD_FLAG_RW, 437, 27, 0x0, 0x0},
-        {"para5_e", DPP_FIELD_FLAG_RW, 410, 14, 0x0, 0x0},
-        {"para4_h_e", DPP_FIELD_FLAG_RW, 396, 9, 0x0, 0x0},
-        {"para4_l_e", DPP_FIELD_FLAG_RW, 387, 32, 0x0, 0x0},
-        {"para3_e", DPP_FIELD_FLAG_RW, 355, 14, 0x0, 0x0},
-        {"para2_h_e", DPP_FIELD_FLAG_RW, 341, 9, 0x0, 0x0},
-        {"para2_l_e", DPP_FIELD_FLAG_RW, 332, 32, 0x0, 0x0},
-        {"para1_e", DPP_FIELD_FLAG_RW, 300, 14, 0x0, 0x0},
-        {"para0_h_e", DPP_FIELD_FLAG_RW, 286, 9, 0x0, 0x0},
-        {"para0_l_e", DPP_FIELD_FLAG_RW, 277, 32, 0x0, 0x0},
-        {"para8_c", DPP_FIELD_FLAG_RW, 245, 27, 0x0, 0x0},
-        {"para7_c", DPP_FIELD_FLAG_RW, 218, 27, 0x0, 0x0},
-        {"para6_c", DPP_FIELD_FLAG_RW, 191, 27, 0x0, 0x0},
-        {"para5_c", DPP_FIELD_FLAG_RW, 164, 14, 0x0, 0x0},
-        {"para4_h_c", DPP_FIELD_FLAG_RW, 150, 9, 0x0, 0x0},
-        {"para4_l_c", DPP_FIELD_FLAG_RW, 141, 32, 0x0, 0x0},
-        {"para3_c", DPP_FIELD_FLAG_RW, 109, 14, 0x0, 0x0},
-        {"para2_h_c", DPP_FIELD_FLAG_RW, 95, 9, 0x0, 0x0},
-        {"para2_l_c", DPP_FIELD_FLAG_RW, 86, 32, 0x0, 0x0},
-        {"para1_c", DPP_FIELD_FLAG_RW, 54, 14, 0x0, 0x0},
-        {"para0_h_c", DPP_FIELD_FLAG_RW, 40, 9, 0x0, 0x0},
-        {"para0_l_c", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_begin_flow_id_reg[] = 
-    {
-        {"cara_begin_flow_id", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carb_begin_flow_id_reg[] = 
-    {
-        {"carb_begin_flow_id", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_carc_begin_flow_id_reg[] = 
-    {
-        {"carc_begin_flow_id", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_prog_full_assert_cfg_w_reg[] = 
-    {
-        {"prog_full_assert_cfg_w", DPP_FIELD_FLAG_RW, 7, 8, 0xe0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_prog_full_negate_cfg_w_reg[] = 
-    {
-        {"prog_full_negate_cfg_w", DPP_FIELD_FLAG_RW, 7, 8, 0xdf, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_timeout_limit_reg[] = 
-    {
-        {"timeout_limit", DPP_FIELD_FLAG_RW, 15, 16, 0x100, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_pkt_des_fifo_overflow_reg[] = 
-    {
-        {"pkt_des_fifo_overflow", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_pkt_des_fifo_underflow_reg[] = 
-    {
-        {"pkt_des_fifo_underflow", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_pkt_des_fifo_prog_full_reg[] = 
-    {
-        {"pkt_des_fifo_prog_full", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_pkt_des_fifo_prog_empty_reg[] = 
-    {
-        {"pkt_des_fifo_prog_empty", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_pkt_des_fifo_full_reg[] = 
-    {
-        {"pkt_des_fifo_full", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_pkt_des_fifo_empty_reg[] = 
-    {
-        {"pkt_des_fifo_empty", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_pkt_size_offset_reg[] = 
-    {
-        {"pkt_size_offset", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_car_plcr_init_dont_reg[] = 
-    {
-        {"plcr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_max_pkt_size_a_reg[] = 
-    {
-        {"max_pkt_size_a", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_max_pkt_size_b_reg[] = 
-    {
-        {"max_pkt_size_b", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_max_pkt_size_c_reg[] = 
-    {
-        {"max_pkt_size_c", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_car_hierarchy_mode_reg[] = 
-    {
-        {"car_hierarchy_mode", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_prog_empty_assert_cfg_w_reg[] = 
-    {
-        {"prog_empty_assert_cfg_w", DPP_FIELD_FLAG_RW, 7, 8, 0x3, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_prog_empty_negate_cfg_w_reg[] = 
-    {
-        {"prog_empty_negate_cfg_w", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_pkt_des_fifo_ovf_int_reg[] = 
-    {
-        {"pkt_des_fifo_ovf_int", DPP_FIELD_FLAG_RO, 1, 2, 0x00, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_pkt_des_fifo_data_count_reg[] = 
-    {
-        {"pkt_des_fifo_data_count", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_pkt_des_fifo_udf_int_reg[] = 
-    {
-        {"pkt_des_fifo_udf_int", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_queue_ram0_159_0_pkt_reg[] = 
-    {
-        {"cara_drop", DPP_FIELD_FLAG_RW, 147, 1, 0x0, 0x0},
-        {"cara_plcr_en", DPP_FIELD_FLAG_RW, 146, 1, 0x0, 0x0},
-        {"cara_profile_id", DPP_FIELD_FLAG_RW, 145, 9, 0x0, 0x0},
-        {"cara_tq_h", DPP_FIELD_FLAG_RO, 136, 13, 0x0, 0x0},
-        {"cara_tq_l", DPP_FIELD_FLAG_RO, 123, 32, 0x0, 0x0},
-        {"cara_dc_high", DPP_FIELD_FLAG_RO, 50, 5, 0x0, 0x0},
-        {"cara_dc_low", DPP_FIELD_FLAG_RO, 45, 32, 0x0, 0x0},
-        {"cara_tc", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_car0_cara_profile_ram1_255_0_pkt_reg[] = 
-    {
-        {"cara_profile_wr", DPP_FIELD_FLAG_RW, 224, 1, 0x0, 0x0},
-        {"cara_pkt_sign", DPP_FIELD_FLAG_RW, 216, 1, 0x0, 0x0},
-        {"cara_pkt_cir", DPP_FIELD_FLAG_RW, 189, 30, 0x0, 0x0},
-        {"cara_pkt_cbs", DPP_FIELD_FLAG_RW, 150, 14, 0x0, 0x0},
-        {"cara_pri0", DPP_FIELD_FLAG_RW, 39, 5, 0x0, 0x0},
-        {"cara_pri1", DPP_FIELD_FLAG_RW, 34, 5, 0x0, 0x0},
-        {"cara_pri2", DPP_FIELD_FLAG_RW, 29, 5, 0x0, 0x0},
-        {"cara_pri3", DPP_FIELD_FLAG_RW, 24, 5, 0x0, 0x0},
-        {"cara_pri4", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0},
-        {"cara_pri5", DPP_FIELD_FLAG_RW, 14, 5, 0x0, 0x0},
-        {"cara_pri6", DPP_FIELD_FLAG_RW, 9, 5, 0x0, 0x0},
-        {"cara_pri7", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat4k_etcam_block0_7_port_id_cfg_reg[] = 
-    {
-        {"block7_port_id", DPP_FIELD_FLAG_RW, 31, 4, 0x0, 0x0},
-        {"block6_port_id", DPP_FIELD_FLAG_RW, 27, 4, 0x0, 0x0},
-        {"block5_port_id", DPP_FIELD_FLAG_RW, 23, 4, 0x0, 0x0},
-        {"block4_port_id", DPP_FIELD_FLAG_RW, 19, 4, 0x0, 0x0},
-        {"block3_port_id", DPP_FIELD_FLAG_RW, 15, 4, 0x0, 0x0},
-        {"block2_port_id", DPP_FIELD_FLAG_RW, 11, 4, 0x0, 0x0},
-        {"block1_port_id", DPP_FIELD_FLAG_RW, 7, 4, 0x0, 0x0},
-        {"block0_port_id", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat4k_etcam_block0_3_base_addr_cfg_reg[] = 
-    {
-        {"block3_base_addr_cfg", DPP_FIELD_FLAG_RW, 30, 7, 0x0, 0x0},
-        {"block2_base_addr_cfg", DPP_FIELD_FLAG_RW, 22, 7, 0x0, 0x0},
-        {"block1_base_addr_cfg", DPP_FIELD_FLAG_RW, 14, 7, 0x0, 0x0},
-        {"block0_base_addr_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat4k_etcam_block4_7_base_addr_cfg_reg[] = 
-    {
-        {"block7_base_addr_cfg", DPP_FIELD_FLAG_RW, 30, 7, 0x0, 0x0},
-        {"block6_base_addr_cfg", DPP_FIELD_FLAG_RW, 22, 7, 0x0, 0x0},
-        {"block5_base_addr_cfg", DPP_FIELD_FLAG_RW, 14, 7, 0x0, 0x0},
-        {"block4_base_addr_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_eram_wr_interval_cnt_reg[] = 
-    {
-        {"cfg_eram_wr_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_zcam_wr_interval_cnt_reg[] = 
-    {
-        {"cfg_zcam_wr_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_tcam_wr_interval_cnt_reg[] = 
-    {
-        {"cfg_zcam_wr_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_ddr_wr_interval_cnt_reg[] = 
-    {
-        {"cfg_ddr_wr_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_hash_wr_interval_cnt_reg[] = 
-    {
-        {"cfg_hash_wr_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_eram_rd_interval_cnt_reg[] = 
-    {
-        {"cfg_eram_rd_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_zcam_rd_interval_cnt_reg[] = 
-    {
-        {"cfg_zcam_rd_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_tcam_rd_interval_cnt_reg[] = 
-    {
-        {"cfg_tcam_rd_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_ddr_rd_interval_cnt_reg[] = 
-    {
-        {"cfg_ddr_rd_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_queue_lock_state_0_3_reg[] = 
-    {
-        {"cfg_dtb_queue_lock_state", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_axim0_w_convert_0_mode_reg[] = 
-    {
-        {"w_convert_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_axim0_r_convert_0_mode_reg[] = 
-    {
-        {"r_convert_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_axim0_aximr_os_reg[] = 
-    {
-        {"aximr_os", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_axim1_w_convert_1_mode_reg[] = 
-    {
-        {"w_convert_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_axim1_r_convert_1_mode_reg[] = 
-    {
-        {"r_convert_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_axis_axis_convert_mode_reg[] = 
-    {
-        {"w_r_convert_mode", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb4k_dtb_enq_cfg_queue_dtb_addr_h_0_127_reg[] = 
-    {
-        {"cfg_queue_dtb_addr_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb4k_dtb_enq_cfg_queue_dtb_addr_l_0_127_reg[] = 
-    {
-        {"cfg_queue_dtb_addr_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb4k_dtb_enq_cfg_queue_dtb_len_0_127_reg[] = 
-    {
-        {"cfg_dtb_cmd_type", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0},
-        {"cfg_dtb_cmd_int_en", DPP_FIELD_FLAG_RW, 29, 1, 0x0, 0x0},
-        {"cfg_queue_dtb_len", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg[] = 
-    {
-        {"info_queue_buf_space_left", DPP_FIELD_FLAG_RO, 5, 6, 0x20, 0x0},
-    };
-DPP_FIELD_T g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg[] = 
-    {
-        {"dbi_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"queue_en", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0},
-        {"cfg_epid", DPP_FIELD_FLAG_RW, 27, 4, 0x0, 0x0},
-        {"cfg_vfunc_num", DPP_FIELD_FLAG_RW, 23, 8, 0x0, 0x0},
-        {"cfg_vector", DPP_FIELD_FLAG_RW, 14, 7, 0x0, 0x0},
-        {"cfg_func_num", DPP_FIELD_FLAG_RW, 7, 3, 0x0, 0x0},
-        {"cfg_vfunc_active", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_ms_en_reg[] = 
-    {
-        {"cpu_trpgrx_ms_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_port_en_reg[] = 
-    {
-        {"cpu_trpgrx_port_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_look_en_reg[] = 
-    {
-        {"cpu_trpgrx_look_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_ram_almost_full_reg[] = 
-    {
-        {"cpu_trpgrx_ram_almost_full", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_ram_test_en_reg[] = 
-    {
-        {"cpu_trpgrx_ram_test_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_inmod_pfc_rdy_en_reg[] = 
-    {
-        {"cpu_trpgrx_inmod_pfc_rdy_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_h_reg[] = 
-    {
-        {"cpu_trpgrx_pkt_num_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_l_reg[] = 
-    {
-        {"cpu_trpgrx_pkt_num_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_h_reg[] = 
-    {
-        {"cpu_trpgrx_pkt_byte_num_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_l_reg[] = 
-    {
-        {"cpu_trpgrx_pkt_byte_num_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_cnt_clr_reg[] = 
-    {
-        {"cpu_trpgrx_pkt_cnt_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_fc_clk_freq_reg[] = 
-    {
-        {"cpu_trpgrx_fc_clk_freq", DPP_FIELD_FLAG_RW, 10, 11, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_fc_en_reg[] = 
-    {
-        {"cpu_trpgrx_fc_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_fc_token_add_num_reg[] = 
-    {
-        {"cpu_trpgrx_fc_token_add_num", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_fc_token_max_num_reg[] = 
-    {
-        {"cpu_trpgrx_fc_token_max_num", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_port_state_info_reg[] = 
-    {
-        {"cpu_trpgrx_port_state_info", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_reg[] = 
-    {
-        {"cpu_trpgrx_ram_past_max_dep", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_clr_reg[] = 
-    {
-        {"cpu_trpgrx_ram_past_max_dep_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_reg[] = 
-    {
-        {"cpu_trpgrx_pkt_past_max_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_clr_reg[] = 
-    {
-        {"cpu_trpgrx_pkt_past_max_len_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_reg[] = 
-    {
-        {"cpu_trpgrx_pkt_past_min_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_clr_reg[] = 
-    {
-        {"cpu_trpgrx_pkt_past_min_len_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_ram_trpg_rx_data_ram_reg[] = 
-    {
-        {"trpg_rx_data_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_ram_trpg_rx_info_ram_reg[] = 
-    {
-        {"trpg_rx_info_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_ms_en_reg[] = 
-    {
-        {"cpu_trpgtx_ms_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_port_en_reg[] = 
-    {
-        {"cpu_trpgtx_port_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_look_en_reg[] = 
-    {
-        {"cpu_trpgtx_look_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_ram_almost_full_reg[] = 
-    {
-        {"cpu_trpgtx_ram_almost_full", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_ram_test_en_reg[] = 
-    {
-        {"cpu_trpgtx_ram_test_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_h_reg[] = 
-    {
-        {"cpu_trpgtx_pkt_num_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_l_reg[] = 
-    {
-        {"cpu_trpgtx_pkt_num_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_h_reg[] = 
-    {
-        {"cpu_trpgtx_pkt_byte_num_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_l_reg[] = 
-    {
-        {"cpu_trpgtx_pkt_byte_num_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_cnt_clr_reg[] = 
-    {
-        {"cpu_trpgtx_pkt_cnt_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_fc_clk_freq_reg[] = 
-    {
-        {"cpu_trpgtx_fc_clk_freq", DPP_FIELD_FLAG_RW, 10, 11, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_fc_en_reg[] = 
-    {
-        {"cpu_trpgtx_fc_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_fc_token_add_num_reg[] = 
-    {
-        {"cpu_trpgtx_fc_token_add_num", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_fc_token_max_num_reg[] = 
-    {
-        {"cpu_trpgtx_fc_token_max_num", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_port_state_info_reg[] = 
-    {
-        {"cpu_trpgtx_port_state_info", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_reg[] = 
-    {
-        {"cpu_trpgtx_ram_past_max_dep", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_clr_reg[] = 
-    {
-        {"cpu_trpgtx_ram_past_max_dep_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_reg[] = 
-    {
-        {"cpu_trpgtx_pkt_past_max_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_clr_reg[] = 
-    {
-        {"cpu_trpgtx_pkt_past_max_len_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_reg[] = 
-    {
-        {"cpu_trpgtx_pkt_past_min_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_clr_reg[] = 
-    {
-        {"cpu_trpgtx_pkt_past_min_len_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_almost_full_reg[] = 
-    {
-        {"cpu_trpgtx_etm_ram_almost_full", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_test_en_reg[] = 
-    {
-        {"cpu_trpgtx_etm_ram_test_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_update_int_mask_reg[] = 
-    {
-        {"cpu_todtime_update_int_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_update_int_clr_reg[] = 
-    {
-        {"cpu_todtime_update_int_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_ram_test_en_reg[] = 
-    {
-        {"cpu_todtime_ram_test_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_ram_trpg_tx_data_ram_reg[] = 
-    {
-        {"trpg_tx_data_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_ram_trpg_tx_info_ram_reg[] = 
-    {
-        {"trpg_tx_info_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_etm_ram_trpg_tx_etm_data_ram_reg[] = 
-    {
-        {"trpg_tx_etm_data_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_etm_ram_trpg_tx_etm_info_ram_reg[] = 
-    {
-        {"trpg_tx_etm_info_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_chip_version_reg_reg[] = 
-    {
-        {"chip_version_reg", DPP_FIELD_FLAG_RO, 31, 4, 0x1, 0x0},
-        {"chip_sub_reg", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0},
-        {"chip_type_reg", DPP_FIELD_FLAG_RO, 23, 24, 0x211650, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_chip_date_reg_reg[] = 
-    {
-        {"chip_date_reg", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_cfgmt_crc_en_reg[] = 
-    {
-        {"cfgmt_crc_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_cfg_port_transfer_en_reg[] = 
-    {
-        {"cfg_port_transfer_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_tm_sa_work_mode_reg[] = 
-    {
-        {"tm_sa_work_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cfgmt_local_sa_id_reg[] = 
-    {
-        {"local_sa_id", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_olif_rdy_reg[] = 
-    {
-        {"cfgmt_block_mode", DPP_FIELD_FLAG_RO, 5, 2, 0x2, 0x0},
-        {"cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RO, 3, 1, 0x1, 0x0},
-        {"cfgmt_count_rd_mode", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"olif_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_emem_prog_full_reg[] = 
-    {
-        {"emem_prog_full_assert", DPP_FIELD_FLAG_RW, 24, 9, 0xb9, 0x0},
-        {"emem_prog_full_negate", DPP_FIELD_FLAG_RW, 8, 9, 0xac, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_port_order_fifo_full_reg[] = 
-    {
-        {"port_order_fifo_full_assert", DPP_FIELD_FLAG_RW, 22, 7, 0x32, 0x0},
-        {"port_order_fifo_full_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x32, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_olif_release_last_reg[] = 
-    {
-        {"olif_release_last_addr", DPP_FIELD_FLAG_RO, 24, 19, 0x0, 0x0},
-        {"olif_release_last_bank", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_olif_fifo_empty_state_reg[] = 
-    {
-        {"qmu_para_fifo_empty", DPP_FIELD_FLAG_RO, 2, 1, 0x1, 0x0},
-        {"emem_empty", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0},
-        {"imem_empty", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_qmu_olif_release_fc_cnt_reg[] = 
-    {
-        {"qmu_olif_release_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_olif_qmu_link_fc_cnt_reg[] = 
-    {
-        {"olif_qmu_link_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_lif0_link_fc_cnt_reg[] = 
-    {
-        {"lif0_link_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_olif_tmmu_fc_cnt_reg[] = 
-    {
-        {"olif_tmmu_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_olif_mmu_fc_cnt_reg[] = 
-    {
-        {"olif_mmu_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_olif_qmu_port_rdy_h_reg[] = 
-    {
-        {"olif_qmu_port_rdy_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_olif_qmu_port_rdy_l_reg[] = 
-    {
-        {"olif_qmu_port_rdy_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_lif0_port_rdy_h_reg[] = 
-    {
-        {"lif0_port_rdy_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_lif0_port_rdy_l_reg[] = 
-    {
-        {"lif0_port_rdy_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_qmu_olif_rd_sop_cnt_reg[] = 
-    {
-        {"qmu_olif_rd_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_qmu_olif_rd_eop_cnt_reg[] = 
-    {
-        {"qmu_olif_rd_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_qmu_olif_rd_vld_cnt_reg[] = 
-    {
-        {"qmu_olif_rd_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_qmu_olif_rd_blk_cnt_reg[] = 
-    {
-        {"qmu_olif_rd_blk_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_mmu_tm_data_sop_cnt_reg[] = 
-    {
-        {"mmu_tm_data_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_mmu_tm_data_eop_cnt_reg[] = 
-    {
-        {"mmu_tm_data_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_mmu_tm_data_vld_cnt_reg[] = 
-    {
-        {"mmu_tm_data_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_odma_tm_data_sop_cnt_reg[] = 
-    {
-        {"odma_tm_data_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_odma_tm_data_eop_cnt_reg[] = 
-    {
-        {"odma_tm_data_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_odma_tm_deq_vld_cnt_reg[] = 
-    {
-        {"odma_tm_deq_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_olif_qmu_release_vld_cnt_reg[] = 
-    {
-        {"olif_qmu_release_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_emem_dat_vld_cnt_reg[] = 
-    {
-        {"emem_dat_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_imem_dat_vld_cnt_reg[] = 
-    {
-        {"imem_dat_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_emem_dat_rd_cnt_reg[] = 
-    {
-        {"emem_dat_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_imem_dat_rd_cnt_reg[] = 
-    {
-        {"imem_dat_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_qmu_olif_rd_sop_emem_cnt_reg[] = 
-    {
-        {"qmu_olif_rd_sop_emem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_qmu_olif_rd_vld_emem_cnt_reg[] = 
-    {
-        {"qmu_olif_rd_vld_emem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_cpu_last_wr_addr_reg[] = 
-    {
-        {"cpu_last_wr_addr", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_cpu_last_wr_data_reg[] = 
-    {
-        {"cpu_last_wr_data", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_cpu_last_rd_addr_reg[] = 
-    {
-        {"cpu_last_rd_addr", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_qmu_olif_last_port_reg[] = 
-    {
-        {"qmu_olif_last_port", DPP_FIELD_FLAG_RO, 6, 7, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_qmu_olif_last_addr_reg[] = 
-    {
-        {"qmu_olif_last_addr", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_qmu_olif_last_bank_reg[] = 
-    {
-        {"qmu_olif_last_bank", DPP_FIELD_FLAG_RO, 6, 7, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_tm_lif_byte_stat_reg[] = 
-    {
-        {"tm_lif_byte_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_olif_tm_lif_err_stat_reg[] = 
-    {
-        {"tm_lif_err_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_port_share_cnt_reg[] = 
-    {
-        {"port_share_cnt", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_total_imem_cnt_reg[] = 
-    {
-        {"total_imem_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_pp_q_len_reg[] = 
-    {
-        {"pp_q_len", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_sys_q_len_reg[] = 
-    {
-        {"sys_q_len", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_cfg_error_warning_reg[] = 
-    {
-        {"error_correction_11", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0},
-        {"error_correction_10", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0},
-        {"error_correction_9", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0},
-        {"error_correction_8", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0},
-        {"error_correction_7", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"error_correction_6", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"error_correction5", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"error_correction_4", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"error_correction_3", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"error_correction_2", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"error_correction_1", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"error_correction_0", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_mult_qlen_th_en_reg[] = 
-    {
-        {"mult_qlen_th", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_mult_qlen_th_reg[] = 
-    {
-        {"mult_qlen_th", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_cfg_move_reg[] = 
-    {
-        {"cfgmt_sys_move_en", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0},
-        {"cfgmt_port_move_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"cfgmt_flow_move_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cfgmt_total_th_reg[] = 
-    {
-        {"cfgmt_total_th", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cfgmt_port_share_th_reg[] = 
-    {
-        {"cfgmt_port_share_th", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_sa_unreach_state_reg[] = 
-    {
-        {"sa_unreach_state", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_mv_port_th_reg[] = 
-    {
-        {"port_th", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_mv_drop_sp_th_reg[] = 
-    {
-        {"mvdrop_sp_th", DPP_FIELD_FLAG_RW, 8, 9, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_state_warning_reg[] = 
-    {
-        {"deq_q_num_warning", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"deq_pkt_len_warning", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"enq_pkt_dp_warning", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"unenq_q_num_warning", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"enq_q_num_warning", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"enq_pkt_len_warning", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_reg[] = 
-    {
-        {"tmmu_cgavd_dma_fifo_cnt", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_max_reg[] = 
-    {
-        {"tmmu_cgavd_dma_fifo_cnt_max", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_imem_total_cnt_reg[] = 
-    {
-        {"imem_total_cnt", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_imem_total_cnt_max_reg[] = 
-    {
-        {"imem_total_cnt_max", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow0_omem_cnt_reg[] = 
-    {
-        {"flow0_omem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow1_omem_cnt_reg[] = 
-    {
-        {"flow1_omem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow2_omem_cnt_reg[] = 
-    {
-        {"flow2_omem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow3_omem_cnt_reg[] = 
-    {
-        {"flow3_omem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_flow4_omem_cnt_reg[] = 
-    {
-        {"flow4_omem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_appoint_flow_num_message_1_reg[] = 
-    {
-        {"appoint_flow_num_en_1", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0},
-        {"appoint_flow_num_1", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_appoint_flow_num_message_2_reg[] = 
-    {
-        {"appoint_flow_num_en_2", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"appoint_flow_num_2", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_odma_cgavd_pkt_num_1_reg[] = 
-    {
-        {"odma_cgavd_pkt_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_odma_cgavd_byte_num_1_reg[] = 
-    {
-        {"odma_cgavd_byte_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_enqueue_pkt_num_1_reg[] = 
-    {
-        {"cgavd_enqueue_pkt_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_dequeue_pkt_num_1_reg[] = 
-    {
-        {"cgavd_dequeue_pkt_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_imem_num_1_reg[] = 
-    {
-        {"cgavd_qmu_pkt_imem_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_omem_num_1_reg[] = 
-    {
-        {"cgavd_qmu_pkt_omem_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_imem_num_1_reg[] = 
-    {
-        {"cgavd_qmu_byte_imem_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_omem_num_1_reg[] = 
-    {
-        {"cgavd_qmu_byte_omem_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_drop_num_1_reg[] = 
-    {
-        {"cgavd_qmu_pkt_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_drop_num_1_reg[] = 
-    {
-        {"cgavd_qmu_byte_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_forbid_drop_num_1_reg[] = 
-    {
-        {"cgavd_qmu_forbid_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_td_drop_num_1_reg[] = 
-    {
-        {"cgavd_qmu_flow_td_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_wred_drop_num_1_reg[] = 
-    {
-        {"cgavd_qmu_flow_wred_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_1_reg[] = 
-    {
-        {"cgavd_qmu_flow_wred_dp_drop_num1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_td_num_1_reg[] = 
-    {
-        {"cgavd_qmu_pp_td_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_wred_drop_num_1_reg[] = 
-    {
-        {"cgavd_qmu_pp_wred_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_1_reg[] = 
-    {
-        {"cgavd_qmu_pp_wred_dp_drop_num1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_td_drop_num_1_reg[] = 
-    {
-        {"cgavd_qmu_sys_td_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_gred_drop_num_1_reg[] = 
-    {
-        {"cgavd_qmu_sys_gred_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num1_reg[] = 
-    {
-        {"cgavd_qmu_sys_gred_dp_drop_num1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sa_drop_num_1_reg[] = 
-    {
-        {"cgavd_qmu_sa_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_move_drop_num_1_reg[] = 
-    {
-        {"cgavd_qmu_move_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_tm_mult_drop_num_1_reg[] = 
-    {
-        {"cgavd_qmu_tm_mult_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_tm_error_drop_num_1_reg[] = 
-    {
-        {"cgavd_qmu_tm_error_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_odma_cgavd_pkt_num_2_reg[] = 
-    {
-        {"odma_cgavd_pkt_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_odma_cgavd_byte_num_2_reg[] = 
-    {
-        {"odma_cgavd_byte_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_enqueue_pkt_num_2_reg[] = 
-    {
-        {"cgavd_enqueue_pkt_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_dequeue_pkt_num_2_reg[] = 
-    {
-        {"cgavd_dequeue_pkt_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_imem_num_2_reg[] = 
-    {
-        {"cgavd_qmu_pkt_imem_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_omem_num_2_reg[] = 
-    {
-        {"cgavd_qmu_pkt_omem_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_imem_num_2_reg[] = 
-    {
-        {"cgavd_qmu_byte_imem_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_omem_num_2_reg[] = 
-    {
-        {"cgavd_qmu_byte_omem_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_drop_num_2_reg[] = 
-    {
-        {"cgavd_qmu_pkt_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_drop_num_2_reg[] = 
-    {
-        {"cgavd_qmu_byte_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_forbid_drop_num_2_reg[] = 
-    {
-        {"cgavd_qmu_forbid_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_td_drop_num_2_reg[] = 
-    {
-        {"cgavd_qmu_flow_td_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_wred_drop_num_2_reg[] = 
-    {
-        {"cgavd_qmu_flow_wred_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_2_reg[] = 
-    {
-        {"cgavd_qmu_flow_wred_dp_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_td_num_2_reg[] = 
-    {
-        {"cgavd_qmu_pp_td_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_wred_drop_num_2_reg[] = 
-    {
-        {"cgavd_qmu_pp_wred_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_2_reg[] = 
-    {
-        {"cgavd_qmu_pp_wred_dp_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_td_drop_num_2_reg[] = 
-    {
-        {"cgavd_qmu_sys_td_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_gred_drop_num_2_reg[] = 
-    {
-        {"cgavd_qmu_sys_gred_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num_2_reg[] = 
-    {
-        {"cgavd_qmu_sys_gred_dp_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sa_drop_num_2_reg[] = 
-    {
-        {"cgavd_qmu_sa_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_move_drop_num_2_reg[] = 
-    {
-        {"cgavd_qmu_move_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_tm_mult_drop_num_2_reg[] = 
-    {
-        {"cgavd_qmu_tm_mult_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_cgavd_qmu_tm_error_drop_num_2_reg[] = 
-    {
-        {"cgavd_qmu_tm_error_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_move_flow_th_profile_reg[] = 
-    {
-        {"move_drop_profile", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_cgavd_move_flow_th_reg[] = 
-    {
-        {"move_drop_flow_th", DPP_FIELD_FLAG_RW, 28, 29, 0x50, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_emem_pd_fifo_aful_th_reg[] = 
-    {
-        {"emem_pd_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_dma_data_fifo_aful_th_reg[] = 
-    {
-        {"dma_data_fifo_aful_th", DPP_FIELD_FLAG_RW, 9, 10, 0x190, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_states_0_reg[] = 
-    {
-        {"tm_odma_pkt_rdy", DPP_FIELD_FLAG_RO, 30, 1, 0x1, 0x0},
-        {"dma_data_fifo_empty", DPP_FIELD_FLAG_RO, 29, 1, 0x1, 0x0},
-        {"imem_enq_rd_fifo_empty", DPP_FIELD_FLAG_RO, 28, 1, 0x1, 0x0},
-        {"imem_enq_drop_fifo_empty", DPP_FIELD_FLAG_RO, 27, 1, 0x1, 0x0},
-        {"imem_deq_rd_fifo_empty", DPP_FIELD_FLAG_RO, 26, 1, 0x1, 0x0},
-        {"imem_deq_drop_fifo_empty", DPP_FIELD_FLAG_RO, 25, 1, 0x1, 0x0},
-        {"wr_cmd_fifo_empty", DPP_FIELD_FLAG_RO, 24, 1, 0x1, 0x0},
-        {"cached_pd_fifo_empty", DPP_FIELD_FLAG_RO, 23, 1, 0x1, 0x0},
-        {"emem_pd_fifo_empty", DPP_FIELD_FLAG_RO, 22, 1, 0x1, 0x0},
-        {"pd_order_fifo_empty", DPP_FIELD_FLAG_RO, 21, 1, 0x1, 0x0},
-        {"odma_tm_data_rdy", DPP_FIELD_FLAG_RO, 20, 1, 0x1, 0x0},
-        {"odma_tm_discard_rdy", DPP_FIELD_FLAG_RO, 19, 1, 0x1, 0x0},
-        {"olif_tmmu_rdy", DPP_FIELD_FLAG_RO, 18, 1, 0x1, 0x0},
-        {"mmu_tm_cmd_wr_rdy", DPP_FIELD_FLAG_RO, 17, 1, 0x1, 0x0},
-        {"mmu_tm_data_wr_rdy", DPP_FIELD_FLAG_RO, 16, 1, 0x1, 0x0},
-        {"mmu_tm_rd_rdy", DPP_FIELD_FLAG_RO, 15, 1, 0x1, 0x0},
-        {"mmu_tm_sop_rd_rdy", DPP_FIELD_FLAG_RO, 14, 1, 0x1, 0x0},
-        {"qmu_tmmu_sop_data_rdy", DPP_FIELD_FLAG_RO, 13, 1, 0x1, 0x0},
-        {"tmmu_cmdsw_imem_release_rdy", DPP_FIELD_FLAG_RO, 12, 1, 0x1, 0x0},
-        {"imem_age_release_rdy", DPP_FIELD_FLAG_RO, 11, 1, 0x1, 0x0},
-        {"tmmu_qmu_wr_rdy", DPP_FIELD_FLAG_RO, 10, 1, 0x1, 0x0},
-        {"tmmu_qmu_rdy_7", DPP_FIELD_FLAG_RO, 9, 1, 0x1, 0x0},
-        {"tmmu_qmu_rdy_6", DPP_FIELD_FLAG_RO, 8, 1, 0x1, 0x0},
-        {"tmmu_qmu_rdy_5", DPP_FIELD_FLAG_RO, 7, 1, 0x1, 0x0},
-        {"tmmu_qmu_rdy_4", DPP_FIELD_FLAG_RO, 6, 1, 0x1, 0x0},
-        {"tmmu_qmu_rdy_3", DPP_FIELD_FLAG_RO, 5, 1, 0x1, 0x0},
-        {"tmmu_qmu_rdy_2", DPP_FIELD_FLAG_RO, 4, 1, 0x1, 0x0},
-        {"tmmu_qmu_rdy_1", DPP_FIELD_FLAG_RO, 3, 1, 0x1, 0x0},
-        {"tmmu_qmu_rdy_0", DPP_FIELD_FLAG_RO, 2, 1, 0x1, 0x0},
-        {"tmmu_qmu_rd_rdy", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0},
-        {"tmmu_qmu_sop_rd_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_qmu_tmmu_wr_sop_cnt_reg[] = 
-    {
-        {"qmu_tmmu_wr_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_qmu_tmmu_wr_eop_cnt_reg[] = 
-    {
-        {"qmu_tmmu_wr_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_qmu_tmmu_wr_drop_cnt_reg[] = 
-    {
-        {"qmu_tmmu_wr_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_qmu_tmmu_wr_emem_cnt_reg[] = 
-    {
-        {"qmu_tmmu_wr_emem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_qmu_tmmu_wr_imem_cnt_reg[] = 
-    {
-        {"qmu_tmmu_wr_imem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_mmu_wr_sop_cnt_reg[] = 
-    {
-        {"tmmu_mmu_wr_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_mmu_wr_eop_cnt_reg[] = 
-    {
-        {"tmmu_mmu_wr_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_qmu_tmmu_rd_sop_cnt_reg[] = 
-    {
-        {"qmu_tmmu_rd_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_qmu_tmmu_rd_eop_cnt_reg[] = 
-    {
-        {"qmu_tmmu_rd_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_qmu_tmmu_rd_drop_cnt_reg[] = 
-    {
-        {"qmu_tmmu_rd_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_qmu_tmmu_rd_emem_cnt_reg[] = 
-    {
-        {"qmu_tmmu_rd_emem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_qmu_tmmu_rd_imem_cnt_reg[] = 
-    {
-        {"qmu_tmmu_rd_imem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_mmu_rd_sop_cnt_reg[] = 
-    {
-        {"tmmu_mmu_rd_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_mmu_rd_eop_cnt_reg[] = 
-    {
-        {"tmmu_mmu_rd_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_odma_in_sop_cnt_reg[] = 
-    {
-        {"tmmu_odma_in_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_odma_in_eop_cnt_reg[] = 
-    {
-        {"tmmu_odma_in_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_odma_vld_cnt_reg[] = 
-    {
-        {"tmmu_odma_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_qmu_pd_in_cnt_reg[] = 
-    {
-        {"qmu_pd_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_pd_hit_cnt_reg[] = 
-    {
-        {"tmmu_pd_hit_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_pd_out_cnt_reg[] = 
-    {
-        {"tmmu_pd_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_wr_cmd_fifo_wr_cnt_reg[] = 
-    {
-        {"tmmu_wr_cmd_fifo_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_imem_age_cnt_reg[] = 
-    {
-        {"tmmu_imem_age_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_cmdsch_rd_cnt_reg[] = 
-    {
-        {"tmmu_cmdsch_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_cmdsch_drop_cnt_reg[] = 
-    {
-        {"tmmu_cmdsch_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_cmdsw_drop_cnt_reg[] = 
-    {
-        {"tmmu_cmdsw_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_odma_enq_rd_cnt_reg[] = 
-    {
-        {"tmmu_odma_enq_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_odma_enq_drop_cnt_reg[] = 
-    {
-        {"tmmu_odma_enq_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_odma_imem_age_cnt_reg[] = 
-    {
-        {"tmmu_odma_imem_age_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_odma_deq_rd_cnt_reg[] = 
-    {
-        {"tmmu_odma_deq_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tmmu_odma_deq_drop_cnt_reg[] = 
-    {
-        {"tmmu_odma_deq_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_olif_tmmu_xoff_cnt_reg[] = 
-    {
-        {"olif_tmmu_xoff_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_odma_tm_data_xoff_cnt_reg[] = 
-    {
-        {"odma_tm_data_xoff_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tm_odma_pkt_xoff_cnt_reg[] = 
-    {
-        {"tm_odma_pkt_xoff_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_tm_state_3_reg[] = 
-    {
-        {"tmmu_qmu_rdy_9", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0},
-        {"tmmu_qmu_rdy_8", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_cmd_reg[] = 
-    {
-        {"cfgmt_pd_cache_addr", DPP_FIELD_FLAG_RW, 12, 13, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_rd_done_reg[] = 
-    {
-        {"cfgmt_pd_cache_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_rd_data_0_reg[] = 
-    {
-        {"cfgmt_pd_cache_rd_data_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_rd_data_1_reg[] = 
-    {
-        {"cfgmt_pd_cache_rd_data_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_rd_data_2_reg[] = 
-    {
-        {"cfgmt_pd_cache_rd_data_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_rd_data_3_reg[] = 
-    {
-        {"cfgmt_pd_cache_rd_data_3", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_tmmu_to_odma_para_reg[] = 
-    {
-        {"cfgmt_tmmu_to_odma_para", DPP_FIELD_FLAG_RO, 25, 26, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_dma_data_fifo_cnt_reg[] = 
-    {
-        {"cfgmt_dma_data_fifo_cnt", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit0_offset_reg[] = 
-    {
-        {"cfgmt_cache_tag_bit0_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xd, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit1_offset_reg[] = 
-    {
-        {"cfgmt_cache_tag_bit1_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xe, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit2_offset_reg[] = 
-    {
-        {"cfgmt_cache_tag_bit2_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xf, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit3_offset_reg[] = 
-    {
-        {"cfgmt_cache_tag_bit3_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit4_offset_reg[] = 
-    {
-        {"cfgmt_cache_tag_bit4_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x11, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit5_offset_reg[] = 
-    {
-        {"cfgmt_cache_tag_bit5_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x12, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit0_offset_reg[] = 
-    {
-        {"cfgmt_cache_index_bit0_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit1_offset_reg[] = 
-    {
-        {"cfgmt_cache_index_bit1_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit2_offset_reg[] = 
-    {
-        {"cfgmt_cache_index_bit2_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x2, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit3_offset_reg[] = 
-    {
-        {"cfgmt_cache_index_bit3_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x3, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit4_offset_reg[] = 
-    {
-        {"cfgmt_cache_index_bit4_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit5_offset_reg[] = 
-    {
-        {"cfgmt_cache_index_bit5_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x5, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit6_offset_reg[] = 
-    {
-        {"cfgmt_cache_index_bit6_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x6, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit7_offset_reg[] = 
-    {
-        {"cfgmt_cache_index_bit7_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x7, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit8_offset_reg[] = 
-    {
-        {"cfgmt_cache_index_bit8_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x8, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit9_offset_reg[] = 
-    {
-        {"cfgmt_cache_index_bit9_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x9, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit10_offset_reg[] = 
-    {
-        {"cfgmt_cache_index_bit10_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit11_offset_reg[] = 
-    {
-        {"cfgmt_cache_index_bit11_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xb, 0x0},
-    };
-DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit12_offset_reg[] = 
-    {
-        {"cfgmt_cache_index_bit12_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_bktfull_fifo_full_flagregister_reg[] = 
-    {
-        {"bktfull_fifo_full_flag_core", DPP_FIELD_FLAG_RC, 21, 22, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_fifo_full_regregister_reg[] = 
-    {
-        {"fifo_full_reg", DPP_FIELD_FLAG_RO, 21, 22, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_fifo_empty_regregister_reg[] = 
-    {
-        {"fifo_empty_reg", DPP_FIELD_FLAG_RO, 21, 22, 0x7, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_fifo_almost_full_regregister_reg[] = 
-    {
-        {"fifo_almost_full_reg", DPP_FIELD_FLAG_RO, 21, 22, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_shap_fifo_almost_empty_regregister_reg[] = 
-    {
-        {"fifo_almost_empty_reg", DPP_FIELD_FLAG_RO, 21, 22, 0x7, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_credit_space_select_reg[] = 
-    {
-        {"credit_space_select", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_space_max_reg[] = 
-    {
-        {"stat_space_max", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_space_min_reg[] = 
-    {
-        {"stat_space_min", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_space_credit_reg[] = 
-    {
-        {"stat_space_credit", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_stat_que_step8_credit_reg[] = 
-    {
-        {"stat_que_step8_credit", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_special_que_reg[] = 
-    {
-        {"special_que_id", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_special_que_credit_reg[] = 
-    {
-        {"special_que_credit", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_lif_congest_credit_cnt_reg[] = 
-    {
-        {"lif_congest_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_lif_port_congest_credit_cnt_reg[] = 
-    {
-        {"lif_port_congest_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_congest_credit_cnt_reg[] = 
-    {
-        {"crdt_congest_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_port_congest_credit_cnt_reg[] = 
-    {
-        {"crdt_port_congest_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_congest_port_id_reg[] = 
-    {
-        {"congest_port_id", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_dev_link_control_reg[] = 
-    {
-        {"dev_link_control", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_sa_port_rdy_reg[] = 
-    {
-        {"crdt_sa_port_rdy", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_congest_mode_select_reg[] = 
-    {
-        {"crdt_congest_mode_selectr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_fifo_out_all_crs_normal_cnt_reg[] = 
-    {
-        {"fifo_out_all_crs_normal_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_fifo_out_all_crs_off_cnt_reg[] = 
-    {
-        {"fifo_out_all_crs_off_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_fifo_out_que_crs_normal_cnt_reg[] = 
-    {
-        {"fifo_out_que_crs_normal_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_fifo_out_que_crs_off_cnt_reg[] = 
-    {
-        {"fifo_out_que_crs_off_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_mode_add_60g_reg[] = 
-    {
-        {"mode_add_60g", DPP_FIELD_FLAG_RW, 15, 16, 0xff, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_pp_token_add_reg[] = 
-    {
-        {"pp_token_add_cir", DPP_FIELD_FLAG_RO, 4, 5, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_pp_cir_token_total_dist_cnt_reg[] = 
-    {
-        {"pp_cir_token_total_dist_counter", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_pp_cir_token_total_dec_cnt_reg[] = 
-    {
-        {"pp_cir_token_total_dec_counter", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_dev_credit_cnt_reg[] = 
-    {
-        {"dev_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_no_credit_cnt1_reg[] = 
-    {
-        {"no_credit_cnt1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_no_credit_cnt2_reg[] = 
-    {
-        {"no_credit_cnt2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_asm_interval_0_cfg_reg[] = 
-    {
-        {"asm_interval_0_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0xf, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_asm_interval_1_cfg_reg[] = 
-    {
-        {"asm_interval_1_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x1f, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_asm_interval_2_cfg_reg[] = 
-    {
-        {"asm_interval_2_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x2f, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_asm_interval_3_cfg_reg[] = 
-    {
-        {"asm_interval_3_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x3f, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_asm_interval_4_cfg_reg[] = 
-    {
-        {"asm_interval_4_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x4f, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_asm_interval_5cfg_reg[] = 
-    {
-        {"asm_interval_5_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x5f, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_asm_interval_6_cfg_reg[] = 
-    {
-        {"asm_interval_6_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x6f, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_asm_interval_7_cfg_reg[] = 
-    {
-        {"asm_interval_7_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x7f, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_total_congest_mode_cfg_reg[] = 
-    {
-        {"crdt_total_congest_mode_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_rci_fifo_ini_deep_cfg_reg[] = 
-    {
-        {"rci_fifo_ini_deep_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0x1f4, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_ecc_reg[] = 
-    {
-        {"seinfo_wfq_single_ecc_err", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"seinfo_wfq_double_ecc_err", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"seinfo_fq_single_ecc_err", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"seinfo_fq_double_ecc_err", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"ecc_bypass", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_ucn_asm_rdy_shield_en_reg[] = 
-    {
-        {"ucn_rdy_shield_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"asm_rdy_shield_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_ucn_asm_rdy_reg[] = 
-    {
-        {"ucn_rdy", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0},
-        {"asm_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_rci_grade_reg[] = 
-    {
-        {"rci_grade", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_rci_value_r_reg[] = 
-    {
-        {"crdt_rci_value_r", DPP_FIELD_FLAG_RO, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crdt_interval_now_reg[] = 
-    {
-        {"crdt_interval_now", DPP_FIELD_FLAG_RO, 21, 22, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crs_sheild_flow_id_cfg_reg[] = 
-    {
-        {"crs_sheild_flow_id_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crs_sheild_en_cfg_reg[] = 
-    {
-        {"crs_sheild_en_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_crs_sheild_value_cfg_reg[] = 
-    {
-        {"crs_sheild_value_cfg", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_test_token_calc_ctrl_reg[] = 
-    {
-        {"test_token_calc_state", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"test_token_calc_trigger", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_test_token_sample_cycle_num_reg[] = 
-    {
-        {"sample_cycle_num", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_q_state_0_7_reg[] = 
-    {
-        {"q_token_state_7", DPP_FIELD_FLAG_RO, 29, 2, 0x0, 0x0},
-        {"q_token_state_6", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0},
-        {"q_token_state_5", DPP_FIELD_FLAG_RO, 21, 2, 0x0, 0x0},
-        {"q_token_state_4", DPP_FIELD_FLAG_RO, 17, 2, 0x0, 0x0},
-        {"q_token_state_3", DPP_FIELD_FLAG_RO, 13, 2, 0x0, 0x0},
-        {"q_token_state_2", DPP_FIELD_FLAG_RO, 9, 2, 0x0, 0x0},
-        {"q_token_state_1", DPP_FIELD_FLAG_RO, 5, 2, 0x0, 0x0},
-        {"q_token_state_0", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_crdt_q_state_8_15_reg[] = 
-    {
-        {"q_token_state_15", DPP_FIELD_FLAG_RO, 29, 2, 0x0, 0x0},
-        {"q_token_state_14", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0},
-        {"q_token_state_13", DPP_FIELD_FLAG_RO, 21, 2, 0x0, 0x0},
-        {"q_token_state_12", DPP_FIELD_FLAG_RO, 17, 2, 0x0, 0x0},
-        {"q_token_state_11", DPP_FIELD_FLAG_RO, 13, 2, 0x0, 0x0},
-        {"q_token_state_10", DPP_FIELD_FLAG_RO, 9, 2, 0x0, 0x0},
-        {"q_token_state_9", DPP_FIELD_FLAG_RO, 5, 2, 0x0, 0x0},
-        {"q_token_state_8", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csw_csch_rd_cmd_cnt_reg[] = 
-    {
-        {"csw_csch_rd_cmd_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csw_csch_rd_sop_cnt_reg[] = 
-    {
-        {"csw_csch_rd_sop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csw_csch_rd_eop_cnt_reg[] = 
-    {
-        {"csw_csch_rd_eop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csw_csch_rd_drop_cnt_reg[] = 
-    {
-        {"csw_csch_rd_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csch_mmu_rd_cmd_cnt_reg[] = 
-    {
-        {"csch_mmu_rd_cmd_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csch_mmu_rd_sop_cnt_reg[] = 
-    {
-        {"csch_mmu_rd_sop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csch_mmu_rd_eop_cnt_reg[] = 
-    {
-        {"csch_mmu_rd_eop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csch_mmu_rd_drop_cnt_reg[] = 
-    {
-        {"csch_mmu_rd_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_filter_reg[] = 
-    {
-        {"qcfg_qsch_crs_filter", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_force_en_reg[] = 
-    {
-        {"qcfg_qsch_crs_force_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_force_qnum_reg[] = 
-    {
-        {"qcfg_qsch_crs_force_qnum", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_force_crs_reg[] = 
-    {
-        {"qcfg_qsch_crs_force_crs", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_oshp_sgmii_shap_mode_reg[] = 
-    {
-        {"cfgmt_oshp_sgmii_shap_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_sashap_en_reg[] = 
-    {
-        {"cfgmt_qmu_sashap_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_sashap_token_max_reg[] = 
-    {
-        {"cfgmt_sashap_token_max", DPP_FIELD_FLAG_RW, 31, 32, 0x2000, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_sashap_token_min_reg[] = 
-    {
-        {"cfgmt_sashap_token_min", DPP_FIELD_FLAG_RW, 31, 32, 0xffffe000, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_q3lbaddrate_reg[] = 
-    {
-        {"cfg_qsch_q3lbaddrate", DPP_FIELD_FLAG_RW, 27, 28, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_q012lbaddrate_reg[] = 
-    {
-        {"cfg_qsch_q012lbaddrate", DPP_FIELD_FLAG_RW, 27, 28, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_q3creditlbmaxcnt_reg[] = 
-    {
-        {"cfg_qsch_q3creditlbmaxcnt", DPP_FIELD_FLAG_RW, 7, 8, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_q012creditlbmaxcnt_reg[] = 
-    {
-        {"cfg_qsch_q012creditlbmaxcnt", DPP_FIELD_FLAG_RW, 7, 8, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mul_token_gen_num_reg[] = 
-    {
-        {"cfg_qsch_mul_token_gen_num", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_q3_credit_lb_control_en_reg[] = 
-    {
-        {"cfg_qsch_q3_credit_lb_control_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_q012_credit_lb_control_en_reg[] = 
-    {
-        {"cfg_qsch_q012_credit_lb_control_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_sp_dwrr_en_reg[] = 
-    {
-        {"cfg_qsch_sp_dwrr_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_q01_attach_en_reg[] = 
-    {
-        {"cfg_qsch_q01_attach_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_w0_reg[] = 
-    {
-        {"cfg_qsch_w0", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_w1_reg[] = 
-    {
-        {"cfg_qsch_w1", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_w2_reg[] = 
-    {
-        {"cfg_qsch_w2", DPP_FIELD_FLAG_RW, 6, 7, 0x40, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktmaxcnt1_reg[] = 
-    {
-        {"cfg_qsch_lkybktmaxcnt1", DPP_FIELD_FLAG_RW, 31, 32, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktmaxcnt2_reg[] = 
-    {
-        {"cfg_qsch_lkybktmaxcnt2", DPP_FIELD_FLAG_RW, 31, 32, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktdcrrate1_reg[] = 
-    {
-        {"cfg_qsch_lkybktdcrrate1", DPP_FIELD_FLAG_RW, 31, 32, 0x80000020, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktdcrrate2_reg[] = 
-    {
-        {"cfg_qsch_lkybktdcrrate2", DPP_FIELD_FLAG_RW, 31, 32, 0x80000010, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktdcrrate3_reg[] = 
-    {
-        {"cfg_qsch_lkybktdcrrate3", DPP_FIELD_FLAG_RW, 31, 32, 0x80000004, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktmaxcnt3_reg[] = 
-    {
-        {"cfg_qsch_lkybktmaxcnt3", DPP_FIELD_FLAG_RW, 31, 32, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_qmu_mul_auto_sa_version_reg[] = 
-    {
-        {"cfg_qsch_qmu_mul_auto_sa_version", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_0_reg[] = 
-    {
-        {"cfg_qsch_sa_credit_value_0", DPP_FIELD_FLAG_RW, 13, 14, 0x85, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_1_reg[] = 
-    {
-        {"cfg_qsch_sa_credit_value_1", DPP_FIELD_FLAG_RW, 13, 14, 0x29a, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_2_reg[] = 
-    {
-        {"cfg_qsch_sa_credit_value_2", DPP_FIELD_FLAG_RW, 13, 14, 0x190, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_3_reg[] = 
-    {
-        {"cfg_qsch_sa_credit_value_3", DPP_FIELD_FLAG_RW, 13, 14, 0x4e2, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_4_reg[] = 
-    {
-        {"cfg_qsch_sa_credit_value_4", DPP_FIELD_FLAG_RW, 13, 14, 0x5fe, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_5_reg[] = 
-    {
-        {"cfg_qsch_sa_credit_value_5", DPP_FIELD_FLAG_RW, 13, 14, 0x8a0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_6_reg[] = 
-    {
-        {"cfg_qsch_sa_credit_value_6", DPP_FIELD_FLAG_RW, 13, 14, 0x8a0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_7_reg[] = 
-    {
-        {"cfg_qsch_sa_credit_value_7", DPP_FIELD_FLAG_RW, 13, 14, 0x8a0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_remote_credit_fifo_almost_full_th_reg[] = 
-    {
-        {"cfg_qsch_remote_credit_fifo_almost_full_th", DPP_FIELD_FLAG_RW, 10, 11, 0x7ff, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_auto_credit_fifo_almost_full_th_reg[] = 
-    {
-        {"cfg_qsch_auto_credit_fifo_almost_full_th", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_q3_credit_fifo_almost_full_th_reg[] = 
-    {
-        {"cfg_qsch_q3_credit_fifo_almost_full_th", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_q012_credit_fifo_almost_full_th_reg[] = 
-    {
-        {"cfg_qsch_q012_credit_fifo_almost_full_th", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mul_fc_res_en_reg[] = 
-    {
-        {"cfg_qsch_mul_fc_res_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_mul_ovf_udf_flg_query_reg[] = 
-    {
-        {"qsch_cfg_remote_credit_fifo_full", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0},
-        {"qsch_cfg_remote_credit_fifo_empty", DPP_FIELD_FLAG_RO, 17, 1, 0x1, 0x0},
-        {"qsch_cfg_remote_credit_fifo_overflow", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0},
-        {"qsch_cfg_remote_credit_fifo_underflow", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0},
-        {"qsch_cfg_auto_credit_fifo_full", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0},
-        {"qsch_cfg_auto_credit_fifo_empty", DPP_FIELD_FLAG_RO, 13, 1, 0x1, 0x0},
-        {"qsch_cfg_auto_credit_fifo_overflow", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0},
-        {"qsch_cfg_auto_credit_fifo_underflow", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0},
-        {"qsch_cfg_q3_credit_fifo_full", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0},
-        {"qsch_cfg_q3_credit_fifo_empty", DPP_FIELD_FLAG_RO, 9, 1, 0x1, 0x0},
-        {"qsch_cfg_q3_credit_fifo_overflow", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0},
-        {"qsch_cfg_q3_credit_fifo_underflow", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"qsch_cfg_q012_credit_fifo_full", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"qsch_cfg_q012_credit_fifo_empty", DPP_FIELD_FLAG_RO, 5, 1, 0x1, 0x0},
-        {"qsch_cfg_q012_credit_fifo_overflow", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"qsch_cfg_q012_credit_fifo_underflow", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"qsch_cfg_lkybktoverflow1", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"qsch_cfg_lkybktoverflow2", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"qsch_cfg_lkybktoverflow3", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_mul_cng_flg_query_reg[] = 
-    {
-        {"qsch_cfg_q3cngflag", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"qsch_cfg_q012cngflag", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"qsch_cfg_cngflag1", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"qsch_cfg_cngflag2", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"qsch_cfg_cngflag3", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qsch_cfg_lkybktval1_reg[] = 
-    {
-        {"qsch_cfg_lkybktval1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qsch_cfg_lkybktval2_reg[] = 
-    {
-        {"qsch_cfg_lkybktval2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qsch_cfg_lkybktval3_reg[] = 
-    {
-        {"qsch_cfg_lkybktval3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qsch_cfg_q3lbval_reg[] = 
-    {
-        {"qsch_cfg_q3lbval", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qsch_cfg_q012lbval_reg[] = 
-    {
-        {"qsch_cfg_q012lbval", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qlist_cfgmt_ram_ecc_err2_reg[] = 
-    {
-        {"qlist_imem_pd_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"qlist_imem_pd_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"qlist_imem_up_ptr_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"qlist_imem_up_ptr_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"qlist_imem_down_ptr_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"qlist_imem_down_ptr_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"cmdsw_sop_fifo_single_ecc_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"cmdsw_sop_fifo_double_ecc_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"cmdsw_nsop_fifo_single_ecc_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"cmdsw_nsop_fifo_double_ecc_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"cmdsw_mmudat_fifo_single_ecc_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"cmdsw_mmudat_fifo_double_ecc_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"qlist_rd_release_fwft_single_ecc_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"qlist_rd_release_fwft_double_ecc_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"qlist_drop_imem_fwft_single_ecc_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"qlist_drop_imem_fwft_double_ecc_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csch_aged_cmd_cnt_reg[] = 
-    {
-        {"csch_aged_cmd_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csch_qcfg_csch_congest_cnt_reg[] = 
-    {
-        {"csch_qcfg_csch_congest_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csch_qcfg_qlist_csch_sop_cnt_reg[] = 
-    {
-        {"csch_qcfg_qlist_csch_sop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csch_qcfg_qlist_csch_eop_cnt_reg[] = 
-    {
-        {"csch_qcfg_qlist_csch_eop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csch_qcfg_csch_csw_sop_cnt_reg[] = 
-    {
-        {"csch_qcfg_csch_csw_sop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csch_qcfg_csch_csw_eop_cnt_reg[] = 
-    {
-        {"csch_qcfg_csch_csw_eop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csch_qcfg_qlist_csch_drop_cnt_reg[] = 
-    {
-        {"csch_qcfg_qlist_csch_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csch_qcfg_csch_csw_drop_cnt_reg[] = 
-    {
-        {"csch_qcfg_csch_csw_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csw_mmu_sop_cmd_cnt_reg[] = 
-    {
-        {"csw_mmu_sop_cmd_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_mmu_csw_sop_data_cnt_reg[] = 
-    {
-        {"mmu_csw_sop_data_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csw_qsch_feedb_cnt_reg[] = 
-    {
-        {"csw_qsch_feedb_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_crdt_port_fc_cnt_reg[] = 
-    {
-        {"qmu_crdt_port_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_csch_r_block_cnt_reg[] = 
-    {
-        {"csch_r_block_cnt", DPP_FIELD_FLAG_RO, 16, 17, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_qds_head_rd_reg[] = 
-    {
-        {"qcfg_qlist_qds_head_rd", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_qds_tail_rd_reg[] = 
-    {
-        {"qcfg_qlist_qds_tail_rd", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_ept_rd_reg[] = 
-    {
-        {"qcfg_qlist_ept_rd", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_age_flag_rd_reg[] = 
-    {
-        {"qcfg_qlist_age_flag_rd", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_cti_rd_reg[] = 
-    {
-        {"qcfg_qlist_cti_rd", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_cto_rd_reg[] = 
-    {
-        {"qcfg_qlist_cto_rd", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_chk_rd_reg[] = 
-    {
-        {"qcfg_qlist_chk_rd", DPP_FIELD_FLAG_RO, 18, 19, 0x1, 0x1},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_nod_rd_reg[] = 
-    {
-        {"qcfg_qlist_nod_rd", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_qlist_biu_rd_reg[] = 
-    {
-        {"qcfg_qlist_biu_rd", DPP_FIELD_FLAG_RO, 4, 5, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qsch_r_wlist_flag_reg[] = 
-    {
-        {"qsch_r_wlist_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qcfg_crs_flg_rd_reg[] = 
-    {
-        {"qcfg_crs_flg_rd", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_age_qds_reg[] = 
-    {
-        {"cfgmt_qmu_imem_tp", DPP_FIELD_FLAG_RO, 30, 15, 0x0, 0x0},
-        {"cfgmt_qmu_imem_hp", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_age_qlen_reg[] = 
-    {
-        {"cfgmt_qmu_imem_no_empty", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0},
-        {"cfgmt_qmu_imem_qlen", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_pd_ram_low_reg[] = 
-    {
-        {"cfgmt_qmu_imem_pd_ram_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_pd_ram_high_reg[] = 
-    {
-        {"cfgmt_qmu_imem_pd_ram_high", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_up_ptr_reg[] = 
-    {
-        {"cfgmt_qmu_imem_up_ptr", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_down_ptr_reg[] = 
-    {
-        {"cfgmt_qmu_imem_down_ptr", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_age_flag_reg[] = 
-    {
-        {"cfgmt_qmu_imem_age_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybkt2cngth_reg[] = 
-    {
-        {"cfg_qsch_lkybkt2cngth", DPP_FIELD_FLAG_RW, 31, 32, 0x40, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybkt1cngth_reg[] = 
-    {
-        {"cfg_qsch_lkybkt1cngth", DPP_FIELD_FLAG_RW, 31, 32, 0x40, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybkt3cngth_reg[] = 
-    {
-        {"cfg_qsch_lkybkt3cngth", DPP_FIELD_FLAG_RW, 31, 32, 0x40, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn1_credit_value_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn1_credit_value", DPP_FIELD_FLAG_RW, 13, 14, 0x5fe, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn2_credit_value_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn2_credit_value", DPP_FIELD_FLAG_RW, 13, 14, 0x5fe, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn3_credit_value_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn3_credit_value", DPP_FIELD_FLAG_RW, 13, 14, 0x5fe, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_ansr_seed_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn1_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"cfg_qsch_rm_mul_mcn1_rand_ansr_seed", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_ansr_seed_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn2_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"cfg_qsch_rm_mul_mcn2_rand_ansr_seed", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_ansr_seed_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn3_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"cfg_qsch_rm_mul_mcn3_rand_ansr_seed", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_ansr_th_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn1_rand_ansr_th", DPP_FIELD_FLAG_RW, 7, 8, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_ansr_th_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn2_rand_ansr_th", DPP_FIELD_FLAG_RW, 7, 8, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_ansr_th_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn3_rand_ansr_th", DPP_FIELD_FLAG_RW, 7, 8, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_hold_base_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn1_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"cfg_qsch_rm_mul_mcn1_rand_hold_base", DPP_FIELD_FLAG_RW, 23, 24, 0x1000, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_hold_base_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn2_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"cfg_qsch_rm_mul_mcn2_rand_hold_base", DPP_FIELD_FLAG_RW, 23, 24, 0x1000, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_hold_base_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn3_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"cfg_qsch_rm_mul_mcn3_rand_hold_base", DPP_FIELD_FLAG_RW, 23, 24, 0x1000, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_sel_mask_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn1_rand_sel_mask", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_sel_mask_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn2_rand_sel_mask", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_sel_mask_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn3_rand_sel_mask", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg0_reg[] = 
-    {
-        {"rm_mul_mcn1_rand_sel_seed7", DPP_FIELD_FLAG_RW, 31, 4, 0x8, 0x0},
-        {"rm_mul_mcn1_rand_sel_seed6", DPP_FIELD_FLAG_RW, 27, 4, 0x7, 0x0},
-        {"rm_mul_mcn1_rand_sel_seed5", DPP_FIELD_FLAG_RW, 23, 4, 0x6, 0x0},
-        {"rm_mul_mcn1_rand_sel_seed4", DPP_FIELD_FLAG_RW, 19, 4, 0x5, 0x0},
-        {"rm_mul_mcn1_rand_sel_seed3", DPP_FIELD_FLAG_RW, 15, 4, 0x4, 0x0},
-        {"rm_mul_mcn1_rand_sel_seed2", DPP_FIELD_FLAG_RW, 11, 4, 0x3, 0x0},
-        {"rm_mul_mcn1_rand_sel_seed1", DPP_FIELD_FLAG_RW, 7, 4, 0x2, 0x0},
-        {"rm_mul_mcn1_rand_sel_seed0", DPP_FIELD_FLAG_RW, 3, 4, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg1_reg[] = 
-    {
-        {"rm_mul_mcn1_rand_sel_seed8", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg0_reg[] = 
-    {
-        {"rm_mul_mcn2_rand_sel_seed7", DPP_FIELD_FLAG_RW, 31, 4, 0x8, 0x0},
-        {"rm_mul_mcn2_rand_sel_seed6", DPP_FIELD_FLAG_RW, 27, 4, 0x7, 0x0},
-        {"rm_mul_mcn2_rand_sel_seed5", DPP_FIELD_FLAG_RW, 23, 4, 0x6, 0x0},
-        {"rm_mul_mcn2_rand_sel_seed4", DPP_FIELD_FLAG_RW, 19, 4, 0x5, 0x0},
-        {"rm_mul_mcn2_rand_sel_seed3", DPP_FIELD_FLAG_RW, 15, 4, 0x4, 0x0},
-        {"rm_mul_mcn2_rand_sel_seed2", DPP_FIELD_FLAG_RW, 11, 4, 0x3, 0x0},
-        {"rm_mul_mcn2_rand_sel_seed1", DPP_FIELD_FLAG_RW, 7, 4, 0x2, 0x0},
-        {"rm_mul_mcn2_rand_sel_seed0", DPP_FIELD_FLAG_RW, 3, 4, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg1_reg[] = 
-    {
-        {"rm_mul_mcn2_rand_sel_seed8", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg0_reg[] = 
-    {
-        {"rm_mul_mcn3_rand_sel_seed7", DPP_FIELD_FLAG_RW, 31, 4, 0x8, 0x0},
-        {"rm_mul_mcn3_rand_sel_seed6", DPP_FIELD_FLAG_RW, 27, 4, 0x7, 0x0},
-        {"rm_mul_mcn3_rand_sel_seed5", DPP_FIELD_FLAG_RW, 23, 4, 0x6, 0x0},
-        {"rm_mul_mcn3_rand_sel_seed4", DPP_FIELD_FLAG_RW, 19, 4, 0x5, 0x0},
-        {"rm_mul_mcn3_rand_sel_seed3", DPP_FIELD_FLAG_RW, 15, 4, 0x4, 0x0},
-        {"rm_mul_mcn3_rand_sel_seed2", DPP_FIELD_FLAG_RW, 11, 4, 0x3, 0x0},
-        {"rm_mul_mcn3_rand_sel_seed1", DPP_FIELD_FLAG_RW, 7, 4, 0x2, 0x0},
-        {"rm_mul_mcn3_rand_sel_seed0", DPP_FIELD_FLAG_RW, 3, 4, 0x1, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg1_reg[] = 
-    {
-        {"rm_mul_mcn3_rand_sel_seed8", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th1_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn1_step_wait_th1", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th2_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn1_step_wait_th2", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th3_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn1_step_wait_th3", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th4_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn1_step_wait_th4", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th5_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn1_step_wait_th5", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th6_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn1_step_wait_th6", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th7_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn1_step_wait_th7", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th1_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn2_step_wait_th1", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th2_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn2_step_wait_th2", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th3_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn2_step_wait_th3", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th4_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn2_step_wait_th4", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th5_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn2_step_wait_th5", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th6_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn2_step_wait_th6", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th7_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn2_step_wait_th7", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th1_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn3_step_wait_th1", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th2_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn3_step_wait_th2", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th3_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn3_step_wait_th3", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th4_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn3_step_wait_th4", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th5_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn3_step_wait_th5", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th6_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn3_step_wait_th6", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_rm_mul_mcn3step_wait_th7_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn3_step_wait_th7", DPP_FIELD_FLAG_RW, 15, 16, 0x80, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate0_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate0", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate1_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate1", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate2_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate2", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate3_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate3", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate4_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate4", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate5_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate5", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate6_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate6", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate7_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate7", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate8_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate8", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate9_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate9", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate10_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate10", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate11_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate11", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate12_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate12", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate13_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate13", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate14_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate14", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate15_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate15", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate16_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate16", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate17_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate17", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate18_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate18", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate19_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate19", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate20_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate20", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate21_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate21", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate22_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate22", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate23_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate23", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate24_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate24", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate25_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate25", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate26_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate26", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate27_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate27", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate28_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate28", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate29_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate29", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate30_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate30", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate31_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate31", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate32_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate32", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate33_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate33", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate34_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate34", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate35_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate35", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate36_reg[] = 
-    {
-        {"cfg_qsch_mulcrdcntrate36", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn1_rand_hold_shift_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn1_rand_hold_shift", DPP_FIELD_FLAG_RW, 2, 3, 0x7, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn2_rand_hold_shift_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn2_rand_hold_shift", DPP_FIELD_FLAG_RW, 2, 3, 0x7, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn3_rand_hold_shift_reg[] = 
-    {
-        {"cfg_qsch_rm_mul_mcn3_rand_hold_shift", DPP_FIELD_FLAG_RW, 2, 3, 0x7, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_last_drop_qnum_get_reg[] = 
-    {
-        {"cgavd_qmu_drop_tap", DPP_FIELD_FLAG_RC, 31, 4, 0x0, 0x0},
-        {"last_drop_qnum", DPP_FIELD_FLAG_RC, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_crdt_qmu_credit_cnt_reg[] = 
-    {
-        {"crdt_qmu_credit_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_to_qsch_report_cnt_reg[] = 
-    {
-        {"qmu_to_qsch_report_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_to_cgavd_report_cnt_reg[] = 
-    {
-        {"qmu_to_cgavd_report_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_crdt_crs_normal_cnt_reg[] = 
-    {
-        {"qmu_crdt_crs_normal_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_crdt_crs_off_cnt_reg[] = 
-    {
-        {"qmu_crdt_crs_off_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qsch_qlist_shedule_cnt_reg[] = 
-    {
-        {"qsch_qlist_shedule_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qsch_qlist_sch_ept_cnt_reg[] = 
-    {
-        {"qsch_qlist_sch_ept_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_to_mmu_blk_wr_cnt_reg[] = 
-    {
-        {"qmu_to_mmu_blk_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_to_csw_blk_rd_cnt_reg[] = 
-    {
-        {"qmu_to_csw_blk_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_to_mmu_sop_wr_cnt_reg[] = 
-    {
-        {"qmu_to_mmu_sop_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_to_mmu_eop_wr_cnt_reg[] = 
-    {
-        {"qmu_to_mmu_eop_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_to_mmu_drop_wr_cnt_reg[] = 
-    {
-        {"qmu_to_mmu_drop_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_to_csw_sop_rd_cnt_reg[] = 
-    {
-        {"qmu_to_csw_sop_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_to_csw_eop_rd_cnt_reg[] = 
-    {
-        {"qmu_to_csw_eop_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_qmu_to_csw_drop_rd_cnt_reg[] = 
-    {
-        {"qmu_to_csw_drop_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_mmu_to_qmu_wr_release_cnt_reg[] = 
-    {
-        {"mmu_to_qmu_wr_release_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_mmu_to_qmu_rd_release_cnt_reg[] = 
-    {
-        {"mmu_to_qmu_rd_release_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_observe_qnum_set_reg[] = 
-    {
-        {"observe_qnum_set", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_q_pkt_received_reg[] = 
-    {
-        {"spec_q_pkt_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_q_pkt_dropped_reg[] = 
-    {
-        {"spec_q_pkt_dropped", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_q_pkt_scheduled_reg[] = 
-    {
-        {"spec_q_pkt_scheduled", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_q_wr_cmd_sent_reg[] = 
-    {
-        {"spec_q_wr_cmd_sent", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_q_rd_cmd_sent_reg[] = 
-    {
-        {"spec_q_rd_cmd_sent", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_q_pkt_enq_reg[] = 
-    {
-        {"spec_q_pkt_enq", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_q_pkt_deq_reg[] = 
-    {
-        {"spec_q_pkt_deq", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_q_crdt_uncon_received_reg[] = 
-    {
-        {"spec_q_crdt_uncon_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_q_crdt_cong_received_reg[] = 
-    {
-        {"spec_q_crdt_cong_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_q_crs_normal_cnt_reg[] = 
-    {
-        {"spec_q_crs_normal_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_q_crs_off_cnt_reg[] = 
-    {
-        {"spec_q_crs_off_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_observe_batch_set_reg[] = 
-    {
-        {"observe_batch_set", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_bat_pkt_received_reg[] = 
-    {
-        {"spec_bat_pkt_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_bat_pkt_dropped_reg[] = 
-    {
-        {"spec_bat_pkt_dropped", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_bat_blk_scheduled_reg[] = 
-    {
-        {"spec_bat_blk_scheduled", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_bat_wr_cmd_sent_reg[] = 
-    {
-        {"spec_bat_wr_cmd_sent", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_bat_rd_cmd_sent_reg[] = 
-    {
-        {"spec_bat_rd_cmd_sent", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_bat_pkt_enq_reg[] = 
-    {
-        {"spec_bat_pkt_enq", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_bat_pkt_deq_reg[] = 
-    {
-        {"spec_bat_pkt_deq", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_bat_crdt_uncon_received_reg[] = 
-    {
-        {"spec_bat_crdt_uncon_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_bat_crdt_cong_received_reg[] = 
-    {
-        {"spec_bat_crdt_cong_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_bat_crs_normal_cnt_reg[] = 
-    {
-        {"spec_bat_crs_normal_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_bat_crs_off_cnt_reg[] = 
-    {
-        {"spec_bat_crs_off_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_bcntm_ovfl_qnum_get_reg[] = 
-    {
-        {"bcntm_ovfl_qnum_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_crbal_a_ovf_qnum_get_reg[] = 
-    {
-        {"crbal_a_ovf_qnum_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_crbal_b_ovf_qnum_get_reg[] = 
-    {
-        {"crbal_b_ovf_qnum_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_crbal_drop_qnum_get_reg[] = 
-    {
-        {"crbal_drop_qnum_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_deq_flg_report_cnt_reg[] = 
-    {
-        {"deq_flg_report_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_q_crs_get_reg[] = 
-    {
-        {"spec_q_crs_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_q_crs_in_get_reg[] = 
-    {
-        {"spec_q_crs_in_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_spec_q_crs_flg_csol_get_reg[] = 
-    {
-        {"spec_q_crs_flg_csol_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_etm_qmu_ept_sch_qnum_get_reg[] = 
-    {
-        {"ept_sch_qnum_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_pcie_ddr_switch_reg[] = 
-    {
-        {"pcie_ddr_switch", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_user0_int_en_reg[] = 
-    {
-        {"user_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_user0_int_mask_reg[] = 
-    {
-        {"user_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_user0_int_status_reg[] = 
-    {
-        {"user_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_user1_int_en_reg[] = 
-    {
-        {"user_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_user1_int_mask_reg[] = 
-    {
-        {"user_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_user1_int_status_reg[] = 
-    {
-        {"user_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_user2_int_en_reg[] = 
-    {
-        {"user_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_user2_int_mask_reg[] = 
-    {
-        {"user_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_user2_int_status_reg[] = 
-    {
-        {"user_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_ecc_1b_int_en_reg[] = 
-    {
-        {"ecc_1b_int_en", DPP_FIELD_FLAG_RW, 2, 3, 0xfffff, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_ecc_1b_int_mask_reg[] = 
-    {
-        {"ecc_1b_int_mask", DPP_FIELD_FLAG_RW, 2, 3, 0xfffff, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_ecc_1b_int_status_reg[] = 
-    {
-        {"ecc_1b_int_status", DPP_FIELD_FLAG_RC, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_ecc_2b_int_en_reg[] = 
-    {
-        {"ecc_2b_int_en", DPP_FIELD_FLAG_RW, 2, 3, 0xfffff, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_ecc_2b_int_mask_reg[] = 
-    {
-        {"ecc_2b_int_mask", DPP_FIELD_FLAG_RW, 2, 3, 0xfffff, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_ecc_2b_int_status_reg[] = 
-    {
-        {"ecc_2b_int_status", DPP_FIELD_FLAG_RC, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_cfg_int_status_reg[] = 
-    {
-        {"cfg_int_status", DPP_FIELD_FLAG_RC, 4, 5, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_i_core_to_cntl_reg[] = 
-    {
-        {"i_core_to_cntl", DPP_FIELD_FLAG_RW, 15, 16, 0xaaaa, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_in_low_reg[] = 
-    {
-        {"test_in_low", DPP_FIELD_FLAG_RW, 31, 32, 0x00004000, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_in_high_reg[] = 
-    {
-        {"test_in_high", DPP_FIELD_FLAG_RW, 31, 32, 0x00000000, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_local_interrupt_out_reg[] = 
-    {
-        {"local_interrupt_out", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_pl_ltssm_reg[] = 
-    {
-        {"pl_ltssm", DPP_FIELD_FLAG_RO, 4, 5, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out0_reg[] = 
-    {
-        {"test_out0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out1_reg[] = 
-    {
-        {"test_out1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out2_reg[] = 
-    {
-        {"test_out2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out3_reg[] = 
-    {
-        {"test_out3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out4_reg[] = 
-    {
-        {"test_out4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out5_reg[] = 
-    {
-        {"test_out5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out6_reg[] = 
-    {
-        {"test_out6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out7_reg[] = 
-    {
-        {"test_out7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_sync_o_core_status_reg[] = 
-    {
-        {"sync_o_core_status", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_sync_o_alert_dbe_reg[] = 
-    {
-        {"sync_o_alert_dbe", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_sync_o_alert_sbe_reg[] = 
-    {
-        {"sync_o_alert_sbe", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_sync_o_link_loopback_en_reg[] = 
-    {
-        {"sync_o_link_loopback_en", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_sync_o_local_fs_lf_valid_reg[] = 
-    {
-        {"sync_o_local_fs_lf_valid", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_sync_o_rx_idle_detect_reg[] = 
-    {
-        {"sync_o_rx_idle_detect", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_sync_o_rx_rdy_reg[] = 
-    {
-        {"sync_o_rx_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_sync_o_tx_rdy_reg[] = 
-    {
-        {"sync_o_tx_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_pcie_link_up_cnt_reg[] = 
-    {
-        {"pcie_link_up_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out_pcie0_reg[] = 
-    {
-        {"test_out_pcie0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out_pcie1_reg[] = 
-    {
-        {"test_out_pcie1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out_pcie2_reg[] = 
-    {
-        {"test_out_pcie2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out_pcie3_reg[] = 
-    {
-        {"test_out_pcie3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out_pcie4_reg[] = 
-    {
-        {"test_out_pcie4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out_pcie5_reg[] = 
-    {
-        {"test_out_pcie5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out_pcie6_reg[] = 
-    {
-        {"test_out_pcie6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out_pcie7_reg[] = 
-    {
-        {"test_out_pcie7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out_pcie8_reg[] = 
-    {
-        {"test_out_pcie8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out_pcie9_reg[] = 
-    {
-        {"test_out_pcie9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out_pcie10_reg[] = 
-    {
-        {"test_out_pcie10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out_pcie11_reg[] = 
-    {
-        {"test_out_pcie11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out_pcie12_reg[] = 
-    {
-        {"test_out_pcie12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out_pcie13_reg[] = 
-    {
-        {"test_out_pcie13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out_pcie14_reg[] = 
-    {
-        {"test_out_pcie14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_test_out_pcie15_reg[] = 
-    {
-        {"test_out_pcie15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_int_repeat_en_reg[] = 
-    {
-        {"int_repeat_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_awid_axi_mst_reg[] = 
-    {
-        {"dbg_awid_axi_mst", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_awaddr_axi_mst0_reg[] = 
-    {
-        {"dbg_awaddr_axi_mst0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_awaddr_axi_mst1_reg[] = 
-    {
-        {"dbg_awaddr_axi_mst1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_awlen_axi_mst_reg[] = 
-    {
-        {"dbg_awlen_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_awsize_axi_mst_reg[] = 
-    {
-        {"dbg_awid_axi_mst", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_awburst_axi_mst_reg[] = 
-    {
-        {"dbg_awburst_axi_mst", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_awlock_axi_mst_reg[] = 
-    {
-        {"dbg_awlock_axi_mst", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_awcache_axi_mst_reg[] = 
-    {
-        {"dbg_awcache_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_awprot_axi_mst_reg[] = 
-    {
-        {"dbg_awprot_axi_mst", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_wid_axi_mst_reg[] = 
-    {
-        {"dbg_wid_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_wdata_axi_mst0_reg[] = 
-    {
-        {"dbg_wdata_axi_mst0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_wdata_axi_mst1_reg[] = 
-    {
-        {"dbg_wdata_axi_mst1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_wdata_axi_mst2_reg[] = 
-    {
-        {"dbg_wdata_axi_mst2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_wdata_axi_mst3_reg[] = 
-    {
-        {"dbg_wdata_axi_mst3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_wstrb_axi_mst_reg[] = 
-    {
-        {"dbg_wstrb_axi_mst", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_wlast_axi_mst_reg[] = 
-    {
-        {"dbg_wlast_axi_mst", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_arid_axi_mst_reg[] = 
-    {
-        {"dbg_arid_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_araddr_axi_mst0_reg[] = 
-    {
-        {"dbg_araddr_axi_mst0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_araddr_axi_mst1_reg[] = 
-    {
-        {"dbg_araddr_axi_mst1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_arlen_axi_mst_reg[] = 
-    {
-        {"dbg_arlen_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_arsize_axi_mst_reg[] = 
-    {
-        {"dbg_arsize_axi_mst", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_arburst_axi_mst_reg[] = 
-    {
-        {"dbg_arburst_axi_mst", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_arlock_axi_mst_reg[] = 
-    {
-        {"dbg_arlock_axi_mst", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_arcache_axi_mst_reg[] = 
-    {
-        {"dbg_arcache_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_arprot_axi_mst_reg[] = 
-    {
-        {"dbg_arprot_axi_mst", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_rdata_axi_mst0_reg[] = 
-    {
-        {"dbg_rdata_axi_mst0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_rdata_axi_mst1_reg[] = 
-    {
-        {"dbg_rdata_axi_mst1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_rdata_axi_mst2_reg[] = 
-    {
-        {"dbg_rdata_axi_mst2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_rdata_axi_mst3_reg[] = 
-    {
-        {"dbg_rdata_axi_mst3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_axi_mst_state_reg[] = 
-    {
-        {"axi_mst_state", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_axi_cfg_state_reg[] = 
-    {
-        {"axi_cfg_state", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_axi_slv_rd_state_reg[] = 
-    {
-        {"axi_slv_rd_state", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_axi_slv_wr_state_reg[] = 
-    {
-        {"axi_slv_wr_state", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_axim_delay_en_reg[] = 
-    {
-        {"axim_delay_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_axim_delay_reg[] = 
-    {
-        {"axim_delay", DPP_FIELD_FLAG_RW, 31, 32, 0xff, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_axim_speed_wr_reg[] = 
-    {
-        {"axim_speed_wr", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_axim_speed_rd_reg[] = 
-    {
-        {"axim_speed_rd", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_awaddr_axi_slv0_reg[] = 
-    {
-        {"dbg_awaddr_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_awaddr_axi_slv1_reg[] = 
-    {
-        {"dbg_awaddr_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg0_wdata_axi_slv0_reg[] = 
-    {
-        {"dbg0_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg0_wdata_axi_slv1_reg[] = 
-    {
-        {"dbg0_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg0_wdata_axi_slv2_reg[] = 
-    {
-        {"dbg0_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg0_wdata_axi_slv3_reg[] = 
-    {
-        {"dbg0_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg1_wdata_axi_slv0_reg[] = 
-    {
-        {"dbg1_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg1_wdata_axi_slv1_reg[] = 
-    {
-        {"dbg1_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg1_wdata_axi_slv2_reg[] = 
-    {
-        {"dbg1_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg1_wdata_axi_slv3_reg[] = 
-    {
-        {"dbg1_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg2_wdata_axi_slv0_reg[] = 
-    {
-        {"dbg2_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg2_wdata_axi_slv1_reg[] = 
-    {
-        {"dbg2_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg2_wdata_axi_slv2_reg[] = 
-    {
-        {"dbg2_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg2_wdata_axi_slv3_reg[] = 
-    {
-        {"dbg2_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg3_wdata_axi_slv0_reg[] = 
-    {
-        {"dbg3_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg3_wdata_axi_slv1_reg[] = 
-    {
-        {"dbg3_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg3_wdata_axi_slv2_reg[] = 
-    {
-        {"dbg3_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg3_wdata_axi_slv3_reg[] = 
-    {
-        {"dbg3_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg4_wdata_axi_slv0_reg[] = 
-    {
-        {"dbg4_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg4_wdata_axi_slv1_reg[] = 
-    {
-        {"dbg4_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg4_wdata_axi_slv2_reg[] = 
-    {
-        {"dbg4_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg4_wdata_axi_slv3_reg[] = 
-    {
-        {"dbg4_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg5_wdata_axi_slv0_reg[] = 
-    {
-        {"dbg5_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg5_wdata_axi_slv1_reg[] = 
-    {
-        {"dbg5_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg5_wdata_axi_slv2_reg[] = 
-    {
-        {"dbg5_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg5_wdata_axi_slv3_reg[] = 
-    {
-        {"dbg5_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg6_wdata_axi_slv0_reg[] = 
-    {
-        {"dbg6_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg6_wdata_axi_slv1_reg[] = 
-    {
-        {"dbg6_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg6_wdata_axi_slv2_reg[] = 
-    {
-        {"dbg6_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg6_wdata_axi_slv3_reg[] = 
-    {
-        {"dbg6_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg7_wdata_axi_slv0_reg[] = 
-    {
-        {"dbg7_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg7_wdata_axi_slv1_reg[] = 
-    {
-        {"dbg7_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg7_wdata_axi_slv2_reg[] = 
-    {
-        {"dbg7_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg7_wdata_axi_slv3_reg[] = 
-    {
-        {"dbg7_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg8_wdata_axi_slv0_reg[] = 
-    {
-        {"dbg8_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg8_wdata_axi_slv1_reg[] = 
-    {
-        {"dbg8_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg8_wdata_axi_slv2_reg[] = 
-    {
-        {"dbg8_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg8_wdata_axi_slv3_reg[] = 
-    {
-        {"dbg8_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg9_wdata_axi_slv0_reg[] = 
-    {
-        {"dbg9_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg9_wdata_axi_slv1_reg[] = 
-    {
-        {"dbg9_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg9_wdata_axi_slv2_reg[] = 
-    {
-        {"dbg9_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg9_wdata_axi_slv3_reg[] = 
-    {
-        {"dbg9_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_awlen_axi_slv_reg[] = 
-    {
-        {"dbg_awlen_axi_slv", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_wlast_axi_slv_reg[] = 
-    {
-        {"dbg_wlast_axi_slv", DPP_FIELD_FLAG_RO, 9, 10, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_araddr_axi_slv0_reg[] = 
-    {
-        {"dbg5_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_araddr_axi_slv1_reg[] = 
-    {
-        {"dbg5_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg0_rdata_axi_slv0_reg[] = 
-    {
-        {"dbg5_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg0_rdata_axi_slv1_reg[] = 
-    {
-        {"dbg6_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg0_rdata_axi_slv2_reg[] = 
-    {
-        {"dbg6_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg0_rdata_axi_slv3_reg[] = 
-    {
-        {"dbg6_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg1_rdata_axi_slv0_reg[] = 
-    {
-        {"dbg6_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg1_rdata_axi_slv1_reg[] = 
-    {
-        {"dbg7_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg1_rdata_axi_slv2_reg[] = 
-    {
-        {"dbg7_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg1_rdata_axi_slv3_reg[] = 
-    {
-        {"dbg7_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_pcie_dbg_rlast_axi_slv_reg[] = 
-    {
-        {"dbg_rlast_axi_slv", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_enable_reg[] = 
-    {
-        {"dma_enable", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_up_req_reg[] = 
-    {
-        {"up_req", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_up_current_state_reg[] = 
-    {
-        {"dma_up_current_state", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_up_req_ack_reg[] = 
-    {
-        {"dma_up_req_ack", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_done_latch_reg[] = 
-    {
-        {"done_latch", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_up_cpu_addr_low32_reg[] = 
-    {
-        {"dma_up_cpu_addr_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_up_cpu_addr_high32_reg[] = 
-    {
-        {"dma_up_cpu_addr_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_up_se_addr_reg[] = 
-    {
-        {"dma_up_se_addr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_done_int_reg[] = 
-    {
-        {"dma_done_int", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_sp_cfg_reg[] = 
-    {
-        {"sp_cfg", DPP_FIELD_FLAG_RW, 1, 2, 0x1, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_ing_reg[] = 
-    {
-        {"dma_ing", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_rd_timeout_thresh_reg[] = 
-    {
-        {"rd_timeout_thresh", DPP_FIELD_FLAG_RW, 31, 32, 0x7d0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_tab_sta_up_fifo_gap_reg[] = 
-    {
-        {"dma_tab_sta_up_fifo_gap", DPP_FIELD_FLAG_RW, 8, 9, 0xfa, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_cfg_mac_tim_reg[] = 
-    {
-        {"cfg_mac_tim", DPP_FIELD_FLAG_RW, 31, 32, 0x50, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_cfg_mac_num_reg[] = 
-    {
-        {"cfg_mac_num", DPP_FIELD_FLAG_RW, 8, 9, 0x28, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_init_bd_addr_reg[] = 
-    {
-        {"init_bd_addr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_mac_up_bd_addr1_low32_reg[] = 
-    {
-        {"mac_up_bd_addr1_low32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_mac_up_bd_addr1_high32_reg[] = 
-    {
-        {"mac_up_bd_addr1_high32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_mac_up_bd_addr2_low32_reg[] = 
-    {
-        {"mac_up_bd_addr2_low32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_mac_up_bd_addr2_high32_reg[] = 
-    {
-        {"mac_up_bd_addr2_high32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_cfg_mac_max_num_reg[] = 
-    {
-        {"cfg_mac_max_num", DPP_FIELD_FLAG_RW, 8, 9, 0x1ff, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_wbuf_ff_empty_reg[] = 
-    {
-        {"dma_wbuf_ff_empty", DPP_FIELD_FLAG_RO, 1, 2, 0x3, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_wbuf_state_reg[] = 
-    {
-        {"dma_wbuf_state", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_mac_bd_addr_low32_reg[] = 
-    {
-        {"dma_mac_bd_addr_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_mac_bd_addr_high32_reg[] = 
-    {
-        {"dma_mac_bd_addr_high32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_mac_up_enable_reg[] = 
-    {
-        {"mac_up_enable", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_mac_endian_reg[] = 
-    {
-        {"mac_endian", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_up_endian_reg[] = 
-    {
-        {"up_endian", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_up_rd_cnt_latch_reg[] = 
-    {
-        {"dma_up_rd_cnt_latch", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_up_rcv_cnt_latch_reg[] = 
-    {
-        {"dma_up_rcv_cnt_latch", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_up_cnt_latch_reg[] = 
-    {
-        {"dma_up_cnt_latch", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_cpu_rd_bd_pulse_reg[] = 
-    {
-        {"cpu_rd_bd_pulse", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_cpu_bd_threshold_reg[] = 
-    {
-        {"cpu_bd_threshold", DPP_FIELD_FLAG_RW, 31, 32, 0x64, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_cpu_bd_used_cnt_reg[] = 
-    {
-        {"cpu_bd_used_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_up_rcv_status_reg[] = 
-    {
-        {"dma_up_rcv_status", DPP_FIELD_FLAG_RO, 31, 32, 0x1, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_slv_rid_err_en_reg[] = 
-    {
-        {"slv_rid_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_slv_rresp_err_en_reg[] = 
-    {
-        {"slv_rresp_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_se_rdbk_ff_full_reg[] = 
-    {
-        {"se_rdbk_ff_full", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_up_data_count_reg[] = 
-    {
-        {"dma_up_data_count", DPP_FIELD_FLAG_RO, 9, 10, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_mwr_fifo_afull_gap_reg[] = 
-    {
-        {"dma_mwr_fifo_afull_gap", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_info_fifo_afull_gap_reg[] = 
-    {
-        {"dma_mwr_fifo_afull_gap", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_rd_timeout_set_reg[] = 
-    {
-        {"dma_rd_timeout_set", DPP_FIELD_FLAG_RW, 31, 32, 0x3ffffff, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_bd_dat_err_en_reg[] = 
-    {
-        {"dma_bd_dat_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_repeat_cnt_reg[] = 
-    {
-        {"dma_repeat_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_rd_timeout_en_reg[] = 
-    {
-        {"dma_rd_timeout_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_repeat_read_reg[] = 
-    {
-        {"dma_repeat_read", DPP_FIELD_FLAG_RW, 31, 32, 0xa, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_repeat_read_en_reg[] = 
-    {
-        {"dma_repeat_read_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_bd_ctl_state_reg[] = 
-    {
-        {"bd_ctl_state", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_done_int_cnt_wr_reg[] = 
-    {
-        {"dma_done_int_cnt_wr", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_done_int_cnt_mac_reg[] = 
-    {
-        {"dma_done_int_cnt_mac", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_current_mac_num_reg[] = 
-    {
-        {"current_mac_num", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_cfg_mac_afifo_afull_reg[] = 
-    {
-        {"cfg_mac_afifo_afull", DPP_FIELD_FLAG_RW, 8, 9, 0xc8, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_dma_mac_ff_full_reg[] = 
-    {
-        {"dma_mac_ff_full", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_dma_user_axi_mst_reg[] = 
-    {
-        {"user_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"cfg_epid", DPP_FIELD_FLAG_RW, 27, 4, 0x0, 0x0},
-        {"cfg_vfunc_num", DPP_FIELD_FLAG_RW, 23, 8, 0x0, 0x0},
-        {"cfg_func_num", DPP_FIELD_FLAG_RW, 7, 3, 0x0, 0x0},
-        {"cfg_vfunc_active", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_sbus_state_reg[] = 
-    {
-        {"sbus_state", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_en_reg[] = 
-    {
-        {"mst_debug_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_sbus_command_sel_reg[] = 
-    {
-        {"sbus_command_sel", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_soc_rd_time_out_thresh_reg[] = 
-    {
-        {"soc_rd_time_out_thresh", DPP_FIELD_FLAG_RW, 31, 32, 0x2710, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_big_little_byte_order_reg[] = 
-    {
-        {"big_little_byte_order", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_ecc_bypass_read_reg[] = 
-    {
-        {"ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_ahb_async_wr_fifo_afull_gap_reg[] = 
-    {
-        {"ahb_async_wr_fifo_afull_gap", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_ahb_async_rd_fifo_afull_gap_reg[] = 
-    {
-        {"ahb_async_rd_fifo_afull_gap", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_ahb_async_cpl_fifo_afull_gap_reg[] = 
-    {
-        {"ahb_async_cpl_fifo_afull_gap", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data0_high26_reg[] = 
-    {
-        {"mst_debug_data0_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data0_low32_reg[] = 
-    {
-        {"mst_debug_data0_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data1_high26_reg[] = 
-    {
-        {"mst_debug_data1_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data1_low32_reg[] = 
-    {
-        {"mst_debug_data1_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data2_high26_reg[] = 
-    {
-        {"mst_debug_data2_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data2_low32_reg[] = 
-    {
-        {"mst_debug_data2_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data3_high26_reg[] = 
-    {
-        {"mst_debug_data3_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data3_low32_reg[] = 
-    {
-        {"mst_debug_data3_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data4_high26_reg[] = 
-    {
-        {"mst_debug_data4_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data4_low32_reg[] = 
-    {
-        {"mst_debug_data4_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data5_high26_reg[] = 
-    {
-        {"mst_debug_data5_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data5_low32_reg[] = 
-    {
-        {"mst_debug_data5_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data6_high26_reg[] = 
-    {
-        {"mst_debug_data6_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data6_low32_reg[] = 
-    {
-        {"mst_debug_data6_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data7_high26_reg[] = 
-    {
-        {"mst_debug_data7_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data7_low32_reg[] = 
-    {
-        {"mst_debug_data7_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data8_high26_reg[] = 
-    {
-        {"mst_debug_data8_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data8_low32_reg[] = 
-    {
-        {"mst_debug_data8_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data9_high26_reg[] = 
-    {
-        {"mst_debug_data9_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data9_low32_reg[] = 
-    {
-        {"mst_debug_data9_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data10_high26_reg[] = 
-    {
-        {"mst_debug_data10_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data10_low32_reg[] = 
-    {
-        {"mst_debug_data10_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data11_high26_reg[] = 
-    {
-        {"mst_debug_data11_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data11_low32_reg[] = 
-    {
-        {"mst_debug_data11_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data12_high26_reg[] = 
-    {
-        {"mst_debug_data12_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data12_low32_reg[] = 
-    {
-        {"mst_debug_data12_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data13_high26_reg[] = 
-    {
-        {"mst_debug_data13_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data13_low32_reg[] = 
-    {
-        {"mst_debug_data13_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data14_high26_reg[] = 
-    {
-        {"mst_debug_data14_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data14_low32_reg[] = 
-    {
-        {"mst_debug_data14_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data15_high26_reg[] = 
-    {
-        {"mst_debug_data15_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_cfg_csr_mst_debug_data15_low32_reg[] = 
-    {
-        {"mst_debug_data15_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_ind_access_states_reg[] = 
-    {
-        {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_ind_access_cmd0_reg[] = 
-    {
-        {"wr_mode", DPP_FIELD_FLAG_RW, 29, 1, 0x0, 0x0},
-        {"rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0},
-        {"ind_access_addr0", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_ind_access_data0_reg[] = 
-    {
-        {"ind_access_data0", DPP_FIELD_FLAG_RW, 20, 21, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_ind_access_data1_reg[] = 
-    {
-        {"ind_access_data1", DPP_FIELD_FLAG_RW, 20, 21, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_ind_access_cmd1_reg[] = 
-    {
-        {"ind_access_addr1", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_init_done_reg[] = 
-    {
-        {"mr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_cnt_mode_reg_reg[] = 
-    {
-        {"cfgmt_count_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_cfg_ecc_bypass_read_reg[] = 
-    {
-        {"cfg_ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_cfg_rep_mod_reg[] = 
-    {
-        {"cfg_rep_mod", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_block_ptr_fifo_aful_th_reg[] = 
-    {
-        {"block_ptr3_fifo_aful_th", DPP_FIELD_FLAG_RW, 31, 8, 0xa0, 0x0},
-        {"block_ptr2_fifo_aful_th", DPP_FIELD_FLAG_RW, 23, 8, 0xa0, 0x0},
-        {"block_ptr1_fifo_aful_th", DPP_FIELD_FLAG_RW, 15, 8, 0xa0, 0x0},
-        {"block_ptr0_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0xa0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_pre_rcv_ptr_fifo_aful_th_reg[] = 
-    {
-        {"pre_rcv_ptr3_fifo_aful_th", DPP_FIELD_FLAG_RW, 31, 8, 0xa0, 0x0},
-        {"pre_rcv_ptr2_fifo_aful_th", DPP_FIELD_FLAG_RW, 23, 8, 0xa0, 0x0},
-        {"pre_rcv_ptr1_fifo_aful_th", DPP_FIELD_FLAG_RW, 15, 8, 0xa0, 0x0},
-        {"pre_rcv_ptr0_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0xa0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mgid_fifo_aful_th_reg[] = 
-    {
-        {"mgid3_fifo_aful_th", DPP_FIELD_FLAG_RW, 31, 8, 0xa0, 0x0},
-        {"mgid2_fifo_aful_th", DPP_FIELD_FLAG_RW, 23, 8, 0xa0, 0x0},
-        {"mgid1_fifo_aful_th", DPP_FIELD_FLAG_RW, 15, 8, 0xa0, 0x0},
-        {"mgid0_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0xa0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_rep_cmd_fifo_aful_th_reg[] = 
-    {
-        {"rep_cmd3_fifo_aful_th", DPP_FIELD_FLAG_RW, 31, 8, 0x14, 0x0},
-        {"rep_cmd2_fifo_aful_th", DPP_FIELD_FLAG_RW, 23, 8, 0x14, 0x0},
-        {"rep_cmd1_fifo_aful_th", DPP_FIELD_FLAG_RW, 15, 8, 0x14, 0x0},
-        {"rep_cmd0_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0x14, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_int_mask_1_reg[] = 
-    {
-        {"free_ptr0_fifo_full_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"free_ptr1_fifo_full_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"free_ptr2_fifo_full_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"free_ptr3_fifo_full_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"block_ptr0_fifo_full_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"block_ptr1_fifo_full_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"block_ptr2_fifo_full_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"block_ptr3_fifo_full_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"mgid0_fifo_full_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"mgid1_fifo_full_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"mgid2_fifo_full_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"mgid3_fifo_full_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"pre_rcv_ptr0_fifo_full_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"pre_rcv_ptr1_fifo_full_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"pre_rcv_ptr2_fifo_full_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"pre_rcv_ptr3_fifo_full_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"rep_cmd0_fifo_full_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"rep_cmd1_fifo_full_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"rep_cmd2_fifo_full_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"rep_cmd3_fifo_full_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_int_mask_2_reg[] = 
-    {
-        {"free_ptr0_fifo_udf_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"free_ptr1_fifo_udf_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"free_ptr2_fifo_udf_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"free_ptr3_fifo_udf_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"block_ptr0_fifo_udf_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"block_ptr1_fifo_udf_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"block_ptr2_fifo_udf_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"block_ptr3_fifo_udf_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"mgid0_fifo_udf_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"mgid1_fifo_udf_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"mgid2_fifo_udf_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"mgid3_fifo_udf_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"pre_rcv_ptr0_fifo_udf_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"pre_rcv_ptr1_fifo_udf_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"pre_rcv_ptr2_fifo_udf_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"pre_rcv_ptr3_fifo_udf_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"rep_cmd0_fifo_udf_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"rep_cmd1_fifo_udf_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"rep_cmd2_fifo_udf_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"rep_cmd3_fifo_udf_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_int_mask_3_reg[] = 
-    {
-        {"free_ptr0_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"free_ptr1_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"free_ptr2_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"free_ptr3_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"block_ptr0_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"block_ptr1_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"block_ptr2_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"block_ptr3_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"mgid0_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"mgid1_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"mgid2_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"mgid3_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"pre_rcv_ptr0_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"pre_rcv_ptr1_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"pre_rcv_ptr2_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"pre_rcv_ptr3_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"rep_cmd0_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"rep_cmd1_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"rep_cmd2_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"rep_cmd3_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_int_mask_4_reg[] = 
-    {
-        {"data_buf0_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"data_buf1_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"data_buf2_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"data_buf3_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"mlt_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"free_ptr0_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"free_ptr1_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"free_ptr2_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"free_ptr3_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"block_ptr0_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"block_ptr1_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"block_ptr2_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"block_ptr3_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"mgid0_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"mgid1_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"mgid2_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"mgid3_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"pre_rcv_ptr0_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"pre_rcv_ptr1_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"pre_rcv_ptr2_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"pre_rcv_ptr3_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"rep_cmd0_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"rep_cmd1_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"rep_cmd2_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"rep_cmd3_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_states_1_reg[] = 
-    {
-        {"free_ptr0_fifo_full", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"free_ptr1_fifo_full", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"free_ptr2_fifo_full", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"free_ptr3_fifo_full", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"block_ptr0_fifo_full", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"block_ptr1_fifo_full", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"block_ptr2_fifo_full", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"block_ptr3_fifo_full", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"mgid0_fifo_full", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"mgid1_fifo_full", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"mgid2_fifo_full", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"mgid3_fifo_full", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"pre_rcv_ptr0_fifo_full", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"pre_rcv_ptr1_fifo_full", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"pre_rcv_ptr2_fifo_full", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"pre_rcv_ptr3_fifo_full", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"rep_cmd0_fifo_full", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"rep_cmd1_fifo_full", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"rep_cmd2_fifo_full", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"rep_cmd3_fifo_full", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_states_2_reg[] = 
-    {
-        {"free_ptr0_fifo_udf", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"free_ptr1_fifo_udf", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"free_ptr2_fifo_udf", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"free_ptr3_fifo_udf", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"block_ptr0_fifo_udf", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"block_ptr1_fifo_udf", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"block_ptr2_fifo_udf", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"block_ptr3_fifo_udf", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"mgid0_fifo_udf", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"mgid1_fifo_udf", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"mgid2_fifo_udf", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"mgid3_fifo_udf", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"pre_rcv_ptr0_fifo_udf", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"pre_rcv_ptr1_fifo_udf", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"pre_rcv_ptr2_fifo_udf", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"pre_rcv_ptr3_fifo_udf", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"rep_cmd0_fifo_udf", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"rep_cmd1_fifo_udf", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"rep_cmd2_fifo_udf", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"rep_cmd3_fifo_udf", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_states_3_reg[] = 
-    {
-        {"free_ptr0_fifo_ovf", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"free_ptr1_fifo_ovf", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"free_ptr2_fifo_ovf", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"free_ptr3_fifo_ovf", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"block_ptr0_fifo_ovf", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"block_ptr1_fifo_ovf", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"block_ptr2_fifo_ovf", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"block_ptr3_fifo_ovf", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"mgid0_fifo_ovf", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"mgid1_fifo_ovf", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"mgid2_fifo_ovf", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"mgid3_fifo_ovf", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"pre_rcv_ptr0_fifo_ovf", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"pre_rcv_ptr1_fifo_ovf", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"pre_rcv_ptr2_fifo_ovf", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"pre_rcv_ptr3_fifo_ovf", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"rep_cmd0_fifo_ovf", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"rep_cmd1_fifo_ovf", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"rep_cmd2_fifo_ovf", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"rep_cmd3_fifo_ovf", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_states_4_reg[] = 
-    {
-        {"data_buf0_ram_parity_err", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"data_buf1_ram_parity_err", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"data_buf2_ram_parity_err", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"data_buf3_ram_parity_err", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"mlt_ecc_single_err", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"free_ptr0_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"free_ptr1_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"free_ptr2_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"free_ptr3_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"block_ptr0_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"block_ptr1_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"block_ptr2_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"block_ptr3_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"mgid0_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"mgid1_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"mgid2_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"mgid3_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"pre_rcv_ptr0_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"pre_rcv_ptr1_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"pre_rcv_ptr2_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"pre_rcv_ptr3_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"rep_cmd0_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"rep_cmd1_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"rep_cmd2_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"rep_cmd3_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_states_5_reg[] = 
-    {
-        {"mlt_ecc_double_err", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"free_ptr0_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"free_ptr1_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"free_ptr2_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"free_ptr3_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"block_ptr0_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"block_ptr1_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"block_ptr2_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"block_ptr3_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"mgid0_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"mgid1_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"mgid2_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"mgid3_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"pre_rcv_ptr0_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"pre_rcv_ptr1_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"pre_rcv_ptr2_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"pre_rcv_ptr3_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"rep_cmd0_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"rep_cmd1_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"rep_cmd2_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"rep_cmd3_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_states_6_reg[] = 
-    {
-        {"free_ptr0_fifo_empty", DPP_FIELD_FLAG_RO, 19, 1, 0x1, 0x0},
-        {"free_ptr1_fifo_empty", DPP_FIELD_FLAG_RO, 18, 1, 0x1, 0x0},
-        {"free_ptr2_fifo_empty", DPP_FIELD_FLAG_RO, 17, 1, 0x1, 0x0},
-        {"free_ptr3_fifo_empty", DPP_FIELD_FLAG_RO, 16, 1, 0x1, 0x0},
-        {"block_ptr0_fifo_empty", DPP_FIELD_FLAG_RO, 15, 1, 0x1, 0x0},
-        {"block_ptr1_fifo_empty", DPP_FIELD_FLAG_RO, 14, 1, 0x1, 0x0},
-        {"block_ptr2_fifo_empty", DPP_FIELD_FLAG_RO, 13, 1, 0x1, 0x0},
-        {"block_ptr3_fifo_empty", DPP_FIELD_FLAG_RO, 12, 1, 0x1, 0x0},
-        {"mgid0_fifo_empty", DPP_FIELD_FLAG_RO, 11, 1, 0x1, 0x0},
-        {"mgid1_fifo_empty", DPP_FIELD_FLAG_RO, 10, 1, 0x1, 0x0},
-        {"mgid2_fifo_empty", DPP_FIELD_FLAG_RO, 9, 1, 0x1, 0x0},
-        {"mgid3_fifo_empty", DPP_FIELD_FLAG_RO, 8, 1, 0x1, 0x0},
-        {"pre_rcv_ptr0_fifo_empty", DPP_FIELD_FLAG_RO, 7, 1, 0x1, 0x0},
-        {"pre_rcv_ptr1_fifo_empty", DPP_FIELD_FLAG_RO, 6, 1, 0x1, 0x0},
-        {"pre_rcv_ptr2_fifo_empty", DPP_FIELD_FLAG_RO, 5, 1, 0x1, 0x0},
-        {"pre_rcv_ptr3_fifo_empty", DPP_FIELD_FLAG_RO, 4, 1, 0x1, 0x0},
-        {"rep_cmd0_fifo_empty", DPP_FIELD_FLAG_RO, 3, 1, 0x1, 0x0},
-        {"rep_cmd1_fifo_empty", DPP_FIELD_FLAG_RO, 2, 1, 0x1, 0x0},
-        {"rep_cmd2_fifo_empty", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0},
-        {"rep_cmd3_fifo_empty", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_states_7_reg[] = 
-    {
-        {"cos0_is_rep_busy", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0},
-        {"cos1_is_rep_busy", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0},
-        {"cos2_is_rep_busy", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0},
-        {"cos3_is_rep_busy", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0},
-        {"block_ptr0_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0},
-        {"block_ptr1_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0},
-        {"block_ptr2_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0},
-        {"block_ptr3_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0},
-        {"pre_rcv_ptr0_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0},
-        {"pre_rcv_ptr1_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0},
-        {"pre_rcv_ptr2_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0},
-        {"pre_rcv_ptr3_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0},
-        {"port_shap_rdy", DPP_FIELD_FLAG_RO, 9, 1, 0x1, 0x0},
-        {"mr_lif_group0_rdy_3", DPP_FIELD_FLAG_RO, 8, 1, 0x1, 0x0},
-        {"mr_lif_group0_rdy_2", DPP_FIELD_FLAG_RO, 7, 1, 0x1, 0x0},
-        {"mr_lif_group0_rdy_1", DPP_FIELD_FLAG_RO, 6, 1, 0x1, 0x0},
-        {"mr_lif_group0_rdy_0", DPP_FIELD_FLAG_RO, 5, 1, 0x1, 0x0},
-        {"pktrx_pfc_rdy_3", DPP_FIELD_FLAG_RO, 4, 1, 0x1, 0x0},
-        {"pktrx_pfc_rdy_2", DPP_FIELD_FLAG_RO, 3, 1, 0x1, 0x0},
-        {"pktrx_pfc_rdy_1", DPP_FIELD_FLAG_RO, 2, 1, 0x1, 0x0},
-        {"pktrx_pfc_rdy_0", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0},
-        {"pktrx_link_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_states_8_reg[] = 
-    {
-        {"mr_head", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_sop_in_cnt_reg[] = 
-    {
-        {"mr_sop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_eop_in_cnt_reg[] = 
-    {
-        {"mr_eop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_sop_out_cnt_reg[] = 
-    {
-        {"mr_sop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_eop_out_cnt_reg[] = 
-    {
-        {"mr_eop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_in_cnt_reg[] = 
-    {
-        {"mr_cos0_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_in_cnt_reg[] = 
-    {
-        {"mr_cos1_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_in_cnt_reg[] = 
-    {
-        {"mr_cos2_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_in_cnt_reg[] = 
-    {
-        {"mr_cos3_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_out_cnt_reg[] = 
-    {
-        {"mr_cos0_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_out_cnt_reg[] = 
-    {
-        {"mr_cos1_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_out_cnt_reg[] = 
-    {
-        {"mr_cos2_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_out_cnt_reg[] = 
-    {
-        {"mr_cos3_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_err_in_cnt_reg[] = 
-    {
-        {"mr_err_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_sop_in_cnt_reg[] = 
-    {
-        {"mr_cos0_sop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_eop_in_cnt_reg[] = 
-    {
-        {"mr_cos0_eop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_sop_in_cnt_reg[] = 
-    {
-        {"mr_cos1_sop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_eop_in_cnt_reg[] = 
-    {
-        {"mr_cos1_eop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_sop_in_cnt_reg[] = 
-    {
-        {"mr_cos2_sop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_eop_in_cnt_reg[] = 
-    {
-        {"mr_cos2_eop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_sop_in_cnt_reg[] = 
-    {
-        {"mr_cos3_sop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_eop_in_cnt_reg[] = 
-    {
-        {"mr_cos3_eop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_in_err_cnt_reg[] = 
-    {
-        {"mr_cos0_in_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_in_err_cnt_reg[] = 
-    {
-        {"mr_cos1_in_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_in_err_cnt_reg[] = 
-    {
-        {"mr_cos2_in_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_in_err_cnt_reg[] = 
-    {
-        {"mr_cos3_in_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_sop_out_cnt_reg[] = 
-    {
-        {"mr_cos0_sop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_eop_out_cnt_reg[] = 
-    {
-        {"mr_cos0_eop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_sop_out_cnt_reg[] = 
-    {
-        {"mr_cos1_sop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_eop_out_cnt_reg[] = 
-    {
-        {"mr_cos1_eop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_sop_out_cnt_reg[] = 
-    {
-        {"mr_cos2_sop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_eop_out_cnt_reg[] = 
-    {
-        {"mr_cos2_eop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_sop_out_cnt_reg[] = 
-    {
-        {"mr_cos3_sop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_eop_out_cnt_reg[] = 
-    {
-        {"mr_cos3_eop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_mlt_unvld_cnt_reg[] = 
-    {
-        {"mr_mlt_unvld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_sop_eop_match_cfg_reg[] = 
-    {
-        {"mr_sop_eop_macth_en", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"mr_sop_eop_macth_dicard_th", DPP_FIELD_FLAG_RW, 7, 8, 0xbc, 0x0},
-    };
-DPP_FIELD_T g_nppu_mr_cfg_mr_mlt_unvld_mgid_reg[] = 
-    {
-        {"mr_mlt_unvld_mgid", DPP_FIELD_FLAG_RO, 16, 17, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_isch_fifo_th_1_reg[] = 
-    {
-        {"cfg_sch_fifo7_fc_th", DPP_FIELD_FLAG_RW, 29, 6, 0x30, 0x0},
-        {"cfg_sch_fifo6_fc_th", DPP_FIELD_FLAG_RW, 21, 6, 0x30, 0x0},
-        {"cfg_sch_fifo5_fc_th", DPP_FIELD_FLAG_RW, 13, 6, 0x30, 0x0},
-        {"cfg_sch_fifo4_fc_th", DPP_FIELD_FLAG_RW, 5, 6, 0x30, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_isch_fifo_th_2_reg[] = 
-    {
-        {"cfg_sch_fifo3_drop_th", DPP_FIELD_FLAG_RW, 29, 6, 0x38, 0x0},
-        {"cfg_sch_fifo1_drop_th", DPP_FIELD_FLAG_RW, 21, 6, 0x38, 0x0},
-        {"cfg_sch_fifo0_drop_th", DPP_FIELD_FLAG_RW, 13, 6, 0x38, 0x0},
-        {"cfg_sch_fifo8_fc_th", DPP_FIELD_FLAG_RW, 5, 6, 0x30, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_isch_fifo_th_3_reg[] = 
-    {
-        {"cfg_sch_fifo6_drop_th", DPP_FIELD_FLAG_RW, 29, 6, 0x38, 0x0},
-        {"cfg_sch_fifo5_drop_th", DPP_FIELD_FLAG_RW, 21, 6, 0x38, 0x0},
-        {"cfg_sch_fifo4_drop_th", DPP_FIELD_FLAG_RW, 13, 6, 0x38, 0x0},
-        {"cfg_sch_fifo2_drop_th", DPP_FIELD_FLAG_RW, 5, 6, 0x38, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_isch_fifo_th_4_reg[] = 
-    {
-        {"cfg_sch_fifo9_fc_th", DPP_FIELD_FLAG_RW, 29, 6, 0x30, 0x0},
-        {"cfg_sch_fifo9_drop_th", DPP_FIELD_FLAG_RW, 21, 6, 0x38, 0x0},
-        {"cfg_sch_fifo8_drop_th", DPP_FIELD_FLAG_RW, 13, 6, 0x38, 0x0},
-        {"cfg_sch_fifo7_drop_th", DPP_FIELD_FLAG_RW, 5, 6, 0x38, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_isch_cfg_0_reg[] = 
-    {
-        {"cfg_sch_wrr1_weight1", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_hdu_ex_tpid_0_reg[] = 
-    {
-        {"cfg_type0", DPP_FIELD_FLAG_RW, 31, 16, 0x8100, 0x0},
-        {"cfg_type1", DPP_FIELD_FLAG_RW, 15, 16, 0x9100, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_hdu_ex_tpid_1_reg[] = 
-    {
-        {"cfg_type2", DPP_FIELD_FLAG_RW, 31, 16, 0x88a8, 0x0},
-        {"cfg_type3", DPP_FIELD_FLAG_RW, 15, 16, 0x9200, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_hdu_int_tpid_0_reg[] = 
-    {
-        {"cfg_inner_type0", DPP_FIELD_FLAG_RW, 31, 16, 0x8100, 0x0},
-        {"cfg_inner_type1", DPP_FIELD_FLAG_RW, 15, 16, 0x9100, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_hdu_int_tpid_1_reg[] = 
-    {
-        {"cfg_inner_type2", DPP_FIELD_FLAG_RW, 31, 16, 0x88a8, 0x0},
-        {"cfg_inner_type3", DPP_FIELD_FLAG_RW, 15, 16, 0x9200, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_hdu_hdlc_0_reg[] = 
-    {
-        {"hdlc_cfg0_type", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0},
-        {"hdlc_cfg1_type", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_hdu_hdlc_1_reg[] = 
-    {
-        {"hdlc_cfg2_type", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0},
-        {"hdlc_cfg3_type", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l3type_0_reg[] = 
-    {
-        {"cfg_l3_type0", DPP_FIELD_FLAG_RW, 31, 16, 0xffff, 0x0},
-        {"cfg_l3_type1", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l3type_1_reg[] = 
-    {
-        {"cfg_l3_type2", DPP_FIELD_FLAG_RW, 31, 16, 0xffff, 0x0},
-        {"cfg_l3_type3", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l3type_2_reg[] = 
-    {
-        {"cfg_l3_type4", DPP_FIELD_FLAG_RW, 31, 16, 0xffff, 0x0},
-        {"cfg_l3_type5", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l3type_3_reg[] = 
-    {
-        {"cfg_l3_type6", DPP_FIELD_FLAG_RW, 31, 16, 0xffff, 0x0},
-        {"cfg_l3_type7", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l4type_0_reg[] = 
-    {
-        {"cfg_l4_type0", DPP_FIELD_FLAG_RW, 31, 8, 0xff, 0x0},
-        {"cfg_l4_type1", DPP_FIELD_FLAG_RW, 23, 8, 0xff, 0x0},
-        {"cfg_l4_type2", DPP_FIELD_FLAG_RW, 15, 8, 0xff, 0x0},
-        {"cfg_l4_type3", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l4type_1_reg[] = 
-    {
-        {"cfg_l4_type4", DPP_FIELD_FLAG_RW, 31, 8, 0xff, 0x0},
-        {"cfg_l4_type5", DPP_FIELD_FLAG_RW, 23, 8, 0xff, 0x0},
-        {"cfg_l4_type6", DPP_FIELD_FLAG_RW, 15, 8, 0xff, 0x0},
-        {"cfg_l4_type7", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l4type_2_reg[] = 
-    {
-        {"cfg_l4_type8", DPP_FIELD_FLAG_RW, 23, 8, 0xff, 0x0},
-        {"cfg_l4_type9", DPP_FIELD_FLAG_RW, 15, 8, 0xff, 0x0},
-        {"cfg_l4_type10", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_slot_no_cfg_reg[] = 
-    {
-        {"cfg_parser_slot_no", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_int_en_0_reg[] = 
-    {
-        {"pktrx_int_en_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"pktrx_int_en_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"pktrx_int_en_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"pktrx_int_en_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"pktrx_int_en_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"pktrx_int_en_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"pktrx_int_en_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"pktrx_int_en_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"pktrx_int_en_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"pktrx_int_en_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"pktrx_int_en_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"pktrx_int_en_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"pktrx_int_en_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"pktrx_int_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"pktrx_int_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"pktrx_int_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"pktrx_int_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"pktrx_int_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"pktrx_int_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"pktrx_int_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"pktrx_int_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"pktrx_int_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"pktrx_int_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"pktrx_int_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"pktrx_int_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"pktrx_int_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"pktrx_int_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"pktrx_int_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"pktrx_int_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"pktrx_int_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"pktrx_int_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"pktrx_int_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_int_en_1_reg[] = 
-    {
-        {"pktrx_int_en_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"pktrx_int_en_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"pktrx_int_en_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"pktrx_int_en_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_int_mask_0_reg[] = 
-    {
-        {"pktrx_int_mask_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"pktrx_int_mask_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"pktrx_int_mask_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"pktrx_int_mask_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"pktrx_int_mask_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"pktrx_int_mask_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"pktrx_int_mask_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"pktrx_int_mask_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"pktrx_int_mask_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"pktrx_int_mask_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"pktrx_int_mask_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"pktrx_int_mask_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"pktrx_int_mask_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"pktrx_int_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"pktrx_int_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"pktrx_int_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"pktrx_int_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"pktrx_int_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"pktrx_int_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"pktrx_int_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"pktrx_int_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"pktrx_int_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"pktrx_int_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"pktrx_int_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"pktrx_int_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"pktrx_int_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"pktrx_int_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"pktrx_int_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"pktrx_int_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"pktrx_int_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"pktrx_int_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"pktrx_int_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_int_mask_1_reg[] = 
-    {
-        {"pktrx_int_mask_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"pktrx_int_mask_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"pktrx_int_mask_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"pktrx_int_mask_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_int_status_reg[] = 
-    {
-        {"int_status", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_port_rdy0_reg[] = 
-    {
-        {"pktrx_trpgrx_r1_rdy", DPP_FIELD_FLAG_RO, 31, 10, 0x3ff, 0x0},
-        {"pktrx_trpgrx_r2_rdy", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy0_reg[] = 
-    {
-        {"pktrx_trpgrx_r1_pfc_rdy_0", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy1_reg[] = 
-    {
-        {"pktrx_trpgrx_r1_pfc_rdy_1", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy2_reg[] = 
-    {
-        {"pktrx_trpgrx_r1_pfc_rdy_2", DPP_FIELD_FLAG_RO, 31, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy3_reg[] = 
-    {
-        {"pktrx_trpgrx_r2_pfc_rdy_3", DPP_FIELD_FLAG_RO, 31, 8, 0xf, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy4_reg[] = 
-    {
-        {"pktrx_trpgrx_r2_pfc_rdy_4", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy5_reg[] = 
-    {
-        {"pktrx_trpgrx_r2_pfc_rdy_5", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy6_reg[] = 
-    {
-        {"pktrx_trpgrx_r2_pfc_rdy_6", DPP_FIELD_FLAG_RO, 31, 24, 0xffffff, 0x0},
-    };
-DPP_FIELD_T g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_reg[] = 
-    {
-        {"cfg_port_l2_offset_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_idma_cfg_int_ram_en_reg[] = 
-    {
-        {"phy_sts_parity_err", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"ptr_buf_parity_err", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_idma_cfg_int_ram_mask_reg[] = 
-    {
-        {"phy_sts_parity_err", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"ptr_buf_parity_err", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_idma_cfg_int_ram_status_reg[] = 
-    {
-        {"phy_sts_parity_err", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"ptr_buf_parity_err", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_idma_cfg_subsys_int_mask_flag_reg[] = 
-    {
-        {"subsys_int_mask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_idma_cfg_subsys_int_unmask_flag_reg[] = 
-    {
-        {"subsys_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_idma_cfg_debug_cnt_rdclr_mode_reg[] = 
-    {
-        {"debug_cnt_rdclr_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_int_ram_en0_reg[] = 
-    {
-        {"int_ram_en_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"int_ram_en_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"int_ram_en_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"int_ram_en_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"int_ram_en_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"int_ram_en_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"int_ram_en_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"int_ram_en_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"int_ram_en_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"int_ram_en_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"int_ram_en_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"int_ram_en_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"int_ram_en_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"int_ram_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"int_ram_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"int_ram_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"int_ram_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"int_ram_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"int_ram_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"int_ram_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"int_ram_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"int_ram_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"int_ram_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"int_ram_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"int_ram_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"int_ram_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"int_ram_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"int_ram_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"int_ram_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"int_ram_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"int_ram_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"int_ram_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_int_ram_mask0_reg[] = 
-    {
-        {"int_ram_mask_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"int_ram_mask_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"int_ram_mask_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"int_ram_mask_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"int_ram_mask_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"int_ram_mask_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"int_ram_mask_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"int_ram_mask_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"int_ram_mask_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"int_ram_mask_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"int_ram_mask_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"int_ram_mask_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"int_ram_mask_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"int_ram_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"int_ram_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"int_ram_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"int_ram_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"int_ram_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"int_ram_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"int_ram_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"int_ram_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"int_ram_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"int_ram_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"int_ram_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"int_ram_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"int_ram_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"int_ram_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"int_ram_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"int_ram_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"int_ram_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"int_ram_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"int_ram_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_int_ram_status0_reg[] = 
-    {
-        {"int_ram_status_31", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0},
-        {"int_ram_status_30", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0},
-        {"int_ram_status_29", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0},
-        {"int_ram_status_28", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0},
-        {"int_ram_status_27", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0},
-        {"int_ram_status_26", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0},
-        {"int_ram_status_25", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0},
-        {"int_ram_status_24", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0},
-        {"int_ram_status_23", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0},
-        {"int_ram_status_22", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0},
-        {"int_ram_status_21", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0},
-        {"int_ram_status_20", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0},
-        {"int_ram_status_19", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0},
-        {"int_ram_status_18", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0},
-        {"int_ram_status_17", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0},
-        {"int_ram_status_16", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0},
-        {"int_ram_status_15", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0},
-        {"int_ram_status_14", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0},
-        {"int_ram_status_13", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0},
-        {"int_ram_status_12", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0},
-        {"int_ram_status_11", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0},
-        {"int_ram_status_10", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0},
-        {"int_ram_status_9", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0},
-        {"int_ram_status_8", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0},
-        {"int_ram_status_7", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"int_ram_status_6", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"int_ram_status_5", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"int_ram_status_4", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"int_ram_status_3", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"int_ram_status_2", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"int_ram_status_1", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"int_ram_status_0", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_en0_reg[] = 
-    {
-        {"int_fifo_en_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"int_fifo_en_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"int_fifo_en_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"int_fifo_en_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"int_fifo_en_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"int_fifo_en_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"int_fifo_en_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"int_fifo_en_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"int_fifo_en_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"int_fifo_en_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"int_fifo_en_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"int_fifo_en_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"int_fifo_en_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"int_fifo_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"int_fifo_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"int_fifo_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"int_fifo_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"int_fifo_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"int_fifo_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"int_fifo_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"int_fifo_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"int_fifo_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"int_fifo_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"int_fifo_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"int_fifo_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"int_fifo_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"int_fifo_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"int_fifo_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"int_fifo_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"int_fifo_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"int_fifo_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"int_fifo_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_en1_reg[] = 
-    {
-        {"int_fifo_en_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"int_fifo_en_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"int_fifo_en_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"int_fifo_en_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_mask0_reg[] = 
-    {
-        {"int_fifo_mask_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"int_fifo_mask_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"int_fifo_mask_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"int_fifo_mask_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"int_fifo_mask_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"int_fifo_mask_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"int_fifo_mask_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"int_fifo_mask_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"int_fifo_mask_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"int_fifo_mask_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"int_fifo_mask_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"int_fifo_mask_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"int_fifo_mask_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"int_fifo_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"int_fifo_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"int_fifo_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"int_fifo_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"int_fifo_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"int_fifo_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"int_fifo_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"int_fifo_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"int_fifo_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"int_fifo_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"int_fifo_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"int_fifo_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"int_fifo_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"int_fifo_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"int_fifo_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"int_fifo_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"int_fifo_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"int_fifo_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"int_fifo_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_mask1_reg[] = 
-    {
-        {"int_fifo_mask_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"int_fifo_mask_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"int_fifo_mask_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"int_fifo_mask_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_status0_reg[] = 
-    {
-        {"int_fifo_status_31", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0},
-        {"int_fifo_status_30", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0},
-        {"int_fifo_status_29", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0},
-        {"int_fifo_status_28", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0},
-        {"int_fifo_status_27", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0},
-        {"int_fifo_status_26", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0},
-        {"int_fifo_status_25", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0},
-        {"int_fifo_status_24", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0},
-        {"int_fifo_status_23", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0},
-        {"int_fifo_status_22", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0},
-        {"int_fifo_status_21", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0},
-        {"int_fifo_status_20", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0},
-        {"int_fifo_status_19", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0},
-        {"int_fifo_status_18", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0},
-        {"int_fifo_status_17", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0},
-        {"int_fifo_status_16", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0},
-        {"int_fifo_status_15", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0},
-        {"int_fifo_status_14", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0},
-        {"int_fifo_status_13", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0},
-        {"int_fifo_status_12", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0},
-        {"int_fifo_status_11", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0},
-        {"int_fifo_status_10", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0},
-        {"int_fifo_status_9", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0},
-        {"int_fifo_status_8", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0},
-        {"int_fifo_status_7", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"int_fifo_status_6", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"int_fifo_status_5", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"int_fifo_status_4", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"int_fifo_status_3", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"int_fifo_status_2", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"int_fifo_status_1", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"int_fifo_status_0", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_status1_reg[] = 
-    {
-        {"int_fifo_status_35", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"int_fifo_status_34", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"int_fifo_status_33", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"int_fifo_status_32", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_subsys_int_mask_flag_reg[] = 
-    {
-        {"subsys_int_mask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_subsys_int_unmask_flag_reg[] = 
-    {
-        {"subsys_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_sa_ip_en_reg[] = 
-    {
-        {"sa_ip_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_debug_cnt_rdclr_mode_reg[] = 
-    {
-        {"debug_cnt_rdclr_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_fptr_fifo_aful_assert_cfg_reg[] = 
-    {
-        {"fptr_fifo_aful_assert_cfg", DPP_FIELD_FLAG_RW, 12, 13, 0xff0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_fptr_fifo_aful_negate_cfg_reg[] = 
-    {
-        {"fptr_fifo_aful_negate_cfg", DPP_FIELD_FLAG_RW, 12, 13, 0xff0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_pf_fifo_aful_assert_cfg_reg[] = 
-    {
-        {"pf_fifo_aful_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x8, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_pf_fifo_aful_negate_cfg_reg[] = 
-    {
-        {"pf_fifo_aful_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x8, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_pf_fifo_aept_assert_cfg_reg[] = 
-    {
-        {"pf_fifo_aept_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_pf_fifo_aept_negate_cfg_reg[] = 
-    {
-        {"pf_fifo_aept_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_wb_aful_assert_cfg_reg[] = 
-    {
-        {"wb_aful_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x12, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_wb_aful_negate_cfg_reg[] = 
-    {
-        {"wb_aful_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x12, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_se_key_aful_assert_cfg_reg[] = 
-    {
-        {"se_key_aful_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_se_aful_assert_cfg_reg[] = 
-    {
-        {"ifbrd_se_aful_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_se_aful_negate_cfg_reg[] = 
-    {
-        {"ifbrd_se_aful_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_odma_aful_assert_cfg_reg[] = 
-    {
-        {"ifbrd_odma_aful_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_odma_aful_negate_cfg_reg[] = 
-    {
-        {"ifbrd_odma_aful_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_ppu_aful_assert_cfg_reg[] = 
-    {
-        {"ifbrd_ppu_aful_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_ppu_aful_negate_cfg_reg[] = 
-    {
-        {"ifbrd_ppu_aful_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_mc_logic_aful_assert_cfg_reg[] = 
-    {
-        {"mc_logic_aful_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_mc_logic_aful_negate_cfg_reg[] = 
-    {
-        {"mc_logic_aful_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_mc_logic_diff_reg[] = 
-    {
-        {"mc_logic_diff", DPP_FIELD_FLAG_RW, 7, 8, 0xa, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_cfg_peak_port_cnt_clr_reg[] = 
-    {
-        {"cfg_peak_port_cnt_clr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_crdt_th_reg[] = 
-    {
-        {"ftm_crdt_port_cng_th", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0},
-        {"ftm_crdt_port_th", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_link_th_01_reg[] = 
-    {
-        {"total_congest_th1", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0},
-        {"total_congest_th0", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_link_th_23_reg[] = 
-    {
-        {"total_congest_th3", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0},
-        {"total_congest_th2", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_link_th_45_reg[] = 
-    {
-        {"total_congest_th5", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0},
-        {"total_congest_th4", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_link_th_6_reg[] = 
-    {
-        {"total_congest_th6", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_total_congest_th_reg[] = 
-    {
-        {"all_ftm_total_congest_th", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_cfg_crdt_mode_reg[] = 
-    {
-        {"cfg_crdt_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_cfg_pfc_rdy_high_time_reg[] = 
-    {
-        {"cfg_pfc_rdy_high_time", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_cfg_cfg_pfc_rdy_low_time_reg[] = 
-    {
-        {"cfg_pfc_rdy_low_time", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_pbu_fc_rdy_reg[] = 
-    {
-        {"pbu_oam_send_fc_rdy", DPP_FIELD_FLAG_RO, 7, 2, 0x0, 0x0},
-        {"pbu_odma_fc_rdy", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"pbu_tm_fc_rdy", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"pbu_idma_cos_rdy", DPP_FIELD_FLAG_RO, 1, 2, 0x2, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_pbu_lif_group0_rdy0_reg[] = 
-    {
-        {"pbu_ipg1_rdy", DPP_FIELD_FLAG_RO, 27, 3, 0x0, 0x0},
-        {"pbu_ipg0_rdy", DPP_FIELD_FLAG_RO, 24, 9, 0x0, 0x0},
-        {"pbu_trpgrx_xge_rdy", DPP_FIELD_FLAG_RO, 9, 2, 0x0, 0x0},
-        {"pbu_trpgrx_cge1_rdy", DPP_FIELD_FLAG_RO, 7, 4, 0x0, 0x0},
-        {"pbu_trpgrx_cge0_rdy", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_pbu_lif_group0_rdy1_reg[] = 
-    {
-        {"pbu_lif_group0_rdy1", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_pbu_lif_group1_rdy_reg[] = 
-    {
-        {"pbu_lif_group1_rdy1", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_pbu_lif_group0_pfc_rdy_reg[] = 
-    {
-        {"pbu_lif_group0_pfc_rdy", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_pbu_lif_group1_pfc_rdy_reg[] = 
-    {
-        {"pbu_lif_group1_pfc_rdy", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_pbu_sa_port_rdy_0_31_reg[] = 
-    {
-        {"pbu_sa_port_rdy_0_31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_pbu_sa_port_rdy_32_50_reg[] = 
-    {
-        {"pbu_sa_port_rdy_32_50", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_pbu_pktrx_mr_pfc_rdy_reg[] = 
-    {
-        {"pbu_pktrx_mr_pfc_rdy", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_0_31_reg[] = 
-    {
-        {"pbu_ftm_crdt_port_rdy_0_31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_32_47_reg[] = 
-    {
-        {"pbu_ftm_crdt_port_rdy_32_47", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_0_31_reg[] = 
-    {
-        {"pbu_ftm_crdt_port_cng_rdy_0_31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_32_47_reg[] = 
-    {
-        {"pbu_ftm_crdt_port_cng_rdy_32_47", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_pbu_stat_pbu_ftm_crdt_sys_info_reg[] = 
-    {
-        {"pbu_ftm_crdt_sys_info", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_weight_normal_mc_reg[] = 
-    {
-        {"weight_normal_mc", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_weight_sa_mc_reg[] = 
-    {
-        {"weight_sa_mc", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_weight_etm_reg[] = 
-    {
-        {"weight_etm", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_weight_lp_mc_reg[] = 
-    {
-        {"weight_lp_mc", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_weight_oam_reg[] = 
-    {
-        {"weight_oam", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_weight_lif_ctrl1_reg[] = 
-    {
-        {"weight_lif_ctrl1", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_weight_lif_ctrl2_reg[] = 
-    {
-        {"weight_lif_ctrl2", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_ecc_bypass_read_reg[] = 
-    {
-        {"eccbypass", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_isu_int_mask_reg[] = 
-    {
-        {"isu_int_mask", DPP_FIELD_FLAG_RW, 26, 27, 0x7ffffff, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_cfg_crdt_cycle_reg[] = 
-    {
-        {"cfg_cycle", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_cfg_crdt_value_reg[] = 
-    {
-        {"cfg_value", DPP_FIELD_FLAG_RW, 13, 14, 0x216, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_isu_int_en_reg[] = 
-    {
-        {"isu_int_en", DPP_FIELD_FLAG_RW, 26, 27, 0x7ffffff, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_isu_ppu_fifo_fc_reg[] = 
-    {
-        {"isu_ppu_fifo_fc", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_isu_int_status_reg[] = 
-    {
-        {"isu_int_status_26", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0},
-        {"isu_int_status_25", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0},
-        {"isu_int_status_24", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0},
-        {"isu_int_status_23", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0},
-        {"isu_int_status_22", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0},
-        {"isu_int_status_21", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0},
-        {"isu_int_status_20", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0},
-        {"isu_int_status_19", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0},
-        {"isu_int_status_18", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0},
-        {"isu_int_status_17", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0},
-        {"isu_int_status_16", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0},
-        {"isu_int_status_15", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0},
-        {"isu_int_status_14", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0},
-        {"isu_int_status_13", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0},
-        {"isu_int_status_12", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0},
-        {"isu_int_status_11", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0},
-        {"isu_int_status_10", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0},
-        {"isu_int_status_9", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0},
-        {"isu_int_status_8", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0},
-        {"isu_int_status_7", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"isu_int_status_6", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"isu_int_status_5", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"isu_int_status_4", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"isu_int_status_3", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"isu_int_status_2", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"isu_int_status_1", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"isu_int_status_0", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_fd_prog_full_assert_cfg_reg[] = 
-    {
-        {"fd_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_fd_prog_full_negate_cfg_reg[] = 
-    {
-        {"fd_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_lp_prog_full_assert_cfg_reg[] = 
-    {
-        {"lp_prog_ept_assert_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x80, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_cfg_lp_prog_full_negate_cfg_reg[] = 
-    {
-        {"lp_prog_ept_negate_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x80, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat0_reg[] = 
-    {
-        {"debug_cnt_dat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat1_reg[] = 
-    {
-        {"debug_cnt_dat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat2_reg[] = 
-    {
-        {"debug_cnt_dat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat3_reg[] = 
-    {
-        {"debug_cnt_dat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat4_reg[] = 
-    {
-        {"debug_cnt_dat4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat5_reg[] = 
-    {
-        {"debug_cnt_dat5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat6_reg[] = 
-    {
-        {"debug_cnt_dat6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat7_reg[] = 
-    {
-        {"debug_cnt_dat7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat8_reg[] = 
-    {
-        {"debug_cnt_dat8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat9_reg[] = 
-    {
-        {"debug_cnt_dat9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat10_reg[] = 
-    {
-        {"debug_cnt_dat10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat11_reg[] = 
-    {
-        {"debug_cnt_dat11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat12_reg[] = 
-    {
-        {"debug_cnt_dat12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat13_reg[] = 
-    {
-        {"debug_cnt_dat13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat14_reg[] = 
-    {
-        {"debug_cnt_dat14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat15_reg[] = 
-    {
-        {"debug_cnt_dat15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat16_reg[] = 
-    {
-        {"debug_cnt_dat16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat17_reg[] = 
-    {
-        {"debug_cnt_dat17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat18_reg[] = 
-    {
-        {"debug_cnt_dat18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat19_reg[] = 
-    {
-        {"debug_cnt_dat18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_isu_stat_debug_cnt_cfg_reg[] = 
-    {
-        {"debug_cnt_ovf_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"debug_cnt_rdclr_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0},
-        {"user_cnt_value", DPP_FIELD_FLAG_RW, 29, 4, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_exsa_tdm_offset_reg[] = 
-    {
-        {"exsa_tdm_offset", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_ecc_bypass_readt_reg[] = 
-    {
-        {"ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_odma_int_en_0_reg[] = 
-    {
-        {"odma_int_en_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"odma_int_en_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"odma_int_en_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"odma_int_en_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"odma_int_en_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"odma_int_en_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"odma_int_en_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"odma_int_en_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"odma_int_en_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"odma_int_en_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"odma_int_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_odma_int_en_1_reg[] = 
-    {
-        {"odma_int_en_63", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"odma_int_en_62", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"odma_int_en_61", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"odma_int_en_59", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"odma_int_en_58", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"odma_int_en_57", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"odma_int_en_56", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"odma_int_en_55", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"odma_int_en_54", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"odma_int_en_53", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"odma_int_en_52", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"odma_int_en_51", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"odma_int_en_49", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"odma_int_en_47", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"odma_int_en_45", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"odma_int_en_39", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"odma_int_en_38", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"odma_int_en_37", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"odma_int_en_36", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"odma_int_en_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"odma_int_en_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"odma_int_en_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"odma_int_en_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_odma_int_en_2_reg[] = 
-    {
-        {"odma_int_en_91", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"odma_int_en_88", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"odma_int_en_85", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"odma_int_en_82", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"odma_int_en_79", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"odma_int_en_75", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"odma_int_en_74", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"odma_int_en_71", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"odma_int_en_65", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"odma_int_en_64", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_odma_int_en_3_reg[] = 
-    {
-        {"odma_int_en_115", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"odma_int_en_114", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"odma_int_en_112", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"odma_int_en_110", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"odma_int_en_109", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"odma_int_en_108", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"odma_int_en_107", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"odma_int_en_106", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"odma_int_en_102", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"odma_int_en_101", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"odma_int_en_100", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"odma_int_en_98", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"odma_int_en_96", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_odma_int_mask_0_reg[] = 
-    {
-        {"odma_int_mask_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"odma_int_mask_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"odma_int_mask_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"odma_int_mask_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"odma_int_mask_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"odma_int_mask_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"odma_int_mask_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"odma_int_mask_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"odma_int_mask_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"odma_int_mask_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"odma_int_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_odma_int_mask_1_reg[] = 
-    {
-        {"odma_int_mask_63", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"odma_int_mask_62", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"odma_int_mask_61", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"odma_int_mask_59", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"odma_int_mask_58", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"odma_int_mask_57", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"odma_int_mask_56", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"odma_int_mask_55", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"odma_int_mask_54", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"odma_int_mask_53", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"odma_int_mask_52", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"odma_int_mask_51", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"odma_int_mask_50", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"odma_int_mask_49", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"odma_int_mask_47", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"odma_int_mask_45", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"odma_int_mask_39", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"odma_int_mask_38", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"odma_int_mask_37", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"odma_int_mask_36", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"odma_int_mask_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"odma_int_mask_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"odma_int_mask_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"odma_int_mask_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_odma_int_mask_2_reg[] = 
-    {
-        {"odma_int_mask_91", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"odma_int_mask_88", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"odma_int_mask_85", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"odma_int_mask_82", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"odma_int_mask_79", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"odma_int_mask_75", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"odma_int_mask_74", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"odma_int_mask_71", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"odma_int_mask_65", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"odma_int_mask_64", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_odma_int_mask_3_reg[] = 
-    {
-        {"odma_int_mask_115", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"odma_int_mask_114", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"odma_int_mask_112", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"odma_int_mask_110", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"odma_int_mask_109", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"odma_int_mask_108", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"odma_int_mask_107", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"odma_int_mask_106", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"odma_int_mask_102", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"odma_int_mask_101", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"odma_int_mask_100", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"odma_int_mask_98", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"odma_int_mask_96", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_odma_int_status_0_reg[] = 
-    {
-        {"odma_int_status_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"odma_int_status_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"odma_int_status_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"odma_int_status_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"odma_int_status_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"odma_int_status_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"odma_int_status_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"odma_int_status_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"odma_int_status_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"odma_int_status_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"odma_int_status_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_odma_int_status_1_reg[] = 
-    {
-        {"odma_int_status_63", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"odma_int_status_62", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"odma_int_status_61", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"odma_int_status_59", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"odma_int_status_58", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"odma_int_status_57", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"odma_int_status_56", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"odma_int_status_55", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"odma_int_status_54", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"odma_int_status_53", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"odma_int_status_52", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"odma_int_status_51", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"odma_int_status_49", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"odma_int_status_47", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"odma_int_status_45", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"odma_int_status_39", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"odma_int_status_38", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"odma_int_status_37", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"odma_int_status_36", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"odma_int_status_35", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"odma_int_status_34", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"odma_int_status_33", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"odma_int_status_32", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_odma_int_status_2_reg[] = 
-    {
-        {"odma_int_status_91", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"odma_int_status_88", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"odma_int_status_85", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"odma_int_status_82", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"odma_int_status_79", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"odma_int_status_75", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"odma_int_status_74", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"odma_int_status_71", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"odma_int_status_65", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"odma_int_status_64", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_odma_int_status_3_reg[] = 
-    {
-        {"odma_int_status_117", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"odma_int_status_116", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"odma_int_status_115", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"odma_int_status_114", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"odma_int_status_112", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"odma_int_status_110", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"odma_int_status_109", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"odma_int_status_108", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"odma_int_status_107", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"odma_int_status_106", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"odma_int_status_102", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"odma_int_status_101", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"odma_int_status_100", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"odma_int_status_98", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"odma_int_status_96", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_sp_tdm_err_nor_cfg_reg[] = 
-    {
-        {"sp_tdm_err_nor_cfg", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_a_reg[] = 
-    {
-        {"etm_dis_ptr_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_n_reg[] = 
-    {
-        {"etm_dis_ptr_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_a_reg[] = 
-    {
-        {"ftm_dis_ptr_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_n_reg[] = 
-    {
-        {"ftm_dis_ptr_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_a_reg[] = 
-    {
-        {"tm_dis_fifo_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_n_reg[] = 
-    {
-        {"tm_dis_fifo_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_err_prog_full_cfg_a_reg[] = 
-    {
-        {"err_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_err_prog_full_cfg_n_reg[] = 
-    {
-        {"err_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_tdmuc_prog_full_cfg_a_reg[] = 
-    {
-        {"tdmuc_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_tdmuc_prog_full_cfg_n_reg[] = 
-    {
-        {"tdmuc_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_a_reg[] = 
-    {
-        {"tdmmc_groupid_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_n_reg[] = 
-    {
-        {"tdmmc_groupid_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_a_reg[] = 
-    {
-        {"tdmmc_no_bitmap_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_n_reg[] = 
-    {
-        {"tdmmc_no_bitmap_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_tdmmc_prog_full_cfg_a_reg[] = 
-    {
-        {"tdmmc_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_tdmmc_prog_full_cfg_n_reg[] = 
-    {
-        {"tdmmc_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_desc_prog_full_cfg_a_reg[] = 
-    {
-        {"desc_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x64, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_desc_prog_full_cfg_n_reg[] = 
-    {
-        {"desc_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_dly_prog_full_cfg_a_reg[] = 
-    {
-        {"dly_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_dly_prog_full_cfg_n_reg[] = 
-    {
-        {"dly_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_rsp_prog_full_cfg_a_reg[] = 
-    {
-        {"rsp_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_rsp_prog_full_cfg_n_reg[] = 
-    {
-        {"rsp_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_nor_prog_full_cfg_a_reg[] = 
-    {
-        {"nor_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_nor_prog_full_cfg_n_reg[] = 
-    {
-        {"nor_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_etm_nor_prog_full_cfg_a_reg[] = 
-    {
-        {"etm_nor_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_etm_nor_prog_full_cfg_n_reg[] = 
-    {
-        {"etm_nor_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_ftm_nor_prog_full_cfg_a_reg[] = 
-    {
-        {"ftm_nor_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_ftm_nor_prog_full_cfg_n_reg[] = 
-    {
-        {"ftm_nor_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_etm_prog_full_cfg_a_reg[] = 
-    {
-        {"etm_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_etm_prog_full_cfg_n_reg[] = 
-    {
-        {"etm_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_ftm_prog_full_cfg_a_reg[] = 
-    {
-        {"ftm_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_ftm_prog_full_cfg_n_reg[] = 
-    {
-        {"ftm_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_a_reg[] = 
-    {
-        {"etm_nrdcnt_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_n_reg[] = 
-    {
-        {"etm_nrdcnt_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_a_reg[] = 
-    {
-        {"ftm_nrdcnt_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_n_reg[] = 
-    {
-        {"ftm_nrdcnt_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_pp_prog_full_cfg_a_reg[] = 
-    {
-        {"pp_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_pp_prog_full_cfg_n_reg[] = 
-    {
-        {"pp_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_tm_weight_reg[] = 
-    {
-        {"tm_weight", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_pp_weight_reg[] = 
-    {
-        {"pp_weight", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_ifbcmd_prog_full_cfg_a_reg[] = 
-    {
-        {"ifbcmd_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 6, 7, 0x32, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_ifbcmd_prog_full_cfg_n_reg[] = 
-    {
-        {"ifbcmd_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 6, 7, 0x32, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_mccnt_prog_full_cfg_a_reg[] = 
-    {
-        {"mccnt_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_mccnt_prog_full_cfg_n_reg[] = 
-    {
-        {"mccnt_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 5, 6, 0x19, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_int_or_pon_reg[] = 
-    {
-        {"int_or_pon", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_quemng_cnt_in_err_cnt_reg[] = 
-    {
-        {"quemng_cnt_in_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_lif0_port_eop_cnt_reg[] = 
-    {
-        {"lif0_port_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_lif1_port_eop_cnt_reg[] = 
-    {
-        {"lif1_port_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_lifc_port0_eop_cnt_reg[] = 
-    {
-        {"lifc_port0_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_lifc_port1_eop_cnt_reg[] = 
-    {
-        {"lifc_port1_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_fptr_fifo_prog_ept_cfg_n_reg[] = 
-    {
-        {"fptr_fifo_prog_ept_cfg_n", DPP_FIELD_FLAG_RW, 14, 15, 0x40, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_isu_fifo_prog_full_cfg_a_reg[] = 
-    {
-        {"isu_fifo_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x60, 0x0},
-    };
-DPP_FIELD_T g_nppu_odma_cfg_isu_fifo_prog_full_cfg_n_reg[] = 
-    {
-        {"isu_fifo_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x60, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_access_done_reg[] = 
-    {
-        {"ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_access_command_reg[] = 
-    {
-        {"ind_rd_or_wr", DPP_FIELD_FLAG_RW, 21, 1, 0x0, 0x0},
-        {"ind_mem_mask", DPP_FIELD_FLAG_RW, 20, 4, 0x0, 0x0},
-        {"ind_mem_id", DPP_FIELD_FLAG_RW, 16, 4, 0x0, 0x0},
-        {"ind_mem_addr", DPP_FIELD_FLAG_RW, 12, 13, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_dat0_reg[] = 
-    {
-        {"ind_dat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_dat1_reg[] = 
-    {
-        {"ind_dat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_dat2_reg[] = 
-    {
-        {"ind_dat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_dat3_reg[] = 
-    {
-        {"ind_dat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_oam_tx_main_en_reg[] = 
-    {
-        {"oam_tx_main_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_tx_total_num_reg[] = 
-    {
-        {"tx_total_num", DPP_FIELD_FLAG_RW, 12, 13, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_oam_chk_main_en_reg[] = 
-    {
-        {"oam_chk_main_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_chk_total_num0_reg[] = 
-    {
-        {"chk_total_num0", DPP_FIELD_FLAG_RW, 12, 13, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ma_chk_main_en_reg[] = 
-    {
-        {"oam_chk_main_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_chk_total_num1_reg[] = 
-    {
-        {"chk_total_num0", DPP_FIELD_FLAG_RW, 12, 13, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_tx_stat_en_reg[] = 
-    {
-        {"tx_stat_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_rec_stat_en_reg[] = 
-    {
-        {"rec_stat_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_stat_oam_rdy_mask_reg[] = 
-    {
-        {"stat_oam_rdy_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_session_grading0_reg[] = 
-    {
-        {"session_grading0", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_session_grading1_reg[] = 
-    {
-        {"session_grading1", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_session_grading2_reg[] = 
-    {
-        {"session_grading2", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_session_grading3_reg[] = 
-    {
-        {"session_grading3", DPP_FIELD_FLAG_RW, 2, 3, 0x7, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_bfd_chk_haddr_reg[] = 
-    {
-        {"bfd_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ethccm_chk_haddr_reg[] = 
-    {
-        {"ethccm_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_tpbfd_chk_haddr_reg[] = 
-    {
-        {"tpbfd_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_tpoam_ccm_chk_haddr_reg[] = 
-    {
-        {"tpoam_ccm_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_bfd_tx_haddr_reg[] = 
-    {
-        {"bfd_tx_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ethccm_tx_haddr_reg[] = 
-    {
-        {"ethccm_tx_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_tpbfd_tx_haddr_reg[] = 
-    {
-        {"tpbfd_tx_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_tpoam_ccm_tx_haddr_reg[] = 
-    {
-        {"tpoam_ccm_tx_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ethccm_ma_chk_haddr_reg[] = 
-    {
-        {"ethccm_ma_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_tpccm_ma_chk_haddr_reg[] = 
-    {
-        {"tpccm_ma_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_groupnum_ram_clr_reg[] = 
-    {
-        {"groupnum_ram_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_index_ram0_clr_reg[] = 
-    {
-        {"index_ram0_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_index_ram1_clr_reg[] = 
-    {
-        {"index_ram1_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_rmep_ram_clr_reg[] = 
-    {
-        {"rmep_ram_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ma_ram_clr_reg[] = 
-    {
-        {"ma_ram_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ram_init_done_reg[] = 
-    {
-        {"ram_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_rec_bfd_debug_en_reg[] = 
-    {
-        {"rec_bfd_debug_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_oam_session_int_reg[] = 
-    {
-        {"tpma_int", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"ethma_int", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"bfd_int", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"ethoam_int", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"tpbfd_int", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"tpoam_int", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_pon_int_reg[] = 
-    {
-        {"fifo_int", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"pon_protect_int", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_oam_int_clr_reg[] = 
-    {
-        {"oam_int_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_type_int_clr0_reg[] = 
-    {
-        {"tpma_int_clr", DPP_FIELD_FLAG_WO, 5, 1, 0x0, 0x0},
-        {"ethma_int_clr", DPP_FIELD_FLAG_WO, 4, 1, 0x0, 0x0},
-        {"bfd_int_clr", DPP_FIELD_FLAG_WO, 3, 1, 0x0, 0x0},
-        {"ethoam_int_clr", DPP_FIELD_FLAG_WO, 2, 1, 0x0, 0x0},
-        {"tpbfd_int_clr", DPP_FIELD_FLAG_WO, 1, 1, 0x0, 0x0},
-        {"tpoam_int_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_type_int_clr1_reg[] = 
-    {
-        {"fifo_int_clr", DPP_FIELD_FLAG_WO, 1, 1, 0x0, 0x0},
-        {"pon_protect_int_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_interrupt_mask_reg[] = 
-    {
-        {"fifo_interrupt_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"pon_protect_interruptmask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"tpma_interrupt_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"ethma_interrupt_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"bfd_interrupt_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"ethoam_interrupt_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"tpbfd_interrupt_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"tpoam_interrupt_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_int0_index_reg[] = 
-    {
-        {"int0_index0", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_int1_index_reg[] = 
-    {
-        {"int1_index0", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_int0_index_region_reg[] = 
-    {
-        {"int0_index_region", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_int1_index_region_reg[] = 
-    {
-        {"int1_index_region", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_bdiinfo_fwft_fifo_th_reg[] = 
-    {
-        {"bdiinfo_fwft_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_recsec_fwft_fifo_th_reg[] = 
-    {
-        {"recsec_fwft_fifo_th", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_timing_chk_info0_fwft_fifo_th_reg[] = 
-    {
-        {"timing_chk_info0_fwft_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_recma_fwft_fifo_th_reg[] = 
-    {
-        {"recma_fwft_fifo_th", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_timing_chk_info1_fwft_fifo_th_reg[] = 
-    {
-        {"timing_chk_info1_fwft_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_oam_txinst_fifo_th_reg[] = 
-    {
-        {"oam_txinst_fifo_th", DPP_FIELD_FLAG_RW, 10, 11, 0x300, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_oam_rdinfo_fwft_fifo_th_reg[] = 
-    {
-        {"oam_rdinfo_fwft_fifo_th", DPP_FIELD_FLAG_RW, 9, 10, 0x180, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_lm_cnt_fwft_fifo_th_reg[] = 
-    {
-        {"lm_cnt_fwft_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_oam_pkt_fifo_th_reg[] = 
-    {
-        {"oam_pkt_fifo_th", DPP_FIELD_FLAG_RW, 9, 10, 0x180, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_reclm_stat_fifo_th_reg[] = 
-    {
-        {"reclm_stat_fifo_th", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_txlm_stat_fifo_th_reg[] = 
-    {
-        {"txlm_stat_fifo_th", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_oam_chk_fwft_fifo_th_reg[] = 
-    {
-        {"oam_chk_fwft_fifo_th", DPP_FIELD_FLAG_RW, 9, 10, 0x180, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_txoam_stat_fifo_th_reg[] = 
-    {
-        {"txoam_stat_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_recoam_stat_fifo_th_reg[] = 
-    {
-        {"recoam_stat_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_txpkt_data_fwft_fifo_th_reg[] = 
-    {
-        {"txpkt_data_fwft_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0xc0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_tstpkt_fwft_fifo_th_reg[] = 
-    {
-        {"tstpkt_fwft_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0x80, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_tst_txinst_fwft_fifo_th_reg[] = 
-    {
-        {"tst_txinst_fwft_fifo_th", DPP_FIELD_FLAG_RW, 4, 5, 0x8, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_tstrx_main_en_reg[] = 
-    {
-        {"tstrx_main_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_tsttx_cfg_para_tbl2_reg[] = 
-    {
-        {"ddr_self_test_tx_en", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0},
-        {"tm_self_test_tx_en", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0},
-        {"fast_aging_tx_en", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0},
-        {"timing_aging_tx_en", DPP_FIELD_FLAG_RW, 13, 1, 0x0, 0x0},
-        {"backgroud_flow_tx_en", DPP_FIELD_FLAG_RW, 12, 1, 0x0, 0x0},
-        {"tsttx_tx_en", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0},
-        {"tx_freq", DPP_FIELD_FLAG_RW, 10, 3, 0x1, 0x0},
-        {"tx_offset", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_tsttx_cfg_para_tbl1_reg[] = 
-    {
-        {"tx_count", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_tsttx_cfg_para_tbl0_reg[] = 
-    {
-        {"fast_tx_mode_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"tsttx_tx_head_len", DPP_FIELD_FLAG_RW, 30, 15, 0x0, 0x0},
-        {"tsttx_tx_interval", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_tstrx_cfg_para_reg[] = 
-    {
-        {"tstrx_session_num", DPP_FIELD_FLAG_RW, 16, 16, 0x0, 0x0},
-        {"tstrx_session_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_en_0_reg[] = 
-    {
-        {"fifo_status_int_en_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"fifo_status_int_en_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"fifo_status_int_en_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"fifo_status_int_en_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"fifo_status_int_en_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"fifo_status_int_en_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"fifo_status_int_en_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"fifo_status_int_en_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"fifo_status_int_en_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"fifo_status_int_en_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"fifo_status_int_en_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"fifo_status_int_en_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"fifo_status_int_en_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"fifo_status_int_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"fifo_status_int_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"fifo_status_int_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"fifo_status_int_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"fifo_status_int_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"fifo_status_int_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"fifo_status_int_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"fifo_status_int_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"fifo_status_int_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"fifo_status_int_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"fifo_status_int_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"fifo_status_int_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"fifo_status_int_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"fifo_status_int_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"fifo_status_int_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"fifo_status_int_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"fifo_status_int_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"fifo_status_int_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"fifo_status_int_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_en_1_reg[] = 
-    {
-        {"fifo_status_int_en_41", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"fifo_status_int_en_40", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"fifo_status_int_en_39", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"fifo_status_int_en_38", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"fifo_status_int_en_37", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"fifo_status_int_en_36", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"fifo_status_int_en_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"fifo_status_int_en_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"fifo_status_int_en_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"fifo_status_int_en_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_mask_0_reg[] = 
-    {
-        {"fifo_status_int_mask_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_mask_1_reg[] = 
-    {
-        {"fifo_status_int_mask_41", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_40", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_39", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_38", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_37", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_36", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"fifo_status_int_mask_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_status_reg[] = 
-    {
-        {"fifo_status_int_status", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_main_frequency_reg[] = 
-    {
-        {"main_frequency", DPP_FIELD_FLAG_RW, 9, 10, 0x258, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_oam_cfg_type_reg[] = 
-    {
-        {"oam_cfg_type", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_fst_swch_eth_head0_reg[] = 
-    {
-        {"fst_swch_eth_head", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_fst_swch_eth_head1_reg[] = 
-    {
-        {"fst_swch_eth_head1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_fst_swch_eth_head2_reg[] = 
-    {
-        {"fst_swch_eth_head2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_fst_swch_eth_head3_reg[] = 
-    {
-        {"fst_swch_eth_head3", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_oam_fs_txinst_fifo_th_reg[] = 
-    {
-        {"oam_fs_txinst_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0x1f4, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_oam_ma_fs_txinst_fifo_th_reg[] = 
-    {
-        {"oam_ma_fs_txinst_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0x1f4, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_pon_int_ram_clr_reg[] = 
-    {
-        {"pon_int_ram_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_pon_p_int_index_reg[] = 
-    {
-        {"pon_p_int_index", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_pon_protect_pkt_fifo_th_reg[] = 
-    {
-        {"pon_protect_pkt_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0x1f4, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_pon_laser_off_en_reg[] = 
-    {
-        {"pon_laser_off_en", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_pon_prtct_pkt_tx_en_reg[] = 
-    {
-        {"pon_prtct_pkt_tx_en", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_cfg_pon_master_reg[] = 
-    {
-        {"cfg_pon_master", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_level_mode_reg[] = 
-    {
-        {"level_mode", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_interrupt_en_reg[] = 
-    {
-        {"interrupt_en", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_pon_laser_on_en_reg[] = 
-    {
-        {"pon_laser_on_en", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ti_pon_sd_reg[] = 
-    {
-        {"ti_pon_sd", DPP_FIELD_FLAG_RW, 7, 8, 0x2, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ti_pon_los_reg[] = 
-    {
-        {"ti_pon_los", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_dat4_reg[] = 
-    {
-        {"ind_dat4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_dat5_reg[] = 
-    {
-        {"ind_dat5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_dat6_reg[] = 
-    {
-        {"ind_dat6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_dat7_reg[] = 
-    {
-        {"ind_dat7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_dat8_reg[] = 
-    {
-        {"ind_dat8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_dat9_reg[] = 
-    {
-        {"ind_dat9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_dat10_reg[] = 
-    {
-        {"ind_dat10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_dat11_reg[] = 
-    {
-        {"ind_dat11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_dat12_reg[] = 
-    {
-        {"ind_dat12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_dat13_reg[] = 
-    {
-        {"ind_dat13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_dat14_reg[] = 
-    {
-        {"ind_dat14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ind_dat15_reg[] = 
-    {
-        {"ind_dat15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_oam_2544_pkt_fifo_th_reg[] = 
-    {
-        {"oam_2544_pkt_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0xc0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_txinfo_ram_clr_reg[] = 
-    {
-        {"txinfo_ram_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_txinfo_ram_init_done_reg[] = 
-    {
-        {"txinfo_ram_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_status40_reg[] = 
-    {
-        {"fifo_status_int_status40", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_status41_reg[] = 
-    {
-        {"fifo_status_int_status41", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_oam_2544_fun_en_reg[] = 
-    {
-        {"oam_2544_fun_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_oam_2544_stat_clr_reg[] = 
-    {
-        {"oam_2544_stat_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_txdis_default_reg[] = 
-    {
-        {"txdis_default", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_txdis_default_en_reg[] = 
-    {
-        {"txdis_default_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_tpbfd_firstchk_th_reg[] = 
-    {
-        {"tpbfd_firstchk_th", DPP_FIELD_FLAG_RW, 18, 19, 0xc350, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_ethccm_firstchk_th_reg[] = 
-    {
-        {"ethccm_firstchk_th", DPP_FIELD_FLAG_RW, 18, 19, 0xc350, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_tpccm_firstchk_th_reg[] = 
-    {
-        {"tpccm_firstchk_th", DPP_FIELD_FLAG_RW, 18, 19, 0xc350, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_txstat_req_cnt_reg[] = 
-    {
-        {"txstat_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_chkstat_req_cnt_reg[] = 
-    {
-        {"chkstat_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_stat_oam_fc_cnt_reg[] = 
-    {
-        {"stat1_oam_fc_cnt", DPP_FIELD_FLAG_RC, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_bfdseq_req_cnt_reg[] = 
-    {
-        {"bfdseq_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_lmcnt_req_cnt_reg[] = 
-    {
-        {"lmcnt_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_stat_oam_lm_rsp_cnt_reg[] = 
-    {
-        {"stat2_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_stat_oam_lm_fc_cnt_reg[] = 
-    {
-        {"stat2_oam_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_se_req_cnt_reg[] = 
-    {
-        {"se_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_se_rsp_cnt_reg[] = 
-    {
-        {"se_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_se_oam_fc_cnt_reg[] = 
-    {
-        {"se_oam_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_oam_se_fc_cnt_reg[] = 
-    {
-        {"oam_se_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_oam_pktrx_sop_cnt_reg[] = 
-    {
-        {"oam_pktrx_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_oam_pktrx_eop_cnt_reg[] = 
-    {
-        {"oam_pktrx_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_pktrx_oam_fc_cnt_reg[] = 
-    {
-        {"pktrx_oam_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_pktrx_oam_tst_fc_cnt_reg[] = 
-    {
-        {"pktrx_oam_tst_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_odma_oam_sop_cnt_reg[] = 
-    {
-        {"odma_oam_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_odma_oam_eop_cnt_reg[] = 
-    {
-        {"odma_oam_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_oam_odma_fc_cnt_reg[] = 
-    {
-        {"oam_odma_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_rec_ma_pkt_illegal_cnt_reg[] = 
-    {
-        {"rec_ma_pkt_illegal_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_rec_rmep_pkt_illegal_cnt_reg[] = 
-    {
-        {"rec_rmep_pkt_illegal_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_rec_eth_ais_pkt_cnt_reg[] = 
-    {
-        {"rec_eth_ais_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_rec_tp_ais_pkt_cnt_reg[] = 
-    {
-        {"rec_tp_ais_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_rec_tp_csf_pkt_cnt_reg[] = 
-    {
-        {"rec_tp_csf_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_rec_eth_level_defect_cnt_reg[] = 
-    {
-        {"rec_eth_level_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_rec_eth_megid_defect_cnt_reg[] = 
-    {
-        {"rec_eth_megid_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_rec_eth_mepid_defect_cnt_reg[] = 
-    {
-        {"rec_eth_mepid_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_rec_eth_interval_defect_cnt_reg[] = 
-    {
-        {"rec_eth_interval_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_rec_sess_unenable_cnt_reg[] = 
-    {
-        {"rec_sess_unenable_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_oam_2544_rd_pkt_cnt_reg[] = 
-    {
-        {"oam_2544_rd_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_debug_cnt_clr_reg[] = 
-    {
-        {"debug_cnt_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_oam_pktrx_catch_data_reg[] = 
-    {
-        {"oam_pktrx_catch_data", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_odma_oam_catch_data_reg[] = 
-    {
-        {"odma_oam_catch_data", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_tst_session_tx_cnt_reg[] = 
-    {
-        {"tst_session_tx_cnt", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_tst_session_rx_cnt_reg[] = 
-    {
-        {"tst_session_rx_cnt", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_tstrx_lost_cnt_reg[] = 
-    {
-        {"tstrx_lost_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_bfdseq_wr_cnt_reg[] = 
-    {
-        {"bfdseq_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_bfdtime_wr_cnt_reg[] = 
-    {
-        {"bfdtime_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_lmcnt_wr_cnt_reg[] = 
-    {
-        {"lmcnt_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_oam_fs_pkt_cnt_reg[] = 
-    {
-        {"oam_fs_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_oam_ma_fs_pkt_cnt_reg[] = 
-    {
-        {"lmcnt_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_rec_tp_level_defect_cnt_reg[] = 
-    {
-        {"rec_tp_level_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_rec_tp_megid_defect_cnt_reg[] = 
-    {
-        {"rec_tp_megid_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_rec_tp_mepid_defect_cnt_reg[] = 
-    {
-        {"rec_tp_mepid_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_rec_tp_interval_defect_cnt_reg[] = 
-    {
-        {"rec_tp_interval_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_rd_reg_clear_mode_reg[] = 
-    {
-        {"rd_clear_mode_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_stat_rd_data_reg_clear_mode_reg[] = 
-    {
-        {"rd_data_reg_clear_mode_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_indir_oam_int_status_ram_0_reg[] = 
-    {
-        {"bfd_diag_value_bit4", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"bfd_diag_value_bit3", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"bfd_diag_value_bit2", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"bfd_diag_value_bit1", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"bfd_diag_value_bit0", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"dloc_int", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"drdi_int", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_indir_oam_int_status_ram1_reg[] = 
-    {
-        {"sticky_error_level_defect", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"sticky_error_megid_defect", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"sticky_error_mepid_defect", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"sticky_error_inter_defect", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"sticky_ais_defect", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"sticky_csf_defect", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"current_error_level_defect", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"current_error_megid_defect", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"current_error_mepid_defect", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"current_error_inter_defect", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"current_ais_defect", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"current_csf_defect", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_indir_tst_pkt_tx_para_ram_reg[] = 
-    {
-        {"ddr_self_test_tx_en", DPP_FIELD_FLAG_RW, 80, 1, 0x0, 0x0},
-        {"tm_self_test_tx_en", DPP_FIELD_FLAG_RW, 79, 1, 0x0, 0x0},
-        {"fast_aging_tx_en", DPP_FIELD_FLAG_RW, 78, 1, 0x0, 0x0},
-        {"timing_aging_tx_en", DPP_FIELD_FLAG_RW, 77, 1, 0x0, 0x0},
-        {"backgroud_flow_tx_en", DPP_FIELD_FLAG_RW, 76, 1, 0x0, 0x0},
-        {"tsttx_session_en", DPP_FIELD_FLAG_RW, 75, 1, 0x0, 0x0},
-        {"tx_freq", DPP_FIELD_FLAG_RW, 74, 3, 0x0, 0x0},
-        {"tx_offset", DPP_FIELD_FLAG_RW, 71, 8, 0x0, 0x0},
-        {"tx_count", DPP_FIELD_FLAG_RW, 63, 32, 0x0, 0x0},
-        {"fast_tx_mode_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"tsttx_pkthead_len", DPP_FIELD_FLAG_RW, 30, 15, 0x0, 0x0},
-        {"tsttx_interval", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_indir_groupnumram_reg[] = 
-    {
-        {"mep_down_num", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_indir_oam_tx_tbl_ram_reg[] = 
-    {
-        {"oam_tx_en", DPP_FIELD_FLAG_RW, 62, 1, 0x0, 0x0},
-        {"oam_tx_type", DPP_FIELD_FLAG_RW, 61, 4, 0x0, 0x0},
-        {"oam_fetch_len", DPP_FIELD_FLAG_RW, 57, 14, 0x0, 0x0},
-        {"bfd_seq_tx_en", DPP_FIELD_FLAG_RW, 43, 1, 0x0, 0x0},
-        {"tx_para", DPP_FIELD_FLAG_RW, 42, 7, 0x0, 0x0},
-        {"oam_tx_interval", DPP_FIELD_FLAG_RW, 35, 16, 0x0, 0x0},
-        {"hd_ena_flag", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0},
-        {"last_tx_time", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_indir_oam_chk_tbl_ram_reg[] = 
-    {
-        {"fast_switch_en", DPP_FIELD_FLAG_RW, 55, 1, 0x0, 0x0},
-        {"oam_chk_en", DPP_FIELD_FLAG_RW, 54, 1, 0x0, 0x0},
-        {"oam_chk_type", DPP_FIELD_FLAG_RW, 53, 4, 0x0, 0x0},
-        {"ccm_predel_flag", DPP_FIELD_FLAG_RW, 49, 1, 0x0, 0x0},
-        {"lm_chk_en", DPP_FIELD_FLAG_RW, 48, 1, 0x0, 0x0},
-        {"ccm_group_id", DPP_FIELD_FLAG_RW, 47, 12, 0x0, 0x0},
-        {"oam_chk_internal", DPP_FIELD_FLAG_RW, 35, 16, 0x0, 0x0},
-        {"fist_chk_flag", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0},
-        {"last_chk_time", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_indir_oam_ma_chk_tbl_ram_reg[] = 
-    {
-        {"ma_fast_switch_en", DPP_FIELD_FLAG_RW, 141, 1, 0x0, 0x0},
-        {"ma_chk_en", DPP_FIELD_FLAG_RW, 140, 1, 0x0, 0x0},
-        {"ma_type", DPP_FIELD_FLAG_RW, 139, 1, 0x0, 0x0},
-        {"error_level_defect_en", DPP_FIELD_FLAG_RW, 138, 1, 0x0, 0x0},
-        {"error_megid_defect_en", DPP_FIELD_FLAG_RW, 137, 1, 0x0, 0x0},
-        {"error_mepid_defect_en", DPP_FIELD_FLAG_RW, 136, 1, 0x0, 0x0},
-        {"error_inter_defect_en", DPP_FIELD_FLAG_RW, 135, 1, 0x0, 0x0},
-        {"ais_defect_en", DPP_FIELD_FLAG_RW, 134, 1, 0x0, 0x0},
-        {"csf_defect_en", DPP_FIELD_FLAG_RW, 133, 1, 0x0, 0x0},
-        {"error_level_defect_ccm", DPP_FIELD_FLAG_RW, 132, 3, 0x0, 0x0},
-        {"error_megid_defect_ccm", DPP_FIELD_FLAG_RW, 129, 3, 0x0, 0x0},
-        {"error_mepid_defect_ccm", DPP_FIELD_FLAG_RW, 126, 3, 0x0, 0x0},
-        {"error_inter_defect_ccm", DPP_FIELD_FLAG_RW, 123, 3, 0x0, 0x0},
-        {"ais_defect_ccm", DPP_FIELD_FLAG_RW, 120, 3, 0x0, 0x0},
-        {"csf_defect_ccm", DPP_FIELD_FLAG_RW, 117, 3, 0x0, 0x0},
-        {"ma_predel_en", DPP_FIELD_FLAG_RW, 114, 1, 0x0, 0x0},
-        {"error_level_defect_ts", DPP_FIELD_FLAG_RO, 113, 19, 0x0, 0x0},
-        {"error_megid_defect_ts", DPP_FIELD_FLAG_RO, 94, 19, 0x0, 0x0},
-        {"error_mepid_defect_ts", DPP_FIELD_FLAG_RO, 75, 19, 0x0, 0x0},
-        {"error_inter_defect_ts", DPP_FIELD_FLAG_RO, 56, 19, 0x0, 0x0},
-        {"ais_defect_ts", DPP_FIELD_FLAG_RO, 37, 19, 0x0, 0x0},
-        {"csf_defect_ts", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_nppu_oam_cfg_indir_oam_2544_tx_ram_reg[] = 
-    {
-        {"tx_en_2544", DPP_FIELD_FLAG_RW, 46, 1, 0x0, 0x0},
-        {"tx_cfg_times_2544", DPP_FIELD_FLAG_RW, 45, 16, 0x0, 0x0},
-        {"current_times", DPP_FIELD_FLAG_RW, 29, 16, 0x0, 0x0},
-        {"slice_num", DPP_FIELD_FLAG_RW, 13, 7, 0x0, 0x0},
-        {"pkt_mty", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_interrupt_en_r_reg[] = 
-    {
-        {"interrupt_en_r", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_mec_host_interrupt_reg[] = 
-    {
-        {"mec_host_interrupt", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_dbg_rtl_date_reg[] = 
-    {
-        {"dbg_rtl_date", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_dup_start_num_cfg_reg[] = 
-    {
-        {"dup_start_num_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_debug_data_write_complete_reg[] = 
-    {
-        {"debug_data_write_complete", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_uc_mc_wrr_cfg_reg[] = 
-    {
-        {"uc_mc_wrr_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_debug_pkt_send_en_reg[] = 
-    {
-        {"debug_pkt_send_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_dup_tbl_ind_access_done_reg[] = 
-    {
-        {"dup_tbl_ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_ppu_demux_fifo_interrupt_mask_reg[] = 
-    {
-        {"isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"isu_in_fifo_64x81_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"isu_in_fifo_64x81_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_multicast_fifo_interrupt_mask_reg[] = 
-    {
-        {"ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"pf_req_fwft_fifo_16x36_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"pf_req_fwft_fifo_16x36_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"dup_para_fwft_fifo_16x35_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"dup_para_fwft_fifo_16x35_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"sa_para_fwft_fifo_64x17_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"sa_para_fwft_fifo_64x17_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"group_id_fifo_64x16_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"group_id_fifo_64x16_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"car_flag_fifo_32x1_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"car_flag_fifo_32x1_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_in_schedule_fifo_interrupt_mask_reg[] = 
-    {
-        {"free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"mc_mf_fifo_16x2048_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"mc_mf_fifo_16x2048_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"uc_mf_fifo_96x2048_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"uc_mf_fifo_96x2048_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_mf_out_fifo_interrupt_mask_reg[] = 
-    {
-        {"ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_mask_reg[] = 
-    {
-        {"ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_mask_reg[] = 
-    {
-        {"ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_mccnt_fifo_interrupt_mask_reg[] = 
-    {
-        {"ppu_mccnt_fifo_32x15_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"ppu_mccnt_fifo_32x15_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"mccnt_rsp_fifo_32x1_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"mccnt_rsp_fifo_32x1_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_mask_l_reg[] = 
-    {
-        {"mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_mask_m_reg[] = 
-    {
-        {"ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"ppu_cop_delay_fifo_48x16_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"ppu_cop_delay_fifo_48x16_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"ppu_cop_delay_fifo_16x48_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"ppu_cop_delay_fifo_16x48_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"ppu_cop_delay_fifo_16x32_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"ppu_cop_delay_fifo_16x32_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"ppu_cop_delay_fifo_16x16_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"ppu_cop_delay_fifo_16x16_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_mask_h_reg[] = 
-    {
-        {"coprocessor_fwft_fifo_16x80_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"coprocessor_fwft_fifo_16x80_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_ram_check_err_mask_reg[] = 
-    {
-        {"parity_err_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_fifo_interrupt_mask_reg[] = 
-    {
-        {"instrmem2_wr_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"instrmem2_wr_fifo_udf_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"instrmem2_rd_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"instrmem2_rd_fifo_udf_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"instrmem1_wr_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"instrmem1_wr_fifo_udf_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"instrmem1_rd_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"instrmem1_rd_fifo_udf_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"instrmem0_wr_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"instrmem0_wr_fifo_udf_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"instrmem0_rd_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"instrmem0_rd_fifo_udf_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_ppu_demux_fifo_interrupt_sta_reg[] = 
-    {
-        {"isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"isu_in_fifo_64x81_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"isu_in_fifo_64x81_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_multicast_fifo_interrupt_sta_reg[] = 
-    {
-        {"ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0},
-        {"ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0},
-        {"pf_req_fwft_fifo_16x36_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0},
-        {"pf_req_fwft_fifo_16x36_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0},
-        {"pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0},
-        {"pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0},
-        {"dup_para_fwft_fifo_16x35_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0},
-        {"dup_para_fwft_fifo_16x35_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0},
-        {"se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0},
-        {"se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0},
-        {"sa_para_fwft_fifo_64x17_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0},
-        {"sa_para_fwft_fifo_64x17_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0},
-        {"group_id_fifo_64x16_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"group_id_fifo_64x16_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"car_flag_fifo_32x1_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"car_flag_fifo_32x1_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_in_schedule_fifo_interrupt_sta_reg[] = 
-    {
-        {"free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"mc_mf_fifo_16x2048_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"mc_mf_fifo_16x2048_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"uc_mf_fifo_96x2048_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"uc_mf_fifo_96x2048_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_mf_out_fifo_interrupt_sta_reg[] = 
-    {
-        {"ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0},
-        {"ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0},
-        {"ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0},
-        {"ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0},
-        {"ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_sta_reg[] = 
-    {
-        {"ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0},
-        {"ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0},
-        {"ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0},
-        {"ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0},
-        {"ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_sta_reg[] = 
-    {
-        {"ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_mccnt_fifo_interrupt_sta_reg[] = 
-    {
-        {"ppu_mccnt_fifo_32x15_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"ppu_mccnt_fifo_32x15_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"mccnt_rsp_fifo_32x1_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"mccnt_rsp_fifo_32x1_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_sta_l_reg[] = 
-    {
-        {"mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0},
-        {"mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0},
-        {"mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0},
-        {"mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0},
-        {"mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0},
-        {"mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0},
-        {"mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0},
-        {"mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0},
-        {"mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0},
-        {"mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0},
-        {"mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0},
-        {"mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0},
-        {"mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0},
-        {"mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0},
-        {"mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0},
-        {"mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0},
-        {"mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0},
-        {"mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0},
-        {"mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0},
-        {"mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0},
-        {"mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0},
-        {"mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0},
-        {"mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0},
-        {"mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0},
-        {"mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_sta_m_reg[] = 
-    {
-        {"ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0},
-        {"ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0},
-        {"ppu_cop_delay_fifo_48x16_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0},
-        {"ppu_cop_delay_fifo_48x16_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0},
-        {"ppu_cop_delay_fifo_16x48_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0},
-        {"ppu_cop_delay_fifo_16x48_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0},
-        {"ppu_cop_delay_fifo_16x32_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0},
-        {"ppu_cop_delay_fifo_16x32_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0},
-        {"ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0},
-        {"ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0},
-        {"ppu_cop_delay_fifo_16x16_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0},
-        {"ppu_cop_delay_fifo_16x16_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0},
-        {"ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0},
-        {"ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0},
-        {"ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0},
-        {"ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0},
-        {"mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0},
-        {"mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0},
-        {"mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0},
-        {"mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0},
-        {"mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0},
-        {"mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0},
-        {"mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0},
-        {"mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0},
-        {"mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_sta_h_reg[] = 
-    {
-        {"ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_fifo_interrupt_sta_reg[] = 
-    {
-        {"instrmem1_wr_fifo_ovf_sta", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"instrmem1_wr_fifo_udf_sta", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"instrmem1_rd_fifo_ovf_sta", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"instrmem1_rd_fifo_udf_sta", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"instrmem0_wr_fifo_ovf_sta", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"instrmem0_wr_fifo_udf_sta", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"instrmem0_rd_fifo_ovf_sta", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"instrmem0_rd_fifo_udf_sta", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_ram_check_ecc_err_flag_1_reg[] = 
-    {
-        {"ecc_single_err_sa_para_fifo_int_flag", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ecc_double_err_sa_para_fifo_int_flag", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ecc_single_err_dup_para_fifo_int_flag", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ecc_double_err_dup_para_fifo_int_flag", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ecc_single_err_pf_rsp_fifo_int_flag", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ecc_double_err_pf_rsp_fifo_int_flag", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ecc_single_err_pf_req_fifo_int_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ecc_double_err_pf_req_fifo_int_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ecc_single_err_ppu_reorder_link_ram0_int_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ecc_double_err_ppu_reorder_link_ram0_int_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ecc_single_err_ppu_reorder_link_ram1_int_flag", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ecc_double_err_ppu_reorder_link_ram1_int_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ecc_single_err_ppu_reorder_link_flag_array_ram0_int_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ecc_single_err_ppu_reorder_link_flag_array_ram1_int_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ecc_single_err_ppu_reorder_ifb_ram_int_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ecc_double_err_ppu_reorder_ifb_ram_int_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ecc_single_err_ppu_reorder_flag_array_ram0_int_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ecc_single_err_ppu_reorder_flag_array_ram1_int_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ecc_single_err_ppu_reorder_flag_ram0_int_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ecc_single_err_ppu_reorder_flag_ram1_int_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ecc_single_err_uc_mf_fifo_int_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ecc_double_err_uc_mf_fifo_int_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ecc_single_err_mc_mf_fifo_int_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ecc_double_err_mc_mf_fifo_int_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ecc_single_err_free_global_num_fifo_int_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ecc_double_err_free_global_num_fifo_int_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_ppu_demux_fifo_interrupt_flag_reg[] = 
-    {
-        {"isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"isu_in_fifo_64x81_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"isu_in_fifo_64x81_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_multicast_fifo_interrupt_flag_reg[] = 
-    {
-        {"ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"pf_req_fwft_fifo_16x36_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"pf_req_fwft_fifo_16x36_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0},
-        {"pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"dup_para_fwft_fifo_16x35_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"dup_para_fwft_fifo_16x35_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"sa_para_fwft_fifo_64x17_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"sa_para_fwft_fifo_64x17_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"group_id_fifo_64x16_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"group_id_fifo_64x16_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"car_flag_fifo_32x1_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"car_flag_fifo_32x1_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_in_schedule_fifo_interrupt_flag_reg[] = 
-    {
-        {"free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"mc_mf_fifo_16x2048_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"mc_mf_fifo_16x2048_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"uc_mf_fifo_96x2048_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"uc_mf_fifo_96x2048_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_mf_out_fifo_interrupt_flag_reg[] = 
-    {
-        {"ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_flag_reg[] = 
-    {
-        {"ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_flag_reg[] = 
-    {
-        {"ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_mccnt_fifo_interrupt_flag_reg[] = 
-    {
-        {"ppu_mccnt_fifo_32x15_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ppu_mccnt_fifo_32x15_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"mccnt_rsp_fifo_32x1_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"mccnt_rsp_fifo_32x1_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_flag_l_reg[] = 
-    {
-        {"mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_flag_m_reg[] = 
-    {
-        {"ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ppu_cop_delay_fifo_48x16_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ppu_cop_delay_fifo_48x16_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ppu_cop_delay_fifo_16x48_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ppu_cop_delay_fifo_16x48_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ppu_cop_delay_fifo_16x32_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ppu_cop_delay_fifo_16x32_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ppu_cop_delay_fifo_16x16_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ppu_cop_delay_fifo_16x16_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_flag_h_reg[] = 
-    {
-        {"ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_fifo_interrupt_flag_reg[] = 
-    {
-        {"instrmem2_wr_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"instrmem2_wr_fifo_udf_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"instrmem2_rd_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"instrmem2_rd_fifo_udf_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"instrmem1_wr_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"instrmem1_wr_fifo_udf_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"instrmem1_rd_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"instrmem1_rd_fifo_udf_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"instrmem0_wr_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"instrmem0_wr_fifo_udf_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"instrmem0_rd_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"instrmem0_rd_fifo_udf_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_ram_int_out_reg[] = 
-    {
-        {"instrmem2_bank3_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0},
-        {"instrmem2_bank2_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0},
-        {"instrmem2_bank1_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0},
-        {"instrmem2_bank0_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0},
-        {"instrmem1_bank3_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"instrmem1_bank2_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"instrmem1_bank1_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"instrmem1_bank0_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"instrmem0_bank3_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"instrmem0_bank2_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"instrmem0_bank1_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"instrmem0_bank0_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_ram_int_mask_reg[] = 
-    {
-        {"instrmem2_bank3_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"instrmem2_bank2_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"instrmem2_bank1_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"instrmem2_bank0_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"instrmem1_bank3_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"instrmem1_bank2_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"instrmem1_bank1_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"instrmem1_bank0_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"instrmem0_bank3_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"instrmem0_bank2_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"instrmem0_bank1_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"instrmem0_bank0_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_ram_int_stat_reg[] = 
-    {
-        {"instrmem2_bank3_ram_parity_errstat", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0},
-        {"instrmem2_bank2_ram_parity_errstat", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0},
-        {"instrmem2_bank1_ram_parity_errstat", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0},
-        {"instrmem2_bank0_ram_parity_errstat", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0},
-        {"instrmem1_bank3_ram_parity_errstat", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"instrmem1_bank2_ram_parity_errstat", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"instrmem1_bank1_ram_parity_errstat", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"instrmem1_bank0_ram_parity_errstat", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"instrmem0_bank3_ram_parity_errstat", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"instrmem0_bank2_ram_parity_errstat", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"instrmem0_bank1_ram_parity_errstat", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"instrmem0_bank0_ram_parity_errstat", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_ram_int_flag_reg[] = 
-    {
-        {"instrmem2_bank3_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"instrmem2_bank2_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"instrmem2_bank1_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"instrmem2_bank0_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"instrmem1_bank3_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"instrmem1_bank2_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"instrmem1_bank1_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"instrmem1_bank0_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"instrmem0_bank3_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"instrmem0_bank2_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"instrmem0_bank1_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"instrmem0_bank0_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_count_cfg_reg[] = 
-    {
-        {"ppu_count_overflow_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"ppu_count_rd_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_statics_cfg_reg[] = 
-    {
-        {"csr_statics_mc_type", DPP_FIELD_FLAG_RW, 24, 1, 0x0, 0x0},
-        {"csr_statics_bufnum", DPP_FIELD_FLAG_RW, 22, 7, 0x0, 0x0},
-        {"csr_statics_portnum1", DPP_FIELD_FLAG_RW, 15, 8, 0xc1, 0x0},
-        {"csr_statics_portnum0", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_statics_wb_cfg_reg[] = 
-    {
-        {"csr_statics_wb_halt_send_type", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"csr_statics_wb_mf_type", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"csr_statics_wb_halt_continue_end", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"csr_statics_wb_dup_flag", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"csr_statics_wb_last_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"csr_statics_wb_dis_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_wr_table_self_rsp_en_cfg_reg[] = 
-    {
-        {"wr_table_self_rsp_en_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_random_arbiter_8to1_cfg_reg[] = 
-    {
-        {"ppu_random_arbiter_8to1_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_reorder_bypass_flow_num_cfg_reg[] = 
-    {
-        {"ppu_reorder_bypass_flow_num_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_cos_meter_cfg_h_reg[] = 
-    {
-        {"cbs", DPP_FIELD_FLAG_RW, 22, 10, 0x3ff, 0x0},
-        {"pbs", DPP_FIELD_FLAG_RW, 12, 10, 0x3ff, 0x0},
-        {"green_action", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"yellow_action", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"red_action", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_cos_meter_cfg_l_reg[] = 
-    {
-        {"cir", DPP_FIELD_FLAG_RW, 20, 10, 0x24a, 0x0},
-        {"pir", DPP_FIELD_FLAG_RW, 10, 10, 0x24a, 0x0},
-        {"car_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_rdy_reg[] = 
-    {
-        {"instrmem_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_addr_reg[] = 
-    {
-        {"instrmem_operate", DPP_FIELD_FLAG_WO, 13, 1, 0x0, 0x0},
-        {"instrmem_addr", DPP_FIELD_FLAG_WO, 12, 13, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_ind_access_done_reg[] = 
-    {
-        {"instrmem_ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_instr0_data_l_reg[] = 
-    {
-        {"instrmem_instr0_data_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_instr0_data_h_reg[] = 
-    {
-        {"instrmem_instr0_data_h", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_instr1_data_l_reg[] = 
-    {
-        {"instrmem_instr1_data_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_instr1_data_h_reg[] = 
-    {
-        {"instrmem_instr1_data_h", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_instr2_data_l_reg[] = 
-    {
-        {"instrmem_instr2_data_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_instr2_data_h_reg[] = 
-    {
-        {"instrmem_instr2_data_h", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_instr3_data_l_reg[] = 
-    {
-        {"instrmem_instr3_data_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_instr3_data_h_reg[] = 
-    {
-        {"instrmem_instr3_data_h", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_read_instr0_data_l_reg[] = 
-    {
-        {"instrmem_read_instr0_data_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_read_instr0_data_h_reg[] = 
-    {
-        {"instrmem_read_instr0_data_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_read_instr1_data_l_reg[] = 
-    {
-        {"instrmem_read_instr1_data_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_read_instr1_data_h_reg[] = 
-    {
-        {"instrmem_read_instr1_data_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_read_instr2_data_l_reg[] = 
-    {
-        {"instrmem_read_instr2_data_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_read_instr2_data_h_reg[] = 
-    {
-        {"instrmem_read_instr2_data_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_read_instr3_data_l_reg[] = 
-    {
-        {"instrmem_read_instr3_data_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_instrmem_read_instr3_data_h_reg[] = 
-    {
-        {"instrmem_read_instr3_data_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_se_ppu_mc_srh_fc_cnt_h_reg[] = 
-    {
-        {"se_ppu_mc_srh_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_se_ppu_mc_srh_fc_cnt_l_reg[] = 
-    {
-        {"se_ppu_mc_srh_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_se_mc_srh_fc_cnt_h_reg[] = 
-    {
-        {"ppu_se_mc_srh_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_se_mc_srh_fc_cnt_l_reg[] = 
-    {
-        {"ppu_se_mc_srh_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_se_mc_srh_vld_cnt_h_reg[] = 
-    {
-        {"ppu_se_mc_srh_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_se_mc_srh_vld_cnt_l_reg[] = 
-    {
-        {"ppu_se_mc_srh_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_se_ppu_mc_srh_vld_cnt_h_reg[] = 
-    {
-        {"se_ppu_mc_srh_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_se_ppu_mc_srh_vld_cnt_l_reg[] = 
-    {
-        {"se_ppu_mc_srh_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_h_reg[] = 
-    {
-        {"pbu_ppu_logic_pf_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_l_reg[] = 
-    {
-        {"pbu_ppu_logic_pf_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_h_reg[] = 
-    {
-        {"ppu_pbu_logic_rsp_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_l_reg[] = 
-    {
-        {"ppu_pbu_logic_rsp_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_h_reg[] = 
-    {
-        {"ppu_pbu_logic_pf_req_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_l_reg[] = 
-    {
-        {"ppu_pbu_logic_pf_req_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_h_reg[] = 
-    {
-        {"pbu_ppu_logic_pf_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_l_reg[] = 
-    {
-        {"pbu_ppu_logic_pf_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_h_reg[] = 
-    {
-        {"pbu_ppu_ifb_rd_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_l_reg[] = 
-    {
-        {"pbu_ppu_ifb_rd_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_ppu_wb_fc_cnt_h_reg[] = 
-    {
-        {"pbu_ppu_wb_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_ppu_wb_fc_cnt_l_reg[] = 
-    {
-        {"pbu_ppu_wb_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_h_reg[] = 
-    {
-        {"ppu_pbu_mcode_pf_req_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_l_reg[] = 
-    {
-        {"ppu_pbu_mcode_pf_req_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_h_reg[] = 
-    {
-        {"pbu_ppu_mcode_pf_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_l_reg[] = 
-    {
-        {"pbu_ppu_mcode_pf_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_odma_ppu_para_fc_cnt_h_reg[] = 
-    {
-        {"odma_ppu_para_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_odma_ppu_para_fc_cnt_l_reg[] = 
-    {
-        {"odma_ppu_para_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_h_reg[] = 
-    {
-        {"odma_ppu_mccnt_wr_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_l_reg[] = 
-    {
-        {"odma_ppu_mccnt_wr_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_h_reg[] = 
-    {
-        {"ppu_odma_mccnt_wr_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_l_reg[] = 
-    {
-        {"ppu_odma_mccnt_wr_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_h_reg[] = 
-    {
-        {"odma_ppu_mccnt_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_l_reg[] = 
-    {
-        {"odma_ppu_mccnt_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pktrx_uc_fc_cnt_h_reg[] = 
-    {
-        {"ppu_pktrx_uc_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pktrx_uc_fc_cnt_l_reg[] = 
-    {
-        {"ppu_pktrx_uc_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_fc_cnt_h_reg[] = 
-    {
-        {"ppu_pktrx_mc_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_fc_cnt_l_reg[] = 
-    {
-        {"ppu_pktrx_mc_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pktrx_ppu_desc_vld_cnt_h_reg[] = 
-    {
-        {"pktrx_ppu_desc_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pktrx_ppu_desc_vld_cnt_l_reg[] = 
-    {
-        {"pktrx_ppu_desc_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_h_reg[] = 
-    {
-        {"ppu_pbu_ifb_req_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_l_reg[] = 
-    {
-        {"ppu_pbu_ifb_req_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_h_reg[] = 
-    {
-        {"pbu_ppu_ifb_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_l_reg[] = 
-    {
-        {"pbu_ppu_ifb_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pbu_wb_vld_cnt_h_reg[] = 
-    {
-        {"ppu_pbu_wb_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pbu_wb_vld_cnt_l_reg[] = 
-    {
-        {"ppu_pbu_wb_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_h_reg[] = 
-    {
-        {"pbu_ppu_reorder_para_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_l_reg[] = 
-    {
-        {"pbu_ppu_reorder_para_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_odma_para_vld_cnt_h_reg[] = 
-    {
-        {"ppu_odma_para_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_odma_para_vld_cnt_l_reg[] = 
-    {
-        {"ppu_odma_para_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_mc_vld_cnt_h_reg[] = 
-    {
-        {"statics_isu_ppu_mc_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_mc_vld_cnt_l_reg[] = 
-    {
-        {"statics_isu_ppu_mc_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_h_reg[] = 
-    {
-        {"statics_isu_ppu_mc_loop_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_l_reg[] = 
-    {
-        {"statics_isu_ppu_mc_loop_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_uc_vld_cnt_h_reg[] = 
-    {
-        {"statics_isu_ppu_uc_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_uc_vld_cnt_l_reg[] = 
-    {
-        {"statics_isu_ppu_uc_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_h_reg[] = 
-    {
-        {"statics_isu_ppu_uc_bufnumis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_l_reg[] = 
-    {
-        {"statics_isu_ppu_uc_bufnumis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_vld_cnt_h_reg[] = 
-    {
-        {"statics_demux_schedule_mc_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_vld_cnt_l_reg[] = 
-    {
-        {"statics_demux_schedule_mc_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_h_reg[] = 
-    {
-        {"statics_demux_schedule_mc_bufnumis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_l_reg[] = 
-    {
-        {"statics_demux_schedule_mc_bufnumis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_h_reg[] = 
-    {
-        {"statics_demux_schedule_mc_srcportis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_l_reg[] = 
-    {
-        {"statics_demux_schedule_mc_srcportis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_h_reg[] = 
-    {
-        {"statics_demux_schedule_mc_srcportis1_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_l_reg[] = 
-    {
-        {"statics_demux_schedule_mc_srcportis1_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_vld_cnt_h_reg[] = 
-    {
-        {"statics_demux_schedule_uc_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_vld_cnt_l_reg[] = 
-    {
-        {"statics_demux_schedule_uc_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_h_reg[] = 
-    {
-        {"statics_demux_schedule_uc_bufnumis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_l_reg[] = 
-    {
-        {"statics_demux_schedule_uc_bufnumis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_h_reg[] = 
-    {
-        {"statics_demux_schedule_uc_srcportis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_l_reg[] = 
-    {
-        {"statics_demux_schedule_uc_srcportis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_h_reg[] = 
-    {
-        {"statics_demux_schedule_uc_srcportis1_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_l_reg[] = 
-    {
-        {"statics_demux_schedule_uc_srcportis1_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_vld_cnt_h_reg[] = 
-    {
-        {"statics_ppu_wb_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_vld_cnt_l_reg[] = 
-    {
-        {"statics_ppu_wb_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_h_reg[] = 
-    {
-        {"statics_ppu_wb_bufnumis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_l_reg[] = 
-    {
-        {"statics_ppu_wb_bufnumis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_h_reg[] = 
-    {
-        {"statics_ppu_wb_srcportis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_l_reg[] = 
-    {
-        {"statics_ppu_wb_srcportis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_h_reg[] = 
-    {
-        {"statics_ppu_wb_srcportis1_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_l_reg[] = 
-    {
-        {"statics_ppu_wb_srcportis1_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_h_reg[] = 
-    {
-        {"statics_ppu_wb_halt_send_type_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_l_reg[] = 
-    {
-        {"statics_ppu_wb_halt_send_type_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_h_reg[] = 
-    {
-        {"statics_ppu_wb_mf_type_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_l_reg[] = 
-    {
-        {"statics_ppu_wb_mf_type_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_h_reg[] = 
-    {
-        {"statics_ppu_wb_halt_continue_end_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_l_reg[] = 
-    {
-        {"statics_ppu_wb_halt_continue_end_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_h_reg[] = 
-    {
-        {"statics_ppu_wb_dup_flag_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_l_reg[] = 
-    {
-        {"statics_ppu_wb_dup_flag_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_h_reg[] = 
-    {
-        {"statics_ppu_wb_last_flag_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_l_reg[] = 
-    {
-        {"statics_ppu_wb_last_flag_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_h_reg[] = 
-    {
-        {"statics_ppu_wb_dis_flag_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_l_reg[] = 
-    {
-        {"statics_ppu_wb_dis_flag_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h_reg[] = 
-    {
-        {"statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l_reg[] = 
-    {
-        {"statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_h_reg[] = 
-    {
-        {"statics_pbu_ppu_reorder_mf_type_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_l_reg[] = 
-    {
-        {"statics_pbu_ppu_reorder_mf_type_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h_reg[] = 
-    {
-        {"statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l_reg[] = 
-    {
-        {"statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_car_green_pkt_vld_cnt_h_reg[] = 
-    {
-        {"car_green_pkt_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_car_green_pkt_vld_cnt_l_reg[] = 
-    {
-        {"car_green_pkt_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_car_yellow_pkt_vld_cnt_h_reg[] = 
-    {
-        {"car_yellow_pkt_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_car_yellow_pkt_vld_cnt_l_reg[] = 
-    {
-        {"car_yellow_pkt_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_car_red_pkt_vld_cnt_h_reg[] = 
-    {
-        {"car_red_pkt_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_car_red_pkt_vld_cnt_l_reg[] = 
-    {
-        {"car_red_pkt_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_car_drop_pkt_vld_cnt_h_reg[] = 
-    {
-        {"car_drop_pkt_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_car_drop_pkt_vld_cnt_l_reg[] = 
-    {
-        {"car_drop_pkt_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_h_reg[] = 
-    {
-        {"ppu_pktrx_mc_ptr_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_l_reg[] = 
-    {
-        {"ppu_pktrx_mc_ptr_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_ppu_loopback_fc_cnt_h_reg[] = 
-    {
-        {"ppu_pktrx_mc_ptr_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_ppu_loopback_fc_cnt_l_reg[] = 
-    {
-        {"ppu_pktrx_mc_ptr_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_mccnt_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"mccnt_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_mccnt_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"mccnt_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_mccnt_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"mccnt_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_mccnt_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"mccnt_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_uc_mf_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"uc_mf_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x10, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_uc_mf_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"uc_mf_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x10, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_uc_mf_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"uc_mf_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_uc_mf_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"uc_mf_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_mc_mf_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"mc_mf_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_mc_mf_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"mc_mf_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_mc_mf_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"mc_mf_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_mc_mf_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"mc_mf_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_mf_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"isu_mf_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_mf_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"isu_mf_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_mf_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"isu_mf_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_mf_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"isu_mf_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_fwft_mf_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"isu_fwft_mf_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_fwft_mf_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"isu_fwft_mf_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_mc_para_mf_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"isu_mc_para_mf_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x50, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_mc_para_mf_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"isu_mc_para_mf_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x50, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"isu_mc_para_mf_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"isu_mc_para_mf_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_group_id_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"group_id_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x3c, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_group_id_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"group_id_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x3c, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_group_id_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"group_id_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_group_id_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"group_id_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_sa_para_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"sa_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x3c, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_sa_para_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"sa_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x3c, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_sa_para_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"sa_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_sa_para_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"sa_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_se_mc_rsp_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"se_mc_rsp_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0xa, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_se_mc_rsp_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"se_mc_rsp_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0xa, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_se_mc_rsp_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"se_mc_rsp_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_se_mc_rsp_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"se_mc_rsp_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_dup_para_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"dup_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_dup_para_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"dup_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_dup_para_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"dup_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_dup_para_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"dup_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pf_rsp_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"pf_rsp_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pf_rsp_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"pf_rsp_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pf_rsp_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"pf_rsp_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pf_rsp_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"pf_rsp_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_dup_freeptr_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"dup_freeptr_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x7c, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_dup_freeptr_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"dup_freeptr_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x7c, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_dup_freeptr_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"dup_freeptr_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x58, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_dup_freeptr_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"dup_freeptr_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x58, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pf_req_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"pf_req_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pf_req_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"pf_req_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pf_req_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"pf_req_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pf_req_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"pf_req_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_car_flag_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"car_flag_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_car_flag_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"car_flag_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_car_flag_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"car_flag_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_car_flag_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"car_flag_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_cluster_mf_out_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_cluster_mf_out_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_cluster_mf_out_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_cluster_mf_out_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_key_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_key_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_key_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_key_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_key_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_key_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_key_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_key_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_random_mod_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_random_mod_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_random_mod_result_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x28, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_random_mod_result_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x28, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_checksum_result_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_checksum_result_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_checksum_result_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_checksum_result_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_crc_first_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xe, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_crc_first_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xe, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_crc_bypass_delay_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xe, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_crc_bypass_delay_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xe, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_crc_bypass_delay_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_crc_bypass_delay_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_crc_second_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_crc_second_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x30, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x30, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_multiply_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_multiply_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_multiply_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_multiply_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_free_global_num_fwft_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"free_global_num_fwft_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 12, 13, 0xffc, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_free_global_num_fwft_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"free_global_num_fwft_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 12, 13, 0xffc, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_free_global_num_fwft_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"free_global_num_fwft_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 12, 13, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_free_global_num_fwft_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"free_global_num_fwft_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 12, 13, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 14, 15, 0x3ff6, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 14, 15, 0x3ff6, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 14, 15, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 14, 15, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data0_reg[] = 
-    {
-        {"pkt_data0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data1_reg[] = 
-    {
-        {"pkt_data1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data2_reg[] = 
-    {
-        {"pkt_data2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data3_reg[] = 
-    {
-        {"pkt_data3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data4_reg[] = 
-    {
-        {"pkt_data4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data5_reg[] = 
-    {
-        {"pkt_data5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data6_reg[] = 
-    {
-        {"pkt_data6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data7_reg[] = 
-    {
-        {"pkt_data7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data8_reg[] = 
-    {
-        {"pkt_data8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data9_reg[] = 
-    {
-        {"pkt_data9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data10_reg[] = 
-    {
-        {"pkt_data10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data11_reg[] = 
-    {
-        {"pkt_data11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data12_reg[] = 
-    {
-        {"pkt_data12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data13_reg[] = 
-    {
-        {"pkt_data13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data14_reg[] = 
-    {
-        {"pkt_data14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data15_reg[] = 
-    {
-        {"pkt_data15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data16_reg[] = 
-    {
-        {"pkt_data16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data17_reg[] = 
-    {
-        {"pkt_data17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data18_reg[] = 
-    {
-        {"pkt_data18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data19_reg[] = 
-    {
-        {"pkt_data19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data20_reg[] = 
-    {
-        {"pkt_data20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data21_reg[] = 
-    {
-        {"pkt_data21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data22_reg[] = 
-    {
-        {"pkt_data22", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data23_reg[] = 
-    {
-        {"pkt_data23", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data24_reg[] = 
-    {
-        {"pkt_data24", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data25_reg[] = 
-    {
-        {"pkt_data25", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data26_reg[] = 
-    {
-        {"pkt_data26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data27_reg[] = 
-    {
-        {"pkt_data27", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data28_reg[] = 
-    {
-        {"pkt_data28", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data29_reg[] = 
-    {
-        {"pkt_data29", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data30_reg[] = 
-    {
-        {"pkt_data30", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data31_reg[] = 
-    {
-        {"pkt_data31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data32_reg[] = 
-    {
-        {"pkt_data32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data33_reg[] = 
-    {
-        {"pkt_data33", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data34_reg[] = 
-    {
-        {"pkt_data34", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data35_reg[] = 
-    {
-        {"pkt_data35", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data36_reg[] = 
-    {
-        {"pkt_data36", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data37_reg[] = 
-    {
-        {"pkt_data37", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data38_reg[] = 
-    {
-        {"pkt_data38", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data39_reg[] = 
-    {
-        {"pkt_data39", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data40_reg[] = 
-    {
-        {"pkt_data40", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data41_reg[] = 
-    {
-        {"pkt_data41", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data42_reg[] = 
-    {
-        {"pkt_data42", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data43_reg[] = 
-    {
-        {"pkt_data43", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data44_reg[] = 
-    {
-        {"pkt_data44", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data45_reg[] = 
-    {
-        {"pkt_data45", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data46_reg[] = 
-    {
-        {"pkt_data46", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data47_reg[] = 
-    {
-        {"pkt_data47", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data48_reg[] = 
-    {
-        {"pkt_data48", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data49_reg[] = 
-    {
-        {"pkt_data49", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data50_reg[] = 
-    {
-        {"pkt_data50", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data51_reg[] = 
-    {
-        {"pkt_data51", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data52_reg[] = 
-    {
-        {"pkt_data52", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data53_reg[] = 
-    {
-        {"pkt_data53", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data54_reg[] = 
-    {
-        {"pkt_data54", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data55_reg[] = 
-    {
-        {"pkt_data55", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data56_reg[] = 
-    {
-        {"pkt_data56", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data57_reg[] = 
-    {
-        {"pkt_data57", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data58_reg[] = 
-    {
-        {"pkt_data58", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data59_reg[] = 
-    {
-        {"pkt_data59", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data60_reg[] = 
-    {
-        {"pkt_data60", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data61_reg[] = 
-    {
-        {"pkt_data61", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data62_reg[] = 
-    {
-        {"pkt_data62", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data63_reg[] = 
-    {
-        {"pkt_data63", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data64_reg[] = 
-    {
-        {"pkt_data64", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data65_reg[] = 
-    {
-        {"pkt_data65", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data66_reg[] = 
-    {
-        {"pkt_data66", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data67_reg[] = 
-    {
-        {"pkt_data67", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data68_reg[] = 
-    {
-        {"pkt_data68", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data69_reg[] = 
-    {
-        {"pkt_data69", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data70_reg[] = 
-    {
-        {"pkt_data70", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data71_reg[] = 
-    {
-        {"pkt_data71", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data72_reg[] = 
-    {
-        {"pkt_data72", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data73_reg[] = 
-    {
-        {"pkt_data73", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data74_reg[] = 
-    {
-        {"pkt_data74", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data75_reg[] = 
-    {
-        {"pkt_data75", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data76_reg[] = 
-    {
-        {"pkt_data76", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data77_reg[] = 
-    {
-        {"pkt_data77", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data78_reg[] = 
-    {
-        {"pkt_data78", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data79_reg[] = 
-    {
-        {"pkt_data79", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data80_reg[] = 
-    {
-        {"pkt_data80", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data81_reg[] = 
-    {
-        {"pkt_data81", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data82_reg[] = 
-    {
-        {"pkt_data82", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data83_reg[] = 
-    {
-        {"pkt_data83", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data84_reg[] = 
-    {
-        {"pkt_data84", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data85_reg[] = 
-    {
-        {"pkt_data85", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data86_reg[] = 
-    {
-        {"pkt_data86", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data87_reg[] = 
-    {
-        {"pkt_data87", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data88_reg[] = 
-    {
-        {"pkt_data88", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data89_reg[] = 
-    {
-        {"pkt_data89", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data90_reg[] = 
-    {
-        {"pkt_data90", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data91_reg[] = 
-    {
-        {"pkt_data91", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data92_reg[] = 
-    {
-        {"pkt_data92", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data93_reg[] = 
-    {
-        {"pkt_data93", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data94_reg[] = 
-    {
-        {"pkt_data94", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data95_reg[] = 
-    {
-        {"pkt_data95", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data96_reg[] = 
-    {
-        {"pkt_data96", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data97_reg[] = 
-    {
-        {"pkt_data97", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data98_reg[] = 
-    {
-        {"pkt_data98", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data99_reg[] = 
-    {
-        {"pkt_data99", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data100_reg[] = 
-    {
-        {"pkt_data100", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data101_reg[] = 
-    {
-        {"pkt_data101", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data102_reg[] = 
-    {
-        {"pkt_data102", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data103_reg[] = 
-    {
-        {"pkt_data103", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data104_reg[] = 
-    {
-        {"pkt_data104", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data105_reg[] = 
-    {
-        {"pkt_data105", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data106_reg[] = 
-    {
-        {"pkt_data106", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data107_reg[] = 
-    {
-        {"pkt_data107", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data108_reg[] = 
-    {
-        {"pkt_data108", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data109_reg[] = 
-    {
-        {"pkt_data109", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data110_reg[] = 
-    {
-        {"pkt_data110", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data111_reg[] = 
-    {
-        {"pkt_data111", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data112_reg[] = 
-    {
-        {"pkt_data112", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data113_reg[] = 
-    {
-        {"pkt_data113", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data114_reg[] = 
-    {
-        {"pkt_data114", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data115_reg[] = 
-    {
-        {"pkt_data115", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data116_reg[] = 
-    {
-        {"pkt_data116", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data117_reg[] = 
-    {
-        {"pkt_data117", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data118_reg[] = 
-    {
-        {"pkt_data118", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data119_reg[] = 
-    {
-        {"pkt_data119", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data120_reg[] = 
-    {
-        {"pkt_data120", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data121_reg[] = 
-    {
-        {"pkt_data121", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data122_reg[] = 
-    {
-        {"pkt_data122", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data123_reg[] = 
-    {
-        {"pkt_data123", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data124_reg[] = 
-    {
-        {"pkt_data124", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data125_reg[] = 
-    {
-        {"pkt_data125", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data126_reg[] = 
-    {
-        {"pkt_data126", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_pkt_data127_reg[] = 
-    {
-        {"pkt_data127", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr0_reg[] = 
-    {
-        {"spr0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr1_reg[] = 
-    {
-        {"spr1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr2_reg[] = 
-    {
-        {"spr2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr3_reg[] = 
-    {
-        {"spr3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr4_reg[] = 
-    {
-        {"spr4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr5_reg[] = 
-    {
-        {"spr5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr6_reg[] = 
-    {
-        {"spr6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr7_reg[] = 
-    {
-        {"spr7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr8_reg[] = 
-    {
-        {"spr8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr9_reg[] = 
-    {
-        {"spr9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr10_reg[] = 
-    {
-        {"spr10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr11_reg[] = 
-    {
-        {"spr11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr12_reg[] = 
-    {
-        {"spr12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr13_reg[] = 
-    {
-        {"spr13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr14_reg[] = 
-    {
-        {"spr14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr15_reg[] = 
-    {
-        {"spr15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr16_reg[] = 
-    {
-        {"spr16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr17_reg[] = 
-    {
-        {"spr17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr18_reg[] = 
-    {
-        {"spr18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr19_reg[] = 
-    {
-        {"spr19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr20_reg[] = 
-    {
-        {"spr20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr21_reg[] = 
-    {
-        {"spr21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr22_reg[] = 
-    {
-        {"spr22", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr23_reg[] = 
-    {
-        {"spr23", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr24_reg[] = 
-    {
-        {"spr24", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr25_reg[] = 
-    {
-        {"spr25", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr26_reg[] = 
-    {
-        {"spr26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr27_reg[] = 
-    {
-        {"spr27", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr28_reg[] = 
-    {
-        {"spr28", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr29_reg[] = 
-    {
-        {"spr29", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr30_reg[] = 
-    {
-        {"spr30", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_spr31_reg[] = 
-    {
-        {"spr31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp0_reg[] = 
-    {
-        {"rsp0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp1_reg[] = 
-    {
-        {"rsp1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp2_reg[] = 
-    {
-        {"rsp2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp3_reg[] = 
-    {
-        {"rsp3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp4_reg[] = 
-    {
-        {"rsp4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp5_reg[] = 
-    {
-        {"rsp5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp6_reg[] = 
-    {
-        {"rsp6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp7_reg[] = 
-    {
-        {"rsp7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp8_reg[] = 
-    {
-        {"rsp8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp9_reg[] = 
-    {
-        {"rsp9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp10_reg[] = 
-    {
-        {"rsp10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp11_reg[] = 
-    {
-        {"rsp11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp12_reg[] = 
-    {
-        {"rsp12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp13_reg[] = 
-    {
-        {"rsp13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp14_reg[] = 
-    {
-        {"rsp14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp15_reg[] = 
-    {
-        {"rsp15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp16_reg[] = 
-    {
-        {"rsp16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp17_reg[] = 
-    {
-        {"rsp17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp18_reg[] = 
-    {
-        {"rsp18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp19_reg[] = 
-    {
-        {"rsp19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp20_reg[] = 
-    {
-        {"rsp20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp21_reg[] = 
-    {
-        {"rsp21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp22_reg[] = 
-    {
-        {"rsp22", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp23_reg[] = 
-    {
-        {"rsp23", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp24_reg[] = 
-    {
-        {"rsp24", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp25_reg[] = 
-    {
-        {"rsp25", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp26_reg[] = 
-    {
-        {"rsp26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp27_reg[] = 
-    {
-        {"rsp27", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp28_reg[] = 
-    {
-        {"rsp28", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp29_reg[] = 
-    {
-        {"rsp29", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp30_reg[] = 
-    {
-        {"rsp30", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_rsp31_reg[] = 
-    {
-        {"rsp31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key0_reg[] = 
-    {
-        {"key0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key1_reg[] = 
-    {
-        {"key1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key2_reg[] = 
-    {
-        {"key2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key3_reg[] = 
-    {
-        {"key3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key4_reg[] = 
-    {
-        {"key4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key5_reg[] = 
-    {
-        {"key5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key6_reg[] = 
-    {
-        {"key6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key7_reg[] = 
-    {
-        {"key7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key8_reg[] = 
-    {
-        {"key8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key9_reg[] = 
-    {
-        {"key9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key10_reg[] = 
-    {
-        {"key10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key11_reg[] = 
-    {
-        {"key11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key12_reg[] = 
-    {
-        {"key12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key13_reg[] = 
-    {
-        {"key13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key14_reg[] = 
-    {
-        {"key14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key15_reg[] = 
-    {
-        {"key15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key16_reg[] = 
-    {
-        {"key16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key17_reg[] = 
-    {
-        {"key17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key18_reg[] = 
-    {
-        {"key18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_key19_reg[] = 
-    {
-        {"key19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_ppu_flag_reg[] = 
-    {
-        {"me_num", DPP_FIELD_FLAG_RO, 26, 3, 0x0, 0x0},
-        {"thread_num", DPP_FIELD_FLAG_RO, 19, 4, 0x0, 0x0},
-        {"flag", DPP_FIELD_FLAG_RO, 11, 12, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_int_1200m_flag_reg[] = 
-    {
-        {"me7_interrupt_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"me6_interrupt_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"me5_interrupt_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"me4_interrupt_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"me3_interrupt_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"me2_interrupt_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"me1_interrupt_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"me0_interrupt_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_bp_instr_l_reg[] = 
-    {
-        {"bp_instr_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_bp_instr_h_reg[] = 
-    {
-        {"bp_instr_h", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_bp_addr_reg[] = 
-    {
-        {"bp_addr", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_drr_reg[] = 
-    {
-        {"drr", DPP_FIELD_FLAG_RO, 4, 5, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_dsr_reg[] = 
-    {
-        {"dsr", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_dbg_rtl_date_reg[] = 
-    {
-        {"dbg_rtl_date", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_continue_reg[] = 
-    {
-        {"me_continue", DPP_FIELD_FLAG_WO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_step_reg[] = 
-    {
-        {"me_step", DPP_FIELD_FLAG_WO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_refresh_reg[] = 
-    {
-        {"me_refresh", DPP_FIELD_FLAG_WO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_drr_clr_reg[] = 
-    {
-        {"drr_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_busy_thresold_reg[] = 
-    {
-        {"me_busy_thresold", DPP_FIELD_FLAG_RW, 15, 16, 0x7fff, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_int_1200m_sta_reg[] = 
-    {
-        {"me7_interrupt_sta", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"me6_interrupt_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"me5_interrupt_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"me4_interrupt_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"me3_interrupt_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"me2_interrupt_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"me1_interrupt_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"me0_interrupt_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_int_1200m_me_fifo_mask_l_reg[] = 
-    {
-        {"me_free_pkt_q_overflow_mask", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"me_free_pkt_q_underflow_mask", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"me_free_thread_q_overflow_mask", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"me_free_thread_q_underflow_mask", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"me_pkt_in_overflow_mask", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"me_pkt_in_underflow_mask", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"me_rdy_q_overflow_mask", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"me_rdy_q_underflow_mask", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"me_pkt_out_q_overflow_mask", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"me_pkt_out_q_underflow_mask", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"me_continue_q_overflow_mask", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"me_continue_q_underflow_mask", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"me_esrh_q_overflow_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"me_esrh_q_underflow_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"me_isrh_q_overflow_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"me_isrh_q_underflow_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"me_cache_miss_q_overflow_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"me_cache_miss_q_underflow_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"me_base_q_u0_overflow_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"me_base_q_u0_underflow_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"me_base_q_u1_overflow_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"me_base_q_u1_underflow_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"me_base_q_u2_overflow_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"me_base_q_u2_underflow_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"me_base_q_u3_overflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"me_base_q_u3_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"me_reg_pc_q_overflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"me_reg_pc_q_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"me_branch_q_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"me_branch_q_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"me_pkt_base_q_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"me_pkt_base_q_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_int_1200m_me_fifo_mask_h_reg[] = 
-    {
-        {"me_except_refetch_pc_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"me_except_refetch_pc_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_fifo_interrupt_flag_l_reg[] = 
-    {
-        {"me_free_pkt_q_overflow_flag", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"me_free_pkt_q_underflow_flag", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"me_free_thread_q_overflow_flag", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"me_free_thread_q_underflow_flag", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"me_pkt_in_overflow_flag", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"me_pkt_in_underflow_flag", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"me_rdy_q_overflow_flag", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"me_rdy_q_underflow_flag", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"me_pkt_out_q_overflow_flag", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"me_pkt_out_q_underflow_flag", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"me_continue_q_overflow_flag", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"me_continue_q_underflow_flag", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"me_esrh_q_overflow_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"me_esrh_q_underflow_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"me_isrh_q_overflow_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"me_isrh_q_underflow_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"me_cache_miss_q_overflow_flag", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"me_cache_miss_q_underflow_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"me_base_q_u0_overflow_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"me_base_q_u0_underflow_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"me_base_q_u1_overflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"me_base_q_u1_underflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"me_base_q_u2_overflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"me_base_q_u2_underflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"me_base_q_u3_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"me_base_q_u3_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"me_reg_pc_q_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"me_reg_pc_q_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"me_branch_q_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"me_branch_q_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"me_pkt_base_q_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"me_pkt_base_q_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_fifo_interrupt_flag_h_reg[] = 
-    {
-        {"me_except_refetch_pc_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"me_except_refetch_pc_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_fifo_interrupt_sta_l_reg[] = 
-    {
-        {"me_free_pkt_q_overflow_sta", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0},
-        {"me_free_pkt_q_underflow_sta", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0},
-        {"me_free_thread_q_overflow_sta", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0},
-        {"me_free_thread_q_underflow_sta", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0},
-        {"me_pkt_in_overflow_sta", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0},
-        {"me_pkt_in_underflow_sta", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0},
-        {"me_rdy_q_overflow_sta", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0},
-        {"me_rdy_q_underflow_sta", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0},
-        {"me_pkt_out_q_overflow_sta", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0},
-        {"me_pkt_out_q_underflow_sta", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0},
-        {"me_continue_q_overflow_sta", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0},
-        {"me_continue_q_underflow_sta", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0},
-        {"me_esrh_q_overflow_sta", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0},
-        {"me_esrh_q_underflow_sta", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0},
-        {"me_isrh_q_overflow_sta", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0},
-        {"me_isrh_q_underflow_sta", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0},
-        {"me_cache_miss_q_overflow_sta", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0},
-        {"me_cache_miss_q_underflow_sta", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0},
-        {"me_base_q_u0_overflow_sta", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0},
-        {"me_base_q_u0_underflow_sta", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0},
-        {"me_base_q_u1_overflow_sta", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0},
-        {"me_base_q_u1_underflow_sta", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0},
-        {"me_base_q_u2_overflow_sta", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0},
-        {"me_base_q_u2_underflow_sta", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0},
-        {"me_base_q_u3_overflow_sta", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"me_base_q_u3_underflow_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"me_reg_pc_q_overflow_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"me_reg_pc_q_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"me_branch_q_overflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"me_branch_q_underflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"me_pkt_base_q_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"me_pkt_base_q_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_fifo_interrupt_sta_h_reg[] = 
-    {
-        {"me_except_refetch_pc_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"me_except_refetch_pc_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_mask_l_reg[] = 
-    {
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_mask", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_mask", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_mask", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_mask", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_mask", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_mask", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_mask", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_mask", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_mask", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_mask", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"ise_rsp_ram_free_ptr_u0_overflow_mask", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"ise_rsp_ram_free_ptr_u0_underflow_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"ppu_sta_rsp_afifo_64x79_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_mask_h_reg[] = 
-    {
-        {"ppu_se_key_afifo_32x54_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"ppu_se_key_afifo_32x665_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"ppu_sta_key_afifo_32x110_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"ese_rsp_ram_free_ptr_u0_overflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"ese_rsp_ram_free_ptr_u0_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_flag_l_reg[] = 
-    {
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_flag", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_flag", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_flag", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_flag", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ise_rsp_ram_free_ptr_u0_overflow_flag", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ise_rsp_ram_free_ptr_u0_underflow_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ppu_sta_rsp_afifo_64x79_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_flag_h_reg[] = 
-    {
-        {"ppu_se_key_afifo_32x54_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ppu_se_key_afifo_32x665_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ppu_sta_key_afifo_32x110_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ese_rsp_ram_free_ptr_u0_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ese_rsp_ram_free_ptr_u0_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_stat_l_reg[] = 
-    {
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_stat", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_stat", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_stat", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_stat", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_stat", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_stat", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_stat", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_stat", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_stat", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_stat", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_stat", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0},
-        {"ise_rsp_ram_free_ptr_u0_overflow_stat", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0},
-        {"ise_rsp_ram_free_ptr_u0_underflow_stat", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_stat", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_stat", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_stat", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_stat", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_stat", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_stat", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_stat", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_stat", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_stat", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_stat", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_stat", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_stat", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_stat", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_stat", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_stat", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_stat", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"ppu_sta_rsp_afifo_64x79_wrapper_underflow_stat", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_stat", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_stat_h_reg[] = 
-    {
-        {"ppu_se_key_afifo_32x54_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0},
-        {"ppu_se_key_afifo_32x665_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0},
-        {"ppu_sta_key_afifo_32x110_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0},
-        {"ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_stat", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0},
-        {"ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0},
-        {"ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_stat", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0},
-        {"ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0},
-        {"ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_stat", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0},
-        {"ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0},
-        {"ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_stat", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_stat", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0},
-        {"ese_rsp_ram_free_ptr_u0_overflow_stat", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"ese_rsp_ram_free_ptr_u0_underflow_stat", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_stat", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_stat", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_stat", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_stat", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_stat", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_stat", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_statics_wb_exception_cfg_reg[] = 
-    {
-        {"csr_statics_wb_exception_code5", DPP_FIELD_FLAG_RW, 22, 3, 0x7, 0x0},
-        {"csr_statics_wb_exception_code4", DPP_FIELD_FLAG_RW, 18, 3, 0x6, 0x0},
-        {"csr_statics_wb_exception_code3", DPP_FIELD_FLAG_RW, 14, 3, 0x5, 0x0},
-        {"csr_statics_wb_exception_code2", DPP_FIELD_FLAG_RW, 10, 3, 0x4, 0x0},
-        {"csr_statics_wb_exception_code1", DPP_FIELD_FLAG_RW, 6, 3, 0x3, 0x0},
-        {"csr_statics_wb_exception_code0", DPP_FIELD_FLAG_RW, 2, 3, 0x2, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_thread_switch_en_reg[] = 
-    {
-        {"thread_switch_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_is_me_not_idle_reg[] = 
-    {
-        {"me7_is_not_idle", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"me6_is_not_idle", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"me5_is_not_idle", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"me4_is_not_idle", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"me3_is_not_idle", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"me2_is_not_idle", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"me1_is_not_idle", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"me0_is_not_idle", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_cluster_mf_in_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_cluster_mf_in_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ese_rsp_afifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ese_rsp_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0xe, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ese_rsp_afifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ese_rsp_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0xe, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ise_rsp_afifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ise_rsp_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ise_rsp_afifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ise_rsp_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x6, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x6, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_sta_rsp_afifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"sta_rsp_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_sta_rsp_afifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"sta_rsp_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cop_rsp_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"cop_rsp_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x17, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cop_rsp_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"cop_rsp_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x17, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cop_rsp_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"cop_rsp_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cop_rsp_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"cop_rsp_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mcode_pf_rsp_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"mcode_pf_rsp_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mcode_pf_rsp_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"mcode_pf_rsp_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"mcode_pf_rsp_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"mcode_pf_rsp_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_ise_key_afifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_ise_key_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_ise_key_afifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_ise_key_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_ese_key_afifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_ese_key_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_ese_key_afifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_ese_key_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_sta_key_afifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_sta_key_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_sta_key_afifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_sta_key_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_int_600m_cluster_mex_fifo_mask_reg[] = 
-    {
-        {"ppu_se_key_afifo_32x54_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"ppu_se_key_afifo_32x665_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"ppu_sta_key_afifo_32x110_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"ppu_sta_rsp_afifo_64x79_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cluster_mex_fifo_600m_interrupt_flag_reg[] = 
-    {
-        {"ppu_se_key_afifo_32x54_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ppu_se_key_afifo_32x665_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ppu_sta_key_afifo_32x110_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ppu_sta_rsp_afifo_64x79_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cluster_mex_fifo_600m_interrupt_sta_reg[] = 
-    {
-        {"ppu_se_key_afifo_32x54_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"ppu_se_key_afifo_32x665_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"ppu_sta_key_afifo_32x110_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"ppu_sta_rsp_afifo_64x79_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mex_cnt_cfg_reg[] = 
-    {
-        {"csr_count_overflow_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"csr_count_rd_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_int_600m_cluster_mex_ram_ecc_error_interrupt_mask_reg[] = 
-    {
-        {"ppu_sta_key_ram_1r1w_32x110_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"ppu_se_key_afifo_32x665_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"ppu_se_key_afifo_32x54_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"ppu_sta_key_ram_1r1w_32x110_ecc_single_err_flag", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"ppu_se_key_afifo_32x665_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"ppu_se_key_afifo_32x54_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_flag_reg[] = 
-    {
-        {"ppu_sta_key_ram_1r1w_32x110_ecc_double_err_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ppu_se_key_afifo_32x665_ecc_double_err_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ppu_se_key_afifo_32x54_ecc_double_err_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ppu_sta_key_ram_1r1w_32x110_ecc_single_err_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ppu_se_key_afifo_32x665_ecc_single_err_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ppu_se_key_afifo_32x54_ecc_single_err_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_sta_reg[] = 
-    {
-        {"ppu_sta_key_ram_1r1w_32x110_ecc_double_err_stat", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"ppu_se_key_afifo_32x665_ecc_double_err_stat", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"ppu_se_key_afifo_32x54_ecc_double_err_stat", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"ppu_sta_key_ram_1r1w_32x110_ecc_single_err_stat", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"ppu_se_key_afifo_32x665_ecc_single_err_stat", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"ppu_se_key_afifo_32x54_ecc_single_err_stat", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ppu_cluster_mf_in_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ppu_cluster_mf_in_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ese_rsp_afifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ese_rsp_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x2c, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ese_rsp_afifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ese_rsp_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x2c, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ise_rsp_afifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"ise_rsp_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x29, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ise_rsp_afifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"ise_rsp_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x29, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_sta_rsp_afifo_prog_full_assert_cfg_reg[] = 
-    {
-        {"sta_rsp_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x27, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_sta_rsp_afifo_prog_full_negate_cfg_reg[] = 
-    {
-        {"sta_rsp_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x27, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_ise_key_afifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_ise_key_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_ise_key_afifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_ise_key_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_ese_key_afifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_ese_key_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_ese_key_afifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_ese_key_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_sta_key_afifo_prog_empty_assert_cfg_reg[] = 
-    {
-        {"ppu_sta_key_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_sta_key_afifo_prog_empty_negate_cfg_reg[] = 
-    {
-        {"ppu_sta_key_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_vld_cnt_h_reg[] = 
-    {
-        {"ppu_cluster_mf_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_vld_cnt_l_reg[] = 
-    {
-        {"ppu_cluster_mf_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cluster_ise_key_out_vld_cnt_reg[] = 
-    {
-        {"cluster_ise_key_out_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ise_cluster_rsp_in_vld_cnt_reg[] = 
-    {
-        {"ise_cluster_rsp_in_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cluster_ese_key_out_vld_cnt_reg[] = 
-    {
-        {"cluster_ese_key_out_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ese_cluster_rsp_in_vld_cnt_reg[] = 
-    {
-        {"ese_cluster_rsp_in_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cluster_stat_cmd_vld_cnt_reg[] = 
-    {
-        {"cluster_stat_cmd_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_stat_cluster_rsp_vld_cnt_reg[] = 
-    {
-        {"stat_cluster_rsp_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mex_debug_key_vld_cnt_reg[] = 
-    {
-        {"mex_debug_key_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ise_cluster_key_fc_cnt_reg[] = 
-    {
-        {"ise_cluster_key_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_ese_cluster_key_fc_cnt_reg[] = 
-    {
-        {"ese_cluster_key_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cluster_ise_rsp_fc_cnt_reg[] = 
-    {
-        {"cluster_ise_rsp_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cluster_ese_rsp_fc_cnt_reg[] = 
-    {
-        {"cluster_ese_rsp_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_stat_cluster_cmd_fc_cnt_reg[] = 
-    {
-        {"stat_cluster_cmd_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cluster_stat_rsp_fc_cnt_reg[] = 
-    {
-        {"cluster_stat_rsp_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cluster_ppu_mf_vld_cnt_l_reg[] = 
-    {
-        {"cluster_ppu_mf_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cluster_ppu_mf_vld_cnt_h_reg[] = 
-    {
-        {"cluster_ppu_mf_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cluster_cop_key_vld_cnt_l_reg[] = 
-    {
-        {"cluster_cop_key_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cluster_cop_key_vld_cnt_h_reg[] = 
-    {
-        {"cluster_cop_key_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cop_cluster_rsp_vld_cnt_l_reg[] = 
-    {
-        {"cop_cluster_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_cop_cluster_rsp_vld_cnt_h_reg[] = 
-    {
-        {"cop_cluster_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_sop_cnt_l_reg[] = 
-    {
-        {"mex_me_pkt_in_sop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_sop_cnt_h_reg[] = 
-    {
-        {"mex_me_pkt_in_sop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_eop_cnt_l_reg[] = 
-    {
-        {"mex_me_pkt_in_eop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_eop_cnt_h_reg[] = 
-    {
-        {"mex_me_pkt_in_eop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_vld_cnt_l_reg[] = 
-    {
-        {"mex_me_pkt_in_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_vld_cnt_h_reg[] = 
-    {
-        {"mex_me_pkt_in_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_sop_cnt_l_reg[] = 
-    {
-        {"me_mex_pkt_out_sop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_sop_cnt_h_reg[] = 
-    {
-        {"me_mex_pkt_out_sop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_eop_cnt_l_reg[] = 
-    {
-        {"me_mex_pkt_out_eop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_eop_cnt_h_reg[] = 
-    {
-        {"me_mex_pkt_out_eop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_vld_cnt_l_reg[] = 
-    {
-        {"me_mex_pkt_out_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_vld_cnt_h_reg[] = 
-    {
-        {"me_mex_pkt_out_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_sop_cnt_l_reg[] = 
-    {
-        {"me_mex_i_key_out_sop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_sop_cnt_h_reg[] = 
-    {
-        {"me_mex_i_key_out_sop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_eop_cnt_l_reg[] = 
-    {
-        {"me_mex_i_key_out_eop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_eop_cnt_h_reg[] = 
-    {
-        {"me_mex_i_key_out_eop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_vld_cnt_l_reg[] = 
-    {
-        {"me_mex_i_key_out_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_vld_cnt_h_reg[] = 
-    {
-        {"me_mex_i_key_out_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_sop_cnt_l_reg[] = 
-    {
-        {"me_mex_e_key_out_sop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_sop_cnt_h_reg[] = 
-    {
-        {"me_mex_e_key_out_sop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_eop_cnt_l_reg[] = 
-    {
-        {"me_mex_e_key_out_eop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_eop_cnt_h_reg[] = 
-    {
-        {"me_mex_e_key_out_eop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_vld_cnt_l_reg[] = 
-    {
-        {"me_mex_e_key_out_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_vld_cnt_h_reg[] = 
-    {
-        {"me_mex_e_key_out_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_demux_ise_key_vld_cnt_l_reg[] = 
-    {
-        {"me_mex_demux_ise_key_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_demux_ise_key_vld_cnt_h_reg[] = 
-    {
-        {"me_mex_demux_ise_key_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_demux_ese_key_vld_cnt_l_reg[] = 
-    {
-        {"me_mex_demux_ese_key_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_demux_ese_key_vld_cnt_h_reg[] = 
-    {
-        {"me_mex_demux_ese_key_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_demux_sta_key_vld_cnt_l_reg[] = 
-    {
-        {"me_mex_demux_sta_key_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_demux_sta_key_vld_cnt_h_reg[] = 
-    {
-        {"me_mex_demux_sta_key_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_demux_cop_key_vld_cnt_l_reg[] = 
-    {
-        {"me_mex_demux_cop_key_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_mex_demux_cop_key_vld_cnt_h_reg[] = 
-    {
-        {"me_mex_demux_cop_key_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_l_reg[] = 
-    {
-        {"mex_me_demux_ise_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_h_reg[] = 
-    {
-        {"mex_me_demux_ise_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_l_reg[] = 
-    {
-        {"mex_me_demux_ese_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_h_reg[] = 
-    {
-        {"mex_me_demux_ese_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_l_reg[] = 
-    {
-        {"mex_me_demux_sta_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_h_reg[] = 
-    {
-        {"mex_me_demux_sta_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_l_reg[] = 
-    {
-        {"mex_me_demux_cop_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_h_reg[] = 
-    {
-        {"mex_me_demux_cop_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_exception_code0_cnt_l_reg[] = 
-    {
-        {"me_exception_code0_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_exception_code0_cnt_h_reg[] = 
-    {
-        {"me_exception_code0_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_exception_code1_cnt_l_reg[] = 
-    {
-        {"me_exception_code1_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_exception_code1_cnt_h_reg[] = 
-    {
-        {"me_exception_code1_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_exception_code2_cnt_l_reg[] = 
-    {
-        {"me_exception_code2_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_exception_code2_cnt_h_reg[] = 
-    {
-        {"me_exception_code2_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_exception_code3_cnt_l_reg[] = 
-    {
-        {"me_exception_code3_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_exception_code3_cnt_h_reg[] = 
-    {
-        {"me_exception_code3_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_exception_code4_cnt_l_reg[] = 
-    {
-        {"me_exception_code4_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_exception_code4_cnt_h_reg[] = 
-    {
-        {"me_exception_code4_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_exception_code5_cnt_l_reg[] = 
-    {
-        {"me_exception_code5_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ppu_cluster_me_exception_code5_cnt_h_reg[] = 
-    {
-        {"me_exception_code5_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_ppu_soft_rst_reg[] = 
-    {
-        {"ppu_soft_rst", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_ept_flag_reg[] = 
-    {
-        {"ept_flag", DPP_FIELD_FLAG_RO, 5, 6, 0x3f, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_ddr_key_lk0_3_reg[] = 
-    {
-        {"ddr_key_lk0_3", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_ddr_key_lk0_2_reg[] = 
-    {
-        {"ddr_key_lk0_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_ddr_key_lk0_1_reg[] = 
-    {
-        {"ddr_key_lk0_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_ddr_key_lk0_0_reg[] = 
-    {
-        {"ddr_key_lk0_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_ddr_key_lk1_3_reg[] = 
-    {
-        {"ddr_key_lk1_3", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_ddr_key_lk1_2_reg[] = 
-    {
-        {"ddr_key_lk1_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_ddr_key_lk1_1_reg[] = 
-    {
-        {"ddr_key_lk1_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_ddr_key_lk1_0_reg[] = 
-    {
-        {"ddr_key_lk1_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_18_reg[] = 
-    {
-        {"hash_key_lk0_18", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_17_reg[] = 
-    {
-        {"hash_key_lk0_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_16_reg[] = 
-    {
-        {"hash_key_lk0_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_15_reg[] = 
-    {
-        {"hash_key_lk0_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_14_reg[] = 
-    {
-        {"hash_key_lk0_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_13_reg[] = 
-    {
-        {"hash_key_lk0_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_12_reg[] = 
-    {
-        {"hash_key_lk0_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_11_reg[] = 
-    {
-        {"hash_key_lk0_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_10_reg[] = 
-    {
-        {"hash_key_lk0_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_9_reg[] = 
-    {
-        {"hash_key_lk0_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_8_reg[] = 
-    {
-        {"hash_key_lk0_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_7_reg[] = 
-    {
-        {"hash_key_lk0_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_6_reg[] = 
-    {
-        {"hash_key_lk0_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_5_reg[] = 
-    {
-        {"hash_key_lk0_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_4_reg[] = 
-    {
-        {"hash_key_lk0_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_3_reg[] = 
-    {
-        {"hash_key_lk0_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_2_reg[] = 
-    {
-        {"hash_key_lk0_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_1_reg[] = 
-    {
-        {"hash_key_lk0_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk0_0_reg[] = 
-    {
-        {"hash_key_lk0_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_18_reg[] = 
-    {
-        {"hash_key_lk1_18", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_17_reg[] = 
-    {
-        {"hash_key_lk1_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_16_reg[] = 
-    {
-        {"hash_key_lk1_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_15_reg[] = 
-    {
-        {"hash_key_lk1_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_14_reg[] = 
-    {
-        {"hash_key_lk1_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_13_reg[] = 
-    {
-        {"hash_key_lk1_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_12_reg[] = 
-    {
-        {"hash_key_lk1_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_11_reg[] = 
-    {
-        {"hash_key_lk1_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_10_reg[] = 
-    {
-        {"hash_key_lk1_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_9_reg[] = 
-    {
-        {"hash_key_lk1_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_8_reg[] = 
-    {
-        {"hash_key_lk1_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_7_reg[] = 
-    {
-        {"hash_key_lk1_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_6_reg[] = 
-    {
-        {"hash_key_lk1_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_5_reg[] = 
-    {
-        {"hash_key_lk1_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_4_reg[] = 
-    {
-        {"hash_key_lk1_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_3_reg[] = 
-    {
-        {"hash_key_lk1_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_2_reg[] = 
-    {
-        {"hash_key_lk1_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_1_reg[] = 
-    {
-        {"hash_key_lk1_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk1_0_reg[] = 
-    {
-        {"hash_key_lk1_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_18_reg[] = 
-    {
-        {"hash_key_lk2_18", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_17_reg[] = 
-    {
-        {"hash_key_lk2_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_16_reg[] = 
-    {
-        {"hash_key_lk2_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_15_reg[] = 
-    {
-        {"hash_key_lk2_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_14_reg[] = 
-    {
-        {"hash_key_lk2_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_13_reg[] = 
-    {
-        {"hash_key_lk2_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_12_reg[] = 
-    {
-        {"hash_key_lk2_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_11_reg[] = 
-    {
-        {"hash_key_lk2_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_10_reg[] = 
-    {
-        {"hash_key_lk2_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_9_reg[] = 
-    {
-        {"hash_key_lk2_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_8_reg[] = 
-    {
-        {"hash_key_lk2_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_7_reg[] = 
-    {
-        {"hash_key_lk2_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_6_reg[] = 
-    {
-        {"hash_key_lk2_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_5_reg[] = 
-    {
-        {"hash_key_lk2_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_4_reg[] = 
-    {
-        {"hash_key_lk2_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_3_reg[] = 
-    {
-        {"hash_key_lk2_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_2_reg[] = 
-    {
-        {"hash_key_lk2_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_1_reg[] = 
-    {
-        {"hash_key_lk2_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk2_0_reg[] = 
-    {
-        {"hash_key_lk2_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_18_reg[] = 
-    {
-        {"hash_key_lk3_18", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_17_reg[] = 
-    {
-        {"hash_key_lk3_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_16_reg[] = 
-    {
-        {"hash_key_lk3_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_15_reg[] = 
-    {
-        {"hash_key_lk3_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_14_reg[] = 
-    {
-        {"hash_key_lk3_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_13_reg[] = 
-    {
-        {"hash_key_lk3_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_12_reg[] = 
-    {
-        {"hash_key_lk3_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_11_reg[] = 
-    {
-        {"hash_key_lk3_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_10_reg[] = 
-    {
-        {"hash_key_lk3_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_9_reg[] = 
-    {
-        {"hash_key_lk3_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_8_reg[] = 
-    {
-        {"hash_key_lk3_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_7_reg[] = 
-    {
-        {"hash_key_lk3_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_6_reg[] = 
-    {
-        {"hash_key_lk3_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_5_reg[] = 
-    {
-        {"hash_key_lk3_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_4_reg[] = 
-    {
-        {"hash_key_lk3_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_3_reg[] = 
-    {
-        {"hash_key_lk3_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_2_reg[] = 
-    {
-        {"hash_key_lk3_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_1_reg[] = 
-    {
-        {"hash_key_lk3_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_hash_key_lk3_0_reg[] = 
-    {
-        {"hash_key_lk3_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk0_6_reg[] = 
-    {
-        {"lpm_key_lk0_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk0_5_reg[] = 
-    {
-        {"lpm_key_lk0_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk0_4_reg[] = 
-    {
-        {"lpm_key_lk0_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk0_3_reg[] = 
-    {
-        {"lpm_key_lk0_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk0_2_reg[] = 
-    {
-        {"lpm_key_lk0_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk0_1_reg[] = 
-    {
-        {"lpm_key_lk0_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk0_0_reg[] = 
-    {
-        {"lpm_key_lk0_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk1_6_reg[] = 
-    {
-        {"lpm_key_lk1_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk1_5_reg[] = 
-    {
-        {"lpm_key_lk1_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk1_4_reg[] = 
-    {
-        {"lpm_key_lk1_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk1_3_reg[] = 
-    {
-        {"lpm_key_lk1_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk1_2_reg[] = 
-    {
-        {"lpm_key_lk1_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk1_1_reg[] = 
-    {
-        {"lpm_key_lk1_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk1_0_reg[] = 
-    {
-        {"lpm_key_lk1_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk2_6_reg[] = 
-    {
-        {"lpm_key_lk2_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk2_5_reg[] = 
-    {
-        {"lpm_key_lk2_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk2_4_reg[] = 
-    {
-        {"lpm_key_lk2_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk2_3_reg[] = 
-    {
-        {"lpm_key_lk2_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk2_2_reg[] = 
-    {
-        {"lpm_key_lk2_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk2_1_reg[] = 
-    {
-        {"lpm_key_lk2_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk2_0_reg[] = 
-    {
-        {"lpm_key_lk2_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk3_6_reg[] = 
-    {
-        {"lpm_key_lk3_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk3_5_reg[] = 
-    {
-        {"lpm_key_lk3_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk3_4_reg[] = 
-    {
-        {"lpm_key_lk3_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk3_3_reg[] = 
-    {
-        {"lpm_key_lk3_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk3_2_reg[] = 
-    {
-        {"lpm_key_lk3_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk3_1_reg[] = 
-    {
-        {"lpm_key_lk3_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_lpm_key_lk3_0_reg[] = 
-    {
-        {"lpm_key_lk3_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_22_reg[] = 
-    {
-        {"etcam_key_lk0_22", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_21_reg[] = 
-    {
-        {"etcam_key_lk0_21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_20_reg[] = 
-    {
-        {"etcam_key_lk0_20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_19_reg[] = 
-    {
-        {"etcam_key_lk0_19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_18_reg[] = 
-    {
-        {"etcam_key_lk0_18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_17_reg[] = 
-    {
-        {"etcam_key_lk0_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_16_reg[] = 
-    {
-        {"etcam_key_lk0_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_15_reg[] = 
-    {
-        {"etcam_key_lk0_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_14_reg[] = 
-    {
-        {"etcam_key_lk0_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_13_reg[] = 
-    {
-        {"etcam_key_lk0_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_12_reg[] = 
-    {
-        {"etcam_key_lk0_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_11_reg[] = 
-    {
-        {"etcam_key_lk0_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_10_reg[] = 
-    {
-        {"etcam_key_lk0_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_9_reg[] = 
-    {
-        {"etcam_key_lk0_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_8_reg[] = 
-    {
-        {"etcam_key_lk0_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_7_reg[] = 
-    {
-        {"etcam_key_lk0_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_6_reg[] = 
-    {
-        {"etcam_key_lk0_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_5_reg[] = 
-    {
-        {"etcam_key_lk0_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_4_reg[] = 
-    {
-        {"etcam_key_lk0_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_3_reg[] = 
-    {
-        {"etcam_key_lk0_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_2_reg[] = 
-    {
-        {"etcam_key_lk0_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_1_reg[] = 
-    {
-        {"etcam_key_lk0_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk0_0_reg[] = 
-    {
-        {"etcam_key_lk0_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_22_reg[] = 
-    {
-        {"etcam_key_lk1_22", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_21_reg[] = 
-    {
-        {"etcam_key_lk1_21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_20_reg[] = 
-    {
-        {"etcam_key_lk1_20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_19_reg[] = 
-    {
-        {"etcam_key_lk1_19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_18_reg[] = 
-    {
-        {"etcam_key_lk1_18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_17_reg[] = 
-    {
-        {"etcam_key_lk1_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_16_reg[] = 
-    {
-        {"etcam_key_lk1_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_15_reg[] = 
-    {
-        {"etcam_key_lk1_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_14_reg[] = 
-    {
-        {"etcam_key_lk1_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_13_reg[] = 
-    {
-        {"etcam_key_lk1_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_12_reg[] = 
-    {
-        {"etcam_key_lk1_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_11_reg[] = 
-    {
-        {"etcam_key_lk1_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_10_reg[] = 
-    {
-        {"etcam_key_lk1_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_9_reg[] = 
-    {
-        {"etcam_key_lk1_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_8_reg[] = 
-    {
-        {"etcam_key_lk1_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_7_reg[] = 
-    {
-        {"etcam_key_lk1_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_6_reg[] = 
-    {
-        {"etcam_key_lk1_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_5_reg[] = 
-    {
-        {"etcam_key_lk1_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_4_reg[] = 
-    {
-        {"etcam_key_lk1_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_3_reg[] = 
-    {
-        {"etcam_key_lk1_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_2_reg[] = 
-    {
-        {"etcam_key_lk1_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_1_reg[] = 
-    {
-        {"etcam_key_lk1_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk1_0_reg[] = 
-    {
-        {"etcam_key_lk1_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_22_reg[] = 
-    {
-        {"etcam_key_lk2_22", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_21_reg[] = 
-    {
-        {"etcam_key_lk2_21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_20_reg[] = 
-    {
-        {"etcam_key_lk2_20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_19_reg[] = 
-    {
-        {"etcam_key_lk2_19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_18_reg[] = 
-    {
-        {"etcam_key_lk2_18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_17_reg[] = 
-    {
-        {"etcam_key_lk2_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_16_reg[] = 
-    {
-        {"etcam_key_lk2_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_15_reg[] = 
-    {
-        {"etcam_key_lk2_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_14_reg[] = 
-    {
-        {"etcam_key_lk2_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_13_reg[] = 
-    {
-        {"etcam_key_lk2_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_12_reg[] = 
-    {
-        {"etcam_key_lk2_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_11_reg[] = 
-    {
-        {"etcam_key_lk2_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_10_reg[] = 
-    {
-        {"etcam_key_lk2_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_9_reg[] = 
-    {
-        {"etcam_key_lk2_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_8_reg[] = 
-    {
-        {"etcam_key_lk2_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_7_reg[] = 
-    {
-        {"etcam_key_lk2_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_6_reg[] = 
-    {
-        {"etcam_key_lk2_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_5_reg[] = 
-    {
-        {"etcam_key_lk2_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_4_reg[] = 
-    {
-        {"etcam_key_lk2_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_3_reg[] = 
-    {
-        {"etcam_key_lk2_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_2_reg[] = 
-    {
-        {"etcam_key_lk2_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_1_reg[] = 
-    {
-        {"etcam_key_lk2_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk2_0_reg[] = 
-    {
-        {"etcam_key_lk2_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_22_reg[] = 
-    {
-        {"etcam_key_lk3_22", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_21_reg[] = 
-    {
-        {"etcam_key_lk3_21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_20_reg[] = 
-    {
-        {"etcam_key_lk3_20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_19_reg[] = 
-    {
-        {"etcam_key_lk3_19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_18_reg[] = 
-    {
-        {"etcam_key_lk3_18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_17_reg[] = 
-    {
-        {"etcam_key_lk3_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_16_reg[] = 
-    {
-        {"etcam_key_lk3_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_15_reg[] = 
-    {
-        {"etcam_key_lk3_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_14_reg[] = 
-    {
-        {"etcam_key_lk3_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_13_reg[] = 
-    {
-        {"etcam_key_lk3_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_12_reg[] = 
-    {
-        {"etcam_key_lk3_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_11_reg[] = 
-    {
-        {"etcam_key_lk3_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_10_reg[] = 
-    {
-        {"etcam_key_lk3_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_9_reg[] = 
-    {
-        {"etcam_key_lk3_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_8_reg[] = 
-    {
-        {"etcam_key_lk3_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_7_reg[] = 
-    {
-        {"etcam_key_lk3_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_6_reg[] = 
-    {
-        {"etcam_key_lk3_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_5_reg[] = 
-    {
-        {"etcam_key_lk3_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_4_reg[] = 
-    {
-        {"etcam_key_lk3_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_3_reg[] = 
-    {
-        {"etcam_key_lk3_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_2_reg[] = 
-    {
-        {"etcam_key_lk3_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_1_reg[] = 
-    {
-        {"etcam_key_lk3_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_etcam_key_lk3_0_reg[] = 
-    {
-        {"etcam_key_lk3_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_pbu_key_lk0_3_reg[] = 
-    {
-        {"pbu_key_lk0_3", DPP_FIELD_FLAG_RO, 20, 21, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_pbu_key_lk0_2_reg[] = 
-    {
-        {"pbu_key_lk0_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_pbu_key_lk0_1_reg[] = 
-    {
-        {"pbu_key_lk0_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_pbu_key_lk0_0_reg[] = 
-    {
-        {"pbu_key_lk0_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_pbu_key_lk1_3_reg[] = 
-    {
-        {"pbu_key_lk1_3", DPP_FIELD_FLAG_RO, 20, 21, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_pbu_key_lk1_2_reg[] = 
-    {
-        {"pbu_key_lk1_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_pbu_key_lk1_1_reg[] = 
-    {
-        {"pbu_key_lk1_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_pbu_key_lk1_0_reg[] = 
-    {
-        {"pbu_key_lk1_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_pbu_key_lk2_3_reg[] = 
-    {
-        {"pbu_key_lk2_3", DPP_FIELD_FLAG_RO, 20, 21, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_pbu_key_lk2_2_reg[] = 
-    {
-        {"pbu_key_lk2_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_pbu_key_lk2_1_reg[] = 
-    {
-        {"pbu_key_lk2_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_pbu_key_lk2_0_reg[] = 
-    {
-        {"pbu_key_lk2_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_pbu_key_lk3_3_reg[] = 
-    {
-        {"pbu_key_lk3_3", DPP_FIELD_FLAG_RO, 20, 21, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_pbu_key_lk3_2_reg[] = 
-    {
-        {"pbu_key_lk3_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_pbu_key_lk3_1_reg[] = 
-    {
-        {"pbu_key_lk3_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cfg_pbu_key_lk3_0_reg[] = 
-    {
-        {"pbu_key_lk3_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_learn_fifo_pfull_ast_reg[] = 
-    {
-        {"schd_learn_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_learn_fifo_pfull_neg_reg[] = 
-    {
-        {"schd_learn_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_hash0_fifo_pfull_ast_reg[] = 
-    {
-        {"schd_hash0_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_hash0_fifo_pfull_neg_reg[] = 
-    {
-        {"schd_hash0_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_hash1_fifo_pfull_ast_reg[] = 
-    {
-        {"schd_hash1_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_hash1_fifo_pfull_neg_reg[] = 
-    {
-        {"schd_hash1_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_hash2_fifo_pfull_ast_reg[] = 
-    {
-        {"schd_hash2_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_hash2_fifo_pfull_neg_reg[] = 
-    {
-        {"schd_hash2_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_hash3_fifo_pfull_ast_reg[] = 
-    {
-        {"schd_hash3_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_hash3_fifo_pfull_neg_reg[] = 
-    {
-        {"schd_hash3_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_lpm_fifo_pfull_ast_reg[] = 
-    {
-        {"schd_lpm_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_lpm_fifo_pfull_neg_reg[] = 
-    {
-        {"schd_lpm_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_key_fifo_pfull_ast_reg[] = 
-    {
-        {"hash0_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_key_fifo_pfull_neg_reg[] = 
-    {
-        {"hash0_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_sreq_fifo_pfull_ast_reg[] = 
-    {
-        {"hash0_sreq_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_sreq_fifo_pfull_neg_reg[] = 
-    {
-        {"hash0_sreq_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_int_rsp_fifo_pfull_ast_reg[] = 
-    {
-        {"hash0_int_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_int_rsp_fifo_pfull_neg_reg[] = 
-    {
-        {"hash0_int_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_ext_rsp_fifo_pfull_ast_reg[] = 
-    {
-        {"hash0_ext_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x20, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_ext_rsp_fifo_pfull_neg_reg[] = 
-    {
-        {"hash0_ext_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_key_fifo_pfull_ast_reg[] = 
-    {
-        {"hash1_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_key_fifo_pfull_neg_reg[] = 
-    {
-        {"hash1_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_sreq_fifo_pfull_ast_reg[] = 
-    {
-        {"hash1_sreq_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_sreq_fifo_pfull_neg_reg[] = 
-    {
-        {"hash1_sreq_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_int_rsp_fifo_pfull_ast_reg[] = 
-    {
-        {"hash1_int_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_int_rsp_fifo_pfull_neg_reg[] = 
-    {
-        {"hash1_int_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_ext_rsp_fifo_pfull_ast_reg[] = 
-    {
-        {"hash1_ext_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x20, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_ext_rsp_fifo_pfull_neg_reg[] = 
-    {
-        {"hash1_ext_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_key_fifo_pfull_ast_reg[] = 
-    {
-        {"hash2_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_key_fifo_pfull_neg_reg[] = 
-    {
-        {"hash2_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_sreq_fifo_pfull_ast_reg[] = 
-    {
-        {"hash2_sreq_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_sreq_fifo_pfull_neg_reg[] = 
-    {
-        {"hash2_sreq_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_int_rsp_fifo_pfull_ast_reg[] = 
-    {
-        {"hash2_int_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_int_rsp_fifo_pfull_neg_reg[] = 
-    {
-        {"hash2_int_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_ext_rsp_fifo_pfull_ast_reg[] = 
-    {
-        {"hash2_ext_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x20, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_ext_rsp_fifo_pfull_neg_reg[] = 
-    {
-        {"hash2_ext_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_key_fifo_pfull_ast_reg[] = 
-    {
-        {"hash3_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_key_fifo_pfull_neg_reg[] = 
-    {
-        {"hash3_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_sreq_fifo_pfull_ast_reg[] = 
-    {
-        {"hash3_sreq_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_sreq_fifo_pfull_neg_reg[] = 
-    {
-        {"hash3_sreq_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_int_rsp_fifo_pfull_ast_reg[] = 
-    {
-        {"hash3_int_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_int_rsp_fifo_pfull_neg_reg[] = 
-    {
-        {"hash3_int_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_ext_rsp_fifo_pfull_ast_reg[] = 
-    {
-        {"hash3_ext_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x20, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_ext_rsp_fifo_pfull_neg_reg[] = 
-    {
-        {"hash3_ext_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_as_info_reg[] = 
-    {
-        {"lpm_as_type", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"lpm_as_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u0_pfull_neg_reg[] = 
-    {
-        {"lpm_ext_rsp_fifo_u0_pfull_neg", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u2_pfull_ast_reg[] = 
-    {
-        {"lpm_ext_rsp_fifo_u2_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1e4, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u2_pfull_neg_reg[] = 
-    {
-        {"lpm_ext_rsp_fifo_u2_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1e0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u3_pfull_ast_reg[] = 
-    {
-        {"lpm_ext_rsp_fifo_u3_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1e4, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u3_pfull_neg_reg[] = 
-    {
-        {"lpm_ext_rsp_fifo_u3_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1e0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u4_pfull_ast_reg[] = 
-    {
-        {"lpm_ext_rsp_fifo_u4_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u4_pfull_neg_reg[] = 
-    {
-        {"lpm_ext_rsp_fifo_u4_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_as_rsp_fifo_u0_pfull_ast_reg[] = 
-    {
-        {"lpm_as_rsp_fifo_u0_pfull_ast", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_as_rsp_fifo_u0_pfull_neg_reg[] = 
-    {
-        {"lpm_as_rsp_fifo_u0_pfull_neg", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_as_rsp_fifo_u1_pfull_ast_reg[] = 
-    {
-        {"lpm_as_rsp_fifo_u1_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1e2, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_as_rsp_fifo_u1_pfull_neg_reg[] = 
-    {
-        {"lpm_as_rsp_fifo_u1_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1dc, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_v4_ddr3_base_addr_reg[] = 
-    {
-        {"lpm_v4_ddr3_base_addr", DPP_FIELD_FLAG_RW, 25, 26, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_v6_ddr3_base_addr_reg[] = 
-    {
-        {"lpm_v6_ddr3_base_addr", DPP_FIELD_FLAG_RW, 25, 26, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_debug_cnt_mode_reg[] = 
-    {
-        {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash_p0_key_vld_cnt_reg[] = 
-    {
-        {"hash_p0_key_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash_p1_key_vld_cnt_reg[] = 
-    {
-        {"hash_p1_key_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash_p2_key_vld_cnt_reg[] = 
-    {
-        {"hash_p2_key_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash_p3_key_vld_cnt_reg[] = 
-    {
-        {"hash_p3_key_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_p0_key_vld_cnt_reg[] = 
-    {
-        {"lpm_p0_key_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash_p0_rsp_vld_cnt_reg[] = 
-    {
-        {"hash_p0_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash_p1_rsp_vld_cnt_reg[] = 
-    {
-        {"hash_p1_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash_p2_rsp_vld_cnt_reg[] = 
-    {
-        {"hash_p2_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash_p3_rsp_vld_cnt_reg[] = 
-    {
-        {"hash_p3_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_p0_rsp_vld_cnt_reg[] = 
-    {
-        {"lpm_p0_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash_p0_smf_cnt_reg[] = 
-    {
-        {"hash_p0_smf_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash_p1_smf_cnt_reg[] = 
-    {
-        {"hash_p1_smf_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash_p2_smf_cnt_reg[] = 
-    {
-        {"hash_p2_smf_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash_p3_smf_cnt_reg[] = 
-    {
-        {"hash_p3_smf_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_p0_smf_cnt_reg[] = 
-    {
-        {"lpm_p0_smf_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash_p0_spacevld_cnt_reg[] = 
-    {
-        {"hash_p0_spacevld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash_p1_spacevld_cnt_reg[] = 
-    {
-        {"hash_p1_spacevld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash_p2_spacevld_cnt_reg[] = 
-    {
-        {"hash_p2_spacevld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash_p3_spacevld_cnt_reg[] = 
-    {
-        {"hash_p3_spacevld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_smmu1_p0_req_vld_cnt_reg[] = 
-    {
-        {"smmu1_p0_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_smmu1_p1_req_vld_cnt_reg[] = 
-    {
-        {"smmu1_p1_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_smmu1_p2_req_vld_cnt_reg[] = 
-    {
-        {"smmu1_p2_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_smmu1_p3_req_vld_cnt_reg[] = 
-    {
-        {"smmu1_p3_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_smmu1_p4_req_vld_cnt_reg[] = 
-    {
-        {"smmu1_p4_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_smmu1_p5_req_vld_cnt_reg[] = 
-    {
-        {"smmu1_p5_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_smmu1_p0_rsp_vld_cnt_reg[] = 
-    {
-        {"smmu1_p0_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_smmu1_p1_rsp_vld_cnt_reg[] = 
-    {
-        {"smmu1_p1_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_smmu1_p2_rsp_vld_cnt_reg[] = 
-    {
-        {"smmu1_p2_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_smmu1_p3_rsp_vld_cnt_reg[] = 
-    {
-        {"smmu1_p3_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_smmu1_p4_rsp_vld_cnt_reg[] = 
-    {
-        {"smmu1_p4_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_smmu1_p5_rsp_vld_cnt_reg[] = 
-    {
-        {"smmu1_p5_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_learn_fifo_int_cnt_reg[] = 
-    {
-        {"schd_learn_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_hash0_fifo_int_cnt_reg[] = 
-    {
-        {"schd_hash0_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_hash1_fifo_int_cnt_reg[] = 
-    {
-        {"schd_hash1_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_hash2_fifo_int_cnt_reg[] = 
-    {
-        {"schd_hash2_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_hash3_fifo_int_cnt_reg[] = 
-    {
-        {"schd_hash3_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_lpm_fifo_int_cnt_reg[] = 
-    {
-        {"schd_lpm_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_learn_fifo_parity_err_cnt_reg[] = 
-    {
-        {"schd_learn_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_hash0_fifo_parity_err_cnt_reg[] = 
-    {
-        {"schd_hash0_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_hash1_fifo_parity_err_cnt_reg[] = 
-    {
-        {"schd_hash1_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_hash2_fifo_parity_err_cnt_reg[] = 
-    {
-        {"schd_hash2_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_hash3_fifo_parity_err_cnt_reg[] = 
-    {
-        {"schd_hash3_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_lpm_fifo_parity_err_cnt_reg[] = 
-    {
-        {"schd_lpm_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_rd_init_cft_cnt_reg[] = 
-    {
-        {"rd_init_cft_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp0_zblk0_ecc_err_cnt_reg[] = 
-    {
-        {"zgp0_zblk0_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp0_zblk1_ecc_err_cnt_reg[] = 
-    {
-        {"zgp0_zblk1_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp0_zblk2_ecc_err_cnt_reg[] = 
-    {
-        {"zgp0_zblk2_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp0_zblk3_ecc_err_cnt_reg[] = 
-    {
-        {"zgp0_zblk3_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp0_zblk4_ecc_err_cnt_reg[] = 
-    {
-        {"zgp0_zblk4_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp0_zblk5_ecc_err_cnt_reg[] = 
-    {
-        {"zgp0_zblk5_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp0_zblk6_ecc_err_cnt_reg[] = 
-    {
-        {"zgp0_zblk6_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp0_zblk7_ecc_err_cnt_reg[] = 
-    {
-        {"zgp0_zblk7_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp1_zblk0_ecc_err_cnt_reg[] = 
-    {
-        {"zgp1_zblk0_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp1_zblk1_ecc_err_cnt_reg[] = 
-    {
-        {"zgp1_zblk1_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp1_zblk2_ecc_err_cnt_reg[] = 
-    {
-        {"zgp1_zblk2_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp1_zblk3_ecc_err_cnt_reg[] = 
-    {
-        {"zgp1_zblk3_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp1_zblk4_ecc_err_cnt_reg[] = 
-    {
-        {"zgp1_zblk4_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp1_zblk5_ecc_err_cnt_reg[] = 
-    {
-        {"zgp1_zblk5_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp1_zblk6_ecc_err_cnt_reg[] = 
-    {
-        {"zgp1_zblk6_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp1_zblk7_ecc_err_cnt_reg[] = 
-    {
-        {"zgp1_zblk7_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp2_zblk0_ecc_err_cnt_reg[] = 
-    {
-        {"zgp2_zblk0_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp2_zblk1_ecc_err_cnt_reg[] = 
-    {
-        {"zgp2_zblk1_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp2_zblk2_ecc_err_cnt_reg[] = 
-    {
-        {"zgp2_zblk2_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp2_zblk3_ecc_err_cnt_reg[] = 
-    {
-        {"zgp2_zblk3_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp2_zblk4_ecc_err_cnt_reg[] = 
-    {
-        {"zgp2_zblk4_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp2_zblk5_ecc_err_cnt_reg[] = 
-    {
-        {"zgp2_zblk5_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp2_zblk6_ecc_err_cnt_reg[] = 
-    {
-        {"zgp2_zblk6_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp2_zblk7_ecc_err_cnt_reg[] = 
-    {
-        {"zgp2_zblk7_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp3_zblk0_ecc_err_cnt_reg[] = 
-    {
-        {"zgp3_zblk0_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp3_zblk1_ecc_err_cnt_reg[] = 
-    {
-        {"zgp3_zblk1_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp3_zblk2_ecc_err_cnt_reg[] = 
-    {
-        {"zgp3_zblk2_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp3_zblk3_ecc_err_cnt_reg[] = 
-    {
-        {"zgp3_zblk3_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp3_zblk4_ecc_err_cnt_reg[] = 
-    {
-        {"zgp3_zblk4_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp3_zblk5_ecc_err_cnt_reg[] = 
-    {
-        {"zgp3_zblk5_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp3_zblk6_ecc_err_cnt_reg[] = 
-    {
-        {"zgp3_zblk6_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zgp3_zblk7_ecc_err_cnt_reg[] = 
-    {
-        {"zgp3_zblk7_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zcam_hash_p0_err_cnt_reg[] = 
-    {
-        {"zcam_hash_p0_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zcam_hash_p1_err_cnt_reg[] = 
-    {
-        {"zcam_hash_p1_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zcam_hash_p2_err_cnt_reg[] = 
-    {
-        {"zcam_hash_p2_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zcam_hash_p3_err_cnt_reg[] = 
-    {
-        {"zcam_hash_p3_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zcam_lpm_err_cnt_reg[] = 
-    {
-        {"zcam_lpm_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_sreq_fifo_parity_err_cnt_reg[] = 
-    {
-        {"hash0_sreq_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_sreq_fifo_int_cnt_reg[] = 
-    {
-        {"hash0_sreq_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_key_fifo_int_cnt_reg[] = 
-    {
-        {"hash0_key_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_int_rsp_fifo_parity_err_cnt_reg[] = 
-    {
-        {"hash0_int_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_ext_rsp_fifo_parity_err_cnt_reg[] = 
-    {
-        {"hash0_ext_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_ext_rsp_fifo_int_cnt_reg[] = 
-    {
-        {"hash0_ext_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_int_rsp_fifo_int_cnt_reg[] = 
-    {
-        {"hash0_int_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_sreq_fifo_parity_err_cnt_reg[] = 
-    {
-        {"hash1_sreq_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_sreq_fifo_int_cnt_reg[] = 
-    {
-        {"hash1_sreq_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_key_fifo_int_cnt_reg[] = 
-    {
-        {"hash1_key_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_int_rsp_fifo_parity_err_cnt_reg[] = 
-    {
-        {"hash1_int_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_ext_rsp_fifo_parity_err_cnt_reg[] = 
-    {
-        {"hash1_ext_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_ext_rsp_fifo_int_cnt_reg[] = 
-    {
-        {"hash1_ext_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_int_rsp_fifo_int_cnt_reg[] = 
-    {
-        {"hash1_int_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_sreq_fifo_parity_err_cnt_reg[] = 
-    {
-        {"hash2_sreq_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_sreq_fifo_int_cnt_reg[] = 
-    {
-        {"hash2_sreq_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_key_fifo_int_cnt_reg[] = 
-    {
-        {"hash2_key_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_int_rsp_fifo_parity_err_cnt_reg[] = 
-    {
-        {"hash2_int_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_ext_rsp_fifo_parity_err_cnt_reg[] = 
-    {
-        {"hash2_ext_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_ext_rsp_fifo_int_cnt_reg[] = 
-    {
-        {"hash2_ext_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_int_rsp_fifo_int_cnt_reg[] = 
-    {
-        {"hash2_int_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_sreq_fifo_parity_err_cnt_reg[] = 
-    {
-        {"hash3_sreq_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_sreq_fifo_int_cnt_reg[] = 
-    {
-        {"hash3_sreq_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_key_fifo_int_cnt_reg[] = 
-    {
-        {"hash3_key_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_int_rsp_fifo_parity_err_cnt_reg[] = 
-    {
-        {"hash3_int_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_ext_rsp_fifo_parity_err_cnt_reg[] = 
-    {
-        {"hash3_ext_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_ext_rsp_fifo_int_cnt_reg[] = 
-    {
-        {"hash3_ext_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_int_rsp_fifo_int_cnt_reg[] = 
-    {
-        {"hash3_int_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_int_cnt_reg[] = 
-    {
-        {"lpm_ext_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_ext_v6_fifo_int_cnt_reg[] = 
-    {
-        {"lpm_ext_v6_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_ext_v4_fifo_int_cnt_reg[] = 
-    {
-        {"lpm_ext_v4_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_ext_addr_fifo_int_cnt_reg[] = 
-    {
-        {"lpm_ext_addr_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_ext_v4_fifo_parity_err_cnt_reg[] = 
-    {
-        {"lpm_ext_v4_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_ext_v6_fifo_parity_err_cnt_reg[] = 
-    {
-        {"lpm_ext_v6_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_parity_err_cnt_reg[] = 
-    {
-        {"lpm_ext_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_as_req_fifo_int_cnt_reg[] = 
-    {
-        {"lpm_as_req_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_as_int_rsp_fifo_int_cnt_reg[] = 
-    {
-        {"lpm_as_int_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_se_alg_int_status_reg[] = 
-    {
-        {"schd_int_unmask_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"zblk_ecc_int_unmask_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"hash0_int_unmask_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"hash1_int_unmask_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"hash2_int_unmask_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"hash3_int_unmask_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"lpm_int_unmask_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_int_en_reg[] = 
-    {
-        {"wr_rsp_fifo_ovfl", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"init_rd_cft_en", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"schd_lpm_fifo_parity_errl", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"schd_hash3_fifo_parity_err", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"schd_hash2_fifo_parity_err", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"schd_hash1_fifo_parity_err", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"schd_hash0_fifo_parity_err", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"schd_learn_fifo_parity_err", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"schd_lpm_fifo_ovfl", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"schd_hash3_fifo_ovfl", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"schd_hash2_fifo_unfl", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"schd_hash1_fifo_ovfl", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"schd_hash0_fifo_ovfl", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"schd_learn_fifo_ovfl", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_int_mask_reg[] = 
-    {
-        {"schd_int_mask", DPP_FIELD_FLAG_RW, 13, 14, 0x3fff, 0x0},
-    };
-DPP_FIELD_T g_se_alg_schd_int_status_reg[] = 
-    {
-        {"schd_int_status", DPP_FIELD_FLAG_RC, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblk_ecc_int_en_reg[] = 
-    {
-        {"zblk_ecc_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffff, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblk_ecc_int_mask_reg[] = 
-    {
-        {"zblk_ecc_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffff, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblk_ecc_int_status_reg[] = 
-    {
-        {"zblk_ecc_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_int_en_reg[] = 
-    {
-        {"zcam_hash_p0_err_en", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"hash0_agree_int_fifo_ovf_en", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"hash0_agree_ext_fifo_ovf_en", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"hash0_agree_ext_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"hash0_agree_int_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"hash0_key_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"hash0_sreq_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"hash0_key_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_int_mask_reg[] = 
-    {
-        {"hash0_int_mask", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash0_int_status_reg[] = 
-    {
-        {"hash0_int_status", DPP_FIELD_FLAG_RC, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_int_en_reg[] = 
-    {
-        {"zcam_hash_p1_err_en", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"hash1_agree_int_fifo_ovf_en", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"hash1_agree_ext_fifo_ovf_en", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"hash1_agree_ext_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"hash1_agree_int_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"hash1_key_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"hash1_sreq_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"hash1_key_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_int_mask_reg[] = 
-    {
-        {"hash1_int_mask", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash1_int_status_reg[] = 
-    {
-        {"hash1_int_status", DPP_FIELD_FLAG_RC, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_int_en_reg[] = 
-    {
-        {"zcam_hash_p2_err_en", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"hash2_agree_int_fifo_ovf_en", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"hash2_agree_ext_fifo_ovf_en", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"hash2_agree_ext_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"hash2_agree_int_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"hash2_key_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"hash2_sreq_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"hash2_key_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_int_mask_reg[] = 
-    {
-        {"hash2_int_mask", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash2_int_status_reg[] = 
-    {
-        {"hash2_int_status", DPP_FIELD_FLAG_RC, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_int_en_reg[] = 
-    {
-        {"zcam_hash_p3_err_en", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"hash3_agree_int_fifo_ovf_en", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"hash3_agree_ext_fifo_ovf_en", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"hash3_agree_ext_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"hash3_agree_int_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"hash3_key_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"hash3_sreq_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"hash3_key_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_int_mask_reg[] = 
-    {
-        {"hash3_int_mask", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_se_alg_hash3_int_status_reg[] = 
-    {
-        {"hash3_int_status", DPP_FIELD_FLAG_RC, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_int_en_reg[] = 
-    {
-        {"zcam_lpm_err_en", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"lpm_as_int_rsp_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"lpm_as_req_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"lpm_ext_ddr_rsp_fifo_parity_en", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"lpm_ext_v6_key_parity_en", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"lpm_ext_v4_key_parity_en", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"lpm_ext_addr_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"lpm_ext_v4_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"lpm_ext_v6_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"lpm_ext_ddr_rsp_ovf_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_int_mask_reg[] = 
-    {
-        {"lpm_int_mask", DPP_FIELD_FLAG_RW, 9, 10, 0x3ff, 0x0},
-    };
-DPP_FIELD_T g_se_alg_lpm_int_status_reg[] = 
-    {
-        {"lpm_int_status", DPP_FIELD_FLAG_RC, 9, 10, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_lpm_mask0_reg[] = 
-    {
-        {"vpn_id_mask", DPP_FIELD_FLAG_RW, 143, 16, 0x0, 0x0},
-        {"prefix0_mask", DPP_FIELD_FLAG_RW, 127, 32, 0x0, 0x0},
-        {"prefix1_mask", DPP_FIELD_FLAG_RW, 95, 32, 0x0, 0x0},
-        {"prefix2_mask", DPP_FIELD_FLAG_RW, 63, 32, 0x0, 0x0},
-        {"prefix3_mask", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_lpm_mask1_reg[] = 
-    {
-        {"vpn_id_mask", DPP_FIELD_FLAG_RW, 143, 16, 0x0, 0x0},
-        {"prefix0_mask", DPP_FIELD_FLAG_RW, 127, 32, 0x0, 0x0},
-        {"prefix1_mask", DPP_FIELD_FLAG_RW, 95, 32, 0x0, 0x0},
-        {"prefix2_mask", DPP_FIELD_FLAG_RW, 63, 32, 0x0, 0x0},
-        {"prefix3_mask", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_lpm_mask2_reg[] = 
-    {
-        {"vpn_id_mask", DPP_FIELD_FLAG_RW, 143, 16, 0x0, 0x0},
-        {"prefix0_mask", DPP_FIELD_FLAG_RW, 127, 32, 0x0, 0x0},
-        {"prefix1_mask", DPP_FIELD_FLAG_RW, 95, 32, 0x0, 0x0},
-        {"prefix2_mask", DPP_FIELD_FLAG_RW, 63, 32, 0x0, 0x0},
-        {"prefix3_mask", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_lpm_mask3_reg[] = 
-    {
-        {"vpn_id_mask", DPP_FIELD_FLAG_RW, 143, 16, 0x0, 0x0},
-        {"prefix0_mask", DPP_FIELD_FLAG_RW, 127, 32, 0x0, 0x0},
-        {"prefix1_mask", DPP_FIELD_FLAG_RW, 95, 32, 0x0, 0x0},
-        {"prefix2_mask", DPP_FIELD_FLAG_RW, 63, 32, 0x0, 0x0},
-        {"prefix3_mask", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_default_route0_reg[] = 
-    {
-        {"vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0},
-        {"vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0},
-        {"vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_default_route1_reg[] = 
-    {
-        {"vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0},
-        {"vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0},
-        {"vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_default_route2_reg[] = 
-    {
-        {"vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0},
-        {"vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0},
-        {"vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_default_route3_reg[] = 
-    {
-        {"vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0},
-        {"vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0},
-        {"vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_default_route4_reg[] = 
-    {
-        {"vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0},
-        {"vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0},
-        {"vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_default_route5_reg[] = 
-    {
-        {"vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0},
-        {"vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0},
-        {"vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_default_route6_reg[] = 
-    {
-        {"vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0},
-        {"vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0},
-        {"vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_default_route7_reg[] = 
-    {
-        {"vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0},
-        {"vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0},
-        {"vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_hash_listtable_item0_reg[] = 
-    {
-        {"hash_item", DPP_FIELD_FLAG_RW, 511, 512, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_hash_listtable_item1_reg[] = 
-    {
-        {"hash_item", DPP_FIELD_FLAG_RW, 511, 512, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_hash_listtable_item2_reg[] = 
-    {
-        {"hash_item", DPP_FIELD_FLAG_RW, 511, 512, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_hash_listtable_item3_reg[] = 
-    {
-        {"hash_item", DPP_FIELD_FLAG_RW, 511, 512, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_ecc_err_status_reg[] = 
-    {
-        {"sram3_ecc_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"sram2_ecc_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"sram1_ecc_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"sram0_ecc_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_lpm_v6_sram_cmp_reg[] = 
-    {
-        {"sram_cmp_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_alg_zblock_lpm_v4_sram_cmp_reg[] = 
-    {
-        {"sram_cmp_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_parser_kschd_pful_cfg_reg[] = 
-    {
-        {"kschd_pful_assert", DPP_FIELD_FLAG_RW, 11, 6, 0xc, 0x0},
-        {"kschd_pful_negate", DPP_FIELD_FLAG_RW, 5, 6, 0xc, 0x0},
-    };
-DPP_FIELD_T g_se_parser_debug_cnt_mode_reg[] = 
-    {
-        {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_parser_parser_int_en_reg[] = 
-    {
-        {"parser_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_parser_parser_int_mask_reg[] = 
-    {
-        {"parser_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_parser_parser_int_status_reg[] = 
-    {
-        {"parser_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_parser_parser_int_unmask_flag_reg[] = 
-    {
-        {"parser_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_parser_ecc_bypass_read_reg[] = 
-    {
-        {"ecc_bypass_read", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0},
-    };
-DPP_FIELD_T g_se_parser_mex0_5_req_cnt_reg[] = 
-    {
-        {"mex0_5_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_parser_kschd_req0_5_cnt_reg[] = 
-    {
-        {"kschd_req0_5_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_parser_kschd_parser_fc0_5_cnt_reg[] = 
-    {
-        {"kschd_parser_fc0_5_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_parser_se_ppu_mex0_5_fc_cnt_reg[] = 
-    {
-        {"se_ppu_mex0_5_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_parser_smmu0_marc_fc_cnt_reg[] = 
-    {
-        {"smmu0_marc_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_parser_smmu0_marc_key_cnt_reg[] = 
-    {
-        {"smmu0_marc_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_parser_cmmu_key_cnt_reg[] = 
-    {
-        {"cmmu_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_parser_cmmu_parser_fc_cnt_reg[] = 
-    {
-        {"cmmu_parser_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_parser_marc_tab_type_err_mex0_5_cnt_reg[] = 
-    {
-        {"marc_tab_type_err_mex0_5_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_parser_eram_fulladdr_drop_cnt_reg[] = 
-    {
-        {"eram_fulladdr_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_hash0_pful_cfg_reg[] = 
-    {
-        {"hash0_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7d9f6, 0x0},
-    };
-DPP_FIELD_T g_se_as_hash1_pful_cfg_reg[] = 
-    {
-        {"hash1_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7d9f6, 0x0},
-    };
-DPP_FIELD_T g_se_as_hash2_pful_cfg_reg[] = 
-    {
-        {"hash2_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7d9f6, 0x0},
-    };
-DPP_FIELD_T g_se_as_hash3_pful_cfg_reg[] = 
-    {
-        {"hash3_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7d9f6, 0x0},
-    };
-DPP_FIELD_T g_se_as_pbu_pful_cfg_reg[] = 
-    {
-        {"pbu_pful_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x69a, 0x0},
-    };
-DPP_FIELD_T g_se_as_lpm_pful_cfg_reg[] = 
-    {
-        {"lpm_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7d9f6, 0x0},
-    };
-DPP_FIELD_T g_se_as_etcam_pful_cfg_reg[] = 
-    {
-        {"etcam_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1c38, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_learn0_fifo_cfg_reg[] = 
-    {
-        {"as_learn1_pful_negate", DPP_FIELD_FLAG_RW, 27, 7, 0x38, 0x0},
-        {"as_learn1_pful_asert", DPP_FIELD_FLAG_RW, 20, 7, 0x38, 0x0},
-        {"as_learn0_pful_negate", DPP_FIELD_FLAG_RW, 13, 7, 0x38, 0x0},
-        {"as_learn0_pful_asert", DPP_FIELD_FLAG_RW, 6, 7, 0x38, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_learn1_fifo_cfg_reg[] = 
-    {
-        {"as_learn3_pful_negate", DPP_FIELD_FLAG_RW, 27, 7, 0x38, 0x0},
-        {"as_learn3_pful_asert", DPP_FIELD_FLAG_RW, 20, 7, 0x38, 0x0},
-        {"as_learn2_pful_negate", DPP_FIELD_FLAG_RW, 13, 7, 0x38, 0x0},
-        {"as_learn2_pful_asert", DPP_FIELD_FLAG_RW, 6, 7, 0x38, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_dma_fifo_cfg_reg[] = 
-    {
-        {"as_dma_fifo_cfg", DPP_FIELD_FLAG_RW, 15, 16, 0x7272, 0x0},
-    };
-DPP_FIELD_T g_se_as_age_pful_cfg_reg[] = 
-    {
-        {"age_pful_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x618, 0x0},
-    };
-DPP_FIELD_T g_se_as_etcam_rsp_cfg_reg[] = 
-    {
-        {"eram_rsp_pful_negate", DPP_FIELD_FLAG_RW, 27, 7, 0x24, 0x0},
-        {"eram_rsp_pful_assert", DPP_FIELD_FLAG_RW, 20, 7, 0x24, 0x0},
-        {"etcam_rsp_pful_negate", DPP_FIELD_FLAG_RW, 13, 7, 0x21, 0x0},
-        {"etcam_rsp_pful_assert", DPP_FIELD_FLAG_RW, 6, 7, 0x21, 0x0},
-    };
-DPP_FIELD_T g_se_as_pbu_ecc_bypass_read_reg[] = 
-    {
-        {"pbu_ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_as_etcam0_ecc_bypass_read_reg[] = 
-    {
-        {"etcam0_ecc_bypass_read", DPP_FIELD_FLAG_RW, 2, 3, 0x7, 0x0},
-    };
-DPP_FIELD_T g_se_as_etcam1_ecc_bypass_read_reg[] = 
-    {
-        {"etcam1_ecc_bypass_read", DPP_FIELD_FLAG_RW, 2, 3, 0x7, 0x0},
-    };
-DPP_FIELD_T g_se_as_lpm_ecc_bypass_read_reg[] = 
-    {
-        {"lpm_ecc_bypass_read", DPP_FIELD_FLAG_RW, 1, 2, 0x3, 0x0},
-    };
-DPP_FIELD_T g_se_as_hash_ecc_bypass_read_reg[] = 
-    {
-        {"hash3_ecc_bypass_read", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"hash2_ecc_bypass_read", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"hash1_ecc_bypass_read", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"hash0_ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_as_hash_learn_ecc_bypass_read_reg[] = 
-    {
-        {"hash_learn_ecc_bypass_read", DPP_FIELD_FLAG_RW, 3, 4, 0xf, 0x0},
-    };
-DPP_FIELD_T g_se_as_debug_cnt_mode_reg[] = 
-    {
-        {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_int_0_en_reg[] = 
-    {
-        {"as_int_0_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_int_0_mask_reg[] = 
-    {
-        {"as_int_0_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_int_1_en_reg[] = 
-    {
-        {"as_int_1_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_int_1_mask_reg[] = 
-    {
-        {"as_int_1_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_int_2_en_reg[] = 
-    {
-        {"as_int_2_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_int_2_mask_reg[] = 
-    {
-        {"as_int_2_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_int_0_status_reg[] = 
-    {
-        {"port0_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_int_1_status_reg[] = 
-    {
-        {"port1_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_int_2_status_reg[] = 
-    {
-        {"port2_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_se_as_int_status_reg[] = 
-    {
-        {"as_int_2_unmask_flag", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"as_int_1_unmask_flag", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"as_int_0_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_hash0_3_wr_req_cnt_reg[] = 
-    {
-        {"hash0_3_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_smmu0_etcam0_1_fc_cnt_reg[] = 
-    {
-        {"smmu0_etcam0_1_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_etcam0_1_smmu0_req_cnt_reg[] = 
-    {
-        {"etcam0_1_smmu0_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_smmu0_etcam0_1_rsp_cnt_reg[] = 
-    {
-        {"smmu0_etcam0_1_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_hla_hash_p0_3_key_cnt_reg[] = 
-    {
-        {"as_hla_hash_p0_3_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_hla_lpm_p0_key_cnt_reg[] = 
-    {
-        {"as_hla_lpm_p0_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_alg_as_hash_p0_3_rsp_cnt_reg[] = 
-    {
-        {"alg_as_hash_p0_3_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_alg_as_hash_p0_3_smf_rsp_cnt_reg[] = 
-    {
-        {"alg_as_hash_p0_3_smf_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_alg_as_lpm_p0_rsp_cnt_reg[] = 
-    {
-        {"alg_as_lpm_p0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_alg_as_lpm_p0_3_smf_rsp_cnt_reg[] = 
-    {
-        {"alg_as_lpm_p0_3_smf_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_pbu_key_cnt_reg[] = 
-    {
-        {"as_pbu_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_pbu_se_dpi_rsp_dat_cnt_reg[] = 
-    {
-        {"pbu_se_dpi_rsp_dat_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_etcam_ctrl_req0_cnt_reg[] = 
-    {
-        {"as_etcam_ctrl_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_etcam_ctrl_as_index0_1_cnt_reg[] = 
-    {
-        {"etcam_ctrl_as_index0_1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_etcam_ctrl_as_hit0_1_cnt_reg[] = 
-    {
-        {"etcam_ctrl_as_hit0_1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_smmu0_req_cnt_reg[] = 
-    {
-        {"as_smmu0_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_learn_hla_wr_cnt_reg[] = 
-    {
-        {"learn_hla_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_smmu1_req_cnt_reg[] = 
-    {
-        {"as_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_se_cfg_mac_dat_cnt_reg[] = 
-    {
-        {"se_cfg_mac_dat_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_alg_as_hash_p0_3_fc_cnt_reg[] = 
-    {
-        {"alg_as_hash_p0_3_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_alg_as_lpm_p0_fc_cnt_reg[] = 
-    {
-        {"alg_as_lpm_p0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_alg_hash_p0_3_fc_cnt_reg[] = 
-    {
-        {"as_alg_hash_p0_3_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_alg_lpm_p0_fc_cnt_reg[] = 
-    {
-        {"as_alg_lpm_p0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_pbu_fc_cnt_reg[] = 
-    {
-        {"as_pbu_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_pbu_se_dpi_key_fc_cnt_reg[] = 
-    {
-        {"pbu_se_dpi_key_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_as_etcam_ctrl_fc0_1_cnt_reg[] = 
-    {
-        {"as_etcam_ctrl_fc0_1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_etcam_ctrl_as_fc0_1_cnt_reg[] = 
-    {
-        {"etcam_ctrl_as_fc0_1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_smmu0_as_mac_age_fc_cnt_reg[] = 
-    {
-        {"smmu0_as_mac_age_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_alg_learn_fc_cnt_reg[] = 
-    {
-        {"alg_learn_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_smmu1_as_fc_cnt_reg[] = 
-    {
-        {"smmu1_as_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_as_cfg_se_mac_fc_cnt_reg[] = 
-    {
-        {"cfg_se_mac_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_kschd_cpu_rdy_reg[] = 
-    {
-        {"kschd_cpu_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_ppu0_ecc_bypass_read_reg[] = 
-    {
-        {"ppu0_ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_pbu_ecc_bypass_read_reg[] = 
-    {
-        {"pbu_ecc_bypass_read", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_smmu1_ecc_bypass_read_reg[] = 
-    {
-        {"u3_smmu1_ecc_bypass_read", DPP_FIELD_FLAG_RO, 23, 6, 0x3f, 0x0},
-        {"u2_smmu1_ecc_bypass_read", DPP_FIELD_FLAG_RO, 17, 6, 0x3f, 0x0},
-        {"u1_smmu1_ecc_bypass_read", DPP_FIELD_FLAG_RO, 11, 6, 0x3f, 0x0},
-        {"u0_smmu1_ecc_bypass_read", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_ass_ecc_bypass_read_reg[] = 
-    {
-        {"ass_ecc_bypass_read", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_sdt_h_reg[] = 
-    {
-        {"sdt_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_sdt_l_reg[] = 
-    {
-        {"sdt_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_hash_key15_reg[] = 
-    {
-        {"dma_en", DPP_FIELD_FLAG_RW, 25, 1, 0x0, 0x0},
-        {"delete_en", DPP_FIELD_FLAG_RW, 24, 1, 0x0, 0x0},
-        {"hash_key15", DPP_FIELD_FLAG_RW, 23, 24, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_hash_key14_reg[] = 
-    {
-        {"hash_key14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_hash_key13_reg[] = 
-    {
-        {"hash_key13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_hash_key12_reg[] = 
-    {
-        {"hash_key12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_hash_key11_reg[] = 
-    {
-        {"hash_key11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_hash_key10_reg[] = 
-    {
-        {"hash_key10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_hash_key9_reg[] = 
-    {
-        {"hash_key9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_hash_key8_reg[] = 
-    {
-        {"hash_key8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_hash_key7_reg[] = 
-    {
-        {"hash_key7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_hash_key6_reg[] = 
-    {
-        {"hash_key6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_hash_key5_reg[] = 
-    {
-        {"hash_key5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_hash_key4_reg[] = 
-    {
-        {"hash_key4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_hash_key3_reg[] = 
-    {
-        {"hash_key3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_hash_key2_reg[] = 
-    {
-        {"hash_key2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_hash_key1_reg[] = 
-    {
-        {"hash_key1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_hash_key0_reg[] = 
-    {
-        {"hash_key0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_schd_int_0_en_reg[] = 
-    {
-        {"port0_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_schd_int_0_mask_reg[] = 
-    {
-        {"port0_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_schd_int_1_en_reg[] = 
-    {
-        {"port1_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_schd_int_1_mask_reg[] = 
-    {
-        {"port1_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_schd_int_2_en_reg[] = 
-    {
-        {"port2_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_schd_int_2_mask_reg[] = 
-    {
-        {"port2_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_schd_int_3_en_reg[] = 
-    {
-        {"port3_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_schd_int_3_mask_reg[] = 
-    {
-        {"port3_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_schd_int_4_en_reg[] = 
-    {
-        {"port4_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_schd_int_4_mask_reg[] = 
-    {
-        {"port4_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_schd_int_0_status_reg[] = 
-    {
-        {"port0_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_schd_int_1_status_reg[] = 
-    {
-        {"port1_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_schd_int_2_status_reg[] = 
-    {
-        {"port2_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_schd_int_3_status_reg[] = 
-    {
-        {"port3_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_schd_int_4_status_reg[] = 
-    {
-        {"port4_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_se_kschd_int_status_reg[] = 
-    {
-        {"schd_int4_unmask_flag", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"schd_int3_unmask_flag", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"schd_int2_unmask_flag", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"schd_int1_unmask_flag", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"schd_int0_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_debug_cnt_mode_reg[] = 
-    {
-        {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_se_parser_kschd_key0_3_cnt_reg[] = 
-    {
-        {"se_parser_kschd_key0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_se_smmu1_key0_3_cnt_reg[] = 
-    {
-        {"se_smmu1_key0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_kschd_as_key0_cnt_reg[] = 
-    {
-        {"kschd_as_key0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_kschd_as_key1_cnt_reg[] = 
-    {
-        {"kschd_as_key1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_kschd_as_key2_cnt_reg[] = 
-    {
-        {"kschd_as_key2_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_kschd_as_key3_cnt_reg[] = 
-    {
-        {"kschd_as_key3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_kschd_as_key4_cnt_reg[] = 
-    {
-        {"kschd_as_key4_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_kschd_as_key5_cnt_reg[] = 
-    {
-        {"kschd_as_key5_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_kschd_as_key6_cnt_reg[] = 
-    {
-        {"kschd_as_key6_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_kschd_as_key9_cnt_reg[] = 
-    {
-        {"kschd_as_key9_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_kschd_se_parser_fc0_3_cnt_reg[] = 
-    {
-        {"kschd_se_parser_fc0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_smmu1_se_fc0_3_cnt_reg[] = 
-    {
-        {"smmu1_se_fc0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt0_reg[] = 
-    {
-        {"as_kschd_fc_cnt0", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt1_reg[] = 
-    {
-        {"as_kschd_fc_cnt1", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt2_reg[] = 
-    {
-        {"as_kschd_fc_cnt2", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt3_reg[] = 
-    {
-        {"as_kschd_fc_cnt3", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt4_reg[] = 
-    {
-        {"as_kschd_fc_cnt4", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt5_reg[] = 
-    {
-        {"as_kschd_fc_cnt5", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt6_reg[] = 
-    {
-        {"as_kschd_fc_cnt6", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt9_reg[] = 
-    {
-        {"as_kschd_fc_cnt9", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_hash_pful_cfg_reg[] = 
-    {
-        {"rschd_hash_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00370037, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_hash_ept_cfg_reg[] = 
-    {
-        {"rschd_hash_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00090009, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_pbu_pful_cfg_reg[] = 
-    {
-        {"rschd_pbu_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x002d002d, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_pbu_ept_cfg_reg[] = 
-    {
-        {"rschd_pbu_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00130013, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_lpm_pful_cfg_reg[] = 
-    {
-        {"rschd_lpm_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00240024, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_lpm_ept_cfg_reg[] = 
-    {
-        {"rschd_lpm_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x001c001c, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_etcam_pful_cfg_reg[] = 
-    {
-        {"rschd_etcam_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00110011, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_etcam_ept_cfg_reg[] = 
-    {
-        {"rschd_etcam_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x002f002f, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_smmu0_wb_pful_cfg_reg[] = 
-    {
-        {"smmu0_wb_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00330033, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_smmu0_wb_ept_cfg_reg[] = 
-    {
-        {"smmu0_wb_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x000d000d, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_smmu1_wb_pful_cfg_reg[] = 
-    {
-        {"smmu1_wb_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x003a003a, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_smmu1_wb_ept_cfg_reg[] = 
-    {
-        {"smmu1_wb_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00060006, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_alg_wb_pful_cfg_reg[] = 
-    {
-        {"alg_wb_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x003a003a, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_alg_wb_ept_cfg_reg[] = 
-    {
-        {"alg_wb_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00060006, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_wr_rsp_vld_en_reg[] = 
-    {
-        {"wr_rsp_vld_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_nppu_wb_pful_cfg_reg[] = 
-    {
-        {"nppu_wb_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00380038, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_nppu_wb_ept_cfg_reg[] = 
-    {
-        {"nppu_wb_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00080008, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_port0_int_en_reg[] = 
-    {
-        {"port0_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_port0_int_mask_reg[] = 
-    {
-        {"port0_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_port1_int_en_reg[] = 
-    {
-        {"port1_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_port1_int_mask_reg[] = 
-    {
-        {"port1_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_port0_int_status_reg[] = 
-    {
-        {"port0_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_port1_int_status_reg[] = 
-    {
-        {"port1_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_se_rschd_int_status_reg[] = 
-    {
-        {"port1_int_unmask_flag", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"port0_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_debug_cnt_mode_reg[] = 
-    {
-        {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_se_ppu_mex0_5_rsp1_cnt_reg[] = 
-    {
-        {"se_ppu_mex0_5_rsp1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_as_rschd_rsp0_cnt_reg[] = 
-    {
-        {"as_rschd_rsp0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_as_rschd_rsp1_cnt_reg[] = 
-    {
-        {"as_rschd_rsp1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_as_rschd_rsp2_cnt_reg[] = 
-    {
-        {"as_rschd_rsp2_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_as_rschd_rsp3_cnt_reg[] = 
-    {
-        {"as_rschd_rsp3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_as_rschd_rsp4_cnt_reg[] = 
-    {
-        {"as_rschd_rsp4_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_as_rschd_rsp5_cnt_reg[] = 
-    {
-        {"as_rschd_rsp5_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_as_rschd_rsp6_cnt_reg[] = 
-    {
-        {"as_rschd_rsp6_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_as_rschd_rsp9_cnt_reg[] = 
-    {
-        {"as_rschd_rsp9_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_smmu1_se_rsp0_3_cnt_reg[] = 
-    {
-        {"smmu1_se_rsp0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_ppu_se_mex0_3_fc_cnt_reg[] = 
-    {
-        {"ppu_se_mex0_3_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt0_reg[] = 
-    {
-        {"rschd_as_fc_cnt0", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt1_reg[] = 
-    {
-        {"rschd_as_fc_cnt1", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt2_reg[] = 
-    {
-        {"rschd_as_fc_cnt2", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt3_reg[] = 
-    {
-        {"rschd_as_fc_cnt3", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt4_reg[] = 
-    {
-        {"rschd_as_fc_cnt4", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt5_reg[] = 
-    {
-        {"rschd_as_fc_cnt5", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt6_reg[] = 
-    {
-        {"rschd_as_fc_cnt6", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt9_reg[] = 
-    {
-        {"rschd_as_fc_cnt9", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_se_smmu1_fc0_3_cnt_reg[] = 
-    {
-        {"se_smmu1_fc0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_smmu0_se_wr_done_cnt_reg[] = 
-    {
-        {"smmu0_se_wr_done_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_se_smmu0_wr_done_fc_cnt_reg[] = 
-    {
-        {"se_smmu0_wr_done_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_smmu1_se_wr_rsp_cnt_reg[] = 
-    {
-        {"smmu1_se_wr_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_se_smmu1_wr_rsp_fc_cnt_reg[] = 
-    {
-        {"se_smmu1_wr_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_alg_se_wr_rsp_cnt_reg[] = 
-    {
-        {"alg_se_wr_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_rschd_se_alg_wr_rsp_fc_cnt_reg[] = 
-    {
-        {"se_alg_wr_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_pful_cfg0_reg[] = 
-    {
-        {"kschd_pful_assert0_1", DPP_FIELD_FLAG_RW, 27, 7, 0x18, 0x0},
-        {"kschd_pful_negate0_1", DPP_FIELD_FLAG_RW, 20, 7, 0x18, 0x0},
-        {"kschd_pful_assert0_0", DPP_FIELD_FLAG_RW, 13, 7, 0x20, 0x0},
-        {"kschd_pful_negate0_0", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_pful_cfg1_reg[] = 
-    {
-        {"kschd_pful_assert1_1", DPP_FIELD_FLAG_RW, 25, 7, 0x20, 0x0},
-        {"kschd_pful_negate1_1", DPP_FIELD_FLAG_RW, 18, 7, 0x20, 0x0},
-        {"kschd_pful_assert1_0", DPP_FIELD_FLAG_RW, 11, 6, 0x0c, 0x0},
-        {"kschd_pful_negate1_0", DPP_FIELD_FLAG_RW, 5, 6, 0x0c, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl_pful1_cfg_reg[] = 
-    {
-        {"ctrl_pful1_assert", DPP_FIELD_FLAG_RW, 7, 4, 0x3, 0x0},
-        {"ctrl_pful1_negate", DPP_FIELD_FLAG_RW, 3, 4, 0x2, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl_pful2_cfg_reg[] = 
-    {
-        {"ctrl_pful2_assert", DPP_FIELD_FLAG_RW, 9, 5, 0x0a, 0x0},
-        {"ctrl_pful2_negate", DPP_FIELD_FLAG_RW, 4, 5, 0x08, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl_pful3_cfg_reg[] = 
-    {
-        {"ctrl_pful3_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x38, 0x0},
-        {"ctrl_pful3_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x36, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_pful_cfg_reg[] = 
-    {
-        {"rschd_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x24, 0x0},
-        {"rschd_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_ept_cfg_reg[] = 
-    {
-        {"rschd_ept_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x1c, 0x0},
-        {"rschd_ept_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x1c, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_alucmd_pful_cfg_reg[] = 
-    {
-        {"alucmd_pful_assert", DPP_FIELD_FLAG_RW, 11, 6, 0x18, 0x0},
-        {"alucmd_pful_negate", DPP_FIELD_FLAG_RW, 5, 6, 0x16, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_aluwr_pful_cfg_reg[] = 
-    {
-        {"aluwr_pful_assert", DPP_FIELD_FLAG_RW, 7, 4, 0x5, 0x0},
-        {"aluwr_pful_negate", DPP_FIELD_FLAG_RW, 3, 4, 0x4, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_wr_arb_pful_cfg0_reg[] = 
-    {
-        {"wr_arb_pful0_assert", DPP_FIELD_FLAG_RW, 11, 6, 0x15, 0x0},
-        {"wr_arb_pful0_negate", DPP_FIELD_FLAG_RW, 5, 6, 0x15, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_wr_arb_pful_cfg1_reg[] = 
-    {
-        {"wr_arb_pful1_assert", DPP_FIELD_FLAG_RW, 15, 8, 0x64, 0x0},
-        {"wr_arb_pful1_negate", DPP_FIELD_FLAG_RW, 7, 8, 0x64, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ord_pful_cfg_reg[] = 
-    {
-        {"ord_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x2a, 0x0},
-        {"ord_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x2a, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cfg_dma_baddr_reg[] = 
-    {
-        {"cfg_dma_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cfg_odma0_baddr_reg[] = 
-    {
-        {"cfg_odma0_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cfg_odma1_baddr_reg[] = 
-    {
-        {"cfg_odma1_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cfg_odma2_baddr_reg[] = 
-    {
-        {"cfg_odma2_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cfg_odma_tdm_baddr_reg[] = 
-    {
-        {"cfg_odma_tdm_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cfg_mcast_baddr_reg[] = 
-    {
-        {"cfg_mcast_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cfg_lpm0_reg[] = 
-    {
-        {"lpm0_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0},
-        {"lpm0_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cfg_lpm1_reg[] = 
-    {
-        {"lpm1_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0},
-        {"lpm1_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cfg_lpm2_reg[] = 
-    {
-        {"lpm2_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0},
-        {"lpm2_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cfg_lpm3_reg[] = 
-    {
-        {"lpm3_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0},
-        {"lpm3_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cfg_lpm4_reg[] = 
-    {
-        {"lpm4_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0},
-        {"lpm4_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cfg_lpm5_reg[] = 
-    {
-        {"lpm5_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0},
-        {"lpm5_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cfg_lpm6_reg[] = 
-    {
-        {"lpm6_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0},
-        {"lpm6_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cfg_lpm7_reg[] = 
-    {
-        {"lpm7_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0},
-        {"lpm7_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_debug_cnt_mode_reg[] = 
-    {
-        {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_stat_overflow_mode_reg[] = 
-    {
-        {"stat_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_init_en_cfg_tmp_reg[] = 
-    {
-        {"init_en_cfg_tmp31", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp30", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp29", DPP_FIELD_FLAG_RW, 29, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp28", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp27", DPP_FIELD_FLAG_RW, 27, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp26", DPP_FIELD_FLAG_RW, 26, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp25", DPP_FIELD_FLAG_RW, 25, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp24", DPP_FIELD_FLAG_RW, 24, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp23", DPP_FIELD_FLAG_RW, 23, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp22", DPP_FIELD_FLAG_RW, 22, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp21", DPP_FIELD_FLAG_RW, 21, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp20", DPP_FIELD_FLAG_RW, 20, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp19", DPP_FIELD_FLAG_RW, 19, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp18", DPP_FIELD_FLAG_RW, 18, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp17", DPP_FIELD_FLAG_RW, 17, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp16", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp15", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp14", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp13", DPP_FIELD_FLAG_RW, 13, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp12", DPP_FIELD_FLAG_RW, 12, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp11", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp10", DPP_FIELD_FLAG_RW, 10, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp9", DPP_FIELD_FLAG_RW, 9, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp8", DPP_FIELD_FLAG_RW, 8, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp7", DPP_FIELD_FLAG_RW, 7, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp6", DPP_FIELD_FLAG_RW, 6, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp5", DPP_FIELD_FLAG_RW, 5, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp4", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp3", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp2", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp1", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"init_en_cfg_tmp0", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int_unmask_flag_reg[] = 
-    {
-        {"smmu0_int0_31_unmask_flag", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int0_en_reg[] = 
-    {
-        {"smmu0_int0_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int0_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int0_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int0_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int0_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int0_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int0_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int0_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int0_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int0_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int0_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int0_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int0_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int0_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int0_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int0_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int0_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int0_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int0_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int0_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int0_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int0_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int0_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int0_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int0_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int0_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int0_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int0_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int0_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int0_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int0_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int0_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int0_mask_reg[] = 
-    {
-        {"smmu0_int0_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int0_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int0_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int0_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int0_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int0_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int0_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int0_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int0_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int0_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int0_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int0_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int0_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int0_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int0_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int0_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int0_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int0_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int0_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int0_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int0_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int0_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int0_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int0_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int0_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int0_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int0_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int0_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int0_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int0_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int0_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int0_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int0_status_reg[] = 
-    {
-        {"smmu0_int0_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int0_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int0_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int0_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int0_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int0_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int0_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int0_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int0_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int0_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int0_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int0_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int0_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int0_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int0_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int0_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int0_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int0_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int0_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int0_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int0_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int0_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int0_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int0_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int0_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int0_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int0_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int0_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int0_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int0_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int0_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int0_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int1_en_reg[] = 
-    {
-        {"smmu0_int1_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int1_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int1_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int1_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int1_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int1_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int1_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int1_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int1_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int1_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int1_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int1_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int1_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int1_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int1_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int1_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int1_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int1_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int1_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int1_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int1_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int1_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int1_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int1_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int1_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int1_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int1_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int1_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int1_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int1_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int1_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int1_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int1_mask_reg[] = 
-    {
-        {"smmu0_int1_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int1_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int1_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int1_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int1_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int1_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int1_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int1_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int1_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int1_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int1_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int1_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int1_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int1_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int1_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int1_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int1_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int1_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int1_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int1_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int1_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int1_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int1_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int1_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int1_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int1_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int1_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int1_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int1_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int1_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int1_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int1_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int1_status_reg[] = 
-    {
-        {"smmu0_int1_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int1_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int1_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int1_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int1_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int1_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int1_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int1_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int1_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int1_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int1_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int1_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int1_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int1_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int1_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int1_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int1_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int1_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int1_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int1_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int1_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int1_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int1_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int1_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int1_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int1_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int1_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int1_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int1_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int1_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int1_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int1_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int2_en_reg[] = 
-    {
-        {"smmu0_int2_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int2_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int2_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int2_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int2_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int2_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int2_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int2_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int2_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int2_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int2_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int2_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int2_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int2_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int2_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int2_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int2_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int2_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int2_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int2_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int2_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int2_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int2_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int2_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int2_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int2_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int2_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int2_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int2_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int2_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int2_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int2_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int2_mask_reg[] = 
-    {
-        {"smmu0_int2_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int2_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int2_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int2_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int2_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int2_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int2_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int2_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int2_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int2_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int2_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int2_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int2_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int2_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int2_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int2_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int2_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int2_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int2_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int2_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int2_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int2_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int2_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int2_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int2_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int2_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int2_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int2_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int2_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int2_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int2_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int2_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int2_status_reg[] = 
-    {
-        {"smmu0_int2_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int2_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int2_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int2_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int2_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int2_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int2_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int2_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int2_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int2_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int2_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int2_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int2_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int2_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int2_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int2_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int2_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int2_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int2_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int2_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int2_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int2_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int2_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int2_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int2_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int2_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int2_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int2_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int2_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int2_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int2_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int2_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int3_en_reg[] = 
-    {
-        {"smmu0_int3_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int3_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int3_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int3_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int3_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int3_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int3_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int3_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int3_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int3_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int3_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int3_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int3_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int3_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int3_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int3_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int3_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int3_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int3_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int3_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int3_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int3_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int3_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int3_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int3_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int3_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int3_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int3_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int3_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int3_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int3_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int3_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int3_mask_reg[] = 
-    {
-        {"smmu0_int3_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int3_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int3_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int3_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int3_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int3_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int3_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int3_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int3_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int3_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int3_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int3_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int3_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int3_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int3_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int3_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int3_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int3_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int3_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int3_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int3_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int3_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int3_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int3_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int3_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int3_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int3_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int3_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int3_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int3_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int3_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int3_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int3_status_reg[] = 
-    {
-        {"smmu0_int3_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int3_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int3_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int3_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int3_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int3_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int3_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int3_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int3_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int3_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int3_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int3_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int3_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int3_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int3_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int3_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int3_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int3_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int3_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int3_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int3_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int3_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int3_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int3_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int3_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int3_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int3_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int3_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int3_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int3_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int3_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int3_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int4_en_reg[] = 
-    {
-        {"smmu0_int4_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int4_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int4_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int4_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int4_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int4_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int4_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int4_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int4_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int4_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int4_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int4_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int4_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int4_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int4_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int4_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int4_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int4_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int4_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int4_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int4_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int4_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int4_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int4_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int4_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int4_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int4_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int4_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int4_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int4_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int4_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int4_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int4_mask_reg[] = 
-    {
-        {"smmu0_int4_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int4_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int4_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int4_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int4_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int4_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int4_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int4_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int4_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int4_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int4_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int4_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int4_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int4_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int4_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int4_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int4_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int4_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int4_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int4_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int4_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int4_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int4_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int4_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int4_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int4_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int4_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int4_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int4_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int4_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int4_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int4_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int4_status_reg[] = 
-    {
-        {"smmu0_int4_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int4_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int4_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int4_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int4_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int4_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int4_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int4_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int4_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int4_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int4_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int4_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int4_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int4_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int4_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int4_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int4_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int4_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int4_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int4_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int4_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int4_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int4_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int4_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int4_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int4_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int4_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int4_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int4_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int4_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int4_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int4_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int5_en_reg[] = 
-    {
-        {"smmu0_int5_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int5_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int5_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int5_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int5_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int5_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int5_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int5_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int5_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int5_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int5_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int5_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int5_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int5_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int5_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int5_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int5_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int5_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int5_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int5_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int5_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int5_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int5_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int5_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int5_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int5_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int5_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int5_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int5_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int5_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int5_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int5_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int5_mask_reg[] = 
-    {
-        {"smmu0_int5_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int5_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int5_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int5_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int5_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int5_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int5_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int5_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int5_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int5_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int5_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int5_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int5_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int5_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int5_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int5_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int5_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int5_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int5_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int5_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int5_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int5_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int5_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int5_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int5_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int5_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int5_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int5_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int5_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int5_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int5_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int5_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int5_status_reg[] = 
-    {
-        {"smmu0_int5_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int5_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int5_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int5_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int5_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int5_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int5_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int5_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int5_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int5_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int5_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int5_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int5_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int5_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int5_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int5_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int5_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int5_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int5_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int5_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int5_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int5_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int5_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int5_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int5_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int5_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int5_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int5_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int5_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int5_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int5_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int5_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int6_en_reg[] = 
-    {
-        {"smmu0_int6_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int6_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int6_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int6_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int6_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int6_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int6_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int6_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int6_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int6_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int6_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int6_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int6_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int6_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int6_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int6_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int6_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int6_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int6_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int6_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int6_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int6_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int6_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int6_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int6_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int6_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int6_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int6_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int6_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int6_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int6_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int6_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int6_mask_reg[] = 
-    {
-        {"smmu0_int6_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int6_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int6_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int6_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int6_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int6_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int6_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int6_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int6_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int6_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int6_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int6_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int6_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int6_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int6_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int6_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int6_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int6_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int6_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int6_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int6_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int6_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int6_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int6_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int6_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int6_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int6_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int6_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int6_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int6_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int6_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int6_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int6_status_reg[] = 
-    {
-        {"smmu0_int6_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int6_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int6_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int6_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int6_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int6_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int6_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int6_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int6_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int6_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int6_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int6_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int6_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int6_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int6_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int6_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int6_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int6_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int6_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int6_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int6_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int6_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int6_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int6_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int6_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int6_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int6_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int6_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int6_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int6_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int6_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int6_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int7_en_reg[] = 
-    {
-        {"smmu0_int7_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int7_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int7_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int7_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int7_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int7_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int7_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int7_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int7_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int7_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int7_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int7_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int7_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int7_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int7_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int7_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int7_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int7_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int7_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int7_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int7_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int7_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int7_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int7_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int7_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int7_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int7_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int7_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int7_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int7_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int7_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int7_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int7_mask_reg[] = 
-    {
-        {"smmu0_int7_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int7_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int7_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int7_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int7_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int7_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int7_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int7_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int7_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int7_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int7_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int7_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int7_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int7_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int7_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int7_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int7_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int7_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int7_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int7_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int7_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int7_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int7_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int7_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int7_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int7_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int7_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int7_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int7_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int7_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int7_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int7_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int7_status_reg[] = 
-    {
-        {"smmu0_int7_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int7_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int7_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int7_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int7_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int7_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int7_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int7_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int7_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int7_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int7_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int7_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int7_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int7_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int7_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int7_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int7_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int7_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int7_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int7_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int7_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int7_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int7_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int7_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int7_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int7_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int7_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int7_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int7_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int7_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int7_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int7_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int8_en_reg[] = 
-    {
-        {"smmu0_int8_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int8_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int8_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int8_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int8_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int8_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int8_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int8_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int8_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int8_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int8_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int8_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int8_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int8_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int8_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int8_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int8_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int8_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int8_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int8_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int8_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int8_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int8_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int8_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int8_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int8_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int8_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int8_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int8_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int8_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int8_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int8_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int8_mask_reg[] = 
-    {
-        {"smmu0_int8_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int8_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int8_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int8_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int8_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int8_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int8_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int8_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int8_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int8_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int8_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int8_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int8_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int8_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int8_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int8_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int8_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int8_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int8_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int8_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int8_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int8_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int8_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int8_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int8_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int8_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int8_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int8_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int8_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int8_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int8_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int8_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int8_status_reg[] = 
-    {
-        {"smmu0_int8_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int8_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int8_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int8_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int8_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int8_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int8_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int8_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int8_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int8_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int8_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int8_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int8_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int8_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int8_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int8_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int8_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int8_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int8_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int8_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int8_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int8_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int8_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int8_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int8_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int8_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int8_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int8_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int8_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int8_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int8_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int8_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int9_en_reg[] = 
-    {
-        {"smmu0_int8_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int8_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int8_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int8_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int8_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int8_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int8_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int8_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int8_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int8_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int8_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int8_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int9_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int9_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int9_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int9_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int9_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int9_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int9_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int9_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int9_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int9_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int9_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int9_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int9_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int9_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int9_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int9_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int9_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int9_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int9_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int9_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int9_mask_reg[] = 
-    {
-        {"smmu0_int9_mask0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int9_status_reg[] = 
-    {
-        {"smmu0_int9_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int10_en_reg[] = 
-    {
-        {"smmu0_int10_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"smmu0_int10_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"smmu0_int10_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"smmu0_int10_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"smmu0_int10_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"smmu0_int10_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"smmu0_int10_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"smmu0_int10_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"smmu0_int10_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"smmu0_int10_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"smmu0_int10_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"smmu0_int10_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"smmu0_int10_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int10_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int10_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int10_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int10_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int10_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int10_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int10_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int10_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int10_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int10_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int10_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int10_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int10_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int10_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int10_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int10_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int10_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int10_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int10_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int10_mask_reg[] = 
-    {
-        {"smmu0_int10_mask0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int10_status_reg[] = 
-    {
-        {"smmu0_int10_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int11_en_reg[] = 
-    {
-        {"smmu0_int11_en0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int11_mask_reg[] = 
-    {
-        {"smmu0_int11_mask0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int11_status_reg[] = 
-    {
-        {"smmu0_int11_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int12_en_reg[] = 
-    {
-        {"smmu0_int12_en0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int12_mask_reg[] = 
-    {
-        {"smmu0_int12_mask0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int12_status_reg[] = 
-    {
-        {"smmu0_int12_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int13_en_reg[] = 
-    {
-        {"smmu0_int13_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int13_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int13_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int13_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int13_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int13_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int13_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int13_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int13_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int13_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int13_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int13_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int13_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int13_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int13_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int13_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int13_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int13_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int13_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int13_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int13_mask_reg[] = 
-    {
-        {"smmu0_int13_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"smmu0_int13_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"smmu0_int13_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"smmu0_int13_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int13_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int13_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int13_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int13_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int13_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int13_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int13_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int13_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int13_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int13_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int13_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int13_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int13_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int13_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int13_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int13_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int13_status_reg[] = 
-    {
-        {"smmu0_int13_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int13_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int13_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int13_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int13_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int13_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int13_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int13_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int13_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int13_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int13_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int13_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int13_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int13_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int13_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int13_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int13_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int13_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int13_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int13_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int14_en_reg[] = 
-    {
-        {"smmu0_int14_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int14_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int14_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int14_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int14_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int14_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int14_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int14_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int14_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int14_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int14_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int14_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int14_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int14_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int14_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int14_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int14_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int14_mask_reg[] = 
-    {
-        {"smmu0_int14_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"smmu0_int14_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"smmu0_int14_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"smmu0_int14_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"smmu0_int14_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"smmu0_int14_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"smmu0_int14_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"smmu0_int14_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"smmu0_int14_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"smmu0_int14_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"smmu0_int14_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"smmu0_int14_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"smmu0_int14_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"smmu0_int14_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"smmu0_int14_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"smmu0_int14_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"smmu0_int14_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int14_status_reg[] = 
-    {
-        {"smmu0_int14_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int14_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int14_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int14_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int14_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int14_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int14_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int14_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int14_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int14_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int14_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int14_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int14_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int14_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int14_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int14_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int14_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_ecc_unmask_flag_reg[] = 
-    {
-        {"smmu0_int53_unmask_flag", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int52_unmask_flag", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int51_unmask_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int50_unmask_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int49_unmask_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int48_unmask_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int47_unmask_flag", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int46_unmask_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int45_unmask_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int44_unmask_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int43_unmask_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int42_unmask_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int41_unmask_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int40_unmask_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int39_unmask_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int38_unmask_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int37_unmask_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int36_unmask_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int35_unmask_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int34_unmask_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int33_unmask_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int32_unmask_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int15_en_reg[] = 
-    {
-        {"smmu0_int15_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int15_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int15_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int15_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int15_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int15_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int15_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int15_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int15_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int15_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int15_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int15_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int15_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int15_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int15_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int15_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int15_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int15_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int15_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int15_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int15_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int15_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int15_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int15_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int15_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int15_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int15_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int15_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int15_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int15_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int15_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int15_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int15_mask_reg[] = 
-    {
-        {"smmu0_int15_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int15_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int15_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int15_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int15_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int15_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int15_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int15_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int15_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int15_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int15_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int15_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int15_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int15_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int15_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int15_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int15_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int15_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int15_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int15_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int15_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int15_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int15_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int15_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int15_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int15_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int15_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int15_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int15_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int15_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int15_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int15_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int15_status_reg[] = 
-    {
-        {"smmu0_int15_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int15_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int15_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int15_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int15_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int15_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int15_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int15_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int15_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int15_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int15_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int15_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int15_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int15_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int15_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int15_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int15_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int15_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int15_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int15_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int15_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int15_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int15_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int15_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int15_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int15_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int15_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int15_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int15_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int15_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int15_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int15_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int16_en_reg[] = 
-    {
-        {"smmu0_int16_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int16_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int16_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int16_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int16_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int16_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int16_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int16_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int16_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int16_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int16_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int16_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int16_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int16_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int16_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int16_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int16_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int16_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int16_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int16_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int16_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int16_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int16_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int16_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int16_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int16_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int16_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int16_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int16_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int16_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int16_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int16_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int16_mask_reg[] = 
-    {
-        {"smmu0_int16_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int16_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int16_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int16_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int16_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int16_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int16_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int16_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int16_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int16_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int16_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int16_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int16_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int16_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int16_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int16_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int16_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int16_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int16_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int16_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int16_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int16_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int16_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int16_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int16_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int16_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int16_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int16_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int16_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int16_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int16_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int16_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int16_status_reg[] = 
-    {
-        {"smmu0_int16_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int16_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int16_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int16_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int16_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int16_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int16_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int16_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int16_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int16_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int16_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int16_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int16_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int16_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int16_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int16_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int16_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int16_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int16_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int16_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int16_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int16_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int16_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int16_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int16_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int16_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int16_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int16_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int16_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int16_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int16_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int16_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int17_en_reg[] = 
-    {
-        {"smmu0_int17_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int17_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int17_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int17_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int17_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int17_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int17_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int17_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int17_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int17_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int17_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int17_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int17_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int17_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int17_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int17_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int17_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int17_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int17_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int17_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int17_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int17_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int17_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int17_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int17_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int17_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int17_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int17_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int17_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int17_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int17_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int17_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int17_mask_reg[] = 
-    {
-        {"smmu0_int17_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int17_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int17_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int17_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int17_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int17_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int17_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int17_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int17_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int17_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int17_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int17_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int17_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int17_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int17_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int17_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int17_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int17_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int17_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int17_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int17_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int17_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int17_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int17_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int17_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int17_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int17_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int17_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int17_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int17_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int17_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int17_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int17_status_reg[] = 
-    {
-        {"smmu0_int17_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int17_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int17_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int17_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int17_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int17_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int17_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int17_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int17_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int17_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int17_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int17_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int17_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int17_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int17_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int17_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int17_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int17_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int17_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int17_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int17_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int17_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int17_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int17_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int17_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int17_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int17_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int17_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int17_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int17_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int17_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int17_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int18_en_reg[] = 
-    {
-        {"smmu0_int18_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int18_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int18_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int18_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int18_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int18_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int18_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int18_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int18_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int18_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int18_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int18_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int18_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int18_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int18_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int18_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int18_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int18_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int18_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int18_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int18_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int18_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int18_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int18_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int18_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int18_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int18_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int18_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int18_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int18_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int18_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int18_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int18_mask_reg[] = 
-    {
-        {"smmu0_int18_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int18_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int18_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int18_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int18_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int18_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int18_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int18_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int18_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int18_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int18_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int18_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int18_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int18_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int18_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int18_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int18_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int18_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int18_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int18_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int18_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int18_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int18_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int18_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int18_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int18_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int18_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int18_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int18_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int18_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int18_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int18_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int18_status_reg[] = 
-    {
-        {"smmu0_int18_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int18_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int18_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int18_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int18_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int18_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int18_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int18_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int18_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int18_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int18_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int18_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int18_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int18_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int18_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int18_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int18_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int18_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int18_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int18_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int18_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int18_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int18_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int18_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int18_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int18_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int18_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int18_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int18_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int18_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int18_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int18_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int19_en_reg[] = 
-    {
-        {"smmu0_int19_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int19_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int19_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int19_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int19_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int19_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int19_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int19_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int19_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int19_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int19_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int19_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int19_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int19_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int19_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int19_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int19_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int19_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int19_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int19_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int19_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int19_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int19_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int19_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int19_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int19_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int19_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int19_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int19_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int19_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int19_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int19_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int19_mask_reg[] = 
-    {
-        {"smmu0_int19_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int19_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int19_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int19_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int19_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int19_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int19_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int19_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int19_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int19_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int19_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int19_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int19_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int19_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int19_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int19_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int19_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int19_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int19_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int19_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int19_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int19_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int19_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int19_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int19_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int19_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int19_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int19_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int19_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int19_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int19_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int19_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int19_status_reg[] = 
-    {
-        {"smmu0_int19_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int19_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int19_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int19_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int19_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int19_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int19_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int19_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int19_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int19_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int19_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int19_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int19_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int19_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int19_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int19_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int19_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int19_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int19_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int19_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int19_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int19_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int19_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int19_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int19_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int19_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int19_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int19_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int19_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int19_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int19_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int19_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int20_en_reg[] = 
-    {
-        {"smmu0_int20_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int20_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int20_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int20_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int20_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int20_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int20_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int20_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int20_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int20_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int20_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int20_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int20_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int20_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int20_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int20_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int20_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int20_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int20_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int20_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int20_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int20_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int20_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int20_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int20_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int20_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int20_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int20_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int20_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int20_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int20_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int20_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int20_mask_reg[] = 
-    {
-        {"smmu0_int20_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int20_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int20_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int20_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int20_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int20_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int20_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int20_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int20_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int20_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int20_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int20_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int20_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int20_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int20_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int20_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int20_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int20_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int20_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int20_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int20_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int20_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int20_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int20_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int20_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int20_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int20_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int20_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int20_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int20_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int20_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int20_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int20_status_reg[] = 
-    {
-        {"smmu0_int20_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int20_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int20_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int20_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int20_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int20_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int20_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int20_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int20_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int20_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int20_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int20_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int20_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int20_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int20_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int20_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int20_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int20_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int20_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int20_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int20_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int20_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int20_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int20_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int20_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int20_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int20_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int20_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int20_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int20_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int20_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int20_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int21_en_reg[] = 
-    {
-        {"smmu0_int21_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int21_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int21_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int21_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int21_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int21_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int21_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int21_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int21_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int21_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int21_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int21_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int21_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int21_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int21_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int21_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int21_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int21_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int21_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int21_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int21_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int21_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int21_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int21_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int21_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int21_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int21_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int21_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int21_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int21_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int21_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int21_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int21_mask_reg[] = 
-    {
-        {"smmu0_int21_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int21_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int21_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int21_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int21_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int21_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int21_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int21_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int21_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int21_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int21_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int21_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int21_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int21_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int21_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int21_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int21_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int21_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int21_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int21_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int21_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int21_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int21_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int21_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int21_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int21_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int21_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int21_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int21_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int21_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int21_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int21_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int21_status_reg[] = 
-    {
-        {"smmu0_int21_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int21_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int21_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int21_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int21_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int21_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int21_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int21_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int21_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int21_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int21_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int21_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int21_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int21_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int21_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int21_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int21_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int21_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int21_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int21_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int21_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int21_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int21_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int21_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int21_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int21_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int21_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int21_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int21_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int21_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int21_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int21_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int22_en_reg[] = 
-    {
-        {"smmu0_int22_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int22_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int22_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int22_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int22_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int22_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int22_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int22_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int22_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int22_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int22_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int22_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int22_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int22_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int22_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int22_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int22_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int22_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int22_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int22_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int22_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int22_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int22_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int22_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int22_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int22_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int22_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int22_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int22_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int22_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int22_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int22_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int22_mask_reg[] = 
-    {
-        {"smmu0_int22_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int22_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int22_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int22_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int22_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int22_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int22_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int22_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int22_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int22_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int22_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int22_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int22_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int22_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int22_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int22_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int22_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int22_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int22_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int22_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int22_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int22_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int22_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int22_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int22_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int22_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int22_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int22_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int22_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int22_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int22_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int22_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int22_status_reg[] = 
-    {
-        {"smmu0_int22_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int22_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int22_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int22_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int22_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int22_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int22_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int22_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int22_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int22_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int22_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int22_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int22_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int22_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int22_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int22_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int22_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int22_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int22_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int22_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int22_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int22_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int22_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int22_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int22_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int22_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int22_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int22_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int22_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int22_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int22_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int22_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int23_en_reg[] = 
-    {
-        {"smmu0_int23_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int23_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int23_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int23_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int23_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int23_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int23_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int23_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int23_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int23_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int23_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int23_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int23_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int23_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int23_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int23_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int23_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int23_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int23_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int23_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int23_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int23_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int23_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int23_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int23_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int23_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int23_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int23_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int23_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int23_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int23_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int23_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int23_mask_reg[] = 
-    {
-        {"smmu0_int23_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int23_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int23_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int23_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int23_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int23_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int23_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int23_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int23_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int23_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int23_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int23_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int23_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int23_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int23_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int23_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int23_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int23_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int23_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int23_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int23_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int23_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int23_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int23_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int23_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int23_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int23_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int23_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int23_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int23_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int23_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int23_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int23_status_reg[] = 
-    {
-        {"smmu0_int23_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int23_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int23_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int23_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int23_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int23_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int23_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int23_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int23_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int23_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int23_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int23_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int23_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int23_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int23_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int23_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int23_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int23_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int23_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int23_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int23_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int23_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int23_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int23_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int23_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int23_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int23_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int23_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int23_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int23_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int23_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int23_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int24_en_reg[] = 
-    {
-        {"smmu0_int24_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int24_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int24_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int24_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int24_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int24_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int24_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int24_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int24_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int24_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int24_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int24_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int24_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int24_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int24_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int24_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int24_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int24_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int24_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int24_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int24_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int24_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int24_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int24_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int24_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int24_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int24_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int24_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int24_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int24_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int24_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int24_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int24_mask_reg[] = 
-    {
-        {"smmu0_int24_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int24_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int24_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int24_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int24_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int24_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int24_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int24_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int24_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int24_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int24_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int24_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int24_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int24_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int24_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int24_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int24_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int24_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int24_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int24_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int24_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int24_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int24_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int24_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int24_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int24_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int24_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int24_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int24_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int24_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int24_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int24_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int24_status_reg[] = 
-    {
-        {"smmu0_int24_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int24_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int24_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int24_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int24_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int24_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int24_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int24_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int24_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int24_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int24_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int24_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int24_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int24_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int24_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int24_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int24_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int24_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int24_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int24_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int24_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int24_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int24_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int24_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int24_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int24_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int24_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int24_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int24_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int24_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int24_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int24_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int25_en_reg[] = 
-    {
-        {"smmu0_int25_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int25_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int25_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int25_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int25_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int25_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int25_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int25_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int25_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int25_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int25_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int25_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int25_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int25_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int25_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int25_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int25_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int25_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int25_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int25_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int25_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int25_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int25_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int25_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int25_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int25_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int25_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int25_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int25_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int25_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int25_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int25_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int25_mask_reg[] = 
-    {
-        {"smmu0_int25_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int25_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int25_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int25_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int25_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int25_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int25_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int25_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int25_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int25_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int25_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int25_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int25_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int25_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int25_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int25_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int25_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int25_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int25_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int25_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int25_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int25_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int25_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int25_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int25_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int25_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int25_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int25_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int25_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int25_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int25_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int25_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int25_status_reg[] = 
-    {
-        {"smmu0_int25_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int25_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int25_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int25_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int25_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int25_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int25_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int25_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int25_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int25_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int25_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int25_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int25_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int25_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int25_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int25_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int25_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int25_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int25_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int25_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int25_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int25_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int25_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int25_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int25_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int25_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int25_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int25_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int25_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int25_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int25_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int25_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int26_en_reg[] = 
-    {
-        {"smmu0_int26_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int26_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int26_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int26_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int26_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int26_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int26_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int26_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int26_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int26_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int26_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int26_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int26_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int26_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int26_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int26_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int26_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int26_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int26_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int26_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int26_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int26_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int26_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int26_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int26_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int26_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int26_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int26_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int26_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int26_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int26_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int26_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int26_mask_reg[] = 
-    {
-        {"smmu0_int26_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int26_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int26_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int26_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int26_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int26_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int26_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int26_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int26_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int26_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int26_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int26_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int26_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int26_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int26_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int26_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int26_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int26_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int26_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int26_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int26_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int26_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int26_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int26_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int26_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int26_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int26_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int26_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int26_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int26_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int26_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int26_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int26_status_reg[] = 
-    {
-        {"smmu0_int26_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int26_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int26_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int26_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int26_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int26_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int26_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int26_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int26_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int26_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int26_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int26_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int26_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int26_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int26_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int26_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int26_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int26_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int26_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int26_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int26_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int26_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int26_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int26_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int26_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int26_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int26_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int26_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int26_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int26_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int26_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int26_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int27_en_reg[] = 
-    {
-        {"smmu0_int27_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int27_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int27_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int27_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int27_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int27_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int27_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int27_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int27_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int27_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int27_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int27_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int27_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int27_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int27_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int27_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int27_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int27_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int27_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int27_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int27_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int27_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int27_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int27_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int27_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int27_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int27_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int27_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int27_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int27_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int27_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int27_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int27_mask_reg[] = 
-    {
-        {"smmu0_int27_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int27_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int27_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int27_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int27_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int27_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int27_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int27_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int27_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int27_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int27_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int27_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int27_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int27_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int27_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int27_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int27_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int27_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int27_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int27_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int27_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int27_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int27_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int27_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int27_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int27_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int27_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int27_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int27_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int27_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int27_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int27_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int27_status_reg[] = 
-    {
-        {"smmu0_int27_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int27_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int27_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int27_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int27_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int27_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int27_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int27_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int27_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int27_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int27_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int27_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int27_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int27_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int27_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int27_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int27_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int27_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int27_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int27_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int27_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int27_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int27_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int27_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int27_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int27_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int27_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int27_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int27_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int27_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int27_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int27_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int28_en_reg[] = 
-    {
-        {"smmu0_int28_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int28_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int28_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int28_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int28_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int28_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int28_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int28_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int28_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int28_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int28_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int28_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int28_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int28_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int28_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int28_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int28_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int28_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int28_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int28_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int28_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int28_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int28_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int28_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int28_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int28_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int28_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int28_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int28_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int28_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int28_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int28_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int28_mask_reg[] = 
-    {
-        {"smmu0_int28_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int28_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int28_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int28_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int28_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int28_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int28_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int28_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int28_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int28_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int28_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int28_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int28_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int28_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int28_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int28_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int28_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int28_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int28_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int28_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int28_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int28_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int28_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int28_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int28_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int28_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int28_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int28_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int28_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int28_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int28_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int28_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int28_status_reg[] = 
-    {
-        {"smmu0_int28_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int28_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int28_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int28_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int28_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int28_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int28_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int28_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int28_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int28_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int28_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int28_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int28_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int28_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int28_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int28_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int28_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int28_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int28_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int28_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int28_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int28_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int28_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int28_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int28_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int28_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int28_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int28_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int28_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int28_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int28_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int28_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int29_en_reg[] = 
-    {
-        {"smmu0_int29_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int29_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int29_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int29_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int29_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int29_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int29_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int29_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int29_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int29_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int29_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int29_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int29_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int29_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int29_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int29_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int29_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int29_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int29_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int29_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int29_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int29_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int29_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int29_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int29_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int29_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int29_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int29_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int29_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int29_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int29_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int29_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int29_mask_reg[] = 
-    {
-        {"smmu0_int29_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int29_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int29_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int29_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int29_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int29_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int29_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int29_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int29_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int29_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int29_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int29_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int29_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int29_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int29_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int29_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int29_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int29_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int29_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int29_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int29_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int29_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int29_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int29_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int29_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int29_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int29_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int29_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int29_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int29_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int29_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int29_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int29_status_reg[] = 
-    {
-        {"smmu0_int29_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int29_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int29_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int29_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int29_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int29_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int29_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int29_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int29_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int29_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int29_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int29_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int29_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int29_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int29_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int29_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int29_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int29_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int29_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int29_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int29_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int29_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int29_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int29_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int29_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int29_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int29_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int29_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int29_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int29_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int29_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int29_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int30_en_reg[] = 
-    {
-        {"smmu0_int30_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int30_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int30_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int30_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int30_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int30_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int30_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int30_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int30_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int30_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int30_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int30_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int30_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int30_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int30_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int30_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int30_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int30_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int30_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int30_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int30_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int30_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int30_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int30_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int30_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int30_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int30_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int30_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int30_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int30_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int30_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int30_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int30_mask_reg[] = 
-    {
-        {"smmu0_int30_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int30_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int30_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int30_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int30_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int30_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int30_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int30_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int30_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int30_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int30_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int30_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int30_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int30_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int30_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int30_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int30_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int30_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int30_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int30_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int30_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int30_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int30_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int30_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int30_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int30_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int30_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int30_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int30_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int30_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int30_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int30_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int30_status_reg[] = 
-    {
-        {"smmu0_int30_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int30_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int30_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int30_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int30_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int30_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int30_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int30_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int30_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int30_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int30_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int30_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int30_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int30_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int30_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int30_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int30_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int30_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int30_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int30_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int30_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int30_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int30_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int30_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int30_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int30_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int30_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int30_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int30_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int30_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int30_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int30_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int31_en_reg[] = 
-    {
-        {"smmu0_int31_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int31_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int31_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int31_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int31_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int31_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int31_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int31_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int31_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int31_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int31_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int31_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int31_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int31_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int31_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int31_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int31_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int31_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int31_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int31_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int31_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int31_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int31_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int31_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int31_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int31_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int31_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int31_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int31_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int31_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int31_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int31_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int31_mask_reg[] = 
-    {
-        {"smmu0_int31_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int31_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int31_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int31_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int31_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int31_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int31_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int31_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int31_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int31_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int31_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int31_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int31_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int31_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int31_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int31_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int31_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int31_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int31_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int31_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int31_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int31_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int31_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int31_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int31_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int31_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int31_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int31_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int31_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int31_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int31_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int31_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int31_status_reg[] = 
-    {
-        {"smmu0_int31_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int31_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int31_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int31_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int31_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int31_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int31_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int31_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int31_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int31_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int31_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int31_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int31_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int31_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int31_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int31_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int31_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int31_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int31_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int31_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int31_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int31_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int31_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int31_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int31_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int31_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int31_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int31_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int31_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int31_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int31_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int31_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int32_en_reg[] = 
-    {
-        {"smmu0_int32_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int32_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int32_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int32_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int32_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int32_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int32_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int32_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int32_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int32_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int32_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int32_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int32_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int32_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int32_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int32_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int32_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int32_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int32_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int32_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int32_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int32_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int32_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int32_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int32_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int32_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int32_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int32_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int32_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int32_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int32_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int32_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int32_mask_reg[] = 
-    {
-        {"smmu0_int32_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int32_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int32_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int32_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int32_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int32_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int32_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int32_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int32_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int32_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int32_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int32_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int32_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int32_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int32_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int32_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int32_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int32_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int32_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int32_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int32_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int32_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int32_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int32_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int32_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int32_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int32_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int32_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int32_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int32_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int32_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int32_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int32_status_reg[] = 
-    {
-        {"smmu0_int32_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int32_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int32_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int32_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int32_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int32_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int32_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int32_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int32_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int32_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int32_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int32_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int32_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int32_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int32_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int32_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int32_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int32_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int32_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int32_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int32_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int32_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int32_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int32_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int32_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int32_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int32_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int32_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int32_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int32_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int32_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int32_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int33_en_reg[] = 
-    {
-        {"smmu0_int33_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int33_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int33_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int33_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int33_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int33_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int33_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int33_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int33_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int33_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int33_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int33_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int33_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int33_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int33_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int33_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int33_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int33_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int33_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int33_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int33_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int33_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int33_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int33_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int33_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int33_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int33_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int33_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int33_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int33_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int33_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int33_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int33_mask_reg[] = 
-    {
-        {"smmu0_int33_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int33_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int33_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int33_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int33_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int33_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int33_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int33_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int33_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int33_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int33_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int33_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int33_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int33_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int33_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int33_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int33_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int33_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int33_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int33_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int33_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int33_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int33_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int33_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int33_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int33_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int33_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int33_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int33_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int33_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int33_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int33_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int33_status_reg[] = 
-    {
-        {"smmu0_int33_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int33_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int33_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int33_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int33_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int33_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int33_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int33_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int33_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int33_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int33_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int33_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int33_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int33_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int33_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int33_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int33_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int33_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int33_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int33_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int33_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int33_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int33_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int33_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int33_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int33_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int33_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int33_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int33_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int33_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int33_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int33_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int34_en_reg[] = 
-    {
-        {"smmu0_int34_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int34_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int34_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int34_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int34_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int34_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int34_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int34_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int34_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int34_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int34_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int34_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int34_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int34_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int34_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int34_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int34_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int34_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int34_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int34_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int34_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int34_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int34_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int34_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int34_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int34_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int34_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int34_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int34_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int34_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int34_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int34_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int34_mask_reg[] = 
-    {
-        {"smmu0_int34_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"smmu0_int34_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"smmu0_int34_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"smmu0_int34_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"smmu0_int34_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"smmu0_int34_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"smmu0_int34_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"smmu0_int34_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"smmu0_int34_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"smmu0_int34_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"smmu0_int34_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"smmu0_int34_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"smmu0_int34_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"smmu0_int34_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"smmu0_int34_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"smmu0_int34_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"smmu0_int34_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"smmu0_int34_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"smmu0_int34_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"smmu0_int34_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"smmu0_int34_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"smmu0_int34_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"smmu0_int34_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"smmu0_int34_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"smmu0_int34_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"smmu0_int34_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"smmu0_int34_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"smmu0_int34_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"smmu0_int34_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int34_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int34_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int34_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int34_status_reg[] = 
-    {
-        {"smmu0_int34_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"smmu0_int34_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"smmu0_int34_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"smmu0_int34_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"smmu0_int34_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"smmu0_int34_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"smmu0_int34_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"smmu0_int34_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"smmu0_int34_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"smmu0_int34_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"smmu0_int34_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"smmu0_int34_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"smmu0_int34_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"smmu0_int34_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"smmu0_int34_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"smmu0_int34_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"smmu0_int34_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"smmu0_int34_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"smmu0_int34_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"smmu0_int34_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"smmu0_int34_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"smmu0_int34_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"smmu0_int34_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"smmu0_int34_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"smmu0_int34_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"smmu0_int34_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"smmu0_int34_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"smmu0_int34_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"smmu0_int34_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int34_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int34_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int34_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int35_en_reg[] = 
-    {
-        {"smmu0_int35_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int35_mask_reg[] = 
-    {
-        {"smmu0_int35_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int35_status_reg[] = 
-    {
-        {"smmu0_int35_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int36_en_reg[] = 
-    {
-        {"smmu0_int36_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int36_mask_reg[] = 
-    {
-        {"smmu0_int36_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int36_status_reg[] = 
-    {
-        {"smmu0_int36_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int37_en_reg[] = 
-    {
-        {"smmu0_int37_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int37_mask_reg[] = 
-    {
-        {"smmu0_int37_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int37_status_reg[] = 
-    {
-        {"smmu0_int37_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int38_en_reg[] = 
-    {
-        {"smmu0_int38_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int38_mask_reg[] = 
-    {
-        {"smmu0_int38_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int38_status_reg[] = 
-    {
-        {"smmu0_int38_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int39_en_reg[] = 
-    {
-        {"smmu0_int39_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int39_mask_reg[] = 
-    {
-        {"smmu0_int39_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int39_status_reg[] = 
-    {
-        {"smmu0_int39_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int40_en_reg[] = 
-    {
-        {"smmu0_int40_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int40_mask_reg[] = 
-    {
-        {"smmu0_int40_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int40_status_reg[] = 
-    {
-        {"smmu0_int40_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int41_en_reg[] = 
-    {
-        {"smmu0_int41_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int41_mask_reg[] = 
-    {
-        {"smmu0_int41_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int41_status_reg[] = 
-    {
-        {"smmu0_int41_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int42_en_reg[] = 
-    {
-        {"smmu0_int42_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int42_mask_reg[] = 
-    {
-        {"smmu0_int42_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int42_status_reg[] = 
-    {
-        {"smmu0_int42_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int43_en_reg[] = 
-    {
-        {"smmu0_int43_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int43_mask_reg[] = 
-    {
-        {"smmu0_int43_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int43_status_reg[] = 
-    {
-        {"smmu0_int43_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int44_en_reg[] = 
-    {
-        {"smmu0_int44_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int44_mask_reg[] = 
-    {
-        {"smmu0_int44_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int44_status_reg[] = 
-    {
-        {"smmu0_int44_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int45_en_reg[] = 
-    {
-        {"smmu0_int45_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int45_mask_reg[] = 
-    {
-        {"smmu0_int45_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int45_status_reg[] = 
-    {
-        {"smmu0_int45_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int46_en_reg[] = 
-    {
-        {"smmu0_int46_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int46_mask_reg[] = 
-    {
-        {"smmu0_int46_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int46_status_reg[] = 
-    {
-        {"smmu0_int46_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int47_en_reg[] = 
-    {
-        {"smmu0_int47_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int47_mask_reg[] = 
-    {
-        {"smmu0_int47_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int47_status_reg[] = 
-    {
-        {"smmu0_int47_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int48_en_reg[] = 
-    {
-        {"smmu0_int48_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int48_mask_reg[] = 
-    {
-        {"smmu0_int48_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int48_status_reg[] = 
-    {
-        {"smmu0_int48_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int49_en_reg[] = 
-    {
-        {"smmu0_int49_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int49_mask_reg[] = 
-    {
-        {"smmu0_int49_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int49_status_reg[] = 
-    {
-        {"smmu0_int49_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int50_en_reg[] = 
-    {
-        {"smmu0_int50_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int50_mask_reg[] = 
-    {
-        {"smmu0_int50_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int50_status_reg[] = 
-    {
-        {"smmu0_int50_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int51_en_reg[] = 
-    {
-        {"smmu0_int51_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int51_mask_reg[] = 
-    {
-        {"smmu0_int51_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int51_status_reg[] = 
-    {
-        {"smmu0_int51_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int52_en_reg[] = 
-    {
-        {"smmu0_int52_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int52_mask_reg[] = 
-    {
-        {"smmu0_int52_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int52_status_reg[] = 
-    {
-        {"smmu0_int52_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int53_en_reg[] = 
-    {
-        {"smmu0_int53_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int53_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int53_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int53_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int53_mask_reg[] = 
-    {
-        {"smmu0_int53_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"smmu0_int53_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"smmu0_int53_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_int53_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_int53_status_reg[] = 
-    {
-        {"smmu0_int53_status15", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_int53_status14", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_int53_status13", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_int53_status12", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl0_arbiter_ecc_bypass_reg[] = 
-    {
-        {"ctrl1_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"ctrl1_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"ctrl1_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"ctrl1_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"ctrl1_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"ctrl1_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"ctrl1_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"ctrl1_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"ctrl1_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"ctrl1_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"ctrl1_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"ctrl1_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"ctrl1_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"ctrl1_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"ctrl1_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"ctrl1_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"ctrl0_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"ctrl0_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"ctrl0_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"ctrl0_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"ctrl0_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"ctrl0_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"ctrl0_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"ctrl0_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"ctrl0_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"ctrl0_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"ctrl0_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"ctrl0_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"ctrl0_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"ctrl0_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"ctrl0_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"ctrl0_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl2_arbiter_ecc_bypass_reg[] = 
-    {
-        {"ctrl3_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"ctrl3_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"ctrl3_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"ctrl3_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"ctrl3_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"ctrl3_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"ctrl3_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"ctrl3_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"ctrl3_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"ctrl3_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"ctrl3_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"ctrl3_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"ctrl3_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"ctrl3_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"ctrl3_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"ctrl3_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"ctrl2_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"ctrl2_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"ctrl2_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"ctrl2_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"ctrl2_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"ctrl2_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"ctrl2_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"ctrl2_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"ctrl2_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"ctrl2_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"ctrl2_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"ctrl2_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"ctrl2_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"ctrl2_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"ctrl2_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"ctrl2_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl4_arbiter_ecc_bypass_reg[] = 
-    {
-        {"ctrl5_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"ctrl5_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"ctrl5_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"ctrl5_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"ctrl5_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"ctrl5_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"ctrl5_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"ctrl5_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"ctrl5_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"ctrl5_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"ctrl5_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"ctrl5_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"ctrl5_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"ctrl5_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"ctrl5_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"ctrl5_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"ctrl4_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"ctrl4_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"ctrl4_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"ctrl4_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"ctrl4_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"ctrl4_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"ctrl4_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"ctrl4_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"ctrl4_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"ctrl4_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"ctrl4_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"ctrl4_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"ctrl4_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"ctrl4_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"ctrl4_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"ctrl4_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl6_arbiter_ecc_bypass_reg[] = 
-    {
-        {"ctrl7_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"ctrl7_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"ctrl7_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"ctrl7_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"ctrl7_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"ctrl7_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"ctrl7_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"ctrl7_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"ctrl7_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"ctrl7_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"ctrl7_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"ctrl7_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"ctrl7_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"ctrl7_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"ctrl7_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"ctrl7_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"ctrl6_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"ctrl6_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"ctrl6_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"ctrl6_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"ctrl6_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"ctrl6_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"ctrl6_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"ctrl6_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"ctrl6_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"ctrl6_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"ctrl6_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"ctrl6_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"ctrl6_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"ctrl6_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"ctrl6_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"ctrl6_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl8_arbiter_ecc_bypass_reg[] = 
-    {
-        {"ctrl9_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"ctrl9_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"ctrl9_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"ctrl9_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"ctrl9_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"ctrl9_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"ctrl9_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"ctrl9_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"ctrl9_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"ctrl9_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"ctrl9_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"ctrl9_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"ctrl9_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"ctrl9_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"ctrl9_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"ctrl9_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"ctrl8_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"ctrl8_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"ctrl8_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"ctrl8_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"ctrl8_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"ctrl8_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"ctrl8_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"ctrl8_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"ctrl8_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"ctrl8_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"ctrl8_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"ctrl8_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"ctrl8_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"ctrl8_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"ctrl8_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"ctrl8_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl10_arbiter_ecc_bypass_reg[] = 
-    {
-        {"ctrl11_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"ctrl11_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"ctrl11_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"ctrl11_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"ctrl11_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"ctrl11_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"ctrl11_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"ctrl11_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"ctrl11_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"ctrl11_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"ctrl11_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"ctrl11_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"ctrl11_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"ctrl11_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"ctrl11_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"ctrl11_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"ctrl10_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"ctrl10_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"ctrl10_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"ctrl10_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"ctrl10_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"ctrl10_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"ctrl10_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"ctrl10_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"ctrl10_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"ctrl10_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"ctrl10_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"ctrl10_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"ctrl10_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"ctrl10_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"ctrl10_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"ctrl10_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl12_arbiter_ecc_bypass_reg[] = 
-    {
-        {"ctrl13_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"ctrl13_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"ctrl13_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"ctrl13_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"ctrl13_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"ctrl13_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"ctrl13_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"ctrl13_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"ctrl13_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"ctrl13_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"ctrl13_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"ctrl13_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"ctrl13_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"ctrl13_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"ctrl13_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"ctrl13_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"ctrl12_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"ctrl12_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"ctrl12_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"ctrl12_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"ctrl12_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"ctrl12_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"ctrl12_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"ctrl12_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"ctrl12_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"ctrl12_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"ctrl12_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"ctrl12_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"ctrl12_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"ctrl12_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"ctrl12_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"ctrl12_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl14_arbiter_ecc_bypass_reg[] = 
-    {
-        {"ctrl15_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"ctrl15_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"ctrl15_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"ctrl15_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"ctrl15_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"ctrl15_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"ctrl15_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"ctrl15_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"ctrl15_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"ctrl15_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"ctrl15_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"ctrl15_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"ctrl15_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"ctrl15_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"ctrl15_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"ctrl15_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"ctrl14_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"ctrl14_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"ctrl14_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"ctrl14_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"ctrl14_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"ctrl14_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"ctrl14_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"ctrl14_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"ctrl14_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"ctrl14_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"ctrl14_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"ctrl14_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"ctrl14_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"ctrl14_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"ctrl14_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"ctrl14_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl16_arbiter_ecc_bypass_reg[] = 
-    {
-        {"ctrl17_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"ctrl17_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"ctrl17_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"ctrl17_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"ctrl17_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"ctrl17_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"ctrl17_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"ctrl17_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"ctrl17_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"ctrl17_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"ctrl17_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"ctrl17_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"ctrl17_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"ctrl17_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"ctrl17_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"ctrl17_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"ctrl16_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"ctrl16_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"ctrl16_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"ctrl16_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"ctrl16_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"ctrl16_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"ctrl16_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"ctrl16_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"ctrl16_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"ctrl16_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"ctrl16_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"ctrl16_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"ctrl16_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"ctrl16_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"ctrl16_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"ctrl16_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl18_arbiter_ecc_bypass_reg[] = 
-    {
-        {"ctrl19_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"ctrl19_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"ctrl19_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"ctrl19_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"ctrl19_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"ctrl19_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"ctrl19_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"ctrl19_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"ctrl19_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"ctrl19_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"ctrl19_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"ctrl19_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"ctrl19_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"ctrl19_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"ctrl19_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"ctrl19_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"ctrl18_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"ctrl18_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"ctrl18_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"ctrl18_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"ctrl18_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"ctrl18_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"ctrl18_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"ctrl18_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"ctrl18_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"ctrl18_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"ctrl18_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"ctrl18_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"ctrl18_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"ctrl18_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"ctrl18_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"ctrl18_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl20_arbiter_ecc_bypass_reg[] = 
-    {
-        {"ctrl21_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"ctrl21_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"ctrl21_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"ctrl21_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"ctrl21_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"ctrl21_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"ctrl21_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"ctrl21_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"ctrl21_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"ctrl21_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"ctrl21_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"ctrl21_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"ctrl21_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"ctrl21_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"ctrl21_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"ctrl21_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"ctrl20_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"ctrl20_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"ctrl20_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"ctrl20_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"ctrl20_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"ctrl20_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"ctrl20_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"ctrl20_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"ctrl20_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"ctrl20_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"ctrl20_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"ctrl20_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"ctrl20_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"ctrl20_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"ctrl20_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"ctrl20_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl22_arbiter_ecc_bypass_reg[] = 
-    {
-        {"ctrl23_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"ctrl23_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"ctrl23_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"ctrl23_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"ctrl23_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"ctrl23_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"ctrl23_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"ctrl23_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"ctrl23_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"ctrl23_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"ctrl23_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"ctrl23_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"ctrl23_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"ctrl23_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"ctrl23_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"ctrl23_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"ctrl22_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"ctrl22_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"ctrl22_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"ctrl22_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"ctrl22_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"ctrl22_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"ctrl22_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"ctrl22_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"ctrl22_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"ctrl22_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"ctrl22_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"ctrl22_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"ctrl22_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"ctrl22_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"ctrl22_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"ctrl22_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl24_arbiter_ecc_bypass_reg[] = 
-    {
-        {"ctrl25_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"ctrl25_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"ctrl25_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"ctrl25_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"ctrl25_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"ctrl25_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"ctrl25_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"ctrl25_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"ctrl25_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"ctrl25_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"ctrl25_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"ctrl25_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"ctrl25_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"ctrl25_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"ctrl25_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"ctrl25_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"ctrl24_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"ctrl24_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"ctrl24_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"ctrl24_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"ctrl24_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"ctrl24_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"ctrl24_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"ctrl24_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"ctrl24_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"ctrl24_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"ctrl24_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"ctrl24_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"ctrl24_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"ctrl24_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"ctrl24_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"ctrl24_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl26_arbiter_ecc_bypass_reg[] = 
-    {
-        {"ctrl27_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"ctrl27_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"ctrl27_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"ctrl27_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"ctrl27_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"ctrl27_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"ctrl27_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"ctrl27_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"ctrl27_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"ctrl27_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"ctrl27_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"ctrl27_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"ctrl27_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"ctrl27_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"ctrl27_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"ctrl27_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"ctrl26_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"ctrl26_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"ctrl26_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"ctrl26_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"ctrl26_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"ctrl26_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"ctrl26_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"ctrl26_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"ctrl26_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"ctrl26_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"ctrl26_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"ctrl26_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"ctrl26_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"ctrl26_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"ctrl26_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"ctrl26_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl28_arbiter_ecc_bypass_reg[] = 
-    {
-        {"ctrl29_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"ctrl29_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"ctrl29_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"ctrl29_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"ctrl29_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"ctrl29_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"ctrl29_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"ctrl29_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"ctrl29_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"ctrl29_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"ctrl29_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"ctrl29_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"ctrl29_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"ctrl29_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"ctrl29_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"ctrl29_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"ctrl28_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"ctrl28_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"ctrl28_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"ctrl28_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"ctrl28_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"ctrl28_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"ctrl28_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"ctrl28_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"ctrl28_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"ctrl28_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"ctrl28_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"ctrl28_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"ctrl28_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"ctrl28_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"ctrl28_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"ctrl28_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl30_arbiter_ecc_bypass_reg[] = 
-    {
-        {"ctrl31_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0},
-        {"ctrl31_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0},
-        {"ctrl31_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0},
-        {"ctrl31_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0},
-        {"ctrl31_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0},
-        {"ctrl31_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0},
-        {"ctrl31_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0},
-        {"ctrl31_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0},
-        {"ctrl31_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0},
-        {"ctrl31_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0},
-        {"ctrl31_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0},
-        {"ctrl31_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0},
-        {"ctrl31_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0},
-        {"ctrl31_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0},
-        {"ctrl31_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0},
-        {"ctrl31_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0},
-        {"ctrl30_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0},
-        {"ctrl30_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0},
-        {"ctrl30_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0},
-        {"ctrl30_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0},
-        {"ctrl30_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0},
-        {"ctrl30_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0},
-        {"ctrl30_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0},
-        {"ctrl30_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0},
-        {"ctrl30_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0},
-        {"ctrl30_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0},
-        {"ctrl30_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0},
-        {"ctrl30_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0},
-        {"ctrl30_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0},
-        {"ctrl30_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0},
-        {"ctrl30_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"ctrl30_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl_req_ecc_bypass_reg[] = 
-    {
-        {"ctrl_req_ecc_bypass_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl_info_ecc_bypass_reg[] = 
-    {
-        {"ctrl_info_ecc_bypass_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_rschd_ecc_bypass_reg[] = 
-    {
-        {"smmu0_rschd_ecc_bypass_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_wr_ecc_bypass_reg[] = 
-    {
-        {"smmu0_wr_ecc_bypass1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0},
-        {"smmu0_wr_ecc_bypass0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl0_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl0_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl0_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl1_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl1_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl1_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl2_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl2_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl2_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl3_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl3_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl3_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl4_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl4_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl4_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl5_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl5_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl5_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl6_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl6_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl6_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl7_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl7_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl7_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl8_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl8_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl8_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl9_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl9_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl9_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl10_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl10_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl10_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl11_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl11_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl11_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl12_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl12_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl12_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl13_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl13_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl13_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl14_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl14_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl14_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl15_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl15_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl15_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl16_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl16_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl16_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl17_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl17_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl17_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl18_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl18_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl18_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl19_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl19_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl19_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl20_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl20_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl20_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl21_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl21_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl21_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl22_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl22_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl22_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl23_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl23_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl23_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl24_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl24_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl24_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl25_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl25_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl25_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl26_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl26_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl26_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl27_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl27_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl27_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl28_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl28_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl28_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl29_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl29_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl29_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl30_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl30_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl30_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl31_arbiter_ecc_err_reg[] = 
-    {
-        {"ctrl31_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"ctrl31_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl_req_ecc_single_err_reg[] = 
-    {
-        {"ctrl_req_ecc_single_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl_req_ecc_double_err_reg[] = 
-    {
-        {"ctrl_req_ecc_double_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl_info_ecc_single_err_reg[] = 
-    {
-        {"ctrl_info_ecc_single_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl_info_ecc_double_err_reg[] = 
-    {
-        {"ctrl_info_ecc_double_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_wr_ecc_err_reg[] = 
-    {
-        {"smmu0_wr_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"smmu0_wr_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"smmu0_wr_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"smmu0_wr_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_rschd_ecc_single_err_reg[] = 
-    {
-        {"smmu0_rschd_ecc_single_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_rschd_ecc_double_err_reg[] = 
-    {
-        {"smmu0_rschd_ecc_double_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ord_fifo_empty_reg[] = 
-    {
-        {"ord_fifo_empty", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_wr_arb_fifo_empty_reg[] = 
-    {
-        {"wr_arb_fifo_empty", DPP_FIELD_FLAG_RO, 3, 4, 0xf, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty0_reg[] = 
-    {
-        {"ctrl_fifo_empty0_5", DPP_FIELD_FLAG_RO, 29, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty0_4", DPP_FIELD_FLAG_RO, 24, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty0_3", DPP_FIELD_FLAG_RO, 19, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty0_2", DPP_FIELD_FLAG_RO, 14, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty0_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty0_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty1_reg[] = 
-    {
-        {"ctrl_fifo_empty1_5", DPP_FIELD_FLAG_RO, 29, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty1_4", DPP_FIELD_FLAG_RO, 24, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty1_3", DPP_FIELD_FLAG_RO, 19, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty1_2", DPP_FIELD_FLAG_RO, 14, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty1_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty1_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty2_reg[] = 
-    {
-        {"ctrl_fifo_empty2_5", DPP_FIELD_FLAG_RO, 29, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty2_4", DPP_FIELD_FLAG_RO, 24, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty2_3", DPP_FIELD_FLAG_RO, 19, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty2_2", DPP_FIELD_FLAG_RO, 14, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty2_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty2_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty3_reg[] = 
-    {
-        {"ctrl_fifo_empty3_5", DPP_FIELD_FLAG_RO, 29, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty3_4", DPP_FIELD_FLAG_RO, 24, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty3_3", DPP_FIELD_FLAG_RO, 19, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty3_2", DPP_FIELD_FLAG_RO, 14, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty3_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty3_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty4_reg[] = 
-    {
-        {"ctrl_fifo_empty4_5", DPP_FIELD_FLAG_RO, 29, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty4_4", DPP_FIELD_FLAG_RO, 24, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty4_3", DPP_FIELD_FLAG_RO, 19, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty4_2", DPP_FIELD_FLAG_RO, 14, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty4_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty4_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty5_reg[] = 
-    {
-        {"ctrl_fifo_empty5_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0},
-        {"ctrl_fifo_empty5_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty0_reg[] = 
-    {
-        {"kschd_fifo_empty0", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty1_reg[] = 
-    {
-        {"kschd_fifo_empty1", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty2_reg[] = 
-    {
-        {"kschd_fifo_empty2", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty3_reg[] = 
-    {
-        {"kschd_fifo_empty3", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty4_reg[] = 
-    {
-        {"kschd_fifo_empty4", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty5_reg[] = 
-    {
-        {"kschd_fifo_empty5", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty6_reg[] = 
-    {
-        {"kschd_fifo_empty6", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty7_reg[] = 
-    {
-        {"kschd_fifo_empty7", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty8_reg[] = 
-    {
-        {"kschd_fifo_empty8", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty9_reg[] = 
-    {
-        {"kschd_fifo_empty9", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty10_reg[] = 
-    {
-        {"kschd_fifo_empty10", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty11_reg[] = 
-    {
-        {"kschd_fifo_empty11", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty12_reg[] = 
-    {
-        {"kschd_fifo_empty12", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty13_reg[] = 
-    {
-        {"kschd_fifo_empty13", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty14_reg[] = 
-    {
-        {"kschd_fifo_empty14", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty15_reg[] = 
-    {
-        {"kschd_fifo_empty15", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty16_reg[] = 
-    {
-        {"kschd_fifo_empty16", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty17_reg[] = 
-    {
-        {"kschd_fifo_empty17", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty18_reg[] = 
-    {
-        {"kschd_fifo_empty18", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty19_reg[] = 
-    {
-        {"kschd_fifo_empty19", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty20_reg[] = 
-    {
-        {"kschd_fifo_empty20", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty21_reg[] = 
-    {
-        {"kschd_fifo_empty21", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty22_reg[] = 
-    {
-        {"kschd_fifo_empty22", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty23_reg[] = 
-    {
-        {"kschd_fifo_empty23", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty24_reg[] = 
-    {
-        {"kschd_fifo_empty24", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty25_reg[] = 
-    {
-        {"kschd_fifo_empty25", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty26_reg[] = 
-    {
-        {"kschd_fifo_empty26", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty27_reg[] = 
-    {
-        {"kschd_fifo_empty27", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty28_reg[] = 
-    {
-        {"kschd_fifo_empty28", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty29_reg[] = 
-    {
-        {"kschd_fifo_empty29", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty30_reg[] = 
-    {
-        {"kschd_fifo_empty30", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty31_reg[] = 
-    {
-        {"kschd_fifo_empty31", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty0_reg[] = 
-    {
-        {"rschd_fifo_empty0", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty1_reg[] = 
-    {
-        {"rschd_fifo_empty1", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty2_reg[] = 
-    {
-        {"rschd_fifo_empty2", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty3_reg[] = 
-    {
-        {"rschd_fifo_empty3", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty4_reg[] = 
-    {
-        {"rschd_fifo_empty4", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty5_reg[] = 
-    {
-        {"rschd_fifo_empty5", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty6_reg[] = 
-    {
-        {"rschd_fifo_empty6", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty7_reg[] = 
-    {
-        {"rschd_fifo_empty7", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty8_reg[] = 
-    {
-        {"rschd_fifo_empty8", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty9_reg[] = 
-    {
-        {"rschd_fifo_empty9", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty10_reg[] = 
-    {
-        {"rschd_fifo_empty10", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty11_reg[] = 
-    {
-        {"rschd_fifo_empty11", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty12_reg[] = 
-    {
-        {"rschd_fifo_empty12", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty13_reg[] = 
-    {
-        {"rschd_fifo_empty13", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty14_reg[] = 
-    {
-        {"rschd_fifo_empty14", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty15_reg[] = 
-    {
-        {"rschd_fifo_empty15", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty16_reg[] = 
-    {
-        {"rschd_fifo_empty16", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty17_reg[] = 
-    {
-        {"rschd_fifo_empty17", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty18_reg[] = 
-    {
-        {"rschd_fifo_empty18", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty19_reg[] = 
-    {
-        {"rschd_fifo_empty19", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty20_reg[] = 
-    {
-        {"rschd_fifo_empty20", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty21_reg[] = 
-    {
-        {"rschd_fifo_empty21", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty22_reg[] = 
-    {
-        {"rschd_fifo_empty22", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty23_reg[] = 
-    {
-        {"rschd_fifo_empty23", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty24_reg[] = 
-    {
-        {"rschd_fifo_empty24", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty25_reg[] = 
-    {
-        {"rschd_fifo_empty25", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty26_reg[] = 
-    {
-        {"rschd_fifo_empty26", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty27_reg[] = 
-    {
-        {"rschd_fifo_empty27", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty28_reg[] = 
-    {
-        {"rschd_fifo_empty28", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty29_reg[] = 
-    {
-        {"rschd_fifo_empty29", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty30_reg[] = 
-    {
-        {"rschd_fifo_empty30", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty31_reg[] = 
-    {
-        {"rschd_fifo_empty31", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ept_flag_reg[] = 
-    {
-        {"ept_flag8", DPP_FIELD_FLAG_RO, 8, 1, 0x1, 0x0},
-        {"ept_flag7", DPP_FIELD_FLAG_RO, 7, 1, 0x1, 0x0},
-        {"ept_flag6", DPP_FIELD_FLAG_RO, 6, 1, 0x1, 0x0},
-        {"ept_flag5", DPP_FIELD_FLAG_RO, 5, 1, 0x1, 0x0},
-        {"ept_flag4", DPP_FIELD_FLAG_RO, 4, 1, 0x1, 0x0},
-        {"ept_flag3", DPP_FIELD_FLAG_RO, 3, 1, 0x1, 0x0},
-        {"ept_flag2", DPP_FIELD_FLAG_RO, 2, 1, 0x1, 0x0},
-        {"ept_flag1", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0},
-        {"ept_flag0", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ppu_soft_rst_reg[] = 
-    {
-        {"ppu_soft_rst", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_as_mac_age_fc_cnt_reg[] = 
-    {
-        {"smmu0_as_mac_age_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_marc_se_parser_fc_cnt_reg[] = 
-    {
-        {"smmu0_marc_se_parser_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_wr_arb_cpu_fc_cnt_reg[] = 
-    {
-        {"wr_arb_cpu_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_lpm_as_fc_cnt_reg[] = 
-    {
-        {"smmu0_lpm_as_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_lpm_as_smmu0_fc_cnt_reg[] = 
-    {
-        {"lpm_as_smmu0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_etcam1_0_as_fc_cnt_reg[] = 
-    {
-        {"smmu0_etcam1_0_as_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_as_etcam1_0_smmu0_fc_cnt_reg[] = 
-    {
-        {"as_etcam1_0_smmu0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_ppu_mcast_fc_cnt_reg[] = 
-    {
-        {"smmu0_ppu_mcast_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ppu_smmu0_mcast_fc_cnt_reg[] = 
-    {
-        {"ppu_smmu0_mcast_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_odma_smmu0_tdm_fc_rsp_fc_cnt_reg[] = 
-    {
-        {"odma_smmu0_tdm_fc_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_odma_tdm_fc_key_fc_cnt_reg[] = 
-    {
-        {"smmu0_odma_tdm_fc_key_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_odma_fc_cnt_reg[] = 
-    {
-        {"smmu0_odma_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_cfg_tab_rd_fc_cnt_reg[] = 
-    {
-        {"smmu0_cfg_tab_rd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_stat_fc15_0_cnt_reg[] = 
-    {
-        {"smmu0_stat_fc15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_stat_smmu0_fc15_0_cnt_reg[] = 
-    {
-        {"stat_smmu0_fc15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_ppu_mex5_0_fc_cnt_reg[] = 
-    {
-        {"smmu0_ppu_mex5_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ppu_smmu0_mex5_0_fc_cnt_reg[] = 
-    {
-        {"ppu_smmu0_mex5_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_as_smmu0_mac_age_req_cnt_reg[] = 
-    {
-        {"as_smmu0_mac_age_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_se_parser_smmu0_marc_key_cnt_reg[] = 
-    {
-        {"se_parser_smmu0_marc_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rdat_cnt_reg[] = 
-    {
-        {"cpu_ind_rdat_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rd_req_cnt_reg[] = 
-    {
-        {"cpu_ind_rd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cpu_ind_wr_req_cnt_reg[] = 
-    {
-        {"cpu_ind_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_plcr_rsp0_cnt_reg[] = 
-    {
-        {"smmu0_plcr_rsp0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_plcr_smmu0_req0_cnt_reg[] = 
-    {
-        {"plcr_smmu0_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_lpm_as_rsp_cnt_reg[] = 
-    {
-        {"smmu0_lpm_as_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_lpm_as_smmu0_req_cnt_reg[] = 
-    {
-        {"lpm_as_smmu0_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_etcam1_0_as_rsp_cnt_reg[] = 
-    {
-        {"smmu0_etcam1_0_as_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_etcam1_0_as_smmu0_req_cnt_reg[] = 
-    {
-        {"etcam1_0_as_smmu0_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_ppu_mcast_rsp_cnt_reg[] = 
-    {
-        {"smmu0_ppu_mcast_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ppu_smmu0_mcast_key_cnt_reg[] = 
-    {
-        {"ppu_smmu0_mcast_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_odma_tdm_mc_rsp_cnt_reg[] = 
-    {
-        {"smmu0_odma_tdm_mc_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_odma_smmu0_tdm_mc_key_cnt_reg[] = 
-    {
-        {"odma_smmu0_tdm_mc_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_odma_rsp_cnt_reg[] = 
-    {
-        {"smmu0_odma_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_odma_smmu0_cmd_cnt_reg[] = 
-    {
-        {"odma_smmu0_cmd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_cfg_tab_rdat_cnt_reg[] = 
-    {
-        {"smmu0_cfg_tab_rdat_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_cfg_smmu0_tab_rd_cnt_reg[] = 
-    {
-        {"cfg_smmu0_tab_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_stat_rsp15_0_cnt_reg[] = 
-    {
-        {"smmu0_stat_rsp15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_stat_smmu0_req15_0_cnt_reg[] = 
-    {
-        {"stat_smmu0_req15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_smmu0_ppu_mex5_0_rsp_cnt_reg[] = 
-    {
-        {"smmu0_ppu_mex5_0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ppu_smmu0_mex5_0_key_cnt_reg[] = 
-    {
-        {"ppu_smmu0_mex5_0_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ftm_stat_smmu0_req0_cnt_reg[] = 
-    {
-        {"ftm_stat_smmu0_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_ftm_stat_smmu0_req1_cnt_reg[] = 
-    {
-        {"ftm_stat_smmu0_req1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_etm_stat_smmu0_req0_cnt_reg[] = 
-    {
-        {"etm_stat_smmu0_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_etm_stat_smmu0_req1_cnt_reg[] = 
-    {
-        {"etm_stat_smmu0_req1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_req_eram0_31_rd_cnt_reg[] = 
-    {
-        {"req_eram0_31_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu0_smmu0_req_eram0_31_wr_cnt_reg[] = 
-    {
-        {"req_eram0_31_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_wdat1_reg[] = 
-    {
-        {"ddr_wdat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_wdat2_reg[] = 
-    {
-        {"ddr_wdat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_wdat3_reg[] = 
-    {
-        {"ddr_wdat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_wdat4_reg[] = 
-    {
-        {"ddr_wdat4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_wdat5_reg[] = 
-    {
-        {"ddr_wdat5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_wdat6_reg[] = 
-    {
-        {"ddr_wdat6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_wdat7_reg[] = 
-    {
-        {"ddr_wdat7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_wdat8_reg[] = 
-    {
-        {"ddr_wdat8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_wdat9_reg[] = 
-    {
-        {"ddr_wdat9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_wdat10_reg[] = 
-    {
-        {"ddr_wdat10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_wdat11_reg[] = 
-    {
-        {"ddr_wdat11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_wdat12_reg[] = 
-    {
-        {"ddr_wdat12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_wdat13_reg[] = 
-    {
-        {"ddr_wdat13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_wdat14_reg[] = 
-    {
-        {"ddr_wdat14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_wdat15_reg[] = 
-    {
-        {"ddr_wdat15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cnt_stat_cache_en_reg[] = 
-    {
-        {"cnt_stat_cache_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cnt_stat_cache_clr_reg[] = 
-    {
-        {"cnt_stat_cache_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cnt_stat_cache_req_63_32_reg[] = 
-    {
-        {"cnt_stat_cache_req_63_32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cnt_stat_cache_req_31_0_reg[] = 
-    {
-        {"cnt_stat_cache_req_31_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cnt_stat_cache_hit_63_32_reg[] = 
-    {
-        {"cnt_stat_cache_hit_63_32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cnt_stat_cache_hit_31_0_reg[] = 
-    {
-        {"cnt_stat_cache_hit_31_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_cmd0_reg[] = 
-    {
-        {"ecc_en", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"rw_len", DPP_FIELD_FLAG_RW, 21, 2, 0x0, 0x0},
-        {"baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_info_addr_reg[] = 
-    {
-        {"info_addr", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_cmd1_reg[] = 
-    {
-        {"rw_flag", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"rw_addr", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_clr_start_addr_reg[] = 
-    {
-        {"clr_start_addr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_clr_end_addr_reg[] = 
-    {
-        {"clr_end_addr", DPP_FIELD_FLAG_RW, 31, 32, 0xffffff, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_clr_tbl_en_reg[] = 
-    {
-        {"cfg_init_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"clr_tbl_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_debug_cnt_mode_reg[] = 
-    {
-        {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_init_done_reg[] = 
-    {
-        {"cache_init_done", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0},
-        {"clr_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"init_ok", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rsp_rd_done_reg[] = 
-    {
-        {"cpu_rsp_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ksch_oam_sp_en_reg[] = 
-    {
-        {"ksch_oam_sp_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cfg_cache_en_reg[] = 
-    {
-        {"cfg_cache_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cache_age_en_reg[] = 
-    {
-        {"cache_age_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rdat0_reg[] = 
-    {
-        {"cpu_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rdat1_reg[] = 
-    {
-        {"cpu_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rdat2_reg[] = 
-    {
-        {"cpu_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rdat3_reg[] = 
-    {
-        {"cpu_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rdat4_reg[] = 
-    {
-        {"cpu_rdat4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rdat5_reg[] = 
-    {
-        {"cpu_rdat5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rdat6_reg[] = 
-    {
-        {"cpu_rdat6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rdat7_reg[] = 
-    {
-        {"cpu_rdat7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rdat8_reg[] = 
-    {
-        {"cpu_rdat8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rdat9_reg[] = 
-    {
-        {"cpu_rdat9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rdat10_reg[] = 
-    {
-        {"cpu_rdat10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rdat11_reg[] = 
-    {
-        {"cpu_rdat11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rdat12_reg[] = 
-    {
-        {"cpu_rdat12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rdat13_reg[] = 
-    {
-        {"cpu_rdat13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rdat14_reg[] = 
-    {
-        {"cpu_rdat14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rdat15_reg[] = 
-    {
-        {"cpu_rdat15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ctrl_cpu_rd_rdy_reg[] = 
-    {
-        {"ctrl_cpu_rd_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_warbi_rdy_cfg_reg[] = 
-    {
-        {"cpu_warbi_rdy_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_dir_arbi_cpu_rpful_reg[] = 
-    {
-        {"smmu1_cfg_rpful", DPP_FIELD_FLAG_RW, 15, 8, 0x44, 0x0},
-        {"smmu1_cfg_wpful", DPP_FIELD_FLAG_RW, 7, 8, 0x44, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_dir_arbi_wpful_reg[] = 
-    {
-        {"smmu1_ser_wdir_pful", DPP_FIELD_FLAG_RW, 17, 10, 0x14a, 0x0},
-        {"smmu1_cfg_wdir_pful", DPP_FIELD_FLAG_RW, 7, 8, 0x22, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cfg_wr_arbi_pful0_reg[] = 
-    {
-        {"arbi_out_pful", DPP_FIELD_FLAG_RW, 17, 12, 0x71c, 0x0},
-        {"cpu_wr_pful", DPP_FIELD_FLAG_RW, 5, 6, 0x22, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cfg_wr_arbi_pful1_reg[] = 
-    {
-        {"tm_wr_pful", DPP_FIELD_FLAG_RW, 23, 12, 0x4d3, 0x0},
-        {"stat_wr_pful", DPP_FIELD_FLAG_RW, 11, 12, 0x555, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_wdone_pful_cfg_reg[] = 
-    {
-        {"smmu1_wdone_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7e1f8, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_stat_rate_cfg_cnt_reg[] = 
-    {
-        {"stat_rate_cfg_cnt", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ftm_rate_cfg_cnt_reg[] = 
-    {
-        {"ftm_rate_cfg_cnt", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_etm_rate_cfg_cnt_reg[] = 
-    {
-        {"etm_rate_cfg_cnt", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_dir_rate_cfg_cnt_reg[] = 
-    {
-        {"dir_rate_cfg_cnt", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_hash_rate_cfg_cnt_reg[] = 
-    {
-        {"hash_rate_cfg_cnt", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ftm_tbl_cfg_reg[] = 
-    {
-        {"ftm_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_v4_as_tbl_cfg_reg[] = 
-    {
-        {"lpm_v4_as_rsp_len", DPP_FIELD_FLAG_RW, 22, 2, 0x0, 0x0},
-        {"lpm_v4_as_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"lpm_v4_as_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_v4_tbl_cfg_reg[] = 
-    {
-        {"lpm_v4_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"lpm_v4_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"lpm_v4_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_v6_tbl_cfg_reg[] = 
-    {
-        {"lpm_v6_len", DPP_FIELD_FLAG_RO, 22, 2, 0x2, 0x0},
-        {"lpm_v6_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"lpm_v6_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_v6_as_tbl_cfg_reg[] = 
-    {
-        {"lpm_v6_as_rsp_len", DPP_FIELD_FLAG_RW, 22, 2, 0x0, 0x0},
-        {"lpm_v6_as_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"lpm_v6_as_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_dma_tbl_cfg_reg[] = 
-    {
-        {"dma_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_oam_tbl_cfg_reg[] = 
-    {
-        {"oam_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ctrl_rpar_cpu_pful_reg[] = 
-    {
-        {"ctrl_rpar_cpu_pful", DPP_FIELD_FLAG_RW, 7, 8, 0x44, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cfg_ksch_dir_pful_reg[] = 
-    {
-        {"cfg_ksch_dir_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3434, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cfg_ksch_hash_pful_reg[] = 
-    {
-        {"cfg_ksch_hash_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3030, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cfg_ksch_lpm_pful_reg[] = 
-    {
-        {"cfg_ksch_lpm_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3030, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cfg_ksch_lpm_as_pful_reg[] = 
-    {
-        {"cfg_ksch_lpm_as_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3030, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cfg_ksch_stat_pful_reg[] = 
-    {
-        {"cfg_ksch_stat_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3434, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cfg_ksch_tm_pful_reg[] = 
-    {
-        {"cfg_ksch_tm_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3232, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cfg_ksch_oam_pful_reg[] = 
-    {
-        {"cfg_ksch_oam_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x2a2a, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cfg_ksch_dma_pful_reg[] = 
-    {
-        {"cfg_ksch_dma_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x2727, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ctrl_wfifo_cfg_reg[] = 
-    {
-        {"ctrl_wfifo_cfg", DPP_FIELD_FLAG_RW, 9, 10, 0x18c, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_rsch_hash_ptr_cfg_reg[] = 
-    {
-        {"rsch_hash_ptr_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0xe, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_rsch_lpm_ptr_cfg_reg[] = 
-    {
-        {"rsch_lpm_ptr_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0xe, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_rsch_lpm_as_ptr_cfg_reg[] = 
-    {
-        {"rsch_lpm_as_ptr_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0xe, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_rsch_stat_ptr_cfg_reg[] = 
-    {
-        {"rsch_stat_ptr_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0xe, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_rsch_oam_ptr_cfg_reg[] = 
-    {
-        {"rsch_oam_ptr_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0x12, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_rschd_fifo_pept_cfg_reg[] = 
-    {
-        {"rschd_fifo_pept_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x204, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_dir_fifo_pful_cfg_reg[] = 
-    {
-        {"dir_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_hash_fifo_pful_cfg_reg[] = 
-    {
-        {"hash_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_fifo_pful_cfg_reg[] = 
-    {
-        {"lpm_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_as_fifo_pful_cfg_reg[] = 
-    {
-        {"lpm_as_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_stat_fifo_pful_cfg_reg[] = 
-    {
-        {"stat_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ftm_fifo_pful_cfg_reg[] = 
-    {
-        {"ftm_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_etm_fifo_pful_cfg_reg[] = 
-    {
-        {"etm_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_oam_fifo_pful_cfg_reg[] = 
-    {
-        {"oam_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_dma_fifo_pful_cfg_reg[] = 
-    {
-        {"dma_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cache_rsp_rr_fifo_cfg_reg[] = 
-    {
-        {"rr_pfull_assert0", DPP_FIELD_FLAG_RW, 11, 6, 0x14, 0x0},
-        {"rr_pfull_negate0", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr_rsp_rr_fifo_cfg_reg[] = 
-    {
-        {"rr_pfull_assert1", DPP_FIELD_FLAG_RW, 13, 7, 0x20, 0x0},
-        {"rr_pfull_negate1", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_cahce_fifo_cfg_reg[] = 
-    {
-        {"smmu1_cahce_fwft_fifo_pfull_assert", DPP_FIELD_FLAG_RW, 7, 4, 0x6, 0x0},
-        {"smmu1_cahce_fwft_fifo_pfull_negate", DPP_FIELD_FLAG_RW, 3, 4, 0x6, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cache_rsp_fifo_cfg_reg[] = 
-    {
-        {"rschd_fifo_pfull_assert", DPP_FIELD_FLAG_RW, 11, 6, 0x10, 0x0},
-        {"rschd_fifo_pfull_negate", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_test_state_reg[] = 
-    {
-        {"test_state", DPP_FIELD_FLAG_RW, 31, 32, 0x11111111, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cache_fifo_ept_reg[] = 
-    {
-        {"cache_fifo_ept", DPP_FIELD_FLAG_RO, 1, 2, 0x3, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_rr_fifo_ept_reg[] = 
-    {
-        {"rr_fifo_ept", DPP_FIELD_FLAG_RO, 1, 2, 0x3, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_wr_fifo_ept_reg[] = 
-    {
-        {"dir_arbi_ept", DPP_FIELD_FLAG_RO, 6, 7, 0x7f, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_wdone_fifo_ept_reg[] = 
-    {
-        {"wdone_fifo_ept", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_kschd_fifo_ept0_reg[] = 
-    {
-        {"kschd_fifo_ept0", DPP_FIELD_FLAG_RO, 14, 15, 0x7fff, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cash_fifo_ept_reg[] = 
-    {
-        {"cash_fifo_ept", DPP_FIELD_FLAG_RO, 1, 2, 0x3, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ctrl_fifo_ept_reg[] = 
-    {
-        {"ctrl_fifo_ept", DPP_FIELD_FLAG_RO, 2, 3, 0x7, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_rschd_ept3_reg[] = 
-    {
-        {"rschd_fifo_ept3", DPP_FIELD_FLAG_RO, 31, 32, 0xffffff, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_rschd_ept2_reg[] = 
-    {
-        {"rschd_fifo_ept2", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_rschd_ept1_reg[] = 
-    {
-        {"rschd_fifo_ept1", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_rschd_ept0_reg[] = 
-    {
-        {"rschd_fifo_ept0", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cash0_ecc_err_addr_reg[] = 
-    {
-        {"cash0_ecc_err_addr", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_arbi_cpu_wr_rdy_reg[] = 
-    {
-        {"arbi_cpu_wr_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_int_0_en_reg[] = 
-    {
-        {"smmu1_int_0_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_int_0_mask_reg[] = 
-    {
-        {"smmu1_int_0_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_int_1_en_reg[] = 
-    {
-        {"smmu1_int_1_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_int_1_mask_reg[] = 
-    {
-        {"smmu1_int_1_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_int_2_en_reg[] = 
-    {
-        {"smmu1_int_2_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_int_2_mask_reg[] = 
-    {
-        {"smmu1_int_2_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_int_3_en_reg[] = 
-    {
-        {"smmu1_int_3_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_int_3_mask_reg[] = 
-    {
-        {"smmu1_int_3_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_int_0_status_reg[] = 
-    {
-        {"smmu1_int_0_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_int_1_status_reg[] = 
-    {
-        {"smmu1_int_1_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_int_2_status_reg[] = 
-    {
-        {"smmu1_int_2_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_int_3_status_reg[] = 
-    {
-        {"smmu1_int_3_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_int_status_reg[] = 
-    {
-        {"smmu1_int_status", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ctrl_to_cash7_0_fc_cnt_reg[] = 
-    {
-        {"ctrl_to_cash7_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cash7_0_to_ctrl_req_cnt_reg[] = 
-    {
-        {"cash7_0_to_ctrl_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_rschd_to_cache7_fc_cnt_reg[] = 
-    {
-        {"rschd_to_cache7_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cash7_to_cache_rsp_cnt_reg[] = 
-    {
-        {"cash7_to_cache_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cash7_to_ctrl_fc_cnt_reg[] = 
-    {
-        {"cash7_to_ctrl_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ctrl_to_cash7_0_rsp_cnt_reg[] = 
-    {
-        {"ctrl_to_cash7_0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_kschd_to_cache7_0_req_cnt_reg[] = 
-    {
-        {"kschd_to_cache7_0_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cache7_0_to_kschd_fc_cnt_reg[] = 
-    {
-        {"cache7_0_to_kschd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_dma_to_smmu1_rd_req_cnt_reg[] = 
-    {
-        {"dma_to_smmu1_rd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_oam_to_kschd_req_cnt_reg[] = 
-    {
-        {"oam_to_kschd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_oam_rr_state_rsp_cnt_reg[] = 
-    {
-        {"oam_rr_state_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_oam_clash_info_cnt_reg[] = 
-    {
-        {"oam_clash_info_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_oam_to_rr_req_cnt_reg[] = 
-    {
-        {"oam_to_rr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_as_to_kschd_req_cnt_reg[] = 
-    {
-        {"lpm_as_to_kschd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_as_rr_state_rsp_cnt_reg[] = 
-    {
-        {"lpm_as_rr_state_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_as_clash_info_cnt_reg[] = 
-    {
-        {"lpm_as_clash_info_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_as_to_rr_req_cnt_reg[] = 
-    {
-        {"lpm_as_to_rr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_to_kschd_req_cnt_reg[] = 
-    {
-        {"lpm_to_kschd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_rr_state_rsp_cnt_reg[] = 
-    {
-        {"lpm_rr_state_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_clash_info_cnt_reg[] = 
-    {
-        {"lpm_clash_info_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_to_rr_req_cnt_reg[] = 
-    {
-        {"lpm_to_rr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_hash3_0_to_kschd_req_cnt_reg[] = 
-    {
-        {"hash3_0_to_kschd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_hash3_0_rr_state_rsp_cnt_reg[] = 
-    {
-        {"hash3_0_rr_state_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_hash3_0_clash_info_cnt_reg[] = 
-    {
-        {"hash3_0_clash_info_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_hash3_0_to_rr_req_cnt_reg[] = 
-    {
-        {"hash3_0_to_rr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_dir3_0_to_kschd_req_cnt_reg[] = 
-    {
-        {"dir3_0_to_kschd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_dir3_0_clash_info_cnt_reg[] = 
-    {
-        {"dir3_0_clash_info_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_dir_tbl_wr_req_cnt_reg[] = 
-    {
-        {"dir_tbl_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_warbi_to_dir_tbl_warbi_fc_cnt_reg[] = 
-    {
-        {"warbi_to_dir_tbl_warbi_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_dir3_0_to_bank_rr_req_cnt_reg[] = 
-    {
-        {"dir3_0_to_bank_rr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_kschd_to_dir3_0_fc_cnt_reg[] = 
-    {
-        {"kschd_to_dir3_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_dir3_0_rr_state_rsp_cnt_reg[] = 
-    {
-        {"dir3_0_rr_state_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_wr_done_to_warbi_fc_cnt_reg[] = 
-    {
-        {"wr_done_to_warbi_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_wr_done_ptr_req_cnt_reg[] = 
-    {
-        {"wr_done_ptr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ctrl7_0_to_warbi_fc_cnt_reg[] = 
-    {
-        {"ctrl7_0_to_warbi_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_warbi_to_ctrl7_0_wr_req_cnt_reg[] = 
-    {
-        {"warbi_to_ctrl7_0_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_warbi_to_cash7_0_wr_req_cnt_reg[] = 
-    {
-        {"warbi_to_cash7_0_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_warbi_to_cpu_wr_fc_cnt_reg[] = 
-    {
-        {"warbi_to_cpu_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_wr_req_cnt_reg[] = 
-    {
-        {"cpu_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ctrl7_0_to_cpu_rd_rsp_cnt_reg[] = 
-    {
-        {"ctrl7_0_to_cpu_rd_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_to_ctrl7_0_rd_req_cnt_reg[] = 
-    {
-        {"cpu_to_ctrl7_0_rd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_rd_dir_tbl_rsp_cnt_reg[] = 
-    {
-        {"cpu_rd_dir_tbl_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cpu_to_dir_tbl_rd_wr_req_cnt_reg[] = 
-    {
-        {"cpu_to_dir_tbl_rd_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_mmu_7_0_rsp_fc_cnt_reg[] = 
-    {
-        {"smmu1_to_mmu_7_0_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_mmu_7_0_to_smmu1_rd_rsp_cnt_reg[] = 
-    {
-        {"mmu_7_0_to_smmu1_rd_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_mmu_7_0_to_smmu1_rd_fc_cnt_reg[] = 
-    {
-        {"mmu_7_0_to_smmu1_rd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_mmu_7_rd_req_cnt_reg[] = 
-    {
-        {"smmu1_to_mmu_7_rd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_mmu_7_to_smmu1_wr_fc_cnt_reg[] = 
-    {
-        {"mmu_7_to_smmu1_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_mmu_7_0_wr_req_cnt_reg[] = 
-    {
-        {"smmu1_to_mmu_7_0_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_se_to_smmu1_wr_rsp_fc_cnt_reg[] = 
-    {
-        {"se_to_smmu1_wr_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_se_wr_rsp_cnt_reg[] = 
-    {
-        {"smmu1_to_se_wr_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ddr7_0_wr_rsp_cnt_reg[] = 
-    {
-        {"ddr7_0_wr_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_as_fc_cnt_reg[] = 
-    {
-        {"smmu1_to_as_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_as_to_smmu1_wr_req_cnt_reg[] = 
-    {
-        {"as_to_smmu1_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_se_parser_fc_cnt_reg[] = 
-    {
-        {"smmu1_to_se_parser_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_se_parser_to_smmu1_req_cnt_reg[] = 
-    {
-        {"se_parser_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_etm_wr_fc_cnt_reg[] = 
-    {
-        {"smmu1_to_etm_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_etm_wr_req_cnt_reg[] = 
-    {
-        {"etm_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_ftm_wr_fc_cnt_reg[] = 
-    {
-        {"smmu1_to_ftm_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ftm_wr_req_cnt_reg[] = 
-    {
-        {"ftm_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_state_wr_fc_cnt_reg[] = 
-    {
-        {"smmu1_to_state_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_state_wr_req_cnt_reg[] = 
-    {
-        {"state_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_se_to_dma_rsp_cnt_reg[] = 
-    {
-        {"se_to_dma_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_se_to_dma_fc_cnt_reg[] = 
-    {
-        {"se_to_dma_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_oam_to_smmu1_fc_cnt_reg[] = 
-    {
-        {"oam_to_smmu1_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_oam_rsp_cnt_reg[] = 
-    {
-        {"smmu1_to_oam_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_oam_fc_cnt_reg[] = 
-    {
-        {"smmu1_to_oam_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_oam_to_smmu1_req_cnt_reg[] = 
-    {
-        {"oam_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_etm_rsp_cnt_reg[] = 
-    {
-        {"smmu1_to_etm_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_ftm_rsp_cnt_reg[] = 
-    {
-        {"smmu1_to_ftm_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_etm_fc_cnt_reg[] = 
-    {
-        {"smmu1_to_etm_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_etm_to_smmu1_req_cnt_reg[] = 
-    {
-        {"etm_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_ftm_fc_cnt_reg[] = 
-    {
-        {"smmu1_to_ftm_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_ftm_to_smmu1_req_cnt_reg[] = 
-    {
-        {"ftm_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_stat_rsp_cnt_reg[] = 
-    {
-        {"smmu1_to_stat_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_stat_fc_cnt_reg[] = 
-    {
-        {"smmu1_to_stat_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_stat_to_smmu1_req_cnt_reg[] = 
-    {
-        {"stat_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_as_to_smmu1_fc_cnt_reg[] = 
-    {
-        {"lpm_as_to_smmu1_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_to_smmu1_fc_cnt_reg[] = 
-    {
-        {"lpm_to_smmu1_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_lpm_as_rsp_cnt_reg[] = 
-    {
-        {"smmu1_to_lpm_as_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_lpm_rsp_cnt_reg[] = 
-    {
-        {"smmu1_to_lpm_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_lpm_as_fc_cnt_reg[] = 
-    {
-        {"smmu1_to_lpm_as_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_lpm_fc_cnt_reg[] = 
-    {
-        {"smmu1_to_lpm_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_as_to_smmu1_req_cnt_reg[] = 
-    {
-        {"lpm_as_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_lpm_to_smmu1_req_cnt_reg[] = 
-    {
-        {"lpm_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_hash3_0_to_smmu1_fc_cnt_reg[] = 
-    {
-        {"hash3_0_to_smmu1_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_hash3_0_rsp_cnt_reg[] = 
-    {
-        {"smmu1_to_hash3_0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_hash3_0_fc_cnt_reg[] = 
-    {
-        {"smmu1_to_hash3_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_hash3_0_to_smmu1_cnt_reg[] = 
-    {
-        {"hash3_0_to_smmu1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_se_to_smmu1_dir3_0_rsp_fc_cnt_reg[] = 
-    {
-        {"se_to_smmu1_dir3_0_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_se_dir3_0_rsp_cnt_reg[] = 
-    {
-        {"smmu1_to_se_dir3_0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_smmu1_to_se_dir3_0_fc_cnt_reg[] = 
-    {
-        {"smmu1_to_se_dir3_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_se_to_smmu1_dir3_0_cnt_reg[] = 
-    {
-        {"se_to_smmu1_dir3_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_smmu1_cache7_0_to_rschd_rsp_cnt_reg[] = 
-    {
-        {"cache7_0_to_rschd_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_ddr_rw_addr_reg[] = 
-    {
-        {"ddr_wr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_ddr_rw_mode_reg[] = 
-    {
-        {"ddr_rw_flag", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"ddr_rw_mode", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cp_cmd_reg[] = 
-    {
-        {"stat_tbl_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cpu_ind_rd_done_reg[] = 
-    {
-        {"cpu_ind_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cpu_ind_rdat0_reg[] = 
-    {
-        {"cpu_ind_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cpu_ind_rdat1_reg[] = 
-    {
-        {"cpu_ind_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cpu_ind_rdat2_reg[] = 
-    {
-        {"cpu_ind_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cpu_ind_rdat3_reg[] = 
-    {
-        {"cpu_ind_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cpu_ddr_fifo_almful_reg[] = 
-    {
-        {"cpu_ddr_fifo_almful", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_debug_cnt_mode_reg[] = 
-    {
-        {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cmmu_pful_cfg_reg[] = 
-    {
-        {"alu_cmd_pful_negate", DPP_FIELD_FLAG_RW, 17, 9, 0xf8, 0x0},
-        {"alu_cmd_pful_assert", DPP_FIELD_FLAG_RW, 8, 9, 0xf8, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cmmu_stat_pful_cfg_reg[] = 
-    {
-        {"cmmu_stat_pful_negate", DPP_FIELD_FLAG_RW, 11, 6, 0x14, 0x0},
-        {"cmmu_stat_pful_assert", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_stat_overflow_mode_reg[] = 
-    {
-        {"stat_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cmmu_cp_fifo_pful_reg[] = 
-    {
-        {"cmmu_cp_fifo_pful", DPP_FIELD_FLAG_RW, 7, 8, 0x66, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_ddr_wr_dat0_reg[] = 
-    {
-        {"ddr_wr_dat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_ddr_wr_dat1_reg[] = 
-    {
-        {"ddr_wr_dat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cmmu_int_unmask_flag_reg[] = 
-    {
-        {"cmmu_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cmmu_int_en_reg[] = 
-    {
-        {"cmmu_int_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"cmmu_int_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"cmmu_int_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"cmmu_int_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"cmmu_int_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"cmmu_int_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"cmmu_int_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"cmmu_int_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"cmmu_int_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"cmmu_int_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"cmmu_int_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"cmmu_int_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"cmmu_int_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cmmu_int_mask_reg[] = 
-    {
-        {"cmmu_int_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"cmmu_int_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"cmmu_int_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"cmmu_int_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"cmmu_int_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"cmmu_int_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"cmmu_int_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"cmmu_int_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"cmmu_int_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"cmmu_int_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"cmmu_int_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"cmmu_int_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"cmmu_int_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cmmu_int_status_reg[] = 
-    {
-        {"cmmu_int_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"cmmu_int_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"cmmu_int_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"cmmu_int_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"cmmu_int_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"cmmu_int_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"cmmu_int_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"cmmu_int_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"cmmu_int_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"cmmu_int_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"cmmu_int_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"cmmu_int_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"cmmu_int_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_stat_cmmu_req_cnt_reg[] = 
-    {
-        {"stat_cmmu_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cmmu_fc0_cnt_reg[] = 
-    {
-        {"cmmu_stat_rdy", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cmmu_fc1_cnt_reg[] = 
-    {
-        {"smmu1_cmmu_wr_rdy", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_se_cmmu_cmmu_fc2_cnt_reg[] = 
-    {
-        {"smmu1_cmmu_rd_rdy", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl0_cfg_reg[] = 
-    {
-        {"hash0_tbl0_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash0_tbl0_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash0_tbl0_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl1_cfg_reg[] = 
-    {
-        {"hash0_tbl1_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash0_tbl1_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash0_tbl1_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl2_cfg_reg[] = 
-    {
-        {"hash0_tbl2_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash0_tbl2_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash0_tbl2_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl3_cfg_reg[] = 
-    {
-        {"hash0_tbl3_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash0_tbl3_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash0_tbl3_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl4_cfg_reg[] = 
-    {
-        {"hash0_tbl4_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash0_tbl4_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash0_tbl4_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl5_cfg_reg[] = 
-    {
-        {"hash0_tbl5_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash0_tbl5_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash0_tbl5_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl6_cfg_reg[] = 
-    {
-        {"hash0_tbl6_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash0_tbl6_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash0_tbl6_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl7_cfg_reg[] = 
-    {
-        {"hash0_tbl7_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash0_tbl7_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash0_tbl7_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl0_cfg_reg[] = 
-    {
-        {"hash1_tbl0_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash1_tbl0_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash1_tbl0_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl1_cfg_reg[] = 
-    {
-        {"hash1_tbl1_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash1_tbl1_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash1_tbl1_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl2_cfg_reg[] = 
-    {
-        {"hash1_tbl2_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash1_tbl2_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash1_tbl2_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl3_cfg_reg[] = 
-    {
-        {"hash1_tbl3_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash1_tbl3_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash1_tbl3_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl4_cfg_reg[] = 
-    {
-        {"hash1_tbl4_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash1_tbl4_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash1_tbl4_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl5_cfg_reg[] = 
-    {
-        {"hash1_tbl5_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash1_tbl5_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash1_tbl5_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl6_cfg_reg[] = 
-    {
-        {"hash1_tbl6_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash1_tbl6_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash1_tbl6_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl7_cfg_reg[] = 
-    {
-        {"hash1_tbl7_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash1_tbl7_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash1_tbl7_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl0_cfg_reg[] = 
-    {
-        {"hash2_tbl0_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash2_tbl0_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash2_tbl0_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl1_cfg_reg[] = 
-    {
-        {"hash2_tbl1_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash2_tbl1_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash2_tbl1_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl2_cfg_reg[] = 
-    {
-        {"hash2_tbl2_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash2_tbl2_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash2_tbl2_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl3_cfg_reg[] = 
-    {
-        {"hash2_tbl3_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash2_tbl3_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash2_tbl3_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl4_cfg_reg[] = 
-    {
-        {"hash2_tbl4_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash2_tbl4_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash2_tbl4_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl5_cfg_reg[] = 
-    {
-        {"hash2_tbl5_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash2_tbl5_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash2_tbl5_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl6_cfg_reg[] = 
-    {
-        {"hash2_tbl6_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash2_tbl6_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash2_tbl6_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl7_cfg_reg[] = 
-    {
-        {"hash2_tbl7_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash2_tbl7_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash2_tbl7_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl0_cfg_reg[] = 
-    {
-        {"hash3_tbl0_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash3_tbl0_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash3_tbl0_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl1_cfg_reg[] = 
-    {
-        {"hash3_tbl1_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash3_tbl1_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash3_tbl1_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl2_cfg_reg[] = 
-    {
-        {"hash3_tbl2_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash3_tbl2_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash3_tbl2_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl3_cfg_reg[] = 
-    {
-        {"hash3_tbl3_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash3_tbl3_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash3_tbl3_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl4_cfg_reg[] = 
-    {
-        {"hash3_tbl4_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash3_tbl4_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash3_tbl4_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl5_cfg_reg[] = 
-    {
-        {"hash3_tbl5_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash3_tbl5_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash3_tbl5_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl6_cfg_reg[] = 
-    {
-        {"hash3_tbl6_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash3_tbl6_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash3_tbl6_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl7_cfg_reg[] = 
-    {
-        {"hash3_tbl7_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0},
-        {"hash3_tbl7_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"hash3_tbl7_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_wdat1_reg[] = 
-    {
-        {"cpu_ind_eram_wdat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_wdat2_reg[] = 
-    {
-        {"cpu_ind_eram_wdat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_wdat3_reg[] = 
-    {
-        {"cpu_ind_eram_wdat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_req_info_reg[] = 
-    {
-        {"rw_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"read_mode", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0},
-        {"tm_cs", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0},
-        {"queue_cs", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0},
-        {"rw_addr", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_rd_done_reg[] = 
-    {
-        {"cpu_ind_eram_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_rdat0_reg[] = 
-    {
-        {"cpu_ind_eram_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_rdat1_reg[] = 
-    {
-        {"cpu_ind_eram_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_rdat2_reg[] = 
-    {
-        {"cpu_ind_eram_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_rdat3_reg[] = 
-    {
-        {"cpu_ind_eram_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_tm_alu_eram_cpu_rdy_reg[] = 
-    {
-        {"tm_alu_eram_cpu_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_oam_stat_cfg_reg[] = 
-    {
-        {"oam_flow_control_cfg", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"oam_lm_flow_control_cfg", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"oam_in_eram_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_ftm_port_sel_cfg_reg[] = 
-    {
-        {"ftm_port0_sel_cfg", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0},
-        {"ftm_port1_sel_cfg", DPP_FIELD_FLAG_RW, 14, 5, 0x1, 0x0},
-        {"ftm_port2_sel_cfg", DPP_FIELD_FLAG_RW, 9, 5, 0xf, 0x0},
-        {"ftm_port3_sel_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_oam_eram_base_addr_reg[] = 
-    {
-        {"oam_eram_base_addr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_oam_lm_eram_base_addr_reg[] = 
-    {
-        {"oam_lm_eram_base_addr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_oam_ddr_base_addr_reg[] = 
-    {
-        {"oam_ddr_base_addr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_plcr0_schd_pful_cfg_reg[] = 
-    {
-        {"plcr0_schd_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x2c, 0x0},
-        {"plcr0_schd_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x2c, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_oam_lm_ord_pful_cfg_reg[] = 
-    {
-        {"oam_lm_ord_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x28, 0x0},
-        {"oam_lm_ord_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x28, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_ddr_schd_pful_cfg_reg[] = 
-    {
-        {"ddr_schd_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x2c, 0x0},
-        {"ddr_schd_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x2c, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_eram_schd_pful_cfg_reg[] = 
-    {
-        {"eram_schd_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x28, 0x0},
-        {"eram_schd_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x28, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_eram_schd_pept_cfg_reg[] = 
-    {
-        {"eram_schd_pept_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x18, 0x0},
-        {"eram_schd_pept_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x18, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_eram_schd_oam_pful_cfg_reg[] = 
-    {
-        {"eram_schd_oam_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x28, 0x0},
-        {"eram_schd_oam_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x28, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_eram_schd_oam_pept_cfg_reg[] = 
-    {
-        {"eram_schd_oam_pept_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x18, 0x0},
-        {"eram_schd_oam_pept_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x18, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_eram_schd_oam_lm_pful_cfg_reg[] = 
-    {
-        {"eram_schd_oam_lm_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x28, 0x0},
-        {"eram_schd_oam_lm_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x28, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_eram_schd_oam_lm_pept_cfg_reg[] = 
-    {
-        {"eram_schd_oam_lm_pept_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x18, 0x0},
-        {"eram_schd_oam_lm_pept_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x18, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_rschd_pful_cfg_reg[] = 
-    {
-        {"rschd_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x24, 0x0},
-        {"rschd_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_rschd_pept_cfg_reg[] = 
-    {
-        {"rschd_pept_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x1c, 0x0},
-        {"rschd_pept_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x1c, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_rschd_plcr_pful_cfg_reg[] = 
-    {
-        {"rschd_plcr_pful_assert", DPP_FIELD_FLAG_RW, 15, 8, 0x40, 0x0},
-        {"rschd_plcr_pful_negate", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_rschd_plcr_pept_cfg_reg[] = 
-    {
-        {"rschd_plcr_pept_assert", DPP_FIELD_FLAG_RW, 15, 8, 0x40, 0x0},
-        {"rschd_plcr_pept_negate", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_rschd_plcr_info_pful_cfg_reg[] = 
-    {
-        {"rschd_plcr_info_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x38, 0x0},
-        {"rschd_plcr_info_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x38, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_alu_arb_cpu_pful_cfg_reg[] = 
-    {
-        {"alu_arb_cpu_pful_assert", DPP_FIELD_FLAG_RW, 9, 5, 0x08, 0x0},
-        {"alu_arb_cpu_pful_negate", DPP_FIELD_FLAG_RW, 4, 5, 0x08, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_alu_arb_user_pful_cfg_reg[] = 
-    {
-        {"alu_arb_user_pful_assert", DPP_FIELD_FLAG_RW, 9, 5, 0x0d, 0x0},
-        {"alu_arb_user_pful_negate", DPP_FIELD_FLAG_RW, 4, 5, 0x0d, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_alu_arb_stat_pful_cfg_reg[] = 
-    {
-        {"alu_arb_stat_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x20, 0x0},
-        {"alu_arb_stat_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cycmov_dat_pful_cfg_reg[] = 
-    {
-        {"cycmov_dat_pful_assert", DPP_FIELD_FLAG_RW, 9, 5, 0x0d, 0x0},
-        {"cycmov_dat_pful_negate", DPP_FIELD_FLAG_RW, 4, 5, 0x0d, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_ddr_opr_pful_cfg_reg[] = 
-    {
-        {"ddr_opr_pful_assert", DPP_FIELD_FLAG_RW, 9, 5, 0xc, 0x0},
-        {"ddr_opr_pful_negate", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cycle_mov_pful_cfg_reg[] = 
-    {
-        {"cycle_mov_pful_assert", DPP_FIELD_FLAG_RW, 11, 6, 0x1c, 0x0},
-        {"cycle_mov_pful_negate", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cntovf_pful_cfg_reg[] = 
-    {
-        {"cntovf_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x32, 0x0},
-        {"cntovf_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x32, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_eram_schd_plcr_pful_cfg_reg[] = 
-    {
-        {"eram_schd_plcr_pful_assert", DPP_FIELD_FLAG_RW, 15, 8, 0x40, 0x0},
-        {"eram_schd_plcr_pful_negate", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_eram_schd_plcr_pept_cfg_reg[] = 
-    {
-        {"eram_schd_plcr_pept_assert", DPP_FIELD_FLAG_RW, 15, 8, 0x40, 0x0},
-        {"eram_schd_plcr_pept_negate", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_debug_cnt_mode_reg[] = 
-    {
-        {"cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_tm_mov_period_cfg_reg[] = 
-    {
-        {"etm_mov_period_cfg", DPP_FIELD_FLAG_RW, 15, 8, 0x3c, 0x0},
-        {"ftm_mov_period_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x3c, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_alu_ddr_cpu_req_pful_cfg_reg[] = 
-    {
-        {"alu_ddr_cpu_req_pful_assert", DPP_FIELD_FLAG_RW, 7, 4, 0x4, 0x0},
-        {"alu_ddr_cpu_req_pful_negate", DPP_FIELD_FLAG_RW, 3, 4, 0x4, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cycmov_addr_pful_cfg_reg[] = 
-    {
-        {"cycmov_addr_pful_assert", DPP_FIELD_FLAG_RW, 9, 5, 0xd, 0x0},
-        {"cycmov_addr_pful_negate", DPP_FIELD_FLAG_RW, 4, 5, 0xd, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_ord_ddr_plcr_fifo_empty_reg[] = 
-    {
-        {"ord_oam_lm_empty", DPP_FIELD_FLAG_RO, 19, 1, 0x1, 0x0},
-        {"ddr_schd_fifo_empty", DPP_FIELD_FLAG_RO, 18, 7, 0x7f, 0x0},
-        {"plcr0_schd_fifo_empty", DPP_FIELD_FLAG_RO, 5, 6, 0x3f, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_tm_stat_fifo_empty_reg[] = 
-    {
-        {"tm_stat_fifo_empty", DPP_FIELD_FLAG_RO, 13, 14, 0x3fff, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_eram_schd_fifo_empty_0_1_reg[] = 
-    {
-        {"eram_schd_fifo_empty1", DPP_FIELD_FLAG_RO, 31, 16, 0xffff, 0x0},
-        {"eram_schd_fifo_empty0", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_eram_schd_fifo_empty_2_3_reg[] = 
-    {
-        {"eram_schd_fifo_empty3", DPP_FIELD_FLAG_RO, 31, 16, 0xffff, 0x0},
-        {"eram_schd_fifo_empty2", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_eram_schd_fifo_empty_4_5_reg[] = 
-    {
-        {"eram_schd_fifo_empty5", DPP_FIELD_FLAG_RO, 31, 16, 0xffff, 0x0},
-        {"eram_schd_fifo_empty4", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_eram_schd_fifo_empty_6_7_reg[] = 
-    {
-        {"eram_schd_fifo_empty7", DPP_FIELD_FLAG_RO, 31, 16, 0xffff, 0x0},
-        {"eram_schd_fifo_empty6", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_eram_schd_fifo_empty_free_8_reg[] = 
-    {
-        {"eram_schd_free_fifo_empty8", DPP_FIELD_FLAG_RO, 24, 1, 0x1, 0x0},
-        {"eram_schd_free_fifo_empty7", DPP_FIELD_FLAG_RO, 23, 1, 0x1, 0x0},
-        {"eram_schd_free_fifo_empty6", DPP_FIELD_FLAG_RO, 22, 1, 0x1, 0x0},
-        {"eram_schd_free_fifo_empty5", DPP_FIELD_FLAG_RO, 21, 1, 0x1, 0x0},
-        {"eram_schd_free_fifo_empty4", DPP_FIELD_FLAG_RO, 20, 1, 0x1, 0x0},
-        {"eram_schd_free_fifo_empty3", DPP_FIELD_FLAG_RO, 19, 1, 0x1, 0x0},
-        {"eram_schd_free_fifo_empty2", DPP_FIELD_FLAG_RO, 18, 1, 0x1, 0x0},
-        {"eram_schd_free_fifo_empty1", DPP_FIELD_FLAG_RO, 17, 1, 0x1, 0x0},
-        {"eram_schd_free_fifo_empty0", DPP_FIELD_FLAG_RO, 16, 1, 0x1, 0x0},
-        {"eram_schd_fifo_empty8", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_rschd_fifo_empty_0_3_reg[] = 
-    {
-        {"rschd_fifo_empty3", DPP_FIELD_FLAG_RO, 31, 8, 0xff, 0x0},
-        {"rschd_fifo_empty2", DPP_FIELD_FLAG_RO, 23, 8, 0xff, 0x0},
-        {"rschd_fifo_empty1", DPP_FIELD_FLAG_RO, 15, 8, 0xff, 0x0},
-        {"rschd_fifo_empty0", DPP_FIELD_FLAG_RO, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_rschd_fifo_empty_4_7_reg[] = 
-    {
-        {"rschd_fifo_empty7", DPP_FIELD_FLAG_RO, 31, 8, 0xff, 0x0},
-        {"rschd_fifo_empty6", DPP_FIELD_FLAG_RO, 23, 8, 0xff, 0x0},
-        {"rschd_fifo_empty5", DPP_FIELD_FLAG_RO, 15, 8, 0xff, 0x0},
-        {"rschd_fifo_empty4", DPP_FIELD_FLAG_RO, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_rschd_fifo_empty_8_11_reg[] = 
-    {
-        {"rschd_fifo_empty11", DPP_FIELD_FLAG_RO, 31, 8, 0xff, 0x0},
-        {"rschd_fifo_empty10", DPP_FIELD_FLAG_RO, 23, 8, 0xff, 0x0},
-        {"rschd_fifo_empty9", DPP_FIELD_FLAG_RO, 15, 8, 0xff, 0x0},
-        {"rschd_fifo_empty8", DPP_FIELD_FLAG_RO, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_rschd_fifo_empty_12_15_reg[] = 
-    {
-        {"rschd_fifo_empty15", DPP_FIELD_FLAG_RO, 31, 8, 0xff, 0x0},
-        {"rschd_fifo_empty14", DPP_FIELD_FLAG_RO, 23, 8, 0xff, 0x0},
-        {"rschd_fifo_empty13", DPP_FIELD_FLAG_RO, 15, 8, 0xff, 0x0},
-        {"rschd_fifo_empty12", DPP_FIELD_FLAG_RO, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_rschd_fifo_empty_plcr_16_17_reg[] = 
-    {
-        {"rschd_fifo_empty_plcr", DPP_FIELD_FLAG_RO, 16, 1, 0x1, 0x0},
-        {"rschd_fifo_empty17", DPP_FIELD_FLAG_RO, 15, 8, 0xff, 0x0},
-        {"rschd_fifo_empty16", DPP_FIELD_FLAG_RO, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int_unmask_flag_reg[] = 
-    {
-        {"stat_int5_unmask_flag", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0},
-        {"stat_int4_unmask_flag", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"stat_int3_unmask_flag", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"stat_int2_unmask_flag", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"stat_int1_unmask_flag", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"stat_int0_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int0_en_reg[] = 
-    {
-        {"stat_int0_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"stat_int0_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"stat_int0_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"stat_int0_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"stat_int0_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"stat_int0_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"stat_int0_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"stat_int0_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"stat_int0_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"stat_int0_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"stat_int0_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"stat_int0_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"stat_int0_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"stat_int0_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"stat_int0_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"stat_int0_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"stat_int0_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"stat_int0_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"stat_int0_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"stat_int0_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"stat_int0_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"stat_int0_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"stat_int0_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"stat_int0_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"stat_int0_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"stat_int0_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"stat_int0_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"stat_int0_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"stat_int0_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"stat_int0_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"stat_int0_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"stat_int0_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int0_mask_reg[] = 
-    {
-        {"stat_int0_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"stat_int0_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"stat_int0_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"stat_int0_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"stat_int0_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"stat_int0_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"stat_int0_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"stat_int0_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"stat_int0_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"stat_int0_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"stat_int0_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"stat_int0_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"stat_int0_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"stat_int0_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"stat_int0_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"stat_int0_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"stat_int0_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"stat_int0_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"stat_int0_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"stat_int0_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"stat_int0_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"stat_int0_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"stat_int0_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"stat_int0_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"stat_int0_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"stat_int0_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"stat_int0_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"stat_int0_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"stat_int0_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"stat_int0_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"stat_int0_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"stat_int0_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int0_status_reg[] = 
-    {
-        {"stat_int0_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"stat_int0_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"stat_int0_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"stat_int0_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"stat_int0_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"stat_int0_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"stat_int0_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"stat_int0_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"stat_int0_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"stat_int0_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"stat_int0_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"stat_int0_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"stat_int0_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"stat_int0_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"stat_int0_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"stat_int0_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"stat_int0_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"stat_int0_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"stat_int0_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"stat_int0_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"stat_int0_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"stat_int0_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"stat_int0_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"stat_int0_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"stat_int0_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"stat_int0_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"stat_int0_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"stat_int0_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"stat_int0_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"stat_int0_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"stat_int0_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"stat_int0_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int1_en_reg[] = 
-    {
-        {"stat_int1_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"stat_int1_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"stat_int1_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"stat_int1_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"stat_int1_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"stat_int1_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"stat_int1_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"stat_int1_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"stat_int1_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"stat_int1_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"stat_int1_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"stat_int1_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"stat_int1_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"stat_int1_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"stat_int1_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"stat_int1_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"stat_int1_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"stat_int1_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"stat_int1_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"stat_int1_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"stat_int1_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"stat_int1_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"stat_int1_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"stat_int1_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"stat_int1_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"stat_int1_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"stat_int1_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"stat_int1_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"stat_int1_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"stat_int1_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"stat_int1_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"stat_int1_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int1_mask_reg[] = 
-    {
-        {"stat_int1_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"stat_int1_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"stat_int1_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"stat_int1_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"stat_int1_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"stat_int1_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"stat_int1_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"stat_int1_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"stat_int1_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"stat_int1_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"stat_int1_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"stat_int1_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"stat_int1_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"stat_int1_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"stat_int1_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"stat_int1_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"stat_int1_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"stat_int1_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"stat_int1_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"stat_int1_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"stat_int1_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"stat_int1_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"stat_int1_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"stat_int1_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"stat_int1_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"stat_int1_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"stat_int1_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"stat_int1_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"stat_int1_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"stat_int1_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"stat_int1_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"stat_int1_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int1_status_reg[] = 
-    {
-        {"stat_int1_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"stat_int1_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"stat_int1_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"stat_int1_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"stat_int1_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"stat_int1_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"stat_int1_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"stat_int1_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"stat_int1_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"stat_int1_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"stat_int1_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"stat_int1_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"stat_int1_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"stat_int1_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"stat_int1_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"stat_int1_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"stat_int1_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"stat_int1_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"stat_int1_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"stat_int1_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"stat_int1_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"stat_int1_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"stat_int1_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"stat_int1_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"stat_int1_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"stat_int1_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"stat_int1_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"stat_int1_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"stat_int1_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"stat_int1_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"stat_int1_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"stat_int1_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int2_en_reg[] = 
-    {
-        {"stat_int2_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"stat_int2_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"stat_int2_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"stat_int2_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"stat_int2_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"stat_int2_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"stat_int2_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"stat_int2_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"stat_int2_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"stat_int2_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"stat_int2_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"stat_int2_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"stat_int2_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"stat_int2_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"stat_int2_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"stat_int2_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"stat_int2_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"stat_int2_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"stat_int2_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"stat_int2_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"stat_int2_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"stat_int2_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"stat_int2_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"stat_int2_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"stat_int2_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"stat_int2_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"stat_int2_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"stat_int2_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"stat_int2_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"stat_int2_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"stat_int2_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"stat_int2_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int2_mask_reg[] = 
-    {
-        {"stat_int2_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"stat_int2_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"stat_int2_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"stat_int2_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"stat_int2_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"stat_int2_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"stat_int2_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"stat_int2_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"stat_int2_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"stat_int2_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"stat_int2_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"stat_int2_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"stat_int2_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"stat_int2_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"stat_int2_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"stat_int2_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"stat_int2_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"stat_int2_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"stat_int2_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"stat_int2_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"stat_int2_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"stat_int2_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"stat_int2_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"stat_int2_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"stat_int2_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"stat_int2_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"stat_int2_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"stat_int2_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"stat_int2_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"stat_int2_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"stat_int2_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"stat_int2_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int2_status_reg[] = 
-    {
-        {"stat_int2_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"stat_int2_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"stat_int2_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"stat_int2_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"stat_int2_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"stat_int2_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"stat_int2_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"stat_int2_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"stat_int2_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"stat_int2_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"stat_int2_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"stat_int2_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"stat_int2_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"stat_int2_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"stat_int2_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"stat_int2_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"stat_int2_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"stat_int2_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"stat_int2_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"stat_int2_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"stat_int2_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"stat_int2_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"stat_int2_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"stat_int2_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"stat_int2_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"stat_int2_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"stat_int2_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"stat_int2_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"stat_int2_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"stat_int2_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"stat_int2_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"stat_int2_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int3_en_reg[] = 
-    {
-        {"stat_int3_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"stat_int3_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"stat_int3_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"stat_int3_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"stat_int3_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"stat_int3_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"stat_int3_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"stat_int3_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"stat_int3_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"stat_int3_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"stat_int3_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"stat_int3_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"stat_int3_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"stat_int3_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"stat_int3_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"stat_int3_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"stat_int3_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"stat_int3_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"stat_int3_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"stat_int3_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"stat_int3_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"stat_int3_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"stat_int3_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"stat_int3_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"stat_int3_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"stat_int3_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"stat_int3_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"stat_int3_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"stat_int3_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"stat_int3_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"stat_int3_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"stat_int3_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int3_mask_reg[] = 
-    {
-        {"stat_int3_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0},
-        {"stat_int3_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0},
-        {"stat_int3_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0},
-        {"stat_int3_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0},
-        {"stat_int3_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0},
-        {"stat_int3_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0},
-        {"stat_int3_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0},
-        {"stat_int3_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0},
-        {"stat_int3_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0},
-        {"stat_int3_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0},
-        {"stat_int3_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0},
-        {"stat_int3_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0},
-        {"stat_int3_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0},
-        {"stat_int3_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"stat_int3_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"stat_int3_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"stat_int3_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"stat_int3_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"stat_int3_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"stat_int3_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"stat_int3_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"stat_int3_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"stat_int3_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"stat_int3_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"stat_int3_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"stat_int3_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"stat_int3_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"stat_int3_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"stat_int3_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"stat_int3_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"stat_int3_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"stat_int3_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int3_status_reg[] = 
-    {
-        {"stat_int3_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0},
-        {"stat_int3_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0},
-        {"stat_int3_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0},
-        {"stat_int3_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0},
-        {"stat_int3_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0},
-        {"stat_int3_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0},
-        {"stat_int3_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0},
-        {"stat_int3_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0},
-        {"stat_int3_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0},
-        {"stat_int3_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0},
-        {"stat_int3_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0},
-        {"stat_int3_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0},
-        {"stat_int3_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0},
-        {"stat_int3_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"stat_int3_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"stat_int3_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"stat_int3_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"stat_int3_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"stat_int3_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"stat_int3_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"stat_int3_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"stat_int3_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"stat_int3_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"stat_int3_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"stat_int3_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"stat_int3_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"stat_int3_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"stat_int3_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"stat_int3_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"stat_int3_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"stat_int3_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"stat_int3_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int4_en_reg[] = 
-    {
-        {"stat_int4_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"stat_int4_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"stat_int4_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"stat_int4_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"stat_int4_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"stat_int4_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"stat_int4_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"stat_int4_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"stat_int4_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"stat_int4_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"stat_int4_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"stat_int4_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"stat_int4_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"stat_int4_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"stat_int4_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"stat_int4_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"stat_int4_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"stat_int4_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"stat_int4_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int4_mask_reg[] = 
-    {
-        {"stat_int4_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"stat_int4_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"stat_int4_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"stat_int4_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"stat_int4_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"stat_int4_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"stat_int4_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"stat_int4_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"stat_int4_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"stat_int4_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"stat_int4_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"stat_int4_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"stat_int4_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"stat_int4_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"stat_int4_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"stat_int4_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"stat_int4_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"stat_int4_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"stat_int4_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int4_status_reg[] = 
-    {
-        {"stat_int4_mask_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"stat_int4_mask_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"stat_int4_mask_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"stat_int4_mask_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"stat_int4_mask_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"stat_int4_mask_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"stat_int4_mask_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"stat_int4_mask_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"stat_int4_mask_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"stat_int4_mask_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"stat_int4_mask_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"stat_int4_mask_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"stat_int4_mask_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"stat_int4_mask_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"stat_int4_mask_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"stat_int4_mask_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"stat_int4_mask_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"stat_int4_mask_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"stat_int4_mask_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int5_en_reg[] = 
-    {
-        {"stat_int5_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"stat_int5_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"stat_int5_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"stat_int5_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"stat_int5_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"stat_int5_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"stat_int5_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"stat_int5_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"stat_int5_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"stat_int5_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"stat_int5_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"stat_int5_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"stat_int5_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"stat_int5_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"stat_int5_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"stat_int5_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"stat_int5_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"stat_int5_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"stat_int5_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int5_mask_reg[] = 
-    {
-        {"stat_int5_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"stat_int5_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"stat_int5_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"stat_int5_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"stat_int5_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"stat_int5_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"stat_int5_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"stat_int5_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"stat_int5_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"stat_int5_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"stat_int5_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"stat_int5_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"stat_int5_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"stat_int5_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"stat_int5_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"stat_int5_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"stat_int5_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"stat_int5_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"stat_int5_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_int5_status_reg[] = 
-    {
-        {"stat_int5_mask_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"stat_int5_mask_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"stat_int5_mask_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"stat_int5_mask_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"stat_int5_mask_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"stat_int5_mask_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"stat_int5_mask_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"stat_int5_mask_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"stat_int5_mask_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"stat_int5_mask_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"stat_int5_mask_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"stat_int5_mask_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"stat_int5_mask_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"stat_int5_mask_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"stat_int5_mask_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"stat_int5_mask_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"stat_int5_mask_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"stat_int5_mask_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"stat_int5_mask_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_rschd_ecc_bypass_reg[] = 
-    {
-        {"rschd_ecc_bypass_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"rschd_ecc_bypass_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_rschd_ecc_single_err_reg[] = 
-    {
-        {"rschd_ecc_single_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"rschd_ecc_single_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_rschd_ecc_double_err_reg[] = 
-    {
-        {"rschd_ecc_double_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"rschd_ecc_double_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat0_reg[] = 
-    {
-        {"cpu_ind_ddr_wdat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat1_reg[] = 
-    {
-        {"cpu_ind_ddr_wdat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat2_reg[] = 
-    {
-        {"cpu_ind_ddr_wdat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat3_reg[] = 
-    {
-        {"cpu_ind_ddr_wdat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat4_reg[] = 
-    {
-        {"cpu_ind_ddr_wdat4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat5_reg[] = 
-    {
-        {"cpu_ind_ddr_wdat5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat6_reg[] = 
-    {
-        {"cpu_ind_ddr_wdat6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat7_reg[] = 
-    {
-        {"cpu_ind_ddr_wdat7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat8_reg[] = 
-    {
-        {"cpu_ind_ddr_wdat8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat9_reg[] = 
-    {
-        {"cpu_ind_ddr_wdat9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat10_reg[] = 
-    {
-        {"cpu_ind_ddr_wdat10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat11_reg[] = 
-    {
-        {"cpu_ind_ddr_wdat11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat12_reg[] = 
-    {
-        {"cpu_ind_ddr_wdat12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat13_reg[] = 
-    {
-        {"cpu_ind_ddr_wdat13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat14_reg[] = 
-    {
-        {"cpu_ind_ddr_wdat14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat15_reg[] = 
-    {
-        {"cpu_ind_ddr_wdat15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_req_info_reg[] = 
-    {
-        {"rw_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"read_mode", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0},
-        {"tm_cs", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0},
-        {"rw_addr", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rd_done_reg[] = 
-    {
-        {"cpu_ind_ddr_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat0_reg[] = 
-    {
-        {"cpu_ind_ddr_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat1_reg[] = 
-    {
-        {"cpu_ind_ddr_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat2_reg[] = 
-    {
-        {"cpu_ind_ddr_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat3_reg[] = 
-    {
-        {"cpu_ind_ddr_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat4_reg[] = 
-    {
-        {"cpu_ind_ddr_rdat4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat5_reg[] = 
-    {
-        {"cpu_ind_ddr_rdat5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat6_reg[] = 
-    {
-        {"cpu_ind_ddr_rdat6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat7_reg[] = 
-    {
-        {"cpu_ind_ddr_rdat7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat8_reg[] = 
-    {
-        {"cpu_ind_ddr_rdat8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat9_reg[] = 
-    {
-        {"cpu_ind_ddr_rdat9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat10_reg[] = 
-    {
-        {"cpu_ind_ddr_rdat10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat11_reg[] = 
-    {
-        {"cpu_ind_ddr_rdat11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat12_reg[] = 
-    {
-        {"cpu_ind_ddr_rdat12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat13_reg[] = 
-    {
-        {"cpu_ind_ddr_rdat13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat14_reg[] = 
-    {
-        {"cpu_ind_ddr_rdat14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat15_reg[] = 
-    {
-        {"cpu_ind_ddr_rdat15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_tm_alu_ddr_cpu_rdy_reg[] = 
-    {
-        {"tm_alu_ddr_cpu_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_ept_flag_reg[] = 
-    {
-        {"ept_flag", DPP_FIELD_FLAG_RO, 5, 6, 0x3f, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_ppu_soft_rst_reg[] = 
-    {
-        {"ppu_soft_rst", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_smmu0_fc15_0_cnt_reg[] = 
-    {
-        {"stat_smmu0_fc15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_smmu0_stat_fc15_0_cnt_reg[] = 
-    {
-        {"smmu0_stat_fc15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_smmu0_stat_rsp15_0_cnt_reg[] = 
-    {
-        {"smmu0_stat_rsp15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_smmu0_req15_0_cnt_reg[] = 
-    {
-        {"stat_smmu0_req15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_ppu_stat_mec5_0_rsp_fc_cnt_reg[] = 
-    {
-        {"ppu_stat_mec5_0_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_ppu_mec5_0_key_fc_cnt_reg[] = 
-    {
-        {"stat_ppu_mec5_0_key_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_ppu_mec5_0_rsp_cnt_reg[] = 
-    {
-        {"stat_ppu_mec5_0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_ppu_stat_mec5_0_key_cnt_reg[] = 
-    {
-        {"ppu_stat_mec5_0_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_ppu5_0_no_exist_opcd_ex_cnt_reg[] = 
-    {
-        {"ppu5_0_no_exist_opcd_ex_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_se_etm_stat_wr_fc_cnt_reg[] = 
-    {
-        {"se_etm_stat_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_se_etm_stat_rd_fc_cnt_reg[] = 
-    {
-        {"se_etm_stat_rd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_etm_deq_fc_cnt_reg[] = 
-    {
-        {"stat_etm_deq_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_etm_enq_fc_cnt_reg[] = 
-    {
-        {"stat_etm_enq_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_oam_lm_fc_cnt_reg[] = 
-    {
-        {"stat_oam_lm_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_oam_stat_lm_fc_cnt_reg[] = 
-    {
-        {"oam_stat_lm_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_oam_fc_cnt_reg[] = 
-    {
-        {"stat_oam_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cmmu_stat_fc_cnt_reg[] = 
-    {
-        {"cmmu_stat_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_cmmu_req_cnt_reg[] = 
-    {
-        {"stat_cmmu_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_smmu0_plcr_rsp0_cnt_reg[] = 
-    {
-        {"smmu0_plcr_rsp0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_plcr_smmu0_req0_cnt_reg[] = 
-    {
-        {"plcr_smmu0_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_stat_oam_lm_rsp_cnt_reg[] = 
-    {
-        {"stat_oam_lm_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_oam_stat_lm_req_cnt_reg[] = 
-    {
-        {"oam_stat_lm_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_oam_stat_req_cnt_reg[] = 
-    {
-        {"oam_stat_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_se_etm_stat_rsp_cnt_reg[] = 
-    {
-        {"se_etm_stat_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_etm_stat_se_wr_req_cnt_reg[] = 
-    {
-        {"etm_stat_se_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_etm_stat_se_rd_req_cnt_reg[] = 
-    {
-        {"etm_stat_se_rd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_etm_stat_smmu0_req_cnt0_reg[] = 
-    {
-        {"etm_stat_smmu0_req_cnt0", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_etm_stat_smmu0_req_cnt1_reg[] = 
-    {
-        {"etm_stat_smmu0_req_cnt1", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_tm_stat_eram_cpu_rsp_cnt_reg[] = 
-    {
-        {"tm_stat_eram_cpu_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_rd_eram_req_cnt_reg[] = 
-    {
-        {"cpu_rd_eram_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_wr_eram_req_cnt_reg[] = 
-    {
-        {"cpu_wr_eram_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_tm_stat_ddr_cpu_rsp_cnt_reg[] = 
-    {
-        {"tm_stat_ddr_cpu_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_rd_ddr_req_cnt_reg[] = 
-    {
-        {"cpu_rd_ddr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_stat_cfg_cpu_wr_ddr_req_cnt_reg[] = 
-    {
-        {"cpu_wr_ddr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat1_reg[] = 
-    {
-        {"wdat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat2_reg[] = 
-    {
-        {"wdat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat3_reg[] = 
-    {
-        {"wdat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat4_reg[] = 
-    {
-        {"wdat4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat5_reg[] = 
-    {
-        {"wdat5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat6_reg[] = 
-    {
-        {"wdat6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat7_reg[] = 
-    {
-        {"wdat7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat8_reg[] = 
-    {
-        {"wdat8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat9_reg[] = 
-    {
-        {"wdat9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat10_reg[] = 
-    {
-        {"wdat10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat11_reg[] = 
-    {
-        {"wdat11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat12_reg[] = 
-    {
-        {"wdat12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat13_reg[] = 
-    {
-        {"wdat13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat14_reg[] = 
-    {
-        {"wdat14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat15_reg[] = 
-    {
-        {"wdat15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat16_reg[] = 
-    {
-        {"wdat16", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat17_reg[] = 
-    {
-        {"wdat17", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat18_reg[] = 
-    {
-        {"wdat18", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_cpu_ind_wdat19_reg[] = 
-    {
-        {"wdat19", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_t_strwc_cfg_reg[] = 
-    {
-        {"t_strwc_cfg", DPP_FIELD_FLAG_RW, 1, 2, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_etcam_int_unmask_flag_reg[] = 
-    {
-        {"etcam_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_etcam_int_en0_reg[] = 
-    {
-        {"etcam_int_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"etcam_int_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"etcam_int_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"etcam_int_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"etcam_int_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"etcam_int_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"etcam_int_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"etcam_int_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"etcam_int_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"etcam_int_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"etcam_int_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"etcam_int_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"etcam_int_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"etcam_int_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"etcam_int_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"etcam_int_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"etcam_int_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"etcam_int_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_etcam_int_mask0_reg[] = 
-    {
-        {"etcam_int_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0},
-        {"etcam_int_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0},
-        {"etcam_int_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0},
-        {"etcam_int_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"etcam_int_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0},
-        {"etcam_int_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0},
-        {"etcam_int_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0},
-        {"etcam_int_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0},
-        {"etcam_int_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0},
-        {"etcam_int_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0},
-        {"etcam_int_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0},
-        {"etcam_int_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0},
-        {"etcam_int_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0},
-        {"etcam_int_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0},
-        {"etcam_int_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0},
-        {"etcam_int_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0},
-        {"etcam_int_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0},
-        {"etcam_int_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_etcam_int_status_reg[] = 
-    {
-        {"etcam_int_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0},
-        {"etcam_int_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0},
-        {"etcam_int_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0},
-        {"etcam_int_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0},
-        {"etcam_int_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0},
-        {"etcam_int_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0},
-        {"etcam_int_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0},
-        {"etcam_int_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0},
-        {"etcam_int_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0},
-        {"etcam_int_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0},
-        {"etcam_int_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0},
-        {"etcam_int_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0},
-        {"etcam_int_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0},
-        {"etcam_int_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0},
-        {"etcam_int_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0},
-        {"etcam_int_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0},
-        {"etcam_int_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0},
-        {"etcam_int_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_int_tb_ini_ok_reg[] = 
-    {
-        {"int_tb_ini_ok", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_etcam_clk_en_reg[] = 
-    {
-        {"etcam_clk_en", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_as_etcam_req0_cnt_reg[] = 
-    {
-        {"as_etcam_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_as_etcam_req1_cnt_reg[] = 
-    {
-        {"as_etcam_req1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_etcam_as_index0_cnt_reg[] = 
-    {
-        {"etcam_as_index0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_etcam_as_index1_cnt_reg[] = 
-    {
-        {"etcam_as_index1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_etcam_not_hit0_cnt_reg[] = 
-    {
-        {"etcam_not_hit0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_etcam_not_hit1_cnt_reg[] = 
-    {
-        {"etcam_not_hit1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_table_id_not_match_cnt_reg[] = 
-    {
-        {"table_id_not_match_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_table_id_clash01_cnt_reg[] = 
-    {
-        {"table_id_clash01_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_etcam_cpu_fl_reg[] = 
-    {
-        {"etcam_cpu_fl", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_stat_etcam_etcam_arb_empty_reg[] = 
-    {
-        {"etcam_arb_empty", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_event0_reg[] = 
-    {
-        {"cfg_finish_int_event0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_event1_reg[] = 
-    {
-        {"cfg_finish_int_event1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_event2_reg[] = 
-    {
-        {"cfg_finish_int_event2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_event3_reg[] = 
-    {
-        {"cfg_finish_int_event3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_maks0_reg[] = 
-    {
-        {"cfg_finish_int_mask0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_maks1_reg[] = 
-    {
-        {"cfg_finish_int_mask1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_maks2_reg[] = 
-    {
-        {"cfg_finish_int_mask2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_maks3_reg[] = 
-    {
-        {"cfg_finish_int_mask3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_test0_reg[] = 
-    {
-        {"cfg_finish_int_test0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_test1_reg[] = 
-    {
-        {"cfg_finish_int_test1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_test2_reg[] = 
-    {
-        {"cfg_finish_int_test2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_test3_reg[] = 
-    {
-        {"cfg_finish_int_test3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_int_to_riscv_sel_reg[] = 
-    {
-        {"cfg_dtb_int_to_riscv_sel0", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_ep_int_msix_enable_reg[] = 
-    {
-        {"cfg_dtb_ep_int_msix_enable", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_h_0_15_reg[] = 
-    {
-        {"cfg_dtb_ep_doorbell_addr_h_0_15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_l_0_15_reg[] = 
-    {
-        {"cfg_dtb_ep_doorbell_addr_l_0_15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_debug_mode_en_reg[] = 
-    {
-        {"cfg_dtb_debug_mode_en", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_table_addr_high_reg[] = 
-    {
-        {"info_axi_last_rd_table_addr_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_table_addr_low_reg[] = 
-    {
-        {"info_axi_last_rd_table_addr_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_table_len_reg[] = 
-    {
-        {"info_axi_last_rd_table_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_table_user_reg[] = 
-    {
-        {"info_rd_table_user_en", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0},
-        {"info_rd_table_epid", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0},
-        {"info_rd_table_vfunc_num", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0},
-        {"info_rd_table_func_num", DPP_FIELD_FLAG_RO, 7, 3, 0x0, 0x0},
-        {"info_rd_table_vfunc_active", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_table_onload_cnt_reg[] = 
-    {
-        {"info_axi_last_rd_table_onload_cnt", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_axi_rd_table_resp_err_reg[] = 
-    {
-        {"cnt_axi_rd_table_resp_err", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_pd_addr_high_reg[] = 
-    {
-        {"info_axi_last_rd_pd_addr_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_pd_addr_low_reg[] = 
-    {
-        {"info_axi_last_rd_pd_addr_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_pd_len_reg[] = 
-    {
-        {"info_axi_last_rd_pd_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_pd_user_reg[] = 
-    {
-        {"info_rd_pd_user_en", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0},
-        {"info_rd_pd_epid", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0},
-        {"info_rd_pd_vfunc_num", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0},
-        {"info_rd_pd_func_num", DPP_FIELD_FLAG_RO, 7, 3, 0x0, 0x0},
-        {"info_rd_pd_vfunc_active", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_pd_onload_cnt_reg[] = 
-    {
-        {"info_axi_last_rd_pd_onload_cnt", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_axi_rd_pd_resp_err_reg[] = 
-    {
-        {"cnt_axi_rd_pd_resp_err", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_high_reg[] = 
-    {
-        {"info_axi_last_wr_ctrl_addr_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_low_reg[] = 
-    {
-        {"info_axi_last_wr_ctrl_addr_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ctrl_len_reg[] = 
-    {
-        {"info_axi_last_wr_ctrl_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ctrl_user_reg[] = 
-    {
-        {"info_wr_ctrl_user_en", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0},
-        {"info_wr_ctrl_epid", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0},
-        {"info_wr_ctrl_vfunc_num", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0},
-        {"info_wr_ctrl_func_num", DPP_FIELD_FLAG_RO, 7, 3, 0x0, 0x0},
-        {"info_wr_ctrl_vfunc_active", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ctrl_onload_cnt_reg[] = 
-    {
-        {"info_axi_last_wr_ctrl_onload_cnt", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_axi_wr_ctrl_resp_err_reg[] = 
-    {
-        {"cnt_axi_wr_ctrl_resp_err", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_high_reg[] = 
-    {
-        {"info_axi_last_wr_ddr_addr_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_low_reg[] = 
-    {
-        {"info_axi_last_wr_ddr_addr_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ddr_len_reg[] = 
-    {
-        {"info_axi_last_wr_ddr_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ddr_user_reg[] = 
-    {
-        {"info_wr_ddr_user_en", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0},
-        {"info_wr_ddr_epid", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0},
-        {"info_wr_ddr_vfunc_num", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0},
-        {"info_wr_ddr_func_num", DPP_FIELD_FLAG_RO, 7, 3, 0x0, 0x0},
-        {"info_wr_ddr_vfunc_active", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ddr_onload_cnt_reg[] = 
-    {
-        {"info_axi_last_wr_ddr_onload_cnt", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_axi_wr_ddr_resp_err_reg[] = 
-    {
-        {"cnt_axi_wr_ddr_resp_err", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_fin_addr_high_reg[] = 
-    {
-        {"info_axi_last_wr_fin_addr_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_fin_addr_low_reg[] = 
-    {
-        {"info_axi_last_wr_fin_addr_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_fin_len_reg[] = 
-    {
-        {"info_axi_last_wr_fin_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_fin_user_reg[] = 
-    {
-        {"info_wr_fin_user_en", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0},
-        {"info_wr_fin_epid", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0},
-        {"info_wr_fin_vfunc_num", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0},
-        {"info_wr_fin_func_num", DPP_FIELD_FLAG_RO, 7, 3, 0x0, 0x0},
-        {"info_wr_fin_vfunc_active", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_fin_onload_cnt_reg[] = 
-    {
-        {"info_axi_last_wr_fin_onload_cnt", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_axi_wr_fin_resp_err_reg[] = 
-    {
-        {"cnt_axi_wr_fin_resp_err", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_high_reg[] = 
-    {
-        {"cnt_dtb_wr_smmu0_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_low_reg[] = 
-    {
-        {"cnt_dtb_wr_smmu0_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_high_reg[] = 
-    {
-        {"cnt_dtb_wr_smmu1_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_low_reg[] = 
-    {
-        {"cnt_dtb_wr_smmu1_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_high_reg[] = 
-    {
-        {"cnt_dtb_wr_zcam_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_low_reg[] = 
-    {
-        {"cnt_dtb_wr_zcam_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_high_reg[] = 
-    {
-        {"cnt_dtb_wr_etcam_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_low_reg[] = 
-    {
-        {"cnt_dtb_wr_etcam_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_hash_table_high_reg[] = 
-    {
-        {"cnt_dtb_wr_hash_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_hash_table_low_reg[] = 
-    {
-        {"cnt_dtb_wr_hash_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_high_reg[] = 
-    {
-        {"cnt_dtb_rd_smmu0_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_low_reg[] = 
-    {
-        {"cnt_dtb_rd_smmu0_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_high_reg[] = 
-    {
-        {"cnt_dtb_rd_smmu1_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_low_reg[] = 
-    {
-        {"cnt_dtb_rd_smmu1_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_high_reg[] = 
-    {
-        {"cnt_dtb_rd_zcam_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_low_reg[] = 
-    {
-        {"cnt_dtb_rd_zcam_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_high_reg[] = 
-    {
-        {"cnt_dtb_rd_etcam_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_low_reg[] = 
-    {
-        {"cnt_dtb_rd_etcam_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_wr_ctrl_state_reg[] = 
-    {
-        {"info_wr_ctrl_state", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_rd_table_state_reg[] = 
-    {
-        {"info_rd_table_state", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_rd_pd_state_reg[] = 
-    {
-        {"info_rd_pd_state", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_dump_cmd_state_reg[] = 
-    {
-        {"info_dump_cmd_state", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_info_wr_ddr_state_reg[] = 
-    {
-        {"info_wr_ddr_state", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_debug_info_clr_reg[] = 
-    {
-        {"cfg_dtb_debug_info_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_ddos_cfg_ddos_stat_dump_thrd_0_15_reg[] = 
-    {
-        {"cfg_ddos_stat_dump_thrd", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_ddos_cfg_ddos_stat_dump_thrd_comp_en_reg[] = 
-    {
-        {"cfg_ddos_stat_dump_thrd_comp_en", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_ddos_cfg_ddos_dump_stat_num_reg[] = 
-    {
-        {"cfg_ddos_dump_stat_num", DPP_FIELD_FLAG_RW, 23, 24, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_ddos_cfg_ddos_even_hash_table_baddr_reg[] = 
-    {
-        {"cfg_ddos_even_hash_table_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_ddos_cfg_ddos_odd_hash_table_baddr_reg[] = 
-    {
-        {"cfg_ddos_odd_hash_table_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_ddos_cfg_ddos_stat_index_offset_reg[] = 
-    {
-        {"cfg_ddos_stat_index_offset", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_ddos_cfg_ddos_ns_flag_cnt_reg[] = 
-    {
-        {"cfg_ddos_ns_flag_cnt", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_ddos_cfg_ddos_even_stat_table_baddr_reg[] = 
-    {
-        {"cfg_ddos_even_stat_table_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_ddos_cfg_ddos_odd_stat_table_baddr_reg[] = 
-    {
-        {"cfg_ddos_odd_stat_table_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_ddos_cfg_ddos_even_stat_dump_daddr_h_reg[] = 
-    {
-        {"cfg_ddos_even_stat_dump_daddr_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_ddos_cfg_ddos_even_stat_dump_daddr_l_reg[] = 
-    {
-        {"cfg_ddos_even_stat_dump_daddr_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_h_reg[] = 
-    {
-        {"cfg_ddos_odd_stat_dump_daddr_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_l_reg[] = 
-    {
-        {"cfg_ddos_odd_stat_dump_daddr_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_ddos_cfg_ddos_work_mode_enable_reg[] = 
-    {
-        {"cfg_ddos_mode_work_enable", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_ddos_cfg_ddos_stat_table_len_reg[] = 
-    {
-        {"cfg_ddos_stat_table_len", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_ddos_cfg_ddos_hash_table_len_reg[] = 
-    {
-        {"cfg_ddos_hash_table_len", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram0_0_255_reg[] = 
-    {
-        {"traf_ctrl_ram0_0_255", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram1_0_255_reg[] = 
-    {
-        {"traf_ctrl_ram1_0_255", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram2_0_255_reg[] = 
-    {
-        {"traf_ctrl_ram2_0_255", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram3_0_255_reg[] = 
-    {
-        {"traf_ctrl_ram3_0_255", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram4_0_255_reg[] = 
-    {
-        {"traf_ctrl_ram4_0_255", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram5_0_63_reg[] = 
-    {
-        {"traf_ctrl_ram5_0_63", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_ram_dump_pd_ram_0_2047_reg[] = 
-    {
-        {"dump_pd_ram_0_2047", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_ram_rd_ctrl_ram_0_4095_reg[] = 
-    {
-        {"rd_ctrl_ram_0_4095", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_ram_rd_table_ram_0_8191_reg[] = 
-    {
-        {"rd_table_ram_0_8191", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_dtb_dtb_ram_dtb_cmd_man_ram_0_16383_reg[] = 
-    {
-        {"dtb_cmd_man_ram_0_16383", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_ms_st_reg[] = 
-    {
-        {"cpu_trpgrx_ms_st", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_ms_ind_reg[] = 
-    {
-        {"cpu_trpgrx_ms_ind", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_ms_slave_ind_reg[] = 
-    {
-        {"cpu_trpgrx_ms_slave_ind", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_up_water_level_reg[] = 
-    {
-        {"cpu_trpgrx_up_water_level", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_low_water_level_reg[] = 
-    {
-        {"cpu_trpgrx_low_water_level", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_ms_st_reg[] = 
-    {
-        {"cpu_trpgtx_ms_st", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_ms_ind_reg[] = 
-    {
-        {"cpu_trpgtx_ms_ind", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_ms_slave_ind_reg[] = 
-    {
-        {"cpu_trpgtx_ms_slave_ind", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_update_int_event_reg[] = 
-    {
-        {"cpu_todtime_update_int_event", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_update_int_test_reg[] = 
-    {
-        {"cpu_todtime_update_int_test", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_update_int_addr_reg[] = 
-    {
-        {"cpu_todtime_update_int_addr", DPP_FIELD_FLAG_RO, 10, 11, 0x0, 0x0},
-    };
-DPP_FIELD_T g_trpg_trpg_tx_todtime_ram_trpg_tx_todtime_ram_reg[] = 
-    {
-        {"trpg_tx_todtime_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_test_reg_reg[] = 
-    {
-        {"cfg_tsn_test_reg", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_qbv_enable_reg[] = 
-    {
-        {"cfg_tsn_port_qbv_enable", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_phy_port_sel_reg[] = 
-    {
-        {"cfg_tsn_phy_port_sel", DPP_FIELD_FLAG_RW, 3, 4, 0xf, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_time_sel_reg[] = 
-    {
-        {"cfg_tsn_port_time_sel", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_clk_freq_reg[] = 
-    {
-        {"en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"cfg_tsn_clk_freq", DPP_FIELD_FLAG_RW, 30, 31, 0x64, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_read_ram_n_reg[] = 
-    {
-        {"cfg_tsn_data", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0},
-        {"cfg_tsn_read_status", DPP_FIELD_FLAG_RO, 5, 4, 0x0, 0x0},
-        {"cfg_tsn_read_ram_n", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_exe_time_reg[] = 
-    {
-        {"cfg_tsn_exe_time", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_itr_shift_reg[] = 
-    {
-        {"cfg_tsn_port_itr_shift", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_base_time_h_reg[] = 
-    {
-        {"cfg_tsn_port_base_time_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_base_time_l_reg[] = 
-    {
-        {"cfg_tsn_port_base_time_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_cycle_time_h_reg[] = 
-    {
-        {"cfg_tsn_port_cycle_time_h", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_cycle_time_l_reg[] = 
-    {
-        {"cfg_tsn_port_cycle_time_l", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_guard_band_time_reg[] = 
-    {
-        {"cfg_tsn_port_guard_band_time", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_default_gate_en_reg[] = 
-    {
-        {"cfg_tsn_port_default_gate_en", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_change_gate_en_reg[] = 
-    {
-        {"cfg_tsn_port_change_gate_en", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_init_finish_reg[] = 
-    {
-        {"cfg_tsn_port_init_finish", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_change_en_reg[] = 
-    {
-        {"cfg_tsn_port_change_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_gcl_num0_reg[] = 
-    {
-        {"cfg_tsn_port_gcl_num0", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_gcl_num1_reg[] = 
-    {
-        {"cfg_tsn_port_gcl_num1", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_gcl_value0_reg[] = 
-    {
-        {"cfg_tsn_port_gcl_gate_control0", DPP_FIELD_FLAG_RW, 31, 8, 0x0, 0x0},
-        {"cfg_tsn_port_gcl_interval_time0", DPP_FIELD_FLAG_RW, 23, 24, 0x0, 0x0},
-    };
-DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_gcl_value1_reg[] = 
-    {
-        {"cfg_tsn_port_gcl_gate_control1", DPP_FIELD_FLAG_RW, 31, 8, 0x0, 0x0},
-        {"cfg_tsn_port_gcl_interval_time1", DPP_FIELD_FLAG_RW, 23, 24, 0x0, 0x0},
-    };
-DPP_FIELD_T g_axi_axi_conv_cfg_epid_v_func_num_reg[] = 
-    {
-        {"user_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
-        {"cfg_epid", DPP_FIELD_FLAG_RW, 27, 4, 0x0, 0x0},
-        {"cfg_vfunc_num", DPP_FIELD_FLAG_RW, 23, 8, 0x0, 0x0},
-        {"cfg_func_num", DPP_FIELD_FLAG_RW, 7, 3, 0x0, 0x0},
-        {"cfg_vfunc_active", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_axi_axi_conv_info_axim_rw_hsk_cnt_reg[] = 
-    {
-        {"axim_rd_handshake_cnt", DPP_FIELD_FLAG_RO, 24, 9, 0x0, 0x0},
-        {"axim_wr_handshake_cnt", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_axi_axi_conv_info_axim_last_wr_id_reg[] = 
-    {
-        {"axim_rd_id", DPP_FIELD_FLAG_RO, 24, 9, 0x0, 0x0},
-        {"axim_wr_id", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0},
-    };
-DPP_FIELD_T g_axi_axi_conv_info_axim_last_wr_addr_h_reg[] = 
-    {
-        {"aximlastwraddrhigh", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_axi_axi_conv_info_axim_last_wr_addr_l_reg[] = 
-    {
-        {"aximlastrdaddrlow", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_axi_axi_conv_cfg_debug_info_clr_en_reg[] = 
-    {
-        {"cfg_global_clr_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_pp1s_interrupt_reg[] = 
-    {
-        {"int_state", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"int_test", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0},
-        {"int_clr", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"int_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_pp1s_external_select_reg[] = 
-    {
-        {"pp1s_external_select", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_pp1s_out_select_reg[] = 
-    {
-        {"pp1s_out_sel", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_test_pp1s_select_reg[] = 
-    {
-        {"test_pp1s_sel", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_local_pp1s_en_reg[] = 
-    {
-        {"local_pp1s_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_local_pp1s_adjust_reg[] = 
-    {
-        {"local_pp1s_adjust_sel", DPP_FIELD_FLAG_RW, 2, 2, 0x0, 0x0},
-        {"local_pp1s_adjust_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_local_pp1s_adjust_value_reg[] = 
-    {
-        {"local_pp1s_adjust_value", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_pp1s_to_np_select_reg[] = 
-    {
-        {"pp1s_to_np_sel", DPP_FIELD_FLAG_RW, 1, 2, 0x3, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_pd_u1_sel_reg[] = 
-    {
-        {"pd_u1_sel1", DPP_FIELD_FLAG_RW, 5, 3, 0x0, 0x0},
-        {"pd_u1_sel0", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_pd_u1_pd0_shift_reg[] = 
-    {
-        {"pd_u1_pd0_shift", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_pd_u1_pd1_shift_reg[] = 
-    {
-        {"pd_u1_pd1_shift", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_pd_u1_result_reg[] = 
-    {
-        {"pd_u1_result_sign", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0},
-        {"pd_u1_overflow", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0},
-        {"pd_u1_result", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_pd_u2_sel_reg[] = 
-    {
-        {"pd_u2_sel1", DPP_FIELD_FLAG_RW, 5, 3, 0x0, 0x0},
-        {"pd_u2_sel0", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_pd_u2_pd0_shift_reg[] = 
-    {
-        {"pd_u2_pd0_shift", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_pd_u2_pd1_shift_reg[] = 
-    {
-        {"pd_u2_pd1_shift", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_pd_u2_result_reg[] = 
-    {
-        {"pd_u2_result_sign", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0},
-        {"pd_u2_overflow", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0},
-        {"pd_u2_result", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_tsn_group_nanosecond_delay0_reg[] = 
-    {
-        {"tsn_group_nanosecond_delay0", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_tsn_group_fracnanosecond_delay0_reg[] = 
-    {
-        {"tsn_group_fracnanosecond_delay0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_tsn_group_nanosecond_delay1_reg[] = 
-    {
-        {"tsn_group_nanosecond_delay1", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_tsn_group_fracnanosecond_delay1_reg[] = 
-    {
-        {"tsn_group_fracnanosecond_delay1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_tsn_group_nanosecond_delay2_reg[] = 
-    {
-        {"tsn_group_nanosecond_delay2", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_tsn_group_fracnanosecond_delay2_reg[] = 
-    {
-        {"tsn_group_fracnanosecond_delay2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_tsn_group_nanosecond_delay3_reg[] = 
-    {
-        {"tsn_group_nanosecond_delay3", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_tsn_group_fracnanosecond_delay3_reg[] = 
-    {
-        {"tsn_group_fracnanosecond_delay3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_tsn_ptp1588_rdma_nanosecond_delay_reg[] = 
-    {
-        {"ptp1588_rdma_nanosecond_delay", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_ptp1588_rdma_fracnanosecond_delay_reg[] = 
-    {
-        {"ptp1588_rdma_fracnanosecond_delay", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_ptp1588_np_nanosecond_delay_reg[] = 
-    {
-        {"ptp1588_np_nanosecond_delay", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_ptp1588_np_fracnanosecond_delay_reg[] = 
-    {
-        {"ptp1588_np_fracnanosecond_delay", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptp_top_time_sync_period_reg[] = 
-    {
-        {"time_sync_period", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_module_id_reg[] = 
-    {
-        {"module_id", DPP_FIELD_FLAG_RO, 15, 16, 0x89, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_module_version_reg[] = 
-    {
-        {"module_major_version", DPP_FIELD_FLAG_RO, 15, 8, 0x3, 0x0},
-        {"module_minor_version", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_module_date_reg[] = 
-    {
-        {"year", DPP_FIELD_FLAG_RO, 31, 16, 0x2017, 0x0},
-        {"month", DPP_FIELD_FLAG_RO, 15, 8, 0x1, 0x0},
-        {"date", DPP_FIELD_FLAG_RO, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_interrupt_status_reg[] = 
-    {
-        {"pps_in_status", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0},
-        {"fifo_almost_full_status", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"fifo_no_empty_status", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0},
-        {"trigger_output_status", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0},
-        {"trigger_input_status", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_interrupt_event_reg[] = 
-    {
-        {"pps_in_event", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0},
-        {"fifo_almost_full_event", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0},
-        {"fifo_no_empty_event", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0},
-        {"trigger_output_event", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"trigger_input_event", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_interrupt_mask_reg[] = 
-    {
-        {"pps_in_event_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0},
-        {"fifo_almost_full_event_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0},
-        {"fifo_no_empty_event_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0},
-        {"trigger_output_event_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"trigger_input_eventt_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_interrupt_test_reg[] = 
-    {
-        {"trigger_pps_in_event_test", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0},
-        {"trigger_fifo_almost_full_event_test", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0},
-        {"trigger_fifo_no_empty_event_test", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0},
-        {"trigger_output_event_test", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"trigger_input_event_test", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_hw_clock_cycle_integer_reg[] = 
-    {
-        {"integeral_nanosecond_of_hw_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_hw_clock_cycle_fraction_reg[] = 
-    {
-        {"fractional_nanosecond_of_hw_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_ptp_clock_cycle_integer_reg[] = 
-    {
-        {"integeral_nanosecond_of_ptp_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_ptp_clock_cycle_fraction_reg[] = 
-    {
-        {"fractional_nanosecond_of_ptp_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_ptp_configuration_reg[] = 
-    {
-        {"trig_oe", DPP_FIELD_FLAG_RW, 18, 1, 0x0, 0x0},
-        {"hw_time_update_en", DPP_FIELD_FLAG_RW, 17, 1, 0x0, 0x0},
-        {"ptp1588_tod_time_update_en", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0},
-        {"timer_enable", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0},
-        {"pps_output_enable", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0},
-        {"pp1_output_enable", DPP_FIELD_FLAG_RW, 13, 1, 0x0, 0x0},
-        {"pp2_output_enable", DPP_FIELD_FLAG_RW, 12, 1, 0x0, 0x0},
-        {"enable_writing_timestamps_to_the_fifo", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0},
-        {"l2s_time_output_select", DPP_FIELD_FLAG_RW, 10, 1, 0x0, 0x0},
-        {"reserved_9", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0},
-        {"pps_input_select", DPP_FIELD_FLAG_RW, 8, 1, 0x0, 0x0},
-        {"pp_output_select", DPP_FIELD_FLAG_RW, 7, 1, 0x0, 0x0},
-        {"reserved_6", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0},
-        {"timer_run_mode", DPP_FIELD_FLAG_RW, 5, 2, 0x0, 0x0},
-        {"update_command_select", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0},
-        {"trigger_out_enable", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0},
-        {"trigger_in_enable", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"timer_capture_slave_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_timer_control_reg[] = 
-    {
-        {"ptpmoutputsynchroningstate", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0},
-        {"ptp1588_fifo_read_command", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0},
-        {"adjust_the_timer", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pps_income_delay_reg[] = 
-    {
-        {"pps_income_delay_nanosecond", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0},
-        {"pps_income_delay_frac_nanosecond", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_clock_cycle_update_reg[] = 
-    {
-        {"tsn3_clock_cycle_update_enable", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0},
-        {"tsn2_clock_cycle_update_enable", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0},
-        {"tsn1_clock_cycle_update_enable", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0},
-        {"tsn0_clock_cycle_update_enable", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"ptp1588_clock_cycle_update_enable", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_cycle_time_of_output_period_pulse_1_reg[] = 
-    {
-        {"clock_number_of_output_period_pulse_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_cycle_time_of_output_period_pulse_2_reg[] = 
-    {
-        {"clock_number_of_output_period_pulse_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_timer_latch_en_reg[] = 
-    {
-        {"latch_the_timer_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_timer_latch_sel_reg[] = 
-    {
-        {"timer_latch_sel", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_trigger_in_tod_nanosecond_reg[] = 
-    {
-        {"trigger_in_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_trigger_in_lower_tod_second_reg[] = 
-    {
-        {"trigger_in_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_trigger_in_high_tod_second_reg[] = 
-    {
-        {"trigger_in_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_trigger_in_fracnanosecond_reg[] = 
-    {
-        {"trigger_in_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_trigger_in_hardware_time_low_reg[] = 
-    {
-        {"trigger_in_hardware_time_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_trigger_in_hardware_time_high_reg[] = 
-    {
-        {"trigger_in_hardware_time_high", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_trigger_out_tod_nanosecond_reg[] = 
-    {
-        {"trigger_out_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_trigger_out_lower_tod_second_reg[] = 
-    {
-        {"trigger_out_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_trigger_out_high_tod_second_reg[] = 
-    {
-        {"trigger_out_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_trigger_out_hardware_time_low_reg[] = 
-    {
-        {"trigger_out_hardware_time_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_trigger_out_hardware_time_high_reg[] = 
-    {
-        {"trigger_out_hardware_time_high", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_adjust_tod_nanosecond_reg[] = 
-    {
-        {"adjust_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_adjust_lower_tod_second_reg[] = 
-    {
-        {"adjust_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_adjust_high_tod_second_reg[] = 
-    {
-        {"adjust_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_adjust_fracnanosecond_reg[] = 
-    {
-        {"adjust_fracnanosecond", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_adjust_hardware_time_low_reg[] = 
-    {
-        {"adjust_hardware_time_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_adjust_hardware_time_high_reg[] = 
-    {
-        {"adjust_hardware_time_high", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_latch_tod_nanosecond_reg[] = 
-    {
-        {"latch_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_latch_lower_tod_second_reg[] = 
-    {
-        {"latch_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_latch_high_tod_second_reg[] = 
-    {
-        {"latch_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_latch_fracnanosecond_reg[] = 
-    {
-        {"latch_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_latch_hardware_time_low_reg[] = 
-    {
-        {"latch_hardware_time_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_latch_hardware_time_high_reg[] = 
-    {
-        {"latch_hardware_time_high", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_real_tod_nanosecond_reg[] = 
-    {
-        {"real_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_real_lower_tod_second_reg[] = 
-    {
-        {"real_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_real_high_tod_second_reg[] = 
-    {
-        {"real_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_real_hardware_time_low_reg[] = 
-    {
-        {"real_hardware_time_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_real_hardware_time_high_reg[] = 
-    {
-        {"real_hardware_time_high", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_ptp1588_event_message_port_reg[] = 
-    {
-        {"ptp1588_event_message_port", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_ptp1588_event_message_timestamp_low_reg[] = 
-    {
-        {"ptp1588_event_message_timestamp_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_ptp1588_event_message_timestamp_high_reg[] = 
-    {
-        {"ptp1588_event_message_timestamp_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_ptp1588_event_message_fifo_status_reg[] = 
-    {
-        {"fifo_full", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0},
-        {"fifo_empty", DPP_FIELD_FLAG_RO, 8, 1, 0x1, 0x0},
-        {"timestamps_count", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tod_nanosecond_reg[] = 
-    {
-        {"latch_1588tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_lower_tod_second_reg[] = 
-    {
-        {"latch_lower_1588tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_high_tod_second_reg[] = 
-    {
-        {"latch_high_1588tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_fracnanosecond_reg[] = 
-    {
-        {"latch_1588fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn_time_configuration_reg[] = 
-    {
-        {"tsn_pps_enable", DPP_FIELD_FLAG_RW, 19, 4, 0x0, 0x0},
-        {"tsn_timer_enable", DPP_FIELD_FLAG_RW, 15, 4, 0x0, 0x0},
-        {"tsn_timer_run_mode", DPP_FIELD_FLAG_RW, 11, 8, 0x0, 0x0},
-        {"timer_capture_slave_mode", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn_timer_control_reg[] = 
-    {
-        {"adjust_the_tsn3_timer", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0},
-        {"adjust_the_tsn2_timer", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0},
-        {"adjust_the_tsn1_timer", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0},
-        {"adjust_the_tsn0_timer", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn0_clock_cycle_integer_reg[] = 
-    {
-        {"integeral_nanosecond_of_tsn0_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn0_clock_cycle_fraction_reg[] = 
-    {
-        {"fractional_nanosecond_of_tsn0_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn1_clock_cycle_integer_reg[] = 
-    {
-        {"integeral_nanosecond_of_tsn1_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn1_clock_cycle_fraction_reg[] = 
-    {
-        {"fractional_nanosecond_of_tsn1_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn2_clock_cycle_integer_reg[] = 
-    {
-        {"integeral_nanosecond_of_tsn2_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn2_clock_cycle_fraction_reg[] = 
-    {
-        {"fractional_nanosecond_of_tsn2_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn3_clock_cycle_integer_reg[] = 
-    {
-        {"integeral_nanosecond_of_tsn3_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn3_clock_cycle_fraction_reg[] = 
-    {
-        {"fractional_nanosecond_of_tsn3_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn0_adjust_tod_nanosecond_reg[] = 
-    {
-        {"tsn0_adjust_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn0_adjust_lower_tod_second_reg[] = 
-    {
-        {"tsn0_adjust_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn0_adjust_high_tod_second_reg[] = 
-    {
-        {"tsn0_adjust_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn0_adjust_fracnanosecond_reg[] = 
-    {
-        {"tsn0_adjust_fracnanosecond", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn1_adjust_tod_nanosecond_reg[] = 
-    {
-        {"tsn1_adjust_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn1_adjust_lower_tod_second_reg[] = 
-    {
-        {"tsn1_adjust_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn1_adjust_high_tod_second_reg[] = 
-    {
-        {"tsn1_adjust_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn1_adjust_fracnanosecond_reg[] = 
-    {
-        {"tsn1_adjust_fracnanosecond", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn2_adjust_tod_nanosecond_reg[] = 
-    {
-        {"tsn2_adjust_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn2_adjust_lower_tod_second_reg[] = 
-    {
-        {"tsn2_adjust_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn2_adjust_high_tod_second_reg[] = 
-    {
-        {"tsn2_adjust_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn2_adjust_fracnanosecond_reg[] = 
-    {
-        {"tsn2_adjust_fracnanosecond", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn3_adjust_tod_nanosecond_reg[] = 
-    {
-        {"tsn3_adjust_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn3_adjust_lower_tod_second_reg[] = 
-    {
-        {"tsn3_adjust_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn3_adjust_high_tod_second_reg[] = 
-    {
-        {"tsn3_adjust_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn3_adjust_fracnanosecond_reg[] = 
-    {
-        {"tsn3_adjust_fracnanosecond", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn0_latch_tod_nanosecond_reg[] = 
-    {
-        {"tsn0_latch_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn0_latch_lower_tod_second_reg[] = 
-    {
-        {"tsn0_latch_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn0_latch_high_tod_second_reg[] = 
-    {
-        {"tsn0_latch_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn0_latch_fracnanosecond_reg[] = 
-    {
-        {"tsn0_latch_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn1_latch_tod_nanosecond_reg[] = 
-    {
-        {"tsn1_latch_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn1_latch_lower_tod_second_reg[] = 
-    {
-        {"tsn1_latch_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn1_latch_high_tod_second_reg[] = 
-    {
-        {"tsn1_latch_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn1_latch_fracnanosecond_reg[] = 
-    {
-        {"tsn1_latch_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn2_latch_tod_nanosecond_reg[] = 
-    {
-        {"tsn2_latch_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn2_latch_lower_tod_second_reg[] = 
-    {
-        {"tsn2_latch_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn2_latch_high_tod_second_reg[] = 
-    {
-        {"tsn2_latch_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn2_latch_fracnanosecond_reg[] = 
-    {
-        {"tsn2_latch_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn3_latch_tod_nanosecond_reg[] = 
-    {
-        {"tsn3_latch_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn3_latch_lower_tod_second_reg[] = 
-    {
-        {"tsn3_latch_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn3_latch_high_tod_second_reg[] = 
-    {
-        {"tsn3_latch_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn3_latch_fracnanosecond_reg[] = 
-    {
-        {"tsn3_latch_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn0_tod_nanosecond_reg[] = 
-    {
-        {"latch_tsn0_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn0_lower_tod_second_reg[] = 
-    {
-        {"latch_lower_tsn0_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn0_high_tod_second_reg[] = 
-    {
-        {"latch_high_tsn0_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn0_fracnanosecond_reg[] = 
-    {
-        {"latch_tsn0_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn1_tod_nanosecond_reg[] = 
-    {
-        {"latch_tsn1_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn1_lower_tod_second_reg[] = 
-    {
-        {"latch_lower_tsn1_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn1_high_tod_second_reg[] = 
-    {
-        {"latch_high_tsn1_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn1_fracnanosecond_reg[] = 
-    {
-        {"latch_tsn1_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn2_tod_nanosecond_reg[] = 
-    {
-        {"latch_tsn2_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn2_lower_tod_second_reg[] = 
-    {
-        {"latch_lower_tsn2_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn2_high_tod_second_reg[] = 
-    {
-        {"latch_high_tsn2_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn2_fracnanosecond_reg[] = 
-    {
-        {"latch_tsn2_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn3_tod_nanosecond_reg[] = 
-    {
-        {"latch_tsn3_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn3_lower_tod_second_reg[] = 
-    {
-        {"latch_lower_tsn3_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn3_high_tod_second_reg[] = 
-    {
-        {"latch_high_tsn3_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn3_fracnanosecond_reg[] = 
-    {
-        {"latch_tsn3_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn0_real_tod_nanosecond_reg[] = 
-    {
-        {"tsn0_real_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn0_real_lower_tod_second_reg[] = 
-    {
-        {"tsn0_real_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn0_real_high_tod_second_reg[] = 
-    {
-        {"tsn0_real_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn1_real_tod_nanosecond_reg[] = 
-    {
-        {"tsn1_real_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn1_real_lower_tod_second_reg[] = 
-    {
-        {"tsn1_real_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn1_real_high_tod_second_reg[] = 
-    {
-        {"tsn1_real_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn2_real_tod_nanosecond_reg[] = 
-    {
-        {"tsn2_real_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn2_real_lower_tod_second_reg[] = 
-    {
-        {"tsn2_real_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn2_real_high_tod_second_reg[] = 
-    {
-        {"tsn2_real_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn3_real_tod_nanosecond_reg[] = 
-    {
-        {"tsn3_real_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn3_real_lower_tod_second_reg[] = 
-    {
-        {"tsn3_real_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_tsn3_real_high_tod_second_reg[] = 
-    {
-        {"tsn3_real_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_real_ptp_clock_cycle_integer_reg[] = 
-    {
-        {"integeral_nanosecond_of_real_ptp_clock_cycle", DPP_FIELD_FLAG_RO, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_real_ptp_clock_cycle_fraction_reg[] = 
-    {
-        {"fractional_nanosecond_of_real_ptp_clock_cycle", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_real_tsn0_clock_cycle_integer_reg[] = 
-    {
-        {"integeral_nanosecond_of_real_tsn0_clock_cycle", DPP_FIELD_FLAG_RO, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_real_tsn0_clock_cycle_fraction_reg[] = 
-    {
-        {"fractional_nanosecond_of_real_tsn0_clock_cycle", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_real_tsn1_clock_cycle_integer_reg[] = 
-    {
-        {"integeral_nanosecond_of_real_tsn1_clock_cycle", DPP_FIELD_FLAG_RO, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_real_tsn1_clock_cycle_fraction_reg[] = 
-    {
-        {"fractional_nanosecond_of_real_tsn1_clock_cycle", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_real_tsn2_clock_cycle_integer_reg[] = 
-    {
-        {"integeral_nanosecond_of_real_tsn2_clock_cycle", DPP_FIELD_FLAG_RO, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_real_tsn2_clock_cycle_fraction_reg[] = 
-    {
-        {"fractional_nanosecond_of_real_tsn2_clock_cycle", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_real_tsn3_clock_cycle_integer_reg[] = 
-    {
-        {"integeral_nanosecond_of_real_tsn3_clock_cycle", DPP_FIELD_FLAG_RO, 7, 8, 0x1, 0x0},
-    };
-DPP_FIELD_T g_ptptm_ptptm_real_tsn3_clock_cycle_fraction_reg[] = 
-    {
-        {"fractional_nanosecond_of_real_tsn3_clock_cycle", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
-    };
-DPP_REG_T g_dpp_reg_info[] = 
-{
-    {
-        "cpu_check_reg",
-        ETM_CFGMT_CPU_CHECK_REGr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x60,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cfgmt_cpu_check_reg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_blksize",
-        ETM_CFGMT_CFGMT_BLKSIZEr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x70,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cfgmt_cfgmt_blksize_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "reg_int_state_reg",
-        ETM_CFGMT_REG_INT_STATE_REGr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x90,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        7,
-        g_etm_cfgmt_reg_int_state_reg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "reg_int_mask_reg",
-        ETM_CFGMT_REG_INT_MASK_REGr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xa0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        7,
-        g_etm_cfgmt_reg_int_mask_reg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "timeout_limit",
-        ETM_CFGMT_TIMEOUT_LIMITr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xb0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cfgmt_timeout_limit_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "subsystem_rdy_reg",
-        ETM_CFGMT_SUBSYSTEM_RDY_REGr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xc0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_etm_cfgmt_subsystem_rdy_reg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "subsystem_en_reg",
-        ETM_CFGMT_SUBSYSTEM_EN_REGr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xd0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_cfgmt_subsystem_en_reg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_int_reg",
-        ETM_CFGMT_CFGMT_INT_REGr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cfgmt_cfgmt_int_reg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_work_mode",
-        ETM_CFGMT_QMU_WORK_MODEr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x100,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cfgmt_qmu_work_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_ddr_attach",
-        ETM_CFGMT_CFGMT_DDR_ATTACHr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x120,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cfgmt_cfgmt_ddr_attach_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_mode_reg",
-        ETM_CFGMT_CNT_MODE_REGr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x140,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_etm_cfgmt_cnt_mode_reg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "clkgate_en",
-        ETM_CFGMT_CLKGATE_ENr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cfgmt_clkgate_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "softrst_en",
-        ETM_CFGMT_SOFTRST_ENr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cfgmt_softrst_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "imem_prog_full",
-        ETM_OLIF_IMEM_PROG_FULLr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_olif_imem_prog_full_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_para_prog_full",
-        ETM_OLIF_QMU_PARA_PROG_FULLr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_olif_qmu_para_prog_full_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "olif_int_mask",
-        ETM_OLIF_OLIF_INT_MASKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        19,
-        g_etm_olif_olif_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "itmhram_parity_err_2_int",
-        ETM_OLIF_ITMHRAM_PARITY_ERR_2_INTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x9,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        22,
-        g_etm_olif_itmhram_parity_err_2_int_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lif0_port_rdy_mask_h",
-        ETM_OLIF_LIF0_PORT_RDY_MASK_Hr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x30,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_lif0_port_rdy_mask_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lif0_port_rdy_mask_l",
-        ETM_OLIF_LIF0_PORT_RDY_MASK_Lr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x31,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_lif0_port_rdy_mask_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lif0_port_rdy_cfg_h",
-        ETM_OLIF_LIF0_PORT_RDY_CFG_Hr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x32,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_lif0_port_rdy_cfg_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lif0_port_rdy_cfg_l",
-        ETM_OLIF_LIF0_PORT_RDY_CFG_Lr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x33,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_lif0_port_rdy_cfg_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lif0_link_rdy_mask_cfg",
-        ETM_OLIF_LIF0_LINK_RDY_MASK_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x34,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_olif_lif0_link_rdy_mask_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_lif_stat_cfg",
-        ETM_OLIF_TM_LIF_STAT_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x40,
-        (32/8),
-        0,
-        0xf + 1,
-        0,
-        0x1,
-        4,
-        g_etm_olif_tm_lif_stat_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_lif_sop_stat",
-        ETM_OLIF_TM_LIF_SOP_STATr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x50,
-        (32/8),
-        0,
-        0xf + 1,
-        0,
-        0x1,
-        1,
-        g_etm_olif_tm_lif_sop_stat_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_lif_eop_stat",
-        ETM_OLIF_TM_LIF_EOP_STATr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x60,
-        (32/8),
-        0,
-        0xf + 1,
-        0,
-        0x1,
-        1,
-        g_etm_olif_tm_lif_eop_stat_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_lif_vld_stat",
-        ETM_OLIF_TM_LIF_VLD_STATr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x80,
-        (32/8),
-        0,
-        0xf + 1,
-        0,
-        0x1,
-        1,
-        g_etm_olif_tm_lif_vld_stat_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "prog_full_assert_cfg",
-        ETM_CGAVD_PROG_FULL_ASSERT_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_cgavd_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_int",
-        ETM_CGAVD_CGAVD_INTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_int_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_ram_err",
-        ETM_CGAVD_CGAVD_RAM_ERRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x3,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        13,
-        g_etm_cgavd_cgavd_ram_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_int_mask",
-        ETM_CGAVD_CGAVD_INT_MASKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_ram_err_int_mask",
-        ETM_CGAVD_CGAVD_RAM_ERR_INT_MASKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x5,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        13,
-        g_etm_cgavd_cgavd_ram_err_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_byte_mode",
-        ETM_CGAVD_CFGMT_BYTE_MODEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x6,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cfgmt_byte_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "avg_qlen_return_zero_en",
-        ETM_CGAVD_AVG_QLEN_RETURN_ZERO_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x7,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_avg_qlen_return_zero_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_wred_q_len_th",
-        ETM_CGAVD_FLOW_WRED_Q_LEN_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x20,
-        (32/8),
-        0,
-        0x1f + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_flow_wred_q_len_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_wq",
-        ETM_CGAVD_FLOW_WQr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x40,
-        (32/8),
-        0,
-        0x1f + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_flow_wq_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_wred_max_th",
-        ETM_CGAVD_FLOW_WRED_MAX_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x100,
-        (32/8),
-        0,
-        0xff + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_flow_wred_max_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_wred_min_th",
-        ETM_CGAVD_FLOW_WRED_MIN_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x200,
-        (32/8),
-        0,
-        0xff + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_flow_wred_min_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_wred_cfg_para",
-        ETM_CGAVD_FLOW_WRED_CFG_PARAr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x300,
-        (32/8),
-        0,
-        0xff + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_flow_wred_cfg_para_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_avg_q_len",
-        ETM_CGAVD_PP_AVG_Q_LENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x400,
-        (32/8),
-        0,
-        0x7f + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_pp_avg_q_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_td_th",
-        ETM_CGAVD_PP_TD_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x600,
-        (32/8),
-        0,
-        0x7f + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_pp_td_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_ca_mtd",
-        ETM_CGAVD_PP_CA_MTDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x800,
-        (32/8),
-        0,
-        0x7f + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_pp_ca_mtd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_wred_grp_th_en",
-        ETM_CGAVD_PP_WRED_GRP_TH_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0xc00,
-        (32/8),
-        0,
-        0x7f + 1,
-        0,
-        0x1,
-        2,
-        g_etm_cgavd_pp_wred_grp_th_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_wred_q_len_th",
-        ETM_CGAVD_PP_WRED_Q_LEN_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0xe00,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_pp_wred_q_len_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_wq",
-        ETM_CGAVD_PP_WQr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0xe08,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_pp_wq_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_wred_max_th",
-        ETM_CGAVD_PP_WRED_MAX_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x1000,
-        (32/8),
-        0,
-        0x3f + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_pp_wred_max_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_wred_min_th",
-        ETM_CGAVD_PP_WRED_MIN_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x1080,
-        (32/8),
-        0,
-        0x3f + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_pp_wred_min_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_cfg_para",
-        ETM_CGAVD_PP_CFG_PARAr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x1100,
-        (32/8),
-        0,
-        0x3f + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_pp_cfg_para_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sys_avg_q_len",
-        ETM_CGAVD_SYS_AVG_Q_LENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1200,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_sys_avg_q_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sys_td_th",
-        ETM_CGAVD_SYS_TD_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1202,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_sys_td_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sys_cgavd_metd",
-        ETM_CGAVD_SYS_CGAVD_METDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1204,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_sys_cgavd_metd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sys_cfg_q_grp_para",
-        ETM_CGAVD_SYS_CFG_Q_GRP_PARAr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1208,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_sys_cfg_q_grp_para_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sys_wq",
-        ETM_CGAVD_SYS_WQr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1210,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_sys_wq_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "gred_max_th",
-        ETM_CGAVD_GRED_MAX_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x1218,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_gred_max_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "gred_mid_th",
-        ETM_CGAVD_GRED_MID_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x1228,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_gred_mid_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "gred_min_th",
-        ETM_CGAVD_GRED_MIN_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x1238,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_gred_min_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "gred_cfg_para0",
-        ETM_CGAVD_GRED_CFG_PARA0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x1248,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_gred_cfg_para0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "gred_cfg_para1",
-        ETM_CGAVD_GRED_CFG_PARA1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x1258,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_gred_cfg_para1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "gred_cfg_para2",
-        ETM_CGAVD_GRED_CFG_PARA2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x1268,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_gred_cfg_para2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sys_window_th_h",
-        ETM_CGAVD_SYS_WINDOW_TH_Hr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1278,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_sys_window_th_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sys_window_th_l",
-        ETM_CGAVD_SYS_WINDOW_TH_Lr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x127a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_sys_window_th_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "amplify_gene0",
-        ETM_CGAVD_AMPLIFY_GENE0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x127c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_amplify_gene0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "amplify_gene1",
-        ETM_CGAVD_AMPLIFY_GENE1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x127d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_amplify_gene1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "amplify_gene2",
-        ETM_CGAVD_AMPLIFY_GENE2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x127e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_amplify_gene2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "amplify_gene3",
-        ETM_CGAVD_AMPLIFY_GENE3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x127f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_amplify_gene3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "amplify_gene4",
-        ETM_CGAVD_AMPLIFY_GENE4r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1280,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_amplify_gene4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "amplify_gene5",
-        ETM_CGAVD_AMPLIFY_GENE5r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1281,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_amplify_gene5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "amplify_gene6",
-        ETM_CGAVD_AMPLIFY_GENE6r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1282,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_amplify_gene6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "amplify_gene7",
-        ETM_CGAVD_AMPLIFY_GENE7r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1283,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_amplify_gene7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "amplify_gene8",
-        ETM_CGAVD_AMPLIFY_GENE8r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1284,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_amplify_gene8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "amplify_gene9",
-        ETM_CGAVD_AMPLIFY_GENE9r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1285,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_amplify_gene9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "amplify_gene10",
-        ETM_CGAVD_AMPLIFY_GENE10r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1286,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_amplify_gene10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "amplify_gene11",
-        ETM_CGAVD_AMPLIFY_GENE11r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1287,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_amplify_gene11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "amplify_gene12",
-        ETM_CGAVD_AMPLIFY_GENE12r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1288,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_amplify_gene12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "amplify_gene13",
-        ETM_CGAVD_AMPLIFY_GENE13r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1289,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_amplify_gene13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "amplify_gene14",
-        ETM_CGAVD_AMPLIFY_GENE14r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x128a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_amplify_gene14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "amplify_gene15",
-        ETM_CGAVD_AMPLIFY_GENE15r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x128b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_amplify_gene15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "equal_pkt_len_en",
-        ETM_CGAVD_EQUAL_PKT_LEN_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x128c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_equal_pkt_len_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "equal_pkt_len_th0",
-        ETM_CGAVD_EQUAL_PKT_LEN_TH0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x128d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_equal_pkt_len_th0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "equal_pkt_len_th1",
-        ETM_CGAVD_EQUAL_PKT_LEN_TH1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x128e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_equal_pkt_len_th1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "equal_pkt_len_th2",
-        ETM_CGAVD_EQUAL_PKT_LEN_TH2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x128f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_equal_pkt_len_th2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "equal_pkt_len_th3",
-        ETM_CGAVD_EQUAL_PKT_LEN_TH3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1290,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_equal_pkt_len_th3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "equal_pkt_len_th4",
-        ETM_CGAVD_EQUAL_PKT_LEN_TH4r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1291,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_equal_pkt_len_th4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "equal_pkt_len_th5",
-        ETM_CGAVD_EQUAL_PKT_LEN_TH5r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1292,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_equal_pkt_len_th5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "equal_pkt_len_th6",
-        ETM_CGAVD_EQUAL_PKT_LEN_TH6r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1293,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_equal_pkt_len_th6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "equal_pkt_len0",
-        ETM_CGAVD_EQUAL_PKT_LEN0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1294,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_equal_pkt_len0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "equal_pkt_len1",
-        ETM_CGAVD_EQUAL_PKT_LEN1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1295,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_equal_pkt_len1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "equal_pkt_len2",
-        ETM_CGAVD_EQUAL_PKT_LEN2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1296,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_equal_pkt_len2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "equal_pkt_len3",
-        ETM_CGAVD_EQUAL_PKT_LEN3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1297,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_equal_pkt_len3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "equal_pkt_len4",
-        ETM_CGAVD_EQUAL_PKT_LEN4r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1298,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_equal_pkt_len4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "equal_pkt_len5",
-        ETM_CGAVD_EQUAL_PKT_LEN5r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1299,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_equal_pkt_len5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "equal_pkt_len6",
-        ETM_CGAVD_EQUAL_PKT_LEN6r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x129a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_equal_pkt_len6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "equal_pkt_len7",
-        ETM_CGAVD_EQUAL_PKT_LEN7r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x129b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_equal_pkt_len7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_cpu_set_avg_len",
-        ETM_CGAVD_FLOW_CPU_SET_AVG_LENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x129c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow_cpu_set_avg_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_cpu_set_q_len",
-        ETM_CGAVD_FLOW_CPU_SET_Q_LENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x129d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow_cpu_set_q_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_cpu_set_avg_q_len",
-        ETM_CGAVD_PP_CPU_SET_AVG_Q_LENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12ef,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_pp_cpu_set_avg_q_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_cpu_set_q_len",
-        ETM_CGAVD_PP_CPU_SET_Q_LENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x129e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_pp_cpu_set_q_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sys_cpu_set_avg_len",
-        ETM_CGAVD_SYS_CPU_SET_AVG_LENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_sys_cpu_set_avg_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sys_cpu_set_q_len",
-        ETM_CGAVD_SYS_CPU_SET_Q_LENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12a2,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_sys_cpu_set_q_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pke_len_calc_sign",
-        ETM_CGAVD_PKE_LEN_CALC_SIGNr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12a3,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_pke_len_calc_sign_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rd_cpu_or_ram",
-        ETM_CGAVD_RD_CPU_OR_RAMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_etm_cgavd_rd_cpu_or_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "q_len_update_disable",
-        ETM_CGAVD_Q_LEN_UPDATE_DISABLEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12a5,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_etm_cgavd_q_len_update_disable_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_dp_sel",
-        ETM_CGAVD_CGAVD_DP_SELr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12ad,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        9,
-        g_etm_cgavd_cgavd_dp_sel_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_sub_en",
-        ETM_CGAVD_CGAVD_SUB_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12e6,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_etm_cgavd_cgavd_sub_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "default_start_queue",
-        ETM_CGAVD_DEFAULT_START_QUEUEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12e7,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_default_start_queue_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "default_finish_queue",
-        ETM_CGAVD_DEFAULT_FINISH_QUEUEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_default_finish_queue_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "protocol_start_queue",
-        ETM_CGAVD_PROTOCOL_START_QUEUEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12e9,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_protocol_start_queue_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "protocol_finish_queue",
-        ETM_CGAVD_PROTOCOL_FINISH_QUEUEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12ea,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_protocol_finish_queue_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "uniform_td_th",
-        ETM_CGAVD_UNIFORM_TD_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12eb,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_uniform_td_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "uniform_td_th_en",
-        ETM_CGAVD_UNIFORM_TD_TH_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_uniform_td_th_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_cfg_fc",
-        ETM_CGAVD_CGAVD_CFG_FCr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12ed,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_cfg_fc_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_cfg_no_fc",
-        ETM_CGAVD_CGAVD_CFG_NO_FCr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12ee,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_cfg_no_fc_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_force_imem_omem",
-        ETM_CGAVD_CGAVD_FORCE_IMEM_OMEMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_cgavd_cgavd_force_imem_omem_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_sys_q_len_l",
-        ETM_CGAVD_CGAVD_SYS_Q_LEN_Lr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12f1,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_sys_q_len_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "default_queue_en",
-        ETM_CGAVD_DEFAULT_QUEUE_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12f5,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_default_queue_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "protocol_queue_en",
-        ETM_CGAVD_PROTOCOL_QUEUE_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12f6,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_protocol_queue_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tc_flowid_dat",
-        ETM_CGAVD_CFG_TC_FLOWID_DATr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x1400,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_cfg_tc_flowid_dat_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_td_th",
-        ETM_CGAVD_FLOW_TD_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x40000,
-        (32/8),
-        0,
-        0x23FF + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_flow_td_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_ca_mtd",
-        ETM_CGAVD_FLOW_CA_MTDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x80000,
-        (32/8),
-        0,
-        0x23FF + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_flow_ca_mtd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_dynamic_th_en",
-        ETM_CGAVD_FLOW_DYNAMIC_TH_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0xc0000,
-        (32/8),
-        0,
-        0x23FF + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_flow_dynamic_th_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_num",
-        ETM_CGAVD_PP_NUMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x100000,
-        (32/8),
-        0,
-        0x23FF + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_pp_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_q_len",
-        ETM_CGAVD_FLOW_Q_LENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x140000,
-        (32/8),
-        0,
-        0x23FF + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_flow_q_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_wred_grp",
-        ETM_CGAVD_FLOW_WRED_GRPr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x180000,
-        (32/8),
-        0,
-        0x23FF + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_flow_wred_grp_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_avg_q_len",
-        ETM_CGAVD_FLOW_AVG_Q_LENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x1c0000,
-        (32/8),
-        0,
-        0x23FF + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_flow_avg_q_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qos_sign",
-        ETM_CGAVD_QOS_SIGNr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x200000,
-        (32/8),
-        0,
-        0x23FF + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_qos_sign_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "q_pri",
-        ETM_CGAVD_Q_PRIr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x240000,
-        (32/8),
-        0,
-        0x23FF + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_q_pri_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_tm_itmd_rd_low",
-        ETM_CGAVD_ODMA_TM_ITMD_RD_LOWr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x250000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_odma_tm_itmd_rd_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_tm_itmd_rd_mid",
-        ETM_CGAVD_ODMA_TM_ITMD_RD_MIDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x250001,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_odma_tm_itmd_rd_mid_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_tm_itmd_rd_high",
-        ETM_CGAVD_ODMA_TM_ITMD_RD_HIGHr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x250002,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_odma_tm_itmd_rd_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_stat_pkt_len",
-        ETM_CGAVD_CGAVD_STAT_PKT_LENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x250003,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_cgavd_cgavd_stat_pkt_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_stat_qnum",
-        ETM_CGAVD_CGAVD_STAT_QNUMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x250004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_cgavd_cgavd_stat_qnum_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_stat_dp",
-        ETM_CGAVD_CGAVD_STAT_DPr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x250005,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_stat_dp_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_num0",
-        ETM_CGAVD_FLOW_NUM0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow_num0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_num1",
-        ETM_CGAVD_FLOW_NUM1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260001,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow_num1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_num2",
-        ETM_CGAVD_FLOW_NUM2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260002,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow_num2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_num3",
-        ETM_CGAVD_FLOW_NUM3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260003,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow_num3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_num4",
-        ETM_CGAVD_FLOW_NUM4r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow_num4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow0_imem_cnt",
-        ETM_CGAVD_FLOW0_IMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow0_imem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow1_imem_cnt",
-        ETM_CGAVD_FLOW1_IMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260011,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow1_imem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow2_imem_cnt",
-        ETM_CGAVD_FLOW2_IMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260012,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow2_imem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow3_imem_cnt",
-        ETM_CGAVD_FLOW3_IMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260013,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow3_imem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow4_imem_cnt",
-        ETM_CGAVD_FLOW4_IMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow4_imem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow0_drop_cnt",
-        ETM_CGAVD_FLOW0_DROP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow0_drop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow1_drop_cnt",
-        ETM_CGAVD_FLOW1_DROP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260031,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow1_drop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow2_drop_cnt",
-        ETM_CGAVD_FLOW2_DROP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260032,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow2_drop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow3_drop_cnt",
-        ETM_CGAVD_FLOW3_DROP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260033,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow3_drop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow4_drop_cnt",
-        ETM_CGAVD_FLOW4_DROP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow4_drop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fc_count_mode",
-        ETM_CGAVD_FC_COUNT_MODEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x264000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_fc_count_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_cgavd_fc_num",
-        ETM_CGAVD_QMU_CGAVD_FC_NUMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x264100,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_cgavd_qmu_cgavd_fc_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_odma_fc_num",
-        ETM_CGAVD_CGAVD_ODMA_FC_NUMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x264101,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_cgavd_cgavd_odma_fc_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_offset",
-        ETM_CGAVD_CFG_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x290000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cfg_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_init_done",
-        ETM_TMMU_TMMU_INIT_DONEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0001,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_init_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_int_mask_1",
-        ETM_TMMU_TMMU_INT_MASK_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x002,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        27,
-        g_etm_tmmu_tmmu_int_mask_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_int_mask_2",
-        ETM_TMMU_TMMU_INT_MASK_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0003,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        17,
-        g_etm_tmmu_tmmu_int_mask_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_tm_pure_imem_en",
-        ETM_TMMU_CFGMT_TM_PURE_IMEM_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_tm_pure_imem_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_force_ddr_rdy_cfg",
-        ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0005,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_force_ddr_rdy_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pd_order_fifo_aful_th",
-        ETM_TMMU_PD_ORDER_FIFO_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0007,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_pd_order_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cached_pd_fifo_aful_th",
-        ETM_TMMU_CACHED_PD_FIFO_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cached_pd_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "wr_cmd_fifo_aful_th",
-        ETM_TMMU_WR_CMD_FIFO_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_wr_cmd_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "imem_enq_rd_fifo_aful_th",
-        ETM_TMMU_IMEM_ENQ_RD_FIFO_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_imem_enq_rd_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "imem_enq_drop_fifo_aful_th",
-        ETM_TMMU_IMEM_ENQ_DROP_FIFO_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_imem_enq_drop_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "imem_deq_drop_fifo_aful_th",
-        ETM_TMMU_IMEM_DEQ_DROP_FIFO_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_imem_deq_drop_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "imem_deq_rd_fifo_aful_th",
-        ETM_TMMU_IMEM_DEQ_RD_FIFO_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_imem_deq_rd_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_states_1",
-        ETM_TMMU_TMMU_STATES_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0011,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        27,
-        g_etm_tmmu_tmmu_states_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_states_2",
-        ETM_TMMU_TMMU_STATES_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0012,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        17,
-        g_etm_tmmu_tmmu_states_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "shap_ind_cmd",
-        ETM_SHAP_SHAP_IND_CMDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_etm_shap_shap_ind_cmd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "shap_ind_sta",
-        ETM_SHAP_SHAP_IND_STAr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_shap_ind_sta_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "shap_ind_data0",
-        ETM_SHAP_SHAP_IND_DATA0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_shap_ind_data0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "shap_ind_data1",
-        ETM_SHAP_SHAP_IND_DATA1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_shap_ind_data1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "full_threshold",
-        ETM_SHAP_FULL_THRESHOLDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_full_threshold_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "empty_threshold",
-        ETM_SHAP_EMPTY_THRESHOLDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_empty_threshold_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "shap_sta_init_cfg",
-        ETM_SHAP_SHAP_STA_INIT_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_shap_shap_sta_init_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "shap_cfg_init_cfg",
-        ETM_SHAP_SHAP_CFG_INIT_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_shap_shap_cfg_init_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "token_mode_switch",
-        ETM_SHAP_TOKEN_MODE_SWITCHr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_token_mode_switch_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "token_grain",
-        ETM_SHAP_TOKEN_GRAINr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x21,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_token_grain_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crd_grain",
-        ETM_SHAP_CRD_GRAINr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x22,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_crd_grain_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "shap_stat_ctrl",
-        ETM_SHAP_SHAP_STAT_CTRLr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x37,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_shap_stat_ctrl_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "token_stat_id",
-        ETM_SHAP_TOKEN_STAT_IDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x38,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_token_stat_id_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "token_stat",
-        ETM_SHAP_TOKEN_STATr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x39,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_token_stat_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "shap_stat_clk_cnt",
-        ETM_SHAP_SHAP_STAT_CLK_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x74,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_shap_stat_clk_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "shap_bucket_map_tbl",
-        ETM_SHAP_SHAP_BUCKET_MAP_TBLr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x80000000 + 0x000000,
-        (64/8),
-        0,
-        0xABFF + 1,
-        0,
-        1,
-        1,
-        g_etm_shap_shap_bucket_map_tbl_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "bkt_para_tbl",
-        ETM_SHAP_BKT_PARA_TBLr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x80000000 + 0x100000,
-        (64/8),
-        0,
-        0xAFF + 1,
-        0,
-        1,
-        2,
-        g_etm_shap_bkt_para_tbl_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "credit_en",
-        ETM_CRDT_CREDIT_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0001,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_credit_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crt_inter1",
-        ETM_CRDT_CRT_INTER1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0002,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crt_inter1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "db_token",
-        ETM_CRDT_DB_TOKENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0003,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_db_token_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crs_flt_cfg",
-        ETM_CRDT_CRS_FLT_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crs_flt_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "th_sp",
-        ETM_CRDT_TH_SPr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0005,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_th_sp_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "th_wfq_fq",
-        ETM_CRDT_TH_WFQ_FQr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0006,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_crdt_th_wfq_fq_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "th_wfq2_fq2",
-        ETM_CRDT_TH_WFQ2_FQ2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0007,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_crdt_th_wfq2_fq2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "th_wfq4_fq4",
-        ETM_CRDT_TH_WFQ4_FQ4r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_crdt_th_wfq4_fq4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_state",
-        ETM_CRDT_CFG_STATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0009,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_cfg_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_ind_cmd",
-        ETM_CRDT_CRDT_IND_CMDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_etm_crdt_crdt_ind_cmd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_ind_sta",
-        ETM_CRDT_CRDT_IND_STAr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crdt_ind_sta_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_ind_data0",
-        ETM_CRDT_CRDT_IND_DATA0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crdt_ind_data0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_ind_data1",
-        ETM_CRDT_CRDT_IND_DATA1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crdt_ind_data1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_state",
-        ETM_CRDT_CRDT_STATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_crdt_crdt_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_id_0",
-        ETM_CRDT_STAT_QUE_ID_0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x10,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_stat_que_id_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_id_1",
-        ETM_CRDT_STAT_QUE_ID_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x11,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_stat_que_id_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_id_2",
-        ETM_CRDT_STAT_QUE_ID_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_stat_que_id_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_id_3",
-        ETM_CRDT_STAT_QUE_ID_3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x13,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_stat_que_id_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_id_4",
-        ETM_CRDT_STAT_QUE_ID_4r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x14,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_stat_que_id_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_id_5",
-        ETM_CRDT_STAT_QUE_ID_5r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x15,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_stat_que_id_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_id_6",
-        ETM_CRDT_STAT_QUE_ID_6r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x16,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_stat_que_id_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_id_7",
-        ETM_CRDT_STAT_QUE_ID_7r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x17,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_stat_que_id_7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_id_8",
-        ETM_CRDT_STAT_QUE_ID_8r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x18,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_stat_que_id_8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_id_9",
-        ETM_CRDT_STAT_QUE_ID_9r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x19,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_stat_que_id_9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_id_10",
-        ETM_CRDT_STAT_QUE_ID_10r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_stat_que_id_10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_id_11",
-        ETM_CRDT_STAT_QUE_ID_11r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_stat_que_id_11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_id_12",
-        ETM_CRDT_STAT_QUE_ID_12r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_stat_que_id_12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_id_13",
-        ETM_CRDT_STAT_QUE_ID_13r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_stat_que_id_13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_id_14",
-        ETM_CRDT_STAT_QUE_ID_14r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_stat_que_id_14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_id_15",
-        ETM_CRDT_STAT_QUE_ID_15r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_stat_que_id_15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_credit",
-        ETM_CRDT_STAT_QUE_CREDITr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x20,
-        (32/8),
-        0,
-        0x0f + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_stat_que_credit_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_cfg_ram_init",
-        ETM_CRDT_CRDT_CFG_RAM_INITr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x7a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_crdt_crdt_cfg_ram_init_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_sta_ram_init",
-        ETM_CRDT_CRDT_STA_RAM_INITr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x7b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_crdt_crdt_sta_ram_init_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crs_que_id",
-        ETM_CRDT_CRS_QUE_IDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x86,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crs_que_id_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_crs_end_state",
-        ETM_CRDT_QMU_CRS_END_STATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x87,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_qmu_crs_end_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "shap_rdy",
-        ETM_CRDT_SHAP_RDYr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x90,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_shap_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "shap_int_reg",
-        ETM_CRDT_SHAP_INT_REGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x91,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_shap_int_reg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "shap_int_mask_reg",
-        ETM_CRDT_SHAP_INT_MASK_REGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x92,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_shap_int_mask_reg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "token_state_almost_empty_th",
-        ETM_CRDT_TOKEN_STATE_ALMOST_EMPTY_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x93,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_token_state_almost_empty_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "token_state_empty_th",
-        ETM_CRDT_TOKEN_STATE_EMPTY_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x94,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_token_state_empty_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "full_th",
-        ETM_CRDT_FULL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x95,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_full_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_c_level_shap_en",
-        ETM_CRDT_PP_C_LEVEL_SHAP_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x96,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_pp_c_level_shap_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "enq_token_th",
-        ETM_CRDT_ENQ_TOKEN_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x97,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_enq_token_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_tokenq_level1_qstate_weight_cir",
-        ETM_CRDT_PP_TOKENQ_LEVEL1_QSTATE_WEIGHT_CIRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x98,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_crdt_pp_tokenq_level1_qstate_weight_cir_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_idle_weight_level1_cir",
-        ETM_CRDT_PP_IDLE_WEIGHT_LEVEL1_CIRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x99,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_pp_idle_weight_level1_cir_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rci_grade_th_0_cfg",
-        ETM_CRDT_RCI_GRADE_TH_0_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xc0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_rci_grade_th_0_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rci_grade_th_1_cfg",
-        ETM_CRDT_RCI_GRADE_TH_1_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xc1,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_rci_grade_th_1_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rci_grade_th_2_cfg",
-        ETM_CRDT_RCI_GRADE_TH_2_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xc2,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_rci_grade_th_2_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rci_grade_th_3_cfg",
-        ETM_CRDT_RCI_GRADE_TH_3_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xc3,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_rci_grade_th_3_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rci_grade_th_4_cfg",
-        ETM_CRDT_RCI_GRADE_TH_4_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xc4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_rci_grade_th_4_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rci_grade_th_5_cfg",
-        ETM_CRDT_RCI_GRADE_TH_5_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xc5,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_rci_grade_th_5_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rci_grade_th_6_cfg",
-        ETM_CRDT_RCI_GRADE_TH_6_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xc6,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_rci_grade_th_6_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow_del_cmd",
-        ETM_CRDT_FLOW_DEL_CMDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x00f1,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_etm_crdt_flow_del_cmd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_clr",
-        ETM_CRDT_CNT_CLRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x00f2,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_cnt_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_int_bus",
-        ETM_CRDT_CRDT_INT_BUSr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x00f3,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        19,
-        g_etm_crdt_crdt_int_bus_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_int_mask",
-        ETM_CRDT_CRDT_INT_MASKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x00f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crdt_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_weight_together",
-        ETM_CRDT_CFG_WEIGHT_TOGETHERr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x00f9,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_cfg_weight_together_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "weight",
-        ETM_CRDT_WEIGHTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x00fa,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_crdt_weight_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dev_sp_state",
-        ETM_CRDT_DEV_SP_STATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x11e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_dev_sp_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dev_crs",
-        ETM_CRDT_DEV_CRSr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x11f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_dev_crs_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "congest_token_disable_31_0",
-        ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x130,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_congest_token_disable_31_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "congest_token_disable_63_32",
-        ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x131,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_congest_token_disable_63_32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_interval_en_cfg",
-        ETM_CRDT_CRDT_INTERVAL_EN_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0139,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crdt_interval_en_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "q_token_staue_cfg",
-        ETM_CRDT_Q_TOKEN_STAUE_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x150,
-        (32/8),
-        0,
-        0xf + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_q_token_staue_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "q_token_dist_cnt",
-        ETM_CRDT_Q_TOKEN_DIST_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x160,
-        (32/8),
-        0,
-        0xf + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_q_token_dist_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "q_token_dec_cnt",
-        ETM_CRDT_Q_TOKEN_DEC_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x170,
-        (32/8),
-        0,
-        0xf + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_q_token_dec_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_weight_ram",
-        ETM_CRDT_PP_WEIGHT_RAMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x41000000,
-        (32/8),
-        0,
-        0x003F + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_pp_weight_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_cbs_shape_en_ram",
-        ETM_CRDT_PP_CBS_SHAPE_EN_RAMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x42000000,
-        (32/8),
-        0,
-        0x003f + 1,
-        0,
-        1,
-        2,
-        g_etm_crdt_pp_cbs_shape_en_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_next_pc_q_state_ram",
-        ETM_CRDT_PP_NEXT_PC_Q_STATE_RAMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x43000000,
-        (32/8),
-        0,
-        0x003f + 1,
-        0,
-        1,
-        3,
-        g_etm_crdt_pp_next_pc_q_state_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dev_interval",
-        ETM_CRDT_DEV_INTERVALr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x50000000,
-        (32/8),
-        0,
-        0x0127 + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_dev_interval_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dev_wfq_cnt",
-        ETM_CRDT_DEV_WFQ_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x51000000,
-        (32/8),
-        0,
-        0x0007 + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_dev_wfq_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dev_wfq_state",
-        ETM_CRDT_DEV_WFQ_STATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x52000000,
-        (32/8),
-        0,
-        0x0007 + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_dev_wfq_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dev_active_head_ptr",
-        ETM_CRDT_DEV_ACTIVE_HEAD_PTRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x53000000,
-        (32/8),
-        0,
-        0x0007 + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_dev_active_head_ptr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dev_active_tail_ptr",
-        ETM_CRDT_DEV_ACTIVE_TAIL_PTRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x54000000,
-        (32/8),
-        0,
-        0x0007 + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_dev_active_tail_ptr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dev_unactive_head_ptr",
-        ETM_CRDT_DEV_UNACTIVE_HEAD_PTRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x55000000,
-        (32/8),
-        0,
-        0x0037 + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_dev_unactive_head_ptr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dev_unactive_tail_ptr",
-        ETM_CRDT_DEV_UNACTIVE_TAIL_PTRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x56000000,
-        (32/8),
-        0,
-        0x0037 + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_dev_unactive_tail_ptr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_weight",
-        ETM_CRDT_PP_WEIGHTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x44000000,
-        (32/8),
-        0,
-        0x003F + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_pp_weight_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_que_state",
-        ETM_CRDT_PP_QUE_STATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x46000000,
-        (32/8),
-        0,
-        0x003f + 1,
-        0,
-        1,
-        5,
-        g_etm_crdt_pp_que_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_next_ptr",
-        ETM_CRDT_PP_NEXT_PTRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x49000000,
-        (32/8),
-        0,
-        0x003f + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_pp_next_ptr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_cfg",
-        ETM_CRDT_PP_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x4a000000,
-        (32/8),
-        0,
-        0x003f + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_pp_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_up_ptr",
-        ETM_CRDT_PP_UP_PTRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x4b000000,
-        (32/8),
-        0,
-        0x003f + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_pp_up_ptr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "credit_drop_num",
-        ETM_CRDT_CREDIT_DROP_NUMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x180,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_credit_drop_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_id_lv0",
-        ETM_CRDT_SE_ID_LV0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x181,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_se_id_lv0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_id_lv1",
-        ETM_CRDT_SE_ID_LV1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x182,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_se_id_lv1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_id_lv2",
-        ETM_CRDT_SE_ID_LV2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x183,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_se_id_lv2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_id_lv3",
-        ETM_CRDT_SE_ID_LV3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x184,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_se_id_lv3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_id_lv4",
-        ETM_CRDT_SE_ID_LV4r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x185,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_se_id_lv4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "que_id",
-        ETM_CRDT_QUE_IDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x186,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_que_id_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_info_lv0",
-        ETM_CRDT_SE_INFO_LV0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x187,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_etm_crdt_se_info_lv0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_info_lv1",
-        ETM_CRDT_SE_INFO_LV1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x188,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_etm_crdt_se_info_lv1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_info_lv2",
-        ETM_CRDT_SE_INFO_LV2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x189,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_etm_crdt_se_info_lv2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_info_lv3",
-        ETM_CRDT_SE_INFO_LV3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x18a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_etm_crdt_se_info_lv3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_info_lv4",
-        ETM_CRDT_SE_INFO_LV4r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x18b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_etm_crdt_se_info_lv4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "que_state",
-        ETM_CRDT_QUE_STATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x18c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_que_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "eir_off_in_advance",
-        ETM_CRDT_EIR_OFF_IN_ADVANCEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x190,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_eir_off_in_advance_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "double_level_shap_prevent",
-        ETM_CRDT_DOUBLE_LEVEL_SHAP_PREVENTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x192,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_double_level_shap_prevent_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "add_store_cycle",
-        ETM_CRDT_ADD_STORE_CYCLEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x193,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_add_store_cycle_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tflag2_wr_flag_sum",
-        ETM_CRDT_TFLAG2_WR_FLAG_SUMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x194,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_tflag2_wr_flag_sum_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flowque_para_tbl",
-        ETM_CRDT_FLOWQUE_PARA_TBLr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x00000000 + 0x200000,
-        (32/8),
-        0,
-        0x47FF + 1,
-        0,
-        1,
-        3,
-        g_etm_crdt_flowque_para_tbl_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_para_tbl",
-        ETM_CRDT_SE_PARA_TBLr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x80000000 + 0x300000,
-        (64/8),
-        0,
-        0x63FF + 1,
-        0,
-        1,
-        5,
-        g_etm_crdt_se_para_tbl_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flowque_ins_tbl",
-        ETM_CRDT_FLOWQUE_INS_TBLr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x00000000 + 0x400000,
-        (32/8),
-        0,
-        0x47FF + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_flowque_ins_tbl_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_ins_tbl",
-        ETM_CRDT_SE_INS_TBLr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x00000000 + 0x500000,
-        (32/8),
-        0,
-        0x63FF + 1,
-        0,
-        1,
-        2,
-        g_etm_crdt_se_ins_tbl_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "eir_crs_filter_tbl",
-        ETM_CRDT_EIR_CRS_FILTER_TBLr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x00000000 + 0x600000,
-        (32/8),
-        0,
-        0x23FF + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_eir_crs_filter_tbl_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_cfg_done",
-        ETM_QMU_QCFG_QLIST_CFG_DONEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x10,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qcfg_qlist_cfg_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qsch_credit_value",
-        ETM_QMU_QCFG_QSCH_CREDIT_VALUEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x11,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qcfg_qsch_credit_value_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qsch_crbal_init_value",
-        ETM_QMU_QCFG_QSCH_CRBAL_INIT_VALUEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qcfg_qsch_crbal_init_value_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qsch_crbal_init_mask",
-        ETM_QMU_QCFG_QSCH_CRBAL_INIT_MASKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x13,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qcfg_qsch_crbal_init_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cmdsch_rd_cmd_aful_th",
-        ETM_QMU_CMDSCH_RD_CMD_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x22,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cmdsch_rd_cmd_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_port_fc_interval",
-        ETM_QMU_CFG_PORT_FC_INTERVALr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x23,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_port_fc_interval_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_csch_aged_cfg",
-        ETM_QMU_QCFG_CSCH_AGED_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x24,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qcfg_csch_aged_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_csch_aged_scan_time",
-        ETM_QMU_QCFG_CSCH_AGED_SCAN_TIMEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x25,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qcfg_csch_aged_scan_time_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qmu_qlist_state_query",
-        ETM_QMU_QCFG_QMU_QLIST_STATE_QUERYr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x26,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        19,
-        g_etm_qmu_qcfg_qmu_qlist_state_query_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qsch_crbal_drop_en",
-        ETM_QMU_CFGMT_QSCH_CRBAL_DROP_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x27,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_qmu_cfgmt_qsch_crbal_drop_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_wlist_qnum_fifo_aful_th",
-        ETM_QMU_CFGMT_WLIST_QNUM_FIFO_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x29,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_wlist_qnum_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_csw_pkt_blk_mode",
-        ETM_QMU_QCFG_CSW_PKT_BLK_MODEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x28,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qcfg_csw_pkt_blk_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_ram_init_cancel",
-        ETM_QMU_QCFG_QLIST_RAM_INIT_CANCELr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qcfg_qlist_ram_init_cancel_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qsch_crbal_transfer_mode",
-        ETM_QMU_QCFG_QSCH_CRBAL_TRANSFER_MODEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_qmu_qcfg_qsch_crbal_transfer_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_qclr_interval",
-        ETM_QMU_QCFG_QLIST_QCLR_INTERVALr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qcfg_qlist_qclr_interval_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qsch_qclr_rate",
-        ETM_QMU_QCFG_QSCH_QCLR_RATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qcfg_qsch_qclr_rate_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_ddr_random",
-        ETM_QMU_QCFG_QLIST_DDR_RANDOMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qcfg_qlist_ddr_random_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qlist_pds_fifo_afull_th",
-        ETM_QMU_CFGMT_QLIST_PDS_FIFO_AFULL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x30,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_qlist_pds_fifo_afull_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_sop_cmd_fifo_afull_th",
-        ETM_QMU_CFGMT_SOP_CMD_FIFO_AFULL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x31,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_sop_cmd_fifo_afull_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_non_sop_cmd_fifo_afull_th",
-        ETM_QMU_CFGMT_NON_SOP_CMD_FIFO_AFULL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x32,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_non_sop_cmd_fifo_afull_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_mmu_data_fifo_afull_th",
-        ETM_QMU_CFGMT_MMU_DATA_FIFO_AFULL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x33,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_mmu_data_fifo_afull_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_bank_ept_th",
-        ETM_QMU_QCFG_QLIST_BANK_EPT_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x34,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qcfg_qlist_bank_ept_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "random_bypass_en",
-        ETM_QMU_RANDOM_BYPASS_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x36,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_random_bypass_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_crs_spd_bypass",
-        ETM_QMU_CFGMT_CRS_SPD_BYPASSr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x37,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_crs_spd_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_crs_interval",
-        ETM_QMU_CFGMT_CRS_INTERVALr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x38,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_crs_interval_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_auto_credit_control_en",
-        ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x3b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_auto_credit_control_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_autocrfrstque",
-        ETM_QMU_CFG_QSCH_AUTOCRFRSTQUEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x3c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_autocrfrstque_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_autocrlastque",
-        ETM_QMU_CFG_QSCH_AUTOCRLASTQUEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x3d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_autocrlastque_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_autocreditrate",
-        ETM_QMU_CFG_QSCH_AUTOCREDITRATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x3e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_autocreditrate_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_scanfrstque",
-        ETM_QMU_CFG_QSCH_SCANFRSTQUEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x51,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_scanfrstque_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_scanlastque",
-        ETM_QMU_CFG_QSCH_SCANLASTQUEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x52,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_scanlastque_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_scanrate",
-        ETM_QMU_CFG_QSCH_SCANRATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x53,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_scanrate_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_scan_en",
-        ETM_QMU_CFG_QSCH_SCAN_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x54,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_scan_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qsch_rd_credit_fifo_rate",
-        ETM_QMU_CFGMT_QSCH_RD_CREDIT_FIFO_RATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x7c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_qsch_rd_credit_fifo_rate_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_bdep",
-        ETM_QMU_QCFG_QLIST_BDEPr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x9a7,
-        (32/8),
-        0,
-        0x3F + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_bdep_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_bhead",
-        ETM_QMU_QCFG_QLIST_BHEADr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x9e7,
-        (32/8),
-        0,
-        0x3F + 1,
-        0,
-        1,
-        2,
-        g_etm_qmu_qcfg_qlist_bhead_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_btail",
-        ETM_QMU_QCFG_QLIST_BTAILr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0xa27,
-        (32/8),
-        0,
-        0x3F + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_btail_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qsch_shap_param",
-        ETM_QMU_QCFG_QSCH_SHAP_PARAMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0xfc,
-        (32/8),
-        0,
-        0x3F + 1,
-        0,
-        1,
-        3,
-        g_etm_qmu_qcfg_qsch_shap_param_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qsch_shap_token",
-        ETM_QMU_QCFG_QSCH_SHAP_TOKENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x185,
-        (32/8),
-        0,
-        0x3F + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qsch_shap_token_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qsch_shap_offset",
-        ETM_QMU_QCFG_QSCH_SHAP_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x20e,
-        (32/8),
-        0,
-        0x3F + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qsch_shap_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qsch_crs_eir_th",
-        ETM_QMU_QCFG_QSCH_CRS_EIR_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x250,
-        (32/8),
-        0,
-        0xF + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qsch_crs_eir_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qsch_crs_th1",
-        ETM_QMU_QCFG_QSCH_CRS_TH1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x297,
-        (32/8),
-        0,
-        0xF + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qsch_crs_th1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qsch_crs_th2",
-        ETM_QMU_QCFG_QSCH_CRS_TH2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x2a7,
-        (32/8),
-        0,
-        0xF + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qsch_crs_th2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_csch_congest_th",
-        ETM_QMU_QCFG_CSCH_CONGEST_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x2b7,
-        (32/8),
-        0,
-        0x3F + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_csch_congest_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_csch_sp_fc_th",
-        ETM_QMU_QCFG_CSCH_SP_FC_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x330,
-        (32/8),
-        0,
-        0x140 + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_csch_sp_fc_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_csw_shap_parameter",
-        ETM_QMU_QCFG_CSW_SHAP_PARAMETERr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x5d0,
-        (32/8),
-        0,
-        0x3F + 1,
-        0,
-        1,
-        2,
-        g_etm_qmu_qcfg_csw_shap_parameter_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_rd_release_aful_th",
-        ETM_QMU_CFGMT_RD_RELEASE_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x58e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_rd_release_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_drop_imem_release_fifo_aful_th",
-        ETM_QMU_CFGMT_DROP_IMEM_RELEASE_FIFO_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x58f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_drop_imem_release_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_nnh_rd_buf_aful_th",
-        ETM_QMU_CFGMT_NNH_RD_BUF_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x590,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_nnh_rd_buf_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_pid_use_inall",
-        ETM_QMU_CFG_PID_USE_INALLr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x591,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_pid_use_inall_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_pid_round_th",
-        ETM_QMU_CFG_PID_ROUND_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x592,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_pid_round_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_credit_fifo_afull_th",
-        ETM_QMU_CFGMT_CREDIT_FIFO_AFULL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x593,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_credit_fifo_afull_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_scan_fifo_afull_th",
-        ETM_QMU_CFGMT_SCAN_FIFO_AFULL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x594,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_scan_fifo_afull_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_small_fifo_aful_th",
-        ETM_QMU_CFGMT_SMALL_FIFO_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x595,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_small_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_free_addr_fifo_aful_th",
-        ETM_QMU_CFGMT_FREE_ADDR_FIFO_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x596,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_free_addr_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_enq_rpt_fifo_aful_th",
-        ETM_QMU_CFGMT_ENQ_RPT_FIFO_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x597,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_enq_rpt_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_csw_shap_token_depth",
-        ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTHr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x656,
-        (32/8),
-        0,
-        0x3F + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_csw_shap_token_depth_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_csw_shap_offset_value",
-        ETM_QMU_QCFG_CSW_SHAP_OFFSET_VALUEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x6cf,
-        (32/8),
-        0,
-        0x3F + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_csw_shap_offset_value_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_csw_fc_offset_value",
-        ETM_QMU_QCFG_CSW_FC_OFFSET_VALUEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x750,
-        (32/8),
-        0,
-        0x3F + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_csw_fc_offset_value_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_init_done_state",
-        ETM_QMU_QMU_INIT_DONE_STATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_etm_qmu_qmu_init_done_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csw_qcfg_port_shap_rdy_0",
-        ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2001,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csw_qcfg_port_shap_rdy_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csw_qcfg_port_shap_rdy_1",
-        ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2002,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csw_qcfg_port_shap_rdy_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qlist_cfgmt_ram_init_done",
-        ETM_QMU_QLIST_CFGMT_RAM_INIT_DONEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2015,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        8,
-        g_etm_qmu_qlist_cfgmt_ram_init_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qlist_cfgmt_ram_ecc_err",
-        ETM_QMU_QLIST_CFGMT_RAM_ECC_ERRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2016,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        30,
-        g_etm_qmu_qlist_cfgmt_ram_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qlist_cfgmt_ram_slot_err",
-        ETM_QMU_QLIST_CFGMT_RAM_SLOT_ERRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2017,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        20,
-        g_etm_qmu_qlist_cfgmt_ram_slot_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qsch_cfgmt_ram_ecc",
-        ETM_QMU_QSCH_CFGMT_RAM_ECCr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        27,
-        g_etm_qmu_qsch_cfgmt_ram_ecc_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qlist_cfgmt_fifo_state",
-        ETM_QMU_QLIST_CFGMT_FIFO_STATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2019,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        26,
-        g_etm_qmu_qlist_cfgmt_fifo_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qlist_qcfg_clr_done",
-        ETM_QMU_QLIST_QCFG_CLR_DONEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x201a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qlist_qcfg_clr_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_int_mask1",
-        ETM_QMU_QMU_INT_MASK1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x201b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_int_mask1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_int_mask2",
-        ETM_QMU_QMU_INT_MASK2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x201c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_int_mask2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_int_mask3",
-        ETM_QMU_QMU_INT_MASK3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x201d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_int_mask3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_int_mask4",
-        ETM_QMU_QMU_INT_MASK4r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x201e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_int_mask4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_int_mask5",
-        ETM_QMU_QMU_INT_MASK5r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x201f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_int_mask5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_int_mask6",
-        ETM_QMU_QMU_INT_MASK6r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2013,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_int_mask6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cmd_sch_cfgmt_fifo_state",
-        ETM_QMU_CMD_SCH_CFGMT_FIFO_STATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        26,
-        g_etm_qmu_cmd_sch_cfgmt_fifo_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qlist_r_bcnt",
-        ETM_QMU_QLIST_R_BCNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x60000,
-        (32/8),
-        0,
-        0x23ff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qlist_r_bcnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qsch_rw_crbal",
-        ETM_QMU_QSCH_RW_CRBALr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x70000,
-        (32/8),
-        0,
-        0x23ff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qsch_rw_crbal_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qsch_rw_crs",
-        ETM_QMU_QSCH_RW_CRSr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x80000,
-        (32/8),
-        0,
-        0x23ff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qsch_rw_crs_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qsch_r_wlist_empty",
-        ETM_QMU_QSCH_R_WLIST_EMPTYr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0xa0000,
-        (32/8),
-        0,
-        0xfff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qsch_r_wlist_empty_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_baram_rd",
-        ETM_QMU_QCFG_QLIST_BARAM_RDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0xe0000,
-        (32/8),
-        0,
-        0x7ff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_baram_rd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qsch_crbal_fb_rw",
-        ETM_QMU_QCFG_QSCH_CRBAL_FB_RWr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0xb0000,
-        (32/8),
-        0,
-        0x23ff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qsch_crbal_fb_rw_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_grp0_bank",
-        ETM_QMU_QCFG_QLIST_GRP0_BANKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x7c1,
-        (32/8),
-        0,
-        0x3f + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_grp0_bank_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_grp1_bank",
-        ETM_QMU_QCFG_QLIST_GRP1_BANKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x801,
-        (32/8),
-        0,
-        0x3f + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_grp1_bank_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_grp2_bank",
-        ETM_QMU_QCFG_QLIST_GRP2_BANKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x841,
-        (32/8),
-        0,
-        0x3f + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_grp2_bank_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_grp3_bank",
-        ETM_QMU_QCFG_QLIST_GRP3_BANKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x881,
-        (32/8),
-        0,
-        0x3f + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_grp3_bank_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_grp4_bank",
-        ETM_QMU_QCFG_QLIST_GRP4_BANKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x8c1,
-        (32/8),
-        0,
-        0x3f + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_grp4_bank_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_grp5_bank",
-        ETM_QMU_QCFG_QLIST_GRP5_BANKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x967,
-        (32/8),
-        0,
-        0x3f + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_grp5_bank_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_grp6_bank",
-        ETM_QMU_QCFG_QLIST_GRP6_BANKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0xc00,
-        (32/8),
-        0,
-        0x3f + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_grp6_bank_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_grp7_bank",
-        ETM_QMU_QCFG_QLIST_GRP7_BANKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0xc40,
-        (32/8),
-        0,
-        0x3f + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_grp7_bank_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_grp",
-        ETM_QMU_QCFG_QLIST_GRPr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x901,
-        (32/8),
-        0,
-        0x3f + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_grp_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_active_to_bank_cfg",
-        ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x941,
-        (32/8),
-        0,
-        0xf + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_cfgmt_active_to_bank_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_ddr_in_mmu_cfg",
-        ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x951,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_cfgmt_ddr_in_mmu_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_ddr_in_qmu_cfg",
-        ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x959,
-        (32/8),
-        0,
-        0x9 + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_cfgmt_ddr_in_qmu_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_bank_to_mmu_cfg",
-        ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0xb00,
-        (32/8),
-        0,
-        0x3f + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_cfgmt_bank_to_mmu_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_bank_to_qmu_cfg",
-        ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0xb40,
-        (32/8),
-        0,
-        0x4f + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_cfgmt_bank_to_qmu_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_grp_ram_n_clr_thd",
-        ETM_QMU_CFGMT_GRP_RAM_N_CLR_THDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe0a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_grp_ram_n_clr_thd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_age_pkt_num",
-        ETM_QMU_CFGMT_AGE_PKT_NUMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe00,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_age_pkt_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_age_multi_interval",
-        ETM_QMU_CFGMT_AGE_MULTI_INTERVALr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe01,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_age_multi_interval_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_pkt_age_en",
-        ETM_QMU_CFGMT_QMU_PKT_AGE_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe02,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_qmu_pkt_age_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_pkt_age_interval",
-        ETM_QMU_CFGMT_QMU_PKT_AGE_INTERVALr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe03,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_qmu_pkt_age_interval_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_pkt_age_start_end",
-        ETM_QMU_CFGMT_QMU_PKT_AGE_START_ENDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe04,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_qmu_cfgmt_qmu_pkt_age_start_end_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_pkt_age_req_aful_th",
-        ETM_QMU_CFGMT_PKT_AGE_REQ_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe05,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_pkt_age_req_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_pkt_age_step_interval",
-        ETM_QMU_CFGMT_PKT_AGE_STEP_INTERVALr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe12,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_pkt_age_step_interval_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_imem_age_mode",
-        ETM_QMU_CFGMT_QMU_IMEM_AGE_MODEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe06,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_etm_qmu_cfgmt_qmu_imem_age_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_imem_qlen_age_interval",
-        ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_INTERVALr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe07,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_qmu_imem_qlen_age_interval_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_imem_time_age_interval",
-        ETM_QMU_CFGMT_QMU_IMEM_TIME_AGE_INTERVALr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe08,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_qmu_imem_time_age_interval_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_imem_qlen_age_thd",
-        ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_THDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe09,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_qmu_imem_qlen_age_thd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_imem_age_step_interval",
-        ETM_QMU_CFGMT_IMEM_AGE_STEP_INTERVALr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe13,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_imem_age_step_interval_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_ecc_bypass_read",
-        ETM_QMU_CFGMT_QMU_ECC_BYPASS_READr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe0b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_qmu_ecc_bypass_read_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_resp_stat_fc_en",
-        ETM_QMU_CFGMT_QMU_RESP_STAT_FC_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe0c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_qmu_resp_stat_fc_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_bank_xoff_pds_mode",
-        ETM_QMU_CFGMT_QMU_BANK_XOFF_PDS_MODEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe10,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_qmu_bank_xoff_pds_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_stat_offset",
-        ETM_QMU_CFGMT_QMU_STAT_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe11,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_qmu_stat_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fc_cnt_mode",
-        ETM_QMU_FC_CNT_MODEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2800,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_fc_cnt_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mmu_qmu_wr_fc_cnt",
-        ETM_QMU_MMU_QMU_WR_FC_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2801,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_mmu_qmu_wr_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mmu_qmu_rd_fc_cnt",
-        ETM_QMU_MMU_QMU_RD_FC_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2802,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_mmu_qmu_rd_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_cgavd_fc_cnt",
-        ETM_QMU_QMU_CGAVD_FC_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2803,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_cgavd_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_pkt_cnt",
-        ETM_QMU_CGAVD_QMU_PKT_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2804,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cgavd_qmu_pkt_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_pktlen_all",
-        ETM_QMU_CGAVD_QMU_PKTLEN_ALLr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2805,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cgavd_qmu_pktlen_all_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "observe_portfc_spec",
-        ETM_QMU_OBSERVE_PORTFC_SPECr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2818,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_observe_portfc_spec_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_lif_portfc_count",
-        ETM_QMU_SPEC_LIF_PORTFC_COUNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2819,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_lif_portfc_count_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_pfc_en",
-        ETM_QMU_CFGMT_QMU_PFC_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_qmu_pfc_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_pfc_mask_1",
-        ETM_QMU_CFGMT_QMU_PFC_MASK_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20e1,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_qmu_pfc_mask_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_pfc_mask_2",
-        ETM_QMU_CFGMT_QMU_PFC_MASK_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20e2,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_qmu_pfc_mask_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_repeat",
-        CFG_PCIE_INT_REPEATr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_int_repeat_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_up_size",
-        CFG_DMA_DMA_UP_SIZEr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_up_size_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "soc_wr_time_out_thresh",
-        CFG_CSR_SOC_WR_TIME_OUT_THRESHr,
-        CFG,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_soc_wr_time_out_thresh_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_shap_param",
-        NPPU_MR_CFG_CFG_SHAP_PARAMr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_mr_cfg_cfg_shap_param_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_shap_token",
-        NPPU_MR_CFG_CFG_SHAP_TOKENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_mr_cfg_cfg_shap_token_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "idle_ptr_fifo_aful_th",
-        NPPU_MR_CFG_IDLE_PTR_FIFO_AFUL_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x003c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_mr_cfg_idle_ptr_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos_port_cfg",
-        NPPU_MR_CFG_MR_COS_PORT_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0104,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_mr_cfg_mr_cos_port_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_status",
-        NPPU_PKTRX_CFG_IND_STATUSr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_ind_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_cmd",
-        NPPU_PKTRX_CFG_IND_CMDr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_nppu_pktrx_cfg_ind_cmd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data0",
-        NPPU_PKTRX_CFG_IND_DATA0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_ind_data0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data1",
-        NPPU_PKTRX_CFG_IND_DATA1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_ind_data1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data2",
-        NPPU_PKTRX_CFG_IND_DATA2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_ind_data2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data3",
-        NPPU_PKTRX_CFG_IND_DATA3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_ind_data3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data4",
-        NPPU_PKTRX_CFG_IND_DATA4r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_ind_data4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data5",
-        NPPU_PKTRX_CFG_IND_DATA5r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_ind_data5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data6",
-        NPPU_PKTRX_CFG_IND_DATA6r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_ind_data6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data7",
-        NPPU_PKTRX_CFG_IND_DATA7r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_ind_data7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tcam_0_cmd",
-        NPPU_PKTRX_CFG_TCAM_0_CMDr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        11,
-        g_nppu_pktrx_cfg_tcam_0_cmd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tcam_1_cmd",
-        NPPU_PKTRX_CFG_TCAM_1_CMDr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x002c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        8,
-        g_nppu_pktrx_cfg_tcam_1_cmd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port_en_0",
-        NPPU_PKTRX_CFG_PORT_EN_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_port_en_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port_en_1",
-        NPPU_PKTRX_CFG_PORT_EN_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_port_en_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port_en_2",
-        NPPU_PKTRX_CFG_PORT_EN_2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_port_en_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port_en_3",
-        NPPU_PKTRX_CFG_PORT_EN_3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x003c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_nppu_pktrx_cfg_port_en_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_port_l2_offset_mode_0",
-        NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_port_l2_offset_mode_1",
-        NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_port_l2_offset_mode_2",
-        NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_port_l2_offset_mode_3",
-        NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port_fc_mode_0",
-        NPPU_PKTRX_CFG_PORT_FC_MODE_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_port_fc_mode_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port_fc_mode_1",
-        NPPU_PKTRX_CFG_PORT_FC_MODE_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_port_fc_mode_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port_fc_mode_2",
-        NPPU_PKTRX_CFG_PORT_FC_MODE_2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_port_fc_mode_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port_fc_mode_3",
-        NPPU_PKTRX_CFG_PORT_FC_MODE_3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x005c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_port_fc_mode_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port_fc_mode_4",
-        NPPU_PKTRX_CFG_PORT_FC_MODE_4r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_port_fc_mode_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port_fc_mode_5",
-        NPPU_PKTRX_CFG_PORT_FC_MODE_5r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_port_fc_mode_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port_fc_mode_6",
-        NPPU_PKTRX_CFG_PORT_FC_MODE_6r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_port_fc_mode_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port_fc_mode_7",
-        NPPU_PKTRX_CFG_PORT_FC_MODE_7r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x006c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_nppu_pktrx_cfg_port_fc_mode_7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_isch_aging_th",
-        NPPU_PKTRX_CFG_CFG_ISCH_AGING_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0070,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_pktrx_cfg_cfg_isch_aging_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isch_fifo_th_0",
-        NPPU_PKTRX_CFG_ISCH_FIFO_TH_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0074,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pktrx_cfg_isch_fifo_th_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isch_cfg_1",
-        NPPU_PKTRX_CFG_ISCH_CFG_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x008c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_nppu_pktrx_cfg_isch_cfg_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tcam_0_vld",
-        NPPU_PKTRX_CFG_TCAM_0_VLDr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00d4,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        4,
-        1,
-        g_nppu_pktrx_cfg_tcam_0_vld_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tcam_1_vld",
-        NPPU_PKTRX_CFG_TCAM_1_VLDr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00f4,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        4,
-        1,
-        g_nppu_pktrx_cfg_tcam_1_vld_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_port_en_mask",
-        NPPU_PKTRX_CFG_CPU_PORT_EN_MASKr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_cpu_port_en_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_glbal_cfg_0",
-        NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_glbal_cfg_1",
-        NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_pktrx_glbal_cfg_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_glbal_cfg_2",
-        NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0200,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_pktrx_glbal_cfg_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_glbal_cfg_3",
-        NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0204,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_pktrx_glbal_cfg_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "nppu_start",
-        NPPU_PKTRX_CFG_NPPU_STARTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0208,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_nppu_start_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_status",
-        NPPU_PKTRX_STAT_IND_STATUSr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_STAT_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_stat_ind_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_cmd",
-        NPPU_PKTRX_STAT_IND_CMDr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_STAT_BASE_ADDR + 0x0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_nppu_pktrx_stat_ind_cmd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data0",
-        NPPU_PKTRX_STAT_IND_DATA0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_STAT_BASE_ADDR + 0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_stat_ind_data0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_ovfl_mode",
-        NPPU_IDMA_CFG_DEBUG_CNT_OVFL_MODEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x4f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_idma_cfg_debug_cnt_ovfl_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_status",
-        NPPU_IDMA_STAT_IND_STATUSr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_STAT_BASE_ADDR + 0x0400,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_idma_stat_ind_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_cmd",
-        NPPU_IDMA_STAT_IND_CMDr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_STAT_BASE_ADDR + 0x0404,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_nppu_idma_stat_ind_cmd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data0",
-        NPPU_IDMA_STAT_IND_DATA0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_STAT_BASE_ADDR + 0x0408,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_idma_stat_ind_data0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_status",
-        NPPU_PBU_CFG_IND_STATUSr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x400,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_ind_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_cmd",
-        NPPU_PBU_CFG_IND_CMDr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x404,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_nppu_pbu_cfg_ind_cmd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data0",
-        NPPU_PBU_CFG_IND_DATA0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x408,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_ind_data0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data1",
-        NPPU_PBU_CFG_IND_DATA1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x40c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_ind_data1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data2",
-        NPPU_PBU_CFG_IND_DATA2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x410,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_ind_data2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data3",
-        NPPU_PBU_CFG_IND_DATA3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x414,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_ind_data3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data4",
-        NPPU_PBU_CFG_IND_DATA4r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x418,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_ind_data4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data5",
-        NPPU_PBU_CFG_IND_DATA5r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x41c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_ind_data5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data6",
-        NPPU_PBU_CFG_IND_DATA6r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x420,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_ind_data6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data7",
-        NPPU_PBU_CFG_IND_DATA7r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x424,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_ind_data7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "idma_public_th",
-        NPPU_PBU_CFG_IDMA_PUBLIC_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_idma_public_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lif_public_th",
-        NPPU_PBU_CFG_LIF_PUBLIC_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_lif_public_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "idma_total_th",
-        NPPU_PBU_CFG_IDMA_TOTAL_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_idma_total_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lif_total_th",
-        NPPU_PBU_CFG_LIF_TOTAL_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_lif_total_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mc_total_th",
-        NPPU_PBU_CFG_MC_TOTAL_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_mc_total_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mc_cos10_th",
-        NPPU_PBU_CFG_MC_COS10_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pbu_cfg_mc_cos10_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mc_cos32_th",
-        NPPU_PBU_CFG_MC_COS32_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pbu_cfg_mc_cos32_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mc_cos54_th",
-        NPPU_PBU_CFG_MC_COS54_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pbu_cfg_mc_cos54_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mc_cos76_th",
-        NPPU_PBU_CFG_MC_COS76_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pbu_cfg_mc_cos76_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_ovfl_mode",
-        NPPU_PBU_CFG_DEBUG_CNT_OVFL_MODEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_debug_cnt_ovfl_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_key_aful_negate_cfg",
-        NPPU_PBU_CFG_SE_KEY_AFUL_NEGATE_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x530,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_se_key_aful_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sa_flag",
-        NPPU_PBU_CFG_SA_FLAGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x724,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_sa_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data",
-        NPPU_PBU_STAT_IND_DATAr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        127 + 1,
-        0,
-        4,
-        1,
-        g_nppu_pbu_stat_ind_data_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_status",
-        NPPU_PBU_STAT_IND_STATUSr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x0400,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_ind_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_cmd",
-        NPPU_PBU_STAT_IND_CMDr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x0404,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_nppu_pbu_stat_ind_cmd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "total_cnt",
-        NPPU_PBU_STAT_TOTAL_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x558,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_total_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "idma_pub_cnt",
-        NPPU_PBU_STAT_IDMA_PUB_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x55c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_idma_pub_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lif_pub_cnt",
-        NPPU_PBU_STAT_LIF_PUB_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x560,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_lif_pub_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mc_total_cnt",
-        NPPU_PBU_STAT_MC_TOTAL_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x564,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_mc_total_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_thram_init_done",
-        NPPU_PBU_STAT_PBU_THRAM_INIT_DONEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x568,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_pbu_thram_init_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ifb_fptr_init_done",
-        NPPU_PBU_STAT_IFB_FPTR_INIT_DONEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x56c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_ifb_fptr_init_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "weight_normal_uc",
-        NPPU_ISU_CFG_WEIGHT_NORMAL_UCr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_weight_normal_uc_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fabric_or_saip",
-        NPPU_ISU_CFG_FABRIC_OR_SAIPr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_fabric_or_saip_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_status",
-        NPPU_ISU_STAT_IND_STATUSr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_ind_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_cmd",
-        NPPU_ISU_STAT_IND_CMDr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_nppu_isu_stat_ind_cmd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat0",
-        NPPU_ISU_STAT_IND_DAT0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_ind_dat0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_access_done",
-        NPPU_ODMA_CFG_IND_ACCESS_DONEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_ind_access_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_command",
-        NPPU_ODMA_CFG_IND_COMMANDr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_nppu_odma_cfg_ind_command_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat0",
-        NPPU_ODMA_CFG_IND_DAT0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_ind_dat0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat1",
-        NPPU_ODMA_CFG_IND_DAT1r,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_ind_dat1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fabric_or_saip",
-        NPPU_ODMA_CFG_FABRIC_OR_SAIPr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_fabric_or_saip_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "max_pkt_len",
-        NPPU_ODMA_CFG_MAX_PKT_LENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_max_pkt_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "age_en",
-        NPPU_ODMA_CFG_AGE_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_age_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "age_mode",
-        NPPU_ODMA_CFG_AGE_MODEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_age_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "age_value_time",
-        NPPU_ODMA_CFG_AGE_VALUE_TIMEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x005c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_age_value_time_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "age_value_room",
-        NPPU_ODMA_CFG_AGE_VALUE_ROOMr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_age_value_room_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "age_out_cnt",
-        NPPU_ODMA_CFG_AGE_OUT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_age_out_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "token_value_a",
-        NPPU_ODMA_CFG_TOKEN_VALUE_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0114,
-        (32/8),
-        0,
-        59 + 1,
-        0,
-        4,
-        1,
-        g_nppu_odma_cfg_token_value_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "token_value_b",
-        NPPU_ODMA_CFG_TOKEN_VALUE_Br,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0204,
-        (32/8),
-        0,
-        1 + 1,
-        0,
-        4,
-        1,
-        g_nppu_odma_cfg_token_value_b_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_shap_en_p0",
-        NPPU_ODMA_CFG_CFG_SHAP_EN_P0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x020c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_cfg_shap_en_p0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_shap_en_p1",
-        NPPU_ODMA_CFG_CFG_SHAP_EN_P1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0210,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_cfg_shap_en_p1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_shap_en_tm",
-        NPPU_ODMA_CFG_CFG_SHAP_EN_TMr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0214,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_cfg_shap_en_tm_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_status",
-        NPPU_ODMA_STAT_IND_STATUSr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_STAT_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_stat_ind_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_cmd",
-        NPPU_ODMA_STAT_IND_CMDr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_STAT_BASE_ADDR + 0x0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_nppu_odma_stat_ind_cmd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_data0",
-        NPPU_ODMA_STAT_IND_DATA0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_STAT_BASE_ADDR + 0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_stat_ind_data0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_cfg",
-        NPPU_ODMA_STAT_DEBUG_CNT_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_STAT_BASE_ADDR + 0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_nppu_odma_stat_debug_cnt_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "bfd_firstchk_th",
-        NPPU_OAM_CFG_BFD_FIRSTCHK_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_bfd_firstchk_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_fc_idmath_ram",
-        NPPU_PBU_CFG_MEMID_0_PBU_FC_IDMATH_RAMr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x0000,
-        (192/8),
-        0,
-        127 + 1,
-        0,
-        1,
-        11,
-        g_nppu_pbu_cfg_memid_0_pbu_fc_idmath_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_fc_macth_ram",
-        NPPU_PBU_CFG_MEMID_1_PBU_FC_MACTH_RAMr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x0000,
-        (128/8),
-        0,
-        56 + 1,
-        0,
-        1,
-        8,
-        g_nppu_pbu_cfg_memid_1_pbu_fc_macth_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "all_kind_port_cnt",
-        NPPU_PBU_STAT_MEMID_1_ALL_KIND_PORT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x0000,
-        (32/8),
-        0,
-        127 + 1,
-        0,
-        1,
-        2,
-        g_nppu_pbu_stat_memid_1_all_kind_port_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_ifb_req_vld_cnt",
-        NPPU_PBU_STAT_MEMID_2_PPU_PBU_IFB_REQ_VLD_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_2_ppu_pbu_ifb_req_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_ifb_rsp_vld_cnt",
-        NPPU_PBU_STAT_MEMID_2_PBU_PPU_IFB_RSP_VLD_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0005,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_2_pbu_ppu_ifb_rsp_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_pbu_recy_ptr_vld_cnt",
-        NPPU_PBU_STAT_MEMID_2_ODMA_PBU_RECY_PTR_VLD_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0006,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_2_odma_pbu_recy_ptr_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_mcode_pf_req_cnt",
-        NPPU_PBU_STAT_MEMID_2_PPU_PBU_MCODE_PF_REQ_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0007,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_2_ppu_pbu_mcode_pf_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_mcode_pf_rsp_cnt",
-        NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_RSP_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_logic_pf_req_cnt",
-        NPPU_PBU_STAT_MEMID_2_PPU_PBU_LOGIC_PF_REQ_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0009,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_2_ppu_pbu_logic_pf_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_logic_pf_rsp_cnt",
-        NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_RSP_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_use_ptr_pulse_cnt",
-        NPPU_PBU_STAT_MEMID_2_PPU_USE_PTR_PULSE_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_2_ppu_use_ptr_pulse_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_wb_vld_cnt",
-        NPPU_PBU_STAT_MEMID_2_PPU_PBU_WB_VLD_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_2_ppu_pbu_wb_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_reorder_para_vld_cnt",
-        NPPU_PBU_STAT_MEMID_2_PBU_PPU_REORDER_PARA_VLD_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_2_pbu_ppu_reorder_para_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_pbu_dpi_key_vld_cnt",
-        NPPU_PBU_STAT_MEMID_2_SE_PBU_DPI_KEY_VLD_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_2_se_pbu_dpi_key_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_se_dpi_rsp_datvld_cnt",
-        NPPU_PBU_STAT_MEMID_2_PBU_SE_DPI_RSP_DATVLD_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_2_pbu_se_dpi_rsp_datvld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_pbu_ifb_rd1_cnt",
-        NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD1_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd1_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_pbu_ifb_rd2_cnt",
-        NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD2_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0011,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd2_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_mcode_pf_no_rsp_cnt",
-        NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_NO_RSP_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0015,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_no_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_logic_pf_no_rsp_cnt",
-        NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_NO_RSP_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0016,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_no_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_ifb_data",
-        NPPU_PBU_STAT_MEMID_3_CPU_RD_IFB_DATAr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x0000,
-        (2048/8),
-        0,
-        16383 + 1,
-        0,
-        1,
-        1,
-        g_nppu_pbu_stat_memid_3_cpu_rd_ifb_data_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mux_sel_rgt",
-        NPPU_PBU_STAT_MEMID_4_MUX_SEL_RGTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_memid_4_mux_sel_rgt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port_pub_cnt",
-        NPPU_PBU_STAT_MEMID_5_PORT_PUB_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x0000,
-        (32/8),
-        0,
-        127 + 1,
-        0,
-        1,
-        1,
-        g_nppu_pbu_stat_memid_5_port_pub_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "idma_o_isu_pkt_pulse_total_cnt",
-        NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_PKT_PULSE_TOTAL_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0012,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_idma_stat_memid_1_idma_o_isu_pkt_pulse_total_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "idma_o_isu_epkt_pulse_total_cnt",
-        NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_EPKT_PULSE_TOTAL_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0013,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_idma_stat_memid_1_idma_o_isu_epkt_pulse_total_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "idma_dispkt_pulse_total_cnt",
-        NPPU_IDMA_STAT_MEMID_1_IDMA_DISPKT_PULSE_TOTAL_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_idma_stat_memid_1_idma_dispkt_pulse_total_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "idma_o_isu_pkt_pulse_cnt",
-        NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_PKT_PULSE_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x0000,
-        (32/8),
-        0,
-        127 + 1,
-        0,
-        1,
-        1,
-        g_nppu_idma_stat_memid_0_idma_o_isu_pkt_pulse_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "idma_o_isu_epkt_pulse_cnt",
-        NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_EPKT_PULSE_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x0080,
-        (32/8),
-        0,
-        127 + 1,
-        0,
-        1,
-        1,
-        g_nppu_idma_stat_memid_0_idma_o_isu_epkt_pulse_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "idma_dispkt_pulse_cnt",
-        NPPU_IDMA_STAT_MEMID_0_IDMA_DISPKT_PULSE_CNTr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x0100,
-        (32/8),
-        0,
-        127 + 1,
-        0,
-        1,
-        1,
-        g_nppu_idma_stat_memid_0_idma_dispkt_pulse_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_r",
-        PPU_PPU_TEST_Rr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_test_r_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_debug_en_r",
-        PPU_PPU_PPU_DEBUG_EN_Rr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x00c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_debug_en_r_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csr_dup_table_wr_data",
-        PPU_PPU_CSR_DUP_TABLE_WR_DATAr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_ppu_ppu_csr_dup_table_wr_data_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csr_dup_table_rd_data",
-        PPU_PPU_CSR_DUP_TABLE_RD_DATAr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_ppu_ppu_csr_dup_table_rd_data_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csr_dup_table_addr",
-        PPU_PPU_CSR_DUP_TABLE_ADDRr,
-        PPU,
-        DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x03c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_ppu_ppu_csr_dup_table_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_debug_vld",
-        PPU_PPU_PPU_DEBUG_VLDr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_debug_vld_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cop_thash_rsk_319_288",
-        PPU_PPU_COP_THASH_RSK_319_288r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_cop_thash_rsk_319_288_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cop_thash_rsk_287_256",
-        PPU_PPU_COP_THASH_RSK_287_256r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_cop_thash_rsk_287_256_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cop_thash_rsk_255_224",
-        PPU_PPU_COP_THASH_RSK_255_224r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_cop_thash_rsk_255_224_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cop_thash_rsk_223_192",
-        PPU_PPU_COP_THASH_RSK_223_192r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x05c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_cop_thash_rsk_223_192_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cop_thash_rsk_191_160",
-        PPU_PPU_COP_THASH_RSK_191_160r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_cop_thash_rsk_191_160_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cop_thash_rsk_159_128",
-        PPU_PPU_COP_THASH_RSK_159_128r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_cop_thash_rsk_159_128_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cop_thash_rsk_127_096",
-        PPU_PPU_COP_THASH_RSK_127_096r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_cop_thash_rsk_127_096_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cop_thash_rsk_095_064",
-        PPU_PPU_COP_THASH_RSK_095_064r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x06c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_cop_thash_rsk_095_064_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cop_thash_rsk_063_032",
-        PPU_PPU_COP_THASH_RSK_063_032r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x070,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_cop_thash_rsk_063_032_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cop_thash_rsk_031_000",
-        PPU_PPU_COP_THASH_RSK_031_000r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x074,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_cop_thash_rsk_031_000_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ipv4_ipid_start_value",
-        PPU_PPU_CFG_IPV4_IPID_START_VALUEr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x078,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_cfg_ipv4_ipid_start_value_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ipv4_ipid_end_value",
-        PPU_PPU_CFG_IPV4_IPID_END_VALUEr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x07c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_cfg_ipv4_ipid_end_value_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cluster_mf_in_en",
-        PPU_PPU_CLUSTER_MF_IN_ENr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x150,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_cluster_mf_in_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_empty",
-        PPU_PPU_PPU_EMPTYr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x154,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_empty_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_w_addr",
-        PPU_PPU_INSTRMEM_W_ADDRr,
-        PPU,
-        DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x514,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_instrmem_w_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_w_data_191_160",
-        PPU_PPU_INSTRMEM_W_DATA_191_160r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x518,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_instrmem_w_data_191_160_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_w_data_159_128",
-        PPU_PPU_INSTRMEM_W_DATA_159_128r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x51c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_instrmem_w_data_159_128_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_w_data_127_96",
-        PPU_PPU_INSTRMEM_W_DATA_127_96r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x520,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_instrmem_w_data_127_96_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_w_data_95_64",
-        PPU_PPU_INSTRMEM_W_DATA_95_64r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x524,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_instrmem_w_data_95_64_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_w_data_63_32",
-        PPU_PPU_INSTRMEM_W_DATA_63_32r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x528,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_instrmem_w_data_63_32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_w_data_31_0",
-        PPU_PPU_INSTRMEM_W_DATA_31_0r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x52c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_instrmem_w_data_31_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_fwft_mf_fifo_prog_full_assert_cfg",
-        PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_isu_fwft_mf_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_fwft_mf_fifo_prog_full_negate_cfg",
-        PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_isu_fwft_mf_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_1200m_mask",
-        PPU_CLUSTER_INT_1200M_MASKr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x98,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        8,
-        g_ppu_cluster_int_1200m_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "wr_high_data_r_mex",
-        PPU4K_CLUSTER_WR_HIGH_DATA_R_MEXr,
-        PPU4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4000,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu4k_cluster_wr_high_data_r_mex_reg,
-        dpp_ppu_write,
-        dpp_ppu_read,
-    },
-    {
-        "wr_low_data_r_mex",
-        PPU4K_CLUSTER_WR_LOW_DATA_R_MEXr,
-        PPU4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4004,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu4k_cluster_wr_low_data_r_mex_reg,
-        dpp_ppu_write,
-        dpp_ppu_read,
-    },
-    {
-        "addr_r_mex",
-        PPU4K_CLUSTER_ADDR_R_MEXr,
-        PPU4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4008,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        2,
-        g_ppu4k_cluster_addr_r_mex_reg,
-        dpp_ppu_write,
-        dpp_ppu_read,
-    },
-    {
-        "sdt_tbl_ind_access_done",
-        PPU4K_CLUSTER_SDT_TBL_IND_ACCESS_DONEr,
-        PPU4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x400c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu4k_cluster_sdt_tbl_ind_access_done_reg,
-        dpp_ppu_write,
-        dpp_ppu_read,
-    },
-    {
-        "rd_high_data_r_mex",
-        PPU4K_CLUSTER_RD_HIGH_DATA_R_MEXr,
-        PPU4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4010,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu4k_cluster_rd_high_data_r_mex_reg,
-        dpp_ppu_write,
-        dpp_ppu_read,
-    },
-    {
-        "rd_low_data_r_mex",
-        PPU4K_CLUSTER_RD_LOW_DATA_R_MEXr,
-        PPU4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4014,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu4k_cluster_rd_low_data_r_mex_reg,
-        dpp_ppu_write,
-        dpp_ppu_read,
-    },
-    {
-        "init_ok",
-        SE_ALG_INIT_OKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_init_ok_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_rdy",
-        SE_ALG_CPU_RD_RDYr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_data_tmp0",
-        SE_ALG_CPU_RD_DATA_TMP0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_data_tmp0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_data_tmp1",
-        SE_ALG_CPU_RD_DATA_TMP1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_data_tmp1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_data_tmp2",
-        SE_ALG_CPU_RD_DATA_TMP2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_data_tmp2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_data_tmp3",
-        SE_ALG_CPU_RD_DATA_TMP3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_data_tmp3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_data_tmp4",
-        SE_ALG_CPU_RD_DATA_TMP4r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x005c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_data_tmp4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_data_tmp5",
-        SE_ALG_CPU_RD_DATA_TMP5r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_data_tmp5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_data_tmp6",
-        SE_ALG_CPU_RD_DATA_TMP6r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_data_tmp6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_data_tmp7",
-        SE_ALG_CPU_RD_DATA_TMP7r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_data_tmp7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_data_tmp8",
-        SE_ALG_CPU_RD_DATA_TMP8r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x006c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_data_tmp8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_data_tmp9",
-        SE_ALG_CPU_RD_DATA_TMP9r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0070,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_data_tmp9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_data_tmp10",
-        SE_ALG_CPU_RD_DATA_TMP10r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0074,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_data_tmp10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_data_tmp11",
-        SE_ALG_CPU_RD_DATA_TMP11r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0078,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_data_tmp11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_data_tmp12",
-        SE_ALG_CPU_RD_DATA_TMP12r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x007c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_data_tmp12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_data_tmp13",
-        SE_ALG_CPU_RD_DATA_TMP13r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_data_tmp13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_data_tmp14",
-        SE_ALG_CPU_RD_DATA_TMP14r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_data_tmp14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_data_tmp15",
-        SE_ALG_CPU_RD_DATA_TMP15r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_cpu_rd_data_tmp15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_v4_config_rgt",
-        SE_ALG_LPM_V4_CONFIG_RGTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x014c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_se_alg_lpm_v4_config_rgt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_v6_config_rgt",
-        SE_ALG_LPM_V6_CONFIG_RGTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0150,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_se_alg_lpm_v6_config_rgt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_ext_rsp_fifo_u0_pfull_ast",
-        SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x015c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_ext_rsp_fifo_u0_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_age_pat_cfg",
-        SE_AS_HASH_AGE_PAT_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_hash_age_pat_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "learn_rdy_cfg",
-        SE_AS_LEARN_RDY_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_learn_rdy_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_as_pful_cfg",
-        SE_KSCHD_KSCHD_AS_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_kschd_as_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_dir_pful_cfg",
-        SE_KSCHD_KSCHD_DIR_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_kschd_dir_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_as_ept_cfg",
-        SE_KSCHD_KSCHD_AS_EPT_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_kschd_as_ept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_arbi_pful_cfg",
-        SE_KSCHD_CPU_ARBI_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_cpu_arbi_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_pbu_pful_cfg",
-        SE_KSCHD_KSCHD_PBU_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_kschd_pbu_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_dir_pful_cfg",
-        SE_RSCHD_RSCHD_DIR_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_dir_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_dir_ept_cfg",
-        SE_RSCHD_RSCHD_DIR_EPT_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_dir_ept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_cmd_rgt",
-        SE4K_SE_ALG_CPU_CMD_RGTr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        7,
-        g_se4k_se_alg_cpu_cmd_rgt_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_wr_data_tmp0",
-        SE4K_SE_ALG_CPU_WR_DATA_TMP0r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_wr_data_tmp0_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_wr_data_tmp1",
-        SE4K_SE_ALG_CPU_WR_DATA_TMP1r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_wr_data_tmp1_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_wr_data_tmp2",
-        SE4K_SE_ALG_CPU_WR_DATA_TMP2r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_wr_data_tmp2_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_wr_data_tmp3",
-        SE4K_SE_ALG_CPU_WR_DATA_TMP3r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_wr_data_tmp3_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_wr_data_tmp4",
-        SE4K_SE_ALG_CPU_WR_DATA_TMP4r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_wr_data_tmp4_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_wr_data_tmp5",
-        SE4K_SE_ALG_CPU_WR_DATA_TMP5r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_wr_data_tmp5_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_wr_data_tmp6",
-        SE4K_SE_ALG_CPU_WR_DATA_TMP6r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_wr_data_tmp6_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_wr_data_tmp7",
-        SE4K_SE_ALG_CPU_WR_DATA_TMP7r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_wr_data_tmp7_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_wr_data_tmp8",
-        SE4K_SE_ALG_CPU_WR_DATA_TMP8r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_wr_data_tmp8_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_wr_data_tmp9",
-        SE4K_SE_ALG_CPU_WR_DATA_TMP9r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x002c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_wr_data_tmp9_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_wr_data_tmp10",
-        SE4K_SE_ALG_CPU_WR_DATA_TMP10r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_wr_data_tmp10_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_wr_data_tmp11",
-        SE4K_SE_ALG_CPU_WR_DATA_TMP11r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_wr_data_tmp11_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_wr_data_tmp12",
-        SE4K_SE_ALG_CPU_WR_DATA_TMP12r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_wr_data_tmp12_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_wr_data_tmp13",
-        SE4K_SE_ALG_CPU_WR_DATA_TMP13r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x003c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_wr_data_tmp13_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_wr_data_tmp14",
-        SE4K_SE_ALG_CPU_WR_DATA_TMP14r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_wr_data_tmp14_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_wr_data_tmp15",
-        SE4K_SE_ALG_CPU_WR_DATA_TMP15r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_wr_data_tmp15_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_rdy",
-        SE4K_SE_ALG_CPU_RD_RDYr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_rdy_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_data_tmp0",
-        SE4K_SE_ALG_CPU_RD_DATA_TMP0r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_data_tmp0_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_data_tmp1",
-        SE4K_SE_ALG_CPU_RD_DATA_TMP1r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_data_tmp1_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_data_tmp2",
-        SE4K_SE_ALG_CPU_RD_DATA_TMP2r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_data_tmp2_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_data_tmp3",
-        SE4K_SE_ALG_CPU_RD_DATA_TMP3r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_data_tmp3_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_data_tmp4",
-        SE4K_SE_ALG_CPU_RD_DATA_TMP4r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x005c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_data_tmp4_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_data_tmp5",
-        SE4K_SE_ALG_CPU_RD_DATA_TMP5r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_data_tmp5_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_data_tmp6",
-        SE4K_SE_ALG_CPU_RD_DATA_TMP6r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_data_tmp6_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_data_tmp7",
-        SE4K_SE_ALG_CPU_RD_DATA_TMP7r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_data_tmp7_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_data_tmp8",
-        SE4K_SE_ALG_CPU_RD_DATA_TMP8r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x006c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_data_tmp8_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_data_tmp9",
-        SE4K_SE_ALG_CPU_RD_DATA_TMP9r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0070,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_data_tmp9_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_data_tmp10",
-        SE4K_SE_ALG_CPU_RD_DATA_TMP10r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0074,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_data_tmp10_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_data_tmp11",
-        SE4K_SE_ALG_CPU_RD_DATA_TMP11r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0078,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_data_tmp11_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_data_tmp12",
-        SE4K_SE_ALG_CPU_RD_DATA_TMP12r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x007c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_data_tmp12_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_data_tmp13",
-        SE4K_SE_ALG_CPU_RD_DATA_TMP13r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_data_tmp13_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_data_tmp14",
-        SE4K_SE_ALG_CPU_RD_DATA_TMP14r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_data_tmp14_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_rd_data_tmp15",
-        SE4K_SE_ALG_CPU_RD_DATA_TMP15r,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_cpu_rd_data_tmp15_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash0_ext_cfg_rgt",
-        SE4K_SE_ALG_HASH0_EXT_CFG_RGTr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se4k_se_alg_hash0_ext_cfg_rgt_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash1_ext_cfg_rgt",
-        SE4K_SE_ALG_HASH1_EXT_CFG_RGTr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se4k_se_alg_hash1_ext_cfg_rgt_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash2_ext_cfg_rgt",
-        SE4K_SE_ALG_HASH2_EXT_CFG_RGTr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se4k_se_alg_hash2_ext_cfg_rgt_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash3_ext_cfg_rgt",
-        SE4K_SE_ALG_HASH3_EXT_CFG_RGTr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se4k_se_alg_hash3_ext_cfg_rgt_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash0_tbl30_depth",
-        SE4K_SE_ALG_HASH0_TBL30_DEPTHr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_se4k_se_alg_hash0_tbl30_depth_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash0_tbl74_depth",
-        SE4K_SE_ALG_HASH0_TBL74_DEPTHr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_se4k_se_alg_hash0_tbl74_depth_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash1_tbl30_depth",
-        SE4K_SE_ALG_HASH1_TBL30_DEPTHr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_se4k_se_alg_hash1_tbl30_depth_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash1_tbl74_depth",
-        SE4K_SE_ALG_HASH1_TBL74_DEPTHr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_se4k_se_alg_hash1_tbl74_depth_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash2_tbl30_depth",
-        SE4K_SE_ALG_HASH2_TBL30_DEPTHr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_se4k_se_alg_hash2_tbl30_depth_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash2_tbl74_depth",
-        SE4K_SE_ALG_HASH2_TBL74_DEPTHr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_se4k_se_alg_hash2_tbl74_depth_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash3_tbl30_depth",
-        SE4K_SE_ALG_HASH3_TBL30_DEPTHr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_se4k_se_alg_hash3_tbl30_depth_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash3_tbl74_depth",
-        SE4K_SE_ALG_HASH3_TBL74_DEPTHr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_se4k_se_alg_hash3_tbl74_depth_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "wr_rsp_cfg",
-        SE4K_SE_ALG_WR_RSP_CFGr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se4k_se_alg_wr_rsp_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash_mono_flag",
-        SE4K_SE_ALG_HASH_MONO_FLAGr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_se4k_se_alg_hash_mono_flag_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash10_ext_crc_cfg",
-        SE4K_SE_ALG_HASH10_EXT_CRC_CFGr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se4k_se_alg_hash10_ext_crc_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash32_ext_crc_cfg",
-        SE4K_SE_ALG_HASH32_EXT_CRC_CFGr,
-        SE4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se4k_se_alg_hash32_ext_crc_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "zblock_service_configure",
-        SE4K_SE_ALG_ZBLOCK_SERVICE_CONFIGUREr,
-        SE4K,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x10000,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        3,
-        g_se4k_se_alg_zblock_service_configure_reg,
-        dpp_se_alg_write,
-        dpp_se_alg_read,
-    },
-    {
-        "zblock_hash_zcell_mono",
-        SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONOr,
-        SE4K,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x10014,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        8,
-        g_se4k_se_alg_zblock_hash_zcell_mono_reg,
-        dpp_se_alg_write,
-        dpp_se_alg_read,
-    },
-    {
-        "zlock_hash_zreg_mono",
-        SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONOr,
-        SE4K,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x10015,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        8,
-        g_se4k_se_alg_zlock_hash_zreg_mono_reg,
-        dpp_se_alg_write,
-        dpp_se_alg_read,
-    },
-    {
-        "init_done",
-        SMMU0_SMMU0_INIT_DONEr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_init_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat0",
-        SMMU0_SMMU0_CPU_IND_WDAT0r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cpu_ind_wdat0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat1",
-        SMMU0_SMMU0_CPU_IND_WDAT1r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cpu_ind_wdat1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat2",
-        SMMU0_SMMU0_CPU_IND_WDAT2r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cpu_ind_wdat2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat3",
-        SMMU0_SMMU0_CPU_IND_WDAT3r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cpu_ind_wdat3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_cmd",
-        SMMU0_SMMU0_CPU_IND_CMDr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_smmu0_smmu0_cpu_ind_cmd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_rd_done",
-        SMMU0_SMMU0_CPU_IND_RD_DONEr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cpu_ind_rd_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_rdat0",
-        SMMU0_SMMU0_CPU_IND_RDAT0r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cpu_ind_rdat0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_rdat1",
-        SMMU0_SMMU0_CPU_IND_RDAT1r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cpu_ind_rdat1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_rdat2",
-        SMMU0_SMMU0_CPU_IND_RDAT2r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cpu_ind_rdat2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_rdat3",
-        SMMU0_SMMU0_CPU_IND_RDAT3r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cpu_ind_rdat3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_plcr_mono",
-        SMMU0_SMMU0_CFG_PLCR_MONOr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000108,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cfg_plcr_mono_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "wr_arb_cpu_rdy",
-        SMMU0_SMMU0_WR_ARB_CPU_RDYr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000010c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_wr_arb_cpu_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_stat_en_cfg",
-        SMMU0_SMMU0_TM_STAT_EN_CFGr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000110,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_tm_stat_en_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wdat0",
-        SE_SMMU1_DDR_WDAT0r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ddr_wdat0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dir_arbi_ser_rpful",
-        SE_SMMU1_DIR_ARBI_SER_RPFULr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000010c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_dir_arbi_ser_rpful_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_wr_arbi_pful2",
-        SE_SMMU1_CFG_WR_ARBI_PFUL2r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000120,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_smmu1_cfg_wr_arbi_pful2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_tbl_cfg",
-        SE_SMMU1_ETM_TBL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_etm_tbl_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_cash_addr_pful",
-        SE_SMMU1_CFG_CASH_ADDR_PFULr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000020c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cfg_cash_addr_pful_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_rfifo_cfg",
-        SE_SMMU1_CTRL_RFIFO_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000234,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_se_smmu1_ctrl_rfifo_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cache_req_fifo_cfg",
-        SE_SMMU1_CACHE_REQ_FIFO_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000288,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_smmu1_cache_req_fifo_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_eram_wdat0",
-        STAT_STAT_CFG_CPU_IND_ERAM_WDAT0r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_eram_wdat0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_port_sel_cfg",
-        STAT_STAT_CFG_ETM_PORT_SEL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_stat_stat_cfg_etm_port_sel_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_stat_cfg",
-        STAT_STAT_CFG_TM_STAT_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_stat_stat_cfg_tm_stat_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_eram_depth",
-        STAT_STAT_CFG_PPU_ERAM_DEPTHr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_ppu_eram_depth_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_eram_base_addr",
-        STAT_STAT_CFG_PPU_ERAM_BASE_ADDRr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_ppu_eram_base_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_ddr_base_addr",
-        STAT_STAT_CFG_PPU_DDR_BASE_ADDRr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_ppu_ddr_base_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "plcr0_base_addr",
-        STAT_STAT_CFG_PLCR0_BASE_ADDRr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000006c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_plcr0_base_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_stat_start_addr_cfg",
-        STAT_STAT_CFG_ETM_STAT_START_ADDR_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_etm_stat_start_addr_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_stat_depth_cfg",
-        STAT_STAT_CFG_ETM_STAT_DEPTH_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_etm_stat_depth_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cycle_mov_en_cfg",
-        STAT_STAT_CFG_CYCLE_MOV_EN_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cycle_mov_en_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat0",
-        STAT_ETCAM_CPU_IND_WDAT0r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ctrl_tmp0",
-        STAT_ETCAM_CPU_IND_CTRL_TMP0r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        7,
-        g_stat_etcam_cpu_ind_ctrl_tmp0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ctrl_tmp1",
-        STAT_ETCAM_CPU_IND_CTRL_TMP1r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_stat_etcam_cpu_ind_ctrl_tmp1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_rd_done",
-        STAT_ETCAM_CPU_IND_RD_DONEr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x000001fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_rd_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat0",
-        STAT_ETCAM_CPU_RDAT0r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000200,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat1",
-        STAT_ETCAM_CPU_RDAT1r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000204,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat2",
-        STAT_ETCAM_CPU_RDAT2r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000208,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat3",
-        STAT_ETCAM_CPU_RDAT3r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000020c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat4",
-        STAT_ETCAM_CPU_RDAT4r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000210,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat5",
-        STAT_ETCAM_CPU_RDAT5r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000214,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat6",
-        STAT_ETCAM_CPU_RDAT6r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000218,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat7",
-        STAT_ETCAM_CPU_RDAT7r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000021c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat8",
-        STAT_ETCAM_CPU_RDAT8r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000220,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat9",
-        STAT_ETCAM_CPU_RDAT9r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000224,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat10",
-        STAT_ETCAM_CPU_RDAT10r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000228,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat11",
-        STAT_ETCAM_CPU_RDAT11r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000022c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat12",
-        STAT_ETCAM_CPU_RDAT12r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000230,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat13",
-        STAT_ETCAM_CPU_RDAT13r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000234,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat14",
-        STAT_ETCAM_CPU_RDAT14r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000238,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat15",
-        STAT_ETCAM_CPU_RDAT15r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000023c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat16",
-        STAT_ETCAM_CPU_RDAT16r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000240,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat17",
-        STAT_ETCAM_CPU_RDAT17r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000244,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat18",
-        STAT_ETCAM_CPU_RDAT18r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000248,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat19",
-        STAT_ETCAM_CPU_RDAT19r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000024c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_rdat19_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qvbo",
-        STAT_ETCAM_QVBOr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000250,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_qvbo_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_overflow_mode",
-        STAT_ETCAM_CNT_OVERFLOW_MODEr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x000003ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_etcam_cnt_overflow_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_queue_ram0_159_0",
-        STAT_CAR0_CARA_QUEUE_RAM0_159_0r,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x000000 + 0x14000000,
-        (160/8),
-        0,
-        0x7FFF + 1,
-        0,
-        8,
-        9,
-        g_stat_car0_cara_queue_ram0_159_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_profile_ram1_255_0",
-        STAT_CAR0_CARA_PROFILE_RAM1_255_0r,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x040000 + 0x20000000,
-        (256/8),
-        0,
-        0x1FF + 1,
-        0,
-        8,
-        31,
-        g_stat_car0_cara_profile_ram1_255_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_qovs_ram_ram2",
-        STAT_CAR0_CARA_QOVS_RAM_RAM2r,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x80000,
-        (32/8),
-        0,
-        0x7FFF + 1,
-        0,
-        1,
-        1,
-        g_stat_car0_cara_qovs_ram_ram2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "look_up_table1",
-        STAT_CAR0_LOOK_UP_TABLE1r,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0xc0000,
-        (32/8),
-        0,
-        0x7FFF + 1,
-        0,
-        1,
-        2,
-        g_stat_car0_look_up_table1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_pkt_des_i_cnt",
-        STAT_CAR0_CARA_PKT_DES_I_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c0000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_cara_pkt_des_i_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_green_pkt_i_cnt",
-        STAT_CAR0_CARA_GREEN_PKT_I_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c0001,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_cara_green_pkt_i_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_yellow_pkt_i_cnt",
-        STAT_CAR0_CARA_YELLOW_PKT_I_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c0002,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_cara_yellow_pkt_i_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_red_pkt_i_cnt",
-        STAT_CAR0_CARA_RED_PKT_I_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c0003,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_cara_red_pkt_i_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_pkt_des_o_cnt",
-        STAT_CAR0_CARA_PKT_DES_O_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_cara_pkt_des_o_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_green_pkt_o_cnt",
-        STAT_CAR0_CARA_GREEN_PKT_O_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c0005,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_cara_green_pkt_o_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_yellow_pkt_o_cnt",
-        STAT_CAR0_CARA_YELLOW_PKT_O_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c0006,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_cara_yellow_pkt_o_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_red_pkt_o_cnt",
-        STAT_CAR0_CARA_RED_PKT_O_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c0007,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_cara_red_pkt_o_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_pkt_des_fc_for_cfg_cnt",
-        STAT_CAR0_CARA_PKT_DES_FC_FOR_CFG_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_cara_pkt_des_fc_for_cfg_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_appoint_qnum_or_sp",
-        STAT_CAR0_CARA_APPOINT_QNUM_OR_SPr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c0009,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_stat_car0_cara_appoint_qnum_or_sp_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_cfgmt_count_mode",
-        STAT_CAR0_CARA_CFGMT_COUNT_MODEr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c000a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_car0_cara_cfgmt_count_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_pkt_size_cnt",
-        STAT_CAR0_CARA_PKT_SIZE_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c000b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_cara_pkt_size_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_plcr_init_dont",
-        STAT_CAR0_CARA_PLCR_INIT_DONTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_cara_plcr_init_dont_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_queue_ram0_159_0",
-        STAT_CAR0_CARB_QUEUE_RAM0_159_0r,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x100000 + 0x14000000,
-        (160/8),
-        0,
-        0xFFF + 1,
-        0,
-        8,
-        9,
-        g_stat_car0_carb_queue_ram0_159_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_profile_ram1_255_0",
-        STAT_CAR0_CARB_PROFILE_RAM1_255_0r,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x140000 + 0x20000000,
-        (256/8),
-        0,
-        0x7F + 1,
-        0,
-        8,
-        33,
-        g_stat_car0_carb_profile_ram1_255_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_qovs_ram_ram2",
-        STAT_CAR0_CARB_QOVS_RAM_RAM2r,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x180000,
-        (32/8),
-        0,
-        0xFFF + 1,
-        0,
-        1,
-        1,
-        g_stat_car0_carb_qovs_ram_ram2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "look_up_table2",
-        STAT_CAR0_LOOK_UP_TABLE2r,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x1c0000,
-        (32/8),
-        0,
-        0xFFF + 1,
-        0,
-        1,
-        2,
-        g_stat_car0_look_up_table2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_pkt_des_i_cnt",
-        STAT_CAR0_CARB_PKT_DES_I_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c1000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carb_pkt_des_i_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_green_pkt_i_cnt",
-        STAT_CAR0_CARB_GREEN_PKT_I_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c1001,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carb_green_pkt_i_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_yellow_pkt_i_cnt",
-        STAT_CAR0_CARB_YELLOW_PKT_I_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c1002,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carb_yellow_pkt_i_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_red_pkt_i_cnt",
-        STAT_CAR0_CARB_RED_PKT_I_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c1003,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carb_red_pkt_i_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_pkt_des_o_cnt",
-        STAT_CAR0_CARB_PKT_DES_O_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c1004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carb_pkt_des_o_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_green_pkt_o_cnt",
-        STAT_CAR0_CARB_GREEN_PKT_O_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c1005,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carb_green_pkt_o_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_yellow_pkt_o_cnt",
-        STAT_CAR0_CARB_YELLOW_PKT_O_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c1006,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carb_yellow_pkt_o_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_red_pkt_o_cnt",
-        STAT_CAR0_CARB_RED_PKT_O_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c1007,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carb_red_pkt_o_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_pkt_des_fc_for_cfg_cnt",
-        STAT_CAR0_CARB_PKT_DES_FC_FOR_CFG_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c1008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carb_pkt_des_fc_for_cfg_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_appoint_qnum_or_sp",
-        STAT_CAR0_CARB_APPOINT_QNUM_OR_SPr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c1009,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_stat_car0_carb_appoint_qnum_or_sp_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_cfgmt_count_mode",
-        STAT_CAR0_CARB_CFGMT_COUNT_MODEr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c100a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_car0_carb_cfgmt_count_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_pkt_size_cnt",
-        STAT_CAR0_CARB_PKT_SIZE_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c100b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carb_pkt_size_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_plcr_init_dont",
-        STAT_CAR0_CARB_PLCR_INIT_DONTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c100c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carb_plcr_init_dont_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_queue_ram0_159_0",
-        STAT_CAR0_CARC_QUEUE_RAM0_159_0r,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x200000 + 0x14000000,
-        (160/8),
-        0,
-        0x3FF + 1,
-        0,
-        8,
-        9,
-        g_stat_car0_carc_queue_ram0_159_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_profile_ram1_255_0",
-        STAT_CAR0_CARC_PROFILE_RAM1_255_0r,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x240000 + 0x20000000,
-        (256/8),
-        0,
-        0x1F + 1,
-        0,
-        8,
-        33,
-        g_stat_car0_carc_profile_ram1_255_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_qovs_ram_ram2",
-        STAT_CAR0_CARC_QOVS_RAM_RAM2r,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x280000,
-        (32/8),
-        0,
-        0x3FF + 1,
-        0,
-        1,
-        1,
-        g_stat_car0_carc_qovs_ram_ram2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_pkt_des_i_cnt",
-        STAT_CAR0_CARC_PKT_DES_I_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c2000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carc_pkt_des_i_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_green_pkt_i_cnt",
-        STAT_CAR0_CARC_GREEN_PKT_I_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c2001,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carc_green_pkt_i_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_yellow_pkt_i_cnt",
-        STAT_CAR0_CARC_YELLOW_PKT_I_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c2002,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carc_yellow_pkt_i_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_red_pkt_i_cnt",
-        STAT_CAR0_CARC_RED_PKT_I_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c2003,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carc_red_pkt_i_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_pkt_des_o_cnt",
-        STAT_CAR0_CARC_PKT_DES_O_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c2004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carc_pkt_des_o_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_green_pkt_o_cnt",
-        STAT_CAR0_CARC_GREEN_PKT_O_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c2005,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carc_green_pkt_o_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_yellow_pkt_o_cnt",
-        STAT_CAR0_CARC_YELLOW_PKT_O_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c2006,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carc_yellow_pkt_o_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_red_pkt_o_cnt",
-        STAT_CAR0_CARC_RED_PKT_O_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c2007,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carc_red_pkt_o_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_pkt_des_fc_for_cfg_cnt",
-        STAT_CAR0_CARC_PKT_DES_FC_FOR_CFG_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c2008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carc_pkt_des_fc_for_cfg_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_appoint_qnum_or_sp",
-        STAT_CAR0_CARC_APPOINT_QNUM_OR_SPr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c2009,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_stat_car0_carc_appoint_qnum_or_sp_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_cfgmt_count_mode",
-        STAT_CAR0_CARC_CFGMT_COUNT_MODEr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c200a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_car0_carc_cfgmt_count_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_pkt_size_cnt",
-        STAT_CAR0_CARC_PKT_SIZE_CNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c200b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carc_pkt_size_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_plcr_init_dont",
-        STAT_CAR0_CARC_PLCR_INIT_DONTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c200c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carc_plcr_init_dont_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_random_ram",
-        STAT_CAR0_CARB_RANDOM_RAMr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x2d0000 + 0x40000000,
-        (512/8),
-        0,
-        0x1f + 1,
-        0,
-        16,
-        24,
-        g_stat_car0_carb_random_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_random_ram",
-        STAT_CAR0_CARC_RANDOM_RAMr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x2e0000 + 0x40000000,
-        (512/8),
-        0,
-        0x7 + 1,
-        0,
-        16,
-        24,
-        g_stat_car0_carc_random_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_begin_flow_id",
-        STAT_CAR0_CARA_BEGIN_FLOW_IDr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_cara_begin_flow_id_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carb_begin_flow_id",
-        STAT_CAR0_CARB_BEGIN_FLOW_IDr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300001,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carb_begin_flow_id_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "carc_begin_flow_id",
-        STAT_CAR0_CARC_BEGIN_FLOW_IDr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300002,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_carc_begin_flow_id_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "prog_full_assert_cfg_w",
-        STAT_CAR0_PROG_FULL_ASSERT_CFG_Wr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300003,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_prog_full_assert_cfg_w_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "prog_full_negate_cfg_w",
-        STAT_CAR0_PROG_FULL_NEGATE_CFG_Wr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_prog_full_negate_cfg_w_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "timeout_limit",
-        STAT_CAR0_TIMEOUT_LIMITr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300005,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_timeout_limit_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_des_fifo_overflow",
-        STAT_CAR0_PKT_DES_FIFO_OVERFLOWr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300006,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_pkt_des_fifo_overflow_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_des_fifo_underflow",
-        STAT_CAR0_PKT_DES_FIFO_UNDERFLOWr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300007,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_pkt_des_fifo_underflow_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_des_fifo_prog_full",
-        STAT_CAR0_PKT_DES_FIFO_PROG_FULLr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_pkt_des_fifo_prog_full_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_des_fifo_prog_empty",
-        STAT_CAR0_PKT_DES_FIFO_PROG_EMPTYr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300009,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_pkt_des_fifo_prog_empty_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_des_fifo_full",
-        STAT_CAR0_PKT_DES_FIFO_FULLr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x30000a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_pkt_des_fifo_full_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_des_fifo_empty",
-        STAT_CAR0_PKT_DES_FIFO_EMPTYr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x30000b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_pkt_des_fifo_empty_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_size_offset",
-        STAT_CAR0_PKT_SIZE_OFFSETr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x30000e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_pkt_size_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "car_plcr_init_dont",
-        STAT_CAR0_CAR_PLCR_INIT_DONTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x30000f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_car_plcr_init_dont_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "max_pkt_size_a",
-        STAT_CAR0_MAX_PKT_SIZE_Ar,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_max_pkt_size_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "max_pkt_size_b",
-        STAT_CAR0_MAX_PKT_SIZE_Br,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300011,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_max_pkt_size_b_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "max_pkt_size_c",
-        STAT_CAR0_MAX_PKT_SIZE_Cr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300012,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_max_pkt_size_c_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "car_hierarchy_mode",
-        STAT_CAR0_CAR_HIERARCHY_MODEr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300013,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_car_hierarchy_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "prog_empty_assert_cfg_w",
-        STAT_CAR0_PROG_EMPTY_ASSERT_CFG_Wr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_prog_empty_assert_cfg_w_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "prog_empty_negate_cfg_w",
-        STAT_CAR0_PROG_EMPTY_NEGATE_CFG_Wr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300015,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_prog_empty_negate_cfg_w_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_des_fifo_ovf_int",
-        STAT_CAR0_PKT_DES_FIFO_OVF_INTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300016,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_pkt_des_fifo_ovf_int_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_des_fifo_data_count",
-        STAT_CAR0_PKT_DES_FIFO_DATA_COUNTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300017,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_pkt_des_fifo_data_count_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_des_fifo_udf_int",
-        STAT_CAR0_PKT_DES_FIFO_UDF_INTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x300018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_car0_pkt_des_fifo_udf_int_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_queue_ram0_159_0_pkt",
-        STAT_CAR0_CARA_QUEUE_RAM0_159_0_PKTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x000000 + 0x14000000,
-        (160/8),
-        0,
-        0x7FFF + 1,
-        0,
-        8,
-        8,
-        g_stat_car0_cara_queue_ram0_159_0_pkt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cara_profile_ram1_255_0_pkt",
-        STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKTr,
-        STAT,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x040000 + 0x20000000,
-        (256/8),
-        0,
-        0x1FF + 1,
-        0,
-        8,
-        12,
-        g_stat_car0_cara_profile_ram1_255_0_pkt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "block0_7_port_id_cfg",
-        STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFGr,
-        STAT4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000005c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        8,
-        g_stat4k_etcam_block0_7_port_id_cfg_reg,
-        dpp_write,
-        dpp_read,
-    },
-    {
-        "block0_3_base_addr_cfg",
-        STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFGr,
-        STAT4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_stat4k_etcam_block0_3_base_addr_cfg_reg,
-        dpp_write,
-        dpp_read,
-    },
-    {
-        "block4_7_base_addr_cfg",
-        STAT4K_ETCAM_BLOCK4_7_BASE_ADDR_CFGr,
-        STAT4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_stat4k_etcam_block4_7_base_addr_cfg_reg,
-        dpp_write,
-        dpp_read,
-    },
-    {
-        "cfg_eram_wr_interval_cnt",
-        DTB_DTB_CFG_CFG_ERAM_WR_INTERVAL_CNTr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_eram_wr_interval_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_zcam_wr_interval_cnt",
-        DTB_DTB_CFG_CFG_ZCAM_WR_INTERVAL_CNTr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_zcam_wr_interval_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tcam_wr_interval_cnt",
-        DTB_DTB_CFG_CFG_TCAM_WR_INTERVAL_CNTr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_tcam_wr_interval_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddr_wr_interval_cnt",
-        DTB_DTB_CFG_CFG_DDR_WR_INTERVAL_CNTr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_ddr_wr_interval_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_hash_wr_interval_cnt",
-        DTB_DTB_CFG_CFG_HASH_WR_INTERVAL_CNTr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_hash_wr_interval_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_eram_rd_interval_cnt",
-        DTB_DTB_CFG_CFG_ERAM_RD_INTERVAL_CNTr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_eram_rd_interval_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_zcam_rd_interval_cnt",
-        DTB_DTB_CFG_CFG_ZCAM_RD_INTERVAL_CNTr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x005c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_zcam_rd_interval_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tcam_rd_interval_cnt",
-        DTB_DTB_CFG_CFG_TCAM_RD_INTERVAL_CNTr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_tcam_rd_interval_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddr_rd_interval_cnt",
-        DTB_DTB_CFG_CFG_DDR_RD_INTERVAL_CNTr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_ddr_rd_interval_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_dtb_queue_lock_state_0_3",
-        DTB_DTB_CFG_CFG_DTB_QUEUE_LOCK_STATE_0_3r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0080,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_dtb_dtb_cfg_cfg_dtb_queue_lock_state_0_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "w_convert_0_mode",
-        DTB_DTB_AXIM0_W_CONVERT_0_MODEr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_AXIM0_BASE_ADDR + 0x6060,
-        (32/8),
-        0,
-        1 + 1,
-        0,
-        256,
-        1,
-        g_dtb_dtb_axim0_w_convert_0_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "r_convert_0_mode",
-        DTB_DTB_AXIM0_R_CONVERT_0_MODEr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_AXIM0_BASE_ADDR + 0x2060,
-        (32/8),
-        0,
-        1 + 1,
-        0,
-        256,
-        1,
-        g_dtb_dtb_axim0_r_convert_0_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "aximr_os",
-        DTB_DTB_AXIM0_AXIMR_OSr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_AXIM0_BASE_ADDR + 0x2000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_axim0_aximr_os_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "w_convert_1_mode",
-        DTB_DTB_AXIM1_W_CONVERT_1_MODEr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_AXIM1_BASE_ADDR + 0x6060,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        256,
-        1,
-        g_dtb_dtb_axim1_w_convert_1_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "r_convert_1_mode",
-        DTB_DTB_AXIM1_R_CONVERT_1_MODEr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_AXIM1_BASE_ADDR + 0x2060,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        256,
-        1,
-        g_dtb_dtb_axim1_r_convert_1_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "axis_convert_mode",
-        DTB_DTB_AXIS_AXIS_CONVERT_MODEr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_AXIS_BASE_ADDR + 0x0450,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_axis_axis_convert_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_queue_dtb_addr_h_0_127",
-        DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_H_0_127r,
-        DTB4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        127 + 1,
-        0,
-        32,
-        1,
-        g_dtb4k_dtb_enq_cfg_queue_dtb_addr_h_0_127_reg,
-        dpp_write,
-        dpp_read,
-    },
-    {
-        "cfg_queue_dtb_addr_l_0_127",
-        DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_L_0_127r,
-        DTB4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR + 0x0004,
-        (32/8),
-        0,
-        127 + 1,
-        0,
-        32,
-        1,
-        g_dtb4k_dtb_enq_cfg_queue_dtb_addr_l_0_127_reg,
-        dpp_write,
-        dpp_read,
-    },
-    {
-        "cfg_queue_dtb_len_0_127",
-        DTB4K_DTB_ENQ_CFG_QUEUE_DTB_LEN_0_127r,
-        DTB4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR + 0x0008,
-        (32/8),
-        0,
-        127 + 1,
-        0,
-        32,
-        3,
-        g_dtb4k_dtb_enq_cfg_queue_dtb_len_0_127_reg,
-        dpp_write,
-        dpp_read,
-    },
-    {
-        "info_queue_buf_space_left_0_127",
-        DTB4K_DTB_ENQ_INFO_QUEUE_BUF_SPACE_LEFT_0_127r,
-        DTB4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR + 0x000c,
-        (32/8),
-        0,
-        127 + 1,
-        0,
-        32,
-        1,
-        g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg,
-        dpp_write,
-        dpp_read,
-    },
-    {
-        "cfg_epid_v_func_num_0_127",
-        DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127r,
-        DTB4K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR + 0x0010,
-        (32/8),
-        0,
-        127 + 1,
-        0,
-        32,
-        7,
-        g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg,
-        dpp_write,
-        dpp_read,
-    },
-    {
-        "cpu_trpg_ms_en",
-        TRPG_TRPG_RX_PORT_CPU_TRPG_MS_ENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0004,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpg_ms_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpg_port_en",
-        TRPG_TRPG_RX_PORT_CPU_TRPG_PORT_ENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0010,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpg_port_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpg_look_en",
-        TRPG_TRPG_RX_PORT_CPU_TRPG_LOOK_ENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0014,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpg_look_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_ram_almost_full",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_ALMOST_FULLr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0028,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_ram_almost_full_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_ram_test_en",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_TEST_ENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x002c,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_ram_test_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_inmod_pfc_rdy_en",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_INMOD_PFC_RDY_ENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0030,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_inmod_pfc_rdy_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_pkt_num_h",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_Hr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0034,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_pkt_num_l",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_Lr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0038,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_pkt_byte_num_h",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_Hr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x003c,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_pkt_byte_num_l",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_Lr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0040,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_pkt_cnt_clr",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_CNT_CLRr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0044,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_pkt_cnt_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_fc_clk_freq",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_CLK_FREQr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0048,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_fc_clk_freq_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_fc_en",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_ENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x004c,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_fc_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_fc_token_add_num",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_ADD_NUMr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0050,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_fc_token_add_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_fc_token_max_num",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_MAX_NUMr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0054,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_fc_token_max_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_port_state_info",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_PORT_STATE_INFOr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0058,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_port_state_info_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_ram_past_max_dep",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEPr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x005c,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_ram_past_max_dep_clr",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEP_CLRr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0060,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_pkt_past_max_len",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0064,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_pkt_past_max_len_clr",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LEN_CLRr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0068,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_pkt_past_min_len",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x006c,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_pkt_past_min_len_clr",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LEN_CLRr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0070,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trpg_rx_data_ram",
-        TRPG_TRPG_RX_RAM_TRPG_RX_DATA_RAMr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_RAM_BASE_ADDR + 0x0000,
-        (32/8),
-        DPP_TRPG_RAM_NUM,
-        2047 + 1,
-        DPP_TRPG_RAM_SPACE_SIZE,
-        4,
-        1,
-        g_trpg_trpg_rx_ram_trpg_rx_data_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trpg_rx_info_ram",
-        TRPG_TRPG_RX_RAM_TRPG_RX_INFO_RAMr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_RAM_BASE_ADDR + 0x2000,
-        (32/8),
-        DPP_TRPG_RAM_NUM,
-        255 + 1,
-        DPP_TRPG_RAM_SPACE_SIZE,
-        4,
-        1,
-        g_trpg_trpg_rx_ram_trpg_rx_info_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpg_ms_en",
-        TRPG_TRPG_TX_PORT_CPU_TRPG_MS_ENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0004,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpg_ms_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpg_port_en",
-        TRPG_TRPG_TX_PORT_CPU_TRPG_PORT_ENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0010,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpg_port_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpg_look_en",
-        TRPG_TRPG_TX_PORT_CPU_TRPG_LOOK_ENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0014,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpg_look_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_ram_almost_full",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_ALMOST_FULLr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0018,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_ram_almost_full_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_ram_test_en",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_TEST_ENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x001c,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_ram_test_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_pkt_num_h",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_Hr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0034,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_pkt_num_l",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_Lr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0038,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_pkt_byte_num_h",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_Hr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x003c,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_pkt_byte_num_l",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_Lr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0040,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_pkt_cnt_clr",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_CNT_CLRr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0044,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_pkt_cnt_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_fc_clk_freq",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_CLK_FREQr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0048,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_fc_clk_freq_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_fc_en",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_ENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x004c,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_fc_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_fc_token_add_num",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_ADD_NUMr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0050,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_fc_token_add_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_fc_token_max_num",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_MAX_NUMr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0054,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_fc_token_max_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_port_state_info",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_PORT_STATE_INFOr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0058,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_port_state_info_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_ram_past_max_dep",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEPr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x005c,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_ram_past_max_dep_clr",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEP_CLRr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0060,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_pkt_past_max_len",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0064,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_pkt_past_max_len_clr",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LEN_CLRr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0068,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_pkt_past_min_len",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x006c,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_pkt_past_min_len_clr",
-        TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LEN_CLRr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0070,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_etm_ram_almost_full",
-        TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_ALMOST_FULLr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_ETM_PORT_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_almost_full_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgtx_etm_ram_test_en",
-        TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_TEST_ENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_ETM_PORT_BASE_ADDR + 0x0010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_test_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_todtime_update_int_mask",
-        TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_MASKr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_trpg_trpg_tx_glb_cpu_todtime_update_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_todtime_update_int_clr",
-        TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_CLRr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x0010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_trpg_trpg_tx_glb_cpu_todtime_update_int_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_todtime_ram_test_en",
-        TRPG_TRPG_TX_GLB_CPU_TODTIME_RAM_TEST_ENr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_trpg_trpg_tx_glb_cpu_todtime_ram_test_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trpg_tx_data_ram",
-        TRPG_TRPG_TX_RAM_TRPG_TX_DATA_RAMr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_RAM_BASE_ADDR + 0x0000,
-        (32/8),
-        DPP_TRPG_RAM_NUM,
-        12031 + 1,
-        DPP_TRPG_RAM_SPACE_SIZE,
-        4,
-        1,
-        g_trpg_trpg_tx_ram_trpg_tx_data_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trpg_tx_info_ram",
-        TRPG_TRPG_TX_RAM_TRPG_TX_INFO_RAMr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_RAM_BASE_ADDR + 0xc000,
-        (32/8),
-        DPP_TRPG_RAM_NUM,
-        751 + 1,
-        DPP_TRPG_RAM_SPACE_SIZE,
-        4,
-        1,
-        g_trpg_trpg_tx_ram_trpg_tx_info_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trpg_tx_etm_data_ram",
-        TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_DATA_RAMr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_ETM_RAM_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        511 + 1,
-        0,
-        4,
-        1,
-        g_trpg_trpg_tx_etm_ram_trpg_tx_etm_data_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trpg_tx_etm_info_ram",
-        TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_INFO_RAMr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_ETM_RAM_BASE_ADDR + 0x800,
-        (32/8),
-        0,
-        31 + 1,
-        0,
-        4,
-        1,
-        g_trpg_trpg_tx_etm_ram_trpg_tx_etm_info_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "chip_version_reg",
-        ETM_CFGMT_CHIP_VERSION_REGr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x40,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_etm_cfgmt_chip_version_reg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "chip_date_reg",
-        ETM_CFGMT_CHIP_DATE_REGr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x50,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cfgmt_chip_date_reg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_crc_en",
-        ETM_CFGMT_CFGMT_CRC_ENr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x80,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cfgmt_cfgmt_crc_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_port_transfer_en",
-        ETM_CFGMT_CFG_PORT_TRANSFER_ENr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x130,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cfgmt_cfg_port_transfer_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_sa_work_mode",
-        ETM_CFGMT_TM_SA_WORK_MODEr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x180,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cfgmt_tm_sa_work_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "local_sa_id",
-        ETM_CFGMT_LOCAL_SA_IDr,
-        ETM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x190,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cfgmt_local_sa_id_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "olif_rdy",
-        ETM_OLIF_OLIF_RDYr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_etm_olif_olif_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "emem_prog_full",
-        ETM_OLIF_EMEM_PROG_FULLr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x3,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_olif_emem_prog_full_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port_order_fifo_full",
-        ETM_OLIF_PORT_ORDER_FIFO_FULLr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x5,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_olif_port_order_fifo_full_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "olif_release_last",
-        ETM_OLIF_OLIF_RELEASE_LASTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x6,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_olif_olif_release_last_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "olif_fifo_empty_state",
-        ETM_OLIF_OLIF_FIFO_EMPTY_STATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xa,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_etm_olif_olif_fifo_empty_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_olif_release_fc_cnt",
-        ETM_OLIF_QMU_OLIF_RELEASE_FC_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xb,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_qmu_olif_release_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "olif_qmu_link_fc_cnt",
-        ETM_OLIF_OLIF_QMU_LINK_FC_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_olif_qmu_link_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lif0_link_fc_cnt",
-        ETM_OLIF_LIF0_LINK_FC_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xd,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_lif0_link_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "olif_tmmu_fc_cnt",
-        ETM_OLIF_OLIF_TMMU_FC_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_olif_tmmu_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "olif_mmu_fc_cnt",
-        ETM_OLIF_OLIF_MMU_FC_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xf,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_olif_mmu_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "olif_qmu_port_rdy_h",
-        ETM_OLIF_OLIF_QMU_PORT_RDY_Hr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x10,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_olif_qmu_port_rdy_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "olif_qmu_port_rdy_l",
-        ETM_OLIF_OLIF_QMU_PORT_RDY_Lr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x11,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_olif_qmu_port_rdy_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lif0_port_rdy_h",
-        ETM_OLIF_LIF0_PORT_RDY_Hr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_lif0_port_rdy_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lif0_port_rdy_l",
-        ETM_OLIF_LIF0_PORT_RDY_Lr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x13,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_lif0_port_rdy_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_olif_rd_sop_cnt",
-        ETM_OLIF_QMU_OLIF_RD_SOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x14,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_qmu_olif_rd_sop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_olif_rd_eop_cnt",
-        ETM_OLIF_QMU_OLIF_RD_EOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x15,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_qmu_olif_rd_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_olif_rd_vld_cnt",
-        ETM_OLIF_QMU_OLIF_RD_VLD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x16,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_qmu_olif_rd_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_olif_rd_blk_cnt",
-        ETM_OLIF_QMU_OLIF_RD_BLK_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x17,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_qmu_olif_rd_blk_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mmu_tm_data_sop_cnt",
-        ETM_OLIF_MMU_TM_DATA_SOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x18,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_mmu_tm_data_sop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mmu_tm_data_eop_cnt",
-        ETM_OLIF_MMU_TM_DATA_EOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x19,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_mmu_tm_data_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mmu_tm_data_vld_cnt",
-        ETM_OLIF_MMU_TM_DATA_VLD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_mmu_tm_data_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_tm_data_sop_cnt",
-        ETM_OLIF_ODMA_TM_DATA_SOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_odma_tm_data_sop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_tm_data_eop_cnt",
-        ETM_OLIF_ODMA_TM_DATA_EOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_odma_tm_data_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_tm_deq_vld_cnt",
-        ETM_OLIF_ODMA_TM_DEQ_VLD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_odma_tm_deq_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "olif_qmu_release_vld_cnt",
-        ETM_OLIF_OLIF_QMU_RELEASE_VLD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_olif_qmu_release_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "emem_dat_vld_cnt",
-        ETM_OLIF_EMEM_DAT_VLD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_emem_dat_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "imem_dat_vld_cnt",
-        ETM_OLIF_IMEM_DAT_VLD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x21,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_imem_dat_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "emem_dat_rd_cnt",
-        ETM_OLIF_EMEM_DAT_RD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x22,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_emem_dat_rd_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "imem_dat_rd_cnt",
-        ETM_OLIF_IMEM_DAT_RD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x23,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_imem_dat_rd_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_olif_rd_sop_emem_cnt",
-        ETM_OLIF_QMU_OLIF_RD_SOP_EMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x24,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_qmu_olif_rd_sop_emem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_olif_rd_vld_emem_cnt",
-        ETM_OLIF_QMU_OLIF_RD_VLD_EMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x25,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_qmu_olif_rd_vld_emem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_last_wr_addr",
-        ETM_OLIF_CPU_LAST_WR_ADDRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x26,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_cpu_last_wr_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_last_wr_data",
-        ETM_OLIF_CPU_LAST_WR_DATAr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x27,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_cpu_last_wr_data_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_last_rd_addr",
-        ETM_OLIF_CPU_LAST_RD_ADDRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x28,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_cpu_last_rd_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_olif_last_port",
-        ETM_OLIF_QMU_OLIF_LAST_PORTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x35,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_qmu_olif_last_port_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_olif_last_addr",
-        ETM_OLIF_QMU_OLIF_LAST_ADDRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x36,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_qmu_olif_last_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_olif_last_bank",
-        ETM_OLIF_QMU_OLIF_LAST_BANKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x37,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_olif_qmu_olif_last_bank_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_lif_byte_stat",
-        ETM_OLIF_TM_LIF_BYTE_STATr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x70,
-        (32/8),
-        0,
-        0xf + 1,
-        0,
-        0x1,
-        1,
-        g_etm_olif_tm_lif_byte_stat_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_lif_err_stat",
-        ETM_OLIF_TM_LIF_ERR_STATr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x90,
-        (32/8),
-        0,
-        0xf + 1,
-        0,
-        0x1,
-        1,
-        g_etm_olif_tm_lif_err_stat_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port_share_cnt",
-        ETM_CGAVD_PORT_SHARE_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_port_share_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "total_imem_cnt",
-        ETM_CGAVD_TOTAL_IMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xa,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_total_imem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_q_len",
-        ETM_CGAVD_PP_Q_LENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0xa00,
-        (32/8),
-        0,
-        0x7f + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_pp_q_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sys_q_len",
-        ETM_CGAVD_SYS_Q_LENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1205,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_sys_q_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_cfg_error_warning",
-        ETM_CGAVD_CGAVD_CFG_ERROR_WARNINGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12de,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        12,
-        g_etm_cgavd_cgavd_cfg_error_warning_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mult_qlen_th_en",
-        ETM_CGAVD_MULT_QLEN_TH_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12df,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_mult_qlen_th_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mult_qlen_th",
-        ETM_CGAVD_MULT_QLEN_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_mult_qlen_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_cfg_move",
-        ETM_CGAVD_CGAVD_CFG_MOVEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12e1,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_etm_cgavd_cgavd_cfg_move_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_total_th",
-        ETM_CGAVD_CFGMT_TOTAL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12e2,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cfgmt_total_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_port_share_th",
-        ETM_CGAVD_CFGMT_PORT_SHARE_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x12e3,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cfgmt_port_share_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sa_unreach_state",
-        ETM_CGAVD_SA_UNREACH_STATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x1300,
-        (32/8),
-        0,
-        0x3 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_sa_unreach_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mv_port_th",
-        ETM_CGAVD_MV_PORT_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x2000,
-        (32/8),
-        0,
-        0x3f + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_mv_port_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mv_drop_sp_th",
-        ETM_CGAVD_MV_DROP_SP_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x3000,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_mv_drop_sp_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_state_warning",
-        ETM_CGAVD_CGAVD_STATE_WARNINGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x250006,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_etm_cgavd_cgavd_state_warning_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_cgavd_dma_fifo_cnt",
-        ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x250008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_cgavd_dma_fifo_cnt_max",
-        ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNT_MAXr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x250009,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_max_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "imem_total_cnt",
-        ETM_CGAVD_IMEM_TOTAL_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x25000a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_imem_total_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "imem_total_cnt_max",
-        ETM_CGAVD_IMEM_TOTAL_CNT_MAXr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x25000b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_imem_total_cnt_max_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow0_omem_cnt",
-        ETM_CGAVD_FLOW0_OMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow0_omem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow1_omem_cnt",
-        ETM_CGAVD_FLOW1_OMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260021,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow1_omem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow2_omem_cnt",
-        ETM_CGAVD_FLOW2_OMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260022,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow2_omem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow3_omem_cnt",
-        ETM_CGAVD_FLOW3_OMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260023,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow3_omem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flow4_omem_cnt",
-        ETM_CGAVD_FLOW4_OMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x260024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_flow4_omem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "appoint_flow_num_message_1",
-        ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x261000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_cgavd_appoint_flow_num_message_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "appoint_flow_num_message_2",
-        ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x261001,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_cgavd_appoint_flow_num_message_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_cgavd_pkt_num_1",
-        ETM_CGAVD_ODMA_CGAVD_PKT_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_odma_cgavd_pkt_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_cgavd_byte_num_1",
-        ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262001,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_odma_cgavd_byte_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_enqueue_pkt_num_1",
-        ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262002,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_enqueue_pkt_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_dequeue_pkt_num_1",
-        ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262003,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_dequeue_pkt_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_pkt_imem_num_1",
-        ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_pkt_imem_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_pkt_omem_num_1",
-        ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262005,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_pkt_omem_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_byte_imem_num_1",
-        ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262006,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_byte_imem_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_byte_omem_num_1",
-        ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262007,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_byte_omem_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_pkt_drop_num_1",
-        ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_pkt_drop_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_byte_drop_num_1",
-        ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262009,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_byte_drop_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_forbid_drop_num_1",
-        ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_forbid_drop_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_flow_td_drop_num_1",
-        ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262011,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_flow_td_drop_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_flow_wred_drop_num_1",
-        ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262012,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_flow_wred_drop_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_flow_wred_dp_drop_num_1",
-        ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x262100,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_pp_td_num_1",
-        ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262200,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_pp_td_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_pp_wred_drop_num_1",
-        ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262201,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_pp_wred_drop_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_pp_wred_dp_drop_num_1",
-        ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x262300,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_sys_td_drop_num_1",
-        ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262400,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_sys_td_drop_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_sys_gred_drop_num_1",
-        ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262401,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_sys_gred_drop_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_sys_gred_dp_drop_num1",
-        ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x262500,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_sa_drop_num_1",
-        ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262600,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_sa_drop_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_move_drop_num_1",
-        ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262601,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_move_drop_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_tm_mult_drop_num_1",
-        ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262602,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_tm_mult_drop_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_tm_error_drop_num_1",
-        ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x262603,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_tm_error_drop_num_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_cgavd_pkt_num_2",
-        ETM_CGAVD_ODMA_CGAVD_PKT_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_odma_cgavd_pkt_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_cgavd_byte_num_2",
-        ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263001,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_odma_cgavd_byte_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_enqueue_pkt_num_2",
-        ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263002,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_enqueue_pkt_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_dequeue_pkt_num_2",
-        ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263003,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_dequeue_pkt_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_pkt_imem_num_2",
-        ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_pkt_imem_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_pkt_omem_num_2",
-        ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263005,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_pkt_omem_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_byte_imem_num_2",
-        ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263006,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_byte_imem_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_byte_omem_num_2",
-        ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263007,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_byte_omem_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_pkt_drop_num_2",
-        ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_pkt_drop_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_byte_drop_num_2",
-        ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263009,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_byte_drop_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_forbid_drop_num_2",
-        ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_forbid_drop_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_flow_td_drop_num_2",
-        ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263011,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_flow_td_drop_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_flow_wred_drop_num_2",
-        ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263012,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_flow_wred_drop_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_flow_wred_dp_drop_num_2",
-        ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x263100,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_pp_td_num_2",
-        ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263200,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_pp_td_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_pp_wred_drop_num_2",
-        ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263201,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_pp_wred_drop_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_pp_wred_dp_drop_num_2",
-        ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x263300,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_sys_td_drop_num_2",
-        ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263400,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_sys_td_drop_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_sys_gred_drop_num_2",
-        ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263401,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_sys_gred_drop_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_sys_gred_dp_drop_num_2",
-        ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x263500,
-        (32/8),
-        0,
-        0x7 + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_sa_drop_num_2",
-        ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263600,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_sa_drop_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_move_drop_num_2",
-        ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263601,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_move_drop_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_tm_mult_drop_num_2",
-        ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263602,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_tm_mult_drop_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cgavd_qmu_tm_error_drop_num_2",
-        ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x263603,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_cgavd_cgavd_qmu_tm_error_drop_num_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "move_flow_th_profile",
-        ETM_CGAVD_MOVE_FLOW_TH_PROFILEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x270000,
-        (32/8),
-        0,
-        0x23FF + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_move_flow_th_profile_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "move_flow_th",
-        ETM_CGAVD_MOVE_FLOW_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x280000,
-        (32/8),
-        0,
-        0xF + 1,
-        0,
-        0x1,
-        1,
-        g_etm_cgavd_move_flow_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "emem_pd_fifo_aful_th",
-        ETM_TMMU_EMEM_PD_FIFO_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0009,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_emem_pd_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_data_fifo_aful_th",
-        ETM_TMMU_DMA_DATA_FIFO_AFUL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_dma_data_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_states_0",
-        ETM_TMMU_TMMU_STATES_0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        31,
-        g_etm_tmmu_tmmu_states_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_tmmu_wr_sop_cnt",
-        ETM_TMMU_QMU_TMMU_WR_SOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0013,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_qmu_tmmu_wr_sop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_tmmu_wr_eop_cnt",
-        ETM_TMMU_QMU_TMMU_WR_EOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_qmu_tmmu_wr_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_tmmu_wr_drop_cnt",
-        ETM_TMMU_QMU_TMMU_WR_DROP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0015,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_qmu_tmmu_wr_drop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_tmmu_wr_emem_cnt",
-        ETM_TMMU_QMU_TMMU_WR_EMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0016,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_qmu_tmmu_wr_emem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_tmmu_wr_imem_cnt",
-        ETM_TMMU_QMU_TMMU_WR_IMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0017,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_qmu_tmmu_wr_imem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_mmu_wr_sop_cnt",
-        ETM_TMMU_TMMU_MMU_WR_SOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_mmu_wr_sop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_mmu_wr_eop_cnt",
-        ETM_TMMU_TMMU_MMU_WR_EOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0019,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_mmu_wr_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_tmmu_rd_sop_cnt",
-        ETM_TMMU_QMU_TMMU_RD_SOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x001a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_qmu_tmmu_rd_sop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_tmmu_rd_eop_cnt",
-        ETM_TMMU_QMU_TMMU_RD_EOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x001b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_qmu_tmmu_rd_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_tmmu_rd_drop_cnt",
-        ETM_TMMU_QMU_TMMU_RD_DROP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_qmu_tmmu_rd_drop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_tmmu_rd_emem_cnt",
-        ETM_TMMU_QMU_TMMU_RD_EMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x001d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_qmu_tmmu_rd_emem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_tmmu_rd_imem_cnt",
-        ETM_TMMU_QMU_TMMU_RD_IMEM_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x001e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_qmu_tmmu_rd_imem_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_mmu_rd_sop_cnt",
-        ETM_TMMU_TMMU_MMU_RD_SOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x001f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_mmu_rd_sop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_mmu_rd_eop_cnt",
-        ETM_TMMU_TMMU_MMU_RD_EOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_mmu_rd_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_odma_in_sop_cnt",
-        ETM_TMMU_TMMU_ODMA_IN_SOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0021,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_odma_in_sop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_odma_in_eop_cnt",
-        ETM_TMMU_TMMU_ODMA_IN_EOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0022,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_odma_in_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_odma_vld_cnt",
-        ETM_TMMU_TMMU_ODMA_VLD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0023,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_odma_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_pd_in_cnt",
-        ETM_TMMU_QMU_PD_IN_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_qmu_pd_in_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_pd_hit_cnt",
-        ETM_TMMU_TMMU_PD_HIT_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0025,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_pd_hit_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_pd_out_cnt",
-        ETM_TMMU_TMMU_PD_OUT_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0026,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_pd_out_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_wr_cmd_fifo_wr_cnt",
-        ETM_TMMU_TMMU_WR_CMD_FIFO_WR_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0027,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_wr_cmd_fifo_wr_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_imem_age_cnt",
-        ETM_TMMU_TMMU_IMEM_AGE_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_imem_age_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_cmdsch_rd_cnt",
-        ETM_TMMU_TMMU_CMDSCH_RD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0029,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_cmdsch_rd_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_cmdsch_drop_cnt",
-        ETM_TMMU_TMMU_CMDSCH_DROP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x002a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_cmdsch_drop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_cmdsw_drop_cnt",
-        ETM_TMMU_TMMU_CMDSW_DROP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x002b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_cmdsw_drop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_odma_enq_rd_cnt",
-        ETM_TMMU_TMMU_ODMA_ENQ_RD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x002c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_odma_enq_rd_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_odma_enq_drop_cnt",
-        ETM_TMMU_TMMU_ODMA_ENQ_DROP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x002d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_odma_enq_drop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_odma_imem_age_cnt",
-        ETM_TMMU_TMMU_ODMA_IMEM_AGE_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x002e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_odma_imem_age_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_odma_deq_rd_cnt",
-        ETM_TMMU_TMMU_ODMA_DEQ_RD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x002f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_odma_deq_rd_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tmmu_odma_deq_drop_cnt",
-        ETM_TMMU_TMMU_ODMA_DEQ_DROP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tmmu_odma_deq_drop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "olif_tmmu_xoff_cnt",
-        ETM_TMMU_OLIF_TMMU_XOFF_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0031,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_olif_tmmu_xoff_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_tm_data_xoff_cnt",
-        ETM_TMMU_ODMA_TM_DATA_XOFF_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0032,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_odma_tm_data_xoff_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_odma_pkt_xoff_cnt",
-        ETM_TMMU_TM_ODMA_PKT_XOFF_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0033,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_tm_odma_pkt_xoff_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_state_3",
-        ETM_TMMU_TM_STATE_3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_tmmu_tm_state_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_pd_cache_cmd",
-        ETM_TMMU_CFGMT_PD_CACHE_CMDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_pd_cache_cmd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_pd_cache_rd_done",
-        ETM_TMMU_CFGMT_PD_CACHE_RD_DONEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0051,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_pd_cache_rd_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_pd_cache_rd_data_0",
-        ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0052,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_pd_cache_rd_data_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_pd_cache_rd_data_1",
-        ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0053,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_pd_cache_rd_data_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_pd_cache_rd_data_2",
-        ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_pd_cache_rd_data_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_pd_cache_rd_data_3",
-        ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0055,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_pd_cache_rd_data_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_tmmu_to_odma_para",
-        ETM_TMMU_CFGMT_TMMU_TO_ODMA_PARAr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0056,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_tmmu_to_odma_para_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_dma_data_fifo_cnt",
-        ETM_TMMU_CFGMT_DMA_DATA_FIFO_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0057,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_dma_data_fifo_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_tag_bit0_offset",
-        ETM_TMMU_CFGMT_CACHE_TAG_BIT0_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_tag_bit0_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_tag_bit1_offset",
-        ETM_TMMU_CFGMT_CACHE_TAG_BIT1_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0061,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_tag_bit1_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_tag_bit2_offset",
-        ETM_TMMU_CFGMT_CACHE_TAG_BIT2_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0062,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_tag_bit2_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_tag_bit3_offset",
-        ETM_TMMU_CFGMT_CACHE_TAG_BIT3_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0063,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_tag_bit3_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_tag_bit4_offset",
-        ETM_TMMU_CFGMT_CACHE_TAG_BIT4_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_tag_bit4_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_tag_bit5_offset",
-        ETM_TMMU_CFGMT_CACHE_TAG_BIT5_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0065,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_tag_bit5_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_index_bit0_offset",
-        ETM_TMMU_CFGMT_CACHE_INDEX_BIT0_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0066,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_index_bit0_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_index_bit1_offset",
-        ETM_TMMU_CFGMT_CACHE_INDEX_BIT1_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0067,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_index_bit1_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_index_bit2_offset",
-        ETM_TMMU_CFGMT_CACHE_INDEX_BIT2_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_index_bit2_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_index_bit3_offset",
-        ETM_TMMU_CFGMT_CACHE_INDEX_BIT3_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0069,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_index_bit3_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_index_bit4_offset",
-        ETM_TMMU_CFGMT_CACHE_INDEX_BIT4_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x006a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_index_bit4_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_index_bit5_offset",
-        ETM_TMMU_CFGMT_CACHE_INDEX_BIT5_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x006b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_index_bit5_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_index_bit6_offset",
-        ETM_TMMU_CFGMT_CACHE_INDEX_BIT6_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x006c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_index_bit6_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_index_bit7_offset",
-        ETM_TMMU_CFGMT_CACHE_INDEX_BIT7_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x006d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_index_bit7_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_index_bit8_offset",
-        ETM_TMMU_CFGMT_CACHE_INDEX_BIT8_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x006e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_index_bit8_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_index_bit9_offset",
-        ETM_TMMU_CFGMT_CACHE_INDEX_BIT9_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x006f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_index_bit9_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_index_bit10_offset",
-        ETM_TMMU_CFGMT_CACHE_INDEX_BIT10_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0070,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_index_bit10_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_index_bit11_offset",
-        ETM_TMMU_CFGMT_CACHE_INDEX_BIT11_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0071,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_index_bit11_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_cache_index_bit12_offset",
-        ETM_TMMU_CFGMT_CACHE_INDEX_BIT12_OFFSETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0072,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_tmmu_cfgmt_cache_index_bit12_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "bktfull_fifo_full_flagregister",
-        ETM_SHAP_BKTFULL_FIFO_FULL_FLAGREGISTERr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x26,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_bktfull_fifo_full_flagregister_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fifo_full_regregister",
-        ETM_SHAP_FIFO_FULL_REGREGISTERr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x29,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_fifo_full_regregister_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fifo_empty_regregister",
-        ETM_SHAP_FIFO_EMPTY_REGREGISTERr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_fifo_empty_regregister_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fifo_almost_full_regregister",
-        ETM_SHAP_FIFO_ALMOST_FULL_REGREGISTERr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_fifo_almost_full_regregister_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fifo_almost_empty_regregister",
-        ETM_SHAP_FIFO_ALMOST_EMPTY_REGREGISTERr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x32,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_shap_fifo_almost_empty_regregister_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "credit_space_select",
-        ETM_CRDT_CREDIT_SPACE_SELECTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x000e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_credit_space_select_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_space_max",
-        ETM_CRDT_STAT_SPACE_MAXr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x30,
-        (32/8),
-        0,
-        0x0f + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_stat_space_max_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_space_min",
-        ETM_CRDT_STAT_SPACE_MINr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x40,
-        (32/8),
-        0,
-        0x0f + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_stat_space_min_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_space_credit",
-        ETM_CRDT_STAT_SPACE_CREDITr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x50,
-        (32/8),
-        0,
-        0x0f + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_stat_space_credit_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_que_step8_credit",
-        ETM_CRDT_STAT_QUE_STEP8_CREDITr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x60,
-        (32/8),
-        0,
-        0x07 + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_stat_que_step8_credit_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "special_que",
-        ETM_CRDT_SPECIAL_QUEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x68,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_special_que_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "special_que_credit",
-        ETM_CRDT_SPECIAL_QUE_CREDITr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x69,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_special_que_credit_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lif_congest_credit_cnt",
-        ETM_CRDT_LIF_CONGEST_CREDIT_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x70,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_lif_congest_credit_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lif_port_congest_credit_cnt",
-        ETM_CRDT_LIF_PORT_CONGEST_CREDIT_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x71,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_lif_port_congest_credit_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_congest_credit_cnt",
-        ETM_CRDT_CRDT_CONGEST_CREDIT_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x72,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crdt_congest_credit_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_port_congest_credit_cnt",
-        ETM_CRDT_CRDT_PORT_CONGEST_CREDIT_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x73,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crdt_port_congest_credit_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "congest_port_id",
-        ETM_CRDT_CONGEST_PORT_IDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x74,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_congest_port_id_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dev_link_control",
-        ETM_CRDT_DEV_LINK_CONTROLr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x75,
-        (32/8),
-        0,
-        0x1 + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_dev_link_control_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_sa_port_rdy",
-        ETM_CRDT_CRDT_SA_PORT_RDYr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x77,
-        (32/8),
-        0,
-        0x1 + 1,
-        0,
-        1,
-        1,
-        g_etm_crdt_crdt_sa_port_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_congest_mode_select",
-        ETM_CRDT_CRDT_CONGEST_MODE_SELECTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x81,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crdt_congest_mode_select_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fifo_out_all_crs_normal_cnt",
-        ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x82,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_fifo_out_all_crs_normal_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fifo_out_all_crs_off_cnt",
-        ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x83,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_fifo_out_all_crs_off_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fifo_out_que_crs_normal_cnt",
-        ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x84,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_fifo_out_que_crs_normal_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fifo_out_que_crs_off_cnt",
-        ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x85,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_fifo_out_que_crs_off_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mode_add_60g",
-        ETM_CRDT_MODE_ADD_60Gr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x9a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_mode_add_60g_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_token_add",
-        ETM_CRDT_PP_TOKEN_ADDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x9b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_pp_token_add_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_cir_token_total_dist_cnt",
-        ETM_CRDT_PP_CIR_TOKEN_TOTAL_DIST_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x9c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_pp_cir_token_total_dist_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_cir_token_total_dec_cnt",
-        ETM_CRDT_PP_CIR_TOKEN_TOTAL_DEC_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x9d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_pp_cir_token_total_dec_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dev_credit_cnt",
-        ETM_CRDT_DEV_CREDIT_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xb0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_dev_credit_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "no_credit_cnt1",
-        ETM_CRDT_NO_CREDIT_CNT1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xb7,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_no_credit_cnt1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "no_credit_cnt2",
-        ETM_CRDT_NO_CREDIT_CNT2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xb8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_no_credit_cnt2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "asm_interval_0_cfg",
-        ETM_CRDT_ASM_INTERVAL_0_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xc7,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_asm_interval_0_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "asm_interval_1_cfg",
-        ETM_CRDT_ASM_INTERVAL_1_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xc8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_asm_interval_1_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "asm_interval_2_cfg",
-        ETM_CRDT_ASM_INTERVAL_2_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xc9,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_asm_interval_2_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "asm_interval_3_cfg",
-        ETM_CRDT_ASM_INTERVAL_3_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xca,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_asm_interval_3_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "asm_interval_4_cfg",
-        ETM_CRDT_ASM_INTERVAL_4_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xcb,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_asm_interval_4_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "asm_interval_5cfg",
-        ETM_CRDT_ASM_INTERVAL_5CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xcc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_asm_interval_5cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "asm_interval_6_cfg",
-        ETM_CRDT_ASM_INTERVAL_6_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xcd,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_asm_interval_6_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "asm_interval_7_cfg",
-        ETM_CRDT_ASM_INTERVAL_7_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xce,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_asm_interval_7_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_total_congest_mode_cfg",
-        ETM_CRDT_CRDT_TOTAL_CONGEST_MODE_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xcf,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crdt_total_congest_mode_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rci_fifo_ini_deep_cfg",
-        ETM_CRDT_RCI_FIFO_INI_DEEP_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xd0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_rci_fifo_ini_deep_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_ecc",
-        ETM_CRDT_CRDT_ECCr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x121,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_etm_crdt_crdt_ecc_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ucn_asm_rdy_shield_en",
-        ETM_CRDT_UCN_ASM_RDY_SHIELD_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x013a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_crdt_ucn_asm_rdy_shield_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ucn_asm_rdy",
-        ETM_CRDT_UCN_ASM_RDYr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x013b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_crdt_ucn_asm_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rci_grade",
-        ETM_CRDT_RCI_GRADEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x013c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_rci_grade_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_rci_value_r",
-        ETM_CRDT_CRDT_RCI_VALUE_Rr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x013d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crdt_rci_value_r_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_interval_now",
-        ETM_CRDT_CRDT_INTERVAL_NOWr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x013e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crdt_interval_now_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crs_sheild_flow_id_cfg",
-        ETM_CRDT_CRS_SHEILD_FLOW_ID_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0140,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crs_sheild_flow_id_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crs_sheild_en_cfg",
-        ETM_CRDT_CRS_SHEILD_EN_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0141,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crs_sheild_en_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crs_sheild_value_cfg",
-        ETM_CRDT_CRS_SHEILD_VALUE_CFGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x0142,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_crs_sheild_value_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_token_calc_ctrl",
-        ETM_CRDT_TEST_TOKEN_CALC_CTRLr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x14c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_crdt_test_token_calc_ctrl_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_token_sample_cycle_num",
-        ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x14d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_crdt_test_token_sample_cycle_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "q_state_0_7",
-        ETM_CRDT_Q_STATE_0_7r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x14e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        8,
-        g_etm_crdt_q_state_0_7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "q_state_8_15",
-        ETM_CRDT_Q_STATE_8_15r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x14f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        8,
-        g_etm_crdt_q_state_8_15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csw_csch_rd_cmd_cnt",
-        ETM_QMU_CSW_CSCH_RD_CMD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x14,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csw_csch_rd_cmd_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csw_csch_rd_sop_cnt",
-        ETM_QMU_CSW_CSCH_RD_SOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x15,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csw_csch_rd_sop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csw_csch_rd_eop_cnt",
-        ETM_QMU_CSW_CSCH_RD_EOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x16,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csw_csch_rd_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csw_csch_rd_drop_cnt",
-        ETM_QMU_CSW_CSCH_RD_DROP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x17,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csw_csch_rd_drop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csch_mmu_rd_cmd_cnt",
-        ETM_QMU_CSCH_MMU_RD_CMD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x18,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csch_mmu_rd_cmd_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csch_mmu_rd_sop_cnt",
-        ETM_QMU_CSCH_MMU_RD_SOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x19,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csch_mmu_rd_sop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csch_mmu_rd_eop_cnt",
-        ETM_QMU_CSCH_MMU_RD_EOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csch_mmu_rd_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csch_mmu_rd_drop_cnt",
-        ETM_QMU_CSCH_MMU_RD_DROP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csch_mmu_rd_drop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qsch_crs_filter",
-        ETM_QMU_QCFG_QSCH_CRS_FILTERr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qcfg_qsch_crs_filter_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qsch_crs_force_en",
-        ETM_QMU_QCFG_QSCH_CRS_FORCE_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qcfg_qsch_crs_force_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qsch_crs_force_qnum",
-        ETM_QMU_QCFG_QSCH_CRS_FORCE_QNUMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qcfg_qsch_crs_force_qnum_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qsch_crs_force_crs",
-        ETM_QMU_QCFG_QSCH_CRS_FORCE_CRSr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x1f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qcfg_qsch_crs_force_crs_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_oshp_sgmii_shap_mode",
-        ETM_QMU_CFGMT_OSHP_SGMII_SHAP_MODEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_oshp_sgmii_shap_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_sashap_en",
-        ETM_QMU_CFGMT_QMU_SASHAP_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x21,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_qmu_sashap_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_sashap_token_max",
-        ETM_QMU_CFGMT_SASHAP_TOKEN_MAXr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x39,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_sashap_token_max_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_sashap_token_min",
-        ETM_QMU_CFGMT_SASHAP_TOKEN_MINr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x3a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfgmt_sashap_token_min_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_q3lbaddrate",
-        ETM_QMU_CFG_QSCH_Q3LBADDRATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x3f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_q3lbaddrate_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_q012lbaddrate",
-        ETM_QMU_CFG_QSCH_Q012LBADDRATEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x40,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_q012lbaddrate_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_q3creditlbmaxcnt",
-        ETM_QMU_CFG_QSCH_Q3CREDITLBMAXCNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x41,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_q3creditlbmaxcnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_q012creditlbmaxcnt",
-        ETM_QMU_CFG_QSCH_Q012CREDITLBMAXCNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x42,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_q012creditlbmaxcnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mul_token_gen_num",
-        ETM_QMU_CFG_QSCH_MUL_TOKEN_GEN_NUMr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x43,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mul_token_gen_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_q3_credit_lb_control_en",
-        ETM_QMU_CFG_QSCH_Q3_CREDIT_LB_CONTROL_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x44,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_q3_credit_lb_control_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_q012_credit_lb_control_en",
-        ETM_QMU_CFG_QSCH_Q012_CREDIT_LB_CONTROL_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x45,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_q012_credit_lb_control_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_sp_dwrr_en",
-        ETM_QMU_CFG_QSCH_SP_DWRR_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x46,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_sp_dwrr_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_q01_attach_en",
-        ETM_QMU_CFG_QSCH_Q01_ATTACH_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x47,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_q01_attach_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_w0",
-        ETM_QMU_CFG_QSCH_W0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x48,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_w0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_w1",
-        ETM_QMU_CFG_QSCH_W1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x49,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_w1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_w2",
-        ETM_QMU_CFG_QSCH_W2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x4a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_w2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_lkybktmaxcnt1",
-        ETM_QMU_CFG_QSCH_LKYBKTMAXCNT1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x4b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_lkybktmaxcnt1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_lkybktmaxcnt2",
-        ETM_QMU_CFG_QSCH_LKYBKTMAXCNT2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x4c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_lkybktmaxcnt2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_lkybktdcrrate1",
-        ETM_QMU_CFG_QSCH_LKYBKTDCRRATE1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x4d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_lkybktdcrrate1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_lkybktdcrrate2",
-        ETM_QMU_CFG_QSCH_LKYBKTDCRRATE2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x4e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_lkybktdcrrate2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_lkybktdcrrate3",
-        ETM_QMU_CFG_QSCH_LKYBKTDCRRATE3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x4f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_lkybktdcrrate3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_lkybktmaxcnt3",
-        ETM_QMU_CFG_QSCH_LKYBKTMAXCNT3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x50,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_lkybktmaxcnt3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_qmu_mul_auto_sa_version",
-        ETM_QMU_CFG_QSCH_QMU_MUL_AUTO_SA_VERSIONr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x55,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_qmu_mul_auto_sa_version_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_sa_credit_value_0",
-        ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x56,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_sa_credit_value_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_sa_credit_value_1",
-        ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x57,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_sa_credit_value_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_sa_credit_value_2",
-        ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x58,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_sa_credit_value_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_sa_credit_value_3",
-        ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x59,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_sa_credit_value_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_sa_credit_value_4",
-        ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_4r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x5a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_sa_credit_value_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_sa_credit_value_5",
-        ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_5r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x5b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_sa_credit_value_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_sa_credit_value_6",
-        ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_6r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x5c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_sa_credit_value_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_sa_credit_value_7",
-        ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_7r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x5d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_sa_credit_value_7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_remote_credit_fifo_almost_full_th",
-        ETM_QMU_CFG_QSCH_REMOTE_CREDIT_FIFO_ALMOST_FULL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x76,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_remote_credit_fifo_almost_full_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_auto_credit_fifo_almost_full_th",
-        ETM_QMU_CFG_QSCH_AUTO_CREDIT_FIFO_ALMOST_FULL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x77,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_auto_credit_fifo_almost_full_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_q3_credit_fifo_almost_full_th",
-        ETM_QMU_CFG_QSCH_Q3_CREDIT_FIFO_ALMOST_FULL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x78,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_q3_credit_fifo_almost_full_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_q012_credit_fifo_almost_full_th",
-        ETM_QMU_CFG_QSCH_Q012_CREDIT_FIFO_ALMOST_FULL_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x79,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_q012_credit_fifo_almost_full_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mul_fc_res_en",
-        ETM_QMU_CFG_QSCH_MUL_FC_RES_ENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x7a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mul_fc_res_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_mul_ovf_udf_flg_query",
-        ETM_QMU_CFGMT_MUL_OVF_UDF_FLG_QUERYr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x7d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        19,
-        g_etm_qmu_cfgmt_mul_ovf_udf_flg_query_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_mul_cng_flg_query",
-        ETM_QMU_CFGMT_MUL_CNG_FLG_QUERYr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x7e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_etm_qmu_cfgmt_mul_cng_flg_query_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qsch_cfg_lkybktval1",
-        ETM_QMU_QSCH_CFG_LKYBKTVAL1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x7f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qsch_cfg_lkybktval1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qsch_cfg_lkybktval2",
-        ETM_QMU_QSCH_CFG_LKYBKTVAL2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x80,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qsch_cfg_lkybktval2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qsch_cfg_lkybktval3",
-        ETM_QMU_QSCH_CFG_LKYBKTVAL3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x81,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qsch_cfg_lkybktval3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qsch_cfg_q3lbval",
-        ETM_QMU_QSCH_CFG_Q3LBVALr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x82,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qsch_cfg_q3lbval_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qsch_cfg_q012lbval",
-        ETM_QMU_QSCH_CFG_Q012LBVALr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x83,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qsch_cfg_q012lbval_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qlist_cfgmt_ram_ecc_err2",
-        ETM_QMU_QLIST_CFGMT_RAM_ECC_ERR2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        16,
-        g_etm_qmu_qlist_cfgmt_ram_ecc_err2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csch_aged_cmd_cnt",
-        ETM_QMU_CSCH_AGED_CMD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2838,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csch_aged_cmd_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csch_qcfg_csch_congest_cnt",
-        ETM_QMU_CSCH_QCFG_CSCH_CONGEST_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2839,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csch_qcfg_csch_congest_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csch_qcfg_qlist_csch_sop_cnt",
-        ETM_QMU_CSCH_QCFG_QLIST_CSCH_SOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x283a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csch_qcfg_qlist_csch_sop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csch_qcfg_qlist_csch_eop_cnt",
-        ETM_QMU_CSCH_QCFG_QLIST_CSCH_EOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x283b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csch_qcfg_qlist_csch_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csch_qcfg_csch_csw_sop_cnt",
-        ETM_QMU_CSCH_QCFG_CSCH_CSW_SOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x283c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csch_qcfg_csch_csw_sop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csch_qcfg_csch_csw_eop_cnt",
-        ETM_QMU_CSCH_QCFG_CSCH_CSW_EOP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x283d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csch_qcfg_csch_csw_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csch_qcfg_qlist_csch_drop_cnt",
-        ETM_QMU_CSCH_QCFG_QLIST_CSCH_DROP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x283e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csch_qcfg_qlist_csch_drop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csch_qcfg_csch_csw_drop_cnt",
-        ETM_QMU_CSCH_QCFG_CSCH_CSW_DROP_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x283f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csch_qcfg_csch_csw_drop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csw_mmu_sop_cmd_cnt",
-        ETM_QMU_CSW_MMU_SOP_CMD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2840,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csw_mmu_sop_cmd_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mmu_csw_sop_data_cnt",
-        ETM_QMU_MMU_CSW_SOP_DATA_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2841,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_mmu_csw_sop_data_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csw_qsch_feedb_cnt",
-        ETM_QMU_CSW_QSCH_FEEDB_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2842,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_csw_qsch_feedb_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_crdt_port_fc_cnt",
-        ETM_QMU_QMU_CRDT_PORT_FC_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2843,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_crdt_port_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "csch_r_block_cnt",
-        ETM_QMU_CSCH_R_BLOCK_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x3400,
-        (32/8),
-        0,
-        0x1ff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_csch_r_block_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_qds_head_rd",
-        ETM_QMU_QCFG_QLIST_QDS_HEAD_RDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x10000,
-        (32/8),
-        0,
-        0x23ff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_qds_head_rd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_qds_tail_rd",
-        ETM_QMU_QCFG_QLIST_QDS_TAIL_RDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x20000,
-        (32/8),
-        0,
-        0x23ff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_qds_tail_rd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_ept_rd",
-        ETM_QMU_QCFG_QLIST_EPT_RDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x30000,
-        (32/8),
-        0,
-        0x23ff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_ept_rd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_age_flag_rd",
-        ETM_QMU_QCFG_QLIST_AGE_FLAG_RDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x38000,
-        (32/8),
-        0,
-        0x23ff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_age_flag_rd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_cti_rd",
-        ETM_QMU_QCFG_QLIST_CTI_RDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x40000,
-        (32/8),
-        0,
-        0x23ff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_cti_rd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_cto_rd",
-        ETM_QMU_QCFG_QLIST_CTO_RDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x50000,
-        (32/8),
-        0,
-        0x23ff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_cto_rd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_chk_rd",
-        ETM_QMU_QCFG_QLIST_CHK_RDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x100000,
-        (32/8),
-        0,
-        0x7fff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_chk_rd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_nod_rd",
-        ETM_QMU_QCFG_QLIST_NOD_RDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x140000,
-        (32/8),
-        0,
-        0x7fff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_nod_rd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_qlist_biu_rd",
-        ETM_QMU_QCFG_QLIST_BIU_RDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x180000,
-        (32/8),
-        0,
-        0x7fff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_qlist_biu_rd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qsch_r_wlist_flag",
-        ETM_QMU_QSCH_R_WLIST_FLAGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x90000,
-        (32/8),
-        0,
-        0x23ff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qsch_r_wlist_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qcfg_crs_flg_rd",
-        ETM_QMU_QCFG_CRS_FLG_RDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0xd0000,
-        (32/8),
-        0,
-        0x23ff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_qcfg_crs_flg_rd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_imem_age_qds",
-        ETM_QMU_CFGMT_QMU_IMEM_AGE_QDSr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe0d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_qmu_cfgmt_qmu_imem_age_qds_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_imem_age_qlen",
-        ETM_QMU_CFGMT_QMU_IMEM_AGE_QLENr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0xe0e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_qmu_cfgmt_qmu_imem_age_qlen_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_imem_pd_ram_low",
-        ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_LOWr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x1c0000,
-        (32/8),
-        0,
-        0x3fff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_cfgmt_qmu_imem_pd_ram_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_imem_pd_ram_high",
-        ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_HIGHr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x1c4000,
-        (32/8),
-        0,
-        0x3fff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_cfgmt_qmu_imem_pd_ram_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_imem_up_ptr",
-        ETM_QMU_CFGMT_QMU_IMEM_UP_PTRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x200000,
-        (32/8),
-        0,
-        0x3fff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_cfgmt_qmu_imem_up_ptr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_imem_down_ptr",
-        ETM_QMU_CFGMT_QMU_IMEM_DOWN_PTRr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x240000,
-        (32/8),
-        0,
-        0x3fff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_cfgmt_qmu_imem_down_ptr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfgmt_qmu_imem_age_flag",
-        ETM_QMU_CFGMT_QMU_IMEM_AGE_FLAGr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x280000,
-        (32/8),
-        0,
-        0x7ffff + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_cfgmt_qmu_imem_age_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_lkybkt2cngth",
-        ETM_QMU_CFG_QSCH_LKYBKT2CNGTHr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x2040,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_cfg_qsch_lkybkt2cngth_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_lkybkt1cngth",
-        ETM_QMU_CFG_QSCH_LKYBKT1CNGTHr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x2030,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_cfg_qsch_lkybkt1cngth_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_lkybkt3cngth",
-        ETM_QMU_CFG_QSCH_LKYBKT3CNGTHr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x2050,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_cfg_qsch_lkybkt3cngth_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_rm_mul_mcn1_credit_value",
-        ETM_QMU_CFG_QSCH_RM_MUL_MCN1_CREDIT_VALUEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x2060,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_cfg_qsch_rm_mul_mcn1_credit_value_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_rm_mul_mcn2_credit_value",
-        ETM_QMU_CFG_QSCH_RM_MUL_MCN2_CREDIT_VALUEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x2070,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_cfg_qsch_rm_mul_mcn2_credit_value_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_rm_mul_mcn3_credit_value",
-        ETM_QMU_CFG_QSCH_RM_MUL_MCN3_CREDIT_VALUEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x2080,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        1,
-        1,
-        g_etm_qmu_cfg_qsch_rm_mul_mcn3_credit_value_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn1_rand_ansr_seed",
-        ETM_QMU_RM_MUL_MCN1_RAND_ANSR_SEEDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_qmu_rm_mul_mcn1_rand_ansr_seed_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn2_rand_ansr_seed",
-        ETM_QMU_RM_MUL_MCN2_RAND_ANSR_SEEDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2091,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_qmu_rm_mul_mcn2_rand_ansr_seed_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn3_rand_ansr_seed",
-        ETM_QMU_RM_MUL_MCN3_RAND_ANSR_SEEDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2092,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_qmu_rm_mul_mcn3_rand_ansr_seed_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn1_rand_ansr_th",
-        ETM_QMU_RM_MUL_MCN1_RAND_ANSR_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2093,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn1_rand_ansr_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn2_rand_ansr_th",
-        ETM_QMU_RM_MUL_MCN2_RAND_ANSR_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn2_rand_ansr_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn3_rand_ansr_th",
-        ETM_QMU_RM_MUL_MCN3_RAND_ANSR_THr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2095,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn3_rand_ansr_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn1_rand_hold_base",
-        ETM_QMU_RM_MUL_MCN1_RAND_HOLD_BASEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2096,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_qmu_rm_mul_mcn1_rand_hold_base_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn2_rand_hold_base",
-        ETM_QMU_RM_MUL_MCN2_RAND_HOLD_BASEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2097,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_qmu_rm_mul_mcn2_rand_hold_base_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn3_rand_hold_base",
-        ETM_QMU_RM_MUL_MCN3_RAND_HOLD_BASEr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2098,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_qmu_rm_mul_mcn3_rand_hold_base_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn1_rand_sel_mask",
-        ETM_QMU_RM_MUL_MCN1_RAND_SEL_MASKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2099,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn1_rand_sel_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn2_rand_sel_mask",
-        ETM_QMU_RM_MUL_MCN2_RAND_SEL_MASKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x209a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn2_rand_sel_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn3_rand_sel_mask",
-        ETM_QMU_RM_MUL_MCN3_RAND_SEL_MASKr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x209b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn3_rand_sel_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn1_rand_sel_seed_reg0",
-        ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x209c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        8,
-        g_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn1_rand_sel_seed_reg1",
-        ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x209d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn2_rand_sel_seed_reg0",
-        ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x209e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        8,
-        g_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn2_rand_sel_seed_reg1",
-        ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x209f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn3_rand_sel_seed_reg0",
-        ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        8,
-        g_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn3_rand_sel_seed_reg1",
-        ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20a1,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn1_step_wait_th1",
-        ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20a2,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn1_step_wait_th1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn1_step_wait_th2",
-        ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20a3,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn1_step_wait_th2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn1_step_wait_th3",
-        ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn1_step_wait_th3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn1_step_wait_th4",
-        ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH4r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20a5,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn1_step_wait_th4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn1_step_wait_th5",
-        ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH5r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20a6,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn1_step_wait_th5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn1_step_wait_th6",
-        ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH6r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20a7,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn1_step_wait_th6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn1_step_wait_th7",
-        ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH7r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn1_step_wait_th7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn2_step_wait_th1",
-        ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20a9,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn2_step_wait_th1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn2_step_wait_th2",
-        ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20aa,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn2_step_wait_th2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn2_step_wait_th3",
-        ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20ab,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn2_step_wait_th3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn2_step_wait_th4",
-        ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH4r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn2_step_wait_th4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn2_step_wait_th5",
-        ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH5r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20ad,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn2_step_wait_th5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn2_step_wait_th6",
-        ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH6r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20ae,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn2_step_wait_th6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn2_step_wait_th7",
-        ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH7r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20af,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn2_step_wait_th7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn3_step_wait_th1",
-        ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn3_step_wait_th1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn3_step_wait_th2",
-        ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20b1,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn3_step_wait_th2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn3_step_wait_th3",
-        ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20b2,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn3_step_wait_th3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn3_step_wait_th4",
-        ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH4r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20b3,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn3_step_wait_th4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn3_step_wait_th5",
-        ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH5r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn3_step_wait_th5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn3_step_wait_th6",
-        ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH6r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20b5,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn3_step_wait_th6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rm_mul_mcn3step_wait_th7",
-        ETM_QMU_RM_MUL_MCN3STEP_WAIT_TH7r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20b6,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_rm_mul_mcn3step_wait_th7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate0",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE0r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20b7,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate1",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE1r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate2",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE2r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20b9,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate3",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE3r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20ba,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate4",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE4r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20bb,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate5",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE5r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate6",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE6r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20bd,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate7",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE7r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20be,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate8",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE8r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20bf,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate9",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE9r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate10",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE10r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20c1,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate11",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE11r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20c2,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate12",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE12r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20c3,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate13",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE13r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate14",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE14r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20c5,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate15",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE15r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20c6,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate16",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE16r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20c7,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate17",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE17r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate18",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE18r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20c9,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate19",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE19r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20ca,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate19_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate20",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE20r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20cb,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate20_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate21",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE21r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate21_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate22",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE22r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20cd,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate22_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate23",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE23r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20ce,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate23_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate24",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE24r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20cf,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate24_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate25",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE25r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate25_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate26",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE26r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20d1,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate27",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE27r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20d2,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate27_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate28",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE28r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20d3,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate28_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate29",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE29r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate29_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate30",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE30r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20d5,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate30_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate31",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE31r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20d6,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate31_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate32",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE32r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20d7,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate33",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE33r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate33_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate34",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE34r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20d9,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate34_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate35",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE35r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20da,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate35_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_mulcrdcntrate36",
-        ETM_QMU_CFG_QSCH_MULCRDCNTRATE36r,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20db,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_mulcrdcntrate36_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_rm_mul_mcn1_rand_hold_shift",
-        ETM_QMU_CFG_QSCH_RM_MUL_MCN1_RAND_HOLD_SHIFTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_rm_mul_mcn1_rand_hold_shift_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_rm_mul_mcn2_rand_hold_shift",
-        ETM_QMU_CFG_QSCH_RM_MUL_MCN2_RAND_HOLD_SHIFTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20dd,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_rm_mul_mcn2_rand_hold_shift_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_qsch_rm_mul_mcn3_rand_hold_shift",
-        ETM_QMU_CFG_QSCH_RM_MUL_MCN3_RAND_HOLD_SHIFTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x20de,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_cfg_qsch_rm_mul_mcn3_rand_hold_shift_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "last_drop_qnum_get",
-        ETM_QMU_LAST_DROP_QNUM_GETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2806,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_etm_qmu_last_drop_qnum_get_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crdt_qmu_credit_cnt",
-        ETM_QMU_CRDT_QMU_CREDIT_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2807,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_crdt_qmu_credit_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_to_qsch_report_cnt",
-        ETM_QMU_QMU_TO_QSCH_REPORT_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2808,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_to_qsch_report_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_to_cgavd_report_cnt",
-        ETM_QMU_QMU_TO_CGAVD_REPORT_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2809,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_to_cgavd_report_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_crdt_crs_normal_cnt",
-        ETM_QMU_QMU_CRDT_CRS_NORMAL_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x280a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_crdt_crs_normal_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_crdt_crs_off_cnt",
-        ETM_QMU_QMU_CRDT_CRS_OFF_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x280b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_crdt_crs_off_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qsch_qlist_shedule_cnt",
-        ETM_QMU_QSCH_QLIST_SHEDULE_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x280c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qsch_qlist_shedule_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qsch_qlist_sch_ept_cnt",
-        ETM_QMU_QSCH_QLIST_SCH_EPT_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x280d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qsch_qlist_sch_ept_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_to_mmu_blk_wr_cnt",
-        ETM_QMU_QMU_TO_MMU_BLK_WR_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x280e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_to_mmu_blk_wr_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_to_csw_blk_rd_cnt",
-        ETM_QMU_QMU_TO_CSW_BLK_RD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x280f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_to_csw_blk_rd_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_to_mmu_sop_wr_cnt",
-        ETM_QMU_QMU_TO_MMU_SOP_WR_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2810,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_to_mmu_sop_wr_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_to_mmu_eop_wr_cnt",
-        ETM_QMU_QMU_TO_MMU_EOP_WR_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2811,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_to_mmu_eop_wr_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_to_mmu_drop_wr_cnt",
-        ETM_QMU_QMU_TO_MMU_DROP_WR_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2812,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_to_mmu_drop_wr_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_to_csw_sop_rd_cnt",
-        ETM_QMU_QMU_TO_CSW_SOP_RD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2813,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_to_csw_sop_rd_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_to_csw_eop_rd_cnt",
-        ETM_QMU_QMU_TO_CSW_EOP_RD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2814,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_to_csw_eop_rd_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "qmu_to_csw_drop_rd_cnt",
-        ETM_QMU_QMU_TO_CSW_DROP_RD_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2815,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_qmu_to_csw_drop_rd_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mmu_to_qmu_wr_release_cnt",
-        ETM_QMU_MMU_TO_QMU_WR_RELEASE_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2816,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_mmu_to_qmu_wr_release_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mmu_to_qmu_rd_release_cnt",
-        ETM_QMU_MMU_TO_QMU_RD_RELEASE_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2817,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_mmu_to_qmu_rd_release_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "observe_qnum_set",
-        ETM_QMU_OBSERVE_QNUM_SETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2820,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_observe_qnum_set_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_q_pkt_received",
-        ETM_QMU_SPEC_Q_PKT_RECEIVEDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2821,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_q_pkt_received_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_q_pkt_dropped",
-        ETM_QMU_SPEC_Q_PKT_DROPPEDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2822,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_q_pkt_dropped_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_q_pkt_scheduled",
-        ETM_QMU_SPEC_Q_PKT_SCHEDULEDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2823,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_q_pkt_scheduled_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_q_wr_cmd_sent",
-        ETM_QMU_SPEC_Q_WR_CMD_SENTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2824,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_q_wr_cmd_sent_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_q_rd_cmd_sent",
-        ETM_QMU_SPEC_Q_RD_CMD_SENTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2825,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_q_rd_cmd_sent_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_q_pkt_enq",
-        ETM_QMU_SPEC_Q_PKT_ENQr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2826,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_q_pkt_enq_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_q_pkt_deq",
-        ETM_QMU_SPEC_Q_PKT_DEQr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2827,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_q_pkt_deq_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_q_crdt_uncon_received",
-        ETM_QMU_SPEC_Q_CRDT_UNCON_RECEIVEDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2828,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_q_crdt_uncon_received_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_q_crdt_cong_received",
-        ETM_QMU_SPEC_Q_CRDT_CONG_RECEIVEDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2829,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_q_crdt_cong_received_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_q_crs_normal_cnt",
-        ETM_QMU_SPEC_Q_CRS_NORMAL_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x282a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_q_crs_normal_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_q_crs_off_cnt",
-        ETM_QMU_SPEC_Q_CRS_OFF_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x282b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_q_crs_off_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "observe_batch_set",
-        ETM_QMU_OBSERVE_BATCH_SETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x282c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_observe_batch_set_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_bat_pkt_received",
-        ETM_QMU_SPEC_BAT_PKT_RECEIVEDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x282d,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_bat_pkt_received_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_bat_pkt_dropped",
-        ETM_QMU_SPEC_BAT_PKT_DROPPEDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x282e,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_bat_pkt_dropped_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_bat_blk_scheduled",
-        ETM_QMU_SPEC_BAT_BLK_SCHEDULEDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x282f,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_bat_blk_scheduled_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_bat_wr_cmd_sent",
-        ETM_QMU_SPEC_BAT_WR_CMD_SENTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2830,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_bat_wr_cmd_sent_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_bat_rd_cmd_sent",
-        ETM_QMU_SPEC_BAT_RD_CMD_SENTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2831,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_bat_rd_cmd_sent_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_bat_pkt_enq",
-        ETM_QMU_SPEC_BAT_PKT_ENQr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2832,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_bat_pkt_enq_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_bat_pkt_deq",
-        ETM_QMU_SPEC_BAT_PKT_DEQr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2833,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_bat_pkt_deq_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_bat_crdt_uncon_received",
-        ETM_QMU_SPEC_BAT_CRDT_UNCON_RECEIVEDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2834,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_bat_crdt_uncon_received_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_bat_crdt_cong_received",
-        ETM_QMU_SPEC_BAT_CRDT_CONG_RECEIVEDr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2835,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_bat_crdt_cong_received_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_bat_crs_normal_cnt",
-        ETM_QMU_SPEC_BAT_CRS_NORMAL_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2836,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_bat_crs_normal_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_bat_crs_off_cnt",
-        ETM_QMU_SPEC_BAT_CRS_OFF_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2837,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_bat_crs_off_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "bcntm_ovfl_qnum_get",
-        ETM_QMU_BCNTM_OVFL_QNUM_GETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2844,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_bcntm_ovfl_qnum_get_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crbal_a_ovf_qnum_get",
-        ETM_QMU_CRBAL_A_OVF_QNUM_GETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2845,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_crbal_a_ovf_qnum_get_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crbal_b_ovf_qnum_get",
-        ETM_QMU_CRBAL_B_OVF_QNUM_GETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2846,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_crbal_b_ovf_qnum_get_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "crbal_drop_qnum_get",
-        ETM_QMU_CRBAL_DROP_QNUM_GETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2847,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_crbal_drop_qnum_get_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "deq_flg_report_cnt",
-        ETM_QMU_DEQ_FLG_REPORT_CNTr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2848,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_deq_flg_report_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_q_crs_get",
-        ETM_QMU_SPEC_Q_CRS_GETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x2849,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_q_crs_get_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_q_crs_in_get",
-        ETM_QMU_SPEC_Q_CRS_IN_GETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x284a,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_q_crs_in_get_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spec_q_crs_flg_csol_get",
-        ETM_QMU_SPEC_Q_CRS_FLG_CSOL_GETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x284b,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_spec_q_crs_flg_csol_get_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ept_sch_qnum_get",
-        ETM_QMU_EPT_SCH_QNUM_GETr,
-        ETM,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        0x284c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_etm_qmu_ept_sch_qnum_get_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pcie_ddr_switch",
-        CFG_PCIE_PCIE_DDR_SWITCHr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_pcie_ddr_switch_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "user0_int_en",
-        CFG_PCIE_USER0_INT_ENr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_user0_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "user0_int_mask",
-        CFG_PCIE_USER0_INT_MASKr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_user0_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "user0_int_status",
-        CFG_PCIE_USER0_INT_STATUSr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x00c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_user0_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "user1_int_en",
-        CFG_PCIE_USER1_INT_ENr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_user1_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "user1_int_mask",
-        CFG_PCIE_USER1_INT_MASKr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_user1_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "user1_int_status",
-        CFG_PCIE_USER1_INT_STATUSr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_user1_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "user2_int_en",
-        CFG_PCIE_USER2_INT_ENr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x01c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_user2_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "user2_int_mask",
-        CFG_PCIE_USER2_INT_MASKr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_user2_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "user2_int_status",
-        CFG_PCIE_USER2_INT_STATUSr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_user2_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ecc_1b_int_en",
-        CFG_PCIE_ECC_1B_INT_ENr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_ecc_1b_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ecc_1b_int_mask",
-        CFG_PCIE_ECC_1B_INT_MASKr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x02c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_ecc_1b_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ecc_1b_int_status",
-        CFG_PCIE_ECC_1B_INT_STATUSr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_ecc_1b_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ecc_2b_int_en",
-        CFG_PCIE_ECC_2B_INT_ENr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_ecc_2b_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ecc_2b_int_mask",
-        CFG_PCIE_ECC_2B_INT_MASKr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_ecc_2b_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ecc_2b_int_status",
-        CFG_PCIE_ECC_2B_INT_STATUSr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x03c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_ecc_2b_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_int_status",
-        CFG_PCIE_CFG_INT_STATUSr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_cfg_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "i_core_to_cntl",
-        CFG_PCIE_I_CORE_TO_CNTLr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_i_core_to_cntl_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_in_low",
-        CFG_PCIE_TEST_IN_LOWr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_in_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_in_high",
-        CFG_PCIE_TEST_IN_HIGHr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x04c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_in_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "local_interrupt_out",
-        CFG_PCIE_LOCAL_INTERRUPT_OUTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_local_interrupt_out_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pl_ltssm",
-        CFG_PCIE_PL_LTSSMr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_pl_ltssm_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out0",
-        CFG_PCIE_TEST_OUT0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out1",
-        CFG_PCIE_TEST_OUT1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x05c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out2",
-        CFG_PCIE_TEST_OUT2r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out3",
-        CFG_PCIE_TEST_OUT3r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out4",
-        CFG_PCIE_TEST_OUT4r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out5",
-        CFG_PCIE_TEST_OUT5r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x06c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out6",
-        CFG_PCIE_TEST_OUT6r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x070,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out7",
-        CFG_PCIE_TEST_OUT7r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x074,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sync_o_core_status",
-        CFG_PCIE_SYNC_O_CORE_STATUSr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x078,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_sync_o_core_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sync_o_alert_dbe",
-        CFG_PCIE_SYNC_O_ALERT_DBEr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x07c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_sync_o_alert_dbe_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sync_o_alert_sbe",
-        CFG_PCIE_SYNC_O_ALERT_SBEr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_sync_o_alert_sbe_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sync_o_link_loopback_en",
-        CFG_PCIE_SYNC_O_LINK_LOOPBACK_ENr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_sync_o_link_loopback_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sync_o_local_fs_lf_valid",
-        CFG_PCIE_SYNC_O_LOCAL_FS_LF_VALIDr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_sync_o_local_fs_lf_valid_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sync_o_rx_idle_detect",
-        CFG_PCIE_SYNC_O_RX_IDLE_DETECTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x08c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_sync_o_rx_idle_detect_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sync_o_rx_rdy",
-        CFG_PCIE_SYNC_O_RX_RDYr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_sync_o_rx_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sync_o_tx_rdy",
-        CFG_PCIE_SYNC_O_TX_RDYr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_sync_o_tx_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pcie_link_up_cnt",
-        CFG_PCIE_PCIE_LINK_UP_CNTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x098,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_pcie_link_up_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out_pcie0",
-        CFG_PCIE_TEST_OUT_PCIE0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x09c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out_pcie0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out_pcie1",
-        CFG_PCIE_TEST_OUT_PCIE1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out_pcie1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out_pcie2",
-        CFG_PCIE_TEST_OUT_PCIE2r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out_pcie2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out_pcie3",
-        CFG_PCIE_TEST_OUT_PCIE3r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out_pcie3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out_pcie4",
-        CFG_PCIE_TEST_OUT_PCIE4r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out_pcie4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out_pcie5",
-        CFG_PCIE_TEST_OUT_PCIE5r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out_pcie5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out_pcie6",
-        CFG_PCIE_TEST_OUT_PCIE6r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out_pcie6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out_pcie7",
-        CFG_PCIE_TEST_OUT_PCIE7r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out_pcie7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out_pcie8",
-        CFG_PCIE_TEST_OUT_PCIE8r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out_pcie8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out_pcie9",
-        CFG_PCIE_TEST_OUT_PCIE9r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out_pcie9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out_pcie10",
-        CFG_PCIE_TEST_OUT_PCIE10r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out_pcie10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out_pcie11",
-        CFG_PCIE_TEST_OUT_PCIE11r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out_pcie11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out_pcie12",
-        CFG_PCIE_TEST_OUT_PCIE12r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out_pcie12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out_pcie13",
-        CFG_PCIE_TEST_OUT_PCIE13r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out_pcie13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out_pcie14",
-        CFG_PCIE_TEST_OUT_PCIE14r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out_pcie14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_out_pcie15",
-        CFG_PCIE_TEST_OUT_PCIE15r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_test_out_pcie15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_repeat_en",
-        CFG_PCIE_INT_REPEAT_ENr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_int_repeat_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_awid_axi_mst",
-        CFG_PCIE_DBG_AWID_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x400,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_awid_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_awaddr_axi_mst0",
-        CFG_PCIE_DBG_AWADDR_AXI_MST0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x404,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_awaddr_axi_mst0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_awaddr_axi_mst1",
-        CFG_PCIE_DBG_AWADDR_AXI_MST1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x408,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_awaddr_axi_mst1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_awlen_axi_mst",
-        CFG_PCIE_DBG_AWLEN_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x40c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_awlen_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_awsize_axi_mst",
-        CFG_PCIE_DBG_AWSIZE_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x410,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_awsize_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_awburst_axi_mst",
-        CFG_PCIE_DBG_AWBURST_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x414,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_awburst_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_awlock_axi_mst",
-        CFG_PCIE_DBG_AWLOCK_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x418,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_awlock_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_awcache_axi_mst",
-        CFG_PCIE_DBG_AWCACHE_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x41c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_awcache_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_awprot_axi_mst",
-        CFG_PCIE_DBG_AWPROT_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x420,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_awprot_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_wid_axi_mst",
-        CFG_PCIE_DBG_WID_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x424,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_wid_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_wdata_axi_mst0",
-        CFG_PCIE_DBG_WDATA_AXI_MST0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x428,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_wdata_axi_mst0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_wdata_axi_mst1",
-        CFG_PCIE_DBG_WDATA_AXI_MST1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x42c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_wdata_axi_mst1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_wdata_axi_mst2",
-        CFG_PCIE_DBG_WDATA_AXI_MST2r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x430,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_wdata_axi_mst2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_wdata_axi_mst3",
-        CFG_PCIE_DBG_WDATA_AXI_MST3r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x434,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_wdata_axi_mst3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_wstrb_axi_mst",
-        CFG_PCIE_DBG_WSTRB_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x438,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_wstrb_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_wlast_axi_mst",
-        CFG_PCIE_DBG_WLAST_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x43c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_wlast_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_arid_axi_mst",
-        CFG_PCIE_DBG_ARID_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x440,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_arid_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_araddr_axi_mst0",
-        CFG_PCIE_DBG_ARADDR_AXI_MST0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x444,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_araddr_axi_mst0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_araddr_axi_mst1",
-        CFG_PCIE_DBG_ARADDR_AXI_MST1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x448,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_araddr_axi_mst1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_arlen_axi_mst",
-        CFG_PCIE_DBG_ARLEN_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x44c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_arlen_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_arsize_axi_mst",
-        CFG_PCIE_DBG_ARSIZE_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x450,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_arsize_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_arburst_axi_mst",
-        CFG_PCIE_DBG_ARBURST_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x454,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_arburst_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_arlock_axi_mst",
-        CFG_PCIE_DBG_ARLOCK_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x458,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_arlock_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_arcache_axi_mst",
-        CFG_PCIE_DBG_ARCACHE_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x45c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_arcache_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_arprot_axi_mst",
-        CFG_PCIE_DBG_ARPROT_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x460,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_arprot_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_rdata_axi_mst0",
-        CFG_PCIE_DBG_RDATA_AXI_MST0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x464,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_rdata_axi_mst0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_rdata_axi_mst1",
-        CFG_PCIE_DBG_RDATA_AXI_MST1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x468,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_rdata_axi_mst1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_rdata_axi_mst2",
-        CFG_PCIE_DBG_RDATA_AXI_MST2r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x46c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_rdata_axi_mst2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_rdata_axi_mst3",
-        CFG_PCIE_DBG_RDATA_AXI_MST3r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x470,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_rdata_axi_mst3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "axi_mst_state",
-        CFG_PCIE_AXI_MST_STATEr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x474,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_axi_mst_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "axi_cfg_state",
-        CFG_PCIE_AXI_CFG_STATEr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x478,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_axi_cfg_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "axi_slv_rd_state",
-        CFG_PCIE_AXI_SLV_RD_STATEr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x47c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_axi_slv_rd_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "axi_slv_wr_state",
-        CFG_PCIE_AXI_SLV_WR_STATEr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x480,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_axi_slv_wr_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "axim_delay_en",
-        CFG_PCIE_AXIM_DELAY_ENr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x484,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_axim_delay_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "axim_delay",
-        CFG_PCIE_AXIM_DELAYr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x488,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_axim_delay_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "axim_speed_wr",
-        CFG_PCIE_AXIM_SPEED_WRr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x48c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_axim_speed_wr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "axim_speed_rd",
-        CFG_PCIE_AXIM_SPEED_RDr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x490,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_axim_speed_rd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_awaddr_axi_slv0",
-        CFG_PCIE_DBG_AWADDR_AXI_SLV0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_awaddr_axi_slv0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_awaddr_axi_slv1",
-        CFG_PCIE_DBG_AWADDR_AXI_SLV1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_awaddr_axi_slv1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg0_wdata_axi_slv0",
-        CFG_PCIE_DBG0_WDATA_AXI_SLV0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg0_wdata_axi_slv0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg0_wdata_axi_slv1",
-        CFG_PCIE_DBG0_WDATA_AXI_SLV1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg0_wdata_axi_slv1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg0_wdata_axi_slv2",
-        CFG_PCIE_DBG0_WDATA_AXI_SLV2r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg0_wdata_axi_slv2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg0_wdata_axi_slv3",
-        CFG_PCIE_DBG0_WDATA_AXI_SLV3r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg0_wdata_axi_slv3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg1_wdata_axi_slv0",
-        CFG_PCIE_DBG1_WDATA_AXI_SLV0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg1_wdata_axi_slv0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg1_wdata_axi_slv1",
-        CFG_PCIE_DBG1_WDATA_AXI_SLV1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg1_wdata_axi_slv1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg1_wdata_axi_slv2",
-        CFG_PCIE_DBG1_WDATA_AXI_SLV2r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg1_wdata_axi_slv2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg1_wdata_axi_slv3",
-        CFG_PCIE_DBG1_WDATA_AXI_SLV3r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg1_wdata_axi_slv3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg2_wdata_axi_slv0",
-        CFG_PCIE_DBG2_WDATA_AXI_SLV0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg2_wdata_axi_slv0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg2_wdata_axi_slv1",
-        CFG_PCIE_DBG2_WDATA_AXI_SLV1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg2_wdata_axi_slv1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg2_wdata_axi_slv2",
-        CFG_PCIE_DBG2_WDATA_AXI_SLV2r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg2_wdata_axi_slv2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg2_wdata_axi_slv3",
-        CFG_PCIE_DBG2_WDATA_AXI_SLV3r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg2_wdata_axi_slv3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg3_wdata_axi_slv0",
-        CFG_PCIE_DBG3_WDATA_AXI_SLV0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg3_wdata_axi_slv0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg3_wdata_axi_slv1",
-        CFG_PCIE_DBG3_WDATA_AXI_SLV1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg3_wdata_axi_slv1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg3_wdata_axi_slv2",
-        CFG_PCIE_DBG3_WDATA_AXI_SLV2r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x500,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg3_wdata_axi_slv2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg3_wdata_axi_slv3",
-        CFG_PCIE_DBG3_WDATA_AXI_SLV3r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x504,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg3_wdata_axi_slv3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg4_wdata_axi_slv0",
-        CFG_PCIE_DBG4_WDATA_AXI_SLV0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x508,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg4_wdata_axi_slv0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg4_wdata_axi_slv1",
-        CFG_PCIE_DBG4_WDATA_AXI_SLV1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x50c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg4_wdata_axi_slv1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg4_wdata_axi_slv2",
-        CFG_PCIE_DBG4_WDATA_AXI_SLV2r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x510,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg4_wdata_axi_slv2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg4_wdata_axi_slv3",
-        CFG_PCIE_DBG4_WDATA_AXI_SLV3r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x514,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg4_wdata_axi_slv3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg5_wdata_axi_slv0",
-        CFG_PCIE_DBG5_WDATA_AXI_SLV0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x518,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg5_wdata_axi_slv0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg5_wdata_axi_slv1",
-        CFG_PCIE_DBG5_WDATA_AXI_SLV1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x51c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg5_wdata_axi_slv1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg5_wdata_axi_slv2",
-        CFG_PCIE_DBG5_WDATA_AXI_SLV2r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x520,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg5_wdata_axi_slv2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg5_wdata_axi_slv3",
-        CFG_PCIE_DBG5_WDATA_AXI_SLV3r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x524,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg5_wdata_axi_slv3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg6_wdata_axi_slv0",
-        CFG_PCIE_DBG6_WDATA_AXI_SLV0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x528,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg6_wdata_axi_slv0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg6_wdata_axi_slv1",
-        CFG_PCIE_DBG6_WDATA_AXI_SLV1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x52c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg6_wdata_axi_slv1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg6_wdata_axi_slv2",
-        CFG_PCIE_DBG6_WDATA_AXI_SLV2r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x530,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg6_wdata_axi_slv2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg6_wdata_axi_slv3",
-        CFG_PCIE_DBG6_WDATA_AXI_SLV3r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x534,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg6_wdata_axi_slv3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg7_wdata_axi_slv0",
-        CFG_PCIE_DBG7_WDATA_AXI_SLV0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x538,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg7_wdata_axi_slv0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg7_wdata_axi_slv1",
-        CFG_PCIE_DBG7_WDATA_AXI_SLV1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x53c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg7_wdata_axi_slv1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg7_wdata_axi_slv2",
-        CFG_PCIE_DBG7_WDATA_AXI_SLV2r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x540,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg7_wdata_axi_slv2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg7_wdata_axi_slv3",
-        CFG_PCIE_DBG7_WDATA_AXI_SLV3r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x544,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg7_wdata_axi_slv3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg8_wdata_axi_slv0",
-        CFG_PCIE_DBG8_WDATA_AXI_SLV0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x548,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg8_wdata_axi_slv0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg8_wdata_axi_slv1",
-        CFG_PCIE_DBG8_WDATA_AXI_SLV1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x54c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg8_wdata_axi_slv1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg8_wdata_axi_slv2",
-        CFG_PCIE_DBG8_WDATA_AXI_SLV2r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x550,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg8_wdata_axi_slv2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg8_wdata_axi_slv3",
-        CFG_PCIE_DBG8_WDATA_AXI_SLV3r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x554,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg8_wdata_axi_slv3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg9_wdata_axi_slv0",
-        CFG_PCIE_DBG9_WDATA_AXI_SLV0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x558,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg9_wdata_axi_slv0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg9_wdata_axi_slv1",
-        CFG_PCIE_DBG9_WDATA_AXI_SLV1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x55c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg9_wdata_axi_slv1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg9_wdata_axi_slv2",
-        CFG_PCIE_DBG9_WDATA_AXI_SLV2r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x560,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg9_wdata_axi_slv2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg9_wdata_axi_slv3",
-        CFG_PCIE_DBG9_WDATA_AXI_SLV3r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x564,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg9_wdata_axi_slv3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_awlen_axi_slv",
-        CFG_PCIE_DBG_AWLEN_AXI_SLVr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x568,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_awlen_axi_slv_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_wlast_axi_slv",
-        CFG_PCIE_DBG_WLAST_AXI_SLVr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x56c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_wlast_axi_slv_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_araddr_axi_slv0",
-        CFG_PCIE_DBG_ARADDR_AXI_SLV0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x580,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_araddr_axi_slv0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_araddr_axi_slv1",
-        CFG_PCIE_DBG_ARADDR_AXI_SLV1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x584,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_araddr_axi_slv1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg0_rdata_axi_slv0",
-        CFG_PCIE_DBG0_RDATA_AXI_SLV0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x588,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg0_rdata_axi_slv0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg0_rdata_axi_slv1",
-        CFG_PCIE_DBG0_RDATA_AXI_SLV1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x58c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg0_rdata_axi_slv1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg0_rdata_axi_slv2",
-        CFG_PCIE_DBG0_RDATA_AXI_SLV2r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x590,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg0_rdata_axi_slv2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg0_rdata_axi_slv3",
-        CFG_PCIE_DBG0_RDATA_AXI_SLV3r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x594,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg0_rdata_axi_slv3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg1_rdata_axi_slv0",
-        CFG_PCIE_DBG1_RDATA_AXI_SLV0r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x598,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg1_rdata_axi_slv0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg1_rdata_axi_slv1",
-        CFG_PCIE_DBG1_RDATA_AXI_SLV1r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x59c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg1_rdata_axi_slv1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg1_rdata_axi_slv2",
-        CFG_PCIE_DBG1_RDATA_AXI_SLV2r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x5a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg1_rdata_axi_slv2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg1_rdata_axi_slv3",
-        CFG_PCIE_DBG1_RDATA_AXI_SLV3r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x5a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg1_rdata_axi_slv3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_rlast_axi_slv",
-        CFG_PCIE_DBG_RLAST_AXI_SLVr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x5a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_pcie_dbg_rlast_axi_slv_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_enable",
-        CFG_DMA_DMA_ENABLEr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_enable_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "up_req",
-        CFG_DMA_UP_REQr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_up_req_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_up_current_state",
-        CFG_DMA_DMA_UP_CURRENT_STATEr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_up_current_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_up_req_ack",
-        CFG_DMA_DMA_UP_REQ_ACKr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x00c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_up_req_ack_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_done_latch",
-        CFG_DMA_DMA_DONE_LATCHr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_done_latch_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_up_cpu_addr_low32",
-        CFG_DMA_DMA_UP_CPU_ADDR_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_up_cpu_addr_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_up_cpu_addr_high32",
-        CFG_DMA_DMA_UP_CPU_ADDR_HIGH32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x01c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_up_cpu_addr_high32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_up_se_addr",
-        CFG_DMA_DMA_UP_SE_ADDRr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_up_se_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_done_int",
-        CFG_DMA_DMA_DONE_INTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_done_int_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sp_cfg",
-        CFG_DMA_SP_CFGr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_sp_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_ing",
-        CFG_DMA_DMA_INGr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x03c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_ing_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rd_timeout_thresh",
-        CFG_DMA_RD_TIMEOUT_THRESHr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_rd_timeout_thresh_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_tab_sta_up_fifo_gap",
-        CFG_DMA_DMA_TAB_STA_UP_FIFO_GAPr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_tab_sta_up_fifo_gap_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_mac_tim",
-        CFG_DMA_CFG_MAC_TIMr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_cfg_mac_tim_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_mac_num",
-        CFG_DMA_CFG_MAC_NUMr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x04c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_cfg_mac_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "init_bd_addr",
-        CFG_DMA_INIT_BD_ADDRr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_init_bd_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mac_up_bd_addr1_low32",
-        CFG_DMA_MAC_UP_BD_ADDR1_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_mac_up_bd_addr1_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mac_up_bd_addr1_high32",
-        CFG_DMA_MAC_UP_BD_ADDR1_HIGH32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_mac_up_bd_addr1_high32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mac_up_bd_addr2_low32",
-        CFG_DMA_MAC_UP_BD_ADDR2_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x05c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_mac_up_bd_addr2_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mac_up_bd_addr2_high32",
-        CFG_DMA_MAC_UP_BD_ADDR2_HIGH32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_mac_up_bd_addr2_high32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_mac_max_num",
-        CFG_DMA_CFG_MAC_MAX_NUMr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_cfg_mac_max_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_wbuf_ff_empty",
-        CFG_DMA_DMA_WBUF_FF_EMPTYr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_wbuf_ff_empty_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_wbuf_state",
-        CFG_DMA_DMA_WBUF_STATEr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x06c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_wbuf_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_mac_bd_addr_low32",
-        CFG_DMA_DMA_MAC_BD_ADDR_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x070,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_mac_bd_addr_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_mac_bd_addr_high32",
-        CFG_DMA_DMA_MAC_BD_ADDR_HIGH32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x074,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_mac_bd_addr_high32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mac_up_enable",
-        CFG_DMA_MAC_UP_ENABLEr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x078,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_mac_up_enable_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mac_endian",
-        CFG_DMA_MAC_ENDIANr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x07c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_mac_endian_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "up_endian",
-        CFG_DMA_UP_ENDIANr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_up_endian_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_up_rd_cnt_latch",
-        CFG_DMA_DMA_UP_RD_CNT_LATCHr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_up_rd_cnt_latch_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_up_rcv_cnt_latch",
-        CFG_DMA_DMA_UP_RCV_CNT_LATCHr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_up_rcv_cnt_latch_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_up_cnt_latch",
-        CFG_DMA_DMA_UP_CNT_LATCHr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x08c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_up_cnt_latch_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_bd_pulse",
-        CFG_DMA_CPU_RD_BD_PULSEr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_cpu_rd_bd_pulse_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_bd_threshold",
-        CFG_DMA_CPU_BD_THRESHOLDr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_cpu_bd_threshold_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_bd_used_cnt",
-        CFG_DMA_CPU_BD_USED_CNTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x098,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_cpu_bd_used_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_up_rcv_status",
-        CFG_DMA_DMA_UP_RCV_STATUSr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x09c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_up_rcv_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "slv_rid_err_en",
-        CFG_DMA_SLV_RID_ERR_ENr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_slv_rid_err_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "slv_rresp_err_en",
-        CFG_DMA_SLV_RRESP_ERR_ENr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_slv_rresp_err_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_rdbk_ff_full",
-        CFG_DMA_SE_RDBK_FF_FULLr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_se_rdbk_ff_full_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_up_data_count",
-        CFG_DMA_DMA_UP_DATA_COUNTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_up_data_count_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_mwr_fifo_afull_gap",
-        CFG_DMA_DMA_MWR_FIFO_AFULL_GAPr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0xb0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_mwr_fifo_afull_gap_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_info_fifo_afull_gap",
-        CFG_DMA_DMA_INFO_FIFO_AFULL_GAPr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0xb4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_info_fifo_afull_gap_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_rd_timeout_set",
-        CFG_DMA_DMA_RD_TIMEOUT_SETr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_rd_timeout_set_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_bd_dat_err_en",
-        CFG_DMA_DMA_BD_DAT_ERR_ENr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_bd_dat_err_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_repeat_cnt",
-        CFG_DMA_DMA_REPEAT_CNTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_repeat_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_rd_timeout_en",
-        CFG_DMA_DMA_RD_TIMEOUT_ENr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_rd_timeout_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_repeat_read",
-        CFG_DMA_DMA_REPEAT_READr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_repeat_read_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_repeat_read_en",
-        CFG_DMA_DMA_REPEAT_READ_ENr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_repeat_read_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "bd_ctl_state",
-        CFG_DMA_BD_CTL_STATEr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_bd_ctl_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_done_int_cnt_wr",
-        CFG_DMA_DMA_DONE_INT_CNT_WRr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_done_int_cnt_wr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_done_int_cnt_mac",
-        CFG_DMA_DMA_DONE_INT_CNT_MACr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_done_int_cnt_mac_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "current_mac_num",
-        CFG_DMA_CURRENT_MAC_NUMr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_current_mac_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_mac_afifo_afull",
-        CFG_DMA_CFG_MAC_AFIFO_AFULLr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_cfg_mac_afifo_afull_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_mac_ff_full",
-        CFG_DMA_DMA_MAC_FF_FULLr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_dma_dma_mac_ff_full_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "user_axi_mst",
-        CFG_DMA_USER_AXI_MSTr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0100,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_cfg_dma_user_axi_mst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sbus_state",
-        CFG_CSR_SBUS_STATEr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_sbus_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_en",
-        CFG_CSR_MST_DEBUG_ENr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sbus_command_sel",
-        CFG_CSR_SBUS_COMMAND_SELr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_sbus_command_sel_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "soc_rd_time_out_thresh",
-        CFG_CSR_SOC_RD_TIME_OUT_THRESHr,
-        CFG,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x02c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_soc_rd_time_out_thresh_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "big_little_byte_order",
-        CFG_CSR_BIG_LITTLE_BYTE_ORDERr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_big_little_byte_order_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ecc_bypass_read",
-        CFG_CSR_ECC_BYPASS_READr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_ecc_bypass_read_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ahb_async_wr_fifo_afull_gap",
-        CFG_CSR_AHB_ASYNC_WR_FIFO_AFULL_GAPr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_ahb_async_wr_fifo_afull_gap_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ahb_async_rd_fifo_afull_gap",
-        CFG_CSR_AHB_ASYNC_RD_FIFO_AFULL_GAPr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x03c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_ahb_async_rd_fifo_afull_gap_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ahb_async_cpl_fifo_afull_gap",
-        CFG_CSR_AHB_ASYNC_CPL_FIFO_AFULL_GAPr,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_ahb_async_cpl_fifo_afull_gap_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data0_high26",
-        CFG_CSR_MST_DEBUG_DATA0_HIGH26r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data0_high26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data0_low32",
-        CFG_CSR_MST_DEBUG_DATA0_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data0_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data1_high26",
-        CFG_CSR_MST_DEBUG_DATA1_HIGH26r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data1_high26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data1_low32",
-        CFG_CSR_MST_DEBUG_DATA1_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x08c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data1_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data2_high26",
-        CFG_CSR_MST_DEBUG_DATA2_HIGH26r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data2_high26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data2_low32",
-        CFG_CSR_MST_DEBUG_DATA2_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data2_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data3_high26",
-        CFG_CSR_MST_DEBUG_DATA3_HIGH26r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x098,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data3_high26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data3_low32",
-        CFG_CSR_MST_DEBUG_DATA3_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x09c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data3_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data4_high26",
-        CFG_CSR_MST_DEBUG_DATA4_HIGH26r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data4_high26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data4_low32",
-        CFG_CSR_MST_DEBUG_DATA4_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data4_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data5_high26",
-        CFG_CSR_MST_DEBUG_DATA5_HIGH26r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data5_high26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data5_low32",
-        CFG_CSR_MST_DEBUG_DATA5_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data5_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data6_high26",
-        CFG_CSR_MST_DEBUG_DATA6_HIGH26r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data6_high26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data6_low32",
-        CFG_CSR_MST_DEBUG_DATA6_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data6_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data7_high26",
-        CFG_CSR_MST_DEBUG_DATA7_HIGH26r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data7_high26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data7_low32",
-        CFG_CSR_MST_DEBUG_DATA7_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data7_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data8_high26",
-        CFG_CSR_MST_DEBUG_DATA8_HIGH26r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data8_high26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data8_low32",
-        CFG_CSR_MST_DEBUG_DATA8_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data8_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data9_high26",
-        CFG_CSR_MST_DEBUG_DATA9_HIGH26r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data9_high26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data9_low32",
-        CFG_CSR_MST_DEBUG_DATA9_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data9_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data10_high26",
-        CFG_CSR_MST_DEBUG_DATA10_HIGH26r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data10_high26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data10_low32",
-        CFG_CSR_MST_DEBUG_DATA10_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data10_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data11_high26",
-        CFG_CSR_MST_DEBUG_DATA11_HIGH26r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data11_high26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data11_low32",
-        CFG_CSR_MST_DEBUG_DATA11_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data11_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data12_high26",
-        CFG_CSR_MST_DEBUG_DATA12_HIGH26r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data12_high26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data12_low32",
-        CFG_CSR_MST_DEBUG_DATA12_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data12_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data13_high26",
-        CFG_CSR_MST_DEBUG_DATA13_HIGH26r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data13_high26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data13_low32",
-        CFG_CSR_MST_DEBUG_DATA13_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data13_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data14_high26",
-        CFG_CSR_MST_DEBUG_DATA14_HIGH26r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data14_high26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data14_low32",
-        CFG_CSR_MST_DEBUG_DATA14_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data14_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data15_high26",
-        CFG_CSR_MST_DEBUG_DATA15_HIGH26r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data15_high26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mst_debug_data15_low32",
-        CFG_CSR_MST_DEBUG_DATA15_LOW32r,
-        CFG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_cfg_csr_mst_debug_data15_low32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_access_states",
-        NPPU_MR_CFG_IND_ACCESS_STATESr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_ind_access_states_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_access_cmd0",
-        NPPU_MR_CFG_IND_ACCESS_CMD0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_nppu_mr_cfg_ind_access_cmd0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_access_data0",
-        NPPU_MR_CFG_IND_ACCESS_DATA0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_ind_access_data0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_access_data1",
-        NPPU_MR_CFG_IND_ACCESS_DATA1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_ind_access_data1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_access_cmd1",
-        NPPU_MR_CFG_IND_ACCESS_CMD1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_ind_access_cmd1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_init_done",
-        NPPU_MR_CFG_MR_INIT_DONEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_init_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_mode_reg",
-        NPPU_MR_CFG_CNT_MODE_REGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_mr_cfg_cnt_mode_reg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ecc_bypass_read",
-        NPPU_MR_CFG_CFG_ECC_BYPASS_READr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_cfg_ecc_bypass_read_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_rep_mod",
-        NPPU_MR_CFG_CFG_REP_MODr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_cfg_rep_mod_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "block_ptr_fifo_aful_th",
-        NPPU_MR_CFG_BLOCK_PTR_FIFO_AFUL_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x002c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_mr_cfg_block_ptr_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pre_rcv_ptr_fifo_aful_th",
-        NPPU_MR_CFG_PRE_RCV_PTR_FIFO_AFUL_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_mr_cfg_pre_rcv_ptr_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mgid_fifo_aful_th",
-        NPPU_MR_CFG_MGID_FIFO_AFUL_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_mr_cfg_mgid_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rep_cmd_fifo_aful_th",
-        NPPU_MR_CFG_REP_CMD_FIFO_AFUL_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_mr_cfg_rep_cmd_fifo_aful_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_int_mask_1",
-        NPPU_MR_CFG_MR_INT_MASK_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x00c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        20,
-        g_nppu_mr_cfg_mr_int_mask_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_int_mask_2",
-        NPPU_MR_CFG_MR_INT_MASK_2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x00c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        20,
-        g_nppu_mr_cfg_mr_int_mask_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_int_mask_3",
-        NPPU_MR_CFG_MR_INT_MASK_3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x00c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        20,
-        g_nppu_mr_cfg_mr_int_mask_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_int_mask_4",
-        NPPU_MR_CFG_MR_INT_MASK_4r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x00cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        25,
-        g_nppu_mr_cfg_mr_int_mask_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_states_1",
-        NPPU_MR_CFG_MR_STATES_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        20,
-        g_nppu_mr_cfg_mr_states_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_states_2",
-        NPPU_MR_CFG_MR_STATES_2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        20,
-        g_nppu_mr_cfg_mr_states_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_states_3",
-        NPPU_MR_CFG_MR_STATES_3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        20,
-        g_nppu_mr_cfg_mr_states_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_states_4",
-        NPPU_MR_CFG_MR_STATES_4r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        25,
-        g_nppu_mr_cfg_mr_states_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_states_5",
-        NPPU_MR_CFG_MR_STATES_5r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        21,
-        g_nppu_mr_cfg_mr_states_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_states_6",
-        NPPU_MR_CFG_MR_STATES_6r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        20,
-        g_nppu_mr_cfg_mr_states_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_states_7",
-        NPPU_MR_CFG_MR_STATES_7r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        22,
-        g_nppu_mr_cfg_mr_states_7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_states_8",
-        NPPU_MR_CFG_MR_STATES_8r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x005c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_states_8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_sop_in_cnt",
-        NPPU_MR_CFG_MR_SOP_IN_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_sop_in_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_eop_in_cnt",
-        NPPU_MR_CFG_MR_EOP_IN_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_eop_in_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_sop_out_cnt",
-        NPPU_MR_CFG_MR_SOP_OUT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_sop_out_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_eop_out_cnt",
-        NPPU_MR_CFG_MR_EOP_OUT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x006c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_eop_out_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos0_in_cnt",
-        NPPU_MR_CFG_MR_COS0_IN_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0070,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos0_in_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos1_in_cnt",
-        NPPU_MR_CFG_MR_COS1_IN_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0074,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos1_in_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos2_in_cnt",
-        NPPU_MR_CFG_MR_COS2_IN_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0078,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos2_in_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos3_in_cnt",
-        NPPU_MR_CFG_MR_COS3_IN_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x007c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos3_in_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos0_out_cnt",
-        NPPU_MR_CFG_MR_COS0_OUT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos0_out_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos1_out_cnt",
-        NPPU_MR_CFG_MR_COS1_OUT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos1_out_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos2_out_cnt",
-        NPPU_MR_CFG_MR_COS2_OUT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos2_out_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos3_out_cnt",
-        NPPU_MR_CFG_MR_COS3_OUT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x008c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos3_out_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_err_in_cnt",
-        NPPU_MR_CFG_MR_ERR_IN_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_err_in_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos0_sop_in_cnt",
-        NPPU_MR_CFG_MR_COS0_SOP_IN_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0140,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos0_sop_in_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos0_eop_in_cnt",
-        NPPU_MR_CFG_MR_COS0_EOP_IN_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0144,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos0_eop_in_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos1_sop_in_cnt",
-        NPPU_MR_CFG_MR_COS1_SOP_IN_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0148,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos1_sop_in_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos1_eop_in_cnt",
-        NPPU_MR_CFG_MR_COS1_EOP_IN_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x014c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos1_eop_in_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos2_sop_in_cnt",
-        NPPU_MR_CFG_MR_COS2_SOP_IN_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0150,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos2_sop_in_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos2_eop_in_cnt",
-        NPPU_MR_CFG_MR_COS2_EOP_IN_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0154,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos2_eop_in_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos3_sop_in_cnt",
-        NPPU_MR_CFG_MR_COS3_SOP_IN_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0158,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos3_sop_in_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos3_eop_in_cnt",
-        NPPU_MR_CFG_MR_COS3_EOP_IN_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x015c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos3_eop_in_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos0_in_err_cnt",
-        NPPU_MR_CFG_MR_COS0_IN_ERR_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0160,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos0_in_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos1_in_err_cnt",
-        NPPU_MR_CFG_MR_COS1_IN_ERR_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0164,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos1_in_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos2_in_err_cnt",
-        NPPU_MR_CFG_MR_COS2_IN_ERR_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0168,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos2_in_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos3_in_err_cnt",
-        NPPU_MR_CFG_MR_COS3_IN_ERR_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x016c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos3_in_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos0_sop_out_cnt",
-        NPPU_MR_CFG_MR_COS0_SOP_OUT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0170,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos0_sop_out_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos0_eop_out_cnt",
-        NPPU_MR_CFG_MR_COS0_EOP_OUT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0174,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos0_eop_out_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos1_sop_out_cnt",
-        NPPU_MR_CFG_MR_COS1_SOP_OUT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0178,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos1_sop_out_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos1_eop_out_cnt",
-        NPPU_MR_CFG_MR_COS1_EOP_OUT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x017c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos1_eop_out_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos2_sop_out_cnt",
-        NPPU_MR_CFG_MR_COS2_SOP_OUT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0180,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos2_sop_out_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos2_eop_out_cnt",
-        NPPU_MR_CFG_MR_COS2_EOP_OUT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0184,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos2_eop_out_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos3_sop_out_cnt",
-        NPPU_MR_CFG_MR_COS3_SOP_OUT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0188,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos3_sop_out_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_cos3_eop_out_cnt",
-        NPPU_MR_CFG_MR_COS3_EOP_OUT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x018c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_cos3_eop_out_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_mlt_unvld_cnt",
-        NPPU_MR_CFG_MR_MLT_UNVLD_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0190,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_mlt_unvld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_sop_eop_match_cfg",
-        NPPU_MR_CFG_MR_SOP_EOP_MATCH_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0100,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_mr_cfg_mr_sop_eop_match_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mr_mlt_unvld_mgid",
-        NPPU_MR_CFG_MR_MLT_UNVLD_MGIDr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0108,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_mr_cfg_mr_mlt_unvld_mgid_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isch_fifo_th_1",
-        NPPU_PKTRX_CFG_ISCH_FIFO_TH_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0078,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pktrx_cfg_isch_fifo_th_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isch_fifo_th_2",
-        NPPU_PKTRX_CFG_ISCH_FIFO_TH_2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x007c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pktrx_cfg_isch_fifo_th_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isch_fifo_th_3",
-        NPPU_PKTRX_CFG_ISCH_FIFO_TH_3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pktrx_cfg_isch_fifo_th_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isch_fifo_th_4",
-        NPPU_PKTRX_CFG_ISCH_FIFO_TH_4r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pktrx_cfg_isch_fifo_th_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isch_cfg_0",
-        NPPU_PKTRX_CFG_ISCH_CFG_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_isch_cfg_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hdu_ex_tpid_0",
-        NPPU_PKTRX_CFG_HDU_EX_TPID_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_pktrx_cfg_hdu_ex_tpid_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hdu_ex_tpid_1",
-        NPPU_PKTRX_CFG_HDU_EX_TPID_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_pktrx_cfg_hdu_ex_tpid_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hdu_int_tpid_0",
-        NPPU_PKTRX_CFG_HDU_INT_TPID_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0098,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_pktrx_cfg_hdu_int_tpid_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hdu_int_tpid_1",
-        NPPU_PKTRX_CFG_HDU_INT_TPID_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x009c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_pktrx_cfg_hdu_int_tpid_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hdu_hdlc_0",
-        NPPU_PKTRX_CFG_HDU_HDLC_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_pktrx_cfg_hdu_hdlc_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hdu_hdlc_1",
-        NPPU_PKTRX_CFG_HDU_HDLC_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_pktrx_cfg_hdu_hdlc_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hdu_udf_l3type_0",
-        NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_pktrx_cfg_hdu_udf_l3type_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hdu_udf_l3type_1",
-        NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_pktrx_cfg_hdu_udf_l3type_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hdu_udf_l3type_2",
-        NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_pktrx_cfg_hdu_udf_l3type_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hdu_udf_l3type_3",
-        NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_pktrx_cfg_hdu_udf_l3type_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hdu_udf_l4type_0",
-        NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pktrx_cfg_hdu_udf_l4type_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hdu_udf_l4type_1",
-        NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pktrx_cfg_hdu_udf_l4type_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hdu_udf_l4type_2",
-        NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_nppu_pktrx_cfg_hdu_udf_l4type_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "slot_no_cfg",
-        NPPU_PKTRX_CFG_SLOT_NO_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_slot_no_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_int_en_0",
-        NPPU_PKTRX_CFG_PKTRX_INT_EN_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0114,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_nppu_pktrx_cfg_pktrx_int_en_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_int_en_1",
-        NPPU_PKTRX_CFG_PKTRX_INT_EN_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0118,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pktrx_cfg_pktrx_int_en_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_int_mask_0",
-        NPPU_PKTRX_CFG_PKTRX_INT_MASK_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x011c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_nppu_pktrx_cfg_pktrx_int_mask_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_int_mask_1",
-        NPPU_PKTRX_CFG_PKTRX_INT_MASK_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0120,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pktrx_cfg_pktrx_int_mask_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_int_status",
-        NPPU_PKTRX_CFG_PKTRX_INT_STATUSr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0124,
-        (32/8),
-        0,
-        35 + 1,
-        0,
-        4,
-        1,
-        g_nppu_pktrx_cfg_pktrx_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_port_rdy0",
-        NPPU_PKTRX_CFG_PKTRX_PORT_RDY0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_pktrx_cfg_pktrx_port_rdy0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_lif0_pfc_rdy0",
-        NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_lif0_pfc_rdy1",
-        NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_lif0_pfc_rdy2",
-        NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_lif0_pfc_rdy3",
-        NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_lif0_pfc_rdy4",
-        NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY4r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_lif0_pfc_rdy5",
-        NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY5r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_lif0_pfc_rdy6",
-        NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY6r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_port_l2_offset_mode",
-        NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_ram_en",
-        NPPU_IDMA_CFG_INT_RAM_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_idma_cfg_int_ram_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_ram_mask",
-        NPPU_IDMA_CFG_INT_RAM_MASKr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_idma_cfg_int_ram_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_ram_status",
-        NPPU_IDMA_CFG_INT_RAM_STATUSr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_idma_cfg_int_ram_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "subsys_int_mask_flag",
-        NPPU_IDMA_CFG_SUBSYS_INT_MASK_FLAGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x180,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_idma_cfg_subsys_int_mask_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "subsys_int_unmask_flag",
-        NPPU_IDMA_CFG_SUBSYS_INT_UNMASK_FLAGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x184,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_idma_cfg_subsys_int_unmask_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_rdclr_mode",
-        NPPU_IDMA_CFG_DEBUG_CNT_RDCLR_MODEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x4f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_idma_cfg_debug_cnt_rdclr_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_ram_en0",
-        NPPU_PBU_CFG_INT_RAM_EN0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_nppu_pbu_cfg_int_ram_en0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_ram_mask0",
-        NPPU_PBU_CFG_INT_RAM_MASK0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_nppu_pbu_cfg_int_ram_mask0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_ram_status0",
-        NPPU_PBU_CFG_INT_RAM_STATUS0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_nppu_pbu_cfg_int_ram_status0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_fifo_en0",
-        NPPU_PBU_CFG_INT_FIFO_EN0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x0c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_nppu_pbu_cfg_int_fifo_en0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_fifo_en1",
-        NPPU_PBU_CFG_INT_FIFO_EN1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x0c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pbu_cfg_int_fifo_en1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_fifo_mask0",
-        NPPU_PBU_CFG_INT_FIFO_MASK0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x100,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_nppu_pbu_cfg_int_fifo_mask0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_fifo_mask1",
-        NPPU_PBU_CFG_INT_FIFO_MASK1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x104,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pbu_cfg_int_fifo_mask1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_fifo_status0",
-        NPPU_PBU_CFG_INT_FIFO_STATUS0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x140,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_nppu_pbu_cfg_int_fifo_status0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_fifo_status1",
-        NPPU_PBU_CFG_INT_FIFO_STATUS1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x144,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pbu_cfg_int_fifo_status1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "subsys_int_mask_flag",
-        NPPU_PBU_CFG_SUBSYS_INT_MASK_FLAGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x180,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_subsys_int_mask_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "subsys_int_unmask_flag",
-        NPPU_PBU_CFG_SUBSYS_INT_UNMASK_FLAGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x184,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_subsys_int_unmask_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sa_ip_en",
-        NPPU_PBU_CFG_SA_IP_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_sa_ip_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_rdclr_mode",
-        NPPU_PBU_CFG_DEBUG_CNT_RDCLR_MODEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_debug_cnt_rdclr_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fptr_fifo_aful_assert_cfg",
-        NPPU_PBU_CFG_FPTR_FIFO_AFUL_ASSERT_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x50c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_fptr_fifo_aful_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fptr_fifo_aful_negate_cfg",
-        NPPU_PBU_CFG_FPTR_FIFO_AFUL_NEGATE_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x510,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_fptr_fifo_aful_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pf_fifo_aful_assert_cfg",
-        NPPU_PBU_CFG_PF_FIFO_AFUL_ASSERT_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x514,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_pf_fifo_aful_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pf_fifo_aful_negate_cfg",
-        NPPU_PBU_CFG_PF_FIFO_AFUL_NEGATE_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x518,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_pf_fifo_aful_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pf_fifo_aept_assert_cfg",
-        NPPU_PBU_CFG_PF_FIFO_AEPT_ASSERT_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x51c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_pf_fifo_aept_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pf_fifo_aept_negate_cfg",
-        NPPU_PBU_CFG_PF_FIFO_AEPT_NEGATE_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x520,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_pf_fifo_aept_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "wb_aful_assert_cfg",
-        NPPU_PBU_CFG_WB_AFUL_ASSERT_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x524,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_wb_aful_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "wb_aful_negate_cfg",
-        NPPU_PBU_CFG_WB_AFUL_NEGATE_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x528,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_wb_aful_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_key_aful_assert_cfg",
-        NPPU_PBU_CFG_SE_KEY_AFUL_ASSERT_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x52c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_se_key_aful_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ifbrd_se_aful_assert_cfg",
-        NPPU_PBU_CFG_IFBRD_SE_AFUL_ASSERT_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x534,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_ifbrd_se_aful_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ifbrd_se_aful_negate_cfg",
-        NPPU_PBU_CFG_IFBRD_SE_AFUL_NEGATE_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x538,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_ifbrd_se_aful_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ifbrd_odma_aful_assert_cfg",
-        NPPU_PBU_CFG_IFBRD_ODMA_AFUL_ASSERT_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x53c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_ifbrd_odma_aful_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ifbrd_odma_aful_negate_cfg",
-        NPPU_PBU_CFG_IFBRD_ODMA_AFUL_NEGATE_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x540,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_ifbrd_odma_aful_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ifbrd_ppu_aful_assert_cfg",
-        NPPU_PBU_CFG_IFBRD_PPU_AFUL_ASSERT_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x544,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_ifbrd_ppu_aful_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ifbrd_ppu_aful_negate_cfg",
-        NPPU_PBU_CFG_IFBRD_PPU_AFUL_NEGATE_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x548,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_ifbrd_ppu_aful_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mc_logic_aful_assert_cfg",
-        NPPU_PBU_CFG_MC_LOGIC_AFUL_ASSERT_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x54c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_mc_logic_aful_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mc_logic_aful_negate_cfg",
-        NPPU_PBU_CFG_MC_LOGIC_AFUL_NEGATE_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x550,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_mc_logic_aful_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mc_logic_diff",
-        NPPU_PBU_CFG_MC_LOGIC_DIFFr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x5e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_mc_logic_diff_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_peak_port_cnt_clr",
-        NPPU_PBU_CFG_CFG_PEAK_PORT_CNT_CLRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x0600,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_nppu_pbu_cfg_cfg_peak_port_cnt_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "all_ftm_crdt_th",
-        NPPU_PBU_CFG_ALL_FTM_CRDT_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x0640,
-        (32/8),
-        0,
-        47 + 1,
-        0,
-        4,
-        2,
-        g_nppu_pbu_cfg_all_ftm_crdt_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "all_ftm_link_th_01",
-        NPPU_PBU_CFG_ALL_FTM_LINK_TH_01r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x700,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_pbu_cfg_all_ftm_link_th_01_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "all_ftm_link_th_23",
-        NPPU_PBU_CFG_ALL_FTM_LINK_TH_23r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x704,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_pbu_cfg_all_ftm_link_th_23_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "all_ftm_link_th_45",
-        NPPU_PBU_CFG_ALL_FTM_LINK_TH_45r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x708,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_pbu_cfg_all_ftm_link_th_45_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "all_ftm_link_th_6",
-        NPPU_PBU_CFG_ALL_FTM_LINK_TH_6r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x70c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_all_ftm_link_th_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "all_ftm_total_congest_th",
-        NPPU_PBU_CFG_ALL_FTM_TOTAL_CONGEST_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x710,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_all_ftm_total_congest_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_crdt_mode",
-        NPPU_PBU_CFG_CFG_CRDT_MODEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x720,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_cfg_crdt_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_pfc_rdy_high_time",
-        NPPU_PBU_CFG_CFG_PFC_RDY_HIGH_TIMEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x728,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_cfg_pfc_rdy_high_time_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_pfc_rdy_low_time",
-        NPPU_PBU_CFG_CFG_PFC_RDY_LOW_TIMEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x72c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_cfg_cfg_pfc_rdy_low_time_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_fc_rdy",
-        NPPU_PBU_STAT_PBU_FC_RDYr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x580,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_pbu_stat_pbu_fc_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_lif_group0_rdy0",
-        NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x5c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_nppu_pbu_stat_pbu_lif_group0_rdy0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_lif_group0_rdy1",
-        NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x5c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_pbu_lif_group0_rdy1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_lif_group1_rdy",
-        NPPU_PBU_STAT_PBU_LIF_GROUP1_RDYr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x5e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_pbu_lif_group1_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_lif_group0_pfc_rdy",
-        NPPU_PBU_STAT_PBU_LIF_GROUP0_PFC_RDYr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x0600,
-        (32/8),
-        0,
-        11 + 1,
-        0,
-        4,
-        1,
-        g_nppu_pbu_stat_pbu_lif_group0_pfc_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_lif_group1_pfc_rdy",
-        NPPU_PBU_STAT_PBU_LIF_GROUP1_PFC_RDYr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x0640,
-        (32/8),
-        0,
-        1 + 1,
-        0,
-        4,
-        1,
-        g_nppu_pbu_stat_pbu_lif_group1_pfc_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_sa_port_rdy_0_31",
-        NPPU_PBU_STAT_PBU_SA_PORT_RDY_0_31r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x680,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_pbu_sa_port_rdy_0_31_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_sa_port_rdy_32_50",
-        NPPU_PBU_STAT_PBU_SA_PORT_RDY_32_50r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x684,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_pbu_sa_port_rdy_32_50_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_pktrx_mr_pfc_rdy",
-        NPPU_PBU_STAT_PBU_PKTRX_MR_PFC_RDYr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_pbu_pktrx_mr_pfc_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ftm_crdt_port_rdy_0_31",
-        NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_0_31r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_0_31_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ftm_crdt_port_rdy_32_47",
-        NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_32_47r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_32_47_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ftm_crdt_port_cng_rdy_0_31",
-        NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_0_31r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_0_31_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ftm_crdt_port_cng_rdy_32_47",
-        NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_32_47r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_32_47_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ftm_crdt_sys_info",
-        NPPU_PBU_STAT_PBU_FTM_CRDT_SYS_INFOr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_pbu_stat_pbu_ftm_crdt_sys_info_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "weight_normal_mc",
-        NPPU_ISU_CFG_WEIGHT_NORMAL_MCr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_weight_normal_mc_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "weight_sa_mc",
-        NPPU_ISU_CFG_WEIGHT_SA_MCr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_weight_sa_mc_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "weight_etm",
-        NPPU_ISU_CFG_WEIGHT_ETMr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_weight_etm_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "weight_lp_mc",
-        NPPU_ISU_CFG_WEIGHT_LP_MCr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_weight_lp_mc_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "weight_oam",
-        NPPU_ISU_CFG_WEIGHT_OAMr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_weight_oam_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "weight_lif_ctrl1",
-        NPPU_ISU_CFG_WEIGHT_LIF_CTRL1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_weight_lif_ctrl1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "weight_lif_ctrl2",
-        NPPU_ISU_CFG_WEIGHT_LIF_CTRL2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_weight_lif_ctrl2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ecc_bypass_read",
-        NPPU_ISU_CFG_ECC_BYPASS_READr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_ecc_bypass_read_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_int_mask",
-        NPPU_ISU_CFG_ISU_INT_MASKr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_isu_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_crdt_cycle",
-        NPPU_ISU_CFG_CFG_CRDT_CYCLEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x002c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_cfg_crdt_cycle_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_crdt_value",
-        NPPU_ISU_CFG_CFG_CRDT_VALUEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_cfg_crdt_value_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_int_en",
-        NPPU_ISU_CFG_ISU_INT_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_isu_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_ppu_fifo_fc",
-        NPPU_ISU_CFG_ISU_PPU_FIFO_FCr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_isu_ppu_fifo_fc_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_int_status",
-        NPPU_ISU_CFG_ISU_INT_STATUSr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x003c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        27,
-        g_nppu_isu_cfg_isu_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fd_prog_full_assert_cfg",
-        NPPU_ISU_CFG_FD_PROG_FULL_ASSERT_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_fd_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fd_prog_full_negate_cfg",
-        NPPU_ISU_CFG_FD_PROG_FULL_NEGATE_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_fd_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lp_prog_full_assert_cfg",
-        NPPU_ISU_CFG_LP_PROG_FULL_ASSERT_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_lp_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lp_prog_full_negate_cfg",
-        NPPU_ISU_CFG_LP_PROG_FULL_NEGATE_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_cfg_lp_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat0",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat1",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat2",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat3",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat4",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT4r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat5",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT5r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat6",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT6r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat7",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT7r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat8",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT8r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x002c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat9",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT9r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat10",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT10r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat11",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT11r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat12",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT12r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x003c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat13",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT13r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat14",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT14r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat15",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT15r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat16",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT16r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat17",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT17r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat18",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT18r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_dat19",
-        NPPU_ISU_STAT_DEBUG_CNT_DAT19r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_isu_stat_debug_cnt_dat19_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_cfg",
-        NPPU_ISU_STAT_DEBUG_CNT_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0100,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_nppu_isu_stat_debug_cnt_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "exsa_tdm_offset",
-        NPPU_ODMA_CFG_EXSA_TDM_OFFSETr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_exsa_tdm_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ecc_bypass_readt",
-        NPPU_ODMA_CFG_ECC_BYPASS_READTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_ecc_bypass_readt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_int_en_0",
-        NPPU_ODMA_CFG_ODMA_INT_EN_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        11,
-        g_nppu_odma_cfg_odma_int_en_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_int_en_1",
-        NPPU_ODMA_CFG_ODMA_INT_EN_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        23,
-        g_nppu_odma_cfg_odma_int_en_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_int_en_2",
-        NPPU_ODMA_CFG_ODMA_INT_EN_2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        10,
-        g_nppu_odma_cfg_odma_int_en_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_int_en_3",
-        NPPU_ODMA_CFG_ODMA_INT_EN_3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x002c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        13,
-        g_nppu_odma_cfg_odma_int_en_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_int_mask_0",
-        NPPU_ODMA_CFG_ODMA_INT_MASK_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        11,
-        g_nppu_odma_cfg_odma_int_mask_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_int_mask_1",
-        NPPU_ODMA_CFG_ODMA_INT_MASK_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        24,
-        g_nppu_odma_cfg_odma_int_mask_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_int_mask_2",
-        NPPU_ODMA_CFG_ODMA_INT_MASK_2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        10,
-        g_nppu_odma_cfg_odma_int_mask_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_int_mask_3",
-        NPPU_ODMA_CFG_ODMA_INT_MASK_3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x003c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        13,
-        g_nppu_odma_cfg_odma_int_mask_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_int_status_0",
-        NPPU_ODMA_CFG_ODMA_INT_STATUS_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        11,
-        g_nppu_odma_cfg_odma_int_status_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_int_status_1",
-        NPPU_ODMA_CFG_ODMA_INT_STATUS_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        23,
-        g_nppu_odma_cfg_odma_int_status_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_int_status_2",
-        NPPU_ODMA_CFG_ODMA_INT_STATUS_2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        10,
-        g_nppu_odma_cfg_odma_int_status_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_int_status_3",
-        NPPU_ODMA_CFG_ODMA_INT_STATUS_3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        15,
-        g_nppu_odma_cfg_odma_int_status_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sp_tdm_err_nor_cfg",
-        NPPU_ODMA_CFG_SP_TDM_ERR_NOR_CFGr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_sp_tdm_err_nor_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_dis_ptr_prog_full_cfg_a",
-        NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_dis_ptr_prog_full_cfg_n",
-        NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x006c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ftm_dis_ptr_prog_full_cfg_a",
-        NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0070,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ftm_dis_ptr_prog_full_cfg_n",
-        NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0074,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_dis_fifo_prog_full_cfg_a",
-        NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0078,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_dis_fifo_prog_full_cfg_n",
-        NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x007c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "err_prog_full_cfg_a",
-        NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_err_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "err_prog_full_cfg_n",
-        NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x008c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_err_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tdmuc_prog_full_cfg_a",
-        NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_tdmuc_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tdmuc_prog_full_cfg_n",
-        NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_tdmuc_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tdmmc_groupid_prog_full_cfg_a",
-        NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0098,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tdmmc_groupid_prog_full_cfg_n",
-        NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x009c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tdmmc_no_bitmap_prog_full_cfg_a",
-        NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tdmmc_no_bitmap_prog_full_cfg_n",
-        NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tdmmc_prog_full_cfg_a",
-        NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_tdmmc_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tdmmc_prog_full_cfg_n",
-        NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_tdmmc_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "desc_prog_full_cfg_a",
-        NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_desc_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "desc_prog_full_cfg_n",
-        NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_desc_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dly_prog_full_cfg_a",
-        NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_dly_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dly_prog_full_cfg_n",
-        NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_dly_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp_prog_full_cfg_a",
-        NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_rsp_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp_prog_full_cfg_n",
-        NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_rsp_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "nor_prog_full_cfg_a",
-        NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_nor_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "nor_prog_full_cfg_n",
-        NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_nor_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_nor_prog_full_cfg_a",
-        NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_etm_nor_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_nor_prog_full_cfg_n",
-        NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_etm_nor_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ftm_nor_prog_full_cfg_a",
-        NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_ftm_nor_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ftm_nor_prog_full_cfg_n",
-        NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_ftm_nor_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_prog_full_cfg_a",
-        NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_etm_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_prog_full_cfg_n",
-        NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_etm_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ftm_prog_full_cfg_a",
-        NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_ftm_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ftm_prog_full_cfg_n",
-        NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_ftm_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_nrdcnt_prog_full_cfg_a",
-        NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_nrdcnt_prog_full_cfg_n",
-        NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ftm_nrdcnt_prog_full_cfg_a",
-        NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ftm_nrdcnt_prog_full_cfg_n",
-        NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_prog_full_cfg_a",
-        NPPU_ODMA_CFG_PP_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0104,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_pp_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_prog_full_cfg_n",
-        NPPU_ODMA_CFG_PP_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0108,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_pp_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_weight",
-        NPPU_ODMA_CFG_TM_WEIGHTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x010c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_tm_weight_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp_weight",
-        NPPU_ODMA_CFG_PP_WEIGHTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0110,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_pp_weight_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ifbcmd_prog_full_cfg_a",
-        NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0218,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_ifbcmd_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ifbcmd_prog_full_cfg_n",
-        NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x021c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_ifbcmd_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mccnt_prog_full_cfg_a",
-        NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0220,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_mccnt_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mccnt_prog_full_cfg_n",
-        NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0224,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_mccnt_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_or_pon",
-        NPPU_ODMA_CFG_INT_OR_PONr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x228,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_int_or_pon_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "quemng_cnt_in_err_cnt",
-        NPPU_ODMA_CFG_QUEMNG_CNT_IN_ERR_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x22c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_quemng_cnt_in_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lif0_port_eop_cnt",
-        NPPU_ODMA_CFG_LIF0_PORT_EOP_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x240,
-        (32/8),
-        0,
-        47 + 1,
-        0,
-        4,
-        1,
-        g_nppu_odma_cfg_lif0_port_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lif1_port_eop_cnt",
-        NPPU_ODMA_CFG_LIF1_PORT_EOP_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x300,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        4,
-        1,
-        g_nppu_odma_cfg_lif1_port_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lifc_port0_eop_cnt",
-        NPPU_ODMA_CFG_LIFC_PORT0_EOP_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x320,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_lifc_port0_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lifc_port1_eop_cnt",
-        NPPU_ODMA_CFG_LIFC_PORT1_EOP_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x324,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_lifc_port1_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fptr_fifo_prog_ept_cfg_n",
-        NPPU_ODMA_CFG_FPTR_FIFO_PROG_EPT_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0404,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_fptr_fifo_prog_ept_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_fifo_prog_full_cfg_a",
-        NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_Ar,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0408,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_isu_fifo_prog_full_cfg_a_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_fifo_prog_full_cfg_n",
-        NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_Nr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x040c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_odma_cfg_isu_fifo_prog_full_cfg_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_access_done",
-        NPPU_OAM_CFG_IND_ACCESS_DONEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_access_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_access_command",
-        NPPU_OAM_CFG_IND_ACCESS_COMMANDr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_nppu_oam_cfg_ind_access_command_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat0",
-        NPPU_OAM_CFG_IND_DAT0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_dat0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat1",
-        NPPU_OAM_CFG_IND_DAT1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_dat1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat2",
-        NPPU_OAM_CFG_IND_DAT2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_dat2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat3",
-        NPPU_OAM_CFG_IND_DAT3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_dat3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_tx_main_en",
-        NPPU_OAM_CFG_OAM_TX_MAIN_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_oam_tx_main_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tx_total_num",
-        NPPU_OAM_CFG_TX_TOTAL_NUMr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_tx_total_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_chk_main_en",
-        NPPU_OAM_CFG_OAM_CHK_MAIN_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_oam_chk_main_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "chk_total_num0",
-        NPPU_OAM_CFG_CHK_TOTAL_NUM0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_chk_total_num0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ma_chk_main_en",
-        NPPU_OAM_CFG_MA_CHK_MAIN_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ma_chk_main_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "chk_total_num1",
-        NPPU_OAM_CFG_CHK_TOTAL_NUM1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x002c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_chk_total_num1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tx_stat_en",
-        NPPU_OAM_CFG_TX_STAT_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_tx_stat_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rec_stat_en",
-        NPPU_OAM_CFG_REC_STAT_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_rec_stat_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_oam_rdy_mask",
-        NPPU_OAM_CFG_STAT_OAM_RDY_MASKr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x003c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_stat_oam_rdy_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "session_grading0",
-        NPPU_OAM_CFG_SESSION_GRADING0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_session_grading0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "session_grading1",
-        NPPU_OAM_CFG_SESSION_GRADING1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_session_grading1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "session_grading2",
-        NPPU_OAM_CFG_SESSION_GRADING2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_session_grading2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "session_grading3",
-        NPPU_OAM_CFG_SESSION_GRADING3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_session_grading3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "bfd_chk_haddr",
-        NPPU_OAM_CFG_BFD_CHK_HADDRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_bfd_chk_haddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ethccm_chk_haddr",
-        NPPU_OAM_CFG_ETHCCM_CHK_HADDRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ethccm_chk_haddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tpbfd_chk_haddr",
-        NPPU_OAM_CFG_TPBFD_CHK_HADDRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_tpbfd_chk_haddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tpoam_ccm_chk_haddr",
-        NPPU_OAM_CFG_TPOAM_CCM_CHK_HADDRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x005c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_tpoam_ccm_chk_haddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "bfd_tx_haddr",
-        NPPU_OAM_CFG_BFD_TX_HADDRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_bfd_tx_haddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ethccm_tx_haddr",
-        NPPU_OAM_CFG_ETHCCM_TX_HADDRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ethccm_tx_haddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tpbfd_tx_haddr",
-        NPPU_OAM_CFG_TPBFD_TX_HADDRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_tpbfd_tx_haddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tpoam_ccm_tx_haddr",
-        NPPU_OAM_CFG_TPOAM_CCM_TX_HADDRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x006c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_tpoam_ccm_tx_haddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ethccm_ma_chk_haddr",
-        NPPU_OAM_CFG_ETHCCM_MA_CHK_HADDRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0070,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ethccm_ma_chk_haddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tpccm_ma_chk_haddr",
-        NPPU_OAM_CFG_TPCCM_MA_CHK_HADDRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0074,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_tpccm_ma_chk_haddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "groupnum_ram_clr",
-        NPPU_OAM_CFG_GROUPNUM_RAM_CLRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0078,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_groupnum_ram_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "index_ram0_clr",
-        NPPU_OAM_CFG_INDEX_RAM0_CLRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x007c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_index_ram0_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "index_ram1_clr",
-        NPPU_OAM_CFG_INDEX_RAM1_CLRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_index_ram1_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rmep_ram_clr",
-        NPPU_OAM_CFG_RMEP_RAM_CLRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_rmep_ram_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ma_ram_clr",
-        NPPU_OAM_CFG_MA_RAM_CLRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ma_ram_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ram_init_done",
-        NPPU_OAM_CFG_RAM_INIT_DONEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x008c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ram_init_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rec_bfd_debug_en",
-        NPPU_OAM_CFG_REC_BFD_DEBUG_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_rec_bfd_debug_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_session_int",
-        NPPU_OAM_CFG_OAM_SESSION_INTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0098,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_nppu_oam_cfg_oam_session_int_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pon_int",
-        NPPU_OAM_CFG_PON_INTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x009c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_oam_cfg_pon_int_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_int_clr",
-        NPPU_OAM_CFG_OAM_INT_CLRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_oam_int_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "type_int_clr0",
-        NPPU_OAM_CFG_TYPE_INT_CLR0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_nppu_oam_cfg_type_int_clr0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "type_int_clr1",
-        NPPU_OAM_CFG_TYPE_INT_CLR1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_nppu_oam_cfg_type_int_clr1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "interrupt_mask",
-        NPPU_OAM_CFG_INTERRUPT_MASKr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        8,
-        g_nppu_oam_cfg_interrupt_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int0_index",
-        NPPU_OAM_CFG_INT0_INDEXr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00b0,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_nppu_oam_cfg_int0_index_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int1_index",
-        NPPU_OAM_CFG_INT1_INDEXr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00c0,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_nppu_oam_cfg_int1_index_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int0_index_region",
-        NPPU_OAM_CFG_INT0_INDEX_REGIONr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_int0_index_region_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int1_index_region",
-        NPPU_OAM_CFG_INT1_INDEX_REGIONr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_int1_index_region_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "bdiinfo_fwft_fifo_th",
-        NPPU_OAM_CFG_BDIINFO_FWFT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_bdiinfo_fwft_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "recsec_fwft_fifo_th",
-        NPPU_OAM_CFG_RECSEC_FWFT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_recsec_fwft_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "timing_chk_info0_fwft_fifo_th",
-        NPPU_OAM_CFG_TIMING_CHK_INFO0_FWFT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_timing_chk_info0_fwft_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "recma_fwft_fifo_th",
-        NPPU_OAM_CFG_RECMA_FWFT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_recma_fwft_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "timing_chk_info1_fwft_fifo_th",
-        NPPU_OAM_CFG_TIMING_CHK_INFO1_FWFT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_timing_chk_info1_fwft_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_txinst_fifo_th",
-        NPPU_OAM_CFG_OAM_TXINST_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_oam_txinst_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_rdinfo_fwft_fifo_th",
-        NPPU_OAM_CFG_OAM_RDINFO_FWFT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_oam_rdinfo_fwft_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lm_cnt_fwft_fifo_th",
-        NPPU_OAM_CFG_LM_CNT_FWFT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_lm_cnt_fwft_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_pkt_fifo_th",
-        NPPU_OAM_CFG_OAM_PKT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_oam_pkt_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "reclm_stat_fifo_th",
-        NPPU_OAM_CFG_RECLM_STAT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_reclm_stat_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "txlm_stat_fifo_th",
-        NPPU_OAM_CFG_TXLM_STAT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00100,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_txlm_stat_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_chk_fwft_fifo_th",
-        NPPU_OAM_CFG_OAM_CHK_FWFT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0104,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_oam_chk_fwft_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "txoam_stat_fifo_th",
-        NPPU_OAM_CFG_TXOAM_STAT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0108,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_txoam_stat_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "recoam_stat_fifo_th",
-        NPPU_OAM_CFG_RECOAM_STAT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x010c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_recoam_stat_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "txpkt_data_fwft_fifo_th",
-        NPPU_OAM_CFG_TXPKT_DATA_FWFT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0110,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_txpkt_data_fwft_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tstpkt_fwft_fifo_th",
-        NPPU_OAM_CFG_TSTPKT_FWFT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0114,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_tstpkt_fwft_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tst_txinst_fwft_fifo_th",
-        NPPU_OAM_CFG_TST_TXINST_FWFT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0118,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_tst_txinst_fwft_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tstrx_main_en",
-        NPPU_OAM_CFG_TSTRX_MAIN_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x011c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_tstrx_main_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsttx_cfg_para_tbl2",
-        NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0120,
-        (32/8),
-        0,
-        9 + 1,
-        0,
-        12,
-        8,
-        g_nppu_oam_cfg_tsttx_cfg_para_tbl2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsttx_cfg_para_tbl1",
-        NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0124,
-        (32/8),
-        0,
-        9 + 1,
-        0,
-        12,
-        1,
-        g_nppu_oam_cfg_tsttx_cfg_para_tbl1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsttx_cfg_para_tbl0",
-        NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0128,
-        (32/8),
-        0,
-        9 + 1,
-        0,
-        12,
-        3,
-        g_nppu_oam_cfg_tsttx_cfg_para_tbl0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tstrx_cfg_para",
-        NPPU_OAM_CFG_TSTRX_CFG_PARAr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0198,
-        (32/8),
-        0,
-        0x9 + 1,
-        0,
-        4,
-        2,
-        g_nppu_oam_cfg_tstrx_cfg_para_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fifo_status_int_en_0",
-        NPPU_OAM_CFG_FIFO_STATUS_INT_EN_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x01c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_nppu_oam_cfg_fifo_status_int_en_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fifo_status_int_en_1",
-        NPPU_OAM_CFG_FIFO_STATUS_INT_EN_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x01c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        10,
-        g_nppu_oam_cfg_fifo_status_int_en_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fifo_status_int_mask_0",
-        NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x01c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_nppu_oam_cfg_fifo_status_int_mask_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fifo_status_int_mask_1",
-        NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x01cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        10,
-        g_nppu_oam_cfg_fifo_status_int_mask_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fifo_status_int_status",
-        NPPU_OAM_CFG_FIFO_STATUS_INT_STATUSr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x01d0,
-        (32/8),
-        0,
-        39 + 1,
-        0,
-        4,
-        1,
-        g_nppu_oam_cfg_fifo_status_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "main_frequency",
-        NPPU_OAM_CFG_MAIN_FREQUENCYr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0270,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_main_frequency_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_cfg_type",
-        NPPU_OAM_CFG_OAM_CFG_TYPEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0274,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_oam_cfg_type_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fst_swch_eth_head0",
-        NPPU_OAM_CFG_FST_SWCH_ETH_HEAD0r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0278,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_fst_swch_eth_head0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fst_swch_eth_head1",
-        NPPU_OAM_CFG_FST_SWCH_ETH_HEAD1r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x027c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_fst_swch_eth_head1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fst_swch_eth_head2",
-        NPPU_OAM_CFG_FST_SWCH_ETH_HEAD2r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0280,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_fst_swch_eth_head2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fst_swch_eth_head3",
-        NPPU_OAM_CFG_FST_SWCH_ETH_HEAD3r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0284,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_fst_swch_eth_head3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_fs_txinst_fifo_th",
-        NPPU_OAM_CFG_OAM_FS_TXINST_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0288,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_oam_fs_txinst_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_ma_fs_txinst_fifo_th",
-        NPPU_OAM_CFG_OAM_MA_FS_TXINST_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x028c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_oam_ma_fs_txinst_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pon_int_ram_clr",
-        NPPU_OAM_CFG_PON_INT_RAM_CLRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0290,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_pon_int_ram_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pon_p_int_index",
-        NPPU_OAM_CFG_PON_P_INT_INDEXr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0294,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_pon_p_int_index_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pon_protect_pkt_fifo_th",
-        NPPU_OAM_CFG_PON_PROTECT_PKT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0298,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_pon_protect_pkt_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pon_laser_off_en",
-        NPPU_OAM_CFG_PON_LASER_OFF_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x029c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_pon_laser_off_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pon_prtct_pkt_tx_en",
-        NPPU_OAM_CFG_PON_PRTCT_PKT_TX_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_pon_prtct_pkt_tx_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_pon_master",
-        NPPU_OAM_CFG_CFG_PON_MASTERr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_cfg_pon_master_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "level_mode",
-        NPPU_OAM_CFG_LEVEL_MODEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_level_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "interrupt_en",
-        NPPU_OAM_CFG_INTERRUPT_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_interrupt_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pon_laser_on_en",
-        NPPU_OAM_CFG_PON_LASER_ON_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_pon_laser_on_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ti_pon_sd",
-        NPPU_OAM_CFG_TI_PON_SDr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ti_pon_sd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ti_pon_los",
-        NPPU_OAM_CFG_TI_PON_LOSr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ti_pon_los_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat4",
-        NPPU_OAM_CFG_IND_DAT4r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_dat4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat5",
-        NPPU_OAM_CFG_IND_DAT5r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_dat5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat6",
-        NPPU_OAM_CFG_IND_DAT6r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_dat6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat7",
-        NPPU_OAM_CFG_IND_DAT7r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_dat7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat8",
-        NPPU_OAM_CFG_IND_DAT8r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_dat8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat9",
-        NPPU_OAM_CFG_IND_DAT9r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_dat9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat10",
-        NPPU_OAM_CFG_IND_DAT10r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_dat10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat11",
-        NPPU_OAM_CFG_IND_DAT11r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_dat11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat12",
-        NPPU_OAM_CFG_IND_DAT12r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_dat12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat13",
-        NPPU_OAM_CFG_IND_DAT13r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_dat13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat14",
-        NPPU_OAM_CFG_IND_DAT14r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_dat14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ind_dat15",
-        NPPU_OAM_CFG_IND_DAT15r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ind_dat15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_2544_pkt_fifo_th",
-        NPPU_OAM_CFG_OAM_2544_PKT_FIFO_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_oam_2544_pkt_fifo_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "txinfo_ram_clr",
-        NPPU_OAM_CFG_TXINFO_RAM_CLRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_txinfo_ram_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "txinfo_ram_init_done",
-        NPPU_OAM_CFG_TXINFO_RAM_INIT_DONEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_txinfo_ram_init_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fifo_status_int_status40",
-        NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS40r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_fifo_status_int_status40_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "fifo_status_int_status41",
-        NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS41r,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_fifo_status_int_status41_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_2544_fun_en",
-        NPPU_OAM_CFG_OAM_2544_FUN_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0300,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_oam_2544_fun_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_2544_stat_clr",
-        NPPU_OAM_CFG_OAM_2544_STAT_CLRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0304,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_oam_2544_stat_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "txdis_default",
-        NPPU_OAM_CFG_TXDIS_DEFAULTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0308,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_txdis_default_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "txdis_default_en",
-        NPPU_OAM_CFG_TXDIS_DEFAULT_ENr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x030c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_txdis_default_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tpbfd_firstchk_th",
-        NPPU_OAM_CFG_TPBFD_FIRSTCHK_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0310,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_tpbfd_firstchk_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ethccm_firstchk_th",
-        NPPU_OAM_CFG_ETHCCM_FIRSTCHK_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0314,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_ethccm_firstchk_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tpccm_firstchk_th",
-        NPPU_OAM_CFG_TPCCM_FIRSTCHK_THr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0318,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_cfg_tpccm_firstchk_th_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "txstat_req_cnt",
-        NPPU_OAM_STAT_TXSTAT_REQ_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_txstat_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "chkstat_req_cnt",
-        NPPU_OAM_STAT_CHKSTAT_REQ_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_chkstat_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_oam_fc_cnt",
-        NPPU_OAM_STAT_STAT_OAM_FC_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_stat_oam_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "bfdseq_req_cnt",
-        NPPU_OAM_STAT_BFDSEQ_REQ_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_bfdseq_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lmcnt_req_cnt",
-        NPPU_OAM_STAT_LMCNT_REQ_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_lmcnt_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_oam_lm_rsp_cnt",
-        NPPU_OAM_STAT_STAT_OAM_LM_RSP_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_stat_oam_lm_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_oam_lm_fc_cnt",
-        NPPU_OAM_STAT_STAT_OAM_LM_FC_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_stat_oam_lm_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_req_cnt",
-        NPPU_OAM_STAT_SE_REQ_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_se_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_rsp_cnt",
-        NPPU_OAM_STAT_SE_RSP_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_se_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_oam_fc_cnt",
-        NPPU_OAM_STAT_SE_OAM_FC_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_se_oam_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_se_fc_cnt",
-        NPPU_OAM_STAT_OAM_SE_FC_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_oam_se_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_pktrx_sop_cnt",
-        NPPU_OAM_STAT_OAM_PKTRX_SOP_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x002c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_oam_pktrx_sop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_pktrx_eop_cnt",
-        NPPU_OAM_STAT_OAM_PKTRX_EOP_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_oam_pktrx_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_oam_fc_cnt",
-        NPPU_OAM_STAT_PKTRX_OAM_FC_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_pktrx_oam_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_oam_tst_fc_cnt",
-        NPPU_OAM_STAT_PKTRX_OAM_TST_FC_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_pktrx_oam_tst_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_oam_sop_cnt",
-        NPPU_OAM_STAT_ODMA_OAM_SOP_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x003c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_odma_oam_sop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_oam_eop_cnt",
-        NPPU_OAM_STAT_ODMA_OAM_EOP_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_odma_oam_eop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_odma_fc_cnt",
-        NPPU_OAM_STAT_OAM_ODMA_FC_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_oam_odma_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rec_ma_pkt_illegal_cnt",
-        NPPU_OAM_STAT_REC_MA_PKT_ILLEGAL_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_rec_ma_pkt_illegal_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rec_rmep_pkt_illegal_cnt",
-        NPPU_OAM_STAT_REC_RMEP_PKT_ILLEGAL_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_rec_rmep_pkt_illegal_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rec_eth_ais_pkt_cnt",
-        NPPU_OAM_STAT_REC_ETH_AIS_PKT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_rec_eth_ais_pkt_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rec_tp_ais_pkt_cnt",
-        NPPU_OAM_STAT_REC_TP_AIS_PKT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_rec_tp_ais_pkt_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rec_tp_csf_pkt_cnt",
-        NPPU_OAM_STAT_REC_TP_CSF_PKT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_rec_tp_csf_pkt_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rec_eth_level_defect_cnt",
-        NPPU_OAM_STAT_REC_ETH_LEVEL_DEFECT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x005c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_rec_eth_level_defect_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rec_eth_megid_defect_cnt",
-        NPPU_OAM_STAT_REC_ETH_MEGID_DEFECT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_rec_eth_megid_defect_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rec_eth_mepid_defect_cnt",
-        NPPU_OAM_STAT_REC_ETH_MEPID_DEFECT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_rec_eth_mepid_defect_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rec_eth_interval_defect_cnt",
-        NPPU_OAM_STAT_REC_ETH_INTERVAL_DEFECT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_rec_eth_interval_defect_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rec_sess_unenable_cnt",
-        NPPU_OAM_STAT_REC_SESS_UNENABLE_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x006c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_rec_sess_unenable_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_2544_rd_pkt_cnt",
-        NPPU_OAM_STAT_OAM_2544_RD_PKT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0070,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_oam_2544_rd_pkt_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_clr",
-        NPPU_OAM_STAT_DEBUG_CNT_CLRr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0074,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_debug_cnt_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_pktrx_catch_data",
-        NPPU_OAM_STAT_OAM_PKTRX_CATCH_DATAr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0078,
-        (32/8),
-        0,
-        0x1F + 1,
-        0,
-        4,
-        1,
-        g_nppu_oam_stat_oam_pktrx_catch_data_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_oam_catch_data",
-        NPPU_OAM_STAT_ODMA_OAM_CATCH_DATAr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x00f8,
-        (32/8),
-        0,
-        0x1F + 1,
-        0,
-        4,
-        1,
-        g_nppu_oam_stat_odma_oam_catch_data_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tst_session_tx_cnt",
-        NPPU_OAM_STAT_TST_SESSION_TX_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0178,
-        (32/8),
-        0,
-        0x9 + 1,
-        0,
-        4,
-        1,
-        g_nppu_oam_stat_tst_session_tx_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tst_session_rx_cnt",
-        NPPU_OAM_STAT_TST_SESSION_RX_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01a0,
-        (32/8),
-        0,
-        0x9 + 1,
-        0,
-        4,
-        1,
-        g_nppu_oam_stat_tst_session_rx_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tstrx_lost_cnt",
-        NPPU_OAM_STAT_TSTRX_LOST_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01c8,
-        (32/8),
-        0,
-        0x9 + 1,
-        0,
-        4,
-        1,
-        g_nppu_oam_stat_tstrx_lost_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "bfdseq_wr_cnt",
-        NPPU_OAM_STAT_BFDSEQ_WR_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_bfdseq_wr_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "bfdtime_wr_cnt",
-        NPPU_OAM_STAT_BFDTIME_WR_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_bfdtime_wr_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lmcnt_wr_cnt",
-        NPPU_OAM_STAT_LMCNT_WR_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_lmcnt_wr_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_fs_pkt_cnt",
-        NPPU_OAM_STAT_OAM_FS_PKT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_oam_fs_pkt_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_ma_fs_pkt_cnt",
-        NPPU_OAM_STAT_OAM_MA_FS_PKT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0200,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_oam_ma_fs_pkt_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rec_tp_level_defect_cnt",
-        NPPU_OAM_STAT_REC_TP_LEVEL_DEFECT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0204,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_rec_tp_level_defect_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rec_tp_megid_defect_cnt",
-        NPPU_OAM_STAT_REC_TP_MEGID_DEFECT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0208,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_rec_tp_megid_defect_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rec_tp_mepid_defect_cnt",
-        NPPU_OAM_STAT_REC_TP_MEPID_DEFECT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x020c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_rec_tp_mepid_defect_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rec_tp_interval_defect_cnt",
-        NPPU_OAM_STAT_REC_TP_INTERVAL_DEFECT_CNTr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0210,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_rec_tp_interval_defect_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rd_reg_clear_mode",
-        NPPU_OAM_STAT_RD_REG_CLEAR_MODEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0214,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_rd_reg_clear_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rd_data_reg_clear_mode",
-        NPPU_OAM_STAT_RD_DATA_REG_CLEAR_MODEr,
-        NPPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0218,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_nppu_oam_stat_rd_data_reg_clear_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_int_status_ram_0",
-        NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM_0r,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x00000000,
-        (32/8),
-        0,
-        4095 + 1,
-        0,
-        1,
-        7,
-        g_nppu_oam_cfg_indir_oam_int_status_ram_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_int_status_ram1",
-        NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM1r,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x10000000,
-        (32/8),
-        0,
-        4095 + 1,
-        0,
-        1,
-        12,
-        g_nppu_oam_cfg_indir_oam_int_status_ram1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tst_pkt_tx_para_ram",
-        NPPU_OAM_CFG_INDIR_TST_PKT_TX_PARA_RAMr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x20000000,
-        (96/8),
-        0,
-        127 + 1,
-        0,
-        1,
-        12,
-        g_nppu_oam_cfg_indir_tst_pkt_tx_para_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "groupnumram",
-        NPPU_OAM_CFG_INDIR_GROUPNUMRAMr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x30000000,
-        (32/8),
-        0,
-        4095 + 1,
-        0,
-        1,
-        1,
-        g_nppu_oam_cfg_indir_groupnumram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_tx_tbl_ram",
-        NPPU_OAM_CFG_INDIR_OAM_TX_TBL_RAMr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x40000000,
-        (64/8),
-        0,
-        4095 + 1,
-        0,
-        1,
-        8,
-        g_nppu_oam_cfg_indir_oam_tx_tbl_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_chk_tbl_ram",
-        NPPU_OAM_CFG_INDIR_OAM_CHK_TBL_RAMr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x50000000,
-        (64/8),
-        0,
-        4095 + 1,
-        0,
-        1,
-        9,
-        g_nppu_oam_cfg_indir_oam_chk_tbl_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_ma_chk_tbl_ram",
-        NPPU_OAM_CFG_INDIR_OAM_MA_CHK_TBL_RAMr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x60000000,
-        (160/8),
-        0,
-        4095 + 1,
-        0,
-        1,
-        22,
-        g_nppu_oam_cfg_indir_oam_ma_chk_tbl_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_2544_tx_ram",
-        NPPU_OAM_CFG_INDIR_OAM_2544_TX_RAMr,
-        NPPU,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_UNI_ARRAY,
-        0x90000000,
-        (64/8),
-        0,
-        127 + 1,
-        0,
-        1,
-        5,
-        g_nppu_oam_cfg_indir_oam_2544_tx_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "interrupt_en_r",
-        PPU_PPU_INTERRUPT_EN_Rr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_interrupt_en_r_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mec_host_interrupt",
-        PPU_PPU_MEC_HOST_INTERRUPTr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_mec_host_interrupt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_rtl_date",
-        PPU_PPU_DBG_RTL_DATEr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_dbg_rtl_date_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dup_start_num_cfg",
-        PPU_PPU_DUP_START_NUM_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x02c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_dup_start_num_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_data_write_complete",
-        PPU_PPU_DEBUG_DATA_WRITE_COMPLETEr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_debug_data_write_complete_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "uc_mc_wrr_cfg",
-        PPU_PPU_UC_MC_WRR_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_uc_mc_wrr_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_pkt_send_en",
-        PPU_PPU_DEBUG_PKT_SEND_ENr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_debug_pkt_send_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dup_tbl_ind_access_done",
-        PPU_PPU_DUP_TBL_IND_ACCESS_DONEr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x04c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_dup_tbl_ind_access_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_ppu_demux_fifo_interrupt_mask",
-        PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_MASKr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_ppu_ppu_isu_ppu_demux_fifo_interrupt_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_multicast_fifo_interrupt_mask",
-        PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_MASKr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        20,
-        g_ppu_ppu_ppu_multicast_fifo_interrupt_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_in_schedule_fifo_interrupt_mask",
-        PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_MASKr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_ppu_ppu_ppu_in_schedule_fifo_interrupt_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_mf_out_fifo_interrupt_mask",
-        PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_MASKr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x08c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        12,
-        g_ppu_ppu_ppu_mf_out_fifo_interrupt_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_mcode_pf_req_schedule_fifo_interrupt_mask",
-        PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_MASKr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        12,
-        g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_mcode_pf_rsp_schedule_fifo_interrupt_mask",
-        PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_MASKr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_mccnt_fifo_interrupt_mask",
-        PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_MASKr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x098,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_ppu_ppu_ppu_mccnt_fifo_interrupt_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "coprocessor_fifo_interrupt_mask_l",
-        PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x09c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_ppu_ppu_coprocessor_fifo_interrupt_mask_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "coprocessor_fifo_interrupt_mask_m",
-        PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Mr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_ppu_ppu_coprocessor_fifo_interrupt_mask_m_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "coprocessor_fifo_interrupt_mask_h",
-        PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_ppu_ppu_coprocessor_fifo_interrupt_mask_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_ram_check_err_mask",
-        PPU_PPU_PPU_RAM_CHECK_ERR_MASKr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_ram_check_err_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_fifo_interrupt_mask",
-        PPU_PPU_INSTRMEM_FIFO_INTERRUPT_MASKr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        12,
-        g_ppu_ppu_instrmem_fifo_interrupt_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_ppu_demux_fifo_interrupt_sta",
-        PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_STAr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xc0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_ppu_ppu_isu_ppu_demux_fifo_interrupt_sta_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_multicast_fifo_interrupt_sta",
-        PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_STAr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        20,
-        g_ppu_ppu_ppu_multicast_fifo_interrupt_sta_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_in_schedule_fifo_interrupt_sta",
-        PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_STAr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_ppu_ppu_ppu_in_schedule_fifo_interrupt_sta_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_mf_out_fifo_interrupt_sta",
-        PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_STAr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xcc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        12,
-        g_ppu_ppu_ppu_mf_out_fifo_interrupt_sta_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_mcode_pf_req_schedule_fifo_interrupt_sta",
-        PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_STAr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        12,
-        g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_sta_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_mcode_pf_rsp_schedule_fifo_interrupt_sta",
-        PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_STAr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_sta_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_mccnt_fifo_interrupt_sta",
-        PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_STAr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_ppu_ppu_ppu_mccnt_fifo_interrupt_sta_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "coprocessor_fifo_interrupt_sta_l",
-        PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_ppu_ppu_coprocessor_fifo_interrupt_sta_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "coprocessor_fifo_interrupt_sta_m",
-        PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Mr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_ppu_ppu_coprocessor_fifo_interrupt_sta_m_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "coprocessor_fifo_interrupt_sta_h",
-        PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xe4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_ppu_ppu_coprocessor_fifo_interrupt_sta_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_fifo_interrupt_sta",
-        PPU_PPU_INSTRMEM_FIFO_INTERRUPT_STAr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        8,
-        g_ppu_ppu_instrmem_fifo_interrupt_sta_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_ram_check_ecc_err_flag_1",
-        PPU_PPU_PPU_RAM_CHECK_ECC_ERR_FLAG_1r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        26,
-        g_ppu_ppu_ppu_ram_check_ecc_err_flag_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_ppu_demux_fifo_interrupt_flag",
-        PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_FLAGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x100,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_ppu_ppu_isu_ppu_demux_fifo_interrupt_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_multicast_fifo_interrupt_flag",
-        PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_FLAGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x104,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        20,
-        g_ppu_ppu_ppu_multicast_fifo_interrupt_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_in_schedule_fifo_interrupt_flag",
-        PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_FLAGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x108,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_ppu_ppu_ppu_in_schedule_fifo_interrupt_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_mf_out_fifo_interrupt_flag",
-        PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_FLAGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x10c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        12,
-        g_ppu_ppu_ppu_mf_out_fifo_interrupt_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_mcode_pf_req_schedule_fifo_interrupt_flag",
-        PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_FLAGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x110,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        12,
-        g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_mcode_pf_rsp_schedule_fifo_interrupt_flag",
-        PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_FLAGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x114,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_mccnt_fifo_interrupt_flag",
-        PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_FLAGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x118,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_ppu_ppu_ppu_mccnt_fifo_interrupt_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "coprocessor_fifo_interrupt_flag_l",
-        PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x11c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_ppu_ppu_coprocessor_fifo_interrupt_flag_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "coprocessor_fifo_interrupt_flag_m",
-        PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Mr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x120,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_ppu_ppu_coprocessor_fifo_interrupt_flag_m_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "coprocessor_fifo_interrupt_flag_h",
-        PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x124,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_ppu_ppu_coprocessor_fifo_interrupt_flag_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_fifo_interrupt_flag",
-        PPU_PPU_INSTRMEM_FIFO_INTERRUPT_FLAGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x128,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        12,
-        g_ppu_ppu_instrmem_fifo_interrupt_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_ram_int_out",
-        PPU_PPU_INSTRMEM_RAM_INT_OUTr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x140,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        12,
-        g_ppu_ppu_instrmem_ram_int_out_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_ram_int_mask",
-        PPU_PPU_INSTRMEM_RAM_INT_MASKr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x144,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        12,
-        g_ppu_ppu_instrmem_ram_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_ram_int_stat",
-        PPU_PPU_INSTRMEM_RAM_INT_STATr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x148,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        12,
-        g_ppu_ppu_instrmem_ram_int_stat_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_ram_int_flag",
-        PPU_PPU_INSTRMEM_RAM_INT_FLAGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x14c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        12,
-        g_ppu_ppu_instrmem_ram_int_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_count_cfg",
-        PPU_PPU_PPU_COUNT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x158,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_ppu_ppu_ppu_count_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_statics_cfg",
-        PPU_PPU_PPU_STATICS_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x15c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_ppu_ppu_ppu_statics_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_statics_wb_cfg",
-        PPU_PPU_PPU_STATICS_WB_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x160,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_ppu_ppu_ppu_statics_wb_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "wr_table_self_rsp_en_cfg",
-        PPU_PPU_WR_TABLE_SELF_RSP_EN_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x164,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_wr_table_self_rsp_en_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_random_arbiter_8to1_cfg",
-        PPU_PPU_PPU_RANDOM_ARBITER_8TO1_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x168,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_random_arbiter_8to1_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_reorder_bypass_flow_num_cfg",
-        PPU_PPU_PPU_REORDER_BYPASS_FLOW_NUM_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x16c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_reorder_bypass_flow_num_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cos_meter_cfg_h",
-        PPU_PPU_COS_METER_CFG_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x170,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        8,
-        5,
-        g_ppu_ppu_cos_meter_cfg_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cos_meter_cfg_l",
-        PPU_PPU_COS_METER_CFG_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x174,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        8,
-        3,
-        g_ppu_ppu_cos_meter_cfg_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_rdy",
-        PPU_PPU_INSTRMEM_RDYr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x1c0,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_addr",
-        PPU_PPU_INSTRMEM_ADDRr,
-        PPU,
-        DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x1d0,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        2,
-        g_ppu_ppu_instrmem_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_ind_access_done",
-        PPU_PPU_INSTRMEM_IND_ACCESS_DONEr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x1e0,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_ind_access_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_instr0_data_l",
-        PPU_PPU_INSTRMEM_INSTR0_DATA_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x1f0,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_instr0_data_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_instr0_data_h",
-        PPU_PPU_INSTRMEM_INSTR0_DATA_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x200,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_instr0_data_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_instr1_data_l",
-        PPU_PPU_INSTRMEM_INSTR1_DATA_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x210,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_instr1_data_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_instr1_data_h",
-        PPU_PPU_INSTRMEM_INSTR1_DATA_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x220,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_instr1_data_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_instr2_data_l",
-        PPU_PPU_INSTRMEM_INSTR2_DATA_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x230,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_instr2_data_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_instr2_data_h",
-        PPU_PPU_INSTRMEM_INSTR2_DATA_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x240,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_instr2_data_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_instr3_data_l",
-        PPU_PPU_INSTRMEM_INSTR3_DATA_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x250,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_instr3_data_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_instr3_data_h",
-        PPU_PPU_INSTRMEM_INSTR3_DATA_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x260,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_instr3_data_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_read_instr0_data_l",
-        PPU_PPU_INSTRMEM_READ_INSTR0_DATA_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x270,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_read_instr0_data_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_read_instr0_data_h",
-        PPU_PPU_INSTRMEM_READ_INSTR0_DATA_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x280,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_read_instr0_data_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_read_instr1_data_l",
-        PPU_PPU_INSTRMEM_READ_INSTR1_DATA_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x290,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_read_instr1_data_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_read_instr1_data_h",
-        PPU_PPU_INSTRMEM_READ_INSTR1_DATA_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x2a0,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_read_instr1_data_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_read_instr2_data_l",
-        PPU_PPU_INSTRMEM_READ_INSTR2_DATA_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x2b0,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_read_instr2_data_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_read_instr2_data_h",
-        PPU_PPU_INSTRMEM_READ_INSTR2_DATA_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x2c0,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_read_instr2_data_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_read_instr3_data_l",
-        PPU_PPU_INSTRMEM_READ_INSTR3_DATA_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x2d0,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_read_instr3_data_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "instrmem_read_instr3_data_h",
-        PPU_PPU_INSTRMEM_READ_INSTR3_DATA_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x2e0,
-        (32/8),
-        0,
-        2 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_instrmem_read_instr3_data_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_ppu_mc_srh_fc_cnt_h",
-        PPU_PPU_SE_PPU_MC_SRH_FC_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x300,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_se_ppu_mc_srh_fc_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_ppu_mc_srh_fc_cnt_l",
-        PPU_PPU_SE_PPU_MC_SRH_FC_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x304,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_se_ppu_mc_srh_fc_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_se_mc_srh_fc_cnt_h",
-        PPU_PPU_PPU_SE_MC_SRH_FC_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x308,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_se_mc_srh_fc_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_se_mc_srh_fc_cnt_l",
-        PPU_PPU_PPU_SE_MC_SRH_FC_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x30c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_se_mc_srh_fc_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_se_mc_srh_vld_cnt_h",
-        PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x310,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_se_mc_srh_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_se_mc_srh_vld_cnt_l",
-        PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x314,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_se_mc_srh_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_ppu_mc_srh_vld_cnt_h",
-        PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x318,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_se_ppu_mc_srh_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_ppu_mc_srh_vld_cnt_l",
-        PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x31c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_se_ppu_mc_srh_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_logic_pf_fc_cnt_h",
-        PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x320,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_logic_pf_fc_cnt_l",
-        PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x324,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_logic_rsp_fc_cnt_h",
-        PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x328,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_logic_rsp_fc_cnt_l",
-        PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x32c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_logic_pf_req_vld_cnt_h",
-        PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x330,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_logic_pf_req_vld_cnt_l",
-        PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x334,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_logic_pf_rsp_vld_cnt_h",
-        PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x338,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_logic_pf_rsp_vld_cnt_l",
-        PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x33c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_ifb_rd_fc_cnt_h",
-        PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x340,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_ifb_rd_fc_cnt_l",
-        PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x344,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_wb_fc_cnt_h",
-        PPU_PPU_PBU_PPU_WB_FC_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x348,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pbu_ppu_wb_fc_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_wb_fc_cnt_l",
-        PPU_PPU_PBU_PPU_WB_FC_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x34c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pbu_ppu_wb_fc_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_mcode_pf_req_vld_cnt_h",
-        PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x350,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_mcode_pf_req_vld_cnt_l",
-        PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x354,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_mcode_pf_rsp_vld_cnt_h",
-        PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x358,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_mcode_pf_rsp_vld_cnt_l",
-        PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x35c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_ppu_para_fc_cnt_h",
-        PPU_PPU_ODMA_PPU_PARA_FC_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x360,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_odma_ppu_para_fc_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_ppu_para_fc_cnt_l",
-        PPU_PPU_ODMA_PPU_PARA_FC_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x364,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_odma_ppu_para_fc_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_ppu_mccnt_wr_fc_cnt_h",
-        PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x368,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_ppu_mccnt_wr_fc_cnt_l",
-        PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x36c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_odma_mccnt_wr_vld_cnt_h",
-        PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x370,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_odma_mccnt_wr_vld_cnt_l",
-        PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x374,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_ppu_mccnt_rsp_vld_cnt_h",
-        PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x378,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_ppu_mccnt_rsp_vld_cnt_l",
-        PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x37c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pktrx_uc_fc_cnt_h",
-        PPU_PPU_PPU_PKTRX_UC_FC_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x380,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pktrx_uc_fc_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pktrx_uc_fc_cnt_l",
-        PPU_PPU_PPU_PKTRX_UC_FC_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x384,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pktrx_uc_fc_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pktrx_mc_fc_cnt_h",
-        PPU_PPU_PPU_PKTRX_MC_FC_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x388,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pktrx_mc_fc_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pktrx_mc_fc_cnt_l",
-        PPU_PPU_PPU_PKTRX_MC_FC_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x38c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pktrx_mc_fc_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_ppu_desc_vld_cnt_h",
-        PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x390,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pktrx_ppu_desc_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pktrx_ppu_desc_vld_cnt_l",
-        PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x394,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pktrx_ppu_desc_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_ifb_req_vld_cnt_h",
-        PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x398,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_ifb_req_vld_cnt_l",
-        PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x39c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_ifb_rsp_vld_cnt_h",
-        PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_ifb_rsp_vld_cnt_l",
-        PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_wb_vld_cnt_h",
-        PPU_PPU_PPU_PBU_WB_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pbu_wb_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_wb_vld_cnt_l",
-        PPU_PPU_PPU_PBU_WB_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pbu_wb_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_reorder_para_vld_cnt_h",
-        PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ppu_reorder_para_vld_cnt_l",
-        PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_odma_para_vld_cnt_h",
-        PPU_PPU_PPU_ODMA_PARA_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_odma_para_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_odma_para_vld_cnt_l",
-        PPU_PPU_PPU_ODMA_PARA_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_odma_para_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_isu_ppu_mc_vld_cnt_h",
-        PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x400,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_isu_ppu_mc_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_isu_ppu_mc_vld_cnt_l",
-        PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x404,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_isu_ppu_mc_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_isu_ppu_mc_loop_vld_cnt_h",
-        PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x410,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_isu_ppu_mc_loop_vld_cnt_l",
-        PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x414,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_isu_ppu_uc_vld_cnt_h",
-        PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x418,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_isu_ppu_uc_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_isu_ppu_uc_vld_cnt_l",
-        PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x41c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_isu_ppu_uc_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_isu_ppu_uc_bufnumis0_vld_cnt_h",
-        PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x420,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_isu_ppu_uc_bufnumis0_vld_cnt_l",
-        PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x424,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_demux_schedule_mc_vld_cnt_h",
-        PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x438,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_demux_schedule_mc_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_demux_schedule_mc_vld_cnt_l",
-        PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x43c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_demux_schedule_mc_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_demux_schedule_mc_bufnumis0_vld_cnt_h",
-        PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x440,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_demux_schedule_mc_bufnumis0_vld_cnt_l",
-        PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x444,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_demux_schedule_mc_srcportis0_vld_cnt_h",
-        PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x448,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_demux_schedule_mc_srcportis0_vld_cnt_l",
-        PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x44c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_demux_schedule_mc_srcportis1_vld_cnt_h",
-        PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x450,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_demux_schedule_mc_srcportis1_vld_cnt_l",
-        PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x454,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_demux_schedule_uc_vld_cnt_h",
-        PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x458,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_demux_schedule_uc_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_demux_schedule_uc_vld_cnt_l",
-        PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x45c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_demux_schedule_uc_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_demux_schedule_uc_bufnumis0_vld_cnt_h",
-        PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x460,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_demux_schedule_uc_bufnumis0_vld_cnt_l",
-        PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x464,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_demux_schedule_uc_srcportis0_vld_cnt_h",
-        PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x468,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_demux_schedule_uc_srcportis0_vld_cnt_l",
-        PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x46c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_demux_schedule_uc_srcportis1_vld_cnt_h",
-        PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x470,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_demux_schedule_uc_srcportis1_vld_cnt_l",
-        PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x474,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_vld_cnt_h",
-        PPU_PPU_STATICS_PPU_WB_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x478,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_vld_cnt_l",
-        PPU_PPU_STATICS_PPU_WB_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x47c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_bufnumis0_vld_cnt_h",
-        PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x480,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_bufnumis0_vld_cnt_l",
-        PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x484,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_srcportis0_vld_cnt_h",
-        PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x488,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_srcportis0_vld_cnt_l",
-        PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x48c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_srcportis1_vld_cnt_h",
-        PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x490,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_srcportis1_vld_cnt_l",
-        PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x494,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_halt_send_type_vld_cnt_h",
-        PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x498,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_halt_send_type_vld_cnt_l",
-        PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x49c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_mf_type_vld_cnt_h",
-        PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_mf_type_vld_cnt_l",
-        PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_halt_continue_end_vld_cnt_h",
-        PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_halt_continue_end_vld_cnt_l",
-        PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_dup_flag_vld_cnt_h",
-        PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_dup_flag_vld_cnt_l",
-        PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_last_flag_vld_cnt_h",
-        PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_last_flag_vld_cnt_l",
-        PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_dis_flag_vld_cnt_h",
-        PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_ppu_wb_dis_flag_vld_cnt_l",
-        PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h",
-        PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l",
-        PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_pbu_ppu_reorder_mf_type_vld_cnt_h",
-        PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_pbu_ppu_reorder_mf_type_vld_cnt_l",
-        PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h",
-        PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l",
-        PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "car_green_pkt_vld_cnt_h",
-        PPU_PPU_CAR_GREEN_PKT_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_car_green_pkt_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "car_green_pkt_vld_cnt_l",
-        PPU_PPU_CAR_GREEN_PKT_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_car_green_pkt_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "car_yellow_pkt_vld_cnt_h",
-        PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_car_yellow_pkt_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "car_yellow_pkt_vld_cnt_l",
-        PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_car_yellow_pkt_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "car_red_pkt_vld_cnt_h",
-        PPU_PPU_CAR_RED_PKT_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_car_red_pkt_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "car_red_pkt_vld_cnt_l",
-        PPU_PPU_CAR_RED_PKT_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_car_red_pkt_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "car_drop_pkt_vld_cnt_h",
-        PPU_PPU_CAR_DROP_PKT_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_car_drop_pkt_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "car_drop_pkt_vld_cnt_l",
-        PPU_PPU_CAR_DROP_PKT_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_car_drop_pkt_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pktrx_mc_ptr_vld_cnt_h",
-        PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x500,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pktrx_mc_ptr_vld_cnt_l",
-        PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x504,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_ppu_loopback_fc_cnt_h",
-        PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x508,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_isu_ppu_loopback_fc_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_ppu_loopback_fc_cnt_l",
-        PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x50c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_isu_ppu_loopback_fc_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg",
-        PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x540,
-        (32/8),
-        0,
-        0x5 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg",
-        PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x558,
-        (32/8),
-        0,
-        0x5 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg",
-        PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x570,
-        (32/8),
-        0,
-        0x5 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg",
-        PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x588,
-        (32/8),
-        0,
-        0x5 + 1,
-        0,
-        4,
-        1,
-        g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg",
-        PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg",
-        PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg",
-        PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg",
-        PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mccnt_fifo_prog_full_assert_cfg",
-        PPU_PPU_MCCNT_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_mccnt_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mccnt_fifo_prog_full_negate_cfg",
-        PPU_PPU_MCCNT_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_mccnt_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mccnt_fifo_prog_empty_assert_cfg",
-        PPU_PPU_MCCNT_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_mccnt_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mccnt_fifo_prog_empty_negate_cfg",
-        PPU_PPU_MCCNT_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_mccnt_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "uc_mf_fifo_prog_full_assert_cfg",
-        PPU_PPU_UC_MF_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_uc_mf_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "uc_mf_fifo_prog_full_negate_cfg",
-        PPU_PPU_UC_MF_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_uc_mf_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "uc_mf_fifo_prog_empty_assert_cfg",
-        PPU_PPU_UC_MF_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_uc_mf_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "uc_mf_fifo_prog_empty_negate_cfg",
-        PPU_PPU_UC_MF_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_uc_mf_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mc_mf_fifo_prog_full_assert_cfg",
-        PPU_PPU_MC_MF_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_mc_mf_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mc_mf_fifo_prog_full_negate_cfg",
-        PPU_PPU_MC_MF_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_mc_mf_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mc_mf_fifo_prog_empty_assert_cfg",
-        PPU_PPU_MC_MF_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_mc_mf_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mc_mf_fifo_prog_empty_negate_cfg",
-        PPU_PPU_MC_MF_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_mc_mf_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_mf_fifo_prog_full_assert_cfg",
-        PPU_PPU_ISU_MF_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_isu_mf_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_mf_fifo_prog_full_negate_cfg",
-        PPU_PPU_ISU_MF_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_isu_mf_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_mf_fifo_prog_empty_assert_cfg",
-        PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_isu_mf_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_mf_fifo_prog_empty_negate_cfg",
-        PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_isu_mf_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_fwft_mf_fifo_prog_empty_assert_cfg",
-        PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_isu_fwft_mf_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_fwft_mf_fifo_prog_empty_negate_cfg",
-        PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_isu_fwft_mf_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_mc_para_mf_fifo_prog_full_assert_cfg",
-        PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x600,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_isu_mc_para_mf_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_mc_para_mf_fifo_prog_full_negate_cfg",
-        PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x604,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_isu_mc_para_mf_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_mc_para_mf_fifo_prog_empty_assert_cfg",
-        PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x608,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "isu_mc_para_mf_fifo_prog_empty_negate_cfg",
-        PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x60c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "group_id_fifo_prog_full_assert_cfg",
-        PPU_PPU_GROUP_ID_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x610,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_group_id_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "group_id_fifo_prog_full_negate_cfg",
-        PPU_PPU_GROUP_ID_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x614,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_group_id_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "group_id_fifo_prog_empty_assert_cfg",
-        PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x618,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_group_id_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "group_id_fifo_prog_empty_negate_cfg",
-        PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x61c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_group_id_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sa_para_fifo_prog_full_assert_cfg",
-        PPU_PPU_SA_PARA_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x620,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_sa_para_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sa_para_fifo_prog_full_negate_cfg",
-        PPU_PPU_SA_PARA_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x624,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_sa_para_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sa_para_fifo_prog_empty_assert_cfg",
-        PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x628,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_sa_para_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sa_para_fifo_prog_empty_negate_cfg",
-        PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x62c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_sa_para_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_mc_rsp_fifo_prog_full_assert_cfg",
-        PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x630,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_se_mc_rsp_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_mc_rsp_fifo_prog_full_negate_cfg",
-        PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x634,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_se_mc_rsp_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_mc_rsp_fifo_prog_empty_assert_cfg",
-        PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x638,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_se_mc_rsp_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_mc_rsp_fifo_prog_empty_negate_cfg",
-        PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x63c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_se_mc_rsp_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dup_para_fifo_prog_full_assert_cfg",
-        PPU_PPU_DUP_PARA_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x640,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_dup_para_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dup_para_fifo_prog_full_negate_cfg",
-        PPU_PPU_DUP_PARA_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x644,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_dup_para_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dup_para_fifo_prog_empty_assert_cfg",
-        PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x648,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_dup_para_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dup_para_fifo_prog_empty_negate_cfg",
-        PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x64c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_dup_para_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pf_rsp_fifo_prog_full_assert_cfg",
-        PPU_PPU_PF_RSP_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x650,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pf_rsp_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pf_rsp_fifo_prog_full_negate_cfg",
-        PPU_PPU_PF_RSP_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x654,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pf_rsp_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pf_rsp_fifo_prog_empty_assert_cfg",
-        PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x658,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pf_rsp_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pf_rsp_fifo_prog_empty_negate_cfg",
-        PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x65c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pf_rsp_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dup_freeptr_fifo_prog_full_assert_cfg",
-        PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x660,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_dup_freeptr_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dup_freeptr_fifo_prog_full_negate_cfg",
-        PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x664,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_dup_freeptr_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dup_freeptr_fifo_prog_empty_assert_cfg",
-        PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x668,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_dup_freeptr_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dup_freeptr_fifo_prog_empty_negate_cfg",
-        PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x66c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_dup_freeptr_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pf_req_fifo_prog_full_assert_cfg",
-        PPU_PPU_PF_REQ_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x670,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pf_req_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pf_req_fifo_prog_full_negate_cfg",
-        PPU_PPU_PF_REQ_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x674,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pf_req_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pf_req_fifo_prog_empty_assert_cfg",
-        PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x678,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pf_req_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pf_req_fifo_prog_empty_negate_cfg",
-        PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x67c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pf_req_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "car_flag_fifo_prog_full_assert_cfg",
-        PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x680,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_car_flag_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "car_flag_fifo_prog_full_negate_cfg",
-        PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x684,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_car_flag_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "car_flag_fifo_prog_empty_assert_cfg",
-        PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x688,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_car_flag_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "car_flag_fifo_prog_empty_negate_cfg",
-        PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x68c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_car_flag_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cluster_mf_out_afifo_prog_full_assert_cfg",
-        PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x690,
-        (32/8),
-        0,
-        0x5 + 1,
-        0,
-        16,
-        1,
-        g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cluster_mf_out_afifo_prog_full_negate_cfg",
-        PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x694,
-        (32/8),
-        0,
-        0x5 + 1,
-        0,
-        16,
-        1,
-        g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cluster_mf_out_afifo_prog_empty_assert_cfg",
-        PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x698,
-        (32/8),
-        0,
-        0x5 + 1,
-        0,
-        16,
-        1,
-        g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cluster_mf_out_afifo_prog_empty_negate_cfg",
-        PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x69c,
-        (32/8),
-        0,
-        0x5 + 1,
-        0,
-        16,
-        1,
-        g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_key_fifo_prog_full_assert_cfg",
-        PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x6f0,
-        (32/8),
-        0,
-        0x5 + 1,
-        0,
-        16,
-        1,
-        g_ppu_ppu_ppu_cop_key_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_key_fifo_prog_full_negate_cfg",
-        PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x6f4,
-        (32/8),
-        0,
-        0x5 + 1,
-        0,
-        16,
-        1,
-        g_ppu_ppu_ppu_cop_key_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_key_fifo_prog_empty_assert_cfg",
-        PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x6f8,
-        (32/8),
-        0,
-        0x5 + 1,
-        0,
-        16,
-        1,
-        g_ppu_ppu_ppu_cop_key_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_key_fifo_prog_empty_negate_cfg",
-        PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x6fc,
-        (32/8),
-        0,
-        0x5 + 1,
-        0,
-        16,
-        1,
-        g_ppu_ppu_ppu_cop_key_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_random_mod_para_fifo_prog_full_assert_cfg",
-        PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x750,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_random_mod_para_fifo_prog_full_negate_cfg",
-        PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x754,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg",
-        PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x758,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg",
-        PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x75c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_random_mod_result_fifo_prog_full_assert_cfg",
-        PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x760,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_random_mod_result_fifo_prog_full_negate_cfg",
-        PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x764,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg",
-        PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x768,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg",
-        PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x76c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_checksum_result_fifo_prog_full_assert_cfg",
-        PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x770,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_checksum_result_fifo_prog_full_negate_cfg",
-        PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x774,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_checksum_result_fifo_prog_empty_assert_cfg",
-        PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x778,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_checksum_result_fifo_prog_empty_negate_cfg",
-        PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x77c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_crc_first_para_fifo_prog_full_assert_cfg",
-        PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x780,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_crc_first_para_fifo_prog_full_negate_cfg",
-        PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x784,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg",
-        PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x788,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg",
-        PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x78c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_crc_bypass_delay_prog_full_assert_cfg",
-        PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x790,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_crc_bypass_delay_prog_full_negate_cfg",
-        PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x794,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_crc_bypass_delay_prog_empty_assert_cfg",
-        PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x798,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_crc_bypass_delay_prog_empty_negate_cfg",
-        PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x79c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_crc_second_para_fifo_prog_full_assert_cfg",
-        PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_crc_second_para_fifo_prog_full_negate_cfg",
-        PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg",
-        PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg",
-        PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg",
-        PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg",
-        PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg",
-        PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg",
-        PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_multiply_para_fifo_prog_full_assert_cfg",
-        PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_multiply_para_fifo_prog_full_negate_cfg",
-        PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_multiply_para_fifo_prog_empty_assert_cfg",
-        PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_multiply_para_fifo_prog_empty_negate_cfg",
-        PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg",
-        PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg",
-        PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg",
-        PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg",
-        PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "free_global_num_fwft_fifo_prog_full_assert_cfg",
-        PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_free_global_num_fwft_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "free_global_num_fwft_fifo_prog_full_negate_cfg",
-        PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_free_global_num_fwft_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "free_global_num_fwft_fifo_prog_empty_assert_cfg",
-        PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_free_global_num_fwft_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "free_global_num_fwft_fifo_prog_empty_negate_cfg",
-        PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_free_global_num_fwft_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg",
-        PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg",
-        PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg",
-        PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg",
-        PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data0",
-        PPU_PPU_PKT_DATA0r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x800,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data1",
-        PPU_PPU_PKT_DATA1r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x804,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data2",
-        PPU_PPU_PKT_DATA2r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x808,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data3",
-        PPU_PPU_PKT_DATA3r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x80c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data4",
-        PPU_PPU_PKT_DATA4r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x810,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data5",
-        PPU_PPU_PKT_DATA5r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x814,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data6",
-        PPU_PPU_PKT_DATA6r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x818,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data7",
-        PPU_PPU_PKT_DATA7r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x81c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data8",
-        PPU_PPU_PKT_DATA8r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x820,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data9",
-        PPU_PPU_PKT_DATA9r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x824,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data10",
-        PPU_PPU_PKT_DATA10r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x828,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data11",
-        PPU_PPU_PKT_DATA11r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x82c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data12",
-        PPU_PPU_PKT_DATA12r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x830,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data13",
-        PPU_PPU_PKT_DATA13r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x834,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data14",
-        PPU_PPU_PKT_DATA14r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x838,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data15",
-        PPU_PPU_PKT_DATA15r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x83c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data16",
-        PPU_PPU_PKT_DATA16r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x840,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data17",
-        PPU_PPU_PKT_DATA17r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x844,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data18",
-        PPU_PPU_PKT_DATA18r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x848,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data19",
-        PPU_PPU_PKT_DATA19r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x84c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data19_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data20",
-        PPU_PPU_PKT_DATA20r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x850,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data20_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data21",
-        PPU_PPU_PKT_DATA21r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x854,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data21_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data22",
-        PPU_PPU_PKT_DATA22r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x858,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data22_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data23",
-        PPU_PPU_PKT_DATA23r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x85c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data23_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data24",
-        PPU_PPU_PKT_DATA24r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x860,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data24_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data25",
-        PPU_PPU_PKT_DATA25r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x864,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data25_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data26",
-        PPU_PPU_PKT_DATA26r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x868,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data27",
-        PPU_PPU_PKT_DATA27r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x86c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data27_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data28",
-        PPU_PPU_PKT_DATA28r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x870,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data28_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data29",
-        PPU_PPU_PKT_DATA29r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x874,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data29_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data30",
-        PPU_PPU_PKT_DATA30r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x878,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data30_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data31",
-        PPU_PPU_PKT_DATA31r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x87c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data31_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data32",
-        PPU_PPU_PKT_DATA32r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x880,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data33",
-        PPU_PPU_PKT_DATA33r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x884,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data33_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data34",
-        PPU_PPU_PKT_DATA34r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x888,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data34_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data35",
-        PPU_PPU_PKT_DATA35r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x88c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data35_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data36",
-        PPU_PPU_PKT_DATA36r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x890,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data36_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data37",
-        PPU_PPU_PKT_DATA37r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x894,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data37_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data38",
-        PPU_PPU_PKT_DATA38r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x898,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data38_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data39",
-        PPU_PPU_PKT_DATA39r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x89c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data39_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data40",
-        PPU_PPU_PKT_DATA40r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data40_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data41",
-        PPU_PPU_PKT_DATA41r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data41_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data42",
-        PPU_PPU_PKT_DATA42r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data42_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data43",
-        PPU_PPU_PKT_DATA43r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data43_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data44",
-        PPU_PPU_PKT_DATA44r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data44_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data45",
-        PPU_PPU_PKT_DATA45r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data45_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data46",
-        PPU_PPU_PKT_DATA46r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data46_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data47",
-        PPU_PPU_PKT_DATA47r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data47_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data48",
-        PPU_PPU_PKT_DATA48r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data48_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data49",
-        PPU_PPU_PKT_DATA49r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data49_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data50",
-        PPU_PPU_PKT_DATA50r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data50_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data51",
-        PPU_PPU_PKT_DATA51r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data51_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data52",
-        PPU_PPU_PKT_DATA52r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data52_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data53",
-        PPU_PPU_PKT_DATA53r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data53_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data54",
-        PPU_PPU_PKT_DATA54r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data54_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data55",
-        PPU_PPU_PKT_DATA55r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data55_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data56",
-        PPU_PPU_PKT_DATA56r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data56_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data57",
-        PPU_PPU_PKT_DATA57r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data57_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data58",
-        PPU_PPU_PKT_DATA58r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data58_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data59",
-        PPU_PPU_PKT_DATA59r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data59_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data60",
-        PPU_PPU_PKT_DATA60r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data60_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data61",
-        PPU_PPU_PKT_DATA61r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data61_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data62",
-        PPU_PPU_PKT_DATA62r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data62_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data63",
-        PPU_PPU_PKT_DATA63r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data63_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data64",
-        PPU_PPU_PKT_DATA64r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x900,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data64_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data65",
-        PPU_PPU_PKT_DATA65r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x904,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data65_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data66",
-        PPU_PPU_PKT_DATA66r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x908,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data66_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data67",
-        PPU_PPU_PKT_DATA67r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x90c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data67_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data68",
-        PPU_PPU_PKT_DATA68r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x910,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data68_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data69",
-        PPU_PPU_PKT_DATA69r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x914,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data69_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data70",
-        PPU_PPU_PKT_DATA70r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x918,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data70_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data71",
-        PPU_PPU_PKT_DATA71r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x91c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data71_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data72",
-        PPU_PPU_PKT_DATA72r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x920,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data72_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data73",
-        PPU_PPU_PKT_DATA73r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x924,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data73_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data74",
-        PPU_PPU_PKT_DATA74r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x928,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data74_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data75",
-        PPU_PPU_PKT_DATA75r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x92c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data75_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data76",
-        PPU_PPU_PKT_DATA76r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x930,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data76_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data77",
-        PPU_PPU_PKT_DATA77r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x934,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data77_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data78",
-        PPU_PPU_PKT_DATA78r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x938,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data78_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data79",
-        PPU_PPU_PKT_DATA79r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x93c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data79_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data80",
-        PPU_PPU_PKT_DATA80r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x940,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data80_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data81",
-        PPU_PPU_PKT_DATA81r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x944,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data81_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data82",
-        PPU_PPU_PKT_DATA82r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x948,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data82_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data83",
-        PPU_PPU_PKT_DATA83r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x94c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data83_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data84",
-        PPU_PPU_PKT_DATA84r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x950,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data84_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data85",
-        PPU_PPU_PKT_DATA85r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x954,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data85_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data86",
-        PPU_PPU_PKT_DATA86r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x958,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data86_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data87",
-        PPU_PPU_PKT_DATA87r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x95c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data87_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data88",
-        PPU_PPU_PKT_DATA88r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x960,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data88_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data89",
-        PPU_PPU_PKT_DATA89r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x964,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data89_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data90",
-        PPU_PPU_PKT_DATA90r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x968,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data90_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data91",
-        PPU_PPU_PKT_DATA91r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x96c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data91_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data92",
-        PPU_PPU_PKT_DATA92r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x970,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data92_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data93",
-        PPU_PPU_PKT_DATA93r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x974,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data93_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data94",
-        PPU_PPU_PKT_DATA94r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x978,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data94_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data95",
-        PPU_PPU_PKT_DATA95r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x97c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data95_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data96",
-        PPU_PPU_PKT_DATA96r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x980,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data96_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data97",
-        PPU_PPU_PKT_DATA97r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x984,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data97_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data98",
-        PPU_PPU_PKT_DATA98r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x988,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data98_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data99",
-        PPU_PPU_PKT_DATA99r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x98c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data99_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data100",
-        PPU_PPU_PKT_DATA100r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x990,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data100_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data101",
-        PPU_PPU_PKT_DATA101r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x994,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data101_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data102",
-        PPU_PPU_PKT_DATA102r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x998,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data102_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data103",
-        PPU_PPU_PKT_DATA103r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x99c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data103_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data104",
-        PPU_PPU_PKT_DATA104r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data104_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data105",
-        PPU_PPU_PKT_DATA105r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data105_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data106",
-        PPU_PPU_PKT_DATA106r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data106_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data107",
-        PPU_PPU_PKT_DATA107r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data107_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data108",
-        PPU_PPU_PKT_DATA108r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data108_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data109",
-        PPU_PPU_PKT_DATA109r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data109_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data110",
-        PPU_PPU_PKT_DATA110r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data110_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data111",
-        PPU_PPU_PKT_DATA111r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data111_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data112",
-        PPU_PPU_PKT_DATA112r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data112_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data113",
-        PPU_PPU_PKT_DATA113r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data113_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data114",
-        PPU_PPU_PKT_DATA114r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data114_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data115",
-        PPU_PPU_PKT_DATA115r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data115_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data116",
-        PPU_PPU_PKT_DATA116r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data116_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data117",
-        PPU_PPU_PKT_DATA117r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data117_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data118",
-        PPU_PPU_PKT_DATA118r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data118_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data119",
-        PPU_PPU_PKT_DATA119r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data119_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data120",
-        PPU_PPU_PKT_DATA120r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data120_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data121",
-        PPU_PPU_PKT_DATA121r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data121_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data122",
-        PPU_PPU_PKT_DATA122r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data122_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data123",
-        PPU_PPU_PKT_DATA123r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data123_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data124",
-        PPU_PPU_PKT_DATA124r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data124_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data125",
-        PPU_PPU_PKT_DATA125r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data125_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data126",
-        PPU_PPU_PKT_DATA126r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data126_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pkt_data127",
-        PPU_PPU_PKT_DATA127r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_pkt_data127_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr0",
-        PPU_PPU_SPR0r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa00,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr1",
-        PPU_PPU_SPR1r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa04,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr2",
-        PPU_PPU_SPR2r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa08,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr3",
-        PPU_PPU_SPR3r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa0c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr4",
-        PPU_PPU_SPR4r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa10,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr5",
-        PPU_PPU_SPR5r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa14,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr6",
-        PPU_PPU_SPR6r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa18,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr7",
-        PPU_PPU_SPR7r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa1c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr8",
-        PPU_PPU_SPR8r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa20,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr9",
-        PPU_PPU_SPR9r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa24,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr10",
-        PPU_PPU_SPR10r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa28,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr11",
-        PPU_PPU_SPR11r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa2c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr12",
-        PPU_PPU_SPR12r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa30,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr13",
-        PPU_PPU_SPR13r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa34,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr14",
-        PPU_PPU_SPR14r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa38,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr15",
-        PPU_PPU_SPR15r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa3c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr16",
-        PPU_PPU_SPR16r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa40,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr17",
-        PPU_PPU_SPR17r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa44,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr18",
-        PPU_PPU_SPR18r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa48,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr19",
-        PPU_PPU_SPR19r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa4c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr19_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr20",
-        PPU_PPU_SPR20r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa50,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr20_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr21",
-        PPU_PPU_SPR21r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa54,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr21_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr22",
-        PPU_PPU_SPR22r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa58,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr22_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr23",
-        PPU_PPU_SPR23r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa5c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr23_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr24",
-        PPU_PPU_SPR24r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa60,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr24_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr25",
-        PPU_PPU_SPR25r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa64,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr25_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr26",
-        PPU_PPU_SPR26r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa68,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr27",
-        PPU_PPU_SPR27r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa6c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr27_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr28",
-        PPU_PPU_SPR28r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa70,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr28_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr29",
-        PPU_PPU_SPR29r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa74,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr29_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr30",
-        PPU_PPU_SPR30r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa78,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr30_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "spr31",
-        PPU_PPU_SPR31r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa7c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_spr31_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp0",
-        PPU_PPU_RSP0r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa80,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp1",
-        PPU_PPU_RSP1r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa84,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp2",
-        PPU_PPU_RSP2r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa88,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp3",
-        PPU_PPU_RSP3r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa8c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp4",
-        PPU_PPU_RSP4r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa90,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp5",
-        PPU_PPU_RSP5r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa94,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp6",
-        PPU_PPU_RSP6r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa98,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp7",
-        PPU_PPU_RSP7r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa9c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp8",
-        PPU_PPU_RSP8r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaa0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp9",
-        PPU_PPU_RSP9r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaa4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp10",
-        PPU_PPU_RSP10r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaa8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp11",
-        PPU_PPU_RSP11r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp12",
-        PPU_PPU_RSP12r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xab0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp13",
-        PPU_PPU_RSP13r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xab4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp14",
-        PPU_PPU_RSP14r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xab8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp15",
-        PPU_PPU_RSP15r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xabc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp16",
-        PPU_PPU_RSP16r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xac0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp17",
-        PPU_PPU_RSP17r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xac4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp18",
-        PPU_PPU_RSP18r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xac8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp19",
-        PPU_PPU_RSP19r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xacc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp19_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp20",
-        PPU_PPU_RSP20r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xad0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp20_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp21",
-        PPU_PPU_RSP21r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xad4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp21_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp22",
-        PPU_PPU_RSP22r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xad8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp22_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp23",
-        PPU_PPU_RSP23r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xadc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp23_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp24",
-        PPU_PPU_RSP24r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xae0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp24_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp25",
-        PPU_PPU_RSP25r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xae4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp25_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp26",
-        PPU_PPU_RSP26r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xae8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp27",
-        PPU_PPU_RSP27r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp27_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp28",
-        PPU_PPU_RSP28r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaf0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp28_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp29",
-        PPU_PPU_RSP29r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaf4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp29_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp30",
-        PPU_PPU_RSP30r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaf8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp30_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsp31",
-        PPU_PPU_RSP31r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xafc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_rsp31_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key0",
-        PPU_PPU_KEY0r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb00,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key1",
-        PPU_PPU_KEY1r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb04,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key2",
-        PPU_PPU_KEY2r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb08,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key3",
-        PPU_PPU_KEY3r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb0c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key4",
-        PPU_PPU_KEY4r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb10,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key5",
-        PPU_PPU_KEY5r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb14,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key6",
-        PPU_PPU_KEY6r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb18,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key7",
-        PPU_PPU_KEY7r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb1c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key8",
-        PPU_PPU_KEY8r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb20,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key9",
-        PPU_PPU_KEY9r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb24,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key10",
-        PPU_PPU_KEY10r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb28,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key11",
-        PPU_PPU_KEY11r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb2c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key12",
-        PPU_PPU_KEY12r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb30,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key13",
-        PPU_PPU_KEY13r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb34,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key14",
-        PPU_PPU_KEY14r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb38,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key15",
-        PPU_PPU_KEY15r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb3c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key16",
-        PPU_PPU_KEY16r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb40,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key17",
-        PPU_PPU_KEY17r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb44,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key18",
-        PPU_PPU_KEY18r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb48,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "key19",
-        PPU_PPU_KEY19r,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb4c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ppu_ppu_key19_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "flag",
-        PPU_PPU_FLAGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb50,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_ppu_ppu_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_1200m_flag",
-        PPU_CLUSTER_INT_1200M_FLAGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x00,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        8,
-        g_ppu_cluster_int_1200m_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "bp_instr_l",
-        PPU_CLUSTER_BP_INSTR_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x04,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_bp_instr_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "bp_instr_h",
-        PPU_CLUSTER_BP_INSTR_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x08,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_bp_instr_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "bp_addr",
-        PPU_CLUSTER_BP_ADDRr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x0c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0x7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        4,
-        1,
-        g_ppu_cluster_bp_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "drr",
-        PPU_CLUSTER_DRRr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0x7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        4,
-        1,
-        g_ppu_cluster_drr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dsr",
-        PPU_CLUSTER_DSRr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_dsr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dbg_rtl_date",
-        PPU_CLUSTER_DBG_RTL_DATEr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x50,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_dbg_rtl_date_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_continue",
-        PPU_CLUSTER_ME_CONTINUEr,
-        PPU,
-        DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x80,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_me_continue_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_step",
-        PPU_CLUSTER_ME_STEPr,
-        PPU,
-        DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x84,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_me_step_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_refresh",
-        PPU_CLUSTER_ME_REFRESHr,
-        PPU,
-        DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x88,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_me_refresh_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "drr_clr",
-        PPU_CLUSTER_DRR_CLRr,
-        PPU,
-        DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x8c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_drr_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_busy_thresold",
-        PPU_CLUSTER_ME_BUSY_THRESOLDr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x90,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_me_busy_thresold_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_1200m_sta",
-        PPU_CLUSTER_INT_1200M_STAr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x94,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        8,
-        g_ppu_cluster_int_1200m_sta_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_1200m_me_fifo_mask_l",
-        PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc0,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0x7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        4,
-        32,
-        g_ppu_cluster_int_1200m_me_fifo_mask_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_1200m_me_fifo_mask_h",
-        PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xe0,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0x7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        4,
-        2,
-        g_ppu_cluster_int_1200m_me_fifo_mask_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_fifo_interrupt_flag_l",
-        PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x100,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0x7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        4,
-        32,
-        g_ppu_cluster_me_fifo_interrupt_flag_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_fifo_interrupt_flag_h",
-        PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x120,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0x7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        4,
-        2,
-        g_ppu_cluster_me_fifo_interrupt_flag_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_fifo_interrupt_sta_l",
-        PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x140,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0x7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        4,
-        32,
-        g_ppu_cluster_me_fifo_interrupt_sta_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_fifo_interrupt_sta_h",
-        PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x160,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0x7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        4,
-        2,
-        g_ppu_cluster_me_fifo_interrupt_sta_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_1200m_cluster_mex_fifo_mask_l",
-        PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x800,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        32,
-        g_ppu_cluster_int_1200m_cluster_mex_fifo_mask_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_1200m_cluster_mex_fifo_mask_h",
-        PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x804,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        19,
-        g_ppu_cluster_int_1200m_cluster_mex_fifo_mask_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_1200m_cluster_mex_fifo_flag_l",
-        PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x808,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        32,
-        g_ppu_cluster_int_1200m_cluster_mex_fifo_flag_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_1200m_cluster_mex_fifo_flag_h",
-        PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x80c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        19,
-        g_ppu_cluster_int_1200m_cluster_mex_fifo_flag_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_1200m_cluster_mex_fifo_stat_l",
-        PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x810,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        32,
-        g_ppu_cluster_int_1200m_cluster_mex_fifo_stat_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_1200m_cluster_mex_fifo_stat_h",
-        PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x814,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        19,
-        g_ppu_cluster_int_1200m_cluster_mex_fifo_stat_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_statics_wb_exception_cfg",
-        PPU_CLUSTER_PPU_STATICS_WB_EXCEPTION_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x824,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        6,
-        g_ppu_cluster_ppu_statics_wb_exception_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "thread_switch_en",
-        PPU_CLUSTER_THREAD_SWITCH_ENr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x8c0,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_thread_switch_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "is_me_not_idle",
-        PPU_CLUSTER_IS_ME_NOT_IDLEr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x8c4,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        8,
-        g_ppu_cluster_is_me_not_idle_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cluster_mf_in_afifo_prog_empty_assert_cfg",
-        PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc00,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cluster_mf_in_afifo_prog_empty_negate_cfg",
-        PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc04,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ese_rsp_afifo_prog_empty_assert_cfg",
-        PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc08,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ese_rsp_afifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ese_rsp_afifo_prog_empty_negate_cfg",
-        PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc0c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ese_rsp_afifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ise_rsp_afifo_prog_empty_assert_cfg",
-        PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc10,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ise_rsp_afifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ise_rsp_afifo_prog_empty_negate_cfg",
-        PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc14,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ise_rsp_afifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg",
-        PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc18,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg",
-        PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc1c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg",
-        PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc20,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg",
-        PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc24,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg",
-        PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc28,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg",
-        PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc2c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg",
-        PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc30,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg",
-        PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc34,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sta_rsp_afifo_prog_empty_assert_cfg",
-        PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc38,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_sta_rsp_afifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sta_rsp_afifo_prog_empty_negate_cfg",
-        PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc3c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_sta_rsp_afifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg",
-        PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc40,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg",
-        PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc44,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg",
-        PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc48,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg",
-        PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc4c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cop_rsp_fifo_prog_full_assert_cfg",
-        PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc50,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_cop_rsp_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cop_rsp_fifo_prog_full_negate_cfg",
-        PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc54,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_cop_rsp_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cop_rsp_fifo_prog_empty_assert_cfg",
-        PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc58,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_cop_rsp_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cop_rsp_fifo_prog_empty_negate_cfg",
-        PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc5c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_cop_rsp_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mcode_pf_rsp_fifo_prog_full_assert_cfg",
-        PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc60,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_mcode_pf_rsp_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mcode_pf_rsp_fifo_prog_full_negate_cfg",
-        PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc64,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_mcode_pf_rsp_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mcode_pf_rsp_fifo_prog_empty_assert_cfg",
-        PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc68,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mcode_pf_rsp_fifo_prog_empty_negate_cfg",
-        PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc6c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg",
-        PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc70,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg",
-        PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc74,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg",
-        PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc78,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg",
-        PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc7c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_ise_key_afifo_prog_full_assert_cfg",
-        PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc80,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_ise_key_afifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_ise_key_afifo_prog_full_negate_cfg",
-        PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc84,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_ise_key_afifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_ese_key_afifo_prog_full_assert_cfg",
-        PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc88,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_ese_key_afifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_ese_key_afifo_prog_full_negate_cfg",
-        PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc8c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_ese_key_afifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_sta_key_afifo_prog_full_assert_cfg",
-        PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc90,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_sta_key_afifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_sta_key_afifo_prog_full_negate_cfg",
-        PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc94,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_sta_key_afifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_600m_cluster_mex_fifo_mask",
-        PPU_CLUSTER_INT_600M_CLUSTER_MEX_FIFO_MASKr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4034,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        7,
-        g_ppu_cluster_int_600m_cluster_mex_fifo_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cluster_mex_fifo_600m_interrupt_flag",
-        PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_FLAGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4038,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        7,
-        g_ppu_cluster_cluster_mex_fifo_600m_interrupt_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cluster_mex_fifo_600m_interrupt_sta",
-        PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_STAr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x403c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        7,
-        g_ppu_cluster_cluster_mex_fifo_600m_interrupt_sta_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex_cnt_cfg",
-        PPU_CLUSTER_MEX_CNT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4050,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        2,
-        g_ppu_cluster_mex_cnt_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_600m_cluster_mex_ram_ecc_error_interrupt_mask",
-        PPU_CLUSTER_INT_600M_CLUSTER_MEX_RAM_ECC_ERROR_INTERRUPT_MASKr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4064,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        6,
-        g_ppu_cluster_int_600m_cluster_mex_ram_ecc_error_interrupt_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cluster_mex_ram_600m_ecc_error_interrupt_flag",
-        PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_FLAGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4068,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        6,
-        g_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cluster_mex_ram_600m_ecc_error_interrupt_sta",
-        PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_STAr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x406c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        6,
-        g_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_sta_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cluster_mf_in_afifo_prog_full_assert_cfg",
-        PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4400,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cluster_mf_in_afifo_prog_full_negate_cfg",
-        PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4410,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ese_rsp_afifo_prog_full_assert_cfg",
-        PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4420,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ese_rsp_afifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ese_rsp_afifo_prog_full_negate_cfg",
-        PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4430,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ese_rsp_afifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ise_rsp_afifo_prog_full_assert_cfg",
-        PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4440,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ise_rsp_afifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ise_rsp_afifo_prog_full_negate_cfg",
-        PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4450,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ise_rsp_afifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sta_rsp_afifo_prog_full_assert_cfg",
-        PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4460,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_sta_rsp_afifo_prog_full_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sta_rsp_afifo_prog_full_negate_cfg",
-        PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4470,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_sta_rsp_afifo_prog_full_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_ise_key_afifo_prog_empty_assert_cfg",
-        PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4480,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_ise_key_afifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_ise_key_afifo_prog_empty_negate_cfg",
-        PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4490,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_ise_key_afifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_ese_key_afifo_prog_empty_assert_cfg",
-        PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x44a0,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_ese_key_afifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_ese_key_afifo_prog_empty_negate_cfg",
-        PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x44b0,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_ese_key_afifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_sta_key_afifo_prog_empty_assert_cfg",
-        PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x44c0,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_sta_key_afifo_prog_empty_assert_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_sta_key_afifo_prog_empty_negate_cfg",
-        PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x44d0,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_sta_key_afifo_prog_empty_negate_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cluster_mf_vld_cnt_h",
-        PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6000,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_cluster_mf_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_cluster_mf_vld_cnt_l",
-        PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6004,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ppu_cluster_mf_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cluster_ise_key_out_vld_cnt",
-        PPU_CLUSTER_CLUSTER_ISE_KEY_OUT_VLD_CNTr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6008,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_cluster_ise_key_out_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ise_cluster_rsp_in_vld_cnt",
-        PPU_CLUSTER_ISE_CLUSTER_RSP_IN_VLD_CNTr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x600c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ise_cluster_rsp_in_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cluster_ese_key_out_vld_cnt",
-        PPU_CLUSTER_CLUSTER_ESE_KEY_OUT_VLD_CNTr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6010,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_cluster_ese_key_out_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ese_cluster_rsp_in_vld_cnt",
-        PPU_CLUSTER_ESE_CLUSTER_RSP_IN_VLD_CNTr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6014,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ese_cluster_rsp_in_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cluster_stat_cmd_vld_cnt",
-        PPU_CLUSTER_CLUSTER_STAT_CMD_VLD_CNTr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6018,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_cluster_stat_cmd_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_cluster_rsp_vld_cnt",
-        PPU_CLUSTER_STAT_CLUSTER_RSP_VLD_CNTr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x601c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_stat_cluster_rsp_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex_debug_key_vld_cnt",
-        PPU_CLUSTER_MEX_DEBUG_KEY_VLD_CNTr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6020,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_mex_debug_key_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ise_cluster_key_fc_cnt",
-        PPU_CLUSTER_ISE_CLUSTER_KEY_FC_CNTr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6024,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ise_cluster_key_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ese_cluster_key_fc_cnt",
-        PPU_CLUSTER_ESE_CLUSTER_KEY_FC_CNTr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6028,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_ese_cluster_key_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cluster_ise_rsp_fc_cnt",
-        PPU_CLUSTER_CLUSTER_ISE_RSP_FC_CNTr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x602c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_cluster_ise_rsp_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cluster_ese_rsp_fc_cnt",
-        PPU_CLUSTER_CLUSTER_ESE_RSP_FC_CNTr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6030,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_cluster_ese_rsp_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_cluster_cmd_fc_cnt",
-        PPU_CLUSTER_STAT_CLUSTER_CMD_FC_CNTr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6034,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_stat_cluster_cmd_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cluster_stat_rsp_fc_cnt",
-        PPU_CLUSTER_CLUSTER_STAT_RSP_FC_CNTr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6038,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_cluster_stat_rsp_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cluster_ppu_mf_vld_cnt_l",
-        PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2000,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_cluster_ppu_mf_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cluster_ppu_mf_vld_cnt_h",
-        PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2004,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_cluster_ppu_mf_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cluster_cop_key_vld_cnt_l",
-        PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2008,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_cluster_cop_key_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cluster_cop_key_vld_cnt_h",
-        PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x200c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_cluster_cop_key_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cop_cluster_rsp_vld_cnt_l",
-        PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2010,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_cop_cluster_rsp_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cop_cluster_rsp_vld_cnt_h",
-        PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2014,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        0,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        0,
-        1,
-        g_ppu_cluster_cop_cluster_rsp_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex_me_pkt_in_sop_cnt_l",
-        PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2018,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_mex_me_pkt_in_sop_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex_me_pkt_in_sop_cnt_h",
-        PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x201c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_mex_me_pkt_in_sop_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex_me_pkt_in_eop_cnt_l",
-        PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2020,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_mex_me_pkt_in_eop_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex_me_pkt_in_eop_cnt_h",
-        PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2024,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_mex_me_pkt_in_eop_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex_me_pkt_in_vld_cnt_l",
-        PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2028,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_mex_me_pkt_in_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex_me_pkt_in_vld_cnt_h",
-        PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x202c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_mex_me_pkt_in_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_pkt_out_sop_cnt_l",
-        PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20d8,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_pkt_out_sop_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_pkt_out_sop_cnt_h",
-        PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20dc,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_pkt_out_sop_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_pkt_out_eop_cnt_l",
-        PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20e0,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_pkt_out_eop_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_pkt_out_eop_cnt_h",
-        PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20e4,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_pkt_out_eop_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_pkt_out_vld_cnt_l",
-        PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20e8,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_pkt_out_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_pkt_out_vld_cnt_h",
-        PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20ec,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_pkt_out_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_i_key_out_sop_cnt_l",
-        PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2198,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_i_key_out_sop_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_i_key_out_sop_cnt_h",
-        PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x219c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_i_key_out_sop_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_i_key_out_eop_cnt_l",
-        PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x21a0,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_i_key_out_eop_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_i_key_out_eop_cnt_h",
-        PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x21a4,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_i_key_out_eop_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_i_key_out_vld_cnt_l",
-        PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x21a8,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_i_key_out_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_i_key_out_vld_cnt_h",
-        PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x21ac,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_i_key_out_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_e_key_out_sop_cnt_l",
-        PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2258,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_e_key_out_sop_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_e_key_out_sop_cnt_h",
-        PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x225c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_e_key_out_sop_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_e_key_out_eop_cnt_l",
-        PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2260,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_e_key_out_eop_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_e_key_out_eop_cnt_h",
-        PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2264,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_e_key_out_eop_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_e_key_out_vld_cnt_l",
-        PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2268,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_e_key_out_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_e_key_out_vld_cnt_h",
-        PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x226c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_mex_e_key_out_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_demux_ise_key_vld_cnt_l",
-        PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2318,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        8,
-        1,
-        g_ppu_cluster_me_mex_demux_ise_key_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_demux_ise_key_vld_cnt_h",
-        PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x231c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        8,
-        1,
-        g_ppu_cluster_me_mex_demux_ise_key_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_demux_ese_key_vld_cnt_l",
-        PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2358,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        8,
-        1,
-        g_ppu_cluster_me_mex_demux_ese_key_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_demux_ese_key_vld_cnt_h",
-        PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x235c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        8,
-        1,
-        g_ppu_cluster_me_mex_demux_ese_key_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_demux_sta_key_vld_cnt_l",
-        PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2398,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        8,
-        1,
-        g_ppu_cluster_me_mex_demux_sta_key_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_demux_sta_key_vld_cnt_h",
-        PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x239c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        8,
-        1,
-        g_ppu_cluster_me_mex_demux_sta_key_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_demux_cop_key_vld_cnt_l",
-        PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x23d8,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        8,
-        1,
-        g_ppu_cluster_me_mex_demux_cop_key_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_mex_demux_cop_key_vld_cnt_h",
-        PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x23dc,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        8,
-        1,
-        g_ppu_cluster_me_mex_demux_cop_key_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex_me_demux_ise_rsp_vld_cnt_l",
-        PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2418,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        8,
-        1,
-        g_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex_me_demux_ise_rsp_vld_cnt_h",
-        PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x241c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        8,
-        1,
-        g_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex_me_demux_ese_rsp_vld_cnt_l",
-        PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2458,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        8,
-        1,
-        g_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex_me_demux_ese_rsp_vld_cnt_h",
-        PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x245c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        8,
-        1,
-        g_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex_me_demux_sta_rsp_vld_cnt_l",
-        PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2498,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        8,
-        1,
-        g_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex_me_demux_sta_rsp_vld_cnt_h",
-        PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x249c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        8,
-        1,
-        g_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex_me_demux_cop_rsp_vld_cnt_l",
-        PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x24d8,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        8,
-        1,
-        g_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex_me_demux_cop_rsp_vld_cnt_h",
-        PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x24dc,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        8,
-        1,
-        g_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_exception_code0_cnt_l",
-        PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2518,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_exception_code0_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_exception_code0_cnt_h",
-        PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x251c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_exception_code0_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_exception_code1_cnt_l",
-        PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2520,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_exception_code1_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_exception_code1_cnt_h",
-        PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2524,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_exception_code1_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_exception_code2_cnt_l",
-        PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2528,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_exception_code2_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_exception_code2_cnt_h",
-        PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x252c,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_exception_code2_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_exception_code3_cnt_l",
-        PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25d8,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_exception_code3_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_exception_code3_cnt_h",
-        PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25dc,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_exception_code3_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_exception_code4_cnt_l",
-        PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25e0,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_exception_code4_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_exception_code4_cnt_h",
-        PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25e4,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_exception_code4_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_exception_code5_cnt_l",
-        PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_Lr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25e8,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_exception_code5_cnt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "me_exception_code5_cnt_h",
-        PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_Hr,
-        PPU,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25ec,
-        (32/8),
-        DPP_PPU_CLUSTER_NUM,
-        7 + 1,
-        DPP_PPU_CLUSTER_SPACE_SIZE,
-        24,
-        1,
-        g_ppu_cluster_me_exception_code5_cnt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_soft_rst",
-        SE_CFG_PPU_SOFT_RSTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_ppu_soft_rst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ept_flag",
-        SE_CFG_EPT_FLAGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_ept_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_key_lk0_3",
-        SE_CFG_DDR_KEY_LK0_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_ddr_key_lk0_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_key_lk0_2",
-        SE_CFG_DDR_KEY_LK0_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_ddr_key_lk0_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_key_lk0_1",
-        SE_CFG_DDR_KEY_LK0_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_ddr_key_lk0_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_key_lk0_0",
-        SE_CFG_DDR_KEY_LK0_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000002c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_ddr_key_lk0_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_key_lk1_3",
-        SE_CFG_DDR_KEY_LK1_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_ddr_key_lk1_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_key_lk1_2",
-        SE_CFG_DDR_KEY_LK1_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_ddr_key_lk1_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_key_lk1_1",
-        SE_CFG_DDR_KEY_LK1_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_ddr_key_lk1_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_key_lk1_0",
-        SE_CFG_DDR_KEY_LK1_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000003c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_ddr_key_lk1_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_18",
-        SE_CFG_HASH_KEY_LK0_18r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_17",
-        SE_CFG_HASH_KEY_LK0_17r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_16",
-        SE_CFG_HASH_KEY_LK0_16r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_15",
-        SE_CFG_HASH_KEY_LK0_15r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000008c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_14",
-        SE_CFG_HASH_KEY_LK0_14r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_13",
-        SE_CFG_HASH_KEY_LK0_13r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_12",
-        SE_CFG_HASH_KEY_LK0_12r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000098,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_11",
-        SE_CFG_HASH_KEY_LK0_11r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000009c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_10",
-        SE_CFG_HASH_KEY_LK0_10r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_9",
-        SE_CFG_HASH_KEY_LK0_9r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_8",
-        SE_CFG_HASH_KEY_LK0_8r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_7",
-        SE_CFG_HASH_KEY_LK0_7r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_6",
-        SE_CFG_HASH_KEY_LK0_6r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_5",
-        SE_CFG_HASH_KEY_LK0_5r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_4",
-        SE_CFG_HASH_KEY_LK0_4r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_3",
-        SE_CFG_HASH_KEY_LK0_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_2",
-        SE_CFG_HASH_KEY_LK0_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_1",
-        SE_CFG_HASH_KEY_LK0_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk0_0",
-        SE_CFG_HASH_KEY_LK0_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk0_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_18",
-        SE_CFG_HASH_KEY_LK1_18r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_17",
-        SE_CFG_HASH_KEY_LK1_17r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_16",
-        SE_CFG_HASH_KEY_LK1_16r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_15",
-        SE_CFG_HASH_KEY_LK1_15r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_14",
-        SE_CFG_HASH_KEY_LK1_14r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_13",
-        SE_CFG_HASH_KEY_LK1_13r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_12",
-        SE_CFG_HASH_KEY_LK1_12r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_11",
-        SE_CFG_HASH_KEY_LK1_11r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_10",
-        SE_CFG_HASH_KEY_LK1_10r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_9",
-        SE_CFG_HASH_KEY_LK1_9r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_8",
-        SE_CFG_HASH_KEY_LK1_8r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_7",
-        SE_CFG_HASH_KEY_LK1_7r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_6",
-        SE_CFG_HASH_KEY_LK1_6r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_5",
-        SE_CFG_HASH_KEY_LK1_5r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000100,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_4",
-        SE_CFG_HASH_KEY_LK1_4r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000104,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_3",
-        SE_CFG_HASH_KEY_LK1_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000108,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_2",
-        SE_CFG_HASH_KEY_LK1_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000010c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_1",
-        SE_CFG_HASH_KEY_LK1_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000110,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk1_0",
-        SE_CFG_HASH_KEY_LK1_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000114,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk1_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_18",
-        SE_CFG_HASH_KEY_LK2_18r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000118,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_17",
-        SE_CFG_HASH_KEY_LK2_17r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000011c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_16",
-        SE_CFG_HASH_KEY_LK2_16r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000120,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_15",
-        SE_CFG_HASH_KEY_LK2_15r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000124,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_14",
-        SE_CFG_HASH_KEY_LK2_14r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000128,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_13",
-        SE_CFG_HASH_KEY_LK2_13r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000012c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_12",
-        SE_CFG_HASH_KEY_LK2_12r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000130,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_11",
-        SE_CFG_HASH_KEY_LK2_11r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000134,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_10",
-        SE_CFG_HASH_KEY_LK2_10r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000138,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_9",
-        SE_CFG_HASH_KEY_LK2_9r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000013c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_8",
-        SE_CFG_HASH_KEY_LK2_8r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000140,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_7",
-        SE_CFG_HASH_KEY_LK2_7r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000144,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_6",
-        SE_CFG_HASH_KEY_LK2_6r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000148,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_5",
-        SE_CFG_HASH_KEY_LK2_5r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000014c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_4",
-        SE_CFG_HASH_KEY_LK2_4r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000150,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_3",
-        SE_CFG_HASH_KEY_LK2_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000154,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_2",
-        SE_CFG_HASH_KEY_LK2_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000158,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_1",
-        SE_CFG_HASH_KEY_LK2_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000015c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk2_0",
-        SE_CFG_HASH_KEY_LK2_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000160,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk2_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_18",
-        SE_CFG_HASH_KEY_LK3_18r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000164,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_17",
-        SE_CFG_HASH_KEY_LK3_17r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000168,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_16",
-        SE_CFG_HASH_KEY_LK3_16r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000016c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_15",
-        SE_CFG_HASH_KEY_LK3_15r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000170,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_14",
-        SE_CFG_HASH_KEY_LK3_14r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000174,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_13",
-        SE_CFG_HASH_KEY_LK3_13r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000178,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_12",
-        SE_CFG_HASH_KEY_LK3_12r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000017c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_11",
-        SE_CFG_HASH_KEY_LK3_11r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000180,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_10",
-        SE_CFG_HASH_KEY_LK3_10r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000184,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_9",
-        SE_CFG_HASH_KEY_LK3_9r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000188,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_8",
-        SE_CFG_HASH_KEY_LK3_8r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000018c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_7",
-        SE_CFG_HASH_KEY_LK3_7r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000190,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_6",
-        SE_CFG_HASH_KEY_LK3_6r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000194,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_5",
-        SE_CFG_HASH_KEY_LK3_5r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000198,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_4",
-        SE_CFG_HASH_KEY_LK3_4r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000019c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_3",
-        SE_CFG_HASH_KEY_LK3_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000001a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_2",
-        SE_CFG_HASH_KEY_LK3_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000001a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_1",
-        SE_CFG_HASH_KEY_LK3_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000001a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key_lk3_0",
-        SE_CFG_HASH_KEY_LK3_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000001ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_hash_key_lk3_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk0_6",
-        SE_CFG_LPM_KEY_LK0_6r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk0_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk0_5",
-        SE_CFG_LPM_KEY_LK0_5r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk0_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk0_4",
-        SE_CFG_LPM_KEY_LK0_4r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk0_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk0_3",
-        SE_CFG_LPM_KEY_LK0_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk0_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk0_2",
-        SE_CFG_LPM_KEY_LK0_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk0_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk0_1",
-        SE_CFG_LPM_KEY_LK0_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk0_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk0_0",
-        SE_CFG_LPM_KEY_LK0_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk0_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk1_6",
-        SE_CFG_LPM_KEY_LK1_6r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk1_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk1_5",
-        SE_CFG_LPM_KEY_LK1_5r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000300,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk1_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk1_4",
-        SE_CFG_LPM_KEY_LK1_4r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000304,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk1_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk1_3",
-        SE_CFG_LPM_KEY_LK1_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000308,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk1_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk1_2",
-        SE_CFG_LPM_KEY_LK1_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000030c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk1_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk1_1",
-        SE_CFG_LPM_KEY_LK1_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000310,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk1_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk1_0",
-        SE_CFG_LPM_KEY_LK1_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000314,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk1_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk2_6",
-        SE_CFG_LPM_KEY_LK2_6r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000318,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk2_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk2_5",
-        SE_CFG_LPM_KEY_LK2_5r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000031c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk2_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk2_4",
-        SE_CFG_LPM_KEY_LK2_4r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000320,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk2_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk2_3",
-        SE_CFG_LPM_KEY_LK2_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000324,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk2_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk2_2",
-        SE_CFG_LPM_KEY_LK2_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000328,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk2_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk2_1",
-        SE_CFG_LPM_KEY_LK2_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000032c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk2_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk2_0",
-        SE_CFG_LPM_KEY_LK2_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000330,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk2_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk3_6",
-        SE_CFG_LPM_KEY_LK3_6r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000334,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk3_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk3_5",
-        SE_CFG_LPM_KEY_LK3_5r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000338,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk3_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk3_4",
-        SE_CFG_LPM_KEY_LK3_4r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000033c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk3_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk3_3",
-        SE_CFG_LPM_KEY_LK3_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000340,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk3_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk3_2",
-        SE_CFG_LPM_KEY_LK3_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000344,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk3_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk3_1",
-        SE_CFG_LPM_KEY_LK3_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000348,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk3_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_key_lk3_0",
-        SE_CFG_LPM_KEY_LK3_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000034c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_lpm_key_lk3_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_22",
-        SE_CFG_ETCAM_KEY_LK0_22r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_22_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_21",
-        SE_CFG_ETCAM_KEY_LK0_21r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_21_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_20",
-        SE_CFG_ETCAM_KEY_LK0_20r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_20_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_19",
-        SE_CFG_ETCAM_KEY_LK0_19r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_19_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_18",
-        SE_CFG_ETCAM_KEY_LK0_18r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_17",
-        SE_CFG_ETCAM_KEY_LK0_17r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_16",
-        SE_CFG_ETCAM_KEY_LK0_16r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_15",
-        SE_CFG_ETCAM_KEY_LK0_15r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_14",
-        SE_CFG_ETCAM_KEY_LK0_14r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_13",
-        SE_CFG_ETCAM_KEY_LK0_13r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_12",
-        SE_CFG_ETCAM_KEY_LK0_12r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_11",
-        SE_CFG_ETCAM_KEY_LK0_11r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_10",
-        SE_CFG_ETCAM_KEY_LK0_10r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_9",
-        SE_CFG_ETCAM_KEY_LK0_9r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_8",
-        SE_CFG_ETCAM_KEY_LK0_8r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_7",
-        SE_CFG_ETCAM_KEY_LK0_7r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_6",
-        SE_CFG_ETCAM_KEY_LK0_6r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000400,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_5",
-        SE_CFG_ETCAM_KEY_LK0_5r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000404,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_4",
-        SE_CFG_ETCAM_KEY_LK0_4r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000408,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_3",
-        SE_CFG_ETCAM_KEY_LK0_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000040c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_2",
-        SE_CFG_ETCAM_KEY_LK0_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000410,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_1",
-        SE_CFG_ETCAM_KEY_LK0_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000414,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk0_0",
-        SE_CFG_ETCAM_KEY_LK0_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000418,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk0_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_22",
-        SE_CFG_ETCAM_KEY_LK1_22r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000041c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_22_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_21",
-        SE_CFG_ETCAM_KEY_LK1_21r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000420,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_21_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_20",
-        SE_CFG_ETCAM_KEY_LK1_20r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000424,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_20_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_19",
-        SE_CFG_ETCAM_KEY_LK1_19r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000428,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_19_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_18",
-        SE_CFG_ETCAM_KEY_LK1_18r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000042c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_17",
-        SE_CFG_ETCAM_KEY_LK1_17r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000430,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_16",
-        SE_CFG_ETCAM_KEY_LK1_16r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000434,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_15",
-        SE_CFG_ETCAM_KEY_LK1_15r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000438,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_14",
-        SE_CFG_ETCAM_KEY_LK1_14r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000043c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_13",
-        SE_CFG_ETCAM_KEY_LK1_13r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000440,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_12",
-        SE_CFG_ETCAM_KEY_LK1_12r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000444,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_11",
-        SE_CFG_ETCAM_KEY_LK1_11r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000448,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_10",
-        SE_CFG_ETCAM_KEY_LK1_10r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000044c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_9",
-        SE_CFG_ETCAM_KEY_LK1_9r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000450,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_8",
-        SE_CFG_ETCAM_KEY_LK1_8r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000454,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_7",
-        SE_CFG_ETCAM_KEY_LK1_7r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000458,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_6",
-        SE_CFG_ETCAM_KEY_LK1_6r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000045c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_5",
-        SE_CFG_ETCAM_KEY_LK1_5r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000460,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_4",
-        SE_CFG_ETCAM_KEY_LK1_4r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000464,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_3",
-        SE_CFG_ETCAM_KEY_LK1_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000468,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_2",
-        SE_CFG_ETCAM_KEY_LK1_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000046c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_1",
-        SE_CFG_ETCAM_KEY_LK1_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000470,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk1_0",
-        SE_CFG_ETCAM_KEY_LK1_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000474,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk1_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_22",
-        SE_CFG_ETCAM_KEY_LK2_22r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000478,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_22_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_21",
-        SE_CFG_ETCAM_KEY_LK2_21r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000047c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_21_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_20",
-        SE_CFG_ETCAM_KEY_LK2_20r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000480,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_20_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_19",
-        SE_CFG_ETCAM_KEY_LK2_19r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000484,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_19_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_18",
-        SE_CFG_ETCAM_KEY_LK2_18r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000488,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_17",
-        SE_CFG_ETCAM_KEY_LK2_17r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000048c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_16",
-        SE_CFG_ETCAM_KEY_LK2_16r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000490,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_15",
-        SE_CFG_ETCAM_KEY_LK2_15r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000494,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_14",
-        SE_CFG_ETCAM_KEY_LK2_14r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000498,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_13",
-        SE_CFG_ETCAM_KEY_LK2_13r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000049c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_12",
-        SE_CFG_ETCAM_KEY_LK2_12r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_11",
-        SE_CFG_ETCAM_KEY_LK2_11r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_10",
-        SE_CFG_ETCAM_KEY_LK2_10r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_9",
-        SE_CFG_ETCAM_KEY_LK2_9r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_8",
-        SE_CFG_ETCAM_KEY_LK2_8r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_7",
-        SE_CFG_ETCAM_KEY_LK2_7r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_6",
-        SE_CFG_ETCAM_KEY_LK2_6r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_5",
-        SE_CFG_ETCAM_KEY_LK2_5r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_4",
-        SE_CFG_ETCAM_KEY_LK2_4r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_3",
-        SE_CFG_ETCAM_KEY_LK2_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_2",
-        SE_CFG_ETCAM_KEY_LK2_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_1",
-        SE_CFG_ETCAM_KEY_LK2_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk2_0",
-        SE_CFG_ETCAM_KEY_LK2_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk2_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_22",
-        SE_CFG_ETCAM_KEY_LK3_22r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_22_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_21",
-        SE_CFG_ETCAM_KEY_LK3_21r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_21_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_20",
-        SE_CFG_ETCAM_KEY_LK3_20r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_20_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_19",
-        SE_CFG_ETCAM_KEY_LK3_19r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_19_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_18",
-        SE_CFG_ETCAM_KEY_LK3_18r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_17",
-        SE_CFG_ETCAM_KEY_LK3_17r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_16",
-        SE_CFG_ETCAM_KEY_LK3_16r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_15",
-        SE_CFG_ETCAM_KEY_LK3_15r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_14",
-        SE_CFG_ETCAM_KEY_LK3_14r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_13",
-        SE_CFG_ETCAM_KEY_LK3_13r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_12",
-        SE_CFG_ETCAM_KEY_LK3_12r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_11",
-        SE_CFG_ETCAM_KEY_LK3_11r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000500,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_10",
-        SE_CFG_ETCAM_KEY_LK3_10r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000504,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_9",
-        SE_CFG_ETCAM_KEY_LK3_9r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000508,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_8",
-        SE_CFG_ETCAM_KEY_LK3_8r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000050c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_7",
-        SE_CFG_ETCAM_KEY_LK3_7r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000510,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_6",
-        SE_CFG_ETCAM_KEY_LK3_6r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000514,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_5",
-        SE_CFG_ETCAM_KEY_LK3_5r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000518,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_4",
-        SE_CFG_ETCAM_KEY_LK3_4r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000051c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_3",
-        SE_CFG_ETCAM_KEY_LK3_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000520,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_2",
-        SE_CFG_ETCAM_KEY_LK3_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000524,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_1",
-        SE_CFG_ETCAM_KEY_LK3_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000528,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_key_lk3_0",
-        SE_CFG_ETCAM_KEY_LK3_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000052c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_etcam_key_lk3_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_key_lk0_3",
-        SE_CFG_PBU_KEY_LK0_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_pbu_key_lk0_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_key_lk0_2",
-        SE_CFG_PBU_KEY_LK0_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_pbu_key_lk0_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_key_lk0_1",
-        SE_CFG_PBU_KEY_LK0_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_pbu_key_lk0_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_key_lk0_0",
-        SE_CFG_PBU_KEY_LK0_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_pbu_key_lk0_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_key_lk1_3",
-        SE_CFG_PBU_KEY_LK1_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_pbu_key_lk1_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_key_lk1_2",
-        SE_CFG_PBU_KEY_LK1_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_pbu_key_lk1_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_key_lk1_1",
-        SE_CFG_PBU_KEY_LK1_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_pbu_key_lk1_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_key_lk1_0",
-        SE_CFG_PBU_KEY_LK1_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_pbu_key_lk1_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_key_lk2_3",
-        SE_CFG_PBU_KEY_LK2_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_pbu_key_lk2_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_key_lk2_2",
-        SE_CFG_PBU_KEY_LK2_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_pbu_key_lk2_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_key_lk2_1",
-        SE_CFG_PBU_KEY_LK2_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_pbu_key_lk2_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_key_lk2_0",
-        SE_CFG_PBU_KEY_LK2_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_pbu_key_lk2_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_key_lk3_3",
-        SE_CFG_PBU_KEY_LK3_3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_pbu_key_lk3_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_key_lk3_2",
-        SE_CFG_PBU_KEY_LK3_2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_pbu_key_lk3_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_key_lk3_1",
-        SE_CFG_PBU_KEY_LK3_1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_pbu_key_lk3_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_key_lk3_0",
-        SE_CFG_PBU_KEY_LK3_0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cfg_pbu_key_lk3_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_learn_fifo_pfull_ast",
-        SE_ALG_SCHD_LEARN_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x008c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_learn_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_learn_fifo_pfull_neg",
-        SE_ALG_SCHD_LEARN_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_learn_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_hash0_fifo_pfull_ast",
-        SE_ALG_SCHD_HASH0_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_hash0_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_hash0_fifo_pfull_neg",
-        SE_ALG_SCHD_HASH0_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0098,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_hash0_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_hash1_fifo_pfull_ast",
-        SE_ALG_SCHD_HASH1_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x009c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_hash1_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_hash1_fifo_pfull_neg",
-        SE_ALG_SCHD_HASH1_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_hash1_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_hash2_fifo_pfull_ast",
-        SE_ALG_SCHD_HASH2_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_hash2_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_hash2_fifo_pfull_neg",
-        SE_ALG_SCHD_HASH2_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_hash2_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_hash3_fifo_pfull_ast",
-        SE_ALG_SCHD_HASH3_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_hash3_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_hash3_fifo_pfull_neg",
-        SE_ALG_SCHD_HASH3_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_hash3_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_lpm_fifo_pfull_ast",
-        SE_ALG_SCHD_LPM_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_lpm_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_lpm_fifo_pfull_neg",
-        SE_ALG_SCHD_LPM_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_lpm_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_key_fifo_pfull_ast",
-        SE_ALG_HASH0_KEY_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_key_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_key_fifo_pfull_neg",
-        SE_ALG_HASH0_KEY_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_key_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_sreq_fifo_pfull_ast",
-        SE_ALG_HASH0_SREQ_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_sreq_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_sreq_fifo_pfull_neg",
-        SE_ALG_HASH0_SREQ_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_sreq_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_int_rsp_fifo_pfull_ast",
-        SE_ALG_HASH0_INT_RSP_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_int_rsp_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_int_rsp_fifo_pfull_neg",
-        SE_ALG_HASH0_INT_RSP_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_int_rsp_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_ext_rsp_fifo_pfull_ast",
-        SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_ext_rsp_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_ext_rsp_fifo_pfull_neg",
-        SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_ext_rsp_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_key_fifo_pfull_ast",
-        SE_ALG_HASH1_KEY_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_key_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_key_fifo_pfull_neg",
-        SE_ALG_HASH1_KEY_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_key_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_sreq_fifo_pfull_ast",
-        SE_ALG_HASH1_SREQ_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_sreq_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_sreq_fifo_pfull_neg",
-        SE_ALG_HASH1_SREQ_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_sreq_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_int_rsp_fifo_pfull_ast",
-        SE_ALG_HASH1_INT_RSP_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_int_rsp_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_int_rsp_fifo_pfull_neg",
-        SE_ALG_HASH1_INT_RSP_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0100,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_int_rsp_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_ext_rsp_fifo_pfull_ast",
-        SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0104,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_ext_rsp_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_ext_rsp_fifo_pfull_neg",
-        SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0108,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_ext_rsp_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_key_fifo_pfull_ast",
-        SE_ALG_HASH2_KEY_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x010c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_key_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_key_fifo_pfull_neg",
-        SE_ALG_HASH2_KEY_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0110,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_key_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_sreq_fifo_pfull_ast",
-        SE_ALG_HASH2_SREQ_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0114,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_sreq_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_sreq_fifo_pfull_neg",
-        SE_ALG_HASH2_SREQ_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0118,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_sreq_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_int_rsp_fifo_pfull_ast",
-        SE_ALG_HASH2_INT_RSP_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x011c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_int_rsp_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_int_rsp_fifo_pfull_neg",
-        SE_ALG_HASH2_INT_RSP_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0120,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_int_rsp_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_ext_rsp_fifo_pfull_ast",
-        SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0124,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_ext_rsp_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_ext_rsp_fifo_pfull_neg",
-        SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0128,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_ext_rsp_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_key_fifo_pfull_ast",
-        SE_ALG_HASH3_KEY_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x012c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_key_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_key_fifo_pfull_neg",
-        SE_ALG_HASH3_KEY_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0130,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_key_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_sreq_fifo_pfull_ast",
-        SE_ALG_HASH3_SREQ_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0134,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_sreq_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_sreq_fifo_pfull_neg",
-        SE_ALG_HASH3_SREQ_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0138,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_sreq_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_int_rsp_fifo_pfull_ast",
-        SE_ALG_HASH3_INT_RSP_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x013c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_int_rsp_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_int_rsp_fifo_pfull_neg",
-        SE_ALG_HASH3_INT_RSP_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0140,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_int_rsp_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_ext_rsp_fifo_pfull_ast",
-        SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0144,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_ext_rsp_fifo_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_ext_rsp_fifo_pfull_neg",
-        SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0148,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_ext_rsp_fifo_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_as_info",
-        SE_ALG_LPM_AS_INFOr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0158,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_alg_lpm_as_info_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_ext_rsp_fifo_u0_pfull_neg",
-        SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0160,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_ext_rsp_fifo_u0_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_ext_rsp_fifo_u2_pfull_ast",
-        SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x016c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_ext_rsp_fifo_u2_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_ext_rsp_fifo_u2_pfull_neg",
-        SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0170,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_ext_rsp_fifo_u2_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_ext_rsp_fifo_u3_pfull_ast",
-        SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0174,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_ext_rsp_fifo_u3_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_ext_rsp_fifo_u3_pfull_neg",
-        SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0178,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_ext_rsp_fifo_u3_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_ext_rsp_fifo_u4_pfull_ast",
-        SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x017c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_ext_rsp_fifo_u4_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_ext_rsp_fifo_u4_pfull_neg",
-        SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0180,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_ext_rsp_fifo_u4_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_as_rsp_fifo_u0_pfull_ast",
-        SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x018c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_as_rsp_fifo_u0_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_as_rsp_fifo_u0_pfull_neg",
-        SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0190,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_as_rsp_fifo_u0_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_as_rsp_fifo_u1_pfull_ast",
-        SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_ASTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0194,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_as_rsp_fifo_u1_pfull_ast_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_as_rsp_fifo_u1_pfull_neg",
-        SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_NEGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0198,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_as_rsp_fifo_u1_pfull_neg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_v4_ddr3_base_addr",
-        SE_ALG_LPM_V4_DDR3_BASE_ADDRr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x019c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_v4_ddr3_base_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_v6_ddr3_base_addr",
-        SE_ALG_LPM_V6_DDR3_BASE_ADDRr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_v6_ddr3_base_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_mode",
-        SE_ALG_DEBUG_CNT_MODEr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_alg_debug_cnt_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_p0_key_vld_cnt",
-        SE_ALG_HASH_P0_KEY_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash_p0_key_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_p1_key_vld_cnt",
-        SE_ALG_HASH_P1_KEY_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash_p1_key_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_p2_key_vld_cnt",
-        SE_ALG_HASH_P2_KEY_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash_p2_key_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_p3_key_vld_cnt",
-        SE_ALG_HASH_P3_KEY_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x100c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash_p3_key_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_p0_key_vld_cnt",
-        SE_ALG_LPM_P0_KEY_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_p0_key_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_p0_rsp_vld_cnt",
-        SE_ALG_HASH_P0_RSP_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash_p0_rsp_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_p1_rsp_vld_cnt",
-        SE_ALG_HASH_P1_RSP_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash_p1_rsp_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_p2_rsp_vld_cnt",
-        SE_ALG_HASH_P2_RSP_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x101c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash_p2_rsp_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_p3_rsp_vld_cnt",
-        SE_ALG_HASH_P3_RSP_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash_p3_rsp_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_p0_rsp_vld_cnt",
-        SE_ALG_LPM_P0_RSP_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_p0_rsp_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_p0_smf_cnt",
-        SE_ALG_HASH_P0_SMF_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash_p0_smf_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_p1_smf_cnt",
-        SE_ALG_HASH_P1_SMF_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x102c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash_p1_smf_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_p2_smf_cnt",
-        SE_ALG_HASH_P2_SMF_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash_p2_smf_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_p3_smf_cnt",
-        SE_ALG_HASH_P3_SMF_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash_p3_smf_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_p0_smf_cnt",
-        SE_ALG_LPM_P0_SMF_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_p0_smf_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_p0_spacevld_cnt",
-        SE_ALG_HASH_P0_SPACEVLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x103c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash_p0_spacevld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_p1_spacevld_cnt",
-        SE_ALG_HASH_P1_SPACEVLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash_p1_spacevld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_p2_spacevld_cnt",
-        SE_ALG_HASH_P2_SPACEVLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash_p2_spacevld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_p3_spacevld_cnt",
-        SE_ALG_HASH_P3_SPACEVLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash_p3_spacevld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_p0_req_vld_cnt",
-        SE_ALG_SMMU1_P0_REQ_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x104c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_smmu1_p0_req_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_p1_req_vld_cnt",
-        SE_ALG_SMMU1_P1_REQ_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_smmu1_p1_req_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_p2_req_vld_cnt",
-        SE_ALG_SMMU1_P2_REQ_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_smmu1_p2_req_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_p3_req_vld_cnt",
-        SE_ALG_SMMU1_P3_REQ_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_smmu1_p3_req_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_p4_req_vld_cnt",
-        SE_ALG_SMMU1_P4_REQ_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x105c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_smmu1_p4_req_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_p5_req_vld_cnt",
-        SE_ALG_SMMU1_P5_REQ_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_smmu1_p5_req_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_p0_rsp_vld_cnt",
-        SE_ALG_SMMU1_P0_RSP_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_smmu1_p0_rsp_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_p1_rsp_vld_cnt",
-        SE_ALG_SMMU1_P1_RSP_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_smmu1_p1_rsp_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_p2_rsp_vld_cnt",
-        SE_ALG_SMMU1_P2_RSP_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x106c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_smmu1_p2_rsp_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_p3_rsp_vld_cnt",
-        SE_ALG_SMMU1_P3_RSP_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1070,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_smmu1_p3_rsp_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_p4_rsp_vld_cnt",
-        SE_ALG_SMMU1_P4_RSP_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1074,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_smmu1_p4_rsp_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_p5_rsp_vld_cnt",
-        SE_ALG_SMMU1_P5_RSP_VLD_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1078,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_smmu1_p5_rsp_vld_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_learn_fifo_int_cnt",
-        SE_ALG_SCHD_LEARN_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x107c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_learn_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_hash0_fifo_int_cnt",
-        SE_ALG_SCHD_HASH0_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_hash0_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_hash1_fifo_int_cnt",
-        SE_ALG_SCHD_HASH1_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_hash1_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_hash2_fifo_int_cnt",
-        SE_ALG_SCHD_HASH2_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_hash2_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_hash3_fifo_int_cnt",
-        SE_ALG_SCHD_HASH3_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x108c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_hash3_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_lpm_fifo_int_cnt",
-        SE_ALG_SCHD_LPM_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_lpm_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_learn_fifo_parity_err_cnt",
-        SE_ALG_SCHD_LEARN_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_learn_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_hash0_fifo_parity_err_cnt",
-        SE_ALG_SCHD_HASH0_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1098,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_hash0_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_hash1_fifo_parity_err_cnt",
-        SE_ALG_SCHD_HASH1_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x109c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_hash1_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_hash2_fifo_parity_err_cnt",
-        SE_ALG_SCHD_HASH2_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_hash2_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_hash3_fifo_parity_err_cnt",
-        SE_ALG_SCHD_HASH3_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_hash3_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_lpm_fifo_parity_err_cnt",
-        SE_ALG_SCHD_LPM_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_lpm_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rd_init_cft_cnt",
-        SE_ALG_RD_INIT_CFT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_rd_init_cft_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp0_zblk0_ecc_err_cnt",
-        SE_ALG_ZGP0_ZBLK0_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp0_zblk0_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp0_zblk1_ecc_err_cnt",
-        SE_ALG_ZGP0_ZBLK1_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp0_zblk1_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp0_zblk2_ecc_err_cnt",
-        SE_ALG_ZGP0_ZBLK2_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp0_zblk2_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp0_zblk3_ecc_err_cnt",
-        SE_ALG_ZGP0_ZBLK3_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp0_zblk3_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp0_zblk4_ecc_err_cnt",
-        SE_ALG_ZGP0_ZBLK4_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp0_zblk4_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp0_zblk5_ecc_err_cnt",
-        SE_ALG_ZGP0_ZBLK5_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp0_zblk5_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp0_zblk6_ecc_err_cnt",
-        SE_ALG_ZGP0_ZBLK6_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp0_zblk6_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp0_zblk7_ecc_err_cnt",
-        SE_ALG_ZGP0_ZBLK7_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp0_zblk7_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp1_zblk0_ecc_err_cnt",
-        SE_ALG_ZGP1_ZBLK0_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp1_zblk0_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp1_zblk1_ecc_err_cnt",
-        SE_ALG_ZGP1_ZBLK1_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp1_zblk1_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp1_zblk2_ecc_err_cnt",
-        SE_ALG_ZGP1_ZBLK2_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp1_zblk2_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp1_zblk3_ecc_err_cnt",
-        SE_ALG_ZGP1_ZBLK3_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp1_zblk3_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp1_zblk4_ecc_err_cnt",
-        SE_ALG_ZGP1_ZBLK4_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp1_zblk4_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp1_zblk5_ecc_err_cnt",
-        SE_ALG_ZGP1_ZBLK5_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp1_zblk5_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp1_zblk6_ecc_err_cnt",
-        SE_ALG_ZGP1_ZBLK6_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp1_zblk6_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp1_zblk7_ecc_err_cnt",
-        SE_ALG_ZGP1_ZBLK7_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp1_zblk7_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp2_zblk0_ecc_err_cnt",
-        SE_ALG_ZGP2_ZBLK0_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp2_zblk0_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp2_zblk1_ecc_err_cnt",
-        SE_ALG_ZGP2_ZBLK1_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp2_zblk1_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp2_zblk2_ecc_err_cnt",
-        SE_ALG_ZGP2_ZBLK2_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp2_zblk2_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp2_zblk3_ecc_err_cnt",
-        SE_ALG_ZGP2_ZBLK3_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp2_zblk3_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp2_zblk4_ecc_err_cnt",
-        SE_ALG_ZGP2_ZBLK4_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1100,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp2_zblk4_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp2_zblk5_ecc_err_cnt",
-        SE_ALG_ZGP2_ZBLK5_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1104,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp2_zblk5_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp2_zblk6_ecc_err_cnt",
-        SE_ALG_ZGP2_ZBLK6_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1108,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp2_zblk6_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp2_zblk7_ecc_err_cnt",
-        SE_ALG_ZGP2_ZBLK7_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x110c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp2_zblk7_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp3_zblk0_ecc_err_cnt",
-        SE_ALG_ZGP3_ZBLK0_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1110,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp3_zblk0_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp3_zblk1_ecc_err_cnt",
-        SE_ALG_ZGP3_ZBLK1_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1114,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp3_zblk1_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp3_zblk2_ecc_err_cnt",
-        SE_ALG_ZGP3_ZBLK2_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1118,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp3_zblk2_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp3_zblk3_ecc_err_cnt",
-        SE_ALG_ZGP3_ZBLK3_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x111c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp3_zblk3_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp3_zblk4_ecc_err_cnt",
-        SE_ALG_ZGP3_ZBLK4_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1120,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp3_zblk4_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp3_zblk5_ecc_err_cnt",
-        SE_ALG_ZGP3_ZBLK5_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1124,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp3_zblk5_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp3_zblk6_ecc_err_cnt",
-        SE_ALG_ZGP3_ZBLK6_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1128,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp3_zblk6_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zgp3_zblk7_ecc_err_cnt",
-        SE_ALG_ZGP3_ZBLK7_ECC_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x112c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zgp3_zblk7_ecc_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zcam_hash_p0_err_cnt",
-        SE_ALG_ZCAM_HASH_P0_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1130,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zcam_hash_p0_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zcam_hash_p1_err_cnt",
-        SE_ALG_ZCAM_HASH_P1_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1134,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zcam_hash_p1_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zcam_hash_p2_err_cnt",
-        SE_ALG_ZCAM_HASH_P2_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1138,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zcam_hash_p2_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zcam_hash_p3_err_cnt",
-        SE_ALG_ZCAM_HASH_P3_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x113c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zcam_hash_p3_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zcam_lpm_err_cnt",
-        SE_ALG_ZCAM_LPM_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1140,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zcam_lpm_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_sreq_fifo_parity_err_cnt",
-        SE_ALG_HASH0_SREQ_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1144,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_sreq_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_sreq_fifo_int_cnt",
-        SE_ALG_HASH0_SREQ_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1148,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_sreq_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_key_fifo_int_cnt",
-        SE_ALG_HASH0_KEY_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x114c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_key_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_int_rsp_fifo_parity_err_cnt",
-        SE_ALG_HASH0_INT_RSP_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1150,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_int_rsp_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_ext_rsp_fifo_parity_err_cnt",
-        SE_ALG_HASH0_EXT_RSP_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1154,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_ext_rsp_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_ext_rsp_fifo_int_cnt",
-        SE_ALG_HASH0_EXT_RSP_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1158,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_ext_rsp_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_int_rsp_fifo_int_cnt",
-        SE_ALG_HASH0_INT_RSP_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x115c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_int_rsp_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_sreq_fifo_parity_err_cnt",
-        SE_ALG_HASH1_SREQ_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1160,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_sreq_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_sreq_fifo_int_cnt",
-        SE_ALG_HASH1_SREQ_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1164,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_sreq_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_key_fifo_int_cnt",
-        SE_ALG_HASH1_KEY_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1168,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_key_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_int_rsp_fifo_parity_err_cnt",
-        SE_ALG_HASH1_INT_RSP_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x116c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_int_rsp_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_ext_rsp_fifo_parity_err_cnt",
-        SE_ALG_HASH1_EXT_RSP_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1170,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_ext_rsp_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_ext_rsp_fifo_int_cnt",
-        SE_ALG_HASH1_EXT_RSP_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1174,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_ext_rsp_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_int_rsp_fifo_int_cnt",
-        SE_ALG_HASH1_INT_RSP_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1178,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_int_rsp_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_sreq_fifo_parity_err_cnt",
-        SE_ALG_HASH2_SREQ_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x117c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_sreq_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_sreq_fifo_int_cnt",
-        SE_ALG_HASH2_SREQ_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1180,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_sreq_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_key_fifo_int_cnt",
-        SE_ALG_HASH2_KEY_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1184,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_key_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_int_rsp_fifo_parity_err_cnt",
-        SE_ALG_HASH2_INT_RSP_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1188,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_int_rsp_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_ext_rsp_fifo_parity_err_cnt",
-        SE_ALG_HASH2_EXT_RSP_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x118c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_ext_rsp_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_ext_rsp_fifo_int_cnt",
-        SE_ALG_HASH2_EXT_RSP_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1190,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_ext_rsp_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_int_rsp_fifo_int_cnt",
-        SE_ALG_HASH2_INT_RSP_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1194,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_int_rsp_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_sreq_fifo_parity_err_cnt",
-        SE_ALG_HASH3_SREQ_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1198,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_sreq_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_sreq_fifo_int_cnt",
-        SE_ALG_HASH3_SREQ_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x119c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_sreq_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_key_fifo_int_cnt",
-        SE_ALG_HASH3_KEY_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_key_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_int_rsp_fifo_parity_err_cnt",
-        SE_ALG_HASH3_INT_RSP_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_int_rsp_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_ext_rsp_fifo_parity_err_cnt",
-        SE_ALG_HASH3_EXT_RSP_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_ext_rsp_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_ext_rsp_fifo_int_cnt",
-        SE_ALG_HASH3_EXT_RSP_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_ext_rsp_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_int_rsp_fifo_int_cnt",
-        SE_ALG_HASH3_INT_RSP_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_int_rsp_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_ext_rsp_fifo_int_cnt",
-        SE_ALG_LPM_EXT_RSP_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_ext_rsp_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_ext_v6_fifo_int_cnt",
-        SE_ALG_LPM_EXT_V6_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_ext_v6_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_ext_v4_fifo_int_cnt",
-        SE_ALG_LPM_EXT_V4_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_ext_v4_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_ext_addr_fifo_int_cnt",
-        SE_ALG_LPM_EXT_ADDR_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_ext_addr_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_ext_v4_fifo_parity_err_cnt",
-        SE_ALG_LPM_EXT_V4_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_ext_v4_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_ext_v6_fifo_parity_err_cnt",
-        SE_ALG_LPM_EXT_V6_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_ext_v6_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_ext_rsp_fifo_parity_err_cnt",
-        SE_ALG_LPM_EXT_RSP_FIFO_PARITY_ERR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_ext_rsp_fifo_parity_err_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_as_req_fifo_int_cnt",
-        SE_ALG_LPM_AS_REQ_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_as_req_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_as_int_rsp_fifo_int_cnt",
-        SE_ALG_LPM_AS_INT_RSP_FIFO_INT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_as_int_rsp_fifo_int_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_alg_int_status",
-        SE_ALG_SE_ALG_INT_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1800,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        7,
-        g_se_alg_se_alg_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_en",
-        SE_ALG_SCHD_INT_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1804,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        14,
-        g_se_alg_schd_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_mask",
-        SE_ALG_SCHD_INT_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1808,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_status",
-        SE_ALG_SCHD_INT_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x180c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_schd_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblk_ecc_int_en",
-        SE_ALG_ZBLK_ECC_INT_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1810,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zblk_ecc_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblk_ecc_int_mask",
-        SE_ALG_ZBLK_ECC_INT_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1814,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zblk_ecc_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblk_ecc_int_status",
-        SE_ALG_ZBLK_ECC_INT_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1818,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_zblk_ecc_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_int_en",
-        SE_ALG_HASH0_INT_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x181c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        8,
-        g_se_alg_hash0_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_int_mask",
-        SE_ALG_HASH0_INT_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1820,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_int_status",
-        SE_ALG_HASH0_INT_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1824,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash0_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_int_en",
-        SE_ALG_HASH1_INT_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1828,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        8,
-        g_se_alg_hash1_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_int_mask",
-        SE_ALG_HASH1_INT_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x182c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_int_status",
-        SE_ALG_HASH1_INT_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1830,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash1_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_int_en",
-        SE_ALG_HASH2_INT_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1834,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        8,
-        g_se_alg_hash2_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_int_mask",
-        SE_ALG_HASH2_INT_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1838,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_int_status",
-        SE_ALG_HASH2_INT_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x183c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash2_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_int_en",
-        SE_ALG_HASH3_INT_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1840,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        8,
-        g_se_alg_hash3_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_int_mask",
-        SE_ALG_HASH3_INT_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1844,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_int_status",
-        SE_ALG_HASH3_INT_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1848,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_hash3_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_int_en",
-        SE_ALG_LPM_INT_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x184c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        10,
-        g_se_alg_lpm_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_int_mask",
-        SE_ALG_LPM_INT_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1850,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_int_status",
-        SE_ALG_LPM_INT_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1854,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_alg_lpm_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_lpm_mask0",
-        SE_ALG_ZBLOCK_LPM_MASK0r,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x10001,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        5,
-        g_se_alg_zblock_lpm_mask0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_lpm_mask1",
-        SE_ALG_ZBLOCK_LPM_MASK1r,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x10002,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        5,
-        g_se_alg_zblock_lpm_mask1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_lpm_mask2",
-        SE_ALG_ZBLOCK_LPM_MASK2r,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x10003,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        5,
-        g_se_alg_zblock_lpm_mask2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_lpm_mask3",
-        SE_ALG_ZBLOCK_LPM_MASK3r,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x10004,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        5,
-        g_se_alg_zblock_lpm_mask3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_default_route0",
-        SE_ALG_ZBLOCK_DEFAULT_ROUTE0r,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x10005,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        4,
-        g_se_alg_zblock_default_route0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_default_route1",
-        SE_ALG_ZBLOCK_DEFAULT_ROUTE1r,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x10006,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        4,
-        g_se_alg_zblock_default_route1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_default_route2",
-        SE_ALG_ZBLOCK_DEFAULT_ROUTE2r,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x10007,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        4,
-        g_se_alg_zblock_default_route2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_default_route3",
-        SE_ALG_ZBLOCK_DEFAULT_ROUTE3r,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x10008,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        4,
-        g_se_alg_zblock_default_route3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_default_route4",
-        SE_ALG_ZBLOCK_DEFAULT_ROUTE4r,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x10009,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        4,
-        g_se_alg_zblock_default_route4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_default_route5",
-        SE_ALG_ZBLOCK_DEFAULT_ROUTE5r,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x1000a,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        4,
-        g_se_alg_zblock_default_route5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_default_route6",
-        SE_ALG_ZBLOCK_DEFAULT_ROUTE6r,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x1000b,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        4,
-        g_se_alg_zblock_default_route6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_default_route7",
-        SE_ALG_ZBLOCK_DEFAULT_ROUTE7r,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x1000c,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        4,
-        g_se_alg_zblock_default_route7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_hash_listtable_item0",
-        SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM0r,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x1000d,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        1,
-        g_se_alg_zblock_hash_listtable_item0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_hash_listtable_item1",
-        SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM1r,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x1000e,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        1,
-        g_se_alg_zblock_hash_listtable_item1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_hash_listtable_item2",
-        SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM2r,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x1000f,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        1,
-        g_se_alg_zblock_hash_listtable_item2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_hash_listtable_item3",
-        SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM3r,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x10010,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        1,
-        g_se_alg_zblock_hash_listtable_item3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_ecc_err_status",
-        SE_ALG_ZBLOCK_ECC_ERR_STATUSr,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x10011,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        4,
-        g_se_alg_zblock_ecc_err_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_lpm_v6_sram_cmp",
-        SE_ALG_ZBLOCK_LPM_V6_SRAM_CMPr,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x10012,
-        (512/8),
-        3 + 1,
-        7 + 1,
-        0x4000,
-        0x800,
-        1,
-        g_se_alg_zblock_lpm_v6_sram_cmp_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "zblock_lpm_v4_sram_cmp",
-        SE_ALG_ZBLOCK_LPM_V4_SRAM_CMPr,
-        SE,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_BIN_ARRAY,
-        0x10013,
-        (512/8),
-        3 + 1,
-        5 + 1,
-        0x4000,
-        0x800,
-        1,
-        g_se_alg_zblock_lpm_v4_sram_cmp_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_pful_cfg",
-        SE_PARSER_KSCHD_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_parser_kschd_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_mode",
-        SE_PARSER_DEBUG_CNT_MODEr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_parser_debug_cnt_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "parser_int_en",
-        SE_PARSER_PARSER_INT_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x0000000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_parser_parser_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "parser_int_mask",
-        SE_PARSER_PARSER_INT_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_parser_parser_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "parser_int_status",
-        SE_PARSER_PARSER_INT_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_parser_parser_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "parser_int_unmask_flag",
-        SE_PARSER_PARSER_INT_UNMASK_FLAGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_parser_parser_int_unmask_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ecc_bypass_read",
-        SE_PARSER_ECC_BYPASS_READr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x0000001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_parser_ecc_bypass_read_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mex0_5_req_cnt",
-        SE_PARSER_MEX0_5_REQ_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000400,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_se_parser_mex0_5_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_req0_5_cnt",
-        SE_PARSER_KSCHD_REQ0_5_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000420,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_se_parser_kschd_req0_5_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_parser_fc0_5_cnt",
-        SE_PARSER_KSCHD_PARSER_FC0_5_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000440,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_se_parser_kschd_parser_fc0_5_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_ppu_mex0_5_fc_cnt",
-        SE_PARSER_SE_PPU_MEX0_5_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000460,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_se_parser_se_ppu_mex0_5_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_marc_fc_cnt",
-        SE_PARSER_SMMU0_MARC_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000480,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_parser_smmu0_marc_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_marc_key_cnt",
-        SE_PARSER_SMMU0_MARC_KEY_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000484,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_parser_smmu0_marc_key_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cmmu_key_cnt",
-        SE_PARSER_CMMU_KEY_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000488,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_parser_cmmu_key_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cmmu_parser_fc_cnt",
-        SE_PARSER_CMMU_PARSER_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x0000048c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_parser_cmmu_parser_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "marc_tab_type_err_mex0_5_cnt",
-        SE_PARSER_MARC_TAB_TYPE_ERR_MEX0_5_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000490,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_se_parser_marc_tab_type_err_mex0_5_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "eram_fulladdr_drop_cnt",
-        SE_PARSER_ERAM_FULLADDR_DROP_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x000004b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_parser_eram_fulladdr_drop_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_pful_cfg",
-        SE_AS_HASH0_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_hash0_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash1_pful_cfg",
-        SE_AS_HASH1_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_hash1_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash2_pful_cfg",
-        SE_AS_HASH2_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_hash2_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_pful_cfg",
-        SE_AS_HASH3_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_hash3_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_pful_cfg",
-        SE_AS_PBU_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_pbu_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_pful_cfg",
-        SE_AS_LPM_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_lpm_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_pful_cfg",
-        SE_AS_ETCAM_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_etcam_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_learn0_fifo_cfg",
-        SE_AS_AS_LEARN0_FIFO_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_se_as_as_learn0_fifo_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_learn1_fifo_cfg",
-        SE_AS_AS_LEARN1_FIFO_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_se_as_as_learn1_fifo_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_dma_fifo_cfg",
-        SE_AS_AS_DMA_FIFO_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_as_dma_fifo_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "age_pful_cfg",
-        SE_AS_AGE_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_age_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_rsp_cfg",
-        SE_AS_ETCAM_RSP_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_se_as_etcam_rsp_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ecc_bypass_read",
-        SE_AS_PBU_ECC_BYPASS_READr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_pbu_ecc_bypass_read_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam0_ecc_bypass_read",
-        SE_AS_ETCAM0_ECC_BYPASS_READr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000200,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_etcam0_ecc_bypass_read_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam1_ecc_bypass_read",
-        SE_AS_ETCAM1_ECC_BYPASS_READr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000204,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_etcam1_ecc_bypass_read_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_ecc_bypass_read",
-        SE_AS_LPM_ECC_BYPASS_READr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000208,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_lpm_ecc_bypass_read_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_ecc_bypass_read",
-        SE_AS_HASH_ECC_BYPASS_READr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000020c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_se_as_hash_ecc_bypass_read_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_learn_ecc_bypass_read",
-        SE_AS_HASH_LEARN_ECC_BYPASS_READr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000210,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_hash_learn_ecc_bypass_read_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_mode",
-        SE_AS_DEBUG_CNT_MODEr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000003e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_as_debug_cnt_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_int_0_en",
-        SE_AS_AS_INT_0_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000440,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_as_int_0_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_int_0_mask",
-        SE_AS_AS_INT_0_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000444,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_as_int_0_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_int_1_en",
-        SE_AS_AS_INT_1_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000448,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_as_int_1_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_int_1_mask",
-        SE_AS_AS_INT_1_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000044c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_as_int_1_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_int_2_en",
-        SE_AS_AS_INT_2_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000450,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_as_int_2_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_int_2_mask",
-        SE_AS_AS_INT_2_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000454,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_as_int_2_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_int_0_status",
-        SE_AS_AS_INT_0_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000458,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_as_int_0_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_int_1_status",
-        SE_AS_AS_INT_1_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000045c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_as_int_1_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_int_2_status",
-        SE_AS_AS_INT_2_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000460,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_as_int_2_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_as_int_status",
-        SE_AS_SE_AS_INT_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000464,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_se_as_se_as_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_3_wr_req_cnt",
-        SE_AS_HASH0_3_WR_REQ_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000082c,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_as_hash0_3_wr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_etcam0_1_fc_cnt",
-        SE_AS_SMMU0_ETCAM0_1_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000083c,
-        (32/8),
-        0,
-        0 + 1,
-        0,
-        4,
-        1,
-        g_se_as_smmu0_etcam0_1_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam0_1_smmu0_req_cnt",
-        SE_AS_ETCAM0_1_SMMU0_REQ_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000844,
-        (32/8),
-        0,
-        0 + 1,
-        0,
-        8,
-        1,
-        g_se_as_etcam0_1_smmu0_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_etcam0_1_rsp_cnt",
-        SE_AS_SMMU0_ETCAM0_1_RSP_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000848,
-        (32/8),
-        0,
-        0 + 1,
-        0,
-        8,
-        1,
-        g_se_as_smmu0_etcam0_1_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_hla_hash_p0_3_key_cnt",
-        SE_AS_AS_HLA_HASH_P0_3_KEY_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000854,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_as_as_hla_hash_p0_3_key_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_hla_lpm_p0_key_cnt",
-        SE_AS_AS_HLA_LPM_P0_KEY_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000864,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_as_hla_lpm_p0_key_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "alg_as_hash_p0_3_rsp_cnt",
-        SE_AS_ALG_AS_HASH_P0_3_RSP_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000868,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        8,
-        1,
-        g_se_as_alg_as_hash_p0_3_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "alg_as_hash_p0_3_smf_rsp_cnt",
-        SE_AS_ALG_AS_HASH_P0_3_SMF_RSP_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000086c,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        8,
-        1,
-        g_se_as_alg_as_hash_p0_3_smf_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "alg_as_lpm_p0_rsp_cnt",
-        SE_AS_ALG_AS_LPM_P0_RSP_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000888,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_alg_as_lpm_p0_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "alg_as_lpm_p0_3_smf_rsp_cnt",
-        SE_AS_ALG_AS_LPM_P0_3_SMF_RSP_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000088c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_alg_as_lpm_p0_3_smf_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_pbu_key_cnt",
-        SE_AS_AS_PBU_KEY_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000890,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_as_pbu_key_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_se_dpi_rsp_dat_cnt",
-        SE_AS_PBU_SE_DPI_RSP_DAT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000894,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_pbu_se_dpi_rsp_dat_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_etcam_ctrl_req0_cnt",
-        SE_AS_AS_ETCAM_CTRL_REQ0_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000898,
-        (32/8),
-        0,
-        0 + 1,
-        0,
-        4,
-        1,
-        g_se_as_as_etcam_ctrl_req0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_ctrl_as_index0_1_cnt",
-        SE_AS_ETCAM_CTRL_AS_INDEX0_1_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008a0,
-        (32/8),
-        0,
-        0 + 1,
-        0,
-        8,
-        1,
-        g_se_as_etcam_ctrl_as_index0_1_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_ctrl_as_hit0_1_cnt",
-        SE_AS_ETCAM_CTRL_AS_HIT0_1_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008a4,
-        (32/8),
-        0,
-        0 + 1,
-        0,
-        8,
-        1,
-        g_se_as_etcam_ctrl_as_hit0_1_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_smmu0_req_cnt",
-        SE_AS_AS_SMMU0_REQ_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_as_smmu0_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "learn_hla_wr_cnt",
-        SE_AS_LEARN_HLA_WR_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_learn_hla_wr_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_smmu1_req_cnt",
-        SE_AS_AS_SMMU1_REQ_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_as_smmu1_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_cfg_mac_dat_cnt",
-        SE_AS_SE_CFG_MAC_DAT_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_se_cfg_mac_dat_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "alg_as_hash_p0_3_fc_cnt",
-        SE_AS_ALG_AS_HASH_P0_3_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008c0,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_as_alg_as_hash_p0_3_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "alg_as_lpm_p0_fc_cnt",
-        SE_AS_ALG_AS_LPM_P0_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_alg_as_lpm_p0_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_alg_hash_p0_3_fc_cnt",
-        SE_AS_AS_ALG_HASH_P0_3_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008d4,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_as_as_alg_hash_p0_3_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_alg_lpm_p0_fc_cnt",
-        SE_AS_AS_ALG_LPM_P0_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_as_alg_lpm_p0_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_pbu_fc_cnt",
-        SE_AS_AS_PBU_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_as_pbu_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_se_dpi_key_fc_cnt",
-        SE_AS_PBU_SE_DPI_KEY_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_pbu_se_dpi_key_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_etcam_ctrl_fc0_1_cnt",
-        SE_AS_AS_ETCAM_CTRL_FC0_1_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008f0,
-        (32/8),
-        0,
-        0 + 1,
-        0,
-        4,
-        1,
-        g_se_as_as_etcam_ctrl_fc0_1_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_ctrl_as_fc0_1_cnt",
-        SE_AS_ETCAM_CTRL_AS_FC0_1_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008f8,
-        (32/8),
-        0,
-        0 + 1,
-        0,
-        4,
-        1,
-        g_se_as_etcam_ctrl_as_fc0_1_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_as_mac_age_fc_cnt",
-        SE_AS_SMMU0_AS_MAC_AGE_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000900,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_smmu0_as_mac_age_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "alg_learn_fc_cnt",
-        SE_AS_ALG_LEARN_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000904,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_alg_learn_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_as_fc_cnt",
-        SE_AS_SMMU1_AS_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000908,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_smmu1_as_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_se_mac_fc_cnt",
-        SE_AS_CFG_SE_MAC_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000090c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_as_cfg_se_mac_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_cpu_rdy",
-        SE_KSCHD_KSCHD_CPU_RDYr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_kschd_cpu_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu0_ecc_bypass_read",
-        SE_KSCHD_PPU0_ECC_BYPASS_READr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_ppu0_ecc_bypass_read_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pbu_ecc_bypass_read",
-        SE_KSCHD_PBU_ECC_BYPASS_READr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_pbu_ecc_bypass_read_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_ecc_bypass_read",
-        SE_KSCHD_SMMU1_ECC_BYPASS_READr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000002c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_se_kschd_smmu1_ecc_bypass_read_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ass_ecc_bypass_read",
-        SE_KSCHD_ASS_ECC_BYPASS_READr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_ass_ecc_bypass_read_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sdt_h",
-        SE_KSCHD_SDT_Hr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_sdt_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "sdt_l",
-        SE_KSCHD_SDT_Lr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_sdt_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key15",
-        SE_KSCHD_HASH_KEY15r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_se_kschd_hash_key15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key14",
-        SE_KSCHD_HASH_KEY14r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_hash_key14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key13",
-        SE_KSCHD_HASH_KEY13r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_hash_key13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key12",
-        SE_KSCHD_HASH_KEY12r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_hash_key12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key11",
-        SE_KSCHD_HASH_KEY11r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_hash_key11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key10",
-        SE_KSCHD_HASH_KEY10r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000005c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_hash_key10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key9",
-        SE_KSCHD_HASH_KEY9r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_hash_key9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key8",
-        SE_KSCHD_HASH_KEY8r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_hash_key8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key7",
-        SE_KSCHD_HASH_KEY7r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_hash_key7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key6",
-        SE_KSCHD_HASH_KEY6r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000006c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_hash_key6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key5",
-        SE_KSCHD_HASH_KEY5r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000070,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_hash_key5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key4",
-        SE_KSCHD_HASH_KEY4r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000074,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_hash_key4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key3",
-        SE_KSCHD_HASH_KEY3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000078,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_hash_key3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key2",
-        SE_KSCHD_HASH_KEY2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000007c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_hash_key2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key1",
-        SE_KSCHD_HASH_KEY1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_hash_key1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_key0",
-        SE_KSCHD_HASH_KEY0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_hash_key0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_0_en",
-        SE_KSCHD_SCHD_INT_0_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_schd_int_0_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_0_mask",
-        SE_KSCHD_SCHD_INT_0_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_schd_int_0_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_1_en",
-        SE_KSCHD_SCHD_INT_1_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_schd_int_1_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_1_mask",
-        SE_KSCHD_SCHD_INT_1_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_schd_int_1_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_2_en",
-        SE_KSCHD_SCHD_INT_2_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_schd_int_2_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_2_mask",
-        SE_KSCHD_SCHD_INT_2_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_schd_int_2_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_3_en",
-        SE_KSCHD_SCHD_INT_3_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_schd_int_3_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_3_mask",
-        SE_KSCHD_SCHD_INT_3_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_schd_int_3_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_4_en",
-        SE_KSCHD_SCHD_INT_4_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_schd_int_4_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_4_mask",
-        SE_KSCHD_SCHD_INT_4_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_schd_int_4_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_0_status",
-        SE_KSCHD_SCHD_INT_0_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_schd_int_0_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_1_status",
-        SE_KSCHD_SCHD_INT_1_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_schd_int_1_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_2_status",
-        SE_KSCHD_SCHD_INT_2_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_schd_int_2_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_3_status",
-        SE_KSCHD_SCHD_INT_3_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_schd_int_3_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "schd_int_4_status",
-        SE_KSCHD_SCHD_INT_4_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_schd_int_4_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_kschd_int_status",
-        SE_KSCHD_SE_KSCHD_INT_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000148,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_se_kschd_se_kschd_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_mode",
-        SE_KSCHD_DEBUG_CNT_MODEr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000003ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_kschd_debug_cnt_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_parser_kschd_key0_3_cnt",
-        SE_KSCHD_SE_PARSER_KSCHD_KEY0_3_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000878,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_se_kschd_se_parser_kschd_key0_3_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_smmu1_key0_3_cnt",
-        SE_KSCHD_SE_SMMU1_KEY0_3_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000890,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_kschd_se_smmu1_key0_3_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_as_key0_cnt",
-        SE_KSCHD_KSCHD_AS_KEY0_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_kschd_as_key0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_as_key1_cnt",
-        SE_KSCHD_KSCHD_AS_KEY1_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_kschd_as_key1_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_as_key2_cnt",
-        SE_KSCHD_KSCHD_AS_KEY2_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_kschd_as_key2_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_as_key3_cnt",
-        SE_KSCHD_KSCHD_AS_KEY3_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_kschd_as_key3_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_as_key4_cnt",
-        SE_KSCHD_KSCHD_AS_KEY4_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_kschd_as_key4_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_as_key5_cnt",
-        SE_KSCHD_KSCHD_AS_KEY5_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_kschd_as_key5_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_as_key6_cnt",
-        SE_KSCHD_KSCHD_AS_KEY6_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_kschd_as_key6_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_as_key9_cnt",
-        SE_KSCHD_KSCHD_AS_KEY9_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_kschd_as_key9_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_se_parser_fc0_3_cnt",
-        SE_KSCHD_KSCHD_SE_PARSER_FC0_3_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008c0,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_se_kschd_kschd_se_parser_fc0_3_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_se_fc0_3_cnt",
-        SE_KSCHD_SMMU1_SE_FC0_3_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008d8,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_kschd_smmu1_se_fc0_3_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_kschd_fc_cnt0",
-        SE_KSCHD_AS_KSCHD_FC_CNT0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_as_kschd_fc_cnt0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_kschd_fc_cnt1",
-        SE_KSCHD_AS_KSCHD_FC_CNT1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_as_kschd_fc_cnt1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_kschd_fc_cnt2",
-        SE_KSCHD_AS_KSCHD_FC_CNT2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_as_kschd_fc_cnt2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_kschd_fc_cnt3",
-        SE_KSCHD_AS_KSCHD_FC_CNT3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_as_kschd_fc_cnt3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_kschd_fc_cnt4",
-        SE_KSCHD_AS_KSCHD_FC_CNT4r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_as_kschd_fc_cnt4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_kschd_fc_cnt5",
-        SE_KSCHD_AS_KSCHD_FC_CNT5r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_as_kschd_fc_cnt5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_kschd_fc_cnt6",
-        SE_KSCHD_AS_KSCHD_FC_CNT6r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000900,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_as_kschd_fc_cnt6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_kschd_fc_cnt9",
-        SE_KSCHD_AS_KSCHD_FC_CNT9r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000904,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_kschd_as_kschd_fc_cnt9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_hash_pful_cfg",
-        SE_RSCHD_RSCHD_HASH_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_hash_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_hash_ept_cfg",
-        SE_RSCHD_RSCHD_HASH_EPT_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_hash_ept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_pbu_pful_cfg",
-        SE_RSCHD_RSCHD_PBU_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_pbu_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_pbu_ept_cfg",
-        SE_RSCHD_RSCHD_PBU_EPT_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_pbu_ept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_lpm_pful_cfg",
-        SE_RSCHD_RSCHD_LPM_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_lpm_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_lpm_ept_cfg",
-        SE_RSCHD_RSCHD_LPM_EPT_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_lpm_ept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_etcam_pful_cfg",
-        SE_RSCHD_RSCHD_ETCAM_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_etcam_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_etcam_ept_cfg",
-        SE_RSCHD_RSCHD_ETCAM_EPT_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_etcam_ept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_wb_pful_cfg",
-        SE_RSCHD_SMMU0_WB_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_smmu0_wb_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_wb_ept_cfg",
-        SE_RSCHD_SMMU0_WB_EPT_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_smmu0_wb_ept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_wb_pful_cfg",
-        SE_RSCHD_SMMU1_WB_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_smmu1_wb_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_wb_ept_cfg",
-        SE_RSCHD_SMMU1_WB_EPT_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_smmu1_wb_ept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "alg_wb_pful_cfg",
-        SE_RSCHD_ALG_WB_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_alg_wb_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "alg_wb_ept_cfg",
-        SE_RSCHD_ALG_WB_EPT_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_alg_wb_ept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "wr_rsp_vld_en",
-        SE_RSCHD_WR_RSP_VLD_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_wr_rsp_vld_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "nppu_wb_pful_cfg",
-        SE_RSCHD_NPPU_WB_PFUL_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000005c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_nppu_wb_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "nppu_wb_ept_cfg",
-        SE_RSCHD_NPPU_WB_EPT_CFGr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_nppu_wb_ept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port0_int_en",
-        SE_RSCHD_PORT0_INT_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_port0_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port0_int_mask",
-        SE_RSCHD_PORT0_INT_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_port0_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port1_int_en",
-        SE_RSCHD_PORT1_INT_ENr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_port1_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port1_int_mask",
-        SE_RSCHD_PORT1_INT_MASKr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_port1_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port0_int_status",
-        SE_RSCHD_PORT0_INT_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_port0_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "port1_int_status",
-        SE_RSCHD_PORT1_INT_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_port1_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_rschd_int_status",
-        SE_RSCHD_SE_RSCHD_INT_STATUSr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000018c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_rschd_se_rschd_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_mode",
-        SE_RSCHD_DEBUG_CNT_MODEr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000003ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_rschd_debug_cnt_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_ppu_mex0_5_rsp1_cnt",
-        SE_RSCHD_SE_PPU_MEX0_5_RSP1_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000880,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_se_rschd_se_ppu_mex0_5_rsp1_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_rschd_rsp0_cnt",
-        SE_RSCHD_AS_RSCHD_RSP0_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000898,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_as_rschd_rsp0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_rschd_rsp1_cnt",
-        SE_RSCHD_AS_RSCHD_RSP1_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000089c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_as_rschd_rsp1_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_rschd_rsp2_cnt",
-        SE_RSCHD_AS_RSCHD_RSP2_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_as_rschd_rsp2_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_rschd_rsp3_cnt",
-        SE_RSCHD_AS_RSCHD_RSP3_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_as_rschd_rsp3_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_rschd_rsp4_cnt",
-        SE_RSCHD_AS_RSCHD_RSP4_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_as_rschd_rsp4_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_rschd_rsp5_cnt",
-        SE_RSCHD_AS_RSCHD_RSP5_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_as_rschd_rsp5_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_rschd_rsp6_cnt",
-        SE_RSCHD_AS_RSCHD_RSP6_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_as_rschd_rsp6_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_rschd_rsp9_cnt",
-        SE_RSCHD_AS_RSCHD_RSP9_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_as_rschd_rsp9_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_se_rsp0_3_cnt",
-        SE_RSCHD_SMMU1_SE_RSP0_3_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008b8,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_rschd_smmu1_se_rsp0_3_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_se_mex0_3_fc_cnt",
-        SE_RSCHD_PPU_SE_MEX0_3_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008c4,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_se_rschd_ppu_se_mex0_3_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_as_fc_cnt0",
-        SE_RSCHD_RSCHD_AS_FC_CNT0r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_as_fc_cnt0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_as_fc_cnt1",
-        SE_RSCHD_RSCHD_AS_FC_CNT1r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_as_fc_cnt1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_as_fc_cnt2",
-        SE_RSCHD_RSCHD_AS_FC_CNT2r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_as_fc_cnt2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_as_fc_cnt3",
-        SE_RSCHD_RSCHD_AS_FC_CNT3r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_as_fc_cnt3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_as_fc_cnt4",
-        SE_RSCHD_RSCHD_AS_FC_CNT4r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_as_fc_cnt4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_as_fc_cnt5",
-        SE_RSCHD_RSCHD_AS_FC_CNT5r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_as_fc_cnt5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_as_fc_cnt6",
-        SE_RSCHD_RSCHD_AS_FC_CNT6r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_as_fc_cnt6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_as_fc_cnt9",
-        SE_RSCHD_RSCHD_AS_FC_CNT9r,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_rschd_as_fc_cnt9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_smmu1_fc0_3_cnt",
-        SE_RSCHD_SE_SMMU1_FC0_3_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000900,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_rschd_se_smmu1_fc0_3_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_se_wr_done_cnt",
-        SE_RSCHD_SMMU0_SE_WR_DONE_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000910,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_smmu0_se_wr_done_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_smmu0_wr_done_fc_cnt",
-        SE_RSCHD_SE_SMMU0_WR_DONE_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000914,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_se_smmu0_wr_done_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_se_wr_rsp_cnt",
-        SE_RSCHD_SMMU1_SE_WR_RSP_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000918,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_smmu1_se_wr_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_smmu1_wr_rsp_fc_cnt",
-        SE_RSCHD_SE_SMMU1_WR_RSP_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000091c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_se_smmu1_wr_rsp_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "alg_se_wr_rsp_cnt",
-        SE_RSCHD_ALG_SE_WR_RSP_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000920,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_alg_se_wr_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_alg_wr_rsp_fc_cnt",
-        SE_RSCHD_SE_ALG_WR_RSP_FC_CNTr,
-        SE,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000924,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_rschd_se_alg_wr_rsp_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_pful_cfg0",
-        SMMU0_SMMU0_KSCHD_PFUL_CFG0r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_smmu0_smmu0_kschd_pful_cfg0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_pful_cfg1",
-        SMMU0_SMMU0_KSCHD_PFUL_CFG1r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_smmu0_smmu0_kschd_pful_cfg1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_pful1_cfg",
-        SMMU0_SMMU0_CTRL_PFUL1_CFGr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_ctrl_pful1_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_pful2_cfg",
-        SMMU0_SMMU0_CTRL_PFUL2_CFGr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000008c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_ctrl_pful2_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_pful3_cfg",
-        SMMU0_SMMU0_CTRL_PFUL3_CFGr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_ctrl_pful3_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_pful_cfg",
-        SMMU0_SMMU0_RSCHD_PFUL_CFGr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_rschd_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_ept_cfg",
-        SMMU0_SMMU0_RSCHD_EPT_CFGr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000098,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_rschd_ept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "alucmd_pful_cfg",
-        SMMU0_SMMU0_ALUCMD_PFUL_CFGr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000009c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_alucmd_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "aluwr_pful_cfg",
-        SMMU0_SMMU0_ALUWR_PFUL_CFGr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_aluwr_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "wr_arb_pful_cfg0",
-        SMMU0_SMMU0_WR_ARB_PFUL_CFG0r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_wr_arb_pful_cfg0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "wr_arb_pful_cfg1",
-        SMMU0_SMMU0_WR_ARB_PFUL_CFG1r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_wr_arb_pful_cfg1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ord_pful_cfg",
-        SMMU0_SMMU0_ORD_PFUL_CFGr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_ord_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_dma_baddr",
-        SMMU0_SMMU0_CFG_DMA_BADDRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cfg_dma_baddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_odma0_baddr",
-        SMMU0_SMMU0_CFG_ODMA0_BADDRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cfg_odma0_baddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_odma1_baddr",
-        SMMU0_SMMU0_CFG_ODMA1_BADDRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cfg_odma1_baddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_odma2_baddr",
-        SMMU0_SMMU0_CFG_ODMA2_BADDRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cfg_odma2_baddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_odma_tdm_baddr",
-        SMMU0_SMMU0_CFG_ODMA_TDM_BADDRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cfg_odma_tdm_baddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_mcast_baddr",
-        SMMU0_SMMU0_CFG_MCAST_BADDRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cfg_mcast_baddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_lpm0",
-        SMMU0_SMMU0_CFG_LPM0r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_cfg_lpm0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_lpm1",
-        SMMU0_SMMU0_CFG_LPM1r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_cfg_lpm1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_lpm2",
-        SMMU0_SMMU0_CFG_LPM2r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_cfg_lpm2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_lpm3",
-        SMMU0_SMMU0_CFG_LPM3r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_cfg_lpm3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_lpm4",
-        SMMU0_SMMU0_CFG_LPM4r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_cfg_lpm4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_lpm5",
-        SMMU0_SMMU0_CFG_LPM5r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_cfg_lpm5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_lpm6",
-        SMMU0_SMMU0_CFG_LPM6r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_cfg_lpm6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_lpm7",
-        SMMU0_SMMU0_CFG_LPM7r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_cfg_lpm7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_mode",
-        SMMU0_SMMU0_DEBUG_CNT_MODEr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000100,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_debug_cnt_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_overflow_mode",
-        SMMU0_SMMU0_STAT_OVERFLOW_MODEr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000104,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_stat_overflow_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "init_en_cfg_tmp",
-        SMMU0_SMMU0_INIT_EN_CFG_TMPr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000013c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_init_en_cfg_tmp_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int_unmask_flag",
-        SMMU0_SMMU0_SMMU0_INT_UNMASK_FLAGr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000140,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int_unmask_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int0_en",
-        SMMU0_SMMU0_SMMU0_INT0_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000144,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int0_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int0_mask",
-        SMMU0_SMMU0_SMMU0_INT0_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000148,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int0_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int0_status",
-        SMMU0_SMMU0_SMMU0_INT0_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000014c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int0_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int1_en",
-        SMMU0_SMMU0_SMMU0_INT1_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000150,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int1_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int1_mask",
-        SMMU0_SMMU0_SMMU0_INT1_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000154,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int1_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int1_status",
-        SMMU0_SMMU0_SMMU0_INT1_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000158,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int1_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int2_en",
-        SMMU0_SMMU0_SMMU0_INT2_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000015c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int2_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int2_mask",
-        SMMU0_SMMU0_SMMU0_INT2_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000160,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int2_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int2_status",
-        SMMU0_SMMU0_SMMU0_INT2_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000164,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int2_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int3_en",
-        SMMU0_SMMU0_SMMU0_INT3_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000168,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int3_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int3_mask",
-        SMMU0_SMMU0_SMMU0_INT3_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000016c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int3_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int3_status",
-        SMMU0_SMMU0_SMMU0_INT3_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000170,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int3_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int4_en",
-        SMMU0_SMMU0_SMMU0_INT4_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000174,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int4_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int4_mask",
-        SMMU0_SMMU0_SMMU0_INT4_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000178,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int4_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int4_status",
-        SMMU0_SMMU0_SMMU0_INT4_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000017c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int4_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int5_en",
-        SMMU0_SMMU0_SMMU0_INT5_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000180,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int5_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int5_mask",
-        SMMU0_SMMU0_SMMU0_INT5_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000184,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int5_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int5_status",
-        SMMU0_SMMU0_SMMU0_INT5_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000188,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int5_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int6_en",
-        SMMU0_SMMU0_SMMU0_INT6_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000018c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int6_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int6_mask",
-        SMMU0_SMMU0_SMMU0_INT6_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000190,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int6_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int6_status",
-        SMMU0_SMMU0_SMMU0_INT6_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000194,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int6_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int7_en",
-        SMMU0_SMMU0_SMMU0_INT7_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000198,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int7_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int7_mask",
-        SMMU0_SMMU0_SMMU0_INT7_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000019c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int7_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int7_status",
-        SMMU0_SMMU0_SMMU0_INT7_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int7_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int8_en",
-        SMMU0_SMMU0_SMMU0_INT8_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int8_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int8_mask",
-        SMMU0_SMMU0_SMMU0_INT8_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int8_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int8_status",
-        SMMU0_SMMU0_SMMU0_INT8_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int8_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int9_en",
-        SMMU0_SMMU0_SMMU0_INT9_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int9_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int9_mask",
-        SMMU0_SMMU0_SMMU0_INT9_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int9_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int9_status",
-        SMMU0_SMMU0_SMMU0_INT9_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int9_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int10_en",
-        SMMU0_SMMU0_SMMU0_INT10_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int10_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int10_mask",
-        SMMU0_SMMU0_SMMU0_INT10_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int10_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int10_status",
-        SMMU0_SMMU0_SMMU0_INT10_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int10_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int11_en",
-        SMMU0_SMMU0_SMMU0_INT11_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int11_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int11_mask",
-        SMMU0_SMMU0_SMMU0_INT11_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int11_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int11_status",
-        SMMU0_SMMU0_SMMU0_INT11_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int11_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int12_en",
-        SMMU0_SMMU0_SMMU0_INT12_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int12_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int12_mask",
-        SMMU0_SMMU0_SMMU0_INT12_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int12_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int12_status",
-        SMMU0_SMMU0_SMMU0_INT12_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int12_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int13_en",
-        SMMU0_SMMU0_SMMU0_INT13_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        20,
-        g_smmu0_smmu0_smmu0_int13_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int13_mask",
-        SMMU0_SMMU0_SMMU0_INT13_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        20,
-        g_smmu0_smmu0_smmu0_int13_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int13_status",
-        SMMU0_SMMU0_SMMU0_INT13_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        20,
-        g_smmu0_smmu0_smmu0_int13_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int14_en",
-        SMMU0_SMMU0_SMMU0_INT14_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        17,
-        g_smmu0_smmu0_smmu0_int14_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int14_mask",
-        SMMU0_SMMU0_SMMU0_INT14_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        17,
-        g_smmu0_smmu0_smmu0_int14_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int14_status",
-        SMMU0_SMMU0_SMMU0_INT14_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        17,
-        g_smmu0_smmu0_smmu0_int14_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_ecc_unmask_flag",
-        SMMU0_SMMU0_SMMU0_ECC_UNMASK_FLAGr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        22,
-        g_smmu0_smmu0_smmu0_ecc_unmask_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int15_en",
-        SMMU0_SMMU0_SMMU0_INT15_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int15_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int15_mask",
-        SMMU0_SMMU0_SMMU0_INT15_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000200,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int15_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int15_status",
-        SMMU0_SMMU0_SMMU0_INT15_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000204,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int15_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int16_en",
-        SMMU0_SMMU0_SMMU0_INT16_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000208,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int16_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int16_mask",
-        SMMU0_SMMU0_SMMU0_INT16_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000020c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int16_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int16_status",
-        SMMU0_SMMU0_SMMU0_INT16_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000210,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int16_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int17_en",
-        SMMU0_SMMU0_SMMU0_INT17_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000214,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int17_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int17_mask",
-        SMMU0_SMMU0_SMMU0_INT17_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000218,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int17_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int17_status",
-        SMMU0_SMMU0_SMMU0_INT17_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000021c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int17_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int18_en",
-        SMMU0_SMMU0_SMMU0_INT18_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000220,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int18_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int18_mask",
-        SMMU0_SMMU0_SMMU0_INT18_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000224,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int18_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int18_status",
-        SMMU0_SMMU0_SMMU0_INT18_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000228,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int18_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int19_en",
-        SMMU0_SMMU0_SMMU0_INT19_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000022c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int19_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int19_mask",
-        SMMU0_SMMU0_SMMU0_INT19_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000230,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int19_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int19_status",
-        SMMU0_SMMU0_SMMU0_INT19_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000234,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int19_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int20_en",
-        SMMU0_SMMU0_SMMU0_INT20_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000238,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int20_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int20_mask",
-        SMMU0_SMMU0_SMMU0_INT20_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000023c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int20_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int20_status",
-        SMMU0_SMMU0_SMMU0_INT20_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000240,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int20_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int21_en",
-        SMMU0_SMMU0_SMMU0_INT21_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000244,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int21_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int21_mask",
-        SMMU0_SMMU0_SMMU0_INT21_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000248,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int21_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int21_status",
-        SMMU0_SMMU0_SMMU0_INT21_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000024c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int21_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int22_en",
-        SMMU0_SMMU0_SMMU0_INT22_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000250,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int22_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int22_mask",
-        SMMU0_SMMU0_SMMU0_INT22_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000254,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int22_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int22_status",
-        SMMU0_SMMU0_SMMU0_INT22_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000258,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int22_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int23_en",
-        SMMU0_SMMU0_SMMU0_INT23_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000025c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int23_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int23_mask",
-        SMMU0_SMMU0_SMMU0_INT23_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000260,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int23_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int23_status",
-        SMMU0_SMMU0_SMMU0_INT23_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000264,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int23_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int24_en",
-        SMMU0_SMMU0_SMMU0_INT24_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000268,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int24_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int24_mask",
-        SMMU0_SMMU0_SMMU0_INT24_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000026c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int24_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int24_status",
-        SMMU0_SMMU0_SMMU0_INT24_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000270,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int24_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int25_en",
-        SMMU0_SMMU0_SMMU0_INT25_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000274,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int25_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int25_mask",
-        SMMU0_SMMU0_SMMU0_INT25_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000278,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int25_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int25_status",
-        SMMU0_SMMU0_SMMU0_INT25_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000027c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int25_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int26_en",
-        SMMU0_SMMU0_SMMU0_INT26_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000280,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int26_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int26_mask",
-        SMMU0_SMMU0_SMMU0_INT26_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000284,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int26_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int26_status",
-        SMMU0_SMMU0_SMMU0_INT26_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000288,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int26_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int27_en",
-        SMMU0_SMMU0_SMMU0_INT27_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000028c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int27_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int27_mask",
-        SMMU0_SMMU0_SMMU0_INT27_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000290,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int27_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int27_status",
-        SMMU0_SMMU0_SMMU0_INT27_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000294,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int27_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int28_en",
-        SMMU0_SMMU0_SMMU0_INT28_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000298,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int28_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int28_mask",
-        SMMU0_SMMU0_SMMU0_INT28_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000029c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int28_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int28_status",
-        SMMU0_SMMU0_SMMU0_INT28_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int28_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int29_en",
-        SMMU0_SMMU0_SMMU0_INT29_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int29_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int29_mask",
-        SMMU0_SMMU0_SMMU0_INT29_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int29_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int29_status",
-        SMMU0_SMMU0_SMMU0_INT29_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int29_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int30_en",
-        SMMU0_SMMU0_SMMU0_INT30_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int30_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int30_mask",
-        SMMU0_SMMU0_SMMU0_INT30_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int30_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int30_status",
-        SMMU0_SMMU0_SMMU0_INT30_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int30_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int31_en",
-        SMMU0_SMMU0_SMMU0_INT31_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int31_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int31_mask",
-        SMMU0_SMMU0_SMMU0_INT31_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int31_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int31_status",
-        SMMU0_SMMU0_SMMU0_INT31_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int31_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int32_en",
-        SMMU0_SMMU0_SMMU0_INT32_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int32_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int32_mask",
-        SMMU0_SMMU0_SMMU0_INT32_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int32_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int32_status",
-        SMMU0_SMMU0_SMMU0_INT32_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int32_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int33_en",
-        SMMU0_SMMU0_SMMU0_INT33_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int33_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int33_mask",
-        SMMU0_SMMU0_SMMU0_INT33_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int33_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int33_status",
-        SMMU0_SMMU0_SMMU0_INT33_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int33_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int34_en",
-        SMMU0_SMMU0_SMMU0_INT34_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int34_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int34_mask",
-        SMMU0_SMMU0_SMMU0_INT34_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int34_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int34_status",
-        SMMU0_SMMU0_SMMU0_INT34_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_smmu0_int34_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int35_en",
-        SMMU0_SMMU0_SMMU0_INT35_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int35_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int35_mask",
-        SMMU0_SMMU0_SMMU0_INT35_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int35_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int35_status",
-        SMMU0_SMMU0_SMMU0_INT35_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int35_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int36_en",
-        SMMU0_SMMU0_SMMU0_INT36_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int36_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int36_mask",
-        SMMU0_SMMU0_SMMU0_INT36_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int36_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int36_status",
-        SMMU0_SMMU0_SMMU0_INT36_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000300,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int36_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int37_en",
-        SMMU0_SMMU0_SMMU0_INT37_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000304,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int37_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int37_mask",
-        SMMU0_SMMU0_SMMU0_INT37_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000308,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int37_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int37_status",
-        SMMU0_SMMU0_SMMU0_INT37_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000030c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int37_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int38_en",
-        SMMU0_SMMU0_SMMU0_INT38_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000310,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int38_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int38_mask",
-        SMMU0_SMMU0_SMMU0_INT38_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000314,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int38_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int38_status",
-        SMMU0_SMMU0_SMMU0_INT38_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000318,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int38_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int39_en",
-        SMMU0_SMMU0_SMMU0_INT39_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000036c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int39_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int39_mask",
-        SMMU0_SMMU0_SMMU0_INT39_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000370,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int39_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int39_status",
-        SMMU0_SMMU0_SMMU0_INT39_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000374,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int39_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int40_en",
-        SMMU0_SMMU0_SMMU0_INT40_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000378,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int40_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int40_mask",
-        SMMU0_SMMU0_SMMU0_INT40_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000037c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int40_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int40_status",
-        SMMU0_SMMU0_SMMU0_INT40_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000380,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int40_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int41_en",
-        SMMU0_SMMU0_SMMU0_INT41_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000384,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int41_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int41_mask",
-        SMMU0_SMMU0_SMMU0_INT41_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000388,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int41_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int41_status",
-        SMMU0_SMMU0_SMMU0_INT41_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000038c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int41_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int42_en",
-        SMMU0_SMMU0_SMMU0_INT42_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000390,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int42_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int42_mask",
-        SMMU0_SMMU0_SMMU0_INT42_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000394,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int42_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int42_status",
-        SMMU0_SMMU0_SMMU0_INT42_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000398,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int42_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int43_en",
-        SMMU0_SMMU0_SMMU0_INT43_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000039c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int43_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int43_mask",
-        SMMU0_SMMU0_SMMU0_INT43_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int43_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int43_status",
-        SMMU0_SMMU0_SMMU0_INT43_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int43_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int44_en",
-        SMMU0_SMMU0_SMMU0_INT44_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int44_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int44_mask",
-        SMMU0_SMMU0_SMMU0_INT44_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int44_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int44_status",
-        SMMU0_SMMU0_SMMU0_INT44_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int44_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int45_en",
-        SMMU0_SMMU0_SMMU0_INT45_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int45_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int45_mask",
-        SMMU0_SMMU0_SMMU0_INT45_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int45_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int45_status",
-        SMMU0_SMMU0_SMMU0_INT45_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int45_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int46_en",
-        SMMU0_SMMU0_SMMU0_INT46_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int46_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int46_mask",
-        SMMU0_SMMU0_SMMU0_INT46_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int46_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int46_status",
-        SMMU0_SMMU0_SMMU0_INT46_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int46_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int47_en",
-        SMMU0_SMMU0_SMMU0_INT47_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int47_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int47_mask",
-        SMMU0_SMMU0_SMMU0_INT47_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int47_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int47_status",
-        SMMU0_SMMU0_SMMU0_INT47_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int47_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int48_en",
-        SMMU0_SMMU0_SMMU0_INT48_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int48_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int48_mask",
-        SMMU0_SMMU0_SMMU0_INT48_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int48_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int48_status",
-        SMMU0_SMMU0_SMMU0_INT48_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int48_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int49_en",
-        SMMU0_SMMU0_SMMU0_INT49_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int49_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int49_mask",
-        SMMU0_SMMU0_SMMU0_INT49_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int49_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int49_status",
-        SMMU0_SMMU0_SMMU0_INT49_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int49_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int50_en",
-        SMMU0_SMMU0_SMMU0_INT50_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int50_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int50_mask",
-        SMMU0_SMMU0_SMMU0_INT50_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int50_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int50_status",
-        SMMU0_SMMU0_SMMU0_INT50_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int50_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int51_en",
-        SMMU0_SMMU0_SMMU0_INT51_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int51_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int51_mask",
-        SMMU0_SMMU0_SMMU0_INT51_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000400,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int51_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int51_status",
-        SMMU0_SMMU0_SMMU0_INT51_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000404,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int51_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int52_en",
-        SMMU0_SMMU0_SMMU0_INT52_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000408,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int52_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int52_mask",
-        SMMU0_SMMU0_SMMU0_INT52_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000040c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int52_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int52_status",
-        SMMU0_SMMU0_SMMU0_INT52_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000410,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_int52_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int53_en",
-        SMMU0_SMMU0_SMMU0_INT53_ENr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000414,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_smmu0_smmu0_smmu0_int53_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int53_mask",
-        SMMU0_SMMU0_SMMU0_INT53_MASKr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000418,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_smmu0_smmu0_smmu0_int53_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_int53_status",
-        SMMU0_SMMU0_SMMU0_INT53_STATUSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000041c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_smmu0_smmu0_smmu0_int53_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl0_arbiter_ecc_bypass",
-        SMMU0_SMMU0_CTRL0_ARBITER_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000031c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl0_arbiter_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl2_arbiter_ecc_bypass",
-        SMMU0_SMMU0_CTRL2_ARBITER_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000320,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl2_arbiter_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl4_arbiter_ecc_bypass",
-        SMMU0_SMMU0_CTRL4_ARBITER_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000324,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl4_arbiter_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl6_arbiter_ecc_bypass",
-        SMMU0_SMMU0_CTRL6_ARBITER_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000328,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl6_arbiter_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl8_arbiter_ecc_bypass",
-        SMMU0_SMMU0_CTRL8_ARBITER_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000032c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl8_arbiter_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl10_arbiter_ecc_bypass",
-        SMMU0_SMMU0_CTRL10_ARBITER_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000330,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl10_arbiter_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl12_arbiter_ecc_bypass",
-        SMMU0_SMMU0_CTRL12_ARBITER_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000334,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl12_arbiter_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl14_arbiter_ecc_bypass",
-        SMMU0_SMMU0_CTRL14_ARBITER_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000338,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl14_arbiter_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl16_arbiter_ecc_bypass",
-        SMMU0_SMMU0_CTRL16_ARBITER_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000033c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl16_arbiter_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl18_arbiter_ecc_bypass",
-        SMMU0_SMMU0_CTRL18_ARBITER_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000340,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl18_arbiter_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl20_arbiter_ecc_bypass",
-        SMMU0_SMMU0_CTRL20_ARBITER_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000344,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl20_arbiter_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl22_arbiter_ecc_bypass",
-        SMMU0_SMMU0_CTRL22_ARBITER_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000348,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl22_arbiter_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl24_arbiter_ecc_bypass",
-        SMMU0_SMMU0_CTRL24_ARBITER_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000034c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl24_arbiter_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl26_arbiter_ecc_bypass",
-        SMMU0_SMMU0_CTRL26_ARBITER_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000350,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl26_arbiter_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl28_arbiter_ecc_bypass",
-        SMMU0_SMMU0_CTRL28_ARBITER_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000354,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl28_arbiter_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl30_arbiter_ecc_bypass",
-        SMMU0_SMMU0_CTRL30_ARBITER_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000358,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl30_arbiter_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_req_ecc_bypass",
-        SMMU0_SMMU0_CTRL_REQ_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000035c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_ctrl_req_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_info_ecc_bypass",
-        SMMU0_SMMU0_CTRL_INFO_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000360,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_ctrl_info_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_rschd_ecc_bypass",
-        SMMU0_SMMU0_SMMU0_RSCHD_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000368,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_rschd_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_wr_ecc_bypass",
-        SMMU0_SMMU0_SMMU0_WR_ECC_BYPASSr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000364,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_smmu0_wr_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl0_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL0_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f50,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl0_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl1_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL1_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f54,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl1_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl2_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL2_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f58,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl2_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl3_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL3_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f5c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl3_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl4_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL4_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f60,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl4_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl5_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL5_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f64,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl5_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl6_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL6_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f68,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl6_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl7_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL7_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f6c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl7_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl8_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL8_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f70,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl8_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl9_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL9_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f74,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl9_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl10_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL10_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f78,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl10_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl11_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL11_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f7c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl11_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl12_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL12_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f80,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl12_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl13_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL13_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f84,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl13_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl14_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL14_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f88,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl14_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl15_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL15_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f8c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl15_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl16_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL16_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f90,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl16_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl17_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL17_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f94,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl17_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl18_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL18_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f98,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl18_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl19_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL19_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f9c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl19_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl20_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL20_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fa0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl20_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl21_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL21_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fa4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl21_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl22_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL22_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fa8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl22_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl23_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL23_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl23_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl24_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL24_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fb0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl24_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl25_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL25_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fb4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl25_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl26_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL26_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fbc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl26_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl27_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL27_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fc0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl27_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl28_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL28_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fc4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl28_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl29_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL29_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fc8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl29_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl30_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL30_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fcc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl30_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl31_arbiter_ecc_err",
-        SMMU0_SMMU0_CTRL31_ARBITER_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fd0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_smmu0_smmu0_ctrl31_arbiter_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_req_ecc_single_err",
-        SMMU0_SMMU0_CTRL_REQ_ECC_SINGLE_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fd4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_ctrl_req_ecc_single_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_req_ecc_double_err",
-        SMMU0_SMMU0_CTRL_REQ_ECC_DOUBLE_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fd8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_ctrl_req_ecc_double_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_info_ecc_single_err",
-        SMMU0_SMMU0_CTRL_INFO_ECC_SINGLE_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fdc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_ctrl_info_ecc_single_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_info_ecc_double_err",
-        SMMU0_SMMU0_CTRL_INFO_ECC_DOUBLE_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fe0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_ctrl_info_ecc_double_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_wr_ecc_err",
-        SMMU0_SMMU0_SMMU0_WR_ECC_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fe4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_smmu0_smmu0_smmu0_wr_ecc_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_rschd_ecc_single_err",
-        SMMU0_SMMU0_SMMU0_RSCHD_ECC_SINGLE_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fe8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_rschd_ecc_single_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_rschd_ecc_double_err",
-        SMMU0_SMMU0_SMMU0_RSCHD_ECC_DOUBLE_ERRr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_rschd_ecc_double_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ord_fifo_empty",
-        SMMU0_SMMU0_ORD_FIFO_EMPTYr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000440,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_ord_fifo_empty_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "wr_arb_fifo_empty",
-        SMMU0_SMMU0_WR_ARB_FIFO_EMPTYr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000444,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_wr_arb_fifo_empty_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_fifo_empty0",
-        SMMU0_SMMU0_CTRL_FIFO_EMPTY0r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000448,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_smmu0_smmu0_ctrl_fifo_empty0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_fifo_empty1",
-        SMMU0_SMMU0_CTRL_FIFO_EMPTY1r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000044c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_smmu0_smmu0_ctrl_fifo_empty1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_fifo_empty2",
-        SMMU0_SMMU0_CTRL_FIFO_EMPTY2r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000450,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_smmu0_smmu0_ctrl_fifo_empty2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_fifo_empty3",
-        SMMU0_SMMU0_CTRL_FIFO_EMPTY3r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000454,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_smmu0_smmu0_ctrl_fifo_empty3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_fifo_empty4",
-        SMMU0_SMMU0_CTRL_FIFO_EMPTY4r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000560,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_smmu0_smmu0_ctrl_fifo_empty4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_fifo_empty5",
-        SMMU0_SMMU0_CTRL_FIFO_EMPTY5r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000564,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_smmu0_smmu0_ctrl_fifo_empty5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty0",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY0r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000458,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty1",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY1r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000045c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty2",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY2r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000460,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty3",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY3r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000464,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty4",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY4r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000468,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty5",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY5r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000046c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty6",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY6r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000470,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty7",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY7r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000474,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty8",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY8r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000478,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty9",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY9r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000047c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty10",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY10r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000480,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty11",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY11r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000484,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty12",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY12r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000488,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty13",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY13r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000048c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty14",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY14r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000490,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty15",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY15r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000494,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty16",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY16r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000498,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty17",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY17r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000049c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty18",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY18r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty19",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY19r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty19_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty20",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY20r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty20_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty21",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY21r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty21_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty22",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY22r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty22_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty23",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY23r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty23_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty24",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY24r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty24_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty25",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY25r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty25_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty26",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY26r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty27",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY27r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty27_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty28",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY28r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty28_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty29",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY29r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty29_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty30",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY30r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty30_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_empty31",
-        SMMU0_SMMU0_KSCHD_FIFO_EMPTY31r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_kschd_fifo_empty31_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty0",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY0r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty1",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY1r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty2",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY2r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty3",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY3r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty4",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY4r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty5",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY5r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty6",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY6r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty7",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY7r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty8",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY8r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty9",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY9r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty10",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY10r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000500,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty11",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY11r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000504,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty12",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY12r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000508,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty13",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY13r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000050c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty14",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY14r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000510,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty15",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY15r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000514,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty16",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY16r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000518,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty17",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY17r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000051c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty18",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY18r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000520,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty19",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY19r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000524,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty19_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty20",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY20r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000528,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty20_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty21",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY21r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000052c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty21_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty22",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY22r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000530,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty22_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty23",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY23r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000534,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty23_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty24",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY24r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000538,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty24_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty25",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY25r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000053c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty25_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty26",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY26r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000540,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty26_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty27",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY27r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000544,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty27_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty28",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY28r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000548,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty28_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty29",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY29r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000054c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty29_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty30",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY30r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000550,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty30_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty31",
-        SMMU0_SMMU0_RSCHD_FIFO_EMPTY31r,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000554,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_rschd_fifo_empty31_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ept_flag",
-        SMMU0_SMMU0_EPT_FLAGr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000558,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        9,
-        g_smmu0_smmu0_ept_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_soft_rst",
-        SMMU0_SMMU0_PPU_SOFT_RSTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000055c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_ppu_soft_rst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_as_mac_age_fc_cnt",
-        SMMU0_SMMU0_SMMU0_AS_MAC_AGE_FC_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000800,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_as_mac_age_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_marc_se_parser_fc_cnt",
-        SMMU0_SMMU0_SMMU0_MARC_SE_PARSER_FC_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000804,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_marc_se_parser_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "wr_arb_cpu_fc_cnt",
-        SMMU0_SMMU0_WR_ARB_CPU_FC_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000808,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_wr_arb_cpu_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_lpm_as_fc_cnt",
-        SMMU0_SMMU0_SMMU0_LPM_AS_FC_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000080c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_lpm_as_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_as_smmu0_fc_cnt",
-        SMMU0_SMMU0_LPM_AS_SMMU0_FC_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000810,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_lpm_as_smmu0_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_etcam1_0_as_fc_cnt",
-        SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_FC_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000814,
-        (32/8),
-        0,
-        1 + 1,
-        0,
-        4,
-        1,
-        g_smmu0_smmu0_smmu0_etcam1_0_as_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_etcam1_0_smmu0_fc_cnt",
-        SMMU0_SMMU0_AS_ETCAM1_0_SMMU0_FC_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000081c,
-        (32/8),
-        0,
-        1 + 1,
-        0,
-        4,
-        1,
-        g_smmu0_smmu0_as_etcam1_0_smmu0_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_ppu_mcast_fc_cnt",
-        SMMU0_SMMU0_SMMU0_PPU_MCAST_FC_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000824,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_ppu_mcast_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_smmu0_mcast_fc_cnt",
-        SMMU0_SMMU0_PPU_SMMU0_MCAST_FC_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000828,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_ppu_smmu0_mcast_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_smmu0_tdm_fc_rsp_fc_cnt",
-        SMMU0_SMMU0_ODMA_SMMU0_TDM_FC_RSP_FC_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000082c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_odma_smmu0_tdm_fc_rsp_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_odma_tdm_fc_key_fc_cnt",
-        SMMU0_SMMU0_SMMU0_ODMA_TDM_FC_KEY_FC_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000830,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_odma_tdm_fc_key_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_odma_fc_cnt",
-        SMMU0_SMMU0_SMMU0_ODMA_FC_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000834,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_odma_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_cfg_tab_rd_fc_cnt",
-        SMMU0_SMMU0_SMMU0_CFG_TAB_RD_FC_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000838,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_cfg_tab_rd_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_stat_fc15_0_cnt",
-        SMMU0_SMMU0_SMMU0_STAT_FC15_0_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000083c,
-        (32/8),
-        0,
-        15 + 1,
-        0,
-        4,
-        1,
-        g_smmu0_smmu0_smmu0_stat_fc15_0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_smmu0_fc15_0_cnt",
-        SMMU0_SMMU0_STAT_SMMU0_FC15_0_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000087c,
-        (32/8),
-        0,
-        15 + 1,
-        0,
-        4,
-        1,
-        g_smmu0_smmu0_stat_smmu0_fc15_0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_ppu_mex5_0_fc_cnt",
-        SMMU0_SMMU0_SMMU0_PPU_MEX5_0_FC_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008bc,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_smmu0_smmu0_smmu0_ppu_mex5_0_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_smmu0_mex5_0_fc_cnt",
-        SMMU0_SMMU0_PPU_SMMU0_MEX5_0_FC_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008d4,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_smmu0_smmu0_ppu_smmu0_mex5_0_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_smmu0_mac_age_req_cnt",
-        SMMU0_SMMU0_AS_SMMU0_MAC_AGE_REQ_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_as_smmu0_mac_age_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_parser_smmu0_marc_key_cnt",
-        SMMU0_SMMU0_SE_PARSER_SMMU0_MARC_KEY_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_se_parser_smmu0_marc_key_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_rdat_cnt",
-        SMMU0_SMMU0_CPU_IND_RDAT_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cpu_ind_rdat_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_rd_req_cnt",
-        SMMU0_SMMU0_CPU_IND_RD_REQ_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cpu_ind_rd_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wr_req_cnt",
-        SMMU0_SMMU0_CPU_IND_WR_REQ_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cpu_ind_wr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_plcr_rsp0_cnt",
-        SMMU0_SMMU0_SMMU0_PLCR_RSP0_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000900,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_plcr_rsp0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "plcr_smmu0_req0_cnt",
-        SMMU0_SMMU0_PLCR_SMMU0_REQ0_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000904,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_plcr_smmu0_req0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_lpm_as_rsp_cnt",
-        SMMU0_SMMU0_SMMU0_LPM_AS_RSP_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000908,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_lpm_as_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_as_smmu0_req_cnt",
-        SMMU0_SMMU0_LPM_AS_SMMU0_REQ_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000090c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_lpm_as_smmu0_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_etcam1_0_as_rsp_cnt",
-        SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_RSP_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000910,
-        (32/8),
-        0,
-        1 + 1,
-        0,
-        4,
-        1,
-        g_smmu0_smmu0_smmu0_etcam1_0_as_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam1_0_as_smmu0_req_cnt",
-        SMMU0_SMMU0_ETCAM1_0_AS_SMMU0_REQ_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000918,
-        (32/8),
-        0,
-        1 + 1,
-        0,
-        4,
-        1,
-        g_smmu0_smmu0_etcam1_0_as_smmu0_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_ppu_mcast_rsp_cnt",
-        SMMU0_SMMU0_SMMU0_PPU_MCAST_RSP_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000920,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_ppu_mcast_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_smmu0_mcast_key_cnt",
-        SMMU0_SMMU0_PPU_SMMU0_MCAST_KEY_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000924,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_ppu_smmu0_mcast_key_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_odma_tdm_mc_rsp_cnt",
-        SMMU0_SMMU0_SMMU0_ODMA_TDM_MC_RSP_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000928,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_odma_tdm_mc_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_smmu0_tdm_mc_key_cnt",
-        SMMU0_SMMU0_ODMA_SMMU0_TDM_MC_KEY_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000092c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_odma_smmu0_tdm_mc_key_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_odma_rsp_cnt",
-        SMMU0_SMMU0_SMMU0_ODMA_RSP_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000930,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_odma_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "odma_smmu0_cmd_cnt",
-        SMMU0_SMMU0_ODMA_SMMU0_CMD_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000934,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_odma_smmu0_cmd_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_cfg_tab_rdat_cnt",
-        SMMU0_SMMU0_SMMU0_CFG_TAB_RDAT_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000938,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_smmu0_cfg_tab_rdat_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_smmu0_tab_rd_cnt",
-        SMMU0_SMMU0_CFG_SMMU0_TAB_RD_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000093c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_cfg_smmu0_tab_rd_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_stat_rsp15_0_cnt",
-        SMMU0_SMMU0_SMMU0_STAT_RSP15_0_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000940,
-        (32/8),
-        0,
-        15 + 1,
-        0,
-        4,
-        1,
-        g_smmu0_smmu0_smmu0_stat_rsp15_0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_smmu0_req15_0_cnt",
-        SMMU0_SMMU0_STAT_SMMU0_REQ15_0_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000980,
-        (32/8),
-        0,
-        15 + 1,
-        0,
-        4,
-        1,
-        g_smmu0_smmu0_stat_smmu0_req15_0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_ppu_mex5_0_rsp_cnt",
-        SMMU0_SMMU0_SMMU0_PPU_MEX5_0_RSP_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009c0,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_smmu0_smmu0_smmu0_ppu_mex5_0_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_smmu0_mex5_0_key_cnt",
-        SMMU0_SMMU0_PPU_SMMU0_MEX5_0_KEY_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009d8,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_smmu0_smmu0_ppu_smmu0_mex5_0_key_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ftm_stat_smmu0_req0_cnt",
-        SMMU0_SMMU0_FTM_STAT_SMMU0_REQ0_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_ftm_stat_smmu0_req0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ftm_stat_smmu0_req1_cnt",
-        SMMU0_SMMU0_FTM_STAT_SMMU0_REQ1_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_ftm_stat_smmu0_req1_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_stat_smmu0_req0_cnt",
-        SMMU0_SMMU0_ETM_STAT_SMMU0_REQ0_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_etm_stat_smmu0_req0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_stat_smmu0_req1_cnt",
-        SMMU0_SMMU0_ETM_STAT_SMMU0_REQ1_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_smmu0_smmu0_etm_stat_smmu0_req1_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "req_eram0_31_rd_cnt",
-        SMMU0_SMMU0_REQ_ERAM0_31_RD_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000a00,
-        (32/8),
-        0,
-        31 + 1,
-        0,
-        8,
-        1,
-        g_smmu0_smmu0_req_eram0_31_rd_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "req_eram0_31_wr_cnt",
-        SMMU0_SMMU0_REQ_ERAM0_31_WR_CNTr,
-        SMMU0,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000a04,
-        (32/8),
-        0,
-        31 + 1,
-        0,
-        8,
-        1,
-        g_smmu0_smmu0_req_eram0_31_wr_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wdat1",
-        SE_SMMU1_DDR_WDAT1r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ddr_wdat1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wdat2",
-        SE_SMMU1_DDR_WDAT2r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ddr_wdat2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wdat3",
-        SE_SMMU1_DDR_WDAT3r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ddr_wdat3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wdat4",
-        SE_SMMU1_DDR_WDAT4r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ddr_wdat4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wdat5",
-        SE_SMMU1_DDR_WDAT5r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ddr_wdat5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wdat6",
-        SE_SMMU1_DDR_WDAT6r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ddr_wdat6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wdat7",
-        SE_SMMU1_DDR_WDAT7r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ddr_wdat7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wdat8",
-        SE_SMMU1_DDR_WDAT8r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ddr_wdat8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wdat9",
-        SE_SMMU1_DDR_WDAT9r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ddr_wdat9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wdat10",
-        SE_SMMU1_DDR_WDAT10r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ddr_wdat10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wdat11",
-        SE_SMMU1_DDR_WDAT11r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000002c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ddr_wdat11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wdat12",
-        SE_SMMU1_DDR_WDAT12r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ddr_wdat12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wdat13",
-        SE_SMMU1_DDR_WDAT13r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ddr_wdat13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wdat14",
-        SE_SMMU1_DDR_WDAT14r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ddr_wdat14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wdat15",
-        SE_SMMU1_DDR_WDAT15r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000003c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ddr_wdat15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_stat_cache_en",
-        SE_SMMU1_CNT_STAT_CACHE_ENr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cnt_stat_cache_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_stat_cache_clr",
-        SE_SMMU1_CNT_STAT_CACHE_CLRr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cnt_stat_cache_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_stat_cache_req_63_32",
-        SE_SMMU1_CNT_STAT_CACHE_REQ_63_32r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cnt_stat_cache_req_63_32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_stat_cache_req_31_0",
-        SE_SMMU1_CNT_STAT_CACHE_REQ_31_0r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cnt_stat_cache_req_31_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_stat_cache_hit_63_32",
-        SE_SMMU1_CNT_STAT_CACHE_HIT_63_32r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cnt_stat_cache_hit_63_32_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_stat_cache_hit_31_0",
-        SE_SMMU1_CNT_STAT_CACHE_HIT_31_0r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cnt_stat_cache_hit_31_0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_cmd0",
-        SE_SMMU1_DDR_CMD0r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_se_smmu1_ddr_cmd0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_addr",
-        SE_SMMU1_INFO_ADDRr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_info_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_cmd1",
-        SE_SMMU1_DDR_CMD1r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_smmu1_ddr_cmd1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "clr_start_addr",
-        SE_SMMU1_CLR_START_ADDRr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000006c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_clr_start_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "clr_end_addr",
-        SE_SMMU1_CLR_END_ADDRr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000070,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_clr_end_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "clr_tbl_en",
-        SE_SMMU1_CLR_TBL_ENr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000074,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_smmu1_clr_tbl_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_mode",
-        SE_SMMU1_DEBUG_CNT_MODEr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_smmu1_debug_cnt_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "init_done",
-        SE_SMMU1_INIT_DONEr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_se_smmu1_init_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rsp_rd_done",
-        SE_SMMU1_CPU_RSP_RD_DONEr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000008c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rsp_rd_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ksch_oam_sp_en",
-        SE_SMMU1_KSCH_OAM_SP_ENr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ksch_oam_sp_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_cache_en",
-        SE_SMMU1_CFG_CACHE_ENr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cfg_cache_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cache_age_en",
-        SE_SMMU1_CACHE_AGE_ENr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cache_age_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat0",
-        SE_SMMU1_CPU_RDAT0r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rdat0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat1",
-        SE_SMMU1_CPU_RDAT1r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rdat1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat2",
-        SE_SMMU1_CPU_RDAT2r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rdat2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat3",
-        SE_SMMU1_CPU_RDAT3r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rdat3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat4",
-        SE_SMMU1_CPU_RDAT4r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rdat4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat5",
-        SE_SMMU1_CPU_RDAT5r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rdat5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat6",
-        SE_SMMU1_CPU_RDAT6r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rdat6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat7",
-        SE_SMMU1_CPU_RDAT7r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rdat7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat8",
-        SE_SMMU1_CPU_RDAT8r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rdat8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat9",
-        SE_SMMU1_CPU_RDAT9r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rdat9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat10",
-        SE_SMMU1_CPU_RDAT10r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rdat10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat11",
-        SE_SMMU1_CPU_RDAT11r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rdat11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat12",
-        SE_SMMU1_CPU_RDAT12r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rdat12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat13",
-        SE_SMMU1_CPU_RDAT13r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rdat13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat14",
-        SE_SMMU1_CPU_RDAT14r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rdat14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rdat15",
-        SE_SMMU1_CPU_RDAT15r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rdat15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_cpu_rd_rdy",
-        SE_SMMU1_CTRL_CPU_RD_RDYr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000100,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ctrl_cpu_rd_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_warbi_rdy_cfg",
-        SE_SMMU1_CPU_WARBI_RDY_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000104,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_warbi_rdy_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dir_arbi_cpu_rpful",
-        SE_SMMU1_DIR_ARBI_CPU_RPFULr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000108,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_smmu1_dir_arbi_cpu_rpful_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dir_arbi_wpful",
-        SE_SMMU1_DIR_ARBI_WPFULr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000110,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_smmu1_dir_arbi_wpful_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_wr_arbi_pful0",
-        SE_SMMU1_CFG_WR_ARBI_PFUL0r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000118,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_smmu1_cfg_wr_arbi_pful0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_wr_arbi_pful1",
-        SE_SMMU1_CFG_WR_ARBI_PFUL1r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000011c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_smmu1_cfg_wr_arbi_pful1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_wdone_pful_cfg",
-        SE_SMMU1_SMMU1_WDONE_PFUL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000124,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_wdone_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_rate_cfg_cnt",
-        SE_SMMU1_STAT_RATE_CFG_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000128,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_stat_rate_cfg_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ftm_rate_cfg_cnt",
-        SE_SMMU1_FTM_RATE_CFG_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000012c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ftm_rate_cfg_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_rate_cfg_cnt",
-        SE_SMMU1_ETM_RATE_CFG_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000130,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_etm_rate_cfg_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dir_rate_cfg_cnt",
-        SE_SMMU1_DIR_RATE_CFG_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000134,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_dir_rate_cfg_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_rate_cfg_cnt",
-        SE_SMMU1_HASH_RATE_CFG_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000138,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_hash_rate_cfg_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ftm_tbl_cfg",
-        SE_SMMU1_FTM_TBL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ftm_tbl_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_v4_as_tbl_cfg",
-        SE_SMMU1_LPM_V4_AS_TBL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_se_smmu1_lpm_v4_as_tbl_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_v4_tbl_cfg",
-        SE_SMMU1_LPM_V4_TBL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_se_smmu1_lpm_v4_tbl_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_v6_tbl_cfg",
-        SE_SMMU1_LPM_V6_TBL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_se_smmu1_lpm_v6_tbl_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_v6_as_tbl_cfg",
-        SE_SMMU1_LPM_V6_AS_TBL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_se_smmu1_lpm_v6_as_tbl_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_tbl_cfg",
-        SE_SMMU1_DMA_TBL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_dma_tbl_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_tbl_cfg",
-        SE_SMMU1_OAM_TBL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_oam_tbl_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_rpar_cpu_pful",
-        SE_SMMU1_CTRL_RPAR_CPU_PFULr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ctrl_rpar_cpu_pful_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ksch_dir_pful",
-        SE_SMMU1_CFG_KSCH_DIR_PFULr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cfg_ksch_dir_pful_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ksch_hash_pful",
-        SE_SMMU1_CFG_KSCH_HASH_PFULr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cfg_ksch_hash_pful_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ksch_lpm_pful",
-        SE_SMMU1_CFG_KSCH_LPM_PFULr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cfg_ksch_lpm_pful_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ksch_lpm_as_pful",
-        SE_SMMU1_CFG_KSCH_LPM_AS_PFULr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cfg_ksch_lpm_as_pful_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ksch_stat_pful",
-        SE_SMMU1_CFG_KSCH_STAT_PFULr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cfg_ksch_stat_pful_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ksch_tm_pful",
-        SE_SMMU1_CFG_KSCH_TM_PFULr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000200,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cfg_ksch_tm_pful_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ksch_oam_pful",
-        SE_SMMU1_CFG_KSCH_OAM_PFULr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000204,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cfg_ksch_oam_pful_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ksch_dma_pful",
-        SE_SMMU1_CFG_KSCH_DMA_PFULr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000208,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cfg_ksch_dma_pful_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_wfifo_cfg",
-        SE_SMMU1_CTRL_WFIFO_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000230,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ctrl_wfifo_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsch_hash_ptr_cfg",
-        SE_SMMU1_RSCH_HASH_PTR_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000240,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_rsch_hash_ptr_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsch_lpm_ptr_cfg",
-        SE_SMMU1_RSCH_LPM_PTR_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000244,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_rsch_lpm_ptr_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsch_lpm_as_ptr_cfg",
-        SE_SMMU1_RSCH_LPM_AS_PTR_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000248,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_rsch_lpm_as_ptr_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsch_stat_ptr_cfg",
-        SE_SMMU1_RSCH_STAT_PTR_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000024c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_rsch_stat_ptr_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rsch_oam_ptr_cfg",
-        SE_SMMU1_RSCH_OAM_PTR_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000250,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_rsch_oam_ptr_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_pept_cfg",
-        SE_SMMU1_RSCHD_FIFO_PEPT_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000254,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_rschd_fifo_pept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dir_fifo_pful_cfg",
-        SE_SMMU1_DIR_FIFO_PFUL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000258,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_dir_fifo_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash_fifo_pful_cfg",
-        SE_SMMU1_HASH_FIFO_PFUL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000025c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_hash_fifo_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_fifo_pful_cfg",
-        SE_SMMU1_LPM_FIFO_PFUL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000260,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_lpm_fifo_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_as_fifo_pful_cfg",
-        SE_SMMU1_LPM_AS_FIFO_PFUL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000264,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_lpm_as_fifo_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_fifo_pful_cfg",
-        SE_SMMU1_STAT_FIFO_PFUL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000268,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_stat_fifo_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ftm_fifo_pful_cfg",
-        SE_SMMU1_FTM_FIFO_PFUL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000026c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ftm_fifo_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_fifo_pful_cfg",
-        SE_SMMU1_ETM_FIFO_PFUL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000270,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_etm_fifo_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_fifo_pful_cfg",
-        SE_SMMU1_OAM_FIFO_PFUL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000274,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_oam_fifo_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_fifo_pful_cfg",
-        SE_SMMU1_DMA_FIFO_PFUL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000278,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_dma_fifo_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cache_rsp_rr_fifo_cfg",
-        SE_SMMU1_CACHE_RSP_RR_FIFO_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000027c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_smmu1_cache_rsp_rr_fifo_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_rsp_rr_fifo_cfg",
-        SE_SMMU1_DDR_RSP_RR_FIFO_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000280,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_smmu1_ddr_rsp_rr_fifo_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_cahce_fifo_cfg",
-        SE_SMMU1_CPU_CAHCE_FIFO_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000284,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_smmu1_cpu_cahce_fifo_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cache_rsp_fifo_cfg",
-        SE_SMMU1_CACHE_RSP_FIFO_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000028c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_smmu1_cache_rsp_fifo_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_state",
-        SE_SMMU1_TEST_STATEr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000002c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_test_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cache_fifo_ept",
-        SE_SMMU1_CACHE_FIFO_EPTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000002f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cache_fifo_ept_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rr_fifo_ept",
-        SE_SMMU1_RR_FIFO_EPTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000002fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_rr_fifo_ept_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "wr_fifo_ept",
-        SE_SMMU1_WR_FIFO_EPTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000304,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_wr_fifo_ept_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "wdone_fifo_ept",
-        SE_SMMU1_WDONE_FIFO_EPTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000308,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_wdone_fifo_ept_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_fifo_ept0",
-        SE_SMMU1_KSCHD_FIFO_EPT0r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000318,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_kschd_fifo_ept0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cash_fifo_ept",
-        SE_SMMU1_CASH_FIFO_EPTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000031c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cash_fifo_ept_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_fifo_ept",
-        SE_SMMU1_CTRL_FIFO_EPTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000320,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ctrl_fifo_ept_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_rschd_ept3",
-        SE_SMMU1_SMMU1_RSCHD_EPT3r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000324,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_rschd_ept3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_rschd_ept2",
-        SE_SMMU1_SMMU1_RSCHD_EPT2r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000328,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_rschd_ept2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_rschd_ept1",
-        SE_SMMU1_SMMU1_RSCHD_EPT1r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000032c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_rschd_ept1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_rschd_ept0",
-        SE_SMMU1_SMMU1_RSCHD_EPT0r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000330,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_rschd_ept0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cash0_ecc_err_addr",
-        SE_SMMU1_CASH0_ECC_ERR_ADDRr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000334,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cash0_ecc_err_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "arbi_cpu_wr_rdy",
-        SE_SMMU1_ARBI_CPU_WR_RDYr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000354,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_arbi_cpu_wr_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_int_0_en",
-        SE_SMMU1_SMMU1_INT_0_ENr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000480,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_int_0_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_int_0_mask",
-        SE_SMMU1_SMMU1_INT_0_MASKr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000484,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_int_0_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_int_1_en",
-        SE_SMMU1_SMMU1_INT_1_ENr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000488,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_int_1_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_int_1_mask",
-        SE_SMMU1_SMMU1_INT_1_MASKr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000048c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_int_1_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_int_2_en",
-        SE_SMMU1_SMMU1_INT_2_ENr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000490,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_int_2_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_int_2_mask",
-        SE_SMMU1_SMMU1_INT_2_MASKr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000494,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_int_2_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_int_3_en",
-        SE_SMMU1_SMMU1_INT_3_ENr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000498,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_int_3_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_int_3_mask",
-        SE_SMMU1_SMMU1_INT_3_MASKr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000049c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_int_3_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_int_0_status",
-        SE_SMMU1_SMMU1_INT_0_STATUSr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000540,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_int_0_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_int_1_status",
-        SE_SMMU1_SMMU1_INT_1_STATUSr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000544,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_int_1_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_int_2_status",
-        SE_SMMU1_SMMU1_INT_2_STATUSr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000548,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_int_2_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_int_3_status",
-        SE_SMMU1_SMMU1_INT_3_STATUSr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000054c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_int_3_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_int_status",
-        SE_SMMU1_SMMU1_INT_STATUSr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000005a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_to_cash7_0_fc_cnt",
-        SE_SMMU1_CTRL_TO_CASH7_0_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000600,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        24,
-        1,
-        g_se_smmu1_ctrl_to_cash7_0_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cash7_0_to_ctrl_req_cnt",
-        SE_SMMU1_CASH7_0_TO_CTRL_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000604,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        24,
-        1,
-        g_se_smmu1_cash7_0_to_ctrl_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_to_cache7_fc_cnt",
-        SE_SMMU1_RSCHD_TO_CACHE7_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000608,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        24,
-        1,
-        g_se_smmu1_rschd_to_cache7_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cash7_to_cache_rsp_cnt",
-        SE_SMMU1_CASH7_TO_CACHE_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000060c,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        24,
-        1,
-        g_se_smmu1_cash7_to_cache_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cash7_to_ctrl_fc_cnt",
-        SE_SMMU1_CASH7_TO_CTRL_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000610,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        24,
-        1,
-        g_se_smmu1_cash7_to_ctrl_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl_to_cash7_0_rsp_cnt",
-        SE_SMMU1_CTRL_TO_CASH7_0_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000614,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        24,
-        1,
-        g_se_smmu1_ctrl_to_cash7_0_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_to_cache7_0_req_cnt",
-        SE_SMMU1_KSCHD_TO_CACHE7_0_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000006c0,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_kschd_to_cache7_0_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cache7_0_to_kschd_fc_cnt",
-        SE_SMMU1_CACHE7_0_TO_KSCHD_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000006e0,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_cache7_0_to_kschd_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dma_to_smmu1_rd_req_cnt",
-        SE_SMMU1_DMA_TO_SMMU1_RD_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000700,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_dma_to_smmu1_rd_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_to_kschd_req_cnt",
-        SE_SMMU1_OAM_TO_KSCHD_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000704,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_oam_to_kschd_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_rr_state_rsp_cnt",
-        SE_SMMU1_OAM_RR_STATE_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000708,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_oam_rr_state_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_clash_info_cnt",
-        SE_SMMU1_OAM_CLASH_INFO_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000070c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_oam_clash_info_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_to_rr_req_cnt",
-        SE_SMMU1_OAM_TO_RR_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000710,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_oam_to_rr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_as_to_kschd_req_cnt",
-        SE_SMMU1_LPM_AS_TO_KSCHD_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000714,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_lpm_as_to_kschd_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_as_rr_state_rsp_cnt",
-        SE_SMMU1_LPM_AS_RR_STATE_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000718,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_lpm_as_rr_state_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_as_clash_info_cnt",
-        SE_SMMU1_LPM_AS_CLASH_INFO_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000071c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_lpm_as_clash_info_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_as_to_rr_req_cnt",
-        SE_SMMU1_LPM_AS_TO_RR_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000720,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_lpm_as_to_rr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_to_kschd_req_cnt",
-        SE_SMMU1_LPM_TO_KSCHD_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000724,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_lpm_to_kschd_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_rr_state_rsp_cnt",
-        SE_SMMU1_LPM_RR_STATE_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000728,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_lpm_rr_state_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_clash_info_cnt",
-        SE_SMMU1_LPM_CLASH_INFO_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000072c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_lpm_clash_info_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_to_rr_req_cnt",
-        SE_SMMU1_LPM_TO_RR_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000730,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_lpm_to_rr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_0_to_kschd_req_cnt",
-        SE_SMMU1_HASH3_0_TO_KSCHD_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000734,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        16,
-        1,
-        g_se_smmu1_hash3_0_to_kschd_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_0_rr_state_rsp_cnt",
-        SE_SMMU1_HASH3_0_RR_STATE_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000738,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        16,
-        1,
-        g_se_smmu1_hash3_0_rr_state_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_0_clash_info_cnt",
-        SE_SMMU1_HASH3_0_CLASH_INFO_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000073c,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        16,
-        1,
-        g_se_smmu1_hash3_0_clash_info_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_0_to_rr_req_cnt",
-        SE_SMMU1_HASH3_0_TO_RR_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000740,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        16,
-        1,
-        g_se_smmu1_hash3_0_to_rr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dir3_0_to_kschd_req_cnt",
-        SE_SMMU1_DIR3_0_TO_KSCHD_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000774,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        8,
-        1,
-        g_se_smmu1_dir3_0_to_kschd_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dir3_0_clash_info_cnt",
-        SE_SMMU1_DIR3_0_CLASH_INFO_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000778,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        8,
-        1,
-        g_se_smmu1_dir3_0_clash_info_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dir_tbl_wr_req_cnt",
-        SE_SMMU1_DIR_TBL_WR_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000794,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_dir_tbl_wr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "warbi_to_dir_tbl_warbi_fc_cnt",
-        SE_SMMU1_WARBI_TO_DIR_TBL_WARBI_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000798,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_warbi_to_dir_tbl_warbi_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dir3_0_to_bank_rr_req_cnt",
-        SE_SMMU1_DIR3_0_TO_BANK_RR_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000079c,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_dir3_0_to_bank_rr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "kschd_to_dir3_0_fc_cnt",
-        SE_SMMU1_KSCHD_TO_DIR3_0_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007ac,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_kschd_to_dir3_0_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dir3_0_rr_state_rsp_cnt",
-        SE_SMMU1_DIR3_0_RR_STATE_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007bc,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_dir3_0_rr_state_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "wr_done_to_warbi_fc_cnt",
-        SE_SMMU1_WR_DONE_TO_WARBI_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_wr_done_to_warbi_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "wr_done_ptr_req_cnt",
-        SE_SMMU1_WR_DONE_PTR_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_wr_done_ptr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl7_0_to_warbi_fc_cnt",
-        SE_SMMU1_CTRL7_0_TO_WARBI_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007d4,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_ctrl7_0_to_warbi_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "warbi_to_ctrl7_0_wr_req_cnt",
-        SE_SMMU1_WARBI_TO_CTRL7_0_WR_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007f4,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_warbi_to_ctrl7_0_wr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "warbi_to_cash7_0_wr_req_cnt",
-        SE_SMMU1_WARBI_TO_CASH7_0_WR_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000814,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_warbi_to_cash7_0_wr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "warbi_to_cpu_wr_fc_cnt",
-        SE_SMMU1_WARBI_TO_CPU_WR_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000834,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_warbi_to_cpu_wr_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_wr_req_cnt",
-        SE_SMMU1_CPU_WR_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000838,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_wr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ctrl7_0_to_cpu_rd_rsp_cnt",
-        SE_SMMU1_CTRL7_0_TO_CPU_RD_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000083c,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_ctrl7_0_to_cpu_rd_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_to_ctrl7_0_rd_req_cnt",
-        SE_SMMU1_CPU_TO_CTRL7_0_RD_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000085c,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_cpu_to_ctrl7_0_rd_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_dir_tbl_rsp_cnt",
-        SE_SMMU1_CPU_RD_DIR_TBL_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000087c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_rd_dir_tbl_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_to_dir_tbl_rd_wr_req_cnt",
-        SE_SMMU1_CPU_TO_DIR_TBL_RD_WR_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000880,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_cpu_to_dir_tbl_rd_wr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_mmu_7_0_rsp_fc_cnt",
-        SE_SMMU1_SMMU1_TO_MMU_7_0_RSP_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000884,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        24,
-        1,
-        g_se_smmu1_smmu1_to_mmu_7_0_rsp_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mmu_7_0_to_smmu1_rd_rsp_cnt",
-        SE_SMMU1_MMU_7_0_TO_SMMU1_RD_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000888,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        24,
-        1,
-        g_se_smmu1_mmu_7_0_to_smmu1_rd_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mmu_7_0_to_smmu1_rd_fc_cnt",
-        SE_SMMU1_MMU_7_0_TO_SMMU1_RD_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000088c,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        24,
-        1,
-        g_se_smmu1_mmu_7_0_to_smmu1_rd_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_mmu_7_rd_req_cnt",
-        SE_SMMU1_SMMU1_TO_MMU_7_RD_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000890,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        24,
-        1,
-        g_se_smmu1_smmu1_to_mmu_7_rd_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "mmu_7_to_smmu1_wr_fc_cnt",
-        SE_SMMU1_MMU_7_TO_SMMU1_WR_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000894,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        24,
-        1,
-        g_se_smmu1_mmu_7_to_smmu1_wr_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_mmu_7_0_wr_req_cnt",
-        SE_SMMU1_SMMU1_TO_MMU_7_0_WR_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000898,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        24,
-        1,
-        g_se_smmu1_smmu1_to_mmu_7_0_wr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_to_smmu1_wr_rsp_fc_cnt",
-        SE_SMMU1_SE_TO_SMMU1_WR_RSP_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000944,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_se_to_smmu1_wr_rsp_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_se_wr_rsp_cnt",
-        SE_SMMU1_SMMU1_TO_SE_WR_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000948,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_se_wr_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr7_0_wr_rsp_cnt",
-        SE_SMMU1_DDR7_0_WR_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000094c,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_ddr7_0_wr_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_as_fc_cnt",
-        SE_SMMU1_SMMU1_TO_AS_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000096c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_as_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_to_smmu1_wr_req_cnt",
-        SE_SMMU1_AS_TO_SMMU1_WR_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000970,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_as_to_smmu1_wr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_se_parser_fc_cnt",
-        SE_SMMU1_SMMU1_TO_SE_PARSER_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000974,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_se_parser_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_parser_to_smmu1_req_cnt",
-        SE_SMMU1_SE_PARSER_TO_SMMU1_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000978,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_se_parser_to_smmu1_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_etm_wr_fc_cnt",
-        SE_SMMU1_SMMU1_TO_ETM_WR_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000097c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_etm_wr_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_wr_req_cnt",
-        SE_SMMU1_ETM_WR_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000980,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_etm_wr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_ftm_wr_fc_cnt",
-        SE_SMMU1_SMMU1_TO_FTM_WR_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000984,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_ftm_wr_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ftm_wr_req_cnt",
-        SE_SMMU1_FTM_WR_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000988,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ftm_wr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_state_wr_fc_cnt",
-        SE_SMMU1_SMMU1_TO_STATE_WR_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000098c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_state_wr_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "state_wr_req_cnt",
-        SE_SMMU1_STATE_WR_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000990,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_state_wr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_to_dma_rsp_cnt",
-        SE_SMMU1_SE_TO_DMA_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000994,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_se_to_dma_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_to_dma_fc_cnt",
-        SE_SMMU1_SE_TO_DMA_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000998,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_se_to_dma_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_to_smmu1_fc_cnt",
-        SE_SMMU1_OAM_TO_SMMU1_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000099c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_oam_to_smmu1_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_oam_rsp_cnt",
-        SE_SMMU1_SMMU1_TO_OAM_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_oam_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_oam_fc_cnt",
-        SE_SMMU1_SMMU1_TO_OAM_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_oam_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_to_smmu1_req_cnt",
-        SE_SMMU1_OAM_TO_SMMU1_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_oam_to_smmu1_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_etm_rsp_cnt",
-        SE_SMMU1_SMMU1_TO_ETM_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_etm_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_ftm_rsp_cnt",
-        SE_SMMU1_SMMU1_TO_FTM_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_ftm_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_etm_fc_cnt",
-        SE_SMMU1_SMMU1_TO_ETM_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_etm_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_to_smmu1_req_cnt",
-        SE_SMMU1_ETM_TO_SMMU1_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_etm_to_smmu1_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_ftm_fc_cnt",
-        SE_SMMU1_SMMU1_TO_FTM_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_ftm_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ftm_to_smmu1_req_cnt",
-        SE_SMMU1_FTM_TO_SMMU1_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_ftm_to_smmu1_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_stat_rsp_cnt",
-        SE_SMMU1_SMMU1_TO_STAT_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_stat_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_stat_fc_cnt",
-        SE_SMMU1_SMMU1_TO_STAT_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_stat_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_to_smmu1_req_cnt",
-        SE_SMMU1_STAT_TO_SMMU1_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_stat_to_smmu1_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_as_to_smmu1_fc_cnt",
-        SE_SMMU1_LPM_AS_TO_SMMU1_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_lpm_as_to_smmu1_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_to_smmu1_fc_cnt",
-        SE_SMMU1_LPM_TO_SMMU1_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_lpm_to_smmu1_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_lpm_as_rsp_cnt",
-        SE_SMMU1_SMMU1_TO_LPM_AS_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_lpm_as_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_lpm_rsp_cnt",
-        SE_SMMU1_SMMU1_TO_LPM_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_lpm_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_lpm_as_fc_cnt",
-        SE_SMMU1_SMMU1_TO_LPM_AS_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_lpm_as_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_lpm_fc_cnt",
-        SE_SMMU1_SMMU1_TO_LPM_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_smmu1_to_lpm_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_as_to_smmu1_req_cnt",
-        SE_SMMU1_LPM_AS_TO_SMMU1_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_lpm_as_to_smmu1_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "lpm_to_smmu1_req_cnt",
-        SE_SMMU1_LPM_TO_SMMU1_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_smmu1_lpm_to_smmu1_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_0_to_smmu1_fc_cnt",
-        SE_SMMU1_HASH3_0_TO_SMMU1_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009f0,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_hash3_0_to_smmu1_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_hash3_0_rsp_cnt",
-        SE_SMMU1_SMMU1_TO_HASH3_0_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a00,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_smmu1_to_hash3_0_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_hash3_0_fc_cnt",
-        SE_SMMU1_SMMU1_TO_HASH3_0_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a10,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_smmu1_to_hash3_0_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash3_0_to_smmu1_cnt",
-        SE_SMMU1_HASH3_0_TO_SMMU1_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a20,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_hash3_0_to_smmu1_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_to_smmu1_dir3_0_rsp_fc_cnt",
-        SE_SMMU1_SE_TO_SMMU1_DIR3_0_RSP_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a30,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_se_to_smmu1_dir3_0_rsp_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_se_dir3_0_rsp_cnt",
-        SE_SMMU1_SMMU1_TO_SE_DIR3_0_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a40,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_smmu1_to_se_dir3_0_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu1_to_se_dir3_0_fc_cnt",
-        SE_SMMU1_SMMU1_TO_SE_DIR3_0_FC_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a50,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_smmu1_to_se_dir3_0_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_to_smmu1_dir3_0_cnt",
-        SE_SMMU1_SE_TO_SMMU1_DIR3_0_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a60,
-        (32/8),
-        0,
-        3 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_se_to_smmu1_dir3_0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cache7_0_to_rschd_rsp_cnt",
-        SE_SMMU1_CACHE7_0_TO_RSCHD_RSP_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a70,
-        (32/8),
-        0,
-        7 + 1,
-        0,
-        4,
-        1,
-        g_se_smmu1_cache7_0_to_rschd_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_rw_addr",
-        SE_CMMU_DDR_RW_ADDRr,
-        SMMU1,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_ddr_rw_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_rw_mode",
-        SE_CMMU_DDR_RW_MODEr,
-        SMMU1,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_cmmu_ddr_rw_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cp_cmd",
-        SE_CMMU_CP_CMDr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_cp_cmd_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_rd_done",
-        SE_CMMU_CPU_IND_RD_DONEr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_cpu_ind_rd_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_rdat0",
-        SE_CMMU_CPU_IND_RDAT0r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_cpu_ind_rdat0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_rdat1",
-        SE_CMMU_CPU_IND_RDAT1r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_cpu_ind_rdat1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_rdat2",
-        SE_CMMU_CPU_IND_RDAT2r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_cpu_ind_rdat2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_rdat3",
-        SE_CMMU_CPU_IND_RDAT3r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000002c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_cpu_ind_rdat3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ddr_fifo_almful",
-        SE_CMMU_CPU_DDR_FIFO_ALMFULr,
-        SMMU1,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_cpu_ddr_fifo_almful_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_mode",
-        SE_CMMU_DEBUG_CNT_MODEr,
-        SMMU1,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_cmmu_debug_cnt_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cmmu_pful_cfg",
-        SE_CMMU_CMMU_PFUL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_cmmu_cmmu_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cmmu_stat_pful_cfg",
-        SE_CMMU_CMMU_STAT_PFUL_CFGr,
-        SMMU1,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000003c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_se_cmmu_cmmu_stat_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_overflow_mode",
-        SE_CMMU_STAT_OVERFLOW_MODEr,
-        SMMU1,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_stat_overflow_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cmmu_cp_fifo_pful",
-        SE_CMMU_CMMU_CP_FIFO_PFULr,
-        SMMU1,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_cmmu_cp_fifo_pful_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wr_dat0",
-        SE_CMMU_DDR_WR_DAT0r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000078,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_ddr_wr_dat0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_wr_dat1",
-        SE_CMMU_DDR_WR_DAT1r,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000007c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_ddr_wr_dat1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cmmu_int_unmask_flag",
-        SE_CMMU_CMMU_INT_UNMASK_FLAGr,
-        SMMU1,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_cmmu_int_unmask_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cmmu_int_en",
-        SE_CMMU_CMMU_INT_ENr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        13,
-        g_se_cmmu_cmmu_int_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cmmu_int_mask",
-        SE_CMMU_CMMU_INT_MASKr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        13,
-        g_se_cmmu_cmmu_int_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cmmu_int_status",
-        SE_CMMU_CMMU_INT_STATUSr,
-        SMMU1,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000008c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        13,
-        g_se_cmmu_cmmu_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_cmmu_req_cnt",
-        SE_CMMU_STAT_CMMU_REQ_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000400,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_stat_cmmu_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cmmu_fc0_cnt",
-        SE_CMMU_CMMU_FC0_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000404,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_cmmu_fc0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cmmu_fc1_cnt",
-        SE_CMMU_CMMU_FC1_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000408,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_cmmu_fc1_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cmmu_fc2_cnt",
-        SE_CMMU_CMMU_FC2_CNTr,
-        SMMU1,
-        DPP_REG_FLAG_INDIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000040c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_se_cmmu_cmmu_fc2_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hash0_tbl0_cfg",
-        SMMU14K_SE_SMMU1_HASH0_TBL0_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000148,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash0_tbl0_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash0_tbl1_cfg",
-        SMMU14K_SE_SMMU1_HASH0_TBL1_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000014c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash0_tbl1_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash0_tbl2_cfg",
-        SMMU14K_SE_SMMU1_HASH0_TBL2_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000150,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash0_tbl2_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash0_tbl3_cfg",
-        SMMU14K_SE_SMMU1_HASH0_TBL3_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000154,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash0_tbl3_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash0_tbl4_cfg",
-        SMMU14K_SE_SMMU1_HASH0_TBL4_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000158,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash0_tbl4_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash0_tbl5_cfg",
-        SMMU14K_SE_SMMU1_HASH0_TBL5_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000015c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash0_tbl5_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash0_tbl6_cfg",
-        SMMU14K_SE_SMMU1_HASH0_TBL6_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000160,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash0_tbl6_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash0_tbl7_cfg",
-        SMMU14K_SE_SMMU1_HASH0_TBL7_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000164,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash0_tbl7_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash1_tbl0_cfg",
-        SMMU14K_SE_SMMU1_HASH1_TBL0_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000168,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash1_tbl0_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash1_tbl1_cfg",
-        SMMU14K_SE_SMMU1_HASH1_TBL1_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000016c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash1_tbl1_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash1_tbl2_cfg",
-        SMMU14K_SE_SMMU1_HASH1_TBL2_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000170,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash1_tbl2_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash1_tbl3_cfg",
-        SMMU14K_SE_SMMU1_HASH1_TBL3_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000174,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash1_tbl3_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash1_tbl4_cfg",
-        SMMU14K_SE_SMMU1_HASH1_TBL4_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000178,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash1_tbl4_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash1_tbl5_cfg",
-        SMMU14K_SE_SMMU1_HASH1_TBL5_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000017c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash1_tbl5_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash1_tbl6_cfg",
-        SMMU14K_SE_SMMU1_HASH1_TBL6_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000180,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash1_tbl6_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash1_tbl7_cfg",
-        SMMU14K_SE_SMMU1_HASH1_TBL7_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000184,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash1_tbl7_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash2_tbl0_cfg",
-        SMMU14K_SE_SMMU1_HASH2_TBL0_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000188,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash2_tbl0_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash2_tbl1_cfg",
-        SMMU14K_SE_SMMU1_HASH2_TBL1_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000018c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash2_tbl1_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash2_tbl2_cfg",
-        SMMU14K_SE_SMMU1_HASH2_TBL2_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000190,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash2_tbl2_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash2_tbl3_cfg",
-        SMMU14K_SE_SMMU1_HASH2_TBL3_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000194,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash2_tbl3_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash2_tbl4_cfg",
-        SMMU14K_SE_SMMU1_HASH2_TBL4_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000198,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash2_tbl4_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash2_tbl5_cfg",
-        SMMU14K_SE_SMMU1_HASH2_TBL5_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000019c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash2_tbl5_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash2_tbl6_cfg",
-        SMMU14K_SE_SMMU1_HASH2_TBL6_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash2_tbl6_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash2_tbl7_cfg",
-        SMMU14K_SE_SMMU1_HASH2_TBL7_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash2_tbl7_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash3_tbl0_cfg",
-        SMMU14K_SE_SMMU1_HASH3_TBL0_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash3_tbl0_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash3_tbl1_cfg",
-        SMMU14K_SE_SMMU1_HASH3_TBL1_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash3_tbl1_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash3_tbl2_cfg",
-        SMMU14K_SE_SMMU1_HASH3_TBL2_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash3_tbl2_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash3_tbl3_cfg",
-        SMMU14K_SE_SMMU1_HASH3_TBL3_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash3_tbl3_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash3_tbl4_cfg",
-        SMMU14K_SE_SMMU1_HASH3_TBL4_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash3_tbl4_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash3_tbl5_cfg",
-        SMMU14K_SE_SMMU1_HASH3_TBL5_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash3_tbl5_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash3_tbl6_cfg",
-        SMMU14K_SE_SMMU1_HASH3_TBL6_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash3_tbl6_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "hash3_tbl7_cfg",
-        SMMU14K_SE_SMMU1_HASH3_TBL7_CFGr,
-        SMMU14K,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_smmu14k_se_smmu1_hash3_tbl7_cfg_reg,
-        dpp_se_write,
-        dpp_se_read,
-    },
-    {
-        "cpu_ind_eram_wdat1",
-        STAT_STAT_CFG_CPU_IND_ERAM_WDAT1r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_eram_wdat1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_eram_wdat2",
-        STAT_STAT_CFG_CPU_IND_ERAM_WDAT2r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_eram_wdat2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_eram_wdat3",
-        STAT_STAT_CFG_CPU_IND_ERAM_WDAT3r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_eram_wdat3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_eram_req_info",
-        STAT_STAT_CFG_CPU_IND_ERAM_REQ_INFOr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_stat_stat_cfg_cpu_ind_eram_req_info_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_eram_rd_done",
-        STAT_STAT_CFG_CPU_IND_ERAM_RD_DONEr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_eram_rd_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_eram_rdat0",
-        STAT_STAT_CFG_CPU_IND_ERAM_RDAT0r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_eram_rdat0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_eram_rdat1",
-        STAT_STAT_CFG_CPU_IND_ERAM_RDAT1r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_eram_rdat1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_eram_rdat2",
-        STAT_STAT_CFG_CPU_IND_ERAM_RDAT2r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_eram_rdat2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_eram_rdat3",
-        STAT_STAT_CFG_CPU_IND_ERAM_RDAT3r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_eram_rdat3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_alu_eram_cpu_rdy",
-        STAT_STAT_CFG_TM_ALU_ERAM_CPU_RDYr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_tm_alu_eram_cpu_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_stat_cfg",
-        STAT_STAT_CFG_OAM_STAT_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_stat_stat_cfg_oam_stat_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ftm_port_sel_cfg",
-        STAT_STAT_CFG_FTM_PORT_SEL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_stat_stat_cfg_ftm_port_sel_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_eram_base_addr",
-        STAT_STAT_CFG_OAM_ERAM_BASE_ADDRr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_oam_eram_base_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_lm_eram_base_addr",
-        STAT_STAT_CFG_OAM_LM_ERAM_BASE_ADDRr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000005c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_oam_lm_eram_base_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_ddr_base_addr",
-        STAT_STAT_CFG_OAM_DDR_BASE_ADDRr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_oam_ddr_base_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "plcr0_schd_pful_cfg",
-        STAT_STAT_CFG_PLCR0_SCHD_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000078,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_plcr0_schd_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_lm_ord_pful_cfg",
-        STAT_STAT_CFG_OAM_LM_ORD_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_oam_lm_ord_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_schd_pful_cfg",
-        STAT_STAT_CFG_DDR_SCHD_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_ddr_schd_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "eram_schd_pful_cfg",
-        STAT_STAT_CFG_ERAM_SCHD_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_eram_schd_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "eram_schd_pept_cfg",
-        STAT_STAT_CFG_ERAM_SCHD_PEPT_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000008c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_eram_schd_pept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "eram_schd_oam_pful_cfg",
-        STAT_STAT_CFG_ERAM_SCHD_OAM_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_eram_schd_oam_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "eram_schd_oam_pept_cfg",
-        STAT_STAT_CFG_ERAM_SCHD_OAM_PEPT_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_eram_schd_oam_pept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "eram_schd_oam_lm_pful_cfg",
-        STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000098,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_eram_schd_oam_lm_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "eram_schd_oam_lm_pept_cfg",
-        STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PEPT_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000009c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_eram_schd_oam_lm_pept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_pful_cfg",
-        STAT_STAT_CFG_RSCHD_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_rschd_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_pept_cfg",
-        STAT_STAT_CFG_RSCHD_PEPT_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_rschd_pept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_plcr_pful_cfg",
-        STAT_STAT_CFG_RSCHD_PLCR_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_rschd_plcr_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_plcr_pept_cfg",
-        STAT_STAT_CFG_RSCHD_PLCR_PEPT_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_rschd_plcr_pept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_plcr_info_pful_cfg",
-        STAT_STAT_CFG_RSCHD_PLCR_INFO_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_rschd_plcr_info_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "alu_arb_cpu_pful_cfg",
-        STAT_STAT_CFG_ALU_ARB_CPU_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_alu_arb_cpu_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "alu_arb_user_pful_cfg",
-        STAT_STAT_CFG_ALU_ARB_USER_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_alu_arb_user_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "alu_arb_stat_pful_cfg",
-        STAT_STAT_CFG_ALU_ARB_STAT_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_alu_arb_stat_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cycmov_dat_pful_cfg",
-        STAT_STAT_CFG_CYCMOV_DAT_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_cycmov_dat_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ddr_opr_pful_cfg",
-        STAT_STAT_CFG_DDR_OPR_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_ddr_opr_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cycle_mov_pful_cfg",
-        STAT_STAT_CFG_CYCLE_MOV_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_cycle_mov_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cntovf_pful_cfg",
-        STAT_STAT_CFG_CNTOVF_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_cntovf_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "eram_schd_plcr_pful_cfg",
-        STAT_STAT_CFG_ERAM_SCHD_PLCR_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_eram_schd_plcr_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "eram_schd_plcr_pept_cfg",
-        STAT_STAT_CFG_ERAM_SCHD_PLCR_PEPT_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_eram_schd_plcr_pept_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "debug_cnt_mode",
-        STAT_STAT_CFG_DEBUG_CNT_MODEr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_debug_cnt_mode_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_mov_period_cfg",
-        STAT_STAT_CFG_TM_MOV_PERIOD_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_tm_mov_period_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "alu_ddr_cpu_req_pful_cfg",
-        STAT_STAT_CFG_ALU_DDR_CPU_REQ_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_alu_ddr_cpu_req_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cycmov_addr_pful_cfg",
-        STAT_STAT_CFG_CYCMOV_ADDR_PFUL_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_cycmov_addr_pful_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ord_ddr_plcr_fifo_empty",
-        STAT_STAT_CFG_ORD_DDR_PLCR_FIFO_EMPTYr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000100,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_stat_stat_cfg_ord_ddr_plcr_fifo_empty_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_stat_fifo_empty",
-        STAT_STAT_CFG_TM_STAT_FIFO_EMPTYr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000104,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_tm_stat_fifo_empty_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "eram_schd_fifo_empty_0_1",
-        STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_0_1r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000108,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_eram_schd_fifo_empty_0_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "eram_schd_fifo_empty_2_3",
-        STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_2_3r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000010c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_eram_schd_fifo_empty_2_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "eram_schd_fifo_empty_4_5",
-        STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_4_5r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000110,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_eram_schd_fifo_empty_4_5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "eram_schd_fifo_empty_6_7",
-        STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_6_7r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000114,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_stat_stat_cfg_eram_schd_fifo_empty_6_7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "eram_schd_fifo_empty_free_8",
-        STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_FREE_8r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000118,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        10,
-        g_stat_stat_cfg_eram_schd_fifo_empty_free_8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty_0_3",
-        STAT_STAT_CFG_RSCHD_FIFO_EMPTY_0_3r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000011c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_stat_stat_cfg_rschd_fifo_empty_0_3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty_4_7",
-        STAT_STAT_CFG_RSCHD_FIFO_EMPTY_4_7r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000120,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_stat_stat_cfg_rschd_fifo_empty_4_7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty_8_11",
-        STAT_STAT_CFG_RSCHD_FIFO_EMPTY_8_11r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000124,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_stat_stat_cfg_rschd_fifo_empty_8_11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty_12_15",
-        STAT_STAT_CFG_RSCHD_FIFO_EMPTY_12_15r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000128,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_stat_stat_cfg_rschd_fifo_empty_12_15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_fifo_empty_plcr_16_17",
-        STAT_STAT_CFG_RSCHD_FIFO_EMPTY_PLCR_16_17r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000012c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_stat_stat_cfg_rschd_fifo_empty_plcr_16_17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int_unmask_flag",
-        STAT_STAT_CFG_STAT_INT_UNMASK_FLAGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000140,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        6,
-        g_stat_stat_cfg_stat_int_unmask_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int0_en",
-        STAT_STAT_CFG_STAT_INT0_ENr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000144,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_stat_stat_cfg_stat_int0_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int0_mask",
-        STAT_STAT_CFG_STAT_INT0_MASKr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000148,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_stat_stat_cfg_stat_int0_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int0_status",
-        STAT_STAT_CFG_STAT_INT0_STATUSr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000014c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_stat_stat_cfg_stat_int0_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int1_en",
-        STAT_STAT_CFG_STAT_INT1_ENr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000150,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_stat_stat_cfg_stat_int1_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int1_mask",
-        STAT_STAT_CFG_STAT_INT1_MASKr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000154,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_stat_stat_cfg_stat_int1_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int1_status",
-        STAT_STAT_CFG_STAT_INT1_STATUSr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000158,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_stat_stat_cfg_stat_int1_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int2_en",
-        STAT_STAT_CFG_STAT_INT2_ENr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000015c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_stat_stat_cfg_stat_int2_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int2_mask",
-        STAT_STAT_CFG_STAT_INT2_MASKr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000160,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_stat_stat_cfg_stat_int2_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int2_status",
-        STAT_STAT_CFG_STAT_INT2_STATUSr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000164,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_stat_stat_cfg_stat_int2_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int3_en",
-        STAT_STAT_CFG_STAT_INT3_ENr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000168,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_stat_stat_cfg_stat_int3_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int3_mask",
-        STAT_STAT_CFG_STAT_INT3_MASKr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000016c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_stat_stat_cfg_stat_int3_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int3_status",
-        STAT_STAT_CFG_STAT_INT3_STATUSr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000170,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        32,
-        g_stat_stat_cfg_stat_int3_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int4_en",
-        STAT_STAT_CFG_STAT_INT4_ENr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000174,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        19,
-        g_stat_stat_cfg_stat_int4_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int4_mask",
-        STAT_STAT_CFG_STAT_INT4_MASKr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000178,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        19,
-        g_stat_stat_cfg_stat_int4_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int4_status",
-        STAT_STAT_CFG_STAT_INT4_STATUSr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000017c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        19,
-        g_stat_stat_cfg_stat_int4_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int5_en",
-        STAT_STAT_CFG_STAT_INT5_ENr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000180,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        19,
-        g_stat_stat_cfg_stat_int5_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int5_mask",
-        STAT_STAT_CFG_STAT_INT5_MASKr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000184,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        19,
-        g_stat_stat_cfg_stat_int5_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_int5_status",
-        STAT_STAT_CFG_STAT_INT5_STATUSr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000188,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        19,
-        g_stat_stat_cfg_stat_int5_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_ecc_bypass",
-        STAT_STAT_CFG_RSCHD_ECC_BYPASSr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000198,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        19,
-        g_stat_stat_cfg_rschd_ecc_bypass_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_ecc_single_err",
-        STAT_STAT_CFG_RSCHD_ECC_SINGLE_ERRr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000019c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        19,
-        g_stat_stat_cfg_rschd_ecc_single_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rschd_ecc_double_err",
-        STAT_STAT_CFG_RSCHD_ECC_DOUBLE_ERRr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000001a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        19,
-        g_stat_stat_cfg_rschd_ecc_double_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_wdat0",
-        STAT_STAT_CFG_CPU_IND_DDR_WDAT0r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000200,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_wdat0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_wdat1",
-        STAT_STAT_CFG_CPU_IND_DDR_WDAT1r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000204,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_wdat1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_wdat2",
-        STAT_STAT_CFG_CPU_IND_DDR_WDAT2r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000208,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_wdat2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_wdat3",
-        STAT_STAT_CFG_CPU_IND_DDR_WDAT3r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000020c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_wdat3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_wdat4",
-        STAT_STAT_CFG_CPU_IND_DDR_WDAT4r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000210,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_wdat4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_wdat5",
-        STAT_STAT_CFG_CPU_IND_DDR_WDAT5r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000214,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_wdat5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_wdat6",
-        STAT_STAT_CFG_CPU_IND_DDR_WDAT6r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000218,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_wdat6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_wdat7",
-        STAT_STAT_CFG_CPU_IND_DDR_WDAT7r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000021c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_wdat7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_wdat8",
-        STAT_STAT_CFG_CPU_IND_DDR_WDAT8r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000220,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_wdat8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_wdat9",
-        STAT_STAT_CFG_CPU_IND_DDR_WDAT9r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000224,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_wdat9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_wdat10",
-        STAT_STAT_CFG_CPU_IND_DDR_WDAT10r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000228,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_wdat10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_wdat11",
-        STAT_STAT_CFG_CPU_IND_DDR_WDAT11r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000022c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_wdat11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_wdat12",
-        STAT_STAT_CFG_CPU_IND_DDR_WDAT12r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000230,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_wdat12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_wdat13",
-        STAT_STAT_CFG_CPU_IND_DDR_WDAT13r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000234,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_wdat13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_wdat14",
-        STAT_STAT_CFG_CPU_IND_DDR_WDAT14r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000238,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_wdat14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_wdat15",
-        STAT_STAT_CFG_CPU_IND_DDR_WDAT15r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000023c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_wdat15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_req_info",
-        STAT_STAT_CFG_CPU_IND_DDR_REQ_INFOr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000240,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_stat_stat_cfg_cpu_ind_ddr_req_info_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rd_done",
-        STAT_STAT_CFG_CPU_IND_DDR_RD_DONEr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000244,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rd_done_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rdat0",
-        STAT_STAT_CFG_CPU_IND_DDR_RDAT0r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000248,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rdat0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rdat1",
-        STAT_STAT_CFG_CPU_IND_DDR_RDAT1r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000024c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rdat1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rdat2",
-        STAT_STAT_CFG_CPU_IND_DDR_RDAT2r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000250,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rdat2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rdat3",
-        STAT_STAT_CFG_CPU_IND_DDR_RDAT3r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000254,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rdat3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rdat4",
-        STAT_STAT_CFG_CPU_IND_DDR_RDAT4r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000258,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rdat4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rdat5",
-        STAT_STAT_CFG_CPU_IND_DDR_RDAT5r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000025c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rdat5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rdat6",
-        STAT_STAT_CFG_CPU_IND_DDR_RDAT6r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000260,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rdat6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rdat7",
-        STAT_STAT_CFG_CPU_IND_DDR_RDAT7r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000264,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rdat7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rdat8",
-        STAT_STAT_CFG_CPU_IND_DDR_RDAT8r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000268,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rdat8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rdat9",
-        STAT_STAT_CFG_CPU_IND_DDR_RDAT9r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000026c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rdat9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rdat10",
-        STAT_STAT_CFG_CPU_IND_DDR_RDAT10r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000270,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rdat10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rdat11",
-        STAT_STAT_CFG_CPU_IND_DDR_RDAT11r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000274,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rdat11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rdat12",
-        STAT_STAT_CFG_CPU_IND_DDR_RDAT12r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000278,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rdat12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rdat13",
-        STAT_STAT_CFG_CPU_IND_DDR_RDAT13r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000027c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rdat13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rdat14",
-        STAT_STAT_CFG_CPU_IND_DDR_RDAT14r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000280,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rdat14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_ddr_rdat15",
-        STAT_STAT_CFG_CPU_IND_DDR_RDAT15r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000284,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_ind_ddr_rdat15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_alu_ddr_cpu_rdy",
-        STAT_STAT_CFG_TM_ALU_DDR_CPU_RDYr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000288,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_tm_alu_ddr_cpu_rdy_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ept_flag",
-        STAT_STAT_CFG_EPT_FLAGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000003f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_ept_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_soft_rst",
-        STAT_STAT_CFG_PPU_SOFT_RSTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000003fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_ppu_soft_rst_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_smmu0_fc15_0_cnt",
-        STAT_STAT_CFG_STAT_SMMU0_FC15_0_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000400,
-        (32/8),
-        0,
-        15 + 1,
-        0,
-        4,
-        1,
-        g_stat_stat_cfg_stat_smmu0_fc15_0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_stat_fc15_0_cnt",
-        STAT_STAT_CFG_SMMU0_STAT_FC15_0_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000440,
-        (32/8),
-        0,
-        15 + 1,
-        0,
-        4,
-        1,
-        g_stat_stat_cfg_smmu0_stat_fc15_0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_stat_rsp15_0_cnt",
-        STAT_STAT_CFG_SMMU0_STAT_RSP15_0_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000480,
-        (32/8),
-        0,
-        15 + 1,
-        0,
-        4,
-        1,
-        g_stat_stat_cfg_smmu0_stat_rsp15_0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_smmu0_req15_0_cnt",
-        STAT_STAT_CFG_STAT_SMMU0_REQ15_0_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000004c0,
-        (32/8),
-        0,
-        15 + 1,
-        0,
-        4,
-        1,
-        g_stat_stat_cfg_stat_smmu0_req15_0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_stat_mec5_0_rsp_fc_cnt",
-        STAT_STAT_CFG_PPU_STAT_MEC5_0_RSP_FC_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000500,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_stat_stat_cfg_ppu_stat_mec5_0_rsp_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_ppu_mec5_0_key_fc_cnt",
-        STAT_STAT_CFG_STAT_PPU_MEC5_0_KEY_FC_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000518,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_stat_stat_cfg_stat_ppu_mec5_0_key_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_ppu_mec5_0_rsp_cnt",
-        STAT_STAT_CFG_STAT_PPU_MEC5_0_RSP_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000530,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_stat_stat_cfg_stat_ppu_mec5_0_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu_stat_mec5_0_key_cnt",
-        STAT_STAT_CFG_PPU_STAT_MEC5_0_KEY_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000548,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_stat_stat_cfg_ppu_stat_mec5_0_key_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ppu5_0_no_exist_opcd_ex_cnt",
-        STAT_STAT_CFG_PPU5_0_NO_EXIST_OPCD_EX_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000560,
-        (32/8),
-        0,
-        5 + 1,
-        0,
-        4,
-        1,
-        g_stat_stat_cfg_ppu5_0_no_exist_opcd_ex_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_etm_stat_wr_fc_cnt",
-        STAT_STAT_CFG_SE_ETM_STAT_WR_FC_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000578,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_se_etm_stat_wr_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_etm_stat_rd_fc_cnt",
-        STAT_STAT_CFG_SE_ETM_STAT_RD_FC_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000057c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_se_etm_stat_rd_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_etm_deq_fc_cnt",
-        STAT_STAT_CFG_STAT_ETM_DEQ_FC_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000580,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_stat_etm_deq_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_etm_enq_fc_cnt",
-        STAT_STAT_CFG_STAT_ETM_ENQ_FC_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000584,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_stat_etm_enq_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_oam_lm_fc_cnt",
-        STAT_STAT_CFG_STAT_OAM_LM_FC_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000588,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_stat_oam_lm_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_stat_lm_fc_cnt",
-        STAT_STAT_CFG_OAM_STAT_LM_FC_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000058c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_oam_stat_lm_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_oam_fc_cnt",
-        STAT_STAT_CFG_STAT_OAM_FC_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000590,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_stat_oam_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cmmu_stat_fc_cnt",
-        STAT_STAT_CFG_CMMU_STAT_FC_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000594,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cmmu_stat_fc_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_cmmu_req_cnt",
-        STAT_STAT_CFG_STAT_CMMU_REQ_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000598,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_stat_cmmu_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "smmu0_plcr_rsp0_cnt",
-        STAT_STAT_CFG_SMMU0_PLCR_RSP0_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000059c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_smmu0_plcr_rsp0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "plcr_smmu0_req0_cnt",
-        STAT_STAT_CFG_PLCR_SMMU0_REQ0_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_plcr_smmu0_req0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "stat_oam_lm_rsp_cnt",
-        STAT_STAT_CFG_STAT_OAM_LM_RSP_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_stat_oam_lm_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_stat_lm_req_cnt",
-        STAT_STAT_CFG_OAM_STAT_LM_REQ_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_oam_stat_lm_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "oam_stat_req_cnt",
-        STAT_STAT_CFG_OAM_STAT_REQ_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_oam_stat_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "se_etm_stat_rsp_cnt",
-        STAT_STAT_CFG_SE_ETM_STAT_RSP_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_se_etm_stat_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_stat_se_wr_req_cnt",
-        STAT_STAT_CFG_ETM_STAT_SE_WR_REQ_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_etm_stat_se_wr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_stat_se_rd_req_cnt",
-        STAT_STAT_CFG_ETM_STAT_SE_RD_REQ_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_etm_stat_se_rd_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_stat_smmu0_req_cnt0",
-        STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT0r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_etm_stat_smmu0_req_cnt0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etm_stat_smmu0_req_cnt1",
-        STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT1r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_etm_stat_smmu0_req_cnt1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_stat_eram_cpu_rsp_cnt",
-        STAT_STAT_CFG_TM_STAT_ERAM_CPU_RSP_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_tm_stat_eram_cpu_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_eram_req_cnt",
-        STAT_STAT_CFG_CPU_RD_ERAM_REQ_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_rd_eram_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_wr_eram_req_cnt",
-        STAT_STAT_CFG_CPU_WR_ERAM_REQ_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_wr_eram_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tm_stat_ddr_cpu_rsp_cnt",
-        STAT_STAT_CFG_TM_STAT_DDR_CPU_RSP_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_tm_stat_ddr_cpu_rsp_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_rd_ddr_req_cnt",
-        STAT_STAT_CFG_CPU_RD_DDR_REQ_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_rd_ddr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_wr_ddr_req_cnt",
-        STAT_STAT_CFG_CPU_WR_DDR_REQ_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_stat_cfg_cpu_wr_ddr_req_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat1",
-        STAT_ETCAM_CPU_IND_WDAT1r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat2",
-        STAT_ETCAM_CPU_IND_WDAT2r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat3",
-        STAT_ETCAM_CPU_IND_WDAT3r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat4",
-        STAT_ETCAM_CPU_IND_WDAT4r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat4_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat5",
-        STAT_ETCAM_CPU_IND_WDAT5r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat5_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat6",
-        STAT_ETCAM_CPU_IND_WDAT6r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat6_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat7",
-        STAT_ETCAM_CPU_IND_WDAT7r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat7_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat8",
-        STAT_ETCAM_CPU_IND_WDAT8r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat8_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat9",
-        STAT_ETCAM_CPU_IND_WDAT9r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat9_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat10",
-        STAT_ETCAM_CPU_IND_WDAT10r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000002c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat10_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat11",
-        STAT_ETCAM_CPU_IND_WDAT11r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat11_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat12",
-        STAT_ETCAM_CPU_IND_WDAT12r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat12_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat13",
-        STAT_ETCAM_CPU_IND_WDAT13r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat13_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat14",
-        STAT_ETCAM_CPU_IND_WDAT14r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000003c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat14_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat15",
-        STAT_ETCAM_CPU_IND_WDAT15r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat16",
-        STAT_ETCAM_CPU_IND_WDAT16r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat16_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat17",
-        STAT_ETCAM_CPU_IND_WDAT17r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat17_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat18",
-        STAT_ETCAM_CPU_IND_WDAT18r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat18_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_ind_wdat19",
-        STAT_ETCAM_CPU_IND_WDAT19r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_cpu_ind_wdat19_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "t_strwc_cfg",
-        STAT_ETCAM_T_STRWC_CFGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000074,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_t_strwc_cfg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_int_unmask_flag",
-        STAT_ETCAM_ETCAM_INT_UNMASK_FLAGr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_etcam_int_unmask_flag_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_int_en0",
-        STAT_ETCAM_ETCAM_INT_EN0r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        18,
-        g_stat_etcam_etcam_int_en0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_int_mask0",
-        STAT_ETCAM_ETCAM_INT_MASK0r,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000008c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        18,
-        g_stat_etcam_etcam_int_mask0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_int_status",
-        STAT_ETCAM_ETCAM_INT_STATUSr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        18,
-        g_stat_etcam_etcam_int_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "int_tb_ini_ok",
-        STAT_ETCAM_INT_TB_INI_OKr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x000003f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_int_tb_ini_ok_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_clk_en",
-        STAT_ETCAM_ETCAM_CLK_ENr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x000003fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_etcam_clk_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_etcam_req0_cnt",
-        STAT_ETCAM_AS_ETCAM_REQ0_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000400,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_as_etcam_req0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "as_etcam_req1_cnt",
-        STAT_ETCAM_AS_ETCAM_REQ1_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000404,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_as_etcam_req1_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_as_index0_cnt",
-        STAT_ETCAM_ETCAM_AS_INDEX0_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000408,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_etcam_as_index0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_as_index1_cnt",
-        STAT_ETCAM_ETCAM_AS_INDEX1_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000040c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_etcam_as_index1_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_not_hit0_cnt",
-        STAT_ETCAM_ETCAM_NOT_HIT0_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000410,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_etcam_not_hit0_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_not_hit1_cnt",
-        STAT_ETCAM_ETCAM_NOT_HIT1_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000414,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_etcam_not_hit1_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "table_id_not_match_cnt",
-        STAT_ETCAM_TABLE_ID_NOT_MATCH_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000418,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_table_id_not_match_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "table_id_clash01_cnt",
-        STAT_ETCAM_TABLE_ID_CLASH01_CNTr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000041c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_table_id_clash01_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_cpu_fl",
-        STAT_ETCAM_ETCAM_CPU_FLr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000044c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_etcam_cpu_fl_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "etcam_arb_empty",
-        STAT_ETCAM_ETCAM_ARB_EMPTYr,
-        STAT,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000450,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_stat_etcam_etcam_arb_empty_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_finish_int_event0",
-        DTB_DTB_CFG_CFG_FINISH_INT_EVENT0r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_finish_int_event0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_finish_int_event1",
-        DTB_DTB_CFG_CFG_FINISH_INT_EVENT1r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_finish_int_event1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_finish_int_event2",
-        DTB_DTB_CFG_CFG_FINISH_INT_EVENT2r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_finish_int_event2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_finish_int_event3",
-        DTB_DTB_CFG_CFG_FINISH_INT_EVENT3r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_finish_int_event3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_finish_int_maks0",
-        DTB_DTB_CFG_CFG_FINISH_INT_MAKS0r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_finish_int_maks0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_finish_int_maks1",
-        DTB_DTB_CFG_CFG_FINISH_INT_MAKS1r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_finish_int_maks1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_finish_int_maks2",
-        DTB_DTB_CFG_CFG_FINISH_INT_MAKS2r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_finish_int_maks2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_finish_int_maks3",
-        DTB_DTB_CFG_CFG_FINISH_INT_MAKS3r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_finish_int_maks3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_finish_int_test0",
-        DTB_DTB_CFG_CFG_FINISH_INT_TEST0r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_finish_int_test0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_finish_int_test1",
-        DTB_DTB_CFG_CFG_FINISH_INT_TEST1r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_finish_int_test1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_finish_int_test2",
-        DTB_DTB_CFG_CFG_FINISH_INT_TEST2r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_finish_int_test2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_finish_int_test3",
-        DTB_DTB_CFG_CFG_FINISH_INT_TEST3r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x002c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_finish_int_test3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_dtb_int_to_riscv_sel",
-        DTB_DTB_CFG_CFG_DTB_INT_TO_RISCV_SELr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_dtb_int_to_riscv_sel_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_dtb_ep_int_msix_enable",
-        DTB_DTB_CFG_CFG_DTB_EP_INT_MSIX_ENABLEr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_dtb_ep_int_msix_enable_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_dtb_ep_doorbell_addr_h_0_15",
-        DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_H_0_15r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0100,
-        (32/8),
-        0,
-        15 + 1,
-        0,
-        4,
-        1,
-        g_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_h_0_15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_dtb_ep_doorbell_addr_l_0_15",
-        DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_L_0_15r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0140,
-        (32/8),
-        0,
-        15 + 1,
-        0,
-        4,
-        1,
-        g_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_l_0_15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_dtb_debug_mode_en",
-        DTB_DTB_CFG_CFG_DTB_DEBUG_MODE_ENr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0180,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_dtb_debug_mode_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_rd_table_addr_high",
-        DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_HIGHr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0184,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_rd_table_addr_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_rd_table_addr_low",
-        DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_LOWr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0188,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_rd_table_addr_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_rd_table_len",
-        DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_LENr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x018c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_rd_table_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_rd_table_user",
-        DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USERr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0190,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_dtb_dtb_cfg_info_axi_last_rd_table_user_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_rd_table_onload_cnt",
-        DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ONLOAD_CNTr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0194,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_rd_table_onload_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_axi_rd_table_resp_err",
-        DTB_DTB_CFG_CNT_AXI_RD_TABLE_RESP_ERRr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0198,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_axi_rd_table_resp_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_rd_pd_addr_high",
-        DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_HIGHr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_rd_pd_addr_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_rd_pd_addr_low",
-        DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_LOWr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_rd_pd_addr_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_rd_pd_len",
-        DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_LENr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_rd_pd_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_rd_pd_user",
-        DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USERr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_dtb_dtb_cfg_info_axi_last_rd_pd_user_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_rd_pd_onload_cnt",
-        DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ONLOAD_CNTr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_rd_pd_onload_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_axi_rd_pd_resp_err",
-        DTB_DTB_CFG_CNT_AXI_RD_PD_RESP_ERRr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_axi_rd_pd_resp_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_wr_ctrl_addr_high",
-        DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_HIGHr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_wr_ctrl_addr_low",
-        DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_LOWr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_wr_ctrl_len",
-        DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_LENr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_wr_ctrl_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_wr_ctrl_user",
-        DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USERr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_dtb_dtb_cfg_info_axi_last_wr_ctrl_user_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_wr_ctrl_onload_cnt",
-        DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ONLOAD_CNTr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_wr_ctrl_onload_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_axi_wr_ctrl_resp_err",
-        DTB_DTB_CFG_CNT_AXI_WR_CTRL_RESP_ERRr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_axi_wr_ctrl_resp_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_wr_ddr_addr_high",
-        DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_HIGHr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_wr_ddr_addr_low",
-        DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_LOWr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_wr_ddr_len",
-        DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_LENr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_wr_ddr_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_wr_ddr_user",
-        DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USERr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_dtb_dtb_cfg_info_axi_last_wr_ddr_user_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_wr_ddr_onload_cnt",
-        DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ONLOAD_CNTr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_wr_ddr_onload_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_axi_wr_ddr_resp_err",
-        DTB_DTB_CFG_CNT_AXI_WR_DDR_RESP_ERRr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_axi_wr_ddr_resp_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_wr_fin_addr_high",
-        DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_HIGHr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_wr_fin_addr_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_wr_fin_addr_low",
-        DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_LOWr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_wr_fin_addr_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_wr_fin_len",
-        DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_LENr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_wr_fin_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_wr_fin_user",
-        DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USERr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_dtb_dtb_cfg_info_axi_last_wr_fin_user_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axi_last_wr_fin_onload_cnt",
-        DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ONLOAD_CNTr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_axi_last_wr_fin_onload_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_axi_wr_fin_resp_err",
-        DTB_DTB_CFG_CNT_AXI_WR_FIN_RESP_ERRr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_axi_wr_fin_resp_err_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_wr_smmu0_table_high",
-        DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_HIGHr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0200,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_wr_smmu0_table_low",
-        DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_LOWr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0204,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_wr_smmu1_table_high",
-        DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_HIGHr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0208,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_wr_smmu1_table_low",
-        DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_LOWr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x020c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_wr_zcam_table_high",
-        DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_HIGHr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0210,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_wr_zcam_table_low",
-        DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_LOWr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0214,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_wr_etcam_table_high",
-        DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_HIGHr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0218,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_wr_etcam_table_low",
-        DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_LOWr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x021c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_wr_hash_table_high",
-        DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_HIGHr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0220,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_wr_hash_table_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_wr_hash_table_low",
-        DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_LOWr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0224,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_wr_hash_table_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_rd_smmu0_table_high",
-        DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_HIGHr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0228,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_rd_smmu0_table_low",
-        DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_LOWr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x022c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_rd_smmu1_table_high",
-        DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_HIGHr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0230,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_rd_smmu1_table_low",
-        DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_LOWr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0234,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_rd_zcam_table_high",
-        DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_HIGHr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0238,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_rd_zcam_table_low",
-        DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_LOWr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x023c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_rd_etcam_table_high",
-        DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_HIGHr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0240,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cnt_dtb_rd_etcam_table_low",
-        DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_LOWr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0244,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_wr_ctrl_state",
-        DTB_DTB_CFG_INFO_WR_CTRL_STATEr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0248,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_wr_ctrl_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_rd_table_state",
-        DTB_DTB_CFG_INFO_RD_TABLE_STATEr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x024c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_rd_table_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_rd_pd_state",
-        DTB_DTB_CFG_INFO_RD_PD_STATEr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0250,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_rd_pd_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_dump_cmd_state",
-        DTB_DTB_CFG_INFO_DUMP_CMD_STATEr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0254,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_dump_cmd_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_wr_ddr_state",
-        DTB_DTB_CFG_INFO_WR_DDR_STATEr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0258,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_info_wr_ddr_state_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_dtb_debug_info_clr",
-        DTB_DTB_CFG_CFG_DTB_DEBUG_INFO_CLRr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x025c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_dtb_cfg_cfg_dtb_debug_info_clr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddos_stat_dump_thrd_0_15",
-        DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_0_15r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        15 + 1,
-        0,
-        4,
-        1,
-        g_dtb_ddos_cfg_ddos_stat_dump_thrd_0_15_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddos_stat_dump_thrd_comp_en",
-        DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_COMP_ENr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_ddos_cfg_ddos_stat_dump_thrd_comp_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddos_dump_stat_num",
-        DTB_DDOS_CFG_DDOS_DUMP_STAT_NUMr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_ddos_cfg_ddos_dump_stat_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddos_even_hash_table_baddr",
-        DTB_DDOS_CFG_DDOS_EVEN_HASH_TABLE_BADDRr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_ddos_cfg_ddos_even_hash_table_baddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddos_odd_hash_table_baddr",
-        DTB_DDOS_CFG_DDOS_ODD_HASH_TABLE_BADDRr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_ddos_cfg_ddos_odd_hash_table_baddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddos_stat_index_offset",
-        DTB_DDOS_CFG_DDOS_STAT_INDEX_OFFSETr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_ddos_cfg_ddos_stat_index_offset_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddos_ns_flag_cnt",
-        DTB_DDOS_CFG_DDOS_NS_FLAG_CNTr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_ddos_cfg_ddos_ns_flag_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddos_even_stat_table_baddr",
-        DTB_DDOS_CFG_DDOS_EVEN_STAT_TABLE_BADDRr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_ddos_cfg_ddos_even_stat_table_baddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddos_odd_stat_table_baddr",
-        DTB_DDOS_CFG_DDOS_ODD_STAT_TABLE_BADDRr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x005c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_ddos_cfg_ddos_odd_stat_table_baddr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddos_even_stat_dump_daddr_h",
-        DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_Hr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_ddos_cfg_ddos_even_stat_dump_daddr_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddos_even_stat_dump_daddr_l",
-        DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_Lr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_ddos_cfg_ddos_even_stat_dump_daddr_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddos_odd_stat_dump_daddr_h",
-        DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_Hr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddos_odd_stat_dump_daddr_l",
-        DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_Lr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x006c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddos_work_mode_enable",
-        DTB_DDOS_CFG_DDOS_WORK_MODE_ENABLEr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0070,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_ddos_cfg_ddos_work_mode_enable_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddos_stat_table_len",
-        DTB_DDOS_CFG_DDOS_STAT_TABLE_LENr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0074,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_ddos_cfg_ddos_stat_table_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_ddos_hash_table_len",
-        DTB_DDOS_CFG_DDOS_HASH_TABLE_LENr,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0078,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_dtb_ddos_cfg_ddos_hash_table_len_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "traf_ctrl_ram0_0_255",
-        DTB_DTB_RAM_TRAF_CTRL_RAM0_0_255r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x00000,
-        (32/8),
-        0,
-        255 + 1,
-        0,
-        4,
-        1,
-        g_dtb_dtb_ram_traf_ctrl_ram0_0_255_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "traf_ctrl_ram1_0_255",
-        DTB_DTB_RAM_TRAF_CTRL_RAM1_0_255r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x00400,
-        (32/8),
-        0,
-        255 + 1,
-        0,
-        4,
-        1,
-        g_dtb_dtb_ram_traf_ctrl_ram1_0_255_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "traf_ctrl_ram2_0_255",
-        DTB_DTB_RAM_TRAF_CTRL_RAM2_0_255r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x00800,
-        (32/8),
-        0,
-        255 + 1,
-        0,
-        4,
-        1,
-        g_dtb_dtb_ram_traf_ctrl_ram2_0_255_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "traf_ctrl_ram3_0_255",
-        DTB_DTB_RAM_TRAF_CTRL_RAM3_0_255r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x00c00,
-        (32/8),
-        0,
-        255 + 1,
-        0,
-        4,
-        1,
-        g_dtb_dtb_ram_traf_ctrl_ram3_0_255_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "traf_ctrl_ram4_0_255",
-        DTB_DTB_RAM_TRAF_CTRL_RAM4_0_255r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x01000,
-        (32/8),
-        0,
-        255 + 1,
-        0,
-        4,
-        1,
-        g_dtb_dtb_ram_traf_ctrl_ram4_0_255_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "traf_ctrl_ram5_0_63",
-        DTB_DTB_RAM_TRAF_CTRL_RAM5_0_63r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x01400,
-        (32/8),
-        0,
-        63 + 1,
-        0,
-        4,
-        1,
-        g_dtb_dtb_ram_traf_ctrl_ram5_0_63_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dump_pd_ram_0_2047",
-        DTB_DTB_RAM_DUMP_PD_RAM_0_2047r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x02000,
-        (32/8),
-        0,
-        2047 + 1,
-        0,
-        4,
-        1,
-        g_dtb_dtb_ram_dump_pd_ram_0_2047_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rd_ctrl_ram_0_4095",
-        DTB_DTB_RAM_RD_CTRL_RAM_0_4095r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x04000,
-        (32/8),
-        0,
-        4095 + 1,
-        0,
-        4,
-        1,
-        g_dtb_dtb_ram_rd_ctrl_ram_0_4095_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "rd_table_ram_0_8191",
-        DTB_DTB_RAM_RD_TABLE_RAM_0_8191r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x08000,
-        (32/8),
-        0,
-        8191 + 1,
-        0,
-        4,
-        1,
-        g_dtb_dtb_ram_rd_table_ram_0_8191_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "dtb_cmd_man_ram_0_16383",
-        DTB_DTB_RAM_DTB_CMD_MAN_RAM_0_16383r,
-        DTB,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x10000,
-        (32/8),
-        0,
-        16383 + 1,
-        0,
-        4,
-        1,
-        g_dtb_dtb_ram_dtb_cmd_man_ram_0_16383_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpg_ms_st",
-        TRPG_TRPG_RX_PORT_CPU_TRPG_MS_STr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0000,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpg_ms_st_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpg_ms_ind",
-        TRPG_TRPG_RX_PORT_CPU_TRPG_MS_INDr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0008,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpg_ms_ind_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpg_ms_slave_ind",
-        TRPG_TRPG_RX_PORT_CPU_TRPG_MS_SLAVE_INDr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x000c,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpg_ms_slave_ind_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_up_water_level",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_UP_WATER_LEVELr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0020,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_up_water_level_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpgrx_low_water_level",
-        TRPG_TRPG_RX_PORT_CPU_TRPGRX_LOW_WATER_LEVELr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0024,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_rx_port_cpu_trpgrx_low_water_level_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpg_ms_st",
-        TRPG_TRPG_TX_PORT_CPU_TRPG_MS_STr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0000,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpg_ms_st_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpg_ms_ind",
-        TRPG_TRPG_TX_PORT_CPU_TRPG_MS_INDr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0008,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpg_ms_ind_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_trpg_ms_slave_ind",
-        TRPG_TRPG_TX_PORT_CPU_TRPG_MS_SLAVE_INDr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x000c,
-        (32/8),
-        DPP_TRPG_PORT_NUM,
-        0,
-        DPP_TRPG_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_trpg_trpg_tx_port_cpu_trpg_ms_slave_ind_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_todtime_update_int_event",
-        TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_EVENTr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_trpg_trpg_tx_glb_cpu_todtime_update_int_event_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_todtime_update_int_test",
-        TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_TESTr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_trpg_trpg_tx_glb_cpu_todtime_update_int_test_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cpu_todtime_update_int_addr",
-        TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_ADDRr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x0014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_trpg_trpg_tx_glb_cpu_todtime_update_int_addr_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trpg_tx_todtime_ram",
-        TRPG_TRPG_TX_TODTIME_RAM_TRPG_TX_TODTIME_RAMr,
-        TRPG,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_UNI_ARRAY,
-        SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_TODTIME_RAM_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        4095 + 1,
-        0,
-        4,
-        1,
-        g_trpg_trpg_tx_todtime_ram_trpg_tx_todtime_ram_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_test_reg",
-        TSN_TSN_PORT_CFG_TSN_TEST_REGr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x000,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_tsn_tsn_port_cfg_tsn_test_reg_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_port_qbv_enable",
-        TSN_TSN_PORT_CFG_TSN_PORT_QBV_ENABLEr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0004,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_tsn_tsn_port_cfg_tsn_port_qbv_enable_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_phy_port_sel",
-        TSN_TSN_PORT_CFG_TSN_PHY_PORT_SELr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0008,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_tsn_tsn_port_cfg_tsn_phy_port_sel_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_port_time_sel",
-        TSN_TSN_PORT_CFG_TSN_PORT_TIME_SELr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x000c,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_tsn_tsn_port_cfg_tsn_port_time_sel_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_clk_freq",
-        TSN_TSN_PORT_CFG_TSN_CLK_FREQr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0014,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        2,
-        g_tsn_tsn_port_cfg_tsn_clk_freq_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_read_ram_n",
-        TSN_TSN_PORT_CFG_TSN_READ_RAM_Nr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0018,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        3,
-        g_tsn_tsn_port_cfg_tsn_read_ram_n_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_exe_time",
-        TSN_TSN_PORT_CFG_TSN_EXE_TIMEr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x001c,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_tsn_tsn_port_cfg_tsn_exe_time_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_port_itr_shift",
-        TSN_TSN_PORT_CFG_TSN_PORT_ITR_SHIFTr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0020,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_tsn_tsn_port_cfg_tsn_port_itr_shift_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_port_base_time_h",
-        TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_Hr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0024,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_tsn_tsn_port_cfg_tsn_port_base_time_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_port_base_time_l",
-        TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_Lr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0028,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_tsn_tsn_port_cfg_tsn_port_base_time_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_port_cycle_time_h",
-        TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_Hr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0030,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_tsn_tsn_port_cfg_tsn_port_cycle_time_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_port_cycle_time_l",
-        TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_Lr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0034,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_tsn_tsn_port_cfg_tsn_port_cycle_time_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_port_guard_band_time",
-        TSN_TSN_PORT_CFG_TSN_PORT_GUARD_BAND_TIMEr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0040,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        7 + 1,
-        DPP_TSN_PORT_SPACE_SIZE,
-        4,
-        1,
-        g_tsn_tsn_port_cfg_tsn_port_guard_band_time_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_port_default_gate_en",
-        TSN_TSN_PORT_CFG_TSN_PORT_DEFAULT_GATE_ENr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0060,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_tsn_tsn_port_cfg_tsn_port_default_gate_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_port_change_gate_en",
-        TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_GATE_ENr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0064,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_tsn_tsn_port_cfg_tsn_port_change_gate_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_port_init_finish",
-        TSN_TSN_PORT_CFG_TSN_PORT_INIT_FINISHr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0068,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_tsn_tsn_port_cfg_tsn_port_init_finish_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_port_change_en",
-        TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_ENr,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x006c,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_tsn_tsn_port_cfg_tsn_port_change_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_port_gcl_num0",
-        TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM0r,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0070,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_tsn_tsn_port_cfg_tsn_port_gcl_num0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_port_gcl_num1",
-        TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM1r,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0074,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        0,
-        DPP_TSN_PORT_SPACE_SIZE,
-        0,
-        1,
-        g_tsn_tsn_port_cfg_tsn_port_gcl_num1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_port_gcl_value0",
-        TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE0r,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x1000,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        255 + 1,
-        DPP_TSN_PORT_SPACE_SIZE,
-        4,
-        2,
-        g_tsn_tsn_port_cfg_tsn_port_gcl_value0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_tsn_port_gcl_value1",
-        TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE1r,
-        TSN,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_BIN_ARRAY,
-        SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x2000,
-        (32/8),
-        DPP_TSN_PORT_NUM,
-        255 + 1,
-        DPP_TSN_PORT_SPACE_SIZE,
-        4,
-        2,
-        g_tsn_tsn_port_cfg_tsn_port_gcl_value1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_epid_v_func_num",
-        AXI_AXI_CONV_CFG_EPID_V_FUNC_NUMr,
-        AXI,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_AXI_CONV_BASE_ADDR + 0x0010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_axi_axi_conv_cfg_epid_v_func_num_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axim_rw_hsk_cnt",
-        AXI_AXI_CONV_INFO_AXIM_RW_HSK_CNTr,
-        AXI,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_AXI_CONV_BASE_ADDR + 0x0020,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_axi_axi_conv_info_axim_rw_hsk_cnt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axim_last_wr_id",
-        AXI_AXI_CONV_INFO_AXIM_LAST_WR_IDr,
-        AXI,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_AXI_CONV_BASE_ADDR + 0x0024,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_axi_axi_conv_info_axim_last_wr_id_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axim_last_wr_addr_h",
-        AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_Hr,
-        AXI,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_AXI_CONV_BASE_ADDR + 0x0030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_axi_axi_conv_info_axim_last_wr_addr_h_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "info_axim_last_wr_addr_l",
-        AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_Lr,
-        AXI,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_AXI_CONV_BASE_ADDR + 0x0034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_axi_axi_conv_info_axim_last_wr_addr_l_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cfg_debug_info_clr_en",
-        AXI_AXI_CONV_CFG_DEBUG_INFO_CLR_ENr,
-        AXI,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_AXI_CONV_BASE_ADDR + 0x0038,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_axi_axi_conv_cfg_debug_info_clr_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_interrupt",
-        PTPTM_PTP_TOP_PP1S_INTERRUPTr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_ptptm_ptp_top_pp1s_interrupt_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_external_select",
-        PTPTM_PTP_TOP_PP1S_EXTERNAL_SELECTr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0004,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_pp1s_external_select_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_out_select",
-        PTPTM_PTP_TOP_PP1S_OUT_SELECTr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_pp1s_out_select_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "test_pp1s_select",
-        PTPTM_PTP_TOP_TEST_PP1S_SELECTr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_test_pp1s_select_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "local_pp1s_en",
-        PTPTM_PTP_TOP_LOCAL_PP1S_ENr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_local_pp1s_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "local_pp1s_adjust",
-        PTPTM_PTP_TOP_LOCAL_PP1S_ADJUSTr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_ptptm_ptp_top_local_pp1s_adjust_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "local_pp1s_adjust_value",
-        PTPTM_PTP_TOP_LOCAL_PP1S_ADJUST_VALUEr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_local_pp1s_adjust_value_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_to_np_select",
-        PTPTM_PTP_TOP_PP1S_TO_NP_SELECTr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_pp1s_to_np_select_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pd_u1_sel",
-        PTPTM_PTP_TOP_PD_U1_SELr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_ptptm_ptp_top_pd_u1_sel_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pd_u1_pd0_shift",
-        PTPTM_PTP_TOP_PD_U1_PD0_SHIFTr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_pd_u1_pd0_shift_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pd_u1_pd1_shift",
-        PTPTM_PTP_TOP_PD_U1_PD1_SHIFTr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_pd_u1_pd1_shift_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pd_u1_result",
-        PTPTM_PTP_TOP_PD_U1_RESULTr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_ptptm_ptp_top_pd_u1_result_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pd_u2_sel",
-        PTPTM_PTP_TOP_PD_U2_SELr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_ptptm_ptp_top_pd_u2_sel_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pd_u2_pd0_shift",
-        PTPTM_PTP_TOP_PD_U2_PD0_SHIFTr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_pd_u2_pd0_shift_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pd_u2_pd1_shift",
-        PTPTM_PTP_TOP_PD_U2_PD1_SHIFTr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_pd_u2_pd1_shift_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pd_u2_result",
-        PTPTM_PTP_TOP_PD_U2_RESULTr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x005c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_ptptm_ptp_top_pd_u2_result_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn_group_nanosecond_delay0",
-        PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY0r,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_tsn_group_nanosecond_delay0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn_group_fracnanosecond_delay0",
-        PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY0r,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_tsn_group_fracnanosecond_delay0_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn_group_nanosecond_delay1",
-        PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY1r,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_tsn_group_nanosecond_delay1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn_group_fracnanosecond_delay1",
-        PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY1r,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x008c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_tsn_group_fracnanosecond_delay1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn_group_nanosecond_delay2",
-        PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY2r,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_tsn_group_nanosecond_delay2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn_group_fracnanosecond_delay2",
-        PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY2r,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_tsn_group_fracnanosecond_delay2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn_group_nanosecond_delay3",
-        PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY3r,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x0098,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_tsn_group_nanosecond_delay3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn_group_fracnanosecond_delay3",
-        PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY3r,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x009c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_tsn_group_fracnanosecond_delay3_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn_ptp1588_rdma_nanosecond_delay",
-        PTPTM_PTP_TOP_TSN_PTP1588_RDMA_NANOSECOND_DELAYr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x00a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_tsn_ptp1588_rdma_nanosecond_delay_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ptp1588_rdma_fracnanosecond_delay",
-        PTPTM_PTP_TOP_PTP1588_RDMA_FRACNANOSECOND_DELAYr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x00a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_ptp1588_rdma_fracnanosecond_delay_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ptp1588_np_nanosecond_delay",
-        PTPTM_PTP_TOP_PTP1588_NP_NANOSECOND_DELAYr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x00a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_ptp1588_np_nanosecond_delay_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ptp1588_np_fracnanosecond_delay",
-        PTPTM_PTP_TOP_PTP1588_NP_FRACNANOSECOND_DELAYr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x00ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_ptp1588_np_fracnanosecond_delay_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "time_sync_period",
-        PTPTM_PTP_TOP_TIME_SYNC_PERIODr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP0_BASE_ADDR + 0x00b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptp_top_time_sync_period_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "module_id",
-        PTPTM_PTPTM_MODULE_IDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0000,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_module_id_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "module_version",
-        PTPTM_PTPTM_MODULE_VERSIONr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0008,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_ptptm_ptptm_module_version_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "module_date",
-        PTPTM_PTPTM_MODULE_DATEr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x000c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_ptptm_ptptm_module_date_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "interrupt_status",
-        PTPTM_PTPTM_INTERRUPT_STATUSr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0010,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_ptptm_ptptm_interrupt_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "interrupt_event",
-        PTPTM_PTPTM_INTERRUPT_EVENTr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0014,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_ptptm_ptptm_interrupt_event_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "interrupt_mask",
-        PTPTM_PTPTM_INTERRUPT_MASKr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0018,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_ptptm_ptptm_interrupt_mask_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "interrupt_test",
-        PTPTM_PTPTM_INTERRUPT_TESTr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x001c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_ptptm_ptptm_interrupt_test_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hw_clock_cycle_integer",
-        PTPTM_PTPTM_HW_CLOCK_CYCLE_INTEGERr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0028,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_hw_clock_cycle_integer_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "hw_clock_cycle_fraction",
-        PTPTM_PTPTM_HW_CLOCK_CYCLE_FRACTIONr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x002c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_hw_clock_cycle_fraction_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ptp_clock_cycle_integer",
-        PTPTM_PTPTM_PTP_CLOCK_CYCLE_INTEGERr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0030,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_ptp_clock_cycle_integer_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ptp_clock_cycle_fraction",
-        PTPTM_PTPTM_PTP_CLOCK_CYCLE_FRACTIONr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0034,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_ptp_clock_cycle_fraction_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ptp_configuration",
-        PTPTM_PTPTM_PTP_CONFIGURATIONr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0040,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        18,
-        g_ptptm_ptptm_ptp_configuration_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "timer_control",
-        PTPTM_PTPTM_TIMER_CONTROLr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0044,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_ptptm_ptptm_timer_control_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pps_income_delay",
-        PTPTM_PTPTM_PPS_INCOME_DELAYr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0048,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        2,
-        g_ptptm_ptptm_pps_income_delay_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "clock_cycle_update",
-        PTPTM_PTPTM_CLOCK_CYCLE_UPDATEr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x004c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        5,
-        g_ptptm_ptptm_clock_cycle_update_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cycle_time_of_output_period_pulse_1",
-        PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_1r,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0050,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_cycle_time_of_output_period_pulse_1_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "cycle_time_of_output_period_pulse_2",
-        PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_2r,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0054,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_cycle_time_of_output_period_pulse_2_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "timer_latch_en",
-        PTPTM_PTPTM_TIMER_LATCH_ENr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0058,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_timer_latch_en_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "timer_latch_sel",
-        PTPTM_PTPTM_TIMER_LATCH_SELr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x005c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_timer_latch_sel_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trigger_in_tod_nanosecond",
-        PTPTM_PTPTM_TRIGGER_IN_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0060,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_trigger_in_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trigger_in_lower_tod_second",
-        PTPTM_PTPTM_TRIGGER_IN_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0064,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_trigger_in_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trigger_in_high_tod_second",
-        PTPTM_PTPTM_TRIGGER_IN_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0068,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_trigger_in_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trigger_in_fracnanosecond",
-        PTPTM_PTPTM_TRIGGER_IN_FRACNANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x006c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_trigger_in_fracnanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trigger_in_hardware_time_low",
-        PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_LOWr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0070,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_trigger_in_hardware_time_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trigger_in_hardware_time_high",
-        PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_HIGHr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0074,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_trigger_in_hardware_time_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trigger_out_tod_nanosecond",
-        PTPTM_PTPTM_TRIGGER_OUT_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0080,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_trigger_out_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trigger_out_lower_tod_second",
-        PTPTM_PTPTM_TRIGGER_OUT_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0084,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_trigger_out_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trigger_out_high_tod_second",
-        PTPTM_PTPTM_TRIGGER_OUT_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0088,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_trigger_out_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trigger_out_hardware_time_low",
-        PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_LOWr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0090,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_trigger_out_hardware_time_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "trigger_out_hardware_time_high",
-        PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_HIGHr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0094,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_trigger_out_hardware_time_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "adjust_tod_nanosecond",
-        PTPTM_PTPTM_ADJUST_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_adjust_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "adjust_lower_tod_second",
-        PTPTM_PTPTM_ADJUST_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_adjust_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "adjust_high_tod_second",
-        PTPTM_PTPTM_ADJUST_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_adjust_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "adjust_fracnanosecond",
-        PTPTM_PTPTM_ADJUST_FRACNANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_adjust_fracnanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "adjust_hardware_time_low",
-        PTPTM_PTPTM_ADJUST_HARDWARE_TIME_LOWr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_adjust_hardware_time_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "adjust_hardware_time_high",
-        PTPTM_PTPTM_ADJUST_HARDWARE_TIME_HIGHr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_adjust_hardware_time_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "latch_tod_nanosecond",
-        PTPTM_PTPTM_LATCH_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_latch_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "latch_lower_tod_second",
-        PTPTM_PTPTM_LATCH_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_latch_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "latch_high_tod_second",
-        PTPTM_PTPTM_LATCH_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_latch_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "latch_fracnanosecond",
-        PTPTM_PTPTM_LATCH_FRACNANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_latch_fracnanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "latch_hardware_time_low",
-        PTPTM_PTPTM_LATCH_HARDWARE_TIME_LOWr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_latch_hardware_time_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "latch_hardware_time_high",
-        PTPTM_PTPTM_LATCH_HARDWARE_TIME_HIGHr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_latch_hardware_time_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "real_tod_nanosecond",
-        PTPTM_PTPTM_REAL_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_real_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "real_lower_tod_second",
-        PTPTM_PTPTM_REAL_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_real_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "real_high_tod_second",
-        PTPTM_PTPTM_REAL_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_real_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "real_hardware_time_low",
-        PTPTM_PTPTM_REAL_HARDWARE_TIME_LOWr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_real_hardware_time_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "real_hardware_time_high",
-        PTPTM_PTPTM_REAL_HARDWARE_TIME_HIGHr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_real_hardware_time_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ptp1588_event_message_port",
-        PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_PORTr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0100,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_ptp1588_event_message_port_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ptp1588_event_message_timestamp_low",
-        PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_LOWr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0104,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_ptp1588_event_message_timestamp_low_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ptp1588_event_message_timestamp_high",
-        PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_HIGHr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0108,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_ptp1588_event_message_timestamp_high_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "ptp1588_event_message_fifo_status",
-        PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_FIFO_STATUSr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x010c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        3,
-        g_ptptm_ptptm_ptp1588_event_message_fifo_status_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tod_nanosecond",
-        PTPTM_PTPTM_PP1S_LATCH_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0120,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_lower_tod_second",
-        PTPTM_PTPTM_PP1S_LATCH_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0124,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_high_tod_second",
-        PTPTM_PTPTM_PP1S_LATCH_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0128,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_fracnanosecond",
-        PTPTM_PTPTM_PP1S_LATCH_FRACNANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x012c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_fracnanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn_time_configuration",
-        PTPTM_PTPTM_TSN_TIME_CONFIGURATIONr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0140,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_ptptm_ptptm_tsn_time_configuration_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn_timer_control",
-        PTPTM_PTPTM_TSN_TIMER_CONTROLr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00144,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        4,
-        g_ptptm_ptptm_tsn_timer_control_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn0_clock_cycle_integer",
-        PTPTM_PTPTM_TSN0_CLOCK_CYCLE_INTEGERr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x00148,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn0_clock_cycle_integer_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn0_clock_cycle_fraction",
-        PTPTM_PTPTM_TSN0_CLOCK_CYCLE_FRACTIONr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x014c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn0_clock_cycle_fraction_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn1_clock_cycle_integer",
-        PTPTM_PTPTM_TSN1_CLOCK_CYCLE_INTEGERr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0150,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn1_clock_cycle_integer_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn1_clock_cycle_fraction",
-        PTPTM_PTPTM_TSN1_CLOCK_CYCLE_FRACTIONr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0154,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn1_clock_cycle_fraction_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn2_clock_cycle_integer",
-        PTPTM_PTPTM_TSN2_CLOCK_CYCLE_INTEGERr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0158,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn2_clock_cycle_integer_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn2_clock_cycle_fraction",
-        PTPTM_PTPTM_TSN2_CLOCK_CYCLE_FRACTIONr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x015c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn2_clock_cycle_fraction_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn3_clock_cycle_integer",
-        PTPTM_PTPTM_TSN3_CLOCK_CYCLE_INTEGERr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0160,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn3_clock_cycle_integer_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn3_clock_cycle_fraction",
-        PTPTM_PTPTM_TSN3_CLOCK_CYCLE_FRACTIONr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0164,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn3_clock_cycle_fraction_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn0_adjust_tod_nanosecond",
-        PTPTM_PTPTM_TSN0_ADJUST_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0180,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn0_adjust_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn0_adjust_lower_tod_second",
-        PTPTM_PTPTM_TSN0_ADJUST_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0184,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn0_adjust_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn0_adjust_high_tod_second",
-        PTPTM_PTPTM_TSN0_ADJUST_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0188,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn0_adjust_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn0_adjust_fracnanosecond",
-        PTPTM_PTPTM_TSN0_ADJUST_FRACNANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x018c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn0_adjust_fracnanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn1_adjust_tod_nanosecond",
-        PTPTM_PTPTM_TSN1_ADJUST_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0190,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn1_adjust_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn1_adjust_lower_tod_second",
-        PTPTM_PTPTM_TSN1_ADJUST_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0194,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn1_adjust_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn1_adjust_high_tod_second",
-        PTPTM_PTPTM_TSN1_ADJUST_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0198,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn1_adjust_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn1_adjust_fracnanosecond",
-        PTPTM_PTPTM_TSN1_ADJUST_FRACNANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x019c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn1_adjust_fracnanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn2_adjust_tod_nanosecond",
-        PTPTM_PTPTM_TSN2_ADJUST_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn2_adjust_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn2_adjust_lower_tod_second",
-        PTPTM_PTPTM_TSN2_ADJUST_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn2_adjust_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn2_adjust_high_tod_second",
-        PTPTM_PTPTM_TSN2_ADJUST_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01a8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn2_adjust_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn2_adjust_fracnanosecond",
-        PTPTM_PTPTM_TSN2_ADJUST_FRACNANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01ac,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn2_adjust_fracnanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn3_adjust_tod_nanosecond",
-        PTPTM_PTPTM_TSN3_ADJUST_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01b0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn3_adjust_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn3_adjust_lower_tod_second",
-        PTPTM_PTPTM_TSN3_ADJUST_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01b4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn3_adjust_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn3_adjust_high_tod_second",
-        PTPTM_PTPTM_TSN3_ADJUST_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01b8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn3_adjust_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn3_adjust_fracnanosecond",
-        PTPTM_PTPTM_TSN3_ADJUST_FRACNANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01bc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn3_adjust_fracnanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn0_latch_tod_nanosecond",
-        PTPTM_PTPTM_TSN0_LATCH_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01c0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn0_latch_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn0_latch_lower_tod_second",
-        PTPTM_PTPTM_TSN0_LATCH_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01c4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn0_latch_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn0_latch_high_tod_second",
-        PTPTM_PTPTM_TSN0_LATCH_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01c8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn0_latch_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn0_latch_fracnanosecond",
-        PTPTM_PTPTM_TSN0_LATCH_FRACNANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01cc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn0_latch_fracnanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn1_latch_tod_nanosecond",
-        PTPTM_PTPTM_TSN1_LATCH_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01d0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn1_latch_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn1_latch_lower_tod_second",
-        PTPTM_PTPTM_TSN1_LATCH_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01d4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn1_latch_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn1_latch_high_tod_second",
-        PTPTM_PTPTM_TSN1_LATCH_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01d8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn1_latch_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn1_latch_fracnanosecond",
-        PTPTM_PTPTM_TSN1_LATCH_FRACNANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01dc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn1_latch_fracnanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn2_latch_tod_nanosecond",
-        PTPTM_PTPTM_TSN2_LATCH_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01e0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn2_latch_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn2_latch_lower_tod_second",
-        PTPTM_PTPTM_TSN2_LATCH_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01e4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn2_latch_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn2_latch_high_tod_second",
-        PTPTM_PTPTM_TSN2_LATCH_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01e8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn2_latch_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn2_latch_fracnanosecond",
-        PTPTM_PTPTM_TSN2_LATCH_FRACNANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01ec,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn2_latch_fracnanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn3_latch_tod_nanosecond",
-        PTPTM_PTPTM_TSN3_LATCH_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01f0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn3_latch_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn3_latch_lower_tod_second",
-        PTPTM_PTPTM_TSN3_LATCH_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01f4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn3_latch_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn3_latch_high_tod_second",
-        PTPTM_PTPTM_TSN3_LATCH_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01f8,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn3_latch_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn3_latch_fracnanosecond",
-        PTPTM_PTPTM_TSN3_LATCH_FRACNANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x01fc,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn3_latch_fracnanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tsn0_tod_nanosecond",
-        PTPTM_PTPTM_PP1S_LATCH_TSN0_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0200,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tsn0_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tsn0_lower_tod_second",
-        PTPTM_PTPTM_PP1S_LATCH_TSN0_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0204,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tsn0_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tsn0_high_tod_second",
-        PTPTM_PTPTM_PP1S_LATCH_TSN0_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0208,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tsn0_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tsn0_fracnanosecond",
-        PTPTM_PTPTM_PP1S_LATCH_TSN0_FRACNANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x020c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tsn0_fracnanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tsn1_tod_nanosecond",
-        PTPTM_PTPTM_PP1S_LATCH_TSN1_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0210,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tsn1_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tsn1_lower_tod_second",
-        PTPTM_PTPTM_PP1S_LATCH_TSN1_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0214,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tsn1_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tsn1_high_tod_second",
-        PTPTM_PTPTM_PP1S_LATCH_TSN1_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0218,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tsn1_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tsn1_fracnanosecond",
-        PTPTM_PTPTM_PP1S_LATCH_TSN1_FRACNANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x021c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tsn1_fracnanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tsn2_tod_nanosecond",
-        PTPTM_PTPTM_PP1S_LATCH_TSN2_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0220,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tsn2_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tsn2_lower_tod_second",
-        PTPTM_PTPTM_PP1S_LATCH_TSN2_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0224,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tsn2_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tsn2_high_tod_second",
-        PTPTM_PTPTM_PP1S_LATCH_TSN2_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0228,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tsn2_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tsn2_fracnanosecond",
-        PTPTM_PTPTM_PP1S_LATCH_TSN2_FRACNANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x022c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tsn2_fracnanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tsn3_tod_nanosecond",
-        PTPTM_PTPTM_PP1S_LATCH_TSN3_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0230,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tsn3_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tsn3_lower_tod_second",
-        PTPTM_PTPTM_PP1S_LATCH_TSN3_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0234,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tsn3_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tsn3_high_tod_second",
-        PTPTM_PTPTM_PP1S_LATCH_TSN3_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0238,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tsn3_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "pp1s_latch_tsn3_fracnanosecond",
-        PTPTM_PTPTM_PP1S_LATCH_TSN3_FRACNANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x023c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_pp1s_latch_tsn3_fracnanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn0_real_tod_nanosecond",
-        PTPTM_PTPTM_TSN0_REAL_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0240,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn0_real_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn0_real_lower_tod_second",
-        PTPTM_PTPTM_TSN0_REAL_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0244,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn0_real_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn0_real_high_tod_second",
-        PTPTM_PTPTM_TSN0_REAL_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0248,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn0_real_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn1_real_tod_nanosecond",
-        PTPTM_PTPTM_TSN1_REAL_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x024c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn1_real_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn1_real_lower_tod_second",
-        PTPTM_PTPTM_TSN1_REAL_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0250,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn1_real_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn1_real_high_tod_second",
-        PTPTM_PTPTM_TSN1_REAL_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0254,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn1_real_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn2_real_tod_nanosecond",
-        PTPTM_PTPTM_TSN2_REAL_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0258,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn2_real_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn2_real_lower_tod_second",
-        PTPTM_PTPTM_TSN2_REAL_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x025c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn2_real_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn2_real_high_tod_second",
-        PTPTM_PTPTM_TSN2_REAL_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0260,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn2_real_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn3_real_tod_nanosecond",
-        PTPTM_PTPTM_TSN3_REAL_TOD_NANOSECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0264,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn3_real_tod_nanosecond_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn3_real_lower_tod_second",
-        PTPTM_PTPTM_TSN3_REAL_LOWER_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0268,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn3_real_lower_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "tsn3_real_high_tod_second",
-        PTPTM_PTPTM_TSN3_REAL_HIGH_TOD_SECONDr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x026c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_tsn3_real_high_tod_second_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "real_ptp_clock_cycle_integer",
-        PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_INTEGERr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0280,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_real_ptp_clock_cycle_integer_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "real_ptp_clock_cycle_fraction",
-        PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_FRACTIONr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0284,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_real_ptp_clock_cycle_fraction_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "real_tsn0_clock_cycle_integer",
-        PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_INTEGERr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0288,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_real_tsn0_clock_cycle_integer_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "real_tsn0_clock_cycle_fraction",
-        PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_FRACTIONr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x028c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_real_tsn0_clock_cycle_fraction_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "real_tsn1_clock_cycle_integer",
-        PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_INTEGERr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0290,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_real_tsn1_clock_cycle_integer_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "real_tsn1_clock_cycle_fraction",
-        PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_FRACTIONr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0294,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_real_tsn1_clock_cycle_fraction_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "real_tsn2_clock_cycle_integer",
-        PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_INTEGERr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x0298,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_real_tsn2_clock_cycle_integer_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "real_tsn2_clock_cycle_fraction",
-        PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_FRACTIONr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x029c,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_real_tsn2_clock_cycle_fraction_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "real_tsn3_clock_cycle_integer",
-        PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_INTEGERr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x02a0,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_real_tsn3_clock_cycle_integer_reg,
-        NULL,
-        NULL,
-    },
-    {
-        "real_tsn3_clock_cycle_fraction",
-        PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_FRACTIONr,
-        PTPTM,
-        DPP_REG_FLAG_DIRECT,
-        DPP_REG_NUL_ARRAY,
-        SYS_PTP1_BASE_ADDR + 0x02a4,
-        (32/8),
-        0,
-        0,
-        0,
-        0,
-        1,
-        g_ptptm_ptptm_real_tsn3_clock_cycle_fraction_reg,
-        NULL,
-        NULL,
-    },
+DPP_FIELD_T g_etm_cfgmt_cpu_check_reg_reg[] = {
+	{ "cpu_check_reg", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_cfgmt_blksize_reg[] = {
+	{ "cfgmt_blksize", DPP_FIELD_FLAG_RW, 1, 2, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_reg_int_state_reg_reg[] = {
+	{ "shap_int", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "crdt_int", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "mmu_int", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "qmu_int", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "cgavd_int", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "olif_int", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "cfgmt_int_buf", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_reg_int_mask_reg_reg[] = {
+	{ "shap_int_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "crdt_int_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "tmmu_int_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "qmu_int_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "cgavd_int_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "olif_int_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "cfgmt_int_buf_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_timeout_limit_reg[] = {
+	{ "timeout_limit", DPP_FIELD_FLAG_RW, 15, 16, 0xfff, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_subsystem_rdy_reg_reg[] = {
+	{ "olif_rdy", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "qmu_rdy", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "cgavd_rdy", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "tmmu_rdy", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "shap_rdy", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "crdt_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_subsystem_en_reg_reg[] = {
+	{ "subsystem_en_buf_31_28", DPP_FIELD_FLAG_RW, 31, 4, 0x0, 0x0 },
+	{ "subsystem_en_buf_25_0", DPP_FIELD_FLAG_RW, 25, 26, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_cfgmt_int_reg_reg[] = {
+	{ "cfgmt_int_buf", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_qmu_work_mode_reg[] = {
+	{ "qmu_work_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_cfgmt_ddr_attach_reg[] = {
+	{ "cfgmt_ddr_attach", DPP_FIELD_FLAG_RW, 9, 10, 0xf, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_cnt_mode_reg_reg[] = {
+	{ "cfgmt_fc_count_mode", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0 },
+	{ "cfgmt_count_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_clkgate_en_reg[] = {
+	{ "clkgate_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_softrst_en_reg[] = {
+	{ "softrst_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_imem_prog_full_reg[] = {
+	{ "imem_prog_full_assert", DPP_FIELD_FLAG_RW, 24, 9, 0x9c, 0x0 },
+	{ "imem_prog_full_negate", DPP_FIELD_FLAG_RW, 8, 9, 0x94, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_qmu_para_prog_full_reg[] = {
+	{ "qmu_para_prog_full_assert", DPP_FIELD_FLAG_RW, 26, 11, 0x370, 0x0 },
+	{ "qmu_para_prog_full_negate", DPP_FIELD_FLAG_RW, 10, 11, 0x370, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_olif_int_mask_reg[] = {
+	{ "emem_dat_sop_err_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "emem_dat_eop_err_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "imem_dat_sop_err_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "imem_dat_eop_err_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "crcram_parity_err_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "emem_fifo_ecc_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "imem_fifo_ecc_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "emem_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "emem_fifo_udf_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "imem_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "imem_fifo_udf_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "para_fifo_ecc_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "para_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "para_fifo_udf_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "itmh_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "itmh_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "order_fifo_parity_err_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "order_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "order_fifo_udf_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_itmhram_parity_err_2_int_reg[] = {
+	{ "emem_dat_sop_err", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "emem_dat_eop_err", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "imem_dat_sop_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "imem_dat_eop_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "crcram_parity_err_1_int", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "emem_fifo_ecc_single_err_int", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "emem_fifo_ecc_double_err_int", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "imem_fifo_ecc_single_err_int", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "imem_fifo_ecc_double_err_int", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "emem_fifo_ovf_int", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "emem_fifo_udf_int", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "imem_fifo_ovf_int", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "imem_fifo_udf_int", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "para_fifo_ecc_single_err_int", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "para_fifo_ecc_double_err_int", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "para_fifo_ovf_int", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "para_fifo_udf_int", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "itmh_ecc_single_err_int", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "itmh_ecc_double_err_int", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "order_fifo_parity_err_int", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "order_fifo_ovf_int", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "order_fifo_udf_int", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_lif0_port_rdy_mask_h_reg[] = {
+	{ "lif0_port_rdy_mask_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_lif0_port_rdy_mask_l_reg[] = {
+	{ "lif0_port_rdy_mask_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_lif0_port_rdy_cfg_h_reg[] = {
+	{ "lif0_port_rdy_cfg_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_lif0_port_rdy_cfg_l_reg[] = {
+	{ "lif0_port_rdy_cfg_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_lif0_link_rdy_mask_cfg_reg[] = {
+	{ "lif0_link_rdy_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "lif0_link_rdy_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_tm_lif_stat_cfg_reg[] = {
+	{ "all_or_by_port", DPP_FIELD_FLAG_RW, 24, 1, 0x0, 0x0 },
+	{ "i_or_e_sel", DPP_FIELD_FLAG_RW, 17, 2, 0x0, 0x0 },
+	{ "port_or_dest_id_sel", DPP_FIELD_FLAG_RW, 8, 1, 0x0, 0x0 },
+	{ "port_dest_id", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x1 },
+};
+DPP_FIELD_T g_etm_olif_tm_lif_sop_stat_reg[] = {
+	{ "tm_lif_sop_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_tm_lif_eop_stat_reg[] = {
+	{ "tm_lif_eop_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_tm_lif_vld_stat_reg[] = {
+	{ "tm_lif_vld_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_prog_full_assert_cfg_reg[] = {
+	{ "prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 31, 16, 0xdc, 0x0 },
+	{ "prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 15, 16, 0xc8, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_int_reg[] = {
+	{ "cgavd_int", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_ram_err_reg[] = {
+	{ "flow_qnum_intb", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "flow_qnum_inta", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "pp_qlen_inta", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "pp_qlen_intb", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "pp_tdth_int", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "flow_tdth_inta", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "flow_tdth_intb", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "flow_qlen_inta", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "flow_qlen_intb", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "qmu_cgavd_fifo_uv_int", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "qmu_cgavd_fifo_ov_int", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "pds_deal_fifo_ov_int", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "pds_deal_fifo_uv_int", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_int_mask_reg[] = {
+	{ "cgavd_int_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_ram_err_int_mask_reg[] = {
+	{ "flow_qnum_inta_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "flow_qnum_intb_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "pp_qlen_inta_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "pp_qlen_intb_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "pp_tdth_int_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "flow_tdth_inta_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "flow_tdth_intb_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "flow_qlen_inta_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "flow_qlen_intb_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "qmu_cgavd_fifo_uv_int_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "qmu_cgavd_fifo_ov_int_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "pds_deal_fifo_ov_int_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "pds_deal_fifo_uv_int_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cfgmt_byte_mode_reg[] = {
+	{ "cfgmt_byte_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_avg_qlen_return_zero_en_reg[] = {
+	{ "avg_qlen_return_zero_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_wred_q_len_th_reg[] = {
+	{ "flow_wred_q_len_th", DPP_FIELD_FLAG_RW, 28, 29, 0x400, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_wq_reg[] = {
+	{ "wq_flow", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_wred_max_th_reg[] = {
+	{ "flow_wred_max_th", DPP_FIELD_FLAG_RW, 28, 29, 0x1000, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_wred_min_th_reg[] = {
+	{ "flow_wred_min_th", DPP_FIELD_FLAG_RW, 28, 29, 0x10, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_wred_cfg_para_reg[] = {
+	{ "flow_wred_cfg_para", DPP_FIELD_FLAG_RW, 31, 32, 0x13ec, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_pp_avg_q_len_reg[] = {
+	{ "pp_avg_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_pp_td_th_reg[] = {
+	{ "pp_td_th", DPP_FIELD_FLAG_RW, 28, 29, 0x400, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_pp_ca_mtd_reg[] = {
+	{ "pp_ca_mtd", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_pp_wred_grp_th_en_reg[] = {
+	{ "pp_wred_grp", DPP_FIELD_FLAG_RW, 3, 3, 0x0, 0x0 },
+	{ "pp_wred_grp_th_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_pp_wred_q_len_th_reg[] = {
+	{ "pp_wred_q_len_th", DPP_FIELD_FLAG_RW, 28, 29, 0x100000, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_pp_wq_reg[] = {
+	{ "wq_pp", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_pp_wred_max_th_reg[] = {
+	{ "pp_wred_max_th", DPP_FIELD_FLAG_RW, 28, 29, 0x80000, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_pp_wred_min_th_reg[] = {
+	{ "pp_wred_min_th", DPP_FIELD_FLAG_RW, 28, 29, 0x800, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_pp_cfg_para_reg[] = {
+	{ "pp_cfg_para", DPP_FIELD_FLAG_RW, 31, 32, 0x9f600, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_sys_avg_q_len_reg[] = {
+	{ "sys_avg_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_sys_td_th_reg[] = {
+	{ "sys_td_th", DPP_FIELD_FLAG_RW, 28, 29, 0x1ff00, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_sys_cgavd_metd_reg[] = {
+	{ "sys_cgavd_metd", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_sys_cfg_q_grp_para_reg[] = {
+	{ "gred_q_len_th_sys", DPP_FIELD_FLAG_RW, 28, 29, 0x1fffe00, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_sys_wq_reg[] = {
+	{ "wq_sys", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_gred_max_th_reg[] = {
+	{ "gred_max_th", DPP_FIELD_FLAG_RW, 28, 29, 0x1000000, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_gred_mid_th_reg[] = {
+	{ "gred_mid_th", DPP_FIELD_FLAG_RW, 28, 29, 0x600000, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_gred_min_th_reg[] = {
+	{ "gred_min_th", DPP_FIELD_FLAG_RW, 28, 29, 0x80000, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_gred_cfg_para0_reg[] = {
+	{ "gred_cfg_para0", DPP_FIELD_FLAG_RW, 31, 32, 0x92aaaa, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_gred_cfg_para1_reg[] = {
+	{ "gred_cfg_para1", DPP_FIELD_FLAG_RW, 31, 32, 0x1900000, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_gred_cfg_para2_reg[] = {
+	{ "gred_cfg_para2", DPP_FIELD_FLAG_RW, 31, 32, 0xf00000, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_sys_window_th_h_reg[] = {
+	{ "sys_window_th_h", DPP_FIELD_FLAG_RW, 28, 29, 0x1d00000, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_sys_window_th_l_reg[] = {
+	{ "sys_window_th_l", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_amplify_gene0_reg[] = {
+	{ "amplify_gene0", DPP_FIELD_FLAG_RW, 11, 12, 0x200, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_amplify_gene1_reg[] = {
+	{ "amplify_gene1", DPP_FIELD_FLAG_RW, 11, 12, 0x82, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_amplify_gene2_reg[] = {
+	{ "amplify_gene2", DPP_FIELD_FLAG_RW, 11, 12, 0x80, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_amplify_gene3_reg[] = {
+	{ "amplify_gene3", DPP_FIELD_FLAG_RW, 11, 12, 0x7e, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_amplify_gene4_reg[] = {
+	{ "amplify_gene4", DPP_FIELD_FLAG_RW, 11, 12, 0x7c, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_amplify_gene5_reg[] = {
+	{ "amplify_gene5", DPP_FIELD_FLAG_RW, 11, 12, 0x78, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_amplify_gene6_reg[] = {
+	{ "amplify_gene6", DPP_FIELD_FLAG_RW, 11, 12, 0x70, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_amplify_gene7_reg[] = {
+	{ "amplify_gene7", DPP_FIELD_FLAG_RW, 11, 12, 0x68, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_amplify_gene8_reg[] = {
+	{ "amplify_gene8", DPP_FIELD_FLAG_RW, 11, 12, 0x60, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_amplify_gene9_reg[] = {
+	{ "amplify_gene9", DPP_FIELD_FLAG_RW, 11, 12, 0x58, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_amplify_gene10_reg[] = {
+	{ "amplify_gene10", DPP_FIELD_FLAG_RW, 11, 12, 0x50, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_amplify_gene11_reg[] = {
+	{ "amplify_gene11", DPP_FIELD_FLAG_RW, 11, 12, 0x40, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_amplify_gene12_reg[] = {
+	{ "amplify_gene12", DPP_FIELD_FLAG_RW, 11, 12, 0x20, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_amplify_gene13_reg[] = {
+	{ "amplify_gene13", DPP_FIELD_FLAG_RW, 11, 12, 0x8, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_amplify_gene14_reg[] = {
+	{ "amplify_gene14", DPP_FIELD_FLAG_RW, 11, 12, 0x2, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_amplify_gene15_reg[] = {
+	{ "amplify_gene15", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_equal_pkt_len_en_reg[] = {
+	{ "equal_pkt_len_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th0_reg[] = {
+	{ "equal_pkt_len_th0", DPP_FIELD_FLAG_RW, 14, 15, 0x4, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th1_reg[] = {
+	{ "equal_pkt_len_th1", DPP_FIELD_FLAG_RW, 14, 15, 0x8, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th2_reg[] = {
+	{ "equal_pkt_len_th2", DPP_FIELD_FLAG_RW, 14, 15, 0x10, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th3_reg[] = {
+	{ "equal_pkt_len_th3", DPP_FIELD_FLAG_RW, 14, 15, 0x18, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th4_reg[] = {
+	{ "equal_pkt_len_th4", DPP_FIELD_FLAG_RW, 14, 15, 0x20, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th5_reg[] = {
+	{ "equal_pkt_len_th5", DPP_FIELD_FLAG_RW, 14, 15, 0x40, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_equal_pkt_len_th6_reg[] = {
+	{ "equal_pkt_len_th6", DPP_FIELD_FLAG_RW, 14, 15, 0x60, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_equal_pkt_len0_reg[] = {
+	{ "equal_pkt_len0", DPP_FIELD_FLAG_RW, 14, 15, 0x20, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_equal_pkt_len1_reg[] = {
+	{ "equal_pkt_len1", DPP_FIELD_FLAG_RW, 14, 15, 0x30, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_equal_pkt_len2_reg[] = {
+	{ "equal_pkt_len2", DPP_FIELD_FLAG_RW, 14, 15, 0x40, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_equal_pkt_len3_reg[] = {
+	{ "equal_pkt_len3", DPP_FIELD_FLAG_RW, 14, 15, 0x50, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_equal_pkt_len4_reg[] = {
+	{ "equal_pkt_len4", DPP_FIELD_FLAG_RW, 14, 15, 0x60, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_equal_pkt_len5_reg[] = {
+	{ "equal_pkt_len5", DPP_FIELD_FLAG_RW, 14, 15, 0x70, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_equal_pkt_len6_reg[] = {
+	{ "equal_pkt_len6", DPP_FIELD_FLAG_RW, 14, 15, 0x78, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_equal_pkt_len7_reg[] = {
+	{ "equal_pkt_len7", DPP_FIELD_FLAG_RW, 14, 15, 0x80, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_cpu_set_avg_len_reg[] = {
+	{ "flow_cpu_set_avg_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_cpu_set_q_len_reg[] = {
+	{ "flow_cpu_set_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_pp_cpu_set_avg_q_len_reg[] = {
+	{ "pp_cpu_set_avg_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_pp_cpu_set_q_len_reg[] = {
+	{ "pp_cpu_set_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_sys_cpu_set_avg_len_reg[] = {
+	{ "sys_cpu_set_avg_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_sys_cpu_set_q_len_reg[] = {
+	{ "sys_cpu_set_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_pke_len_calc_sign_reg[] = {
+	{ "pke_len_calc_sign", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_rd_cpu_or_ram_reg[] = {
+	{ "cpu_sel_sys_q_len_en", DPP_FIELD_FLAG_RW, 5, 1, 0x0, 0x0 },
+	{ "cpu_sel_sys_avg_q_len_en", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0 },
+	{ "cpu_sel_pp_q_len_en", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0 },
+	{ "cpu_sel_pp_avg_q_len_en", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0 },
+	{ "cpu_sel_flow_q_len_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "cpu_sel_flow_avg_q_len_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_q_len_update_disable_reg[] = {
+	{ "q_len_sys_update_en", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0 },
+	{ "q_len_pp_update_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "q_len_flow_update_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_dp_sel_reg[] = {
+	{ "flow_dp_sel_high", DPP_FIELD_FLAG_RW, 8, 1, 0x0, 0x0 },
+	{ "flow_dp_sel_mid", DPP_FIELD_FLAG_RW, 7, 1, 0x0, 0x0 },
+	{ "flow_dp_sel_low", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "pp_dp_sel_high", DPP_FIELD_FLAG_RW, 5, 1, 0x0, 0x0 },
+	{ "pp_dp_sel_mid", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0 },
+	{ "pp_dp_sel_low", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "sys_dp_sel_high", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0 },
+	{ "sys_dp_sel_mid", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "sys_dp_sel_low", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_sub_en_reg[] = {
+	{ "cgavd_sa_sub_en", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0 },
+	{ "cgavd_sys_sub_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "cgavd_pp_sub_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "cgavd_flow_sub_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_default_start_queue_reg[] = {
+	{ "default_start_queue", DPP_FIELD_FLAG_RW, 13, 14, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_default_finish_queue_reg[] = {
+	{ "default_finish_queue", DPP_FIELD_FLAG_RW, 13, 14, 0x1ff, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_protocol_start_queue_reg[] = {
+	{ "protocol_start_queue", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_protocol_finish_queue_reg[] = {
+	{ "protocol_finish_queue", DPP_FIELD_FLAG_RW, 13, 14, 0xff, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_uniform_td_th_reg[] = {
+	{ "uniform_td_th", DPP_FIELD_FLAG_RW, 28, 29, 0x200, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_uniform_td_th_en_reg[] = {
+	{ "uniform_td_th_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_cfg_fc_reg[] = {
+	{ "cgavd_cfg_fc", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_cfg_no_fc_reg[] = {
+	{ "cgavd_cfg_no_fc", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_force_imem_omem_reg[] = {
+	{ "imem_omem_force_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "choose_imem_omem", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_sys_q_len_l_reg[] = {
+	{ "cgavd_sys_q_len_l", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_default_queue_en_reg[] = {
+	{ "default_queue_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_protocol_queue_en_reg[] = {
+	{ "protocol_queue_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cfg_tc_flowid_dat_reg[] = {
+	{ "cfg_tc_flowid_dat", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_td_th_reg[] = {
+	{ "flow_td_th", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_ca_mtd_reg[] = {
+	{ "flow_ca_mtd", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_dynamic_th_en_reg[] = {
+	{ "flow_dynamic_th_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_pp_num_reg[] = {
+	{ "pp_num", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_q_len_reg[] = {
+	{ "flow_q_len", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_wred_grp_reg[] = {
+	{ "flow_wred_grp", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_avg_q_len_reg[] = {
+	{ "flow_avg_q_len", DPP_FIELD_FLAG_RW, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_qos_sign_reg[] = {
+	{ "qos_sign_flow_cfg_din", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_q_pri_reg[] = {
+	{ "qpri_flow_cfg_din", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_odma_tm_itmd_rd_low_reg[] = {
+	{ "odma_tm_itmd_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_odma_tm_itmd_rd_mid_reg[] = {
+	{ "odma_tm_itmd_mid", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_odma_tm_itmd_rd_high_reg[] = {
+	{ "odma_tm_itmd_high", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_stat_pkt_len_reg[] = {
+	{ "expect_deq_pkt_len", DPP_FIELD_FLAG_RW, 25, 10, 0x0, 0x0 },
+	{ "expect_enq_pkt_len", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_stat_qnum_reg[] = {
+	{ "cgavd_unexcept_qnum", DPP_FIELD_FLAG_RW, 29, 14, 0x0, 0x0 },
+	{ "cgavd_except_qnum", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_stat_dp_reg[] = {
+	{ "cgavd_stat_dp", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_num0_reg[] = {
+	{ "flow_num0", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_num1_reg[] = {
+	{ "flow_num1", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_num2_reg[] = {
+	{ "flow_num2", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_num3_reg[] = {
+	{ "flow_num3", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow_num4_reg[] = {
+	{ "flow_num4", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow0_imem_cnt_reg[] = {
+	{ "flow0_imem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow1_imem_cnt_reg[] = {
+	{ "flow1_imem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow2_imem_cnt_reg[] = {
+	{ "flow2_imem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow3_imem_cnt_reg[] = {
+	{ "flow3_imem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow4_imem_cnt_reg[] = {
+	{ "flow4_imem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow0_drop_cnt_reg[] = {
+	{ "flow0_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow1_drop_cnt_reg[] = {
+	{ "flow1_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow2_drop_cnt_reg[] = {
+	{ "flow2_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow3_drop_cnt_reg[] = {
+	{ "flow3_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow4_drop_cnt_reg[] = {
+	{ "flow4_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_fc_count_mode_reg[] = {
+	{ "fc_count_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_qmu_cgavd_fc_num_reg[] = {
+	{ "qmu_cgavd_fc_state", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0 },
+	{ "qmu_cgavd_fc_num", DPP_FIELD_FLAG_RO, 30, 31, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_odma_fc_num_reg[] = {
+	{ "cgavd_lif_fc_state", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0 },
+	{ "cgavd_lif_fc_num", DPP_FIELD_FLAG_RO, 30, 31, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cfg_offset_reg[] = {
+	{ "cfg_offset", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_init_done_reg[] = {
+	{ "tmmu_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_int_mask_1_reg[] = {
+	{ "imem_enq_rd_fifo_full_mask", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "imem_enq_rd_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "imem_enq_rd_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "imem_enq_drop_fifo_full_mask", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "imem_enq_drop_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "imem_enq_drop_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "imem_deq_rd_fifo_full_mask", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "imem_deq_rd_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "imem_deq_rd_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "imem_deq_drop_fifo_full_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "imem_deq_drop_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "imem_deq_drop_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "dma_data_fifo_full_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "dma_data_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "dma_data_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "wr_cmd_fifo_full_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "wr_cmd_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "wr_cmd_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "cached_pd_fifo_full_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "cached_pd_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "cached_pd_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "emem_pd_fifo_full_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "emem_pd_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "emem_pd_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "pd_order_fifo_full_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "pd_order_fifo_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "pd_order_fifo_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_int_mask_2_reg[] = {
+	{ "dma_data_fifo_parity_err_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "imem_enq_rd_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1,
+	  0x0 },
+	{ "imem_enq_rd_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1,
+	  0x0 },
+	{ "imem_enq_drop_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1,
+	  0x0 },
+	{ "imem_enq_drop_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1,
+	  0x0 },
+	{ "imem_deq_rd_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1,
+	  0x0 },
+	{ "imem_deq_rd_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1,
+	  0x0 },
+	{ "imem_deq_drop_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1,
+	  0x0 },
+	{ "imem_deq_drop_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1,
+	  0x0 },
+	{ "wr_cmd_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "wr_cmd_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "pd_cache_ram_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "pd_cache_ram_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "cached_pd_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "cached_pd_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "emem_pd_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "emem_pd_fifo_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_tm_pure_imem_en_reg[] = {
+	{ "cfgmt_tm_pure_imem_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_force_ddr_rdy_cfg_reg[] = {
+	{ "cfgmt_force_ddr_rdy_cfg", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_pd_order_fifo_aful_th_reg[] = {
+	{ "pd_order_fifo_aful_th", DPP_FIELD_FLAG_RW, 10, 11, 0x384, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cached_pd_fifo_aful_th_reg[] = {
+	{ "cached_pd_fifo_aful_th", DPP_FIELD_FLAG_RW, 9, 10, 0x1f0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_wr_cmd_fifo_aful_th_reg[] = {
+	{ "wr_cmd_fifo_aful_th", DPP_FIELD_FLAG_RW, 9, 10, 0x190, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_imem_enq_rd_fifo_aful_th_reg[] = {
+	{ "imem_enq_rd_fifo_aful_th", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_imem_enq_drop_fifo_aful_th_reg[] = {
+	{ "imem_enq_drop_fifo_aful_th", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_imem_deq_drop_fifo_aful_th_reg[] = {
+	{ "imem_deq_drop_fifo_aful_th", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_imem_deq_rd_fifo_aful_th_reg[] = {
+	{ "imem_deq_rd_fifo_aful_th", DPP_FIELD_FLAG_RW, 10, 11, 0x320, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_states_1_reg[] = {
+	{ "imem_enq_rd_fifo_full", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "imem_enq_rd_fifo_overflow", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "imem_enq_rd_fifo_underflow", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "imem_enq_drop_fifo_full", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "imem_enq_drop_fifo_overflow", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "imem_enq_drop_fifo_underflow", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "imem_deq_rd_fifo_full", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "imem_deq_rd_fifo_overflow", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "imem_deq_rd_fifo_underflow", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "imem_deq_drop_fifo_full", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "imem_deq_drop_fifo_overflow", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "imem_deq_drop_fifo_underflow", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "dma_data_fifo_full", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "dma_data_fifo_overflow", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "dma_data_fifo_underflow", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "wr_cmd_fifo_full", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "wr_cmd_fifo_overflow", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "wr_cmd_fifo_underflow", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "cached_pd_fifo_full", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "cached_pd_fifo_overflow", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "cached_pd_fifo_underflow", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "emem_pd_fifo_full", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "emem_pd_fifo_overflow", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "emem_pd_fifo_underflow", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "pd_order_fifo_full", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "pd_order_fifo_overflow", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "pd_order_fifo_underflow", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_states_2_reg[] = {
+	{ "dma_data_fifo_parity_err", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "imem_enq_rd_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "imem_enq_rd_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "imem_enq_drop_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "imem_enq_drop_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "imem_deq_rd_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "imem_deq_rd_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "imem_deq_drop_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "imem_deq_drop_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "wr_cmd_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "wr_cmd_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "pd_cache_ram_ecc_single_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "pd_cache_ram_ecc_double_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "cached_pd_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "cached_pd_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "emem_pd_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "emem_pd_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_shap_ind_cmd_reg[] = {
+	{ "rd", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0 },
+	{ "mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0 },
+	{ "addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_shap_ind_sta_reg[] = {
+	{ "indirectaccessdone", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_shap_ind_data0_reg[] = {
+	{ "indirectdata0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_shap_ind_data1_reg[] = {
+	{ "indirectdata1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_full_threshold_reg[] = {
+	{ "full_threshold", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_empty_threshold_reg[] = {
+	{ "empty_threshold", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_shap_sta_init_cfg_reg[] = {
+	{ "sta_ram_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "sta_ram_init_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_shap_cfg_init_cfg_reg[] = {
+	{ "cfg_ram_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "cfg_ram_init_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_token_mode_switch_reg[] = {
+	{ "token_mode_switch", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_token_grain_reg[] = {
+	{ "token_grain", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_crd_grain_reg[] = {
+	{ "crd_grain", DPP_FIELD_FLAG_RW, 20, 21, 0x8fc, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_shap_stat_ctrl_reg[] = {
+	{ "shap_stat_ctrl", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_token_stat_id_reg[] = {
+	{ "token_stat_id", DPP_FIELD_FLAG_RW, 10, 11, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_token_stat_reg[] = {
+	{ "token_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_shap_stat_clk_cnt_reg[] = {
+	{ "shap_stat_clk_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_shap_bucket_map_tbl_reg[] = {
+	{ "shap_map", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_bkt_para_tbl_reg[] = {
+	{ "bucket_depth", DPP_FIELD_FLAG_RW, 35, 11, 0x0, 0x0 },
+	{ "bucket_rate", DPP_FIELD_FLAG_RW, 24, 25, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_credit_en_reg[] = {
+	{ "credit_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crt_inter1_reg[] = {
+	{ "crd_inter1", DPP_FIELD_FLAG_RW, 8, 9, 0x2d, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_db_token_reg[] = {
+	{ "db_token", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crs_flt_cfg_reg[] = {
+	{ "crs_flt_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_th_sp_reg[] = {
+	{ "th_sp", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_th_wfq_fq_reg[] = {
+	{ "th_fq", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0 },
+	{ "th_wfq", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_th_wfq2_fq2_reg[] = {
+	{ "th_fq2", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0 },
+	{ "th_wfq2", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_th_wfq4_fq4_reg[] = {
+	{ "th_fq4", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0 },
+	{ "th_wfq4", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_cfg_state_reg[] = {
+	{ "cfg_state", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_ind_cmd_reg[] = {
+	{ "rd", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0 },
+	{ "mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0 },
+	{ "addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_ind_sta_reg[] = {
+	{ "indirectaccessdone", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_ind_data0_reg[] = {
+	{ "indirectdata0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_ind_data1_reg[] = {
+	{ "indirectdata1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_state_reg[] = {
+	{ "crdt_int", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "crdt_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_id_0_reg[] = {
+	{ "stat_que_id_0", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_id_1_reg[] = {
+	{ "stat_que_id_1", DPP_FIELD_FLAG_RW, 13, 14, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_id_2_reg[] = {
+	{ "stat_que_id_2", DPP_FIELD_FLAG_RW, 13, 14, 0x2, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_id_3_reg[] = {
+	{ "stat_que_id_3", DPP_FIELD_FLAG_RW, 13, 14, 0x3, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_id_4_reg[] = {
+	{ "stat_que_id_4", DPP_FIELD_FLAG_RW, 13, 14, 0x4, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_id_5_reg[] = {
+	{ "stat_que_id_5", DPP_FIELD_FLAG_RW, 13, 14, 0x5, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_id_6_reg[] = {
+	{ "stat_que_id_6", DPP_FIELD_FLAG_RW, 13, 14, 0x6, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_id_7_reg[] = {
+	{ "stat_que_id_7", DPP_FIELD_FLAG_RW, 13, 14, 0x7, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_id_8_reg[] = {
+	{ "stat_que_id_8", DPP_FIELD_FLAG_RW, 13, 14, 0x8, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_id_9_reg[] = {
+	{ "stat_que_id_9", DPP_FIELD_FLAG_RW, 13, 14, 0x9, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_id_10_reg[] = {
+	{ "stat_que_id_10", DPP_FIELD_FLAG_RW, 13, 14, 0xa, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_id_11_reg[] = {
+	{ "stat_que_id_11", DPP_FIELD_FLAG_RW, 13, 14, 0xb, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_id_12_reg[] = {
+	{ "stat_que_id_12", DPP_FIELD_FLAG_RW, 13, 14, 0xc, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_id_13_reg[] = {
+	{ "stat_que_id_13", DPP_FIELD_FLAG_RW, 13, 14, 0xd, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_id_14_reg[] = {
+	{ "stat_que_id_14", DPP_FIELD_FLAG_RW, 13, 14, 0xe, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_id_15_reg[] = {
+	{ "stat_que_id_15", DPP_FIELD_FLAG_RW, 13, 14, 0xf, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_credit_reg[] = {
+	{ "stat_que_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_cfg_ram_init_reg[] = {
+	{ "cfg_ram_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "cfg_ram_init_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_sta_ram_init_reg[] = {
+	{ "sta_ram_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "sta_ram_init_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crs_que_id_reg[] = {
+	{ "crs_que_id", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_qmu_crs_end_state_reg[] = {
+	{ "qmu_crs_end_state", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_shap_rdy_reg[] = {
+	{ "shap_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_shap_int_reg_reg[] = {
+	{ "pp_c_token_min_int", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_shap_int_mask_reg_reg[] = {
+	{ "pp_c_token_min_int_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_token_state_almost_empty_th_reg[] = {
+	{ "token_state_almost_empty_th", DPP_FIELD_FLAG_RW, 16, 17, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_token_state_empty_th_reg[] = {
+	{ "token_state_empty_th", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_full_th_reg[] = {
+	{ "token_state_full_th", DPP_FIELD_FLAG_RW, 16, 17, 0x2, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_pp_c_level_shap_en_reg[] = {
+	{ "pp_c_level_shap_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_enq_token_th_reg[] = {
+	{ "enq_token_th", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_pp_tokenq_level1_qstate_weight_cir_reg[] = {
+	{ "pp_pp_q_state_cir", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0 },
+	{ "pp_pp_q_weight_wfq_l1_cir", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_pp_idle_weight_level1_cir_reg[] = {
+	{ "pp_idle_q_weight_wfq_l1_cir", DPP_FIELD_FLAG_RO, 25, 26, 0x1ffffff,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_crdt_rci_grade_th_0_cfg_reg[] = {
+	{ "rci_grade_th_0_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x177, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_rci_grade_th_1_cfg_reg[] = {
+	{ "rci_grade_th_1_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x2ee, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_rci_grade_th_2_cfg_reg[] = {
+	{ "rci_grade_th_2_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x465, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_rci_grade_th_3_cfg_reg[] = {
+	{ "rci_grade_th_3_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x47e, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_rci_grade_th_4_cfg_reg[] = {
+	{ "rci_grade_th_4_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x753, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_rci_grade_th_5_cfg_reg[] = {
+	{ "rci_grade_th_5_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x8ca, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_rci_grade_th_6_cfg_reg[] = {
+	{ "rci_grade_th_6_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0xa41, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_flow_del_cmd_reg[] = {
+	{ "flow_del_busy", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0 },
+	{ "flow_alt_cmd", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "flow_alt_ind", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_cnt_clr_reg[] = {
+	{ "cnt_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_int_bus_reg[] = {
+	{ "ldstr_fifo15_ovf_int", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0 },
+	{ "ldstr_fifo14_ovf_int", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0 },
+	{ "ldstr_fifo13_ovf_int", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0 },
+	{ "ldstr_fifo12_ovf_int", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0 },
+	{ "ldstr_fifo11_ovf_int", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0 },
+	{ "ldstr_fifo10_ovf_int", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0 },
+	{ "ldstr_fifo9_ovf_int", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0 },
+	{ "ldstr_fifo8_ovf_int", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0 },
+	{ "ldstr_fifo7_ovf_int", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0 },
+	{ "ldstr_fifo6_ovf_int", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0 },
+	{ "ldstr_fifo5_ovf_int", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0 },
+	{ "ldstr_fifo4_ovf_int", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0 },
+	{ "ldstr_fifo3_ovf_int", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0 },
+	{ "ldstr_fifo2_ovf_int", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0 },
+	{ "ldstr_fifo1_ovf_int", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0 },
+	{ "ldstr_fifo0_ovf_int", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0 },
+	{ "cfg_del_err_int", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "flwin_secrs_fifo_ovf_int", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "flwin_voqcrs_fifo_ovf_int", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_int_mask_reg[] = {
+	{ "crdt_int_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_cfg_weight_together_reg[] = {
+	{ "cfg_weight_together", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_weight_reg[] = {
+	{ "c_weight", DPP_FIELD_FLAG_RW, 22, 7, 0x0, 0x0 },
+	{ "e_weight", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_dev_sp_state_reg[] = {
+	{ "dev_sp_state", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_dev_crs_reg[] = {
+	{ "dev_crs", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_congest_token_disable_31_0_reg[] = {
+	{ "congest_token_disable_31_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_congest_token_disable_63_32_reg[] = {
+	{ "congest_token_disable_63_32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_interval_en_cfg_reg[] = {
+	{ "crdt_interval_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_q_token_staue_cfg_reg[] = {
+	{ "test_token_q_id", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_q_token_dist_cnt_reg[] = {
+	{ "q_token_dist_counter", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_q_token_dec_cnt_reg[] = {
+	{ "q_token_dec_counter", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_pp_weight_ram_reg[] = {
+	{ "pp_c_weight", DPP_FIELD_FLAG_RW, 25, 26, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_pp_cbs_shape_en_ram_reg[] = {
+	{ "pp_cbs", DPP_FIELD_FLAG_RW, 17, 17, 0x0, 0x0 },
+	{ "pp_c_shap_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_pp_next_pc_q_state_ram_reg[] = {
+	{ "pp_next_pc", DPP_FIELD_FLAG_RO, 24, 6, 0x0, 0x0 },
+	{ "pp_token_num", DPP_FIELD_FLAG_RO, 18, 18, 0x20000, 0x0 },
+	{ "pp_q_state", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_dev_interval_reg[] = {
+	{ "dev_interval", DPP_FIELD_FLAG_RW, 21, 22, 0xf, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_dev_wfq_cnt_reg[] = {
+	{ "dev_wfq_cnt", DPP_FIELD_FLAG_RO, 6, 7, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_dev_wfq_state_reg[] = {
+	{ "dev_wfq_state", DPP_FIELD_FLAG_RO, 6, 7, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_dev_active_head_ptr_reg[] = {
+	{ "dev_active_head_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_dev_active_tail_ptr_reg[] = {
+	{ "dev_active_tail_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_dev_unactive_head_ptr_reg[] = {
+	{ "dev_unactive_head_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_dev_unactive_tail_ptr_reg[] = {
+	{ "dev_unactive_tail_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_pp_weight_reg[] = {
+	{ "pp_weight", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_pp_que_state_reg[] = {
+	{ "pp_enque_flag", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0 },
+	{ "pp_cir", DPP_FIELD_FLAG_RO, 15, 2, 0x2, 0x0 },
+	{ "pp_congest_cir", DPP_FIELD_FLAG_RO, 13, 2, 0x0, 0x0 },
+	{ "pp_crs", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0 },
+	{ "dev_sp", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_pp_next_ptr_reg[] = {
+	{ "pp_next_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_pp_cfg_reg[] = {
+	{ "pp_cfg", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_pp_up_ptr_reg[] = {
+	{ "pp_up_ptr", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_credit_drop_num_reg[] = {
+	{ "credit_drop_num", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_se_id_lv0_reg[] = {
+	{ "se_id_out_lv0", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_se_id_lv1_reg[] = {
+	{ "se_id_out_lv1", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_se_id_lv2_reg[] = {
+	{ "se_id_out_lv2", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_se_id_lv3_reg[] = {
+	{ "se_id_out_lv3", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_se_id_lv4_reg[] = {
+	{ "se_id_out_lv4", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_que_id_reg[] = {
+	{ "que_id_out", DPP_FIELD_FLAG_RO, 17, 18, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_se_info_lv0_reg[] = {
+	{ "se_shape_lv0", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0 },
+	{ "se_ins_out_lv0", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0 },
+	{ "se_state_out_lv0", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0 },
+	{ "se_new_state_out_lv0", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_se_info_lv1_reg[] = {
+	{ "se_shape_lv1", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0 },
+	{ "se_ins_out_lv1", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0 },
+	{ "se_state_out_lv1", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0 },
+	{ "se_new_state_out_lv1", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_se_info_lv2_reg[] = {
+	{ "se_shape_lv2", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0 },
+	{ "se_ins_out_lv2", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0 },
+	{ "se_state_out_lv2", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0 },
+	{ "se_new_state_out_lv2", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_se_info_lv3_reg[] = {
+	{ "se_shape_lv3", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0 },
+	{ "se_ins_out_lv3", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0 },
+	{ "se_state_out_lv3", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0 },
+	{ "se_new_state_out_lv3", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_se_info_lv4_reg[] = {
+	{ "se_shape_lv4", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0 },
+	{ "se_ins_out_lv4", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0 },
+	{ "se_state_out_lv4", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0 },
+	{ "se_new_state_out_lv4", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_que_state_reg[] = {
+	{ "que_state_out", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_eir_off_in_advance_reg[] = {
+	{ "eir_crs_filter", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_double_level_shap_prevent_reg[] = {
+	{ "double_level_shap_prevent", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_add_store_cycle_reg[] = {
+	{ "add_store_cycle", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_tflag2_wr_flag_sum_reg[] = {
+	{ "tflag2_wr_flag_sum", DPP_FIELD_FLAG_RO, 4, 5, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_flowque_para_tbl_reg[] = {
+	{ "flowque_link", DPP_FIELD_FLAG_RW, 30, 15, 0x7fff, 0x0 },
+	{ "flowque_w", DPP_FIELD_FLAG_RW, 14, 11, 0x0, 0x0 },
+	{ "flowque_pri", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_se_para_tbl_reg[] = {
+	{ "se_insw", DPP_FIELD_FLAG_RW, 33, 1, 0x0, 0x0 },
+	{ "se_link", DPP_FIELD_FLAG_RW, 30, 15, 0x7fff, 0x0 },
+	{ "cp_token_en", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0 },
+	{ "se_w", DPP_FIELD_FLAG_RW, 14, 11, 0x0, 0x0 },
+	{ "se_pri", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_flowque_ins_tbl_reg[] = {
+	{ "flowque_ins", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_se_ins_tbl_reg[] = {
+	{ "se_ins_flag", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "se_ins_priority", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_eir_crs_filter_tbl_reg[] = {
+	{ "eir_crs_filter", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_cfg_done_reg[] = {
+	{ "qcfg_qlist_cfg_done", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qsch_credit_value_reg[] = {
+	{ "qcfg_qsch_credit_value", DPP_FIELD_FLAG_RW, 13, 14, 0x8fc, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qsch_crbal_init_value_reg[] = {
+	{ "qcfg_qsch_crbal_init_value", DPP_FIELD_FLAG_RW, 16, 17, 0xff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qsch_crbal_init_mask_reg[] = {
+	{ "qcfg_qsch_crbal_init_mask", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cmdsch_rd_cmd_aful_th_reg[] = {
+	{ "cmdsch_rd_cmd_aful_th", DPP_FIELD_FLAG_RW, 9, 10, 0x80, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_port_fc_interval_reg[] = {
+	{ "cfg_port_fc_interval", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_csch_aged_cfg_reg[] = {
+	{ "qcfg_csch_aged_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_csch_aged_scan_time_reg[] = {
+	{ "qcfg_csch_aged_scan_time", DPP_FIELD_FLAG_RW, 31, 32, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qmu_qlist_state_query_reg[] = {
+	{ "pkt_age_req_fifo_afull", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0 },
+	{ "rd_release_fwft_afull", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0 },
+	{ "drop_imem_fwft_afull", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0 },
+	{ "pkt_age_req_fifo_empty", DPP_FIELD_FLAG_RO, 24, 1, 0x1, 0x0 },
+	{ "rd_release_fwft_empty", DPP_FIELD_FLAG_RO, 23, 1, 0x1, 0x0 },
+	{ "drop_imem_fwft_empty", DPP_FIELD_FLAG_RO, 22, 1, 0x1, 0x0 },
+	{ "mmu_qmu_sop_rd_rdy", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0 },
+	{ "big_fifo_empty", DPP_FIELD_FLAG_RO, 20, 1, 0x1, 0x0 },
+	{ "qmu_mmu_rd_release_rdy", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0 },
+	{ "xsw_qmu_crs_rdy", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0 },
+	{ "mmu_qmu_rdy", DPP_FIELD_FLAG_RO, 17, 10, 0x0, 0x0 },
+	{ "mmu_ql_wr_rdy", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "mmu_ql_rd_rdy", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "csw_ql_rdy", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "ql_init_done", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "free_addr_ready", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "bank_group_afull", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "pds_fwft_empty", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0 },
+	{ "enq_rpt_fwft_afull", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qsch_crbal_drop_en_reg[] = {
+	{ "cfgmt_qsch_all_crbal_drop_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "cfgmt_qsch_crbal_drop_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_wlist_qnum_fifo_aful_th_reg[] = {
+	{ "cfgmt_wlist_qnum_fifo_aful_th", DPP_FIELD_FLAG_RW, 3, 4, 0x4, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_csw_pkt_blk_mode_reg[] = {
+	{ "qcfg_csw_pkt_blk_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_ram_init_cancel_reg[] = {
+	{ "qcfg_qlist_ram_init_cancel", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qsch_crbal_transfer_mode_reg[] = {
+	{ "qcfg_qsch_crbal_transfer_mode", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0 },
+	{ "qcfg_qsch_crbal_transfer_value", DPP_FIELD_FLAG_RW, 15, 16, 0x3e8, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_qclr_interval_reg[] = {
+	{ "qcfg_qlist_qclr_interval", DPP_FIELD_FLAG_RW, 31, 32, 0x400, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qsch_qclr_rate_reg[] = {
+	{ "qcfg_qsch_qclr_rate", DPP_FIELD_FLAG_RW, 31, 32, 0xff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_ddr_random_reg[] = {
+	{ "qcfg_qlist_ddr_random", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qlist_pds_fifo_afull_th_reg[] = {
+	{ "cfgmt_qlist_pds_fifo_afull_th", DPP_FIELD_FLAG_RW, 5, 6, 0xc, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_sop_cmd_fifo_afull_th_reg[] = {
+	{ "cfgmt_sop_cmd_fifo_afull_th", DPP_FIELD_FLAG_RW, 7, 8, 0x78, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_non_sop_cmd_fifo_afull_th_reg[] = {
+	{ "cfgmt_non_sop_cmd_fifo_afull_th", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_mmu_data_fifo_afull_th_reg[] = {
+	{ "cfgmt_mmu_data_fifo_afull_th", DPP_FIELD_FLAG_RW, 9, 10, 0xf0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_bank_ept_th_reg[] = {
+	{ "qcfg_qlist_bank_ept_th", DPP_FIELD_FLAG_RW, 17, 18, 0x3, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_random_bypass_en_reg[] = {
+	{ "random_bypass_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_crs_spd_bypass_reg[] = {
+	{ "cfgmt_crs_spd_bypass", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_crs_interval_reg[] = {
+	{ "cfgmt_crs_interval", DPP_FIELD_FLAG_RW, 31, 32, 0x8, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_auto_credit_control_en_reg[] = {
+	{ "cfg_qsch_auto_credit_control_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_autocrfrstque_reg[] = {
+	{ "cfg_qsch_autocrfrstque", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_autocrlastque_reg[] = {
+	{ "cfg_qsch_autocrlastque", DPP_FIELD_FLAG_RW, 15, 16, 0x3ff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_autocreditrate_reg[] = {
+	{ "cfg_qsch_autocreditrate", DPP_FIELD_FLAG_RW, 19, 20, 0x20, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_scanfrstque_reg[] = {
+	{ "cfg_qsch_scanfrstque", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_scanlastque_reg[] = {
+	{ "cfg_qsch_scanlastque", DPP_FIELD_FLAG_RW, 13, 14, 0x3ff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_scanrate_reg[] = {
+	{ "cfg_qsch_scanrate", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_scan_en_reg[] = {
+	{ "cfg_qsch_scan_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qsch_rd_credit_fifo_rate_reg[] = {
+	{ "cfgmt_qsch_rd_credit_fifo_rate", DPP_FIELD_FLAG_RW, 23, 24, 0xa, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_bdep_reg[] = {
+	{ "qcfg_qlist_bdep", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_bhead_reg[] = {
+	{ "bank_vld", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0 },
+	{ "qcfg_qlist_bhead", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_btail_reg[] = {
+	{ "qcfg_qlist_btail", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qsch_shap_param_reg[] = {
+	{ "qcfg_qsch_shap_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "qcfg_qsch_shap_param1", DPP_FIELD_FLAG_RW, 23, 12, 0x0, 0x0 },
+	{ "qcfg_qsch_shap_param2", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qsch_shap_token_reg[] = {
+	{ "qcfg_qsch_shap_token", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qsch_shap_offset_reg[] = {
+	{ "qcfg_qsch_shap_offset", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_eir_th_reg[] = {
+	{ "qcfg_qsch_crs_eir_th", DPP_FIELD_FLAG_RW, 18, 19, 0x80, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_th1_reg[] = {
+	{ "qcfg_qsch_crs_th1", DPP_FIELD_FLAG_RW, 31, 32, 0x57584c4c, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_th2_reg[] = {
+	{ "qcfg_qsch_crs_th2", DPP_FIELD_FLAG_RW, 31, 32, 0x200, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_csch_congest_th_reg[] = {
+	{ "qcfg_csch_congest_th", DPP_FIELD_FLAG_RW, 13, 14, 0xc8, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_csch_sp_fc_th_reg[] = {
+	{ "qcfg_csch_sp_fc_th", DPP_FIELD_FLAG_RW, 13, 14, 0x12c, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_csw_shap_parameter_reg[] = {
+	{ "qcfg_csw_shap_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "qcfg_csw_shap_parameter", DPP_FIELD_FLAG_RW, 23, 24, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_rd_release_aful_th_reg[] = {
+	{ "cfgmt_rd_release_aful_th", DPP_FIELD_FLAG_RW, 8, 9, 0x80, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_drop_imem_release_fifo_aful_th_reg[] = {
+	{ "cfgmt_drop_imem_release_fifo_aful_th", DPP_FIELD_FLAG_RW, 8, 9, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_nnh_rd_buf_aful_th_reg[] = {
+	{ "cfgmt_nnh_rd_buf_aful_th", DPP_FIELD_FLAG_RW, 5, 6, 0xa, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_pid_use_inall_reg[] = {
+	{ "cfgmt_nod_rd_buf_0_aful_th", DPP_FIELD_FLAG_RW, 4, 5, 0x3, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_pid_round_th_reg[] = {
+	{ "cfgmt_nod_rd_buf_1_aful_th", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_credit_fifo_afull_th_reg[] = {
+	{ "cfgmt_credit_fifo_afull_th", DPP_FIELD_FLAG_RW, 5, 6, 0xa, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_scan_fifo_afull_th_reg[] = {
+	{ "cfgmt_scan_fifo_afull_th", DPP_FIELD_FLAG_RW, 5, 6, 0xa, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_small_fifo_aful_th_reg[] = {
+	{ "cfgmt_small_fifo_aful_th", DPP_FIELD_FLAG_RW, 5, 6, 0x9, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_free_addr_fifo_aful_th_reg[] = {
+	{ "cfgmt_free_addr_fifo_aful_th", DPP_FIELD_FLAG_RW, 5, 6, 0x16, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_enq_rpt_fifo_aful_th_reg[] = {
+	{ "cfgmt_enq_rpt_fifo_aful_th", DPP_FIELD_FLAG_RW, 9, 10, 0x3e8, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_csw_shap_token_depth_reg[] = {
+	{ "qcfg_csw_shap_token_depth", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_csw_shap_offset_value_reg[] = {
+	{ "qcfg_csw_shap_offset_value", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_csw_fc_offset_value_reg[] = {
+	{ "qcfg_csw_fc_offset_value", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_init_done_state_reg[] = {
+	{ "csch_qcfg_init_done", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "qsch_qcfg_init_done", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "qlist_qcfg_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "qcsr_ram_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csw_qcfg_port_shap_rdy_0_reg[] = {
+	{ "csw_qcfg_port_shap_rdy_0", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csw_qcfg_port_shap_rdy_1_reg[] = {
+	{ "csw_qcfg_port_shap_rdy_1", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qlist_cfgmt_ram_init_done_reg[] = {
+	{ "qlist_qcfg_qds_ram_init_done", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "qlist_qcfg_chk_ram_init_done", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "qlist_qcfg_ept_ram_init_done", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "qlist_qcfg_cti_ram_init_done", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "qlist_qcfg_cto_ram_init_done", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "qlist_qcfg_bcnt_ram_init_done", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "qlist_qcfg_biu_ram_init_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "qlist_qcfg_baram_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qlist_cfgmt_ram_ecc_err_reg[] = {
+	{ "qds_ram_parity_err", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "qcsr_qnum_fifo_parity_err", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "sa_id_ram_parity_err", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "enq_rpt_fifo_parity_err", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "bcnts_parity_err", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "baram_parity_err_a", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "baram_parity_err_b", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "bcntm_ram_parity_err", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "biu_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "chk_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "cmd_sch_cmd_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "cmd_sch_list_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "cmd_sch_hp_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "cmd_sch_tp_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "cmd_sch_enq_active_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0,
+	  0x0 },
+	{ "cmd_sch_deq_active_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0,
+	  0x0 },
+	{ "cmd_sch_empty_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "cmd_sch_eop_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "cmd_sch_blkcnt_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "biu_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "chk_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "cmd_sch_cmd_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "cmd_sch_list_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "cmd_sch_hp_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "cmd_sch_tp_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "cmd_sch_enq_active_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0,
+	  0x0 },
+	{ "cmd_sch_deq_active_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0,
+	  0x0 },
+	{ "cmd_sch_empty_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "cmd_sch_eop_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "cmd_sch_blkcnt_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qlist_cfgmt_ram_slot_err_reg[] = {
+	{ "qds_ram_enq_rd_slot_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "qds_ram_deq_rd_slot_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "qds_ram_enq_wr_slot_err", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "qds_ram_deq_wr_slot_err", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "chk_ram_enq_rd_slot_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "chk_ram_deq_rd_slot_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "chk_ram_enq_wr_slot_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "chk_ram_deq_wr_slot_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ept_ram_enq_rd_slot_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ept_ram_deq_rd_slot_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ept_ram_enq_wr_slot_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ept_ram_deq_wr_slot_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "cti_ram_enq_rd_slot_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "cti_ram_deq_rd_slot_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "cti_ram_enq_wr_slot_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "cti_ram_deq_wr_slot_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "cto_ram_enq_rd_slot_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "cto_ram_deq_rd_slot_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "cto_ram_enq_wr_slot_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "cto_ram_deq_wr_slot_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qsch_cfgmt_ram_ecc_reg[] = {
+	{ "crbal_rama_parity_error", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "crbal_ramb_parity_error", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "crs_ram_parity_error", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "wlist_flag_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "wlist_next_single_ecc_err", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "wlist_wactive_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "wlist_ractive_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "wlist_tp1_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "wlist_tp2_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "wlist_empty1_ram_single_ecc_err_a", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "wlist_empty1_ram_single_ecc_err_b", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "wlist_empty2_ram_single_ecc_err_a", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "wlist_empty2_ram_single_ecc_err_b", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "wlist_hp_ram_single_ecc_err_a", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "wlist_hp_ram_single_ecc_err_b", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "wlist_flag_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "wlist_next_double_ecc_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "wlist_wactive_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "wlist_ractive_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "wlist_tp1_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "wlist_tp2_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "wlist_empty1_ram_double_ecc_err_a", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "wlist_empty1_ram_double_ecc_err_b", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "wlist_empty2_ram_double_ecc_err_a", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "wlist_empty2_ram_double_ecc_err_b", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "wlist_hp_ram_double_ecc_err_a", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "wlist_hp_ram_double_ecc_err_b", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qlist_cfgmt_fifo_state_reg[] = {
+	{ "pkt_age_req_fifo_overflow", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "pkt_age_req_fifo_underflow", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "qcsr_big_fifo_ovfl", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "qcsr_small_fifo_overflow", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "enq_rpt_fifo_overflow", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "enq_rpt_fifo_underflow", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "pds_fwft_overflow", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "pds_fwft_underflow", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "free_addr_fifo_overflow", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "free_addr_fifo_underflow", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "rd_release_fwft_overflow", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "rd_release_fwft_underflow", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "pid_free_list_overflow", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "pid_free_list_underflow", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "pid_prp_list_overflow", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "pid_prp_list_underflow", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "pid_rdy_list_overflow", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "pid_rdy_list_underflow", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "drop_imem_release_fwft_overflow", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "drop_imem_release_fwft_underflow", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "nnh_rd_buf_fifo_overflow", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "nnh_rd_buf_fifo_underflow", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "nod_rd_buf_0_fifo_overflow", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "nod_rd_buf_0_fifo_underflow", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "nod_rd_buf_1_fifo_overflow", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "nod_rd_buf_1_fifo_underflow", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qlist_qcfg_clr_done_reg[] = {
+	{ "qlist_qcfg_clr_done", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_int_mask1_reg[] = {
+	{ "qmu_int_mask1", DPP_FIELD_FLAG_RW, 29, 30, 0x3fffffff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_int_mask2_reg[] = {
+	{ "qmu_int_mask2", DPP_FIELD_FLAG_RW, 19, 20, 0xfffff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_int_mask3_reg[] = {
+	{ "qmu_int_mask3", DPP_FIELD_FLAG_RW, 26, 27, 0x7ffffff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_int_mask4_reg[] = {
+	{ "qmu_int_mask4", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_int_mask5_reg[] = {
+	{ "qmu_int_mask5", DPP_FIELD_FLAG_RW, 30, 31, 0x7fffffff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_int_mask6_reg[] = {
+	{ "qmu_int_mask6", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cmd_sch_cfgmt_fifo_state_reg[] = {
+	{ "nsop_fifo_parity_err", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "cmdsch_rd_cmd_fifo_parity_err", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "sop_fifo_afull", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "sop_fifo_empty", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "sop_fifo_overflow", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "sop_fifo_underflow", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "mmu_data_fifo_afull", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "mmu_data_fifo_empty", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "mmudat_fifo_overflow", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "mmudat_fifo_underflow", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "non_sop_fifo_afull", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "non_sop_fifo_empty", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "nsop_fifo_overflow", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "nsop_fifo_underflow", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "cmdsch_rd_cmd_fifo_afull", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "cmdsch_rd_cmd_fifo_empty", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "cmdsch_rd_cmd_fifo_overflow", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "cmdsch_rd_cmd_fifo_underflow", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "wlist_qnum_fifo_overflow", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "wlist_qnum_fifo_underflow", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "qsch_scan_fifo_overflow", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "qsch_scan_fifo_underflow", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "qsch_credit_fifo_overflow", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "qsch_credit_fifo_underflow", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "qsch_credit_fifo2_overflow", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "qsch_credit_fifo2_underflow", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qlist_r_bcnt_reg[] = {
+	{ "qlist_r_bcnt", DPP_FIELD_FLAG_RO, 21, 22, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qsch_rw_crbal_reg[] = {
+	{ "qsch_rw_crbal", DPP_FIELD_FLAG_RW, 16, 17, 0xff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qsch_rw_crs_reg[] = {
+	{ "qsch_rw_crs", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qsch_r_wlist_empty_reg[] = {
+	{ "qsch_r_wlist_empty", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_baram_rd_reg[] = {
+	{ "qcfg_qlist_baram_rd", DPP_FIELD_FLAG_RO, 6, 7, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qsch_crbal_fb_rw_reg[] = {
+	{ "qcfg_qlist_crbal_fb_rw", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp0_bank_reg[] = {
+	{ "qcfg_qlist_grp0_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp1_bank_reg[] = {
+	{ "qcfg_qlist_grp1_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp2_bank_reg[] = {
+	{ "qcfg_qlist_grp2_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp3_bank_reg[] = {
+	{ "qcfg_qlist_grp3_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp4_bank_reg[] = {
+	{ "qcfg_qlist_grp4_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp5_bank_reg[] = {
+	{ "qcfg_qlist_grp5_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp6_bank_reg[] = {
+	{ "qcfg_qlist_grp6_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp7_bank_reg[] = {
+	{ "qcfg_qlist_grp7_bank_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_grp_reg[] = {
+	{ "qcfg_qlist_grp_wr", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_active_to_bank_cfg_reg[] = {
+	{ "cfgmt_active_to_bank_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x1 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_ddr_in_mmu_cfg_reg[] = {
+	{ "cfgmt_ddr_in_mmu_cfg", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x1 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_ddr_in_qmu_cfg_reg[] = {
+	{ "cfgmt_ddr_in_qmu_cfg", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_bank_to_mmu_cfg_reg[] = {
+	{ "cfgmt_bank_in_mmu_cfg", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x1 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_bank_to_qmu_cfg_reg[] = {
+	{ "cfgmt_bank_in_qmu_cfg", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x1 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_grp_ram_n_clr_thd_reg[] = {
+	{ "cfgmt_grp_ram_n_clr_thd", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_age_pkt_num_reg[] = {
+	{ "cfgmt_age_pkt_num", DPP_FIELD_FLAG_RW, 3, 4, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_age_multi_interval_reg[] = {
+	{ "cfgmt_age_multi_interval", DPP_FIELD_FLAG_RW, 15, 16, 0xff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pkt_age_en_reg[] = {
+	{ "cfgmt_qmu_pkt_age_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pkt_age_interval_reg[] = {
+	{ "cfgmt_qmu_pkt_age_interval", DPP_FIELD_FLAG_RW, 31, 32, 0xff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pkt_age_start_end_reg[] = {
+	{ "cfgmt_qmu_pkt_age_end", DPP_FIELD_FLAG_RW, 31, 16, 0x23ff, 0x0 },
+	{ "cfgmt_qmu_pkt_age_start", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_pkt_age_req_aful_th_reg[] = {
+	{ "cfgmt_pkt_age_req_aful_th", DPP_FIELD_FLAG_RW, 5, 6, 0xa, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_pkt_age_step_interval_reg[] = {
+	{ "cfgmt_pkt_age_step_interval", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_age_mode_reg[] = {
+	{ "cfgmt_qmu_imem_age_en", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0 },
+	{ "cfgmt_qmu_imem_age_qlen_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "cfgmt_qmu_imem_age_time_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_qlen_age_interval_reg[] = {
+	{ "cfgmt_qmu_imem_qlen_age_interval", DPP_FIELD_FLAG_RW, 15, 16, 0xff,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_time_age_interval_reg[] = {
+	{ "cfgmt_qmu_imem_time_age_interval", DPP_FIELD_FLAG_RW, 31, 32, 0xff,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_qlen_age_thd_reg[] = {
+	{ "cfgmt_qmu_imem_qlen_age_thd", DPP_FIELD_FLAG_RW, 13, 14, 0x1000, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_imem_age_step_interval_reg[] = {
+	{ "cfgmt_imem_age_step_interval", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_ecc_bypass_read_reg[] = {
+	{ "cfgmt_qmu_ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_resp_stat_fc_en_reg[] = {
+	{ "cfgmt_qmu_resp_stat_fc_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_bank_xoff_pds_mode_reg[] = {
+	{ "cfgmt_qmu_bank_xoff_pds_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_stat_offset_reg[] = {
+	{ "cfgmt_qmu_stat_offset", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_fc_cnt_mode_reg[] = {
+	{ "fc_cnt_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_mmu_qmu_wr_fc_cnt_reg[] = {
+	{ "mmu_qmu_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_mmu_qmu_rd_fc_cnt_reg[] = {
+	{ "mmu_qmu_rd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_cgavd_fc_cnt_reg[] = {
+	{ "qmu_cgavd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cgavd_qmu_pkt_cnt_reg[] = {
+	{ "cgavd_qmu_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cgavd_qmu_pktlen_all_reg[] = {
+	{ "cgavd_qmu_pktlen_all", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_observe_portfc_spec_reg[] = {
+	{ "observe_portfc_spec", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_lif_portfc_count_reg[] = {
+	{ "spec_lif_portfc_count", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pfc_en_reg[] = {
+	{ "cfgmt_qmu_pfc_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pfc_mask_1_reg[] = {
+	{ "cfgmt_qmu_pfc_mask_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_pfc_mask_2_reg[] = {
+	{ "cfgmt_qmu_pfc_mask_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_int_repeat_reg[] = {
+	{ "int_repeat", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_up_size_reg[] = {
+	{ "dma_up_size", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_soc_wr_time_out_thresh_reg[] = {
+	{ "soc_wr_time_out_thresh", DPP_FIELD_FLAG_RW, 31, 32, 0xfa0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_cfg_shap_param_reg[] = {
+	{ "shap_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "shap_rate", DPP_FIELD_FLAG_RW, 30, 31, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_cfg_shap_token_reg[] = {
+	{ "cfg_shap_plen_offset", DPP_FIELD_FLAG_RW, 31, 8, 0x00, 0x0 },
+	{ "cfg_shap_token", DPP_FIELD_FLAG_RW, 16, 17, 0xf0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_idle_ptr_fifo_aful_th_reg[] = {
+	{ "idle_ptr3_fifo_aful_th", DPP_FIELD_FLAG_RW, 31, 8, 0x5a, 0x0 },
+	{ "idle_ptr2_fifo_aful_th", DPP_FIELD_FLAG_RW, 23, 8, 0x5a, 0x0 },
+	{ "idle_ptr1_fifo_aful_th", DPP_FIELD_FLAG_RW, 15, 8, 0x5a, 0x0 },
+	{ "idle_ptr0_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0x5a, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos_port_cfg_reg[] = {
+	{ "cos3_port_cfg", DPP_FIELD_FLAG_RW, 31, 8, 0x3f, 0x0 },
+	{ "cos2_port_cfg", DPP_FIELD_FLAG_RW, 23, 8, 0x3e, 0x0 },
+	{ "cos1_port_cfg", DPP_FIELD_FLAG_RW, 15, 8, 0x3d, 0x0 },
+	{ "cos0_port_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x3c, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_ind_status_reg[] = {
+	{ "ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_ind_cmd_reg[] = {
+	{ "ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0 },
+	{ "ind_mem_id", DPP_FIELD_FLAG_RW, 22, 3, 0x0, 0x0 },
+	{ "ind_mem_addr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_ind_data0_reg[] = {
+	{ "ind_dat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_ind_data1_reg[] = {
+	{ "ind_dat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_ind_data2_reg[] = {
+	{ "ind_dat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_ind_data3_reg[] = {
+	{ "ind_dat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_ind_data4_reg[] = {
+	{ "ind_dat4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_ind_data5_reg[] = {
+	{ "ind_dat5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_ind_data6_reg[] = {
+	{ "ind_dat6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_ind_data7_reg[] = {
+	{ "ind_dat7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_tcam_0_cmd_reg[] = {
+	{ "cfg_vben", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "cfg_vbi", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "cfg_t_strwc", DPP_FIELD_FLAG_RW, 22, 2, 0x1, 0x0 },
+	{ "tcam0_sm", DPP_FIELD_FLAG_RW, 20, 6, 0x0, 0x0 },
+	{ "tcam0_smen", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0 },
+	{ "tcam0_rm", DPP_FIELD_FLAG_RW, 13, 2, 0x2, 0x0 },
+	{ "tcam0_rmen", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0 },
+	{ "tcam0_enable", DPP_FIELD_FLAG_RW, 10, 1, 0x0, 0x0 },
+	{ "tcam0_flush", DPP_FIELD_FLAG_WO, 9, 1, 0x0, 0x0 },
+	{ "tcam0_unload", DPP_FIELD_FLAG_WO, 8, 1, 0x0, 0x0 },
+	{ "tcam0_unload_addr", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_tcam_1_cmd_reg[] = {
+	{ "tcam1_sm", DPP_FIELD_FLAG_RW, 20, 6, 0x0, 0x0 },
+	{ "tcam1_smen", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0 },
+	{ "tcam1_rm", DPP_FIELD_FLAG_RW, 13, 2, 0x2, 0x0 },
+	{ "tcam1_rmen", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0 },
+	{ "tcam1_enable", DPP_FIELD_FLAG_RW, 10, 1, 0x0, 0x0 },
+	{ "tcam1_flush", DPP_FIELD_FLAG_WO, 9, 1, 0x0, 0x0 },
+	{ "tcam1_unload", DPP_FIELD_FLAG_WO, 8, 1, 0x0, 0x0 },
+	{ "tcam1_unload_addr", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_port_en_0_reg[] = {
+	{ "cfg_isch_port_en_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_port_en_1_reg[] = {
+	{ "cfg_isch_port_en_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_port_en_2_reg[] = {
+	{ "cfg_isch_port_en_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_port_en_3_reg[] = {
+	{ "cfg_port_change_en_0", DPP_FIELD_FLAG_RW, 26, 1, 0x0, 0x0 },
+	{ "cfg_port_change_en_1", DPP_FIELD_FLAG_RW, 25, 1, 0x0, 0x0 },
+	{ "cfg_isch_port_en_3", DPP_FIELD_FLAG_RW, 22, 23, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_0_reg[] = {
+	{ "cfg_port_l2_offset_mode_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_1_reg[] = {
+	{ "cfg_port_l2_offset_mode_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_2_reg[] = {
+	{ "cfg_port_l2_offset_mode_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_3_reg[] = {
+	{ "cfg_port_l2_offset_mode_3", DPP_FIELD_FLAG_RW, 22, 23, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_0_reg[] = {
+	{ "cfg_isch_fc_mode_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_1_reg[] = {
+	{ "cfg_isch_fc_mode_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_2_reg[] = {
+	{ "cfg_isch_fc_mode_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_3_reg[] = {
+	{ "cfg_isch_fc_mode_3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_4_reg[] = {
+	{ "cfg_isch_fc_mode_4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_5_reg[] = {
+	{ "cfg_isch_fc_mode_5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_6_reg[] = {
+	{ "cfg_isch_fc_mode_6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_port_fc_mode_7_reg[] = {
+	{ "cfg_pfu_aging_en", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "cfg_isch_aging_en", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0 },
+	{ "cfg_isch_fc_mode_7", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_cfg_isch_aging_th_reg[] = {
+	{ "cfg_pfu_delay_cycle", DPP_FIELD_FLAG_RW, 31, 16, 0x8000, 0x0 },
+	{ "cfg_isch_aging_th", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_isch_fifo_th_0_reg[] = {
+	{ "cfg_sch_fifo3_fc_th", DPP_FIELD_FLAG_RW, 29, 6, 0x30, 0x0 },
+	{ "cfg_sch_fifo2_fc_th", DPP_FIELD_FLAG_RW, 21, 6, 0x30, 0x0 },
+	{ "cfg_sch_fifo1_fc_th", DPP_FIELD_FLAG_RW, 13, 6, 0x30, 0x0 },
+	{ "cfg_sch_fifo0_fc_th", DPP_FIELD_FLAG_RW, 5, 6, 0x30, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_isch_cfg_1_reg[] = {
+	{ "cfg_parser_max_len_en", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "cfg_parser_max_len", DPP_FIELD_FLAG_RW, 30, 15, 0x3e80, 0x0 },
+	{ "cfg_parser_min_len_en", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0 },
+	{ "cfg_parser_min_len", DPP_FIELD_FLAG_RW, 14, 7, 0x3c, 0x0 },
+	{ "sp_sch_sel", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_tcam_0_vld_reg[] = {
+	{ "cfg_tcam0_vld", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_tcam_1_vld_reg[] = {
+	{ "cfg_tcam1_vld", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_cpu_port_en_mask_reg[] = {
+	{ "cpu_port_en_mask", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg[] = {
+	{ "pktrx_glbal_cfg_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_1_reg[] = {
+	{ "pktrx_glbal_cfg_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_2_reg[] = {
+	{ "pktrx_glbal_cfg_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_3_reg[] = {
+	{ "pktrx_glbal_cfg_3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_nppu_start_reg[] = {
+	{ "nppu_start", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_stat_ind_status_reg[] = {
+	{ "ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_stat_ind_cmd_reg[] = {
+	{ "ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0 },
+	{ "ind_mem_id", DPP_FIELD_FLAG_RW, 22, 3, 0x0, 0x0 },
+	{ "ind_mem_addr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_stat_ind_data0_reg[] = {
+	{ "ind_dat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_idma_cfg_debug_cnt_ovfl_mode_reg[] = {
+	{ "debug_cnt_ovfl_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_idma_stat_ind_status_reg[] = {
+	{ "ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_idma_stat_ind_cmd_reg[] = {
+	{ "ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0 },
+	{ "ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0 },
+	{ "ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_idma_stat_ind_data0_reg[] = {
+	{ "ind_data0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_ind_status_reg[] = {
+	{ "ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_ind_cmd_reg[] = {
+	{ "ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0 },
+	{ "ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0 },
+	{ "ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_ind_data0_reg[] = {
+	{ "ind_data0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_ind_data1_reg[] = {
+	{ "ind_data1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_ind_data2_reg[] = {
+	{ "ind_data2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_ind_data3_reg[] = {
+	{ "ind_data3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_ind_data4_reg[] = {
+	{ "ind_data4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_ind_data5_reg[] = {
+	{ "ind_data5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_ind_data6_reg[] = {
+	{ "ind_data6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_ind_data7_reg[] = {
+	{ "ind_data7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_idma_public_th_reg[] = {
+	{ "idma_public_th", DPP_FIELD_FLAG_RW, 14, 15, 0x400, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_lif_public_th_reg[] = {
+	{ "lif_public_th", DPP_FIELD_FLAG_RW, 14, 15, 0x400, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_idma_total_th_reg[] = {
+	{ "idma_total_th", DPP_FIELD_FLAG_RW, 14, 15, 0x3ffc, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_lif_total_th_reg[] = {
+	{ "lif_total_th", DPP_FIELD_FLAG_RW, 14, 15, 0x3fa2, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_mc_total_th_reg[] = {
+	{ "mc_total_th", DPP_FIELD_FLAG_RW, 14, 15, 0x400, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_mc_cos10_th_reg[] = {
+	{ "mc_cos1_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "mc_cos0_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0 },
+	{ "mc_cos1_th", DPP_FIELD_FLAG_RW, 29, 15, 0x80, 0x0 },
+	{ "mc_cos0_th", DPP_FIELD_FLAG_RW, 14, 15, 0x80, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_mc_cos32_th_reg[] = {
+	{ "mc_cos3_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "mc_cos2_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0 },
+	{ "mc_cos3_th", DPP_FIELD_FLAG_RW, 29, 15, 0x80, 0x0 },
+	{ "mc_cos2_th", DPP_FIELD_FLAG_RW, 14, 15, 0x80, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_mc_cos54_th_reg[] = {
+	{ "mc_cos5_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "mc_cos4_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0 },
+	{ "mc_cos5_th", DPP_FIELD_FLAG_RW, 29, 15, 0x80, 0x0 },
+	{ "mc_cos4_th", DPP_FIELD_FLAG_RW, 14, 15, 0x80, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_mc_cos76_th_reg[] = {
+	{ "mc_cos7_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "mc_cos6_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0 },
+	{ "mc_cos7_th", DPP_FIELD_FLAG_RW, 29, 15, 0x80, 0x0 },
+	{ "mc_cos6_th", DPP_FIELD_FLAG_RW, 14, 15, 0x80, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_debug_cnt_ovfl_mode_reg[] = {
+	{ "debug_cnt_ovfl_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_se_key_aful_negate_cfg_reg[] = {
+	{ "se_key_aful_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_sa_flag_reg[] = {
+	{ "sa_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_ind_data_reg[] = {
+	{ "ind_data", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_ind_status_reg[] = {
+	{ "ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_ind_cmd_reg[] = {
+	{ "ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0 },
+	{ "ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0 },
+	{ "ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_total_cnt_reg[] = {
+	{ "total_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_idma_pub_cnt_reg[] = {
+	{ "idma_pub_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_lif_pub_cnt_reg[] = {
+	{ "lif_pub_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_mc_total_cnt_reg[] = {
+	{ "mc_total_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_pbu_thram_init_done_reg[] = {
+	{ "pbu_thram_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_ifb_fptr_init_done_reg[] = {
+	{ "ifb_fptr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_weight_normal_uc_reg[] = {
+	{ "weight_normal_uc", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_fabric_or_saip_reg[] = {
+	{ "fabric_or_saip", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_ind_status_reg[] = {
+	{ "ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_ind_cmd_reg[] = {
+	{ "ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0 },
+	{ "ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0 },
+	{ "ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_ind_dat0_reg[] = {
+	{ "ind_dat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_ind_access_done_reg[] = {
+	{ "ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_ind_command_reg[] = {
+	{ "ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0 },
+	{ "ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0 },
+	{ "ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_ind_dat0_reg[] = {
+	{ "ind_dat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_ind_dat1_reg[] = {
+	{ "ind_dat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_fabric_or_saip_reg[] = {
+	{ "fabric_or_saip", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_max_pkt_len_reg[] = {
+	{ "max_pkt_len", DPP_FIELD_FLAG_RW, 14, 15, 0x3f00, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_age_en_reg[] = {
+	{ "age_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_age_mode_reg[] = {
+	{ "age_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_age_value_time_reg[] = {
+	{ "age_value_time", DPP_FIELD_FLAG_RW, 31, 32, 0xe4e1c0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_age_value_room_reg[] = {
+	{ "age_value_room", DPP_FIELD_FLAG_RW, 31, 32, 0x1e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_age_out_cnt_reg[] = {
+	{ "age_out_cnt", DPP_FIELD_FLAG_RW, 6, 7, 0xa, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_token_value_a_reg[] = {
+	{ "token_value_a", DPP_FIELD_FLAG_RW, 31, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_token_value_b_reg[] = {
+	{ "token_value_b", DPP_FIELD_FLAG_RW, 31, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_cfg_shap_en_p0_reg[] = {
+	{ "cfg_shap_en_p0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_cfg_shap_en_p1_reg[] = {
+	{ "cfg_shap_en_p1", DPP_FIELD_FLAG_RW, 31, 28, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_cfg_shap_en_tm_reg[] = {
+	{ "cfg_shap_en_tm", DPP_FIELD_FLAG_RW, 31, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_stat_ind_status_reg[] = {
+	{ "ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_stat_ind_cmd_reg[] = {
+	{ "ind_rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0 },
+	{ "ind_mem_id", DPP_FIELD_FLAG_RW, 27, 8, 0x0, 0x0 },
+	{ "ind_mem_addr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_stat_ind_data0_reg[] = {
+	{ "ind_dat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_stat_debug_cnt_cfg_reg[] = {
+	{ "debug_cnt_ovf_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "debug_cnt_rdclr_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0 },
+	{ "user_cnt_value", DPP_FIELD_FLAG_RW, 29, 4, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_bfd_firstchk_th_reg[] = {
+	{ "bfd_firstchk_th", DPP_FIELD_FLAG_RW, 18, 19, 0xc350, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_memid_0_pbu_fc_idmath_ram_reg[] = {
+	{ "lif_th_15", DPP_FIELD_FLAG_RW, 164, 15, 0x0, 0x0 },
+	{ "lif_prv_15", DPP_FIELD_FLAG_RW, 149, 15, 0x0, 0x0 },
+	{ "idma_prv_15", DPP_FIELD_FLAG_RW, 134, 15, 0x0, 0x0 },
+	{ "idma_th_cos0_15", DPP_FIELD_FLAG_RW, 119, 15, 0x0, 0x0 },
+	{ "idma_th_cos1_15", DPP_FIELD_FLAG_RW, 104, 15, 0x0, 0x0 },
+	{ "idma_th_cos2_15", DPP_FIELD_FLAG_RW, 89, 15, 0x0, 0x0 },
+	{ "idma_th_cos3_15", DPP_FIELD_FLAG_RW, 74, 15, 0x0, 0x0 },
+	{ "idma_th_cos4_15", DPP_FIELD_FLAG_RW, 59, 15, 0x0, 0x0 },
+	{ "idma_th_cos5_15", DPP_FIELD_FLAG_RW, 44, 15, 0x0, 0x0 },
+	{ "idma_th_cos6_15", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0 },
+	{ "idma_th_cos7_15", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_memid_1_pbu_fc_macth_ram_reg[] = {
+	{ "cos7_th", DPP_FIELD_FLAG_RW, 119, 15, 0x0, 0x0 },
+	{ "cos6_th", DPP_FIELD_FLAG_RW, 104, 15, 0x0, 0x0 },
+	{ "cos5_th", DPP_FIELD_FLAG_RW, 89, 15, 0x0, 0x0 },
+	{ "cos4_th", DPP_FIELD_FLAG_RW, 74, 15, 0x0, 0x0 },
+	{ "cos3_th", DPP_FIELD_FLAG_RW, 59, 15, 0x0, 0x0 },
+	{ "cos2_th", DPP_FIELD_FLAG_RW, 44, 15, 0x0, 0x0 },
+	{ "cos1_th", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0 },
+	{ "cos0_th", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_1_all_kind_port_cnt_reg[] = {
+	{ "peak_port_cnt", DPP_FIELD_FLAG_RO, 29, 15, 0x0, 0x0 },
+	{ "current_port_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_2_ppu_pbu_ifb_req_vld_cnt_reg[] = {
+	{ "ppu_pbu_ifb_req_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_ifb_rsp_vld_cnt_reg[] = {
+	{ "pbu_ppu_ifb_rsp_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_2_odma_pbu_recy_ptr_vld_cnt_reg[] = {
+	{ "odma_pbu_recy_ptr_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_2_ppu_pbu_mcode_pf_req_cnt_reg[] = {
+	{ "ppu_pbu_mcode_pf_req_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_rsp_cnt_reg[] = {
+	{ "pbu_ppu_mcode_pf_rsp_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_2_ppu_pbu_logic_pf_req_cnt_reg[] = {
+	{ "ppu_pbu_logic_pf_req_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_rsp_cnt_reg[] = {
+	{ "pbu_ppu_logic_pf_rsp_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_2_ppu_use_ptr_pulse_cnt_reg[] = {
+	{ "ppu_use_ptr_pulse_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_2_ppu_pbu_wb_vld_cnt_reg[] = {
+	{ "ppu_pbu_wb_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_reorder_para_vld_cnt_reg[] = {
+	{ "pbu_ppu_reorder_para_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_2_se_pbu_dpi_key_vld_cnt_reg[] = {
+	{ "se_pbu_dpi_key_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_se_dpi_rsp_datvld_cnt_reg[] = {
+	{ "pbu_se_dpi_rsp_datvld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd1_cnt_reg[] = {
+	{ "odma_pbu_ifb_rd1_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd2_cnt_reg[] = {
+	{ "odma_pbu_ifb_rd2_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_no_rsp_cnt_reg[] = {
+	{ "pbu_ppu_mcode_pf_no_rsp_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_no_rsp_cnt_reg[] = {
+	{ "pbu_ppu_logic_pf_no_rsp_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_3_cpu_rd_ifb_data_reg[] = {
+	{ "cpu_rd_ifb_data", DPP_FIELD_FLAG_RO, 2047, 2048, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_4_mux_sel_rgt_reg[] = {
+	{ "current_port_cnt", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_memid_5_port_pub_cnt_reg[] = {
+	{ "port_pub_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_idma_stat_memid_1_idma_o_isu_pkt_pulse_total_cnt_reg[] = {
+	{ "idma_o_isu_pkt_pulse_total_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_idma_stat_memid_1_idma_o_isu_epkt_pulse_total_cnt_reg[] = {
+	{ "idma_o_isu_epkt_pulse_total_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_idma_stat_memid_1_idma_dispkt_pulse_total_cnt_reg[] = {
+	{ "idma_dispkt_pulse_total_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_idma_stat_memid_0_idma_o_isu_pkt_pulse_cnt_reg[] = {
+	{ "idma_o_isu_pkt_pulse_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_idma_stat_memid_0_idma_o_isu_epkt_pulse_cnt_reg[] = {
+	{ "idma_o_isu_epkt_pulse_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_idma_stat_memid_0_idma_dispkt_pulse_cnt_reg[] = {
+	{ "idma_dispkt_pulse_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_test_r_reg[] = {
+	{ "test_r", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_debug_en_r_reg[] = {
+	{ "debug_en_r", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_csr_dup_table_wr_data_reg[] = {
+	{ "item_vld", DPP_FIELD_FLAG_RW, 24, 1, 0x0, 0x0 },
+	{ "flownum_vld", DPP_FIELD_FLAG_RW, 23, 1, 0x0, 0x0 },
+	{ "start_pc", DPP_FIELD_FLAG_RW, 22, 15, 0x0, 0x0 },
+	{ "flownum", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_csr_dup_table_rd_data_reg[] = {
+	{ "item_vld", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0 },
+	{ "flownum_vld", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0 },
+	{ "start_pc", DPP_FIELD_FLAG_RO, 22, 15, 0x0, 0x0 },
+	{ "flownum", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_csr_dup_table_addr_reg[] = {
+	{ "csr_dup_table_operation", DPP_FIELD_FLAG_WO, 6, 1, 0x0, 0x0 },
+	{ "csr_dup_table_addr", DPP_FIELD_FLAG_WO, 5, 6, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_debug_vld_reg[] = {
+	{ "ppu_debug_vld", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_319_288_reg[] = {
+	{ "rsk_319_288", DPP_FIELD_FLAG_RW, 31, 32, 0x6d5a56da, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_287_256_reg[] = {
+	{ "rsk_287_256", DPP_FIELD_FLAG_RW, 31, 32, 0x255b0ec2, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_255_224_reg[] = {
+	{ "rsk_255_224", DPP_FIELD_FLAG_RW, 31, 32, 0x4167253d, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_223_192_reg[] = {
+	{ "rsk_223_192", DPP_FIELD_FLAG_RW, 31, 32, 0x43a38fb0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_191_160_reg[] = {
+	{ "rsk_191_160", DPP_FIELD_FLAG_RW, 31, 32, 0xd0ca2bcb, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_159_128_reg[] = {
+	{ "rsk_159_128", DPP_FIELD_FLAG_RW, 31, 32, 0xae7b30b4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_127_096_reg[] = {
+	{ "rsk_127_096", DPP_FIELD_FLAG_RW, 31, 32, 0x77cb2da3, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_095_064_reg[] = {
+	{ "rsk_095_064", DPP_FIELD_FLAG_RW, 31, 32, 0x8030f20c, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_063_032_reg[] = {
+	{ "rsk_063_032", DPP_FIELD_FLAG_RW, 31, 32, 0x6a42b73b, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_cop_thash_rsk_031_000_reg[] = {
+	{ "rsk_031_000", DPP_FIELD_FLAG_RW, 31, 32, 0xbeac01fa, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_cfg_ipv4_ipid_start_value_reg[] = {
+	{ "cfg_ipv4_ipid_start_value", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_cfg_ipv4_ipid_end_value_reg[] = {
+	{ "cfg_ipv4_ipid_end_value", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_cluster_mf_in_en_reg[] = {
+	{ "cluster_mf_in_en", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_empty_reg[] = {
+	{ "ppu_empty", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_w_addr_reg[] = {
+	{ "instrmem_w_addr", DPP_FIELD_FLAG_WO, 12, 13, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_w_data_191_160_reg[] = {
+	{ "instrmem_w_data_191_160", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_w_data_159_128_reg[] = {
+	{ "instrmem_w_data_159_128", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_w_data_127_96_reg[] = {
+	{ "instrmem_w_data_127_96", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_w_data_95_64_reg[] = {
+	{ "instrmem_w_data_95_64", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_w_data_63_32_reg[] = {
+	{ "instrmem_w_data_63_32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_w_data_31_0_reg[] = {
+	{ "instrmem_w_data_31_0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_fwft_mf_fifo_prog_full_assert_cfg_reg[] = {
+	{ "isu_fwft_mf_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_fwft_mf_fifo_prog_full_negate_cfg_reg[] = {
+	{ "isu_fwft_mf_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_int_1200m_mask_reg[] = {
+	{ "me7_interrupt_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "me6_interrupt_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "me5_interrupt_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "me4_interrupt_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "me3_interrupt_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "me2_interrupt_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "me1_interrupt_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "me0_interrupt_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu4k_cluster_wr_high_data_r_mex_reg[] = {
+	{ "wr_high_data_r_mex", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu4k_cluster_wr_low_data_r_mex_reg[] = {
+	{ "wr_low_data_r_mex", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu4k_cluster_addr_r_mex_reg[] = {
+	{ "operate_type", DPP_FIELD_FLAG_WO, 8, 1, 0x0, 0x0 },
+	{ "addr_r_mex", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu4k_cluster_sdt_tbl_ind_access_done_reg[] = {
+	{ "rd_addr_r_mex", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu4k_cluster_rd_high_data_r_mex_reg[] = {
+	{ "rd_high_data_r_mex", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu4k_cluster_rd_low_data_r_mex_reg[] = {
+	{ "rd_low_data_r_mex", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_init_ok_reg[] = {
+	{ "init_ok", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_rdy_reg[] = {
+	{ "cpu_rd_rdy", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_data_tmp0_reg[] = {
+	{ "cpu_rd_data_tmp0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_data_tmp1_reg[] = {
+	{ "cpu_rd_data_tmp1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_data_tmp2_reg[] = {
+	{ "cpu_rd_data_tmp2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_data_tmp3_reg[] = {
+	{ "cpu_rd_data_tmp3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_data_tmp4_reg[] = {
+	{ "cpu_rd_data_tmp4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_data_tmp5_reg[] = {
+	{ "cpu_rd_data_tmp5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_data_tmp6_reg[] = {
+	{ "cpu_rd_data_tmp6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_data_tmp7_reg[] = {
+	{ "cpu_rd_data_tmp7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_data_tmp8_reg[] = {
+	{ "cpu_rd_data_tmp8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_data_tmp9_reg[] = {
+	{ "cpu_rd_data_tmp9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_data_tmp10_reg[] = {
+	{ "cpu_rd_data_tmp10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_data_tmp11_reg[] = {
+	{ "cpu_rd_data_tmp11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_data_tmp12_reg[] = {
+	{ "cpu_rd_data_tmp12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_data_tmp13_reg[] = {
+	{ "cpu_rd_data_tmp13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_data_tmp14_reg[] = {
+	{ "cpu_rd_data_tmp14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_cpu_rd_data_tmp15_reg[] = {
+	{ "cpu_rd_data_tmp15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_v4_config_rgt_reg[] = {
+	{ "lpm_v4_shift_sel", DPP_FIELD_FLAG_RW, 4, 2, 0x0, 0x0 },
+	{ "lpm_v4_sram_cmp_flag", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0 },
+	{ "lpm_v4_ddr3_addr_sel", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_v6_config_rgt_reg[] = {
+	{ "lpm_v6_shift_sel", DPP_FIELD_FLAG_RW, 5, 2, 0x0, 0x0 },
+	{ "lpm_v6_sram_cmp_flag", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0 },
+	{ "lpm_v6_ddr3_addr_sel", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u0_pfull_ast_reg[] = {
+	{ "lpm_ext_rsp_fifo_u0_pfull_ast", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0 },
+};
+DPP_FIELD_T g_se_as_hash_age_pat_cfg_reg[] = {
+	{ "hash_age_pat_cfg", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_learn_rdy_cfg_reg[] = {
+	{ "learn_rdy_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_kschd_as_pful_cfg_reg[] = {
+	{ "kschd_as_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1326, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_kschd_dir_pful_cfg_reg[] = {
+	{ "kschd_dir_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1326, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_kschd_as_ept_cfg_reg[] = {
+	{ "kschd_as_ept_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0xc18, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_cpu_arbi_pful_cfg_reg[] = {
+	{ "cpu_arbi_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1326, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_kschd_pbu_pful_cfg_reg[] = {
+	{ "kschd_pbu_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1326, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_dir_pful_cfg_reg[] = {
+	{ "rschd_dir_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00360036, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_dir_ept_cfg_reg[] = {
+	{ "rschd_dir_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x000a000a, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_cmd_rgt_reg[] = {
+	{ "rd_flag", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "mask", DPP_FIELD_FLAG_RW, 20, 4, 0x0, 0x0 },
+	{ "reg_sram_flag", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0 },
+	{ "zgroup_id", DPP_FIELD_FLAG_RW, 15, 2, 0x0, 0x0 },
+	{ "zblock_id", DPP_FIELD_FLAG_RW, 13, 3, 0x0, 0x0 },
+	{ "zcell_id", DPP_FIELD_FLAG_RW, 10, 2, 0x0, 0x0 },
+	{ "addr", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp0_reg[] = {
+	{ "cpu_wr_data_tmp0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp1_reg[] = {
+	{ "cpu_wr_data_tmp1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp2_reg[] = {
+	{ "cpu_wr_data_tmp2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp3_reg[] = {
+	{ "cpu_wr_data_tmp3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp4_reg[] = {
+	{ "cpu_wr_data_tmp4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp5_reg[] = {
+	{ "cpu_wr_data_tmp5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp6_reg[] = {
+	{ "cpu_wr_data_tmp6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp7_reg[] = {
+	{ "cpu_wr_data_tmp7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp8_reg[] = {
+	{ "cpu_wr_data_tmp8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp9_reg[] = {
+	{ "cpu_wr_data_tmp9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp10_reg[] = {
+	{ "cpu_wr_data_tmp10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp11_reg[] = {
+	{ "cpu_wr_data_tmp11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp12_reg[] = {
+	{ "cpu_wr_data_tmp12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp13_reg[] = {
+	{ "cpu_wr_data_tmp13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp14_reg[] = {
+	{ "cpu_wr_data_tmp14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_wr_data_tmp15_reg[] = {
+	{ "cpu_wr_data_tmp15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_rdy_reg[] = {
+	{ "cpu_rd_rdy", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp0_reg[] = {
+	{ "cpu_rd_data_tmp0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp1_reg[] = {
+	{ "cpu_rd_data_tmp1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp2_reg[] = {
+	{ "cpu_rd_data_tmp2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp3_reg[] = {
+	{ "cpu_rd_data_tmp3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp4_reg[] = {
+	{ "cpu_rd_data_tmp4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp5_reg[] = {
+	{ "cpu_rd_data_tmp5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp6_reg[] = {
+	{ "cpu_rd_data_tmp6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp7_reg[] = {
+	{ "cpu_rd_data_tmp7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp8_reg[] = {
+	{ "cpu_rd_data_tmp8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp9_reg[] = {
+	{ "cpu_rd_data_tmp9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp10_reg[] = {
+	{ "cpu_rd_data_tmp10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp11_reg[] = {
+	{ "cpu_rd_data_tmp11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp12_reg[] = {
+	{ "cpu_rd_data_tmp12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp13_reg[] = {
+	{ "cpu_rd_data_tmp13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp14_reg[] = {
+	{ "cpu_rd_data_tmp14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_cpu_rd_data_tmp15_reg[] = {
+	{ "cpu_rd_data_tmp15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_hash0_ext_cfg_rgt_reg[] = {
+	{ "hash0_ext_mode", DPP_FIELD_FLAG_RW, 8, 8, 0x0, 0x0 },
+	{ "hash0_ext_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_hash1_ext_cfg_rgt_reg[] = {
+	{ "hash1_ext_mode", DPP_FIELD_FLAG_RW, 8, 8, 0x0, 0x0 },
+	{ "hash1_ext_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_hash2_ext_cfg_rgt_reg[] = {
+	{ "hash2_ext_mode", DPP_FIELD_FLAG_RW, 8, 8, 0x0, 0x0 },
+	{ "hash2_ext_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_hash3_ext_cfg_rgt_reg[] = {
+	{ "hash3_ext_mode", DPP_FIELD_FLAG_RW, 8, 8, 0x0, 0x0 },
+	{ "hash3_ext_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_hash0_tbl30_depth_reg[] = {
+	{ "hash0_tbl3_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0 },
+	{ "hash0_tbl2_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0 },
+	{ "hash0_tbl1_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0 },
+	{ "hash0_tbl0_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_hash0_tbl74_depth_reg[] = {
+	{ "hash0_tbl7_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0 },
+	{ "hash0_tbl6_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0 },
+	{ "hash0_tbl5_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0 },
+	{ "hash0_tbl4_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_hash1_tbl30_depth_reg[] = {
+	{ "hash1_tbl3_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0 },
+	{ "hash1_tbl2_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0 },
+	{ "hash1_tbl1_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0 },
+	{ "hash1_tbl0_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_hash1_tbl74_depth_reg[] = {
+	{ "hash1_tbl7_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0 },
+	{ "hash1_tbl6_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0 },
+	{ "hash1_tbl5_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0 },
+	{ "hash1_tbl4_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_hash2_tbl30_depth_reg[] = {
+	{ "hash2_tbl3_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0 },
+	{ "hash2_tbl2_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0 },
+	{ "hash2_tbl1_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0 },
+	{ "hash2_tbl0_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_hash2_tbl74_depth_reg[] = {
+	{ "hash2_tbl7_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0 },
+	{ "hash2_tbl6_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0 },
+	{ "hash2_tbl5_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0 },
+	{ "hash2_tbl4_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_hash3_tbl30_depth_reg[] = {
+	{ "hash3_tbl3_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0 },
+	{ "hash3_tbl2_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0 },
+	{ "hash3_tbl1_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0 },
+	{ "hash3_tbl0_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_hash3_tbl74_depth_reg[] = {
+	{ "hash3_tbl7_depth", DPP_FIELD_FLAG_RW, 31, 8, 0x12, 0x0 },
+	{ "hash3_tbl6_depth", DPP_FIELD_FLAG_RW, 23, 8, 0x12, 0x0 },
+	{ "hash3_tbl5_depth", DPP_FIELD_FLAG_RW, 15, 8, 0x12, 0x0 },
+	{ "hash3_tbl4_depth", DPP_FIELD_FLAG_RW, 7, 8, 0x12, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_wr_rsp_cfg_reg[] = {
+	{ "wr_rsp_fifo_cfg", DPP_FIELD_FLAG_RW, 9, 10, 0x18c, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_hash_mono_flag_reg[] = {
+	{ "hash3_mono_flag", DPP_FIELD_FLAG_RW, 31, 8, 0x0, 0x0 },
+	{ "hash2_mono_flag", DPP_FIELD_FLAG_RW, 23, 8, 0x0, 0x0 },
+	{ "hash1_mono_flag", DPP_FIELD_FLAG_RW, 15, 8, 0x0, 0x0 },
+	{ "hash0_mono_flag", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_hash10_ext_crc_cfg_reg[] = {
+	{ "hash1_crc_cfg", DPP_FIELD_FLAG_RW, 31, 16, 0x5555, 0x0 },
+	{ "hash0_crc_cfg", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_hash32_ext_crc_cfg_reg[] = {
+	{ "hash3_crc_cfg", DPP_FIELD_FLAG_RW, 31, 16, 0xffff, 0x0 },
+	{ "hash2_crc_cfg", DPP_FIELD_FLAG_RW, 15, 16, 0xaaaa, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_zblock_service_configure_reg[] = {
+	{ "service_sel", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0 },
+	{ "hash_channel_sel", DPP_FIELD_FLAG_RW, 2, 2, 0x0, 0x0 },
+	{ "st_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_zblock_hash_zcell_mono_reg[] = {
+	{ "ha_zcell3_mono_flag", DPP_FIELD_FLAG_RW, 27, 1, 0x0, 0x0 },
+	{ "ha_zcell3_tbl_id", DPP_FIELD_FLAG_RW, 26, 3, 0x0, 0x0 },
+	{ "ha_zcell2_mono_flag", DPP_FIELD_FLAG_RW, 19, 1, 0x0, 0x0 },
+	{ "ha_zcell2_tbl_id", DPP_FIELD_FLAG_RW, 18, 3, 0x0, 0x0 },
+	{ "ha_zcell1_mono_flag", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0 },
+	{ "ha_zcell1_tbl_id", DPP_FIELD_FLAG_RW, 10, 3, 0x0, 0x0 },
+	{ "ha_zcell0_mono_flag", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0 },
+	{ "ha_zcell0_tbl_id", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se4k_se_alg_zlock_hash_zreg_mono_reg[] = {
+	{ "ha_zreg3_mono_flag", DPP_FIELD_FLAG_RW, 27, 1, 0x0, 0x0 },
+	{ "ha_zreg3_tbl_id", DPP_FIELD_FLAG_RW, 26, 3, 0x0, 0x0 },
+	{ "ha_zreg2_mono_flag", DPP_FIELD_FLAG_RW, 19, 1, 0x0, 0x0 },
+	{ "ha_zreg2_tbl_id", DPP_FIELD_FLAG_RW, 18, 3, 0x0, 0x0 },
+	{ "ha_zreg1_mono_flag", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0 },
+	{ "ha_zreg1_tbl_id", DPP_FIELD_FLAG_RW, 10, 3, 0x0, 0x0 },
+	{ "ha_zreg0_mono_flag", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0 },
+	{ "ha_zreg0_tbl_id", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_init_done_reg[] = {
+	{ "init_done", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cpu_ind_wdat0_reg[] = {
+	{ "cpu_ind_wdat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cpu_ind_wdat1_reg[] = {
+	{ "cpu_ind_wdat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cpu_ind_wdat2_reg[] = {
+	{ "cpu_ind_wdat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cpu_ind_wdat3_reg[] = {
+	{ "cpu_ind_wdat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = {
+	{ "cpu_ind_rw", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "cpu_ind_rd_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0 },
+	{ "cpu_req_mode", DPP_FIELD_FLAG_RW, 27, 2, 0x0, 0x0 },
+	{ "cpu_ind_addr", DPP_FIELD_FLAG_RW, 25, 26, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rd_done_reg[] = {
+	{ "cpu_ind_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rdat0_reg[] = {
+	{ "cpu_ind_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rdat1_reg[] = {
+	{ "cpu_ind_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rdat2_reg[] = {
+	{ "cpu_ind_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rdat3_reg[] = {
+	{ "cpu_ind_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cfg_plcr_mono_reg[] = {
+	{ "cfg_plcr_mono", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_wr_arb_cpu_rdy_reg[] = {
+	{ "wr_arb_cpu_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_tm_stat_en_cfg_reg[] = {
+	{ "tm_stat_en_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_wdat0_reg[] = {
+	{ "ddr_wdat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_dir_arbi_ser_rpful_reg[] = {
+	{ "dir_arbi_ser_rpful", DPP_FIELD_FLAG_RW, 9, 10, 0x14a, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cfg_wr_arbi_pful2_reg[] = {
+	{ "hash_wr_pful", DPP_FIELD_FLAG_RW, 19, 10, 0x14a, 0x0 },
+	{ "dir_wr_pful", DPP_FIELD_FLAG_RW, 9, 10, 0x14a, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_etm_tbl_cfg_reg[] = {
+	{ "etm_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cfg_cash_addr_pful_reg[] = {
+	{ "cfg_cash_addr_pful", DPP_FIELD_FLAG_RW, 19, 20, 0x7e1f8, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ctrl_rfifo_cfg_reg[] = {
+	{ "brst_fwft_fifo_prog_empty_assert", DPP_FIELD_FLAG_RW, 31, 10, 0x2, 0x0 },
+	{ "brst_fwft_fifo_prog_empty_negate", DPP_FIELD_FLAG_RW, 21, 10, 0x2, 0x0 },
+	{ "brst_fwft_fifo_prog_full_assert", DPP_FIELD_FLAG_RW, 11, 6, 0x18, 0x0 },
+	{ "brst_fwft_fifo_prog_full_negate", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cache_req_fifo_cfg_reg[] = {
+	{ "srch_fifo_pfull_assert", DPP_FIELD_FLAG_RW, 9, 5, 0xc, 0x0 },
+	{ "srch_fifo_pfull_negate", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_wdat0_reg[] = {
+	{ "cpu_ind_eram_wdat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_etm_port_sel_cfg_reg[] = {
+	{ "etm_port0_sel_cfg", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0 },
+	{ "etm_port1_sel_cfg", DPP_FIELD_FLAG_RW, 14, 5, 0x1, 0x0 },
+	{ "etm_port2_sel_cfg", DPP_FIELD_FLAG_RW, 9, 5, 0xf, 0x0 },
+	{ "etm_port3_sel_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_tm_stat_cfg_reg[] = {
+	{ "stat_overflow_mode", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "tm_stat_mode_cfg", DPP_FIELD_FLAG_RW, 6, 3, 0x4, 0x0 },
+	{ "tm_flow_control_cfg", DPP_FIELD_FLAG_RW, 3, 4, 0xf, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_ppu_eram_depth_reg[] = {
+	{ "ppu_eram_depth", DPP_FIELD_FLAG_RW, 18, 19, 0x38000, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_ppu_eram_base_addr_reg[] = {
+	{ "ppu_eram_base_addr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_ppu_ddr_base_addr_reg[] = {
+	{ "ppu_ddr_base_addr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_plcr0_base_addr_reg[] = {
+	{ "plcr0_base_addr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_etm_stat_start_addr_cfg_reg[] = {
+	{ "etm_stat_start_addr_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_etm_stat_depth_cfg_reg[] = {
+	{ "etm_stat_depth_cfg", DPP_FIELD_FLAG_RW, 2, 3, 0x5, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cycle_mov_en_cfg_reg[] = {
+	{ "cycle_mov_en_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat0_reg[] = {
+	{ "wdat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_ctrl_tmp0_reg[] = {
+	{ "reg_tcam_flag", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0 },
+	{ "flush", DPP_FIELD_FLAG_RW, 29, 8, 0x0, 0x0 },
+	{ "rd_wr", DPP_FIELD_FLAG_RW, 21, 1, 0x0, 0x0 },
+	{ "wr_mode", DPP_FIELD_FLAG_RW, 20, 8, 0x0, 0x0 },
+	{ "dat_or_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x0, 0x0 },
+	{ "ram_sel", DPP_FIELD_FLAG_RW, 11, 3, 0x0, 0x0 },
+	{ "addr", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_ctrl_tmp1_reg[] = {
+	{ "row_or_col_msk", DPP_FIELD_FLAG_RW, 9, 1, 0x0, 0x0 },
+	{ "vben", DPP_FIELD_FLAG_RW, 8, 1, 0x0, 0x0 },
+	{ "vbit", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_rd_done_reg[] = {
+	{ "cpu_ind_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat0_reg[] = {
+	{ "cpu_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat1_reg[] = {
+	{ "cpu_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat2_reg[] = {
+	{ "cpu_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat3_reg[] = {
+	{ "cpu_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat4_reg[] = {
+	{ "cpu_rdat4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat5_reg[] = {
+	{ "cpu_rdat5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat6_reg[] = {
+	{ "cpu_rdat6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat7_reg[] = {
+	{ "cpu_rdat7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat8_reg[] = {
+	{ "cpu_rdat8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat9_reg[] = {
+	{ "cpu_rdat9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat10_reg[] = {
+	{ "cpu_rdat10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat11_reg[] = {
+	{ "cpu_rdat11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat12_reg[] = {
+	{ "cpu_rdat12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat13_reg[] = {
+	{ "cpu_rdat13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat14_reg[] = {
+	{ "cpu_rdat14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat15_reg[] = {
+	{ "cpu_rdat15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat16_reg[] = {
+	{ "cpu_rdat16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat17_reg[] = {
+	{ "cpu_rdat17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat18_reg[] = {
+	{ "cpu_rdat18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_rdat19_reg[] = {
+	{ "cpu_rdat19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_qvbo_reg[] = {
+	{ "qvbo", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cnt_overflow_mode_reg[] = {
+	{ "cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = {
+	{ "cara_drop", DPP_FIELD_FLAG_RW, 147, 1, 0x0, 0x0 },
+	{ "cara_plcr_en", DPP_FIELD_FLAG_RW, 146, 1, 0x0, 0x0 },
+	{ "cara_profile_id", DPP_FIELD_FLAG_RW, 145, 9, 0x0, 0x0 },
+	{ "cara_tq_h", DPP_FIELD_FLAG_RO, 136, 13, 0x0, 0x0 },
+	{ "cara_tq_l", DPP_FIELD_FLAG_RO, 123, 32, 0x0, 0x0 },
+	{ "cara_ted", DPP_FIELD_FLAG_RO, 91, 19, 0x0, 0x0 },
+	{ "cara_tcd", DPP_FIELD_FLAG_RO, 72, 19, 0x0, 0x0 },
+	{ "cara_tei", DPP_FIELD_FLAG_RO, 53, 27, 0x0, 0x0 },
+	{ "cara_tci", DPP_FIELD_FLAG_RO, 26, 27, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_profile_ram1_255_0_reg[] = {
+	{ "cara_profile_wr", DPP_FIELD_FLAG_RW, 224, 1, 0x0, 0x0 },
+	{ "cara_pkt_sign", DPP_FIELD_FLAG_RW, 216, 1, 0x0, 0x0 },
+	{ "cara_cd", DPP_FIELD_FLAG_RW, 215, 2, 0x0, 0x0 },
+	{ "cara_cf", DPP_FIELD_FLAG_RW, 213, 1, 0x0, 0x0 },
+	{ "cara_cm", DPP_FIELD_FLAG_RW, 212, 1, 0x0, 0x0 },
+	{ "cara_eir", DPP_FIELD_FLAG_RW, 211, 24, 0x0, 0x0 },
+	{ "cara_cir", DPP_FIELD_FLAG_RW, 187, 24, 0x0, 0x0 },
+	{ "cara_ebs_pbs", DPP_FIELD_FLAG_RW, 163, 27, 0x0, 0x0 },
+	{ "cara_cbs", DPP_FIELD_FLAG_RW, 136, 27, 0x0, 0x0 },
+	{ "cara_c_pri1", DPP_FIELD_FLAG_RW, 109, 5, 0x0, 0x0 },
+	{ "cara_c_pri2", DPP_FIELD_FLAG_RW, 104, 5, 0x0, 0x0 },
+	{ "cara_c_pri3", DPP_FIELD_FLAG_RW, 99, 5, 0x0, 0x0 },
+	{ "cara_c_pri4", DPP_FIELD_FLAG_RW, 94, 5, 0x0, 0x0 },
+	{ "cara_c_pri5", DPP_FIELD_FLAG_RW, 89, 5, 0x0, 0x0 },
+	{ "cara_c_pri6", DPP_FIELD_FLAG_RW, 84, 5, 0x0, 0x0 },
+	{ "cara_c_pri7", DPP_FIELD_FLAG_RW, 79, 5, 0x0, 0x0 },
+	{ "cara_e_g_pri1", DPP_FIELD_FLAG_RW, 74, 5, 0x0, 0x0 },
+	{ "cara_e_g_pri2", DPP_FIELD_FLAG_RW, 69, 5, 0x0, 0x0 },
+	{ "cara_e_g_pri3", DPP_FIELD_FLAG_RW, 64, 5, 0x0, 0x0 },
+	{ "cara_e_g_pri4", DPP_FIELD_FLAG_RW, 59, 5, 0x0, 0x0 },
+	{ "cara_e_g_pri5", DPP_FIELD_FLAG_RW, 54, 5, 0x0, 0x0 },
+	{ "cara_e_g_pri6", DPP_FIELD_FLAG_RW, 49, 5, 0x0, 0x0 },
+	{ "cara_e_g_pri7", DPP_FIELD_FLAG_RW, 44, 5, 0x0, 0x0 },
+	{ "cara_e_y_pri0", DPP_FIELD_FLAG_RW, 39, 5, 0x0, 0x0 },
+	{ "cara_e_y_pri1", DPP_FIELD_FLAG_RW, 34, 5, 0x0, 0x0 },
+	{ "cara_e_y_pri2", DPP_FIELD_FLAG_RW, 29, 5, 0x0, 0x0 },
+	{ "cara_e_y_pri3", DPP_FIELD_FLAG_RW, 24, 5, 0x0, 0x0 },
+	{ "cara_e_y_pri4", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0 },
+	{ "cara_e_y_pri5", DPP_FIELD_FLAG_RW, 14, 5, 0x0, 0x0 },
+	{ "cara_e_y_pri6", DPP_FIELD_FLAG_RW, 9, 5, 0x0, 0x0 },
+	{ "cara_e_y_pri7", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_qovs_ram_ram2_reg[] = {
+	{ "cara_qovs", DPP_FIELD_FLAG_RW, 1, 2, 0x2, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_look_up_table1_reg[] = {
+	{ "cara_flow_id", DPP_FIELD_FLAG_RW, 14, 12, 0x0, 0x0 },
+	{ "cara_sp", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_pkt_des_i_cnt_reg[] = {
+	{ "cara_pkt_des_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_green_pkt_i_cnt_reg[] = {
+	{ "cara_green_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_yellow_pkt_i_cnt_reg[] = {
+	{ "cara_yellow_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_red_pkt_i_cnt_reg[] = {
+	{ "cara_red_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_pkt_des_o_cnt_reg[] = {
+	{ "cara_pkt_des_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_green_pkt_o_cnt_reg[] = {
+	{ "cara_green_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_yellow_pkt_o_cnt_reg[] = {
+	{ "cara_yellow_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_red_pkt_o_cnt_reg[] = {
+	{ "cara_red_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_pkt_des_fc_for_cfg_cnt_reg[] = {
+	{ "cara_pkt_des_fc_for_cfg_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_appoint_qnum_or_sp_reg[] = {
+	{ "cara_appoint_qnum_or_not", DPP_FIELD_FLAG_RW, 19, 1, 0x0, 0x0 },
+	{ "cara_appoint_sp_or_not", DPP_FIELD_FLAG_RW, 18, 1, 0x0, 0x0 },
+	{ "cara_plcr_stat_sp", DPP_FIELD_FLAG_RW, 17, 3, 0x0, 0x0 },
+	{ "cara_plcr_stat_qnum", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_cfgmt_count_mode_reg[] = {
+	{ "cara_cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "cara_cfgmt_count_rd_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_pkt_size_cnt_reg[] = {
+	{ "cara_pkt_size_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_plcr_init_dont_reg[] = {
+	{ "cara_plcr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = {
+	{ "carb_drop", DPP_FIELD_FLAG_RW, 147, 1, 0x0, 0x0 },
+	{ "carb_plcr_en", DPP_FIELD_FLAG_RW, 146, 1, 0x0, 0x0 },
+	{ "carb_profile_id", DPP_FIELD_FLAG_RW, 145, 9, 0x0, 0x0 },
+	{ "carb_tq_h", DPP_FIELD_FLAG_RO, 136, 13, 0x0, 0x0 },
+	{ "carb_tq_l", DPP_FIELD_FLAG_RO, 123, 32, 0x0, 0x0 },
+	{ "carb_ted", DPP_FIELD_FLAG_RO, 91, 19, 0x0, 0x0 },
+	{ "carb_tcd", DPP_FIELD_FLAG_RO, 72, 19, 0x0, 0x0 },
+	{ "carb_tei", DPP_FIELD_FLAG_RO, 53, 27, 0x0, 0x0 },
+	{ "carb_tci", DPP_FIELD_FLAG_RO, 26, 27, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_profile_ram1_255_0_reg[] = {
+	{ "carb_profile_wr", DPP_FIELD_FLAG_RW, 224, 1, 0x0, 0x0 },
+	{ "carb_random_discard_en_e", DPP_FIELD_FLAG_RW, 218, 1, 0x0, 0x0 },
+	{ "carb_random_discard_en_c", DPP_FIELD_FLAG_RW, 217, 1, 0x0, 0x0 },
+	{ "carb_pkt_sign", DPP_FIELD_FLAG_RW, 216, 1, 0x0, 0x0 },
+	{ "carb_cd", DPP_FIELD_FLAG_RW, 215, 2, 0x0, 0x0 },
+	{ "carb_cf", DPP_FIELD_FLAG_RW, 213, 1, 0x0, 0x0 },
+	{ "carb_cm", DPP_FIELD_FLAG_RW, 212, 1, 0x0, 0x0 },
+	{ "carb_eir", DPP_FIELD_FLAG_RW, 211, 24, 0x0, 0x0 },
+	{ "carb_cir", DPP_FIELD_FLAG_RW, 187, 24, 0x0, 0x0 },
+	{ "carb_ebs_pbs", DPP_FIELD_FLAG_RW, 163, 27, 0x0, 0x0 },
+	{ "carb_cbs", DPP_FIELD_FLAG_RW, 136, 27, 0x0, 0x0 },
+	{ "carb_c_pri1", DPP_FIELD_FLAG_RW, 109, 5, 0x0, 0x0 },
+	{ "carb_c_pri2", DPP_FIELD_FLAG_RW, 104, 5, 0x0, 0x0 },
+	{ "carb_c_pri3", DPP_FIELD_FLAG_RW, 99, 5, 0x0, 0x0 },
+	{ "carb_c_pri4", DPP_FIELD_FLAG_RW, 94, 5, 0x0, 0x0 },
+	{ "carb_c_pri5", DPP_FIELD_FLAG_RW, 89, 5, 0x0, 0x0 },
+	{ "carb_c_pri6", DPP_FIELD_FLAG_RW, 84, 5, 0x0, 0x0 },
+	{ "carb_c_pri7", DPP_FIELD_FLAG_RW, 79, 5, 0x0, 0x0 },
+	{ "carb_e_g_pri1", DPP_FIELD_FLAG_RW, 74, 5, 0x0, 0x0 },
+	{ "carb_e_g_pri2", DPP_FIELD_FLAG_RW, 69, 5, 0x0, 0x0 },
+	{ "carb_e_g_pri3", DPP_FIELD_FLAG_RW, 64, 5, 0x0, 0x0 },
+	{ "carb_e_g_pri4", DPP_FIELD_FLAG_RW, 59, 5, 0x0, 0x0 },
+	{ "carb_e_g_pri5", DPP_FIELD_FLAG_RW, 54, 5, 0x0, 0x0 },
+	{ "carb_e_g_pri6", DPP_FIELD_FLAG_RW, 49, 5, 0x0, 0x0 },
+	{ "carb_e_g_pri7", DPP_FIELD_FLAG_RW, 44, 5, 0x0, 0x0 },
+	{ "carb_e_y_pri0", DPP_FIELD_FLAG_RW, 39, 5, 0x0, 0x0 },
+	{ "carb_e_y_pri1", DPP_FIELD_FLAG_RW, 34, 5, 0x0, 0x0 },
+	{ "carb_e_y_pri2", DPP_FIELD_FLAG_RW, 29, 5, 0x0, 0x0 },
+	{ "carb_e_y_pri3", DPP_FIELD_FLAG_RW, 24, 5, 0x0, 0x0 },
+	{ "carb_e_y_pri4", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0 },
+	{ "carb_e_y_pri5", DPP_FIELD_FLAG_RW, 14, 5, 0x0, 0x0 },
+	{ "carb_e_y_pri6", DPP_FIELD_FLAG_RW, 9, 5, 0x0, 0x0 },
+	{ "carb_e_y_pri7", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_qovs_ram_ram2_reg[] = {
+	{ "carb_qovs", DPP_FIELD_FLAG_RW, 1, 2, 0x2, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_look_up_table2_reg[] = {
+	{ "carb_flow_id", DPP_FIELD_FLAG_RW, 12, 10, 0x0, 0x0 },
+	{ "carb_sp", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_pkt_des_i_cnt_reg[] = {
+	{ "carb_pkt_des_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_green_pkt_i_cnt_reg[] = {
+	{ "carb_green_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_yellow_pkt_i_cnt_reg[] = {
+	{ "carb_yellow_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_red_pkt_i_cnt_reg[] = {
+	{ "carb_red_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_pkt_des_o_cnt_reg[] = {
+	{ "carb_pkt_des_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_green_pkt_o_cnt_reg[] = {
+	{ "carb_green_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_yellow_pkt_o_cnt_reg[] = {
+	{ "carb_yellow_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_red_pkt_o_cnt_reg[] = {
+	{ "carb_red_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_pkt_des_fc_for_cfg_cnt_reg[] = {
+	{ "carb_pkt_des_fc_for_cfg_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_appoint_qnum_or_sp_reg[] = {
+	{ "carb_appoint_qnum_or_not", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0 },
+	{ "carb_appoint_sp_or_not", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0 },
+	{ "carb_plcr_stat_sp", DPP_FIELD_FLAG_RW, 14, 3, 0x0, 0x0 },
+	{ "carb_plcr_stat_qnum", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_cfgmt_count_mode_reg[] = {
+	{ "carb_cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "carb_cfgmt_count_rd_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_pkt_size_cnt_reg[] = {
+	{ "carb_pkt_size_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_plcr_init_dont_reg[] = {
+	{ "carb_plcr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = {
+	{ "carc_drop", DPP_FIELD_FLAG_RW, 147, 1, 0x0, 0x0 },
+	{ "carc_plcr_en", DPP_FIELD_FLAG_RW, 146, 1, 0x0, 0x0 },
+	{ "carc_profile_id", DPP_FIELD_FLAG_RW, 145, 9, 0x0, 0x0 },
+	{ "carc_tq_h", DPP_FIELD_FLAG_RO, 136, 13, 0x0, 0x0 },
+	{ "carc_tq_l", DPP_FIELD_FLAG_RO, 123, 32, 0x0, 0x0 },
+	{ "carc_ted", DPP_FIELD_FLAG_RO, 91, 19, 0x0, 0x0 },
+	{ "carc_tcd", DPP_FIELD_FLAG_RO, 72, 19, 0x0, 0x0 },
+	{ "carc_tei", DPP_FIELD_FLAG_RO, 53, 27, 0x0, 0x0 },
+	{ "carc_tci", DPP_FIELD_FLAG_RO, 26, 27, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_profile_ram1_255_0_reg[] = {
+	{ "carc_profile_wr", DPP_FIELD_FLAG_RW, 224, 1, 0x0, 0x0 },
+	{ "carc_random_discard_en_e", DPP_FIELD_FLAG_RW, 218, 1, 0x0, 0x0 },
+	{ "carc_random_discard_en_c", DPP_FIELD_FLAG_RW, 217, 1, 0x0, 0x0 },
+	{ "carc_pkt_sign", DPP_FIELD_FLAG_RW, 216, 1, 0x0, 0x0 },
+	{ "carc_cd", DPP_FIELD_FLAG_RW, 215, 2, 0x0, 0x0 },
+	{ "carc_cf", DPP_FIELD_FLAG_RW, 213, 1, 0x0, 0x0 },
+	{ "carc_cm", DPP_FIELD_FLAG_RW, 212, 1, 0x0, 0x0 },
+	{ "carc_eir", DPP_FIELD_FLAG_RW, 211, 24, 0x0, 0x0 },
+	{ "carc_cir", DPP_FIELD_FLAG_RW, 187, 24, 0x0, 0x0 },
+	{ "carc_ebs_pbs", DPP_FIELD_FLAG_RW, 163, 27, 0x0, 0x0 },
+	{ "carc_cbs", DPP_FIELD_FLAG_RW, 136, 27, 0x0, 0x0 },
+	{ "carc_c_pri1", DPP_FIELD_FLAG_RW, 109, 5, 0x0, 0x0 },
+	{ "carc_c_pri2", DPP_FIELD_FLAG_RW, 104, 5, 0x0, 0x0 },
+	{ "carc_c_pri3", DPP_FIELD_FLAG_RW, 99, 5, 0x0, 0x0 },
+	{ "carc_c_pri4", DPP_FIELD_FLAG_RW, 94, 5, 0x0, 0x0 },
+	{ "carc_c_pri5", DPP_FIELD_FLAG_RW, 89, 5, 0x0, 0x0 },
+	{ "carc_c_pri6", DPP_FIELD_FLAG_RW, 84, 5, 0x0, 0x0 },
+	{ "carc_c_pri7", DPP_FIELD_FLAG_RW, 79, 5, 0x0, 0x0 },
+	{ "carc_e_g_pri1", DPP_FIELD_FLAG_RW, 74, 5, 0x0, 0x0 },
+	{ "carc_e_g_pri2", DPP_FIELD_FLAG_RW, 69, 5, 0x0, 0x0 },
+	{ "carc_e_g_pri3", DPP_FIELD_FLAG_RW, 64, 5, 0x0, 0x0 },
+	{ "carc_e_g_pri4", DPP_FIELD_FLAG_RW, 59, 5, 0x0, 0x0 },
+	{ "carc_e_g_pri5", DPP_FIELD_FLAG_RW, 54, 5, 0x0, 0x0 },
+	{ "carc_e_g_pri6", DPP_FIELD_FLAG_RW, 49, 5, 0x0, 0x0 },
+	{ "carc_e_g_pri7", DPP_FIELD_FLAG_RW, 44, 5, 0x0, 0x0 },
+	{ "carc_e_y_pri0", DPP_FIELD_FLAG_RW, 39, 5, 0x0, 0x0 },
+	{ "carc_e_y_pri1", DPP_FIELD_FLAG_RW, 34, 5, 0x0, 0x0 },
+	{ "carc_e_y_pri2", DPP_FIELD_FLAG_RW, 29, 5, 0x0, 0x0 },
+	{ "carc_e_y_pri3", DPP_FIELD_FLAG_RW, 24, 5, 0x0, 0x0 },
+	{ "carc_e_y_pri4", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0 },
+	{ "carc_e_y_pri5", DPP_FIELD_FLAG_RW, 14, 5, 0x0, 0x0 },
+	{ "carc_e_y_pri6", DPP_FIELD_FLAG_RW, 9, 5, 0x0, 0x0 },
+	{ "carc_e_y_pri7", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_qovs_ram_ram2_reg[] = {
+	{ "carc_qovs", DPP_FIELD_FLAG_RW, 1, 2, 0x2, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_pkt_des_i_cnt_reg[] = {
+	{ "carc_pkt_des_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_green_pkt_i_cnt_reg[] = {
+	{ "carc_green_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_yellow_pkt_i_cnt_reg[] = {
+	{ "carc_yellow_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_red_pkt_i_cnt_reg[] = {
+	{ "carc_red_pkt_i_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_pkt_des_o_cnt_reg[] = {
+	{ "carc_pkt_des_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_green_pkt_o_cnt_reg[] = {
+	{ "carc_green_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_yellow_pkt_o_cnt_reg[] = {
+	{ "carc_yellow_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_red_pkt_o_cnt_reg[] = {
+	{ "carc_red_pkt_o_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_pkt_des_fc_for_cfg_cnt_reg[] = {
+	{ "carc_pkt_des_fc_for_cfg_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_appoint_qnum_or_sp_reg[] = {
+	{ "carc_appoint_qnum_or_not", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0 },
+	{ "carc_appoint_sp_or_not", DPP_FIELD_FLAG_RW, 13, 1, 0x0, 0x0 },
+	{ "carc_plcr_stat_sp", DPP_FIELD_FLAG_RW, 12, 3, 0x0, 0x0 },
+	{ "carc_plcr_stat_qnum", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_cfgmt_count_mode_reg[] = {
+	{ "carc_cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "carc_cfgmt_count_rd_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_pkt_size_cnt_reg[] = {
+	{ "carc_pkt_size_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_plcr_init_dont_reg[] = {
+	{ "carc_plcr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_random_ram_reg[] = {
+	{ "para8_e", DPP_FIELD_FLAG_RW, 491, 27, 0x0, 0x0 },
+	{ "para7_e", DPP_FIELD_FLAG_RW, 464, 27, 0x0, 0x0 },
+	{ "para6_e", DPP_FIELD_FLAG_RW, 437, 27, 0x0, 0x0 },
+	{ "para5_e", DPP_FIELD_FLAG_RW, 410, 14, 0x0, 0x0 },
+	{ "para4_h_e", DPP_FIELD_FLAG_RW, 396, 9, 0x0, 0x0 },
+	{ "para4_l_e", DPP_FIELD_FLAG_RW, 387, 32, 0x0, 0x0 },
+	{ "para3_e", DPP_FIELD_FLAG_RW, 355, 14, 0x0, 0x0 },
+	{ "para2_h_e", DPP_FIELD_FLAG_RW, 341, 9, 0x0, 0x0 },
+	{ "para2_l_e", DPP_FIELD_FLAG_RW, 332, 32, 0x0, 0x0 },
+	{ "para1_e", DPP_FIELD_FLAG_RW, 300, 14, 0x0, 0x0 },
+	{ "para0_h_e", DPP_FIELD_FLAG_RW, 286, 9, 0x0, 0x0 },
+	{ "para0_l_e", DPP_FIELD_FLAG_RW, 277, 32, 0x0, 0x0 },
+	{ "para8_c", DPP_FIELD_FLAG_RW, 245, 27, 0x0, 0x0 },
+	{ "para7_c", DPP_FIELD_FLAG_RW, 218, 27, 0x0, 0x0 },
+	{ "para6_c", DPP_FIELD_FLAG_RW, 191, 27, 0x0, 0x0 },
+	{ "para5_c", DPP_FIELD_FLAG_RW, 164, 14, 0x0, 0x0 },
+	{ "para4_h_c", DPP_FIELD_FLAG_RW, 150, 9, 0x0, 0x0 },
+	{ "para4_l_c", DPP_FIELD_FLAG_RW, 141, 32, 0x0, 0x0 },
+	{ "para3_c", DPP_FIELD_FLAG_RW, 109, 14, 0x0, 0x0 },
+	{ "para2_h_c", DPP_FIELD_FLAG_RW, 95, 9, 0x0, 0x0 },
+	{ "para2_l_c", DPP_FIELD_FLAG_RW, 86, 32, 0x0, 0x0 },
+	{ "para1_c", DPP_FIELD_FLAG_RW, 54, 14, 0x0, 0x0 },
+	{ "para0_h_c", DPP_FIELD_FLAG_RW, 40, 9, 0x0, 0x0 },
+	{ "para0_l_c", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_random_ram_reg[] = {
+	{ "para8_e", DPP_FIELD_FLAG_RW, 491, 27, 0x0, 0x0 },
+	{ "para7_e", DPP_FIELD_FLAG_RW, 464, 27, 0x0, 0x0 },
+	{ "para6_e", DPP_FIELD_FLAG_RW, 437, 27, 0x0, 0x0 },
+	{ "para5_e", DPP_FIELD_FLAG_RW, 410, 14, 0x0, 0x0 },
+	{ "para4_h_e", DPP_FIELD_FLAG_RW, 396, 9, 0x0, 0x0 },
+	{ "para4_l_e", DPP_FIELD_FLAG_RW, 387, 32, 0x0, 0x0 },
+	{ "para3_e", DPP_FIELD_FLAG_RW, 355, 14, 0x0, 0x0 },
+	{ "para2_h_e", DPP_FIELD_FLAG_RW, 341, 9, 0x0, 0x0 },
+	{ "para2_l_e", DPP_FIELD_FLAG_RW, 332, 32, 0x0, 0x0 },
+	{ "para1_e", DPP_FIELD_FLAG_RW, 300, 14, 0x0, 0x0 },
+	{ "para0_h_e", DPP_FIELD_FLAG_RW, 286, 9, 0x0, 0x0 },
+	{ "para0_l_e", DPP_FIELD_FLAG_RW, 277, 32, 0x0, 0x0 },
+	{ "para8_c", DPP_FIELD_FLAG_RW, 245, 27, 0x0, 0x0 },
+	{ "para7_c", DPP_FIELD_FLAG_RW, 218, 27, 0x0, 0x0 },
+	{ "para6_c", DPP_FIELD_FLAG_RW, 191, 27, 0x0, 0x0 },
+	{ "para5_c", DPP_FIELD_FLAG_RW, 164, 14, 0x0, 0x0 },
+	{ "para4_h_c", DPP_FIELD_FLAG_RW, 150, 9, 0x0, 0x0 },
+	{ "para4_l_c", DPP_FIELD_FLAG_RW, 141, 32, 0x0, 0x0 },
+	{ "para3_c", DPP_FIELD_FLAG_RW, 109, 14, 0x0, 0x0 },
+	{ "para2_h_c", DPP_FIELD_FLAG_RW, 95, 9, 0x0, 0x0 },
+	{ "para2_l_c", DPP_FIELD_FLAG_RW, 86, 32, 0x0, 0x0 },
+	{ "para1_c", DPP_FIELD_FLAG_RW, 54, 14, 0x0, 0x0 },
+	{ "para0_h_c", DPP_FIELD_FLAG_RW, 40, 9, 0x0, 0x0 },
+	{ "para0_l_c", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_begin_flow_id_reg[] = {
+	{ "cara_begin_flow_id", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carb_begin_flow_id_reg[] = {
+	{ "carb_begin_flow_id", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_carc_begin_flow_id_reg[] = {
+	{ "carc_begin_flow_id", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_prog_full_assert_cfg_w_reg[] = {
+	{ "prog_full_assert_cfg_w", DPP_FIELD_FLAG_RW, 7, 8, 0xe0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_prog_full_negate_cfg_w_reg[] = {
+	{ "prog_full_negate_cfg_w", DPP_FIELD_FLAG_RW, 7, 8, 0xdf, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_timeout_limit_reg[] = {
+	{ "timeout_limit", DPP_FIELD_FLAG_RW, 15, 16, 0x100, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_pkt_des_fifo_overflow_reg[] = {
+	{ "pkt_des_fifo_overflow", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_pkt_des_fifo_underflow_reg[] = {
+	{ "pkt_des_fifo_underflow", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_pkt_des_fifo_prog_full_reg[] = {
+	{ "pkt_des_fifo_prog_full", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_pkt_des_fifo_prog_empty_reg[] = {
+	{ "pkt_des_fifo_prog_empty", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_pkt_des_fifo_full_reg[] = {
+	{ "pkt_des_fifo_full", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_pkt_des_fifo_empty_reg[] = {
+	{ "pkt_des_fifo_empty", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_pkt_size_offset_reg[] = {
+	{ "pkt_size_offset", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_car_plcr_init_dont_reg[] = {
+	{ "plcr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_max_pkt_size_a_reg[] = {
+	{ "max_pkt_size_a", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_max_pkt_size_b_reg[] = {
+	{ "max_pkt_size_b", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_max_pkt_size_c_reg[] = {
+	{ "max_pkt_size_c", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_car_hierarchy_mode_reg[] = {
+	{ "car_hierarchy_mode", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_prog_empty_assert_cfg_w_reg[] = {
+	{ "prog_empty_assert_cfg_w", DPP_FIELD_FLAG_RW, 7, 8, 0x3, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_prog_empty_negate_cfg_w_reg[] = {
+	{ "prog_empty_negate_cfg_w", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_pkt_des_fifo_ovf_int_reg[] = {
+	{ "pkt_des_fifo_ovf_int", DPP_FIELD_FLAG_RO, 1, 2, 0x00, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_pkt_des_fifo_data_count_reg[] = {
+	{ "pkt_des_fifo_data_count", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_pkt_des_fifo_udf_int_reg[] = {
+	{ "pkt_des_fifo_udf_int", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_queue_ram0_159_0_pkt_reg[] = {
+	{ "cara_drop", DPP_FIELD_FLAG_RW, 147, 1, 0x0, 0x0 },
+	{ "cara_plcr_en", DPP_FIELD_FLAG_RW, 146, 1, 0x0, 0x0 },
+	{ "cara_profile_id", DPP_FIELD_FLAG_RW, 145, 9, 0x0, 0x0 },
+	{ "cara_tq_h", DPP_FIELD_FLAG_RO, 136, 13, 0x0, 0x0 },
+	{ "cara_tq_l", DPP_FIELD_FLAG_RO, 123, 32, 0x0, 0x0 },
+	{ "cara_dc_high", DPP_FIELD_FLAG_RO, 50, 5, 0x0, 0x0 },
+	{ "cara_dc_low", DPP_FIELD_FLAG_RO, 45, 32, 0x0, 0x0 },
+	{ "cara_tc", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_car0_cara_profile_ram1_255_0_pkt_reg[] = {
+	{ "cara_profile_wr", DPP_FIELD_FLAG_RW, 224, 1, 0x0, 0x0 },
+	{ "cara_pkt_sign", DPP_FIELD_FLAG_RW, 216, 1, 0x0, 0x0 },
+	{ "cara_pkt_cir", DPP_FIELD_FLAG_RW, 189, 30, 0x0, 0x0 },
+	{ "cara_pkt_cbs", DPP_FIELD_FLAG_RW, 150, 14, 0x0, 0x0 },
+	{ "cara_pri0", DPP_FIELD_FLAG_RW, 39, 5, 0x0, 0x0 },
+	{ "cara_pri1", DPP_FIELD_FLAG_RW, 34, 5, 0x0, 0x0 },
+	{ "cara_pri2", DPP_FIELD_FLAG_RW, 29, 5, 0x0, 0x0 },
+	{ "cara_pri3", DPP_FIELD_FLAG_RW, 24, 5, 0x0, 0x0 },
+	{ "cara_pri4", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0 },
+	{ "cara_pri5", DPP_FIELD_FLAG_RW, 14, 5, 0x0, 0x0 },
+	{ "cara_pri6", DPP_FIELD_FLAG_RW, 9, 5, 0x0, 0x0 },
+	{ "cara_pri7", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat4k_etcam_block0_7_port_id_cfg_reg[] = {
+	{ "block7_port_id", DPP_FIELD_FLAG_RW, 31, 4, 0x0, 0x0 },
+	{ "block6_port_id", DPP_FIELD_FLAG_RW, 27, 4, 0x0, 0x0 },
+	{ "block5_port_id", DPP_FIELD_FLAG_RW, 23, 4, 0x0, 0x0 },
+	{ "block4_port_id", DPP_FIELD_FLAG_RW, 19, 4, 0x0, 0x0 },
+	{ "block3_port_id", DPP_FIELD_FLAG_RW, 15, 4, 0x0, 0x0 },
+	{ "block2_port_id", DPP_FIELD_FLAG_RW, 11, 4, 0x0, 0x0 },
+	{ "block1_port_id", DPP_FIELD_FLAG_RW, 7, 4, 0x0, 0x0 },
+	{ "block0_port_id", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat4k_etcam_block0_3_base_addr_cfg_reg[] = {
+	{ "block3_base_addr_cfg", DPP_FIELD_FLAG_RW, 30, 7, 0x0, 0x0 },
+	{ "block2_base_addr_cfg", DPP_FIELD_FLAG_RW, 22, 7, 0x0, 0x0 },
+	{ "block1_base_addr_cfg", DPP_FIELD_FLAG_RW, 14, 7, 0x0, 0x0 },
+	{ "block0_base_addr_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat4k_etcam_block4_7_base_addr_cfg_reg[] = {
+	{ "block7_base_addr_cfg", DPP_FIELD_FLAG_RW, 30, 7, 0x0, 0x0 },
+	{ "block6_base_addr_cfg", DPP_FIELD_FLAG_RW, 22, 7, 0x0, 0x0 },
+	{ "block5_base_addr_cfg", DPP_FIELD_FLAG_RW, 14, 7, 0x0, 0x0 },
+	{ "block4_base_addr_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_eram_wr_interval_cnt_reg[] = {
+	{ "cfg_eram_wr_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_zcam_wr_interval_cnt_reg[] = {
+	{ "cfg_zcam_wr_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_tcam_wr_interval_cnt_reg[] = {
+	{ "cfg_zcam_wr_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_ddr_wr_interval_cnt_reg[] = {
+	{ "cfg_ddr_wr_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_hash_wr_interval_cnt_reg[] = {
+	{ "cfg_hash_wr_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_eram_rd_interval_cnt_reg[] = {
+	{ "cfg_eram_rd_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_zcam_rd_interval_cnt_reg[] = {
+	{ "cfg_zcam_rd_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_tcam_rd_interval_cnt_reg[] = {
+	{ "cfg_tcam_rd_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_ddr_rd_interval_cnt_reg[] = {
+	{ "cfg_ddr_rd_interval_cnt", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_queue_lock_state_0_3_reg[] = {
+	{ "cfg_dtb_queue_lock_state", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_axim0_w_convert_0_mode_reg[] = {
+	{ "w_convert_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_axim0_r_convert_0_mode_reg[] = {
+	{ "r_convert_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_axim0_aximr_os_reg[] = {
+	{ "aximr_os", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_axim1_w_convert_1_mode_reg[] = {
+	{ "w_convert_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_axim1_r_convert_1_mode_reg[] = {
+	{ "r_convert_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_axis_axis_convert_mode_reg[] = {
+	{ "w_r_convert_mode", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb4k_dtb_enq_cfg_queue_dtb_addr_h_0_127_reg[] = {
+	{ "cfg_queue_dtb_addr_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb4k_dtb_enq_cfg_queue_dtb_addr_l_0_127_reg[] = {
+	{ "cfg_queue_dtb_addr_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb4k_dtb_enq_cfg_queue_dtb_len_0_127_reg[] = {
+	{ "cfg_dtb_cmd_type", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0 },
+	{ "cfg_dtb_cmd_int_en", DPP_FIELD_FLAG_RW, 29, 1, 0x0, 0x0 },
+	{ "cfg_queue_dtb_len", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg[] = {
+	{ "info_queue_buf_space_left", DPP_FIELD_FLAG_RO, 5, 6, 0x20, 0x0 },
+};
+DPP_FIELD_T g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg[] = {
+	{ "dbi_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "queue_en", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0 },
+	{ "cfg_epid", DPP_FIELD_FLAG_RW, 27, 4, 0x0, 0x0 },
+	{ "cfg_vfunc_num", DPP_FIELD_FLAG_RW, 23, 8, 0x0, 0x0 },
+	{ "cfg_vector", DPP_FIELD_FLAG_RW, 14, 7, 0x0, 0x0 },
+	{ "cfg_func_num", DPP_FIELD_FLAG_RW, 7, 3, 0x0, 0x0 },
+	{ "cfg_vfunc_active", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_ms_en_reg[] = {
+	{ "cpu_trpgrx_ms_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_port_en_reg[] = {
+	{ "cpu_trpgrx_port_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_look_en_reg[] = {
+	{ "cpu_trpgrx_look_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_ram_almost_full_reg[] = {
+	{ "cpu_trpgrx_ram_almost_full", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_ram_test_en_reg[] = {
+	{ "cpu_trpgrx_ram_test_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_inmod_pfc_rdy_en_reg[] = {
+	{ "cpu_trpgrx_inmod_pfc_rdy_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_h_reg[] = {
+	{ "cpu_trpgrx_pkt_num_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_l_reg[] = {
+	{ "cpu_trpgrx_pkt_num_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_h_reg[] = {
+	{ "cpu_trpgrx_pkt_byte_num_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_l_reg[] = {
+	{ "cpu_trpgrx_pkt_byte_num_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_cnt_clr_reg[] = {
+	{ "cpu_trpgrx_pkt_cnt_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_fc_clk_freq_reg[] = {
+	{ "cpu_trpgrx_fc_clk_freq", DPP_FIELD_FLAG_RW, 10, 11, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_fc_en_reg[] = {
+	{ "cpu_trpgrx_fc_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_fc_token_add_num_reg[] = {
+	{ "cpu_trpgrx_fc_token_add_num", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_fc_token_max_num_reg[] = {
+	{ "cpu_trpgrx_fc_token_max_num", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_port_state_info_reg[] = {
+	{ "cpu_trpgrx_port_state_info", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_reg[] = {
+	{ "cpu_trpgrx_ram_past_max_dep", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_clr_reg[] = {
+	{ "cpu_trpgrx_ram_past_max_dep_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_reg[] = {
+	{ "cpu_trpgrx_pkt_past_max_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_clr_reg[] = {
+	{ "cpu_trpgrx_pkt_past_max_len_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_reg[] = {
+	{ "cpu_trpgrx_pkt_past_min_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_clr_reg[] = {
+	{ "cpu_trpgrx_pkt_past_min_len_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_ram_trpg_rx_data_ram_reg[] = {
+	{ "trpg_rx_data_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_ram_trpg_rx_info_ram_reg[] = {
+	{ "trpg_rx_info_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_ms_en_reg[] = {
+	{ "cpu_trpgtx_ms_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_port_en_reg[] = {
+	{ "cpu_trpgtx_port_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_look_en_reg[] = {
+	{ "cpu_trpgtx_look_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_ram_almost_full_reg[] = {
+	{ "cpu_trpgtx_ram_almost_full", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_ram_test_en_reg[] = {
+	{ "cpu_trpgtx_ram_test_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_h_reg[] = {
+	{ "cpu_trpgtx_pkt_num_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_l_reg[] = {
+	{ "cpu_trpgtx_pkt_num_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_h_reg[] = {
+	{ "cpu_trpgtx_pkt_byte_num_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_l_reg[] = {
+	{ "cpu_trpgtx_pkt_byte_num_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_cnt_clr_reg[] = {
+	{ "cpu_trpgtx_pkt_cnt_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_fc_clk_freq_reg[] = {
+	{ "cpu_trpgtx_fc_clk_freq", DPP_FIELD_FLAG_RW, 10, 11, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_fc_en_reg[] = {
+	{ "cpu_trpgtx_fc_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_fc_token_add_num_reg[] = {
+	{ "cpu_trpgtx_fc_token_add_num", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_fc_token_max_num_reg[] = {
+	{ "cpu_trpgtx_fc_token_max_num", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_port_state_info_reg[] = {
+	{ "cpu_trpgtx_port_state_info", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_reg[] = {
+	{ "cpu_trpgtx_ram_past_max_dep", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_clr_reg[] = {
+	{ "cpu_trpgtx_ram_past_max_dep_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_reg[] = {
+	{ "cpu_trpgtx_pkt_past_max_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_clr_reg[] = {
+	{ "cpu_trpgtx_pkt_past_max_len_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_reg[] = {
+	{ "cpu_trpgtx_pkt_past_min_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_clr_reg[] = {
+	{ "cpu_trpgtx_pkt_past_min_len_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_almost_full_reg[] = {
+	{ "cpu_trpgtx_etm_ram_almost_full", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_test_en_reg[] = {
+	{ "cpu_trpgtx_etm_ram_test_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_update_int_mask_reg[] = {
+	{ "cpu_todtime_update_int_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_update_int_clr_reg[] = {
+	{ "cpu_todtime_update_int_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_ram_test_en_reg[] = {
+	{ "cpu_todtime_ram_test_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_ram_trpg_tx_data_ram_reg[] = {
+	{ "trpg_tx_data_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_ram_trpg_tx_info_ram_reg[] = {
+	{ "trpg_tx_info_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_etm_ram_trpg_tx_etm_data_ram_reg[] = {
+	{ "trpg_tx_etm_data_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_etm_ram_trpg_tx_etm_info_ram_reg[] = {
+	{ "trpg_tx_etm_info_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_chip_version_reg_reg[] = {
+	{ "chip_version_reg", DPP_FIELD_FLAG_RO, 31, 4, 0x1, 0x0 },
+	{ "chip_sub_reg", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0 },
+	{ "chip_type_reg", DPP_FIELD_FLAG_RO, 23, 24, 0x211650, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_chip_date_reg_reg[] = {
+	{ "chip_date_reg", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_cfgmt_crc_en_reg[] = {
+	{ "cfgmt_crc_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_cfg_port_transfer_en_reg[] = {
+	{ "cfg_port_transfer_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_tm_sa_work_mode_reg[] = {
+	{ "tm_sa_work_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cfgmt_local_sa_id_reg[] = {
+	{ "local_sa_id", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_olif_rdy_reg[] = {
+	{ "cfgmt_block_mode", DPP_FIELD_FLAG_RO, 5, 2, 0x2, 0x0 },
+	{ "cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RO, 3, 1, 0x1, 0x0 },
+	{ "cfgmt_count_rd_mode", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "olif_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_emem_prog_full_reg[] = {
+	{ "emem_prog_full_assert", DPP_FIELD_FLAG_RW, 24, 9, 0xb9, 0x0 },
+	{ "emem_prog_full_negate", DPP_FIELD_FLAG_RW, 8, 9, 0xac, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_port_order_fifo_full_reg[] = {
+	{ "port_order_fifo_full_assert", DPP_FIELD_FLAG_RW, 22, 7, 0x32, 0x0 },
+	{ "port_order_fifo_full_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x32, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_olif_release_last_reg[] = {
+	{ "olif_release_last_addr", DPP_FIELD_FLAG_RO, 24, 19, 0x0, 0x0 },
+	{ "olif_release_last_bank", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_olif_fifo_empty_state_reg[] = {
+	{ "qmu_para_fifo_empty", DPP_FIELD_FLAG_RO, 2, 1, 0x1, 0x0 },
+	{ "emem_empty", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0 },
+	{ "imem_empty", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_qmu_olif_release_fc_cnt_reg[] = {
+	{ "qmu_olif_release_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_olif_qmu_link_fc_cnt_reg[] = {
+	{ "olif_qmu_link_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_lif0_link_fc_cnt_reg[] = {
+	{ "lif0_link_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_olif_tmmu_fc_cnt_reg[] = {
+	{ "olif_tmmu_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_olif_mmu_fc_cnt_reg[] = {
+	{ "olif_mmu_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_olif_qmu_port_rdy_h_reg[] = {
+	{ "olif_qmu_port_rdy_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_olif_qmu_port_rdy_l_reg[] = {
+	{ "olif_qmu_port_rdy_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_lif0_port_rdy_h_reg[] = {
+	{ "lif0_port_rdy_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_lif0_port_rdy_l_reg[] = {
+	{ "lif0_port_rdy_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_qmu_olif_rd_sop_cnt_reg[] = {
+	{ "qmu_olif_rd_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_qmu_olif_rd_eop_cnt_reg[] = {
+	{ "qmu_olif_rd_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_qmu_olif_rd_vld_cnt_reg[] = {
+	{ "qmu_olif_rd_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_qmu_olif_rd_blk_cnt_reg[] = {
+	{ "qmu_olif_rd_blk_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_mmu_tm_data_sop_cnt_reg[] = {
+	{ "mmu_tm_data_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_mmu_tm_data_eop_cnt_reg[] = {
+	{ "mmu_tm_data_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_mmu_tm_data_vld_cnt_reg[] = {
+	{ "mmu_tm_data_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_odma_tm_data_sop_cnt_reg[] = {
+	{ "odma_tm_data_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_odma_tm_data_eop_cnt_reg[] = {
+	{ "odma_tm_data_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_odma_tm_deq_vld_cnt_reg[] = {
+	{ "odma_tm_deq_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_olif_qmu_release_vld_cnt_reg[] = {
+	{ "olif_qmu_release_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_emem_dat_vld_cnt_reg[] = {
+	{ "emem_dat_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_imem_dat_vld_cnt_reg[] = {
+	{ "imem_dat_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_emem_dat_rd_cnt_reg[] = {
+	{ "emem_dat_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_imem_dat_rd_cnt_reg[] = {
+	{ "imem_dat_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_qmu_olif_rd_sop_emem_cnt_reg[] = {
+	{ "qmu_olif_rd_sop_emem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_qmu_olif_rd_vld_emem_cnt_reg[] = {
+	{ "qmu_olif_rd_vld_emem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_cpu_last_wr_addr_reg[] = {
+	{ "cpu_last_wr_addr", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_cpu_last_wr_data_reg[] = {
+	{ "cpu_last_wr_data", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_cpu_last_rd_addr_reg[] = {
+	{ "cpu_last_rd_addr", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_qmu_olif_last_port_reg[] = {
+	{ "qmu_olif_last_port", DPP_FIELD_FLAG_RO, 6, 7, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_qmu_olif_last_addr_reg[] = {
+	{ "qmu_olif_last_addr", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_qmu_olif_last_bank_reg[] = {
+	{ "qmu_olif_last_bank", DPP_FIELD_FLAG_RO, 6, 7, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_tm_lif_byte_stat_reg[] = {
+	{ "tm_lif_byte_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_olif_tm_lif_err_stat_reg[] = {
+	{ "tm_lif_err_stat", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_port_share_cnt_reg[] = {
+	{ "port_share_cnt", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_total_imem_cnt_reg[] = {
+	{ "total_imem_cnt", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_pp_q_len_reg[] = {
+	{ "pp_q_len", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_sys_q_len_reg[] = {
+	{ "sys_q_len", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_cfg_error_warning_reg[] = {
+	{ "error_correction_11", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0 },
+	{ "error_correction_10", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0 },
+	{ "error_correction_9", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0 },
+	{ "error_correction_8", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0 },
+	{ "error_correction_7", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "error_correction_6", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "error_correction5", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "error_correction_4", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "error_correction_3", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "error_correction_2", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "error_correction_1", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "error_correction_0", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_mult_qlen_th_en_reg[] = {
+	{ "mult_qlen_th", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_mult_qlen_th_reg[] = {
+	{ "mult_qlen_th", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_cfg_move_reg[] = {
+	{ "cfgmt_sys_move_en", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0 },
+	{ "cfgmt_port_move_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "cfgmt_flow_move_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cfgmt_total_th_reg[] = {
+	{ "cfgmt_total_th", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cfgmt_port_share_th_reg[] = {
+	{ "cfgmt_port_share_th", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_sa_unreach_state_reg[] = {
+	{ "sa_unreach_state", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_mv_port_th_reg[] = {
+	{ "port_th", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_mv_drop_sp_th_reg[] = {
+	{ "mvdrop_sp_th", DPP_FIELD_FLAG_RW, 8, 9, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_state_warning_reg[] = {
+	{ "deq_q_num_warning", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "deq_pkt_len_warning", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "enq_pkt_dp_warning", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "unenq_q_num_warning", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "enq_q_num_warning", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "enq_pkt_len_warning", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_reg[] = {
+	{ "tmmu_cgavd_dma_fifo_cnt", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_max_reg[] = {
+	{ "tmmu_cgavd_dma_fifo_cnt_max", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_imem_total_cnt_reg[] = {
+	{ "imem_total_cnt", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_imem_total_cnt_max_reg[] = {
+	{ "imem_total_cnt_max", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow0_omem_cnt_reg[] = {
+	{ "flow0_omem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow1_omem_cnt_reg[] = {
+	{ "flow1_omem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow2_omem_cnt_reg[] = {
+	{ "flow2_omem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow3_omem_cnt_reg[] = {
+	{ "flow3_omem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_flow4_omem_cnt_reg[] = {
+	{ "flow4_omem_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_appoint_flow_num_message_1_reg[] = {
+	{ "appoint_flow_num_en_1", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0 },
+	{ "appoint_flow_num_1", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_appoint_flow_num_message_2_reg[] = {
+	{ "appoint_flow_num_en_2", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "appoint_flow_num_2", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_odma_cgavd_pkt_num_1_reg[] = {
+	{ "odma_cgavd_pkt_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_odma_cgavd_byte_num_1_reg[] = {
+	{ "odma_cgavd_byte_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_enqueue_pkt_num_1_reg[] = {
+	{ "cgavd_enqueue_pkt_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_dequeue_pkt_num_1_reg[] = {
+	{ "cgavd_dequeue_pkt_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_imem_num_1_reg[] = {
+	{ "cgavd_qmu_pkt_imem_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_omem_num_1_reg[] = {
+	{ "cgavd_qmu_pkt_omem_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_imem_num_1_reg[] = {
+	{ "cgavd_qmu_byte_imem_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_omem_num_1_reg[] = {
+	{ "cgavd_qmu_byte_omem_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_drop_num_1_reg[] = {
+	{ "cgavd_qmu_pkt_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_drop_num_1_reg[] = {
+	{ "cgavd_qmu_byte_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_forbid_drop_num_1_reg[] = {
+	{ "cgavd_qmu_forbid_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_td_drop_num_1_reg[] = {
+	{ "cgavd_qmu_flow_td_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_wred_drop_num_1_reg[] = {
+	{ "cgavd_qmu_flow_wred_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_1_reg[] = {
+	{ "cgavd_qmu_flow_wred_dp_drop_num1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_td_num_1_reg[] = {
+	{ "cgavd_qmu_pp_td_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_wred_drop_num_1_reg[] = {
+	{ "cgavd_qmu_pp_wred_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_1_reg[] = {
+	{ "cgavd_qmu_pp_wred_dp_drop_num1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_td_drop_num_1_reg[] = {
+	{ "cgavd_qmu_sys_td_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_gred_drop_num_1_reg[] = {
+	{ "cgavd_qmu_sys_gred_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num1_reg[] = {
+	{ "cgavd_qmu_sys_gred_dp_drop_num1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sa_drop_num_1_reg[] = {
+	{ "cgavd_qmu_sa_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_move_drop_num_1_reg[] = {
+	{ "cgavd_qmu_move_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_tm_mult_drop_num_1_reg[] = {
+	{ "cgavd_qmu_tm_mult_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_tm_error_drop_num_1_reg[] = {
+	{ "cgavd_qmu_tm_error_drop_num_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_odma_cgavd_pkt_num_2_reg[] = {
+	{ "odma_cgavd_pkt_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_odma_cgavd_byte_num_2_reg[] = {
+	{ "odma_cgavd_byte_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_enqueue_pkt_num_2_reg[] = {
+	{ "cgavd_enqueue_pkt_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_dequeue_pkt_num_2_reg[] = {
+	{ "cgavd_dequeue_pkt_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_imem_num_2_reg[] = {
+	{ "cgavd_qmu_pkt_imem_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_omem_num_2_reg[] = {
+	{ "cgavd_qmu_pkt_omem_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_imem_num_2_reg[] = {
+	{ "cgavd_qmu_byte_imem_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_omem_num_2_reg[] = {
+	{ "cgavd_qmu_byte_omem_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pkt_drop_num_2_reg[] = {
+	{ "cgavd_qmu_pkt_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_byte_drop_num_2_reg[] = {
+	{ "cgavd_qmu_byte_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_forbid_drop_num_2_reg[] = {
+	{ "cgavd_qmu_forbid_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_td_drop_num_2_reg[] = {
+	{ "cgavd_qmu_flow_td_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_wred_drop_num_2_reg[] = {
+	{ "cgavd_qmu_flow_wred_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_2_reg[] = {
+	{ "cgavd_qmu_flow_wred_dp_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_td_num_2_reg[] = {
+	{ "cgavd_qmu_pp_td_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_wred_drop_num_2_reg[] = {
+	{ "cgavd_qmu_pp_wred_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_2_reg[] = {
+	{ "cgavd_qmu_pp_wred_dp_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_td_drop_num_2_reg[] = {
+	{ "cgavd_qmu_sys_td_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_gred_drop_num_2_reg[] = {
+	{ "cgavd_qmu_sys_gred_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num_2_reg[] = {
+	{ "cgavd_qmu_sys_gred_dp_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_sa_drop_num_2_reg[] = {
+	{ "cgavd_qmu_sa_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_move_drop_num_2_reg[] = {
+	{ "cgavd_qmu_move_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_tm_mult_drop_num_2_reg[] = {
+	{ "cgavd_qmu_tm_mult_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_cgavd_qmu_tm_error_drop_num_2_reg[] = {
+	{ "cgavd_qmu_tm_error_drop_num_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_move_flow_th_profile_reg[] = {
+	{ "move_drop_profile", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_cgavd_move_flow_th_reg[] = {
+	{ "move_drop_flow_th", DPP_FIELD_FLAG_RW, 28, 29, 0x50, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_emem_pd_fifo_aful_th_reg[] = {
+	{ "emem_pd_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_dma_data_fifo_aful_th_reg[] = {
+	{ "dma_data_fifo_aful_th", DPP_FIELD_FLAG_RW, 9, 10, 0x190, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_states_0_reg[] = {
+	{ "tm_odma_pkt_rdy", DPP_FIELD_FLAG_RO, 30, 1, 0x1, 0x0 },
+	{ "dma_data_fifo_empty", DPP_FIELD_FLAG_RO, 29, 1, 0x1, 0x0 },
+	{ "imem_enq_rd_fifo_empty", DPP_FIELD_FLAG_RO, 28, 1, 0x1, 0x0 },
+	{ "imem_enq_drop_fifo_empty", DPP_FIELD_FLAG_RO, 27, 1, 0x1, 0x0 },
+	{ "imem_deq_rd_fifo_empty", DPP_FIELD_FLAG_RO, 26, 1, 0x1, 0x0 },
+	{ "imem_deq_drop_fifo_empty", DPP_FIELD_FLAG_RO, 25, 1, 0x1, 0x0 },
+	{ "wr_cmd_fifo_empty", DPP_FIELD_FLAG_RO, 24, 1, 0x1, 0x0 },
+	{ "cached_pd_fifo_empty", DPP_FIELD_FLAG_RO, 23, 1, 0x1, 0x0 },
+	{ "emem_pd_fifo_empty", DPP_FIELD_FLAG_RO, 22, 1, 0x1, 0x0 },
+	{ "pd_order_fifo_empty", DPP_FIELD_FLAG_RO, 21, 1, 0x1, 0x0 },
+	{ "odma_tm_data_rdy", DPP_FIELD_FLAG_RO, 20, 1, 0x1, 0x0 },
+	{ "odma_tm_discard_rdy", DPP_FIELD_FLAG_RO, 19, 1, 0x1, 0x0 },
+	{ "olif_tmmu_rdy", DPP_FIELD_FLAG_RO, 18, 1, 0x1, 0x0 },
+	{ "mmu_tm_cmd_wr_rdy", DPP_FIELD_FLAG_RO, 17, 1, 0x1, 0x0 },
+	{ "mmu_tm_data_wr_rdy", DPP_FIELD_FLAG_RO, 16, 1, 0x1, 0x0 },
+	{ "mmu_tm_rd_rdy", DPP_FIELD_FLAG_RO, 15, 1, 0x1, 0x0 },
+	{ "mmu_tm_sop_rd_rdy", DPP_FIELD_FLAG_RO, 14, 1, 0x1, 0x0 },
+	{ "qmu_tmmu_sop_data_rdy", DPP_FIELD_FLAG_RO, 13, 1, 0x1, 0x0 },
+	{ "tmmu_cmdsw_imem_release_rdy", DPP_FIELD_FLAG_RO, 12, 1, 0x1, 0x0 },
+	{ "imem_age_release_rdy", DPP_FIELD_FLAG_RO, 11, 1, 0x1, 0x0 },
+	{ "tmmu_qmu_wr_rdy", DPP_FIELD_FLAG_RO, 10, 1, 0x1, 0x0 },
+	{ "tmmu_qmu_rdy_7", DPP_FIELD_FLAG_RO, 9, 1, 0x1, 0x0 },
+	{ "tmmu_qmu_rdy_6", DPP_FIELD_FLAG_RO, 8, 1, 0x1, 0x0 },
+	{ "tmmu_qmu_rdy_5", DPP_FIELD_FLAG_RO, 7, 1, 0x1, 0x0 },
+	{ "tmmu_qmu_rdy_4", DPP_FIELD_FLAG_RO, 6, 1, 0x1, 0x0 },
+	{ "tmmu_qmu_rdy_3", DPP_FIELD_FLAG_RO, 5, 1, 0x1, 0x0 },
+	{ "tmmu_qmu_rdy_2", DPP_FIELD_FLAG_RO, 4, 1, 0x1, 0x0 },
+	{ "tmmu_qmu_rdy_1", DPP_FIELD_FLAG_RO, 3, 1, 0x1, 0x0 },
+	{ "tmmu_qmu_rdy_0", DPP_FIELD_FLAG_RO, 2, 1, 0x1, 0x0 },
+	{ "tmmu_qmu_rd_rdy", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0 },
+	{ "tmmu_qmu_sop_rd_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_qmu_tmmu_wr_sop_cnt_reg[] = {
+	{ "qmu_tmmu_wr_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_qmu_tmmu_wr_eop_cnt_reg[] = {
+	{ "qmu_tmmu_wr_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_qmu_tmmu_wr_drop_cnt_reg[] = {
+	{ "qmu_tmmu_wr_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_qmu_tmmu_wr_emem_cnt_reg[] = {
+	{ "qmu_tmmu_wr_emem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_qmu_tmmu_wr_imem_cnt_reg[] = {
+	{ "qmu_tmmu_wr_imem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_mmu_wr_sop_cnt_reg[] = {
+	{ "tmmu_mmu_wr_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_mmu_wr_eop_cnt_reg[] = {
+	{ "tmmu_mmu_wr_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_qmu_tmmu_rd_sop_cnt_reg[] = {
+	{ "qmu_tmmu_rd_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_qmu_tmmu_rd_eop_cnt_reg[] = {
+	{ "qmu_tmmu_rd_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_qmu_tmmu_rd_drop_cnt_reg[] = {
+	{ "qmu_tmmu_rd_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_qmu_tmmu_rd_emem_cnt_reg[] = {
+	{ "qmu_tmmu_rd_emem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_qmu_tmmu_rd_imem_cnt_reg[] = {
+	{ "qmu_tmmu_rd_imem_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_mmu_rd_sop_cnt_reg[] = {
+	{ "tmmu_mmu_rd_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_mmu_rd_eop_cnt_reg[] = {
+	{ "tmmu_mmu_rd_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_odma_in_sop_cnt_reg[] = {
+	{ "tmmu_odma_in_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_odma_in_eop_cnt_reg[] = {
+	{ "tmmu_odma_in_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_odma_vld_cnt_reg[] = {
+	{ "tmmu_odma_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_qmu_pd_in_cnt_reg[] = {
+	{ "qmu_pd_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_pd_hit_cnt_reg[] = {
+	{ "tmmu_pd_hit_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_pd_out_cnt_reg[] = {
+	{ "tmmu_pd_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_wr_cmd_fifo_wr_cnt_reg[] = {
+	{ "tmmu_wr_cmd_fifo_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_imem_age_cnt_reg[] = {
+	{ "tmmu_imem_age_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_cmdsch_rd_cnt_reg[] = {
+	{ "tmmu_cmdsch_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_cmdsch_drop_cnt_reg[] = {
+	{ "tmmu_cmdsch_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_cmdsw_drop_cnt_reg[] = {
+	{ "tmmu_cmdsw_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_odma_enq_rd_cnt_reg[] = {
+	{ "tmmu_odma_enq_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_odma_enq_drop_cnt_reg[] = {
+	{ "tmmu_odma_enq_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_odma_imem_age_cnt_reg[] = {
+	{ "tmmu_odma_imem_age_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_odma_deq_rd_cnt_reg[] = {
+	{ "tmmu_odma_deq_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tmmu_odma_deq_drop_cnt_reg[] = {
+	{ "tmmu_odma_deq_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_olif_tmmu_xoff_cnt_reg[] = {
+	{ "olif_tmmu_xoff_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_odma_tm_data_xoff_cnt_reg[] = {
+	{ "odma_tm_data_xoff_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tm_odma_pkt_xoff_cnt_reg[] = {
+	{ "tm_odma_pkt_xoff_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_tm_state_3_reg[] = {
+	{ "tmmu_qmu_rdy_9", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0 },
+	{ "tmmu_qmu_rdy_8", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_cmd_reg[] = {
+	{ "cfgmt_pd_cache_addr", DPP_FIELD_FLAG_RW, 12, 13, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_rd_done_reg[] = {
+	{ "cfgmt_pd_cache_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_rd_data_0_reg[] = {
+	{ "cfgmt_pd_cache_rd_data_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_rd_data_1_reg[] = {
+	{ "cfgmt_pd_cache_rd_data_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_rd_data_2_reg[] = {
+	{ "cfgmt_pd_cache_rd_data_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_pd_cache_rd_data_3_reg[] = {
+	{ "cfgmt_pd_cache_rd_data_3", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_tmmu_to_odma_para_reg[] = {
+	{ "cfgmt_tmmu_to_odma_para", DPP_FIELD_FLAG_RO, 25, 26, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_dma_data_fifo_cnt_reg[] = {
+	{ "cfgmt_dma_data_fifo_cnt", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit0_offset_reg[] = {
+	{ "cfgmt_cache_tag_bit0_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xd, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit1_offset_reg[] = {
+	{ "cfgmt_cache_tag_bit1_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xe, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit2_offset_reg[] = {
+	{ "cfgmt_cache_tag_bit2_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xf, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit3_offset_reg[] = {
+	{ "cfgmt_cache_tag_bit3_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit4_offset_reg[] = {
+	{ "cfgmt_cache_tag_bit4_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x11, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_tag_bit5_offset_reg[] = {
+	{ "cfgmt_cache_tag_bit5_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x12, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit0_offset_reg[] = {
+	{ "cfgmt_cache_index_bit0_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit1_offset_reg[] = {
+	{ "cfgmt_cache_index_bit1_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit2_offset_reg[] = {
+	{ "cfgmt_cache_index_bit2_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x2, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit3_offset_reg[] = {
+	{ "cfgmt_cache_index_bit3_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x3, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit4_offset_reg[] = {
+	{ "cfgmt_cache_index_bit4_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit5_offset_reg[] = {
+	{ "cfgmt_cache_index_bit5_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x5, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit6_offset_reg[] = {
+	{ "cfgmt_cache_index_bit6_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x6, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit7_offset_reg[] = {
+	{ "cfgmt_cache_index_bit7_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x7, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit8_offset_reg[] = {
+	{ "cfgmt_cache_index_bit8_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x8, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit9_offset_reg[] = {
+	{ "cfgmt_cache_index_bit9_offset", DPP_FIELD_FLAG_RW, 4, 5, 0x9, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit10_offset_reg[] = {
+	{ "cfgmt_cache_index_bit10_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit11_offset_reg[] = {
+	{ "cfgmt_cache_index_bit11_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xb, 0x0 },
+};
+DPP_FIELD_T g_etm_tmmu_cfgmt_cache_index_bit12_offset_reg[] = {
+	{ "cfgmt_cache_index_bit12_offset", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_bktfull_fifo_full_flagregister_reg[] = {
+	{ "bktfull_fifo_full_flag_core", DPP_FIELD_FLAG_RC, 21, 22, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_fifo_full_regregister_reg[] = {
+	{ "fifo_full_reg", DPP_FIELD_FLAG_RO, 21, 22, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_fifo_empty_regregister_reg[] = {
+	{ "fifo_empty_reg", DPP_FIELD_FLAG_RO, 21, 22, 0x7, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_fifo_almost_full_regregister_reg[] = {
+	{ "fifo_almost_full_reg", DPP_FIELD_FLAG_RO, 21, 22, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_shap_fifo_almost_empty_regregister_reg[] = {
+	{ "fifo_almost_empty_reg", DPP_FIELD_FLAG_RO, 21, 22, 0x7, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_credit_space_select_reg[] = {
+	{ "credit_space_select", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_space_max_reg[] = {
+	{ "stat_space_max", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_space_min_reg[] = {
+	{ "stat_space_min", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_space_credit_reg[] = {
+	{ "stat_space_credit", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_stat_que_step8_credit_reg[] = {
+	{ "stat_que_step8_credit", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_special_que_reg[] = {
+	{ "special_que_id", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_special_que_credit_reg[] = {
+	{ "special_que_credit", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_lif_congest_credit_cnt_reg[] = {
+	{ "lif_congest_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_lif_port_congest_credit_cnt_reg[] = {
+	{ "lif_port_congest_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_congest_credit_cnt_reg[] = {
+	{ "crdt_congest_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_port_congest_credit_cnt_reg[] = {
+	{ "crdt_port_congest_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_congest_port_id_reg[] = {
+	{ "congest_port_id", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_dev_link_control_reg[] = {
+	{ "dev_link_control", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_sa_port_rdy_reg[] = {
+	{ "crdt_sa_port_rdy", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_congest_mode_select_reg[] = {
+	{ "crdt_congest_mode_selectr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_fifo_out_all_crs_normal_cnt_reg[] = {
+	{ "fifo_out_all_crs_normal_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_fifo_out_all_crs_off_cnt_reg[] = {
+	{ "fifo_out_all_crs_off_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_fifo_out_que_crs_normal_cnt_reg[] = {
+	{ "fifo_out_que_crs_normal_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_fifo_out_que_crs_off_cnt_reg[] = {
+	{ "fifo_out_que_crs_off_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_mode_add_60g_reg[] = {
+	{ "mode_add_60g", DPP_FIELD_FLAG_RW, 15, 16, 0xff, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_pp_token_add_reg[] = {
+	{ "pp_token_add_cir", DPP_FIELD_FLAG_RO, 4, 5, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_pp_cir_token_total_dist_cnt_reg[] = {
+	{ "pp_cir_token_total_dist_counter", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_pp_cir_token_total_dec_cnt_reg[] = {
+	{ "pp_cir_token_total_dec_counter", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_dev_credit_cnt_reg[] = {
+	{ "dev_credit_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_no_credit_cnt1_reg[] = {
+	{ "no_credit_cnt1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_no_credit_cnt2_reg[] = {
+	{ "no_credit_cnt2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_asm_interval_0_cfg_reg[] = {
+	{ "asm_interval_0_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0xf, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_asm_interval_1_cfg_reg[] = {
+	{ "asm_interval_1_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x1f, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_asm_interval_2_cfg_reg[] = {
+	{ "asm_interval_2_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x2f, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_asm_interval_3_cfg_reg[] = {
+	{ "asm_interval_3_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x3f, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_asm_interval_4_cfg_reg[] = {
+	{ "asm_interval_4_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x4f, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_asm_interval_5cfg_reg[] = {
+	{ "asm_interval_5_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x5f, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_asm_interval_6_cfg_reg[] = {
+	{ "asm_interval_6_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x6f, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_asm_interval_7_cfg_reg[] = {
+	{ "asm_interval_7_cfg", DPP_FIELD_FLAG_RW, 21, 22, 0x7f, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_total_congest_mode_cfg_reg[] = {
+	{ "crdt_total_congest_mode_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_rci_fifo_ini_deep_cfg_reg[] = {
+	{ "rci_fifo_ini_deep_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0x1f4, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_ecc_reg[] = {
+	{ "seinfo_wfq_single_ecc_err", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "seinfo_wfq_double_ecc_err", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "seinfo_fq_single_ecc_err", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "seinfo_fq_double_ecc_err", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "ecc_bypass", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_ucn_asm_rdy_shield_en_reg[] = {
+	{ "ucn_rdy_shield_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "asm_rdy_shield_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_ucn_asm_rdy_reg[] = {
+	{ "ucn_rdy", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0 },
+	{ "asm_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_rci_grade_reg[] = {
+	{ "rci_grade", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_rci_value_r_reg[] = {
+	{ "crdt_rci_value_r", DPP_FIELD_FLAG_RO, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crdt_interval_now_reg[] = {
+	{ "crdt_interval_now", DPP_FIELD_FLAG_RO, 21, 22, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crs_sheild_flow_id_cfg_reg[] = {
+	{ "crs_sheild_flow_id_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crs_sheild_en_cfg_reg[] = {
+	{ "crs_sheild_en_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_crs_sheild_value_cfg_reg[] = {
+	{ "crs_sheild_value_cfg", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_test_token_calc_ctrl_reg[] = {
+	{ "test_token_calc_state", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "test_token_calc_trigger", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_test_token_sample_cycle_num_reg[] = {
+	{ "sample_cycle_num", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_q_state_0_7_reg[] = {
+	{ "q_token_state_7", DPP_FIELD_FLAG_RO, 29, 2, 0x0, 0x0 },
+	{ "q_token_state_6", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0 },
+	{ "q_token_state_5", DPP_FIELD_FLAG_RO, 21, 2, 0x0, 0x0 },
+	{ "q_token_state_4", DPP_FIELD_FLAG_RO, 17, 2, 0x0, 0x0 },
+	{ "q_token_state_3", DPP_FIELD_FLAG_RO, 13, 2, 0x0, 0x0 },
+	{ "q_token_state_2", DPP_FIELD_FLAG_RO, 9, 2, 0x0, 0x0 },
+	{ "q_token_state_1", DPP_FIELD_FLAG_RO, 5, 2, 0x0, 0x0 },
+	{ "q_token_state_0", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_crdt_q_state_8_15_reg[] = {
+	{ "q_token_state_15", DPP_FIELD_FLAG_RO, 29, 2, 0x0, 0x0 },
+	{ "q_token_state_14", DPP_FIELD_FLAG_RO, 25, 2, 0x0, 0x0 },
+	{ "q_token_state_13", DPP_FIELD_FLAG_RO, 21, 2, 0x0, 0x0 },
+	{ "q_token_state_12", DPP_FIELD_FLAG_RO, 17, 2, 0x0, 0x0 },
+	{ "q_token_state_11", DPP_FIELD_FLAG_RO, 13, 2, 0x0, 0x0 },
+	{ "q_token_state_10", DPP_FIELD_FLAG_RO, 9, 2, 0x0, 0x0 },
+	{ "q_token_state_9", DPP_FIELD_FLAG_RO, 5, 2, 0x0, 0x0 },
+	{ "q_token_state_8", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csw_csch_rd_cmd_cnt_reg[] = {
+	{ "csw_csch_rd_cmd_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csw_csch_rd_sop_cnt_reg[] = {
+	{ "csw_csch_rd_sop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csw_csch_rd_eop_cnt_reg[] = {
+	{ "csw_csch_rd_eop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csw_csch_rd_drop_cnt_reg[] = {
+	{ "csw_csch_rd_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csch_mmu_rd_cmd_cnt_reg[] = {
+	{ "csch_mmu_rd_cmd_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csch_mmu_rd_sop_cnt_reg[] = {
+	{ "csch_mmu_rd_sop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csch_mmu_rd_eop_cnt_reg[] = {
+	{ "csch_mmu_rd_eop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csch_mmu_rd_drop_cnt_reg[] = {
+	{ "csch_mmu_rd_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_filter_reg[] = {
+	{ "qcfg_qsch_crs_filter", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_force_en_reg[] = {
+	{ "qcfg_qsch_crs_force_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_force_qnum_reg[] = {
+	{ "qcfg_qsch_crs_force_qnum", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qsch_crs_force_crs_reg[] = {
+	{ "qcfg_qsch_crs_force_crs", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_oshp_sgmii_shap_mode_reg[] = {
+	{ "cfgmt_oshp_sgmii_shap_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_sashap_en_reg[] = {
+	{ "cfgmt_qmu_sashap_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_sashap_token_max_reg[] = {
+	{ "cfgmt_sashap_token_max", DPP_FIELD_FLAG_RW, 31, 32, 0x2000, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_sashap_token_min_reg[] = {
+	{ "cfgmt_sashap_token_min", DPP_FIELD_FLAG_RW, 31, 32, 0xffffe000, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_q3lbaddrate_reg[] = {
+	{ "cfg_qsch_q3lbaddrate", DPP_FIELD_FLAG_RW, 27, 28, 0x80, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_q012lbaddrate_reg[] = {
+	{ "cfg_qsch_q012lbaddrate", DPP_FIELD_FLAG_RW, 27, 28, 0x80, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_q3creditlbmaxcnt_reg[] = {
+	{ "cfg_qsch_q3creditlbmaxcnt", DPP_FIELD_FLAG_RW, 7, 8, 0x80, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_q012creditlbmaxcnt_reg[] = {
+	{ "cfg_qsch_q012creditlbmaxcnt", DPP_FIELD_FLAG_RW, 7, 8, 0x80, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mul_token_gen_num_reg[] = {
+	{ "cfg_qsch_mul_token_gen_num", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_q3_credit_lb_control_en_reg[] = {
+	{ "cfg_qsch_q3_credit_lb_control_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_q012_credit_lb_control_en_reg[] = {
+	{ "cfg_qsch_q012_credit_lb_control_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_sp_dwrr_en_reg[] = {
+	{ "cfg_qsch_sp_dwrr_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_q01_attach_en_reg[] = {
+	{ "cfg_qsch_q01_attach_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_w0_reg[] = {
+	{ "cfg_qsch_w0", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_w1_reg[] = {
+	{ "cfg_qsch_w1", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_w2_reg[] = {
+	{ "cfg_qsch_w2", DPP_FIELD_FLAG_RW, 6, 7, 0x40, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktmaxcnt1_reg[] = {
+	{ "cfg_qsch_lkybktmaxcnt1", DPP_FIELD_FLAG_RW, 31, 32, 0x80, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktmaxcnt2_reg[] = {
+	{ "cfg_qsch_lkybktmaxcnt2", DPP_FIELD_FLAG_RW, 31, 32, 0x80, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktdcrrate1_reg[] = {
+	{ "cfg_qsch_lkybktdcrrate1", DPP_FIELD_FLAG_RW, 31, 32, 0x80000020, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktdcrrate2_reg[] = {
+	{ "cfg_qsch_lkybktdcrrate2", DPP_FIELD_FLAG_RW, 31, 32, 0x80000010, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktdcrrate3_reg[] = {
+	{ "cfg_qsch_lkybktdcrrate3", DPP_FIELD_FLAG_RW, 31, 32, 0x80000004, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybktmaxcnt3_reg[] = {
+	{ "cfg_qsch_lkybktmaxcnt3", DPP_FIELD_FLAG_RW, 31, 32, 0x80, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_qmu_mul_auto_sa_version_reg[] = {
+	{ "cfg_qsch_qmu_mul_auto_sa_version", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_0_reg[] = {
+	{ "cfg_qsch_sa_credit_value_0", DPP_FIELD_FLAG_RW, 13, 14, 0x85, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_1_reg[] = {
+	{ "cfg_qsch_sa_credit_value_1", DPP_FIELD_FLAG_RW, 13, 14, 0x29a, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_2_reg[] = {
+	{ "cfg_qsch_sa_credit_value_2", DPP_FIELD_FLAG_RW, 13, 14, 0x190, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_3_reg[] = {
+	{ "cfg_qsch_sa_credit_value_3", DPP_FIELD_FLAG_RW, 13, 14, 0x4e2, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_4_reg[] = {
+	{ "cfg_qsch_sa_credit_value_4", DPP_FIELD_FLAG_RW, 13, 14, 0x5fe, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_5_reg[] = {
+	{ "cfg_qsch_sa_credit_value_5", DPP_FIELD_FLAG_RW, 13, 14, 0x8a0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_6_reg[] = {
+	{ "cfg_qsch_sa_credit_value_6", DPP_FIELD_FLAG_RW, 13, 14, 0x8a0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_sa_credit_value_7_reg[] = {
+	{ "cfg_qsch_sa_credit_value_7", DPP_FIELD_FLAG_RW, 13, 14, 0x8a0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_remote_credit_fifo_almost_full_th_reg[] = {
+	{ "cfg_qsch_remote_credit_fifo_almost_full_th", DPP_FIELD_FLAG_RW, 10, 11,
+	  0x7ff, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_auto_credit_fifo_almost_full_th_reg[] = {
+	{ "cfg_qsch_auto_credit_fifo_almost_full_th", DPP_FIELD_FLAG_RW, 5, 6, 0x1c,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_q3_credit_fifo_almost_full_th_reg[] = {
+	{ "cfg_qsch_q3_credit_fifo_almost_full_th", DPP_FIELD_FLAG_RW, 5, 6, 0x1c,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_q012_credit_fifo_almost_full_th_reg[] = {
+	{ "cfg_qsch_q012_credit_fifo_almost_full_th", DPP_FIELD_FLAG_RW, 5, 6, 0x1c,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mul_fc_res_en_reg[] = {
+	{ "cfg_qsch_mul_fc_res_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_mul_ovf_udf_flg_query_reg[] = {
+	{ "qsch_cfg_remote_credit_fifo_full", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0 },
+	{ "qsch_cfg_remote_credit_fifo_empty", DPP_FIELD_FLAG_RO, 17, 1, 0x1, 0x0 },
+	{ "qsch_cfg_remote_credit_fifo_overflow", DPP_FIELD_FLAG_RO, 16, 1, 0x0,
+	  0x0 },
+	{ "qsch_cfg_remote_credit_fifo_underflow", DPP_FIELD_FLAG_RO, 15, 1, 0x0,
+	  0x0 },
+	{ "qsch_cfg_auto_credit_fifo_full", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0 },
+	{ "qsch_cfg_auto_credit_fifo_empty", DPP_FIELD_FLAG_RO, 13, 1, 0x1, 0x0 },
+	{ "qsch_cfg_auto_credit_fifo_overflow", DPP_FIELD_FLAG_RO, 12, 1, 0x0,
+	  0x0 },
+	{ "qsch_cfg_auto_credit_fifo_underflow", DPP_FIELD_FLAG_RO, 11, 1, 0x0,
+	  0x0 },
+	{ "qsch_cfg_q3_credit_fifo_full", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0 },
+	{ "qsch_cfg_q3_credit_fifo_empty", DPP_FIELD_FLAG_RO, 9, 1, 0x1, 0x0 },
+	{ "qsch_cfg_q3_credit_fifo_overflow", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0 },
+	{ "qsch_cfg_q3_credit_fifo_underflow", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "qsch_cfg_q012_credit_fifo_full", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "qsch_cfg_q012_credit_fifo_empty", DPP_FIELD_FLAG_RO, 5, 1, 0x1, 0x0 },
+	{ "qsch_cfg_q012_credit_fifo_overflow", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "qsch_cfg_q012_credit_fifo_underflow", DPP_FIELD_FLAG_RO, 3, 1, 0x0,
+	  0x0 },
+	{ "qsch_cfg_lkybktoverflow1", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "qsch_cfg_lkybktoverflow2", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "qsch_cfg_lkybktoverflow3", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_mul_cng_flg_query_reg[] = {
+	{ "qsch_cfg_q3cngflag", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "qsch_cfg_q012cngflag", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "qsch_cfg_cngflag1", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "qsch_cfg_cngflag2", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "qsch_cfg_cngflag3", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qsch_cfg_lkybktval1_reg[] = {
+	{ "qsch_cfg_lkybktval1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qsch_cfg_lkybktval2_reg[] = {
+	{ "qsch_cfg_lkybktval2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qsch_cfg_lkybktval3_reg[] = {
+	{ "qsch_cfg_lkybktval3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qsch_cfg_q3lbval_reg[] = {
+	{ "qsch_cfg_q3lbval", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qsch_cfg_q012lbval_reg[] = {
+	{ "qsch_cfg_q012lbval", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qlist_cfgmt_ram_ecc_err2_reg[] = {
+	{ "qlist_imem_pd_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "qlist_imem_pd_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "qlist_imem_up_ptr_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0,
+	  0x0 },
+	{ "qlist_imem_up_ptr_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0,
+	  0x0 },
+	{ "qlist_imem_down_ptr_ram_single_ecc_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0,
+	  0x0 },
+	{ "qlist_imem_down_ptr_ram_double_ecc_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0,
+	  0x0 },
+	{ "cmdsw_sop_fifo_single_ecc_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "cmdsw_sop_fifo_double_ecc_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "cmdsw_nsop_fifo_single_ecc_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "cmdsw_nsop_fifo_double_ecc_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "cmdsw_mmudat_fifo_single_ecc_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "cmdsw_mmudat_fifo_double_ecc_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "qlist_rd_release_fwft_single_ecc_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0,
+	  0x0 },
+	{ "qlist_rd_release_fwft_double_ecc_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0,
+	  0x0 },
+	{ "qlist_drop_imem_fwft_single_ecc_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0,
+	  0x0 },
+	{ "qlist_drop_imem_fwft_double_ecc_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csch_aged_cmd_cnt_reg[] = {
+	{ "csch_aged_cmd_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csch_qcfg_csch_congest_cnt_reg[] = {
+	{ "csch_qcfg_csch_congest_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csch_qcfg_qlist_csch_sop_cnt_reg[] = {
+	{ "csch_qcfg_qlist_csch_sop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csch_qcfg_qlist_csch_eop_cnt_reg[] = {
+	{ "csch_qcfg_qlist_csch_eop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csch_qcfg_csch_csw_sop_cnt_reg[] = {
+	{ "csch_qcfg_csch_csw_sop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csch_qcfg_csch_csw_eop_cnt_reg[] = {
+	{ "csch_qcfg_csch_csw_eop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csch_qcfg_qlist_csch_drop_cnt_reg[] = {
+	{ "csch_qcfg_qlist_csch_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csch_qcfg_csch_csw_drop_cnt_reg[] = {
+	{ "csch_qcfg_csch_csw_drop_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csw_mmu_sop_cmd_cnt_reg[] = {
+	{ "csw_mmu_sop_cmd_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_mmu_csw_sop_data_cnt_reg[] = {
+	{ "mmu_csw_sop_data_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csw_qsch_feedb_cnt_reg[] = {
+	{ "csw_qsch_feedb_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_crdt_port_fc_cnt_reg[] = {
+	{ "qmu_crdt_port_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_csch_r_block_cnt_reg[] = {
+	{ "csch_r_block_cnt", DPP_FIELD_FLAG_RO, 16, 17, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_qds_head_rd_reg[] = {
+	{ "qcfg_qlist_qds_head_rd", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_qds_tail_rd_reg[] = {
+	{ "qcfg_qlist_qds_tail_rd", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_ept_rd_reg[] = {
+	{ "qcfg_qlist_ept_rd", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_age_flag_rd_reg[] = {
+	{ "qcfg_qlist_age_flag_rd", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_cti_rd_reg[] = {
+	{ "qcfg_qlist_cti_rd", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_cto_rd_reg[] = {
+	{ "qcfg_qlist_cto_rd", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_chk_rd_reg[] = {
+	{ "qcfg_qlist_chk_rd", DPP_FIELD_FLAG_RO, 18, 19, 0x1, 0x1 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_nod_rd_reg[] = {
+	{ "qcfg_qlist_nod_rd", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_qlist_biu_rd_reg[] = {
+	{ "qcfg_qlist_biu_rd", DPP_FIELD_FLAG_RO, 4, 5, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qsch_r_wlist_flag_reg[] = {
+	{ "qsch_r_wlist_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qcfg_crs_flg_rd_reg[] = {
+	{ "qcfg_crs_flg_rd", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_age_qds_reg[] = {
+	{ "cfgmt_qmu_imem_tp", DPP_FIELD_FLAG_RO, 30, 15, 0x0, 0x0 },
+	{ "cfgmt_qmu_imem_hp", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_age_qlen_reg[] = {
+	{ "cfgmt_qmu_imem_no_empty", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0 },
+	{ "cfgmt_qmu_imem_qlen", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_pd_ram_low_reg[] = {
+	{ "cfgmt_qmu_imem_pd_ram_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_pd_ram_high_reg[] = {
+	{ "cfgmt_qmu_imem_pd_ram_high", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_up_ptr_reg[] = {
+	{ "cfgmt_qmu_imem_up_ptr", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_down_ptr_reg[] = {
+	{ "cfgmt_qmu_imem_down_ptr", DPP_FIELD_FLAG_RO, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfgmt_qmu_imem_age_flag_reg[] = {
+	{ "cfgmt_qmu_imem_age_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybkt2cngth_reg[] = {
+	{ "cfg_qsch_lkybkt2cngth", DPP_FIELD_FLAG_RW, 31, 32, 0x40, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybkt1cngth_reg[] = {
+	{ "cfg_qsch_lkybkt1cngth", DPP_FIELD_FLAG_RW, 31, 32, 0x40, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_lkybkt3cngth_reg[] = {
+	{ "cfg_qsch_lkybkt3cngth", DPP_FIELD_FLAG_RW, 31, 32, 0x40, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn1_credit_value_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn1_credit_value", DPP_FIELD_FLAG_RW, 13, 14, 0x5fe,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn2_credit_value_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn2_credit_value", DPP_FIELD_FLAG_RW, 13, 14, 0x5fe,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn3_credit_value_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn3_credit_value", DPP_FIELD_FLAG_RW, 13, 14, 0x5fe,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_ansr_seed_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn1_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0,
+	  0x0 },
+	{ "cfg_qsch_rm_mul_mcn1_rand_ansr_seed", DPP_FIELD_FLAG_RW, 7, 8, 0x1,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_ansr_seed_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn2_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0,
+	  0x0 },
+	{ "cfg_qsch_rm_mul_mcn2_rand_ansr_seed", DPP_FIELD_FLAG_RW, 7, 8, 0x1,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_ansr_seed_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn3_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0,
+	  0x0 },
+	{ "cfg_qsch_rm_mul_mcn3_rand_ansr_seed", DPP_FIELD_FLAG_RW, 7, 8, 0x1,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_ansr_th_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn1_rand_ansr_th", DPP_FIELD_FLAG_RW, 7, 8, 0x80, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_ansr_th_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn2_rand_ansr_th", DPP_FIELD_FLAG_RW, 7, 8, 0x80, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_ansr_th_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn3_rand_ansr_th", DPP_FIELD_FLAG_RW, 7, 8, 0x80, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_hold_base_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn1_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x1,
+	  0x0 },
+	{ "cfg_qsch_rm_mul_mcn1_rand_hold_base", DPP_FIELD_FLAG_RW, 23, 24, 0x1000,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_hold_base_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn2_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x1,
+	  0x0 },
+	{ "cfg_qsch_rm_mul_mcn2_rand_hold_base", DPP_FIELD_FLAG_RW, 23, 24, 0x1000,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_hold_base_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn3_rand_mchsm_en", DPP_FIELD_FLAG_RW, 31, 1, 0x1,
+	  0x0 },
+	{ "cfg_qsch_rm_mul_mcn3_rand_hold_base", DPP_FIELD_FLAG_RW, 23, 24, 0x1000,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_sel_mask_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn1_rand_sel_mask", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_sel_mask_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn2_rand_sel_mask", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_sel_mask_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn3_rand_sel_mask", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg0_reg[] = {
+	{ "rm_mul_mcn1_rand_sel_seed7", DPP_FIELD_FLAG_RW, 31, 4, 0x8, 0x0 },
+	{ "rm_mul_mcn1_rand_sel_seed6", DPP_FIELD_FLAG_RW, 27, 4, 0x7, 0x0 },
+	{ "rm_mul_mcn1_rand_sel_seed5", DPP_FIELD_FLAG_RW, 23, 4, 0x6, 0x0 },
+	{ "rm_mul_mcn1_rand_sel_seed4", DPP_FIELD_FLAG_RW, 19, 4, 0x5, 0x0 },
+	{ "rm_mul_mcn1_rand_sel_seed3", DPP_FIELD_FLAG_RW, 15, 4, 0x4, 0x0 },
+	{ "rm_mul_mcn1_rand_sel_seed2", DPP_FIELD_FLAG_RW, 11, 4, 0x3, 0x0 },
+	{ "rm_mul_mcn1_rand_sel_seed1", DPP_FIELD_FLAG_RW, 7, 4, 0x2, 0x0 },
+	{ "rm_mul_mcn1_rand_sel_seed0", DPP_FIELD_FLAG_RW, 3, 4, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg1_reg[] = {
+	{ "rm_mul_mcn1_rand_sel_seed8", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg0_reg[] = {
+	{ "rm_mul_mcn2_rand_sel_seed7", DPP_FIELD_FLAG_RW, 31, 4, 0x8, 0x0 },
+	{ "rm_mul_mcn2_rand_sel_seed6", DPP_FIELD_FLAG_RW, 27, 4, 0x7, 0x0 },
+	{ "rm_mul_mcn2_rand_sel_seed5", DPP_FIELD_FLAG_RW, 23, 4, 0x6, 0x0 },
+	{ "rm_mul_mcn2_rand_sel_seed4", DPP_FIELD_FLAG_RW, 19, 4, 0x5, 0x0 },
+	{ "rm_mul_mcn2_rand_sel_seed3", DPP_FIELD_FLAG_RW, 15, 4, 0x4, 0x0 },
+	{ "rm_mul_mcn2_rand_sel_seed2", DPP_FIELD_FLAG_RW, 11, 4, 0x3, 0x0 },
+	{ "rm_mul_mcn2_rand_sel_seed1", DPP_FIELD_FLAG_RW, 7, 4, 0x2, 0x0 },
+	{ "rm_mul_mcn2_rand_sel_seed0", DPP_FIELD_FLAG_RW, 3, 4, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg1_reg[] = {
+	{ "rm_mul_mcn2_rand_sel_seed8", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg0_reg[] = {
+	{ "rm_mul_mcn3_rand_sel_seed7", DPP_FIELD_FLAG_RW, 31, 4, 0x8, 0x0 },
+	{ "rm_mul_mcn3_rand_sel_seed6", DPP_FIELD_FLAG_RW, 27, 4, 0x7, 0x0 },
+	{ "rm_mul_mcn3_rand_sel_seed5", DPP_FIELD_FLAG_RW, 23, 4, 0x6, 0x0 },
+	{ "rm_mul_mcn3_rand_sel_seed4", DPP_FIELD_FLAG_RW, 19, 4, 0x5, 0x0 },
+	{ "rm_mul_mcn3_rand_sel_seed3", DPP_FIELD_FLAG_RW, 15, 4, 0x4, 0x0 },
+	{ "rm_mul_mcn3_rand_sel_seed2", DPP_FIELD_FLAG_RW, 11, 4, 0x3, 0x0 },
+	{ "rm_mul_mcn3_rand_sel_seed1", DPP_FIELD_FLAG_RW, 7, 4, 0x2, 0x0 },
+	{ "rm_mul_mcn3_rand_sel_seed0", DPP_FIELD_FLAG_RW, 3, 4, 0x1, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg1_reg[] = {
+	{ "rm_mul_mcn3_rand_sel_seed8", DPP_FIELD_FLAG_RW, 3, 4, 0x9, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th1_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn1_step_wait_th1", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th2_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn1_step_wait_th2", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th3_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn1_step_wait_th3", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th4_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn1_step_wait_th4", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th5_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn1_step_wait_th5", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th6_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn1_step_wait_th6", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn1_step_wait_th7_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn1_step_wait_th7", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th1_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn2_step_wait_th1", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th2_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn2_step_wait_th2", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th3_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn2_step_wait_th3", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th4_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn2_step_wait_th4", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th5_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn2_step_wait_th5", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th6_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn2_step_wait_th6", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn2_step_wait_th7_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn2_step_wait_th7", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th1_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn3_step_wait_th1", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th2_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn3_step_wait_th2", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th3_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn3_step_wait_th3", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th4_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn3_step_wait_th4", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th5_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn3_step_wait_th5", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn3_step_wait_th6_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn3_step_wait_th6", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_rm_mul_mcn3step_wait_th7_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn3_step_wait_th7", DPP_FIELD_FLAG_RW, 15, 16, 0x80,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate0_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate0", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate1_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate1", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate2_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate2", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate3_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate3", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate4_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate4", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate5_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate5", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate6_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate6", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate7_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate7", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate8_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate8", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate9_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate9", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate10_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate10", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate11_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate11", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate12_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate12", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate13_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate13", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate14_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate14", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate15_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate15", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate16_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate16", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate17_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate17", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate18_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate18", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate19_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate19", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate20_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate20", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate21_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate21", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate22_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate22", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate23_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate23", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate24_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate24", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate25_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate25", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate26_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate26", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate27_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate27", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate28_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate28", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate29_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate29", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate30_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate30", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate31_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate31", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate32_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate32", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate33_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate33", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate34_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate34", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate35_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate35", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_mulcrdcntrate36_reg[] = {
+	{ "cfg_qsch_mulcrdcntrate36", DPP_FIELD_FLAG_RW, 19, 20, 0x100, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn1_rand_hold_shift_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn1_rand_hold_shift", DPP_FIELD_FLAG_RW, 2, 3, 0x7,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn2_rand_hold_shift_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn2_rand_hold_shift", DPP_FIELD_FLAG_RW, 2, 3, 0x7,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_cfg_qsch_rm_mul_mcn3_rand_hold_shift_reg[] = {
+	{ "cfg_qsch_rm_mul_mcn3_rand_hold_shift", DPP_FIELD_FLAG_RW, 2, 3, 0x7,
+	  0x0 },
+};
+DPP_FIELD_T g_etm_qmu_last_drop_qnum_get_reg[] = {
+	{ "cgavd_qmu_drop_tap", DPP_FIELD_FLAG_RC, 31, 4, 0x0, 0x0 },
+	{ "last_drop_qnum", DPP_FIELD_FLAG_RC, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_crdt_qmu_credit_cnt_reg[] = {
+	{ "crdt_qmu_credit_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_to_qsch_report_cnt_reg[] = {
+	{ "qmu_to_qsch_report_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_to_cgavd_report_cnt_reg[] = {
+	{ "qmu_to_cgavd_report_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_crdt_crs_normal_cnt_reg[] = {
+	{ "qmu_crdt_crs_normal_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_crdt_crs_off_cnt_reg[] = {
+	{ "qmu_crdt_crs_off_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qsch_qlist_shedule_cnt_reg[] = {
+	{ "qsch_qlist_shedule_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qsch_qlist_sch_ept_cnt_reg[] = {
+	{ "qsch_qlist_sch_ept_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_to_mmu_blk_wr_cnt_reg[] = {
+	{ "qmu_to_mmu_blk_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_to_csw_blk_rd_cnt_reg[] = {
+	{ "qmu_to_csw_blk_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_to_mmu_sop_wr_cnt_reg[] = {
+	{ "qmu_to_mmu_sop_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_to_mmu_eop_wr_cnt_reg[] = {
+	{ "qmu_to_mmu_eop_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_to_mmu_drop_wr_cnt_reg[] = {
+	{ "qmu_to_mmu_drop_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_to_csw_sop_rd_cnt_reg[] = {
+	{ "qmu_to_csw_sop_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_to_csw_eop_rd_cnt_reg[] = {
+	{ "qmu_to_csw_eop_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_qmu_to_csw_drop_rd_cnt_reg[] = {
+	{ "qmu_to_csw_drop_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_mmu_to_qmu_wr_release_cnt_reg[] = {
+	{ "mmu_to_qmu_wr_release_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_mmu_to_qmu_rd_release_cnt_reg[] = {
+	{ "mmu_to_qmu_rd_release_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_observe_qnum_set_reg[] = {
+	{ "observe_qnum_set", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_q_pkt_received_reg[] = {
+	{ "spec_q_pkt_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_q_pkt_dropped_reg[] = {
+	{ "spec_q_pkt_dropped", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_q_pkt_scheduled_reg[] = {
+	{ "spec_q_pkt_scheduled", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_q_wr_cmd_sent_reg[] = {
+	{ "spec_q_wr_cmd_sent", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_q_rd_cmd_sent_reg[] = {
+	{ "spec_q_rd_cmd_sent", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_q_pkt_enq_reg[] = {
+	{ "spec_q_pkt_enq", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_q_pkt_deq_reg[] = {
+	{ "spec_q_pkt_deq", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_q_crdt_uncon_received_reg[] = {
+	{ "spec_q_crdt_uncon_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_q_crdt_cong_received_reg[] = {
+	{ "spec_q_crdt_cong_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_q_crs_normal_cnt_reg[] = {
+	{ "spec_q_crs_normal_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_q_crs_off_cnt_reg[] = {
+	{ "spec_q_crs_off_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_observe_batch_set_reg[] = {
+	{ "observe_batch_set", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_bat_pkt_received_reg[] = {
+	{ "spec_bat_pkt_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_bat_pkt_dropped_reg[] = {
+	{ "spec_bat_pkt_dropped", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_bat_blk_scheduled_reg[] = {
+	{ "spec_bat_blk_scheduled", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_bat_wr_cmd_sent_reg[] = {
+	{ "spec_bat_wr_cmd_sent", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_bat_rd_cmd_sent_reg[] = {
+	{ "spec_bat_rd_cmd_sent", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_bat_pkt_enq_reg[] = {
+	{ "spec_bat_pkt_enq", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_bat_pkt_deq_reg[] = {
+	{ "spec_bat_pkt_deq", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_bat_crdt_uncon_received_reg[] = {
+	{ "spec_bat_crdt_uncon_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_bat_crdt_cong_received_reg[] = {
+	{ "spec_bat_crdt_cong_received", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_bat_crs_normal_cnt_reg[] = {
+	{ "spec_bat_crs_normal_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_bat_crs_off_cnt_reg[] = {
+	{ "spec_bat_crs_off_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_bcntm_ovfl_qnum_get_reg[] = {
+	{ "bcntm_ovfl_qnum_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_crbal_a_ovf_qnum_get_reg[] = {
+	{ "crbal_a_ovf_qnum_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_crbal_b_ovf_qnum_get_reg[] = {
+	{ "crbal_b_ovf_qnum_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_crbal_drop_qnum_get_reg[] = {
+	{ "crbal_drop_qnum_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_deq_flg_report_cnt_reg[] = {
+	{ "deq_flg_report_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_q_crs_get_reg[] = {
+	{ "spec_q_crs_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_q_crs_in_get_reg[] = {
+	{ "spec_q_crs_in_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_spec_q_crs_flg_csol_get_reg[] = {
+	{ "spec_q_crs_flg_csol_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_etm_qmu_ept_sch_qnum_get_reg[] = {
+	{ "ept_sch_qnum_get", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_pcie_ddr_switch_reg[] = {
+	{ "pcie_ddr_switch", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_user0_int_en_reg[] = {
+	{ "user_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_user0_int_mask_reg[] = {
+	{ "user_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_user0_int_status_reg[] = {
+	{ "user_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_user1_int_en_reg[] = {
+	{ "user_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_user1_int_mask_reg[] = {
+	{ "user_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_user1_int_status_reg[] = {
+	{ "user_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_user2_int_en_reg[] = {
+	{ "user_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_user2_int_mask_reg[] = {
+	{ "user_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_user2_int_status_reg[] = {
+	{ "user_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_ecc_1b_int_en_reg[] = {
+	{ "ecc_1b_int_en", DPP_FIELD_FLAG_RW, 2, 3, 0xfffff, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_ecc_1b_int_mask_reg[] = {
+	{ "ecc_1b_int_mask", DPP_FIELD_FLAG_RW, 2, 3, 0xfffff, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_ecc_1b_int_status_reg[] = {
+	{ "ecc_1b_int_status", DPP_FIELD_FLAG_RC, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_ecc_2b_int_en_reg[] = {
+	{ "ecc_2b_int_en", DPP_FIELD_FLAG_RW, 2, 3, 0xfffff, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_ecc_2b_int_mask_reg[] = {
+	{ "ecc_2b_int_mask", DPP_FIELD_FLAG_RW, 2, 3, 0xfffff, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_ecc_2b_int_status_reg[] = {
+	{ "ecc_2b_int_status", DPP_FIELD_FLAG_RC, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_cfg_int_status_reg[] = {
+	{ "cfg_int_status", DPP_FIELD_FLAG_RC, 4, 5, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_i_core_to_cntl_reg[] = {
+	{ "i_core_to_cntl", DPP_FIELD_FLAG_RW, 15, 16, 0xaaaa, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_in_low_reg[] = {
+	{ "test_in_low", DPP_FIELD_FLAG_RW, 31, 32, 0x00004000, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_in_high_reg[] = {
+	{ "test_in_high", DPP_FIELD_FLAG_RW, 31, 32, 0x00000000, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_local_interrupt_out_reg[] = {
+	{ "local_interrupt_out", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_pl_ltssm_reg[] = {
+	{ "pl_ltssm", DPP_FIELD_FLAG_RO, 4, 5, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out0_reg[] = {
+	{ "test_out0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out1_reg[] = {
+	{ "test_out1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out2_reg[] = {
+	{ "test_out2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out3_reg[] = {
+	{ "test_out3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out4_reg[] = {
+	{ "test_out4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out5_reg[] = {
+	{ "test_out5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out6_reg[] = {
+	{ "test_out6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out7_reg[] = {
+	{ "test_out7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_sync_o_core_status_reg[] = {
+	{ "sync_o_core_status", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_sync_o_alert_dbe_reg[] = {
+	{ "sync_o_alert_dbe", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_sync_o_alert_sbe_reg[] = {
+	{ "sync_o_alert_sbe", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_sync_o_link_loopback_en_reg[] = {
+	{ "sync_o_link_loopback_en", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_sync_o_local_fs_lf_valid_reg[] = {
+	{ "sync_o_local_fs_lf_valid", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_sync_o_rx_idle_detect_reg[] = {
+	{ "sync_o_rx_idle_detect", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_sync_o_rx_rdy_reg[] = {
+	{ "sync_o_rx_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_sync_o_tx_rdy_reg[] = {
+	{ "sync_o_tx_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_pcie_link_up_cnt_reg[] = {
+	{ "pcie_link_up_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out_pcie0_reg[] = {
+	{ "test_out_pcie0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out_pcie1_reg[] = {
+	{ "test_out_pcie1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out_pcie2_reg[] = {
+	{ "test_out_pcie2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out_pcie3_reg[] = {
+	{ "test_out_pcie3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out_pcie4_reg[] = {
+	{ "test_out_pcie4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out_pcie5_reg[] = {
+	{ "test_out_pcie5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out_pcie6_reg[] = {
+	{ "test_out_pcie6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out_pcie7_reg[] = {
+	{ "test_out_pcie7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out_pcie8_reg[] = {
+	{ "test_out_pcie8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out_pcie9_reg[] = {
+	{ "test_out_pcie9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out_pcie10_reg[] = {
+	{ "test_out_pcie10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out_pcie11_reg[] = {
+	{ "test_out_pcie11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out_pcie12_reg[] = {
+	{ "test_out_pcie12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out_pcie13_reg[] = {
+	{ "test_out_pcie13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out_pcie14_reg[] = {
+	{ "test_out_pcie14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_test_out_pcie15_reg[] = {
+	{ "test_out_pcie15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_int_repeat_en_reg[] = {
+	{ "int_repeat_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_awid_axi_mst_reg[] = {
+	{ "dbg_awid_axi_mst", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_awaddr_axi_mst0_reg[] = {
+	{ "dbg_awaddr_axi_mst0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_awaddr_axi_mst1_reg[] = {
+	{ "dbg_awaddr_axi_mst1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_awlen_axi_mst_reg[] = {
+	{ "dbg_awlen_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_awsize_axi_mst_reg[] = {
+	{ "dbg_awid_axi_mst", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_awburst_axi_mst_reg[] = {
+	{ "dbg_awburst_axi_mst", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_awlock_axi_mst_reg[] = {
+	{ "dbg_awlock_axi_mst", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_awcache_axi_mst_reg[] = {
+	{ "dbg_awcache_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_awprot_axi_mst_reg[] = {
+	{ "dbg_awprot_axi_mst", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_wid_axi_mst_reg[] = {
+	{ "dbg_wid_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_wdata_axi_mst0_reg[] = {
+	{ "dbg_wdata_axi_mst0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_wdata_axi_mst1_reg[] = {
+	{ "dbg_wdata_axi_mst1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_wdata_axi_mst2_reg[] = {
+	{ "dbg_wdata_axi_mst2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_wdata_axi_mst3_reg[] = {
+	{ "dbg_wdata_axi_mst3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_wstrb_axi_mst_reg[] = {
+	{ "dbg_wstrb_axi_mst", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_wlast_axi_mst_reg[] = {
+	{ "dbg_wlast_axi_mst", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_arid_axi_mst_reg[] = {
+	{ "dbg_arid_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_araddr_axi_mst0_reg[] = {
+	{ "dbg_araddr_axi_mst0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_araddr_axi_mst1_reg[] = {
+	{ "dbg_araddr_axi_mst1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_arlen_axi_mst_reg[] = {
+	{ "dbg_arlen_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_arsize_axi_mst_reg[] = {
+	{ "dbg_arsize_axi_mst", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_arburst_axi_mst_reg[] = {
+	{ "dbg_arburst_axi_mst", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_arlock_axi_mst_reg[] = {
+	{ "dbg_arlock_axi_mst", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_arcache_axi_mst_reg[] = {
+	{ "dbg_arcache_axi_mst", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_arprot_axi_mst_reg[] = {
+	{ "dbg_arprot_axi_mst", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_rdata_axi_mst0_reg[] = {
+	{ "dbg_rdata_axi_mst0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_rdata_axi_mst1_reg[] = {
+	{ "dbg_rdata_axi_mst1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_rdata_axi_mst2_reg[] = {
+	{ "dbg_rdata_axi_mst2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_rdata_axi_mst3_reg[] = {
+	{ "dbg_rdata_axi_mst3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_axi_mst_state_reg[] = {
+	{ "axi_mst_state", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_axi_cfg_state_reg[] = {
+	{ "axi_cfg_state", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_axi_slv_rd_state_reg[] = {
+	{ "axi_slv_rd_state", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_axi_slv_wr_state_reg[] = {
+	{ "axi_slv_wr_state", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_axim_delay_en_reg[] = {
+	{ "axim_delay_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_axim_delay_reg[] = {
+	{ "axim_delay", DPP_FIELD_FLAG_RW, 31, 32, 0xff, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_axim_speed_wr_reg[] = {
+	{ "axim_speed_wr", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_axim_speed_rd_reg[] = {
+	{ "axim_speed_rd", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_awaddr_axi_slv0_reg[] = {
+	{ "dbg_awaddr_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_awaddr_axi_slv1_reg[] = {
+	{ "dbg_awaddr_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg0_wdata_axi_slv0_reg[] = {
+	{ "dbg0_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg0_wdata_axi_slv1_reg[] = {
+	{ "dbg0_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg0_wdata_axi_slv2_reg[] = {
+	{ "dbg0_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg0_wdata_axi_slv3_reg[] = {
+	{ "dbg0_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg1_wdata_axi_slv0_reg[] = {
+	{ "dbg1_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg1_wdata_axi_slv1_reg[] = {
+	{ "dbg1_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg1_wdata_axi_slv2_reg[] = {
+	{ "dbg1_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg1_wdata_axi_slv3_reg[] = {
+	{ "dbg1_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg2_wdata_axi_slv0_reg[] = {
+	{ "dbg2_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg2_wdata_axi_slv1_reg[] = {
+	{ "dbg2_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg2_wdata_axi_slv2_reg[] = {
+	{ "dbg2_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg2_wdata_axi_slv3_reg[] = {
+	{ "dbg2_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg3_wdata_axi_slv0_reg[] = {
+	{ "dbg3_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg3_wdata_axi_slv1_reg[] = {
+	{ "dbg3_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg3_wdata_axi_slv2_reg[] = {
+	{ "dbg3_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg3_wdata_axi_slv3_reg[] = {
+	{ "dbg3_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg4_wdata_axi_slv0_reg[] = {
+	{ "dbg4_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg4_wdata_axi_slv1_reg[] = {
+	{ "dbg4_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg4_wdata_axi_slv2_reg[] = {
+	{ "dbg4_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg4_wdata_axi_slv3_reg[] = {
+	{ "dbg4_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg5_wdata_axi_slv0_reg[] = {
+	{ "dbg5_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg5_wdata_axi_slv1_reg[] = {
+	{ "dbg5_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg5_wdata_axi_slv2_reg[] = {
+	{ "dbg5_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg5_wdata_axi_slv3_reg[] = {
+	{ "dbg5_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg6_wdata_axi_slv0_reg[] = {
+	{ "dbg6_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg6_wdata_axi_slv1_reg[] = {
+	{ "dbg6_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg6_wdata_axi_slv2_reg[] = {
+	{ "dbg6_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg6_wdata_axi_slv3_reg[] = {
+	{ "dbg6_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg7_wdata_axi_slv0_reg[] = {
+	{ "dbg7_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg7_wdata_axi_slv1_reg[] = {
+	{ "dbg7_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg7_wdata_axi_slv2_reg[] = {
+	{ "dbg7_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg7_wdata_axi_slv3_reg[] = {
+	{ "dbg7_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg8_wdata_axi_slv0_reg[] = {
+	{ "dbg8_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg8_wdata_axi_slv1_reg[] = {
+	{ "dbg8_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg8_wdata_axi_slv2_reg[] = {
+	{ "dbg8_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg8_wdata_axi_slv3_reg[] = {
+	{ "dbg8_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg9_wdata_axi_slv0_reg[] = {
+	{ "dbg9_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg9_wdata_axi_slv1_reg[] = {
+	{ "dbg9_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg9_wdata_axi_slv2_reg[] = {
+	{ "dbg9_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg9_wdata_axi_slv3_reg[] = {
+	{ "dbg9_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_awlen_axi_slv_reg[] = {
+	{ "dbg_awlen_axi_slv", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_wlast_axi_slv_reg[] = {
+	{ "dbg_wlast_axi_slv", DPP_FIELD_FLAG_RO, 9, 10, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_araddr_axi_slv0_reg[] = {
+	{ "dbg5_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_araddr_axi_slv1_reg[] = {
+	{ "dbg5_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg0_rdata_axi_slv0_reg[] = {
+	{ "dbg5_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg0_rdata_axi_slv1_reg[] = {
+	{ "dbg6_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg0_rdata_axi_slv2_reg[] = {
+	{ "dbg6_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg0_rdata_axi_slv3_reg[] = {
+	{ "dbg6_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg1_rdata_axi_slv0_reg[] = {
+	{ "dbg6_wdata_axi_slv3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg1_rdata_axi_slv1_reg[] = {
+	{ "dbg7_wdata_axi_slv0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg1_rdata_axi_slv2_reg[] = {
+	{ "dbg7_wdata_axi_slv1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg1_rdata_axi_slv3_reg[] = {
+	{ "dbg7_wdata_axi_slv2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_pcie_dbg_rlast_axi_slv_reg[] = {
+	{ "dbg_rlast_axi_slv", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_enable_reg[] = {
+	{ "dma_enable", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_up_req_reg[] = {
+	{ "up_req", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_up_current_state_reg[] = {
+	{ "dma_up_current_state", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_up_req_ack_reg[] = {
+	{ "dma_up_req_ack", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_done_latch_reg[] = {
+	{ "done_latch", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_up_cpu_addr_low32_reg[] = {
+	{ "dma_up_cpu_addr_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_up_cpu_addr_high32_reg[] = {
+	{ "dma_up_cpu_addr_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_up_se_addr_reg[] = {
+	{ "dma_up_se_addr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_done_int_reg[] = {
+	{ "dma_done_int", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_sp_cfg_reg[] = {
+	{ "sp_cfg", DPP_FIELD_FLAG_RW, 1, 2, 0x1, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_ing_reg[] = {
+	{ "dma_ing", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_rd_timeout_thresh_reg[] = {
+	{ "rd_timeout_thresh", DPP_FIELD_FLAG_RW, 31, 32, 0x7d0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_tab_sta_up_fifo_gap_reg[] = {
+	{ "dma_tab_sta_up_fifo_gap", DPP_FIELD_FLAG_RW, 8, 9, 0xfa, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_cfg_mac_tim_reg[] = {
+	{ "cfg_mac_tim", DPP_FIELD_FLAG_RW, 31, 32, 0x50, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_cfg_mac_num_reg[] = {
+	{ "cfg_mac_num", DPP_FIELD_FLAG_RW, 8, 9, 0x28, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_init_bd_addr_reg[] = {
+	{ "init_bd_addr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_mac_up_bd_addr1_low32_reg[] = {
+	{ "mac_up_bd_addr1_low32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_mac_up_bd_addr1_high32_reg[] = {
+	{ "mac_up_bd_addr1_high32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_mac_up_bd_addr2_low32_reg[] = {
+	{ "mac_up_bd_addr2_low32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_mac_up_bd_addr2_high32_reg[] = {
+	{ "mac_up_bd_addr2_high32", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_cfg_mac_max_num_reg[] = {
+	{ "cfg_mac_max_num", DPP_FIELD_FLAG_RW, 8, 9, 0x1ff, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_wbuf_ff_empty_reg[] = {
+	{ "dma_wbuf_ff_empty", DPP_FIELD_FLAG_RO, 1, 2, 0x3, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_wbuf_state_reg[] = {
+	{ "dma_wbuf_state", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_mac_bd_addr_low32_reg[] = {
+	{ "dma_mac_bd_addr_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_mac_bd_addr_high32_reg[] = {
+	{ "dma_mac_bd_addr_high32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_mac_up_enable_reg[] = {
+	{ "mac_up_enable", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_mac_endian_reg[] = {
+	{ "mac_endian", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_up_endian_reg[] = {
+	{ "up_endian", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_up_rd_cnt_latch_reg[] = {
+	{ "dma_up_rd_cnt_latch", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_up_rcv_cnt_latch_reg[] = {
+	{ "dma_up_rcv_cnt_latch", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_up_cnt_latch_reg[] = {
+	{ "dma_up_cnt_latch", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_cpu_rd_bd_pulse_reg[] = {
+	{ "cpu_rd_bd_pulse", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_cpu_bd_threshold_reg[] = {
+	{ "cpu_bd_threshold", DPP_FIELD_FLAG_RW, 31, 32, 0x64, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_cpu_bd_used_cnt_reg[] = {
+	{ "cpu_bd_used_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_up_rcv_status_reg[] = {
+	{ "dma_up_rcv_status", DPP_FIELD_FLAG_RO, 31, 32, 0x1, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_slv_rid_err_en_reg[] = {
+	{ "slv_rid_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_slv_rresp_err_en_reg[] = {
+	{ "slv_rresp_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_se_rdbk_ff_full_reg[] = {
+	{ "se_rdbk_ff_full", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_up_data_count_reg[] = {
+	{ "dma_up_data_count", DPP_FIELD_FLAG_RO, 9, 10, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_mwr_fifo_afull_gap_reg[] = {
+	{ "dma_mwr_fifo_afull_gap", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_info_fifo_afull_gap_reg[] = {
+	{ "dma_mwr_fifo_afull_gap", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_rd_timeout_set_reg[] = {
+	{ "dma_rd_timeout_set", DPP_FIELD_FLAG_RW, 31, 32, 0x3ffffff, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_bd_dat_err_en_reg[] = {
+	{ "dma_bd_dat_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_repeat_cnt_reg[] = {
+	{ "dma_repeat_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_rd_timeout_en_reg[] = {
+	{ "dma_rd_timeout_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_repeat_read_reg[] = {
+	{ "dma_repeat_read", DPP_FIELD_FLAG_RW, 31, 32, 0xa, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_repeat_read_en_reg[] = {
+	{ "dma_repeat_read_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_bd_ctl_state_reg[] = {
+	{ "bd_ctl_state", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_done_int_cnt_wr_reg[] = {
+	{ "dma_done_int_cnt_wr", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_done_int_cnt_mac_reg[] = {
+	{ "dma_done_int_cnt_mac", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_current_mac_num_reg[] = {
+	{ "current_mac_num", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_cfg_mac_afifo_afull_reg[] = {
+	{ "cfg_mac_afifo_afull", DPP_FIELD_FLAG_RW, 8, 9, 0xc8, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_dma_mac_ff_full_reg[] = {
+	{ "dma_mac_ff_full", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_dma_user_axi_mst_reg[] = {
+	{ "user_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "cfg_epid", DPP_FIELD_FLAG_RW, 27, 4, 0x0, 0x0 },
+	{ "cfg_vfunc_num", DPP_FIELD_FLAG_RW, 23, 8, 0x0, 0x0 },
+	{ "cfg_func_num", DPP_FIELD_FLAG_RW, 7, 3, 0x0, 0x0 },
+	{ "cfg_vfunc_active", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_sbus_state_reg[] = {
+	{ "sbus_state", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_en_reg[] = {
+	{ "mst_debug_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_sbus_command_sel_reg[] = {
+	{ "sbus_command_sel", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_soc_rd_time_out_thresh_reg[] = {
+	{ "soc_rd_time_out_thresh", DPP_FIELD_FLAG_RW, 31, 32, 0x2710, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_big_little_byte_order_reg[] = {
+	{ "big_little_byte_order", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_ecc_bypass_read_reg[] = {
+	{ "ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_ahb_async_wr_fifo_afull_gap_reg[] = {
+	{ "ahb_async_wr_fifo_afull_gap", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_ahb_async_rd_fifo_afull_gap_reg[] = {
+	{ "ahb_async_rd_fifo_afull_gap", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_ahb_async_cpl_fifo_afull_gap_reg[] = {
+	{ "ahb_async_cpl_fifo_afull_gap", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data0_high26_reg[] = {
+	{ "mst_debug_data0_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data0_low32_reg[] = {
+	{ "mst_debug_data0_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data1_high26_reg[] = {
+	{ "mst_debug_data1_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data1_low32_reg[] = {
+	{ "mst_debug_data1_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data2_high26_reg[] = {
+	{ "mst_debug_data2_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data2_low32_reg[] = {
+	{ "mst_debug_data2_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data3_high26_reg[] = {
+	{ "mst_debug_data3_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data3_low32_reg[] = {
+	{ "mst_debug_data3_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data4_high26_reg[] = {
+	{ "mst_debug_data4_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data4_low32_reg[] = {
+	{ "mst_debug_data4_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data5_high26_reg[] = {
+	{ "mst_debug_data5_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data5_low32_reg[] = {
+	{ "mst_debug_data5_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data6_high26_reg[] = {
+	{ "mst_debug_data6_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data6_low32_reg[] = {
+	{ "mst_debug_data6_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data7_high26_reg[] = {
+	{ "mst_debug_data7_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data7_low32_reg[] = {
+	{ "mst_debug_data7_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data8_high26_reg[] = {
+	{ "mst_debug_data8_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data8_low32_reg[] = {
+	{ "mst_debug_data8_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data9_high26_reg[] = {
+	{ "mst_debug_data9_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data9_low32_reg[] = {
+	{ "mst_debug_data9_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data10_high26_reg[] = {
+	{ "mst_debug_data10_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data10_low32_reg[] = {
+	{ "mst_debug_data10_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data11_high26_reg[] = {
+	{ "mst_debug_data11_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data11_low32_reg[] = {
+	{ "mst_debug_data11_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data12_high26_reg[] = {
+	{ "mst_debug_data12_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data12_low32_reg[] = {
+	{ "mst_debug_data12_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data13_high26_reg[] = {
+	{ "mst_debug_data13_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data13_low32_reg[] = {
+	{ "mst_debug_data13_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data14_high26_reg[] = {
+	{ "mst_debug_data14_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data14_low32_reg[] = {
+	{ "mst_debug_data14_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data15_high26_reg[] = {
+	{ "mst_debug_data15_high26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_cfg_csr_mst_debug_data15_low32_reg[] = {
+	{ "mst_debug_data15_low32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_ind_access_states_reg[] = {
+	{ "ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_ind_access_cmd0_reg[] = {
+	{ "wr_mode", DPP_FIELD_FLAG_RW, 29, 1, 0x0, 0x0 },
+	{ "rd_or_wr", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0 },
+	{ "ind_access_addr0", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_ind_access_data0_reg[] = {
+	{ "ind_access_data0", DPP_FIELD_FLAG_RW, 20, 21, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_ind_access_data1_reg[] = {
+	{ "ind_access_data1", DPP_FIELD_FLAG_RW, 20, 21, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_ind_access_cmd1_reg[] = {
+	{ "ind_access_addr1", DPP_FIELD_FLAG_RW, 16, 17, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_init_done_reg[] = {
+	{ "mr_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_cnt_mode_reg_reg[] = {
+	{ "cfgmt_count_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "cfgmt_count_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_cfg_ecc_bypass_read_reg[] = {
+	{ "cfg_ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_cfg_rep_mod_reg[] = {
+	{ "cfg_rep_mod", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_block_ptr_fifo_aful_th_reg[] = {
+	{ "block_ptr3_fifo_aful_th", DPP_FIELD_FLAG_RW, 31, 8, 0xa0, 0x0 },
+	{ "block_ptr2_fifo_aful_th", DPP_FIELD_FLAG_RW, 23, 8, 0xa0, 0x0 },
+	{ "block_ptr1_fifo_aful_th", DPP_FIELD_FLAG_RW, 15, 8, 0xa0, 0x0 },
+	{ "block_ptr0_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0xa0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_pre_rcv_ptr_fifo_aful_th_reg[] = {
+	{ "pre_rcv_ptr3_fifo_aful_th", DPP_FIELD_FLAG_RW, 31, 8, 0xa0, 0x0 },
+	{ "pre_rcv_ptr2_fifo_aful_th", DPP_FIELD_FLAG_RW, 23, 8, 0xa0, 0x0 },
+	{ "pre_rcv_ptr1_fifo_aful_th", DPP_FIELD_FLAG_RW, 15, 8, 0xa0, 0x0 },
+	{ "pre_rcv_ptr0_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0xa0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mgid_fifo_aful_th_reg[] = {
+	{ "mgid3_fifo_aful_th", DPP_FIELD_FLAG_RW, 31, 8, 0xa0, 0x0 },
+	{ "mgid2_fifo_aful_th", DPP_FIELD_FLAG_RW, 23, 8, 0xa0, 0x0 },
+	{ "mgid1_fifo_aful_th", DPP_FIELD_FLAG_RW, 15, 8, 0xa0, 0x0 },
+	{ "mgid0_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0xa0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_rep_cmd_fifo_aful_th_reg[] = {
+	{ "rep_cmd3_fifo_aful_th", DPP_FIELD_FLAG_RW, 31, 8, 0x14, 0x0 },
+	{ "rep_cmd2_fifo_aful_th", DPP_FIELD_FLAG_RW, 23, 8, 0x14, 0x0 },
+	{ "rep_cmd1_fifo_aful_th", DPP_FIELD_FLAG_RW, 15, 8, 0x14, 0x0 },
+	{ "rep_cmd0_fifo_aful_th", DPP_FIELD_FLAG_RW, 7, 8, 0x14, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_int_mask_1_reg[] = {
+	{ "free_ptr0_fifo_full_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "free_ptr1_fifo_full_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "free_ptr2_fifo_full_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "free_ptr3_fifo_full_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "block_ptr0_fifo_full_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "block_ptr1_fifo_full_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "block_ptr2_fifo_full_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "block_ptr3_fifo_full_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "mgid0_fifo_full_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "mgid1_fifo_full_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "mgid2_fifo_full_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "mgid3_fifo_full_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr0_fifo_full_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr1_fifo_full_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr2_fifo_full_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr3_fifo_full_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "rep_cmd0_fifo_full_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "rep_cmd1_fifo_full_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "rep_cmd2_fifo_full_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "rep_cmd3_fifo_full_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_int_mask_2_reg[] = {
+	{ "free_ptr0_fifo_udf_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "free_ptr1_fifo_udf_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "free_ptr2_fifo_udf_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "free_ptr3_fifo_udf_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "block_ptr0_fifo_udf_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "block_ptr1_fifo_udf_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "block_ptr2_fifo_udf_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "block_ptr3_fifo_udf_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "mgid0_fifo_udf_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "mgid1_fifo_udf_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "mgid2_fifo_udf_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "mgid3_fifo_udf_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr0_fifo_udf_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr1_fifo_udf_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr2_fifo_udf_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr3_fifo_udf_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "rep_cmd0_fifo_udf_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "rep_cmd1_fifo_udf_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "rep_cmd2_fifo_udf_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "rep_cmd3_fifo_udf_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_int_mask_3_reg[] = {
+	{ "free_ptr0_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "free_ptr1_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "free_ptr2_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "free_ptr3_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "block_ptr0_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "block_ptr1_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "block_ptr2_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "block_ptr3_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "mgid0_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "mgid1_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "mgid2_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "mgid3_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr0_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr1_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr2_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr3_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "rep_cmd0_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "rep_cmd1_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "rep_cmd2_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "rep_cmd3_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_int_mask_4_reg[] = {
+	{ "data_buf0_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "data_buf1_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "data_buf2_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "data_buf3_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "mlt_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "free_ptr0_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1,
+	  0x0 },
+	{ "free_ptr1_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1,
+	  0x0 },
+	{ "free_ptr2_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1,
+	  0x0 },
+	{ "free_ptr3_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1,
+	  0x0 },
+	{ "block_ptr0_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1,
+	  0x0 },
+	{ "block_ptr1_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1,
+	  0x0 },
+	{ "block_ptr2_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1,
+	  0x0 },
+	{ "block_ptr3_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1,
+	  0x0 },
+	{ "mgid0_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "mgid1_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "mgid2_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "mgid3_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr0_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1,
+	  0x0 },
+	{ "pre_rcv_ptr1_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1,
+	  0x0 },
+	{ "pre_rcv_ptr2_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1,
+	  0x0 },
+	{ "pre_rcv_ptr3_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1,
+	  0x0 },
+	{ "rep_cmd0_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "rep_cmd1_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "rep_cmd2_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "rep_cmd3_fifo_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_states_1_reg[] = {
+	{ "free_ptr0_fifo_full", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "free_ptr1_fifo_full", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "free_ptr2_fifo_full", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "free_ptr3_fifo_full", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "block_ptr0_fifo_full", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "block_ptr1_fifo_full", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "block_ptr2_fifo_full", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "block_ptr3_fifo_full", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "mgid0_fifo_full", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "mgid1_fifo_full", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "mgid2_fifo_full", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "mgid3_fifo_full", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr0_fifo_full", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr1_fifo_full", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr2_fifo_full", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr3_fifo_full", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "rep_cmd0_fifo_full", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "rep_cmd1_fifo_full", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "rep_cmd2_fifo_full", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "rep_cmd3_fifo_full", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_states_2_reg[] = {
+	{ "free_ptr0_fifo_udf", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "free_ptr1_fifo_udf", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "free_ptr2_fifo_udf", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "free_ptr3_fifo_udf", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "block_ptr0_fifo_udf", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "block_ptr1_fifo_udf", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "block_ptr2_fifo_udf", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "block_ptr3_fifo_udf", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "mgid0_fifo_udf", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "mgid1_fifo_udf", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "mgid2_fifo_udf", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "mgid3_fifo_udf", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr0_fifo_udf", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr1_fifo_udf", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr2_fifo_udf", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr3_fifo_udf", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "rep_cmd0_fifo_udf", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "rep_cmd1_fifo_udf", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "rep_cmd2_fifo_udf", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "rep_cmd3_fifo_udf", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_states_3_reg[] = {
+	{ "free_ptr0_fifo_ovf", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "free_ptr1_fifo_ovf", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "free_ptr2_fifo_ovf", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "free_ptr3_fifo_ovf", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "block_ptr0_fifo_ovf", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "block_ptr1_fifo_ovf", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "block_ptr2_fifo_ovf", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "block_ptr3_fifo_ovf", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "mgid0_fifo_ovf", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "mgid1_fifo_ovf", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "mgid2_fifo_ovf", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "mgid3_fifo_ovf", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr0_fifo_ovf", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr1_fifo_ovf", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr2_fifo_ovf", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr3_fifo_ovf", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "rep_cmd0_fifo_ovf", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "rep_cmd1_fifo_ovf", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "rep_cmd2_fifo_ovf", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "rep_cmd3_fifo_ovf", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_states_4_reg[] = {
+	{ "data_buf0_ram_parity_err", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "data_buf1_ram_parity_err", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "data_buf2_ram_parity_err", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "data_buf3_ram_parity_err", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "mlt_ecc_single_err", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "free_ptr0_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "free_ptr1_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "free_ptr2_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "free_ptr3_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "block_ptr0_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "block_ptr1_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "block_ptr2_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "block_ptr3_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "mgid0_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "mgid1_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "mgid2_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "mgid3_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr0_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr1_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr2_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr3_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "rep_cmd0_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "rep_cmd1_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "rep_cmd2_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "rep_cmd3_fifo_ecc_single_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_states_5_reg[] = {
+	{ "mlt_ecc_double_err", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "free_ptr0_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "free_ptr1_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "free_ptr2_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "free_ptr3_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "block_ptr0_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "block_ptr1_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "block_ptr2_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "block_ptr3_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "mgid0_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "mgid1_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "mgid2_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "mgid3_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr0_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr1_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr2_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr3_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "rep_cmd0_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "rep_cmd1_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "rep_cmd2_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "rep_cmd3_fifo_ecc_double_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_states_6_reg[] = {
+	{ "free_ptr0_fifo_empty", DPP_FIELD_FLAG_RO, 19, 1, 0x1, 0x0 },
+	{ "free_ptr1_fifo_empty", DPP_FIELD_FLAG_RO, 18, 1, 0x1, 0x0 },
+	{ "free_ptr2_fifo_empty", DPP_FIELD_FLAG_RO, 17, 1, 0x1, 0x0 },
+	{ "free_ptr3_fifo_empty", DPP_FIELD_FLAG_RO, 16, 1, 0x1, 0x0 },
+	{ "block_ptr0_fifo_empty", DPP_FIELD_FLAG_RO, 15, 1, 0x1, 0x0 },
+	{ "block_ptr1_fifo_empty", DPP_FIELD_FLAG_RO, 14, 1, 0x1, 0x0 },
+	{ "block_ptr2_fifo_empty", DPP_FIELD_FLAG_RO, 13, 1, 0x1, 0x0 },
+	{ "block_ptr3_fifo_empty", DPP_FIELD_FLAG_RO, 12, 1, 0x1, 0x0 },
+	{ "mgid0_fifo_empty", DPP_FIELD_FLAG_RO, 11, 1, 0x1, 0x0 },
+	{ "mgid1_fifo_empty", DPP_FIELD_FLAG_RO, 10, 1, 0x1, 0x0 },
+	{ "mgid2_fifo_empty", DPP_FIELD_FLAG_RO, 9, 1, 0x1, 0x0 },
+	{ "mgid3_fifo_empty", DPP_FIELD_FLAG_RO, 8, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr0_fifo_empty", DPP_FIELD_FLAG_RO, 7, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr1_fifo_empty", DPP_FIELD_FLAG_RO, 6, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr2_fifo_empty", DPP_FIELD_FLAG_RO, 5, 1, 0x1, 0x0 },
+	{ "pre_rcv_ptr3_fifo_empty", DPP_FIELD_FLAG_RO, 4, 1, 0x1, 0x0 },
+	{ "rep_cmd0_fifo_empty", DPP_FIELD_FLAG_RO, 3, 1, 0x1, 0x0 },
+	{ "rep_cmd1_fifo_empty", DPP_FIELD_FLAG_RO, 2, 1, 0x1, 0x0 },
+	{ "rep_cmd2_fifo_empty", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0 },
+	{ "rep_cmd3_fifo_empty", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_states_7_reg[] = {
+	{ "cos0_is_rep_busy", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0 },
+	{ "cos1_is_rep_busy", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0 },
+	{ "cos2_is_rep_busy", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0 },
+	{ "cos3_is_rep_busy", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0 },
+	{ "block_ptr0_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0 },
+	{ "block_ptr1_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0 },
+	{ "block_ptr2_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0 },
+	{ "block_ptr3_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr0_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr1_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr2_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0 },
+	{ "pre_rcv_ptr3_fifo_non_sop_ren_rdy", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0 },
+	{ "port_shap_rdy", DPP_FIELD_FLAG_RO, 9, 1, 0x1, 0x0 },
+	{ "mr_lif_group0_rdy_3", DPP_FIELD_FLAG_RO, 8, 1, 0x1, 0x0 },
+	{ "mr_lif_group0_rdy_2", DPP_FIELD_FLAG_RO, 7, 1, 0x1, 0x0 },
+	{ "mr_lif_group0_rdy_1", DPP_FIELD_FLAG_RO, 6, 1, 0x1, 0x0 },
+	{ "mr_lif_group0_rdy_0", DPP_FIELD_FLAG_RO, 5, 1, 0x1, 0x0 },
+	{ "pktrx_pfc_rdy_3", DPP_FIELD_FLAG_RO, 4, 1, 0x1, 0x0 },
+	{ "pktrx_pfc_rdy_2", DPP_FIELD_FLAG_RO, 3, 1, 0x1, 0x0 },
+	{ "pktrx_pfc_rdy_1", DPP_FIELD_FLAG_RO, 2, 1, 0x1, 0x0 },
+	{ "pktrx_pfc_rdy_0", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0 },
+	{ "pktrx_link_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_states_8_reg[] = {
+	{ "mr_head", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_sop_in_cnt_reg[] = {
+	{ "mr_sop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_eop_in_cnt_reg[] = {
+	{ "mr_eop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_sop_out_cnt_reg[] = {
+	{ "mr_sop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_eop_out_cnt_reg[] = {
+	{ "mr_eop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_in_cnt_reg[] = {
+	{ "mr_cos0_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_in_cnt_reg[] = {
+	{ "mr_cos1_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_in_cnt_reg[] = {
+	{ "mr_cos2_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_in_cnt_reg[] = {
+	{ "mr_cos3_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_out_cnt_reg[] = {
+	{ "mr_cos0_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_out_cnt_reg[] = {
+	{ "mr_cos1_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_out_cnt_reg[] = {
+	{ "mr_cos2_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_out_cnt_reg[] = {
+	{ "mr_cos3_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_err_in_cnt_reg[] = {
+	{ "mr_err_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_sop_in_cnt_reg[] = {
+	{ "mr_cos0_sop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_eop_in_cnt_reg[] = {
+	{ "mr_cos0_eop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_sop_in_cnt_reg[] = {
+	{ "mr_cos1_sop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_eop_in_cnt_reg[] = {
+	{ "mr_cos1_eop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_sop_in_cnt_reg[] = {
+	{ "mr_cos2_sop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_eop_in_cnt_reg[] = {
+	{ "mr_cos2_eop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_sop_in_cnt_reg[] = {
+	{ "mr_cos3_sop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_eop_in_cnt_reg[] = {
+	{ "mr_cos3_eop_in_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_in_err_cnt_reg[] = {
+	{ "mr_cos0_in_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_in_err_cnt_reg[] = {
+	{ "mr_cos1_in_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_in_err_cnt_reg[] = {
+	{ "mr_cos2_in_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_in_err_cnt_reg[] = {
+	{ "mr_cos3_in_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_sop_out_cnt_reg[] = {
+	{ "mr_cos0_sop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos0_eop_out_cnt_reg[] = {
+	{ "mr_cos0_eop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_sop_out_cnt_reg[] = {
+	{ "mr_cos1_sop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos1_eop_out_cnt_reg[] = {
+	{ "mr_cos1_eop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_sop_out_cnt_reg[] = {
+	{ "mr_cos2_sop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos2_eop_out_cnt_reg[] = {
+	{ "mr_cos2_eop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_sop_out_cnt_reg[] = {
+	{ "mr_cos3_sop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_cos3_eop_out_cnt_reg[] = {
+	{ "mr_cos3_eop_out_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_mlt_unvld_cnt_reg[] = {
+	{ "mr_mlt_unvld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_sop_eop_match_cfg_reg[] = {
+	{ "mr_sop_eop_macth_en", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "mr_sop_eop_macth_dicard_th", DPP_FIELD_FLAG_RW, 7, 8, 0xbc, 0x0 },
+};
+DPP_FIELD_T g_nppu_mr_cfg_mr_mlt_unvld_mgid_reg[] = {
+	{ "mr_mlt_unvld_mgid", DPP_FIELD_FLAG_RO, 16, 17, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_isch_fifo_th_1_reg[] = {
+	{ "cfg_sch_fifo7_fc_th", DPP_FIELD_FLAG_RW, 29, 6, 0x30, 0x0 },
+	{ "cfg_sch_fifo6_fc_th", DPP_FIELD_FLAG_RW, 21, 6, 0x30, 0x0 },
+	{ "cfg_sch_fifo5_fc_th", DPP_FIELD_FLAG_RW, 13, 6, 0x30, 0x0 },
+	{ "cfg_sch_fifo4_fc_th", DPP_FIELD_FLAG_RW, 5, 6, 0x30, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_isch_fifo_th_2_reg[] = {
+	{ "cfg_sch_fifo3_drop_th", DPP_FIELD_FLAG_RW, 29, 6, 0x38, 0x0 },
+	{ "cfg_sch_fifo1_drop_th", DPP_FIELD_FLAG_RW, 21, 6, 0x38, 0x0 },
+	{ "cfg_sch_fifo0_drop_th", DPP_FIELD_FLAG_RW, 13, 6, 0x38, 0x0 },
+	{ "cfg_sch_fifo8_fc_th", DPP_FIELD_FLAG_RW, 5, 6, 0x30, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_isch_fifo_th_3_reg[] = {
+	{ "cfg_sch_fifo6_drop_th", DPP_FIELD_FLAG_RW, 29, 6, 0x38, 0x0 },
+	{ "cfg_sch_fifo5_drop_th", DPP_FIELD_FLAG_RW, 21, 6, 0x38, 0x0 },
+	{ "cfg_sch_fifo4_drop_th", DPP_FIELD_FLAG_RW, 13, 6, 0x38, 0x0 },
+	{ "cfg_sch_fifo2_drop_th", DPP_FIELD_FLAG_RW, 5, 6, 0x38, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_isch_fifo_th_4_reg[] = {
+	{ "cfg_sch_fifo9_fc_th", DPP_FIELD_FLAG_RW, 29, 6, 0x30, 0x0 },
+	{ "cfg_sch_fifo9_drop_th", DPP_FIELD_FLAG_RW, 21, 6, 0x38, 0x0 },
+	{ "cfg_sch_fifo8_drop_th", DPP_FIELD_FLAG_RW, 13, 6, 0x38, 0x0 },
+	{ "cfg_sch_fifo7_drop_th", DPP_FIELD_FLAG_RW, 5, 6, 0x38, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_isch_cfg_0_reg[] = {
+	{ "cfg_sch_wrr1_weight1", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_hdu_ex_tpid_0_reg[] = {
+	{ "cfg_type0", DPP_FIELD_FLAG_RW, 31, 16, 0x8100, 0x0 },
+	{ "cfg_type1", DPP_FIELD_FLAG_RW, 15, 16, 0x9100, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_hdu_ex_tpid_1_reg[] = {
+	{ "cfg_type2", DPP_FIELD_FLAG_RW, 31, 16, 0x88a8, 0x0 },
+	{ "cfg_type3", DPP_FIELD_FLAG_RW, 15, 16, 0x9200, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_hdu_int_tpid_0_reg[] = {
+	{ "cfg_inner_type0", DPP_FIELD_FLAG_RW, 31, 16, 0x8100, 0x0 },
+	{ "cfg_inner_type1", DPP_FIELD_FLAG_RW, 15, 16, 0x9100, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_hdu_int_tpid_1_reg[] = {
+	{ "cfg_inner_type2", DPP_FIELD_FLAG_RW, 31, 16, 0x88a8, 0x0 },
+	{ "cfg_inner_type3", DPP_FIELD_FLAG_RW, 15, 16, 0x9200, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_hdu_hdlc_0_reg[] = {
+	{ "hdlc_cfg0_type", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0 },
+	{ "hdlc_cfg1_type", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_hdu_hdlc_1_reg[] = {
+	{ "hdlc_cfg2_type", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0 },
+	{ "hdlc_cfg3_type", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l3type_0_reg[] = {
+	{ "cfg_l3_type0", DPP_FIELD_FLAG_RW, 31, 16, 0xffff, 0x0 },
+	{ "cfg_l3_type1", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l3type_1_reg[] = {
+	{ "cfg_l3_type2", DPP_FIELD_FLAG_RW, 31, 16, 0xffff, 0x0 },
+	{ "cfg_l3_type3", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l3type_2_reg[] = {
+	{ "cfg_l3_type4", DPP_FIELD_FLAG_RW, 31, 16, 0xffff, 0x0 },
+	{ "cfg_l3_type5", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l3type_3_reg[] = {
+	{ "cfg_l3_type6", DPP_FIELD_FLAG_RW, 31, 16, 0xffff, 0x0 },
+	{ "cfg_l3_type7", DPP_FIELD_FLAG_RW, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l4type_0_reg[] = {
+	{ "cfg_l4_type0", DPP_FIELD_FLAG_RW, 31, 8, 0xff, 0x0 },
+	{ "cfg_l4_type1", DPP_FIELD_FLAG_RW, 23, 8, 0xff, 0x0 },
+	{ "cfg_l4_type2", DPP_FIELD_FLAG_RW, 15, 8, 0xff, 0x0 },
+	{ "cfg_l4_type3", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l4type_1_reg[] = {
+	{ "cfg_l4_type4", DPP_FIELD_FLAG_RW, 31, 8, 0xff, 0x0 },
+	{ "cfg_l4_type5", DPP_FIELD_FLAG_RW, 23, 8, 0xff, 0x0 },
+	{ "cfg_l4_type6", DPP_FIELD_FLAG_RW, 15, 8, 0xff, 0x0 },
+	{ "cfg_l4_type7", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_hdu_udf_l4type_2_reg[] = {
+	{ "cfg_l4_type8", DPP_FIELD_FLAG_RW, 23, 8, 0xff, 0x0 },
+	{ "cfg_l4_type9", DPP_FIELD_FLAG_RW, 15, 8, 0xff, 0x0 },
+	{ "cfg_l4_type10", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_slot_no_cfg_reg[] = {
+	{ "cfg_parser_slot_no", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_int_en_0_reg[] = {
+	{ "pktrx_int_en_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_int_en_1_reg[] = {
+	{ "pktrx_int_en_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "pktrx_int_en_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_int_mask_0_reg[] = {
+	{ "pktrx_int_mask_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_int_mask_1_reg[] = {
+	{ "pktrx_int_mask_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "pktrx_int_mask_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_int_status_reg[] = {
+	{ "int_status", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_port_rdy0_reg[] = {
+	{ "pktrx_trpgrx_r1_rdy", DPP_FIELD_FLAG_RO, 31, 10, 0x3ff, 0x0 },
+	{ "pktrx_trpgrx_r2_rdy", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy0_reg[] = {
+	{ "pktrx_trpgrx_r1_pfc_rdy_0", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy1_reg[] = {
+	{ "pktrx_trpgrx_r1_pfc_rdy_1", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy2_reg[] = {
+	{ "pktrx_trpgrx_r1_pfc_rdy_2", DPP_FIELD_FLAG_RO, 31, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy3_reg[] = {
+	{ "pktrx_trpgrx_r2_pfc_rdy_3", DPP_FIELD_FLAG_RO, 31, 8, 0xf, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy4_reg[] = {
+	{ "pktrx_trpgrx_r2_pfc_rdy_4", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy5_reg[] = {
+	{ "pktrx_trpgrx_r2_pfc_rdy_5", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy6_reg[] = {
+	{ "pktrx_trpgrx_r2_pfc_rdy_6", DPP_FIELD_FLAG_RO, 31, 24, 0xffffff, 0x0 },
+};
+DPP_FIELD_T g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_reg[] = {
+	{ "cfg_port_l2_offset_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_idma_cfg_int_ram_en_reg[] = {
+	{ "phy_sts_parity_err", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "ptr_buf_parity_err", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_idma_cfg_int_ram_mask_reg[] = {
+	{ "phy_sts_parity_err", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "ptr_buf_parity_err", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_idma_cfg_int_ram_status_reg[] = {
+	{ "phy_sts_parity_err", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "ptr_buf_parity_err", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_idma_cfg_subsys_int_mask_flag_reg[] = {
+	{ "subsys_int_mask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_idma_cfg_subsys_int_unmask_flag_reg[] = {
+	{ "subsys_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_idma_cfg_debug_cnt_rdclr_mode_reg[] = {
+	{ "debug_cnt_rdclr_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_int_ram_en0_reg[] = {
+	{ "int_ram_en_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "int_ram_en_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "int_ram_en_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "int_ram_en_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "int_ram_en_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "int_ram_en_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "int_ram_en_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "int_ram_en_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "int_ram_en_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "int_ram_en_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "int_ram_en_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "int_ram_en_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "int_ram_en_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "int_ram_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "int_ram_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "int_ram_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "int_ram_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "int_ram_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "int_ram_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "int_ram_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "int_ram_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "int_ram_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "int_ram_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "int_ram_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "int_ram_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "int_ram_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "int_ram_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "int_ram_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "int_ram_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "int_ram_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "int_ram_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "int_ram_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_int_ram_mask0_reg[] = {
+	{ "int_ram_mask_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "int_ram_mask_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "int_ram_mask_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "int_ram_mask_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "int_ram_mask_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "int_ram_mask_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "int_ram_mask_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "int_ram_mask_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "int_ram_mask_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "int_ram_mask_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "int_ram_mask_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "int_ram_mask_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "int_ram_mask_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "int_ram_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "int_ram_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "int_ram_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "int_ram_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "int_ram_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "int_ram_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "int_ram_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "int_ram_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "int_ram_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "int_ram_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "int_ram_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "int_ram_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "int_ram_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "int_ram_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "int_ram_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "int_ram_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "int_ram_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "int_ram_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "int_ram_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_int_ram_status0_reg[] = {
+	{ "int_ram_status_31", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0 },
+	{ "int_ram_status_30", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0 },
+	{ "int_ram_status_29", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0 },
+	{ "int_ram_status_28", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0 },
+	{ "int_ram_status_27", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0 },
+	{ "int_ram_status_26", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0 },
+	{ "int_ram_status_25", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0 },
+	{ "int_ram_status_24", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0 },
+	{ "int_ram_status_23", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0 },
+	{ "int_ram_status_22", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0 },
+	{ "int_ram_status_21", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0 },
+	{ "int_ram_status_20", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0 },
+	{ "int_ram_status_19", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0 },
+	{ "int_ram_status_18", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0 },
+	{ "int_ram_status_17", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0 },
+	{ "int_ram_status_16", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0 },
+	{ "int_ram_status_15", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0 },
+	{ "int_ram_status_14", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0 },
+	{ "int_ram_status_13", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0 },
+	{ "int_ram_status_12", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0 },
+	{ "int_ram_status_11", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0 },
+	{ "int_ram_status_10", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0 },
+	{ "int_ram_status_9", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0 },
+	{ "int_ram_status_8", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0 },
+	{ "int_ram_status_7", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "int_ram_status_6", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "int_ram_status_5", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "int_ram_status_4", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "int_ram_status_3", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "int_ram_status_2", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "int_ram_status_1", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "int_ram_status_0", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_en0_reg[] = {
+	{ "int_fifo_en_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "int_fifo_en_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "int_fifo_en_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "int_fifo_en_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "int_fifo_en_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "int_fifo_en_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "int_fifo_en_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "int_fifo_en_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "int_fifo_en_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "int_fifo_en_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "int_fifo_en_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "int_fifo_en_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "int_fifo_en_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "int_fifo_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "int_fifo_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "int_fifo_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "int_fifo_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "int_fifo_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "int_fifo_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "int_fifo_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "int_fifo_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "int_fifo_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "int_fifo_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "int_fifo_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "int_fifo_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "int_fifo_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "int_fifo_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "int_fifo_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "int_fifo_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "int_fifo_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "int_fifo_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "int_fifo_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_en1_reg[] = {
+	{ "int_fifo_en_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "int_fifo_en_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "int_fifo_en_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "int_fifo_en_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_mask0_reg[] = {
+	{ "int_fifo_mask_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_mask1_reg[] = {
+	{ "int_fifo_mask_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "int_fifo_mask_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_status0_reg[] = {
+	{ "int_fifo_status_31", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0 },
+	{ "int_fifo_status_30", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0 },
+	{ "int_fifo_status_29", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0 },
+	{ "int_fifo_status_28", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0 },
+	{ "int_fifo_status_27", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0 },
+	{ "int_fifo_status_26", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0 },
+	{ "int_fifo_status_25", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0 },
+	{ "int_fifo_status_24", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0 },
+	{ "int_fifo_status_23", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0 },
+	{ "int_fifo_status_22", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0 },
+	{ "int_fifo_status_21", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0 },
+	{ "int_fifo_status_20", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0 },
+	{ "int_fifo_status_19", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0 },
+	{ "int_fifo_status_18", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0 },
+	{ "int_fifo_status_17", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0 },
+	{ "int_fifo_status_16", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0 },
+	{ "int_fifo_status_15", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0 },
+	{ "int_fifo_status_14", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0 },
+	{ "int_fifo_status_13", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0 },
+	{ "int_fifo_status_12", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0 },
+	{ "int_fifo_status_11", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0 },
+	{ "int_fifo_status_10", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0 },
+	{ "int_fifo_status_9", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0 },
+	{ "int_fifo_status_8", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0 },
+	{ "int_fifo_status_7", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "int_fifo_status_6", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "int_fifo_status_5", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "int_fifo_status_4", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "int_fifo_status_3", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "int_fifo_status_2", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "int_fifo_status_1", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "int_fifo_status_0", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_int_fifo_status1_reg[] = {
+	{ "int_fifo_status_35", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "int_fifo_status_34", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "int_fifo_status_33", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "int_fifo_status_32", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_subsys_int_mask_flag_reg[] = {
+	{ "subsys_int_mask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_subsys_int_unmask_flag_reg[] = {
+	{ "subsys_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_sa_ip_en_reg[] = {
+	{ "sa_ip_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_debug_cnt_rdclr_mode_reg[] = {
+	{ "debug_cnt_rdclr_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_fptr_fifo_aful_assert_cfg_reg[] = {
+	{ "fptr_fifo_aful_assert_cfg", DPP_FIELD_FLAG_RW, 12, 13, 0xff0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_fptr_fifo_aful_negate_cfg_reg[] = {
+	{ "fptr_fifo_aful_negate_cfg", DPP_FIELD_FLAG_RW, 12, 13, 0xff0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_pf_fifo_aful_assert_cfg_reg[] = {
+	{ "pf_fifo_aful_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x8, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_pf_fifo_aful_negate_cfg_reg[] = {
+	{ "pf_fifo_aful_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x8, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_pf_fifo_aept_assert_cfg_reg[] = {
+	{ "pf_fifo_aept_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_pf_fifo_aept_negate_cfg_reg[] = {
+	{ "pf_fifo_aept_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_wb_aful_assert_cfg_reg[] = {
+	{ "wb_aful_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x12, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_wb_aful_negate_cfg_reg[] = {
+	{ "wb_aful_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x12, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_se_key_aful_assert_cfg_reg[] = {
+	{ "se_key_aful_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_se_aful_assert_cfg_reg[] = {
+	{ "ifbrd_se_aful_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_se_aful_negate_cfg_reg[] = {
+	{ "ifbrd_se_aful_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_odma_aful_assert_cfg_reg[] = {
+	{ "ifbrd_odma_aful_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_odma_aful_negate_cfg_reg[] = {
+	{ "ifbrd_odma_aful_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_ppu_aful_assert_cfg_reg[] = {
+	{ "ifbrd_ppu_aful_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_ifbrd_ppu_aful_negate_cfg_reg[] = {
+	{ "ifbrd_ppu_aful_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_mc_logic_aful_assert_cfg_reg[] = {
+	{ "mc_logic_aful_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_mc_logic_aful_negate_cfg_reg[] = {
+	{ "mc_logic_aful_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_mc_logic_diff_reg[] = {
+	{ "mc_logic_diff", DPP_FIELD_FLAG_RW, 7, 8, 0xa, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_cfg_peak_port_cnt_clr_reg[] = {
+	{ "cfg_peak_port_cnt_clr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_crdt_th_reg[] = {
+	{ "ftm_crdt_port_cng_th", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0 },
+	{ "ftm_crdt_port_th", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_link_th_01_reg[] = {
+	{ "total_congest_th1", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0 },
+	{ "total_congest_th0", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_link_th_23_reg[] = {
+	{ "total_congest_th3", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0 },
+	{ "total_congest_th2", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_link_th_45_reg[] = {
+	{ "total_congest_th5", DPP_FIELD_FLAG_RW, 29, 15, 0x0, 0x0 },
+	{ "total_congest_th4", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_link_th_6_reg[] = {
+	{ "total_congest_th6", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_all_ftm_total_congest_th_reg[] = {
+	{ "all_ftm_total_congest_th", DPP_FIELD_FLAG_RW, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_cfg_crdt_mode_reg[] = {
+	{ "cfg_crdt_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_cfg_pfc_rdy_high_time_reg[] = {
+	{ "cfg_pfc_rdy_high_time", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_cfg_cfg_pfc_rdy_low_time_reg[] = {
+	{ "cfg_pfc_rdy_low_time", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_pbu_fc_rdy_reg[] = {
+	{ "pbu_oam_send_fc_rdy", DPP_FIELD_FLAG_RO, 7, 2, 0x0, 0x0 },
+	{ "pbu_odma_fc_rdy", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "pbu_tm_fc_rdy", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "pbu_idma_cos_rdy", DPP_FIELD_FLAG_RO, 1, 2, 0x2, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_pbu_lif_group0_rdy0_reg[] = {
+	{ "pbu_ipg1_rdy", DPP_FIELD_FLAG_RO, 27, 3, 0x0, 0x0 },
+	{ "pbu_ipg0_rdy", DPP_FIELD_FLAG_RO, 24, 9, 0x0, 0x0 },
+	{ "pbu_trpgrx_xge_rdy", DPP_FIELD_FLAG_RO, 9, 2, 0x0, 0x0 },
+	{ "pbu_trpgrx_cge1_rdy", DPP_FIELD_FLAG_RO, 7, 4, 0x0, 0x0 },
+	{ "pbu_trpgrx_cge0_rdy", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_pbu_lif_group0_rdy1_reg[] = {
+	{ "pbu_lif_group0_rdy1", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_pbu_lif_group1_rdy_reg[] = {
+	{ "pbu_lif_group1_rdy1", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_pbu_lif_group0_pfc_rdy_reg[] = {
+	{ "pbu_lif_group0_pfc_rdy", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_pbu_lif_group1_pfc_rdy_reg[] = {
+	{ "pbu_lif_group1_pfc_rdy", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_pbu_sa_port_rdy_0_31_reg[] = {
+	{ "pbu_sa_port_rdy_0_31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_pbu_sa_port_rdy_32_50_reg[] = {
+	{ "pbu_sa_port_rdy_32_50", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_pbu_pktrx_mr_pfc_rdy_reg[] = {
+	{ "pbu_pktrx_mr_pfc_rdy", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_0_31_reg[] = {
+	{ "pbu_ftm_crdt_port_rdy_0_31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_32_47_reg[] = {
+	{ "pbu_ftm_crdt_port_rdy_32_47", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_0_31_reg[] = {
+	{ "pbu_ftm_crdt_port_cng_rdy_0_31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_32_47_reg[] = {
+	{ "pbu_ftm_crdt_port_cng_rdy_32_47", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_pbu_stat_pbu_ftm_crdt_sys_info_reg[] = {
+	{ "pbu_ftm_crdt_sys_info", DPP_FIELD_FLAG_RO, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_weight_normal_mc_reg[] = {
+	{ "weight_normal_mc", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_weight_sa_mc_reg[] = {
+	{ "weight_sa_mc", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_weight_etm_reg[] = {
+	{ "weight_etm", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_weight_lp_mc_reg[] = {
+	{ "weight_lp_mc", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_weight_oam_reg[] = {
+	{ "weight_oam", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_weight_lif_ctrl1_reg[] = {
+	{ "weight_lif_ctrl1", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_weight_lif_ctrl2_reg[] = {
+	{ "weight_lif_ctrl2", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_ecc_bypass_read_reg[] = {
+	{ "eccbypass", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_isu_int_mask_reg[] = {
+	{ "isu_int_mask", DPP_FIELD_FLAG_RW, 26, 27, 0x7ffffff, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_cfg_crdt_cycle_reg[] = {
+	{ "cfg_cycle", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_cfg_crdt_value_reg[] = {
+	{ "cfg_value", DPP_FIELD_FLAG_RW, 13, 14, 0x216, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_isu_int_en_reg[] = {
+	{ "isu_int_en", DPP_FIELD_FLAG_RW, 26, 27, 0x7ffffff, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_isu_ppu_fifo_fc_reg[] = {
+	{ "isu_ppu_fifo_fc", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_isu_int_status_reg[] = {
+	{ "isu_int_status_26", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0 },
+	{ "isu_int_status_25", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0 },
+	{ "isu_int_status_24", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0 },
+	{ "isu_int_status_23", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0 },
+	{ "isu_int_status_22", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0 },
+	{ "isu_int_status_21", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0 },
+	{ "isu_int_status_20", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0 },
+	{ "isu_int_status_19", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0 },
+	{ "isu_int_status_18", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0 },
+	{ "isu_int_status_17", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0 },
+	{ "isu_int_status_16", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0 },
+	{ "isu_int_status_15", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0 },
+	{ "isu_int_status_14", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0 },
+	{ "isu_int_status_13", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0 },
+	{ "isu_int_status_12", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0 },
+	{ "isu_int_status_11", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0 },
+	{ "isu_int_status_10", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0 },
+	{ "isu_int_status_9", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0 },
+	{ "isu_int_status_8", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0 },
+	{ "isu_int_status_7", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "isu_int_status_6", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "isu_int_status_5", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "isu_int_status_4", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "isu_int_status_3", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "isu_int_status_2", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "isu_int_status_1", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "isu_int_status_0", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_fd_prog_full_assert_cfg_reg[] = {
+	{ "fd_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_fd_prog_full_negate_cfg_reg[] = {
+	{ "fd_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_lp_prog_full_assert_cfg_reg[] = {
+	{ "lp_prog_ept_assert_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x80, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_cfg_lp_prog_full_negate_cfg_reg[] = {
+	{ "lp_prog_ept_negate_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x80, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat0_reg[] = {
+	{ "debug_cnt_dat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat1_reg[] = {
+	{ "debug_cnt_dat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat2_reg[] = {
+	{ "debug_cnt_dat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat3_reg[] = {
+	{ "debug_cnt_dat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat4_reg[] = {
+	{ "debug_cnt_dat4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat5_reg[] = {
+	{ "debug_cnt_dat5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat6_reg[] = {
+	{ "debug_cnt_dat6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat7_reg[] = {
+	{ "debug_cnt_dat7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat8_reg[] = {
+	{ "debug_cnt_dat8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat9_reg[] = {
+	{ "debug_cnt_dat9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat10_reg[] = {
+	{ "debug_cnt_dat10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat11_reg[] = {
+	{ "debug_cnt_dat11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat12_reg[] = {
+	{ "debug_cnt_dat12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat13_reg[] = {
+	{ "debug_cnt_dat13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat14_reg[] = {
+	{ "debug_cnt_dat14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat15_reg[] = {
+	{ "debug_cnt_dat15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat16_reg[] = {
+	{ "debug_cnt_dat16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat17_reg[] = {
+	{ "debug_cnt_dat17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat18_reg[] = {
+	{ "debug_cnt_dat18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_dat19_reg[] = {
+	{ "debug_cnt_dat18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_isu_stat_debug_cnt_cfg_reg[] = {
+	{ "debug_cnt_ovf_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "debug_cnt_rdclr_mode", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0 },
+	{ "user_cnt_value", DPP_FIELD_FLAG_RW, 29, 4, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_exsa_tdm_offset_reg[] = {
+	{ "exsa_tdm_offset", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_ecc_bypass_readt_reg[] = {
+	{ "ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_odma_int_en_0_reg[] = {
+	{ "odma_int_en_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "odma_int_en_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "odma_int_en_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "odma_int_en_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "odma_int_en_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "odma_int_en_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "odma_int_en_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "odma_int_en_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "odma_int_en_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "odma_int_en_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "odma_int_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_odma_int_en_1_reg[] = {
+	{ "odma_int_en_63", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "odma_int_en_62", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "odma_int_en_61", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "odma_int_en_59", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "odma_int_en_58", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "odma_int_en_57", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "odma_int_en_56", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "odma_int_en_55", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "odma_int_en_54", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "odma_int_en_53", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "odma_int_en_52", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "odma_int_en_51", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "odma_int_en_49", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "odma_int_en_47", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "odma_int_en_45", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "odma_int_en_39", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "odma_int_en_38", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "odma_int_en_37", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "odma_int_en_36", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "odma_int_en_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "odma_int_en_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "odma_int_en_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "odma_int_en_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_odma_int_en_2_reg[] = {
+	{ "odma_int_en_91", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "odma_int_en_88", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "odma_int_en_85", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "odma_int_en_82", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "odma_int_en_79", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "odma_int_en_75", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "odma_int_en_74", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "odma_int_en_71", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "odma_int_en_65", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "odma_int_en_64", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_odma_int_en_3_reg[] = {
+	{ "odma_int_en_115", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "odma_int_en_114", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "odma_int_en_112", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "odma_int_en_110", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "odma_int_en_109", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "odma_int_en_108", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "odma_int_en_107", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "odma_int_en_106", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "odma_int_en_102", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "odma_int_en_101", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "odma_int_en_100", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "odma_int_en_98", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "odma_int_en_96", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_odma_int_mask_0_reg[] = {
+	{ "odma_int_mask_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "odma_int_mask_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "odma_int_mask_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "odma_int_mask_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "odma_int_mask_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "odma_int_mask_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "odma_int_mask_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "odma_int_mask_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "odma_int_mask_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "odma_int_mask_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "odma_int_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_odma_int_mask_1_reg[] = {
+	{ "odma_int_mask_63", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "odma_int_mask_62", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "odma_int_mask_61", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "odma_int_mask_59", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "odma_int_mask_58", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "odma_int_mask_57", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "odma_int_mask_56", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "odma_int_mask_55", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "odma_int_mask_54", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "odma_int_mask_53", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "odma_int_mask_52", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "odma_int_mask_51", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "odma_int_mask_50", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "odma_int_mask_49", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "odma_int_mask_47", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "odma_int_mask_45", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "odma_int_mask_39", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "odma_int_mask_38", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "odma_int_mask_37", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "odma_int_mask_36", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "odma_int_mask_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "odma_int_mask_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "odma_int_mask_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "odma_int_mask_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_odma_int_mask_2_reg[] = {
+	{ "odma_int_mask_91", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "odma_int_mask_88", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "odma_int_mask_85", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "odma_int_mask_82", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "odma_int_mask_79", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "odma_int_mask_75", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "odma_int_mask_74", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "odma_int_mask_71", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "odma_int_mask_65", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "odma_int_mask_64", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_odma_int_mask_3_reg[] = {
+	{ "odma_int_mask_115", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "odma_int_mask_114", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "odma_int_mask_112", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "odma_int_mask_110", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "odma_int_mask_109", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "odma_int_mask_108", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "odma_int_mask_107", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "odma_int_mask_106", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "odma_int_mask_102", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "odma_int_mask_101", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "odma_int_mask_100", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "odma_int_mask_98", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "odma_int_mask_96", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_odma_int_status_0_reg[] = {
+	{ "odma_int_status_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "odma_int_status_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "odma_int_status_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "odma_int_status_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "odma_int_status_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "odma_int_status_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "odma_int_status_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "odma_int_status_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "odma_int_status_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "odma_int_status_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "odma_int_status_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_odma_int_status_1_reg[] = {
+	{ "odma_int_status_63", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "odma_int_status_62", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "odma_int_status_61", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "odma_int_status_59", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "odma_int_status_58", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "odma_int_status_57", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "odma_int_status_56", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "odma_int_status_55", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "odma_int_status_54", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "odma_int_status_53", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "odma_int_status_52", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "odma_int_status_51", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "odma_int_status_49", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "odma_int_status_47", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "odma_int_status_45", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "odma_int_status_39", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "odma_int_status_38", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "odma_int_status_37", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "odma_int_status_36", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "odma_int_status_35", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "odma_int_status_34", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "odma_int_status_33", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "odma_int_status_32", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_odma_int_status_2_reg[] = {
+	{ "odma_int_status_91", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "odma_int_status_88", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "odma_int_status_85", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "odma_int_status_82", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "odma_int_status_79", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "odma_int_status_75", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "odma_int_status_74", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "odma_int_status_71", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "odma_int_status_65", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "odma_int_status_64", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_odma_int_status_3_reg[] = {
+	{ "odma_int_status_117", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "odma_int_status_116", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "odma_int_status_115", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "odma_int_status_114", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "odma_int_status_112", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "odma_int_status_110", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "odma_int_status_109", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "odma_int_status_108", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "odma_int_status_107", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "odma_int_status_106", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "odma_int_status_102", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "odma_int_status_101", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "odma_int_status_100", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "odma_int_status_98", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "odma_int_status_96", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_sp_tdm_err_nor_cfg_reg[] = {
+	{ "sp_tdm_err_nor_cfg", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_a_reg[] = {
+	{ "etm_dis_ptr_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_n_reg[] = {
+	{ "etm_dis_ptr_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_a_reg[] = {
+	{ "ftm_dis_ptr_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_n_reg[] = {
+	{ "ftm_dis_ptr_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_a_reg[] = {
+	{ "tm_dis_fifo_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_n_reg[] = {
+	{ "tm_dis_fifo_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_err_prog_full_cfg_a_reg[] = {
+	{ "err_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_err_prog_full_cfg_n_reg[] = {
+	{ "err_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_tdmuc_prog_full_cfg_a_reg[] = {
+	{ "tdmuc_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_tdmuc_prog_full_cfg_n_reg[] = {
+	{ "tdmuc_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_a_reg[] = {
+	{ "tdmmc_groupid_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_n_reg[] = {
+	{ "tdmmc_groupid_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_a_reg[] = {
+	{ "tdmmc_no_bitmap_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8,
+	  0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_n_reg[] = {
+	{ "tdmmc_no_bitmap_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8,
+	  0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_tdmmc_prog_full_cfg_a_reg[] = {
+	{ "tdmmc_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_tdmmc_prog_full_cfg_n_reg[] = {
+	{ "tdmmc_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_desc_prog_full_cfg_a_reg[] = {
+	{ "desc_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x64, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_desc_prog_full_cfg_n_reg[] = {
+	{ "desc_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_dly_prog_full_cfg_a_reg[] = {
+	{ "dly_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_dly_prog_full_cfg_n_reg[] = {
+	{ "dly_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_rsp_prog_full_cfg_a_reg[] = {
+	{ "rsp_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_rsp_prog_full_cfg_n_reg[] = {
+	{ "rsp_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_nor_prog_full_cfg_a_reg[] = {
+	{ "nor_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_nor_prog_full_cfg_n_reg[] = {
+	{ "nor_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 10, 11, 0x3e8, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_etm_nor_prog_full_cfg_a_reg[] = {
+	{ "etm_nor_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_etm_nor_prog_full_cfg_n_reg[] = {
+	{ "etm_nor_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_ftm_nor_prog_full_cfg_a_reg[] = {
+	{ "ftm_nor_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_ftm_nor_prog_full_cfg_n_reg[] = {
+	{ "ftm_nor_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_etm_prog_full_cfg_a_reg[] = {
+	{ "etm_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_etm_prog_full_cfg_n_reg[] = {
+	{ "etm_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_ftm_prog_full_cfg_a_reg[] = {
+	{ "ftm_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_ftm_prog_full_cfg_n_reg[] = {
+	{ "ftm_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_a_reg[] = {
+	{ "etm_nrdcnt_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_n_reg[] = {
+	{ "etm_nrdcnt_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_a_reg[] = {
+	{ "ftm_nrdcnt_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_n_reg[] = {
+	{ "ftm_nrdcnt_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_pp_prog_full_cfg_a_reg[] = {
+	{ "pp_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_pp_prog_full_cfg_n_reg[] = {
+	{ "pp_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x6e, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_tm_weight_reg[] = {
+	{ "tm_weight", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_pp_weight_reg[] = {
+	{ "pp_weight", DPP_FIELD_FLAG_RW, 6, 7, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_ifbcmd_prog_full_cfg_a_reg[] = {
+	{ "ifbcmd_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 6, 7, 0x32, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_ifbcmd_prog_full_cfg_n_reg[] = {
+	{ "ifbcmd_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 6, 7, 0x32, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_mccnt_prog_full_cfg_a_reg[] = {
+	{ "mccnt_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_mccnt_prog_full_cfg_n_reg[] = {
+	{ "mccnt_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 5, 6, 0x19, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_int_or_pon_reg[] = {
+	{ "int_or_pon", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_quemng_cnt_in_err_cnt_reg[] = {
+	{ "quemng_cnt_in_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_lif0_port_eop_cnt_reg[] = {
+	{ "lif0_port_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_lif1_port_eop_cnt_reg[] = {
+	{ "lif1_port_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_lifc_port0_eop_cnt_reg[] = {
+	{ "lifc_port0_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_lifc_port1_eop_cnt_reg[] = {
+	{ "lifc_port1_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_fptr_fifo_prog_ept_cfg_n_reg[] = {
+	{ "fptr_fifo_prog_ept_cfg_n", DPP_FIELD_FLAG_RW, 14, 15, 0x40, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_isu_fifo_prog_full_cfg_a_reg[] = {
+	{ "isu_fifo_prog_full_cfg_a", DPP_FIELD_FLAG_RW, 7, 8, 0x60, 0x0 },
+};
+DPP_FIELD_T g_nppu_odma_cfg_isu_fifo_prog_full_cfg_n_reg[] = {
+	{ "isu_fifo_prog_full_cfg_n", DPP_FIELD_FLAG_RW, 7, 8, 0x60, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_access_done_reg[] = {
+	{ "ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_access_command_reg[] = {
+	{ "ind_rd_or_wr", DPP_FIELD_FLAG_RW, 21, 1, 0x0, 0x0 },
+	{ "ind_mem_mask", DPP_FIELD_FLAG_RW, 20, 4, 0x0, 0x0 },
+	{ "ind_mem_id", DPP_FIELD_FLAG_RW, 16, 4, 0x0, 0x0 },
+	{ "ind_mem_addr", DPP_FIELD_FLAG_RW, 12, 13, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_dat0_reg[] = {
+	{ "ind_dat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_dat1_reg[] = {
+	{ "ind_dat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_dat2_reg[] = {
+	{ "ind_dat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_dat3_reg[] = {
+	{ "ind_dat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_oam_tx_main_en_reg[] = {
+	{ "oam_tx_main_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_tx_total_num_reg[] = {
+	{ "tx_total_num", DPP_FIELD_FLAG_RW, 12, 13, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_oam_chk_main_en_reg[] = {
+	{ "oam_chk_main_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_chk_total_num0_reg[] = {
+	{ "chk_total_num0", DPP_FIELD_FLAG_RW, 12, 13, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ma_chk_main_en_reg[] = {
+	{ "oam_chk_main_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_chk_total_num1_reg[] = {
+	{ "chk_total_num0", DPP_FIELD_FLAG_RW, 12, 13, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_tx_stat_en_reg[] = {
+	{ "tx_stat_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_rec_stat_en_reg[] = {
+	{ "rec_stat_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_stat_oam_rdy_mask_reg[] = {
+	{ "stat_oam_rdy_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_session_grading0_reg[] = {
+	{ "session_grading0", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_session_grading1_reg[] = {
+	{ "session_grading1", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_session_grading2_reg[] = {
+	{ "session_grading2", DPP_FIELD_FLAG_RW, 2, 3, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_session_grading3_reg[] = {
+	{ "session_grading3", DPP_FIELD_FLAG_RW, 2, 3, 0x7, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_bfd_chk_haddr_reg[] = {
+	{ "bfd_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ethccm_chk_haddr_reg[] = {
+	{ "ethccm_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_tpbfd_chk_haddr_reg[] = {
+	{ "tpbfd_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_tpoam_ccm_chk_haddr_reg[] = {
+	{ "tpoam_ccm_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_bfd_tx_haddr_reg[] = {
+	{ "bfd_tx_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ethccm_tx_haddr_reg[] = {
+	{ "ethccm_tx_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_tpbfd_tx_haddr_reg[] = {
+	{ "tpbfd_tx_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_tpoam_ccm_tx_haddr_reg[] = {
+	{ "tpoam_ccm_tx_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ethccm_ma_chk_haddr_reg[] = {
+	{ "ethccm_ma_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_tpccm_ma_chk_haddr_reg[] = {
+	{ "tpccm_ma_chk_haddr", DPP_FIELD_FLAG_RW, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_groupnum_ram_clr_reg[] = {
+	{ "groupnum_ram_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_index_ram0_clr_reg[] = {
+	{ "index_ram0_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_index_ram1_clr_reg[] = {
+	{ "index_ram1_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_rmep_ram_clr_reg[] = {
+	{ "rmep_ram_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ma_ram_clr_reg[] = {
+	{ "ma_ram_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ram_init_done_reg[] = {
+	{ "ram_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_rec_bfd_debug_en_reg[] = {
+	{ "rec_bfd_debug_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_oam_session_int_reg[] = {
+	{ "tpma_int", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "ethma_int", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "bfd_int", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "ethoam_int", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "tpbfd_int", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "tpoam_int", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_pon_int_reg[] = {
+	{ "fifo_int", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "pon_protect_int", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_oam_int_clr_reg[] = {
+	{ "oam_int_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_type_int_clr0_reg[] = {
+	{ "tpma_int_clr", DPP_FIELD_FLAG_WO, 5, 1, 0x0, 0x0 },
+	{ "ethma_int_clr", DPP_FIELD_FLAG_WO, 4, 1, 0x0, 0x0 },
+	{ "bfd_int_clr", DPP_FIELD_FLAG_WO, 3, 1, 0x0, 0x0 },
+	{ "ethoam_int_clr", DPP_FIELD_FLAG_WO, 2, 1, 0x0, 0x0 },
+	{ "tpbfd_int_clr", DPP_FIELD_FLAG_WO, 1, 1, 0x0, 0x0 },
+	{ "tpoam_int_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_type_int_clr1_reg[] = {
+	{ "fifo_int_clr", DPP_FIELD_FLAG_WO, 1, 1, 0x0, 0x0 },
+	{ "pon_protect_int_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_interrupt_mask_reg[] = {
+	{ "fifo_interrupt_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "pon_protect_interruptmask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "tpma_interrupt_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "ethma_interrupt_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "bfd_interrupt_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "ethoam_interrupt_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "tpbfd_interrupt_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "tpoam_interrupt_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_int0_index_reg[] = {
+	{ "int0_index0", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_int1_index_reg[] = {
+	{ "int1_index0", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_int0_index_region_reg[] = {
+	{ "int0_index_region", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_int1_index_region_reg[] = {
+	{ "int1_index_region", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_bdiinfo_fwft_fifo_th_reg[] = {
+	{ "bdiinfo_fwft_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_recsec_fwft_fifo_th_reg[] = {
+	{ "recsec_fwft_fifo_th", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_timing_chk_info0_fwft_fifo_th_reg[] = {
+	{ "timing_chk_info0_fwft_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_recma_fwft_fifo_th_reg[] = {
+	{ "recma_fwft_fifo_th", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_timing_chk_info1_fwft_fifo_th_reg[] = {
+	{ "timing_chk_info1_fwft_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_oam_txinst_fifo_th_reg[] = {
+	{ "oam_txinst_fifo_th", DPP_FIELD_FLAG_RW, 10, 11, 0x300, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_oam_rdinfo_fwft_fifo_th_reg[] = {
+	{ "oam_rdinfo_fwft_fifo_th", DPP_FIELD_FLAG_RW, 9, 10, 0x180, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_lm_cnt_fwft_fifo_th_reg[] = {
+	{ "lm_cnt_fwft_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_oam_pkt_fifo_th_reg[] = {
+	{ "oam_pkt_fifo_th", DPP_FIELD_FLAG_RW, 9, 10, 0x180, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_reclm_stat_fifo_th_reg[] = {
+	{ "reclm_stat_fifo_th", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_txlm_stat_fifo_th_reg[] = {
+	{ "txlm_stat_fifo_th", DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_oam_chk_fwft_fifo_th_reg[] = {
+	{ "oam_chk_fwft_fifo_th", DPP_FIELD_FLAG_RW, 9, 10, 0x180, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_txoam_stat_fifo_th_reg[] = {
+	{ "txoam_stat_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_recoam_stat_fifo_th_reg[] = {
+	{ "recoam_stat_fifo_th", DPP_FIELD_FLAG_RW, 6, 7, 0x30, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_txpkt_data_fwft_fifo_th_reg[] = {
+	{ "txpkt_data_fwft_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0xc0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_tstpkt_fwft_fifo_th_reg[] = {
+	{ "tstpkt_fwft_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0x80, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_tst_txinst_fwft_fifo_th_reg[] = {
+	{ "tst_txinst_fwft_fifo_th", DPP_FIELD_FLAG_RW, 4, 5, 0x8, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_tstrx_main_en_reg[] = {
+	{ "tstrx_main_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_tsttx_cfg_para_tbl2_reg[] = {
+	{ "ddr_self_test_tx_en", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0 },
+	{ "tm_self_test_tx_en", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0 },
+	{ "fast_aging_tx_en", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0 },
+	{ "timing_aging_tx_en", DPP_FIELD_FLAG_RW, 13, 1, 0x0, 0x0 },
+	{ "backgroud_flow_tx_en", DPP_FIELD_FLAG_RW, 12, 1, 0x0, 0x0 },
+	{ "tsttx_tx_en", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0 },
+	{ "tx_freq", DPP_FIELD_FLAG_RW, 10, 3, 0x1, 0x0 },
+	{ "tx_offset", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_tsttx_cfg_para_tbl1_reg[] = {
+	{ "tx_count", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_tsttx_cfg_para_tbl0_reg[] = {
+	{ "fast_tx_mode_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "tsttx_tx_head_len", DPP_FIELD_FLAG_RW, 30, 15, 0x0, 0x0 },
+	{ "tsttx_tx_interval", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_tstrx_cfg_para_reg[] = {
+	{ "tstrx_session_num", DPP_FIELD_FLAG_RW, 16, 16, 0x0, 0x0 },
+	{ "tstrx_session_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_en_0_reg[] = {
+	{ "fifo_status_int_en_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_en_1_reg[] = {
+	{ "fifo_status_int_en_41", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_40", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_39", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_38", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_37", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_36", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "fifo_status_int_en_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_mask_0_reg[] = {
+	{ "fifo_status_int_mask_31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_mask_1_reg[] = {
+	{ "fifo_status_int_mask_41", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_40", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_39", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_38", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_37", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_36", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_35", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_34", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_33", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "fifo_status_int_mask_32", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_status_reg[] = {
+	{ "fifo_status_int_status", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_main_frequency_reg[] = {
+	{ "main_frequency", DPP_FIELD_FLAG_RW, 9, 10, 0x258, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_oam_cfg_type_reg[] = {
+	{ "oam_cfg_type", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_fst_swch_eth_head0_reg[] = {
+	{ "fst_swch_eth_head", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_fst_swch_eth_head1_reg[] = {
+	{ "fst_swch_eth_head1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_fst_swch_eth_head2_reg[] = {
+	{ "fst_swch_eth_head2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_fst_swch_eth_head3_reg[] = {
+	{ "fst_swch_eth_head3", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_oam_fs_txinst_fifo_th_reg[] = {
+	{ "oam_fs_txinst_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0x1f4, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_oam_ma_fs_txinst_fifo_th_reg[] = {
+	{ "oam_ma_fs_txinst_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0x1f4, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_pon_int_ram_clr_reg[] = {
+	{ "pon_int_ram_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_pon_p_int_index_reg[] = {
+	{ "pon_p_int_index", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_pon_protect_pkt_fifo_th_reg[] = {
+	{ "pon_protect_pkt_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0x1f4, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_pon_laser_off_en_reg[] = {
+	{ "pon_laser_off_en", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_pon_prtct_pkt_tx_en_reg[] = {
+	{ "pon_prtct_pkt_tx_en", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_cfg_pon_master_reg[] = {
+	{ "cfg_pon_master", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_level_mode_reg[] = {
+	{ "level_mode", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_interrupt_en_reg[] = {
+	{ "interrupt_en", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_pon_laser_on_en_reg[] = {
+	{ "pon_laser_on_en", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ti_pon_sd_reg[] = {
+	{ "ti_pon_sd", DPP_FIELD_FLAG_RW, 7, 8, 0x2, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ti_pon_los_reg[] = {
+	{ "ti_pon_los", DPP_FIELD_FLAG_RW, 7, 8, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_dat4_reg[] = {
+	{ "ind_dat4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_dat5_reg[] = {
+	{ "ind_dat5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_dat6_reg[] = {
+	{ "ind_dat6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_dat7_reg[] = {
+	{ "ind_dat7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_dat8_reg[] = {
+	{ "ind_dat8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_dat9_reg[] = {
+	{ "ind_dat9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_dat10_reg[] = {
+	{ "ind_dat10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_dat11_reg[] = {
+	{ "ind_dat11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_dat12_reg[] = {
+	{ "ind_dat12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_dat13_reg[] = {
+	{ "ind_dat13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_dat14_reg[] = {
+	{ "ind_dat14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ind_dat15_reg[] = {
+	{ "ind_dat15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_oam_2544_pkt_fifo_th_reg[] = {
+	{ "oam_2544_pkt_fifo_th", DPP_FIELD_FLAG_RW, 8, 9, 0xc0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_txinfo_ram_clr_reg[] = {
+	{ "txinfo_ram_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_txinfo_ram_init_done_reg[] = {
+	{ "txinfo_ram_init_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_status40_reg[] = {
+	{ "fifo_status_int_status40", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_fifo_status_int_status41_reg[] = {
+	{ "fifo_status_int_status41", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_oam_2544_fun_en_reg[] = {
+	{ "oam_2544_fun_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_oam_2544_stat_clr_reg[] = {
+	{ "oam_2544_stat_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_txdis_default_reg[] = {
+	{ "txdis_default", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_txdis_default_en_reg[] = {
+	{ "txdis_default_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_tpbfd_firstchk_th_reg[] = {
+	{ "tpbfd_firstchk_th", DPP_FIELD_FLAG_RW, 18, 19, 0xc350, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_ethccm_firstchk_th_reg[] = {
+	{ "ethccm_firstchk_th", DPP_FIELD_FLAG_RW, 18, 19, 0xc350, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_tpccm_firstchk_th_reg[] = {
+	{ "tpccm_firstchk_th", DPP_FIELD_FLAG_RW, 18, 19, 0xc350, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_txstat_req_cnt_reg[] = {
+	{ "txstat_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_chkstat_req_cnt_reg[] = {
+	{ "chkstat_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_stat_oam_fc_cnt_reg[] = {
+	{ "stat1_oam_fc_cnt", DPP_FIELD_FLAG_RC, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_bfdseq_req_cnt_reg[] = {
+	{ "bfdseq_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_lmcnt_req_cnt_reg[] = {
+	{ "lmcnt_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_stat_oam_lm_rsp_cnt_reg[] = {
+	{ "stat2_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_stat_oam_lm_fc_cnt_reg[] = {
+	{ "stat2_oam_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_se_req_cnt_reg[] = {
+	{ "se_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_se_rsp_cnt_reg[] = {
+	{ "se_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_se_oam_fc_cnt_reg[] = {
+	{ "se_oam_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_oam_se_fc_cnt_reg[] = {
+	{ "oam_se_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_oam_pktrx_sop_cnt_reg[] = {
+	{ "oam_pktrx_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_oam_pktrx_eop_cnt_reg[] = {
+	{ "oam_pktrx_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_pktrx_oam_fc_cnt_reg[] = {
+	{ "pktrx_oam_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_pktrx_oam_tst_fc_cnt_reg[] = {
+	{ "pktrx_oam_tst_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_odma_oam_sop_cnt_reg[] = {
+	{ "odma_oam_sop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_odma_oam_eop_cnt_reg[] = {
+	{ "odma_oam_eop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_oam_odma_fc_cnt_reg[] = {
+	{ "oam_odma_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_rec_ma_pkt_illegal_cnt_reg[] = {
+	{ "rec_ma_pkt_illegal_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_rec_rmep_pkt_illegal_cnt_reg[] = {
+	{ "rec_rmep_pkt_illegal_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_rec_eth_ais_pkt_cnt_reg[] = {
+	{ "rec_eth_ais_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_rec_tp_ais_pkt_cnt_reg[] = {
+	{ "rec_tp_ais_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_rec_tp_csf_pkt_cnt_reg[] = {
+	{ "rec_tp_csf_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_rec_eth_level_defect_cnt_reg[] = {
+	{ "rec_eth_level_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_rec_eth_megid_defect_cnt_reg[] = {
+	{ "rec_eth_megid_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_rec_eth_mepid_defect_cnt_reg[] = {
+	{ "rec_eth_mepid_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_rec_eth_interval_defect_cnt_reg[] = {
+	{ "rec_eth_interval_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_rec_sess_unenable_cnt_reg[] = {
+	{ "rec_sess_unenable_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_oam_2544_rd_pkt_cnt_reg[] = {
+	{ "oam_2544_rd_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_debug_cnt_clr_reg[] = {
+	{ "debug_cnt_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_oam_pktrx_catch_data_reg[] = {
+	{ "oam_pktrx_catch_data", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_odma_oam_catch_data_reg[] = {
+	{ "odma_oam_catch_data", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_tst_session_tx_cnt_reg[] = {
+	{ "tst_session_tx_cnt", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_tst_session_rx_cnt_reg[] = {
+	{ "tst_session_rx_cnt", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_tstrx_lost_cnt_reg[] = {
+	{ "tstrx_lost_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_bfdseq_wr_cnt_reg[] = {
+	{ "bfdseq_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_bfdtime_wr_cnt_reg[] = {
+	{ "bfdtime_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_lmcnt_wr_cnt_reg[] = {
+	{ "lmcnt_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_oam_fs_pkt_cnt_reg[] = {
+	{ "oam_fs_pkt_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_oam_ma_fs_pkt_cnt_reg[] = {
+	{ "lmcnt_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_rec_tp_level_defect_cnt_reg[] = {
+	{ "rec_tp_level_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_rec_tp_megid_defect_cnt_reg[] = {
+	{ "rec_tp_megid_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_rec_tp_mepid_defect_cnt_reg[] = {
+	{ "rec_tp_mepid_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_rec_tp_interval_defect_cnt_reg[] = {
+	{ "rec_tp_interval_defect_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_rd_reg_clear_mode_reg[] = {
+	{ "rd_clear_mode_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_stat_rd_data_reg_clear_mode_reg[] = {
+	{ "rd_data_reg_clear_mode_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_indir_oam_int_status_ram_0_reg[] = {
+	{ "bfd_diag_value_bit4", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "bfd_diag_value_bit3", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "bfd_diag_value_bit2", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "bfd_diag_value_bit1", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "bfd_diag_value_bit0", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "dloc_int", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "drdi_int", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_indir_oam_int_status_ram1_reg[] = {
+	{ "sticky_error_level_defect", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "sticky_error_megid_defect", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "sticky_error_mepid_defect", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "sticky_error_inter_defect", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "sticky_ais_defect", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "sticky_csf_defect", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "current_error_level_defect", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "current_error_megid_defect", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "current_error_mepid_defect", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "current_error_inter_defect", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "current_ais_defect", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "current_csf_defect", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_indir_tst_pkt_tx_para_ram_reg[] = {
+	{ "ddr_self_test_tx_en", DPP_FIELD_FLAG_RW, 80, 1, 0x0, 0x0 },
+	{ "tm_self_test_tx_en", DPP_FIELD_FLAG_RW, 79, 1, 0x0, 0x0 },
+	{ "fast_aging_tx_en", DPP_FIELD_FLAG_RW, 78, 1, 0x0, 0x0 },
+	{ "timing_aging_tx_en", DPP_FIELD_FLAG_RW, 77, 1, 0x0, 0x0 },
+	{ "backgroud_flow_tx_en", DPP_FIELD_FLAG_RW, 76, 1, 0x0, 0x0 },
+	{ "tsttx_session_en", DPP_FIELD_FLAG_RW, 75, 1, 0x0, 0x0 },
+	{ "tx_freq", DPP_FIELD_FLAG_RW, 74, 3, 0x0, 0x0 },
+	{ "tx_offset", DPP_FIELD_FLAG_RW, 71, 8, 0x0, 0x0 },
+	{ "tx_count", DPP_FIELD_FLAG_RW, 63, 32, 0x0, 0x0 },
+	{ "fast_tx_mode_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "tsttx_pkthead_len", DPP_FIELD_FLAG_RW, 30, 15, 0x0, 0x0 },
+	{ "tsttx_interval", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_indir_groupnumram_reg[] = {
+	{ "mep_down_num", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_indir_oam_tx_tbl_ram_reg[] = {
+	{ "oam_tx_en", DPP_FIELD_FLAG_RW, 62, 1, 0x0, 0x0 },
+	{ "oam_tx_type", DPP_FIELD_FLAG_RW, 61, 4, 0x0, 0x0 },
+	{ "oam_fetch_len", DPP_FIELD_FLAG_RW, 57, 14, 0x0, 0x0 },
+	{ "bfd_seq_tx_en", DPP_FIELD_FLAG_RW, 43, 1, 0x0, 0x0 },
+	{ "tx_para", DPP_FIELD_FLAG_RW, 42, 7, 0x0, 0x0 },
+	{ "oam_tx_interval", DPP_FIELD_FLAG_RW, 35, 16, 0x0, 0x0 },
+	{ "hd_ena_flag", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0 },
+	{ "last_tx_time", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_indir_oam_chk_tbl_ram_reg[] = {
+	{ "fast_switch_en", DPP_FIELD_FLAG_RW, 55, 1, 0x0, 0x0 },
+	{ "oam_chk_en", DPP_FIELD_FLAG_RW, 54, 1, 0x0, 0x0 },
+	{ "oam_chk_type", DPP_FIELD_FLAG_RW, 53, 4, 0x0, 0x0 },
+	{ "ccm_predel_flag", DPP_FIELD_FLAG_RW, 49, 1, 0x0, 0x0 },
+	{ "lm_chk_en", DPP_FIELD_FLAG_RW, 48, 1, 0x0, 0x0 },
+	{ "ccm_group_id", DPP_FIELD_FLAG_RW, 47, 12, 0x0, 0x0 },
+	{ "oam_chk_internal", DPP_FIELD_FLAG_RW, 35, 16, 0x0, 0x0 },
+	{ "fist_chk_flag", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0 },
+	{ "last_chk_time", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_indir_oam_ma_chk_tbl_ram_reg[] = {
+	{ "ma_fast_switch_en", DPP_FIELD_FLAG_RW, 141, 1, 0x0, 0x0 },
+	{ "ma_chk_en", DPP_FIELD_FLAG_RW, 140, 1, 0x0, 0x0 },
+	{ "ma_type", DPP_FIELD_FLAG_RW, 139, 1, 0x0, 0x0 },
+	{ "error_level_defect_en", DPP_FIELD_FLAG_RW, 138, 1, 0x0, 0x0 },
+	{ "error_megid_defect_en", DPP_FIELD_FLAG_RW, 137, 1, 0x0, 0x0 },
+	{ "error_mepid_defect_en", DPP_FIELD_FLAG_RW, 136, 1, 0x0, 0x0 },
+	{ "error_inter_defect_en", DPP_FIELD_FLAG_RW, 135, 1, 0x0, 0x0 },
+	{ "ais_defect_en", DPP_FIELD_FLAG_RW, 134, 1, 0x0, 0x0 },
+	{ "csf_defect_en", DPP_FIELD_FLAG_RW, 133, 1, 0x0, 0x0 },
+	{ "error_level_defect_ccm", DPP_FIELD_FLAG_RW, 132, 3, 0x0, 0x0 },
+	{ "error_megid_defect_ccm", DPP_FIELD_FLAG_RW, 129, 3, 0x0, 0x0 },
+	{ "error_mepid_defect_ccm", DPP_FIELD_FLAG_RW, 126, 3, 0x0, 0x0 },
+	{ "error_inter_defect_ccm", DPP_FIELD_FLAG_RW, 123, 3, 0x0, 0x0 },
+	{ "ais_defect_ccm", DPP_FIELD_FLAG_RW, 120, 3, 0x0, 0x0 },
+	{ "csf_defect_ccm", DPP_FIELD_FLAG_RW, 117, 3, 0x0, 0x0 },
+	{ "ma_predel_en", DPP_FIELD_FLAG_RW, 114, 1, 0x0, 0x0 },
+	{ "error_level_defect_ts", DPP_FIELD_FLAG_RO, 113, 19, 0x0, 0x0 },
+	{ "error_megid_defect_ts", DPP_FIELD_FLAG_RO, 94, 19, 0x0, 0x0 },
+	{ "error_mepid_defect_ts", DPP_FIELD_FLAG_RO, 75, 19, 0x0, 0x0 },
+	{ "error_inter_defect_ts", DPP_FIELD_FLAG_RO, 56, 19, 0x0, 0x0 },
+	{ "ais_defect_ts", DPP_FIELD_FLAG_RO, 37, 19, 0x0, 0x0 },
+	{ "csf_defect_ts", DPP_FIELD_FLAG_RO, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_nppu_oam_cfg_indir_oam_2544_tx_ram_reg[] = {
+	{ "tx_en_2544", DPP_FIELD_FLAG_RW, 46, 1, 0x0, 0x0 },
+	{ "tx_cfg_times_2544", DPP_FIELD_FLAG_RW, 45, 16, 0x0, 0x0 },
+	{ "current_times", DPP_FIELD_FLAG_RW, 29, 16, 0x0, 0x0 },
+	{ "slice_num", DPP_FIELD_FLAG_RW, 13, 7, 0x0, 0x0 },
+	{ "pkt_mty", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_interrupt_en_r_reg[] = {
+	{ "interrupt_en_r", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_mec_host_interrupt_reg[] = {
+	{ "mec_host_interrupt", DPP_FIELD_FLAG_RO, 5, 6, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_dbg_rtl_date_reg[] = {
+	{ "dbg_rtl_date", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_dup_start_num_cfg_reg[] = {
+	{ "dup_start_num_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_debug_data_write_complete_reg[] = {
+	{ "debug_data_write_complete", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_uc_mc_wrr_cfg_reg[] = {
+	{ "uc_mc_wrr_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_debug_pkt_send_en_reg[] = {
+	{ "debug_pkt_send_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_dup_tbl_ind_access_done_reg[] = {
+	{ "dup_tbl_ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_ppu_demux_fifo_interrupt_mask_reg[] = {
+	{ "isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW,
+	  3, 1, 0x1, 0x0 },
+	{ "isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "isu_in_fifo_64x81_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1,
+	  0x1, 0x0 },
+	{ "isu_in_fifo_64x81_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1,
+	  0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_multicast_fifo_interrupt_mask_reg[] = {
+	{ "ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "pf_req_fwft_fifo_16x36_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 17,
+	  1, 0x1, 0x0 },
+	{ "pf_req_fwft_fifo_16x36_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 16,
+	  1, 0x1, 0x0 },
+	{ "pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 15,
+	  1, 0x1, 0x0 },
+	{ "pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 14,
+	  1, 0x1, 0x0 },
+	{ "dup_para_fwft_fifo_16x35_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW,
+	  13, 1, 0x1, 0x0 },
+	{ "dup_para_fwft_fifo_16x35_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW,
+	  12, 1, 0x1, 0x0 },
+	{ "se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW,
+	  11, 1, 0x1, 0x0 },
+	{ "se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW,
+	  10, 1, 0x1, 0x0 },
+	{ "sa_para_fwft_fifo_64x17_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 9,
+	  1, 0x1, 0x0 },
+	{ "sa_para_fwft_fifo_64x17_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 8,
+	  1, 0x1, 0x0 },
+	{ "group_id_fifo_64x16_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 7, 1,
+	  0x1, 0x0 },
+	{ "group_id_fifo_64x16_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1,
+	  0x1, 0x0 },
+	{ "isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW,
+	  3, 1, 0x1, 0x0 },
+	{ "dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "car_flag_fifo_32x1_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1,
+	  0x0 },
+	{ "car_flag_fifo_32x1_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_in_schedule_fifo_interrupt_mask_reg[] = {
+	{ "free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "mc_mf_fifo_16x2048_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1,
+	  0x1, 0x0 },
+	{ "mc_mf_fifo_16x2048_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1,
+	  0x1, 0x0 },
+	{ "uc_mf_fifo_96x2048_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1,
+	  0x1, 0x0 },
+	{ "uc_mf_fifo_96x2048_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1,
+	  0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_mf_out_fifo_interrupt_mask_reg[] = {
+	{ "ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_mask_reg[] = {
+	{ "ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_mask_reg[] = {
+	{ "ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_mccnt_fifo_interrupt_mask_reg[] = {
+	{ "ppu_mccnt_fifo_32x15_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 5, 1,
+	  0x1, 0x0 },
+	{ "ppu_mccnt_fifo_32x15_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1,
+	  0x1, 0x0 },
+	{ "ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 3,
+	  1, 0x1, 0x0 },
+	{ "ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW,
+	  2, 1, 0x1, 0x0 },
+	{ "mccnt_rsp_fifo_32x1_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1,
+	  0x1, 0x0 },
+	{ "mccnt_rsp_fifo_32x1_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1,
+	  0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_mask_l_reg[] = {
+	{ "mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_mask_m_reg[] = {
+	{ "ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_mask", DPP_FIELD_FLAG_RW,
+	  31, 1, 0x1, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "ppu_cop_delay_fifo_48x16_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 29,
+	  1, 0x1, 0x0 },
+	{ "ppu_cop_delay_fifo_48x16_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 28,
+	  1, 0x1, 0x0 },
+	{ "ppu_cop_delay_fifo_16x48_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 27,
+	  1, 0x1, 0x0 },
+	{ "ppu_cop_delay_fifo_16x48_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 26,
+	  1, 0x1, 0x0 },
+	{ "ppu_cop_delay_fifo_16x32_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 25,
+	  1, 0x1, 0x0 },
+	{ "ppu_cop_delay_fifo_16x32_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 24,
+	  1, 0x1, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_mask", DPP_FIELD_FLAG_RW,
+	  23, 1, 0x1, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "ppu_cop_delay_fifo_16x16_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 21,
+	  1, 0x1, 0x0 },
+	{ "ppu_cop_delay_fifo_16x16_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 20,
+	  1, 0x1, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_mask", DPP_FIELD_FLAG_RW,
+	  19, 1, 0x1, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_mask", DPP_FIELD_FLAG_RW,
+	  17, 1, 0x1, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_mask",
+	  DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_mask_h_reg[] = {
+	{ "coprocessor_fwft_fifo_16x80_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 3,
+	  1, 0x1, 0x0 },
+	{ "coprocessor_fwft_fifo_16x80_wrapper_underflow_mask", DPP_FIELD_FLAG_RW,
+	  2, 1, 0x1, 0x0 },
+	{ "ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_ram_check_err_mask_reg[] = {
+	{ "parity_err_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_fifo_interrupt_mask_reg[] = {
+	{ "instrmem2_wr_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "instrmem2_wr_fifo_udf_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "instrmem2_rd_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "instrmem2_rd_fifo_udf_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "instrmem1_wr_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "instrmem1_wr_fifo_udf_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "instrmem1_rd_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "instrmem1_rd_fifo_udf_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "instrmem0_wr_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "instrmem0_wr_fifo_udf_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "instrmem0_rd_fifo_ovf_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "instrmem0_rd_fifo_udf_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_ppu_demux_fifo_interrupt_sta_reg[] = {
+	{ "isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO,
+	  3, 1, 0x0, 0x0 },
+	{ "isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO,
+	  2, 1, 0x0, 0x0 },
+	{ "isu_in_fifo_64x81_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0,
+	  0x0 },
+	{ "isu_in_fifo_64x81_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_multicast_fifo_interrupt_sta_reg[] = {
+	{ "ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_sta",
+	  DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0 },
+	{ "ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0 },
+	{ "pf_req_fwft_fifo_16x36_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 17,
+	  1, 0x0, 0x0 },
+	{ "pf_req_fwft_fifo_16x36_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 16,
+	  1, 0x0, 0x0 },
+	{ "pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 15,
+	  1, 0x0, 0x0 },
+	{ "pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 14,
+	  1, 0x0, 0x0 },
+	{ "dup_para_fwft_fifo_16x35_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 13,
+	  1, 0x0, 0x0 },
+	{ "dup_para_fwft_fifo_16x35_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO,
+	  12, 1, 0x0, 0x0 },
+	{ "se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO,
+	  11, 1, 0x0, 0x0 },
+	{ "se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO,
+	  10, 1, 0x0, 0x0 },
+	{ "sa_para_fwft_fifo_64x17_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 9,
+	  1, 0x0, 0x0 },
+	{ "sa_para_fwft_fifo_64x17_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 8,
+	  1, 0x0, 0x0 },
+	{ "group_id_fifo_64x16_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 7, 1,
+	  0x0, 0x0 },
+	{ "group_id_fifo_64x16_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 6, 1,
+	  0x0, 0x0 },
+	{ "isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO,
+	  5, 1, 0x0, 0x0 },
+	{ "isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO,
+	  3, 1, 0x0, 0x0 },
+	{ "dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO,
+	  2, 1, 0x0, 0x0 },
+	{ "car_flag_fifo_32x1_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0,
+	  0x0 },
+	{ "car_flag_fifo_32x1_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_in_schedule_fifo_interrupt_sta_reg[] = {
+	{ "free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_sta",
+	  DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "mc_mf_fifo_16x2048_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 3, 1,
+	  0x0, 0x0 },
+	{ "mc_mf_fifo_16x2048_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 2, 1,
+	  0x0, 0x0 },
+	{ "uc_mf_fifo_96x2048_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1,
+	  0x0, 0x0 },
+	{ "uc_mf_fifo_96x2048_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_mf_out_fifo_interrupt_sta_reg[] = {
+	{ "ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_sta",
+	  DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0 },
+	{ "ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0 },
+	{ "ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_sta",
+	  DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0 },
+	{ "ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0 },
+	{ "ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_sta",
+	  DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_sta",
+	  DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_sta",
+	  DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_sta",
+	  DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_sta_reg[] = {
+	{ "ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta",
+	  DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0 },
+	{ "ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta",
+	  DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0 },
+	{ "ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta",
+	  DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0 },
+	{ "ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta",
+	  DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0 },
+	{ "ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta",
+	  DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_sta",
+	  DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_sta_reg[] = {
+	{ "ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_sta",
+	  DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_mccnt_fifo_interrupt_sta_reg[] = {
+	{ "ppu_mccnt_fifo_32x15_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 5, 1,
+	  0x0, 0x0 },
+	{ "ppu_mccnt_fifo_32x15_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1,
+	  0x0, 0x0 },
+	{ "ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 3,
+	  1, 0x0, 0x0 },
+	{ "ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 2,
+	  1, 0x0, 0x0 },
+	{ "mccnt_rsp_fifo_32x1_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1,
+	  0x0, 0x0 },
+	{ "mccnt_rsp_fifo_32x1_wrapper_u0_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_sta_l_reg[] = {
+	{ "mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0 },
+	{ "mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0 },
+	{ "mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0 },
+	{ "mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0 },
+	{ "mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO,
+	  27, 1, 0x0, 0x0 },
+	{ "mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0 },
+	{ "mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0 },
+	{ "mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0 },
+	{ "mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0 },
+	{ "mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0 },
+	{ "mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0 },
+	{ "mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0 },
+	{ "mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO,
+	  19, 1, 0x0, 0x0 },
+	{ "mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0 },
+	{ "mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0 },
+	{ "mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0 },
+	{ "mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0 },
+	{ "mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0 },
+	{ "mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0 },
+	{ "mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0 },
+	{ "mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO,
+	  11, 1, 0x0, 0x0 },
+	{ "mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0 },
+	{ "mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0 },
+	{ "mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0 },
+	{ "mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO,
+	  3, 1, 0x0, 0x0 },
+	{ "mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_sta_m_reg[] = {
+	{ "ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_sta", DPP_FIELD_FLAG_RO,
+	  31, 1, 0x0, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_sta", DPP_FIELD_FLAG_RO,
+	  30, 1, 0x0, 0x0 },
+	{ "ppu_cop_delay_fifo_48x16_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 29, 1,
+	  0x0, 0x0 },
+	{ "ppu_cop_delay_fifo_48x16_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 28,
+	  1, 0x0, 0x0 },
+	{ "ppu_cop_delay_fifo_16x48_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 27, 1,
+	  0x0, 0x0 },
+	{ "ppu_cop_delay_fifo_16x48_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 26,
+	  1, 0x0, 0x0 },
+	{ "ppu_cop_delay_fifo_16x32_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 25, 1,
+	  0x0, 0x0 },
+	{ "ppu_cop_delay_fifo_16x32_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 24,
+	  1, 0x0, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_sta", DPP_FIELD_FLAG_RO,
+	  23, 1, 0x0, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_sta", DPP_FIELD_FLAG_RO,
+	  22, 1, 0x0, 0x0 },
+	{ "ppu_cop_delay_fifo_16x16_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 21, 1,
+	  0x0, 0x0 },
+	{ "ppu_cop_delay_fifo_16x16_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 20,
+	  1, 0x0, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_sta", DPP_FIELD_FLAG_RO,
+	  19, 1, 0x0, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_sta", DPP_FIELD_FLAG_RO,
+	  18, 1, 0x0, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_sta", DPP_FIELD_FLAG_RO,
+	  17, 1, 0x0, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_sta", DPP_FIELD_FLAG_RO,
+	  16, 1, 0x0, 0x0 },
+	{ "mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0 },
+	{ "mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0 },
+	{ "mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0 },
+	{ "mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0 },
+	{ "mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO,
+	  11, 1, 0x0, 0x0 },
+	{ "mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0 },
+	{ "mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0 },
+	{ "mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0 },
+	{ "mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flg_sta", DPP_FIELD_FLAG_RO,
+	  3, 1, 0x0, 0x0 },
+	{ "mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flg_sta",
+	  DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_sta_h_reg[] = {
+	{ "ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_sta",
+	  DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_sta",
+	  DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_fifo_interrupt_sta_reg[] = {
+	{ "instrmem1_wr_fifo_ovf_sta", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "instrmem1_wr_fifo_udf_sta", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "instrmem1_rd_fifo_ovf_sta", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "instrmem1_rd_fifo_udf_sta", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "instrmem0_wr_fifo_ovf_sta", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "instrmem0_wr_fifo_udf_sta", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "instrmem0_rd_fifo_ovf_sta", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "instrmem0_rd_fifo_udf_sta", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_ram_check_ecc_err_flag_1_reg[] = {
+	{ "ecc_single_err_sa_para_fifo_int_flag", DPP_FIELD_FLAG_RC, 25, 1, 0x0,
+	  0x0 },
+	{ "ecc_double_err_sa_para_fifo_int_flag", DPP_FIELD_FLAG_RC, 24, 1, 0x0,
+	  0x0 },
+	{ "ecc_single_err_dup_para_fifo_int_flag", DPP_FIELD_FLAG_RC, 23, 1, 0x0,
+	  0x0 },
+	{ "ecc_double_err_dup_para_fifo_int_flag", DPP_FIELD_FLAG_RC, 22, 1, 0x0,
+	  0x0 },
+	{ "ecc_single_err_pf_rsp_fifo_int_flag", DPP_FIELD_FLAG_RC, 21, 1, 0x0,
+	  0x0 },
+	{ "ecc_double_err_pf_rsp_fifo_int_flag", DPP_FIELD_FLAG_RC, 20, 1, 0x0,
+	  0x0 },
+	{ "ecc_single_err_pf_req_fifo_int_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0,
+	  0x0 },
+	{ "ecc_double_err_pf_req_fifo_int_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0,
+	  0x0 },
+	{ "ecc_single_err_ppu_reorder_link_ram0_int_flag", DPP_FIELD_FLAG_RC, 17, 1,
+	  0x0, 0x0 },
+	{ "ecc_double_err_ppu_reorder_link_ram0_int_flag", DPP_FIELD_FLAG_RC, 16, 1,
+	  0x0, 0x0 },
+	{ "ecc_single_err_ppu_reorder_link_ram1_int_flag", DPP_FIELD_FLAG_RC, 15, 1,
+	  0x0, 0x0 },
+	{ "ecc_double_err_ppu_reorder_link_ram1_int_flag", DPP_FIELD_FLAG_RC, 14, 1,
+	  0x0, 0x0 },
+	{ "ecc_single_err_ppu_reorder_link_flag_array_ram0_int_flag",
+	  DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ecc_single_err_ppu_reorder_link_flag_array_ram1_int_flag",
+	  DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ecc_single_err_ppu_reorder_ifb_ram_int_flag", DPP_FIELD_FLAG_RC, 11, 1,
+	  0x0, 0x0 },
+	{ "ecc_double_err_ppu_reorder_ifb_ram_int_flag", DPP_FIELD_FLAG_RC, 10, 1,
+	  0x0, 0x0 },
+	{ "ecc_single_err_ppu_reorder_flag_array_ram0_int_flag", DPP_FIELD_FLAG_RC,
+	  9, 1, 0x0, 0x0 },
+	{ "ecc_single_err_ppu_reorder_flag_array_ram1_int_flag", DPP_FIELD_FLAG_RC,
+	  8, 1, 0x0, 0x0 },
+	{ "ecc_single_err_ppu_reorder_flag_ram0_int_flag", DPP_FIELD_FLAG_RC, 7, 1,
+	  0x0, 0x0 },
+	{ "ecc_single_err_ppu_reorder_flag_ram1_int_flag", DPP_FIELD_FLAG_RC, 6, 1,
+	  0x0, 0x0 },
+	{ "ecc_single_err_uc_mf_fifo_int_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ecc_double_err_uc_mf_fifo_int_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ecc_single_err_mc_mf_fifo_int_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ecc_double_err_mc_mf_fifo_int_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ecc_single_err_free_global_num_fifo_int_flag", DPP_FIELD_FLAG_RC, 1, 1,
+	  0x0, 0x0 },
+	{ "ecc_double_err_free_global_num_fifo_int_flag", DPP_FIELD_FLAG_RC, 0, 1,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_ppu_demux_fifo_interrupt_flag_reg[] = {
+	{ "isu_in_para_fwft_fifo_32x81_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC,
+	  3, 1, 0x0, 0x0 },
+	{ "isu_in_para_fwft_fifo_32x81_wrapper_u0_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "isu_in_fifo_64x81_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1,
+	  0x0, 0x0 },
+	{ "isu_in_fifo_64x81_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_multicast_fifo_interrupt_flag_reg[] = {
+	{ "ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ppu_pktrx_mc_ptr_fifo_16384x17_wrapper_u0_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "pf_req_fwft_fifo_16x36_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 17,
+	  1, 0x0, 0x0 },
+	{ "pf_req_fwft_fifo_16x36_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 16,
+	  1, 0x0, 0x0 },
+	{ "pf_rsp_fwft_fifo_32x34_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RO, 15,
+	  1, 0x0, 0x0 },
+	{ "pf_rsp_fwft_fifo_32x34_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 14,
+	  1, 0x0, 0x0 },
+	{ "dup_para_fwft_fifo_16x35_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC,
+	  13, 1, 0x0, 0x0 },
+	{ "dup_para_fwft_fifo_16x35_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC,
+	  12, 1, 0x0, 0x0 },
+	{ "se_mc_rsp_fwft_fifo_32x17_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC,
+	  11, 1, 0x0, 0x0 },
+	{ "se_mc_rsp_fwft_fifo_32x17_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC,
+	  10, 1, 0x0, 0x0 },
+	{ "sa_para_fwft_fifo_64x17_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 9,
+	  1, 0x0, 0x0 },
+	{ "sa_para_fwft_fifo_64x17_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 8,
+	  1, 0x0, 0x0 },
+	{ "group_id_fifo_64x16_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1,
+	  0x0, 0x0 },
+	{ "group_id_fifo_64x16_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1,
+	  0x0, 0x0 },
+	{ "isu_mc_para_fwft_fifo_128x34_wrapper_u0_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "isu_mc_para_fwft_fifo_128x34_wrapper_u0_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "dup_freeptr_fwft_fifo_128x7_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC,
+	  3, 1, 0x0, 0x0 },
+	{ "dup_freeptr_fwft_fifo_128x7_wrapper_u0_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "car_flag_fifo_32x1_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0,
+	  0x0 },
+	{ "car_flag_fifo_32x1_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_in_schedule_fifo_interrupt_flag_reg[] = {
+	{ "free_global_num_fwft_fifo_8192x13_wrapper_u0_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "free_global_num_fwft_fifo_8192x13_wrapper_u0_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "mc_mf_fifo_16x2048_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1,
+	  0x0, 0x0 },
+	{ "mc_mf_fifo_16x2048_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1,
+	  0x0, 0x0 },
+	{ "uc_mf_fifo_96x2048_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1,
+	  0x0, 0x0 },
+	{ "uc_mf_fifo_96x2048_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_mf_out_fifo_interrupt_flag_reg[] = {
+	{ "ppu_cluster5_mf_out_afifo_32x2048_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ppu_cluster5_mf_out_afifo_32x2048_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ppu_cluster4_mf_out_afifo_32x2048_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ppu_cluster4_mf_out_afifo_32x2048_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ppu_cluster3_mf_out_afifo_32x2048_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ppu_cluster3_mf_out_afifo_32x2048_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ppu_cluster2_mf_out_afifo_32x2048_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ppu_cluster2_mf_out_afifo_32x2048_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ppu_cluster1_mf_out_afifo_32x2048_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ppu_cluster1_mf_out_afifo_32x2048_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ppu_cluster0_mf_out_afifo_32x2048_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ppu_cluster0_mf_out_afifo_32x2048_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_flag_reg[] = {
+	{ "ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ppu_cluster5_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ppu_cluster4_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ppu_cluster3_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ppu_cluster2_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ppu_cluster1_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ppu_cluster0_pbu_mcode_pf_req_afifo_32x15_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_flag_reg[] = {
+	{ "ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0r_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ppu_pbu_mcode_pf_rsp_afifo_64x16_wrapper_u0_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_mccnt_fifo_interrupt_flag_reg[] = {
+	{ "ppu_mccnt_fifo_32x15_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1,
+	  0x0, 0x0 },
+	{ "ppu_mccnt_fifo_32x15_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1,
+	  0x0, 0x0 },
+	{ "ppu_wb_data_fifo_32x2048_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 3,
+	  1, 0x0, 0x0 },
+	{ "ppu_wb_data_fifo_32x2048_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC,
+	  2, 1, 0x0, 0x0 },
+	{ "mccnt_rsp_fifo_32x1_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1,
+	  0x0, 0x0 },
+	{ "mccnt_rsp_fifo_32x1_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_flag_l_reg[] = {
+	{ "mec3_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC,
+	  31, 1, 0x0, 0x0 },
+	{ "mec3_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC,
+	  30, 1, 0x0, 0x0 },
+	{ "mec3_cop_key_checksum_fifo_32x180_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "mec3_cop_key_checksum_fifo_32x180_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "mec3_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC,
+	  27, 1, 0x0, 0x0 },
+	{ "mec3_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC,
+	  26, 1, 0x0, 0x0 },
+	{ "mec3_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "mec3_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "mec2_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC,
+	  23, 1, 0x0, 0x0 },
+	{ "mec2_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC,
+	  22, 1, 0x0, 0x0 },
+	{ "mec2_cop_key_checksum_fifo_32x180_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "mec2_cop_key_checksum_fifo_32x180_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "mec2_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC,
+	  19, 1, 0x0, 0x0 },
+	{ "mec2_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC,
+	  18, 1, 0x0, 0x0 },
+	{ "mec2_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "mec2_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "mec1_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC,
+	  15, 1, 0x0, 0x0 },
+	{ "mec1_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC,
+	  14, 1, 0x0, 0x0 },
+	{ "mec1_cop_key_checksum_fifo_32x180_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "mec1_cop_key_checksum_fifo_32x180_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "mec1_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC,
+	  11, 1, 0x0, 0x0 },
+	{ "mec1_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC,
+	  10, 1, 0x0, 0x0 },
+	{ "mec1_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "mec1_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "mec0_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC,
+	  7, 1, 0x0, 0x0 },
+	{ "mec0_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC,
+	  6, 1, 0x0, 0x0 },
+	{ "mec0_cop_key_checksum_fifo_32x180_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "mec0_cop_key_checksum_fifo_32x180_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "mec0_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 3,
+	  1, 0x0, 0x0 },
+	{ "mec0_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC,
+	  2, 1, 0x0, 0x0 },
+	{ "mec0_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "mec0_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_flag_m_reg[] = {
+	{ "ppu_cop_result_fwft_fifo_80x80_wrapper_overflow_flag", DPP_FIELD_FLAG_RC,
+	  31, 1, 0x0, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_80x80_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ppu_cop_delay_fifo_48x16_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 29,
+	  1, 0x0, 0x0 },
+	{ "ppu_cop_delay_fifo_48x16_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 28,
+	  1, 0x0, 0x0 },
+	{ "ppu_cop_delay_fifo_16x48_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 27,
+	  1, 0x0, 0x0 },
+	{ "ppu_cop_delay_fifo_16x48_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 26,
+	  1, 0x0, 0x0 },
+	{ "ppu_cop_delay_fifo_16x32_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 25,
+	  1, 0x0, 0x0 },
+	{ "ppu_cop_delay_fifo_16x32_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 24,
+	  1, 0x0, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_96x80_wrapper_overflow_flag", DPP_FIELD_FLAG_RC,
+	  23, 1, 0x0, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_96x80_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ppu_cop_delay_fifo_16x16_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 21,
+	  1, 0x0, 0x0 },
+	{ "ppu_cop_delay_fifo_16x16_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 20,
+	  1, 0x0, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_32x80_wrapper_overflow_flag", DPP_FIELD_FLAG_RC,
+	  19, 1, 0x0, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_32x80_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_16x80_wrapper_overflow_flag", DPP_FIELD_FLAG_RC,
+	  17, 1, 0x0, 0x0 },
+	{ "ppu_cop_result_fwft_fifo_16x80_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "mec5_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC,
+	  15, 1, 0x0, 0x0 },
+	{ "mec5_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC,
+	  14, 1, 0x0, 0x0 },
+	{ "mec5_cop_key_checksum_fifo_32x180_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "mec5_cop_key_checksum_fifo_32x180_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "mec5_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC,
+	  11, 1, 0x0, 0x0 },
+	{ "mec5_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC,
+	  10, 1, 0x0, 0x0 },
+	{ "mec5_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "mec5_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "mec4_cop_key_crc_fifo_32x625_wrapper_overflow_flag", DPP_FIELD_FLAG_RC,
+	  7, 1, 0x0, 0x0 },
+	{ "mec4_cop_key_crc_fifo_32x625_wrapper_underflow_flag", DPP_FIELD_FLAG_RC,
+	  6, 1, 0x0, 0x0 },
+	{ "mec4_cop_key_checksum_fifo_32x180_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "mec4_cop_key_checksum_fifo_32x180_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "mec4_cop_key_mul_fifo_32x52_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 3,
+	  1, 0x0, 0x0 },
+	{ "mec4_cop_key_mul_fifo_32x52_wrapper_underflow_flag", DPP_FIELD_FLAG_RC,
+	  2, 1, 0x0, 0x0 },
+	{ "mec4_cop_key_random_mod_fifo_32x44_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "mec4_cop_key_random_mod_fifo_32x44_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_coprocessor_fifo_interrupt_flag_h_reg[] = {
+	{ "ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ppu_cop_random_mod_para_delay_fifo_48x16_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_fifo_interrupt_flag_reg[] = {
+	{ "instrmem2_wr_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "instrmem2_wr_fifo_udf_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "instrmem2_rd_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "instrmem2_rd_fifo_udf_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "instrmem1_wr_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "instrmem1_wr_fifo_udf_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "instrmem1_rd_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "instrmem1_rd_fifo_udf_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "instrmem0_wr_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "instrmem0_wr_fifo_udf_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "instrmem0_rd_fifo_ovf_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "instrmem0_rd_fifo_udf_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_ram_int_out_reg[] = {
+	{ "instrmem2_bank3_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 11, 1, 0x0,
+	  0x0 },
+	{ "instrmem2_bank2_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 10, 1, 0x0,
+	  0x0 },
+	{ "instrmem2_bank1_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 9, 1, 0x0,
+	  0x0 },
+	{ "instrmem2_bank0_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 8, 1, 0x0,
+	  0x0 },
+	{ "instrmem1_bank3_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 7, 1, 0x0,
+	  0x0 },
+	{ "instrmem1_bank2_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 6, 1, 0x0,
+	  0x0 },
+	{ "instrmem1_bank1_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 5, 1, 0x0,
+	  0x0 },
+	{ "instrmem1_bank0_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 4, 1, 0x0,
+	  0x0 },
+	{ "instrmem0_bank3_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 3, 1, 0x0,
+	  0x0 },
+	{ "instrmem0_bank2_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 2, 1, 0x0,
+	  0x0 },
+	{ "instrmem0_bank1_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 1, 1, 0x0,
+	  0x0 },
+	{ "instrmem0_bank0_ram_parity_err_int_out", DPP_FIELD_FLAG_RO, 0, 1, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_ram_int_mask_reg[] = {
+	{ "instrmem2_bank3_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1,
+	  0x0 },
+	{ "instrmem2_bank2_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1,
+	  0x0 },
+	{ "instrmem2_bank1_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1,
+	  0x0 },
+	{ "instrmem2_bank0_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1,
+	  0x0 },
+	{ "instrmem1_bank3_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1,
+	  0x0 },
+	{ "instrmem1_bank2_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1,
+	  0x0 },
+	{ "instrmem1_bank1_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1,
+	  0x0 },
+	{ "instrmem1_bank0_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1,
+	  0x0 },
+	{ "instrmem0_bank3_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1,
+	  0x0 },
+	{ "instrmem0_bank2_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1,
+	  0x0 },
+	{ "instrmem0_bank1_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1,
+	  0x0 },
+	{ "instrmem0_bank0_ram_parity_err_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_ram_int_stat_reg[] = {
+	{ "instrmem2_bank3_ram_parity_errstat", DPP_FIELD_FLAG_RO, 11, 1, 0x0,
+	  0x0 },
+	{ "instrmem2_bank2_ram_parity_errstat", DPP_FIELD_FLAG_RO, 10, 1, 0x0,
+	  0x0 },
+	{ "instrmem2_bank1_ram_parity_errstat", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0 },
+	{ "instrmem2_bank0_ram_parity_errstat", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0 },
+	{ "instrmem1_bank3_ram_parity_errstat", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "instrmem1_bank2_ram_parity_errstat", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "instrmem1_bank1_ram_parity_errstat", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "instrmem1_bank0_ram_parity_errstat", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "instrmem0_bank3_ram_parity_errstat", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "instrmem0_bank2_ram_parity_errstat", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "instrmem0_bank1_ram_parity_errstat", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "instrmem0_bank0_ram_parity_errstat", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_ram_int_flag_reg[] = {
+	{ "instrmem2_bank3_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0,
+	  0x0 },
+	{ "instrmem2_bank2_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0,
+	  0x0 },
+	{ "instrmem2_bank1_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0,
+	  0x0 },
+	{ "instrmem2_bank0_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0,
+	  0x0 },
+	{ "instrmem1_bank3_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0,
+	  0x0 },
+	{ "instrmem1_bank2_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0,
+	  0x0 },
+	{ "instrmem1_bank1_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0,
+	  0x0 },
+	{ "instrmem1_bank0_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0,
+	  0x0 },
+	{ "instrmem0_bank3_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0,
+	  0x0 },
+	{ "instrmem0_bank2_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0,
+	  0x0 },
+	{ "instrmem0_bank1_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0,
+	  0x0 },
+	{ "instrmem0_bank0_ram_parity_err_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_count_cfg_reg[] = {
+	{ "ppu_count_overflow_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "ppu_count_rd_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_statics_cfg_reg[] = {
+	{ "csr_statics_mc_type", DPP_FIELD_FLAG_RW, 24, 1, 0x0, 0x0 },
+	{ "csr_statics_bufnum", DPP_FIELD_FLAG_RW, 22, 7, 0x0, 0x0 },
+	{ "csr_statics_portnum1", DPP_FIELD_FLAG_RW, 15, 8, 0xc1, 0x0 },
+	{ "csr_statics_portnum0", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_statics_wb_cfg_reg[] = {
+	{ "csr_statics_wb_halt_send_type", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "csr_statics_wb_mf_type", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "csr_statics_wb_halt_continue_end", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "csr_statics_wb_dup_flag", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "csr_statics_wb_last_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "csr_statics_wb_dis_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_wr_table_self_rsp_en_cfg_reg[] = {
+	{ "wr_table_self_rsp_en_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_random_arbiter_8to1_cfg_reg[] = {
+	{ "ppu_random_arbiter_8to1_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_reorder_bypass_flow_num_cfg_reg[] = {
+	{ "ppu_reorder_bypass_flow_num_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_cos_meter_cfg_h_reg[] = {
+	{ "cbs", DPP_FIELD_FLAG_RW, 22, 10, 0x3ff, 0x0 },
+	{ "pbs", DPP_FIELD_FLAG_RW, 12, 10, 0x3ff, 0x0 },
+	{ "green_action", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "yellow_action", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "red_action", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_cos_meter_cfg_l_reg[] = {
+	{ "cir", DPP_FIELD_FLAG_RW, 20, 10, 0x24a, 0x0 },
+	{ "pir", DPP_FIELD_FLAG_RW, 10, 10, 0x24a, 0x0 },
+	{ "car_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_rdy_reg[] = {
+	{ "instrmem_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_addr_reg[] = {
+	{ "instrmem_operate", DPP_FIELD_FLAG_WO, 13, 1, 0x0, 0x0 },
+	{ "instrmem_addr", DPP_FIELD_FLAG_WO, 12, 13, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_ind_access_done_reg[] = {
+	{ "instrmem_ind_access_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_instr0_data_l_reg[] = {
+	{ "instrmem_instr0_data_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_instr0_data_h_reg[] = {
+	{ "instrmem_instr0_data_h", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_instr1_data_l_reg[] = {
+	{ "instrmem_instr1_data_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_instr1_data_h_reg[] = {
+	{ "instrmem_instr1_data_h", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_instr2_data_l_reg[] = {
+	{ "instrmem_instr2_data_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_instr2_data_h_reg[] = {
+	{ "instrmem_instr2_data_h", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_instr3_data_l_reg[] = {
+	{ "instrmem_instr3_data_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_instr3_data_h_reg[] = {
+	{ "instrmem_instr3_data_h", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_read_instr0_data_l_reg[] = {
+	{ "instrmem_read_instr0_data_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_read_instr0_data_h_reg[] = {
+	{ "instrmem_read_instr0_data_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_read_instr1_data_l_reg[] = {
+	{ "instrmem_read_instr1_data_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_read_instr1_data_h_reg[] = {
+	{ "instrmem_read_instr1_data_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_read_instr2_data_l_reg[] = {
+	{ "instrmem_read_instr2_data_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_read_instr2_data_h_reg[] = {
+	{ "instrmem_read_instr2_data_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_read_instr3_data_l_reg[] = {
+	{ "instrmem_read_instr3_data_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_instrmem_read_instr3_data_h_reg[] = {
+	{ "instrmem_read_instr3_data_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_se_ppu_mc_srh_fc_cnt_h_reg[] = {
+	{ "se_ppu_mc_srh_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_se_ppu_mc_srh_fc_cnt_l_reg[] = {
+	{ "se_ppu_mc_srh_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_se_mc_srh_fc_cnt_h_reg[] = {
+	{ "ppu_se_mc_srh_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_se_mc_srh_fc_cnt_l_reg[] = {
+	{ "ppu_se_mc_srh_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_se_mc_srh_vld_cnt_h_reg[] = {
+	{ "ppu_se_mc_srh_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_se_mc_srh_vld_cnt_l_reg[] = {
+	{ "ppu_se_mc_srh_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_se_ppu_mc_srh_vld_cnt_h_reg[] = {
+	{ "se_ppu_mc_srh_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_se_ppu_mc_srh_vld_cnt_l_reg[] = {
+	{ "se_ppu_mc_srh_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_h_reg[] = {
+	{ "pbu_ppu_logic_pf_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_l_reg[] = {
+	{ "pbu_ppu_logic_pf_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_h_reg[] = {
+	{ "ppu_pbu_logic_rsp_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_l_reg[] = {
+	{ "ppu_pbu_logic_rsp_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_h_reg[] = {
+	{ "ppu_pbu_logic_pf_req_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_l_reg[] = {
+	{ "ppu_pbu_logic_pf_req_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_h_reg[] = {
+	{ "pbu_ppu_logic_pf_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_l_reg[] = {
+	{ "pbu_ppu_logic_pf_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_h_reg[] = {
+	{ "pbu_ppu_ifb_rd_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_l_reg[] = {
+	{ "pbu_ppu_ifb_rd_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_ppu_wb_fc_cnt_h_reg[] = {
+	{ "pbu_ppu_wb_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_ppu_wb_fc_cnt_l_reg[] = {
+	{ "pbu_ppu_wb_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_h_reg[] = {
+	{ "ppu_pbu_mcode_pf_req_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_l_reg[] = {
+	{ "ppu_pbu_mcode_pf_req_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_h_reg[] = {
+	{ "pbu_ppu_mcode_pf_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_l_reg[] = {
+	{ "pbu_ppu_mcode_pf_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_odma_ppu_para_fc_cnt_h_reg[] = {
+	{ "odma_ppu_para_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_odma_ppu_para_fc_cnt_l_reg[] = {
+	{ "odma_ppu_para_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_h_reg[] = {
+	{ "odma_ppu_mccnt_wr_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_l_reg[] = {
+	{ "odma_ppu_mccnt_wr_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_h_reg[] = {
+	{ "ppu_odma_mccnt_wr_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_l_reg[] = {
+	{ "ppu_odma_mccnt_wr_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_h_reg[] = {
+	{ "odma_ppu_mccnt_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_l_reg[] = {
+	{ "odma_ppu_mccnt_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pktrx_uc_fc_cnt_h_reg[] = {
+	{ "ppu_pktrx_uc_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pktrx_uc_fc_cnt_l_reg[] = {
+	{ "ppu_pktrx_uc_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_fc_cnt_h_reg[] = {
+	{ "ppu_pktrx_mc_fc_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_fc_cnt_l_reg[] = {
+	{ "ppu_pktrx_mc_fc_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pktrx_ppu_desc_vld_cnt_h_reg[] = {
+	{ "pktrx_ppu_desc_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pktrx_ppu_desc_vld_cnt_l_reg[] = {
+	{ "pktrx_ppu_desc_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_h_reg[] = {
+	{ "ppu_pbu_ifb_req_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_l_reg[] = {
+	{ "ppu_pbu_ifb_req_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_h_reg[] = {
+	{ "pbu_ppu_ifb_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_l_reg[] = {
+	{ "pbu_ppu_ifb_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pbu_wb_vld_cnt_h_reg[] = {
+	{ "ppu_pbu_wb_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pbu_wb_vld_cnt_l_reg[] = {
+	{ "ppu_pbu_wb_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_h_reg[] = {
+	{ "pbu_ppu_reorder_para_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_l_reg[] = {
+	{ "pbu_ppu_reorder_para_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_odma_para_vld_cnt_h_reg[] = {
+	{ "ppu_odma_para_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_odma_para_vld_cnt_l_reg[] = {
+	{ "ppu_odma_para_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_mc_vld_cnt_h_reg[] = {
+	{ "statics_isu_ppu_mc_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_mc_vld_cnt_l_reg[] = {
+	{ "statics_isu_ppu_mc_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_h_reg[] = {
+	{ "statics_isu_ppu_mc_loop_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_l_reg[] = {
+	{ "statics_isu_ppu_mc_loop_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_uc_vld_cnt_h_reg[] = {
+	{ "statics_isu_ppu_uc_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_uc_vld_cnt_l_reg[] = {
+	{ "statics_isu_ppu_uc_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_h_reg[] = {
+	{ "statics_isu_ppu_uc_bufnumis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_l_reg[] = {
+	{ "statics_isu_ppu_uc_bufnumis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_vld_cnt_h_reg[] = {
+	{ "statics_demux_schedule_mc_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_vld_cnt_l_reg[] = {
+	{ "statics_demux_schedule_mc_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_h_reg[] = {
+	{ "statics_demux_schedule_mc_bufnumis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15,
+	  16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_l_reg[] = {
+	{ "statics_demux_schedule_mc_bufnumis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31,
+	  32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_h_reg[] = {
+	{ "statics_demux_schedule_mc_srcportis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15,
+	  16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_l_reg[] = {
+	{ "statics_demux_schedule_mc_srcportis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31,
+	  32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_h_reg[] = {
+	{ "statics_demux_schedule_mc_srcportis1_vld_cnt_h", DPP_FIELD_FLAG_RO, 15,
+	  16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_l_reg[] = {
+	{ "statics_demux_schedule_mc_srcportis1_vld_cnt_l", DPP_FIELD_FLAG_RO, 31,
+	  32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_vld_cnt_h_reg[] = {
+	{ "statics_demux_schedule_uc_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_vld_cnt_l_reg[] = {
+	{ "statics_demux_schedule_uc_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_h_reg[] = {
+	{ "statics_demux_schedule_uc_bufnumis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15,
+	  16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_l_reg[] = {
+	{ "statics_demux_schedule_uc_bufnumis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31,
+	  32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_h_reg[] = {
+	{ "statics_demux_schedule_uc_srcportis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15,
+	  16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_l_reg[] = {
+	{ "statics_demux_schedule_uc_srcportis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31,
+	  32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_h_reg[] = {
+	{ "statics_demux_schedule_uc_srcportis1_vld_cnt_h", DPP_FIELD_FLAG_RO, 15,
+	  16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_l_reg[] = {
+	{ "statics_demux_schedule_uc_srcportis1_vld_cnt_l", DPP_FIELD_FLAG_RO, 31,
+	  32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_vld_cnt_h_reg[] = {
+	{ "statics_ppu_wb_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_vld_cnt_l_reg[] = {
+	{ "statics_ppu_wb_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_h_reg[] = {
+	{ "statics_ppu_wb_bufnumis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_l_reg[] = {
+	{ "statics_ppu_wb_bufnumis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_h_reg[] = {
+	{ "statics_ppu_wb_srcportis0_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_l_reg[] = {
+	{ "statics_ppu_wb_srcportis0_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_h_reg[] = {
+	{ "statics_ppu_wb_srcportis1_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_l_reg[] = {
+	{ "statics_ppu_wb_srcportis1_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_h_reg[] = {
+	{ "statics_ppu_wb_halt_send_type_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_l_reg[] = {
+	{ "statics_ppu_wb_halt_send_type_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_h_reg[] = {
+	{ "statics_ppu_wb_mf_type_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_l_reg[] = {
+	{ "statics_ppu_wb_mf_type_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_h_reg[] = {
+	{ "statics_ppu_wb_halt_continue_end_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_l_reg[] = {
+	{ "statics_ppu_wb_halt_continue_end_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_h_reg[] = {
+	{ "statics_ppu_wb_dup_flag_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_l_reg[] = {
+	{ "statics_ppu_wb_dup_flag_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_h_reg[] = {
+	{ "statics_ppu_wb_last_flag_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_l_reg[] = {
+	{ "statics_ppu_wb_last_flag_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_h_reg[] = {
+	{ "statics_ppu_wb_dis_flag_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_l_reg[] = {
+	{ "statics_ppu_wb_dis_flag_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h_reg[] = {
+	{ "statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h", DPP_FIELD_FLAG_RO, 15,
+	  16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l_reg[] = {
+	{ "statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l", DPP_FIELD_FLAG_RO, 31,
+	  32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_h_reg[] = {
+	{ "statics_pbu_ppu_reorder_mf_type_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_l_reg[] = {
+	{ "statics_pbu_ppu_reorder_mf_type_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T
+g_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h_reg[] = {
+	{ "statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h", DPP_FIELD_FLAG_RO,
+	  15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T
+g_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l_reg[] = {
+	{ "statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l", DPP_FIELD_FLAG_RO,
+	  31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_car_green_pkt_vld_cnt_h_reg[] = {
+	{ "car_green_pkt_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_car_green_pkt_vld_cnt_l_reg[] = {
+	{ "car_green_pkt_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_car_yellow_pkt_vld_cnt_h_reg[] = {
+	{ "car_yellow_pkt_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_car_yellow_pkt_vld_cnt_l_reg[] = {
+	{ "car_yellow_pkt_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_car_red_pkt_vld_cnt_h_reg[] = {
+	{ "car_red_pkt_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_car_red_pkt_vld_cnt_l_reg[] = {
+	{ "car_red_pkt_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_car_drop_pkt_vld_cnt_h_reg[] = {
+	{ "car_drop_pkt_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_car_drop_pkt_vld_cnt_l_reg[] = {
+	{ "car_drop_pkt_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_h_reg[] = {
+	{ "ppu_pktrx_mc_ptr_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_l_reg[] = {
+	{ "ppu_pktrx_mc_ptr_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_ppu_loopback_fc_cnt_h_reg[] = {
+	{ "ppu_pktrx_mc_ptr_vld_cnt_h", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_ppu_loopback_fc_cnt_l_reg[] = {
+	{ "ppu_pktrx_mc_ptr_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg_reg[] = {
+	{ "ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5,
+	  6, 0x10, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg_reg[] = {
+	{ "ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5,
+	  6, 0x10, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW,
+	  5, 6, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW,
+	  5, 6, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg_reg[] = {
+	{ "ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7,
+	  0x20, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg_reg[] = {
+	{ "ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7,
+	  0x20, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7,
+	  0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7,
+	  0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_mccnt_fifo_prog_full_assert_cfg_reg[] = {
+	{ "mccnt_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_mccnt_fifo_prog_full_negate_cfg_reg[] = {
+	{ "mccnt_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_mccnt_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "mccnt_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_mccnt_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "mccnt_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_uc_mf_fifo_prog_full_assert_cfg_reg[] = {
+	{ "uc_mf_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x10, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_uc_mf_fifo_prog_full_negate_cfg_reg[] = {
+	{ "uc_mf_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x10, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_uc_mf_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "uc_mf_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_uc_mf_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "uc_mf_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_mc_mf_fifo_prog_full_assert_cfg_reg[] = {
+	{ "mc_mf_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_mc_mf_fifo_prog_full_negate_cfg_reg[] = {
+	{ "mc_mf_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xa, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_mc_mf_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "mc_mf_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_mc_mf_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "mc_mf_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_mf_fifo_prog_full_assert_cfg_reg[] = {
+	{ "isu_mf_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_mf_fifo_prog_full_negate_cfg_reg[] = {
+	{ "isu_mf_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x10, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_mf_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "isu_mf_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_mf_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "isu_mf_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_fwft_mf_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "isu_fwft_mf_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_fwft_mf_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "isu_fwft_mf_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_mc_para_mf_fifo_prog_full_assert_cfg_reg[] = {
+	{ "isu_mc_para_mf_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x50,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_mc_para_mf_fifo_prog_full_negate_cfg_reg[] = {
+	{ "isu_mc_para_mf_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x50,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "isu_mc_para_mf_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "isu_mc_para_mf_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_group_id_fifo_prog_full_assert_cfg_reg[] = {
+	{ "group_id_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x3c,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_group_id_fifo_prog_full_negate_cfg_reg[] = {
+	{ "group_id_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x3c,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_group_id_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "group_id_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_group_id_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "group_id_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_sa_para_fifo_prog_full_assert_cfg_reg[] = {
+	{ "sa_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x3c, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_sa_para_fifo_prog_full_negate_cfg_reg[] = {
+	{ "sa_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x3c, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_sa_para_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "sa_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_sa_para_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "sa_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_se_mc_rsp_fifo_prog_full_assert_cfg_reg[] = {
+	{ "se_mc_rsp_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0xa,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_se_mc_rsp_fifo_prog_full_negate_cfg_reg[] = {
+	{ "se_mc_rsp_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0xa,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_se_mc_rsp_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "se_mc_rsp_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_se_mc_rsp_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "se_mc_rsp_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_dup_para_fifo_prog_full_assert_cfg_reg[] = {
+	{ "dup_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_dup_para_fifo_prog_full_negate_cfg_reg[] = {
+	{ "dup_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_dup_para_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "dup_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_dup_para_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "dup_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pf_rsp_fifo_prog_full_assert_cfg_reg[] = {
+	{ "pf_rsp_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pf_rsp_fifo_prog_full_negate_cfg_reg[] = {
+	{ "pf_rsp_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pf_rsp_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "pf_rsp_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pf_rsp_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "pf_rsp_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_dup_freeptr_fifo_prog_full_assert_cfg_reg[] = {
+	{ "dup_freeptr_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x7c,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_dup_freeptr_fifo_prog_full_negate_cfg_reg[] = {
+	{ "dup_freeptr_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x7c,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_dup_freeptr_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "dup_freeptr_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x58,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_dup_freeptr_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "dup_freeptr_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x58,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pf_req_fifo_prog_full_assert_cfg_reg[] = {
+	{ "pf_req_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pf_req_fifo_prog_full_negate_cfg_reg[] = {
+	{ "pf_req_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pf_req_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "pf_req_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pf_req_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "pf_req_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_car_flag_fifo_prog_full_assert_cfg_reg[] = {
+	{ "car_flag_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_car_flag_fifo_prog_full_negate_cfg_reg[] = {
+	{ "car_flag_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_car_flag_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "car_flag_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_car_flag_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "car_flag_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_cluster_mf_out_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6,
+	  0x10, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_cluster_mf_out_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6,
+	  0x10, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_cluster_mf_out_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6,
+	  0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_cluster_mf_out_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6,
+	  0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_key_fifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_cop_key_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_key_fifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_cop_key_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_key_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_cop_key_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_key_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_cop_key_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_cop_random_mod_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6,
+	  7, 0x24, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_cop_random_mod_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6,
+	  7, 0x24, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW,
+	  6, 7, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW,
+	  6, 7, 0x4, 0x0 },
+};
+DPP_FIELD_T
+g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_cop_random_mod_result_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW,
+	  7, 8, 0x28, 0x0 },
+};
+DPP_FIELD_T
+g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_cop_random_mod_result_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW,
+	  7, 8, 0x28, 0x0 },
+};
+DPP_FIELD_T
+g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW,
+	  7, 8, 0x4, 0x0 },
+};
+DPP_FIELD_T
+g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW,
+	  7, 8, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_cop_checksum_result_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4,
+	  5, 0xa, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_cop_checksum_result_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4,
+	  5, 0xa, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_cop_checksum_result_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW,
+	  4, 5, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_cop_checksum_result_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW,
+	  4, 5, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_cop_crc_first_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4,
+	  5, 0xe, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_cop_crc_first_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4,
+	  5, 0xe, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4,
+	  5, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4,
+	  5, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_assert_cfg_reg[] = {
+	{ "ppu_cop_crc_bypass_delay_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5,
+	  0xe, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_negate_cfg_reg[] = {
+	{ "ppu_cop_crc_bypass_delay_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5,
+	  0xe, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_cop_crc_bypass_delay_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4, 5,
+	  0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_cop_crc_bypass_delay_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4, 5,
+	  0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_cop_crc_second_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6,
+	  7, 0x24, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_cop_crc_second_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6,
+	  7, 0x24, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW,
+	  6, 7, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW,
+	  6, 7, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7,
+	  8, 0x30, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7,
+	  8, 0x30, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW,
+	  7, 8, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW,
+	  7, 8, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_cop_multiply_para_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 4,
+	  5, 0xa, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_cop_multiply_para_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 4,
+	  5, 0xa, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_cop_multiply_para_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 4,
+	  5, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_cop_multiply_para_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 4,
+	  5, 0x4, 0x0 },
+};
+DPP_FIELD_T
+g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg",
+	  DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0 },
+};
+DPP_FIELD_T
+g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg",
+	  DPP_FIELD_FLAG_RW, 5, 6, 0x18, 0x0 },
+};
+DPP_FIELD_T
+g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg",
+	  DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0 },
+};
+DPP_FIELD_T
+g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg",
+	  DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_free_global_num_fwft_fifo_prog_full_assert_cfg_reg[] = {
+	{ "free_global_num_fwft_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 12,
+	  13, 0xffc, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_free_global_num_fwft_fifo_prog_full_negate_cfg_reg[] = {
+	{ "free_global_num_fwft_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 12,
+	  13, 0xffc, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_free_global_num_fwft_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "free_global_num_fwft_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 12,
+	  13, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_free_global_num_fwft_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "free_global_num_fwft_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 12,
+	  13, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 14, 15,
+	  0x3ff6, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 14, 15,
+	  0x3ff6, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 14, 15,
+	  0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 14, 15,
+	  0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data0_reg[] = {
+	{ "pkt_data0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data1_reg[] = {
+	{ "pkt_data1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data2_reg[] = {
+	{ "pkt_data2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data3_reg[] = {
+	{ "pkt_data3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data4_reg[] = {
+	{ "pkt_data4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data5_reg[] = {
+	{ "pkt_data5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data6_reg[] = {
+	{ "pkt_data6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data7_reg[] = {
+	{ "pkt_data7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data8_reg[] = {
+	{ "pkt_data8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data9_reg[] = {
+	{ "pkt_data9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data10_reg[] = {
+	{ "pkt_data10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data11_reg[] = {
+	{ "pkt_data11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data12_reg[] = {
+	{ "pkt_data12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data13_reg[] = {
+	{ "pkt_data13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data14_reg[] = {
+	{ "pkt_data14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data15_reg[] = {
+	{ "pkt_data15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data16_reg[] = {
+	{ "pkt_data16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data17_reg[] = {
+	{ "pkt_data17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data18_reg[] = {
+	{ "pkt_data18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data19_reg[] = {
+	{ "pkt_data19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data20_reg[] = {
+	{ "pkt_data20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data21_reg[] = {
+	{ "pkt_data21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data22_reg[] = {
+	{ "pkt_data22", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data23_reg[] = {
+	{ "pkt_data23", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data24_reg[] = {
+	{ "pkt_data24", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data25_reg[] = {
+	{ "pkt_data25", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data26_reg[] = {
+	{ "pkt_data26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data27_reg[] = {
+	{ "pkt_data27", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data28_reg[] = {
+	{ "pkt_data28", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data29_reg[] = {
+	{ "pkt_data29", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data30_reg[] = {
+	{ "pkt_data30", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data31_reg[] = {
+	{ "pkt_data31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data32_reg[] = {
+	{ "pkt_data32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data33_reg[] = {
+	{ "pkt_data33", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data34_reg[] = {
+	{ "pkt_data34", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data35_reg[] = {
+	{ "pkt_data35", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data36_reg[] = {
+	{ "pkt_data36", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data37_reg[] = {
+	{ "pkt_data37", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data38_reg[] = {
+	{ "pkt_data38", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data39_reg[] = {
+	{ "pkt_data39", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data40_reg[] = {
+	{ "pkt_data40", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data41_reg[] = {
+	{ "pkt_data41", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data42_reg[] = {
+	{ "pkt_data42", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data43_reg[] = {
+	{ "pkt_data43", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data44_reg[] = {
+	{ "pkt_data44", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data45_reg[] = {
+	{ "pkt_data45", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data46_reg[] = {
+	{ "pkt_data46", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data47_reg[] = {
+	{ "pkt_data47", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data48_reg[] = {
+	{ "pkt_data48", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data49_reg[] = {
+	{ "pkt_data49", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data50_reg[] = {
+	{ "pkt_data50", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data51_reg[] = {
+	{ "pkt_data51", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data52_reg[] = {
+	{ "pkt_data52", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data53_reg[] = {
+	{ "pkt_data53", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data54_reg[] = {
+	{ "pkt_data54", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data55_reg[] = {
+	{ "pkt_data55", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data56_reg[] = {
+	{ "pkt_data56", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data57_reg[] = {
+	{ "pkt_data57", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data58_reg[] = {
+	{ "pkt_data58", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data59_reg[] = {
+	{ "pkt_data59", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data60_reg[] = {
+	{ "pkt_data60", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data61_reg[] = {
+	{ "pkt_data61", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data62_reg[] = {
+	{ "pkt_data62", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data63_reg[] = {
+	{ "pkt_data63", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data64_reg[] = {
+	{ "pkt_data64", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data65_reg[] = {
+	{ "pkt_data65", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data66_reg[] = {
+	{ "pkt_data66", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data67_reg[] = {
+	{ "pkt_data67", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data68_reg[] = {
+	{ "pkt_data68", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data69_reg[] = {
+	{ "pkt_data69", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data70_reg[] = {
+	{ "pkt_data70", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data71_reg[] = {
+	{ "pkt_data71", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data72_reg[] = {
+	{ "pkt_data72", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data73_reg[] = {
+	{ "pkt_data73", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data74_reg[] = {
+	{ "pkt_data74", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data75_reg[] = {
+	{ "pkt_data75", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data76_reg[] = {
+	{ "pkt_data76", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data77_reg[] = {
+	{ "pkt_data77", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data78_reg[] = {
+	{ "pkt_data78", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data79_reg[] = {
+	{ "pkt_data79", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data80_reg[] = {
+	{ "pkt_data80", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data81_reg[] = {
+	{ "pkt_data81", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data82_reg[] = {
+	{ "pkt_data82", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data83_reg[] = {
+	{ "pkt_data83", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data84_reg[] = {
+	{ "pkt_data84", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data85_reg[] = {
+	{ "pkt_data85", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data86_reg[] = {
+	{ "pkt_data86", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data87_reg[] = {
+	{ "pkt_data87", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data88_reg[] = {
+	{ "pkt_data88", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data89_reg[] = {
+	{ "pkt_data89", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data90_reg[] = {
+	{ "pkt_data90", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data91_reg[] = {
+	{ "pkt_data91", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data92_reg[] = {
+	{ "pkt_data92", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data93_reg[] = {
+	{ "pkt_data93", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data94_reg[] = {
+	{ "pkt_data94", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data95_reg[] = {
+	{ "pkt_data95", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data96_reg[] = {
+	{ "pkt_data96", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data97_reg[] = {
+	{ "pkt_data97", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data98_reg[] = {
+	{ "pkt_data98", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data99_reg[] = {
+	{ "pkt_data99", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data100_reg[] = {
+	{ "pkt_data100", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data101_reg[] = {
+	{ "pkt_data101", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data102_reg[] = {
+	{ "pkt_data102", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data103_reg[] = {
+	{ "pkt_data103", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data104_reg[] = {
+	{ "pkt_data104", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data105_reg[] = {
+	{ "pkt_data105", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data106_reg[] = {
+	{ "pkt_data106", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data107_reg[] = {
+	{ "pkt_data107", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data108_reg[] = {
+	{ "pkt_data108", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data109_reg[] = {
+	{ "pkt_data109", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data110_reg[] = {
+	{ "pkt_data110", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data111_reg[] = {
+	{ "pkt_data111", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data112_reg[] = {
+	{ "pkt_data112", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data113_reg[] = {
+	{ "pkt_data113", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data114_reg[] = {
+	{ "pkt_data114", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data115_reg[] = {
+	{ "pkt_data115", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data116_reg[] = {
+	{ "pkt_data116", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data117_reg[] = {
+	{ "pkt_data117", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data118_reg[] = {
+	{ "pkt_data118", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data119_reg[] = {
+	{ "pkt_data119", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data120_reg[] = {
+	{ "pkt_data120", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data121_reg[] = {
+	{ "pkt_data121", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data122_reg[] = {
+	{ "pkt_data122", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data123_reg[] = {
+	{ "pkt_data123", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data124_reg[] = {
+	{ "pkt_data124", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data125_reg[] = {
+	{ "pkt_data125", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data126_reg[] = {
+	{ "pkt_data126", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_pkt_data127_reg[] = {
+	{ "pkt_data127", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr0_reg[] = {
+	{ "spr0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr1_reg[] = {
+	{ "spr1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr2_reg[] = {
+	{ "spr2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr3_reg[] = {
+	{ "spr3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr4_reg[] = {
+	{ "spr4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr5_reg[] = {
+	{ "spr5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr6_reg[] = {
+	{ "spr6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr7_reg[] = {
+	{ "spr7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr8_reg[] = {
+	{ "spr8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr9_reg[] = {
+	{ "spr9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr10_reg[] = {
+	{ "spr10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr11_reg[] = {
+	{ "spr11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr12_reg[] = {
+	{ "spr12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr13_reg[] = {
+	{ "spr13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr14_reg[] = {
+	{ "spr14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr15_reg[] = {
+	{ "spr15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr16_reg[] = {
+	{ "spr16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr17_reg[] = {
+	{ "spr17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr18_reg[] = {
+	{ "spr18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr19_reg[] = {
+	{ "spr19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr20_reg[] = {
+	{ "spr20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr21_reg[] = {
+	{ "spr21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr22_reg[] = {
+	{ "spr22", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr23_reg[] = {
+	{ "spr23", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr24_reg[] = {
+	{ "spr24", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr25_reg[] = {
+	{ "spr25", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr26_reg[] = {
+	{ "spr26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr27_reg[] = {
+	{ "spr27", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr28_reg[] = {
+	{ "spr28", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr29_reg[] = {
+	{ "spr29", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr30_reg[] = {
+	{ "spr30", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_spr31_reg[] = {
+	{ "spr31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp0_reg[] = {
+	{ "rsp0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp1_reg[] = {
+	{ "rsp1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp2_reg[] = {
+	{ "rsp2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp3_reg[] = {
+	{ "rsp3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp4_reg[] = {
+	{ "rsp4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp5_reg[] = {
+	{ "rsp5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp6_reg[] = {
+	{ "rsp6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp7_reg[] = {
+	{ "rsp7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp8_reg[] = {
+	{ "rsp8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp9_reg[] = {
+	{ "rsp9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp10_reg[] = {
+	{ "rsp10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp11_reg[] = {
+	{ "rsp11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp12_reg[] = {
+	{ "rsp12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp13_reg[] = {
+	{ "rsp13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp14_reg[] = {
+	{ "rsp14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp15_reg[] = {
+	{ "rsp15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp16_reg[] = {
+	{ "rsp16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp17_reg[] = {
+	{ "rsp17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp18_reg[] = {
+	{ "rsp18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp19_reg[] = {
+	{ "rsp19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp20_reg[] = {
+	{ "rsp20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp21_reg[] = {
+	{ "rsp21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp22_reg[] = {
+	{ "rsp22", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp23_reg[] = {
+	{ "rsp23", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp24_reg[] = {
+	{ "rsp24", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp25_reg[] = {
+	{ "rsp25", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp26_reg[] = {
+	{ "rsp26", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp27_reg[] = {
+	{ "rsp27", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp28_reg[] = {
+	{ "rsp28", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp29_reg[] = {
+	{ "rsp29", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp30_reg[] = {
+	{ "rsp30", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_rsp31_reg[] = {
+	{ "rsp31", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key0_reg[] = {
+	{ "key0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key1_reg[] = {
+	{ "key1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key2_reg[] = {
+	{ "key2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key3_reg[] = {
+	{ "key3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key4_reg[] = {
+	{ "key4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key5_reg[] = {
+	{ "key5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key6_reg[] = {
+	{ "key6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key7_reg[] = {
+	{ "key7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key8_reg[] = {
+	{ "key8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key9_reg[] = {
+	{ "key9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key10_reg[] = {
+	{ "key10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key11_reg[] = {
+	{ "key11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key12_reg[] = {
+	{ "key12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key13_reg[] = {
+	{ "key13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key14_reg[] = {
+	{ "key14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key15_reg[] = {
+	{ "key15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key16_reg[] = {
+	{ "key16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key17_reg[] = {
+	{ "key17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key18_reg[] = {
+	{ "key18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_key19_reg[] = {
+	{ "key19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_ppu_flag_reg[] = {
+	{ "me_num", DPP_FIELD_FLAG_RO, 26, 3, 0x0, 0x0 },
+	{ "thread_num", DPP_FIELD_FLAG_RO, 19, 4, 0x0, 0x0 },
+	{ "flag", DPP_FIELD_FLAG_RO, 11, 12, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_int_1200m_flag_reg[] = {
+	{ "me7_interrupt_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "me6_interrupt_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "me5_interrupt_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "me4_interrupt_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "me3_interrupt_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "me2_interrupt_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "me1_interrupt_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "me0_interrupt_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_bp_instr_l_reg[] = {
+	{ "bp_instr_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_bp_instr_h_reg[] = {
+	{ "bp_instr_h", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_bp_addr_reg[] = {
+	{ "bp_addr", DPP_FIELD_FLAG_RO, 14, 15, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_drr_reg[] = {
+	{ "drr", DPP_FIELD_FLAG_RO, 4, 5, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_dsr_reg[] = {
+	{ "dsr", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_dbg_rtl_date_reg[] = {
+	{ "dbg_rtl_date", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_continue_reg[] = {
+	{ "me_continue", DPP_FIELD_FLAG_WO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_step_reg[] = {
+	{ "me_step", DPP_FIELD_FLAG_WO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_refresh_reg[] = {
+	{ "me_refresh", DPP_FIELD_FLAG_WO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_drr_clr_reg[] = {
+	{ "drr_clr", DPP_FIELD_FLAG_WO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_busy_thresold_reg[] = {
+	{ "me_busy_thresold", DPP_FIELD_FLAG_RW, 15, 16, 0x7fff, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_int_1200m_sta_reg[] = {
+	{ "me7_interrupt_sta", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "me6_interrupt_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "me5_interrupt_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "me4_interrupt_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "me3_interrupt_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "me2_interrupt_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "me1_interrupt_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "me0_interrupt_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_int_1200m_me_fifo_mask_l_reg[] = {
+	{ "me_free_pkt_q_overflow_mask", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "me_free_pkt_q_underflow_mask", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "me_free_thread_q_overflow_mask", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "me_free_thread_q_underflow_mask", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "me_pkt_in_overflow_mask", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "me_pkt_in_underflow_mask", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "me_rdy_q_overflow_mask", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "me_rdy_q_underflow_mask", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "me_pkt_out_q_overflow_mask", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "me_pkt_out_q_underflow_mask", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "me_continue_q_overflow_mask", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "me_continue_q_underflow_mask", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "me_esrh_q_overflow_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "me_esrh_q_underflow_mask", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "me_isrh_q_overflow_mask", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "me_isrh_q_underflow_mask", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "me_cache_miss_q_overflow_mask", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "me_cache_miss_q_underflow_mask", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "me_base_q_u0_overflow_mask", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "me_base_q_u0_underflow_mask", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "me_base_q_u1_overflow_mask", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "me_base_q_u1_underflow_mask", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "me_base_q_u2_overflow_mask", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "me_base_q_u2_underflow_mask", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "me_base_q_u3_overflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "me_base_q_u3_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "me_reg_pc_q_overflow_mask", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "me_reg_pc_q_underflow_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "me_branch_q_overflow_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "me_branch_q_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "me_pkt_base_q_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "me_pkt_base_q_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_int_1200m_me_fifo_mask_h_reg[] = {
+	{ "me_except_refetch_pc_overflow_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "me_except_refetch_pc_underflow_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x1,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_fifo_interrupt_flag_l_reg[] = {
+	{ "me_free_pkt_q_overflow_flag", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "me_free_pkt_q_underflow_flag", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "me_free_thread_q_overflow_flag", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "me_free_thread_q_underflow_flag", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "me_pkt_in_overflow_flag", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "me_pkt_in_underflow_flag", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "me_rdy_q_overflow_flag", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "me_rdy_q_underflow_flag", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "me_pkt_out_q_overflow_flag", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "me_pkt_out_q_underflow_flag", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "me_continue_q_overflow_flag", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "me_continue_q_underflow_flag", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "me_esrh_q_overflow_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "me_esrh_q_underflow_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "me_isrh_q_overflow_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "me_isrh_q_underflow_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "me_cache_miss_q_overflow_flag", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "me_cache_miss_q_underflow_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "me_base_q_u0_overflow_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "me_base_q_u0_underflow_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "me_base_q_u1_overflow_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "me_base_q_u1_underflow_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "me_base_q_u2_overflow_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "me_base_q_u2_underflow_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "me_base_q_u3_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "me_base_q_u3_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "me_reg_pc_q_overflow_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "me_reg_pc_q_underflow_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "me_branch_q_overflow_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "me_branch_q_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "me_pkt_base_q_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "me_pkt_base_q_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_fifo_interrupt_flag_h_reg[] = {
+	{ "me_except_refetch_pc_overflow_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "me_except_refetch_pc_underflow_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_fifo_interrupt_sta_l_reg[] = {
+	{ "me_free_pkt_q_overflow_sta", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0 },
+	{ "me_free_pkt_q_underflow_sta", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0 },
+	{ "me_free_thread_q_overflow_sta", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0 },
+	{ "me_free_thread_q_underflow_sta", DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0 },
+	{ "me_pkt_in_overflow_sta", DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0 },
+	{ "me_pkt_in_underflow_sta", DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0 },
+	{ "me_rdy_q_overflow_sta", DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0 },
+	{ "me_rdy_q_underflow_sta", DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0 },
+	{ "me_pkt_out_q_overflow_sta", DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0 },
+	{ "me_pkt_out_q_underflow_sta", DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0 },
+	{ "me_continue_q_overflow_sta", DPP_FIELD_FLAG_RO, 21, 1, 0x0, 0x0 },
+	{ "me_continue_q_underflow_sta", DPP_FIELD_FLAG_RO, 20, 1, 0x0, 0x0 },
+	{ "me_esrh_q_overflow_sta", DPP_FIELD_FLAG_RO, 19, 1, 0x0, 0x0 },
+	{ "me_esrh_q_underflow_sta", DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0 },
+	{ "me_isrh_q_overflow_sta", DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0 },
+	{ "me_isrh_q_underflow_sta", DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0 },
+	{ "me_cache_miss_q_overflow_sta", DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0 },
+	{ "me_cache_miss_q_underflow_sta", DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0 },
+	{ "me_base_q_u0_overflow_sta", DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0 },
+	{ "me_base_q_u0_underflow_sta", DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0 },
+	{ "me_base_q_u1_overflow_sta", DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0 },
+	{ "me_base_q_u1_underflow_sta", DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0 },
+	{ "me_base_q_u2_overflow_sta", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0 },
+	{ "me_base_q_u2_underflow_sta", DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0 },
+	{ "me_base_q_u3_overflow_sta", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "me_base_q_u3_underflow_sta", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "me_reg_pc_q_overflow_sta", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "me_reg_pc_q_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "me_branch_q_overflow_sta", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "me_branch_q_underflow_sta", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "me_pkt_base_q_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "me_pkt_base_q_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_fifo_interrupt_sta_h_reg[] = {
+	{ "me_except_refetch_pc_overflow_sta", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "me_except_refetch_pc_underflow_sta", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_mask_l_reg[] = {
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW,
+	  21, 1, 0x1, 0x0 },
+	{ "ise_rsp_ram_free_ptr_u0_overflow_mask", DPP_FIELD_FLAG_RW, 20, 1, 0x1,
+	  0x0 },
+	{ "ise_rsp_ram_free_ptr_u0_underflow_mask", DPP_FIELD_FLAG_RW, 19, 1, 0x1,
+	  0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "ppu_sta_rsp_afifo_64x79_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 2, 1,
+	  0x1, 0x0 },
+	{ "ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_mask", DPP_FIELD_FLAG_RW,
+	  1, 1, 0x1, 0x0 },
+	{ "ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_mask", DPP_FIELD_FLAG_RW,
+	  0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_mask_h_reg[] = {
+	{ "ppu_se_key_afifo_32x54_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 18, 1,
+	  0x1, 0x0 },
+	{ "ppu_se_key_afifo_32x665_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 17, 1,
+	  0x1, 0x0 },
+	{ "ppu_sta_key_afifo_32x110_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 16,
+	  1, 0x1, 0x0 },
+	{ "ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_mask", DPP_FIELD_FLAG_RW,
+	  12, 1, 0x1, 0x0 },
+	{ "ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_mask", DPP_FIELD_FLAG_RW,
+	  11, 1, 0x1, 0x0 },
+	{ "ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_mask", DPP_FIELD_FLAG_RW,
+	  8, 1, 0x1, 0x0 },
+	{ "ese_rsp_ram_free_ptr_u0_overflow_mask", DPP_FIELD_FLAG_RW, 7, 1, 0x1,
+	  0x0 },
+	{ "ese_rsp_ram_free_ptr_u0_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1, 0x1,
+	  0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_mask",
+	  DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_flag_l_reg[] = {
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC,
+	  21, 1, 0x0, 0x0 },
+	{ "ise_rsp_ram_free_ptr_u0_overflow_flag", DPP_FIELD_FLAG_RC, 20, 1, 0x0,
+	  0x0 },
+	{ "ise_rsp_ram_free_ptr_u0_underflow_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0,
+	  0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ppu_sta_rsp_afifo_64x79_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 2, 1,
+	  0x0, 0x0 },
+	{ "ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_flag", DPP_FIELD_FLAG_RC,
+	  1, 1, 0x0, 0x0 },
+	{ "ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_flag", DPP_FIELD_FLAG_RC,
+	  0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_flag_h_reg[] = {
+	{ "ppu_se_key_afifo_32x54_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 18, 1,
+	  0x0, 0x0 },
+	{ "ppu_se_key_afifo_32x665_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 17, 1,
+	  0x0, 0x0 },
+	{ "ppu_sta_key_afifo_32x110_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 16,
+	  1, 0x0, 0x0 },
+	{ "ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_flag", DPP_FIELD_FLAG_RC,
+	  12, 1, 0x0, 0x0 },
+	{ "ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_flag", DPP_FIELD_FLAG_RC,
+	  11, 1, 0x0, 0x0 },
+	{ "ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_flag", DPP_FIELD_FLAG_RC,
+	  8, 1, 0x0, 0x0 },
+	{ "ese_rsp_ram_free_ptr_u0_overflow_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0,
+	  0x0 },
+	{ "ese_rsp_ram_free_ptr_u0_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0,
+	  0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_flag",
+	  DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_stat_l_reg[] = {
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 28, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 27, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 26, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 25, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 24, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 23, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 22, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_afifo_64x143_wrapper_u0_underflow_stat", DPP_FIELD_FLAG_RO,
+	  21, 1, 0x0, 0x0 },
+	{ "ise_rsp_ram_free_ptr_u0_overflow_stat", DPP_FIELD_FLAG_RO, 20, 1, 0x0,
+	  0x0 },
+	{ "ise_rsp_ram_free_ptr_u0_underflow_stat", DPP_FIELD_FLAG_RO, 19, 1, 0x0,
+	  0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 18, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 17, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 16, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 12, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u3_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 11, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u4_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 8, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u5_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u6_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_ptr_fwft_fifo_128x7_wrapper_u7_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "ppu_sta_rsp_afifo_64x79_wrapper_underflow_stat", DPP_FIELD_FLAG_RO, 2, 1,
+	  0x0, 0x0 },
+	{ "ppu_sta_rsp_fwft_fifo_128x79_wrapper_overflow_stat", DPP_FIELD_FLAG_RO,
+	  1, 1, 0x0, 0x0 },
+	{ "ppu_sta_rsp_fwft_fifo_128x79_wrapper_underflow_stat", DPP_FIELD_FLAG_RO,
+	  0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_int_1200m_cluster_mex_fifo_stat_h_reg[] = {
+	{ "ppu_se_key_afifo_32x54_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 18, 1,
+	  0x0, 0x0 },
+	{ "ppu_se_key_afifo_32x665_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 17, 1,
+	  0x0, 0x0 },
+	{ "ppu_sta_key_afifo_32x110_wrapper_overflow_stat", DPP_FIELD_FLAG_RO, 16,
+	  1, 0x0, 0x0 },
+	{ "ppu_cluster_mf_in_afifo_32x2048_wrapper_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 15, 1, 0x0, 0x0 },
+	{ "ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 14, 1, 0x0, 0x0 },
+	{ "ppu_pbu_mcode_pf_rsp_fifo_32x13_wrapper_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 13, 1, 0x0, 0x0 },
+	{ "ppu_coprocess_rsp_fifo_32x77_wrapper_overflow_stat", DPP_FIELD_FLAG_RO,
+	  12, 1, 0x0, 0x0 },
+	{ "ppu_coprocess_rsp_fifo_32x77_wrapper_underflow_stat", DPP_FIELD_FLAG_RO,
+	  11, 1, 0x0, 0x0 },
+	{ "ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 10, 1, 0x0, 0x0 },
+	{ "ppu_coprocess_rsp_fwft_fifo_128x78_wrapper_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_afifo_64x271_wrapper_u0_underflow_stat", DPP_FIELD_FLAG_RO,
+	  8, 1, 0x0, 0x0 },
+	{ "ese_rsp_ram_free_ptr_u0_overflow_stat", DPP_FIELD_FLAG_RO, 7, 1, 0x0,
+	  0x0 },
+	{ "ese_rsp_ram_free_ptr_u0_underflow_stat", DPP_FIELD_FLAG_RO, 6, 1, 0x0,
+	  0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u0_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u1_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_overflow_stat",
+	  DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_ptr_fwft_fifo_128x7_wrapper_u2_underflow_stat",
+	  DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_statics_wb_exception_cfg_reg[] = {
+	{ "csr_statics_wb_exception_code5", DPP_FIELD_FLAG_RW, 22, 3, 0x7, 0x0 },
+	{ "csr_statics_wb_exception_code4", DPP_FIELD_FLAG_RW, 18, 3, 0x6, 0x0 },
+	{ "csr_statics_wb_exception_code3", DPP_FIELD_FLAG_RW, 14, 3, 0x5, 0x0 },
+	{ "csr_statics_wb_exception_code2", DPP_FIELD_FLAG_RW, 10, 3, 0x4, 0x0 },
+	{ "csr_statics_wb_exception_code1", DPP_FIELD_FLAG_RW, 6, 3, 0x3, 0x0 },
+	{ "csr_statics_wb_exception_code0", DPP_FIELD_FLAG_RW, 2, 3, 0x2, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_thread_switch_en_reg[] = {
+	{ "thread_switch_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_is_me_not_idle_reg[] = {
+	{ "me7_is_not_idle", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "me6_is_not_idle", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "me5_is_not_idle", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "me4_is_not_idle", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "me3_is_not_idle", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "me2_is_not_idle", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "me1_is_not_idle", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "me0_is_not_idle", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_cluster_mf_in_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6,
+	  0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_cluster_mf_in_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6,
+	  0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ese_rsp_afifo_prog_empty_assert_cfg_reg[] = {
+	{ "ese_rsp_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0xe,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ese_rsp_afifo_prog_empty_negate_cfg_reg[] = {
+	{ "ese_rsp_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0xe,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ise_rsp_afifo_prog_empty_assert_cfg_reg[] = {
+	{ "ise_rsp_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x20,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ise_rsp_afifo_prog_empty_negate_cfg_reg[] = {
+	{ "ise_rsp_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x20,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg_reg[] = {
+	{ "ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8,
+	  0x78, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg_reg[] = {
+	{ "ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8,
+	  0x78, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8,
+	  0x6, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8,
+	  0x6, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg_reg[] = {
+	{ "ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8,
+	  0x78, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg_reg[] = {
+	{ "ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8,
+	  0x78, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8,
+	  0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8,
+	  0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_sta_rsp_afifo_prog_empty_assert_cfg_reg[] = {
+	{ "sta_rsp_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_sta_rsp_afifo_prog_empty_negate_cfg_reg[] = {
+	{ "sta_rsp_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8,
+	  0x78, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8,
+	  0x78, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8,
+	  0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8,
+	  0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cop_rsp_fifo_prog_full_assert_cfg_reg[] = {
+	{ "cop_rsp_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x17, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cop_rsp_fifo_prog_full_negate_cfg_reg[] = {
+	{ "cop_rsp_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x17, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cop_rsp_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "cop_rsp_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cop_rsp_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "cop_rsp_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mcode_pf_rsp_fifo_prog_full_assert_cfg_reg[] = {
+	{ "mcode_pf_rsp_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mcode_pf_rsp_fifo_prog_full_negate_cfg_reg[] = {
+	{ "mcode_pf_rsp_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x18,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "mcode_pf_rsp_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "mcode_pf_rsp_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8,
+	  0x78, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8,
+	  0x78, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 7, 8,
+	  0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 7, 8,
+	  0x4, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_ise_key_afifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_ise_key_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_ise_key_afifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_ise_key_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_ese_key_afifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_ese_key_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_ese_key_afifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_ese_key_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_sta_key_afifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_sta_key_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_sta_key_afifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_sta_key_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x14,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_int_600m_cluster_mex_fifo_mask_reg[] = {
+	{ "ppu_se_key_afifo_32x54_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 6, 1,
+	  0x1, 0x0 },
+	{ "ppu_se_key_afifo_32x665_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 5, 1,
+	  0x1, 0x0 },
+	{ "ppu_sta_key_afifo_32x110_wrapper_underflow_mask", DPP_FIELD_FLAG_RW, 4,
+	  1, 0x1, 0x0 },
+	{ "ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_mask",
+	  DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 2,
+	  1, 0x1, 0x0 },
+	{ "ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_mask", DPP_FIELD_FLAG_RW, 1,
+	  1, 0x1, 0x0 },
+	{ "ppu_sta_rsp_afifo_64x79_wrapper_overflow_mask", DPP_FIELD_FLAG_RW, 0, 1,
+	  0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cluster_mex_fifo_600m_interrupt_flag_reg[] = {
+	{ "ppu_se_key_afifo_32x54_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 6, 1,
+	  0x0, 0x0 },
+	{ "ppu_se_key_afifo_32x665_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 5, 1,
+	  0x0, 0x0 },
+	{ "ppu_sta_key_afifo_32x110_wrapper_underflow_flag", DPP_FIELD_FLAG_RC, 4,
+	  1, 0x0, 0x0 },
+	{ "ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_flag",
+	  DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 2,
+	  1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_flag", DPP_FIELD_FLAG_RC, 1,
+	  1, 0x0, 0x0 },
+	{ "ppu_sta_rsp_afifo_64x79_wrapper_overflow_flag", DPP_FIELD_FLAG_RC, 0, 1,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cluster_mex_fifo_600m_interrupt_sta_reg[] = {
+	{ "ppu_se_key_afifo_32x54_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 6, 1,
+	  0x0, 0x0 },
+	{ "ppu_se_key_afifo_32x665_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 5, 1,
+	  0x0, 0x0 },
+	{ "ppu_sta_key_afifo_32x110_wrapper_underflow_sta", DPP_FIELD_FLAG_RO, 4, 1,
+	  0x0, 0x0 },
+	{ "ppu_cluster_mf_in_afifo_32x2048_wrapper_overflow_sta", DPP_FIELD_FLAG_RO,
+	  3, 1, 0x0, 0x0 },
+	{ "ppu_ese_rsp_afifo_64x271_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 2,
+	  1, 0x0, 0x0 },
+	{ "ppu_ise_rsp_afifo_64x143_wrapper_u0_overflow_sta", DPP_FIELD_FLAG_RO, 1,
+	  1, 0x0, 0x0 },
+	{ "ppu_sta_rsp_afifo_64x79_wrapper_overflow_sta", DPP_FIELD_FLAG_RO, 0, 1,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mex_cnt_cfg_reg[] = {
+	{ "csr_count_overflow_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "csr_count_rd_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T
+g_ppu_cluster_int_600m_cluster_mex_ram_ecc_error_interrupt_mask_reg[] = {
+	{ "ppu_sta_key_ram_1r1w_32x110_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 5,
+	  1, 0x1, 0x0 },
+	{ "ppu_se_key_afifo_32x665_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 4, 1,
+	  0x1, 0x0 },
+	{ "ppu_se_key_afifo_32x54_ecc_double_err_mask", DPP_FIELD_FLAG_RW, 3, 1,
+	  0x1, 0x0 },
+	{ "ppu_sta_key_ram_1r1w_32x110_ecc_single_err_flag", DPP_FIELD_FLAG_RW, 2,
+	  1, 0x1, 0x0 },
+	{ "ppu_se_key_afifo_32x665_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 1, 1,
+	  0x1, 0x0 },
+	{ "ppu_se_key_afifo_32x54_ecc_single_err_mask", DPP_FIELD_FLAG_RW, 0, 1,
+	  0x1, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_flag_reg[] = {
+	{ "ppu_sta_key_ram_1r1w_32x110_ecc_double_err_flag", DPP_FIELD_FLAG_RC, 5,
+	  1, 0x0, 0x0 },
+	{ "ppu_se_key_afifo_32x665_ecc_double_err_flag", DPP_FIELD_FLAG_RC, 4, 1,
+	  0x0, 0x0 },
+	{ "ppu_se_key_afifo_32x54_ecc_double_err_flag", DPP_FIELD_FLAG_RC, 3, 1,
+	  0x0, 0x0 },
+	{ "ppu_sta_key_ram_1r1w_32x110_ecc_single_err_flag", DPP_FIELD_FLAG_RC, 2,
+	  1, 0x0, 0x0 },
+	{ "ppu_se_key_afifo_32x665_ecc_single_err_flag", DPP_FIELD_FLAG_RC, 1, 1,
+	  0x0, 0x0 },
+	{ "ppu_se_key_afifo_32x54_ecc_single_err_flag", DPP_FIELD_FLAG_RC, 0, 1,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_sta_reg[] = {
+	{ "ppu_sta_key_ram_1r1w_32x110_ecc_double_err_stat", DPP_FIELD_FLAG_RO, 5,
+	  1, 0x0, 0x0 },
+	{ "ppu_se_key_afifo_32x665_ecc_double_err_stat", DPP_FIELD_FLAG_RO, 4, 1,
+	  0x0, 0x0 },
+	{ "ppu_se_key_afifo_32x54_ecc_double_err_stat", DPP_FIELD_FLAG_RO, 3, 1,
+	  0x0, 0x0 },
+	{ "ppu_sta_key_ram_1r1w_32x110_ecc_single_err_stat", DPP_FIELD_FLAG_RO, 2,
+	  1, 0x0, 0x0 },
+	{ "ppu_se_key_afifo_32x665_ecc_single_err_stat", DPP_FIELD_FLAG_RO, 1, 1,
+	  0x0, 0x0 },
+	{ "ppu_se_key_afifo_32x54_ecc_single_err_stat", DPP_FIELD_FLAG_RO, 0, 1,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_assert_cfg_reg[] = {
+	{ "ppu_cluster_mf_in_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6,
+	  0x10, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_negate_cfg_reg[] = {
+	{ "ppu_cluster_mf_in_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6,
+	  0x10, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ese_rsp_afifo_prog_full_assert_cfg_reg[] = {
+	{ "ese_rsp_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x2c,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ese_rsp_afifo_prog_full_negate_cfg_reg[] = {
+	{ "ese_rsp_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x2c,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ise_rsp_afifo_prog_full_assert_cfg_reg[] = {
+	{ "ise_rsp_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x29,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ise_rsp_afifo_prog_full_negate_cfg_reg[] = {
+	{ "ise_rsp_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x29,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_sta_rsp_afifo_prog_full_assert_cfg_reg[] = {
+	{ "sta_rsp_afifo_prog_full_assert_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x27,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_sta_rsp_afifo_prog_full_negate_cfg_reg[] = {
+	{ "sta_rsp_afifo_prog_full_negate_cfg", DPP_FIELD_FLAG_RW, 6, 7, 0x27,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_ise_key_afifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_ise_key_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_ise_key_afifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_ise_key_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_ese_key_afifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_ese_key_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_ese_key_afifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_ese_key_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_sta_key_afifo_prog_empty_assert_cfg_reg[] = {
+	{ "ppu_sta_key_afifo_prog_empty_assert_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_sta_key_afifo_prog_empty_negate_cfg_reg[] = {
+	{ "ppu_sta_key_afifo_prog_empty_negate_cfg", DPP_FIELD_FLAG_RW, 5, 6, 0x4,
+	  0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_vld_cnt_h_reg[] = {
+	{ "ppu_cluster_mf_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ppu_cluster_mf_vld_cnt_l_reg[] = {
+	{ "ppu_cluster_mf_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cluster_ise_key_out_vld_cnt_reg[] = {
+	{ "cluster_ise_key_out_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ise_cluster_rsp_in_vld_cnt_reg[] = {
+	{ "ise_cluster_rsp_in_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cluster_ese_key_out_vld_cnt_reg[] = {
+	{ "cluster_ese_key_out_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ese_cluster_rsp_in_vld_cnt_reg[] = {
+	{ "ese_cluster_rsp_in_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cluster_stat_cmd_vld_cnt_reg[] = {
+	{ "cluster_stat_cmd_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_stat_cluster_rsp_vld_cnt_reg[] = {
+	{ "stat_cluster_rsp_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mex_debug_key_vld_cnt_reg[] = {
+	{ "mex_debug_key_vld_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ise_cluster_key_fc_cnt_reg[] = {
+	{ "ise_cluster_key_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_ese_cluster_key_fc_cnt_reg[] = {
+	{ "ese_cluster_key_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cluster_ise_rsp_fc_cnt_reg[] = {
+	{ "cluster_ise_rsp_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cluster_ese_rsp_fc_cnt_reg[] = {
+	{ "cluster_ese_rsp_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_stat_cluster_cmd_fc_cnt_reg[] = {
+	{ "stat_cluster_cmd_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cluster_stat_rsp_fc_cnt_reg[] = {
+	{ "cluster_stat_rsp_fc_cnt", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cluster_ppu_mf_vld_cnt_l_reg[] = {
+	{ "cluster_ppu_mf_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cluster_ppu_mf_vld_cnt_h_reg[] = {
+	{ "cluster_ppu_mf_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cluster_cop_key_vld_cnt_l_reg[] = {
+	{ "cluster_cop_key_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cluster_cop_key_vld_cnt_h_reg[] = {
+	{ "cluster_cop_key_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cop_cluster_rsp_vld_cnt_l_reg[] = {
+	{ "cop_cluster_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_cop_cluster_rsp_vld_cnt_h_reg[] = {
+	{ "cop_cluster_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_sop_cnt_l_reg[] = {
+	{ "mex_me_pkt_in_sop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_sop_cnt_h_reg[] = {
+	{ "mex_me_pkt_in_sop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_eop_cnt_l_reg[] = {
+	{ "mex_me_pkt_in_eop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_eop_cnt_h_reg[] = {
+	{ "mex_me_pkt_in_eop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_vld_cnt_l_reg[] = {
+	{ "mex_me_pkt_in_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mex_me_pkt_in_vld_cnt_h_reg[] = {
+	{ "mex_me_pkt_in_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_sop_cnt_l_reg[] = {
+	{ "me_mex_pkt_out_sop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_sop_cnt_h_reg[] = {
+	{ "me_mex_pkt_out_sop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_eop_cnt_l_reg[] = {
+	{ "me_mex_pkt_out_eop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_eop_cnt_h_reg[] = {
+	{ "me_mex_pkt_out_eop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_vld_cnt_l_reg[] = {
+	{ "me_mex_pkt_out_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_pkt_out_vld_cnt_h_reg[] = {
+	{ "me_mex_pkt_out_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_sop_cnt_l_reg[] = {
+	{ "me_mex_i_key_out_sop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_sop_cnt_h_reg[] = {
+	{ "me_mex_i_key_out_sop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_eop_cnt_l_reg[] = {
+	{ "me_mex_i_key_out_eop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_eop_cnt_h_reg[] = {
+	{ "me_mex_i_key_out_eop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_vld_cnt_l_reg[] = {
+	{ "me_mex_i_key_out_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_i_key_out_vld_cnt_h_reg[] = {
+	{ "me_mex_i_key_out_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_sop_cnt_l_reg[] = {
+	{ "me_mex_e_key_out_sop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_sop_cnt_h_reg[] = {
+	{ "me_mex_e_key_out_sop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_eop_cnt_l_reg[] = {
+	{ "me_mex_e_key_out_eop_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_eop_cnt_h_reg[] = {
+	{ "me_mex_e_key_out_eop_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_vld_cnt_l_reg[] = {
+	{ "me_mex_e_key_out_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_e_key_out_vld_cnt_h_reg[] = {
+	{ "me_mex_e_key_out_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_demux_ise_key_vld_cnt_l_reg[] = {
+	{ "me_mex_demux_ise_key_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_demux_ise_key_vld_cnt_h_reg[] = {
+	{ "me_mex_demux_ise_key_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_demux_ese_key_vld_cnt_l_reg[] = {
+	{ "me_mex_demux_ese_key_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_demux_ese_key_vld_cnt_h_reg[] = {
+	{ "me_mex_demux_ese_key_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_demux_sta_key_vld_cnt_l_reg[] = {
+	{ "me_mex_demux_sta_key_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_demux_sta_key_vld_cnt_h_reg[] = {
+	{ "me_mex_demux_sta_key_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_demux_cop_key_vld_cnt_l_reg[] = {
+	{ "me_mex_demux_cop_key_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_mex_demux_cop_key_vld_cnt_h_reg[] = {
+	{ "me_mex_demux_cop_key_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_l_reg[] = {
+	{ "mex_me_demux_ise_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_h_reg[] = {
+	{ "mex_me_demux_ise_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_l_reg[] = {
+	{ "mex_me_demux_ese_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_h_reg[] = {
+	{ "mex_me_demux_ese_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_l_reg[] = {
+	{ "mex_me_demux_sta_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_h_reg[] = {
+	{ "mex_me_demux_sta_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_l_reg[] = {
+	{ "mex_me_demux_cop_rsp_vld_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_h_reg[] = {
+	{ "mex_me_demux_cop_rsp_vld_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_exception_code0_cnt_l_reg[] = {
+	{ "me_exception_code0_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_exception_code0_cnt_h_reg[] = {
+	{ "me_exception_code0_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_exception_code1_cnt_l_reg[] = {
+	{ "me_exception_code1_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_exception_code1_cnt_h_reg[] = {
+	{ "me_exception_code1_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_exception_code2_cnt_l_reg[] = {
+	{ "me_exception_code2_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_exception_code2_cnt_h_reg[] = {
+	{ "me_exception_code2_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_exception_code3_cnt_l_reg[] = {
+	{ "me_exception_code3_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_exception_code3_cnt_h_reg[] = {
+	{ "me_exception_code3_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_exception_code4_cnt_l_reg[] = {
+	{ "me_exception_code4_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_exception_code4_cnt_h_reg[] = {
+	{ "me_exception_code4_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_exception_code5_cnt_l_reg[] = {
+	{ "me_exception_code5_cnt_l", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ppu_cluster_me_exception_code5_cnt_h_reg[] = {
+	{ "me_exception_code5_cnt_h", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_ppu_soft_rst_reg[] = {
+	{ "ppu_soft_rst", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_ept_flag_reg[] = {
+	{ "ept_flag", DPP_FIELD_FLAG_RO, 5, 6, 0x3f, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_ddr_key_lk0_3_reg[] = {
+	{ "ddr_key_lk0_3", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_ddr_key_lk0_2_reg[] = {
+	{ "ddr_key_lk0_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_ddr_key_lk0_1_reg[] = {
+	{ "ddr_key_lk0_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_ddr_key_lk0_0_reg[] = {
+	{ "ddr_key_lk0_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_ddr_key_lk1_3_reg[] = {
+	{ "ddr_key_lk1_3", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_ddr_key_lk1_2_reg[] = {
+	{ "ddr_key_lk1_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_ddr_key_lk1_1_reg[] = {
+	{ "ddr_key_lk1_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_ddr_key_lk1_0_reg[] = {
+	{ "ddr_key_lk1_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_18_reg[] = {
+	{ "hash_key_lk0_18", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_17_reg[] = {
+	{ "hash_key_lk0_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_16_reg[] = {
+	{ "hash_key_lk0_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_15_reg[] = {
+	{ "hash_key_lk0_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_14_reg[] = {
+	{ "hash_key_lk0_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_13_reg[] = {
+	{ "hash_key_lk0_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_12_reg[] = {
+	{ "hash_key_lk0_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_11_reg[] = {
+	{ "hash_key_lk0_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_10_reg[] = {
+	{ "hash_key_lk0_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_9_reg[] = {
+	{ "hash_key_lk0_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_8_reg[] = {
+	{ "hash_key_lk0_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_7_reg[] = {
+	{ "hash_key_lk0_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_6_reg[] = {
+	{ "hash_key_lk0_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_5_reg[] = {
+	{ "hash_key_lk0_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_4_reg[] = {
+	{ "hash_key_lk0_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_3_reg[] = {
+	{ "hash_key_lk0_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_2_reg[] = {
+	{ "hash_key_lk0_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_1_reg[] = {
+	{ "hash_key_lk0_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk0_0_reg[] = {
+	{ "hash_key_lk0_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_18_reg[] = {
+	{ "hash_key_lk1_18", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_17_reg[] = {
+	{ "hash_key_lk1_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_16_reg[] = {
+	{ "hash_key_lk1_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_15_reg[] = {
+	{ "hash_key_lk1_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_14_reg[] = {
+	{ "hash_key_lk1_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_13_reg[] = {
+	{ "hash_key_lk1_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_12_reg[] = {
+	{ "hash_key_lk1_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_11_reg[] = {
+	{ "hash_key_lk1_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_10_reg[] = {
+	{ "hash_key_lk1_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_9_reg[] = {
+	{ "hash_key_lk1_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_8_reg[] = {
+	{ "hash_key_lk1_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_7_reg[] = {
+	{ "hash_key_lk1_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_6_reg[] = {
+	{ "hash_key_lk1_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_5_reg[] = {
+	{ "hash_key_lk1_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_4_reg[] = {
+	{ "hash_key_lk1_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_3_reg[] = {
+	{ "hash_key_lk1_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_2_reg[] = {
+	{ "hash_key_lk1_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_1_reg[] = {
+	{ "hash_key_lk1_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk1_0_reg[] = {
+	{ "hash_key_lk1_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_18_reg[] = {
+	{ "hash_key_lk2_18", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_17_reg[] = {
+	{ "hash_key_lk2_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_16_reg[] = {
+	{ "hash_key_lk2_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_15_reg[] = {
+	{ "hash_key_lk2_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_14_reg[] = {
+	{ "hash_key_lk2_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_13_reg[] = {
+	{ "hash_key_lk2_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_12_reg[] = {
+	{ "hash_key_lk2_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_11_reg[] = {
+	{ "hash_key_lk2_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_10_reg[] = {
+	{ "hash_key_lk2_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_9_reg[] = {
+	{ "hash_key_lk2_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_8_reg[] = {
+	{ "hash_key_lk2_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_7_reg[] = {
+	{ "hash_key_lk2_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_6_reg[] = {
+	{ "hash_key_lk2_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_5_reg[] = {
+	{ "hash_key_lk2_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_4_reg[] = {
+	{ "hash_key_lk2_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_3_reg[] = {
+	{ "hash_key_lk2_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_2_reg[] = {
+	{ "hash_key_lk2_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_1_reg[] = {
+	{ "hash_key_lk2_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk2_0_reg[] = {
+	{ "hash_key_lk2_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_18_reg[] = {
+	{ "hash_key_lk3_18", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_17_reg[] = {
+	{ "hash_key_lk3_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_16_reg[] = {
+	{ "hash_key_lk3_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_15_reg[] = {
+	{ "hash_key_lk3_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_14_reg[] = {
+	{ "hash_key_lk3_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_13_reg[] = {
+	{ "hash_key_lk3_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_12_reg[] = {
+	{ "hash_key_lk3_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_11_reg[] = {
+	{ "hash_key_lk3_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_10_reg[] = {
+	{ "hash_key_lk3_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_9_reg[] = {
+	{ "hash_key_lk3_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_8_reg[] = {
+	{ "hash_key_lk3_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_7_reg[] = {
+	{ "hash_key_lk3_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_6_reg[] = {
+	{ "hash_key_lk3_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_5_reg[] = {
+	{ "hash_key_lk3_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_4_reg[] = {
+	{ "hash_key_lk3_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_3_reg[] = {
+	{ "hash_key_lk3_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_2_reg[] = {
+	{ "hash_key_lk3_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_1_reg[] = {
+	{ "hash_key_lk3_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_hash_key_lk3_0_reg[] = {
+	{ "hash_key_lk3_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk0_6_reg[] = {
+	{ "lpm_key_lk0_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk0_5_reg[] = {
+	{ "lpm_key_lk0_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk0_4_reg[] = {
+	{ "lpm_key_lk0_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk0_3_reg[] = {
+	{ "lpm_key_lk0_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk0_2_reg[] = {
+	{ "lpm_key_lk0_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk0_1_reg[] = {
+	{ "lpm_key_lk0_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk0_0_reg[] = {
+	{ "lpm_key_lk0_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk1_6_reg[] = {
+	{ "lpm_key_lk1_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk1_5_reg[] = {
+	{ "lpm_key_lk1_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk1_4_reg[] = {
+	{ "lpm_key_lk1_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk1_3_reg[] = {
+	{ "lpm_key_lk1_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk1_2_reg[] = {
+	{ "lpm_key_lk1_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk1_1_reg[] = {
+	{ "lpm_key_lk1_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk1_0_reg[] = {
+	{ "lpm_key_lk1_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk2_6_reg[] = {
+	{ "lpm_key_lk2_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk2_5_reg[] = {
+	{ "lpm_key_lk2_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk2_4_reg[] = {
+	{ "lpm_key_lk2_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk2_3_reg[] = {
+	{ "lpm_key_lk2_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk2_2_reg[] = {
+	{ "lpm_key_lk2_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk2_1_reg[] = {
+	{ "lpm_key_lk2_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk2_0_reg[] = {
+	{ "lpm_key_lk2_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk3_6_reg[] = {
+	{ "lpm_key_lk3_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk3_5_reg[] = {
+	{ "lpm_key_lk3_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk3_4_reg[] = {
+	{ "lpm_key_lk3_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk3_3_reg[] = {
+	{ "lpm_key_lk3_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk3_2_reg[] = {
+	{ "lpm_key_lk3_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk3_1_reg[] = {
+	{ "lpm_key_lk3_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_lpm_key_lk3_0_reg[] = {
+	{ "lpm_key_lk3_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_22_reg[] = {
+	{ "etcam_key_lk0_22", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_21_reg[] = {
+	{ "etcam_key_lk0_21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_20_reg[] = {
+	{ "etcam_key_lk0_20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_19_reg[] = {
+	{ "etcam_key_lk0_19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_18_reg[] = {
+	{ "etcam_key_lk0_18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_17_reg[] = {
+	{ "etcam_key_lk0_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_16_reg[] = {
+	{ "etcam_key_lk0_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_15_reg[] = {
+	{ "etcam_key_lk0_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_14_reg[] = {
+	{ "etcam_key_lk0_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_13_reg[] = {
+	{ "etcam_key_lk0_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_12_reg[] = {
+	{ "etcam_key_lk0_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_11_reg[] = {
+	{ "etcam_key_lk0_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_10_reg[] = {
+	{ "etcam_key_lk0_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_9_reg[] = {
+	{ "etcam_key_lk0_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_8_reg[] = {
+	{ "etcam_key_lk0_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_7_reg[] = {
+	{ "etcam_key_lk0_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_6_reg[] = {
+	{ "etcam_key_lk0_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_5_reg[] = {
+	{ "etcam_key_lk0_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_4_reg[] = {
+	{ "etcam_key_lk0_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_3_reg[] = {
+	{ "etcam_key_lk0_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_2_reg[] = {
+	{ "etcam_key_lk0_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_1_reg[] = {
+	{ "etcam_key_lk0_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk0_0_reg[] = {
+	{ "etcam_key_lk0_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_22_reg[] = {
+	{ "etcam_key_lk1_22", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_21_reg[] = {
+	{ "etcam_key_lk1_21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_20_reg[] = {
+	{ "etcam_key_lk1_20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_19_reg[] = {
+	{ "etcam_key_lk1_19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_18_reg[] = {
+	{ "etcam_key_lk1_18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_17_reg[] = {
+	{ "etcam_key_lk1_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_16_reg[] = {
+	{ "etcam_key_lk1_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_15_reg[] = {
+	{ "etcam_key_lk1_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_14_reg[] = {
+	{ "etcam_key_lk1_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_13_reg[] = {
+	{ "etcam_key_lk1_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_12_reg[] = {
+	{ "etcam_key_lk1_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_11_reg[] = {
+	{ "etcam_key_lk1_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_10_reg[] = {
+	{ "etcam_key_lk1_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_9_reg[] = {
+	{ "etcam_key_lk1_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_8_reg[] = {
+	{ "etcam_key_lk1_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_7_reg[] = {
+	{ "etcam_key_lk1_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_6_reg[] = {
+	{ "etcam_key_lk1_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_5_reg[] = {
+	{ "etcam_key_lk1_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_4_reg[] = {
+	{ "etcam_key_lk1_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_3_reg[] = {
+	{ "etcam_key_lk1_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_2_reg[] = {
+	{ "etcam_key_lk1_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_1_reg[] = {
+	{ "etcam_key_lk1_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk1_0_reg[] = {
+	{ "etcam_key_lk1_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_22_reg[] = {
+	{ "etcam_key_lk2_22", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_21_reg[] = {
+	{ "etcam_key_lk2_21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_20_reg[] = {
+	{ "etcam_key_lk2_20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_19_reg[] = {
+	{ "etcam_key_lk2_19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_18_reg[] = {
+	{ "etcam_key_lk2_18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_17_reg[] = {
+	{ "etcam_key_lk2_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_16_reg[] = {
+	{ "etcam_key_lk2_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_15_reg[] = {
+	{ "etcam_key_lk2_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_14_reg[] = {
+	{ "etcam_key_lk2_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_13_reg[] = {
+	{ "etcam_key_lk2_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_12_reg[] = {
+	{ "etcam_key_lk2_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_11_reg[] = {
+	{ "etcam_key_lk2_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_10_reg[] = {
+	{ "etcam_key_lk2_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_9_reg[] = {
+	{ "etcam_key_lk2_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_8_reg[] = {
+	{ "etcam_key_lk2_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_7_reg[] = {
+	{ "etcam_key_lk2_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_6_reg[] = {
+	{ "etcam_key_lk2_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_5_reg[] = {
+	{ "etcam_key_lk2_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_4_reg[] = {
+	{ "etcam_key_lk2_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_3_reg[] = {
+	{ "etcam_key_lk2_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_2_reg[] = {
+	{ "etcam_key_lk2_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_1_reg[] = {
+	{ "etcam_key_lk2_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk2_0_reg[] = {
+	{ "etcam_key_lk2_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_22_reg[] = {
+	{ "etcam_key_lk3_22", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_21_reg[] = {
+	{ "etcam_key_lk3_21", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_20_reg[] = {
+	{ "etcam_key_lk3_20", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_19_reg[] = {
+	{ "etcam_key_lk3_19", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_18_reg[] = {
+	{ "etcam_key_lk3_18", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_17_reg[] = {
+	{ "etcam_key_lk3_17", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_16_reg[] = {
+	{ "etcam_key_lk3_16", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_15_reg[] = {
+	{ "etcam_key_lk3_15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_14_reg[] = {
+	{ "etcam_key_lk3_14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_13_reg[] = {
+	{ "etcam_key_lk3_13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_12_reg[] = {
+	{ "etcam_key_lk3_12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_11_reg[] = {
+	{ "etcam_key_lk3_11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_10_reg[] = {
+	{ "etcam_key_lk3_10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_9_reg[] = {
+	{ "etcam_key_lk3_9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_8_reg[] = {
+	{ "etcam_key_lk3_8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_7_reg[] = {
+	{ "etcam_key_lk3_7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_6_reg[] = {
+	{ "etcam_key_lk3_6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_5_reg[] = {
+	{ "etcam_key_lk3_5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_4_reg[] = {
+	{ "etcam_key_lk3_4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_3_reg[] = {
+	{ "etcam_key_lk3_3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_2_reg[] = {
+	{ "etcam_key_lk3_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_1_reg[] = {
+	{ "etcam_key_lk3_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_etcam_key_lk3_0_reg[] = {
+	{ "etcam_key_lk3_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_pbu_key_lk0_3_reg[] = {
+	{ "pbu_key_lk0_3", DPP_FIELD_FLAG_RO, 20, 21, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_pbu_key_lk0_2_reg[] = {
+	{ "pbu_key_lk0_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_pbu_key_lk0_1_reg[] = {
+	{ "pbu_key_lk0_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_pbu_key_lk0_0_reg[] = {
+	{ "pbu_key_lk0_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_pbu_key_lk1_3_reg[] = {
+	{ "pbu_key_lk1_3", DPP_FIELD_FLAG_RO, 20, 21, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_pbu_key_lk1_2_reg[] = {
+	{ "pbu_key_lk1_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_pbu_key_lk1_1_reg[] = {
+	{ "pbu_key_lk1_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_pbu_key_lk1_0_reg[] = {
+	{ "pbu_key_lk1_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_pbu_key_lk2_3_reg[] = {
+	{ "pbu_key_lk2_3", DPP_FIELD_FLAG_RO, 20, 21, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_pbu_key_lk2_2_reg[] = {
+	{ "pbu_key_lk2_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_pbu_key_lk2_1_reg[] = {
+	{ "pbu_key_lk2_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_pbu_key_lk2_0_reg[] = {
+	{ "pbu_key_lk2_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_pbu_key_lk3_3_reg[] = {
+	{ "pbu_key_lk3_3", DPP_FIELD_FLAG_RO, 20, 21, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_pbu_key_lk3_2_reg[] = {
+	{ "pbu_key_lk3_2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_pbu_key_lk3_1_reg[] = {
+	{ "pbu_key_lk3_1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cfg_pbu_key_lk3_0_reg[] = {
+	{ "pbu_key_lk3_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_learn_fifo_pfull_ast_reg[] = {
+	{ "schd_learn_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_learn_fifo_pfull_neg_reg[] = {
+	{ "schd_learn_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_hash0_fifo_pfull_ast_reg[] = {
+	{ "schd_hash0_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_hash0_fifo_pfull_neg_reg[] = {
+	{ "schd_hash0_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_hash1_fifo_pfull_ast_reg[] = {
+	{ "schd_hash1_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_hash1_fifo_pfull_neg_reg[] = {
+	{ "schd_hash1_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_hash2_fifo_pfull_ast_reg[] = {
+	{ "schd_hash2_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_hash2_fifo_pfull_neg_reg[] = {
+	{ "schd_hash2_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_hash3_fifo_pfull_ast_reg[] = {
+	{ "schd_hash3_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_hash3_fifo_pfull_neg_reg[] = {
+	{ "schd_hash3_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_lpm_fifo_pfull_ast_reg[] = {
+	{ "schd_lpm_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_lpm_fifo_pfull_neg_reg[] = {
+	{ "schd_lpm_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_key_fifo_pfull_ast_reg[] = {
+	{ "hash0_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_key_fifo_pfull_neg_reg[] = {
+	{ "hash0_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_sreq_fifo_pfull_ast_reg[] = {
+	{ "hash0_sreq_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_sreq_fifo_pfull_neg_reg[] = {
+	{ "hash0_sreq_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_int_rsp_fifo_pfull_ast_reg[] = {
+	{ "hash0_int_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_int_rsp_fifo_pfull_neg_reg[] = {
+	{ "hash0_int_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_ext_rsp_fifo_pfull_ast_reg[] = {
+	{ "hash0_ext_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x20, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_ext_rsp_fifo_pfull_neg_reg[] = {
+	{ "hash0_ext_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_key_fifo_pfull_ast_reg[] = {
+	{ "hash1_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_key_fifo_pfull_neg_reg[] = {
+	{ "hash1_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_sreq_fifo_pfull_ast_reg[] = {
+	{ "hash1_sreq_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_sreq_fifo_pfull_neg_reg[] = {
+	{ "hash1_sreq_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_int_rsp_fifo_pfull_ast_reg[] = {
+	{ "hash1_int_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_int_rsp_fifo_pfull_neg_reg[] = {
+	{ "hash1_int_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_ext_rsp_fifo_pfull_ast_reg[] = {
+	{ "hash1_ext_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x20, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_ext_rsp_fifo_pfull_neg_reg[] = {
+	{ "hash1_ext_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_key_fifo_pfull_ast_reg[] = {
+	{ "hash2_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_key_fifo_pfull_neg_reg[] = {
+	{ "hash2_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_sreq_fifo_pfull_ast_reg[] = {
+	{ "hash2_sreq_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_sreq_fifo_pfull_neg_reg[] = {
+	{ "hash2_sreq_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_int_rsp_fifo_pfull_ast_reg[] = {
+	{ "hash2_int_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_int_rsp_fifo_pfull_neg_reg[] = {
+	{ "hash2_int_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_ext_rsp_fifo_pfull_ast_reg[] = {
+	{ "hash2_ext_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x20, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_ext_rsp_fifo_pfull_neg_reg[] = {
+	{ "hash2_ext_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_key_fifo_pfull_ast_reg[] = {
+	{ "hash3_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_key_fifo_pfull_neg_reg[] = {
+	{ "hash3_key_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_sreq_fifo_pfull_ast_reg[] = {
+	{ "hash3_sreq_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_sreq_fifo_pfull_neg_reg[] = {
+	{ "hash3_sreq_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_int_rsp_fifo_pfull_ast_reg[] = {
+	{ "hash3_int_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1cc, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_int_rsp_fifo_pfull_neg_reg[] = {
+	{ "hash3_int_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1c8, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_ext_rsp_fifo_pfull_ast_reg[] = {
+	{ "hash3_ext_rsp_fifo_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x20, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_ext_rsp_fifo_pfull_neg_reg[] = {
+	{ "hash3_ext_rsp_fifo_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x1e, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_as_info_reg[] = {
+	{ "lpm_as_type", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "lpm_as_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u0_pfull_neg_reg[] = {
+	{ "lpm_ext_rsp_fifo_u0_pfull_neg", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u2_pfull_ast_reg[] = {
+	{ "lpm_ext_rsp_fifo_u2_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1e4, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u2_pfull_neg_reg[] = {
+	{ "lpm_ext_rsp_fifo_u2_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1e0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u3_pfull_ast_reg[] = {
+	{ "lpm_ext_rsp_fifo_u3_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1e4, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u3_pfull_neg_reg[] = {
+	{ "lpm_ext_rsp_fifo_u3_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1e0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u4_pfull_ast_reg[] = {
+	{ "lpm_ext_rsp_fifo_u4_pfull_ast", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_u4_pfull_neg_reg[] = {
+	{ "lpm_ext_rsp_fifo_u4_pfull_neg", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_as_rsp_fifo_u0_pfull_ast_reg[] = {
+	{ "lpm_as_rsp_fifo_u0_pfull_ast", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_as_rsp_fifo_u0_pfull_neg_reg[] = {
+	{ "lpm_as_rsp_fifo_u0_pfull_neg", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_as_rsp_fifo_u1_pfull_ast_reg[] = {
+	{ "lpm_as_rsp_fifo_u1_pfull_ast", DPP_FIELD_FLAG_RW, 9, 10, 0x1e2, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_as_rsp_fifo_u1_pfull_neg_reg[] = {
+	{ "lpm_as_rsp_fifo_u1_pfull_neg", DPP_FIELD_FLAG_RW, 9, 10, 0x1dc, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_v4_ddr3_base_addr_reg[] = {
+	{ "lpm_v4_ddr3_base_addr", DPP_FIELD_FLAG_RW, 25, 26, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_v6_ddr3_base_addr_reg[] = {
+	{ "lpm_v6_ddr3_base_addr", DPP_FIELD_FLAG_RW, 25, 26, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_debug_cnt_mode_reg[] = {
+	{ "cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash_p0_key_vld_cnt_reg[] = {
+	{ "hash_p0_key_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash_p1_key_vld_cnt_reg[] = {
+	{ "hash_p1_key_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash_p2_key_vld_cnt_reg[] = {
+	{ "hash_p2_key_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash_p3_key_vld_cnt_reg[] = {
+	{ "hash_p3_key_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_p0_key_vld_cnt_reg[] = {
+	{ "lpm_p0_key_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash_p0_rsp_vld_cnt_reg[] = {
+	{ "hash_p0_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash_p1_rsp_vld_cnt_reg[] = {
+	{ "hash_p1_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash_p2_rsp_vld_cnt_reg[] = {
+	{ "hash_p2_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash_p3_rsp_vld_cnt_reg[] = {
+	{ "hash_p3_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_p0_rsp_vld_cnt_reg[] = {
+	{ "lpm_p0_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash_p0_smf_cnt_reg[] = {
+	{ "hash_p0_smf_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash_p1_smf_cnt_reg[] = {
+	{ "hash_p1_smf_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash_p2_smf_cnt_reg[] = {
+	{ "hash_p2_smf_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash_p3_smf_cnt_reg[] = {
+	{ "hash_p3_smf_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_p0_smf_cnt_reg[] = {
+	{ "lpm_p0_smf_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash_p0_spacevld_cnt_reg[] = {
+	{ "hash_p0_spacevld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash_p1_spacevld_cnt_reg[] = {
+	{ "hash_p1_spacevld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash_p2_spacevld_cnt_reg[] = {
+	{ "hash_p2_spacevld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash_p3_spacevld_cnt_reg[] = {
+	{ "hash_p3_spacevld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_smmu1_p0_req_vld_cnt_reg[] = {
+	{ "smmu1_p0_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_smmu1_p1_req_vld_cnt_reg[] = {
+	{ "smmu1_p1_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_smmu1_p2_req_vld_cnt_reg[] = {
+	{ "smmu1_p2_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_smmu1_p3_req_vld_cnt_reg[] = {
+	{ "smmu1_p3_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_smmu1_p4_req_vld_cnt_reg[] = {
+	{ "smmu1_p4_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_smmu1_p5_req_vld_cnt_reg[] = {
+	{ "smmu1_p5_req_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_smmu1_p0_rsp_vld_cnt_reg[] = {
+	{ "smmu1_p0_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_smmu1_p1_rsp_vld_cnt_reg[] = {
+	{ "smmu1_p1_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_smmu1_p2_rsp_vld_cnt_reg[] = {
+	{ "smmu1_p2_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_smmu1_p3_rsp_vld_cnt_reg[] = {
+	{ "smmu1_p3_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_smmu1_p4_rsp_vld_cnt_reg[] = {
+	{ "smmu1_p4_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_smmu1_p5_rsp_vld_cnt_reg[] = {
+	{ "smmu1_p5_rsp_vld_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_learn_fifo_int_cnt_reg[] = {
+	{ "schd_learn_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_hash0_fifo_int_cnt_reg[] = {
+	{ "schd_hash0_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_hash1_fifo_int_cnt_reg[] = {
+	{ "schd_hash1_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_hash2_fifo_int_cnt_reg[] = {
+	{ "schd_hash2_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_hash3_fifo_int_cnt_reg[] = {
+	{ "schd_hash3_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_lpm_fifo_int_cnt_reg[] = {
+	{ "schd_lpm_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_learn_fifo_parity_err_cnt_reg[] = {
+	{ "schd_learn_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_hash0_fifo_parity_err_cnt_reg[] = {
+	{ "schd_hash0_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_hash1_fifo_parity_err_cnt_reg[] = {
+	{ "schd_hash1_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_hash2_fifo_parity_err_cnt_reg[] = {
+	{ "schd_hash2_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_hash3_fifo_parity_err_cnt_reg[] = {
+	{ "schd_hash3_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_lpm_fifo_parity_err_cnt_reg[] = {
+	{ "schd_lpm_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_rd_init_cft_cnt_reg[] = {
+	{ "rd_init_cft_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp0_zblk0_ecc_err_cnt_reg[] = {
+	{ "zgp0_zblk0_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp0_zblk1_ecc_err_cnt_reg[] = {
+	{ "zgp0_zblk1_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp0_zblk2_ecc_err_cnt_reg[] = {
+	{ "zgp0_zblk2_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp0_zblk3_ecc_err_cnt_reg[] = {
+	{ "zgp0_zblk3_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp0_zblk4_ecc_err_cnt_reg[] = {
+	{ "zgp0_zblk4_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp0_zblk5_ecc_err_cnt_reg[] = {
+	{ "zgp0_zblk5_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp0_zblk6_ecc_err_cnt_reg[] = {
+	{ "zgp0_zblk6_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp0_zblk7_ecc_err_cnt_reg[] = {
+	{ "zgp0_zblk7_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp1_zblk0_ecc_err_cnt_reg[] = {
+	{ "zgp1_zblk0_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp1_zblk1_ecc_err_cnt_reg[] = {
+	{ "zgp1_zblk1_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp1_zblk2_ecc_err_cnt_reg[] = {
+	{ "zgp1_zblk2_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp1_zblk3_ecc_err_cnt_reg[] = {
+	{ "zgp1_zblk3_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp1_zblk4_ecc_err_cnt_reg[] = {
+	{ "zgp1_zblk4_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp1_zblk5_ecc_err_cnt_reg[] = {
+	{ "zgp1_zblk5_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp1_zblk6_ecc_err_cnt_reg[] = {
+	{ "zgp1_zblk6_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp1_zblk7_ecc_err_cnt_reg[] = {
+	{ "zgp1_zblk7_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp2_zblk0_ecc_err_cnt_reg[] = {
+	{ "zgp2_zblk0_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp2_zblk1_ecc_err_cnt_reg[] = {
+	{ "zgp2_zblk1_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp2_zblk2_ecc_err_cnt_reg[] = {
+	{ "zgp2_zblk2_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp2_zblk3_ecc_err_cnt_reg[] = {
+	{ "zgp2_zblk3_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp2_zblk4_ecc_err_cnt_reg[] = {
+	{ "zgp2_zblk4_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp2_zblk5_ecc_err_cnt_reg[] = {
+	{ "zgp2_zblk5_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp2_zblk6_ecc_err_cnt_reg[] = {
+	{ "zgp2_zblk6_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp2_zblk7_ecc_err_cnt_reg[] = {
+	{ "zgp2_zblk7_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp3_zblk0_ecc_err_cnt_reg[] = {
+	{ "zgp3_zblk0_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp3_zblk1_ecc_err_cnt_reg[] = {
+	{ "zgp3_zblk1_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp3_zblk2_ecc_err_cnt_reg[] = {
+	{ "zgp3_zblk2_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp3_zblk3_ecc_err_cnt_reg[] = {
+	{ "zgp3_zblk3_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp3_zblk4_ecc_err_cnt_reg[] = {
+	{ "zgp3_zblk4_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp3_zblk5_ecc_err_cnt_reg[] = {
+	{ "zgp3_zblk5_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp3_zblk6_ecc_err_cnt_reg[] = {
+	{ "zgp3_zblk6_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zgp3_zblk7_ecc_err_cnt_reg[] = {
+	{ "zgp3_zblk7_ecc_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zcam_hash_p0_err_cnt_reg[] = {
+	{ "zcam_hash_p0_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zcam_hash_p1_err_cnt_reg[] = {
+	{ "zcam_hash_p1_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zcam_hash_p2_err_cnt_reg[] = {
+	{ "zcam_hash_p2_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zcam_hash_p3_err_cnt_reg[] = {
+	{ "zcam_hash_p3_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zcam_lpm_err_cnt_reg[] = {
+	{ "zcam_lpm_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_sreq_fifo_parity_err_cnt_reg[] = {
+	{ "hash0_sreq_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_sreq_fifo_int_cnt_reg[] = {
+	{ "hash0_sreq_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_key_fifo_int_cnt_reg[] = {
+	{ "hash0_key_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_int_rsp_fifo_parity_err_cnt_reg[] = {
+	{ "hash0_int_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_ext_rsp_fifo_parity_err_cnt_reg[] = {
+	{ "hash0_ext_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_ext_rsp_fifo_int_cnt_reg[] = {
+	{ "hash0_ext_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_int_rsp_fifo_int_cnt_reg[] = {
+	{ "hash0_int_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_sreq_fifo_parity_err_cnt_reg[] = {
+	{ "hash1_sreq_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_sreq_fifo_int_cnt_reg[] = {
+	{ "hash1_sreq_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_key_fifo_int_cnt_reg[] = {
+	{ "hash1_key_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_int_rsp_fifo_parity_err_cnt_reg[] = {
+	{ "hash1_int_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_ext_rsp_fifo_parity_err_cnt_reg[] = {
+	{ "hash1_ext_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_ext_rsp_fifo_int_cnt_reg[] = {
+	{ "hash1_ext_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_int_rsp_fifo_int_cnt_reg[] = {
+	{ "hash1_int_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_sreq_fifo_parity_err_cnt_reg[] = {
+	{ "hash2_sreq_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_sreq_fifo_int_cnt_reg[] = {
+	{ "hash2_sreq_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_key_fifo_int_cnt_reg[] = {
+	{ "hash2_key_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_int_rsp_fifo_parity_err_cnt_reg[] = {
+	{ "hash2_int_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_ext_rsp_fifo_parity_err_cnt_reg[] = {
+	{ "hash2_ext_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_ext_rsp_fifo_int_cnt_reg[] = {
+	{ "hash2_ext_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_int_rsp_fifo_int_cnt_reg[] = {
+	{ "hash2_int_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_sreq_fifo_parity_err_cnt_reg[] = {
+	{ "hash3_sreq_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_sreq_fifo_int_cnt_reg[] = {
+	{ "hash3_sreq_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_key_fifo_int_cnt_reg[] = {
+	{ "hash3_key_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_int_rsp_fifo_parity_err_cnt_reg[] = {
+	{ "hash3_int_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_ext_rsp_fifo_parity_err_cnt_reg[] = {
+	{ "hash3_ext_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_ext_rsp_fifo_int_cnt_reg[] = {
+	{ "hash3_ext_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_int_rsp_fifo_int_cnt_reg[] = {
+	{ "hash3_int_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_int_cnt_reg[] = {
+	{ "lpm_ext_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_ext_v6_fifo_int_cnt_reg[] = {
+	{ "lpm_ext_v6_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_ext_v4_fifo_int_cnt_reg[] = {
+	{ "lpm_ext_v4_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_ext_addr_fifo_int_cnt_reg[] = {
+	{ "lpm_ext_addr_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_ext_v4_fifo_parity_err_cnt_reg[] = {
+	{ "lpm_ext_v4_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_ext_v6_fifo_parity_err_cnt_reg[] = {
+	{ "lpm_ext_v6_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_ext_rsp_fifo_parity_err_cnt_reg[] = {
+	{ "lpm_ext_rsp_fifo_parity_err_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_as_req_fifo_int_cnt_reg[] = {
+	{ "lpm_as_req_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_as_int_rsp_fifo_int_cnt_reg[] = {
+	{ "lpm_as_int_rsp_fifo_int_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_se_alg_int_status_reg[] = {
+	{ "schd_int_unmask_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "zblk_ecc_int_unmask_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "hash0_int_unmask_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "hash1_int_unmask_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "hash2_int_unmask_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "hash3_int_unmask_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "lpm_int_unmask_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_int_en_reg[] = {
+	{ "wr_rsp_fifo_ovfl", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "init_rd_cft_en", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "schd_lpm_fifo_parity_errl", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "schd_hash3_fifo_parity_err", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "schd_hash2_fifo_parity_err", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "schd_hash1_fifo_parity_err", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "schd_hash0_fifo_parity_err", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "schd_learn_fifo_parity_err", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "schd_lpm_fifo_ovfl", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "schd_hash3_fifo_ovfl", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "schd_hash2_fifo_unfl", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "schd_hash1_fifo_ovfl", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "schd_hash0_fifo_ovfl", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "schd_learn_fifo_ovfl", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_int_mask_reg[] = {
+	{ "schd_int_mask", DPP_FIELD_FLAG_RW, 13, 14, 0x3fff, 0x0 },
+};
+DPP_FIELD_T g_se_alg_schd_int_status_reg[] = {
+	{ "schd_int_status", DPP_FIELD_FLAG_RC, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblk_ecc_int_en_reg[] = {
+	{ "zblk_ecc_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffff, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblk_ecc_int_mask_reg[] = {
+	{ "zblk_ecc_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffff, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblk_ecc_int_status_reg[] = {
+	{ "zblk_ecc_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_int_en_reg[] = {
+	{ "zcam_hash_p0_err_en", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "hash0_agree_int_fifo_ovf_en", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "hash0_agree_ext_fifo_ovf_en", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "hash0_agree_ext_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "hash0_agree_int_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "hash0_key_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "hash0_sreq_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "hash0_key_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_int_mask_reg[] = {
+	{ "hash0_int_mask", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash0_int_status_reg[] = {
+	{ "hash0_int_status", DPP_FIELD_FLAG_RC, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_int_en_reg[] = {
+	{ "zcam_hash_p1_err_en", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "hash1_agree_int_fifo_ovf_en", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "hash1_agree_ext_fifo_ovf_en", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "hash1_agree_ext_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "hash1_agree_int_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "hash1_key_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "hash1_sreq_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "hash1_key_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_int_mask_reg[] = {
+	{ "hash1_int_mask", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash1_int_status_reg[] = {
+	{ "hash1_int_status", DPP_FIELD_FLAG_RC, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_int_en_reg[] = {
+	{ "zcam_hash_p2_err_en", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "hash2_agree_int_fifo_ovf_en", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "hash2_agree_ext_fifo_ovf_en", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "hash2_agree_ext_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "hash2_agree_int_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "hash2_key_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "hash2_sreq_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "hash2_key_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_int_mask_reg[] = {
+	{ "hash2_int_mask", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash2_int_status_reg[] = {
+	{ "hash2_int_status", DPP_FIELD_FLAG_RC, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_int_en_reg[] = {
+	{ "zcam_hash_p3_err_en", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "hash3_agree_int_fifo_ovf_en", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "hash3_agree_ext_fifo_ovf_en", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "hash3_agree_ext_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "hash3_agree_int_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "hash3_key_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "hash3_sreq_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "hash3_key_fifo_parity_err_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_int_mask_reg[] = {
+	{ "hash3_int_mask", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_se_alg_hash3_int_status_reg[] = {
+	{ "hash3_int_status", DPP_FIELD_FLAG_RC, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_int_en_reg[] = {
+	{ "zcam_lpm_err_en", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "lpm_as_int_rsp_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "lpm_as_req_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "lpm_ext_ddr_rsp_fifo_parity_en", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "lpm_ext_v6_key_parity_en", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "lpm_ext_v4_key_parity_en", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "lpm_ext_addr_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "lpm_ext_v4_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "lpm_ext_v6_fifo_ovfl_en", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "lpm_ext_ddr_rsp_ovf_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_int_mask_reg[] = {
+	{ "lpm_int_mask", DPP_FIELD_FLAG_RW, 9, 10, 0x3ff, 0x0 },
+};
+DPP_FIELD_T g_se_alg_lpm_int_status_reg[] = {
+	{ "lpm_int_status", DPP_FIELD_FLAG_RC, 9, 10, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_lpm_mask0_reg[] = {
+	{ "vpn_id_mask", DPP_FIELD_FLAG_RW, 143, 16, 0x0, 0x0 },
+	{ "prefix0_mask", DPP_FIELD_FLAG_RW, 127, 32, 0x0, 0x0 },
+	{ "prefix1_mask", DPP_FIELD_FLAG_RW, 95, 32, 0x0, 0x0 },
+	{ "prefix2_mask", DPP_FIELD_FLAG_RW, 63, 32, 0x0, 0x0 },
+	{ "prefix3_mask", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_lpm_mask1_reg[] = {
+	{ "vpn_id_mask", DPP_FIELD_FLAG_RW, 143, 16, 0x0, 0x0 },
+	{ "prefix0_mask", DPP_FIELD_FLAG_RW, 127, 32, 0x0, 0x0 },
+	{ "prefix1_mask", DPP_FIELD_FLAG_RW, 95, 32, 0x0, 0x0 },
+	{ "prefix2_mask", DPP_FIELD_FLAG_RW, 63, 32, 0x0, 0x0 },
+	{ "prefix3_mask", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_lpm_mask2_reg[] = {
+	{ "vpn_id_mask", DPP_FIELD_FLAG_RW, 143, 16, 0x0, 0x0 },
+	{ "prefix0_mask", DPP_FIELD_FLAG_RW, 127, 32, 0x0, 0x0 },
+	{ "prefix1_mask", DPP_FIELD_FLAG_RW, 95, 32, 0x0, 0x0 },
+	{ "prefix2_mask", DPP_FIELD_FLAG_RW, 63, 32, 0x0, 0x0 },
+	{ "prefix3_mask", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_lpm_mask3_reg[] = {
+	{ "vpn_id_mask", DPP_FIELD_FLAG_RW, 143, 16, 0x0, 0x0 },
+	{ "prefix0_mask", DPP_FIELD_FLAG_RW, 127, 32, 0x0, 0x0 },
+	{ "prefix1_mask", DPP_FIELD_FLAG_RW, 95, 32, 0x0, 0x0 },
+	{ "prefix2_mask", DPP_FIELD_FLAG_RW, 63, 32, 0x0, 0x0 },
+	{ "prefix3_mask", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_default_route0_reg[] = {
+	{ "vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0 },
+	{ "vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0 },
+	{ "vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_default_route1_reg[] = {
+	{ "vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0 },
+	{ "vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0 },
+	{ "vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_default_route2_reg[] = {
+	{ "vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0 },
+	{ "vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0 },
+	{ "vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_default_route3_reg[] = {
+	{ "vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0 },
+	{ "vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0 },
+	{ "vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_default_route4_reg[] = {
+	{ "vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0 },
+	{ "vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0 },
+	{ "vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_default_route5_reg[] = {
+	{ "vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0 },
+	{ "vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0 },
+	{ "vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_default_route6_reg[] = {
+	{ "vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0 },
+	{ "vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0 },
+	{ "vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_default_route7_reg[] = {
+	{ "vpn_id", DPP_FIELD_FLAG_RW, 39, 16, 0x0, 0x0 },
+	{ "vpn_dresult", DPP_FIELD_FLAG_RW, 23, 22, 0x0, 0x0 },
+	{ "vpn_flag", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "vpn_vld", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_hash_listtable_item0_reg[] = {
+	{ "hash_item", DPP_FIELD_FLAG_RW, 511, 512, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_hash_listtable_item1_reg[] = {
+	{ "hash_item", DPP_FIELD_FLAG_RW, 511, 512, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_hash_listtable_item2_reg[] = {
+	{ "hash_item", DPP_FIELD_FLAG_RW, 511, 512, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_hash_listtable_item3_reg[] = {
+	{ "hash_item", DPP_FIELD_FLAG_RW, 511, 512, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_ecc_err_status_reg[] = {
+	{ "sram3_ecc_err", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "sram2_ecc_err", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "sram1_ecc_err", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "sram0_ecc_err", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_lpm_v6_sram_cmp_reg[] = {
+	{ "sram_cmp_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_alg_zblock_lpm_v4_sram_cmp_reg[] = {
+	{ "sram_cmp_flag", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_parser_kschd_pful_cfg_reg[] = {
+	{ "kschd_pful_assert", DPP_FIELD_FLAG_RW, 11, 6, 0xc, 0x0 },
+	{ "kschd_pful_negate", DPP_FIELD_FLAG_RW, 5, 6, 0xc, 0x0 },
+};
+DPP_FIELD_T g_se_parser_debug_cnt_mode_reg[] = {
+	{ "cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_parser_parser_int_en_reg[] = {
+	{ "parser_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_parser_parser_int_mask_reg[] = {
+	{ "parser_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_parser_parser_int_status_reg[] = {
+	{ "parser_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_parser_parser_int_unmask_flag_reg[] = {
+	{ "parser_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_parser_ecc_bypass_read_reg[] = {
+	{ "ecc_bypass_read", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0 },
+};
+DPP_FIELD_T g_se_parser_mex0_5_req_cnt_reg[] = {
+	{ "mex0_5_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_parser_kschd_req0_5_cnt_reg[] = {
+	{ "kschd_req0_5_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_parser_kschd_parser_fc0_5_cnt_reg[] = {
+	{ "kschd_parser_fc0_5_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_parser_se_ppu_mex0_5_fc_cnt_reg[] = {
+	{ "se_ppu_mex0_5_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_parser_smmu0_marc_fc_cnt_reg[] = {
+	{ "smmu0_marc_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_parser_smmu0_marc_key_cnt_reg[] = {
+	{ "smmu0_marc_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_parser_cmmu_key_cnt_reg[] = {
+	{ "cmmu_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_parser_cmmu_parser_fc_cnt_reg[] = {
+	{ "cmmu_parser_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_parser_marc_tab_type_err_mex0_5_cnt_reg[] = {
+	{ "marc_tab_type_err_mex0_5_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_parser_eram_fulladdr_drop_cnt_reg[] = {
+	{ "eram_fulladdr_drop_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_hash0_pful_cfg_reg[] = {
+	{ "hash0_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7d9f6, 0x0 },
+};
+DPP_FIELD_T g_se_as_hash1_pful_cfg_reg[] = {
+	{ "hash1_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7d9f6, 0x0 },
+};
+DPP_FIELD_T g_se_as_hash2_pful_cfg_reg[] = {
+	{ "hash2_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7d9f6, 0x0 },
+};
+DPP_FIELD_T g_se_as_hash3_pful_cfg_reg[] = {
+	{ "hash3_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7d9f6, 0x0 },
+};
+DPP_FIELD_T g_se_as_pbu_pful_cfg_reg[] = {
+	{ "pbu_pful_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x69a, 0x0 },
+};
+DPP_FIELD_T g_se_as_lpm_pful_cfg_reg[] = {
+	{ "lpm_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7d9f6, 0x0 },
+};
+DPP_FIELD_T g_se_as_etcam_pful_cfg_reg[] = {
+	{ "etcam_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1c38, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_learn0_fifo_cfg_reg[] = {
+	{ "as_learn1_pful_negate", DPP_FIELD_FLAG_RW, 27, 7, 0x38, 0x0 },
+	{ "as_learn1_pful_asert", DPP_FIELD_FLAG_RW, 20, 7, 0x38, 0x0 },
+	{ "as_learn0_pful_negate", DPP_FIELD_FLAG_RW, 13, 7, 0x38, 0x0 },
+	{ "as_learn0_pful_asert", DPP_FIELD_FLAG_RW, 6, 7, 0x38, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_learn1_fifo_cfg_reg[] = {
+	{ "as_learn3_pful_negate", DPP_FIELD_FLAG_RW, 27, 7, 0x38, 0x0 },
+	{ "as_learn3_pful_asert", DPP_FIELD_FLAG_RW, 20, 7, 0x38, 0x0 },
+	{ "as_learn2_pful_negate", DPP_FIELD_FLAG_RW, 13, 7, 0x38, 0x0 },
+	{ "as_learn2_pful_asert", DPP_FIELD_FLAG_RW, 6, 7, 0x38, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_dma_fifo_cfg_reg[] = {
+	{ "as_dma_fifo_cfg", DPP_FIELD_FLAG_RW, 15, 16, 0x7272, 0x0 },
+};
+DPP_FIELD_T g_se_as_age_pful_cfg_reg[] = {
+	{ "age_pful_cfg", DPP_FIELD_FLAG_RW, 11, 12, 0x618, 0x0 },
+};
+DPP_FIELD_T g_se_as_etcam_rsp_cfg_reg[] = {
+	{ "eram_rsp_pful_negate", DPP_FIELD_FLAG_RW, 27, 7, 0x24, 0x0 },
+	{ "eram_rsp_pful_assert", DPP_FIELD_FLAG_RW, 20, 7, 0x24, 0x0 },
+	{ "etcam_rsp_pful_negate", DPP_FIELD_FLAG_RW, 13, 7, 0x21, 0x0 },
+	{ "etcam_rsp_pful_assert", DPP_FIELD_FLAG_RW, 6, 7, 0x21, 0x0 },
+};
+DPP_FIELD_T g_se_as_pbu_ecc_bypass_read_reg[] = {
+	{ "pbu_ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_as_etcam0_ecc_bypass_read_reg[] = {
+	{ "etcam0_ecc_bypass_read", DPP_FIELD_FLAG_RW, 2, 3, 0x7, 0x0 },
+};
+DPP_FIELD_T g_se_as_etcam1_ecc_bypass_read_reg[] = {
+	{ "etcam1_ecc_bypass_read", DPP_FIELD_FLAG_RW, 2, 3, 0x7, 0x0 },
+};
+DPP_FIELD_T g_se_as_lpm_ecc_bypass_read_reg[] = {
+	{ "lpm_ecc_bypass_read", DPP_FIELD_FLAG_RW, 1, 2, 0x3, 0x0 },
+};
+DPP_FIELD_T g_se_as_hash_ecc_bypass_read_reg[] = {
+	{ "hash3_ecc_bypass_read", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "hash2_ecc_bypass_read", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "hash1_ecc_bypass_read", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "hash0_ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_as_hash_learn_ecc_bypass_read_reg[] = {
+	{ "hash_learn_ecc_bypass_read", DPP_FIELD_FLAG_RW, 3, 4, 0xf, 0x0 },
+};
+DPP_FIELD_T g_se_as_debug_cnt_mode_reg[] = {
+	{ "cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_int_0_en_reg[] = {
+	{ "as_int_0_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_int_0_mask_reg[] = {
+	{ "as_int_0_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_int_1_en_reg[] = {
+	{ "as_int_1_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_int_1_mask_reg[] = {
+	{ "as_int_1_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_int_2_en_reg[] = {
+	{ "as_int_2_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_int_2_mask_reg[] = {
+	{ "as_int_2_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_int_0_status_reg[] = {
+	{ "port0_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_int_1_status_reg[] = {
+	{ "port1_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_int_2_status_reg[] = {
+	{ "port2_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_se_as_int_status_reg[] = {
+	{ "as_int_2_unmask_flag", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "as_int_1_unmask_flag", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "as_int_0_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_hash0_3_wr_req_cnt_reg[] = {
+	{ "hash0_3_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_smmu0_etcam0_1_fc_cnt_reg[] = {
+	{ "smmu0_etcam0_1_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_etcam0_1_smmu0_req_cnt_reg[] = {
+	{ "etcam0_1_smmu0_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_smmu0_etcam0_1_rsp_cnt_reg[] = {
+	{ "smmu0_etcam0_1_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_hla_hash_p0_3_key_cnt_reg[] = {
+	{ "as_hla_hash_p0_3_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_hla_lpm_p0_key_cnt_reg[] = {
+	{ "as_hla_lpm_p0_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_alg_as_hash_p0_3_rsp_cnt_reg[] = {
+	{ "alg_as_hash_p0_3_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_alg_as_hash_p0_3_smf_rsp_cnt_reg[] = {
+	{ "alg_as_hash_p0_3_smf_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_alg_as_lpm_p0_rsp_cnt_reg[] = {
+	{ "alg_as_lpm_p0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_alg_as_lpm_p0_3_smf_rsp_cnt_reg[] = {
+	{ "alg_as_lpm_p0_3_smf_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_pbu_key_cnt_reg[] = {
+	{ "as_pbu_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_pbu_se_dpi_rsp_dat_cnt_reg[] = {
+	{ "pbu_se_dpi_rsp_dat_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_etcam_ctrl_req0_cnt_reg[] = {
+	{ "as_etcam_ctrl_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_etcam_ctrl_as_index0_1_cnt_reg[] = {
+	{ "etcam_ctrl_as_index0_1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_etcam_ctrl_as_hit0_1_cnt_reg[] = {
+	{ "etcam_ctrl_as_hit0_1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_smmu0_req_cnt_reg[] = {
+	{ "as_smmu0_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_learn_hla_wr_cnt_reg[] = {
+	{ "learn_hla_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_smmu1_req_cnt_reg[] = {
+	{ "as_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_se_cfg_mac_dat_cnt_reg[] = {
+	{ "se_cfg_mac_dat_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_alg_as_hash_p0_3_fc_cnt_reg[] = {
+	{ "alg_as_hash_p0_3_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_alg_as_lpm_p0_fc_cnt_reg[] = {
+	{ "alg_as_lpm_p0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_alg_hash_p0_3_fc_cnt_reg[] = {
+	{ "as_alg_hash_p0_3_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_alg_lpm_p0_fc_cnt_reg[] = {
+	{ "as_alg_lpm_p0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_pbu_fc_cnt_reg[] = {
+	{ "as_pbu_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_pbu_se_dpi_key_fc_cnt_reg[] = {
+	{ "pbu_se_dpi_key_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_as_etcam_ctrl_fc0_1_cnt_reg[] = {
+	{ "as_etcam_ctrl_fc0_1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_etcam_ctrl_as_fc0_1_cnt_reg[] = {
+	{ "etcam_ctrl_as_fc0_1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_smmu0_as_mac_age_fc_cnt_reg[] = {
+	{ "smmu0_as_mac_age_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_alg_learn_fc_cnt_reg[] = {
+	{ "alg_learn_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_smmu1_as_fc_cnt_reg[] = {
+	{ "smmu1_as_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_as_cfg_se_mac_fc_cnt_reg[] = {
+	{ "cfg_se_mac_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_kschd_cpu_rdy_reg[] = {
+	{ "kschd_cpu_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_ppu0_ecc_bypass_read_reg[] = {
+	{ "ppu0_ecc_bypass_read", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_pbu_ecc_bypass_read_reg[] = {
+	{ "pbu_ecc_bypass_read", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_smmu1_ecc_bypass_read_reg[] = {
+	{ "u3_smmu1_ecc_bypass_read", DPP_FIELD_FLAG_RO, 23, 6, 0x3f, 0x0 },
+	{ "u2_smmu1_ecc_bypass_read", DPP_FIELD_FLAG_RO, 17, 6, 0x3f, 0x0 },
+	{ "u1_smmu1_ecc_bypass_read", DPP_FIELD_FLAG_RO, 11, 6, 0x3f, 0x0 },
+	{ "u0_smmu1_ecc_bypass_read", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_ass_ecc_bypass_read_reg[] = {
+	{ "ass_ecc_bypass_read", DPP_FIELD_FLAG_RW, 5, 6, 0x3f, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_sdt_h_reg[] = {
+	{ "sdt_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_sdt_l_reg[] = {
+	{ "sdt_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_hash_key15_reg[] = {
+	{ "dma_en", DPP_FIELD_FLAG_RW, 25, 1, 0x0, 0x0 },
+	{ "delete_en", DPP_FIELD_FLAG_RW, 24, 1, 0x0, 0x0 },
+	{ "hash_key15", DPP_FIELD_FLAG_RW, 23, 24, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_hash_key14_reg[] = {
+	{ "hash_key14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_hash_key13_reg[] = {
+	{ "hash_key13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_hash_key12_reg[] = {
+	{ "hash_key12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_hash_key11_reg[] = {
+	{ "hash_key11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_hash_key10_reg[] = {
+	{ "hash_key10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_hash_key9_reg[] = {
+	{ "hash_key9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_hash_key8_reg[] = {
+	{ "hash_key8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_hash_key7_reg[] = {
+	{ "hash_key7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_hash_key6_reg[] = {
+	{ "hash_key6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_hash_key5_reg[] = {
+	{ "hash_key5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_hash_key4_reg[] = {
+	{ "hash_key4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_hash_key3_reg[] = {
+	{ "hash_key3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_hash_key2_reg[] = {
+	{ "hash_key2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_hash_key1_reg[] = {
+	{ "hash_key1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_hash_key0_reg[] = {
+	{ "hash_key0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_schd_int_0_en_reg[] = {
+	{ "port0_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_schd_int_0_mask_reg[] = {
+	{ "port0_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_schd_int_1_en_reg[] = {
+	{ "port1_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_schd_int_1_mask_reg[] = {
+	{ "port1_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_schd_int_2_en_reg[] = {
+	{ "port2_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_schd_int_2_mask_reg[] = {
+	{ "port2_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_schd_int_3_en_reg[] = {
+	{ "port3_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_schd_int_3_mask_reg[] = {
+	{ "port3_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_schd_int_4_en_reg[] = {
+	{ "port4_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_schd_int_4_mask_reg[] = {
+	{ "port4_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_schd_int_0_status_reg[] = {
+	{ "port0_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_schd_int_1_status_reg[] = {
+	{ "port1_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_schd_int_2_status_reg[] = {
+	{ "port2_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_schd_int_3_status_reg[] = {
+	{ "port3_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_schd_int_4_status_reg[] = {
+	{ "port4_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_se_kschd_int_status_reg[] = {
+	{ "schd_int4_unmask_flag", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "schd_int3_unmask_flag", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "schd_int2_unmask_flag", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "schd_int1_unmask_flag", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "schd_int0_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_debug_cnt_mode_reg[] = {
+	{ "cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_se_parser_kschd_key0_3_cnt_reg[] = {
+	{ "se_parser_kschd_key0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_se_smmu1_key0_3_cnt_reg[] = {
+	{ "se_smmu1_key0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_kschd_as_key0_cnt_reg[] = {
+	{ "kschd_as_key0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_kschd_as_key1_cnt_reg[] = {
+	{ "kschd_as_key1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_kschd_as_key2_cnt_reg[] = {
+	{ "kschd_as_key2_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_kschd_as_key3_cnt_reg[] = {
+	{ "kschd_as_key3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_kschd_as_key4_cnt_reg[] = {
+	{ "kschd_as_key4_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_kschd_as_key5_cnt_reg[] = {
+	{ "kschd_as_key5_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_kschd_as_key6_cnt_reg[] = {
+	{ "kschd_as_key6_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_kschd_as_key9_cnt_reg[] = {
+	{ "kschd_as_key9_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_kschd_se_parser_fc0_3_cnt_reg[] = {
+	{ "kschd_se_parser_fc0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_smmu1_se_fc0_3_cnt_reg[] = {
+	{ "smmu1_se_fc0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt0_reg[] = {
+	{ "as_kschd_fc_cnt0", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt1_reg[] = {
+	{ "as_kschd_fc_cnt1", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt2_reg[] = {
+	{ "as_kschd_fc_cnt2", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt3_reg[] = {
+	{ "as_kschd_fc_cnt3", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt4_reg[] = {
+	{ "as_kschd_fc_cnt4", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt5_reg[] = {
+	{ "as_kschd_fc_cnt5", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt6_reg[] = {
+	{ "as_kschd_fc_cnt6", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_kschd_as_kschd_fc_cnt9_reg[] = {
+	{ "as_kschd_fc_cnt9", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_hash_pful_cfg_reg[] = {
+	{ "rschd_hash_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00370037, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_hash_ept_cfg_reg[] = {
+	{ "rschd_hash_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00090009, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_pbu_pful_cfg_reg[] = {
+	{ "rschd_pbu_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x002d002d, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_pbu_ept_cfg_reg[] = {
+	{ "rschd_pbu_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00130013, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_lpm_pful_cfg_reg[] = {
+	{ "rschd_lpm_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00240024, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_lpm_ept_cfg_reg[] = {
+	{ "rschd_lpm_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x001c001c, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_etcam_pful_cfg_reg[] = {
+	{ "rschd_etcam_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00110011, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_etcam_ept_cfg_reg[] = {
+	{ "rschd_etcam_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x002f002f, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_smmu0_wb_pful_cfg_reg[] = {
+	{ "smmu0_wb_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00330033, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_smmu0_wb_ept_cfg_reg[] = {
+	{ "smmu0_wb_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x000d000d, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_smmu1_wb_pful_cfg_reg[] = {
+	{ "smmu1_wb_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x003a003a, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_smmu1_wb_ept_cfg_reg[] = {
+	{ "smmu1_wb_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00060006, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_alg_wb_pful_cfg_reg[] = {
+	{ "alg_wb_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x003a003a, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_alg_wb_ept_cfg_reg[] = {
+	{ "alg_wb_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00060006, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_wr_rsp_vld_en_reg[] = {
+	{ "wr_rsp_vld_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_nppu_wb_pful_cfg_reg[] = {
+	{ "nppu_wb_pful_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00380038, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_nppu_wb_ept_cfg_reg[] = {
+	{ "nppu_wb_ept_cfg", DPP_FIELD_FLAG_RW, 31, 32, 0x00080008, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_port0_int_en_reg[] = {
+	{ "port0_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_port0_int_mask_reg[] = {
+	{ "port0_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_port1_int_en_reg[] = {
+	{ "port1_int_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_port1_int_mask_reg[] = {
+	{ "port1_int_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_port0_int_status_reg[] = {
+	{ "port0_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_port1_int_status_reg[] = {
+	{ "port1_int_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_se_rschd_int_status_reg[] = {
+	{ "port1_int_unmask_flag", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "port0_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_debug_cnt_mode_reg[] = {
+	{ "cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_se_ppu_mex0_5_rsp1_cnt_reg[] = {
+	{ "se_ppu_mex0_5_rsp1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_as_rschd_rsp0_cnt_reg[] = {
+	{ "as_rschd_rsp0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_as_rschd_rsp1_cnt_reg[] = {
+	{ "as_rschd_rsp1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_as_rschd_rsp2_cnt_reg[] = {
+	{ "as_rschd_rsp2_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_as_rschd_rsp3_cnt_reg[] = {
+	{ "as_rschd_rsp3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_as_rschd_rsp4_cnt_reg[] = {
+	{ "as_rschd_rsp4_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_as_rschd_rsp5_cnt_reg[] = {
+	{ "as_rschd_rsp5_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_as_rschd_rsp6_cnt_reg[] = {
+	{ "as_rschd_rsp6_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_as_rschd_rsp9_cnt_reg[] = {
+	{ "as_rschd_rsp9_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_smmu1_se_rsp0_3_cnt_reg[] = {
+	{ "smmu1_se_rsp0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_ppu_se_mex0_3_fc_cnt_reg[] = {
+	{ "ppu_se_mex0_3_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt0_reg[] = {
+	{ "rschd_as_fc_cnt0", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt1_reg[] = {
+	{ "rschd_as_fc_cnt1", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt2_reg[] = {
+	{ "rschd_as_fc_cnt2", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt3_reg[] = {
+	{ "rschd_as_fc_cnt3", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt4_reg[] = {
+	{ "rschd_as_fc_cnt4", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt5_reg[] = {
+	{ "rschd_as_fc_cnt5", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt6_reg[] = {
+	{ "rschd_as_fc_cnt6", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_rschd_as_fc_cnt9_reg[] = {
+	{ "rschd_as_fc_cnt9", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_se_smmu1_fc0_3_cnt_reg[] = {
+	{ "se_smmu1_fc0_3_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_smmu0_se_wr_done_cnt_reg[] = {
+	{ "smmu0_se_wr_done_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_se_smmu0_wr_done_fc_cnt_reg[] = {
+	{ "se_smmu0_wr_done_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_smmu1_se_wr_rsp_cnt_reg[] = {
+	{ "smmu1_se_wr_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_se_smmu1_wr_rsp_fc_cnt_reg[] = {
+	{ "se_smmu1_wr_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_alg_se_wr_rsp_cnt_reg[] = {
+	{ "alg_se_wr_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_rschd_se_alg_wr_rsp_fc_cnt_reg[] = {
+	{ "se_alg_wr_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_pful_cfg0_reg[] = {
+	{ "kschd_pful_assert0_1", DPP_FIELD_FLAG_RW, 27, 7, 0x18, 0x0 },
+	{ "kschd_pful_negate0_1", DPP_FIELD_FLAG_RW, 20, 7, 0x18, 0x0 },
+	{ "kschd_pful_assert0_0", DPP_FIELD_FLAG_RW, 13, 7, 0x20, 0x0 },
+	{ "kschd_pful_negate0_0", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_pful_cfg1_reg[] = {
+	{ "kschd_pful_assert1_1", DPP_FIELD_FLAG_RW, 25, 7, 0x20, 0x0 },
+	{ "kschd_pful_negate1_1", DPP_FIELD_FLAG_RW, 18, 7, 0x20, 0x0 },
+	{ "kschd_pful_assert1_0", DPP_FIELD_FLAG_RW, 11, 6, 0x0c, 0x0 },
+	{ "kschd_pful_negate1_0", DPP_FIELD_FLAG_RW, 5, 6, 0x0c, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl_pful1_cfg_reg[] = {
+	{ "ctrl_pful1_assert", DPP_FIELD_FLAG_RW, 7, 4, 0x3, 0x0 },
+	{ "ctrl_pful1_negate", DPP_FIELD_FLAG_RW, 3, 4, 0x2, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl_pful2_cfg_reg[] = {
+	{ "ctrl_pful2_assert", DPP_FIELD_FLAG_RW, 9, 5, 0x0a, 0x0 },
+	{ "ctrl_pful2_negate", DPP_FIELD_FLAG_RW, 4, 5, 0x08, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl_pful3_cfg_reg[] = {
+	{ "ctrl_pful3_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x38, 0x0 },
+	{ "ctrl_pful3_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x36, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_pful_cfg_reg[] = {
+	{ "rschd_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x24, 0x0 },
+	{ "rschd_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_ept_cfg_reg[] = {
+	{ "rschd_ept_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x1c, 0x0 },
+	{ "rschd_ept_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x1c, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_alucmd_pful_cfg_reg[] = {
+	{ "alucmd_pful_assert", DPP_FIELD_FLAG_RW, 11, 6, 0x18, 0x0 },
+	{ "alucmd_pful_negate", DPP_FIELD_FLAG_RW, 5, 6, 0x16, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_aluwr_pful_cfg_reg[] = {
+	{ "aluwr_pful_assert", DPP_FIELD_FLAG_RW, 7, 4, 0x5, 0x0 },
+	{ "aluwr_pful_negate", DPP_FIELD_FLAG_RW, 3, 4, 0x4, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_wr_arb_pful_cfg0_reg[] = {
+	{ "wr_arb_pful0_assert", DPP_FIELD_FLAG_RW, 11, 6, 0x15, 0x0 },
+	{ "wr_arb_pful0_negate", DPP_FIELD_FLAG_RW, 5, 6, 0x15, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_wr_arb_pful_cfg1_reg[] = {
+	{ "wr_arb_pful1_assert", DPP_FIELD_FLAG_RW, 15, 8, 0x64, 0x0 },
+	{ "wr_arb_pful1_negate", DPP_FIELD_FLAG_RW, 7, 8, 0x64, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ord_pful_cfg_reg[] = {
+	{ "ord_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x2a, 0x0 },
+	{ "ord_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x2a, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cfg_dma_baddr_reg[] = {
+	{ "cfg_dma_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cfg_odma0_baddr_reg[] = {
+	{ "cfg_odma0_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cfg_odma1_baddr_reg[] = {
+	{ "cfg_odma1_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cfg_odma2_baddr_reg[] = {
+	{ "cfg_odma2_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cfg_odma_tdm_baddr_reg[] = {
+	{ "cfg_odma_tdm_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cfg_mcast_baddr_reg[] = {
+	{ "cfg_mcast_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cfg_lpm0_reg[] = {
+	{ "lpm0_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0 },
+	{ "lpm0_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cfg_lpm1_reg[] = {
+	{ "lpm1_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0 },
+	{ "lpm1_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cfg_lpm2_reg[] = {
+	{ "lpm2_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0 },
+	{ "lpm2_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cfg_lpm3_reg[] = {
+	{ "lpm3_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0 },
+	{ "lpm3_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cfg_lpm4_reg[] = {
+	{ "lpm4_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0 },
+	{ "lpm4_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cfg_lpm5_reg[] = {
+	{ "lpm5_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0 },
+	{ "lpm5_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cfg_lpm6_reg[] = {
+	{ "lpm6_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0 },
+	{ "lpm6_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cfg_lpm7_reg[] = {
+	{ "lpm7_rsp_mode", DPP_FIELD_FLAG_RW, 21, 3, 0x0, 0x0 },
+	{ "lpm7_baddr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_debug_cnt_mode_reg[] = {
+	{ "cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_stat_overflow_mode_reg[] = {
+	{ "stat_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_init_en_cfg_tmp_reg[] = {
+	{ "init_en_cfg_tmp31", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp30", DPP_FIELD_FLAG_RW, 30, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp29", DPP_FIELD_FLAG_RW, 29, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp28", DPP_FIELD_FLAG_RW, 28, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp27", DPP_FIELD_FLAG_RW, 27, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp26", DPP_FIELD_FLAG_RW, 26, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp25", DPP_FIELD_FLAG_RW, 25, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp24", DPP_FIELD_FLAG_RW, 24, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp23", DPP_FIELD_FLAG_RW, 23, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp22", DPP_FIELD_FLAG_RW, 22, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp21", DPP_FIELD_FLAG_RW, 21, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp20", DPP_FIELD_FLAG_RW, 20, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp19", DPP_FIELD_FLAG_RW, 19, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp18", DPP_FIELD_FLAG_RW, 18, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp17", DPP_FIELD_FLAG_RW, 17, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp16", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp15", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp14", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp13", DPP_FIELD_FLAG_RW, 13, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp12", DPP_FIELD_FLAG_RW, 12, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp11", DPP_FIELD_FLAG_RW, 11, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp10", DPP_FIELD_FLAG_RW, 10, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp9", DPP_FIELD_FLAG_RW, 9, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp8", DPP_FIELD_FLAG_RW, 8, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp7", DPP_FIELD_FLAG_RW, 7, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp6", DPP_FIELD_FLAG_RW, 6, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp5", DPP_FIELD_FLAG_RW, 5, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp4", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp3", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp2", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp1", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "init_en_cfg_tmp0", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int_unmask_flag_reg[] = {
+	{ "smmu0_int0_31_unmask_flag", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int0_en_reg[] = {
+	{ "smmu0_int0_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int0_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int0_mask_reg[] = {
+	{ "smmu0_int0_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int0_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int0_status_reg[] = {
+	{ "smmu0_int0_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int0_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int1_en_reg[] = {
+	{ "smmu0_int1_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int1_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int1_mask_reg[] = {
+	{ "smmu0_int1_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int1_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int1_status_reg[] = {
+	{ "smmu0_int1_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int1_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int2_en_reg[] = {
+	{ "smmu0_int2_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int2_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int2_mask_reg[] = {
+	{ "smmu0_int2_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int2_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int2_status_reg[] = {
+	{ "smmu0_int2_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int2_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int3_en_reg[] = {
+	{ "smmu0_int3_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int3_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int3_mask_reg[] = {
+	{ "smmu0_int3_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int3_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int3_status_reg[] = {
+	{ "smmu0_int3_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int3_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int4_en_reg[] = {
+	{ "smmu0_int4_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int4_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int4_mask_reg[] = {
+	{ "smmu0_int4_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int4_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int4_status_reg[] = {
+	{ "smmu0_int4_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int4_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int5_en_reg[] = {
+	{ "smmu0_int5_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int5_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int5_mask_reg[] = {
+	{ "smmu0_int5_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int5_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int5_status_reg[] = {
+	{ "smmu0_int5_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int5_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int6_en_reg[] = {
+	{ "smmu0_int6_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int6_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int6_mask_reg[] = {
+	{ "smmu0_int6_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int6_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int6_status_reg[] = {
+	{ "smmu0_int6_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int6_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int7_en_reg[] = {
+	{ "smmu0_int7_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int7_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int7_mask_reg[] = {
+	{ "smmu0_int7_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int7_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int7_status_reg[] = {
+	{ "smmu0_int7_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int7_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int8_en_reg[] = {
+	{ "smmu0_int8_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int8_mask_reg[] = {
+	{ "smmu0_int8_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int8_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int8_status_reg[] = {
+	{ "smmu0_int8_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int8_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int9_en_reg[] = {
+	{ "smmu0_int8_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int8_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int9_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int9_mask_reg[] = {
+	{ "smmu0_int9_mask0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int9_status_reg[] = {
+	{ "smmu0_int9_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int10_en_reg[] = {
+	{ "smmu0_int10_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int10_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int10_mask_reg[] = {
+	{ "smmu0_int10_mask0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int10_status_reg[] = {
+	{ "smmu0_int10_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int11_en_reg[] = {
+	{ "smmu0_int11_en0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int11_mask_reg[] = {
+	{ "smmu0_int11_mask0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int11_status_reg[] = {
+	{ "smmu0_int11_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int12_en_reg[] = {
+	{ "smmu0_int12_en0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int12_mask_reg[] = {
+	{ "smmu0_int12_mask0_31", DPP_FIELD_FLAG_RW, 31, 32, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int12_status_reg[] = {
+	{ "smmu0_int12_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int13_en_reg[] = {
+	{ "smmu0_int13_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int13_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int13_mask_reg[] = {
+	{ "smmu0_int13_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int13_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int13_status_reg[] = {
+	{ "smmu0_int13_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int13_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int14_en_reg[] = {
+	{ "smmu0_int14_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int14_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int14_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int14_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int14_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int14_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int14_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int14_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int14_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int14_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int14_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int14_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int14_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int14_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int14_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int14_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int14_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int14_mask_reg[] = {
+	{ "smmu0_int14_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int14_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int14_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int14_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int14_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int14_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int14_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int14_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int14_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int14_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int14_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int14_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int14_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int14_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int14_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int14_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int14_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int14_status_reg[] = {
+	{ "smmu0_int14_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int14_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int14_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int14_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int14_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int14_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int14_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int14_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int14_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int14_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int14_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int14_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int14_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int14_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int14_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int14_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int14_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_ecc_unmask_flag_reg[] = {
+	{ "smmu0_int53_unmask_flag", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int52_unmask_flag", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int51_unmask_flag", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int50_unmask_flag", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int49_unmask_flag", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int48_unmask_flag", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int47_unmask_flag", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int46_unmask_flag", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int45_unmask_flag", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int44_unmask_flag", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int43_unmask_flag", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int42_unmask_flag", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int41_unmask_flag", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int40_unmask_flag", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int39_unmask_flag", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int38_unmask_flag", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int37_unmask_flag", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int36_unmask_flag", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int35_unmask_flag", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int34_unmask_flag", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int33_unmask_flag", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int32_unmask_flag", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int15_en_reg[] = {
+	{ "smmu0_int15_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int15_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int15_mask_reg[] = {
+	{ "smmu0_int15_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int15_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int15_status_reg[] = {
+	{ "smmu0_int15_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int15_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int16_en_reg[] = {
+	{ "smmu0_int16_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int16_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int16_mask_reg[] = {
+	{ "smmu0_int16_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int16_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int16_status_reg[] = {
+	{ "smmu0_int16_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int16_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int17_en_reg[] = {
+	{ "smmu0_int17_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int17_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int17_mask_reg[] = {
+	{ "smmu0_int17_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int17_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int17_status_reg[] = {
+	{ "smmu0_int17_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int17_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int18_en_reg[] = {
+	{ "smmu0_int18_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int18_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int18_mask_reg[] = {
+	{ "smmu0_int18_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int18_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int18_status_reg[] = {
+	{ "smmu0_int18_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int18_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int19_en_reg[] = {
+	{ "smmu0_int19_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int19_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int19_mask_reg[] = {
+	{ "smmu0_int19_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int19_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int19_status_reg[] = {
+	{ "smmu0_int19_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int19_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int20_en_reg[] = {
+	{ "smmu0_int20_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int20_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int20_mask_reg[] = {
+	{ "smmu0_int20_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int20_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int20_status_reg[] = {
+	{ "smmu0_int20_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int20_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int21_en_reg[] = {
+	{ "smmu0_int21_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int21_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int21_mask_reg[] = {
+	{ "smmu0_int21_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int21_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int21_status_reg[] = {
+	{ "smmu0_int21_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int21_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int22_en_reg[] = {
+	{ "smmu0_int22_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int22_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int22_mask_reg[] = {
+	{ "smmu0_int22_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int22_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int22_status_reg[] = {
+	{ "smmu0_int22_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int22_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int23_en_reg[] = {
+	{ "smmu0_int23_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int23_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int23_mask_reg[] = {
+	{ "smmu0_int23_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int23_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int23_status_reg[] = {
+	{ "smmu0_int23_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int23_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int24_en_reg[] = {
+	{ "smmu0_int24_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int24_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int24_mask_reg[] = {
+	{ "smmu0_int24_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int24_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int24_status_reg[] = {
+	{ "smmu0_int24_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int24_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int25_en_reg[] = {
+	{ "smmu0_int25_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int25_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int25_mask_reg[] = {
+	{ "smmu0_int25_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int25_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int25_status_reg[] = {
+	{ "smmu0_int25_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int25_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int26_en_reg[] = {
+	{ "smmu0_int26_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int26_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int26_mask_reg[] = {
+	{ "smmu0_int26_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int26_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int26_status_reg[] = {
+	{ "smmu0_int26_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int26_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int27_en_reg[] = {
+	{ "smmu0_int27_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int27_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int27_mask_reg[] = {
+	{ "smmu0_int27_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int27_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int27_status_reg[] = {
+	{ "smmu0_int27_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int27_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int28_en_reg[] = {
+	{ "smmu0_int28_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int28_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int28_mask_reg[] = {
+	{ "smmu0_int28_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int28_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int28_status_reg[] = {
+	{ "smmu0_int28_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int28_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int29_en_reg[] = {
+	{ "smmu0_int29_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int29_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int29_mask_reg[] = {
+	{ "smmu0_int29_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int29_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int29_status_reg[] = {
+	{ "smmu0_int29_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int29_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int30_en_reg[] = {
+	{ "smmu0_int30_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int30_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int30_mask_reg[] = {
+	{ "smmu0_int30_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int30_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int30_status_reg[] = {
+	{ "smmu0_int30_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int30_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int31_en_reg[] = {
+	{ "smmu0_int31_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int31_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int31_mask_reg[] = {
+	{ "smmu0_int31_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int31_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int31_status_reg[] = {
+	{ "smmu0_int31_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int31_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int32_en_reg[] = {
+	{ "smmu0_int32_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int32_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int32_mask_reg[] = {
+	{ "smmu0_int32_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int32_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int32_status_reg[] = {
+	{ "smmu0_int32_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int32_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int33_en_reg[] = {
+	{ "smmu0_int33_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int33_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int33_mask_reg[] = {
+	{ "smmu0_int33_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int33_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int33_status_reg[] = {
+	{ "smmu0_int33_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int33_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int34_en_reg[] = {
+	{ "smmu0_int34_en31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int34_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int34_mask_reg[] = {
+	{ "smmu0_int34_mask31", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask30", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask29", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask28", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask27", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask26", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask25", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask24", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask23", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask22", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask21", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask20", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask19", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask18", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask17", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask16", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int34_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int34_status_reg[] = {
+	{ "smmu0_int34_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int34_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int35_en_reg[] = {
+	{ "smmu0_int35_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int35_mask_reg[] = {
+	{ "smmu0_int35_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int35_status_reg[] = {
+	{ "smmu0_int35_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int36_en_reg[] = {
+	{ "smmu0_int36_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int36_mask_reg[] = {
+	{ "smmu0_int36_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int36_status_reg[] = {
+	{ "smmu0_int36_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int37_en_reg[] = {
+	{ "smmu0_int37_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int37_mask_reg[] = {
+	{ "smmu0_int37_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int37_status_reg[] = {
+	{ "smmu0_int37_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int38_en_reg[] = {
+	{ "smmu0_int38_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int38_mask_reg[] = {
+	{ "smmu0_int38_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int38_status_reg[] = {
+	{ "smmu0_int38_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int39_en_reg[] = {
+	{ "smmu0_int39_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int39_mask_reg[] = {
+	{ "smmu0_int39_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int39_status_reg[] = {
+	{ "smmu0_int39_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int40_en_reg[] = {
+	{ "smmu0_int40_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int40_mask_reg[] = {
+	{ "smmu0_int40_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int40_status_reg[] = {
+	{ "smmu0_int40_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int41_en_reg[] = {
+	{ "smmu0_int41_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int41_mask_reg[] = {
+	{ "smmu0_int41_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int41_status_reg[] = {
+	{ "smmu0_int41_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int42_en_reg[] = {
+	{ "smmu0_int42_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int42_mask_reg[] = {
+	{ "smmu0_int42_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int42_status_reg[] = {
+	{ "smmu0_int42_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int43_en_reg[] = {
+	{ "smmu0_int43_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int43_mask_reg[] = {
+	{ "smmu0_int43_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int43_status_reg[] = {
+	{ "smmu0_int43_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int44_en_reg[] = {
+	{ "smmu0_int44_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int44_mask_reg[] = {
+	{ "smmu0_int44_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int44_status_reg[] = {
+	{ "smmu0_int44_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int45_en_reg[] = {
+	{ "smmu0_int45_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int45_mask_reg[] = {
+	{ "smmu0_int45_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int45_status_reg[] = {
+	{ "smmu0_int45_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int46_en_reg[] = {
+	{ "smmu0_int46_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int46_mask_reg[] = {
+	{ "smmu0_int46_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int46_status_reg[] = {
+	{ "smmu0_int46_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int47_en_reg[] = {
+	{ "smmu0_int47_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int47_mask_reg[] = {
+	{ "smmu0_int47_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int47_status_reg[] = {
+	{ "smmu0_int47_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int48_en_reg[] = {
+	{ "smmu0_int48_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int48_mask_reg[] = {
+	{ "smmu0_int48_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int48_status_reg[] = {
+	{ "smmu0_int48_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int49_en_reg[] = {
+	{ "smmu0_int49_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int49_mask_reg[] = {
+	{ "smmu0_int49_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int49_status_reg[] = {
+	{ "smmu0_int49_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int50_en_reg[] = {
+	{ "smmu0_int50_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int50_mask_reg[] = {
+	{ "smmu0_int50_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int50_status_reg[] = {
+	{ "smmu0_int50_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int51_en_reg[] = {
+	{ "smmu0_int51_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int51_mask_reg[] = {
+	{ "smmu0_int51_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int51_status_reg[] = {
+	{ "smmu0_int51_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int52_en_reg[] = {
+	{ "smmu0_int52_en0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int52_mask_reg[] = {
+	{ "smmu0_int52_mask0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int52_status_reg[] = {
+	{ "smmu0_int52_status0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int53_en_reg[] = {
+	{ "smmu0_int53_en3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int53_en2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int53_en1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int53_en0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int53_mask_reg[] = {
+	{ "smmu0_int53_mask3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "smmu0_int53_mask2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "smmu0_int53_mask1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_int53_mask0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_int53_status_reg[] = {
+	{ "smmu0_int53_status15", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_int53_status14", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_int53_status13", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_int53_status12", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl0_arbiter_ecc_bypass_reg[] = {
+	{ "ctrl1_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "ctrl1_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "ctrl1_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "ctrl1_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "ctrl1_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "ctrl1_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "ctrl1_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "ctrl1_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "ctrl1_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "ctrl1_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "ctrl1_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "ctrl1_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "ctrl1_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "ctrl1_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "ctrl1_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "ctrl1_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "ctrl0_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "ctrl0_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "ctrl0_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "ctrl0_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "ctrl0_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "ctrl0_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "ctrl0_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "ctrl0_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "ctrl0_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "ctrl0_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "ctrl0_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "ctrl0_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "ctrl0_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "ctrl0_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "ctrl0_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "ctrl0_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl2_arbiter_ecc_bypass_reg[] = {
+	{ "ctrl3_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "ctrl3_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "ctrl3_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "ctrl3_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "ctrl3_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "ctrl3_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "ctrl3_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "ctrl3_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "ctrl3_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "ctrl3_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "ctrl3_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "ctrl3_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "ctrl3_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "ctrl3_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "ctrl3_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "ctrl3_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "ctrl2_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "ctrl2_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "ctrl2_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "ctrl2_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "ctrl2_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "ctrl2_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "ctrl2_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "ctrl2_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "ctrl2_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "ctrl2_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "ctrl2_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "ctrl2_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "ctrl2_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "ctrl2_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "ctrl2_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "ctrl2_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl4_arbiter_ecc_bypass_reg[] = {
+	{ "ctrl5_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "ctrl5_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "ctrl5_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "ctrl5_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "ctrl5_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "ctrl5_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "ctrl5_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "ctrl5_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "ctrl5_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "ctrl5_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "ctrl5_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "ctrl5_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "ctrl5_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "ctrl5_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "ctrl5_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "ctrl5_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "ctrl4_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "ctrl4_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "ctrl4_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "ctrl4_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "ctrl4_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "ctrl4_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "ctrl4_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "ctrl4_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "ctrl4_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "ctrl4_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "ctrl4_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "ctrl4_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "ctrl4_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "ctrl4_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "ctrl4_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "ctrl4_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl6_arbiter_ecc_bypass_reg[] = {
+	{ "ctrl7_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "ctrl7_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "ctrl7_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "ctrl7_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "ctrl7_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "ctrl7_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "ctrl7_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "ctrl7_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "ctrl7_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "ctrl7_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "ctrl7_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "ctrl7_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "ctrl7_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "ctrl7_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "ctrl7_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "ctrl7_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "ctrl6_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "ctrl6_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "ctrl6_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "ctrl6_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "ctrl6_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "ctrl6_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "ctrl6_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "ctrl6_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "ctrl6_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "ctrl6_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "ctrl6_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "ctrl6_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "ctrl6_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "ctrl6_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "ctrl6_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "ctrl6_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl8_arbiter_ecc_bypass_reg[] = {
+	{ "ctrl9_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "ctrl9_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "ctrl9_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "ctrl9_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "ctrl9_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "ctrl9_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "ctrl9_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "ctrl9_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "ctrl9_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "ctrl9_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "ctrl9_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "ctrl9_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "ctrl9_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "ctrl9_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "ctrl9_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "ctrl9_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "ctrl8_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "ctrl8_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "ctrl8_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "ctrl8_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "ctrl8_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "ctrl8_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "ctrl8_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "ctrl8_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "ctrl8_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "ctrl8_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "ctrl8_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "ctrl8_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "ctrl8_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "ctrl8_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "ctrl8_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "ctrl8_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl10_arbiter_ecc_bypass_reg[] = {
+	{ "ctrl11_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "ctrl11_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "ctrl11_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "ctrl11_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "ctrl11_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "ctrl11_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "ctrl11_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "ctrl11_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "ctrl11_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "ctrl11_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "ctrl11_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "ctrl11_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "ctrl11_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "ctrl11_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "ctrl11_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "ctrl11_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "ctrl10_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "ctrl10_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "ctrl10_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "ctrl10_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "ctrl10_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "ctrl10_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "ctrl10_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "ctrl10_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "ctrl10_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "ctrl10_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "ctrl10_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "ctrl10_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "ctrl10_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "ctrl10_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "ctrl10_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "ctrl10_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl12_arbiter_ecc_bypass_reg[] = {
+	{ "ctrl13_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "ctrl13_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "ctrl13_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "ctrl13_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "ctrl13_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "ctrl13_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "ctrl13_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "ctrl13_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "ctrl13_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "ctrl13_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "ctrl13_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "ctrl13_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "ctrl13_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "ctrl13_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "ctrl13_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "ctrl13_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "ctrl12_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "ctrl12_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "ctrl12_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "ctrl12_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "ctrl12_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "ctrl12_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "ctrl12_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "ctrl12_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "ctrl12_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "ctrl12_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "ctrl12_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "ctrl12_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "ctrl12_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "ctrl12_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "ctrl12_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "ctrl12_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl14_arbiter_ecc_bypass_reg[] = {
+	{ "ctrl15_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "ctrl15_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "ctrl15_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "ctrl15_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "ctrl15_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "ctrl15_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "ctrl15_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "ctrl15_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "ctrl15_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "ctrl15_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "ctrl15_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "ctrl15_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "ctrl15_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "ctrl15_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "ctrl15_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "ctrl15_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "ctrl14_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "ctrl14_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "ctrl14_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "ctrl14_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "ctrl14_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "ctrl14_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "ctrl14_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "ctrl14_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "ctrl14_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "ctrl14_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "ctrl14_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "ctrl14_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "ctrl14_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "ctrl14_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "ctrl14_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "ctrl14_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl16_arbiter_ecc_bypass_reg[] = {
+	{ "ctrl17_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "ctrl17_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "ctrl17_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "ctrl17_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "ctrl17_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "ctrl17_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "ctrl17_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "ctrl17_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "ctrl17_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "ctrl17_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "ctrl17_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "ctrl17_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "ctrl17_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "ctrl17_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "ctrl17_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "ctrl17_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "ctrl16_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "ctrl16_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "ctrl16_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "ctrl16_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "ctrl16_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "ctrl16_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "ctrl16_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "ctrl16_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "ctrl16_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "ctrl16_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "ctrl16_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "ctrl16_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "ctrl16_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "ctrl16_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "ctrl16_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "ctrl16_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl18_arbiter_ecc_bypass_reg[] = {
+	{ "ctrl19_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "ctrl19_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "ctrl19_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "ctrl19_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "ctrl19_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "ctrl19_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "ctrl19_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "ctrl19_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "ctrl19_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "ctrl19_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "ctrl19_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "ctrl19_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "ctrl19_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "ctrl19_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "ctrl19_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "ctrl19_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "ctrl18_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "ctrl18_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "ctrl18_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "ctrl18_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "ctrl18_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "ctrl18_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "ctrl18_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "ctrl18_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "ctrl18_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "ctrl18_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "ctrl18_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "ctrl18_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "ctrl18_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "ctrl18_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "ctrl18_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "ctrl18_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl20_arbiter_ecc_bypass_reg[] = {
+	{ "ctrl21_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "ctrl21_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "ctrl21_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "ctrl21_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "ctrl21_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "ctrl21_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "ctrl21_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "ctrl21_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "ctrl21_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "ctrl21_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "ctrl21_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "ctrl21_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "ctrl21_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "ctrl21_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "ctrl21_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "ctrl21_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "ctrl20_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "ctrl20_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "ctrl20_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "ctrl20_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "ctrl20_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "ctrl20_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "ctrl20_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "ctrl20_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "ctrl20_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "ctrl20_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "ctrl20_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "ctrl20_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "ctrl20_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "ctrl20_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "ctrl20_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "ctrl20_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl22_arbiter_ecc_bypass_reg[] = {
+	{ "ctrl23_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "ctrl23_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "ctrl23_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "ctrl23_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "ctrl23_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "ctrl23_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "ctrl23_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "ctrl23_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "ctrl23_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "ctrl23_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "ctrl23_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "ctrl23_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "ctrl23_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "ctrl23_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "ctrl23_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "ctrl23_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "ctrl22_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "ctrl22_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "ctrl22_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "ctrl22_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "ctrl22_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "ctrl22_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "ctrl22_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "ctrl22_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "ctrl22_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "ctrl22_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "ctrl22_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "ctrl22_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "ctrl22_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "ctrl22_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "ctrl22_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "ctrl22_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl24_arbiter_ecc_bypass_reg[] = {
+	{ "ctrl25_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "ctrl25_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "ctrl25_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "ctrl25_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "ctrl25_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "ctrl25_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "ctrl25_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "ctrl25_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "ctrl25_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "ctrl25_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "ctrl25_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "ctrl25_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "ctrl25_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "ctrl25_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "ctrl25_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "ctrl25_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "ctrl24_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "ctrl24_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "ctrl24_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "ctrl24_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "ctrl24_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "ctrl24_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "ctrl24_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "ctrl24_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "ctrl24_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "ctrl24_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "ctrl24_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "ctrl24_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "ctrl24_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "ctrl24_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "ctrl24_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "ctrl24_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl26_arbiter_ecc_bypass_reg[] = {
+	{ "ctrl27_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "ctrl27_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "ctrl27_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "ctrl27_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "ctrl27_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "ctrl27_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "ctrl27_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "ctrl27_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "ctrl27_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "ctrl27_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "ctrl27_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "ctrl27_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "ctrl27_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "ctrl27_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "ctrl27_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "ctrl27_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "ctrl26_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "ctrl26_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "ctrl26_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "ctrl26_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "ctrl26_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "ctrl26_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "ctrl26_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "ctrl26_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "ctrl26_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "ctrl26_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "ctrl26_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "ctrl26_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "ctrl26_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "ctrl26_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "ctrl26_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "ctrl26_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl28_arbiter_ecc_bypass_reg[] = {
+	{ "ctrl29_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "ctrl29_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "ctrl29_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "ctrl29_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "ctrl29_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "ctrl29_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "ctrl29_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "ctrl29_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "ctrl29_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "ctrl29_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "ctrl29_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "ctrl29_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "ctrl29_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "ctrl29_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "ctrl29_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "ctrl29_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "ctrl28_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "ctrl28_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "ctrl28_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "ctrl28_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "ctrl28_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "ctrl28_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "ctrl28_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "ctrl28_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "ctrl28_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "ctrl28_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "ctrl28_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "ctrl28_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "ctrl28_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "ctrl28_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "ctrl28_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "ctrl28_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl30_arbiter_ecc_bypass_reg[] = {
+	{ "ctrl31_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 31, 1, 0x1, 0x0 },
+	{ "ctrl31_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 30, 1, 0x1, 0x0 },
+	{ "ctrl31_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 29, 1, 0x1, 0x0 },
+	{ "ctrl31_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 28, 1, 0x1, 0x0 },
+	{ "ctrl31_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 27, 1, 0x1, 0x0 },
+	{ "ctrl31_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 26, 1, 0x1, 0x0 },
+	{ "ctrl31_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 25, 1, 0x1, 0x0 },
+	{ "ctrl31_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 24, 1, 0x1, 0x0 },
+	{ "ctrl31_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 23, 1, 0x1, 0x0 },
+	{ "ctrl31_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 22, 1, 0x1, 0x0 },
+	{ "ctrl31_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 21, 1, 0x1, 0x0 },
+	{ "ctrl31_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 20, 1, 0x1, 0x0 },
+	{ "ctrl31_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 19, 1, 0x1, 0x0 },
+	{ "ctrl31_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 18, 1, 0x1, 0x0 },
+	{ "ctrl31_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 17, 1, 0x1, 0x0 },
+	{ "ctrl31_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 16, 1, 0x1, 0x0 },
+	{ "ctrl30_arbiter_ecc_bypass_15", DPP_FIELD_FLAG_RC, 15, 1, 0x1, 0x0 },
+	{ "ctrl30_arbiter_ecc_bypass_14", DPP_FIELD_FLAG_RC, 14, 1, 0x1, 0x0 },
+	{ "ctrl30_arbiter_ecc_bypass_13", DPP_FIELD_FLAG_RC, 13, 1, 0x1, 0x0 },
+	{ "ctrl30_arbiter_ecc_bypass_12", DPP_FIELD_FLAG_RC, 12, 1, 0x1, 0x0 },
+	{ "ctrl30_arbiter_ecc_bypass_11", DPP_FIELD_FLAG_RC, 11, 1, 0x1, 0x0 },
+	{ "ctrl30_arbiter_ecc_bypass_10", DPP_FIELD_FLAG_RC, 10, 1, 0x1, 0x0 },
+	{ "ctrl30_arbiter_ecc_bypass_9", DPP_FIELD_FLAG_RC, 9, 1, 0x1, 0x0 },
+	{ "ctrl30_arbiter_ecc_bypass_8", DPP_FIELD_FLAG_RC, 8, 1, 0x1, 0x0 },
+	{ "ctrl30_arbiter_ecc_bypass_7", DPP_FIELD_FLAG_RC, 7, 1, 0x1, 0x0 },
+	{ "ctrl30_arbiter_ecc_bypass_6", DPP_FIELD_FLAG_RC, 6, 1, 0x1, 0x0 },
+	{ "ctrl30_arbiter_ecc_bypass_5", DPP_FIELD_FLAG_RC, 5, 1, 0x1, 0x0 },
+	{ "ctrl30_arbiter_ecc_bypass_4", DPP_FIELD_FLAG_RC, 4, 1, 0x1, 0x0 },
+	{ "ctrl30_arbiter_ecc_bypass_3", DPP_FIELD_FLAG_RC, 3, 1, 0x1, 0x0 },
+	{ "ctrl30_arbiter_ecc_bypass_2", DPP_FIELD_FLAG_RC, 2, 1, 0x1, 0x0 },
+	{ "ctrl30_arbiter_ecc_bypass_1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "ctrl30_arbiter_ecc_bypass_0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl_req_ecc_bypass_reg[] = {
+	{ "ctrl_req_ecc_bypass_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl_info_ecc_bypass_reg[] = {
+	{ "ctrl_info_ecc_bypass_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_rschd_ecc_bypass_reg[] = {
+	{ "smmu0_rschd_ecc_bypass_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0xffffffff,
+	  0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_wr_ecc_bypass_reg[] = {
+	{ "smmu0_wr_ecc_bypass1", DPP_FIELD_FLAG_RC, 1, 1, 0x1, 0x0 },
+	{ "smmu0_wr_ecc_bypass0", DPP_FIELD_FLAG_RC, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl0_arbiter_ecc_err_reg[] = {
+	{ "ctrl0_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl0_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl1_arbiter_ecc_err_reg[] = {
+	{ "ctrl1_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl1_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl2_arbiter_ecc_err_reg[] = {
+	{ "ctrl2_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl2_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl3_arbiter_ecc_err_reg[] = {
+	{ "ctrl3_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl3_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl4_arbiter_ecc_err_reg[] = {
+	{ "ctrl4_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl4_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl5_arbiter_ecc_err_reg[] = {
+	{ "ctrl5_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl5_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl6_arbiter_ecc_err_reg[] = {
+	{ "ctrl6_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl6_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl7_arbiter_ecc_err_reg[] = {
+	{ "ctrl7_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl7_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl8_arbiter_ecc_err_reg[] = {
+	{ "ctrl8_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl8_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl9_arbiter_ecc_err_reg[] = {
+	{ "ctrl9_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl9_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl10_arbiter_ecc_err_reg[] = {
+	{ "ctrl10_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl10_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl11_arbiter_ecc_err_reg[] = {
+	{ "ctrl11_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl11_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl12_arbiter_ecc_err_reg[] = {
+	{ "ctrl12_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl12_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl13_arbiter_ecc_err_reg[] = {
+	{ "ctrl13_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl13_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl14_arbiter_ecc_err_reg[] = {
+	{ "ctrl14_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl14_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl15_arbiter_ecc_err_reg[] = {
+	{ "ctrl15_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl15_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl16_arbiter_ecc_err_reg[] = {
+	{ "ctrl16_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl16_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl17_arbiter_ecc_err_reg[] = {
+	{ "ctrl17_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl17_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl18_arbiter_ecc_err_reg[] = {
+	{ "ctrl18_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl18_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl19_arbiter_ecc_err_reg[] = {
+	{ "ctrl19_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl19_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl20_arbiter_ecc_err_reg[] = {
+	{ "ctrl20_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl20_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl21_arbiter_ecc_err_reg[] = {
+	{ "ctrl21_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl21_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl22_arbiter_ecc_err_reg[] = {
+	{ "ctrl22_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl22_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl23_arbiter_ecc_err_reg[] = {
+	{ "ctrl23_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl23_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl24_arbiter_ecc_err_reg[] = {
+	{ "ctrl24_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl24_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl25_arbiter_ecc_err_reg[] = {
+	{ "ctrl25_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl25_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl26_arbiter_ecc_err_reg[] = {
+	{ "ctrl26_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl26_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl27_arbiter_ecc_err_reg[] = {
+	{ "ctrl27_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl27_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl28_arbiter_ecc_err_reg[] = {
+	{ "ctrl28_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl28_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl29_arbiter_ecc_err_reg[] = {
+	{ "ctrl29_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl29_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl30_arbiter_ecc_err_reg[] = {
+	{ "ctrl30_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl30_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl31_arbiter_ecc_err_reg[] = {
+	{ "ctrl31_arbiter_ecc_err_31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "ctrl31_arbiter_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl_req_ecc_single_err_reg[] = {
+	{ "ctrl_req_ecc_single_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl_req_ecc_double_err_reg[] = {
+	{ "ctrl_req_ecc_double_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl_info_ecc_single_err_reg[] = {
+	{ "ctrl_info_ecc_single_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl_info_ecc_double_err_reg[] = {
+	{ "ctrl_info_ecc_double_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_wr_ecc_err_reg[] = {
+	{ "smmu0_wr_ecc_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "smmu0_wr_ecc_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "smmu0_wr_ecc_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "smmu0_wr_ecc_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_rschd_ecc_single_err_reg[] = {
+	{ "smmu0_rschd_ecc_single_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_rschd_ecc_double_err_reg[] = {
+	{ "smmu0_rschd_ecc_double_err_0_31", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ord_fifo_empty_reg[] = {
+	{ "ord_fifo_empty", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_wr_arb_fifo_empty_reg[] = {
+	{ "wr_arb_fifo_empty", DPP_FIELD_FLAG_RO, 3, 4, 0xf, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty0_reg[] = {
+	{ "ctrl_fifo_empty0_5", DPP_FIELD_FLAG_RO, 29, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty0_4", DPP_FIELD_FLAG_RO, 24, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty0_3", DPP_FIELD_FLAG_RO, 19, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty0_2", DPP_FIELD_FLAG_RO, 14, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty0_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty0_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty1_reg[] = {
+	{ "ctrl_fifo_empty1_5", DPP_FIELD_FLAG_RO, 29, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty1_4", DPP_FIELD_FLAG_RO, 24, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty1_3", DPP_FIELD_FLAG_RO, 19, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty1_2", DPP_FIELD_FLAG_RO, 14, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty1_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty1_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty2_reg[] = {
+	{ "ctrl_fifo_empty2_5", DPP_FIELD_FLAG_RO, 29, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty2_4", DPP_FIELD_FLAG_RO, 24, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty2_3", DPP_FIELD_FLAG_RO, 19, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty2_2", DPP_FIELD_FLAG_RO, 14, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty2_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty2_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty3_reg[] = {
+	{ "ctrl_fifo_empty3_5", DPP_FIELD_FLAG_RO, 29, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty3_4", DPP_FIELD_FLAG_RO, 24, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty3_3", DPP_FIELD_FLAG_RO, 19, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty3_2", DPP_FIELD_FLAG_RO, 14, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty3_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty3_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty4_reg[] = {
+	{ "ctrl_fifo_empty4_5", DPP_FIELD_FLAG_RO, 29, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty4_4", DPP_FIELD_FLAG_RO, 24, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty4_3", DPP_FIELD_FLAG_RO, 19, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty4_2", DPP_FIELD_FLAG_RO, 14, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty4_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty4_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ctrl_fifo_empty5_reg[] = {
+	{ "ctrl_fifo_empty5_1", DPP_FIELD_FLAG_RO, 9, 5, 0x1f, 0x0 },
+	{ "ctrl_fifo_empty5_0", DPP_FIELD_FLAG_RO, 4, 5, 0x1f, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty0_reg[] = {
+	{ "kschd_fifo_empty0", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty1_reg[] = {
+	{ "kschd_fifo_empty1", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty2_reg[] = {
+	{ "kschd_fifo_empty2", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty3_reg[] = {
+	{ "kschd_fifo_empty3", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty4_reg[] = {
+	{ "kschd_fifo_empty4", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty5_reg[] = {
+	{ "kschd_fifo_empty5", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty6_reg[] = {
+	{ "kschd_fifo_empty6", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty7_reg[] = {
+	{ "kschd_fifo_empty7", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty8_reg[] = {
+	{ "kschd_fifo_empty8", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty9_reg[] = {
+	{ "kschd_fifo_empty9", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty10_reg[] = {
+	{ "kschd_fifo_empty10", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty11_reg[] = {
+	{ "kschd_fifo_empty11", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty12_reg[] = {
+	{ "kschd_fifo_empty12", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty13_reg[] = {
+	{ "kschd_fifo_empty13", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty14_reg[] = {
+	{ "kschd_fifo_empty14", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty15_reg[] = {
+	{ "kschd_fifo_empty15", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty16_reg[] = {
+	{ "kschd_fifo_empty16", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty17_reg[] = {
+	{ "kschd_fifo_empty17", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty18_reg[] = {
+	{ "kschd_fifo_empty18", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty19_reg[] = {
+	{ "kschd_fifo_empty19", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty20_reg[] = {
+	{ "kschd_fifo_empty20", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty21_reg[] = {
+	{ "kschd_fifo_empty21", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty22_reg[] = {
+	{ "kschd_fifo_empty22", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty23_reg[] = {
+	{ "kschd_fifo_empty23", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty24_reg[] = {
+	{ "kschd_fifo_empty24", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty25_reg[] = {
+	{ "kschd_fifo_empty25", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty26_reg[] = {
+	{ "kschd_fifo_empty26", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty27_reg[] = {
+	{ "kschd_fifo_empty27", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty28_reg[] = {
+	{ "kschd_fifo_empty28", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty29_reg[] = {
+	{ "kschd_fifo_empty29", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty30_reg[] = {
+	{ "kschd_fifo_empty30", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_kschd_fifo_empty31_reg[] = {
+	{ "kschd_fifo_empty31", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty0_reg[] = {
+	{ "rschd_fifo_empty0", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty1_reg[] = {
+	{ "rschd_fifo_empty1", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty2_reg[] = {
+	{ "rschd_fifo_empty2", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty3_reg[] = {
+	{ "rschd_fifo_empty3", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty4_reg[] = {
+	{ "rschd_fifo_empty4", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty5_reg[] = {
+	{ "rschd_fifo_empty5", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty6_reg[] = {
+	{ "rschd_fifo_empty6", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty7_reg[] = {
+	{ "rschd_fifo_empty7", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty8_reg[] = {
+	{ "rschd_fifo_empty8", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty9_reg[] = {
+	{ "rschd_fifo_empty9", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty10_reg[] = {
+	{ "rschd_fifo_empty10", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty11_reg[] = {
+	{ "rschd_fifo_empty11", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty12_reg[] = {
+	{ "rschd_fifo_empty12", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty13_reg[] = {
+	{ "rschd_fifo_empty13", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty14_reg[] = {
+	{ "rschd_fifo_empty14", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty15_reg[] = {
+	{ "rschd_fifo_empty15", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty16_reg[] = {
+	{ "rschd_fifo_empty16", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty17_reg[] = {
+	{ "rschd_fifo_empty17", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty18_reg[] = {
+	{ "rschd_fifo_empty18", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty19_reg[] = {
+	{ "rschd_fifo_empty19", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty20_reg[] = {
+	{ "rschd_fifo_empty20", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty21_reg[] = {
+	{ "rschd_fifo_empty21", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty22_reg[] = {
+	{ "rschd_fifo_empty22", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty23_reg[] = {
+	{ "rschd_fifo_empty23", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty24_reg[] = {
+	{ "rschd_fifo_empty24", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty25_reg[] = {
+	{ "rschd_fifo_empty25", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty26_reg[] = {
+	{ "rschd_fifo_empty26", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty27_reg[] = {
+	{ "rschd_fifo_empty27", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty28_reg[] = {
+	{ "rschd_fifo_empty28", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty29_reg[] = {
+	{ "rschd_fifo_empty29", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty30_reg[] = {
+	{ "rschd_fifo_empty30", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_rschd_fifo_empty31_reg[] = {
+	{ "rschd_fifo_empty31", DPP_FIELD_FLAG_RO, 14, 15, 0x7ffe, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ept_flag_reg[] = {
+	{ "ept_flag8", DPP_FIELD_FLAG_RO, 8, 1, 0x1, 0x0 },
+	{ "ept_flag7", DPP_FIELD_FLAG_RO, 7, 1, 0x1, 0x0 },
+	{ "ept_flag6", DPP_FIELD_FLAG_RO, 6, 1, 0x1, 0x0 },
+	{ "ept_flag5", DPP_FIELD_FLAG_RO, 5, 1, 0x1, 0x0 },
+	{ "ept_flag4", DPP_FIELD_FLAG_RO, 4, 1, 0x1, 0x0 },
+	{ "ept_flag3", DPP_FIELD_FLAG_RO, 3, 1, 0x1, 0x0 },
+	{ "ept_flag2", DPP_FIELD_FLAG_RO, 2, 1, 0x1, 0x0 },
+	{ "ept_flag1", DPP_FIELD_FLAG_RO, 1, 1, 0x1, 0x0 },
+	{ "ept_flag0", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ppu_soft_rst_reg[] = {
+	{ "ppu_soft_rst", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_as_mac_age_fc_cnt_reg[] = {
+	{ "smmu0_as_mac_age_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_marc_se_parser_fc_cnt_reg[] = {
+	{ "smmu0_marc_se_parser_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_wr_arb_cpu_fc_cnt_reg[] = {
+	{ "wr_arb_cpu_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_lpm_as_fc_cnt_reg[] = {
+	{ "smmu0_lpm_as_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_lpm_as_smmu0_fc_cnt_reg[] = {
+	{ "lpm_as_smmu0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_etcam1_0_as_fc_cnt_reg[] = {
+	{ "smmu0_etcam1_0_as_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_as_etcam1_0_smmu0_fc_cnt_reg[] = {
+	{ "as_etcam1_0_smmu0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_ppu_mcast_fc_cnt_reg[] = {
+	{ "smmu0_ppu_mcast_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ppu_smmu0_mcast_fc_cnt_reg[] = {
+	{ "ppu_smmu0_mcast_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_odma_smmu0_tdm_fc_rsp_fc_cnt_reg[] = {
+	{ "odma_smmu0_tdm_fc_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_odma_tdm_fc_key_fc_cnt_reg[] = {
+	{ "smmu0_odma_tdm_fc_key_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_odma_fc_cnt_reg[] = {
+	{ "smmu0_odma_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_cfg_tab_rd_fc_cnt_reg[] = {
+	{ "smmu0_cfg_tab_rd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_stat_fc15_0_cnt_reg[] = {
+	{ "smmu0_stat_fc15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_stat_smmu0_fc15_0_cnt_reg[] = {
+	{ "stat_smmu0_fc15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_ppu_mex5_0_fc_cnt_reg[] = {
+	{ "smmu0_ppu_mex5_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ppu_smmu0_mex5_0_fc_cnt_reg[] = {
+	{ "ppu_smmu0_mex5_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_as_smmu0_mac_age_req_cnt_reg[] = {
+	{ "as_smmu0_mac_age_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_se_parser_smmu0_marc_key_cnt_reg[] = {
+	{ "se_parser_smmu0_marc_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rdat_cnt_reg[] = {
+	{ "cpu_ind_rdat_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cpu_ind_rd_req_cnt_reg[] = {
+	{ "cpu_ind_rd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cpu_ind_wr_req_cnt_reg[] = {
+	{ "cpu_ind_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_plcr_rsp0_cnt_reg[] = {
+	{ "smmu0_plcr_rsp0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_plcr_smmu0_req0_cnt_reg[] = {
+	{ "plcr_smmu0_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_lpm_as_rsp_cnt_reg[] = {
+	{ "smmu0_lpm_as_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_lpm_as_smmu0_req_cnt_reg[] = {
+	{ "lpm_as_smmu0_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_etcam1_0_as_rsp_cnt_reg[] = {
+	{ "smmu0_etcam1_0_as_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_etcam1_0_as_smmu0_req_cnt_reg[] = {
+	{ "etcam1_0_as_smmu0_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_ppu_mcast_rsp_cnt_reg[] = {
+	{ "smmu0_ppu_mcast_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ppu_smmu0_mcast_key_cnt_reg[] = {
+	{ "ppu_smmu0_mcast_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_odma_tdm_mc_rsp_cnt_reg[] = {
+	{ "smmu0_odma_tdm_mc_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_odma_smmu0_tdm_mc_key_cnt_reg[] = {
+	{ "odma_smmu0_tdm_mc_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_odma_rsp_cnt_reg[] = {
+	{ "smmu0_odma_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_odma_smmu0_cmd_cnt_reg[] = {
+	{ "odma_smmu0_cmd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_cfg_tab_rdat_cnt_reg[] = {
+	{ "smmu0_cfg_tab_rdat_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_cfg_smmu0_tab_rd_cnt_reg[] = {
+	{ "cfg_smmu0_tab_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_stat_rsp15_0_cnt_reg[] = {
+	{ "smmu0_stat_rsp15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_stat_smmu0_req15_0_cnt_reg[] = {
+	{ "stat_smmu0_req15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_smmu0_ppu_mex5_0_rsp_cnt_reg[] = {
+	{ "smmu0_ppu_mex5_0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ppu_smmu0_mex5_0_key_cnt_reg[] = {
+	{ "ppu_smmu0_mex5_0_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ftm_stat_smmu0_req0_cnt_reg[] = {
+	{ "ftm_stat_smmu0_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_ftm_stat_smmu0_req1_cnt_reg[] = {
+	{ "ftm_stat_smmu0_req1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_etm_stat_smmu0_req0_cnt_reg[] = {
+	{ "etm_stat_smmu0_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_etm_stat_smmu0_req1_cnt_reg[] = {
+	{ "etm_stat_smmu0_req1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_req_eram0_31_rd_cnt_reg[] = {
+	{ "req_eram0_31_rd_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu0_smmu0_req_eram0_31_wr_cnt_reg[] = {
+	{ "req_eram0_31_wr_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_wdat1_reg[] = {
+	{ "ddr_wdat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_wdat2_reg[] = {
+	{ "ddr_wdat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_wdat3_reg[] = {
+	{ "ddr_wdat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_wdat4_reg[] = {
+	{ "ddr_wdat4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_wdat5_reg[] = {
+	{ "ddr_wdat5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_wdat6_reg[] = {
+	{ "ddr_wdat6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_wdat7_reg[] = {
+	{ "ddr_wdat7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_wdat8_reg[] = {
+	{ "ddr_wdat8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_wdat9_reg[] = {
+	{ "ddr_wdat9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_wdat10_reg[] = {
+	{ "ddr_wdat10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_wdat11_reg[] = {
+	{ "ddr_wdat11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_wdat12_reg[] = {
+	{ "ddr_wdat12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_wdat13_reg[] = {
+	{ "ddr_wdat13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_wdat14_reg[] = {
+	{ "ddr_wdat14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_wdat15_reg[] = {
+	{ "ddr_wdat15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cnt_stat_cache_en_reg[] = {
+	{ "cnt_stat_cache_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cnt_stat_cache_clr_reg[] = {
+	{ "cnt_stat_cache_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cnt_stat_cache_req_63_32_reg[] = {
+	{ "cnt_stat_cache_req_63_32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cnt_stat_cache_req_31_0_reg[] = {
+	{ "cnt_stat_cache_req_31_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cnt_stat_cache_hit_63_32_reg[] = {
+	{ "cnt_stat_cache_hit_63_32", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cnt_stat_cache_hit_31_0_reg[] = {
+	{ "cnt_stat_cache_hit_31_0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_cmd0_reg[] = {
+	{ "ecc_en", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "rw_len", DPP_FIELD_FLAG_RW, 21, 2, 0x0, 0x0 },
+	{ "baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_info_addr_reg[] = {
+	{ "info_addr", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_cmd1_reg[] = {
+	{ "rw_flag", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "rw_addr", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_clr_start_addr_reg[] = {
+	{ "clr_start_addr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_clr_end_addr_reg[] = {
+	{ "clr_end_addr", DPP_FIELD_FLAG_RW, 31, 32, 0xffffff, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_clr_tbl_en_reg[] = {
+	{ "cfg_init_en", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "clr_tbl_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_debug_cnt_mode_reg[] = {
+	{ "cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_init_done_reg[] = {
+	{ "cache_init_done", DPP_FIELD_FLAG_RO, 7, 1, 0x0, 0x0 },
+	{ "clr_done", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "init_ok", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rsp_rd_done_reg[] = {
+	{ "cpu_rsp_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ksch_oam_sp_en_reg[] = {
+	{ "ksch_oam_sp_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cfg_cache_en_reg[] = {
+	{ "cfg_cache_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cache_age_en_reg[] = {
+	{ "cache_age_en", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rdat0_reg[] = {
+	{ "cpu_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rdat1_reg[] = {
+	{ "cpu_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rdat2_reg[] = {
+	{ "cpu_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rdat3_reg[] = {
+	{ "cpu_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rdat4_reg[] = {
+	{ "cpu_rdat4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rdat5_reg[] = {
+	{ "cpu_rdat5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rdat6_reg[] = {
+	{ "cpu_rdat6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rdat7_reg[] = {
+	{ "cpu_rdat7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rdat8_reg[] = {
+	{ "cpu_rdat8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rdat9_reg[] = {
+	{ "cpu_rdat9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rdat10_reg[] = {
+	{ "cpu_rdat10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rdat11_reg[] = {
+	{ "cpu_rdat11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rdat12_reg[] = {
+	{ "cpu_rdat12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rdat13_reg[] = {
+	{ "cpu_rdat13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rdat14_reg[] = {
+	{ "cpu_rdat14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rdat15_reg[] = {
+	{ "cpu_rdat15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ctrl_cpu_rd_rdy_reg[] = {
+	{ "ctrl_cpu_rd_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_warbi_rdy_cfg_reg[] = {
+	{ "cpu_warbi_rdy_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_dir_arbi_cpu_rpful_reg[] = {
+	{ "smmu1_cfg_rpful", DPP_FIELD_FLAG_RW, 15, 8, 0x44, 0x0 },
+	{ "smmu1_cfg_wpful", DPP_FIELD_FLAG_RW, 7, 8, 0x44, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_dir_arbi_wpful_reg[] = {
+	{ "smmu1_ser_wdir_pful", DPP_FIELD_FLAG_RW, 17, 10, 0x14a, 0x0 },
+	{ "smmu1_cfg_wdir_pful", DPP_FIELD_FLAG_RW, 7, 8, 0x22, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cfg_wr_arbi_pful0_reg[] = {
+	{ "arbi_out_pful", DPP_FIELD_FLAG_RW, 17, 12, 0x71c, 0x0 },
+	{ "cpu_wr_pful", DPP_FIELD_FLAG_RW, 5, 6, 0x22, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cfg_wr_arbi_pful1_reg[] = {
+	{ "tm_wr_pful", DPP_FIELD_FLAG_RW, 23, 12, 0x4d3, 0x0 },
+	{ "stat_wr_pful", DPP_FIELD_FLAG_RW, 11, 12, 0x555, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_wdone_pful_cfg_reg[] = {
+	{ "smmu1_wdone_pful_cfg", DPP_FIELD_FLAG_RW, 19, 20, 0x7e1f8, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_stat_rate_cfg_cnt_reg[] = {
+	{ "stat_rate_cfg_cnt", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ftm_rate_cfg_cnt_reg[] = {
+	{ "ftm_rate_cfg_cnt", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_etm_rate_cfg_cnt_reg[] = {
+	{ "etm_rate_cfg_cnt", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_dir_rate_cfg_cnt_reg[] = {
+	{ "dir_rate_cfg_cnt", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_hash_rate_cfg_cnt_reg[] = {
+	{ "hash_rate_cfg_cnt", DPP_FIELD_FLAG_RW, 9, 10, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ftm_tbl_cfg_reg[] = {
+	{ "ftm_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_v4_as_tbl_cfg_reg[] = {
+	{ "lpm_v4_as_rsp_len", DPP_FIELD_FLAG_RW, 22, 2, 0x0, 0x0 },
+	{ "lpm_v4_as_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "lpm_v4_as_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_v4_tbl_cfg_reg[] = {
+	{ "lpm_v4_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "lpm_v4_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "lpm_v4_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_v6_tbl_cfg_reg[] = {
+	{ "lpm_v6_len", DPP_FIELD_FLAG_RO, 22, 2, 0x2, 0x0 },
+	{ "lpm_v6_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "lpm_v6_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_v6_as_tbl_cfg_reg[] = {
+	{ "lpm_v6_as_rsp_len", DPP_FIELD_FLAG_RW, 22, 2, 0x0, 0x0 },
+	{ "lpm_v6_as_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "lpm_v6_as_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_dma_tbl_cfg_reg[] = {
+	{ "dma_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_oam_tbl_cfg_reg[] = {
+	{ "oam_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ctrl_rpar_cpu_pful_reg[] = {
+	{ "ctrl_rpar_cpu_pful", DPP_FIELD_FLAG_RW, 7, 8, 0x44, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cfg_ksch_dir_pful_reg[] = {
+	{ "cfg_ksch_dir_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3434, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cfg_ksch_hash_pful_reg[] = {
+	{ "cfg_ksch_hash_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3030, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cfg_ksch_lpm_pful_reg[] = {
+	{ "cfg_ksch_lpm_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3030, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cfg_ksch_lpm_as_pful_reg[] = {
+	{ "cfg_ksch_lpm_as_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3030, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cfg_ksch_stat_pful_reg[] = {
+	{ "cfg_ksch_stat_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3434, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cfg_ksch_tm_pful_reg[] = {
+	{ "cfg_ksch_tm_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x3232, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cfg_ksch_oam_pful_reg[] = {
+	{ "cfg_ksch_oam_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x2a2a, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cfg_ksch_dma_pful_reg[] = {
+	{ "cfg_ksch_dma_pful", DPP_FIELD_FLAG_RW, 15, 16, 0x2727, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ctrl_wfifo_cfg_reg[] = {
+	{ "ctrl_wfifo_cfg", DPP_FIELD_FLAG_RW, 9, 10, 0x18c, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_rsch_hash_ptr_cfg_reg[] = {
+	{ "rsch_hash_ptr_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0xe, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_rsch_lpm_ptr_cfg_reg[] = {
+	{ "rsch_lpm_ptr_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0xe, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_rsch_lpm_as_ptr_cfg_reg[] = {
+	{ "rsch_lpm_as_ptr_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0xe, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_rsch_stat_ptr_cfg_reg[] = {
+	{ "rsch_stat_ptr_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0xe, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_rsch_oam_ptr_cfg_reg[] = {
+	{ "rsch_oam_ptr_cfg", DPP_FIELD_FLAG_RW, 8, 9, 0x12, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_rschd_fifo_pept_cfg_reg[] = {
+	{ "rschd_fifo_pept_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x204, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_dir_fifo_pful_cfg_reg[] = {
+	{ "dir_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_hash_fifo_pful_cfg_reg[] = {
+	{ "hash_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_fifo_pful_cfg_reg[] = {
+	{ "lpm_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_as_fifo_pful_cfg_reg[] = {
+	{ "lpm_as_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_stat_fifo_pful_cfg_reg[] = {
+	{ "stat_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ftm_fifo_pful_cfg_reg[] = {
+	{ "ftm_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_etm_fifo_pful_cfg_reg[] = {
+	{ "etm_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_oam_fifo_pful_cfg_reg[] = {
+	{ "oam_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_dma_fifo_pful_cfg_reg[] = {
+	{ "dma_fifo_pful_cfg", DPP_FIELD_FLAG_RW, 13, 14, 0x1e3c, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cache_rsp_rr_fifo_cfg_reg[] = {
+	{ "rr_pfull_assert0", DPP_FIELD_FLAG_RW, 11, 6, 0x14, 0x0 },
+	{ "rr_pfull_negate0", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr_rsp_rr_fifo_cfg_reg[] = {
+	{ "rr_pfull_assert1", DPP_FIELD_FLAG_RW, 13, 7, 0x20, 0x0 },
+	{ "rr_pfull_negate1", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_cahce_fifo_cfg_reg[] = {
+	{ "smmu1_cahce_fwft_fifo_pfull_assert", DPP_FIELD_FLAG_RW, 7, 4, 0x6, 0x0 },
+	{ "smmu1_cahce_fwft_fifo_pfull_negate", DPP_FIELD_FLAG_RW, 3, 4, 0x6, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cache_rsp_fifo_cfg_reg[] = {
+	{ "rschd_fifo_pfull_assert", DPP_FIELD_FLAG_RW, 11, 6, 0x10, 0x0 },
+	{ "rschd_fifo_pfull_negate", DPP_FIELD_FLAG_RW, 5, 6, 0x10, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_test_state_reg[] = {
+	{ "test_state", DPP_FIELD_FLAG_RW, 31, 32, 0x11111111, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cache_fifo_ept_reg[] = {
+	{ "cache_fifo_ept", DPP_FIELD_FLAG_RO, 1, 2, 0x3, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_rr_fifo_ept_reg[] = {
+	{ "rr_fifo_ept", DPP_FIELD_FLAG_RO, 1, 2, 0x3, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_wr_fifo_ept_reg[] = {
+	{ "dir_arbi_ept", DPP_FIELD_FLAG_RO, 6, 7, 0x7f, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_wdone_fifo_ept_reg[] = {
+	{ "wdone_fifo_ept", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_kschd_fifo_ept0_reg[] = {
+	{ "kschd_fifo_ept0", DPP_FIELD_FLAG_RO, 14, 15, 0x7fff, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cash_fifo_ept_reg[] = {
+	{ "cash_fifo_ept", DPP_FIELD_FLAG_RO, 1, 2, 0x3, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ctrl_fifo_ept_reg[] = {
+	{ "ctrl_fifo_ept", DPP_FIELD_FLAG_RO, 2, 3, 0x7, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_rschd_ept3_reg[] = {
+	{ "rschd_fifo_ept3", DPP_FIELD_FLAG_RO, 31, 32, 0xffffff, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_rschd_ept2_reg[] = {
+	{ "rschd_fifo_ept2", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_rschd_ept1_reg[] = {
+	{ "rschd_fifo_ept1", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_rschd_ept0_reg[] = {
+	{ "rschd_fifo_ept0", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cash0_ecc_err_addr_reg[] = {
+	{ "cash0_ecc_err_addr", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_arbi_cpu_wr_rdy_reg[] = {
+	{ "arbi_cpu_wr_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_int_0_en_reg[] = {
+	{ "smmu1_int_0_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_int_0_mask_reg[] = {
+	{ "smmu1_int_0_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_int_1_en_reg[] = {
+	{ "smmu1_int_1_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_int_1_mask_reg[] = {
+	{ "smmu1_int_1_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_int_2_en_reg[] = {
+	{ "smmu1_int_2_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_int_2_mask_reg[] = {
+	{ "smmu1_int_2_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_int_3_en_reg[] = {
+	{ "smmu1_int_3_en", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_int_3_mask_reg[] = {
+	{ "smmu1_int_3_mask", DPP_FIELD_FLAG_RW, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_int_0_status_reg[] = {
+	{ "smmu1_int_0_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_int_1_status_reg[] = {
+	{ "smmu1_int_1_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_int_2_status_reg[] = {
+	{ "smmu1_int_2_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_int_3_status_reg[] = {
+	{ "smmu1_int_3_status", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_int_status_reg[] = {
+	{ "smmu1_int_status", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ctrl_to_cash7_0_fc_cnt_reg[] = {
+	{ "ctrl_to_cash7_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cash7_0_to_ctrl_req_cnt_reg[] = {
+	{ "cash7_0_to_ctrl_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_rschd_to_cache7_fc_cnt_reg[] = {
+	{ "rschd_to_cache7_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cash7_to_cache_rsp_cnt_reg[] = {
+	{ "cash7_to_cache_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cash7_to_ctrl_fc_cnt_reg[] = {
+	{ "cash7_to_ctrl_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ctrl_to_cash7_0_rsp_cnt_reg[] = {
+	{ "ctrl_to_cash7_0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_kschd_to_cache7_0_req_cnt_reg[] = {
+	{ "kschd_to_cache7_0_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cache7_0_to_kschd_fc_cnt_reg[] = {
+	{ "cache7_0_to_kschd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_dma_to_smmu1_rd_req_cnt_reg[] = {
+	{ "dma_to_smmu1_rd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_oam_to_kschd_req_cnt_reg[] = {
+	{ "oam_to_kschd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_oam_rr_state_rsp_cnt_reg[] = {
+	{ "oam_rr_state_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_oam_clash_info_cnt_reg[] = {
+	{ "oam_clash_info_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_oam_to_rr_req_cnt_reg[] = {
+	{ "oam_to_rr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_as_to_kschd_req_cnt_reg[] = {
+	{ "lpm_as_to_kschd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_as_rr_state_rsp_cnt_reg[] = {
+	{ "lpm_as_rr_state_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_as_clash_info_cnt_reg[] = {
+	{ "lpm_as_clash_info_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_as_to_rr_req_cnt_reg[] = {
+	{ "lpm_as_to_rr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_to_kschd_req_cnt_reg[] = {
+	{ "lpm_to_kschd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_rr_state_rsp_cnt_reg[] = {
+	{ "lpm_rr_state_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_clash_info_cnt_reg[] = {
+	{ "lpm_clash_info_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_to_rr_req_cnt_reg[] = {
+	{ "lpm_to_rr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_hash3_0_to_kschd_req_cnt_reg[] = {
+	{ "hash3_0_to_kschd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_hash3_0_rr_state_rsp_cnt_reg[] = {
+	{ "hash3_0_rr_state_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_hash3_0_clash_info_cnt_reg[] = {
+	{ "hash3_0_clash_info_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_hash3_0_to_rr_req_cnt_reg[] = {
+	{ "hash3_0_to_rr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_dir3_0_to_kschd_req_cnt_reg[] = {
+	{ "dir3_0_to_kschd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_dir3_0_clash_info_cnt_reg[] = {
+	{ "dir3_0_clash_info_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_dir_tbl_wr_req_cnt_reg[] = {
+	{ "dir_tbl_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_warbi_to_dir_tbl_warbi_fc_cnt_reg[] = {
+	{ "warbi_to_dir_tbl_warbi_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_dir3_0_to_bank_rr_req_cnt_reg[] = {
+	{ "dir3_0_to_bank_rr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_kschd_to_dir3_0_fc_cnt_reg[] = {
+	{ "kschd_to_dir3_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_dir3_0_rr_state_rsp_cnt_reg[] = {
+	{ "dir3_0_rr_state_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_wr_done_to_warbi_fc_cnt_reg[] = {
+	{ "wr_done_to_warbi_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_wr_done_ptr_req_cnt_reg[] = {
+	{ "wr_done_ptr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ctrl7_0_to_warbi_fc_cnt_reg[] = {
+	{ "ctrl7_0_to_warbi_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_warbi_to_ctrl7_0_wr_req_cnt_reg[] = {
+	{ "warbi_to_ctrl7_0_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_warbi_to_cash7_0_wr_req_cnt_reg[] = {
+	{ "warbi_to_cash7_0_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_warbi_to_cpu_wr_fc_cnt_reg[] = {
+	{ "warbi_to_cpu_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_wr_req_cnt_reg[] = {
+	{ "cpu_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ctrl7_0_to_cpu_rd_rsp_cnt_reg[] = {
+	{ "ctrl7_0_to_cpu_rd_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_to_ctrl7_0_rd_req_cnt_reg[] = {
+	{ "cpu_to_ctrl7_0_rd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_rd_dir_tbl_rsp_cnt_reg[] = {
+	{ "cpu_rd_dir_tbl_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cpu_to_dir_tbl_rd_wr_req_cnt_reg[] = {
+	{ "cpu_to_dir_tbl_rd_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_mmu_7_0_rsp_fc_cnt_reg[] = {
+	{ "smmu1_to_mmu_7_0_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_mmu_7_0_to_smmu1_rd_rsp_cnt_reg[] = {
+	{ "mmu_7_0_to_smmu1_rd_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_mmu_7_0_to_smmu1_rd_fc_cnt_reg[] = {
+	{ "mmu_7_0_to_smmu1_rd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_mmu_7_rd_req_cnt_reg[] = {
+	{ "smmu1_to_mmu_7_rd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_mmu_7_to_smmu1_wr_fc_cnt_reg[] = {
+	{ "mmu_7_to_smmu1_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_mmu_7_0_wr_req_cnt_reg[] = {
+	{ "smmu1_to_mmu_7_0_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_se_to_smmu1_wr_rsp_fc_cnt_reg[] = {
+	{ "se_to_smmu1_wr_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_se_wr_rsp_cnt_reg[] = {
+	{ "smmu1_to_se_wr_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ddr7_0_wr_rsp_cnt_reg[] = {
+	{ "ddr7_0_wr_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_as_fc_cnt_reg[] = {
+	{ "smmu1_to_as_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_as_to_smmu1_wr_req_cnt_reg[] = {
+	{ "as_to_smmu1_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_se_parser_fc_cnt_reg[] = {
+	{ "smmu1_to_se_parser_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_se_parser_to_smmu1_req_cnt_reg[] = {
+	{ "se_parser_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_etm_wr_fc_cnt_reg[] = {
+	{ "smmu1_to_etm_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_etm_wr_req_cnt_reg[] = {
+	{ "etm_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_ftm_wr_fc_cnt_reg[] = {
+	{ "smmu1_to_ftm_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ftm_wr_req_cnt_reg[] = {
+	{ "ftm_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_state_wr_fc_cnt_reg[] = {
+	{ "smmu1_to_state_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_state_wr_req_cnt_reg[] = {
+	{ "state_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_se_to_dma_rsp_cnt_reg[] = {
+	{ "se_to_dma_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_se_to_dma_fc_cnt_reg[] = {
+	{ "se_to_dma_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_oam_to_smmu1_fc_cnt_reg[] = {
+	{ "oam_to_smmu1_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_oam_rsp_cnt_reg[] = {
+	{ "smmu1_to_oam_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_oam_fc_cnt_reg[] = {
+	{ "smmu1_to_oam_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_oam_to_smmu1_req_cnt_reg[] = {
+	{ "oam_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_etm_rsp_cnt_reg[] = {
+	{ "smmu1_to_etm_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_ftm_rsp_cnt_reg[] = {
+	{ "smmu1_to_ftm_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_etm_fc_cnt_reg[] = {
+	{ "smmu1_to_etm_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_etm_to_smmu1_req_cnt_reg[] = {
+	{ "etm_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_ftm_fc_cnt_reg[] = {
+	{ "smmu1_to_ftm_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_ftm_to_smmu1_req_cnt_reg[] = {
+	{ "ftm_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_stat_rsp_cnt_reg[] = {
+	{ "smmu1_to_stat_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_stat_fc_cnt_reg[] = {
+	{ "smmu1_to_stat_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_stat_to_smmu1_req_cnt_reg[] = {
+	{ "stat_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_as_to_smmu1_fc_cnt_reg[] = {
+	{ "lpm_as_to_smmu1_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_to_smmu1_fc_cnt_reg[] = {
+	{ "lpm_to_smmu1_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_lpm_as_rsp_cnt_reg[] = {
+	{ "smmu1_to_lpm_as_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_lpm_rsp_cnt_reg[] = {
+	{ "smmu1_to_lpm_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_lpm_as_fc_cnt_reg[] = {
+	{ "smmu1_to_lpm_as_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_lpm_fc_cnt_reg[] = {
+	{ "smmu1_to_lpm_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_as_to_smmu1_req_cnt_reg[] = {
+	{ "lpm_as_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_lpm_to_smmu1_req_cnt_reg[] = {
+	{ "lpm_to_smmu1_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_hash3_0_to_smmu1_fc_cnt_reg[] = {
+	{ "hash3_0_to_smmu1_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_hash3_0_rsp_cnt_reg[] = {
+	{ "smmu1_to_hash3_0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_hash3_0_fc_cnt_reg[] = {
+	{ "smmu1_to_hash3_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_hash3_0_to_smmu1_cnt_reg[] = {
+	{ "hash3_0_to_smmu1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_se_to_smmu1_dir3_0_rsp_fc_cnt_reg[] = {
+	{ "se_to_smmu1_dir3_0_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_se_dir3_0_rsp_cnt_reg[] = {
+	{ "smmu1_to_se_dir3_0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_smmu1_to_se_dir3_0_fc_cnt_reg[] = {
+	{ "smmu1_to_se_dir3_0_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_se_to_smmu1_dir3_0_cnt_reg[] = {
+	{ "se_to_smmu1_dir3_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_smmu1_cache7_0_to_rschd_rsp_cnt_reg[] = {
+	{ "cache7_0_to_rschd_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_ddr_rw_addr_reg[] = {
+	{ "ddr_wr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_ddr_rw_mode_reg[] = {
+	{ "ddr_rw_flag", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "ddr_rw_mode", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cp_cmd_reg[] = {
+	{ "stat_tbl_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cpu_ind_rd_done_reg[] = {
+	{ "cpu_ind_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cpu_ind_rdat0_reg[] = {
+	{ "cpu_ind_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cpu_ind_rdat1_reg[] = {
+	{ "cpu_ind_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cpu_ind_rdat2_reg[] = {
+	{ "cpu_ind_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cpu_ind_rdat3_reg[] = {
+	{ "cpu_ind_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cpu_ddr_fifo_almful_reg[] = {
+	{ "cpu_ddr_fifo_almful", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_debug_cnt_mode_reg[] = {
+	{ "cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cmmu_pful_cfg_reg[] = {
+	{ "alu_cmd_pful_negate", DPP_FIELD_FLAG_RW, 17, 9, 0xf8, 0x0 },
+	{ "alu_cmd_pful_assert", DPP_FIELD_FLAG_RW, 8, 9, 0xf8, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cmmu_stat_pful_cfg_reg[] = {
+	{ "cmmu_stat_pful_negate", DPP_FIELD_FLAG_RW, 11, 6, 0x14, 0x0 },
+	{ "cmmu_stat_pful_assert", DPP_FIELD_FLAG_RW, 5, 6, 0x14, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_stat_overflow_mode_reg[] = {
+	{ "stat_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cmmu_cp_fifo_pful_reg[] = {
+	{ "cmmu_cp_fifo_pful", DPP_FIELD_FLAG_RW, 7, 8, 0x66, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_ddr_wr_dat0_reg[] = {
+	{ "ddr_wr_dat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_ddr_wr_dat1_reg[] = {
+	{ "ddr_wr_dat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cmmu_int_unmask_flag_reg[] = {
+	{ "cmmu_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cmmu_int_en_reg[] = {
+	{ "cmmu_int_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "cmmu_int_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "cmmu_int_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "cmmu_int_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "cmmu_int_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "cmmu_int_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "cmmu_int_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "cmmu_int_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "cmmu_int_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "cmmu_int_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "cmmu_int_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "cmmu_int_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "cmmu_int_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cmmu_int_mask_reg[] = {
+	{ "cmmu_int_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "cmmu_int_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "cmmu_int_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "cmmu_int_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "cmmu_int_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "cmmu_int_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "cmmu_int_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "cmmu_int_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "cmmu_int_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "cmmu_int_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "cmmu_int_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "cmmu_int_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "cmmu_int_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cmmu_int_status_reg[] = {
+	{ "cmmu_int_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "cmmu_int_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "cmmu_int_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "cmmu_int_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "cmmu_int_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "cmmu_int_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "cmmu_int_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "cmmu_int_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "cmmu_int_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "cmmu_int_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "cmmu_int_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "cmmu_int_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "cmmu_int_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_stat_cmmu_req_cnt_reg[] = {
+	{ "stat_cmmu_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cmmu_fc0_cnt_reg[] = {
+	{ "cmmu_stat_rdy", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cmmu_fc1_cnt_reg[] = {
+	{ "smmu1_cmmu_wr_rdy", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_se_cmmu_cmmu_fc2_cnt_reg[] = {
+	{ "smmu1_cmmu_rd_rdy", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl0_cfg_reg[] = {
+	{ "hash0_tbl0_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash0_tbl0_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash0_tbl0_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl1_cfg_reg[] = {
+	{ "hash0_tbl1_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash0_tbl1_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash0_tbl1_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl2_cfg_reg[] = {
+	{ "hash0_tbl2_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash0_tbl2_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash0_tbl2_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl3_cfg_reg[] = {
+	{ "hash0_tbl3_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash0_tbl3_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash0_tbl3_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl4_cfg_reg[] = {
+	{ "hash0_tbl4_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash0_tbl4_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash0_tbl4_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl5_cfg_reg[] = {
+	{ "hash0_tbl5_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash0_tbl5_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash0_tbl5_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl6_cfg_reg[] = {
+	{ "hash0_tbl6_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash0_tbl6_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash0_tbl6_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash0_tbl7_cfg_reg[] = {
+	{ "hash0_tbl7_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash0_tbl7_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash0_tbl7_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl0_cfg_reg[] = {
+	{ "hash1_tbl0_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash1_tbl0_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash1_tbl0_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl1_cfg_reg[] = {
+	{ "hash1_tbl1_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash1_tbl1_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash1_tbl1_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl2_cfg_reg[] = {
+	{ "hash1_tbl2_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash1_tbl2_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash1_tbl2_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl3_cfg_reg[] = {
+	{ "hash1_tbl3_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash1_tbl3_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash1_tbl3_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl4_cfg_reg[] = {
+	{ "hash1_tbl4_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash1_tbl4_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash1_tbl4_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl5_cfg_reg[] = {
+	{ "hash1_tbl5_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash1_tbl5_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash1_tbl5_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl6_cfg_reg[] = {
+	{ "hash1_tbl6_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash1_tbl6_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash1_tbl6_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash1_tbl7_cfg_reg[] = {
+	{ "hash1_tbl7_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash1_tbl7_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash1_tbl7_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl0_cfg_reg[] = {
+	{ "hash2_tbl0_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash2_tbl0_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash2_tbl0_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl1_cfg_reg[] = {
+	{ "hash2_tbl1_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash2_tbl1_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash2_tbl1_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl2_cfg_reg[] = {
+	{ "hash2_tbl2_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash2_tbl2_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash2_tbl2_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl3_cfg_reg[] = {
+	{ "hash2_tbl3_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash2_tbl3_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash2_tbl3_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl4_cfg_reg[] = {
+	{ "hash2_tbl4_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash2_tbl4_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash2_tbl4_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl5_cfg_reg[] = {
+	{ "hash2_tbl5_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash2_tbl5_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash2_tbl5_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl6_cfg_reg[] = {
+	{ "hash2_tbl6_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash2_tbl6_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash2_tbl6_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash2_tbl7_cfg_reg[] = {
+	{ "hash2_tbl7_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash2_tbl7_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash2_tbl7_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl0_cfg_reg[] = {
+	{ "hash3_tbl0_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash3_tbl0_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash3_tbl0_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl1_cfg_reg[] = {
+	{ "hash3_tbl1_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash3_tbl1_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash3_tbl1_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl2_cfg_reg[] = {
+	{ "hash3_tbl2_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash3_tbl2_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash3_tbl2_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl3_cfg_reg[] = {
+	{ "hash3_tbl3_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash3_tbl3_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash3_tbl3_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl4_cfg_reg[] = {
+	{ "hash3_tbl4_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash3_tbl4_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash3_tbl4_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl5_cfg_reg[] = {
+	{ "hash3_tbl5_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash3_tbl5_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash3_tbl5_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl6_cfg_reg[] = {
+	{ "hash3_tbl6_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash3_tbl6_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash3_tbl6_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_smmu14k_se_smmu1_hash3_tbl7_cfg_reg[] = {
+	{ "hash3_tbl7_len", DPP_FIELD_FLAG_RO, 22, 2, 0x1, 0x0 },
+	{ "hash3_tbl7_ecc_en", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "hash3_tbl7_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_wdat1_reg[] = {
+	{ "cpu_ind_eram_wdat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_wdat2_reg[] = {
+	{ "cpu_ind_eram_wdat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_wdat3_reg[] = {
+	{ "cpu_ind_eram_wdat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_req_info_reg[] = {
+	{ "rw_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "read_mode", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0 },
+	{ "tm_cs", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0 },
+	{ "queue_cs", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0 },
+	{ "rw_addr", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_rd_done_reg[] = {
+	{ "cpu_ind_eram_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_rdat0_reg[] = {
+	{ "cpu_ind_eram_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_rdat1_reg[] = {
+	{ "cpu_ind_eram_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_rdat2_reg[] = {
+	{ "cpu_ind_eram_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_eram_rdat3_reg[] = {
+	{ "cpu_ind_eram_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_tm_alu_eram_cpu_rdy_reg[] = {
+	{ "tm_alu_eram_cpu_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_oam_stat_cfg_reg[] = {
+	{ "oam_flow_control_cfg", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "oam_lm_flow_control_cfg", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "oam_in_eram_cfg", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_ftm_port_sel_cfg_reg[] = {
+	{ "ftm_port0_sel_cfg", DPP_FIELD_FLAG_RW, 19, 5, 0x0, 0x0 },
+	{ "ftm_port1_sel_cfg", DPP_FIELD_FLAG_RW, 14, 5, 0x1, 0x0 },
+	{ "ftm_port2_sel_cfg", DPP_FIELD_FLAG_RW, 9, 5, 0xf, 0x0 },
+	{ "ftm_port3_sel_cfg", DPP_FIELD_FLAG_RW, 4, 5, 0x10, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_oam_eram_base_addr_reg[] = {
+	{ "oam_eram_base_addr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_oam_lm_eram_base_addr_reg[] = {
+	{ "oam_lm_eram_base_addr", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_oam_ddr_base_addr_reg[] = {
+	{ "oam_ddr_base_addr", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_plcr0_schd_pful_cfg_reg[] = {
+	{ "plcr0_schd_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x2c, 0x0 },
+	{ "plcr0_schd_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x2c, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_oam_lm_ord_pful_cfg_reg[] = {
+	{ "oam_lm_ord_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x28, 0x0 },
+	{ "oam_lm_ord_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x28, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_ddr_schd_pful_cfg_reg[] = {
+	{ "ddr_schd_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x2c, 0x0 },
+	{ "ddr_schd_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x2c, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_eram_schd_pful_cfg_reg[] = {
+	{ "eram_schd_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x28, 0x0 },
+	{ "eram_schd_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x28, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_eram_schd_pept_cfg_reg[] = {
+	{ "eram_schd_pept_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x18, 0x0 },
+	{ "eram_schd_pept_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x18, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_eram_schd_oam_pful_cfg_reg[] = {
+	{ "eram_schd_oam_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x28, 0x0 },
+	{ "eram_schd_oam_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x28, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_eram_schd_oam_pept_cfg_reg[] = {
+	{ "eram_schd_oam_pept_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x18, 0x0 },
+	{ "eram_schd_oam_pept_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x18, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_eram_schd_oam_lm_pful_cfg_reg[] = {
+	{ "eram_schd_oam_lm_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x28, 0x0 },
+	{ "eram_schd_oam_lm_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x28, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_eram_schd_oam_lm_pept_cfg_reg[] = {
+	{ "eram_schd_oam_lm_pept_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x18, 0x0 },
+	{ "eram_schd_oam_lm_pept_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x18, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_rschd_pful_cfg_reg[] = {
+	{ "rschd_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x24, 0x0 },
+	{ "rschd_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x24, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_rschd_pept_cfg_reg[] = {
+	{ "rschd_pept_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x1c, 0x0 },
+	{ "rschd_pept_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x1c, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_rschd_plcr_pful_cfg_reg[] = {
+	{ "rschd_plcr_pful_assert", DPP_FIELD_FLAG_RW, 15, 8, 0x40, 0x0 },
+	{ "rschd_plcr_pful_negate", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_rschd_plcr_pept_cfg_reg[] = {
+	{ "rschd_plcr_pept_assert", DPP_FIELD_FLAG_RW, 15, 8, 0x40, 0x0 },
+	{ "rschd_plcr_pept_negate", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_rschd_plcr_info_pful_cfg_reg[] = {
+	{ "rschd_plcr_info_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x38, 0x0 },
+	{ "rschd_plcr_info_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x38, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_alu_arb_cpu_pful_cfg_reg[] = {
+	{ "alu_arb_cpu_pful_assert", DPP_FIELD_FLAG_RW, 9, 5, 0x08, 0x0 },
+	{ "alu_arb_cpu_pful_negate", DPP_FIELD_FLAG_RW, 4, 5, 0x08, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_alu_arb_user_pful_cfg_reg[] = {
+	{ "alu_arb_user_pful_assert", DPP_FIELD_FLAG_RW, 9, 5, 0x0d, 0x0 },
+	{ "alu_arb_user_pful_negate", DPP_FIELD_FLAG_RW, 4, 5, 0x0d, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_alu_arb_stat_pful_cfg_reg[] = {
+	{ "alu_arb_stat_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x20, 0x0 },
+	{ "alu_arb_stat_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x20, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cycmov_dat_pful_cfg_reg[] = {
+	{ "cycmov_dat_pful_assert", DPP_FIELD_FLAG_RW, 9, 5, 0x0d, 0x0 },
+	{ "cycmov_dat_pful_negate", DPP_FIELD_FLAG_RW, 4, 5, 0x0d, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_ddr_opr_pful_cfg_reg[] = {
+	{ "ddr_opr_pful_assert", DPP_FIELD_FLAG_RW, 9, 5, 0xc, 0x0 },
+	{ "ddr_opr_pful_negate", DPP_FIELD_FLAG_RW, 4, 5, 0xc, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cycle_mov_pful_cfg_reg[] = {
+	{ "cycle_mov_pful_assert", DPP_FIELD_FLAG_RW, 11, 6, 0x1c, 0x0 },
+	{ "cycle_mov_pful_negate", DPP_FIELD_FLAG_RW, 5, 6, 0x1c, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cntovf_pful_cfg_reg[] = {
+	{ "cntovf_pful_assert", DPP_FIELD_FLAG_RW, 13, 7, 0x32, 0x0 },
+	{ "cntovf_pful_negate", DPP_FIELD_FLAG_RW, 6, 7, 0x32, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_eram_schd_plcr_pful_cfg_reg[] = {
+	{ "eram_schd_plcr_pful_assert", DPP_FIELD_FLAG_RW, 15, 8, 0x40, 0x0 },
+	{ "eram_schd_plcr_pful_negate", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_eram_schd_plcr_pept_cfg_reg[] = {
+	{ "eram_schd_plcr_pept_assert", DPP_FIELD_FLAG_RW, 15, 8, 0x40, 0x0 },
+	{ "eram_schd_plcr_pept_negate", DPP_FIELD_FLAG_RW, 7, 8, 0x40, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_debug_cnt_mode_reg[] = {
+	{ "cnt_rd_mode", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "cnt_overflow_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_tm_mov_period_cfg_reg[] = {
+	{ "etm_mov_period_cfg", DPP_FIELD_FLAG_RW, 15, 8, 0x3c, 0x0 },
+	{ "ftm_mov_period_cfg", DPP_FIELD_FLAG_RW, 7, 8, 0x3c, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_alu_ddr_cpu_req_pful_cfg_reg[] = {
+	{ "alu_ddr_cpu_req_pful_assert", DPP_FIELD_FLAG_RW, 7, 4, 0x4, 0x0 },
+	{ "alu_ddr_cpu_req_pful_negate", DPP_FIELD_FLAG_RW, 3, 4, 0x4, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cycmov_addr_pful_cfg_reg[] = {
+	{ "cycmov_addr_pful_assert", DPP_FIELD_FLAG_RW, 9, 5, 0xd, 0x0 },
+	{ "cycmov_addr_pful_negate", DPP_FIELD_FLAG_RW, 4, 5, 0xd, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_ord_ddr_plcr_fifo_empty_reg[] = {
+	{ "ord_oam_lm_empty", DPP_FIELD_FLAG_RO, 19, 1, 0x1, 0x0 },
+	{ "ddr_schd_fifo_empty", DPP_FIELD_FLAG_RO, 18, 7, 0x7f, 0x0 },
+	{ "plcr0_schd_fifo_empty", DPP_FIELD_FLAG_RO, 5, 6, 0x3f, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_tm_stat_fifo_empty_reg[] = {
+	{ "tm_stat_fifo_empty", DPP_FIELD_FLAG_RO, 13, 14, 0x3fff, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_eram_schd_fifo_empty_0_1_reg[] = {
+	{ "eram_schd_fifo_empty1", DPP_FIELD_FLAG_RO, 31, 16, 0xffff, 0x0 },
+	{ "eram_schd_fifo_empty0", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_eram_schd_fifo_empty_2_3_reg[] = {
+	{ "eram_schd_fifo_empty3", DPP_FIELD_FLAG_RO, 31, 16, 0xffff, 0x0 },
+	{ "eram_schd_fifo_empty2", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_eram_schd_fifo_empty_4_5_reg[] = {
+	{ "eram_schd_fifo_empty5", DPP_FIELD_FLAG_RO, 31, 16, 0xffff, 0x0 },
+	{ "eram_schd_fifo_empty4", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_eram_schd_fifo_empty_6_7_reg[] = {
+	{ "eram_schd_fifo_empty7", DPP_FIELD_FLAG_RO, 31, 16, 0xffff, 0x0 },
+	{ "eram_schd_fifo_empty6", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_eram_schd_fifo_empty_free_8_reg[] = {
+	{ "eram_schd_free_fifo_empty8", DPP_FIELD_FLAG_RO, 24, 1, 0x1, 0x0 },
+	{ "eram_schd_free_fifo_empty7", DPP_FIELD_FLAG_RO, 23, 1, 0x1, 0x0 },
+	{ "eram_schd_free_fifo_empty6", DPP_FIELD_FLAG_RO, 22, 1, 0x1, 0x0 },
+	{ "eram_schd_free_fifo_empty5", DPP_FIELD_FLAG_RO, 21, 1, 0x1, 0x0 },
+	{ "eram_schd_free_fifo_empty4", DPP_FIELD_FLAG_RO, 20, 1, 0x1, 0x0 },
+	{ "eram_schd_free_fifo_empty3", DPP_FIELD_FLAG_RO, 19, 1, 0x1, 0x0 },
+	{ "eram_schd_free_fifo_empty2", DPP_FIELD_FLAG_RO, 18, 1, 0x1, 0x0 },
+	{ "eram_schd_free_fifo_empty1", DPP_FIELD_FLAG_RO, 17, 1, 0x1, 0x0 },
+	{ "eram_schd_free_fifo_empty0", DPP_FIELD_FLAG_RO, 16, 1, 0x1, 0x0 },
+	{ "eram_schd_fifo_empty8", DPP_FIELD_FLAG_RO, 15, 16, 0xffff, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_rschd_fifo_empty_0_3_reg[] = {
+	{ "rschd_fifo_empty3", DPP_FIELD_FLAG_RO, 31, 8, 0xff, 0x0 },
+	{ "rschd_fifo_empty2", DPP_FIELD_FLAG_RO, 23, 8, 0xff, 0x0 },
+	{ "rschd_fifo_empty1", DPP_FIELD_FLAG_RO, 15, 8, 0xff, 0x0 },
+	{ "rschd_fifo_empty0", DPP_FIELD_FLAG_RO, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_rschd_fifo_empty_4_7_reg[] = {
+	{ "rschd_fifo_empty7", DPP_FIELD_FLAG_RO, 31, 8, 0xff, 0x0 },
+	{ "rschd_fifo_empty6", DPP_FIELD_FLAG_RO, 23, 8, 0xff, 0x0 },
+	{ "rschd_fifo_empty5", DPP_FIELD_FLAG_RO, 15, 8, 0xff, 0x0 },
+	{ "rschd_fifo_empty4", DPP_FIELD_FLAG_RO, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_rschd_fifo_empty_8_11_reg[] = {
+	{ "rschd_fifo_empty11", DPP_FIELD_FLAG_RO, 31, 8, 0xff, 0x0 },
+	{ "rschd_fifo_empty10", DPP_FIELD_FLAG_RO, 23, 8, 0xff, 0x0 },
+	{ "rschd_fifo_empty9", DPP_FIELD_FLAG_RO, 15, 8, 0xff, 0x0 },
+	{ "rschd_fifo_empty8", DPP_FIELD_FLAG_RO, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_rschd_fifo_empty_12_15_reg[] = {
+	{ "rschd_fifo_empty15", DPP_FIELD_FLAG_RO, 31, 8, 0xff, 0x0 },
+	{ "rschd_fifo_empty14", DPP_FIELD_FLAG_RO, 23, 8, 0xff, 0x0 },
+	{ "rschd_fifo_empty13", DPP_FIELD_FLAG_RO, 15, 8, 0xff, 0x0 },
+	{ "rschd_fifo_empty12", DPP_FIELD_FLAG_RO, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_rschd_fifo_empty_plcr_16_17_reg[] = {
+	{ "rschd_fifo_empty_plcr", DPP_FIELD_FLAG_RO, 16, 1, 0x1, 0x0 },
+	{ "rschd_fifo_empty17", DPP_FIELD_FLAG_RO, 15, 8, 0xff, 0x0 },
+	{ "rschd_fifo_empty16", DPP_FIELD_FLAG_RO, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int_unmask_flag_reg[] = {
+	{ "stat_int5_unmask_flag", DPP_FIELD_FLAG_RO, 5, 1, 0x0, 0x0 },
+	{ "stat_int4_unmask_flag", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "stat_int3_unmask_flag", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "stat_int2_unmask_flag", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "stat_int1_unmask_flag", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "stat_int0_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int0_en_reg[] = {
+	{ "stat_int0_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "stat_int0_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "stat_int0_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "stat_int0_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "stat_int0_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "stat_int0_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "stat_int0_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "stat_int0_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "stat_int0_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "stat_int0_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "stat_int0_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "stat_int0_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "stat_int0_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "stat_int0_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "stat_int0_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "stat_int0_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "stat_int0_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "stat_int0_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "stat_int0_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "stat_int0_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "stat_int0_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "stat_int0_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "stat_int0_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "stat_int0_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "stat_int0_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "stat_int0_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "stat_int0_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "stat_int0_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "stat_int0_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "stat_int0_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "stat_int0_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "stat_int0_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int0_mask_reg[] = {
+	{ "stat_int0_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "stat_int0_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "stat_int0_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "stat_int0_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "stat_int0_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "stat_int0_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "stat_int0_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "stat_int0_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "stat_int0_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "stat_int0_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "stat_int0_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "stat_int0_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "stat_int0_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "stat_int0_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "stat_int0_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "stat_int0_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "stat_int0_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "stat_int0_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "stat_int0_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "stat_int0_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "stat_int0_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "stat_int0_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "stat_int0_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "stat_int0_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "stat_int0_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "stat_int0_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "stat_int0_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "stat_int0_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "stat_int0_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "stat_int0_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "stat_int0_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "stat_int0_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int0_status_reg[] = {
+	{ "stat_int0_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "stat_int0_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "stat_int0_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "stat_int0_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "stat_int0_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "stat_int0_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "stat_int0_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "stat_int0_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "stat_int0_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "stat_int0_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "stat_int0_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "stat_int0_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "stat_int0_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "stat_int0_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "stat_int0_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "stat_int0_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "stat_int0_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "stat_int0_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "stat_int0_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "stat_int0_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "stat_int0_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "stat_int0_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "stat_int0_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "stat_int0_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "stat_int0_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "stat_int0_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "stat_int0_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "stat_int0_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "stat_int0_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "stat_int0_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "stat_int0_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "stat_int0_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int1_en_reg[] = {
+	{ "stat_int1_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "stat_int1_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "stat_int1_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "stat_int1_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "stat_int1_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "stat_int1_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "stat_int1_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "stat_int1_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "stat_int1_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "stat_int1_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "stat_int1_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "stat_int1_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "stat_int1_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "stat_int1_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "stat_int1_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "stat_int1_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "stat_int1_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "stat_int1_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "stat_int1_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "stat_int1_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "stat_int1_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "stat_int1_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "stat_int1_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "stat_int1_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "stat_int1_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "stat_int1_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "stat_int1_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "stat_int1_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "stat_int1_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "stat_int1_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "stat_int1_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "stat_int1_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int1_mask_reg[] = {
+	{ "stat_int1_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "stat_int1_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "stat_int1_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "stat_int1_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "stat_int1_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "stat_int1_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "stat_int1_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "stat_int1_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "stat_int1_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "stat_int1_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "stat_int1_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "stat_int1_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "stat_int1_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "stat_int1_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "stat_int1_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "stat_int1_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "stat_int1_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "stat_int1_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "stat_int1_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "stat_int1_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "stat_int1_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "stat_int1_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "stat_int1_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "stat_int1_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "stat_int1_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "stat_int1_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "stat_int1_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "stat_int1_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "stat_int1_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "stat_int1_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "stat_int1_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "stat_int1_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int1_status_reg[] = {
+	{ "stat_int1_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "stat_int1_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "stat_int1_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "stat_int1_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "stat_int1_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "stat_int1_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "stat_int1_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "stat_int1_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "stat_int1_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "stat_int1_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "stat_int1_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "stat_int1_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "stat_int1_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "stat_int1_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "stat_int1_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "stat_int1_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "stat_int1_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "stat_int1_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "stat_int1_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "stat_int1_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "stat_int1_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "stat_int1_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "stat_int1_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "stat_int1_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "stat_int1_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "stat_int1_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "stat_int1_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "stat_int1_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "stat_int1_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "stat_int1_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "stat_int1_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "stat_int1_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int2_en_reg[] = {
+	{ "stat_int2_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "stat_int2_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "stat_int2_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "stat_int2_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "stat_int2_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "stat_int2_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "stat_int2_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "stat_int2_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "stat_int2_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "stat_int2_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "stat_int2_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "stat_int2_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "stat_int2_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "stat_int2_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "stat_int2_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "stat_int2_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "stat_int2_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "stat_int2_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "stat_int2_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "stat_int2_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "stat_int2_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "stat_int2_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "stat_int2_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "stat_int2_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "stat_int2_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "stat_int2_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "stat_int2_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "stat_int2_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "stat_int2_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "stat_int2_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "stat_int2_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "stat_int2_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int2_mask_reg[] = {
+	{ "stat_int2_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "stat_int2_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "stat_int2_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "stat_int2_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "stat_int2_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "stat_int2_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "stat_int2_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "stat_int2_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "stat_int2_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "stat_int2_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "stat_int2_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "stat_int2_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "stat_int2_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "stat_int2_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "stat_int2_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "stat_int2_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "stat_int2_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "stat_int2_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "stat_int2_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "stat_int2_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "stat_int2_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "stat_int2_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "stat_int2_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "stat_int2_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "stat_int2_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "stat_int2_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "stat_int2_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "stat_int2_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "stat_int2_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "stat_int2_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "stat_int2_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "stat_int2_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int2_status_reg[] = {
+	{ "stat_int2_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "stat_int2_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "stat_int2_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "stat_int2_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "stat_int2_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "stat_int2_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "stat_int2_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "stat_int2_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "stat_int2_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "stat_int2_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "stat_int2_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "stat_int2_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "stat_int2_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "stat_int2_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "stat_int2_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "stat_int2_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "stat_int2_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "stat_int2_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "stat_int2_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "stat_int2_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "stat_int2_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "stat_int2_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "stat_int2_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "stat_int2_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "stat_int2_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "stat_int2_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "stat_int2_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "stat_int2_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "stat_int2_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "stat_int2_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "stat_int2_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "stat_int2_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int3_en_reg[] = {
+	{ "stat_int3_en31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "stat_int3_en30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "stat_int3_en29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "stat_int3_en28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "stat_int3_en27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "stat_int3_en26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "stat_int3_en25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "stat_int3_en24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "stat_int3_en23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "stat_int3_en22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "stat_int3_en21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "stat_int3_en20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "stat_int3_en19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "stat_int3_en18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "stat_int3_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "stat_int3_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "stat_int3_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "stat_int3_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "stat_int3_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "stat_int3_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "stat_int3_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "stat_int3_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "stat_int3_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "stat_int3_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "stat_int3_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "stat_int3_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "stat_int3_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "stat_int3_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "stat_int3_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "stat_int3_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "stat_int3_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "stat_int3_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int3_mask_reg[] = {
+	{ "stat_int3_mask31", DPP_FIELD_FLAG_RW, 31, 1, 0x1, 0x0 },
+	{ "stat_int3_mask30", DPP_FIELD_FLAG_RW, 30, 1, 0x1, 0x0 },
+	{ "stat_int3_mask29", DPP_FIELD_FLAG_RW, 29, 1, 0x1, 0x0 },
+	{ "stat_int3_mask28", DPP_FIELD_FLAG_RW, 28, 1, 0x1, 0x0 },
+	{ "stat_int3_mask27", DPP_FIELD_FLAG_RW, 27, 1, 0x1, 0x0 },
+	{ "stat_int3_mask26", DPP_FIELD_FLAG_RW, 26, 1, 0x1, 0x0 },
+	{ "stat_int3_mask25", DPP_FIELD_FLAG_RW, 25, 1, 0x1, 0x0 },
+	{ "stat_int3_mask24", DPP_FIELD_FLAG_RW, 24, 1, 0x1, 0x0 },
+	{ "stat_int3_mask23", DPP_FIELD_FLAG_RW, 23, 1, 0x1, 0x0 },
+	{ "stat_int3_mask22", DPP_FIELD_FLAG_RW, 22, 1, 0x1, 0x0 },
+	{ "stat_int3_mask21", DPP_FIELD_FLAG_RW, 21, 1, 0x1, 0x0 },
+	{ "stat_int3_mask20", DPP_FIELD_FLAG_RW, 20, 1, 0x1, 0x0 },
+	{ "stat_int3_mask19", DPP_FIELD_FLAG_RW, 19, 1, 0x1, 0x0 },
+	{ "stat_int3_mask18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "stat_int3_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "stat_int3_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "stat_int3_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "stat_int3_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "stat_int3_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "stat_int3_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "stat_int3_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "stat_int3_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "stat_int3_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "stat_int3_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "stat_int3_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "stat_int3_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "stat_int3_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "stat_int3_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "stat_int3_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "stat_int3_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "stat_int3_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "stat_int3_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int3_status_reg[] = {
+	{ "stat_int3_status31", DPP_FIELD_FLAG_RC, 31, 1, 0x0, 0x0 },
+	{ "stat_int3_status30", DPP_FIELD_FLAG_RC, 30, 1, 0x0, 0x0 },
+	{ "stat_int3_status29", DPP_FIELD_FLAG_RC, 29, 1, 0x0, 0x0 },
+	{ "stat_int3_status28", DPP_FIELD_FLAG_RC, 28, 1, 0x0, 0x0 },
+	{ "stat_int3_status27", DPP_FIELD_FLAG_RC, 27, 1, 0x0, 0x0 },
+	{ "stat_int3_status26", DPP_FIELD_FLAG_RC, 26, 1, 0x0, 0x0 },
+	{ "stat_int3_status25", DPP_FIELD_FLAG_RC, 25, 1, 0x0, 0x0 },
+	{ "stat_int3_status24", DPP_FIELD_FLAG_RC, 24, 1, 0x0, 0x0 },
+	{ "stat_int3_status23", DPP_FIELD_FLAG_RC, 23, 1, 0x0, 0x0 },
+	{ "stat_int3_status22", DPP_FIELD_FLAG_RC, 22, 1, 0x0, 0x0 },
+	{ "stat_int3_status21", DPP_FIELD_FLAG_RC, 21, 1, 0x0, 0x0 },
+	{ "stat_int3_status20", DPP_FIELD_FLAG_RC, 20, 1, 0x0, 0x0 },
+	{ "stat_int3_status19", DPP_FIELD_FLAG_RC, 19, 1, 0x0, 0x0 },
+	{ "stat_int3_status18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "stat_int3_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "stat_int3_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "stat_int3_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "stat_int3_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "stat_int3_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "stat_int3_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "stat_int3_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "stat_int3_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "stat_int3_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "stat_int3_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "stat_int3_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "stat_int3_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "stat_int3_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "stat_int3_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "stat_int3_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "stat_int3_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "stat_int3_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "stat_int3_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int4_en_reg[] = {
+	{ "stat_int4_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "stat_int4_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "stat_int4_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "stat_int4_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "stat_int4_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "stat_int4_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "stat_int4_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "stat_int4_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "stat_int4_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "stat_int4_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "stat_int4_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "stat_int4_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "stat_int4_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "stat_int4_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "stat_int4_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "stat_int4_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "stat_int4_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "stat_int4_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "stat_int4_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int4_mask_reg[] = {
+	{ "stat_int4_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "stat_int4_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int4_status_reg[] = {
+	{ "stat_int4_mask_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "stat_int4_mask_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int5_en_reg[] = {
+	{ "stat_int5_en_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "stat_int5_en_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "stat_int5_en_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "stat_int5_en_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "stat_int5_en_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "stat_int5_en_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "stat_int5_en_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "stat_int5_en_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "stat_int5_en_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "stat_int5_en_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "stat_int5_en_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "stat_int5_en_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "stat_int5_en_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "stat_int5_en_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "stat_int5_en_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "stat_int5_en_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "stat_int5_en_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "stat_int5_en_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "stat_int5_en_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int5_mask_reg[] = {
+	{ "stat_int5_mask_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "stat_int5_mask_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_int5_status_reg[] = {
+	{ "stat_int5_mask_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "stat_int5_mask_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_rschd_ecc_bypass_reg[] = {
+	{ "rschd_ecc_bypass_18", DPP_FIELD_FLAG_RW, 18, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "rschd_ecc_bypass_0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_rschd_ecc_single_err_reg[] = {
+	{ "rschd_ecc_single_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "rschd_ecc_single_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_rschd_ecc_double_err_reg[] = {
+	{ "rschd_ecc_double_err_18", DPP_FIELD_FLAG_RC, 18, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "rschd_ecc_double_err_0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat0_reg[] = {
+	{ "cpu_ind_ddr_wdat0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat1_reg[] = {
+	{ "cpu_ind_ddr_wdat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat2_reg[] = {
+	{ "cpu_ind_ddr_wdat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat3_reg[] = {
+	{ "cpu_ind_ddr_wdat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat4_reg[] = {
+	{ "cpu_ind_ddr_wdat4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat5_reg[] = {
+	{ "cpu_ind_ddr_wdat5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat6_reg[] = {
+	{ "cpu_ind_ddr_wdat6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat7_reg[] = {
+	{ "cpu_ind_ddr_wdat7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat8_reg[] = {
+	{ "cpu_ind_ddr_wdat8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat9_reg[] = {
+	{ "cpu_ind_ddr_wdat9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat10_reg[] = {
+	{ "cpu_ind_ddr_wdat10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat11_reg[] = {
+	{ "cpu_ind_ddr_wdat11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat12_reg[] = {
+	{ "cpu_ind_ddr_wdat12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat13_reg[] = {
+	{ "cpu_ind_ddr_wdat13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat14_reg[] = {
+	{ "cpu_ind_ddr_wdat14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_wdat15_reg[] = {
+	{ "cpu_ind_ddr_wdat15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_req_info_reg[] = {
+	{ "rw_mode", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "read_mode", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0 },
+	{ "tm_cs", DPP_FIELD_FLAG_RW, 14, 1, 0x0, 0x0 },
+	{ "rw_addr", DPP_FIELD_FLAG_RW, 13, 14, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rd_done_reg[] = {
+	{ "cpu_ind_ddr_rd_done", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat0_reg[] = {
+	{ "cpu_ind_ddr_rdat0", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat1_reg[] = {
+	{ "cpu_ind_ddr_rdat1", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat2_reg[] = {
+	{ "cpu_ind_ddr_rdat2", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat3_reg[] = {
+	{ "cpu_ind_ddr_rdat3", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat4_reg[] = {
+	{ "cpu_ind_ddr_rdat4", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat5_reg[] = {
+	{ "cpu_ind_ddr_rdat5", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat6_reg[] = {
+	{ "cpu_ind_ddr_rdat6", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat7_reg[] = {
+	{ "cpu_ind_ddr_rdat7", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat8_reg[] = {
+	{ "cpu_ind_ddr_rdat8", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat9_reg[] = {
+	{ "cpu_ind_ddr_rdat9", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat10_reg[] = {
+	{ "cpu_ind_ddr_rdat10", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat11_reg[] = {
+	{ "cpu_ind_ddr_rdat11", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat12_reg[] = {
+	{ "cpu_ind_ddr_rdat12", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat13_reg[] = {
+	{ "cpu_ind_ddr_rdat13", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat14_reg[] = {
+	{ "cpu_ind_ddr_rdat14", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_ind_ddr_rdat15_reg[] = {
+	{ "cpu_ind_ddr_rdat15", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_tm_alu_ddr_cpu_rdy_reg[] = {
+	{ "tm_alu_ddr_cpu_rdy", DPP_FIELD_FLAG_RO, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_ept_flag_reg[] = {
+	{ "ept_flag", DPP_FIELD_FLAG_RO, 5, 6, 0x3f, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_ppu_soft_rst_reg[] = {
+	{ "ppu_soft_rst", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_smmu0_fc15_0_cnt_reg[] = {
+	{ "stat_smmu0_fc15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_smmu0_stat_fc15_0_cnt_reg[] = {
+	{ "smmu0_stat_fc15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_smmu0_stat_rsp15_0_cnt_reg[] = {
+	{ "smmu0_stat_rsp15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_smmu0_req15_0_cnt_reg[] = {
+	{ "stat_smmu0_req15_0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_ppu_stat_mec5_0_rsp_fc_cnt_reg[] = {
+	{ "ppu_stat_mec5_0_rsp_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_ppu_mec5_0_key_fc_cnt_reg[] = {
+	{ "stat_ppu_mec5_0_key_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_ppu_mec5_0_rsp_cnt_reg[] = {
+	{ "stat_ppu_mec5_0_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_ppu_stat_mec5_0_key_cnt_reg[] = {
+	{ "ppu_stat_mec5_0_key_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_ppu5_0_no_exist_opcd_ex_cnt_reg[] = {
+	{ "ppu5_0_no_exist_opcd_ex_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_se_etm_stat_wr_fc_cnt_reg[] = {
+	{ "se_etm_stat_wr_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_se_etm_stat_rd_fc_cnt_reg[] = {
+	{ "se_etm_stat_rd_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_etm_deq_fc_cnt_reg[] = {
+	{ "stat_etm_deq_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_etm_enq_fc_cnt_reg[] = {
+	{ "stat_etm_enq_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_oam_lm_fc_cnt_reg[] = {
+	{ "stat_oam_lm_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_oam_stat_lm_fc_cnt_reg[] = {
+	{ "oam_stat_lm_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_oam_fc_cnt_reg[] = {
+	{ "stat_oam_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cmmu_stat_fc_cnt_reg[] = {
+	{ "cmmu_stat_fc_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_cmmu_req_cnt_reg[] = {
+	{ "stat_cmmu_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_smmu0_plcr_rsp0_cnt_reg[] = {
+	{ "smmu0_plcr_rsp0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_plcr_smmu0_req0_cnt_reg[] = {
+	{ "plcr_smmu0_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_stat_oam_lm_rsp_cnt_reg[] = {
+	{ "stat_oam_lm_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_oam_stat_lm_req_cnt_reg[] = {
+	{ "oam_stat_lm_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_oam_stat_req_cnt_reg[] = {
+	{ "oam_stat_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_se_etm_stat_rsp_cnt_reg[] = {
+	{ "se_etm_stat_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_etm_stat_se_wr_req_cnt_reg[] = {
+	{ "etm_stat_se_wr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_etm_stat_se_rd_req_cnt_reg[] = {
+	{ "etm_stat_se_rd_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_etm_stat_smmu0_req_cnt0_reg[] = {
+	{ "etm_stat_smmu0_req_cnt0", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_etm_stat_smmu0_req_cnt1_reg[] = {
+	{ "etm_stat_smmu0_req_cnt1", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_tm_stat_eram_cpu_rsp_cnt_reg[] = {
+	{ "tm_stat_eram_cpu_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_rd_eram_req_cnt_reg[] = {
+	{ "cpu_rd_eram_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_wr_eram_req_cnt_reg[] = {
+	{ "cpu_wr_eram_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_tm_stat_ddr_cpu_rsp_cnt_reg[] = {
+	{ "tm_stat_ddr_cpu_rsp_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_rd_ddr_req_cnt_reg[] = {
+	{ "cpu_rd_ddr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_stat_cfg_cpu_wr_ddr_req_cnt_reg[] = {
+	{ "cpu_wr_ddr_req_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat1_reg[] = {
+	{ "wdat1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat2_reg[] = {
+	{ "wdat2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat3_reg[] = {
+	{ "wdat3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat4_reg[] = {
+	{ "wdat4", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat5_reg[] = {
+	{ "wdat5", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat6_reg[] = {
+	{ "wdat6", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat7_reg[] = {
+	{ "wdat7", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat8_reg[] = {
+	{ "wdat8", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat9_reg[] = {
+	{ "wdat9", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat10_reg[] = {
+	{ "wdat10", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat11_reg[] = {
+	{ "wdat11", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat12_reg[] = {
+	{ "wdat12", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat13_reg[] = {
+	{ "wdat13", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat14_reg[] = {
+	{ "wdat14", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat15_reg[] = {
+	{ "wdat15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat16_reg[] = {
+	{ "wdat16", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat17_reg[] = {
+	{ "wdat17", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat18_reg[] = {
+	{ "wdat18", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_cpu_ind_wdat19_reg[] = {
+	{ "wdat19", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_t_strwc_cfg_reg[] = {
+	{ "t_strwc_cfg", DPP_FIELD_FLAG_RW, 1, 2, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_etcam_int_unmask_flag_reg[] = {
+	{ "etcam_int_unmask_flag", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_etcam_int_en0_reg[] = {
+	{ "etcam_int_en17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "etcam_int_en16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "etcam_int_en15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "etcam_int_en14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "etcam_int_en13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "etcam_int_en12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "etcam_int_en11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "etcam_int_en10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "etcam_int_en9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "etcam_int_en8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "etcam_int_en7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "etcam_int_en6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "etcam_int_en5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "etcam_int_en4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "etcam_int_en3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "etcam_int_en2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "etcam_int_en1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "etcam_int_en0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_etcam_int_mask0_reg[] = {
+	{ "etcam_int_mask17", DPP_FIELD_FLAG_RW, 17, 1, 0x1, 0x0 },
+	{ "etcam_int_mask16", DPP_FIELD_FLAG_RW, 16, 1, 0x1, 0x0 },
+	{ "etcam_int_mask15", DPP_FIELD_FLAG_RW, 15, 1, 0x1, 0x0 },
+	{ "etcam_int_mask14", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "etcam_int_mask13", DPP_FIELD_FLAG_RW, 13, 1, 0x1, 0x0 },
+	{ "etcam_int_mask12", DPP_FIELD_FLAG_RW, 12, 1, 0x1, 0x0 },
+	{ "etcam_int_mask11", DPP_FIELD_FLAG_RW, 11, 1, 0x1, 0x0 },
+	{ "etcam_int_mask10", DPP_FIELD_FLAG_RW, 10, 1, 0x1, 0x0 },
+	{ "etcam_int_mask9", DPP_FIELD_FLAG_RW, 9, 1, 0x1, 0x0 },
+	{ "etcam_int_mask8", DPP_FIELD_FLAG_RW, 8, 1, 0x1, 0x0 },
+	{ "etcam_int_mask7", DPP_FIELD_FLAG_RW, 7, 1, 0x1, 0x0 },
+	{ "etcam_int_mask6", DPP_FIELD_FLAG_RW, 6, 1, 0x1, 0x0 },
+	{ "etcam_int_mask5", DPP_FIELD_FLAG_RW, 5, 1, 0x1, 0x0 },
+	{ "etcam_int_mask4", DPP_FIELD_FLAG_RW, 4, 1, 0x1, 0x0 },
+	{ "etcam_int_mask3", DPP_FIELD_FLAG_RW, 3, 1, 0x1, 0x0 },
+	{ "etcam_int_mask2", DPP_FIELD_FLAG_RW, 2, 1, 0x1, 0x0 },
+	{ "etcam_int_mask1", DPP_FIELD_FLAG_RW, 1, 1, 0x1, 0x0 },
+	{ "etcam_int_mask0", DPP_FIELD_FLAG_RW, 0, 1, 0x1, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_etcam_int_status_reg[] = {
+	{ "etcam_int_status17", DPP_FIELD_FLAG_RC, 17, 1, 0x0, 0x0 },
+	{ "etcam_int_status16", DPP_FIELD_FLAG_RC, 16, 1, 0x0, 0x0 },
+	{ "etcam_int_status15", DPP_FIELD_FLAG_RC, 15, 1, 0x0, 0x0 },
+	{ "etcam_int_status14", DPP_FIELD_FLAG_RC, 14, 1, 0x0, 0x0 },
+	{ "etcam_int_status13", DPP_FIELD_FLAG_RC, 13, 1, 0x0, 0x0 },
+	{ "etcam_int_status12", DPP_FIELD_FLAG_RC, 12, 1, 0x0, 0x0 },
+	{ "etcam_int_status11", DPP_FIELD_FLAG_RC, 11, 1, 0x0, 0x0 },
+	{ "etcam_int_status10", DPP_FIELD_FLAG_RC, 10, 1, 0x0, 0x0 },
+	{ "etcam_int_status9", DPP_FIELD_FLAG_RC, 9, 1, 0x0, 0x0 },
+	{ "etcam_int_status8", DPP_FIELD_FLAG_RC, 8, 1, 0x0, 0x0 },
+	{ "etcam_int_status7", DPP_FIELD_FLAG_RC, 7, 1, 0x0, 0x0 },
+	{ "etcam_int_status6", DPP_FIELD_FLAG_RC, 6, 1, 0x0, 0x0 },
+	{ "etcam_int_status5", DPP_FIELD_FLAG_RC, 5, 1, 0x0, 0x0 },
+	{ "etcam_int_status4", DPP_FIELD_FLAG_RC, 4, 1, 0x0, 0x0 },
+	{ "etcam_int_status3", DPP_FIELD_FLAG_RC, 3, 1, 0x0, 0x0 },
+	{ "etcam_int_status2", DPP_FIELD_FLAG_RC, 2, 1, 0x0, 0x0 },
+	{ "etcam_int_status1", DPP_FIELD_FLAG_RC, 1, 1, 0x0, 0x0 },
+	{ "etcam_int_status0", DPP_FIELD_FLAG_RC, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_int_tb_ini_ok_reg[] = {
+	{ "int_tb_ini_ok", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_etcam_clk_en_reg[] = {
+	{ "etcam_clk_en", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_as_etcam_req0_cnt_reg[] = {
+	{ "as_etcam_req0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_as_etcam_req1_cnt_reg[] = {
+	{ "as_etcam_req1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_etcam_as_index0_cnt_reg[] = {
+	{ "etcam_as_index0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_etcam_as_index1_cnt_reg[] = {
+	{ "etcam_as_index1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_etcam_not_hit0_cnt_reg[] = {
+	{ "etcam_not_hit0_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_etcam_not_hit1_cnt_reg[] = {
+	{ "etcam_not_hit1_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_table_id_not_match_cnt_reg[] = {
+	{ "table_id_not_match_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_table_id_clash01_cnt_reg[] = {
+	{ "table_id_clash01_cnt", DPP_FIELD_FLAG_RC, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_etcam_cpu_fl_reg[] = {
+	{ "etcam_cpu_fl", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_stat_etcam_etcam_arb_empty_reg[] = {
+	{ "etcam_arb_empty", DPP_FIELD_FLAG_RO, 31, 32, 0xffffffff, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_event0_reg[] = {
+	{ "cfg_finish_int_event0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_event1_reg[] = {
+	{ "cfg_finish_int_event1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_event2_reg[] = {
+	{ "cfg_finish_int_event2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_event3_reg[] = {
+	{ "cfg_finish_int_event3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_maks0_reg[] = {
+	{ "cfg_finish_int_mask0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_maks1_reg[] = {
+	{ "cfg_finish_int_mask1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_maks2_reg[] = {
+	{ "cfg_finish_int_mask2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_maks3_reg[] = {
+	{ "cfg_finish_int_mask3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_test0_reg[] = {
+	{ "cfg_finish_int_test0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_test1_reg[] = {
+	{ "cfg_finish_int_test1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_test2_reg[] = {
+	{ "cfg_finish_int_test2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_finish_int_test3_reg[] = {
+	{ "cfg_finish_int_test3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_int_to_riscv_sel_reg[] = {
+	{ "cfg_dtb_int_to_riscv_sel0", DPP_FIELD_FLAG_RW, 6, 7, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_ep_int_msix_enable_reg[] = {
+	{ "cfg_dtb_ep_int_msix_enable", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_h_0_15_reg[] = {
+	{ "cfg_dtb_ep_doorbell_addr_h_0_15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_l_0_15_reg[] = {
+	{ "cfg_dtb_ep_doorbell_addr_l_0_15", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_debug_mode_en_reg[] = {
+	{ "cfg_dtb_debug_mode_en", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_table_addr_high_reg[] = {
+	{ "info_axi_last_rd_table_addr_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_table_addr_low_reg[] = {
+	{ "info_axi_last_rd_table_addr_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_table_len_reg[] = {
+	{ "info_axi_last_rd_table_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_table_user_reg[] = {
+	{ "info_rd_table_user_en", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0 },
+	{ "info_rd_table_epid", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0 },
+	{ "info_rd_table_vfunc_num", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0 },
+	{ "info_rd_table_func_num", DPP_FIELD_FLAG_RO, 7, 3, 0x0, 0x0 },
+	{ "info_rd_table_vfunc_active", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_table_onload_cnt_reg[] = {
+	{ "info_axi_last_rd_table_onload_cnt", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_axi_rd_table_resp_err_reg[] = {
+	{ "cnt_axi_rd_table_resp_err", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_pd_addr_high_reg[] = {
+	{ "info_axi_last_rd_pd_addr_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_pd_addr_low_reg[] = {
+	{ "info_axi_last_rd_pd_addr_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_pd_len_reg[] = {
+	{ "info_axi_last_rd_pd_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_pd_user_reg[] = {
+	{ "info_rd_pd_user_en", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0 },
+	{ "info_rd_pd_epid", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0 },
+	{ "info_rd_pd_vfunc_num", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0 },
+	{ "info_rd_pd_func_num", DPP_FIELD_FLAG_RO, 7, 3, 0x0, 0x0 },
+	{ "info_rd_pd_vfunc_active", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_rd_pd_onload_cnt_reg[] = {
+	{ "info_axi_last_rd_pd_onload_cnt", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_axi_rd_pd_resp_err_reg[] = {
+	{ "cnt_axi_rd_pd_resp_err", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_high_reg[] = {
+	{ "info_axi_last_wr_ctrl_addr_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_low_reg[] = {
+	{ "info_axi_last_wr_ctrl_addr_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ctrl_len_reg[] = {
+	{ "info_axi_last_wr_ctrl_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ctrl_user_reg[] = {
+	{ "info_wr_ctrl_user_en", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0 },
+	{ "info_wr_ctrl_epid", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0 },
+	{ "info_wr_ctrl_vfunc_num", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0 },
+	{ "info_wr_ctrl_func_num", DPP_FIELD_FLAG_RO, 7, 3, 0x0, 0x0 },
+	{ "info_wr_ctrl_vfunc_active", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ctrl_onload_cnt_reg[] = {
+	{ "info_axi_last_wr_ctrl_onload_cnt", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_axi_wr_ctrl_resp_err_reg[] = {
+	{ "cnt_axi_wr_ctrl_resp_err", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_high_reg[] = {
+	{ "info_axi_last_wr_ddr_addr_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_low_reg[] = {
+	{ "info_axi_last_wr_ddr_addr_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ddr_len_reg[] = {
+	{ "info_axi_last_wr_ddr_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ddr_user_reg[] = {
+	{ "info_wr_ddr_user_en", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0 },
+	{ "info_wr_ddr_epid", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0 },
+	{ "info_wr_ddr_vfunc_num", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0 },
+	{ "info_wr_ddr_func_num", DPP_FIELD_FLAG_RO, 7, 3, 0x0, 0x0 },
+	{ "info_wr_ddr_vfunc_active", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_ddr_onload_cnt_reg[] = {
+	{ "info_axi_last_wr_ddr_onload_cnt", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_axi_wr_ddr_resp_err_reg[] = {
+	{ "cnt_axi_wr_ddr_resp_err", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_fin_addr_high_reg[] = {
+	{ "info_axi_last_wr_fin_addr_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_fin_addr_low_reg[] = {
+	{ "info_axi_last_wr_fin_addr_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_fin_len_reg[] = {
+	{ "info_axi_last_wr_fin_len", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_fin_user_reg[] = {
+	{ "info_wr_fin_user_en", DPP_FIELD_FLAG_RO, 31, 1, 0x0, 0x0 },
+	{ "info_wr_fin_epid", DPP_FIELD_FLAG_RO, 27, 4, 0x0, 0x0 },
+	{ "info_wr_fin_vfunc_num", DPP_FIELD_FLAG_RO, 23, 8, 0x0, 0x0 },
+	{ "info_wr_fin_func_num", DPP_FIELD_FLAG_RO, 7, 3, 0x0, 0x0 },
+	{ "info_wr_fin_vfunc_active", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_axi_last_wr_fin_onload_cnt_reg[] = {
+	{ "info_axi_last_wr_fin_onload_cnt", DPP_FIELD_FLAG_RO, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_axi_wr_fin_resp_err_reg[] = {
+	{ "cnt_axi_wr_fin_resp_err", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_high_reg[] = {
+	{ "cnt_dtb_wr_smmu0_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_low_reg[] = {
+	{ "cnt_dtb_wr_smmu0_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_high_reg[] = {
+	{ "cnt_dtb_wr_smmu1_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_low_reg[] = {
+	{ "cnt_dtb_wr_smmu1_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_high_reg[] = {
+	{ "cnt_dtb_wr_zcam_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_low_reg[] = {
+	{ "cnt_dtb_wr_zcam_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_high_reg[] = {
+	{ "cnt_dtb_wr_etcam_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_low_reg[] = {
+	{ "cnt_dtb_wr_etcam_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_hash_table_high_reg[] = {
+	{ "cnt_dtb_wr_hash_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_wr_hash_table_low_reg[] = {
+	{ "cnt_dtb_wr_hash_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_high_reg[] = {
+	{ "cnt_dtb_rd_smmu0_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_low_reg[] = {
+	{ "cnt_dtb_rd_smmu0_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_high_reg[] = {
+	{ "cnt_dtb_rd_smmu1_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_low_reg[] = {
+	{ "cnt_dtb_rd_smmu1_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_high_reg[] = {
+	{ "cnt_dtb_rd_zcam_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_low_reg[] = {
+	{ "cnt_dtb_rd_zcam_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_high_reg[] = {
+	{ "cnt_dtb_rd_etcam_table_high", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_low_reg[] = {
+	{ "cnt_dtb_rd_etcam_table_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_wr_ctrl_state_reg[] = {
+	{ "info_wr_ctrl_state", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_rd_table_state_reg[] = {
+	{ "info_rd_table_state", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_rd_pd_state_reg[] = {
+	{ "info_rd_pd_state", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_dump_cmd_state_reg[] = {
+	{ "info_dump_cmd_state", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_info_wr_ddr_state_reg[] = {
+	{ "info_wr_ddr_state", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_cfg_cfg_dtb_debug_info_clr_reg[] = {
+	{ "cfg_dtb_debug_info_clr", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_ddos_cfg_ddos_stat_dump_thrd_0_15_reg[] = {
+	{ "cfg_ddos_stat_dump_thrd", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_ddos_cfg_ddos_stat_dump_thrd_comp_en_reg[] = {
+	{ "cfg_ddos_stat_dump_thrd_comp_en", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_ddos_cfg_ddos_dump_stat_num_reg[] = {
+	{ "cfg_ddos_dump_stat_num", DPP_FIELD_FLAG_RW, 23, 24, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_ddos_cfg_ddos_even_hash_table_baddr_reg[] = {
+	{ "cfg_ddos_even_hash_table_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_ddos_cfg_ddos_odd_hash_table_baddr_reg[] = {
+	{ "cfg_ddos_odd_hash_table_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_ddos_cfg_ddos_stat_index_offset_reg[] = {
+	{ "cfg_ddos_stat_index_offset", DPP_FIELD_FLAG_RW, 18, 19, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_ddos_cfg_ddos_ns_flag_cnt_reg[] = {
+	{ "cfg_ddos_ns_flag_cnt", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_ddos_cfg_ddos_even_stat_table_baddr_reg[] = {
+	{ "cfg_ddos_even_stat_table_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_ddos_cfg_ddos_odd_stat_table_baddr_reg[] = {
+	{ "cfg_ddos_odd_stat_table_baddr", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_ddos_cfg_ddos_even_stat_dump_daddr_h_reg[] = {
+	{ "cfg_ddos_even_stat_dump_daddr_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_ddos_cfg_ddos_even_stat_dump_daddr_l_reg[] = {
+	{ "cfg_ddos_even_stat_dump_daddr_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_h_reg[] = {
+	{ "cfg_ddos_odd_stat_dump_daddr_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_l_reg[] = {
+	{ "cfg_ddos_odd_stat_dump_daddr_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_ddos_cfg_ddos_work_mode_enable_reg[] = {
+	{ "cfg_ddos_mode_work_enable", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_ddos_cfg_ddos_stat_table_len_reg[] = {
+	{ "cfg_ddos_stat_table_len", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_ddos_cfg_ddos_hash_table_len_reg[] = {
+	{ "cfg_ddos_hash_table_len", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram0_0_255_reg[] = {
+	{ "traf_ctrl_ram0_0_255", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram1_0_255_reg[] = {
+	{ "traf_ctrl_ram1_0_255", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram2_0_255_reg[] = {
+	{ "traf_ctrl_ram2_0_255", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram3_0_255_reg[] = {
+	{ "traf_ctrl_ram3_0_255", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram4_0_255_reg[] = {
+	{ "traf_ctrl_ram4_0_255", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_ram_traf_ctrl_ram5_0_63_reg[] = {
+	{ "traf_ctrl_ram5_0_63", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_ram_dump_pd_ram_0_2047_reg[] = {
+	{ "dump_pd_ram_0_2047", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_ram_rd_ctrl_ram_0_4095_reg[] = {
+	{ "rd_ctrl_ram_0_4095", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_ram_rd_table_ram_0_8191_reg[] = {
+	{ "rd_table_ram_0_8191", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_dtb_dtb_ram_dtb_cmd_man_ram_0_16383_reg[] = {
+	{ "dtb_cmd_man_ram_0_16383", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_ms_st_reg[] = {
+	{ "cpu_trpgrx_ms_st", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_ms_ind_reg[] = {
+	{ "cpu_trpgrx_ms_ind", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpg_ms_slave_ind_reg[] = {
+	{ "cpu_trpgrx_ms_slave_ind", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_up_water_level_reg[] = {
+	{ "cpu_trpgrx_up_water_level", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_rx_port_cpu_trpgrx_low_water_level_reg[] = {
+	{ "cpu_trpgrx_low_water_level", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_ms_st_reg[] = {
+	{ "cpu_trpgtx_ms_st", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_ms_ind_reg[] = {
+	{ "cpu_trpgtx_ms_ind", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_port_cpu_trpg_ms_slave_ind_reg[] = {
+	{ "cpu_trpgtx_ms_slave_ind", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_update_int_event_reg[] = {
+	{ "cpu_todtime_update_int_event", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_update_int_test_reg[] = {
+	{ "cpu_todtime_update_int_test", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_glb_cpu_todtime_update_int_addr_reg[] = {
+	{ "cpu_todtime_update_int_addr", DPP_FIELD_FLAG_RO, 10, 11, 0x0, 0x0 },
+};
+DPP_FIELD_T g_trpg_trpg_tx_todtime_ram_trpg_tx_todtime_ram_reg[] = {
+	{ "trpg_tx_todtime_ram", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_test_reg_reg[] = {
+	{ "cfg_tsn_test_reg", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_qbv_enable_reg[] = {
+	{ "cfg_tsn_port_qbv_enable", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_phy_port_sel_reg[] = {
+	{ "cfg_tsn_phy_port_sel", DPP_FIELD_FLAG_RW, 3, 4, 0xf, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_time_sel_reg[] = {
+	{ "cfg_tsn_port_time_sel", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_clk_freq_reg[] = {
+	{ "en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "cfg_tsn_clk_freq", DPP_FIELD_FLAG_RW, 30, 31, 0x64, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_read_ram_n_reg[] = {
+	{ "cfg_tsn_data", DPP_FIELD_FLAG_RO, 15, 8, 0x0, 0x0 },
+	{ "cfg_tsn_read_status", DPP_FIELD_FLAG_RO, 5, 4, 0x0, 0x0 },
+	{ "cfg_tsn_read_ram_n", DPP_FIELD_FLAG_RO, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_exe_time_reg[] = {
+	{ "cfg_tsn_exe_time", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_itr_shift_reg[] = {
+	{ "cfg_tsn_port_itr_shift", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_base_time_h_reg[] = {
+	{ "cfg_tsn_port_base_time_h", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_base_time_l_reg[] = {
+	{ "cfg_tsn_port_base_time_l", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_cycle_time_h_reg[] = {
+	{ "cfg_tsn_port_cycle_time_h", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_cycle_time_l_reg[] = {
+	{ "cfg_tsn_port_cycle_time_l", DPP_FIELD_FLAG_RW, 19, 20, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_guard_band_time_reg[] = {
+	{ "cfg_tsn_port_guard_band_time", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_default_gate_en_reg[] = {
+	{ "cfg_tsn_port_default_gate_en", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_change_gate_en_reg[] = {
+	{ "cfg_tsn_port_change_gate_en", DPP_FIELD_FLAG_RW, 7, 8, 0xff, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_init_finish_reg[] = {
+	{ "cfg_tsn_port_init_finish", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_change_en_reg[] = {
+	{ "cfg_tsn_port_change_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_gcl_num0_reg[] = {
+	{ "cfg_tsn_port_gcl_num0", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_gcl_num1_reg[] = {
+	{ "cfg_tsn_port_gcl_num1", DPP_FIELD_FLAG_RW, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_gcl_value0_reg[] = {
+	{ "cfg_tsn_port_gcl_gate_control0", DPP_FIELD_FLAG_RW, 31, 8, 0x0, 0x0 },
+	{ "cfg_tsn_port_gcl_interval_time0", DPP_FIELD_FLAG_RW, 23, 24, 0x0, 0x0 },
+};
+DPP_FIELD_T g_tsn_tsn_port_cfg_tsn_port_gcl_value1_reg[] = {
+	{ "cfg_tsn_port_gcl_gate_control1", DPP_FIELD_FLAG_RW, 31, 8, 0x0, 0x0 },
+	{ "cfg_tsn_port_gcl_interval_time1", DPP_FIELD_FLAG_RW, 23, 24, 0x0, 0x0 },
+};
+DPP_FIELD_T g_axi_axi_conv_cfg_epid_v_func_num_reg[] = {
+	{ "user_en", DPP_FIELD_FLAG_RW, 31, 1, 0x0, 0x0 },
+	{ "cfg_epid", DPP_FIELD_FLAG_RW, 27, 4, 0x0, 0x0 },
+	{ "cfg_vfunc_num", DPP_FIELD_FLAG_RW, 23, 8, 0x0, 0x0 },
+	{ "cfg_func_num", DPP_FIELD_FLAG_RW, 7, 3, 0x0, 0x0 },
+	{ "cfg_vfunc_active", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_axi_axi_conv_info_axim_rw_hsk_cnt_reg[] = {
+	{ "axim_rd_handshake_cnt", DPP_FIELD_FLAG_RO, 24, 9, 0x0, 0x0 },
+	{ "axim_wr_handshake_cnt", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_axi_axi_conv_info_axim_last_wr_id_reg[] = {
+	{ "axim_rd_id", DPP_FIELD_FLAG_RO, 24, 9, 0x0, 0x0 },
+	{ "axim_wr_id", DPP_FIELD_FLAG_RO, 8, 9, 0x0, 0x0 },
+};
+DPP_FIELD_T g_axi_axi_conv_info_axim_last_wr_addr_h_reg[] = {
+	{ "aximlastwraddrhigh", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_axi_axi_conv_info_axim_last_wr_addr_l_reg[] = {
+	{ "aximlastrdaddrlow", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_axi_axi_conv_cfg_debug_info_clr_en_reg[] = {
+	{ "cfg_global_clr_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_pp1s_interrupt_reg[] = {
+	{ "int_state", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "int_test", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0 },
+	{ "int_clr", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "int_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_pp1s_external_select_reg[] = {
+	{ "pp1s_external_select", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_pp1s_out_select_reg[] = {
+	{ "pp1s_out_sel", DPP_FIELD_FLAG_RW, 1, 2, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_test_pp1s_select_reg[] = {
+	{ "test_pp1s_sel", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_local_pp1s_en_reg[] = {
+	{ "local_pp1s_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_local_pp1s_adjust_reg[] = {
+	{ "local_pp1s_adjust_sel", DPP_FIELD_FLAG_RW, 2, 2, 0x0, 0x0 },
+	{ "local_pp1s_adjust_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_local_pp1s_adjust_value_reg[] = {
+	{ "local_pp1s_adjust_value", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_pp1s_to_np_select_reg[] = {
+	{ "pp1s_to_np_sel", DPP_FIELD_FLAG_RW, 1, 2, 0x3, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_pd_u1_sel_reg[] = {
+	{ "pd_u1_sel1", DPP_FIELD_FLAG_RW, 5, 3, 0x0, 0x0 },
+	{ "pd_u1_sel0", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_pd_u1_pd0_shift_reg[] = {
+	{ "pd_u1_pd0_shift", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_pd_u1_pd1_shift_reg[] = {
+	{ "pd_u1_pd1_shift", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_pd_u1_result_reg[] = {
+	{ "pd_u1_result_sign", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0 },
+	{ "pd_u1_overflow", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0 },
+	{ "pd_u1_result", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_pd_u2_sel_reg[] = {
+	{ "pd_u2_sel1", DPP_FIELD_FLAG_RW, 5, 3, 0x0, 0x0 },
+	{ "pd_u2_sel0", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_pd_u2_pd0_shift_reg[] = {
+	{ "pd_u2_pd0_shift", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_pd_u2_pd1_shift_reg[] = {
+	{ "pd_u2_pd1_shift", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_pd_u2_result_reg[] = {
+	{ "pd_u2_result_sign", DPP_FIELD_FLAG_RO, 30, 1, 0x0, 0x0 },
+	{ "pd_u2_overflow", DPP_FIELD_FLAG_RO, 29, 1, 0x0, 0x0 },
+	{ "pd_u2_result", DPP_FIELD_FLAG_RO, 28, 29, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_tsn_group_nanosecond_delay0_reg[] = {
+	{ "tsn_group_nanosecond_delay0", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_tsn_group_fracnanosecond_delay0_reg[] = {
+	{ "tsn_group_fracnanosecond_delay0", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_tsn_group_nanosecond_delay1_reg[] = {
+	{ "tsn_group_nanosecond_delay1", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_tsn_group_fracnanosecond_delay1_reg[] = {
+	{ "tsn_group_fracnanosecond_delay1", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_tsn_group_nanosecond_delay2_reg[] = {
+	{ "tsn_group_nanosecond_delay2", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_tsn_group_fracnanosecond_delay2_reg[] = {
+	{ "tsn_group_fracnanosecond_delay2", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_tsn_group_nanosecond_delay3_reg[] = {
+	{ "tsn_group_nanosecond_delay3", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_tsn_group_fracnanosecond_delay3_reg[] = {
+	{ "tsn_group_fracnanosecond_delay3", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_tsn_ptp1588_rdma_nanosecond_delay_reg[] = {
+	{ "ptp1588_rdma_nanosecond_delay", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_ptp1588_rdma_fracnanosecond_delay_reg[] = {
+	{ "ptp1588_rdma_fracnanosecond_delay", DPP_FIELD_FLAG_RW, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_ptp1588_np_nanosecond_delay_reg[] = {
+	{ "ptp1588_np_nanosecond_delay", DPP_FIELD_FLAG_RW, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_ptp1588_np_fracnanosecond_delay_reg[] = {
+	{ "ptp1588_np_fracnanosecond_delay", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptp_top_time_sync_period_reg[] = {
+	{ "time_sync_period", DPP_FIELD_FLAG_RW, 2, 3, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_module_id_reg[] = {
+	{ "module_id", DPP_FIELD_FLAG_RO, 15, 16, 0x89, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_module_version_reg[] = {
+	{ "module_major_version", DPP_FIELD_FLAG_RO, 15, 8, 0x3, 0x0 },
+	{ "module_minor_version", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_module_date_reg[] = {
+	{ "year", DPP_FIELD_FLAG_RO, 31, 16, 0x2017, 0x0 },
+	{ "month", DPP_FIELD_FLAG_RO, 15, 8, 0x1, 0x0 },
+	{ "date", DPP_FIELD_FLAG_RO, 7, 8, 0x1, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_interrupt_status_reg[] = {
+	{ "pps_in_status", DPP_FIELD_FLAG_RO, 4, 1, 0x0, 0x0 },
+	{ "fifo_almost_full_status", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "fifo_no_empty_status", DPP_FIELD_FLAG_RO, 2, 1, 0x0, 0x0 },
+	{ "trigger_output_status", DPP_FIELD_FLAG_RO, 1, 1, 0x0, 0x0 },
+	{ "trigger_input_status", DPP_FIELD_FLAG_RO, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_interrupt_event_reg[] = {
+	{ "pps_in_event", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0 },
+	{ "fifo_almost_full_event", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0 },
+	{ "fifo_no_empty_event", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0 },
+	{ "trigger_output_event", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "trigger_input_event", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_interrupt_mask_reg[] = {
+	{ "pps_in_event_mask", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0 },
+	{ "fifo_almost_full_event_mask", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0 },
+	{ "fifo_no_empty_event_mask", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0 },
+	{ "trigger_output_event_mask", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "trigger_input_eventt_mask", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_interrupt_test_reg[] = {
+	{ "trigger_pps_in_event_test", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0 },
+	{ "trigger_fifo_almost_full_event_test", DPP_FIELD_FLAG_RW, 3, 1, 0x0,
+	  0x0 },
+	{ "trigger_fifo_no_empty_event_test", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0 },
+	{ "trigger_output_event_test", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "trigger_input_event_test", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_hw_clock_cycle_integer_reg[] = {
+	{ "integeral_nanosecond_of_hw_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1,
+	  0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_hw_clock_cycle_fraction_reg[] = {
+	{ "fractional_nanosecond_of_hw_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_ptp_clock_cycle_integer_reg[] = {
+	{ "integeral_nanosecond_of_ptp_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1,
+	  0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_ptp_clock_cycle_fraction_reg[] = {
+	{ "fractional_nanosecond_of_ptp_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_ptp_configuration_reg[] = {
+	{ "trig_oe", DPP_FIELD_FLAG_RW, 18, 1, 0x0, 0x0 },
+	{ "hw_time_update_en", DPP_FIELD_FLAG_RW, 17, 1, 0x0, 0x0 },
+	{ "ptp1588_tod_time_update_en", DPP_FIELD_FLAG_RW, 16, 1, 0x0, 0x0 },
+	{ "timer_enable", DPP_FIELD_FLAG_RW, 15, 1, 0x0, 0x0 },
+	{ "pps_output_enable", DPP_FIELD_FLAG_RW, 14, 1, 0x1, 0x0 },
+	{ "pp1_output_enable", DPP_FIELD_FLAG_RW, 13, 1, 0x0, 0x0 },
+	{ "pp2_output_enable", DPP_FIELD_FLAG_RW, 12, 1, 0x0, 0x0 },
+	{ "enable_writing_timestamps_to_the_fifo", DPP_FIELD_FLAG_RW, 11, 1, 0x0,
+	  0x0 },
+	{ "l2s_time_output_select", DPP_FIELD_FLAG_RW, 10, 1, 0x0, 0x0 },
+	{ "reserved_9", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0 },
+	{ "pps_input_select", DPP_FIELD_FLAG_RW, 8, 1, 0x0, 0x0 },
+	{ "pp_output_select", DPP_FIELD_FLAG_RW, 7, 1, 0x0, 0x0 },
+	{ "reserved_6", DPP_FIELD_FLAG_RO, 6, 1, 0x0, 0x0 },
+	{ "timer_run_mode", DPP_FIELD_FLAG_RW, 5, 2, 0x0, 0x0 },
+	{ "update_command_select", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0 },
+	{ "trigger_out_enable", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0 },
+	{ "trigger_in_enable", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "timer_capture_slave_mode", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_timer_control_reg[] = {
+	{ "ptpmoutputsynchroningstate", DPP_FIELD_FLAG_RO, 3, 1, 0x0, 0x0 },
+	{ "ptp1588_fifo_read_command", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0 },
+	{ "adjust_the_timer", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pps_income_delay_reg[] = {
+	{ "pps_income_delay_nanosecond", DPP_FIELD_FLAG_RW, 31, 16, 0x0, 0x0 },
+	{ "pps_income_delay_frac_nanosecond", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_clock_cycle_update_reg[] = {
+	{ "tsn3_clock_cycle_update_enable", DPP_FIELD_FLAG_RW, 4, 1, 0x0, 0x0 },
+	{ "tsn2_clock_cycle_update_enable", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0 },
+	{ "tsn1_clock_cycle_update_enable", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0 },
+	{ "tsn0_clock_cycle_update_enable", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "ptp1588_clock_cycle_update_enable", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_cycle_time_of_output_period_pulse_1_reg[] = {
+	{ "clock_number_of_output_period_pulse_1", DPP_FIELD_FLAG_RW, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_cycle_time_of_output_period_pulse_2_reg[] = {
+	{ "clock_number_of_output_period_pulse_2", DPP_FIELD_FLAG_RW, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_timer_latch_en_reg[] = {
+	{ "latch_the_timer_en", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_timer_latch_sel_reg[] = {
+	{ "timer_latch_sel", DPP_FIELD_FLAG_RW, 5, 6, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_trigger_in_tod_nanosecond_reg[] = {
+	{ "trigger_in_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_trigger_in_lower_tod_second_reg[] = {
+	{ "trigger_in_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_trigger_in_high_tod_second_reg[] = {
+	{ "trigger_in_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_trigger_in_fracnanosecond_reg[] = {
+	{ "trigger_in_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_trigger_in_hardware_time_low_reg[] = {
+	{ "trigger_in_hardware_time_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_trigger_in_hardware_time_high_reg[] = {
+	{ "trigger_in_hardware_time_high", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_trigger_out_tod_nanosecond_reg[] = {
+	{ "trigger_out_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_trigger_out_lower_tod_second_reg[] = {
+	{ "trigger_out_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_trigger_out_high_tod_second_reg[] = {
+	{ "trigger_out_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_trigger_out_hardware_time_low_reg[] = {
+	{ "trigger_out_hardware_time_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_trigger_out_hardware_time_high_reg[] = {
+	{ "trigger_out_hardware_time_high", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_adjust_tod_nanosecond_reg[] = {
+	{ "adjust_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_adjust_lower_tod_second_reg[] = {
+	{ "adjust_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_adjust_high_tod_second_reg[] = {
+	{ "adjust_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_adjust_fracnanosecond_reg[] = {
+	{ "adjust_fracnanosecond", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_adjust_hardware_time_low_reg[] = {
+	{ "adjust_hardware_time_low", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_adjust_hardware_time_high_reg[] = {
+	{ "adjust_hardware_time_high", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_latch_tod_nanosecond_reg[] = {
+	{ "latch_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_latch_lower_tod_second_reg[] = {
+	{ "latch_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_latch_high_tod_second_reg[] = {
+	{ "latch_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_latch_fracnanosecond_reg[] = {
+	{ "latch_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_latch_hardware_time_low_reg[] = {
+	{ "latch_hardware_time_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_latch_hardware_time_high_reg[] = {
+	{ "latch_hardware_time_high", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_real_tod_nanosecond_reg[] = {
+	{ "real_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_real_lower_tod_second_reg[] = {
+	{ "real_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_real_high_tod_second_reg[] = {
+	{ "real_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_real_hardware_time_low_reg[] = {
+	{ "real_hardware_time_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_real_hardware_time_high_reg[] = {
+	{ "real_hardware_time_high", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_ptp1588_event_message_port_reg[] = {
+	{ "ptp1588_event_message_port", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_ptp1588_event_message_timestamp_low_reg[] = {
+	{ "ptp1588_event_message_timestamp_low", DPP_FIELD_FLAG_RO, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_ptp1588_event_message_timestamp_high_reg[] = {
+	{ "ptp1588_event_message_timestamp_high", DPP_FIELD_FLAG_RO, 31, 32, 0x0,
+	  0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_ptp1588_event_message_fifo_status_reg[] = {
+	{ "fifo_full", DPP_FIELD_FLAG_RO, 9, 1, 0x0, 0x0 },
+	{ "fifo_empty", DPP_FIELD_FLAG_RO, 8, 1, 0x1, 0x0 },
+	{ "timestamps_count", DPP_FIELD_FLAG_RO, 7, 8, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tod_nanosecond_reg[] = {
+	{ "latch_1588tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_lower_tod_second_reg[] = {
+	{ "latch_lower_1588tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_high_tod_second_reg[] = {
+	{ "latch_high_1588tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_fracnanosecond_reg[] = {
+	{ "latch_1588fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn_time_configuration_reg[] = {
+	{ "tsn_pps_enable", DPP_FIELD_FLAG_RW, 19, 4, 0x0, 0x0 },
+	{ "tsn_timer_enable", DPP_FIELD_FLAG_RW, 15, 4, 0x0, 0x0 },
+	{ "tsn_timer_run_mode", DPP_FIELD_FLAG_RW, 11, 8, 0x0, 0x0 },
+	{ "timer_capture_slave_mode", DPP_FIELD_FLAG_RW, 3, 4, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn_timer_control_reg[] = {
+	{ "adjust_the_tsn3_timer", DPP_FIELD_FLAG_RW, 3, 1, 0x0, 0x0 },
+	{ "adjust_the_tsn2_timer", DPP_FIELD_FLAG_RW, 2, 1, 0x0, 0x0 },
+	{ "adjust_the_tsn1_timer", DPP_FIELD_FLAG_RW, 1, 1, 0x0, 0x0 },
+	{ "adjust_the_tsn0_timer", DPP_FIELD_FLAG_RW, 0, 1, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn0_clock_cycle_integer_reg[] = {
+	{ "integeral_nanosecond_of_tsn0_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1,
+	  0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn0_clock_cycle_fraction_reg[] = {
+	{ "fractional_nanosecond_of_tsn0_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn1_clock_cycle_integer_reg[] = {
+	{ "integeral_nanosecond_of_tsn1_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1,
+	  0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn1_clock_cycle_fraction_reg[] = {
+	{ "fractional_nanosecond_of_tsn1_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn2_clock_cycle_integer_reg[] = {
+	{ "integeral_nanosecond_of_tsn2_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1,
+	  0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn2_clock_cycle_fraction_reg[] = {
+	{ "fractional_nanosecond_of_tsn2_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn3_clock_cycle_integer_reg[] = {
+	{ "integeral_nanosecond_of_tsn3_clock_cycle", DPP_FIELD_FLAG_RW, 7, 8, 0x1,
+	  0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn3_clock_cycle_fraction_reg[] = {
+	{ "fractional_nanosecond_of_tsn3_clock_cycle", DPP_FIELD_FLAG_RW, 31, 32,
+	  0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn0_adjust_tod_nanosecond_reg[] = {
+	{ "tsn0_adjust_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn0_adjust_lower_tod_second_reg[] = {
+	{ "tsn0_adjust_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn0_adjust_high_tod_second_reg[] = {
+	{ "tsn0_adjust_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn0_adjust_fracnanosecond_reg[] = {
+	{ "tsn0_adjust_fracnanosecond", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn1_adjust_tod_nanosecond_reg[] = {
+	{ "tsn1_adjust_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn1_adjust_lower_tod_second_reg[] = {
+	{ "tsn1_adjust_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn1_adjust_high_tod_second_reg[] = {
+	{ "tsn1_adjust_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn1_adjust_fracnanosecond_reg[] = {
+	{ "tsn1_adjust_fracnanosecond", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn2_adjust_tod_nanosecond_reg[] = {
+	{ "tsn2_adjust_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn2_adjust_lower_tod_second_reg[] = {
+	{ "tsn2_adjust_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn2_adjust_high_tod_second_reg[] = {
+	{ "tsn2_adjust_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn2_adjust_fracnanosecond_reg[] = {
+	{ "tsn2_adjust_fracnanosecond", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn3_adjust_tod_nanosecond_reg[] = {
+	{ "tsn3_adjust_tod_nanosecond", DPP_FIELD_FLAG_RW, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn3_adjust_lower_tod_second_reg[] = {
+	{ "tsn3_adjust_lower_tod_second", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn3_adjust_high_tod_second_reg[] = {
+	{ "tsn3_adjust_high_tod_second", DPP_FIELD_FLAG_RW, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn3_adjust_fracnanosecond_reg[] = {
+	{ "tsn3_adjust_fracnanosecond", DPP_FIELD_FLAG_RW, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn0_latch_tod_nanosecond_reg[] = {
+	{ "tsn0_latch_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn0_latch_lower_tod_second_reg[] = {
+	{ "tsn0_latch_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn0_latch_high_tod_second_reg[] = {
+	{ "tsn0_latch_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn0_latch_fracnanosecond_reg[] = {
+	{ "tsn0_latch_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn1_latch_tod_nanosecond_reg[] = {
+	{ "tsn1_latch_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn1_latch_lower_tod_second_reg[] = {
+	{ "tsn1_latch_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn1_latch_high_tod_second_reg[] = {
+	{ "tsn1_latch_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn1_latch_fracnanosecond_reg[] = {
+	{ "tsn1_latch_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn2_latch_tod_nanosecond_reg[] = {
+	{ "tsn2_latch_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn2_latch_lower_tod_second_reg[] = {
+	{ "tsn2_latch_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn2_latch_high_tod_second_reg[] = {
+	{ "tsn2_latch_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn2_latch_fracnanosecond_reg[] = {
+	{ "tsn2_latch_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn3_latch_tod_nanosecond_reg[] = {
+	{ "tsn3_latch_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn3_latch_lower_tod_second_reg[] = {
+	{ "tsn3_latch_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn3_latch_high_tod_second_reg[] = {
+	{ "tsn3_latch_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn3_latch_fracnanosecond_reg[] = {
+	{ "tsn3_latch_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn0_tod_nanosecond_reg[] = {
+	{ "latch_tsn0_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn0_lower_tod_second_reg[] = {
+	{ "latch_lower_tsn0_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn0_high_tod_second_reg[] = {
+	{ "latch_high_tsn0_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn0_fracnanosecond_reg[] = {
+	{ "latch_tsn0_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn1_tod_nanosecond_reg[] = {
+	{ "latch_tsn1_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn1_lower_tod_second_reg[] = {
+	{ "latch_lower_tsn1_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn1_high_tod_second_reg[] = {
+	{ "latch_high_tsn1_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn1_fracnanosecond_reg[] = {
+	{ "latch_tsn1_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn2_tod_nanosecond_reg[] = {
+	{ "latch_tsn2_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn2_lower_tod_second_reg[] = {
+	{ "latch_lower_tsn2_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn2_high_tod_second_reg[] = {
+	{ "latch_high_tsn2_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn2_fracnanosecond_reg[] = {
+	{ "latch_tsn2_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn3_tod_nanosecond_reg[] = {
+	{ "latch_tsn3_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn3_lower_tod_second_reg[] = {
+	{ "latch_lower_tsn3_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn3_high_tod_second_reg[] = {
+	{ "latch_high_tsn3_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_pp1s_latch_tsn3_fracnanosecond_reg[] = {
+	{ "latch_tsn3_fracnanosecond", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn0_real_tod_nanosecond_reg[] = {
+	{ "tsn0_real_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn0_real_lower_tod_second_reg[] = {
+	{ "tsn0_real_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn0_real_high_tod_second_reg[] = {
+	{ "tsn0_real_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn1_real_tod_nanosecond_reg[] = {
+	{ "tsn1_real_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn1_real_lower_tod_second_reg[] = {
+	{ "tsn1_real_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn1_real_high_tod_second_reg[] = {
+	{ "tsn1_real_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn2_real_tod_nanosecond_reg[] = {
+	{ "tsn2_real_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn2_real_lower_tod_second_reg[] = {
+	{ "tsn2_real_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn2_real_high_tod_second_reg[] = {
+	{ "tsn2_real_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn3_real_tod_nanosecond_reg[] = {
+	{ "tsn3_real_tod_nanosecond", DPP_FIELD_FLAG_RO, 29, 30, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn3_real_lower_tod_second_reg[] = {
+	{ "tsn3_real_lower_tod_second", DPP_FIELD_FLAG_RO, 31, 32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_tsn3_real_high_tod_second_reg[] = {
+	{ "tsn3_real_high_tod_second", DPP_FIELD_FLAG_RO, 15, 16, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_real_ptp_clock_cycle_integer_reg[] = {
+	{ "integeral_nanosecond_of_real_ptp_clock_cycle", DPP_FIELD_FLAG_RO, 7, 8,
+	  0x1, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_real_ptp_clock_cycle_fraction_reg[] = {
+	{ "fractional_nanosecond_of_real_ptp_clock_cycle", DPP_FIELD_FLAG_RO, 31,
+	  32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_real_tsn0_clock_cycle_integer_reg[] = {
+	{ "integeral_nanosecond_of_real_tsn0_clock_cycle", DPP_FIELD_FLAG_RO, 7, 8,
+	  0x1, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_real_tsn0_clock_cycle_fraction_reg[] = {
+	{ "fractional_nanosecond_of_real_tsn0_clock_cycle", DPP_FIELD_FLAG_RO, 31,
+	  32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_real_tsn1_clock_cycle_integer_reg[] = {
+	{ "integeral_nanosecond_of_real_tsn1_clock_cycle", DPP_FIELD_FLAG_RO, 7, 8,
+	  0x1, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_real_tsn1_clock_cycle_fraction_reg[] = {
+	{ "fractional_nanosecond_of_real_tsn1_clock_cycle", DPP_FIELD_FLAG_RO, 31,
+	  32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_real_tsn2_clock_cycle_integer_reg[] = {
+	{ "integeral_nanosecond_of_real_tsn2_clock_cycle", DPP_FIELD_FLAG_RO, 7, 8,
+	  0x1, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_real_tsn2_clock_cycle_fraction_reg[] = {
+	{ "fractional_nanosecond_of_real_tsn2_clock_cycle", DPP_FIELD_FLAG_RO, 31,
+	  32, 0x0, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_real_tsn3_clock_cycle_integer_reg[] = {
+	{ "integeral_nanosecond_of_real_tsn3_clock_cycle", DPP_FIELD_FLAG_RO, 7, 8,
+	  0x1, 0x0 },
+};
+DPP_FIELD_T g_ptptm_ptptm_real_tsn3_clock_cycle_fraction_reg[] = {
+	{ "fractional_nanosecond_of_real_tsn3_clock_cycle", DPP_FIELD_FLAG_RO, 31,
+	  32, 0x0, 0x0 },
+};
+DPP_REG_T g_dpp_reg_info[] = {
+	{
+			"cpu_check_reg",
+			ETM_CFGMT_CPU_CHECK_REGr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x60,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cfgmt_cpu_check_reg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_blksize",
+			ETM_CFGMT_CFGMT_BLKSIZEr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x70,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cfgmt_cfgmt_blksize_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"reg_int_state_reg",
+			ETM_CFGMT_REG_INT_STATE_REGr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x90,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			7,
+			g_etm_cfgmt_reg_int_state_reg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"reg_int_mask_reg",
+			ETM_CFGMT_REG_INT_MASK_REGr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xa0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			7,
+			g_etm_cfgmt_reg_int_mask_reg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"timeout_limit",
+			ETM_CFGMT_TIMEOUT_LIMITr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xb0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cfgmt_timeout_limit_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"subsystem_rdy_reg",
+			ETM_CFGMT_SUBSYSTEM_RDY_REGr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xc0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_etm_cfgmt_subsystem_rdy_reg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"subsystem_en_reg",
+			ETM_CFGMT_SUBSYSTEM_EN_REGr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xd0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_cfgmt_subsystem_en_reg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_int_reg",
+			ETM_CFGMT_CFGMT_INT_REGr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cfgmt_cfgmt_int_reg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_work_mode",
+			ETM_CFGMT_QMU_WORK_MODEr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x100,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cfgmt_qmu_work_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_ddr_attach",
+			ETM_CFGMT_CFGMT_DDR_ATTACHr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x120,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cfgmt_cfgmt_ddr_attach_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_mode_reg",
+			ETM_CFGMT_CNT_MODE_REGr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x140,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_etm_cfgmt_cnt_mode_reg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"clkgate_en",
+			ETM_CFGMT_CLKGATE_ENr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cfgmt_clkgate_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"softrst_en",
+			ETM_CFGMT_SOFTRST_ENr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cfgmt_softrst_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"imem_prog_full",
+			ETM_OLIF_IMEM_PROG_FULLr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_olif_imem_prog_full_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_para_prog_full",
+			ETM_OLIF_QMU_PARA_PROG_FULLr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_olif_qmu_para_prog_full_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"olif_int_mask",
+			ETM_OLIF_OLIF_INT_MASKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			19,
+			g_etm_olif_olif_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"itmhram_parity_err_2_int",
+			ETM_OLIF_ITMHRAM_PARITY_ERR_2_INTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x9,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			22,
+			g_etm_olif_itmhram_parity_err_2_int_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lif0_port_rdy_mask_h",
+			ETM_OLIF_LIF0_PORT_RDY_MASK_Hr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x30,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_lif0_port_rdy_mask_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lif0_port_rdy_mask_l",
+			ETM_OLIF_LIF0_PORT_RDY_MASK_Lr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x31,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_lif0_port_rdy_mask_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lif0_port_rdy_cfg_h",
+			ETM_OLIF_LIF0_PORT_RDY_CFG_Hr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x32,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_lif0_port_rdy_cfg_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lif0_port_rdy_cfg_l",
+			ETM_OLIF_LIF0_PORT_RDY_CFG_Lr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x33,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_lif0_port_rdy_cfg_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lif0_link_rdy_mask_cfg",
+			ETM_OLIF_LIF0_LINK_RDY_MASK_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x34,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_olif_lif0_link_rdy_mask_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_lif_stat_cfg",
+			ETM_OLIF_TM_LIF_STAT_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x40,
+			(32 / 8),
+			0,
+			0xf + 1,
+			0,
+			0x1,
+			4,
+			g_etm_olif_tm_lif_stat_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_lif_sop_stat",
+			ETM_OLIF_TM_LIF_SOP_STATr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x50,
+			(32 / 8),
+			0,
+			0xf + 1,
+			0,
+			0x1,
+			1,
+			g_etm_olif_tm_lif_sop_stat_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_lif_eop_stat",
+			ETM_OLIF_TM_LIF_EOP_STATr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x60,
+			(32 / 8),
+			0,
+			0xf + 1,
+			0,
+			0x1,
+			1,
+			g_etm_olif_tm_lif_eop_stat_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_lif_vld_stat",
+			ETM_OLIF_TM_LIF_VLD_STATr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x80,
+			(32 / 8),
+			0,
+			0xf + 1,
+			0,
+			0x1,
+			1,
+			g_etm_olif_tm_lif_vld_stat_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"prog_full_assert_cfg",
+			ETM_CGAVD_PROG_FULL_ASSERT_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_cgavd_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_int",
+			ETM_CGAVD_CGAVD_INTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_int_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_ram_err",
+			ETM_CGAVD_CGAVD_RAM_ERRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x3,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			13,
+			g_etm_cgavd_cgavd_ram_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_int_mask",
+			ETM_CGAVD_CGAVD_INT_MASKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_ram_err_int_mask",
+			ETM_CGAVD_CGAVD_RAM_ERR_INT_MASKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x5,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			13,
+			g_etm_cgavd_cgavd_ram_err_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_byte_mode",
+			ETM_CGAVD_CFGMT_BYTE_MODEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x6,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cfgmt_byte_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"avg_qlen_return_zero_en",
+			ETM_CGAVD_AVG_QLEN_RETURN_ZERO_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x7,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_avg_qlen_return_zero_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_wred_q_len_th",
+			ETM_CGAVD_FLOW_WRED_Q_LEN_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x20,
+			(32 / 8),
+			0,
+			0x1f + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_flow_wred_q_len_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_wq",
+			ETM_CGAVD_FLOW_WQr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x40,
+			(32 / 8),
+			0,
+			0x1f + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_flow_wq_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_wred_max_th",
+			ETM_CGAVD_FLOW_WRED_MAX_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x100,
+			(32 / 8),
+			0,
+			0xff + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_flow_wred_max_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_wred_min_th",
+			ETM_CGAVD_FLOW_WRED_MIN_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x200,
+			(32 / 8),
+			0,
+			0xff + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_flow_wred_min_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_wred_cfg_para",
+			ETM_CGAVD_FLOW_WRED_CFG_PARAr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x300,
+			(32 / 8),
+			0,
+			0xff + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_flow_wred_cfg_para_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_avg_q_len",
+			ETM_CGAVD_PP_AVG_Q_LENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x400,
+			(32 / 8),
+			0,
+			0x7f + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_pp_avg_q_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_td_th",
+			ETM_CGAVD_PP_TD_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x600,
+			(32 / 8),
+			0,
+			0x7f + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_pp_td_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_ca_mtd",
+			ETM_CGAVD_PP_CA_MTDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x800,
+			(32 / 8),
+			0,
+			0x7f + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_pp_ca_mtd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_wred_grp_th_en",
+			ETM_CGAVD_PP_WRED_GRP_TH_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0xc00,
+			(32 / 8),
+			0,
+			0x7f + 1,
+			0,
+			0x1,
+			2,
+			g_etm_cgavd_pp_wred_grp_th_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_wred_q_len_th",
+			ETM_CGAVD_PP_WRED_Q_LEN_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0xe00,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_pp_wred_q_len_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_wq",
+			ETM_CGAVD_PP_WQr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0xe08,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_pp_wq_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_wred_max_th",
+			ETM_CGAVD_PP_WRED_MAX_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x1000,
+			(32 / 8),
+			0,
+			0x3f + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_pp_wred_max_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_wred_min_th",
+			ETM_CGAVD_PP_WRED_MIN_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x1080,
+			(32 / 8),
+			0,
+			0x3f + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_pp_wred_min_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_cfg_para",
+			ETM_CGAVD_PP_CFG_PARAr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x1100,
+			(32 / 8),
+			0,
+			0x3f + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_pp_cfg_para_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sys_avg_q_len",
+			ETM_CGAVD_SYS_AVG_Q_LENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1200,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_sys_avg_q_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sys_td_th",
+			ETM_CGAVD_SYS_TD_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1202,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_sys_td_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sys_cgavd_metd",
+			ETM_CGAVD_SYS_CGAVD_METDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1204,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_sys_cgavd_metd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sys_cfg_q_grp_para",
+			ETM_CGAVD_SYS_CFG_Q_GRP_PARAr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1208,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_sys_cfg_q_grp_para_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sys_wq",
+			ETM_CGAVD_SYS_WQr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1210,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_sys_wq_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"gred_max_th",
+			ETM_CGAVD_GRED_MAX_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x1218,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_gred_max_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"gred_mid_th",
+			ETM_CGAVD_GRED_MID_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x1228,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_gred_mid_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"gred_min_th",
+			ETM_CGAVD_GRED_MIN_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x1238,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_gred_min_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"gred_cfg_para0",
+			ETM_CGAVD_GRED_CFG_PARA0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x1248,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_gred_cfg_para0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"gred_cfg_para1",
+			ETM_CGAVD_GRED_CFG_PARA1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x1258,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_gred_cfg_para1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"gred_cfg_para2",
+			ETM_CGAVD_GRED_CFG_PARA2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x1268,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_gred_cfg_para2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sys_window_th_h",
+			ETM_CGAVD_SYS_WINDOW_TH_Hr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1278,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_sys_window_th_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sys_window_th_l",
+			ETM_CGAVD_SYS_WINDOW_TH_Lr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x127a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_sys_window_th_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"amplify_gene0",
+			ETM_CGAVD_AMPLIFY_GENE0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x127c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_amplify_gene0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"amplify_gene1",
+			ETM_CGAVD_AMPLIFY_GENE1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x127d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_amplify_gene1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"amplify_gene2",
+			ETM_CGAVD_AMPLIFY_GENE2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x127e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_amplify_gene2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"amplify_gene3",
+			ETM_CGAVD_AMPLIFY_GENE3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x127f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_amplify_gene3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"amplify_gene4",
+			ETM_CGAVD_AMPLIFY_GENE4r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1280,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_amplify_gene4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"amplify_gene5",
+			ETM_CGAVD_AMPLIFY_GENE5r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1281,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_amplify_gene5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"amplify_gene6",
+			ETM_CGAVD_AMPLIFY_GENE6r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1282,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_amplify_gene6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"amplify_gene7",
+			ETM_CGAVD_AMPLIFY_GENE7r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1283,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_amplify_gene7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"amplify_gene8",
+			ETM_CGAVD_AMPLIFY_GENE8r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1284,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_amplify_gene8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"amplify_gene9",
+			ETM_CGAVD_AMPLIFY_GENE9r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1285,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_amplify_gene9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"amplify_gene10",
+			ETM_CGAVD_AMPLIFY_GENE10r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1286,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_amplify_gene10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"amplify_gene11",
+			ETM_CGAVD_AMPLIFY_GENE11r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1287,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_amplify_gene11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"amplify_gene12",
+			ETM_CGAVD_AMPLIFY_GENE12r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1288,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_amplify_gene12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"amplify_gene13",
+			ETM_CGAVD_AMPLIFY_GENE13r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1289,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_amplify_gene13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"amplify_gene14",
+			ETM_CGAVD_AMPLIFY_GENE14r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x128a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_amplify_gene14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"amplify_gene15",
+			ETM_CGAVD_AMPLIFY_GENE15r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x128b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_amplify_gene15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"equal_pkt_len_en",
+			ETM_CGAVD_EQUAL_PKT_LEN_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x128c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_equal_pkt_len_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"equal_pkt_len_th0",
+			ETM_CGAVD_EQUAL_PKT_LEN_TH0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x128d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_equal_pkt_len_th0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"equal_pkt_len_th1",
+			ETM_CGAVD_EQUAL_PKT_LEN_TH1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x128e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_equal_pkt_len_th1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"equal_pkt_len_th2",
+			ETM_CGAVD_EQUAL_PKT_LEN_TH2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x128f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_equal_pkt_len_th2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"equal_pkt_len_th3",
+			ETM_CGAVD_EQUAL_PKT_LEN_TH3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1290,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_equal_pkt_len_th3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"equal_pkt_len_th4",
+			ETM_CGAVD_EQUAL_PKT_LEN_TH4r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1291,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_equal_pkt_len_th4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"equal_pkt_len_th5",
+			ETM_CGAVD_EQUAL_PKT_LEN_TH5r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1292,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_equal_pkt_len_th5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"equal_pkt_len_th6",
+			ETM_CGAVD_EQUAL_PKT_LEN_TH6r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1293,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_equal_pkt_len_th6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"equal_pkt_len0",
+			ETM_CGAVD_EQUAL_PKT_LEN0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1294,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_equal_pkt_len0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"equal_pkt_len1",
+			ETM_CGAVD_EQUAL_PKT_LEN1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1295,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_equal_pkt_len1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"equal_pkt_len2",
+			ETM_CGAVD_EQUAL_PKT_LEN2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1296,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_equal_pkt_len2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"equal_pkt_len3",
+			ETM_CGAVD_EQUAL_PKT_LEN3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1297,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_equal_pkt_len3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"equal_pkt_len4",
+			ETM_CGAVD_EQUAL_PKT_LEN4r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1298,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_equal_pkt_len4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"equal_pkt_len5",
+			ETM_CGAVD_EQUAL_PKT_LEN5r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1299,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_equal_pkt_len5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"equal_pkt_len6",
+			ETM_CGAVD_EQUAL_PKT_LEN6r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x129a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_equal_pkt_len6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"equal_pkt_len7",
+			ETM_CGAVD_EQUAL_PKT_LEN7r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x129b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_equal_pkt_len7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_cpu_set_avg_len",
+			ETM_CGAVD_FLOW_CPU_SET_AVG_LENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x129c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow_cpu_set_avg_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_cpu_set_q_len",
+			ETM_CGAVD_FLOW_CPU_SET_Q_LENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x129d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow_cpu_set_q_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_cpu_set_avg_q_len",
+			ETM_CGAVD_PP_CPU_SET_AVG_Q_LENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12ef,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_pp_cpu_set_avg_q_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_cpu_set_q_len",
+			ETM_CGAVD_PP_CPU_SET_Q_LENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x129e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_pp_cpu_set_q_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sys_cpu_set_avg_len",
+			ETM_CGAVD_SYS_CPU_SET_AVG_LENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_sys_cpu_set_avg_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sys_cpu_set_q_len",
+			ETM_CGAVD_SYS_CPU_SET_Q_LENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12a2,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_sys_cpu_set_q_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pke_len_calc_sign",
+			ETM_CGAVD_PKE_LEN_CALC_SIGNr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12a3,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_pke_len_calc_sign_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rd_cpu_or_ram",
+			ETM_CGAVD_RD_CPU_OR_RAMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_etm_cgavd_rd_cpu_or_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"q_len_update_disable",
+			ETM_CGAVD_Q_LEN_UPDATE_DISABLEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12a5,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_etm_cgavd_q_len_update_disable_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_dp_sel",
+			ETM_CGAVD_CGAVD_DP_SELr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12ad,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			9,
+			g_etm_cgavd_cgavd_dp_sel_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_sub_en",
+			ETM_CGAVD_CGAVD_SUB_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12e6,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_etm_cgavd_cgavd_sub_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"default_start_queue",
+			ETM_CGAVD_DEFAULT_START_QUEUEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12e7,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_default_start_queue_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"default_finish_queue",
+			ETM_CGAVD_DEFAULT_FINISH_QUEUEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_default_finish_queue_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"protocol_start_queue",
+			ETM_CGAVD_PROTOCOL_START_QUEUEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12e9,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_protocol_start_queue_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"protocol_finish_queue",
+			ETM_CGAVD_PROTOCOL_FINISH_QUEUEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12ea,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_protocol_finish_queue_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"uniform_td_th",
+			ETM_CGAVD_UNIFORM_TD_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12eb,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_uniform_td_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"uniform_td_th_en",
+			ETM_CGAVD_UNIFORM_TD_TH_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_uniform_td_th_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_cfg_fc",
+			ETM_CGAVD_CGAVD_CFG_FCr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12ed,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_cfg_fc_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_cfg_no_fc",
+			ETM_CGAVD_CGAVD_CFG_NO_FCr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12ee,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_cfg_no_fc_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_force_imem_omem",
+			ETM_CGAVD_CGAVD_FORCE_IMEM_OMEMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_cgavd_cgavd_force_imem_omem_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_sys_q_len_l",
+			ETM_CGAVD_CGAVD_SYS_Q_LEN_Lr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12f1,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_sys_q_len_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"default_queue_en",
+			ETM_CGAVD_DEFAULT_QUEUE_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12f5,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_default_queue_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"protocol_queue_en",
+			ETM_CGAVD_PROTOCOL_QUEUE_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12f6,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_protocol_queue_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tc_flowid_dat",
+			ETM_CGAVD_CFG_TC_FLOWID_DATr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x1400,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_cfg_tc_flowid_dat_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_td_th",
+			ETM_CGAVD_FLOW_TD_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x40000,
+			(32 / 8),
+			0,
+			0x23FF + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_flow_td_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_ca_mtd",
+			ETM_CGAVD_FLOW_CA_MTDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x80000,
+			(32 / 8),
+			0,
+			0x23FF + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_flow_ca_mtd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_dynamic_th_en",
+			ETM_CGAVD_FLOW_DYNAMIC_TH_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0xc0000,
+			(32 / 8),
+			0,
+			0x23FF + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_flow_dynamic_th_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_num",
+			ETM_CGAVD_PP_NUMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x100000,
+			(32 / 8),
+			0,
+			0x23FF + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_pp_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_q_len",
+			ETM_CGAVD_FLOW_Q_LENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x140000,
+			(32 / 8),
+			0,
+			0x23FF + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_flow_q_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_wred_grp",
+			ETM_CGAVD_FLOW_WRED_GRPr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x180000,
+			(32 / 8),
+			0,
+			0x23FF + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_flow_wred_grp_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_avg_q_len",
+			ETM_CGAVD_FLOW_AVG_Q_LENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x1c0000,
+			(32 / 8),
+			0,
+			0x23FF + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_flow_avg_q_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qos_sign",
+			ETM_CGAVD_QOS_SIGNr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x200000,
+			(32 / 8),
+			0,
+			0x23FF + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_qos_sign_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"q_pri",
+			ETM_CGAVD_Q_PRIr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x240000,
+			(32 / 8),
+			0,
+			0x23FF + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_q_pri_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_tm_itmd_rd_low",
+			ETM_CGAVD_ODMA_TM_ITMD_RD_LOWr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x250000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_odma_tm_itmd_rd_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_tm_itmd_rd_mid",
+			ETM_CGAVD_ODMA_TM_ITMD_RD_MIDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x250001,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_odma_tm_itmd_rd_mid_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_tm_itmd_rd_high",
+			ETM_CGAVD_ODMA_TM_ITMD_RD_HIGHr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x250002,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_odma_tm_itmd_rd_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_stat_pkt_len",
+			ETM_CGAVD_CGAVD_STAT_PKT_LENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x250003,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_cgavd_cgavd_stat_pkt_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_stat_qnum",
+			ETM_CGAVD_CGAVD_STAT_QNUMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x250004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_cgavd_cgavd_stat_qnum_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_stat_dp",
+			ETM_CGAVD_CGAVD_STAT_DPr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x250005,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_stat_dp_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_num0",
+			ETM_CGAVD_FLOW_NUM0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow_num0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_num1",
+			ETM_CGAVD_FLOW_NUM1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260001,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow_num1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_num2",
+			ETM_CGAVD_FLOW_NUM2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260002,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow_num2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_num3",
+			ETM_CGAVD_FLOW_NUM3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260003,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow_num3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_num4",
+			ETM_CGAVD_FLOW_NUM4r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow_num4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow0_imem_cnt",
+			ETM_CGAVD_FLOW0_IMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow0_imem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow1_imem_cnt",
+			ETM_CGAVD_FLOW1_IMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260011,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow1_imem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow2_imem_cnt",
+			ETM_CGAVD_FLOW2_IMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260012,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow2_imem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow3_imem_cnt",
+			ETM_CGAVD_FLOW3_IMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260013,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow3_imem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow4_imem_cnt",
+			ETM_CGAVD_FLOW4_IMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow4_imem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow0_drop_cnt",
+			ETM_CGAVD_FLOW0_DROP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow0_drop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow1_drop_cnt",
+			ETM_CGAVD_FLOW1_DROP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260031,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow1_drop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow2_drop_cnt",
+			ETM_CGAVD_FLOW2_DROP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260032,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow2_drop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow3_drop_cnt",
+			ETM_CGAVD_FLOW3_DROP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260033,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow3_drop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow4_drop_cnt",
+			ETM_CGAVD_FLOW4_DROP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow4_drop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fc_count_mode",
+			ETM_CGAVD_FC_COUNT_MODEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x264000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_fc_count_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_cgavd_fc_num",
+			ETM_CGAVD_QMU_CGAVD_FC_NUMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x264100,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_cgavd_qmu_cgavd_fc_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_odma_fc_num",
+			ETM_CGAVD_CGAVD_ODMA_FC_NUMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x264101,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_cgavd_cgavd_odma_fc_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_offset",
+			ETM_CGAVD_CFG_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x290000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cfg_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_init_done",
+			ETM_TMMU_TMMU_INIT_DONEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0001,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_init_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_int_mask_1",
+			ETM_TMMU_TMMU_INT_MASK_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x002,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			27,
+			g_etm_tmmu_tmmu_int_mask_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_int_mask_2",
+			ETM_TMMU_TMMU_INT_MASK_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0003,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			17,
+			g_etm_tmmu_tmmu_int_mask_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_tm_pure_imem_en",
+			ETM_TMMU_CFGMT_TM_PURE_IMEM_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_tm_pure_imem_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_force_ddr_rdy_cfg",
+			ETM_TMMU_CFGMT_FORCE_DDR_RDY_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0005,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_force_ddr_rdy_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pd_order_fifo_aful_th",
+			ETM_TMMU_PD_ORDER_FIFO_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0007,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_pd_order_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cached_pd_fifo_aful_th",
+			ETM_TMMU_CACHED_PD_FIFO_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cached_pd_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"wr_cmd_fifo_aful_th",
+			ETM_TMMU_WR_CMD_FIFO_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_wr_cmd_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"imem_enq_rd_fifo_aful_th",
+			ETM_TMMU_IMEM_ENQ_RD_FIFO_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_imem_enq_rd_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"imem_enq_drop_fifo_aful_th",
+			ETM_TMMU_IMEM_ENQ_DROP_FIFO_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_imem_enq_drop_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"imem_deq_drop_fifo_aful_th",
+			ETM_TMMU_IMEM_DEQ_DROP_FIFO_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_imem_deq_drop_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"imem_deq_rd_fifo_aful_th",
+			ETM_TMMU_IMEM_DEQ_RD_FIFO_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_imem_deq_rd_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_states_1",
+			ETM_TMMU_TMMU_STATES_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0011,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			27,
+			g_etm_tmmu_tmmu_states_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_states_2",
+			ETM_TMMU_TMMU_STATES_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0012,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			17,
+			g_etm_tmmu_tmmu_states_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"shap_ind_cmd",
+			ETM_SHAP_SHAP_IND_CMDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_etm_shap_shap_ind_cmd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"shap_ind_sta",
+			ETM_SHAP_SHAP_IND_STAr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_shap_ind_sta_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"shap_ind_data0",
+			ETM_SHAP_SHAP_IND_DATA0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_shap_ind_data0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"shap_ind_data1",
+			ETM_SHAP_SHAP_IND_DATA1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_shap_ind_data1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"full_threshold",
+			ETM_SHAP_FULL_THRESHOLDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_full_threshold_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"empty_threshold",
+			ETM_SHAP_EMPTY_THRESHOLDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_empty_threshold_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"shap_sta_init_cfg",
+			ETM_SHAP_SHAP_STA_INIT_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_shap_shap_sta_init_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"shap_cfg_init_cfg",
+			ETM_SHAP_SHAP_CFG_INIT_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_shap_shap_cfg_init_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"token_mode_switch",
+			ETM_SHAP_TOKEN_MODE_SWITCHr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_token_mode_switch_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"token_grain",
+			ETM_SHAP_TOKEN_GRAINr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x21,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_token_grain_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crd_grain",
+			ETM_SHAP_CRD_GRAINr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x22,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_crd_grain_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"shap_stat_ctrl",
+			ETM_SHAP_SHAP_STAT_CTRLr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x37,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_shap_stat_ctrl_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"token_stat_id",
+			ETM_SHAP_TOKEN_STAT_IDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x38,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_token_stat_id_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"token_stat",
+			ETM_SHAP_TOKEN_STATr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x39,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_token_stat_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"shap_stat_clk_cnt",
+			ETM_SHAP_SHAP_STAT_CLK_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x74,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_shap_stat_clk_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"shap_bucket_map_tbl",
+			ETM_SHAP_SHAP_BUCKET_MAP_TBLr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x80000000 + 0x000000,
+			(64 / 8),
+			0,
+			0xABFF + 1,
+			0,
+			1,
+			1,
+			g_etm_shap_shap_bucket_map_tbl_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"bkt_para_tbl",
+			ETM_SHAP_BKT_PARA_TBLr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x80000000 + 0x100000,
+			(64 / 8),
+			0,
+			0xAFF + 1,
+			0,
+			1,
+			2,
+			g_etm_shap_bkt_para_tbl_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"credit_en",
+			ETM_CRDT_CREDIT_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0001,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_credit_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crt_inter1",
+			ETM_CRDT_CRT_INTER1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0002,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crt_inter1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"db_token",
+			ETM_CRDT_DB_TOKENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0003,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_db_token_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crs_flt_cfg",
+			ETM_CRDT_CRS_FLT_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crs_flt_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"th_sp",
+			ETM_CRDT_TH_SPr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0005,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_th_sp_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"th_wfq_fq",
+			ETM_CRDT_TH_WFQ_FQr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0006,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_crdt_th_wfq_fq_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"th_wfq2_fq2",
+			ETM_CRDT_TH_WFQ2_FQ2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0007,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_crdt_th_wfq2_fq2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"th_wfq4_fq4",
+			ETM_CRDT_TH_WFQ4_FQ4r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_crdt_th_wfq4_fq4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_state",
+			ETM_CRDT_CFG_STATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0009,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_cfg_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_ind_cmd",
+			ETM_CRDT_CRDT_IND_CMDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_etm_crdt_crdt_ind_cmd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_ind_sta",
+			ETM_CRDT_CRDT_IND_STAr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crdt_ind_sta_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_ind_data0",
+			ETM_CRDT_CRDT_IND_DATA0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crdt_ind_data0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_ind_data1",
+			ETM_CRDT_CRDT_IND_DATA1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crdt_ind_data1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_state",
+			ETM_CRDT_CRDT_STATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_crdt_crdt_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_id_0",
+			ETM_CRDT_STAT_QUE_ID_0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x10,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_stat_que_id_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_id_1",
+			ETM_CRDT_STAT_QUE_ID_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x11,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_stat_que_id_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_id_2",
+			ETM_CRDT_STAT_QUE_ID_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_stat_que_id_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_id_3",
+			ETM_CRDT_STAT_QUE_ID_3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x13,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_stat_que_id_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_id_4",
+			ETM_CRDT_STAT_QUE_ID_4r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x14,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_stat_que_id_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_id_5",
+			ETM_CRDT_STAT_QUE_ID_5r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x15,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_stat_que_id_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_id_6",
+			ETM_CRDT_STAT_QUE_ID_6r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x16,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_stat_que_id_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_id_7",
+			ETM_CRDT_STAT_QUE_ID_7r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x17,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_stat_que_id_7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_id_8",
+			ETM_CRDT_STAT_QUE_ID_8r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x18,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_stat_que_id_8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_id_9",
+			ETM_CRDT_STAT_QUE_ID_9r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x19,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_stat_que_id_9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_id_10",
+			ETM_CRDT_STAT_QUE_ID_10r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_stat_que_id_10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_id_11",
+			ETM_CRDT_STAT_QUE_ID_11r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_stat_que_id_11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_id_12",
+			ETM_CRDT_STAT_QUE_ID_12r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_stat_que_id_12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_id_13",
+			ETM_CRDT_STAT_QUE_ID_13r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_stat_que_id_13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_id_14",
+			ETM_CRDT_STAT_QUE_ID_14r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_stat_que_id_14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_id_15",
+			ETM_CRDT_STAT_QUE_ID_15r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_stat_que_id_15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_credit",
+			ETM_CRDT_STAT_QUE_CREDITr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x20,
+			(32 / 8),
+			0,
+			0x0f + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_stat_que_credit_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_cfg_ram_init",
+			ETM_CRDT_CRDT_CFG_RAM_INITr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x7a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_crdt_crdt_cfg_ram_init_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_sta_ram_init",
+			ETM_CRDT_CRDT_STA_RAM_INITr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x7b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_crdt_crdt_sta_ram_init_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crs_que_id",
+			ETM_CRDT_CRS_QUE_IDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x86,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crs_que_id_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_crs_end_state",
+			ETM_CRDT_QMU_CRS_END_STATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x87,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_qmu_crs_end_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"shap_rdy",
+			ETM_CRDT_SHAP_RDYr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x90,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_shap_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"shap_int_reg",
+			ETM_CRDT_SHAP_INT_REGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x91,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_shap_int_reg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"shap_int_mask_reg",
+			ETM_CRDT_SHAP_INT_MASK_REGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x92,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_shap_int_mask_reg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"token_state_almost_empty_th",
+			ETM_CRDT_TOKEN_STATE_ALMOST_EMPTY_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x93,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_token_state_almost_empty_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"token_state_empty_th",
+			ETM_CRDT_TOKEN_STATE_EMPTY_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x94,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_token_state_empty_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"full_th",
+			ETM_CRDT_FULL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x95,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_full_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_c_level_shap_en",
+			ETM_CRDT_PP_C_LEVEL_SHAP_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x96,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_pp_c_level_shap_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"enq_token_th",
+			ETM_CRDT_ENQ_TOKEN_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x97,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_enq_token_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_tokenq_level1_qstate_weight_cir",
+			ETM_CRDT_PP_TOKENQ_LEVEL1_QSTATE_WEIGHT_CIRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x98,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_crdt_pp_tokenq_level1_qstate_weight_cir_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_idle_weight_level1_cir",
+			ETM_CRDT_PP_IDLE_WEIGHT_LEVEL1_CIRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x99,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_pp_idle_weight_level1_cir_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rci_grade_th_0_cfg",
+			ETM_CRDT_RCI_GRADE_TH_0_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xc0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_rci_grade_th_0_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rci_grade_th_1_cfg",
+			ETM_CRDT_RCI_GRADE_TH_1_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xc1,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_rci_grade_th_1_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rci_grade_th_2_cfg",
+			ETM_CRDT_RCI_GRADE_TH_2_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xc2,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_rci_grade_th_2_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rci_grade_th_3_cfg",
+			ETM_CRDT_RCI_GRADE_TH_3_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xc3,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_rci_grade_th_3_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rci_grade_th_4_cfg",
+			ETM_CRDT_RCI_GRADE_TH_4_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xc4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_rci_grade_th_4_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rci_grade_th_5_cfg",
+			ETM_CRDT_RCI_GRADE_TH_5_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xc5,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_rci_grade_th_5_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rci_grade_th_6_cfg",
+			ETM_CRDT_RCI_GRADE_TH_6_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xc6,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_rci_grade_th_6_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow_del_cmd",
+			ETM_CRDT_FLOW_DEL_CMDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x00f1,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_etm_crdt_flow_del_cmd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_clr",
+			ETM_CRDT_CNT_CLRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x00f2,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_cnt_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_int_bus",
+			ETM_CRDT_CRDT_INT_BUSr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x00f3,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			19,
+			g_etm_crdt_crdt_int_bus_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_int_mask",
+			ETM_CRDT_CRDT_INT_MASKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x00f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crdt_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_weight_together",
+			ETM_CRDT_CFG_WEIGHT_TOGETHERr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x00f9,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_cfg_weight_together_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"weight",
+			ETM_CRDT_WEIGHTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x00fa,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_crdt_weight_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dev_sp_state",
+			ETM_CRDT_DEV_SP_STATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x11e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_dev_sp_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dev_crs",
+			ETM_CRDT_DEV_CRSr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x11f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_dev_crs_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"congest_token_disable_31_0",
+			ETM_CRDT_CONGEST_TOKEN_DISABLE_31_0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x130,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_congest_token_disable_31_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"congest_token_disable_63_32",
+			ETM_CRDT_CONGEST_TOKEN_DISABLE_63_32r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x131,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_congest_token_disable_63_32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_interval_en_cfg",
+			ETM_CRDT_CRDT_INTERVAL_EN_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0139,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crdt_interval_en_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"q_token_staue_cfg",
+			ETM_CRDT_Q_TOKEN_STAUE_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x150,
+			(32 / 8),
+			0,
+			0xf + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_q_token_staue_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"q_token_dist_cnt",
+			ETM_CRDT_Q_TOKEN_DIST_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x160,
+			(32 / 8),
+			0,
+			0xf + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_q_token_dist_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"q_token_dec_cnt",
+			ETM_CRDT_Q_TOKEN_DEC_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x170,
+			(32 / 8),
+			0,
+			0xf + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_q_token_dec_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_weight_ram",
+			ETM_CRDT_PP_WEIGHT_RAMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x41000000,
+			(32 / 8),
+			0,
+			0x003F + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_pp_weight_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_cbs_shape_en_ram",
+			ETM_CRDT_PP_CBS_SHAPE_EN_RAMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x42000000,
+			(32 / 8),
+			0,
+			0x003f + 1,
+			0,
+			1,
+			2,
+			g_etm_crdt_pp_cbs_shape_en_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_next_pc_q_state_ram",
+			ETM_CRDT_PP_NEXT_PC_Q_STATE_RAMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x43000000,
+			(32 / 8),
+			0,
+			0x003f + 1,
+			0,
+			1,
+			3,
+			g_etm_crdt_pp_next_pc_q_state_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dev_interval",
+			ETM_CRDT_DEV_INTERVALr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x50000000,
+			(32 / 8),
+			0,
+			0x0127 + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_dev_interval_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dev_wfq_cnt",
+			ETM_CRDT_DEV_WFQ_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x51000000,
+			(32 / 8),
+			0,
+			0x0007 + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_dev_wfq_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dev_wfq_state",
+			ETM_CRDT_DEV_WFQ_STATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x52000000,
+			(32 / 8),
+			0,
+			0x0007 + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_dev_wfq_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dev_active_head_ptr",
+			ETM_CRDT_DEV_ACTIVE_HEAD_PTRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x53000000,
+			(32 / 8),
+			0,
+			0x0007 + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_dev_active_head_ptr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dev_active_tail_ptr",
+			ETM_CRDT_DEV_ACTIVE_TAIL_PTRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x54000000,
+			(32 / 8),
+			0,
+			0x0007 + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_dev_active_tail_ptr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dev_unactive_head_ptr",
+			ETM_CRDT_DEV_UNACTIVE_HEAD_PTRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x55000000,
+			(32 / 8),
+			0,
+			0x0037 + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_dev_unactive_head_ptr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dev_unactive_tail_ptr",
+			ETM_CRDT_DEV_UNACTIVE_TAIL_PTRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x56000000,
+			(32 / 8),
+			0,
+			0x0037 + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_dev_unactive_tail_ptr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_weight",
+			ETM_CRDT_PP_WEIGHTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x44000000,
+			(32 / 8),
+			0,
+			0x003F + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_pp_weight_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_que_state",
+			ETM_CRDT_PP_QUE_STATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x46000000,
+			(32 / 8),
+			0,
+			0x003f + 1,
+			0,
+			1,
+			5,
+			g_etm_crdt_pp_que_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_next_ptr",
+			ETM_CRDT_PP_NEXT_PTRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x49000000,
+			(32 / 8),
+			0,
+			0x003f + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_pp_next_ptr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_cfg",
+			ETM_CRDT_PP_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x4a000000,
+			(32 / 8),
+			0,
+			0x003f + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_pp_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_up_ptr",
+			ETM_CRDT_PP_UP_PTRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x4b000000,
+			(32 / 8),
+			0,
+			0x003f + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_pp_up_ptr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"credit_drop_num",
+			ETM_CRDT_CREDIT_DROP_NUMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x180,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_credit_drop_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_id_lv0",
+			ETM_CRDT_SE_ID_LV0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x181,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_se_id_lv0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_id_lv1",
+			ETM_CRDT_SE_ID_LV1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x182,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_se_id_lv1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_id_lv2",
+			ETM_CRDT_SE_ID_LV2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x183,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_se_id_lv2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_id_lv3",
+			ETM_CRDT_SE_ID_LV3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x184,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_se_id_lv3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_id_lv4",
+			ETM_CRDT_SE_ID_LV4r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x185,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_se_id_lv4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"que_id",
+			ETM_CRDT_QUE_IDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x186,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_que_id_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_info_lv0",
+			ETM_CRDT_SE_INFO_LV0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x187,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_etm_crdt_se_info_lv0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_info_lv1",
+			ETM_CRDT_SE_INFO_LV1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x188,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_etm_crdt_se_info_lv1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_info_lv2",
+			ETM_CRDT_SE_INFO_LV2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x189,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_etm_crdt_se_info_lv2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_info_lv3",
+			ETM_CRDT_SE_INFO_LV3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x18a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_etm_crdt_se_info_lv3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_info_lv4",
+			ETM_CRDT_SE_INFO_LV4r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x18b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_etm_crdt_se_info_lv4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"que_state",
+			ETM_CRDT_QUE_STATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x18c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_que_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"eir_off_in_advance",
+			ETM_CRDT_EIR_OFF_IN_ADVANCEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x190,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_eir_off_in_advance_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"double_level_shap_prevent",
+			ETM_CRDT_DOUBLE_LEVEL_SHAP_PREVENTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x192,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_double_level_shap_prevent_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"add_store_cycle",
+			ETM_CRDT_ADD_STORE_CYCLEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x193,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_add_store_cycle_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tflag2_wr_flag_sum",
+			ETM_CRDT_TFLAG2_WR_FLAG_SUMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x194,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_tflag2_wr_flag_sum_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flowque_para_tbl",
+			ETM_CRDT_FLOWQUE_PARA_TBLr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x00000000 + 0x200000,
+			(32 / 8),
+			0,
+			0x47FF + 1,
+			0,
+			1,
+			3,
+			g_etm_crdt_flowque_para_tbl_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_para_tbl",
+			ETM_CRDT_SE_PARA_TBLr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x80000000 + 0x300000,
+			(64 / 8),
+			0,
+			0x63FF + 1,
+			0,
+			1,
+			5,
+			g_etm_crdt_se_para_tbl_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flowque_ins_tbl",
+			ETM_CRDT_FLOWQUE_INS_TBLr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x00000000 + 0x400000,
+			(32 / 8),
+			0,
+			0x47FF + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_flowque_ins_tbl_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_ins_tbl",
+			ETM_CRDT_SE_INS_TBLr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x00000000 + 0x500000,
+			(32 / 8),
+			0,
+			0x63FF + 1,
+			0,
+			1,
+			2,
+			g_etm_crdt_se_ins_tbl_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"eir_crs_filter_tbl",
+			ETM_CRDT_EIR_CRS_FILTER_TBLr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x00000000 + 0x600000,
+			(32 / 8),
+			0,
+			0x23FF + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_eir_crs_filter_tbl_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_cfg_done",
+			ETM_QMU_QCFG_QLIST_CFG_DONEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x10,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qcfg_qlist_cfg_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qsch_credit_value",
+			ETM_QMU_QCFG_QSCH_CREDIT_VALUEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x11,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qcfg_qsch_credit_value_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qsch_crbal_init_value",
+			ETM_QMU_QCFG_QSCH_CRBAL_INIT_VALUEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qcfg_qsch_crbal_init_value_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qsch_crbal_init_mask",
+			ETM_QMU_QCFG_QSCH_CRBAL_INIT_MASKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x13,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qcfg_qsch_crbal_init_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cmdsch_rd_cmd_aful_th",
+			ETM_QMU_CMDSCH_RD_CMD_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x22,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cmdsch_rd_cmd_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_port_fc_interval",
+			ETM_QMU_CFG_PORT_FC_INTERVALr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x23,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_port_fc_interval_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_csch_aged_cfg",
+			ETM_QMU_QCFG_CSCH_AGED_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x24,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qcfg_csch_aged_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_csch_aged_scan_time",
+			ETM_QMU_QCFG_CSCH_AGED_SCAN_TIMEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x25,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qcfg_csch_aged_scan_time_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qmu_qlist_state_query",
+			ETM_QMU_QCFG_QMU_QLIST_STATE_QUERYr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x26,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			19,
+			g_etm_qmu_qcfg_qmu_qlist_state_query_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qsch_crbal_drop_en",
+			ETM_QMU_CFGMT_QSCH_CRBAL_DROP_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x27,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_qmu_cfgmt_qsch_crbal_drop_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_wlist_qnum_fifo_aful_th",
+			ETM_QMU_CFGMT_WLIST_QNUM_FIFO_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x29,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_wlist_qnum_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_csw_pkt_blk_mode",
+			ETM_QMU_QCFG_CSW_PKT_BLK_MODEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x28,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qcfg_csw_pkt_blk_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_ram_init_cancel",
+			ETM_QMU_QCFG_QLIST_RAM_INIT_CANCELr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qcfg_qlist_ram_init_cancel_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qsch_crbal_transfer_mode",
+			ETM_QMU_QCFG_QSCH_CRBAL_TRANSFER_MODEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_qmu_qcfg_qsch_crbal_transfer_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_qclr_interval",
+			ETM_QMU_QCFG_QLIST_QCLR_INTERVALr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qcfg_qlist_qclr_interval_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qsch_qclr_rate",
+			ETM_QMU_QCFG_QSCH_QCLR_RATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qcfg_qsch_qclr_rate_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_ddr_random",
+			ETM_QMU_QCFG_QLIST_DDR_RANDOMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qcfg_qlist_ddr_random_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qlist_pds_fifo_afull_th",
+			ETM_QMU_CFGMT_QLIST_PDS_FIFO_AFULL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x30,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_qlist_pds_fifo_afull_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_sop_cmd_fifo_afull_th",
+			ETM_QMU_CFGMT_SOP_CMD_FIFO_AFULL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x31,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_sop_cmd_fifo_afull_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_non_sop_cmd_fifo_afull_th",
+			ETM_QMU_CFGMT_NON_SOP_CMD_FIFO_AFULL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x32,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_non_sop_cmd_fifo_afull_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_mmu_data_fifo_afull_th",
+			ETM_QMU_CFGMT_MMU_DATA_FIFO_AFULL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x33,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_mmu_data_fifo_afull_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_bank_ept_th",
+			ETM_QMU_QCFG_QLIST_BANK_EPT_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x34,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qcfg_qlist_bank_ept_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"random_bypass_en",
+			ETM_QMU_RANDOM_BYPASS_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x36,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_random_bypass_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_crs_spd_bypass",
+			ETM_QMU_CFGMT_CRS_SPD_BYPASSr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x37,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_crs_spd_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_crs_interval",
+			ETM_QMU_CFGMT_CRS_INTERVALr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x38,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_crs_interval_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_auto_credit_control_en",
+			ETM_QMU_CFG_QSCH_AUTO_CREDIT_CONTROL_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x3b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_auto_credit_control_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_autocrfrstque",
+			ETM_QMU_CFG_QSCH_AUTOCRFRSTQUEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x3c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_autocrfrstque_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_autocrlastque",
+			ETM_QMU_CFG_QSCH_AUTOCRLASTQUEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x3d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_autocrlastque_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_autocreditrate",
+			ETM_QMU_CFG_QSCH_AUTOCREDITRATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x3e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_autocreditrate_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_scanfrstque",
+			ETM_QMU_CFG_QSCH_SCANFRSTQUEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x51,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_scanfrstque_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_scanlastque",
+			ETM_QMU_CFG_QSCH_SCANLASTQUEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x52,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_scanlastque_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_scanrate",
+			ETM_QMU_CFG_QSCH_SCANRATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x53,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_scanrate_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_scan_en",
+			ETM_QMU_CFG_QSCH_SCAN_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x54,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_scan_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qsch_rd_credit_fifo_rate",
+			ETM_QMU_CFGMT_QSCH_RD_CREDIT_FIFO_RATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x7c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_qsch_rd_credit_fifo_rate_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_bdep",
+			ETM_QMU_QCFG_QLIST_BDEPr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x9a7,
+			(32 / 8),
+			0,
+			0x3F + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_bdep_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_bhead",
+			ETM_QMU_QCFG_QLIST_BHEADr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x9e7,
+			(32 / 8),
+			0,
+			0x3F + 1,
+			0,
+			1,
+			2,
+			g_etm_qmu_qcfg_qlist_bhead_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_btail",
+			ETM_QMU_QCFG_QLIST_BTAILr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0xa27,
+			(32 / 8),
+			0,
+			0x3F + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_btail_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qsch_shap_param",
+			ETM_QMU_QCFG_QSCH_SHAP_PARAMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0xfc,
+			(32 / 8),
+			0,
+			0x3F + 1,
+			0,
+			1,
+			3,
+			g_etm_qmu_qcfg_qsch_shap_param_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qsch_shap_token",
+			ETM_QMU_QCFG_QSCH_SHAP_TOKENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x185,
+			(32 / 8),
+			0,
+			0x3F + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qsch_shap_token_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qsch_shap_offset",
+			ETM_QMU_QCFG_QSCH_SHAP_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x20e,
+			(32 / 8),
+			0,
+			0x3F + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qsch_shap_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qsch_crs_eir_th",
+			ETM_QMU_QCFG_QSCH_CRS_EIR_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x250,
+			(32 / 8),
+			0,
+			0xF + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qsch_crs_eir_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qsch_crs_th1",
+			ETM_QMU_QCFG_QSCH_CRS_TH1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x297,
+			(32 / 8),
+			0,
+			0xF + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qsch_crs_th1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qsch_crs_th2",
+			ETM_QMU_QCFG_QSCH_CRS_TH2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x2a7,
+			(32 / 8),
+			0,
+			0xF + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qsch_crs_th2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_csch_congest_th",
+			ETM_QMU_QCFG_CSCH_CONGEST_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x2b7,
+			(32 / 8),
+			0,
+			0x3F + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_csch_congest_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_csch_sp_fc_th",
+			ETM_QMU_QCFG_CSCH_SP_FC_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x330,
+			(32 / 8),
+			0,
+			0x140 + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_csch_sp_fc_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_csw_shap_parameter",
+			ETM_QMU_QCFG_CSW_SHAP_PARAMETERr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x5d0,
+			(32 / 8),
+			0,
+			0x3F + 1,
+			0,
+			1,
+			2,
+			g_etm_qmu_qcfg_csw_shap_parameter_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_rd_release_aful_th",
+			ETM_QMU_CFGMT_RD_RELEASE_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x58e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_rd_release_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_drop_imem_release_fifo_aful_th",
+			ETM_QMU_CFGMT_DROP_IMEM_RELEASE_FIFO_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x58f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_drop_imem_release_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_nnh_rd_buf_aful_th",
+			ETM_QMU_CFGMT_NNH_RD_BUF_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x590,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_nnh_rd_buf_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_pid_use_inall",
+			ETM_QMU_CFG_PID_USE_INALLr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x591,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_pid_use_inall_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_pid_round_th",
+			ETM_QMU_CFG_PID_ROUND_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x592,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_pid_round_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_credit_fifo_afull_th",
+			ETM_QMU_CFGMT_CREDIT_FIFO_AFULL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x593,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_credit_fifo_afull_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_scan_fifo_afull_th",
+			ETM_QMU_CFGMT_SCAN_FIFO_AFULL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x594,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_scan_fifo_afull_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_small_fifo_aful_th",
+			ETM_QMU_CFGMT_SMALL_FIFO_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x595,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_small_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_free_addr_fifo_aful_th",
+			ETM_QMU_CFGMT_FREE_ADDR_FIFO_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x596,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_free_addr_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_enq_rpt_fifo_aful_th",
+			ETM_QMU_CFGMT_ENQ_RPT_FIFO_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x597,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_enq_rpt_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_csw_shap_token_depth",
+			ETM_QMU_QCFG_CSW_SHAP_TOKEN_DEPTHr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x656,
+			(32 / 8),
+			0,
+			0x3F + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_csw_shap_token_depth_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_csw_shap_offset_value",
+			ETM_QMU_QCFG_CSW_SHAP_OFFSET_VALUEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x6cf,
+			(32 / 8),
+			0,
+			0x3F + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_csw_shap_offset_value_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_csw_fc_offset_value",
+			ETM_QMU_QCFG_CSW_FC_OFFSET_VALUEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x750,
+			(32 / 8),
+			0,
+			0x3F + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_csw_fc_offset_value_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_init_done_state",
+			ETM_QMU_QMU_INIT_DONE_STATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_etm_qmu_qmu_init_done_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csw_qcfg_port_shap_rdy_0",
+			ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2001,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csw_qcfg_port_shap_rdy_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csw_qcfg_port_shap_rdy_1",
+			ETM_QMU_CSW_QCFG_PORT_SHAP_RDY_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2002,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csw_qcfg_port_shap_rdy_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qlist_cfgmt_ram_init_done",
+			ETM_QMU_QLIST_CFGMT_RAM_INIT_DONEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2015,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			8,
+			g_etm_qmu_qlist_cfgmt_ram_init_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qlist_cfgmt_ram_ecc_err",
+			ETM_QMU_QLIST_CFGMT_RAM_ECC_ERRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2016,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			30,
+			g_etm_qmu_qlist_cfgmt_ram_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qlist_cfgmt_ram_slot_err",
+			ETM_QMU_QLIST_CFGMT_RAM_SLOT_ERRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2017,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			20,
+			g_etm_qmu_qlist_cfgmt_ram_slot_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qsch_cfgmt_ram_ecc",
+			ETM_QMU_QSCH_CFGMT_RAM_ECCr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			27,
+			g_etm_qmu_qsch_cfgmt_ram_ecc_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qlist_cfgmt_fifo_state",
+			ETM_QMU_QLIST_CFGMT_FIFO_STATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2019,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			26,
+			g_etm_qmu_qlist_cfgmt_fifo_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qlist_qcfg_clr_done",
+			ETM_QMU_QLIST_QCFG_CLR_DONEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x201a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qlist_qcfg_clr_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_int_mask1",
+			ETM_QMU_QMU_INT_MASK1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x201b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_int_mask1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_int_mask2",
+			ETM_QMU_QMU_INT_MASK2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x201c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_int_mask2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_int_mask3",
+			ETM_QMU_QMU_INT_MASK3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x201d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_int_mask3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_int_mask4",
+			ETM_QMU_QMU_INT_MASK4r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x201e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_int_mask4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_int_mask5",
+			ETM_QMU_QMU_INT_MASK5r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x201f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_int_mask5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_int_mask6",
+			ETM_QMU_QMU_INT_MASK6r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2013,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_int_mask6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cmd_sch_cfgmt_fifo_state",
+			ETM_QMU_CMD_SCH_CFGMT_FIFO_STATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			26,
+			g_etm_qmu_cmd_sch_cfgmt_fifo_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qlist_r_bcnt",
+			ETM_QMU_QLIST_R_BCNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x60000,
+			(32 / 8),
+			0,
+			0x23ff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qlist_r_bcnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qsch_rw_crbal",
+			ETM_QMU_QSCH_RW_CRBALr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x70000,
+			(32 / 8),
+			0,
+			0x23ff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qsch_rw_crbal_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qsch_rw_crs",
+			ETM_QMU_QSCH_RW_CRSr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x80000,
+			(32 / 8),
+			0,
+			0x23ff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qsch_rw_crs_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qsch_r_wlist_empty",
+			ETM_QMU_QSCH_R_WLIST_EMPTYr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0xa0000,
+			(32 / 8),
+			0,
+			0xfff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qsch_r_wlist_empty_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_baram_rd",
+			ETM_QMU_QCFG_QLIST_BARAM_RDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0xe0000,
+			(32 / 8),
+			0,
+			0x7ff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_baram_rd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qsch_crbal_fb_rw",
+			ETM_QMU_QCFG_QSCH_CRBAL_FB_RWr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0xb0000,
+			(32 / 8),
+			0,
+			0x23ff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qsch_crbal_fb_rw_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_grp0_bank",
+			ETM_QMU_QCFG_QLIST_GRP0_BANKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x7c1,
+			(32 / 8),
+			0,
+			0x3f + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_grp0_bank_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_grp1_bank",
+			ETM_QMU_QCFG_QLIST_GRP1_BANKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x801,
+			(32 / 8),
+			0,
+			0x3f + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_grp1_bank_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_grp2_bank",
+			ETM_QMU_QCFG_QLIST_GRP2_BANKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x841,
+			(32 / 8),
+			0,
+			0x3f + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_grp2_bank_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_grp3_bank",
+			ETM_QMU_QCFG_QLIST_GRP3_BANKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x881,
+			(32 / 8),
+			0,
+			0x3f + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_grp3_bank_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_grp4_bank",
+			ETM_QMU_QCFG_QLIST_GRP4_BANKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x8c1,
+			(32 / 8),
+			0,
+			0x3f + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_grp4_bank_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_grp5_bank",
+			ETM_QMU_QCFG_QLIST_GRP5_BANKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x967,
+			(32 / 8),
+			0,
+			0x3f + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_grp5_bank_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_grp6_bank",
+			ETM_QMU_QCFG_QLIST_GRP6_BANKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0xc00,
+			(32 / 8),
+			0,
+			0x3f + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_grp6_bank_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_grp7_bank",
+			ETM_QMU_QCFG_QLIST_GRP7_BANKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0xc40,
+			(32 / 8),
+			0,
+			0x3f + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_grp7_bank_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_grp",
+			ETM_QMU_QCFG_QLIST_GRPr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x901,
+			(32 / 8),
+			0,
+			0x3f + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_grp_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_active_to_bank_cfg",
+			ETM_QMU_CFGMT_ACTIVE_TO_BANK_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x941,
+			(32 / 8),
+			0,
+			0xf + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_cfgmt_active_to_bank_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_ddr_in_mmu_cfg",
+			ETM_QMU_CFGMT_DDR_IN_MMU_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x951,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_cfgmt_ddr_in_mmu_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_ddr_in_qmu_cfg",
+			ETM_QMU_CFGMT_DDR_IN_QMU_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x959,
+			(32 / 8),
+			0,
+			0x9 + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_cfgmt_ddr_in_qmu_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_bank_to_mmu_cfg",
+			ETM_QMU_CFGMT_BANK_TO_MMU_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0xb00,
+			(32 / 8),
+			0,
+			0x3f + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_cfgmt_bank_to_mmu_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_bank_to_qmu_cfg",
+			ETM_QMU_CFGMT_BANK_TO_QMU_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0xb40,
+			(32 / 8),
+			0,
+			0x4f + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_cfgmt_bank_to_qmu_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_grp_ram_n_clr_thd",
+			ETM_QMU_CFGMT_GRP_RAM_N_CLR_THDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe0a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_grp_ram_n_clr_thd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_age_pkt_num",
+			ETM_QMU_CFGMT_AGE_PKT_NUMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe00,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_age_pkt_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_age_multi_interval",
+			ETM_QMU_CFGMT_AGE_MULTI_INTERVALr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe01,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_age_multi_interval_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_pkt_age_en",
+			ETM_QMU_CFGMT_QMU_PKT_AGE_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe02,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_qmu_pkt_age_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_pkt_age_interval",
+			ETM_QMU_CFGMT_QMU_PKT_AGE_INTERVALr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe03,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_qmu_pkt_age_interval_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_pkt_age_start_end",
+			ETM_QMU_CFGMT_QMU_PKT_AGE_START_ENDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe04,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_qmu_cfgmt_qmu_pkt_age_start_end_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_pkt_age_req_aful_th",
+			ETM_QMU_CFGMT_PKT_AGE_REQ_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe05,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_pkt_age_req_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_pkt_age_step_interval",
+			ETM_QMU_CFGMT_PKT_AGE_STEP_INTERVALr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe12,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_pkt_age_step_interval_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_imem_age_mode",
+			ETM_QMU_CFGMT_QMU_IMEM_AGE_MODEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe06,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_etm_qmu_cfgmt_qmu_imem_age_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_imem_qlen_age_interval",
+			ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_INTERVALr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe07,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_qmu_imem_qlen_age_interval_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_imem_time_age_interval",
+			ETM_QMU_CFGMT_QMU_IMEM_TIME_AGE_INTERVALr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe08,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_qmu_imem_time_age_interval_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_imem_qlen_age_thd",
+			ETM_QMU_CFGMT_QMU_IMEM_QLEN_AGE_THDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe09,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_qmu_imem_qlen_age_thd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_imem_age_step_interval",
+			ETM_QMU_CFGMT_IMEM_AGE_STEP_INTERVALr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe13,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_imem_age_step_interval_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_ecc_bypass_read",
+			ETM_QMU_CFGMT_QMU_ECC_BYPASS_READr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe0b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_qmu_ecc_bypass_read_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_resp_stat_fc_en",
+			ETM_QMU_CFGMT_QMU_RESP_STAT_FC_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe0c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_qmu_resp_stat_fc_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_bank_xoff_pds_mode",
+			ETM_QMU_CFGMT_QMU_BANK_XOFF_PDS_MODEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe10,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_qmu_bank_xoff_pds_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_stat_offset",
+			ETM_QMU_CFGMT_QMU_STAT_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe11,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_qmu_stat_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fc_cnt_mode",
+			ETM_QMU_FC_CNT_MODEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2800,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_fc_cnt_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mmu_qmu_wr_fc_cnt",
+			ETM_QMU_MMU_QMU_WR_FC_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2801,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_mmu_qmu_wr_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mmu_qmu_rd_fc_cnt",
+			ETM_QMU_MMU_QMU_RD_FC_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2802,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_mmu_qmu_rd_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_cgavd_fc_cnt",
+			ETM_QMU_QMU_CGAVD_FC_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2803,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_cgavd_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_pkt_cnt",
+			ETM_QMU_CGAVD_QMU_PKT_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2804,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cgavd_qmu_pkt_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_pktlen_all",
+			ETM_QMU_CGAVD_QMU_PKTLEN_ALLr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2805,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cgavd_qmu_pktlen_all_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"observe_portfc_spec",
+			ETM_QMU_OBSERVE_PORTFC_SPECr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2818,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_observe_portfc_spec_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_lif_portfc_count",
+			ETM_QMU_SPEC_LIF_PORTFC_COUNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2819,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_lif_portfc_count_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_pfc_en",
+			ETM_QMU_CFGMT_QMU_PFC_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_qmu_pfc_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_pfc_mask_1",
+			ETM_QMU_CFGMT_QMU_PFC_MASK_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20e1,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_qmu_pfc_mask_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_pfc_mask_2",
+			ETM_QMU_CFGMT_QMU_PFC_MASK_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20e2,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_qmu_pfc_mask_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_repeat",
+			CFG_PCIE_INT_REPEATr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_int_repeat_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_up_size",
+			CFG_DMA_DMA_UP_SIZEr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_up_size_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"soc_wr_time_out_thresh",
+			CFG_CSR_SOC_WR_TIME_OUT_THRESHr,
+			CFG,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_soc_wr_time_out_thresh_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_shap_param",
+			NPPU_MR_CFG_CFG_SHAP_PARAMr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_mr_cfg_cfg_shap_param_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_shap_token",
+			NPPU_MR_CFG_CFG_SHAP_TOKENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_mr_cfg_cfg_shap_token_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"idle_ptr_fifo_aful_th",
+			NPPU_MR_CFG_IDLE_PTR_FIFO_AFUL_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x003c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_mr_cfg_idle_ptr_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos_port_cfg",
+			NPPU_MR_CFG_MR_COS_PORT_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0104,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_mr_cfg_mr_cos_port_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_status",
+			NPPU_PKTRX_CFG_IND_STATUSr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_ind_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_cmd",
+			NPPU_PKTRX_CFG_IND_CMDr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_nppu_pktrx_cfg_ind_cmd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data0",
+			NPPU_PKTRX_CFG_IND_DATA0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_ind_data0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data1",
+			NPPU_PKTRX_CFG_IND_DATA1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_ind_data1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data2",
+			NPPU_PKTRX_CFG_IND_DATA2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_ind_data2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data3",
+			NPPU_PKTRX_CFG_IND_DATA3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_ind_data3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data4",
+			NPPU_PKTRX_CFG_IND_DATA4r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_ind_data4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data5",
+			NPPU_PKTRX_CFG_IND_DATA5r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_ind_data5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data6",
+			NPPU_PKTRX_CFG_IND_DATA6r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_ind_data6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data7",
+			NPPU_PKTRX_CFG_IND_DATA7r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_ind_data7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tcam_0_cmd",
+			NPPU_PKTRX_CFG_TCAM_0_CMDr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			11,
+			g_nppu_pktrx_cfg_tcam_0_cmd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tcam_1_cmd",
+			NPPU_PKTRX_CFG_TCAM_1_CMDr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x002c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			8,
+			g_nppu_pktrx_cfg_tcam_1_cmd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port_en_0",
+			NPPU_PKTRX_CFG_PORT_EN_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_port_en_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port_en_1",
+			NPPU_PKTRX_CFG_PORT_EN_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_port_en_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port_en_2",
+			NPPU_PKTRX_CFG_PORT_EN_2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_port_en_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port_en_3",
+			NPPU_PKTRX_CFG_PORT_EN_3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x003c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_nppu_pktrx_cfg_port_en_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_port_l2_offset_mode_0",
+			NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_port_l2_offset_mode_1",
+			NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_port_l2_offset_mode_2",
+			NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_port_l2_offset_mode_3",
+			NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODE_3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port_fc_mode_0",
+			NPPU_PKTRX_CFG_PORT_FC_MODE_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_port_fc_mode_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port_fc_mode_1",
+			NPPU_PKTRX_CFG_PORT_FC_MODE_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_port_fc_mode_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port_fc_mode_2",
+			NPPU_PKTRX_CFG_PORT_FC_MODE_2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_port_fc_mode_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port_fc_mode_3",
+			NPPU_PKTRX_CFG_PORT_FC_MODE_3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x005c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_port_fc_mode_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port_fc_mode_4",
+			NPPU_PKTRX_CFG_PORT_FC_MODE_4r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_port_fc_mode_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port_fc_mode_5",
+			NPPU_PKTRX_CFG_PORT_FC_MODE_5r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_port_fc_mode_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port_fc_mode_6",
+			NPPU_PKTRX_CFG_PORT_FC_MODE_6r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_port_fc_mode_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port_fc_mode_7",
+			NPPU_PKTRX_CFG_PORT_FC_MODE_7r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x006c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_nppu_pktrx_cfg_port_fc_mode_7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_isch_aging_th",
+			NPPU_PKTRX_CFG_CFG_ISCH_AGING_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0070,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_pktrx_cfg_cfg_isch_aging_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isch_fifo_th_0",
+			NPPU_PKTRX_CFG_ISCH_FIFO_TH_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0074,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pktrx_cfg_isch_fifo_th_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isch_cfg_1",
+			NPPU_PKTRX_CFG_ISCH_CFG_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x008c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_nppu_pktrx_cfg_isch_cfg_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tcam_0_vld",
+			NPPU_PKTRX_CFG_TCAM_0_VLDr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00d4,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			4,
+			1,
+			g_nppu_pktrx_cfg_tcam_0_vld_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tcam_1_vld",
+			NPPU_PKTRX_CFG_TCAM_1_VLDr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00f4,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			4,
+			1,
+			g_nppu_pktrx_cfg_tcam_1_vld_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_port_en_mask",
+			NPPU_PKTRX_CFG_CPU_PORT_EN_MASKr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_cpu_port_en_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_glbal_cfg_0",
+			NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_glbal_cfg_1",
+			NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_pktrx_glbal_cfg_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_glbal_cfg_2",
+			NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0200,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_pktrx_glbal_cfg_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_glbal_cfg_3",
+			NPPU_PKTRX_CFG_PKTRX_GLBAL_CFG_3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0204,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_pktrx_glbal_cfg_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"nppu_start",
+			NPPU_PKTRX_CFG_NPPU_STARTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0208,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_nppu_start_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_status",
+			NPPU_PKTRX_STAT_IND_STATUSr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_STAT_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_stat_ind_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_cmd",
+			NPPU_PKTRX_STAT_IND_CMDr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_STAT_BASE_ADDR + 0x0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_nppu_pktrx_stat_ind_cmd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data0",
+			NPPU_PKTRX_STAT_IND_DATA0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_STAT_BASE_ADDR + 0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_stat_ind_data0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_ovfl_mode",
+			NPPU_IDMA_CFG_DEBUG_CNT_OVFL_MODEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x4f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_idma_cfg_debug_cnt_ovfl_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_status",
+			NPPU_IDMA_STAT_IND_STATUSr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_STAT_BASE_ADDR + 0x0400,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_idma_stat_ind_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_cmd",
+			NPPU_IDMA_STAT_IND_CMDr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_STAT_BASE_ADDR + 0x0404,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_nppu_idma_stat_ind_cmd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data0",
+			NPPU_IDMA_STAT_IND_DATA0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_STAT_BASE_ADDR + 0x0408,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_idma_stat_ind_data0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_status",
+			NPPU_PBU_CFG_IND_STATUSr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x400,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_ind_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_cmd",
+			NPPU_PBU_CFG_IND_CMDr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x404,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_nppu_pbu_cfg_ind_cmd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data0",
+			NPPU_PBU_CFG_IND_DATA0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x408,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_ind_data0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data1",
+			NPPU_PBU_CFG_IND_DATA1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x40c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_ind_data1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data2",
+			NPPU_PBU_CFG_IND_DATA2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x410,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_ind_data2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data3",
+			NPPU_PBU_CFG_IND_DATA3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x414,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_ind_data3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data4",
+			NPPU_PBU_CFG_IND_DATA4r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x418,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_ind_data4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data5",
+			NPPU_PBU_CFG_IND_DATA5r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x41c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_ind_data5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data6",
+			NPPU_PBU_CFG_IND_DATA6r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x420,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_ind_data6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data7",
+			NPPU_PBU_CFG_IND_DATA7r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x424,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_ind_data7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"idma_public_th",
+			NPPU_PBU_CFG_IDMA_PUBLIC_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_idma_public_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lif_public_th",
+			NPPU_PBU_CFG_LIF_PUBLIC_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_lif_public_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"idma_total_th",
+			NPPU_PBU_CFG_IDMA_TOTAL_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_idma_total_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lif_total_th",
+			NPPU_PBU_CFG_LIF_TOTAL_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_lif_total_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mc_total_th",
+			NPPU_PBU_CFG_MC_TOTAL_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_mc_total_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mc_cos10_th",
+			NPPU_PBU_CFG_MC_COS10_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pbu_cfg_mc_cos10_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mc_cos32_th",
+			NPPU_PBU_CFG_MC_COS32_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pbu_cfg_mc_cos32_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mc_cos54_th",
+			NPPU_PBU_CFG_MC_COS54_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pbu_cfg_mc_cos54_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mc_cos76_th",
+			NPPU_PBU_CFG_MC_COS76_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pbu_cfg_mc_cos76_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_ovfl_mode",
+			NPPU_PBU_CFG_DEBUG_CNT_OVFL_MODEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_debug_cnt_ovfl_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_key_aful_negate_cfg",
+			NPPU_PBU_CFG_SE_KEY_AFUL_NEGATE_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x530,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_se_key_aful_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sa_flag",
+			NPPU_PBU_CFG_SA_FLAGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x724,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_sa_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data",
+			NPPU_PBU_STAT_IND_DATAr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			127 + 1,
+			0,
+			4,
+			1,
+			g_nppu_pbu_stat_ind_data_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_status",
+			NPPU_PBU_STAT_IND_STATUSr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x0400,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_ind_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_cmd",
+			NPPU_PBU_STAT_IND_CMDr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x0404,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_nppu_pbu_stat_ind_cmd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"total_cnt",
+			NPPU_PBU_STAT_TOTAL_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x558,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_total_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"idma_pub_cnt",
+			NPPU_PBU_STAT_IDMA_PUB_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x55c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_idma_pub_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lif_pub_cnt",
+			NPPU_PBU_STAT_LIF_PUB_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x560,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_lif_pub_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mc_total_cnt",
+			NPPU_PBU_STAT_MC_TOTAL_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x564,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_mc_total_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_thram_init_done",
+			NPPU_PBU_STAT_PBU_THRAM_INIT_DONEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x568,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_pbu_thram_init_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ifb_fptr_init_done",
+			NPPU_PBU_STAT_IFB_FPTR_INIT_DONEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x56c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_ifb_fptr_init_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"weight_normal_uc",
+			NPPU_ISU_CFG_WEIGHT_NORMAL_UCr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_weight_normal_uc_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fabric_or_saip",
+			NPPU_ISU_CFG_FABRIC_OR_SAIPr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_fabric_or_saip_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_status",
+			NPPU_ISU_STAT_IND_STATUSr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_ind_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_cmd",
+			NPPU_ISU_STAT_IND_CMDr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_nppu_isu_stat_ind_cmd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat0",
+			NPPU_ISU_STAT_IND_DAT0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_ind_dat0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_access_done",
+			NPPU_ODMA_CFG_IND_ACCESS_DONEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_ind_access_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_command",
+			NPPU_ODMA_CFG_IND_COMMANDr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_nppu_odma_cfg_ind_command_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat0",
+			NPPU_ODMA_CFG_IND_DAT0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_ind_dat0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat1",
+			NPPU_ODMA_CFG_IND_DAT1r,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_ind_dat1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fabric_or_saip",
+			NPPU_ODMA_CFG_FABRIC_OR_SAIPr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_fabric_or_saip_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"max_pkt_len",
+			NPPU_ODMA_CFG_MAX_PKT_LENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_max_pkt_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"age_en",
+			NPPU_ODMA_CFG_AGE_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_age_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"age_mode",
+			NPPU_ODMA_CFG_AGE_MODEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_age_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"age_value_time",
+			NPPU_ODMA_CFG_AGE_VALUE_TIMEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x005c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_age_value_time_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"age_value_room",
+			NPPU_ODMA_CFG_AGE_VALUE_ROOMr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_age_value_room_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"age_out_cnt",
+			NPPU_ODMA_CFG_AGE_OUT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_age_out_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"token_value_a",
+			NPPU_ODMA_CFG_TOKEN_VALUE_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0114,
+			(32 / 8),
+			0,
+			59 + 1,
+			0,
+			4,
+			1,
+			g_nppu_odma_cfg_token_value_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"token_value_b",
+			NPPU_ODMA_CFG_TOKEN_VALUE_Br,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0204,
+			(32 / 8),
+			0,
+			1 + 1,
+			0,
+			4,
+			1,
+			g_nppu_odma_cfg_token_value_b_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_shap_en_p0",
+			NPPU_ODMA_CFG_CFG_SHAP_EN_P0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x020c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_cfg_shap_en_p0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_shap_en_p1",
+			NPPU_ODMA_CFG_CFG_SHAP_EN_P1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0210,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_cfg_shap_en_p1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_shap_en_tm",
+			NPPU_ODMA_CFG_CFG_SHAP_EN_TMr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0214,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_cfg_shap_en_tm_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_status",
+			NPPU_ODMA_STAT_IND_STATUSr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_STAT_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_stat_ind_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_cmd",
+			NPPU_ODMA_STAT_IND_CMDr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_STAT_BASE_ADDR + 0x0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_nppu_odma_stat_ind_cmd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_data0",
+			NPPU_ODMA_STAT_IND_DATA0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_STAT_BASE_ADDR + 0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_stat_ind_data0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_cfg",
+			NPPU_ODMA_STAT_DEBUG_CNT_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_STAT_BASE_ADDR + 0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_nppu_odma_stat_debug_cnt_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"bfd_firstchk_th",
+			NPPU_OAM_CFG_BFD_FIRSTCHK_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_bfd_firstchk_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_fc_idmath_ram",
+			NPPU_PBU_CFG_MEMID_0_PBU_FC_IDMATH_RAMr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x0000,
+			(192 / 8),
+			0,
+			127 + 1,
+			0,
+			1,
+			11,
+			g_nppu_pbu_cfg_memid_0_pbu_fc_idmath_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_fc_macth_ram",
+			NPPU_PBU_CFG_MEMID_1_PBU_FC_MACTH_RAMr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x0000,
+			(128 / 8),
+			0,
+			56 + 1,
+			0,
+			1,
+			8,
+			g_nppu_pbu_cfg_memid_1_pbu_fc_macth_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"all_kind_port_cnt",
+			NPPU_PBU_STAT_MEMID_1_ALL_KIND_PORT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x0000,
+			(32 / 8),
+			0,
+			127 + 1,
+			0,
+			1,
+			2,
+			g_nppu_pbu_stat_memid_1_all_kind_port_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_ifb_req_vld_cnt",
+			NPPU_PBU_STAT_MEMID_2_PPU_PBU_IFB_REQ_VLD_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_2_ppu_pbu_ifb_req_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_ifb_rsp_vld_cnt",
+			NPPU_PBU_STAT_MEMID_2_PBU_PPU_IFB_RSP_VLD_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0005,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_2_pbu_ppu_ifb_rsp_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_pbu_recy_ptr_vld_cnt",
+			NPPU_PBU_STAT_MEMID_2_ODMA_PBU_RECY_PTR_VLD_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0006,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_2_odma_pbu_recy_ptr_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_mcode_pf_req_cnt",
+			NPPU_PBU_STAT_MEMID_2_PPU_PBU_MCODE_PF_REQ_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0007,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_2_ppu_pbu_mcode_pf_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_mcode_pf_rsp_cnt",
+			NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_RSP_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_logic_pf_req_cnt",
+			NPPU_PBU_STAT_MEMID_2_PPU_PBU_LOGIC_PF_REQ_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0009,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_2_ppu_pbu_logic_pf_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_logic_pf_rsp_cnt",
+			NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_RSP_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_use_ptr_pulse_cnt",
+			NPPU_PBU_STAT_MEMID_2_PPU_USE_PTR_PULSE_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_2_ppu_use_ptr_pulse_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_wb_vld_cnt",
+			NPPU_PBU_STAT_MEMID_2_PPU_PBU_WB_VLD_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_2_ppu_pbu_wb_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_reorder_para_vld_cnt",
+			NPPU_PBU_STAT_MEMID_2_PBU_PPU_REORDER_PARA_VLD_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_2_pbu_ppu_reorder_para_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_pbu_dpi_key_vld_cnt",
+			NPPU_PBU_STAT_MEMID_2_SE_PBU_DPI_KEY_VLD_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_2_se_pbu_dpi_key_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_se_dpi_rsp_datvld_cnt",
+			NPPU_PBU_STAT_MEMID_2_PBU_SE_DPI_RSP_DATVLD_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_2_pbu_se_dpi_rsp_datvld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_pbu_ifb_rd1_cnt",
+			NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD1_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd1_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_pbu_ifb_rd2_cnt",
+			NPPU_PBU_STAT_MEMID_2_ODMA_PBU_IFB_RD2_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0011,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_2_odma_pbu_ifb_rd2_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_mcode_pf_no_rsp_cnt",
+			NPPU_PBU_STAT_MEMID_2_PBU_PPU_MCODE_PF_NO_RSP_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0015,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_2_pbu_ppu_mcode_pf_no_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_logic_pf_no_rsp_cnt",
+			NPPU_PBU_STAT_MEMID_2_PBU_PPU_LOGIC_PF_NO_RSP_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0016,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_2_pbu_ppu_logic_pf_no_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_ifb_data",
+			NPPU_PBU_STAT_MEMID_3_CPU_RD_IFB_DATAr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x0000,
+			(2048 / 8),
+			0,
+			16383 + 1,
+			0,
+			1,
+			1,
+			g_nppu_pbu_stat_memid_3_cpu_rd_ifb_data_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mux_sel_rgt",
+			NPPU_PBU_STAT_MEMID_4_MUX_SEL_RGTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_memid_4_mux_sel_rgt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port_pub_cnt",
+			NPPU_PBU_STAT_MEMID_5_PORT_PUB_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x0000,
+			(32 / 8),
+			0,
+			127 + 1,
+			0,
+			1,
+			1,
+			g_nppu_pbu_stat_memid_5_port_pub_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"idma_o_isu_pkt_pulse_total_cnt",
+			NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_PKT_PULSE_TOTAL_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0012,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_idma_stat_memid_1_idma_o_isu_pkt_pulse_total_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"idma_o_isu_epkt_pulse_total_cnt",
+			NPPU_IDMA_STAT_MEMID_1_IDMA_O_ISU_EPKT_PULSE_TOTAL_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0013,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_idma_stat_memid_1_idma_o_isu_epkt_pulse_total_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"idma_dispkt_pulse_total_cnt",
+			NPPU_IDMA_STAT_MEMID_1_IDMA_DISPKT_PULSE_TOTAL_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_idma_stat_memid_1_idma_dispkt_pulse_total_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"idma_o_isu_pkt_pulse_cnt",
+			NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_PKT_PULSE_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x0000,
+			(32 / 8),
+			0,
+			127 + 1,
+			0,
+			1,
+			1,
+			g_nppu_idma_stat_memid_0_idma_o_isu_pkt_pulse_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"idma_o_isu_epkt_pulse_cnt",
+			NPPU_IDMA_STAT_MEMID_0_IDMA_O_ISU_EPKT_PULSE_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x0080,
+			(32 / 8),
+			0,
+			127 + 1,
+			0,
+			1,
+			1,
+			g_nppu_idma_stat_memid_0_idma_o_isu_epkt_pulse_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"idma_dispkt_pulse_cnt",
+			NPPU_IDMA_STAT_MEMID_0_IDMA_DISPKT_PULSE_CNTr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x0100,
+			(32 / 8),
+			0,
+			127 + 1,
+			0,
+			1,
+			1,
+			g_nppu_idma_stat_memid_0_idma_dispkt_pulse_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_r",
+			PPU_PPU_TEST_Rr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_test_r_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_debug_en_r",
+			PPU_PPU_PPU_DEBUG_EN_Rr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x00c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_debug_en_r_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csr_dup_table_wr_data",
+			PPU_PPU_CSR_DUP_TABLE_WR_DATAr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_ppu_ppu_csr_dup_table_wr_data_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csr_dup_table_rd_data",
+			PPU_PPU_CSR_DUP_TABLE_RD_DATAr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_ppu_ppu_csr_dup_table_rd_data_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csr_dup_table_addr",
+			PPU_PPU_CSR_DUP_TABLE_ADDRr,
+			PPU,
+			DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x03c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_ppu_ppu_csr_dup_table_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_debug_vld",
+			PPU_PPU_PPU_DEBUG_VLDr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_debug_vld_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cop_thash_rsk_319_288",
+			PPU_PPU_COP_THASH_RSK_319_288r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_cop_thash_rsk_319_288_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cop_thash_rsk_287_256",
+			PPU_PPU_COP_THASH_RSK_287_256r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_cop_thash_rsk_287_256_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cop_thash_rsk_255_224",
+			PPU_PPU_COP_THASH_RSK_255_224r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_cop_thash_rsk_255_224_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cop_thash_rsk_223_192",
+			PPU_PPU_COP_THASH_RSK_223_192r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x05c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_cop_thash_rsk_223_192_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cop_thash_rsk_191_160",
+			PPU_PPU_COP_THASH_RSK_191_160r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_cop_thash_rsk_191_160_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cop_thash_rsk_159_128",
+			PPU_PPU_COP_THASH_RSK_159_128r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_cop_thash_rsk_159_128_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cop_thash_rsk_127_096",
+			PPU_PPU_COP_THASH_RSK_127_096r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_cop_thash_rsk_127_096_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cop_thash_rsk_095_064",
+			PPU_PPU_COP_THASH_RSK_095_064r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x06c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_cop_thash_rsk_095_064_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cop_thash_rsk_063_032",
+			PPU_PPU_COP_THASH_RSK_063_032r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x070,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_cop_thash_rsk_063_032_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cop_thash_rsk_031_000",
+			PPU_PPU_COP_THASH_RSK_031_000r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x074,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_cop_thash_rsk_031_000_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ipv4_ipid_start_value",
+			PPU_PPU_CFG_IPV4_IPID_START_VALUEr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x078,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_cfg_ipv4_ipid_start_value_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ipv4_ipid_end_value",
+			PPU_PPU_CFG_IPV4_IPID_END_VALUEr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x07c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_cfg_ipv4_ipid_end_value_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cluster_mf_in_en",
+			PPU_PPU_CLUSTER_MF_IN_ENr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x150,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_cluster_mf_in_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_empty",
+			PPU_PPU_PPU_EMPTYr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x154,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_empty_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_w_addr",
+			PPU_PPU_INSTRMEM_W_ADDRr,
+			PPU,
+			DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x514,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_instrmem_w_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_w_data_191_160",
+			PPU_PPU_INSTRMEM_W_DATA_191_160r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x518,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_instrmem_w_data_191_160_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_w_data_159_128",
+			PPU_PPU_INSTRMEM_W_DATA_159_128r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x51c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_instrmem_w_data_159_128_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_w_data_127_96",
+			PPU_PPU_INSTRMEM_W_DATA_127_96r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x520,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_instrmem_w_data_127_96_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_w_data_95_64",
+			PPU_PPU_INSTRMEM_W_DATA_95_64r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x524,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_instrmem_w_data_95_64_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_w_data_63_32",
+			PPU_PPU_INSTRMEM_W_DATA_63_32r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x528,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_instrmem_w_data_63_32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_w_data_31_0",
+			PPU_PPU_INSTRMEM_W_DATA_31_0r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x52c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_instrmem_w_data_31_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_fwft_mf_fifo_prog_full_assert_cfg",
+			PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_isu_fwft_mf_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_fwft_mf_fifo_prog_full_negate_cfg",
+			PPU_PPU_ISU_FWFT_MF_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_isu_fwft_mf_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_1200m_mask",
+			PPU_CLUSTER_INT_1200M_MASKr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x98,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			8,
+			g_ppu_cluster_int_1200m_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"wr_high_data_r_mex",
+			PPU4K_CLUSTER_WR_HIGH_DATA_R_MEXr,
+			PPU4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4000,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu4k_cluster_wr_high_data_r_mex_reg,
+			dpp_ppu_write,
+			dpp_ppu_read,
+	},
+	{
+			"wr_low_data_r_mex",
+			PPU4K_CLUSTER_WR_LOW_DATA_R_MEXr,
+			PPU4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4004,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu4k_cluster_wr_low_data_r_mex_reg,
+			dpp_ppu_write,
+			dpp_ppu_read,
+	},
+	{
+			"addr_r_mex",
+			PPU4K_CLUSTER_ADDR_R_MEXr,
+			PPU4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4008,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			2,
+			g_ppu4k_cluster_addr_r_mex_reg,
+			dpp_ppu_write,
+			dpp_ppu_read,
+	},
+	{
+			"sdt_tbl_ind_access_done",
+			PPU4K_CLUSTER_SDT_TBL_IND_ACCESS_DONEr,
+			PPU4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x400c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu4k_cluster_sdt_tbl_ind_access_done_reg,
+			dpp_ppu_write,
+			dpp_ppu_read,
+	},
+	{
+			"rd_high_data_r_mex",
+			PPU4K_CLUSTER_RD_HIGH_DATA_R_MEXr,
+			PPU4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4010,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu4k_cluster_rd_high_data_r_mex_reg,
+			dpp_ppu_write,
+			dpp_ppu_read,
+	},
+	{
+			"rd_low_data_r_mex",
+			PPU4K_CLUSTER_RD_LOW_DATA_R_MEXr,
+			PPU4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4014,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu4k_cluster_rd_low_data_r_mex_reg,
+			dpp_ppu_write,
+			dpp_ppu_read,
+	},
+	{
+			"init_ok",
+			SE_ALG_INIT_OKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_init_ok_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_rdy",
+			SE_ALG_CPU_RD_RDYr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_data_tmp0",
+			SE_ALG_CPU_RD_DATA_TMP0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_data_tmp0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_data_tmp1",
+			SE_ALG_CPU_RD_DATA_TMP1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_data_tmp1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_data_tmp2",
+			SE_ALG_CPU_RD_DATA_TMP2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_data_tmp2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_data_tmp3",
+			SE_ALG_CPU_RD_DATA_TMP3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_data_tmp3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_data_tmp4",
+			SE_ALG_CPU_RD_DATA_TMP4r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x005c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_data_tmp4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_data_tmp5",
+			SE_ALG_CPU_RD_DATA_TMP5r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_data_tmp5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_data_tmp6",
+			SE_ALG_CPU_RD_DATA_TMP6r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_data_tmp6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_data_tmp7",
+			SE_ALG_CPU_RD_DATA_TMP7r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_data_tmp7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_data_tmp8",
+			SE_ALG_CPU_RD_DATA_TMP8r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x006c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_data_tmp8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_data_tmp9",
+			SE_ALG_CPU_RD_DATA_TMP9r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0070,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_data_tmp9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_data_tmp10",
+			SE_ALG_CPU_RD_DATA_TMP10r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0074,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_data_tmp10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_data_tmp11",
+			SE_ALG_CPU_RD_DATA_TMP11r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0078,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_data_tmp11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_data_tmp12",
+			SE_ALG_CPU_RD_DATA_TMP12r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x007c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_data_tmp12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_data_tmp13",
+			SE_ALG_CPU_RD_DATA_TMP13r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_data_tmp13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_data_tmp14",
+			SE_ALG_CPU_RD_DATA_TMP14r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_data_tmp14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_data_tmp15",
+			SE_ALG_CPU_RD_DATA_TMP15r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_cpu_rd_data_tmp15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_v4_config_rgt",
+			SE_ALG_LPM_V4_CONFIG_RGTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x014c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_se_alg_lpm_v4_config_rgt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_v6_config_rgt",
+			SE_ALG_LPM_V6_CONFIG_RGTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0150,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_se_alg_lpm_v6_config_rgt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_ext_rsp_fifo_u0_pfull_ast",
+			SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x015c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_ext_rsp_fifo_u0_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_age_pat_cfg",
+			SE_AS_HASH_AGE_PAT_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_hash_age_pat_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"learn_rdy_cfg",
+			SE_AS_LEARN_RDY_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_learn_rdy_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_as_pful_cfg",
+			SE_KSCHD_KSCHD_AS_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_kschd_as_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_dir_pful_cfg",
+			SE_KSCHD_KSCHD_DIR_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_kschd_dir_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_as_ept_cfg",
+			SE_KSCHD_KSCHD_AS_EPT_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_kschd_as_ept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_arbi_pful_cfg",
+			SE_KSCHD_CPU_ARBI_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_cpu_arbi_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_pbu_pful_cfg",
+			SE_KSCHD_KSCHD_PBU_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_kschd_pbu_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_dir_pful_cfg",
+			SE_RSCHD_RSCHD_DIR_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_dir_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_dir_ept_cfg",
+			SE_RSCHD_RSCHD_DIR_EPT_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_dir_ept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_cmd_rgt",
+			SE4K_SE_ALG_CPU_CMD_RGTr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			7,
+			g_se4k_se_alg_cpu_cmd_rgt_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_wr_data_tmp0",
+			SE4K_SE_ALG_CPU_WR_DATA_TMP0r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_wr_data_tmp0_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_wr_data_tmp1",
+			SE4K_SE_ALG_CPU_WR_DATA_TMP1r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_wr_data_tmp1_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_wr_data_tmp2",
+			SE4K_SE_ALG_CPU_WR_DATA_TMP2r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_wr_data_tmp2_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_wr_data_tmp3",
+			SE4K_SE_ALG_CPU_WR_DATA_TMP3r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_wr_data_tmp3_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_wr_data_tmp4",
+			SE4K_SE_ALG_CPU_WR_DATA_TMP4r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_wr_data_tmp4_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_wr_data_tmp5",
+			SE4K_SE_ALG_CPU_WR_DATA_TMP5r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_wr_data_tmp5_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_wr_data_tmp6",
+			SE4K_SE_ALG_CPU_WR_DATA_TMP6r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_wr_data_tmp6_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_wr_data_tmp7",
+			SE4K_SE_ALG_CPU_WR_DATA_TMP7r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_wr_data_tmp7_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_wr_data_tmp8",
+			SE4K_SE_ALG_CPU_WR_DATA_TMP8r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_wr_data_tmp8_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_wr_data_tmp9",
+			SE4K_SE_ALG_CPU_WR_DATA_TMP9r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x002c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_wr_data_tmp9_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_wr_data_tmp10",
+			SE4K_SE_ALG_CPU_WR_DATA_TMP10r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_wr_data_tmp10_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_wr_data_tmp11",
+			SE4K_SE_ALG_CPU_WR_DATA_TMP11r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_wr_data_tmp11_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_wr_data_tmp12",
+			SE4K_SE_ALG_CPU_WR_DATA_TMP12r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_wr_data_tmp12_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_wr_data_tmp13",
+			SE4K_SE_ALG_CPU_WR_DATA_TMP13r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x003c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_wr_data_tmp13_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_wr_data_tmp14",
+			SE4K_SE_ALG_CPU_WR_DATA_TMP14r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_wr_data_tmp14_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_wr_data_tmp15",
+			SE4K_SE_ALG_CPU_WR_DATA_TMP15r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_wr_data_tmp15_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_rdy",
+			SE4K_SE_ALG_CPU_RD_RDYr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_rdy_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_data_tmp0",
+			SE4K_SE_ALG_CPU_RD_DATA_TMP0r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_data_tmp0_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_data_tmp1",
+			SE4K_SE_ALG_CPU_RD_DATA_TMP1r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_data_tmp1_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_data_tmp2",
+			SE4K_SE_ALG_CPU_RD_DATA_TMP2r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_data_tmp2_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_data_tmp3",
+			SE4K_SE_ALG_CPU_RD_DATA_TMP3r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_data_tmp3_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_data_tmp4",
+			SE4K_SE_ALG_CPU_RD_DATA_TMP4r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x005c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_data_tmp4_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_data_tmp5",
+			SE4K_SE_ALG_CPU_RD_DATA_TMP5r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_data_tmp5_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_data_tmp6",
+			SE4K_SE_ALG_CPU_RD_DATA_TMP6r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_data_tmp6_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_data_tmp7",
+			SE4K_SE_ALG_CPU_RD_DATA_TMP7r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_data_tmp7_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_data_tmp8",
+			SE4K_SE_ALG_CPU_RD_DATA_TMP8r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x006c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_data_tmp8_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_data_tmp9",
+			SE4K_SE_ALG_CPU_RD_DATA_TMP9r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0070,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_data_tmp9_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_data_tmp10",
+			SE4K_SE_ALG_CPU_RD_DATA_TMP10r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0074,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_data_tmp10_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_data_tmp11",
+			SE4K_SE_ALG_CPU_RD_DATA_TMP11r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0078,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_data_tmp11_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_data_tmp12",
+			SE4K_SE_ALG_CPU_RD_DATA_TMP12r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x007c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_data_tmp12_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_data_tmp13",
+			SE4K_SE_ALG_CPU_RD_DATA_TMP13r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_data_tmp13_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_data_tmp14",
+			SE4K_SE_ALG_CPU_RD_DATA_TMP14r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_data_tmp14_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_rd_data_tmp15",
+			SE4K_SE_ALG_CPU_RD_DATA_TMP15r,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_cpu_rd_data_tmp15_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash0_ext_cfg_rgt",
+			SE4K_SE_ALG_HASH0_EXT_CFG_RGTr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se4k_se_alg_hash0_ext_cfg_rgt_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash1_ext_cfg_rgt",
+			SE4K_SE_ALG_HASH1_EXT_CFG_RGTr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se4k_se_alg_hash1_ext_cfg_rgt_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash2_ext_cfg_rgt",
+			SE4K_SE_ALG_HASH2_EXT_CFG_RGTr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se4k_se_alg_hash2_ext_cfg_rgt_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash3_ext_cfg_rgt",
+			SE4K_SE_ALG_HASH3_EXT_CFG_RGTr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se4k_se_alg_hash3_ext_cfg_rgt_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash0_tbl30_depth",
+			SE4K_SE_ALG_HASH0_TBL30_DEPTHr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_se4k_se_alg_hash0_tbl30_depth_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash0_tbl74_depth",
+			SE4K_SE_ALG_HASH0_TBL74_DEPTHr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_se4k_se_alg_hash0_tbl74_depth_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash1_tbl30_depth",
+			SE4K_SE_ALG_HASH1_TBL30_DEPTHr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_se4k_se_alg_hash1_tbl30_depth_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash1_tbl74_depth",
+			SE4K_SE_ALG_HASH1_TBL74_DEPTHr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_se4k_se_alg_hash1_tbl74_depth_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash2_tbl30_depth",
+			SE4K_SE_ALG_HASH2_TBL30_DEPTHr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_se4k_se_alg_hash2_tbl30_depth_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash2_tbl74_depth",
+			SE4K_SE_ALG_HASH2_TBL74_DEPTHr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_se4k_se_alg_hash2_tbl74_depth_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash3_tbl30_depth",
+			SE4K_SE_ALG_HASH3_TBL30_DEPTHr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_se4k_se_alg_hash3_tbl30_depth_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash3_tbl74_depth",
+			SE4K_SE_ALG_HASH3_TBL74_DEPTHr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_se4k_se_alg_hash3_tbl74_depth_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"wr_rsp_cfg",
+			SE4K_SE_ALG_WR_RSP_CFGr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se4k_se_alg_wr_rsp_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash_mono_flag",
+			SE4K_SE_ALG_HASH_MONO_FLAGr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_se4k_se_alg_hash_mono_flag_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash10_ext_crc_cfg",
+			SE4K_SE_ALG_HASH10_EXT_CRC_CFGr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se4k_se_alg_hash10_ext_crc_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash32_ext_crc_cfg",
+			SE4K_SE_ALG_HASH32_EXT_CRC_CFGr,
+			SE4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se4k_se_alg_hash32_ext_crc_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"zblock_service_configure",
+			SE4K_SE_ALG_ZBLOCK_SERVICE_CONFIGUREr,
+			SE4K,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x10000,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			3,
+			g_se4k_se_alg_zblock_service_configure_reg,
+			dpp_se_alg_write,
+			dpp_se_alg_read,
+	},
+	{
+			"zblock_hash_zcell_mono",
+			SE4K_SE_ALG_ZBLOCK_HASH_ZCELL_MONOr,
+			SE4K,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x10014,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			8,
+			g_se4k_se_alg_zblock_hash_zcell_mono_reg,
+			dpp_se_alg_write,
+			dpp_se_alg_read,
+	},
+	{
+			"zlock_hash_zreg_mono",
+			SE4K_SE_ALG_ZLOCK_HASH_ZREG_MONOr,
+			SE4K,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x10015,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			8,
+			g_se4k_se_alg_zlock_hash_zreg_mono_reg,
+			dpp_se_alg_write,
+			dpp_se_alg_read,
+	},
+	{
+			"init_done",
+			SMMU0_SMMU0_INIT_DONEr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_init_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat0",
+			SMMU0_SMMU0_CPU_IND_WDAT0r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cpu_ind_wdat0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat1",
+			SMMU0_SMMU0_CPU_IND_WDAT1r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cpu_ind_wdat1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat2",
+			SMMU0_SMMU0_CPU_IND_WDAT2r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cpu_ind_wdat2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat3",
+			SMMU0_SMMU0_CPU_IND_WDAT3r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cpu_ind_wdat3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_cmd",
+			SMMU0_SMMU0_CPU_IND_CMDr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_smmu0_smmu0_cpu_ind_cmd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_rd_done",
+			SMMU0_SMMU0_CPU_IND_RD_DONEr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cpu_ind_rd_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_rdat0",
+			SMMU0_SMMU0_CPU_IND_RDAT0r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cpu_ind_rdat0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_rdat1",
+			SMMU0_SMMU0_CPU_IND_RDAT1r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cpu_ind_rdat1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_rdat2",
+			SMMU0_SMMU0_CPU_IND_RDAT2r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cpu_ind_rdat2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_rdat3",
+			SMMU0_SMMU0_CPU_IND_RDAT3r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cpu_ind_rdat3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_plcr_mono",
+			SMMU0_SMMU0_CFG_PLCR_MONOr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000108,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cfg_plcr_mono_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"wr_arb_cpu_rdy",
+			SMMU0_SMMU0_WR_ARB_CPU_RDYr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000010c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_wr_arb_cpu_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_stat_en_cfg",
+			SMMU0_SMMU0_TM_STAT_EN_CFGr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000110,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_tm_stat_en_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wdat0",
+			SE_SMMU1_DDR_WDAT0r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ddr_wdat0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dir_arbi_ser_rpful",
+			SE_SMMU1_DIR_ARBI_SER_RPFULr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000010c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_dir_arbi_ser_rpful_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_wr_arbi_pful2",
+			SE_SMMU1_CFG_WR_ARBI_PFUL2r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000120,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_smmu1_cfg_wr_arbi_pful2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_tbl_cfg",
+			SE_SMMU1_ETM_TBL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_etm_tbl_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_cash_addr_pful",
+			SE_SMMU1_CFG_CASH_ADDR_PFULr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000020c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cfg_cash_addr_pful_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_rfifo_cfg",
+			SE_SMMU1_CTRL_RFIFO_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000234,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_se_smmu1_ctrl_rfifo_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cache_req_fifo_cfg",
+			SE_SMMU1_CACHE_REQ_FIFO_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000288,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_smmu1_cache_req_fifo_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_eram_wdat0",
+			STAT_STAT_CFG_CPU_IND_ERAM_WDAT0r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_eram_wdat0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_port_sel_cfg",
+			STAT_STAT_CFG_ETM_PORT_SEL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_stat_stat_cfg_etm_port_sel_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_stat_cfg",
+			STAT_STAT_CFG_TM_STAT_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_stat_stat_cfg_tm_stat_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_eram_depth",
+			STAT_STAT_CFG_PPU_ERAM_DEPTHr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_ppu_eram_depth_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_eram_base_addr",
+			STAT_STAT_CFG_PPU_ERAM_BASE_ADDRr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_ppu_eram_base_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_ddr_base_addr",
+			STAT_STAT_CFG_PPU_DDR_BASE_ADDRr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_ppu_ddr_base_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"plcr0_base_addr",
+			STAT_STAT_CFG_PLCR0_BASE_ADDRr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000006c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_plcr0_base_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_stat_start_addr_cfg",
+			STAT_STAT_CFG_ETM_STAT_START_ADDR_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_etm_stat_start_addr_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_stat_depth_cfg",
+			STAT_STAT_CFG_ETM_STAT_DEPTH_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_etm_stat_depth_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cycle_mov_en_cfg",
+			STAT_STAT_CFG_CYCLE_MOV_EN_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cycle_mov_en_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat0",
+			STAT_ETCAM_CPU_IND_WDAT0r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ctrl_tmp0",
+			STAT_ETCAM_CPU_IND_CTRL_TMP0r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			7,
+			g_stat_etcam_cpu_ind_ctrl_tmp0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ctrl_tmp1",
+			STAT_ETCAM_CPU_IND_CTRL_TMP1r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_stat_etcam_cpu_ind_ctrl_tmp1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_rd_done",
+			STAT_ETCAM_CPU_IND_RD_DONEr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x000001fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_rd_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat0",
+			STAT_ETCAM_CPU_RDAT0r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000200,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat1",
+			STAT_ETCAM_CPU_RDAT1r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000204,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat2",
+			STAT_ETCAM_CPU_RDAT2r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000208,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat3",
+			STAT_ETCAM_CPU_RDAT3r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000020c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat4",
+			STAT_ETCAM_CPU_RDAT4r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000210,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat5",
+			STAT_ETCAM_CPU_RDAT5r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000214,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat6",
+			STAT_ETCAM_CPU_RDAT6r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000218,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat7",
+			STAT_ETCAM_CPU_RDAT7r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000021c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat8",
+			STAT_ETCAM_CPU_RDAT8r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000220,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat9",
+			STAT_ETCAM_CPU_RDAT9r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000224,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat10",
+			STAT_ETCAM_CPU_RDAT10r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000228,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat11",
+			STAT_ETCAM_CPU_RDAT11r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000022c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat12",
+			STAT_ETCAM_CPU_RDAT12r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000230,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat13",
+			STAT_ETCAM_CPU_RDAT13r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000234,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat14",
+			STAT_ETCAM_CPU_RDAT14r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000238,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat15",
+			STAT_ETCAM_CPU_RDAT15r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000023c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat16",
+			STAT_ETCAM_CPU_RDAT16r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000240,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat17",
+			STAT_ETCAM_CPU_RDAT17r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000244,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat18",
+			STAT_ETCAM_CPU_RDAT18r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000248,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat19",
+			STAT_ETCAM_CPU_RDAT19r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000024c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_rdat19_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qvbo",
+			STAT_ETCAM_QVBOr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000250,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_qvbo_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_overflow_mode",
+			STAT_ETCAM_CNT_OVERFLOW_MODEr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x000003ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_etcam_cnt_overflow_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_queue_ram0_159_0",
+			STAT_CAR0_CARA_QUEUE_RAM0_159_0r,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x000000 + 0x14000000,
+			(160 / 8),
+			0,
+			0x7FFF + 1,
+			0,
+			8,
+			9,
+			g_stat_car0_cara_queue_ram0_159_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_profile_ram1_255_0",
+			STAT_CAR0_CARA_PROFILE_RAM1_255_0r,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x040000 + 0x20000000,
+			(256 / 8),
+			0,
+			0x1FF + 1,
+			0,
+			8,
+			31,
+			g_stat_car0_cara_profile_ram1_255_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_qovs_ram_ram2",
+			STAT_CAR0_CARA_QOVS_RAM_RAM2r,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x80000,
+			(32 / 8),
+			0,
+			0x7FFF + 1,
+			0,
+			1,
+			1,
+			g_stat_car0_cara_qovs_ram_ram2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"look_up_table1",
+			STAT_CAR0_LOOK_UP_TABLE1r,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0xc0000,
+			(32 / 8),
+			0,
+			0x7FFF + 1,
+			0,
+			1,
+			2,
+			g_stat_car0_look_up_table1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_pkt_des_i_cnt",
+			STAT_CAR0_CARA_PKT_DES_I_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c0000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_cara_pkt_des_i_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_green_pkt_i_cnt",
+			STAT_CAR0_CARA_GREEN_PKT_I_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c0001,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_cara_green_pkt_i_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_yellow_pkt_i_cnt",
+			STAT_CAR0_CARA_YELLOW_PKT_I_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c0002,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_cara_yellow_pkt_i_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_red_pkt_i_cnt",
+			STAT_CAR0_CARA_RED_PKT_I_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c0003,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_cara_red_pkt_i_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_pkt_des_o_cnt",
+			STAT_CAR0_CARA_PKT_DES_O_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_cara_pkt_des_o_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_green_pkt_o_cnt",
+			STAT_CAR0_CARA_GREEN_PKT_O_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c0005,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_cara_green_pkt_o_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_yellow_pkt_o_cnt",
+			STAT_CAR0_CARA_YELLOW_PKT_O_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c0006,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_cara_yellow_pkt_o_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_red_pkt_o_cnt",
+			STAT_CAR0_CARA_RED_PKT_O_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c0007,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_cara_red_pkt_o_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_pkt_des_fc_for_cfg_cnt",
+			STAT_CAR0_CARA_PKT_DES_FC_FOR_CFG_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_cara_pkt_des_fc_for_cfg_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_appoint_qnum_or_sp",
+			STAT_CAR0_CARA_APPOINT_QNUM_OR_SPr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c0009,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_stat_car0_cara_appoint_qnum_or_sp_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_cfgmt_count_mode",
+			STAT_CAR0_CARA_CFGMT_COUNT_MODEr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c000a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_car0_cara_cfgmt_count_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_pkt_size_cnt",
+			STAT_CAR0_CARA_PKT_SIZE_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c000b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_cara_pkt_size_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_plcr_init_dont",
+			STAT_CAR0_CARA_PLCR_INIT_DONTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_cara_plcr_init_dont_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_queue_ram0_159_0",
+			STAT_CAR0_CARB_QUEUE_RAM0_159_0r,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x100000 + 0x14000000,
+			(160 / 8),
+			0,
+			0xFFF + 1,
+			0,
+			8,
+			9,
+			g_stat_car0_carb_queue_ram0_159_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_profile_ram1_255_0",
+			STAT_CAR0_CARB_PROFILE_RAM1_255_0r,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x140000 + 0x20000000,
+			(256 / 8),
+			0,
+			0x7F + 1,
+			0,
+			8,
+			33,
+			g_stat_car0_carb_profile_ram1_255_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_qovs_ram_ram2",
+			STAT_CAR0_CARB_QOVS_RAM_RAM2r,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x180000,
+			(32 / 8),
+			0,
+			0xFFF + 1,
+			0,
+			1,
+			1,
+			g_stat_car0_carb_qovs_ram_ram2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"look_up_table2",
+			STAT_CAR0_LOOK_UP_TABLE2r,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x1c0000,
+			(32 / 8),
+			0,
+			0xFFF + 1,
+			0,
+			1,
+			2,
+			g_stat_car0_look_up_table2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_pkt_des_i_cnt",
+			STAT_CAR0_CARB_PKT_DES_I_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c1000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carb_pkt_des_i_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_green_pkt_i_cnt",
+			STAT_CAR0_CARB_GREEN_PKT_I_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c1001,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carb_green_pkt_i_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_yellow_pkt_i_cnt",
+			STAT_CAR0_CARB_YELLOW_PKT_I_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c1002,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carb_yellow_pkt_i_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_red_pkt_i_cnt",
+			STAT_CAR0_CARB_RED_PKT_I_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c1003,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carb_red_pkt_i_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_pkt_des_o_cnt",
+			STAT_CAR0_CARB_PKT_DES_O_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c1004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carb_pkt_des_o_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_green_pkt_o_cnt",
+			STAT_CAR0_CARB_GREEN_PKT_O_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c1005,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carb_green_pkt_o_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_yellow_pkt_o_cnt",
+			STAT_CAR0_CARB_YELLOW_PKT_O_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c1006,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carb_yellow_pkt_o_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_red_pkt_o_cnt",
+			STAT_CAR0_CARB_RED_PKT_O_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c1007,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carb_red_pkt_o_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_pkt_des_fc_for_cfg_cnt",
+			STAT_CAR0_CARB_PKT_DES_FC_FOR_CFG_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c1008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carb_pkt_des_fc_for_cfg_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_appoint_qnum_or_sp",
+			STAT_CAR0_CARB_APPOINT_QNUM_OR_SPr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c1009,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_stat_car0_carb_appoint_qnum_or_sp_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_cfgmt_count_mode",
+			STAT_CAR0_CARB_CFGMT_COUNT_MODEr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c100a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_car0_carb_cfgmt_count_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_pkt_size_cnt",
+			STAT_CAR0_CARB_PKT_SIZE_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c100b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carb_pkt_size_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_plcr_init_dont",
+			STAT_CAR0_CARB_PLCR_INIT_DONTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c100c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carb_plcr_init_dont_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_queue_ram0_159_0",
+			STAT_CAR0_CARC_QUEUE_RAM0_159_0r,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x200000 + 0x14000000,
+			(160 / 8),
+			0,
+			0x3FF + 1,
+			0,
+			8,
+			9,
+			g_stat_car0_carc_queue_ram0_159_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_profile_ram1_255_0",
+			STAT_CAR0_CARC_PROFILE_RAM1_255_0r,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x240000 + 0x20000000,
+			(256 / 8),
+			0,
+			0x1F + 1,
+			0,
+			8,
+			33,
+			g_stat_car0_carc_profile_ram1_255_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_qovs_ram_ram2",
+			STAT_CAR0_CARC_QOVS_RAM_RAM2r,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x280000,
+			(32 / 8),
+			0,
+			0x3FF + 1,
+			0,
+			1,
+			1,
+			g_stat_car0_carc_qovs_ram_ram2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_pkt_des_i_cnt",
+			STAT_CAR0_CARC_PKT_DES_I_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c2000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carc_pkt_des_i_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_green_pkt_i_cnt",
+			STAT_CAR0_CARC_GREEN_PKT_I_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c2001,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carc_green_pkt_i_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_yellow_pkt_i_cnt",
+			STAT_CAR0_CARC_YELLOW_PKT_I_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c2002,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carc_yellow_pkt_i_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_red_pkt_i_cnt",
+			STAT_CAR0_CARC_RED_PKT_I_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c2003,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carc_red_pkt_i_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_pkt_des_o_cnt",
+			STAT_CAR0_CARC_PKT_DES_O_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c2004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carc_pkt_des_o_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_green_pkt_o_cnt",
+			STAT_CAR0_CARC_GREEN_PKT_O_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c2005,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carc_green_pkt_o_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_yellow_pkt_o_cnt",
+			STAT_CAR0_CARC_YELLOW_PKT_O_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c2006,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carc_yellow_pkt_o_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_red_pkt_o_cnt",
+			STAT_CAR0_CARC_RED_PKT_O_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c2007,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carc_red_pkt_o_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_pkt_des_fc_for_cfg_cnt",
+			STAT_CAR0_CARC_PKT_DES_FC_FOR_CFG_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c2008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carc_pkt_des_fc_for_cfg_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_appoint_qnum_or_sp",
+			STAT_CAR0_CARC_APPOINT_QNUM_OR_SPr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c2009,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_stat_car0_carc_appoint_qnum_or_sp_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_cfgmt_count_mode",
+			STAT_CAR0_CARC_CFGMT_COUNT_MODEr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c200a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_car0_carc_cfgmt_count_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_pkt_size_cnt",
+			STAT_CAR0_CARC_PKT_SIZE_CNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c200b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carc_pkt_size_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_plcr_init_dont",
+			STAT_CAR0_CARC_PLCR_INIT_DONTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c200c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carc_plcr_init_dont_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_random_ram",
+			STAT_CAR0_CARB_RANDOM_RAMr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x2d0000 + 0x40000000,
+			(512 / 8),
+			0,
+			0x1f + 1,
+			0,
+			16,
+			24,
+			g_stat_car0_carb_random_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_random_ram",
+			STAT_CAR0_CARC_RANDOM_RAMr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x2e0000 + 0x40000000,
+			(512 / 8),
+			0,
+			0x7 + 1,
+			0,
+			16,
+			24,
+			g_stat_car0_carc_random_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_begin_flow_id",
+			STAT_CAR0_CARA_BEGIN_FLOW_IDr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_cara_begin_flow_id_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carb_begin_flow_id",
+			STAT_CAR0_CARB_BEGIN_FLOW_IDr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300001,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carb_begin_flow_id_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"carc_begin_flow_id",
+			STAT_CAR0_CARC_BEGIN_FLOW_IDr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300002,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_carc_begin_flow_id_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"prog_full_assert_cfg_w",
+			STAT_CAR0_PROG_FULL_ASSERT_CFG_Wr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300003,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_prog_full_assert_cfg_w_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"prog_full_negate_cfg_w",
+			STAT_CAR0_PROG_FULL_NEGATE_CFG_Wr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_prog_full_negate_cfg_w_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"timeout_limit",
+			STAT_CAR0_TIMEOUT_LIMITr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300005,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_timeout_limit_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_des_fifo_overflow",
+			STAT_CAR0_PKT_DES_FIFO_OVERFLOWr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300006,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_pkt_des_fifo_overflow_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_des_fifo_underflow",
+			STAT_CAR0_PKT_DES_FIFO_UNDERFLOWr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300007,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_pkt_des_fifo_underflow_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_des_fifo_prog_full",
+			STAT_CAR0_PKT_DES_FIFO_PROG_FULLr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_pkt_des_fifo_prog_full_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_des_fifo_prog_empty",
+			STAT_CAR0_PKT_DES_FIFO_PROG_EMPTYr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300009,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_pkt_des_fifo_prog_empty_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_des_fifo_full",
+			STAT_CAR0_PKT_DES_FIFO_FULLr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x30000a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_pkt_des_fifo_full_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_des_fifo_empty",
+			STAT_CAR0_PKT_DES_FIFO_EMPTYr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x30000b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_pkt_des_fifo_empty_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_size_offset",
+			STAT_CAR0_PKT_SIZE_OFFSETr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x30000e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_pkt_size_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"car_plcr_init_dont",
+			STAT_CAR0_CAR_PLCR_INIT_DONTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x30000f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_car_plcr_init_dont_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"max_pkt_size_a",
+			STAT_CAR0_MAX_PKT_SIZE_Ar,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_max_pkt_size_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"max_pkt_size_b",
+			STAT_CAR0_MAX_PKT_SIZE_Br,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300011,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_max_pkt_size_b_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"max_pkt_size_c",
+			STAT_CAR0_MAX_PKT_SIZE_Cr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300012,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_max_pkt_size_c_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"car_hierarchy_mode",
+			STAT_CAR0_CAR_HIERARCHY_MODEr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300013,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_car_hierarchy_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"prog_empty_assert_cfg_w",
+			STAT_CAR0_PROG_EMPTY_ASSERT_CFG_Wr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_prog_empty_assert_cfg_w_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"prog_empty_negate_cfg_w",
+			STAT_CAR0_PROG_EMPTY_NEGATE_CFG_Wr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300015,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_prog_empty_negate_cfg_w_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_des_fifo_ovf_int",
+			STAT_CAR0_PKT_DES_FIFO_OVF_INTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300016,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_pkt_des_fifo_ovf_int_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_des_fifo_data_count",
+			STAT_CAR0_PKT_DES_FIFO_DATA_COUNTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300017,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_pkt_des_fifo_data_count_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_des_fifo_udf_int",
+			STAT_CAR0_PKT_DES_FIFO_UDF_INTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x300018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_car0_pkt_des_fifo_udf_int_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_queue_ram0_159_0_pkt",
+			STAT_CAR0_CARA_QUEUE_RAM0_159_0_PKTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x000000 + 0x14000000,
+			(160 / 8),
+			0,
+			0x7FFF + 1,
+			0,
+			8,
+			8,
+			g_stat_car0_cara_queue_ram0_159_0_pkt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cara_profile_ram1_255_0_pkt",
+			STAT_CAR0_CARA_PROFILE_RAM1_255_0_PKTr,
+			STAT,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x040000 + 0x20000000,
+			(256 / 8),
+			0,
+			0x1FF + 1,
+			0,
+			8,
+			12,
+			g_stat_car0_cara_profile_ram1_255_0_pkt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"block0_7_port_id_cfg",
+			STAT4K_ETCAM_BLOCK0_7_PORT_ID_CFGr,
+			STAT4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000005c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			8,
+			g_stat4k_etcam_block0_7_port_id_cfg_reg,
+			dpp_write,
+			dpp_read,
+	},
+	{
+			"block0_3_base_addr_cfg",
+			STAT4K_ETCAM_BLOCK0_3_BASE_ADDR_CFGr,
+			STAT4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_stat4k_etcam_block0_3_base_addr_cfg_reg,
+			dpp_write,
+			dpp_read,
+	},
+	{
+			"block4_7_base_addr_cfg",
+			STAT4K_ETCAM_BLOCK4_7_BASE_ADDR_CFGr,
+			STAT4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_stat4k_etcam_block4_7_base_addr_cfg_reg,
+			dpp_write,
+			dpp_read,
+	},
+	{
+			"cfg_eram_wr_interval_cnt",
+			DTB_DTB_CFG_CFG_ERAM_WR_INTERVAL_CNTr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_eram_wr_interval_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_zcam_wr_interval_cnt",
+			DTB_DTB_CFG_CFG_ZCAM_WR_INTERVAL_CNTr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_zcam_wr_interval_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tcam_wr_interval_cnt",
+			DTB_DTB_CFG_CFG_TCAM_WR_INTERVAL_CNTr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_tcam_wr_interval_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddr_wr_interval_cnt",
+			DTB_DTB_CFG_CFG_DDR_WR_INTERVAL_CNTr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_ddr_wr_interval_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_hash_wr_interval_cnt",
+			DTB_DTB_CFG_CFG_HASH_WR_INTERVAL_CNTr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_hash_wr_interval_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_eram_rd_interval_cnt",
+			DTB_DTB_CFG_CFG_ERAM_RD_INTERVAL_CNTr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_eram_rd_interval_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_zcam_rd_interval_cnt",
+			DTB_DTB_CFG_CFG_ZCAM_RD_INTERVAL_CNTr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x005c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_zcam_rd_interval_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tcam_rd_interval_cnt",
+			DTB_DTB_CFG_CFG_TCAM_RD_INTERVAL_CNTr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_tcam_rd_interval_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddr_rd_interval_cnt",
+			DTB_DTB_CFG_CFG_DDR_RD_INTERVAL_CNTr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_ddr_rd_interval_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_dtb_queue_lock_state_0_3",
+			DTB_DTB_CFG_CFG_DTB_QUEUE_LOCK_STATE_0_3r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0080,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_dtb_dtb_cfg_cfg_dtb_queue_lock_state_0_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"w_convert_0_mode",
+			DTB_DTB_AXIM0_W_CONVERT_0_MODEr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_AXIM0_BASE_ADDR + 0x6060,
+			(32 / 8),
+			0,
+			1 + 1,
+			0,
+			256,
+			1,
+			g_dtb_dtb_axim0_w_convert_0_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"r_convert_0_mode",
+			DTB_DTB_AXIM0_R_CONVERT_0_MODEr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_AXIM0_BASE_ADDR + 0x2060,
+			(32 / 8),
+			0,
+			1 + 1,
+			0,
+			256,
+			1,
+			g_dtb_dtb_axim0_r_convert_0_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"aximr_os",
+			DTB_DTB_AXIM0_AXIMR_OSr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_AXIM0_BASE_ADDR + 0x2000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_axim0_aximr_os_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"w_convert_1_mode",
+			DTB_DTB_AXIM1_W_CONVERT_1_MODEr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_AXIM1_BASE_ADDR + 0x6060,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			256,
+			1,
+			g_dtb_dtb_axim1_w_convert_1_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"r_convert_1_mode",
+			DTB_DTB_AXIM1_R_CONVERT_1_MODEr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_AXIM1_BASE_ADDR + 0x2060,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			256,
+			1,
+			g_dtb_dtb_axim1_r_convert_1_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"axis_convert_mode",
+			DTB_DTB_AXIS_AXIS_CONVERT_MODEr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_AXIS_BASE_ADDR + 0x0450,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_axis_axis_convert_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_queue_dtb_addr_h_0_127",
+			DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_H_0_127r,
+			DTB4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			127 + 1,
+			0,
+			32,
+			1,
+			g_dtb4k_dtb_enq_cfg_queue_dtb_addr_h_0_127_reg,
+			dpp_write,
+			dpp_read,
+	},
+	{
+			"cfg_queue_dtb_addr_l_0_127",
+			DTB4K_DTB_ENQ_CFG_QUEUE_DTB_ADDR_L_0_127r,
+			DTB4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR + 0x0004,
+			(32 / 8),
+			0,
+			127 + 1,
+			0,
+			32,
+			1,
+			g_dtb4k_dtb_enq_cfg_queue_dtb_addr_l_0_127_reg,
+			dpp_write,
+			dpp_read,
+	},
+	{
+			"cfg_queue_dtb_len_0_127",
+			DTB4K_DTB_ENQ_CFG_QUEUE_DTB_LEN_0_127r,
+			DTB4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR + 0x0008,
+			(32 / 8),
+			0,
+			127 + 1,
+			0,
+			32,
+			3,
+			g_dtb4k_dtb_enq_cfg_queue_dtb_len_0_127_reg,
+			dpp_write,
+			dpp_read,
+	},
+	{
+			"info_queue_buf_space_left_0_127",
+			DTB4K_DTB_ENQ_INFO_QUEUE_BUF_SPACE_LEFT_0_127r,
+			DTB4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR + 0x000c,
+			(32 / 8),
+			0,
+			127 + 1,
+			0,
+			32,
+			1,
+			g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg,
+			dpp_write,
+			dpp_read,
+	},
+	{
+			"cfg_epid_v_func_num_0_127",
+			DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127r,
+			DTB4K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_ENQ_BASE_ADDR + 0x0010,
+			(32 / 8),
+			0,
+			127 + 1,
+			0,
+			32,
+			7,
+			g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg,
+			dpp_write,
+			dpp_read,
+	},
+	{
+			"cpu_trpg_ms_en",
+			TRPG_TRPG_RX_PORT_CPU_TRPG_MS_ENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0004,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpg_ms_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpg_port_en",
+			TRPG_TRPG_RX_PORT_CPU_TRPG_PORT_ENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0010,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpg_port_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpg_look_en",
+			TRPG_TRPG_RX_PORT_CPU_TRPG_LOOK_ENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0014,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpg_look_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_ram_almost_full",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_ALMOST_FULLr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0028,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_ram_almost_full_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_ram_test_en",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_TEST_ENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x002c,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_ram_test_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_inmod_pfc_rdy_en",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_INMOD_PFC_RDY_ENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0030,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_inmod_pfc_rdy_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_pkt_num_h",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_Hr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0034,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_pkt_num_l",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_NUM_Lr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0038,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_pkt_num_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_pkt_byte_num_h",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_Hr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x003c,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_pkt_byte_num_l",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_BYTE_NUM_Lr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0040,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_pkt_byte_num_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_pkt_cnt_clr",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_CNT_CLRr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0044,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_pkt_cnt_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_fc_clk_freq",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_CLK_FREQr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0048,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_fc_clk_freq_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_fc_en",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_ENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x004c,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_fc_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_fc_token_add_num",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_ADD_NUMr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0050,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_fc_token_add_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_fc_token_max_num",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_FC_TOKEN_MAX_NUMr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0054,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_fc_token_max_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_port_state_info",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_PORT_STATE_INFOr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0058,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_port_state_info_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_ram_past_max_dep",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEPr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x005c,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_ram_past_max_dep_clr",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_RAM_PAST_MAX_DEP_CLRr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0060,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_ram_past_max_dep_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_pkt_past_max_len",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0064,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_pkt_past_max_len_clr",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MAX_LEN_CLRr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0068,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_max_len_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_pkt_past_min_len",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x006c,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_pkt_past_min_len_clr",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_PKT_PAST_MIN_LEN_CLRr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0070,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_pkt_past_min_len_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trpg_rx_data_ram",
+			TRPG_TRPG_RX_RAM_TRPG_RX_DATA_RAMr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_RAM_BASE_ADDR + 0x0000,
+			(32 / 8),
+			DPP_TRPG_RAM_NUM,
+			2047 + 1,
+			DPP_TRPG_RAM_SPACE_SIZE,
+			4,
+			1,
+			g_trpg_trpg_rx_ram_trpg_rx_data_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trpg_rx_info_ram",
+			TRPG_TRPG_RX_RAM_TRPG_RX_INFO_RAMr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_RAM_BASE_ADDR + 0x2000,
+			(32 / 8),
+			DPP_TRPG_RAM_NUM,
+			255 + 1,
+			DPP_TRPG_RAM_SPACE_SIZE,
+			4,
+			1,
+			g_trpg_trpg_rx_ram_trpg_rx_info_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpg_ms_en",
+			TRPG_TRPG_TX_PORT_CPU_TRPG_MS_ENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0004,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpg_ms_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpg_port_en",
+			TRPG_TRPG_TX_PORT_CPU_TRPG_PORT_ENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0010,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpg_port_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpg_look_en",
+			TRPG_TRPG_TX_PORT_CPU_TRPG_LOOK_ENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0014,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpg_look_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_ram_almost_full",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_ALMOST_FULLr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0018,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_ram_almost_full_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_ram_test_en",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_TEST_ENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x001c,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_ram_test_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_pkt_num_h",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_Hr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0034,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_pkt_num_l",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_NUM_Lr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0038,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_pkt_num_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_pkt_byte_num_h",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_Hr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x003c,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_pkt_byte_num_l",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_BYTE_NUM_Lr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0040,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_pkt_byte_num_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_pkt_cnt_clr",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_CNT_CLRr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0044,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_pkt_cnt_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_fc_clk_freq",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_CLK_FREQr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0048,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_fc_clk_freq_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_fc_en",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_ENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x004c,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_fc_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_fc_token_add_num",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_ADD_NUMr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0050,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_fc_token_add_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_fc_token_max_num",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_FC_TOKEN_MAX_NUMr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0054,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_fc_token_max_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_port_state_info",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_PORT_STATE_INFOr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0058,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_port_state_info_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_ram_past_max_dep",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEPr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x005c,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_ram_past_max_dep_clr",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_RAM_PAST_MAX_DEP_CLRr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0060,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_ram_past_max_dep_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_pkt_past_max_len",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0064,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_pkt_past_max_len_clr",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MAX_LEN_CLRr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0068,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_max_len_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_pkt_past_min_len",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x006c,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_pkt_past_min_len_clr",
+			TRPG_TRPG_TX_PORT_CPU_TRPGTX_PKT_PAST_MIN_LEN_CLRr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0070,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpgtx_pkt_past_min_len_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_etm_ram_almost_full",
+			TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_ALMOST_FULLr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_ETM_PORT_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_almost_full_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgtx_etm_ram_test_en",
+			TRPG_TRPG_TX_ETM_PORT_CPU_TRPGTX_ETM_RAM_TEST_ENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_ETM_PORT_BASE_ADDR + 0x0010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_trpg_trpg_tx_etm_port_cpu_trpgtx_etm_ram_test_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_todtime_update_int_mask",
+			TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_MASKr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_trpg_trpg_tx_glb_cpu_todtime_update_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_todtime_update_int_clr",
+			TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_CLRr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x0010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_trpg_trpg_tx_glb_cpu_todtime_update_int_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_todtime_ram_test_en",
+			TRPG_TRPG_TX_GLB_CPU_TODTIME_RAM_TEST_ENr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_trpg_trpg_tx_glb_cpu_todtime_ram_test_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trpg_tx_data_ram",
+			TRPG_TRPG_TX_RAM_TRPG_TX_DATA_RAMr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_RAM_BASE_ADDR + 0x0000,
+			(32 / 8),
+			DPP_TRPG_RAM_NUM,
+			12031 + 1,
+			DPP_TRPG_RAM_SPACE_SIZE,
+			4,
+			1,
+			g_trpg_trpg_tx_ram_trpg_tx_data_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trpg_tx_info_ram",
+			TRPG_TRPG_TX_RAM_TRPG_TX_INFO_RAMr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_RAM_BASE_ADDR + 0xc000,
+			(32 / 8),
+			DPP_TRPG_RAM_NUM,
+			751 + 1,
+			DPP_TRPG_RAM_SPACE_SIZE,
+			4,
+			1,
+			g_trpg_trpg_tx_ram_trpg_tx_info_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trpg_tx_etm_data_ram",
+			TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_DATA_RAMr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_ETM_RAM_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			511 + 1,
+			0,
+			4,
+			1,
+			g_trpg_trpg_tx_etm_ram_trpg_tx_etm_data_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trpg_tx_etm_info_ram",
+			TRPG_TRPG_TX_ETM_RAM_TRPG_TX_ETM_INFO_RAMr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_ETM_RAM_BASE_ADDR + 0x800,
+			(32 / 8),
+			0,
+			31 + 1,
+			0,
+			4,
+			1,
+			g_trpg_trpg_tx_etm_ram_trpg_tx_etm_info_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"chip_version_reg",
+			ETM_CFGMT_CHIP_VERSION_REGr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x40,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_etm_cfgmt_chip_version_reg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"chip_date_reg",
+			ETM_CFGMT_CHIP_DATE_REGr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x50,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cfgmt_chip_date_reg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_crc_en",
+			ETM_CFGMT_CFGMT_CRC_ENr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x80,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cfgmt_cfgmt_crc_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_port_transfer_en",
+			ETM_CFGMT_CFG_PORT_TRANSFER_ENr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x130,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cfgmt_cfg_port_transfer_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_sa_work_mode",
+			ETM_CFGMT_TM_SA_WORK_MODEr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x180,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cfgmt_tm_sa_work_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"local_sa_id",
+			ETM_CFGMT_LOCAL_SA_IDr,
+			ETM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x190,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cfgmt_local_sa_id_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"olif_rdy",
+			ETM_OLIF_OLIF_RDYr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_etm_olif_olif_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"emem_prog_full",
+			ETM_OLIF_EMEM_PROG_FULLr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x3,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_olif_emem_prog_full_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port_order_fifo_full",
+			ETM_OLIF_PORT_ORDER_FIFO_FULLr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x5,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_olif_port_order_fifo_full_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"olif_release_last",
+			ETM_OLIF_OLIF_RELEASE_LASTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x6,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_olif_olif_release_last_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"olif_fifo_empty_state",
+			ETM_OLIF_OLIF_FIFO_EMPTY_STATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xa,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_etm_olif_olif_fifo_empty_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_olif_release_fc_cnt",
+			ETM_OLIF_QMU_OLIF_RELEASE_FC_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xb,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_qmu_olif_release_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"olif_qmu_link_fc_cnt",
+			ETM_OLIF_OLIF_QMU_LINK_FC_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_olif_qmu_link_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lif0_link_fc_cnt",
+			ETM_OLIF_LIF0_LINK_FC_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xd,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_lif0_link_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"olif_tmmu_fc_cnt",
+			ETM_OLIF_OLIF_TMMU_FC_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_olif_tmmu_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"olif_mmu_fc_cnt",
+			ETM_OLIF_OLIF_MMU_FC_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xf,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_olif_mmu_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"olif_qmu_port_rdy_h",
+			ETM_OLIF_OLIF_QMU_PORT_RDY_Hr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x10,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_olif_qmu_port_rdy_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"olif_qmu_port_rdy_l",
+			ETM_OLIF_OLIF_QMU_PORT_RDY_Lr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x11,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_olif_qmu_port_rdy_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lif0_port_rdy_h",
+			ETM_OLIF_LIF0_PORT_RDY_Hr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_lif0_port_rdy_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lif0_port_rdy_l",
+			ETM_OLIF_LIF0_PORT_RDY_Lr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x13,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_lif0_port_rdy_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_olif_rd_sop_cnt",
+			ETM_OLIF_QMU_OLIF_RD_SOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x14,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_qmu_olif_rd_sop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_olif_rd_eop_cnt",
+			ETM_OLIF_QMU_OLIF_RD_EOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x15,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_qmu_olif_rd_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_olif_rd_vld_cnt",
+			ETM_OLIF_QMU_OLIF_RD_VLD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x16,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_qmu_olif_rd_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_olif_rd_blk_cnt",
+			ETM_OLIF_QMU_OLIF_RD_BLK_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x17,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_qmu_olif_rd_blk_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mmu_tm_data_sop_cnt",
+			ETM_OLIF_MMU_TM_DATA_SOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x18,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_mmu_tm_data_sop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mmu_tm_data_eop_cnt",
+			ETM_OLIF_MMU_TM_DATA_EOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x19,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_mmu_tm_data_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mmu_tm_data_vld_cnt",
+			ETM_OLIF_MMU_TM_DATA_VLD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_mmu_tm_data_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_tm_data_sop_cnt",
+			ETM_OLIF_ODMA_TM_DATA_SOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_odma_tm_data_sop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_tm_data_eop_cnt",
+			ETM_OLIF_ODMA_TM_DATA_EOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_odma_tm_data_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_tm_deq_vld_cnt",
+			ETM_OLIF_ODMA_TM_DEQ_VLD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_odma_tm_deq_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"olif_qmu_release_vld_cnt",
+			ETM_OLIF_OLIF_QMU_RELEASE_VLD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_olif_qmu_release_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"emem_dat_vld_cnt",
+			ETM_OLIF_EMEM_DAT_VLD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_emem_dat_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"imem_dat_vld_cnt",
+			ETM_OLIF_IMEM_DAT_VLD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x21,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_imem_dat_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"emem_dat_rd_cnt",
+			ETM_OLIF_EMEM_DAT_RD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x22,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_emem_dat_rd_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"imem_dat_rd_cnt",
+			ETM_OLIF_IMEM_DAT_RD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x23,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_imem_dat_rd_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_olif_rd_sop_emem_cnt",
+			ETM_OLIF_QMU_OLIF_RD_SOP_EMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x24,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_qmu_olif_rd_sop_emem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_olif_rd_vld_emem_cnt",
+			ETM_OLIF_QMU_OLIF_RD_VLD_EMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x25,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_qmu_olif_rd_vld_emem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_last_wr_addr",
+			ETM_OLIF_CPU_LAST_WR_ADDRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x26,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_cpu_last_wr_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_last_wr_data",
+			ETM_OLIF_CPU_LAST_WR_DATAr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x27,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_cpu_last_wr_data_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_last_rd_addr",
+			ETM_OLIF_CPU_LAST_RD_ADDRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x28,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_cpu_last_rd_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_olif_last_port",
+			ETM_OLIF_QMU_OLIF_LAST_PORTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x35,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_qmu_olif_last_port_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_olif_last_addr",
+			ETM_OLIF_QMU_OLIF_LAST_ADDRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x36,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_qmu_olif_last_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_olif_last_bank",
+			ETM_OLIF_QMU_OLIF_LAST_BANKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x37,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_olif_qmu_olif_last_bank_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_lif_byte_stat",
+			ETM_OLIF_TM_LIF_BYTE_STATr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x70,
+			(32 / 8),
+			0,
+			0xf + 1,
+			0,
+			0x1,
+			1,
+			g_etm_olif_tm_lif_byte_stat_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_lif_err_stat",
+			ETM_OLIF_TM_LIF_ERR_STATr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x90,
+			(32 / 8),
+			0,
+			0xf + 1,
+			0,
+			0x1,
+			1,
+			g_etm_olif_tm_lif_err_stat_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port_share_cnt",
+			ETM_CGAVD_PORT_SHARE_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_port_share_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"total_imem_cnt",
+			ETM_CGAVD_TOTAL_IMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xa,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_total_imem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_q_len",
+			ETM_CGAVD_PP_Q_LENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0xa00,
+			(32 / 8),
+			0,
+			0x7f + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_pp_q_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sys_q_len",
+			ETM_CGAVD_SYS_Q_LENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1205,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_sys_q_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_cfg_error_warning",
+			ETM_CGAVD_CGAVD_CFG_ERROR_WARNINGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12de,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			12,
+			g_etm_cgavd_cgavd_cfg_error_warning_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mult_qlen_th_en",
+			ETM_CGAVD_MULT_QLEN_TH_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12df,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_mult_qlen_th_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mult_qlen_th",
+			ETM_CGAVD_MULT_QLEN_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_mult_qlen_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_cfg_move",
+			ETM_CGAVD_CGAVD_CFG_MOVEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12e1,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_etm_cgavd_cgavd_cfg_move_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_total_th",
+			ETM_CGAVD_CFGMT_TOTAL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12e2,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cfgmt_total_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_port_share_th",
+			ETM_CGAVD_CFGMT_PORT_SHARE_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x12e3,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cfgmt_port_share_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sa_unreach_state",
+			ETM_CGAVD_SA_UNREACH_STATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x1300,
+			(32 / 8),
+			0,
+			0x3 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_sa_unreach_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mv_port_th",
+			ETM_CGAVD_MV_PORT_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x2000,
+			(32 / 8),
+			0,
+			0x3f + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_mv_port_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mv_drop_sp_th",
+			ETM_CGAVD_MV_DROP_SP_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x3000,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_mv_drop_sp_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_state_warning",
+			ETM_CGAVD_CGAVD_STATE_WARNINGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x250006,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_etm_cgavd_cgavd_state_warning_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_cgavd_dma_fifo_cnt",
+			ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x250008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_cgavd_dma_fifo_cnt_max",
+			ETM_CGAVD_TMMU_CGAVD_DMA_FIFO_CNT_MAXr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x250009,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_tmmu_cgavd_dma_fifo_cnt_max_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"imem_total_cnt",
+			ETM_CGAVD_IMEM_TOTAL_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x25000a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_imem_total_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"imem_total_cnt_max",
+			ETM_CGAVD_IMEM_TOTAL_CNT_MAXr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x25000b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_imem_total_cnt_max_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow0_omem_cnt",
+			ETM_CGAVD_FLOW0_OMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow0_omem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow1_omem_cnt",
+			ETM_CGAVD_FLOW1_OMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260021,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow1_omem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow2_omem_cnt",
+			ETM_CGAVD_FLOW2_OMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260022,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow2_omem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow3_omem_cnt",
+			ETM_CGAVD_FLOW3_OMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260023,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow3_omem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flow4_omem_cnt",
+			ETM_CGAVD_FLOW4_OMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x260024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_flow4_omem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"appoint_flow_num_message_1",
+			ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x261000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_cgavd_appoint_flow_num_message_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"appoint_flow_num_message_2",
+			ETM_CGAVD_APPOINT_FLOW_NUM_MESSAGE_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x261001,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_cgavd_appoint_flow_num_message_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_cgavd_pkt_num_1",
+			ETM_CGAVD_ODMA_CGAVD_PKT_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_odma_cgavd_pkt_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_cgavd_byte_num_1",
+			ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262001,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_odma_cgavd_byte_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_enqueue_pkt_num_1",
+			ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262002,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_enqueue_pkt_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_dequeue_pkt_num_1",
+			ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262003,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_dequeue_pkt_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_pkt_imem_num_1",
+			ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_pkt_imem_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_pkt_omem_num_1",
+			ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262005,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_pkt_omem_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_byte_imem_num_1",
+			ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262006,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_byte_imem_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_byte_omem_num_1",
+			ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262007,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_byte_omem_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_pkt_drop_num_1",
+			ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_pkt_drop_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_byte_drop_num_1",
+			ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262009,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_byte_drop_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_forbid_drop_num_1",
+			ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_forbid_drop_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_flow_td_drop_num_1",
+			ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262011,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_flow_td_drop_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_flow_wred_drop_num_1",
+			ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262012,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_flow_wred_drop_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_flow_wred_dp_drop_num_1",
+			ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x262100,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_pp_td_num_1",
+			ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262200,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_pp_td_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_pp_wred_drop_num_1",
+			ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262201,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_pp_wred_drop_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_pp_wred_dp_drop_num_1",
+			ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x262300,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_sys_td_drop_num_1",
+			ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262400,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_sys_td_drop_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_sys_gred_drop_num_1",
+			ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262401,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_sys_gred_drop_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_sys_gred_dp_drop_num1",
+			ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x262500,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_sa_drop_num_1",
+			ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262600,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_sa_drop_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_move_drop_num_1",
+			ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262601,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_move_drop_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_tm_mult_drop_num_1",
+			ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262602,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_tm_mult_drop_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_tm_error_drop_num_1",
+			ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x262603,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_tm_error_drop_num_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_cgavd_pkt_num_2",
+			ETM_CGAVD_ODMA_CGAVD_PKT_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_odma_cgavd_pkt_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_cgavd_byte_num_2",
+			ETM_CGAVD_ODMA_CGAVD_BYTE_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263001,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_odma_cgavd_byte_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_enqueue_pkt_num_2",
+			ETM_CGAVD_CGAVD_ENQUEUE_PKT_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263002,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_enqueue_pkt_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_dequeue_pkt_num_2",
+			ETM_CGAVD_CGAVD_DEQUEUE_PKT_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263003,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_dequeue_pkt_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_pkt_imem_num_2",
+			ETM_CGAVD_CGAVD_QMU_PKT_IMEM_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_pkt_imem_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_pkt_omem_num_2",
+			ETM_CGAVD_CGAVD_QMU_PKT_OMEM_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263005,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_pkt_omem_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_byte_imem_num_2",
+			ETM_CGAVD_CGAVD_QMU_BYTE_IMEM_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263006,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_byte_imem_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_byte_omem_num_2",
+			ETM_CGAVD_CGAVD_QMU_BYTE_OMEM_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263007,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_byte_omem_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_pkt_drop_num_2",
+			ETM_CGAVD_CGAVD_QMU_PKT_DROP_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_pkt_drop_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_byte_drop_num_2",
+			ETM_CGAVD_CGAVD_QMU_BYTE_DROP_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263009,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_byte_drop_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_forbid_drop_num_2",
+			ETM_CGAVD_CGAVD_QMU_FORBID_DROP_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_forbid_drop_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_flow_td_drop_num_2",
+			ETM_CGAVD_CGAVD_QMU_FLOW_TD_DROP_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263011,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_flow_td_drop_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_flow_wred_drop_num_2",
+			ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DROP_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263012,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_flow_wred_drop_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_flow_wred_dp_drop_num_2",
+			ETM_CGAVD_CGAVD_QMU_FLOW_WRED_DP_DROP_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x263100,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_cgavd_qmu_flow_wred_dp_drop_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_pp_td_num_2",
+			ETM_CGAVD_CGAVD_QMU_PP_TD_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263200,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_pp_td_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_pp_wred_drop_num_2",
+			ETM_CGAVD_CGAVD_QMU_PP_WRED_DROP_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263201,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_pp_wred_drop_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_pp_wred_dp_drop_num_2",
+			ETM_CGAVD_CGAVD_QMU_PP_WRED_DP_DROP_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x263300,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_cgavd_qmu_pp_wred_dp_drop_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_sys_td_drop_num_2",
+			ETM_CGAVD_CGAVD_QMU_SYS_TD_DROP_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263400,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_sys_td_drop_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_sys_gred_drop_num_2",
+			ETM_CGAVD_CGAVD_QMU_SYS_GRED_DROP_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263401,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_sys_gred_drop_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_sys_gred_dp_drop_num_2",
+			ETM_CGAVD_CGAVD_QMU_SYS_GRED_DP_DROP_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x263500,
+			(32 / 8),
+			0,
+			0x7 + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_cgavd_qmu_sys_gred_dp_drop_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_sa_drop_num_2",
+			ETM_CGAVD_CGAVD_QMU_SA_DROP_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263600,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_sa_drop_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_move_drop_num_2",
+			ETM_CGAVD_CGAVD_QMU_MOVE_DROP_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263601,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_move_drop_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_tm_mult_drop_num_2",
+			ETM_CGAVD_CGAVD_QMU_TM_MULT_DROP_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263602,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_tm_mult_drop_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cgavd_qmu_tm_error_drop_num_2",
+			ETM_CGAVD_CGAVD_QMU_TM_ERROR_DROP_NUM_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x263603,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_cgavd_cgavd_qmu_tm_error_drop_num_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"move_flow_th_profile",
+			ETM_CGAVD_MOVE_FLOW_TH_PROFILEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x270000,
+			(32 / 8),
+			0,
+			0x23FF + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_move_flow_th_profile_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"move_flow_th",
+			ETM_CGAVD_MOVE_FLOW_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x280000,
+			(32 / 8),
+			0,
+			0xF + 1,
+			0,
+			0x1,
+			1,
+			g_etm_cgavd_move_flow_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"emem_pd_fifo_aful_th",
+			ETM_TMMU_EMEM_PD_FIFO_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0009,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_emem_pd_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_data_fifo_aful_th",
+			ETM_TMMU_DMA_DATA_FIFO_AFUL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_dma_data_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_states_0",
+			ETM_TMMU_TMMU_STATES_0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			31,
+			g_etm_tmmu_tmmu_states_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_tmmu_wr_sop_cnt",
+			ETM_TMMU_QMU_TMMU_WR_SOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0013,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_qmu_tmmu_wr_sop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_tmmu_wr_eop_cnt",
+			ETM_TMMU_QMU_TMMU_WR_EOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_qmu_tmmu_wr_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_tmmu_wr_drop_cnt",
+			ETM_TMMU_QMU_TMMU_WR_DROP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0015,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_qmu_tmmu_wr_drop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_tmmu_wr_emem_cnt",
+			ETM_TMMU_QMU_TMMU_WR_EMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0016,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_qmu_tmmu_wr_emem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_tmmu_wr_imem_cnt",
+			ETM_TMMU_QMU_TMMU_WR_IMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0017,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_qmu_tmmu_wr_imem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_mmu_wr_sop_cnt",
+			ETM_TMMU_TMMU_MMU_WR_SOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_mmu_wr_sop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_mmu_wr_eop_cnt",
+			ETM_TMMU_TMMU_MMU_WR_EOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0019,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_mmu_wr_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_tmmu_rd_sop_cnt",
+			ETM_TMMU_QMU_TMMU_RD_SOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x001a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_qmu_tmmu_rd_sop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_tmmu_rd_eop_cnt",
+			ETM_TMMU_QMU_TMMU_RD_EOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x001b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_qmu_tmmu_rd_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_tmmu_rd_drop_cnt",
+			ETM_TMMU_QMU_TMMU_RD_DROP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_qmu_tmmu_rd_drop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_tmmu_rd_emem_cnt",
+			ETM_TMMU_QMU_TMMU_RD_EMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x001d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_qmu_tmmu_rd_emem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_tmmu_rd_imem_cnt",
+			ETM_TMMU_QMU_TMMU_RD_IMEM_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x001e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_qmu_tmmu_rd_imem_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_mmu_rd_sop_cnt",
+			ETM_TMMU_TMMU_MMU_RD_SOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x001f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_mmu_rd_sop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_mmu_rd_eop_cnt",
+			ETM_TMMU_TMMU_MMU_RD_EOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_mmu_rd_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_odma_in_sop_cnt",
+			ETM_TMMU_TMMU_ODMA_IN_SOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0021,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_odma_in_sop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_odma_in_eop_cnt",
+			ETM_TMMU_TMMU_ODMA_IN_EOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0022,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_odma_in_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_odma_vld_cnt",
+			ETM_TMMU_TMMU_ODMA_VLD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0023,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_odma_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_pd_in_cnt",
+			ETM_TMMU_QMU_PD_IN_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_qmu_pd_in_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_pd_hit_cnt",
+			ETM_TMMU_TMMU_PD_HIT_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0025,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_pd_hit_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_pd_out_cnt",
+			ETM_TMMU_TMMU_PD_OUT_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0026,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_pd_out_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_wr_cmd_fifo_wr_cnt",
+			ETM_TMMU_TMMU_WR_CMD_FIFO_WR_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0027,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_wr_cmd_fifo_wr_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_imem_age_cnt",
+			ETM_TMMU_TMMU_IMEM_AGE_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_imem_age_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_cmdsch_rd_cnt",
+			ETM_TMMU_TMMU_CMDSCH_RD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0029,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_cmdsch_rd_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_cmdsch_drop_cnt",
+			ETM_TMMU_TMMU_CMDSCH_DROP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x002a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_cmdsch_drop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_cmdsw_drop_cnt",
+			ETM_TMMU_TMMU_CMDSW_DROP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x002b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_cmdsw_drop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_odma_enq_rd_cnt",
+			ETM_TMMU_TMMU_ODMA_ENQ_RD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x002c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_odma_enq_rd_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_odma_enq_drop_cnt",
+			ETM_TMMU_TMMU_ODMA_ENQ_DROP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x002d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_odma_enq_drop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_odma_imem_age_cnt",
+			ETM_TMMU_TMMU_ODMA_IMEM_AGE_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x002e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_odma_imem_age_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_odma_deq_rd_cnt",
+			ETM_TMMU_TMMU_ODMA_DEQ_RD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x002f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_odma_deq_rd_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tmmu_odma_deq_drop_cnt",
+			ETM_TMMU_TMMU_ODMA_DEQ_DROP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tmmu_odma_deq_drop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"olif_tmmu_xoff_cnt",
+			ETM_TMMU_OLIF_TMMU_XOFF_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0031,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_olif_tmmu_xoff_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_tm_data_xoff_cnt",
+			ETM_TMMU_ODMA_TM_DATA_XOFF_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0032,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_odma_tm_data_xoff_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_odma_pkt_xoff_cnt",
+			ETM_TMMU_TM_ODMA_PKT_XOFF_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0033,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_tm_odma_pkt_xoff_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_state_3",
+			ETM_TMMU_TM_STATE_3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_tmmu_tm_state_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_pd_cache_cmd",
+			ETM_TMMU_CFGMT_PD_CACHE_CMDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_pd_cache_cmd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_pd_cache_rd_done",
+			ETM_TMMU_CFGMT_PD_CACHE_RD_DONEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0051,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_pd_cache_rd_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_pd_cache_rd_data_0",
+			ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0052,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_pd_cache_rd_data_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_pd_cache_rd_data_1",
+			ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0053,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_pd_cache_rd_data_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_pd_cache_rd_data_2",
+			ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_pd_cache_rd_data_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_pd_cache_rd_data_3",
+			ETM_TMMU_CFGMT_PD_CACHE_RD_DATA_3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0055,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_pd_cache_rd_data_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_tmmu_to_odma_para",
+			ETM_TMMU_CFGMT_TMMU_TO_ODMA_PARAr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0056,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_tmmu_to_odma_para_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_dma_data_fifo_cnt",
+			ETM_TMMU_CFGMT_DMA_DATA_FIFO_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0057,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_dma_data_fifo_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_tag_bit0_offset",
+			ETM_TMMU_CFGMT_CACHE_TAG_BIT0_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_tag_bit0_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_tag_bit1_offset",
+			ETM_TMMU_CFGMT_CACHE_TAG_BIT1_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0061,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_tag_bit1_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_tag_bit2_offset",
+			ETM_TMMU_CFGMT_CACHE_TAG_BIT2_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0062,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_tag_bit2_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_tag_bit3_offset",
+			ETM_TMMU_CFGMT_CACHE_TAG_BIT3_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0063,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_tag_bit3_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_tag_bit4_offset",
+			ETM_TMMU_CFGMT_CACHE_TAG_BIT4_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_tag_bit4_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_tag_bit5_offset",
+			ETM_TMMU_CFGMT_CACHE_TAG_BIT5_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0065,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_tag_bit5_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_index_bit0_offset",
+			ETM_TMMU_CFGMT_CACHE_INDEX_BIT0_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0066,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_index_bit0_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_index_bit1_offset",
+			ETM_TMMU_CFGMT_CACHE_INDEX_BIT1_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0067,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_index_bit1_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_index_bit2_offset",
+			ETM_TMMU_CFGMT_CACHE_INDEX_BIT2_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_index_bit2_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_index_bit3_offset",
+			ETM_TMMU_CFGMT_CACHE_INDEX_BIT3_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0069,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_index_bit3_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_index_bit4_offset",
+			ETM_TMMU_CFGMT_CACHE_INDEX_BIT4_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x006a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_index_bit4_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_index_bit5_offset",
+			ETM_TMMU_CFGMT_CACHE_INDEX_BIT5_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x006b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_index_bit5_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_index_bit6_offset",
+			ETM_TMMU_CFGMT_CACHE_INDEX_BIT6_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x006c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_index_bit6_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_index_bit7_offset",
+			ETM_TMMU_CFGMT_CACHE_INDEX_BIT7_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x006d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_index_bit7_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_index_bit8_offset",
+			ETM_TMMU_CFGMT_CACHE_INDEX_BIT8_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x006e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_index_bit8_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_index_bit9_offset",
+			ETM_TMMU_CFGMT_CACHE_INDEX_BIT9_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x006f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_index_bit9_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_index_bit10_offset",
+			ETM_TMMU_CFGMT_CACHE_INDEX_BIT10_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0070,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_index_bit10_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_index_bit11_offset",
+			ETM_TMMU_CFGMT_CACHE_INDEX_BIT11_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0071,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_index_bit11_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_cache_index_bit12_offset",
+			ETM_TMMU_CFGMT_CACHE_INDEX_BIT12_OFFSETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0072,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_tmmu_cfgmt_cache_index_bit12_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"bktfull_fifo_full_flagregister",
+			ETM_SHAP_BKTFULL_FIFO_FULL_FLAGREGISTERr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x26,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_bktfull_fifo_full_flagregister_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fifo_full_regregister",
+			ETM_SHAP_FIFO_FULL_REGREGISTERr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x29,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_fifo_full_regregister_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fifo_empty_regregister",
+			ETM_SHAP_FIFO_EMPTY_REGREGISTERr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_fifo_empty_regregister_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fifo_almost_full_regregister",
+			ETM_SHAP_FIFO_ALMOST_FULL_REGREGISTERr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_fifo_almost_full_regregister_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fifo_almost_empty_regregister",
+			ETM_SHAP_FIFO_ALMOST_EMPTY_REGREGISTERr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x32,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_shap_fifo_almost_empty_regregister_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"credit_space_select",
+			ETM_CRDT_CREDIT_SPACE_SELECTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x000e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_credit_space_select_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_space_max",
+			ETM_CRDT_STAT_SPACE_MAXr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x30,
+			(32 / 8),
+			0,
+			0x0f + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_stat_space_max_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_space_min",
+			ETM_CRDT_STAT_SPACE_MINr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x40,
+			(32 / 8),
+			0,
+			0x0f + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_stat_space_min_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_space_credit",
+			ETM_CRDT_STAT_SPACE_CREDITr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x50,
+			(32 / 8),
+			0,
+			0x0f + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_stat_space_credit_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_que_step8_credit",
+			ETM_CRDT_STAT_QUE_STEP8_CREDITr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x60,
+			(32 / 8),
+			0,
+			0x07 + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_stat_que_step8_credit_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"special_que",
+			ETM_CRDT_SPECIAL_QUEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x68,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_special_que_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"special_que_credit",
+			ETM_CRDT_SPECIAL_QUE_CREDITr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x69,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_special_que_credit_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lif_congest_credit_cnt",
+			ETM_CRDT_LIF_CONGEST_CREDIT_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x70,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_lif_congest_credit_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lif_port_congest_credit_cnt",
+			ETM_CRDT_LIF_PORT_CONGEST_CREDIT_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x71,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_lif_port_congest_credit_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_congest_credit_cnt",
+			ETM_CRDT_CRDT_CONGEST_CREDIT_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x72,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crdt_congest_credit_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_port_congest_credit_cnt",
+			ETM_CRDT_CRDT_PORT_CONGEST_CREDIT_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x73,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crdt_port_congest_credit_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"congest_port_id",
+			ETM_CRDT_CONGEST_PORT_IDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x74,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_congest_port_id_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dev_link_control",
+			ETM_CRDT_DEV_LINK_CONTROLr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x75,
+			(32 / 8),
+			0,
+			0x1 + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_dev_link_control_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_sa_port_rdy",
+			ETM_CRDT_CRDT_SA_PORT_RDYr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x77,
+			(32 / 8),
+			0,
+			0x1 + 1,
+			0,
+			1,
+			1,
+			g_etm_crdt_crdt_sa_port_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_congest_mode_select",
+			ETM_CRDT_CRDT_CONGEST_MODE_SELECTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x81,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crdt_congest_mode_select_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fifo_out_all_crs_normal_cnt",
+			ETM_CRDT_FIFO_OUT_ALL_CRS_NORMAL_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x82,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_fifo_out_all_crs_normal_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fifo_out_all_crs_off_cnt",
+			ETM_CRDT_FIFO_OUT_ALL_CRS_OFF_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x83,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_fifo_out_all_crs_off_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fifo_out_que_crs_normal_cnt",
+			ETM_CRDT_FIFO_OUT_QUE_CRS_NORMAL_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x84,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_fifo_out_que_crs_normal_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fifo_out_que_crs_off_cnt",
+			ETM_CRDT_FIFO_OUT_QUE_CRS_OFF_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x85,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_fifo_out_que_crs_off_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mode_add_60g",
+			ETM_CRDT_MODE_ADD_60Gr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x9a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_mode_add_60g_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_token_add",
+			ETM_CRDT_PP_TOKEN_ADDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x9b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_pp_token_add_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_cir_token_total_dist_cnt",
+			ETM_CRDT_PP_CIR_TOKEN_TOTAL_DIST_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x9c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_pp_cir_token_total_dist_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_cir_token_total_dec_cnt",
+			ETM_CRDT_PP_CIR_TOKEN_TOTAL_DEC_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x9d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_pp_cir_token_total_dec_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dev_credit_cnt",
+			ETM_CRDT_DEV_CREDIT_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xb0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_dev_credit_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"no_credit_cnt1",
+			ETM_CRDT_NO_CREDIT_CNT1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xb7,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_no_credit_cnt1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"no_credit_cnt2",
+			ETM_CRDT_NO_CREDIT_CNT2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xb8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_no_credit_cnt2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"asm_interval_0_cfg",
+			ETM_CRDT_ASM_INTERVAL_0_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xc7,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_asm_interval_0_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"asm_interval_1_cfg",
+			ETM_CRDT_ASM_INTERVAL_1_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xc8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_asm_interval_1_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"asm_interval_2_cfg",
+			ETM_CRDT_ASM_INTERVAL_2_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xc9,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_asm_interval_2_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"asm_interval_3_cfg",
+			ETM_CRDT_ASM_INTERVAL_3_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xca,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_asm_interval_3_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"asm_interval_4_cfg",
+			ETM_CRDT_ASM_INTERVAL_4_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xcb,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_asm_interval_4_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"asm_interval_5cfg",
+			ETM_CRDT_ASM_INTERVAL_5CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xcc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_asm_interval_5cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"asm_interval_6_cfg",
+			ETM_CRDT_ASM_INTERVAL_6_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xcd,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_asm_interval_6_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"asm_interval_7_cfg",
+			ETM_CRDT_ASM_INTERVAL_7_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xce,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_asm_interval_7_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_total_congest_mode_cfg",
+			ETM_CRDT_CRDT_TOTAL_CONGEST_MODE_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xcf,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crdt_total_congest_mode_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rci_fifo_ini_deep_cfg",
+			ETM_CRDT_RCI_FIFO_INI_DEEP_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xd0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_rci_fifo_ini_deep_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_ecc",
+			ETM_CRDT_CRDT_ECCr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x121,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_etm_crdt_crdt_ecc_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ucn_asm_rdy_shield_en",
+			ETM_CRDT_UCN_ASM_RDY_SHIELD_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x013a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_crdt_ucn_asm_rdy_shield_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ucn_asm_rdy",
+			ETM_CRDT_UCN_ASM_RDYr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x013b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_crdt_ucn_asm_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rci_grade",
+			ETM_CRDT_RCI_GRADEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x013c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_rci_grade_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_rci_value_r",
+			ETM_CRDT_CRDT_RCI_VALUE_Rr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x013d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crdt_rci_value_r_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_interval_now",
+			ETM_CRDT_CRDT_INTERVAL_NOWr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x013e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crdt_interval_now_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crs_sheild_flow_id_cfg",
+			ETM_CRDT_CRS_SHEILD_FLOW_ID_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0140,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crs_sheild_flow_id_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crs_sheild_en_cfg",
+			ETM_CRDT_CRS_SHEILD_EN_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0141,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crs_sheild_en_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crs_sheild_value_cfg",
+			ETM_CRDT_CRS_SHEILD_VALUE_CFGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x0142,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_crs_sheild_value_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_token_calc_ctrl",
+			ETM_CRDT_TEST_TOKEN_CALC_CTRLr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x14c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_crdt_test_token_calc_ctrl_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_token_sample_cycle_num",
+			ETM_CRDT_TEST_TOKEN_SAMPLE_CYCLE_NUMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x14d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_crdt_test_token_sample_cycle_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"q_state_0_7",
+			ETM_CRDT_Q_STATE_0_7r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x14e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			8,
+			g_etm_crdt_q_state_0_7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"q_state_8_15",
+			ETM_CRDT_Q_STATE_8_15r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x14f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			8,
+			g_etm_crdt_q_state_8_15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csw_csch_rd_cmd_cnt",
+			ETM_QMU_CSW_CSCH_RD_CMD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x14,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csw_csch_rd_cmd_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csw_csch_rd_sop_cnt",
+			ETM_QMU_CSW_CSCH_RD_SOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x15,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csw_csch_rd_sop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csw_csch_rd_eop_cnt",
+			ETM_QMU_CSW_CSCH_RD_EOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x16,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csw_csch_rd_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csw_csch_rd_drop_cnt",
+			ETM_QMU_CSW_CSCH_RD_DROP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x17,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csw_csch_rd_drop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csch_mmu_rd_cmd_cnt",
+			ETM_QMU_CSCH_MMU_RD_CMD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x18,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csch_mmu_rd_cmd_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csch_mmu_rd_sop_cnt",
+			ETM_QMU_CSCH_MMU_RD_SOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x19,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csch_mmu_rd_sop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csch_mmu_rd_eop_cnt",
+			ETM_QMU_CSCH_MMU_RD_EOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csch_mmu_rd_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csch_mmu_rd_drop_cnt",
+			ETM_QMU_CSCH_MMU_RD_DROP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csch_mmu_rd_drop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qsch_crs_filter",
+			ETM_QMU_QCFG_QSCH_CRS_FILTERr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qcfg_qsch_crs_filter_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qsch_crs_force_en",
+			ETM_QMU_QCFG_QSCH_CRS_FORCE_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qcfg_qsch_crs_force_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qsch_crs_force_qnum",
+			ETM_QMU_QCFG_QSCH_CRS_FORCE_QNUMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qcfg_qsch_crs_force_qnum_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qsch_crs_force_crs",
+			ETM_QMU_QCFG_QSCH_CRS_FORCE_CRSr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x1f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qcfg_qsch_crs_force_crs_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_oshp_sgmii_shap_mode",
+			ETM_QMU_CFGMT_OSHP_SGMII_SHAP_MODEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_oshp_sgmii_shap_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_sashap_en",
+			ETM_QMU_CFGMT_QMU_SASHAP_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x21,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_qmu_sashap_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_sashap_token_max",
+			ETM_QMU_CFGMT_SASHAP_TOKEN_MAXr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x39,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_sashap_token_max_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_sashap_token_min",
+			ETM_QMU_CFGMT_SASHAP_TOKEN_MINr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x3a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfgmt_sashap_token_min_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_q3lbaddrate",
+			ETM_QMU_CFG_QSCH_Q3LBADDRATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x3f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_q3lbaddrate_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_q012lbaddrate",
+			ETM_QMU_CFG_QSCH_Q012LBADDRATEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x40,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_q012lbaddrate_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_q3creditlbmaxcnt",
+			ETM_QMU_CFG_QSCH_Q3CREDITLBMAXCNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x41,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_q3creditlbmaxcnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_q012creditlbmaxcnt",
+			ETM_QMU_CFG_QSCH_Q012CREDITLBMAXCNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x42,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_q012creditlbmaxcnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mul_token_gen_num",
+			ETM_QMU_CFG_QSCH_MUL_TOKEN_GEN_NUMr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x43,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mul_token_gen_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_q3_credit_lb_control_en",
+			ETM_QMU_CFG_QSCH_Q3_CREDIT_LB_CONTROL_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x44,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_q3_credit_lb_control_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_q012_credit_lb_control_en",
+			ETM_QMU_CFG_QSCH_Q012_CREDIT_LB_CONTROL_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x45,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_q012_credit_lb_control_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_sp_dwrr_en",
+			ETM_QMU_CFG_QSCH_SP_DWRR_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x46,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_sp_dwrr_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_q01_attach_en",
+			ETM_QMU_CFG_QSCH_Q01_ATTACH_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x47,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_q01_attach_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_w0",
+			ETM_QMU_CFG_QSCH_W0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x48,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_w0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_w1",
+			ETM_QMU_CFG_QSCH_W1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x49,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_w1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_w2",
+			ETM_QMU_CFG_QSCH_W2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x4a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_w2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_lkybktmaxcnt1",
+			ETM_QMU_CFG_QSCH_LKYBKTMAXCNT1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x4b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_lkybktmaxcnt1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_lkybktmaxcnt2",
+			ETM_QMU_CFG_QSCH_LKYBKTMAXCNT2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x4c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_lkybktmaxcnt2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_lkybktdcrrate1",
+			ETM_QMU_CFG_QSCH_LKYBKTDCRRATE1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x4d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_lkybktdcrrate1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_lkybktdcrrate2",
+			ETM_QMU_CFG_QSCH_LKYBKTDCRRATE2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x4e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_lkybktdcrrate2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_lkybktdcrrate3",
+			ETM_QMU_CFG_QSCH_LKYBKTDCRRATE3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x4f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_lkybktdcrrate3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_lkybktmaxcnt3",
+			ETM_QMU_CFG_QSCH_LKYBKTMAXCNT3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x50,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_lkybktmaxcnt3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_qmu_mul_auto_sa_version",
+			ETM_QMU_CFG_QSCH_QMU_MUL_AUTO_SA_VERSIONr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x55,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_qmu_mul_auto_sa_version_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_sa_credit_value_0",
+			ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x56,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_sa_credit_value_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_sa_credit_value_1",
+			ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x57,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_sa_credit_value_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_sa_credit_value_2",
+			ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x58,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_sa_credit_value_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_sa_credit_value_3",
+			ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x59,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_sa_credit_value_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_sa_credit_value_4",
+			ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_4r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x5a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_sa_credit_value_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_sa_credit_value_5",
+			ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_5r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x5b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_sa_credit_value_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_sa_credit_value_6",
+			ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_6r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x5c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_sa_credit_value_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_sa_credit_value_7",
+			ETM_QMU_CFG_QSCH_SA_CREDIT_VALUE_7r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x5d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_sa_credit_value_7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_remote_credit_fifo_almost_full_th",
+			ETM_QMU_CFG_QSCH_REMOTE_CREDIT_FIFO_ALMOST_FULL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x76,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_remote_credit_fifo_almost_full_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_auto_credit_fifo_almost_full_th",
+			ETM_QMU_CFG_QSCH_AUTO_CREDIT_FIFO_ALMOST_FULL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x77,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_auto_credit_fifo_almost_full_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_q3_credit_fifo_almost_full_th",
+			ETM_QMU_CFG_QSCH_Q3_CREDIT_FIFO_ALMOST_FULL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x78,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_q3_credit_fifo_almost_full_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_q012_credit_fifo_almost_full_th",
+			ETM_QMU_CFG_QSCH_Q012_CREDIT_FIFO_ALMOST_FULL_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x79,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_q012_credit_fifo_almost_full_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mul_fc_res_en",
+			ETM_QMU_CFG_QSCH_MUL_FC_RES_ENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x7a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mul_fc_res_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_mul_ovf_udf_flg_query",
+			ETM_QMU_CFGMT_MUL_OVF_UDF_FLG_QUERYr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x7d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			19,
+			g_etm_qmu_cfgmt_mul_ovf_udf_flg_query_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_mul_cng_flg_query",
+			ETM_QMU_CFGMT_MUL_CNG_FLG_QUERYr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x7e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_etm_qmu_cfgmt_mul_cng_flg_query_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qsch_cfg_lkybktval1",
+			ETM_QMU_QSCH_CFG_LKYBKTVAL1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x7f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qsch_cfg_lkybktval1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qsch_cfg_lkybktval2",
+			ETM_QMU_QSCH_CFG_LKYBKTVAL2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x80,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qsch_cfg_lkybktval2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qsch_cfg_lkybktval3",
+			ETM_QMU_QSCH_CFG_LKYBKTVAL3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x81,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qsch_cfg_lkybktval3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qsch_cfg_q3lbval",
+			ETM_QMU_QSCH_CFG_Q3LBVALr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x82,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qsch_cfg_q3lbval_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qsch_cfg_q012lbval",
+			ETM_QMU_QSCH_CFG_Q012LBVALr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x83,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qsch_cfg_q012lbval_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qlist_cfgmt_ram_ecc_err2",
+			ETM_QMU_QLIST_CFGMT_RAM_ECC_ERR2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			16,
+			g_etm_qmu_qlist_cfgmt_ram_ecc_err2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csch_aged_cmd_cnt",
+			ETM_QMU_CSCH_AGED_CMD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2838,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csch_aged_cmd_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csch_qcfg_csch_congest_cnt",
+			ETM_QMU_CSCH_QCFG_CSCH_CONGEST_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2839,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csch_qcfg_csch_congest_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csch_qcfg_qlist_csch_sop_cnt",
+			ETM_QMU_CSCH_QCFG_QLIST_CSCH_SOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x283a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csch_qcfg_qlist_csch_sop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csch_qcfg_qlist_csch_eop_cnt",
+			ETM_QMU_CSCH_QCFG_QLIST_CSCH_EOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x283b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csch_qcfg_qlist_csch_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csch_qcfg_csch_csw_sop_cnt",
+			ETM_QMU_CSCH_QCFG_CSCH_CSW_SOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x283c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csch_qcfg_csch_csw_sop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csch_qcfg_csch_csw_eop_cnt",
+			ETM_QMU_CSCH_QCFG_CSCH_CSW_EOP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x283d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csch_qcfg_csch_csw_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csch_qcfg_qlist_csch_drop_cnt",
+			ETM_QMU_CSCH_QCFG_QLIST_CSCH_DROP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x283e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csch_qcfg_qlist_csch_drop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csch_qcfg_csch_csw_drop_cnt",
+			ETM_QMU_CSCH_QCFG_CSCH_CSW_DROP_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x283f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csch_qcfg_csch_csw_drop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csw_mmu_sop_cmd_cnt",
+			ETM_QMU_CSW_MMU_SOP_CMD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2840,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csw_mmu_sop_cmd_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mmu_csw_sop_data_cnt",
+			ETM_QMU_MMU_CSW_SOP_DATA_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2841,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_mmu_csw_sop_data_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csw_qsch_feedb_cnt",
+			ETM_QMU_CSW_QSCH_FEEDB_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2842,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_csw_qsch_feedb_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_crdt_port_fc_cnt",
+			ETM_QMU_QMU_CRDT_PORT_FC_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2843,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_crdt_port_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"csch_r_block_cnt",
+			ETM_QMU_CSCH_R_BLOCK_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x3400,
+			(32 / 8),
+			0,
+			0x1ff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_csch_r_block_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_qds_head_rd",
+			ETM_QMU_QCFG_QLIST_QDS_HEAD_RDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x10000,
+			(32 / 8),
+			0,
+			0x23ff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_qds_head_rd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_qds_tail_rd",
+			ETM_QMU_QCFG_QLIST_QDS_TAIL_RDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x20000,
+			(32 / 8),
+			0,
+			0x23ff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_qds_tail_rd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_ept_rd",
+			ETM_QMU_QCFG_QLIST_EPT_RDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x30000,
+			(32 / 8),
+			0,
+			0x23ff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_ept_rd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_age_flag_rd",
+			ETM_QMU_QCFG_QLIST_AGE_FLAG_RDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x38000,
+			(32 / 8),
+			0,
+			0x23ff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_age_flag_rd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_cti_rd",
+			ETM_QMU_QCFG_QLIST_CTI_RDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x40000,
+			(32 / 8),
+			0,
+			0x23ff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_cti_rd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_cto_rd",
+			ETM_QMU_QCFG_QLIST_CTO_RDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x50000,
+			(32 / 8),
+			0,
+			0x23ff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_cto_rd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_chk_rd",
+			ETM_QMU_QCFG_QLIST_CHK_RDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x100000,
+			(32 / 8),
+			0,
+			0x7fff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_chk_rd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_nod_rd",
+			ETM_QMU_QCFG_QLIST_NOD_RDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x140000,
+			(32 / 8),
+			0,
+			0x7fff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_nod_rd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_qlist_biu_rd",
+			ETM_QMU_QCFG_QLIST_BIU_RDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x180000,
+			(32 / 8),
+			0,
+			0x7fff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_qlist_biu_rd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qsch_r_wlist_flag",
+			ETM_QMU_QSCH_R_WLIST_FLAGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x90000,
+			(32 / 8),
+			0,
+			0x23ff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qsch_r_wlist_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qcfg_crs_flg_rd",
+			ETM_QMU_QCFG_CRS_FLG_RDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0xd0000,
+			(32 / 8),
+			0,
+			0x23ff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_qcfg_crs_flg_rd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_imem_age_qds",
+			ETM_QMU_CFGMT_QMU_IMEM_AGE_QDSr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe0d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_qmu_cfgmt_qmu_imem_age_qds_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_imem_age_qlen",
+			ETM_QMU_CFGMT_QMU_IMEM_AGE_QLENr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0xe0e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_qmu_cfgmt_qmu_imem_age_qlen_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_imem_pd_ram_low",
+			ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_LOWr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x1c0000,
+			(32 / 8),
+			0,
+			0x3fff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_cfgmt_qmu_imem_pd_ram_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_imem_pd_ram_high",
+			ETM_QMU_CFGMT_QMU_IMEM_PD_RAM_HIGHr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x1c4000,
+			(32 / 8),
+			0,
+			0x3fff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_cfgmt_qmu_imem_pd_ram_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_imem_up_ptr",
+			ETM_QMU_CFGMT_QMU_IMEM_UP_PTRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x200000,
+			(32 / 8),
+			0,
+			0x3fff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_cfgmt_qmu_imem_up_ptr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_imem_down_ptr",
+			ETM_QMU_CFGMT_QMU_IMEM_DOWN_PTRr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x240000,
+			(32 / 8),
+			0,
+			0x3fff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_cfgmt_qmu_imem_down_ptr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfgmt_qmu_imem_age_flag",
+			ETM_QMU_CFGMT_QMU_IMEM_AGE_FLAGr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x280000,
+			(32 / 8),
+			0,
+			0x7ffff + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_cfgmt_qmu_imem_age_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_lkybkt2cngth",
+			ETM_QMU_CFG_QSCH_LKYBKT2CNGTHr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x2040,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_cfg_qsch_lkybkt2cngth_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_lkybkt1cngth",
+			ETM_QMU_CFG_QSCH_LKYBKT1CNGTHr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x2030,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_cfg_qsch_lkybkt1cngth_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_lkybkt3cngth",
+			ETM_QMU_CFG_QSCH_LKYBKT3CNGTHr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x2050,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_cfg_qsch_lkybkt3cngth_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_rm_mul_mcn1_credit_value",
+			ETM_QMU_CFG_QSCH_RM_MUL_MCN1_CREDIT_VALUEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x2060,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_cfg_qsch_rm_mul_mcn1_credit_value_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_rm_mul_mcn2_credit_value",
+			ETM_QMU_CFG_QSCH_RM_MUL_MCN2_CREDIT_VALUEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x2070,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_cfg_qsch_rm_mul_mcn2_credit_value_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_rm_mul_mcn3_credit_value",
+			ETM_QMU_CFG_QSCH_RM_MUL_MCN3_CREDIT_VALUEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x2080,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			1,
+			1,
+			g_etm_qmu_cfg_qsch_rm_mul_mcn3_credit_value_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn1_rand_ansr_seed",
+			ETM_QMU_RM_MUL_MCN1_RAND_ANSR_SEEDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_qmu_rm_mul_mcn1_rand_ansr_seed_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn2_rand_ansr_seed",
+			ETM_QMU_RM_MUL_MCN2_RAND_ANSR_SEEDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2091,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_qmu_rm_mul_mcn2_rand_ansr_seed_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn3_rand_ansr_seed",
+			ETM_QMU_RM_MUL_MCN3_RAND_ANSR_SEEDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2092,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_qmu_rm_mul_mcn3_rand_ansr_seed_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn1_rand_ansr_th",
+			ETM_QMU_RM_MUL_MCN1_RAND_ANSR_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2093,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn1_rand_ansr_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn2_rand_ansr_th",
+			ETM_QMU_RM_MUL_MCN2_RAND_ANSR_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn2_rand_ansr_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn3_rand_ansr_th",
+			ETM_QMU_RM_MUL_MCN3_RAND_ANSR_THr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2095,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn3_rand_ansr_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn1_rand_hold_base",
+			ETM_QMU_RM_MUL_MCN1_RAND_HOLD_BASEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2096,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_qmu_rm_mul_mcn1_rand_hold_base_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn2_rand_hold_base",
+			ETM_QMU_RM_MUL_MCN2_RAND_HOLD_BASEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2097,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_qmu_rm_mul_mcn2_rand_hold_base_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn3_rand_hold_base",
+			ETM_QMU_RM_MUL_MCN3_RAND_HOLD_BASEr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2098,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_qmu_rm_mul_mcn3_rand_hold_base_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn1_rand_sel_mask",
+			ETM_QMU_RM_MUL_MCN1_RAND_SEL_MASKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2099,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn1_rand_sel_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn2_rand_sel_mask",
+			ETM_QMU_RM_MUL_MCN2_RAND_SEL_MASKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x209a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn2_rand_sel_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn3_rand_sel_mask",
+			ETM_QMU_RM_MUL_MCN3_RAND_SEL_MASKr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x209b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn3_rand_sel_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn1_rand_sel_seed_reg0",
+			ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x209c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			8,
+			g_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn1_rand_sel_seed_reg1",
+			ETM_QMU_RM_MUL_MCN1_RAND_SEL_SEED_REG1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x209d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn1_rand_sel_seed_reg1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn2_rand_sel_seed_reg0",
+			ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x209e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			8,
+			g_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn2_rand_sel_seed_reg1",
+			ETM_QMU_RM_MUL_MCN2_RAND_SEL_SEED_REG1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x209f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn2_rand_sel_seed_reg1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn3_rand_sel_seed_reg0",
+			ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			8,
+			g_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn3_rand_sel_seed_reg1",
+			ETM_QMU_RM_MUL_MCN3_RAND_SEL_SEED_REG1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20a1,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn3_rand_sel_seed_reg1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn1_step_wait_th1",
+			ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20a2,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn1_step_wait_th1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn1_step_wait_th2",
+			ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20a3,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn1_step_wait_th2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn1_step_wait_th3",
+			ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn1_step_wait_th3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn1_step_wait_th4",
+			ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH4r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20a5,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn1_step_wait_th4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn1_step_wait_th5",
+			ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH5r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20a6,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn1_step_wait_th5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn1_step_wait_th6",
+			ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH6r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20a7,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn1_step_wait_th6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn1_step_wait_th7",
+			ETM_QMU_RM_MUL_MCN1_STEP_WAIT_TH7r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn1_step_wait_th7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn2_step_wait_th1",
+			ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20a9,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn2_step_wait_th1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn2_step_wait_th2",
+			ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20aa,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn2_step_wait_th2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn2_step_wait_th3",
+			ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20ab,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn2_step_wait_th3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn2_step_wait_th4",
+			ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH4r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn2_step_wait_th4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn2_step_wait_th5",
+			ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH5r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20ad,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn2_step_wait_th5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn2_step_wait_th6",
+			ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH6r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20ae,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn2_step_wait_th6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn2_step_wait_th7",
+			ETM_QMU_RM_MUL_MCN2_STEP_WAIT_TH7r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20af,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn2_step_wait_th7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn3_step_wait_th1",
+			ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn3_step_wait_th1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn3_step_wait_th2",
+			ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20b1,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn3_step_wait_th2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn3_step_wait_th3",
+			ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20b2,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn3_step_wait_th3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn3_step_wait_th4",
+			ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH4r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20b3,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn3_step_wait_th4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn3_step_wait_th5",
+			ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH5r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn3_step_wait_th5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn3_step_wait_th6",
+			ETM_QMU_RM_MUL_MCN3_STEP_WAIT_TH6r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20b5,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn3_step_wait_th6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rm_mul_mcn3step_wait_th7",
+			ETM_QMU_RM_MUL_MCN3STEP_WAIT_TH7r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20b6,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_rm_mul_mcn3step_wait_th7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate0",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE0r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20b7,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate1",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE1r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate2",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE2r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20b9,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate3",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE3r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20ba,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate4",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE4r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20bb,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate5",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE5r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate6",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE6r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20bd,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate7",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE7r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20be,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate8",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE8r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20bf,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate9",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE9r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate10",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE10r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20c1,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate11",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE11r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20c2,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate12",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE12r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20c3,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate13",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE13r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate14",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE14r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20c5,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate15",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE15r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20c6,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate16",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE16r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20c7,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate17",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE17r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate18",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE18r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20c9,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate19",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE19r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20ca,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate19_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate20",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE20r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20cb,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate20_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate21",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE21r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate21_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate22",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE22r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20cd,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate22_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate23",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE23r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20ce,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate23_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate24",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE24r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20cf,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate24_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate25",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE25r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate25_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate26",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE26r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20d1,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate27",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE27r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20d2,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate27_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate28",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE28r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20d3,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate28_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate29",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE29r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate29_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate30",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE30r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20d5,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate30_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate31",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE31r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20d6,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate31_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate32",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE32r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20d7,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate33",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE33r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate33_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate34",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE34r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20d9,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate34_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate35",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE35r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20da,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate35_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_mulcrdcntrate36",
+			ETM_QMU_CFG_QSCH_MULCRDCNTRATE36r,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20db,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_mulcrdcntrate36_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_rm_mul_mcn1_rand_hold_shift",
+			ETM_QMU_CFG_QSCH_RM_MUL_MCN1_RAND_HOLD_SHIFTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_rm_mul_mcn1_rand_hold_shift_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_rm_mul_mcn2_rand_hold_shift",
+			ETM_QMU_CFG_QSCH_RM_MUL_MCN2_RAND_HOLD_SHIFTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20dd,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_rm_mul_mcn2_rand_hold_shift_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_qsch_rm_mul_mcn3_rand_hold_shift",
+			ETM_QMU_CFG_QSCH_RM_MUL_MCN3_RAND_HOLD_SHIFTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x20de,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_cfg_qsch_rm_mul_mcn3_rand_hold_shift_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"last_drop_qnum_get",
+			ETM_QMU_LAST_DROP_QNUM_GETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2806,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_etm_qmu_last_drop_qnum_get_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crdt_qmu_credit_cnt",
+			ETM_QMU_CRDT_QMU_CREDIT_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2807,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_crdt_qmu_credit_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_to_qsch_report_cnt",
+			ETM_QMU_QMU_TO_QSCH_REPORT_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2808,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_to_qsch_report_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_to_cgavd_report_cnt",
+			ETM_QMU_QMU_TO_CGAVD_REPORT_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2809,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_to_cgavd_report_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_crdt_crs_normal_cnt",
+			ETM_QMU_QMU_CRDT_CRS_NORMAL_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x280a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_crdt_crs_normal_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_crdt_crs_off_cnt",
+			ETM_QMU_QMU_CRDT_CRS_OFF_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x280b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_crdt_crs_off_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qsch_qlist_shedule_cnt",
+			ETM_QMU_QSCH_QLIST_SHEDULE_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x280c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qsch_qlist_shedule_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qsch_qlist_sch_ept_cnt",
+			ETM_QMU_QSCH_QLIST_SCH_EPT_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x280d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qsch_qlist_sch_ept_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_to_mmu_blk_wr_cnt",
+			ETM_QMU_QMU_TO_MMU_BLK_WR_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x280e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_to_mmu_blk_wr_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_to_csw_blk_rd_cnt",
+			ETM_QMU_QMU_TO_CSW_BLK_RD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x280f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_to_csw_blk_rd_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_to_mmu_sop_wr_cnt",
+			ETM_QMU_QMU_TO_MMU_SOP_WR_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2810,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_to_mmu_sop_wr_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_to_mmu_eop_wr_cnt",
+			ETM_QMU_QMU_TO_MMU_EOP_WR_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2811,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_to_mmu_eop_wr_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_to_mmu_drop_wr_cnt",
+			ETM_QMU_QMU_TO_MMU_DROP_WR_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2812,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_to_mmu_drop_wr_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_to_csw_sop_rd_cnt",
+			ETM_QMU_QMU_TO_CSW_SOP_RD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2813,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_to_csw_sop_rd_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_to_csw_eop_rd_cnt",
+			ETM_QMU_QMU_TO_CSW_EOP_RD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2814,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_to_csw_eop_rd_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"qmu_to_csw_drop_rd_cnt",
+			ETM_QMU_QMU_TO_CSW_DROP_RD_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2815,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_qmu_to_csw_drop_rd_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mmu_to_qmu_wr_release_cnt",
+			ETM_QMU_MMU_TO_QMU_WR_RELEASE_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2816,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_mmu_to_qmu_wr_release_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mmu_to_qmu_rd_release_cnt",
+			ETM_QMU_MMU_TO_QMU_RD_RELEASE_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2817,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_mmu_to_qmu_rd_release_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"observe_qnum_set",
+			ETM_QMU_OBSERVE_QNUM_SETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2820,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_observe_qnum_set_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_q_pkt_received",
+			ETM_QMU_SPEC_Q_PKT_RECEIVEDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2821,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_q_pkt_received_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_q_pkt_dropped",
+			ETM_QMU_SPEC_Q_PKT_DROPPEDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2822,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_q_pkt_dropped_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_q_pkt_scheduled",
+			ETM_QMU_SPEC_Q_PKT_SCHEDULEDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2823,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_q_pkt_scheduled_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_q_wr_cmd_sent",
+			ETM_QMU_SPEC_Q_WR_CMD_SENTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2824,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_q_wr_cmd_sent_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_q_rd_cmd_sent",
+			ETM_QMU_SPEC_Q_RD_CMD_SENTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2825,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_q_rd_cmd_sent_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_q_pkt_enq",
+			ETM_QMU_SPEC_Q_PKT_ENQr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2826,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_q_pkt_enq_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_q_pkt_deq",
+			ETM_QMU_SPEC_Q_PKT_DEQr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2827,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_q_pkt_deq_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_q_crdt_uncon_received",
+			ETM_QMU_SPEC_Q_CRDT_UNCON_RECEIVEDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2828,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_q_crdt_uncon_received_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_q_crdt_cong_received",
+			ETM_QMU_SPEC_Q_CRDT_CONG_RECEIVEDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2829,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_q_crdt_cong_received_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_q_crs_normal_cnt",
+			ETM_QMU_SPEC_Q_CRS_NORMAL_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x282a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_q_crs_normal_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_q_crs_off_cnt",
+			ETM_QMU_SPEC_Q_CRS_OFF_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x282b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_q_crs_off_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"observe_batch_set",
+			ETM_QMU_OBSERVE_BATCH_SETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x282c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_observe_batch_set_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_bat_pkt_received",
+			ETM_QMU_SPEC_BAT_PKT_RECEIVEDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x282d,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_bat_pkt_received_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_bat_pkt_dropped",
+			ETM_QMU_SPEC_BAT_PKT_DROPPEDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x282e,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_bat_pkt_dropped_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_bat_blk_scheduled",
+			ETM_QMU_SPEC_BAT_BLK_SCHEDULEDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x282f,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_bat_blk_scheduled_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_bat_wr_cmd_sent",
+			ETM_QMU_SPEC_BAT_WR_CMD_SENTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2830,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_bat_wr_cmd_sent_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_bat_rd_cmd_sent",
+			ETM_QMU_SPEC_BAT_RD_CMD_SENTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2831,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_bat_rd_cmd_sent_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_bat_pkt_enq",
+			ETM_QMU_SPEC_BAT_PKT_ENQr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2832,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_bat_pkt_enq_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_bat_pkt_deq",
+			ETM_QMU_SPEC_BAT_PKT_DEQr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2833,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_bat_pkt_deq_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_bat_crdt_uncon_received",
+			ETM_QMU_SPEC_BAT_CRDT_UNCON_RECEIVEDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2834,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_bat_crdt_uncon_received_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_bat_crdt_cong_received",
+			ETM_QMU_SPEC_BAT_CRDT_CONG_RECEIVEDr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2835,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_bat_crdt_cong_received_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_bat_crs_normal_cnt",
+			ETM_QMU_SPEC_BAT_CRS_NORMAL_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2836,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_bat_crs_normal_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_bat_crs_off_cnt",
+			ETM_QMU_SPEC_BAT_CRS_OFF_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2837,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_bat_crs_off_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"bcntm_ovfl_qnum_get",
+			ETM_QMU_BCNTM_OVFL_QNUM_GETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2844,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_bcntm_ovfl_qnum_get_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crbal_a_ovf_qnum_get",
+			ETM_QMU_CRBAL_A_OVF_QNUM_GETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2845,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_crbal_a_ovf_qnum_get_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crbal_b_ovf_qnum_get",
+			ETM_QMU_CRBAL_B_OVF_QNUM_GETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2846,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_crbal_b_ovf_qnum_get_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"crbal_drop_qnum_get",
+			ETM_QMU_CRBAL_DROP_QNUM_GETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2847,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_crbal_drop_qnum_get_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"deq_flg_report_cnt",
+			ETM_QMU_DEQ_FLG_REPORT_CNTr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2848,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_deq_flg_report_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_q_crs_get",
+			ETM_QMU_SPEC_Q_CRS_GETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x2849,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_q_crs_get_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_q_crs_in_get",
+			ETM_QMU_SPEC_Q_CRS_IN_GETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x284a,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_q_crs_in_get_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spec_q_crs_flg_csol_get",
+			ETM_QMU_SPEC_Q_CRS_FLG_CSOL_GETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x284b,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_spec_q_crs_flg_csol_get_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ept_sch_qnum_get",
+			ETM_QMU_EPT_SCH_QNUM_GETr,
+			ETM,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			0x284c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_etm_qmu_ept_sch_qnum_get_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pcie_ddr_switch",
+			CFG_PCIE_PCIE_DDR_SWITCHr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_pcie_ddr_switch_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"user0_int_en",
+			CFG_PCIE_USER0_INT_ENr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_user0_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"user0_int_mask",
+			CFG_PCIE_USER0_INT_MASKr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_user0_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"user0_int_status",
+			CFG_PCIE_USER0_INT_STATUSr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x00c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_user0_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"user1_int_en",
+			CFG_PCIE_USER1_INT_ENr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_user1_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"user1_int_mask",
+			CFG_PCIE_USER1_INT_MASKr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_user1_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"user1_int_status",
+			CFG_PCIE_USER1_INT_STATUSr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_user1_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"user2_int_en",
+			CFG_PCIE_USER2_INT_ENr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x01c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_user2_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"user2_int_mask",
+			CFG_PCIE_USER2_INT_MASKr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_user2_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"user2_int_status",
+			CFG_PCIE_USER2_INT_STATUSr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_user2_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ecc_1b_int_en",
+			CFG_PCIE_ECC_1B_INT_ENr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_ecc_1b_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ecc_1b_int_mask",
+			CFG_PCIE_ECC_1B_INT_MASKr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x02c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_ecc_1b_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ecc_1b_int_status",
+			CFG_PCIE_ECC_1B_INT_STATUSr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_ecc_1b_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ecc_2b_int_en",
+			CFG_PCIE_ECC_2B_INT_ENr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_ecc_2b_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ecc_2b_int_mask",
+			CFG_PCIE_ECC_2B_INT_MASKr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_ecc_2b_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ecc_2b_int_status",
+			CFG_PCIE_ECC_2B_INT_STATUSr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x03c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_ecc_2b_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_int_status",
+			CFG_PCIE_CFG_INT_STATUSr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_cfg_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"i_core_to_cntl",
+			CFG_PCIE_I_CORE_TO_CNTLr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_i_core_to_cntl_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_in_low",
+			CFG_PCIE_TEST_IN_LOWr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_in_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_in_high",
+			CFG_PCIE_TEST_IN_HIGHr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x04c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_in_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"local_interrupt_out",
+			CFG_PCIE_LOCAL_INTERRUPT_OUTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_local_interrupt_out_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pl_ltssm",
+			CFG_PCIE_PL_LTSSMr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_pl_ltssm_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out0",
+			CFG_PCIE_TEST_OUT0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out1",
+			CFG_PCIE_TEST_OUT1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x05c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out2",
+			CFG_PCIE_TEST_OUT2r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out3",
+			CFG_PCIE_TEST_OUT3r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out4",
+			CFG_PCIE_TEST_OUT4r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out5",
+			CFG_PCIE_TEST_OUT5r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x06c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out6",
+			CFG_PCIE_TEST_OUT6r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x070,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out7",
+			CFG_PCIE_TEST_OUT7r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x074,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sync_o_core_status",
+			CFG_PCIE_SYNC_O_CORE_STATUSr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x078,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_sync_o_core_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sync_o_alert_dbe",
+			CFG_PCIE_SYNC_O_ALERT_DBEr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x07c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_sync_o_alert_dbe_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sync_o_alert_sbe",
+			CFG_PCIE_SYNC_O_ALERT_SBEr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_sync_o_alert_sbe_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sync_o_link_loopback_en",
+			CFG_PCIE_SYNC_O_LINK_LOOPBACK_ENr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_sync_o_link_loopback_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sync_o_local_fs_lf_valid",
+			CFG_PCIE_SYNC_O_LOCAL_FS_LF_VALIDr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_sync_o_local_fs_lf_valid_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sync_o_rx_idle_detect",
+			CFG_PCIE_SYNC_O_RX_IDLE_DETECTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x08c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_sync_o_rx_idle_detect_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sync_o_rx_rdy",
+			CFG_PCIE_SYNC_O_RX_RDYr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_sync_o_rx_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sync_o_tx_rdy",
+			CFG_PCIE_SYNC_O_TX_RDYr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_sync_o_tx_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pcie_link_up_cnt",
+			CFG_PCIE_PCIE_LINK_UP_CNTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x098,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_pcie_link_up_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out_pcie0",
+			CFG_PCIE_TEST_OUT_PCIE0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x09c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out_pcie0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out_pcie1",
+			CFG_PCIE_TEST_OUT_PCIE1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out_pcie1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out_pcie2",
+			CFG_PCIE_TEST_OUT_PCIE2r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out_pcie2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out_pcie3",
+			CFG_PCIE_TEST_OUT_PCIE3r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out_pcie3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out_pcie4",
+			CFG_PCIE_TEST_OUT_PCIE4r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out_pcie4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out_pcie5",
+			CFG_PCIE_TEST_OUT_PCIE5r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out_pcie5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out_pcie6",
+			CFG_PCIE_TEST_OUT_PCIE6r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out_pcie6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out_pcie7",
+			CFG_PCIE_TEST_OUT_PCIE7r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out_pcie7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out_pcie8",
+			CFG_PCIE_TEST_OUT_PCIE8r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out_pcie8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out_pcie9",
+			CFG_PCIE_TEST_OUT_PCIE9r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out_pcie9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out_pcie10",
+			CFG_PCIE_TEST_OUT_PCIE10r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out_pcie10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out_pcie11",
+			CFG_PCIE_TEST_OUT_PCIE11r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out_pcie11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out_pcie12",
+			CFG_PCIE_TEST_OUT_PCIE12r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out_pcie12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out_pcie13",
+			CFG_PCIE_TEST_OUT_PCIE13r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out_pcie13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out_pcie14",
+			CFG_PCIE_TEST_OUT_PCIE14r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out_pcie14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_out_pcie15",
+			CFG_PCIE_TEST_OUT_PCIE15r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_test_out_pcie15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_repeat_en",
+			CFG_PCIE_INT_REPEAT_ENr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x0e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_int_repeat_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_awid_axi_mst",
+			CFG_PCIE_DBG_AWID_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x400,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_awid_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_awaddr_axi_mst0",
+			CFG_PCIE_DBG_AWADDR_AXI_MST0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x404,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_awaddr_axi_mst0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_awaddr_axi_mst1",
+			CFG_PCIE_DBG_AWADDR_AXI_MST1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x408,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_awaddr_axi_mst1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_awlen_axi_mst",
+			CFG_PCIE_DBG_AWLEN_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x40c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_awlen_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_awsize_axi_mst",
+			CFG_PCIE_DBG_AWSIZE_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x410,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_awsize_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_awburst_axi_mst",
+			CFG_PCIE_DBG_AWBURST_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x414,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_awburst_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_awlock_axi_mst",
+			CFG_PCIE_DBG_AWLOCK_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x418,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_awlock_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_awcache_axi_mst",
+			CFG_PCIE_DBG_AWCACHE_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x41c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_awcache_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_awprot_axi_mst",
+			CFG_PCIE_DBG_AWPROT_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x420,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_awprot_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_wid_axi_mst",
+			CFG_PCIE_DBG_WID_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x424,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_wid_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_wdata_axi_mst0",
+			CFG_PCIE_DBG_WDATA_AXI_MST0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x428,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_wdata_axi_mst0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_wdata_axi_mst1",
+			CFG_PCIE_DBG_WDATA_AXI_MST1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x42c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_wdata_axi_mst1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_wdata_axi_mst2",
+			CFG_PCIE_DBG_WDATA_AXI_MST2r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x430,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_wdata_axi_mst2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_wdata_axi_mst3",
+			CFG_PCIE_DBG_WDATA_AXI_MST3r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x434,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_wdata_axi_mst3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_wstrb_axi_mst",
+			CFG_PCIE_DBG_WSTRB_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x438,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_wstrb_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_wlast_axi_mst",
+			CFG_PCIE_DBG_WLAST_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x43c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_wlast_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_arid_axi_mst",
+			CFG_PCIE_DBG_ARID_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x440,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_arid_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_araddr_axi_mst0",
+			CFG_PCIE_DBG_ARADDR_AXI_MST0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x444,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_araddr_axi_mst0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_araddr_axi_mst1",
+			CFG_PCIE_DBG_ARADDR_AXI_MST1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x448,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_araddr_axi_mst1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_arlen_axi_mst",
+			CFG_PCIE_DBG_ARLEN_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x44c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_arlen_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_arsize_axi_mst",
+			CFG_PCIE_DBG_ARSIZE_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x450,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_arsize_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_arburst_axi_mst",
+			CFG_PCIE_DBG_ARBURST_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x454,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_arburst_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_arlock_axi_mst",
+			CFG_PCIE_DBG_ARLOCK_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x458,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_arlock_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_arcache_axi_mst",
+			CFG_PCIE_DBG_ARCACHE_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x45c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_arcache_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_arprot_axi_mst",
+			CFG_PCIE_DBG_ARPROT_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x460,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_arprot_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_rdata_axi_mst0",
+			CFG_PCIE_DBG_RDATA_AXI_MST0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x464,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_rdata_axi_mst0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_rdata_axi_mst1",
+			CFG_PCIE_DBG_RDATA_AXI_MST1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x468,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_rdata_axi_mst1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_rdata_axi_mst2",
+			CFG_PCIE_DBG_RDATA_AXI_MST2r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x46c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_rdata_axi_mst2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_rdata_axi_mst3",
+			CFG_PCIE_DBG_RDATA_AXI_MST3r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x470,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_rdata_axi_mst3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"axi_mst_state",
+			CFG_PCIE_AXI_MST_STATEr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x474,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_axi_mst_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"axi_cfg_state",
+			CFG_PCIE_AXI_CFG_STATEr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x478,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_axi_cfg_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"axi_slv_rd_state",
+			CFG_PCIE_AXI_SLV_RD_STATEr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x47c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_axi_slv_rd_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"axi_slv_wr_state",
+			CFG_PCIE_AXI_SLV_WR_STATEr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x480,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_axi_slv_wr_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"axim_delay_en",
+			CFG_PCIE_AXIM_DELAY_ENr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x484,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_axim_delay_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"axim_delay",
+			CFG_PCIE_AXIM_DELAYr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x488,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_axim_delay_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"axim_speed_wr",
+			CFG_PCIE_AXIM_SPEED_WRr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x48c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_axim_speed_wr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"axim_speed_rd",
+			CFG_PCIE_AXIM_SPEED_RDr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x490,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_axim_speed_rd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_awaddr_axi_slv0",
+			CFG_PCIE_DBG_AWADDR_AXI_SLV0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_awaddr_axi_slv0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_awaddr_axi_slv1",
+			CFG_PCIE_DBG_AWADDR_AXI_SLV1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_awaddr_axi_slv1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg0_wdata_axi_slv0",
+			CFG_PCIE_DBG0_WDATA_AXI_SLV0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg0_wdata_axi_slv0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg0_wdata_axi_slv1",
+			CFG_PCIE_DBG0_WDATA_AXI_SLV1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg0_wdata_axi_slv1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg0_wdata_axi_slv2",
+			CFG_PCIE_DBG0_WDATA_AXI_SLV2r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg0_wdata_axi_slv2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg0_wdata_axi_slv3",
+			CFG_PCIE_DBG0_WDATA_AXI_SLV3r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg0_wdata_axi_slv3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg1_wdata_axi_slv0",
+			CFG_PCIE_DBG1_WDATA_AXI_SLV0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg1_wdata_axi_slv0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg1_wdata_axi_slv1",
+			CFG_PCIE_DBG1_WDATA_AXI_SLV1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg1_wdata_axi_slv1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg1_wdata_axi_slv2",
+			CFG_PCIE_DBG1_WDATA_AXI_SLV2r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg1_wdata_axi_slv2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg1_wdata_axi_slv3",
+			CFG_PCIE_DBG1_WDATA_AXI_SLV3r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg1_wdata_axi_slv3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg2_wdata_axi_slv0",
+			CFG_PCIE_DBG2_WDATA_AXI_SLV0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg2_wdata_axi_slv0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg2_wdata_axi_slv1",
+			CFG_PCIE_DBG2_WDATA_AXI_SLV1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg2_wdata_axi_slv1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg2_wdata_axi_slv2",
+			CFG_PCIE_DBG2_WDATA_AXI_SLV2r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg2_wdata_axi_slv2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg2_wdata_axi_slv3",
+			CFG_PCIE_DBG2_WDATA_AXI_SLV3r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg2_wdata_axi_slv3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg3_wdata_axi_slv0",
+			CFG_PCIE_DBG3_WDATA_AXI_SLV0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg3_wdata_axi_slv0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg3_wdata_axi_slv1",
+			CFG_PCIE_DBG3_WDATA_AXI_SLV1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x4fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg3_wdata_axi_slv1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg3_wdata_axi_slv2",
+			CFG_PCIE_DBG3_WDATA_AXI_SLV2r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x500,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg3_wdata_axi_slv2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg3_wdata_axi_slv3",
+			CFG_PCIE_DBG3_WDATA_AXI_SLV3r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x504,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg3_wdata_axi_slv3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg4_wdata_axi_slv0",
+			CFG_PCIE_DBG4_WDATA_AXI_SLV0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x508,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg4_wdata_axi_slv0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg4_wdata_axi_slv1",
+			CFG_PCIE_DBG4_WDATA_AXI_SLV1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x50c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg4_wdata_axi_slv1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg4_wdata_axi_slv2",
+			CFG_PCIE_DBG4_WDATA_AXI_SLV2r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x510,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg4_wdata_axi_slv2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg4_wdata_axi_slv3",
+			CFG_PCIE_DBG4_WDATA_AXI_SLV3r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x514,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg4_wdata_axi_slv3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg5_wdata_axi_slv0",
+			CFG_PCIE_DBG5_WDATA_AXI_SLV0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x518,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg5_wdata_axi_slv0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg5_wdata_axi_slv1",
+			CFG_PCIE_DBG5_WDATA_AXI_SLV1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x51c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg5_wdata_axi_slv1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg5_wdata_axi_slv2",
+			CFG_PCIE_DBG5_WDATA_AXI_SLV2r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x520,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg5_wdata_axi_slv2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg5_wdata_axi_slv3",
+			CFG_PCIE_DBG5_WDATA_AXI_SLV3r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x524,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg5_wdata_axi_slv3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg6_wdata_axi_slv0",
+			CFG_PCIE_DBG6_WDATA_AXI_SLV0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x528,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg6_wdata_axi_slv0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg6_wdata_axi_slv1",
+			CFG_PCIE_DBG6_WDATA_AXI_SLV1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x52c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg6_wdata_axi_slv1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg6_wdata_axi_slv2",
+			CFG_PCIE_DBG6_WDATA_AXI_SLV2r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x530,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg6_wdata_axi_slv2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg6_wdata_axi_slv3",
+			CFG_PCIE_DBG6_WDATA_AXI_SLV3r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x534,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg6_wdata_axi_slv3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg7_wdata_axi_slv0",
+			CFG_PCIE_DBG7_WDATA_AXI_SLV0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x538,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg7_wdata_axi_slv0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg7_wdata_axi_slv1",
+			CFG_PCIE_DBG7_WDATA_AXI_SLV1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x53c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg7_wdata_axi_slv1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg7_wdata_axi_slv2",
+			CFG_PCIE_DBG7_WDATA_AXI_SLV2r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x540,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg7_wdata_axi_slv2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg7_wdata_axi_slv3",
+			CFG_PCIE_DBG7_WDATA_AXI_SLV3r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x544,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg7_wdata_axi_slv3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg8_wdata_axi_slv0",
+			CFG_PCIE_DBG8_WDATA_AXI_SLV0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x548,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg8_wdata_axi_slv0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg8_wdata_axi_slv1",
+			CFG_PCIE_DBG8_WDATA_AXI_SLV1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x54c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg8_wdata_axi_slv1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg8_wdata_axi_slv2",
+			CFG_PCIE_DBG8_WDATA_AXI_SLV2r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x550,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg8_wdata_axi_slv2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg8_wdata_axi_slv3",
+			CFG_PCIE_DBG8_WDATA_AXI_SLV3r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x554,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg8_wdata_axi_slv3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg9_wdata_axi_slv0",
+			CFG_PCIE_DBG9_WDATA_AXI_SLV0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x558,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg9_wdata_axi_slv0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg9_wdata_axi_slv1",
+			CFG_PCIE_DBG9_WDATA_AXI_SLV1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x55c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg9_wdata_axi_slv1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg9_wdata_axi_slv2",
+			CFG_PCIE_DBG9_WDATA_AXI_SLV2r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x560,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg9_wdata_axi_slv2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg9_wdata_axi_slv3",
+			CFG_PCIE_DBG9_WDATA_AXI_SLV3r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x564,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg9_wdata_axi_slv3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_awlen_axi_slv",
+			CFG_PCIE_DBG_AWLEN_AXI_SLVr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x568,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_awlen_axi_slv_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_wlast_axi_slv",
+			CFG_PCIE_DBG_WLAST_AXI_SLVr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x56c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_wlast_axi_slv_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_araddr_axi_slv0",
+			CFG_PCIE_DBG_ARADDR_AXI_SLV0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x580,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_araddr_axi_slv0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_araddr_axi_slv1",
+			CFG_PCIE_DBG_ARADDR_AXI_SLV1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x584,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_araddr_axi_slv1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg0_rdata_axi_slv0",
+			CFG_PCIE_DBG0_RDATA_AXI_SLV0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x588,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg0_rdata_axi_slv0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg0_rdata_axi_slv1",
+			CFG_PCIE_DBG0_RDATA_AXI_SLV1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x58c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg0_rdata_axi_slv1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg0_rdata_axi_slv2",
+			CFG_PCIE_DBG0_RDATA_AXI_SLV2r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x590,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg0_rdata_axi_slv2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg0_rdata_axi_slv3",
+			CFG_PCIE_DBG0_RDATA_AXI_SLV3r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x594,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg0_rdata_axi_slv3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg1_rdata_axi_slv0",
+			CFG_PCIE_DBG1_RDATA_AXI_SLV0r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x598,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg1_rdata_axi_slv0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg1_rdata_axi_slv1",
+			CFG_PCIE_DBG1_RDATA_AXI_SLV1r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x59c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg1_rdata_axi_slv1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg1_rdata_axi_slv2",
+			CFG_PCIE_DBG1_RDATA_AXI_SLV2r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x5a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg1_rdata_axi_slv2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg1_rdata_axi_slv3",
+			CFG_PCIE_DBG1_RDATA_AXI_SLV3r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x5a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg1_rdata_axi_slv3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_rlast_axi_slv",
+			CFG_PCIE_DBG_RLAST_AXI_SLVr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_PCIE_BASE_ADDR + 0x5a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_pcie_dbg_rlast_axi_slv_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_enable",
+			CFG_DMA_DMA_ENABLEr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_enable_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"up_req",
+			CFG_DMA_UP_REQr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_up_req_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_up_current_state",
+			CFG_DMA_DMA_UP_CURRENT_STATEr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_up_current_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_up_req_ack",
+			CFG_DMA_DMA_UP_REQ_ACKr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x00c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_up_req_ack_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_done_latch",
+			CFG_DMA_DMA_DONE_LATCHr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_done_latch_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_up_cpu_addr_low32",
+			CFG_DMA_DMA_UP_CPU_ADDR_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_up_cpu_addr_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_up_cpu_addr_high32",
+			CFG_DMA_DMA_UP_CPU_ADDR_HIGH32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x01c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_up_cpu_addr_high32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_up_se_addr",
+			CFG_DMA_DMA_UP_SE_ADDRr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_up_se_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_done_int",
+			CFG_DMA_DMA_DONE_INTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_done_int_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sp_cfg",
+			CFG_DMA_SP_CFGr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_sp_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_ing",
+			CFG_DMA_DMA_INGr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x03c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_ing_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rd_timeout_thresh",
+			CFG_DMA_RD_TIMEOUT_THRESHr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_rd_timeout_thresh_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_tab_sta_up_fifo_gap",
+			CFG_DMA_DMA_TAB_STA_UP_FIFO_GAPr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_tab_sta_up_fifo_gap_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_mac_tim",
+			CFG_DMA_CFG_MAC_TIMr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_cfg_mac_tim_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_mac_num",
+			CFG_DMA_CFG_MAC_NUMr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x04c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_cfg_mac_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"init_bd_addr",
+			CFG_DMA_INIT_BD_ADDRr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_init_bd_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mac_up_bd_addr1_low32",
+			CFG_DMA_MAC_UP_BD_ADDR1_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_mac_up_bd_addr1_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mac_up_bd_addr1_high32",
+			CFG_DMA_MAC_UP_BD_ADDR1_HIGH32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_mac_up_bd_addr1_high32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mac_up_bd_addr2_low32",
+			CFG_DMA_MAC_UP_BD_ADDR2_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x05c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_mac_up_bd_addr2_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mac_up_bd_addr2_high32",
+			CFG_DMA_MAC_UP_BD_ADDR2_HIGH32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_mac_up_bd_addr2_high32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_mac_max_num",
+			CFG_DMA_CFG_MAC_MAX_NUMr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_cfg_mac_max_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_wbuf_ff_empty",
+			CFG_DMA_DMA_WBUF_FF_EMPTYr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_wbuf_ff_empty_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_wbuf_state",
+			CFG_DMA_DMA_WBUF_STATEr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x06c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_wbuf_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_mac_bd_addr_low32",
+			CFG_DMA_DMA_MAC_BD_ADDR_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x070,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_mac_bd_addr_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_mac_bd_addr_high32",
+			CFG_DMA_DMA_MAC_BD_ADDR_HIGH32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x074,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_mac_bd_addr_high32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mac_up_enable",
+			CFG_DMA_MAC_UP_ENABLEr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x078,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_mac_up_enable_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mac_endian",
+			CFG_DMA_MAC_ENDIANr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x07c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_mac_endian_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"up_endian",
+			CFG_DMA_UP_ENDIANr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_up_endian_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_up_rd_cnt_latch",
+			CFG_DMA_DMA_UP_RD_CNT_LATCHr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_up_rd_cnt_latch_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_up_rcv_cnt_latch",
+			CFG_DMA_DMA_UP_RCV_CNT_LATCHr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_up_rcv_cnt_latch_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_up_cnt_latch",
+			CFG_DMA_DMA_UP_CNT_LATCHr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x08c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_up_cnt_latch_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_bd_pulse",
+			CFG_DMA_CPU_RD_BD_PULSEr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_cpu_rd_bd_pulse_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_bd_threshold",
+			CFG_DMA_CPU_BD_THRESHOLDr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_cpu_bd_threshold_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_bd_used_cnt",
+			CFG_DMA_CPU_BD_USED_CNTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x098,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_cpu_bd_used_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_up_rcv_status",
+			CFG_DMA_DMA_UP_RCV_STATUSr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x09c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_up_rcv_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"slv_rid_err_en",
+			CFG_DMA_SLV_RID_ERR_ENr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_slv_rid_err_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"slv_rresp_err_en",
+			CFG_DMA_SLV_RRESP_ERR_ENr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_slv_rresp_err_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_rdbk_ff_full",
+			CFG_DMA_SE_RDBK_FF_FULLr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_se_rdbk_ff_full_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_up_data_count",
+			CFG_DMA_DMA_UP_DATA_COUNTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_up_data_count_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_mwr_fifo_afull_gap",
+			CFG_DMA_DMA_MWR_FIFO_AFULL_GAPr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0xb0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_mwr_fifo_afull_gap_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_info_fifo_afull_gap",
+			CFG_DMA_DMA_INFO_FIFO_AFULL_GAPr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0xb4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_info_fifo_afull_gap_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_rd_timeout_set",
+			CFG_DMA_DMA_RD_TIMEOUT_SETr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_rd_timeout_set_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_bd_dat_err_en",
+			CFG_DMA_DMA_BD_DAT_ERR_ENr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_bd_dat_err_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_repeat_cnt",
+			CFG_DMA_DMA_REPEAT_CNTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_repeat_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_rd_timeout_en",
+			CFG_DMA_DMA_RD_TIMEOUT_ENr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_rd_timeout_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_repeat_read",
+			CFG_DMA_DMA_REPEAT_READr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_repeat_read_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_repeat_read_en",
+			CFG_DMA_DMA_REPEAT_READ_ENr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_repeat_read_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"bd_ctl_state",
+			CFG_DMA_BD_CTL_STATEr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_bd_ctl_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_done_int_cnt_wr",
+			CFG_DMA_DMA_DONE_INT_CNT_WRr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_done_int_cnt_wr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_done_int_cnt_mac",
+			CFG_DMA_DMA_DONE_INT_CNT_MACr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_done_int_cnt_mac_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"current_mac_num",
+			CFG_DMA_CURRENT_MAC_NUMr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_current_mac_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_mac_afifo_afull",
+			CFG_DMA_CFG_MAC_AFIFO_AFULLr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_cfg_mac_afifo_afull_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_mac_ff_full",
+			CFG_DMA_DMA_MAC_FF_FULLr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_dma_dma_mac_ff_full_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"user_axi_mst",
+			CFG_DMA_USER_AXI_MSTr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_DMA_BASE_ADDR + 0x0100,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_cfg_dma_user_axi_mst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sbus_state",
+			CFG_CSR_SBUS_STATEr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_sbus_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_en",
+			CFG_CSR_MST_DEBUG_ENr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sbus_command_sel",
+			CFG_CSR_SBUS_COMMAND_SELr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_sbus_command_sel_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"soc_rd_time_out_thresh",
+			CFG_CSR_SOC_RD_TIME_OUT_THRESHr,
+			CFG,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x02c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_soc_rd_time_out_thresh_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"big_little_byte_order",
+			CFG_CSR_BIG_LITTLE_BYTE_ORDERr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_big_little_byte_order_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ecc_bypass_read",
+			CFG_CSR_ECC_BYPASS_READr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_ecc_bypass_read_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ahb_async_wr_fifo_afull_gap",
+			CFG_CSR_AHB_ASYNC_WR_FIFO_AFULL_GAPr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_ahb_async_wr_fifo_afull_gap_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ahb_async_rd_fifo_afull_gap",
+			CFG_CSR_AHB_ASYNC_RD_FIFO_AFULL_GAPr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x03c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_ahb_async_rd_fifo_afull_gap_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ahb_async_cpl_fifo_afull_gap",
+			CFG_CSR_AHB_ASYNC_CPL_FIFO_AFULL_GAPr,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_ahb_async_cpl_fifo_afull_gap_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data0_high26",
+			CFG_CSR_MST_DEBUG_DATA0_HIGH26r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data0_high26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data0_low32",
+			CFG_CSR_MST_DEBUG_DATA0_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data0_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data1_high26",
+			CFG_CSR_MST_DEBUG_DATA1_HIGH26r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data1_high26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data1_low32",
+			CFG_CSR_MST_DEBUG_DATA1_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x08c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data1_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data2_high26",
+			CFG_CSR_MST_DEBUG_DATA2_HIGH26r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data2_high26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data2_low32",
+			CFG_CSR_MST_DEBUG_DATA2_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data2_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data3_high26",
+			CFG_CSR_MST_DEBUG_DATA3_HIGH26r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x098,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data3_high26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data3_low32",
+			CFG_CSR_MST_DEBUG_DATA3_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x09c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data3_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data4_high26",
+			CFG_CSR_MST_DEBUG_DATA4_HIGH26r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data4_high26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data4_low32",
+			CFG_CSR_MST_DEBUG_DATA4_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data4_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data5_high26",
+			CFG_CSR_MST_DEBUG_DATA5_HIGH26r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data5_high26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data5_low32",
+			CFG_CSR_MST_DEBUG_DATA5_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data5_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data6_high26",
+			CFG_CSR_MST_DEBUG_DATA6_HIGH26r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data6_high26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data6_low32",
+			CFG_CSR_MST_DEBUG_DATA6_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data6_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data7_high26",
+			CFG_CSR_MST_DEBUG_DATA7_HIGH26r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data7_high26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data7_low32",
+			CFG_CSR_MST_DEBUG_DATA7_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data7_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data8_high26",
+			CFG_CSR_MST_DEBUG_DATA8_HIGH26r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data8_high26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data8_low32",
+			CFG_CSR_MST_DEBUG_DATA8_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data8_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data9_high26",
+			CFG_CSR_MST_DEBUG_DATA9_HIGH26r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data9_high26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data9_low32",
+			CFG_CSR_MST_DEBUG_DATA9_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data9_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data10_high26",
+			CFG_CSR_MST_DEBUG_DATA10_HIGH26r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data10_high26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data10_low32",
+			CFG_CSR_MST_DEBUG_DATA10_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data10_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data11_high26",
+			CFG_CSR_MST_DEBUG_DATA11_HIGH26r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data11_high26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data11_low32",
+			CFG_CSR_MST_DEBUG_DATA11_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data11_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data12_high26",
+			CFG_CSR_MST_DEBUG_DATA12_HIGH26r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data12_high26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data12_low32",
+			CFG_CSR_MST_DEBUG_DATA12_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data12_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data13_high26",
+			CFG_CSR_MST_DEBUG_DATA13_HIGH26r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data13_high26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data13_low32",
+			CFG_CSR_MST_DEBUG_DATA13_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data13_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data14_high26",
+			CFG_CSR_MST_DEBUG_DATA14_HIGH26r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data14_high26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data14_low32",
+			CFG_CSR_MST_DEBUG_DATA14_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data14_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data15_high26",
+			CFG_CSR_MST_DEBUG_DATA15_HIGH26r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data15_high26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mst_debug_data15_low32",
+			CFG_CSR_MST_DEBUG_DATA15_LOW32r,
+			CFG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_CFG_BASE_ADDR + MODULE_CFG_CSR_BASE_ADDR + 0x0fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_cfg_csr_mst_debug_data15_low32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_access_states",
+			NPPU_MR_CFG_IND_ACCESS_STATESr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_ind_access_states_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_access_cmd0",
+			NPPU_MR_CFG_IND_ACCESS_CMD0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_nppu_mr_cfg_ind_access_cmd0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_access_data0",
+			NPPU_MR_CFG_IND_ACCESS_DATA0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_ind_access_data0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_access_data1",
+			NPPU_MR_CFG_IND_ACCESS_DATA1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_ind_access_data1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_access_cmd1",
+			NPPU_MR_CFG_IND_ACCESS_CMD1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_ind_access_cmd1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_init_done",
+			NPPU_MR_CFG_MR_INIT_DONEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_init_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_mode_reg",
+			NPPU_MR_CFG_CNT_MODE_REGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_mr_cfg_cnt_mode_reg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ecc_bypass_read",
+			NPPU_MR_CFG_CFG_ECC_BYPASS_READr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_cfg_ecc_bypass_read_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_rep_mod",
+			NPPU_MR_CFG_CFG_REP_MODr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_cfg_rep_mod_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"block_ptr_fifo_aful_th",
+			NPPU_MR_CFG_BLOCK_PTR_FIFO_AFUL_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x002c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_mr_cfg_block_ptr_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pre_rcv_ptr_fifo_aful_th",
+			NPPU_MR_CFG_PRE_RCV_PTR_FIFO_AFUL_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_mr_cfg_pre_rcv_ptr_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mgid_fifo_aful_th",
+			NPPU_MR_CFG_MGID_FIFO_AFUL_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_mr_cfg_mgid_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rep_cmd_fifo_aful_th",
+			NPPU_MR_CFG_REP_CMD_FIFO_AFUL_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_mr_cfg_rep_cmd_fifo_aful_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_int_mask_1",
+			NPPU_MR_CFG_MR_INT_MASK_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x00c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			20,
+			g_nppu_mr_cfg_mr_int_mask_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_int_mask_2",
+			NPPU_MR_CFG_MR_INT_MASK_2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x00c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			20,
+			g_nppu_mr_cfg_mr_int_mask_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_int_mask_3",
+			NPPU_MR_CFG_MR_INT_MASK_3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x00c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			20,
+			g_nppu_mr_cfg_mr_int_mask_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_int_mask_4",
+			NPPU_MR_CFG_MR_INT_MASK_4r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x00cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			25,
+			g_nppu_mr_cfg_mr_int_mask_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_states_1",
+			NPPU_MR_CFG_MR_STATES_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			20,
+			g_nppu_mr_cfg_mr_states_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_states_2",
+			NPPU_MR_CFG_MR_STATES_2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			20,
+			g_nppu_mr_cfg_mr_states_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_states_3",
+			NPPU_MR_CFG_MR_STATES_3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			20,
+			g_nppu_mr_cfg_mr_states_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_states_4",
+			NPPU_MR_CFG_MR_STATES_4r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			25,
+			g_nppu_mr_cfg_mr_states_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_states_5",
+			NPPU_MR_CFG_MR_STATES_5r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			21,
+			g_nppu_mr_cfg_mr_states_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_states_6",
+			NPPU_MR_CFG_MR_STATES_6r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			20,
+			g_nppu_mr_cfg_mr_states_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_states_7",
+			NPPU_MR_CFG_MR_STATES_7r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			22,
+			g_nppu_mr_cfg_mr_states_7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_states_8",
+			NPPU_MR_CFG_MR_STATES_8r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x005c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_states_8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_sop_in_cnt",
+			NPPU_MR_CFG_MR_SOP_IN_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_sop_in_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_eop_in_cnt",
+			NPPU_MR_CFG_MR_EOP_IN_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_eop_in_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_sop_out_cnt",
+			NPPU_MR_CFG_MR_SOP_OUT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_sop_out_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_eop_out_cnt",
+			NPPU_MR_CFG_MR_EOP_OUT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x006c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_eop_out_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos0_in_cnt",
+			NPPU_MR_CFG_MR_COS0_IN_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0070,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos0_in_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos1_in_cnt",
+			NPPU_MR_CFG_MR_COS1_IN_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0074,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos1_in_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos2_in_cnt",
+			NPPU_MR_CFG_MR_COS2_IN_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0078,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos2_in_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos3_in_cnt",
+			NPPU_MR_CFG_MR_COS3_IN_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x007c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos3_in_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos0_out_cnt",
+			NPPU_MR_CFG_MR_COS0_OUT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos0_out_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos1_out_cnt",
+			NPPU_MR_CFG_MR_COS1_OUT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos1_out_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos2_out_cnt",
+			NPPU_MR_CFG_MR_COS2_OUT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos2_out_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos3_out_cnt",
+			NPPU_MR_CFG_MR_COS3_OUT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x008c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos3_out_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_err_in_cnt",
+			NPPU_MR_CFG_MR_ERR_IN_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_err_in_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos0_sop_in_cnt",
+			NPPU_MR_CFG_MR_COS0_SOP_IN_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0140,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos0_sop_in_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos0_eop_in_cnt",
+			NPPU_MR_CFG_MR_COS0_EOP_IN_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0144,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos0_eop_in_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos1_sop_in_cnt",
+			NPPU_MR_CFG_MR_COS1_SOP_IN_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0148,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos1_sop_in_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos1_eop_in_cnt",
+			NPPU_MR_CFG_MR_COS1_EOP_IN_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x014c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos1_eop_in_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos2_sop_in_cnt",
+			NPPU_MR_CFG_MR_COS2_SOP_IN_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0150,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos2_sop_in_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos2_eop_in_cnt",
+			NPPU_MR_CFG_MR_COS2_EOP_IN_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0154,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos2_eop_in_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos3_sop_in_cnt",
+			NPPU_MR_CFG_MR_COS3_SOP_IN_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0158,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos3_sop_in_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos3_eop_in_cnt",
+			NPPU_MR_CFG_MR_COS3_EOP_IN_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x015c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos3_eop_in_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos0_in_err_cnt",
+			NPPU_MR_CFG_MR_COS0_IN_ERR_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0160,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos0_in_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos1_in_err_cnt",
+			NPPU_MR_CFG_MR_COS1_IN_ERR_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0164,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos1_in_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos2_in_err_cnt",
+			NPPU_MR_CFG_MR_COS2_IN_ERR_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0168,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos2_in_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos3_in_err_cnt",
+			NPPU_MR_CFG_MR_COS3_IN_ERR_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x016c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos3_in_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos0_sop_out_cnt",
+			NPPU_MR_CFG_MR_COS0_SOP_OUT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0170,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos0_sop_out_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos0_eop_out_cnt",
+			NPPU_MR_CFG_MR_COS0_EOP_OUT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0174,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos0_eop_out_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos1_sop_out_cnt",
+			NPPU_MR_CFG_MR_COS1_SOP_OUT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0178,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos1_sop_out_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos1_eop_out_cnt",
+			NPPU_MR_CFG_MR_COS1_EOP_OUT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x017c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos1_eop_out_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos2_sop_out_cnt",
+			NPPU_MR_CFG_MR_COS2_SOP_OUT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0180,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos2_sop_out_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos2_eop_out_cnt",
+			NPPU_MR_CFG_MR_COS2_EOP_OUT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0184,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos2_eop_out_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos3_sop_out_cnt",
+			NPPU_MR_CFG_MR_COS3_SOP_OUT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0188,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos3_sop_out_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_cos3_eop_out_cnt",
+			NPPU_MR_CFG_MR_COS3_EOP_OUT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x018c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_cos3_eop_out_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_mlt_unvld_cnt",
+			NPPU_MR_CFG_MR_MLT_UNVLD_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0190,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_mlt_unvld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_sop_eop_match_cfg",
+			NPPU_MR_CFG_MR_SOP_EOP_MATCH_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0100,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_mr_cfg_mr_sop_eop_match_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mr_mlt_unvld_mgid",
+			NPPU_MR_CFG_MR_MLT_UNVLD_MGIDr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_MR_CFG_BASE_ADDR + 0x0108,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_mr_cfg_mr_mlt_unvld_mgid_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isch_fifo_th_1",
+			NPPU_PKTRX_CFG_ISCH_FIFO_TH_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0078,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pktrx_cfg_isch_fifo_th_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isch_fifo_th_2",
+			NPPU_PKTRX_CFG_ISCH_FIFO_TH_2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x007c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pktrx_cfg_isch_fifo_th_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isch_fifo_th_3",
+			NPPU_PKTRX_CFG_ISCH_FIFO_TH_3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pktrx_cfg_isch_fifo_th_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isch_fifo_th_4",
+			NPPU_PKTRX_CFG_ISCH_FIFO_TH_4r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pktrx_cfg_isch_fifo_th_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isch_cfg_0",
+			NPPU_PKTRX_CFG_ISCH_CFG_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_isch_cfg_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hdu_ex_tpid_0",
+			NPPU_PKTRX_CFG_HDU_EX_TPID_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_pktrx_cfg_hdu_ex_tpid_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hdu_ex_tpid_1",
+			NPPU_PKTRX_CFG_HDU_EX_TPID_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_pktrx_cfg_hdu_ex_tpid_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hdu_int_tpid_0",
+			NPPU_PKTRX_CFG_HDU_INT_TPID_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0098,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_pktrx_cfg_hdu_int_tpid_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hdu_int_tpid_1",
+			NPPU_PKTRX_CFG_HDU_INT_TPID_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x009c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_pktrx_cfg_hdu_int_tpid_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hdu_hdlc_0",
+			NPPU_PKTRX_CFG_HDU_HDLC_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_pktrx_cfg_hdu_hdlc_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hdu_hdlc_1",
+			NPPU_PKTRX_CFG_HDU_HDLC_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_pktrx_cfg_hdu_hdlc_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hdu_udf_l3type_0",
+			NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_pktrx_cfg_hdu_udf_l3type_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hdu_udf_l3type_1",
+			NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_pktrx_cfg_hdu_udf_l3type_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hdu_udf_l3type_2",
+			NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_pktrx_cfg_hdu_udf_l3type_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hdu_udf_l3type_3",
+			NPPU_PKTRX_CFG_HDU_UDF_L3TYPE_3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_pktrx_cfg_hdu_udf_l3type_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hdu_udf_l4type_0",
+			NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pktrx_cfg_hdu_udf_l4type_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hdu_udf_l4type_1",
+			NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pktrx_cfg_hdu_udf_l4type_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hdu_udf_l4type_2",
+			NPPU_PKTRX_CFG_HDU_UDF_L4TYPE_2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_nppu_pktrx_cfg_hdu_udf_l4type_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"slot_no_cfg",
+			NPPU_PKTRX_CFG_SLOT_NO_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x00d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_slot_no_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_int_en_0",
+			NPPU_PKTRX_CFG_PKTRX_INT_EN_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0114,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_nppu_pktrx_cfg_pktrx_int_en_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_int_en_1",
+			NPPU_PKTRX_CFG_PKTRX_INT_EN_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0118,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pktrx_cfg_pktrx_int_en_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_int_mask_0",
+			NPPU_PKTRX_CFG_PKTRX_INT_MASK_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x011c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_nppu_pktrx_cfg_pktrx_int_mask_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_int_mask_1",
+			NPPU_PKTRX_CFG_PKTRX_INT_MASK_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0120,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pktrx_cfg_pktrx_int_mask_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_int_status",
+			NPPU_PKTRX_CFG_PKTRX_INT_STATUSr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x0124,
+			(32 / 8),
+			0,
+			35 + 1,
+			0,
+			4,
+			1,
+			g_nppu_pktrx_cfg_pktrx_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_port_rdy0",
+			NPPU_PKTRX_CFG_PKTRX_PORT_RDY0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_pktrx_cfg_pktrx_port_rdy0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_lif0_pfc_rdy0",
+			NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_lif0_pfc_rdy1",
+			NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_lif0_pfc_rdy2",
+			NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_lif0_pfc_rdy3",
+			NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_lif0_pfc_rdy4",
+			NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY4r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_lif0_pfc_rdy5",
+			NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY5r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_lif0_pfc_rdy6",
+			NPPU_PKTRX_CFG_PKTRX_LIF0_PFC_RDY6r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_pktrx_lif0_pfc_rdy6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_port_l2_offset_mode",
+			NPPU_PKTRX_CFG_CFG_PORT_L2_OFFSET_MODEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pktrx_cfg_cfg_port_l2_offset_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_ram_en",
+			NPPU_IDMA_CFG_INT_RAM_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_idma_cfg_int_ram_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_ram_mask",
+			NPPU_IDMA_CFG_INT_RAM_MASKr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_idma_cfg_int_ram_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_ram_status",
+			NPPU_IDMA_CFG_INT_RAM_STATUSr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_idma_cfg_int_ram_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"subsys_int_mask_flag",
+			NPPU_IDMA_CFG_SUBSYS_INT_MASK_FLAGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x180,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_idma_cfg_subsys_int_mask_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"subsys_int_unmask_flag",
+			NPPU_IDMA_CFG_SUBSYS_INT_UNMASK_FLAGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x184,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_idma_cfg_subsys_int_unmask_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_rdclr_mode",
+			NPPU_IDMA_CFG_DEBUG_CNT_RDCLR_MODEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_IDMA_CFG_BASE_ADDR + 0x4f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_idma_cfg_debug_cnt_rdclr_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_ram_en0",
+			NPPU_PBU_CFG_INT_RAM_EN0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_nppu_pbu_cfg_int_ram_en0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_ram_mask0",
+			NPPU_PBU_CFG_INT_RAM_MASK0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_nppu_pbu_cfg_int_ram_mask0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_ram_status0",
+			NPPU_PBU_CFG_INT_RAM_STATUS0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_nppu_pbu_cfg_int_ram_status0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_fifo_en0",
+			NPPU_PBU_CFG_INT_FIFO_EN0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x0c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_nppu_pbu_cfg_int_fifo_en0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_fifo_en1",
+			NPPU_PBU_CFG_INT_FIFO_EN1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x0c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pbu_cfg_int_fifo_en1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_fifo_mask0",
+			NPPU_PBU_CFG_INT_FIFO_MASK0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x100,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_nppu_pbu_cfg_int_fifo_mask0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_fifo_mask1",
+			NPPU_PBU_CFG_INT_FIFO_MASK1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x104,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pbu_cfg_int_fifo_mask1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_fifo_status0",
+			NPPU_PBU_CFG_INT_FIFO_STATUS0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x140,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_nppu_pbu_cfg_int_fifo_status0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_fifo_status1",
+			NPPU_PBU_CFG_INT_FIFO_STATUS1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x144,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pbu_cfg_int_fifo_status1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"subsys_int_mask_flag",
+			NPPU_PBU_CFG_SUBSYS_INT_MASK_FLAGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x180,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_subsys_int_mask_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"subsys_int_unmask_flag",
+			NPPU_PBU_CFG_SUBSYS_INT_UNMASK_FLAGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x184,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_subsys_int_unmask_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sa_ip_en",
+			NPPU_PBU_CFG_SA_IP_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_sa_ip_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_rdclr_mode",
+			NPPU_PBU_CFG_DEBUG_CNT_RDCLR_MODEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x4f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_debug_cnt_rdclr_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fptr_fifo_aful_assert_cfg",
+			NPPU_PBU_CFG_FPTR_FIFO_AFUL_ASSERT_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x50c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_fptr_fifo_aful_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fptr_fifo_aful_negate_cfg",
+			NPPU_PBU_CFG_FPTR_FIFO_AFUL_NEGATE_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x510,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_fptr_fifo_aful_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pf_fifo_aful_assert_cfg",
+			NPPU_PBU_CFG_PF_FIFO_AFUL_ASSERT_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x514,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_pf_fifo_aful_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pf_fifo_aful_negate_cfg",
+			NPPU_PBU_CFG_PF_FIFO_AFUL_NEGATE_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x518,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_pf_fifo_aful_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pf_fifo_aept_assert_cfg",
+			NPPU_PBU_CFG_PF_FIFO_AEPT_ASSERT_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x51c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_pf_fifo_aept_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pf_fifo_aept_negate_cfg",
+			NPPU_PBU_CFG_PF_FIFO_AEPT_NEGATE_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x520,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_pf_fifo_aept_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"wb_aful_assert_cfg",
+			NPPU_PBU_CFG_WB_AFUL_ASSERT_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x524,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_wb_aful_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"wb_aful_negate_cfg",
+			NPPU_PBU_CFG_WB_AFUL_NEGATE_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x528,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_wb_aful_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_key_aful_assert_cfg",
+			NPPU_PBU_CFG_SE_KEY_AFUL_ASSERT_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x52c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_se_key_aful_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ifbrd_se_aful_assert_cfg",
+			NPPU_PBU_CFG_IFBRD_SE_AFUL_ASSERT_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x534,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_ifbrd_se_aful_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ifbrd_se_aful_negate_cfg",
+			NPPU_PBU_CFG_IFBRD_SE_AFUL_NEGATE_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x538,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_ifbrd_se_aful_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ifbrd_odma_aful_assert_cfg",
+			NPPU_PBU_CFG_IFBRD_ODMA_AFUL_ASSERT_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x53c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_ifbrd_odma_aful_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ifbrd_odma_aful_negate_cfg",
+			NPPU_PBU_CFG_IFBRD_ODMA_AFUL_NEGATE_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x540,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_ifbrd_odma_aful_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ifbrd_ppu_aful_assert_cfg",
+			NPPU_PBU_CFG_IFBRD_PPU_AFUL_ASSERT_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x544,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_ifbrd_ppu_aful_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ifbrd_ppu_aful_negate_cfg",
+			NPPU_PBU_CFG_IFBRD_PPU_AFUL_NEGATE_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x548,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_ifbrd_ppu_aful_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mc_logic_aful_assert_cfg",
+			NPPU_PBU_CFG_MC_LOGIC_AFUL_ASSERT_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x54c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_mc_logic_aful_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mc_logic_aful_negate_cfg",
+			NPPU_PBU_CFG_MC_LOGIC_AFUL_NEGATE_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x550,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_mc_logic_aful_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mc_logic_diff",
+			NPPU_PBU_CFG_MC_LOGIC_DIFFr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x5e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_mc_logic_diff_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_peak_port_cnt_clr",
+			NPPU_PBU_CFG_CFG_PEAK_PORT_CNT_CLRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x0600,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_nppu_pbu_cfg_cfg_peak_port_cnt_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"all_ftm_crdt_th",
+			NPPU_PBU_CFG_ALL_FTM_CRDT_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x0640,
+			(32 / 8),
+			0,
+			47 + 1,
+			0,
+			4,
+			2,
+			g_nppu_pbu_cfg_all_ftm_crdt_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"all_ftm_link_th_01",
+			NPPU_PBU_CFG_ALL_FTM_LINK_TH_01r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x700,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_pbu_cfg_all_ftm_link_th_01_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"all_ftm_link_th_23",
+			NPPU_PBU_CFG_ALL_FTM_LINK_TH_23r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x704,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_pbu_cfg_all_ftm_link_th_23_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"all_ftm_link_th_45",
+			NPPU_PBU_CFG_ALL_FTM_LINK_TH_45r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x708,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_pbu_cfg_all_ftm_link_th_45_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"all_ftm_link_th_6",
+			NPPU_PBU_CFG_ALL_FTM_LINK_TH_6r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x70c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_all_ftm_link_th_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"all_ftm_total_congest_th",
+			NPPU_PBU_CFG_ALL_FTM_TOTAL_CONGEST_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x710,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_all_ftm_total_congest_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_crdt_mode",
+			NPPU_PBU_CFG_CFG_CRDT_MODEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x720,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_cfg_crdt_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_pfc_rdy_high_time",
+			NPPU_PBU_CFG_CFG_PFC_RDY_HIGH_TIMEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x728,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_cfg_pfc_rdy_high_time_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_pfc_rdy_low_time",
+			NPPU_PBU_CFG_CFG_PFC_RDY_LOW_TIMEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_CFG_BASE_ADDR + 0x72c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_cfg_cfg_pfc_rdy_low_time_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_fc_rdy",
+			NPPU_PBU_STAT_PBU_FC_RDYr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x580,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_pbu_stat_pbu_fc_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_lif_group0_rdy0",
+			NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x5c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_nppu_pbu_stat_pbu_lif_group0_rdy0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_lif_group0_rdy1",
+			NPPU_PBU_STAT_PBU_LIF_GROUP0_RDY1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x5c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_pbu_lif_group0_rdy1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_lif_group1_rdy",
+			NPPU_PBU_STAT_PBU_LIF_GROUP1_RDYr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x5e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_pbu_lif_group1_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_lif_group0_pfc_rdy",
+			NPPU_PBU_STAT_PBU_LIF_GROUP0_PFC_RDYr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x0600,
+			(32 / 8),
+			0,
+			11 + 1,
+			0,
+			4,
+			1,
+			g_nppu_pbu_stat_pbu_lif_group0_pfc_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_lif_group1_pfc_rdy",
+			NPPU_PBU_STAT_PBU_LIF_GROUP1_PFC_RDYr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x0640,
+			(32 / 8),
+			0,
+			1 + 1,
+			0,
+			4,
+			1,
+			g_nppu_pbu_stat_pbu_lif_group1_pfc_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_sa_port_rdy_0_31",
+			NPPU_PBU_STAT_PBU_SA_PORT_RDY_0_31r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x680,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_pbu_sa_port_rdy_0_31_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_sa_port_rdy_32_50",
+			NPPU_PBU_STAT_PBU_SA_PORT_RDY_32_50r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x684,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_pbu_sa_port_rdy_32_50_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_pktrx_mr_pfc_rdy",
+			NPPU_PBU_STAT_PBU_PKTRX_MR_PFC_RDYr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_pbu_pktrx_mr_pfc_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ftm_crdt_port_rdy_0_31",
+			NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_0_31r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_0_31_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ftm_crdt_port_rdy_32_47",
+			NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_RDY_32_47r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_pbu_ftm_crdt_port_rdy_32_47_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ftm_crdt_port_cng_rdy_0_31",
+			NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_0_31r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_0_31_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ftm_crdt_port_cng_rdy_32_47",
+			NPPU_PBU_STAT_PBU_FTM_CRDT_PORT_CNG_RDY_32_47r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_pbu_ftm_crdt_port_cng_rdy_32_47_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ftm_crdt_sys_info",
+			NPPU_PBU_STAT_PBU_FTM_CRDT_SYS_INFOr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_PBU_STAT_BASE_ADDR + 0x6b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_pbu_stat_pbu_ftm_crdt_sys_info_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"weight_normal_mc",
+			NPPU_ISU_CFG_WEIGHT_NORMAL_MCr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_weight_normal_mc_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"weight_sa_mc",
+			NPPU_ISU_CFG_WEIGHT_SA_MCr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_weight_sa_mc_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"weight_etm",
+			NPPU_ISU_CFG_WEIGHT_ETMr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_weight_etm_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"weight_lp_mc",
+			NPPU_ISU_CFG_WEIGHT_LP_MCr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_weight_lp_mc_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"weight_oam",
+			NPPU_ISU_CFG_WEIGHT_OAMr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_weight_oam_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"weight_lif_ctrl1",
+			NPPU_ISU_CFG_WEIGHT_LIF_CTRL1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_weight_lif_ctrl1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"weight_lif_ctrl2",
+			NPPU_ISU_CFG_WEIGHT_LIF_CTRL2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_weight_lif_ctrl2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ecc_bypass_read",
+			NPPU_ISU_CFG_ECC_BYPASS_READr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_ecc_bypass_read_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_int_mask",
+			NPPU_ISU_CFG_ISU_INT_MASKr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_isu_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_crdt_cycle",
+			NPPU_ISU_CFG_CFG_CRDT_CYCLEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x002c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_cfg_crdt_cycle_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_crdt_value",
+			NPPU_ISU_CFG_CFG_CRDT_VALUEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_cfg_crdt_value_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_int_en",
+			NPPU_ISU_CFG_ISU_INT_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_isu_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_ppu_fifo_fc",
+			NPPU_ISU_CFG_ISU_PPU_FIFO_FCr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_isu_ppu_fifo_fc_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_int_status",
+			NPPU_ISU_CFG_ISU_INT_STATUSr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x003c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			27,
+			g_nppu_isu_cfg_isu_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fd_prog_full_assert_cfg",
+			NPPU_ISU_CFG_FD_PROG_FULL_ASSERT_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_fd_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fd_prog_full_negate_cfg",
+			NPPU_ISU_CFG_FD_PROG_FULL_NEGATE_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_fd_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lp_prog_full_assert_cfg",
+			NPPU_ISU_CFG_LP_PROG_FULL_ASSERT_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x0048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_lp_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lp_prog_full_negate_cfg",
+			NPPU_ISU_CFG_LP_PROG_FULL_NEGATE_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_CFG_BASE_ADDR + 0x004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_cfg_lp_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat0",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat1",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat2",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat3",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat4",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT4r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat5",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT5r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat6",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT6r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat7",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT7r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat8",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT8r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x002c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat9",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT9r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat10",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT10r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat11",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT11r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat12",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT12r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x003c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat13",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT13r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat14",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT14r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat15",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT15r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat16",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT16r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat17",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT17r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat18",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT18r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_dat19",
+			NPPU_ISU_STAT_DEBUG_CNT_DAT19r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_isu_stat_debug_cnt_dat19_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_cfg",
+			NPPU_ISU_STAT_DEBUG_CNT_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ISU_STAT_BASE_ADDR + 0x0100,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_nppu_isu_stat_debug_cnt_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"exsa_tdm_offset",
+			NPPU_ODMA_CFG_EXSA_TDM_OFFSETr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_exsa_tdm_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ecc_bypass_readt",
+			NPPU_ODMA_CFG_ECC_BYPASS_READTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_ecc_bypass_readt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_int_en_0",
+			NPPU_ODMA_CFG_ODMA_INT_EN_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			11,
+			g_nppu_odma_cfg_odma_int_en_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_int_en_1",
+			NPPU_ODMA_CFG_ODMA_INT_EN_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			23,
+			g_nppu_odma_cfg_odma_int_en_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_int_en_2",
+			NPPU_ODMA_CFG_ODMA_INT_EN_2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			10,
+			g_nppu_odma_cfg_odma_int_en_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_int_en_3",
+			NPPU_ODMA_CFG_ODMA_INT_EN_3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x002c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			13,
+			g_nppu_odma_cfg_odma_int_en_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_int_mask_0",
+			NPPU_ODMA_CFG_ODMA_INT_MASK_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			11,
+			g_nppu_odma_cfg_odma_int_mask_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_int_mask_1",
+			NPPU_ODMA_CFG_ODMA_INT_MASK_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			24,
+			g_nppu_odma_cfg_odma_int_mask_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_int_mask_2",
+			NPPU_ODMA_CFG_ODMA_INT_MASK_2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			10,
+			g_nppu_odma_cfg_odma_int_mask_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_int_mask_3",
+			NPPU_ODMA_CFG_ODMA_INT_MASK_3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x003c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			13,
+			g_nppu_odma_cfg_odma_int_mask_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_int_status_0",
+			NPPU_ODMA_CFG_ODMA_INT_STATUS_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			11,
+			g_nppu_odma_cfg_odma_int_status_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_int_status_1",
+			NPPU_ODMA_CFG_ODMA_INT_STATUS_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			23,
+			g_nppu_odma_cfg_odma_int_status_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_int_status_2",
+			NPPU_ODMA_CFG_ODMA_INT_STATUS_2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			10,
+			g_nppu_odma_cfg_odma_int_status_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_int_status_3",
+			NPPU_ODMA_CFG_ODMA_INT_STATUS_3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			15,
+			g_nppu_odma_cfg_odma_int_status_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sp_tdm_err_nor_cfg",
+			NPPU_ODMA_CFG_SP_TDM_ERR_NOR_CFGr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_sp_tdm_err_nor_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_dis_ptr_prog_full_cfg_a",
+			NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_dis_ptr_prog_full_cfg_n",
+			NPPU_ODMA_CFG_ETM_DIS_PTR_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x006c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_etm_dis_ptr_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ftm_dis_ptr_prog_full_cfg_a",
+			NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0070,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ftm_dis_ptr_prog_full_cfg_n",
+			NPPU_ODMA_CFG_FTM_DIS_PTR_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0074,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_ftm_dis_ptr_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_dis_fifo_prog_full_cfg_a",
+			NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0078,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_dis_fifo_prog_full_cfg_n",
+			NPPU_ODMA_CFG_TM_DIS_FIFO_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x007c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_tm_dis_fifo_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"err_prog_full_cfg_a",
+			NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_err_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"err_prog_full_cfg_n",
+			NPPU_ODMA_CFG_ERR_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x008c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_err_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tdmuc_prog_full_cfg_a",
+			NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_tdmuc_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tdmuc_prog_full_cfg_n",
+			NPPU_ODMA_CFG_TDMUC_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_tdmuc_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tdmmc_groupid_prog_full_cfg_a",
+			NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0098,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tdmmc_groupid_prog_full_cfg_n",
+			NPPU_ODMA_CFG_TDMMC_GROUPID_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x009c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_tdmmc_groupid_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tdmmc_no_bitmap_prog_full_cfg_a",
+			NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tdmmc_no_bitmap_prog_full_cfg_n",
+			NPPU_ODMA_CFG_TDMMC_NO_BITMAP_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_tdmmc_no_bitmap_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tdmmc_prog_full_cfg_a",
+			NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_tdmmc_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tdmmc_prog_full_cfg_n",
+			NPPU_ODMA_CFG_TDMMC_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_tdmmc_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"desc_prog_full_cfg_a",
+			NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_desc_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"desc_prog_full_cfg_n",
+			NPPU_ODMA_CFG_DESC_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_desc_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dly_prog_full_cfg_a",
+			NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_dly_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dly_prog_full_cfg_n",
+			NPPU_ODMA_CFG_DLY_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_dly_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp_prog_full_cfg_a",
+			NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_rsp_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp_prog_full_cfg_n",
+			NPPU_ODMA_CFG_RSP_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_rsp_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"nor_prog_full_cfg_a",
+			NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_nor_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"nor_prog_full_cfg_n",
+			NPPU_ODMA_CFG_NOR_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_nor_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_nor_prog_full_cfg_a",
+			NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_etm_nor_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_nor_prog_full_cfg_n",
+			NPPU_ODMA_CFG_ETM_NOR_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_etm_nor_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ftm_nor_prog_full_cfg_a",
+			NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_ftm_nor_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ftm_nor_prog_full_cfg_n",
+			NPPU_ODMA_CFG_FTM_NOR_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_ftm_nor_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_prog_full_cfg_a",
+			NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_etm_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_prog_full_cfg_n",
+			NPPU_ODMA_CFG_ETM_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_etm_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ftm_prog_full_cfg_a",
+			NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_ftm_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ftm_prog_full_cfg_n",
+			NPPU_ODMA_CFG_FTM_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_ftm_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_nrdcnt_prog_full_cfg_a",
+			NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_nrdcnt_prog_full_cfg_n",
+			NPPU_ODMA_CFG_ETM_NRDCNT_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_etm_nrdcnt_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ftm_nrdcnt_prog_full_cfg_a",
+			NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ftm_nrdcnt_prog_full_cfg_n",
+			NPPU_ODMA_CFG_FTM_NRDCNT_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x00fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_ftm_nrdcnt_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_prog_full_cfg_a",
+			NPPU_ODMA_CFG_PP_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0104,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_pp_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_prog_full_cfg_n",
+			NPPU_ODMA_CFG_PP_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0108,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_pp_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_weight",
+			NPPU_ODMA_CFG_TM_WEIGHTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x010c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_tm_weight_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp_weight",
+			NPPU_ODMA_CFG_PP_WEIGHTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0110,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_pp_weight_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ifbcmd_prog_full_cfg_a",
+			NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0218,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_ifbcmd_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ifbcmd_prog_full_cfg_n",
+			NPPU_ODMA_CFG_IFBCMD_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x021c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_ifbcmd_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mccnt_prog_full_cfg_a",
+			NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0220,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_mccnt_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mccnt_prog_full_cfg_n",
+			NPPU_ODMA_CFG_MCCNT_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0224,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_mccnt_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_or_pon",
+			NPPU_ODMA_CFG_INT_OR_PONr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x228,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_int_or_pon_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"quemng_cnt_in_err_cnt",
+			NPPU_ODMA_CFG_QUEMNG_CNT_IN_ERR_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x22c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_quemng_cnt_in_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lif0_port_eop_cnt",
+			NPPU_ODMA_CFG_LIF0_PORT_EOP_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x240,
+			(32 / 8),
+			0,
+			47 + 1,
+			0,
+			4,
+			1,
+			g_nppu_odma_cfg_lif0_port_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lif1_port_eop_cnt",
+			NPPU_ODMA_CFG_LIF1_PORT_EOP_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x300,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			4,
+			1,
+			g_nppu_odma_cfg_lif1_port_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lifc_port0_eop_cnt",
+			NPPU_ODMA_CFG_LIFC_PORT0_EOP_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x320,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_lifc_port0_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lifc_port1_eop_cnt",
+			NPPU_ODMA_CFG_LIFC_PORT1_EOP_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x324,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_lifc_port1_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fptr_fifo_prog_ept_cfg_n",
+			NPPU_ODMA_CFG_FPTR_FIFO_PROG_EPT_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0404,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_fptr_fifo_prog_ept_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_fifo_prog_full_cfg_a",
+			NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_Ar,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x0408,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_isu_fifo_prog_full_cfg_a_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_fifo_prog_full_cfg_n",
+			NPPU_ODMA_CFG_ISU_FIFO_PROG_FULL_CFG_Nr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_ODMA_CFG_BASE_ADDR + 0x040c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_odma_cfg_isu_fifo_prog_full_cfg_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_access_done",
+			NPPU_OAM_CFG_IND_ACCESS_DONEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_access_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_access_command",
+			NPPU_OAM_CFG_IND_ACCESS_COMMANDr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_nppu_oam_cfg_ind_access_command_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat0",
+			NPPU_OAM_CFG_IND_DAT0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_dat0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat1",
+			NPPU_OAM_CFG_IND_DAT1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_dat1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat2",
+			NPPU_OAM_CFG_IND_DAT2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_dat2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat3",
+			NPPU_OAM_CFG_IND_DAT3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_dat3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_tx_main_en",
+			NPPU_OAM_CFG_OAM_TX_MAIN_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_oam_tx_main_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tx_total_num",
+			NPPU_OAM_CFG_TX_TOTAL_NUMr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_tx_total_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_chk_main_en",
+			NPPU_OAM_CFG_OAM_CHK_MAIN_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_oam_chk_main_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"chk_total_num0",
+			NPPU_OAM_CFG_CHK_TOTAL_NUM0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_chk_total_num0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ma_chk_main_en",
+			NPPU_OAM_CFG_MA_CHK_MAIN_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ma_chk_main_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"chk_total_num1",
+			NPPU_OAM_CFG_CHK_TOTAL_NUM1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x002c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_chk_total_num1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tx_stat_en",
+			NPPU_OAM_CFG_TX_STAT_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_tx_stat_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rec_stat_en",
+			NPPU_OAM_CFG_REC_STAT_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_rec_stat_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_oam_rdy_mask",
+			NPPU_OAM_CFG_STAT_OAM_RDY_MASKr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x003c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_stat_oam_rdy_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"session_grading0",
+			NPPU_OAM_CFG_SESSION_GRADING0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_session_grading0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"session_grading1",
+			NPPU_OAM_CFG_SESSION_GRADING1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_session_grading1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"session_grading2",
+			NPPU_OAM_CFG_SESSION_GRADING2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_session_grading2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"session_grading3",
+			NPPU_OAM_CFG_SESSION_GRADING3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_session_grading3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"bfd_chk_haddr",
+			NPPU_OAM_CFG_BFD_CHK_HADDRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_bfd_chk_haddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ethccm_chk_haddr",
+			NPPU_OAM_CFG_ETHCCM_CHK_HADDRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ethccm_chk_haddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tpbfd_chk_haddr",
+			NPPU_OAM_CFG_TPBFD_CHK_HADDRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_tpbfd_chk_haddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tpoam_ccm_chk_haddr",
+			NPPU_OAM_CFG_TPOAM_CCM_CHK_HADDRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x005c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_tpoam_ccm_chk_haddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"bfd_tx_haddr",
+			NPPU_OAM_CFG_BFD_TX_HADDRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_bfd_tx_haddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ethccm_tx_haddr",
+			NPPU_OAM_CFG_ETHCCM_TX_HADDRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ethccm_tx_haddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tpbfd_tx_haddr",
+			NPPU_OAM_CFG_TPBFD_TX_HADDRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_tpbfd_tx_haddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tpoam_ccm_tx_haddr",
+			NPPU_OAM_CFG_TPOAM_CCM_TX_HADDRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x006c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_tpoam_ccm_tx_haddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ethccm_ma_chk_haddr",
+			NPPU_OAM_CFG_ETHCCM_MA_CHK_HADDRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0070,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ethccm_ma_chk_haddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tpccm_ma_chk_haddr",
+			NPPU_OAM_CFG_TPCCM_MA_CHK_HADDRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0074,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_tpccm_ma_chk_haddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"groupnum_ram_clr",
+			NPPU_OAM_CFG_GROUPNUM_RAM_CLRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0078,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_groupnum_ram_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"index_ram0_clr",
+			NPPU_OAM_CFG_INDEX_RAM0_CLRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x007c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_index_ram0_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"index_ram1_clr",
+			NPPU_OAM_CFG_INDEX_RAM1_CLRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_index_ram1_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rmep_ram_clr",
+			NPPU_OAM_CFG_RMEP_RAM_CLRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_rmep_ram_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ma_ram_clr",
+			NPPU_OAM_CFG_MA_RAM_CLRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ma_ram_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ram_init_done",
+			NPPU_OAM_CFG_RAM_INIT_DONEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x008c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ram_init_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rec_bfd_debug_en",
+			NPPU_OAM_CFG_REC_BFD_DEBUG_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_rec_bfd_debug_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_session_int",
+			NPPU_OAM_CFG_OAM_SESSION_INTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0098,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_nppu_oam_cfg_oam_session_int_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pon_int",
+			NPPU_OAM_CFG_PON_INTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x009c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_oam_cfg_pon_int_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_int_clr",
+			NPPU_OAM_CFG_OAM_INT_CLRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_oam_int_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"type_int_clr0",
+			NPPU_OAM_CFG_TYPE_INT_CLR0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_nppu_oam_cfg_type_int_clr0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"type_int_clr1",
+			NPPU_OAM_CFG_TYPE_INT_CLR1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_nppu_oam_cfg_type_int_clr1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"interrupt_mask",
+			NPPU_OAM_CFG_INTERRUPT_MASKr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			8,
+			g_nppu_oam_cfg_interrupt_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int0_index",
+			NPPU_OAM_CFG_INT0_INDEXr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00b0,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_nppu_oam_cfg_int0_index_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int1_index",
+			NPPU_OAM_CFG_INT1_INDEXr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00c0,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_nppu_oam_cfg_int1_index_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int0_index_region",
+			NPPU_OAM_CFG_INT0_INDEX_REGIONr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_int0_index_region_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int1_index_region",
+			NPPU_OAM_CFG_INT1_INDEX_REGIONr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_int1_index_region_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"bdiinfo_fwft_fifo_th",
+			NPPU_OAM_CFG_BDIINFO_FWFT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_bdiinfo_fwft_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"recsec_fwft_fifo_th",
+			NPPU_OAM_CFG_RECSEC_FWFT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_recsec_fwft_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"timing_chk_info0_fwft_fifo_th",
+			NPPU_OAM_CFG_TIMING_CHK_INFO0_FWFT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_timing_chk_info0_fwft_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"recma_fwft_fifo_th",
+			NPPU_OAM_CFG_RECMA_FWFT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_recma_fwft_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"timing_chk_info1_fwft_fifo_th",
+			NPPU_OAM_CFG_TIMING_CHK_INFO1_FWFT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_timing_chk_info1_fwft_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_txinst_fifo_th",
+			NPPU_OAM_CFG_OAM_TXINST_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_oam_txinst_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_rdinfo_fwft_fifo_th",
+			NPPU_OAM_CFG_OAM_RDINFO_FWFT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_oam_rdinfo_fwft_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lm_cnt_fwft_fifo_th",
+			NPPU_OAM_CFG_LM_CNT_FWFT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_lm_cnt_fwft_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_pkt_fifo_th",
+			NPPU_OAM_CFG_OAM_PKT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_oam_pkt_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"reclm_stat_fifo_th",
+			NPPU_OAM_CFG_RECLM_STAT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_reclm_stat_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"txlm_stat_fifo_th",
+			NPPU_OAM_CFG_TXLM_STAT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x00100,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_txlm_stat_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_chk_fwft_fifo_th",
+			NPPU_OAM_CFG_OAM_CHK_FWFT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0104,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_oam_chk_fwft_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"txoam_stat_fifo_th",
+			NPPU_OAM_CFG_TXOAM_STAT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0108,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_txoam_stat_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"recoam_stat_fifo_th",
+			NPPU_OAM_CFG_RECOAM_STAT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x010c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_recoam_stat_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"txpkt_data_fwft_fifo_th",
+			NPPU_OAM_CFG_TXPKT_DATA_FWFT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0110,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_txpkt_data_fwft_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tstpkt_fwft_fifo_th",
+			NPPU_OAM_CFG_TSTPKT_FWFT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0114,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_tstpkt_fwft_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tst_txinst_fwft_fifo_th",
+			NPPU_OAM_CFG_TST_TXINST_FWFT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0118,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_tst_txinst_fwft_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tstrx_main_en",
+			NPPU_OAM_CFG_TSTRX_MAIN_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x011c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_tstrx_main_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsttx_cfg_para_tbl2",
+			NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0120,
+			(32 / 8),
+			0,
+			9 + 1,
+			0,
+			12,
+			8,
+			g_nppu_oam_cfg_tsttx_cfg_para_tbl2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsttx_cfg_para_tbl1",
+			NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0124,
+			(32 / 8),
+			0,
+			9 + 1,
+			0,
+			12,
+			1,
+			g_nppu_oam_cfg_tsttx_cfg_para_tbl1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsttx_cfg_para_tbl0",
+			NPPU_OAM_CFG_TSTTX_CFG_PARA_TBL0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0128,
+			(32 / 8),
+			0,
+			9 + 1,
+			0,
+			12,
+			3,
+			g_nppu_oam_cfg_tsttx_cfg_para_tbl0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tstrx_cfg_para",
+			NPPU_OAM_CFG_TSTRX_CFG_PARAr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0198,
+			(32 / 8),
+			0,
+			0x9 + 1,
+			0,
+			4,
+			2,
+			g_nppu_oam_cfg_tstrx_cfg_para_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fifo_status_int_en_0",
+			NPPU_OAM_CFG_FIFO_STATUS_INT_EN_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x01c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_nppu_oam_cfg_fifo_status_int_en_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fifo_status_int_en_1",
+			NPPU_OAM_CFG_FIFO_STATUS_INT_EN_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x01c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			10,
+			g_nppu_oam_cfg_fifo_status_int_en_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fifo_status_int_mask_0",
+			NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x01c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_nppu_oam_cfg_fifo_status_int_mask_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fifo_status_int_mask_1",
+			NPPU_OAM_CFG_FIFO_STATUS_INT_MASK_1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x01cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			10,
+			g_nppu_oam_cfg_fifo_status_int_mask_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fifo_status_int_status",
+			NPPU_OAM_CFG_FIFO_STATUS_INT_STATUSr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x01d0,
+			(32 / 8),
+			0,
+			39 + 1,
+			0,
+			4,
+			1,
+			g_nppu_oam_cfg_fifo_status_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"main_frequency",
+			NPPU_OAM_CFG_MAIN_FREQUENCYr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0270,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_main_frequency_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_cfg_type",
+			NPPU_OAM_CFG_OAM_CFG_TYPEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0274,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_oam_cfg_type_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fst_swch_eth_head0",
+			NPPU_OAM_CFG_FST_SWCH_ETH_HEAD0r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0278,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_fst_swch_eth_head0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fst_swch_eth_head1",
+			NPPU_OAM_CFG_FST_SWCH_ETH_HEAD1r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x027c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_fst_swch_eth_head1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fst_swch_eth_head2",
+			NPPU_OAM_CFG_FST_SWCH_ETH_HEAD2r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0280,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_fst_swch_eth_head2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fst_swch_eth_head3",
+			NPPU_OAM_CFG_FST_SWCH_ETH_HEAD3r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0284,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_fst_swch_eth_head3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_fs_txinst_fifo_th",
+			NPPU_OAM_CFG_OAM_FS_TXINST_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0288,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_oam_fs_txinst_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_ma_fs_txinst_fifo_th",
+			NPPU_OAM_CFG_OAM_MA_FS_TXINST_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x028c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_oam_ma_fs_txinst_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pon_int_ram_clr",
+			NPPU_OAM_CFG_PON_INT_RAM_CLRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0290,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_pon_int_ram_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pon_p_int_index",
+			NPPU_OAM_CFG_PON_P_INT_INDEXr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0294,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_pon_p_int_index_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pon_protect_pkt_fifo_th",
+			NPPU_OAM_CFG_PON_PROTECT_PKT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0298,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_pon_protect_pkt_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pon_laser_off_en",
+			NPPU_OAM_CFG_PON_LASER_OFF_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x029c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_pon_laser_off_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pon_prtct_pkt_tx_en",
+			NPPU_OAM_CFG_PON_PRTCT_PKT_TX_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_pon_prtct_pkt_tx_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_pon_master",
+			NPPU_OAM_CFG_CFG_PON_MASTERr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_cfg_pon_master_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"level_mode",
+			NPPU_OAM_CFG_LEVEL_MODEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_level_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"interrupt_en",
+			NPPU_OAM_CFG_INTERRUPT_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_interrupt_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pon_laser_on_en",
+			NPPU_OAM_CFG_PON_LASER_ON_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_pon_laser_on_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ti_pon_sd",
+			NPPU_OAM_CFG_TI_PON_SDr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ti_pon_sd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ti_pon_los",
+			NPPU_OAM_CFG_TI_PON_LOSr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ti_pon_los_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat4",
+			NPPU_OAM_CFG_IND_DAT4r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_dat4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat5",
+			NPPU_OAM_CFG_IND_DAT5r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_dat5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat6",
+			NPPU_OAM_CFG_IND_DAT6r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_dat6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat7",
+			NPPU_OAM_CFG_IND_DAT7r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_dat7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat8",
+			NPPU_OAM_CFG_IND_DAT8r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_dat8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat9",
+			NPPU_OAM_CFG_IND_DAT9r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_dat9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat10",
+			NPPU_OAM_CFG_IND_DAT10r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_dat10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat11",
+			NPPU_OAM_CFG_IND_DAT11r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_dat11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat12",
+			NPPU_OAM_CFG_IND_DAT12r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_dat12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat13",
+			NPPU_OAM_CFG_IND_DAT13r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_dat13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat14",
+			NPPU_OAM_CFG_IND_DAT14r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_dat14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ind_dat15",
+			NPPU_OAM_CFG_IND_DAT15r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ind_dat15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_2544_pkt_fifo_th",
+			NPPU_OAM_CFG_OAM_2544_PKT_FIFO_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_oam_2544_pkt_fifo_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"txinfo_ram_clr",
+			NPPU_OAM_CFG_TXINFO_RAM_CLRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_txinfo_ram_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"txinfo_ram_init_done",
+			NPPU_OAM_CFG_TXINFO_RAM_INIT_DONEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_txinfo_ram_init_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fifo_status_int_status40",
+			NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS40r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_fifo_status_int_status40_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"fifo_status_int_status41",
+			NPPU_OAM_CFG_FIFO_STATUS_INT_STATUS41r,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x02fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_fifo_status_int_status41_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_2544_fun_en",
+			NPPU_OAM_CFG_OAM_2544_FUN_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0300,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_oam_2544_fun_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_2544_stat_clr",
+			NPPU_OAM_CFG_OAM_2544_STAT_CLRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0304,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_oam_2544_stat_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"txdis_default",
+			NPPU_OAM_CFG_TXDIS_DEFAULTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0308,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_txdis_default_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"txdis_default_en",
+			NPPU_OAM_CFG_TXDIS_DEFAULT_ENr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x030c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_txdis_default_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tpbfd_firstchk_th",
+			NPPU_OAM_CFG_TPBFD_FIRSTCHK_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0310,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_tpbfd_firstchk_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ethccm_firstchk_th",
+			NPPU_OAM_CFG_ETHCCM_FIRSTCHK_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0314,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_ethccm_firstchk_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tpccm_firstchk_th",
+			NPPU_OAM_CFG_TPCCM_FIRSTCHK_THr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_CFG_BASE_ADDR + 0x0318,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_cfg_tpccm_firstchk_th_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"txstat_req_cnt",
+			NPPU_OAM_STAT_TXSTAT_REQ_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_txstat_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"chkstat_req_cnt",
+			NPPU_OAM_STAT_CHKSTAT_REQ_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_chkstat_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_oam_fc_cnt",
+			NPPU_OAM_STAT_STAT_OAM_FC_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_stat_oam_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"bfdseq_req_cnt",
+			NPPU_OAM_STAT_BFDSEQ_REQ_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_bfdseq_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lmcnt_req_cnt",
+			NPPU_OAM_STAT_LMCNT_REQ_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_lmcnt_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_oam_lm_rsp_cnt",
+			NPPU_OAM_STAT_STAT_OAM_LM_RSP_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_stat_oam_lm_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_oam_lm_fc_cnt",
+			NPPU_OAM_STAT_STAT_OAM_LM_FC_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_stat_oam_lm_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_req_cnt",
+			NPPU_OAM_STAT_SE_REQ_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_se_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_rsp_cnt",
+			NPPU_OAM_STAT_SE_RSP_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_se_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_oam_fc_cnt",
+			NPPU_OAM_STAT_SE_OAM_FC_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_se_oam_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_se_fc_cnt",
+			NPPU_OAM_STAT_OAM_SE_FC_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_oam_se_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_pktrx_sop_cnt",
+			NPPU_OAM_STAT_OAM_PKTRX_SOP_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x002c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_oam_pktrx_sop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_pktrx_eop_cnt",
+			NPPU_OAM_STAT_OAM_PKTRX_EOP_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_oam_pktrx_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_oam_fc_cnt",
+			NPPU_OAM_STAT_PKTRX_OAM_FC_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_pktrx_oam_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_oam_tst_fc_cnt",
+			NPPU_OAM_STAT_PKTRX_OAM_TST_FC_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_pktrx_oam_tst_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_oam_sop_cnt",
+			NPPU_OAM_STAT_ODMA_OAM_SOP_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x003c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_odma_oam_sop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_oam_eop_cnt",
+			NPPU_OAM_STAT_ODMA_OAM_EOP_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_odma_oam_eop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_odma_fc_cnt",
+			NPPU_OAM_STAT_OAM_ODMA_FC_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_oam_odma_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rec_ma_pkt_illegal_cnt",
+			NPPU_OAM_STAT_REC_MA_PKT_ILLEGAL_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_rec_ma_pkt_illegal_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rec_rmep_pkt_illegal_cnt",
+			NPPU_OAM_STAT_REC_RMEP_PKT_ILLEGAL_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_rec_rmep_pkt_illegal_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rec_eth_ais_pkt_cnt",
+			NPPU_OAM_STAT_REC_ETH_AIS_PKT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_rec_eth_ais_pkt_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rec_tp_ais_pkt_cnt",
+			NPPU_OAM_STAT_REC_TP_AIS_PKT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_rec_tp_ais_pkt_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rec_tp_csf_pkt_cnt",
+			NPPU_OAM_STAT_REC_TP_CSF_PKT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_rec_tp_csf_pkt_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rec_eth_level_defect_cnt",
+			NPPU_OAM_STAT_REC_ETH_LEVEL_DEFECT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x005c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_rec_eth_level_defect_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rec_eth_megid_defect_cnt",
+			NPPU_OAM_STAT_REC_ETH_MEGID_DEFECT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_rec_eth_megid_defect_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rec_eth_mepid_defect_cnt",
+			NPPU_OAM_STAT_REC_ETH_MEPID_DEFECT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_rec_eth_mepid_defect_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rec_eth_interval_defect_cnt",
+			NPPU_OAM_STAT_REC_ETH_INTERVAL_DEFECT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_rec_eth_interval_defect_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rec_sess_unenable_cnt",
+			NPPU_OAM_STAT_REC_SESS_UNENABLE_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x006c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_rec_sess_unenable_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_2544_rd_pkt_cnt",
+			NPPU_OAM_STAT_OAM_2544_RD_PKT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0070,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_oam_2544_rd_pkt_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_clr",
+			NPPU_OAM_STAT_DEBUG_CNT_CLRr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0074,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_debug_cnt_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_pktrx_catch_data",
+			NPPU_OAM_STAT_OAM_PKTRX_CATCH_DATAr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0078,
+			(32 / 8),
+			0,
+			0x1F + 1,
+			0,
+			4,
+			1,
+			g_nppu_oam_stat_oam_pktrx_catch_data_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_oam_catch_data",
+			NPPU_OAM_STAT_ODMA_OAM_CATCH_DATAr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x00f8,
+			(32 / 8),
+			0,
+			0x1F + 1,
+			0,
+			4,
+			1,
+			g_nppu_oam_stat_odma_oam_catch_data_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tst_session_tx_cnt",
+			NPPU_OAM_STAT_TST_SESSION_TX_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0178,
+			(32 / 8),
+			0,
+			0x9 + 1,
+			0,
+			4,
+			1,
+			g_nppu_oam_stat_tst_session_tx_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tst_session_rx_cnt",
+			NPPU_OAM_STAT_TST_SESSION_RX_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01a0,
+			(32 / 8),
+			0,
+			0x9 + 1,
+			0,
+			4,
+			1,
+			g_nppu_oam_stat_tst_session_rx_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tstrx_lost_cnt",
+			NPPU_OAM_STAT_TSTRX_LOST_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01c8,
+			(32 / 8),
+			0,
+			0x9 + 1,
+			0,
+			4,
+			1,
+			g_nppu_oam_stat_tstrx_lost_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"bfdseq_wr_cnt",
+			NPPU_OAM_STAT_BFDSEQ_WR_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_bfdseq_wr_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"bfdtime_wr_cnt",
+			NPPU_OAM_STAT_BFDTIME_WR_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_bfdtime_wr_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lmcnt_wr_cnt",
+			NPPU_OAM_STAT_LMCNT_WR_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_lmcnt_wr_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_fs_pkt_cnt",
+			NPPU_OAM_STAT_OAM_FS_PKT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x01fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_oam_fs_pkt_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_ma_fs_pkt_cnt",
+			NPPU_OAM_STAT_OAM_MA_FS_PKT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0200,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_oam_ma_fs_pkt_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rec_tp_level_defect_cnt",
+			NPPU_OAM_STAT_REC_TP_LEVEL_DEFECT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0204,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_rec_tp_level_defect_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rec_tp_megid_defect_cnt",
+			NPPU_OAM_STAT_REC_TP_MEGID_DEFECT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0208,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_rec_tp_megid_defect_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rec_tp_mepid_defect_cnt",
+			NPPU_OAM_STAT_REC_TP_MEPID_DEFECT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x020c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_rec_tp_mepid_defect_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rec_tp_interval_defect_cnt",
+			NPPU_OAM_STAT_REC_TP_INTERVAL_DEFECT_CNTr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0210,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_rec_tp_interval_defect_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rd_reg_clear_mode",
+			NPPU_OAM_STAT_RD_REG_CLEAR_MODEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0214,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_rd_reg_clear_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rd_data_reg_clear_mode",
+			NPPU_OAM_STAT_RD_DATA_REG_CLEAR_MODEr,
+			NPPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_NPPU_BASE_ADDR + MODULE_NPPU_OAM_STAT_BASE_ADDR + 0x0218,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_nppu_oam_stat_rd_data_reg_clear_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_int_status_ram_0",
+			NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM_0r,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x00000000,
+			(32 / 8),
+			0,
+			4095 + 1,
+			0,
+			1,
+			7,
+			g_nppu_oam_cfg_indir_oam_int_status_ram_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_int_status_ram1",
+			NPPU_OAM_CFG_INDIR_OAM_INT_STATUS_RAM1r,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x10000000,
+			(32 / 8),
+			0,
+			4095 + 1,
+			0,
+			1,
+			12,
+			g_nppu_oam_cfg_indir_oam_int_status_ram1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tst_pkt_tx_para_ram",
+			NPPU_OAM_CFG_INDIR_TST_PKT_TX_PARA_RAMr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x20000000,
+			(96 / 8),
+			0,
+			127 + 1,
+			0,
+			1,
+			12,
+			g_nppu_oam_cfg_indir_tst_pkt_tx_para_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"groupnumram",
+			NPPU_OAM_CFG_INDIR_GROUPNUMRAMr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x30000000,
+			(32 / 8),
+			0,
+			4095 + 1,
+			0,
+			1,
+			1,
+			g_nppu_oam_cfg_indir_groupnumram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_tx_tbl_ram",
+			NPPU_OAM_CFG_INDIR_OAM_TX_TBL_RAMr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x40000000,
+			(64 / 8),
+			0,
+			4095 + 1,
+			0,
+			1,
+			8,
+			g_nppu_oam_cfg_indir_oam_tx_tbl_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_chk_tbl_ram",
+			NPPU_OAM_CFG_INDIR_OAM_CHK_TBL_RAMr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x50000000,
+			(64 / 8),
+			0,
+			4095 + 1,
+			0,
+			1,
+			9,
+			g_nppu_oam_cfg_indir_oam_chk_tbl_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_ma_chk_tbl_ram",
+			NPPU_OAM_CFG_INDIR_OAM_MA_CHK_TBL_RAMr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x60000000,
+			(160 / 8),
+			0,
+			4095 + 1,
+			0,
+			1,
+			22,
+			g_nppu_oam_cfg_indir_oam_ma_chk_tbl_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_2544_tx_ram",
+			NPPU_OAM_CFG_INDIR_OAM_2544_TX_RAMr,
+			NPPU,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_UNI_ARRAY,
+			0x90000000,
+			(64 / 8),
+			0,
+			127 + 1,
+			0,
+			1,
+			5,
+			g_nppu_oam_cfg_indir_oam_2544_tx_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"interrupt_en_r",
+			PPU_PPU_INTERRUPT_EN_Rr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_interrupt_en_r_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mec_host_interrupt",
+			PPU_PPU_MEC_HOST_INTERRUPTr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_mec_host_interrupt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_rtl_date",
+			PPU_PPU_DBG_RTL_DATEr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_dbg_rtl_date_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dup_start_num_cfg",
+			PPU_PPU_DUP_START_NUM_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x02c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_dup_start_num_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_data_write_complete",
+			PPU_PPU_DEBUG_DATA_WRITE_COMPLETEr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_debug_data_write_complete_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"uc_mc_wrr_cfg",
+			PPU_PPU_UC_MC_WRR_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_uc_mc_wrr_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_pkt_send_en",
+			PPU_PPU_DEBUG_PKT_SEND_ENr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_debug_pkt_send_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dup_tbl_ind_access_done",
+			PPU_PPU_DUP_TBL_IND_ACCESS_DONEr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x04c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_dup_tbl_ind_access_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_ppu_demux_fifo_interrupt_mask",
+			PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_MASKr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_ppu_ppu_isu_ppu_demux_fifo_interrupt_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_multicast_fifo_interrupt_mask",
+			PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_MASKr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			20,
+			g_ppu_ppu_ppu_multicast_fifo_interrupt_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_in_schedule_fifo_interrupt_mask",
+			PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_MASKr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_ppu_ppu_ppu_in_schedule_fifo_interrupt_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_mf_out_fifo_interrupt_mask",
+			PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_MASKr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x08c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			12,
+			g_ppu_ppu_ppu_mf_out_fifo_interrupt_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_mcode_pf_req_schedule_fifo_interrupt_mask",
+			PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_MASKr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			12,
+			g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_mcode_pf_rsp_schedule_fifo_interrupt_mask",
+			PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_MASKr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_mccnt_fifo_interrupt_mask",
+			PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_MASKr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x098,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_ppu_ppu_ppu_mccnt_fifo_interrupt_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"coprocessor_fifo_interrupt_mask_l",
+			PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x09c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_ppu_ppu_coprocessor_fifo_interrupt_mask_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"coprocessor_fifo_interrupt_mask_m",
+			PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Mr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_ppu_ppu_coprocessor_fifo_interrupt_mask_m_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"coprocessor_fifo_interrupt_mask_h",
+			PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_MASK_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_ppu_ppu_coprocessor_fifo_interrupt_mask_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_ram_check_err_mask",
+			PPU_PPU_PPU_RAM_CHECK_ERR_MASKr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_ram_check_err_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_fifo_interrupt_mask",
+			PPU_PPU_INSTRMEM_FIFO_INTERRUPT_MASKr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			12,
+			g_ppu_ppu_instrmem_fifo_interrupt_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_ppu_demux_fifo_interrupt_sta",
+			PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_STAr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xc0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_ppu_ppu_isu_ppu_demux_fifo_interrupt_sta_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_multicast_fifo_interrupt_sta",
+			PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_STAr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			20,
+			g_ppu_ppu_ppu_multicast_fifo_interrupt_sta_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_in_schedule_fifo_interrupt_sta",
+			PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_STAr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_ppu_ppu_ppu_in_schedule_fifo_interrupt_sta_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_mf_out_fifo_interrupt_sta",
+			PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_STAr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xcc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			12,
+			g_ppu_ppu_ppu_mf_out_fifo_interrupt_sta_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_mcode_pf_req_schedule_fifo_interrupt_sta",
+			PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_STAr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			12,
+			g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_sta_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_mcode_pf_rsp_schedule_fifo_interrupt_sta",
+			PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_STAr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_sta_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_mccnt_fifo_interrupt_sta",
+			PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_STAr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_ppu_ppu_ppu_mccnt_fifo_interrupt_sta_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"coprocessor_fifo_interrupt_sta_l",
+			PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_ppu_ppu_coprocessor_fifo_interrupt_sta_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"coprocessor_fifo_interrupt_sta_m",
+			PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Mr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_ppu_ppu_coprocessor_fifo_interrupt_sta_m_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"coprocessor_fifo_interrupt_sta_h",
+			PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_STA_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xe4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_ppu_ppu_coprocessor_fifo_interrupt_sta_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_fifo_interrupt_sta",
+			PPU_PPU_INSTRMEM_FIFO_INTERRUPT_STAr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			8,
+			g_ppu_ppu_instrmem_fifo_interrupt_sta_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_ram_check_ecc_err_flag_1",
+			PPU_PPU_PPU_RAM_CHECK_ECC_ERR_FLAG_1r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x0f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			26,
+			g_ppu_ppu_ppu_ram_check_ecc_err_flag_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_ppu_demux_fifo_interrupt_flag",
+			PPU_PPU_ISU_PPU_DEMUX_FIFO_INTERRUPT_FLAGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x100,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_ppu_ppu_isu_ppu_demux_fifo_interrupt_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_multicast_fifo_interrupt_flag",
+			PPU_PPU_PPU_MULTICAST_FIFO_INTERRUPT_FLAGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x104,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			20,
+			g_ppu_ppu_ppu_multicast_fifo_interrupt_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_in_schedule_fifo_interrupt_flag",
+			PPU_PPU_PPU_IN_SCHEDULE_FIFO_INTERRUPT_FLAGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x108,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_ppu_ppu_ppu_in_schedule_fifo_interrupt_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_mf_out_fifo_interrupt_flag",
+			PPU_PPU_PPU_MF_OUT_FIFO_INTERRUPT_FLAGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x10c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			12,
+			g_ppu_ppu_ppu_mf_out_fifo_interrupt_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_mcode_pf_req_schedule_fifo_interrupt_flag",
+			PPU_PPU_PBU_MCODE_PF_REQ_SCHEDULE_FIFO_INTERRUPT_FLAGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x110,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			12,
+			g_ppu_ppu_pbu_mcode_pf_req_schedule_fifo_interrupt_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_mcode_pf_rsp_schedule_fifo_interrupt_flag",
+			PPU_PPU_PBU_MCODE_PF_RSP_SCHEDULE_FIFO_INTERRUPT_FLAGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x114,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_ppu_ppu_pbu_mcode_pf_rsp_schedule_fifo_interrupt_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_mccnt_fifo_interrupt_flag",
+			PPU_PPU_PPU_MCCNT_FIFO_INTERRUPT_FLAGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x118,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_ppu_ppu_ppu_mccnt_fifo_interrupt_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"coprocessor_fifo_interrupt_flag_l",
+			PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x11c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_ppu_ppu_coprocessor_fifo_interrupt_flag_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"coprocessor_fifo_interrupt_flag_m",
+			PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Mr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x120,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_ppu_ppu_coprocessor_fifo_interrupt_flag_m_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"coprocessor_fifo_interrupt_flag_h",
+			PPU_PPU_COPROCESSOR_FIFO_INTERRUPT_FLAG_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x124,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_ppu_ppu_coprocessor_fifo_interrupt_flag_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_fifo_interrupt_flag",
+			PPU_PPU_INSTRMEM_FIFO_INTERRUPT_FLAGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x128,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			12,
+			g_ppu_ppu_instrmem_fifo_interrupt_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_ram_int_out",
+			PPU_PPU_INSTRMEM_RAM_INT_OUTr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x140,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			12,
+			g_ppu_ppu_instrmem_ram_int_out_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_ram_int_mask",
+			PPU_PPU_INSTRMEM_RAM_INT_MASKr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x144,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			12,
+			g_ppu_ppu_instrmem_ram_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_ram_int_stat",
+			PPU_PPU_INSTRMEM_RAM_INT_STATr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x148,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			12,
+			g_ppu_ppu_instrmem_ram_int_stat_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_ram_int_flag",
+			PPU_PPU_INSTRMEM_RAM_INT_FLAGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x14c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			12,
+			g_ppu_ppu_instrmem_ram_int_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_count_cfg",
+			PPU_PPU_PPU_COUNT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x158,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_ppu_ppu_ppu_count_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_statics_cfg",
+			PPU_PPU_PPU_STATICS_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x15c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_ppu_ppu_ppu_statics_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_statics_wb_cfg",
+			PPU_PPU_PPU_STATICS_WB_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x160,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_ppu_ppu_ppu_statics_wb_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"wr_table_self_rsp_en_cfg",
+			PPU_PPU_WR_TABLE_SELF_RSP_EN_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x164,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_wr_table_self_rsp_en_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_random_arbiter_8to1_cfg",
+			PPU_PPU_PPU_RANDOM_ARBITER_8TO1_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x168,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_random_arbiter_8to1_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_reorder_bypass_flow_num_cfg",
+			PPU_PPU_PPU_REORDER_BYPASS_FLOW_NUM_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x16c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_reorder_bypass_flow_num_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cos_meter_cfg_h",
+			PPU_PPU_COS_METER_CFG_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x170,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			8,
+			5,
+			g_ppu_ppu_cos_meter_cfg_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cos_meter_cfg_l",
+			PPU_PPU_COS_METER_CFG_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x174,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			8,
+			3,
+			g_ppu_ppu_cos_meter_cfg_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_rdy",
+			PPU_PPU_INSTRMEM_RDYr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x1c0,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_addr",
+			PPU_PPU_INSTRMEM_ADDRr,
+			PPU,
+			DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x1d0,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			2,
+			g_ppu_ppu_instrmem_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_ind_access_done",
+			PPU_PPU_INSTRMEM_IND_ACCESS_DONEr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x1e0,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_ind_access_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_instr0_data_l",
+			PPU_PPU_INSTRMEM_INSTR0_DATA_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x1f0,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_instr0_data_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_instr0_data_h",
+			PPU_PPU_INSTRMEM_INSTR0_DATA_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x200,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_instr0_data_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_instr1_data_l",
+			PPU_PPU_INSTRMEM_INSTR1_DATA_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x210,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_instr1_data_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_instr1_data_h",
+			PPU_PPU_INSTRMEM_INSTR1_DATA_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x220,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_instr1_data_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_instr2_data_l",
+			PPU_PPU_INSTRMEM_INSTR2_DATA_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x230,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_instr2_data_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_instr2_data_h",
+			PPU_PPU_INSTRMEM_INSTR2_DATA_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x240,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_instr2_data_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_instr3_data_l",
+			PPU_PPU_INSTRMEM_INSTR3_DATA_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x250,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_instr3_data_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_instr3_data_h",
+			PPU_PPU_INSTRMEM_INSTR3_DATA_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x260,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_instr3_data_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_read_instr0_data_l",
+			PPU_PPU_INSTRMEM_READ_INSTR0_DATA_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x270,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_read_instr0_data_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_read_instr0_data_h",
+			PPU_PPU_INSTRMEM_READ_INSTR0_DATA_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x280,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_read_instr0_data_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_read_instr1_data_l",
+			PPU_PPU_INSTRMEM_READ_INSTR1_DATA_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x290,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_read_instr1_data_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_read_instr1_data_h",
+			PPU_PPU_INSTRMEM_READ_INSTR1_DATA_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x2a0,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_read_instr1_data_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_read_instr2_data_l",
+			PPU_PPU_INSTRMEM_READ_INSTR2_DATA_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x2b0,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_read_instr2_data_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_read_instr2_data_h",
+			PPU_PPU_INSTRMEM_READ_INSTR2_DATA_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x2c0,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_read_instr2_data_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_read_instr3_data_l",
+			PPU_PPU_INSTRMEM_READ_INSTR3_DATA_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x2d0,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_read_instr3_data_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"instrmem_read_instr3_data_h",
+			PPU_PPU_INSTRMEM_READ_INSTR3_DATA_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x2e0,
+			(32 / 8),
+			0,
+			2 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_instrmem_read_instr3_data_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_ppu_mc_srh_fc_cnt_h",
+			PPU_PPU_SE_PPU_MC_SRH_FC_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x300,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_se_ppu_mc_srh_fc_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_ppu_mc_srh_fc_cnt_l",
+			PPU_PPU_SE_PPU_MC_SRH_FC_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x304,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_se_ppu_mc_srh_fc_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_se_mc_srh_fc_cnt_h",
+			PPU_PPU_PPU_SE_MC_SRH_FC_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x308,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_se_mc_srh_fc_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_se_mc_srh_fc_cnt_l",
+			PPU_PPU_PPU_SE_MC_SRH_FC_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x30c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_se_mc_srh_fc_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_se_mc_srh_vld_cnt_h",
+			PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x310,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_se_mc_srh_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_se_mc_srh_vld_cnt_l",
+			PPU_PPU_PPU_SE_MC_SRH_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x314,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_se_mc_srh_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_ppu_mc_srh_vld_cnt_h",
+			PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x318,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_se_ppu_mc_srh_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_ppu_mc_srh_vld_cnt_l",
+			PPU_PPU_SE_PPU_MC_SRH_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x31c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_se_ppu_mc_srh_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_logic_pf_fc_cnt_h",
+			PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x320,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_logic_pf_fc_cnt_l",
+			PPU_PPU_PBU_PPU_LOGIC_PF_FC_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x324,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pbu_ppu_logic_pf_fc_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_logic_rsp_fc_cnt_h",
+			PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x328,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_logic_rsp_fc_cnt_l",
+			PPU_PPU_PPU_PBU_LOGIC_RSP_FC_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x32c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pbu_logic_rsp_fc_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_logic_pf_req_vld_cnt_h",
+			PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x330,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_logic_pf_req_vld_cnt_l",
+			PPU_PPU_PPU_PBU_LOGIC_PF_REQ_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x334,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pbu_logic_pf_req_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_logic_pf_rsp_vld_cnt_h",
+			PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x338,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_logic_pf_rsp_vld_cnt_l",
+			PPU_PPU_PBU_PPU_LOGIC_PF_RSP_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x33c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pbu_ppu_logic_pf_rsp_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_ifb_rd_fc_cnt_h",
+			PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x340,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_ifb_rd_fc_cnt_l",
+			PPU_PPU_PBU_PPU_IFB_RD_FC_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x344,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pbu_ppu_ifb_rd_fc_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_wb_fc_cnt_h",
+			PPU_PPU_PBU_PPU_WB_FC_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x348,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pbu_ppu_wb_fc_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_wb_fc_cnt_l",
+			PPU_PPU_PBU_PPU_WB_FC_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x34c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pbu_ppu_wb_fc_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_mcode_pf_req_vld_cnt_h",
+			PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x350,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_mcode_pf_req_vld_cnt_l",
+			PPU_PPU_PPU_PBU_MCODE_PF_REQ_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x354,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pbu_mcode_pf_req_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_mcode_pf_rsp_vld_cnt_h",
+			PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x358,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_mcode_pf_rsp_vld_cnt_l",
+			PPU_PPU_PBU_PPU_MCODE_PF_RSP_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x35c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pbu_ppu_mcode_pf_rsp_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_ppu_para_fc_cnt_h",
+			PPU_PPU_ODMA_PPU_PARA_FC_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x360,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_odma_ppu_para_fc_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_ppu_para_fc_cnt_l",
+			PPU_PPU_ODMA_PPU_PARA_FC_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x364,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_odma_ppu_para_fc_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_ppu_mccnt_wr_fc_cnt_h",
+			PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x368,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_ppu_mccnt_wr_fc_cnt_l",
+			PPU_PPU_ODMA_PPU_MCCNT_WR_FC_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x36c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_odma_ppu_mccnt_wr_fc_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_odma_mccnt_wr_vld_cnt_h",
+			PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x370,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_odma_mccnt_wr_vld_cnt_l",
+			PPU_PPU_PPU_ODMA_MCCNT_WR_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x374,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_odma_mccnt_wr_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_ppu_mccnt_rsp_vld_cnt_h",
+			PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x378,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_ppu_mccnt_rsp_vld_cnt_l",
+			PPU_PPU_ODMA_PPU_MCCNT_RSP_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x37c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_odma_ppu_mccnt_rsp_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pktrx_uc_fc_cnt_h",
+			PPU_PPU_PPU_PKTRX_UC_FC_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x380,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pktrx_uc_fc_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pktrx_uc_fc_cnt_l",
+			PPU_PPU_PPU_PKTRX_UC_FC_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x384,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pktrx_uc_fc_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pktrx_mc_fc_cnt_h",
+			PPU_PPU_PPU_PKTRX_MC_FC_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x388,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pktrx_mc_fc_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pktrx_mc_fc_cnt_l",
+			PPU_PPU_PPU_PKTRX_MC_FC_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x38c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pktrx_mc_fc_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_ppu_desc_vld_cnt_h",
+			PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x390,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pktrx_ppu_desc_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pktrx_ppu_desc_vld_cnt_l",
+			PPU_PPU_PKTRX_PPU_DESC_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x394,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pktrx_ppu_desc_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_ifb_req_vld_cnt_h",
+			PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x398,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_ifb_req_vld_cnt_l",
+			PPU_PPU_PPU_PBU_IFB_REQ_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x39c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pbu_ifb_req_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_ifb_rsp_vld_cnt_h",
+			PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_ifb_rsp_vld_cnt_l",
+			PPU_PPU_PBU_PPU_IFB_RSP_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pbu_ppu_ifb_rsp_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_wb_vld_cnt_h",
+			PPU_PPU_PPU_PBU_WB_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pbu_wb_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_wb_vld_cnt_l",
+			PPU_PPU_PPU_PBU_WB_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pbu_wb_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_reorder_para_vld_cnt_h",
+			PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ppu_reorder_para_vld_cnt_l",
+			PPU_PPU_PBU_PPU_REORDER_PARA_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pbu_ppu_reorder_para_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_odma_para_vld_cnt_h",
+			PPU_PPU_PPU_ODMA_PARA_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_odma_para_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_odma_para_vld_cnt_l",
+			PPU_PPU_PPU_ODMA_PARA_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x3bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_odma_para_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_isu_ppu_mc_vld_cnt_h",
+			PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x400,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_isu_ppu_mc_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_isu_ppu_mc_vld_cnt_l",
+			PPU_PPU_STATICS_ISU_PPU_MC_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x404,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_isu_ppu_mc_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_isu_ppu_mc_loop_vld_cnt_h",
+			PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x410,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_isu_ppu_mc_loop_vld_cnt_l",
+			PPU_PPU_STATICS_ISU_PPU_MC_LOOP_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x414,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_isu_ppu_mc_loop_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_isu_ppu_uc_vld_cnt_h",
+			PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x418,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_isu_ppu_uc_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_isu_ppu_uc_vld_cnt_l",
+			PPU_PPU_STATICS_ISU_PPU_UC_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x41c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_isu_ppu_uc_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_isu_ppu_uc_bufnumis0_vld_cnt_h",
+			PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x420,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_isu_ppu_uc_bufnumis0_vld_cnt_l",
+			PPU_PPU_STATICS_ISU_PPU_UC_BUFNUMIS0_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x424,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_isu_ppu_uc_bufnumis0_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_demux_schedule_mc_vld_cnt_h",
+			PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x438,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_demux_schedule_mc_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_demux_schedule_mc_vld_cnt_l",
+			PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x43c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_demux_schedule_mc_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_demux_schedule_mc_bufnumis0_vld_cnt_h",
+			PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x440,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_demux_schedule_mc_bufnumis0_vld_cnt_l",
+			PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_BUFNUMIS0_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x444,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_demux_schedule_mc_bufnumis0_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_demux_schedule_mc_srcportis0_vld_cnt_h",
+			PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x448,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_demux_schedule_mc_srcportis0_vld_cnt_l",
+			PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS0_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x44c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_demux_schedule_mc_srcportis0_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_demux_schedule_mc_srcportis1_vld_cnt_h",
+			PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x450,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_demux_schedule_mc_srcportis1_vld_cnt_l",
+			PPU_PPU_STATICS_DEMUX_SCHEDULE_MC_SRCPORTIS1_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x454,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_demux_schedule_mc_srcportis1_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_demux_schedule_uc_vld_cnt_h",
+			PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x458,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_demux_schedule_uc_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_demux_schedule_uc_vld_cnt_l",
+			PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x45c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_demux_schedule_uc_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_demux_schedule_uc_bufnumis0_vld_cnt_h",
+			PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x460,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_demux_schedule_uc_bufnumis0_vld_cnt_l",
+			PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_BUFNUMIS0_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x464,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_demux_schedule_uc_bufnumis0_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_demux_schedule_uc_srcportis0_vld_cnt_h",
+			PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x468,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_demux_schedule_uc_srcportis0_vld_cnt_l",
+			PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS0_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x46c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_demux_schedule_uc_srcportis0_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_demux_schedule_uc_srcportis1_vld_cnt_h",
+			PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x470,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_demux_schedule_uc_srcportis1_vld_cnt_l",
+			PPU_PPU_STATICS_DEMUX_SCHEDULE_UC_SRCPORTIS1_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x474,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_demux_schedule_uc_srcportis1_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_vld_cnt_h",
+			PPU_PPU_STATICS_PPU_WB_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x478,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_vld_cnt_l",
+			PPU_PPU_STATICS_PPU_WB_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x47c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_bufnumis0_vld_cnt_h",
+			PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x480,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_bufnumis0_vld_cnt_l",
+			PPU_PPU_STATICS_PPU_WB_BUFNUMIS0_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x484,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_bufnumis0_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_srcportis0_vld_cnt_h",
+			PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x488,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_srcportis0_vld_cnt_l",
+			PPU_PPU_STATICS_PPU_WB_SRCPORTIS0_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x48c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_srcportis0_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_srcportis1_vld_cnt_h",
+			PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x490,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_srcportis1_vld_cnt_l",
+			PPU_PPU_STATICS_PPU_WB_SRCPORTIS1_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x494,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_srcportis1_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_halt_send_type_vld_cnt_h",
+			PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x498,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_halt_send_type_vld_cnt_l",
+			PPU_PPU_STATICS_PPU_WB_HALT_SEND_TYPE_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x49c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_halt_send_type_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_mf_type_vld_cnt_h",
+			PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_mf_type_vld_cnt_l",
+			PPU_PPU_STATICS_PPU_WB_MF_TYPE_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_mf_type_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_halt_continue_end_vld_cnt_h",
+			PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_halt_continue_end_vld_cnt_l",
+			PPU_PPU_STATICS_PPU_WB_HALT_CONTINUE_END_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_halt_continue_end_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_dup_flag_vld_cnt_h",
+			PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_dup_flag_vld_cnt_l",
+			PPU_PPU_STATICS_PPU_WB_DUP_FLAG_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_dup_flag_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_last_flag_vld_cnt_h",
+			PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_last_flag_vld_cnt_l",
+			PPU_PPU_STATICS_PPU_WB_LAST_FLAG_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_last_flag_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_dis_flag_vld_cnt_h",
+			PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_ppu_wb_dis_flag_vld_cnt_l",
+			PPU_PPU_STATICS_PPU_WB_DIS_FLAG_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_ppu_wb_dis_flag_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h",
+			PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l",
+			PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_SEND_TYPE_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_pbu_ppu_reorder_halt_send_type_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_pbu_ppu_reorder_mf_type_vld_cnt_h",
+			PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_pbu_ppu_reorder_mf_type_vld_cnt_l",
+			PPU_PPU_STATICS_PBU_PPU_REORDER_MF_TYPE_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_pbu_ppu_reorder_mf_type_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h",
+			PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l",
+			PPU_PPU_STATICS_PBU_PPU_REORDER_HALT_CONTINUE_END_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_statics_pbu_ppu_reorder_halt_continue_end_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"car_green_pkt_vld_cnt_h",
+			PPU_PPU_CAR_GREEN_PKT_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_car_green_pkt_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"car_green_pkt_vld_cnt_l",
+			PPU_PPU_CAR_GREEN_PKT_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_car_green_pkt_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"car_yellow_pkt_vld_cnt_h",
+			PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_car_yellow_pkt_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"car_yellow_pkt_vld_cnt_l",
+			PPU_PPU_CAR_YELLOW_PKT_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_car_yellow_pkt_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"car_red_pkt_vld_cnt_h",
+			PPU_PPU_CAR_RED_PKT_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_car_red_pkt_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"car_red_pkt_vld_cnt_l",
+			PPU_PPU_CAR_RED_PKT_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_car_red_pkt_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"car_drop_pkt_vld_cnt_h",
+			PPU_PPU_CAR_DROP_PKT_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_car_drop_pkt_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"car_drop_pkt_vld_cnt_l",
+			PPU_PPU_CAR_DROP_PKT_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x4fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_car_drop_pkt_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pktrx_mc_ptr_vld_cnt_h",
+			PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x500,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pktrx_mc_ptr_vld_cnt_l",
+			PPU_PPU_PPU_PKTRX_MC_PTR_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x504,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pktrx_mc_ptr_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_ppu_loopback_fc_cnt_h",
+			PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x508,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_isu_ppu_loopback_fc_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_ppu_loopback_fc_cnt_l",
+			PPU_PPU_ISU_PPU_LOOPBACK_FC_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x50c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_isu_ppu_loopback_fc_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg",
+			PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x540,
+			(32 / 8),
+			0,
+			0x5 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg",
+			PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x558,
+			(32 / 8),
+			0,
+			0x5 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg",
+			PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x570,
+			(32 / 8),
+			0,
+			0x5 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg",
+			PPU_PPU_PPU_CULSTER_PBU_MCODE_PF_REQ_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x588,
+			(32 / 8),
+			0,
+			0x5 + 1,
+			0,
+			4,
+			1,
+			g_ppu_ppu_ppu_culster_pbu_mcode_pf_req_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg",
+			PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg",
+			PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg",
+			PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg",
+			PPU_PPU_PPU_PBU_MCODE_PF_RSP_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pbu_mcode_pf_rsp_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mccnt_fifo_prog_full_assert_cfg",
+			PPU_PPU_MCCNT_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_mccnt_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mccnt_fifo_prog_full_negate_cfg",
+			PPU_PPU_MCCNT_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_mccnt_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mccnt_fifo_prog_empty_assert_cfg",
+			PPU_PPU_MCCNT_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_mccnt_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mccnt_fifo_prog_empty_negate_cfg",
+			PPU_PPU_MCCNT_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_mccnt_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"uc_mf_fifo_prog_full_assert_cfg",
+			PPU_PPU_UC_MF_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_uc_mf_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"uc_mf_fifo_prog_full_negate_cfg",
+			PPU_PPU_UC_MF_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_uc_mf_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"uc_mf_fifo_prog_empty_assert_cfg",
+			PPU_PPU_UC_MF_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_uc_mf_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"uc_mf_fifo_prog_empty_negate_cfg",
+			PPU_PPU_UC_MF_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_uc_mf_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mc_mf_fifo_prog_full_assert_cfg",
+			PPU_PPU_MC_MF_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_mc_mf_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mc_mf_fifo_prog_full_negate_cfg",
+			PPU_PPU_MC_MF_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_mc_mf_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mc_mf_fifo_prog_empty_assert_cfg",
+			PPU_PPU_MC_MF_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_mc_mf_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mc_mf_fifo_prog_empty_negate_cfg",
+			PPU_PPU_MC_MF_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_mc_mf_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_mf_fifo_prog_full_assert_cfg",
+			PPU_PPU_ISU_MF_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_isu_mf_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_mf_fifo_prog_full_negate_cfg",
+			PPU_PPU_ISU_MF_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_isu_mf_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_mf_fifo_prog_empty_assert_cfg",
+			PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_isu_mf_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_mf_fifo_prog_empty_negate_cfg",
+			PPU_PPU_ISU_MF_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_isu_mf_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_fwft_mf_fifo_prog_empty_assert_cfg",
+			PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_isu_fwft_mf_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_fwft_mf_fifo_prog_empty_negate_cfg",
+			PPU_PPU_ISU_FWFT_MF_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x5fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_isu_fwft_mf_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_mc_para_mf_fifo_prog_full_assert_cfg",
+			PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x600,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_isu_mc_para_mf_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_mc_para_mf_fifo_prog_full_negate_cfg",
+			PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x604,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_isu_mc_para_mf_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_mc_para_mf_fifo_prog_empty_assert_cfg",
+			PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x608,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"isu_mc_para_mf_fifo_prog_empty_negate_cfg",
+			PPU_PPU_ISU_MC_PARA_MF_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x60c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_isu_mc_para_mf_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"group_id_fifo_prog_full_assert_cfg",
+			PPU_PPU_GROUP_ID_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x610,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_group_id_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"group_id_fifo_prog_full_negate_cfg",
+			PPU_PPU_GROUP_ID_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x614,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_group_id_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"group_id_fifo_prog_empty_assert_cfg",
+			PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x618,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_group_id_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"group_id_fifo_prog_empty_negate_cfg",
+			PPU_PPU_GROUP_ID_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x61c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_group_id_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sa_para_fifo_prog_full_assert_cfg",
+			PPU_PPU_SA_PARA_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x620,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_sa_para_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sa_para_fifo_prog_full_negate_cfg",
+			PPU_PPU_SA_PARA_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x624,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_sa_para_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sa_para_fifo_prog_empty_assert_cfg",
+			PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x628,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_sa_para_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sa_para_fifo_prog_empty_negate_cfg",
+			PPU_PPU_SA_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x62c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_sa_para_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_mc_rsp_fifo_prog_full_assert_cfg",
+			PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x630,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_se_mc_rsp_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_mc_rsp_fifo_prog_full_negate_cfg",
+			PPU_PPU_SE_MC_RSP_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x634,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_se_mc_rsp_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_mc_rsp_fifo_prog_empty_assert_cfg",
+			PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x638,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_se_mc_rsp_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_mc_rsp_fifo_prog_empty_negate_cfg",
+			PPU_PPU_SE_MC_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x63c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_se_mc_rsp_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dup_para_fifo_prog_full_assert_cfg",
+			PPU_PPU_DUP_PARA_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x640,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_dup_para_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dup_para_fifo_prog_full_negate_cfg",
+			PPU_PPU_DUP_PARA_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x644,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_dup_para_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dup_para_fifo_prog_empty_assert_cfg",
+			PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x648,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_dup_para_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dup_para_fifo_prog_empty_negate_cfg",
+			PPU_PPU_DUP_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x64c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_dup_para_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pf_rsp_fifo_prog_full_assert_cfg",
+			PPU_PPU_PF_RSP_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x650,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pf_rsp_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pf_rsp_fifo_prog_full_negate_cfg",
+			PPU_PPU_PF_RSP_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x654,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pf_rsp_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pf_rsp_fifo_prog_empty_assert_cfg",
+			PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x658,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pf_rsp_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pf_rsp_fifo_prog_empty_negate_cfg",
+			PPU_PPU_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x65c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pf_rsp_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dup_freeptr_fifo_prog_full_assert_cfg",
+			PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x660,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_dup_freeptr_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dup_freeptr_fifo_prog_full_negate_cfg",
+			PPU_PPU_DUP_FREEPTR_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x664,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_dup_freeptr_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dup_freeptr_fifo_prog_empty_assert_cfg",
+			PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x668,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_dup_freeptr_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dup_freeptr_fifo_prog_empty_negate_cfg",
+			PPU_PPU_DUP_FREEPTR_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x66c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_dup_freeptr_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pf_req_fifo_prog_full_assert_cfg",
+			PPU_PPU_PF_REQ_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x670,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pf_req_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pf_req_fifo_prog_full_negate_cfg",
+			PPU_PPU_PF_REQ_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x674,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pf_req_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pf_req_fifo_prog_empty_assert_cfg",
+			PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x678,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pf_req_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pf_req_fifo_prog_empty_negate_cfg",
+			PPU_PPU_PF_REQ_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x67c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pf_req_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"car_flag_fifo_prog_full_assert_cfg",
+			PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x680,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_car_flag_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"car_flag_fifo_prog_full_negate_cfg",
+			PPU_PPU_CAR_FLAG_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x684,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_car_flag_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"car_flag_fifo_prog_empty_assert_cfg",
+			PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x688,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_car_flag_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"car_flag_fifo_prog_empty_negate_cfg",
+			PPU_PPU_CAR_FLAG_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x68c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_car_flag_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cluster_mf_out_afifo_prog_full_assert_cfg",
+			PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x690,
+			(32 / 8),
+			0,
+			0x5 + 1,
+			0,
+			16,
+			1,
+			g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cluster_mf_out_afifo_prog_full_negate_cfg",
+			PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x694,
+			(32 / 8),
+			0,
+			0x5 + 1,
+			0,
+			16,
+			1,
+			g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cluster_mf_out_afifo_prog_empty_assert_cfg",
+			PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x698,
+			(32 / 8),
+			0,
+			0x5 + 1,
+			0,
+			16,
+			1,
+			g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cluster_mf_out_afifo_prog_empty_negate_cfg",
+			PPU_PPU_PPU_CLUSTER_MF_OUT_AFIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x69c,
+			(32 / 8),
+			0,
+			0x5 + 1,
+			0,
+			16,
+			1,
+			g_ppu_ppu_ppu_cluster_mf_out_afifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_key_fifo_prog_full_assert_cfg",
+			PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x6f0,
+			(32 / 8),
+			0,
+			0x5 + 1,
+			0,
+			16,
+			1,
+			g_ppu_ppu_ppu_cop_key_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_key_fifo_prog_full_negate_cfg",
+			PPU_PPU_PPU_COP_KEY_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x6f4,
+			(32 / 8),
+			0,
+			0x5 + 1,
+			0,
+			16,
+			1,
+			g_ppu_ppu_ppu_cop_key_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_key_fifo_prog_empty_assert_cfg",
+			PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x6f8,
+			(32 / 8),
+			0,
+			0x5 + 1,
+			0,
+			16,
+			1,
+			g_ppu_ppu_ppu_cop_key_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_key_fifo_prog_empty_negate_cfg",
+			PPU_PPU_PPU_COP_KEY_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x6fc,
+			(32 / 8),
+			0,
+			0x5 + 1,
+			0,
+			16,
+			1,
+			g_ppu_ppu_ppu_cop_key_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_random_mod_para_fifo_prog_full_assert_cfg",
+			PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x750,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_random_mod_para_fifo_prog_full_negate_cfg",
+			PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x754,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg",
+			PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x758,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg",
+			PPU_PPU_PPU_COP_RANDOM_MOD_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x75c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_random_mod_para_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_random_mod_result_fifo_prog_full_assert_cfg",
+			PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x760,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_random_mod_result_fifo_prog_full_negate_cfg",
+			PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x764,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg",
+			PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x768,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg",
+			PPU_PPU_PPU_COP_RANDOM_MOD_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x76c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_random_mod_result_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_checksum_result_fifo_prog_full_assert_cfg",
+			PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x770,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_checksum_result_fifo_prog_full_negate_cfg",
+			PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x774,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_checksum_result_fifo_prog_empty_assert_cfg",
+			PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x778,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_checksum_result_fifo_prog_empty_negate_cfg",
+			PPU_PPU_PPU_COP_CHECKSUM_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x77c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_checksum_result_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_crc_first_para_fifo_prog_full_assert_cfg",
+			PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x780,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_crc_first_para_fifo_prog_full_negate_cfg",
+			PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x784,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg",
+			PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x788,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg",
+			PPU_PPU_PPU_COP_CRC_FIRST_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x78c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_crc_first_para_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_crc_bypass_delay_prog_full_assert_cfg",
+			PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x790,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_crc_bypass_delay_prog_full_negate_cfg",
+			PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x794,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_crc_bypass_delay_prog_empty_assert_cfg",
+			PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x798,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_crc_bypass_delay_prog_empty_negate_cfg",
+			PPU_PPU_PPU_COP_CRC_BYPASS_DELAY_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x79c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_crc_bypass_delay_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_crc_second_para_fifo_prog_full_assert_cfg",
+			PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_crc_second_para_fifo_prog_full_negate_cfg",
+			PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg",
+			PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg",
+			PPU_PPU_PPU_COP_CRC_SECOND_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_crc_second_para_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg",
+			PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg",
+			PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg",
+			PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg",
+			PPU_PPU_PPU_COP_CRC_RESULT_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_crc_result_fwft_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_multiply_para_fifo_prog_full_assert_cfg",
+			PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_multiply_para_fifo_prog_full_negate_cfg",
+			PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_multiply_para_fifo_prog_empty_assert_cfg",
+			PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_multiply_para_fifo_prog_empty_negate_cfg",
+			PPU_PPU_PPU_COP_MULTIPLY_PARA_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_multiply_para_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg",
+			PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg",
+			PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg",
+			PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg",
+			PPU_PPU_PPU_COP_MULTIPLY_PARA_RESULT_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_cop_multiply_para_result_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"free_global_num_fwft_fifo_prog_full_assert_cfg",
+			PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_free_global_num_fwft_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"free_global_num_fwft_fifo_prog_full_negate_cfg",
+			PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_free_global_num_fwft_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"free_global_num_fwft_fifo_prog_empty_assert_cfg",
+			PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_free_global_num_fwft_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"free_global_num_fwft_fifo_prog_empty_negate_cfg",
+			PPU_PPU_FREE_GLOBAL_NUM_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_free_global_num_fwft_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg",
+			PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg",
+			PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg",
+			PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg",
+			PPU_PPU_PPU_PKTRX_MC_PTR_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x7fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_ppu_pktrx_mc_ptr_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data0",
+			PPU_PPU_PKT_DATA0r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x800,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data1",
+			PPU_PPU_PKT_DATA1r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x804,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data2",
+			PPU_PPU_PKT_DATA2r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x808,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data3",
+			PPU_PPU_PKT_DATA3r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x80c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data4",
+			PPU_PPU_PKT_DATA4r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x810,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data5",
+			PPU_PPU_PKT_DATA5r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x814,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data6",
+			PPU_PPU_PKT_DATA6r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x818,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data7",
+			PPU_PPU_PKT_DATA7r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x81c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data8",
+			PPU_PPU_PKT_DATA8r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x820,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data9",
+			PPU_PPU_PKT_DATA9r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x824,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data10",
+			PPU_PPU_PKT_DATA10r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x828,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data11",
+			PPU_PPU_PKT_DATA11r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x82c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data12",
+			PPU_PPU_PKT_DATA12r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x830,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data13",
+			PPU_PPU_PKT_DATA13r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x834,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data14",
+			PPU_PPU_PKT_DATA14r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x838,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data15",
+			PPU_PPU_PKT_DATA15r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x83c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data16",
+			PPU_PPU_PKT_DATA16r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x840,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data17",
+			PPU_PPU_PKT_DATA17r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x844,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data18",
+			PPU_PPU_PKT_DATA18r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x848,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data19",
+			PPU_PPU_PKT_DATA19r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x84c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data19_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data20",
+			PPU_PPU_PKT_DATA20r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x850,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data20_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data21",
+			PPU_PPU_PKT_DATA21r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x854,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data21_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data22",
+			PPU_PPU_PKT_DATA22r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x858,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data22_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data23",
+			PPU_PPU_PKT_DATA23r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x85c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data23_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data24",
+			PPU_PPU_PKT_DATA24r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x860,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data24_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data25",
+			PPU_PPU_PKT_DATA25r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x864,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data25_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data26",
+			PPU_PPU_PKT_DATA26r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x868,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data27",
+			PPU_PPU_PKT_DATA27r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x86c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data27_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data28",
+			PPU_PPU_PKT_DATA28r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x870,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data28_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data29",
+			PPU_PPU_PKT_DATA29r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x874,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data29_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data30",
+			PPU_PPU_PKT_DATA30r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x878,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data30_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data31",
+			PPU_PPU_PKT_DATA31r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x87c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data31_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data32",
+			PPU_PPU_PKT_DATA32r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x880,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data33",
+			PPU_PPU_PKT_DATA33r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x884,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data33_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data34",
+			PPU_PPU_PKT_DATA34r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x888,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data34_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data35",
+			PPU_PPU_PKT_DATA35r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x88c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data35_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data36",
+			PPU_PPU_PKT_DATA36r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x890,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data36_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data37",
+			PPU_PPU_PKT_DATA37r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x894,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data37_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data38",
+			PPU_PPU_PKT_DATA38r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x898,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data38_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data39",
+			PPU_PPU_PKT_DATA39r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x89c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data39_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data40",
+			PPU_PPU_PKT_DATA40r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data40_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data41",
+			PPU_PPU_PKT_DATA41r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data41_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data42",
+			PPU_PPU_PKT_DATA42r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data42_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data43",
+			PPU_PPU_PKT_DATA43r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data43_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data44",
+			PPU_PPU_PKT_DATA44r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data44_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data45",
+			PPU_PPU_PKT_DATA45r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data45_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data46",
+			PPU_PPU_PKT_DATA46r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data46_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data47",
+			PPU_PPU_PKT_DATA47r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data47_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data48",
+			PPU_PPU_PKT_DATA48r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data48_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data49",
+			PPU_PPU_PKT_DATA49r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data49_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data50",
+			PPU_PPU_PKT_DATA50r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data50_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data51",
+			PPU_PPU_PKT_DATA51r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data51_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data52",
+			PPU_PPU_PKT_DATA52r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data52_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data53",
+			PPU_PPU_PKT_DATA53r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data53_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data54",
+			PPU_PPU_PKT_DATA54r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data54_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data55",
+			PPU_PPU_PKT_DATA55r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data55_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data56",
+			PPU_PPU_PKT_DATA56r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data56_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data57",
+			PPU_PPU_PKT_DATA57r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data57_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data58",
+			PPU_PPU_PKT_DATA58r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data58_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data59",
+			PPU_PPU_PKT_DATA59r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data59_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data60",
+			PPU_PPU_PKT_DATA60r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data60_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data61",
+			PPU_PPU_PKT_DATA61r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data61_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data62",
+			PPU_PPU_PKT_DATA62r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data62_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data63",
+			PPU_PPU_PKT_DATA63r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x8fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data63_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data64",
+			PPU_PPU_PKT_DATA64r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x900,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data64_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data65",
+			PPU_PPU_PKT_DATA65r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x904,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data65_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data66",
+			PPU_PPU_PKT_DATA66r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x908,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data66_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data67",
+			PPU_PPU_PKT_DATA67r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x90c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data67_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data68",
+			PPU_PPU_PKT_DATA68r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x910,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data68_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data69",
+			PPU_PPU_PKT_DATA69r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x914,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data69_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data70",
+			PPU_PPU_PKT_DATA70r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x918,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data70_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data71",
+			PPU_PPU_PKT_DATA71r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x91c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data71_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data72",
+			PPU_PPU_PKT_DATA72r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x920,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data72_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data73",
+			PPU_PPU_PKT_DATA73r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x924,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data73_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data74",
+			PPU_PPU_PKT_DATA74r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x928,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data74_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data75",
+			PPU_PPU_PKT_DATA75r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x92c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data75_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data76",
+			PPU_PPU_PKT_DATA76r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x930,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data76_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data77",
+			PPU_PPU_PKT_DATA77r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x934,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data77_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data78",
+			PPU_PPU_PKT_DATA78r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x938,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data78_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data79",
+			PPU_PPU_PKT_DATA79r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x93c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data79_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data80",
+			PPU_PPU_PKT_DATA80r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x940,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data80_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data81",
+			PPU_PPU_PKT_DATA81r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x944,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data81_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data82",
+			PPU_PPU_PKT_DATA82r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x948,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data82_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data83",
+			PPU_PPU_PKT_DATA83r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x94c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data83_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data84",
+			PPU_PPU_PKT_DATA84r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x950,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data84_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data85",
+			PPU_PPU_PKT_DATA85r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x954,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data85_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data86",
+			PPU_PPU_PKT_DATA86r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x958,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data86_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data87",
+			PPU_PPU_PKT_DATA87r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x95c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data87_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data88",
+			PPU_PPU_PKT_DATA88r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x960,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data88_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data89",
+			PPU_PPU_PKT_DATA89r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x964,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data89_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data90",
+			PPU_PPU_PKT_DATA90r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x968,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data90_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data91",
+			PPU_PPU_PKT_DATA91r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x96c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data91_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data92",
+			PPU_PPU_PKT_DATA92r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x970,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data92_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data93",
+			PPU_PPU_PKT_DATA93r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x974,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data93_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data94",
+			PPU_PPU_PKT_DATA94r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x978,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data94_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data95",
+			PPU_PPU_PKT_DATA95r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x97c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data95_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data96",
+			PPU_PPU_PKT_DATA96r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x980,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data96_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data97",
+			PPU_PPU_PKT_DATA97r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x984,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data97_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data98",
+			PPU_PPU_PKT_DATA98r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x988,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data98_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data99",
+			PPU_PPU_PKT_DATA99r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x98c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data99_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data100",
+			PPU_PPU_PKT_DATA100r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x990,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data100_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data101",
+			PPU_PPU_PKT_DATA101r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x994,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data101_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data102",
+			PPU_PPU_PKT_DATA102r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x998,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data102_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data103",
+			PPU_PPU_PKT_DATA103r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x99c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data103_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data104",
+			PPU_PPU_PKT_DATA104r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data104_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data105",
+			PPU_PPU_PKT_DATA105r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data105_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data106",
+			PPU_PPU_PKT_DATA106r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data106_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data107",
+			PPU_PPU_PKT_DATA107r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data107_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data108",
+			PPU_PPU_PKT_DATA108r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data108_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data109",
+			PPU_PPU_PKT_DATA109r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data109_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data110",
+			PPU_PPU_PKT_DATA110r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data110_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data111",
+			PPU_PPU_PKT_DATA111r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data111_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data112",
+			PPU_PPU_PKT_DATA112r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data112_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data113",
+			PPU_PPU_PKT_DATA113r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data113_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data114",
+			PPU_PPU_PKT_DATA114r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data114_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data115",
+			PPU_PPU_PKT_DATA115r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data115_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data116",
+			PPU_PPU_PKT_DATA116r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data116_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data117",
+			PPU_PPU_PKT_DATA117r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data117_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data118",
+			PPU_PPU_PKT_DATA118r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data118_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data119",
+			PPU_PPU_PKT_DATA119r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data119_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data120",
+			PPU_PPU_PKT_DATA120r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data120_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data121",
+			PPU_PPU_PKT_DATA121r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data121_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data122",
+			PPU_PPU_PKT_DATA122r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data122_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data123",
+			PPU_PPU_PKT_DATA123r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data123_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data124",
+			PPU_PPU_PKT_DATA124r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data124_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data125",
+			PPU_PPU_PKT_DATA125r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data125_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data126",
+			PPU_PPU_PKT_DATA126r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data126_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pkt_data127",
+			PPU_PPU_PKT_DATA127r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0x9fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_pkt_data127_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr0",
+			PPU_PPU_SPR0r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa00,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr1",
+			PPU_PPU_SPR1r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa04,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr2",
+			PPU_PPU_SPR2r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa08,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr3",
+			PPU_PPU_SPR3r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa0c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr4",
+			PPU_PPU_SPR4r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa10,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr5",
+			PPU_PPU_SPR5r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa14,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr6",
+			PPU_PPU_SPR6r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa18,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr7",
+			PPU_PPU_SPR7r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa1c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr8",
+			PPU_PPU_SPR8r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa20,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr9",
+			PPU_PPU_SPR9r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa24,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr10",
+			PPU_PPU_SPR10r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa28,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr11",
+			PPU_PPU_SPR11r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa2c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr12",
+			PPU_PPU_SPR12r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa30,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr13",
+			PPU_PPU_SPR13r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa34,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr14",
+			PPU_PPU_SPR14r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa38,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr15",
+			PPU_PPU_SPR15r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa3c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr16",
+			PPU_PPU_SPR16r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa40,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr17",
+			PPU_PPU_SPR17r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa44,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr18",
+			PPU_PPU_SPR18r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa48,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr19",
+			PPU_PPU_SPR19r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa4c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr19_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr20",
+			PPU_PPU_SPR20r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa50,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr20_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr21",
+			PPU_PPU_SPR21r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa54,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr21_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr22",
+			PPU_PPU_SPR22r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa58,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr22_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr23",
+			PPU_PPU_SPR23r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa5c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr23_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr24",
+			PPU_PPU_SPR24r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa60,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr24_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr25",
+			PPU_PPU_SPR25r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa64,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr25_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr26",
+			PPU_PPU_SPR26r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa68,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr27",
+			PPU_PPU_SPR27r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa6c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr27_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr28",
+			PPU_PPU_SPR28r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa70,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr28_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr29",
+			PPU_PPU_SPR29r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa74,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr29_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr30",
+			PPU_PPU_SPR30r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa78,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr30_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"spr31",
+			PPU_PPU_SPR31r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa7c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_spr31_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp0",
+			PPU_PPU_RSP0r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa80,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp1",
+			PPU_PPU_RSP1r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa84,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp2",
+			PPU_PPU_RSP2r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa88,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp3",
+			PPU_PPU_RSP3r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa8c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp4",
+			PPU_PPU_RSP4r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa90,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp5",
+			PPU_PPU_RSP5r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa94,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp6",
+			PPU_PPU_RSP6r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa98,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp7",
+			PPU_PPU_RSP7r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xa9c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp8",
+			PPU_PPU_RSP8r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaa0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp9",
+			PPU_PPU_RSP9r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaa4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp10",
+			PPU_PPU_RSP10r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaa8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp11",
+			PPU_PPU_RSP11r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp12",
+			PPU_PPU_RSP12r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xab0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp13",
+			PPU_PPU_RSP13r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xab4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp14",
+			PPU_PPU_RSP14r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xab8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp15",
+			PPU_PPU_RSP15r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xabc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp16",
+			PPU_PPU_RSP16r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xac0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp17",
+			PPU_PPU_RSP17r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xac4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp18",
+			PPU_PPU_RSP18r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xac8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp19",
+			PPU_PPU_RSP19r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xacc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp19_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp20",
+			PPU_PPU_RSP20r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xad0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp20_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp21",
+			PPU_PPU_RSP21r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xad4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp21_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp22",
+			PPU_PPU_RSP22r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xad8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp22_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp23",
+			PPU_PPU_RSP23r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xadc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp23_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp24",
+			PPU_PPU_RSP24r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xae0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp24_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp25",
+			PPU_PPU_RSP25r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xae4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp25_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp26",
+			PPU_PPU_RSP26r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xae8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp27",
+			PPU_PPU_RSP27r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp27_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp28",
+			PPU_PPU_RSP28r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaf0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp28_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp29",
+			PPU_PPU_RSP29r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaf4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp29_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp30",
+			PPU_PPU_RSP30r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xaf8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp30_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsp31",
+			PPU_PPU_RSP31r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xafc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_rsp31_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key0",
+			PPU_PPU_KEY0r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb00,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key1",
+			PPU_PPU_KEY1r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb04,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key2",
+			PPU_PPU_KEY2r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb08,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key3",
+			PPU_PPU_KEY3r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb0c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key4",
+			PPU_PPU_KEY4r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb10,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key5",
+			PPU_PPU_KEY5r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb14,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key6",
+			PPU_PPU_KEY6r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb18,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key7",
+			PPU_PPU_KEY7r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb1c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key8",
+			PPU_PPU_KEY8r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb20,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key9",
+			PPU_PPU_KEY9r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb24,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key10",
+			PPU_PPU_KEY10r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb28,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key11",
+			PPU_PPU_KEY11r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb2c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key12",
+			PPU_PPU_KEY12r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb30,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key13",
+			PPU_PPU_KEY13r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb34,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key14",
+			PPU_PPU_KEY14r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb38,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key15",
+			PPU_PPU_KEY15r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb3c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key16",
+			PPU_PPU_KEY16r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb40,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key17",
+			PPU_PPU_KEY17r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb44,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key18",
+			PPU_PPU_KEY18r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb48,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"key19",
+			PPU_PPU_KEY19r,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb4c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ppu_ppu_key19_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"flag",
+			PPU_PPU_FLAGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_PPU_CSR_BASE_ADDR + 0xb50,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_ppu_ppu_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_1200m_flag",
+			PPU_CLUSTER_INT_1200M_FLAGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x00,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			8,
+			g_ppu_cluster_int_1200m_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"bp_instr_l",
+			PPU_CLUSTER_BP_INSTR_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x04,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_bp_instr_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"bp_instr_h",
+			PPU_CLUSTER_BP_INSTR_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x08,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_bp_instr_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"bp_addr",
+			PPU_CLUSTER_BP_ADDRr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x0c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0x7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			4,
+			1,
+			g_ppu_cluster_bp_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"drr",
+			PPU_CLUSTER_DRRr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0x7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			4,
+			1,
+			g_ppu_cluster_drr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dsr",
+			PPU_CLUSTER_DSRr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_dsr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dbg_rtl_date",
+			PPU_CLUSTER_DBG_RTL_DATEr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x50,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_dbg_rtl_date_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_continue",
+			PPU_CLUSTER_ME_CONTINUEr,
+			PPU,
+			DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x80,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_me_continue_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_step",
+			PPU_CLUSTER_ME_STEPr,
+			PPU,
+			DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x84,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_me_step_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_refresh",
+			PPU_CLUSTER_ME_REFRESHr,
+			PPU,
+			DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x88,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_me_refresh_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"drr_clr",
+			PPU_CLUSTER_DRR_CLRr,
+			PPU,
+			DPP_REG_FLAG_WO | DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x8c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_drr_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_busy_thresold",
+			PPU_CLUSTER_ME_BUSY_THRESOLDr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x90,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_me_busy_thresold_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_1200m_sta",
+			PPU_CLUSTER_INT_1200M_STAr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x94,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			8,
+			g_ppu_cluster_int_1200m_sta_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_1200m_me_fifo_mask_l",
+			PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc0,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0x7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			4,
+			32,
+			g_ppu_cluster_int_1200m_me_fifo_mask_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_1200m_me_fifo_mask_h",
+			PPU_CLUSTER_INT_1200M_ME_FIFO_MASK_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xe0,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0x7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			4,
+			2,
+			g_ppu_cluster_int_1200m_me_fifo_mask_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_fifo_interrupt_flag_l",
+			PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x100,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0x7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			4,
+			32,
+			g_ppu_cluster_me_fifo_interrupt_flag_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_fifo_interrupt_flag_h",
+			PPU_CLUSTER_ME_FIFO_INTERRUPT_FLAG_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x120,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0x7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			4,
+			2,
+			g_ppu_cluster_me_fifo_interrupt_flag_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_fifo_interrupt_sta_l",
+			PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x140,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0x7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			4,
+			32,
+			g_ppu_cluster_me_fifo_interrupt_sta_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_fifo_interrupt_sta_h",
+			PPU_CLUSTER_ME_FIFO_INTERRUPT_STA_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x160,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0x7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			4,
+			2,
+			g_ppu_cluster_me_fifo_interrupt_sta_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_1200m_cluster_mex_fifo_mask_l",
+			PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x800,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			32,
+			g_ppu_cluster_int_1200m_cluster_mex_fifo_mask_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_1200m_cluster_mex_fifo_mask_h",
+			PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_MASK_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x804,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			19,
+			g_ppu_cluster_int_1200m_cluster_mex_fifo_mask_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_1200m_cluster_mex_fifo_flag_l",
+			PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x808,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			32,
+			g_ppu_cluster_int_1200m_cluster_mex_fifo_flag_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_1200m_cluster_mex_fifo_flag_h",
+			PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_FLAG_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x80c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			19,
+			g_ppu_cluster_int_1200m_cluster_mex_fifo_flag_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_1200m_cluster_mex_fifo_stat_l",
+			PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x810,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			32,
+			g_ppu_cluster_int_1200m_cluster_mex_fifo_stat_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_1200m_cluster_mex_fifo_stat_h",
+			PPU_CLUSTER_INT_1200M_CLUSTER_MEX_FIFO_STAT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x814,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			19,
+			g_ppu_cluster_int_1200m_cluster_mex_fifo_stat_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_statics_wb_exception_cfg",
+			PPU_CLUSTER_PPU_STATICS_WB_EXCEPTION_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x824,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			6,
+			g_ppu_cluster_ppu_statics_wb_exception_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"thread_switch_en",
+			PPU_CLUSTER_THREAD_SWITCH_ENr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x8c0,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_thread_switch_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"is_me_not_idle",
+			PPU_CLUSTER_IS_ME_NOT_IDLEr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x8c4,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			8,
+			g_ppu_cluster_is_me_not_idle_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cluster_mf_in_afifo_prog_empty_assert_cfg",
+			PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc00,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cluster_mf_in_afifo_prog_empty_negate_cfg",
+			PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc04,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ese_rsp_afifo_prog_empty_assert_cfg",
+			PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc08,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ese_rsp_afifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ese_rsp_afifo_prog_empty_negate_cfg",
+			PPU_CLUSTER_ESE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc0c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ese_rsp_afifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ise_rsp_afifo_prog_empty_assert_cfg",
+			PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc10,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ise_rsp_afifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ise_rsp_afifo_prog_empty_negate_cfg",
+			PPU_CLUSTER_ISE_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc14,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ise_rsp_afifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg",
+			PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc18,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg",
+			PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc1c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg",
+			PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc20,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg",
+			PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO0_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc24,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_rsp_ptr_fwft_fifo0_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg",
+			PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc28,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg",
+			PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc2c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg",
+			PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc30,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg",
+			PPU_CLUSTER_PPU_RSP_PTR_FWFT_FIFO1_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc34,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_rsp_ptr_fwft_fifo1_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sta_rsp_afifo_prog_empty_assert_cfg",
+			PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc38,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_sta_rsp_afifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sta_rsp_afifo_prog_empty_negate_cfg",
+			PPU_CLUSTER_STA_RSP_AFIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc3c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_sta_rsp_afifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg",
+			PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc40,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg",
+			PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc44,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg",
+			PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc48,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg",
+			PPU_CLUSTER_PPU_STA_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc4c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_sta_rsp_fwft_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cop_rsp_fifo_prog_full_assert_cfg",
+			PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc50,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_cop_rsp_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cop_rsp_fifo_prog_full_negate_cfg",
+			PPU_CLUSTER_COP_RSP_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc54,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_cop_rsp_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cop_rsp_fifo_prog_empty_assert_cfg",
+			PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc58,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_cop_rsp_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cop_rsp_fifo_prog_empty_negate_cfg",
+			PPU_CLUSTER_COP_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc5c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_cop_rsp_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mcode_pf_rsp_fifo_prog_full_assert_cfg",
+			PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc60,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_mcode_pf_rsp_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mcode_pf_rsp_fifo_prog_full_negate_cfg",
+			PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc64,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_mcode_pf_rsp_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mcode_pf_rsp_fifo_prog_empty_assert_cfg",
+			PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc68,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mcode_pf_rsp_fifo_prog_empty_negate_cfg",
+			PPU_CLUSTER_MCODE_PF_RSP_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc6c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_mcode_pf_rsp_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg",
+			PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc70,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg",
+			PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc74,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg",
+			PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc78,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg",
+			PPU_CLUSTER_PPU_COP_RSP_FWFT_FIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc7c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_cop_rsp_fwft_fifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_ise_key_afifo_prog_full_assert_cfg",
+			PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc80,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_ise_key_afifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_ise_key_afifo_prog_full_negate_cfg",
+			PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc84,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_ise_key_afifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_ese_key_afifo_prog_full_assert_cfg",
+			PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc88,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_ese_key_afifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_ese_key_afifo_prog_full_negate_cfg",
+			PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc8c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_ese_key_afifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_sta_key_afifo_prog_full_assert_cfg",
+			PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc90,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_sta_key_afifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_sta_key_afifo_prog_full_negate_cfg",
+			PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0xc94,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_sta_key_afifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_600m_cluster_mex_fifo_mask",
+			PPU_CLUSTER_INT_600M_CLUSTER_MEX_FIFO_MASKr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4034,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			7,
+			g_ppu_cluster_int_600m_cluster_mex_fifo_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cluster_mex_fifo_600m_interrupt_flag",
+			PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_FLAGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4038,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			7,
+			g_ppu_cluster_cluster_mex_fifo_600m_interrupt_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cluster_mex_fifo_600m_interrupt_sta",
+			PPU_CLUSTER_CLUSTER_MEX_FIFO_600M_INTERRUPT_STAr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x403c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			7,
+			g_ppu_cluster_cluster_mex_fifo_600m_interrupt_sta_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex_cnt_cfg",
+			PPU_CLUSTER_MEX_CNT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4050,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			2,
+			g_ppu_cluster_mex_cnt_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_600m_cluster_mex_ram_ecc_error_interrupt_mask",
+			PPU_CLUSTER_INT_600M_CLUSTER_MEX_RAM_ECC_ERROR_INTERRUPT_MASKr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4064,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			6,
+			g_ppu_cluster_int_600m_cluster_mex_ram_ecc_error_interrupt_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cluster_mex_ram_600m_ecc_error_interrupt_flag",
+			PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_FLAGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4068,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			6,
+			g_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cluster_mex_ram_600m_ecc_error_interrupt_sta",
+			PPU_CLUSTER_CLUSTER_MEX_RAM_600M_ECC_ERROR_INTERRUPT_STAr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x406c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			6,
+			g_ppu_cluster_cluster_mex_ram_600m_ecc_error_interrupt_sta_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cluster_mf_in_afifo_prog_full_assert_cfg",
+			PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4400,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cluster_mf_in_afifo_prog_full_negate_cfg",
+			PPU_CLUSTER_PPU_CLUSTER_MF_IN_AFIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4410,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_cluster_mf_in_afifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ese_rsp_afifo_prog_full_assert_cfg",
+			PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4420,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ese_rsp_afifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ese_rsp_afifo_prog_full_negate_cfg",
+			PPU_CLUSTER_ESE_RSP_AFIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4430,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ese_rsp_afifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ise_rsp_afifo_prog_full_assert_cfg",
+			PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4440,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ise_rsp_afifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ise_rsp_afifo_prog_full_negate_cfg",
+			PPU_CLUSTER_ISE_RSP_AFIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4450,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ise_rsp_afifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sta_rsp_afifo_prog_full_assert_cfg",
+			PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4460,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_sta_rsp_afifo_prog_full_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sta_rsp_afifo_prog_full_negate_cfg",
+			PPU_CLUSTER_STA_RSP_AFIFO_PROG_FULL_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4470,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_sta_rsp_afifo_prog_full_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_ise_key_afifo_prog_empty_assert_cfg",
+			PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4480,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_ise_key_afifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_ise_key_afifo_prog_empty_negate_cfg",
+			PPU_CLUSTER_PPU_ISE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x4490,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_ise_key_afifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_ese_key_afifo_prog_empty_assert_cfg",
+			PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x44a0,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_ese_key_afifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_ese_key_afifo_prog_empty_negate_cfg",
+			PPU_CLUSTER_PPU_ESE_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x44b0,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_ese_key_afifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_sta_key_afifo_prog_empty_assert_cfg",
+			PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_ASSERT_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x44c0,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_sta_key_afifo_prog_empty_assert_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_sta_key_afifo_prog_empty_negate_cfg",
+			PPU_CLUSTER_PPU_STA_KEY_AFIFO_PROG_EMPTY_NEGATE_CFGr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x44d0,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_sta_key_afifo_prog_empty_negate_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cluster_mf_vld_cnt_h",
+			PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6000,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_cluster_mf_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_cluster_mf_vld_cnt_l",
+			PPU_CLUSTER_PPU_CLUSTER_MF_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6004,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ppu_cluster_mf_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cluster_ise_key_out_vld_cnt",
+			PPU_CLUSTER_CLUSTER_ISE_KEY_OUT_VLD_CNTr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6008,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_cluster_ise_key_out_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ise_cluster_rsp_in_vld_cnt",
+			PPU_CLUSTER_ISE_CLUSTER_RSP_IN_VLD_CNTr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x600c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ise_cluster_rsp_in_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cluster_ese_key_out_vld_cnt",
+			PPU_CLUSTER_CLUSTER_ESE_KEY_OUT_VLD_CNTr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6010,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_cluster_ese_key_out_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ese_cluster_rsp_in_vld_cnt",
+			PPU_CLUSTER_ESE_CLUSTER_RSP_IN_VLD_CNTr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6014,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ese_cluster_rsp_in_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cluster_stat_cmd_vld_cnt",
+			PPU_CLUSTER_CLUSTER_STAT_CMD_VLD_CNTr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6018,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_cluster_stat_cmd_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_cluster_rsp_vld_cnt",
+			PPU_CLUSTER_STAT_CLUSTER_RSP_VLD_CNTr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x601c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_stat_cluster_rsp_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex_debug_key_vld_cnt",
+			PPU_CLUSTER_MEX_DEBUG_KEY_VLD_CNTr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6020,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_mex_debug_key_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ise_cluster_key_fc_cnt",
+			PPU_CLUSTER_ISE_CLUSTER_KEY_FC_CNTr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6024,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ise_cluster_key_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ese_cluster_key_fc_cnt",
+			PPU_CLUSTER_ESE_CLUSTER_KEY_FC_CNTr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6028,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_ese_cluster_key_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cluster_ise_rsp_fc_cnt",
+			PPU_CLUSTER_CLUSTER_ISE_RSP_FC_CNTr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x602c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_cluster_ise_rsp_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cluster_ese_rsp_fc_cnt",
+			PPU_CLUSTER_CLUSTER_ESE_RSP_FC_CNTr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6030,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_cluster_ese_rsp_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_cluster_cmd_fc_cnt",
+			PPU_CLUSTER_STAT_CLUSTER_CMD_FC_CNTr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6034,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_stat_cluster_cmd_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cluster_stat_rsp_fc_cnt",
+			PPU_CLUSTER_CLUSTER_STAT_RSP_FC_CNTr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x6038,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_cluster_stat_rsp_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cluster_ppu_mf_vld_cnt_l",
+			PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2000,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_cluster_ppu_mf_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cluster_ppu_mf_vld_cnt_h",
+			PPU_CLUSTER_CLUSTER_PPU_MF_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2004,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_cluster_ppu_mf_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cluster_cop_key_vld_cnt_l",
+			PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2008,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_cluster_cop_key_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cluster_cop_key_vld_cnt_h",
+			PPU_CLUSTER_CLUSTER_COP_KEY_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x200c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_cluster_cop_key_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cop_cluster_rsp_vld_cnt_l",
+			PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2010,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_cop_cluster_rsp_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cop_cluster_rsp_vld_cnt_h",
+			PPU_CLUSTER_COP_CLUSTER_RSP_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2014,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			0,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			0,
+			1,
+			g_ppu_cluster_cop_cluster_rsp_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex_me_pkt_in_sop_cnt_l",
+			PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2018,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_mex_me_pkt_in_sop_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex_me_pkt_in_sop_cnt_h",
+			PPU_CLUSTER_MEX_ME_PKT_IN_SOP_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x201c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_mex_me_pkt_in_sop_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex_me_pkt_in_eop_cnt_l",
+			PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2020,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_mex_me_pkt_in_eop_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex_me_pkt_in_eop_cnt_h",
+			PPU_CLUSTER_MEX_ME_PKT_IN_EOP_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2024,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_mex_me_pkt_in_eop_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex_me_pkt_in_vld_cnt_l",
+			PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2028,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_mex_me_pkt_in_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex_me_pkt_in_vld_cnt_h",
+			PPU_CLUSTER_MEX_ME_PKT_IN_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x202c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_mex_me_pkt_in_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_pkt_out_sop_cnt_l",
+			PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20d8,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_pkt_out_sop_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_pkt_out_sop_cnt_h",
+			PPU_CLUSTER_ME_MEX_PKT_OUT_SOP_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20dc,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_pkt_out_sop_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_pkt_out_eop_cnt_l",
+			PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20e0,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_pkt_out_eop_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_pkt_out_eop_cnt_h",
+			PPU_CLUSTER_ME_MEX_PKT_OUT_EOP_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20e4,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_pkt_out_eop_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_pkt_out_vld_cnt_l",
+			PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20e8,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_pkt_out_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_pkt_out_vld_cnt_h",
+			PPU_CLUSTER_ME_MEX_PKT_OUT_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x20ec,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_pkt_out_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_i_key_out_sop_cnt_l",
+			PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2198,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_i_key_out_sop_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_i_key_out_sop_cnt_h",
+			PPU_CLUSTER_ME_MEX_I_KEY_OUT_SOP_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x219c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_i_key_out_sop_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_i_key_out_eop_cnt_l",
+			PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x21a0,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_i_key_out_eop_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_i_key_out_eop_cnt_h",
+			PPU_CLUSTER_ME_MEX_I_KEY_OUT_EOP_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x21a4,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_i_key_out_eop_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_i_key_out_vld_cnt_l",
+			PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x21a8,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_i_key_out_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_i_key_out_vld_cnt_h",
+			PPU_CLUSTER_ME_MEX_I_KEY_OUT_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x21ac,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_i_key_out_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_e_key_out_sop_cnt_l",
+			PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2258,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_e_key_out_sop_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_e_key_out_sop_cnt_h",
+			PPU_CLUSTER_ME_MEX_E_KEY_OUT_SOP_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x225c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_e_key_out_sop_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_e_key_out_eop_cnt_l",
+			PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2260,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_e_key_out_eop_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_e_key_out_eop_cnt_h",
+			PPU_CLUSTER_ME_MEX_E_KEY_OUT_EOP_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2264,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_e_key_out_eop_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_e_key_out_vld_cnt_l",
+			PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2268,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_e_key_out_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_e_key_out_vld_cnt_h",
+			PPU_CLUSTER_ME_MEX_E_KEY_OUT_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x226c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_mex_e_key_out_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_demux_ise_key_vld_cnt_l",
+			PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2318,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			8,
+			1,
+			g_ppu_cluster_me_mex_demux_ise_key_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_demux_ise_key_vld_cnt_h",
+			PPU_CLUSTER_ME_MEX_DEMUX_ISE_KEY_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x231c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			8,
+			1,
+			g_ppu_cluster_me_mex_demux_ise_key_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_demux_ese_key_vld_cnt_l",
+			PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2358,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			8,
+			1,
+			g_ppu_cluster_me_mex_demux_ese_key_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_demux_ese_key_vld_cnt_h",
+			PPU_CLUSTER_ME_MEX_DEMUX_ESE_KEY_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x235c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			8,
+			1,
+			g_ppu_cluster_me_mex_demux_ese_key_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_demux_sta_key_vld_cnt_l",
+			PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2398,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			8,
+			1,
+			g_ppu_cluster_me_mex_demux_sta_key_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_demux_sta_key_vld_cnt_h",
+			PPU_CLUSTER_ME_MEX_DEMUX_STA_KEY_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x239c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			8,
+			1,
+			g_ppu_cluster_me_mex_demux_sta_key_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_demux_cop_key_vld_cnt_l",
+			PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x23d8,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			8,
+			1,
+			g_ppu_cluster_me_mex_demux_cop_key_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_mex_demux_cop_key_vld_cnt_h",
+			PPU_CLUSTER_ME_MEX_DEMUX_COP_KEY_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x23dc,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			8,
+			1,
+			g_ppu_cluster_me_mex_demux_cop_key_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex_me_demux_ise_rsp_vld_cnt_l",
+			PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2418,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			8,
+			1,
+			g_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex_me_demux_ise_rsp_vld_cnt_h",
+			PPU_CLUSTER_MEX_ME_DEMUX_ISE_RSP_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x241c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			8,
+			1,
+			g_ppu_cluster_mex_me_demux_ise_rsp_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex_me_demux_ese_rsp_vld_cnt_l",
+			PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2458,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			8,
+			1,
+			g_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex_me_demux_ese_rsp_vld_cnt_h",
+			PPU_CLUSTER_MEX_ME_DEMUX_ESE_RSP_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x245c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			8,
+			1,
+			g_ppu_cluster_mex_me_demux_ese_rsp_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex_me_demux_sta_rsp_vld_cnt_l",
+			PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2498,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			8,
+			1,
+			g_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex_me_demux_sta_rsp_vld_cnt_h",
+			PPU_CLUSTER_MEX_ME_DEMUX_STA_RSP_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x249c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			8,
+			1,
+			g_ppu_cluster_mex_me_demux_sta_rsp_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex_me_demux_cop_rsp_vld_cnt_l",
+			PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x24d8,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			8,
+			1,
+			g_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex_me_demux_cop_rsp_vld_cnt_h",
+			PPU_CLUSTER_MEX_ME_DEMUX_COP_RSP_VLD_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x24dc,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			8,
+			1,
+			g_ppu_cluster_mex_me_demux_cop_rsp_vld_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_exception_code0_cnt_l",
+			PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2518,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_exception_code0_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_exception_code0_cnt_h",
+			PPU_CLUSTER_ME_EXCEPTION_CODE0_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x251c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_exception_code0_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_exception_code1_cnt_l",
+			PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2520,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_exception_code1_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_exception_code1_cnt_h",
+			PPU_CLUSTER_ME_EXCEPTION_CODE1_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2524,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_exception_code1_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_exception_code2_cnt_l",
+			PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x2528,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_exception_code2_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_exception_code2_cnt_h",
+			PPU_CLUSTER_ME_EXCEPTION_CODE2_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x252c,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_exception_code2_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_exception_code3_cnt_l",
+			PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25d8,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_exception_code3_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_exception_code3_cnt_h",
+			PPU_CLUSTER_ME_EXCEPTION_CODE3_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25dc,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_exception_code3_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_exception_code4_cnt_l",
+			PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25e0,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_exception_code4_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_exception_code4_cnt_h",
+			PPU_CLUSTER_ME_EXCEPTION_CODE4_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25e4,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_exception_code4_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_exception_code5_cnt_l",
+			PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_Lr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25e8,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_exception_code5_cnt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"me_exception_code5_cnt_h",
+			PPU_CLUSTER_ME_EXCEPTION_CODE5_CNT_Hr,
+			PPU,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_PPU_BASE_ADDR + MODULE_CLUSTER0_BASE_ADDR + 0x25ec,
+			(32 / 8),
+			DPP_PPU_CLUSTER_NUM,
+			7 + 1,
+			DPP_PPU_CLUSTER_SPACE_SIZE,
+			24,
+			1,
+			g_ppu_cluster_me_exception_code5_cnt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_soft_rst",
+			SE_CFG_PPU_SOFT_RSTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_ppu_soft_rst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ept_flag",
+			SE_CFG_EPT_FLAGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_ept_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_key_lk0_3",
+			SE_CFG_DDR_KEY_LK0_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_ddr_key_lk0_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_key_lk0_2",
+			SE_CFG_DDR_KEY_LK0_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_ddr_key_lk0_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_key_lk0_1",
+			SE_CFG_DDR_KEY_LK0_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_ddr_key_lk0_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_key_lk0_0",
+			SE_CFG_DDR_KEY_LK0_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000002c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_ddr_key_lk0_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_key_lk1_3",
+			SE_CFG_DDR_KEY_LK1_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_ddr_key_lk1_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_key_lk1_2",
+			SE_CFG_DDR_KEY_LK1_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_ddr_key_lk1_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_key_lk1_1",
+			SE_CFG_DDR_KEY_LK1_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_ddr_key_lk1_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_key_lk1_0",
+			SE_CFG_DDR_KEY_LK1_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000003c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_ddr_key_lk1_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_18",
+			SE_CFG_HASH_KEY_LK0_18r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_17",
+			SE_CFG_HASH_KEY_LK0_17r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_16",
+			SE_CFG_HASH_KEY_LK0_16r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_15",
+			SE_CFG_HASH_KEY_LK0_15r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000008c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_14",
+			SE_CFG_HASH_KEY_LK0_14r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_13",
+			SE_CFG_HASH_KEY_LK0_13r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_12",
+			SE_CFG_HASH_KEY_LK0_12r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000098,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_11",
+			SE_CFG_HASH_KEY_LK0_11r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000009c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_10",
+			SE_CFG_HASH_KEY_LK0_10r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_9",
+			SE_CFG_HASH_KEY_LK0_9r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_8",
+			SE_CFG_HASH_KEY_LK0_8r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_7",
+			SE_CFG_HASH_KEY_LK0_7r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_6",
+			SE_CFG_HASH_KEY_LK0_6r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_5",
+			SE_CFG_HASH_KEY_LK0_5r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_4",
+			SE_CFG_HASH_KEY_LK0_4r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_3",
+			SE_CFG_HASH_KEY_LK0_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_2",
+			SE_CFG_HASH_KEY_LK0_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_1",
+			SE_CFG_HASH_KEY_LK0_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk0_0",
+			SE_CFG_HASH_KEY_LK0_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk0_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_18",
+			SE_CFG_HASH_KEY_LK1_18r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_17",
+			SE_CFG_HASH_KEY_LK1_17r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_16",
+			SE_CFG_HASH_KEY_LK1_16r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_15",
+			SE_CFG_HASH_KEY_LK1_15r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_14",
+			SE_CFG_HASH_KEY_LK1_14r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_13",
+			SE_CFG_HASH_KEY_LK1_13r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_12",
+			SE_CFG_HASH_KEY_LK1_12r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_11",
+			SE_CFG_HASH_KEY_LK1_11r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_10",
+			SE_CFG_HASH_KEY_LK1_10r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_9",
+			SE_CFG_HASH_KEY_LK1_9r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_8",
+			SE_CFG_HASH_KEY_LK1_8r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_7",
+			SE_CFG_HASH_KEY_LK1_7r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_6",
+			SE_CFG_HASH_KEY_LK1_6r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000000fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_5",
+			SE_CFG_HASH_KEY_LK1_5r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000100,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_4",
+			SE_CFG_HASH_KEY_LK1_4r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000104,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_3",
+			SE_CFG_HASH_KEY_LK1_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000108,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_2",
+			SE_CFG_HASH_KEY_LK1_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000010c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_1",
+			SE_CFG_HASH_KEY_LK1_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000110,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk1_0",
+			SE_CFG_HASH_KEY_LK1_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000114,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk1_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_18",
+			SE_CFG_HASH_KEY_LK2_18r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000118,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_17",
+			SE_CFG_HASH_KEY_LK2_17r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000011c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_16",
+			SE_CFG_HASH_KEY_LK2_16r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000120,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_15",
+			SE_CFG_HASH_KEY_LK2_15r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000124,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_14",
+			SE_CFG_HASH_KEY_LK2_14r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000128,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_13",
+			SE_CFG_HASH_KEY_LK2_13r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000012c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_12",
+			SE_CFG_HASH_KEY_LK2_12r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000130,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_11",
+			SE_CFG_HASH_KEY_LK2_11r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000134,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_10",
+			SE_CFG_HASH_KEY_LK2_10r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000138,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_9",
+			SE_CFG_HASH_KEY_LK2_9r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000013c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_8",
+			SE_CFG_HASH_KEY_LK2_8r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000140,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_7",
+			SE_CFG_HASH_KEY_LK2_7r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000144,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_6",
+			SE_CFG_HASH_KEY_LK2_6r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000148,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_5",
+			SE_CFG_HASH_KEY_LK2_5r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000014c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_4",
+			SE_CFG_HASH_KEY_LK2_4r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000150,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_3",
+			SE_CFG_HASH_KEY_LK2_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000154,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_2",
+			SE_CFG_HASH_KEY_LK2_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000158,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_1",
+			SE_CFG_HASH_KEY_LK2_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000015c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk2_0",
+			SE_CFG_HASH_KEY_LK2_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000160,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk2_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_18",
+			SE_CFG_HASH_KEY_LK3_18r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000164,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_17",
+			SE_CFG_HASH_KEY_LK3_17r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000168,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_16",
+			SE_CFG_HASH_KEY_LK3_16r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000016c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_15",
+			SE_CFG_HASH_KEY_LK3_15r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000170,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_14",
+			SE_CFG_HASH_KEY_LK3_14r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000174,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_13",
+			SE_CFG_HASH_KEY_LK3_13r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000178,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_12",
+			SE_CFG_HASH_KEY_LK3_12r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000017c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_11",
+			SE_CFG_HASH_KEY_LK3_11r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000180,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_10",
+			SE_CFG_HASH_KEY_LK3_10r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000184,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_9",
+			SE_CFG_HASH_KEY_LK3_9r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000188,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_8",
+			SE_CFG_HASH_KEY_LK3_8r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000018c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_7",
+			SE_CFG_HASH_KEY_LK3_7r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000190,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_6",
+			SE_CFG_HASH_KEY_LK3_6r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000194,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_5",
+			SE_CFG_HASH_KEY_LK3_5r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000198,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_4",
+			SE_CFG_HASH_KEY_LK3_4r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000019c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_3",
+			SE_CFG_HASH_KEY_LK3_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000001a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_2",
+			SE_CFG_HASH_KEY_LK3_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000001a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_1",
+			SE_CFG_HASH_KEY_LK3_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000001a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key_lk3_0",
+			SE_CFG_HASH_KEY_LK3_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000001ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_hash_key_lk3_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk0_6",
+			SE_CFG_LPM_KEY_LK0_6r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk0_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk0_5",
+			SE_CFG_LPM_KEY_LK0_5r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk0_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk0_4",
+			SE_CFG_LPM_KEY_LK0_4r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk0_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk0_3",
+			SE_CFG_LPM_KEY_LK0_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk0_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk0_2",
+			SE_CFG_LPM_KEY_LK0_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk0_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk0_1",
+			SE_CFG_LPM_KEY_LK0_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk0_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk0_0",
+			SE_CFG_LPM_KEY_LK0_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk0_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk1_6",
+			SE_CFG_LPM_KEY_LK1_6r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000002fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk1_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk1_5",
+			SE_CFG_LPM_KEY_LK1_5r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000300,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk1_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk1_4",
+			SE_CFG_LPM_KEY_LK1_4r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000304,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk1_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk1_3",
+			SE_CFG_LPM_KEY_LK1_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000308,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk1_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk1_2",
+			SE_CFG_LPM_KEY_LK1_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000030c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk1_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk1_1",
+			SE_CFG_LPM_KEY_LK1_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000310,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk1_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk1_0",
+			SE_CFG_LPM_KEY_LK1_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000314,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk1_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk2_6",
+			SE_CFG_LPM_KEY_LK2_6r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000318,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk2_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk2_5",
+			SE_CFG_LPM_KEY_LK2_5r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000031c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk2_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk2_4",
+			SE_CFG_LPM_KEY_LK2_4r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000320,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk2_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk2_3",
+			SE_CFG_LPM_KEY_LK2_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000324,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk2_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk2_2",
+			SE_CFG_LPM_KEY_LK2_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000328,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk2_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk2_1",
+			SE_CFG_LPM_KEY_LK2_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000032c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk2_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk2_0",
+			SE_CFG_LPM_KEY_LK2_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000330,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk2_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk3_6",
+			SE_CFG_LPM_KEY_LK3_6r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000334,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk3_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk3_5",
+			SE_CFG_LPM_KEY_LK3_5r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000338,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk3_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk3_4",
+			SE_CFG_LPM_KEY_LK3_4r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000033c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk3_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk3_3",
+			SE_CFG_LPM_KEY_LK3_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000340,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk3_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk3_2",
+			SE_CFG_LPM_KEY_LK3_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000344,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk3_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk3_1",
+			SE_CFG_LPM_KEY_LK3_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000348,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk3_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_key_lk3_0",
+			SE_CFG_LPM_KEY_LK3_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000034c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_lpm_key_lk3_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_22",
+			SE_CFG_ETCAM_KEY_LK0_22r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_22_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_21",
+			SE_CFG_ETCAM_KEY_LK0_21r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_21_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_20",
+			SE_CFG_ETCAM_KEY_LK0_20r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_20_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_19",
+			SE_CFG_ETCAM_KEY_LK0_19r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_19_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_18",
+			SE_CFG_ETCAM_KEY_LK0_18r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_17",
+			SE_CFG_ETCAM_KEY_LK0_17r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_16",
+			SE_CFG_ETCAM_KEY_LK0_16r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_15",
+			SE_CFG_ETCAM_KEY_LK0_15r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_14",
+			SE_CFG_ETCAM_KEY_LK0_14r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_13",
+			SE_CFG_ETCAM_KEY_LK0_13r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_12",
+			SE_CFG_ETCAM_KEY_LK0_12r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_11",
+			SE_CFG_ETCAM_KEY_LK0_11r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_10",
+			SE_CFG_ETCAM_KEY_LK0_10r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_9",
+			SE_CFG_ETCAM_KEY_LK0_9r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_8",
+			SE_CFG_ETCAM_KEY_LK0_8r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_7",
+			SE_CFG_ETCAM_KEY_LK0_7r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000003fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_6",
+			SE_CFG_ETCAM_KEY_LK0_6r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000400,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_5",
+			SE_CFG_ETCAM_KEY_LK0_5r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000404,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_4",
+			SE_CFG_ETCAM_KEY_LK0_4r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000408,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_3",
+			SE_CFG_ETCAM_KEY_LK0_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000040c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_2",
+			SE_CFG_ETCAM_KEY_LK0_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000410,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_1",
+			SE_CFG_ETCAM_KEY_LK0_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000414,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk0_0",
+			SE_CFG_ETCAM_KEY_LK0_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000418,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk0_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_22",
+			SE_CFG_ETCAM_KEY_LK1_22r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000041c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_22_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_21",
+			SE_CFG_ETCAM_KEY_LK1_21r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000420,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_21_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_20",
+			SE_CFG_ETCAM_KEY_LK1_20r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000424,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_20_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_19",
+			SE_CFG_ETCAM_KEY_LK1_19r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000428,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_19_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_18",
+			SE_CFG_ETCAM_KEY_LK1_18r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000042c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_17",
+			SE_CFG_ETCAM_KEY_LK1_17r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000430,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_16",
+			SE_CFG_ETCAM_KEY_LK1_16r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000434,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_15",
+			SE_CFG_ETCAM_KEY_LK1_15r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000438,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_14",
+			SE_CFG_ETCAM_KEY_LK1_14r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000043c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_13",
+			SE_CFG_ETCAM_KEY_LK1_13r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000440,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_12",
+			SE_CFG_ETCAM_KEY_LK1_12r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000444,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_11",
+			SE_CFG_ETCAM_KEY_LK1_11r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000448,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_10",
+			SE_CFG_ETCAM_KEY_LK1_10r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000044c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_9",
+			SE_CFG_ETCAM_KEY_LK1_9r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000450,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_8",
+			SE_CFG_ETCAM_KEY_LK1_8r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000454,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_7",
+			SE_CFG_ETCAM_KEY_LK1_7r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000458,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_6",
+			SE_CFG_ETCAM_KEY_LK1_6r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000045c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_5",
+			SE_CFG_ETCAM_KEY_LK1_5r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000460,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_4",
+			SE_CFG_ETCAM_KEY_LK1_4r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000464,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_3",
+			SE_CFG_ETCAM_KEY_LK1_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000468,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_2",
+			SE_CFG_ETCAM_KEY_LK1_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000046c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_1",
+			SE_CFG_ETCAM_KEY_LK1_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000470,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk1_0",
+			SE_CFG_ETCAM_KEY_LK1_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000474,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk1_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_22",
+			SE_CFG_ETCAM_KEY_LK2_22r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000478,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_22_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_21",
+			SE_CFG_ETCAM_KEY_LK2_21r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000047c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_21_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_20",
+			SE_CFG_ETCAM_KEY_LK2_20r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000480,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_20_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_19",
+			SE_CFG_ETCAM_KEY_LK2_19r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000484,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_19_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_18",
+			SE_CFG_ETCAM_KEY_LK2_18r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000488,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_17",
+			SE_CFG_ETCAM_KEY_LK2_17r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000048c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_16",
+			SE_CFG_ETCAM_KEY_LK2_16r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000490,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_15",
+			SE_CFG_ETCAM_KEY_LK2_15r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000494,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_14",
+			SE_CFG_ETCAM_KEY_LK2_14r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000498,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_13",
+			SE_CFG_ETCAM_KEY_LK2_13r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000049c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_12",
+			SE_CFG_ETCAM_KEY_LK2_12r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_11",
+			SE_CFG_ETCAM_KEY_LK2_11r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_10",
+			SE_CFG_ETCAM_KEY_LK2_10r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_9",
+			SE_CFG_ETCAM_KEY_LK2_9r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_8",
+			SE_CFG_ETCAM_KEY_LK2_8r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_7",
+			SE_CFG_ETCAM_KEY_LK2_7r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_6",
+			SE_CFG_ETCAM_KEY_LK2_6r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_5",
+			SE_CFG_ETCAM_KEY_LK2_5r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_4",
+			SE_CFG_ETCAM_KEY_LK2_4r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_3",
+			SE_CFG_ETCAM_KEY_LK2_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_2",
+			SE_CFG_ETCAM_KEY_LK2_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_1",
+			SE_CFG_ETCAM_KEY_LK2_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk2_0",
+			SE_CFG_ETCAM_KEY_LK2_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk2_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_22",
+			SE_CFG_ETCAM_KEY_LK3_22r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_22_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_21",
+			SE_CFG_ETCAM_KEY_LK3_21r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_21_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_20",
+			SE_CFG_ETCAM_KEY_LK3_20r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_20_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_19",
+			SE_CFG_ETCAM_KEY_LK3_19r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_19_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_18",
+			SE_CFG_ETCAM_KEY_LK3_18r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_17",
+			SE_CFG_ETCAM_KEY_LK3_17r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_16",
+			SE_CFG_ETCAM_KEY_LK3_16r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_15",
+			SE_CFG_ETCAM_KEY_LK3_15r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_14",
+			SE_CFG_ETCAM_KEY_LK3_14r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_13",
+			SE_CFG_ETCAM_KEY_LK3_13r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_12",
+			SE_CFG_ETCAM_KEY_LK3_12r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000004fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_11",
+			SE_CFG_ETCAM_KEY_LK3_11r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000500,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_10",
+			SE_CFG_ETCAM_KEY_LK3_10r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000504,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_9",
+			SE_CFG_ETCAM_KEY_LK3_9r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000508,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_8",
+			SE_CFG_ETCAM_KEY_LK3_8r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000050c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_7",
+			SE_CFG_ETCAM_KEY_LK3_7r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000510,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_6",
+			SE_CFG_ETCAM_KEY_LK3_6r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000514,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_5",
+			SE_CFG_ETCAM_KEY_LK3_5r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000518,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_4",
+			SE_CFG_ETCAM_KEY_LK3_4r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000051c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_3",
+			SE_CFG_ETCAM_KEY_LK3_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000520,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_2",
+			SE_CFG_ETCAM_KEY_LK3_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000524,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_1",
+			SE_CFG_ETCAM_KEY_LK3_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x00000528,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_key_lk3_0",
+			SE_CFG_ETCAM_KEY_LK3_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x0000052c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_etcam_key_lk3_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_key_lk0_3",
+			SE_CFG_PBU_KEY_LK0_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_pbu_key_lk0_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_key_lk0_2",
+			SE_CFG_PBU_KEY_LK0_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_pbu_key_lk0_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_key_lk0_1",
+			SE_CFG_PBU_KEY_LK0_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_pbu_key_lk0_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_key_lk0_0",
+			SE_CFG_PBU_KEY_LK0_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_pbu_key_lk0_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_key_lk1_3",
+			SE_CFG_PBU_KEY_LK1_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_pbu_key_lk1_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_key_lk1_2",
+			SE_CFG_PBU_KEY_LK1_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_pbu_key_lk1_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_key_lk1_1",
+			SE_CFG_PBU_KEY_LK1_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_pbu_key_lk1_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_key_lk1_0",
+			SE_CFG_PBU_KEY_LK1_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_pbu_key_lk1_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_key_lk2_3",
+			SE_CFG_PBU_KEY_LK2_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_pbu_key_lk2_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_key_lk2_2",
+			SE_CFG_PBU_KEY_LK2_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_pbu_key_lk2_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_key_lk2_1",
+			SE_CFG_PBU_KEY_LK2_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_pbu_key_lk2_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_key_lk2_0",
+			SE_CFG_PBU_KEY_LK2_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_pbu_key_lk2_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_key_lk3_3",
+			SE_CFG_PBU_KEY_LK3_3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_pbu_key_lk3_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_key_lk3_2",
+			SE_CFG_PBU_KEY_LK3_2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_pbu_key_lk3_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_key_lk3_1",
+			SE_CFG_PBU_KEY_LK3_1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_pbu_key_lk3_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_key_lk3_0",
+			SE_CFG_PBU_KEY_LK3_0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_CFG_BASE_ADDR + 0x000006dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cfg_pbu_key_lk3_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_learn_fifo_pfull_ast",
+			SE_ALG_SCHD_LEARN_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x008c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_learn_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_learn_fifo_pfull_neg",
+			SE_ALG_SCHD_LEARN_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_learn_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_hash0_fifo_pfull_ast",
+			SE_ALG_SCHD_HASH0_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_hash0_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_hash0_fifo_pfull_neg",
+			SE_ALG_SCHD_HASH0_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0098,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_hash0_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_hash1_fifo_pfull_ast",
+			SE_ALG_SCHD_HASH1_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x009c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_hash1_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_hash1_fifo_pfull_neg",
+			SE_ALG_SCHD_HASH1_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_hash1_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_hash2_fifo_pfull_ast",
+			SE_ALG_SCHD_HASH2_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_hash2_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_hash2_fifo_pfull_neg",
+			SE_ALG_SCHD_HASH2_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_hash2_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_hash3_fifo_pfull_ast",
+			SE_ALG_SCHD_HASH3_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_hash3_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_hash3_fifo_pfull_neg",
+			SE_ALG_SCHD_HASH3_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_hash3_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_lpm_fifo_pfull_ast",
+			SE_ALG_SCHD_LPM_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_lpm_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_lpm_fifo_pfull_neg",
+			SE_ALG_SCHD_LPM_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_lpm_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_key_fifo_pfull_ast",
+			SE_ALG_HASH0_KEY_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_key_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_key_fifo_pfull_neg",
+			SE_ALG_HASH0_KEY_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_key_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_sreq_fifo_pfull_ast",
+			SE_ALG_HASH0_SREQ_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_sreq_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_sreq_fifo_pfull_neg",
+			SE_ALG_HASH0_SREQ_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_sreq_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_int_rsp_fifo_pfull_ast",
+			SE_ALG_HASH0_INT_RSP_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_int_rsp_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_int_rsp_fifo_pfull_neg",
+			SE_ALG_HASH0_INT_RSP_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_int_rsp_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_ext_rsp_fifo_pfull_ast",
+			SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_ext_rsp_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_ext_rsp_fifo_pfull_neg",
+			SE_ALG_HASH0_EXT_RSP_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_ext_rsp_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_key_fifo_pfull_ast",
+			SE_ALG_HASH1_KEY_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_key_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_key_fifo_pfull_neg",
+			SE_ALG_HASH1_KEY_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_key_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_sreq_fifo_pfull_ast",
+			SE_ALG_HASH1_SREQ_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_sreq_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_sreq_fifo_pfull_neg",
+			SE_ALG_HASH1_SREQ_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_sreq_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_int_rsp_fifo_pfull_ast",
+			SE_ALG_HASH1_INT_RSP_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_int_rsp_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_int_rsp_fifo_pfull_neg",
+			SE_ALG_HASH1_INT_RSP_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0100,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_int_rsp_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_ext_rsp_fifo_pfull_ast",
+			SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0104,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_ext_rsp_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_ext_rsp_fifo_pfull_neg",
+			SE_ALG_HASH1_EXT_RSP_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0108,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_ext_rsp_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_key_fifo_pfull_ast",
+			SE_ALG_HASH2_KEY_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x010c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_key_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_key_fifo_pfull_neg",
+			SE_ALG_HASH2_KEY_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0110,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_key_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_sreq_fifo_pfull_ast",
+			SE_ALG_HASH2_SREQ_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0114,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_sreq_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_sreq_fifo_pfull_neg",
+			SE_ALG_HASH2_SREQ_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0118,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_sreq_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_int_rsp_fifo_pfull_ast",
+			SE_ALG_HASH2_INT_RSP_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x011c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_int_rsp_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_int_rsp_fifo_pfull_neg",
+			SE_ALG_HASH2_INT_RSP_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0120,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_int_rsp_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_ext_rsp_fifo_pfull_ast",
+			SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0124,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_ext_rsp_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_ext_rsp_fifo_pfull_neg",
+			SE_ALG_HASH2_EXT_RSP_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0128,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_ext_rsp_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_key_fifo_pfull_ast",
+			SE_ALG_HASH3_KEY_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x012c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_key_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_key_fifo_pfull_neg",
+			SE_ALG_HASH3_KEY_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0130,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_key_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_sreq_fifo_pfull_ast",
+			SE_ALG_HASH3_SREQ_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0134,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_sreq_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_sreq_fifo_pfull_neg",
+			SE_ALG_HASH3_SREQ_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0138,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_sreq_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_int_rsp_fifo_pfull_ast",
+			SE_ALG_HASH3_INT_RSP_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x013c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_int_rsp_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_int_rsp_fifo_pfull_neg",
+			SE_ALG_HASH3_INT_RSP_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0140,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_int_rsp_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_ext_rsp_fifo_pfull_ast",
+			SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0144,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_ext_rsp_fifo_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_ext_rsp_fifo_pfull_neg",
+			SE_ALG_HASH3_EXT_RSP_FIFO_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0148,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_ext_rsp_fifo_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_as_info",
+			SE_ALG_LPM_AS_INFOr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0158,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_alg_lpm_as_info_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_ext_rsp_fifo_u0_pfull_neg",
+			SE_ALG_LPM_EXT_RSP_FIFO_U0_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0160,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_ext_rsp_fifo_u0_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_ext_rsp_fifo_u2_pfull_ast",
+			SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x016c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_ext_rsp_fifo_u2_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_ext_rsp_fifo_u2_pfull_neg",
+			SE_ALG_LPM_EXT_RSP_FIFO_U2_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0170,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_ext_rsp_fifo_u2_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_ext_rsp_fifo_u3_pfull_ast",
+			SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0174,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_ext_rsp_fifo_u3_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_ext_rsp_fifo_u3_pfull_neg",
+			SE_ALG_LPM_EXT_RSP_FIFO_U3_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0178,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_ext_rsp_fifo_u3_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_ext_rsp_fifo_u4_pfull_ast",
+			SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x017c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_ext_rsp_fifo_u4_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_ext_rsp_fifo_u4_pfull_neg",
+			SE_ALG_LPM_EXT_RSP_FIFO_U4_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0180,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_ext_rsp_fifo_u4_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_as_rsp_fifo_u0_pfull_ast",
+			SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x018c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_as_rsp_fifo_u0_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_as_rsp_fifo_u0_pfull_neg",
+			SE_ALG_LPM_AS_RSP_FIFO_U0_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0190,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_as_rsp_fifo_u0_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_as_rsp_fifo_u1_pfull_ast",
+			SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_ASTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0194,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_as_rsp_fifo_u1_pfull_ast_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_as_rsp_fifo_u1_pfull_neg",
+			SE_ALG_LPM_AS_RSP_FIFO_U1_PFULL_NEGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x0198,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_as_rsp_fifo_u1_pfull_neg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_v4_ddr3_base_addr",
+			SE_ALG_LPM_V4_DDR3_BASE_ADDRr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x019c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_v4_ddr3_base_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_v6_ddr3_base_addr",
+			SE_ALG_LPM_V6_DDR3_BASE_ADDRr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_v6_ddr3_base_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_mode",
+			SE_ALG_DEBUG_CNT_MODEr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x01d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_alg_debug_cnt_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_p0_key_vld_cnt",
+			SE_ALG_HASH_P0_KEY_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash_p0_key_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_p1_key_vld_cnt",
+			SE_ALG_HASH_P1_KEY_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash_p1_key_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_p2_key_vld_cnt",
+			SE_ALG_HASH_P2_KEY_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash_p2_key_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_p3_key_vld_cnt",
+			SE_ALG_HASH_P3_KEY_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x100c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash_p3_key_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_p0_key_vld_cnt",
+			SE_ALG_LPM_P0_KEY_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_p0_key_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_p0_rsp_vld_cnt",
+			SE_ALG_HASH_P0_RSP_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash_p0_rsp_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_p1_rsp_vld_cnt",
+			SE_ALG_HASH_P1_RSP_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash_p1_rsp_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_p2_rsp_vld_cnt",
+			SE_ALG_HASH_P2_RSP_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x101c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash_p2_rsp_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_p3_rsp_vld_cnt",
+			SE_ALG_HASH_P3_RSP_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash_p3_rsp_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_p0_rsp_vld_cnt",
+			SE_ALG_LPM_P0_RSP_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_p0_rsp_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_p0_smf_cnt",
+			SE_ALG_HASH_P0_SMF_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash_p0_smf_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_p1_smf_cnt",
+			SE_ALG_HASH_P1_SMF_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x102c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash_p1_smf_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_p2_smf_cnt",
+			SE_ALG_HASH_P2_SMF_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash_p2_smf_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_p3_smf_cnt",
+			SE_ALG_HASH_P3_SMF_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash_p3_smf_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_p0_smf_cnt",
+			SE_ALG_LPM_P0_SMF_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_p0_smf_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_p0_spacevld_cnt",
+			SE_ALG_HASH_P0_SPACEVLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x103c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash_p0_spacevld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_p1_spacevld_cnt",
+			SE_ALG_HASH_P1_SPACEVLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash_p1_spacevld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_p2_spacevld_cnt",
+			SE_ALG_HASH_P2_SPACEVLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash_p2_spacevld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_p3_spacevld_cnt",
+			SE_ALG_HASH_P3_SPACEVLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash_p3_spacevld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_p0_req_vld_cnt",
+			SE_ALG_SMMU1_P0_REQ_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x104c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_smmu1_p0_req_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_p1_req_vld_cnt",
+			SE_ALG_SMMU1_P1_REQ_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_smmu1_p1_req_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_p2_req_vld_cnt",
+			SE_ALG_SMMU1_P2_REQ_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_smmu1_p2_req_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_p3_req_vld_cnt",
+			SE_ALG_SMMU1_P3_REQ_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_smmu1_p3_req_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_p4_req_vld_cnt",
+			SE_ALG_SMMU1_P4_REQ_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x105c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_smmu1_p4_req_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_p5_req_vld_cnt",
+			SE_ALG_SMMU1_P5_REQ_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_smmu1_p5_req_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_p0_rsp_vld_cnt",
+			SE_ALG_SMMU1_P0_RSP_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_smmu1_p0_rsp_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_p1_rsp_vld_cnt",
+			SE_ALG_SMMU1_P1_RSP_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_smmu1_p1_rsp_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_p2_rsp_vld_cnt",
+			SE_ALG_SMMU1_P2_RSP_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x106c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_smmu1_p2_rsp_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_p3_rsp_vld_cnt",
+			SE_ALG_SMMU1_P3_RSP_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1070,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_smmu1_p3_rsp_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_p4_rsp_vld_cnt",
+			SE_ALG_SMMU1_P4_RSP_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1074,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_smmu1_p4_rsp_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_p5_rsp_vld_cnt",
+			SE_ALG_SMMU1_P5_RSP_VLD_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1078,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_smmu1_p5_rsp_vld_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_learn_fifo_int_cnt",
+			SE_ALG_SCHD_LEARN_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x107c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_learn_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_hash0_fifo_int_cnt",
+			SE_ALG_SCHD_HASH0_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_hash0_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_hash1_fifo_int_cnt",
+			SE_ALG_SCHD_HASH1_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_hash1_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_hash2_fifo_int_cnt",
+			SE_ALG_SCHD_HASH2_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_hash2_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_hash3_fifo_int_cnt",
+			SE_ALG_SCHD_HASH3_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x108c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_hash3_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_lpm_fifo_int_cnt",
+			SE_ALG_SCHD_LPM_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_lpm_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_learn_fifo_parity_err_cnt",
+			SE_ALG_SCHD_LEARN_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_learn_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_hash0_fifo_parity_err_cnt",
+			SE_ALG_SCHD_HASH0_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1098,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_hash0_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_hash1_fifo_parity_err_cnt",
+			SE_ALG_SCHD_HASH1_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x109c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_hash1_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_hash2_fifo_parity_err_cnt",
+			SE_ALG_SCHD_HASH2_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_hash2_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_hash3_fifo_parity_err_cnt",
+			SE_ALG_SCHD_HASH3_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_hash3_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_lpm_fifo_parity_err_cnt",
+			SE_ALG_SCHD_LPM_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_lpm_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rd_init_cft_cnt",
+			SE_ALG_RD_INIT_CFT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_rd_init_cft_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp0_zblk0_ecc_err_cnt",
+			SE_ALG_ZGP0_ZBLK0_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp0_zblk0_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp0_zblk1_ecc_err_cnt",
+			SE_ALG_ZGP0_ZBLK1_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp0_zblk1_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp0_zblk2_ecc_err_cnt",
+			SE_ALG_ZGP0_ZBLK2_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp0_zblk2_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp0_zblk3_ecc_err_cnt",
+			SE_ALG_ZGP0_ZBLK3_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp0_zblk3_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp0_zblk4_ecc_err_cnt",
+			SE_ALG_ZGP0_ZBLK4_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp0_zblk4_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp0_zblk5_ecc_err_cnt",
+			SE_ALG_ZGP0_ZBLK5_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp0_zblk5_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp0_zblk6_ecc_err_cnt",
+			SE_ALG_ZGP0_ZBLK6_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp0_zblk6_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp0_zblk7_ecc_err_cnt",
+			SE_ALG_ZGP0_ZBLK7_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp0_zblk7_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp1_zblk0_ecc_err_cnt",
+			SE_ALG_ZGP1_ZBLK0_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp1_zblk0_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp1_zblk1_ecc_err_cnt",
+			SE_ALG_ZGP1_ZBLK1_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp1_zblk1_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp1_zblk2_ecc_err_cnt",
+			SE_ALG_ZGP1_ZBLK2_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp1_zblk2_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp1_zblk3_ecc_err_cnt",
+			SE_ALG_ZGP1_ZBLK3_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp1_zblk3_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp1_zblk4_ecc_err_cnt",
+			SE_ALG_ZGP1_ZBLK4_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp1_zblk4_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp1_zblk5_ecc_err_cnt",
+			SE_ALG_ZGP1_ZBLK5_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp1_zblk5_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp1_zblk6_ecc_err_cnt",
+			SE_ALG_ZGP1_ZBLK6_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp1_zblk6_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp1_zblk7_ecc_err_cnt",
+			SE_ALG_ZGP1_ZBLK7_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp1_zblk7_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp2_zblk0_ecc_err_cnt",
+			SE_ALG_ZGP2_ZBLK0_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp2_zblk0_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp2_zblk1_ecc_err_cnt",
+			SE_ALG_ZGP2_ZBLK1_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp2_zblk1_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp2_zblk2_ecc_err_cnt",
+			SE_ALG_ZGP2_ZBLK2_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp2_zblk2_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp2_zblk3_ecc_err_cnt",
+			SE_ALG_ZGP2_ZBLK3_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x10fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp2_zblk3_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp2_zblk4_ecc_err_cnt",
+			SE_ALG_ZGP2_ZBLK4_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1100,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp2_zblk4_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp2_zblk5_ecc_err_cnt",
+			SE_ALG_ZGP2_ZBLK5_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1104,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp2_zblk5_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp2_zblk6_ecc_err_cnt",
+			SE_ALG_ZGP2_ZBLK6_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1108,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp2_zblk6_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp2_zblk7_ecc_err_cnt",
+			SE_ALG_ZGP2_ZBLK7_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x110c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp2_zblk7_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp3_zblk0_ecc_err_cnt",
+			SE_ALG_ZGP3_ZBLK0_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1110,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp3_zblk0_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp3_zblk1_ecc_err_cnt",
+			SE_ALG_ZGP3_ZBLK1_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1114,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp3_zblk1_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp3_zblk2_ecc_err_cnt",
+			SE_ALG_ZGP3_ZBLK2_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1118,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp3_zblk2_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp3_zblk3_ecc_err_cnt",
+			SE_ALG_ZGP3_ZBLK3_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x111c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp3_zblk3_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp3_zblk4_ecc_err_cnt",
+			SE_ALG_ZGP3_ZBLK4_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1120,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp3_zblk4_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp3_zblk5_ecc_err_cnt",
+			SE_ALG_ZGP3_ZBLK5_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1124,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp3_zblk5_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp3_zblk6_ecc_err_cnt",
+			SE_ALG_ZGP3_ZBLK6_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1128,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp3_zblk6_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zgp3_zblk7_ecc_err_cnt",
+			SE_ALG_ZGP3_ZBLK7_ECC_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x112c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zgp3_zblk7_ecc_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zcam_hash_p0_err_cnt",
+			SE_ALG_ZCAM_HASH_P0_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1130,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zcam_hash_p0_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zcam_hash_p1_err_cnt",
+			SE_ALG_ZCAM_HASH_P1_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1134,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zcam_hash_p1_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zcam_hash_p2_err_cnt",
+			SE_ALG_ZCAM_HASH_P2_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1138,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zcam_hash_p2_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zcam_hash_p3_err_cnt",
+			SE_ALG_ZCAM_HASH_P3_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x113c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zcam_hash_p3_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zcam_lpm_err_cnt",
+			SE_ALG_ZCAM_LPM_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1140,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zcam_lpm_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_sreq_fifo_parity_err_cnt",
+			SE_ALG_HASH0_SREQ_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1144,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_sreq_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_sreq_fifo_int_cnt",
+			SE_ALG_HASH0_SREQ_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1148,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_sreq_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_key_fifo_int_cnt",
+			SE_ALG_HASH0_KEY_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x114c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_key_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_int_rsp_fifo_parity_err_cnt",
+			SE_ALG_HASH0_INT_RSP_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1150,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_int_rsp_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_ext_rsp_fifo_parity_err_cnt",
+			SE_ALG_HASH0_EXT_RSP_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1154,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_ext_rsp_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_ext_rsp_fifo_int_cnt",
+			SE_ALG_HASH0_EXT_RSP_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1158,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_ext_rsp_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_int_rsp_fifo_int_cnt",
+			SE_ALG_HASH0_INT_RSP_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x115c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_int_rsp_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_sreq_fifo_parity_err_cnt",
+			SE_ALG_HASH1_SREQ_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1160,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_sreq_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_sreq_fifo_int_cnt",
+			SE_ALG_HASH1_SREQ_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1164,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_sreq_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_key_fifo_int_cnt",
+			SE_ALG_HASH1_KEY_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1168,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_key_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_int_rsp_fifo_parity_err_cnt",
+			SE_ALG_HASH1_INT_RSP_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x116c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_int_rsp_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_ext_rsp_fifo_parity_err_cnt",
+			SE_ALG_HASH1_EXT_RSP_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1170,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_ext_rsp_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_ext_rsp_fifo_int_cnt",
+			SE_ALG_HASH1_EXT_RSP_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1174,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_ext_rsp_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_int_rsp_fifo_int_cnt",
+			SE_ALG_HASH1_INT_RSP_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1178,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_int_rsp_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_sreq_fifo_parity_err_cnt",
+			SE_ALG_HASH2_SREQ_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x117c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_sreq_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_sreq_fifo_int_cnt",
+			SE_ALG_HASH2_SREQ_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1180,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_sreq_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_key_fifo_int_cnt",
+			SE_ALG_HASH2_KEY_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1184,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_key_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_int_rsp_fifo_parity_err_cnt",
+			SE_ALG_HASH2_INT_RSP_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1188,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_int_rsp_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_ext_rsp_fifo_parity_err_cnt",
+			SE_ALG_HASH2_EXT_RSP_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x118c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_ext_rsp_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_ext_rsp_fifo_int_cnt",
+			SE_ALG_HASH2_EXT_RSP_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1190,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_ext_rsp_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_int_rsp_fifo_int_cnt",
+			SE_ALG_HASH2_INT_RSP_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1194,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_int_rsp_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_sreq_fifo_parity_err_cnt",
+			SE_ALG_HASH3_SREQ_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1198,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_sreq_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_sreq_fifo_int_cnt",
+			SE_ALG_HASH3_SREQ_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x119c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_sreq_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_key_fifo_int_cnt",
+			SE_ALG_HASH3_KEY_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_key_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_int_rsp_fifo_parity_err_cnt",
+			SE_ALG_HASH3_INT_RSP_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_int_rsp_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_ext_rsp_fifo_parity_err_cnt",
+			SE_ALG_HASH3_EXT_RSP_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_ext_rsp_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_ext_rsp_fifo_int_cnt",
+			SE_ALG_HASH3_EXT_RSP_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_ext_rsp_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_int_rsp_fifo_int_cnt",
+			SE_ALG_HASH3_INT_RSP_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_int_rsp_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_ext_rsp_fifo_int_cnt",
+			SE_ALG_LPM_EXT_RSP_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_ext_rsp_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_ext_v6_fifo_int_cnt",
+			SE_ALG_LPM_EXT_V6_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_ext_v6_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_ext_v4_fifo_int_cnt",
+			SE_ALG_LPM_EXT_V4_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_ext_v4_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_ext_addr_fifo_int_cnt",
+			SE_ALG_LPM_EXT_ADDR_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_ext_addr_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_ext_v4_fifo_parity_err_cnt",
+			SE_ALG_LPM_EXT_V4_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_ext_v4_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_ext_v6_fifo_parity_err_cnt",
+			SE_ALG_LPM_EXT_V6_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_ext_v6_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_ext_rsp_fifo_parity_err_cnt",
+			SE_ALG_LPM_EXT_RSP_FIFO_PARITY_ERR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_ext_rsp_fifo_parity_err_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_as_req_fifo_int_cnt",
+			SE_ALG_LPM_AS_REQ_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_as_req_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_as_int_rsp_fifo_int_cnt",
+			SE_ALG_LPM_AS_INT_RSP_FIFO_INT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x11d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_as_int_rsp_fifo_int_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_alg_int_status",
+			SE_ALG_SE_ALG_INT_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1800,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			7,
+			g_se_alg_se_alg_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_en",
+			SE_ALG_SCHD_INT_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1804,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			14,
+			g_se_alg_schd_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_mask",
+			SE_ALG_SCHD_INT_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1808,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_status",
+			SE_ALG_SCHD_INT_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x180c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_schd_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblk_ecc_int_en",
+			SE_ALG_ZBLK_ECC_INT_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1810,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zblk_ecc_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblk_ecc_int_mask",
+			SE_ALG_ZBLK_ECC_INT_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1814,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zblk_ecc_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblk_ecc_int_status",
+			SE_ALG_ZBLK_ECC_INT_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1818,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_zblk_ecc_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_int_en",
+			SE_ALG_HASH0_INT_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x181c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			8,
+			g_se_alg_hash0_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_int_mask",
+			SE_ALG_HASH0_INT_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1820,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_int_status",
+			SE_ALG_HASH0_INT_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1824,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash0_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_int_en",
+			SE_ALG_HASH1_INT_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1828,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			8,
+			g_se_alg_hash1_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_int_mask",
+			SE_ALG_HASH1_INT_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x182c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_int_status",
+			SE_ALG_HASH1_INT_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1830,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash1_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_int_en",
+			SE_ALG_HASH2_INT_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1834,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			8,
+			g_se_alg_hash2_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_int_mask",
+			SE_ALG_HASH2_INT_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1838,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_int_status",
+			SE_ALG_HASH2_INT_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x183c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash2_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_int_en",
+			SE_ALG_HASH3_INT_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1840,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			8,
+			g_se_alg_hash3_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_int_mask",
+			SE_ALG_HASH3_INT_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1844,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_int_status",
+			SE_ALG_HASH3_INT_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1848,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_hash3_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_int_en",
+			SE_ALG_LPM_INT_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x184c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			10,
+			g_se_alg_lpm_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_int_mask",
+			SE_ALG_LPM_INT_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1850,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_int_status",
+			SE_ALG_LPM_INT_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_ALG_BASE_ADDR + 0x1854,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_alg_lpm_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_lpm_mask0",
+			SE_ALG_ZBLOCK_LPM_MASK0r,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x10001,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			5,
+			g_se_alg_zblock_lpm_mask0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_lpm_mask1",
+			SE_ALG_ZBLOCK_LPM_MASK1r,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x10002,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			5,
+			g_se_alg_zblock_lpm_mask1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_lpm_mask2",
+			SE_ALG_ZBLOCK_LPM_MASK2r,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x10003,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			5,
+			g_se_alg_zblock_lpm_mask2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_lpm_mask3",
+			SE_ALG_ZBLOCK_LPM_MASK3r,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x10004,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			5,
+			g_se_alg_zblock_lpm_mask3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_default_route0",
+			SE_ALG_ZBLOCK_DEFAULT_ROUTE0r,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x10005,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			4,
+			g_se_alg_zblock_default_route0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_default_route1",
+			SE_ALG_ZBLOCK_DEFAULT_ROUTE1r,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x10006,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			4,
+			g_se_alg_zblock_default_route1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_default_route2",
+			SE_ALG_ZBLOCK_DEFAULT_ROUTE2r,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x10007,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			4,
+			g_se_alg_zblock_default_route2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_default_route3",
+			SE_ALG_ZBLOCK_DEFAULT_ROUTE3r,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x10008,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			4,
+			g_se_alg_zblock_default_route3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_default_route4",
+			SE_ALG_ZBLOCK_DEFAULT_ROUTE4r,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x10009,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			4,
+			g_se_alg_zblock_default_route4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_default_route5",
+			SE_ALG_ZBLOCK_DEFAULT_ROUTE5r,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x1000a,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			4,
+			g_se_alg_zblock_default_route5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_default_route6",
+			SE_ALG_ZBLOCK_DEFAULT_ROUTE6r,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x1000b,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			4,
+			g_se_alg_zblock_default_route6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_default_route7",
+			SE_ALG_ZBLOCK_DEFAULT_ROUTE7r,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x1000c,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			4,
+			g_se_alg_zblock_default_route7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_hash_listtable_item0",
+			SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM0r,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x1000d,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			1,
+			g_se_alg_zblock_hash_listtable_item0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_hash_listtable_item1",
+			SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM1r,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x1000e,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			1,
+			g_se_alg_zblock_hash_listtable_item1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_hash_listtable_item2",
+			SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM2r,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x1000f,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			1,
+			g_se_alg_zblock_hash_listtable_item2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_hash_listtable_item3",
+			SE_ALG_ZBLOCK_HASH_LISTTABLE_ITEM3r,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x10010,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			1,
+			g_se_alg_zblock_hash_listtable_item3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_ecc_err_status",
+			SE_ALG_ZBLOCK_ECC_ERR_STATUSr,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x10011,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			4,
+			g_se_alg_zblock_ecc_err_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_lpm_v6_sram_cmp",
+			SE_ALG_ZBLOCK_LPM_V6_SRAM_CMPr,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x10012,
+			(512 / 8),
+			3 + 1,
+			7 + 1,
+			0x4000,
+			0x800,
+			1,
+			g_se_alg_zblock_lpm_v6_sram_cmp_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"zblock_lpm_v4_sram_cmp",
+			SE_ALG_ZBLOCK_LPM_V4_SRAM_CMPr,
+			SE,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_BIN_ARRAY,
+			0x10013,
+			(512 / 8),
+			3 + 1,
+			5 + 1,
+			0x4000,
+			0x800,
+			1,
+			g_se_alg_zblock_lpm_v4_sram_cmp_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_pful_cfg",
+			SE_PARSER_KSCHD_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_parser_kschd_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_mode",
+			SE_PARSER_DEBUG_CNT_MODEr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_parser_debug_cnt_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"parser_int_en",
+			SE_PARSER_PARSER_INT_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x0000000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_parser_parser_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"parser_int_mask",
+			SE_PARSER_PARSER_INT_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_parser_parser_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"parser_int_status",
+			SE_PARSER_PARSER_INT_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_parser_parser_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"parser_int_unmask_flag",
+			SE_PARSER_PARSER_INT_UNMASK_FLAGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_parser_parser_int_unmask_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ecc_bypass_read",
+			SE_PARSER_ECC_BYPASS_READr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x0000001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_parser_ecc_bypass_read_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mex0_5_req_cnt",
+			SE_PARSER_MEX0_5_REQ_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000400,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_se_parser_mex0_5_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_req0_5_cnt",
+			SE_PARSER_KSCHD_REQ0_5_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000420,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_se_parser_kschd_req0_5_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_parser_fc0_5_cnt",
+			SE_PARSER_KSCHD_PARSER_FC0_5_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000440,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_se_parser_kschd_parser_fc0_5_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_ppu_mex0_5_fc_cnt",
+			SE_PARSER_SE_PPU_MEX0_5_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000460,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_se_parser_se_ppu_mex0_5_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_marc_fc_cnt",
+			SE_PARSER_SMMU0_MARC_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000480,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_parser_smmu0_marc_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_marc_key_cnt",
+			SE_PARSER_SMMU0_MARC_KEY_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000484,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_parser_smmu0_marc_key_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cmmu_key_cnt",
+			SE_PARSER_CMMU_KEY_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000488,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_parser_cmmu_key_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cmmu_parser_fc_cnt",
+			SE_PARSER_CMMU_PARSER_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x0000048c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_parser_cmmu_parser_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"marc_tab_type_err_mex0_5_cnt",
+			SE_PARSER_MARC_TAB_TYPE_ERR_MEX0_5_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x00000490,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_se_parser_marc_tab_type_err_mex0_5_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"eram_fulladdr_drop_cnt",
+			SE_PARSER_ERAM_FULLADDR_DROP_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_PARSER_BASE_ADDR + 0x000004b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_parser_eram_fulladdr_drop_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_pful_cfg",
+			SE_AS_HASH0_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_hash0_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash1_pful_cfg",
+			SE_AS_HASH1_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_hash1_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash2_pful_cfg",
+			SE_AS_HASH2_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_hash2_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_pful_cfg",
+			SE_AS_HASH3_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_hash3_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_pful_cfg",
+			SE_AS_PBU_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_pbu_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_pful_cfg",
+			SE_AS_LPM_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_lpm_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_pful_cfg",
+			SE_AS_ETCAM_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_etcam_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_learn0_fifo_cfg",
+			SE_AS_AS_LEARN0_FIFO_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_se_as_as_learn0_fifo_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_learn1_fifo_cfg",
+			SE_AS_AS_LEARN1_FIFO_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_se_as_as_learn1_fifo_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_dma_fifo_cfg",
+			SE_AS_AS_DMA_FIFO_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_as_dma_fifo_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"age_pful_cfg",
+			SE_AS_AGE_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_age_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_rsp_cfg",
+			SE_AS_ETCAM_RSP_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_se_as_etcam_rsp_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ecc_bypass_read",
+			SE_AS_PBU_ECC_BYPASS_READr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000001fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_pbu_ecc_bypass_read_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam0_ecc_bypass_read",
+			SE_AS_ETCAM0_ECC_BYPASS_READr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000200,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_etcam0_ecc_bypass_read_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam1_ecc_bypass_read",
+			SE_AS_ETCAM1_ECC_BYPASS_READr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000204,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_etcam1_ecc_bypass_read_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_ecc_bypass_read",
+			SE_AS_LPM_ECC_BYPASS_READr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000208,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_lpm_ecc_bypass_read_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_ecc_bypass_read",
+			SE_AS_HASH_ECC_BYPASS_READr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000020c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_se_as_hash_ecc_bypass_read_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_learn_ecc_bypass_read",
+			SE_AS_HASH_LEARN_ECC_BYPASS_READr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000210,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_hash_learn_ecc_bypass_read_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_mode",
+			SE_AS_DEBUG_CNT_MODEr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000003e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_as_debug_cnt_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_int_0_en",
+			SE_AS_AS_INT_0_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000440,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_as_int_0_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_int_0_mask",
+			SE_AS_AS_INT_0_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000444,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_as_int_0_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_int_1_en",
+			SE_AS_AS_INT_1_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000448,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_as_int_1_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_int_1_mask",
+			SE_AS_AS_INT_1_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000044c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_as_int_1_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_int_2_en",
+			SE_AS_AS_INT_2_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000450,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_as_int_2_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_int_2_mask",
+			SE_AS_AS_INT_2_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000454,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_as_int_2_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_int_0_status",
+			SE_AS_AS_INT_0_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000458,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_as_int_0_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_int_1_status",
+			SE_AS_AS_INT_1_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000045c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_as_int_1_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_int_2_status",
+			SE_AS_AS_INT_2_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000460,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_as_int_2_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_as_int_status",
+			SE_AS_SE_AS_INT_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000464,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_se_as_se_as_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_3_wr_req_cnt",
+			SE_AS_HASH0_3_WR_REQ_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000082c,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_as_hash0_3_wr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_etcam0_1_fc_cnt",
+			SE_AS_SMMU0_ETCAM0_1_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000083c,
+			(32 / 8),
+			0,
+			0 + 1,
+			0,
+			4,
+			1,
+			g_se_as_smmu0_etcam0_1_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam0_1_smmu0_req_cnt",
+			SE_AS_ETCAM0_1_SMMU0_REQ_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000844,
+			(32 / 8),
+			0,
+			0 + 1,
+			0,
+			8,
+			1,
+			g_se_as_etcam0_1_smmu0_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_etcam0_1_rsp_cnt",
+			SE_AS_SMMU0_ETCAM0_1_RSP_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000848,
+			(32 / 8),
+			0,
+			0 + 1,
+			0,
+			8,
+			1,
+			g_se_as_smmu0_etcam0_1_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_hla_hash_p0_3_key_cnt",
+			SE_AS_AS_HLA_HASH_P0_3_KEY_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000854,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_as_as_hla_hash_p0_3_key_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_hla_lpm_p0_key_cnt",
+			SE_AS_AS_HLA_LPM_P0_KEY_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000864,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_as_hla_lpm_p0_key_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"alg_as_hash_p0_3_rsp_cnt",
+			SE_AS_ALG_AS_HASH_P0_3_RSP_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000868,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			8,
+			1,
+			g_se_as_alg_as_hash_p0_3_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"alg_as_hash_p0_3_smf_rsp_cnt",
+			SE_AS_ALG_AS_HASH_P0_3_SMF_RSP_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000086c,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			8,
+			1,
+			g_se_as_alg_as_hash_p0_3_smf_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"alg_as_lpm_p0_rsp_cnt",
+			SE_AS_ALG_AS_LPM_P0_RSP_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000888,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_alg_as_lpm_p0_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"alg_as_lpm_p0_3_smf_rsp_cnt",
+			SE_AS_ALG_AS_LPM_P0_3_SMF_RSP_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000088c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_alg_as_lpm_p0_3_smf_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_pbu_key_cnt",
+			SE_AS_AS_PBU_KEY_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000890,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_as_pbu_key_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_se_dpi_rsp_dat_cnt",
+			SE_AS_PBU_SE_DPI_RSP_DAT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000894,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_pbu_se_dpi_rsp_dat_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_etcam_ctrl_req0_cnt",
+			SE_AS_AS_ETCAM_CTRL_REQ0_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000898,
+			(32 / 8),
+			0,
+			0 + 1,
+			0,
+			4,
+			1,
+			g_se_as_as_etcam_ctrl_req0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_ctrl_as_index0_1_cnt",
+			SE_AS_ETCAM_CTRL_AS_INDEX0_1_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008a0,
+			(32 / 8),
+			0,
+			0 + 1,
+			0,
+			8,
+			1,
+			g_se_as_etcam_ctrl_as_index0_1_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_ctrl_as_hit0_1_cnt",
+			SE_AS_ETCAM_CTRL_AS_HIT0_1_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008a4,
+			(32 / 8),
+			0,
+			0 + 1,
+			0,
+			8,
+			1,
+			g_se_as_etcam_ctrl_as_hit0_1_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_smmu0_req_cnt",
+			SE_AS_AS_SMMU0_REQ_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_as_smmu0_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"learn_hla_wr_cnt",
+			SE_AS_LEARN_HLA_WR_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_learn_hla_wr_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_smmu1_req_cnt",
+			SE_AS_AS_SMMU1_REQ_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_as_smmu1_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_cfg_mac_dat_cnt",
+			SE_AS_SE_CFG_MAC_DAT_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_se_cfg_mac_dat_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"alg_as_hash_p0_3_fc_cnt",
+			SE_AS_ALG_AS_HASH_P0_3_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008c0,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_as_alg_as_hash_p0_3_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"alg_as_lpm_p0_fc_cnt",
+			SE_AS_ALG_AS_LPM_P0_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_alg_as_lpm_p0_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_alg_hash_p0_3_fc_cnt",
+			SE_AS_AS_ALG_HASH_P0_3_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008d4,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_as_as_alg_hash_p0_3_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_alg_lpm_p0_fc_cnt",
+			SE_AS_AS_ALG_LPM_P0_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_as_alg_lpm_p0_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_pbu_fc_cnt",
+			SE_AS_AS_PBU_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_as_pbu_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_se_dpi_key_fc_cnt",
+			SE_AS_PBU_SE_DPI_KEY_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_pbu_se_dpi_key_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_etcam_ctrl_fc0_1_cnt",
+			SE_AS_AS_ETCAM_CTRL_FC0_1_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008f0,
+			(32 / 8),
+			0,
+			0 + 1,
+			0,
+			4,
+			1,
+			g_se_as_as_etcam_ctrl_fc0_1_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_ctrl_as_fc0_1_cnt",
+			SE_AS_ETCAM_CTRL_AS_FC0_1_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x000008f8,
+			(32 / 8),
+			0,
+			0 + 1,
+			0,
+			4,
+			1,
+			g_se_as_etcam_ctrl_as_fc0_1_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_as_mac_age_fc_cnt",
+			SE_AS_SMMU0_AS_MAC_AGE_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000900,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_smmu0_as_mac_age_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"alg_learn_fc_cnt",
+			SE_AS_ALG_LEARN_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000904,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_alg_learn_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_as_fc_cnt",
+			SE_AS_SMMU1_AS_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x00000908,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_smmu1_as_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_se_mac_fc_cnt",
+			SE_AS_CFG_SE_MAC_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_AS_BASE_ADDR + 0x0000090c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_as_cfg_se_mac_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_cpu_rdy",
+			SE_KSCHD_KSCHD_CPU_RDYr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_kschd_cpu_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu0_ecc_bypass_read",
+			SE_KSCHD_PPU0_ECC_BYPASS_READr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_ppu0_ecc_bypass_read_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pbu_ecc_bypass_read",
+			SE_KSCHD_PBU_ECC_BYPASS_READr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_pbu_ecc_bypass_read_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_ecc_bypass_read",
+			SE_KSCHD_SMMU1_ECC_BYPASS_READr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000002c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_se_kschd_smmu1_ecc_bypass_read_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ass_ecc_bypass_read",
+			SE_KSCHD_ASS_ECC_BYPASS_READr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_ass_ecc_bypass_read_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sdt_h",
+			SE_KSCHD_SDT_Hr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_sdt_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"sdt_l",
+			SE_KSCHD_SDT_Lr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_sdt_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key15",
+			SE_KSCHD_HASH_KEY15r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_se_kschd_hash_key15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key14",
+			SE_KSCHD_HASH_KEY14r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_hash_key14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key13",
+			SE_KSCHD_HASH_KEY13r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_hash_key13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key12",
+			SE_KSCHD_HASH_KEY12r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_hash_key12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key11",
+			SE_KSCHD_HASH_KEY11r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_hash_key11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key10",
+			SE_KSCHD_HASH_KEY10r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000005c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_hash_key10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key9",
+			SE_KSCHD_HASH_KEY9r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_hash_key9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key8",
+			SE_KSCHD_HASH_KEY8r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_hash_key8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key7",
+			SE_KSCHD_HASH_KEY7r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_hash_key7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key6",
+			SE_KSCHD_HASH_KEY6r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000006c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_hash_key6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key5",
+			SE_KSCHD_HASH_KEY5r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000070,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_hash_key5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key4",
+			SE_KSCHD_HASH_KEY4r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000074,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_hash_key4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key3",
+			SE_KSCHD_HASH_KEY3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000078,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_hash_key3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key2",
+			SE_KSCHD_HASH_KEY2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x0000007c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_hash_key2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key1",
+			SE_KSCHD_HASH_KEY1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_hash_key1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_key0",
+			SE_KSCHD_HASH_KEY0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_hash_key0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_0_en",
+			SE_KSCHD_SCHD_INT_0_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_schd_int_0_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_0_mask",
+			SE_KSCHD_SCHD_INT_0_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_schd_int_0_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_1_en",
+			SE_KSCHD_SCHD_INT_1_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_schd_int_1_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_1_mask",
+			SE_KSCHD_SCHD_INT_1_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_schd_int_1_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_2_en",
+			SE_KSCHD_SCHD_INT_2_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_schd_int_2_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_2_mask",
+			SE_KSCHD_SCHD_INT_2_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_schd_int_2_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_3_en",
+			SE_KSCHD_SCHD_INT_3_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_schd_int_3_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_3_mask",
+			SE_KSCHD_SCHD_INT_3_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_schd_int_3_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_4_en",
+			SE_KSCHD_SCHD_INT_4_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_schd_int_4_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_4_mask",
+			SE_KSCHD_SCHD_INT_4_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_schd_int_4_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_0_status",
+			SE_KSCHD_SCHD_INT_0_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_schd_int_0_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_1_status",
+			SE_KSCHD_SCHD_INT_1_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_schd_int_1_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_2_status",
+			SE_KSCHD_SCHD_INT_2_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_schd_int_2_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_3_status",
+			SE_KSCHD_SCHD_INT_3_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_schd_int_3_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"schd_int_4_status",
+			SE_KSCHD_SCHD_INT_4_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000000f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_schd_int_4_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_kschd_int_status",
+			SE_KSCHD_SE_KSCHD_INT_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000148,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_se_kschd_se_kschd_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_mode",
+			SE_KSCHD_DEBUG_CNT_MODEr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000003ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_kschd_debug_cnt_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_parser_kschd_key0_3_cnt",
+			SE_KSCHD_SE_PARSER_KSCHD_KEY0_3_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000878,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_se_kschd_se_parser_kschd_key0_3_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_smmu1_key0_3_cnt",
+			SE_KSCHD_SE_SMMU1_KEY0_3_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000890,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_kschd_se_smmu1_key0_3_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_as_key0_cnt",
+			SE_KSCHD_KSCHD_AS_KEY0_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_kschd_as_key0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_as_key1_cnt",
+			SE_KSCHD_KSCHD_AS_KEY1_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_kschd_as_key1_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_as_key2_cnt",
+			SE_KSCHD_KSCHD_AS_KEY2_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_kschd_as_key2_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_as_key3_cnt",
+			SE_KSCHD_KSCHD_AS_KEY3_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_kschd_as_key3_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_as_key4_cnt",
+			SE_KSCHD_KSCHD_AS_KEY4_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_kschd_as_key4_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_as_key5_cnt",
+			SE_KSCHD_KSCHD_AS_KEY5_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_kschd_as_key5_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_as_key6_cnt",
+			SE_KSCHD_KSCHD_AS_KEY6_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_kschd_as_key6_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_as_key9_cnt",
+			SE_KSCHD_KSCHD_AS_KEY9_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_kschd_as_key9_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_se_parser_fc0_3_cnt",
+			SE_KSCHD_KSCHD_SE_PARSER_FC0_3_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008c0,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_se_kschd_kschd_se_parser_fc0_3_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_se_fc0_3_cnt",
+			SE_KSCHD_SMMU1_SE_FC0_3_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008d8,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_kschd_smmu1_se_fc0_3_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_kschd_fc_cnt0",
+			SE_KSCHD_AS_KSCHD_FC_CNT0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_as_kschd_fc_cnt0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_kschd_fc_cnt1",
+			SE_KSCHD_AS_KSCHD_FC_CNT1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_as_kschd_fc_cnt1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_kschd_fc_cnt2",
+			SE_KSCHD_AS_KSCHD_FC_CNT2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_as_kschd_fc_cnt2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_kschd_fc_cnt3",
+			SE_KSCHD_AS_KSCHD_FC_CNT3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_as_kschd_fc_cnt3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_kschd_fc_cnt4",
+			SE_KSCHD_AS_KSCHD_FC_CNT4r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_as_kschd_fc_cnt4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_kschd_fc_cnt5",
+			SE_KSCHD_AS_KSCHD_FC_CNT5r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x000008fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_as_kschd_fc_cnt5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_kschd_fc_cnt6",
+			SE_KSCHD_AS_KSCHD_FC_CNT6r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000900,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_as_kschd_fc_cnt6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_kschd_fc_cnt9",
+			SE_KSCHD_AS_KSCHD_FC_CNT9r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_KSCHD_BASE_ADDR + 0x00000904,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_kschd_as_kschd_fc_cnt9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_hash_pful_cfg",
+			SE_RSCHD_RSCHD_HASH_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_hash_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_hash_ept_cfg",
+			SE_RSCHD_RSCHD_HASH_EPT_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_hash_ept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_pbu_pful_cfg",
+			SE_RSCHD_RSCHD_PBU_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_pbu_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_pbu_ept_cfg",
+			SE_RSCHD_RSCHD_PBU_EPT_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_pbu_ept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_lpm_pful_cfg",
+			SE_RSCHD_RSCHD_LPM_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_lpm_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_lpm_ept_cfg",
+			SE_RSCHD_RSCHD_LPM_EPT_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_lpm_ept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_etcam_pful_cfg",
+			SE_RSCHD_RSCHD_ETCAM_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_etcam_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_etcam_ept_cfg",
+			SE_RSCHD_RSCHD_ETCAM_EPT_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_etcam_ept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_wb_pful_cfg",
+			SE_RSCHD_SMMU0_WB_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_smmu0_wb_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_wb_ept_cfg",
+			SE_RSCHD_SMMU0_WB_EPT_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_smmu0_wb_ept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_wb_pful_cfg",
+			SE_RSCHD_SMMU1_WB_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_smmu1_wb_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_wb_ept_cfg",
+			SE_RSCHD_SMMU1_WB_EPT_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_smmu1_wb_ept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"alg_wb_pful_cfg",
+			SE_RSCHD_ALG_WB_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_alg_wb_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"alg_wb_ept_cfg",
+			SE_RSCHD_ALG_WB_EPT_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_alg_wb_ept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"wr_rsp_vld_en",
+			SE_RSCHD_WR_RSP_VLD_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_wr_rsp_vld_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"nppu_wb_pful_cfg",
+			SE_RSCHD_NPPU_WB_PFUL_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000005c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_nppu_wb_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"nppu_wb_ept_cfg",
+			SE_RSCHD_NPPU_WB_EPT_CFGr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_nppu_wb_ept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port0_int_en",
+			SE_RSCHD_PORT0_INT_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_port0_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port0_int_mask",
+			SE_RSCHD_PORT0_INT_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_port0_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port1_int_en",
+			SE_RSCHD_PORT1_INT_ENr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_port1_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port1_int_mask",
+			SE_RSCHD_PORT1_INT_MASKr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_port1_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port0_int_status",
+			SE_RSCHD_PORT0_INT_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_port0_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"port1_int_status",
+			SE_RSCHD_PORT1_INT_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000000d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_port1_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_rschd_int_status",
+			SE_RSCHD_SE_RSCHD_INT_STATUSr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000018c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_rschd_se_rschd_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_mode",
+			SE_RSCHD_DEBUG_CNT_MODEr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000003ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_rschd_debug_cnt_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_ppu_mex0_5_rsp1_cnt",
+			SE_RSCHD_SE_PPU_MEX0_5_RSP1_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000880,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_se_rschd_se_ppu_mex0_5_rsp1_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_rschd_rsp0_cnt",
+			SE_RSCHD_AS_RSCHD_RSP0_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000898,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_as_rschd_rsp0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_rschd_rsp1_cnt",
+			SE_RSCHD_AS_RSCHD_RSP1_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000089c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_as_rschd_rsp1_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_rschd_rsp2_cnt",
+			SE_RSCHD_AS_RSCHD_RSP2_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_as_rschd_rsp2_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_rschd_rsp3_cnt",
+			SE_RSCHD_AS_RSCHD_RSP3_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_as_rschd_rsp3_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_rschd_rsp4_cnt",
+			SE_RSCHD_AS_RSCHD_RSP4_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_as_rschd_rsp4_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_rschd_rsp5_cnt",
+			SE_RSCHD_AS_RSCHD_RSP5_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_as_rschd_rsp5_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_rschd_rsp6_cnt",
+			SE_RSCHD_AS_RSCHD_RSP6_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_as_rschd_rsp6_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_rschd_rsp9_cnt",
+			SE_RSCHD_AS_RSCHD_RSP9_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_as_rschd_rsp9_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_se_rsp0_3_cnt",
+			SE_RSCHD_SMMU1_SE_RSP0_3_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008b8,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_rschd_smmu1_se_rsp0_3_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_se_mex0_3_fc_cnt",
+			SE_RSCHD_PPU_SE_MEX0_3_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008c4,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_se_rschd_ppu_se_mex0_3_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_as_fc_cnt0",
+			SE_RSCHD_RSCHD_AS_FC_CNT0r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_as_fc_cnt0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_as_fc_cnt1",
+			SE_RSCHD_RSCHD_AS_FC_CNT1r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_as_fc_cnt1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_as_fc_cnt2",
+			SE_RSCHD_RSCHD_AS_FC_CNT2r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_as_fc_cnt2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_as_fc_cnt3",
+			SE_RSCHD_RSCHD_AS_FC_CNT3r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_as_fc_cnt3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_as_fc_cnt4",
+			SE_RSCHD_RSCHD_AS_FC_CNT4r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_as_fc_cnt4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_as_fc_cnt5",
+			SE_RSCHD_RSCHD_AS_FC_CNT5r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_as_fc_cnt5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_as_fc_cnt6",
+			SE_RSCHD_RSCHD_AS_FC_CNT6r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_as_fc_cnt6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_as_fc_cnt9",
+			SE_RSCHD_RSCHD_AS_FC_CNT9r,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x000008fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_rschd_as_fc_cnt9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_smmu1_fc0_3_cnt",
+			SE_RSCHD_SE_SMMU1_FC0_3_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000900,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_rschd_se_smmu1_fc0_3_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_se_wr_done_cnt",
+			SE_RSCHD_SMMU0_SE_WR_DONE_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000910,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_smmu0_se_wr_done_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_smmu0_wr_done_fc_cnt",
+			SE_RSCHD_SE_SMMU0_WR_DONE_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000914,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_se_smmu0_wr_done_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_se_wr_rsp_cnt",
+			SE_RSCHD_SMMU1_SE_WR_RSP_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000918,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_smmu1_se_wr_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_smmu1_wr_rsp_fc_cnt",
+			SE_RSCHD_SE_SMMU1_WR_RSP_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x0000091c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_se_smmu1_wr_rsp_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"alg_se_wr_rsp_cnt",
+			SE_RSCHD_ALG_SE_WR_RSP_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000920,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_alg_se_wr_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_alg_wr_rsp_fc_cnt",
+			SE_RSCHD_SE_ALG_WR_RSP_FC_CNTr,
+			SE,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_BASE_ADDR + MODULE_SE_RSCHD_BASE_ADDR + 0x00000924,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_rschd_se_alg_wr_rsp_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_pful_cfg0",
+			SMMU0_SMMU0_KSCHD_PFUL_CFG0r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_smmu0_smmu0_kschd_pful_cfg0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_pful_cfg1",
+			SMMU0_SMMU0_KSCHD_PFUL_CFG1r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_smmu0_smmu0_kschd_pful_cfg1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_pful1_cfg",
+			SMMU0_SMMU0_CTRL_PFUL1_CFGr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_ctrl_pful1_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_pful2_cfg",
+			SMMU0_SMMU0_CTRL_PFUL2_CFGr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000008c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_ctrl_pful2_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_pful3_cfg",
+			SMMU0_SMMU0_CTRL_PFUL3_CFGr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_ctrl_pful3_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_pful_cfg",
+			SMMU0_SMMU0_RSCHD_PFUL_CFGr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_rschd_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_ept_cfg",
+			SMMU0_SMMU0_RSCHD_EPT_CFGr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000098,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_rschd_ept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"alucmd_pful_cfg",
+			SMMU0_SMMU0_ALUCMD_PFUL_CFGr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000009c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_alucmd_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"aluwr_pful_cfg",
+			SMMU0_SMMU0_ALUWR_PFUL_CFGr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_aluwr_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"wr_arb_pful_cfg0",
+			SMMU0_SMMU0_WR_ARB_PFUL_CFG0r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_wr_arb_pful_cfg0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"wr_arb_pful_cfg1",
+			SMMU0_SMMU0_WR_ARB_PFUL_CFG1r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_wr_arb_pful_cfg1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ord_pful_cfg",
+			SMMU0_SMMU0_ORD_PFUL_CFGr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_ord_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_dma_baddr",
+			SMMU0_SMMU0_CFG_DMA_BADDRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cfg_dma_baddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_odma0_baddr",
+			SMMU0_SMMU0_CFG_ODMA0_BADDRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cfg_odma0_baddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_odma1_baddr",
+			SMMU0_SMMU0_CFG_ODMA1_BADDRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cfg_odma1_baddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_odma2_baddr",
+			SMMU0_SMMU0_CFG_ODMA2_BADDRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cfg_odma2_baddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_odma_tdm_baddr",
+			SMMU0_SMMU0_CFG_ODMA_TDM_BADDRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cfg_odma_tdm_baddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_mcast_baddr",
+			SMMU0_SMMU0_CFG_MCAST_BADDRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cfg_mcast_baddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_lpm0",
+			SMMU0_SMMU0_CFG_LPM0r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_cfg_lpm0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_lpm1",
+			SMMU0_SMMU0_CFG_LPM1r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_cfg_lpm1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_lpm2",
+			SMMU0_SMMU0_CFG_LPM2r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_cfg_lpm2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_lpm3",
+			SMMU0_SMMU0_CFG_LPM3r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_cfg_lpm3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_lpm4",
+			SMMU0_SMMU0_CFG_LPM4r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_cfg_lpm4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_lpm5",
+			SMMU0_SMMU0_CFG_LPM5r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_cfg_lpm5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_lpm6",
+			SMMU0_SMMU0_CFG_LPM6r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_cfg_lpm6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_lpm7",
+			SMMU0_SMMU0_CFG_LPM7r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000000f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_cfg_lpm7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_mode",
+			SMMU0_SMMU0_DEBUG_CNT_MODEr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000100,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_debug_cnt_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_overflow_mode",
+			SMMU0_SMMU0_STAT_OVERFLOW_MODEr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000104,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_stat_overflow_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"init_en_cfg_tmp",
+			SMMU0_SMMU0_INIT_EN_CFG_TMPr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000013c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_init_en_cfg_tmp_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int_unmask_flag",
+			SMMU0_SMMU0_SMMU0_INT_UNMASK_FLAGr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000140,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int_unmask_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int0_en",
+			SMMU0_SMMU0_SMMU0_INT0_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000144,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int0_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int0_mask",
+			SMMU0_SMMU0_SMMU0_INT0_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000148,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int0_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int0_status",
+			SMMU0_SMMU0_SMMU0_INT0_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000014c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int0_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int1_en",
+			SMMU0_SMMU0_SMMU0_INT1_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000150,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int1_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int1_mask",
+			SMMU0_SMMU0_SMMU0_INT1_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000154,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int1_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int1_status",
+			SMMU0_SMMU0_SMMU0_INT1_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000158,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int1_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int2_en",
+			SMMU0_SMMU0_SMMU0_INT2_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000015c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int2_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int2_mask",
+			SMMU0_SMMU0_SMMU0_INT2_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000160,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int2_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int2_status",
+			SMMU0_SMMU0_SMMU0_INT2_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000164,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int2_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int3_en",
+			SMMU0_SMMU0_SMMU0_INT3_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000168,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int3_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int3_mask",
+			SMMU0_SMMU0_SMMU0_INT3_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000016c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int3_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int3_status",
+			SMMU0_SMMU0_SMMU0_INT3_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000170,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int3_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int4_en",
+			SMMU0_SMMU0_SMMU0_INT4_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000174,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int4_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int4_mask",
+			SMMU0_SMMU0_SMMU0_INT4_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000178,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int4_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int4_status",
+			SMMU0_SMMU0_SMMU0_INT4_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000017c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int4_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int5_en",
+			SMMU0_SMMU0_SMMU0_INT5_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000180,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int5_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int5_mask",
+			SMMU0_SMMU0_SMMU0_INT5_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000184,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int5_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int5_status",
+			SMMU0_SMMU0_SMMU0_INT5_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000188,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int5_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int6_en",
+			SMMU0_SMMU0_SMMU0_INT6_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000018c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int6_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int6_mask",
+			SMMU0_SMMU0_SMMU0_INT6_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000190,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int6_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int6_status",
+			SMMU0_SMMU0_SMMU0_INT6_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000194,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int6_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int7_en",
+			SMMU0_SMMU0_SMMU0_INT7_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000198,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int7_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int7_mask",
+			SMMU0_SMMU0_SMMU0_INT7_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000019c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int7_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int7_status",
+			SMMU0_SMMU0_SMMU0_INT7_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int7_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int8_en",
+			SMMU0_SMMU0_SMMU0_INT8_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int8_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int8_mask",
+			SMMU0_SMMU0_SMMU0_INT8_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int8_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int8_status",
+			SMMU0_SMMU0_SMMU0_INT8_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int8_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int9_en",
+			SMMU0_SMMU0_SMMU0_INT9_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int9_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int9_mask",
+			SMMU0_SMMU0_SMMU0_INT9_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int9_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int9_status",
+			SMMU0_SMMU0_SMMU0_INT9_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int9_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int10_en",
+			SMMU0_SMMU0_SMMU0_INT10_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int10_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int10_mask",
+			SMMU0_SMMU0_SMMU0_INT10_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int10_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int10_status",
+			SMMU0_SMMU0_SMMU0_INT10_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int10_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int11_en",
+			SMMU0_SMMU0_SMMU0_INT11_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int11_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int11_mask",
+			SMMU0_SMMU0_SMMU0_INT11_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int11_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int11_status",
+			SMMU0_SMMU0_SMMU0_INT11_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int11_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int12_en",
+			SMMU0_SMMU0_SMMU0_INT12_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int12_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int12_mask",
+			SMMU0_SMMU0_SMMU0_INT12_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int12_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int12_status",
+			SMMU0_SMMU0_SMMU0_INT12_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int12_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int13_en",
+			SMMU0_SMMU0_SMMU0_INT13_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			20,
+			g_smmu0_smmu0_smmu0_int13_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int13_mask",
+			SMMU0_SMMU0_SMMU0_INT13_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			20,
+			g_smmu0_smmu0_smmu0_int13_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int13_status",
+			SMMU0_SMMU0_SMMU0_INT13_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			20,
+			g_smmu0_smmu0_smmu0_int13_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int14_en",
+			SMMU0_SMMU0_SMMU0_INT14_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			17,
+			g_smmu0_smmu0_smmu0_int14_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int14_mask",
+			SMMU0_SMMU0_SMMU0_INT14_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			17,
+			g_smmu0_smmu0_smmu0_int14_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int14_status",
+			SMMU0_SMMU0_SMMU0_INT14_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			17,
+			g_smmu0_smmu0_smmu0_int14_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_ecc_unmask_flag",
+			SMMU0_SMMU0_SMMU0_ECC_UNMASK_FLAGr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			22,
+			g_smmu0_smmu0_smmu0_ecc_unmask_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int15_en",
+			SMMU0_SMMU0_SMMU0_INT15_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000001fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int15_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int15_mask",
+			SMMU0_SMMU0_SMMU0_INT15_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000200,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int15_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int15_status",
+			SMMU0_SMMU0_SMMU0_INT15_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000204,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int15_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int16_en",
+			SMMU0_SMMU0_SMMU0_INT16_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000208,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int16_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int16_mask",
+			SMMU0_SMMU0_SMMU0_INT16_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000020c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int16_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int16_status",
+			SMMU0_SMMU0_SMMU0_INT16_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000210,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int16_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int17_en",
+			SMMU0_SMMU0_SMMU0_INT17_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000214,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int17_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int17_mask",
+			SMMU0_SMMU0_SMMU0_INT17_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000218,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int17_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int17_status",
+			SMMU0_SMMU0_SMMU0_INT17_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000021c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int17_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int18_en",
+			SMMU0_SMMU0_SMMU0_INT18_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000220,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int18_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int18_mask",
+			SMMU0_SMMU0_SMMU0_INT18_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000224,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int18_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int18_status",
+			SMMU0_SMMU0_SMMU0_INT18_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000228,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int18_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int19_en",
+			SMMU0_SMMU0_SMMU0_INT19_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000022c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int19_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int19_mask",
+			SMMU0_SMMU0_SMMU0_INT19_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000230,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int19_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int19_status",
+			SMMU0_SMMU0_SMMU0_INT19_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000234,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int19_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int20_en",
+			SMMU0_SMMU0_SMMU0_INT20_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000238,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int20_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int20_mask",
+			SMMU0_SMMU0_SMMU0_INT20_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000023c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int20_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int20_status",
+			SMMU0_SMMU0_SMMU0_INT20_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000240,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int20_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int21_en",
+			SMMU0_SMMU0_SMMU0_INT21_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000244,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int21_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int21_mask",
+			SMMU0_SMMU0_SMMU0_INT21_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000248,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int21_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int21_status",
+			SMMU0_SMMU0_SMMU0_INT21_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000024c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int21_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int22_en",
+			SMMU0_SMMU0_SMMU0_INT22_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000250,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int22_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int22_mask",
+			SMMU0_SMMU0_SMMU0_INT22_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000254,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int22_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int22_status",
+			SMMU0_SMMU0_SMMU0_INT22_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000258,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int22_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int23_en",
+			SMMU0_SMMU0_SMMU0_INT23_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000025c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int23_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int23_mask",
+			SMMU0_SMMU0_SMMU0_INT23_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000260,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int23_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int23_status",
+			SMMU0_SMMU0_SMMU0_INT23_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000264,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int23_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int24_en",
+			SMMU0_SMMU0_SMMU0_INT24_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000268,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int24_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int24_mask",
+			SMMU0_SMMU0_SMMU0_INT24_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000026c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int24_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int24_status",
+			SMMU0_SMMU0_SMMU0_INT24_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000270,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int24_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int25_en",
+			SMMU0_SMMU0_SMMU0_INT25_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000274,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int25_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int25_mask",
+			SMMU0_SMMU0_SMMU0_INT25_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000278,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int25_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int25_status",
+			SMMU0_SMMU0_SMMU0_INT25_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000027c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int25_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int26_en",
+			SMMU0_SMMU0_SMMU0_INT26_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000280,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int26_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int26_mask",
+			SMMU0_SMMU0_SMMU0_INT26_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000284,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int26_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int26_status",
+			SMMU0_SMMU0_SMMU0_INT26_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000288,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int26_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int27_en",
+			SMMU0_SMMU0_SMMU0_INT27_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000028c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int27_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int27_mask",
+			SMMU0_SMMU0_SMMU0_INT27_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000290,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int27_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int27_status",
+			SMMU0_SMMU0_SMMU0_INT27_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000294,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int27_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int28_en",
+			SMMU0_SMMU0_SMMU0_INT28_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000298,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int28_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int28_mask",
+			SMMU0_SMMU0_SMMU0_INT28_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000029c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int28_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int28_status",
+			SMMU0_SMMU0_SMMU0_INT28_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int28_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int29_en",
+			SMMU0_SMMU0_SMMU0_INT29_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int29_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int29_mask",
+			SMMU0_SMMU0_SMMU0_INT29_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int29_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int29_status",
+			SMMU0_SMMU0_SMMU0_INT29_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int29_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int30_en",
+			SMMU0_SMMU0_SMMU0_INT30_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int30_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int30_mask",
+			SMMU0_SMMU0_SMMU0_INT30_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int30_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int30_status",
+			SMMU0_SMMU0_SMMU0_INT30_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int30_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int31_en",
+			SMMU0_SMMU0_SMMU0_INT31_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int31_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int31_mask",
+			SMMU0_SMMU0_SMMU0_INT31_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int31_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int31_status",
+			SMMU0_SMMU0_SMMU0_INT31_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int31_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int32_en",
+			SMMU0_SMMU0_SMMU0_INT32_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int32_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int32_mask",
+			SMMU0_SMMU0_SMMU0_INT32_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int32_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int32_status",
+			SMMU0_SMMU0_SMMU0_INT32_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int32_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int33_en",
+			SMMU0_SMMU0_SMMU0_INT33_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int33_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int33_mask",
+			SMMU0_SMMU0_SMMU0_INT33_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int33_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int33_status",
+			SMMU0_SMMU0_SMMU0_INT33_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int33_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int34_en",
+			SMMU0_SMMU0_SMMU0_INT34_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int34_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int34_mask",
+			SMMU0_SMMU0_SMMU0_INT34_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int34_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int34_status",
+			SMMU0_SMMU0_SMMU0_INT34_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_smmu0_int34_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int35_en",
+			SMMU0_SMMU0_SMMU0_INT35_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int35_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int35_mask",
+			SMMU0_SMMU0_SMMU0_INT35_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int35_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int35_status",
+			SMMU0_SMMU0_SMMU0_INT35_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int35_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int36_en",
+			SMMU0_SMMU0_SMMU0_INT36_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int36_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int36_mask",
+			SMMU0_SMMU0_SMMU0_INT36_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000002fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int36_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int36_status",
+			SMMU0_SMMU0_SMMU0_INT36_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000300,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int36_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int37_en",
+			SMMU0_SMMU0_SMMU0_INT37_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000304,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int37_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int37_mask",
+			SMMU0_SMMU0_SMMU0_INT37_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000308,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int37_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int37_status",
+			SMMU0_SMMU0_SMMU0_INT37_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000030c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int37_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int38_en",
+			SMMU0_SMMU0_SMMU0_INT38_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000310,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int38_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int38_mask",
+			SMMU0_SMMU0_SMMU0_INT38_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000314,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int38_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int38_status",
+			SMMU0_SMMU0_SMMU0_INT38_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000318,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int38_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int39_en",
+			SMMU0_SMMU0_SMMU0_INT39_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000036c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int39_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int39_mask",
+			SMMU0_SMMU0_SMMU0_INT39_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000370,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int39_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int39_status",
+			SMMU0_SMMU0_SMMU0_INT39_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000374,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int39_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int40_en",
+			SMMU0_SMMU0_SMMU0_INT40_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000378,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int40_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int40_mask",
+			SMMU0_SMMU0_SMMU0_INT40_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000037c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int40_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int40_status",
+			SMMU0_SMMU0_SMMU0_INT40_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000380,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int40_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int41_en",
+			SMMU0_SMMU0_SMMU0_INT41_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000384,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int41_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int41_mask",
+			SMMU0_SMMU0_SMMU0_INT41_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000388,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int41_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int41_status",
+			SMMU0_SMMU0_SMMU0_INT41_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000038c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int41_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int42_en",
+			SMMU0_SMMU0_SMMU0_INT42_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000390,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int42_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int42_mask",
+			SMMU0_SMMU0_SMMU0_INT42_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000394,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int42_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int42_status",
+			SMMU0_SMMU0_SMMU0_INT42_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000398,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int42_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int43_en",
+			SMMU0_SMMU0_SMMU0_INT43_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000039c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int43_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int43_mask",
+			SMMU0_SMMU0_SMMU0_INT43_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int43_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int43_status",
+			SMMU0_SMMU0_SMMU0_INT43_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int43_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int44_en",
+			SMMU0_SMMU0_SMMU0_INT44_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int44_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int44_mask",
+			SMMU0_SMMU0_SMMU0_INT44_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int44_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int44_status",
+			SMMU0_SMMU0_SMMU0_INT44_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int44_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int45_en",
+			SMMU0_SMMU0_SMMU0_INT45_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int45_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int45_mask",
+			SMMU0_SMMU0_SMMU0_INT45_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int45_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int45_status",
+			SMMU0_SMMU0_SMMU0_INT45_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int45_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int46_en",
+			SMMU0_SMMU0_SMMU0_INT46_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int46_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int46_mask",
+			SMMU0_SMMU0_SMMU0_INT46_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int46_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int46_status",
+			SMMU0_SMMU0_SMMU0_INT46_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int46_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int47_en",
+			SMMU0_SMMU0_SMMU0_INT47_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int47_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int47_mask",
+			SMMU0_SMMU0_SMMU0_INT47_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int47_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int47_status",
+			SMMU0_SMMU0_SMMU0_INT47_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int47_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int48_en",
+			SMMU0_SMMU0_SMMU0_INT48_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int48_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int48_mask",
+			SMMU0_SMMU0_SMMU0_INT48_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int48_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int48_status",
+			SMMU0_SMMU0_SMMU0_INT48_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int48_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int49_en",
+			SMMU0_SMMU0_SMMU0_INT49_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int49_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int49_mask",
+			SMMU0_SMMU0_SMMU0_INT49_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int49_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int49_status",
+			SMMU0_SMMU0_SMMU0_INT49_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int49_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int50_en",
+			SMMU0_SMMU0_SMMU0_INT50_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int50_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int50_mask",
+			SMMU0_SMMU0_SMMU0_INT50_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int50_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int50_status",
+			SMMU0_SMMU0_SMMU0_INT50_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int50_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int51_en",
+			SMMU0_SMMU0_SMMU0_INT51_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000003fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int51_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int51_mask",
+			SMMU0_SMMU0_SMMU0_INT51_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000400,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int51_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int51_status",
+			SMMU0_SMMU0_SMMU0_INT51_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000404,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int51_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int52_en",
+			SMMU0_SMMU0_SMMU0_INT52_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000408,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int52_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int52_mask",
+			SMMU0_SMMU0_SMMU0_INT52_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000040c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int52_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int52_status",
+			SMMU0_SMMU0_SMMU0_INT52_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000410,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_int52_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int53_en",
+			SMMU0_SMMU0_SMMU0_INT53_ENr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000414,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_smmu0_smmu0_smmu0_int53_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int53_mask",
+			SMMU0_SMMU0_SMMU0_INT53_MASKr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000418,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_smmu0_smmu0_smmu0_int53_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_int53_status",
+			SMMU0_SMMU0_SMMU0_INT53_STATUSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000041c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_smmu0_smmu0_smmu0_int53_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl0_arbiter_ecc_bypass",
+			SMMU0_SMMU0_CTRL0_ARBITER_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000031c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl0_arbiter_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl2_arbiter_ecc_bypass",
+			SMMU0_SMMU0_CTRL2_ARBITER_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000320,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl2_arbiter_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl4_arbiter_ecc_bypass",
+			SMMU0_SMMU0_CTRL4_ARBITER_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000324,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl4_arbiter_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl6_arbiter_ecc_bypass",
+			SMMU0_SMMU0_CTRL6_ARBITER_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000328,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl6_arbiter_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl8_arbiter_ecc_bypass",
+			SMMU0_SMMU0_CTRL8_ARBITER_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000032c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl8_arbiter_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl10_arbiter_ecc_bypass",
+			SMMU0_SMMU0_CTRL10_ARBITER_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000330,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl10_arbiter_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl12_arbiter_ecc_bypass",
+			SMMU0_SMMU0_CTRL12_ARBITER_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000334,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl12_arbiter_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl14_arbiter_ecc_bypass",
+			SMMU0_SMMU0_CTRL14_ARBITER_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000338,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl14_arbiter_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl16_arbiter_ecc_bypass",
+			SMMU0_SMMU0_CTRL16_ARBITER_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000033c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl16_arbiter_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl18_arbiter_ecc_bypass",
+			SMMU0_SMMU0_CTRL18_ARBITER_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000340,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl18_arbiter_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl20_arbiter_ecc_bypass",
+			SMMU0_SMMU0_CTRL20_ARBITER_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000344,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl20_arbiter_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl22_arbiter_ecc_bypass",
+			SMMU0_SMMU0_CTRL22_ARBITER_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000348,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl22_arbiter_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl24_arbiter_ecc_bypass",
+			SMMU0_SMMU0_CTRL24_ARBITER_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000034c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl24_arbiter_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl26_arbiter_ecc_bypass",
+			SMMU0_SMMU0_CTRL26_ARBITER_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000350,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl26_arbiter_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl28_arbiter_ecc_bypass",
+			SMMU0_SMMU0_CTRL28_ARBITER_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000354,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl28_arbiter_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl30_arbiter_ecc_bypass",
+			SMMU0_SMMU0_CTRL30_ARBITER_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000358,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl30_arbiter_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_req_ecc_bypass",
+			SMMU0_SMMU0_CTRL_REQ_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000035c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_ctrl_req_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_info_ecc_bypass",
+			SMMU0_SMMU0_CTRL_INFO_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000360,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_ctrl_info_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_rschd_ecc_bypass",
+			SMMU0_SMMU0_SMMU0_RSCHD_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000368,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_rschd_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_wr_ecc_bypass",
+			SMMU0_SMMU0_SMMU0_WR_ECC_BYPASSr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000364,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_smmu0_wr_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl0_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL0_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f50,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl0_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl1_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL1_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f54,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl1_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl2_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL2_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f58,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl2_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl3_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL3_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f5c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl3_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl4_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL4_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f60,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl4_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl5_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL5_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f64,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl5_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl6_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL6_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f68,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl6_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl7_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL7_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f6c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl7_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl8_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL8_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f70,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl8_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl9_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL9_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f74,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl9_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl10_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL10_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f78,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl10_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl11_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL11_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f7c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl11_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl12_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL12_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f80,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl12_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl13_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL13_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f84,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl13_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl14_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL14_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f88,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl14_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl15_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL15_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f8c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl15_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl16_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL16_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f90,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl16_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl17_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL17_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f94,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl17_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl18_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL18_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f98,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl18_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl19_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL19_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000f9c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl19_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl20_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL20_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fa0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl20_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl21_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL21_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fa4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl21_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl22_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL22_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fa8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl22_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl23_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL23_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl23_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl24_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL24_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fb0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl24_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl25_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL25_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fb4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl25_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl26_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL26_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fbc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl26_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl27_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL27_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fc0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl27_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl28_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL28_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fc4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl28_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl29_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL29_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fc8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl29_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl30_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL30_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fcc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl30_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl31_arbiter_ecc_err",
+			SMMU0_SMMU0_CTRL31_ARBITER_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fd0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_smmu0_smmu0_ctrl31_arbiter_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_req_ecc_single_err",
+			SMMU0_SMMU0_CTRL_REQ_ECC_SINGLE_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fd4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_ctrl_req_ecc_single_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_req_ecc_double_err",
+			SMMU0_SMMU0_CTRL_REQ_ECC_DOUBLE_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fd8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_ctrl_req_ecc_double_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_info_ecc_single_err",
+			SMMU0_SMMU0_CTRL_INFO_ECC_SINGLE_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fdc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_ctrl_info_ecc_single_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_info_ecc_double_err",
+			SMMU0_SMMU0_CTRL_INFO_ECC_DOUBLE_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fe0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_ctrl_info_ecc_double_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_wr_ecc_err",
+			SMMU0_SMMU0_SMMU0_WR_ECC_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fe4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_smmu0_smmu0_smmu0_wr_ecc_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_rschd_ecc_single_err",
+			SMMU0_SMMU0_SMMU0_RSCHD_ECC_SINGLE_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fe8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_rschd_ecc_single_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_rschd_ecc_double_err",
+			SMMU0_SMMU0_SMMU0_RSCHD_ECC_DOUBLE_ERRr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000fec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_rschd_ecc_double_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ord_fifo_empty",
+			SMMU0_SMMU0_ORD_FIFO_EMPTYr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000440,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_ord_fifo_empty_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"wr_arb_fifo_empty",
+			SMMU0_SMMU0_WR_ARB_FIFO_EMPTYr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000444,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_wr_arb_fifo_empty_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_fifo_empty0",
+			SMMU0_SMMU0_CTRL_FIFO_EMPTY0r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000448,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_smmu0_smmu0_ctrl_fifo_empty0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_fifo_empty1",
+			SMMU0_SMMU0_CTRL_FIFO_EMPTY1r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000044c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_smmu0_smmu0_ctrl_fifo_empty1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_fifo_empty2",
+			SMMU0_SMMU0_CTRL_FIFO_EMPTY2r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000450,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_smmu0_smmu0_ctrl_fifo_empty2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_fifo_empty3",
+			SMMU0_SMMU0_CTRL_FIFO_EMPTY3r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000454,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_smmu0_smmu0_ctrl_fifo_empty3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_fifo_empty4",
+			SMMU0_SMMU0_CTRL_FIFO_EMPTY4r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000560,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_smmu0_smmu0_ctrl_fifo_empty4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_fifo_empty5",
+			SMMU0_SMMU0_CTRL_FIFO_EMPTY5r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000564,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_smmu0_smmu0_ctrl_fifo_empty5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty0",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY0r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000458,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty1",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY1r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000045c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty2",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY2r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000460,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty3",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY3r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000464,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty4",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY4r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000468,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty5",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY5r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000046c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty6",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY6r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000470,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty7",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY7r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000474,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty8",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY8r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000478,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty9",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY9r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000047c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty10",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY10r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000480,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty11",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY11r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000484,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty12",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY12r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000488,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty13",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY13r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000048c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty14",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY14r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000490,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty15",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY15r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000494,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty16",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY16r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000498,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty17",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY17r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000049c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty18",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY18r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty19",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY19r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty19_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty20",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY20r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty20_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty21",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY21r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty21_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty22",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY22r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty22_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty23",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY23r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty23_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty24",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY24r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty24_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty25",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY25r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty25_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty26",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY26r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty27",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY27r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty27_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty28",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY28r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty28_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty29",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY29r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty29_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty30",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY30r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty30_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_empty31",
+			SMMU0_SMMU0_KSCHD_FIFO_EMPTY31r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_kschd_fifo_empty31_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty0",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY0r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty1",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY1r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty2",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY2r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty3",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY3r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty4",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY4r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty5",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY5r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty6",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY6r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty7",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY7r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty8",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY8r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty9",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY9r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000004fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty10",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY10r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000500,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty11",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY11r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000504,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty12",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY12r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000508,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty13",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY13r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000050c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty14",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY14r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000510,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty15",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY15r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000514,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty16",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY16r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000518,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty17",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY17r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000051c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty18",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY18r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000520,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty19",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY19r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000524,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty19_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty20",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY20r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000528,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty20_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty21",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY21r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000052c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty21_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty22",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY22r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000530,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty22_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty23",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY23r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000534,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty23_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty24",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY24r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000538,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty24_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty25",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY25r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000053c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty25_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty26",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY26r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000540,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty26_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty27",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY27r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000544,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty27_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty28",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY28r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000548,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty28_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty29",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY29r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000054c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty29_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty30",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY30r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000550,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty30_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty31",
+			SMMU0_SMMU0_RSCHD_FIFO_EMPTY31r,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000554,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_rschd_fifo_empty31_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ept_flag",
+			SMMU0_SMMU0_EPT_FLAGr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000558,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			9,
+			g_smmu0_smmu0_ept_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_soft_rst",
+			SMMU0_SMMU0_PPU_SOFT_RSTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000055c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_ppu_soft_rst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_as_mac_age_fc_cnt",
+			SMMU0_SMMU0_SMMU0_AS_MAC_AGE_FC_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000800,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_as_mac_age_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_marc_se_parser_fc_cnt",
+			SMMU0_SMMU0_SMMU0_MARC_SE_PARSER_FC_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000804,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_marc_se_parser_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"wr_arb_cpu_fc_cnt",
+			SMMU0_SMMU0_WR_ARB_CPU_FC_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000808,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_wr_arb_cpu_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_lpm_as_fc_cnt",
+			SMMU0_SMMU0_SMMU0_LPM_AS_FC_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000080c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_lpm_as_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_as_smmu0_fc_cnt",
+			SMMU0_SMMU0_LPM_AS_SMMU0_FC_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000810,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_lpm_as_smmu0_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_etcam1_0_as_fc_cnt",
+			SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_FC_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000814,
+			(32 / 8),
+			0,
+			1 + 1,
+			0,
+			4,
+			1,
+			g_smmu0_smmu0_smmu0_etcam1_0_as_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_etcam1_0_smmu0_fc_cnt",
+			SMMU0_SMMU0_AS_ETCAM1_0_SMMU0_FC_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000081c,
+			(32 / 8),
+			0,
+			1 + 1,
+			0,
+			4,
+			1,
+			g_smmu0_smmu0_as_etcam1_0_smmu0_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_ppu_mcast_fc_cnt",
+			SMMU0_SMMU0_SMMU0_PPU_MCAST_FC_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000824,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_ppu_mcast_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_smmu0_mcast_fc_cnt",
+			SMMU0_SMMU0_PPU_SMMU0_MCAST_FC_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000828,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_ppu_smmu0_mcast_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_smmu0_tdm_fc_rsp_fc_cnt",
+			SMMU0_SMMU0_ODMA_SMMU0_TDM_FC_RSP_FC_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000082c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_odma_smmu0_tdm_fc_rsp_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_odma_tdm_fc_key_fc_cnt",
+			SMMU0_SMMU0_SMMU0_ODMA_TDM_FC_KEY_FC_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000830,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_odma_tdm_fc_key_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_odma_fc_cnt",
+			SMMU0_SMMU0_SMMU0_ODMA_FC_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000834,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_odma_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_cfg_tab_rd_fc_cnt",
+			SMMU0_SMMU0_SMMU0_CFG_TAB_RD_FC_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000838,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_cfg_tab_rd_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_stat_fc15_0_cnt",
+			SMMU0_SMMU0_SMMU0_STAT_FC15_0_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000083c,
+			(32 / 8),
+			0,
+			15 + 1,
+			0,
+			4,
+			1,
+			g_smmu0_smmu0_smmu0_stat_fc15_0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_smmu0_fc15_0_cnt",
+			SMMU0_SMMU0_STAT_SMMU0_FC15_0_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000087c,
+			(32 / 8),
+			0,
+			15 + 1,
+			0,
+			4,
+			1,
+			g_smmu0_smmu0_stat_smmu0_fc15_0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_ppu_mex5_0_fc_cnt",
+			SMMU0_SMMU0_SMMU0_PPU_MEX5_0_FC_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008bc,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_smmu0_smmu0_smmu0_ppu_mex5_0_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_smmu0_mex5_0_fc_cnt",
+			SMMU0_SMMU0_PPU_SMMU0_MEX5_0_FC_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008d4,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_smmu0_smmu0_ppu_smmu0_mex5_0_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_smmu0_mac_age_req_cnt",
+			SMMU0_SMMU0_AS_SMMU0_MAC_AGE_REQ_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_as_smmu0_mac_age_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_parser_smmu0_marc_key_cnt",
+			SMMU0_SMMU0_SE_PARSER_SMMU0_MARC_KEY_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_se_parser_smmu0_marc_key_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_rdat_cnt",
+			SMMU0_SMMU0_CPU_IND_RDAT_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cpu_ind_rdat_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_rd_req_cnt",
+			SMMU0_SMMU0_CPU_IND_RD_REQ_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cpu_ind_rd_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wr_req_cnt",
+			SMMU0_SMMU0_CPU_IND_WR_REQ_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000008fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cpu_ind_wr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_plcr_rsp0_cnt",
+			SMMU0_SMMU0_SMMU0_PLCR_RSP0_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000900,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_plcr_rsp0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"plcr_smmu0_req0_cnt",
+			SMMU0_SMMU0_PLCR_SMMU0_REQ0_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000904,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_plcr_smmu0_req0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_lpm_as_rsp_cnt",
+			SMMU0_SMMU0_SMMU0_LPM_AS_RSP_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000908,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_lpm_as_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_as_smmu0_req_cnt",
+			SMMU0_SMMU0_LPM_AS_SMMU0_REQ_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000090c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_lpm_as_smmu0_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_etcam1_0_as_rsp_cnt",
+			SMMU0_SMMU0_SMMU0_ETCAM1_0_AS_RSP_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000910,
+			(32 / 8),
+			0,
+			1 + 1,
+			0,
+			4,
+			1,
+			g_smmu0_smmu0_smmu0_etcam1_0_as_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam1_0_as_smmu0_req_cnt",
+			SMMU0_SMMU0_ETCAM1_0_AS_SMMU0_REQ_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000918,
+			(32 / 8),
+			0,
+			1 + 1,
+			0,
+			4,
+			1,
+			g_smmu0_smmu0_etcam1_0_as_smmu0_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_ppu_mcast_rsp_cnt",
+			SMMU0_SMMU0_SMMU0_PPU_MCAST_RSP_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000920,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_ppu_mcast_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_smmu0_mcast_key_cnt",
+			SMMU0_SMMU0_PPU_SMMU0_MCAST_KEY_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000924,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_ppu_smmu0_mcast_key_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_odma_tdm_mc_rsp_cnt",
+			SMMU0_SMMU0_SMMU0_ODMA_TDM_MC_RSP_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000928,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_odma_tdm_mc_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_smmu0_tdm_mc_key_cnt",
+			SMMU0_SMMU0_ODMA_SMMU0_TDM_MC_KEY_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000092c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_odma_smmu0_tdm_mc_key_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_odma_rsp_cnt",
+			SMMU0_SMMU0_SMMU0_ODMA_RSP_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000930,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_odma_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"odma_smmu0_cmd_cnt",
+			SMMU0_SMMU0_ODMA_SMMU0_CMD_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000934,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_odma_smmu0_cmd_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_cfg_tab_rdat_cnt",
+			SMMU0_SMMU0_SMMU0_CFG_TAB_RDAT_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000938,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_smmu0_cfg_tab_rdat_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_smmu0_tab_rd_cnt",
+			SMMU0_SMMU0_CFG_SMMU0_TAB_RD_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x0000093c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_cfg_smmu0_tab_rd_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_stat_rsp15_0_cnt",
+			SMMU0_SMMU0_SMMU0_STAT_RSP15_0_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000940,
+			(32 / 8),
+			0,
+			15 + 1,
+			0,
+			4,
+			1,
+			g_smmu0_smmu0_smmu0_stat_rsp15_0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_smmu0_req15_0_cnt",
+			SMMU0_SMMU0_STAT_SMMU0_REQ15_0_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000980,
+			(32 / 8),
+			0,
+			15 + 1,
+			0,
+			4,
+			1,
+			g_smmu0_smmu0_stat_smmu0_req15_0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_ppu_mex5_0_rsp_cnt",
+			SMMU0_SMMU0_SMMU0_PPU_MEX5_0_RSP_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009c0,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_smmu0_smmu0_smmu0_ppu_mex5_0_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_smmu0_mex5_0_key_cnt",
+			SMMU0_SMMU0_PPU_SMMU0_MEX5_0_KEY_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009d8,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_smmu0_smmu0_ppu_smmu0_mex5_0_key_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ftm_stat_smmu0_req0_cnt",
+			SMMU0_SMMU0_FTM_STAT_SMMU0_REQ0_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_ftm_stat_smmu0_req0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ftm_stat_smmu0_req1_cnt",
+			SMMU0_SMMU0_FTM_STAT_SMMU0_REQ1_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_ftm_stat_smmu0_req1_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_stat_smmu0_req0_cnt",
+			SMMU0_SMMU0_ETM_STAT_SMMU0_REQ0_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_etm_stat_smmu0_req0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_stat_smmu0_req1_cnt",
+			SMMU0_SMMU0_ETM_STAT_SMMU0_REQ1_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x000009fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_smmu0_smmu0_etm_stat_smmu0_req1_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"req_eram0_31_rd_cnt",
+			SMMU0_SMMU0_REQ_ERAM0_31_RD_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000a00,
+			(32 / 8),
+			0,
+			31 + 1,
+			0,
+			8,
+			1,
+			g_smmu0_smmu0_req_eram0_31_rd_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"req_eram0_31_wr_cnt",
+			SMMU0_SMMU0_REQ_ERAM0_31_WR_CNTr,
+			SMMU0,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU0_BASE_ADDR + MODULE_SE_SMMU0_BASE_ADDR + 0x00000a04,
+			(32 / 8),
+			0,
+			31 + 1,
+			0,
+			8,
+			1,
+			g_smmu0_smmu0_req_eram0_31_wr_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wdat1",
+			SE_SMMU1_DDR_WDAT1r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ddr_wdat1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wdat2",
+			SE_SMMU1_DDR_WDAT2r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ddr_wdat2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wdat3",
+			SE_SMMU1_DDR_WDAT3r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ddr_wdat3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wdat4",
+			SE_SMMU1_DDR_WDAT4r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ddr_wdat4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wdat5",
+			SE_SMMU1_DDR_WDAT5r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ddr_wdat5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wdat6",
+			SE_SMMU1_DDR_WDAT6r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ddr_wdat6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wdat7",
+			SE_SMMU1_DDR_WDAT7r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ddr_wdat7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wdat8",
+			SE_SMMU1_DDR_WDAT8r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ddr_wdat8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wdat9",
+			SE_SMMU1_DDR_WDAT9r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ddr_wdat9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wdat10",
+			SE_SMMU1_DDR_WDAT10r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ddr_wdat10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wdat11",
+			SE_SMMU1_DDR_WDAT11r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000002c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ddr_wdat11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wdat12",
+			SE_SMMU1_DDR_WDAT12r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ddr_wdat12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wdat13",
+			SE_SMMU1_DDR_WDAT13r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ddr_wdat13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wdat14",
+			SE_SMMU1_DDR_WDAT14r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ddr_wdat14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wdat15",
+			SE_SMMU1_DDR_WDAT15r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000003c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ddr_wdat15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_stat_cache_en",
+			SE_SMMU1_CNT_STAT_CACHE_ENr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cnt_stat_cache_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_stat_cache_clr",
+			SE_SMMU1_CNT_STAT_CACHE_CLRr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cnt_stat_cache_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_stat_cache_req_63_32",
+			SE_SMMU1_CNT_STAT_CACHE_REQ_63_32r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cnt_stat_cache_req_63_32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_stat_cache_req_31_0",
+			SE_SMMU1_CNT_STAT_CACHE_REQ_31_0r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cnt_stat_cache_req_31_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_stat_cache_hit_63_32",
+			SE_SMMU1_CNT_STAT_CACHE_HIT_63_32r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cnt_stat_cache_hit_63_32_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_stat_cache_hit_31_0",
+			SE_SMMU1_CNT_STAT_CACHE_HIT_31_0r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cnt_stat_cache_hit_31_0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_cmd0",
+			SE_SMMU1_DDR_CMD0r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_se_smmu1_ddr_cmd0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_addr",
+			SE_SMMU1_INFO_ADDRr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_info_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_cmd1",
+			SE_SMMU1_DDR_CMD1r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_smmu1_ddr_cmd1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"clr_start_addr",
+			SE_SMMU1_CLR_START_ADDRr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000006c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_clr_start_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"clr_end_addr",
+			SE_SMMU1_CLR_END_ADDRr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000070,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_clr_end_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"clr_tbl_en",
+			SE_SMMU1_CLR_TBL_ENr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000074,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_smmu1_clr_tbl_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_mode",
+			SE_SMMU1_DEBUG_CNT_MODEr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_smmu1_debug_cnt_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"init_done",
+			SE_SMMU1_INIT_DONEr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_se_smmu1_init_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rsp_rd_done",
+			SE_SMMU1_CPU_RSP_RD_DONEr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000008c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rsp_rd_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ksch_oam_sp_en",
+			SE_SMMU1_KSCH_OAM_SP_ENr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ksch_oam_sp_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_cache_en",
+			SE_SMMU1_CFG_CACHE_ENr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cfg_cache_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cache_age_en",
+			SE_SMMU1_CACHE_AGE_ENr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cache_age_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat0",
+			SE_SMMU1_CPU_RDAT0r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rdat0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat1",
+			SE_SMMU1_CPU_RDAT1r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rdat1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat2",
+			SE_SMMU1_CPU_RDAT2r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rdat2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat3",
+			SE_SMMU1_CPU_RDAT3r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rdat3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat4",
+			SE_SMMU1_CPU_RDAT4r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rdat4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat5",
+			SE_SMMU1_CPU_RDAT5r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rdat5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat6",
+			SE_SMMU1_CPU_RDAT6r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rdat6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat7",
+			SE_SMMU1_CPU_RDAT7r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rdat7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat8",
+			SE_SMMU1_CPU_RDAT8r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rdat8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat9",
+			SE_SMMU1_CPU_RDAT9r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rdat9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat10",
+			SE_SMMU1_CPU_RDAT10r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rdat10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat11",
+			SE_SMMU1_CPU_RDAT11r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rdat11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat12",
+			SE_SMMU1_CPU_RDAT12r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rdat12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat13",
+			SE_SMMU1_CPU_RDAT13r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rdat13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat14",
+			SE_SMMU1_CPU_RDAT14r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rdat14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rdat15",
+			SE_SMMU1_CPU_RDAT15r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000000fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rdat15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_cpu_rd_rdy",
+			SE_SMMU1_CTRL_CPU_RD_RDYr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000100,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ctrl_cpu_rd_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_warbi_rdy_cfg",
+			SE_SMMU1_CPU_WARBI_RDY_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000104,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_warbi_rdy_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dir_arbi_cpu_rpful",
+			SE_SMMU1_DIR_ARBI_CPU_RPFULr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000108,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_smmu1_dir_arbi_cpu_rpful_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dir_arbi_wpful",
+			SE_SMMU1_DIR_ARBI_WPFULr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000110,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_smmu1_dir_arbi_wpful_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_wr_arbi_pful0",
+			SE_SMMU1_CFG_WR_ARBI_PFUL0r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000118,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_smmu1_cfg_wr_arbi_pful0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_wr_arbi_pful1",
+			SE_SMMU1_CFG_WR_ARBI_PFUL1r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000011c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_smmu1_cfg_wr_arbi_pful1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_wdone_pful_cfg",
+			SE_SMMU1_SMMU1_WDONE_PFUL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000124,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_wdone_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_rate_cfg_cnt",
+			SE_SMMU1_STAT_RATE_CFG_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000128,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_stat_rate_cfg_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ftm_rate_cfg_cnt",
+			SE_SMMU1_FTM_RATE_CFG_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000012c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ftm_rate_cfg_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_rate_cfg_cnt",
+			SE_SMMU1_ETM_RATE_CFG_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000130,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_etm_rate_cfg_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dir_rate_cfg_cnt",
+			SE_SMMU1_DIR_RATE_CFG_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000134,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_dir_rate_cfg_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_rate_cfg_cnt",
+			SE_SMMU1_HASH_RATE_CFG_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000138,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_hash_rate_cfg_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ftm_tbl_cfg",
+			SE_SMMU1_FTM_TBL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ftm_tbl_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_v4_as_tbl_cfg",
+			SE_SMMU1_LPM_V4_AS_TBL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_se_smmu1_lpm_v4_as_tbl_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_v4_tbl_cfg",
+			SE_SMMU1_LPM_V4_TBL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_se_smmu1_lpm_v4_tbl_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_v6_tbl_cfg",
+			SE_SMMU1_LPM_V6_TBL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_se_smmu1_lpm_v6_tbl_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_v6_as_tbl_cfg",
+			SE_SMMU1_LPM_V6_AS_TBL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_se_smmu1_lpm_v6_as_tbl_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_tbl_cfg",
+			SE_SMMU1_DMA_TBL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_dma_tbl_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_tbl_cfg",
+			SE_SMMU1_OAM_TBL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_oam_tbl_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_rpar_cpu_pful",
+			SE_SMMU1_CTRL_RPAR_CPU_PFULr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ctrl_rpar_cpu_pful_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ksch_dir_pful",
+			SE_SMMU1_CFG_KSCH_DIR_PFULr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cfg_ksch_dir_pful_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ksch_hash_pful",
+			SE_SMMU1_CFG_KSCH_HASH_PFULr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cfg_ksch_hash_pful_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ksch_lpm_pful",
+			SE_SMMU1_CFG_KSCH_LPM_PFULr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cfg_ksch_lpm_pful_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ksch_lpm_as_pful",
+			SE_SMMU1_CFG_KSCH_LPM_AS_PFULr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cfg_ksch_lpm_as_pful_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ksch_stat_pful",
+			SE_SMMU1_CFG_KSCH_STAT_PFULr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cfg_ksch_stat_pful_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ksch_tm_pful",
+			SE_SMMU1_CFG_KSCH_TM_PFULr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000200,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cfg_ksch_tm_pful_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ksch_oam_pful",
+			SE_SMMU1_CFG_KSCH_OAM_PFULr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000204,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cfg_ksch_oam_pful_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ksch_dma_pful",
+			SE_SMMU1_CFG_KSCH_DMA_PFULr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000208,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cfg_ksch_dma_pful_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_wfifo_cfg",
+			SE_SMMU1_CTRL_WFIFO_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000230,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ctrl_wfifo_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsch_hash_ptr_cfg",
+			SE_SMMU1_RSCH_HASH_PTR_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000240,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_rsch_hash_ptr_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsch_lpm_ptr_cfg",
+			SE_SMMU1_RSCH_LPM_PTR_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000244,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_rsch_lpm_ptr_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsch_lpm_as_ptr_cfg",
+			SE_SMMU1_RSCH_LPM_AS_PTR_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000248,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_rsch_lpm_as_ptr_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsch_stat_ptr_cfg",
+			SE_SMMU1_RSCH_STAT_PTR_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000024c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_rsch_stat_ptr_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rsch_oam_ptr_cfg",
+			SE_SMMU1_RSCH_OAM_PTR_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000250,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_rsch_oam_ptr_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_pept_cfg",
+			SE_SMMU1_RSCHD_FIFO_PEPT_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000254,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_rschd_fifo_pept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dir_fifo_pful_cfg",
+			SE_SMMU1_DIR_FIFO_PFUL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000258,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_dir_fifo_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash_fifo_pful_cfg",
+			SE_SMMU1_HASH_FIFO_PFUL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000025c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_hash_fifo_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_fifo_pful_cfg",
+			SE_SMMU1_LPM_FIFO_PFUL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000260,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_lpm_fifo_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_as_fifo_pful_cfg",
+			SE_SMMU1_LPM_AS_FIFO_PFUL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000264,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_lpm_as_fifo_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_fifo_pful_cfg",
+			SE_SMMU1_STAT_FIFO_PFUL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000268,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_stat_fifo_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ftm_fifo_pful_cfg",
+			SE_SMMU1_FTM_FIFO_PFUL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000026c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ftm_fifo_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_fifo_pful_cfg",
+			SE_SMMU1_ETM_FIFO_PFUL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000270,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_etm_fifo_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_fifo_pful_cfg",
+			SE_SMMU1_OAM_FIFO_PFUL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000274,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_oam_fifo_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_fifo_pful_cfg",
+			SE_SMMU1_DMA_FIFO_PFUL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000278,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_dma_fifo_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cache_rsp_rr_fifo_cfg",
+			SE_SMMU1_CACHE_RSP_RR_FIFO_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000027c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_smmu1_cache_rsp_rr_fifo_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_rsp_rr_fifo_cfg",
+			SE_SMMU1_DDR_RSP_RR_FIFO_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000280,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_smmu1_ddr_rsp_rr_fifo_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_cahce_fifo_cfg",
+			SE_SMMU1_CPU_CAHCE_FIFO_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000284,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_smmu1_cpu_cahce_fifo_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cache_rsp_fifo_cfg",
+			SE_SMMU1_CACHE_RSP_FIFO_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000028c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_smmu1_cache_rsp_fifo_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_state",
+			SE_SMMU1_TEST_STATEr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000002c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_test_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cache_fifo_ept",
+			SE_SMMU1_CACHE_FIFO_EPTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000002f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cache_fifo_ept_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rr_fifo_ept",
+			SE_SMMU1_RR_FIFO_EPTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000002fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_rr_fifo_ept_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"wr_fifo_ept",
+			SE_SMMU1_WR_FIFO_EPTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000304,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_wr_fifo_ept_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"wdone_fifo_ept",
+			SE_SMMU1_WDONE_FIFO_EPTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000308,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_wdone_fifo_ept_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_fifo_ept0",
+			SE_SMMU1_KSCHD_FIFO_EPT0r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000318,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_kschd_fifo_ept0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cash_fifo_ept",
+			SE_SMMU1_CASH_FIFO_EPTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000031c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cash_fifo_ept_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_fifo_ept",
+			SE_SMMU1_CTRL_FIFO_EPTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000320,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ctrl_fifo_ept_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_rschd_ept3",
+			SE_SMMU1_SMMU1_RSCHD_EPT3r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000324,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_rschd_ept3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_rschd_ept2",
+			SE_SMMU1_SMMU1_RSCHD_EPT2r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000328,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_rschd_ept2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_rschd_ept1",
+			SE_SMMU1_SMMU1_RSCHD_EPT1r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000032c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_rschd_ept1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_rschd_ept0",
+			SE_SMMU1_SMMU1_RSCHD_EPT0r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000330,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_rschd_ept0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cash0_ecc_err_addr",
+			SE_SMMU1_CASH0_ECC_ERR_ADDRr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000334,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cash0_ecc_err_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"arbi_cpu_wr_rdy",
+			SE_SMMU1_ARBI_CPU_WR_RDYr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000354,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_arbi_cpu_wr_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_int_0_en",
+			SE_SMMU1_SMMU1_INT_0_ENr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000480,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_int_0_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_int_0_mask",
+			SE_SMMU1_SMMU1_INT_0_MASKr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000484,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_int_0_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_int_1_en",
+			SE_SMMU1_SMMU1_INT_1_ENr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000488,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_int_1_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_int_1_mask",
+			SE_SMMU1_SMMU1_INT_1_MASKr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000048c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_int_1_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_int_2_en",
+			SE_SMMU1_SMMU1_INT_2_ENr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000490,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_int_2_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_int_2_mask",
+			SE_SMMU1_SMMU1_INT_2_MASKr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000494,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_int_2_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_int_3_en",
+			SE_SMMU1_SMMU1_INT_3_ENr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000498,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_int_3_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_int_3_mask",
+			SE_SMMU1_SMMU1_INT_3_MASKr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000049c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_int_3_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_int_0_status",
+			SE_SMMU1_SMMU1_INT_0_STATUSr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000540,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_int_0_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_int_1_status",
+			SE_SMMU1_SMMU1_INT_1_STATUSr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000544,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_int_1_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_int_2_status",
+			SE_SMMU1_SMMU1_INT_2_STATUSr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000548,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_int_2_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_int_3_status",
+			SE_SMMU1_SMMU1_INT_3_STATUSr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000054c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_int_3_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_int_status",
+			SE_SMMU1_SMMU1_INT_STATUSr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000005a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_to_cash7_0_fc_cnt",
+			SE_SMMU1_CTRL_TO_CASH7_0_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000600,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			24,
+			1,
+			g_se_smmu1_ctrl_to_cash7_0_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cash7_0_to_ctrl_req_cnt",
+			SE_SMMU1_CASH7_0_TO_CTRL_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000604,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			24,
+			1,
+			g_se_smmu1_cash7_0_to_ctrl_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_to_cache7_fc_cnt",
+			SE_SMMU1_RSCHD_TO_CACHE7_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000608,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			24,
+			1,
+			g_se_smmu1_rschd_to_cache7_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cash7_to_cache_rsp_cnt",
+			SE_SMMU1_CASH7_TO_CACHE_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000060c,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			24,
+			1,
+			g_se_smmu1_cash7_to_cache_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cash7_to_ctrl_fc_cnt",
+			SE_SMMU1_CASH7_TO_CTRL_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000610,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			24,
+			1,
+			g_se_smmu1_cash7_to_ctrl_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl_to_cash7_0_rsp_cnt",
+			SE_SMMU1_CTRL_TO_CASH7_0_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000614,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			24,
+			1,
+			g_se_smmu1_ctrl_to_cash7_0_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_to_cache7_0_req_cnt",
+			SE_SMMU1_KSCHD_TO_CACHE7_0_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000006c0,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_kschd_to_cache7_0_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cache7_0_to_kschd_fc_cnt",
+			SE_SMMU1_CACHE7_0_TO_KSCHD_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000006e0,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_cache7_0_to_kschd_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dma_to_smmu1_rd_req_cnt",
+			SE_SMMU1_DMA_TO_SMMU1_RD_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000700,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_dma_to_smmu1_rd_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_to_kschd_req_cnt",
+			SE_SMMU1_OAM_TO_KSCHD_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000704,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_oam_to_kschd_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_rr_state_rsp_cnt",
+			SE_SMMU1_OAM_RR_STATE_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000708,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_oam_rr_state_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_clash_info_cnt",
+			SE_SMMU1_OAM_CLASH_INFO_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000070c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_oam_clash_info_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_to_rr_req_cnt",
+			SE_SMMU1_OAM_TO_RR_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000710,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_oam_to_rr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_as_to_kschd_req_cnt",
+			SE_SMMU1_LPM_AS_TO_KSCHD_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000714,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_lpm_as_to_kschd_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_as_rr_state_rsp_cnt",
+			SE_SMMU1_LPM_AS_RR_STATE_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000718,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_lpm_as_rr_state_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_as_clash_info_cnt",
+			SE_SMMU1_LPM_AS_CLASH_INFO_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000071c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_lpm_as_clash_info_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_as_to_rr_req_cnt",
+			SE_SMMU1_LPM_AS_TO_RR_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000720,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_lpm_as_to_rr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_to_kschd_req_cnt",
+			SE_SMMU1_LPM_TO_KSCHD_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000724,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_lpm_to_kschd_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_rr_state_rsp_cnt",
+			SE_SMMU1_LPM_RR_STATE_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000728,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_lpm_rr_state_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_clash_info_cnt",
+			SE_SMMU1_LPM_CLASH_INFO_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000072c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_lpm_clash_info_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_to_rr_req_cnt",
+			SE_SMMU1_LPM_TO_RR_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000730,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_lpm_to_rr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_0_to_kschd_req_cnt",
+			SE_SMMU1_HASH3_0_TO_KSCHD_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000734,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			16,
+			1,
+			g_se_smmu1_hash3_0_to_kschd_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_0_rr_state_rsp_cnt",
+			SE_SMMU1_HASH3_0_RR_STATE_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000738,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			16,
+			1,
+			g_se_smmu1_hash3_0_rr_state_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_0_clash_info_cnt",
+			SE_SMMU1_HASH3_0_CLASH_INFO_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000073c,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			16,
+			1,
+			g_se_smmu1_hash3_0_clash_info_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_0_to_rr_req_cnt",
+			SE_SMMU1_HASH3_0_TO_RR_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000740,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			16,
+			1,
+			g_se_smmu1_hash3_0_to_rr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dir3_0_to_kschd_req_cnt",
+			SE_SMMU1_DIR3_0_TO_KSCHD_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000774,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			8,
+			1,
+			g_se_smmu1_dir3_0_to_kschd_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dir3_0_clash_info_cnt",
+			SE_SMMU1_DIR3_0_CLASH_INFO_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000778,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			8,
+			1,
+			g_se_smmu1_dir3_0_clash_info_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dir_tbl_wr_req_cnt",
+			SE_SMMU1_DIR_TBL_WR_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000794,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_dir_tbl_wr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"warbi_to_dir_tbl_warbi_fc_cnt",
+			SE_SMMU1_WARBI_TO_DIR_TBL_WARBI_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000798,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_warbi_to_dir_tbl_warbi_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dir3_0_to_bank_rr_req_cnt",
+			SE_SMMU1_DIR3_0_TO_BANK_RR_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000079c,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_dir3_0_to_bank_rr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"kschd_to_dir3_0_fc_cnt",
+			SE_SMMU1_KSCHD_TO_DIR3_0_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007ac,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_kschd_to_dir3_0_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dir3_0_rr_state_rsp_cnt",
+			SE_SMMU1_DIR3_0_RR_STATE_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007bc,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_dir3_0_rr_state_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"wr_done_to_warbi_fc_cnt",
+			SE_SMMU1_WR_DONE_TO_WARBI_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_wr_done_to_warbi_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"wr_done_ptr_req_cnt",
+			SE_SMMU1_WR_DONE_PTR_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_wr_done_ptr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl7_0_to_warbi_fc_cnt",
+			SE_SMMU1_CTRL7_0_TO_WARBI_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007d4,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_ctrl7_0_to_warbi_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"warbi_to_ctrl7_0_wr_req_cnt",
+			SE_SMMU1_WARBI_TO_CTRL7_0_WR_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000007f4,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_warbi_to_ctrl7_0_wr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"warbi_to_cash7_0_wr_req_cnt",
+			SE_SMMU1_WARBI_TO_CASH7_0_WR_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000814,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_warbi_to_cash7_0_wr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"warbi_to_cpu_wr_fc_cnt",
+			SE_SMMU1_WARBI_TO_CPU_WR_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000834,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_warbi_to_cpu_wr_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_wr_req_cnt",
+			SE_SMMU1_CPU_WR_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000838,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_wr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ctrl7_0_to_cpu_rd_rsp_cnt",
+			SE_SMMU1_CTRL7_0_TO_CPU_RD_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000083c,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_ctrl7_0_to_cpu_rd_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_to_ctrl7_0_rd_req_cnt",
+			SE_SMMU1_CPU_TO_CTRL7_0_RD_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000085c,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_cpu_to_ctrl7_0_rd_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_dir_tbl_rsp_cnt",
+			SE_SMMU1_CPU_RD_DIR_TBL_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000087c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_rd_dir_tbl_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_to_dir_tbl_rd_wr_req_cnt",
+			SE_SMMU1_CPU_TO_DIR_TBL_RD_WR_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000880,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_cpu_to_dir_tbl_rd_wr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_mmu_7_0_rsp_fc_cnt",
+			SE_SMMU1_SMMU1_TO_MMU_7_0_RSP_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000884,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			24,
+			1,
+			g_se_smmu1_smmu1_to_mmu_7_0_rsp_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mmu_7_0_to_smmu1_rd_rsp_cnt",
+			SE_SMMU1_MMU_7_0_TO_SMMU1_RD_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000888,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			24,
+			1,
+			g_se_smmu1_mmu_7_0_to_smmu1_rd_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mmu_7_0_to_smmu1_rd_fc_cnt",
+			SE_SMMU1_MMU_7_0_TO_SMMU1_RD_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000088c,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			24,
+			1,
+			g_se_smmu1_mmu_7_0_to_smmu1_rd_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_mmu_7_rd_req_cnt",
+			SE_SMMU1_SMMU1_TO_MMU_7_RD_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000890,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			24,
+			1,
+			g_se_smmu1_smmu1_to_mmu_7_rd_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"mmu_7_to_smmu1_wr_fc_cnt",
+			SE_SMMU1_MMU_7_TO_SMMU1_WR_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000894,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			24,
+			1,
+			g_se_smmu1_mmu_7_to_smmu1_wr_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_mmu_7_0_wr_req_cnt",
+			SE_SMMU1_SMMU1_TO_MMU_7_0_WR_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000898,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			24,
+			1,
+			g_se_smmu1_smmu1_to_mmu_7_0_wr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_to_smmu1_wr_rsp_fc_cnt",
+			SE_SMMU1_SE_TO_SMMU1_WR_RSP_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000944,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_se_to_smmu1_wr_rsp_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_se_wr_rsp_cnt",
+			SE_SMMU1_SMMU1_TO_SE_WR_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000948,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_se_wr_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr7_0_wr_rsp_cnt",
+			SE_SMMU1_DDR7_0_WR_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000094c,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_ddr7_0_wr_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_as_fc_cnt",
+			SE_SMMU1_SMMU1_TO_AS_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000096c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_as_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_to_smmu1_wr_req_cnt",
+			SE_SMMU1_AS_TO_SMMU1_WR_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000970,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_as_to_smmu1_wr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_se_parser_fc_cnt",
+			SE_SMMU1_SMMU1_TO_SE_PARSER_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000974,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_se_parser_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_parser_to_smmu1_req_cnt",
+			SE_SMMU1_SE_PARSER_TO_SMMU1_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000978,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_se_parser_to_smmu1_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_etm_wr_fc_cnt",
+			SE_SMMU1_SMMU1_TO_ETM_WR_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000097c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_etm_wr_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_wr_req_cnt",
+			SE_SMMU1_ETM_WR_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000980,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_etm_wr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_ftm_wr_fc_cnt",
+			SE_SMMU1_SMMU1_TO_FTM_WR_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000984,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_ftm_wr_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ftm_wr_req_cnt",
+			SE_SMMU1_FTM_WR_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000988,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ftm_wr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_state_wr_fc_cnt",
+			SE_SMMU1_SMMU1_TO_STATE_WR_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000098c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_state_wr_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"state_wr_req_cnt",
+			SE_SMMU1_STATE_WR_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000990,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_state_wr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_to_dma_rsp_cnt",
+			SE_SMMU1_SE_TO_DMA_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000994,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_se_to_dma_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_to_dma_fc_cnt",
+			SE_SMMU1_SE_TO_DMA_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000998,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_se_to_dma_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_to_smmu1_fc_cnt",
+			SE_SMMU1_OAM_TO_SMMU1_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000099c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_oam_to_smmu1_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_oam_rsp_cnt",
+			SE_SMMU1_SMMU1_TO_OAM_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_oam_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_oam_fc_cnt",
+			SE_SMMU1_SMMU1_TO_OAM_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_oam_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_to_smmu1_req_cnt",
+			SE_SMMU1_OAM_TO_SMMU1_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_oam_to_smmu1_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_etm_rsp_cnt",
+			SE_SMMU1_SMMU1_TO_ETM_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_etm_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_ftm_rsp_cnt",
+			SE_SMMU1_SMMU1_TO_FTM_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_ftm_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_etm_fc_cnt",
+			SE_SMMU1_SMMU1_TO_ETM_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_etm_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_to_smmu1_req_cnt",
+			SE_SMMU1_ETM_TO_SMMU1_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_etm_to_smmu1_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_ftm_fc_cnt",
+			SE_SMMU1_SMMU1_TO_FTM_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_ftm_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ftm_to_smmu1_req_cnt",
+			SE_SMMU1_FTM_TO_SMMU1_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_ftm_to_smmu1_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_stat_rsp_cnt",
+			SE_SMMU1_SMMU1_TO_STAT_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_stat_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_stat_fc_cnt",
+			SE_SMMU1_SMMU1_TO_STAT_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_stat_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_to_smmu1_req_cnt",
+			SE_SMMU1_STAT_TO_SMMU1_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_stat_to_smmu1_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_as_to_smmu1_fc_cnt",
+			SE_SMMU1_LPM_AS_TO_SMMU1_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_lpm_as_to_smmu1_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_to_smmu1_fc_cnt",
+			SE_SMMU1_LPM_TO_SMMU1_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_lpm_to_smmu1_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_lpm_as_rsp_cnt",
+			SE_SMMU1_SMMU1_TO_LPM_AS_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_lpm_as_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_lpm_rsp_cnt",
+			SE_SMMU1_SMMU1_TO_LPM_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_lpm_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_lpm_as_fc_cnt",
+			SE_SMMU1_SMMU1_TO_LPM_AS_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_lpm_as_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_lpm_fc_cnt",
+			SE_SMMU1_SMMU1_TO_LPM_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_smmu1_to_lpm_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_as_to_smmu1_req_cnt",
+			SE_SMMU1_LPM_AS_TO_SMMU1_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_lpm_as_to_smmu1_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"lpm_to_smmu1_req_cnt",
+			SE_SMMU1_LPM_TO_SMMU1_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_smmu1_lpm_to_smmu1_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_0_to_smmu1_fc_cnt",
+			SE_SMMU1_HASH3_0_TO_SMMU1_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000009f0,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_hash3_0_to_smmu1_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_hash3_0_rsp_cnt",
+			SE_SMMU1_SMMU1_TO_HASH3_0_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a00,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_smmu1_to_hash3_0_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_hash3_0_fc_cnt",
+			SE_SMMU1_SMMU1_TO_HASH3_0_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a10,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_smmu1_to_hash3_0_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash3_0_to_smmu1_cnt",
+			SE_SMMU1_HASH3_0_TO_SMMU1_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a20,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_hash3_0_to_smmu1_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_to_smmu1_dir3_0_rsp_fc_cnt",
+			SE_SMMU1_SE_TO_SMMU1_DIR3_0_RSP_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a30,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_se_to_smmu1_dir3_0_rsp_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_se_dir3_0_rsp_cnt",
+			SE_SMMU1_SMMU1_TO_SE_DIR3_0_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a40,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_smmu1_to_se_dir3_0_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu1_to_se_dir3_0_fc_cnt",
+			SE_SMMU1_SMMU1_TO_SE_DIR3_0_FC_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a50,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_smmu1_to_se_dir3_0_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_to_smmu1_dir3_0_cnt",
+			SE_SMMU1_SE_TO_SMMU1_DIR3_0_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a60,
+			(32 / 8),
+			0,
+			3 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_se_to_smmu1_dir3_0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cache7_0_to_rschd_rsp_cnt",
+			SE_SMMU1_CACHE7_0_TO_RSCHD_RSP_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000a70,
+			(32 / 8),
+			0,
+			7 + 1,
+			0,
+			4,
+			1,
+			g_se_smmu1_cache7_0_to_rschd_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_rw_addr",
+			SE_CMMU_DDR_RW_ADDRr,
+			SMMU1,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_ddr_rw_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_rw_mode",
+			SE_CMMU_DDR_RW_MODEr,
+			SMMU1,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_cmmu_ddr_rw_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cp_cmd",
+			SE_CMMU_CP_CMDr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_cp_cmd_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_rd_done",
+			SE_CMMU_CPU_IND_RD_DONEr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_cpu_ind_rd_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_rdat0",
+			SE_CMMU_CPU_IND_RDAT0r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_cpu_ind_rdat0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_rdat1",
+			SE_CMMU_CPU_IND_RDAT1r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_cpu_ind_rdat1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_rdat2",
+			SE_CMMU_CPU_IND_RDAT2r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_cpu_ind_rdat2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_rdat3",
+			SE_CMMU_CPU_IND_RDAT3r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000002c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_cpu_ind_rdat3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ddr_fifo_almful",
+			SE_CMMU_CPU_DDR_FIFO_ALMFULr,
+			SMMU1,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_cpu_ddr_fifo_almful_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_mode",
+			SE_CMMU_DEBUG_CNT_MODEr,
+			SMMU1,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_cmmu_debug_cnt_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cmmu_pful_cfg",
+			SE_CMMU_CMMU_PFUL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_cmmu_cmmu_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cmmu_stat_pful_cfg",
+			SE_CMMU_CMMU_STAT_PFUL_CFGr,
+			SMMU1,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000003c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_se_cmmu_cmmu_stat_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_overflow_mode",
+			SE_CMMU_STAT_OVERFLOW_MODEr,
+			SMMU1,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_stat_overflow_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cmmu_cp_fifo_pful",
+			SE_CMMU_CMMU_CP_FIFO_PFULr,
+			SMMU1,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_cmmu_cp_fifo_pful_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wr_dat0",
+			SE_CMMU_DDR_WR_DAT0r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000078,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_ddr_wr_dat0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_wr_dat1",
+			SE_CMMU_DDR_WR_DAT1r,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000007c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_ddr_wr_dat1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cmmu_int_unmask_flag",
+			SE_CMMU_CMMU_INT_UNMASK_FLAGr,
+			SMMU1,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_cmmu_int_unmask_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cmmu_int_en",
+			SE_CMMU_CMMU_INT_ENr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			13,
+			g_se_cmmu_cmmu_int_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cmmu_int_mask",
+			SE_CMMU_CMMU_INT_MASKr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			13,
+			g_se_cmmu_cmmu_int_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cmmu_int_status",
+			SE_CMMU_CMMU_INT_STATUSr,
+			SMMU1,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000008c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			13,
+			g_se_cmmu_cmmu_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_cmmu_req_cnt",
+			SE_CMMU_STAT_CMMU_REQ_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000400,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_stat_cmmu_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cmmu_fc0_cnt",
+			SE_CMMU_CMMU_FC0_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000404,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_cmmu_fc0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cmmu_fc1_cnt",
+			SE_CMMU_CMMU_FC1_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x00000408,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_cmmu_fc1_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cmmu_fc2_cnt",
+			SE_CMMU_CMMU_FC2_CNTr,
+			SMMU1,
+			DPP_REG_FLAG_INDIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_CMMU_BASE_ADDR + 0x0000040c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_se_cmmu_cmmu_fc2_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hash0_tbl0_cfg",
+			SMMU14K_SE_SMMU1_HASH0_TBL0_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000148,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash0_tbl0_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash0_tbl1_cfg",
+			SMMU14K_SE_SMMU1_HASH0_TBL1_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000014c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash0_tbl1_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash0_tbl2_cfg",
+			SMMU14K_SE_SMMU1_HASH0_TBL2_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000150,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash0_tbl2_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash0_tbl3_cfg",
+			SMMU14K_SE_SMMU1_HASH0_TBL3_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000154,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash0_tbl3_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash0_tbl4_cfg",
+			SMMU14K_SE_SMMU1_HASH0_TBL4_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000158,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash0_tbl4_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash0_tbl5_cfg",
+			SMMU14K_SE_SMMU1_HASH0_TBL5_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000015c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash0_tbl5_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash0_tbl6_cfg",
+			SMMU14K_SE_SMMU1_HASH0_TBL6_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000160,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash0_tbl6_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash0_tbl7_cfg",
+			SMMU14K_SE_SMMU1_HASH0_TBL7_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000164,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash0_tbl7_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash1_tbl0_cfg",
+			SMMU14K_SE_SMMU1_HASH1_TBL0_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000168,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash1_tbl0_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash1_tbl1_cfg",
+			SMMU14K_SE_SMMU1_HASH1_TBL1_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000016c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash1_tbl1_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash1_tbl2_cfg",
+			SMMU14K_SE_SMMU1_HASH1_TBL2_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000170,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash1_tbl2_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash1_tbl3_cfg",
+			SMMU14K_SE_SMMU1_HASH1_TBL3_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000174,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash1_tbl3_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash1_tbl4_cfg",
+			SMMU14K_SE_SMMU1_HASH1_TBL4_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000178,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash1_tbl4_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash1_tbl5_cfg",
+			SMMU14K_SE_SMMU1_HASH1_TBL5_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000017c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash1_tbl5_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash1_tbl6_cfg",
+			SMMU14K_SE_SMMU1_HASH1_TBL6_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000180,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash1_tbl6_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash1_tbl7_cfg",
+			SMMU14K_SE_SMMU1_HASH1_TBL7_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000184,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash1_tbl7_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash2_tbl0_cfg",
+			SMMU14K_SE_SMMU1_HASH2_TBL0_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000188,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash2_tbl0_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash2_tbl1_cfg",
+			SMMU14K_SE_SMMU1_HASH2_TBL1_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000018c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash2_tbl1_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash2_tbl2_cfg",
+			SMMU14K_SE_SMMU1_HASH2_TBL2_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000190,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash2_tbl2_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash2_tbl3_cfg",
+			SMMU14K_SE_SMMU1_HASH2_TBL3_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000194,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash2_tbl3_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash2_tbl4_cfg",
+			SMMU14K_SE_SMMU1_HASH2_TBL4_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x00000198,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash2_tbl4_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash2_tbl5_cfg",
+			SMMU14K_SE_SMMU1_HASH2_TBL5_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x0000019c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash2_tbl5_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash2_tbl6_cfg",
+			SMMU14K_SE_SMMU1_HASH2_TBL6_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash2_tbl6_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash2_tbl7_cfg",
+			SMMU14K_SE_SMMU1_HASH2_TBL7_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash2_tbl7_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash3_tbl0_cfg",
+			SMMU14K_SE_SMMU1_HASH3_TBL0_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash3_tbl0_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash3_tbl1_cfg",
+			SMMU14K_SE_SMMU1_HASH3_TBL1_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash3_tbl1_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash3_tbl2_cfg",
+			SMMU14K_SE_SMMU1_HASH3_TBL2_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash3_tbl2_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash3_tbl3_cfg",
+			SMMU14K_SE_SMMU1_HASH3_TBL3_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash3_tbl3_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash3_tbl4_cfg",
+			SMMU14K_SE_SMMU1_HASH3_TBL4_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash3_tbl4_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash3_tbl5_cfg",
+			SMMU14K_SE_SMMU1_HASH3_TBL5_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash3_tbl5_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash3_tbl6_cfg",
+			SMMU14K_SE_SMMU1_HASH3_TBL6_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash3_tbl6_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"hash3_tbl7_cfg",
+			SMMU14K_SE_SMMU1_HASH3_TBL7_CFGr,
+			SMMU14K,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_SE_SMMU1_BASE_ADDR + MODULE_SE_SMMU1_BASE_ADDR + 0x000001c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_smmu14k_se_smmu1_hash3_tbl7_cfg_reg,
+			dpp_se_write,
+			dpp_se_read,
+	},
+	{
+			"cpu_ind_eram_wdat1",
+			STAT_STAT_CFG_CPU_IND_ERAM_WDAT1r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_eram_wdat1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_eram_wdat2",
+			STAT_STAT_CFG_CPU_IND_ERAM_WDAT2r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_eram_wdat2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_eram_wdat3",
+			STAT_STAT_CFG_CPU_IND_ERAM_WDAT3r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_eram_wdat3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_eram_req_info",
+			STAT_STAT_CFG_CPU_IND_ERAM_REQ_INFOr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_stat_stat_cfg_cpu_ind_eram_req_info_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_eram_rd_done",
+			STAT_STAT_CFG_CPU_IND_ERAM_RD_DONEr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_eram_rd_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_eram_rdat0",
+			STAT_STAT_CFG_CPU_IND_ERAM_RDAT0r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_eram_rdat0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_eram_rdat1",
+			STAT_STAT_CFG_CPU_IND_ERAM_RDAT1r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_eram_rdat1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_eram_rdat2",
+			STAT_STAT_CFG_CPU_IND_ERAM_RDAT2r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_eram_rdat2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_eram_rdat3",
+			STAT_STAT_CFG_CPU_IND_ERAM_RDAT3r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_eram_rdat3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_alu_eram_cpu_rdy",
+			STAT_STAT_CFG_TM_ALU_ERAM_CPU_RDYr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_tm_alu_eram_cpu_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_stat_cfg",
+			STAT_STAT_CFG_OAM_STAT_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_stat_stat_cfg_oam_stat_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ftm_port_sel_cfg",
+			STAT_STAT_CFG_FTM_PORT_SEL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_stat_stat_cfg_ftm_port_sel_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_eram_base_addr",
+			STAT_STAT_CFG_OAM_ERAM_BASE_ADDRr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_oam_eram_base_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_lm_eram_base_addr",
+			STAT_STAT_CFG_OAM_LM_ERAM_BASE_ADDRr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000005c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_oam_lm_eram_base_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_ddr_base_addr",
+			STAT_STAT_CFG_OAM_DDR_BASE_ADDRr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_oam_ddr_base_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"plcr0_schd_pful_cfg",
+			STAT_STAT_CFG_PLCR0_SCHD_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000078,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_plcr0_schd_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_lm_ord_pful_cfg",
+			STAT_STAT_CFG_OAM_LM_ORD_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_oam_lm_ord_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_schd_pful_cfg",
+			STAT_STAT_CFG_DDR_SCHD_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_ddr_schd_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"eram_schd_pful_cfg",
+			STAT_STAT_CFG_ERAM_SCHD_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_eram_schd_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"eram_schd_pept_cfg",
+			STAT_STAT_CFG_ERAM_SCHD_PEPT_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000008c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_eram_schd_pept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"eram_schd_oam_pful_cfg",
+			STAT_STAT_CFG_ERAM_SCHD_OAM_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_eram_schd_oam_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"eram_schd_oam_pept_cfg",
+			STAT_STAT_CFG_ERAM_SCHD_OAM_PEPT_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_eram_schd_oam_pept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"eram_schd_oam_lm_pful_cfg",
+			STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000098,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_eram_schd_oam_lm_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"eram_schd_oam_lm_pept_cfg",
+			STAT_STAT_CFG_ERAM_SCHD_OAM_LM_PEPT_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000009c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_eram_schd_oam_lm_pept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_pful_cfg",
+			STAT_STAT_CFG_RSCHD_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_rschd_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_pept_cfg",
+			STAT_STAT_CFG_RSCHD_PEPT_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_rschd_pept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_plcr_pful_cfg",
+			STAT_STAT_CFG_RSCHD_PLCR_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_rschd_plcr_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_plcr_pept_cfg",
+			STAT_STAT_CFG_RSCHD_PLCR_PEPT_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_rschd_plcr_pept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_plcr_info_pful_cfg",
+			STAT_STAT_CFG_RSCHD_PLCR_INFO_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_rschd_plcr_info_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"alu_arb_cpu_pful_cfg",
+			STAT_STAT_CFG_ALU_ARB_CPU_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_alu_arb_cpu_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"alu_arb_user_pful_cfg",
+			STAT_STAT_CFG_ALU_ARB_USER_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_alu_arb_user_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"alu_arb_stat_pful_cfg",
+			STAT_STAT_CFG_ALU_ARB_STAT_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_alu_arb_stat_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cycmov_dat_pful_cfg",
+			STAT_STAT_CFG_CYCMOV_DAT_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_cycmov_dat_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ddr_opr_pful_cfg",
+			STAT_STAT_CFG_DDR_OPR_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_ddr_opr_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cycle_mov_pful_cfg",
+			STAT_STAT_CFG_CYCLE_MOV_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_cycle_mov_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cntovf_pful_cfg",
+			STAT_STAT_CFG_CNTOVF_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_cntovf_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"eram_schd_plcr_pful_cfg",
+			STAT_STAT_CFG_ERAM_SCHD_PLCR_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_eram_schd_plcr_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"eram_schd_plcr_pept_cfg",
+			STAT_STAT_CFG_ERAM_SCHD_PLCR_PEPT_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_eram_schd_plcr_pept_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"debug_cnt_mode",
+			STAT_STAT_CFG_DEBUG_CNT_MODEr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_debug_cnt_mode_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_mov_period_cfg",
+			STAT_STAT_CFG_TM_MOV_PERIOD_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_tm_mov_period_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"alu_ddr_cpu_req_pful_cfg",
+			STAT_STAT_CFG_ALU_DDR_CPU_REQ_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_alu_ddr_cpu_req_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cycmov_addr_pful_cfg",
+			STAT_STAT_CFG_CYCMOV_ADDR_PFUL_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000000f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_cycmov_addr_pful_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ord_ddr_plcr_fifo_empty",
+			STAT_STAT_CFG_ORD_DDR_PLCR_FIFO_EMPTYr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000100,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_stat_stat_cfg_ord_ddr_plcr_fifo_empty_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_stat_fifo_empty",
+			STAT_STAT_CFG_TM_STAT_FIFO_EMPTYr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000104,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_tm_stat_fifo_empty_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"eram_schd_fifo_empty_0_1",
+			STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_0_1r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000108,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_eram_schd_fifo_empty_0_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"eram_schd_fifo_empty_2_3",
+			STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_2_3r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000010c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_eram_schd_fifo_empty_2_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"eram_schd_fifo_empty_4_5",
+			STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_4_5r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000110,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_eram_schd_fifo_empty_4_5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"eram_schd_fifo_empty_6_7",
+			STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_6_7r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000114,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_stat_stat_cfg_eram_schd_fifo_empty_6_7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"eram_schd_fifo_empty_free_8",
+			STAT_STAT_CFG_ERAM_SCHD_FIFO_EMPTY_FREE_8r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000118,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			10,
+			g_stat_stat_cfg_eram_schd_fifo_empty_free_8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty_0_3",
+			STAT_STAT_CFG_RSCHD_FIFO_EMPTY_0_3r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000011c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_stat_stat_cfg_rschd_fifo_empty_0_3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty_4_7",
+			STAT_STAT_CFG_RSCHD_FIFO_EMPTY_4_7r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000120,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_stat_stat_cfg_rschd_fifo_empty_4_7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty_8_11",
+			STAT_STAT_CFG_RSCHD_FIFO_EMPTY_8_11r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000124,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_stat_stat_cfg_rschd_fifo_empty_8_11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty_12_15",
+			STAT_STAT_CFG_RSCHD_FIFO_EMPTY_12_15r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000128,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_stat_stat_cfg_rschd_fifo_empty_12_15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_fifo_empty_plcr_16_17",
+			STAT_STAT_CFG_RSCHD_FIFO_EMPTY_PLCR_16_17r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000012c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_stat_stat_cfg_rschd_fifo_empty_plcr_16_17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int_unmask_flag",
+			STAT_STAT_CFG_STAT_INT_UNMASK_FLAGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000140,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			6,
+			g_stat_stat_cfg_stat_int_unmask_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int0_en",
+			STAT_STAT_CFG_STAT_INT0_ENr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000144,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_stat_stat_cfg_stat_int0_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int0_mask",
+			STAT_STAT_CFG_STAT_INT0_MASKr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000148,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_stat_stat_cfg_stat_int0_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int0_status",
+			STAT_STAT_CFG_STAT_INT0_STATUSr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000014c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_stat_stat_cfg_stat_int0_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int1_en",
+			STAT_STAT_CFG_STAT_INT1_ENr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000150,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_stat_stat_cfg_stat_int1_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int1_mask",
+			STAT_STAT_CFG_STAT_INT1_MASKr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000154,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_stat_stat_cfg_stat_int1_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int1_status",
+			STAT_STAT_CFG_STAT_INT1_STATUSr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000158,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_stat_stat_cfg_stat_int1_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int2_en",
+			STAT_STAT_CFG_STAT_INT2_ENr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000015c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_stat_stat_cfg_stat_int2_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int2_mask",
+			STAT_STAT_CFG_STAT_INT2_MASKr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000160,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_stat_stat_cfg_stat_int2_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int2_status",
+			STAT_STAT_CFG_STAT_INT2_STATUSr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000164,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_stat_stat_cfg_stat_int2_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int3_en",
+			STAT_STAT_CFG_STAT_INT3_ENr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000168,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_stat_stat_cfg_stat_int3_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int3_mask",
+			STAT_STAT_CFG_STAT_INT3_MASKr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000016c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_stat_stat_cfg_stat_int3_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int3_status",
+			STAT_STAT_CFG_STAT_INT3_STATUSr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000170,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			32,
+			g_stat_stat_cfg_stat_int3_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int4_en",
+			STAT_STAT_CFG_STAT_INT4_ENr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000174,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			19,
+			g_stat_stat_cfg_stat_int4_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int4_mask",
+			STAT_STAT_CFG_STAT_INT4_MASKr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000178,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			19,
+			g_stat_stat_cfg_stat_int4_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int4_status",
+			STAT_STAT_CFG_STAT_INT4_STATUSr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000017c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			19,
+			g_stat_stat_cfg_stat_int4_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int5_en",
+			STAT_STAT_CFG_STAT_INT5_ENr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000180,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			19,
+			g_stat_stat_cfg_stat_int5_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int5_mask",
+			STAT_STAT_CFG_STAT_INT5_MASKr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000184,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			19,
+			g_stat_stat_cfg_stat_int5_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_int5_status",
+			STAT_STAT_CFG_STAT_INT5_STATUSr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000188,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			19,
+			g_stat_stat_cfg_stat_int5_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_ecc_bypass",
+			STAT_STAT_CFG_RSCHD_ECC_BYPASSr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000198,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			19,
+			g_stat_stat_cfg_rschd_ecc_bypass_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_ecc_single_err",
+			STAT_STAT_CFG_RSCHD_ECC_SINGLE_ERRr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000019c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			19,
+			g_stat_stat_cfg_rschd_ecc_single_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rschd_ecc_double_err",
+			STAT_STAT_CFG_RSCHD_ECC_DOUBLE_ERRr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000001a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			19,
+			g_stat_stat_cfg_rschd_ecc_double_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_wdat0",
+			STAT_STAT_CFG_CPU_IND_DDR_WDAT0r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000200,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_wdat0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_wdat1",
+			STAT_STAT_CFG_CPU_IND_DDR_WDAT1r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000204,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_wdat1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_wdat2",
+			STAT_STAT_CFG_CPU_IND_DDR_WDAT2r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000208,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_wdat2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_wdat3",
+			STAT_STAT_CFG_CPU_IND_DDR_WDAT3r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000020c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_wdat3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_wdat4",
+			STAT_STAT_CFG_CPU_IND_DDR_WDAT4r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000210,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_wdat4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_wdat5",
+			STAT_STAT_CFG_CPU_IND_DDR_WDAT5r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000214,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_wdat5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_wdat6",
+			STAT_STAT_CFG_CPU_IND_DDR_WDAT6r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000218,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_wdat6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_wdat7",
+			STAT_STAT_CFG_CPU_IND_DDR_WDAT7r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000021c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_wdat7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_wdat8",
+			STAT_STAT_CFG_CPU_IND_DDR_WDAT8r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000220,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_wdat8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_wdat9",
+			STAT_STAT_CFG_CPU_IND_DDR_WDAT9r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000224,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_wdat9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_wdat10",
+			STAT_STAT_CFG_CPU_IND_DDR_WDAT10r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000228,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_wdat10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_wdat11",
+			STAT_STAT_CFG_CPU_IND_DDR_WDAT11r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000022c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_wdat11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_wdat12",
+			STAT_STAT_CFG_CPU_IND_DDR_WDAT12r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000230,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_wdat12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_wdat13",
+			STAT_STAT_CFG_CPU_IND_DDR_WDAT13r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000234,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_wdat13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_wdat14",
+			STAT_STAT_CFG_CPU_IND_DDR_WDAT14r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000238,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_wdat14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_wdat15",
+			STAT_STAT_CFG_CPU_IND_DDR_WDAT15r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000023c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_wdat15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_req_info",
+			STAT_STAT_CFG_CPU_IND_DDR_REQ_INFOr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000240,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_stat_stat_cfg_cpu_ind_ddr_req_info_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rd_done",
+			STAT_STAT_CFG_CPU_IND_DDR_RD_DONEr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000244,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rd_done_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rdat0",
+			STAT_STAT_CFG_CPU_IND_DDR_RDAT0r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000248,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rdat0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rdat1",
+			STAT_STAT_CFG_CPU_IND_DDR_RDAT1r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000024c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rdat1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rdat2",
+			STAT_STAT_CFG_CPU_IND_DDR_RDAT2r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000250,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rdat2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rdat3",
+			STAT_STAT_CFG_CPU_IND_DDR_RDAT3r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000254,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rdat3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rdat4",
+			STAT_STAT_CFG_CPU_IND_DDR_RDAT4r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000258,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rdat4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rdat5",
+			STAT_STAT_CFG_CPU_IND_DDR_RDAT5r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000025c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rdat5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rdat6",
+			STAT_STAT_CFG_CPU_IND_DDR_RDAT6r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000260,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rdat6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rdat7",
+			STAT_STAT_CFG_CPU_IND_DDR_RDAT7r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000264,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rdat7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rdat8",
+			STAT_STAT_CFG_CPU_IND_DDR_RDAT8r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000268,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rdat8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rdat9",
+			STAT_STAT_CFG_CPU_IND_DDR_RDAT9r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000026c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rdat9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rdat10",
+			STAT_STAT_CFG_CPU_IND_DDR_RDAT10r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000270,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rdat10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rdat11",
+			STAT_STAT_CFG_CPU_IND_DDR_RDAT11r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000274,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rdat11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rdat12",
+			STAT_STAT_CFG_CPU_IND_DDR_RDAT12r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000278,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rdat12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rdat13",
+			STAT_STAT_CFG_CPU_IND_DDR_RDAT13r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000027c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rdat13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rdat14",
+			STAT_STAT_CFG_CPU_IND_DDR_RDAT14r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000280,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rdat14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_ddr_rdat15",
+			STAT_STAT_CFG_CPU_IND_DDR_RDAT15r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000284,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_ind_ddr_rdat15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_alu_ddr_cpu_rdy",
+			STAT_STAT_CFG_TM_ALU_DDR_CPU_RDYr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000288,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_tm_alu_ddr_cpu_rdy_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ept_flag",
+			STAT_STAT_CFG_EPT_FLAGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000003f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_ept_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_soft_rst",
+			STAT_STAT_CFG_PPU_SOFT_RSTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000003fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_ppu_soft_rst_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_smmu0_fc15_0_cnt",
+			STAT_STAT_CFG_STAT_SMMU0_FC15_0_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000400,
+			(32 / 8),
+			0,
+			15 + 1,
+			0,
+			4,
+			1,
+			g_stat_stat_cfg_stat_smmu0_fc15_0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_stat_fc15_0_cnt",
+			STAT_STAT_CFG_SMMU0_STAT_FC15_0_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000440,
+			(32 / 8),
+			0,
+			15 + 1,
+			0,
+			4,
+			1,
+			g_stat_stat_cfg_smmu0_stat_fc15_0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_stat_rsp15_0_cnt",
+			STAT_STAT_CFG_SMMU0_STAT_RSP15_0_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000480,
+			(32 / 8),
+			0,
+			15 + 1,
+			0,
+			4,
+			1,
+			g_stat_stat_cfg_smmu0_stat_rsp15_0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_smmu0_req15_0_cnt",
+			STAT_STAT_CFG_STAT_SMMU0_REQ15_0_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000004c0,
+			(32 / 8),
+			0,
+			15 + 1,
+			0,
+			4,
+			1,
+			g_stat_stat_cfg_stat_smmu0_req15_0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_stat_mec5_0_rsp_fc_cnt",
+			STAT_STAT_CFG_PPU_STAT_MEC5_0_RSP_FC_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000500,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_stat_stat_cfg_ppu_stat_mec5_0_rsp_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_ppu_mec5_0_key_fc_cnt",
+			STAT_STAT_CFG_STAT_PPU_MEC5_0_KEY_FC_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000518,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_stat_stat_cfg_stat_ppu_mec5_0_key_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_ppu_mec5_0_rsp_cnt",
+			STAT_STAT_CFG_STAT_PPU_MEC5_0_RSP_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000530,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_stat_stat_cfg_stat_ppu_mec5_0_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu_stat_mec5_0_key_cnt",
+			STAT_STAT_CFG_PPU_STAT_MEC5_0_KEY_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000548,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_stat_stat_cfg_ppu_stat_mec5_0_key_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ppu5_0_no_exist_opcd_ex_cnt",
+			STAT_STAT_CFG_PPU5_0_NO_EXIST_OPCD_EX_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000560,
+			(32 / 8),
+			0,
+			5 + 1,
+			0,
+			4,
+			1,
+			g_stat_stat_cfg_ppu5_0_no_exist_opcd_ex_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_etm_stat_wr_fc_cnt",
+			STAT_STAT_CFG_SE_ETM_STAT_WR_FC_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000578,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_se_etm_stat_wr_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_etm_stat_rd_fc_cnt",
+			STAT_STAT_CFG_SE_ETM_STAT_RD_FC_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000057c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_se_etm_stat_rd_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_etm_deq_fc_cnt",
+			STAT_STAT_CFG_STAT_ETM_DEQ_FC_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000580,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_stat_etm_deq_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_etm_enq_fc_cnt",
+			STAT_STAT_CFG_STAT_ETM_ENQ_FC_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000584,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_stat_etm_enq_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_oam_lm_fc_cnt",
+			STAT_STAT_CFG_STAT_OAM_LM_FC_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000588,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_stat_oam_lm_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_stat_lm_fc_cnt",
+			STAT_STAT_CFG_OAM_STAT_LM_FC_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000058c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_oam_stat_lm_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_oam_fc_cnt",
+			STAT_STAT_CFG_STAT_OAM_FC_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000590,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_stat_oam_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cmmu_stat_fc_cnt",
+			STAT_STAT_CFG_CMMU_STAT_FC_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000594,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cmmu_stat_fc_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_cmmu_req_cnt",
+			STAT_STAT_CFG_STAT_CMMU_REQ_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x00000598,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_stat_cmmu_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"smmu0_plcr_rsp0_cnt",
+			STAT_STAT_CFG_SMMU0_PLCR_RSP0_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x0000059c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_smmu0_plcr_rsp0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"plcr_smmu0_req0_cnt",
+			STAT_STAT_CFG_PLCR_SMMU0_REQ0_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_plcr_smmu0_req0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"stat_oam_lm_rsp_cnt",
+			STAT_STAT_CFG_STAT_OAM_LM_RSP_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_stat_oam_lm_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_stat_lm_req_cnt",
+			STAT_STAT_CFG_OAM_STAT_LM_REQ_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_oam_stat_lm_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"oam_stat_req_cnt",
+			STAT_STAT_CFG_OAM_STAT_REQ_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_oam_stat_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"se_etm_stat_rsp_cnt",
+			STAT_STAT_CFG_SE_ETM_STAT_RSP_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_se_etm_stat_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_stat_se_wr_req_cnt",
+			STAT_STAT_CFG_ETM_STAT_SE_WR_REQ_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_etm_stat_se_wr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_stat_se_rd_req_cnt",
+			STAT_STAT_CFG_ETM_STAT_SE_RD_REQ_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_etm_stat_se_rd_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_stat_smmu0_req_cnt0",
+			STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT0r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_etm_stat_smmu0_req_cnt0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etm_stat_smmu0_req_cnt1",
+			STAT_STAT_CFG_ETM_STAT_SMMU0_REQ_CNT1r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_etm_stat_smmu0_req_cnt1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_stat_eram_cpu_rsp_cnt",
+			STAT_STAT_CFG_TM_STAT_ERAM_CPU_RSP_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_tm_stat_eram_cpu_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_eram_req_cnt",
+			STAT_STAT_CFG_CPU_RD_ERAM_REQ_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_rd_eram_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_wr_eram_req_cnt",
+			STAT_STAT_CFG_CPU_WR_ERAM_REQ_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_wr_eram_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tm_stat_ddr_cpu_rsp_cnt",
+			STAT_STAT_CFG_TM_STAT_DDR_CPU_RSP_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_tm_stat_ddr_cpu_rsp_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_rd_ddr_req_cnt",
+			STAT_STAT_CFG_CPU_RD_DDR_REQ_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_rd_ddr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_wr_ddr_req_cnt",
+			STAT_STAT_CFG_CPU_WR_DDR_REQ_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_GLBL_BASE_ADDR + 0x000005d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_stat_cfg_cpu_wr_ddr_req_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat1",
+			STAT_ETCAM_CPU_IND_WDAT1r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat2",
+			STAT_ETCAM_CPU_IND_WDAT2r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat3",
+			STAT_ETCAM_CPU_IND_WDAT3r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat4",
+			STAT_ETCAM_CPU_IND_WDAT4r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat4_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat5",
+			STAT_ETCAM_CPU_IND_WDAT5r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat5_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat6",
+			STAT_ETCAM_CPU_IND_WDAT6r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat6_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat7",
+			STAT_ETCAM_CPU_IND_WDAT7r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat7_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat8",
+			STAT_ETCAM_CPU_IND_WDAT8r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat8_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat9",
+			STAT_ETCAM_CPU_IND_WDAT9r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat9_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat10",
+			STAT_ETCAM_CPU_IND_WDAT10r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000002c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat10_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat11",
+			STAT_ETCAM_CPU_IND_WDAT11r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat11_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat12",
+			STAT_ETCAM_CPU_IND_WDAT12r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat12_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat13",
+			STAT_ETCAM_CPU_IND_WDAT13r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat13_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat14",
+			STAT_ETCAM_CPU_IND_WDAT14r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000003c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat14_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat15",
+			STAT_ETCAM_CPU_IND_WDAT15r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat16",
+			STAT_ETCAM_CPU_IND_WDAT16r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat16_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat17",
+			STAT_ETCAM_CPU_IND_WDAT17r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat17_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat18",
+			STAT_ETCAM_CPU_IND_WDAT18r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat18_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_ind_wdat19",
+			STAT_ETCAM_CPU_IND_WDAT19r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_cpu_ind_wdat19_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"t_strwc_cfg",
+			STAT_ETCAM_T_STRWC_CFGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000074,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_t_strwc_cfg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_int_unmask_flag",
+			STAT_ETCAM_ETCAM_INT_UNMASK_FLAGr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_etcam_int_unmask_flag_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_int_en0",
+			STAT_ETCAM_ETCAM_INT_EN0r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			18,
+			g_stat_etcam_etcam_int_en0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_int_mask0",
+			STAT_ETCAM_ETCAM_INT_MASK0r,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000008c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			18,
+			g_stat_etcam_etcam_int_mask0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_int_status",
+			STAT_ETCAM_ETCAM_INT_STATUSr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			18,
+			g_stat_etcam_etcam_int_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"int_tb_ini_ok",
+			STAT_ETCAM_INT_TB_INI_OKr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x000003f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_int_tb_ini_ok_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_clk_en",
+			STAT_ETCAM_ETCAM_CLK_ENr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x000003fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_etcam_clk_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_etcam_req0_cnt",
+			STAT_ETCAM_AS_ETCAM_REQ0_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000400,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_as_etcam_req0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"as_etcam_req1_cnt",
+			STAT_ETCAM_AS_ETCAM_REQ1_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000404,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_as_etcam_req1_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_as_index0_cnt",
+			STAT_ETCAM_ETCAM_AS_INDEX0_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000408,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_etcam_as_index0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_as_index1_cnt",
+			STAT_ETCAM_ETCAM_AS_INDEX1_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000040c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_etcam_as_index1_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_not_hit0_cnt",
+			STAT_ETCAM_ETCAM_NOT_HIT0_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000410,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_etcam_not_hit0_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_not_hit1_cnt",
+			STAT_ETCAM_ETCAM_NOT_HIT1_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000414,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_etcam_not_hit1_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"table_id_not_match_cnt",
+			STAT_ETCAM_TABLE_ID_NOT_MATCH_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000418,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_table_id_not_match_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"table_id_clash01_cnt",
+			STAT_ETCAM_TABLE_ID_CLASH01_CNTr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000041c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_table_id_clash01_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_cpu_fl",
+			STAT_ETCAM_ETCAM_CPU_FLr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x0000044c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_etcam_cpu_fl_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"etcam_arb_empty",
+			STAT_ETCAM_ETCAM_ARB_EMPTYr,
+			STAT,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_STAT_BASE_ADDR + MODULE_STAT_ETCAM_BASE_ADDR + 0x00000450,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_stat_etcam_etcam_arb_empty_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_finish_int_event0",
+			DTB_DTB_CFG_CFG_FINISH_INT_EVENT0r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_finish_int_event0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_finish_int_event1",
+			DTB_DTB_CFG_CFG_FINISH_INT_EVENT1r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_finish_int_event1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_finish_int_event2",
+			DTB_DTB_CFG_CFG_FINISH_INT_EVENT2r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_finish_int_event2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_finish_int_event3",
+			DTB_DTB_CFG_CFG_FINISH_INT_EVENT3r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_finish_int_event3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_finish_int_maks0",
+			DTB_DTB_CFG_CFG_FINISH_INT_MAKS0r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_finish_int_maks0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_finish_int_maks1",
+			DTB_DTB_CFG_CFG_FINISH_INT_MAKS1r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_finish_int_maks1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_finish_int_maks2",
+			DTB_DTB_CFG_CFG_FINISH_INT_MAKS2r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_finish_int_maks2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_finish_int_maks3",
+			DTB_DTB_CFG_CFG_FINISH_INT_MAKS3r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_finish_int_maks3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_finish_int_test0",
+			DTB_DTB_CFG_CFG_FINISH_INT_TEST0r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_finish_int_test0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_finish_int_test1",
+			DTB_DTB_CFG_CFG_FINISH_INT_TEST1r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_finish_int_test1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_finish_int_test2",
+			DTB_DTB_CFG_CFG_FINISH_INT_TEST2r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_finish_int_test2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_finish_int_test3",
+			DTB_DTB_CFG_CFG_FINISH_INT_TEST3r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x002c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_finish_int_test3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_dtb_int_to_riscv_sel",
+			DTB_DTB_CFG_CFG_DTB_INT_TO_RISCV_SELr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_dtb_int_to_riscv_sel_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_dtb_ep_int_msix_enable",
+			DTB_DTB_CFG_CFG_DTB_EP_INT_MSIX_ENABLEr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_dtb_ep_int_msix_enable_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_dtb_ep_doorbell_addr_h_0_15",
+			DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_H_0_15r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0100,
+			(32 / 8),
+			0,
+			15 + 1,
+			0,
+			4,
+			1,
+			g_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_h_0_15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_dtb_ep_doorbell_addr_l_0_15",
+			DTB_DTB_CFG_CFG_DTB_EP_DOORBELL_ADDR_L_0_15r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0140,
+			(32 / 8),
+			0,
+			15 + 1,
+			0,
+			4,
+			1,
+			g_dtb_dtb_cfg_cfg_dtb_ep_doorbell_addr_l_0_15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_dtb_debug_mode_en",
+			DTB_DTB_CFG_CFG_DTB_DEBUG_MODE_ENr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0180,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_dtb_debug_mode_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_rd_table_addr_high",
+			DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_HIGHr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0184,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_rd_table_addr_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_rd_table_addr_low",
+			DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ADDR_LOWr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0188,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_rd_table_addr_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_rd_table_len",
+			DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_LENr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x018c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_rd_table_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_rd_table_user",
+			DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_USERr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0190,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_dtb_dtb_cfg_info_axi_last_rd_table_user_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_rd_table_onload_cnt",
+			DTB_DTB_CFG_INFO_AXI_LAST_RD_TABLE_ONLOAD_CNTr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0194,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_rd_table_onload_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_axi_rd_table_resp_err",
+			DTB_DTB_CFG_CNT_AXI_RD_TABLE_RESP_ERRr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0198,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_axi_rd_table_resp_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_rd_pd_addr_high",
+			DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_HIGHr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_rd_pd_addr_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_rd_pd_addr_low",
+			DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ADDR_LOWr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_rd_pd_addr_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_rd_pd_len",
+			DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_LENr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_rd_pd_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_rd_pd_user",
+			DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_USERr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_dtb_dtb_cfg_info_axi_last_rd_pd_user_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_rd_pd_onload_cnt",
+			DTB_DTB_CFG_INFO_AXI_LAST_RD_PD_ONLOAD_CNTr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_rd_pd_onload_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_axi_rd_pd_resp_err",
+			DTB_DTB_CFG_CNT_AXI_RD_PD_RESP_ERRr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_axi_rd_pd_resp_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_wr_ctrl_addr_high",
+			DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_HIGHr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_wr_ctrl_addr_low",
+			DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ADDR_LOWr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_wr_ctrl_addr_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_wr_ctrl_len",
+			DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_LENr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_wr_ctrl_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_wr_ctrl_user",
+			DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_USERr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_dtb_dtb_cfg_info_axi_last_wr_ctrl_user_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_wr_ctrl_onload_cnt",
+			DTB_DTB_CFG_INFO_AXI_LAST_WR_CTRL_ONLOAD_CNTr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_wr_ctrl_onload_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_axi_wr_ctrl_resp_err",
+			DTB_DTB_CFG_CNT_AXI_WR_CTRL_RESP_ERRr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_axi_wr_ctrl_resp_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_wr_ddr_addr_high",
+			DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_HIGHr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_wr_ddr_addr_low",
+			DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ADDR_LOWr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_wr_ddr_addr_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_wr_ddr_len",
+			DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_LENr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_wr_ddr_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_wr_ddr_user",
+			DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_USERr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_dtb_dtb_cfg_info_axi_last_wr_ddr_user_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_wr_ddr_onload_cnt",
+			DTB_DTB_CFG_INFO_AXI_LAST_WR_DDR_ONLOAD_CNTr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_wr_ddr_onload_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_axi_wr_ddr_resp_err",
+			DTB_DTB_CFG_CNT_AXI_WR_DDR_RESP_ERRr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_axi_wr_ddr_resp_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_wr_fin_addr_high",
+			DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_HIGHr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_wr_fin_addr_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_wr_fin_addr_low",
+			DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ADDR_LOWr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_wr_fin_addr_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_wr_fin_len",
+			DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_LENr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_wr_fin_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_wr_fin_user",
+			DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_USERr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_dtb_dtb_cfg_info_axi_last_wr_fin_user_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axi_last_wr_fin_onload_cnt",
+			DTB_DTB_CFG_INFO_AXI_LAST_WR_FIN_ONLOAD_CNTr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_axi_last_wr_fin_onload_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_axi_wr_fin_resp_err",
+			DTB_DTB_CFG_CNT_AXI_WR_FIN_RESP_ERRr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x01fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_axi_wr_fin_resp_err_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_wr_smmu0_table_high",
+			DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_HIGHr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0200,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_wr_smmu0_table_low",
+			DTB_DTB_CFG_CNT_DTB_WR_SMMU0_TABLE_LOWr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0204,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_wr_smmu0_table_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_wr_smmu1_table_high",
+			DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_HIGHr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0208,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_wr_smmu1_table_low",
+			DTB_DTB_CFG_CNT_DTB_WR_SMMU1_TABLE_LOWr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x020c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_wr_smmu1_table_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_wr_zcam_table_high",
+			DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_HIGHr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0210,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_wr_zcam_table_low",
+			DTB_DTB_CFG_CNT_DTB_WR_ZCAM_TABLE_LOWr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0214,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_wr_zcam_table_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_wr_etcam_table_high",
+			DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_HIGHr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0218,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_wr_etcam_table_low",
+			DTB_DTB_CFG_CNT_DTB_WR_ETCAM_TABLE_LOWr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x021c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_wr_etcam_table_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_wr_hash_table_high",
+			DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_HIGHr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0220,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_wr_hash_table_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_wr_hash_table_low",
+			DTB_DTB_CFG_CNT_DTB_WR_HASH_TABLE_LOWr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0224,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_wr_hash_table_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_rd_smmu0_table_high",
+			DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_HIGHr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0228,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_rd_smmu0_table_low",
+			DTB_DTB_CFG_CNT_DTB_RD_SMMU0_TABLE_LOWr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x022c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_rd_smmu0_table_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_rd_smmu1_table_high",
+			DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_HIGHr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0230,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_rd_smmu1_table_low",
+			DTB_DTB_CFG_CNT_DTB_RD_SMMU1_TABLE_LOWr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0234,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_rd_smmu1_table_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_rd_zcam_table_high",
+			DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_HIGHr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0238,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_rd_zcam_table_low",
+			DTB_DTB_CFG_CNT_DTB_RD_ZCAM_TABLE_LOWr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x023c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_rd_zcam_table_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_rd_etcam_table_high",
+			DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_HIGHr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0240,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cnt_dtb_rd_etcam_table_low",
+			DTB_DTB_CFG_CNT_DTB_RD_ETCAM_TABLE_LOWr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0244,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cnt_dtb_rd_etcam_table_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_wr_ctrl_state",
+			DTB_DTB_CFG_INFO_WR_CTRL_STATEr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0248,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_wr_ctrl_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_rd_table_state",
+			DTB_DTB_CFG_INFO_RD_TABLE_STATEr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x024c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_rd_table_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_rd_pd_state",
+			DTB_DTB_CFG_INFO_RD_PD_STATEr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0250,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_rd_pd_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_dump_cmd_state",
+			DTB_DTB_CFG_INFO_DUMP_CMD_STATEr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0254,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_dump_cmd_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_wr_ddr_state",
+			DTB_DTB_CFG_INFO_WR_DDR_STATEr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x0258,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_info_wr_ddr_state_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_dtb_debug_info_clr",
+			DTB_DTB_CFG_CFG_DTB_DEBUG_INFO_CLRr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_CFG_BASE_ADDR + 0x025c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_dtb_cfg_cfg_dtb_debug_info_clr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddos_stat_dump_thrd_0_15",
+			DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_0_15r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			15 + 1,
+			0,
+			4,
+			1,
+			g_dtb_ddos_cfg_ddos_stat_dump_thrd_0_15_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddos_stat_dump_thrd_comp_en",
+			DTB_DDOS_CFG_DDOS_STAT_DUMP_THRD_COMP_ENr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_ddos_cfg_ddos_stat_dump_thrd_comp_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddos_dump_stat_num",
+			DTB_DDOS_CFG_DDOS_DUMP_STAT_NUMr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_ddos_cfg_ddos_dump_stat_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddos_even_hash_table_baddr",
+			DTB_DDOS_CFG_DDOS_EVEN_HASH_TABLE_BADDRr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_ddos_cfg_ddos_even_hash_table_baddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddos_odd_hash_table_baddr",
+			DTB_DDOS_CFG_DDOS_ODD_HASH_TABLE_BADDRr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_ddos_cfg_ddos_odd_hash_table_baddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddos_stat_index_offset",
+			DTB_DDOS_CFG_DDOS_STAT_INDEX_OFFSETr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_ddos_cfg_ddos_stat_index_offset_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddos_ns_flag_cnt",
+			DTB_DDOS_CFG_DDOS_NS_FLAG_CNTr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_ddos_cfg_ddos_ns_flag_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddos_even_stat_table_baddr",
+			DTB_DDOS_CFG_DDOS_EVEN_STAT_TABLE_BADDRr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_ddos_cfg_ddos_even_stat_table_baddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddos_odd_stat_table_baddr",
+			DTB_DDOS_CFG_DDOS_ODD_STAT_TABLE_BADDRr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x005c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_ddos_cfg_ddos_odd_stat_table_baddr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddos_even_stat_dump_daddr_h",
+			DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_Hr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_ddos_cfg_ddos_even_stat_dump_daddr_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddos_even_stat_dump_daddr_l",
+			DTB_DDOS_CFG_DDOS_EVEN_STAT_DUMP_DADDR_Lr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_ddos_cfg_ddos_even_stat_dump_daddr_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddos_odd_stat_dump_daddr_h",
+			DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_Hr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddos_odd_stat_dump_daddr_l",
+			DTB_DDOS_CFG_DDOS_ODD_STAT_DUMP_DADDR_Lr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x006c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_ddos_cfg_ddos_odd_stat_dump_daddr_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddos_work_mode_enable",
+			DTB_DDOS_CFG_DDOS_WORK_MODE_ENABLEr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0070,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_ddos_cfg_ddos_work_mode_enable_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddos_stat_table_len",
+			DTB_DDOS_CFG_DDOS_STAT_TABLE_LENr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0074,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_ddos_cfg_ddos_stat_table_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_ddos_hash_table_len",
+			DTB_DDOS_CFG_DDOS_HASH_TABLE_LENr,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_DDOS_BASE_ADDR + 0x0078,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_dtb_ddos_cfg_ddos_hash_table_len_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"traf_ctrl_ram0_0_255",
+			DTB_DTB_RAM_TRAF_CTRL_RAM0_0_255r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x00000,
+			(32 / 8),
+			0,
+			255 + 1,
+			0,
+			4,
+			1,
+			g_dtb_dtb_ram_traf_ctrl_ram0_0_255_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"traf_ctrl_ram1_0_255",
+			DTB_DTB_RAM_TRAF_CTRL_RAM1_0_255r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x00400,
+			(32 / 8),
+			0,
+			255 + 1,
+			0,
+			4,
+			1,
+			g_dtb_dtb_ram_traf_ctrl_ram1_0_255_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"traf_ctrl_ram2_0_255",
+			DTB_DTB_RAM_TRAF_CTRL_RAM2_0_255r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x00800,
+			(32 / 8),
+			0,
+			255 + 1,
+			0,
+			4,
+			1,
+			g_dtb_dtb_ram_traf_ctrl_ram2_0_255_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"traf_ctrl_ram3_0_255",
+			DTB_DTB_RAM_TRAF_CTRL_RAM3_0_255r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x00c00,
+			(32 / 8),
+			0,
+			255 + 1,
+			0,
+			4,
+			1,
+			g_dtb_dtb_ram_traf_ctrl_ram3_0_255_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"traf_ctrl_ram4_0_255",
+			DTB_DTB_RAM_TRAF_CTRL_RAM4_0_255r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x01000,
+			(32 / 8),
+			0,
+			255 + 1,
+			0,
+			4,
+			1,
+			g_dtb_dtb_ram_traf_ctrl_ram4_0_255_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"traf_ctrl_ram5_0_63",
+			DTB_DTB_RAM_TRAF_CTRL_RAM5_0_63r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x01400,
+			(32 / 8),
+			0,
+			63 + 1,
+			0,
+			4,
+			1,
+			g_dtb_dtb_ram_traf_ctrl_ram5_0_63_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dump_pd_ram_0_2047",
+			DTB_DTB_RAM_DUMP_PD_RAM_0_2047r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x02000,
+			(32 / 8),
+			0,
+			2047 + 1,
+			0,
+			4,
+			1,
+			g_dtb_dtb_ram_dump_pd_ram_0_2047_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rd_ctrl_ram_0_4095",
+			DTB_DTB_RAM_RD_CTRL_RAM_0_4095r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x04000,
+			(32 / 8),
+			0,
+			4095 + 1,
+			0,
+			4,
+			1,
+			g_dtb_dtb_ram_rd_ctrl_ram_0_4095_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"rd_table_ram_0_8191",
+			DTB_DTB_RAM_RD_TABLE_RAM_0_8191r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x08000,
+			(32 / 8),
+			0,
+			8191 + 1,
+			0,
+			4,
+			1,
+			g_dtb_dtb_ram_rd_table_ram_0_8191_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"dtb_cmd_man_ram_0_16383",
+			DTB_DTB_RAM_DTB_CMD_MAN_RAM_0_16383r,
+			DTB,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_DTB_BASE_ADDR + MODULE_DTB_RAM_BASE_ADDR + 0x10000,
+			(32 / 8),
+			0,
+			16383 + 1,
+			0,
+			4,
+			1,
+			g_dtb_dtb_ram_dtb_cmd_man_ram_0_16383_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpg_ms_st",
+			TRPG_TRPG_RX_PORT_CPU_TRPG_MS_STr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0000,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpg_ms_st_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpg_ms_ind",
+			TRPG_TRPG_RX_PORT_CPU_TRPG_MS_INDr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0008,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpg_ms_ind_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpg_ms_slave_ind",
+			TRPG_TRPG_RX_PORT_CPU_TRPG_MS_SLAVE_INDr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x000c,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpg_ms_slave_ind_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_up_water_level",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_UP_WATER_LEVELr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0020,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_up_water_level_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpgrx_low_water_level",
+			TRPG_TRPG_RX_PORT_CPU_TRPGRX_LOW_WATER_LEVELr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_RX_BASE_ADDR + 0x0024,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_rx_port_cpu_trpgrx_low_water_level_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpg_ms_st",
+			TRPG_TRPG_TX_PORT_CPU_TRPG_MS_STr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0000,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpg_ms_st_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpg_ms_ind",
+			TRPG_TRPG_TX_PORT_CPU_TRPG_MS_INDr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x0008,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpg_ms_ind_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_trpg_ms_slave_ind",
+			TRPG_TRPG_TX_PORT_CPU_TRPG_MS_SLAVE_INDr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_BASE_ADDR + 0x000c,
+			(32 / 8),
+			DPP_TRPG_PORT_NUM,
+			0,
+			DPP_TRPG_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_trpg_trpg_tx_port_cpu_trpg_ms_slave_ind_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_todtime_update_int_event",
+			TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_EVENTr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_trpg_trpg_tx_glb_cpu_todtime_update_int_event_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_todtime_update_int_test",
+			TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_TESTr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_trpg_trpg_tx_glb_cpu_todtime_update_int_test_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cpu_todtime_update_int_addr",
+			TRPG_TRPG_TX_GLB_CPU_TODTIME_UPDATE_INT_ADDRr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_GLB_BASE_ADDR + 0x0014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_trpg_trpg_tx_glb_cpu_todtime_update_int_addr_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trpg_tx_todtime_ram",
+			TRPG_TRPG_TX_TODTIME_RAM_TRPG_TX_TODTIME_RAMr,
+			TRPG,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_UNI_ARRAY,
+			SYS_TRPG_BASE_ADDR + MODULE_TRPG_TX_TODTIME_RAM_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			4095 + 1,
+			0,
+			4,
+			1,
+			g_trpg_trpg_tx_todtime_ram_trpg_tx_todtime_ram_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_test_reg",
+			TSN_TSN_PORT_CFG_TSN_TEST_REGr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x000,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_tsn_tsn_port_cfg_tsn_test_reg_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_port_qbv_enable",
+			TSN_TSN_PORT_CFG_TSN_PORT_QBV_ENABLEr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0004,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_tsn_tsn_port_cfg_tsn_port_qbv_enable_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_phy_port_sel",
+			TSN_TSN_PORT_CFG_TSN_PHY_PORT_SELr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0008,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_tsn_tsn_port_cfg_tsn_phy_port_sel_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_port_time_sel",
+			TSN_TSN_PORT_CFG_TSN_PORT_TIME_SELr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x000c,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_tsn_tsn_port_cfg_tsn_port_time_sel_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_clk_freq",
+			TSN_TSN_PORT_CFG_TSN_CLK_FREQr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0014,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			2,
+			g_tsn_tsn_port_cfg_tsn_clk_freq_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_read_ram_n",
+			TSN_TSN_PORT_CFG_TSN_READ_RAM_Nr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0018,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			3,
+			g_tsn_tsn_port_cfg_tsn_read_ram_n_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_exe_time",
+			TSN_TSN_PORT_CFG_TSN_EXE_TIMEr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x001c,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_tsn_tsn_port_cfg_tsn_exe_time_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_port_itr_shift",
+			TSN_TSN_PORT_CFG_TSN_PORT_ITR_SHIFTr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0020,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_tsn_tsn_port_cfg_tsn_port_itr_shift_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_port_base_time_h",
+			TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_Hr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0024,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_tsn_tsn_port_cfg_tsn_port_base_time_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_port_base_time_l",
+			TSN_TSN_PORT_CFG_TSN_PORT_BASE_TIME_Lr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0028,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_tsn_tsn_port_cfg_tsn_port_base_time_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_port_cycle_time_h",
+			TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_Hr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0030,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_tsn_tsn_port_cfg_tsn_port_cycle_time_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_port_cycle_time_l",
+			TSN_TSN_PORT_CFG_TSN_PORT_CYCLE_TIME_Lr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0034,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_tsn_tsn_port_cfg_tsn_port_cycle_time_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_port_guard_band_time",
+			TSN_TSN_PORT_CFG_TSN_PORT_GUARD_BAND_TIMEr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0040,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			7 + 1,
+			DPP_TSN_PORT_SPACE_SIZE,
+			4,
+			1,
+			g_tsn_tsn_port_cfg_tsn_port_guard_band_time_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_port_default_gate_en",
+			TSN_TSN_PORT_CFG_TSN_PORT_DEFAULT_GATE_ENr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0060,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_tsn_tsn_port_cfg_tsn_port_default_gate_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_port_change_gate_en",
+			TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_GATE_ENr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0064,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_tsn_tsn_port_cfg_tsn_port_change_gate_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_port_init_finish",
+			TSN_TSN_PORT_CFG_TSN_PORT_INIT_FINISHr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0068,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_tsn_tsn_port_cfg_tsn_port_init_finish_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_port_change_en",
+			TSN_TSN_PORT_CFG_TSN_PORT_CHANGE_ENr,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x006c,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_tsn_tsn_port_cfg_tsn_port_change_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_port_gcl_num0",
+			TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM0r,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0070,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_tsn_tsn_port_cfg_tsn_port_gcl_num0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_port_gcl_num1",
+			TSN_TSN_PORT_CFG_TSN_PORT_GCL_NUM1r,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x0074,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			0,
+			DPP_TSN_PORT_SPACE_SIZE,
+			0,
+			1,
+			g_tsn_tsn_port_cfg_tsn_port_gcl_num1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_port_gcl_value0",
+			TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE0r,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x1000,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			255 + 1,
+			DPP_TSN_PORT_SPACE_SIZE,
+			4,
+			2,
+			g_tsn_tsn_port_cfg_tsn_port_gcl_value0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_tsn_port_gcl_value1",
+			TSN_TSN_PORT_CFG_TSN_PORT_GCL_VALUE1r,
+			TSN,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_BIN_ARRAY,
+			SYS_TSN_BASE_ADDR + MODULE_TSN_PORT0_BASE_ADDR + 0x2000,
+			(32 / 8),
+			DPP_TSN_PORT_NUM,
+			255 + 1,
+			DPP_TSN_PORT_SPACE_SIZE,
+			4,
+			2,
+			g_tsn_tsn_port_cfg_tsn_port_gcl_value1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_epid_v_func_num",
+			AXI_AXI_CONV_CFG_EPID_V_FUNC_NUMr,
+			AXI,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_AXI_CONV_BASE_ADDR + 0x0010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_axi_axi_conv_cfg_epid_v_func_num_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axim_rw_hsk_cnt",
+			AXI_AXI_CONV_INFO_AXIM_RW_HSK_CNTr,
+			AXI,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_AXI_CONV_BASE_ADDR + 0x0020,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_axi_axi_conv_info_axim_rw_hsk_cnt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axim_last_wr_id",
+			AXI_AXI_CONV_INFO_AXIM_LAST_WR_IDr,
+			AXI,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_AXI_CONV_BASE_ADDR + 0x0024,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_axi_axi_conv_info_axim_last_wr_id_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axim_last_wr_addr_h",
+			AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_Hr,
+			AXI,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_AXI_CONV_BASE_ADDR + 0x0030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_axi_axi_conv_info_axim_last_wr_addr_h_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"info_axim_last_wr_addr_l",
+			AXI_AXI_CONV_INFO_AXIM_LAST_WR_ADDR_Lr,
+			AXI,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_AXI_CONV_BASE_ADDR + 0x0034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_axi_axi_conv_info_axim_last_wr_addr_l_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cfg_debug_info_clr_en",
+			AXI_AXI_CONV_CFG_DEBUG_INFO_CLR_ENr,
+			AXI,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_AXI_CONV_BASE_ADDR + 0x0038,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_axi_axi_conv_cfg_debug_info_clr_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_interrupt",
+			PTPTM_PTP_TOP_PP1S_INTERRUPTr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_ptptm_ptp_top_pp1s_interrupt_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_external_select",
+			PTPTM_PTP_TOP_PP1S_EXTERNAL_SELECTr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0004,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_pp1s_external_select_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_out_select",
+			PTPTM_PTP_TOP_PP1S_OUT_SELECTr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_pp1s_out_select_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"test_pp1s_select",
+			PTPTM_PTP_TOP_TEST_PP1S_SELECTr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_test_pp1s_select_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"local_pp1s_en",
+			PTPTM_PTP_TOP_LOCAL_PP1S_ENr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_local_pp1s_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"local_pp1s_adjust",
+			PTPTM_PTP_TOP_LOCAL_PP1S_ADJUSTr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_ptptm_ptp_top_local_pp1s_adjust_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"local_pp1s_adjust_value",
+			PTPTM_PTP_TOP_LOCAL_PP1S_ADJUST_VALUEr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_local_pp1s_adjust_value_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_to_np_select",
+			PTPTM_PTP_TOP_PP1S_TO_NP_SELECTr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_pp1s_to_np_select_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pd_u1_sel",
+			PTPTM_PTP_TOP_PD_U1_SELr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_ptptm_ptp_top_pd_u1_sel_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pd_u1_pd0_shift",
+			PTPTM_PTP_TOP_PD_U1_PD0_SHIFTr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_pd_u1_pd0_shift_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pd_u1_pd1_shift",
+			PTPTM_PTP_TOP_PD_U1_PD1_SHIFTr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_pd_u1_pd1_shift_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pd_u1_result",
+			PTPTM_PTP_TOP_PD_U1_RESULTr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_ptptm_ptp_top_pd_u1_result_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pd_u2_sel",
+			PTPTM_PTP_TOP_PD_U2_SELr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_ptptm_ptp_top_pd_u2_sel_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pd_u2_pd0_shift",
+			PTPTM_PTP_TOP_PD_U2_PD0_SHIFTr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_pd_u2_pd0_shift_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pd_u2_pd1_shift",
+			PTPTM_PTP_TOP_PD_U2_PD1_SHIFTr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_pd_u2_pd1_shift_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pd_u2_result",
+			PTPTM_PTP_TOP_PD_U2_RESULTr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x005c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_ptptm_ptp_top_pd_u2_result_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn_group_nanosecond_delay0",
+			PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY0r,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_tsn_group_nanosecond_delay0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn_group_fracnanosecond_delay0",
+			PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY0r,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_tsn_group_fracnanosecond_delay0_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn_group_nanosecond_delay1",
+			PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY1r,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_tsn_group_nanosecond_delay1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn_group_fracnanosecond_delay1",
+			PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY1r,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x008c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_tsn_group_fracnanosecond_delay1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn_group_nanosecond_delay2",
+			PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY2r,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_tsn_group_nanosecond_delay2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn_group_fracnanosecond_delay2",
+			PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY2r,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_tsn_group_fracnanosecond_delay2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn_group_nanosecond_delay3",
+			PTPTM_PTP_TOP_TSN_GROUP_NANOSECOND_DELAY3r,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x0098,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_tsn_group_nanosecond_delay3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn_group_fracnanosecond_delay3",
+			PTPTM_PTP_TOP_TSN_GROUP_FRACNANOSECOND_DELAY3r,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x009c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_tsn_group_fracnanosecond_delay3_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn_ptp1588_rdma_nanosecond_delay",
+			PTPTM_PTP_TOP_TSN_PTP1588_RDMA_NANOSECOND_DELAYr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x00a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_tsn_ptp1588_rdma_nanosecond_delay_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ptp1588_rdma_fracnanosecond_delay",
+			PTPTM_PTP_TOP_PTP1588_RDMA_FRACNANOSECOND_DELAYr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x00a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_ptp1588_rdma_fracnanosecond_delay_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ptp1588_np_nanosecond_delay",
+			PTPTM_PTP_TOP_PTP1588_NP_NANOSECOND_DELAYr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x00a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_ptp1588_np_nanosecond_delay_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ptp1588_np_fracnanosecond_delay",
+			PTPTM_PTP_TOP_PTP1588_NP_FRACNANOSECOND_DELAYr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x00ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_ptp1588_np_fracnanosecond_delay_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"time_sync_period",
+			PTPTM_PTP_TOP_TIME_SYNC_PERIODr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP0_BASE_ADDR + 0x00b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptp_top_time_sync_period_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"module_id",
+			PTPTM_PTPTM_MODULE_IDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0000,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_module_id_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"module_version",
+			PTPTM_PTPTM_MODULE_VERSIONr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0008,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_ptptm_ptptm_module_version_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"module_date",
+			PTPTM_PTPTM_MODULE_DATEr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x000c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_ptptm_ptptm_module_date_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"interrupt_status",
+			PTPTM_PTPTM_INTERRUPT_STATUSr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0010,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_ptptm_ptptm_interrupt_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"interrupt_event",
+			PTPTM_PTPTM_INTERRUPT_EVENTr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0014,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_ptptm_ptptm_interrupt_event_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"interrupt_mask",
+			PTPTM_PTPTM_INTERRUPT_MASKr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0018,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_ptptm_ptptm_interrupt_mask_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"interrupt_test",
+			PTPTM_PTPTM_INTERRUPT_TESTr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x001c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_ptptm_ptptm_interrupt_test_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hw_clock_cycle_integer",
+			PTPTM_PTPTM_HW_CLOCK_CYCLE_INTEGERr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0028,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_hw_clock_cycle_integer_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"hw_clock_cycle_fraction",
+			PTPTM_PTPTM_HW_CLOCK_CYCLE_FRACTIONr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x002c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_hw_clock_cycle_fraction_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ptp_clock_cycle_integer",
+			PTPTM_PTPTM_PTP_CLOCK_CYCLE_INTEGERr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0030,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_ptp_clock_cycle_integer_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ptp_clock_cycle_fraction",
+			PTPTM_PTPTM_PTP_CLOCK_CYCLE_FRACTIONr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0034,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_ptp_clock_cycle_fraction_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ptp_configuration",
+			PTPTM_PTPTM_PTP_CONFIGURATIONr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0040,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			18,
+			g_ptptm_ptptm_ptp_configuration_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"timer_control",
+			PTPTM_PTPTM_TIMER_CONTROLr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0044,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_ptptm_ptptm_timer_control_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pps_income_delay",
+			PTPTM_PTPTM_PPS_INCOME_DELAYr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0048,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			2,
+			g_ptptm_ptptm_pps_income_delay_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"clock_cycle_update",
+			PTPTM_PTPTM_CLOCK_CYCLE_UPDATEr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x004c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			5,
+			g_ptptm_ptptm_clock_cycle_update_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cycle_time_of_output_period_pulse_1",
+			PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_1r,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0050,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_cycle_time_of_output_period_pulse_1_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"cycle_time_of_output_period_pulse_2",
+			PTPTM_PTPTM_CYCLE_TIME_OF_OUTPUT_PERIOD_PULSE_2r,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0054,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_cycle_time_of_output_period_pulse_2_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"timer_latch_en",
+			PTPTM_PTPTM_TIMER_LATCH_ENr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0058,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_timer_latch_en_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"timer_latch_sel",
+			PTPTM_PTPTM_TIMER_LATCH_SELr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x005c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_timer_latch_sel_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trigger_in_tod_nanosecond",
+			PTPTM_PTPTM_TRIGGER_IN_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0060,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_trigger_in_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trigger_in_lower_tod_second",
+			PTPTM_PTPTM_TRIGGER_IN_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0064,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_trigger_in_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trigger_in_high_tod_second",
+			PTPTM_PTPTM_TRIGGER_IN_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0068,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_trigger_in_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trigger_in_fracnanosecond",
+			PTPTM_PTPTM_TRIGGER_IN_FRACNANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x006c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_trigger_in_fracnanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trigger_in_hardware_time_low",
+			PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_LOWr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0070,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_trigger_in_hardware_time_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trigger_in_hardware_time_high",
+			PTPTM_PTPTM_TRIGGER_IN_HARDWARE_TIME_HIGHr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0074,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_trigger_in_hardware_time_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trigger_out_tod_nanosecond",
+			PTPTM_PTPTM_TRIGGER_OUT_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0080,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_trigger_out_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trigger_out_lower_tod_second",
+			PTPTM_PTPTM_TRIGGER_OUT_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0084,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_trigger_out_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trigger_out_high_tod_second",
+			PTPTM_PTPTM_TRIGGER_OUT_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0088,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_trigger_out_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trigger_out_hardware_time_low",
+			PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_LOWr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0090,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_trigger_out_hardware_time_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"trigger_out_hardware_time_high",
+			PTPTM_PTPTM_TRIGGER_OUT_HARDWARE_TIME_HIGHr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0094,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_trigger_out_hardware_time_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"adjust_tod_nanosecond",
+			PTPTM_PTPTM_ADJUST_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_adjust_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"adjust_lower_tod_second",
+			PTPTM_PTPTM_ADJUST_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_adjust_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"adjust_high_tod_second",
+			PTPTM_PTPTM_ADJUST_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_adjust_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"adjust_fracnanosecond",
+			PTPTM_PTPTM_ADJUST_FRACNANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_adjust_fracnanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"adjust_hardware_time_low",
+			PTPTM_PTPTM_ADJUST_HARDWARE_TIME_LOWr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_adjust_hardware_time_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"adjust_hardware_time_high",
+			PTPTM_PTPTM_ADJUST_HARDWARE_TIME_HIGHr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_adjust_hardware_time_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"latch_tod_nanosecond",
+			PTPTM_PTPTM_LATCH_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_latch_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"latch_lower_tod_second",
+			PTPTM_PTPTM_LATCH_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_latch_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"latch_high_tod_second",
+			PTPTM_PTPTM_LATCH_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_latch_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"latch_fracnanosecond",
+			PTPTM_PTPTM_LATCH_FRACNANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_latch_fracnanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"latch_hardware_time_low",
+			PTPTM_PTPTM_LATCH_HARDWARE_TIME_LOWr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_latch_hardware_time_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"latch_hardware_time_high",
+			PTPTM_PTPTM_LATCH_HARDWARE_TIME_HIGHr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_latch_hardware_time_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"real_tod_nanosecond",
+			PTPTM_PTPTM_REAL_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_real_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"real_lower_tod_second",
+			PTPTM_PTPTM_REAL_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_real_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"real_high_tod_second",
+			PTPTM_PTPTM_REAL_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_real_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"real_hardware_time_low",
+			PTPTM_PTPTM_REAL_HARDWARE_TIME_LOWr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_real_hardware_time_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"real_hardware_time_high",
+			PTPTM_PTPTM_REAL_HARDWARE_TIME_HIGHr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_real_hardware_time_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ptp1588_event_message_port",
+			PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_PORTr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0100,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_ptp1588_event_message_port_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ptp1588_event_message_timestamp_low",
+			PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_LOWr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0104,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_ptp1588_event_message_timestamp_low_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ptp1588_event_message_timestamp_high",
+			PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_TIMESTAMP_HIGHr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0108,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_ptp1588_event_message_timestamp_high_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"ptp1588_event_message_fifo_status",
+			PTPTM_PTPTM_PTP1588_EVENT_MESSAGE_FIFO_STATUSr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x010c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			3,
+			g_ptptm_ptptm_ptp1588_event_message_fifo_status_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tod_nanosecond",
+			PTPTM_PTPTM_PP1S_LATCH_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0120,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_lower_tod_second",
+			PTPTM_PTPTM_PP1S_LATCH_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0124,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_high_tod_second",
+			PTPTM_PTPTM_PP1S_LATCH_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0128,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_fracnanosecond",
+			PTPTM_PTPTM_PP1S_LATCH_FRACNANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x012c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_fracnanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn_time_configuration",
+			PTPTM_PTPTM_TSN_TIME_CONFIGURATIONr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0140,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_ptptm_ptptm_tsn_time_configuration_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn_timer_control",
+			PTPTM_PTPTM_TSN_TIMER_CONTROLr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00144,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			4,
+			g_ptptm_ptptm_tsn_timer_control_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn0_clock_cycle_integer",
+			PTPTM_PTPTM_TSN0_CLOCK_CYCLE_INTEGERr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x00148,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn0_clock_cycle_integer_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn0_clock_cycle_fraction",
+			PTPTM_PTPTM_TSN0_CLOCK_CYCLE_FRACTIONr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x014c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn0_clock_cycle_fraction_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn1_clock_cycle_integer",
+			PTPTM_PTPTM_TSN1_CLOCK_CYCLE_INTEGERr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0150,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn1_clock_cycle_integer_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn1_clock_cycle_fraction",
+			PTPTM_PTPTM_TSN1_CLOCK_CYCLE_FRACTIONr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0154,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn1_clock_cycle_fraction_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn2_clock_cycle_integer",
+			PTPTM_PTPTM_TSN2_CLOCK_CYCLE_INTEGERr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0158,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn2_clock_cycle_integer_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn2_clock_cycle_fraction",
+			PTPTM_PTPTM_TSN2_CLOCK_CYCLE_FRACTIONr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x015c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn2_clock_cycle_fraction_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn3_clock_cycle_integer",
+			PTPTM_PTPTM_TSN3_CLOCK_CYCLE_INTEGERr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0160,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn3_clock_cycle_integer_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn3_clock_cycle_fraction",
+			PTPTM_PTPTM_TSN3_CLOCK_CYCLE_FRACTIONr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0164,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn3_clock_cycle_fraction_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn0_adjust_tod_nanosecond",
+			PTPTM_PTPTM_TSN0_ADJUST_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0180,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn0_adjust_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn0_adjust_lower_tod_second",
+			PTPTM_PTPTM_TSN0_ADJUST_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0184,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn0_adjust_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn0_adjust_high_tod_second",
+			PTPTM_PTPTM_TSN0_ADJUST_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0188,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn0_adjust_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn0_adjust_fracnanosecond",
+			PTPTM_PTPTM_TSN0_ADJUST_FRACNANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x018c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn0_adjust_fracnanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn1_adjust_tod_nanosecond",
+			PTPTM_PTPTM_TSN1_ADJUST_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0190,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn1_adjust_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn1_adjust_lower_tod_second",
+			PTPTM_PTPTM_TSN1_ADJUST_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0194,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn1_adjust_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn1_adjust_high_tod_second",
+			PTPTM_PTPTM_TSN1_ADJUST_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0198,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn1_adjust_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn1_adjust_fracnanosecond",
+			PTPTM_PTPTM_TSN1_ADJUST_FRACNANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x019c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn1_adjust_fracnanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn2_adjust_tod_nanosecond",
+			PTPTM_PTPTM_TSN2_ADJUST_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn2_adjust_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn2_adjust_lower_tod_second",
+			PTPTM_PTPTM_TSN2_ADJUST_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn2_adjust_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn2_adjust_high_tod_second",
+			PTPTM_PTPTM_TSN2_ADJUST_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01a8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn2_adjust_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn2_adjust_fracnanosecond",
+			PTPTM_PTPTM_TSN2_ADJUST_FRACNANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01ac,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn2_adjust_fracnanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn3_adjust_tod_nanosecond",
+			PTPTM_PTPTM_TSN3_ADJUST_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01b0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn3_adjust_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn3_adjust_lower_tod_second",
+			PTPTM_PTPTM_TSN3_ADJUST_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01b4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn3_adjust_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn3_adjust_high_tod_second",
+			PTPTM_PTPTM_TSN3_ADJUST_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01b8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn3_adjust_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn3_adjust_fracnanosecond",
+			PTPTM_PTPTM_TSN3_ADJUST_FRACNANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01bc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn3_adjust_fracnanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn0_latch_tod_nanosecond",
+			PTPTM_PTPTM_TSN0_LATCH_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01c0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn0_latch_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn0_latch_lower_tod_second",
+			PTPTM_PTPTM_TSN0_LATCH_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01c4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn0_latch_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn0_latch_high_tod_second",
+			PTPTM_PTPTM_TSN0_LATCH_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01c8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn0_latch_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn0_latch_fracnanosecond",
+			PTPTM_PTPTM_TSN0_LATCH_FRACNANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01cc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn0_latch_fracnanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn1_latch_tod_nanosecond",
+			PTPTM_PTPTM_TSN1_LATCH_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01d0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn1_latch_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn1_latch_lower_tod_second",
+			PTPTM_PTPTM_TSN1_LATCH_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01d4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn1_latch_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn1_latch_high_tod_second",
+			PTPTM_PTPTM_TSN1_LATCH_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01d8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn1_latch_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn1_latch_fracnanosecond",
+			PTPTM_PTPTM_TSN1_LATCH_FRACNANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01dc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn1_latch_fracnanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn2_latch_tod_nanosecond",
+			PTPTM_PTPTM_TSN2_LATCH_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01e0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn2_latch_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn2_latch_lower_tod_second",
+			PTPTM_PTPTM_TSN2_LATCH_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01e4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn2_latch_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn2_latch_high_tod_second",
+			PTPTM_PTPTM_TSN2_LATCH_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01e8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn2_latch_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn2_latch_fracnanosecond",
+			PTPTM_PTPTM_TSN2_LATCH_FRACNANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01ec,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn2_latch_fracnanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn3_latch_tod_nanosecond",
+			PTPTM_PTPTM_TSN3_LATCH_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01f0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn3_latch_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn3_latch_lower_tod_second",
+			PTPTM_PTPTM_TSN3_LATCH_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01f4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn3_latch_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn3_latch_high_tod_second",
+			PTPTM_PTPTM_TSN3_LATCH_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01f8,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn3_latch_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn3_latch_fracnanosecond",
+			PTPTM_PTPTM_TSN3_LATCH_FRACNANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x01fc,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn3_latch_fracnanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tsn0_tod_nanosecond",
+			PTPTM_PTPTM_PP1S_LATCH_TSN0_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0200,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tsn0_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tsn0_lower_tod_second",
+			PTPTM_PTPTM_PP1S_LATCH_TSN0_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0204,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tsn0_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tsn0_high_tod_second",
+			PTPTM_PTPTM_PP1S_LATCH_TSN0_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0208,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tsn0_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tsn0_fracnanosecond",
+			PTPTM_PTPTM_PP1S_LATCH_TSN0_FRACNANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x020c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tsn0_fracnanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tsn1_tod_nanosecond",
+			PTPTM_PTPTM_PP1S_LATCH_TSN1_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0210,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tsn1_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tsn1_lower_tod_second",
+			PTPTM_PTPTM_PP1S_LATCH_TSN1_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0214,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tsn1_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tsn1_high_tod_second",
+			PTPTM_PTPTM_PP1S_LATCH_TSN1_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0218,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tsn1_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tsn1_fracnanosecond",
+			PTPTM_PTPTM_PP1S_LATCH_TSN1_FRACNANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x021c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tsn1_fracnanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tsn2_tod_nanosecond",
+			PTPTM_PTPTM_PP1S_LATCH_TSN2_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0220,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tsn2_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tsn2_lower_tod_second",
+			PTPTM_PTPTM_PP1S_LATCH_TSN2_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0224,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tsn2_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tsn2_high_tod_second",
+			PTPTM_PTPTM_PP1S_LATCH_TSN2_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0228,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tsn2_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tsn2_fracnanosecond",
+			PTPTM_PTPTM_PP1S_LATCH_TSN2_FRACNANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x022c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tsn2_fracnanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tsn3_tod_nanosecond",
+			PTPTM_PTPTM_PP1S_LATCH_TSN3_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0230,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tsn3_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tsn3_lower_tod_second",
+			PTPTM_PTPTM_PP1S_LATCH_TSN3_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0234,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tsn3_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tsn3_high_tod_second",
+			PTPTM_PTPTM_PP1S_LATCH_TSN3_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0238,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tsn3_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"pp1s_latch_tsn3_fracnanosecond",
+			PTPTM_PTPTM_PP1S_LATCH_TSN3_FRACNANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x023c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_pp1s_latch_tsn3_fracnanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn0_real_tod_nanosecond",
+			PTPTM_PTPTM_TSN0_REAL_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0240,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn0_real_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn0_real_lower_tod_second",
+			PTPTM_PTPTM_TSN0_REAL_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0244,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn0_real_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn0_real_high_tod_second",
+			PTPTM_PTPTM_TSN0_REAL_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0248,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn0_real_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn1_real_tod_nanosecond",
+			PTPTM_PTPTM_TSN1_REAL_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x024c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn1_real_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn1_real_lower_tod_second",
+			PTPTM_PTPTM_TSN1_REAL_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0250,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn1_real_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn1_real_high_tod_second",
+			PTPTM_PTPTM_TSN1_REAL_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0254,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn1_real_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn2_real_tod_nanosecond",
+			PTPTM_PTPTM_TSN2_REAL_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0258,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn2_real_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn2_real_lower_tod_second",
+			PTPTM_PTPTM_TSN2_REAL_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x025c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn2_real_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn2_real_high_tod_second",
+			PTPTM_PTPTM_TSN2_REAL_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0260,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn2_real_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn3_real_tod_nanosecond",
+			PTPTM_PTPTM_TSN3_REAL_TOD_NANOSECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0264,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn3_real_tod_nanosecond_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn3_real_lower_tod_second",
+			PTPTM_PTPTM_TSN3_REAL_LOWER_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0268,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn3_real_lower_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"tsn3_real_high_tod_second",
+			PTPTM_PTPTM_TSN3_REAL_HIGH_TOD_SECONDr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x026c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_tsn3_real_high_tod_second_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"real_ptp_clock_cycle_integer",
+			PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_INTEGERr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0280,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_real_ptp_clock_cycle_integer_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"real_ptp_clock_cycle_fraction",
+			PTPTM_PTPTM_REAL_PTP_CLOCK_CYCLE_FRACTIONr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0284,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_real_ptp_clock_cycle_fraction_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"real_tsn0_clock_cycle_integer",
+			PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_INTEGERr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0288,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_real_tsn0_clock_cycle_integer_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"real_tsn0_clock_cycle_fraction",
+			PTPTM_PTPTM_REAL_TSN0_CLOCK_CYCLE_FRACTIONr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x028c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_real_tsn0_clock_cycle_fraction_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"real_tsn1_clock_cycle_integer",
+			PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_INTEGERr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0290,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_real_tsn1_clock_cycle_integer_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"real_tsn1_clock_cycle_fraction",
+			PTPTM_PTPTM_REAL_TSN1_CLOCK_CYCLE_FRACTIONr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0294,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_real_tsn1_clock_cycle_fraction_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"real_tsn2_clock_cycle_integer",
+			PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_INTEGERr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x0298,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_real_tsn2_clock_cycle_integer_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"real_tsn2_clock_cycle_fraction",
+			PTPTM_PTPTM_REAL_TSN2_CLOCK_CYCLE_FRACTIONr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x029c,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_real_tsn2_clock_cycle_fraction_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"real_tsn3_clock_cycle_integer",
+			PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_INTEGERr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x02a0,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_real_tsn3_clock_cycle_integer_reg,
+			NULL,
+			NULL,
+	},
+	{
+			"real_tsn3_clock_cycle_fraction",
+			PTPTM_PTPTM_REAL_TSN3_CLOCK_CYCLE_FRACTIONr,
+			PTPTM,
+			DPP_REG_FLAG_DIRECT,
+			DPP_REG_NUL_ARRAY,
+			SYS_PTP1_BASE_ADDR + 0x02a4,
+			(32 / 8),
+			0,
+			0,
+			0,
+			0,
+			1,
+			g_ptptm_ptptm_real_tsn3_clock_cycle_fraction_reg,
+			NULL,
+			NULL,
+	},
 };
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_api.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_api.h
index 4ebda14a14790c0eb0f014cfa2e6c220e8120b51..8a061010e3c5f0fce5264730e5df749729e8cfa2 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_api.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_api.h
@@ -24,149 +24,330 @@
 #include "dpp_drv_eram.h"
 #include "dpp_tbl_comm.h"
 
-#define EGR_FLAG_TPID                       ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, tpid) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_VHCA                       ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, vhca) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_UPLINK_PORT                ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, uplink_port) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_RSS_HASH_FACTOR            ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, rss_hash_factor) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_HASH_ALG                   ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, hash_alg) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_PANEL_ID                   ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, panel_id) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_LAG_ID                     ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, lag_id) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_PF_VQM_VFID                ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, pf_vqm_vfid) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_MTU                        ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, mtu) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_HASH_SEARCH_INDEX          ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, hash_search_index) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_PORT_BASE_QID              ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, port_base_qid) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_FD_EN_OFF                  ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, fd_enable) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_TM_EN_OFF                  ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, tm_enable) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_INGRESS_METER_EN_OFF       ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, ingress_meter_enable) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_EGRESS_METER_EN_OFF        ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, egress_meter_enable) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_INGRESS_MODE               ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, ingress_meter_mode) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_EGRESS_MODE                ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, egress_meter_mode) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_VEPA_EN_OFF                ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, vepa_enable) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_SPOOFCHK_EN_OFF            ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, spoof_check_enable) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_INLINE_SEC_OFFLOAD         ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, inline_sec_offload) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_OVS_EN_OFF                 ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, ovs_enable) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_LAG_EN_OFF                 ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, lag_enable) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_IS_PASSTHROUGH             ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, is_passthrough) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_IS_VF                      ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, is_vf) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_VIRTION_VERSION            ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, virtion_version) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_VIRTION_EN_OFF             ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, virtio_enable) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG   ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, accelerator_offload_flag) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_IPV4_TCP_ASSEMBLE          ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, lro_offload) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_IPV6_TCP_ASSEMBLE          ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, lro_offload) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_IP_FRAGMENT_OFFLOAD        ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, ip_fragment_offload) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_TCP_UDP_CHKSUM             ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, tcp_udp_checksum_offload) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_IP_CHKSUM                  ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, ip_checksum_offload) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD  ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, outer_ip_checksum_offload) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_VPORT_IS_UP                ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, is_up) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_IFF_ALLMULTI_EN_OFF        ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, allmulticast_enable) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_HW_BOND_EN_OFF             ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, hw_bond_enable) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_RDMA_OFFLOAD_EN_OFF        ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, rdma_offload_enable) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_VLAN_FILTER_EN_OFF         ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, vlan_filter_enable) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_VLAN_STRIP_OFFLOAD         ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, vlan_strip_offload) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_QINQ_VLAN_STRIP_OFFLOAD    ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, qinq_vlan_strip_offload) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_RSS_EN_OFF                 ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, rss_enable) / sizeof(ZXIC_UINT32)))
-#define EGR_FLAG_MTU_OFFLOAD_EN_OFF         ((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, mtu_offload_enable) / sizeof(ZXIC_UINT32)))
-
-#define PANEL_FLAG_OVS_PF_VFID              ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, ovs_pf_vfid) / sizeof(ZXIC_UINT32)))
-#define PANEL_FLAG_PF_MEMPORT_QID           ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, pf_memport_qid) / sizeof(ZXIC_UINT32)))
-#define PANEL_FLAG_BOND_PF_VQM_VFID         ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, bond_pf_vqm_vfid) / sizeof(ZXIC_UINT32)))
-#define PANEL_FLAG_IS_UP                    ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, is_up) / sizeof(ZXIC_UINT32)))
-#define PANEL_FLAG_BOND_LINK_UP             ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, bond_link_up) / sizeof(ZXIC_UINT32)))
-#define PANEL_FLAG_HW_BOND_ENABLE           ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, hw_bond_enable) / sizeof(ZXIC_UINT32)))
-#define PANEL_FLAG_MTU                      ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, mtu) / sizeof(ZXIC_UINT32)))
-#define PANEL_FLAG_MTU_OFFLOAD_ENABLE       ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, mtu_offload_enable) / sizeof(ZXIC_UINT32)))
-#define PANEL_FLAG_TM_BASE_QUEUE            ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, tm_base_queue) / sizeof(ZXIC_UINT32)))
-#define PANEL_FLAG_PTP_PORT_VFID            ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, ptp_port_vfid) / sizeof(ZXIC_UINT32)))
-#define PANEL_FLAG_PF_VQM_VFID              ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, pf_vqm_vfid) / sizeof(ZXIC_UINT32)))
-#define PANEL_FLAG_TM_SHAPE_ENABLE          ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, tm_shape_enable) / sizeof(ZXIC_UINT32)))
-#define PANEL_FLAG_PTP_TC_ENABLE            ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, ptp_tc_enable) / sizeof(ZXIC_UINT32)))
-#define PANEL_FLAG_TRUST_MODE               ((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, trust_mode) / sizeof(ZXIC_UINT32)))
-
-ZXIC_UINT32 dpp_vport_create(DPP_PF_INFO_T* pf_info);
-ZXIC_UINT32 dpp_vport_create_by_vqm_vfid(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 vqm_vfid);
-ZXIC_UINT32 dpp_vport_delete(DPP_PF_INFO_T* pf_info);
-ZXIC_UINT32 dpp_egr_port_attr_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 attr, ZXIC_UINT32 value);
-ZXIC_UINT32 dpp_egr_port_attr_get(DPP_PF_INFO_T* pf_info, ZXDH_VPORT_T *port_attr_entry);
-ZXIC_UINT32 dpp_rx_flow_hash_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 hash_mode);
-ZXIC_UINT32 dpp_rx_flow_hash_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *hash_mode);
-ZXIC_UINT32 dpp_vport_hash_index_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *hash_index);
-ZXIC_UINT32 dpp_vport_hash_funcs_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 funcs);
-ZXIC_UINT32 dpp_vport_rss_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable);
-ZXIC_UINT32 dpp_vport_virtio_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable);
-ZXIC_UINT32 dpp_vport_virtio_version_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 version);
-ZXIC_UINT32 dpp_vport_vlan_filter_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable);
-ZXIC_UINT32 dpp_vport_vlan_qinq_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable);
-ZXIC_UINT32 dpp_vport_vlan_strip_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable);
-
-ZXIC_UINT32 dpp_vlan_filter_init(DPP_PF_INFO_T* pf_info);
-ZXIC_UINT32 dpp_add_vlan_filter(DPP_PF_INFO_T* pf_info, ZXIC_UINT16 vlan_id);
-ZXIC_UINT32 dpp_del_vlan_filter(DPP_PF_INFO_T* pf_info, ZXIC_UINT16 vlan_id);
-
-ZXIC_UINT32 dpp_vport_bond_pf(DPP_PF_INFO_T* pf_info);
-ZXIC_UINT32 dpp_vport_unbond_pf(DPP_PF_INFO_T* pf_info);
-
-ZXIC_UINT32 dpp_rxfh_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *queue_list, ZXIC_UINT32 queue_num);
-ZXIC_UINT32 dpp_rxfh_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *queue_list, ZXIC_UINT32 queue_num);
-ZXIC_UINT32 dpp_rxfh_del(DPP_PF_INFO_T* pf_info);
-ZXIC_UINT32 dpp_thash_key_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 *hash_key, ZXIC_UINT32 key_num);
-ZXIC_UINT32 dpp_thash_key_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 *hash_key, ZXIC_UINT32 key_num);
-
-ZXIC_UINT32 dpp_add_mac(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac);
-ZXIC_UINT32 dpp_del_mac(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac);
-ZXIC_UINT32 dpp_unicast_mac_dump(DPP_PF_INFO_T* pf_info, MAC_VPORT_INFO *p_mac_arr, ZXIC_UINT32 *p_mac_num);
-ZXIC_UINT32 dpp_unicast_all_mac_delete(DPP_PF_INFO_T* pf_info);
-ZXIC_UINT32 dpp_unicast_all_mac_online_delete(DPP_PF_INFO_T* pf_info);
-
-ZXIC_UINT32 dpp_multi_mac_add_member(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac);
-ZXIC_UINT32 dpp_multi_mac_del_member(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac);
-ZXIC_UINT32 dpp_multicast_mac_dump(DPP_PF_INFO_T* pf_info, MAC_VPORT_INFO *p_mac_arr, ZXIC_UINT32 *p_mac_num);
-ZXIC_UINT32 dpp_multicast_all_mac_delete(DPP_PF_INFO_T* pf_info);
-ZXIC_UINT32 dpp_multicast_all_mac_online_delete(DPP_PF_INFO_T* pf_info);
-
-ZXIC_UINT32 dpp_ptp_port_vfid_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 ptp_port_vfid);
-ZXIC_UINT32 dpp_ptp_tc_enable_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 ptp_tc_enable);
-
-ZXIC_UINT32 dpp_ipsec_enc_entry_add(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT8 *sip, ZXIC_UINT8 *dip,
-                                    ZXIC_UINT8 *sip_mask, ZXIC_UINT8 *dip_mask, ZXIC_UINT32 is_ipv4, ZXIC_UINT32 sa_id);
-ZXIC_UINT32 dpp_ipsec_enc_entry_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index);
-
-ZXIC_UINT32 dpp_lag_group_create(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id);
-ZXIC_UINT32 dpp_lag_group_delete(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id);
-ZXIC_UINT32 dpp_lag_mode_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id, ZXIC_UINT8 mode);
-ZXIC_UINT32 dpp_lag_group_hash_factor_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id, ZXIC_UINT8 factor);
-ZXIC_UINT32 dpp_lag_group_member_add(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id, ZXIC_UINT8 panel_id);
-ZXIC_UINT32 dpp_lag_group_member_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id, ZXIC_UINT8 panel_id);
-
-ZXIC_UINT32 dpp_panel_bond_vport(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id);
-ZXIC_UINT32 dpp_panel_hardware_bond_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT8 enable);
-ZXIC_UINT32 dpp_panel_bond_pf_vqm_vfid_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT16 vqm_vfid);
-ZXIC_UINT32 dpp_panel_bond_pf_memport_qid_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT16 qid);
-ZXIC_UINT32 dpp_panel_ovs_pf_vqm_vfid_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT16 vqm_vfid);
-ZXIC_UINT32 dpp_panel_attr_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT32 attr, ZXIC_UINT32 value);
-
-ZXIC_UINT32 dpp_vport_uc_promisc_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 enable);
-ZXIC_UINT32 dpp_vport_mc_promisc_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 enable);
-
-ZXIC_UINT32 dpp_stat_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt);
-ZXIC_UINT32 dpp_stat_cnt_get_128(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt);
-ZXIC_UINT32 dpp_stat_mc_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt);
-ZXIC_UINT32 dpp_stat_bc_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt);
-ZXIC_UINT32 dpp_stat_1588_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt);
-ZXIC_UINT32 dpp_stat_1588_packet_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt);
-ZXIC_UINT32 dpp_stat_1588_packet_drop_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt);
-ZXIC_UINT32 dpp_stat_1588_enc_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt);
-ZXIC_UINT32 dpp_stat_1588_enc_packet_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt);
-ZXIC_UINT32 dpp_stat_spoof_packet_drop_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt);
-ZXIC_UINT32 dpp_stat_mcode_packet_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt);
-ZXIC_UINT32 dpp_stat_port_bc_packet_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt);
-ZXIC_UINT32 dpp_stat_port_bc_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt);
-ZXIC_UINT32 dpp_stat_port_RDMA_packet_msg_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt);
-ZXIC_UINT32 dpp_stat_port_RDMA_packet_msg_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt);
-ZXIC_UINT32 dpp_stat_plcr_packet_drop_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt);
-ZXIC_UINT32 dpp_stat_plcr_packet_drop_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt);
-ZXIC_UINT32 dpp_stat_MTU_packet_msg_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt);
-ZXIC_UINT32 dpp_stat_MTU_packet_msg_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt);
-
-ZXIC_UINT32 dpp_vport_vhca_id_add(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 vhca_id);
-ZXIC_UINT32 dpp_vport_vhca_id_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 vhca_id);
+#define EGR_FLAG_TPID \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, tpid) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_VHCA \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, vhca) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_UPLINK_PORT \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, uplink_port) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_RSS_HASH_FACTOR                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, rss_hash_factor) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_HASH_ALG \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, hash_alg) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_PANEL_ID \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, panel_id) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_LAG_ID \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, lag_id) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_PF_VQM_VFID \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, pf_vqm_vfid) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_MTU \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, mtu) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_HASH_SEARCH_INDEX                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, hash_search_index) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_PORT_BASE_QID \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, port_base_qid) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_FD_EN_OFF \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, fd_enable) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_TM_EN_OFF \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, tm_enable) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_INGRESS_METER_EN_OFF                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, ingress_meter_enable) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_EGRESS_METER_EN_OFF                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, egress_meter_enable) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_INGRESS_MODE                                   \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, ingress_meter_mode) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_EGRESS_MODE                                   \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, egress_meter_mode) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_VEPA_EN_OFF \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, vepa_enable) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_SPOOFCHK_EN_OFF                                \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, spoof_check_enable) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_INLINE_SEC_OFFLOAD                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, inline_sec_offload) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_OVS_EN_OFF \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, ovs_enable) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_LAG_EN_OFF \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, lag_enable) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_IS_PASSTHROUGH                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, is_passthrough) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_IS_VF \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, is_vf) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_VIRTION_VERSION                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, virtion_version) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_VIRTION_EN_OFF \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, virtio_enable) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, accelerator_offload_flag) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_IPV4_TCP_ASSEMBLE \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, lro_offload) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_IPV6_TCP_ASSEMBLE \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, lro_offload) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_IP_FRAGMENT_OFFLOAD                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, ip_fragment_offload) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_TCP_UDP_CHKSUM                                       \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, tcp_udp_checksum_offload) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_IP_CHKSUM                                       \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, ip_checksum_offload) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, outer_ip_checksum_offload) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_VPORT_IS_UP \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, is_up) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_IFF_ALLMULTI_EN_OFF                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, allmulticast_enable) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_HW_BOND_EN_OFF                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, hw_bond_enable) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_RDMA_OFFLOAD_EN_OFF                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, rdma_offload_enable) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_VLAN_FILTER_EN_OFF                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, vlan_filter_enable) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_VLAN_STRIP_OFFLOAD                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, vlan_strip_offload) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_QINQ_VLAN_STRIP_OFFLOAD                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, qinq_vlan_strip_offload) / \
+				   sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_RSS_EN_OFF \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, rss_enable) / sizeof(ZXIC_UINT32)))
+#define EGR_FLAG_MTU_OFFLOAD_EN_OFF                             \
+	((ZXIC_UINT32)(offsetof(ZXDH_VPORT_T, mtu_offload_enable) / \
+				   sizeof(ZXIC_UINT32)))
+
+#define PANEL_FLAG_OVS_PF_VFID                                \
+	((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, ovs_pf_vfid) / \
+				   sizeof(ZXIC_UINT32)))
+#define PANEL_FLAG_PF_MEMPORT_QID                                \
+	((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, pf_memport_qid) / \
+				   sizeof(ZXIC_UINT32)))
+#define PANEL_FLAG_BOND_PF_VQM_VFID                                \
+	((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, bond_pf_vqm_vfid) / \
+				   sizeof(ZXIC_UINT32)))
+#define PANEL_FLAG_IS_UP \
+	((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, is_up) / sizeof(ZXIC_UINT32)))
+#define PANEL_FLAG_BOND_LINK_UP                                \
+	((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, bond_link_up) / \
+				   sizeof(ZXIC_UINT32)))
+#define PANEL_FLAG_HW_BOND_ENABLE                                \
+	((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, hw_bond_enable) / \
+				   sizeof(ZXIC_UINT32)))
+#define PANEL_FLAG_MTU \
+	((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, mtu) / sizeof(ZXIC_UINT32)))
+#define PANEL_FLAG_MTU_OFFLOAD_ENABLE                                \
+	((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, mtu_offload_enable) / \
+				   sizeof(ZXIC_UINT32)))
+#define PANEL_FLAG_TM_BASE_QUEUE                                \
+	((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, tm_base_queue) / \
+				   sizeof(ZXIC_UINT32)))
+#define PANEL_FLAG_PTP_PORT_VFID                                \
+	((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, ptp_port_vfid) / \
+				   sizeof(ZXIC_UINT32)))
+#define PANEL_FLAG_PF_VQM_VFID                                \
+	((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, pf_vqm_vfid) / \
+				   sizeof(ZXIC_UINT32)))
+#define PANEL_FLAG_TM_SHAPE_ENABLE                                \
+	((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, tm_shape_enable) / \
+				   sizeof(ZXIC_UINT32)))
+#define PANEL_FLAG_PTP_TC_ENABLE                                \
+	((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, ptp_tc_enable) / \
+				   sizeof(ZXIC_UINT32)))
+#define PANEL_FLAG_TRUST_MODE                                \
+	((ZXIC_UINT32)(offsetof(ZXDH_PANEL_PORT_T, trust_mode) / \
+				   sizeof(ZXIC_UINT32)))
+
+ZXIC_UINT32 dpp_vport_create(DPP_PF_INFO_T *pf_info);
+ZXIC_UINT32 dpp_vport_create_by_vqm_vfid(DPP_PF_INFO_T *pf_info,
+										 ZXIC_UINT32 vqm_vfid);
+ZXIC_UINT32 dpp_vport_delete(DPP_PF_INFO_T *pf_info);
+ZXIC_UINT32 dpp_egr_port_attr_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 attr,
+								  ZXIC_UINT32 value);
+ZXIC_UINT32 dpp_egr_port_attr_get(DPP_PF_INFO_T *pf_info,
+								  ZXDH_VPORT_T *port_attr_entry);
+ZXIC_UINT32 dpp_rx_flow_hash_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 hash_mode);
+ZXIC_UINT32 dpp_rx_flow_hash_get(DPP_PF_INFO_T *pf_info,
+								 ZXIC_UINT32 *hash_mode);
+ZXIC_UINT32 dpp_vport_hash_index_get(DPP_PF_INFO_T *pf_info,
+									 ZXIC_UINT32 *hash_index);
+ZXIC_UINT32 dpp_vport_hash_funcs_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 funcs);
+ZXIC_UINT32 dpp_vport_rss_en_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 enable);
+ZXIC_UINT32 dpp_vport_virtio_en_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 enable);
+ZXIC_UINT32 dpp_vport_virtio_version_set(DPP_PF_INFO_T *pf_info,
+										 ZXIC_UINT8 version);
+ZXIC_UINT32 dpp_vport_vlan_filter_en_set(DPP_PF_INFO_T *pf_info,
+										 ZXIC_UINT8 enable);
+ZXIC_UINT32 dpp_vport_vlan_qinq_en_set(DPP_PF_INFO_T *pf_info,
+									   ZXIC_UINT8 enable);
+ZXIC_UINT32 dpp_vport_vlan_strip_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 enable);
+
+ZXIC_UINT32 dpp_vlan_filter_init(DPP_PF_INFO_T *pf_info);
+ZXIC_UINT32 dpp_add_vlan_filter(DPP_PF_INFO_T *pf_info, ZXIC_UINT16 vlan_id);
+ZXIC_UINT32 dpp_del_vlan_filter(DPP_PF_INFO_T *pf_info, ZXIC_UINT16 vlan_id);
+
+ZXIC_UINT32 dpp_vport_bond_pf(DPP_PF_INFO_T *pf_info);
+ZXIC_UINT32 dpp_vport_unbond_pf(DPP_PF_INFO_T *pf_info);
+
+ZXIC_UINT32 dpp_rxfh_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 *queue_list,
+						 ZXIC_UINT32 queue_num);
+ZXIC_UINT32 dpp_rxfh_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 *queue_list,
+						 ZXIC_UINT32 queue_num);
+ZXIC_UINT32 dpp_rxfh_del(DPP_PF_INFO_T *pf_info);
+ZXIC_UINT32 dpp_thash_key_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 *hash_key,
+							  ZXIC_UINT32 key_num);
+ZXIC_UINT32 dpp_thash_key_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 *hash_key,
+							  ZXIC_UINT32 key_num);
+
+ZXIC_UINT32 dpp_add_mac(DPP_PF_INFO_T *pf_info, ZXIC_CONST ZXIC_VOID *mac);
+ZXIC_UINT32 dpp_del_mac(DPP_PF_INFO_T *pf_info, ZXIC_CONST ZXIC_VOID *mac);
+ZXIC_UINT32 dpp_unicast_mac_dump(DPP_PF_INFO_T *pf_info,
+								 MAC_VPORT_INFO *p_mac_arr,
+								 ZXIC_UINT32 *p_mac_num);
+ZXIC_UINT32 dpp_unicast_all_mac_delete(DPP_PF_INFO_T *pf_info);
+ZXIC_UINT32 dpp_unicast_all_mac_online_delete(DPP_PF_INFO_T *pf_info);
+
+ZXIC_UINT32 dpp_multi_mac_add_member(DPP_PF_INFO_T *pf_info,
+									 ZXIC_CONST ZXIC_VOID *mac);
+ZXIC_UINT32 dpp_multi_mac_del_member(DPP_PF_INFO_T *pf_info,
+									 ZXIC_CONST ZXIC_VOID *mac);
+ZXIC_UINT32 dpp_multicast_mac_dump(DPP_PF_INFO_T *pf_info,
+								   MAC_VPORT_INFO *p_mac_arr,
+								   ZXIC_UINT32 *p_mac_num);
+ZXIC_UINT32 dpp_multicast_all_mac_delete(DPP_PF_INFO_T *pf_info);
+ZXIC_UINT32 dpp_multicast_all_mac_online_delete(DPP_PF_INFO_T *pf_info);
+
+ZXIC_UINT32 dpp_ptp_port_vfid_set(DPP_PF_INFO_T *pf_info,
+								  ZXIC_UINT32 ptp_port_vfid);
+ZXIC_UINT32 dpp_ptp_tc_enable_set(DPP_PF_INFO_T *pf_info,
+								  ZXIC_UINT32 ptp_tc_enable);
+
+ZXIC_UINT32 dpp_ipsec_enc_entry_add(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 index,
+									ZXIC_UINT8 *sip, ZXIC_UINT8 *dip,
+									ZXIC_UINT8 *sip_mask, ZXIC_UINT8 *dip_mask,
+									ZXIC_UINT32 is_ipv4, ZXIC_UINT32 sa_id);
+ZXIC_UINT32 dpp_ipsec_enc_entry_del(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 index);
+
+ZXIC_UINT32 dpp_lag_group_create(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 lag_id);
+ZXIC_UINT32 dpp_lag_group_delete(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 lag_id);
+ZXIC_UINT32 dpp_lag_mode_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 lag_id,
+							 ZXIC_UINT8 mode);
+ZXIC_UINT32 dpp_lag_group_hash_factor_set(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT8 lag_id, ZXIC_UINT8 factor);
+ZXIC_UINT32 dpp_lag_group_member_add(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 lag_id,
+									 ZXIC_UINT8 panel_id);
+ZXIC_UINT32 dpp_lag_group_member_del(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 lag_id,
+									 ZXIC_UINT8 panel_id);
+
+ZXIC_UINT32 dpp_panel_bond_vport(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 panel_id);
+ZXIC_UINT32 dpp_panel_hardware_bond_set(DPP_PF_INFO_T *pf_info,
+										ZXIC_UINT8 panel_id, ZXIC_UINT8 enable);
+ZXIC_UINT32 dpp_panel_bond_pf_vqm_vfid_set(DPP_PF_INFO_T *pf_info,
+										   ZXIC_UINT8 panel_id,
+										   ZXIC_UINT16 vqm_vfid);
+ZXIC_UINT32 dpp_panel_bond_pf_memport_qid_set(DPP_PF_INFO_T *pf_info,
+											  ZXIC_UINT8 panel_id,
+											  ZXIC_UINT16 qid);
+ZXIC_UINT32 dpp_panel_ovs_pf_vqm_vfid_set(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT8 panel_id,
+										  ZXIC_UINT16 vqm_vfid);
+ZXIC_UINT32 dpp_panel_attr_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 panel_id,
+							   ZXIC_UINT32 attr, ZXIC_UINT32 value);
+
+ZXIC_UINT32 dpp_vport_uc_promisc_set(DPP_PF_INFO_T *pf_info,
+									 ZXIC_UINT32 enable);
+ZXIC_UINT32 dpp_vport_mc_promisc_set(DPP_PF_INFO_T *pf_info,
+									 ZXIC_UINT32 enable);
+
+ZXIC_UINT32 dpp_stat_cnt_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 index,
+							 ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt);
+ZXIC_UINT32 dpp_stat_cnt_get_128(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 index,
+								 ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt,
+								 ZXIC_UINT64 *p_pk_cnt);
+ZXIC_UINT32 dpp_stat_mc_packet_rx_cnt_get(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 index, ZXIC_UINT32 mode,
+										  ZXIC_UINT64 *p_cnt);
+ZXIC_UINT32 dpp_stat_bc_packet_rx_cnt_get(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 index, ZXIC_UINT32 mode,
+										  ZXIC_UINT64 *p_cnt);
+ZXIC_UINT32 dpp_stat_1588_packet_rx_cnt_get(DPP_PF_INFO_T *pf_info,
+											ZXIC_UINT32 index, ZXIC_UINT32 mode,
+											ZXIC_UINT64 *p_cnt);
+ZXIC_UINT32 dpp_stat_1588_packet_tx_cnt_get(DPP_PF_INFO_T *pf_info,
+											ZXIC_UINT32 index, ZXIC_UINT32 mode,
+											ZXIC_UINT64 *p_cnt);
+ZXIC_UINT32 dpp_stat_1588_packet_drop_cnt_get(DPP_PF_INFO_T *pf_info,
+											  ZXIC_UINT32 index,
+											  ZXIC_UINT32 mode,
+											  ZXIC_UINT64 *p_cnt);
+ZXIC_UINT32 dpp_stat_1588_enc_packet_rx_cnt_get(DPP_PF_INFO_T *pf_info,
+												ZXIC_UINT32 index,
+												ZXIC_UINT32 mode,
+												ZXIC_UINT64 *p_cnt);
+ZXIC_UINT32 dpp_stat_1588_enc_packet_tx_cnt_get(DPP_PF_INFO_T *pf_info,
+												ZXIC_UINT32 index,
+												ZXIC_UINT32 mode,
+												ZXIC_UINT64 *p_cnt);
+ZXIC_UINT32 dpp_stat_spoof_packet_drop_cnt_get(DPP_PF_INFO_T *pf_info,
+											   ZXIC_UINT32 index,
+											   ZXIC_UINT32 mode,
+											   ZXIC_UINT64 *p_cnt);
+ZXIC_UINT32 dpp_stat_mcode_packet_cnt_get(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 index, ZXIC_UINT32 mode,
+										  ZXIC_UINT64 *p_cnt);
+ZXIC_UINT32 dpp_stat_port_bc_packet_tx_cnt_get(DPP_PF_INFO_T *pf_info,
+											   ZXIC_UINT32 index,
+											   ZXIC_UINT32 mode,
+											   ZXIC_UINT64 *p_cnt);
+ZXIC_UINT32 dpp_stat_port_bc_packet_rx_cnt_get(DPP_PF_INFO_T *pf_info,
+											   ZXIC_UINT32 index,
+											   ZXIC_UINT32 mode,
+											   ZXIC_UINT64 *p_cnt);
+ZXIC_UINT32 dpp_stat_port_RDMA_packet_msg_tx_cnt_get(DPP_PF_INFO_T *pf_info,
+													 ZXIC_UINT32 index,
+													 ZXIC_UINT32 mode,
+													 ZXIC_UINT64 *p_pkB_cnt,
+													 ZXIC_UINT64 *p_pk_cnt);
+ZXIC_UINT32 dpp_stat_port_RDMA_packet_msg_rx_cnt_get(DPP_PF_INFO_T *pf_info,
+													 ZXIC_UINT32 index,
+													 ZXIC_UINT32 mode,
+													 ZXIC_UINT64 *p_pkB_cnt,
+													 ZXIC_UINT64 *p_pk_cnt);
+ZXIC_UINT32 dpp_stat_plcr_packet_drop_tx_cnt_get(DPP_PF_INFO_T *pf_info,
+												 ZXIC_UINT32 index,
+												 ZXIC_UINT32 mode,
+												 ZXIC_UINT64 *p_pkB_cnt,
+												 ZXIC_UINT64 *p_pk_cnt);
+ZXIC_UINT32 dpp_stat_plcr_packet_drop_rx_cnt_get(DPP_PF_INFO_T *pf_info,
+												 ZXIC_UINT32 index,
+												 ZXIC_UINT32 mode,
+												 ZXIC_UINT64 *p_pkB_cnt,
+												 ZXIC_UINT64 *p_pk_cnt);
+ZXIC_UINT32 dpp_stat_MTU_packet_msg_tx_cnt_get(DPP_PF_INFO_T *pf_info,
+											   ZXIC_UINT32 index,
+											   ZXIC_UINT32 mode,
+											   ZXIC_UINT64 *p_pkB_cnt,
+											   ZXIC_UINT64 *p_pk_cnt);
+ZXIC_UINT32 dpp_stat_MTU_packet_msg_rx_cnt_get(DPP_PF_INFO_T *pf_info,
+											   ZXIC_UINT32 index,
+											   ZXIC_UINT32 mode,
+											   ZXIC_UINT64 *p_pkB_cnt,
+											   ZXIC_UINT64 *p_pk_cnt);
+
+ZXIC_UINT32 dpp_vport_vhca_id_add(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 vhca_id);
+ZXIC_UINT32 dpp_vport_vhca_id_del(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 vhca_id);
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_bc.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_bc.h
index 01f42cc90ebdfcadc087606eba92a4b52bac9b35..2eef1f74247cb4431572f312edc028b3aad8d69f 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_bc.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_bc.h
@@ -23,17 +23,15 @@
 #include "zxic_common.h"
 #include "dpp_type_api.h"
 
-#define BC_GROUP_NUM                (4)
-#define BC_MEMBER_NUM_IN_GROUP      (64)
+#define BC_GROUP_NUM (4)
+#define BC_MEMBER_NUM_IN_GROUP (64)
 
-typedef struct dpp_vport_bc_info_t
-{
-    ZXIC_UINT64 bc_bitmap[BC_GROUP_NUM];
+typedef struct dpp_vport_bc_info_t {
+	ZXIC_UINT64 bc_bitmap[BC_GROUP_NUM];
 } DPP_VPORT_BC_INFO_T;
 
-typedef struct dpp_vport_bc_table_t
-{
-    DPP_VPORT_BC_INFO_T bc_info;
+typedef struct dpp_vport_bc_table_t {
+	DPP_VPORT_BC_INFO_T bc_info;
 } DPP_VPORT_BC_TABLE_T;
 
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_comm.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_comm.h
index 7e6852f599fd7fd0f78cb7640fe95af00965d757..9598b8428a23afedbeb00f9037de94531d9a76c6 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_comm.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_comm.h
@@ -29,51 +29,60 @@
 #include "dpp_tbl_bc.h"
 #include "dpp_tbl_promisc.h"
 
-#define VF_ACTIVE(VPORT)            ((VPORT & 0x0800) >> 11)
-#define EPID(VPORT)                 ((VPORT & 0x7000) >> 12)
-#define FUNC_NUM(VPORT)             ((VPORT & 0x0700) >> 8) 
-#define VFUNC_NUM(VPORT)            ((VPORT & 0x00FF)) 
+#define VF_ACTIVE(VPORT) ((VPORT & 0x0800) >> 11)
+#define EPID(VPORT) ((VPORT & 0x7000) >> 12)
+#define FUNC_NUM(VPORT) ((VPORT & 0x0700) >> 8)
+#define VFUNC_NUM(VPORT) ((VPORT & 0x00FF))
 
-#define PF_VQM_VFID_OFFSET          (1152)
-#define IS_PF(VPORT)                (!VF_ACTIVE(VPORT))
-#define VQM_VFID(VPORT)             (IS_PF(VPORT) ? \
-                                    (PF_VQM_VFID_OFFSET + (EPID(VPORT) * 8) + FUNC_NUM(VPORT)) : \
-                                    ((EPID(VPORT) * 256) + VFUNC_NUM(VPORT)))
+#define PF_VQM_VFID_OFFSET (1152)
+#define IS_PF(VPORT) (!VF_ACTIVE(VPORT))
+#define VQM_VFID(VPORT)                                                        \
+	(IS_PF(VPORT) ? (PF_VQM_VFID_OFFSET + EPID(VPORT) * 8 + FUNC_NUM(VPORT)) : \
+					  (EPID(VPORT) * 256 + VFUNC_NUM(VPORT)))
 
-#define OWNER_PF_VQM_VFID(VPORT)    (PF_VQM_VFID_OFFSET + (EPID(VPORT) * 8) + FUNC_NUM(VPORT))
-#define OWNER_PF_VPORT(VPORT)       (((EPID(VPORT)) << 12) | ((FUNC_NUM(VPORT)) << 8))
+#define OWNER_PF_VQM_VFID(VPORT) \
+	(PF_VQM_VFID_OFFSET + EPID(VPORT) * 8 + FUNC_NUM(VPORT))
+#define OWNER_PF_VPORT(VPORT) (((EPID(VPORT)) << 12) | ((FUNC_NUM(VPORT)) << 8))
 
-#define VQM_VFID_MAX_NUM            (2048)
+#define VQM_VFID_MAX_NUM (2048)
 
-typedef struct dpp_vport_mgr_t
-{
-    DPP_VPORT_BC_TABLE_T        bc_table;
-    DPP_VPORT_MC_TABLE_T        mc_table;
-    DPP_VPORT_PROMISC_TABLE_T   uc_promisc_table;
-    DPP_VPORT_PROMISC_TABLE_T   mc_promisc_table;
+typedef struct dpp_vport_mgr_t {
+	DPP_VPORT_BC_TABLE_T bc_table;
+	DPP_VPORT_MC_TABLE_T mc_table;
+	DPP_VPORT_PROMISC_TABLE_T uc_promisc_table;
+	DPP_VPORT_PROMISC_TABLE_T mc_promisc_table;
 } DPP_VPORT_MGR_T;
 
-typedef struct
-{
-    uint8_t addr[6];
-    uint16_t vport;
-}MAC_VPORT_INFO;
+typedef struct {
+	uint8_t addr[6];
+	uint16_t vport;
+} MAC_VPORT_INFO;
 
-typedef struct
-{
-    uint8_t mc_addr[6];
-    uint16_t pf_flag;
-}MC_PF_FLAG_MGR;
+typedef struct {
+	uint8_t mc_addr[6];
+	uint16_t pf_flag;
+} MC_PF_FLAG_MGR;
 
 ZXIC_UINT32 dpp_data_print(ZXIC_UINT8 *data, ZXIC_UINT32 len);
 ZXIC_UINT32 dpp_vport_attr_value_show(ZXIC_VOID);
-ZXIC_UINT32 dpp_vport_mgr_init(DPP_PF_INFO_T* pf_info);
-ZXIC_UINT32 dpp_vport_mgr_release(DPP_PF_INFO_T* pf_info);
-ZXIC_UINT32 dpp_vport_bc_table_get(DPP_PF_INFO_T* pf_info, DPP_VPORT_BC_TABLE_T** bc_table);
-ZXIC_UINT32 dpp_vport_mc_table_get(DPP_PF_INFO_T* pf_info, DPP_VPORT_MC_TABLE_T** mc_table);
-ZXIC_UINT32 dpp_vport_uc_promisc_table_get(DPP_PF_INFO_T* pf_info, DPP_VPORT_PROMISC_TABLE_T** promisc_table);
-ZXIC_UINT32 dpp_vport_mc_promisc_table_get(DPP_PF_INFO_T* pf_info, DPP_VPORT_PROMISC_TABLE_T** promisc_table);
-ZXIC_UINT32 dpp_vport_get_by_vqm_vfid(ZXIC_UINT16 pf_vport, ZXIC_UINT32 vqm_vfid, ZXIC_UINT16* vport);
-ZXIC_UINT32 dpp_vport_get_by_mc_bitmap(ZXIC_UINT16 pf_vport, ZXIC_UINT32 group_id, ZXIC_UINT64 mc_bitmap, ZXIC_UINT16 vport[64], ZXIC_UINT32* vport_num);
+ZXIC_UINT32 dpp_vport_mgr_init(DPP_PF_INFO_T *pf_info);
+ZXIC_UINT32 dpp_vport_mgr_release(DPP_PF_INFO_T *pf_info);
+ZXIC_UINT32 dpp_vport_bc_table_get(DPP_PF_INFO_T *pf_info,
+								   DPP_VPORT_BC_TABLE_T **bc_table);
+ZXIC_UINT32 dpp_vport_mc_table_get(DPP_PF_INFO_T *pf_info,
+								   DPP_VPORT_MC_TABLE_T **mc_table);
+ZXIC_UINT32
+dpp_vport_uc_promisc_table_get(DPP_PF_INFO_T *pf_info,
+							   DPP_VPORT_PROMISC_TABLE_T **promisc_table);
+ZXIC_UINT32
+dpp_vport_mc_promisc_table_get(DPP_PF_INFO_T *pf_info,
+							   DPP_VPORT_PROMISC_TABLE_T **promisc_table);
+ZXIC_UINT32 dpp_vport_get_by_vqm_vfid(ZXIC_UINT16 pf_vport,
+									  ZXIC_UINT32 vqm_vfid, ZXIC_UINT16 *vport);
+ZXIC_UINT32 dpp_vport_get_by_mc_bitmap(ZXIC_UINT16 pf_vport,
+									   ZXIC_UINT32 group_id,
+									   ZXIC_UINT64 mc_bitmap,
+									   ZXIC_UINT16 vport[64],
+									   ZXIC_UINT32 *vport_num);
 
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_diag.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_diag.h
index e2c609d00aae41e906e16aba5c8af10f6d070337..913d6c1516e6813ae1a07e4efc16aabe21798648 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_diag.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_diag.h
@@ -23,34 +23,47 @@
 #include "zxic_common.h"
 #include "dpp_type_api.h"
 
-ZXIC_CONST ZXIC_CHAR* dpp_vport_table_attr_name_get(ZXIC_UINT32 attr);
-ZXIC_CONST ZXIC_CHAR* dpp_vport_panel_table_attr_name_get(ZXIC_UINT32 attr);
+ZXIC_CHAR *dpp_vport_table_attr_name_get(ZXIC_UINT32 attr);
+ZXIC_CHAR *dpp_vport_panel_table_attr_name_get(ZXIC_UINT32 attr);
 
 ZXIC_UINT32 diag_dpp_vport_mac_add(ZXIC_UINT16 slot, ZXIC_UINT16 vport,
-                                   ZXIC_UINT8 mac0, ZXIC_UINT8 mac1, ZXIC_UINT8 mac2,
-                                   ZXIC_UINT8 mac3, ZXIC_UINT8 mac4, ZXIC_UINT8 mac5);
+								   ZXIC_UINT8 mac0, ZXIC_UINT8 mac1,
+								   ZXIC_UINT8 mac2, ZXIC_UINT8 mac3,
+								   ZXIC_UINT8 mac4, ZXIC_UINT8 mac5);
 ZXIC_UINT32 diag_dpp_vport_mac_del(ZXIC_UINT16 slot, ZXIC_UINT16 vport,
-                                   ZXIC_UINT8 mac0, ZXIC_UINT8 mac1, ZXIC_UINT8 mac2,
-                                   ZXIC_UINT8 mac3, ZXIC_UINT8 mac4, ZXIC_UINT8 mac5);
+								   ZXIC_UINT8 mac0, ZXIC_UINT8 mac1,
+								   ZXIC_UINT8 mac2, ZXIC_UINT8 mac3,
+								   ZXIC_UINT8 mac4, ZXIC_UINT8 mac5);
 ZXIC_UINT32 diag_dpp_vport_mac_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport);
 ZXIC_UINT32 diag_dpp_vport_mc_mac_add(ZXIC_UINT16 slot, ZXIC_UINT16 vport,
-                                   ZXIC_UINT8 mac0, ZXIC_UINT8 mac1, ZXIC_UINT8 mac2,
-                                   ZXIC_UINT8 mac3, ZXIC_UINT8 mac4, ZXIC_UINT8 mac5);
+									  ZXIC_UINT8 mac0, ZXIC_UINT8 mac1,
+									  ZXIC_UINT8 mac2, ZXIC_UINT8 mac3,
+									  ZXIC_UINT8 mac4, ZXIC_UINT8 mac5);
 ZXIC_UINT32 diag_dpp_vport_mc_mac_del(ZXIC_UINT16 slot, ZXIC_UINT16 vport,
-                                   ZXIC_UINT8 mac0, ZXIC_UINT8 mac1, ZXIC_UINT8 mac2,
-                                   ZXIC_UINT8 mac3, ZXIC_UINT8 mac4, ZXIC_UINT8 mac5);
+									  ZXIC_UINT8 mac0, ZXIC_UINT8 mac1,
+									  ZXIC_UINT8 mac2, ZXIC_UINT8 mac3,
+									  ZXIC_UINT8 mac4, ZXIC_UINT8 mac5);
 ZXIC_UINT32 diag_dpp_vport_mc_mac_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport);
-ZXIC_UINT32 diag_dpp_vport_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 attr,
-                                                                         ZXIC_UINT32 value);
+ZXIC_UINT32 diag_dpp_vport_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport,
+									 ZXIC_UINT32 attr, ZXIC_UINT32 value);
 ZXIC_UINT32 diag_dpp_vport_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport);
-ZXIC_UINT32 diag_dpp_vport_panel_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT8 panel_id,
-                                                                ZXIC_UINT32 attr, ZXIC_UINT32 value);
-ZXIC_UINT32 diag_dpp_vport_panel_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT8 panel_id);
-ZXIC_UINT32 diag_dpp_vport_bc_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 enable);
+ZXIC_UINT32 diag_dpp_vport_panel_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport,
+										   ZXIC_UINT8 panel_id,
+										   ZXIC_UINT32 attr, ZXIC_UINT32 value);
+ZXIC_UINT32 diag_dpp_vport_panel_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport,
+										   ZXIC_UINT8 panel_id);
+ZXIC_UINT32 diag_dpp_vport_bc_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport,
+										ZXIC_UINT32 enable);
 ZXIC_UINT32 diag_dpp_vport_bc_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport);
-ZXIC_UINT32 diag_dpp_vport_uc_promisc_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 enable);
-ZXIC_UINT32 diag_dpp_vport_uc_promisc_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport);
-ZXIC_UINT32 diag_dpp_vport_mc_promisc_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 enable);
-ZXIC_UINT32 diag_dpp_vport_mc_promisc_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport);
+ZXIC_UINT32 diag_dpp_vport_uc_promisc_table_set(ZXIC_UINT16 slot,
+												ZXIC_UINT16 vport,
+												ZXIC_UINT32 enable);
+ZXIC_UINT32 diag_dpp_vport_uc_promisc_table_prt(ZXIC_UINT16 slot,
+												ZXIC_UINT16 vport);
+ZXIC_UINT32 diag_dpp_vport_mc_promisc_table_set(ZXIC_UINT16 slot,
+												ZXIC_UINT16 vport,
+												ZXIC_UINT32 enable);
+ZXIC_UINT32 diag_dpp_vport_mc_promisc_table_prt(ZXIC_UINT16 slot,
+												ZXIC_UINT16 vport);
 
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_lag.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_lag.h
index 02381599c89bd9fb8953c8eae5609fbfeab3ae0e..206a4639b1c32d391dbca1edebd8e01d5bcb3be3 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_lag.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_lag.h
@@ -23,7 +23,7 @@
 #include "zxic_common.h"
 #include "dpp_type_api.h"
 
-#define LAG_LACP_MODE       (2)
-#define LAG_STANDBY_MODE    (1)
+#define LAG_LACP_MODE (2)
+#define LAG_STANDBY_MODE (1)
 
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_mc.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_mc.h
index 97a354b6aa745a3a21082f5ac933f39c2e9b38d0..29316653acdb08c6c019dfb0d9090146b3c58e7a 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_mc.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_mc.h
@@ -23,21 +23,19 @@
 #include "zxic_common.h"
 #include "dpp_type_api.h"
 
-#define MC_TABLE_SIZE           (32)
-#define MC_GROUP_NUM            (4)
-#define MC_MEMBER_NUM_IN_GROUP  (64)
+#define MC_TABLE_SIZE (32)
+#define MC_GROUP_NUM (4)
+#define MC_MEMBER_NUM_IN_GROUP (64)
 
-typedef struct dpp_vport_mc_info_t
-{
-    ZXIC_UINT32 is_valid;
-    ZXIC_UINT8  mac[6];
-    ZXIC_UINT32 mc_pf_enable;
-    ZXIC_UINT64 mc_bitmap[MC_GROUP_NUM];
+typedef struct dpp_vport_mc_info_t {
+	ZXIC_UINT32 is_valid;
+	ZXIC_UINT8 mac[6];
+	ZXIC_UINT32 mc_pf_enable;
+	ZXIC_UINT64 mc_bitmap[MC_GROUP_NUM];
 } DPP_VPORT_MC_INFO_T;
 
-typedef struct dpp_vport_mc_table_t
-{
-    DPP_VPORT_MC_INFO_T mc_info[MC_TABLE_SIZE];
+typedef struct dpp_vport_mc_table_t {
+	DPP_VPORT_MC_INFO_T mc_info[MC_TABLE_SIZE];
 } DPP_VPORT_MC_TABLE_T;
 
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_promisc.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_promisc.h
index e97a7c74124660e174170371f6a086ef193b3c43..8e0be17c3905fca3060a06c93189faf39c7056d2 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_promisc.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_promisc.h
@@ -23,18 +23,16 @@
 #include "zxic_common.h"
 #include "dpp_type_api.h"
 
-#define PROMISC_GROUP_NUM                (4)
-#define PROMISC_MEMBER_NUM_IN_GROUP      (64)
+#define PROMISC_GROUP_NUM (4)
+#define PROMISC_MEMBER_NUM_IN_GROUP (64)
 
-typedef struct dpp_vport_promisc_info_t
-{
-    ZXIC_UINT32 pf_enable;
-    ZXIC_UINT64 bitmap[PROMISC_GROUP_NUM];
+typedef struct dpp_vport_promisc_info_t {
+	ZXIC_UINT32 pf_enable;
+	ZXIC_UINT64 bitmap[PROMISC_GROUP_NUM];
 } DPP_VPORT_PROMISC_INFO_T;
 
-typedef struct dpp_vport_uc_promisc_table_t
-{
-    DPP_VPORT_PROMISC_INFO_T promisc_info;
+typedef struct dpp_vport_uc_promisc_table_t {
+	DPP_VPORT_PROMISC_INFO_T promisc_info;
 } DPP_VPORT_PROMISC_TABLE_T;
 
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_qid.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_qid.h
index b233da2fe82e52582ffb5c01835431e1d79b8634..fdb2832f898c205367880fc5b786a4ab66352e49 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_qid.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_qid.h
@@ -23,6 +23,6 @@
 #include "zxic_common.h"
 #include "dpp_type_api.h"
 
-#define RSS_TO_VQID_GROUP_NUM   (32)
+#define RSS_TO_VQID_GROUP_NUM (32)
 
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_stat.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_stat.h
index 4a1872843bcfccea83a08baddef14fae37c5eb0e..eb953046d8531eac50a346a279b3616a092aff6c 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_stat.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_stat.h
@@ -23,55 +23,59 @@
 #include "zxic_common.h"
 #include "dpp_type_api.h"
 
-#define DPP_STAT_MC_PACKET_RX_CNT_ERAM_BAADDR           ((ZXIC_UINT32)(0x1A))
-#define DPP_STAT_MC_PACKET_RX_CNT_ERAM_DEPTH            ((ZXIC_UINT32)(40))
+#define DPP_STAT_MC_PACKET_RX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0x1A))
+#define DPP_STAT_MC_PACKET_RX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(40))
 
-#define DPP_STAT_BC_PACKET_RX_CNT_ERAM_BAADDR           ((ZXIC_UINT32)(0x42))
-#define DPP_STAT_BC_PACKET_RX_CNT_ERAM_DEPTH            ((ZXIC_UINT32)(40 * 1024))
+#define DPP_STAT_BC_PACKET_RX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0x42))
+#define DPP_STAT_BC_PACKET_RX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(40 * 1024))
 
-#define DPP_STAT_1588_PACKET_RX_CNT_ERAM_BAADDR         ((ZXIC_UINT32)(0xA042))
-#define DPP_STAT_1588_PACKET_RX_CNT_ERAM_DEPTH          ((ZXIC_UINT32)(0x800))
+#define DPP_STAT_1588_PACKET_RX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xA042))
+#define DPP_STAT_1588_PACKET_RX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800))
 
-#define DPP_STAT_1588_PACKET_TX_CNT_ERAM_BAADDR         ((ZXIC_UINT32)(0xA842))
-#define DPP_STAT_1588_PACKET_TX_CNT_ERAM_DEPTH          ((ZXIC_UINT32)(0x800))
+#define DPP_STAT_1588_PACKET_TX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xA842))
+#define DPP_STAT_1588_PACKET_TX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800))
 
-#define DPP_STAT_1588_PACKET_DROP_CNT_ERAM_BAADDR       ((ZXIC_UINT32)(0xB042))
-#define DPP_STAT_1588_PACKET_DROP_CNT_ERAM_DEPTH        ((ZXIC_UINT32)(0x800))
+#define DPP_STAT_1588_PACKET_DROP_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xB042))
+#define DPP_STAT_1588_PACKET_DROP_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800))
 
-#define DPP_STAT_1588_ENC_PACKET_RX_CNT_ERAM_BAADDR     ((ZXIC_UINT32)(0xC042))
-#define DPP_STAT_1588_ENC_PACKET_RX_CNT_ERAM_DEPTH      ((ZXIC_UINT32)(0x800))
+#define DPP_STAT_1588_ENC_PACKET_RX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xC042))
+#define DPP_STAT_1588_ENC_PACKET_RX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800))
 
-#define DPP_STAT_1588_ENC_PACKET_TX_CNT_ERAM_BAADDR     ((ZXIC_UINT32)(0xB842))
-#define DPP_STAT_1588_ENC_PACKET_TX_CNT_ERAM_DEPTH      ((ZXIC_UINT32)(0x800))
+#define DPP_STAT_1588_ENC_PACKET_TX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xB842))
+#define DPP_STAT_1588_ENC_PACKET_TX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800))
 
-#define DPP_STAT_SPOOF_PACKET_DROP_CNT_ERAM_BAADDR      ((ZXIC_UINT32)(0xC842))
-#define DPP_STAT_SPOOF_PACKET_DROP_CNT_ERAM_DEPTH       ((ZXIC_UINT32)(0x40))
+#define DPP_STAT_SPOOF_PACKET_DROP_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xC842))
+#define DPP_STAT_SPOOF_PACKET_DROP_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x40))
 
-#define DPP_STAT_MCODE_PACKET_CNT_ERAM_BAADDR           ((ZXIC_UINT32)(0xC882))
-#define DPP_STAT_MCODE_PACKET_CNT_ERAM_DEPTH            ((ZXIC_UINT32)(0x80))
+#define DPP_STAT_MCODE_PACKET_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xC882))
+#define DPP_STAT_MCODE_PACKET_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x80))
 
-#define DPP_STAT_PORT_BC_PACKET_TX_CNT_ERAM_BAADDR      ((ZXIC_UINT32)(0xC902))
-#define DPP_STAT_PORT_BC_PACKET_TX_CNT_ERAM_DEPTH       ((ZXIC_UINT32)(0x800))
+#define DPP_STAT_PORT_BC_PACKET_TX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xC902))
+#define DPP_STAT_PORT_BC_PACKET_TX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800))
 
-#define DPP_STAT_PORT_BC_PACKET_RX_CNT_ERAM_BAADDR      ((ZXIC_UINT32)(0xD102))
-#define DPP_STAT_PORT_BC_PACKET_RX_CNT_ERAM_DEPTH       ((ZXIC_UINT32)(0x800))
+#define DPP_STAT_PORT_BC_PACKET_RX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0xD102))
+#define DPP_STAT_PORT_BC_PACKET_RX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800))
 
-#define DPP_STAT_PORT_RDMA_PACKET_TX_CNT_ERAM_BAADDR    ((ZXIC_UINT32)(0x6C81)) // 128bit
-#define DPP_STAT_PORT_RDMA_PACKET_TX_CNT_ERAM_DEPTH     ((ZXIC_UINT32)(0x400))
+#define DPP_STAT_PORT_RDMA_PACKET_TX_CNT_ERAM_BAADDR \
+	((ZXIC_UINT32)(0x6C81)) // 128bit
+#define DPP_STAT_PORT_RDMA_PACKET_TX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x400))
 
-#define DPP_STAT_PORT_RDMA_PACKET_RX_CNT_ERAM_BAADDR    ((ZXIC_UINT32)(0x7081)) // 128bit
-#define DPP_STAT_PORT_RDMA_PACKET_RX_CNT_ERAM_DEPTH     ((ZXIC_UINT32)(0x400))
+#define DPP_STAT_PORT_RDMA_PACKET_RX_CNT_ERAM_BAADDR \
+	((ZXIC_UINT32)(0x7081)) // 128bit
+#define DPP_STAT_PORT_RDMA_PACKET_RX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x400))
 
-#define DPP_STAT_PLCR_PACKET_DROP_TX_CNT_ERAM_BAADDR    ((ZXIC_UINT32)(0x7481))
-#define DPP_STAT_PLCR_PACKET_DROP_TX_CNT_ERAM_DEPTH     ((ZXIC_UINT32)(0x800))
+#define DPP_STAT_PLCR_PACKET_DROP_TX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0x7481))
+#define DPP_STAT_PLCR_PACKET_DROP_TX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800))
 
-#define DPP_STAT_PLCR_PACKET_DROP_RX_CNT_ERAM_BAADDR    ((ZXIC_UINT32)(0x7C81))
-#define DPP_STAT_PLCR_PACKET_DROP_RX_CNT_ERAM_DEPTH     ((ZXIC_UINT32)(0x800))
+#define DPP_STAT_PLCR_PACKET_DROP_RX_CNT_ERAM_BAADDR ((ZXIC_UINT32)(0x7C81))
+#define DPP_STAT_PLCR_PACKET_DROP_RX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x800))
 
-#define DPP_STAT_MTU_PACKET_DROP_TX_CNT_ERAM_BAADDR     ((ZXIC_UINT32)(0x8481)) // 128bit
-#define DPP_STAT_MTU_PACKET_DROP_TX_CNT_ERAM_DEPTH      ((ZXIC_UINT32)(0x500))
+#define DPP_STAT_MTU_PACKET_DROP_TX_CNT_ERAM_BAADDR \
+	((ZXIC_UINT32)(0x8481)) // 128bit
+#define DPP_STAT_MTU_PACKET_DROP_TX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x500))
 
-#define DPP_STAT_MTU_PACKET_DROP_RX_CNT_ERAM_BAADDR     ((ZXIC_UINT32)(0x8981)) // 128bit
-#define DPP_STAT_MTU_PACKET_DROP_RX_CNT_ERAM_DEPTH      ((ZXIC_UINT32)(0x500))
+#define DPP_STAT_MTU_PACKET_DROP_RX_CNT_ERAM_BAADDR \
+	((ZXIC_UINT32)(0x8981)) // 128bit
+#define DPP_STAT_MTU_PACKET_DROP_RX_CNT_ERAM_DEPTH ((ZXIC_UINT32)(0x500))
 
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_tm.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_tm.h
index 88b215ad7aa6868afd995f648ba7256d9e87db68..9d114087cd454392fdf1d23ca1cac976e679b7f0 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_tm.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_tm.h
@@ -25,21 +25,37 @@
 #include "dpp_dev.h"
 
 #define TM_BASE_QUEUE_VALID (0x1000)
-#define TRUST_MODE_VALID    (0x10)
-#define UP_VALID            (0x10)
-#define TC_VALID            (0x10)
-#define TM_SWITCH_ON        (1)
-#define TM_SWITCH_OFF        (0)
+#define TRUST_MODE_VALID (0x10)
+#define UP_VALID (0x10)
+#define TC_VALID (0x10)
+#define TM_SWITCH_ON (1)
+#define TM_SWITCH_OFF (0)
 
-ZXIC_UINT32 dpp_tm_flowid_pport_table_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 port, ZXIC_UINT32 flow_id);
-ZXIC_UINT32 dpp_tm_flowid_pport_table_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 port);
-ZXIC_UINT32 dpp_tm_pport_trust_mode_table_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 mode);
-ZXIC_UINT32 dpp_tm_pport_trust_mode_table_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port);
-ZXIC_UINT32 dpp_tm_pport_dscp_map_table_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 dscp_id, ZXIC_UINT32 up_id);
-ZXIC_UINT32 dpp_tm_pport_dscp_map_table_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 dscp_id);
-ZXIC_UINT32 dpp_tm_pport_up_map_table_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 up_id, ZXIC_UINT32 tc_id);
-ZXIC_UINT32 dpp_tm_pport_up_map_table_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32  port, ZXIC_UINT32 up_id);
-ZXIC_UINT32 dpp_tm_pport_mcode_switch_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 mode);
-ZXIC_UINT32 dpp_tm_pport_mcode_switch_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port);
+ZXIC_UINT32 dpp_tm_flowid_pport_table_set(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 port,
+										  ZXIC_UINT32 flow_id);
+ZXIC_UINT32 dpp_tm_flowid_pport_table_del(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 port);
+ZXIC_UINT32 dpp_tm_pport_trust_mode_table_set(DPP_PF_INFO_T *pf_info,
+											  ZXIC_UINT32 port,
+											  ZXIC_UINT32 mode);
+ZXIC_UINT32 dpp_tm_pport_trust_mode_table_del(DPP_PF_INFO_T *pf_info,
+											  ZXIC_UINT32 port);
+ZXIC_UINT32 dpp_tm_pport_dscp_map_table_set(DPP_PF_INFO_T *pf_info,
+											ZXIC_UINT32 port,
+											ZXIC_UINT32 dscp_id,
+											ZXIC_UINT32 up_id);
+ZXIC_UINT32 dpp_tm_pport_dscp_map_table_del(DPP_PF_INFO_T *pf_info,
+											ZXIC_UINT32 port,
+											ZXIC_UINT32 dscp_id);
+ZXIC_UINT32 dpp_tm_pport_up_map_table_set(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 port, ZXIC_UINT32 up_id,
+										  ZXIC_UINT32 tc_id);
+ZXIC_UINT32 dpp_tm_pport_up_map_table_del(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 port, ZXIC_UINT32 up_id);
+ZXIC_UINT32 dpp_tm_pport_mcode_switch_set(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 port, ZXIC_UINT32 mode);
+ZXIC_UINT32 dpp_tm_pport_mcode_switch_del(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 port);
 
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_vlan.h b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_vlan.h
index 22950e162054fd08de3270eeb262c86410ac821a..cee2dc93dcf950f6ab479e5df60a48fe35a6743f 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_vlan.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/include/dpp_tbl_vlan.h
@@ -23,7 +23,7 @@
 #include "zxic_common.h"
 #include "dpp_type_api.h"
 
-#define VLAN_GROUP_NUM        (35)
-#define VLAN_ID_NUM_IN_GROUP  (120)
+#define VLAN_GROUP_NUM (35)
+#define VLAN_ID_NUM_IN_GROUP (120)
 
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_bc.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_bc.c
index d313222d8d02c6f1a38a6015c06f8b6ee0505e4d..1f46c32f7b7f6026dc0c641a46c90940666c1a8c 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_bc.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_bc.c
@@ -12,185 +12,188 @@
 #include "dpp_tbl_comm.h"
 #include "dpp_tbl_bc.h"
 
-ZXIC_UINT32 dpp_vport_bc_info_add(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_vport_bc_info_add(DPP_PF_INFO_T *pf_info)
 {
-    ZXIC_UINT32 group_id  = 0;
-    ZXIC_UINT32 vfunc_num = 0;
-    ZXIC_UINT32 rc        = DPP_OK;
+	ZXIC_UINT32 group_id = 0;
+	ZXIC_UINT32 vfunc_num = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    DPP_VPORT_BC_TABLE_T* bc_table = NULL;
+	DPP_VPORT_BC_TABLE_T *bc_table = NULL;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    rc = dpp_vport_bc_table_get(pf_info, &bc_table);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_get");
-    ZXIC_COMM_CHECK_POINT(bc_table);
+	rc = dpp_vport_bc_table_get(pf_info, &bc_table);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_get");
+	ZXIC_COMM_CHECK_POINT(bc_table);
 
-    vfunc_num = VFUNC_NUM(pf_info->vport);
-    ZXIC_COMM_CHECK_INDEX(vfunc_num, 0, (BC_GROUP_NUM * BC_MEMBER_NUM_IN_GROUP) - 1);
+	vfunc_num = VFUNC_NUM(pf_info->vport);
+	ZXIC_COMM_CHECK_INDEX(vfunc_num, 0,
+						  BC_GROUP_NUM * BC_MEMBER_NUM_IN_GROUP - 1);
 
-    group_id  = vfunc_num / BC_MEMBER_NUM_IN_GROUP;
-    ZXIC_COMM_CHECK_INDEX(group_id, 0, BC_GROUP_NUM - 1);
+	group_id = vfunc_num / BC_MEMBER_NUM_IN_GROUP;
+	ZXIC_COMM_CHECK_INDEX(group_id, 0, BC_GROUP_NUM - 1);
 
-    bc_table->bc_info.bc_bitmap[group_id] |= ((ZXIC_UINT64)(1) << (BC_MEMBER_NUM_IN_GROUP - 1 -
-                                                                  (vfunc_num % BC_MEMBER_NUM_IN_GROUP)));
+	bc_table->bc_info.bc_bitmap[group_id] |=
+			((ZXIC_UINT64)(1) << (BC_MEMBER_NUM_IN_GROUP - 1 -
+								  (vfunc_num % BC_MEMBER_NUM_IN_GROUP)));
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_vport_bc_info_del(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_vport_bc_info_del(DPP_PF_INFO_T *pf_info)
 {
-    ZXIC_UINT32 group_id  = 0;
-    ZXIC_UINT32 vfunc_num = 0;
-    ZXIC_UINT32 rc        = DPP_OK;
+	ZXIC_UINT32 group_id = 0;
+	ZXIC_UINT32 vfunc_num = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    DPP_VPORT_BC_TABLE_T* bc_table = NULL;
+	DPP_VPORT_BC_TABLE_T *bc_table = NULL;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    rc = dpp_vport_bc_table_get(pf_info, &bc_table);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_get");
-    ZXIC_COMM_CHECK_POINT(bc_table);
+	rc = dpp_vport_bc_table_get(pf_info, &bc_table);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_get");
+	ZXIC_COMM_CHECK_POINT(bc_table);
 
-    vfunc_num = VFUNC_NUM(pf_info->vport);
-    ZXIC_COMM_CHECK_INDEX(vfunc_num, 0, (BC_GROUP_NUM * BC_MEMBER_NUM_IN_GROUP) - 1);
+	vfunc_num = VFUNC_NUM(pf_info->vport);
+	ZXIC_COMM_CHECK_INDEX(vfunc_num, 0,
+						  BC_GROUP_NUM * BC_MEMBER_NUM_IN_GROUP - 1);
 
-    group_id  = vfunc_num / BC_MEMBER_NUM_IN_GROUP;
-    ZXIC_COMM_CHECK_INDEX(group_id, 0, BC_GROUP_NUM - 1);
+	group_id = vfunc_num / BC_MEMBER_NUM_IN_GROUP;
+	ZXIC_COMM_CHECK_INDEX(group_id, 0, BC_GROUP_NUM - 1);
 
-    bc_table->bc_info.bc_bitmap[group_id] &= ~((ZXIC_UINT64)(1) << (BC_MEMBER_NUM_IN_GROUP - 1 -
-                                                                   (vfunc_num % BC_MEMBER_NUM_IN_GROUP)));
+	bc_table->bc_info.bc_bitmap[group_id] &=
+			~((ZXIC_UINT64)(1) << (BC_MEMBER_NUM_IN_GROUP - 1 -
+								   (vfunc_num % BC_MEMBER_NUM_IN_GROUP)));
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_vport_bc_info_clear_all(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_vport_bc_info_clear_all(DPP_PF_INFO_T *pf_info)
 {
-    ZXIC_UINT32 group_id = 0;
-    ZXIC_UINT32 rc       = DPP_OK;
+	ZXIC_UINT32 group_id = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    DPP_VPORT_BC_TABLE_T* bc_table = NULL;
+	DPP_VPORT_BC_TABLE_T *bc_table = NULL;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    rc = dpp_vport_bc_table_get(pf_info, &bc_table);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_get");
-    ZXIC_COMM_CHECK_POINT(bc_table);
+	rc = dpp_vport_bc_table_get(pf_info, &bc_table);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_get");
+	ZXIC_COMM_CHECK_POINT(bc_table);
 
-    for (group_id = 0; group_id < BC_GROUP_NUM; group_id++)
-    {
-        bc_table->bc_info.bc_bitmap[group_id] = 0;
-    }
+	for (group_id = 0; group_id < BC_GROUP_NUM; group_id++) {
+		bc_table->bc_info.bc_bitmap[group_id] = 0;
+	}
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_vport_bc_table_insert(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_vport_bc_table_insert(DPP_PF_INFO_T *pf_info)
 {
-    DPP_DEV_T dev = {0};
-
-    ZXIC_UINT32 dev_id   = 0;
-    ZXIC_UINT32 group_id = 0;
-    ZXIC_UINT32 index    = 0;
-    ZXIC_UINT32 sdt_no   = ZXDH_SDT_BC_TABLE;
-    ZXIC_UINT32 queue    = 0;
-    ZXIC_UINT32 rc       = DPP_OK;
-
-    ZXDH_BC_T bc_entry   = {0};
-    DPP_VPORT_BC_TABLE_T *bc_table = NULL;
-
-    ZXIC_COMM_CHECK_POINT(pf_info);
-
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
-
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
-
-    rc = dpp_vport_bc_table_get(pf_info, &bc_table);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_get");
-    ZXIC_COMM_CHECK_POINT(bc_table);
-
-    for (group_id = 0; group_id < BC_GROUP_NUM; group_id++)
-    {
-        index = (((OWNER_PF_VQM_VFID(pf_info->vport) - PF_VQM_VFID_OFFSET) << 2)| group_id);
-        bc_entry.hit_flag = 1;
-        bc_entry.bc_bitmap = bc_table->bc_info.bc_bitmap[group_id];
-
-        rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &bc_entry);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
-
-        ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u group_id: %u index: 0x%02x.\n", __FUNCTION__,
-                                                     pf_info->slot, pf_info->vport, sdt_no, group_id, index);
-        ZXIC_COMM_PRINT("[%s] bc_bitmap: %02x %02x %02x %02x %02x %02x %02x %02x.\n", __FUNCTION__,
-                                                                  *((ZXIC_UINT8*)(&bc_entry.bc_bitmap) + 7),
-                                                                  *((ZXIC_UINT8*)(&bc_entry.bc_bitmap) + 6),
-                                                                  *((ZXIC_UINT8*)(&bc_entry.bc_bitmap) + 5),
-                                                                  *((ZXIC_UINT8*)(&bc_entry.bc_bitmap) + 4),
-                                                                  *((ZXIC_UINT8*)(&bc_entry.bc_bitmap) + 3),
-                                                                  *((ZXIC_UINT8*)(&bc_entry.bc_bitmap) + 2),
-                                                                  *((ZXIC_UINT8*)(&bc_entry.bc_bitmap) + 1),
-                                                                  *((ZXIC_UINT8*)(&bc_entry.bc_bitmap) + 0));
-    }
-
-    return DPP_OK;
+	DPP_DEV_T dev = { 0 };
+
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 group_id = 0;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_BC_TABLE;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	ZXDH_BC_T bc_entry = { 0 };
+	DPP_VPORT_BC_TABLE_T *bc_table = NULL;
+
+	ZXIC_COMM_CHECK_POINT(pf_info);
+
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+
+	rc = dpp_vport_bc_table_get(pf_info, &bc_table);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_get");
+	ZXIC_COMM_CHECK_POINT(bc_table);
+
+	for (group_id = 0; group_id < BC_GROUP_NUM; group_id++) {
+		index = (((OWNER_PF_VQM_VFID(pf_info->vport) - PF_VQM_VFID_OFFSET)
+				  << 2) |
+				 group_id);
+		bc_entry.hit_flag = 1;
+		bc_entry.bc_bitmap = bc_table->bc_info.bc_bitmap[group_id];
+
+		rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &bc_entry);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
+
+		ZXIC_COMM_PRINT(
+				"[%s] slot: %u vport: 0x%04x sdt_no: %u group_id: %u index: 0x%02x.\n",
+				__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, group_id,
+				index);
+		ZXIC_COMM_PRINT(
+				"[%s] bc_bitmap: %02x %02x %02x %02x %02x %02x %02x %02x.\n",
+				__FUNCTION__, *((ZXIC_UINT8 *)(&bc_entry.bc_bitmap) + 7),
+				*((ZXIC_UINT8 *)(&bc_entry.bc_bitmap) + 6),
+				*((ZXIC_UINT8 *)(&bc_entry.bc_bitmap) + 5),
+				*((ZXIC_UINT8 *)(&bc_entry.bc_bitmap) + 4),
+				*((ZXIC_UINT8 *)(&bc_entry.bc_bitmap) + 3),
+				*((ZXIC_UINT8 *)(&bc_entry.bc_bitmap) + 2),
+				*((ZXIC_UINT8 *)(&bc_entry.bc_bitmap) + 1),
+				*((ZXIC_UINT8 *)(&bc_entry.bc_bitmap) + 0));
+	}
+
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_vport_bond_pf(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_vport_bond_pf(DPP_PF_INFO_T *pf_info)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
-                                                            pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    if (IS_PF(pf_info->vport))
-    {
-        rc = dpp_vport_bc_info_clear_all(pf_info);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_info_clear_all");
-    }
-    else
-    {
-        rc = dpp_vport_bc_info_add(pf_info);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_info_add");
-    }
+	if (IS_PF(pf_info->vport)) {
+		rc = dpp_vport_bc_info_clear_all(pf_info);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_info_clear_all");
+	} else {
+		rc = dpp_vport_bc_info_add(pf_info);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_info_add");
+	}
 
-    rc = dpp_vport_bc_table_insert(pf_info);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_insert");
+	rc = dpp_vport_bc_table_insert(pf_info);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
-                                                            pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_bond_pf);
 
-ZXIC_UINT32 dpp_vport_unbond_pf(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_vport_unbond_pf(DPP_PF_INFO_T *pf_info)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
-                                                            pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    if (IS_PF(pf_info->vport))
-    {
-        ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x is pf, no vf to del.\n", __FUNCTION__,
-                                                            pf_info->slot, pf_info->vport);
-        return DPP_ERR;
-    }
+	if (IS_PF(pf_info->vport)) {
+		ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x is pf, no vf to del.\n",
+						__FUNCTION__, pf_info->slot, pf_info->vport);
+		return DPP_ERR;
+	}
 
-    rc = dpp_vport_bc_info_del(pf_info);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_info_del");
+	rc = dpp_vport_bc_info_del(pf_info);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_info_del");
 
-    rc = dpp_vport_bc_table_insert(pf_info);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_insert");
+	rc = dpp_vport_bc_table_insert(pf_info);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bc_table_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
-                                                            pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_unbond_pf);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_comm.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_comm.c
index cc7cf330b1ca2096ca9e00683f549c9a456a5a7c..59c88743641cd3daf17c760b1a5049c61e4a0c7f 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_comm.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_comm.c
@@ -14,273 +14,293 @@
 #include "dpp_tbl_comm.h"
 #include "dpp_tbl_api.h"
 
-static DPP_VPORT_MGR_T g_vport_mgr[DPP_PCIE_SLOT_MAX][DPP_PCIE_CHANNEL_MAX] = {0};
+static DPP_VPORT_MGR_T g_vport_mgr[DPP_PCIE_SLOT_MAX][DPP_PCIE_CHANNEL_MAX] = {
+	0
+};
 
 ZXIC_UINT32 dpp_data_print(ZXIC_UINT8 *data, ZXIC_UINT32 len)
 {
-    ZXIC_UINT32 i             = 0;
-    ZXIC_UINT32 loop_cnt      = len / 16;
-    ZXIC_UINT32 last_line_len = len % 16;
-
-    ZXIC_COMM_PRINT("-----------------------------------------------\n");
-    for (i = 0; i < loop_cnt; i++)
-    {
-        ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
-               *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3),
-               *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7),
-               *(data + (i * 16) + 8), *(data + (i * 16) + 9), *(data + (i * 16) + 10), *(data + (i * 16) + 11),
-               *(data + (i * 16) + 12), *(data + (i * 16) + 13), *(data + (i * 16) + 14), *(data + (i * 16) + 15));
-    }
-    if (last_line_len != 0)
-    {
-        if (last_line_len == 1)
-        {
-            ZXIC_COMM_PRINT("%02x\n", *(data + (i * 16) + 0));
-        }
-        else if (last_line_len == 2)
-        {
-            ZXIC_COMM_PRINT("%02x %02x\n", *(data + (i * 16) + 0), *(data + (i * 16) + 1));
-        }
-        else if (last_line_len == 3)
-        {
-            ZXIC_COMM_PRINT("%02x %02x %02x\n", *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2));
-        }
-        else if (last_line_len == 4)
-        {
-            ZXIC_COMM_PRINT("%02x %02x %02x %02x\n",
-                    *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3));
-        }
-        else if (last_line_len == 5)
-        {
-            ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x\n",
-                    *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3),
-                    *(data + (i * 16) + 4));
-        }
-        else if (last_line_len == 6)
-        {
-            ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x\n",
-                    *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3),
-                    *(data + (i * 16) + 4), *(data + (i * 16) + 5));
-        }
-        else if (last_line_len == 7)
-        {
-            ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x\n",
-                    *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3),
-                    *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6));
-        }
-        else if (last_line_len == 8)
-        {
-            ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x\n",
-                    *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3),
-                    *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7));
-        }
-        else if (last_line_len == 9)
-        {
-            ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
-                    *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3),
-                    *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7),
-                    *(data + (i * 16) + 8));
-        }
-        else if (last_line_len == 10)
-        {
-            ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
-                    *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3),
-                    *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7),
-                    *(data + (i * 16) + 8), *(data + (i * 16) + 9));
-        }
-        else if (last_line_len == 11)
-        {
-            ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
-                    *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3),
-                    *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7),
-                    *(data + (i * 16) + 8), *(data + (i * 16) + 9), *(data + (i * 16) + 10));
-        }
-        else if (last_line_len == 12)
-        {
-            ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
-                    *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3),
-                    *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7),
-                    *(data + (i * 16) + 8), *(data + (i * 16) + 9), *(data + (i * 16) + 10), *(data + (i * 16) + 11));
-        }
-        else if (last_line_len == 13)
-        {
-            ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
-                    *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3),
-                    *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7),
-                    *(data + (i * 16) + 8), *(data + (i * 16) + 9), *(data + (i * 16) + 10), *(data + (i * 16) + 11),
-                    *(data + (i * 16) + 12));
-        }
-        else if (last_line_len == 14)
-        {
-            ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
-                    *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3),
-                    *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7),
-                    *(data + (i * 16) + 8), *(data + (i * 16) + 9), *(data + (i * 16) + 10), *(data + (i * 16) + 11),
-                    *(data + (i * 16) + 12), *(data + (i * 16) + 13));
-        }
-        else if (last_line_len == 15)
-        {
-            ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
-                    *(data + (i * 16) + 0), *(data + (i * 16) + 1), *(data + (i * 16) + 2), *(data + (i * 16) + 3),
-                    *(data + (i * 16) + 4), *(data + (i * 16) + 5), *(data + (i * 16) + 6), *(data + (i * 16) + 7),
-                    *(data + (i * 16) + 8), *(data + (i * 16) + 9), *(data + (i * 16) + 10), *(data + (i * 16) + 11),
-                    *(data + (i * 16) + 12), *(data + (i * 16) + 13), *(data + (i * 16) + 14));
-        }
-    }
-    ZXIC_COMM_PRINT("-----------------------------------------------\n");
-
-    return DPP_OK;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 loop_cnt = len / 16;
+	ZXIC_UINT32 last_line_len = len % 16;
+
+	ZXIC_COMM_PRINT("-----------------------------------------------\n");
+	for (i = 0; i < loop_cnt; i++) {
+		ZXIC_COMM_PRINT(
+				"%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
+				*(data + (i * 16) + 0), *(data + (i * 16) + 1),
+				*(data + (i * 16) + 2), *(data + (i * 16) + 3),
+				*(data + (i * 16) + 4), *(data + (i * 16) + 5),
+				*(data + (i * 16) + 6), *(data + (i * 16) + 7),
+				*(data + (i * 16) + 8), *(data + (i * 16) + 9),
+				*(data + (i * 16) + 10), *(data + (i * 16) + 11),
+				*(data + (i * 16) + 12), *(data + (i * 16) + 13),
+				*(data + (i * 16) + 14), *(data + (i * 16) + 15));
+	}
+	if (last_line_len != 0) {
+		if (last_line_len == 1) {
+			ZXIC_COMM_PRINT("%02x\n", *(data + (i * 16) + 0));
+		} else if (last_line_len == 2) {
+			ZXIC_COMM_PRINT("%02x %02x\n", *(data + (i * 16) + 0),
+							*(data + (i * 16) + 1));
+		} else if (last_line_len == 3) {
+			ZXIC_COMM_PRINT("%02x %02x %02x\n", *(data + (i * 16) + 0),
+							*(data + (i * 16) + 1), *(data + (i * 16) + 2));
+		} else if (last_line_len == 4) {
+			ZXIC_COMM_PRINT("%02x %02x %02x %02x\n", *(data + (i * 16) + 0),
+							*(data + (i * 16) + 1), *(data + (i * 16) + 2),
+							*(data + (i * 16) + 3));
+		} else if (last_line_len == 5) {
+			ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x\n",
+							*(data + (i * 16) + 0), *(data + (i * 16) + 1),
+							*(data + (i * 16) + 2), *(data + (i * 16) + 3),
+							*(data + (i * 16) + 4));
+		} else if (last_line_len == 6) {
+			ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x\n",
+							*(data + (i * 16) + 0), *(data + (i * 16) + 1),
+							*(data + (i * 16) + 2), *(data + (i * 16) + 3),
+							*(data + (i * 16) + 4), *(data + (i * 16) + 5));
+		} else if (last_line_len == 7) {
+			ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x\n",
+							*(data + (i * 16) + 0), *(data + (i * 16) + 1),
+							*(data + (i * 16) + 2), *(data + (i * 16) + 3),
+							*(data + (i * 16) + 4), *(data + (i * 16) + 5),
+							*(data + (i * 16) + 6));
+		} else if (last_line_len == 8) {
+			ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x\n",
+							*(data + (i * 16) + 0), *(data + (i * 16) + 1),
+							*(data + (i * 16) + 2), *(data + (i * 16) + 3),
+							*(data + (i * 16) + 4), *(data + (i * 16) + 5),
+							*(data + (i * 16) + 6), *(data + (i * 16) + 7));
+		} else if (last_line_len == 9) {
+			ZXIC_COMM_PRINT("%02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
+							*(data + (i * 16) + 0), *(data + (i * 16) + 1),
+							*(data + (i * 16) + 2), *(data + (i * 16) + 3),
+							*(data + (i * 16) + 4), *(data + (i * 16) + 5),
+							*(data + (i * 16) + 6), *(data + (i * 16) + 7),
+							*(data + (i * 16) + 8));
+		} else if (last_line_len == 10) {
+			ZXIC_COMM_PRINT(
+					"%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
+					*(data + (i * 16) + 0), *(data + (i * 16) + 1),
+					*(data + (i * 16) + 2), *(data + (i * 16) + 3),
+					*(data + (i * 16) + 4), *(data + (i * 16) + 5),
+					*(data + (i * 16) + 6), *(data + (i * 16) + 7),
+					*(data + (i * 16) + 8), *(data + (i * 16) + 9));
+		} else if (last_line_len == 11) {
+			ZXIC_COMM_PRINT(
+					"%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
+					*(data + (i * 16) + 0), *(data + (i * 16) + 1),
+					*(data + (i * 16) + 2), *(data + (i * 16) + 3),
+					*(data + (i * 16) + 4), *(data + (i * 16) + 5),
+					*(data + (i * 16) + 6), *(data + (i * 16) + 7),
+					*(data + (i * 16) + 8), *(data + (i * 16) + 9),
+					*(data + (i * 16) + 10));
+		} else if (last_line_len == 12) {
+			ZXIC_COMM_PRINT(
+					"%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
+					*(data + (i * 16) + 0), *(data + (i * 16) + 1),
+					*(data + (i * 16) + 2), *(data + (i * 16) + 3),
+					*(data + (i * 16) + 4), *(data + (i * 16) + 5),
+					*(data + (i * 16) + 6), *(data + (i * 16) + 7),
+					*(data + (i * 16) + 8), *(data + (i * 16) + 9),
+					*(data + (i * 16) + 10), *(data + (i * 16) + 11));
+		} else if (last_line_len == 13) {
+			ZXIC_COMM_PRINT(
+					"%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
+					*(data + (i * 16) + 0), *(data + (i * 16) + 1),
+					*(data + (i * 16) + 2), *(data + (i * 16) + 3),
+					*(data + (i * 16) + 4), *(data + (i * 16) + 5),
+					*(data + (i * 16) + 6), *(data + (i * 16) + 7),
+					*(data + (i * 16) + 8), *(data + (i * 16) + 9),
+					*(data + (i * 16) + 10), *(data + (i * 16) + 11),
+					*(data + (i * 16) + 12));
+		} else if (last_line_len == 14) {
+			ZXIC_COMM_PRINT(
+					"%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
+					*(data + (i * 16) + 0), *(data + (i * 16) + 1),
+					*(data + (i * 16) + 2), *(data + (i * 16) + 3),
+					*(data + (i * 16) + 4), *(data + (i * 16) + 5),
+					*(data + (i * 16) + 6), *(data + (i * 16) + 7),
+					*(data + (i * 16) + 8), *(data + (i * 16) + 9),
+					*(data + (i * 16) + 10), *(data + (i * 16) + 11),
+					*(data + (i * 16) + 12), *(data + (i * 16) + 13));
+		} else if (last_line_len == 15) {
+			ZXIC_COMM_PRINT(
+					"%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
+					*(data + (i * 16) + 0), *(data + (i * 16) + 1),
+					*(data + (i * 16) + 2), *(data + (i * 16) + 3),
+					*(data + (i * 16) + 4), *(data + (i * 16) + 5),
+					*(data + (i * 16) + 6), *(data + (i * 16) + 7),
+					*(data + (i * 16) + 8), *(data + (i * 16) + 9),
+					*(data + (i * 16) + 10), *(data + (i * 16) + 11),
+					*(data + (i * 16) + 12), *(data + (i * 16) + 13),
+					*(data + (i * 16) + 14));
+		}
+	}
+	ZXIC_COMM_PRINT("-----------------------------------------------\n");
+
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_vport_mgr_init(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_vport_mgr_init(DPP_PF_INFO_T *pf_info)
 {
-    ZXIC_UINT16 slot = 0;
-    ZXIC_UINT16 channel_id = 0;
+	ZXIC_UINT16 slot = 0;
+	ZXIC_UINT16 channel_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    slot = pf_info->slot;
-    ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1);
+	slot = pf_info->slot;
+	ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1);
 
-    channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
-    ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
+	channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
+	ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
 
-    ZXIC_COMM_MEMSET(&g_vport_mgr[slot][channel_id], 0x00, sizeof(DPP_VPORT_MGR_T));
+	ZXIC_COMM_MEMSET(&g_vport_mgr[slot][channel_id], 0x00,
+					 sizeof(DPP_VPORT_MGR_T));
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_vport_mgr_release(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_vport_mgr_release(DPP_PF_INFO_T *pf_info)
 {
-    ZXIC_UINT16 slot = 0;
-    ZXIC_UINT16 channel_id = 0;
+	ZXIC_UINT16 slot = 0;
+	ZXIC_UINT16 channel_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    slot = pf_info->slot;
-    ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1);
+	slot = pf_info->slot;
+	ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1);
 
-    channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
-    ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
+	channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
+	ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
 
-    ZXIC_COMM_MEMSET(&g_vport_mgr[slot][channel_id], 0x00, sizeof(DPP_VPORT_MGR_T));
+	ZXIC_COMM_MEMSET(&g_vport_mgr[slot][channel_id], 0x00,
+					 sizeof(DPP_VPORT_MGR_T));
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_vport_bc_table_get(DPP_PF_INFO_T* pf_info, DPP_VPORT_BC_TABLE_T** bc_table)
+ZXIC_UINT32 dpp_vport_bc_table_get(DPP_PF_INFO_T *pf_info,
+								   DPP_VPORT_BC_TABLE_T **bc_table)
 {
-    ZXIC_UINT16 slot = 0;
-    ZXIC_UINT16 channel_id = 0;
+	ZXIC_UINT16 slot = 0;
+	ZXIC_UINT16 channel_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(bc_table);
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(bc_table);
 
-    slot = pf_info->slot;
-    ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1);
+	slot = pf_info->slot;
+	ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1);
 
-    channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
-    ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
+	channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
+	ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
 
-    *bc_table = &g_vport_mgr[slot][channel_id].bc_table;
+	*bc_table = &g_vport_mgr[slot][channel_id].bc_table;
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_vport_mc_table_get(DPP_PF_INFO_T* pf_info, DPP_VPORT_MC_TABLE_T** mc_table)
+ZXIC_UINT32 dpp_vport_mc_table_get(DPP_PF_INFO_T *pf_info,
+								   DPP_VPORT_MC_TABLE_T **mc_table)
 {
-    ZXIC_UINT16 slot = 0;
-    ZXIC_UINT16 channel_id = 0;
+	ZXIC_UINT16 slot = 0;
+	ZXIC_UINT16 channel_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(mc_table);
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(mc_table);
 
-    slot = pf_info->slot;
-    ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1);
+	slot = pf_info->slot;
+	ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1);
 
-    channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
-    ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
+	channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
+	ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
 
-    *mc_table = &g_vport_mgr[slot][channel_id].mc_table;
+	*mc_table = &g_vport_mgr[slot][channel_id].mc_table;
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_vport_uc_promisc_table_get(DPP_PF_INFO_T* pf_info, DPP_VPORT_PROMISC_TABLE_T** promisc_table)
+ZXIC_UINT32
+dpp_vport_uc_promisc_table_get(DPP_PF_INFO_T *pf_info,
+							   DPP_VPORT_PROMISC_TABLE_T **promisc_table)
 {
-    ZXIC_UINT16 slot = 0;
-    ZXIC_UINT16 channel_id = 0;
+	ZXIC_UINT16 slot = 0;
+	ZXIC_UINT16 channel_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(promisc_table);
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(promisc_table);
 
-    slot = pf_info->slot;
-    ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1);
+	slot = pf_info->slot;
+	ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1);
 
-    channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
-    ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
+	channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
+	ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
 
-    *promisc_table = &g_vport_mgr[slot][channel_id].uc_promisc_table;
+	*promisc_table = &g_vport_mgr[slot][channel_id].uc_promisc_table;
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_vport_mc_promisc_table_get(DPP_PF_INFO_T* pf_info, DPP_VPORT_PROMISC_TABLE_T** promisc_table)
+ZXIC_UINT32
+dpp_vport_mc_promisc_table_get(DPP_PF_INFO_T *pf_info,
+							   DPP_VPORT_PROMISC_TABLE_T **promisc_table)
 {
-    ZXIC_UINT16 slot = 0;
-    ZXIC_UINT16 channel_id = 0;
+	ZXIC_UINT16 slot = 0;
+	ZXIC_UINT16 channel_id = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(promisc_table);
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(promisc_table);
 
-    slot = pf_info->slot;
-    ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1);
+	slot = pf_info->slot;
+	ZXIC_COMM_CHECK_INDEX(slot, 0, DPP_PCIE_SLOT_MAX - 1);
 
-    channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
-    ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
+	channel_id = DPP_PCIE_CHANNEL_ID(pf_info->vport);
+	ZXIC_COMM_CHECK_INDEX(channel_id, 0, DPP_PCIE_CHANNEL_MAX - 1);
 
-    *promisc_table = &g_vport_mgr[slot][channel_id].mc_promisc_table;
+	*promisc_table = &g_vport_mgr[slot][channel_id].mc_promisc_table;
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_vport_get_by_vqm_vfid(ZXIC_UINT16 pf_vport, ZXIC_UINT32 vqm_vfid, ZXIC_UINT16* vport)
+ZXIC_UINT32 dpp_vport_get_by_vqm_vfid(ZXIC_UINT16 pf_vport,
+									  ZXIC_UINT32 vqm_vfid, ZXIC_UINT16 *vport)
 {
-    ZXIC_COMM_CHECK_POINT(vport);
-
-    if (vqm_vfid >= PF_VQM_VFID_OFFSET)
-    {
-        *vport = pf_vport;
-    }
-    else
-    {
-        *vport = ((EPID(pf_vport) << 12) | 0x800 | (FUNC_NUM(pf_vport) << 8) | (vqm_vfid - (EPID(pf_vport) * 256)));
-    }
-    return DPP_OK;
+	ZXIC_COMM_CHECK_POINT(vport);
+
+	if (vqm_vfid >= PF_VQM_VFID_OFFSET) {
+		*vport = pf_vport;
+	} else {
+		*vport = ((EPID(pf_vport) << 12) | 0x800 | (FUNC_NUM(pf_vport) << 8) |
+				  (vqm_vfid - EPID(pf_vport) * 256));
+	}
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_vport_get_by_mc_bitmap(ZXIC_UINT16 pf_vport, ZXIC_UINT32 group_id, ZXIC_UINT64 mc_bitmap,
-                                                         ZXIC_UINT16 vport[64], ZXIC_UINT32* p_vport_num)
+ZXIC_UINT32 dpp_vport_get_by_mc_bitmap(ZXIC_UINT16 pf_vport,
+									   ZXIC_UINT32 group_id,
+									   ZXIC_UINT64 mc_bitmap,
+									   ZXIC_UINT16 vport[64],
+									   ZXIC_UINT32 *p_vport_num)
 {
-    ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 i = 0;
 
-    ZXIC_UINT32 vport_num = 0;
+	ZXIC_UINT32 vport_num = 0;
 
-    ZXIC_COMM_CHECK_POINT(vport);
-    ZXIC_COMM_CHECK_POINT(p_vport_num);
+	ZXIC_COMM_CHECK_POINT(vport);
+	ZXIC_COMM_CHECK_POINT(p_vport_num);
 
-    for (i = 0; i < MC_MEMBER_NUM_IN_GROUP; i++)
-    {
-        if ((mc_bitmap >> i) & 1)
-        {
-            vport[vport_num] = ((EPID(pf_vport) << 12) | 0x800 | (FUNC_NUM(pf_vport) << 8) |
-                                ((group_id * MC_MEMBER_NUM_IN_GROUP) + MC_MEMBER_NUM_IN_GROUP - 1 - i));
-            vport_num ++;
-        }
-    }
+	for (i = 0; i < MC_MEMBER_NUM_IN_GROUP; i++) {
+		if ((mc_bitmap >> i) & 1) {
+			vport[vport_num] = ((EPID(pf_vport) << 12) | 0x800 |
+								(FUNC_NUM(pf_vport) << 8) |
+								(group_id * MC_MEMBER_NUM_IN_GROUP +
+								 MC_MEMBER_NUM_IN_GROUP - 1 - i));
+			vport_num++;
+		}
+	}
 
-    *p_vport_num = vport_num;
+	*p_vport_num = vport_num;
 
-    return DPP_OK;
+	return DPP_OK;
 }
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_diag.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_diag.c
index e1cdbd36d39ee89276bd2f75a34866c1a37a02bd..b77d517bc3fd3df7e19f4371d1d6a37852251d4a 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_diag.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_diag.c
@@ -3,464 +3,573 @@
 #include "dpp_dtb.h"
 #include "dpp_drv_sdt.h"
 
-ZXIC_CONST ZXIC_CHAR* g_vport_table_attr_name[] = {
-    "tpid","vhca","uplink_port","rss_hash_factor","hash_alg","panel_id","lag_id","pf_vqm_vfid","rsv3",
-    "mtu","port_base_qid","hash_search_index","rsv1","tm_enable","ingress_meter_enable","egress_meter_enable",
-    "ingress_meter_mode","egress_meter_mode","fd_enable","vepa_enable","spoof_check_enable","inline_sec_offload",
-    "ovs_enable","lag_enable","is_passthrough","is_vf","virtion_version","virtio_enable","accelerator_offload_flag",
-    "lro_offload","ip_fragment_offload","tcp_udp_checksum_offload","ip_checksum_offload","outer_ip_checksum_offload",
-    "is_up","allmulticast_enable","hw_bond_enable","rdma_offload_enable","vlan_filter_enable","vlan_strip_offload",
-    "qinq_vlan_strip_offload","rss_enable","mtu_offload_enable","hit_flag"
+ZXIC_CHAR *g_vport_table_attr_name[] = { "tpid",
+										 "vhca",
+										 "uplink_port",
+										 "rss_hash_factor",
+										 "hash_alg",
+										 "panel_id",
+										 "lag_id",
+										 "pf_vqm_vfid",
+										 "rsv3",
+										 "mtu",
+										 "port_base_qid",
+										 "hash_search_index",
+										 "rsv1",
+										 "tm_enable",
+										 "ingress_meter_enable",
+										 "egress_meter_enable",
+										 "ingress_meter_mode",
+										 "egress_meter_mode",
+										 "fd_enable",
+										 "vepa_enable",
+										 "spoof_check_enable",
+										 "inline_sec_offload",
+										 "ovs_enable",
+										 "lag_enable",
+										 "is_passthrough",
+										 "is_vf",
+										 "virtion_version",
+										 "virtio_enable",
+										 "accelerator_offload_flag",
+										 "lro_offload",
+										 "ip_fragment_offload",
+										 "tcp_udp_checksum_offload",
+										 "ip_checksum_offload",
+										 "outer_ip_checksum_offload",
+										 "is_up",
+										 "allmulticast_enable",
+										 "hw_bond_enable",
+										 "rdma_offload_enable",
+										 "vlan_filter_enable",
+										 "vlan_strip_offload",
+										 "qinq_vlan_strip_offload",
+										 "rss_enable",
+										 "mtu_offload_enable",
+										 "hit_flag" };
+
+ZXIC_CHAR *g_vport_panel_table_attr_name[] = {
+	"rsv7",			"ovs_pf_vfid",		"rsv6",			 "pf_memport_qid",
+	"rsv5",			"bond_pf_vqm_vfid", "rsv4",			 "is_up",
+	"bond_link_up", "hw_bond_enable",	"mtu",			 "mtu_offload_enable",
+	"rsv3",			"tm_base_queue",	"ptp_port_vfid", "rsv2",
+	"pf_vqm_vfid",	"tm_shape_enable",	"ptp_tc_enable", "trust_mode",
+	"hit_flag"
 };
 
-ZXIC_CONST ZXIC_CHAR* g_vport_panel_table_attr_name[] = {
-    "rsv7","ovs_pf_vfid","rsv6","pf_memport_qid","rsv5","bond_pf_vqm_vfid","rsv4","is_up","bond_link_up","hw_bond_enable",
-    "mtu","mtu_offload_enable","rsv3","tm_base_queue","ptp_port_vfid","rsv2","pf_vqm_vfid","tm_shape_enable","ptp_tc_enable",
-    "trust_mode","hit_flag"
-};
-
-ZXIC_CONST ZXIC_CHAR* dpp_vport_table_attr_name_get(ZXIC_UINT32 attr)
+ZXIC_CHAR *dpp_vport_table_attr_name_get(ZXIC_UINT32 attr)
 {
-    if (attr >= (sizeof(ZXDH_VPORT_T) / sizeof(ZXIC_UINT32)))
-    {
-        return NULL;
-    }
+	if (attr >= (sizeof(ZXDH_VPORT_T) / sizeof(ZXIC_UINT32))) {
+		return "null";
+	}
 
-    return g_vport_table_attr_name[attr];
+	return g_vport_table_attr_name[attr];
 }
 
-ZXIC_CONST ZXIC_CHAR* dpp_vport_panel_table_attr_name_get(ZXIC_UINT32 attr)
+ZXIC_CHAR *dpp_vport_panel_table_attr_name_get(ZXIC_UINT32 attr)
 {
-    if (attr >= (sizeof(ZXDH_PANEL_PORT_T) / sizeof(ZXIC_UINT32)))
-    {
-        return NULL;
-    }
+	if (attr >= (sizeof(ZXDH_PANEL_PORT_T) / sizeof(ZXIC_UINT32))) {
+		return "null";
+	}
 
-    return g_vport_panel_table_attr_name[attr];
+	return g_vport_panel_table_attr_name[attr];
 }
 
 ZXIC_UINT32 diag_dpp_vport_mac_add(ZXIC_UINT16 slot, ZXIC_UINT16 vport,
-                                   ZXIC_UINT8 mac0, ZXIC_UINT8 mac1, ZXIC_UINT8 mac2,
-                                   ZXIC_UINT8 mac3, ZXIC_UINT8 mac4, ZXIC_UINT8 mac5)
+								   ZXIC_UINT8 mac0, ZXIC_UINT8 mac1,
+								   ZXIC_UINT8 mac2, ZXIC_UINT8 mac3,
+								   ZXIC_UINT8 mac4, ZXIC_UINT8 mac5)
 {
-    DPP_PF_INFO_T pf_info = {slot, vport};
+	DPP_PF_INFO_T pf_info = { slot, vport };
 
-    ZXIC_UINT8  mac[6];
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT8 mac[6];
+	ZXIC_UINT32 rc = DPP_OK;
 
-    mac[0] = mac0;
-    mac[1] = mac1;
-    mac[2] = mac2;
-    mac[3] = mac3;
-    mac[4] = mac4;
-    mac[5] = mac5;
+	mac[0] = mac0;
+	mac[1] = mac1;
+	mac[2] = mac2;
+	mac[3] = mac3;
+	mac[4] = mac4;
+	mac[5] = mac5;
 
-    rc = dpp_add_mac(&pf_info, mac);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_add_mac");
+	rc = dpp_add_mac(&pf_info, mac);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_add_mac");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 diag_dpp_vport_mac_del(ZXIC_UINT16 slot, ZXIC_UINT16 vport,
-                                   ZXIC_UINT8 mac0, ZXIC_UINT8 mac1, ZXIC_UINT8 mac2,
-                                   ZXIC_UINT8 mac3, ZXIC_UINT8 mac4, ZXIC_UINT8 mac5)
+								   ZXIC_UINT8 mac0, ZXIC_UINT8 mac1,
+								   ZXIC_UINT8 mac2, ZXIC_UINT8 mac3,
+								   ZXIC_UINT8 mac4, ZXIC_UINT8 mac5)
 {
-    DPP_PF_INFO_T pf_info = {slot, vport};
+	DPP_PF_INFO_T pf_info = { slot, vport };
 
-    ZXIC_UINT8  mac[6];
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT8 mac[6];
+	ZXIC_UINT32 rc = DPP_OK;
 
-    mac[0] = mac0;
-    mac[1] = mac1;
-    mac[2] = mac2;
-    mac[3] = mac3;
-    mac[4] = mac4;
-    mac[5] = mac5;
+	mac[0] = mac0;
+	mac[1] = mac1;
+	mac[2] = mac2;
+	mac[3] = mac3;
+	mac[4] = mac4;
+	mac[5] = mac5;
 
-    rc = dpp_del_mac(&pf_info, mac);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_del_mac");
+	rc = dpp_del_mac(&pf_info, mac);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_del_mac");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 diag_dpp_vport_mac_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport)
 {
-    ZXIC_UINT32 mac_num = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 mac_num = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    DPP_PF_INFO_T pf_info = {slot, vport};
+	DPP_PF_INFO_T pf_info = { slot, vport };
 
-    MAC_VPORT_INFO *p_mac_arr = (MAC_VPORT_INFO *)ZXIC_COMM_MALLOC(DTB_DUMP_UNICAST_MAC_DUMP_NUM *
-                                                                          sizeof(MAC_VPORT_INFO));
-    ZXIC_COMM_CHECK_POINT(p_mac_arr);
+	MAC_VPORT_INFO *p_mac_arr = (MAC_VPORT_INFO *)ZXIC_COMM_MALLOC(
+			DTB_DUMP_UNICAST_MAC_DUMP_NUM * sizeof(MAC_VPORT_INFO));
+	ZXIC_COMM_CHECK_POINT(p_mac_arr);
 
-    rc = dpp_unicast_mac_dump(&pf_info, p_mac_arr, &mac_num);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE(rc, "dpp_unicast_mac_dump", p_mac_arr);
+	rc = dpp_unicast_mac_dump(&pf_info, p_mac_arr, &mac_num);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE(rc, "dpp_unicast_mac_dump", p_mac_arr);
 
-    ZXIC_COMM_PRINT("-----------------------------------------------\n");
-    for (i = 0; i < mac_num; i++)
-    {
-        ZXIC_COMM_PRINT("slot: %u vport: 0x%04x mac: %02x:%02x:%02x:%02x:%02x:%02x\n",
-                                                          slot, p_mac_arr[i].vport,
-                                                          p_mac_arr[i].addr[0], p_mac_arr[i].addr[1],
-                                                          p_mac_arr[i].addr[2], p_mac_arr[i].addr[3],
-                                                          p_mac_arr[i].addr[4], p_mac_arr[i].addr[5]);
-    }
-    ZXIC_COMM_PRINT("-----------------------------------------------\n");
+	ZXIC_COMM_PRINT("-----------------------------------------------\n");
+	for (i = 0; i < mac_num; i++) {
+		ZXIC_COMM_PRINT(
+				"slot: %u vport: 0x%04x mac: %02x:%02x:%02x:%02x:%02x:%02x\n",
+				slot, p_mac_arr[i].vport, p_mac_arr[i].addr[0],
+				p_mac_arr[i].addr[1], p_mac_arr[i].addr[2],
+				p_mac_arr[i].addr[3], p_mac_arr[i].addr[4],
+				p_mac_arr[i].addr[5]);
+	}
+	ZXIC_COMM_PRINT("-----------------------------------------------\n");
 
-    ZXIC_COMM_FREE(p_mac_arr);
+	ZXIC_COMM_FREE(p_mac_arr);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 diag_dpp_vport_mc_mac_add(ZXIC_UINT16 slot, ZXIC_UINT16 vport,
-                                   ZXIC_UINT8 mac0, ZXIC_UINT8 mac1, ZXIC_UINT8 mac2,
-                                   ZXIC_UINT8 mac3, ZXIC_UINT8 mac4, ZXIC_UINT8 mac5)
+									  ZXIC_UINT8 mac0, ZXIC_UINT8 mac1,
+									  ZXIC_UINT8 mac2, ZXIC_UINT8 mac3,
+									  ZXIC_UINT8 mac4, ZXIC_UINT8 mac5)
 {
-    DPP_PF_INFO_T pf_info = {slot, vport};
+	DPP_PF_INFO_T pf_info = { slot, vport };
 
-    ZXIC_UINT8  mac[6];
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT8 mac[6];
+	ZXIC_UINT32 rc = DPP_OK;
 
-    mac[0] = mac0;
-    mac[1] = mac1;
-    mac[2] = mac2;
-    mac[3] = mac3;
-    mac[4] = mac4;
-    mac[5] = mac5;
+	mac[0] = mac0;
+	mac[1] = mac1;
+	mac[2] = mac2;
+	mac[3] = mac3;
+	mac[4] = mac4;
+	mac[5] = mac5;
 
-    rc = dpp_multi_mac_add_member(&pf_info, mac);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_multi_mac_add_member");
+	rc = dpp_multi_mac_add_member(&pf_info, mac);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_multi_mac_add_member");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 diag_dpp_vport_mc_mac_del(ZXIC_UINT16 slot, ZXIC_UINT16 vport,
-                                   ZXIC_UINT8 mac0, ZXIC_UINT8 mac1, ZXIC_UINT8 mac2,
-                                   ZXIC_UINT8 mac3, ZXIC_UINT8 mac4, ZXIC_UINT8 mac5)
+									  ZXIC_UINT8 mac0, ZXIC_UINT8 mac1,
+									  ZXIC_UINT8 mac2, ZXIC_UINT8 mac3,
+									  ZXIC_UINT8 mac4, ZXIC_UINT8 mac5)
 {
-    DPP_PF_INFO_T pf_info = {slot, vport};
+	DPP_PF_INFO_T pf_info = { slot, vport };
 
-    ZXIC_UINT8  mac[6];
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT8 mac[6];
+	ZXIC_UINT32 rc = DPP_OK;
 
-    mac[0] = mac0;
-    mac[1] = mac1;
-    mac[2] = mac2;
-    mac[3] = mac3;
-    mac[4] = mac4;
-    mac[5] = mac5;
+	mac[0] = mac0;
+	mac[1] = mac1;
+	mac[2] = mac2;
+	mac[3] = mac3;
+	mac[4] = mac4;
+	mac[5] = mac5;
 
-    rc = dpp_multi_mac_del_member(&pf_info, mac);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_multi_mac_del_member");
+	rc = dpp_multi_mac_del_member(&pf_info, mac);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_multi_mac_del_member");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 diag_dpp_vport_mc_mac_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport)
 {
-    ZXIC_UINT32 mac_num = 0;
-    ZXIC_UINT32 i = 0;
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 mac_num = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    DPP_PF_INFO_T pf_info = {slot, vport};
+	DPP_PF_INFO_T pf_info = { slot, vport };
 
-    MAC_VPORT_INFO *p_mac_arr = (MAC_VPORT_INFO *)ZXIC_COMM_MALLOC(DTB_DUMP_MULTICAST_MAC_DUMP_NUM *
-                                                                            sizeof(MAC_VPORT_INFO));
-    ZXIC_COMM_CHECK_POINT(p_mac_arr);
+	MAC_VPORT_INFO *p_mac_arr = (MAC_VPORT_INFO *)ZXIC_COMM_MALLOC(
+			DTB_DUMP_MULTICAST_MAC_DUMP_NUM * sizeof(MAC_VPORT_INFO));
+	ZXIC_COMM_CHECK_POINT(p_mac_arr);
 
-    rc = dpp_multicast_mac_dump(&pf_info, p_mac_arr, &mac_num);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE(rc, "dpp_multicast_mac_dump", p_mac_arr);
+	rc = dpp_multicast_mac_dump(&pf_info, p_mac_arr, &mac_num);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE(rc, "dpp_multicast_mac_dump", p_mac_arr);
 
-    ZXIC_COMM_PRINT("-----------------------------------------------\n");
-    for (i = 0; i < mac_num; i++)
-    {
-        ZXIC_COMM_PRINT("slot: %u vport: 0x%04x mac: %02x:%02x:%02x:%02x:%02x:%02x\n",
-                                                          slot, p_mac_arr[i].vport,
-                                                          p_mac_arr[i].addr[0], p_mac_arr[i].addr[1],
-                                                          p_mac_arr[i].addr[2], p_mac_arr[i].addr[3],
-                                                          p_mac_arr[i].addr[4], p_mac_arr[i].addr[5]);
-    }
-    ZXIC_COMM_PRINT("-----------------------------------------------\n");
+	ZXIC_COMM_PRINT("-----------------------------------------------\n");
+	for (i = 0; i < mac_num; i++) {
+		ZXIC_COMM_PRINT(
+				"slot: %u vport: 0x%04x mac: %02x:%02x:%02x:%02x:%02x:%02x\n",
+				slot, p_mac_arr[i].vport, p_mac_arr[i].addr[0],
+				p_mac_arr[i].addr[1], p_mac_arr[i].addr[2],
+				p_mac_arr[i].addr[3], p_mac_arr[i].addr[4],
+				p_mac_arr[i].addr[5]);
+	}
+	ZXIC_COMM_PRINT("-----------------------------------------------\n");
 
-    ZXIC_COMM_FREE(p_mac_arr);
+	ZXIC_COMM_FREE(p_mac_arr);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-ZXIC_UINT32 diag_dpp_vport_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 attr,
-                                                                         ZXIC_UINT32 value)
+ZXIC_UINT32 diag_dpp_vport_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport,
+									 ZXIC_UINT32 attr, ZXIC_UINT32 value)
 {
-    DPP_PF_INFO_T pf_info = {slot, vport};
+	DPP_PF_INFO_T pf_info = { slot, vport };
 
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    rc = dpp_egr_port_attr_set(&pf_info, attr, value);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
+	rc = dpp_egr_port_attr_set(&pf_info, attr, value);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
 ZXIC_UINT32 diag_dpp_vport_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport)
 {
-    ZXDH_VPORT_T port_table = {0};
-    DPP_PF_INFO_T pf_info = {slot, vport};
-
-    ZXIC_UINT32 rc = DPP_OK;
-
-    rc = dpp_egr_port_attr_get(&pf_info, &port_table);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
-
-    ZXIC_COMM_PRINT("-----------------------------------------------\n");
-    ZXIC_COMM_PRINT("hit_flag = %u\n", port_table.hit_flag);
-    ZXIC_COMM_PRINT("%02u mtu_offload_enable = %u\n", EGR_FLAG_MTU_OFFLOAD_EN_OFF, port_table.mtu_offload_enable);
-    ZXIC_COMM_PRINT("%02u rss_enable = %u\n", EGR_FLAG_RSS_EN_OFF, port_table.rss_enable);
-    ZXIC_COMM_PRINT("%02u qinq_vlan_strip_offload = %u\n", EGR_FLAG_QINQ_VLAN_STRIP_OFFLOAD, port_table.qinq_vlan_strip_offload);
-    ZXIC_COMM_PRINT("%02u vlan_strip_offload = %u\n", EGR_FLAG_VLAN_STRIP_OFFLOAD, port_table.vlan_strip_offload);
-    ZXIC_COMM_PRINT("%02u vlan_filter_enable = %u\n", EGR_FLAG_VLAN_FILTER_EN_OFF, port_table.vlan_filter_enable);
-    ZXIC_COMM_PRINT("%02u rdma_offload_enable = %u\n", EGR_FLAG_RDMA_OFFLOAD_EN_OFF, port_table.rdma_offload_enable);
-    ZXIC_COMM_PRINT("%02u hw_bond_enable = %u\n", EGR_FLAG_HW_BOND_EN_OFF, port_table.hw_bond_enable);
-    ZXIC_COMM_PRINT("%02u allmulticast_enable = %u\n", EGR_FLAG_IFF_ALLMULTI_EN_OFF, port_table.allmulticast_enable);
-    ZXIC_COMM_PRINT("%02u is_up = %u\n", EGR_FLAG_VPORT_IS_UP, port_table.is_up);
-    ZXIC_COMM_PRINT("%02u outer_ip_checksum_offload = %u\n", EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD, port_table.outer_ip_checksum_offload);
-    ZXIC_COMM_PRINT("%02u ip_checksum_offload = %u\n", EGR_FLAG_IP_CHKSUM, port_table.ip_checksum_offload);
-    ZXIC_COMM_PRINT("%02u tcp_udp_checksum_offload = %u\n", EGR_FLAG_TCP_UDP_CHKSUM, port_table.tcp_udp_checksum_offload);
-    ZXIC_COMM_PRINT("%02u ip_fragment_offload = %u\n", EGR_FLAG_IP_FRAGMENT_OFFLOAD, port_table.ip_fragment_offload);
-    ZXIC_COMM_PRINT("%02u lro_offload = %u\n", EGR_FLAG_IPV6_TCP_ASSEMBLE, port_table.lro_offload);
-    ZXIC_COMM_PRINT("%02u lro_offload = %u\n", EGR_FLAG_IPV4_TCP_ASSEMBLE, port_table.lro_offload);
-    ZXIC_COMM_PRINT("%02u accelerator_offload_flag = %u\n", EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, port_table.accelerator_offload_flag);
-    ZXIC_COMM_PRINT("%02u virtio_enable = %u\n", EGR_FLAG_VIRTION_EN_OFF, port_table.virtio_enable);
-    ZXIC_COMM_PRINT("%02u virtion_version = %u\n", EGR_FLAG_VIRTION_VERSION, port_table.virtion_version);
-    ZXIC_COMM_PRINT("%02u is_vf = %u\n", EGR_FLAG_IS_VF, port_table.is_vf);
-    ZXIC_COMM_PRINT("%02u is_passthrough = %u\n", EGR_FLAG_IS_PASSTHROUGH, port_table.is_passthrough);
-    ZXIC_COMM_PRINT("%02u lag_enable = %u\n", EGR_FLAG_LAG_EN_OFF, port_table.lag_enable);
-    ZXIC_COMM_PRINT("%02u ovs_enable = %u\n", EGR_FLAG_OVS_EN_OFF, port_table.ovs_enable);
-    ZXIC_COMM_PRINT("%02u inline_sec_offload = %u\n", EGR_FLAG_INLINE_SEC_OFFLOAD, port_table.inline_sec_offload);
-    ZXIC_COMM_PRINT("%02u spoof_check_enable = %u\n", EGR_FLAG_SPOOFCHK_EN_OFF, port_table.spoof_check_enable);
-    ZXIC_COMM_PRINT("%02u vepa_enable = %u\n", EGR_FLAG_VEPA_EN_OFF, port_table.vepa_enable);
-    ZXIC_COMM_PRINT("%02u fd_enable = %u\n", EGR_FLAG_FD_EN_OFF, port_table.fd_enable);
-    ZXIC_COMM_PRINT("%02u egress_meter_mode = %u\n", EGR_FLAG_EGRESS_MODE, port_table.egress_meter_mode);
-    ZXIC_COMM_PRINT("%02u ingress_meter_mode = %u\n", EGR_FLAG_INGRESS_MODE, port_table.ingress_meter_mode);
-    ZXIC_COMM_PRINT("%02u egress_meter_enable = %u\n", EGR_FLAG_EGRESS_METER_EN_OFF, port_table.egress_meter_enable);
-    ZXIC_COMM_PRINT("%02u ingress_meter_enable = %u\n", EGR_FLAG_INGRESS_METER_EN_OFF, port_table.ingress_meter_enable);
-    ZXIC_COMM_PRINT("%02u tm_enable = %u\n", EGR_FLAG_TM_EN_OFF, port_table.tm_enable);
-    ZXIC_COMM_PRINT("%02u hash_search_index = %u\n", EGR_FLAG_HASH_SEARCH_INDEX, port_table.hash_search_index);
-    ZXIC_COMM_PRINT("%02u port_base_qid = %u\n", EGR_FLAG_PORT_BASE_QID, port_table.port_base_qid);
-    ZXIC_COMM_PRINT("%02u mtu = %u\n", EGR_FLAG_MTU, port_table.mtu);
-    ZXIC_COMM_PRINT("%02u pf_vqm_vfid = %u\n", EGR_FLAG_PF_VQM_VFID, port_table.pf_vqm_vfid);
-    ZXIC_COMM_PRINT("%02u lag_id = %u\n", EGR_FLAG_LAG_ID, port_table.lag_id);
-    ZXIC_COMM_PRINT("%02u panel_id = %u\n", EGR_FLAG_PANEL_ID, port_table.panel_id);
-    ZXIC_COMM_PRINT("%02u hash_alg = %u\n", EGR_FLAG_HASH_ALG, port_table.hash_alg);
-    ZXIC_COMM_PRINT("%02u rss_hash_factor = %u\n", EGR_FLAG_RSS_HASH_FACTOR, port_table.rss_hash_factor);
-    ZXIC_COMM_PRINT("%02u uplink_port = %u\n", EGR_FLAG_UPLINK_PORT, port_table.uplink_port);
-    ZXIC_COMM_PRINT("%02u vhca = %u\n", EGR_FLAG_VHCA, port_table.vhca);
-    ZXIC_COMM_PRINT("%02u tpid = %u\n", EGR_FLAG_TPID, port_table.tpid);
-    ZXIC_COMM_PRINT("-----------------------------------------------\n");
-
-    return DPP_OK;
+	ZXDH_VPORT_T port_table = { 0 };
+	DPP_PF_INFO_T pf_info = { slot, vport };
+
+	ZXIC_UINT32 rc = DPP_OK;
+
+	rc = dpp_egr_port_attr_get(&pf_info, &port_table);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
+
+	ZXIC_COMM_PRINT("-----------------------------------------------\n");
+	ZXIC_COMM_PRINT("hit_flag = %u\n", port_table.hit_flag);
+	ZXIC_COMM_PRINT("%02u mtu_offload_enable = %u\n",
+					EGR_FLAG_MTU_OFFLOAD_EN_OFF, port_table.mtu_offload_enable);
+	ZXIC_COMM_PRINT("%02u rss_enable = %u\n", EGR_FLAG_RSS_EN_OFF,
+					port_table.rss_enable);
+	ZXIC_COMM_PRINT("%02u qinq_vlan_strip_offload = %u\n",
+					EGR_FLAG_QINQ_VLAN_STRIP_OFFLOAD,
+					port_table.qinq_vlan_strip_offload);
+	ZXIC_COMM_PRINT("%02u vlan_strip_offload = %u\n",
+					EGR_FLAG_VLAN_STRIP_OFFLOAD, port_table.vlan_strip_offload);
+	ZXIC_COMM_PRINT("%02u vlan_filter_enable = %u\n",
+					EGR_FLAG_VLAN_FILTER_EN_OFF, port_table.vlan_filter_enable);
+	ZXIC_COMM_PRINT("%02u rdma_offload_enable = %u\n",
+					EGR_FLAG_RDMA_OFFLOAD_EN_OFF,
+					port_table.rdma_offload_enable);
+	ZXIC_COMM_PRINT("%02u hw_bond_enable = %u\n", EGR_FLAG_HW_BOND_EN_OFF,
+					port_table.hw_bond_enable);
+	ZXIC_COMM_PRINT("%02u allmulticast_enable = %u\n",
+					EGR_FLAG_IFF_ALLMULTI_EN_OFF,
+					port_table.allmulticast_enable);
+	ZXIC_COMM_PRINT("%02u is_up = %u\n", EGR_FLAG_VPORT_IS_UP,
+					port_table.is_up);
+	ZXIC_COMM_PRINT("%02u outer_ip_checksum_offload = %u\n",
+					EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD,
+					port_table.outer_ip_checksum_offload);
+	ZXIC_COMM_PRINT("%02u ip_checksum_offload = %u\n", EGR_FLAG_IP_CHKSUM,
+					port_table.ip_checksum_offload);
+	ZXIC_COMM_PRINT("%02u tcp_udp_checksum_offload = %u\n",
+					EGR_FLAG_TCP_UDP_CHKSUM,
+					port_table.tcp_udp_checksum_offload);
+	ZXIC_COMM_PRINT("%02u ip_fragment_offload = %u\n",
+					EGR_FLAG_IP_FRAGMENT_OFFLOAD,
+					port_table.ip_fragment_offload);
+	ZXIC_COMM_PRINT("%02u lro_offload = %u\n", EGR_FLAG_IPV6_TCP_ASSEMBLE,
+					port_table.lro_offload);
+	ZXIC_COMM_PRINT("%02u lro_offload = %u\n", EGR_FLAG_IPV4_TCP_ASSEMBLE,
+					port_table.lro_offload);
+	ZXIC_COMM_PRINT("%02u accelerator_offload_flag = %u\n",
+					EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG,
+					port_table.accelerator_offload_flag);
+	ZXIC_COMM_PRINT("%02u virtio_enable = %u\n", EGR_FLAG_VIRTION_EN_OFF,
+					port_table.virtio_enable);
+	ZXIC_COMM_PRINT("%02u virtion_version = %u\n", EGR_FLAG_VIRTION_VERSION,
+					port_table.virtion_version);
+	ZXIC_COMM_PRINT("%02u is_vf = %u\n", EGR_FLAG_IS_VF, port_table.is_vf);
+	ZXIC_COMM_PRINT("%02u is_passthrough = %u\n", EGR_FLAG_IS_PASSTHROUGH,
+					port_table.is_passthrough);
+	ZXIC_COMM_PRINT("%02u lag_enable = %u\n", EGR_FLAG_LAG_EN_OFF,
+					port_table.lag_enable);
+	ZXIC_COMM_PRINT("%02u ovs_enable = %u\n", EGR_FLAG_OVS_EN_OFF,
+					port_table.ovs_enable);
+	ZXIC_COMM_PRINT("%02u inline_sec_offload = %u\n",
+					EGR_FLAG_INLINE_SEC_OFFLOAD, port_table.inline_sec_offload);
+	ZXIC_COMM_PRINT("%02u spoof_check_enable = %u\n", EGR_FLAG_SPOOFCHK_EN_OFF,
+					port_table.spoof_check_enable);
+	ZXIC_COMM_PRINT("%02u vepa_enable = %u\n", EGR_FLAG_VEPA_EN_OFF,
+					port_table.vepa_enable);
+	ZXIC_COMM_PRINT("%02u fd_enable = %u\n", EGR_FLAG_FD_EN_OFF,
+					port_table.fd_enable);
+	ZXIC_COMM_PRINT("%02u egress_meter_mode = %u\n", EGR_FLAG_EGRESS_MODE,
+					port_table.egress_meter_mode);
+	ZXIC_COMM_PRINT("%02u ingress_meter_mode = %u\n", EGR_FLAG_INGRESS_MODE,
+					port_table.ingress_meter_mode);
+	ZXIC_COMM_PRINT("%02u egress_meter_enable = %u\n",
+					EGR_FLAG_EGRESS_METER_EN_OFF,
+					port_table.egress_meter_enable);
+	ZXIC_COMM_PRINT("%02u ingress_meter_enable = %u\n",
+					EGR_FLAG_INGRESS_METER_EN_OFF,
+					port_table.ingress_meter_enable);
+	ZXIC_COMM_PRINT("%02u tm_enable = %u\n", EGR_FLAG_TM_EN_OFF,
+					port_table.tm_enable);
+	ZXIC_COMM_PRINT("%02u hash_search_index = %u\n", EGR_FLAG_HASH_SEARCH_INDEX,
+					port_table.hash_search_index);
+	ZXIC_COMM_PRINT("%02u port_base_qid = %u\n", EGR_FLAG_PORT_BASE_QID,
+					port_table.port_base_qid);
+	ZXIC_COMM_PRINT("%02u mtu = %u\n", EGR_FLAG_MTU, port_table.mtu);
+	ZXIC_COMM_PRINT("%02u pf_vqm_vfid = %u\n", EGR_FLAG_PF_VQM_VFID,
+					port_table.pf_vqm_vfid);
+	ZXIC_COMM_PRINT("%02u lag_id = %u\n", EGR_FLAG_LAG_ID, port_table.lag_id);
+	ZXIC_COMM_PRINT("%02u panel_id = %u\n", EGR_FLAG_PANEL_ID,
+					port_table.panel_id);
+	ZXIC_COMM_PRINT("%02u hash_alg = %u\n", EGR_FLAG_HASH_ALG,
+					port_table.hash_alg);
+	ZXIC_COMM_PRINT("%02u rss_hash_factor = %u\n", EGR_FLAG_RSS_HASH_FACTOR,
+					port_table.rss_hash_factor);
+	ZXIC_COMM_PRINT("%02u uplink_port = %u\n", EGR_FLAG_UPLINK_PORT,
+					port_table.uplink_port);
+	ZXIC_COMM_PRINT("%02u vhca = %u\n", EGR_FLAG_VHCA, port_table.vhca);
+	ZXIC_COMM_PRINT("%02u tpid = %u\n", EGR_FLAG_TPID, port_table.tpid);
+	ZXIC_COMM_PRINT("-----------------------------------------------\n");
+
+	return DPP_OK;
 }
 
-ZXIC_UINT32 diag_dpp_vport_panel_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT8 panel_id,
-                                                                ZXIC_UINT32 attr, ZXIC_UINT32 value)
+ZXIC_UINT32 diag_dpp_vport_panel_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport,
+										   ZXIC_UINT8 panel_id,
+										   ZXIC_UINT32 attr, ZXIC_UINT32 value)
 {
-    DPP_PF_INFO_T pf_info = {slot, vport};
+	DPP_PF_INFO_T pf_info = { slot, vport };
 
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    rc = dpp_panel_attr_set(&pf_info, panel_id, attr, value);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
+	rc = dpp_panel_attr_set(&pf_info, panel_id, attr, value);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-ZXIC_UINT32 diag_dpp_vport_panel_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT8 panel_id)
+ZXIC_UINT32 diag_dpp_vport_panel_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport,
+										   ZXIC_UINT8 panel_id)
 {
-    DPP_DEV_T dev = {0};
-    ZXDH_PANEL_PORT_T panel_table = {0};
-    DPP_PF_INFO_T pf_info = {slot, vport};
-
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_PANEL_PORT_ATTR_TABLE;
-    ZXIC_UINT32 rc     = DPP_OK;
-
-    rc = dpp_dev_get(dev_id, &pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
-
-    rc = dpp_dtb_queue_id_get(dev_id, &pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
-
-    rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, panel_id, &panel_table);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
-
-    ZXIC_COMM_PRINT("-----------------------------------------------\n");
-    ZXIC_COMM_PRINT("hit_flag = %u\n", panel_table.hit_flag);
-    ZXIC_COMM_PRINT("%02u trust_mode = %u\n", PANEL_FLAG_TRUST_MODE, panel_table.trust_mode);
-    ZXIC_COMM_PRINT("%02u ptp_tc_enable = %u\n", PANEL_FLAG_PTP_TC_ENABLE, panel_table.ptp_tc_enable);
-    ZXIC_COMM_PRINT("%02u tm_shape_enable = %u\n", PANEL_FLAG_TM_SHAPE_ENABLE, panel_table.tm_shape_enable);
-    ZXIC_COMM_PRINT("%02u pf_vqm_vfid = %u\n", PANEL_FLAG_PF_VQM_VFID, panel_table.pf_vqm_vfid);
-    ZXIC_COMM_PRINT("%02u ptp_port_vfid = %u\n", PANEL_FLAG_PTP_PORT_VFID, panel_table.ptp_port_vfid);
-    ZXIC_COMM_PRINT("%02u tm_base_queue = %u\n", PANEL_FLAG_TM_BASE_QUEUE, panel_table.tm_base_queue);
-    ZXIC_COMM_PRINT("%02u mtu_offload_enable = %u\n", PANEL_FLAG_MTU_OFFLOAD_ENABLE, panel_table.mtu_offload_enable);
-    ZXIC_COMM_PRINT("%02u mtu = %u\n", PANEL_FLAG_MTU, panel_table.mtu);
-    ZXIC_COMM_PRINT("%02u hw_bond_enable = %u\n", PANEL_FLAG_HW_BOND_ENABLE, panel_table.hw_bond_enable);
-    ZXIC_COMM_PRINT("%02u bond_link_up = %u\n", PANEL_FLAG_BOND_LINK_UP, panel_table.bond_link_up);
-    ZXIC_COMM_PRINT("%02u is_up = %u\n", PANEL_FLAG_IS_UP, panel_table.is_up);
-    ZXIC_COMM_PRINT("%02u bond_pf_vqm_vfid = %u\n", PANEL_FLAG_BOND_PF_VQM_VFID, panel_table.bond_pf_vqm_vfid);
-    ZXIC_COMM_PRINT("%02u pf_memport_qid = %u\n", PANEL_FLAG_PF_MEMPORT_QID, panel_table.pf_memport_qid);
-    ZXIC_COMM_PRINT("%02u ovs_pf_vfid = %u\n", PANEL_FLAG_OVS_PF_VFID, panel_table.ovs_pf_vfid);
-    ZXIC_COMM_PRINT("-----------------------------------------------\n");
-
-    return DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXDH_PANEL_PORT_T panel_table = { 0 };
+	DPP_PF_INFO_T pf_info = { slot, vport };
+
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_PANEL_PORT_ATTR_TABLE;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	rc = dpp_dev_get(dev_id, &pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+
+	rc = dpp_dtb_queue_id_get(dev_id, &pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+
+	rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, panel_id, &panel_table);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
+
+	ZXIC_COMM_PRINT("-----------------------------------------------\n");
+	ZXIC_COMM_PRINT("hit_flag = %u\n", panel_table.hit_flag);
+	ZXIC_COMM_PRINT("%02u trust_mode = %u\n", PANEL_FLAG_TRUST_MODE,
+					panel_table.trust_mode);
+	ZXIC_COMM_PRINT("%02u ptp_tc_enable = %u\n", PANEL_FLAG_PTP_TC_ENABLE,
+					panel_table.ptp_tc_enable);
+	ZXIC_COMM_PRINT("%02u tm_shape_enable = %u\n", PANEL_FLAG_TM_SHAPE_ENABLE,
+					panel_table.tm_shape_enable);
+	ZXIC_COMM_PRINT("%02u pf_vqm_vfid = %u\n", PANEL_FLAG_PF_VQM_VFID,
+					panel_table.pf_vqm_vfid);
+	ZXIC_COMM_PRINT("%02u ptp_port_vfid = %u\n", PANEL_FLAG_PTP_PORT_VFID,
+					panel_table.ptp_port_vfid);
+	ZXIC_COMM_PRINT("%02u tm_base_queue = %u\n", PANEL_FLAG_TM_BASE_QUEUE,
+					panel_table.tm_base_queue);
+	ZXIC_COMM_PRINT("%02u mtu_offload_enable = %u\n",
+					PANEL_FLAG_MTU_OFFLOAD_ENABLE,
+					panel_table.mtu_offload_enable);
+	ZXIC_COMM_PRINT("%02u mtu = %u\n", PANEL_FLAG_MTU, panel_table.mtu);
+	ZXIC_COMM_PRINT("%02u hw_bond_enable = %u\n", PANEL_FLAG_HW_BOND_ENABLE,
+					panel_table.hw_bond_enable);
+	ZXIC_COMM_PRINT("%02u bond_link_up = %u\n", PANEL_FLAG_BOND_LINK_UP,
+					panel_table.bond_link_up);
+	ZXIC_COMM_PRINT("%02u is_up = %u\n", PANEL_FLAG_IS_UP, panel_table.is_up);
+	ZXIC_COMM_PRINT("%02u bond_pf_vqm_vfid = %u\n", PANEL_FLAG_BOND_PF_VQM_VFID,
+					panel_table.bond_pf_vqm_vfid);
+	ZXIC_COMM_PRINT("%02u pf_memport_qid = %u\n", PANEL_FLAG_PF_MEMPORT_QID,
+					panel_table.pf_memport_qid);
+	ZXIC_COMM_PRINT("%02u ovs_pf_vfid = %u\n", PANEL_FLAG_OVS_PF_VFID,
+					panel_table.ovs_pf_vfid);
+	ZXIC_COMM_PRINT("-----------------------------------------------\n");
+
+	return DPP_OK;
 }
 
-ZXIC_UINT32 diag_dpp_vport_bc_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 enable)
+ZXIC_UINT32 diag_dpp_vport_bc_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport,
+										ZXIC_UINT32 enable)
 {
-    DPP_PF_INFO_T pf_info = {slot, vport};
-
-    ZXIC_UINT32 rc = DPP_OK;
-
-    if (enable == 1)
-    {
-        rc = dpp_vport_bond_pf(&pf_info);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bond_pf");
-    }
-    else
-    {
-        rc = dpp_vport_unbond_pf(&pf_info);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_vport_unbond_pf");
-    }
-
-    return DPP_OK;
+	DPP_PF_INFO_T pf_info = { slot, vport };
+
+	ZXIC_UINT32 rc = DPP_OK;
+
+	if (enable == 1) {
+		rc = dpp_vport_bond_pf(&pf_info);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_vport_bond_pf");
+	} else {
+		rc = dpp_vport_unbond_pf(&pf_info);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_vport_unbond_pf");
+	}
+
+	return DPP_OK;
 }
 
 ZXIC_UINT32 diag_dpp_vport_bc_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport)
 {
-    DPP_DEV_T dev = {0};
-    ZXDH_BC_T bc_table = {0};
-    DPP_PF_INFO_T pf_info = {slot, vport};
-
-    ZXIC_UINT32 dev_id   = 0;
-    ZXIC_UINT32 queue    = 0;
-    ZXIC_UINT32 sdt_no   = ZXDH_SDT_BC_TABLE;
-    ZXIC_UINT32 group_id = 0;
-    ZXIC_UINT32 index    = 0;
-    ZXIC_UINT32 i        = 0;
-    ZXIC_UINT32 rc       = DPP_OK;
-
-    rc = dpp_dev_get(dev_id, &pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
-
-    rc = dpp_dtb_queue_id_get(dev_id, &pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
-
-    ZXIC_COMM_PRINT("-----------------------------------------------\n");
-    for (group_id = 0; group_id < BC_GROUP_NUM; group_id++)
-    {
-        index = (((OWNER_PF_VQM_VFID(pf_info.vport) - PF_VQM_VFID_OFFSET) << 2)| group_id);
-
-        rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &bc_table);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
-
-        if (bc_table.hit_flag == 1)
-        {
-            for (i = 0; i < BC_MEMBER_NUM_IN_GROUP; i++)
-            {
-                if ((bc_table.bc_bitmap & ((ZXIC_UINT64)(1) << (BC_MEMBER_NUM_IN_GROUP - 1 - i))) != 0)
-                {
-                    ZXIC_COMM_PRINT("vf %u enable\n", i + (group_id * BC_MEMBER_NUM_IN_GROUP));
-                }
-            }
-        }
-    }
-    ZXIC_COMM_PRINT("-----------------------------------------------\n");
-
-    return DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXDH_BC_T bc_table = { 0 };
+	DPP_PF_INFO_T pf_info = { slot, vport };
+
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_BC_TABLE;
+	ZXIC_UINT32 group_id = 0;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	rc = dpp_dev_get(dev_id, &pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+
+	rc = dpp_dtb_queue_id_get(dev_id, &pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+
+	ZXIC_COMM_PRINT("-----------------------------------------------\n");
+	for (group_id = 0; group_id < BC_GROUP_NUM; group_id++) {
+		index = (((OWNER_PF_VQM_VFID(pf_info.vport) - PF_VQM_VFID_OFFSET)
+				  << 2) |
+				 group_id);
+
+		rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &bc_table);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
+
+		if (bc_table.hit_flag == 1) {
+			for (i = 0; i < BC_MEMBER_NUM_IN_GROUP; i++) {
+				if ((bc_table.bc_bitmap &
+					 ((ZXIC_UINT64)(1) << (BC_MEMBER_NUM_IN_GROUP - 1 - i))) !=
+					0) {
+					ZXIC_COMM_PRINT("vf %u enable\n",
+									i + group_id * BC_MEMBER_NUM_IN_GROUP);
+				}
+			}
+		}
+	}
+	ZXIC_COMM_PRINT("-----------------------------------------------\n");
+
+	return DPP_OK;
 }
 
-ZXIC_UINT32 diag_dpp_vport_promisc_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 sdt_no)
+ZXIC_UINT32 diag_dpp_vport_promisc_table_prt(ZXIC_UINT16 slot,
+											 ZXIC_UINT16 vport,
+											 ZXIC_UINT32 sdt_no)
 {
-    DPP_DEV_T dev = {0};
-    ZXDH_PROMISC_T promisc_table[4] = {0};
-    DPP_PF_INFO_T pf_info = {slot, vport};
-
-    ZXIC_UINT32 dev_id   = 0;
-    ZXIC_UINT32 queue    = 0;
-    ZXIC_UINT32 group_id = 0;
-    ZXIC_UINT32 index    = 0;
-    ZXIC_UINT32 i        = 0;
-    ZXIC_UINT32 rc       = DPP_OK;
-
-    rc = dpp_dev_get(dev_id, &pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
-
-    rc = dpp_dtb_queue_id_get(dev_id, &pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
-
-    ZXIC_COMM_PRINT("-----------------------------------------------\n");
-    for (group_id = 0; group_id < BC_GROUP_NUM; group_id++)
-    {
-        index = (((OWNER_PF_VQM_VFID(pf_info.vport) - PF_VQM_VFID_OFFSET) << 2)| group_id);
-
-        rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &promisc_table[group_id]);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
-
-        if (promisc_table[group_id].hit_flag == 1)
-        {
-            for (i = 0; i < PROMISC_MEMBER_NUM_IN_GROUP; i++)
-            {
-                if ((promisc_table[group_id].bitmap & ((ZXIC_UINT64)(1) << (PROMISC_MEMBER_NUM_IN_GROUP - 1 - i))) != 0)
-                {
-                    ZXIC_COMM_PRINT("vf %u enable\n", i + (group_id * PROMISC_MEMBER_NUM_IN_GROUP));
-                }
-            }
-        }
-    }
-    if ((promisc_table[0].pf_enable == 1) && (promisc_table[1].pf_enable == 1) &&
-        (promisc_table[2].pf_enable == 1) && (promisc_table[3].pf_enable == 1))
-    {
-        ZXIC_COMM_PRINT("pf enable\n");
-    }
-    ZXIC_COMM_PRINT("-----------------------------------------------\n");
-
-    return DPP_OK;
+	DPP_DEV_T dev = { 0 };
+	ZXDH_PROMISC_T promisc_table[4] = { 0 };
+	DPP_PF_INFO_T pf_info = { slot, vport };
+
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 group_id = 0;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	rc = dpp_dev_get(dev_id, &pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+
+	rc = dpp_dtb_queue_id_get(dev_id, &pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+
+	ZXIC_COMM_PRINT("-----------------------------------------------\n");
+	for (group_id = 0; group_id < BC_GROUP_NUM; group_id++) {
+		index = (((OWNER_PF_VQM_VFID(pf_info.vport) - PF_VQM_VFID_OFFSET)
+				  << 2) |
+				 group_id);
+
+		rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index,
+								  &promisc_table[group_id]);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
+
+		if (promisc_table[group_id].hit_flag == 1) {
+			for (i = 0; i < PROMISC_MEMBER_NUM_IN_GROUP; i++) {
+				if ((promisc_table[group_id].bitmap &
+					 ((ZXIC_UINT64)(1)
+					  << (PROMISC_MEMBER_NUM_IN_GROUP - 1 - i))) != 0) {
+					ZXIC_COMM_PRINT("vf %u enable\n",
+									i + group_id * PROMISC_MEMBER_NUM_IN_GROUP);
+				}
+			}
+		}
+	}
+	if (promisc_table[0].pf_enable == 1 && promisc_table[1].pf_enable == 1 &&
+		promisc_table[2].pf_enable == 1 && promisc_table[3].pf_enable == 1) {
+		ZXIC_COMM_PRINT("pf enable\n");
+	}
+	ZXIC_COMM_PRINT("-----------------------------------------------\n");
+
+	return DPP_OK;
 }
 
-ZXIC_UINT32 diag_dpp_vport_uc_promisc_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 enable)
+ZXIC_UINT32 diag_dpp_vport_uc_promisc_table_set(ZXIC_UINT16 slot,
+												ZXIC_UINT16 vport,
+												ZXIC_UINT32 enable)
 {
-    DPP_PF_INFO_T pf_info = {slot, vport};
+	DPP_PF_INFO_T pf_info = { slot, vport };
 
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    rc = dpp_vport_uc_promisc_set(&pf_info, enable);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_uc_promisc_set");
+	rc = dpp_vport_uc_promisc_set(&pf_info, enable);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_uc_promisc_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-ZXIC_UINT32 diag_dpp_vport_uc_promisc_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport)
+ZXIC_UINT32 diag_dpp_vport_uc_promisc_table_prt(ZXIC_UINT16 slot,
+												ZXIC_UINT16 vport)
 {
-    diag_dpp_vport_promisc_table_prt(slot, vport, ZXDH_SDT_UC_PROMISC_TABLE);
+	diag_dpp_vport_promisc_table_prt(slot, vport, ZXDH_SDT_UC_PROMISC_TABLE);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-ZXIC_UINT32 diag_dpp_vport_mc_promisc_table_set(ZXIC_UINT16 slot, ZXIC_UINT16 vport, ZXIC_UINT32 enable)
+ZXIC_UINT32 diag_dpp_vport_mc_promisc_table_set(ZXIC_UINT16 slot,
+												ZXIC_UINT16 vport,
+												ZXIC_UINT32 enable)
 {
-    DPP_PF_INFO_T pf_info = {slot, vport};
+	DPP_PF_INFO_T pf_info = { slot, vport };
 
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    rc = dpp_vport_mc_promisc_set(&pf_info, enable);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_promisc_set");
+	rc = dpp_vport_mc_promisc_set(&pf_info, enable);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_promisc_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 
-ZXIC_UINT32 diag_dpp_vport_mc_promisc_table_prt(ZXIC_UINT16 slot, ZXIC_UINT16 vport)
+ZXIC_UINT32 diag_dpp_vport_mc_promisc_table_prt(ZXIC_UINT16 slot,
+												ZXIC_UINT16 vport)
 {
-    diag_dpp_vport_promisc_table_prt(slot, vport, ZXDH_SDT_MC_PROMISC_TABLE);
+	diag_dpp_vport_promisc_table_prt(slot, vport, ZXDH_SDT_MC_PROMISC_TABLE);
 
-    return DPP_OK;
+	return DPP_OK;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_ipsec.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_ipsec.c
index 05f5fefcfbb1fda296ee847721c93d1321a5c49a..c2c14b6cd0207d99ac53230a3b6271c5a1f9a424 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_ipsec.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_ipsec.c
@@ -11,97 +11,99 @@
 #include "dpp_tbl_comm.h"
 #include "dpp_tbl_ipsec.h"
 
-ZXIC_UINT32 dpp_ipsec_enc_entry_add(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, 
-                                    ZXIC_UINT8 *sip, ZXIC_UINT8 *dip,
-                                    ZXIC_UINT8 *sip_mask, ZXIC_UINT8 *dip_mask,
-                                    ZXIC_UINT32 is_ipv4, ZXIC_UINT32 sa_id)
+ZXIC_UINT32 dpp_ipsec_enc_entry_add(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 index,
+									ZXIC_UINT8 *sip, ZXIC_UINT8 *dip,
+									ZXIC_UINT8 *sip_mask, ZXIC_UINT8 *dip_mask,
+									ZXIC_UINT32 is_ipv4, ZXIC_UINT32 sa_id)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
 
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_IPSEC_ENC_TABLE;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_IPSEC_ENC_TABLE;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_IPSEC_ENC_T ipsec_enc_entry = {0};
+	ZXDH_IPSEC_ENC_T ipsec_enc_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(sip);
-    ZXIC_COMM_CHECK_POINT(dip);
-    ZXIC_COMM_CHECK_POINT(sip_mask);
-    ZXIC_COMM_CHECK_POINT(dip_mask);
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(sip);
+	ZXIC_COMM_CHECK_POINT(dip);
+	ZXIC_COMM_CHECK_POINT(sip_mask);
+	ZXIC_COMM_CHECK_POINT(dip_mask);
 
-    ZXIC_COMM_MEMSET(&ipsec_enc_entry, 0, sizeof(ZXDH_IPSEC_ENC_T));
+	ZXIC_COMM_MEMSET(&ipsec_enc_entry, 0, sizeof(ZXDH_IPSEC_ENC_T));
 
-    ipsec_enc_entry.index = index;
+	ipsec_enc_entry.index = index;
 
-    ZXIC_COMM_MEMCPY(ipsec_enc_entry.key.sip, sip, is_ipv4? 4 : 16);
-    ZXIC_COMM_MEMCPY(ipsec_enc_entry.key.dip, dip, is_ipv4? 4 : 16);
-    ZXIC_COMM_MEMCPY(ipsec_enc_entry.mask.sip, sip_mask, is_ipv4? 4 : 16);
-    ZXIC_COMM_MEMCPY(ipsec_enc_entry.mask.dip, dip_mask, is_ipv4? 4 : 16);
+	ZXIC_COMM_MEMCPY(ipsec_enc_entry.key.sip, sip, is_ipv4 ? 4 : 16);
+	ZXIC_COMM_MEMCPY(ipsec_enc_entry.key.dip, dip, is_ipv4 ? 4 : 16);
+	ZXIC_COMM_MEMCPY(ipsec_enc_entry.mask.sip, sip_mask, is_ipv4 ? 4 : 16);
+	ZXIC_COMM_MEMCPY(ipsec_enc_entry.mask.dip, dip_mask, is_ipv4 ? 4 : 16);
 
-    ipsec_enc_entry.entry.sa_id = sa_id;
+	ipsec_enc_entry.entry.sa_id = sa_id;
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_apt_dtb_acl_entry_insert(&dev, queue, sdt_no, &ipsec_enc_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_acl_entry_insert");
+	rc = dpp_apt_dtb_acl_entry_insert(&dev, queue, sdt_no, &ipsec_enc_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_acl_entry_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u sa_id: %u is_ipv4: %u.\n",
-                    __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index, sa_id, is_ipv4);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u sa_id: %u is_ipv4: %u.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index, sa_id,
+			is_ipv4);
 
-    ZXIC_COMM_PRINT("[%s] sip:\n", __FUNCTION__);
-    dpp_data_print(sip, is_ipv4? 4 : 16);
+	ZXIC_COMM_PRINT("[%s] sip:\n", __FUNCTION__);
+	dpp_data_print(sip, is_ipv4 ? 4 : 16);
 
-    ZXIC_COMM_PRINT("[%s] sip_mask:\n", __FUNCTION__);
-    dpp_data_print(sip_mask, is_ipv4? 4 : 16);
+	ZXIC_COMM_PRINT("[%s] sip_mask:\n", __FUNCTION__);
+	dpp_data_print(sip_mask, is_ipv4 ? 4 : 16);
 
-    ZXIC_COMM_PRINT("[%s] dip:\n", __FUNCTION__);
-    dpp_data_print(dip, is_ipv4? 4 : 16);
+	ZXIC_COMM_PRINT("[%s] dip:\n", __FUNCTION__);
+	dpp_data_print(dip, is_ipv4 ? 4 : 16);
 
-    ZXIC_COMM_PRINT("[%s] dip_mask:\n", __FUNCTION__);
-    dpp_data_print(dip_mask, is_ipv4? 4 : 16);
+	ZXIC_COMM_PRINT("[%s] dip_mask:\n", __FUNCTION__);
+	dpp_data_print(dip_mask, is_ipv4 ? 4 : 16);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_ipsec_enc_entry_add);
 
-ZXIC_UINT32 dpp_ipsec_enc_entry_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index)
+ZXIC_UINT32 dpp_ipsec_enc_entry_del(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 index)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
 
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_IPSEC_ENC_TABLE;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_IPSEC_ENC_TABLE;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_IPSEC_ENC_T ipsec_enc_entry = {0};
+	ZXDH_IPSEC_ENC_T ipsec_enc_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_MEMSET(&ipsec_enc_entry, 0, sizeof(ZXDH_IPSEC_ENC_T));
-    ZXIC_COMM_MEMSET(&ipsec_enc_entry.mask, 0xFF, sizeof(ZXDH_IPSEC_ENC_MASK));
+	ZXIC_COMM_MEMSET(&ipsec_enc_entry, 0, sizeof(ZXDH_IPSEC_ENC_T));
+	ZXIC_COMM_MEMSET(&ipsec_enc_entry.mask, 0xFF, sizeof(ZXDH_IPSEC_ENC_MASK));
 
-    ipsec_enc_entry.index = index;
+	ipsec_enc_entry.index = index;
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_apt_dtb_acl_entry_insert(&dev, queue, sdt_no, &ipsec_enc_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_acl_entry_insert");
+	rc = dpp_apt_dtb_acl_entry_insert(&dev, queue, sdt_no, &ipsec_enc_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_acl_entry_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u.\n",
-                    __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_ipsec_enc_entry_del);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_lag.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_lag.c
index 14bbfef130c72f77151998100411d84dfd13994e..284d28e40b09f3cc732689b0df613f57a327c9e9 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_lag.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_lag.c
@@ -13,241 +13,261 @@
 #include "dpp_tbl_port.h"
 #include "dpp_tbl_lag.h"
 
-ZXIC_UINT32 dpp_lag_group_create(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id)
+ZXIC_UINT32 dpp_lag_group_create(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 lag_id)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_LAG_T lag_entry = {0};
+	ZXDH_LAG_T lag_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u start.\n", __FUNCTION__,
-                                                pf_info->slot, pf_info->vport, sdt_no, lag_id);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u start.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, lag_id);
 
-    ZXIC_COMM_MEMSET(&lag_entry, 0, sizeof(ZXDH_LAG_T));
+	ZXIC_COMM_MEMSET(&lag_entry, 0, sizeof(ZXDH_LAG_T));
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    lag_entry.hit_flag = 1;
-    lag_entry.bond_mode = LAG_LACP_MODE;
+	lag_entry.hit_flag = 1;
+	lag_entry.bond_mode = LAG_LACP_MODE;
 
-    rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, lag_id, &lag_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
+	rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, lag_id, &lag_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u success.\n", __FUNCTION__,
-                                                pf_info->slot, pf_info->vport, sdt_no, lag_id);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, lag_id);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_lag_group_create);
 
-ZXIC_UINT32 dpp_lag_group_delete(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id)
+ZXIC_UINT32 dpp_lag_group_delete(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 lag_id)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u start.\n", __FUNCTION__,
-                                                pf_info->slot, pf_info->vport, sdt_no, lag_id);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u start.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, lag_id);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_apt_dtb_eram_clear(&dev, queue, sdt_no, lag_id);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_clear");
+	rc = dpp_apt_dtb_eram_clear(&dev, queue, sdt_no, lag_id);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_clear");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u success.\n", __FUNCTION__,
-                                                  pf_info->slot, pf_info->vport, sdt_no, lag_id);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, lag_id);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_lag_group_delete);
 
-ZXIC_UINT32 dpp_lag_mode_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id, ZXIC_UINT8 mode)
+ZXIC_UINT32 dpp_lag_mode_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 lag_id,
+							 ZXIC_UINT8 mode)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_LAG_T lag_entry = {0};
+	ZXDH_LAG_T lag_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u mode: %u start.\n", __FUNCTION__,
-                                                   pf_info->slot, pf_info->vport, sdt_no, lag_id, mode);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u mode: %u start.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, lag_id, mode);
 
-    ZXIC_COMM_CHECK_INDEX(mode, LAG_STANDBY_MODE, LAG_LACP_MODE);
+	ZXIC_COMM_CHECK_INDEX(mode, LAG_STANDBY_MODE, LAG_LACP_MODE);
 
-    ZXIC_COMM_MEMSET(&lag_entry, 0, sizeof(ZXDH_LAG_T));
+	ZXIC_COMM_MEMSET(&lag_entry, 0, sizeof(ZXDH_LAG_T));
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, lag_id, &lag_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
+	rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, lag_id, &lag_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
 
-    lag_entry.hit_flag = 1;
-    lag_entry.bond_mode = mode;
+	lag_entry.hit_flag = 1;
+	lag_entry.bond_mode = mode;
 
-    rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, lag_id, &lag_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
+	rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, lag_id, &lag_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u mode: %u success.\n", __FUNCTION__,
-                                                     pf_info->slot, pf_info->vport, sdt_no, lag_id, mode);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u mode: %u success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, lag_id, mode);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_lag_mode_set);
 
-ZXIC_UINT32 dpp_lag_group_hash_factor_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id, ZXIC_UINT8 factor)
+ZXIC_UINT32 dpp_lag_group_hash_factor_set(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT8 lag_id, ZXIC_UINT8 factor)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_LAG_T lag_entry = {0};
+	ZXDH_LAG_T lag_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u factor: %u start.\n", __FUNCTION__,
-                                                   pf_info->slot, pf_info->vport, sdt_no, lag_id, factor);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u factor: %u start.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, lag_id,
+			factor);
 
-    ZXIC_COMM_MEMSET(&lag_entry, 0, sizeof(ZXDH_LAG_T));
+	ZXIC_COMM_MEMSET(&lag_entry, 0, sizeof(ZXDH_LAG_T));
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, lag_id, &lag_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
+	rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, lag_id, &lag_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
 
-    lag_entry.hit_flag = 1;
-    lag_entry.hash_factor = factor;
+	lag_entry.hit_flag = 1;
+	lag_entry.hash_factor = factor;
 
-    rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, lag_id, &lag_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
+	rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, lag_id, &lag_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u factor: %u success.\n", __FUNCTION__,
-                                                     pf_info->slot, pf_info->vport, sdt_no, lag_id, factor);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u factor: %u success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, lag_id,
+			factor);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_lag_group_hash_factor_set);
 
-ZXIC_UINT32 dpp_lag_group_member_add(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id, ZXIC_UINT8 panel_id)
+ZXIC_UINT32 dpp_lag_group_member_add(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 lag_id,
+									 ZXIC_UINT8 panel_id)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_LAG_T lag_entry = {0};
+	ZXDH_LAG_T lag_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u panel_id: %u start.\n", __FUNCTION__,
-                                                   pf_info->slot, pf_info->vport, sdt_no, lag_id, panel_id);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u panel_id: %u start.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, lag_id,
+			panel_id);
 
-    ZXIC_COMM_MEMSET(&lag_entry, 0, sizeof(ZXDH_LAG_T));
+	ZXIC_COMM_MEMSET(&lag_entry, 0, sizeof(ZXDH_LAG_T));
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, lag_id, &lag_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
+	rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, lag_id, &lag_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
 
-    lag_entry.hit_flag = 1;
+	lag_entry.hit_flag = 1;
 
-    if ((lag_entry.member_bitmap & (1 << (15 - panel_id))) == 0)
-    {
-        lag_entry.member_bitmap |= (1 << (15 - panel_id));
-        lag_entry.member_num++;
-    }
+	if ((lag_entry.member_bitmap & (1 << (15 - panel_id))) == 0) {
+		lag_entry.member_bitmap |= (1 << (15 - panel_id));
+		lag_entry.member_num++;
+	}
 
-    rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, lag_id, &lag_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
+	rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, lag_id, &lag_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u panel_id: %u success.\n", __FUNCTION__,
-                                                     pf_info->slot, pf_info->vport, sdt_no, lag_id, panel_id);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u panel_id: %u success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, lag_id,
+			panel_id);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_lag_group_member_add);
 
-ZXIC_UINT32 dpp_lag_group_member_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 lag_id, ZXIC_UINT8 panel_id)
+ZXIC_UINT32 dpp_lag_group_member_del(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 lag_id,
+									 ZXIC_UINT8 panel_id)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_LAG_TABLE;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_LAG_T lag_entry = {0};
+	ZXDH_LAG_T lag_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u panel_id: %u start.\n", __FUNCTION__,
-                                                   pf_info->slot, pf_info->vport, sdt_no, lag_id, panel_id);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u panel_id: %u start.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, lag_id,
+			panel_id);
 
-    ZXIC_COMM_MEMSET(&lag_entry, 0, sizeof(ZXDH_LAG_T));
+	ZXIC_COMM_MEMSET(&lag_entry, 0, sizeof(ZXDH_LAG_T));
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, lag_id, &lag_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
+	rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, lag_id, &lag_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
 
-    lag_entry.hit_flag = 1;
+	lag_entry.hit_flag = 1;
 
-    if ((lag_entry.member_bitmap & (1 << (15 - panel_id))) != 0)
-    {
-        lag_entry.member_bitmap &= ~(1 << (15 - panel_id));
-        lag_entry.member_num--;
-    }
+	if ((lag_entry.member_bitmap & (1 << (15 - panel_id))) != 0) {
+		lag_entry.member_bitmap &= ~(1 << (15 - panel_id));
+		lag_entry.member_num--;
+	}
 
-    rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, lag_id, &lag_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
+	rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, lag_id, &lag_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u panel_id: %u success.\n", __FUNCTION__,
-                                                     pf_info->slot, pf_info->vport, sdt_no, lag_id, panel_id);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u lag_id: %u panel_id: %u success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, lag_id,
+			panel_id);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_lag_group_member_del);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_mac.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_mac.c
index ef2df77b13da253d94c2102caf7d4668fa15ed93..1935bfb2ab7c376c210d981895914a8b4170a0ba 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_mac.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_mac.c
@@ -14,243 +14,261 @@
 
 ZXIC_VOID dpp_l2_entry_print(ZXDH_L2_ENTRY_T *l2_entry)
 {
-    ZXIC_COMM_TRACE_INFO("key--mac: %02x:%02x:%02x:%02x:%02x:%02x.\n", 
-                               l2_entry->key.dmac_addr[0], l2_entry->key.dmac_addr[1],
-                               l2_entry->key.dmac_addr[2], l2_entry->key.dmac_addr[3],
-                               l2_entry->key.dmac_addr[4], l2_entry->key.dmac_addr[5]);
-    ZXIC_COMM_TRACE_INFO("key--rsv: 0x%02x\n", l2_entry->key.rsv);
-
-    ZXIC_COMM_TRACE_INFO("entry--vqm_vfid: 0x%02x\n", l2_entry->entry.vqm_vfid);
-    ZXIC_COMM_TRACE_INFO("entry--rsv: 0x%02x\n", l2_entry->entry.rsv);
-    ZXIC_COMM_TRACE_INFO("entry--hit_flag: 0x%02x\n", l2_entry->entry.hit_flag);
+	ZXIC_COMM_TRACE_INFO("key--mac: %02x:%02x:%02x:%02x:%02x:%02x.\n",
+						 l2_entry->key.dmac_addr[0], l2_entry->key.dmac_addr[1],
+						 l2_entry->key.dmac_addr[2], l2_entry->key.dmac_addr[3],
+						 l2_entry->key.dmac_addr[4],
+						 l2_entry->key.dmac_addr[5]);
+	ZXIC_COMM_TRACE_INFO("key--rsv: 0x%02x\n", l2_entry->key.rsv);
+
+	ZXIC_COMM_TRACE_INFO("entry--vqm_vfid: 0x%02x\n", l2_entry->entry.vqm_vfid);
+	ZXIC_COMM_TRACE_INFO("entry--rsv: 0x%02x\n", l2_entry->entry.rsv);
+	ZXIC_COMM_TRACE_INFO("entry--hit_flag: 0x%02x\n", l2_entry->entry.hit_flag);
 }
 
-ZXIC_UINT32 dpp_add_mac(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac)
+ZXIC_UINT32 dpp_add_mac(DPP_PF_INFO_T *pf_info, ZXIC_CONST ZXIC_VOID *mac)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id     = 0;
-    ZXIC_UINT32 queue      = 0;
-    ZXIC_UINT32 sdt_no     = 0;
-    ZXIC_UINT32 hash_index = 0;
-    ZXIC_UINT32 rc         = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = 0;
+	ZXIC_UINT32 hash_index = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_L2_ENTRY_T l2_entry = {0};
+	ZXDH_L2_ENTRY_T l2_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(mac);
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(mac);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    ZXIC_COMM_MEMSET(&l2_entry, 0, sizeof(ZXDH_L2_ENTRY_T));
+	ZXIC_COMM_MEMSET(&l2_entry, 0, sizeof(ZXDH_L2_ENTRY_T));
 
-    memmove(l2_entry.key.dmac_addr, mac, 6);
-    l2_entry.entry.vqm_vfid = VQM_VFID(pf_info->vport);
-    l2_entry.entry.hit_flag = 0x00;
+	memmove(l2_entry.key.dmac_addr, mac, 6);
+	l2_entry.entry.vqm_vfid = VQM_VFID(pf_info->vport);
+	l2_entry.entry.hit_flag = 0x00;
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_vport_hash_index_get(pf_info, &hash_index);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
+	rc = dpp_vport_hash_index_get(pf_info, &hash_index);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
 
-    sdt_no = ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 + hash_index;
+	sdt_no = ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 + hash_index;
 
-    rc = dpp_apt_dtb_hash_insert(&dev, queue, sdt_no, &l2_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_hash_insert");
+	rc = dpp_apt_dtb_hash_insert(&dev, queue, sdt_no, &l2_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_hash_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u vqm_vfid: %u mac: %02x:%02x:%02x:%02x:%02x:%02x.\n",
-                                                          __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no,
-                                                          l2_entry.entry.vqm_vfid,
-                                                          l2_entry.key.dmac_addr[0], l2_entry.key.dmac_addr[1],
-                                                          l2_entry.key.dmac_addr[2], l2_entry.key.dmac_addr[3],
-                                                          l2_entry.key.dmac_addr[4], l2_entry.key.dmac_addr[5]);
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
-    return DPP_OK;
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u vqm_vfid: %u mac: %02x:%02x:%02x:%02x:%02x:%02x.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no,
+			l2_entry.entry.vqm_vfid, l2_entry.key.dmac_addr[0],
+			l2_entry.key.dmac_addr[1], l2_entry.key.dmac_addr[2],
+			l2_entry.key.dmac_addr[3], l2_entry.key.dmac_addr[4],
+			l2_entry.key.dmac_addr[5]);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_add_mac);
 
-ZXIC_UINT32 dpp_del_mac(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac)
+ZXIC_UINT32 dpp_del_mac(DPP_PF_INFO_T *pf_info, ZXIC_CONST ZXIC_VOID *mac)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id     = 0;
-    ZXIC_UINT32 queue      = 0;
-    ZXIC_UINT32 sdt_no     = 0;
-    ZXIC_UINT32 hash_index = 0;
-    ZXIC_UINT32 rc         = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = 0;
+	ZXIC_UINT32 hash_index = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_L2_ENTRY_T l2_entry = {0};
+	ZXDH_L2_ENTRY_T l2_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(mac);
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(mac);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    ZXIC_COMM_MEMSET(&l2_entry, 0, sizeof(ZXDH_L2_ENTRY_T));
+	ZXIC_COMM_MEMSET(&l2_entry, 0, sizeof(ZXDH_L2_ENTRY_T));
 
-    memmove(l2_entry.key.dmac_addr, mac, 6);
+	memmove(l2_entry.key.dmac_addr, mac, 6);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_vport_hash_index_get(pf_info, &hash_index);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
+	rc = dpp_vport_hash_index_get(pf_info, &hash_index);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
 
-    sdt_no = ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 + hash_index;
+	sdt_no = ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 + hash_index;
 
-    rc = dpp_apt_dtb_hash_delete(&dev, queue, sdt_no, &l2_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_hash_delete");
+	rc = dpp_apt_dtb_hash_delete(&dev, queue, sdt_no, &l2_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_hash_delete");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u vqm_vfid: %u mac: %02x:%02x:%02x:%02x:%02x:%02x success.\n",
-                                                          __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no,
-                                                          l2_entry.entry.vqm_vfid,
-                                                          l2_entry.key.dmac_addr[0], l2_entry.key.dmac_addr[1],
-                                                          l2_entry.key.dmac_addr[2], l2_entry.key.dmac_addr[3],
-                                                          l2_entry.key.dmac_addr[4], l2_entry.key.dmac_addr[5]);
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
-    return DPP_OK;
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u vqm_vfid: %u mac: %02x:%02x:%02x:%02x:%02x:%02x success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no,
+			l2_entry.entry.vqm_vfid, l2_entry.key.dmac_addr[0],
+			l2_entry.key.dmac_addr[1], l2_entry.key.dmac_addr[2],
+			l2_entry.key.dmac_addr[3], l2_entry.key.dmac_addr[4],
+			l2_entry.key.dmac_addr[5]);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_del_mac);
 
-ZXIC_UINT32 dpp_unicast_mac_dump(DPP_PF_INFO_T* pf_info, MAC_VPORT_INFO *p_mac_arr, ZXIC_UINT32 *p_mac_num)
+ZXIC_UINT32 dpp_unicast_mac_dump(DPP_PF_INFO_T *pf_info,
+								 MAC_VPORT_INFO *p_mac_arr,
+								 ZXIC_UINT32 *p_mac_num)
 {
-    DPP_DEV_T dev = {0};
-
-    ZXIC_UINT32 rc     = DPP_OK;
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue_id  = 0;
-    ZXIC_UINT32 hash_index = 0;
-    ZXIC_UINT32 sdt_no = 0;
-    ZXIC_UINT32 current_vqm_vfid = 0;
-    ZXIC_UINT16 current_vport = 0;
-
-    ZXIC_UINT32 max_item_num = DTB_DUMP_UNICAST_MAC_DUMP_NUM;
-    ZXIC_UINT32 entryNum = 0;
-    ZXDH_L2_ENTRY_T *pL2DataArr = NULL;
-    ZXDH_L2_ENTRY_T *p_l2_temp_entry = NULL;
-    MAC_VPORT_INFO *p_temp_mac_info = NULL;
-
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(p_mac_arr);
-    ZXIC_COMM_CHECK_POINT(p_mac_num);
-
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
-
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
-
-    rc = dpp_vport_hash_index_get(pf_info, &hash_index);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
-
-    sdt_no = ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 + hash_index;
-
-    pL2DataArr = (ZXDH_L2_ENTRY_T *)ZXIC_COMM_MALLOC(max_item_num * sizeof(ZXDH_L2_ENTRY_T));
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(pL2DataArr);
-    
-    rc = dpp_apt_dtb_hash_table_unicast_mac_dump(&dev, queue_id, sdt_no, pL2DataArr, &entryNum);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_apt_dtb_hash_table_unicast_mac_dump", pL2DataArr);
-
-    ZXIC_COMM_TRACE_INFO("unicast mac dump num:0x%x\n", entryNum);
-
-    for(index = 0; index < entryNum; index ++)
-    {
-        p_l2_temp_entry = pL2DataArr + index;
-        p_temp_mac_info = p_mac_arr + index;
-
-        ZXIC_COMM_TRACE_INFO("l2 entry index:0x%x\n", index);
-        dpp_l2_entry_print(p_l2_temp_entry);
-
-        //从l2中获取mac地址给mac_info，再转换vport信息
-        ZXIC_COMM_MEMCPY(p_temp_mac_info->addr, p_l2_temp_entry->key.dmac_addr, 6);
-        current_vqm_vfid = p_l2_temp_entry->entry.vqm_vfid;
-
-        rc = dpp_vport_get_by_vqm_vfid(OWNER_PF_VPORT(pf_info->vport),  current_vqm_vfid, &current_vport);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_vport_get_by_vqm_vfid", pL2DataArr);
-        p_temp_mac_info->vport = current_vport;
-        ZXIC_COMM_TRACE_INFO("current_vqm_vfid:0x%x --> current_vport:0x%x\n", current_vqm_vfid, current_vport);
-    }
-
-    *p_mac_num = entryNum;
-
-    ZXIC_COMM_FREE(pL2DataArr);
-    return DPP_OK;
+	DPP_DEV_T dev = { 0 };
+
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue_id = 0;
+	ZXIC_UINT32 hash_index = 0;
+	ZXIC_UINT32 sdt_no = 0;
+	ZXIC_UINT32 current_vqm_vfid = 0;
+	ZXIC_UINT16 current_vport = 0;
+
+	ZXIC_UINT32 max_item_num = DTB_DUMP_UNICAST_MAC_DUMP_NUM;
+	ZXIC_UINT32 entryNum = 0;
+	ZXDH_L2_ENTRY_T *pL2DataArr = NULL;
+	ZXDH_L2_ENTRY_T *p_l2_temp_entry = NULL;
+	MAC_VPORT_INFO *p_temp_mac_info = NULL;
+
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(p_mac_arr);
+	ZXIC_COMM_CHECK_POINT(p_mac_num);
+
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+
+	rc = dpp_vport_hash_index_get(pf_info, &hash_index);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
+
+	sdt_no = ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 + hash_index;
+
+	pL2DataArr = (ZXDH_L2_ENTRY_T *)ZXIC_COMM_MALLOC(max_item_num *
+													 sizeof(ZXDH_L2_ENTRY_T));
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(pL2DataArr);
+
+	rc = dpp_apt_dtb_hash_table_unicast_mac_dump(&dev, queue_id, sdt_no,
+												 pL2DataArr, &entryNum);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+			rc, "dpp_apt_dtb_hash_table_unicast_mac_dump", pL2DataArr);
+
+	ZXIC_COMM_TRACE_INFO("unicast mac dump num:0x%x\n", entryNum);
+
+	for (index = 0; index < entryNum; index++) {
+		p_l2_temp_entry = pL2DataArr + index;
+		p_temp_mac_info = p_mac_arr + index;
+
+		ZXIC_COMM_TRACE_INFO("l2 entry index:0x%x\n", index);
+		dpp_l2_entry_print(p_l2_temp_entry);
+
+		//从l2中获取mac地址给mac_info，再转换vport信息
+		ZXIC_COMM_MEMCPY(p_temp_mac_info->addr, p_l2_temp_entry->key.dmac_addr,
+						 6);
+		current_vqm_vfid = p_l2_temp_entry->entry.vqm_vfid;
+
+		rc = dpp_vport_get_by_vqm_vfid(OWNER_PF_VPORT(pf_info->vport),
+									   current_vqm_vfid, &current_vport);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+				rc, "dpp_vport_get_by_vqm_vfid", pL2DataArr);
+		p_temp_mac_info->vport = current_vport;
+		ZXIC_COMM_TRACE_INFO("current_vqm_vfid:0x%x --> current_vport:0x%x\n",
+							 current_vqm_vfid, current_vport);
+	}
+
+	*p_mac_num = entryNum;
+
+	ZXIC_COMM_FREE(pL2DataArr);
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_unicast_mac_dump);
 
-ZXIC_UINT32 dpp_unicast_all_mac_delete(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_unicast_all_mac_delete(DPP_PF_INFO_T *pf_info)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 rc = DPP_OK;
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue_id  = 0;
-    ZXIC_UINT32 sdt_no = 0;
-    ZXIC_UINT32 hash_index = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue_id = 0;
+	ZXIC_UINT32 sdt_no = 0;
+	ZXIC_UINT32 hash_index = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_vport_hash_index_get(pf_info, &hash_index);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
+	rc = dpp_vport_hash_index_get(pf_info, &hash_index);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
 
-    sdt_no = ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 + hash_index;
+	sdt_no = ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 + hash_index;
 
-    rc = dpp_dtb_hash_offline_delete(&dev, queue_id, sdt_no);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_hash_offline_delete");
+	rc = dpp_dtb_hash_offline_delete(&dev, queue_id, sdt_no);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_hash_offline_delete");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_unicast_all_mac_delete);
 
-ZXIC_UINT32 dpp_unicast_all_mac_online_delete(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_unicast_all_mac_online_delete(DPP_PF_INFO_T *pf_info)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 rc = DPP_OK;
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue_id  = 0;
-    ZXIC_UINT32 sdt_no = 0;
-    ZXIC_UINT32 hash_index = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue_id = 0;
+	ZXIC_UINT32 sdt_no = 0;
+	ZXIC_UINT32 hash_index = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_vport_hash_index_get(pf_info, &hash_index);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
+	rc = dpp_vport_hash_index_get(pf_info, &hash_index);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
 
-    sdt_no = ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 + hash_index;
+	sdt_no = ZXDH_SDT_L2_ENTRY_TABLE_PHYPORT0 + hash_index;
 
-    rc = dpp_dtb_hash_online_delete(&dev, queue_id, sdt_no);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_hash_online_delete");
+	rc = dpp_dtb_hash_online_delete(&dev, queue_id, sdt_no);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_hash_online_delete");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_unicast_all_mac_online_delete);
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_mc.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_mc.c
index d3d142319d333d6eb72d049b597a0e4d3f6720f2..59fd44e6857e3d1d0c6acfb5ff2a066cdbcda59e 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_mc.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_mc.c
@@ -15,477 +15,492 @@
 
 ZXIC_VOID dpp_mc_entry_print(ZXDH_MC_T *mc_entry)
 {
-    ZXIC_COMM_TRACE_INFO("key--mc_mac: %02x:%02x:%02x:%02x:%02x:%02x.\n", 
-                               mc_entry->key.mc_mac[0], mc_entry->key.mc_mac[1],
-                               mc_entry->key.mc_mac[2], mc_entry->key.mc_mac[3],
-                               mc_entry->key.mc_mac[4], mc_entry->key.mc_mac[5]);
-    ZXIC_COMM_TRACE_INFO("key--group_id: 0x%02x\n", mc_entry->key.group_id);
-    ZXIC_COMM_TRACE_INFO("key--rsv: 0x%02x\n", mc_entry->key.rsv);
-
-    ZXIC_COMM_TRACE_INFO("entry--mc_bitmap: 0x%016llx\n", mc_entry->entry.mc_bitmap);
-    ZXIC_COMM_TRACE_INFO("entry--rsv2: 0x%02x\n", mc_entry->entry.rsv2);
-    ZXIC_COMM_TRACE_INFO("entry--rsv1: 0x%02x\n", mc_entry->entry.rsv1);
-    ZXIC_COMM_TRACE_INFO("entry--mc_pf_enable: 0x%02x\n", mc_entry->entry.mc_pf_enable);
-    ZXIC_COMM_TRACE_INFO("entry--hit_flag: 0x%02x\n", mc_entry->entry.hit_flag);
+	ZXIC_COMM_TRACE_INFO("key--mc_mac: %02x:%02x:%02x:%02x:%02x:%02x.\n",
+						 mc_entry->key.mc_mac[0], mc_entry->key.mc_mac[1],
+						 mc_entry->key.mc_mac[2], mc_entry->key.mc_mac[3],
+						 mc_entry->key.mc_mac[4], mc_entry->key.mc_mac[5]);
+	ZXIC_COMM_TRACE_INFO("key--group_id: 0x%02x\n", mc_entry->key.group_id);
+	ZXIC_COMM_TRACE_INFO("key--rsv: 0x%02x\n", mc_entry->key.rsv);
+
+	ZXIC_COMM_TRACE_INFO("entry--mc_bitmap: 0x%016llx\n",
+						 mc_entry->entry.mc_bitmap);
+	ZXIC_COMM_TRACE_INFO("entry--rsv2: 0x%02x\n", mc_entry->entry.rsv2);
+	ZXIC_COMM_TRACE_INFO("entry--rsv1: 0x%02x\n", mc_entry->entry.rsv1);
+	ZXIC_COMM_TRACE_INFO("entry--mc_pf_enable: 0x%02x\n",
+						 mc_entry->entry.mc_pf_enable);
+	ZXIC_COMM_TRACE_INFO("entry--hit_flag: 0x%02x\n", mc_entry->entry.hit_flag);
 }
 
-ZXIC_UINT32 dpp_vport_mc_info_add(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac)
+ZXIC_UINT32 dpp_vport_mc_info_add(DPP_PF_INFO_T *pf_info,
+								  ZXIC_CONST ZXIC_VOID *mac)
 {
-    ZXIC_UINT32 index     = 0;
-    ZXIC_UINT32 group_id  = 0;
-    ZXIC_UINT32 vfunc_num = 0;
-    ZXIC_UINT32 rc        = DPP_OK;
-
-    DPP_VPORT_MC_TABLE_T* mc_table = NULL;
-
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(mac);
-
-    rc = dpp_vport_mc_table_get(pf_info, &mc_table);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_table_get");
-    ZXIC_COMM_CHECK_POINT(mc_table);
-
-    vfunc_num = VFUNC_NUM(pf_info->vport);
-    ZXIC_COMM_CHECK_INDEX(vfunc_num, 0, (MC_GROUP_NUM * MC_MEMBER_NUM_IN_GROUP) - 1);
-
-    group_id  = vfunc_num / MC_MEMBER_NUM_IN_GROUP;
-    ZXIC_COMM_CHECK_INDEX(group_id, 0, MC_GROUP_NUM - 1);
-
-    for (index = 0; index < MC_TABLE_SIZE; index++)
-    {
-        if (mc_table->mc_info[index].is_valid == 0)
-        {
-            continue;
-        }
-        if (ZXIC_COMM_MEMCMP(mc_table->mc_info[index].mac, mac, 6) == 0)
-        {
-            if (IS_PF(pf_info->vport))
-            {
-                mc_table->mc_info[index].mc_pf_enable = 1;
-            }
-            else
-            {
-                mc_table->mc_info[index].mc_bitmap[group_id] |= ((ZXIC_UINT64)(1) << (MC_MEMBER_NUM_IN_GROUP - 1 -
-                                                                                 (vfunc_num % MC_MEMBER_NUM_IN_GROUP)));
-            }
-            return DPP_OK;
-        }
-    }
-
-    for (index = 0; index < MC_TABLE_SIZE; index++)
-    {
-        if (mc_table->mc_info[index].is_valid == 1)
-        {
-            continue;
-        }
-        mc_table->mc_info[index].is_valid = 1;
-        memmove(mc_table->mc_info[index].mac, mac, 6);
-
-        if (IS_PF(pf_info->vport))
-        {
-            mc_table->mc_info[index].mc_pf_enable = 1;
-        }
-        else
-        {
-            mc_table->mc_info[index].mc_bitmap[group_id] |= ((ZXIC_UINT64)(1) << (MC_MEMBER_NUM_IN_GROUP - 1 -
-                                                                             (vfunc_num % MC_MEMBER_NUM_IN_GROUP)));
-        }
-
-        return DPP_OK;
-    }
-
-    return DPP_RC_TABLE_RANGE_INVALID;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 group_id = 0;
+	ZXIC_UINT32 vfunc_num = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	DPP_VPORT_MC_TABLE_T *mc_table = NULL;
+
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(mac);
+
+	rc = dpp_vport_mc_table_get(pf_info, &mc_table);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_table_get");
+	ZXIC_COMM_CHECK_POINT(mc_table);
+
+	vfunc_num = VFUNC_NUM(pf_info->vport);
+	ZXIC_COMM_CHECK_INDEX(vfunc_num, 0,
+						  MC_GROUP_NUM * MC_MEMBER_NUM_IN_GROUP - 1);
+
+	group_id = vfunc_num / MC_MEMBER_NUM_IN_GROUP;
+	ZXIC_COMM_CHECK_INDEX(group_id, 0, MC_GROUP_NUM - 1);
+
+	for (index = 0; index < MC_TABLE_SIZE; index++) {
+		if (mc_table->mc_info[index].is_valid == 0) {
+			continue;
+		}
+		if (ZXIC_COMM_MEMCMP(mc_table->mc_info[index].mac, mac, 6) == 0) {
+			if (IS_PF(pf_info->vport)) {
+				mc_table->mc_info[index].mc_pf_enable = 1;
+			} else {
+				mc_table->mc_info[index].mc_bitmap[group_id] |=
+						((ZXIC_UINT64)(1)
+						 << (MC_MEMBER_NUM_IN_GROUP - 1 -
+							 (vfunc_num % MC_MEMBER_NUM_IN_GROUP)));
+			}
+			return DPP_OK;
+		}
+	}
+
+	for (index = 0; index < MC_TABLE_SIZE; index++) {
+		if (mc_table->mc_info[index].is_valid == 1) {
+			continue;
+		}
+		mc_table->mc_info[index].is_valid = 1;
+		memmove(mc_table->mc_info[index].mac, mac, 6);
+
+		if (IS_PF(pf_info->vport)) {
+			mc_table->mc_info[index].mc_pf_enable = 1;
+		} else {
+			mc_table->mc_info[index].mc_bitmap[group_id] |=
+					((ZXIC_UINT64)(1)
+					 << (MC_MEMBER_NUM_IN_GROUP - 1 -
+						 (vfunc_num % MC_MEMBER_NUM_IN_GROUP)));
+		}
+
+		return DPP_OK;
+	}
+
+	return DPP_ERR;
 }
 
-ZXIC_UINT32 dpp_vport_mc_info_del(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac)
+ZXIC_UINT32 dpp_vport_mc_info_del(DPP_PF_INFO_T *pf_info,
+								  ZXIC_CONST ZXIC_VOID *mac)
 {
-    ZXIC_UINT32 index     = 0;
-    ZXIC_UINT32 group_id  = 0;
-    ZXIC_UINT32 vfunc_num = 0;
-    ZXIC_UINT32 rc        = DPP_OK;
-
-    DPP_VPORT_MC_TABLE_T* mc_table = NULL;
-
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(mac);
-
-    rc = dpp_vport_mc_table_get(pf_info, &mc_table);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_table_get");
-    ZXIC_COMM_CHECK_POINT(mc_table);
-
-    vfunc_num = VFUNC_NUM(pf_info->vport);
-    ZXIC_COMM_CHECK_INDEX(vfunc_num, 0, (MC_GROUP_NUM * MC_MEMBER_NUM_IN_GROUP) - 1);
-
-    group_id  = vfunc_num / MC_MEMBER_NUM_IN_GROUP;
-    ZXIC_COMM_CHECK_INDEX(group_id, 0, MC_GROUP_NUM - 1);
-
-    for (index = 0; index < MC_TABLE_SIZE; index++)
-    {
-        if (mc_table->mc_info[index].is_valid == 0)
-        {
-            continue;
-        }
-        if (ZXIC_COMM_MEMCMP(mc_table->mc_info[index].mac, mac, 6) == 0)
-        {
-            if (IS_PF(pf_info->vport))
-            {
-                mc_table->mc_info[index].mc_pf_enable = 0;
-            }
-            else
-            {
-                mc_table->mc_info[index].mc_bitmap[group_id] &= ~((ZXIC_UINT64)(1) << (MC_MEMBER_NUM_IN_GROUP - 1 -
-                                                                                  (vfunc_num % MC_MEMBER_NUM_IN_GROUP)));
-            }
-
-            if ((mc_table->mc_info[index].mc_bitmap[0] == 0) && (mc_table->mc_info[index].mc_bitmap[1] == 0) &&
-                (mc_table->mc_info[index].mc_bitmap[2] == 0) && (mc_table->mc_info[index].mc_bitmap[3] == 0) &&
-                (mc_table->mc_info[index].mc_pf_enable == 0))
-            {
-                mc_table->mc_info[index].is_valid = 0;
-                ZXIC_COMM_MEMSET(mc_table->mc_info[index].mac, 0x00, 6);
-            }
-
-            return DPP_OK;
-        }
-    }
-
-    return DPP_OK;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 group_id = 0;
+	ZXIC_UINT32 vfunc_num = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	DPP_VPORT_MC_TABLE_T *mc_table = NULL;
+
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(mac);
+
+	rc = dpp_vport_mc_table_get(pf_info, &mc_table);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_table_get");
+	ZXIC_COMM_CHECK_POINT(mc_table);
+
+	vfunc_num = VFUNC_NUM(pf_info->vport);
+	ZXIC_COMM_CHECK_INDEX(vfunc_num, 0,
+						  MC_GROUP_NUM * MC_MEMBER_NUM_IN_GROUP - 1);
+
+	group_id = vfunc_num / MC_MEMBER_NUM_IN_GROUP;
+	ZXIC_COMM_CHECK_INDEX(group_id, 0, MC_GROUP_NUM - 1);
+
+	for (index = 0; index < MC_TABLE_SIZE; index++) {
+		if (mc_table->mc_info[index].is_valid == 0) {
+			continue;
+		}
+		if (ZXIC_COMM_MEMCMP(mc_table->mc_info[index].mac, mac, 6) == 0) {
+			if (IS_PF(pf_info->vport)) {
+				mc_table->mc_info[index].mc_pf_enable = 0;
+			} else {
+				mc_table->mc_info[index].mc_bitmap[group_id] &=
+						~((ZXIC_UINT64)(1)
+						  << (MC_MEMBER_NUM_IN_GROUP - 1 -
+							  (vfunc_num % MC_MEMBER_NUM_IN_GROUP)));
+			}
+
+			if (mc_table->mc_info[index].mc_bitmap[0] == 0 &&
+				mc_table->mc_info[index].mc_bitmap[1] == 0 &&
+				mc_table->mc_info[index].mc_bitmap[2] == 0 &&
+				mc_table->mc_info[index].mc_bitmap[3] == 0 &&
+				mc_table->mc_info[index].mc_pf_enable == 0) {
+				mc_table->mc_info[index].is_valid = 0;
+				ZXIC_COMM_MEMSET(mc_table->mc_info[index].mac, 0x00, 6);
+			}
+
+			return DPP_OK;
+		}
+	}
+
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_vport_mc_table_insert(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac)
+ZXIC_UINT32 dpp_vport_mc_table_insert(DPP_PF_INFO_T *pf_info,
+									  ZXIC_CONST ZXIC_VOID *mac)
 {
-    DPP_DEV_T dev = {0};
-
-    ZXIC_UINT32 index      = 0;
-    ZXIC_UINT32 dev_id     = 0;
-    ZXIC_UINT32 sdt_no     = 0;
-    ZXIC_UINT32 queue      = 0;
-    ZXIC_UINT32 group_id   = 0;
-    ZXIC_UINT32 hash_index = 0;
-    ZXIC_UINT32 rc         = DPP_OK;
-
-    ZXDH_MC_T mc_entry = {0};
-    DPP_VPORT_MC_TABLE_T* mc_table = NULL;
-
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(mac);
-
-    ZXIC_COMM_MEMSET(&mc_entry, 0, sizeof(ZXDH_MC_T));
-
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
-
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
-
-    rc = dpp_vport_hash_index_get(pf_info, &hash_index);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
-
-    sdt_no = ZXDH_SDT_MC_TABLE_PHYPORT0 + hash_index;
-
-    rc = dpp_vport_mc_table_get(pf_info, &mc_table);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_table_get");
-    ZXIC_COMM_CHECK_POINT(mc_table);
-
-    for (index = 0; index < MC_TABLE_SIZE; index++)
-    {
-        if (mc_table->mc_info[index].is_valid == 0)
-        {
-            continue;
-        }
-        if (ZXIC_COMM_MEMCMP(mc_table->mc_info[index].mac, mac, 6) != 0)
-        {
-            continue;
-        }
-        for (group_id = 0; group_id < MC_GROUP_NUM; group_id++)
-        {
-            memmove(mc_entry.key.mc_mac, mac, 6);
-            mc_entry.key.group_id = group_id;
-            mc_entry.entry.hit_flag = 0x00;
-            mc_entry.entry.mc_pf_enable = mc_table->mc_info[index].mc_pf_enable;
-            mc_entry.entry.mc_bitmap = mc_table->mc_info[index].mc_bitmap[group_id];
-
-            rc = dpp_apt_dtb_hash_insert(&dev, queue, sdt_no, &mc_entry);
-            ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_hash_insert");
-
-            ZXIC_COMM_PRINT("[%s] slot %u vport: 0x%04x sdt_no: %u group_id: %u.\n",
-                                                __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, group_id);
-            ZXIC_COMM_PRINT("[%s] mac: %02x:%02x:%02x:%02x:%02x:%02x.\n", __FUNCTION__,
-                                                                mc_entry.key.mc_mac[0], mc_entry.key.mc_mac[1],
-                                                                mc_entry.key.mc_mac[2], mc_entry.key.mc_mac[3],
-                                                                mc_entry.key.mc_mac[4], mc_entry.key.mc_mac[5]);
-            ZXIC_COMM_PRINT("[%s] mc_bitmap: %02x %02x %02x %02x %02x %02x %02x %02x.\n", __FUNCTION__,
-                                                                *((ZXIC_UINT8*)(&mc_entry.entry.mc_bitmap) + 7),
-                                                                *((ZXIC_UINT8*)(&mc_entry.entry.mc_bitmap) + 6),
-                                                                *((ZXIC_UINT8*)(&mc_entry.entry.mc_bitmap) + 5),
-                                                                *((ZXIC_UINT8*)(&mc_entry.entry.mc_bitmap) + 4),
-                                                                *((ZXIC_UINT8*)(&mc_entry.entry.mc_bitmap) + 3),
-                                                                *((ZXIC_UINT8*)(&mc_entry.entry.mc_bitmap) + 2),
-                                                                *((ZXIC_UINT8*)(&mc_entry.entry.mc_bitmap) + 1),
-                                                                *((ZXIC_UINT8*)(&mc_entry.entry.mc_bitmap) + 0));
-        }
-        return DPP_OK;
-    }
-
-    for (group_id = 0; group_id < MC_GROUP_NUM; group_id++)
-    {
-        memmove(mc_entry.key.mc_mac, mac, 6);
-        mc_entry.key.group_id = group_id;
-
-        rc = dpp_apt_dtb_hash_delete(&dev, queue, sdt_no, &mc_entry);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_hash_insert");
-
-        ZXIC_COMM_PRINT("[%s] delete mc table.\n", __FUNCTION__);
-        ZXIC_COMM_PRINT("[%s] slot %u vport: 0x%04x sdt_no: %u group_id: %u.\n",
-                                                __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, group_id);
-        ZXIC_COMM_PRINT("[%s] mac: %02x:%02x:%02x:%02x:%02x:%02x.\n", __FUNCTION__,
-                                                                mc_entry.key.mc_mac[0], mc_entry.key.mc_mac[1],
-                                                                mc_entry.key.mc_mac[2], mc_entry.key.mc_mac[3],
-                                                                mc_entry.key.mc_mac[4], mc_entry.key.mc_mac[5]);
-    }
-
-    return DPP_OK;
+	DPP_DEV_T dev = { 0 };
+
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 sdt_no = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 group_id = 0;
+	ZXIC_UINT32 hash_index = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	ZXDH_MC_T mc_entry = { 0 };
+	DPP_VPORT_MC_TABLE_T *mc_table = NULL;
+
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(mac);
+
+	ZXIC_COMM_MEMSET(&mc_entry, 0, sizeof(ZXDH_MC_T));
+
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+
+	rc = dpp_vport_hash_index_get(pf_info, &hash_index);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
+
+	sdt_no = ZXDH_SDT_MC_TABLE_PHYPORT0 + hash_index;
+
+	rc = dpp_vport_mc_table_get(pf_info, &mc_table);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_table_get");
+	ZXIC_COMM_CHECK_POINT(mc_table);
+
+	for (index = 0; index < MC_TABLE_SIZE; index++) {
+		if (mc_table->mc_info[index].is_valid == 0) {
+			continue;
+		}
+		if (ZXIC_COMM_MEMCMP(mc_table->mc_info[index].mac, mac, 6) != 0) {
+			continue;
+		}
+		for (group_id = 0; group_id < MC_GROUP_NUM; group_id++) {
+			memmove(mc_entry.key.mc_mac, mac, 6);
+			mc_entry.key.group_id = group_id;
+			mc_entry.entry.hit_flag = 0x00;
+			mc_entry.entry.mc_pf_enable = mc_table->mc_info[index].mc_pf_enable;
+			mc_entry.entry.mc_bitmap =
+					mc_table->mc_info[index].mc_bitmap[group_id];
+
+			rc = dpp_apt_dtb_hash_insert(&dev, queue, sdt_no, &mc_entry);
+			ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_hash_insert");
+
+			ZXIC_COMM_PRINT(
+					"[%s] slot %u vport: 0x%04x sdt_no: %u group_id: %u.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no,
+					group_id);
+			ZXIC_COMM_PRINT("[%s] mac: %02x:%02x:%02x:%02x:%02x:%02x.\n",
+							__FUNCTION__, mc_entry.key.mc_mac[0],
+							mc_entry.key.mc_mac[1], mc_entry.key.mc_mac[2],
+							mc_entry.key.mc_mac[3], mc_entry.key.mc_mac[4],
+							mc_entry.key.mc_mac[5]);
+			ZXIC_COMM_PRINT(
+					"[%s] mc_bitmap: %02x %02x %02x %02x %02x %02x %02x %02x.\n",
+					__FUNCTION__,
+					*((ZXIC_UINT8 *)(&mc_entry.entry.mc_bitmap) + 7),
+					*((ZXIC_UINT8 *)(&mc_entry.entry.mc_bitmap) + 6),
+					*((ZXIC_UINT8 *)(&mc_entry.entry.mc_bitmap) + 5),
+					*((ZXIC_UINT8 *)(&mc_entry.entry.mc_bitmap) + 4),
+					*((ZXIC_UINT8 *)(&mc_entry.entry.mc_bitmap) + 3),
+					*((ZXIC_UINT8 *)(&mc_entry.entry.mc_bitmap) + 2),
+					*((ZXIC_UINT8 *)(&mc_entry.entry.mc_bitmap) + 1),
+					*((ZXIC_UINT8 *)(&mc_entry.entry.mc_bitmap) + 0));
+		}
+		return DPP_OK;
+	}
+
+	for (group_id = 0; group_id < MC_GROUP_NUM; group_id++) {
+		memmove(mc_entry.key.mc_mac, mac, 6);
+		mc_entry.key.group_id = group_id;
+
+		rc = dpp_apt_dtb_hash_delete(&dev, queue, sdt_no, &mc_entry);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_hash_insert");
+
+		ZXIC_COMM_PRINT("[%s] delete mc table.\n", __FUNCTION__);
+		ZXIC_COMM_PRINT("[%s] slot %u vport: 0x%04x sdt_no: %u group_id: %u.\n",
+						__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no,
+						group_id);
+		ZXIC_COMM_PRINT("[%s] mac: %02x:%02x:%02x:%02x:%02x:%02x.\n",
+						__FUNCTION__, mc_entry.key.mc_mac[0],
+						mc_entry.key.mc_mac[1], mc_entry.key.mc_mac[2],
+						mc_entry.key.mc_mac[3], mc_entry.key.mc_mac[4],
+						mc_entry.key.mc_mac[5]);
+	}
+
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_multi_mac_add_member(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac)
+ZXIC_UINT32 dpp_multi_mac_add_member(DPP_PF_INFO_T *pf_info,
+									 ZXIC_CONST ZXIC_VOID *mac)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    rc = dpp_vport_mc_info_add(pf_info, mac);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_info_add");
+	rc = dpp_vport_mc_info_add(pf_info, mac);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_info_add");
 
-    rc = dpp_vport_mc_table_insert(pf_info, mac);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_table_insert");
-    
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	rc = dpp_vport_mc_table_insert(pf_info, mac);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_table_insert");
 
-    return DPP_OK;
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
+
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_multi_mac_add_member);
 
-ZXIC_UINT32 dpp_multi_mac_del_member(DPP_PF_INFO_T* pf_info, ZXIC_CONST ZXIC_VOID *mac)
+ZXIC_UINT32 dpp_multi_mac_del_member(DPP_PF_INFO_T *pf_info,
+									 ZXIC_CONST ZXIC_VOID *mac)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    rc = dpp_vport_mc_info_del(pf_info, mac);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_info_del");
+	rc = dpp_vport_mc_info_del(pf_info, mac);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_info_del");
 
-    rc = dpp_vport_mc_table_insert(pf_info, mac);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_table_insert");
+	rc = dpp_vport_mc_table_insert(pf_info, mac);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_table_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_multi_mac_del_member);
 
-ZXIC_UINT32 dpp_mc_pf_flag_add(MC_PF_FLAG_MGR * p_flag_mgr, ZXIC_UINT32 index, ZXIC_UINT8 *mc_addr)
+ZXIC_UINT32 dpp_mc_pf_flag_add(MC_PF_FLAG_MGR *p_flag_mgr, ZXIC_UINT32 index,
+							   ZXIC_UINT8 *mc_addr)
 {
-    ZXIC_COMM_MEMCPY(p_flag_mgr[index].mc_addr, mc_addr, 6);
-    p_flag_mgr[index].pf_flag = 1;
-    return DPP_OK;
+	ZXIC_COMM_MEMCPY(p_flag_mgr[index].mc_addr, mc_addr, 6);
+	p_flag_mgr[index].pf_flag = 1;
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_mc_pf_flag_search(MC_PF_FLAG_MGR * p_flag_mgr, ZXIC_UINT8 *mc_addr)
+ZXIC_UINT32 dpp_mc_pf_flag_search(MC_PF_FLAG_MGR *p_flag_mgr,
+								  ZXIC_UINT8 *mc_addr)
 {
-    ZXIC_UINT32 index = 0;
-
-    for(index = 0; index < MC_TABLE_SIZE; index ++)
-    {
-        if (ZXIC_COMM_MEMCMP(p_flag_mgr[index].mc_addr, mc_addr, 6) == 0)
-        {
-            break;
-        }
-    }
-
-    if (index == MC_TABLE_SIZE)
-    {
-        ZXIC_COMM_TRACE_INFO("dpp_mc_pf_flag_search failed\n");
-        return DPP_ERR;
-    }
-
-    return DPP_OK;
+	ZXIC_UINT32 index = 0;
+
+	for (index = 0; index < MC_TABLE_SIZE; index++) {
+		if (ZXIC_COMM_MEMCMP(p_flag_mgr[index].mc_addr, mc_addr, 6) == 0) {
+			break;
+		}
+	}
+
+	if (index == MC_TABLE_SIZE) {
+		ZXIC_COMM_TRACE_INFO("dpp_mc_pf_flag_search failed\n");
+		return DPP_ERR;
+	}
+
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_multicast_mac_dump(DPP_PF_INFO_T* pf_info, MAC_VPORT_INFO *p_mac_arr, ZXIC_UINT32 *p_mac_num)
+ZXIC_UINT32 dpp_multicast_mac_dump(DPP_PF_INFO_T *pf_info,
+								   MAC_VPORT_INFO *p_mac_arr,
+								   ZXIC_UINT32 *p_mac_num)
 {
-    DPP_DEV_T dev = {0};
-
-    ZXIC_UINT32 rc     = DPP_OK;
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT32 mac_info_index = 0;
-    ZXIC_UINT32 num = 0;
-    
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue_id  = 0;
-    ZXIC_UINT32 sdt_no   = 0;
-    ZXIC_UINT32 hash_index = 0;
-    ZXIC_UINT32 current_group_id = 0;
-    ZXIC_UINT64 current_mc_bitmap = 0;
-    ZXIC_UINT32 current_mc_pf_enable = 0;
-
-    ZXIC_UINT16 current_vport[64] = {0};
-    ZXIC_UINT32 current_vport_num = 0;
-
-    MC_PF_FLAG_MGR mc_pf_flag_mgr[MC_TABLE_SIZE] = {0};
-    ZXIC_UINT32 pf_flag_count = 0;
-    
-    ZXIC_UINT32 max_item_num = DTB_DUMP_MULTICAST_MAC_DUMP_NUM;
-    ZXIC_UINT32 entryNum = 0;
-    
-    ZXDH_MC_T *pMcDataArr = NULL;
-    ZXDH_MC_T *p_mc_temp_entry = NULL;
-    MAC_VPORT_INFO *p_temp_mac_info = NULL;
-
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(p_mac_arr);
-    ZXIC_COMM_CHECK_POINT(p_mac_num);
-
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
-
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
-
-    rc = dpp_vport_hash_index_get(pf_info, &hash_index);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
-
-    sdt_no = ZXDH_SDT_MC_TABLE_PHYPORT0 + hash_index;
-
-    pMcDataArr = (ZXDH_MC_T *)ZXIC_COMM_MALLOC(max_item_num * sizeof(ZXDH_MC_T));
-    ZXIC_COMM_CHECK_POINT_NO_ASSERT(pMcDataArr);
-
-    rc = dpp_apt_dtb_hash_table_multicast_mac_dump(&dev, queue_id, sdt_no, pMcDataArr, &entryNum);
-    ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_apt_dtb_hash_table_multicast_mac_dump", pMcDataArr);
-
-    ZXIC_COMM_TRACE_INFO("multicast mac dump num:0x%x\n", entryNum);
-
-    for(index = 0; index < entryNum; index ++)
-    {
-        p_mc_temp_entry = pMcDataArr + index;
-        
-        ZXIC_COMM_TRACE_INFO("mc entry index:0x%x\n", index);
-        dpp_mc_entry_print(p_mc_temp_entry);
-
-        // 从mc中获取mac地址给mac_info，再转换group_id 和 bitmap信息
-        current_group_id = p_mc_temp_entry->key.group_id;
-        current_mc_bitmap = p_mc_temp_entry->entry.mc_bitmap;
-        current_mc_pf_enable = p_mc_temp_entry->entry.mc_pf_enable;
-
-        if(current_mc_pf_enable)
-        {
-            p_temp_mac_info = p_mac_arr + mac_info_index;
-            if(dpp_mc_pf_flag_search(mc_pf_flag_mgr, p_mc_temp_entry->key.mc_mac))
-            {
-                //没差中
-                dpp_mc_pf_flag_add(mc_pf_flag_mgr, pf_flag_count, p_mc_temp_entry->key.mc_mac);
-                pf_flag_count++;
-
-                ZXIC_COMM_MEMCPY(p_temp_mac_info->addr, p_mc_temp_entry->key.mc_mac, 6);
-                p_temp_mac_info->vport = OWNER_PF_VPORT(pf_info->vport);
-
-                mac_info_index = mac_info_index + 1;
-            }
-        }
-
-        rc = dpp_vport_get_by_mc_bitmap(OWNER_PF_VPORT(pf_info->vport), current_group_id, current_mc_bitmap, current_vport, &current_vport_num);
-        ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, "dpp_vport_get_by_mc_bitmap", pMcDataArr);
-
-        ZXIC_COMM_TRACE_INFO("index %d get vf num %d\n", index, current_vport_num);
-
-        for(num = 0; num < current_vport_num; num++)
-        {
-            p_temp_mac_info = p_mac_arr + mac_info_index;
-            ZXIC_COMM_MEMCPY(p_temp_mac_info->addr, p_mc_temp_entry->key.mc_mac, 6);
-            p_temp_mac_info->vport = current_vport[num];
-            mac_info_index = mac_info_index + 1;
-        }
-        ZXIC_COMM_TRACE_INFO("mac_info_index 0x%x\n", mac_info_index);
-
-    }
-
-    ZXIC_COMM_FREE(pMcDataArr);
-
-    *p_mac_num = mac_info_index;
-
-    ZXIC_COMM_TRACE_INFO("dump mac num: 0x%x\n", *p_mac_num);
-
-    return DPP_OK;
+	DPP_DEV_T dev = { 0 };
+
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 mac_info_index = 0;
+	ZXIC_UINT32 num = 0;
+
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue_id = 0;
+	ZXIC_UINT32 sdt_no = 0;
+	ZXIC_UINT32 hash_index = 0;
+	ZXIC_UINT32 current_group_id = 0;
+	ZXIC_UINT64 current_mc_bitmap = 0;
+	ZXIC_UINT32 current_mc_pf_enable = 0;
+
+	ZXIC_UINT16 current_vport[64] = { 0 };
+	ZXIC_UINT32 current_vport_num = 0;
+
+	MC_PF_FLAG_MGR mc_pf_flag_mgr[MC_TABLE_SIZE] = { 0 };
+	ZXIC_UINT32 pf_flag_count = 0;
+
+	ZXIC_UINT32 max_item_num = DTB_DUMP_MULTICAST_MAC_DUMP_NUM;
+	ZXIC_UINT32 entryNum = 0;
+
+	ZXDH_MC_T *pMcDataArr = NULL;
+	ZXDH_MC_T *p_mc_temp_entry = NULL;
+	MAC_VPORT_INFO *p_temp_mac_info = NULL;
+
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(p_mac_arr);
+	ZXIC_COMM_CHECK_POINT(p_mac_num);
+
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+
+	rc = dpp_vport_hash_index_get(pf_info, &hash_index);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
+
+	sdt_no = ZXDH_SDT_MC_TABLE_PHYPORT0 + hash_index;
+
+	pMcDataArr =
+			(ZXDH_MC_T *)ZXIC_COMM_MALLOC(max_item_num * sizeof(ZXDH_MC_T));
+	ZXIC_COMM_CHECK_POINT_NO_ASSERT(pMcDataArr);
+
+	rc = dpp_apt_dtb_hash_table_multicast_mac_dump(&dev, queue_id, sdt_no,
+												   pMcDataArr, &entryNum);
+	ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+			rc, "dpp_apt_dtb_hash_table_multicast_mac_dump", pMcDataArr);
+
+	ZXIC_COMM_TRACE_INFO("multicast mac dump num:0x%x\n", entryNum);
+
+	for (index = 0; index < entryNum; index++) {
+		p_mc_temp_entry = pMcDataArr + index;
+
+		ZXIC_COMM_TRACE_INFO("mc entry index:0x%x\n", index);
+		dpp_mc_entry_print(p_mc_temp_entry);
+
+		// 从mc中获取mac地址给mac_info，再转换group_id 和 bitmap信息
+		current_group_id = p_mc_temp_entry->key.group_id;
+		current_mc_bitmap = p_mc_temp_entry->entry.mc_bitmap;
+		current_mc_pf_enable = p_mc_temp_entry->entry.mc_pf_enable;
+
+		if (current_mc_pf_enable) {
+			p_temp_mac_info = p_mac_arr + mac_info_index;
+			if (dpp_mc_pf_flag_search(mc_pf_flag_mgr,
+									  p_mc_temp_entry->key.mc_mac)) {
+				//没差中
+				dpp_mc_pf_flag_add(mc_pf_flag_mgr, pf_flag_count,
+								   p_mc_temp_entry->key.mc_mac);
+				pf_flag_count++;
+
+				ZXIC_COMM_MEMCPY(p_temp_mac_info->addr,
+								 p_mc_temp_entry->key.mc_mac, 6);
+				p_temp_mac_info->vport = OWNER_PF_VPORT(pf_info->vport);
+
+				mac_info_index = mac_info_index + 1;
+			}
+		}
+
+		rc = dpp_vport_get_by_mc_bitmap(OWNER_PF_VPORT(pf_info->vport),
+										current_group_id, current_mc_bitmap,
+										current_vport, &current_vport_num);
+		ZXIC_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(
+				rc, "dpp_vport_get_by_mc_bitmap", pMcDataArr);
+
+		ZXIC_COMM_TRACE_INFO("index %d get vf num %d\n", index,
+							 current_vport_num);
+
+		for (num = 0; num < current_vport_num; num++) {
+			p_temp_mac_info = p_mac_arr + mac_info_index;
+			ZXIC_COMM_MEMCPY(p_temp_mac_info->addr, p_mc_temp_entry->key.mc_mac,
+							 6);
+			p_temp_mac_info->vport = current_vport[num];
+			mac_info_index = mac_info_index + 1;
+		}
+		ZXIC_COMM_TRACE_INFO("mac_info_index 0x%x\n", mac_info_index);
+	}
+
+	*p_mac_num = mac_info_index;
+
+	ZXIC_COMM_TRACE_INFO("dump mac num: 0x%x\n", *p_mac_num);
+
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_multicast_mac_dump);
 
-ZXIC_UINT32 dpp_multicast_all_mac_delete(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_multicast_all_mac_delete(DPP_PF_INFO_T *pf_info)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 rc = DPP_OK;
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue_id  = 0;
-    ZXIC_UINT32 sdt_no = 0;
-    ZXIC_UINT32 hash_index = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue_id = 0;
+	ZXIC_UINT32 sdt_no = 0;
+	ZXIC_UINT32 hash_index = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_vport_hash_index_get(pf_info, &hash_index);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
+	rc = dpp_vport_hash_index_get(pf_info, &hash_index);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
 
-    sdt_no = ZXDH_SDT_MC_TABLE_PHYPORT0 + hash_index;
+	sdt_no = ZXDH_SDT_MC_TABLE_PHYPORT0 + hash_index;
 
-    rc = dpp_dtb_hash_offline_delete(&dev, queue_id, sdt_no);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_hash_offline_delete");
+	rc = dpp_dtb_hash_offline_delete(&dev, queue_id, sdt_no);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_hash_offline_delete");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_multicast_all_mac_delete);
 
-ZXIC_UINT32 dpp_multicast_all_mac_online_delete(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_multicast_all_mac_online_delete(DPP_PF_INFO_T *pf_info)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 rc = DPP_OK;
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue_id  = 0;
-    ZXIC_UINT32 sdt_no = 0;
-    ZXIC_UINT32 hash_index = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue_id = 0;
+	ZXIC_UINT32 sdt_no = 0;
+	ZXIC_UINT32 hash_index = 0;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue_id);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_vport_hash_index_get(pf_info, &hash_index);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
+	rc = dpp_vport_hash_index_get(pf_info, &hash_index);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_hash_index_get");
 
-    sdt_no = ZXDH_SDT_MC_TABLE_PHYPORT0 + hash_index;
+	sdt_no = ZXDH_SDT_MC_TABLE_PHYPORT0 + hash_index;
 
-    rc = dpp_dtb_hash_online_delete(&dev, queue_id, sdt_no);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_hash_online_delete");
+	rc = dpp_dtb_hash_online_delete(&dev, queue_id, sdt_no);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_hash_online_delete");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_multicast_all_mac_online_delete);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_panel.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_panel.c
index 12f8c461ea99786e60b3e6c84de2f51b3679b104..df20badba38e864001bc0b59a790b421860981a3 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_panel.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_panel.c
@@ -14,122 +14,137 @@
 #include "dpp_tbl_panel.h"
 #include "dpp_tbl_diag.h"
 
-ZXIC_UINT32 dpp_panel_bond_vport(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id)
+ZXIC_UINT32 dpp_panel_bond_vport(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 panel_id)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    rc = dpp_egr_port_attr_set(pf_info, EGR_FLAG_PANEL_ID, panel_id);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
+	rc = dpp_egr_port_attr_set(pf_info, EGR_FLAG_PANEL_ID, panel_id);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
 
-    rc = dpp_panel_attr_set(pf_info, panel_id, PANEL_FLAG_PF_VQM_VFID, OWNER_PF_VQM_VFID(pf_info->vport));
-    ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
+	rc = dpp_panel_attr_set(pf_info, panel_id, PANEL_FLAG_PF_VQM_VFID,
+							OWNER_PF_VQM_VFID(pf_info->vport));
+	ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_panel_bond_vport);
 
-ZXIC_UINT32 dpp_panel_hardware_bond_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT8 enable)
+ZXIC_UINT32 dpp_panel_hardware_bond_set(DPP_PF_INFO_T *pf_info,
+										ZXIC_UINT8 panel_id, ZXIC_UINT8 enable)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = PANEL_FLAG_HW_BOND_ENABLE;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = PANEL_FLAG_HW_BOND_ENABLE;
 
-    rc = dpp_panel_attr_set(pf_info, panel_id, attr, enable);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
+	rc = dpp_panel_attr_set(pf_info, panel_id, attr, enable);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_panel_hardware_bond_set);
 
-ZXIC_UINT32 dpp_panel_bond_pf_vqm_vfid_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT16 vqm_vfid)
+ZXIC_UINT32 dpp_panel_bond_pf_vqm_vfid_set(DPP_PF_INFO_T *pf_info,
+										   ZXIC_UINT8 panel_id,
+										   ZXIC_UINT16 vqm_vfid)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = PANEL_FLAG_BOND_PF_VQM_VFID;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = PANEL_FLAG_BOND_PF_VQM_VFID;
 
-    rc = dpp_panel_attr_set(pf_info, panel_id, attr, vqm_vfid);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
+	rc = dpp_panel_attr_set(pf_info, panel_id, attr, vqm_vfid);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_panel_bond_pf_vqm_vfid_set);
 
-ZXIC_UINT32 dpp_panel_bond_pf_memport_qid_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT16 qid)
+ZXIC_UINT32 dpp_panel_bond_pf_memport_qid_set(DPP_PF_INFO_T *pf_info,
+											  ZXIC_UINT8 panel_id,
+											  ZXIC_UINT16 qid)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = PANEL_FLAG_PF_MEMPORT_QID;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = PANEL_FLAG_PF_MEMPORT_QID;
 
-    rc = dpp_panel_attr_set(pf_info, panel_id, attr, qid);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
+	rc = dpp_panel_attr_set(pf_info, panel_id, attr, qid);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_panel_bond_pf_memport_qid_set);
 
-ZXIC_UINT32 dpp_panel_ovs_pf_vqm_vfid_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT16 vqm_vfid)
+ZXIC_UINT32 dpp_panel_ovs_pf_vqm_vfid_set(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT8 panel_id,
+										  ZXIC_UINT16 vqm_vfid)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = PANEL_FLAG_OVS_PF_VFID;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = PANEL_FLAG_OVS_PF_VFID;
 
-    rc = dpp_panel_attr_set(pf_info, panel_id, attr, vqm_vfid);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
+	rc = dpp_panel_attr_set(pf_info, panel_id, attr, vqm_vfid);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_panel_ovs_pf_vqm_vfid_set);
 
-ZXIC_UINT32 dpp_panel_attr_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 panel_id, ZXIC_UINT32 attr, ZXIC_UINT32 value)
+ZXIC_UINT32 dpp_panel_attr_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 panel_id,
+							   ZXIC_UINT32 attr, ZXIC_UINT32 value)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_PANEL_PORT_ATTR_TABLE;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_PANEL_PORT_ATTR_TABLE;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_PANEL_PORT_T panel_port = {0};
+	ZXDH_PANEL_PORT_T panel_port = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u start.\n",
-                                         __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, panel_id,
-                                               dpp_vport_panel_table_attr_name_get(attr), attr, value);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u start.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, panel_id,
+			dpp_vport_panel_table_attr_name_get(attr), attr, value);
 
-    ZXIC_COMM_CHECK_INDEX(attr, 0, (ZXIC_UINT32)((sizeof(ZXDH_PANEL_PORT_T) / sizeof(ZXIC_UINT32)) - 1));
+	ZXIC_COMM_CHECK_INDEX(
+			attr, 0, ((sizeof(ZXDH_PANEL_PORT_T) / sizeof(ZXIC_UINT32)) - 1));
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = zxic_comm_mutex_lock(DEV_PCIE_MUTEX(&dev));
-    ZXIC_COMM_CHECK_RC(rc, "zxic_comm_mutex_lock");
+	rc = zxic_comm_mutex_lock(DEV_PCIE_MUTEX(&dev));
+	ZXIC_COMM_CHECK_RC(rc, "zxic_comm_mutex_lock");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u lock.\n",
-                                        __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, panel_id,
-                                              dpp_vport_panel_table_attr_name_get(attr), attr, value);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u lock.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, panel_id,
+			dpp_vport_panel_table_attr_name_get(attr), attr, value);
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC_UNLOCK(rc, "dpp_dtb_queue_id_get", DEV_PCIE_MUTEX(&dev));
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC_UNLOCK(rc, "dpp_dtb_queue_id_get", DEV_PCIE_MUTEX(&dev));
 
-    rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, panel_id, &panel_port);
-    ZXIC_COMM_CHECK_RC_UNLOCK(rc, "dpp_apt_dtb_eram_get", DEV_PCIE_MUTEX(&dev));
+	rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, panel_id, &panel_port);
+	ZXIC_COMM_CHECK_RC_UNLOCK(rc, "dpp_apt_dtb_eram_get", DEV_PCIE_MUTEX(&dev));
 
-    panel_port.hit_flag = 1;
-    *((((ZXIC_UINT32 *)(&panel_port)) + attr)) = value;
+	panel_port.hit_flag = 1;
+	*((((ZXIC_UINT32 *)(&panel_port)) + attr)) = value;
 
-    rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, panel_id, &panel_port);
-    ZXIC_COMM_CHECK_RC_UNLOCK(rc, "dpp_apt_dtb_eram_insert", DEV_PCIE_MUTEX(&dev));
+	rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, panel_id, &panel_port);
+	ZXIC_COMM_CHECK_RC_UNLOCK(rc, "dpp_apt_dtb_eram_insert",
+							  DEV_PCIE_MUTEX(&dev));
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u unlock.\n",
-                                          __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, panel_id,
-                                                dpp_vport_panel_table_attr_name_get(attr), attr, value);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u unlock.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, panel_id,
+			dpp_vport_panel_table_attr_name_get(attr), attr, value);
 
-    rc = zxic_comm_mutex_unlock(DEV_PCIE_MUTEX(&dev));
-    ZXIC_COMM_CHECK_RC(rc, "zxic_comm_mutex_unlock");
+	rc = zxic_comm_mutex_unlock(DEV_PCIE_MUTEX(&dev));
+	ZXIC_COMM_CHECK_RC(rc, "zxic_comm_mutex_unlock");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u success.\n",
-                                           __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, panel_id,
-                                                 dpp_vport_panel_table_attr_name_get(attr), attr, value);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, panel_id,
+			dpp_vport_panel_table_attr_name_get(attr), attr, value);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_panel_attr_set);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_port.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_port.c
index 976499f313675db1bc48b3980fbf6fdf80a9479e..f7a1f0a30c88125a500b673ce1044c22532b3699 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_port.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_port.c
@@ -13,321 +13,336 @@
 #include "dpp_tbl_port.h"
 #include "dpp_tbl_diag.h"
 
-ZXIC_UINT32 dpp_vport_create(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_vport_create(DPP_PF_INFO_T *pf_info)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    rc = dpp_vport_create_by_vqm_vfid(pf_info, VQM_VFID(pf_info->vport));
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_create_by_vqm_vfid");
+	rc = dpp_vport_create_by_vqm_vfid(pf_info, VQM_VFID(pf_info->vport));
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_create_by_vqm_vfid");
 
-    rc = dpp_egr_port_attr_set(pf_info, EGR_FLAG_IS_VF, !IS_PF(pf_info->vport));
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
+	rc = dpp_egr_port_attr_set(pf_info, EGR_FLAG_IS_VF, !IS_PF(pf_info->vport));
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
 
-    rc = dpp_egr_port_attr_set(pf_info, EGR_FLAG_PF_VQM_VFID, OWNER_PF_VQM_VFID(pf_info->vport));
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
+	rc = dpp_egr_port_attr_set(pf_info, EGR_FLAG_PF_VQM_VFID,
+							   OWNER_PF_VQM_VFID(pf_info->vport));
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_create);
 
-ZXIC_UINT32 dpp_vport_create_by_vqm_vfid(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 vqm_vfid)
+ZXIC_UINT32 dpp_vport_create_by_vqm_vfid(DPP_PF_INFO_T *pf_info,
+										 ZXIC_UINT32 vqm_vfid)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_VPORT_ATTR_TABLE;
-    ZXIC_UINT32 index  = vqm_vfid;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_VPORT_ATTR_TABLE;
+	ZXIC_UINT32 index = vqm_vfid;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_VPORT_T port_attr_entry = {0};
+	ZXDH_VPORT_T port_attr_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u start.\n", __FUNCTION__,
-                                                pf_info->slot, pf_info->vport, sdt_no, index);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u start.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index);
 
-    ZXIC_COMM_MEMSET(&port_attr_entry, 0, sizeof(ZXDH_VPORT_T));
+	ZXIC_COMM_MEMSET(&port_attr_entry, 0, sizeof(ZXDH_VPORT_T));
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    port_attr_entry.hit_flag = 1;
+	port_attr_entry.hit_flag = 1;
 
-    rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &port_attr_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
+	rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &port_attr_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u success.\n", __FUNCTION__,
-                                                  pf_info->slot, pf_info->vport, sdt_no, index);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_create_by_vqm_vfid);
 
-ZXIC_UINT32 dpp_vport_delete(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_vport_delete(DPP_PF_INFO_T *pf_info)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_VPORT_ATTR_TABLE;
-    ZXIC_UINT32 index  = 0;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_VPORT_ATTR_TABLE;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    index = VQM_VFID(pf_info->vport);
+	index = VQM_VFID(pf_info->vport);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u start.\n", __FUNCTION__,
-                                                pf_info->slot, pf_info->vport, sdt_no, index);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u start.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_apt_dtb_eram_clear(&dev, queue, sdt_no, index);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_clear");
+	rc = dpp_apt_dtb_eram_clear(&dev, queue, sdt_no, index);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_clear");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u success.\n", __FUNCTION__,
-                                                  pf_info->slot, pf_info->vport, sdt_no, index);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_delete);
 
-ZXIC_UINT32 dpp_egr_port_attr_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 attr, ZXIC_UINT32 value)
+ZXIC_UINT32 dpp_egr_port_attr_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 attr,
+								  ZXIC_UINT32 value)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_VPORT_ATTR_TABLE;
-    ZXIC_UINT32 index  = 0;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_VPORT_ATTR_TABLE;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_VPORT_T port_attr_entry = {0};
+	ZXDH_VPORT_T port_attr_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    index = VQM_VFID(pf_info->vport);
+	index = VQM_VFID(pf_info->vport);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u start.\n",
-                                            __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index,
-                                                     dpp_vport_table_attr_name_get(attr), attr, value);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u start.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index,
+			dpp_vport_table_attr_name_get(attr), attr, value);
 
-    ZXIC_COMM_CHECK_INDEX(attr, 0, (ZXIC_UINT32)((sizeof(ZXDH_VPORT_T) / sizeof(ZXIC_UINT32)) - 1));
+	ZXIC_COMM_CHECK_INDEX(attr, 0,
+						  ((sizeof(ZXDH_VPORT_T) / sizeof(ZXIC_UINT32)) - 1));
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &port_attr_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
+	rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &port_attr_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
 
-    port_attr_entry.hit_flag = 1;
-    *((((ZXIC_UINT32 *)(&port_attr_entry)) + attr)) = value;
+	port_attr_entry.hit_flag = 1;
+	*((((ZXIC_UINT32 *)(&port_attr_entry)) + attr)) = value;
 
-    rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &port_attr_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
+	rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &port_attr_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u success.\n",
-                                              __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index,
-                                                       dpp_vport_table_attr_name_get(attr), attr, value);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u attr: %s(%u) value: %u success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index,
+			dpp_vport_table_attr_name_get(attr), attr, value);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_egr_port_attr_set);
 
-ZXIC_UINT32 dpp_egr_port_attr_get(DPP_PF_INFO_T* pf_info, ZXDH_VPORT_T *port_attr_entry)
+ZXIC_UINT32 dpp_egr_port_attr_get(DPP_PF_INFO_T *pf_info,
+								  ZXDH_VPORT_T *port_attr_entry)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_VPORT_ATTR_TABLE;
-    ZXIC_UINT32 index  = 0;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_VPORT_ATTR_TABLE;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(port_attr_entry);
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(port_attr_entry);
 
-    index = VQM_VFID(pf_info->vport);
+	index = VQM_VFID(pf_info->vport);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u start.\n",
-                                    __FUNCTION__, pf_info->slot, pf_info->vport, index);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u start.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport, index);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, port_attr_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
-    ZXIC_COMM_CHECK_INDEX_NOT_EQUAL(port_attr_entry->hit_flag, 1);
+	rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, port_attr_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
+	ZXIC_COMM_CHECK_INDEX_NOT_EQUAL(port_attr_entry->hit_flag, 1);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u success.\n",
-                                    __FUNCTION__, pf_info->slot, pf_info->vport, index);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u success.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport, index);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_egr_port_attr_get);
 
-ZXIC_UINT32 dpp_rx_flow_hash_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 hash_mode)
+ZXIC_UINT32 dpp_rx_flow_hash_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 hash_mode)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = EGR_FLAG_RSS_HASH_FACTOR;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = EGR_FLAG_RSS_HASH_FACTOR;
 
-    rc = dpp_egr_port_attr_set(pf_info, attr, hash_mode & 0xff);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
+	rc = dpp_egr_port_attr_set(pf_info, attr, hash_mode & 0xff);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_rx_flow_hash_set);
 
-ZXIC_UINT32 dpp_rx_flow_hash_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *hash_mode)
+ZXIC_UINT32 dpp_rx_flow_hash_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 *hash_mode)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_VPORT_T port_attr_entry = {0};
+	ZXDH_VPORT_T port_attr_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(hash_mode);
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(hash_mode);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n",
-                                        __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    rc = dpp_egr_port_attr_get(pf_info, &port_attr_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_get");
+	rc = dpp_egr_port_attr_get(pf_info, &port_attr_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_get");
 
-    *hash_mode = port_attr_entry.rss_hash_factor;
+	*hash_mode = port_attr_entry.rss_hash_factor;
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x factor: %u.\n",
-                            __FUNCTION__, pf_info->slot, pf_info->vport, *hash_mode);
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n",
-                                        __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x factor: %u.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport, *hash_mode);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_rx_flow_hash_get);
 
-ZXIC_UINT32 dpp_vport_hash_index_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *hash_index)
+ZXIC_UINT32 dpp_vport_hash_index_get(DPP_PF_INFO_T *pf_info,
+									 ZXIC_UINT32 *hash_index)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_VPORT_T port_attr_entry = {0};
+	ZXDH_VPORT_T port_attr_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(hash_index);
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(hash_index);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n",
-                                        __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    rc = dpp_egr_port_attr_get(pf_info, &port_attr_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_get");
+	rc = dpp_egr_port_attr_get(pf_info, &port_attr_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_get");
 
-    *hash_index = port_attr_entry.hash_search_index;
+	*hash_index = port_attr_entry.hash_search_index;
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x hash_search_index: %u.\n",
-                            __FUNCTION__, pf_info->slot, pf_info->vport, *hash_index);
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n",
-                                         __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x hash_search_index: %u.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport, *hash_index);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_hash_index_get);
 
-ZXIC_UINT32 dpp_vport_hash_funcs_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 funcs)
+ZXIC_UINT32 dpp_vport_hash_funcs_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 funcs)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = EGR_FLAG_HASH_ALG;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = EGR_FLAG_HASH_ALG;
 
-    rc = dpp_egr_port_attr_set(pf_info, attr, funcs & 0x0f);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
+	rc = dpp_egr_port_attr_set(pf_info, attr, funcs & 0x0f);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_hash_funcs_set);
 
-ZXIC_UINT32 dpp_vport_rss_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable)
+ZXIC_UINT32 dpp_vport_rss_en_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 enable)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = EGR_FLAG_RSS_EN_OFF;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = EGR_FLAG_RSS_EN_OFF;
 
-    rc = dpp_egr_port_attr_set(pf_info, attr, enable & 0x1);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
+	rc = dpp_egr_port_attr_set(pf_info, attr, enable & 0x1);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_rss_en_set);
 
-ZXIC_UINT32 dpp_vport_virtio_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable)
+ZXIC_UINT32 dpp_vport_virtio_en_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 enable)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = EGR_FLAG_VIRTION_EN_OFF;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = EGR_FLAG_VIRTION_EN_OFF;
 
-    rc = dpp_egr_port_attr_set(pf_info, attr, enable & 0x1);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
+	rc = dpp_egr_port_attr_set(pf_info, attr, enable & 0x1);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_virtio_en_set);
 
-ZXIC_UINT32 dpp_vport_virtio_version_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 version)
+ZXIC_UINT32 dpp_vport_virtio_version_set(DPP_PF_INFO_T *pf_info,
+										 ZXIC_UINT8 version)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = EGR_FLAG_VIRTION_VERSION;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = EGR_FLAG_VIRTION_VERSION;
 
-    rc = dpp_egr_port_attr_set(pf_info, attr, version & 0x3);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
+	rc = dpp_egr_port_attr_set(pf_info, attr, version & 0x3);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_virtio_version_set);
 
-ZXIC_UINT32 dpp_vport_vlan_filter_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable)
+ZXIC_UINT32 dpp_vport_vlan_filter_en_set(DPP_PF_INFO_T *pf_info,
+										 ZXIC_UINT8 enable)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = EGR_FLAG_VLAN_FILTER_EN_OFF;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = EGR_FLAG_VLAN_FILTER_EN_OFF;
 
-    rc = dpp_egr_port_attr_set(pf_info, attr, enable & 0x1);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
+	rc = dpp_egr_port_attr_set(pf_info, attr, enable & 0x1);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_vlan_filter_en_set);
 
-ZXIC_UINT32 dpp_vport_vlan_qinq_en_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable)
+ZXIC_UINT32 dpp_vport_vlan_qinq_en_set(DPP_PF_INFO_T *pf_info,
+									   ZXIC_UINT8 enable)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = EGR_FLAG_QINQ_VLAN_STRIP_OFFLOAD;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = EGR_FLAG_QINQ_VLAN_STRIP_OFFLOAD;
 
-    rc = dpp_egr_port_attr_set(pf_info, attr, enable & 0x1);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
+	rc = dpp_egr_port_attr_set(pf_info, attr, enable & 0x1);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_vlan_qinq_en_set);
 
-ZXIC_UINT32 dpp_vport_vlan_strip_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 enable)
+ZXIC_UINT32 dpp_vport_vlan_strip_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 enable)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = EGR_FLAG_VLAN_STRIP_OFFLOAD;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = EGR_FLAG_VLAN_STRIP_OFFLOAD;
 
-    rc = dpp_egr_port_attr_set(pf_info, attr, enable & 0x1);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
+	rc = dpp_egr_port_attr_set(pf_info, attr, enable & 0x1);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_vlan_strip_set);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_promisc.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_promisc.c
index 19878da6e0ab45aff4d6e65d75b1dae9c258dcdc..5fa92ac6082b6ccc36bf76cc249f46e5394856d9 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_promisc.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_promisc.c
@@ -12,134 +12,147 @@
 #include "dpp_tbl_comm.h"
 #include "dpp_tbl_promisc.h"
 
-ZXIC_UINT32 dpp_vport_promisc_info_set(DPP_PF_INFO_T* pf_info, DPP_VPORT_PROMISC_TABLE_T* promisc_table, ZXIC_UINT32 enable)
+ZXIC_UINT32 dpp_vport_promisc_info_set(DPP_PF_INFO_T *pf_info,
+									   DPP_VPORT_PROMISC_TABLE_T *promisc_table,
+									   ZXIC_UINT32 enable)
 {
-    ZXIC_UINT32 group_id  = 0;
-    ZXIC_UINT32 vfunc_num = 0;
-    ZXIC_UINT64 bitmap_mask = 0;
-
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(promisc_table);
-    ZXIC_COMM_CHECK_INDEX(enable, 0, 1);
-
-    vfunc_num = VFUNC_NUM(pf_info->vport);
-    ZXIC_COMM_CHECK_INDEX(vfunc_num, 0, (PROMISC_GROUP_NUM * PROMISC_MEMBER_NUM_IN_GROUP) - 1);
-
-    group_id  = vfunc_num / PROMISC_MEMBER_NUM_IN_GROUP;
-    ZXIC_COMM_CHECK_INDEX(group_id, 0, PROMISC_GROUP_NUM - 1);
-
-    bitmap_mask = ((ZXIC_UINT64)(1) << (PROMISC_MEMBER_NUM_IN_GROUP - 1 - (vfunc_num % PROMISC_MEMBER_NUM_IN_GROUP)));
-
-    if (IS_PF(pf_info->vport))
-    {
-        promisc_table->promisc_info.pf_enable = enable;
-    }
-    else
-    {
-        promisc_table->promisc_info.bitmap[group_id] = (enable == 1) ?
-                                                       (promisc_table->promisc_info.bitmap[group_id] | bitmap_mask) :
-                                                       (promisc_table->promisc_info.bitmap[group_id] & ~bitmap_mask);
-    }
-
-    return DPP_OK;
+	ZXIC_UINT32 group_id = 0;
+	ZXIC_UINT32 vfunc_num = 0;
+	ZXIC_UINT64 bitmap_mask = 0;
+
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(promisc_table);
+	ZXIC_COMM_CHECK_INDEX(enable, 0, 1);
+
+	vfunc_num = VFUNC_NUM(pf_info->vport);
+	ZXIC_COMM_CHECK_INDEX(vfunc_num, 0,
+						  PROMISC_GROUP_NUM * PROMISC_MEMBER_NUM_IN_GROUP - 1);
+
+	group_id = vfunc_num / PROMISC_MEMBER_NUM_IN_GROUP;
+	ZXIC_COMM_CHECK_INDEX(group_id, 0, PROMISC_GROUP_NUM - 1);
+
+	bitmap_mask =
+			((ZXIC_UINT64)(1) << (PROMISC_MEMBER_NUM_IN_GROUP - 1 -
+								  (vfunc_num % PROMISC_MEMBER_NUM_IN_GROUP)));
+
+	if (IS_PF(pf_info->vport)) {
+		promisc_table->promisc_info.pf_enable = enable;
+	} else {
+		promisc_table->promisc_info.bitmap[group_id] =
+				(enable == 1) ? (promisc_table->promisc_info.bitmap[group_id] |
+								 bitmap_mask) :
+								  (promisc_table->promisc_info.bitmap[group_id] &
+								 ~bitmap_mask);
+	}
+
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_vport_promisc_table_insert(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 sdt_no, DPP_VPORT_PROMISC_TABLE_T* promisc_table)
+ZXIC_UINT32
+dpp_vport_promisc_table_insert(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 sdt_no,
+							   DPP_VPORT_PROMISC_TABLE_T *promisc_table)
 {
-    DPP_DEV_T dev = {0};
-
-    ZXIC_UINT32 dev_id   = 0;
-    ZXIC_UINT32 group_id = 0;
-    ZXIC_UINT32 index    = 0;
-    ZXIC_UINT32 queue    = 0;
-    ZXIC_UINT32 rc       = DPP_OK;
-
-    ZXDH_PROMISC_T promisc_entry   = {0};
-
-    ZXIC_COMM_CHECK_POINT(pf_info);
-    ZXIC_COMM_CHECK_POINT(promisc_table);
-
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
-
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
-
-    for (group_id = 0; group_id < PROMISC_GROUP_NUM; group_id++)
-    {
-        index = (((OWNER_PF_VQM_VFID(pf_info->vport) - PF_VQM_VFID_OFFSET) << 2)| group_id);
-        promisc_entry.hit_flag = 1;
-        promisc_entry.pf_enable = promisc_table->promisc_info.pf_enable;
-        promisc_entry.bitmap = promisc_table->promisc_info.bitmap[group_id];
-
-        rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &promisc_entry);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
-
-        ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u group_id: %u index: 0x%02x.\n",
-                                        __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, group_id, index);
-        ZXIC_COMM_PRINT("[%s] pf_enable: %u bitmap: %02x %02x %02x %02x %02x %02x %02x %02x.\n", __FUNCTION__,
-                                                                  promisc_entry.pf_enable,
-                                                                  *((ZXIC_UINT8*)(&promisc_entry.bitmap) + 7),
-                                                                  *((ZXIC_UINT8*)(&promisc_entry.bitmap) + 6),
-                                                                  *((ZXIC_UINT8*)(&promisc_entry.bitmap) + 5),
-                                                                  *((ZXIC_UINT8*)(&promisc_entry.bitmap) + 4),
-                                                                  *((ZXIC_UINT8*)(&promisc_entry.bitmap) + 3),
-                                                                  *((ZXIC_UINT8*)(&promisc_entry.bitmap) + 2),
-                                                                  *((ZXIC_UINT8*)(&promisc_entry.bitmap) + 1),
-                                                                  *((ZXIC_UINT8*)(&promisc_entry.bitmap) + 0));
-    }
-
-    return DPP_OK;
+	DPP_DEV_T dev = { 0 };
+
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 group_id = 0;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	ZXDH_PROMISC_T promisc_entry = { 0 };
+
+	ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(promisc_table);
+
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+
+	for (group_id = 0; group_id < PROMISC_GROUP_NUM; group_id++) {
+		index = (((OWNER_PF_VQM_VFID(pf_info->vport) - PF_VQM_VFID_OFFSET)
+				  << 2) |
+				 group_id);
+		promisc_entry.hit_flag = 1;
+		promisc_entry.pf_enable = promisc_table->promisc_info.pf_enable;
+		promisc_entry.bitmap = promisc_table->promisc_info.bitmap[group_id];
+
+		rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index,
+									 &promisc_entry);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
+
+		ZXIC_COMM_PRINT(
+				"[%s] slot: %u vport: 0x%04x sdt_no: %u group_id: %u index: 0x%02x.\n",
+				__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, group_id,
+				index);
+		ZXIC_COMM_PRINT(
+				"[%s] pf_enable: %u bitmap: %02x %02x %02x %02x %02x %02x %02x %02x.\n",
+				__FUNCTION__, promisc_entry.pf_enable,
+				*((ZXIC_UINT8 *)(&promisc_entry.bitmap) + 7),
+				*((ZXIC_UINT8 *)(&promisc_entry.bitmap) + 6),
+				*((ZXIC_UINT8 *)(&promisc_entry.bitmap) + 5),
+				*((ZXIC_UINT8 *)(&promisc_entry.bitmap) + 4),
+				*((ZXIC_UINT8 *)(&promisc_entry.bitmap) + 3),
+				*((ZXIC_UINT8 *)(&promisc_entry.bitmap) + 2),
+				*((ZXIC_UINT8 *)(&promisc_entry.bitmap) + 1),
+				*((ZXIC_UINT8 *)(&promisc_entry.bitmap) + 0));
+	}
+
+	return DPP_OK;
 }
 
-ZXIC_UINT32 dpp_vport_uc_promisc_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 enable)
+ZXIC_UINT32 dpp_vport_uc_promisc_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 enable)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-    DPP_VPORT_PROMISC_TABLE_T* promisc_table = NULL;
+	ZXIC_UINT32 rc = DPP_OK;
+	DPP_VPORT_PROMISC_TABLE_T *promisc_table = NULL;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x enable: %u start.\n",
-                                            __FUNCTION__, pf_info->slot, pf_info->vport, enable);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x enable: %u start.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport, enable);
 
-    rc = dpp_vport_uc_promisc_table_get(pf_info, &promisc_table);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_uc_promisc_table_get");
+	rc = dpp_vport_uc_promisc_table_get(pf_info, &promisc_table);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_uc_promisc_table_get");
 
-    rc = dpp_vport_promisc_info_set(pf_info, promisc_table, enable);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_promisc_info_set");
+	rc = dpp_vport_promisc_info_set(pf_info, promisc_table, enable);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_promisc_info_set");
 
-    rc = dpp_vport_promisc_table_insert(pf_info, ZXDH_SDT_UC_PROMISC_TABLE, promisc_table);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_promisc_table_insert");
+	rc = dpp_vport_promisc_table_insert(pf_info, ZXDH_SDT_UC_PROMISC_TABLE,
+										promisc_table);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_promisc_table_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x enable: %u success.\n",
-                                            __FUNCTION__, pf_info->slot, pf_info->vport, enable);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x enable: %u success.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport, enable);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_uc_promisc_set);
 
-ZXIC_UINT32 dpp_vport_mc_promisc_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 enable)
+ZXIC_UINT32 dpp_vport_mc_promisc_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 enable)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-    DPP_VPORT_PROMISC_TABLE_T* promisc_table = NULL;
+	ZXIC_UINT32 rc = DPP_OK;
+	DPP_VPORT_PROMISC_TABLE_T *promisc_table = NULL;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x enable: %u start.\n",
-                                            __FUNCTION__, pf_info->slot, pf_info->vport, enable);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x enable: %u start.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport, enable);
 
-    rc = dpp_vport_mc_promisc_table_get(pf_info, &promisc_table);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_promisc_table_get");
+	rc = dpp_vport_mc_promisc_table_get(pf_info, &promisc_table);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_mc_promisc_table_get");
 
-    rc = dpp_vport_promisc_info_set(pf_info, promisc_table, enable);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_promisc_info_set");
+	rc = dpp_vport_promisc_info_set(pf_info, promisc_table, enable);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_promisc_info_set");
 
-    rc = dpp_vport_promisc_table_insert(pf_info, ZXDH_SDT_MC_PROMISC_TABLE, promisc_table);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_vport_promisc_table_insert");
+	rc = dpp_vport_promisc_table_insert(pf_info, ZXDH_SDT_MC_PROMISC_TABLE,
+										promisc_table);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_vport_promisc_table_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x enable: %u success.\n",
-                                            __FUNCTION__, pf_info->slot, pf_info->vport, enable);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x enable: %u success.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport, enable);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_mc_promisc_set);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_ptp.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_ptp.c
index 0e09625792a2799872d77f8b3e87f68d4182df83..43abc285473880fcfc49fe26ef2cfdecb8cedc53 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_ptp.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_ptp.c
@@ -12,36 +12,40 @@
 #include "dpp_tbl_comm.h"
 #include "dpp_tbl_ptp.h"
 
-ZXIC_UINT32 dpp_ptp_port_vfid_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 ptp_port_vfid)
+ZXIC_UINT32 dpp_ptp_port_vfid_set(DPP_PF_INFO_T *pf_info,
+								  ZXIC_UINT32 ptp_port_vfid)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = PANEL_FLAG_PTP_PORT_VFID;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = PANEL_FLAG_PTP_PORT_VFID;
 
-    ZXDH_VPORT_T port_attr_entry = {0};
+	ZXDH_VPORT_T port_attr_entry = { 0 };
 
-    rc = dpp_egr_port_attr_get(pf_info, &port_attr_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_get");
+	rc = dpp_egr_port_attr_get(pf_info, &port_attr_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_get");
 
-    rc = dpp_panel_attr_set(pf_info, port_attr_entry.panel_id, attr, ptp_port_vfid);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
+	rc = dpp_panel_attr_set(pf_info, port_attr_entry.panel_id, attr,
+							ptp_port_vfid);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_ptp_port_vfid_set);
 
-ZXIC_UINT32 dpp_ptp_tc_enable_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 ptp_tc_enable)
+ZXIC_UINT32 dpp_ptp_tc_enable_set(DPP_PF_INFO_T *pf_info,
+								  ZXIC_UINT32 ptp_tc_enable)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = PANEL_FLAG_PTP_TC_ENABLE;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = PANEL_FLAG_PTP_TC_ENABLE;
 
-    ZXDH_VPORT_T port_attr_entry = {0};
+	ZXDH_VPORT_T port_attr_entry = { 0 };
 
-    rc = dpp_egr_port_attr_get(pf_info, &port_attr_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_get");
+	rc = dpp_egr_port_attr_get(pf_info, &port_attr_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_egr_port_attr_get");
 
-    rc = dpp_panel_attr_set(pf_info, port_attr_entry.panel_id, attr, ptp_tc_enable);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
+	rc = dpp_panel_attr_set(pf_info, port_attr_entry.panel_id, attr,
+							ptp_tc_enable);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_ptp_tc_enable_set);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_qid.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_qid.c
index 85d797b079692261befbf6d19e33f5444750c5a5..cb4472e2889849cc6a2f153eab3016da10fb639f 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_qid.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_qid.c
@@ -12,197 +12,220 @@
 #include "dpp_tbl_comm.h"
 #include "dpp_tbl_qid.h"
 
-ZXIC_UINT32 dpp_rxfh_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *queue_list, ZXIC_UINT32 queue_num)
+ZXIC_UINT32 dpp_rxfh_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 *queue_list,
+						 ZXIC_UINT32 queue_num)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id   = 0;
-    ZXIC_UINT32 i        = 0;
-    ZXIC_UINT32 queue    = 0;
-    ZXIC_UINT32 group_id = 0;
-    ZXIC_UINT32 sdt_no   = ZXDH_SDT_RSS_TO_VQID_TABLE;
-    ZXIC_UINT32 index    = 0;
-    ZXIC_UINT32 rc       = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 group_id = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_RSS_TO_VQID_TABLE;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_RSS_TO_VQID_T rss_to_vqid_entry = {0};
+	ZXDH_RSS_TO_VQID_T rss_to_vqid_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    ZXIC_COMM_CHECK_POINT(queue_list);
+	ZXIC_COMM_CHECK_POINT(queue_list);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    index = VQM_VFID(pf_info->vport) * RSS_TO_VQID_GROUP_NUM;
-    rss_to_vqid_entry.hit_flag = 1;
+	index = VQM_VFID(pf_info->vport) * RSS_TO_VQID_GROUP_NUM;
+	rss_to_vqid_entry.hit_flag = 1;
 
-    for (group_id = 0; group_id < RSS_TO_VQID_GROUP_NUM; group_id++)
-    {
-        for (i = 0; i < 8; i++)
-        {
-            rss_to_vqid_entry.vqm_qid[i] = queue_list[((group_id * 8) + i) % queue_num];
-        }
+	for (group_id = 0; group_id < RSS_TO_VQID_GROUP_NUM; group_id++) {
+		for (i = 0; i < 8; i++) {
+			rss_to_vqid_entry.vqm_qid[i] =
+					queue_list[((group_id * 8) + i) % queue_num];
+		}
 
-        rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index + group_id, &rss_to_vqid_entry);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
+		rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index + group_id,
+									 &rss_to_vqid_entry);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
 
-        ZXIC_COMM_TRACE_INFO("[%s] slot: %u vport: 0x%04x sdt_no: %u index: 0x%04x.\n",
-                                                    __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index + group_id);
+		ZXIC_COMM_TRACE_INFO(
+				"[%s] slot: %u vport: 0x%04x sdt_no: %u index: 0x%04x.\n",
+				__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no,
+				index + group_id);
 
-        ZXIC_COMM_TRACE_INFO("[%s] vqm_qid0: 0x%04x vqm_qid1: 0x%04x vqm_qid2: 0x%04x vqm_qid3: 0x%04x.\n", __FUNCTION__,
-                                                               rss_to_vqid_entry.vqm_qid[0], rss_to_vqid_entry.vqm_qid[1],
-                                                               rss_to_vqid_entry.vqm_qid[2], rss_to_vqid_entry.vqm_qid[3]);
-        ZXIC_COMM_TRACE_INFO("[%s] vqm_qid4: 0x%04x vqm_qid5: 0x%04x vqm_qid6: 0x%04x vqm_qid7: 0x%04x.\n", __FUNCTION__,
-                                                               rss_to_vqid_entry.vqm_qid[4], rss_to_vqid_entry.vqm_qid[5],
-                                                               rss_to_vqid_entry.vqm_qid[6], rss_to_vqid_entry.vqm_qid[7]);
-    }
+		ZXIC_COMM_TRACE_INFO(
+				"[%s] vqm_qid0: 0x%04x vqm_qid1: 0x%04x vqm_qid2: 0x%04x vqm_qid3: 0x%04x.\n",
+				__FUNCTION__, rss_to_vqid_entry.vqm_qid[0],
+				rss_to_vqid_entry.vqm_qid[1], rss_to_vqid_entry.vqm_qid[2],
+				rss_to_vqid_entry.vqm_qid[3]);
+		ZXIC_COMM_TRACE_INFO(
+				"[%s] vqm_qid4: 0x%04x vqm_qid5: 0x%04x vqm_qid6: 0x%04x vqm_qid7: 0x%04x.\n",
+				__FUNCTION__, rss_to_vqid_entry.vqm_qid[4],
+				rss_to_vqid_entry.vqm_qid[5], rss_to_vqid_entry.vqm_qid[6],
+				rss_to_vqid_entry.vqm_qid[7]);
+	}
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_rxfh_set);
 
-ZXIC_UINT32 dpp_rxfh_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 *queue_list, ZXIC_UINT32 queue_num)
+ZXIC_UINT32 dpp_rxfh_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 *queue_list,
+						 ZXIC_UINT32 queue_num)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id   = 0;
-    ZXIC_UINT32 i        = 0;
-    ZXIC_UINT32 queue = 0;
-    ZXIC_UINT32 group_id = 0;
-    ZXIC_UINT32 sdt_no   = ZXDH_SDT_RSS_TO_VQID_TABLE;
-    ZXIC_UINT32 index    = 0;
-    ZXIC_UINT32 rc       = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 i = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 group_id = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_RSS_TO_VQID_TABLE;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_RSS_TO_VQID_T rss_to_vqid_entry = {0};
+	ZXDH_RSS_TO_VQID_T rss_to_vqid_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    ZXIC_COMM_CHECK_POINT(queue_list);
+	ZXIC_COMM_CHECK_POINT(queue_list);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    index = VQM_VFID(pf_info->vport) * RSS_TO_VQID_GROUP_NUM;
-    for (group_id = 0; group_id < RSS_TO_VQID_GROUP_NUM; group_id++)
-    {
-        rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index + group_id, &rss_to_vqid_entry);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
-        ZXIC_COMM_CHECK_INDEX_NOT_EQUAL(rss_to_vqid_entry.hit_flag, 1);
+	index = VQM_VFID(pf_info->vport) * RSS_TO_VQID_GROUP_NUM;
+	for (group_id = 0; group_id < RSS_TO_VQID_GROUP_NUM; group_id++) {
+		rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index + group_id,
+								  &rss_to_vqid_entry);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
+		ZXIC_COMM_CHECK_INDEX_NOT_EQUAL(rss_to_vqid_entry.hit_flag, 1);
 
-        for (i = 0; i < 8; i++)
-        {
-            queue_list[((group_id * 8) + i) % queue_num] = rss_to_vqid_entry.vqm_qid[i];
-        }
-    }
+		for (i = 0; i < 8; i++) {
+			queue_list[((group_id * 8) + i) % queue_num] =
+					rss_to_vqid_entry.vqm_qid[i];
+		}
+	}
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_rxfh_get);
 
-ZXIC_UINT32 dpp_rxfh_del(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_rxfh_del(DPP_PF_INFO_T *pf_info)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id   = 0;
-    ZXIC_UINT32 queue    = 0;
-    ZXIC_UINT32 group_id = 0;
-    ZXIC_UINT32 sdt_no   = ZXDH_SDT_RSS_TO_VQID_TABLE;
-    ZXIC_UINT32 index    = 0;
-    ZXIC_UINT32 rc       = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 group_id = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_RSS_TO_VQID_TABLE;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    index = VQM_VFID(pf_info->vport) * RSS_TO_VQID_GROUP_NUM;
-    for (group_id = 0; group_id < RSS_TO_VQID_GROUP_NUM; group_id++)
-    {
-        rc = dpp_apt_dtb_eram_clear(&dev, queue, sdt_no, index + group_id);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_clear");
-    }
+	index = VQM_VFID(pf_info->vport) * RSS_TO_VQID_GROUP_NUM;
+	for (group_id = 0; group_id < RSS_TO_VQID_GROUP_NUM; group_id++) {
+		rc = dpp_apt_dtb_eram_clear(&dev, queue, sdt_no, index + group_id);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_clear");
+	}
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_rxfh_del);
 
-ZXIC_UINT32 dpp_thash_key_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 *hash_key, ZXIC_UINT32 key_num)
+ZXIC_UINT32 dpp_thash_key_set(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 *hash_key,
+							  ZXIC_UINT32 key_num)
 {
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    DPP_DEV_T dev = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_T *thash = (DPP_PPU_PPU_COP_THASH_RSK_T*)hash_key;
+	DPP_DEV_T dev = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_T *thash =
+			(DPP_PPU_PPU_COP_THASH_RSK_T *)hash_key;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    ZXIC_COMM_CHECK_POINT(thash);
-    ZXIC_COMM_CHECK_INDEX_LOWER(key_num, (ZXIC_UINT32)sizeof(DPP_PPU_PPU_COP_THASH_RSK_T));
+	ZXIC_COMM_CHECK_POINT(thash);
+	ZXIC_COMM_CHECK_INDEX_LOWER(key_num, sizeof(DPP_PPU_PPU_COP_THASH_RSK_T));
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_ppu_ppu_cop_thash_rsk_set(&dev, thash);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_ppu_ppu_cop_thash_rsk_set");
+	rc = dpp_ppu_ppu_cop_thash_rsk_set(&dev, thash);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_ppu_ppu_cop_thash_rsk_set");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x hash_key:\n", __FUNCTION__, pf_info->slot, pf_info->vport);
-    dpp_data_print(hash_key, key_num);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x hash_key:\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
+	dpp_data_print(hash_key, key_num);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_thash_key_set);
 
-ZXIC_UINT32 dpp_thash_key_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 *hash_key, ZXIC_UINT32 key_num)
+ZXIC_UINT32 dpp_thash_key_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT8 *hash_key,
+							  ZXIC_UINT32 key_num)
 {
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    DPP_DEV_T dev = {0};
-    DPP_PPU_PPU_COP_THASH_RSK_T *thash = (DPP_PPU_PPU_COP_THASH_RSK_T*)hash_key;
+	DPP_DEV_T dev = { 0 };
+	DPP_PPU_PPU_COP_THASH_RSK_T *thash =
+			(DPP_PPU_PPU_COP_THASH_RSK_T *)hash_key;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    ZXIC_COMM_CHECK_POINT(thash);
-    ZXIC_COMM_CHECK_INDEX_LOWER(key_num, (ZXIC_UINT32)sizeof(DPP_PPU_PPU_COP_THASH_RSK_T));
+	ZXIC_COMM_CHECK_POINT(thash);
+	ZXIC_COMM_CHECK_INDEX_LOWER(key_num, sizeof(DPP_PPU_PPU_COP_THASH_RSK_T));
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_ppu_ppu_cop_thash_rsk_get(&dev, thash);
-    ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_ppu_ppu_cop_thash_rsk_get");
+	rc = dpp_ppu_ppu_cop_thash_rsk_get(&dev, thash);
+	ZXIC_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_ppu_ppu_cop_thash_rsk_get");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x hash_key:\n", __FUNCTION__, pf_info->slot, pf_info->vport);
-    dpp_data_print(hash_key, key_num);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x hash_key:\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
+	dpp_data_print(hash_key, key_num);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__, pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_thash_key_get);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_stat.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_stat.c
index ec43525f3a8febf62298ce07e9d6de064388ed52..0f376e7b0719198cf1dc927f957ff41e3d9672c4 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_stat.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_stat.c
@@ -13,374 +13,528 @@
 #include "dpp_tbl_comm.h"
 #include "dpp_tbl_stat.h"
 
-ZXIC_UINT32 dpp_stat_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt)
+ZXIC_UINT32 dpp_stat_cnt_get(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 index,
+							 ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id  = 0;
-    ZXIC_UINT32 queue   = 0;
-    ZXIC_UINT32 buff[2] = {0};
-    ZXIC_UINT32 rc      = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 buff[2] = { 0 };
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_TRACE_INFO("[%s] slot: %u vport: 0x%04x index: %u mode: %u start.\n", __FUNCTION__,
-                                                                pf_info->slot, pf_info->vport, index, mode);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u mode: %u start.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport, index, mode);
 
-    ZXIC_COMM_CHECK_POINT(p_cnt);
-    ZXIC_COMM_CHECK_INDEX(mode, STAT_RD_CLR_MODE_UNCLR, STAT_RD_CLR_MODE_CLR);
-    ZXIC_COMM_CHECK_INDEX(index, 0, ZXDH_STAT_PPU_ERAM_DEPTH - 1);
+	ZXIC_COMM_CHECK_POINT(p_cnt);
+	ZXIC_COMM_CHECK_INDEX(mode, STAT_RD_CLR_MODE_UNCLR, STAT_RD_CLR_MODE_CLR);
+	ZXIC_COMM_CHECK_INDEX(index, 0, ZXDH_STAT_PPU_ERAM_DEPTH - 1);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    if (mode == STAT_RD_CLR_MODE_CLR)
-    {
-        rc = dpp_stat_ppu_cnt_get(&dev, STAT_64_MODE, index, STAT_RD_CLR_MODE_CLR, buff);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_stat_ppu_cnt_get");
-    }
-    else
-    {
-        rc = dpp_dtb_eram_stat_data_get(&dev, queue, ZXDH_STAT_PPU_ERAM_BAADDR, 
-                                                 ERAM128_TBL_64b, index, buff);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_eram_stat_data_get");
-    }
+	if (mode == STAT_RD_CLR_MODE_CLR) {
+		rc = dpp_stat_ppu_cnt_get(&dev, STAT_64_MODE, index,
+								  STAT_RD_CLR_MODE_CLR, buff);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_stat_ppu_cnt_get");
+	} else {
+		rc = dpp_dtb_eram_stat_data_get(&dev, queue, ZXDH_STAT_PPU_ERAM_BAADDR,
+										ERAM128_TBL_64b, index, buff);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_eram_stat_data_get");
+	}
 
-    *p_cnt = ((ZXIC_UINT64)buff[0] << 32) | buff[1];
+	*p_cnt = ((ZXIC_UINT64)buff[0] << 32) | buff[1];
 
-    ZXIC_COMM_TRACE_INFO("[%s] slot: %u vport: 0x%04x index: %u mode: %u cnt: %llu success.\n",
-                                            __FUNCTION__, pf_info->slot, pf_info->vport, index, mode, *p_cnt);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u mode: %u cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, mode, *p_cnt);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_cnt_get);
 
-ZXIC_UINT32 dpp_stat_cnt_get_128(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt)
+ZXIC_UINT32 dpp_stat_cnt_get_128(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 index,
+								 ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt,
+								 ZXIC_UINT64 *p_pk_cnt)
 {
-    DPP_DEV_T dev = {0};
-
-    ZXIC_UINT32 dev_id  = 0;
-    ZXIC_UINT32 queue   = 0;
-    ZXIC_UINT32 buff[4] = {0};
-    ZXIC_UINT32 rc      = DPP_OK;
-
-    ZXIC_COMM_CHECK_POINT(pf_info);
-
-    ZXIC_COMM_TRACE_INFO("[%s] slot: %u vport: 0x%04x index: %u mode: %u start.\n", __FUNCTION__,
-                                                                    pf_info->slot, pf_info->vport, index, mode);
-
-    ZXIC_COMM_CHECK_POINT(p_pkB_cnt);
-    ZXIC_COMM_CHECK_POINT(p_pk_cnt);
-    ZXIC_COMM_CHECK_INDEX(mode, STAT_RD_CLR_MODE_UNCLR, STAT_RD_CLR_MODE_CLR);
-    ZXIC_COMM_CHECK_INDEX(index, 0, ((ZXDH_STAT_PPU_ERAM_DEPTH / 2) - 1));
-
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
-
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
-
-    if (mode == STAT_RD_CLR_MODE_CLR)
-    {
-        rc = dpp_stat_ppu_cnt_get(&dev, STAT_128_MODE, index, STAT_RD_CLR_MODE_CLR, buff);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_stat_ppu_cnt_get");
-    }
-    else
-    {
-        rc = dpp_dtb_eram_stat_data_get(&dev, queue, ZXDH_STAT_PPU_ERAM_BAADDR, 
-                                                 ERAM128_TBL_128b, index, buff);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_eram_stat_data_get");
-    }
-
-    *p_pk_cnt = ((ZXIC_UINT64)buff[0] << 32) | buff[1];
-    *p_pkB_cnt = ((ZXIC_UINT64)buff[2] << 32) | buff[3];
-
-    ZXIC_COMM_TRACE_INFO("[%s] slot: %u vport: 0x%04x index: %u mode: %u h64_cnt: %llu success.\n", __FUNCTION__,
-                                                        pf_info->slot, pf_info->vport, index, mode, *p_pk_cnt);
-    ZXIC_COMM_TRACE_INFO("[%s] slot: %u vport: 0x%04x index: %u mode: %u l64_cnt: %llu success.\n", __FUNCTION__,
-                                                        pf_info->slot, pf_info->vport, index, mode, *p_pkB_cnt);
-
-    return DPP_OK;
+	DPP_DEV_T dev = { 0 };
+
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 buff[4] = { 0 };
+	ZXIC_UINT32 rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(pf_info);
+
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u mode: %u start.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport, index, mode);
+
+	ZXIC_COMM_CHECK_POINT(p_pkB_cnt);
+	ZXIC_COMM_CHECK_POINT(p_pk_cnt);
+	ZXIC_COMM_CHECK_INDEX(mode, STAT_RD_CLR_MODE_UNCLR, STAT_RD_CLR_MODE_CLR);
+	ZXIC_COMM_CHECK_INDEX(index, 0, ZXDH_STAT_PPU_ERAM_DEPTH / 2 - 1);
+
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+
+	if (mode == STAT_RD_CLR_MODE_CLR) {
+		rc = dpp_stat_ppu_cnt_get(&dev, STAT_128_MODE, index,
+								  STAT_RD_CLR_MODE_CLR, buff);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_stat_ppu_cnt_get");
+	} else {
+		rc = dpp_dtb_eram_stat_data_get(&dev, queue, ZXDH_STAT_PPU_ERAM_BAADDR,
+										ERAM128_TBL_128b, index, buff);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_eram_stat_data_get");
+	}
+
+	*p_pk_cnt = ((ZXIC_UINT64)buff[0] << 32) | buff[1];
+	*p_pkB_cnt = ((ZXIC_UINT64)buff[2] << 32) | buff[3];
+
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u mode: %u h64_cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, mode,
+			*p_pk_cnt);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u mode: %u l64_cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, mode,
+			*p_pkB_cnt);
+
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_cnt_get_128);
 
-ZXIC_UINT32 dpp_stat_mc_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt)
+ZXIC_UINT32 dpp_stat_mc_packet_rx_cnt_get(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 index, ZXIC_UINT32 mode,
+										  ZXIC_UINT64 *p_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(p_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_MC_PACKET_RX_CNT_ERAM_DEPTH - 1);
+	ZXIC_COMM_CHECK_POINT(p_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_MC_PACKET_RX_CNT_ERAM_DEPTH - 1);
 
-    rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_MC_PACKET_RX_CNT_ERAM_BAADDR, mode, p_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
+	rc = dpp_stat_cnt_get(pf_info,
+						  index + DPP_STAT_MC_PACKET_RX_CNT_ERAM_BAADDR, mode,
+						  p_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n", __FUNCTION__,
-                                                                    pf_info->slot, pf_info->vport, index, *p_cnt);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_cnt);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_mc_packet_rx_cnt_get);
 
-ZXIC_UINT32 dpp_stat_bc_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt)
+ZXIC_UINT32 dpp_stat_bc_packet_rx_cnt_get(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 index, ZXIC_UINT32 mode,
+										  ZXIC_UINT64 *p_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(p_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_BC_PACKET_RX_CNT_ERAM_DEPTH - 1);
+	ZXIC_COMM_CHECK_POINT(p_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_BC_PACKET_RX_CNT_ERAM_DEPTH - 1);
 
-    rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_BC_PACKET_RX_CNT_ERAM_BAADDR, mode, p_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
+	rc = dpp_stat_cnt_get(pf_info,
+						  index + DPP_STAT_BC_PACKET_RX_CNT_ERAM_BAADDR, mode,
+						  p_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n", __FUNCTION__,
-                                                                    pf_info->slot, pf_info->vport, index, *p_cnt);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_cnt);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_bc_packet_rx_cnt_get);
 
-ZXIC_UINT32 dpp_stat_1588_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt)
+ZXIC_UINT32 dpp_stat_1588_packet_rx_cnt_get(DPP_PF_INFO_T *pf_info,
+											ZXIC_UINT32 index, ZXIC_UINT32 mode,
+											ZXIC_UINT64 *p_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(p_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_1588_PACKET_RX_CNT_ERAM_DEPTH - 1);
+	ZXIC_COMM_CHECK_POINT(p_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_1588_PACKET_RX_CNT_ERAM_DEPTH - 1);
 
-    rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_1588_PACKET_RX_CNT_ERAM_BAADDR, mode, p_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
+	rc = dpp_stat_cnt_get(pf_info,
+						  index + DPP_STAT_1588_PACKET_RX_CNT_ERAM_BAADDR, mode,
+						  p_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n", __FUNCTION__,
-                                                                    pf_info->slot, pf_info->vport, index, *p_cnt);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_cnt);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_1588_packet_rx_cnt_get);
 
-ZXIC_UINT32 dpp_stat_1588_packet_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt)
+ZXIC_UINT32 dpp_stat_1588_packet_tx_cnt_get(DPP_PF_INFO_T *pf_info,
+											ZXIC_UINT32 index, ZXIC_UINT32 mode,
+											ZXIC_UINT64 *p_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(p_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_1588_PACKET_TX_CNT_ERAM_DEPTH - 1);
+	ZXIC_COMM_CHECK_POINT(p_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_1588_PACKET_TX_CNT_ERAM_DEPTH - 1);
 
-    rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_1588_PACKET_TX_CNT_ERAM_BAADDR, mode, p_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
+	rc = dpp_stat_cnt_get(pf_info,
+						  index + DPP_STAT_1588_PACKET_TX_CNT_ERAM_BAADDR, mode,
+						  p_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n", __FUNCTION__,
-                                                                    pf_info->slot, pf_info->vport, index, *p_cnt);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_cnt);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_1588_packet_tx_cnt_get);
 
-ZXIC_UINT32 dpp_stat_1588_packet_drop_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt)
+ZXIC_UINT32 dpp_stat_1588_packet_drop_cnt_get(DPP_PF_INFO_T *pf_info,
+											  ZXIC_UINT32 index,
+											  ZXIC_UINT32 mode,
+											  ZXIC_UINT64 *p_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(p_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_1588_PACKET_DROP_CNT_ERAM_DEPTH - 1);
+	ZXIC_COMM_CHECK_POINT(p_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0,
+						  DPP_STAT_1588_PACKET_DROP_CNT_ERAM_DEPTH - 1);
 
-    rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_1588_PACKET_DROP_CNT_ERAM_BAADDR, mode, p_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
+	rc = dpp_stat_cnt_get(pf_info,
+						  index + DPP_STAT_1588_PACKET_DROP_CNT_ERAM_BAADDR,
+						  mode, p_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n", __FUNCTION__,
-                                                                    pf_info->slot, pf_info->vport, index, *p_cnt);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_cnt);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_1588_packet_drop_cnt_get);
 
-ZXIC_UINT32 dpp_stat_1588_enc_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt)
+ZXIC_UINT32 dpp_stat_1588_enc_packet_rx_cnt_get(DPP_PF_INFO_T *pf_info,
+												ZXIC_UINT32 index,
+												ZXIC_UINT32 mode,
+												ZXIC_UINT64 *p_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(p_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_1588_ENC_PACKET_RX_CNT_ERAM_DEPTH - 1);
+	ZXIC_COMM_CHECK_POINT(p_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0,
+						  DPP_STAT_1588_ENC_PACKET_RX_CNT_ERAM_DEPTH - 1);
 
-    rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_1588_ENC_PACKET_RX_CNT_ERAM_BAADDR, mode, p_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
+	rc = dpp_stat_cnt_get(pf_info,
+						  index + DPP_STAT_1588_ENC_PACKET_RX_CNT_ERAM_BAADDR,
+						  mode, p_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n", __FUNCTION__,
-                                                                    pf_info->slot, pf_info->vport, index, *p_cnt);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_cnt);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_1588_enc_packet_rx_cnt_get);
 
-ZXIC_UINT32 dpp_stat_1588_enc_packet_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt)
+ZXIC_UINT32 dpp_stat_1588_enc_packet_tx_cnt_get(DPP_PF_INFO_T *pf_info,
+												ZXIC_UINT32 index,
+												ZXIC_UINT32 mode,
+												ZXIC_UINT64 *p_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(p_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_1588_ENC_PACKET_TX_CNT_ERAM_DEPTH - 1);
+	ZXIC_COMM_CHECK_POINT(p_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0,
+						  DPP_STAT_1588_ENC_PACKET_TX_CNT_ERAM_DEPTH - 1);
 
-    rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_1588_ENC_PACKET_TX_CNT_ERAM_BAADDR, mode, p_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
+	rc = dpp_stat_cnt_get(pf_info,
+						  index + DPP_STAT_1588_ENC_PACKET_TX_CNT_ERAM_BAADDR,
+						  mode, p_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n", __FUNCTION__,
-                                                                    pf_info->slot, pf_info->vport, index, *p_cnt);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_cnt);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_1588_enc_packet_tx_cnt_get);
 
-ZXIC_UINT32 dpp_stat_spoof_packet_drop_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt)
+ZXIC_UINT32 dpp_stat_spoof_packet_drop_cnt_get(DPP_PF_INFO_T *pf_info,
+											   ZXIC_UINT32 index,
+											   ZXIC_UINT32 mode,
+											   ZXIC_UINT64 *p_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(p_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_SPOOF_PACKET_DROP_CNT_ERAM_DEPTH - 1);
+	ZXIC_COMM_CHECK_POINT(p_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0,
+						  DPP_STAT_SPOOF_PACKET_DROP_CNT_ERAM_DEPTH - 1);
 
-    rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_SPOOF_PACKET_DROP_CNT_ERAM_BAADDR, mode, p_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
+	rc = dpp_stat_cnt_get(pf_info,
+						  index + DPP_STAT_SPOOF_PACKET_DROP_CNT_ERAM_BAADDR,
+						  mode, p_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
 
-    return DPP_OK;
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_cnt);
+
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_spoof_packet_drop_cnt_get);
 
-ZXIC_UINT32 dpp_stat_mcode_packet_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt)
+ZXIC_UINT32 dpp_stat_mcode_packet_cnt_get(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 index, ZXIC_UINT32 mode,
+										  ZXIC_UINT64 *p_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(p_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_MCODE_PACKET_CNT_ERAM_DEPTH - 1);
+	ZXIC_COMM_CHECK_POINT(p_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_MCODE_PACKET_CNT_ERAM_DEPTH - 1);
 
-    rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_MCODE_PACKET_CNT_ERAM_BAADDR, mode, p_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
+	rc = dpp_stat_cnt_get(pf_info,
+						  index + DPP_STAT_MCODE_PACKET_CNT_ERAM_BAADDR, mode,
+						  p_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n", __FUNCTION__,
-                                                                    pf_info->slot, pf_info->vport, index, *p_cnt);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_cnt);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_mcode_packet_cnt_get);
 
-ZXIC_UINT32 dpp_stat_port_bc_packet_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt)
+ZXIC_UINT32 dpp_stat_port_bc_packet_tx_cnt_get(DPP_PF_INFO_T *pf_info,
+											   ZXIC_UINT32 index,
+											   ZXIC_UINT32 mode,
+											   ZXIC_UINT64 *p_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(p_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0,
+						  DPP_STAT_PORT_BC_PACKET_TX_CNT_ERAM_DEPTH - 1);
 
-    ZXIC_COMM_CHECK_POINT(p_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_PORT_BC_PACKET_TX_CNT_ERAM_DEPTH - 1);
+	rc = dpp_stat_cnt_get(pf_info,
+						  index + DPP_STAT_PORT_BC_PACKET_TX_CNT_ERAM_BAADDR,
+						  mode, p_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
 
-    rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_PORT_BC_PACKET_TX_CNT_ERAM_BAADDR, mode, p_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_cnt);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_port_bc_packet_tx_cnt_get);
 
-ZXIC_UINT32 dpp_stat_port_bc_packet_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_cnt)
+ZXIC_UINT32 dpp_stat_port_bc_packet_rx_cnt_get(DPP_PF_INFO_T *pf_info,
+											   ZXIC_UINT32 index,
+											   ZXIC_UINT32 mode,
+											   ZXIC_UINT64 *p_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(p_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0,
+						  DPP_STAT_PORT_BC_PACKET_RX_CNT_ERAM_DEPTH - 1);
 
-    ZXIC_COMM_CHECK_POINT(p_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_PORT_BC_PACKET_RX_CNT_ERAM_DEPTH - 1);
+	rc = dpp_stat_cnt_get(pf_info,
+						  index + DPP_STAT_PORT_BC_PACKET_RX_CNT_ERAM_BAADDR,
+						  mode, p_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
 
-    rc = dpp_stat_cnt_get(pf_info, index + DPP_STAT_PORT_BC_PACKET_RX_CNT_ERAM_BAADDR, mode, p_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get");
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_cnt);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_port_bc_packet_rx_cnt_get);
 
-ZXIC_UINT32 dpp_stat_port_RDMA_packet_msg_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt)
+ZXIC_UINT32 dpp_stat_port_RDMA_packet_msg_tx_cnt_get(DPP_PF_INFO_T *pf_info,
+													 ZXIC_UINT32 index,
+													 ZXIC_UINT32 mode,
+													 ZXIC_UINT64 *p_pkB_cnt,
+													 ZXIC_UINT64 *p_pk_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_POINT(p_pkB_cnt);
-    ZXIC_COMM_CHECK_POINT(p_pk_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_PORT_RDMA_PACKET_TX_CNT_ERAM_DEPTH - 1);
-
-    rc = dpp_stat_cnt_get_128(pf_info, index + DPP_STAT_PORT_RDMA_PACKET_TX_CNT_ERAM_BAADDR, mode, p_pkB_cnt, p_pk_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128");
-
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u h64_cnt: %llu success.\n", __FUNCTION__,
-                                                                    pf_info->slot, pf_info->vport, index, *p_pk_cnt);
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u l64_cnt: %llu success.\n", __FUNCTION__,
-                                                                    pf_info->slot, pf_info->vport, index, *p_pkB_cnt);
-
-    return DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(p_pkB_cnt);
+	ZXIC_COMM_CHECK_POINT(p_pk_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0,
+						  DPP_STAT_PORT_RDMA_PACKET_TX_CNT_ERAM_DEPTH - 1);
+
+	rc = dpp_stat_cnt_get_128(
+			pf_info, index + DPP_STAT_PORT_RDMA_PACKET_TX_CNT_ERAM_BAADDR, mode,
+			p_pkB_cnt, p_pk_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128");
+
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u h64_cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_pk_cnt);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u l64_cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_pkB_cnt);
+
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_port_RDMA_packet_msg_tx_cnt_get);
 
-ZXIC_UINT32 dpp_stat_port_RDMA_packet_msg_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt)
+ZXIC_UINT32 dpp_stat_port_RDMA_packet_msg_rx_cnt_get(DPP_PF_INFO_T *pf_info,
+													 ZXIC_UINT32 index,
+													 ZXIC_UINT32 mode,
+													 ZXIC_UINT64 *p_pkB_cnt,
+													 ZXIC_UINT64 *p_pk_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_POINT(p_pkB_cnt);
-    ZXIC_COMM_CHECK_POINT(p_pk_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_PORT_RDMA_PACKET_RX_CNT_ERAM_DEPTH - 1);
-
-    rc = dpp_stat_cnt_get_128(pf_info, index + DPP_STAT_PORT_RDMA_PACKET_RX_CNT_ERAM_BAADDR, mode, p_pkB_cnt, p_pk_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128");
-
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u h64_cnt: %llu success.\n", __FUNCTION__,
-                                                                    pf_info->slot, pf_info->vport, index, *p_pk_cnt);
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x index: %u l64_cnt: %llu success.\n", __FUNCTION__,
-                                                                    pf_info->slot, pf_info->vport, index, *p_pkB_cnt);
-
-    return DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(p_pkB_cnt);
+	ZXIC_COMM_CHECK_POINT(p_pk_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0,
+						  DPP_STAT_PORT_RDMA_PACKET_RX_CNT_ERAM_DEPTH - 1);
+
+	rc = dpp_stat_cnt_get_128(
+			pf_info, index + DPP_STAT_PORT_RDMA_PACKET_RX_CNT_ERAM_BAADDR, mode,
+			p_pkB_cnt, p_pk_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128");
+
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u h64_cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_pk_cnt);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u l64_cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_pkB_cnt);
+
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_port_RDMA_packet_msg_rx_cnt_get);
 
-ZXIC_UINT32 dpp_stat_plcr_packet_drop_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt)
+ZXIC_UINT32 dpp_stat_plcr_packet_drop_tx_cnt_get(DPP_PF_INFO_T *pf_info,
+												 ZXIC_UINT32 index,
+												 ZXIC_UINT32 mode,
+												 ZXIC_UINT64 *p_pkB_cnt,
+												 ZXIC_UINT64 *p_pk_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_POINT(p_pkB_cnt);
-    ZXIC_COMM_CHECK_POINT(p_pk_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_PLCR_PACKET_DROP_TX_CNT_ERAM_DEPTH - 1);
-
-    rc = dpp_stat_cnt_get_128(pf_info, index + DPP_STAT_PLCR_PACKET_DROP_TX_CNT_ERAM_BAADDR, mode, p_pkB_cnt, p_pk_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128");
-
-    return DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(p_pkB_cnt);
+	ZXIC_COMM_CHECK_POINT(p_pk_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0,
+						  DPP_STAT_PLCR_PACKET_DROP_TX_CNT_ERAM_DEPTH - 1);
+
+	rc = dpp_stat_cnt_get_128(
+			pf_info, index + DPP_STAT_PLCR_PACKET_DROP_TX_CNT_ERAM_BAADDR, mode,
+			p_pkB_cnt, p_pk_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128");
+
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u h64_cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_pk_cnt);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u l64_cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_pkB_cnt);
+
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_plcr_packet_drop_tx_cnt_get);
 
-ZXIC_UINT32 dpp_stat_plcr_packet_drop_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt)
+ZXIC_UINT32 dpp_stat_plcr_packet_drop_rx_cnt_get(DPP_PF_INFO_T *pf_info,
+												 ZXIC_UINT32 index,
+												 ZXIC_UINT32 mode,
+												 ZXIC_UINT64 *p_pkB_cnt,
+												 ZXIC_UINT64 *p_pk_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_POINT(p_pkB_cnt);
-    ZXIC_COMM_CHECK_POINT(p_pk_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_PLCR_PACKET_DROP_RX_CNT_ERAM_DEPTH - 1);
-
-    rc = dpp_stat_cnt_get_128(pf_info, index + DPP_STAT_PLCR_PACKET_DROP_RX_CNT_ERAM_BAADDR, mode, p_pkB_cnt, p_pk_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128");
-
-    return DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(p_pkB_cnt);
+	ZXIC_COMM_CHECK_POINT(p_pk_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0,
+						  DPP_STAT_PLCR_PACKET_DROP_RX_CNT_ERAM_DEPTH - 1);
+
+	rc = dpp_stat_cnt_get_128(
+			pf_info, index + DPP_STAT_PLCR_PACKET_DROP_RX_CNT_ERAM_BAADDR, mode,
+			p_pkB_cnt, p_pk_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128");
+
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u h64_cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_pk_cnt);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u l64_cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_pkB_cnt);
+
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_plcr_packet_drop_rx_cnt_get);
 
-ZXIC_UINT32 dpp_stat_MTU_packet_msg_tx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt)
+ZXIC_UINT32 dpp_stat_MTU_packet_msg_tx_cnt_get(DPP_PF_INFO_T *pf_info,
+											   ZXIC_UINT32 index,
+											   ZXIC_UINT32 mode,
+											   ZXIC_UINT64 *p_pkB_cnt,
+											   ZXIC_UINT64 *p_pk_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_POINT(p_pkB_cnt);
-    ZXIC_COMM_CHECK_POINT(p_pk_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_MTU_PACKET_DROP_TX_CNT_ERAM_DEPTH - 1);
-
-    rc = dpp_stat_cnt_get_128(pf_info, index + DPP_STAT_MTU_PACKET_DROP_TX_CNT_ERAM_BAADDR, mode, p_pkB_cnt, p_pk_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128");
-
-    return DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(p_pkB_cnt);
+	ZXIC_COMM_CHECK_POINT(p_pk_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0,
+						  DPP_STAT_MTU_PACKET_DROP_TX_CNT_ERAM_DEPTH - 1);
+
+	rc = dpp_stat_cnt_get_128(
+			pf_info, index + DPP_STAT_MTU_PACKET_DROP_TX_CNT_ERAM_BAADDR, mode,
+			p_pkB_cnt, p_pk_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128");
+
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u h64_cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_pk_cnt);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u l64_cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_pkB_cnt);
+
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_MTU_packet_msg_tx_cnt_get);
 
-ZXIC_UINT32 dpp_stat_MTU_packet_msg_rx_cnt_get(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 index, ZXIC_UINT32 mode, ZXIC_UINT64 *p_pkB_cnt, ZXIC_UINT64 *p_pk_cnt)
+ZXIC_UINT32 dpp_stat_MTU_packet_msg_rx_cnt_get(DPP_PF_INFO_T *pf_info,
+											   ZXIC_UINT32 index,
+											   ZXIC_UINT32 mode,
+											   ZXIC_UINT64 *p_pkB_cnt,
+											   ZXIC_UINT64 *p_pk_cnt)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-
-    ZXIC_COMM_CHECK_POINT(p_pkB_cnt);
-    ZXIC_COMM_CHECK_POINT(p_pk_cnt);
-    ZXIC_COMM_CHECK_INDEX(index, 0, DPP_STAT_MTU_PACKET_DROP_RX_CNT_ERAM_DEPTH - 1);
-
-    rc = dpp_stat_cnt_get_128(pf_info, index + DPP_STAT_MTU_PACKET_DROP_RX_CNT_ERAM_BAADDR, mode, p_pkB_cnt, p_pk_cnt);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128");
-
-    return DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
+
+	ZXIC_COMM_CHECK_POINT(p_pkB_cnt);
+	ZXIC_COMM_CHECK_POINT(p_pk_cnt);
+	ZXIC_COMM_CHECK_INDEX(index, 0,
+						  DPP_STAT_MTU_PACKET_DROP_RX_CNT_ERAM_DEPTH - 1);
+
+	rc = dpp_stat_cnt_get_128(
+			pf_info, index + DPP_STAT_MTU_PACKET_DROP_RX_CNT_ERAM_BAADDR, mode,
+			p_pkB_cnt, p_pk_cnt);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_stat_cnt_get_128");
+
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u h64_cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_pk_cnt);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x index: %u l64_cnt: %llu success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, index, *p_pkB_cnt);
+
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_stat_MTU_packet_msg_rx_cnt_get);
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_tm.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_tm.c
index 735d7ff555ec31af503a95cc3cc9e0a9ebfcd777..a7efe8929853f7e517c1060ad07e836943480cf9 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_tm.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_tm.c
@@ -7,169 +7,186 @@
 #include "dpp_apt_se_api.h"
 #include "dpp_tbl_api.h"
 
-ZXIC_UINT32 dpp_tm_flowid_pport_table_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 port, ZXIC_UINT32 flow_id)
+ZXIC_UINT32 dpp_tm_flowid_pport_table_set(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 port, ZXIC_UINT32 flow_id)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = PANEL_FLAG_TM_BASE_QUEUE;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = PANEL_FLAG_TM_BASE_QUEUE;
 
-    rc = dpp_panel_attr_set(pf_info, port, attr, flow_id);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
+	rc = dpp_panel_attr_set(pf_info, port, attr, flow_id);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_tm_flowid_pport_table_set);
 
-ZXIC_UINT32 dpp_tm_flowid_pport_table_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT8 port)
+ZXIC_UINT32 dpp_tm_flowid_pport_table_del(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 port)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    rc = dpp_tm_flowid_pport_table_set(pf_info, port, TM_BASE_QUEUE_VALID);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_tm_flowid_pport_table_set");
+	rc = dpp_tm_flowid_pport_table_set(pf_info, port, TM_BASE_QUEUE_VALID);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_tm_flowid_pport_table_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_tm_flowid_pport_table_del);
 
-ZXIC_UINT32 dpp_tm_pport_trust_mode_table_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 mode)
+ZXIC_UINT32 dpp_tm_pport_trust_mode_table_set(DPP_PF_INFO_T *pf_info,
+											  ZXIC_UINT32 port,
+											  ZXIC_UINT32 mode)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = PANEL_FLAG_TRUST_MODE;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = PANEL_FLAG_TRUST_MODE;
 
-    rc = dpp_panel_attr_set(pf_info, port, attr, mode);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
+	rc = dpp_panel_attr_set(pf_info, port, attr, mode);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_tm_pport_trust_mode_table_set);
 
-ZXIC_UINT32 dpp_tm_pport_trust_mode_table_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port)
+ZXIC_UINT32 dpp_tm_pport_trust_mode_table_del(DPP_PF_INFO_T *pf_info,
+											  ZXIC_UINT32 port)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    rc = dpp_tm_pport_trust_mode_table_set(pf_info, port, TRUST_MODE_VALID);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_tm_pport_trust_mode_table_set");
+	rc = dpp_tm_pport_trust_mode_table_set(pf_info, port, TRUST_MODE_VALID);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_tm_pport_trust_mode_table_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_tm_pport_trust_mode_table_del);
 
-ZXIC_UINT32 dpp_tm_pport_dscp_map_table_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 dscp_id, ZXIC_UINT32 up_id)
+ZXIC_UINT32 dpp_tm_pport_dscp_map_table_set(DPP_PF_INFO_T *pf_info,
+											ZXIC_UINT32 port,
+											ZXIC_UINT32 dscp_id,
+											ZXIC_UINT32 up_id)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_DSCP_TO_UP_TABLE;
-    ZXIC_UINT32 index  = 0x3ff & ((port << 6) | (dscp_id & 0x3f));
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_DSCP_TO_UP_TABLE;
+	ZXIC_UINT32 index = 0x3ff & ((port << 6) | (dscp_id & 0x3f));
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_DSCP_TO_UP_T dscp_to_up = {0};
+	ZXDH_DSCP_TO_UP_T dscp_to_up = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u start.\n",
-                                                    __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u start.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    // dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &dscp_to_up);
+	// dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &dscp_to_up);
 
-    dscp_to_up.hit_flag    = 1;
-    dscp_to_up.up = up_id;
+	dscp_to_up.hit_flag = 1;
+	dscp_to_up.up = up_id;
 
-    rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &dscp_to_up);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
+	rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &dscp_to_up);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u success.\n",
-                                                    __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_tm_pport_dscp_map_table_set);
 
-ZXIC_UINT32 dpp_tm_pport_dscp_map_table_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 dscp_id)
+ZXIC_UINT32 dpp_tm_pport_dscp_map_table_del(DPP_PF_INFO_T *pf_info,
+											ZXIC_UINT32 port,
+											ZXIC_UINT32 dscp_id)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    rc = dpp_tm_pport_dscp_map_table_set(pf_info, port, dscp_id, UP_VALID);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_tm_pport_dscp_map_table_set");
+	rc = dpp_tm_pport_dscp_map_table_set(pf_info, port, dscp_id, UP_VALID);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_tm_pport_dscp_map_table_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_tm_pport_dscp_map_table_del);
 
-ZXIC_UINT32 dpp_tm_pport_up_map_table_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 up_id, ZXIC_UINT32 tc_id)
+ZXIC_UINT32 dpp_tm_pport_up_map_table_set(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 port, ZXIC_UINT32 up_id,
+										  ZXIC_UINT32 tc_id)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_UP_TO_TC_TABLE;
-    ZXIC_UINT32 index  = 0x7F & ((port << 3) | (up_id & 0x7));
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_UP_TO_TC_TABLE;
+	ZXIC_UINT32 index = 0x7F & ((port << 3) | (up_id & 0x7));
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_UP_TO_TC_T up_to_tc = {0};
+	ZXDH_UP_TO_TC_T up_to_tc = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u start.\n",
-                                                    __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u start.\n",
+					__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    // dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &up_to_tc);
+	// dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &up_to_tc);
 
-    up_to_tc.hit_flag    = 1;
-    up_to_tc.tc = tc_id;
+	up_to_tc.hit_flag = 1;
+	up_to_tc.tc = tc_id;
 
-    rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &up_to_tc);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
+	rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &up_to_tc);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u success.\n",
-                                                    __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u index: %u success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_tm_pport_up_map_table_set);
 
-ZXIC_UINT32 dpp_tm_pport_up_map_table_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32  port, ZXIC_UINT32 up_id)
+ZXIC_UINT32 dpp_tm_pport_up_map_table_del(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 port, ZXIC_UINT32 up_id)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    rc = dpp_tm_pport_up_map_table_set(pf_info, port, up_id, TC_VALID);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_tm_pport_dscp_map_table_set");
+	rc = dpp_tm_pport_up_map_table_set(pf_info, port, up_id, TC_VALID);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_tm_pport_dscp_map_table_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_tm_pport_up_map_table_del);
 
-ZXIC_UINT32 dpp_tm_pport_mcode_switch_set(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port, ZXIC_UINT32 mode)
+ZXIC_UINT32 dpp_tm_pport_mcode_switch_set(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 port, ZXIC_UINT32 mode)
 {
-    ZXIC_UINT32 rc   = DPP_OK;
-    ZXIC_UINT32 attr = PANEL_FLAG_TM_SHAPE_ENABLE;
+	ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 attr = PANEL_FLAG_TM_SHAPE_ENABLE;
 
-    rc = dpp_panel_attr_set(pf_info, port, attr, mode);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
+	rc = dpp_panel_attr_set(pf_info, port, attr, mode);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_panel_attr_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_tm_pport_mcode_switch_set);
 
-ZXIC_UINT32 dpp_tm_pport_mcode_switch_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 port)
+ZXIC_UINT32 dpp_tm_pport_mcode_switch_del(DPP_PF_INFO_T *pf_info,
+										  ZXIC_UINT32 port)
 {
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    rc = dpp_tm_pport_mcode_switch_set(pf_info, port, TM_SWITCH_OFF);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_tm_pport_mcode_switch_set");
+	rc = dpp_tm_pport_mcode_switch_set(pf_info, port, TM_SWITCH_OFF);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_tm_pport_mcode_switch_set");
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_tm_pport_mcode_switch_del);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_vhca.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_vhca.c
index ee81c056f7ea3362be741574841a31f345e0e84d..a3ad70ce4ef7dc8f763501feebdedd4afd7f5dbc 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_vhca.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_vhca.c
@@ -13,69 +13,73 @@
 #include "dpp_tbl_port.h"
 
 // ZXIC_UINT32 dpp_vport_vhca_id_add(ZXIC_UINT16 vport, ZXIC_UINT32 vhca_id, ZXIC_UINT32 vqm_vfid)
-ZXIC_UINT32 dpp_vport_vhca_id_add(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 vhca_id)
+ZXIC_UINT32 dpp_vport_vhca_id_add(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 vhca_id)
 {
-    ZXIC_UINT32 rc = DPP_OK;
-    DPP_DEV_T dev = {0};
+	ZXIC_UINT32 rc = DPP_OK;
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_VHCA_TABLE;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_VHCA_TABLE;
 
-    ZXDH_VHCA_T vhca_entry = {0};
+	ZXDH_VHCA_T vhca_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u vhca_id: %u start.\n", __FUNCTION__,
-                                                pf_info->slot, pf_info->vport, sdt_no, vhca_id);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u vhca_id: %u start.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, vhca_id);
 
-    ZXIC_COMM_MEMSET(&vhca_entry, 0, sizeof(ZXDH_VHCA_T));
+	ZXIC_COMM_MEMSET(&vhca_entry, 0, sizeof(ZXDH_VHCA_T));
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    vhca_entry.valid = 1;
-    vhca_entry.vqm_vfid = VQM_VFID(pf_info->vport);
+	vhca_entry.valid = 1;
+	vhca_entry.vqm_vfid = VQM_VFID(pf_info->vport);
 
-    rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, vhca_id, &vhca_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
+	rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, vhca_id, &vhca_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u vhca_id: %u success.\n", __FUNCTION__,
-                                                  pf_info->slot, pf_info->vport, sdt_no, vhca_id);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u vhca_id: %u success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, vhca_id);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_vhca_id_add);
 
-ZXIC_UINT32 dpp_vport_vhca_id_del(DPP_PF_INFO_T* pf_info, ZXIC_UINT32 vhca_id)
+ZXIC_UINT32 dpp_vport_vhca_id_del(DPP_PF_INFO_T *pf_info, ZXIC_UINT32 vhca_id)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue  = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_VHCA_TABLE;
-    ZXIC_UINT32 rc     = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_VHCA_TABLE;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u vhca_id: %u start.\n", __FUNCTION__,
-                                                pf_info->slot, pf_info->vport, sdt_no, vhca_id);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u vhca_id: %u start.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, vhca_id);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_apt_dtb_eram_clear(&dev, queue, sdt_no, vhca_id);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_clear");
+	rc = dpp_apt_dtb_eram_clear(&dev, queue, sdt_no, vhca_id);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_clear");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u vhca_id: %u success.\n", __FUNCTION__,
-                                                  pf_info->slot, pf_info->vport, sdt_no, vhca_id);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u vhca_id: %u success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, vhca_id);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vport_vhca_id_del);
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_vlan.c b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_vlan.c
index 6266bbf2f588934f5f799c02e296ef6adba99e8c..5ff0764310b4c4fcdcc5a47d28acf42f5294634d 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_vlan.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_np/table/source/dpp_tbl_vlan.c
@@ -11,142 +11,154 @@
 #include "dpp_tbl_comm.h"
 #include "dpp_tbl_vlan.h"
 
-ZXIC_UINT32 dpp_vlan_filter_init(DPP_PF_INFO_T* pf_info)
+ZXIC_UINT32 dpp_vlan_filter_init(DPP_PF_INFO_T *pf_info)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_VLAN_FILTER_TABLE;
-    ZXIC_UINT32 vlan_group_id = 0;
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_VLAN_FILTER_TABLE;
+	ZXIC_UINT32 vlan_group_id = 0;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_VLAN_FILTER_T vlan_filter_entry = {0};
+	ZXDH_VLAN_FILTER_T vlan_filter_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
-                                                                pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x start.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    ZXIC_COMM_MEMSET(&vlan_filter_entry, 0, sizeof(ZXDH_VLAN_FILTER_T));
+	ZXIC_COMM_MEMSET(&vlan_filter_entry, 0, sizeof(ZXDH_VLAN_FILTER_T));
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    vlan_filter_entry.hit_flag = 1;
+	vlan_filter_entry.hit_flag = 1;
 
-    for (vlan_group_id = 0; vlan_group_id < VLAN_GROUP_NUM; vlan_group_id++)
-    {
-        index = ((vlan_group_id << 11) | (VQM_VFID(pf_info->vport)));
-        rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &vlan_filter_entry);
-        ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
-    }
+	for (vlan_group_id = 0; vlan_group_id < VLAN_GROUP_NUM; vlan_group_id++) {
+		index = (vlan_group_id << 11) | (VQM_VFID(pf_info->vport));
+		rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index,
+									 &vlan_filter_entry);
+		ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
+	}
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
-                                                                pf_info->slot, pf_info->vport);
+	ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x success.\n", __FUNCTION__,
+					pf_info->slot, pf_info->vport);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_vlan_filter_init);
 
-ZXIC_UINT32 dpp_add_vlan_filter(DPP_PF_INFO_T* pf_info, ZXIC_UINT16 vlan_id)
+ZXIC_UINT32 dpp_add_vlan_filter(DPP_PF_INFO_T *pf_info, ZXIC_UINT16 vlan_id)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_VLAN_FILTER_TABLE;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_VLAN_FILTER_TABLE;
 
-    ZXIC_UINT32 vlan_group_id = vlan_id / VLAN_ID_NUM_IN_GROUP;
-    ZXIC_UINT32 vlan_remainder = vlan_id % VLAN_ID_NUM_IN_GROUP;
+	ZXIC_UINT32 vlan_group_id = vlan_id / VLAN_ID_NUM_IN_GROUP;
+	ZXIC_UINT32 vlan_remainder = vlan_id % VLAN_ID_NUM_IN_GROUP;
 
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_VLAN_FILTER_T vlan_filter_entry = {0};
+	ZXDH_VLAN_FILTER_T vlan_filter_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    index = ((vlan_group_id << 11) | (VQM_VFID(pf_info->vport)));
+	index = (vlan_group_id << 11) | (VQM_VFID(pf_info->vport));
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: 0x%04x group_id: %u vlan_id: %u start.\n",
-                         __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index, vlan_group_id, vlan_id);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u index: 0x%04x group_id: %u vlan_id: %u start.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index,
+			vlan_group_id, vlan_id);
 
-    ZXIC_COMM_MEMSET(&vlan_filter_entry, 0, sizeof(ZXDH_VLAN_FILTER_T));
+	ZXIC_COMM_MEMSET(&vlan_filter_entry, 0, sizeof(ZXDH_VLAN_FILTER_T));
 
-    ZXIC_COMM_CHECK_INDEX(vlan_id, 0, 4095);
+	ZXIC_COMM_CHECK_INDEX(vlan_id, 0, 4095);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &vlan_filter_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
+	rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &vlan_filter_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
 
-    vlan_filter_entry.hit_flag = 1;
-    vlan_filter_entry.vport_bitmap[vlan_remainder / 8] |= 1 << (7 - (vlan_remainder % 8));
+	vlan_filter_entry.hit_flag = 1;
+	vlan_filter_entry.vport_bitmap[vlan_remainder / 8] |=
+			1 << (7 - (vlan_remainder % 8));
 
-    rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &vlan_filter_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
+	rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index,
+								 &vlan_filter_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: 0x%04x group_id: %u vlan_id: %u success.\n",
-                           __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index, vlan_group_id, vlan_id);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u index: 0x%04x group_id: %u vlan_id: %u success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index,
+			vlan_group_id, vlan_id);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_add_vlan_filter);
 
-ZXIC_UINT32 dpp_del_vlan_filter(DPP_PF_INFO_T* pf_info, ZXIC_UINT16 vlan_id)
+ZXIC_UINT32 dpp_del_vlan_filter(DPP_PF_INFO_T *pf_info, ZXIC_UINT16 vlan_id)
 {
-    DPP_DEV_T dev = {0};
+	DPP_DEV_T dev = { 0 };
 
-    ZXIC_UINT32 dev_id = 0;
-    ZXIC_UINT32 queue = 0;
-    ZXIC_UINT32 sdt_no = ZXDH_SDT_VLAN_FILTER_TABLE;
+	ZXIC_UINT32 dev_id = 0;
+	ZXIC_UINT32 queue = 0;
+	ZXIC_UINT32 sdt_no = ZXDH_SDT_VLAN_FILTER_TABLE;
 
-    ZXIC_UINT32 vlan_group_id = vlan_id / VLAN_ID_NUM_IN_GROUP;
-    ZXIC_UINT32 vlan_remainder = vlan_id % VLAN_ID_NUM_IN_GROUP;
+	ZXIC_UINT32 vlan_group_id = vlan_id / VLAN_ID_NUM_IN_GROUP;
+	ZXIC_UINT32 vlan_remainder = vlan_id % VLAN_ID_NUM_IN_GROUP;
 
-    ZXIC_UINT32 index = 0;
-    ZXIC_UINT32 rc = DPP_OK;
+	ZXIC_UINT32 index = 0;
+	ZXIC_UINT32 rc = DPP_OK;
 
-    ZXDH_VLAN_FILTER_T vlan_filter_entry = {0};
+	ZXDH_VLAN_FILTER_T vlan_filter_entry = { 0 };
 
-    ZXIC_COMM_CHECK_POINT(pf_info);
+	ZXIC_COMM_CHECK_POINT(pf_info);
 
-    index = ((vlan_group_id << 11) | (VQM_VFID(pf_info->vport)));
+	index = (vlan_group_id << 11) | (VQM_VFID(pf_info->vport));
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: 0x%04x group_id: %u vlan_id: %u start.\n",
-                         __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index, vlan_group_id, vlan_id);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u index: 0x%04x group_id: %u vlan_id: %u start.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index,
+			vlan_group_id, vlan_id);
 
-    ZXIC_COMM_MEMSET(&vlan_filter_entry, 0, sizeof(ZXDH_VLAN_FILTER_T));
+	ZXIC_COMM_MEMSET(&vlan_filter_entry, 0, sizeof(ZXDH_VLAN_FILTER_T));
 
-    ZXIC_COMM_CHECK_INDEX(vlan_id, 0, 4095);
+	ZXIC_COMM_CHECK_INDEX(vlan_id, 0, 4095);
 
-    rc = dpp_dev_get(dev_id, pf_info, &dev);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
+	rc = dpp_dev_get(dev_id, pf_info, &dev);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dev_get");
 
-    rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
+	rc = dpp_dtb_queue_id_get(dev_id, pf_info, &queue);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_dtb_queue_id_get");
 
-    rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &vlan_filter_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
+	rc = dpp_apt_dtb_eram_get(&dev, queue, sdt_no, index, &vlan_filter_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_get");
 
-    vlan_filter_entry.hit_flag = 1;
-    vlan_filter_entry.vport_bitmap[vlan_remainder / 8] &= ~(1 << (7 - (vlan_remainder % 8)));
+	vlan_filter_entry.hit_flag = 1;
+	vlan_filter_entry.vport_bitmap[vlan_remainder / 8] &=
+			~(1 << (7 - (vlan_remainder % 8)));
 
-    rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index, &vlan_filter_entry);
-    ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
+	rc = dpp_apt_dtb_eram_insert(&dev, queue, sdt_no, index,
+								 &vlan_filter_entry);
+	ZXIC_COMM_CHECK_RC(rc, "dpp_apt_dtb_eram_insert");
 
-    ZXIC_COMM_PRINT("[%s] slot: %u vport: 0x%04x sdt_no: %u index: 0x%04x group_id: %u vlan_id: %u success.\n",
-                           __FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index, vlan_group_id, vlan_id);
+	ZXIC_COMM_PRINT(
+			"[%s] slot: %u vport: 0x%04x sdt_no: %u index: 0x%04x group_id: %u vlan_id: %u success.\n",
+			__FUNCTION__, pf_info->slot, pf_info->vport, sdt_no, index,
+			vlan_group_id, vlan_id);
 
-    return DPP_OK;
+	return DPP_OK;
 }
 EXPORT_SYMBOL(dpp_del_vlan_filter);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf.c b/src/net/drivers/net/ethernet/dinghai/en_pf.c
old mode 100755
new mode 100644
index 9b71b3dcbfb733c290bbceacedbe97863c7b2246..9285998ca33de2b2e0b84f53576484fa169c0634
--- a/src/net/drivers/net/ethernet/dinghai/en_pf.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_pf.c
@@ -1,2275 +1,2089 @@
-#include <linux/module.h>
-#include <linux/kmod.h>
-#include <linux/pci.h>
-#include <linux/aer.h>
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/lag.h>
-#include <net/devlink.h>
-#include <linux/dinghai/devlink.h>
-#include <linux/dinghai/helper.h>
-#include <linux/dinghai/dh_cmd.h>
-#include "en_pf.h"
-#include "./en_pf/irq.h"
-#include "./en_pf/eq.h"
-#include "./en_pf/events.h"
-#include "en_aux.h"
-#include "en_sf.h"
-#include "en_np/init/include/dpp_np_init.h"
-#include "en_pf/msg_func.h"
-#include "msg_common.h"
-
-#ifdef CONFIG_ZXDH_SF
-#include <linux/dinghai/en_sf.h>
-#endif
-
-#ifdef DRIVER_VERSION_VAL
-    #define DRV_VERSION DRIVER_VERSION_VAL
-#else
-    #define DRV_VERSION "1.0-1"
-#endif
-
-#define DRV_SUMMARY "ZTE(R) zxdh-net driver"
-
-const char zxdh_pf_driver_version[] = DRV_VERSION;
-static const char zxdh_pf_driver_string[] = DRV_SUMMARY;
-static const char zxdh_pf_copyright[] = "Copyright (c) 2022-23, ZTE Corporation.";
-
-MODULE_AUTHOR("ZTE Corporation");
-MODULE_DESCRIPTION(DRV_SUMMARY);
-MODULE_VERSION(DRV_VERSION);
-MODULE_LICENSE("Dual BSD/GPL");
-
-uint32_t dh_debug_mask;
-module_param_named(debug_mask, dh_debug_mask, uint, 0644);
-MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
-
-static const struct pci_device_id dh_pf_pci_table[] = {
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_VF_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_BSI_VENDOR_ID, ZXDH_PF_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_BSI_VENDOR_ID, ZXDH_VF_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_INICA_BOND_DEVICE_ID), 0 },   /* bond */
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_INICB_BOND_DEVICE_ID), 0 },   /* bond */
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_DPUA_BOND_DEVICE_ID), 0 },    /* bond */
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_INICA_UPF_BOND_DEVICE_ID), 0 },    /* bond */
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_E310_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_VF_E310_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_E312_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_VF_E312_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_DPUB_NOF_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_DPUB_PF_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_DPUB_INITIATOR1_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_DPUB_INITIATOR2_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_DPUB_RDMA_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_VF_DPUB_RDMA_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_UPF_PF_I512_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_UPF_VF_I512_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_INICA_RDMA_PF_DEVICE_ID), 0 },
-    { PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_INICA_RDMA_VF_DEVICE_ID), 0 },
-    { 0, }
-};
-
-MODULE_DEVICE_TABLE(pci, dh_pf_pci_table);
-
-extern struct devlink_ops dh_pf_devlink_ops;
-extern struct dh_core_devlink_ops dh_pf_core_devlink_ops;
-
-#ifdef PTP_DRIVER_INTERFACE_EN
-int zxdh_ptp_init(struct dh_core_dev *zxdev);
-void zxdh_ptp_stop(struct dh_core_dev *zxdev);
-#endif
-
-int32_t dh_pf_pci_init(struct dh_core_dev *dev)
-{
-    int32_t ret = 0;
-    struct zxdh_pf_device *pf_dev = NULL;
-
-    pci_set_drvdata(dev->pdev, dev);
-
-    ret = pci_enable_device(dev->pdev);
-    if (ret != 0)
-    {
-        LOG_ERR("pci_enable_device failed: %d\n", ret);
-        return -ENOMEM;
-    }
-
-    ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(64));
-    if (ret != 0)
-    {
-        ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(32));
-        if (ret != 0)
-        {
-            LOG_ERR("dma_set_mask_and_coherent failed: %d\n", ret);
-            goto err_pci;
-        }
-    }
-
-    ret = pci_request_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM), "dh-pf");
-    if (ret != 0)
-    {
-        LOG_ERR("pci_request_selected_regions failed: %d\n", ret);
-        goto err_pci;
-    }
-
-    pci_enable_pcie_error_reporting(dev->pdev);
-    pci_set_master(dev->pdev);
-    ret = pci_save_state(dev->pdev);
-    if (ret != 0)
-    {
-        LOG_ERR("pci_save_state failed: %d\n", ret);
-        goto err_pci_save_state;
-    }
-
-    pf_dev = dh_core_priv(dev);
-    pf_dev->pci_ioremap_addr[0] = (uint64_t)ioremap(pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0));
-    if (pf_dev->pci_ioremap_addr[0] == 0)
-    {
-        ret = -1;
-        LOG_ERR("ioremap(0x%llx, 0x%llx) failed\n", pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0));
-        goto err_pci_save_state;
-    }
-
-    return 0;
-
-err_pci_save_state:
-    pci_disable_pcie_error_reporting(dev->pdev);
-    pci_release_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM));
-err_pci:
-    pci_disable_device(dev->pdev);
-    return ret;
-}
-
-void dh_pf_pci_close(struct dh_core_dev *dev)
-{
-    struct zxdh_pf_device *pf_dev = NULL;
-
-    pf_dev = dh_core_priv(dev);
-    iounmap((void *)pf_dev->pci_ioremap_addr[0]);
-    pci_disable_pcie_error_reporting(dev->pdev);
-    pci_release_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM));
-    pci_disable_device(dev->pdev);
-
-    return;
-}
-
-int32_t zxdh_pf_pci_find_capability(struct pci_dev *pdev, uint8_t cfg_type, uint32_t ioresource_types, int32_t *bars)
-{
-    int32_t pos = 0;
-    uint8_t type = 0;
-    uint8_t bar = 0;
-
-    for (pos = pci_find_capability(pdev, PCI_CAP_ID_VNDR); pos > 0; pos = pci_find_next_capability(pdev, pos, PCI_CAP_ID_VNDR))
-    {
-        pci_read_config_byte(pdev, pos + offsetof(struct zxdh_pf_pci_cap, cfg_type), &type);
-        pci_read_config_byte(pdev, pos + offsetof(struct zxdh_pf_pci_cap, bar), &bar);
-
-        /* ignore structures with reserved BAR values */
-        if (bar > ZXDH_PF_MAX_BAR_VAL)
-        {
-            continue;
-        }
-
-        if (type == cfg_type)
-        {
-            if (pci_resource_len(pdev, bar) && pci_resource_flags(pdev, bar) & ioresource_types)
-            {
-                *bars |= (1 << bar);
-                return pos;
-            }
-        }
-    }
-
-    return 0;
-}
-
-void __iomem *zxdh_pf_map_capability(struct dh_core_dev *dh_dev, int32_t off,
-                                     size_t minlen, uint32_t align, uint32_t start,
-                                     uint32_t size, size_t *len, resource_size_t *pa)
-{
-    struct pci_dev *pdev = dh_dev->pdev;
-    uint8_t bar = 0;
-    uint32_t offset = 0;
-    uint32_t length = 0;
-    void __iomem *p = NULL;
-
-    pci_read_config_byte(pdev, off + offsetof(struct zxdh_pf_pci_cap, bar), &bar);
-    pci_read_config_dword(pdev, off + offsetof(struct zxdh_pf_pci_cap, offset), &offset);
-    pci_read_config_dword(pdev, off + offsetof(struct zxdh_pf_pci_cap, length), &length);
-
-    if (length <= start)
-    {
-        LOG_ERR("bad capability len %u (>%u expected)\n", length, start);
-        return NULL;
-    }
-
-    if (length - start < minlen)
-    {
-        LOG_ERR("bad capability len %u (>=%zu expected)\n", length, minlen);
-        return NULL;
-    }
-
-    length -= start;
-    if (start + offset < offset)
-    {
-        LOG_ERR("map wrap-around %u+%u\n", start, offset);
-        return NULL;
-    }
-
-    offset += start;
-    if (offset & (align - 1))
-    {
-        LOG_ERR("offset %u not aligned to %u\n", offset, align);
-        return NULL;
-    }
-
-    if (length > size)
-    {
-        length = size;
-    }
-
-    if (len)
-    {
-        *len = length;
-    }
-
-    if (minlen + offset < minlen || minlen + offset > pci_resource_len(pdev, bar))
-    {
-        LOG_ERR("map custom queue %zu@%u " "out of range on bar %i length %lu\n",
-            minlen, offset, bar, (unsigned long)pci_resource_len(pdev, bar));
-        return NULL;
-    }
-
-    p = pci_iomap_range(pdev, bar, offset, length);
-    if (unlikely(p == NULL))
-    {
-        LOG_ERR("unable to map custom queue %u@%u on bar %i\n", length, offset, bar);
-    }
-    else if (pa)
-    {
-        *pa = pci_resource_start(pdev, bar) + offset;
-    }
-
-    return p;
-}
-
-int32_t zxdh_pf_common_cfg_init(struct dh_core_dev *dh_dev)
-{
-    int32_t common = 0;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    struct pci_dev *pdev = dh_dev->pdev;
-
-    /* check for a common config: if not, use legacy mode (bar 0). */
-    common = zxdh_pf_pci_find_capability(pdev, ZXDH_PCI_CAP_COMMON_CFG, IORESOURCE_IO | IORESOURCE_MEM, &pf_dev->modern_bars);
-    if (common == 0)
-    {
-        LOG_ERR("missing capabilities %i, leaving for legacy driver\n", common);
-        return -ENODEV;
-    }
-
-    pf_dev->common = zxdh_pf_map_capability(dh_dev, common,
-                                            sizeof(struct zxdh_pf_pci_common_cfg), ZXDH_PF_ALIGN4, 0,
-                                            sizeof(struct zxdh_pf_pci_common_cfg), NULL, NULL);
-    if (unlikely(pf_dev->common == NULL))
-    {
-        LOG_ERR("pf_dev->common is null\n");
-        return -EINVAL;
-    }
-
-    return 0;
-}
-
-int32_t zxdh_pf_notify_cfg_init(struct dh_core_dev *dh_dev)
-{
-    int32_t notify = 0;
-    uint32_t notify_length = 0;
-    uint32_t notify_offset = 0;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    struct pci_dev *pdev = dh_dev->pdev;
-
-    /* If common is there, these should be too... */
-    notify = zxdh_pf_pci_find_capability(pdev, ZXDH_PCI_CAP_NOTIFY_CFG, IORESOURCE_IO | IORESOURCE_MEM, &pf_dev->modern_bars);
-    if (notify == 0)
-    {
-        LOG_ERR("missing capabilities %i\n", notify);
-        return -EINVAL;
-    }
-
-    pci_read_config_dword(pdev, notify + offsetof(struct zxdh_pf_pci_notify_cap, notify_off_multiplier), &pf_dev->notify_offset_multiplier);
-    pci_read_config_dword(pdev, notify + offsetof(struct zxdh_pf_pci_notify_cap, cap.length), &notify_length);
-    pci_read_config_dword(pdev, notify + offsetof(struct zxdh_pf_pci_notify_cap, cap.offset), &notify_offset);
-
-    /* We don't know how many VQs we'll map, ahead of the time.
-     * If notify length is small, map it all now. Otherwise, map each VQ individually later. */
-    if ((uint64_t)notify_length + (notify_offset % PAGE_SIZE) <= PAGE_SIZE)
-    {
-        pf_dev->notify_base = zxdh_pf_map_capability(dh_dev, notify, ZXDH_PF_MAP_MINLEN2, ZXDH_PF_ALIGN2,
-            0, notify_length, &pf_dev->notify_len, &pf_dev->notify_pa);
-        if (unlikely(pf_dev->notify_base == NULL))
-        {
-            LOG_ERR("pf_dev->notify_base is null\n");
-            return -EINVAL;
-        }
-    }
-    else
-    {
-        pf_dev->notify_map_cap = notify;
-    }
-
-    return 0;
-}
-
-int32_t zxdh_pf_device_cfg_init(struct dh_core_dev *dh_dev)
-{
-    int32_t device = 0;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    struct pci_dev *pdev = dh_dev->pdev;
-
-    /* Device capability is only mandatory for devices that have device-specific configuration. */
-    device = zxdh_pf_pci_find_capability(pdev, ZXDH_PCI_CAP_DEVICE_CFG, IORESOURCE_IO | IORESOURCE_MEM, &pf_dev->modern_bars);
-
-    /* we don't know how much we should map, but PAGE_SIZE is more than enough for all existing devices. */
-    if (device)
-    {
-        pf_dev->device = zxdh_pf_map_capability(dh_dev, device, 0, ZXDH_PF_ALIGN4, 0, PAGE_SIZE, &pf_dev->device_len, NULL);
-        if (unlikely(pf_dev->device == NULL))
-        {
-            LOG_ERR("pf_dev->device is null\n");
-            return -EINVAL;
-        }
-    }
-    return 0;
-}
-
-void zxdh_pf_modern_cfg_uninit(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    struct pci_dev *pdev = dh_dev->pdev;
-
-    if (pf_dev->device)
-    {
-        pci_iounmap(pdev, pf_dev->device);
-    }
-    if (pf_dev->notify_base)
-    {
-        pci_iounmap(pdev, pf_dev->notify_base);
-    }
-    pci_iounmap(pdev, pf_dev->common);
-}
-
-int32_t zxdh_pf_modern_cfg_init(struct dh_core_dev *dh_dev)
-{
-    int32_t ret = 0;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    struct pci_dev *pdev = dh_dev->pdev;
-
-    ret = zxdh_pf_common_cfg_init(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_pf_common_cfg_init failed: %d\n", ret);
-        return -EINVAL;
-    }
-
-    ret = zxdh_pf_notify_cfg_init(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_pf_notify_cfg_init failed: %d\n", ret);
-        goto err_map_notify;
-    }
-
-    ret = zxdh_pf_device_cfg_init(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_pf_device_cfg_init failed: %d\n", ret);
-        goto err_map_device;
-    }
-
-    return 0;
-
-err_map_device:
-    if (pf_dev->notify_base)
-    {
-        pci_iounmap(pdev, pf_dev->notify_base);
-    }
-err_map_notify:
-    pci_iounmap(pdev, pf_dev->common);
-    return -EINVAL;
-}
-
-uint16_t zxdh_pf_get_queue_notify_off(struct dh_core_dev *dh_dev, uint16_t index)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    iowrite16(index, &pf_dev->common->queue_select);
-
-    return ioread16(&pf_dev->common->queue_notify_off);
-}
-
-void __iomem * zxdh_pf_map_vq_notify(struct dh_core_dev *dh_dev, uint32_t index, resource_size_t *pa)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    uint16_t off = 0;
-
-    off = zxdh_pf_get_queue_notify_off(dh_dev, index);
-
-    if (pf_dev->notify_base)
-    {
-        /* offset should not wrap */
-        if ((uint64_t)off * pf_dev->notify_offset_multiplier + 2 > pf_dev->notify_len)
-        {
-            LOG_ERR("bad notification offset %u (x %u) " "for queue %u > %zd",
-                    off, pf_dev->notify_offset_multiplier, index, pf_dev->notify_len);
-            return NULL;
-        }
-
-        if (pa)
-        {
-            *pa = pf_dev->notify_pa + off * pf_dev->notify_offset_multiplier;
-        }
-
-        return pf_dev->notify_base + off * pf_dev->notify_offset_multiplier;
-    }
-    else
-    {
-        return zxdh_pf_map_capability(dh_dev, pf_dev->notify_map_cap, 2, 2,
-                                      off * pf_dev->notify_offset_multiplier, 2, NULL, pa);
-    }
-}
-
-void zxdh_pf_unmap_vq_notify(struct dh_core_dev *dh_dev, void *priv)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    if (!pf_dev->notify_base)
-    {
-        pci_iounmap(dh_dev->pdev, priv);
-    }
-}
-
-void zxdh_pf_set_status(struct dh_core_dev *dh_dev, uint8_t status)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    iowrite8(status, &pf_dev->common->device_status);
-
-    return;
-}
-
-uint8_t zxdh_pf_get_status(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    return ioread8(&pf_dev->common->device_status);
-}
-
-void zxdh_pf_get_vf_mac(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id)
-{
-    uint32_t DEV_MAC_L = 0;
-    uint16_t DEV_MAC_H = 0;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    DEV_MAC_L = ioread32((const void __iomem *)(pf_dev->pf_sriov_cap_base + (pf_dev->sriov_bar_size) * vf_id + ZXDH_DEV_MAC_LOW_OFFSET));
-    mac[0] = DEV_MAC_L & 0xff;
-    mac[1] = (DEV_MAC_L >> 8) & 0xff;
-    mac[2] = (DEV_MAC_L >> 16) & 0xff;
-    mac[3] = (DEV_MAC_L >> 24) & 0xff;
-    DEV_MAC_H = ioread16((const void __iomem *)(pf_dev->pf_sriov_cap_base + (pf_dev->sriov_bar_size) * vf_id + ZXDH_DEV_MAC_HIGH_OFFSET));
-    mac[4] = DEV_MAC_H & 0xff;
-    mac[5] = (DEV_MAC_H >> 8) & 0xff;
-    return;
-}
-
-void zxdh_pf_set_vf_mac(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id)
-{
-    uint32_t DEV_MAC_L = 0;
-    uint16_t DEV_MAC_H = 0;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    DEV_MAC_L = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
-    DEV_MAC_H = mac[4] | (mac[5] << 8);
-    iowrite32(DEV_MAC_L, (void __iomem *)(pf_dev->pf_sriov_cap_base + (pf_dev->sriov_bar_size) * vf_id + ZXDH_DEV_MAC_LOW_OFFSET));
-    iowrite16(DEV_MAC_H, (void __iomem *)(pf_dev->pf_sriov_cap_base + (pf_dev->sriov_bar_size) * vf_id + ZXDH_DEV_MAC_HIGH_OFFSET));
-    return;
-}
-
-void zxdh_set_mac(struct dh_core_dev *dh_dev, uint8_t *mac)
-{
-    uint32_t DEV_MAC_L = 0;
-    uint16_t DEV_MAC_H = 0;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    DEV_MAC_L = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
-    DEV_MAC_H = mac[4] | (mac[5] << 8);
-    iowrite32(DEV_MAC_L, (void __iomem *)(pf_dev->pci_ioremap_addr[0] + ZXDH_DEV_MAC_LOW_OFFSET));
-    iowrite16(DEV_MAC_H, (void __iomem *)(pf_dev->pci_ioremap_addr[0] + ZXDH_DEV_MAC_HIGH_OFFSET));
-    return;
-}
-
-void zxdh_get_mac(struct dh_core_dev *dh_dev, uint8_t *mac)
-{
-    uint32_t DEV_MAC_L = 0;
-    uint16_t DEV_MAC_H = 0;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    DEV_MAC_L = ioread32((void __iomem *)(pf_dev->pci_ioremap_addr[0] + ZXDH_DEV_MAC_LOW_OFFSET));
-    mac[0] = DEV_MAC_L & 0xff;
-    mac[1] = (DEV_MAC_L >> 8) & 0xff;
-    mac[2] = (DEV_MAC_L >> 16) & 0xff;
-    mac[3] = (DEV_MAC_L >> 24) & 0xff;
-    DEV_MAC_H = ioread16((void __iomem *)(pf_dev->pci_ioremap_addr[0] + ZXDH_DEV_MAC_HIGH_OFFSET));
-    mac[4] = DEV_MAC_H & 0xff;
-    mac[5] = (DEV_MAC_H >> 8) & 0xff;
-    return;
-}
-
-uint64_t zxdh_pf_get_features(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    uint64_t device_feature = 0;
-
-    iowrite32(0, &pf_dev->common->device_feature_select);
-    device_feature = ioread32(&pf_dev->common->device_feature);
-    iowrite32(1, &pf_dev->common->device_feature_select);
-    device_feature |= ((uint64_t)ioread32(&pf_dev->common->device_feature) << 32);
-
-    return device_feature;
-}
-
-void zxdh_pf_set_features(struct dh_core_dev *dh_dev, uint64_t features)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    iowrite32(0, &pf_dev->common->guest_feature_select);
-    iowrite32((uint32_t)features, &pf_dev->common->guest_feature);
-    iowrite32(1, &pf_dev->common->guest_feature_select);
-    iowrite32(features >> 32, &pf_dev->common->guest_feature);
-
-    return;
-}
-
-void zxdh_pf_set_queue_enable(struct dh_core_dev *dh_dev, uint16_t index, bool enable)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    iowrite16(index, &pf_dev->common->queue_select);
-    iowrite16(enable, &pf_dev->common->queue_enable);
-}
-
-uint32_t zxdh_pf_get_epbdf(struct dh_core_dev *dh_dev)
-{
-    struct pci_dev *pdev = dh_dev->pdev;
-    uint32_t domain = 0;
-    uint32_t bus = 0;
-    uint32_t devid = 0;
-    uint32_t function = 0;
-    uint32_t epbdf = 0;
-
-    if (pdev == NULL)
-    {
-        LOG_ERR("err: pdev null, return epbdf data 0.\n");
-        return 0;
-    }
-
-    if(sscanf(pci_name(pdev), "%x:%x:%x.%u", &domain, &bus, &devid, &function) != 4)
-    {
-        LOG_ERR("failed to get pcie bus-info\n");
-        return 0;
-    }
-    epbdf = BDF_ECAM(bus, devid, function);
-
-    return epbdf;
-}
-
-int zxdh_pf_get_pannel_port_num(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    return pf_dev->pannel_port_num;
-}
-
-uint16_t zxdh_pf_get_vport(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    return pf_dev->vport;
-}
-
-enum dh_coredev_type zxdh_pf_get_coredev_type(struct dh_core_dev *dh_dev)
-{
-    return dh_dev->coredev_type;
-}
-
-uint16_t zxdh_pf_get_pcie_id(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    return pf_dev->pcie_id;
-}
-
-uint16_t zxdh_pf_get_slot_id(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    return pf_dev->slot_id;
-}
-
-bool zxdh_pf_is_bond(struct dh_core_dev *dh_dev)
-{
-    bool flags = false;
-
-    if (!dh_core_is_pf(dh_dev))
-    {
-        return false;
-    }
-
-    if ((dh_dev->pdev->device == ZXDH_INICA_BOND_DEVICE_ID)
-        || (dh_dev->pdev->device == ZXDH_INICB_BOND_DEVICE_ID)
-        || (dh_dev->pdev->device == ZXDH_INICA_UPF_BOND_DEVICE_ID)
-        || (dh_dev->pdev->device == ZXDH_DPUA_BOND_DEVICE_ID))
-    {
-        flags = true;
-    }
-
-    return  flags;
-}
-
-bool zxdh_pf_is_upf(struct dh_core_dev *dh_dev)
-{
-    bool flags = false;
-
-    if ((dh_dev->pdev->device == ZXDH_UPF_PF_I512_DEVICE_ID)
-        || (dh_dev->pdev->device == ZXDH_UPF_VF_I512_DEVICE_ID))
-    {
-        flags = true;
-    }
-
-    return  flags;
-}
-
-struct zxdh_vf_item *zxdh_pf_get_vf_item(struct dh_core_dev *dh_dev, uint16_t vf_idx)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    if (dh_dev->coredev_type != DH_COREDEV_PF)
-    {
-        LOG_ERR("Invalid device\n");
-        return ERR_PTR(-EINVAL);
-    }
-
-    if (vf_idx >= ZXDH_VF_NUM_MAX)
-    {
-        LOG_ERR("vf idx(%u) out of range(0~255)\n", vf_idx);
-        return ERR_PTR(-EINVAL);
-    }
-
-    if (pf_dev->vf_item == NULL)
-    {
-        LOG_ERR("vf_item is NULL\n");
-        return ERR_PTR(-EINVAL);
-    }
-
-    if (!pf_dev->vf_item[vf_idx].enable)
-    {
-        LOG_ERR("vf(%u) is disable\n", vf_idx);
-        return ERR_PTR(-EINVAL);
-    }
-
-    return &(pf_dev->vf_item[vf_idx]);
-}
-
-int32_t zxdh_pf_dpp_init(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = pf_dev->slot_id;
-    pf_info.vport = pf_dev->vport;
-    return dpp_vport_register(&pf_info, dh_dev->pdev);
-}
-
-int32_t zxdh_pf_dpp_uninit(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = pf_dev->slot_id;
-    pf_info.vport = pf_dev->vport;
-    return dpp_vport_unregister(&pf_info);
-}
-
-void zxdh_pf_ip6mac_lock_init(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    if (dh_dev->coredev_type == DH_COREDEV_PF)
-    {
-        spin_lock_init(&pf_dev->vf_ip6mac_lock);
-    }
-}
-
-int32_t zxdh_init_ip6mac_tbl(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    struct zxdh_ipv6_mac_entry *ip6mac_entry_list = NULL;
-    unsigned int ip6mact_size = DEV_MULTICAST_MAX_NUM;
-    int i;
-
-    pf_dev->ip6mac_tbl = kvzalloc(struct_size(pf_dev->ip6mac_tbl, hash_list, ip6mact_size), GFP_KERNEL);
-    if (!pf_dev->ip6mac_tbl)
-    {
-        LOG_ERR("kvzalloc ip6mac_tbl failed\n");
-        return -ENOMEM;
-    }
-
-    pf_dev->ip6mac_tbl->ip6mact_size = ip6mact_size;
-
-    INIT_LIST_HEAD(&pf_dev->ip6mac_tbl->ip6mac_free_head);
-
-    rwlock_init(&pf_dev->ip6mac_tbl->lock);
-
-    for (i = 0; i < pf_dev->ip6mac_tbl->ip6mact_size; ++i)
-        INIT_LIST_HEAD(&pf_dev->ip6mac_tbl->hash_list[i]);
-
-    ip6mac_entry_list = kvcalloc(pf_dev->ip6mac_tbl->ip6mact_size, sizeof(struct zxdh_ipv6_mac_entry), GFP_KERNEL);
-    if (!ip6mac_entry_list) {
-        kvfree(pf_dev->ip6mac_tbl);
-        LOG_ERR("kvcalloc ip6mac_entry_list failed\n");
-        return -ENOMEM;
-    }
-    pf_dev->ip6mac_tbl->ip6mac_entry_list = (void *)ip6mac_entry_list;
-
-    for (i = 0; i < pf_dev->ip6mac_tbl->ip6mact_size; i++) {
-        INIT_LIST_HEAD(&ip6mac_entry_list[i].list);
-        list_add_tail(&ip6mac_entry_list[i].list, &pf_dev->ip6mac_tbl->ip6mac_free_head);
-    }
-
-    return 0;
-}
-
-void zxdh_cleanup_ip6mac_tbl(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    struct zxdh_ipv6_mac_tbl *ip6mac_tbl = pf_dev->ip6mac_tbl;
-
-    if (ip6mac_tbl)
-    {
-        if (ip6mac_tbl->ip6mac_entry_list)
-        {
-            kvfree(ip6mac_tbl->ip6mac_entry_list);
-            ip6mac_tbl->ip6mac_entry_list = NULL;
-        }
-        kvfree(ip6mac_tbl);
-        pf_dev->ip6mac_tbl = NULL;
-    }
-}
-
-void zxdh_pf_initialized_init(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    pf_dev->initialized_flags = 0;
-    spin_lock_init(&pf_dev->initialized_lock);
-}
-
-void zxdh_pf_initialized_uninit(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    pf_dev->initialized_flags = 0;
-}
-
-struct pci_dev *zxdh_pf_get_pdev(struct dh_core_dev *dh_dev)
-{
-    return dh_dev->pdev;
-}
-
-uint64_t zxdh_pf_get_bar_virt_addr(struct dh_core_dev *dh_dev, uint8_t bar_num)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    return pf_dev->pci_ioremap_addr[bar_num];
-}
-
-int32_t zxdh_pf_msg_send_cmd(struct dh_core_dev *dh_dev, uint16_t module_id, void *msg, void *ack, bool is_sync)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    zxdh_reps_info *reps = (zxdh_reps_info *)(ack);
-    uint64_t vaddr = 0;
-    int32_t err = 0;
-
-    vaddr = (uint64_t)ZXDH_BAR_MSG_BASE(pf_dev->pci_ioremap_addr[0]);
-
-    err = zxdh_send_command(vaddr, pf_dev->pcie_id, module_id, msg, ack, TRUE);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_send_command failed, err=%d\n", err);
-        return -1;
-    }
-
-    if (reps->flag != ZXDH_REPS_SUCC)
-    {
-        LOG_ERR("failed reps->flag: 0x%x\n", reps->flag);
-        return -1;
-    }
-
-    return err;
-}
-
-int32_t zxdh_pf_query_port(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    struct port_message_recv recv = {0};
-    struct port_message_recv *recv_data = &recv;
-    struct zxdh_port_msg msg = {0};
-    struct zxdh_port_msg *payload = &msg;
-    struct zxdh_pannle_port *pnlport, *recvport;
-    int32_t ret = 0, idx = 0;
-
-    payload->pcie_id = zxdh_pf_get_pcie_id(dh_dev);
-
-    ret = zxdh_pf_msg_send_cmd(dh_dev, MODULE_PHYPORT_QUERY, payload, recv_data, true);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_pf_query_port send message failed \n");
-        goto out;
-    }
-
-    pf_dev->port_resource.pannel_num = recv_data->port_num;
-
-    LOG_INFO("zxdh query port num: %u\n", (uint32_t)recv_data->port_num);
-    for (idx = 0; idx < recv_data->port_num; idx++)
-    {
-        if (idx >= ZXDH_PANNEL_PORT_MAX)
-        {
-            LOG_ERR("query port num from fw out of range. \n");
-            continue;
-        }
-
-        pnlport = &pf_dev->port_resource.port[idx];
-        recvport = (struct zxdh_pannle_port *)((uint8_t *)&recv_data->data[idx]);
-
-        pnlport->phyport = recvport->phyport;
-        pnlport->pannel_id = recvport->pannel_id;
-        pnlport->link_check_bit = recvport->link_check_bit;
-        pnlport->flags = 0;
-
-        LOG_INFO("[%d] pannel %u, phyport %u link check bit %u\n", idx,
-            (uint32_t)pnlport->pannel_id, (uint32_t)pnlport->phyport, (uint32_t)pnlport->link_check_bit);
-    }
-
-out:
-    return ret;
-}
-
-int32_t zxdh_pf_query_fwinfo(struct dh_core_dev *dh_dev)
-{
-    int32_t ret = 0;
-
-    ret = zxdh_pf_query_port(dh_dev);
-    if (ret != 0)
-    {
-        return ret;
-    }
-
-    return 0;
-}
-
-uint16_t zxdh_pf_get_queue_num(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    uint16_t qnum = 0;
-
-    qnum = ioread16(&pf_dev->common->num_queues);
-
-    return qnum;
-}
-
-uint16_t zxdh_pf_get_queue_size(struct dh_core_dev *dh_dev, uint16_t index)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    uint16_t queue_size = 0;
-
-    iowrite16(index, &pf_dev->common->queue_select);
-    queue_size = ioread16(&pf_dev->common->queue_size);
-
-    return queue_size;
-}
-
-uint16_t zxdh_pf_get_queue_vector(struct dh_core_dev *dh_dev, uint16_t channel, struct list_head * eqs_list, uint16_t queue_index)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    struct zxdh_pf_pci_common_cfg __iomem *cfg = pf_dev->common;
-    struct dh_eq_vqs *eq_vqs = NULL;
-    struct dh_eq_vqs *n;
-    int32_t i = 0;
-    int32_t msix_vec = ZXDH_MSI_NO_VECTOR;
-
-    iowrite16(queue_index, &cfg->queue_select);
-
-    list_for_each_entry_safe(eq_vqs, n, eqs_list, list)
-    {
-        if (i++ == channel)
-        {
-            iowrite16(eq_vqs->vq_s.core.irq->index, &cfg->queue_msix_vector);
-            break;
-        }
-    }
-
-    msix_vec = ioread16(&cfg->queue_msix_vector);
-
-    /* Flush the write out to device */
-    return msix_vec;
-}
-
-void zxdh_pf_release_queue_vector(struct dh_core_dev *dh_dev, int32_t queue_index)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    struct zxdh_pf_pci_common_cfg __iomem *cfg = pf_dev->common;
-
-    iowrite16(queue_index, &cfg->queue_select);
-    iowrite16(ZXDH_MSI_NO_VECTOR, &cfg->queue_msix_vector);
-}
-
-void zxdh_pf_set_queue_size(struct dh_core_dev *dh_dev, uint32_t index, uint16_t size)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    iowrite16(index, &pf_dev->common->queue_select);
-    iowrite16(size, &pf_dev->common->queue_size);
-}
-
-void zxdh_pf_set_queue_address(struct dh_core_dev *dh_dev, uint32_t index,
-                               uint64_t desc_addr, uint64_t driver_addr, uint64_t device_addr)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    iowrite16(index, &pf_dev->common->queue_select);
-    iowrite32((uint32_t)desc_addr, &pf_dev->common->queue_desc_lo);
-    iowrite32(desc_addr>>32, &pf_dev->common->queue_desc_hi);
-    iowrite32((uint32_t)driver_addr, &pf_dev->common->queue_avail_lo);
-    iowrite32(driver_addr>>32, &pf_dev->common->queue_avail_hi);
-    iowrite32((uint32_t)device_addr, &pf_dev->common->queue_used_lo);
-    iowrite32(device_addr>>32, &pf_dev->common->queue_used_hi);
-}
-
-int32_t zxdh_pf_get_vq_lock(struct dh_core_dev *dh_dev)
-{
-    int32_t i = 0;
-    int32_t val = 0;
-    int32_t wait_time = ZXDH_PF_WAIT_COUNT;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    for (i = 0; i < wait_time; i++)
-    {
-        val = ioread32((const void __iomem *)(pf_dev->pci_ioremap_addr[0] + VQM_HOST_BAR_OFFSET + LOCK_VQ_REG_OFFSET));
-        udelay(ZXDH_PF_DELAY_US);
-        if (val & ZXDH_PF_LOCK_ENABLE_MASK)
-        {
-            break;
-        }
-    }
-
-    if ((val & ZXDH_PF_LOCK_ENABLE_MASK) == 0)
-    {
-        LOG_INFO("get phy vq_id is busy\n");
-        return -1;
-    }
-
-    return 0;
-}
-
-int32_t zxdh_pf_release_vq_lock(struct dh_core_dev *dh_dev)
-{
-    int32_t val = 0;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    val = ioread32((const void __iomem *)(pf_dev->pci_ioremap_addr[0] + VQM_HOST_BAR_OFFSET + LOCK_VQ_REG_OFFSET));
-    if (val & ZXDH_PF_LOCK_ENABLE_MASK)
-    {
-        iowrite32(ZXDH_PF_RELEASE_LOCK_VAL, (void __iomem *)(pf_dev->pci_ioremap_addr[0] + VQM_HOST_BAR_OFFSET + LOCK_VQ_REG_OFFSET));
-        return 0;
-    }
-    else
-    {
-        LOG_INFO("no lock need to be released\n");
-        return -1;
-    }
-}
-
-int32_t zxdh_pf_get_phy_vq(struct dh_core_dev *dh_dev, uint16_t index)
-{
-    int32_t phy_vq_reg = 0;
-    int32_t vq_reg_num = ZXDH_MAX_QUEUES_NUM / ZXDH_PHY_REG_BITS;
-    uint32_t val = 0;
-    uint32_t done = 0;
-    uint8_t queue_type = 0;
-    int32_t j = 0;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    int32_t phy_index = 0;
-
-    for (phy_vq_reg = 0; phy_vq_reg < vq_reg_num; phy_vq_reg++)
-    {
-        val = ioread32((const void __iomem *)(pf_dev->pci_ioremap_addr[0] + PHY_VQ_REG_OFFSET + phy_vq_reg * 4));
-
-        if (index % ZXDH_PF_POWER_INDEX2 == 0)
-        {
-            queue_type = ZXDH_PF_RQ_TYPE;
-        }
-        else
-        {
-            queue_type = ZXDH_PF_TQ_TYPE;
-        }
-
-        for (j = queue_type; j < ZXDH_PHY_REG_BITS; j = j + ZXDH_PF_POWER_INDEX2)
-        {
-            if ((val & (ZXDH_PF_GET_PHY_INDEX_BIT << j)) == 0)
-            {
-                val |= (ZXDH_PF_GET_PHY_INDEX_BIT << j);
-                iowrite32(val, (void __iomem *)(pf_dev->pci_ioremap_addr[0] + PHY_VQ_REG_OFFSET + phy_vq_reg * 4));
-                phy_index = phy_vq_reg * ZXDH_PHY_REG_BITS + j;
-                done = ZXDH_PF_GET_PHY_INDEX_DONE;
-                break;
-            }
-        }
-
-        if (done == ZXDH_PF_GET_PHY_INDEX_DONE)
-        {
-            return phy_index;
-        }
-    }
-
-    LOG_INFO("no availd phy_index\n");
-
-    return -1;
-}
-
-int32_t zxdh_pf_release_phy_vq(struct dh_core_dev *dh_dev, uint32_t *phy_index, uint16_t total_qnum)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    uint16_t lch = 0;
-    uint16_t widx = 0;
-    uint16_t bidx = 0;
-    uint32_t val = 0;
-
-    for (lch = 0; lch < total_qnum; lch++)
-    {
-        if (phy_index[lch] >= ZXDH_MAX_QUEUES_NUM)
-        {
-            continue;
-        }
-
-        widx = phy_index[lch] / 32; //4byte -> 32bits
-        bidx = phy_index[lch] % 32;
-
-        udelay(ZXDH_PF_DELAY_US);
-        val = ioread32((const void __iomem *)(pf_dev->pci_ioremap_addr[0] + PHY_VQ_REG_OFFSET + widx * 4));
-        val &= ~(1 << bidx);
-        iowrite32(val, (void __iomem *)(pf_dev->pci_ioremap_addr[0] + PHY_VQ_REG_OFFSET + widx * 4));
-    }
-
-    return 0;
-}
-
-
-void zxdh_pf_update_link_info(struct dh_core_dev *dh_dev, struct link_info_struct *link_info_val)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    if(pf_dev->link_up && link_info_val->speed == SPEED_UNKNOWN)
-    {
-        LOG_INFO("pf_dev->link_up is %d and link_info_val->speed is %d, can't update pf info\n",pf_dev->link_up ,link_info_val->speed);
-        return;
-    }
-    pf_dev->speed = link_info_val->speed;
-    pf_dev->autoneg_enable = link_info_val->autoneg_enable;
-    pf_dev->supported_speed_modes = link_info_val->supported_speed_modes;
-    pf_dev->advertising_speed_modes = link_info_val->advertising_speed_modes;
-    pf_dev->duplex = link_info_val->duplex;
-}
-
-int32_t zxdh_pf_get_drv_msg(struct dh_core_dev *dh_dev, uint8_t *drv_version, uint8_t *drv_version_len)
-{
-    *drv_version_len = sizeof(zxdh_pf_driver_version);
-    memcpy(drv_version, zxdh_pf_driver_version, *drv_version_len);
-    return 0;
-}
-
-void zxdh_pf_set_vepa(struct dh_core_dev *dh_dev, bool setting)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    pf_dev->vepa = setting;
-}
-
-bool zxdh_pf_get_vepa(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    return pf_dev->vepa;
-}
-
-int32_t zxdh_pf_request_port(struct dh_core_dev *dh_dev, void *data)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    uint8_t port_num = pf_dev->port_resource.pannel_num;
-    struct zxdh_pannle_port *port;
-    struct zxdh_pannle_port *req_data = (struct zxdh_pannle_port *)data;
-    int32_t idx = 0;
-
-    for (idx = 0; idx < port_num; idx++)
-    {
-        port = &pf_dev->port_resource.port[idx];
-        if (!(port->flags & PORT_FLAGS_ALLOC_STAT))
-        {
-            req_data->phyport = port->phyport;
-            req_data->pannel_id = port->pannel_id;
-            req_data->link_check_bit = port->link_check_bit;
-            port->flags |= PORT_FLAGS_ALLOC_STAT;
-            break;
-        }
-    }
-
-    if (idx == port_num)
-    {
-        LOG_ERR("failed to obtain the panel information from the riscv, or this part is not released when the aux is removed\n");
-        return -1;
-    }
-
-    return 0;
-}
-
-int32_t zxdh_pf_release_port(struct dh_core_dev *dh_dev, uint32_t pnl_id)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    uint8_t port_num = pf_dev->port_resource.pannel_num;
-    struct zxdh_pannle_port *port;
-    int32_t idx = 0;
-
-    for (idx = 0; idx < port_num; idx++)
-    {
-        port = &pf_dev->port_resource.port[idx];
-        if (pnl_id == port->pannel_id)
-        {
-            port->flags &= ~PORT_FLAGS_ALLOC_STAT;
-            break;
-        }
-    }
-
-    return 0;
-}
-
-void zxdh_pf_set_bond_num(struct dh_core_dev *dh_dev, bool add)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    if (add)
-    {
-        pf_dev->bond_num++;
-    }
-    else
-    {
-        pf_dev->bond_num--;
-    }
-}
-
-bool zxdh_pf_if_init(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    if (pf_dev->bond_num == 0)
-    {
-        return true;
-    }
-
-    return false;
-}
-
-void zxdh_pf_set_init_comp_flag(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    pf_dev->aux_comp_flag = ZXDH_AUX_COMP_FLAG;
-    return;
-}
-
-struct zxdh_ipv6_mac_tbl * zxdh_pf_get_ip6mac_tbl(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    return pf_dev->ip6mac_tbl;
-}
-
-struct zxdh_en_sf_if en_sf_ops =
-{
-    .en_sf_map_vq_notify        = zxdh_pf_map_vq_notify,
-    .en_sf_unmap_vq_notify      = zxdh_pf_unmap_vq_notify,
-    .en_sf_set_status           = zxdh_pf_set_status,
-    .en_sf_get_status           = zxdh_pf_get_status,
-    .en_sf_get_features         = zxdh_pf_get_features,
-    .en_sf_set_features         = zxdh_pf_set_features,
-    .en_sf_set_vf_mac           = zxdh_pf_set_vf_mac,
-    .en_sf_get_vf_mac           = zxdh_pf_get_vf_mac,
-    .en_sf_set_mac              = zxdh_set_mac,
-    .en_sf_get_mac              = zxdh_get_mac,
-    .en_sf_set_queue_enable     = zxdh_pf_set_queue_enable,
-    .en_sf_get_channels_num     = zxdh_pf_get_vqs_channels_num,
-    .en_sf_get_queue_num        = zxdh_pf_get_queue_num,
-    .en_sf_get_queue_size       = zxdh_pf_get_queue_size,
-    .en_sf_get_queue_vector     = zxdh_pf_get_queue_vector,
-    .en_sf_release_queue_vector = zxdh_pf_release_queue_vector,
-    .en_sf_set_queue_size       = zxdh_pf_set_queue_size,
-    .en_sf_set_queue_address    = zxdh_pf_set_queue_address,
-    .en_sf_vq_irqs_request      = zxdh_pf_vq_irqs_request,
-    .en_sf_affinity_irqs_release = zxdh_pf_affinity_irqs_release,
-    .en_sf_switch_irq           = zxdh_pf_switch_irq,
-    .en_sf_get_vq_lock          = zxdh_pf_get_vq_lock,
-    .en_sf_release_vq_lock      = zxdh_pf_release_vq_lock,
-    .en_sf_get_phy_vq           = zxdh_pf_get_phy_vq,
-    .en_sf_release_phy_vq       = zxdh_pf_release_phy_vq,
-    .en_sf_get_epbdf            = zxdh_pf_get_epbdf,
-    .en_sf_get_vport            = zxdh_pf_get_vport,
-    .en_sf_get_coredev_type     = zxdh_pf_get_coredev_type,
-    .en_sf_get_pcie_id          = zxdh_pf_get_pcie_id,
-    .en_sf_get_slot_id          = zxdh_pf_get_slot_id,
-    .en_sf_is_bond              = zxdh_pf_is_bond,
-    .en_sf_is_upf               = zxdh_pf_is_upf,
-    .en_sf_get_pdev             = zxdh_pf_get_pdev,
-    .en_sf_get_bar_virt_addr    = zxdh_pf_get_bar_virt_addr,
-    .en_sf_msg_send_cmd         = zxdh_pf_msg_send_cmd,
-    .en_sf_async_eq_enable      = zxdh_pf_async_eq_enable,
-    .en_sf_get_vf_item          = zxdh_pf_get_vf_item,
-    .en_sf_set_pf_link_up       = zxdh_pf_set_pf_link_up,
-    .en_sf_get_pf_link_up       = zxdh_pf_get_pf_link_up,
-    .en_sf_update_pf_link_info  = zxdh_pf_update_link_info,
-    .en_sf_get_drv_msg          = zxdh_pf_get_drv_msg,
-    .en_sf_get_vepa             = zxdh_pf_get_vepa,
-    .en_sf_set_vepa             = zxdh_pf_set_vepa,
-    .en_sf_set_bond_num         = zxdh_pf_set_bond_num,
-    .en_sf_if_init              = zxdh_pf_if_init,
-    .en_sf_request_port_info    = zxdh_pf_request_port,
-    .en_sf_release_port_info    = zxdh_pf_release_port,
-    .en_sf_get_link_info_from_vqm = zxdh_pf_get_link_info_from_vqm,
-    .en_sf_set_vf_link_info     = zxdh_pf_set_vf_link_info,
-    .en_sf_set_pf_phy_port      = zxdh_pf_set_pf_phy_port,
-    .en_sf_get_pf_phy_port      = zxdh_pf_get_pf_phy_port,
-    .en_sf_set_init_comp_flag   = zxdh_pf_set_init_comp_flag,
-    .en_sf_get_ip6mac_tbl       = zxdh_pf_get_ip6mac_tbl,
-};
-
-void zxdh_adev_release(struct device *dev)
-{
-
-}
-
-static DEFINE_IDA(zxdh_adev_ida);
-
-int32_t zxdh_plug_aux_dev(struct dh_core_dev *dh_dev, int32_t idx)
-{
-    struct zxdh_auxiliary_device *adev = NULL;
-    struct zxdh_pf_device *pf_dev = NULL;
-    struct zxdh_en_sf_container *sf_con = NULL;
-    struct zxdh_pf_adev *pf_adevs_table = NULL;
-    int32_t ret = 0;
-
-    pf_dev = dh_core_priv(dh_dev);
-
-    if (idx >= pf_dev->adevs_num)
-    {
-        return 0;
-    }
-
-    pf_adevs_table = &pf_dev->adevs_table[idx];
-    if (pf_adevs_table->adev != NULL)
-    {
-       return 0;
-    }
-
-    sf_con = kzalloc(sizeof(struct zxdh_en_sf_container), GFP_KERNEL);
-
-    if (unlikely(sf_con == NULL))
-    {
-        LOG_ERR("zxadev kzalloc is null\n");
-        return -ENOMEM;
-    }
-
-    pf_adevs_table->aux_idx = ida_alloc(&zxdh_adev_ida, GFP_KERNEL);
-    if (pf_adevs_table->aux_idx < 0)
-    {
-        LOG_ERR("failed to allocate device id for aux drvs\n");
-        goto free_kzalloc;
-    }
-
-    adev = &sf_con->adev;
-
-    adev->id = pf_adevs_table->aux_idx;
-    adev->dev.parent = &dh_dev->pdev->dev;
-    adev->dev.release = zxdh_adev_release;
-    adev->name = ZXDH_PF_EN_SF_DEV_ID_NAME;
-
-    pf_adevs_table->adev = adev;
-    sf_con->dh_dev = dh_dev;
-    sf_con->ops = &en_sf_ops;
-
-    ret = zxdh_auxiliary_device_init(adev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_auxiliary_device_init failed: %d\n", ret);
-        goto free_ida_alloc;
-    }
-
-    ret = zxdh_auxiliary_device_add(adev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_auxiliary_device_add failed: %d\n", ret);
-        goto release_aux_init;
-    }
-
-    return 0;
-
-release_aux_init:
-    zxdh_auxiliary_device_uninit(adev);
-free_ida_alloc:
-    ida_simple_remove(&zxdh_adev_ida, pf_adevs_table->aux_idx);
-    pf_adevs_table->aux_idx = -1;
-free_kzalloc:
-    kfree(sf_con);
-    sf_con = NULL;
-    return ret;
-}
-
-void zxdh_unplug_aux_dev(struct dh_core_dev *dh_dev, int32_t idx)
-{
-    struct zxdh_pf_device *pf_dev = NULL;
-    struct zxdh_en_sf_container *sf_con = NULL;
-    struct zxdh_pf_adev *pf_adevs_table = NULL;
-
-    pf_dev = dh_core_priv(dh_dev);
-    if (idx >= pf_dev->adevs_num)
-    {
-        return;
-    }
-
-    pf_adevs_table = &pf_dev->adevs_table[idx];
-    if (!pf_adevs_table->adev)
-    {
-        return;
-    }
-
-    sf_con = container_of(pf_adevs_table->adev, struct zxdh_en_sf_container, adev);
-
-    zxdh_auxiliary_device_delete(pf_adevs_table->adev);
-    zxdh_auxiliary_device_uninit(pf_adevs_table->adev);
-    ida_simple_remove(&zxdh_adev_ida, pf_adevs_table->aux_idx);
-    pf_adevs_table->aux_idx = -1;
-    kfree(sf_con);
-    sf_con = NULL;
-
-    return;
-}
-
-int32_t dh_pf_vf_vport_get(struct dh_core_dev *dev, uint16_t vf_idx, uint16_t *vport)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-    uint16_t pcie_id = 0;
-    struct zxdh_pci_bar_msg in = {0};
-    struct zxdh_msg_recviver_mem result = {0};
-    uint8_t recv_buf[8] = {0};
-    int32_t ret = 0;
-
-    if (vport == NULL)
-    {
-        return BAR_MSG_ERR_NULL;
-    }
-
-    pcie_id = FIND_VF_PCIE_ID(pf_dev->pcie_id, vf_idx);
-
-    in.virt_addr = (uint64_t)ZXDH_BAR_MSG_BASE(pf_dev->pci_ioremap_addr[0]);
-    in.payload_addr = &pcie_id;
-    in.payload_len = sizeof(pcie_id);
-    in.src = MSG_CHAN_END_PF;
-    in.dst = MSG_CHAN_END_RISC;
-    in.event_id = MODULE_VPORT_GET;
-    in.src_pcieid = pf_dev->pcie_id;
-
-    result.recv_buffer = recv_buf;
-    result.buffer_len = sizeof(recv_buf);
-
-    ret = zxdh_bar_chan_sync_msg_send(&in, &result);
-    switch (ret)
-    {
-        case BAR_MSG_OK:
-        {
-            *vport = *(uint16_t *)(recv_buf + 4);
-            LOG_INFO("pf(0x%x) get vf(%u) vport(0x%x) success\n", pf_dev->pcie_id, vf_idx, *vport);
-            break;
-        }
-        default:
-        {
-            LOG_ERR("Failed to pf(0x%x) get vf(%u) vport, ret:%d.\n", pcie_id, vf_idx, ret);
-            break;
-        }
-    }
-
-    return ret;
-}
-
-int32_t dh_pf_vf_item_init(struct dh_core_dev *dev, uint16_t vf_idx)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-    struct zxdh_vf_item *vf_item = NULL;
-
-    if (pf_dev->vf_item == NULL)
-    {
-        LOG_ERR("vf_item is NULL\n");
-        return -EINVAL;
-    }
-    vf_item = &pf_dev->vf_item[vf_idx];
-    vf_item->link_forced = false;
-    vf_item->vport = pf_dev->vf_item[0].vport + vf_idx;
-    vf_item->enable = true;
-    vf_item->spoofchk = true;
-    return 0;
-}
-
-int32_t dh_pf_vf_item_uninit(struct dh_core_dev *dev, uint16_t vf_idx)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-    struct zxdh_vf_item *vf_item = NULL;
-
-    if (pf_dev->vf_item == NULL)
-    {
-        LOG_ERR("vf_item is NULL\n");
-        return -EINVAL;
-    }
-    vf_item = &pf_dev->vf_item[vf_idx];
-    eth_zero_addr(vf_item->mac);
-    vf_item->pf_set_mac = false;
-    vf_item->enable = false;
-    vf_item->vlan = 0;
-    vf_item->qos = 0;
-    vf_item->spoofchk = false;
-    return 0;
-}
-
-int32_t dh_pf_vf_enable(struct dh_core_dev *dev, int32_t num_vfs)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-    int32_t vf_idx = 0;
-    int32_t ret = 0;
-
-    ret = dh_pf_vf_vport_get(dev, 0, &pf_dev->vf_item[0].vport);
-    if (ret != 0)
-    {
-        return ret;
-    }
-
-    for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
-    {
-        ret = dh_pf_vf_item_init(dev, vf_idx);
-        if (ret != 0)
-        {
-            LOG_ERR("Failed to init vf(%d) item\n", vf_idx);
-            return ret;
-        }
-    }
-
-    return ret;
-}
-
-void dh_pf_vf_disable(struct dh_core_dev *dev, int32_t num_vfs)
-{
-    int32_t vf_idx = 0;
-
-    for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
-    {
-        dh_pf_vf_item_uninit(dev, vf_idx);
-    }
-}
-
-int32_t dh_pf_sriov_enable(struct pci_dev *pdev, int32_t num_vfs)
-{
-    struct dh_core_dev *dev = pci_get_drvdata(pdev);
-    int32_t pre_existing_vfs = pci_num_vf(pdev);
-    int32_t ret = 0;
-
-    if ((pre_existing_vfs != 0) && (pre_existing_vfs == num_vfs))
-    {
-        return 0;
-    }
-
-    ret = dh_pf_vf_enable(dev, num_vfs);
-    if (ret != 0)
-    {
-        LOG_ERR("Failed to enable vf\n");
-        return ret;
-    }
-
-#ifdef ZXDH_SRIOV_SYSFS_EN
-    ret = zxdh_create_vfs_sysfs(dev, num_vfs);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_create_vfs_sysfs failed : %d\n", ret);
-        goto err_create_vfs_sysfs;
-    }
-#endif
-
-    ret = pci_enable_sriov(pdev, num_vfs);
-    if (ret != 0)
-    {
-        LOG_ERR("pci_enable_sriov failed : %d\n", ret);
-        goto err_pci_enable_sriov;
-    }
-
-    return ret;
-
-err_pci_enable_sriov:
-#ifdef ZXDH_SRIOV_SYSFS_EN
-    zxdh_sriov_sysfs_exit(dev);
-err_create_vfs_sysfs:
-#endif
-    dh_pf_vf_disable(dev, num_vfs);
-
-    return ret;
-}
-
-void dh_pf_sriov_disable(struct pci_dev *pdev)
-{
-    struct dh_core_dev *dev = pci_get_drvdata(pdev);
-    int32_t num_vfs = pci_num_vf(pdev);
-
-    pci_disable_sriov(pdev);
-#ifdef ZXDH_SRIOV_SYSFS_EN
-    zxdh_destroy_vfs_sysfs(dev, num_vfs);
-#endif
-    dh_pf_vf_disable(dev, num_vfs);
-}
-
-int32_t dh_pf_vf_item_create(struct dh_core_dev *dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-
-    if (dev->coredev_type == DH_COREDEV_PF)
-    {
-        pf_dev->vf_item = kzalloc(sizeof(struct zxdh_vf_item) * ZXDH_VF_NUM_MAX, GFP_KERNEL);
-        if (pf_dev->vf_item == NULL)
-        {
-            LOG_ERR("pf_dev->vf_item kzalloc failed\n");
-            return -ENOMEM;
-        }
-    }
-
-    return 0;
-}
-
-void dh_pf_vf_item_destroy(struct dh_core_dev *dev, bool disable_vf)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-
-    if (dev->coredev_type == DH_COREDEV_PF)
-    {
-        if (disable_vf)
-        {
-            pci_disable_sriov(dev->pdev);
-        }
-        if (pf_dev->vf_item != NULL)
-        {
-            kfree(pf_dev->vf_item);
-            pf_dev->vf_item = NULL;
-        }
-    }
-}
-
-int32_t dh_pf_pcie_id_get(struct dh_core_dev *dh_dev)
-{
-    int32_t pos = 0;
-    uint8_t type = 0;
-    uint16_t padding = 0;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    struct pci_dev *pdev = dh_dev->pdev;
-
-    if (dh_dev->coredev_type == DH_COREDEV_PF)
-    {
-        if (pdev->bus == NULL)
-        {
-            LOG_ERR("pdev->bus is NULL!\n");
-            return -1;
-        }
-        pf_dev->slot_id = pdev->bus->number;
-        LOG_INFO("pf_dev->slot_id: %d\n", pf_dev->slot_id);
-    }
-    for (pos = pci_find_capability(pdev, PCI_CAP_ID_VNDR); pos > 0; pos = pci_find_next_capability(pdev, pos, PCI_CAP_ID_VNDR))
-    {
-        pci_read_config_byte(pdev, pos + offsetof(struct zxdh_pf_pci_cap, cfg_type), &type);
-
-        if (type == ZXDH_PCI_CAP_PCI_CFG)
-        {
-            pci_read_config_word(pdev, pos + offsetof(struct zxdh_pf_pci_cap, padding[0]), &padding);
-            pf_dev->pcie_id = padding;
-            LOG_INFO("pf_dev->pcie_id: 0x%x\n", pf_dev->pcie_id);
-            return 0;
-        }
-    }
-
-    LOG_INFO("the pci_cap that meets the requirements is not matched\n");
-    return -1;
-}
-
-static uint64_t pci_size(uint64_t base, uint64_t maxbase, uint64_t mask)
-{
-    uint64_t size = mask & maxbase;
-
-    if (!size)
-        return 0;
-    size = size & ~(size-1);
-    if (base == maxbase && ((base | (size - 1)) & mask) != mask)
-        return 0;
-    return size;
-}
-
-int32_t zxdh_send_pxe_status_to_riscv(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    zxdh_cfg_np_msg msg = {0};
-    uint64_t vaddr = 0;
-    int32_t err = 0;
-
-    if (dh_dev->coredev_type != DH_COREDEV_PF)
-    {
-        return 0;
-    }
-
-    msg.dev_id = 0;
-    msg.type = ZXDH_CFG_NPSDK_TYPE;
-    msg.operate_mode = ZXDH_STOP_PXE_MODE;
-
-    vaddr = (uint64_t)ZXDH_BAR_MSG_BASE(pf_dev->pci_ioremap_addr[0]);
-
-    err = zxdh_send_command(vaddr, pf_dev->pcie_id, MODULE_NPSDK, &msg, &msg, true);
-    if (err != 0)
-    {
-        LOG_ERR("send pxe status to config np failed: %d\n", err);
-    }
-
-    return err;
-}
-
-int32_t dh_pf_sriov_cap_cfg_init(struct dh_core_dev *dh_dev)
-{
-    int32_t pos = 0;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    struct pci_dev *pdev = dh_dev->pdev;
-    uint32_t bar_address32 = 0;
-    uint64_t bar_address64 = 0;
-    uint64_t bar_size64 = 0;
-    uint32_t bar_size32 = 0;
-    uint64_t mask64 = 0;
-    uint32_t mem_type = 0;
-    uint16_t nr_virtfn = 0;
-
-    if(dh_dev->coredev_type == DH_COREDEV_VF)
-    {
-        return 0;
-    }
-
-    pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
-    if (pos == 0)
-    {
-        return 0;
-    }
-    pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, &nr_virtfn);
-
-    if (nr_virtfn == 0)
-    {
-        return 0;
-    }
-
-    pci_read_config_dword(pdev, pos + PCI_SRIOV_BAR, &bar_address32);
-    pci_write_config_dword(pdev, pos + PCI_SRIOV_BAR, ~0);
-    pci_read_config_dword(pdev, pos + PCI_SRIOV_BAR, &bar_size32);
-    pci_write_config_dword(pdev, pos + PCI_SRIOV_BAR, bar_address32);
-
-    bar_size64 = bar_size32 & PCI_BASE_ADDRESS_MEM_MASK;
-    bar_address64 = bar_address32 & PCI_BASE_ADDRESS_MEM_MASK;
-    mask64 = (uint32_t)PCI_BASE_ADDRESS_MEM_MASK;
-    mem_type = bar_address32 & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
-
-    if(mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64)
-    {
-        pci_read_config_dword(pdev, pos + PCI_SRIOV_BAR + 4, &bar_address32);
-        pci_write_config_dword(pdev, pos + PCI_SRIOV_BAR + 4, ~0);
-        pci_read_config_dword(pdev, pos + PCI_SRIOV_BAR + 4, &bar_size32);
-        pci_write_config_dword(pdev, pos + PCI_SRIOV_BAR + 4, bar_address32);
-
-        bar_size64 |= ((uint64_t)bar_size32 << 32);
-        bar_address64 |= ((uint64_t)bar_address32 << 32);
-        mask64 |= ((uint64_t)~0 << 32);
-    }
-
-    bar_size64 = pci_size(bar_address64, bar_size64, mask64);
-    if (!bar_size64) {
-        LOG_ERR( "reg 0x%x: invalid BAR (can't size)\n", pos);
-    }
-
-    pf_dev->pf_sriov_cap_base = (void __iomem *)ioremap(bar_address64, bar_size64 * nr_virtfn);
-
-    if (!pf_dev->pf_sriov_cap_base)
-    {
-        LOG_ERR("ioremap(0x%llx, 0x%llx) failed\n", bar_address64, bar_size64 * nr_virtfn);
-        return -1;
-    }
-    pf_dev->sriov_bar_size = bar_size64;
-    return 0;
-}
-
-static uint8_t zxdh_pf_fwcap_readb(struct dh_core_dev *dh_dev, uint32_t offset)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    uint64_t vaddr = (uint64_t)ZXDH_BAR_FWCAP(pf_dev->pci_ioremap_addr[0]);
-
-    return readb((const volatile void __iomem *)(vaddr + offset));
-}
-
-static bool zxdh_pf_is_ovs(struct dh_core_dev *dh_dev)
-{
-    uint8_t product = 0;
-
-    product = zxdh_pf_fwcap_readb(dh_dev, ZXDH_PRODUCT_TYPE);
-    LOG_INFO("fwcap read product type: %d\n", (int32_t)product);
-
-    if ((product == ZXDH_PRODUCT_OVS)
-        || (product == ZXDH_PRODUCT_NEO)
-        || (product == ZXDH_PRODUCT_EVB_EP0)
-        || (product == ZXDH_PRODUCT_EVB_EP0_EP4))
-    {
-        return true;
-    }
-
-    return false;
-}
-
-static void zxdh_pf_set_pannel_port_num(struct dh_core_dev *dh_dev, int port_num)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    pf_dev->pannel_port_num = port_num;
-
-    return;
-}
-
-static void zxdh_pf_request_pannel_port_num(struct dh_core_dev *dh_dev, int *port_num)
-{
-    *port_num = (int)zxdh_pf_fwcap_readb(dh_dev, ZXDH_PANNEL_PORT_NUM);
-}
-
-static int32_t zxdh_pf_lag_init(struct dh_core_dev *dh_dev, int32_t *port_num)
-{
-    int port_num_default = 1;
-
-    /* BOND PF && 非OVS场景，则产生异常 */
-    if (zxdh_pf_is_bond(dh_dev) && !zxdh_pf_is_ovs(dh_dev))
-    {
-        return -1;
-    }
-
-    if (!dh_core_is_pf(dh_dev) || !zxdh_pf_is_bond(dh_dev) || !zxdh_pf_is_ovs(dh_dev))
-    {
-        goto out;
-    }
-
-    zxdh_pf_request_pannel_port_num(dh_dev, &port_num_default);
-    zxdh_pf_set_pannel_port_num(dh_dev, port_num_default);
-    zxdh_regitster_ldev(dh_dev);
-
-    LOG_INFO("zxdh pf lag init finish(port num %d)\n", port_num_default);
-out:
-    zxdh_pf_set_pannel_port_num(dh_dev, port_num_default);
-    *port_num = port_num_default;
-    return 0;
-}
-
-static void zxdh_pf_lag_exit(struct dh_core_dev *dh_dev)
-{
-    zxdh_unregitster_ldev(dh_dev);
-}
-
-int32_t dh_pf_adevs_table_init(struct dh_core_dev *dh_dev, int32_t nr)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    pf_dev->adevs_table = kzalloc(sizeof(*(pf_dev->adevs_table)) * nr, GFP_KERNEL);
-    if (!pf_dev->adevs_table)
-    {
-        pf_dev->adevs_num = 0;
-        LOG_ERR("pf_dev->adevs_table kzalloc failed\n");
-        return -ENOMEM;
-    }
-
-    pf_dev->adevs_num = nr;
-
-    return 0;
-}
-
-void dh_pf_adevs_table_destroy(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    if (dh_dev->coredev_type == DH_COREDEV_PF)
-    {
-        if (pf_dev->adevs_table != NULL)
-        {
-            kfree(pf_dev->adevs_table);
-            pf_dev->adevs_table = NULL;
-            pf_dev->adevs_num = 0;
-        }
-    }
-}
-
-void zxdh_unplug_aux_dev_all(struct dh_core_dev *dh_dev)
-{
-    int32_t idx;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    for (idx = 0; idx < pf_dev->adevs_num; idx++)
-    {
-        zxdh_unplug_aux_dev(dh_dev, idx);
-    }
-}
-
-static int32_t dh_pf_probe(struct pci_dev *pdev, const struct pci_device_id *id)
-{
-    struct dh_core_dev *dh_dev = NULL;
-    struct zxdh_pf_device *pf_dev = NULL;
-    struct devlink *devlink = NULL;
-    int32_t ret = 0;
-    int32_t idx = 0;
-    int32_t port_num = 0;
-
-    LOG_INFO("pf level driver probe start\n");
-
-    devlink = zxdh_devlink_alloc(&pdev->dev, &dh_pf_devlink_ops, sizeof(struct zxdh_pf_device));
-    if (devlink == NULL)
-    {
-        LOG_ERR("devlink alloc failed\n");
-        return -ENOMEM;
-    }
-
-    dh_dev = devlink_priv(devlink);
-    dh_dev->device = &pdev->dev;
-    dh_dev->pdev = pdev;
-    dh_dev->devlink_ops = &dh_pf_core_devlink_ops;
-
-    pf_dev = dh_core_priv(dh_dev);
-    pf_dev->vepa = false;
-
-    dh_dev->coredev_type = GET_COREDEV_TYPE(pdev);
-    LOG_INFO("%s device: %s\n", (dh_dev->coredev_type == DH_COREDEV_PF) ? "PF" : "VF", pci_name(pdev));
-
-    ret = dh_pf_pci_init(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("dh_pf_pci_init failed: %d\n", ret);
-        goto err_irq_table_init;
-    }
-
-    ret = dh_pf_pcie_id_get(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("dh_pf_pcie_id_get failed: %d\n", ret);
-        goto err_pci;
-    }
-
-    ret = dh_pf_vf_item_create(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("Failed to alloc vf item\n");
-        goto err_pci;
-    }
-
-    ret = dh_pf_irq_table_init(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("Failed to alloc IRQs\n");
-        goto err_vf_item;
-    }
-
-    ret = dh_pf_eq_table_init(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("Failed to alloc IRQs\n");
-        goto err_eq_table_init;
-    }
-
-    ret = dh_pf_events_init(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("failed to initialize events\n");
-        goto err_events_init;
-    }
-
-    ret = dh_pf_irq_table_create(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("Failed to alloc IRQs\n");
-        goto err_irq_table_create;
-    }
-
-    ret = dh_pf_eq_table_create(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("Failed to alloc EQs\n");
-        goto err_eq_table_create;
-    }
-
-    ret = dh_pf_sriov_cap_cfg_init(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("dh_pf_sriov_cap_cfg_init failed: %d\n", ret);
-        goto err_sriov_cap_init;
-    }
-
-    ret = zxdh_pf_modern_cfg_init(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_pf_modern_cfg_init failed: %d\n", ret);
-        goto err_cfg_init;
-    }
-
-    ret = zxdh_send_pxe_status_to_riscv(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_send_pxe_status_to_riscv failed: %d\n", ret);
-        goto err_send_pxe_status;
-    }
-
-#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
-    zxdh_devlink_register(devlink);
-#else
-    zxdh_devlink_register(devlink, &pdev->dev);
-#endif
-
-    zxdh_pf_initialized_init(dh_dev);
-
-    ret = zxdh_pf_dpp_init(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_pf_dpp_init failed: %d\n", ret);
-        goto err_dpp_init;
-    }
-
-    ret = zxdh_pf_query_fwinfo(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_pf_query_fwinfo failed: %d\n", ret);
-        goto err_query_fwinfo;
-    }
-
-    ret = zxdh_pf_lag_init(dh_dev, &port_num);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_pf_lag_init failed: %d\n", ret);
-        goto err_query_fwinfo;
-    }
-
-    ret = dh_pf_adevs_table_init(dh_dev, port_num);
-    if (ret != 0)
-    {
-        LOG_ERR("dh_pf_adevs_table_init failed: %d\n", ret);
-        goto err_adevs_tbl_init;
-    }
-
-    for (idx = 0; idx < port_num; idx++)
-    {
-        zxdh_plug_aux_dev(dh_dev, idx);
-    }
-
-#ifdef PTP_DRIVER_INTERFACE_EN
-    if (dh_dev->coredev_type == DH_COREDEV_PF)
-    {
-        ret = zxdh_ptp_init(dh_dev);
-        if (ret != 0)
-        {
-            LOG_ERR("zxdh_ptp_init failed: %d\n", ret);
-            goto err_ptp_init;
-        }
-    }
-#endif
-
-    if (!zxdh_pf_is_upf(dh_dev))
-    {
-        ret = zxdh_tsn_init(dh_dev);
-        if (ret != 0)
-        {
-            LOG_ERR("zxdh_tsn_init failed: %d\n", ret);
-            goto err_tsn_init;
-        }
-    }
-
-#ifdef ZXDH_SRIOV_SYSFS_EN
-    ret = zxdh_sriov_sysfs_init(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_sriov_sysfs_init failed: %d, vport = %x\n", ret, pf_dev->vport);
-        goto err_sriov_sysfs;
-    }
-#endif
-
-    zxdh_pf_ip6mac_lock_init(dh_dev);
-
-    ret = zxdh_init_ip6mac_tbl(dh_dev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_init_ip6mac_tbl failed: %d, vport = %x\n", ret, pf_dev->vport);
-        goto err_tsn_init;
-    }
-
-    LOG_INFO("pf level driver probe completed\n");
-
-    return 0;
-
-#ifdef ZXDH_SRIOV_SYSFS_EN
-err_sriov_sysfs:
-#endif
-err_tsn_init:
-    if (!zxdh_pf_is_upf(dh_dev))
-    {
-        zxdh_tsn_exit(dh_dev);
-    }
-err_ptp_init:
-    zxdh_ptp_stop(dh_dev);
-err_adevs_tbl_init:
-    zxdh_pf_lag_exit(dh_dev);
-err_query_fwinfo:
-    zxdh_pf_dpp_uninit(dh_dev);
-err_dpp_init:
-    zxdh_pf_initialized_uninit(dh_dev);
-    zxdh_devlink_unregister(devlink);
-err_send_pxe_status:
-    zxdh_pf_modern_cfg_uninit(dh_dev);
-err_cfg_init:
-    dh_pf_sriov_cap_cfg_uninit(dh_dev);
-err_sriov_cap_init:
-    dh_pf_eq_table_destroy(dh_dev);
-err_eq_table_create:
-    dh_pf_irq_table_destroy(dh_dev);
-err_irq_table_create:
-    dh_pf_events_uninit(dh_dev);
-err_events_init:
-    dh_eq_table_cleanup(dh_dev);
-err_eq_table_init:
-    dh_irq_table_cleanup(dh_dev);
-err_vf_item:
-    dh_pf_vf_item_destroy(dh_dev, true);
-err_pci:
-    dh_pf_pci_close(dh_dev);
-err_irq_table_init:
-    zxdh_devlink_free(devlink);
-    return ret;
-}
-
-static void dh_pf_remove(struct pci_dev *pdev)
-{
-    struct dh_core_dev *dh_dev = pci_get_drvdata(pdev);
-    struct devlink *devlink = priv_to_devlink(dh_dev);
-
-    LOG_INFO("pf level driver remove start\n");
-    zxdh_cleanup_ip6mac_tbl(dh_dev);
-#ifdef ZXDH_SRIOV_SYSFS_EN
-    zxdh_sriov_sysfs_exit(dh_dev);
-#endif
-    if (!zxdh_pf_is_upf(dh_dev))
-    {
-        zxdh_tsn_exit(dh_dev);
-    }
-#ifdef PTP_DRIVER_INTERFACE_EN
-    if (dh_dev->coredev_type == DH_COREDEV_PF)
-    {
-        zxdh_ptp_stop(dh_dev);
-    }
-#endif
-    zxdh_unplug_aux_dev_all(dh_dev);
-    dh_pf_adevs_table_destroy(dh_dev);
-
-    zxdh_pf_lag_exit(dh_dev);
-    zxdh_pf_dpp_uninit(dh_dev);
-    zxdh_pf_initialized_uninit(dh_dev);
-
-    zxdh_devlink_unregister(devlink);
-    zxdh_pf_modern_cfg_uninit(dh_dev);
-    dh_pf_sriov_cap_cfg_uninit(dh_dev);
-    dh_pf_eq_table_destroy(dh_dev);
-    dh_pf_irq_table_destroy(dh_dev);
-    dh_pf_events_uninit(dh_dev);
-    dh_eq_table_cleanup(dh_dev);
-    dh_irq_table_cleanup(dh_dev);
-    dh_pf_vf_item_destroy(dh_dev, true);
-    dh_pf_pci_close(dh_dev);
-    zxdh_devlink_free(devlink);
-
-    pci_set_drvdata(pdev, NULL);
-    LOG_INFO("pf level driver remove completed\n");
-
-    return;
-}
-
-static int32_t dh_pf_suspend(struct pci_dev *pdev, pm_message_t state)
-{
-
-    return 0;
-}
-
-static int32_t dh_pf_resume(struct pci_dev *pdev)
-{
-
-    return 0;
-}
-
-static void dh_pf_shutdown(struct pci_dev *pdev)
-{
-    struct dh_core_dev *dh_dev = pci_get_drvdata(pdev);
-    struct devlink *devlink = priv_to_devlink(dh_dev);
-
-    LOG_INFO("pf level driver shutdown start\n");
-    dh_pf_adevs_table_destroy(dh_dev);
-
-    zxdh_pf_lag_exit(dh_dev);
-    zxdh_pf_dpp_uninit(dh_dev);
-    zxdh_pf_initialized_uninit(dh_dev);
-
-    zxdh_devlink_unregister(devlink);
-    zxdh_pf_modern_cfg_uninit(dh_dev);
-    dh_pf_sriov_cap_cfg_uninit(dh_dev);
-    dh_pf_eq_table_destroy(dh_dev);
-    dh_pf_irq_table_destroy(dh_dev);
-    dh_pf_events_uninit(dh_dev);
-    dh_eq_table_cleanup(dh_dev);
-    dh_irq_table_cleanup(dh_dev);
-    dh_pf_vf_item_destroy(dh_dev, false);
-    dh_pf_pci_close(dh_dev);
-    zxdh_devlink_free(devlink);
-
-    pci_set_drvdata(pdev, NULL);
-    LOG_INFO("pf level driver shutdown completed\n");
-}
-
-static pci_ers_result_t dh_pci_err_detected(struct pci_dev *pdev,
-                                            pci_channel_state_t state)
-{
-    return PCI_ERS_RESULT_NONE;
-}
-
-static pci_ers_result_t dh_pf_pci_slot_reset(struct pci_dev *pdev)
-{
-    return PCI_ERS_RESULT_NONE;
-}
-
-static void dh_pf_pci_resume(struct pci_dev *pdev)
-{
-
-}
-
-int32_t dh_pf_sriov_configure(struct pci_dev *pdev, int32_t num_vfs)
-{
-    struct dh_core_dev *dev = pci_get_drvdata(pdev);
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-    int32_t ret = 0;
-
-    if (dev->coredev_type != DH_COREDEV_PF)
-    {
-        LOG_ERR("This device is not capable of SR-IOV\n");
-        return -EOPNOTSUPP;
-    }
-
-    if (num_vfs > 0)
-    {
-        ret = dh_pf_sriov_enable(pdev, num_vfs);
-        if (ret != 0)
-        {
-            LOG_ERR("Failed to enable sriov, num_vfs:%d\n", num_vfs);
-            return ret;
-        }
-    }
-    else
-    {
-        dh_pf_sriov_disable(pdev);
-    }
-
-    pf_dev->num_vfs = (uint16_t)num_vfs;
-
-    return num_vfs;
-}
-
-static const struct pci_error_handlers dh_pf_err_handler = {
-    .error_detected = dh_pci_err_detected,
-    .slot_reset     = dh_pf_pci_slot_reset,
-    .resume         = dh_pf_pci_resume
-};
-
-static struct pci_driver dh_pf_driver = {
-    .name            = KBUILD_MODNAME,
-    .id_table        = dh_pf_pci_table,
-    .probe           = dh_pf_probe,
-    .remove          = dh_pf_remove,
-    .suspend         = dh_pf_suspend,
-    .resume          = dh_pf_resume,
-    .shutdown        = dh_pf_shutdown,
-    .err_handler     = &dh_pf_err_handler,
-    .sriov_configure = dh_pf_sriov_configure,
-};
-
-static int32_t __init dh_pf_pci_init_module(void)
-{
-    int32_t ret = 0;
-
-    LOG_INFO("%s - version %s\n", zxdh_pf_driver_string, zxdh_pf_driver_version);
-    LOG_INFO("%s\n", zxdh_pf_copyright);
-
-    ret = pci_register_driver(&dh_pf_driver);
-    if (ret != 0)
-    {
-        LOG_ERR("pci_register_driver failed: %d\n", ret);
-        goto err_register_driver;
-    }
-
-#ifdef CONFIG_ZXDH_SF
-    ret = zxdh_en_sf_driver_register();
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_en_sf_driver_register failed: %d\n", ret);
-        goto err_sf_driver_register;
-    }
-#endif
-
-    ret = dh_pf_msg_recv_func_register();
-    if (ret != 0)
-    {
-        LOG_ERR("dh_pf_msg_recv_func_register failed: %d\n", ret);
-        goto err_msg_recv_func_registe;
-    }
-
-    return 0;
-
-err_msg_recv_func_registe:
-#ifdef CONFIG_ZXDH_SF
-    zxdh_en_sf_driver_unregister();
-err_sf_driver_register:
-#endif
-    pci_unregister_driver(&dh_pf_driver);
-err_register_driver:
-    return ret;
-}
-
-static void dh_pf_pci_exit_module(void)
-{
-    LOG_INFO("%s - version %s\n", zxdh_pf_driver_string, zxdh_pf_driver_version);
-    LOG_INFO("%s\n", zxdh_pf_copyright);
-
-    dh_pf_msg_recv_func_unregister();
-
-#ifdef CONFIG_ZXDH_SF
-    zxdh_en_sf_driver_unregister();
-#endif
-
-    pci_unregister_driver(&dh_pf_driver);
-
-    return;
-}
-
-module_init(dh_pf_pci_init_module);
-module_exit(dh_pf_pci_exit_module);
+#include <linux/module.h>
+#include <linux/kmod.h>
+#include <linux/pci.h>
+#include <linux/aer.h>
+#include <linux/dinghai/driver.h>
+#include <linux/dinghai/lag.h>
+#include <net/devlink.h>
+#include <linux/dinghai/devlink.h>
+#include <linux/dinghai/helper.h>
+#include <linux/dinghai/dh_cmd.h>
+#include "en_pf.h"
+#include "./en_pf/irq.h"
+#include "./en_pf/eq.h"
+#include "./en_pf/events.h"
+#include "en_aux.h"
+#include "en_sf.h"
+#include "en_np/init/include/dpp_np_init.h"
+#include "en_pf/msg_func.h"
+#include "msg_common.h"
+
+#ifdef CONFIG_ZXDH_SF
+#include <linux/dinghai/en_sf.h>
+#endif
+
+#define DRV_VERSION_MAJOR 2
+#define DRV_VERSION_MINOR 0
+#define DRV_VERSION_BUILD 4
+
+#define DRV_VERSION                                 \
+	__stringify(DRV_VERSION_MAJOR) "." __stringify( \
+			DRV_VERSION_MINOR) "." __stringify(DRV_VERSION_BUILD)
+
+#define DRV_SUMMARY "ZTE(R) zxdh-net driver"
+
+const char zxdh_pf_driver_version[] = DRV_VERSION;
+static const char zxdh_pf_driver_string[] = DRV_SUMMARY;
+static const char zxdh_pf_copyright[] =
+		"Copyright (c) 2022-23, ZTE Corporation.";
+
+MODULE_AUTHOR("ZTE Corporation");
+MODULE_DESCRIPTION(DRV_SUMMARY);
+MODULE_VERSION(DRV_VERSION);
+MODULE_LICENSE("Dual BSD/GPL");
+
+uint32_t dh_debug_mask;
+module_param_named(debug_mask, dh_debug_mask, uint, 0644);
+MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec "
+							 "time, 3 = both. Default=0");
+
+static const struct pci_device_id dh_pf_pci_table[] = {
+	{ PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_DEVICE_ID), 0 },
+	{ PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_VF_DEVICE_ID), 0 },
+	{ PCI_DEVICE(ZXDH_PF_BSI_VENDOR_ID, ZXDH_PF_DEVICE_ID), 0 },
+	{ PCI_DEVICE(ZXDH_PF_BSI_VENDOR_ID, ZXDH_VF_DEVICE_ID), 0 },
+	{ PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_INICA_BOND_DEVICE_ID), 0 }, /* bond */
+	{ PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_INICB_BOND_DEVICE_ID), 0 }, /* bond */
+	{ PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_DPUA_BOND_DEVICE_ID), 0 }, /* bond */
+	{ PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_E310_DEVICE_ID), 0 },
+	{ PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_VF_E310_DEVICE_ID), 0 },
+	{ PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_PF_E312_DEVICE_ID), 0 },
+	{ PCI_DEVICE(ZXDH_PF_VENDOR_ID, ZXDH_VF_E312_DEVICE_ID), 0 },
+	{
+			0,
+	}
+};
+
+MODULE_DEVICE_TABLE(pci, dh_pf_pci_table);
+
+extern struct devlink_ops dh_pf_devlink_ops;
+extern struct dh_core_devlink_ops dh_pf_core_devlink_ops;
+
+#ifdef PTP_DRIVER_INTERFACE_EN
+int zxdh_ptp_init(struct dh_core_dev *zxdev);
+void zxdh_ptp_stop(struct dh_core_dev *zxdev);
+#endif
+
+int32_t dh_pf_pci_init(struct dh_core_dev *dev)
+{
+	int32_t ret = 0;
+	struct zxdh_pf_device *pf_dev = NULL;
+
+	pci_set_drvdata(dev->pdev, dev);
+
+	ret = pci_enable_device(dev->pdev);
+	if (ret != 0) {
+		LOG_ERR("pci_enable_device failed: %d\n", ret);
+		return -ENOMEM;
+	}
+
+	ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(64));
+	if (ret != 0) {
+		ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(32));
+		if (ret != 0) {
+			LOG_ERR("dma_set_mask_and_coherent failed: %d\n", ret);
+			goto err_pci;
+		}
+	}
+
+	ret = pci_request_selected_regions(
+			dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM), "dh-pf");
+	if (ret != 0) {
+		LOG_ERR("pci_request_selected_regions failed: %d\n", ret);
+		goto err_pci;
+	}
+
+	pci_enable_pcie_error_reporting(dev->pdev);
+	pci_set_master(dev->pdev);
+	ret = pci_save_state(dev->pdev);
+	if (ret != 0) {
+		LOG_ERR("pci_save_state failed: %d\n", ret);
+		goto err_pci_save_state;
+	}
+
+	pf_dev = dh_core_priv(dev);
+	pf_dev->pci_ioremap_addr[0] = (uint64_t)ioremap(
+			pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0));
+	if (pf_dev->pci_ioremap_addr[0] == 0) {
+		ret = -1;
+		LOG_ERR("ioremap(0x%llx, 0x%llx) failed\n",
+				pci_resource_start(dev->pdev, 0),
+				pci_resource_len(dev->pdev, 0));
+		goto err_pci_save_state;
+	}
+
+	return 0;
+
+err_pci_save_state:
+	pci_disable_pcie_error_reporting(dev->pdev);
+	pci_release_selected_regions(dev->pdev,
+								 pci_select_bars(dev->pdev, IORESOURCE_MEM));
+err_pci:
+	pci_disable_device(dev->pdev);
+	return ret;
+}
+
+void dh_pf_pci_close(struct dh_core_dev *dev)
+{
+	struct zxdh_pf_device *pf_dev = NULL;
+
+	pf_dev = dh_core_priv(dev);
+	iounmap((void *)pf_dev->pci_ioremap_addr[0]);
+	pci_disable_pcie_error_reporting(dev->pdev);
+	pci_release_selected_regions(dev->pdev,
+								 pci_select_bars(dev->pdev, IORESOURCE_MEM));
+	pci_disable_device(dev->pdev);
+
+	return;
+}
+
+int32_t zxdh_pf_pci_find_capability(struct pci_dev *pdev, uint8_t cfg_type,
+									uint32_t ioresource_types, int32_t *bars)
+{
+	int32_t pos = 0;
+	uint8_t type = 0;
+	uint8_t bar = 0;
+
+	for (pos = pci_find_capability(pdev, PCI_CAP_ID_VNDR); pos > 0;
+		 pos = pci_find_next_capability(pdev, pos, PCI_CAP_ID_VNDR)) {
+		pci_read_config_byte(
+				pdev, pos + offsetof(struct zxdh_pf_pci_cap, cfg_type), &type);
+		pci_read_config_byte(pdev, pos + offsetof(struct zxdh_pf_pci_cap, bar),
+							 &bar);
+
+		/* ignore structures with reserved BAR values */
+		if (bar > ZXDH_PF_MAX_BAR_VAL) {
+			continue;
+		}
+
+		if (type == cfg_type) {
+			if (pci_resource_len(pdev, bar) &&
+				pci_resource_flags(pdev, bar) & ioresource_types) {
+				*bars |= (1 << bar);
+				return pos;
+			}
+		}
+	}
+
+	return 0;
+}
+
+void __iomem *zxdh_pf_map_capability(struct dh_core_dev *dh_dev, int32_t off,
+									 size_t minlen, uint32_t align,
+									 uint32_t start, uint32_t size, size_t *len,
+									 resource_size_t *pa)
+{
+	struct pci_dev *pdev = dh_dev->pdev;
+	uint8_t bar = 0;
+	uint32_t offset = 0;
+	uint32_t length = 0;
+	void __iomem *p = NULL;
+
+	pci_read_config_byte(pdev, off + offsetof(struct zxdh_pf_pci_cap, bar),
+						 &bar);
+	pci_read_config_dword(pdev, off + offsetof(struct zxdh_pf_pci_cap, offset),
+						  &offset);
+	pci_read_config_dword(pdev, off + offsetof(struct zxdh_pf_pci_cap, length),
+						  &length);
+
+	if (length <= start) {
+		LOG_ERR("bad capability len %u (>%u expected)\n", length, start);
+		return NULL;
+	}
+
+	if (length - start < minlen) {
+		LOG_ERR("bad capability len %u (>=%zu expected)\n", length, minlen);
+		return NULL;
+	}
+
+	length -= start;
+	if (start + offset < offset) {
+		LOG_ERR("map wrap-around %u+%u\n", start, offset);
+		return NULL;
+	}
+
+	offset += start;
+	if (offset & (align - 1)) {
+		LOG_ERR("offset %u not aligned to %u\n", offset, align);
+		return NULL;
+	}
+
+	if (length > size) {
+		length = size;
+	}
+
+	if (len) {
+		*len = length;
+	}
+
+	if (minlen + offset < minlen ||
+		minlen + offset > pci_resource_len(pdev, bar)) {
+		LOG_ERR("map custom queue %zu@%u "
+				"out of range on bar %i length %lu\n",
+				minlen, offset, bar,
+				(unsigned long)pci_resource_len(pdev, bar));
+		return NULL;
+	}
+
+	p = pci_iomap_range(pdev, bar, offset, length);
+	if (unlikely(p == NULL)) {
+		LOG_ERR("unable to map custom queue %u@%u on bar %i\n", length, offset,
+				bar);
+	} else if (pa) {
+		*pa = pci_resource_start(pdev, bar) + offset;
+	}
+
+	return p;
+}
+
+int32_t zxdh_pf_common_cfg_init(struct dh_core_dev *dh_dev)
+{
+	int32_t common = 0;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	struct pci_dev *pdev = dh_dev->pdev;
+
+	/* check for a common config: if not, use legacy mode (bar 0). */
+	common = zxdh_pf_pci_find_capability(pdev, ZXDH_PCI_CAP_COMMON_CFG,
+										 IORESOURCE_IO | IORESOURCE_MEM,
+										 &pf_dev->modern_bars);
+	if (common == 0) {
+		LOG_ERR("missing capabilities %i, leaving for legacy driver\n", common);
+		return -ENODEV;
+	}
+
+	pf_dev->common = zxdh_pf_map_capability(
+			dh_dev, common, sizeof(struct zxdh_pf_pci_common_cfg),
+			ZXDH_PF_ALIGN4, 0, sizeof(struct zxdh_pf_pci_common_cfg), NULL,
+			NULL);
+	if (unlikely(pf_dev->common == NULL)) {
+		LOG_ERR("pf_dev->common is null\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int32_t zxdh_pf_notify_cfg_init(struct dh_core_dev *dh_dev)
+{
+	int32_t notify = 0;
+	uint32_t notify_length = 0;
+	uint32_t notify_offset = 0;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	struct pci_dev *pdev = dh_dev->pdev;
+
+	/* If common is there, these should be too... */
+	notify = zxdh_pf_pci_find_capability(pdev, ZXDH_PCI_CAP_NOTIFY_CFG,
+										 IORESOURCE_IO | IORESOURCE_MEM,
+										 &pf_dev->modern_bars);
+	if (notify == 0) {
+		LOG_ERR("missing capabilities %i\n", notify);
+		return -EINVAL;
+	}
+
+	pci_read_config_dword(pdev,
+						  notify + offsetof(struct zxdh_pf_pci_notify_cap,
+											notify_off_multiplier),
+						  &pf_dev->notify_offset_multiplier);
+	pci_read_config_dword(
+			pdev, notify + offsetof(struct zxdh_pf_pci_notify_cap, cap.length),
+			&notify_length);
+	pci_read_config_dword(
+			pdev, notify + offsetof(struct zxdh_pf_pci_notify_cap, cap.offset),
+			&notify_offset);
+
+	/* We don't know how many VQs we'll map, ahead of the time.
+   * If notify length is small, map it all now. Otherwise, map each VQ
+   * individually later. */
+	if ((uint64_t)notify_length + (notify_offset % PAGE_SIZE) <= PAGE_SIZE) {
+		pf_dev->notify_base = zxdh_pf_map_capability(
+				dh_dev, notify, ZXDH_PF_MAP_MINLEN2, ZXDH_PF_ALIGN2, 0,
+				notify_length, &pf_dev->notify_len, &pf_dev->notify_pa);
+		if (unlikely(pf_dev->notify_base == NULL)) {
+			LOG_ERR("pf_dev->notify_base is null\n");
+			return -EINVAL;
+		}
+	} else {
+		pf_dev->notify_map_cap = notify;
+	}
+
+	return 0;
+}
+
+int32_t zxdh_pf_device_cfg_init(struct dh_core_dev *dh_dev)
+{
+	int32_t device = 0;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	struct pci_dev *pdev = dh_dev->pdev;
+
+	/* Device capability is only mandatory for devices that have device-specific
+   * configuration. */
+	device = zxdh_pf_pci_find_capability(pdev, ZXDH_PCI_CAP_DEVICE_CFG,
+										 IORESOURCE_IO | IORESOURCE_MEM,
+										 &pf_dev->modern_bars);
+
+	/* we don't know how much we should map, but PAGE_SIZE is more than enough for
+   * all existing devices. */
+	if (device) {
+		pf_dev->device = zxdh_pf_map_capability(dh_dev, device, 0,
+												ZXDH_PF_ALIGN4, 0, PAGE_SIZE,
+												&pf_dev->device_len, NULL);
+		if (unlikely(pf_dev->device == NULL)) {
+			LOG_ERR("pf_dev->device is null\n");
+			return -EINVAL;
+		}
+	}
+	return 0;
+}
+
+void zxdh_pf_modern_cfg_uninit(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	struct pci_dev *pdev = dh_dev->pdev;
+
+	if (pf_dev->device) {
+		pci_iounmap(pdev, pf_dev->device);
+	}
+	if (pf_dev->notify_base) {
+		pci_iounmap(pdev, pf_dev->notify_base);
+	}
+	pci_iounmap(pdev, pf_dev->common);
+}
+
+int32_t zxdh_pf_modern_cfg_init(struct dh_core_dev *dh_dev)
+{
+	int32_t ret = 0;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	struct pci_dev *pdev = dh_dev->pdev;
+
+	ret = zxdh_pf_common_cfg_init(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_pf_common_cfg_init failed: %d\n", ret);
+		return -EINVAL;
+	}
+
+	ret = zxdh_pf_notify_cfg_init(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_pf_notify_cfg_init failed: %d\n", ret);
+		goto err_map_notify;
+	}
+
+	ret = zxdh_pf_device_cfg_init(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_pf_device_cfg_init failed: %d\n", ret);
+		goto err_map_device;
+	}
+
+	return 0;
+
+err_map_device:
+	if (pf_dev->notify_base) {
+		pci_iounmap(pdev, pf_dev->notify_base);
+	}
+err_map_notify:
+	pci_iounmap(pdev, pf_dev->common);
+	return -EINVAL;
+}
+
+uint16_t zxdh_pf_get_queue_notify_off(struct dh_core_dev *dh_dev,
+									  uint16_t index)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	iowrite16(index, &pf_dev->common->queue_select);
+
+	return ioread16(&pf_dev->common->queue_notify_off);
+}
+
+void __iomem *zxdh_pf_map_vq_notify(struct dh_core_dev *dh_dev, uint32_t index,
+									resource_size_t *pa)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	uint16_t off = 0;
+
+	off = zxdh_pf_get_queue_notify_off(dh_dev, index);
+
+	if (pf_dev->notify_base) {
+		/* offset should not wrap */
+		if ((uint64_t)off * pf_dev->notify_offset_multiplier + 2 >
+			pf_dev->notify_len) {
+			LOG_ERR("bad notification offset %u (x %u) "
+					"for queue %u > %zd",
+					off, pf_dev->notify_offset_multiplier, index,
+					pf_dev->notify_len);
+			return NULL;
+		}
+
+		if (pa) {
+			*pa = pf_dev->notify_pa + off * pf_dev->notify_offset_multiplier;
+		}
+
+		return pf_dev->notify_base + off * pf_dev->notify_offset_multiplier;
+	} else {
+		return zxdh_pf_map_capability(dh_dev, pf_dev->notify_map_cap, 2, 2,
+									  off * pf_dev->notify_offset_multiplier, 2,
+									  NULL, pa);
+	}
+}
+
+void zxdh_pf_unmap_vq_notify(struct dh_core_dev *dh_dev, void *priv)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	if (!pf_dev->notify_base) {
+		pci_iounmap(dh_dev->pdev, priv);
+	}
+}
+
+void zxdh_pf_set_status(struct dh_core_dev *dh_dev, uint8_t status)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	iowrite8(status, &pf_dev->common->device_status);
+
+	return;
+}
+
+uint8_t zxdh_pf_get_status(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	return ioread8(&pf_dev->common->device_status);
+}
+
+void zxdh_pf_get_vf_mac(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id)
+{
+	uint32_t DEV_MAC_L = 0;
+	uint16_t DEV_MAC_H = 0;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	DEV_MAC_L =
+			ioread32((const void __iomem *)(pf_dev->pf_sriov_cap_base +
+											(pf_dev->sriov_bar_size) * vf_id +
+											ZXDH_DEV_MAC_LOW_OFFSET));
+	mac[0] = DEV_MAC_L & 0xff;
+	mac[1] = (DEV_MAC_L >> 8) & 0xff;
+	mac[2] = (DEV_MAC_L >> 16) & 0xff;
+	mac[3] = (DEV_MAC_L >> 24) & 0xff;
+	DEV_MAC_H =
+			ioread16((const void __iomem *)(pf_dev->pf_sriov_cap_base +
+											(pf_dev->sriov_bar_size) * vf_id +
+											ZXDH_DEV_MAC_HIGH_OFFSET));
+	mac[4] = DEV_MAC_H & 0xff;
+	mac[5] = (DEV_MAC_H >> 8) & 0xff;
+	return;
+}
+
+void zxdh_pf_set_vf_mac(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id)
+{
+	uint32_t DEV_MAC_L = 0;
+	uint16_t DEV_MAC_H = 0;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	DEV_MAC_L = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
+	DEV_MAC_H = mac[4] | (mac[5] << 8);
+	iowrite32(DEV_MAC_L, (void __iomem *)(pf_dev->pf_sriov_cap_base +
+										  (pf_dev->sriov_bar_size) * vf_id +
+										  ZXDH_DEV_MAC_LOW_OFFSET));
+	iowrite16(DEV_MAC_H, (void __iomem *)(pf_dev->pf_sriov_cap_base +
+										  (pf_dev->sriov_bar_size) * vf_id +
+										  ZXDH_DEV_MAC_HIGH_OFFSET));
+	return;
+}
+
+void zxdh_set_mac(struct dh_core_dev *dh_dev, uint8_t *mac)
+{
+	uint32_t DEV_MAC_L = 0;
+	uint16_t DEV_MAC_H = 0;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	DEV_MAC_L = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
+	DEV_MAC_H = mac[4] | (mac[5] << 8);
+	iowrite32(DEV_MAC_L, (void __iomem *)(pf_dev->pci_ioremap_addr[0] +
+										  ZXDH_DEV_MAC_LOW_OFFSET));
+	iowrite16(DEV_MAC_H, (void __iomem *)(pf_dev->pci_ioremap_addr[0] +
+										  ZXDH_DEV_MAC_HIGH_OFFSET));
+	return;
+}
+
+void zxdh_get_mac(struct dh_core_dev *dh_dev, uint8_t *mac)
+{
+	uint32_t DEV_MAC_L = 0;
+	uint16_t DEV_MAC_H = 0;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	DEV_MAC_L = ioread32((void __iomem *)(pf_dev->pci_ioremap_addr[0] +
+										  ZXDH_DEV_MAC_LOW_OFFSET));
+	mac[0] = DEV_MAC_L & 0xff;
+	mac[1] = (DEV_MAC_L >> 8) & 0xff;
+	mac[2] = (DEV_MAC_L >> 16) & 0xff;
+	mac[3] = (DEV_MAC_L >> 24) & 0xff;
+	DEV_MAC_H = ioread16((void __iomem *)(pf_dev->pci_ioremap_addr[0] +
+										  ZXDH_DEV_MAC_HIGH_OFFSET));
+	mac[4] = DEV_MAC_H & 0xff;
+	mac[5] = (DEV_MAC_H >> 8) & 0xff;
+	return;
+}
+
+uint64_t zxdh_pf_get_features(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	uint64_t device_feature = 0;
+
+	iowrite32(0, &pf_dev->common->device_feature_select);
+	device_feature = ioread32(&pf_dev->common->device_feature);
+	iowrite32(1, &pf_dev->common->device_feature_select);
+	device_feature |=
+			((uint64_t)ioread32(&pf_dev->common->device_feature) << 32);
+
+	return device_feature;
+}
+
+void zxdh_pf_set_features(struct dh_core_dev *dh_dev, uint64_t features)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	iowrite32(0, &pf_dev->common->guest_feature_select);
+	iowrite32((uint32_t)features, &pf_dev->common->guest_feature);
+	iowrite32(1, &pf_dev->common->guest_feature_select);
+	iowrite32(features >> 32, &pf_dev->common->guest_feature);
+
+	return;
+}
+
+void zxdh_pf_set_queue_enable(struct dh_core_dev *dh_dev, uint16_t index,
+							  bool enable)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	iowrite16(index, &pf_dev->common->queue_select);
+	iowrite16(enable, &pf_dev->common->queue_enable);
+}
+
+uint32_t zxdh_pf_get_epbdf(struct dh_core_dev *dh_dev)
+{
+	uint32_t domain, bus, devid, function, epbdf = 0;
+	struct pci_dev *pdev = dh_dev->pdev;
+
+	if (pdev != NULL) {
+		sscanf(pci_name(pdev), "%x:%x:%x.%u", &domain, &bus, &devid, &function);
+		epbdf = BDF_ECAM(bus, devid, function);
+	} else {
+		LOG_ERR("err: pdev null, return epbdf data 0.\n");
+	}
+
+	return epbdf;
+}
+
+int zxdh_pf_get_pannel_port_num(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	return pf_dev->pannel_port_num;
+}
+
+uint16_t zxdh_pf_get_vport(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	return pf_dev->vport;
+}
+
+enum dh_coredev_type zxdh_pf_get_coredev_type(struct dh_core_dev *dh_dev)
+{
+	return dh_dev->coredev_type;
+}
+
+uint16_t zxdh_pf_get_pcie_id(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	return pf_dev->pcie_id;
+}
+
+uint16_t zxdh_pf_get_slot_id(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	return pf_dev->slot_id;
+}
+
+bool zxdh_pf_is_bond(struct dh_core_dev *dh_dev)
+{
+	bool flags = false;
+
+	if (!dh_core_is_pf(dh_dev)) {
+		return false;
+	}
+
+	if ((dh_dev->pdev->device == ZXDH_INICA_BOND_DEVICE_ID) ||
+		(dh_dev->pdev->device == ZXDH_INICB_BOND_DEVICE_ID) ||
+		(dh_dev->pdev->device == ZXDH_DPUA_BOND_DEVICE_ID)) {
+		flags = true;
+	}
+
+	return flags;
+}
+
+struct zxdh_vf_item *zxdh_pf_get_vf_item(struct dh_core_dev *dh_dev,
+										 uint16_t vf_idx)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	if (dh_dev->coredev_type != DH_COREDEV_PF) {
+		LOG_ERR("Invalid device\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (vf_idx >= ZXDH_VF_NUM_MAX) {
+		LOG_ERR("vf idx(%u) out of range(0~255)\n", vf_idx);
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (pf_dev->vf_item == NULL) {
+		LOG_ERR("vf_item is NULL\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (!pf_dev->vf_item[vf_idx].enable) {
+		LOG_ERR("vf(%u) is disable\n", vf_idx);
+		return ERR_PTR(-EINVAL);
+	}
+
+	return &(pf_dev->vf_item[vf_idx]);
+}
+
+int32_t zxdh_pf_dpp_init(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = pf_dev->slot_id;
+	pf_info.vport = pf_dev->vport;
+	return dpp_vport_register(&pf_info, dh_dev->pdev);
+}
+
+int32_t zxdh_pf_dpp_uninit(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = pf_dev->slot_id;
+	pf_info.vport = pf_dev->vport;
+	return dpp_vport_unregister(&pf_info);
+}
+
+void zxdh_pf_initialized_init(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	pf_dev->initialized_flags = 0;
+	spin_lock_init(&pf_dev->initialized_lock);
+}
+
+void zxdh_pf_initialized_uninit(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	pf_dev->initialized_flags = 0;
+}
+
+struct pci_dev *zxdh_pf_get_pdev(struct dh_core_dev *dh_dev)
+{
+	return dh_dev->pdev;
+}
+
+uint64_t zxdh_pf_get_bar_virt_addr(struct dh_core_dev *dh_dev, uint8_t bar_num)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	return pf_dev->pci_ioremap_addr[bar_num];
+}
+
+int32_t zxdh_pf_msg_send_cmd(struct dh_core_dev *dh_dev, uint16_t module_id,
+							 void *msg, void *ack, bool is_sync)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	zxdh_reps_info *reps = (zxdh_reps_info *)(ack);
+	uint64_t vaddr = 0;
+	int32_t err = 0;
+
+	vaddr = (uint64_t)ZXDH_BAR_MSG_BASE(pf_dev->pci_ioremap_addr[0]);
+
+	err = zxdh_send_command(vaddr, pf_dev->pcie_id, module_id, msg, ack, TRUE);
+	if (err != 0) {
+		LOG_ERR("zxdh_send_command failed, err=%d\n", err);
+		return -1;
+	}
+
+	if (reps->flag != ZXDH_REPS_SUCC) {
+		LOG_ERR("failed reps->flag: 0x%x\n", reps->flag);
+		return -1;
+	}
+
+	return err;
+}
+
+int32_t zxdh_pf_query_port(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	struct port_message_recv recv = { 0 };
+	struct port_message_recv *recv_data = &recv;
+	struct zxdh_port_msg msg = { 0 };
+	struct zxdh_port_msg *payload = &msg;
+	struct zxdh_pannle_port *pnlport, *recvport;
+	int32_t ret = 0, idx = 0;
+
+	payload->pcie_id = zxdh_pf_get_pcie_id(dh_dev);
+
+	ret = zxdh_pf_msg_send_cmd(dh_dev, MODULE_PHYPORT_QUERY, payload, recv_data,
+							   true);
+	if (ret != 0) {
+		LOG_ERR("zxdh_pf_query_port send message failed \n");
+		goto out;
+	}
+
+	pf_dev->port_resource.pannel_num = recv_data->port_num;
+
+	LOG_INFO("zxdh query port num: %u\n", (uint32_t)recv_data->port_num);
+	for (idx = 0; idx < recv_data->port_num; idx++) {
+		if (idx >= ZXDH_PANNEL_PORT_MAX) {
+			LOG_ERR("query port num from fw out of range. \n");
+			continue;
+		}
+
+		pnlport = &pf_dev->port_resource.port[idx];
+		recvport =
+				(struct zxdh_pannle_port *)((uint8_t *)&recv_data->data[idx]);
+
+		pnlport->phyport = recvport->phyport;
+		pnlport->pannel_id = recvport->pannel_id;
+		pnlport->link_check_bit = recvport->link_check_bit;
+		pnlport->flags = 0;
+
+		LOG_INFO("[%d] pannel %u, phyport %u link check bit %u\n", idx,
+				 (uint32_t)pnlport->pannel_id, (uint32_t)pnlport->phyport,
+				 (uint32_t)pnlport->link_check_bit);
+	}
+
+out:
+	return ret;
+}
+
+int32_t zxdh_pf_query_fwinfo(struct dh_core_dev *dh_dev)
+{
+	int32_t ret = 0;
+
+	ret = zxdh_pf_query_port(dh_dev);
+	if (ret != 0) {
+		return ret;
+	}
+
+	return 0;
+}
+
+uint16_t zxdh_pf_get_queue_num(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	uint16_t qnum = 0;
+
+	qnum = ioread16(&pf_dev->common->num_queues);
+
+	return qnum;
+}
+
+uint16_t zxdh_pf_get_queue_size(struct dh_core_dev *dh_dev, uint16_t index)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	uint16_t queue_size = 0;
+
+	iowrite16(index, &pf_dev->common->queue_select);
+	queue_size = ioread16(&pf_dev->common->queue_size);
+
+	return queue_size;
+}
+
+uint16_t zxdh_pf_get_queue_vector(struct dh_core_dev *dh_dev, uint16_t channel,
+								  struct list_head *eqs_list,
+								  uint16_t queue_index)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	struct zxdh_pf_pci_common_cfg __iomem *cfg = pf_dev->common;
+	struct dh_eq_vqs *eq_vqs = NULL;
+	struct dh_eq_vqs *n;
+	int32_t i = 0;
+	int32_t msix_vec = ZXDH_MSI_NO_VECTOR;
+
+	iowrite16(queue_index, &cfg->queue_select);
+
+	list_for_each_entry_safe(eq_vqs, n, eqs_list, list) {
+		if (i++ == channel) {
+			iowrite16(eq_vqs->vq_s.core.irq->index, &cfg->queue_msix_vector);
+			break;
+		}
+	}
+
+	msix_vec = ioread16(&cfg->queue_msix_vector);
+
+	/* Flush the write out to device */
+	return msix_vec;
+}
+
+void zxdh_pf_release_queue_vector(struct dh_core_dev *dh_dev,
+								  int32_t queue_index)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	struct zxdh_pf_pci_common_cfg __iomem *cfg = pf_dev->common;
+
+	iowrite16(queue_index, &cfg->queue_select);
+	iowrite16(ZXDH_MSI_NO_VECTOR, &cfg->queue_msix_vector);
+}
+
+void zxdh_pf_set_queue_size(struct dh_core_dev *dh_dev, uint32_t index,
+							uint16_t size)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	iowrite16(index, &pf_dev->common->queue_select);
+	iowrite16(size, &pf_dev->common->queue_size);
+}
+
+void zxdh_pf_set_queue_address(struct dh_core_dev *dh_dev, uint32_t index,
+							   uint64_t desc_addr, uint64_t driver_addr,
+							   uint64_t device_addr)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	iowrite16(index, &pf_dev->common->queue_select);
+	iowrite32((uint32_t)desc_addr, &pf_dev->common->queue_desc_lo);
+	iowrite32(desc_addr >> 32, &pf_dev->common->queue_desc_hi);
+	iowrite32((uint32_t)driver_addr, &pf_dev->common->queue_avail_lo);
+	iowrite32(driver_addr >> 32, &pf_dev->common->queue_avail_hi);
+	iowrite32((uint32_t)device_addr, &pf_dev->common->queue_used_lo);
+	iowrite32(device_addr >> 32, &pf_dev->common->queue_used_hi);
+}
+
+int32_t zxdh_pf_get_vq_lock(struct dh_core_dev *dh_dev)
+{
+	int32_t i = 0;
+	int32_t val = 0;
+	int32_t wait_time = ZXDH_PF_WAIT_COUNT;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	for (i = 0; i < wait_time; i++) {
+		val = ioread32((const void __iomem *)(pf_dev->pci_ioremap_addr[0] +
+											  VQM_HOST_BAR_OFFSET +
+											  LOCK_VQ_REG_OFFSET));
+		udelay(ZXDH_PF_DELAY_US);
+		if (val & ZXDH_PF_LOCK_ENABLE_MASK) {
+			break;
+		}
+	}
+
+	if ((val & ZXDH_PF_LOCK_ENABLE_MASK) == 0) {
+		LOG_INFO("get phy vq_id is busy\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+int32_t zxdh_pf_release_vq_lock(struct dh_core_dev *dh_dev)
+{
+	int32_t val = 0;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	val = ioread32((const void __iomem *)(pf_dev->pci_ioremap_addr[0] +
+										  VQM_HOST_BAR_OFFSET +
+										  LOCK_VQ_REG_OFFSET));
+	if (val & ZXDH_PF_LOCK_ENABLE_MASK) {
+		iowrite32(ZXDH_PF_RELEASE_LOCK_VAL,
+				  (void __iomem *)(pf_dev->pci_ioremap_addr[0] +
+								   VQM_HOST_BAR_OFFSET + LOCK_VQ_REG_OFFSET));
+		return 0;
+	} else {
+		LOG_INFO("no lock need to be released\n");
+		return -1;
+	}
+}
+
+int32_t zxdh_pf_get_phy_vq(struct dh_core_dev *dh_dev, uint16_t index)
+{
+	int32_t phy_vq_reg = 0;
+	int32_t vq_reg_num = ZXDH_MAX_QUEUES_NUM / ZXDH_PHY_REG_BITS;
+	uint32_t val = 0;
+	uint32_t done = 0;
+	uint8_t queue_type = 0;
+	int32_t j = 0;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	int32_t phy_index = 0;
+
+	for (phy_vq_reg = 0; phy_vq_reg < vq_reg_num; phy_vq_reg++) {
+		val = ioread32((const void __iomem *)(pf_dev->pci_ioremap_addr[0] +
+											  PHY_VQ_REG_OFFSET +
+											  phy_vq_reg * 4));
+
+		if (index % ZXDH_PF_POWER_INDEX2 == 0) {
+			queue_type = ZXDH_PF_RQ_TYPE;
+		} else {
+			queue_type = ZXDH_PF_TQ_TYPE;
+		}
+
+		for (j = queue_type; j < ZXDH_PHY_REG_BITS;
+			 j = j + ZXDH_PF_POWER_INDEX2) {
+			if ((val & (ZXDH_PF_GET_PHY_INDEX_BIT << j)) == 0) {
+				val |= (ZXDH_PF_GET_PHY_INDEX_BIT << j);
+				iowrite32(val,
+						  (void __iomem *)(pf_dev->pci_ioremap_addr[0] +
+										   PHY_VQ_REG_OFFSET + phy_vq_reg * 4));
+				phy_index = phy_vq_reg * ZXDH_PHY_REG_BITS + j;
+				done = ZXDH_PF_GET_PHY_INDEX_DONE;
+				break;
+			}
+		}
+
+		if (done == ZXDH_PF_GET_PHY_INDEX_DONE) {
+			return phy_index;
+		}
+	}
+
+	LOG_INFO("no availd phy_index\n");
+
+	return -1;
+}
+
+int32_t zxdh_pf_release_phy_vq(struct dh_core_dev *dh_dev, uint32_t *phy_index,
+							   uint16_t total_qnum)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	uint16_t lch = 0;
+	uint16_t widx = 0;
+	uint16_t bidx = 0;
+	uint32_t val = 0;
+
+	for (lch = 0; lch < total_qnum; lch++) {
+		if (phy_index[lch] >= ZXDH_MAX_QUEUES_NUM) {
+			continue;
+		}
+
+		widx = phy_index[lch] / 32; // 4byte -> 32bits
+		bidx = phy_index[lch] % 32;
+
+		udelay(ZXDH_PF_DELAY_US);
+		val = ioread32((const void __iomem *)(pf_dev->pci_ioremap_addr[0] +
+											  PHY_VQ_REG_OFFSET + widx * 4));
+		val &= ~(1 << bidx);
+		iowrite32(val, (void __iomem *)(pf_dev->pci_ioremap_addr[0] +
+										PHY_VQ_REG_OFFSET + widx * 4));
+	}
+
+	return 0;
+}
+
+void zxdh_pf_update_link_info(struct dh_core_dev *dh_dev,
+							  struct link_info_struct *link_info_val)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	if (pf_dev->link_up && link_info_val->speed == SPEED_UNKNOWN) {
+		LOG_INFO("pf_dev->link_up is %d and link_info_val->speed is %d, can't "
+				 "update pf info\n",
+				 pf_dev->link_up, link_info_val->speed);
+		return;
+	}
+	pf_dev->speed = link_info_val->speed;
+	pf_dev->autoneg_enable = link_info_val->autoneg_enable;
+	pf_dev->supported_speed_modes = link_info_val->supported_speed_modes;
+	pf_dev->advertising_speed_modes = link_info_val->advertising_speed_modes;
+	pf_dev->duplex = link_info_val->duplex;
+}
+
+int32_t zxdh_pf_get_drv_msg(struct dh_core_dev *dh_dev, uint8_t *drv_version,
+							uint8_t *drv_version_len)
+{
+	*drv_version_len = sizeof(zxdh_pf_driver_version);
+	memcpy(drv_version, zxdh_pf_driver_version, *drv_version_len);
+	return 0;
+}
+
+void zxdh_pf_set_vepa(struct dh_core_dev *dh_dev, bool setting)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	pf_dev->vepa = setting;
+}
+
+bool zxdh_pf_get_vepa(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	return pf_dev->vepa;
+}
+
+int32_t zxdh_pf_request_port(struct dh_core_dev *dh_dev, void *data)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	uint8_t port_num = pf_dev->port_resource.pannel_num;
+	struct zxdh_pannle_port *port;
+	struct zxdh_pannle_port *req_data = (struct zxdh_pannle_port *)data;
+	int32_t idx = 0;
+
+	for (idx = 0; idx < port_num; idx++) {
+		port = &pf_dev->port_resource.port[idx];
+		if (!(port->flags & PORT_FLAGS_ALLOC_STAT)) {
+			req_data->phyport = port->phyport;
+			req_data->pannel_id = port->pannel_id;
+			req_data->link_check_bit = port->link_check_bit;
+			port->flags |= PORT_FLAGS_ALLOC_STAT;
+			break;
+		}
+	}
+
+	if (idx == port_num) {
+		LOG_ERR("failed to obtain the panel information from the riscv, or this "
+				"part is not released when the aux is removed\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+int32_t zxdh_pf_release_port(struct dh_core_dev *dh_dev, uint32_t pnl_id)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	uint8_t port_num = pf_dev->port_resource.pannel_num;
+	struct zxdh_pannle_port *port;
+	int32_t idx = 0;
+
+	for (idx = 0; idx < port_num; idx++) {
+		port = &pf_dev->port_resource.port[idx];
+		if (pnl_id == port->pannel_id) {
+			port->flags &= ~PORT_FLAGS_ALLOC_STAT;
+			break;
+		}
+	}
+
+	return 0;
+}
+
+void zxdh_pf_set_bond_num(struct dh_core_dev *dh_dev, bool add)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	if (add) {
+		pf_dev->bond_num++;
+	} else {
+		pf_dev->bond_num--;
+	}
+}
+
+bool zxdh_pf_if_init(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	if (pf_dev->bond_num == 0) {
+		return true;
+	}
+
+	return false;
+}
+
+void zxdh_pf_set_init_comp_flag(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	pf_dev->aux_comp_flag = ZXDH_AUX_COMP_FLAG;
+	return;
+}
+
+struct zxdh_en_sf_if en_sf_ops = {
+	.en_sf_map_vq_notify = zxdh_pf_map_vq_notify,
+	.en_sf_unmap_vq_notify = zxdh_pf_unmap_vq_notify,
+	.en_sf_set_status = zxdh_pf_set_status,
+	.en_sf_get_status = zxdh_pf_get_status,
+	.en_sf_get_features = zxdh_pf_get_features,
+	.en_sf_set_features = zxdh_pf_set_features,
+	.en_sf_set_vf_mac = zxdh_pf_set_vf_mac,
+	.en_sf_get_vf_mac = zxdh_pf_get_vf_mac,
+	.en_sf_set_mac = zxdh_set_mac,
+	.en_sf_get_mac = zxdh_get_mac,
+	.en_sf_set_queue_enable = zxdh_pf_set_queue_enable,
+	.en_sf_get_channels_num = zxdh_pf_get_vqs_channels_num,
+	.en_sf_get_queue_num = zxdh_pf_get_queue_num,
+	.en_sf_get_queue_size = zxdh_pf_get_queue_size,
+	.en_sf_get_queue_vector = zxdh_pf_get_queue_vector,
+	.en_sf_release_queue_vector = zxdh_pf_release_queue_vector,
+	.en_sf_set_queue_size = zxdh_pf_set_queue_size,
+	.en_sf_set_queue_address = zxdh_pf_set_queue_address,
+	.en_sf_vq_irqs_request = zxdh_pf_vq_irqs_request,
+	.en_sf_affinity_irqs_release = zxdh_pf_affinity_irqs_release,
+	.en_sf_switch_irq = zxdh_pf_switch_irq,
+	.en_sf_get_vq_lock = zxdh_pf_get_vq_lock,
+	.en_sf_release_vq_lock = zxdh_pf_release_vq_lock,
+	.en_sf_get_phy_vq = zxdh_pf_get_phy_vq,
+	.en_sf_release_phy_vq = zxdh_pf_release_phy_vq,
+	.en_sf_get_epbdf = zxdh_pf_get_epbdf,
+	.en_sf_get_vport = zxdh_pf_get_vport,
+	.en_sf_get_coredev_type = zxdh_pf_get_coredev_type,
+	.en_sf_get_pcie_id = zxdh_pf_get_pcie_id,
+	.en_sf_get_slot_id = zxdh_pf_get_slot_id,
+	.en_sf_is_bond = zxdh_pf_is_bond,
+	.en_sf_get_pdev = zxdh_pf_get_pdev,
+	.en_sf_get_bar_virt_addr = zxdh_pf_get_bar_virt_addr,
+	.en_sf_msg_send_cmd = zxdh_pf_msg_send_cmd,
+	.en_sf_async_eq_enable = zxdh_pf_async_eq_enable,
+	.en_sf_get_vf_item = zxdh_pf_get_vf_item,
+	.en_sf_set_pf_link_up = zxdh_pf_set_pf_link_up,
+	.en_sf_get_pf_link_up = zxdh_pf_get_pf_link_up,
+	.en_sf_update_pf_link_info = zxdh_pf_update_link_info,
+	.en_sf_get_drv_msg = zxdh_pf_get_drv_msg,
+	.en_sf_get_vepa = zxdh_pf_get_vepa,
+	.en_sf_set_vepa = zxdh_pf_set_vepa,
+	.en_sf_set_bond_num = zxdh_pf_set_bond_num,
+	.en_sf_if_init = zxdh_pf_if_init,
+	.en_sf_request_port_info = zxdh_pf_request_port,
+	.en_sf_release_port_info = zxdh_pf_release_port,
+	.en_sf_get_link_info_from_vqm = zxdh_pf_get_link_info_from_vqm,
+	.en_sf_set_vf_link_info = zxdh_pf_set_vf_link_info,
+	.en_sf_set_pf_phy_port = zxdh_pf_set_pf_phy_port,
+	.en_sf_get_pf_phy_port = zxdh_pf_get_pf_phy_port,
+	.en_sf_set_init_comp_flag = zxdh_pf_set_init_comp_flag,
+};
+
+void zxdh_adev_release(struct device *dev)
+{
+}
+
+static DEFINE_IDA(zxdh_adev_ida);
+
+int32_t zxdh_plug_aux_dev(struct dh_core_dev *dh_dev, int32_t idx)
+{
+	struct auxiliary_device *adev = NULL;
+	struct zxdh_pf_device *pf_dev = NULL;
+	struct zxdh_en_sf_container *sf_con = NULL;
+	struct zxdh_pf_adev *pf_adevs_table = NULL;
+	int32_t ret = 0;
+
+	pf_dev = dh_core_priv(dh_dev);
+
+	if (idx >= pf_dev->adevs_num) {
+		return 0;
+	}
+
+	pf_adevs_table = &pf_dev->adevs_table[idx];
+	if (pf_adevs_table->adev != NULL) {
+		return 0;
+	}
+
+	sf_con = kzalloc(sizeof(struct zxdh_en_sf_container), GFP_KERNEL);
+
+	if (unlikely(sf_con == NULL)) {
+		LOG_ERR("zxadev kzalloc is null\n");
+		return -ENOMEM;
+	}
+
+	pf_adevs_table->aux_idx = ida_alloc(&zxdh_adev_ida, GFP_KERNEL);
+	if (pf_adevs_table->aux_idx < 0) {
+		LOG_ERR("failed to allocate device id for aux drvs\n");
+		goto free_kzalloc;
+	}
+
+	adev = &sf_con->adev;
+
+	adev->id = pf_adevs_table->aux_idx;
+	adev->dev.parent = &dh_dev->pdev->dev;
+	adev->dev.release = zxdh_adev_release;
+	adev->name = ZXDH_PF_EN_SF_DEV_ID_NAME;
+
+	pf_adevs_table->adev = adev;
+	sf_con->dh_dev = dh_dev;
+	sf_con->ops = &en_sf_ops;
+
+	ret = auxiliary_device_init(adev);
+	if (ret != 0) {
+		LOG_ERR("auxiliary_device_init failed: %d\n", ret);
+		goto free_ida_alloc;
+	}
+
+	ret = auxiliary_device_add(adev);
+	if (ret != 0) {
+		LOG_ERR("auxiliary_device_add failed: %d\n", ret);
+		goto release_aux_init;
+	}
+
+	LOG_INFO("zxdh_plug_aux_dev finish\n");
+
+	return 0;
+
+release_aux_init:
+	auxiliary_device_uninit(adev);
+free_ida_alloc:
+	ida_simple_remove(&zxdh_adev_ida, pf_adevs_table->aux_idx);
+	pf_adevs_table->aux_idx = -1;
+free_kzalloc:
+	kfree(sf_con);
+	sf_con = NULL;
+	return ret;
+}
+
+void zxdh_unplug_aux_dev(struct dh_core_dev *dh_dev, int32_t idx)
+{
+	struct zxdh_pf_device *pf_dev = NULL;
+	struct zxdh_en_sf_container *sf_con = NULL;
+	struct zxdh_pf_adev *pf_adevs_table = NULL;
+
+	pf_dev = dh_core_priv(dh_dev);
+	if (idx >= pf_dev->adevs_num) {
+		return;
+	}
+
+	pf_adevs_table = &pf_dev->adevs_table[idx];
+	if (!pf_adevs_table->adev) {
+		return;
+	}
+
+	sf_con = container_of(pf_adevs_table->adev, struct zxdh_en_sf_container,
+						  adev);
+
+	auxiliary_device_delete(pf_adevs_table->adev);
+	auxiliary_device_uninit(pf_adevs_table->adev);
+	ida_simple_remove(&zxdh_adev_ida, pf_adevs_table->aux_idx);
+	pf_adevs_table->aux_idx = -1;
+	kfree(sf_con);
+	sf_con = NULL;
+
+	return;
+}
+
+int32_t dh_pf_vf_vport_get(struct dh_core_dev *dev, uint16_t vf_idx,
+						   uint16_t *vport)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+	uint16_t pcie_id = 0;
+	struct zxdh_pci_bar_msg in = { 0 };
+	struct zxdh_msg_recviver_mem result = { 0 };
+	uint8_t recv_buf[8] = { 0 };
+	int32_t ret = 0;
+
+	if (vport == NULL) {
+		return BAR_MSG_ERR_NULL;
+	}
+
+	pcie_id = FIND_VF_PCIE_ID(pf_dev->pcie_id, vf_idx);
+
+	in.virt_addr = (uint64_t)ZXDH_BAR_MSG_BASE(pf_dev->pci_ioremap_addr[0]);
+	in.payload_addr = &pcie_id;
+	in.payload_len = sizeof(pcie_id);
+	in.src = MSG_CHAN_END_PF;
+	in.dst = MSG_CHAN_END_RISC;
+	in.event_id = MODULE_VPORT_GET;
+	in.src_pcieid = pf_dev->pcie_id;
+
+	result.recv_buffer = recv_buf;
+	result.buffer_len = sizeof(recv_buf);
+
+	ret = zxdh_bar_chan_sync_msg_send(&in, &result);
+	switch (ret) {
+	case BAR_MSG_OK: {
+		*vport = *(uint16_t *)(recv_buf + 4);
+		LOG_INFO("pf(0x%x) get vf(%u) vport(0x%x) success\n", pf_dev->pcie_id,
+				 vf_idx, *vport);
+		break;
+	}
+	default: {
+		LOG_ERR("Failed to pf(0x%x) get vf(%u) vport, ret:%d.\n", pcie_id,
+				vf_idx, ret);
+		break;
+	}
+	}
+
+	return ret;
+}
+
+int32_t dh_pf_vf_item_init(struct dh_core_dev *dev, uint16_t vf_idx)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+	struct zxdh_vf_item *vf_item = NULL;
+
+	if (pf_dev->vf_item == NULL) {
+		LOG_ERR("vf_item is NULL\n");
+		return -EINVAL;
+	}
+	vf_item = &pf_dev->vf_item[vf_idx];
+	vf_item->link_forced = false;
+	vf_item->vport = pf_dev->vf_item[0].vport + vf_idx;
+	vf_item->enable = true;
+	vf_item->spoofchk = true;
+	return 0;
+}
+
+int32_t dh_pf_vf_item_uninit(struct dh_core_dev *dev, uint16_t vf_idx)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+	struct zxdh_vf_item *vf_item = NULL;
+
+	if (pf_dev->vf_item == NULL) {
+		LOG_ERR("vf_item is NULL\n");
+		return -EINVAL;
+	}
+	vf_item = &pf_dev->vf_item[vf_idx];
+	eth_zero_addr(vf_item->mac);
+	vf_item->pf_set_mac = false;
+	vf_item->enable = false;
+	vf_item->vlan = 0;
+	vf_item->qos = 0;
+	vf_item->spoofchk = false;
+	return 0;
+}
+
+int32_t dh_pf_vf_enable(struct dh_core_dev *dev, int32_t num_vfs)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+	int32_t vf_idx = 0;
+	int32_t ret = 0;
+
+	ret = dh_pf_vf_vport_get(dev, 0, &pf_dev->vf_item[0].vport);
+	if (ret != 0) {
+		return ret;
+	}
+
+	for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) {
+		ret = dh_pf_vf_item_init(dev, vf_idx);
+		if (ret != 0) {
+			LOG_ERR("Failed to init vf(%d) item\n", vf_idx);
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+void dh_pf_vf_disable(struct dh_core_dev *dev, int32_t num_vfs)
+{
+	int32_t vf_idx = 0;
+
+	for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) {
+		dh_pf_vf_item_uninit(dev, vf_idx);
+	}
+}
+
+int32_t dh_pf_sriov_enable(struct pci_dev *pdev, int32_t num_vfs)
+{
+	struct dh_core_dev *dev = pci_get_drvdata(pdev);
+	int32_t pre_existing_vfs = pci_num_vf(pdev);
+	int32_t ret = 0;
+
+	if ((pre_existing_vfs != 0) && (pre_existing_vfs == num_vfs)) {
+		return 0;
+	}
+
+	ret = dh_pf_vf_enable(dev, num_vfs);
+	if (ret != 0) {
+		LOG_ERR("Failed to enable vf\n");
+		return ret;
+	}
+
+#ifdef ZXDH_SRIOV_SYSFS_EN
+	ret = zxdh_create_vfs_sysfs(dev, num_vfs);
+	if (ret != 0) {
+		LOG_ERR("zxdh_create_vfs_sysfs failed : %d\n", ret);
+		goto err_create_vfs_sysfs;
+	}
+#endif
+
+	ret = pci_enable_sriov(pdev, num_vfs);
+	if (ret != 0) {
+		LOG_ERR("pci_enable_sriov failed : %d\n", ret);
+		goto err_pci_enable_sriov;
+	}
+
+	return ret;
+
+err_pci_enable_sriov:
+#ifdef ZXDH_SRIOV_SYSFS_EN
+	zxdh_sriov_sysfs_exit(dev);
+err_create_vfs_sysfs:
+#endif
+	dh_pf_vf_disable(dev, num_vfs);
+
+	return ret;
+}
+
+void dh_pf_sriov_disable(struct pci_dev *pdev)
+{
+	struct dh_core_dev *dev = pci_get_drvdata(pdev);
+	int32_t num_vfs = pci_num_vf(pdev);
+
+	pci_disable_sriov(pdev);
+#ifdef ZXDH_SRIOV_SYSFS_EN
+	zxdh_destroy_vfs_sysfs(dev, num_vfs);
+#endif
+	dh_pf_vf_disable(dev, num_vfs);
+}
+
+int32_t dh_pf_vf_item_create(struct dh_core_dev *dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+
+	if (dev->coredev_type == DH_COREDEV_PF) {
+		pf_dev->vf_item = kzalloc(sizeof(struct zxdh_vf_item) * ZXDH_VF_NUM_MAX,
+								  GFP_KERNEL);
+		if (pf_dev->vf_item == NULL) {
+			return -ENOMEM;
+		}
+	}
+
+	return 0;
+}
+
+void dh_pf_vf_item_destroy(struct dh_core_dev *dev, bool disable_vf)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+
+	if (dev->coredev_type == DH_COREDEV_PF) {
+		if (disable_vf) {
+			pci_disable_sriov(dev->pdev);
+		}
+		if (pf_dev->vf_item != NULL) {
+			kfree(pf_dev->vf_item);
+			pf_dev->vf_item = NULL;
+		}
+	}
+}
+
+int32_t dh_pf_pcie_id_get(struct dh_core_dev *dh_dev)
+{
+	int32_t pos = 0;
+	uint8_t type = 0;
+	uint16_t padding = 0;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	struct pci_dev *pdev = dh_dev->pdev;
+
+	if (dh_dev->coredev_type == DH_COREDEV_PF) {
+		if (pdev->bus == NULL) {
+			LOG_ERR("pdev->bus is NULL!\n");
+			return -1;
+		}
+		pf_dev->slot_id = pdev->bus->number;
+		LOG_INFO("pf_dev->slot_id: %d\n", pf_dev->slot_id);
+	}
+	for (pos = pci_find_capability(pdev, PCI_CAP_ID_VNDR); pos > 0;
+		 pos = pci_find_next_capability(pdev, pos, PCI_CAP_ID_VNDR)) {
+		pci_read_config_byte(
+				pdev, pos + offsetof(struct zxdh_pf_pci_cap, cfg_type), &type);
+
+		if (type == ZXDH_PCI_CAP_PCI_CFG) {
+			pci_read_config_word(
+					pdev, pos + offsetof(struct zxdh_pf_pci_cap, padding[0]),
+					&padding);
+			pf_dev->pcie_id = padding;
+			LOG_INFO("pf_dev->pcie_id: 0x%x\n", pf_dev->pcie_id);
+			return 0;
+		}
+	}
+	return -1;
+}
+
+static uint64_t pci_size(uint64_t base, uint64_t maxbase, uint64_t mask)
+{
+	uint64_t size = mask & maxbase;
+
+	if (!size)
+		return 0;
+	size = size & ~(size - 1);
+	if (base == maxbase && ((base | (size - 1)) & mask) != mask)
+		return 0;
+	return size;
+}
+
+int32_t zxdh_send_pxe_status_to_riscv(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	zxdh_cfg_np_msg msg = { 0 };
+	zxdh_reps_info ack = { 0 };
+	uint64_t vaddr = 0;
+	int32_t err = 0;
+
+	if (dh_dev->coredev_type != DH_COREDEV_PF) {
+		return 0;
+	}
+
+	msg.dev_id = 0;
+	msg.type = ZXDH_CFG_NPSDK_TYPE;
+	msg.operate_mode = ZXDH_STOP_PXE_MODE;
+
+	vaddr = (uint64_t)ZXDH_BAR_MSG_BASE(pf_dev->pci_ioremap_addr[0]);
+
+	err = zxdh_send_command(vaddr, pf_dev->pcie_id, MODULE_NPSDK, &msg, &ack,
+							true);
+	if (err != 0) {
+		LOG_ERR("send pxe status to config np failed: %d\n", err);
+	}
+
+	return err;
+}
+
+int32_t dh_pf_sriov_cap_cfg_init(struct dh_core_dev *dh_dev)
+{
+	int32_t pos = 0;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	struct pci_dev *pdev = dh_dev->pdev;
+	uint32_t bar_address32 = 0;
+	uint64_t bar_address64 = 0;
+	uint64_t bar_size64 = 0;
+	uint32_t bar_size32 = 0;
+	uint64_t mask64 = 0;
+	uint32_t mem_type = 0;
+	uint16_t nr_virtfn = 0;
+
+	if (dh_dev->coredev_type == DH_COREDEV_VF) {
+		return 0;
+	}
+
+	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
+	if (pos == 0) {
+		return 0;
+	}
+	pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, &nr_virtfn);
+	LOG_INFO("pf_dev->total vf: %d\n", nr_virtfn);
+
+	if (nr_virtfn == 0) {
+		return 0;
+	}
+
+	pci_read_config_dword(pdev, pos + PCI_SRIOV_BAR, &bar_address32);
+	pci_write_config_dword(pdev, pos + PCI_SRIOV_BAR, ~0);
+	pci_read_config_dword(pdev, pos + PCI_SRIOV_BAR, &bar_size32);
+	pci_write_config_dword(pdev, pos + PCI_SRIOV_BAR, bar_address32);
+
+	bar_size64 = bar_size32 & PCI_BASE_ADDRESS_MEM_MASK;
+	bar_address64 = bar_address32 & PCI_BASE_ADDRESS_MEM_MASK;
+	mask64 = (uint32_t)PCI_BASE_ADDRESS_MEM_MASK;
+	mem_type = bar_address32 & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
+
+	if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
+		pci_read_config_dword(pdev, pos + PCI_SRIOV_BAR + 4, &bar_address32);
+		pci_write_config_dword(pdev, pos + PCI_SRIOV_BAR + 4, ~0);
+		pci_read_config_dword(pdev, pos + PCI_SRIOV_BAR + 4, &bar_size32);
+		pci_write_config_dword(pdev, pos + PCI_SRIOV_BAR + 4, bar_address32);
+
+		bar_size64 |= ((uint64_t)bar_size32 << 32);
+		bar_address64 |= ((uint64_t)bar_address32 << 32);
+		mask64 |= ((uint64_t)~0 << 32);
+	}
+
+	bar_size64 = pci_size(bar_address64, bar_size64, mask64);
+	if (!bar_size64) {
+		LOG_INFO("reg 0x%x: invalid BAR (can't size)\n", pos);
+	}
+
+	LOG_INFO("pf cap vf0 bar0 bar_address: 0x%llx , size: 0x%llx\n",
+			 bar_address64, bar_size64);
+
+	pf_dev->pf_sriov_cap_base =
+			(void __iomem *)ioremap(bar_address64, bar_size64 * nr_virtfn);
+
+	if (!pf_dev->pf_sriov_cap_base) {
+		LOG_ERR("ioremap(0x%llx, 0x%llx) failed\n", bar_address64,
+				bar_size64 * nr_virtfn);
+		return -1;
+	}
+	pf_dev->sriov_bar_size = bar_size64;
+	return 0;
+}
+
+static uint8_t zxdh_pf_fwcap_readb(struct dh_core_dev *dh_dev, uint32_t offset)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	uint64_t vaddr = (uint64_t)ZXDH_BAR_FWCAP(pf_dev->pci_ioremap_addr[0]);
+
+	return readb((const volatile void __iomem *)(vaddr + offset));
+}
+
+static bool zxdh_pf_is_ovs(struct dh_core_dev *dh_dev)
+{
+	uint8_t product = 0;
+
+	product = zxdh_pf_fwcap_readb(dh_dev, ZXDH_PRODUCT_TYPE);
+	LOG_INFO("fwcap read product type: %d\n", (int32_t)product);
+
+	if ((product == ZXDH_PRODUCT_OVS) || (product == ZXDH_PRODUCT_NEO) ||
+		(product == ZXDH_PRODUCT_EVB_EP0) ||
+		(product == ZXDH_PRODUCT_EVB_EP0_EP4)) {
+		return true;
+	}
+
+	return false;
+}
+
+static void zxdh_pf_set_pannel_port_num(struct dh_core_dev *dh_dev,
+										int port_num)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	pf_dev->pannel_port_num = port_num;
+
+	return;
+}
+
+static void zxdh_pf_request_pannel_port_num(struct dh_core_dev *dh_dev,
+											int *port_num)
+{
+	*port_num = (int)zxdh_pf_fwcap_readb(dh_dev, ZXDH_PANNEL_PORT_NUM);
+}
+
+static int32_t zxdh_pf_lag_init(struct dh_core_dev *dh_dev, int32_t *port_num)
+{
+	int port_num_default = 1;
+
+	/* BOND PF && 非OVS场景，则产生异常 */
+	if (zxdh_pf_is_bond(dh_dev) && !zxdh_pf_is_ovs(dh_dev)) {
+		return -1;
+	}
+
+	if (!dh_core_is_pf(dh_dev) || !zxdh_pf_is_bond(dh_dev) ||
+		!zxdh_pf_is_ovs(dh_dev)) {
+		goto out;
+	}
+
+	zxdh_pf_request_pannel_port_num(dh_dev, &port_num_default);
+	zxdh_pf_set_pannel_port_num(dh_dev, port_num_default);
+	zxdh_regitster_ldev(dh_dev);
+
+	LOG_INFO("zxdh pf lag init finish(port num %d)\n", port_num_default);
+out:
+	zxdh_pf_set_pannel_port_num(dh_dev, port_num_default);
+	*port_num = port_num_default;
+	return 0;
+}
+
+static void zxdh_pf_lag_exit(struct dh_core_dev *dh_dev)
+{
+	zxdh_unregitster_ldev(dh_dev);
+}
+
+int32_t dh_pf_adevs_table_init(struct dh_core_dev *dh_dev, int32_t nr)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	pf_dev->adevs_table =
+			kzalloc(sizeof(*(pf_dev->adevs_table)) * nr, GFP_KERNEL);
+	if (!pf_dev->adevs_table) {
+		pf_dev->adevs_num = 0;
+		return -ENOMEM;
+	}
+
+	pf_dev->adevs_num = nr;
+
+	return 0;
+}
+
+void dh_pf_adevs_table_destroy(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	if (dh_dev->coredev_type == DH_COREDEV_PF) {
+		if (pf_dev->adevs_table != NULL) {
+			kfree(pf_dev->adevs_table);
+			pf_dev->adevs_table = NULL;
+			pf_dev->adevs_num = 0;
+		}
+	}
+}
+
+void zxdh_unplug_aux_dev_all(struct dh_core_dev *dh_dev)
+{
+	int32_t idx;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	for (idx = 0; idx < pf_dev->adevs_num; idx++) {
+		zxdh_unplug_aux_dev(dh_dev, idx);
+	}
+}
+
+static int32_t dh_pf_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+	struct dh_core_dev *dh_dev = NULL;
+	struct zxdh_pf_device *pf_dev = NULL;
+	struct devlink *devlink = NULL;
+	int32_t ret = 0;
+	int32_t idx = 0;
+	int32_t port_num = 0;
+
+	LOG_INFO("pf driver start to probe");
+
+	devlink = zxdh_devlink_alloc(&pdev->dev, &dh_pf_devlink_ops,
+								 sizeof(struct zxdh_pf_device));
+	if (devlink == NULL) {
+		LOG_ERR("devlink alloc failed\n");
+		return -ENOMEM;
+	}
+
+	dh_dev = devlink_priv(devlink);
+	dh_dev->device = &pdev->dev;
+	dh_dev->pdev = pdev;
+	dh_dev->devlink_ops = &dh_pf_core_devlink_ops;
+
+	pf_dev = dh_core_priv(dh_dev);
+	pf_dev->vepa = false;
+
+	dh_dev->coredev_type = GET_COREDEV_TYPE(pdev);
+	ret = dh_pf_pci_init(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("dh_pf_pci_init failed: %d\n", ret);
+		goto err_irq_table_init;
+	}
+
+	ret = dh_pf_pcie_id_get(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("dh_pf_pcie_id_get failed: %d\n", ret);
+		goto err_pci;
+	}
+
+	ret = dh_pf_vf_item_create(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("Failed to alloc vf item\n");
+		goto err_pci;
+	}
+
+	ret = dh_pf_irq_table_init(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("Failed to alloc IRQs\n");
+		goto err_vf_item;
+	}
+
+	ret = dh_pf_eq_table_init(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("Failed to alloc IRQs\n");
+		goto err_eq_table_init;
+	}
+
+	ret = dh_pf_events_init(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("failed to initialize events\n");
+		goto err_events_init;
+	}
+
+	ret = dh_pf_irq_table_create(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("Failed to alloc IRQs\n");
+		goto err_irq_table_create;
+	}
+
+	ret = dh_pf_eq_table_create(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("Failed to alloc EQs\n");
+		goto err_eq_table_create;
+	}
+
+	ret = dh_pf_sriov_cap_cfg_init(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_pf_modern_cfg_init failed: %d\n", ret);
+		goto err_sriov_cap_init;
+	}
+
+	ret = zxdh_pf_modern_cfg_init(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_pf_modern_cfg_init failed: %d\n", ret);
+		goto err_cfg_init;
+	}
+
+	ret = zxdh_send_pxe_status_to_riscv(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_send_pxe_status_to_riscv failed: %d\n", ret);
+		goto err_send_pxe_status;
+	}
+
+#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
+	zxdh_devlink_register(devlink);
+#else
+	zxdh_devlink_register(devlink, &pdev->dev);
+#endif
+
+	zxdh_pf_initialized_init(dh_dev);
+
+	ret = zxdh_pf_dpp_init(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_pf_dpp_init failed: %d\n", ret);
+		goto err_dpp_init;
+	}
+
+	ret = zxdh_pf_query_fwinfo(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_pf_query_fwinfo failed: %d\n", ret);
+		goto err_query_fwinfo;
+	}
+
+	ret = zxdh_pf_lag_init(dh_dev, &port_num);
+	if (ret != 0) {
+		LOG_ERR("zxdh_pf_lag_init failed: %d\n", ret);
+		goto err_query_fwinfo;
+	}
+
+	ret = dh_pf_adevs_table_init(dh_dev, port_num);
+	if (ret != 0) {
+		LOG_ERR("dh_pf_adevs_table_init failed: %d\n", ret);
+		goto err_adevs_tbl_init;
+	}
+
+	for (idx = 0; idx < port_num; idx++) {
+		zxdh_plug_aux_dev(dh_dev, idx);
+	}
+
+#ifdef PTP_DRIVER_INTERFACE_EN
+	if (dh_dev->coredev_type == DH_COREDEV_PF) {
+		ret = zxdh_ptp_init(dh_dev);
+		if (ret != 0) {
+			LOG_ERR("zxdh_ptp_init failed: %d\n", ret);
+		}
+	}
+#endif
+#ifdef ZXDH_SRIOV_SYSFS_EN
+	ret = zxdh_sriov_sysfs_init(dh_dev);
+	if (ret != 0) {
+		LOG_ERR("zxdh_sriov_sysfs_init failed: %d, vport = %x\n", ret,
+				pf_dev->vport);
+		goto err_sriov_sysfs;
+	}
+#endif
+
+	LOG_INFO("pf driver probe completed\n");
+
+	return 0;
+
+err_sriov_sysfs:
+	zxdh_ptp_stop(dh_dev);
+err_adevs_tbl_init:
+	zxdh_pf_lag_exit(dh_dev);
+err_query_fwinfo:
+	zxdh_pf_dpp_uninit(dh_dev);
+err_dpp_init:
+	zxdh_pf_initialized_uninit(dh_dev);
+	zxdh_devlink_unregister(devlink);
+err_send_pxe_status:
+	zxdh_pf_modern_cfg_uninit(dh_dev);
+err_cfg_init:
+	dh_pf_sriov_cap_cfg_uninit(dh_dev);
+err_sriov_cap_init:
+	dh_pf_eq_table_destroy(dh_dev);
+err_eq_table_create:
+	dh_pf_irq_table_destroy(dh_dev);
+err_irq_table_create:
+	dh_pf_events_uninit(dh_dev);
+err_events_init:
+	dh_eq_table_cleanup(dh_dev);
+err_eq_table_init:
+	dh_irq_table_cleanup(dh_dev);
+err_vf_item:
+	dh_pf_vf_item_destroy(dh_dev, true);
+err_pci:
+	dh_pf_pci_close(dh_dev);
+err_irq_table_init:
+	zxdh_devlink_free(devlink);
+	return ret;
+}
+
+static void dh_pf_remove(struct pci_dev *pdev)
+{
+	struct dh_core_dev *dh_dev = pci_get_drvdata(pdev);
+	struct devlink *devlink = priv_to_devlink(dh_dev);
+
+	LOG_INFO("pf driver start to remove\n");
+
+#ifdef ZXDH_SRIOV_SYSFS_EN
+	zxdh_sriov_sysfs_exit(dh_dev);
+#endif
+#ifdef PTP_DRIVER_INTERFACE_EN
+	if (dh_dev->coredev_type == DH_COREDEV_PF) {
+		zxdh_ptp_stop(dh_dev);
+	}
+#endif
+	zxdh_unplug_aux_dev_all(dh_dev);
+	dh_pf_adevs_table_destroy(dh_dev);
+
+	zxdh_pf_lag_exit(dh_dev);
+	zxdh_pf_dpp_uninit(dh_dev);
+	zxdh_pf_initialized_uninit(dh_dev);
+
+	zxdh_devlink_unregister(devlink);
+	zxdh_pf_modern_cfg_uninit(dh_dev);
+	dh_pf_sriov_cap_cfg_uninit(dh_dev);
+	dh_pf_eq_table_destroy(dh_dev);
+	dh_pf_irq_table_destroy(dh_dev);
+	dh_pf_events_uninit(dh_dev);
+	dh_eq_table_cleanup(dh_dev);
+	dh_irq_table_cleanup(dh_dev);
+	dh_pf_vf_item_destroy(dh_dev, true);
+	dh_pf_pci_close(dh_dev);
+	zxdh_devlink_free(devlink);
+
+	pci_set_drvdata(pdev, NULL);
+	LOG_INFO("pf driver remove completed\n");
+
+	return;
+}
+
+static int32_t dh_pf_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+	return 0;
+}
+
+static int32_t dh_pf_resume(struct pci_dev *pdev)
+{
+	return 0;
+}
+
+static void dh_pf_shutdown(struct pci_dev *pdev)
+{
+	struct dh_core_dev *dh_dev = pci_get_drvdata(pdev);
+	struct devlink *devlink = priv_to_devlink(dh_dev);
+
+	LOG_INFO("dh_pf_shutdown start\n");
+	dh_pf_adevs_table_destroy(dh_dev);
+
+	zxdh_pf_lag_exit(dh_dev);
+	zxdh_pf_dpp_uninit(dh_dev);
+	zxdh_pf_initialized_uninit(dh_dev);
+
+	zxdh_devlink_unregister(devlink);
+	zxdh_pf_modern_cfg_uninit(dh_dev);
+	dh_pf_sriov_cap_cfg_uninit(dh_dev);
+	dh_pf_eq_table_destroy(dh_dev);
+	dh_pf_irq_table_destroy(dh_dev);
+	dh_pf_events_uninit(dh_dev);
+	dh_eq_table_cleanup(dh_dev);
+	dh_irq_table_cleanup(dh_dev);
+	dh_pf_vf_item_destroy(dh_dev, false);
+	dh_pf_pci_close(dh_dev);
+	zxdh_devlink_free(devlink);
+
+	pci_set_drvdata(pdev, NULL);
+	LOG_INFO("dh_pf_shutdown stop\n");
+}
+
+static pci_ers_result_t dh_pci_err_detected(struct pci_dev *pdev,
+											pci_channel_state_t state)
+{
+	return PCI_ERS_RESULT_NONE;
+}
+
+static pci_ers_result_t dh_pf_pci_slot_reset(struct pci_dev *pdev)
+{
+	return PCI_ERS_RESULT_NONE;
+}
+
+static void dh_pf_pci_resume(struct pci_dev *pdev)
+{
+}
+
+int32_t dh_pf_sriov_configure(struct pci_dev *pdev, int32_t num_vfs)
+{
+	struct dh_core_dev *dev = pci_get_drvdata(pdev);
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+	int32_t ret = 0;
+
+	if (dev->coredev_type != DH_COREDEV_PF) {
+		LOG_ERR("This device is not capable of SR-IOV\n");
+		return -EOPNOTSUPP;
+	}
+
+	if (num_vfs > 0) {
+		ret = dh_pf_sriov_enable(pdev, num_vfs);
+		if (ret != 0) {
+			LOG_ERR("Failed to enable sriov, num_vfs:%d\n", num_vfs);
+			return ret;
+		}
+	} else {
+		dh_pf_sriov_disable(pdev);
+	}
+
+	pf_dev->num_vfs = (uint16_t)num_vfs;
+
+	return num_vfs;
+}
+
+static const struct pci_error_handlers dh_pf_err_handler = {
+	.error_detected = dh_pci_err_detected,
+	.slot_reset = dh_pf_pci_slot_reset,
+	.resume = dh_pf_pci_resume
+};
+
+static struct pci_driver dh_pf_driver = {
+	.name = KBUILD_MODNAME,
+	.id_table = dh_pf_pci_table,
+	.probe = dh_pf_probe,
+	.remove = dh_pf_remove,
+	.suspend = dh_pf_suspend,
+	.resume = dh_pf_resume,
+	.shutdown = dh_pf_shutdown,
+	.err_handler = &dh_pf_err_handler,
+	.sriov_configure = dh_pf_sriov_configure,
+};
+
+static int32_t __init dh_pf_pci_init_module(void)
+{
+	int32_t ret = 0;
+
+	LOG_INFO("%s - version %s\n", zxdh_pf_driver_string,
+			 zxdh_pf_driver_version);
+	LOG_INFO("%s\n", zxdh_pf_copyright);
+
+	ret = pci_register_driver(&dh_pf_driver);
+	if (ret != 0) {
+		LOG_ERR("pci_register_driver failed: %d\n", ret);
+		goto err_register_driver;
+	}
+
+#ifdef CONFIG_ZXDH_SF
+	ret = zxdh_en_sf_driver_register();
+	if (ret != 0) {
+		LOG_ERR("zxdh_en_sf_driver_register failed: %d\n", ret);
+		goto err_sf_driver_register;
+	}
+#endif
+
+	ret = dh_pf_msg_recv_func_register();
+	if (ret != 0) {
+		LOG_ERR("dh_pf_msg_recv_func_register failed: %d\n", ret);
+		goto err_msg_recv_func_registe;
+	}
+
+	return 0;
+
+err_msg_recv_func_registe:
+#ifdef CONFIG_ZXDH_SF
+	zxdh_en_sf_driver_unregister();
+err_sf_driver_register:
+#endif
+	pci_unregister_driver(&dh_pf_driver);
+err_register_driver:
+	return ret;
+}
+
+static void dh_pf_pci_exit_module(void)
+{
+	LOG_INFO("%s - version %s\n", zxdh_pf_driver_string,
+			 zxdh_pf_driver_version);
+	LOG_INFO("%s\n", zxdh_pf_copyright);
+
+	dh_pf_msg_recv_func_unregister();
+
+#ifdef CONFIG_ZXDH_SF
+	zxdh_en_sf_driver_unregister();
+#endif
+
+	pci_unregister_driver(&dh_pf_driver);
+
+	return;
+}
+
+module_init(dh_pf_pci_init_module);
+module_exit(dh_pf_pci_exit_module);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf.h b/src/net/drivers/net/ethernet/dinghai/en_pf.h
index 21d10d754c7448d9d6462b2627f4f5dcaee973a2..adaed34d10e32dff65e4a2b64e475ba68f6300ad 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_pf.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_pf.h
@@ -1,179 +1,151 @@
-#ifndef __ZXDH_EN_PF_H__
-#define __ZXDH_EN_PF_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/kcompat.h>
-#include <linux/refcount.h>
-#include "plcr.h"
-#include "en_tsn/zxdh_tsn.h"
-
-/* Common configuration */
-#define ZXDH_PCI_CAP_COMMON_CFG 1
-/* Notifications */
-#define ZXDH_PCI_CAP_NOTIFY_CFG 2
-/* ISR access */
-#define ZXDH_PCI_CAP_ISR_CFG    3
-/* Device specific configuration */
-#define ZXDH_PCI_CAP_DEVICE_CFG 4
-/* PCI configuration access */
-#define ZXDH_PCI_CAP_PCI_CFG    5
-
-#define ZXDH_PF_MAX_BAR_VAL     0x5
-#define ZXDH_PF_ALIGN4          4
-#define ZXDH_PF_ALIGN2          2
-#define ZXDH_PF_MAP_MINLEN2     2
-
-#define ZXDH_DEV_MAC_LOW_OFFSET  0x40
-#define ZXDH_DEV_MAC_HIGH_OFFSET 0x44
-#define ZXDH_DEV_SPEED_OFFSET 0x4c
-#define ZXDH_DEV_DUPLEX_OFFSET 0x50
-
-#define ZXDH_CFG_NPSDK_TYPE     7
-#define ZXDH_STOP_PXE_MODE      1
-
-#define ZXDH_PANNEL_PORT_MAX    (10)
-
-#define GET_COREDEV_TYPE(pdev)     \
-    ((pdev->device == ZXDH_VF_DEVICE_ID) || (pdev->device == ZXDH_VF_E310_DEVICE_ID) || \
-    (pdev->device == ZXDH_VF_E312_DEVICE_ID) || (pdev->device == ZXDH_UPF_VF_I512_DEVICE_ID) || \
-    (pdev->device == ZXDH_INICA_RDMA_VF_DEVICE_ID) || \
-    (pdev->device == ZXDH_VF_DPUB_RDMA_DEVICE_ID)) ? \
-    DH_COREDEV_VF : DH_COREDEV_PF  \
-
-#define ZXDH_AUX_COMP_FLAG      1
-#define ZXDH_AUX_COMP_FLAG_CHECK(pf_dev) \
-    do {                                                   \
-        if (pf_dev->aux_comp_flag != ZXDH_AUX_COMP_FLAG)   \
-        {                                                  \
-            return;                          \
-        }                                                  \
-    } while (0)
-
-#define PORT_FLAGS_ALLOC_STAT      (1 << 0)
-
-
-struct dh_core_dev;
-
-struct zxdh_pf_adev {
-    struct zxdh_auxiliary_device *adev;
-    int32_t aux_idx;
-};
-
-struct zxdh_pannle_port
-{
-    uint8_t pannel_id;
-    uint8_t phyport;
-    uint8_t link_check_bit;
-    uint8_t flags;
-}  __attribute__((packed));
-
-struct zxdh_port_resource
-{
-    uint8_t pannel_num;
-    uint8_t rsv[3];
-    struct zxdh_pannle_port port[ZXDH_PANNEL_PORT_MAX];
-}  __attribute__((packed));
-
-struct zxdh_pf_device {
-    struct list_head virtqueues;
-
-    struct zxdh_pf_pci_common_cfg __iomem *common;
-    /* Device-specific data (non-legacy mode)  */
-    /* Base of vq notifications (non-legacy mode). */
-    void __iomem *device;
-    void __iomem *notify_base;
-    void __iomem *pf_sriov_cap_base;
-    /* Physical base of vq notifications */
-    resource_size_t notify_pa;
-    /* Where to read and clear interrupt */
-    uint8_t __iomem *isr;
-    /* So we can sanity-check accesses. */
-    size_t notify_len;
-    size_t device_len;
-    /* Capability for when we need to map notifications per-vq. */
-    int32_t notify_map_cap;
-    /* Multiply queue_notify_off by this value. (non-legacy mode). */
-    uint32_t notify_offset_multiplier;
-    int32_t modern_bars;
-
-    uint64_t pci_ioremap_addr[6];
-
-    uint32_t speed;
-    uint32_t autoneg_enable;
-    uint32_t supported_speed_modes;
-    uint32_t advertising_speed_modes;
-    uint8_t  duplex;
-
-    uint16_t pcie_id;
-    uint16_t slot_id;
-    uint16_t vport;
-    struct zxdh_vf_item *vf_item;
-    uint16_t num_vfs;
-    bool vepa;
-    uint8_t  phy_port;
-
-    bool link_up;
-    struct work_struct riscv_ready_work;
-    struct work_struct riscv2pf_msg_proc_work;
-    struct work_struct vf2pf_msg_proc_work;
-    struct work_struct link_info_irq_update_vf_bond_pf_work;
-    struct work_struct riscv_ext_pps_work;
-    struct work_struct riscv_local_pps_work;
-
-    uint64_t sriov_bar_size;
-
-    struct zxdh_plcr_table plcr_table;
-    struct zxdh_sriov_sysfs sriov;
-    struct zxdh_pf_adev *adevs_table;
-    int32_t adevs_num;
-
-    struct zxdh_port_resource port_resource;
-    struct zxdh_lag *ldev;
-    int32_t pannel_port_num;
-
-    uint32_t initialized_flags;
-    spinlock_t initialized_lock;
-
-    /* initialization completion flag */
-    uint8_t aux_comp_flag;
-    uint8_t bond_num;
-    struct zxdh_ptp_private *ptp;
-    struct zxdh_tsn_private *tsn;
-    struct zxdh_ipv6_mac_tbl *ip6mac_tbl;
-    spinlock_t vf_ip6mac_lock;
-};
-
-struct zxdh_ipv6_mac_entry {
-	spinlock_t lock;
-	refcount_t refcnt;
-	struct list_head list;
-	uint8_t ipv6_mac[ETH_ALEN];
-};
-
-struct zxdh_ipv6_mac_tbl {
-	unsigned int ip6mact_size;
-	rwlock_t lock;
-	struct list_head ip6mac_free_head;
-	void *ip6mac_entry_list;
-	struct list_head hash_list[];
-};
-
-#define IS_MSGQ_DEV(en_dev)  if ((en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) && \
-                                ((!en_dev->ops->is_bond(en_dev->parent)) || \
-                                (en_dev->ops->is_bond(en_dev->parent) && en_dev->ops->if_init(en_dev->parent))))
-#define NEED_MSGQ(en_dev)  if (en_dev->need_msgq)
-
-bool zxdh_pf_is_bond(struct dh_core_dev *dh_dev);
-bool zxdh_pf_is_upf(struct dh_core_dev *dh_dev);
-int32_t zxdh_pf_msg_send_cmd(struct dh_core_dev *dh_dev, uint16_t module_id, void *msg, void *ack, bool is_sync);
-struct zxdh_vf_item *zxdh_pf_get_vf_item(struct dh_core_dev *dh_dev, uint16_t vf_idx);
-int zxdh_pf_get_pannel_port_num(struct dh_core_dev *dh_dev);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef __ZXDH_EN_PF_H__
+#define __ZXDH_EN_PF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/kcompat.h>
+#include "plcr.h"
+
+/* Common configuration */
+#define ZXDH_PCI_CAP_COMMON_CFG 1
+/* Notifications */
+#define ZXDH_PCI_CAP_NOTIFY_CFG 2
+/* ISR access */
+#define ZXDH_PCI_CAP_ISR_CFG 3
+/* Device specific configuration */
+#define ZXDH_PCI_CAP_DEVICE_CFG 4
+/* PCI configuration access */
+#define ZXDH_PCI_CAP_PCI_CFG 5
+
+#define ZXDH_PF_MAX_BAR_VAL 0x5
+#define ZXDH_PF_ALIGN4 4
+#define ZXDH_PF_ALIGN2 2
+#define ZXDH_PF_MAP_MINLEN2 2
+
+#define ZXDH_DEV_MAC_LOW_OFFSET 0x40
+#define ZXDH_DEV_MAC_HIGH_OFFSET 0x44
+#define ZXDH_DEV_SPEED_OFFSET 0x4c
+#define ZXDH_DEV_DUPLEX_OFFSET 0x50
+
+#define ZXDH_CFG_NPSDK_TYPE 7
+#define ZXDH_STOP_PXE_MODE 1
+
+#define ZXDH_PANNEL_PORT_MAX (10)
+
+#define GET_COREDEV_TYPE(pdev)                    \
+	(((pdev->device == ZXDH_VF_DEVICE_ID) ||      \
+	  (pdev->device == ZXDH_VF_E310_DEVICE_ID) || \
+	  (pdev->device == ZXDH_VF_E312_DEVICE_ID)) ? \
+			   DH_COREDEV_VF :                      \
+			   DH_COREDEV_PF)
+
+#define ZXDH_AUX_COMP_FLAG 1
+#define ZXDH_AUX_COMP_FLAG_CHECK(pf_dev)                   \
+	do {                                                   \
+		if (pf_dev->aux_comp_flag != ZXDH_AUX_COMP_FLAG) { \
+			return;                                        \
+		}                                                  \
+	} while (0)
+
+#define PORT_FLAGS_ALLOC_STAT (1 << 0)
+
+struct dh_core_dev;
+
+struct zxdh_pf_adev {
+	struct auxiliary_device *adev;
+	int32_t aux_idx;
+};
+
+struct zxdh_pannle_port {
+	uint8_t pannel_id;
+	uint8_t phyport;
+	uint8_t link_check_bit;
+	uint8_t flags;
+} __attribute__((packed));
+
+struct zxdh_port_resource {
+	uint8_t pannel_num;
+	uint8_t rsv[3];
+	struct zxdh_pannle_port port[ZXDH_PANNEL_PORT_MAX];
+} __attribute__((packed));
+
+struct zxdh_pf_device {
+	struct list_head virtqueues;
+
+	struct zxdh_pf_pci_common_cfg __iomem *common;
+	/* Device-specific data (non-legacy mode)  */
+	/* Base of vq notifications (non-legacy mode). */
+	void __iomem *device;
+	void __iomem *notify_base;
+	void __iomem *pf_sriov_cap_base;
+	/* Physical base of vq notifications */
+	resource_size_t notify_pa;
+	/* Where to read and clear interrupt */
+	uint8_t __iomem *isr;
+	/* So we can sanity-check accesses. */
+	size_t notify_len;
+	size_t device_len;
+	/* Capability for when we need to map notifications per-vq. */
+	int32_t notify_map_cap;
+	/* Multiply queue_notify_off by this value. (non-legacy mode). */
+	uint32_t notify_offset_multiplier;
+	int32_t modern_bars;
+
+	uint64_t pci_ioremap_addr[6];
+
+	uint32_t speed;
+	uint32_t autoneg_enable;
+	uint32_t supported_speed_modes;
+	uint32_t advertising_speed_modes;
+	uint8_t duplex;
+
+	uint16_t pcie_id;
+	uint16_t slot_id;
+	uint16_t vport;
+	struct zxdh_vf_item *vf_item;
+	uint16_t num_vfs;
+	bool vepa;
+	uint8_t phy_port;
+
+	bool link_up;
+	struct work_struct riscv_ready_work;
+	struct work_struct riscv2pf_msg_proc_work;
+	struct work_struct vf2pf_msg_proc_work;
+	struct work_struct link_info_irq_update_vf_bond_pf_work;
+	struct work_struct riscv_ext_pps_work;
+	struct work_struct riscv_local_pps_work;
+
+	uint64_t sriov_bar_size;
+
+	struct zxdh_plcr_table plcr_table;
+	struct zxdh_sriov_sysfs sriov;
+	struct zxdh_pf_adev *adevs_table;
+	int32_t adevs_num;
+
+	struct zxdh_port_resource port_resource;
+	struct zxdh_lag *ldev;
+	int32_t pannel_port_num;
+
+	uint32_t initialized_flags;
+	spinlock_t initialized_lock;
+
+	/* initialization completion flag */
+	uint8_t aux_comp_flag;
+	uint8_t bond_num;
+	struct zxdh_ptp_private *ptp;
+};
+
+bool zxdh_pf_is_bond(struct dh_core_dev *dh_dev);
+int32_t zxdh_pf_msg_send_cmd(struct dh_core_dev *dh_dev, uint16_t module_id,
+							 void *msg, void *ack, bool is_sync);
+struct zxdh_vf_item *zxdh_pf_get_vf_item(struct dh_core_dev *dh_dev,
+										 uint16_t vf_idx);
+int zxdh_pf_get_pannel_port_num(struct dh_core_dev *dh_dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/devlink.c b/src/net/drivers/net/ethernet/dinghai/en_pf/devlink.c
old mode 100755
new mode 100644
index 48754242f5960b5f01aec998d87bffadf592dfb0..e202c3c3a60b4b8bb9168e6eb9de8c35bc47e25b
--- a/src/net/drivers/net/ethernet/dinghai/en_pf/devlink.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_pf/devlink.c
@@ -1,132 +1,124 @@
-#include <linux/dinghai/driver.h>
-#include <net/devlink.h>
-#include "devlink.h"
-
-
-struct devlink_ops dh_pf_devlink_ops = {
-
-};
-
-enum {
-    DH_PF_PARAMS_MAX,
-};
-
-static int32_t __attribute__((unused)) sample_check(struct dh_core_dev *dev)
-{
-    return 1;
-}
-
-enum dh_pf_devlink_param_id {
-    DH_PF_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
-    DH_PF_DEVLINK_PARAM_ID_SAMPLE,
-};
-
-
-static int32_t dh_devlink_sample_set(struct devlink *devlink, uint32_t id,
-                              struct devlink_param_gset_ctx *ctx)
-{
-    struct dh_core_dev * __attribute__((unused)) dev = devlink_priv(devlink);
-
-    return 0;
-}
-
-static int32_t dh_devlink_sample_get(struct devlink *devlink, uint32_t id,
-                              struct devlink_param_gset_ctx *ctx)
-{
-    struct dh_core_dev * __attribute__((unused)) dev = devlink_priv(devlink);
-
-    return 0;
-}
-
-#ifdef HAVE_DEVLINK_PARAM_REGISTER
-static const struct devlink_params {
-    const char *name;
-    int32_t (*check)(struct dh_core_dev *dev);
-    struct devlink_param param;
-} devlink_params[] = {
-    [DH_PF_PARAMS_MAX] = { .name = "sample",
-                           .check = &sample_check,
-                           .param = DEVLINK_PARAM_DRIVER(DH_PF_DEVLINK_PARAM_ID_SAMPLE,
-                                                          "sample", DEVLINK_PARAM_TYPE_BOOL,
-                                                          BIT(DEVLINK_PARAM_CMODE_RUNTIME),dh_devlink_sample_get,
-                                                          dh_devlink_sample_set,
-                                                          NULL),
-                          }
-};
-
-static int32_t params_register(struct devlink *devlink)
-{
-    int32_t i = 0;
-    int32_t err = 0;
-    struct dh_core_dev *dh_dev = devlink_priv(devlink);
-
-    for (i = 0; i < ARRAY_SIZE(devlink_params); i++)
-    {
-        if(devlink_params[i].check(dh_dev))
-        {
-            err = devlink_param_register(devlink, &devlink_params[i].param);
-            if (err)
-            {
-               goto rollback;
-            }
-        }
-    }
-
-    return 0;
-
-rollback:
-    if (i == 0)
-    {
-        return err;
-    }
-
-    for (; i > 0; i--)
-    {
-        devlink_param_unregister(devlink, &devlink_params[i].param);
-    }
-
-    return err;
-}
-
-static int32_t params_unregister(struct devlink *devlink)
-{
-    int32_t i = 0;
-
-    for (i = 0; i < ARRAY_SIZE(devlink_params); i++)
-    {
-        devlink_param_unregister(devlink, &devlink_params[i].param);
-    }
-
-    return 0;
-}
-#else 
-static struct devlink_param devlink_params [] = {
-    [DH_PF_PARAMS_MAX] = DEVLINK_PARAM_DRIVER(DH_PF_DEVLINK_PARAM_ID_SAMPLE,
-                                                          "sample", DEVLINK_PARAM_TYPE_BOOL,
-                                                          BIT(DEVLINK_PARAM_CMODE_RUNTIME),dh_devlink_sample_get,
-                                                          dh_devlink_sample_set,
-                                                          NULL),
-};
-
-static int32_t params_register(struct devlink *devlink)
-{
-    struct dh_core_dev * __attribute__((unused)) dh_dev = devlink_priv(devlink);
-    int32_t err = 0;
-
-    err = devlink_params_register(devlink, devlink_params, ARRAY_SIZE(devlink_params));
-
-    return err;
-}
-static int32_t params_unregister(struct devlink *devlink)
-{
-    devlink_params_unregister(devlink, devlink_params, ARRAY_SIZE(devlink_params));
-
-    return 0;
-}
-#endif
-
-struct dh_core_devlink_ops dh_pf_core_devlink_ops = {
-    .params_register   =  params_register,
-    .params_unregister =  params_unregister
-};
-
+#include <linux/dinghai/driver.h>
+#include <net/devlink.h>
+#include "devlink.h"
+
+struct devlink_ops dh_pf_devlink_ops = {
+
+};
+
+enum {
+	DH_PF_PARAMS_MAX,
+};
+
+static int32_t __attribute__((unused)) sample_check(struct dh_core_dev *dev)
+{
+	return 1;
+}
+
+enum dh_pf_devlink_param_id {
+	DH_PF_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
+	DH_PF_DEVLINK_PARAM_ID_SAMPLE,
+};
+
+static int32_t dh_devlink_sample_set(struct devlink *devlink, uint32_t id,
+									 struct devlink_param_gset_ctx *ctx)
+{
+	struct dh_core_dev *__attribute__((unused)) dev = devlink_priv(devlink);
+
+	return 0;
+}
+
+static int32_t dh_devlink_sample_get(struct devlink *devlink, uint32_t id,
+									 struct devlink_param_gset_ctx *ctx)
+{
+	struct dh_core_dev *__attribute__((unused)) dev = devlink_priv(devlink);
+
+	return 0;
+}
+
+#ifdef HAVE_DEVLINK_PARAM_REGISTER
+static const struct devlink_params {
+	const char *name;
+	int32_t (*check)(struct dh_core_dev *dev);
+	struct devlink_param param;
+} devlink_params[] = { [DH_PF_PARAMS_MAX] = {
+							   .name = "sample",
+							   .check = &sample_check,
+							   .param = DEVLINK_PARAM_DRIVER(
+									   DH_PF_DEVLINK_PARAM_ID_SAMPLE, "sample",
+									   DEVLINK_PARAM_TYPE_BOOL,
+									   BIT(DEVLINK_PARAM_CMODE_RUNTIME),
+									   dh_devlink_sample_get,
+									   dh_devlink_sample_set, NULL),
+					   } };
+
+static int32_t params_register(struct devlink *devlink)
+{
+	int32_t i = 0;
+	int32_t err = 0;
+	struct dh_core_dev *dh_dev = devlink_priv(devlink);
+
+	for (i = 0; i < ARRAY_SIZE(devlink_params); i++) {
+		if (devlink_params[i].check(dh_dev)) {
+			err = devlink_param_register(devlink, &devlink_params[i].param);
+			if (err) {
+				goto rollback;
+			}
+		}
+	}
+
+	return 0;
+
+rollback:
+	if (i == 0) {
+		return err;
+	}
+
+	for (; i > 0; i--) {
+		devlink_param_unregister(devlink, &devlink_params[i].param);
+	}
+
+	return err;
+}
+
+static int32_t params_unregister(struct devlink *devlink)
+{
+	int32_t i = 0;
+
+	for (i = 0; i < ARRAY_SIZE(devlink_params); i++) {
+		devlink_param_unregister(devlink, &devlink_params[i].param);
+	}
+
+	return 0;
+}
+#else
+static struct devlink_param devlink_params[] = {
+	[DH_PF_PARAMS_MAX] = DEVLINK_PARAM_DRIVER(
+			DH_PF_DEVLINK_PARAM_ID_SAMPLE, "sample", DEVLINK_PARAM_TYPE_BOOL,
+			BIT(DEVLINK_PARAM_CMODE_RUNTIME), dh_devlink_sample_get,
+			dh_devlink_sample_set, NULL),
+};
+
+static int32_t params_register(struct devlink *devlink)
+{
+	struct dh_core_dev *__attribute__((unused)) dh_dev = devlink_priv(devlink);
+	int32_t err = 0;
+
+	err = devlink_params_register(devlink, devlink_params,
+								  ARRAY_SIZE(devlink_params));
+
+	return err;
+}
+static int32_t params_unregister(struct devlink *devlink)
+{
+	devlink_params_unregister(devlink, devlink_params,
+							  ARRAY_SIZE(devlink_params));
+
+	return 0;
+}
+#endif
+
+struct dh_core_devlink_ops dh_pf_core_devlink_ops = {
+	.params_register = params_register,
+	.params_unregister = params_unregister
+};
diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/devlink.h b/src/net/drivers/net/ethernet/dinghai/en_pf/devlink.h
old mode 100755
new mode 100644
index 116d09de2f6b671b52e959a7fc50d9365e675448..31214ab3f0165eb86316adbf0a7180339867406b
--- a/src/net/drivers/net/ethernet/dinghai/en_pf/devlink.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_pf/devlink.h
@@ -1,16 +1,14 @@
-#ifndef __ZXDH_DEVLINK_H__
-#define __ZXDH_DEVLINK_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/devlink.h>
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef __ZXDH_DEVLINK_H__
+#define __ZXDH_DEVLINK_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/devlink.h>
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/en_rep.c b/src/net/drivers/net/ethernet/dinghai/en_pf/en_rep.c
old mode 100755
new mode 100644
diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/eq.c b/src/net/drivers/net/ethernet/dinghai/en_pf/eq.c
old mode 100755
new mode 100644
index ae2e6d1db216a65ed5a63036cc0d0c2bfbce5014..8b478412058e6e54fb36feba1b25a77374606929
--- a/src/net/drivers/net/ethernet/dinghai/en_pf/eq.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_pf/eq.c
@@ -1,455 +1,441 @@
-#include <linux/dinghai/eq.h>
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/helper.h>
-#include <linux/dinghai/dh_cmd.h>
-#include <linux/list.h>
-#include "irq.h"
-#include "eq.h"
-#include "../en_pf.h"
-
-extern irqreturn_t msix_extern_pps_irq_from_risc_handler(struct zxdh_pf_device *dev);
-extern irqreturn_t msix_local_pps_irq_from_risc_handler(struct zxdh_pf_device *dev);
-static int32_t create_async_eqs(struct dh_core_dev *dev);
-
-
-int32_t dh_pf_eq_table_init(struct dh_core_dev *dev)
-{
-    struct dh_pf_eq_table *table_priv = NULL;
-
-    table_priv = kvzalloc(sizeof(*table_priv), GFP_KERNEL);
-    if (unlikely(table_priv == NULL))
-    {
-        LOG_ERR("dh_pf_eq_table kvzalloc failed\n");
-        return -ENOMEM;
-    }
-
-    dh_eq_table_init(dev, table_priv);
-
-    return 0;
-}
-
-uint16_t zxdh_pf_get_vqs_channels_num(struct dh_core_dev *dh_dev)
-{
-    if ((dh_dev->pdev->device == ZXDH_INICA_BOND_DEVICE_ID)
-        || (dh_dev->pdev->device == ZXDH_INICB_BOND_DEVICE_ID)
-        || (dh_dev->pdev->device == ZXDH_INICA_UPF_BOND_DEVICE_ID)
-        || (dh_dev->pdev->device == ZXDH_DPUA_BOND_DEVICE_ID))
-    {
-        return ZXDH_BOND_VQS_CHANNELS_NUM;
-    }
-
-    return ZXDH_VQS_CHANNELS_NUM;
-}
-
-void zxdh_pf_switch_irq(struct dh_core_dev *dh_dev, int32_t i, int32_t op)
-{
-    if (op)
-    {
-        enable_irq(i);
-        return;
-    }
-
-    disable_irq(i);
-    return;
-}
-
-int32_t zxdh_pf_vq_irqs_request(struct dh_core_dev *dh_dev, struct dh_irq **vq_irqs, int32_t vq_channels)
-{
-    struct dh_irq_table *irq_table = &dh_dev->irq_table;
-    struct dh_pf_irq_table *pf_irq_table = irq_table->priv;
-    int32_t ret = 0;
-    int32_t vqs_irq_num = vq_channels;
-
-    ret = dh_irq_affinity_irqs_request_auto(pf_irq_table->pf_vq_pool, vq_irqs, vqs_irq_num);
-    if (ret < vqs_irq_num)
-    {
-        LOG_ERR("the actual obtain irq_num %d < need request irq_num %d\n", ret, vqs_irq_num);
-        return -1;
-    }
-
-    return ret;
-}
-
-void zxdh_pf_affinity_irqs_release(struct dh_core_dev *dh_dev, struct dh_irq **vq_irqs, int32_t num_irqs)
-{
-    struct dh_irq_table *irq_table = &dh_dev->irq_table;
-    struct dh_pf_irq_table *pf_irq_table = irq_table->priv;
-
-    dh_irq_affinity_irqs_release(pf_irq_table->pf_vq_pool, vq_irqs, num_irqs);
-}
-
-static int32_t destroy_async_eq(struct dh_core_dev *dev)
-{
-    struct dh_eq_table *eq_table = &dev->eq_table;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-    struct msix_para in = {0};
-    int32_t err = 0;
-
-    in.vector_risc = ZXDH_PF_INVALID_MSIX_VEC;
-    in.vector_pfvf = ZXDH_PF_INVALID_MSIX_VEC;
-    in.vector_mpf = ZXDH_PF_INVALID_MSIX_VEC;
-    in.driver_type = MSG_CHAN_END_PF;
-    in.pdev = dev->pdev;
-    in.virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET;
-    in.pcie_id = pf_dev->pcie_id;
-
-    mutex_lock(&eq_table->lock);
-
-    err = zxdh_bar_enable_chan(&in, &pf_dev->vport);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_bar_disable_chan failed\n");
-    }
-
-    mutex_unlock(&eq_table->lock);
-
-    return err;
-}
-
-int32_t dh_pf_eq_table_create(struct dh_core_dev *dev)
-{
-    int32_t err = 0;
-
-    err = create_async_eqs(dev);
-    if (err != 0)
-    {
-        LOG_ERR("Failed to create async EQs: %d\n", err);
-        return err;
-    }
-
-    return 0;
-}
-
-/*create eventq*/
-static int32_t create_async_eq(struct dh_core_dev *dev, struct dh_irq *riscv, struct dh_irq *pf)
-{
-    struct dh_eq_table *eq_table = &dev->eq_table;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-    struct msix_para in = {0};
-    int ret = 0;
-
-    in.vector_risc = riscv->index;
-    in.vector_pfvf = pf->index;
-    in.vector_mpf = ZXDH_PF_INVALID_MSIX_VEC;
-    in.driver_type = MSG_CHAN_END_PF;
-    in.pdev = dev->pdev;
-    in.virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET;
-    in.pcie_id = pf_dev->pcie_id;
-
-    mutex_lock(&eq_table->lock);
-
-    LOG_DEBUG("msix vector riscv: %d, pfvf: %d\n", riscv->index, pf->index);
-    ret = zxdh_bar_enable_chan(&in, &pf_dev->vport);
-
-    mutex_unlock(&eq_table->lock);
-
-    return ret;
-}
-
-static int32_t dh_eq_async_riscv_int(struct notifier_block *nb, unsigned long action, void *data)
-{
-    struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-    struct dh_eq_table *eq_table = &dev->eq_table;
-    struct dh_events *events = dev->events;
-    struct dh_event_nb *event_nb = NULL;
-    uint64_t virt_addr = 0;
-    int32_t event_type = 0;
-    uint16_t event_idx = 0;
-    uint16_t i = 0;
-    uint8_t src = MSG_CHAN_END_RISC;
-    uint8_t dst = MSG_CHAN_END_VF;
-
-    if(dev->coredev_type == DH_COREDEV_PF)
-    {
-        dst = MSG_CHAN_END_PF;
-    }
-
-    virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET;
-    event_idx = zxdh_get_event_id(virt_addr, src, dst);
-    event_type = dh_eq_event_type_get(event_idx);
-    LOG_INFO("------------- event_idx: %d, event_type: %d------------\n", event_idx, event_type);
-
-    if(events == NULL)
-    {
-        LOG_ERR("riscv_irq trigger, events is null\n");
-        return 0;
-    }
-
-    for (i = 0; i < events->evt_num; i++)
-    {
-        event_nb = &events->notifiers[i];
-        if (event_type == event_nb->nb.event_type)
-        {
-            LOG_INFO("en_pf async riscv irq_handler called\n");
-            atomic_notifier_call_chain(&eq_table->nh[event_type], event_type, NULL);
-            return 0;
-        }
-    }
-
-    return 0;
-}
-
-static int32_t dh_eq_async_pf_int(struct notifier_block *nb, unsigned long action, void *data)
-{
-    struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-    struct dh_eq_table *eq_table = &dev->eq_table;
-    struct dh_events *events = dev->events;
-    struct dh_event_nb *event_nb = NULL;
-    uint64_t virt_addr = 0;
-    int32_t event_type = 0;
-    uint16_t event_idx = 0;
-    uint16_t i = 0;
-
-    if(dev->coredev_type == DH_COREDEV_VF)
-    {
-        return 0;
-    }
-
-    virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET + ZXDH_BAR_PFVF_MSG_OFFSET;
-    event_idx = zxdh_get_event_id(virt_addr, MSG_CHAN_END_VF, MSG_CHAN_END_PF);
-    event_type = dh_eq_event_type_get(event_idx);
-    LOG_INFO("------------- event_idx: %d, event_type: %d------------\n", event_idx, event_type);
-
-    for (i = 0; i < events->evt_num; i++)
-    {
-        event_nb = &events->notifiers[i];
-
-        if (event_type == event_nb->nb.event_type)
-        {
-            LOG_INFO("en_pf async pf/vf irq_handler called\n");
-            atomic_notifier_call_chain(&eq_table->nh[event_type], event_type, NULL);
-            return 0;
-        }
-    }
-
-    return 0;
-}
-
-static int32_t dh_eq_async_link_info_int_bond_pf(struct notifier_block *nb, unsigned long action, void *data)
-{
-    struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-
-    if(!zxdh_pf_is_bond(dev))
-    {
-        LOG_INFO("isn't bond_pf exit\n");
-        return 0;
-    }
-
-    zxdh_events_work_enqueue(dev, &pf_dev->link_info_irq_update_vf_bond_pf_work);
-    return 0;
-}
-
-static int32_t dh_eq_async_extpps_int(struct notifier_block *nb, unsigned long action, void *data)
-{
-    struct dh_eq_async *eq_pps_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct dh_core_dev *dev = (struct dh_core_dev *)eq_pps_async->priv;
-    struct dh_eq_table *eq_table = &dev->eq_table;
-
-    atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_RISC_EXT_PPS], DH_EVENT_TYPE_NOTIFY_RISC_EXT_PPS, NULL);
-    return 0;
-}
-
-static int32_t dh_eq_async_local_pps_int(struct notifier_block *nb, unsigned long action, void *data)
-{
-    struct dh_eq_async *eq_pps_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct dh_core_dev *dev = (struct dh_core_dev *)eq_pps_async->priv;
-    struct dh_eq_table *eq_table = &dev->eq_table;
-
-    atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_RISC_LOCAL_PPS], DH_EVENT_TYPE_NOTIFY_RISC_LOCAL_PPS, NULL);
-    return 0;
-}
-
-static struct dh_pf_async_irq_table dh_pf_async_irq_tbl[] =
-{
-    {"link_info", dh_eq_async_link_info_int_bond_pf},
-    {"riscv", dh_eq_async_riscv_int},
-    {"pf", dh_eq_async_pf_int},
-    {"expps", dh_eq_async_extpps_int},
-    {"localpps", dh_eq_async_local_pps_int},
-};
-
-static void cleanup_async_eq(struct dh_core_dev *dev, struct dh_eq_async *eq, const char *name)
-{
-    dh_eq_disable(dev, &eq->core, &eq->irq_nb);
-}
-
-static void destroy_async_eqs(struct dh_core_dev *dev)
-{
-    struct dh_eq_table *table = &dev->eq_table;
-    struct dh_pf_eq_table *table_priv = table->priv;
-    int32_t tbl_size = ARRAY_SIZE(dh_pf_async_irq_tbl);
-    int32_t i = 0;
-
-    for (i = 0; i < tbl_size; ++i)
-    {
-        cleanup_async_eq(dev, &table_priv->async_eq_tbl[i], dh_pf_async_irq_tbl[i].name);
-    }
-    destroy_async_eq(dev);
-    dh_irqs_release_vectors(table_priv->async_irq_tbl, tbl_size);
-}
-
-void dh_pf_eq_table_destroy(struct dh_core_dev *dev)
-{
-    destroy_async_eqs(dev);
-}
-
-static int32_t create_async_eqs(struct dh_core_dev *dev)
-{
-    struct dh_eq_table *table = &dev->eq_table;
-    struct dh_pf_eq_table *table_priv = table->priv;
-    struct dh_eq_param param = {};
-    int32_t err = 0;
-    int32_t tbl_size = ARRAY_SIZE(dh_pf_async_irq_tbl);
-    int32_t i = 0;
-    int32_t j = 0;
-    int32_t k = 0;
-
-    for (i = 0; i < tbl_size ; ++i)
-    {
-        table_priv->async_irq_tbl[i] = dh_pf_async_irq_request(dev);
-        if (IS_ERR(table_priv->async_irq_tbl[i]))
-        {
-            err = PTR_ERR(table_priv->async_irq_tbl[i]);
-            LOG_ERR("Failed to get async_irq_tbl[%d]\n", i);
-            goto err_async_irq_request;
-        }
-    }
-
-    err = create_async_eq(dev, table_priv->async_irq_tbl[1], table_priv->async_irq_tbl[2]);
-    if (err != 0)
-    {
-        LOG_ERR("Failed to create async_eq\n");
-        goto err_async_irq_request;
-    }
-
-    param.nent = 10;
-    param.event_type = DH_EVENT_QUEUE_TYPE_RISCV;
-    for (j = 0; j < tbl_size; ++j)
-    {
-        param.irq = table_priv->async_irq_tbl[j],
-        err = setup_async_eq(dev, &table_priv->async_eq_tbl[j], &param,\
-                dh_pf_async_irq_tbl[j].async_int, dh_pf_async_irq_tbl[j].name,\
-                dev);
-        if (err != 0)
-        {
-            LOG_ERR("Failed to setup async_eq_tbl[%d]\n", j);
-            goto err_setup_async_eq;
-        }
-    }
-
-    return 0;
-
-err_setup_async_eq:
-    for (k = 0; k < j; ++k)
-    {
-        cleanup_async_eq(dev, &table_priv->async_eq_tbl[j], dh_pf_async_irq_tbl[j].name);
-    }
-    destroy_async_eq(dev);
-err_async_irq_request:
-    dh_irqs_release_vectors(table_priv->async_irq_tbl, i);
-    return err;
-}
-
-int32_t zxdh_pf_async_eq_enable(struct dh_core_dev *dh_dev, \
-                    struct dh_eq_async *eq, const char *name, bool attach)
-{
-    struct dh_eq_table *table = &dh_dev->eq_table;
-    struct dh_pf_eq_table *table_priv = table->priv;
-    int32_t err = 0;
-    int32_t tbl_size = ARRAY_SIZE(dh_pf_async_irq_tbl);
-    int32_t i = 0;
-
-    for (i = 0; i < tbl_size; ++i)
-    {
-        if(strcmp(dh_pf_async_irq_tbl[i].name, name) == 0)
-        {
-            eq->core.irq = table_priv->async_irq_tbl[i];
-            break;
-        }
-    }
-
-    if (i == tbl_size)
-    {
-        LOG_ERR("failed to find %s irq\n", name);
-        return -1;
-    }
-
-    LOG_DEBUG("%s attach[%d] irq[%d]\n", name, attach, eq->core.irq->index);
-    if (attach)
-    {
-        err = dh_eq_enable(dh_dev, &eq->core, &eq->irq_nb);
-        if (err != 0)
-        {
-            LOG_WARN("failed to enable EQ %d\n", err);
-        }
-    }
-    else
-    {
-        dh_eq_disable(dh_dev, &eq->core, &eq->irq_nb);
-    }
-
-    return err;
-}
-
-void zxdh_pf_get_link_info_from_vqm(struct dh_core_dev *dh_dev, uint8_t *link_up)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    uint32_t dev_link_up = 0;
-
-    dev_link_up = ioread32((void __iomem *)(pf_dev->pci_ioremap_addr[0] + ZXDH_DEV_MAC_HIGH_OFFSET));
-    *link_up = (dev_link_up >> 16) & 0xff;
-
-    LOG_INFO("dev pcieid:0x%x ******** link_up: %d ********\n", pf_dev->pcie_id, *link_up);
-    return;
-}
-
-void zxdh_pf_set_vf_link_info(struct dh_core_dev *dh_dev, uint16_t vf_idx, uint8_t link_up)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    uint32_t dev_link_up = 0;
-
-    dev_link_up = ioread32((void __iomem *)(pf_dev->pf_sriov_cap_base + (pf_dev->sriov_bar_size) * vf_idx + ZXDH_DEV_MAC_HIGH_OFFSET));
-    dev_link_up = (dev_link_up & ~(0xFF << 16)) | ((uint32_t)(link_up) << 16);
-    iowrite32(dev_link_up, (void __iomem *)(pf_dev->pf_sriov_cap_base + (pf_dev->sriov_bar_size) * vf_idx + ZXDH_DEV_MAC_HIGH_OFFSET));
-
-    return;
-}
-
-void zxdh_pf_set_pf_phy_port(struct dh_core_dev *dh_dev, uint8_t phy_port)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    pf_dev->phy_port = phy_port;
-    if (dh_dev->coredev_type == DH_COREDEV_PF)
-    {
-        if (pf_dev->tsn == NULL)
-        {
-            LOG_ERR("pf_dev->tsn is null\n");
-            return;
-        }
-        pf_dev->tsn->phy_port_id = phy_port;
-    }
-}
-
-uint8_t zxdh_pf_get_pf_phy_port(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    return pf_dev->phy_port;
-}
-
-void zxdh_pf_set_pf_link_up(struct dh_core_dev *dh_dev, bool link_up)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    pf_dev->link_up = link_up;
-}
-
-bool zxdh_pf_get_pf_link_up(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    return pf_dev->link_up;
-}
+#include <linux/dinghai/eq.h>
+#include <linux/dinghai/driver.h>
+#include <linux/dinghai/helper.h>
+#include <linux/dinghai/dh_cmd.h>
+#include <linux/list.h>
+#include "irq.h"
+#include "eq.h"
+#include "../en_pf.h"
+
+extern irqreturn_t
+msix_extern_pps_irq_from_risc_handler(struct zxdh_pf_device *dev);
+extern irqreturn_t
+msix_local_pps_irq_from_risc_handler(struct zxdh_pf_device *dev);
+static int32_t create_async_eqs(struct dh_core_dev *dev);
+
+int32_t dh_pf_eq_table_init(struct dh_core_dev *dev)
+{
+	struct dh_pf_eq_table *table_priv = NULL;
+
+	table_priv = kvzalloc(sizeof(*table_priv), GFP_KERNEL);
+	if (unlikely(table_priv == NULL)) {
+		LOG_ERR("dh_pf_eq_table kvzalloc failed\n");
+		return -ENOMEM;
+	}
+
+	dh_eq_table_init(dev, table_priv);
+
+	return 0;
+}
+
+uint16_t zxdh_pf_get_vqs_channels_num(struct dh_core_dev *dh_dev)
+{
+	if ((dh_dev->pdev->device == ZXDH_INICA_BOND_DEVICE_ID) ||
+		(dh_dev->pdev->device == ZXDH_INICB_BOND_DEVICE_ID) ||
+		(dh_dev->pdev->device == ZXDH_DPUA_BOND_DEVICE_ID)) {
+		return ZXDH_BOND_VQS_CHANNELS_NUM;
+	}
+
+	return ZXDH_VQS_CHANNELS_NUM;
+}
+
+void zxdh_pf_switch_irq(struct dh_core_dev *dh_dev, int32_t i, int32_t op)
+{
+	if (op) {
+		enable_irq(i);
+		return;
+	}
+
+	disable_irq(i);
+	return;
+}
+
+int32_t zxdh_pf_vq_irqs_request(struct dh_core_dev *dh_dev,
+								struct dh_irq **vq_irqs, int32_t vq_channels)
+{
+	struct dh_irq_table *irq_table = &dh_dev->irq_table;
+	struct dh_pf_irq_table *pf_irq_table = irq_table->priv;
+	int32_t ret = 0;
+	int32_t vqs_irq_num = vq_channels;
+
+	ret = dh_irq_affinity_irqs_request_auto(pf_irq_table->pf_vq_pool, vq_irqs,
+											vqs_irq_num);
+	if (ret < vqs_irq_num) {
+		LOG_ERR("the actual obtain irq_num %d < need request irq_num %d\n", ret,
+				vqs_irq_num);
+		return -1;
+	}
+
+	return ret;
+}
+
+void zxdh_pf_affinity_irqs_release(struct dh_core_dev *dh_dev,
+								   struct dh_irq **vq_irqs, int32_t num_irqs)
+{
+	struct dh_irq_table *irq_table = &dh_dev->irq_table;
+	struct dh_pf_irq_table *pf_irq_table = irq_table->priv;
+
+	dh_irq_affinity_irqs_release(pf_irq_table->pf_vq_pool, vq_irqs, num_irqs);
+}
+
+static int32_t destroy_async_eq(struct dh_core_dev *dev)
+{
+	struct dh_eq_table *eq_table = &dev->eq_table;
+	int32_t err = 0;
+
+	mutex_lock(&eq_table->lock);
+
+	/*unmap inform device*/
+	mutex_unlock(&eq_table->lock);
+
+	return err;
+}
+
+int32_t dh_pf_eq_table_create(struct dh_core_dev *dev)
+{
+	int32_t err = 0;
+
+	err = create_async_eqs(dev);
+	if (err != 0) {
+		LOG_ERR("Failed to create async EQs: %d\n", err);
+		return err;
+	}
+
+	return 0;
+}
+
+/*create eventq*/
+static int32_t create_async_eq(struct dh_core_dev *dev, struct dh_irq *riscv,
+							   struct dh_irq *pf)
+{
+	struct dh_eq_table *eq_table = &dev->eq_table;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+	struct msix_para in = { 0 };
+	int ret = 0;
+
+	in.vector_risc = riscv->index;
+	in.vector_pfvf = pf->index;
+	in.vector_mpf = 0xff;
+	in.driver_type = MSG_CHAN_END_PF;
+	in.pdev = dev->pdev;
+	in.virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET;
+	in.pcie_id = pf_dev->pcie_id;
+
+	mutex_lock(&eq_table->lock);
+
+	LOG_DEBUG("msix vector riscv: %d, pfvf: %d\n", riscv->index, pf->index);
+	ret = zxdh_bar_enable_chan(&in, &pf_dev->vport);
+
+	mutex_unlock(&eq_table->lock);
+
+	return ret;
+}
+
+static int32_t dh_eq_async_riscv_int(struct notifier_block *nb,
+									 unsigned long action, void *data)
+{
+	struct dh_eq_async *eq_riscv_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+	struct dh_eq_table *eq_table = &dev->eq_table;
+	struct dh_events *events = dev->events;
+	struct dh_event_nb *event_nb = NULL;
+	uint64_t virt_addr = 0;
+	int32_t event_type = 0;
+	uint16_t event_idx = 0;
+	uint16_t i = 0;
+	uint8_t src = MSG_CHAN_END_RISC;
+	uint8_t dst = MSG_CHAN_END_VF;
+
+	if (dev->coredev_type == DH_COREDEV_PF) {
+		dst = MSG_CHAN_END_PF;
+	}
+
+	virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET;
+	event_idx = zxdh_get_event_id(virt_addr, src, dst);
+	event_type = dh_eq_event_type_get(event_idx);
+	LOG_INFO("------------- event_idx: %d, event_type: %d------------\n",
+			 event_idx, event_type);
+
+	if (events == NULL) {
+		LOG_ERR("riscv_irq trigger, events is null\n");
+		return 0;
+	}
+
+	for (i = 0; i < events->evt_num; i++) {
+		event_nb = &events->notifiers[i];
+		if (event_type == event_nb->nb.event_type) {
+			LOG_INFO("en_pf async riscv irq_handler called\n");
+			atomic_notifier_call_chain(&eq_table->nh[event_type], event_type,
+									   NULL);
+			return 0;
+		}
+	}
+
+	return 0;
+}
+
+static int32_t dh_eq_async_pf_int(struct notifier_block *nb,
+								  unsigned long action, void *data)
+{
+	struct dh_eq_async *eq_riscv_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+	struct dh_eq_table *eq_table = &dev->eq_table;
+	struct dh_events *events = dev->events;
+	struct dh_event_nb *event_nb = NULL;
+	uint64_t virt_addr = 0;
+	int32_t event_type = 0;
+	uint16_t event_idx = 0;
+	uint16_t i = 0;
+
+	if (dev->coredev_type == DH_COREDEV_VF) {
+		return 0;
+	}
+
+	virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET +
+				ZXDH_BAR_PFVF_MSG_OFFSET;
+	event_idx = zxdh_get_event_id(virt_addr, MSG_CHAN_END_VF, MSG_CHAN_END_PF);
+	event_type = dh_eq_event_type_get(event_idx);
+	LOG_INFO("------------- event_idx: %d, event_type: %d------------\n",
+			 event_idx, event_type);
+
+	for (i = 0; i < events->evt_num; i++) {
+		event_nb = &events->notifiers[i];
+
+		if (event_type == event_nb->nb.event_type) {
+			LOG_INFO("en_pf async pf/vf irq_handler called\n");
+			atomic_notifier_call_chain(&eq_table->nh[event_type], event_type,
+									   NULL);
+			return 0;
+		}
+	}
+
+	return 0;
+}
+
+static int32_t dh_eq_async_link_info_int_bond_pf(struct notifier_block *nb,
+												 unsigned long action,
+												 void *data)
+{
+	struct dh_eq_async *eq_riscv_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+
+	if (!zxdh_pf_is_bond(dev)) {
+		LOG_INFO("isn't bond_pf exit\n");
+		return 0;
+	}
+
+	zxdh_events_work_enqueue(dev,
+							 &pf_dev->link_info_irq_update_vf_bond_pf_work);
+	return 0;
+}
+
+static int32_t dh_eq_async_extpps_int(struct notifier_block *nb,
+									  unsigned long action, void *data)
+{
+	struct dh_eq_async *eq_pps_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct dh_core_dev *dev = (struct dh_core_dev *)eq_pps_async->priv;
+	struct dh_eq_table *eq_table = &dev->eq_table;
+
+	atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_RISC_EXT_PPS],
+							   DH_EVENT_TYPE_NOTIFY_RISC_EXT_PPS, NULL);
+	return 0;
+}
+
+static int32_t dh_eq_async_local_pps_int(struct notifier_block *nb,
+										 unsigned long action, void *data)
+{
+	struct dh_eq_async *eq_pps_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct dh_core_dev *dev = (struct dh_core_dev *)eq_pps_async->priv;
+	struct dh_eq_table *eq_table = &dev->eq_table;
+
+	atomic_notifier_call_chain(
+			&eq_table->nh[DH_EVENT_TYPE_NOTIFY_RISC_LOCAL_PPS],
+			DH_EVENT_TYPE_NOTIFY_RISC_LOCAL_PPS, NULL);
+	return 0;
+}
+
+static struct dh_pf_async_irq_table dh_pf_async_irq_tbl[] = {
+	{ "link_info", dh_eq_async_link_info_int_bond_pf },
+	{ "riscv", dh_eq_async_riscv_int },
+	{ "pf", dh_eq_async_pf_int },
+	{ "expps", dh_eq_async_extpps_int },
+	{ "localpps", dh_eq_async_local_pps_int },
+};
+
+static void cleanup_async_eq(struct dh_core_dev *dev, struct dh_eq_async *eq,
+							 const char *name)
+{
+	dh_eq_disable(dev, &eq->core, &eq->irq_nb);
+}
+
+static void destroy_async_eqs(struct dh_core_dev *dev)
+{
+	struct dh_eq_table *table = &dev->eq_table;
+	struct dh_pf_eq_table *table_priv = table->priv;
+	int32_t tbl_size = ARRAY_SIZE(dh_pf_async_irq_tbl);
+	int32_t i = 0;
+
+	for (i = 0; i < tbl_size; ++i) {
+		cleanup_async_eq(dev, &table_priv->async_eq_tbl[i],
+						 dh_pf_async_irq_tbl[i].name);
+	}
+	destroy_async_eq(dev);
+	dh_irqs_release_vectors(table_priv->async_irq_tbl, tbl_size);
+}
+
+void dh_pf_eq_table_destroy(struct dh_core_dev *dev)
+{
+	destroy_async_eqs(dev);
+}
+
+static int32_t create_async_eqs(struct dh_core_dev *dev)
+{
+	struct dh_eq_table *table = &dev->eq_table;
+	struct dh_pf_eq_table *table_priv = table->priv;
+	struct dh_eq_param param = {};
+	int32_t err = 0;
+	int32_t tbl_size = ARRAY_SIZE(dh_pf_async_irq_tbl);
+	int32_t i = 0;
+	int32_t j = 0;
+	int32_t k = 0;
+
+	for (i = 0; i < tbl_size; ++i) {
+		table_priv->async_irq_tbl[i] = dh_pf_async_irq_request(dev);
+		if (IS_ERR(table_priv->async_irq_tbl[i])) {
+			err = PTR_ERR(table_priv->async_irq_tbl[i]);
+			LOG_ERR("Failed to get async_irq_tbl[%d]\n", i);
+			goto err_async_irq_request;
+		}
+	}
+
+	err = create_async_eq(dev, table_priv->async_irq_tbl[1],
+						  table_priv->async_irq_tbl[2]);
+	if (err != 0) {
+		LOG_ERR("Failed to create async_eq\n");
+		goto err_async_irq_request;
+	}
+
+	param.nent = 10;
+	param.event_type = DH_EVENT_QUEUE_TYPE_RISCV;
+	for (j = 0; j < tbl_size; ++j) {
+		param.irq = table_priv->async_irq_tbl[j],
+		err = setup_async_eq(dev, &table_priv->async_eq_tbl[j], &param,
+							 dh_pf_async_irq_tbl[j].async_int,
+							 dh_pf_async_irq_tbl[j].name, dev);
+		if (err != 0) {
+			LOG_ERR("Failed to setup async_eq_tbl[%d]\n", j);
+			goto err_setup_async_eq;
+		}
+	}
+
+	return 0;
+
+err_setup_async_eq:
+	for (k = 0; k < j; ++k) {
+		cleanup_async_eq(dev, &table_priv->async_eq_tbl[j],
+						 dh_pf_async_irq_tbl[j].name);
+	}
+	destroy_async_eq(dev);
+err_async_irq_request:
+	dh_irqs_release_vectors(table_priv->async_irq_tbl, i);
+	return err;
+}
+
+int32_t zxdh_pf_async_eq_enable(struct dh_core_dev *dh_dev,
+								struct dh_eq_async *eq, const char *name,
+								bool attach)
+{
+	struct dh_eq_table *table = &dh_dev->eq_table;
+	struct dh_pf_eq_table *table_priv = table->priv;
+	int32_t err = 0;
+	int32_t tbl_size = ARRAY_SIZE(dh_pf_async_irq_tbl);
+	int32_t i = 0;
+
+	for (i = 0; i < tbl_size; ++i) {
+		if (strcmp(dh_pf_async_irq_tbl[i].name, name) == 0) {
+			eq->core.irq = table_priv->async_irq_tbl[i];
+			break;
+		}
+	}
+
+	if (i == tbl_size) {
+		LOG_ERR("failed to find %s irq\n", name);
+		return -1;
+	}
+
+	LOG_DEBUG("%s attach[%d] irq[%d]\n", name, attach, eq->core.irq->index);
+	if (attach) {
+		err = dh_eq_enable(dh_dev, &eq->core, &eq->irq_nb);
+		if (err != 0) {
+			LOG_WARN("failed to enable EQ %d\n", err);
+		}
+	} else {
+		dh_eq_disable(dh_dev, &eq->core, &eq->irq_nb);
+	}
+
+	return err;
+}
+
+void zxdh_pf_get_link_info_from_vqm(struct dh_core_dev *dh_dev,
+									uint8_t *link_up)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	uint32_t dev_link_up = 0;
+
+	dev_link_up = ioread32((void __iomem *)(pf_dev->pci_ioremap_addr[0] +
+											ZXDH_DEV_MAC_HIGH_OFFSET));
+	*link_up = (dev_link_up >> 16) & 0xff;
+
+	LOG_INFO("dev pcieid:0x%x ******** link_up: %d ********\n", pf_dev->pcie_id,
+			 *link_up);
+	return;
+}
+
+void zxdh_pf_set_vf_link_info(struct dh_core_dev *dh_dev, uint16_t vf_idx,
+							  uint8_t link_up)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	uint32_t dev_link_up = 0;
+
+	dev_link_up = ioread32((void __iomem *)(pf_dev->pf_sriov_cap_base +
+											(pf_dev->sriov_bar_size) * vf_idx +
+											ZXDH_DEV_MAC_HIGH_OFFSET));
+	dev_link_up = (dev_link_up & ~(0xFF << 16)) | ((uint32_t)(link_up) << 16);
+	iowrite32(dev_link_up, (void __iomem *)(pf_dev->pf_sriov_cap_base +
+											(pf_dev->sriov_bar_size) * vf_idx +
+											ZXDH_DEV_MAC_HIGH_OFFSET));
+
+	return;
+}
+
+void zxdh_pf_set_pf_phy_port(struct dh_core_dev *dh_dev, uint8_t phy_port)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	pf_dev->phy_port = phy_port;
+}
+
+uint8_t zxdh_pf_get_pf_phy_port(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	return pf_dev->phy_port;
+}
+
+void zxdh_pf_set_pf_link_up(struct dh_core_dev *dh_dev, bool link_up)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	pf_dev->link_up = link_up;
+}
+
+bool zxdh_pf_get_pf_link_up(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	return pf_dev->link_up;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/eq.h b/src/net/drivers/net/ethernet/dinghai/en_pf/eq.h
old mode 100755
new mode 100644
index 5c536357625a140fa4c78adf94b38ae37eb5e854..308ab1d03ca0d8a2b0603ba1c1d79195fcf6f0e3
--- a/src/net/drivers/net/ethernet/dinghai/en_pf/eq.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_pf/eq.h
@@ -1,53 +1,55 @@
-#ifndef __ZXDH_PF_EQ_H__
-#define __ZXDH_PF_EQ_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/driver.h>
-#include <linux/notifier.h>
-#include <linux/types.h>
-#include <linux/dinghai/pci_irq.h>
-#include <linux/dinghai/eq.h>
-
-#define ZXDH_PF_INVALID_MSIX_VEC 0xffff
-
-int32_t dh_pf_eq_table_create(struct dh_core_dev *dev);
-void dh_pf_eq_table_destroy(struct dh_core_dev *dev);
-int32_t dh_pf_eq_table_init(struct dh_core_dev *dev);
-uint16_t zxdh_pf_get_vqs_channels_num(struct dh_core_dev *dh_dev);
-
-void zxdh_pf_switch_irq(struct dh_core_dev *dh_dev, int32_t i, int32_t op);
-int32_t zxdh_pf_vq_irqs_request(struct dh_core_dev *dh_dev, struct dh_irq **vq_irqs, int32_t vq_channels);
-void zxdh_pf_affinity_irqs_release(struct dh_core_dev *dh_dev, struct dh_irq **vq_irqs, int32_t num_irqs);
-void zxdh_enable_irq(struct dh_core_dev *dh_dev, int32_t irq_index);
-
-int32_t zxdh_pf_async_eq_enable(struct dh_core_dev *dev, struct dh_eq_async *eq, const char *name, bool attach);
-void zxdh_pf_set_pf_link_up(struct dh_core_dev *dh_dev, bool link_up);
-bool zxdh_pf_get_pf_link_up(struct dh_core_dev *dh_dev);
-void zxdh_pf_set_vf_link_info(struct dh_core_dev *dh_dev, uint16_t vf_idx, uint8_t link_up);
-void zxdh_pf_get_link_info_from_vqm(struct dh_core_dev *dh_dev, uint8_t *link_up);
-void zxdh_pf_set_pf_phy_port(struct dh_core_dev *dh_dev, uint8_t phy_port);
-uint8_t zxdh_pf_get_pf_phy_port(struct dh_core_dev *dh_dev);
-
-#define ZXDH_PF_ASYNC_IRQ_NUM 5
-struct dh_pf_eq_table {
-    struct dh_irq      **vq_irqs;
-    int32_t vq_irq_num;
-    struct list_head    vqs_eqs_list;
-    struct dh_irq       *async_irq_tbl[ZXDH_PF_ASYNC_IRQ_NUM];
-    struct dh_eq_async  async_eq_tbl[ZXDH_PF_ASYNC_IRQ_NUM];
-};
-
-struct dh_pf_async_irq_table
-{
-    char name[64];
-    notifier_fn_t async_int;
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef __ZXDH_PF_EQ_H__
+#define __ZXDH_PF_EQ_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/driver.h>
+#include <linux/notifier.h>
+#include <linux/types.h>
+#include <linux/dinghai/pci_irq.h>
+#include <linux/dinghai/eq.h>
+
+int32_t dh_pf_eq_table_create(struct dh_core_dev *dev);
+void dh_pf_eq_table_destroy(struct dh_core_dev *dev);
+int32_t dh_pf_eq_table_init(struct dh_core_dev *dev);
+uint16_t zxdh_pf_get_vqs_channels_num(struct dh_core_dev *dh_dev);
+
+void zxdh_pf_switch_irq(struct dh_core_dev *dh_dev, int32_t i, int32_t op);
+int32_t zxdh_pf_vq_irqs_request(struct dh_core_dev *dh_dev,
+								struct dh_irq **vq_irqs, int32_t vq_channels);
+void zxdh_pf_affinity_irqs_release(struct dh_core_dev *dh_dev,
+								   struct dh_irq **vq_irqs, int32_t num_irqs);
+void zxdh_enable_irq(struct dh_core_dev *dh_dev, int32_t irq_index);
+
+int32_t zxdh_pf_async_eq_enable(struct dh_core_dev *dev, struct dh_eq_async *eq,
+								const char *name, bool attach);
+void zxdh_pf_set_pf_link_up(struct dh_core_dev *dh_dev, bool link_up);
+bool zxdh_pf_get_pf_link_up(struct dh_core_dev *dh_dev);
+void zxdh_pf_set_vf_link_info(struct dh_core_dev *dh_dev, uint16_t vf_idx,
+							  uint8_t link_up);
+void zxdh_pf_get_link_info_from_vqm(struct dh_core_dev *dh_dev,
+									uint8_t *link_up);
+void zxdh_pf_set_pf_phy_port(struct dh_core_dev *dh_dev, uint8_t phy_port);
+uint8_t zxdh_pf_get_pf_phy_port(struct dh_core_dev *dh_dev);
+
+#define ZXDH_PF_ASYNC_IRQ_NUM 5
+struct dh_pf_eq_table {
+	struct dh_irq **vq_irqs;
+	int32_t vq_irq_num;
+	struct list_head vqs_eqs_list;
+	struct dh_irq *async_irq_tbl[ZXDH_PF_ASYNC_IRQ_NUM];
+	struct dh_eq_async async_eq_tbl[ZXDH_PF_ASYNC_IRQ_NUM];
+};
+
+struct dh_pf_async_irq_table {
+	char name[64];
+	notifier_fn_t async_int;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/events.c b/src/net/drivers/net/ethernet/dinghai/en_pf/events.c
index 319132d8ca085955c65784d2d47a372ae0b2b75f..7573e13e671b30b14bbd2a430249b33217faa620 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_pf/events.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_pf/events.c
@@ -1,318 +1,337 @@
-#include <linux/gfp.h>
-#include <linux/slab.h>
-#include <linux/dinghai/driver.h>
-#include <linux/notifier.h>
-#include <linux/dinghai/events.h>
-#include <linux/dinghai/dh_cmd.h>
-#include <linux/workqueue.h>
-#include <linux/kernel.h>
-#include "events.h"
-#include "../en_pf.h"
-#include "../msg_common.h"
-#include "eq.h"
-
-static int32_t riscv2pf_notifier(struct notifier_block *, unsigned long, void *);
-static int32_t riscv_ready_notifier(struct notifier_block *, unsigned long, void *);
-static int32_t vf2pf_notifier(struct notifier_block *, unsigned long, void *);
-static int32_t riscv_ext_pps_notifier(struct notifier_block *, unsigned long, void *);
-static int32_t riscv_local_pps_notifier(struct notifier_block *nb, unsigned long type, void *data);
-
-extern irqreturn_t msix_extern_pps_irq_from_risc_handler(struct zxdh_pf_device *dev);
-extern irqreturn_t msix_local_pps_irq_from_risc_handler(struct zxdh_pf_device *dev);
-
-static struct dh_nb pf_events[] = {
-    {.nb.notifier_call = riscv_ready_notifier, .event_type = DH_EVENT_TYPE_RISCV_READY},
-    {.nb.notifier_call = vf2pf_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_VF_TO_PF},
-    {.nb.notifier_call = riscv_ext_pps_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_RISC_EXT_PPS},
-    {.nb.notifier_call = riscv_local_pps_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_RISC_LOCAL_PPS},
-    {.nb.notifier_call = riscv2pf_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_ANY},
-};
-
-static int32_t riscv2pf_notifier(struct notifier_block *nb, unsigned long type, void *data)
-{
-    struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
-    struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    zxdh_events_work_enqueue(dh_dev, &pf_dev->riscv2pf_msg_proc_work);
-
-    return NOTIFY_OK;
-}
-
-static int32_t riscv_ready_notifier(struct notifier_block *nb, unsigned long type, void *data)
-{
-    struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
-    struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    uint64_t virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET;
-    zxdh_bar_reset_valid(virt_addr);
-    zxdh_events_work_enqueue(dh_dev, &pf_dev->riscv_ready_work);
-
-    return NOTIFY_OK;
-}
-
-static int32_t vf2pf_notifier(struct notifier_block *nb, unsigned long type, void *data)
-{
-    struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
-    struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    LOG_INFO("is called\n");
-
-    zxdh_events_work_enqueue(dh_dev, &pf_dev->vf2pf_msg_proc_work);
-
-    return NOTIFY_OK;
-}
-
-static int32_t riscv_ext_pps_notifier(struct notifier_block *nb, unsigned long type, void *data)
-{
-    struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
-    struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    LOG_INFO("is called\n");
-
-    zxdh_events_work_enqueue(dh_dev, &pf_dev->riscv_ext_pps_work);
-
-    return NOTIFY_OK;
-}
-
-static int32_t riscv_local_pps_notifier(struct notifier_block *nb, unsigned long type, void *data)
-{
-    struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
-    struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-    LOG_INFO("is called\n");
-
-    zxdh_events_work_enqueue(dh_dev, &pf_dev->riscv_local_pps_work);
-
-    return NOTIFY_OK;
-}
-
-extern int32_t zxdh_plug_aux_dev(struct dh_core_dev *dh_dev);
-
-static void riscv2pf_msg_proc_work_handler(struct work_struct *_work)
-{
-    struct zxdh_pf_device *pf_dev = container_of(_work, struct zxdh_pf_device, riscv2pf_msg_proc_work);
-
-    uint16_t src = MSG_CHAN_END_RISC;
-    uint16_t dst = MSG_CHAN_END_PF;
-    uint64_t virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET;
-
-    ZXDH_AUX_COMP_FLAG_CHECK(pf_dev);
-
-    zxdh_bar_irq_recv(src, dst, virt_addr, NULL);
-}
-
-static void vf2pf_msg_proc_work_handler(struct work_struct *_work)
-{
-    struct zxdh_pf_device *pf_dev = container_of(_work, struct zxdh_pf_device, vf2pf_msg_proc_work);
-
-    uint16_t src = MSG_CHAN_END_VF;
-    uint16_t dst = MSG_CHAN_END_PF;
-    uint64_t virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET + ZXDH_BAR_PFVF_MSG_OFFSET;
-
-    ZXDH_AUX_COMP_FLAG_CHECK(pf_dev);
-
-    zxdh_bar_irq_recv(src, dst, virt_addr, pf_dev);
-}
-
-static void riscv_ready_work_handler(struct work_struct *_work)
-{
-    struct zxdh_pf_device *pf_dev = container_of(_work, struct zxdh_pf_device, riscv_ready_work);
-    struct dh_core_dev * dh_dev = container_of((void*)pf_dev, struct dh_core_dev, priv);
-
-    ZXDH_AUX_COMP_FLAG_CHECK(pf_dev);
-
-    zxdh_plug_aux_dev(dh_dev);
-}
-
-
-int32_t findFirstSetBit(uint8_t link_up_val) {
-    uint8_t i = 0;
-    for ( ; i < 8; i++)
-    {
-        if (link_up_val & (1 << i))
-        {
-            return i;  // 返回第一个设置位的位置
-        }
-    }
-    return -1;  // 没有找到
-}
-
-int32_t get_link_up_phyport(uint8_t link_up_val,struct zxdh_pf_device *pf_dev, uint8_t *phyport_val)
-{
-    int16_t first_link_up_idx = -1;
-    uint8_t port_num = pf_dev->port_resource.pannel_num;
-    struct zxdh_pannle_port *port;
-    int32_t idx = 0;
-
-    first_link_up_idx = findFirstSetBit(link_up_val);
-    if(first_link_up_idx<0)
-    {
-        return -1;
-    }
-    //基于first_link_up_idx找到phyport值TODO:待完善
-    for (idx = 0; idx < port_num; idx++)
-    {
-        port = &pf_dev->port_resource.port[idx];
-        if (port->link_check_bit == first_link_up_idx)
-        {
-            *phyport_val = port->phyport;
-            LOG_INFO("first link_up idx %d <-> phyport 0x%x\n", first_link_up_idx, port->phyport);
-            return 0;
-        }
-    }
-
-    return -1;
-}
-
-static void link_info_irq_update_vf_bond_pf_work_handler(struct work_struct *_work)
-{
-    struct zxdh_pf_device *pf_dev = container_of(_work, struct zxdh_pf_device, link_info_irq_update_vf_bond_pf_work);
-    struct dh_core_dev * dh_dev = container_of((void*)pf_dev, struct dh_core_dev, priv);
-    struct zxdh_vf_item *vf_item = NULL;
-    int32_t err = 0;
-    uint16_t vf_idx = 0;
-    struct pci_dev *pdev = dh_dev->pdev;
-    uint16_t num_vfs = 0;
-    uint8_t link_up_val = 0;
-    uint8_t phyport_val = 0;
-    uint8_t link_info = 0;
-    uint16_t func_no = 0;
-    uint16_t pf_no = FIND_PF_ID(pf_dev->pcie_id);
-    union zxdh_msg msg = {0};
-
-    ZXDH_AUX_COMP_FLAG_CHECK(pf_dev);
-
-    zxdh_pf_get_link_info_from_vqm(dh_dev, &link_up_val);
-    LOG_INFO("[pf_level] bond_pf pcie_id:0x%x read from VQM, val: 0x%x\n", pf_dev->pcie_id, link_up_val);
-    pf_dev->link_up = (link_up_val == 0) ? FALSE : TRUE;
-
-    if(pf_dev->link_up)
-    {
-        if(get_link_up_phyport(link_up_val, pf_dev, &phyport_val)<0)
-        {
-            LOG_ERR("failed to get link up phyport\n");
-            return;
-        }
-        link_up_val = 1;
-    }
-
-    link_info = (phyport_val & 0x0F) << 4 | (link_up_val & 0x0F);
-    msg.payload.hdr_to_agt.op_code = AGENT_DEV_STATUS_NOTIFY;
-    msg.payload.hdr_to_agt.pcie_id = pf_dev->pcie_id;
-    num_vfs = pci_num_vf(pdev);
-    for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
-    {
-        vf_item = zxdh_pf_get_vf_item(dh_dev, vf_idx);
-        if(vf_item->link_forced == FALSE && vf_item->is_probed)
-        {
-            func_no = GET_FUNC_NO(pf_no, vf_idx);
-            msg.payload.pcie_msix_msg.func_no[msg.payload.pcie_msix_msg.num++] = func_no;
-            zxdh_pf_set_vf_link_info(dh_dev, vf_idx, link_info);
-            LOG_INFO("[pf_level] bond_pf pcie_id:0x%x write phyport[0x%x] and link_up[%d] to VF[%d] VQM[0x%x]\n", pf_dev->pcie_id, phyport_val, link_up_val, vf_idx, link_info);
-        }
-    }
-    LOG_INFO("vf num:%d\n",msg.payload.pcie_msix_msg.num);
-    if(msg.payload.pcie_msix_msg.num > 0)
-    {
-        err = zxdh_pf_msg_send_cmd(dh_dev, MODULE_MAC, &msg, &msg, true);
-        if (err != 0)
-        {
-            LOG_ERR("failed to update VF link info\n");
-        }
-    }
-}
-
-static void riscv_extern_pps_handler(struct work_struct *_work)
-{
-    struct zxdh_pf_device *pf_dev = container_of(_work, struct zxdh_pf_device, riscv_ext_pps_work);
-
-    msix_extern_pps_irq_from_risc_handler(pf_dev);
-}
-
-static void riscv_local_pps_handler(struct work_struct *_work)
-{
-    struct zxdh_pf_device *pf_dev = container_of(_work, struct zxdh_pf_device, riscv_local_pps_work);
-
-    msix_local_pps_irq_from_risc_handler(pf_dev);
-}
-
-int32_t dh_pf_events_init(struct dh_core_dev *dev)
-{
-    struct dh_events *events = NULL;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-    int32_t i = 0;
-    int32_t ret = 0;
-    uint32_t evt_num = ARRAY_SIZE(pf_events);
-
-    if (pf_dev->bond_num != 0)
-    {
-        evt_num -= 1;
-    }
-    events = kzalloc((sizeof(*events) + evt_num * sizeof(struct dh_event_nb)), GFP_KERNEL);
-    if (unlikely(events == NULL))
-    {
-        LOG_ERR("events kzalloc failed: %p\n", events);
-        ret = -ENOMEM;
-        goto err_events_kzalloc;
-    }
-
-    events->evt_num = evt_num;
-    events->dev = dev;
-    dev->events = events;
-    events->wq = create_singlethread_workqueue("dh_pf_events");
-    if (!events->wq)
-    {
-        LOG_ERR("events->wq create_singlethread_workqueue failed: %p\n", events->wq);
-        ret = -ENOMEM;
-        goto err_create_wq;
-    }
-
-    INIT_WORK(&pf_dev->riscv_ready_work, riscv_ready_work_handler);
-    INIT_WORK(&pf_dev->riscv2pf_msg_proc_work, riscv2pf_msg_proc_work_handler);
-    INIT_WORK(&pf_dev->vf2pf_msg_proc_work, vf2pf_msg_proc_work_handler);
-    INIT_WORK(&pf_dev->link_info_irq_update_vf_bond_pf_work, link_info_irq_update_vf_bond_pf_work_handler);
-    INIT_WORK(&pf_dev->riscv_ext_pps_work, riscv_extern_pps_handler);
-    INIT_WORK(&pf_dev->riscv_local_pps_work, riscv_local_pps_handler);
-
-    for (i = 0; i < evt_num; i++)
-    {
-        events->notifiers[i].nb = pf_events[i];
-        events->notifiers[i].ctx = dev;
-        dh_eq_notifier_register(&dev->eq_table, &events->notifiers[i].nb);
-    }
-
-    return 0;
-
-err_create_wq:
-    kfree(events);
-err_events_kzalloc:
-    return ret;
-}
-
-void dh_pf_events_uninit(struct dh_core_dev *dev)
-{
-    struct dh_events *events = dev->events;
-    int32_t i = 0;
-
-    for (i = events->evt_num - 1; i >= 0 ; i--)
-    {
-        dh_eq_notifier_unregister(&dev->eq_table, &events->notifiers[i].nb);
-    }
-
-    zxdh_events_cleanup(dev);
-    return;
-}
-
-
-void dh_pf_sriov_cap_cfg_uninit(struct dh_core_dev *dev)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-    if (dev->coredev_type == DH_COREDEV_PF && pf_dev->pf_sriov_cap_base != NULL)
-    {
-        iounmap((void *)pf_dev->pf_sriov_cap_base);
-        pf_dev->pf_sriov_cap_base = NULL;
-    }
-    return;
+#include <linux/gfp.h>
+#include <linux/slab.h>
+#include <linux/dinghai/driver.h>
+#include <linux/notifier.h>
+#include <linux/dinghai/events.h>
+#include <linux/dinghai/dh_cmd.h>
+#include <linux/workqueue.h>
+#include <linux/kernel.h>
+#include "events.h"
+#include "../en_pf.h"
+#include "../msg_common.h"
+#include "eq.h"
+
+static int32_t riscv2pf_notifier(struct notifier_block *, unsigned long,
+								 void *);
+static int32_t riscv_ready_notifier(struct notifier_block *, unsigned long,
+									void *);
+static int32_t vf2pf_notifier(struct notifier_block *, unsigned long, void *);
+static int32_t riscv_ext_pps_notifier(struct notifier_block *, unsigned long,
+									  void *);
+static int32_t riscv_local_pps_notifier(struct notifier_block *nb,
+										unsigned long type, void *data);
+
+extern irqreturn_t
+msix_extern_pps_irq_from_risc_handler(struct zxdh_pf_device *dev);
+extern irqreturn_t
+msix_local_pps_irq_from_risc_handler(struct zxdh_pf_device *dev);
+
+static struct dh_nb pf_events[] = {
+	{ .nb.notifier_call = riscv_ready_notifier,
+	  .event_type = DH_EVENT_TYPE_RISCV_READY },
+	{ .nb.notifier_call = vf2pf_notifier,
+	  .event_type = DH_EVENT_TYPE_NOTIFY_VF_TO_PF },
+	{ .nb.notifier_call = riscv_ext_pps_notifier,
+	  .event_type = DH_EVENT_TYPE_NOTIFY_RISC_EXT_PPS },
+	{ .nb.notifier_call = riscv_local_pps_notifier,
+	  .event_type = DH_EVENT_TYPE_NOTIFY_RISC_LOCAL_PPS },
+	{ .nb.notifier_call = riscv2pf_notifier,
+	  .event_type = DH_EVENT_TYPE_NOTIFY_ANY },
+};
+
+static int32_t riscv2pf_notifier(struct notifier_block *nb, unsigned long type,
+								 void *data)
+{
+	struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
+	struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	zxdh_events_work_enqueue(dh_dev, &pf_dev->riscv2pf_msg_proc_work);
+
+	return NOTIFY_OK;
+}
+
+static int32_t riscv_ready_notifier(struct notifier_block *nb,
+									unsigned long type, void *data)
+{
+	struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
+	struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+
+	uint64_t virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET;
+	zxdh_bar_reset_valid(virt_addr);
+	zxdh_events_work_enqueue(dh_dev, &pf_dev->riscv_ready_work);
+
+	return NOTIFY_OK;
+}
+
+static int32_t vf2pf_notifier(struct notifier_block *nb, unsigned long type,
+							  void *data)
+{
+	struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
+	struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	LOG_INFO("is called\n");
+
+	zxdh_events_work_enqueue(dh_dev, &pf_dev->vf2pf_msg_proc_work);
+
+	return NOTIFY_OK;
+}
+
+static int32_t riscv_ext_pps_notifier(struct notifier_block *nb,
+									  unsigned long type, void *data)
+{
+	struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
+	struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	LOG_INFO("is called\n");
+
+	zxdh_events_work_enqueue(dh_dev, &pf_dev->riscv_ext_pps_work);
+
+	return NOTIFY_OK;
+}
+
+static int32_t riscv_local_pps_notifier(struct notifier_block *nb,
+										unsigned long type, void *data)
+{
+	struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
+	struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	LOG_INFO("is called\n");
+
+	zxdh_events_work_enqueue(dh_dev, &pf_dev->riscv_local_pps_work);
+
+	return NOTIFY_OK;
+}
+
+extern int32_t zxdh_plug_aux_dev(struct dh_core_dev *dh_dev);
+
+static void riscv2pf_msg_proc_work_handler(struct work_struct *_work)
+{
+	struct zxdh_pf_device *pf_dev =
+			container_of(_work, struct zxdh_pf_device, riscv2pf_msg_proc_work);
+
+	uint16_t src = MSG_CHAN_END_RISC;
+	uint16_t dst = MSG_CHAN_END_PF;
+	uint64_t virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET;
+
+	ZXDH_AUX_COMP_FLAG_CHECK(pf_dev);
+
+	zxdh_bar_irq_recv(src, dst, virt_addr, NULL);
+}
+
+static void vf2pf_msg_proc_work_handler(struct work_struct *_work)
+{
+	struct zxdh_pf_device *pf_dev =
+			container_of(_work, struct zxdh_pf_device, vf2pf_msg_proc_work);
+
+	uint16_t src = MSG_CHAN_END_VF;
+	uint16_t dst = MSG_CHAN_END_PF;
+	uint64_t virt_addr = pf_dev->pci_ioremap_addr[0] + ZXDH_BAR_MSG_OFFSET +
+						 ZXDH_BAR_PFVF_MSG_OFFSET;
+
+	ZXDH_AUX_COMP_FLAG_CHECK(pf_dev);
+
+	zxdh_bar_irq_recv(src, dst, virt_addr, pf_dev);
+}
+
+static void riscv_ready_work_handler(struct work_struct *_work)
+{
+	struct zxdh_pf_device *pf_dev =
+			container_of(_work, struct zxdh_pf_device, riscv_ready_work);
+	struct dh_core_dev *dh_dev =
+			container_of((void *)pf_dev, struct dh_core_dev, priv);
+
+	ZXDH_AUX_COMP_FLAG_CHECK(pf_dev);
+
+	zxdh_plug_aux_dev(dh_dev);
+}
+
+int32_t findFirstSetBit(uint8_t link_up_val)
+{
+	uint8_t i = 0;
+	for (; i < 8; i++) {
+		if (link_up_val & (1 << i)) {
+			return i; // 返回第一个设置位的位置
+		}
+	}
+	return -1; // 没有找到
+}
+
+int32_t get_link_up_phyport(uint8_t link_up_val, struct zxdh_pf_device *pf_dev,
+							uint8_t *phyport_val)
+{
+	int16_t first_link_up_idx = -1;
+	uint8_t port_num = pf_dev->port_resource.pannel_num;
+	struct zxdh_pannle_port *port;
+	int32_t idx = 0;
+
+	first_link_up_idx = findFirstSetBit(link_up_val);
+	if (first_link_up_idx < 0) {
+		return -1;
+	}
+	//基于first_link_up_idx找到phyport值TODO:待完善
+	for (idx = 0; idx < port_num; idx++) {
+		port = &pf_dev->port_resource.port[idx];
+		if (port->link_check_bit == first_link_up_idx) {
+			*phyport_val = port->phyport;
+			LOG_INFO("first link_up idx %d <-> phyport 0x%x\n",
+					 first_link_up_idx, port->phyport);
+			return 0;
+		}
+	}
+
+	return -1;
+}
+
+static void
+link_info_irq_update_vf_bond_pf_work_handler(struct work_struct *_work)
+{
+	struct zxdh_pf_device *pf_dev = container_of(
+			_work, struct zxdh_pf_device, link_info_irq_update_vf_bond_pf_work);
+	struct dh_core_dev *dh_dev =
+			container_of((void *)pf_dev, struct dh_core_dev, priv);
+	struct zxdh_vf_item *vf_item = NULL;
+	int32_t err = 0;
+	uint16_t vf_idx = 0;
+	struct pci_dev *pdev = dh_dev->pdev;
+	uint16_t num_vfs = 0;
+	uint8_t link_up_val = 0;
+	uint8_t phyport_val = 0;
+	uint8_t link_info = 0;
+	uint16_t func_no = 0;
+	uint16_t pf_no = FIND_PF_ID(pf_dev->pcie_id);
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info ack = { 0 };
+
+	ZXDH_AUX_COMP_FLAG_CHECK(pf_dev);
+
+	zxdh_pf_get_link_info_from_vqm(dh_dev, &link_up_val);
+	LOG_INFO("[pf_level] bond_pf pcie_id:0x%x read from VQM, val: 0x%x\n",
+			 pf_dev->pcie_id, link_up_val);
+	pf_dev->link_up = (link_up_val == 0) ? FALSE : TRUE;
+
+	if (pf_dev->link_up) {
+		if (get_link_up_phyport(link_up_val, pf_dev, &phyport_val) < 0) {
+			LOG_ERR("failed to get link up phyport\n");
+			return;
+		}
+		link_up_val = 1;
+	}
+
+	link_info = (phyport_val & 0x0F) << 4 | (link_up_val & 0x0F);
+	msg.hdr_to_agt.op_code = AGENT_DEV_STATUS_NOTIFY;
+	msg.hdr_to_agt.pcie_id = pf_dev->pcie_id;
+	num_vfs = pci_num_vf(pdev);
+	for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) {
+		vf_item = zxdh_pf_get_vf_item(dh_dev, vf_idx);
+		if (vf_item->link_forced == FALSE && vf_item->is_probed) {
+			func_no = GET_FUNC_NO(pf_no, vf_idx);
+			msg.pcie_msix_msg.func_no[msg.pcie_msix_msg.num++] = func_no;
+			zxdh_pf_set_vf_link_info(dh_dev, vf_idx, link_info);
+			LOG_INFO("[pf_level] bond_pf pcie_id:0x%x write phyport[0x%x] and "
+					 "link_up[%d] to VF[%d] VQM[0x%x]\n",
+					 pf_dev->pcie_id, phyport_val, link_up_val, vf_idx,
+					 link_info);
+		}
+	}
+	LOG_INFO("vf num:%d\n", msg.pcie_msix_msg.num);
+	if (msg.pcie_msix_msg.num > 0) {
+		err = zxdh_pf_msg_send_cmd(dh_dev, MODULE_MAC, &msg, &ack, true);
+		if (err != 0) {
+			LOG_ERR("failed to update VF link info\n");
+		}
+	}
+}
+
+static void riscv_extern_pps_handler(struct work_struct *_work)
+{
+	struct zxdh_pf_device *pf_dev =
+			container_of(_work, struct zxdh_pf_device, riscv_ext_pps_work);
+
+	msix_extern_pps_irq_from_risc_handler(pf_dev);
+}
+
+static void riscv_local_pps_handler(struct work_struct *_work)
+{
+	struct zxdh_pf_device *pf_dev =
+			container_of(_work, struct zxdh_pf_device, riscv_local_pps_work);
+
+	msix_local_pps_irq_from_risc_handler(pf_dev);
+}
+
+int32_t dh_pf_events_init(struct dh_core_dev *dev)
+{
+	struct dh_events *events = NULL;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+	int32_t i = 0;
+	int32_t ret = 0;
+	uint32_t evt_num = ARRAY_SIZE(pf_events);
+
+	if (pf_dev->bond_num != 0) {
+		evt_num -= 1;
+	}
+	events = kzalloc((sizeof(*events) + evt_num * sizeof(struct dh_event_nb)),
+					 GFP_KERNEL);
+	if (unlikely(events == NULL)) {
+		LOG_ERR("events kzalloc failed: %p\n", events);
+		ret = -ENOMEM;
+		goto err_events_kzalloc;
+	}
+
+	events->evt_num = evt_num;
+	events->dev = dev;
+	dev->events = events;
+	events->wq = create_singlethread_workqueue("dh_pf_events");
+	if (!events->wq) {
+		LOG_ERR("events->wq create_singlethread_workqueue failed: %p\n",
+				events->wq);
+		ret = -ENOMEM;
+		goto err_create_wq;
+	}
+
+	INIT_WORK(&pf_dev->riscv_ready_work, riscv_ready_work_handler);
+	INIT_WORK(&pf_dev->riscv2pf_msg_proc_work, riscv2pf_msg_proc_work_handler);
+	INIT_WORK(&pf_dev->vf2pf_msg_proc_work, vf2pf_msg_proc_work_handler);
+	INIT_WORK(&pf_dev->link_info_irq_update_vf_bond_pf_work,
+			  link_info_irq_update_vf_bond_pf_work_handler);
+	INIT_WORK(&pf_dev->riscv_ext_pps_work, riscv_extern_pps_handler);
+	INIT_WORK(&pf_dev->riscv_local_pps_work, riscv_local_pps_handler);
+
+	for (i = 0; i < evt_num; i++) {
+		events->notifiers[i].nb = pf_events[i];
+		events->notifiers[i].ctx = dev;
+		dh_eq_notifier_register(&dev->eq_table, &events->notifiers[i].nb);
+	}
+
+	return 0;
+
+err_create_wq:
+	kfree(events);
+err_events_kzalloc:
+	return ret;
+}
+
+void dh_pf_events_uninit(struct dh_core_dev *dev)
+{
+	struct dh_events *events = dev->events;
+	int32_t i = 0;
+
+	for (i = events->evt_num - 1; i >= 0; i--) {
+		dh_eq_notifier_unregister(&dev->eq_table, &events->notifiers[i].nb);
+	}
+
+	zxdh_events_cleanup(dev);
+	return;
+}
+
+void dh_pf_sriov_cap_cfg_uninit(struct dh_core_dev *dev)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+	if (dev->coredev_type == DH_COREDEV_PF &&
+		pf_dev->pf_sriov_cap_base != NULL) {
+		iounmap((void *)pf_dev->pf_sriov_cap_base);
+		pf_dev->pf_sriov_cap_base = NULL;
+	}
+	return;
 }
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/events.h b/src/net/drivers/net/ethernet/dinghai/en_pf/events.h
index 9905db99e8f60a893c62e36219cd16d4bc2feded..9aa6a97de7ad00cc61abcf1faa5b90455e1996e5 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_pf/events.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_pf/events.h
@@ -1,17 +1,16 @@
-#ifndef __ZXDH_PF_EVENTS_H__
-#define __ZXDH_PF_EVENTS_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int32_t dh_pf_events_init(struct dh_core_dev *dev);
-void dh_pf_events_uninit(struct dh_core_dev *dev);
-void dh_pf_sriov_cap_cfg_uninit(struct dh_core_dev *dev);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef __ZXDH_PF_EVENTS_H__
+#define __ZXDH_PF_EVENTS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int32_t dh_pf_events_init(struct dh_core_dev *dev);
+void dh_pf_events_uninit(struct dh_core_dev *dev);
+void dh_pf_sriov_cap_cfg_uninit(struct dh_core_dev *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/irq.c b/src/net/drivers/net/ethernet/dinghai/en_pf/irq.c
old mode 100755
new mode 100644
index c6bcb9eb4cfb663ddf1b6d93412a6d3d91ecc476..40f0e3b3141eb0a562c1c145fa022fb4a2b70e43
--- a/src/net/drivers/net/ethernet/dinghai/en_pf/irq.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_pf/irq.c
@@ -1,180 +1,176 @@
-#include <linux/pci.h>
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/helper.h>
-#include "irq.h"
-#include "eq.h"
-
-#define ZXDH_PF_ASYNC_IRQ_MIN_COMP 0
-#define ZXDH_PF_ASYNC_IRQ_MAX_COMP 19
-
-#define ZXDH_PF_RDMA_IRQ_MIN 0
-#define ZXDH_PF_RDMA_IRQ_MAX 12
-
-#define ZXDH_PF_COMP_IRQ_MIN_COMP 0
-#define ZXDH_PF_COMP_IRQ_MAX_COMP 1
-
-#define ZXDH_PF_VQ_IRQ_MIN 0
-#define ZXDH_PF_VQ_IRQ_MAX 33
-
-
-struct dh_irq_range {
-    int32_t start;
-    int32_t size;
-};
-
-static struct dh_irq_range  __attribute__((unused)) dh_get_pf_range(struct dh_core_dev *dev)
-{
-    struct dh_irq_range tmp = {
-        .start = 0,
-        .size = 0
-    };
-
-    return tmp;
-}
-
-static int32_t irq_pools_init(struct dh_core_dev *dev, int vq_n, int pf_async_vec)
-{
-    struct dh_irq_table *table = &dev->irq_table;
-    struct dh_pf_irq_table *pf_irq_table = (struct dh_pf_irq_table *)table->priv;
-    int32_t err = 0;
-    struct dh_irq_range irq_range;
-
-    if(vq_n > 0)
-    {
-        irq_range.start = ZXDH_VQS_IRQ_START_IDX;
-        irq_range.size = vq_n;
-
-        pf_irq_table->pf_vq_pool = irq_pool_alloc(dev, irq_range.start,
-                                                  irq_range.size, "zxdh_pf_vq",
-                                                  ZXDH_PF_VQ_IRQ_MIN,
-                                                  ZXDH_PF_VQ_IRQ_MAX);
-        if (IS_ERR_OR_NULL(pf_irq_table->pf_vq_pool))
-        {
-            LOG_ERR("pf_irq_table->pf_vq_pool irq_pool_alloc failed\n");
-            return PTR_ERR(pf_irq_table->pf_vq_pool);
-        }
-
-        pf_irq_table->pf_vq_pool->irqs_per_cpu = kcalloc(nr_cpu_ids, sizeof(u16), GFP_KERNEL);
-        if (unlikely(pf_irq_table->pf_vq_pool->irqs_per_cpu == NULL))
-        {
-            LOG_ERR("pf_irq_table->pf_vq_pool->irqs_per_cpu kcalloc failed\n");
-            err = -ENOMEM;
-            goto err_irqs_per_cpu;
-        }
-    }
-
-    if (pf_async_vec > 0)
-    {
-        irq_range.start = 0;
-        irq_range.size = pf_async_vec;
-        pf_irq_table->pf_async_pool = irq_pool_alloc(dev, irq_range.start, irq_range.size, "zxdh_pf_async",
-                                                     ZXDH_PF_ASYNC_IRQ_MIN_COMP,
-                                                     ZXDH_PF_ASYNC_IRQ_MAX_COMP);
-        if (IS_ERR_OR_NULL(pf_irq_table->pf_async_pool))
-        {
-            LOG_ERR("pf_irq_table->pf_async_pool irq_pool_alloc failed\n");
-            err = PTR_ERR(pf_irq_table->pf_async_pool);
-            goto err_irqs_per_cpu;
-        }
-    }
-
-    irq_range.start = ZXDH_RDMA_IRQ_START_IDX;
-    irq_range.size = ZXDH_RDMA_CHANNELS_NUM;
-    pf_irq_table->pf_rdma_pool = irq_pool_alloc(dev, irq_range.start, irq_range.size, "zxdh_pf_rdma",
-                                                ZXDH_PF_RDMA_IRQ_MIN,
-                                                ZXDH_PF_RDMA_IRQ_MAX);
-    if (IS_ERR_OR_NULL(pf_irq_table->pf_rdma_pool))
-    {
-        LOG_ERR("pf_irq_table->pf_rdma_pool irq_pool_alloc failed\n");
-        err = PTR_ERR(pf_irq_table->pf_rdma_pool);
-        goto err_pf_rdma;
-    }
-
-    return 0;
-
-err_pf_rdma:
-    irq_pool_free(pf_irq_table->pf_async_pool);
-err_irqs_per_cpu:
-    irq_pool_free(pf_irq_table->pf_vq_pool);
-    return err;
-}
-
-static void irq_pools_destroy(struct dh_irq_table *table)
-{
-    struct dh_pf_irq_table* pf_irq_table = NULL;
-
-    pf_irq_table = (struct dh_pf_irq_table*)table->priv;
-    pf_irq_table->pf_vq_pool ? irq_pool_free(pf_irq_table->pf_vq_pool) : 0;
-    pf_irq_table->pf_async_pool ? irq_pool_free(pf_irq_table->pf_async_pool) : 0;
-    pf_irq_table->pf_rdma_pool ? irq_pool_free(pf_irq_table->pf_rdma_pool) : 0;
-}
-
-static int32_t zxdh_get_total_vec(struct dh_core_dev *dev)
-{
-    return ZXDH_VQS_CHANNELS_NUM + ZXDH_ASYNC_CHANNELS_NUM + ZXDH_RDMA_CHANNELS_NUM;
-}
-
-int32_t dh_pf_irq_table_create(struct dh_core_dev *dev)
-{
-    int32_t total_vec = 0;
-    int32_t err = 0;
-
-    total_vec = zxdh_get_total_vec(dev);
-
-    total_vec = pci_alloc_irq_vectors(dev->pdev, total_vec, total_vec, PCI_IRQ_MSIX);
-    if (total_vec < 0)
-    {
-        LOG_ERR("pci_alloc_irq_vectors failed: %d\n", total_vec);
-        return total_vec;
-    }
-
-    err = irq_pools_init(dev, ZXDH_VQS_CHANNELS_NUM, ZXDH_ASYNC_CHANNELS_NUM);
-    if (err != 0)
-    {
-        LOG_ERR("irq_pools_init failed: %d\n", err);
-        pci_free_irq_vectors(dev->pdev);
-    }
-
-    return err;
-}
-
-void dh_pf_irq_table_destroy(struct dh_core_dev *dev)
-{
-    struct dh_irq_table *table = &dev->irq_table;
-
-    /* There are cases where IRQs still will be in used when we reaching
-     * to here. Hence, making sure all the irqs are released.
-     */
-    irq_pools_destroy(table);
-    pci_free_irq_vectors(dev->pdev);
-}
-
-struct dh_irq *dh_pf_async_irq_request(struct dh_core_dev *dev)
-{
-    struct dh_irq_table *table = &dev->irq_table;
-    struct dh_pf_irq_table* pf_irq_table;
-
-    pf_irq_table = (struct dh_pf_irq_table*)table->priv;
-
-    return pf_irq_table->pf_async_pool ? zxdh_get_irq_of_pool(dev, pf_irq_table->pf_async_pool) : NULL;
-}
-
-/* irq_table API */
-int32_t dh_pf_irq_table_init(struct dh_core_dev *dev)
-{
-    struct dh_irq_table *irq_table;
-    struct dh_pf_irq_table* pf_irq_table = NULL;
-
-    irq_table = &dev->irq_table;
-
-    pf_irq_table = kvzalloc(sizeof(*pf_irq_table), GFP_KERNEL);
-    if (unlikely(pf_irq_table == NULL))
-    {
-        LOG_ERR("pf_irq_table kvzalloc failed\n");
-        return -ENOMEM;
-    }
-
-    irq_table->priv = pf_irq_table;
-
-    return 0;
+#include <linux/pci.h>
+#include <linux/dinghai/driver.h>
+#include <linux/dinghai/helper.h>
+#include "irq.h"
+#include "eq.h"
+
+#define ZXDH_PF_ASYNC_IRQ_MIN_COMP 0
+#define ZXDH_PF_ASYNC_IRQ_MAX_COMP 19
+
+#define ZXDH_PF_RDMA_IRQ_MIN 0
+#define ZXDH_PF_RDMA_IRQ_MAX 12
+
+#define ZXDH_PF_COMP_IRQ_MIN_COMP 0
+#define ZXDH_PF_COMP_IRQ_MAX_COMP 1
+
+#define ZXDH_PF_VQ_IRQ_MIN 0
+#define ZXDH_PF_VQ_IRQ_MAX 33
+
+struct dh_irq_range {
+	int32_t start;
+	int32_t size;
+};
+
+static struct dh_irq_range __attribute__((unused))
+dh_get_pf_range(struct dh_core_dev *dev)
+{
+	struct dh_irq_range tmp = { .start = 0, .size = 0 };
+
+	return tmp;
+}
+
+static int32_t irq_pools_init(struct dh_core_dev *dev, int vq_n,
+							  int pf_async_vec)
+{
+	struct dh_irq_table *table = &dev->irq_table;
+	struct dh_pf_irq_table *pf_irq_table =
+			(struct dh_pf_irq_table *)table->priv;
+	int32_t err = 0;
+	struct dh_irq_range irq_range;
+
+	if (vq_n > 0) {
+		irq_range.start = ZXDH_VQS_IRQ_START_IDX;
+		irq_range.size = vq_n;
+
+		pf_irq_table->pf_vq_pool = irq_pool_alloc(dev, irq_range.start,
+												  irq_range.size, "zxdh_pf_vq",
+												  ZXDH_PF_VQ_IRQ_MIN,
+												  ZXDH_PF_VQ_IRQ_MAX);
+		if (IS_ERR_OR_NULL(pf_irq_table->pf_vq_pool)) {
+			LOG_ERR("pf_irq_table->pf_vq_pool irq_pool_alloc failed\n");
+			return PTR_ERR(pf_irq_table->pf_vq_pool);
+		}
+
+		pf_irq_table->pf_vq_pool->irqs_per_cpu =
+				kcalloc(nr_cpu_ids, sizeof(u16), GFP_KERNEL);
+		if (unlikely(pf_irq_table->pf_vq_pool->irqs_per_cpu == NULL)) {
+			LOG_ERR("pf_irq_table->pf_vq_pool->irqs_per_cpu kcalloc failed\n");
+			err = -ENOMEM;
+			goto err_irqs_per_cpu;
+		}
+	}
+
+	if (pf_async_vec > 0) {
+		irq_range.start = 0;
+		irq_range.size = pf_async_vec;
+		pf_irq_table->pf_async_pool = irq_pool_alloc(
+				dev, irq_range.start, irq_range.size, "zxdh_pf_async",
+				ZXDH_PF_ASYNC_IRQ_MIN_COMP, ZXDH_PF_ASYNC_IRQ_MAX_COMP);
+		if (IS_ERR_OR_NULL(pf_irq_table->pf_async_pool)) {
+			LOG_ERR("pf_irq_table->pf_async_pool irq_pool_alloc failed\n");
+			err = PTR_ERR(pf_irq_table->pf_async_pool);
+			goto err_irqs_per_cpu;
+		}
+	}
+
+	irq_range.start = ZXDH_RDMA_IRQ_START_IDX;
+	irq_range.size = ZXDH_RDMA_CHANNELS_NUM;
+	pf_irq_table->pf_rdma_pool =
+			irq_pool_alloc(dev, irq_range.start, irq_range.size, "zxdh_pf_rdma",
+						   ZXDH_PF_RDMA_IRQ_MIN, ZXDH_PF_RDMA_IRQ_MAX);
+	if (IS_ERR_OR_NULL(pf_irq_table->pf_rdma_pool)) {
+		LOG_ERR("pf_irq_table->pf_rdma_pool irq_pool_alloc failed\n");
+		err = PTR_ERR(pf_irq_table->pf_rdma_pool);
+		goto err_pf_rdma;
+	}
+
+	return 0;
+
+err_pf_rdma:
+	irq_pool_free(pf_irq_table->pf_async_pool);
+err_irqs_per_cpu:
+	irq_pool_free(pf_irq_table->pf_vq_pool);
+	return err;
+}
+
+static void irq_pools_destroy(struct dh_irq_table *table)
+{
+	struct dh_pf_irq_table *pf_irq_table = NULL;
+
+	pf_irq_table = (struct dh_pf_irq_table *)table->priv;
+	pf_irq_table->pf_vq_pool ? irq_pool_free(pf_irq_table->pf_vq_pool) : 0;
+	pf_irq_table->pf_async_pool ? irq_pool_free(pf_irq_table->pf_async_pool) :
+									0;
+	pf_irq_table->pf_rdma_pool ? irq_pool_free(pf_irq_table->pf_rdma_pool) : 0;
+}
+
+static int32_t zxdh_get_total_vec(struct dh_core_dev *dev)
+{
+	return ZXDH_VQS_CHANNELS_NUM + ZXDH_ASYNC_CHANNELS_NUM +
+		   ZXDH_RDMA_CHANNELS_NUM;
+}
+
+int32_t dh_pf_irq_table_create(struct dh_core_dev *dev)
+{
+	int32_t total_vec = 0;
+	int32_t err = 0;
+
+	total_vec = zxdh_get_total_vec(dev);
+
+	total_vec = pci_alloc_irq_vectors(dev->pdev, total_vec, total_vec,
+									  PCI_IRQ_MSIX);
+	if (total_vec < 0) {
+		LOG_ERR("pci_alloc_irq_vectors failed: %d\n", total_vec);
+		return total_vec;
+	}
+
+	err = irq_pools_init(dev, ZXDH_VQS_CHANNELS_NUM, ZXDH_ASYNC_CHANNELS_NUM);
+	if (err != 0) {
+		LOG_ERR("irq_pools_init failed: %d\n", err);
+		pci_free_irq_vectors(dev->pdev);
+	}
+
+	return err;
+}
+
+void dh_pf_irq_table_destroy(struct dh_core_dev *dev)
+{
+	struct dh_irq_table *table = &dev->irq_table;
+
+	/* There are cases where IRQs still will be in used when we reaching
+   * to here. Hence, making sure all the irqs are released.
+   */
+	irq_pools_destroy(table);
+	pci_free_irq_vectors(dev->pdev);
+}
+
+struct dh_irq *dh_pf_async_irq_request(struct dh_core_dev *dev)
+{
+	struct dh_irq_table *table = &dev->irq_table;
+	struct dh_pf_irq_table *pf_irq_table;
+
+	pf_irq_table = (struct dh_pf_irq_table *)table->priv;
+
+	return pf_irq_table->pf_async_pool ?
+					 zxdh_get_irq_of_pool(dev, pf_irq_table->pf_async_pool) :
+					 NULL;
+}
+
+/* irq_table API */
+int32_t dh_pf_irq_table_init(struct dh_core_dev *dev)
+{
+	struct dh_irq_table *irq_table;
+	struct dh_pf_irq_table *pf_irq_table = NULL;
+
+	irq_table = &dev->irq_table;
+
+	pf_irq_table = kvzalloc(sizeof(*pf_irq_table), GFP_KERNEL);
+	if (unlikely(pf_irq_table == NULL)) {
+		LOG_ERR("pf_irq_table kvzalloc failed\n");
+		return -ENOMEM;
+	}
+
+	irq_table->priv = pf_irq_table;
+
+	return 0;
 }
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/irq.h b/src/net/drivers/net/ethernet/dinghai/en_pf/irq.h
old mode 100755
new mode 100644
index 6cacd5caf3e0d6eebb032f80c9bc9fbcc4385f5b..264e1641108cf966653c120740431f909fb37288
--- a/src/net/drivers/net/ethernet/dinghai/en_pf/irq.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_pf/irq.h
@@ -1,27 +1,27 @@
-#ifndef __ZXDH_PF_IRQ_H__
-#define __ZXDH_PF_IRQ_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/dinghai_irq.h>
-#include <linux/dinghai/driver.h>
-
-struct dh_irq *dh_pf_async_irq_request(struct dh_core_dev *dev);
-int32_t dh_pf_irq_table_create(struct dh_core_dev *dev);
-void dh_pf_irq_table_destroy(struct dh_core_dev *dev);
-int32_t dh_pf_irq_table_init(struct dh_core_dev *dev);
-
-struct dh_pf_irq_table {
-    struct dh_irq_pool *sf_comp_pool;
-    struct dh_irq_pool *pf_async_pool;
-    struct dh_irq_pool *pf_rdma_pool;
-    struct dh_irq_pool *pf_vq_pool;
-};
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef __ZXDH_PF_IRQ_H__
+#define __ZXDH_PF_IRQ_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/dinghai_irq.h>
+#include <linux/dinghai/driver.h>
+
+struct dh_irq *dh_pf_async_irq_request(struct dh_core_dev *dev);
+int32_t dh_pf_irq_table_create(struct dh_core_dev *dev);
+void dh_pf_irq_table_destroy(struct dh_core_dev *dev);
+int32_t dh_pf_irq_table_init(struct dh_core_dev *dev);
+
+struct dh_pf_irq_table {
+	struct dh_irq_pool *sf_comp_pool;
+	struct dh_irq_pool *pf_async_pool;
+	struct dh_irq_pool *pf_rdma_pool;
+	struct dh_irq_pool *pf_vq_pool;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/msg_func.c b/src/net/drivers/net/ethernet/dinghai/en_pf/msg_func.c
index 7ce3c32088d8c4bb8697c3f1579cffb50bd20baa..beb713419c4c2e9c09b7fcfb90d39c0af6526232 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_pf/msg_func.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_pf/msg_func.c
@@ -8,1466 +8,1547 @@
 #include "eq.h"
 #include "msg_func.h"
 
-#define FUNC_NAME_SIZE_MAX       32
+#define FUNC_NAME_SIZE_MAX 32
 
-typedef uint32_t (*zxdh_vf_msg_func)(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev);
+typedef uint32_t (*zxdh_vf_msg_func)(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									 DPP_PF_INFO_T *pf_info,
+									 struct zxdh_vf_item *vf_item,
+									 struct zxdh_pf_device *pf_dev);
 
-typedef struct
-{
-    zxdh_msg_op_code op_code;
-    uint8_t proc_name[FUNC_NAME_SIZE_MAX];
-    zxdh_vf_msg_func msg_proc;
+typedef struct {
+	zxdh_msg_op_code op_code;
+	uint8_t proc_name[FUNC_NAME_SIZE_MAX];
+	zxdh_vf_msg_func msg_proc;
 } zxdh_vf_msg_proc;
 
 void zxdh_u32_array_print(uint32_t *array, uint16_t size)
 {
-    uint16_t i;
-
-    for (i = 0; i < size; ++i)
-    {
-        printk(KERN_CONT "%u    ", array[i]);
-        if ((i + 1) % 8 == 0)
-        {
-            printk(KERN_CONT "\n");
-        }
-    }
+	uint16_t i;
+
+	for (i = 0; i < size; ++i) {
+		printk(KERN_CONT "%u    ", array[i]);
+		if ((i + 1) % 8 == 0) {
+			printk(KERN_CONT "\n");
+		}
+	}
 }
 EXPORT_SYMBOL(zxdh_u32_array_print);
 
-static void zxdh_vf_link_state_get_proc(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static void zxdh_vf_link_state_get_proc(zxdh_msg_info *msg,
+										zxdh_reps_info *reps,
+										DPP_PF_INFO_T *pf_info,
+										struct zxdh_vf_item *vf_item,
+										struct zxdh_pf_device *pf_dev)
 {
-    int vf_idx = msg->hdr.pcie_id & (0xff);
-    uint32_t dev_link_up_reg = 0;
-    uint8_t vf_link_up = 0;
-
-    if(vf_item->link_forced)
-    {
-        vf_link_up = vf_item->link_up ? 1 : 0;
-    }
-    else
-    {
-        vf_link_up = pf_dev->link_up ? 1 : 0;
-    }
-
-    dev_link_up_reg = ioread32((void __iomem *)(pf_dev->pf_sriov_cap_base + (pf_dev->sriov_bar_size) * vf_idx + ZXDH_DEV_MAC_HIGH_OFFSET));
-    dev_link_up_reg = (dev_link_up_reg & ~(0xFF << 16)) | ((uint32_t)(vf_link_up) << 16);
-    iowrite32(dev_link_up_reg, (void __iomem *)(pf_dev->pf_sriov_cap_base + (pf_dev->sriov_bar_size) * vf_idx + ZXDH_DEV_MAC_HIGH_OFFSET));
-
-    LOG_INFO("vf[%d] link_forced is [%s], link state[%s] update ok.\n", vf_idx, vf_item->link_forced?"TRUE":"FALSE", (vf_link_up==1)?"UP":"DOWN");
-
+	int vf_idx = msg->hdr.pcie_id & (0xff);
+	uint32_t dev_link_up_reg = 0;
+	uint8_t vf_link_up = 0;
+
+	if (vf_item->link_forced) {
+		vf_link_up = vf_item->link_up ? 1 : 0;
+	} else {
+		vf_link_up = pf_dev->link_up ? 1 : 0;
+	}
+
+	dev_link_up_reg =
+			ioread32((void __iomem *)(pf_dev->pf_sriov_cap_base +
+									  (pf_dev->sriov_bar_size) * vf_idx +
+									  ZXDH_DEV_MAC_HIGH_OFFSET));
+	dev_link_up_reg = (dev_link_up_reg & ~(0xFF << 16)) |
+					  ((uint32_t)(vf_link_up) << 16);
+	iowrite32(dev_link_up_reg,
+			  (void __iomem *)(pf_dev->pf_sriov_cap_base +
+							   (pf_dev->sriov_bar_size) * vf_idx +
+							   ZXDH_DEV_MAC_HIGH_OFFSET));
+
+	LOG_INFO("vf[%d] link_forced is [%s], link state[%s] update ok.\n", vf_idx,
+			 vf_item->link_forced ? "TRUE" : "FALSE",
+			 (vf_link_up == 1) ? "UP" : "DOWN");
 }
 
 int32_t zxdh_vf_flush_mac(DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item)
 {
-    int32_t err  = 0;
-    uint8_t  i    = 0;
-    uint8_t *addr = NULL;
+	int32_t err = 0;
+	uint8_t i = 0;
+	uint8_t *addr = NULL;
 
-    /* 删除此VF的所有单播mac地址 */
-    for (i = 0; i < DEV_UNICAST_MAX_NUM; ++i)
-    {
-        addr = vf_item->vf_mac_info.unicast_mac[i];
+	/* 删除此VF的所有单播mac地址 */
+	for (i = 0; i < DEV_UNICAST_MAX_NUM; ++i) {
+		addr = vf_item->vf_mac_info.unicast_mac[i];
 
-        if (!is_zero_ether_addr(addr))   /* mac不全为0 */
-        {
+		/* mac不全为0 */
+		if (!is_zero_ether_addr(addr)) {
 #ifdef MAC_CONFIG_DEBUG
-            LOG_INFO("the deleted unicast mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",\
-                    addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+			LOG_INFO(
+					"the deleted unicast mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
+					addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
 #endif /* MAC_CONFIG_DEBUG */
 
-            err = dpp_del_mac(pf_info, addr);
-            if (err != 0)
-            {
-                LOG_ERR("dpp_del_mac failed\n");
-                return err;
-            }
-        }
-    }
-
-    /* 删除此VF的所有组播mac地址 */
-    for (i = 0; i < DEV_MULTICAST_MAX_NUM; ++i)
-    {
-        addr = vf_item->vf_mac_info.multicast_mac[i];
-
-        if (!is_zero_ether_addr(addr))    /* mac不全为0 */
-        {
+			err = dpp_del_mac(pf_info, addr);
+			if (err != 0) {
+				LOG_ERR("dpp_del_mac failed\n");
+				return err;
+			}
+		}
+	}
+
+	/* 删除此VF的所有组播mac地址 */
+	for (i = 0; i < DEV_MULTICAST_MAX_NUM; ++i) {
+		addr = vf_item->vf_mac_info.multicast_mac[i];
+
+		/* mac不全为0 */
+		if (!is_zero_ether_addr(addr)) {
 #ifdef MAC_CONFIG_DEBUG
-            LOG_INFO("the deleted multicasat mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",\
-                    addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+			LOG_INFO(
+					"the deleted multicasat mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
+					addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
 #endif /* MAC_CONFIG_DEBUG */
 
-            err = dpp_multi_mac_del_member(pf_info, addr);
-            if (err != 0)
-            {
-                LOG_ERR("dpp_multi_mac_del_member failed\n");
-                return err;
-            }
-        }
-    }
+			err = dpp_multi_mac_del_member(pf_info, addr);
+			if (err != 0) {
+				LOG_ERR("dpp_multi_mac_del_member failed\n");
+				return err;
+			}
+		}
+	}
 
-    /* 将vf_mac_info结构体全部清零 */
-    memset(&vf_item->vf_mac_info, 0, sizeof(vf_item->vf_mac_info));
+	/* 将vf_mac_info结构体全部清零 */
+	memset(&vf_item->vf_mac_info, 0, sizeof(vf_item->vf_mac_info));
 
-    return err;
+	return err;
 }
 
-static uint32_t zxdh_vf_port_init(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_port_init(zxdh_msg_info *msg, zxdh_reps_info *reps,
+								  DPP_PF_INFO_T *pf_info,
+								  struct zxdh_vf_item *vf_item,
+								  struct zxdh_pf_device *pf_dev)
 {
-    uint32_t ret = 0;
-    uint8_t mac[6] = {0};
-
-    ret = dpp_vport_create(pf_info);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_vport_create failed, ret: %d\n", ret);
-        return ret;
-    }
-
-    if (msg->vf_init_msg.is_upf)
-    {
-        ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_LAG_ID, 0);
-        if (ret != 0)
-        {
-            LOG_ERR("dpp_egr_port_attr_set panel_id %d failed: %d\n", pf_dev->phy_port, ret);
-            goto err_init;
-        }
-
-        ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_LAG_EN_OFF, 1);
-        if (ret != 0)
-        {
-            LOG_ERR("dpp_egr_port_attr_set hash_search_idx %u failed: %d\n", msg->vf_init_msg.hash_search_idx, ret);
-            goto err_init;
-        }
-    }
-    else
-    {
-        ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_PANEL_ID, pf_dev->phy_port);
-        if (ret != 0)
-        {
-            LOG_ERR("dpp_egr_port_attr_set panel_id %d failed: %d\n", pf_dev->phy_port, ret);
-            goto err_init;
-        }
-    }
-
-    ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_HASH_SEARCH_INDEX, msg->vf_init_msg.hash_search_idx);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set hash_search_idx %u failed: %d\n", msg->vf_init_msg.hash_search_idx, ret);
-        goto err_init;
-    }
-
-    ret = dpp_vport_bond_pf(pf_info);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_vport_bond_pf failed, ret: %d\n", ret);
-        goto err_init;
-    }
-
-    ret = dpp_vport_rss_en_set(pf_info, msg->vf_init_msg.rss_enable);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_vport_rss_en_set failed, ret: %d\n", ret);
-        goto err_init;
-    }
-
-    ret = dpp_vport_hash_funcs_set(pf_info, ZXDH_FUNC_TOP);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_vport_hash_funcs_set failed, ret: %d\n", ret);
-        goto err_init;
-    }
-
-    ret = dpp_rx_flow_hash_set(pf_info, ZXDH_NET_RX_FLOW_HASH_SDFNT);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_rx_flow_hash_set failed, ret: %d\n", ret);
-        goto err_init;
-    }
-
-    ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_VEPA_EN_OFF, (uint32_t)pf_dev->vepa);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set vport(0x%x) %s mode failed: %d\n", msg->hdr.vport, pf_dev->vepa?"vepa":"veb", ret);
-        goto err_init;
-    }
-    LOG_INFO("Initialize vport(0x%x) to %s mode\n", msg->hdr.vport, pf_dev->vepa?"vepa":"veb");
-
-    ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_PORT_BASE_QID, msg->vf_init_msg.base_qid);
-    if (ret != 0)
-    {
-        LOG_ERR("set_base_qid %d failed: %d\n", msg->vf_init_msg.base_qid, ret);
-        goto err_init;
-    }
-
-    ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_SPOOFCHK_EN_OFF, vf_item->spoofchk);
-    if (0 != ret)
-    {
-        LOG_ERR("dpp_egr_port_attr_set spookchk %s failed: %d\n", vf_item->spoofchk? "on":"off", ret);
-        goto err_init;
-    }
-
-    ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_IPV4_TCP_ASSEMBLE, 1);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set tcp assemble failed: %d\n", ret);
-        goto err_init;
-    }
-
-    ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_IPV6_TCP_ASSEMBLE, 1);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set tcp assemble failed: %d\n", ret);
-        goto err_init;
-    }
-
-    ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_IP_CHKSUM, 1);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set rx ip checksum failed: %d\n", ret);
-        goto err_init;
-    }
-
-    ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_TCP_UDP_CHKSUM, 1);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set rx l4 checksum failed: %d\n", ret);
-        goto err_init;
-    }
-
-    ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 1);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set accelerator offload failed: %d\n", ret);
-        goto err_init;
-    }
-
-    ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD, 1);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_egr_port_attr_set vxlan outer ip checksum failed: %d\n", ret);
-        goto err_init;
-    }
-    ret = dpp_vport_vlan_filter_en_set(pf_info, 0);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_vport_vlan_filter_en_set failed, ret: %d\n", ret);
-        goto err_init;
-    }
-
-    ret = dpp_vlan_filter_init(pf_info);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_vlan_filter_init failed: %d\n", ret);
-        goto err_init;
-    }
-
-    ret = zxdh_vf_flush_mac(pf_info, vf_item);
-    if (ret != 0)
-    {
-        goto err_init;
-    }
-
-    ether_addr_copy(mac, vf_item->mac);
-    if (is_zero_ether_addr(mac))
-    {
-        get_random_bytes(mac, 6);
-        mac[0] &= 0xfe;
-        LOG_INFO("vf set random mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-    }
-    LOG_INFO("zxdh_vf_port_init mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-    ret = dpp_add_mac(pf_info, mac);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_add_mac failed, ret: %d\n", ret);
-        return ret;
-    }
-
-    dpp_vport_uc_promisc_set(pf_info, 0);
-    dpp_vport_mc_promisc_set(pf_info, 0);
-
-    ether_addr_copy(vf_item->vf_mac_info.unicast_mac[0], mac);
-    ether_addr_copy(reps->vf_init_msg.mac_addr, mac);
-    reps->vf_init_msg.phy_port = pf_dev->phy_port;
-    reps->vf_init_msg.link_up = pf_dev->link_up;
-    reps->vf_init_msg.speed = pf_dev->speed;
-    reps->vf_init_msg.duplex = pf_dev->duplex;
-    reps->vf_init_msg.autoneg_enable = pf_dev->autoneg_enable;
-    reps->vf_init_msg.sup_link_modes = pf_dev->supported_speed_modes;
-    reps->vf_init_msg.adv_link_modes = pf_dev->advertising_speed_modes;
-
-    zxdh_vf_link_state_get_proc(msg, reps, pf_info, vf_item, pf_dev);
-    vf_item->is_probed = true;
-    return 0;
+	uint32_t ret = 0;
+	uint8_t mac[6] = { 0 };
+
+	ret = dpp_vport_create(pf_info);
+	if (ret != 0) {
+		LOG_ERR("dpp_vport_create failed, ret: %d\n", ret);
+		return ret;
+	}
+
+	ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_PANEL_ID, pf_dev->phy_port);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set panel_id %d failed: %d\n",
+				pf_dev->phy_port, ret);
+		goto err_init;
+	}
+
+	ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_HASH_SEARCH_INDEX,
+								msg->vf_init_msg.hash_search_idx);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set hash_search_idx %u failed: %d\n",
+				msg->vf_init_msg.hash_search_idx, ret);
+		goto err_init;
+	}
+
+	ret = dpp_vport_bond_pf(pf_info);
+	if (ret != 0) {
+		LOG_ERR("dpp_vport_bond_pf failed, ret: %d\n", ret);
+		goto err_init;
+	}
+
+	ret = dpp_vport_rss_en_set(pf_info, msg->vf_init_msg.rss_enable);
+	if (ret != 0) {
+		LOG_ERR("dpp_vport_rss_en_set failed, ret: %d\n", ret);
+		goto err_init;
+	}
+
+	ret = dpp_vport_hash_funcs_set(pf_info, ZXDH_FUNC_TOP);
+	if (ret != 0) {
+		LOG_ERR("dpp_vport_hash_funcs_set failed, ret: %d\n", ret);
+		goto err_init;
+	}
+
+	ret = dpp_rx_flow_hash_set(pf_info, ZXDH_NET_RX_FLOW_HASH_SDFNT);
+	if (ret != 0) {
+		LOG_ERR("dpp_rx_flow_hash_set failed, ret: %d\n", ret);
+		goto err_init;
+	}
+
+	ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_VEPA_EN_OFF,
+								(uint32_t)pf_dev->vepa);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set vport(0x%x) %s mode failed: %d\n",
+				msg->hdr.vport, pf_dev->vepa ? "vepa" : "veb", ret);
+		goto err_init;
+	}
+	LOG_INFO("Initialize vport(0x%x) to %s mode\n", msg->hdr.vport,
+			 pf_dev->vepa ? "vepa" : "veb");
+
+	ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_PORT_BASE_QID,
+								msg->vf_init_msg.base_qid);
+	if (ret != 0) {
+		LOG_ERR("set_base_qid %d failed: %d\n", msg->vf_init_msg.base_qid, ret);
+		goto err_init;
+	}
+
+	ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_SPOOFCHK_EN_OFF,
+								vf_item->spoofchk);
+	if (0 != ret) {
+		LOG_ERR("dpp_egr_port_attr_set spookchk %s failed: %d\n",
+				vf_item->spoofchk ? "on" : "off", ret);
+		goto err_init;
+	}
+
+	ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_IPV4_TCP_ASSEMBLE, 1);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set tcp assemble failed: %d\n", ret);
+		goto err_init;
+	}
+
+	ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_IPV6_TCP_ASSEMBLE, 1);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set tcp assemble failed: %d\n", ret);
+		goto err_init;
+	}
+
+	ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_IP_CHKSUM, 1);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set rx ip checksum failed: %d\n", ret);
+		goto err_init;
+	}
+
+	ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_TCP_UDP_CHKSUM, 1);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set rx l4 checksum failed: %d\n", ret);
+		goto err_init;
+	}
+
+	ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_ACCELERATOR_OFFLOAD_FLAG, 1);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set accelerator offload failed: %d\n", ret);
+		goto err_init;
+	}
+
+	ret = dpp_egr_port_attr_set(pf_info, EGR_FLAG_OUTER_IP_CHECKSUM_OFFLOAD, 1);
+	if (ret != 0) {
+		LOG_ERR("dpp_egr_port_attr_set vxlan outer ip checksum failed: %d\n",
+				ret);
+		goto err_init;
+	}
+	ret = dpp_vport_vlan_filter_en_set(pf_info, 0);
+	if (ret != 0) {
+		LOG_ERR("dpp_vport_vlan_filter_en_set failed, ret: %d\n", ret);
+		goto err_init;
+	}
+
+	ret = dpp_vlan_filter_init(pf_info);
+	if (ret != 0) {
+		LOG_ERR("dpp_vlan_filter_init failed: %d\n", ret);
+		goto err_init;
+	}
+
+	ret = zxdh_vf_flush_mac(pf_info, vf_item);
+	if (ret != 0) {
+		goto err_init;
+	}
+
+	ether_addr_copy(mac, vf_item->mac);
+	if (is_zero_ether_addr(mac)) {
+		get_random_bytes(mac, 6);
+		mac[0] &= 0xfe;
+		LOG_INFO("vf set random mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0],
+				 mac[1], mac[2], mac[3], mac[4], mac[5]);
+	}
+	LOG_INFO("zxdh_vf_port_init mac %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", mac[0],
+			 mac[1], mac[2], mac[3], mac[4], mac[5]);
+	ret = dpp_add_mac(pf_info, mac);
+	if (ret != 0) {
+		LOG_ERR("dpp_add_mac failed, ret: %d\n", ret);
+		return ret;
+	}
+
+	dpp_vport_uc_promisc_set(pf_info, 0);
+	dpp_vport_mc_promisc_set(pf_info, 0);
+
+	ether_addr_copy(vf_item->vf_mac_info.unicast_mac[0], mac);
+	ether_addr_copy(reps->vf_init_msg.mac_addr, mac);
+	reps->vf_init_msg.phy_port = pf_dev->phy_port;
+	reps->vf_init_msg.speed = pf_dev->speed;
+	reps->vf_init_msg.duplex = pf_dev->duplex;
+	reps->vf_init_msg.autoneg_enable = pf_dev->autoneg_enable;
+	reps->vf_init_msg.sup_link_modes = pf_dev->supported_speed_modes;
+	reps->vf_init_msg.adv_link_modes = pf_dev->advertising_speed_modes;
+
+	zxdh_vf_link_state_get_proc(msg, reps, pf_info, vf_item, pf_dev);
+	vf_item->is_probed = true;
+	return 0;
 
 err_init:
-    dpp_vport_delete(pf_info);
-    return ret;
+	dpp_vport_delete(pf_info);
+	return ret;
 }
 
-static uint32_t zxdh_vf_port_uninit(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_port_uninit(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									DPP_PF_INFO_T *pf_info,
+									struct zxdh_vf_item *vf_item,
+									struct zxdh_pf_device *pf_dev)
 {
-    int32_t ret = 0;
-
-    dpp_vport_uc_promisc_set(pf_info, 0);
-    dpp_vport_mc_promisc_set(pf_info, 0);
-
-    ret = zxdh_vf_flush_mac(pf_info, vf_item);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_vf_flush_macf failed, ret: %d\n", ret);
-        return ret;
-    }
-
-    ret = dpp_vport_unbond_pf(pf_info);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_vport_unbond_pf failed, ret: %d\n", ret);
-        return ret;
-    }
-
-    ret = dpp_vport_delete(pf_info);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_vport_delete failed, ret: %d\n", ret);
-        return ret;
-    }
-
-    ret = dpp_vport_unregister(pf_info);
-    if (ret != 0)
-    {
-        LOG_ERR("dpp_vport_unregister failed, ret: %d\n", ret);
-        return ret;
-    }
-
-    vf_item->is_probed = false;
-    return ret;
+	int32_t ret = 0;
+
+	dpp_vport_uc_promisc_set(pf_info, 0);
+	dpp_vport_mc_promisc_set(pf_info, 0);
+
+	ret = zxdh_vf_flush_mac(pf_info, vf_item);
+	if (ret != 0) {
+		LOG_ERR("zxdh_vf_flush_macf failed, ret: %d\n", ret);
+		return ret;
+	}
+
+	ret = dpp_vport_unbond_pf(pf_info);
+	if (ret != 0) {
+		LOG_ERR("dpp_vport_unbond_pf failed, ret: %d\n", ret);
+		return ret;
+	}
+
+	ret = dpp_vport_delete(pf_info);
+	if (ret != 0) {
+		LOG_ERR("dpp_vport_delete failed, ret: %d\n", ret);
+		return ret;
+	}
+
+	ret = dpp_vport_unregister(pf_info);
+	if (ret != 0) {
+		LOG_ERR("dpp_vport_unregister failed, ret: %d\n", ret);
+		return ret;
+	}
+
+	vf_item->is_probed = false;
+	return ret;
 }
 
 void zxdh_vf_item_mac_add(struct zxdh_vf_item *vf_item, uint8_t *mac_addr)
 {
-    uint8_t *addr = NULL;
-    uint8_t i = 0;
-
-    if (is_unicast_ether_addr(mac_addr))
-    {
-        for (i = 1; i < DEV_UNICAST_MAX_NUM; ++i)
-        {
-            addr = vf_item->vf_mac_info.unicast_mac[i];
-            if (is_zero_ether_addr(addr)) /*查询没使用的数组*/
-            {
-                /* 将此mac添加到zxdh_vf_item中 */
-                memcpy(addr, mac_addr, ETH_ALEN);
-                break;
-            }
-        }
-    }
-    else
-    {
-        for (i = 0; i < DEV_MULTICAST_MAX_NUM; ++i)
-        {
-            addr = vf_item->vf_mac_info.multicast_mac[i];
-
-            if (is_zero_ether_addr(addr))
-            {
-                /* 将此mac添加到zxdh_vf_item中 */
-                memcpy(addr, mac_addr, ETH_ALEN);
-                break;
-            }
-        }
-    }
-
-    return;
+	uint8_t *addr = NULL;
+	uint8_t i = 0;
+
+	if (is_unicast_ether_addr(mac_addr)) {
+		for (i = 1; i < DEV_UNICAST_MAX_NUM; ++i) {
+			addr = vf_item->vf_mac_info.unicast_mac[i];
+			/*查询没使用的数组*/
+			if (is_zero_ether_addr(addr)) {
+				/* 将此mac添加到zxdh_vf_item中 */
+				memcpy(addr, mac_addr, ETH_ALEN);
+				break;
+			}
+		}
+	} else {
+		for (i = 0; i < DEV_MULTICAST_MAX_NUM; ++i) {
+			addr = vf_item->vf_mac_info.multicast_mac[i];
+
+			if (is_zero_ether_addr(addr)) {
+				/* 将此mac添加到zxdh_vf_item中 */
+				memcpy(addr, mac_addr, ETH_ALEN);
+				break;
+			}
+		}
+	}
+
+	return;
 }
 
 void zxdh_vf_item_mac_del(struct zxdh_vf_item *vf_item, uint8_t *mac_addr)
 {
-    uint8_t i = 0;
-    uint8_t *addr = NULL;
-
-    if (is_unicast_ether_addr(mac_addr))
-    {
-        for (i = 1; i < DEV_UNICAST_MAX_NUM; ++i)
-        {
-            /* 获取此mac地址 */
-            addr = vf_item->vf_mac_info.unicast_mac[i];
-
-            if (ether_addr_equal(addr, mac_addr))/* 查询到此mac */
-            {
+	uint8_t i = 0;
+	uint8_t *addr = NULL;
+
+	if (is_unicast_ether_addr(mac_addr)) {
+		for (i = 1; i < DEV_UNICAST_MAX_NUM; ++i) {
+			/* 获取此mac地址 */
+			addr = vf_item->vf_mac_info.unicast_mac[i];
+
+			/* 查询到此mac */
+			if (ether_addr_equal(addr, mac_addr)) {
 #ifdef MAC_CONFIG_DEBUG
-                LOG_INFO("the mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", \
-                  addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+				LOG_INFO("the mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", addr[0],
+						 addr[1], addr[2], addr[3], addr[4], addr[5]);
 #endif /* MAC_CONFIG_DEBUG */
 
-                /* 在地址数组中将此mac清空*/
-                memset(addr, 0, ETH_ALEN);
-                break;
-            }
-        }
-    }
-    else
-    {
-        for (i = 0; i < DEV_MULTICAST_MAX_NUM; ++i)
-        {
-            addr = vf_item->vf_mac_info.multicast_mac[i];
-
-            if (ether_addr_equal(addr, mac_addr))/* 查询到此mac */
-            {
+				/* 在地址数组中将此mac清空*/
+				memset(addr, 0, ETH_ALEN);
+				break;
+			}
+		}
+	} else {
+		for (i = 0; i < DEV_MULTICAST_MAX_NUM; ++i) {
+			addr = vf_item->vf_mac_info.multicast_mac[i];
+
+			/* 查询到此mac */
+			if (ether_addr_equal(addr, mac_addr)) {
 #ifdef MAC_CONFIG_DEBUG
-                LOG_INFO("the mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
-                  addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+				LOG_INFO("the mac is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", addr[0],
+						 addr[1], addr[2], addr[3], addr[4], addr[5]);
 #endif /* MAC_CONFIG_DEBUG */
 
-                /* 在地址数组中将此mac清空 */
-                memset(addr, 0, ETH_ALEN);
-                break;
-            }
-        }
-    }
+				/* 在地址数组中将此mac清空 */
+				memset(addr, 0, ETH_ALEN);
+				break;
+			}
+		}
+	}
 
-    return;
+	return;
 }
 
-static uint32_t zxdh_vf_mac_add(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_mac_add(zxdh_msg_info *msg, zxdh_reps_info *reps,
+								DPP_PF_INFO_T *pf_info,
+								struct zxdh_vf_item *vf_item,
+								struct zxdh_pf_device *pf_dev)
 {
-    int32_t ret = 0;
-
-    if (ether_addr_equal(vf_item->mac, msg->mac_addr_set_msg.mac_addr) || (vf_item->pf_set_mac && vf_item->trusted) || (vf_item->pf_set_mac == false))
-    {
-        ether_addr_copy(vf_item->vf_mac_info.unicast_mac[0], msg->mac_addr_set_msg.mac_addr);
-        ether_addr_copy(vf_item->mac, msg->mac_addr_set_msg.mac_addr);
-        ret = dpp_add_mac(pf_info, msg->mac_addr_set_msg.mac_addr);
-        if (ret != 0)
-        {
-            LOG_ERR("dpp_add_mac failed, ret: %d\n", ret);
-            return ret;
-        }
-    }
-    else
-    {
-        LOG_ERR("zxdh_vf_mac_add failed, vf not Trusted\n");
-        return -1;
-    }
-
-    return ret;
+	int32_t ret = 0;
+
+	if (ether_addr_equal(vf_item->mac, msg->mac_addr_set_msg.mac_addr) ||
+		(vf_item->pf_set_mac && vf_item->trusted) ||
+		(vf_item->pf_set_mac == false)) {
+		ether_addr_copy(vf_item->vf_mac_info.unicast_mac[0],
+						msg->mac_addr_set_msg.mac_addr);
+		ether_addr_copy(vf_item->mac, msg->mac_addr_set_msg.mac_addr);
+		ret = dpp_add_mac(pf_info, msg->mac_addr_set_msg.mac_addr);
+		if (ret != 0) {
+			LOG_ERR("dpp_add_mac failed, ret: %d\n", ret);
+			return ret;
+		}
+	} else {
+		LOG_ERR("zxdh_vf_mac_add failed, vf not Trusted\n");
+		return -1;
+	}
+
+	return ret;
 }
 
-static uint32_t zxdh_vf_mac_del(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_mac_del(zxdh_msg_info *msg, zxdh_reps_info *reps,
+								DPP_PF_INFO_T *pf_info,
+								struct zxdh_vf_item *vf_item,
+								struct zxdh_pf_device *pf_dev)
 {
-    int32_t ret = 0;
-    uint8_t i = 0;
-    uint8_t *addr = NULL;
-
-    if (msg->mac_addr_set_msg.mac_flag == true)
-    {
-        if ((vf_item->pf_set_mac && vf_item->trusted) || (vf_item->pf_set_mac == false))
-        {
-            eth_zero_addr(vf_item->mac);
-            ret = dpp_del_mac(pf_info, msg->mac_addr_set_msg.mac_addr);
-            if (ret != 0)
-            {
-                LOG_ERR("dpp_del_mac failed, ret: %d\n", ret);
-                return ret;
-            }
-        }
-        else
-        {
-            LOG_ERR("zxdh_vf_mac_del failed, vf not Trusted\n");
-            return -1;
-        }
-    }
-
-    if(msg->mac_addr_set_msg.mac_addr == vf_item->vf_mac_info.unicast_mac[0])
-    {
-        for (i = 1; i < DEV_UNICAST_MAX_NUM; ++i)
-        {
-            addr = vf_item->vf_mac_info.unicast_mac[i];
-            if (is_zero_ether_addr(addr))
-            {
-                memcpy(addr, vf_item->vf_mac_info.unicast_mac[0], ETH_ALEN);
-                break;
-            }
-        }
-    }
-
-    return ret;
+	int32_t ret = 0;
+	uint8_t i = 0;
+	uint8_t *addr = NULL;
+
+	if (msg->mac_addr_set_msg.mac_flag == true) {
+		if ((vf_item->pf_set_mac && vf_item->trusted) ||
+			(vf_item->pf_set_mac == false)) {
+			eth_zero_addr(vf_item->mac);
+			ret = dpp_del_mac(pf_info, msg->mac_addr_set_msg.mac_addr);
+			if (ret != 0) {
+				LOG_ERR("dpp_del_mac failed, ret: %d\n", ret);
+				return ret;
+			}
+		} else {
+			LOG_ERR("zxdh_vf_mac_del failed, vf not Trusted\n");
+			return -1;
+		}
+	}
+
+	if (msg->mac_addr_set_msg.mac_addr == vf_item->vf_mac_info.unicast_mac[0]) {
+		for (i = 1; i < DEV_UNICAST_MAX_NUM; ++i) {
+			addr = vf_item->vf_mac_info.unicast_mac[i];
+			if (is_zero_ether_addr(addr)) {
+				memcpy(addr, vf_item->vf_mac_info.unicast_mac[0], ETH_ALEN);
+				break;
+			}
+		}
+	}
+
+	return ret;
 }
 
-static uint32_t zxdh_vf_filter_mac_add(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_filter_mac_add(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									   DPP_PF_INFO_T *pf_info,
+									   struct zxdh_vf_item *vf_item,
+									   struct zxdh_pf_device *pf_dev)
 {
-    uint32_t err = 0;
+	uint8_t err = 0;
 
 #ifdef MAC_CONFIG_DEBUG
-    /* 将获取到的mac地址配置到NP中 */
-    LOG_INFO("msg->mac_addr_set_msg.mac_addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", \
-            msg->mac_addr_set_msg.mac_addr[0], msg->mac_addr_set_msg.mac_addr[1], \
-            msg->mac_addr_set_msg.mac_addr[2], msg->mac_addr_set_msg.mac_addr[3], \
-            msg->mac_addr_set_msg.mac_addr[4], msg->mac_addr_set_msg.mac_addr[5]);
+	/* 将获取到的mac地址配置到NP中 */
+	LOG_INFO(
+			"msg->mac_addr_set_msg.mac_addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
+			msg->mac_addr_set_msg.mac_addr[0],
+			msg->mac_addr_set_msg.mac_addr[1],
+			msg->mac_addr_set_msg.mac_addr[2],
+			msg->mac_addr_set_msg.mac_addr[3],
+			msg->mac_addr_set_msg.mac_addr[4],
+			msg->mac_addr_set_msg.mac_addr[5]);
 #endif /*MAC_CONFIG_DEBUG */
 
-    err = dpp_add_mac(pf_info, msg->mac_addr_set_msg.mac_addr);
-    if (err != 0)
-    {
-        LOG_ERR("dpp_add_mac failed \n");
-        return err;
-    }
+	err = dpp_add_mac(pf_info, msg->mac_addr_set_msg.mac_addr);
+	if (err != 0) {
+		LOG_ERR("dpp_add_mac failed \n");
+		return err;
+	}
 
-    /* 将此mac地址添加到zxdh_vf_item */
-    zxdh_vf_item_mac_add(vf_item, msg->mac_addr_set_msg.mac_addr);
+	/* 将此mac地址添加到zxdh_vf_item */
+	zxdh_vf_item_mac_add(vf_item, msg->mac_addr_set_msg.mac_addr);
 
-    return err;
+	return err;
 }
 
-static uint32_t zxdh_vf_filter_mac_del(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_filter_mac_del(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									   DPP_PF_INFO_T *pf_info,
+									   struct zxdh_vf_item *vf_item,
+									   struct zxdh_pf_device *pf_dev)
 {
-    uint32_t err = 0;
+	uint8_t err = 0;
 
 #ifdef MAC_CONFIG_DEBUG
-    /* 将获取到的mac地址从NP中删除 */
-    LOG_INFO("msg->mac_addr_set_msg.mac_addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", \
-            msg->mac_addr_set_msg.mac_addr[0], msg->mac_addr_set_msg.mac_addr[1], \
-            msg->mac_addr_set_msg.mac_addr[2], msg->mac_addr_set_msg.mac_addr[3], \
-            msg->mac_addr_set_msg.mac_addr[4], msg->mac_addr_set_msg.mac_addr[5]);
+	/* 将获取到的mac地址从NP中删除 */
+	LOG_INFO(
+			"msg->mac_addr_set_msg.mac_addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
+			msg->mac_addr_set_msg.mac_addr[0],
+			msg->mac_addr_set_msg.mac_addr[1],
+			msg->mac_addr_set_msg.mac_addr[2],
+			msg->mac_addr_set_msg.mac_addr[3],
+			msg->mac_addr_set_msg.mac_addr[4],
+			msg->mac_addr_set_msg.mac_addr[5]);
 #endif /* MAC_CONFIG_DEBUG */
 
-    err = dpp_del_mac(pf_info, msg->mac_addr_set_msg.mac_addr);
-    if (err != 0)
-    {
-        LOG_ERR("dpp_mac_del failed\n");
-        return err;
-    }
+	err = dpp_del_mac(pf_info, msg->mac_addr_set_msg.mac_addr);
+	if (err != 0) {
+		LOG_ERR("dpp_mac_del failed\n");
+		return err;
+	}
 
-    /* 将此mac从zxdh_vf_item中删除 */
-    zxdh_vf_item_mac_del(vf_item, msg->mac_addr_set_msg.mac_addr);
+	/* 将此mac从zxdh_vf_item中删除 */
+	zxdh_vf_item_mac_del(vf_item, msg->mac_addr_set_msg.mac_addr);
 
-    return err;
+	return err;
 }
 
-static uint32_t zxdh_vf_multi_mac_add(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_multi_mac_add(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									  DPP_PF_INFO_T *pf_info,
+									  struct zxdh_vf_item *vf_item,
+									  struct zxdh_pf_device *pf_dev)
 {
-    uint32_t err = 0;
+	uint32_t err = 0;
 
 #ifdef MAC_CONFIG_DEBUG
-    /* 将此mac地址添加到np中 */
-    LOG_INFO("msg->mac_addr_set_msg.mac_addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", \
-            msg->mac_addr_set_msg.mac_addr[0], msg->mac_addr_set_msg.mac_addr[1], \
-            msg->mac_addr_set_msg.mac_addr[2], msg->mac_addr_set_msg.mac_addr[3], \
-            msg->mac_addr_set_msg.mac_addr[4], msg->mac_addr_set_msg.mac_addr[5]);
+	/* 将此mac地址添加到np中 */
+	LOG_INFO(
+			"msg->mac_addr_set_msg.mac_addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
+			msg->mac_addr_set_msg.mac_addr[0],
+			msg->mac_addr_set_msg.mac_addr[1],
+			msg->mac_addr_set_msg.mac_addr[2],
+			msg->mac_addr_set_msg.mac_addr[3],
+			msg->mac_addr_set_msg.mac_addr[4],
+			msg->mac_addr_set_msg.mac_addr[5]);
 #endif /* MAC_CONFIG_DEBUG*/
 
-    err = dpp_multi_mac_add_member(pf_info, msg->mac_addr_set_msg.mac_addr);
-    if (err != 0)
-    {
-        if (err == DPP_RC_TABLE_RANGE_INVALID)
-        {
-            LOG_ERR("multicast mac is beyond 32\n");
-            return DPP_RC_TABLE_RANGE_INVALID;
-        }
-        LOG_ERR("dpp_multi_mac_add_member failed %d\n", err);
-        return err;
-    }
-
-    /* 将此mac添加到zxdh_vf_item中 */
-    zxdh_vf_item_mac_add(vf_item, msg->mac_addr_set_msg.mac_addr);
-
-    return err;
+	err = dpp_multi_mac_add_member(pf_info, msg->mac_addr_set_msg.mac_addr);
+	if (err != 0) {
+		LOG_ERR("dpp_multi_mac_add_member failed %d\n", err);
+		return err;
+	}
+
+	/* 将此mac添加到zxdh_vf_item中 */
+	zxdh_vf_item_mac_add(vf_item, msg->mac_addr_set_msg.mac_addr);
+
+	return err;
 }
 
-static uint32_t zxdh_vf_multi_mac_del(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_multi_mac_del(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									  DPP_PF_INFO_T *pf_info,
+									  struct zxdh_vf_item *vf_item,
+									  struct zxdh_pf_device *pf_dev)
 {
-    uint32_t err = 0;
+	uint32_t err = 0;
 
 #ifdef MAC_CONFIG_DEBUG
-    LOG_INFO("msg->mac_addr_set_msg.mac_addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", \
-            msg->mac_addr_set_msg.mac_addr[0], msg->mac_addr_set_msg.mac_addr[1], \
-            msg->mac_addr_set_msg.mac_addr[2], msg->mac_addr_set_msg.mac_addr[3], \
-            msg->mac_addr_set_msg.mac_addr[4], msg->mac_addr_set_msg.mac_addr[5]);
+	LOG_INFO(
+			"msg->mac_addr_set_msg.mac_addr is %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
+			msg->mac_addr_set_msg.mac_addr[0],
+			msg->mac_addr_set_msg.mac_addr[1],
+			msg->mac_addr_set_msg.mac_addr[2],
+			msg->mac_addr_set_msg.mac_addr[3],
+			msg->mac_addr_set_msg.mac_addr[4],
+			msg->mac_addr_set_msg.mac_addr[5]);
 #endif /* MAC_CONFIG_DEBUG */
 
-    /* 将此组播mac地址从np中删除 */
-    err = dpp_multi_mac_del_member(pf_info, msg->mac_addr_set_msg.mac_addr);
-    if (err != 0)
-    {
-        LOG_INFO("dpp_multi_mac_del_member failed %d\n", err);
-        return err;
-    }
+	/* 将此组播mac地址从np中删除 */
+	err = dpp_multi_mac_del_member(pf_info, msg->mac_addr_set_msg.mac_addr);
+	if (err != 0) {
+		LOG_INFO("dpp_multi_mac_del_member failed %d\n", err);
+		return err;
+	}
 
-    /* 将此mac从zxdh_vf_item中删除 */
-    zxdh_vf_item_mac_del(vf_item, msg->mac_addr_set_msg.mac_addr);
+	/* 将此mac从zxdh_vf_item中删除 */
+	zxdh_vf_item_mac_del(vf_item, msg->mac_addr_set_msg.mac_addr);
 
-    return err;
+	return err;
 }
 
-static uint32_t zxdh_vf_all_mac_add(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_all_mac_add(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									DPP_PF_INFO_T *pf_info,
+									struct zxdh_vf_item *vf_item,
+									struct zxdh_pf_device *pf_dev)
 {
-    /* 配置组播mac*/
-    if (!is_unicast_ether_addr(msg->mac_addr_set_msg.mac_addr))
-    {
-        return zxdh_vf_multi_mac_add(msg, reps, pf_info, vf_item, pf_dev);
-    }
-
-    /* 配置本机mac*/
-    if (msg->mac_addr_set_msg.filter_flag == UNFILTER_MAC)
-    {
-        return zxdh_vf_mac_add(msg, reps, pf_info, vf_item, pf_dev);
-    }
-
-    /* 配置过滤用的单播mac*/
-    return zxdh_vf_filter_mac_add(msg, reps, pf_info, vf_item, pf_dev);
+	/* 配置组播mac*/
+	if (!is_unicast_ether_addr(msg->mac_addr_set_msg.mac_addr)) {
+		return zxdh_vf_multi_mac_add(msg, reps, pf_info, vf_item, pf_dev);
+	}
+
+	/* 配置本机mac*/
+	if (msg->mac_addr_set_msg.filter_flag == UNFILTER_MAC) {
+		return zxdh_vf_mac_add(msg, reps, pf_info, vf_item, pf_dev);
+	}
+
+	/* 配置过滤用的单播mac*/
+	return zxdh_vf_filter_mac_add(msg, reps, pf_info, vf_item, pf_dev);
 }
 
-static uint32_t zxdh_vf_all_mac_del(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_all_mac_del(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									DPP_PF_INFO_T *pf_info,
+									struct zxdh_vf_item *vf_item,
+									struct zxdh_pf_device *pf_dev)
 {
-    /* 删除组播mac */
-    if (!is_unicast_ether_addr(msg->mac_addr_set_msg.mac_addr))
-    {
-        return zxdh_vf_multi_mac_del(msg, reps, pf_info, vf_item, pf_dev);
-    }
-
-    /* 删除本机mac */
-    if (msg->mac_addr_set_msg.filter_flag == UNFILTER_MAC)
-    {
-        return zxdh_vf_mac_del(msg, reps, pf_info, vf_item, pf_dev);
-    }
-
-    /* 删除过滤用的单播mac*/
-    return zxdh_vf_filter_mac_del(msg, reps, pf_info, vf_item, pf_dev);
+	/* 删除组播mac */
+	if (!is_unicast_ether_addr(msg->mac_addr_set_msg.mac_addr)) {
+		return zxdh_vf_multi_mac_del(msg, reps, pf_info, vf_item, pf_dev);
+	}
+
+	/* 删除本机mac */
+	if (msg->mac_addr_set_msg.filter_flag == UNFILTER_MAC) {
+		return zxdh_vf_mac_del(msg, reps, pf_info, vf_item, pf_dev);
+	}
+
+	/* 删除过滤用的单播mac*/
+	return zxdh_vf_filter_mac_del(msg, reps, pf_info, vf_item, pf_dev);
 }
 
-static uint32_t zxdh_vf_ipv6_mac_add(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_all_ipv6_mac_add(zxdh_msg_info *msg,
+										 zxdh_reps_info *reps,
+										 DPP_PF_INFO_T *pf_info,
+										 struct zxdh_vf_item *vf_item,
+										 struct zxdh_pf_device *pf_dev)
 {
-    uint32_t err = 0;
-
-    spin_lock_bh(&pf_dev->vf_ip6mac_lock);
-
-    err = zxdh_vf_multi_mac_add(msg, reps, pf_info, vf_item, pf_dev);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_vf_multi_mac_add failed\n");
-    }
-
-    spin_unlock_bh(&pf_dev->vf_ip6mac_lock);
-
-    return err;
+	uint32_t err = 1;
+	int32_t i = 0;
+	MAC_VPORT_INFO *multicast_mac_arry = NULL;
+	uint32_t current_multicast_num = 0;
+
+	/* 开辟组播数组*/
+	multicast_mac_arry = (MAC_VPORT_INFO *)kzalloc(
+			sizeof(MAC_VPORT_INFO) * MULTICAST_MAX_NUM, GFP_KERNEL);
+	if (multicast_mac_arry == NULL) {
+		LOG_ERR("kzalloc multicast_mac_arry failed\n");
+		return err;
+	}
+
+	/* 从NP中dump所有组播mac地址、总数量*/
+	err = dpp_multicast_mac_dump(pf_info, multicast_mac_arry,
+								 &current_multicast_num);
+	if (err != 0) {
+		LOG_ERR("dpp_multicast_mac_dump failed\n");
+		goto out;
+	}
+
+	/* 判断NP中是否已经存储此多播MAC */
+	for (i = 0; i < current_multicast_num; ++i) {
+		if (memcmp(multicast_mac_arry[i].addr, msg->ipv6_mac_addr_msg.mac_addr,
+				   ETH_ALEN) == 0) {
+			LOG_ERR("Multicast MAC Address: %pM Exist, can't add!!\n",
+					multicast_mac_arry[i].addr);
+			err = 0;
+			goto out;
+		}
+	}
+
+	/* 判断目前NP中所配置mac地址数量是否超过上限*/
+	if (current_multicast_num >= DEV_MULTICAST_MAX_NUM) {
+		LOG_ERR("curr_multicast_num is beyond maximum, can't add!!\n");
+		err = ENOSPC;
+		goto out;
+	}
+
+	err = zxdh_vf_multi_mac_add(msg, reps, pf_info, vf_item, pf_dev);
+	if (err != 0) {
+		LOG_ERR("zxdh_vf_multi_mac_add failed\n");
+	}
+out:
+	if (multicast_mac_arry != NULL) {
+		kfree(multicast_mac_arry);
+	}
+
+	return err;
 }
 
-static uint32_t zxdh_vf_ipv6_mac_del(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_all_ipv6_mac_del(zxdh_msg_info *msg,
+										 zxdh_reps_info *reps,
+										 DPP_PF_INFO_T *pf_info,
+										 struct zxdh_vf_item *vf_item,
+										 struct zxdh_pf_device *pf_dev)
 {
-    uint32_t err = 0;
-
-    spin_lock_bh(&pf_dev->vf_ip6mac_lock);
-
-    err = zxdh_vf_multi_mac_del(msg, reps, pf_info, vf_item, pf_dev);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_vf_multi_mac_del failed\n");
-    }
-
-    spin_unlock_bh(&pf_dev->vf_ip6mac_lock);
-
-    return err;
+	uint32_t err = 1;
+	int32_t i = 0;
+	MAC_VPORT_INFO *multicast_mac_arry = NULL;
+	uint32_t current_multicast_num = 0;
+
+	/* 开辟组播数组*/
+	multicast_mac_arry = (MAC_VPORT_INFO *)kzalloc(
+			sizeof(MAC_VPORT_INFO) * MULTICAST_MAX_NUM, GFP_KERNEL);
+	if (multicast_mac_arry == NULL) {
+		LOG_ERR("kzalloc multicast_mac_arry failed\n");
+		return err;
+	}
+
+	/* 从NP中dump所有组播mac地址、总数量*/
+	err = dpp_multicast_mac_dump(pf_info, multicast_mac_arry,
+								 &current_multicast_num);
+	if (err != 0) {
+		LOG_ERR("dpp_multicast_mac_dump failed\n");
+		goto out;
+	}
+
+	/* 判断NP中是否已经删除此多播MAC */
+	for (i = 0; i < current_multicast_num; ++i) {
+		if (memcmp(multicast_mac_arry[i].addr, msg->ipv6_mac_addr_msg.mac_addr,
+				   ETH_ALEN) != 0) {
+			LOG_ERR("Multicast MAC Address: %pM don't Exist, can't delete!!\n",
+					multicast_mac_arry[i].addr);
+			err = 0;
+			goto out;
+		}
+	}
+
+	/* 判断目前NP中所配置mac地址数量是否小于0 */
+	if (current_multicast_num <= 0) {
+		LOG_ERR("curr_multicast_num is less than 0\n");
+		err = ENOENT;
+		goto out;
+	}
+
+	err = zxdh_vf_multi_mac_del(msg, reps, pf_info, vf_item, pf_dev);
+	if (err != 0) {
+		LOG_ERR("zxdh_vf_multi_mac_del failed\n");
+	}
+out:
+	if (multicast_mac_arry != NULL) {
+		kfree(multicast_mac_arry);
+	}
+
+	return err;
 }
 
-static uint32_t zxdh_vf_mac_get(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_mac_get(zxdh_msg_info *msg, zxdh_reps_info *reps,
+								DPP_PF_INFO_T *pf_info,
+								struct zxdh_vf_item *vf_item,
+								struct zxdh_pf_device *pf_dev)
 {
-    ether_addr_copy(reps->vf_mac_addr_get_msg.mac_addr, vf_item->mac);
-    return 0;
+	ether_addr_copy(reps->vf_mac_addr_get_msg.mac_addr, vf_item->mac);
+	return 0;
 }
 
-static uint32_t zxdh_vf_rss_state_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_rss_state_set(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									  DPP_PF_INFO_T *pf_info,
+									  struct zxdh_vf_item *vf_item,
+									  struct zxdh_pf_device *pf_dev)
 {
-    return dpp_vport_rss_en_set(pf_info, msg->rss_enable_msg.rss_enable);
+	return dpp_vport_rss_en_set(pf_info, msg->rss_enable_msg.rss_enable);
 }
 
-static uint32_t zxdh_vf_rxfh_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_rxfh_set(zxdh_msg_info *msg, zxdh_reps_info *reps,
+								 DPP_PF_INFO_T *pf_info,
+								 struct zxdh_vf_item *vf_item,
+								 struct zxdh_pf_device *pf_dev)
 {
-    return dpp_rxfh_set(pf_info, msg->rxfh_set_msg.queue_map, ZXDH_INDIR_RQT_SIZE);
+	return dpp_rxfh_set(pf_info, msg->rxfh_set_msg.queue_map,
+						ZXDH_INDIR_RQT_SIZE);
 }
 
-static uint32_t zxdh_vf_rxfh_get(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_rxfh_get(zxdh_msg_info *msg, zxdh_reps_info *reps,
+								 DPP_PF_INFO_T *pf_info,
+								 struct zxdh_vf_item *vf_item,
+								 struct zxdh_pf_device *pf_dev)
 {
-    uint32_t err = 0;
+	uint32_t queue_map[ZXDH_INDIR_RQT_SIZE] = { 0 };
+	uint32_t err = 0;
+
+	err = dpp_rxfh_get(pf_info, queue_map, ZXDH_INDIR_RQT_SIZE);
+	if (err != 0) {
+		LOG_ERR("dpp_rxfh_get failed: %d\n", err);
+		return err;
+	}
 
-    err = dpp_rxfh_get(pf_info, reps->rxfh_get_msg.queue_map, ZXDH_INDIR_RQT_SIZE);
-    if (err != 0)
-    {
-        LOG_ERR("dpp_rxfh_get failed: %d\n", err);
-        return err;
-    }
+	LOG_DEBUG("*******vf_queue_map*******\n");
+	zxdh_u32_array_print(queue_map, ZXDH_INDIR_RQT_SIZE);
 
-    return 0;
+	return 0;
 }
 
-static uint32_t zxdh_vf_rxfh_del(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_rxfh_del(zxdh_msg_info *msg, zxdh_reps_info *reps,
+								 DPP_PF_INFO_T *pf_info,
+								 struct zxdh_vf_item *vf_item,
+								 struct zxdh_pf_device *pf_dev)
 {
-    return dpp_rxfh_del(pf_info);
+	return dpp_rxfh_del(pf_info);
 }
 
-static uint32_t zxdh_vf_thash_key_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_thash_key_set(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									  DPP_PF_INFO_T *pf_info,
+									  struct zxdh_vf_item *vf_item,
+									  struct zxdh_pf_device *pf_dev)
 {
-    return dpp_thash_key_set(pf_info, msg->thash_key_set_msg.key_map, ZXDH_NET_HASH_KEY_SIZE);
+	return dpp_thash_key_set(pf_info, msg->thash_key_set_msg.key_map,
+							 ZXDH_NET_HASH_KEY_SIZE);
 }
 
-static uint32_t zxdh_vf_thash_key_get(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_thash_key_get(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									  DPP_PF_INFO_T *pf_info,
+									  struct zxdh_vf_item *vf_item,
+									  struct zxdh_pf_device *pf_dev)
 {
-    return dpp_thash_key_get(pf_info, reps->thash_key_set_msg.key_map, ZXDH_NET_HASH_KEY_SIZE);
+	return dpp_thash_key_get(pf_info, reps->thash_key_set_msg.key_map,
+							 ZXDH_NET_HASH_KEY_SIZE);
 }
 
-static uint32_t zxdh_vf_hash_funcs_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_hash_funcs_set(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									   DPP_PF_INFO_T *pf_info,
+									   struct zxdh_vf_item *vf_item,
+									   struct zxdh_pf_device *pf_dev)
 {
-    return dpp_vport_hash_funcs_set(pf_info, msg->hfunc_set_msg.func);
+	return dpp_vport_hash_funcs_set(pf_info, msg->hfunc_set_msg.func);
 }
 
-static uint32_t zxdh_vf_rx_flow_hash_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_rx_flow_hash_set(zxdh_msg_info *msg,
+										 zxdh_reps_info *reps,
+										 DPP_PF_INFO_T *pf_info,
+										 struct zxdh_vf_item *vf_item,
+										 struct zxdh_pf_device *pf_dev)
 {
-    return dpp_rx_flow_hash_set(pf_info, msg->rx_flow_hash_set_msg.hash_mode);
+	return dpp_rx_flow_hash_set(pf_info, msg->rx_flow_hash_set_msg.hash_mode);
 }
 
-static uint32_t zxdh_vf_vlan_strip_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_vlan_strip_set(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									   DPP_PF_INFO_T *pf_info,
+									   struct zxdh_vf_item *vf_item,
+									   struct zxdh_pf_device *pf_dev)
 {
-    if (msg->vlan_strip_msg.flag == VLAN_STRIP_MSG_TYPE)
-    {
-        return dpp_vport_vlan_strip_set(pf_info, msg->vlan_strip_msg.enable);
-    }
-    else
-    {
-        return dpp_vport_vlan_qinq_en_set(pf_info, msg->vlan_strip_msg.enable);
-    }
+	if (msg->vlan_strip_msg.flag == VLAN_STRIP_MSG_TYPE) {
+		return dpp_vport_vlan_strip_set(pf_info, msg->vlan_strip_msg.enable);
+	} else {
+		return dpp_vport_vlan_qinq_en_set(pf_info, msg->vlan_strip_msg.enable);
+	}
 }
 
-static uint32_t zxdh_vf_qinq_tpid_cfg(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_qinq_tpid_cfg(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									  DPP_PF_INFO_T *pf_info,
+									  struct zxdh_vf_item *vf_item,
+									  struct zxdh_pf_device *pf_dev)
 {
-    return dpp_egr_port_attr_set(pf_info, EGR_FLAG_TPID, msg->tpid_cfg_msg.tpid);
+	return dpp_egr_port_attr_set(pf_info, EGR_FLAG_TPID,
+								 msg->tpid_cfg_msg.tpid);
 }
 
-static uint32_t zxdh_vf_rx_flow_hash_get(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_rx_flow_hash_get(zxdh_msg_info *msg,
+										 zxdh_reps_info *reps,
+										 DPP_PF_INFO_T *pf_info,
+										 struct zxdh_vf_item *vf_item,
+										 struct zxdh_pf_device *pf_dev)
 {
-    return dpp_rx_flow_hash_get(pf_info, &reps->rx_flow_hash_set_msg.hash_mode);
+	return dpp_rx_flow_hash_get(pf_info, &reps->rx_flow_hash_set_msg.hash_mode);
 }
 
-static uint32_t zxdh_vf_port_attrs_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_port_attrs_set(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									   DPP_PF_INFO_T *pf_info,
+									   struct zxdh_vf_item *vf_item,
+									   struct zxdh_pf_device *pf_dev)
 {
-    if (msg->port_attr_set_msg.mode == EGR_FLAG_TCP_UDP_CHKSUM)
-    {
-        dpp_egr_port_attr_set(pf_info, EGR_FLAG_IP_CHKSUM, msg->port_attr_set_msg.value);
-    }
+	if (msg->port_attr_set_msg.mode == EGR_FLAG_TCP_UDP_CHKSUM) {
+		dpp_egr_port_attr_set(pf_info, EGR_FLAG_IP_CHKSUM,
+							  msg->port_attr_set_msg.value);
+	}
 
-    return dpp_egr_port_attr_set(pf_info, msg->port_attr_set_msg.mode, msg->port_attr_set_msg.value);
+	return dpp_egr_port_attr_set(pf_info, msg->port_attr_set_msg.mode,
+								 msg->port_attr_set_msg.value);
 }
 
-static uint32_t zxdh_vf_port_attrs_get(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_port_attrs_get(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									   DPP_PF_INFO_T *pf_info,
+									   struct zxdh_vf_item *vf_item,
+									   struct zxdh_pf_device *pf_dev)
 {
-    return dpp_egr_port_attr_get(pf_info, &reps->port_attr_get_msg.port_attr_entry);
+	return dpp_egr_port_attr_get(pf_info,
+								 &reps->port_attr_get_msg.port_attr_entry);
 }
 
-static uint32_t zxdh_vf_promisc_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_promisc_set(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									DPP_PF_INFO_T *pf_info,
+									struct zxdh_vf_item *vf_item,
+									struct zxdh_pf_device *pf_dev)
 {
-    uint32_t err = 0;
-
-    if (!vf_item->trusted)
-    {
-        LOG_ERR("vf untrusted!\n");
-        return 0;
-    }
-
-    if (msg->promisc_set_msg.mode == ZXDH_PROMISC_MODE)
-    {
-        LOG_INFO("PROMISC_EN_SET: %d", msg->promisc_set_msg.value);
-        err = dpp_vport_uc_promisc_set(pf_info, msg->promisc_set_msg.value);
-        if (err != 0)
-        {
-            LOG_ERR("dpp_vport_uc_promisc_set failed: %d\n", err);
-            return err;
-        }
-        if (msg->promisc_set_msg.mc_follow != 0)
-        {
-            LOG_DEBUG("allmulti_follow\n");
-            err = dpp_vport_mc_promisc_set(pf_info, msg->promisc_set_msg.value);
-            if (err != 0)
-            {
-                LOG_ERR("dpp_vport_mc_promisc_set failed: %d\n", err);
-                return err;
-            }
-        }
-        vf_item->promisc = msg->promisc_set_msg.value;
-    }
-    else if (msg->promisc_set_msg.mode == ZXDH_ALLMULTI_MODE)
-    {
-        LOG_INFO("ALLMULTI_EN_SET: %d", msg->promisc_set_msg.value);
-        err = dpp_vport_mc_promisc_set(pf_info, msg->promisc_set_msg.value);
-        if (err != 0)
-        {
-            LOG_ERR("dpp_vport_mc_promisc_set failed: %d\n", err);
-            return err;
-        }
-        vf_item->mc_promisc = msg->promisc_set_msg.value;
-    }
-    else
-    {
-        LOG_ERR("promisc_set_msg.mode[%d] error\n", msg->promisc_set_msg.mode);
-        return 1;
-    }
-
-    return err;
+	uint32_t err = 0;
+
+	if (!vf_item->trusted) {
+		LOG_ERR("vf untrusted!\n");
+		return 0;
+	}
+
+	if (msg->promisc_set_msg.mode == ZXDH_PROMISC_MODE) {
+		LOG_INFO("PROMISC_EN_SET: %d", msg->promisc_set_msg.value);
+		err = dpp_vport_uc_promisc_set(pf_info, msg->promisc_set_msg.value);
+		if (err != 0) {
+			LOG_ERR("dpp_vport_uc_promisc_set failed: %d\n", err);
+			return err;
+		}
+		if (msg->promisc_set_msg.mc_follow != 0) {
+			LOG_DEBUG("allmulti_follow\n");
+			err = dpp_vport_mc_promisc_set(pf_info, msg->promisc_set_msg.value);
+			if (err != 0) {
+				LOG_ERR("dpp_vport_mc_promisc_set failed: %d\n", err);
+				return err;
+			}
+		}
+		vf_item->promisc = msg->promisc_set_msg.value;
+	} else if (msg->promisc_set_msg.mode == ZXDH_ALLMULTI_MODE) {
+		LOG_INFO("ALLMULTI_EN_SET: %d", msg->promisc_set_msg.value);
+		err = dpp_vport_mc_promisc_set(pf_info, msg->promisc_set_msg.value);
+		if (err != 0) {
+			LOG_ERR("dpp_vport_mc_promisc_set failed: %d\n", err);
+			return err;
+		}
+		vf_item->mc_promisc = msg->promisc_set_msg.value;
+	} else {
+		LOG_ERR("promisc_set_msg.mode[%d] error\n", msg->promisc_set_msg.mode);
+		return 1;
+	}
+
+	return err;
 }
 
-static uint32_t zxdh_vf_vlan_filter_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_vlan_filter_set(zxdh_msg_info *msg,
+										zxdh_reps_info *reps,
+										DPP_PF_INFO_T *pf_info,
+										struct zxdh_vf_item *vf_item,
+										struct zxdh_pf_device *pf_dev)
 {
-    bool vf_vlan_filter_enable = msg->vlan_filter_set_msg.enable;
+	bool vf_vlan_filter_enable = msg->vlan_filter_set_msg.enable;
 
-    return dpp_vport_vlan_filter_en_set(pf_info, vf_vlan_filter_enable);
+	return dpp_vport_vlan_filter_en_set(pf_info, vf_vlan_filter_enable);
 }
 
-static uint32_t zxdh_vf_rx_vid_add(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_rx_vid_add(zxdh_msg_info *msg, zxdh_reps_info *reps,
+								   DPP_PF_INFO_T *pf_info,
+								   struct zxdh_vf_item *vf_item,
+								   struct zxdh_pf_device *pf_dev)
 {
-    uint16_t vid = msg->rx_vid_add_msg.vlan_id;
+	uint16_t vid = msg->rx_vid_add_msg.vlan_id;
 
-    return dpp_add_vlan_filter(pf_info, vid);
+	return dpp_add_vlan_filter(pf_info, vid);
 }
 
-static uint32_t zxdh_vf_rx_vid_del(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_rx_vid_del(zxdh_msg_info *msg, zxdh_reps_info *reps,
+								   DPP_PF_INFO_T *pf_info,
+								   struct zxdh_vf_item *vf_item,
+								   struct zxdh_pf_device *pf_dev)
 {
-    uint16_t vid = msg->rx_vid_del_msg.vlan_id;
+	uint16_t vid = msg->rx_vid_del_msg.vlan_id;
 
-    return dpp_del_vlan_filter(pf_info, vid);
+	return dpp_del_vlan_filter(pf_info, vid);
 }
 
-static uint32_t zxdh_vf_np_stats_get(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_np_stats_get(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									 DPP_PF_INFO_T *pf_info,
+									 struct zxdh_vf_item *vf_item,
+									 struct zxdh_pf_device *pf_dev)
 {
-    uint32_t vf_id = msg->hdr.vf_id;
-
-    dpp_stat_port_bc_packet_rx_cnt_get(pf_info, vf_id, msg->np_stats_get_msg.clear_mode,
-                                        &reps->np_stats_msg.np_rx_broadcast);
-    dpp_stat_port_bc_packet_tx_cnt_get(pf_info, vf_id, msg->np_stats_get_msg.clear_mode,
-                                        &reps->np_stats_msg.np_tx_broadcast);
+	uint32_t vf_id = msg->hdr.vf_id;
+
+	dpp_stat_port_bc_packet_rx_cnt_get(pf_info, vf_id,
+									   msg->np_stats_get_msg.clear_mode,
+									   &reps->np_stats_msg.np_rx_broadcast);
+	dpp_stat_port_bc_packet_tx_cnt_get(pf_info, vf_id,
+									   msg->np_stats_get_msg.clear_mode,
+									   &reps->np_stats_msg.np_tx_broadcast);
+
+	dpp_stat_MTU_packet_msg_rx_cnt_get(pf_info, vf_id,
+									   msg->np_stats_get_msg.clear_mode,
+									   &reps->np_stats_msg.np_rx_mtu_drop_bytes,
+									   &reps->np_stats_msg.np_rx_mtu_drop_pkts);
+	dpp_stat_MTU_packet_msg_tx_cnt_get(pf_info, vf_id,
+									   msg->np_stats_get_msg.clear_mode,
+									   &reps->np_stats_msg.np_tx_mtu_drop_bytes,
+									   &reps->np_stats_msg.np_tx_mtu_drop_pkts);
+
+	dpp_stat_plcr_packet_drop_rx_cnt_get(
+			pf_info, vf_id, msg->np_stats_get_msg.clear_mode,
+			&reps->np_stats_msg.np_rx_plcr_drop_bytes,
+			&reps->np_stats_msg.np_rx_plcr_drop_pkts);
+	dpp_stat_plcr_packet_drop_tx_cnt_get(
+			pf_info, vf_id, msg->np_stats_get_msg.clear_mode,
+			&reps->np_stats_msg.np_tx_plcr_drop_bytes,
+			&reps->np_stats_msg.np_tx_plcr_drop_pkts);
+
+	return 0;
+}
 
-    dpp_stat_MTU_packet_msg_rx_cnt_get(pf_info, vf_id, msg->np_stats_get_msg.clear_mode,
-                                        &reps->np_stats_msg.np_rx_mtu_drop_bytes, &reps->np_stats_msg.np_rx_mtu_drop_pkts);
-    dpp_stat_MTU_packet_msg_tx_cnt_get(pf_info, vf_id, msg->np_stats_get_msg.clear_mode,
-                                        &reps->np_stats_msg.np_tx_mtu_drop_bytes, &reps->np_stats_msg.np_tx_mtu_drop_pkts);
+static uint32_t zxdh_vf_tx_maxrate_set(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									   DPP_PF_INFO_T *pf_info,
+									   struct zxdh_vf_item *vf_item,
+									   struct zxdh_pf_device *pf_dev)
+{
+	uint16_t vport = msg->hdr.vport;
+	uint32_t flowid = msg->tx_maxrate_set_msg.flowid;
+	uint32_t max_rate = msg->tx_maxrate_set_msg.max_rate;
+	int32_t rtn = 0;
 
-    dpp_stat_plcr_packet_drop_rx_cnt_get(pf_info, vf_id, msg->np_stats_get_msg.clear_mode,
-                                          &reps->np_stats_msg.np_rx_plcr_drop_bytes, &reps->np_stats_msg.np_rx_plcr_drop_pkts);
-    dpp_stat_plcr_packet_drop_tx_cnt_get(pf_info, vf_id, msg->np_stats_get_msg.clear_mode,
-                                          &reps->np_stats_msg.np_tx_plcr_drop_bytes, &reps->np_stats_msg.np_tx_plcr_drop_pkts);
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+	rtn = zxdh_plcr_set_rate_limit(pf_dev, E_PLCR_CAR_A, vport, flowid,
+								   max_rate, 0);
 
-    return 0;
+	return rtn;
 }
 
-static uint32_t zxdh_vf_rate_limit_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_plcr_uninit(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									DPP_PF_INFO_T *pf_info,
+									struct zxdh_vf_item *vf_item,
+									struct zxdh_pf_device *pf_dev)
 {
-    int32_t  rtn;
-    uint16_t vport     = msg->hdr.vport;
-    uint32_t flowid    = msg->rate_limit_set_msg.flowid;
-    uint32_t car_type  = msg->rate_limit_set_msg.car_type;
-    uint32_t max_rate  = msg->rate_limit_set_msg.max_rate;
-    uint32_t min_rate  = msg->rate_limit_set_msg.min_rate;
-    uint32_t is_packet = msg->rate_limit_set_msg.is_packet;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    rtn = zxdh_plcr_set_rate_limit(pf_dev, is_packet, car_type, vport, flowid, max_rate, min_rate);
-    reps->rate_limit_set_rsp.err_code = rtn;
-
-    if (PLCR_REMOVE_RATE_LIMIT == rtn)
-    {
-        return 0;
-    }
-    else
-    {
-        return rtn;
-    }
+	uint16_t vport;
+	unsigned long flow_id;
+	E_PLCR_CAR_TYPE car_index;
+	struct xarray *xarray_flow;
+	struct zxdh_plcr_flow *flow = NULL;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	vport = msg->hdr.vport;
+
+	// deal with car A's flowid
+	for (car_index = E_PLCR_CAR_A; car_index <= E_PLCR_CAR_B; car_index++) {
+		xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_index]);
+		xa_for_each_range(xarray_flow, flow_id, flow, 0,
+						  gaudPlcrCarxFlowIdNum[car_index]) {
+			if (flow->vport == vport) {
+				zxdh_plcr_remove_rate_limit(pf_dev, car_index,
+											(uint32_t)flow_id);
+			}
+		}
+	}
+
+	zxdh_plcr_count_profiles(pf_dev);
+
+	return 0;
 }
 
-static uint32_t zxdh_vf_plcr_uninit(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_plcr_flowid_map(zxdh_msg_info *msg,
+										zxdh_reps_info *reps,
+										DPP_PF_INFO_T *pf_info,
+										struct zxdh_vf_item *vf_item,
+										struct zxdh_pf_device *pf_dev)
 {
-    uint16_t        vport;
-    unsigned long   flow_id;
-    E_PLCR_CAR_TYPE car_index;
-    struct xarray  *xarray_flow;
-    struct zxdh_plcr_flow *flow = NULL;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    vport = msg->hdr.vport;
-
-    //deal with car A's flowid
-    for(car_index=E_PLCR_CAR_A; car_index <= E_PLCR_CAR_B; car_index++)
-    {
-        xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_index]);
-        xa_for_each_range(xarray_flow, flow_id, flow, 0, gaudPlcrCarxFlowIdNum[car_index])
-        {
-            if(flow->vport == vport)
-            {
-                zxdh_plcr_remove_rate_limit(pf_dev, car_index, (uint32_t)flow_id);
-
-                //clear vport mappings between car B and car C.
-                if(E_PLCR_CAR_B == car_index)
-                {
-                    zxdh_plcr_clear_map(pf_dev, car_index, flow_id);
-                }
-            }
-        }
-    }
-
-    zxdh_plcr_count_profiles(pf_dev);
-
-    return 0;
+	int32_t rtn = 0;
+	uint32_t car_type = 0;
+	uint32_t flow_id = 0;
+	uint32_t map_flow_id = 0;
+	uint32_t map_sp = 0;
+
+	/*提取消息中的参数字段*/
+	car_type = msg->plcr_flowid_map_msg.car_type;
+	flow_id = msg->plcr_flowid_map_msg.flowid;
+	map_flow_id = msg->plcr_flowid_map_msg.map_flowid;
+	map_sp = msg->plcr_flowid_map_msg.sp;
+	LOG_INFO(
+			"%s-%d:map flow id: vf_item->vport = 0x%x, pf_dev->vport = 0x%x \n",
+			__FUNCTION__, __LINE__, vf_item->vport, pf_dev->vport);
+
+	rtn = dpp_car_queue_map_set(pf_info, car_type, flow_id, map_flow_id,
+								map_sp);
+	if (rtn) {
+		LOG_ERR("%s-%d:dpp_car_queue_map_set failed\n", __FUNCTION__, __LINE__);
+		return rtn;
+	}
+
+	return 0;
 }
 
-static uint32_t zxdh_vf_plcr_flowid_map(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_plcr_flow_init(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									   DPP_PF_INFO_T *pf_info,
+									   struct zxdh_vf_item *vf_item,
+									   struct zxdh_pf_device *pf_dev)
 {
-    int32_t  rtn        = 0;
-    uint32_t car_type   = 0;
-    uint32_t flowid     = 0;
-    uint32_t map_flowid = 0;
-    uint32_t map_sp     = 0;
-
-    /*提取消息中的参数字段*/
-    car_type    = msg->plcr_flowid_map_msg.car_type;
-    flowid      = msg->plcr_flowid_map_msg.flowid;
-    map_flowid  = msg->plcr_flowid_map_msg.map_flowid;
-    map_sp      = msg->plcr_flowid_map_msg.sp;
-
-    //前面的流程会判断是否需要进行映射，不会出现vf端口原来是非0group，现在会被group 0覆盖的情况
-    PLCR_LOG_INFO("dpp_car_queue_map_set: pf_info->vport = 0x%x, car_type = %d, flowid = %d, map_flowid = %d\n", pf_info->vport, car_type, flowid, map_flowid);
-    rtn = dpp_car_queue_map_set(pf_info, car_type, flowid, map_flowid, map_sp);
-    PLCR_COMM_ASSERT(rtn);
-
-    zxdh_plcr_stroe_map(pf_dev, car_type, flowid, map_flowid);
-
-    return 0;
+	int32_t rtn = 0;
+	E_PLCR_CAR_TYPE car_type = msg->plcr_flow_init_msg.car_type;
+	uint32_t flow_id = msg->plcr_flow_init_msg.flowid;
+
+	LOG_INFO("%s-%d:vport = 0x%x, flow_id = %d\n", __FUNCTION__, __LINE__,
+			 vf_item->vport, flow_id);
+	rtn = dpp_car_queue_cfg_set(pf_info, car_type, flow_id, DROP_DISABLE,
+								PLCR_DISABLE, PLCR_CAR_A_PROFILE_DAFAULT);
+	if (rtn)
+		LOG_ERR("%s-%d:dpp_car_queue_cfg_set failed\n", __FUNCTION__, __LINE__);
+
+	return 0;
 }
 
-static uint32_t zxdh_vf_plcr_mode_init(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_plcr_profile_id_add(zxdh_msg_info *msg,
+											zxdh_reps_info *reps,
+											DPP_PF_INFO_T *pf_info,
+											struct zxdh_vf_item *vf_item,
+											struct zxdh_pf_device *pf_dev)
 {
-    int32_t rtn = 0;
+	int32_t rtn = 0;
+	uint32_t car_type = 0;
+	uint16_t profile_id = 0;
 
-    //set mode0
-    rtn =  zxdh_plcr_set_mode(pf_dev, msg->hdr.vport, E_RATE_LIMIT_MODE0);
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+	/*1. 提取消息中的模板参数*/
+	car_type = msg->vf_plcr_profile_id_add_msg.car_type;
 
-    PLCR_COMM_ASSERT(rtn);
+	/*2. 申请新的profile*/
+	rtn = zxdh_plcr_req_profile(pf_dev, car_type, &profile_id);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed !\n", __FUNCTION__, __LINE__);
+		return rtn;
+	}
 
-    return rtn;
-}
+	/*3. 返回消息*/
+	reps->vf_plcr_profile_id_add_rsp.profile_id = profile_id;
 
-static uint32_t zxdh_vf_plcr_flow_init(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
-{
-    int rtn = 0;
-    uint32_t car_type;
-    uint32_t flowid;
-    uint32_t vf_idx;
-    uint32_t vport;
-    uint32_t vfid;
-    uint32_t map_flowid;
-
-    car_type = msg->plcr_flow_init_msg.car_type;
-    flowid = msg->plcr_flow_init_msg.flowid;
-    pf_info->slot = pf_dev->slot_id;
-    pf_info->vport = pf_dev->vport;
-
-    if (car_type == E_PLCR_CAR_C)
-    {
-        //对于carC flow的初始化，需检查目标group中num_vfs是否为0，确定其是否是本次移动前新建
-        for (vf_idx = 0; vf_idx < pf_dev->num_vfs; vf_idx ++)
-        {
-            rtn = zxdh_plcr_get_vport_vfid(pf_dev, vf_idx, &vport, &vfid);
-            PLCR_COMM_ASSERT(rtn);
-            rtn = zxdh_plcr_get_next_map(pf_dev, E_PLCR_CAR_B, vfid * 2, &map_flowid);
-            PLCR_COMM_ASSERT(rtn);
-            if (!rtn && flowid == map_flowid)
-            {
-                PLCR_LOG_INFO("Group is currently being used by at least one VF\n");
-                return 0;
-            }
-        }
-    }
-    PLCR_LOG_INFO("dpp_car_queue_cfg_set: vport = 0x%x, car_type = %d, flowid = %d, plcr_en = 0\n",
-                    pf_dev->vport, car_type, flowid);
-    rtn = dpp_car_queue_cfg_set(pf_info, (uint32_t)car_type, flowid, DROP_DISABLE, PLCR_DISABLE, 0);
-    if (rtn)
-        PLCR_LOG_ERR("failed to call dpp_car_queue_cfg_set()\n");
-
-    return rtn;
-}
-
-static uint32_t zxdh_vf_plcr_profile_id_add(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
-{
-    int32_t                     rtn        = 0;
-    uint32_t                    car_type   = 0;
-    uint16_t                    profile_id = 0;
-
-    LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
-    /*1. 提取消息中的模板参数*/
-    car_type = msg->vf_plcr_profile_id_add_msg.car_type;
-
-    /*2. 申请新的profile*/
-    rtn = zxdh_plcr_req_profile(pf_dev, car_type, &profile_id);
-    if (rtn)
-    {
-        LOG_ERR("%s-%d : failed !\n", __FUNCTION__, __LINE__);
-        return rtn;
-    }
-
-    /*3. 返回消息*/
-    reps->vf_plcr_profile_id_add_rsp.profile_id = profile_id;
-
-    return 0;
+	return 0;
 }
 
-static uint32_t zxdh_vf_plcr_profile_id_delete(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_plcr_profile_id_delete(zxdh_msg_info *msg,
+											   zxdh_reps_info *reps,
+											   DPP_PF_INFO_T *pf_info,
+											   struct zxdh_vf_item *vf_item,
+											   struct zxdh_pf_device *pf_dev)
 {
-    int32_t  rtn        = 0;
-    uint32_t car_type   = 0;
-    uint16_t profile_id = 0;
+	int32_t rtn = 0;
+	uint32_t car_type = 0;
+	uint16_t profile_id = 0;
 
-    LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
-    /*1. 提取消息中的模板参数*/
-    car_type   = msg->vf_plcr_profile_id_delete_msg.car_type;
-    profile_id = msg->vf_plcr_profile_id_delete_msg.profile_id;
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+	/*1. 提取消息中的模板参数*/
+	car_type = msg->vf_plcr_profile_id_delete_msg.car_type;
+	profile_id = msg->vf_plcr_profile_id_delete_msg.profile_id;
 
-    /*2. 限速模板使用计数-1：在下面的解除绑定zxdh_vf_plcr_queue_cfg_set()负责对使用计数-1*/
+	/*2.
+   * 限速模板使用计数-1：在下面的解除绑定zxdh_vf_plcr_queue_cfg_set()负责对使用计数-1*/
 
-    /*3. 释放限速模板资源*/
-    rtn = zxdh_plcr_release_profile(pf_dev, car_type, profile_id);
-    if (rtn)
-    {
-        LOG_ERR("%s-%d : failed !\n", __FUNCTION__, __LINE__);
-        return rtn;
-    }
+	/*3. 释放限速模板资源*/
+	rtn = zxdh_plcr_release_profile(pf_dev, car_type, profile_id);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed !\n", __FUNCTION__, __LINE__);
+		return rtn;
+	}
 
-    /*4. 没有返回消息*/
+	/*4. 没有返回消息*/
 
-    return rtn;
+	return rtn;
 }
 
-static uint32_t zxdh_vf_plcr_profile_cfg_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_plcr_profile_cfg_set(zxdh_msg_info *msg,
+											 zxdh_reps_info *reps,
+											 DPP_PF_INFO_T *pf_info,
+											 struct zxdh_vf_item *vf_item,
+											 struct zxdh_pf_device *pf_dev)
 {
-    int32_t                     rtn            = 0;
-    uint32_t                    car_type       = 0;
-    uint32_t                    pkt_mode       = 0;
-    uint16_t                    profile_id     = 0;
-    uint32_t                    max_rate       = 0;
-    uint32_t                    min_rate       = 0;
-    struct xarray              *xarray_profile = NULL;
-    struct zxdh_plcr_profile   *plcr_profile   = NULL;
-    union zxdh_plcr_profile_cfg profile_cfg;
-
-    LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
-    /*1. 提取消息中的模板参数*/
-    car_type    = msg->vf_plcr_profile_cfg_set_msg.car_type;
-    pkt_mode    = msg->vf_plcr_profile_cfg_set_msg.pkt_mode;
-    profile_id  = msg->vf_plcr_profile_cfg_set_msg.profile_id;
-
-    /*2. 校验外面的profile id和里面的profile id必须一致：限速模板联合体下包限速和字节限速结构体的前面2个成员是一样的（profile_id和pkt_sign）*/
-    if(profile_id != msg->vf_plcr_profile_cfg_set_msg.profile_cfg.byte_profile_cfg.profile_id)
-    {
-        LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__);
-        return -EINVAL;
-    }
-
-    /*3. 校验外面的pkt_mode和里面的pkt_sign必须一致：限速模板联合体下包限速和字节限速结构体的前面2个成员是一样的（profile_id和pkt_sign）*/
-    if(pkt_mode != msg->vf_plcr_profile_cfg_set_msg.profile_cfg.byte_profile_cfg.pkt_sign)
-    {
-        LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__);
-        return -EINVAL;
-    }
-
-    /*2. 获取profile*/
-    xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]);
-    plcr_profile   = xa_load(xarray_profile, profile_id);
-
-    /*3. 包限速处理*/
-    if(1 ==pkt_mode)
-    {
-        /*3.1 获取用户传递的字节限速模板参数*/
-        profile_cfg.pkt_profile_cfg = msg->vf_plcr_profile_cfg_set_msg.profile_cfg.pkt_profile_cfg;
-
-        /*3.2 包模式下直接使用限速模板里的包限速值*/
-        max_rate = profile_cfg.pkt_profile_cfg.cir;
-        min_rate = profile_cfg.pkt_profile_cfg.cir;
-
-        /*3.2 将限速模板的参数，配置到寄存器中去：包限速模板和字节限速模板前面2个成员profile_id和pkt_sign一样，保证了下面接口可以兼容包和字节限速配置*/
-        rtn = zxdh_plcr_cfg_profile(pf_dev, car_type, &profile_cfg.byte_profile_cfg);
-        if (rtn)
-        {
-            LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__);
-            return -EINVAL;
-        }
-    }
-    /*4. 字节限速处理*/
-    else
-    {
-        /*4.1 获取用户传递的字节限速模板参数*/
-        profile_cfg.byte_profile_cfg = msg->vf_plcr_profile_cfg_set_msg.profile_cfg.byte_profile_cfg;
-
-        /*4.2 将寄存器中的配置值，转换成用户限速值（单位：Mbit/s）*/
-        max_rate = zxdh_plcr_reg_maxrate_user(profile_cfg.byte_profile_cfg.eir);
-        min_rate = zxdh_plcr_reg_maxrate_user(profile_cfg.byte_profile_cfg.cir);
-
-        /*4.3 将限速模板的参数，配置到寄存器中去*/
-        rtn = zxdh_plcr_cfg_profile(pf_dev, car_type, &profile_cfg.byte_profile_cfg);
-        if (rtn)
-        {
-            LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__);
-            return -EINVAL;
-        }
-    }
-
-    /*5. 将限速模板参数保存到profile下面*/
-    rtn = zxdh_plcr_store_profile(pf_dev, car_type, max_rate, min_rate, &profile_cfg.byte_profile_cfg);
-    if (rtn)
-    {
-        LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__);
-        return -EINVAL;
-    }
-
-    /*6. 没有返回消息*/
-
-    return 0;
+	int32_t rtn = 0;
+	uint32_t car_type = 0;
+	uint32_t pkt_mode = 0;
+	uint16_t profile_id = 0;
+	uint32_t max_rate = 0;
+	uint32_t min_rate = 0;
+	struct xarray *xarray_profile = NULL;
+	struct zxdh_plcr_profile *plcr_profile = NULL;
+	union zxdh_plcr_profile_cfg profile_cfg;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+	/*1. 提取消息中的模板参数*/
+	car_type = msg->vf_plcr_profile_cfg_set_msg.car_type;
+	pkt_mode = msg->vf_plcr_profile_cfg_set_msg.pkt_mode;
+	profile_id = msg->vf_plcr_profile_cfg_set_msg.profile_id;
+
+	/*2. 校验外面的profile id和里面的profile
+   * id必须一致：限速模板联合体下包限速和字节限速结构体的前面2个成员是一样的（profile_id和pkt_sign）*/
+	if (profile_id != msg->vf_plcr_profile_cfg_set_msg.profile_cfg
+							  .byte_profile_cfg.profile_id) {
+		LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+
+	/*3.
+   * 校验外面的pkt_mode和里面的pkt_sign必须一致：限速模板联合体下包限速和字节限速结构体的前面2个成员是一样的（profile_id和pkt_sign）*/
+	if (pkt_mode !=
+		msg->vf_plcr_profile_cfg_set_msg.profile_cfg.byte_profile_cfg.pkt_sign) {
+		LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+
+	/*2. 获取profile*/
+	xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]);
+	plcr_profile = xa_load(xarray_profile, profile_id);
+
+	/*3. 包限速处理*/
+	if (1 == pkt_mode) {
+		/*3.1 获取用户传递的字节限速模板参数*/
+		profile_cfg.pkt_profile_cfg =
+				msg->vf_plcr_profile_cfg_set_msg.profile_cfg.pkt_profile_cfg;
+
+		/*3.2 包模式下直接使用限速模板里的包限速值*/
+		max_rate = profile_cfg.pkt_profile_cfg.cir;
+		min_rate = profile_cfg.pkt_profile_cfg.cir;
+
+		/*3.2
+     * 将限速模板的参数，配置到寄存器中去：包限速模板和字节限速模板前面2个成员profile_id和pkt_sign一样，保证了下面接口可以兼容包和字节限速配置*/
+		rtn = zxdh_plcr_cfg_profile(pf_dev, car_type,
+									&profile_cfg.byte_profile_cfg);
+		if (rtn) {
+			LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__);
+			return -EINVAL;
+		}
+	}
+	/*4. 字节限速处理*/
+	else {
+		/*4.1 获取用户传递的字节限速模板参数*/
+		profile_cfg.byte_profile_cfg =
+				msg->vf_plcr_profile_cfg_set_msg.profile_cfg.byte_profile_cfg;
+
+		/*4.2 将寄存器中的配置值，转换成用户限速值（单位：Mbit/s）*/
+		max_rate = zxdh_plcr_calc_user_maxrate_cfg(
+				profile_cfg.byte_profile_cfg.eir);
+		min_rate = zxdh_plcr_calc_user_maxrate_cfg(
+				profile_cfg.byte_profile_cfg.cir);
+
+		/*4.3 将限速模板的参数，配置到寄存器中去*/
+		rtn = zxdh_plcr_cfg_profile(pf_dev, car_type,
+									&profile_cfg.byte_profile_cfg);
+		if (rtn) {
+			LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__);
+			return -EINVAL;
+		}
+	}
+
+	/*5. 将限速模板参数保存到profile下面*/
+	rtn = zxdh_plcr_store_profile(pf_dev, car_type, max_rate, min_rate,
+								  &profile_cfg.byte_profile_cfg);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+
+	/*6. 没有返回消息*/
+
+	return 0;
 }
 
-static uint32_t zxdh_vf_plcr_profile_cfg_get(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_plcr_profile_cfg_get(zxdh_msg_info *msg,
+											 zxdh_reps_info *reps,
+											 DPP_PF_INFO_T *pf_info,
+											 struct zxdh_vf_item *vf_item,
+											 struct zxdh_pf_device *pf_dev)
 {
-    int32_t  rtn        = 0;
-    uint32_t car_type   = 0;
-    uint32_t pkt_mode   = 0;
-    uint16_t profile_id = 0;
-
-    LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
-    /*1. 提取消息中的模板参数*/
-    car_type    = msg->vf_plcr_profile_cfg_get_msg.car_type;
-    pkt_mode    = msg->vf_plcr_profile_cfg_get_msg.pkt_mode;
-    profile_id  = msg->vf_plcr_profile_cfg_get_msg.profile_id;
-
-    /*2. 从寄存器中，获取限速模板的参数*/
-    rtn = zxdh_plcr_get_profile(pf_dev, car_type, pkt_mode, profile_id, &reps->vf_plcr_profile_cfg_get_rsp.profile_cfg.byte_profile_cfg);
-    if (rtn)
-    {
-        LOG_ERR("%s-%d : failed to call zxdh_plcr_cfg_profile()\n", __FUNCTION__, __LINE__);
-        return rtn;
-    }
-
-    /*3. 返回消息：上面已经填充好返回消息*/
-
-    return 0;
+	int32_t rtn = 0;
+	uint32_t car_type = 0;
+	uint32_t pkt_mode = 0;
+	uint16_t profile_id = 0;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+	/*1. 提取消息中的模板参数*/
+	car_type = msg->vf_plcr_profile_cfg_get_msg.car_type;
+	pkt_mode = msg->vf_plcr_profile_cfg_get_msg.pkt_mode;
+	profile_id = msg->vf_plcr_profile_cfg_get_msg.profile_id;
+
+	/*2. 从寄存器中，获取限速模板的参数*/
+	rtn = zxdh_plcr_get_profile(
+			pf_dev, car_type, pkt_mode, profile_id,
+			&reps->vf_plcr_profile_cfg_get_rsp.profile_cfg.byte_profile_cfg);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed to call zxdh_plcr_cfg_profile()\n",
+				__FUNCTION__, __LINE__);
+		return rtn;
+	}
+
+	/*3. 返回消息：上面已经填充好返回消息*/
+
+	return 0;
 }
 
-static uint32_t zxdh_vf_plcr_queue_cfg_set(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_plcr_queue_cfg_set(zxdh_msg_info *msg,
+										   zxdh_reps_info *reps,
+										   DPP_PF_INFO_T *pf_info,
+										   struct zxdh_vf_item *vf_item,
+										   struct zxdh_pf_device *pf_dev)
 {
-    int32_t  rtn        = 0;
-    uint32_t car_type   = 0;
-    uint32_t drop_flag  = 0;
-    uint32_t plcr_en    = 0;
-    uint32_t flow_id    = 0;
-    uint32_t profile_id = 0;
-    uint16_t vport      = msg->hdr.vport;
-    struct xarray            *xarray_profile = NULL;
-    struct zxdh_plcr_flow    *plcr_flow      = NULL;
-    struct zxdh_plcr_profile *plcr_profile   = NULL;
-
-    LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
-    LOG_INFO("%s-%d:vport = 0x%x\n", __FUNCTION__, __LINE__, vport);
-
-    /*1. 提取消息中的模板参数*/
-    car_type    = msg->vf_plcr_queue_cfg_set_msg.car_type;
-    drop_flag   = msg->vf_plcr_queue_cfg_set_msg.drop_flag;
-    plcr_en     = msg->vf_plcr_queue_cfg_set_msg.plcr_en;
-    flow_id     = msg->vf_plcr_queue_cfg_set_msg.flow_id;
-    profile_id  = msg->vf_plcr_queue_cfg_set_msg.profile_id;
-
-    /*2. 获取xarray中存储的profile*/
-    xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]);
-    plcr_profile   = xa_load(xarray_profile, profile_id);
-    if(NULL == plcr_profile)
-    {
-        LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__);
-        return -EINVAL;
-    }
-
-    /*3. 绑定flow和profile*/
-    if(PLCR_ENABLE == plcr_en)
-    {
-        /*3.1 申请flow结构体，并存储到xarray*/
-        rtn = zxdh_plcr_req_flow(pf_dev, car_type, flow_id, &plcr_flow);
-        if (rtn)
-        {
-            LOG_ERR("%s-%d : kzalloc failed\n", __FUNCTION__, __LINE__);
-            return -EINVAL;
-        }
-
-        /*3.2 更新flow信息*/
-        zxdh_plcr_update_flow(plcr_flow, vport, plcr_profile->max_rate, plcr_profile->min_rate);
-
-        /*3.3 更新flow信息*/
-        plcr_flow->profile_id = profile_id;
-
-        /*3.4 将flow与profile进行绑定*/
-        rtn = dpp_car_queue_cfg_set(pf_info, car_type, flow_id, drop_flag, plcr_en, profile_id);
-        if (rtn)
-        {
-            LOG_ERR("%s-%d : failed to call dpp_car_queue_cfg_set()\n", __FUNCTION__, __LINE__);
-
-            /*释放先前申请的flow*/
-            zxdh_plcr_release_flow(pf_dev, car_type, flow_id);
-            return -EINVAL;
-        }
-
-        /*3.4 模板使用计数+1*/
-        zxdh_plcr_count_up_profile(pf_dev, car_type, profile_id);
-    }
-    /*4. 解除绑定flow和profile*/
-    else
-    {
-        /*4.1 解除绑定flow与profile*/
-        rtn = dpp_car_queue_cfg_set(pf_info, car_type, flow_id, drop_flag, plcr_en, profile_id);
-        if (rtn)
-        {
-            LOG_ERR("%s-%d : failed to call dpp_car_queue_cfg_set()\n", __FUNCTION__, __LINE__);
-            return -EINVAL;
-        }
-
-        /*4.2 释放flow*/
-        zxdh_plcr_release_flow(pf_dev, car_type, flow_id);
-
-        /*4.3 模板使用计数-1*/
-        zxdh_plcr_count_down_profile(pf_dev, car_type, profile_id);
-    }
-
-    /*5. 没有返回消息*/
-
-    return 0;
+	int32_t rtn = 0;
+	uint32_t car_type = 0;
+	uint32_t drop_flag = 0;
+	uint32_t plcr_en = 0;
+	uint32_t flow_id = 0;
+	uint32_t profile_id = 0;
+	uint16_t vport = msg->hdr.vport;
+	struct xarray *xarray_profile = NULL;
+	struct zxdh_plcr_flow *plcr_flow = NULL;
+	struct zxdh_plcr_profile *plcr_profile = NULL;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+	LOG_INFO("%s-%d:vport = 0x%x\n", __FUNCTION__, __LINE__, vport);
+
+	/*1. 提取消息中的模板参数*/
+	car_type = msg->vf_plcr_queue_cfg_set_msg.car_type;
+	drop_flag = msg->vf_plcr_queue_cfg_set_msg.drop_flag;
+	plcr_en = msg->vf_plcr_queue_cfg_set_msg.plcr_en;
+	flow_id = msg->vf_plcr_queue_cfg_set_msg.flow_id;
+	profile_id = msg->vf_plcr_queue_cfg_set_msg.profile_id;
+
+	/*2. 获取xarray中存储的profile*/
+	xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]);
+	plcr_profile = xa_load(xarray_profile, profile_id);
+	if (NULL == plcr_profile) {
+		LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+
+	/*3. 绑定flow和profile*/
+	if (PLCR_ENABLE == plcr_en) {
+		/*3.1 申请flow结构体，并存储到xarray*/
+		rtn = zxdh_plcr_req_flow(pf_dev, car_type, flow_id, &plcr_flow);
+		if (rtn) {
+			LOG_ERR("%s-%d : kzalloc failed\n", __FUNCTION__, __LINE__);
+			return -EINVAL;
+		}
+
+		/*3.2 更新flow信息*/
+		zxdh_plcr_update_flow(plcr_flow, vport, plcr_profile->max_rate,
+							  plcr_profile->min_rate);
+
+		/*3.3 更新flow信息*/
+		plcr_flow->profile_id = profile_id;
+
+		/*3.4 将flow与profile进行绑定*/
+		rtn = dpp_car_queue_cfg_set(pf_info, car_type, flow_id, drop_flag,
+									plcr_en, profile_id);
+		if (rtn) {
+			LOG_ERR("%s-%d : failed to call dpp_car_queue_cfg_set()\n",
+					__FUNCTION__, __LINE__);
+
+			/*释放先前申请的flow*/
+			zxdh_plcr_release_flow(pf_dev, car_type, flow_id);
+			return -EINVAL;
+		}
+
+		/*3.4 模板使用计数+1*/
+		zxdh_plcr_count_up_profile(pf_dev, car_type, profile_id);
+	}
+	/*4. 解除绑定flow和profile*/
+	else {
+		/*4.1 解除绑定flow与profile*/
+		rtn = dpp_car_queue_cfg_set(pf_info, car_type, flow_id, drop_flag,
+									plcr_en, profile_id);
+		if (rtn) {
+			LOG_ERR("%s-%d : failed to call dpp_car_queue_cfg_set()\n",
+					__FUNCTION__, __LINE__);
+			return -EINVAL;
+		}
+
+		/*4.2 释放flow*/
+		zxdh_plcr_release_flow(pf_dev, car_type, flow_id);
+
+		/*4.3 模板使用计数-1*/
+		zxdh_plcr_count_down_profile(pf_dev, car_type, profile_id);
+	}
+
+	/*5. 没有返回消息*/
+
+	return 0;
 }
 
-static uint32_t zxdh_vf_plcr_port_meter_stat_clr(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_plcr_port_meter_stat_clr(zxdh_msg_info *msg,
+												 zxdh_reps_info *reps,
+												 DPP_PF_INFO_T *pf_info,
+												 struct zxdh_vf_item *vf_item,
+												 struct zxdh_pf_device *pf_dev)
 {
-    int32_t  rtn     = 0;
-    uint64_t pkB_cnt = 0;
-    uint64_t pk_cnt  = 0;
-
-    LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
-    /*1. dpp接口函数原型如下：mode = 1，表示读清零*/
-    dpp_stat_plcr_packet_drop_tx_cnt_get(pf_info, msg->hdr.vf_id, 1, &pkB_cnt, &pk_cnt);
-    dpp_stat_plcr_packet_drop_rx_cnt_get(pf_info, msg->hdr.vf_id, 1, &pkB_cnt, &pk_cnt);
-
-    /*2. 没有返回消息*/
-    return rtn;
+	int32_t rtn = 0;
+	uint64_t pkB_cnt = 0;
+	uint64_t pk_cnt = 0;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+	/*1. dpp接口函数原型如下：mode = 1，表示读清零*/
+	dpp_stat_plcr_packet_drop_tx_cnt_get(pf_info, msg->hdr.vf_id, 1, &pkB_cnt,
+										 &pk_cnt);
+	dpp_stat_plcr_packet_drop_rx_cnt_get(pf_info, msg->hdr.vf_id, 1, &pkB_cnt,
+										 &pk_cnt);
+
+	/*2. 没有返回消息*/
+	return rtn;
 }
 
-static uint32_t zxdh_vf_plcr_port_meter_stat_get(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_plcr_port_meter_stat_get(zxdh_msg_info *msg,
+												 zxdh_reps_info *reps,
+												 DPP_PF_INFO_T *pf_info,
+												 struct zxdh_vf_item *vf_item,
+												 struct zxdh_pf_device *pf_dev)
 {
-    int32_t  rtn        = 0;
-    uint32_t direction  = 0;
-    uint32_t is_clr     = 0;
-    uint64_t *p_pkB_cnt = NULL;
-    uint64_t *p_pk_cnt  = NULL;
-
-    LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
-    /*1. 提取消息中的参数*/
-    direction = msg->vf_plcr_port_meter_stat_get_msg.direction;
-    is_clr    = msg->vf_plcr_port_meter_stat_get_msg.is_clr;
-
-    /*2. 获取返回信息地址*/
-    p_pkB_cnt = &(reps->vf_plcr_port_meter_stat_get_rsp.drop_pkB_cnt);
-    p_pk_cnt  = &(reps->vf_plcr_port_meter_stat_get_rsp.drop_pk_cnt);
-
-    /*2. 获取丢包统计*/
-    if(1 == direction)
-    {
-        dpp_stat_plcr_packet_drop_tx_cnt_get(pf_info, msg->hdr.vf_id, is_clr, p_pkB_cnt, p_pk_cnt);
-    }
-    else
-    {
-        dpp_stat_plcr_packet_drop_rx_cnt_get(pf_info, msg->hdr.vf_id, is_clr, p_pkB_cnt, p_pk_cnt);
-    }
-
-    /*3. 返回丢包统计值*/
-
-    return rtn;
+	int32_t rtn = 0;
+	uint32_t direction = 0;
+	uint32_t is_clr = 0;
+	uint64_t *p_pkB_cnt = NULL;
+	uint64_t *p_pk_cnt = NULL;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+	/*1. 提取消息中的参数*/
+	direction = msg->vf_plcr_port_meter_stat_get_msg.direction;
+	is_clr = msg->vf_plcr_port_meter_stat_get_msg.is_clr;
+
+	/*2. 获取返回信息地址*/
+	p_pkB_cnt = &(reps->vf_plcr_port_meter_stat_get_rsp.drop_pkB_cnt);
+	p_pk_cnt = &(reps->vf_plcr_port_meter_stat_get_rsp.drop_pk_cnt);
+
+	/*2. 获取丢包统计*/
+	if (1 == direction) {
+		dpp_stat_plcr_packet_drop_tx_cnt_get(pf_info, msg->hdr.vf_id, is_clr,
+											 p_pkB_cnt, p_pk_cnt);
+	} else {
+		dpp_stat_plcr_packet_drop_rx_cnt_get(pf_info, msg->hdr.vf_id, is_clr,
+											 p_pkB_cnt, p_pk_cnt);
+	}
+
+	/*3. 返回丢包统计值*/
+
+	return rtn;
 }
 
-static uint32_t zxdh_vf_call_np_1588(zxdh_msg_info *msg, zxdh_reps_info *reps, \
-    DPP_PF_INFO_T *pf_info, struct zxdh_vf_item *vf_item, struct zxdh_pf_device *pf_dev)
+static uint32_t zxdh_vf_call_np_1588(zxdh_msg_info *msg, zxdh_reps_info *reps,
+									 DPP_PF_INFO_T *pf_info,
+									 struct zxdh_vf_item *vf_item,
+									 struct zxdh_pf_device *pf_dev)
 {
-    uint32_t vfid = msg->vf_1588_call_np.vfid;
-    uint32_t interface_num = msg->vf_1588_call_np.call_np_interface_num;
-    uint32_t opt = msg->vf_1588_call_np.ptp_tc_enable_opt;
-
-    switch (interface_num)
-    {
-        case PTP_PORT_VFID_SET:
-        {
-            LOG_INFO("call dpp_ptp_port_vfid_set\n");
-            dpp_ptp_port_vfid_set(pf_info, vfid);
-            break;
-        }
-        case PTP_TC_ENABLE_SET:
-        {
-            LOG_INFO("call dpp_ptp_tc_enable_set\n");
-            dpp_ptp_tc_enable_set(pf_info, opt);
-            break;
-        }
-        default:
-        {
-            LOG_ERR("cannot found the interface_num %u\n", interface_num);
-            return -1;
-        }
-    }
-
-    return 0;
+	uint32_t vfid = msg->vf_1588_call_np.vfid;
+	uint32_t interface_num = msg->vf_1588_call_np.call_np_interface_num;
+	uint32_t opt = msg->vf_1588_call_np.ptp_tc_enable_opt;
+
+	switch (interface_num) {
+	case PTP_PORT_VFID_SET: {
+		LOG_INFO("call dpp_ptp_port_vfid_set\n");
+		dpp_ptp_port_vfid_set(pf_info, vfid);
+		break;
+	}
+	case PTP_TC_ENABLE_SET: {
+		LOG_INFO("call dpp_ptp_tc_enable_set\n");
+		dpp_ptp_tc_enable_set(pf_info, opt);
+		break;
+	}
+	default: {
+		LOG_ERR("cannot found the interface_num %u\n", interface_num);
+		return -1;
+	}
+	}
+
+	return 0;
 }
 
-zxdh_vf_msg_proc vf_msg_proc[] =
-{
-    {ZXDH_VF_PORT_INIT,      "vf_port_init",         zxdh_vf_port_init},
-    {ZXDH_VF_PORT_UNINIT,    "vf_port_uninit",       zxdh_vf_port_uninit},
-    {ZXDH_MAC_ADD,           "vf_all_mac_add",       zxdh_vf_all_mac_add},
-    {ZXDH_MAC_DEL,           "vf_all_mac_del",       zxdh_vf_all_mac_del},
-    {ZXDH_IPV6_MAC_ADD,      "vf_ipv6_mac_add",      zxdh_vf_ipv6_mac_add},
-    {ZXDH_IPV6_MAC_DEL,      "vf_ipv6_mac_del",      zxdh_vf_ipv6_mac_del},
-    {ZXDH_MAC_GET,           "vf_mac_get",           zxdh_vf_mac_get},
-    {ZXDH_RSS_EN_SET,        "vf_rss_state_set",     zxdh_vf_rss_state_set},
-    {ZXDH_RXFH_SET,          "vf_rxfh_set",          zxdh_vf_rxfh_set},
-    {ZXDH_RXFH_GET,          "vf_rxfh_get",          zxdh_vf_rxfh_get},
-    {ZXDH_RXFH_DEL,          "vf_rxfh_del",          zxdh_vf_rxfh_del},
-    {ZXDH_THASH_KEY_SET,     "vf_thash_key_set",     zxdh_vf_thash_key_set},
-    {ZXDH_THASH_KEY_GET,     "vf_thash_key_get",     zxdh_vf_thash_key_get},
-    {ZXDH_HASH_FUNC_SET,     "vf_hash_funcs_set",    zxdh_vf_hash_funcs_set},
-    {ZXDH_RX_FLOW_HASH_SET,  "vf_rx_flow_hash_set",  zxdh_vf_rx_flow_hash_set},
-    {ZXDH_RX_FLOW_HASH_GET,  "vf_rx_flow_hash_get",  zxdh_vf_rx_flow_hash_get},
-    {ZXDH_PORT_ATTRS_SET,    "vf_port_attrs_set",    zxdh_vf_port_attrs_set},
-    {ZXDH_PORT_ATTRS_GET,    "vf_port_attrs_get",    zxdh_vf_port_attrs_get},
-    {ZXDH_PROMISC_SET,       "vf_promisc_set",       zxdh_vf_promisc_set},
-    {ZXDH_VLAN_FILTER_SET,   "vf_vlan_filter_set",   zxdh_vf_vlan_filter_set},
-    {ZXDH_VLAN_FILTER_ADD,   "vf_rx_vid_add",        zxdh_vf_rx_vid_add},
-    {ZXDH_VLAN_FILTER_DEL,   "vf_rx_vid_del",        zxdh_vf_rx_vid_del},
-    {ZXDH_GET_NP_STATS,      "vf_np_stats_get",      zxdh_vf_np_stats_get},
-    {ZXDH_VF_RATE_LIMIT_SET, "vf_rate_limit_set",    zxdh_vf_rate_limit_set},
-    {ZXDH_PLCR_UNINIT,       "vf_plcr_uninit",       zxdh_vf_plcr_uninit},
-    {ZXDH_MAP_PLCR_FLOWID,   "vf_map_plcr_flowid",   zxdh_vf_plcr_flowid_map},
-    {ZXDH_PLCR_MODE_INIT,    "vf_plcr_mode_init",    zxdh_vf_plcr_mode_init},
-    {ZXDH_PLCR_FLOW_INIT,    "vf_plcr_flow_init",    zxdh_vf_plcr_flow_init},
-    {ZXDH_VLAN_OFFLOAD_SET,  "vf_vlan_strip_set",    zxdh_vf_vlan_strip_set},
-    {ZXDH_SET_TPID,          "vf_qinq_tpid_cfg",     zxdh_vf_qinq_tpid_cfg},
-    {ZXDH_PLCR_CAR_PROFILE_ID_ADD,      "vf_plcr_profile_id_add",     zxdh_vf_plcr_profile_id_add},
-    {ZXDH_PLCR_CAR_PROFILE_ID_DELETE,   "vf_plcr_profile_id_detele",  zxdh_vf_plcr_profile_id_delete},
-    {ZXDH_PLCR_CAR_PROFILE_CFG_SET,     "vf_plcr_profile_cfg_set",    zxdh_vf_plcr_profile_cfg_set},
-    {ZXDH_PLCR_CAR_PROFILE_CFG_GET,     "vf_plcr_profile_cfg_get",    zxdh_vf_plcr_profile_cfg_get},
-    {ZXDH_PLCR_CAR_QUEUE_CFG_SET,       "vf_plcr_queue_cfg_set",      zxdh_vf_plcr_queue_cfg_set},
-    {ZXDH_PORT_METER_STAT_CLR,          "vf_plcr_port_meter_stat_clr",zxdh_vf_plcr_port_meter_stat_clr},
-    {ZXDH_PORT_METER_STAT_GET,          "vf_plcr_port_meter_stat_get",zxdh_vf_plcr_port_meter_stat_get},
-    {ZXDH_VF_1588_CALL_NP,   "vf_1588_call_np",      zxdh_vf_call_np_1588},
+zxdh_vf_msg_proc vf_msg_proc[] = {
+	{ ZXDH_VF_PORT_INIT, "vf_port_init", zxdh_vf_port_init },
+	{ ZXDH_VF_PORT_UNINIT, "vf_port_uninit", zxdh_vf_port_uninit },
+	{ ZXDH_MAC_ADD, "vf_all_mac_add", zxdh_vf_all_mac_add },
+	{ ZXDH_MAC_DEL, "vf_all_mac_del", zxdh_vf_all_mac_del },
+	{ ZXDH_IPV6_MAC_ADD, "vf_all_ipv6_mac_add", zxdh_vf_all_ipv6_mac_add },
+	{ ZXDH_IPV6_MAC_DEL, "vf_all_ipv6_mac_del", zxdh_vf_all_ipv6_mac_del },
+	{ ZXDH_MAC_GET, "vf_mac_get", zxdh_vf_mac_get },
+	{ ZXDH_RSS_EN_SET, "vf_rss_state_set", zxdh_vf_rss_state_set },
+	{ ZXDH_RXFH_SET, "vf_rxfh_set", zxdh_vf_rxfh_set },
+	{ ZXDH_RXFH_GET, "vf_rxfh_get", zxdh_vf_rxfh_get },
+	{ ZXDH_RXFH_DEL, "vf_rxfh_del", zxdh_vf_rxfh_del },
+	{ ZXDH_THASH_KEY_SET, "vf_thash_key_set", zxdh_vf_thash_key_set },
+	{ ZXDH_THASH_KEY_GET, "vf_thash_key_get", zxdh_vf_thash_key_get },
+	{ ZXDH_HASH_FUNC_SET, "vf_hash_funcs_set", zxdh_vf_hash_funcs_set },
+	{ ZXDH_RX_FLOW_HASH_SET, "vf_rx_flow_hash_set", zxdh_vf_rx_flow_hash_set },
+	{ ZXDH_RX_FLOW_HASH_GET, "vf_rx_flow_hash_get", zxdh_vf_rx_flow_hash_get },
+	{ ZXDH_PORT_ATTRS_SET, "vf_port_attrs_set", zxdh_vf_port_attrs_set },
+	{ ZXDH_PORT_ATTRS_GET, "vf_port_attrs_get", zxdh_vf_port_attrs_get },
+	{ ZXDH_PROMISC_SET, "vf_promisc_set", zxdh_vf_promisc_set },
+	{ ZXDH_VLAN_FILTER_SET, "vf_vlan_filter_set", zxdh_vf_vlan_filter_set },
+	{ ZXDH_VLAN_FILTER_ADD, "vf_rx_vid_add", zxdh_vf_rx_vid_add },
+	{ ZXDH_VLAN_FILTER_DEL, "vf_rx_vid_del", zxdh_vf_rx_vid_del },
+	{ ZXDH_GET_NP_STATS, "vf_np_stats_get", zxdh_vf_np_stats_get },
+	{ ZXDH_TX_MAXRATE_SET, "vf_tx_maxrate_set", zxdh_vf_tx_maxrate_set },
+	{ ZXDH_PLCR_UNINIT, "vf_plcr_uninit", zxdh_vf_plcr_uninit },
+	{ ZXDH_MAP_PLCR_FLOWID, "vf_map_plcr_flowid", zxdh_vf_plcr_flowid_map },
+	{ ZXDH_PLCR_FLOW_INIT, "vf_plcr_flow_init", zxdh_vf_plcr_flow_init },
+	{ ZXDH_VLAN_OFFLOAD_SET, "vf_vlan_strip_set", zxdh_vf_vlan_strip_set },
+	{ ZXDH_SET_TPID, "vf_qinq_tpid_cfg", zxdh_vf_qinq_tpid_cfg },
+	{ ZXDH_PLCR_CAR_PROFILE_ID_ADD, "vf_plcr_profile_id_add",
+	  zxdh_vf_plcr_profile_id_add },
+	{ ZXDH_PLCR_CAR_PROFILE_ID_DELETE, "vf_plcr_profile_id_detele",
+	  zxdh_vf_plcr_profile_id_delete },
+	{ ZXDH_PLCR_CAR_PROFILE_CFG_SET, "vf_plcr_profile_cfg_set",
+	  zxdh_vf_plcr_profile_cfg_set },
+	{ ZXDH_PLCR_CAR_PROFILE_CFG_GET, "vf_plcr_profile_cfg_get",
+	  zxdh_vf_plcr_profile_cfg_get },
+	{ ZXDH_PLCR_CAR_QUEUE_CFG_SET, "vf_plcr_queue_cfg_set",
+	  zxdh_vf_plcr_queue_cfg_set },
+	{ ZXDH_PORT_METER_STAT_CLR, "vf_plcr_port_meter_stat_clr",
+	  zxdh_vf_plcr_port_meter_stat_clr },
+	{ ZXDH_PORT_METER_STAT_GET, "vf_plcr_port_meter_stat_get",
+	  zxdh_vf_plcr_port_meter_stat_get },
+	{ ZXDH_VF_1588_CALL_NP, "vf_1588_call_np", zxdh_vf_call_np_1588 },
 };
 
-int32_t dh_pf_msg_recv_func(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev)
+int32_t dh_pf_msg_recv_func(void *pay_load, uint16_t len, void *reps_buffer,
+							uint16_t *reps_len, void *dev)
 {
-    zxdh_msg_info *msg = (zxdh_msg_info *)pay_load;
-    zxdh_reps_info *reps = (zxdh_reps_info *)reps_buffer;
-    struct zxdh_pf_device *pf_dev = (struct zxdh_pf_device *)dev;
-    struct zxdh_vf_item *vf_item = NULL;
-    uint32_t ret = 0;
-    int32_t i = 0;
-    int32_t num = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    if (pf_dev == NULL)
-    {
-        LOG_ERR("dev is NULL\n");
-        return -1;
-    }
-
-    LOG_DEBUG("vport: 0x%x\n", msg->hdr.vport);
-    pf_info.slot = pf_dev->slot_id;
-    pf_info.vport = msg->hdr.vport;
-    num = sizeof(vf_msg_proc)/sizeof(zxdh_vf_msg_proc);
-    vf_item = &pf_dev->vf_item[(msg->hdr.pcie_id & (0xff))];
-    for (i = 0; i < num; i++)
-    {
-        *reps_len = sizeof(union zxdh_msg);
-        if (vf_msg_proc[i].op_code == msg->hdr.op_code)
-        {
-            LOG_INFO("%s is called", vf_msg_proc[i].proc_name);
-            ret = vf_msg_proc[i].msg_proc(msg, reps, &pf_info, vf_item, pf_dev);
-            if (ret != 0)
-            {
-                if (((msg->hdr.op_code == ZXDH_MAC_ADD)||(msg->hdr.op_code == ZXDH_IPV6_MAC_ADD)) && (ret == DPP_RC_TABLE_RANGE_INVALID))
-                {
-                    reps->flag = ZXDH_REPS_BEOND_MAC;
-                    return -1;
-                }
-                reps->flag = ZXDH_REPS_FAIL;
-                LOG_ERR("%s failed, ret: %d\n", vf_msg_proc[i].proc_name, ret);
-                return -1;
-            }
-
-            reps->flag = ZXDH_REPS_SUCC;
-            return 0;
-        }
-    }
-
-    LOG_ERR("invalid op_code: [%u]\n", msg->hdr.op_code);
-    return -2;
+	zxdh_msg_info *msg = (zxdh_msg_info *)pay_load;
+	zxdh_reps_info *reps = (zxdh_reps_info *)reps_buffer;
+	struct zxdh_pf_device *pf_dev = (struct zxdh_pf_device *)dev;
+	struct zxdh_vf_item *vf_item = NULL;
+	uint32_t ret = 0;
+	int32_t i = 0;
+	int32_t num = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	if (pf_dev == NULL) {
+		LOG_ERR("dev is NULL\n");
+		return -1;
+	}
+
+	LOG_DEBUG("vport: 0x%x\n", msg->hdr.vport);
+	pf_info.slot = pf_dev->slot_id;
+	pf_info.vport = msg->hdr.vport;
+	num = sizeof(vf_msg_proc) / sizeof(zxdh_vf_msg_proc);
+	vf_item = &pf_dev->vf_item[(msg->hdr.pcie_id & (0xff))];
+	for (i = 0; i < num; i++) {
+		*reps_len = sizeof(zxdh_reps_info);
+		if (vf_msg_proc[i].op_code == msg->hdr.op_code) {
+			LOG_INFO("%s is called", vf_msg_proc[i].proc_name);
+			ret = vf_msg_proc[i].msg_proc(msg, reps, &pf_info, vf_item, pf_dev);
+			if (ret != 0) {
+				reps->flag = ZXDH_REPS_FAIL;
+				LOG_ERR("%s failed, ret: %d\n", vf_msg_proc[i].proc_name, ret);
+				return -1;
+			}
+
+			reps->flag = ZXDH_REPS_SUCC;
+			return 0;
+		}
+	}
+
+	LOG_ERR("invalid op_code: [%u]\n", msg->hdr.op_code);
+	return -2;
 }
 
 int32_t dh_pf_msg_recv_func_register(void)
 {
-    int32_t ret = 0;
+	int32_t ret = 0;
 
-    ret = zxdh_bar_chan_msg_recv_register(MODULE_VF_BAR_MSG_TO_PF, dh_pf_msg_recv_func);
-    if (ret != 0)
-    {
-        LOG_ERR("event_id[%d] register failed: %d\n", MODULE_VF_BAR_MSG_TO_PF, ret);
-        return ret;
-    }
+	ret = zxdh_bar_chan_msg_recv_register(MODULE_VF_BAR_MSG_TO_PF,
+										  dh_pf_msg_recv_func);
+	if (ret != 0) {
+		LOG_ERR("event_id[%d] register failed: %d\n", MODULE_VF_BAR_MSG_TO_PF,
+				ret);
+		return ret;
+	}
 
-    return ret;
+	return ret;
 }
 
 void dh_pf_msg_recv_func_unregister(void)
 {
-    zxdh_bar_chan_msg_recv_unregister(MODULE_VF_BAR_MSG_TO_PF);
+	zxdh_bar_chan_msg_recv_unregister(MODULE_VF_BAR_MSG_TO_PF);
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/msg_func.h b/src/net/drivers/net/ethernet/dinghai/en_pf/msg_func.h
index d54ccffec65dbd5bf729b10bfadff76050e52a4b..c9b63c4afc30e6f61b227fc344ba59e21870ac8b 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_pf/msg_func.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_pf/msg_func.h
@@ -7,12 +7,11 @@ extern "C" {
 
 #include <linux/types.h>
 
-typedef enum
-{
-    PTP_PORT_VFID_SET,
-    PTP_TC_ENABLE_SET,
+typedef enum {
+	PTP_PORT_VFID_SET,
+	PTP_TC_ENABLE_SET,
 
-    MAX_VF_CALL_NP_NUM,
+	MAX_VF_CALL_NP_NUM,
 } vf_call_np_num;
 
 int32_t dh_pf_msg_recv_func_register(void);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_pf/rdma.c b/src/net/drivers/net/ethernet/dinghai/en_pf/rdma.c
old mode 100755
new mode 100644
diff --git a/src/net/drivers/net/ethernet/dinghai/en_plcr.c b/src/net/drivers/net/ethernet/dinghai/en_plcr.c
new file mode 100644
index 0000000000000000000000000000000000000000..22b5758621397f0d28a9922f8917058efe65e27e
--- /dev/null
+++ b/src/net/drivers/net/ethernet/dinghai/en_plcr.c
@@ -0,0 +1,326 @@
+#ifdef AUX_BUS_NO_SUPPORT
+#include <linux/dinghai/auxiliary_bus.h>
+#else
+#include <linux/auxiliary_bus.h>
+#endif
+#include <linux/dinghai/driver.h>
+#include <net/devlink.h>
+#include <net/udp_tunnel.h>
+#include <linux/dinghai/devlink.h>
+#include <linux/dinghai/dh_cmd.h>
+#include <linux/netdevice.h>
+#include "en_aux.h"
+#include "en_ethtool/ethtool.h"
+#include <linux/dinghai/en_sf.h>
+#include <linux/etherdevice.h>
+#include <linux/dinghai/helper.h>
+#include "en_np/table/include/dpp_tbl_api.h"
+#include "en_aux/events.h"
+#include "en_aux/eq.h"
+#include "en_aux/en_cmd.h"
+#include "msg_common.h"
+#include "en_pf.h"
+#include <linux/dinghai/kcompat.h>
+#include "en_aux/en_ioctl.h"
+#ifdef TIME_STAMP_1588
+#include "en_aux/en_1588_pkt_proc.h"
+#endif
+
+/**-------------------------------------------------------------------------------------------------------------------@n
+ * 功能详述:
+ *     - zxdh_map_flowid函数属于接口函数, 其功能是:
+ *     - 将vf下的发送队列和接收队列对应的一级CARflow id映射到VF端口对应的二级CAR
+ *flow id
+ *     - 该接口会在创建vf的流程中被调用
+ *
+ * 该函数在会被调用的说明：
+ *     - 1.会在创建vf的流程中被调用：vf创建的过程中会被分配32个发送队列和32个接收队列，将这些队列对应的一级CAR
+ *flow id映射 到vf端口对应的二级CAR flow id
+ *     - 2.会在用户修改vf的队列数量的时候被调用：
+ *         用户调用ethtool命令设置vf的队列数量
+ *         在钩子函数zxdh_en_set_channels()中会先调用stop()钩子释放所有队列，再调用open()重新申请队列
+ *         由于stop()和open()两个钩子的代码还未编写好，暂时忽略这第二个调用场景
+ *     - 3.在zxdh_vqs_init()内部，virtnet_find_vqs()的后面调用该函数
+ *         zxdh_en_dev_probe()--->
+ *           zxdh_vqs_init()--->virtnet_find_vqs()
+ *
+ *
+ * 参数概述:
+ *     - netdev      : 网络设备结构体指针
+ *     - car_type    ：E_PLCR_CAR_B表示进行一级CAR到二级CAR的flow
+ *id映射，E_PLCR_CAR_C表示进行二级CAR到三级CAR的flow id映射
+ *     - specified_flow_id
+ *：针对驱动卸载时，需要将前一级的flowid映射到本级保留的flowid上，即映射到specified_flow_id
+ *     - 返回值类型是INT32, 含义是: 错误码，正确时为S_OK
+ *
+ * 引用(类变量,外部变量,接口函数):
+ *     - 无
+ *
+ * 注意：该函数内部会进行是否为vf的判断，因为只针对vf进行限速
+ *--------------------------------------------------------------------------------------------------------------------*/
+int zxdh_map_flowid(struct zxdh_en_priv *en_priv, E_PLCR_CAR_TYPE car_type,
+					uint32_t specified_flow_id)
+{
+	int32_t rtn = 0;
+	int32_t i = 0;
+	uint32_t ep_id = 0;
+	uint32_t pf_func_num = 0;
+	uint32_t vf_func_num = 0;
+	uint32_t flow_id = 0;
+	uint32_t map_flow_id = 0;
+	uint32_t map_sp = 0; //优先级默认保持0
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t queue_pairs = en_dev->curr_queue_pairs;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+	// CAR-A ---> CAR-B的flow id映射
+	// todo:需要把每个vf对应flow映射到一个默认三级car
+	// flow，寄存器保留了host复位前二级到三级car的映射关系，和一二级同理
+	if (E_PLCR_CAR_A == car_type) {
+		if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+			if (0 == specified_flow_id)
+				return 0;
+
+			LOG_INFO("%s-%d:map flow id: en_dev->vport = 0x%x \n", __FUNCTION__,
+					 __LINE__, en_dev->vport);
+
+			for (i = 0; i < queue_pairs; i++) {
+				flow_id = en_dev->sq[i].vq->phy_index;
+
+				LOG_INFO("%s-%d:map flow id: %d --- %d\n", __FUNCTION__,
+						 __LINE__, flow_id, specified_flow_id);
+				rtn = dpp_car_queue_map_set(&pf_info, car_type, flow_id,
+											specified_flow_id, map_sp);
+				if (rtn)
+					LOG_ERR("%s-%d:dpp_car_queue_map_set failed\n",
+							__FUNCTION__, __LINE__);
+			}
+		} else if (en_dev->ops->get_coredev_type(en_dev->parent) ==
+				   DH_COREDEV_VF) {
+			/*计算vf tx的flow id，二级CAR前1024个flow id对应vf tx，接下来1024个flow
+       * id对应vf rx，以下map_flow_id计算方式只适用于VF*/
+			ep_id = ((en_dev->vport & 0x7000) >> 12);
+			pf_func_num = ((en_dev->vport & 0x0700) >> 8);
+			vf_func_num = ((en_dev->vport & 0xff));
+			map_flow_id = 256 * ep_id + 32 * pf_func_num +
+						  vf_func_num; //每个pf下32个vf
+			/*如果用户指定了有效的specified_flow_id，则使用这个指定的flowid*/
+			if (0 != specified_flow_id) {
+				map_flow_id = specified_flow_id;
+			}
+			LOG_INFO("%s-%d:map flow id: en_dev->vport = 0x%x \n", __FUNCTION__,
+					 __LINE__, en_dev->vport);
+
+			//遍历所有的发送队列和接收队列（vf端口限速有tx和rx两个方向的需求）
+			for (i = 0; i < queue_pairs; i++) {
+				//获取发送队列号（0 - 4095中的奇数）
+				flow_id = en_dev->sq[i].vq->phy_index;
+
+				// todo：和孙泽明走查的时候，确认一下，flow_id是一级CAR flow
+				// id，map_flow_id是二级CAR flow id ？
+				msg.hdr.op_code = ZXDH_MAP_PLCR_FLOWID;
+				msg.hdr.vport = en_dev->vport;
+				msg.hdr.pcie_id = en_dev->pcie_id;
+				msg.hdr.vf_id = en_dev->pcie_id & (0xff);
+
+				msg.plcr_flowid_map_msg.car_type = car_type;
+				msg.plcr_flowid_map_msg.flowid = flow_id;
+				msg.plcr_flowid_map_msg.map_flowid = map_flow_id;
+				msg.plcr_flowid_map_msg.sp = map_sp;
+				LOG_INFO("%s-%d:map flow id: %d --- %d\n", __FUNCTION__,
+						 __LINE__, flow_id, map_flow_id);
+				rtn = zxdh_send_command_to_specify(
+						en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &reps);
+				if (rtn != 0)
+					LOG_ERR("%s-%d:zxdh_send_command_to_specify failed\n",
+							__FUNCTION__, __LINE__);
+			}
+		}
+	}
+	return rtn;
+}
+
+int zxdh_plcr_flow_init(struct zxdh_en_priv *en_priv, E_PLCR_CAR_TYPE car_type)
+{
+	int32_t rtn = 0;
+	int32_t i = 0;
+	uint32_t flow_id = 0;
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	int32_t queue_pairs = en_dev->curr_queue_pairs;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = en_dev->slot_id;
+	pf_info.vport = en_dev->vport;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	if (E_PLCR_CAR_A == car_type) {
+		if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+			for (i = 0; i < queue_pairs; i++) {
+				flow_id = en_dev->sq[i].vq->phy_index;
+
+				LOG_INFO("%s-%d:vport = 0x%x, flow_id = %d\n", __FUNCTION__,
+						 __LINE__, en_dev->vport, flow_id);
+				rtn = dpp_car_queue_cfg_set(&pf_info, car_type, flow_id,
+											DROP_DISABLE, PLCR_DISABLE,
+											PLCR_CAR_A_PROFILE_DAFAULT);
+				if (rtn)
+					LOG_ERR("%s-%d:dpp_car_queue_cfg_set failed\n",
+							__FUNCTION__, __LINE__);
+			}
+		} else if (en_dev->ops->get_coredev_type(en_dev->parent) ==
+				   DH_COREDEV_VF) {
+			for (i = 0; i < queue_pairs; i++) {
+				flow_id = en_dev->sq[i].vq->phy_index;
+
+				msg.hdr.op_code = ZXDH_PLCR_FLOW_INIT;
+				msg.hdr.vport = en_dev->vport;
+				msg.hdr.pcie_id = en_dev->pcie_id;
+				msg.hdr.vf_id = en_dev->pcie_id & (0xff);
+
+				msg.plcr_flow_init_msg.car_type = car_type;
+				msg.plcr_flow_init_msg.flowid = flow_id;
+
+				rtn = zxdh_send_command_to_specify(
+						en_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &reps);
+				if (rtn != 0)
+					LOG_ERR("%s-%d:zxdh_send_command_to_specify failed\n",
+							__FUNCTION__, __LINE__);
+			}
+		}
+	}
+	return rtn;
+}
+
+/*初始化*/
+// en_pf是软件分层的最底层，与一些硬件做交互的代码,从底层往上创建
+
+int32_t zxdh_plcr_init(struct zxdh_en_priv *en_priv)
+{
+	int32_t rtn = 0;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct dh_core_dev *dh_dev = en_dev->parent;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev->parent);
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		//每个pf及其vf只会进一次该流程，且第一个进probe的只能是pf,不需要判断是否重复初始化
+		xa_init(&pf_dev->plcr_table.plcr_profiles[E_PLCR_CAR_A]);
+		xa_init(&pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_A]);
+
+		xa_init(&pf_dev->plcr_table.plcr_profiles[E_PLCR_CAR_B]);
+		xa_init(&pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_B]);
+
+		xa_init(&pf_dev->plcr_table.plcr_profiles[E_PLCR_CAR_C]);
+		xa_init(&pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_C]);
+
+		//现在分配给pf的队列，先前可能分配给vf使用过，将其映射到二级car保留的flowid上
+		rtn = zxdh_map_flowid(en_priv, E_PLCR_CAR_A,
+							  PLCR_CAR_B_FLOWID_FOR_INIT);
+		if (rtn) {
+			LOG_ERR("%s-%d : zxdh_map_flowid failed\n", __FUNCTION__, __LINE__);
+			return rtn;
+		}
+
+		//将分配给pf的队列对应的一级car flowid，先解除可能存在的与一级car
+		// profile的绑定关系
+		rtn = zxdh_plcr_flow_init(en_priv, E_PLCR_CAR_A);
+		if (rtn) {
+			LOG_ERR("%s-%d : zxdh_plcr_flow_init failed\n", __FUNCTION__,
+					__LINE__);
+			return rtn;
+		}
+	} else if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		//走一遍zxdh_plcr_uninit（）的流程，防止先前该vf端口有未卸载的资源
+		msg.hdr.op_code = ZXDH_PLCR_UNINIT;
+		msg.hdr.vport = en_dev->vport;
+		msg.hdr.pcie_id = en_dev->pcie_id;
+		msg.hdr.vf_id = en_dev->pcie_id & (0xff);
+
+		rtn = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF,
+										   &msg, &reps);
+		if (rtn != 0) {
+			LOG_ERR("%s-%d : zxdh_send_command_to_specify failed: %d\n",
+					__FUNCTION__, __LINE__, rtn);
+		}
+
+		//将vf下队列对应的一级car flowid映射到vf端口对应的二级car flowid
+		rtn = zxdh_map_flowid(en_priv, E_PLCR_CAR_A, 0);
+		if (rtn) {
+			LOG_ERR("%s-%d : zxdh_map_flowid failed\n", __FUNCTION__, __LINE__);
+			return rtn;
+		}
+
+		//将分配给pf的队列对应的一级car flowid，先解除可能存在的与一级car
+		// profile的绑定关系
+		rtn = zxdh_plcr_flow_init(en_priv, E_PLCR_CAR_A);
+		if (rtn) {
+			LOG_ERR("%s-%d : zxdh_plcr_flow_init failed\n", __FUNCTION__,
+					__LINE__);
+			return rtn;
+		}
+		LOG_INFO("zxdh_plcr_init vf completed\n");
+	}
+	return rtn;
+}
+EXPORT_SYMBOL(zxdh_plcr_init);
+
+/*释放PF/VF*/
+int32_t zxdh_plcr_uninit(struct zxdh_en_priv *en_priv)
+{
+	int rtn = 0;
+	zxdh_msg_info msg = { 0 };
+	zxdh_reps_info reps = { 0 };
+
+	struct xarray *xarray_profile;
+	struct xarray *xarray_flow;
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct dh_core_dev *dh_dev = en_dev->parent;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev->parent);
+
+	unsigned long flow_id;
+	E_PLCR_CAR_TYPE car_index;
+	struct zxdh_plcr_profile *profile = NULL;
+	struct zxdh_plcr_flow *flow = NULL;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_PF) {
+		for (car_index = E_PLCR_CAR_A; car_index <= E_PLCR_CAR_B; car_index++) {
+			xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_index]);
+			xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_index]);
+
+			xa_for_each_range(xarray_flow, flow_id, flow, 0,
+							  gaudPlcrCarxFlowIdNum[car_index]) {
+				zxdh_plcr_remove_rate_limit(pf_dev, car_index, flow_id);
+			}
+
+			xa_destroy(xarray_flow);
+			xa_destroy(xarray_profile);
+		}
+	} else if (en_dev->ops->get_coredev_type(en_dev->parent) == DH_COREDEV_VF) {
+		//解除一二级flowid与profile之间的绑定关系，并释放profile
+		msg.hdr.op_code = ZXDH_PLCR_UNINIT;
+		msg.hdr.vport = en_dev->vport;
+		msg.hdr.pcie_id = en_dev->pcie_id;
+		msg.hdr.vf_id = en_dev->pcie_id & (0xff);
+
+		rtn = zxdh_send_command_to_specify(en_dev, MODULE_VF_BAR_MSG_TO_PF,
+										   &msg, &reps);
+		if (rtn != 0) {
+			LOG_ERR("%s-%d : zxdh_send_command_to_specify failed: %d\n",
+					__FUNCTION__, __LINE__, rtn);
+		}
+	}
+	return rtn;
+}
+EXPORT_SYMBOL(zxdh_plcr_uninit);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver.c b/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver.c
index e58d6e884baa09627e03a4a0438d125b46a2ad6c..522dc14492347a31e1038b35b9e7af4d506a15c0 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver.c
@@ -13,422 +13,424 @@
 #include <linux/dinghai/dh_cmd.h>
 #include "zxdh_ptp_common.h"
 
-static uint64_t virt_addr = 0;
-static uint64_t pcie_id = 0;
-static dev_t tod_device_no = 0;
-static struct device *tod_device = NULL;
-static struct file   *tod_device_file = NULL;
-static struct cdev   *tod_device_cdev = NULL;
-static struct class  *tod_device_class = NULL;
+static uint64_t virt_addr;
+static dev_t tod_device_no;
+static struct device *tod_device;
+static struct file *tod_device_file;
+static struct cdev *tod_device_cdev;
+static struct class *tod_device_class;
 
-#define TOD_DEVICE_NAME             "tod_device"
+#define TOD_DEVICE_NAME "tod_device"
 
-int32_t tod_device_set_bar_virtual_addr(uint64_t virtaddr, uint16_t pcieid)
+int32_t tod_device_set_bar_virtual_addr(uint64_t virtaddr)
 {
-    virt_addr = virtaddr;
-    pcie_id = pcieid;
-    PTP_LOG_INFO("%s: bar msg virtaddr: 0x%llx\n", __FUNCTION__, virtaddr);
-    return 0;
+	virt_addr = virtaddr;
+	PTP_LOG_INFO("%s: bar msg virtaddr: 0x%llx\n", __func__, virtaddr);
+	return 0;
 }
 EXPORT_SYMBOL(tod_device_set_bar_virtual_addr);
 
-static int32_t tod_device_sync_msg_send(uint8_t *req, uint32_t req_len, uint8_t *resp, uint32_t resp_len)
+static int32_t tod_device_sync_msg_send(uint8_t *req, uint32_t req_len,
+										uint8_t *resp, uint32_t resp_len)
 {
-    int32_t  result = 0;
-    uint32_t payload_len = 0;
-    struct zxdh_pci_bar_msg in = {0};
-    struct zxdh_msg_recviver_mem out = {0};
-
-    if (req == NULL || req_len < 4)
-    {
-        PTP_LOG_ERR("%s: arg invalid, req: %px, req_len: %u.\n", __FUNCTION__, req, req_len);
-        return -EINVAL;
-    }
-
-    out.buffer_len = 4 + 4 + resp_len; // 4B 消息头 + 4B result + resp_len实际应答消息
-    out.recv_buffer = (uint8_t*)kmalloc(out.buffer_len, GFP_KERNEL);
-    if (out.recv_buffer == NULL)
-    {
-        PTP_LOG_ERR("%s: no space left on device.\n", __FUNCTION__);
-        return -ENOSPC;
-    }
-    memset(out.recv_buffer, 0, out.buffer_len);
-
-    in.virt_addr = virt_addr;
-    in.event_id  = MODULE_TOD;
-    in.src = MSG_CHAN_END_PF;
-    in.dst = MSG_CHAN_END_RISC;
-    in.payload_addr = req;
-    in.payload_len  = req_len;
-    in.src_pcieid = pcie_id;
-
-    if(zxdh_bar_chan_sync_msg_send(&in, &out) != BAR_MSG_OK)
-    {
-        kfree(out.recv_buffer);
-        PTP_LOG_ERR("%s: zxdh_bar_chan_sync_msg_send failed.\n", __FUNCTION__);
-        return -EINVAL;
-    }
-
-    // 消息应答格式: header(4B) + payload(nB), payload最大2048 - 12
-    // header格式: 0xFF(1B) + payload_len(2B) + rsv(1B)
-    // payload格式: result(4B) + msg((n - 4)B)
-    payload_len = *(uint16_t*)((uint8_t*)out.recv_buffer + 1);
-    if (payload_len < 4)
-    {
-        kfree(out.recv_buffer);
-        PTP_LOG_ERR("%s: payload_len: %u check failed.\n", __FUNCTION__, payload_len);
-        return -EINVAL;
-    }
-
-    result = *(int32_t*)((uint8_t*)out.recv_buffer + 4);
-    if (result != 0)
-    {
-        kfree(out.recv_buffer);
-        PTP_LOG_ERR("%s: result: %d check failed.\n", __FUNCTION__, result);
-        return result;
-    }
-
-    if (payload_len > 4 && resp != NULL)
-    {
-        memcpy(resp, out.recv_buffer + 8, (((payload_len - 4) > resp_len) ? resp_len : (payload_len - 4)));
-    }
-
-    kfree(out.recv_buffer);
-
-    return 0;
+	int32_t result = 0;
+	uint32_t payload_len = 0;
+	struct zxdh_pci_bar_msg in = { 0 };
+	struct zxdh_msg_recviver_mem out = { 0 };
+
+	if (req == NULL || req_len < 4) {
+		PTP_LOG_ERR("%s: arg invalid, req: %px, req_len: %u.\n", __func__,
+					req, req_len);
+		return -EINVAL;
+	}
+
+	out.buffer_len =
+			4 + 4 + resp_len; // 4B 消息头 + 4B result + resp_len实际应答消息
+	out.recv_buffer = (uint8_t *)kmalloc(out.buffer_len, GFP_KERNEL);
+	if (out.recv_buffer == NULL) {
+		PTP_LOG_ERR("%s: no space left on device.\n", __func__);
+		return -ENOSPC;
+	}
+
+	in.virt_addr = virt_addr;
+	in.event_id = MODULE_TOD;
+	in.src = MSG_CHAN_END_PF;
+	in.dst = MSG_CHAN_END_RISC;
+	in.payload_addr = req;
+	in.payload_len = req_len;
+
+	if (zxdh_bar_chan_sync_msg_send(&in, &out) != BAR_MSG_OK) {
+		kfree(out.recv_buffer);
+		PTP_LOG_ERR("%s: zxdh_bar_chan_sync_msg_send failed.\n", __func__);
+		return -EINVAL;
+	}
+
+	// 消息应答格式: header(4B) + payload(nB), payload最大2048 - 12
+	// header格式: 0xFF(1B) + payload_len(2B) + rsv(1B)
+	// payload格式: result(4B) + msg((n - 4)B)
+	payload_len = *(uint16_t *)((uint8_t *)out.recv_buffer + 1);
+	if (payload_len < 4) {
+		kfree(out.recv_buffer);
+		PTP_LOG_ERR("%s: payload_len: %u check failed.\n", __func__,
+					payload_len);
+		return -EINVAL;
+	}
+
+	result = *(int32_t *)((uint8_t *)out.recv_buffer + 4);
+	if (result != 0) {
+		kfree(out.recv_buffer);
+		PTP_LOG_ERR("%s: result: %d check failed.\n", __func__, result);
+		return result;
+	}
+
+	if (payload_len > 4 && resp != NULL) {
+		memcpy(resp, out.recv_buffer + 8,
+			   (((payload_len - 4) > resp_len) ? resp_len : (payload_len - 4)));
+	}
+
+	kfree(out.recv_buffer);
+
+	return 0;
 }
 
 static int tod_device_open(struct inode *inode, struct file *file)
 {
-    int32_t result = 0;
-    const char *device = "/dev/ttyAMA1";
-    struct tod_device_msg msg;
-
-    printk(KERN_INFO "%s.\n", __FUNCTION__);
-
-    if (tod_device_file != NULL)
-    {
-        PTP_LOG_INFO("%s: device already open.\n", __FUNCTION__);
-        return 0;
-    }
-
-    memset(&msg, 0x00, sizeof(struct tod_device_msg));
-    msg.type = TOD_DEVICE_MSG_OPEN;
-    memcpy(msg.data, device, strlen(device) + 1);
-
-    result = tod_device_sync_msg_send((uint8_t*)(&msg), sizeof(struct tod_device_msg), (uint8_t*)(&tod_device_file), sizeof(struct file*));
-    if (result != 0)
-    {
-        tod_device_file = NULL;
-        printk(KERN_ERR "%s: tod_device_sync_msg_send failed, result: %d.\n", __FUNCTION__, result);
-        return -EINVAL;
-    }
-    PTP_LOG_INFO("%s: file %px open success.\n", __FUNCTION__, tod_device_file);
-
-    return 0;
+	int32_t result = 0;
+	int8_t *device = "/dev/ttyAMA1";
+	struct tod_device_msg msg;
+
+	printk(KERN_INFO "%s.\n", __func__);
+
+	if (tod_device_file != NULL) {
+		PTP_LOG_INFO("%s: device already open.\n", __func__);
+		return 0;
+	}
+
+	memset(&msg, 0x00, sizeof(struct tod_device_msg));
+	msg.type = TOD_DEVICE_MSG_OPEN;
+	memcpy(msg.data, device, strlen(device) + 1);
+
+	result = tod_device_sync_msg_send((uint8_t *)(&msg),
+									  sizeof(struct tod_device_msg),
+									  (uint8_t *)(&tod_device_file),
+									  sizeof(struct file *));
+	if (result != 0) {
+		tod_device_file = NULL;
+		printk(KERN_ERR "%s: tod_device_sync_msg_send failed, result: %d.\n",
+			   __func__, result);
+		return -EINVAL;
+	}
+	PTP_LOG_INFO("%s: file %px open success.\n", __func__, tod_device_file);
+
+	return 0;
 }
 
 static int tod_device_release(struct inode *inode, struct file *file)
 {
-    int32_t result = 0;
-    struct tod_device_msg msg;
-
-    PTP_LOG_INFO("%s.\n", __FUNCTION__);
-
-    if (tod_device_file == NULL)
-    {
-        PTP_LOG_ERR("%s: device already close.\n", __FUNCTION__);
-        return 0;
-    }
-
-    memset(&msg, 0x00, sizeof(struct tod_device_msg));
-    msg.type = TOD_DEVICE_MSG_CLOSE;
-    msg.file = tod_device_file;
-
-    result = tod_device_sync_msg_send((uint8_t*)(&msg), sizeof(struct tod_device_msg), NULL, 0);
-    if (result != 0)
-    {
-        PTP_LOG_ERR("%s: tod_device_sync_msg_send failed, result: %d.\n", __FUNCTION__, result);
-        return -EINVAL;
-    }
-    PTP_LOG_INFO("%s: file %px close success.\n", __FUNCTION__, tod_device_file);
-    tod_device_file = NULL;
-
-    return 0;
+	int32_t result = 0;
+	struct tod_device_msg msg;
+
+	PTP_LOG_INFO("%s.\n", __func__);
+
+	if (tod_device_file == NULL) {
+		PTP_LOG_ERR("%s: device already close.\n", __func__);
+		return 0;
+	}
+
+	memset(&msg, 0x00, sizeof(struct tod_device_msg));
+	msg.type = TOD_DEVICE_MSG_CLOSE;
+	msg.file = tod_device_file;
+
+	result = tod_device_sync_msg_send((uint8_t *)(&msg),
+									  sizeof(struct tod_device_msg), NULL, 0);
+	if (result != 0) {
+		PTP_LOG_ERR("%s: tod_device_sync_msg_send failed, result: %d.\n",
+					__func__, result);
+		return -EINVAL;
+	}
+	PTP_LOG_INFO("%s: file %px close success.\n", __func__,
+				 tod_device_file);
+	tod_device_file = NULL;
+
+	return 0;
 }
 
-static ssize_t tod_device_read(struct file *file, char *buf, size_t count, loff_t *f_pos)
+static ssize_t tod_device_read(struct file *file, char *buf, size_t count,
+							   loff_t *f_pos)
 {
-    int32_t result = 0;
-    uint8_t *resp = NULL;
-    struct tod_device_msg msg;
-
-    PTP_LOG_INFO("%s.\n", __FUNCTION__);
-
-    if (tod_device_file == NULL)
-    {
-        PTP_LOG_ERR("%s: no such device.\n", __FUNCTION__);
-        return -ENODEV;
-    }
-
-    if (count > (2048 - 12 - sizeof(int32_t) - sizeof(size_t))) // common bar: 2048 - 12, result: 4, count: 8.
-    {
-        PTP_LOG_ERR("%s: no space left on device.\n", __FUNCTION__);
-        return -ENOSPC;
-    }
-
-    resp = (uint8_t*)kmalloc(sizeof(size_t) + count, GFP_KERNEL);
-    if (resp == NULL)
-    {
-        PTP_LOG_ERR("%s: no space left on device.\n", __FUNCTION__);
-        return -ENOSPC;
-    }
-
-    memset(&msg, 0x00, sizeof(struct tod_device_msg));
-    msg.type = TOD_DEVICE_MSG_READ;
-    msg.count = count;
-    msg.file = tod_device_file;
-
-    result = tod_device_sync_msg_send((uint8_t*)(&msg), sizeof(struct tod_device_msg), resp, sizeof(size_t) + count);
-    if (result != 0)
-    {
-        kfree(resp);
-        PTP_LOG_ERR("%s: tod_device_sync_msg_send failed, result: %d.\n", __FUNCTION__, result);
-        return -EINVAL;
-    }
-
-    count = *((size_t*)(resp));
-    if (count > msg.count)
-    {
-        PTP_LOG_ERR("%s: no space left on device.\n", __FUNCTION__);
-        kfree(resp);
-        return -ENOSPC;
-    }
-
-    result = copy_to_user(buf, resp + sizeof(size_t), count);
-    if (result != 0)
-    {
-        kfree(resp);
-        PTP_LOG_ERR("%s: copy_to_user failed, result: %d.\n", __FUNCTION__, result);
-        return -EINVAL;
-    }
-
-    kfree(resp);
-    PTP_LOG_INFO("%s: file %px read %lu bytes success.\n", __FUNCTION__, tod_device_file, count);
-
-    return count;
+	int32_t result = 0;
+	uint8_t *resp = NULL;
+	struct tod_device_msg msg;
+
+	PTP_LOG_INFO("%s.\n", __func__);
+
+	if (tod_device_file == NULL) {
+		PTP_LOG_ERR("%s: no such device.\n", __func__);
+		return -ENODEV;
+	}
+
+	// common bar: 2048 - 12, result: 4, count: 8.
+	if (count > (2048 - 12 - sizeof(int32_t) - sizeof(size_t))) {
+		PTP_LOG_ERR("%s: no space left on device.\n", __func__);
+		return -ENOSPC;
+	}
+
+	resp = (uint8_t *)kmalloc(sizeof(size_t) + count, GFP_KERNEL);
+	if (resp == NULL) {
+		PTP_LOG_ERR("%s: no space left on device.\n", __func__);
+		return -ENOSPC;
+	}
+
+	memset(&msg, 0x00, sizeof(struct tod_device_msg));
+	msg.type = TOD_DEVICE_MSG_READ;
+	msg.count = count;
+	msg.file = tod_device_file;
+
+	result = tod_device_sync_msg_send((uint8_t *)(&msg),
+									  sizeof(struct tod_device_msg), resp,
+									  sizeof(size_t) + count);
+	if (result != 0) {
+		kfree(resp);
+		PTP_LOG_ERR("%s: tod_device_sync_msg_send failed, result: %d.\n",
+					__func__, result);
+		return -EINVAL;
+	}
+
+	count = *((size_t *)(resp));
+	if (count > msg.count) {
+		PTP_LOG_ERR("%s: no space left on device.\n", __func__);
+		return -ENOSPC;
+	}
+
+	result = copy_to_user(buf, resp + sizeof(size_t), count);
+	if (result != 0) {
+		kfree(resp);
+		PTP_LOG_ERR("%s: copy_to_user failed, result: %d.\n", __func__,
+					result);
+		return -EINVAL;
+	}
+
+	kfree(resp);
+	PTP_LOG_INFO("%s: file %px read %lu bytes success.\n", __func__,
+				 tod_device_file, count);
+
+	return count;
 }
 
-static ssize_t tod_device_write(struct file *file, const char *buf, size_t count, loff_t *f_pos)
+static ssize_t tod_device_write(struct file *file, const char *buf,
+								size_t count, loff_t *f_pos)
 {
-    int32_t result = 0;
-    struct tod_device_msg msg;
-
-    PTP_LOG_INFO("%s.\n", __FUNCTION__);
-
-    if (tod_device_file == NULL)
-    {
-        PTP_LOG_ERR("%s: no such device.\n", __FUNCTION__);
-        return -ENODEV;
-    }
-
-    if (count > sizeof(msg.data))
-    {
-        PTP_LOG_ERR("%s: no space left on device.\n", __FUNCTION__);
-        return -ENOSPC;
-    }
-
-    memset(&msg, 0x00, sizeof(struct tod_device_msg));
-    msg.type = TOD_DEVICE_MSG_WRITE;
-    msg.count = count;
-    msg.file = tod_device_file;
-    result = copy_from_user(msg.data, buf, count);
-    if (result != 0)
-    {
-        PTP_LOG_ERR("%s: copy_from_user failed, result: %d.\n", __FUNCTION__, result);
-        return -EINVAL;
-    }
-
-    result = tod_device_sync_msg_send((uint8_t*)(&msg), sizeof(struct tod_device_msg), (uint8_t*)(&count), sizeof(size_t));
-    if (result != 0)
-    {
-        PTP_LOG_ERR("%s: tod_device_sync_msg_send failed, result: %d.\n", __FUNCTION__, result);
-        return -EINVAL;
-    }
-    PTP_LOG_INFO("%s: file %px write %lu bytes success.\n", __FUNCTION__, tod_device_file, count);
-
-    return count;
+	int32_t result = 0;
+	struct tod_device_msg msg;
+
+	PTP_LOG_INFO("%s.\n", __func__);
+
+	if (tod_device_file == NULL) {
+		PTP_LOG_ERR("%s: no such device.\n", __func__);
+		return -ENODEV;
+	}
+
+	if (count > sizeof(msg.data)) {
+		PTP_LOG_ERR("%s: no space left on device.\n", __func__);
+		return -ENOSPC;
+	}
+
+	memset(&msg, 0x00, sizeof(struct tod_device_msg));
+	msg.type = TOD_DEVICE_MSG_WRITE;
+	msg.count = count;
+	msg.file = tod_device_file;
+	result = copy_from_user(msg.data, buf, count);
+	if (result != 0) {
+		PTP_LOG_ERR("%s: copy_from_user failed, result: %d.\n", __func__,
+					result);
+		return -EINVAL;
+	}
+
+	result = tod_device_sync_msg_send((uint8_t *)(&msg),
+									  sizeof(struct tod_device_msg),
+									  (uint8_t *)(&count), sizeof(size_t));
+	if (result != 0) {
+		PTP_LOG_ERR("%s: tod_device_sync_msg_send failed, result: %d.\n",
+					__func__, result);
+		return -EINVAL;
+	}
+	PTP_LOG_INFO("%s: file %px write %lu bytes success.\n", __FUNCTION__,
+				 tod_device_file, count);
+
+	return count;
 }
 
-static __poll_t tod_device_poll(struct file *file, struct poll_table_struct *wait)
+static __poll_t tod_device_poll(struct file *file,
+								struct poll_table_struct *wait)
 {
-    int32_t result = 0;
-    uint16_t poll_mask = 0;
-    struct tod_device_msg msg;
-
-    PTP_LOG_INFO("%s.\n", __FUNCTION__);
-
-    if (tod_device_file == NULL)
-    {
-        PTP_LOG_ERR("%s: no such device.\n", __FUNCTION__);
-        return POLLERR;
-    }
-
-    memset(&msg, 0x00, sizeof(struct tod_device_msg));
-    msg.type = TOD_DEVICE_MSG_POLL;
-    msg.file = tod_device_file;
-
-    result = tod_device_sync_msg_send((uint8_t*)(&msg), sizeof(struct tod_device_msg), (uint8_t*)(&poll_mask), sizeof(uint16_t));
-    if (result != 0)
-    {
-        PTP_LOG_ERR("%s: tod_device_sync_msg_send failed, result: %d.\n", __FUNCTION__, result);
-        return POLLERR;
-    }
-    PTP_LOG_INFO("%s: file %px poll mask 0x%04x success.\n", __FUNCTION__, tod_device_file, poll_mask);
-
-    return poll_mask;
+	int32_t result = 0;
+	uint16_t poll_mask = 0;
+	struct tod_device_msg msg;
+
+	PTP_LOG_INFO("%s.\n", __func__);
+
+	if (tod_device_file == NULL) {
+		PTP_LOG_ERR("%s: no such device.\n", __func__);
+		return POLLERR;
+	}
+
+	memset(&msg, 0x00, sizeof(struct tod_device_msg));
+	msg.type = TOD_DEVICE_MSG_POLL;
+	msg.file = tod_device_file;
+
+	result = tod_device_sync_msg_send((uint8_t *)(&msg),
+									  sizeof(struct tod_device_msg),
+									  (uint8_t *)(&poll_mask),
+									  sizeof(uint16_t));
+	if (result != 0) {
+		PTP_LOG_ERR("%s: tod_device_sync_msg_send failed, result: %d.\n",
+					__func__, result);
+		return POLLERR;
+	}
+	PTP_LOG_INFO("%s: file %px poll mask 0x%04x success.\n", __func__,
+				 tod_device_file, poll_mask);
+
+	return poll_mask;
 }
 
-static long tod_device_ioctl(struct file *file, uint32_t request, unsigned long args)
+static long tod_device_ioctl(struct file *file, uint32_t request,
+							 unsigned long args)
 {
-    int32_t result = 0;
-    uint8_t *resp = NULL;
-    struct tod_device_msg msg;
-
-    PTP_LOG_INFO("%s.\n", __FUNCTION__);
-
-    if (tod_device_file == NULL)
-    {
-        PTP_LOG_ERR("%s: no such device.\n", __FUNCTION__);
-        return -ENODEV;
-    }
-
-    resp = (uint8_t*)kmalloc(sizeof(struct termios), GFP_KERNEL);
-    if (resp == NULL)
-    {
-        PTP_LOG_ERR("%s: no space left on device.\n", __FUNCTION__);
-        return -ENOSPC;
-    }
-
-    memset(&msg, 0x00, sizeof(struct tod_device_msg));
-    msg.type = TOD_DEVICE_MSG_IOCTL;
-    msg.file = tod_device_file;
-    msg.command = request;
-
-    if ((struct termios*)args != NULL)
-    {
-        result = copy_from_user(msg.data, (uint8_t*)args, sizeof(struct termios));
-        if (result != 0)
-        {
-            PTP_LOG_ERR("%s: copy_from_user failed, result: %d.\n", __FUNCTION__, result);
-            kfree(resp);
-            return -EINVAL;
-        }
-    }
-
-    result = tod_device_sync_msg_send((uint8_t*)(&msg), sizeof(struct tod_device_msg), resp, sizeof(struct termios));
-    if (result != 0)
-    {
-        kfree(resp);
-        PTP_LOG_ERR("%s: tod_device_sync_msg_send failed, result: %d.\n", __FUNCTION__, result);
-        return -EINVAL;
-    }
-
-    if ((struct termios*)args != NULL)
-    {
-        result = copy_to_user((uint8_t*)args, resp, sizeof(struct termios));
-        if (result != 0)
-        {
-            kfree(resp);
-            PTP_LOG_ERR("%s: copy_to_user failed, result: %d.\n", __FUNCTION__, result);
-            return -EINVAL;
-        }
-    }
-
-    kfree(resp);
-    PTP_LOG_INFO("%s: file %px ioctl success.\n", __FUNCTION__, tod_device_file);
-
-    return 0;
+	int32_t result = 0;
+	uint8_t *resp = NULL;
+	struct tod_device_msg msg;
+
+	PTP_LOG_INFO("%s.\n", __func__);
+
+	if (tod_device_file == NULL) {
+		PTP_LOG_ERR("%s: no such device.\n", __func__);
+		return -ENODEV;
+	}
+
+	resp = (uint8_t *)kmalloc(sizeof(struct termios), GFP_KERNEL);
+	if (resp == NULL) {
+		PTP_LOG_ERR("%s: no space left on device.\n", __func__);
+		return -ENOSPC;
+	}
+
+	memset(&msg, 0x00, sizeof(struct tod_device_msg));
+	msg.type = TOD_DEVICE_MSG_IOCTL;
+	msg.file = tod_device_file;
+	msg.command = request;
+
+	if ((struct termios *)args != NULL) {
+		result = copy_from_user(msg.data, (uint8_t *)args,
+								sizeof(struct termios));
+		if (result != 0) {
+			PTP_LOG_ERR("%s: copy_from_user failed, result: %d.\n",
+						__func__, result);
+			return -EINVAL;
+		}
+	}
+
+	result = tod_device_sync_msg_send((uint8_t *)(&msg),
+									  sizeof(struct tod_device_msg), resp,
+									  sizeof(struct termios));
+	if (result != 0) {
+		kfree(resp);
+		PTP_LOG_ERR("%s: tod_device_sync_msg_send failed, result: %d.\n",
+					__func__, result);
+		return -EINVAL;
+	}
+
+	if ((struct termios *)args != NULL) {
+		result = copy_to_user((uint8_t *)args, resp, sizeof(struct termios));
+		if (result != 0) {
+			kfree(resp);
+			PTP_LOG_ERR("%s: copy_to_user failed, result: %d.\n", __func__,
+						result);
+			return -EINVAL;
+		}
+	}
+
+	kfree(resp);
+	PTP_LOG_INFO("%s: file %px ioctl success.\n", __func__,
+				 tod_device_file);
+
+	return 0;
 }
 
-struct file_operations tod_device_ops = {
-    .owner          = THIS_MODULE,
-    .open           = tod_device_open,
-    .release        = tod_device_release,
-    .read           = tod_device_read,
-    .write          = tod_device_write,
-    .poll           = tod_device_poll,
-    .unlocked_ioctl = tod_device_ioctl
-};
+struct file_operations tod_device_ops = { .owner = THIS_MODULE,
+										  .open = tod_device_open,
+										  .release = tod_device_release,
+										  .read = tod_device_read,
+										  .write = tod_device_write,
+										  .poll = tod_device_poll,
+										  .unlocked_ioctl = tod_device_ioctl };
 
 static int32_t __init tod_device_init(void)
 {
-    int32_t result = 0;
-
-    PTP_LOG_INFO("%s: start.\n", __FUNCTION__);
-
-    result = alloc_chrdev_region(&tod_device_no, 0, 1, TOD_DEVICE_NAME);
-    if (result < 0)
-    {
-        PTP_LOG_ERR("%s: alloc_chrdev_region failed, result: %d.\n", __FUNCTION__, result);
-        return -EINVAL;
-    }
-
-    tod_device_cdev = cdev_alloc();
-    if (tod_device_cdev == NULL)
-    {
-        PTP_LOG_ERR("%s: cdev_alloc failed, result: %d.\n", __FUNCTION__, result);
-        unregister_chrdev_region(tod_device_no, 1);
-        return -EINVAL;
-    }
-
-    cdev_init(tod_device_cdev, &tod_device_ops);
-    tod_device_cdev->owner = THIS_MODULE;
-    result = cdev_add(tod_device_cdev, tod_device_no, 1);
-    if (result != 0)
-    { 
-        PTP_LOG_ERR("%s: cdev_add failed, result: %d.\n", __FUNCTION__, result);
-        unregister_chrdev_region(tod_device_no, 1);
-        return -EINVAL;
-    }
-
-    tod_device_class = class_create(THIS_MODULE, TOD_DEVICE_NAME);
-    if (IS_ERR(tod_device_class))
-    {
-        PTP_LOG_ERR("%s: class_create failed, err: %lu.\n", __FUNCTION__, PTR_ERR(tod_device_class));
-        cdev_del(tod_device_cdev);
-        unregister_chrdev_region(tod_device_no, 1);
-        return -EINVAL;
-    }
-
-    tod_device = device_create(tod_device_class, NULL, tod_device_no, NULL, TOD_DEVICE_NAME);
-    if (IS_ERR(tod_device))
-    {
-        PTP_LOG_ERR("%s: device_create failed, err: %lu.\n", __FUNCTION__, PTR_ERR(tod_device));
-        class_destroy(tod_device_class);
-        cdev_del(tod_device_cdev);
-        unregister_chrdev_region(tod_device_no, 1);
-        return -EINVAL;
-    }
-
-    PTP_LOG_INFO("%s: success.\n", __FUNCTION__);
-
-    return 0;
+	int32_t result = 0;
+
+	PTP_LOG_INFO("%s: start.\n", __func__);
+
+	result = alloc_chrdev_region(&tod_device_no, 0, 1, TOD_DEVICE_NAME);
+	if (result < 0) {
+		PTP_LOG_ERR("%s: alloc_chrdev_region failed, result: %d.\n",
+					__func__, result);
+		return -EINVAL;
+	}
+
+	tod_device_cdev = cdev_alloc();
+	if (tod_device_cdev == NULL) {
+		PTP_LOG_ERR("%s: cdev_alloc failed, result: %d.\n", __func__,
+					result);
+		unregister_chrdev_region(tod_device_no, 1);
+		return -EINVAL;
+	}
+
+	cdev_init(tod_device_cdev, &tod_device_ops);
+	tod_device_cdev->owner = THIS_MODULE;
+	result = cdev_add(tod_device_cdev, tod_device_no, 1);
+	if (result != 0) {
+		PTP_LOG_ERR("%s: cdev_add failed, result: %d.\n", __func__, result);
+		unregister_chrdev_region(tod_device_no, 1);
+		return -EINVAL;
+	}
+
+	tod_device_class = class_create(THIS_MODULE, TOD_DEVICE_NAME);
+	if (IS_ERR(tod_device_class)) {
+		PTP_LOG_ERR("%s: class_create failed, err: %lu.\n", __func__,
+					PTR_ERR(tod_device_class));
+		cdev_del(tod_device_cdev);
+		unregister_chrdev_region(tod_device_no, 1);
+		return -EINVAL;
+	}
+
+	tod_device = device_create(tod_device_class, NULL, tod_device_no, NULL,
+							   TOD_DEVICE_NAME);
+	if (IS_ERR(tod_device)) {
+		PTP_LOG_ERR("%s: device_create failed, err: %lu.\n", __func__,
+					PTR_ERR(tod_device));
+		class_destroy(tod_device_class);
+		cdev_del(tod_device_cdev);
+		unregister_chrdev_region(tod_device_no, 1);
+		return -EINVAL;
+	}
+
+	printk(KERN_INFO "%s: success.\n", __func__);
+
+	return 0;
 }
 
 static void __exit tod_device_exit(void)
 {
-    PTP_LOG_INFO("%s: start.\n", __FUNCTION__);
+	PTP_LOG_INFO("%s: start.\n", __func__);
 
-    device_destroy(tod_device_class, tod_device_no);
+	device_destroy(tod_device_class, tod_device_no);
 
-    class_destroy(tod_device_class);
+	class_destroy(tod_device_class);
 
-    cdev_del(tod_device_cdev);
+	cdev_del(tod_device_cdev);
 
-    unregister_chrdev_region(tod_device_no, 1);
+	unregister_chrdev_region(tod_device_no, 1);
 
-    PTP_LOG_ERR("%s: success.\n", __FUNCTION__);
+	PTP_LOG_ERR("%s: success.\n", __func__);
 }
 
 module_init(tod_device_init);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver.h b/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver.h
index b02f70a14adb18f05f6fbcb80188e89d92f47483..65d1868409ee82e501b054e34406d9380b024111 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver.h
@@ -3,22 +3,21 @@
 
 #include <linux/types.h>
 
-#define TOD_DEVICE_MSG_OPEN         ((uint32_t)(0))
-#define TOD_DEVICE_MSG_CLOSE        ((uint32_t)(1))
-#define TOD_DEVICE_MSG_READ         ((uint32_t)(2))
-#define TOD_DEVICE_MSG_WRITE        ((uint32_t)(3))
-#define TOD_DEVICE_MSG_POLL         ((uint32_t)(4))
-#define TOD_DEVICE_MSG_IOCTL        ((uint32_t)(5))
+#define TOD_DEVICE_MSG_OPEN ((uint32_t)(0))
+#define TOD_DEVICE_MSG_CLOSE ((uint32_t)(1))
+#define TOD_DEVICE_MSG_READ ((uint32_t)(2))
+#define TOD_DEVICE_MSG_WRITE ((uint32_t)(3))
+#define TOD_DEVICE_MSG_POLL ((uint32_t)(4))
+#define TOD_DEVICE_MSG_IOCTL ((uint32_t)(5))
 
-#define TOD_DEVICE_DATA_LEN         ((uint32_t)(512))
+#define TOD_DEVICE_DATA_LEN ((uint32_t)(512))
 
-struct tod_device_msg
-{
-    uint32_t type;
-    uint32_t command;
-    size_t   count;
-    void*    file;
-    uint8_t  data[TOD_DEVICE_DATA_LEN];
+struct tod_device_msg {
+	uint32_t type;
+	uint32_t command;
+	size_t count;
+	void *file;
+	uint8_t data[TOD_DEVICE_DATA_LEN];
 };
 
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver_stub.c b/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver_stub.c
index 890efa56d9fc5b373e77f68a0ab9518d6fcc448b..5cad966447f81b5905825e598161a291bf7d404b 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver_stub.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_ptp/tod_driver_stub.c
@@ -1,31 +1,28 @@
 #include <linux/module.h>
 //#include "../msg_chan_driver/msg_chan_pub.h"
 #include <linux/dinghai/dh_cmd.h>
-#if 0
-typedef uint16_t (*rsc_recv_func_ptr)(uint8_t *pay_load, uint16_t len, uint8_t *reps_buffer, uint16_t *reps_len);
 
-static rsc_recv_func_ptr g_riscv_event[100] = {0};
+typedef uint16_t (*rsc_recv_func_ptr)(uint8_t *pay_load, uint16_t len,
+									  uint8_t *reps_buffer, uint16_t *reps_len);
+
+static rsc_recv_func_ptr g_riscv_event[100] = { 0 };
 
 uint16_t RSC_MsgProRegister(uint8_t event_id, rsc_recv_func_ptr msg_pro_fun)
 {
-    if(100 <= event_id)
-        return 0;
-    g_riscv_event[event_id] = msg_pro_fun;
-    return 0;
+	g_riscv_event[event_id] = msg_pro_fun;
+	return 0;
 }
 EXPORT_SYMBOL(RSC_MsgProRegister);
 
 uint16_t RSC_MsgProUnregister(uint8_t event_id)
 {
-    if(100 <= event_id)
-        return 0;
-    g_riscv_event[event_id] = NULL;
-    return 0;
+	g_riscv_event[event_id] = NULL;
+	return 0;
 }
 EXPORT_SYMBOL(RSC_MsgProUnregister);
 
-
-// int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in, struct zxdh_msg_recviver_mem *result)
+// int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in, struct
+// zxdh_msg_recviver_mem *result)
 // {
 //     uint16_t reps_len = 0;
 //     uint8_t *reps_buffer = NULL;
@@ -37,10 +34,12 @@ EXPORT_SYMBOL(RSC_MsgProUnregister);
 //         printk(KERN_ERR "%s: no space left on device.\n", __FUNCTION__);
 //         return -ENOSPC;
 //     }
-//     memset(reps_buffer, 0x00, 2048 - 12 + 4); // 消息应答净荷长度最大2048 - 12, 再加上4B消息头
+//     memset(reps_buffer, 0x00, 2048 - 12 + 4); // 消息应答净荷长度最大2048 -
+//     12, 再加上4B消息头
 
 //     ptr = g_riscv_event[in->event_id];
-//     if (ptr(in->payload_addr, in->payload_len, reps_buffer + 4, &reps_len) != 0)
+//     if (ptr(in->payload_addr, in->payload_len, reps_buffer + 4, &reps_len) !=
+//     0)
 //     {
 //         kfree(reps_buffer);
 //         printk(KERN_ERR "%s: rsc_recv_func_ptr failed.\n", __FUNCTION__);
@@ -59,4 +58,3 @@ EXPORT_SYMBOL(RSC_MsgProUnregister);
 // EXPORT_SYMBOL(zxdh_bar_chan_sync_msg_send);
 
 MODULE_LICENSE("GPL");
-#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp.c b/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp.c
index 7724802904af33d57ad8bf911947c051dd272225..de2ea47c0ba1b93292042f6fdff475071b360591 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp.c
@@ -7,7 +7,6 @@
 #include <linux/mod_devicetable.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-
 #include "en_aux.h"
 #include "zxdh_ptp.h"
 #include "zxdh_ptp_regs.h"
@@ -15,446 +14,449 @@
 
 #define ZXDH_PF_BAR0 0
 
-char pps[3][15] = {
-    "pp1s_out",
-    "pp1s_1588",
-    "pp1s_external"
-};
+char pps[3][15] = { "pp1s_out", "pp1s_1588", "pp1s_external" };
 
 // all tsn timer name: tsn0 tsn1 tsn2 tsn3, so the return value is 0/1/2/3.
-static int get_tsn_timer_no(char *clock_name)
+static unsigned int get_tsn_timer_no(char *clock_name)
 {
-    int ret;
-    int timer_no;
-    ret = sscanf(clock_name, "tsn%d", &timer_no);
-    if(ret != 1)
-    {
-        PTP_LOG_INFO(" tsn: %s get timer no fail!\n", clock_name);
-        return -1;
-    }
-    return timer_no;
+	return clock_name[3] - '0';
 }
 
 static uint32_t tsn_clock_cycle_integer_reg(int timer_no)
 {
-    if (0 == timer_no)
-        return TSN_CLOCK_CYCLE_INTEGER(0);
-    else if (1 == timer_no)
-        return TSN_CLOCK_CYCLE_INTEGER(1);
-    else if (2 == timer_no)
-        return TSN_CLOCK_CYCLE_INTEGER(2);
-    else if (3 == timer_no)
-        return TSN_CLOCK_CYCLE_INTEGER(3);
-
-    return 0;
+	if (0 == timer_no)
+		return TSN_CLOCK_CYCLE_INTEGER(0);
+	else if (1 == timer_no)
+		return TSN_CLOCK_CYCLE_INTEGER(1);
+	else if (2 == timer_no)
+		return TSN_CLOCK_CYCLE_INTEGER(2);
+	else if (3 == timer_no)
+		return TSN_CLOCK_CYCLE_INTEGER(3);
+
+	return 0;
 }
 
 static uint32_t tsn_clock_cycle_fraction_reg(int timer_no)
 {
-    if (0 == timer_no)
-        return TSN_CLOCK_CYCLE_FRACTION(0);
-    else if (1 == timer_no)
-        return TSN_CLOCK_CYCLE_FRACTION(1);
-    else if (2 == timer_no)
-        return TSN_CLOCK_CYCLE_FRACTION(2);
-    else if (3 == timer_no)
-        return TSN_CLOCK_CYCLE_FRACTION(3);
-
-    return 0;
+	if (0 == timer_no)
+		return TSN_CLOCK_CYCLE_FRACTION(0);
+	else if (1 == timer_no)
+		return TSN_CLOCK_CYCLE_FRACTION(1);
+	else if (2 == timer_no)
+		return TSN_CLOCK_CYCLE_FRACTION(2);
+	else if (3 == timer_no)
+		return TSN_CLOCK_CYCLE_FRACTION(3);
+
+	return 0;
 }
 
 #define GET_TSN_ADJUST_NANO_REG(tsn_no)            \
-    ({                                             \
-        if (0 == tsn_no)                           \
-            nano_sec_reg = TSN_ADJUST_NANO_SEC(0); \
-        else if (1 == tsn_no)                      \
-            nano_sec_reg = TSN_ADJUST_NANO_SEC(1); \
-        else if (2 == tsn_no)                      \
-            nano_sec_reg = TSN_ADJUST_NANO_SEC(2); \
-        else if (3 == tsn_no)                      \
-            nano_sec_reg = TSN_ADJUST_NANO_SEC(3); \
-    })
+	({                                             \
+		if (0 == tsn_no)                           \
+			nano_sec_reg = TSN_ADJUST_NANO_SEC(0); \
+		else if (1 == tsn_no)                      \
+			nano_sec_reg = TSN_ADJUST_NANO_SEC(1); \
+		else if (2 == tsn_no)                      \
+			nano_sec_reg = TSN_ADJUST_NANO_SEC(2); \
+		else if (3 == tsn_no)                      \
+			nano_sec_reg = TSN_ADJUST_NANO_SEC(3); \
+	})
 
 #define GET_TSN_ADJUST_LOW_SEC_REG(tsn_no)          \
-    ({                                              \
-        if (0 == tsn_no)                            \
-            low_sec_reg = TSN_ADJUST_LOW_SECOND(0); \
-        else if (1 == tsn_no)                       \
-            low_sec_reg = TSN_ADJUST_LOW_SECOND(1); \
-        else if (2 == tsn_no)                       \
-            low_sec_reg = TSN_ADJUST_LOW_SECOND(2); \
-        else if (3 == tsn_no)                       \
-            low_sec_reg = TSN_ADJUST_LOW_SECOND(3); \
-    })
+	({                                              \
+		if (0 == tsn_no)                            \
+			low_sec_reg = TSN_ADJUST_LOW_SECOND(0); \
+		else if (1 == tsn_no)                       \
+			low_sec_reg = TSN_ADJUST_LOW_SECOND(1); \
+		else if (2 == tsn_no)                       \
+			low_sec_reg = TSN_ADJUST_LOW_SECOND(2); \
+		else if (3 == tsn_no)                       \
+			low_sec_reg = TSN_ADJUST_LOW_SECOND(3); \
+	})
 
 #define GET_TSN_ADJUST_HIGH_SEC_REG(tsn_no)           \
-    ({                                                \
-        if (0 == tsn_no)                              \
-            high_sec_reg = TSN_ADJUST_HIGH_SECOND(0); \
-        else if (1 == tsn_no)                         \
-            high_sec_reg = TSN_ADJUST_HIGH_SECOND(1); \
-        else if (2 == tsn_no)                         \
-            high_sec_reg = TSN_ADJUST_HIGH_SECOND(2); \
-        else if (3 == tsn_no)                         \
-            high_sec_reg = TSN_ADJUST_HIGH_SECOND(3); \
-    })
+	({                                                \
+		if (0 == tsn_no)                              \
+			high_sec_reg = TSN_ADJUST_HIGH_SECOND(0); \
+		else if (1 == tsn_no)                         \
+			high_sec_reg = TSN_ADJUST_HIGH_SECOND(1); \
+		else if (2 == tsn_no)                         \
+			high_sec_reg = TSN_ADJUST_HIGH_SECOND(2); \
+		else if (3 == tsn_no)                         \
+			high_sec_reg = TSN_ADJUST_HIGH_SECOND(3); \
+	})
 
 #define GET_TSN_ADJUST_FRAC_NANO_SEC_REG(tsn_no)         \
-    ({                                                   \
-        if (0 == tsn_no)                                 \
-            frac_nano_reg = TSN_ADJUST_FRAC_NANO_SEC(0); \
-        else if (1 == tsn_no)                            \
-            frac_nano_reg = TSN_ADJUST_FRAC_NANO_SEC(1); \
-        else if (2 == tsn_no)                            \
-            frac_nano_reg = TSN_ADJUST_FRAC_NANO_SEC(2); \
-        else if (3 == tsn_no)                            \
-            frac_nano_reg = TSN_ADJUST_FRAC_NANO_SEC(3); \
-    })
+	({                                                   \
+		if (0 == tsn_no)                                 \
+			frac_nano_reg = TSN_ADJUST_FRAC_NANO_SEC(0); \
+		else if (1 == tsn_no)                            \
+			frac_nano_reg = TSN_ADJUST_FRAC_NANO_SEC(1); \
+		else if (2 == tsn_no)                            \
+			frac_nano_reg = TSN_ADJUST_FRAC_NANO_SEC(2); \
+		else if (3 == tsn_no)                            \
+			frac_nano_reg = TSN_ADJUST_FRAC_NANO_SEC(3); \
+	})
 
 #define GET_TSN_LATCH_NANO_REG(tsn_no)            \
-    ({                                            \
-        if (0 == tsn_no)                          \
-            nano_sec_reg = TSN_LATCH_NANO_SEC(0); \
-        else if (1 == tsn_no)                     \
-            nano_sec_reg = TSN_LATCH_NANO_SEC(1); \
-        else if (2 == tsn_no)                     \
-            nano_sec_reg = TSN_LATCH_NANO_SEC(2); \
-        else if (3 == tsn_no)                     \
-            nano_sec_reg = TSN_LATCH_NANO_SEC(3); \
-    })
+	({                                            \
+		if (0 == tsn_no)                          \
+			nano_sec_reg = TSN_LATCH_NANO_SEC(0); \
+		else if (1 == tsn_no)                     \
+			nano_sec_reg = TSN_LATCH_NANO_SEC(1); \
+		else if (2 == tsn_no)                     \
+			nano_sec_reg = TSN_LATCH_NANO_SEC(2); \
+		else if (3 == tsn_no)                     \
+			nano_sec_reg = TSN_LATCH_NANO_SEC(3); \
+	})
 
 #define GET_TSN_LATCH_LOW_SEC_REG(tsn_no)          \
-    ({                                             \
-        if (0 == tsn_no)                           \
-            low_sec_reg = TSN_LATCH_LOW_SECOND(0); \
-        else if (1 == tsn_no)                      \
-            low_sec_reg = TSN_LATCH_LOW_SECOND(1); \
-        else if (2 == tsn_no)                      \
-            low_sec_reg = TSN_LATCH_LOW_SECOND(2); \
-        else if (3 == tsn_no)                      \
-            low_sec_reg = TSN_LATCH_LOW_SECOND(3); \
-    })
+	({                                             \
+		if (0 == tsn_no)                           \
+			low_sec_reg = TSN_LATCH_LOW_SECOND(0); \
+		else if (1 == tsn_no)                      \
+			low_sec_reg = TSN_LATCH_LOW_SECOND(1); \
+		else if (2 == tsn_no)                      \
+			low_sec_reg = TSN_LATCH_LOW_SECOND(2); \
+		else if (3 == tsn_no)                      \
+			low_sec_reg = TSN_LATCH_LOW_SECOND(3); \
+	})
 
 #define GET_TSN_LATCH_HIGH_SEC_REG(tsn_no)           \
-    ({                                               \
-        if (0 == tsn_no)                             \
-            high_sec_reg = TSN_LATCH_HIGH_SECOND(0); \
-        else if (1 == tsn_no)                        \
-            high_sec_reg = TSN_LATCH_HIGH_SECOND(1); \
-        else if (2 == tsn_no)                        \
-            high_sec_reg = TSN_LATCH_HIGH_SECOND(2); \
-        else if (3 == tsn_no)                        \
-            high_sec_reg = TSN_LATCH_HIGH_SECOND(3); \
-    })
+	({                                               \
+		if (0 == tsn_no)                             \
+			high_sec_reg = TSN_LATCH_HIGH_SECOND(0); \
+		else if (1 == tsn_no)                        \
+			high_sec_reg = TSN_LATCH_HIGH_SECOND(1); \
+		else if (2 == tsn_no)                        \
+			high_sec_reg = TSN_LATCH_HIGH_SECOND(2); \
+		else if (3 == tsn_no)                        \
+			high_sec_reg = TSN_LATCH_HIGH_SECOND(3); \
+	})
 
 #define GET_TSN_LATCH_FRAC_NANO_SEC_REG(tsn_no)         \
-    ({                                                  \
-        if (0 == tsn_no)                                \
-            frac_nano_reg = TSN_LATCH_FRAC_NANO_SEC(0); \
-        else if (1 == tsn_no)                           \
-            frac_nano_reg = TSN_LATCH_FRAC_NANO_SEC(1); \
-        else if (2 == tsn_no)                           \
-            frac_nano_reg = TSN_LATCH_FRAC_NANO_SEC(2); \
-        else if (3 == tsn_no)                           \
-            frac_nano_reg = TSN_LATCH_FRAC_NANO_SEC(3); \
-    })
+	({                                                  \
+		if (0 == tsn_no)                                \
+			frac_nano_reg = TSN_LATCH_FRAC_NANO_SEC(0); \
+		else if (1 == tsn_no)                           \
+			frac_nano_reg = TSN_LATCH_FRAC_NANO_SEC(1); \
+		else if (2 == tsn_no)                           \
+			frac_nano_reg = TSN_LATCH_FRAC_NANO_SEC(2); \
+		else if (3 == tsn_no)                           \
+			frac_nano_reg = TSN_LATCH_FRAC_NANO_SEC(3); \
+	})
 
 #define GET_PPS_LATCH_TSN_NANO_REG(tsn_no)            \
-    ({                                                \
-        if (1 == tsn_no)                              \
-            nano_sec_reg = PPS_LATCH_TSN_NANO_SEC(0); \
-        else if (2 == tsn_no)                         \
-            nano_sec_reg = PPS_LATCH_TSN_NANO_SEC(1); \
-        else if (3 == tsn_no)                         \
-            nano_sec_reg = PPS_LATCH_TSN_NANO_SEC(2); \
-        else if (4 == tsn_no)                         \
-            nano_sec_reg = PPS_LATCH_TSN_NANO_SEC(3); \
-    })
+	({                                                \
+		if (1 == tsn_no)                              \
+			nano_sec_reg = PPS_LATCH_TSN_NANO_SEC(0); \
+		else if (2 == tsn_no)                         \
+			nano_sec_reg = PPS_LATCH_TSN_NANO_SEC(1); \
+		else if (3 == tsn_no)                         \
+			nano_sec_reg = PPS_LATCH_TSN_NANO_SEC(2); \
+		else if (4 == tsn_no)                         \
+			nano_sec_reg = PPS_LATCH_TSN_NANO_SEC(3); \
+	})
 
 #define GET_PPS_LATCH_TSN_LOW_SEC_REG(tsn_no)          \
-    ({                                                 \
-        if (1 == tsn_no)                               \
-            low_sec_reg = PPS_LATCH_TSN_LOW_SECOND(0); \
-        else if (2 == tsn_no)                          \
-            low_sec_reg = PPS_LATCH_TSN_LOW_SECOND(1); \
-        else if (3 == tsn_no)                          \
-            low_sec_reg = PPS_LATCH_TSN_LOW_SECOND(2); \
-        else if (4 == tsn_no)                          \
-            low_sec_reg = PPS_LATCH_TSN_LOW_SECOND(3); \
-    })
+	({                                                 \
+		if (1 == tsn_no)                               \
+			low_sec_reg = PPS_LATCH_TSN_LOW_SECOND(0); \
+		else if (2 == tsn_no)                          \
+			low_sec_reg = PPS_LATCH_TSN_LOW_SECOND(1); \
+		else if (3 == tsn_no)                          \
+			low_sec_reg = PPS_LATCH_TSN_LOW_SECOND(2); \
+		else if (4 == tsn_no)                          \
+			low_sec_reg = PPS_LATCH_TSN_LOW_SECOND(3); \
+	})
 
 #define GET_PPS_LATCH_TSN_HIGH_SEC_REG(tsn_no)           \
-    ({                                                   \
-        if (1 == tsn_no)                                 \
-            high_sec_reg = PPS_LATCH_TSN_HIGH_SECOND(0); \
-        else if (2 == tsn_no)                            \
-            high_sec_reg = PPS_LATCH_TSN_HIGH_SECOND(1); \
-        else if (3 == tsn_no)                            \
-            high_sec_reg = PPS_LATCH_TSN_HIGH_SECOND(2); \
-        else if (4 == tsn_no)                            \
-            high_sec_reg = PPS_LATCH_TSN_HIGH_SECOND(3); \
-    })
+	({                                                   \
+		if (1 == tsn_no)                                 \
+			high_sec_reg = PPS_LATCH_TSN_HIGH_SECOND(0); \
+		else if (2 == tsn_no)                            \
+			high_sec_reg = PPS_LATCH_TSN_HIGH_SECOND(1); \
+		else if (3 == tsn_no)                            \
+			high_sec_reg = PPS_LATCH_TSN_HIGH_SECOND(2); \
+		else if (4 == tsn_no)                            \
+			high_sec_reg = PPS_LATCH_TSN_HIGH_SECOND(3); \
+	})
 
 #define GET_PPS_LATCH_TSN_FRAC_NANO_SEC_REG(tsn_no)         \
-    ({                                                      \
-        if (1 == tsn_no)                                    \
-            frac_nano_reg = PPS_LATCH_TSN_FRAC_NANO_SEC(0); \
-        else if (2 == tsn_no)                               \
-            frac_nano_reg = PPS_LATCH_TSN_FRAC_NANO_SEC(1); \
-        else if (3 == tsn_no)                               \
-            frac_nano_reg = PPS_LATCH_TSN_FRAC_NANO_SEC(2); \
-        else if (4 == tsn_no)                               \
-            frac_nano_reg = PPS_LATCH_TSN_FRAC_NANO_SEC(3); \
-    })
-
-enum reg_module
-{
-    PTP_TOP,
-    PTP_M,
-    PTP_S0,
-    PTP_S1,
-    PTP_S2,
+	({                                                      \
+		if (1 == tsn_no)                                    \
+			frac_nano_reg = PPS_LATCH_TSN_FRAC_NANO_SEC(0); \
+		else if (2 == tsn_no)                               \
+			frac_nano_reg = PPS_LATCH_TSN_FRAC_NANO_SEC(1); \
+		else if (3 == tsn_no)                               \
+			frac_nano_reg = PPS_LATCH_TSN_FRAC_NANO_SEC(2); \
+		else if (4 == tsn_no)                               \
+			frac_nano_reg = PPS_LATCH_TSN_FRAC_NANO_SEC(3); \
+	})
+
+enum reg_module {
+	PTP_TOP,
+	PTP_M,
+	PTP_S0,
+	PTP_S1,
+	PTP_S2,
 };
 
 static inline uint32_t zxdh_read_reg(uint64_t base_addr, uint32_t offset)
 {
-    return readl((const volatile void *)(base_addr + offset));
+	return readl((const volatile void *)(base_addr + offset));
 }
 
-static inline void zxdh_write_reg(uint64_t base_addr, uint32_t offset, uint32_t val)
+static inline void zxdh_write_reg(uint64_t base_addr, uint32_t offset,
+								  uint32_t val)
 {
-    writel(val, (volatile void *)(base_addr + offset));
+	writel(val, (volatile void *)(base_addr + offset));
 }
 
 static uint64_t zxdh_ptp_get_bar_addr(struct zxdh_ptp_private *adapter)
 {
-    struct zxdh_pf_device *pf_dev = adapter->pdev;
-    return pf_dev->pci_ioremap_addr[0];
+	struct zxdh_pf_device *pf_dev = adapter->pdev;
+	return pf_dev->pci_ioremap_addr[0];
 }
 
-static struct zxdh_ptp_private* zxdh_ptp_get_ptp_private(struct zxdh_en_device *en_dev)
+static struct zxdh_ptp_private *
+zxdh_ptp_get_ptp_private(struct zxdh_en_device *en_dev)
 {
-    struct zxdh_pf_device *pf_dev = dh_core_priv(en_dev->parent->parent);
-    return pf_dev->ptp;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(en_dev->parent->parent);
+	return pf_dev->ptp;
 }
+
 /**
  * zx_ptp_adjfreq - adjust ptp cycle frequency
  * @ptp: the ptp clock structure
  * @ppb: parts per billion adjustment from base
  *
+ * Adjust the frequency of the ptp cycle counter by the
+ * indicated ppb from the base frequency.
  */
 static int zx_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 {
-    unsigned long flags;
-    int neg_adj = 0;
-    uint32_t cur_nano, cur_frac_nano;
-    uint64_t tmp_frac_nano;
-    uint64_t base_addr;
-    uint64_t bar_addr;
-    uint64_t freq_adj;
-    struct zxdh_ptp_private *adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[0]);
-    
-    PTP_LOG_INFO("name: %s, ppb: %d\n", ptp->name, ppb);
-
-    if (ppb == 0)
-        return 0;
-
-    if (ppb < 0)
-    {
-        ppb     = -ppb;
-        neg_adj = 1;
-    }
-    bar_addr = zxdh_ptp_get_bar_addr(adapter);
-
-    base_addr     = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
-    cur_nano      = zxdh_read_reg(base_addr, PTP_CLOCK_CYCLE_INTEGER);
-    cur_frac_nano = zxdh_read_reg(base_addr, PTP_CLOCK_CYCLE_FRACTION);
-
-    tmp_frac_nano = ((unsigned long long)cur_nano << 32) + cur_frac_nano;
-
-    PTP_LOG_INFO("cur_nano: %u, cur_frac_nano: %u, tmp_frac_nano: 0x%llx\n", cur_nano, cur_frac_nano,
-           tmp_frac_nano);
-
-    /* positive adjust */
-    if (0 == neg_adj)
-    {
-        tmp_frac_nano += tmp_frac_nano * ppb / 1000000000;
-    }
-    else /* negative adjust */
-    {
-        freq_adj = tmp_frac_nano * ppb / 1000000000;
-        if(tmp_frac_nano > freq_adj)
-            tmp_frac_nano -= freq_adj;
-    }
-    PTP_LOG_INFO("new tmp_frac_nano: 0x%llx\n", tmp_frac_nano);
-    cur_nano      = (uint32_t)(tmp_frac_nano >> 32);
-    cur_frac_nano = tmp_frac_nano & 0xffffffff;
-
-    PTP_LOG_INFO("cur_nano: %u, cur_frac_nano: %u\n", cur_nano, cur_frac_nano);
-    spin_lock_irqsave(&adapter->tmreg_lock, flags);
-
-    zxdh_write_reg(base_addr, PTP_CLOCK_CYCLE_INTEGER, cur_nano);
-    zxdh_write_reg(base_addr, PTP_CLOCK_CYCLE_FRACTION, cur_frac_nano);
-    zxdh_write_reg(base_addr, CLOCK_CYCLE_UPDATE, 1);
-
-    spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
-
-    return 0;
-}
+	unsigned long flags;
+	int neg_adj = 0;
+	uint32_t cur_nano, cur_frac_nano;
+	uint64_t tmp_frac_nano;
+	uint64_t base_addr;
+	uint64_t bar_addr;
+	struct zxdh_ptp_private *adapter =
+			container_of(ptp, struct zxdh_ptp_private, ptp_caps[0]);
+
+	PTP_LOG_INFO("name: %s, ppb: %d\n", ptp->name, ppb);
+
+	if (ppb == 0)
+		return 0;
 
+	if (ppb < 0) {
+		ppb = -ppb;
+		neg_adj = 1;
+	}
+	bar_addr = zxdh_ptp_get_bar_addr(adapter);
 
+	base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
+	cur_nano = zxdh_read_reg(base_addr, PTP_CLOCK_CYCLE_INTEGER);
+	cur_frac_nano = zxdh_read_reg(base_addr, PTP_CLOCK_CYCLE_FRACTION);
+
+	tmp_frac_nano = ((unsigned long long)cur_nano << 32) + cur_frac_nano;
+
+	PTP_LOG_INFO("cur_nano: %u, cur_frac_nano: %u, tmp_frac_nano: 0x%llx\n",
+				 cur_nano, cur_frac_nano, tmp_frac_nano);
+
+	/* positive adjust */
+	if (neg_adj == 0) {
+		tmp_frac_nano += tmp_frac_nano * ppb / 1000000000;
+	} else {
+		tmp_frac_nano -= tmp_frac_nano * ppb / 1000000000;
+	}
+	PTP_LOG_INFO("new tmp_frac_nano: 0x%llx\n", tmp_frac_nano);
+	cur_nano = (uint32_t)(tmp_frac_nano >> 32);
+	cur_frac_nano = tmp_frac_nano & 0xffffffff;
+
+	PTP_LOG_INFO("cur_nano: %u, cur_frac_nano: %u\n", cur_nano, cur_frac_nano);
+	spin_lock_irqsave(&adapter->tmreg_lock, flags);
+
+	zxdh_write_reg(base_addr, PTP_CLOCK_CYCLE_INTEGER, cur_nano);
+	zxdh_write_reg(base_addr, PTP_CLOCK_CYCLE_FRACTION, cur_frac_nano);
+	zxdh_write_reg(base_addr, CLOCK_CYCLE_UPDATE, 1);
+
+	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
+
+	return 0;
+}
+
+/**
+ * zxdh_ptp_adjtime
+ * @ptp: the ptp clock structure
+ * @delta: offset to adjust the cycle counter by
+ *
+ */
 static int zxdh_ptp_adjtime(struct ptp_clock_info *ptp_clock, s64 delta)
 {
-    unsigned long flags;
-    uint32_t run_mode;
-    uint32_t reg_val;
-    uint64_t adjust;
-    // s32 rem;
-    uint64_t sec;
-    uint32_t nsec;
-
-    uint64_t base_addr;
-    uint64_t bar_addr;
-    struct zxdh_ptp_private *adapter;
-    PTP_LOG_INFO("name: %s, delta: %lld\n", ptp_clock->name, delta);
-
-    adapter = container_of(ptp_clock, struct zxdh_ptp_private, ptp_caps[0]);
-    bar_addr = zxdh_ptp_get_bar_addr(adapter);
-
-    base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
-
-    spin_lock_irqsave(&adapter->tmreg_lock, flags);
-    // timecounter_adjtime(&adapter->tc, delta);
-
-    /* 1588 timer, update mode */
-    if (delta > 0)
-    {
-        run_mode = INCRE_MODE;
-        adjust   = delta;
-    }
-    else
-    {
-        run_mode = DECRE_MODE;
-        adjust   = -delta;
-    }
-
-    /* adjust value */
-    sec = div_u64_rem(adjust, NSEC_PER_SEC, &nsec);
-    PTP_LOG_INFO("sec: %llu, nsec: %u\n", sec, nsec);
-    // nsec = rem;
-    zxdh_write_reg(base_addr, ADJUST_HIGH_TOD_SECOND, (uint32_t)(sec >> 32));
-    zxdh_write_reg(base_addr, ADJUST_LOWER_TOD_SECOND, (uint32_t)(sec & 0xffffffff));
-    zxdh_write_reg(base_addr, ADJUST_TOD_NANO_SECOND, nsec);
-
-    reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION);
-    reg_val &= ~(0x3 << 4);
-    reg_val |= run_mode << 4 | 1 << TIMER_1588_UPT_EN_BIT;
-    zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val);
-
-    /* enable adjust */
-    zxdh_write_reg(base_addr, TIMER_CONTROL, 1 << 1);
-
-    spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
-
-    return 0;
-}
+	unsigned long flags;
+	uint32_t run_mode;
+	uint32_t reg_val;
+	uint64_t adjust;
+	// s32 rem;
+	uint64_t sec;
+	uint32_t nsec;
 
+	uint64_t base_addr;
+	uint64_t bar_addr;
+	struct zxdh_ptp_private *adapter;
+	PTP_LOG_INFO("name: %s, delta: %lld\n", ptp_clock->name, delta);
+
+	adapter = container_of(ptp_clock, struct zxdh_ptp_private, ptp_caps[0]);
+	bar_addr = zxdh_ptp_get_bar_addr(adapter);
+
+	base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
+
+	spin_lock_irqsave(&adapter->tmreg_lock, flags);
+	// timecounter_adjtime(&adapter->tc, delta);
+
+	/* 1588 timer, update mode */
+	if (delta > 0) {
+		run_mode = INCRE_MODE;
+		adjust = delta;
+	} else {
+		run_mode = DECRE_MODE;
+		adjust = -delta;
+	}
+
+	/* adjust value */
+	sec = div_u64_rem(adjust, NSEC_PER_SEC, &nsec);
+	PTP_LOG_INFO("sec: %llu, nsec: %u\n", sec, nsec);
+	// nsec = rem;
+	zxdh_write_reg(base_addr, ADJUST_HIGH_TOD_SECOND, (uint32_t)(sec >> 32));
+	zxdh_write_reg(base_addr, ADJUST_LOWER_TOD_SECOND,
+				   (uint32_t)(sec & 0xffffffff));
+	zxdh_write_reg(base_addr, ADJUST_TOD_NANO_SECOND, nsec);
+
+	reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION);
+	reg_val &= ~(0x3 << 4);
+	reg_val |= run_mode << 4 | 1 << TIMER_1588_UPT_EN_BIT;
+	zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val);
+
+	/* enable adjust */
+	zxdh_write_reg(base_addr, TIMER_CONTROL, 1 << 1);
+
+	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
+
+	return 0;
+}
 
+/**
+ * zxdh_ptp_gettime
+ * @ptp: the ptp clock structure
+ * @ts: timespec structure to hold the current time value
+ *
+ * read the timecounter and return the correct value on ns,
+ * after converting it into a struct timespec.
+ */
 static int zxdh_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
 {
-    uint32_t ns;
-    uint64_t s;
-    uint32_t reg_val;
-    unsigned long flags;
-
-    uint64_t base_addr;
-    struct zxdh_ptp_private *adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[0]);
-    uint64_t bar_addr = zxdh_ptp_get_bar_addr(adapter);
-    PTP_LOG_INFO("name: %s\n", ptp->name);
-
-    base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
-
-    mutex_lock(&adapter->ptp_clk_mutex);
-    spin_lock_irqsave(&adapter->tmreg_lock, flags);
-
-    // normal mode.
-    reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION);
-    reg_val &= ~(0x3 << PPS_RUN_MODE_BIT);
-    reg_val |= NORMAL_MODE << PPS_RUN_MODE_BIT;
-    zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val);
-    zxdh_write_reg(base_addr, TIMER_LACTH_SEL, 1 << LATCH_1588_TIMER);
-    zxdh_write_reg(base_addr, TIMER_LATCH_EN, 1);
-
-    ns = zxdh_read_reg(base_addr, LATCH_TOD_NANO_SECOND);
-    s  = zxdh_read_reg(base_addr, LATCH_LOWER_TOD_SECOND);
-    s |= (uint64_t)zxdh_read_reg(base_addr, LATCH_HIGH_TOD_SECOND) << 32;
-
-    spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
-    mutex_unlock(&adapter->ptp_clk_mutex);
-
-    // *ts = ns_to_timespec64(ns);
-    ts->tv_sec  = s;
-    ts->tv_nsec = ns;
-    PTP_LOG_INFO("kernel get clock time: %lld.%09ld\n", ts->tv_sec, ts->tv_nsec);
-
-    return 0;
+	// uint64_t ns;
+	uint32_t ns;
+	uint64_t s;
+	uint32_t reg_val;
+	unsigned long flags;
+
+	uint64_t base_addr;
+	struct zxdh_ptp_private *adapter =
+			container_of(ptp, struct zxdh_ptp_private, ptp_caps[0]);
+	uint64_t bar_addr = zxdh_ptp_get_bar_addr(adapter);
+	PTP_LOG_INFO("name: %s\n", ptp->name);
+
+	base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
+
+	mutex_lock(&adapter->ptp_clk_mutex);
+	spin_lock_irqsave(&adapter->tmreg_lock, flags);
+
+	// normal mode.
+	reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION);
+	reg_val &= ~(0x3 << PPS_RUN_MODE_BIT);
+	reg_val |= NORMAL_MODE << PPS_RUN_MODE_BIT;
+	zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val);
+	zxdh_write_reg(base_addr, TIMER_LACTH_SEL, 1 << LATCH_1588_TIMER);
+	zxdh_write_reg(base_addr, TIMER_LATCH_EN, 1);
+
+	ns = zxdh_read_reg(base_addr, LATCH_TOD_NANO_SECOND);
+	s = zxdh_read_reg(base_addr, LATCH_LOWER_TOD_SECOND);
+	s |= (uint64_t)zxdh_read_reg(base_addr, LATCH_HIGH_TOD_SECOND) << 32;
+
+	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
+	mutex_unlock(&adapter->ptp_clk_mutex);
+
+	// *ts = ns_to_timespec64(ns);
+	ts->tv_sec = s;
+	ts->tv_nsec = ns;
+	PTP_LOG_INFO("kernel get clock time: %lld.%09ld\n", ts->tv_sec,
+				 ts->tv_nsec);
+
+	return 0;
 }
 
-static int zxdh_ptp_settime(struct ptp_clock_info *ptp, const struct timespec64 *ts)
+/**
+ * zxdh_ptp_settime
+ * @ptp: the ptp clock structure
+ * @ts: the timespec containing the new time for the cycle counter
+ *
+ */
+static int zxdh_ptp_settime(struct ptp_clock_info *ptp,
+							const struct timespec64 *ts)
 {
-    unsigned long flags;
-    uint32_t reg_val;
+	unsigned long flags;
+	uint32_t reg_val;
+
+	uint64_t base_addr;
+	struct zxdh_ptp_private *adapter =
+			container_of(ptp, struct zxdh_ptp_private, ptp_caps[0]);
 
-    uint64_t base_addr;
-    struct zxdh_ptp_private *adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[0]);
-    
-    uint64_t bar_addr = zxdh_ptp_get_bar_addr(adapter);
-    PTP_LOG_INFO("name: %s, sec: %lld, nsec: %ld\n", ptp->name, ts->tv_sec, ts->tv_nsec);
+	uint64_t bar_addr = zxdh_ptp_get_bar_addr(adapter);
+	PTP_LOG_INFO("name: %s, sec: %lld, nsec: %ld\n", ptp->name, ts->tv_sec,
+				 ts->tv_nsec);
 
-    base_addr  = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
+	base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
 
-    mutex_lock(&adapter->ptp_clk_mutex);
+	mutex_lock(&adapter->ptp_clk_mutex);
+	/* Check the ptp clock */
+	// if (!adapter->ptp_clk_on) {
+	// 	mutex_unlock(&adapter->ptp_clk_mutex);
+	// 	return -EINVAL;
+	// }
 
-    spin_lock_irqsave(&adapter->tmreg_lock, flags);
+	spin_lock_irqsave(&adapter->tmreg_lock, flags);
 
-    /* adjust value */
-    zxdh_write_reg(base_addr, ADJUST_HIGH_TOD_SECOND, (uint32_t)(ts->tv_sec >> 32) & 0xffff);
-    zxdh_write_reg(base_addr, ADJUST_LOWER_TOD_SECOND, (uint32_t)(ts->tv_sec & 0xffffffff));
-    zxdh_write_reg(base_addr, ADJUST_TOD_NANO_SECOND, ts->tv_nsec);
+	/* adjust value */
+	zxdh_write_reg(base_addr, ADJUST_HIGH_TOD_SECOND,
+				   (uint32_t)(ts->tv_sec >> 32) & 0xffff);
+	zxdh_write_reg(base_addr, ADJUST_LOWER_TOD_SECOND,
+				   (uint32_t)(ts->tv_sec & 0xffffffff));
+	zxdh_write_reg(base_addr, ADJUST_TOD_NANO_SECOND, ts->tv_nsec);
 
-    /* 1588 timer, update mode */
-    reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION);
-    reg_val &= ~(0x3 << 4);
-    reg_val |= UPDATE_MODE << 4 | 1 << TIMER_1588_UPT_EN_BIT;
-    zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val);
+	/* 1588 timer, update mode */
+	reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION);
+	reg_val &= ~(0x3 << 4);
+	reg_val |= UPDATE_MODE << 4 | 1 << TIMER_1588_UPT_EN_BIT;
+	zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val);
 
-    /* enable adjust */
-    zxdh_write_reg(base_addr, TIMER_CONTROL, 1 << 1);
+	/* enable adjust */
+	zxdh_write_reg(base_addr, TIMER_CONTROL, 1 << 1);
 
-    spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
-    mutex_unlock(&adapter->ptp_clk_mutex);
+	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
+	mutex_unlock(&adapter->ptp_clk_mutex);
 
-    return 0;
+	return 0;
 }
 
-#if 0
-static int zxdh_ptp_enable_pps(struct zxdh_ptp_private *adapter, int on)
+int zxdh_set_capture_timer(struct ptp_clock_info *ptp, unsigned int timer_no)
 {
-    uint32_t reg_val = 0;
-    uint64_t base_addr;
-
-    uint64_t bar_addr = zxdh_ptp_get_bar_addr(adapter);
-
-    base_addr                        = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
-
-    // bit14 enable ptp pps output
-    reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION);
-    reg_val &= ~(1 << 14);
-    reg_val |= on << 14;
-    zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val);
-    return 0;
+	PTP_LOG_INFO("name: %s, timer_no: %u\n", ptp->name, timer_no);
+	return 0;
 }
-#endif
+
 /**
  * zxdh_ptp_enable
  * @ptp: the ptp clock structure
@@ -462,320 +464,280 @@ static int zxdh_ptp_enable_pps(struct zxdh_ptp_private *adapter, int on)
  * @on: whether to enable or disable the feature
  *
  */
-static int zxdh_ptp_enable(struct ptp_clock_info *ptp, struct ptp_clock_request *rq, int on)
+static int zxdh_ptp_enable(struct ptp_clock_info *ptp,
+						   struct ptp_clock_request *rq, int on)
 {
-#if 1
-    PTP_LOG_INFO("name: %s, rq->type: %d\n", ptp->name, rq->type);
-#else
-    struct zxdh_ptp_private *adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[0]);
-    int ret                          = 0;
-    int pin                          = -1;
-
-    switch (rq->type)
-    {
-        case PTP_CLK_REQ_PPS:
-            ret = zxdh_ptp_enable_pps(adapter, on);
-            return ret;
-        case PTP_CLK_REQ_EXTTS:
-            if (on)
-            {
-                // pin = ptp_find_pin(adapter->ptp_clock[0], PTP_PF_EXTTS,
-                // 	   rq->extts.index);
-                // if (pin < 0)
-                //     return -EBUSY;
-                if (rq->extts.index == 1 || rq->extts.index == 2)  // 选择pps0 or pps1做为capture和中断源
-                {
-                    adapter->pps_channel = rq->extts.index;
-                    zxdh_write_reg(adapter, PP1S_EXTERNAL_SEL, rq->extts.index - 1, PTP_TOP);
-                }
-            }
-            return 0;
-
-        case PTP_CLK_REQ_PEROUT:
-            return 0;
-    }
-    return -EOPNOTSUPP;
-#endif
-    return 0;
+	PTP_LOG_INFO("name: %s, rq->type: %d\n", ptp->name, rq->type);
+	return 0;
 }
 
 static int zxdh_tsn_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 {
-    unsigned long flags;
-    int neg_adj = 0;
-    uint32_t cur_nano, cur_frac_nano;
-    uint64_t tmp_frac_nano;
-    int timer_no;
-    uint32_t integer_reg;
-    uint32_t fraction_reg;
-    uint64_t base_addr;
-    uint64_t bar_addr;
-    uint64_t freq_adj;
-    struct zxdh_ptp_private *adapter;
-
-    PTP_LOG_INFO("name: %s, ppb: %d\n", ptp->name, ppb);
-    timer_no = get_tsn_timer_no(ptp->name);
-    PTP_CHECK_RANGE_WITH_RETURN(timer_no, TSN_TIMER_NAME_MIN_NO, TSN_TIMER_NAME_MAX_NO, -1);
-
-    adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[timer_no + 1]);
-
-    bar_addr = zxdh_ptp_get_bar_addr(adapter);
-    base_addr                        = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
-
-    if (ppb == 0)
-        return 0;
-
-    if (ppb < 0)
-    {
-        ppb     = -ppb;
-        neg_adj = 1;
-    }
-
-    integer_reg  = tsn_clock_cycle_integer_reg(timer_no);
-    fraction_reg = tsn_clock_cycle_fraction_reg(timer_no);
-
-    cur_nano      = zxdh_read_reg(base_addr, integer_reg);
-    cur_frac_nano = zxdh_read_reg(base_addr, fraction_reg);
-
-    tmp_frac_nano = ((unsigned long long)cur_nano << 32) + cur_frac_nano;
-
-    PTP_LOG_INFO("cur_nano: %u, cur_frac_nano: %u, tmp_frac_nano: 0x%llx\n", cur_nano, cur_frac_nano,
-           tmp_frac_nano);
-
-    /* positive adjust */
-    if (0 == neg_adj)
-    {
-        tmp_frac_nano += tmp_frac_nano * ppb / 1000000000;
-    }
-    else /* negative adjust */
-    {
-        freq_adj = tmp_frac_nano * ppb / 1000000000;
-        if(tmp_frac_nano > freq_adj)
-            tmp_frac_nano -= freq_adj;
-    }
-
-    PTP_LOG_INFO("new tmp_frac_nano: 0x%llx\n", tmp_frac_nano);
-    cur_nano      = (uint32_t)(tmp_frac_nano >> 32);
-    cur_frac_nano = tmp_frac_nano & 0xffffffff;
-
-    PTP_LOG_INFO("cur_nano: %u, cur_frac_nano: %u\n", cur_nano, cur_frac_nano);
-    spin_lock_irqsave(&adapter->tmreg_lock, flags);
-
-    zxdh_write_reg(base_addr, integer_reg, cur_nano);
-    zxdh_write_reg(base_addr, fraction_reg, cur_frac_nano);
-
-    zxdh_write_reg(base_addr, CLOCK_CYCLE_UPDATE, 1 << (timer_no + 1));
-
-    spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
-
-    return 0;
-}
+	unsigned long flags;
+	int neg_adj = 0;
+	uint32_t cur_nano, cur_frac_nano;
+	uint64_t tmp_frac_nano;
+	unsigned int timer_no;
+	uint32_t integer_reg;
+	uint32_t fraction_reg;
+	uint64_t base_addr;
+	uint64_t bar_addr;
+	struct zxdh_ptp_private *adapter;
+
+	timer_no = get_tsn_timer_no(ptp->name);
+	PTP_LOG_INFO("name: %s, ppb: %d\n", ptp->name, ppb);
+
+	adapter =
+			container_of(ptp, struct zxdh_ptp_private, ptp_caps[timer_no + 1]);
 
+	bar_addr = zxdh_ptp_get_bar_addr(adapter);
+	base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
 
+	if (ppb == 0)
+		return 0;
+
+	if (ppb < 0) {
+		ppb = -ppb;
+		neg_adj = 1;
+	}
+
+	integer_reg = tsn_clock_cycle_integer_reg(timer_no);
+	fraction_reg = tsn_clock_cycle_fraction_reg(timer_no);
+
+	cur_nano = zxdh_read_reg(base_addr, integer_reg);
+	cur_frac_nano = zxdh_read_reg(base_addr, fraction_reg);
+
+	tmp_frac_nano = ((unsigned long long)cur_nano << 32) + cur_frac_nano;
+
+	PTP_LOG_INFO("cur_nano: %u, cur_frac_nano: %u, tmp_frac_nano: 0x%llx\n",
+				 cur_nano, cur_frac_nano, tmp_frac_nano);
+
+	/* positive adjust */
+	if (neg_adj == 0) {
+		tmp_frac_nano += tmp_frac_nano * ppb / 1000000000;
+	} else {
+		tmp_frac_nano -= tmp_frac_nano * ppb / 1000000000;
+	}
+
+	PTP_LOG_INFO("new tmp_frac_nano: 0x%llx\n", tmp_frac_nano);
+	cur_nano = (uint32_t)(tmp_frac_nano >> 32);
+	cur_frac_nano = tmp_frac_nano & 0xffffffff;
+
+	PTP_LOG_INFO("cur_nano: %u, cur_frac_nano: %u\n", cur_nano, cur_frac_nano);
+	spin_lock_irqsave(&adapter->tmreg_lock, flags);
+
+	zxdh_write_reg(base_addr, integer_reg, cur_nano);
+	zxdh_write_reg(base_addr, fraction_reg, cur_frac_nano);
+
+	zxdh_write_reg(base_addr, CLOCK_CYCLE_UPDATE, 1 << (timer_no + 1));
+
+	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
+
+	return 0;
+}
+
+/**
+ * zxdh_tsn_adjtime
+ * @ptp: the ptp clock structure
+ * @delta: offset to adjust the cycle counter
+ */
 static int zxdh_tsn_adjtime(struct ptp_clock_info *ptp, s64 delta)
 {
-    unsigned long flags;
-    uint32_t run_mode;
-    uint32_t reg_val;
-    uint64_t adjust;
-    uint64_t sec;
-    uint32_t nsec;
-    int timer_no;
-    uint32_t nano_sec_reg;
-    uint32_t low_sec_reg;
-    uint32_t high_sec_reg;
-    int run_mode_bit_shift;
-    uint64_t base_addr;
-    uint64_t bar_addr;
-    struct zxdh_ptp_private *adapter;
-
-    PTP_LOG_INFO("name: %s, delta: %lld\n", ptp->name, delta);
-    timer_no = get_tsn_timer_no(ptp->name);
-    PTP_CHECK_RANGE_WITH_RETURN(timer_no, TSN_TIMER_NAME_MIN_NO, TSN_TIMER_NAME_MAX_NO, -1);
-
-    adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[timer_no + 1]);
-    bar_addr = zxdh_ptp_get_bar_addr(adapter);
-    base_addr                        = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
-
-    spin_lock_irqsave(&adapter->tmreg_lock, flags);
-
-    /* 1588 timer, update mode */
-    if (delta > 0)
-    {
-        run_mode = INCRE_MODE;
-        adjust   = delta;
-    }
-    else
-    {
-        run_mode = DECRE_MODE;
-        adjust   = -delta;
-    }
-
-    GET_TSN_ADJUST_NANO_REG(timer_no);
-    GET_TSN_ADJUST_LOW_SEC_REG(timer_no);
-    GET_TSN_ADJUST_HIGH_SEC_REG(timer_no);
-
-    /* adjust value */
-    sec = div_u64_rem(adjust, NSEC_PER_SEC, &nsec);
-
-    PTP_LOG_INFO("sec: %llu, nsec: %u\n", sec, nsec);
-    // nsec = rem;
-    zxdh_write_reg(base_addr, high_sec_reg, (uint32_t)(sec >> 32));
-    zxdh_write_reg(base_addr, low_sec_reg, (uint32_t)(sec & 0xffffffff));
-    zxdh_write_reg(base_addr, nano_sec_reg, nsec);
-
-    run_mode_bit_shift = 4 + timer_no * 2;
-    reg_val            = zxdh_read_reg(base_addr, TSN_TIME_CONFIGURATION);
-    reg_val &= ~(0x3 << run_mode_bit_shift);
-    reg_val |= run_mode << run_mode_bit_shift;
-    zxdh_write_reg(base_addr, TSN_TIME_CONFIGURATION, reg_val);
-    /* enable adjust */
-    zxdh_write_reg(base_addr, TSN_TIMER_CONTROL, 1 << timer_no);
-
-    spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
-
-    return 0;
+	unsigned long flags;
+	uint32_t run_mode;
+	uint32_t reg_val;
+	uint64_t adjust;
+	uint64_t sec;
+	uint32_t nsec;
+	unsigned int timer_no;
+	uint32_t nano_sec_reg;
+	uint32_t low_sec_reg;
+	uint32_t high_sec_reg;
+	int run_mode_bit_shift;
+	uint64_t base_addr;
+	uint64_t bar_addr;
+	struct zxdh_ptp_private *adapter;
+
+	PTP_LOG_INFO("name: %s, delta: %lld\n", ptp->name, delta);
+	timer_no = get_tsn_timer_no(ptp->name);
+
+	adapter =
+			container_of(ptp, struct zxdh_ptp_private, ptp_caps[timer_no + 1]);
+	bar_addr = zxdh_ptp_get_bar_addr(adapter);
+	base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
+
+	spin_lock_irqsave(&adapter->tmreg_lock, flags);
+
+	/* 1588 timer, update mode */
+	if (delta > 0) {
+		run_mode = INCRE_MODE;
+		adjust = delta;
+	} else {
+		run_mode = DECRE_MODE;
+		adjust = -delta;
+	}
+
+	GET_TSN_ADJUST_NANO_REG(timer_no);
+	GET_TSN_ADJUST_LOW_SEC_REG(timer_no);
+	GET_TSN_ADJUST_HIGH_SEC_REG(timer_no);
+
+	/* adjust value */
+	sec = div_u64_rem(adjust, NSEC_PER_SEC, &nsec);
+
+	PTP_LOG_INFO("sec: %llu, nsec: %u\n", sec, nsec);
+	// nsec = rem;
+	zxdh_write_reg(base_addr, high_sec_reg, (uint32_t)(sec >> 32));
+	zxdh_write_reg(base_addr, low_sec_reg, (uint32_t)(sec & 0xffffffff));
+	zxdh_write_reg(base_addr, nano_sec_reg, nsec);
+
+	run_mode_bit_shift = 4 + timer_no * 2;
+	reg_val = zxdh_read_reg(base_addr, TSN_TIME_CONFIGURATION);
+	reg_val &= ~(0x3 << run_mode_bit_shift);
+	reg_val |= run_mode << run_mode_bit_shift;
+	zxdh_write_reg(base_addr, TSN_TIME_CONFIGURATION, reg_val);
+	/* enable adjust */
+	zxdh_write_reg(base_addr, TSN_TIMER_CONTROL, 1 << timer_no);
+
+	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
+
+	return 0;
 }
 
-
+/**
+ * zxdh_tsn_gettime
+ * @ptp: the ptp clock structure
+ * @ts: timespec structure to hold the current time value
+ *
+ * read the timecounter and return the correct value on ns,
+ * after converting it into a struct timespec.
+ */
 static int zxdh_tsn_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
 {
-    uint32_t ns;
-    uint64_t s;
-    unsigned long flags;
-    int timer_no;
-    uint32_t reg_val;
-    int run_mode_bit_shift;
-    uint32_t nano_sec_reg;
-    uint32_t low_sec_reg;
-    uint32_t high_sec_reg;
-    uint64_t base_addr;
-    uint64_t bar_addr;
-    struct zxdh_ptp_private *adapter;
-
-    PTP_LOG_INFO("name: %s\n", ptp->name);
-    timer_no = get_tsn_timer_no(ptp->name);
-    PTP_CHECK_RANGE_WITH_RETURN(timer_no, TSN_TIMER_NAME_MIN_NO, TSN_TIMER_NAME_MAX_NO, -1);
-
-    adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[timer_no + 1]);
-    bar_addr = zxdh_ptp_get_bar_addr(adapter);
-    base_addr                        = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
-
-    mutex_lock(&adapter->ptp_clk_mutex);
-
-    spin_lock_irqsave(&adapter->tmreg_lock, flags);
-
-    // bit11~bit4, configure normal mode, should make sure bit15~bit12 enable
-    // first.
-    run_mode_bit_shift = 4 + timer_no * 2;
-    reg_val            = zxdh_read_reg(base_addr, TSN_TIME_CONFIGURATION);
-    reg_val &= ~(0x3 << run_mode_bit_shift);
-    reg_val |= NORMAL_MODE << run_mode_bit_shift;
-    zxdh_write_reg(base_addr, TSN_TIME_CONFIGURATION, reg_val);
-
-    // config latch one tsn timer
-    reg_val = 0;
-    reg_val = 1 << (timer_no + 2);
-    zxdh_write_reg(base_addr, TIMER_LACTH_SEL, reg_val);
-
-    // enable latch
-    zxdh_write_reg(base_addr, TIMER_LATCH_EN, 1);
-
-    GET_TSN_LATCH_NANO_REG(timer_no);
-    GET_TSN_LATCH_LOW_SEC_REG(timer_no);
-    GET_TSN_LATCH_HIGH_SEC_REG(timer_no);
-
-    ns = zxdh_read_reg(base_addr, nano_sec_reg);
-    s  = zxdh_read_reg(base_addr, low_sec_reg);
-    s |= (uint64_t)zxdh_read_reg(base_addr, high_sec_reg) << 32;
-
-    spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
-    mutex_unlock(&adapter->ptp_clk_mutex);
-
-    // *ts = ns_to_timespec64(ns);
-    ts->tv_sec  = s;
-    ts->tv_nsec = ns;
-    PTP_LOG_INFO("kernel get %s clock time: %lld.%09ld\n", ptp->name, ts->tv_sec, ts->tv_nsec);
-
-    return 0;
+	uint32_t ns;
+	uint64_t s;
+	unsigned long flags;
+	unsigned int timer_no;
+	uint32_t reg_val;
+	int run_mode_bit_shift;
+	uint32_t nano_sec_reg;
+	uint32_t low_sec_reg;
+	uint32_t high_sec_reg;
+	uint64_t base_addr;
+	uint64_t bar_addr;
+	struct zxdh_ptp_private *adapter;
+
+	PTP_LOG_INFO("name: %s\n", ptp->name);
+	timer_no = get_tsn_timer_no(ptp->name);
+
+	adapter =
+			container_of(ptp, struct zxdh_ptp_private, ptp_caps[timer_no + 1]);
+	bar_addr = zxdh_ptp_get_bar_addr(adapter);
+	base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
+
+	mutex_lock(&adapter->ptp_clk_mutex);
+	/* Check the ptp clock */
+	//if (!adapter->ptp_clk_on) { // 使能了clk_prepare_enable(fep->clk_ptp)
+	// 	mutex_unlock(&adapter->ptp_clk_mutex);
+	// 	return -EINVAL;
+	// }
+	spin_lock_irqsave(&adapter->tmreg_lock, flags);
+
+	// bit11~bit4, configure normal mode, should make sure bit15~bit12 enable
+	// first.
+	run_mode_bit_shift = 4 + timer_no * 2;
+	reg_val = zxdh_read_reg(base_addr, TSN_TIME_CONFIGURATION);
+	reg_val &= ~(0x3 << run_mode_bit_shift);
+	reg_val |= NORMAL_MODE << run_mode_bit_shift;
+	zxdh_write_reg(base_addr, TSN_TIME_CONFIGURATION, reg_val);
+
+	// config latch one tsn timer
+	reg_val = 0;
+	reg_val = 1 << (timer_no + 2);
+	zxdh_write_reg(base_addr, TIMER_LACTH_SEL, reg_val);
+
+	// enable latch
+	zxdh_write_reg(base_addr, TIMER_LATCH_EN, 1);
+
+	GET_TSN_LATCH_NANO_REG(timer_no);
+	GET_TSN_LATCH_LOW_SEC_REG(timer_no);
+	GET_TSN_LATCH_HIGH_SEC_REG(timer_no);
+
+	ns = zxdh_read_reg(base_addr, nano_sec_reg);
+	s = zxdh_read_reg(base_addr, low_sec_reg);
+	s |= (uint64_t)zxdh_read_reg(base_addr, high_sec_reg) << 32;
+
+	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
+	mutex_unlock(&adapter->ptp_clk_mutex);
+
+	// *ts = ns_to_timespec64(ns);
+	ts->tv_sec = s;
+	ts->tv_nsec = ns;
+	PTP_LOG_INFO("kernel get %s clock time: %lld.%09ld\n", ptp->name,
+				 ts->tv_sec, ts->tv_nsec);
+
+	return 0;
 }
 
 /**
  * zxdh_tsn_settime
- * @ptp: the ptp  clock struct
- * @ts: the timespec  containing the new time
+ * @ptp: the ptp clock structure
+ * @ts: the timespec containing the new time for the cycle counter
  */
-static int zxdh_tsn_settime(struct ptp_clock_info *ptp, const struct timespec64 *ts)
+static int zxdh_tsn_settime(struct ptp_clock_info *ptp,
+							const struct timespec64 *ts)
 {
-    unsigned long flags;
-    uint32_t reg_val;
-    int timer_no;
-    int run_mode_bit_shift;
-    uint32_t nano_sec_reg;
-    uint32_t low_sec_reg;
-    uint32_t high_sec_reg;
-    uint64_t base_addr;
-    uint64_t bar_addr;
-    struct zxdh_ptp_private *adapter;
-
-    PTP_LOG_INFO("name: %s, sec: %lld, nsec: %ld\n", ptp->name, ts->tv_sec, ts->tv_nsec);
-    timer_no = get_tsn_timer_no(ptp->name);
-    PTP_CHECK_RANGE_WITH_RETURN(timer_no, TSN_TIMER_NAME_MIN_NO, TSN_TIMER_NAME_MAX_NO, -1);
-
-    adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[timer_no + 1]);
-    bar_addr = zxdh_ptp_get_bar_addr(adapter);
-    base_addr                        = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
-
-    mutex_lock(&adapter->ptp_clk_mutex);
-
-    spin_lock_irqsave(&adapter->tmreg_lock, flags);
-
-    GET_TSN_ADJUST_NANO_REG(timer_no);
-    GET_TSN_ADJUST_LOW_SEC_REG(timer_no);
-    GET_TSN_ADJUST_HIGH_SEC_REG(timer_no);
-
-    /* adjust value */
-    zxdh_write_reg(base_addr, high_sec_reg, (uint32_t)(ts->tv_sec >> 32));
-    zxdh_write_reg(base_addr, low_sec_reg, (uint32_t)(ts->tv_sec & 0xffffffff));
-    zxdh_write_reg(base_addr, nano_sec_reg, ts->tv_nsec);
-
-    run_mode_bit_shift = 4 + timer_no * 2;
-    reg_val            = zxdh_read_reg(base_addr, TSN_TIME_CONFIGURATION);
-    reg_val &= ~(0x3 << run_mode_bit_shift);
-    reg_val |= UPDATE_MODE << run_mode_bit_shift;
-    zxdh_write_reg(base_addr, TSN_TIME_CONFIGURATION, reg_val);
-    /* enable adjust */
-    zxdh_write_reg(base_addr, TSN_TIMER_CONTROL, 1 << timer_no);
-
-    spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
-    mutex_unlock(&adapter->ptp_clk_mutex);
-
-    return 0;
+	unsigned long flags;
+	uint32_t reg_val;
+	unsigned int timer_no;
+	int run_mode_bit_shift;
+	uint32_t nano_sec_reg;
+	uint32_t low_sec_reg;
+	uint32_t high_sec_reg;
+	uint64_t base_addr;
+	uint64_t bar_addr;
+	struct zxdh_ptp_private *adapter;
+
+	timer_no = get_tsn_timer_no(ptp->name);
+	PTP_LOG_INFO("name: %s, sec: %lld, nsec: %ld\n", ptp->name, ts->tv_sec,
+				 ts->tv_nsec);
+
+	adapter =
+			container_of(ptp, struct zxdh_ptp_private, ptp_caps[timer_no + 1]);
+	bar_addr = zxdh_ptp_get_bar_addr(adapter);
+	base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
+
+	mutex_lock(&adapter->ptp_clk_mutex);
+	/* Check the ptp clock */
+	// if (!adapter->ptp_clk_on) {
+	// 	mutex_unlock(&adapter->ptp_clk_mutex);
+	// 	return -EINVAL;
+	// }
+
+	spin_lock_irqsave(&adapter->tmreg_lock, flags);
+
+	GET_TSN_ADJUST_NANO_REG(timer_no);
+	GET_TSN_ADJUST_LOW_SEC_REG(timer_no);
+	GET_TSN_ADJUST_HIGH_SEC_REG(timer_no);
+
+	/* adjust value */
+	zxdh_write_reg(base_addr, high_sec_reg, (uint32_t)(ts->tv_sec >> 32));
+	zxdh_write_reg(base_addr, low_sec_reg, (uint32_t)(ts->tv_sec & 0xffffffff));
+	zxdh_write_reg(base_addr, nano_sec_reg, ts->tv_nsec);
+
+	run_mode_bit_shift = 4 + timer_no * 2;
+	reg_val = zxdh_read_reg(base_addr, TSN_TIME_CONFIGURATION);
+	reg_val &= ~(0x3 << run_mode_bit_shift);
+	reg_val |= UPDATE_MODE << run_mode_bit_shift;
+	zxdh_write_reg(base_addr, TSN_TIME_CONFIGURATION, reg_val);
+	/* enable adjust */
+	zxdh_write_reg(base_addr, TSN_TIMER_CONTROL, 1 << timer_no);
+
+	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
+	mutex_unlock(&adapter->ptp_clk_mutex);
+
+	return 0;
 }
-#if 0
-static int zxdh_tsn_enable_pps(struct zxdh_pf_device *pf_dev, int tsn_timer, int on)
-{
-    uint32_t reg_val = 0;
 
-    uint64_t base_addr;
-    
-    uint64_t bar_addr = zxdh_ptp_get_bar_addr(adapter);
-
-    base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
-
-    // enable or disable tsn pps
-    reg_val = zxdh_read_reg(base_addr, TSN_TIME_CONFIGURATION);
-    reg_val &= ~(1 << (16 + tsn_timer));
-    reg_val |= on << (16 + tsn_timer);
-    zxdh_write_reg(base_addr, TSN_TIME_CONFIGURATION, reg_val);
-
-    // select tsn pps output from test_1pps
-    // reg_val = 0x4 + tsn_timer;
-    // zxdh_write_reg(base_addr, TEST_PP1S_SEL, reg_val, PTP_TOP); //
-    // 这里先不关联配置test_pps输出，单独用ioctl配置test_pps输出
-    return 0;
-}
-#endif
 /**
  * zxdh_tsn_enable
  * @ptp: the ptp clock structure
@@ -783,695 +745,655 @@ static int zxdh_tsn_enable_pps(struct zxdh_pf_device *pf_dev, int tsn_timer, int
  * @on: whether to enable or disable the feature
  *
  */
-static int zxdh_tsn_enable(struct ptp_clock_info *ptp, struct ptp_clock_request *rq, int on)
+static int zxdh_tsn_enable(struct ptp_clock_info *ptp,
+						   struct ptp_clock_request *rq, int on)
 {
-#if 1
-    PTP_LOG_INFO("name: %s, tsn_no: %d, rq->type: %d\n", ptp->name, get_tsn_timer_no(ptp->name),
-           rq->type);
-#else
-    int timer_no;
-    timer_no = get_tsn_timer_no(ptp->name);
-    PTP_CHECK_RANGE_WITH_RETURN(timer_no, TSN_TIMER_NAME_MIN_NO, TSN_TIMER_NAME_MAX_NO, -1);
-
-    struct zxdh_ptp_private *adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[timer_no + 1]);
-    struct zxdh_pf_device *pf_dev    = container_of(adapter, struct zxdh_pf_device, ptp);
-
-    int ret = 0;
-    int pin = -1;
-
-    switch (rq->type)
-    {
-        case PTP_CLK_REQ_PPS:
-            ret = zxdh_tsn_enable_pps(pf_dev, timer_no, on);
-            return ret;
-        case PTP_CLK_REQ_EXTTS:
-            if (on)
-            {
-                // pin = ptp_find_pin(adapter->ptp_clock[timer_no+1], PTP_PF_EXTTS,
-                // 	   rq->extts.index);
-                // if (pin < 0)
-                //     return -EBUSY;
-                if (rq->extts.index == 1 || rq->extts.index == 2)  // 选择pps0 or pps1做为capture和中断源
-                {
-                    adapter->pps_channel = rq->extts.index;
-                    zxdh_write_reg(adapter, PP1S_EXTERNAL_SEL, rq->extts.index - 1, PTP_TOP);
-                }
-            }
-            return 0;
-
-        case PTP_CLK_REQ_PEROUT:
-            return 0;
-    }
-
-    return -EOPNOTSUPP;
-#endif
-    return 0;
+	PTP_LOG_INFO("name: %s, tsn_no: %u, rq->type: %d\n", ptp->name,
+				 get_tsn_timer_no(ptp->name), rq->type);
+	return 0;
+}
+
+int zxdh_set_tsn_capture_timer(struct ptp_clock_info *ptp,
+							   unsigned int timer_no)
+{
+	unsigned int timer;
+	struct zxdh_ptp_private *adapter;
+	PTP_LOG_INFO("name: %s, timer_no: %u\n", ptp->name, timer_no);
+	timer = get_tsn_timer_no(ptp->name);
+	adapter = container_of(ptp, struct zxdh_ptp_private, ptp_caps[timer + 1]);
+
+	adapter->interrupt_capture_timer = timer_no;
+	return 0;
 }
 
-/* This function handle the pps interrupt event. */
+/* This function checks the pps event and reloads the timer compare counter. */
 irqreturn_t msix_extern_pps_irq_from_risc_handler(struct zxdh_pf_device *dev)
 {
-    uint32_t high_sec, low_sec, nsec;
-    struct ptp_clock_event event;
-    int i;
-    struct zxdh_pf_device *zxdev = dev;
-    struct zxdh_ptp_private *adapter;
-    uint64_t bar_addr = 0x0;
-    uint64_t base_addr = 0x0;
-
-    __u32 pps_event;
-    __u32 clear_event;
-    __u32 pps_mask;
-
-    uint32_t nano_sec_reg;
-    uint32_t low_sec_reg;
-    uint32_t high_sec_reg;
-    // PTP_LOG_INFO("irq: %d\n", irq);
-
-    adapter = zxdev->ptp;
-    bar_addr = zxdh_ptp_get_bar_addr(adapter);
-    base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
-    pps_event = zxdh_read_reg(base_addr, INTERRUPT_EVENT); // 0x10
-    pps_mask = zxdh_read_reg(base_addr, INTERRUPT_MASK);
-    PTP_LOG_INFO("bar_addr: 0x%llx, pps_event: 0x%x,pps_mask: 0x%x, capture_timer: %d\n",bar_addr, pps_event, pps_mask, zxdev->ptp->interrupt_capture_timer);
-
-    // disable int
-    for(i = 0; i < PTPM_INTERRUPT_BIT_NUM; i++)
-    {
-        if(pps_event & (1 << i))
-            zxdh_write_reg(base_addr, INTERRUPT_MASK, pps_mask & (~(1 << i)));
-    }
-
-    // 清中断event
-	clear_event = pps_mask & pps_event;   // 0x10
-    zxdh_write_reg(base_addr, INTERRUPT_EVENT, clear_event);
-
-    if(zxdev->ptp->interrupt_capture_timer > INTERRUPT_CAP_TIMER_MAX_NO)
-    {
-        PTP_LOG_INFO("capture_timer: %u out of range!\n", zxdev->ptp->interrupt_capture_timer);
-        return -1;
-    }
-    // 用status不如用event准
-    if (pps_event & (1 << EXTERNAL_PPS_BIT))  // 外部PPS信号产生的中断，Capture模式抓到的TOD
-    {
-        // 1588 timer
-        if (zxdev->ptp->interrupt_capture_timer == 0)
-        {
-            nsec     = zxdh_read_reg(base_addr, PPS_LATCH_TOD_NANO_SECOND);
-            low_sec  = zxdh_read_reg(base_addr, PPS_LATCH_LOWER_TOD_SECOND);
-            high_sec = zxdh_read_reg(base_addr, PPS_LATCH_HIGH_TOD_SECOND);
-        }
-        else  // tsn timer
-        {
-            GET_PPS_LATCH_TSN_HIGH_SEC_REG(zxdev->ptp->interrupt_capture_timer);
-            GET_PPS_LATCH_TSN_LOW_SEC_REG(zxdev->ptp->interrupt_capture_timer);
-            GET_PPS_LATCH_TSN_NANO_REG(zxdev->ptp->interrupt_capture_timer);
-            nsec     = zxdh_read_reg(base_addr, nano_sec_reg);
-            low_sec  = zxdh_read_reg(base_addr, low_sec_reg);
-            high_sec = zxdh_read_reg(base_addr, high_sec_reg);
-        }
-    }
-    else if (pps_event & (1 << TRIGGER_IN_BIT))  // trigger in信号捕捉的TOD
-    {
-        nsec     = zxdh_read_reg(base_addr, TRIGGER_IN_TOD_NANO_SECOND);
-        low_sec  = zxdh_read_reg(base_addr, TRIGGER_IN_LOWER_TOD_SECOND);
-        high_sec = zxdh_read_reg(base_addr, TRIGGER_IN_HIGH_TOD_SECOND);
-    }
-    else
-    {
-        PTP_LOG_INFO("unknown pps irq\n");
-        nsec     = 0;
-        low_sec  = 0;
-        high_sec = 0;
-    }
-
-    event.type      = PTP_CLOCK_EXTTS;
-    event.index     = 0;
-    event.timestamp = (((uint64_t)high_sec << 32) | low_sec) * 1000000000ULL + nsec;
-    PTP_LOG_INFO("nsec: %u, low_sec: %u, high_sec: %u\n", nsec,  low_sec, high_sec);
-    PTP_LOG_INFO("capture_timer: %u, timestamp: %u.%09u\n", zxdev->ptp->interrupt_capture_timer, low_sec,
-           nsec);
-    ptp_clock_event(zxdev->ptp->ptp_clock[zxdev->ptp->interrupt_capture_timer], &event);
-
-    // enable int
-    zxdh_write_reg(base_addr, INTERRUPT_MASK, pps_mask);
-
-    return IRQ_HANDLED;
+	// unsigned long flags;
+	uint32_t high_sec, low_sec, nsec;
+	struct ptp_clock_event event;
+	int i;
+	struct zxdh_pf_device *zxdev = dev;
+	struct zxdh_ptp_private *adapter;
+	uint64_t bar_addr = 0x0;
+	uint64_t base_addr = 0x0;
+
+	__u32 pps_event;
+	__u32 clear_event;
+	__u32 pps_mask;
+
+	uint32_t nano_sec_reg;
+	uint32_t low_sec_reg;
+	uint32_t high_sec_reg;
+	// PTP_LOG_INFO("irq: %d\n", irq);
+
+	adapter = zxdev->ptp;
+	bar_addr = zxdh_ptp_get_bar_addr(adapter);
+	base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
+	pps_event = zxdh_read_reg(base_addr, INTERRUPT_EVENT); // 0x10
+	pps_mask = zxdh_read_reg(base_addr, INTERRUPT_MASK);
+	PTP_LOG_INFO(
+			"bar_addr: 0x%llx, pps_event: 0x%x,pps_mask: 0x%x, capture_timer: %d\n",
+			bar_addr, pps_event, pps_mask, zxdev->ptp->interrupt_capture_timer);
+
+	// disable int
+	for (i = 0; i < PTPM_INTERRUPT_BIT_NUM; i++) {
+		if (pps_event & (1 << i))
+			zxdh_write_reg(base_addr, INTERRUPT_MASK, pps_mask & (~(1 << i)));
+	}
+
+	// 清中断event
+	clear_event = pps_mask & pps_event; // 0x10
+	zxdh_write_reg(base_addr, INTERRUPT_EVENT, clear_event);
+
+	// adapter->interrupt_capture_timer = 0;  // for debug
+	// 用status不如用event准
+	if (pps_event & (1 << EXTERNAL_PPS_BIT)) {// 外部PPS信号产生的中断，Capture模式抓到的TOD
+		// 1588 timer
+		if (zxdev->ptp->interrupt_capture_timer == 0) {
+			nsec = zxdh_read_reg(base_addr, PPS_LATCH_TOD_NANO_SECOND);
+			low_sec = zxdh_read_reg(base_addr, PPS_LATCH_LOWER_TOD_SECOND);
+			high_sec = zxdh_read_reg(base_addr, PPS_LATCH_HIGH_TOD_SECOND);
+		} else {
+			GET_PPS_LATCH_TSN_HIGH_SEC_REG(zxdev->ptp->interrupt_capture_timer);
+			GET_PPS_LATCH_TSN_LOW_SEC_REG(zxdev->ptp->interrupt_capture_timer);
+			GET_PPS_LATCH_TSN_NANO_REG(zxdev->ptp->interrupt_capture_timer);
+			nsec = zxdh_read_reg(base_addr, nano_sec_reg);
+			low_sec = zxdh_read_reg(base_addr, low_sec_reg);
+			high_sec = zxdh_read_reg(base_addr, high_sec_reg);
+		}
+	} else if (pps_event & (1 << TRIGGER_IN_BIT)) {
+		nsec = zxdh_read_reg(base_addr, TRIGGER_IN_TOD_NANO_SECOND);
+		low_sec = zxdh_read_reg(base_addr, TRIGGER_IN_LOWER_TOD_SECOND);
+		high_sec = zxdh_read_reg(base_addr, TRIGGER_IN_HIGH_TOD_SECOND);
+	}
+
+	event.type = PTP_CLOCK_EXTTS;
+	event.index = 0;
+	event.timestamp =
+			(((uint64_t)high_sec << 32) | low_sec) * 1000000000ULL + nsec;
+	PTP_LOG_INFO("nsec: %u, low_sec: %u, high_sec: %u\n", nsec, low_sec,
+				 high_sec);
+	PTP_LOG_INFO("capture_timer: %u, timestamp: %u.%09u\n",
+				 zxdev->ptp->interrupt_capture_timer, low_sec, nsec);
+	ptp_clock_event(zxdev->ptp->ptp_clock[zxdev->ptp->interrupt_capture_timer],
+					&event);
+
+	// enable int
+	zxdh_write_reg(base_addr, INTERRUPT_MASK, pps_mask);
+
+	return IRQ_HANDLED;
 }
 EXPORT_SYMBOL(msix_extern_pps_irq_from_risc_handler);
 
 irqreturn_t msix_local_pps_irq_from_risc_handler(struct zxdh_pf_device *dev)
 {
-    struct ptp_clock_event event;
-    __u32 reg_int;
-    struct zxdh_pf_device *zxdev = dev;
-    struct zxdh_ptp_private *adapter;
-    uint64_t bar_addr = 0x0;
-    uint64_t base_addr = 0x0;
-
-    adapter = zxdev->ptp;
-    bar_addr = zxdh_ptp_get_bar_addr(adapter);
-    base_addr = bar_addr + PTP_HOST_BAR_OFFSET;
-    // PTP_LOG_INFO("irq: %d\n", irq);
-    event.type = PTP_CLOCK_PPS;
-
-    /* adapter->ptp_clock[0]中创建pps, 用pps对应local_pps的中断 */
-    if (!zxdev->ptp->ptp_clock[0])
-        return IRQ_HANDLED;
-
-    ptp_clock_event(zxdev->ptp->ptp_clock[0], &event);
-
-    base_addr = bar_addr + PTP_HOST_BAR_OFFSET;
-    reg_int = zxdh_read_reg(base_addr, LOCAL_PPS_INTERRUPT); // 0x10
-    PTP_LOG_INFO("bar_addr: 0x%llx, reg_int: 0x%x\n",bar_addr, reg_int);
+	struct ptp_clock_event event;
+	__u32 reg_int;
+	struct zxdh_pf_device *zxdev = dev;
+	struct zxdh_ptp_private *adapter;
+	uint64_t bar_addr = 0x0;
+	uint64_t base_addr = 0x0;
+
+	adapter = zxdev->ptp;
+	bar_addr = zxdh_ptp_get_bar_addr(adapter);
+	base_addr = bar_addr + PTP_HOST_BAR_OFFSET;
+	// PTP_LOG_INFO("irq: %d\n", irq);
+	event.type = PTP_CLOCK_PPS;
+
+	/* adapter->ptp_clock[0]中创建pps, 用pps对应local_pps的中断 */
+	if (!zxdev->ptp->ptp_clock[0])
+		return IRQ_HANDLED;
+
+	ptp_clock_event(zxdev->ptp->ptp_clock[0], &event);
+
+	base_addr = bar_addr + PTP_HOST_BAR_OFFSET;
+	reg_int = zxdh_read_reg(base_addr, LOCAL_PPS_INTERRUPT); // 0x10
+	PTP_LOG_INFO("bar_addr: 0x%llx, reg_int: 0x%x\n", bar_addr, reg_int);
 	reg_int |= 1 << 1;
 	zxdh_write_reg(base_addr, LOCAL_PPS_INTERRUPT, reg_int);
 
-#if 0  // only debug for local pps 
-        uint64_t ns;
-		uint32_t s;
-		static uint64_t last_ns;
-		static uint32_t last_s;
+	return IRQ_HANDLED;
+}
+EXPORT_SYMBOL(msix_local_pps_irq_from_risc_handler);
 
-		reg_val = zxdh_read_reg(adapter, PTP_CONFIGURATION, PTP_M);
-		reg_val &= ~(0x3 << 4);
-		reg_val |= NORMAL_MODE << 4;
-		zxdh_write_reg(adapter, PTP_CONFIGURATION, reg_val, PTP_M);
+// for net_device driver get timestamp, param ptp get from get_tsn_clock
+// function. hw timestamp only use 32 bit.
+int get_pkt_timestamp(int32_t clock_no, struct zxdh_en_device *en_dev,
+					  struct time_stamps *ts, u32 *hwts)
+{
+	u32 nano_sec_reg;
+	u32 low_sec_reg;
+	u32 high_sec_reg;
+	int timer_no;
+	int run_mode_bit_shift;
+	u32 reg_val;
+	struct time_stamps temp_ts;
+	unsigned long flags;
+	uint64_t base_addr;
+	uint64_t bar_addr;
+	struct zxdh_ptp_private *adapter;
+	struct ptp_clock_info *ptp;
+	int phcidx;
+
+	if (en_dev == NULL || ts == NULL || hwts == NULL)
+		return -1;
+
+	adapter = zxdh_ptp_get_ptp_private(en_dev);
+	for (phcidx = 0; phcidx < ZX_CLOCK_TIMER_NUM; phcidx++) {
+		if (clock_no == ptp_clock_index(adapter->ptp_clock[phcidx])) {
+			ptp = &adapter->ptp_caps[phcidx];
+			break;
+		}
+	}
+	if (phcidx == ZX_CLOCK_TIMER_NUM) {
+		PTP_LOG_ERR("get phcindex fail\n");
+		return -1;
+	}
+	bar_addr = zxdh_ptp_get_bar_addr(adapter);
+	base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
+
+	PTP_LOG_INFO("ptp->name: %s, bar_addr: 0x%llx\n", ptp->name, bar_addr);
+	// first 80bit and second 80bit: both are 1588 timestamp
+	if (strcmp(ptp->name, "ptp0") == 0) {
+		PTP_LOG_INFO("ptp0\n");
+		spin_lock_irqsave(&adapter->tmreg_lock, flags);
+
+		reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION);
+		reg_val &= ~(0x3 << PPS_RUN_MODE_BIT);
+		reg_val |= NORMAL_MODE << PPS_RUN_MODE_BIT;
+		zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val);
+
+		// config latch 1588 timer and hw timer
+		zxdh_write_reg(base_addr, TIMER_LACTH_SEL,
+					   1 << LATCH_1588_TIMER | 1 << LATCH_HW_TIMER);
 
-		// config latch 1588 timer
-		zxdh_write_reg(adapter, TIMER_LACTH_SEL, 1 << LATCH_1588_TIMER, PTP_M);
+		// enable latch
+		zxdh_write_reg(base_addr, TIMER_LATCH_EN, 1);
+
+		temp_ts.ns = zxdh_read_reg(base_addr, LATCH_TOD_NANO_SECOND);
+		temp_ts.s = zxdh_read_reg(base_addr, LATCH_LOWER_TOD_SECOND);
+		temp_ts.s |= (u64)zxdh_read_reg(base_addr, LATCH_HIGH_TOD_SECOND) << 32;
+
+		ts->ns = temp_ts.ns;
+		ts->s = temp_ts.s;
+
+		ts++;
+		ts->ns = temp_ts.ns;
+		ts->s = temp_ts.s;
+
+		*hwts = zxdh_read_reg(base_addr, LATCH_HARDWARE_TIME_LOW);
+
+		spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
+		// PTP_LOG_INFO("ts[]: 0x%x.%x, hwts: 0x%x\n", ts->s, ts->ns, *hwts);
+	} else {// first 80bit is 1588 timestamp, second 80bit is one tsn timestamp
+		timer_no = get_tsn_timer_no(ptp->name);
+		PTP_LOG_INFO("tsn: %d\n", timer_no);
+
+		spin_lock_irqsave(&adapter->tmreg_lock, flags);
+		reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION);
+		reg_val &= ~(0x3 << PPS_RUN_MODE_BIT);
+		reg_val |= NORMAL_MODE << PPS_RUN_MODE_BIT;
+		zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val);
+
+		// bit11~bit4, configure normal mode, should make sure bit15~bit12 enable
+		// first.
+		run_mode_bit_shift = 4 + timer_no * 2;
+		reg_val = zxdh_read_reg(base_addr, TSN_TIME_CONFIGURATION);
+		reg_val &= ~(0x3 << run_mode_bit_shift);
+		reg_val |= NORMAL_MODE << run_mode_bit_shift;
+		zxdh_write_reg(base_addr, TSN_TIME_CONFIGURATION, reg_val);
+
+		// config latch 1588 and one tsn timer and hw timer
+		zxdh_write_reg(base_addr, TIMER_LACTH_SEL,
+					   1 << LATCH_1588_TIMER | 1 << LATCH_HW_TIMER |
+							   1 << (timer_no + 2));
 
 		// enable latch
-		zxdh_write_reg(adapter, TIMER_LATCH_EN, 1, PTP_M);
+		zxdh_write_reg(base_addr, TIMER_LATCH_EN, 1);
 
+		// read 1588 timer
+		ts->ns = zxdh_read_reg(base_addr, LATCH_TOD_NANO_SECOND);
+		ts->s = zxdh_read_reg(base_addr, LATCH_LOWER_TOD_SECOND);
+		ts->s |= (u64)zxdh_read_reg(base_addr, LATCH_HIGH_TOD_SECOND) << 32;
 
-		ns = zxdh_read_reg(adapter, LATCH_TOD_NANO_SECOND, PTP_M);
-		s = zxdh_read_reg(adapter, LATCH_LOWER_TOD_SECOND, PTP_M);
-		// hwts->s |= (uint64_t)zxdh_read_reg(adapter, LATCH_HIGH_TOD_SECOND, PTP_M) << 32;
+		ts++;
 
-		// ns += s * 1000000000ULL;
-		last_ns = ns;
-		last_s = s;
-        PTP_LOG_INFO("timestamp: cur:%llu.%09lu\n", low_sec*200, nsec);
+		GET_TSN_LATCH_NANO_REG(timer_no);
+		GET_TSN_LATCH_LOW_SEC_REG(timer_no);
+		GET_TSN_LATCH_HIGH_SEC_REG(timer_no);
+		// read one tsn timer
+		ts->ns = zxdh_read_reg(base_addr, nano_sec_reg);
+		ts->s = zxdh_read_reg(base_addr, low_sec_reg);
+		ts->s |= (u64)zxdh_read_reg(base_addr, high_sec_reg) << 32;
 
-#endif
+		*hwts = zxdh_read_reg(base_addr, LATCH_HARDWARE_TIME_LOW);
 
-    return IRQ_HANDLED;
-}
-EXPORT_SYMBOL(msix_local_pps_irq_from_risc_handler);
+		spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
+		// PTP_LOG_INFO("ts[]: 0x%x.%x, hwts: 0x%x\n", ts->s, ts->ns, *hwts);
+	}
 
-// for net_device driver get timestamp, param ptp get from get_tsn_clock
-// function. hw timestamp only use 32 bit.
-int get_pkt_timestamp(int32_t clock_no, struct zxdh_en_device *en_dev, struct time_stamps *ts, u32 *hwts)
-{
-    u32 nano_sec_reg;
-    u32 low_sec_reg;
-    u32 high_sec_reg;
-    int timer_no;
-    int run_mode_bit_shift;
-    u32 reg_val;
-    struct time_stamps temp_ts;
-    unsigned long flags;
-    uint64_t base_addr;
-    uint64_t bar_addr;
-    struct zxdh_ptp_private *adapter;
-    struct ptp_clock_info *ptp;
-    int phcidx;
-
-
-    if (NULL == en_dev || NULL == ts || NULL == hwts)
-        return -1;
-
-    adapter   = zxdh_ptp_get_ptp_private(en_dev);
-    for(phcidx = 0; phcidx < ZX_CLOCK_TIMER_NUM; phcidx++)
-    {
-        if(clock_no == ptp_clock_index(adapter->ptp_clock[phcidx]))
-        {
-            ptp = &adapter->ptp_caps[phcidx];
-            break;
-        }
-    }
-    if(phcidx == ZX_CLOCK_TIMER_NUM)
-    {
-        PTP_LOG_ERR("get phcindex fail\n");
-        return -1;
-    }
-    bar_addr = zxdh_ptp_get_bar_addr(adapter);
-    base_addr                        = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
-
-
-    PTP_LOG_INFO("ptp->name: %s, bar_addr: 0x%llx\n", ptp->name, bar_addr);
-    // first 80bit and second 80bit: both are 1588 timestamp
-    if (0 == strcmp(ptp->name, "ptp0"))
-    {
-        PTP_LOG_INFO("ptp0\n");
-        spin_lock_irqsave(&adapter->tmreg_lock, flags);
-
-        reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION);
-        reg_val &= ~(0x3 << PPS_RUN_MODE_BIT);
-        reg_val |= NORMAL_MODE << PPS_RUN_MODE_BIT;
-        zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val);
-
-        // config latch 1588 timer and hw timer
-        zxdh_write_reg(base_addr, TIMER_LACTH_SEL, 1 << LATCH_1588_TIMER | 1 << LATCH_HW_TIMER);
-
-        // enable latch
-        zxdh_write_reg(base_addr, TIMER_LATCH_EN, 1);
-
-        temp_ts.ns = zxdh_read_reg(base_addr, LATCH_TOD_NANO_SECOND);
-        temp_ts.s  = zxdh_read_reg(base_addr, LATCH_LOWER_TOD_SECOND);
-        temp_ts.s |= (u64)zxdh_read_reg(base_addr, LATCH_HIGH_TOD_SECOND) << 32;
-
-        ts->ns = temp_ts.ns;
-        ts->s  = temp_ts.s;
-
-        ts++;
-        ts->ns = temp_ts.ns;
-        ts->s  = temp_ts.s;
-
-        *hwts = zxdh_read_reg(base_addr, LATCH_HARDWARE_TIME_LOW);
-
-        spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
-        // PTP_LOG_INFO("ts[]: 0x%x.%x, hwts: 0x%x\n", ts->s, ts->ns, *hwts);
-    }
-    else  // first 80bit is 1588 timestamp, second 80bit is one tsn timestamp
-    {
-        timer_no = get_tsn_timer_no(ptp->name);
-        PTP_LOG_INFO("tsn: %d\n", timer_no);
-        PTP_CHECK_RANGE_WITH_RETURN(timer_no, TSN_TIMER_NAME_MIN_NO, TSN_TIMER_NAME_MAX_NO, -1);
-
-        spin_lock_irqsave(&adapter->tmreg_lock, flags);
-
-        reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION);
-        reg_val &= ~(0x3 << PPS_RUN_MODE_BIT);
-        reg_val |= NORMAL_MODE << PPS_RUN_MODE_BIT;
-        zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val);
-
-        // bit11~bit4, configure normal mode, should make sure bit15~bit12 enable
-        // first.
-        run_mode_bit_shift = 4 + timer_no * 2;
-        reg_val            = zxdh_read_reg(base_addr, TSN_TIME_CONFIGURATION);
-        reg_val &= ~(0x3 << run_mode_bit_shift);
-        reg_val |= NORMAL_MODE << run_mode_bit_shift;
-        zxdh_write_reg(base_addr, TSN_TIME_CONFIGURATION, reg_val);
-
-        // config latch 1588 and one tsn timer and hw timer
-        zxdh_write_reg(base_addr, TIMER_LACTH_SEL, 1 << LATCH_1588_TIMER | 1 << LATCH_HW_TIMER | 1 << (timer_no + 2));
-
-        // enable latch
-        zxdh_write_reg(base_addr, TIMER_LATCH_EN, 1);
-
-        // read 1588 timer
-        ts->ns = zxdh_read_reg(base_addr, LATCH_TOD_NANO_SECOND);
-        ts->s  = zxdh_read_reg(base_addr, LATCH_LOWER_TOD_SECOND);
-        ts->s |= (u64)zxdh_read_reg(base_addr, LATCH_HIGH_TOD_SECOND) << 32;
-
-        ts++;
-
-        GET_TSN_LATCH_NANO_REG(timer_no);
-        GET_TSN_LATCH_LOW_SEC_REG(timer_no);
-        GET_TSN_LATCH_HIGH_SEC_REG(timer_no);
-        // read one tsn timer
-        ts->ns = zxdh_read_reg(base_addr, nano_sec_reg);
-        ts->s  = zxdh_read_reg(base_addr, low_sec_reg);
-        ts->s |= (u64)zxdh_read_reg(base_addr, high_sec_reg) << 32;
-
-        *hwts = zxdh_read_reg(base_addr, LATCH_HARDWARE_TIME_LOW);
-
-        spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
-        // PTP_LOG_INFO("ts[]: 0x%x.%x, hwts: 0x%x\n", ts->s, ts->ns, *hwts);
-    }
-
-    return 0;
+	return 0;
 }
 EXPORT_SYMBOL(get_pkt_timestamp);
 
 #define PTPS_NUMS 3
-int enable_write_ts_to_fifo(struct zxdh_en_device *en_dev, u32 enable, u32 mac_number)
+enum reg_module get_ptps_module(u32 mac_number)
 {
-    uint64_t base_addr;
-    uint64_t bar_addr;
-    struct zxdh_ptp_private *adapter;
+	enum reg_module ptps_module;
+
+	switch (mac_number) {
+	case 0:
+		ptps_module = PTP_S0;
+		break;
+	case 1:
+		ptps_module = PTP_S1;
+		break;
+	case 2:
+		ptps_module = PTP_S2;
+		break;
+	default:
+		break;
+	}
+	PTP_LOG_INFO("ptps: %d\n", ptps_module);
+	return ptps_module;
+}
 
-    if (PTPS_NUMS <= mac_number)
-    {
-        PTP_LOG_ERR("mac number out of range\n");
-        return -1;
-    }
+int enable_write_ts_to_fifo(struct zxdh_en_device *en_dev, u32 enable,
+							u32 mac_number)
+{
+	uint64_t base_addr;
+	uint64_t bar_addr;
+	struct zxdh_ptp_private *adapter;
 
+	if (mac_number >= PTPS_NUMS) {
+		PTP_LOG_ERR("mac number out of range\n");
+		return -1;
+	}
 
-    if (NULL == en_dev)
-        return -1;
+	if (en_dev == NULL)
+		return -1;
 
-    adapter   = zxdh_ptp_get_ptp_private(en_dev);
-    bar_addr = zxdh_ptp_get_bar_addr(adapter);
-    base_addr                        = bar_addr + PTPS_HOST_BAR_OFFSET;
+	adapter = zxdh_ptp_get_ptp_private(en_dev);
+	bar_addr = zxdh_ptp_get_bar_addr(adapter);
+	base_addr = bar_addr + PTPS_HOST_BAR_OFFSET;
 
-    PTP_LOG_INFO("bar_addr: 0x%llx, enable: %u, mac: %u\n", bar_addr, enable, mac_number);
-    zxdh_write_reg(base_addr, PTPS_CONFIGURATION, enable);
+	PTP_LOG_INFO("bar_addr: 0x%llx, enable: %u, mac: %u\n", bar_addr, enable,
+				 mac_number);
+	zxdh_write_reg(base_addr, PTPS_CONFIGURATION, enable);
 
-    return 0;
+	return 0;
 }
 EXPORT_SYMBOL(enable_write_ts_to_fifo);
 
-int get_event_ts_info(struct zxdh_en_device *en_dev, struct ptp_buff *p_tsInfo, u32 mac_number)
+int get_event_ts_info(struct zxdh_en_device *en_dev, struct ptp_buff *p_tsInfo,
+					  u32 mac_number)
 {
-    u32 count;
-    int i;
+	u32 count;
+	int i;
 	uint64_t base_addr;
-    uint64_t bar_addr;
-    // enum reg_module ptps_module;
-    struct zxdh_ptp_private *adapter;
-
-    if (PTPS_NUMS <= mac_number)
-    {
-        PTP_LOG_ERR("mac number out of range\n");
-        return -1;
-    }
-
-    if (NULL == en_dev || NULL == p_tsInfo)
-    {
-        PTP_LOG_ERR("input pointer null\n");
-        return -1;
-    }
-   
-    adapter   = zxdh_ptp_get_ptp_private(en_dev);
-    bar_addr = zxdh_ptp_get_bar_addr(adapter);
-    base_addr                        = bar_addr + PTPS_HOST_BAR_OFFSET;
-
-    // the maximum count is 64
-    count = zxdh_read_reg(base_addr, PTP1588_EVENT_MESSAGE_FIFO_STATUS) & 0xff;
-    // half is timestamp and half is match info(messageType, sourcePortIdentity,
-    // sequenceId)
-    if(count > PTP_ENCRYPTED_MESG_MAX_NUM)
-    {
-        PTP_LOG_ERR("encrypted ptp message out of range!\n");
-        return -1;
-    }
-    count /= 2;
-    PTP_LOG_INFO("count: %d\n", count);
-
-    for (i = 0; i < count; i++)
-    {
-        zxdh_write_reg(base_addr, PTPS_TIMER_CONTROL, 1);
-        // read timestamp
-        p_tsInfo->ptpRegInfo[i].cfVal[0] = zxdh_read_reg(base_addr, PTP1588_EVENT_MESSAGE_TS_LOW);
-        p_tsInfo->ptpRegInfo[i].cfVal[1] = zxdh_read_reg(base_addr, PTP1588_EVENT_MESSAGE_TS_HIGH);
-
-        PTP_LOG_INFO("i: %d, low: 0x%x, high: 0x%x\n", i, p_tsInfo->ptpRegInfo[i].cfVal[0], p_tsInfo->ptpRegInfo[i].cfVal[1]);
-        zxdh_write_reg(base_addr, PTPS_TIMER_CONTROL, 1);
-        // read messageType, sourcePortIdentity, sequenceId
-        p_tsInfo->ptpRegInfo[i].matchInfo = zxdh_read_reg(base_addr, PTP1588_EVENT_MESSAGE_TS_LOW);
-        PTP_LOG_INFO("i: %d, matchInfo: 0x%x\n", i, p_tsInfo->ptpRegInfo[i].matchInfo);
-    }
-    p_tsInfo->cfCount = count;
-    PTP_LOG_INFO("success\n");
-    return 0;
+	uint64_t bar_addr;
+	// enum reg_module ptps_module;
+	struct zxdh_ptp_private *adapter;
+
+	if (mac_number >= PTPS_NUMS) {
+		PTP_LOG_ERR("mac number out of range\n");
+		return -1;
+	}
+
+	if (en_dev == NULL || p_tsInfo == NULL) {
+		PTP_LOG_ERR("input pointer null\n");
+		return -1;
+	}
+
+	adapter = zxdh_ptp_get_ptp_private(en_dev);
+	bar_addr = zxdh_ptp_get_bar_addr(adapter);
+	base_addr = bar_addr + PTPS_HOST_BAR_OFFSET;
+
+#if 1
+	// the maximum count is 64
+	count = zxdh_read_reg(base_addr, PTP1588_EVENT_MESSAGE_FIFO_STATUS) & 0xff;
+	// half is timestamp and half is match info(messageType, sourcePortIdentity,
+	// sequenceId)
+	count /= 2;
+	PTP_LOG_INFO("count: %d\n", count);
+
+	for (i = 0; i < count; i++) {
+		zxdh_write_reg(base_addr, PTPS_TIMER_CONTROL, 1);
+		// read timestamp
+		p_tsInfo->ptpRegInfo[i].cfVal[0] =
+				zxdh_read_reg(base_addr, PTP1588_EVENT_MESSAGE_TS_LOW);
+		p_tsInfo->ptpRegInfo[i].cfVal[1] =
+				zxdh_read_reg(base_addr, PTP1588_EVENT_MESSAGE_TS_HIGH);
+
+		PTP_LOG_INFO("i: %d, low: 0x%x, high: 0x%x\n", i,
+					 p_tsInfo->ptpRegInfo[i].cfVal[0],
+					 p_tsInfo->ptpRegInfo[i].cfVal[1]);
+		zxdh_write_reg(base_addr, PTPS_TIMER_CONTROL, 1);
+		// read messageType, sourcePortIdentity, sequenceId
+		p_tsInfo->ptpRegInfo[i].matchInfo =
+				zxdh_read_reg(base_addr, PTP1588_EVENT_MESSAGE_TS_LOW);
+		PTP_LOG_INFO("i: %d, matchInfo: 0x%x\n", i,
+					 p_tsInfo->ptpRegInfo[i].matchInfo);
+	}
+	p_tsInfo->cfCount = count;
+#endif
+	PTP_LOG_INFO("success\n");
+	return 0;
 }
 EXPORT_SYMBOL(get_event_ts_info);
 
-int32_t set_interrupt_capture_timer(struct zxdh_en_device *en_dev, uint32_t index)
+int32_t set_interrupt_capture_timer(struct zxdh_en_device *en_dev,
+									uint32_t index)
 {
-    struct zxdh_ptp_private *adapter;
-    if (NULL == en_dev)
-        return -1;
-
-    if(index > INTERRUPT_CAP_TIMER_MAX_NO)
-    {
-        PTP_LOG_INFO("capture_timer: %u out of range!\n", index);
-        return -1;
-    }
-    adapter   = zxdh_ptp_get_ptp_private(en_dev);
-    adapter->interrupt_capture_timer = index;
-    PTP_LOG_INFO("index: %u\n",index);
-    PTP_LOG_INFO("pci_ioremap_addr[0]=0x%llx,pcie_id: 0x%x, vport: 0x%x, phy_port: %u\n",adapter->pdev->pci_ioremap_addr[0], adapter->pdev->pcie_id, adapter->pdev->vport, adapter->pdev->phy_port);
-    return 0;
+	struct zxdh_ptp_private *adapter;
+	if (en_dev == NULL)
+		return -1;
+
+	adapter = zxdh_ptp_get_ptp_private(en_dev);
+	adapter->interrupt_capture_timer = index;
+	PTP_LOG_INFO("index: %u\n", index);
+	PTP_LOG_INFO(
+			"pci_ioremap_addr[0]=0x%llx,pcie_id: 0x%x, vport: 0x%x, phy_port: %u\n",
+			adapter->pdev->pci_ioremap_addr[0], adapter->pdev->pcie_id,
+			adapter->pdev->vport, adapter->pdev->phy_port);
+	return 0;
 }
 EXPORT_SYMBOL(set_interrupt_capture_timer);
 
-int32_t zxdh_set_pps_selection(struct zxdh_en_device *en_dev, uint32_t pps_type, uint32_t selection)
+int32_t zxdh_set_pps_selection(struct zxdh_en_device *en_dev, uint32_t pps_type,
+							   uint32_t selection)
 {
-    struct zxdh_ptp_private *adapter;
-    uint64_t base_addr;
-    uint64_t bar_addr;
-    if (NULL == en_dev)
-        return -1;
-
-    if(pps_type > PP1S_EXTERNAL || selection > PP1S_TSN3)
-        return -1;
-
-    adapter   = zxdh_ptp_get_ptp_private(en_dev);
-    bar_addr = zxdh_ptp_get_bar_addr(adapter);
-    base_addr         = bar_addr + PTP_HOST_BAR_OFFSET;
-
-    PTP_LOG_INFO("pps_type: %s, selection: %u\n", pps[pps_type], selection);
-
-    switch (pps_type)
-    {
-        case PP1S_OUT:
-            zxdh_write_reg(base_addr, PP1S_OUT_SEL, selection);
-            break;
-        case PP1S_TEST:
-            zxdh_write_reg(base_addr, TEST_PP1S_SEL, selection);
-            break;
-        case PP1S_EXTERNAL:
-            // zxdh_write_reg(adapter, PP1S_EXTERNAL_SEL, sel->config, PTP_TOP);//
-            // 这个用PTP_CLK_REQ_EXTTS来配置
-            break;
-        default:
-            break;
-    }
-
-    return 0;
+	struct zxdh_ptp_private *adapter;
+	uint64_t base_addr;
+	uint64_t bar_addr;
+	if (en_dev == NULL)
+		return -1;
+
+	if (pps_type > PP1S_EXTERNAL || selection > PP1S_TSN3)
+		return -1;
+
+	adapter = zxdh_ptp_get_ptp_private(en_dev);
+	bar_addr = zxdh_ptp_get_bar_addr(adapter);
+	base_addr = bar_addr + PTP_HOST_BAR_OFFSET;
+
+	PTP_LOG_INFO("pps_type: %s, selection: %u\n", pps[pps_type], selection);
+
+	switch (pps_type) {
+	case PP1S_OUT:
+		zxdh_write_reg(base_addr, PP1S_OUT_SEL, selection);
+		break;
+	case PP1S_TEST:
+		zxdh_write_reg(base_addr, TEST_PP1S_SEL, selection);
+		break;
+	case PP1S_EXTERNAL:
+		// zxdh_write_reg(adapter, PP1S_EXTERNAL_SEL, sel->config, PTP_TOP);//
+		// 这个用PTP_CLK_REQ_EXTTS来配置
+		break;
+	default:
+		break;
+	}
+
+	return 0;
 }
 EXPORT_SYMBOL(zxdh_set_pps_selection);
 
-int32_t zxdh_set_pd_detection(struct zxdh_en_device *en_dev, uint32_t pd_index, uint32_t pd_input1, uint32_t pd_input2)
+int32_t zxdh_set_pd_detection(struct zxdh_en_device *en_dev, uint32_t pd_index,
+							  uint32_t pd_input1, uint32_t pd_input2)
 {
-    struct zxdh_ptp_private *adapter;
-    uint64_t base_addr;
-    uint32_t reg_val;
-    uint64_t bar_addr;
-    if (NULL == en_dev)
-        return -1;
-
-    adapter   = zxdh_ptp_get_ptp_private(en_dev);
-    bar_addr = zxdh_ptp_get_bar_addr(adapter);
-    base_addr         = bar_addr + PTP_HOST_BAR_OFFSET;
-
-    PTP_LOG_INFO("pd_index: %u, pd_input1: %u, pd_input2: %u\n", pd_index, pd_input1, pd_input2);
-
-    // bit1~0: Pd_U1_Sel0   bit3~2: Pd_U1_Sel1.
-    reg_val = pd_input1 | pd_input2 << 3;
-
-    if (PHASE_DETECTION1 == pd_index)
-    {
-        zxdh_write_reg(base_addr, PD_U1_SEL, reg_val);
-    }
-    else if(PHASE_DETECTION2 == pd_index)
-    {
-        zxdh_write_reg(base_addr, PD_U2_SEL, reg_val);
-    }
-    else
-    {
-        PTP_LOG_ERR("pd_index error\n");
-        return -1;
-    }
-
-    return 0;
+	struct zxdh_ptp_private *adapter;
+	uint64_t base_addr;
+	uint32_t reg_val;
+	uint64_t bar_addr;
+	if (en_dev == NULL)
+		return -1;
+
+	adapter = zxdh_ptp_get_ptp_private(en_dev);
+	bar_addr = zxdh_ptp_get_bar_addr(adapter);
+	base_addr = bar_addr + PTP_HOST_BAR_OFFSET;
+
+	PTP_LOG_INFO("pd_index: %u, pd_input1: %u, pd_input2: %u\n", pd_index,
+				 pd_input1, pd_input2);
+
+	// bit1~0: Pd_U1_Sel0   bit3~2: Pd_U1_Sel1.
+	reg_val = pd_input1 | pd_input2 << 3;
+
+	if (pd_index == PHASE_DETECTION1) {
+		zxdh_write_reg(base_addr, PD_U1_SEL, reg_val);
+		// pd_result = zxdh_read_reg(base_addr, PD_U1_RESULT);
+	} else if (pd_index == PHASE_DETECTION2) {
+		zxdh_write_reg(base_addr, PD_U2_SEL, reg_val);
+		// pd_result = zxdh_read_reg(base_addr, PD_U2_RESULT);
+	} else {
+		PTP_LOG_ERR("pd_index error\n");
+		return -1;
+	}
+
+	return 0;
 }
 EXPORT_SYMBOL(zxdh_set_pd_detection);
 
-int32_t zxdh_get_pd_value(struct zxdh_en_device *en_dev, uint32_t pd_index, uint32_t *pd_result)
+int32_t zxdh_get_pd_value(struct zxdh_en_device *en_dev, uint32_t pd_index,
+						  uint32_t *pd_result)
 {
-    struct zxdh_ptp_private *adapter;
-    uint64_t base_addr;
-    uint64_t bar_addr;
-    if (NULL == en_dev)
-        return -1;
-
-    adapter   = zxdh_ptp_get_ptp_private(en_dev);
-    bar_addr = zxdh_ptp_get_bar_addr(adapter);
-    base_addr         = bar_addr + PTP_HOST_BAR_OFFSET;
-
-    if (PHASE_DETECTION1 == pd_index)
-    {
-        *pd_result = zxdh_read_reg(base_addr, PD_U1_RESULT);
-    }
-    else if(PHASE_DETECTION2 == pd_index)
-    {
-        *pd_result = zxdh_read_reg(base_addr, PD_U2_RESULT);
-    }
-    else
-    {
-        PTP_LOG_ERR("pd_index error\n");
-        return -1;
-    }
-    PTP_LOG_INFO("pd_index: %u, pd_result: 0x%x\n", pd_index, *pd_result);
-
-    return 0;
+	struct zxdh_ptp_private *adapter;
+	uint64_t base_addr;
+	uint64_t bar_addr;
+	if (en_dev == NULL)
+		return -1;
+
+	adapter = zxdh_ptp_get_ptp_private(en_dev);
+	bar_addr = zxdh_ptp_get_bar_addr(adapter);
+	base_addr = bar_addr + PTP_HOST_BAR_OFFSET;
+
+	if (pd_index == PHASE_DETECTION1) {
+		*pd_result = zxdh_read_reg(base_addr, PD_U1_RESULT);
+	} else if (pd_index == PHASE_DETECTION2) {
+		*pd_result = zxdh_read_reg(base_addr, PD_U2_RESULT);
+	} else {
+		PTP_LOG_ERR("pd_index error\n");
+		return -1;
+	}
+	PTP_LOG_INFO("pd_index: %u, pd_result: 0x%x\n", pd_index, *pd_result);
+
+	return 0;
 }
 EXPORT_SYMBOL(zxdh_get_pd_value);
 
 int get_hw_timestamp(struct zxdh_en_device *en_dev, u32 *hwts)
 {
-    u32 reg_val;
-    unsigned long flags;
-    uint64_t base_addr;
-    uint64_t bar_addr;
-    struct zxdh_ptp_private *adapter;
-
-
-    if (NULL == en_dev || NULL == hwts)
-        return -1;
-
-    adapter   = zxdh_ptp_get_ptp_private(en_dev);
-    bar_addr = zxdh_ptp_get_bar_addr(adapter);
-    base_addr                        = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
+	u32 reg_val;
+	unsigned long flags;
+	uint64_t base_addr;
+	uint64_t bar_addr;
+	struct zxdh_ptp_private *adapter;
 
-    spin_lock_irqsave(&adapter->tmreg_lock, flags);
+	if (NULL == en_dev || NULL == hwts)
+		return -1;
 
+	adapter = zxdh_ptp_get_ptp_private(en_dev);
+	bar_addr = zxdh_ptp_get_bar_addr(adapter);
+	base_addr = bar_addr + PTP_HOST_BAR_OFFSET + PTPM_OFFSET_WITH_TOP;
 
-    reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION);
-    reg_val &= ~(0x3 << PPS_RUN_MODE_BIT);
-    reg_val |= NORMAL_MODE << PPS_RUN_MODE_BIT;
-    zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val);
+	spin_lock_irqsave(&adapter->tmreg_lock, flags);
 
-    // config latch  hw timer
-    zxdh_write_reg(base_addr, TIMER_LACTH_SEL, 1 << LATCH_HW_TIMER);
+	reg_val = zxdh_read_reg(base_addr, PTP_CONFIGURATION);
+	reg_val &= ~(0x3 << PPS_RUN_MODE_BIT);
+	reg_val |= NORMAL_MODE << PPS_RUN_MODE_BIT;
+	zxdh_write_reg(base_addr, PTP_CONFIGURATION, reg_val);
 
-    // enable latch
-    zxdh_write_reg(base_addr, TIMER_LATCH_EN, 1);
+	// config latch  hw timer
+	zxdh_write_reg(base_addr, TIMER_LACTH_SEL, 1 << LATCH_HW_TIMER);
 
-    *hwts = zxdh_read_reg(base_addr, LATCH_HARDWARE_TIME_LOW);
+	// enable latch
+	zxdh_write_reg(base_addr, TIMER_LATCH_EN, 1);
 
+	*hwts = zxdh_read_reg(base_addr, LATCH_HARDWARE_TIME_LOW);
 
-    spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
-    // PTP_LOG_INFO("ts[]: 0x%x.%x, hwts: 0x%x\n", ts->s, ts->ns, *hwts);
+	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
+	// PTP_LOG_INFO("ts[]: 0x%x.%x, hwts: 0x%x\n", ts->s, ts->ns, *hwts);
 
-    return 0;
+	return 0;
 }
 EXPORT_SYMBOL(get_hw_timestamp);
 
-
+/**
+ * zxdh_ptp_init
+ *
+ * This function performs the required steps for enabling ptp
+ * support. If ptp support has already been loaded it simply calls the
+ * cyclecounter init routine and exits.
+ */
 int zxdh_ptp_init(struct dh_core_dev *zxdev)
 {
-    struct zxdh_ptp_private *zxp;
-    int err = -ENOMEM;
-    int i;
-
-    uint32_t reg;
-    uint64_t base_addr;
-    int size;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(zxdev);
-
-    base_addr = pf_dev->pci_ioremap_addr[0] + PTP_HOST_BAR_OFFSET;
-
-    zxp = kzalloc(sizeof(*zxp), GFP_KERNEL);
-    if (!zxp)
-    {
-        PTP_LOG_ERR("zxp kzalloc failed\n");
-        goto no_memory;
-    }
-
-    err = -ENODEV;
-
-    zxp->ptp_caps[0].owner = THIS_MODULE;
-    strlcpy(zxp->ptp_caps[0].name, "ptp0", sizeof(zxp->ptp_caps[0].name));
-
-    zxp->ptp_caps[0].max_adj           = 999999999;
-    zxp->ptp_caps[0].n_alarm           = 0;
-    zxp->ptp_caps[0].n_ext_ts          = 0;  // ptp_chardev.c: ptp_ioctl: if (req.extts.index >= ops->n_ext_ts) 需要改初值
-    zxp->ptp_caps[0].n_per_out         = 0;
-    zxp->ptp_caps[0].n_pins            = 0;  //
-    zxp->ptp_caps[0].pps               = 1;
-    zxp->ptp_caps[0].adjfreq           = zx_ptp_adjfreq;
-    zxp->ptp_caps[0].adjtime           = zxdh_ptp_adjtime;
-    zxp->ptp_caps[0].gettime64         = zxdh_ptp_gettime;
-    zxp->ptp_caps[0].settime64         = zxdh_ptp_settime;
-    zxp->ptp_caps[0].enable            = zxdh_ptp_enable;
-
-    zxp->ptp_clock[0] = ptp_clock_register(&zxp->ptp_caps[0], &zxdev->pdev->dev);
-    if (IS_ERR(zxp->ptp_clock[0]))
-    {
-        zxp->ptp_clock[0] = NULL;
-        PTP_LOG_ERR("ptp_clock_register ptp0 failed\n");
-        goto no_clock;
-    }
-
-    for (i = 0; i < ZX_TSN_TIMER_NUM; i++)
-    {
-        zxp->ptp_caps[i+1].owner = THIS_MODULE;
-        size = snprintf(zxp->ptp_caps[i + 1].name, sizeof(zxp->ptp_caps[i+1].name), "tsn%d", i);
-        if(size >= sizeof(zxp->ptp_caps[i+1].name))
-    		zxp->ptp_caps[i + 1].name[sizeof(zxp->ptp_caps[i+1].name)-1] = '\0';
-
-        zxp->ptp_caps[i + 1].max_adj   = 999999999;
-        zxp->ptp_caps[i + 1].n_alarm   = 0;
-        zxp->ptp_caps[i + 1].n_ext_ts  = 0;
-        zxp->ptp_caps[i + 1].n_per_out = 0;
-        zxp->ptp_caps[i + 1].n_pins    = 0;
-        zxp->ptp_caps[i + 1].pps = 0;
-        zxp->ptp_caps[i + 1].adjfreq           = zxdh_tsn_adjfreq;
-        zxp->ptp_caps[i + 1].adjtime           = zxdh_tsn_adjtime;
-        zxp->ptp_caps[i + 1].gettime64         = zxdh_tsn_gettime;
-        zxp->ptp_caps[i + 1].settime64         = zxdh_tsn_settime;
-        zxp->ptp_caps[i + 1].enable            = zxdh_tsn_enable;
-        zxp->ptp_clock[i + 1] = ptp_clock_register(&zxp->ptp_caps[i + 1], &zxdev->pdev->dev);
-        if (IS_ERR(zxp->ptp_clock[i + 1]))
-        {
-            zxp->ptp_clock[i + 1] = NULL;
-            PTP_LOG_ERR("ptp_clock_register tsn%d failed\n", i);
-            goto no_clock;
-        }
-    }
-
-    spin_lock_init(&zxp->tmreg_lock);
-    mutex_init(&zxp->ptp_clk_mutex);
-
-    pf_dev->ptp = zxp;
-    zxp->pdev = pf_dev;
-
-    reg = zxdh_read_reg(base_addr + PTPM_OFFSET_WITH_TOP, PTP_CONFIGURATION);
-    reg |= 1 << 15;
-    zxdh_write_reg(base_addr + PTPM_OFFSET_WITH_TOP, PTP_CONFIGURATION, reg);
-    // enable four tsn timer and tsn pps enable
-    zxdh_write_reg(base_addr + PTPM_OFFSET_WITH_TOP, TSN_TIME_CONFIGURATION, 0xff000);
-
-    // timesync delay
-    zxdh_write_reg(base_addr, TSN_GROUP_NANO_SEC_DELAY0, 0x1);
-    zxdh_write_reg(base_addr, TSN_GROUP_NANO_SEC_DELAY1, 0x1);
-    zxdh_write_reg(base_addr, TSN_GROUP_NANO_SEC_DELAY2, 0x1);
-    zxdh_write_reg(base_addr, TSN_GROUP_NANO_SEC_DELAY3, 0x1);
-    zxdh_write_reg(base_addr, PTP1588_NP_NANO_SEC_DELAY, 0x1);
-    zxdh_write_reg(base_addr, PTP1588_NVME_NANO_SEC_DELAY1, 0x13);
-    zxdh_write_reg(base_addr, PTP1588_NVME_NANO_SEC_DELAY2, 0x13);
-    zxdh_write_reg(base_addr, PTP1588_RDMA_NANO_SEC_DELAY, 0xC);
-
-    return 0;
+	struct zxdh_ptp_private *zxp;
+	int err = -ENOMEM;
+	int i;
+
+	uint32_t reg;
+	uint64_t base_addr;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(zxdev);
+
+	LOG_INFO("enter\n");
+	base_addr = pf_dev->pci_ioremap_addr[0] + PTP_HOST_BAR_OFFSET;
+
+#if 1
+	zxp = kzalloc(sizeof(*zxp), GFP_KERNEL);
+	if (!zxp)
+		goto no_memory;
+
+	err = -ENODEV;
+
+	zxp->ptp_caps[0].owner = THIS_MODULE;
+	strlcpy(zxp->ptp_caps[0].name, "ptp0", sizeof(zxp->ptp_caps[0].name));
+
+	zxp->ptp_caps[0].max_adj = 999999999;
+	zxp->ptp_caps[0].n_alarm = 0;
+	zxp->ptp_caps[0].n_ext_ts =
+			0; // ptp_chardev.c: ptp_ioctl: if (req.extts.index >= ops->n_ext_ts)
+	// 需要改初值
+	zxp->ptp_caps[0].n_per_out = 0;
+	zxp->ptp_caps[0].n_pins = 0; //
+	zxp->ptp_caps[0].pps = 1;
+	zxp->ptp_caps[0].adjfreq = zx_ptp_adjfreq;
+	zxp->ptp_caps[0].adjtime = zxdh_ptp_adjtime;
+	zxp->ptp_caps[0].gettime64 = zxdh_ptp_gettime;
+	zxp->ptp_caps[0].settime64 = zxdh_ptp_settime;
+	zxp->ptp_caps[0].enable = zxdh_ptp_enable;
+	// zxp->ptp_caps[0].reg_operate       = zxdh_reg_operate;
+	// zxp->ptp_caps[0].pp1s_sel          = zxdh_pp1s_sel;
+	// zxp->ptp_caps[0].phase_detect      = zxdh_phase_detection;
+	// zxp->ptp_caps[0].set_capture_timer = zxdh_set_capture_timer;
+
+	zxp->ptp_clock[0] =
+			ptp_clock_register(&zxp->ptp_caps[0], &zxdev->pdev->dev);
+	if (IS_ERR(zxp->ptp_clock[0])) {
+		zxp->ptp_clock[0] = NULL;
+		PTP_LOG_ERR("ptp_clock_register ptp0 failed\n");
+		goto no_clock;
+	}
+
+	for (i = 0; i < ZX_TSN_TIMER_NUM; i++) {
+		zxp->ptp_caps[i].owner = THIS_MODULE;
+		snprintf(zxp->ptp_caps[i + 1].name, sizeof(zxp->ptp_caps[i].name),
+				 "tsn%d", i);
+
+		zxp->ptp_caps[i + 1].max_adj = 999999999;
+		zxp->ptp_caps[i + 1].n_alarm = 0;
+		zxp->ptp_caps[i + 1].n_ext_ts = 0;
+		zxp->ptp_caps[i + 1].n_per_out = 0;
+		zxp->ptp_caps[i + 1].n_pins = 0;
+		zxp->ptp_caps[i + 1].pps = 0;
+		zxp->ptp_caps[i + 1].adjfreq = zxdh_tsn_adjfreq;
+		zxp->ptp_caps[i + 1].adjtime = zxdh_tsn_adjtime;
+		zxp->ptp_caps[i + 1].gettime64 = zxdh_tsn_gettime;
+		zxp->ptp_caps[i + 1].settime64 = zxdh_tsn_settime;
+		zxp->ptp_caps[i + 1].enable = zxdh_tsn_enable;
+		// zxp->ptp_caps[i + 1].reg_operate       = zxdh_tsn_reg_operate;
+		// zxp->ptp_caps[i + 1].pp1s_sel          = zxdh_tsn_pp1s_sel;
+		// zxp->ptp_caps[i + 1].phase_detect      = zxdh_tsn_phase_detection;
+		// zxp->ptp_caps[i + 1].set_capture_timer = zxdh_set_tsn_capture_timer;
+		zxp->ptp_clock[i + 1] =
+				ptp_clock_register(&zxp->ptp_caps[i + 1], &zxdev->pdev->dev);
+		if (IS_ERR(zxp->ptp_clock[i + 1])) {
+			zxp->ptp_clock[i + 1] = NULL;
+			PTP_LOG_ERR("ptp_clock_register tsn%d failed\n", i);
+			goto no_clock;
+		}
+	}
+
+	spin_lock_init(&zxp->tmreg_lock);
+	mutex_init(&zxp->ptp_clk_mutex);
+
+	pf_dev->ptp = zxp;
+	zxp->pdev = pf_dev;
+
+	// // 需要先开ptps再开ptpm: 需要先配置ptps的补偿值，否则精度有误差
+	// // sync_hw_time_compensaton(0, PTP_S0);
+	// // sync_hw_time_compensaton(0, PTP_S1);
+	// // sync_hw_time_compensaton(0, PTP_S2);
+	reg = zxdh_read_reg(base_addr + PTPM_OFFSET_WITH_TOP, PTP_CONFIGURATION);
+	reg |= 1 << 15;
+	zxdh_write_reg(base_addr + PTPM_OFFSET_WITH_TOP, PTP_CONFIGURATION, reg);
+	// enable four tsn timer and tsn pps enable
+	zxdh_write_reg(base_addr + PTPM_OFFSET_WITH_TOP, TSN_TIME_CONFIGURATION,
+				   0xff000);
+
+	// timesync delay
+	zxdh_write_reg(base_addr, TSN_GROUP_NANO_SEC_DELAY0, 0x1);
+	zxdh_write_reg(base_addr, TSN_GROUP_NANO_SEC_DELAY1, 0x1);
+	zxdh_write_reg(base_addr, TSN_GROUP_NANO_SEC_DELAY2, 0x1);
+	zxdh_write_reg(base_addr, TSN_GROUP_NANO_SEC_DELAY3, 0x1);
+	zxdh_write_reg(base_addr, PTP1588_NP_NANO_SEC_DELAY, 0x1);
+	zxdh_write_reg(base_addr, PTP1588_NVME_NANO_SEC_DELAY1, 0x13);
+	zxdh_write_reg(base_addr, PTP1588_NVME_NANO_SEC_DELAY2, 0x13);
+	zxdh_write_reg(base_addr, PTP1588_RDMA_NANO_SEC_DELAY, 0xC);
+
+#endif
+	PTP_LOG_INFO("success\n");
+	return 0;
 
 no_clock:
-    kfree(zxp);
+	kfree(zxp);
 no_memory:
-    return err;
+	return err;
 }
 EXPORT_SYMBOL(zxdh_ptp_init);
 
 void zxdh_ptp_stop(struct dh_core_dev *zxdev)
 {
-    int i;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(zxdev);
-    struct zxdh_ptp_private *zxp = pf_dev->ptp;
+	int i;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(zxdev);
+	struct zxdh_ptp_private *zxp = pf_dev->ptp;
 
-    if (NULL == zxp)
-        return;
+	if (zxp == NULL)
+		return;
 
-    for (i = 0; i < ZX_CLOCK_TIMER_NUM; i++)
-    {
-        if (zxp->ptp_clock[i])
-            ptp_clock_unregister(zxp->ptp_clock[i]);
-    }
+	for (i = 0; i < ZX_CLOCK_TIMER_NUM; i++) {
+		if (zxp->ptp_clock[i])
+			ptp_clock_unregister(zxp->ptp_clock[i]);
+	}
 
-    kfree(zxp);
+	kfree(zxp);
 }
 EXPORT_SYMBOL(zxdh_ptp_stop);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp.h b/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp.h
index 56d815586550a923e7e0f9c20654a89557c0dcee..385832c442ee107dab6a20944156ea96f741eec7 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp.h
@@ -4,95 +4,76 @@
 #include <linux/ptp_clock_kernel.h>
 #include "../en_pf.h"
 
-#define ZX_CLOCK_TIMER_NUM   5 // 1st: ptp, other: tsn
-#define ZX_TSN_TIMER_NUM     4
+#define ZX_CLOCK_TIMER_NUM 5 // 1st: ptp, other: tsn
+#define ZX_TSN_TIMER_NUM 4
 
-#define PTP_REG_INFO_NUM     32
-#define PTP_ENCRYPTED_MESG_MAX_NUM   64
+#define PTP_REG_INFO_NUM 32
 
-#define PTP_DRIVER_UNINIT    0
-#define PTP_DRIVER_INITED    1
+#define PTP_DRIVER_UNINIT 0
+#define PTP_DRIVER_INITED 1
 
-#define PTP_HOST_BAR_OFFSET  0xc000
+#define PTP_HOST_BAR_OFFSET 0xc000
 #define PTPS_HOST_BAR_OFFSET 0x34000
 
-#define PHASE_DETECTION1     1
-#define PHASE_DETECTION2     2
+#define PHASE_DETECTION1 1
+#define PHASE_DETECTION2 2
 
-#define PTPM_INTERRUPT_BIT_NUM    5
+#define PTPM_INTERRUPT_BIT_NUM 5
 
-#define TSN_TIMER_NAME_MIN_NO     0
-#define TSN_TIMER_NAME_MAX_NO     3
-
-#define INTERRUPT_CAP_TIMER_MIN_NO    0
-#define INTERRUPT_CAP_TIMER_MAX_NO    4
-#define PTP_CHECK_RANGE_WITH_RETURN(val, min, max, ret) \
-    do { \
-        if(!(min <= val && val <= max)) \
-            return ret; \
-    }while(0)
-
-struct time_stamps
-{
+struct time_stamps {
 	u64 s;
 	u32 ns;
 };
 
-struct pkt_hw_ts
-{
+struct pkt_hw_ts {
 	struct time_stamps ts[2];
 };
 
-enum
-{
-    PP1S_OUT,
-    PP1S_TEST,
-    PP1S_EXTERNAL, // maybe use PTP_CLK_REQ_EXTTS
+enum {
+	PP1S_OUT,
+	PP1S_TEST,
+	PP1S_EXTERNAL, // maybe use PTP_CLK_REQ_EXTTS
 };
 
-typedef enum
-{
-    // PPS_OUT / TEST_PP1S / EXTERNAL_PP1S selection:
-    PP1S_REF0,
-    PP1S_REF1,
-    // PPS_OUT / TEST_PP1S  selection:
-    PP1S_LOCAL,
-    PP1S_1588,
-    // TEST PP1S selection only:
-    PP1S_TSN0,
-    PP1S_TSN1,
-    PP1S_TSN2,
-    PP1S_TSN3
-}PPS_SELECT;
+typedef enum {
+	// PPS_OUT / TEST_PP1S / EXTERNAL_PP1S selection:
+	PP1S_REF0,
+	PP1S_REF1,
+	// PPS_OUT / TEST_PP1S  selection:
+	PP1S_LOCAL,
+	PP1S_1588,
+	// TEST PP1S selection only:
+	PP1S_TSN0,
+	PP1S_TSN1,
+	PP1S_TSN2,
+	PP1S_TSN3
+} PPS_SELECT;
 
 struct zxdh_ptp_private {
-    // void __iomem *ptpm_regs;
-    // void __iomem *ptp_top_regs;
-    // void __iomem *ptps0_regs;
-    // void __iomem *ptps1_regs;
-    // void __iomem *ptps2_regs;
-
-    struct mutex ptp_clk_mutex;
-    struct zxdh_pf_device *pdev;
-    struct ptp_clock *ptp_clock[ZX_CLOCK_TIMER_NUM];
+	// void __iomem *ptpm_regs;
+	// void __iomem *ptp_top_regs;
+	// void __iomem *ptps0_regs;
+	// void __iomem *ptps1_regs;
+	// void __iomem *ptps2_regs;
+
+	struct mutex ptp_clk_mutex;
+	struct zxdh_pf_device *pdev;
+	struct ptp_clock *ptp_clock[ZX_CLOCK_TIMER_NUM];
 	struct ptp_clock_info ptp_caps[ZX_CLOCK_TIMER_NUM];
-    unsigned int pps_channel;  // externel pps0/pps1
-    unsigned int interrupt_capture_timer;
-
-    spinlock_t tmreg_lock;
+	unsigned int pps_channel; // externel pps0/pps1
+	unsigned int interrupt_capture_timer;
 
+	spinlock_t tmreg_lock;
 };
 
-struct ptp_reg_info
-{
-    uint32_t cfVal[2];
-    uint32_t matchInfo;
+struct ptp_reg_info {
+	uint32_t cfVal[2];
+	uint32_t matchInfo;
 };
 
-struct ptp_buff
-{
-    uint32_t cfCount;
-    struct ptp_reg_info ptpRegInfo[PTP_REG_INFO_NUM];
+struct ptp_buff {
+	uint32_t cfCount;
+	struct ptp_reg_info ptpRegInfo[PTP_REG_INFO_NUM];
 };
 
 int zxdh_ptp_init(struct dh_core_dev *zxdev);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp_common.h b/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp_common.h
index 902e507c2c873f5714059f1367f18d89ea2c73d5..6839bfc40bc437f2847e83d51b1de6f5073002d3 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp_common.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp_common.h
@@ -8,5 +8,4 @@
 #define PTP_LOG_DEBUG(fmt, arg...) DH_LOG_DEBUG(MODULE_PTP, fmt, ##arg);
 #define PTP_LOG_WARN(fmt, arg...) DH_LOG_WARNING(MODULE_PTP, fmt, ##arg);
 
-
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp_regs.h b/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp_regs.h
index 0103e922e7205a7fe41958c962a7851392ce0fc8..71691a605bc304ea4fcc82ad252c8519afcf7b33 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp_regs.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_ptp/zxdh_ptp_regs.h
@@ -3,458 +3,463 @@
 
 /**************************** ptpm start **************************/
 
-#define PTPM_OFFSET_WITH_TOP        0x4000
+#define PTPM_OFFSET_WITH_TOP 0x4000
 
-#define EXTERNAL_PPS_BIT            4
-#define TRIGGER_OUT_BIT             1
-#define TRIGGER_IN_BIT              0
+#define EXTERNAL_PPS_BIT 4
+#define TRIGGER_OUT_BIT 1
+#define TRIGGER_IN_BIT 0
 /* bit4: pps_in_status
-          0: not receive pps
-          1: receive pps */
-#define INTERRUPT_STATUS            0x00000010
+ * 0: not receive pps
+ * 1: receive pps
+ */
+#define INTERRUPT_STATUS 0x00000010
 /* bit4: pps income event, writing 1 to the bit clearing it
-          0: not receive pps
-          1: receive pps */
-#define INTERRUPT_EVENT             0x00000014
+ * 0: not receive pps
+ * 1: receive pps
+ */
+#define INTERRUPT_EVENT 0x00000014
 /* bit4: pps income event mask
-          0: mask
-          1: no mask */
-#define INTERRUPT_MASK              0x00000018
+ * 0: mask
+ * 1: no mask
+ */
+#define INTERRUPT_MASK 0x00000018
 /* bit4: trigger pps income event test
-          0: not occur
-          1: occur   */
-#define INTERRUPT_TEST              0x0000001C
+ * 0: not occur
+ * 1: occur
+ */
+#define INTERRUPT_TEST 0x0000001C
 
 /* adjust clock cycle, for 1588 and hw timer */
-#define PTP_CLOCK_CYCLE_INTEGER     0x00000030
-#define PTP_CLOCK_CYCLE_FRACTION    0x00000034
-
-/* 
-    BIT18: trig oe
-           1: trig out
-           0: trig in
-    bit17: hw timer update enable, used when timer run mode is update,increment or decrement
-           0: update disable
-           1: update enable
-    bit16: 1588 timer update enable, used when timer run mode is update,increment or decrement
-           0: update disable
-           1: update enable
-    bit15: 1588 and hw time timer enable
-           0: timer disable
-           1: timer enable
-    bit8:  pps input select
-           0: select internal pps
-           1: select external pps
-    bit5:4 1588 tod and hw timer run mode
-           0: normal
-           1: update
-           2: increment
-           3: decrement
-    bit2: trigger out enable
-           0:disable
-           1:enable
-    bit1: trigger in enable
-           0:disable
-           1:enable
-    bit0: 1588 tod timer slave/capture mode
-           0:capture mode, capture 1588 tod timer when input pps pulse
-           1:slave mode, the timer make the input pps as reference
-*/
-#define PTP_CONFIGURATION        0x00000040
-
-#define PPS_TRIGGER_IN_BIT       1
-#define PPS_TRIGGER_OUT_BIT      2
-#define PPS_RUN_MODE_BIT         4
-#define PPS_INPUT_SEL_BIT        8
-#define TIMER_EN_BIT                   15
-#define TIMER_1588_UPT_EN_BIT       16
-#define TIMER_HW_UPT_EN_BIT   17
-#define TRIG_OE                18
+#define PTP_CLOCK_CYCLE_INTEGER 0x00000030
+#define PTP_CLOCK_CYCLE_FRACTION 0x00000034
+
+/* BIT18: trig oe
+ *    1: trig out
+ *    0: trig in
+ * bit17: hw timer update enable, used when timer run mode is update,increment
+ * or decrement 0: update disable 1: update enable bit16: 1588 timer update
+ * enable, used when timer run mode is update,increment or decrement 0: update
+ * disable 1: update enable bit15: 1588 and hw time timer enable 0: timer
+ * disable 1: timer enable bit8:  pps input select 0: select internal pps 1:
+ * select external pps bit5:4 1588 tod and hw timer run mode 0: normal 1: update
+ *    2: increment
+ *    3: decrement
+ * bit2: trigger out enable
+ *    0:disable
+ *    1:enable
+ * bit1: trigger in enable
+ *    0:disable
+ *    1:enable
+ * bit0: 1588 tod timer slave/capture mode
+ *    0:capture mode, capture 1588 tod timer when input pps pulse
+ *    1:slave mode, the timer make the input pps as reference
+ */
+#define PTP_CONFIGURATION 0x00000040
+
+#define PPS_TRIGGER_IN_BIT 1
+#define PPS_TRIGGER_OUT_BIT 2
+#define PPS_RUN_MODE_BIT 4
+#define PPS_INPUT_SEL_BIT 8
+#define TIMER_EN_BIT 15
+#define TIMER_1588_UPT_EN_BIT 16
+#define TIMER_HW_UPT_EN_BIT 17
+#define TRIG_OE 18
 enum timer_run_mode {
-    NORMAL_MODE,
-    UPDATE_MODE,
-    INCRE_MODE,
-    DECRE_MODE,
+	NORMAL_MODE,
+	UPDATE_MODE,
+	INCRE_MODE,
+	DECRE_MODE,
 };
 /* bit1: adjust the 1588 tod and hw timer
-         0: not adjust
-         1: adjust the timer with add/sub/ or update
+ *    0: not adjust
+ *    1: adjust the timer with add/sub/ or update
+ */
+#define TIMER_CONTROL 0x00000044
+#define ADJ_TIMER_BIT 1
+
+/* bit4: tsn3 clock cycle update enable
+ * bit3: tsn2 clock cycle update enable
+ * bit2: tsn1 clock cycle update enable
+ * bit1: tsn0 clock cycle update enable
+ * bit0: 1588 clock cycle update enable
  */
-#define TIMER_CONTROL            0x00000044
-#define ADJ_TIMER_BIT            1
-
-/*
-   bit4: tsn3 clock cycle update enable
-   bit3: tsn2 clock cycle update enable
-   bit2: tsn1 clock cycle update enable
-   bit1: tsn0 clock cycle update enable
-   bit0: 1588 clock cycle update enable
-*/
-#define CLOCK_CYCLE_UPDATE       0x0000004C
+#define CLOCK_CYCLE_UPDATE 0x0000004C
 
 /* bit31~16: nanosecond         0~0xffff
-   bit15~0 : frac nanosecond    0~0xffff  */
-#define PPS_INCOME_DELAY         0x00000048
+ * bit15~0 : frac nanosecond    0~0xffff
+ */
+#define PPS_INCOME_DELAY 0x00000048
 /* bit0, 0:not latch, 1:latch the timer */
-#define TIMER_LATCH_EN           0x00000058
-/* bit5:0, select the latch timer 
-   bit0: 1588 timer
-   bit1: hw timer
-   bit2: tsn0 timer
-   bit3: tsn1 timer
-   bit4: tsn2 timer
-   bit5: tsn3 tiemr */
-#define TIMER_LACTH_SEL           0x0000005C
+#define TIMER_LATCH_EN 0x00000058
+/* bit5:0, select the latch timer
+ * bit0: 1588 timer
+ * bit1: hw timer
+ * bit2: tsn0 timer
+ * bit3: tsn1 timer
+ * bit4: tsn2 timer
+ * bit5: tsn3 timer
+ */
+#define TIMER_LACTH_SEL 0x0000005C
 
 enum latch_timer_type {
-    LATCH_1588_TIMER,
-    LATCH_HW_TIMER,
-    LATCH_TSN0_TIMER,
-    LATCH_TSN1_TIMER,
-    LATCH_TSN2_TIMER,
-    LATCH_TSN3_TIMER,
+	LATCH_1588_TIMER,
+	LATCH_HW_TIMER,
+	LATCH_TSN0_TIMER,
+	LATCH_TSN1_TIMER,
+	LATCH_TSN2_TIMER,
+	LATCH_TSN3_TIMER,
 };
 
-// trigger in 
-#define TRIGGER_IN_TOD_NANO_SECOND    0x00000060
-#define TRIGGER_IN_LOWER_TOD_SECOND   0x00000064
-#define TRIGGER_IN_HIGH_TOD_SECOND    0x00000068
-#define TRIGGER_IN_FRAC_NANO_SECOND   0x0000006C
+// trigger in
+#define TRIGGER_IN_TOD_NANO_SECOND 0x00000060
+#define TRIGGER_IN_LOWER_TOD_SECOND 0x00000064
+#define TRIGGER_IN_HIGH_TOD_SECOND 0x00000068
+#define TRIGGER_IN_FRAC_NANO_SECOND 0x0000006C
 
-#define TRIGGER_IN_HARDWARE_TIME_LOW  0x00000070
+#define TRIGGER_IN_HARDWARE_TIME_LOW 0x00000070
 #define TRIGGER_IN_HARDWARE_TIME_HIGH 0x00000074
 
 // trigger out
-#define TRIGGER_OUT_TOD_NANO_SECOND    0x00000080
-#define TRIGGER_OUT_LOWER_TOD_SECOND   0x00000084
-#define TRIGGER_OUT_HIGH_TOD_SECOND    0x00000088
+#define TRIGGER_OUT_TOD_NANO_SECOND 0x00000080
+#define TRIGGER_OUT_LOWER_TOD_SECOND 0x00000084
+#define TRIGGER_OUT_HIGH_TOD_SECOND 0x00000088
 // #define TRIGGER_OUT_FRAC_NANO_SECOND   0x0000008C  // none
 
-#define TRIGGER_OUT_HARDWARE_TIME_LOW  0x00000090
+#define TRIGGER_OUT_HARDWARE_TIME_LOW 0x00000090
 #define TRIGGER_OUT_HARDWARE_TIME_HIGH 0x00000094
 
-
 /* adjust 1588 timer */
-#define ADJUST_TOD_NANO_SECOND    0x000000A0
-#define ADJUST_LOWER_TOD_SECOND   0x000000A4
-#define ADJUST_HIGH_TOD_SECOND    0x000000A8
-#define ADJUST_FRAC_NANO_SECOND   0x000000AC
+#define ADJUST_TOD_NANO_SECOND 0x000000A0
+#define ADJUST_LOWER_TOD_SECOND 0x000000A4
+#define ADJUST_HIGH_TOD_SECOND 0x000000A8
+#define ADJUST_FRAC_NANO_SECOND 0x000000AC
 /* adjust hardware timer */
-#define ADJUST_HARDWARE_TIME_LOW  0x000000B0
+#define ADJUST_HARDWARE_TIME_LOW 0x000000B0
 #define ADJUST_HARDWARE_TIME_HIGH 0x000000B4
 
 /* 1588 timer latched time */
-#define LATCH_TOD_NANO_SECOND     0x000000C0
-#define LATCH_LOWER_TOD_SECOND    0x000000C4
-#define LATCH_HIGH_TOD_SECOND     0x000000C8
-#define LATCH_FRAC_NANO_SECOND    0x000000CC
+#define LATCH_TOD_NANO_SECOND 0x000000C0
+#define LATCH_LOWER_TOD_SECOND 0x000000C4
+#define LATCH_HIGH_TOD_SECOND 0x000000C8
+#define LATCH_FRAC_NANO_SECOND 0x000000CC
 /* hw timer latched time */
-#define LATCH_HARDWARE_TIME_LOW   0x000000D0
-#define LATCH_HARDWARE_TIME_HIGH  0x000000D4
+#define LATCH_HARDWARE_TIME_LOW 0x000000D0
+#define LATCH_HARDWARE_TIME_HIGH 0x000000D4
 
 /* pps capture tod time*/
-#define PPS_LATCH_TOD_NANO_SECOND  0x00000120
+#define PPS_LATCH_TOD_NANO_SECOND 0x00000120
 #define PPS_LATCH_LOWER_TOD_SECOND 0x00000124
-#define PPS_LATCH_HIGH_TOD_SECOND  0x00000128
+#define PPS_LATCH_HIGH_TOD_SECOND 0x00000128
 #define PPS_LATCH_FRAC_NANO_SECOND 0x0000012C
 
-/*  bit19~16 tsn pps enable
-           bit19: tsn3
-           bit18: tsn2
-           bit17: tsn1
-           bit16: tsn0
-    bit15~12 tsn timer enable
-           bit15: tsn3
-           bit14: tsn2
-           bit13: tsn1
-           bit12: tsn0
-    bit11~10 tsn0 timer run mode
-    bit9~8   tsn1 timer run mode, 
-    bit7~6   tsn2 timer run mode, 
-    bit5~4   tsn3 timer run mode, 
-            0: normal
-            1: update
-            2: increment
-            3: decrement
-    bit3~0: tsn timer slave/capture mode, 0 is capture mode, 1 is slave mode
-            bit3: tsn3
-            bit2: tsn2
-            bit1: tsn1
-            bit0: tsn0
-*/
-#define TSN_TIME_CONFIGURATION        0x00000140
-/*
-    bit3: adjust tsn3 timer
-    bit2: adjust tsn2 timer
-    bit1: adjust tsn1 timer
-    bit0: adjust tsn0 timer
-*/
-#define TSN_TIMER_CONTROL             0x00000144
-#define TSN0_ADJ_EN_BIT               0
-#define TSN1_ADJ_EN_BIT               1
-#define TSN2_ADJ_EN_BIT               2
-#define TSN3_ADJ_EN_BIT               3
+/* bit19~16 tsn pps enable
+ * bit19: tsn3
+ * bit18: tsn2
+ * bit17: tsn1
+ * bit16: tsn0
+ * bit15~12 tsn timer enable
+ * bit15: tsn3
+ * bit14: tsn2
+ * bit13: tsn1
+ * bit12: tsn0
+ * bit11~10 tsn0 timer run mode
+ * bit9~8   tsn1 timer run mode,
+ * bit7~6   tsn2 timer run mode,
+ * bit5~4   tsn3 timer run mode,
+ *    0: normal
+ *    1: update
+ *    2: increment
+ *    3: decrement
+ * bit3~0: tsn timer slave/capture mode, 0 is capture mode, 1 is slave mode
+ * bit3: tsn3
+ * bit2: tsn2
+ * bit1: tsn1
+ * bit0: tsn0
+ */
+#define TSN_TIME_CONFIGURATION 0x00000140
+/* bit3: adjust tsn3 timer
+ * bit2: adjust tsn2 timer
+ * bit1: adjust tsn1 timer
+ * bit0: adjust tsn0 timer
+ */
+#define TSN_TIMER_CONTROL 0x00000144
+#define TSN0_ADJ_EN_BIT 0
+#define TSN1_ADJ_EN_BIT 1
+#define TSN2_ADJ_EN_BIT 2
+#define TSN3_ADJ_EN_BIT 3
 
 /* adjust clock cycle, for four tsn timer */
-#define TSN0_CLOCK_CYCLE_INTEGER      0x00000148
-#define TSN0_CLOCK_CYCLE_FRACTION     0x0000014C
-#define TSN1_CLOCK_CYCLE_INTEGER      0x00000150
-#define TSN1_CLOCK_CYCLE_FRACTION     0x00000154
-#define TSN2_CLOCK_CYCLE_INTEGER      0x00000158
-#define TSN2_CLOCK_CYCLE_FRACTION     0x0000015C
-#define TSN3_CLOCK_CYCLE_INTEGER      0x00000160
-#define TSN3_CLOCK_CYCLE_FRACTION     0x00000164
-
-#define TSN_CLOCK_CYCLE_INTEGER(tsn_no)     TSN##tsn_no##_CLOCK_CYCLE_INTEGER
-#define TSN_CLOCK_CYCLE_FRACTION(tsn_no)    TSN##tsn_no##_CLOCK_CYCLE_FRACTION
+#define TSN0_CLOCK_CYCLE_INTEGER 0x00000148
+#define TSN0_CLOCK_CYCLE_FRACTION 0x0000014C
+#define TSN1_CLOCK_CYCLE_INTEGER 0x00000150
+#define TSN1_CLOCK_CYCLE_FRACTION 0x00000154
+#define TSN2_CLOCK_CYCLE_INTEGER 0x00000158
+#define TSN2_CLOCK_CYCLE_FRACTION 0x0000015C
+#define TSN3_CLOCK_CYCLE_INTEGER 0x00000160
+#define TSN3_CLOCK_CYCLE_FRACTION 0x00000164
+
+#define TSN_CLOCK_CYCLE_INTEGER(tsn_no) TSN##tsn_no##_CLOCK_CYCLE_INTEGER
+#define TSN_CLOCK_CYCLE_FRACTION(tsn_no) TSN##tsn_no##_CLOCK_CYCLE_FRACTION
 
 /* adjust tsn timer */
-#define TSN0_ADJUST_TOD_NANO_SECOND   0x00000180
-#define TSN0_ADJUST_LOWER_TOD_SECOND  0x00000184
-#define TSN0_ADJUST_HIGH_TOD_SECOND   0x00000188
-#define TSN0_ADJUST_FRAC_NANO_SECOND  0x0000018C
-
-#define TSN1_ADJUST_TOD_NANO_SECOND   0x00000190
-#define TSN1_ADJUST_LOWER_TOD_SECOND  0x00000194
-#define TSN1_ADJUST_HIGH_TOD_SECOND   0x00000198
-#define TSN1_ADJUST_FRAC_NANO_SECOND  0x0000019C
-
-#define TSN2_ADJUST_TOD_NANO_SECOND   0x000001A0
-#define TSN2_ADJUST_LOWER_TOD_SECOND  0x000001A4
-#define TSN2_ADJUST_HIGH_TOD_SECOND   0x000001A8
-#define TSN2_ADJUST_FRAC_NANO_SECOND  0x000001AC
-
-#define TSN3_ADJUST_TOD_NANO_SECOND   0x000001B0
-#define TSN3_ADJUST_LOWER_TOD_SECOND  0x000001B4
-#define TSN3_ADJUST_HIGH_TOD_SECOND   0x000001B8
-#define TSN3_ADJUST_FRAC_NANO_SECOND  0x000001BC
-
-#define TSN_ADJUST_NANO_SEC(tsn_no)       TSN##tsn_no##_ADJUST_TOD_NANO_SECOND
-#define TSN_ADJUST_LOW_SECOND(tsn_no)     TSN##tsn_no##_ADJUST_LOWER_TOD_SECOND
-#define TSN_ADJUST_HIGH_SECOND(tsn_no)    TSN##tsn_no##_ADJUST_HIGH_TOD_SECOND
-#define TSN_ADJUST_FRAC_NANO_SEC(tsn_no)  TSN##tsn_no##_ADJUST_FRAC_NANO_SECOND
+#define TSN0_ADJUST_TOD_NANO_SECOND 0x00000180
+#define TSN0_ADJUST_LOWER_TOD_SECOND 0x00000184
+#define TSN0_ADJUST_HIGH_TOD_SECOND 0x00000188
+#define TSN0_ADJUST_FRAC_NANO_SECOND 0x0000018C
+
+#define TSN1_ADJUST_TOD_NANO_SECOND 0x00000190
+#define TSN1_ADJUST_LOWER_TOD_SECOND 0x00000194
+#define TSN1_ADJUST_HIGH_TOD_SECOND 0x00000198
+#define TSN1_ADJUST_FRAC_NANO_SECOND 0x0000019C
+
+#define TSN2_ADJUST_TOD_NANO_SECOND 0x000001A0
+#define TSN2_ADJUST_LOWER_TOD_SECOND 0x000001A4
+#define TSN2_ADJUST_HIGH_TOD_SECOND 0x000001A8
+#define TSN2_ADJUST_FRAC_NANO_SECOND 0x000001AC
+
+#define TSN3_ADJUST_TOD_NANO_SECOND 0x000001B0
+#define TSN3_ADJUST_LOWER_TOD_SECOND 0x000001B4
+#define TSN3_ADJUST_HIGH_TOD_SECOND 0x000001B8
+#define TSN3_ADJUST_FRAC_NANO_SECOND 0x000001BC
+
+#define TSN_ADJUST_NANO_SEC(tsn_no) TSN##tsn_no##_ADJUST_TOD_NANO_SECOND
+#define TSN_ADJUST_LOW_SECOND(tsn_no) TSN##tsn_no##_ADJUST_LOWER_TOD_SECOND
+#define TSN_ADJUST_HIGH_SECOND(tsn_no) TSN##tsn_no##_ADJUST_HIGH_TOD_SECOND
+#define TSN_ADJUST_FRAC_NANO_SEC(tsn_no) TSN##tsn_no##_ADJUST_FRAC_NANO_SECOND
 
 /* tsn0 timer latched time */
-#define TSN0_LATCH_TOD_NANO_SECOND    0x000001C0
-#define TSN0_LATCH_LOWER_TOD_SECOND   0x000001C4
-#define TSN0_LATCH_HIGH_TOD_SECOND    0x000001C8
-#define TSN0_LATCH_FRAC_NANO_SECOND   0x000001CC
+#define TSN0_LATCH_TOD_NANO_SECOND 0x000001C0
+#define TSN0_LATCH_LOWER_TOD_SECOND 0x000001C4
+#define TSN0_LATCH_HIGH_TOD_SECOND 0x000001C8
+#define TSN0_LATCH_FRAC_NANO_SECOND 0x000001CC
 /* tsn1 timer latched time */
-#define TSN1_LATCH_TOD_NANO_SECOND    0x000001D0
-#define TSN1_LATCH_LOWER_TOD_SECOND   0x000001D4
-#define TSN1_LATCH_HIGH_TOD_SECOND    0x000001D8
-#define TSN1_LATCH_FRAC_NANO_SECOND   0x000001DC
+#define TSN1_LATCH_TOD_NANO_SECOND 0x000001D0
+#define TSN1_LATCH_LOWER_TOD_SECOND 0x000001D4
+#define TSN1_LATCH_HIGH_TOD_SECOND 0x000001D8
+#define TSN1_LATCH_FRAC_NANO_SECOND 0x000001DC
 /* tsn2 timer latched time */
-#define TSN2_LATCH_TOD_NANO_SECOND    0x000001E0
-#define TSN2_LATCH_LOWER_TOD_SECOND   0x000001E4
-#define TSN2_LATCH_HIGH_TOD_SECOND    0x000001E8
-#define TSN2_LATCH_FRAC_NANO_SECOND   0x000001EC
+#define TSN2_LATCH_TOD_NANO_SECOND 0x000001E0
+#define TSN2_LATCH_LOWER_TOD_SECOND 0x000001E4
+#define TSN2_LATCH_HIGH_TOD_SECOND 0x000001E8
+#define TSN2_LATCH_FRAC_NANO_SECOND 0x000001EC
 /* tsn3 timer latched time */
-#define TSN3_LATCH_TOD_NANO_SECOND    0x000001F0
-#define TSN3_LATCH_LOWER_TOD_SECOND   0x000001F4
-#define TSN3_LATCH_HIGH_TOD_SECOND    0x000001F8
-#define TSN3_LATCH_FRAC_NANO_SECOND   0x000001FC
+#define TSN3_LATCH_TOD_NANO_SECOND 0x000001F0
+#define TSN3_LATCH_LOWER_TOD_SECOND 0x000001F4
+#define TSN3_LATCH_HIGH_TOD_SECOND 0x000001F8
+#define TSN3_LATCH_FRAC_NANO_SECOND 0x000001FC
 
-#define TSN_LATCH_NANO_SEC(tsn_no)        TSN##tsn_no##_LATCH_TOD_NANO_SECOND
-#define TSN_LATCH_LOW_SECOND(tsn_no)      TSN##tsn_no##_LATCH_LOWER_TOD_SECOND
-#define TSN_LATCH_HIGH_SECOND(tsn_no)     TSN##tsn_no##_LATCH_HIGH_TOD_SECOND
-#define TSN_LATCH_FRAC_NANO_SEC(tsn_no)   TSN##tsn_no##_LATCH_FRAC_NANO_SECOND
+#define TSN_LATCH_NANO_SEC(tsn_no) TSN##tsn_no##_LATCH_TOD_NANO_SECOND
+#define TSN_LATCH_LOW_SECOND(tsn_no) TSN##tsn_no##_LATCH_LOWER_TOD_SECOND
+#define TSN_LATCH_HIGH_SECOND(tsn_no) TSN##tsn_no##_LATCH_HIGH_TOD_SECOND
+#define TSN_LATCH_FRAC_NANO_SEC(tsn_no) TSN##tsn_no##_LATCH_FRAC_NANO_SECOND
 
 /* pps capture tsn0 time*/
-#define PPS_LATCH_TSN0_NANO_SECOND  0x00000200
+#define PPS_LATCH_TSN0_NANO_SECOND 0x00000200
 #define PPS_LATCH_TSN0_LOWER_SECOND 0x00000204
-#define PPS_LATCH_TSN0_HIGH_SECOND  0x00000208
-#define PPS_LATCH_TSN0_FRAC_NANO    0x0000020C
+#define PPS_LATCH_TSN0_HIGH_SECOND 0x00000208
+#define PPS_LATCH_TSN0_FRAC_NANO 0x0000020C
 /* pps capture tsn1 time*/
-#define PPS_LATCH_TSN1_NANO_SECOND  0x00000210
+#define PPS_LATCH_TSN1_NANO_SECOND 0x00000210
 #define PPS_LATCH_TSN1_LOWER_SECOND 0x00000214
-#define PPS_LATCH_TSN1_HIGH_SECOND  0x00000218
-#define PPS_LATCH_TSN1_FRAC_NANO    0x0000021C
+#define PPS_LATCH_TSN1_HIGH_SECOND 0x00000218
+#define PPS_LATCH_TSN1_FRAC_NANO 0x0000021C
 /* pps capture tsn2 time*/
-#define PPS_LATCH_TSN2_NANO_SECOND  0x00000220
+#define PPS_LATCH_TSN2_NANO_SECOND 0x00000220
 #define PPS_LATCH_TSN2_LOWER_SECOND 0x00000224
-#define PPS_LATCH_TSN2_HIGH_SECOND  0x00000228
-#define PPS_LATCH_TSN2_FRAC_NANO    0x0000022C
+#define PPS_LATCH_TSN2_HIGH_SECOND 0x00000228
+#define PPS_LATCH_TSN2_FRAC_NANO 0x0000022C
 /* pps capture tsn3 time*/
-#define PPS_LATCH_TSN3_NANO_SECOND  0x00000230
+#define PPS_LATCH_TSN3_NANO_SECOND 0x00000230
 #define PPS_LATCH_TSN3_LOWER_SECOND 0x00000234
-#define PPS_LATCH_TSN3_HIGH_SECOND  0x00000238
-#define PPS_LATCH_TSN3_FRAC_NANO    0x0000023C
+#define PPS_LATCH_TSN3_HIGH_SECOND 0x00000238
+#define PPS_LATCH_TSN3_FRAC_NANO 0x0000023C
 
-#define PPS_LATCH_TSN_NANO_SEC(tsn_no)        PPS_LATCH_TSN##tsn_no##_NANO_SECOND
-#define PPS_LATCH_TSN_LOW_SECOND(tsn_no)      PPS_LATCH_TSN##tsn_no##_LOWER_SECOND
-#define PPS_LATCH_TSN_HIGH_SECOND(tsn_no)     PPS_LATCH_TSN##tsn_no##_HIGH_SECOND
-#define PPS_LATCH_TSN_FRAC_NANO_SEC(tsn_no)   PPS_LATCH_TSN##tsn_no##_FRAC_NANO
+#define PPS_LATCH_TSN_NANO_SEC(tsn_no) PPS_LATCH_TSN##tsn_no##_NANO_SECOND
+#define PPS_LATCH_TSN_LOW_SECOND(tsn_no) PPS_LATCH_TSN##tsn_no##_LOWER_SECOND
+#define PPS_LATCH_TSN_HIGH_SECOND(tsn_no) PPS_LATCH_TSN##tsn_no##_HIGH_SECOND
+#define PPS_LATCH_TSN_FRAC_NANO_SEC(tsn_no) PPS_LATCH_TSN##tsn_no##_FRAC_NANO
 
 /**************************** ptpm end **************************/
 
-
 /**************************** ptp_top start **************************/
 
-/*  bit3: local pp1s status
-        0: not generate local pp1s
-        1: generate local pp1s
-    bit2: trigger local pp1s event test
-        0: not occur
-        1: occur
-    bit1: writing 1 to the bit clearing local pp1s status
-        0: not clear
-        1: clear
-    bit0: local pp1s event enable
-        0: no enable
-        1: enable */
-#define LOCAL_PPS_INTERRUPT        0x00000000
+/* bit3: local pp1s status
+ *    0: not generate local pp1s
+ *    1: generate local pp1s
+ * bit2: trigger local pp1s event test
+ *    0: not occur
+ *    1: occur
+ * bit1: writing 1 to the bit clearing local pp1s status
+ *    0: not clear
+ *    1: clear
+ * bit0: local pp1s event enable
+ *    0: no enable
+ *    1: enable
+ */
+#define LOCAL_PPS_INTERRUPT 0x00000000
 // bit0:  0 ref0   1 ref1
-#define PP1S_EXTERNAL_SEL          0x00000004
-/*  bit1~0: select pp1s out:
-        00: pp1s ref0
-        01: pp1s ref1
-        10: local pp1s
-        11: 1588 pp1s  */
-#define PP1S_OUT_SEL               0x00000008
-/*  bit2~0: select test pp1s:
-        000: pp1s ref0
-        001: pp1s ref1
-        010: local pp1s
-        011: 1588 pp1s
-        100: tsn0 pp1s
-        101: tsn1 pp1s
-        110: tsn2 pp1s
-        111: tsn3 pp1s  */
-#define TEST_PP1S_SEL              0x0000000C
-
-#define LOCAL_PP1S_EN              0x00000010 // use local_pp1s need enable this reg
-/*  bit2~1: select local pp1s adjust reference
-             00: pp1s ref0
-             01: pp1s ref1
-             10,11: 1588 pp1s
-    bit0:   adjust local pp1s phase once */
-#define LOCAL_PP1S_ADJUST          0x00000014
+#define PP1S_EXTERNAL_SEL 0x00000004
+/* bit1~0: select pp1s out:
+ *    00: pp1s ref0
+ *    01: pp1s ref1
+ *    10: local pp1s
+ *    11: 1588 pp1s
+ */
+#define PP1S_OUT_SEL 0x00000008
+/* bit2~0: select test pp1s:
+ *    000: pp1s ref0
+ *    001: pp1s ref1
+ *    010: local pp1s
+ *    011: 1588 pp1s
+ *    100: tsn0 pp1s
+ *    101: tsn1 pp1s
+ *    110: tsn2 pp1s
+ *    111: tsn3 pp1s
+ */
+#define TEST_PP1S_SEL 0x0000000C
+
+#define LOCAL_PP1S_EN 0x00000010 // use local_pp1s need enable this reg
+/* bit2~1: select local pp1s adjust reference
+ * 00: pp1s ref0
+ * 01: pp1s ref1
+ * 10,11: 1588 pp1s
+ * bit0:   adjust local pp1s phase once
+ */
+#define LOCAL_PP1S_ADJUST 0x00000014
 /* bit29~0: adjust local pp1s value, must below 10e9, 1bit is 1 nanosecond */
-#define LOCAL_PP1S_ADJUST_VALUE    0x00000018
-
-/*  bit5~3: Pd_U1_Sel1
-        000: pp1s ref0
-        001: pp1s ref1
-        010: local pp1s
-        011: 1588 pp1s
-        100: tsn0 pp1s
-        101: tsn1 pp1s
-        110: tsn2 pp1s
-        111: tsn3 pp1s
-    bit2~0: Pd_U1_Sel0
-        000: pp1s ref0
-        001: pp1s ref1
-        010: local pp1s
-        011: 1588 pp1s
-        100: tsn0 pp1s
-        101: tsn1 pp1s
-        110: tsn2 pp1s
-        111: tsn3 pp1s    */
-#define PD_U1_SEL                  0x00000040
+#define LOCAL_PP1S_ADJUST_VALUE 0x00000018
+
+/* bit5~3: Pd_U1_Sel1
+ * 000: pp1s ref0
+ * 001: pp1s ref1
+ * 010: local pp1s
+ * 011: 1588 pp1s
+ * 100: tsn0 pp1s
+ * 101: tsn1 pp1s
+ * 110: tsn2 pp1s
+ * 111: tsn3 pp1s
+ * bit2~0: Pd_U1_Sel0
+ * 000: pp1s ref0
+ * 001: pp1s ref1
+ * 010: local pp1s
+ * 011: 1588 pp1s
+ * 100: tsn0 pp1s
+ * 101: tsn1 pp1s
+ * 110: tsn2 pp1s
+ * 111: tsn3 pp1s
+ */
+#define PD_U1_SEL 0x00000040
 // bit29~0: phase detector module 1 select0 input pp1s shift value.
-#define PD_U1_PD0_SHIFT            0x00000044
-// bit29~0: phase detector module 1 select1 input pp1s shift value. 
-#define PD_U1_PD1_SHIFT            0x00000048
-
-/*  bit30: Pd_U1_Result_sign
-        1: positive
-        0: negative
-    bit29: Pd_U1_Overflow: the interval between two pp1s pluse is greater than 0x1FFF_FFFF, 1 is overflow
-    bit28~0: phase detector module 1 resule value, must below 5*10e8, 1 bit is 1 nanosecond. */
-#define PD_U1_RESULT               0x0000004C
-
-/*  bit5~3: Pd_U2_Sel1
-        000: pp1s ref0
-        001: pp1s ref1
-        010: local pp1s
-        011: 1588 pp1s
-        100: tsn0 pp1s
-        101: tsn1 pp1s
-        110: tsn2 pp1s
-        111: tsn3 pp1s 
-    bit2~0: Pd_U2_Sel0
-        000: pp1s ref0
-        001: pp1s ref1
-        010: local pp1s
-        011: 1588 pp1s
-        100: tsn0 pp1s
-        101: tsn1 pp1s
-        110: tsn2 pp1s
-        111: tsn3 pp1s    */
-#define PD_U2_SEL                  0x00000050
+#define PD_U1_PD0_SHIFT 0x00000044
+// bit29~0: phase detector module 1 select1 input pp1s shift value.
+#define PD_U1_PD1_SHIFT 0x00000048
+
+/* bit30: Pd_U1_Result_sign
+ *    1: positive
+ *    0: negative
+ * bit29: Pd_U1_Overflow: the interval between two pp1s pluse is greater than
+ * 0x1FFF_FFFF, 1 is overflow bit28~0: phase detector module 1 resule value,
+ * must below 5*10e8, 1 bit is 1 nanosecond.
+ */
+#define PD_U1_RESULT 0x0000004C
+
+/* bit5~3: Pd_U2_Sel1
+ *    000: pp1s ref0
+ *    001: pp1s ref1
+ *    010: local pp1s
+ *    011: 1588 pp1s
+ *    100: tsn0 pp1s
+ *    101: tsn1 pp1s
+ *    110: tsn2 pp1s
+ *    111: tsn3 pp1s
+ * bit2~0: Pd_U2_Sel0
+ *    000: pp1s ref0
+ *    001: pp1s ref1
+ *    010: local pp1s
+ *    011: 1588 pp1s
+ *    100: tsn0 pp1s
+ *    101: tsn1 pp1s
+ *    110: tsn2 pp1s
+ *    111: tsn3 pp1s
+ */
+#define PD_U2_SEL 0x00000050
 // bit29~0: phase detector module 2 select0 input pp1s shift value.
-#define PD_U2_PD0_SHIFT            0x00000054
+#define PD_U2_PD0_SHIFT 0x00000054
 // bit29~0: phase detector module 2 select1 input pp1s shift value.
-#define PD_U2_PD1_SHIFT            0x00000058
-/*  bit30: Pd_U2_Result_sign
-        1: positive
-        0: negative
-    bit29: Pd_U2_Overflow: the interval between two pp1s pluse is greater than 0x1FFF_FFFF, 1 is overflow
-    bit28~0: phase detector module 2 resule value, must below 5*10e8, 1 bit is 1 nanosecond. */
-#define PD_U2_RESULT               0x0000005C
-
-#define TSN_GROUP_NANO_SEC_DELAY0            0x00000080
-#define TSN_GROUP_FRAC_NANO_SEC_DELAY0       0x00000084
-#define TSN_GROUP_NANO_SEC_DELAY1            0x00000088
-#define TSN_GROUP_FRAC_NANO_SEC_DELAY1       0x0000008C
-#define TSN_GROUP_NANO_SEC_DELAY2            0x00000090
-#define TSN_GROUP_FRAC_NANO_SEC_DELAY2       0x00000094
-#define TSN_GROUP_NANO_SEC_DELAY3            0x00000098
-#define TSN_GROUP_FRAC_NANO_SEC_DELAY3       0x0000009C
-#define PTP1588_RDMA_NANO_SEC_DELAY          0x000000A0
-#define PTP1588_RDMA_FRAC_NANO_SEC_DELAY     0x000000A4
-#define PTP1588_NP_NANO_SEC_DELAY            0x000000A8
-#define PTP1588_NP_FRAC_NANO_SEC_DELAY       0x000000AC
-#define PTP1588_NVME_NANO_SEC_DELAY1         0x000000C0
-#define PTP1588_NVME_FRAC_NANO_SEC_DELAY1    0x000000C4
-#define PTP1588_NVME_NANO_SEC_DELAY2         0x000000C8
-#define PTP1588_NVME_FRAC_NANO_SEC_DELAY2    0x000000CC
-
+#define PD_U2_PD1_SHIFT 0x00000058
+/* bit30: Pd_U2_Result_sign
+ * 1: positive
+ * 0: negative
+ * bit29: Pd_U2_Overflow: the interval between two pp1s pluse is greater than
+ * 0x1FFF_FFFF, 1 is overflow bit28~0: phase detector module 2 resule value,
+ * must below 5*10e8, 1 bit is 1 nanosecond.
+ */
+#define PD_U2_RESULT 0x0000005C
+
+#define TSN_GROUP_NANO_SEC_DELAY0 0x00000080
+#define TSN_GROUP_FRAC_NANO_SEC_DELAY0 0x00000084
+#define TSN_GROUP_NANO_SEC_DELAY1 0x00000088
+#define TSN_GROUP_FRAC_NANO_SEC_DELAY1 0x0000008C
+#define TSN_GROUP_NANO_SEC_DELAY2 0x00000090
+#define TSN_GROUP_FRAC_NANO_SEC_DELAY2 0x00000094
+#define TSN_GROUP_NANO_SEC_DELAY3 0x00000098
+#define TSN_GROUP_FRAC_NANO_SEC_DELAY3 0x0000009C
+#define PTP1588_RDMA_NANO_SEC_DELAY 0x000000A0
+#define PTP1588_RDMA_FRAC_NANO_SEC_DELAY 0x000000A4
+#define PTP1588_NP_NANO_SEC_DELAY 0x000000A8
+#define PTP1588_NP_FRAC_NANO_SEC_DELAY 0x000000AC
+#define PTP1588_NVME_NANO_SEC_DELAY1 0x000000C0
+#define PTP1588_NVME_FRAC_NANO_SEC_DELAY1 0x000000C4
+#define PTP1588_NVME_NANO_SEC_DELAY2 0x000000C8
+#define PTP1588_NVME_FRAC_NANO_SEC_DELAY2 0x000000CC
 
 /**************************** ptp_top end **************************/
 
-
 /**************************** ptps start **************************/
 /* bit0: enable writing timestamps to the FIFO
-         0: disable
-         1: enable */
-#define PTPS_CONFIGURATION           0x00000020
+ *    0: disable
+ *    1: enable
+ */
+#define PTPS_CONFIGURATION 0x00000020
 
 /* bit0: PTP1588 FIFO read command
-         0: not read
-         1: read */
-#define PTPS_TIMER_CONTROL                0x00000024
+ *    0: not read
+ *    1: read
+ */
+#define PTPS_TIMER_CONTROL 0x00000024
 
-/* bit15~0: integral nanosecond of sync Hardware Time compensaion, 1 bit is 1 nanosecond */
-#define SYNC_HW_TIME_COMPENSATION    0x00000038
+/* bit15~0: integral nanosecond of sync Hardware Time compensaion, 1 bit is 1
+ * nanosecond
+ */
+#define SYNC_HW_TIME_COMPENSATION 0x00000038
+
+/* 对于加密报文，先读 PTP event timestamps
+ * count，然后读时间戳和匹配信息，读时间戳和匹配信息之前，都要先配置TIMER_CONTROL.
+ * 匹配信息是在PTP1588_EVENT_MESSAGE_TS_LOW里，具体对应关系: BIT[23:0]:
+ * messageType, sourcePortIdentity[3:0],sequenceId[15:0]
+ */
 
-/* 对于加密报文，先读 PTP event timestamps count，然后读时间戳和匹配信息，读时间戳和匹配信息之前，都要先配置TIMER_CONTROL.
-   匹配信息是在PTP1588_EVENT_MESSAGE_TS_LOW里，具体对应关系: BIT[23:0]: messageType, sourcePortIdentity[3:0],sequenceId[15:0] */
 /* ptp1588 event message timestamp[31:0] */
-#define PTP1588_EVENT_MESSAGE_TS_LOW    0x00000084
+#define PTP1588_EVENT_MESSAGE_TS_LOW 0x00000084
 /* ptp1588 event message timestamp[63:32] */
-#define PTP1588_EVENT_MESSAGE_TS_HIGH   0x00000088
+#define PTP1588_EVENT_MESSAGE_TS_HIGH 0x00000088
 
 /* bit9: FIFO full
-   bit8: FIFO empty
-   bit7~0: PTP event timestamps count */
-#define PTP1588_EVENT_MESSAGE_FIFO_STATUS   0x0000008C
-
-struct event_ts_info
-{
-   u32 ts_low;
-   u32 ts_high;
-   unsigned char messageType;
-   unsigned char srcPortId;
-   short sequenceId;
+ * bit8: FIFO empty
+ * bit7~0: PTP event timestamps count
+ */
+#define PTP1588_EVENT_MESSAGE_FIFO_STATUS 0x0000008C
+
+struct event_ts_info {
+	u32 ts_low;
+	u32 ts_high;
+	unsigned char messageType;
+	unsigned char srcPortId;
+	short sequenceId;
 };
 
-#define EVENT_MESSAGE_MAX_NUM         32
+#define EVENT_MESSAGE_MAX_NUM 32
 
 /**************************** ptps end **************************/
 
-
-
-
 #endif /* _ZX_REGS_H */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_sf.c b/src/net/drivers/net/ethernet/dinghai/en_sf.c
index 3ef97eaaf8a1eeae3263b0bb673fbc5d45c514b2..7f00f1832bd832fb4c8448a5d6d28aaf15707de3 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_sf.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_sf.c
@@ -1,781 +1,776 @@
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/auxiliary_bus.h>
-#ifdef HAVE_DEV_PRINTK_OPS
-#include <linux/dev_printk.h>
-#endif
-#include <linux/dinghai/devlink.h>
-#include <linux/dinghai/helper.h>
-#include <linux/dinghai/en_aux.h>
-#include <linux/dinghai/dh_cmd.h>
-#include "en_aux.h"
-#include "en_sf.h"
-#include "./en_sf/eq.h"
-
-extern struct devlink_ops dh_sf_devlink_ops;
-extern struct dh_core_devlink_ops dh_sf_core_devlink_ops;
-
-int32_t zxdh_sf_get_vq_lock(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-    int32_t ret = 0;
-
-    ret= en_sf_dev->sf_ops->en_sf_get_vq_lock(dh_dev->parent);
-    if (ret != 0)
-    {
-        LOG_ERR("en_sf_get_vq_lock failed: %d\n", ret);
-        return ret;
-    }
-
-    return 0;
-}
-
-int32_t zxdh_sf_release_vq_lock(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-    int32_t ret = 0;
-
-    ret= en_sf_dev->sf_ops->en_sf_release_vq_lock(dh_dev->parent);
-    if (ret != 0)
-    {
-        LOG_ERR("en_sf_release_vq_lock failed: %d\n", ret);
-        return ret;
-    }
-
-    return 0;
-}
-
-int32_t zxdh_sf_get_phy_vq(struct dh_core_dev *dh_dev, uint16_t index)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-    int32_t phy_index = 0;
-
-    phy_index= en_sf_dev->sf_ops->en_sf_get_phy_vq(dh_dev->parent, index);
-    if (phy_index < 0)
-    {
-        LOG_ERR("en_sf_get_phy_vq failed: %d\n", phy_index);
-    }
-
-    return phy_index;
-}
-
-int32_t zxdh_sf_release_phy_vq(struct dh_core_dev *dh_dev, uint32_t *phy_index, uint16_t total_qnum)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-    int32_t ret = 0;
-
-    ret= en_sf_dev->sf_ops->en_sf_release_phy_vq(dh_dev->parent, phy_index, total_qnum);
-    if (ret != 0)
-    {
-        LOG_ERR("en_sf_relaese_phy_vq failed: %d\n", ret);
-        return ret;
-    }
-
-    return 0;
-}
-
-bool zxdh_en_sf_is_bond(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_is_bond(dh_dev->parent);
-}
-
-bool zxdh_en_sf_is_upf(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_is_upf(dh_dev->parent);
-}
-
-int32_t zxdh_en_sf_get_phy_vq(struct dh_core_dev *dh_dev, uint16_t index)
-{
-    int32_t ret = 0;
-    int32_t phy_index = 0;
-
-    ret = zxdh_sf_get_vq_lock(dh_dev);
-    if (ret < 0)
-    {
-        return ret;
-    }
-
-    phy_index = zxdh_sf_get_phy_vq(dh_dev, index);
-
-    ret = zxdh_sf_release_vq_lock(dh_dev);
-    if (ret < 0)
-    {
-        return ret;
-    }
-
-    return phy_index;
-}
-
-int32_t zxdh_en_sf_release_phy_vq(struct dh_core_dev *dh_dev, uint32_t *phy_index, uint16_t total_qnum)
-{
-    int32_t ret = 0;
-
-    ret = zxdh_sf_get_vq_lock(dh_dev);
-    if (ret < 0)
-    {
-        return ret;
-    }
-
-    zxdh_sf_release_phy_vq(dh_dev, phy_index, total_qnum);
-
-    zxdh_sf_release_vq_lock(dh_dev);
-
-    return ret;
-}
-
-void zxdh_en_sf_set_status(struct dh_core_dev *dh_dev, uint8_t status)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_set_status(dh_dev->parent, status);
-
-    return;
-}
-
-uint8_t zxdh_en_sf_get_status(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-    uint8_t status = 0;
-
-    status = en_sf_dev->sf_ops->en_sf_get_status(dh_dev->parent);
-
-    return status;
-}
-
-void zxdh_en_sf_set_vf_mac(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_set_vf_mac(dh_dev->parent, mac, vf_id);
-
-    return;
-}
-
-void zxdh_en_sf_get_vf_mac(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_get_vf_mac(dh_dev->parent, mac, vf_id);
-
-    return ;
-}
-
-void zxdh_en_sf_set_mac(struct dh_core_dev *dh_dev, uint8_t *mac)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_set_mac(dh_dev->parent, mac);
-
-    return;
-}
-
-void zxdh_en_sf_get_mac(struct dh_core_dev *dh_dev, uint8_t *mac)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_get_mac(dh_dev->parent, mac);
-
-    return ;
-}
-
-uint64_t zxdh_en_sf_get_features(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-    uint64_t device_feature = 0;
-
-    device_feature = en_sf_dev->sf_ops->en_sf_get_features(dh_dev->parent);
-
-    return device_feature;
-}
-
-void zxdh_en_sf_set_features(struct dh_core_dev *dh_dev, uint64_t features)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_set_features(dh_dev->parent, features);
-
-    return;
-}
-
-uint16_t zxdh_en_sf_get_queue_num(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-    uint16_t qnum = 0;
-
-    qnum = en_sf_dev->sf_ops->en_sf_get_queue_num(dh_dev->parent);
-
-    return qnum;
-}
-
-uint16_t zxdh_en_sf_get_queue_size(struct dh_core_dev *dh_dev, uint32_t index)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-    uint16_t queue_size = 0;
-
-    queue_size = en_sf_dev->sf_ops->en_sf_get_queue_size(dh_dev->parent, index);
-
-    return queue_size;
-}
-
-struct pci_dev *zxdh_en_sf_get_pdev(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_get_pdev(dh_dev->parent);
-}
-
-uint64_t zxdh_en_sf_get_bar_virt_addr(struct dh_core_dev *dh_dev, uint8_t bar_num)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_get_bar_virt_addr(dh_dev->parent, bar_num);
-}
-
-int32_t zxdh_en_sf_msg_send_cmd(struct dh_core_dev *dh_dev, uint16_t module_id, void *msg, void *ack, bool is_sync)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_msg_send_cmd(dh_dev->parent, module_id, msg, ack, is_sync);
-}
-
-int32_t zxdh_en_sf_async_eq_enable(struct dh_core_dev *dh_dev, struct dh_eq_async *eq, const char *name, bool attach)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_async_eq_enable(dh_dev->parent, eq, name, attach);
-}
-
-void zxdh_en_sf_set_pf_link_up(struct dh_core_dev *dh_dev, bool link_up)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_set_pf_link_up(dh_dev->parent, link_up);
-    return;
-}
-
-bool zxdh_en_sf_get_pf_link_up(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_get_pf_link_up(dh_dev->parent);
-}
-
-void zxdh_en_sf_update_pf_link_info(struct dh_core_dev *dh_dev, struct link_info_struct *link_info_val)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_update_pf_link_info(dh_dev->parent, link_info_val);
-    return;
-}
-
-int32_t zxdh_en_sf_get_pf_drv_msg(struct dh_core_dev *dh_dev, uint8_t *drv_version, uint8_t *drv_version_len)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_get_drv_msg(dh_dev, drv_version, drv_version_len);
-}
-
-void zxdh_en_sf_set_vepa(struct dh_core_dev *dh_dev, bool setting)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_set_vepa(dh_dev->parent, setting);
-    return;
-}
-
-bool zxdh_en_sf_get_vepa(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_get_vepa(dh_dev->parent);
-}
-
-void zxdh_en_sf_get_link_info_from_vqm(struct dh_core_dev *dh_dev, uint8_t *link_up)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_get_link_info_from_vqm(dh_dev->parent, link_up);
-    return;
-}
-
-void zxdh_en_sf_set_vf_link_info(struct dh_core_dev *dh_dev, uint16_t vf_idx, uint8_t link_up)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_set_vf_link_info(dh_dev->parent, vf_idx, link_up);
-    return;
-}
-
-void zxdh_en_sf_set_pf_phy_port(struct dh_core_dev *dh_dev, uint8_t phy_port)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_set_pf_phy_port(dh_dev->parent, phy_port);
-    return;
-}
-
-uint8_t zxdh_en_sf_get_pf_phy_port(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_get_pf_phy_port(dh_dev->parent);
-}
-
-void zxdh_en_sf_set_rdma_netdev(struct dh_core_dev *dh_dev, void *data)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->netdev = data;
-    return;
-}
-
-void *zxdh_en_sf_get_rdma_netdev(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->netdev;
-}
-
-struct zxdh_rdma_if rdma_ops = {
-    .get_rdma_netdev           = zxdh_en_sf_get_rdma_netdev,
-};
-
-static int32_t zxdh_en_sf_request_port(struct dh_core_dev *dh_dev, void *data)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_request_port_info(dh_dev->parent, data);
-}
-
-static int32_t zxdh_en_sf_release_port(struct dh_core_dev *dh_dev, uint32_t pnl_id)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_release_port_info(dh_dev->parent, pnl_id);
-}
-
-static void zxdh_en_sf_set_bond_num(struct dh_core_dev *dh_dev, bool add)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_set_bond_num(dh_dev->parent, add);
-}
-
-static bool zxdh_en_sf_if_init(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_if_init(dh_dev->parent);
-}
-
-void zxdh_en_sf_set_init_comp_flag(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_set_init_comp_flag(dh_dev->parent);
-    return;
-}
-
-struct zxdh_ipv6_mac_tbl *zxdh_en_sf_get_ip6mac_tbl(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-    return en_sf_dev->sf_ops->en_sf_get_ip6mac_tbl(dh_dev->parent);
-}
-
-struct zxdh_en_if en_ops = {
-    .get_channels_num          = zxdh_en_sf_get_vqs_channels_num,
-    .create_vqs_channels       = zxdh_en_sf_create_vqs_channels,
-    .destroy_vqs_channels      = zxdh_en_sf_destroy_vqs_channels,
-    .switch_vqs_channel        = zxdh_en_sf_switch_vqs_channel,
-    .vqs_channel_bind_handler  = zxdh_en_sf_vqs_channel_bind_handler,
-    .vqs_channel_unbind_handler = zxdh_en_sf_vqs_channel_unbind_handler,
-    .vq_bind_channel           = zxdh_en_sf_vq_bind_channel,
-    .vq_unbind_channel         = zxdh_en_sf_vq_unbind_channel,
-    .vqs_bind_eqs              = zxdh_en_sf_vqs_bind_eqs,
-    .vqs_unbind_eqs            = zxdh_en_sf_vqs_unbind_eqs,
-    .vp_modern_map_vq_notify   = zxdh_en_sf_map_vq_notify,
-    .vp_modern_unmap_vq_notify = zxdh_en_sf_unmap_vq_notify,
-    .activate_phy_vq           = zxdh_en_sf_activate_phy_vq,
-    .get_phy_vq                = zxdh_en_sf_get_phy_vq,
-    .release_phy_vq            = zxdh_en_sf_release_phy_vq,
-    .set_status                = zxdh_en_sf_set_status,
-    .get_status                = zxdh_en_sf_get_status,
-    .set_vf_mac                = zxdh_en_sf_set_vf_mac,
-    .get_vf_mac                = zxdh_en_sf_get_vf_mac,
-    .set_mac                   = zxdh_en_sf_set_mac,
-    .get_mac                   = zxdh_en_sf_get_mac,
-    .get_features              = zxdh_en_sf_get_features,
-    .set_features              = zxdh_en_sf_set_features,
-    .get_queue_num             = zxdh_en_sf_get_queue_num,
-    .get_queue_size            = zxdh_en_sf_get_queue_size,
-    .set_queue_enable          = zxdh_en_sf_set_queue_enable,
-    .get_epbdf                 = zxdh_en_sf_get_epbdf,
-    .get_vport                 = zxdh_en_sf_get_vport,
-    .get_pcie_id               = zxdh_en_sf_get_pcie_id,
-    .get_slot_id               = zxdh_en_sf_get_slot_id,
-    .is_bond                   = zxdh_en_sf_is_bond,
-    .is_upf                    = zxdh_en_sf_is_upf,
-    .get_coredev_type          = zxdh_en_sf_get_coredev_type,
-    .get_pdev                  = zxdh_en_sf_get_pdev,
-    .get_bar_virt_addr         = zxdh_en_sf_get_bar_virt_addr,
-    .msg_send_cmd              = zxdh_en_sf_msg_send_cmd,
-    .async_eq_enable           = zxdh_en_sf_async_eq_enable,
-    .get_vf_item               = zxdh_en_sf_get_vf_item,
-    .set_pf_link_up            = zxdh_en_sf_set_pf_link_up,
-    .get_pf_link_up            = zxdh_en_sf_get_pf_link_up,
-    .update_pf_link_info       = zxdh_en_sf_update_pf_link_info,
-    .get_pf_drv_msg            = zxdh_en_sf_get_pf_drv_msg,
-    .set_vepa                  = zxdh_en_sf_set_vepa,
-    .get_vepa                  = zxdh_en_sf_get_vepa,
-    .get_link_info_from_vqm    = zxdh_en_sf_get_link_info_from_vqm,
-    .set_vf_link_info          = zxdh_en_sf_set_vf_link_info,
-    .request_port              = zxdh_en_sf_request_port,
-    .release_port              = zxdh_en_sf_release_port,
-    .set_bond_num              = zxdh_en_sf_set_bond_num,
-    .if_init                   = zxdh_en_sf_if_init,
-    .set_pf_phy_port           = zxdh_en_sf_set_pf_phy_port,
-    .set_rdma_netdev           = zxdh_en_sf_set_rdma_netdev,
-    .get_pf_phy_port           = zxdh_en_sf_get_pf_phy_port,
-    .set_init_comp_flag        = zxdh_en_sf_set_init_comp_flag,
-    .get_ip6mac_tbl            = zxdh_en_sf_get_ip6mac_tbl,
-};
-
-void zxdh_aux_adev_release(struct device *dev)
-{
-
-}
-
-int32_t zxdh_rdma_infos_request_reset(struct zxdh_rdma_dev_info *rdma_infos, enum zxdh_rdma_reset_type reset_type)
-{
-    return 0;
-}
-
-static struct zxdh_rdma_dev_ops rdma_handle_ops =
-{
-    .request_reset = zxdh_rdma_infos_request_reset,
-};
-
-struct zxdh_rdma_dev_info *zxdh_rdma_infos_init(struct dh_core_dev *dh_dev, struct zxdh_auxiliary_device *adev)
-{
-    struct zxdh_en_container *en_container = container_of(adev, struct zxdh_en_container, adev);
-    struct zxdh_rdma_dev_info *rdma_infos = NULL;
-
-    en_container->rdma_infos = kzalloc(sizeof(*en_container->rdma_infos), GFP_KERNEL);
-    if (unlikely(en_container->rdma_infos == NULL))
-    {
-        LOG_ERR("en_container->rdma_infos kzalloc failed\n");
-        return NULL;
-    }
-
-    rdma_infos = en_container->rdma_infos;
-    rdma_infos->pdev = zxdh_en_sf_get_pdev(dh_dev);
-    rdma_infos->hw_addr = (uint8_t __iomem *)zxdh_en_sf_get_bar_virt_addr(dh_dev, 0);
-    rdma_infos->ver.major = ZXDH_MAJOR_VER;
-    rdma_infos->ver.minor = ZXDH_MINOR_VER;
-    rdma_infos->rdma_protocol = ZXDH_RDMA_PROTOCOL_IWARP;
-    rdma_infos->ops = &rdma_handle_ops;
-    rdma_infos->ftype = ZXDH_FUNCTION_TYPE_PF;
-    rdma_infos->vport_id = zxdh_en_sf_get_vport(dh_dev);
-    if (zxdh_en_sf_get_coredev_type(dh_dev) == DH_COREDEV_VF)
-    {
-        rdma_infos->ftype = ZXDH_FUNCTION_TYPE_VF;
-    }
-
-    rdma_infos->msix_count = ZXDH_RDMA_CHANNELS_NUM;
-    rdma_infos->msix_entries.entry = ZXDH_RDMA_IRQ_START_IDX;
-    rdma_infos->msix_entries.vector = pci_irq_vector(rdma_infos->pdev, ZXDH_RDMA_IRQ_START_IDX);
-
-    return rdma_infos;
-}
-
-int32_t zxdh_net_adev_handle(struct dh_core_dev *dh_dev, struct zxdh_auxiliary_device *adev)
-{
-    struct zxdh_en_container *en_container = container_of(adev, struct zxdh_en_container, adev);
-
-    adev->name = ZXDH_EN_DEV_ID_NAME;
-    adev->dev.parent = dh_dev->device;
-    en_container->rdma_infos = NULL;
-    en_container->ops = &en_ops;
-
-    return 0;
-}
-
-int32_t zxdh_rdma_adev_handle(struct dh_core_dev *dh_dev, struct zxdh_auxiliary_device *adev)
-{
-    struct zxdh_en_container *en_container = container_of(adev, struct zxdh_en_container, adev);
-    struct zxdh_rdma_dev_info *rdma_infos = NULL;
-
-    adev->name = ZXDH_RDMA_DEV_NAME;
-    rdma_infos = zxdh_rdma_infos_init(dh_dev, adev);
-    if (unlikely(rdma_infos == NULL))
-    {
-        LOG_ERR("zxdh_rdma_infos_init failed, return NULL\n");
-        return -1;
-    }
-    rdma_infos->adev = adev;
-    adev->dev.parent = &rdma_infos->pdev->dev;
-    en_container->rdma_ops = &rdma_ops;
-
-    return 0;
-}
-
-struct zxdh_adev_handle_table zxdh_adev_handle_table[] =
-{
-    {NET_AUX_DEVICE,  zxdh_net_adev_handle},
-    {RDMA_AUX_DEVICE, zxdh_rdma_adev_handle},
-};
-
-int32_t zxdh_adev_handle(struct dh_core_dev *dh_dev, struct zxdh_auxiliary_device *adev, enum AUX_DEVICE_TYPE adev_type)
-{
-    uint32_t i = 0;
-    int32_t ret = 0;
-
-    for (i = 0; i < ARRAY_SIZE(zxdh_adev_handle_table); i++)
-    {
-        if((zxdh_adev_handle_table[i].adev_type == adev_type) && (zxdh_adev_handle_table[i].cb_fn))
-        {
-            ret = zxdh_adev_handle_table[i].cb_fn(dh_dev, adev);
-        }
-    }
-
-    return ret;
-}
-
-static DEFINE_IDA(zxdh_aux_adev_ida);
-
-int32_t zxdh_aux_plug_aux_dev(struct dh_core_dev *dh_dev, enum AUX_DEVICE_TYPE adev_type)
-{
-    struct zxdh_auxiliary_device *adev = NULL;
-    struct zxdh_en_sf_device *en_sf_dev = NULL;
-    struct zxdh_en_container *en_container = NULL;
-    struct zxdh_rdma_dev_info *rdma_infos = NULL;
-    int32_t ret = 0;
-    en_sf_dev = dh_core_priv(dh_dev);
-
-    en_container = kzalloc(sizeof(struct zxdh_en_container), GFP_KERNEL);
-    if (unlikely(en_container == NULL))
-    {
-        LOG_ERR("sf_con kzalloc is null\n");
-        return -ENOMEM;
-    }
-
-    en_container->aux_id = ida_alloc(&zxdh_aux_adev_ida, GFP_KERNEL);
-    if (en_container->aux_id < 0)
-    {
-        LOG_ERR("failed to allocate device id for aux drvs\n");
-        goto free_kzalloc;
-    }
-
-    adev = &en_container->adev;
-
-    adev->id = en_container->aux_id;
-    adev->dev.release = zxdh_aux_adev_release;
-    ret = zxdh_adev_handle(dh_dev, adev, adev_type);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_adev_handle failed: %d\n", ret);
-        goto free_ida_alloc;
-    }
-
-    if (en_sf_dev->aux_idx < 0)
-        goto free_rdma_infos_alloc;
-    en_sf_dev->adev[en_sf_dev->aux_idx] = adev;
-    en_sf_dev->aux_idx++;
-
-    en_container->parent = dh_dev;
-
-    ret = zxdh_auxiliary_device_init(adev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_auxiliary_device_init failed: %d\n", ret);
-        goto free_rdma_infos_alloc;
-    }
-
-    ret = zxdh_auxiliary_device_add(adev);
-    if (ret != 0)
-    {
-        LOG_ERR("zxdh_auxiliary_device_add failed: %d\n", ret);
-        goto release_aux_init;
-    }
-
-    return 0;
-
-release_aux_init:
-    zxdh_auxiliary_device_uninit(adev);
-free_rdma_infos_alloc:
-    if (adev_type == RDMA_AUX_DEVICE)
-    {
-        kfree(rdma_infos);
-        rdma_infos = NULL;
-    }
-free_ida_alloc:
-    ida_simple_remove(&zxdh_aux_adev_ida, en_container->aux_id);
-    en_container->aux_id = -1;
-free_kzalloc:
-    kfree(en_container);
-    en_container = NULL;
-    return ret;
-}
-
-void zxdh_aux_unplug_aux_dev(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = NULL;
-    struct zxdh_en_container *en_container = NULL;
-    int16_t i = 0;
-
-    en_sf_dev = dh_core_priv(dh_dev);
-    for (i = en_sf_dev->aux_idx - 1; i >= 0; i--)
-    {
-        en_container = container_of(en_sf_dev->adev[i], struct zxdh_en_container, adev);
-
-        zxdh_auxiliary_device_delete(en_sf_dev->adev[i]);
-        zxdh_auxiliary_device_uninit(en_sf_dev->adev[i]);
-        if (en_container->rdma_infos != NULL)
-        {
-            kfree(en_container->rdma_infos);
-            en_container->rdma_infos = NULL;
-        }
-        ida_simple_remove(&zxdh_aux_adev_ida, en_container->aux_id);
-        en_container->aux_id = -1;
-        kfree(en_container);
-        en_container = NULL;
-    }
-
-    return;
-}
-
-static int32_t zxdh_en_sf_dev_probe(struct zxdh_auxiliary_device *adev, const struct zxdh_auxiliary_device_id *id)
-{
-    int32_t err = 0;
-    struct zxdh_en_sf_container *sf_con = container_of(adev, struct zxdh_en_sf_container, adev);
-    struct dh_core_dev *dh_dev = NULL;
-    struct devlink *devlink = NULL;
-    struct zxdh_en_sf_device *en_sf_dev = NULL;
-    struct zxdh_en_sf_if *sf_ops = sf_con->ops;
-
-    LOG_INFO("sf level driver probe start\n");
-
-    devlink = zxdh_devlink_alloc(&adev->dev, &dh_sf_devlink_ops, sizeof(struct zxdh_en_sf_device));
-    if (devlink == NULL)
-    {
-        LOG_ERR("devlink alloc failed\n");
-        return -ENOMEM;
-    }
-
-    dh_dev = devlink_priv(devlink);
-    en_sf_dev = dh_core_priv(dh_dev);
-    dh_dev->parent = sf_con->dh_dev;
-    dh_dev->device = &adev->dev;
-    dh_dev->irq_table = dh_dev->parent->irq_table;
-    en_sf_dev->max_channels = sf_con->max_channels;
-    en_sf_dev->sf_ops = sf_ops;
-    en_sf_dev->aux_idx = 0;
-    sf_con->cdev = dh_dev;
-    dh_dev->devlink = devlink;
-    dh_dev->devlink_ops = &dh_sf_core_devlink_ops;
-
-    err = dh_en_sf_eq_table_init(dh_dev);
-    if (err != 0)
-    {
-        LOG_ERR("Failed to alloc IRQs\n");
-        goto err_eq_table_init;
-    }
-
-    dh_en_sf_eq_table_create(dh_dev, sf_ops);
-
-#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
-    zxdh_devlink_register(devlink);
-#else
-    zxdh_devlink_register(devlink, &adev->dev);
-#endif
-
-    zxdh_aux_plug_aux_dev(dh_dev, NET_AUX_DEVICE);
-    zxdh_aux_plug_aux_dev(dh_dev, RDMA_AUX_DEVICE);
-
-    LOG_INFO("sf level driver probe completed\n");
-
-    return 0;
-
-err_eq_table_init:
-    zxdh_devlink_free(devlink);
-    return err;
-}
-
-static int32_t zxdh_en_sf_dev_remove(struct zxdh_auxiliary_device *adev)
-{
-    struct zxdh_en_sf_container *sf_con = container_of(adev, struct zxdh_en_sf_container, adev);
-    struct dh_core_dev *dh_dev = NULL;
-    struct devlink *devlink = NULL;
-
-    LOG_INFO("sf level driver remove start\n");
-    dh_dev = sf_con->cdev;
-    devlink = dh_dev->devlink;
-
-    zxdh_aux_unplug_aux_dev(dh_dev);
-    zxdh_devlink_unregister(devlink);
-    dh_sf_eq_table_destroy(dh_dev);
-    dh_eq_table_cleanup(dh_dev);
-    zxdh_devlink_free(devlink);
-    LOG_INFO("sf level driver remove completed\n");
-
-    return 0;
-}
-
-static void zxdh_en_sf_dev_shutdown(struct zxdh_auxiliary_device *adev)
-{
-    struct zxdh_en_sf_container *sf_con = container_of(adev, struct zxdh_en_sf_container, adev);
-    struct dh_core_dev *dh_dev = NULL;
-    struct devlink *devlink = NULL;
-
-    LOG_INFO("sf level driver shutdown start\n");
-#ifdef CONFIG_ZXDH_SF
-    dh_dev = sf_con->cdev;
-    devlink = dh_dev->devlink;
-
-    zxdh_devlink_unregister(devlink);
-    dh_sf_eq_table_destroy(dh_dev);
-    dh_eq_table_cleanup(dh_dev);
-    zxdh_devlink_free(devlink);
-#endif
-    LOG_INFO("sf level driver shutdown completed\n");
-}
-
-static const struct zxdh_auxiliary_device_id zxdh_en_dev_id_table[] = {
-    { .name = ZXDH_PF_NAME "." ZXDH_PF_EN_SF_DEV_ID_NAME, },
-    //{ .name = ZXDH_MPF_NAME "." ZXDH_MPF_EN_SF_DEV_ID_NAME, },
-    { },
-};
-
-MODULE_DEVICE_TABLE(zxdh_auxiliary, zxdh_en_dev_id_table);
-
-static struct zxdh_auxiliary_driver zxdh_en_sf_driver = {
-    .name = ZXDH_PF_EN_SF_DEV_ID_NAME,
-    .probe = zxdh_en_sf_dev_probe,
-    .remove = zxdh_en_sf_dev_remove,
-    .shutdown = zxdh_en_sf_dev_shutdown,
-    .id_table = zxdh_en_dev_id_table,
-};
-
-int32_t zxdh_en_sf_driver_register(void)
-{
-    int32_t err = 0;
-
-    err = zxdh_auxiliary_driver_register(&zxdh_en_sf_driver);
-    if (err != 0)
-    {
-        goto err;
-    }
-
-    return 0;
-
-err:
-    return err;
-}
-
-void zxdh_en_sf_driver_unregister(void)
-{
-    zxdh_auxiliary_driver_unregister(&zxdh_en_sf_driver);
-}
+#include <linux/dinghai/driver.h>
+#ifdef AUX_BUS_NO_SUPPORT
+#include <linux/dinghai/auxiliary_bus.h>
+#else
+#include <linux/auxiliary_bus.h>
+#endif
+#include <linux/dev_printk.h>
+#include <linux/dinghai/devlink.h>
+#include <linux/dinghai/helper.h>
+#include <linux/dinghai/en_aux.h>
+#include <linux/dinghai/dh_cmd.h>
+#include "en_aux.h"
+#include "en_sf.h"
+#include "./en_sf/eq.h"
+
+extern struct devlink_ops dh_sf_devlink_ops;
+extern struct dh_core_devlink_ops dh_sf_core_devlink_ops;
+
+int32_t zxdh_sf_get_vq_lock(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+	int32_t ret = 0;
+
+	ret = en_sf_dev->sf_ops->en_sf_get_vq_lock(dh_dev->parent);
+	if (ret != 0) {
+		LOG_ERR("en_sf_get_vq_lock failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int32_t zxdh_sf_release_vq_lock(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+	int32_t ret = 0;
+
+	ret = en_sf_dev->sf_ops->en_sf_release_vq_lock(dh_dev->parent);
+	if (ret != 0) {
+		LOG_ERR("en_sf_release_vq_lock failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int32_t zxdh_sf_get_phy_vq(struct dh_core_dev *dh_dev, uint16_t index)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+	int32_t phy_index = 0;
+
+	phy_index = en_sf_dev->sf_ops->en_sf_get_phy_vq(dh_dev->parent, index);
+	if (phy_index < 0) {
+		LOG_ERR("en_sf_get_phy_vq failed: %d\n", phy_index);
+	}
+
+	return phy_index;
+}
+
+int32_t zxdh_sf_release_phy_vq(struct dh_core_dev *dh_dev, uint32_t *phy_index,
+							   uint16_t total_qnum)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+	int32_t ret = 0;
+
+	ret = en_sf_dev->sf_ops->en_sf_release_phy_vq(dh_dev->parent, phy_index,
+												  total_qnum);
+	if (ret != 0) {
+		LOG_ERR("en_sf_relaese_phy_vq failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+bool zxdh_en_sf_is_bond(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_is_bond(dh_dev->parent);
+}
+
+int32_t zxdh_en_sf_get_phy_vq(struct dh_core_dev *dh_dev, uint16_t index)
+{
+	int32_t ret = 0;
+	int32_t phy_index = 0;
+
+	ret = zxdh_sf_get_vq_lock(dh_dev);
+	if (ret < 0) {
+		return ret;
+	}
+
+	phy_index = zxdh_sf_get_phy_vq(dh_dev, index);
+
+	ret = zxdh_sf_release_vq_lock(dh_dev);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return phy_index;
+}
+
+int32_t zxdh_en_sf_release_phy_vq(struct dh_core_dev *dh_dev,
+								  uint32_t *phy_index, uint16_t total_qnum)
+{
+	int32_t ret = 0;
+
+	ret = zxdh_sf_get_vq_lock(dh_dev);
+	if (ret < 0) {
+		return ret;
+	}
+
+	zxdh_sf_release_phy_vq(dh_dev, phy_index, total_qnum);
+
+	zxdh_sf_release_vq_lock(dh_dev);
+
+	return ret;
+}
+
+void zxdh_en_sf_set_status(struct dh_core_dev *dh_dev, uint8_t status)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_set_status(dh_dev->parent, status);
+
+	return;
+}
+
+uint8_t zxdh_en_sf_get_status(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+	uint8_t status = 0;
+
+	status = en_sf_dev->sf_ops->en_sf_get_status(dh_dev->parent);
+
+	return status;
+}
+
+void zxdh_en_sf_set_vf_mac(struct dh_core_dev *dh_dev, uint8_t *mac,
+						   int32_t vf_id)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_set_vf_mac(dh_dev->parent, mac, vf_id);
+
+	return;
+}
+
+void zxdh_en_sf_get_vf_mac(struct dh_core_dev *dh_dev, uint8_t *mac,
+						   int32_t vf_id)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_get_vf_mac(dh_dev->parent, mac, vf_id);
+
+	return;
+}
+
+void zxdh_en_sf_set_mac(struct dh_core_dev *dh_dev, uint8_t *mac)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_set_mac(dh_dev->parent, mac);
+
+	return;
+}
+
+void zxdh_en_sf_get_mac(struct dh_core_dev *dh_dev, uint8_t *mac)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_get_mac(dh_dev->parent, mac);
+
+	return;
+}
+
+uint64_t zxdh_en_sf_get_features(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+	uint64_t device_feature = 0;
+
+	device_feature = en_sf_dev->sf_ops->en_sf_get_features(dh_dev->parent);
+
+	return device_feature;
+}
+
+void zxdh_en_sf_set_features(struct dh_core_dev *dh_dev, uint64_t features)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_set_features(dh_dev->parent, features);
+
+	return;
+}
+
+uint16_t zxdh_en_sf_get_queue_num(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+	uint16_t qnum = 0;
+
+	qnum = en_sf_dev->sf_ops->en_sf_get_queue_num(dh_dev->parent);
+
+	return qnum;
+}
+
+uint16_t zxdh_en_sf_get_queue_size(struct dh_core_dev *dh_dev, uint32_t index)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+	uint16_t queue_size = 0;
+
+	queue_size = en_sf_dev->sf_ops->en_sf_get_queue_size(dh_dev->parent, index);
+
+	return queue_size;
+}
+
+struct pci_dev *zxdh_en_sf_get_pdev(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_get_pdev(dh_dev->parent);
+}
+
+uint64_t zxdh_en_sf_get_bar_virt_addr(struct dh_core_dev *dh_dev,
+									  uint8_t bar_num)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_get_bar_virt_addr(dh_dev->parent, bar_num);
+}
+
+int32_t zxdh_en_sf_msg_send_cmd(struct dh_core_dev *dh_dev, uint16_t module_id,
+								void *msg, void *ack, bool is_sync)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_msg_send_cmd(dh_dev->parent, module_id, msg,
+												 ack, is_sync);
+}
+
+int32_t zxdh_en_sf_async_eq_enable(struct dh_core_dev *dh_dev,
+								   struct dh_eq_async *eq, const char *name,
+								   bool attach)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_async_eq_enable(dh_dev->parent, eq, name,
+													attach);
+}
+
+void zxdh_en_sf_set_pf_link_up(struct dh_core_dev *dh_dev, bool link_up)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_set_pf_link_up(dh_dev->parent, link_up);
+	return;
+}
+
+bool zxdh_en_sf_get_pf_link_up(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_get_pf_link_up(dh_dev->parent);
+}
+
+void zxdh_en_sf_update_pf_link_info(struct dh_core_dev *dh_dev,
+									struct link_info_struct *link_info_val)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_update_pf_link_info(dh_dev->parent, link_info_val);
+	return;
+}
+
+int32_t zxdh_en_sf_get_pf_drv_msg(struct dh_core_dev *dh_dev,
+								  uint8_t *drv_version,
+								  uint8_t *drv_version_len)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_get_drv_msg(dh_dev, drv_version,
+												drv_version_len);
+}
+
+void zxdh_en_sf_set_vepa(struct dh_core_dev *dh_dev, bool setting)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_set_vepa(dh_dev->parent, setting);
+	return;
+}
+
+bool zxdh_en_sf_get_vepa(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_get_vepa(dh_dev->parent);
+}
+
+void zxdh_en_sf_get_link_info_from_vqm(struct dh_core_dev *dh_dev,
+									   uint8_t *link_up)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_get_link_info_from_vqm(dh_dev->parent, link_up);
+	return;
+}
+
+void zxdh_en_sf_set_vf_link_info(struct dh_core_dev *dh_dev, uint16_t vf_idx,
+								 uint8_t link_up)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_set_vf_link_info(dh_dev->parent, vf_idx, link_up);
+	return;
+}
+
+void zxdh_en_sf_set_pf_phy_port(struct dh_core_dev *dh_dev, uint8_t phy_port)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_set_pf_phy_port(dh_dev->parent, phy_port);
+	return;
+}
+
+uint8_t zxdh_en_sf_get_pf_phy_port(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_get_pf_phy_port(dh_dev->parent);
+}
+
+void zxdh_en_sf_set_rdma_netdev(struct dh_core_dev *dh_dev, void *data)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->netdev = data;
+	return;
+}
+
+void *zxdh_en_sf_get_rdma_netdev(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->netdev;
+}
+
+struct zxdh_rdma_if rdma_ops = {
+	.get_rdma_netdev = zxdh_en_sf_get_rdma_netdev,
+};
+
+static int32_t zxdh_en_sf_request_port(struct dh_core_dev *dh_dev, void *data)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_request_port_info(dh_dev->parent, data);
+}
+
+static int32_t zxdh_en_sf_release_port(struct dh_core_dev *dh_dev,
+									   uint32_t pnl_id)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_release_port_info(dh_dev->parent, pnl_id);
+}
+
+static void zxdh_en_sf_set_bond_num(struct dh_core_dev *dh_dev, bool add)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_set_bond_num(dh_dev->parent, add);
+}
+
+static bool zxdh_en_sf_if_init(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_if_init(dh_dev->parent);
+}
+
+void zxdh_en_sf_set_init_comp_flag(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_set_init_comp_flag(dh_dev->parent);
+	return;
+}
+
+struct zxdh_en_if en_ops = {
+	.get_channels_num = zxdh_en_sf_get_vqs_channels_num,
+	.create_vqs_channels = zxdh_en_sf_create_vqs_channels,
+	.destroy_vqs_channels = zxdh_en_sf_destroy_vqs_channels,
+	.switch_vqs_channel = zxdh_en_sf_switch_vqs_channel,
+	.vqs_channel_bind_handler = zxdh_en_sf_vqs_channel_bind_handler,
+	.vqs_channel_unbind_handler = zxdh_en_sf_vqs_channel_unbind_handler,
+	.vq_bind_channel = zxdh_en_sf_vq_bind_channel,
+	.vq_unbind_channel = zxdh_en_sf_vq_unbind_channel,
+	.vqs_bind_eqs = zxdh_en_sf_vqs_bind_eqs,
+	.vqs_unbind_eqs = zxdh_en_sf_vqs_unbind_eqs,
+	.vp_modern_map_vq_notify = zxdh_en_sf_map_vq_notify,
+	.vp_modern_unmap_vq_notify = zxdh_en_sf_unmap_vq_notify,
+	.activate_phy_vq = zxdh_en_sf_activate_phy_vq,
+	.get_phy_vq = zxdh_en_sf_get_phy_vq,
+	.release_phy_vq = zxdh_en_sf_release_phy_vq,
+	.set_status = zxdh_en_sf_set_status,
+	.get_status = zxdh_en_sf_get_status,
+	.set_vf_mac = zxdh_en_sf_set_vf_mac,
+	.get_vf_mac = zxdh_en_sf_get_vf_mac,
+	.set_mac = zxdh_en_sf_set_mac,
+	.get_mac = zxdh_en_sf_get_mac,
+	.get_features = zxdh_en_sf_get_features,
+	.set_features = zxdh_en_sf_set_features,
+	.get_queue_num = zxdh_en_sf_get_queue_num,
+	.get_queue_size = zxdh_en_sf_get_queue_size,
+	.set_queue_enable = zxdh_en_sf_set_queue_enable,
+	.get_epbdf = zxdh_en_sf_get_epbdf,
+	.get_vport = zxdh_en_sf_get_vport,
+	.get_pcie_id = zxdh_en_sf_get_pcie_id,
+	.get_slot_id = zxdh_en_sf_get_slot_id,
+	.is_bond = zxdh_en_sf_is_bond,
+	.get_coredev_type = zxdh_en_sf_get_coredev_type,
+	.get_pdev = zxdh_en_sf_get_pdev,
+	.get_bar_virt_addr = zxdh_en_sf_get_bar_virt_addr,
+	.msg_send_cmd = zxdh_en_sf_msg_send_cmd,
+	.async_eq_enable = zxdh_en_sf_async_eq_enable,
+	.get_vf_item = zxdh_en_sf_get_vf_item,
+	.set_pf_link_up = zxdh_en_sf_set_pf_link_up,
+	.get_pf_link_up = zxdh_en_sf_get_pf_link_up,
+	.update_pf_link_info = zxdh_en_sf_update_pf_link_info,
+	.get_pf_drv_msg = zxdh_en_sf_get_pf_drv_msg,
+	.set_vepa = zxdh_en_sf_set_vepa,
+	.get_vepa = zxdh_en_sf_get_vepa,
+	.get_link_info_from_vqm = zxdh_en_sf_get_link_info_from_vqm,
+	.set_vf_link_info = zxdh_en_sf_set_vf_link_info,
+	.request_port = zxdh_en_sf_request_port,
+	.release_port = zxdh_en_sf_release_port,
+	.set_bond_num = zxdh_en_sf_set_bond_num,
+	.if_init = zxdh_en_sf_if_init,
+	.set_pf_phy_port = zxdh_en_sf_set_pf_phy_port,
+	.set_rdma_netdev = zxdh_en_sf_set_rdma_netdev,
+	.get_pf_phy_port = zxdh_en_sf_get_pf_phy_port,
+	.set_init_comp_flag = zxdh_en_sf_set_init_comp_flag,
+};
+
+void zxdh_aux_adev_release(struct device *dev)
+{
+}
+
+int32_t zxdh_rdma_infos_request_reset(struct zxdh_rdma_dev_info *rdma_infos,
+									  enum zxdh_rdma_reset_type reset_type)
+{
+	return 0;
+}
+
+static struct zxdh_rdma_dev_ops rdma_handle_ops = {
+	.request_reset = zxdh_rdma_infos_request_reset,
+};
+
+struct zxdh_rdma_dev_info *zxdh_rdma_infos_init(struct dh_core_dev *dh_dev,
+												struct auxiliary_device *adev)
+{
+	struct zxdh_en_container *en_container =
+			container_of(adev, struct zxdh_en_container, adev);
+	struct zxdh_rdma_dev_info *rdma_infos = NULL;
+
+	en_container->rdma_infos =
+			kzalloc(sizeof(*en_container->rdma_infos), GFP_KERNEL);
+	if (unlikely(en_container->rdma_infos == NULL)) {
+		LOG_ERR("en_container->rdma_infos kzalloc failed\n");
+		return NULL;
+	}
+
+	rdma_infos = en_container->rdma_infos;
+	rdma_infos->pdev = zxdh_en_sf_get_pdev(dh_dev);
+	rdma_infos->hw_addr =
+			(uint8_t __iomem *)zxdh_en_sf_get_bar_virt_addr(dh_dev, 0);
+	rdma_infos->ver.major = ZXDH_MAJOR_VER;
+	rdma_infos->ver.minor = ZXDH_MINOR_VER;
+	rdma_infos->rdma_protocol = ZXDH_RDMA_PROTOCOL_IWARP;
+	rdma_infos->ops = &rdma_handle_ops;
+	rdma_infos->ftype = ZXDH_FUNCTION_TYPE_PF;
+	rdma_infos->vport_id = zxdh_en_sf_get_vport(dh_dev);
+	if (zxdh_en_sf_get_coredev_type(dh_dev) == DH_COREDEV_VF) {
+		rdma_infos->ftype = ZXDH_FUNCTION_TYPE_VF;
+	}
+
+	rdma_infos->msix_count = ZXDH_RDMA_CHANNELS_NUM;
+	rdma_infos->msix_entries.entry = ZXDH_RDMA_IRQ_START_IDX;
+	rdma_infos->msix_entries.vector =
+			pci_irq_vector(rdma_infos->pdev, ZXDH_RDMA_IRQ_START_IDX);
+
+	return rdma_infos;
+}
+
+int32_t zxdh_net_adev_handle(struct dh_core_dev *dh_dev,
+							 struct auxiliary_device *adev)
+{
+	struct zxdh_en_container *en_container =
+			container_of(adev, struct zxdh_en_container, adev);
+
+	adev->name = ZXDH_EN_DEV_ID_NAME;
+	adev->dev.parent = dh_dev->device;
+	en_container->rdma_infos = NULL;
+	en_container->ops = &en_ops;
+
+	return 0;
+}
+
+int32_t zxdh_rdma_adev_handle(struct dh_core_dev *dh_dev,
+							  struct auxiliary_device *adev)
+{
+	struct zxdh_en_container *en_container =
+			container_of(adev, struct zxdh_en_container, adev);
+	struct zxdh_rdma_dev_info *rdma_infos = NULL;
+
+	adev->name = ZXDH_RDMA_DEV_NAME;
+	rdma_infos = zxdh_rdma_infos_init(dh_dev, adev);
+	if (unlikely(rdma_infos == NULL)) {
+		LOG_ERR("zxdh_rdma_infos_init failed, return NULL\n");
+		return -1;
+	}
+	rdma_infos->adev = adev;
+	adev->dev.parent = &rdma_infos->pdev->dev;
+	en_container->rdma_ops = &rdma_ops;
+
+	return 0;
+}
+
+struct zxdh_adev_handle_table zxdh_adev_handle_table[] = {
+	{ NET_AUX_DEVICE, zxdh_net_adev_handle },
+	{ RDMA_AUX_DEVICE, zxdh_rdma_adev_handle },
+};
+
+int32_t zxdh_adev_handle(struct dh_core_dev *dh_dev,
+						 struct auxiliary_device *adev,
+						 enum AUX_DEVICE_TYPE adev_type)
+{
+	uint32_t i = 0;
+	int32_t ret = 0;
+
+	for (i = 0; i < ARRAY_SIZE(zxdh_adev_handle_table); i++) {
+		if ((zxdh_adev_handle_table[i].adev_type == adev_type) &&
+			(zxdh_adev_handle_table[i].cb_fn)) {
+			ret = zxdh_adev_handle_table[i].cb_fn(dh_dev, adev);
+		}
+	}
+
+	return ret;
+}
+
+static DEFINE_IDA(zxdh_aux_adev_ida);
+
+int32_t zxdh_aux_plug_aux_dev(struct dh_core_dev *dh_dev,
+							  enum AUX_DEVICE_TYPE adev_type)
+{
+	struct auxiliary_device *adev = NULL;
+	struct zxdh_en_sf_device *en_sf_dev = NULL;
+	struct zxdh_en_container *en_container = NULL;
+	struct zxdh_rdma_dev_info *rdma_infos = NULL;
+	int32_t ret = 0;
+	en_sf_dev = dh_core_priv(dh_dev);
+
+	en_container = kzalloc(sizeof(struct zxdh_en_container), GFP_KERNEL);
+	if (unlikely(en_container == NULL)) {
+		LOG_ERR("sf_con kzalloc is null\n");
+		return -ENOMEM;
+	}
+
+	en_container->aux_id = ida_alloc(&zxdh_aux_adev_ida, GFP_KERNEL);
+	if (en_container->aux_id < 0) {
+		LOG_ERR("failed to allocate device id for aux drvs\n");
+		goto free_kzalloc;
+	}
+
+	adev = &en_container->adev;
+
+	adev->id = en_container->aux_id;
+	adev->dev.release = zxdh_aux_adev_release;
+	ret = zxdh_adev_handle(dh_dev, adev, adev_type);
+	if (ret != 0) {
+		LOG_ERR("zxdh_adev_handle failed: %d\n", ret);
+		goto free_ida_alloc;
+	}
+
+	en_sf_dev->adev[en_sf_dev->aux_idx] = adev;
+	en_sf_dev->aux_idx++;
+
+	en_container->parent = dh_dev;
+
+	ret = auxiliary_device_init(adev);
+	if (ret != 0) {
+		LOG_ERR("auxiliary_device_init failed: %d\n", ret);
+		goto free_rdma_infos_alloc;
+	}
+
+	ret = auxiliary_device_add(adev);
+	if (ret != 0) {
+		LOG_ERR("auxiliary_device_add failed: %d\n", ret);
+		goto release_aux_init;
+	}
+
+	return 0;
+
+release_aux_init:
+	auxiliary_device_uninit(adev);
+free_rdma_infos_alloc:
+	if (adev_type == RDMA_AUX_DEVICE) {
+		kfree(rdma_infos);
+		rdma_infos = NULL;
+	}
+free_ida_alloc:
+	ida_simple_remove(&zxdh_aux_adev_ida, en_container->aux_id);
+	en_container->aux_id = -1;
+free_kzalloc:
+	kfree(en_container);
+	en_container = NULL;
+	return ret;
+}
+
+void zxdh_aux_unplug_aux_dev(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = NULL;
+	struct zxdh_en_container *en_container = NULL;
+	int16_t i = 0;
+
+	en_sf_dev = dh_core_priv(dh_dev);
+	for (i = en_sf_dev->aux_idx - 1; i >= 0; i--) {
+		en_container = container_of(en_sf_dev->adev[i],
+									struct zxdh_en_container, adev);
+
+		auxiliary_device_delete(en_sf_dev->adev[i]);
+		auxiliary_device_uninit(en_sf_dev->adev[i]);
+		if (en_container->rdma_infos != NULL) {
+			kfree(en_container->rdma_infos);
+			en_container->rdma_infos = NULL;
+		}
+		ida_simple_remove(&zxdh_aux_adev_ida, en_container->aux_id);
+		en_container->aux_id = -1;
+		kfree(en_container);
+		en_container = NULL;
+	}
+
+	return;
+}
+
+static int32_t zxdh_en_sf_dev_probe(struct auxiliary_device *adev,
+									const struct auxiliary_device_id *id)
+{
+	int32_t err = 0;
+	struct zxdh_en_sf_container *sf_con =
+			container_of(adev, struct zxdh_en_sf_container, adev);
+	struct dh_core_dev *dh_dev = NULL;
+	struct devlink *devlink = NULL;
+	struct zxdh_en_sf_device *en_sf_dev = NULL;
+	struct zxdh_en_sf_if *sf_ops = sf_con->ops;
+
+	devlink = zxdh_devlink_alloc(&adev->dev, &dh_sf_devlink_ops,
+								 sizeof(struct zxdh_en_sf_device));
+	if (devlink == NULL) {
+		LOG_ERR("devlink alloc failed\n");
+		return -ENOMEM;
+	}
+
+	dh_dev = devlink_priv(devlink);
+	en_sf_dev = dh_core_priv(dh_dev);
+	dh_dev->parent = sf_con->dh_dev;
+	dh_dev->device = &adev->dev;
+	dh_dev->irq_table = dh_dev->parent->irq_table;
+	en_sf_dev->max_channels = sf_con->max_channels;
+	en_sf_dev->sf_ops = sf_ops;
+	en_sf_dev->aux_idx = 0;
+	sf_con->cdev = dh_dev;
+	dh_dev->devlink = devlink;
+	dh_dev->devlink_ops = &dh_sf_core_devlink_ops;
+
+	err = dh_en_sf_eq_table_init(dh_dev);
+	if (err != 0) {
+		LOG_ERR("Failed to alloc IRQs\n");
+		goto err_eq_table_init;
+	}
+
+	dh_en_sf_eq_table_create(dh_dev, sf_ops);
+
+#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
+	zxdh_devlink_register(devlink);
+#else
+	zxdh_devlink_register(devlink, &adev->dev);
+#endif
+
+	zxdh_aux_plug_aux_dev(dh_dev, NET_AUX_DEVICE);
+	zxdh_aux_plug_aux_dev(dh_dev, RDMA_AUX_DEVICE);
+
+	return 0;
+
+err_eq_table_init:
+	zxdh_devlink_free(devlink);
+	return err;
+}
+
+static int32_t zxdh_en_sf_dev_remove(struct auxiliary_device *adev)
+{
+	struct zxdh_en_sf_container *sf_con =
+			container_of(adev, struct zxdh_en_sf_container, adev);
+	struct dh_core_dev *dh_dev = NULL;
+	struct devlink *devlink = NULL;
+
+	LOG_INFO("zxdh_en_sf_dev_remove start\n");
+	dh_dev = sf_con->cdev;
+	devlink = dh_dev->devlink;
+
+	zxdh_aux_unplug_aux_dev(dh_dev);
+	zxdh_devlink_unregister(devlink);
+	dh_sf_eq_table_destroy(dh_dev);
+	dh_eq_table_cleanup(dh_dev);
+	zxdh_devlink_free(devlink);
+	LOG_INFO("zxdh_en_sf_dev_remove stop\n");
+
+	return 0;
+}
+
+static void zxdh_en_sf_dev_shutdown(struct auxiliary_device *adev)
+{
+	struct zxdh_en_sf_container *sf_con =
+			container_of(adev, struct zxdh_en_sf_container, adev);
+	struct dh_core_dev *dh_dev = NULL;
+	struct devlink *devlink = NULL;
+
+	LOG_INFO("zxdh_en_sf_dev_shutdown start\n");
+#ifdef CONFIG_ZXDH_SF
+	dh_dev = sf_con->cdev;
+	devlink = dh_dev->devlink;
+
+	zxdh_devlink_unregister(devlink);
+	dh_sf_eq_table_destroy(dh_dev);
+	dh_eq_table_cleanup(dh_dev);
+	zxdh_devlink_free(devlink);
+#endif
+	LOG_INFO("zxdh_en_sf_dev_shutdown stop\n");
+}
+
+static const struct auxiliary_device_id zxdh_en_dev_id_table[] = {
+	{
+			.name = ZXDH_PF_NAME "." ZXDH_PF_EN_SF_DEV_ID_NAME,
+	},
+	//{ .name = ZXDH_MPF_NAME "." ZXDH_MPF_EN_SF_DEV_ID_NAME, },
+	{},
+};
+
+MODULE_DEVICE_TABLE(auxiliary, zxdh_en_dev_id_table);
+
+static struct auxiliary_driver zxdh_en_sf_driver = {
+	.name = ZXDH_PF_EN_SF_DEV_ID_NAME,
+	.probe = zxdh_en_sf_dev_probe,
+	.remove = zxdh_en_sf_dev_remove,
+	.shutdown = zxdh_en_sf_dev_shutdown,
+	.id_table = zxdh_en_dev_id_table,
+};
+
+int32_t zxdh_en_sf_driver_register(void)
+{
+	int32_t err = 0;
+
+	err = auxiliary_driver_register(&zxdh_en_sf_driver);
+	if (err != 0) {
+		goto err;
+	}
+
+	return 0;
+
+err:
+	return err;
+}
+
+void zxdh_en_sf_driver_unregister(void)
+{
+	auxiliary_driver_unregister(&zxdh_en_sf_driver);
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_sf.h b/src/net/drivers/net/ethernet/dinghai/en_sf.h
index 028b951a7d05c090899485e22921df2a7b087ca1..2999e3bf4ec3ba898a1ffb1dc2ad739f5533d2e6 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_sf.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_sf.h
@@ -1,107 +1,104 @@
-#ifndef __ZXDH_PF_EN_SF_H__
-#define __ZXDH_PF_EN_SF_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/auxiliary_bus.h>
-#include <linux/dinghai/en_sf.h>
-#include <linux/types.h>
-#include <linux/dinghai/queue.h>
-#include <linux/dinghai/pci_irq.h>
-
-#define ZXDH_MAJOR_VER     10
-#define ZXDH_MINOR_VER     1
-#define ZXDH_SF_ADEV_NUM   32
-
-struct zxdh_rdma_dev_info;
-
-enum AUX_DEVICE_TYPE
-{
-    NET_AUX_DEVICE,
-    RDMA_AUX_DEVICE,
-};
-
-struct zxdh_adev_handle_table
-{
-    enum AUX_DEVICE_TYPE adev_type;
-    int32_t (*cb_fn)(struct dh_core_dev *dh_dev, struct zxdh_auxiliary_device *adev);
-};
-
-struct zxdh_ver_info
-{
-    uint16_t major;
-    uint16_t minor;
-    uint64_t support;
-};
-
-enum zxdh_function_type
-{
-    ZXDH_FUNCTION_TYPE_PF,
-    ZXDH_FUNCTION_TYPE_VF,
-};
-
-enum zxdh_rdma_protocol
-{
-    ZXDH_RDMA_PROTOCOL_IWARP = BIT(0),
-    ZXDH_RDMA_PROTOCOL_ROCEV2 = BIT(1),
-};
-
-struct zxdh_rdma_qos_params
-{
-    uint8_t reserve;
-};
-
-enum zxdh_rdma_reset_type
-{
-    ZXDH_RESET_MTU_CHANGE,
-    ZXDH_RESET_HW_ERROR,
-};
-
-struct zxdh_rdma_dev_ops
-{
-    int32_t (*request_reset)(struct zxdh_rdma_dev_info *rdma_infos, enum zxdh_rdma_reset_type reset_type);
-};
-
-/* auxiliary driver tailored information about the core PCI dev */
-struct zxdh_rdma_dev_info
-{
-    struct pci_dev *pdev;
-    struct zxdh_auxiliary_device *adev;
-
-    uint8_t __iomem *hw_addr;
-    int32_t adev_info_id;
-    struct zxdh_ver_info ver;
-
-    void *auxiliary_priv;
-
-    enum zxdh_function_type ftype;
-    uint16_t vport_id;
-    /* Current active RDMA protocol */
-    enum zxdh_rdma_protocol rdma_protocol;
-
-    struct zxdh_rdma_qos_params qos_info;
-
-    struct msix_entry msix_entries;
-    /* How many vectors are reserved for this device */
-    uint16_t msix_count;
-    /* function pointers to be initialized by core PCI driver and called by auxiliary driver */
-    struct zxdh_rdma_dev_ops *ops;
-};
-
-struct zxdh_en_sf_device {
-    int32_t max_channels;
-    struct zxdh_en_sf_if *sf_ops;
-    void *netdev;
-
-    struct zxdh_auxiliary_device *adev[ZXDH_SF_ADEV_NUM];
-    int32_t aux_idx;
-};
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef __ZXDH_PF_EN_SF_H__
+#define __ZXDH_PF_EN_SF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/driver.h>
+#ifdef AUX_BUS_NO_SUPPORT
+#include <linux/dinghai/auxiliary_bus.h>
+#else
+#include <linux/auxiliary_bus.h>
+#endif
+#include <linux/dinghai/en_sf.h>
+#include <linux/types.h>
+#include <linux/dinghai/queue.h>
+#include <linux/dinghai/pci_irq.h>
+
+#define ZXDH_MAJOR_VER 10
+#define ZXDH_MINOR_VER 1
+#define ZXDH_SF_ADEV_NUM 32
+
+struct zxdh_rdma_dev_info;
+
+enum AUX_DEVICE_TYPE {
+	NET_AUX_DEVICE,
+	RDMA_AUX_DEVICE,
+};
+
+struct zxdh_adev_handle_table {
+	enum AUX_DEVICE_TYPE adev_type;
+	int32_t (*cb_fn)(struct dh_core_dev *dh_dev, struct auxiliary_device *adev);
+};
+
+struct zxdh_ver_info {
+	uint16_t major;
+	uint16_t minor;
+	uint64_t support;
+};
+
+enum zxdh_function_type {
+	ZXDH_FUNCTION_TYPE_PF,
+	ZXDH_FUNCTION_TYPE_VF,
+};
+
+enum zxdh_rdma_protocol {
+	ZXDH_RDMA_PROTOCOL_IWARP = BIT(0),
+	ZXDH_RDMA_PROTOCOL_ROCEV2 = BIT(1),
+};
+
+struct zxdh_rdma_qos_params {
+	uint8_t reserve;
+};
+
+enum zxdh_rdma_reset_type {
+	ZXDH_RESET_MTU_CHANGE,
+	ZXDH_RESET_HW_ERROR,
+};
+
+struct zxdh_rdma_dev_ops {
+	int32_t (*request_reset)(struct zxdh_rdma_dev_info *rdma_infos,
+							 enum zxdh_rdma_reset_type reset_type);
+};
+
+/* auxiliary driver tailored information about the core PCI dev */
+struct zxdh_rdma_dev_info {
+	struct pci_dev *pdev;
+	struct auxiliary_device *adev;
+
+	uint8_t __iomem *hw_addr;
+	int32_t adev_info_id;
+	struct zxdh_ver_info ver;
+
+	void *auxiliary_priv;
+
+	enum zxdh_function_type ftype;
+	uint16_t vport_id;
+	/* Current active RDMA protocol */
+	enum zxdh_rdma_protocol rdma_protocol;
+
+	struct zxdh_rdma_qos_params qos_info;
+
+	struct msix_entry msix_entries;
+	/* How many vectors are reserved for this device */
+	uint16_t msix_count;
+	/* function pointers to be initialized by core PCI driver and called by
+   * auxiliary driver */
+	struct zxdh_rdma_dev_ops *ops;
+};
+
+struct zxdh_en_sf_device {
+	int32_t max_channels;
+	struct zxdh_en_sf_if *sf_ops;
+	void *netdev;
+
+	struct auxiliary_device *adev[ZXDH_SF_ADEV_NUM];
+	int32_t aux_idx;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_sf/devlink.c b/src/net/drivers/net/ethernet/dinghai/en_sf/devlink.c
index 0a65b7508352ccb720490ba2da2aece9d69cdec7..d303a03ab101084ab11d3bdbe341900d4367f2b5 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_sf/devlink.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_sf/devlink.c
@@ -2,130 +2,123 @@
 #include <net/devlink.h>
 #include "devlink.h"
 
-
 struct devlink_ops dh_sf_devlink_ops = {
 
 };
 
 enum {
-    DH_SF_PARAMS_MAX,
+	DH_SF_PARAMS_MAX,
 };
 
 static int32_t __attribute__((unused)) sample_check(struct dh_core_dev *dev)
 {
-    return 1;
+	return 1;
 }
 
 enum dh_sf_devlink_param_id {
-    DH_SF_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
-    DH_SF_DEVLINK_PARAM_ID_SAMPLE,
+	DH_SF_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
+	DH_SF_DEVLINK_PARAM_ID_SAMPLE,
 };
 
-
 static int32_t dh_devlink_sample_set(struct devlink *devlink, uint32_t id,
-                              struct devlink_param_gset_ctx *ctx)
+									 struct devlink_param_gset_ctx *ctx)
 {
-    struct dh_core_dev * __attribute__((unused)) dev = devlink_priv(devlink);
+	struct dh_core_dev *__attribute__((unused)) dev = devlink_priv(devlink);
 
-    return 0;
+	return 0;
 }
 
 static int32_t dh_devlink_sample_get(struct devlink *devlink, uint32_t id,
-                              struct devlink_param_gset_ctx *ctx)
+									 struct devlink_param_gset_ctx *ctx)
 {
-    struct dh_core_dev * __attribute__((unused)) dev = devlink_priv(devlink);
+	struct dh_core_dev *__attribute__((unused)) dev = devlink_priv(devlink);
 
-    return 0;
+	return 0;
 }
 
 #ifdef HAVE_DEVLINK_PARAM_REGISTER
 static const struct devlink_params {
-    const char *name;
-    int32_t (*check)(struct dh_core_dev *dev);
-    struct devlink_param param;
-} devlink_params[] = {
-    [DH_SF_PARAMS_MAX] = { .name = "sample",
-                           .check = &sample_check,
-                           .param = DEVLINK_PARAM_DRIVER(DH_SF_DEVLINK_PARAM_ID_SAMPLE,
-                                                          "sample", DEVLINK_PARAM_TYPE_BOOL,
-                                                          BIT(DEVLINK_PARAM_CMODE_RUNTIME),dh_devlink_sample_get,
-                                                          dh_devlink_sample_set,
-                                                          NULL),
-                          }
-};
+	const char *name;
+	int32_t (*check)(struct dh_core_dev *dev);
+	struct devlink_param param;
+} devlink_params[] = { [DH_SF_PARAMS_MAX] = {
+							   .name = "sample",
+							   .check = &sample_check,
+							   .param = DEVLINK_PARAM_DRIVER(
+									   DH_SF_DEVLINK_PARAM_ID_SAMPLE, "sample",
+									   DEVLINK_PARAM_TYPE_BOOL,
+									   BIT(DEVLINK_PARAM_CMODE_RUNTIME),
+									   dh_devlink_sample_get,
+									   dh_devlink_sample_set, NULL),
+					   } };
 
 static int32_t params_register(struct devlink *devlink)
 {
-    int32_t i = 0;
-    int32_t err = 0;
-    struct dh_core_dev *dh_dev = devlink_priv(devlink);
-
-    for (i = 0; i < ARRAY_SIZE(devlink_params); i++)
-    {
-        if(devlink_params[i].check(dh_dev))
-        {
-            err = devlink_param_register(devlink, &devlink_params[i].param);
-            if (err)
-            {
-               goto rollback;
-            }
-        }
-    }
-
-    return 0;
+	int32_t i = 0;
+	int32_t err = 0;
+	struct dh_core_dev *dh_dev = devlink_priv(devlink);
+
+	for (i = 0; i < ARRAY_SIZE(devlink_params); i++) {
+		if (devlink_params[i].check(dh_dev)) {
+			err = devlink_param_register(devlink, &devlink_params[i].param);
+			if (err) {
+				goto rollback;
+			}
+		}
+	}
+
+	return 0;
 
 rollback:
-    if (i == 0)
-    {
-        return err;
-    }
+	if (i == 0) {
+		return err;
+	}
 
-    for (; i > 0; i--)
-    {
-        devlink_param_unregister(devlink, &devlink_params[i].param);
-    }
+	for (; i > 0; i--) {
+		devlink_param_unregister(devlink, &devlink_params[i].param);
+	}
 
-    return err;
+	return err;
 }
 
 static int32_t params_unregister(struct devlink *devlink)
 {
-    int32_t i = 0;
+	int32_t i = 0;
 
-    for (i = 0; i < ARRAY_SIZE(devlink_params); i++)
-    {
-        devlink_param_unregister(devlink, &devlink_params[i].param);
-    }
+	for (i = 0; i < ARRAY_SIZE(devlink_params); i++) {
+		devlink_param_unregister(devlink, &devlink_params[i].param);
+	}
 
-    return 0;
+	return 0;
 }
-#else 
-static struct devlink_param devlink_params [] = {
-    [DH_SF_PARAMS_MAX] = DEVLINK_PARAM_DRIVER(DH_SF_DEVLINK_PARAM_ID_SAMPLE,
-                                                          "sample", DEVLINK_PARAM_TYPE_BOOL,
-                                                          BIT(DEVLINK_PARAM_CMODE_RUNTIME),dh_devlink_sample_get,
-                                                          dh_devlink_sample_set,
-                                                          NULL),
+#else
+static struct devlink_param devlink_params[] = {
+	[DH_SF_PARAMS_MAX] = DEVLINK_PARAM_DRIVER(
+			DH_SF_DEVLINK_PARAM_ID_SAMPLE, "sample", DEVLINK_PARAM_TYPE_BOOL,
+			BIT(DEVLINK_PARAM_CMODE_RUNTIME), dh_devlink_sample_get,
+			dh_devlink_sample_set, NULL),
 };
 
 static int32_t params_register(struct devlink *devlink)
 {
-    struct dh_core_dev * __attribute__((unused)) dh_dev = devlink_priv(devlink);
-    int32_t err = 0;
+	struct dh_core_dev *__attribute__((unused)) dh_dev = devlink_priv(devlink);
+	int32_t err = 0;
 
-    err = devlink_params_register(devlink, devlink_params, ARRAY_SIZE(devlink_params));
+	err = devlink_params_register(devlink, devlink_params,
+								  ARRAY_SIZE(devlink_params));
 
-    return err;
+	return err;
 }
 static int32_t params_unregister(struct devlink *devlink)
 {
-    devlink_params_unregister(devlink, devlink_params, ARRAY_SIZE(devlink_params));
+	devlink_params_unregister(devlink, devlink_params,
+							  ARRAY_SIZE(devlink_params));
 
-    return 0;
+	return 0;
 }
 #endif
 
 struct dh_core_devlink_ops dh_sf_core_devlink_ops = {
-    .params_register   =  params_register,
-    .params_unregister =  params_unregister
+	.params_register = params_register,
+	.params_unregister = params_unregister
 };
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/en_sf/devlink.h b/src/net/drivers/net/ethernet/dinghai/en_sf/devlink.h
index 6622934ed8aa90d5f38bae4b7d4d9bb878c6a8a3..0204d258cde7b226b027b03f63a4f360542ab129 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_sf/devlink.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_sf/devlink.h
@@ -7,7 +7,6 @@ extern "C" {
 
 #include <linux/dinghai/devlink.h>
 
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_sf/eq.c b/src/net/drivers/net/ethernet/dinghai/en_sf/eq.c
index 1999aa431c96826da1401ef6bff98b0588f7958e..6579b366164216f51a4b2659b4409e6a7643e855 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_sf/eq.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_sf/eq.c
@@ -1,391 +1,399 @@
-#include <linux/dinghai/eq.h>
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/helper.h>
-#include <linux/list.h>
-#include <linux/dinghai/en_sf.h>
-#include <linux/dinghai/queue.h>
-#include "irq.h"
-#include "eq.h"
-#include "../en_sf.h"
-
-
-static int32_t create_async_eqs(struct dh_core_dev *dev)
-{
-    return 0;
-}
-
-int32_t dh_en_sf_eq_table_create(struct dh_core_dev *dev, struct zxdh_en_sf_if *ops)
-{
-    int32_t err;
-
-    err = create_async_eqs(dev);
-
-    return err;
-}
-
-void dh_sf_eq_table_destroy(struct dh_core_dev *dev)
-{
-    return;
-}
-
-void zxdh_set_queue_size(struct dh_core_dev *dh_dev, uint32_t index, uint16_t size)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_set_queue_size(dh_dev->parent, index, size);
-}
-
-void zxdh_queue_address(struct dh_core_dev *dh_dev, uint32_t index,
-                        uint64_t desc_addr, uint64_t driver_addr, uint64_t device_addr)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_set_queue_address(dh_dev->parent, index, desc_addr, driver_addr, device_addr);
-}
-
-void zxdh_en_sf_activate_phy_vq(struct dh_core_dev *dh_dev, uint32_t phy_index, int32_t queue_size, uint64_t desc_addr, uint64_t avail_addr, uint64_t used_addr)
-{
-    zxdh_set_queue_size(dh_dev, phy_index, queue_size);
-    zxdh_queue_address(dh_dev, phy_index, desc_addr, avail_addr, used_addr);
-}
-
-int32_t dh_en_sf_eq_table_init(struct dh_core_dev *dev)
-{
-    struct dh_eq_table *eq_table = &dev->eq_table;
-    struct dh_en_sf_eq_table *table_priv = NULL;
-    int32_t err = 0;
-
-    table_priv = kvzalloc(sizeof(*table_priv), GFP_KERNEL);
-    if (unlikely(table_priv == NULL))
-    {
-        LOG_ERR("dh_en_sf_eq_table kvzalloc failed\n");
-        err = -ENOMEM;
-        goto err_table_priv;
-    }
-    dh_eq_table_init(dev, table_priv);
-
-    return 0;
-
-err_table_priv:
-    kvfree(eq_table);
-    return err;
-}
-
-static void vqs_irqs_release(struct dh_core_dev *dh_dev)
-{
-    struct dh_eq_table *table = &dh_dev->eq_table;
-    struct dh_en_sf_eq_table *sf_eq_table = table->priv;
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-    int32_t vqs_channel_num = 0;
-
-    vqs_channel_num = zxdh_en_sf_get_vqs_channels_num(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_affinity_irqs_release(dh_dev->parent, sf_eq_table->vq_irqs, vqs_channel_num);
-
-    dh_irqs_release_vectors(sf_eq_table->vq_irqs, sf_eq_table->vq_irq_num);
-}
-
-static void clean_vqs_eqs(struct dh_core_dev *dh_dev)
-{
-    struct dh_eq_table *table = &dh_dev->eq_table;
-    struct dh_en_sf_eq_table *sf_eq_table = table->priv;
-    struct dh_eq_vqs *eq;
-    struct dh_eq_vqs *n;
-
-    list_for_each_entry_safe(eq, n, &sf_eq_table->vqs_eqs_list, list)
-    {
-        list_del(&eq->list);
-        kfree(eq);
-    }
-}
-
-static void destroy_vqs_eqs(struct dh_core_dev *dh_dev, int32_t vqs_channel_num)
-{
-    struct dh_eq_table *table = &dh_dev->eq_table;
-    struct dh_en_sf_eq_table *sf_eq_table = table->priv;
-    struct dh_eq_vqs *eq;
-    struct dh_eq_vqs *n;
-    int32_t i = 0;
-
-    list_for_each_entry_safe(eq, n, &sf_eq_table->vqs_eqs_list, list)
-    {
-        if (i <= vqs_channel_num)
-        {
-            dh_eq_disable(dh_dev, &eq->vq_s.core, &eq->vq_s.irq_nb);
-        }
-        i++;
-    }
-}
-
-uint16_t zxdh_en_sf_get_vqs_channels_num(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-    uint16_t channels_num = 0;
-
-    channels_num = en_sf_dev->sf_ops->en_sf_get_channels_num(dh_dev->parent);
-
-    return channels_num;
-}
-
-static int32_t create_map_eq(struct dh_core_dev *dev, struct dh_eq *eq, struct dh_eq_param *param)
-{
-    eq->irq = param->irq;
-
-    return 0;
-}
-
-void zxdh_en_sf_destroy_vqs_channels(struct dh_core_dev *dh_dev)
-{
-    struct dh_eq_table *table = &dh_dev->eq_table;
-    struct dh_en_sf_eq_table *sf_eq_table = table->priv;
-
-    clean_vqs_eqs(dh_dev);
-    vqs_irqs_release(dh_dev);
-    kfree(sf_eq_table->vq_irqs);
-}
-
-void zxdh_en_sf_switch_vqs_channel(struct dh_core_dev *dh_dev, int32_t channel, int32_t op)
-{
-    struct dh_eq_table *table = &dh_dev->eq_table;
-    struct dh_en_sf_eq_table *sf_eq_table = table->priv;
-    struct dh_irq *irq = sf_eq_table->vq_irqs[channel];
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_switch_irq(dh_dev->parent, irq->irqn, op);
-}
-
-int32_t zxdh_en_sf_create_vqs_channels(struct dh_core_dev *dh_dev)
-{
-    struct dh_eq_table *table = &dh_dev->eq_table;
-    struct dh_en_sf_eq_table *sf_eq_table = table->priv;
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-    int32_t vqs_channel_num = 0;
-    int32_t i = 0;
-    struct dh_eq_vqs *eq_vqs = NULL;
-    int32_t err = 0;
-
-    vqs_channel_num = zxdh_en_sf_get_vqs_channels_num(dh_dev);
-
-    sf_eq_table->vq_irqs = kcalloc(vqs_channel_num, sizeof(*sf_eq_table->vq_irqs), GFP_KERNEL);
-    if (unlikely(sf_eq_table->vq_irqs == NULL))
-    {
-        LOG_ERR("sf_eq_table->vq_irqs kcalloc null\n");
-        return -ENOMEM;
-    }
-
-    vqs_channel_num = en_sf_dev->sf_ops->en_sf_vq_irqs_request(dh_dev->parent, sf_eq_table->vq_irqs, vqs_channel_num);
-    if (vqs_channel_num < 0)
-    {
-        LOG_ERR("en_sf_vq_irqs_request failed: %d\n", vqs_channel_num);
-        kfree(sf_eq_table->vq_irqs);
-        return vqs_channel_num;
-    }
-
-    sf_eq_table->vq_irq_num = vqs_channel_num;
-
-    INIT_LIST_HEAD(&sf_eq_table->vqs_eqs_list);
-
-    for (i = 0; i < vqs_channel_num; i++)
-    {
-        eq_vqs  = kzalloc(sizeof(struct dh_eq_vqs), GFP_KERNEL);
-        if (unlikely(eq_vqs == NULL))
-        {
-            LOG_ERR("eq_vqs %d kzalloc null\n", i);
-            err = -ENOMEM;
-            goto clean;
-        }
-
-        INIT_LIST_HEAD(&eq_vqs->vqs);
-
-        list_add_tail(&eq_vqs->list, &sf_eq_table->vqs_eqs_list);
-    }
-
-    return vqs_channel_num;
-
-clean:
-    zxdh_en_sf_destroy_vqs_channels(dh_dev);
-    return err;
-}
-
-void zxdh_en_sf_vqs_unbind_eqs(struct dh_core_dev *dh_dev, int32_t vqs_channel_num)
-{
-    struct dh_eq_table *table = &dh_dev->eq_table;
-    struct dh_en_sf_eq_table *sf_eq_table = table->priv;
-    struct dh_eq_vqs *eq;
-    struct dh_eq_vqs *n;
-    int32_t i = 0;
-
-    list_for_each_entry_safe(eq, n, &sf_eq_table->vqs_eqs_list, list)
-    {
-        if (i++ <= vqs_channel_num)
-        {
-            list_del(&eq->vqs);
-        }
-    }
-
-    return;
-}
-
-int32_t zxdh_en_sf_vqs_bind_eqs(struct dh_core_dev *dh_dev, int32_t vqs_channel_num, struct list_head *vq_node)
-{
-    struct dh_eq_table *table = &dh_dev->eq_table;
-    struct dh_en_sf_eq_table *sf_eq_table = table->priv;
-    struct dh_eq_vqs *eq;
-    struct dh_eq_vqs *n;
-    int32_t i = 0;
-
-    list_for_each_entry_safe(eq, n, &sf_eq_table->vqs_eqs_list, list)
-    {
-        if (i++ == vqs_channel_num)
-        {
-            list_add_tail(vq_node, &eq->vqs);
-            return 0;
-        }
-    }
-
-    return -ENOENT;
-}
-
-void __iomem *zxdh_en_sf_map_vq_notify(struct dh_core_dev *dh_dev, uint32_t index, resource_size_t *pa)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-    void __iomem *notify_addr = NULL;
-
-    notify_addr = en_sf_dev->sf_ops->en_sf_map_vq_notify(dh_dev->parent, index, pa);
-
-    return notify_addr;
-}
-
-void zxdh_en_sf_unmap_vq_notify(struct dh_core_dev *dh_dev, void *priv)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_unmap_vq_notify(dh_dev->parent, priv);
-}
-
-void zxdh_en_sf_set_queue_enable(struct dh_core_dev *dh_dev, uint16_t index, bool enable)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_set_queue_enable(dh_dev->parent, index, enable);
-}
-
-uint16_t zxdh_en_sf_get_queue_vector(struct dh_core_dev *dh_dev, uint16_t channel, uint16_t queue_index)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-    struct dh_eq_table *table = &dh_dev->eq_table;
-    struct dh_en_sf_eq_table *sf_eq_table = table->priv;
-    int32_t msix_vec = ZXDH_MSI_NO_VECTOR;
-
-    msix_vec = en_sf_dev->sf_ops->en_sf_get_queue_vector(dh_dev->parent, channel, &sf_eq_table->vqs_eqs_list, queue_index);
-
-    return msix_vec;
-}
-
-void zxdh_en_sf_vq_unbind_channel(struct dh_core_dev *dh_dev, int32_t queue_index)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    en_sf_dev->sf_ops->en_sf_release_queue_vector(dh_dev->parent, queue_index);
-}
-
-int32_t zxdh_en_sf_vq_bind_channel(struct dh_core_dev *dh_dev, int32_t channel_num, int32_t queue_index)
-{
-    int32_t msix_vec = ZXDH_MSI_NO_VECTOR;
-
-    msix_vec = zxdh_en_sf_get_queue_vector(dh_dev, channel_num, queue_index);
-
-    if (msix_vec == ZXDH_MSI_NO_VECTOR)
-    {
-        return -EBUSY;
-    }
-
-    return msix_vec;
-}
-
-void zxdh_en_sf_vqs_channel_unbind_handler(struct dh_core_dev *dh_dev, int32_t vqs_channel_num)
-{
-    destroy_vqs_eqs(dh_dev, vqs_channel_num);
-    return;
-}
-
-int32_t zxdh_en_sf_vqs_channel_bind_handler(struct dh_core_dev *dh_dev, int32_t vqs_channel_num, struct dh_vq_handler *handler)
-{
-    struct dh_eq_table *table = &dh_dev->eq_table;
-    struct dh_en_sf_eq_table *sf_eq_table = table->priv;
-    int32_t i = 0;
-    struct dh_eq_vqs *eq_vqs;
-    struct dh_eq_vqs *n;
-    int32_t err = 0;
-
-    list_for_each_entry_safe(eq_vqs, n, &sf_eq_table->vqs_eqs_list, list)
-    {
-        if (i == vqs_channel_num)
-        {
-            struct dh_eq_param param = {};
-
-            eq_vqs->vq_s.irq_nb.notifier_call = handler->callback;
-            eq_vqs->vq_s.para = handler->para;
-            param = (struct dh_eq_param) {
-                .irq = sf_eq_table->vq_irqs[i],
-                .nent = 0,
-            };
-            create_map_eq(dh_dev, &eq_vqs->vq_s.core, &param);
-
-            err = dh_eq_enable(dh_dev, &eq_vqs->vq_s.core, &eq_vqs->vq_s.irq_nb);
-            if(err != 0)
-            {
-                LOG_ERR("dh_eq_enable failed: %d\n", err);
-                goto clean_eq;
-            }
-            return 0;
-        }
-        i++;
-    }
-
-clean_eq:
-    destroy_vqs_eqs(dh_dev, vqs_channel_num);
-    return err;
-}
-
-uint32_t zxdh_en_sf_get_epbdf(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_get_epbdf(dh_dev->parent);
-}
-
-uint16_t zxdh_en_sf_get_vport(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_get_vport(dh_dev->parent);
-}
-
-enum dh_coredev_type zxdh_en_sf_get_coredev_type(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_get_coredev_type(dh_dev->parent);
-}
-
-uint16_t zxdh_en_sf_get_pcie_id(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_get_pcie_id(dh_dev->parent);
-}
-
-uint16_t zxdh_en_sf_get_slot_id(struct dh_core_dev *dh_dev)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_get_slot_id(dh_dev->parent);
-}
-
-struct zxdh_vf_item *zxdh_en_sf_get_vf_item(struct dh_core_dev *dh_dev, uint16_t vf_idx)
-{
-    struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
-
-    return en_sf_dev->sf_ops->en_sf_get_vf_item(dh_dev->parent, vf_idx);
-}
+#include <linux/dinghai/eq.h>
+#include <linux/dinghai/driver.h>
+#include <linux/dinghai/helper.h>
+#include <linux/list.h>
+#include <linux/dinghai/en_sf.h>
+#include <linux/dinghai/queue.h>
+#include "irq.h"
+#include "eq.h"
+#include "../en_sf.h"
+
+static int32_t create_async_eqs(struct dh_core_dev *dev)
+{
+	return 0;
+}
+
+int32_t dh_en_sf_eq_table_create(struct dh_core_dev *dev,
+								 struct zxdh_en_sf_if *ops)
+{
+	int32_t err;
+
+	err = create_async_eqs(dev);
+
+	return err;
+}
+
+void dh_sf_eq_table_destroy(struct dh_core_dev *dev)
+{
+	return;
+}
+
+void zxdh_set_queue_size(struct dh_core_dev *dh_dev, uint32_t index,
+						 uint16_t size)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_set_queue_size(dh_dev->parent, index, size);
+}
+
+void zxdh_queue_address(struct dh_core_dev *dh_dev, uint32_t index,
+						uint64_t desc_addr, uint64_t driver_addr,
+						uint64_t device_addr)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_set_queue_address(dh_dev->parent, index, desc_addr,
+											   driver_addr, device_addr);
+}
+
+void zxdh_en_sf_activate_phy_vq(struct dh_core_dev *dh_dev, uint32_t phy_index,
+								int32_t queue_size, uint64_t desc_addr,
+								uint64_t avail_addr, uint64_t used_addr)
+{
+	zxdh_set_queue_size(dh_dev, phy_index, queue_size);
+	zxdh_queue_address(dh_dev, phy_index, desc_addr, avail_addr, used_addr);
+}
+
+int32_t dh_en_sf_eq_table_init(struct dh_core_dev *dev)
+{
+	struct dh_eq_table *eq_table = &dev->eq_table;
+	struct dh_en_sf_eq_table *table_priv = NULL;
+	int32_t err = 0;
+
+	table_priv = kvzalloc(sizeof(*table_priv), GFP_KERNEL);
+	if (unlikely(table_priv == NULL)) {
+		err = -ENOMEM;
+		goto err_table_priv;
+	}
+	dh_eq_table_init(dev, table_priv);
+
+	return 0;
+
+err_table_priv:
+	kvfree(eq_table);
+	return err;
+}
+
+static void vqs_irqs_release(struct dh_core_dev *dh_dev)
+{
+	struct dh_eq_table *table = &dh_dev->eq_table;
+	struct dh_en_sf_eq_table *sf_eq_table = table->priv;
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+	int32_t vqs_channel_num = 0;
+
+	vqs_channel_num = zxdh_en_sf_get_vqs_channels_num(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_affinity_irqs_release(
+			dh_dev->parent, sf_eq_table->vq_irqs, vqs_channel_num);
+
+	dh_irqs_release_vectors(sf_eq_table->vq_irqs, sf_eq_table->vq_irq_num);
+}
+
+static void clean_vqs_eqs(struct dh_core_dev *dh_dev)
+{
+	struct dh_eq_table *table = &dh_dev->eq_table;
+	struct dh_en_sf_eq_table *sf_eq_table = table->priv;
+	struct dh_eq_vqs *eq;
+	struct dh_eq_vqs *n;
+
+	list_for_each_entry_safe(eq, n, &sf_eq_table->vqs_eqs_list, list) {
+		list_del(&eq->list);
+		kfree(eq);
+	}
+}
+
+static void destroy_vqs_eqs(struct dh_core_dev *dh_dev, int32_t vqs_channel_num)
+{
+	struct dh_eq_table *table = &dh_dev->eq_table;
+	struct dh_en_sf_eq_table *sf_eq_table = table->priv;
+	struct dh_eq_vqs *eq;
+	struct dh_eq_vqs *n;
+	int32_t i = 0;
+
+	list_for_each_entry_safe(eq, n, &sf_eq_table->vqs_eqs_list, list) {
+		if (i <= vqs_channel_num) {
+			dh_eq_disable(dh_dev, &eq->vq_s.core, &eq->vq_s.irq_nb);
+		}
+		i++;
+	}
+}
+
+uint16_t zxdh_en_sf_get_vqs_channels_num(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+	uint16_t channels_num = 0;
+
+	channels_num = en_sf_dev->sf_ops->en_sf_get_channels_num(dh_dev->parent);
+
+	return channels_num;
+}
+
+static int32_t create_map_eq(struct dh_core_dev *dev, struct dh_eq *eq,
+							 struct dh_eq_param *param)
+{
+	eq->irq = param->irq;
+
+	return 0;
+}
+
+void zxdh_en_sf_destroy_vqs_channels(struct dh_core_dev *dh_dev)
+{
+	struct dh_eq_table *table = &dh_dev->eq_table;
+	struct dh_en_sf_eq_table *sf_eq_table = table->priv;
+
+	clean_vqs_eqs(dh_dev);
+	vqs_irqs_release(dh_dev);
+	kfree(sf_eq_table->vq_irqs);
+}
+
+void zxdh_en_sf_switch_vqs_channel(struct dh_core_dev *dh_dev, int32_t channel,
+								   int32_t op)
+{
+	struct dh_eq_table *table = &dh_dev->eq_table;
+	struct dh_en_sf_eq_table *sf_eq_table = table->priv;
+	struct dh_irq *irq = sf_eq_table->vq_irqs[channel];
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_switch_irq(dh_dev->parent, irq->irqn, op);
+}
+
+int32_t zxdh_en_sf_create_vqs_channels(struct dh_core_dev *dh_dev)
+{
+	struct dh_eq_table *table = &dh_dev->eq_table;
+	struct dh_en_sf_eq_table *sf_eq_table = table->priv;
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+	int32_t vqs_channel_num = 0;
+	int32_t i = 0;
+	struct dh_eq_vqs *eq_vqs = NULL;
+	int32_t err = 0;
+
+	vqs_channel_num = zxdh_en_sf_get_vqs_channels_num(dh_dev);
+
+	sf_eq_table->vq_irqs =
+			kcalloc(vqs_channel_num, sizeof(*sf_eq_table->vq_irqs), GFP_KERNEL);
+	if (unlikely(sf_eq_table->vq_irqs == NULL)) {
+		LOG_ERR("sf_eq_table->vq_irqs kcalloc null\n");
+		return -ENOMEM;
+	}
+
+	vqs_channel_num = en_sf_dev->sf_ops->en_sf_vq_irqs_request(
+			dh_dev->parent, sf_eq_table->vq_irqs, vqs_channel_num);
+	if (vqs_channel_num < 0) {
+		LOG_ERR("en_sf_vq_irqs_request failed: %d\n", vqs_channel_num);
+		kfree(sf_eq_table->vq_irqs);
+		return vqs_channel_num;
+	}
+
+	sf_eq_table->vq_irq_num = vqs_channel_num;
+
+	INIT_LIST_HEAD(&sf_eq_table->vqs_eqs_list);
+
+	for (i = 0; i < vqs_channel_num; i++) {
+		eq_vqs = kzalloc(sizeof(struct dh_eq_vqs), GFP_KERNEL);
+		if (unlikely(eq_vqs == NULL)) {
+			LOG_ERR("eq_vqs %d kzalloc null\n", i);
+			err = -ENOMEM;
+			goto clean;
+		}
+
+		INIT_LIST_HEAD(&eq_vqs->vqs);
+
+		list_add_tail(&eq_vqs->list, &sf_eq_table->vqs_eqs_list);
+	}
+
+	return vqs_channel_num;
+
+clean:
+	zxdh_en_sf_destroy_vqs_channels(dh_dev);
+	return err;
+}
+
+void zxdh_en_sf_vqs_unbind_eqs(struct dh_core_dev *dh_dev,
+							   int32_t vqs_channel_num)
+{
+	struct dh_eq_table *table = &dh_dev->eq_table;
+	struct dh_en_sf_eq_table *sf_eq_table = table->priv;
+	struct dh_eq_vqs *eq;
+	struct dh_eq_vqs *n;
+	int32_t i = 0;
+
+	list_for_each_entry_safe(eq, n, &sf_eq_table->vqs_eqs_list, list) {
+		if (i++ <= vqs_channel_num) {
+			list_del(&eq->vqs);
+		}
+	}
+
+	return;
+}
+
+int32_t zxdh_en_sf_vqs_bind_eqs(struct dh_core_dev *dh_dev,
+								int32_t vqs_channel_num,
+								struct list_head *vq_node)
+{
+	struct dh_eq_table *table = &dh_dev->eq_table;
+	struct dh_en_sf_eq_table *sf_eq_table = table->priv;
+	struct dh_eq_vqs *eq;
+	struct dh_eq_vqs *n;
+	int32_t i = 0;
+
+	list_for_each_entry_safe(eq, n, &sf_eq_table->vqs_eqs_list, list) {
+		if (i++ == vqs_channel_num) {
+			list_add_tail(vq_node, &eq->vqs);
+			return 0;
+		}
+	}
+
+	return -ENOENT;
+}
+
+void __iomem *zxdh_en_sf_map_vq_notify(struct dh_core_dev *dh_dev,
+									   uint32_t index, resource_size_t *pa)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+	void __iomem *notify_addr = NULL;
+
+	notify_addr =
+			en_sf_dev->sf_ops->en_sf_map_vq_notify(dh_dev->parent, index, pa);
+
+	return notify_addr;
+}
+
+void zxdh_en_sf_unmap_vq_notify(struct dh_core_dev *dh_dev, void *priv)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_unmap_vq_notify(dh_dev->parent, priv);
+}
+
+void zxdh_en_sf_set_queue_enable(struct dh_core_dev *dh_dev, uint16_t index,
+								 bool enable)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_set_queue_enable(dh_dev->parent, index, enable);
+}
+
+uint16_t zxdh_en_sf_get_queue_vector(struct dh_core_dev *dh_dev,
+									 uint16_t channel, uint16_t queue_index)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+	struct dh_eq_table *table = &dh_dev->eq_table;
+	struct dh_en_sf_eq_table *sf_eq_table = table->priv;
+	int32_t msix_vec = ZXDH_MSI_NO_VECTOR;
+
+	msix_vec = en_sf_dev->sf_ops->en_sf_get_queue_vector(
+			dh_dev->parent, channel, &sf_eq_table->vqs_eqs_list, queue_index);
+
+	return msix_vec;
+}
+
+void zxdh_en_sf_vq_unbind_channel(struct dh_core_dev *dh_dev,
+								  int32_t queue_index)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	en_sf_dev->sf_ops->en_sf_release_queue_vector(dh_dev->parent, queue_index);
+}
+
+int32_t zxdh_en_sf_vq_bind_channel(struct dh_core_dev *dh_dev,
+								   int32_t channel_num, int32_t queue_index)
+{
+	int32_t msix_vec = ZXDH_MSI_NO_VECTOR;
+
+	msix_vec = zxdh_en_sf_get_queue_vector(dh_dev, channel_num, queue_index);
+
+	if (msix_vec == ZXDH_MSI_NO_VECTOR) {
+		return -EBUSY;
+	}
+
+	return msix_vec;
+}
+
+void zxdh_en_sf_vqs_channel_unbind_handler(struct dh_core_dev *dh_dev,
+										   int32_t vqs_channel_num)
+{
+	destroy_vqs_eqs(dh_dev, vqs_channel_num);
+	return;
+}
+
+int32_t zxdh_en_sf_vqs_channel_bind_handler(struct dh_core_dev *dh_dev,
+											int32_t vqs_channel_num,
+											struct dh_vq_handler *handler)
+{
+	struct dh_eq_table *table = &dh_dev->eq_table;
+	struct dh_en_sf_eq_table *sf_eq_table = table->priv;
+	int32_t i = 0;
+	struct dh_eq_vqs *eq_vqs;
+	struct dh_eq_vqs *n;
+	int32_t err = 0;
+
+	list_for_each_entry_safe(eq_vqs, n, &sf_eq_table->vqs_eqs_list, list) {
+		if (i == vqs_channel_num) {
+			struct dh_eq_param param = {};
+
+			eq_vqs->vq_s.irq_nb.notifier_call = handler->callback;
+			eq_vqs->vq_s.para = handler->para;
+			param = (struct dh_eq_param){
+				.irq = sf_eq_table->vq_irqs[i],
+				.nent = 0,
+			};
+			create_map_eq(dh_dev, &eq_vqs->vq_s.core, &param);
+
+			err = dh_eq_enable(dh_dev, &eq_vqs->vq_s.core,
+							   &eq_vqs->vq_s.irq_nb);
+			if (err != 0) {
+				LOG_ERR("dh_eq_enable failed: %d\n", err);
+				goto clean_eq;
+			}
+			return 0;
+		}
+		i++;
+	}
+
+clean_eq:
+	destroy_vqs_eqs(dh_dev, vqs_channel_num);
+	return err;
+}
+
+uint32_t zxdh_en_sf_get_epbdf(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_get_epbdf(dh_dev->parent);
+}
+
+uint16_t zxdh_en_sf_get_vport(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_get_vport(dh_dev->parent);
+}
+
+enum dh_coredev_type zxdh_en_sf_get_coredev_type(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_get_coredev_type(dh_dev->parent);
+}
+
+uint16_t zxdh_en_sf_get_pcie_id(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_get_pcie_id(dh_dev->parent);
+}
+
+uint16_t zxdh_en_sf_get_slot_id(struct dh_core_dev *dh_dev)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_get_slot_id(dh_dev->parent);
+}
+
+struct zxdh_vf_item *zxdh_en_sf_get_vf_item(struct dh_core_dev *dh_dev,
+											uint16_t vf_idx)
+{
+	struct zxdh_en_sf_device *en_sf_dev = dh_core_priv(dh_dev);
+
+	return en_sf_dev->sf_ops->en_sf_get_vf_item(dh_dev->parent, vf_idx);
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_sf/eq.h b/src/net/drivers/net/ethernet/dinghai/en_sf/eq.h
index 1f6127e276ddcfc91af49c64110f56020ee5ce47..fb8bd502f7b3bc4bb0eefefea7cc524d753f5f1c 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_sf/eq.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_sf/eq.h
@@ -1,57 +1,75 @@
-#ifndef __ZXDH_SF_EQ_H__
-#define __ZXDH_SF_EQ_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/driver.h>
-#include <linux/notifier.h>
-#include <linux/types.h>
-#include <linux/dinghai/pci_irq.h>
-#include <linux/dinghai/eq.h>
-#include <linux/dinghai/en_sf.h>
-
-void dh_en_sf_eq_table_destroy(struct dh_core_dev *dev);
-int32_t dh_en_sf_eq_table_init(struct dh_core_dev *dev);
-int32_t dh_en_sf_eq_table_create(struct dh_core_dev *dev, struct zxdh_en_sf_if *ops);
-void dh_sf_eq_table_destroy(struct dh_core_dev *dev);
-
-uint16_t zxdh_en_sf_get_vqs_channels_num(struct dh_core_dev *dh_dev);
-int32_t zxdh_en_sf_create_vqs_channels(struct dh_core_dev *dh_dev);
-void zxdh_en_sf_destroy_vqs_channels(struct dh_core_dev *dh_dev);
-void zxdh_en_sf_switch_vqs_channel(struct dh_core_dev *dh_dev, int32_t channel, int32_t op);
-int32_t zxdh_en_sf_vqs_channel_bind_handler(struct dh_core_dev *dh_dev, int32_t vqs_channel_num, struct dh_vq_handler *handler);
-void zxdh_en_sf_vqs_channel_unbind_handler(struct dh_core_dev *dh_dev, int32_t vqs_channel_num);
-int32_t zxdh_en_sf_vq_bind_channel(struct dh_core_dev *dh_dev, int32_t channel_num, int32_t queue_index);
-void zxdh_en_sf_vq_unbind_channel(struct dh_core_dev *dh_dev, int32_t queue_index);
-int32_t zxdh_en_sf_vqs_bind_eqs(struct dh_core_dev *dh_dev, int32_t vqs_channel_num, struct list_head *vq_node);
-void zxdh_en_sf_vqs_unbind_eqs(struct dh_core_dev *dh_dev, int32_t vqs_channel_num);
-void __iomem *zxdh_en_sf_map_vq_notify(struct dh_core_dev *dh_dev, uint32_t index, resource_size_t *pa);
-void zxdh_en_sf_unmap_vq_notify(struct dh_core_dev *dh_dev, void *priv);
-void zxdh_en_sf_activate_phy_vq(struct dh_core_dev *dh_dev, uint32_t phy_index, int32_t queue_size, uint64_t desc_addr, uint64_t avail_addr, uint64_t used_addr);
-void zxdh_en_sf_set_queue_enable(struct dh_core_dev *dh_dev, uint16_t index, bool enable);
-uint32_t zxdh_en_sf_get_epbdf(struct dh_core_dev *dh_dev);
-uint16_t zxdh_en_sf_get_vport(struct dh_core_dev *dh_dev);
-uint16_t zxdh_en_sf_get_pcie_id(struct dh_core_dev *dh_dev);
-uint16_t zxdh_en_sf_get_slot_id(struct dh_core_dev *dh_dev);
-enum dh_coredev_type zxdh_en_sf_get_coredev_type(struct dh_core_dev *dh_dev);
-void zxdh_en_sf_dpp_np_init(struct dh_core_dev *dh_dev, uint32_t vport);
-struct pci_dev *zxdh_en_sf_get_pdev(struct dh_core_dev *dh_dev);
-uint64_t zxdh_en_sf_get_bar_virt_addr(struct dh_core_dev *dh_dev, uint8_t bar_num);
-int32_t zxdh_en_sf_do_cmd_exec(struct dh_core_dev *dh_dev, uint32_t dst, uint32_t id, uint32_t len, void *payload, void *ack);
-struct zxdh_vf_item *zxdh_en_sf_get_vf_item(struct dh_core_dev *dh_dev, uint16_t vf_idx);
-
-struct dh_en_sf_eq_table {
-    struct dh_irq **vq_irqs;
-    struct dh_irq *async_irq;
-    struct dh_eq_async async_eq;
-    int32_t vq_irq_num;
-    struct list_head vqs_eqs_list;
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef __ZXDH_SF_EQ_H__
+#define __ZXDH_SF_EQ_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/driver.h>
+#include <linux/notifier.h>
+#include <linux/types.h>
+#include <linux/dinghai/pci_irq.h>
+#include <linux/dinghai/eq.h>
+#include <linux/dinghai/en_sf.h>
+
+void dh_en_sf_eq_table_destroy(struct dh_core_dev *dev);
+int32_t dh_en_sf_eq_table_init(struct dh_core_dev *dev);
+int32_t dh_en_sf_eq_table_create(struct dh_core_dev *dev,
+								 struct zxdh_en_sf_if *ops);
+void dh_sf_eq_table_destroy(struct dh_core_dev *dev);
+
+uint16_t zxdh_en_sf_get_vqs_channels_num(struct dh_core_dev *dh_dev);
+int32_t zxdh_en_sf_create_vqs_channels(struct dh_core_dev *dh_dev);
+void zxdh_en_sf_destroy_vqs_channels(struct dh_core_dev *dh_dev);
+void zxdh_en_sf_switch_vqs_channel(struct dh_core_dev *dh_dev, int32_t channel,
+								   int32_t op);
+int32_t zxdh_en_sf_vqs_channel_bind_handler(struct dh_core_dev *dh_dev,
+											int32_t vqs_channel_num,
+											struct dh_vq_handler *handler);
+void zxdh_en_sf_vqs_channel_unbind_handler(struct dh_core_dev *dh_dev,
+										   int32_t vqs_channel_num);
+int32_t zxdh_en_sf_vq_bind_channel(struct dh_core_dev *dh_dev,
+								   int32_t channel_num, int32_t queue_index);
+void zxdh_en_sf_vq_unbind_channel(struct dh_core_dev *dh_dev,
+								  int32_t queue_index);
+int32_t zxdh_en_sf_vqs_bind_eqs(struct dh_core_dev *dh_dev,
+								int32_t vqs_channel_num,
+								struct list_head *vq_node);
+void zxdh_en_sf_vqs_unbind_eqs(struct dh_core_dev *dh_dev,
+							   int32_t vqs_channel_num);
+void __iomem *zxdh_en_sf_map_vq_notify(struct dh_core_dev *dh_dev,
+									   uint32_t index, resource_size_t *pa);
+void zxdh_en_sf_unmap_vq_notify(struct dh_core_dev *dh_dev, void *priv);
+void zxdh_en_sf_activate_phy_vq(struct dh_core_dev *dh_dev, uint32_t phy_index,
+								int32_t queue_size, uint64_t desc_addr,
+								uint64_t avail_addr, uint64_t used_addr);
+void zxdh_en_sf_set_queue_enable(struct dh_core_dev *dh_dev, uint16_t index,
+								 bool enable);
+uint32_t zxdh_en_sf_get_epbdf(struct dh_core_dev *dh_dev);
+uint16_t zxdh_en_sf_get_vport(struct dh_core_dev *dh_dev);
+uint16_t zxdh_en_sf_get_pcie_id(struct dh_core_dev *dh_dev);
+uint16_t zxdh_en_sf_get_slot_id(struct dh_core_dev *dh_dev);
+enum dh_coredev_type zxdh_en_sf_get_coredev_type(struct dh_core_dev *dh_dev);
+void zxdh_en_sf_dpp_np_init(struct dh_core_dev *dh_dev, uint32_t vport);
+struct pci_dev *zxdh_en_sf_get_pdev(struct dh_core_dev *dh_dev);
+uint64_t zxdh_en_sf_get_bar_virt_addr(struct dh_core_dev *dh_dev,
+									  uint8_t bar_num);
+int32_t zxdh_en_sf_do_cmd_exec(struct dh_core_dev *dh_dev, uint32_t dst,
+							   uint32_t id, uint32_t len, void *payload,
+							   void *ack);
+struct zxdh_vf_item *zxdh_en_sf_get_vf_item(struct dh_core_dev *dh_dev,
+											uint16_t vf_idx);
+
+struct dh_en_sf_eq_table {
+	struct dh_irq **vq_irqs;
+	struct dh_irq *async_irq;
+	struct dh_eq_async async_eq;
+	int32_t vq_irq_num;
+	struct list_head vqs_eqs_list;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/en_sf/irq.c b/src/net/drivers/net/ethernet/dinghai/en_sf/irq.c
index 324354084eb224679d092b983c28ec3ed11d9a7d..1beeae2854572ac376ed6e449ee3db37efbbbb1f 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_sf/irq.c
+++ b/src/net/drivers/net/ethernet/dinghai/en_sf/irq.c
@@ -2,4 +2,3 @@
 #include <linux/dinghai/driver.h>
 #include <linux/dinghai/helper.h>
 #include "irq.h"
-
diff --git a/src/net/drivers/net/ethernet/dinghai/en_sf/irq.h b/src/net/drivers/net/ethernet/dinghai/en_sf/irq.h
index 250305bccc79618562cab2e38e79c82b1034129d..d698d01783273e54b56a0d26c36bafa260ef3454 100644
--- a/src/net/drivers/net/ethernet/dinghai/en_sf/irq.h
+++ b/src/net/drivers/net/ethernet/dinghai/en_sf/irq.h
@@ -8,13 +8,13 @@ extern "C" {
 #include <linux/dinghai/dinghai_irq.h>
 #include <linux/dinghai/driver.h>
 
-struct dh_irq* dh_pf_async_irq_request(struct dh_core_dev *dev);
+struct dh_irq *dh_pf_async_irq_request(struct dh_core_dev *dev);
 int32_t dh_pf_irq_table_create(struct dh_core_dev *dev);
 void dh_pf_irq_table_destroy(struct dh_core_dev *dev);
 int32_t dh_pf_irq_table_init(struct dh_core_dev *dev);
 
 struct dh_en_sf_irq_table {
-    struct dh_irq_pool *sf_vq_pool;
+	struct dh_irq_pool *sf_vq_pool;
 };
 
 #ifdef __cplusplus
diff --git a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn.c b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn.c
deleted file mode 100644
index bc6ac9479195290c59573a3a583072cfc45741e7..0000000000000000000000000000000000000000
--- a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn.c
+++ /dev/null
@@ -1,71 +0,0 @@
-#include <linux/module.h>
-#include <linux/dinghai/log.h>
-#include <linux/dinghai/driver.h>
-#include "en_pf.h"
-#include "zxdh_tsn.h"
-#include "zxdh_tsn_reg.h"
-#include "zxdh_tsn_comm.h"
-#include "zxdh_tsn_ioctl.h"
-
-int32_t zxdh_tsn_init(struct dh_core_dev* dh_dev)
-{
-    struct zxdh_tsn_private* tsn = NULL;
-    struct zxdh_pf_device* pf_dev = NULL;
-
-    ZXDH_TSN_COMM_CHECK_POINT(dh_dev);
-    ZXDH_TSN_COMM_CHECK_INDEX_EQUAL_RETURN_OK(dh_dev->coredev_type, DH_COREDEV_PF);
-
-    pf_dev = dh_core_priv(dh_dev);
-    ZXDH_TSN_COMM_CHECK_POINT(pf_dev);
-
-    tsn = kzalloc(sizeof(struct zxdh_tsn_private), GFP_KERNEL);
-    ZXDH_TSN_COMM_CHECK_POINT(tsn);
-
-    pf_dev->tsn = tsn;
-
-    memset(tsn, 0x00, sizeof(struct zxdh_tsn_private));
-
-    tsn->tsn_qbv_cap.ct_min  = TSN_CYCLE_TIME_MIN;
-    tsn->tsn_qbv_cap.ct_max  = TSN_CYCLE_TIME_MAX;
-    tsn->tsn_qbv_cap.it_min  = TSN_INTERVAL_TIME_MIN;
-    tsn->tsn_qbv_cap.it_max  = TSN_INTERVAL_TIME_MAX;
-    tsn->tsn_qbv_cap.gcl_num = TSN_PORT_GCL_NUM;
-    tsn->tsn_port_id.port_id = TSN_PORT_PORT_ID_DEF;
-    tsn->pci_ioremap_addr    = pf_dev->pci_ioremap_addr[0];
-
-    spin_lock_init(&tsn->tsn_spin_lock);
-
-    hrtimer_init(&tsn->tsn_qbv_change_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
-    tsn->tsn_qbv_change_timer.function = zxdh_tsn_qbv_change_timer_callback;
-
-    return TSN_OK;
-}
-EXPORT_SYMBOL(zxdh_tsn_init);
-
-void zxdh_tsn_exit(struct dh_core_dev* dh_dev)
-{
-    struct zxdh_tsn_private* tsn = NULL;
-    struct zxdh_pf_device* pf_dev = NULL;
-
-    ZXDH_TSN_COMM_CHECK_POINT_RETURN_NONE(dh_dev);
-    ZXDH_TSN_COMM_CHECK_INDEX_EQUAL_RETURN_NONE(dh_dev->coredev_type, DH_COREDEV_PF);
-
-    pf_dev = dh_core_priv(dh_dev);
-    ZXDH_TSN_COMM_CHECK_POINT_RETURN_NONE(pf_dev);
-
-    tsn = pf_dev->tsn;
-    ZXDH_TSN_COMM_CHECK_POINT_RETURN_NONE(tsn);
-
-    hrtimer_cancel(&tsn->tsn_qbv_change_timer);
-
-    if (!IS_ERR_OR_NULL((void*)(tsn->tsn_reg_base_addr)))
-    {
-        tsn_port_disable_set(tsn);
-        tsn_port_phy_port_set(tsn, TSN_PORT_PORT_ID_DEF);
-    }
-
-    kfree(tsn);
-}
-EXPORT_SYMBOL(zxdh_tsn_exit);
-
-MODULE_LICENSE("GPL");
diff --git a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn.h b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn.h
deleted file mode 100644
index 077a483e46611a79e1f80c456752dd2af447a26a..0000000000000000000000000000000000000000
--- a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn.h
+++ /dev/null
@@ -1,112 +0,0 @@
-#ifndef __ZXDH_TSN_H__
-#define __ZXDH_TSN_H__
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-#include <linux/types.h>
-#include <linux/hrtimer.h>
-#include <linux/spinlock.h>
-#include <linux/dinghai/driver.h>
-
-#define TSN_PORT_RAM_NUM                    (2)
-#define TSN_PORT_RAM_MAX                    (TSN_PORT_RAM_NUM -1)
-#define TSN_PORT_GCL_NUM                    (250)
-#define TSN_PORT_GCL_EXT_NUM                (6)
-#define TSN_PORT_GCL_MAX                    (TSN_PORT_GCL_NUM + TSN_PORT_GCL_EXT_NUM - 1)
-#define TSN_PORT_QUEUE_NUM                  (8)
-#define TSN_PORT_QUEUE_MAX                  (TSN_PORT_QUEUE_NUM - 1)
-#define TSN_PORT_PORT_ID_NUM                (4)
-#define TSN_PORT_PORT_ID_MAX                (TSN_PORT_PORT_ID_NUM - 1)
-#define TSN_PORT_PORT_ID_DEF                (15)
-#define TSN_PORT_TIMER_ID_NUM               (4)
-#define TSN_PORT_TIMER_ID_MAX               (TSN_PORT_TIMER_ID_NUM - 1)
-
-#define TSN_PORT_GATE_ENABLE                (1)
-#define TSN_PORT_GATE_DISABLE               (0)
-#define TSN_PORT_INIT_ENABLE                (1)
-#define TSN_PORT_INIT_DISABLE               (0)
-#define TSN_PORT_CHANGE_ENABLE              (1)
-#define TSN_PORT_CHANGE_DISABLE             (0)
-
-#define TSN_PORT_GATE_IDLE                  (0)
-#define TSN_PORT_GATE_RUNNING               (1)
-#define TSN_PORT_GATE_CHANGING              (2)
-#define TSN_PORT_GATE_PENDING               (3)
-
-#define TSN_CYCLE_TIME_MIN                  (500000)
-#define TSN_CYCLE_TIME_MAX                  (4000000000)
-#define TSN_INTERVAL_TIME_MIN               (1000)
-#define TSN_INTERVAL_TIME_MAX               (16000000)
-
-struct zxdh_tsn_port_id
-{
-    uint32_t port_id;
-};
-
-struct zxdh_tsn_timer_id
-{
-    uint32_t timer_id;
-};
-
-struct zxdh_tsn_qbv_cap
-{
-    uint64_t ct_min;
-    uint64_t ct_max;
-    uint32_t it_min;
-    uint32_t it_max;
-    uint32_t gcl_num;
-};
-
-struct zxdh_tsn_qbv_entry 
-{
-    uint32_t gate_state;
-    uint32_t time_interval;
-};
-
-struct zxdh_tsn_qbv_basic 
-{
-    uint64_t base_time;
-    uint64_t cycle_time;
-    uint32_t maxsdu[TSN_PORT_QUEUE_NUM];
-    uint32_t guard_band_time[TSN_PORT_QUEUE_NUM];
-    uint32_t control_list_length;
-    struct zxdh_tsn_qbv_entry control_list[TSN_PORT_GCL_NUM];
-};
-
-struct zxdh_tsn_qbv_conf
-{
-    uint32_t enable;
-    struct zxdh_tsn_qbv_basic admin;
-};
-
-struct zxdh_tsn_qbv_status
-{
-    uint64_t current_time;
-    uint32_t current_status;
-    struct zxdh_tsn_qbv_basic oper;
-};
-
-struct zxdh_tsn_private
-{
-    uint32_t phy_port_id;
-    uint64_t pci_ioremap_addr;
-    uint64_t tsn_reg_base_addr;
-
-    struct zxdh_tsn_port_id tsn_port_id;
-    struct zxdh_tsn_qbv_cap tsn_qbv_cap;
-    struct zxdh_tsn_qbv_conf tsn_qbv_conf[TSN_PORT_RAM_NUM];
-    struct hrtimer tsn_qbv_change_timer;
-
-    spinlock_t tsn_spin_lock;
-};
-
-int32_t zxdh_tsn_init(struct dh_core_dev* dh_dev);
-void    zxdh_tsn_exit(struct dh_core_dev* dh_dev);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ZXDH_TSN_H__ */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_comm.h b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_comm.h
deleted file mode 100644
index 4a8e529433404790249ad81592e04d45dd43b4e2..0000000000000000000000000000000000000000
--- a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_comm.h
+++ /dev/null
@@ -1,228 +0,0 @@
-#ifndef __ZXDH_TSN_COMM_H__
-#define __ZXDH_TSN_COMM_H__
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-#include <linux/types.h>
-#include "log.h"
-
-#ifndef TSN_OK
-#define TSN_OK                   (0)
-#endif
-
-#define ZXDH_TSN_COMM_CHECK_RC(rc)\
-do{\
-    if(TSN_OK != (rc))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[ErrorCode: %d] !\n", rc);\
-        return rc;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_RC_RETURN_NONE(rc)\
-do{\
-    if(TSN_OK != (rc))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[ErrorCode: %d] !\n", rc);\
-        return;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_RC_UNLOCK_RETURN_NONE(rc, lock)\
-do{\
-    if(TSN_OK != (rc))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[ErrorCode: %d] !\n", rc);\
-        spin_unlock(lock);\
-        return;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_RC_UNLOCK_RETURN_VALUE(rc, lock, value)\
-do{\
-    if(TSN_OK != (rc))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[ErrorCode: %d] !\n", rc);\
-        spin_unlock(lock);\
-        return value;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_RC_UNLOCKIRQ_MEMORY_FREE(rc, lock, flags, ptr)\
-do{\
-    if(TSN_OK != (rc))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[ErrorCode: %d] !\n", rc);\
-        spin_unlock_irqrestore(lock, flags);\
-        kfree(ptr);\
-        return rc;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_NONE(rc, lock, ptr)\
-do{\
-    if(TSN_OK != (rc))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[ErrorCode: %d] !\n", rc);\
-        spin_unlock(lock);\
-        kfree(ptr);\
-        return;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(rc, lock, ptr, value)\
-do{\
-    if(TSN_OK != (rc))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[ErrorCode: %d] !\n", rc);\
-        spin_unlock(lock);\
-        kfree(ptr);\
-        return value;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_RC_MEMORY_FREE(rc, ptr)\
-do{\
-    if(TSN_OK != (rc))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[ErrorCode: %d] !\n", rc);\
-        kfree(ptr);\
-        return rc;\
-    }\
-} while(0)
-
-#define ZXDH_TSN_COMM_CHECK_POINT(point)\
-do{\
-    if(NULL == (point))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[Error: POINT NULL] !\n");\
-        return -EINVAL;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_POINT_RETURN_NONE(point)\
-do{\
-    if(NULL == (point))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[Error: POINT NULL] !\n");\
-        return;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_POINT_RETURN_VALUE(point, value)\
-do{\
-    if(NULL == (point))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[Error: POINT NULL] !\n");\
-        return value;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_POINT_UNLOCK_RETURN_NONE(point, lock)\
-do{\
-    if(NULL == (point))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[Error: POINT NULL] !\n");\
-        spin_unlock(lock);\
-        return;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_POINT_UNLOCK_RETURN_VALUE(point, lock, value)\
-do{\
-    if(NULL == (point))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[Error: POINT NULL] !\n");\
-        spin_unlock(lock);\
-        return value;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_POINT_UNLOCK_MEMORY_FREE_RETURN_NONE(point, lock, ptr)\
-do{\
-    if(NULL == (point))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[Error: POINT NULL] !\n");\
-        spin_unlock(lock);\
-        kfree(ptr);\
-        return;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_INDEX(val, min, max)\
-do{\
-    if(((val) < (min)) || ((val) > (max)))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[Error: VALUE %u INVALID] [MIN %u MAX %u] !\n", val, min, max);\
-        return -EINVAL;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_INDEX_64(val, min, max)\
-do{\
-    if(((val) < (min)) || ((val) > (max)))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[Error: VALUE %llu INVALID] [MIN %llu MAX %llu] !\n", val, min, max);\
-        return -EINVAL;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_INDEX_MAX(val, max)\
-do{\
-    if((val) > (max))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[Error: VALUE %u INVALID] [MAX %u] !\n", val, max);\
-        return -EINVAL;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_INDEX_MAX_MEMORY_FREE(val, max, ptr)\
-do{\
-    if((val) > (max))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[Error: VALUE %u INVALID] [MAX %u] !\n", val, max);\
-        kfree(ptr);\
-        return -EINVAL;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_INDEX_EQUAL(val, equal)\
-do{\
-    if((val) != (equal))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[Error: VALUE %u INVALID] [EQUAL %u] !\n", val, equal);\
-        return -EINVAL;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_INDEX_EQUAL_64(val, equal)\
-do{\
-    if((val) != (equal))\
-    {\
-        DH_LOG_ERR(MODULE_TSN, "[Error: VALUE %llu INVALID] [EQUAL %llu] !\n", val, equal);\
-        return -EINVAL;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_INDEX_EQUAL_RETURN_OK(val, equal)\
-do{\
-    if((val) != (equal))\
-    {\
-        return TSN_OK;\
-    }\
-}while(0)
-
-#define ZXDH_TSN_COMM_CHECK_INDEX_EQUAL_RETURN_NONE(val, equal)\
-do{\
-    if((val) != (equal))\
-    {\
-        return;\
-    }\
-}while(0)
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __ZXDH_TSN_COMM_H__ */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_ioctl.c b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_ioctl.c
deleted file mode 100644
index f11b5e09a5754fec88a9734416df151d0ed01b25..0000000000000000000000000000000000000000
--- a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_ioctl.c
+++ /dev/null
@@ -1,695 +0,0 @@
-#include <linux/hrtimer.h>
-#include "log.h"
-#include "en_pf.h"
-#include "en_aux.h"
-#include "zxdh_tsn.h"
-#include "zxdh_tsn_reg.h"
-#include "zxdh_tsn_ioctl.h"
-#include "zxdh_tsn_comm.h"
-#ifndef HAVE_IOPOLL_OPS
-#include <linux/iopoll.h>
-#endif
-
-static int32_t zxdh_tsn_qbv_disable(struct zxdh_tsn_private* tsn)
-{
-    int32_t ret = 0;
-
-    ret = tsn_port_disable_set(tsn);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    memset(tsn->tsn_qbv_conf, 0x00, sizeof(tsn->tsn_qbv_conf));
-
-    hrtimer_cancel(&tsn->tsn_qbv_change_timer);
-
-    DH_LOG_INFO(MODULE_TSN, "tsn port id %u is disable.\n", tsn->tsn_port_id.port_id);
-
-    return TSN_OK;
-}
-
-static int32_t zxdh_tsn_port_id_set(struct zxdh_tsn_private* tsn, struct zxdh_tsn_msg* msg)
-{
-    int32_t  ret = 0;
-    uint64_t reg_base_addr = 0;
-    struct zxdh_tsn_port_id* tsn_port_id = NULL;
-
-    ZXDH_TSN_COMM_CHECK_INDEX_EQUAL(msg->len, (uint32_t)sizeof(struct zxdh_tsn_port_id));
-
-    tsn_port_id = (struct zxdh_tsn_port_id*)msg->data;
-    ZXDH_TSN_COMM_CHECK_POINT(tsn_port_id);
-
-    ZXDH_TSN_COMM_CHECK_INDEX_MAX(tsn_port_id->port_id, TSN_PORT_PORT_ID_MAX);
-
-    if (!IS_ERR_OR_NULL((void*)(tsn->tsn_reg_base_addr)))
-    {
-        ret = tsn_port_disable_set(tsn);
-        ZXDH_TSN_COMM_CHECK_RC(ret);
-
-        ret = tsn_port_phy_port_set(tsn, TSN_PORT_PORT_ID_DEF);
-        ZXDH_TSN_COMM_CHECK_RC(ret);
-    }
-
-    reg_base_addr = tsn->pci_ioremap_addr + TSN_PORT_REG_BAR_OFFSET + ((tsn_port_id->port_id) * TSN_PORT_REG_BAR_SIZE);
-    ret = tsn_write(reg_base_addr, TSN_PORT_PHY_PORT_SEL, tsn->phy_port_id);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    DH_LOG_INFO(MODULE_TSN, "tsn port id %u is bound to phy port id %u.\n", tsn_port_id->port_id,
-                                                                                tsn->phy_port_id);
-    tsn->tsn_reg_base_addr = reg_base_addr;
-    tsn->tsn_port_id.port_id = tsn_port_id->port_id;
-
-    ret = zxdh_tsn_qbv_disable(tsn);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-static int32_t zxdh_tsn_port_id_get(struct zxdh_tsn_private* tsn, struct zxdh_tsn_msg* msg)
-{
-    struct zxdh_tsn_port_id tsn_port_id;
-
-    ZXDH_TSN_COMM_CHECK_INDEX_EQUAL(msg->len, (uint32_t)sizeof(struct zxdh_tsn_port_id));
-
-    tsn_port_id.port_id = tsn->tsn_port_id.port_id;
-
-    memcpy(msg->data, &tsn_port_id, sizeof(struct zxdh_tsn_port_id));
-
-    return TSN_OK;
-}
-
-static int32_t zxdh_tsn_timer_id_set(struct zxdh_tsn_private* tsn, struct zxdh_tsn_msg* msg)
-{
-    int32_t ret = 0;
-    struct zxdh_tsn_timer_id* tsn_timer_id = NULL;
-
-    ZXDH_TSN_COMM_CHECK_INDEX_EQUAL(msg->len, (uint32_t)sizeof(struct zxdh_tsn_timer_id));
-
-    tsn_timer_id = (struct zxdh_tsn_timer_id*)msg->data;
-    ZXDH_TSN_COMM_CHECK_POINT(tsn_timer_id);
-
-    ZXDH_TSN_COMM_CHECK_INDEX_MAX(tsn_timer_id->timer_id, TSN_PORT_TIMER_ID_MAX);
-
-    ret = tsn_port_timer_id_set(tsn, tsn_timer_id->timer_id);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    DH_LOG_INFO(MODULE_TSN, "tsn port id %u is bound to timer id %u.\n", tsn->tsn_port_id.port_id,
-                                                                           tsn_timer_id->timer_id);
-
-    return TSN_OK;
-}
-
-static int32_t zxdh_tsn_timer_id_get(struct zxdh_tsn_private* tsn, struct zxdh_tsn_msg* msg)
-{
-    int32_t ret = 0;
-    struct zxdh_tsn_timer_id tsn_timer_id;
-
-    ZXDH_TSN_COMM_CHECK_INDEX_EQUAL(msg->len, (uint32_t)sizeof(struct zxdh_tsn_timer_id));
-
-    ret = tsn_port_timer_id_get(tsn, &tsn_timer_id.timer_id);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    memcpy(msg->data, &tsn_timer_id, sizeof(struct zxdh_tsn_timer_id));
-
-    return TSN_OK;
-}
-
-static int32_t zxdh_tsn_qbv_conf_check(struct zxdh_tsn_private* tsn, struct zxdh_tsn_qbv_conf* tsn_qbv_conf)
-{
-    uint32_t index = 0;
-    uint64_t time_interval_sum = 0;
-    struct zxdh_tsn_qbv_basic* tsn_qbv_basic = &tsn_qbv_conf->admin;
-    struct zxdh_tsn_qbv_entry* tsn_qbv_entry = tsn_qbv_conf->admin.control_list;
-
-    ZXDH_TSN_COMM_CHECK_INDEX_MAX(tsn_qbv_conf->enable, TSN_PORT_GATE_ENABLE);
-
-    ZXDH_TSN_COMM_CHECK_INDEX_64(tsn_qbv_basic->cycle_time, tsn->tsn_qbv_cap.ct_min, tsn->tsn_qbv_cap.ct_max);
-
-    ZXDH_TSN_COMM_CHECK_INDEX(tsn_qbv_basic->control_list_length, 1, tsn->tsn_qbv_cap.gcl_num);
-
-    for (index = 0; index < tsn_qbv_basic->control_list_length; index++)
-    {
-        ZXDH_TSN_COMM_CHECK_INDEX(tsn_qbv_entry[index].time_interval, tsn->tsn_qbv_cap.it_min, tsn->tsn_qbv_cap.it_max);
-        time_interval_sum += tsn_qbv_entry[index].time_interval;
-    }
-
-    ZXDH_TSN_COMM_CHECK_INDEX_EQUAL_64(tsn_qbv_basic->cycle_time, time_interval_sum);
-
-    return TSN_OK;
-}
-
-static int32_t zxdh_tsn_qbv_base_time_cal(struct zxdh_tsn_private* tsn, struct zxdh_tsn_qbv_conf* tsn_qbv_conf_oper,
-                                                                        struct zxdh_tsn_qbv_conf* tsn_qbv_conf_admin,
-                                                                            uint64_t real_tod_time, uint32_t status)
-{
-    uint64_t oper_base_time = 0;
-    uint64_t oper_cycle_time = 0;
-    uint64_t admin_base_time = 0;
-    uint64_t admin_cycle_time = 0;
-    uint64_t cycle_time_extension = 0;
-
-    ZXDH_TSN_COMM_CHECK_POINT(tsn_qbv_conf_oper);
-    ZXDH_TSN_COMM_CHECK_POINT(tsn_qbv_conf_admin);
-
-    oper_base_time = tsn_qbv_conf_oper->admin.base_time;
-    oper_cycle_time = tsn_qbv_conf_oper->admin.cycle_time;
-
-    admin_base_time = tsn_qbv_conf_admin->admin.base_time;
-    admin_cycle_time = tsn_qbv_conf_admin->admin.cycle_time;
-
-    if (real_tod_time >= admin_base_time)
-    {
-        admin_base_time += admin_cycle_time * (((real_tod_time - admin_base_time) / admin_cycle_time) + 1);
-        if ((admin_base_time - real_tod_time) < TSN_SOFT_RESERVED_TIME)
-        {
-            admin_base_time += TSN_RESERVED_TIME(admin_cycle_time);
-        }
-        DH_LOG_INFO(MODULE_TSN, "tsn port id %u admin_base_time change to %llu real_tod_time %llu diff %llu.\n",
-                       tsn->tsn_port_id.port_id, admin_base_time, real_tod_time, admin_base_time - real_tod_time);
-    }
-    else if ((admin_base_time - real_tod_time) < TSN_SOFT_RESERVED_TIME)
-    {
-        admin_base_time += TSN_RESERVED_TIME(admin_cycle_time);
-        DH_LOG_INFO(MODULE_TSN, "tsn port id %u admin_base_time change to %llu real_tod_time %llu diff %llu.\n",
-                       tsn->tsn_port_id.port_id, admin_base_time, real_tod_time, admin_base_time - real_tod_time);
-    }
-
-    if (status != TSN_PORT_GATE_IDLE)
-    {
-        if (real_tod_time >= oper_base_time)
-        {
-            cycle_time_extension = (admin_base_time - oper_base_time) % oper_cycle_time;
-            if (cycle_time_extension < TSN_CYCLE_TIME_EXTENSION_MIN)
-            {
-                cycle_time_extension += oper_cycle_time;
-            }
-            DH_LOG_INFO(MODULE_TSN, "tsn port id %u cycle_time_extension %llu .\n", tsn->tsn_port_id.port_id, cycle_time_extension);
-
-            if (cycle_time_extension < oper_cycle_time)
-            {
-                oper_base_time += oper_cycle_time * (((real_tod_time - oper_base_time) / oper_cycle_time) + 1);
-                if ((oper_base_time - real_tod_time) < TSN_SOFT_RESERVED_TIME)
-                {
-                    oper_base_time += TSN_RESERVED_TIME(oper_cycle_time);
-                }
-            }
-            else
-            {
-                oper_base_time += oper_cycle_time * (((real_tod_time - oper_base_time) / oper_cycle_time) + 2);
-                if ((oper_base_time - oper_cycle_time - real_tod_time) < TSN_SOFT_RESERVED_TIME)
-                {
-                    oper_base_time += TSN_RESERVED_TIME(oper_cycle_time);
-                }
-            }
-            DH_LOG_INFO(MODULE_TSN, "tsn port id %u oper_base_time change to %llu real_tod_time %llu diff %llu.\n",
-                            tsn->tsn_port_id.port_id, oper_base_time, real_tod_time, oper_base_time - real_tod_time);
-        }
-
-        if (oper_base_time > admin_base_time)
-        {
-            if (cycle_time_extension == oper_cycle_time)
-            {
-                admin_base_time += admin_cycle_time * (((oper_base_time - admin_base_time) / admin_cycle_time));
-            }
-            else
-            {
-                admin_base_time += admin_cycle_time * (((oper_base_time - admin_base_time) / admin_cycle_time) + 1);
-            }
-            DH_LOG_INFO(MODULE_TSN, "tsn port id %u admin_base_time change to %llu oper_base_time %llu diff %llu.\n",
-                            tsn->tsn_port_id.port_id, admin_base_time, oper_base_time, admin_base_time - oper_base_time);
-        }
-    }
-
-    tsn_qbv_conf_admin->admin.base_time = admin_base_time;
-
-    return TSN_OK;
-}
-
-static int32_t zxdh_tsn_qbv_cycle_time_extension_cal(struct zxdh_tsn_private* tsn, struct zxdh_tsn_qbv_conf* tsn_qbv_conf_oper,
-                                                                                   struct zxdh_tsn_qbv_conf* tsn_qbv_conf_admin,
-                                                                                   uint64_t* cycle_time_extension)
-{
-    uint64_t admin_base_time = 0;
-    uint64_t oper_base_time = 0;
-    uint64_t oper_cycle_time = 0;
-
-    ZXDH_TSN_COMM_CHECK_POINT(tsn_qbv_conf_oper);
-    ZXDH_TSN_COMM_CHECK_POINT(tsn_qbv_conf_admin);
-    ZXDH_TSN_COMM_CHECK_POINT(cycle_time_extension);
-
-    oper_base_time = tsn_qbv_conf_oper->admin.base_time;
-    oper_cycle_time = tsn_qbv_conf_oper->admin.cycle_time;
-
-    admin_base_time = tsn_qbv_conf_admin->admin.base_time;
-
-    if ((admin_base_time > oper_base_time) && (oper_cycle_time != 0))
-    {
-        oper_base_time += oper_cycle_time * ((admin_base_time - oper_base_time) / oper_cycle_time);
-        if (admin_base_time >= oper_base_time)
-        {
-            *cycle_time_extension = admin_base_time - oper_base_time;
-            if ((*cycle_time_extension) < TSN_CYCLE_TIME_EXTENSION_MIN)
-            {
-                *cycle_time_extension += oper_cycle_time;
-            }
-            DH_LOG_INFO(MODULE_TSN, "tsn port id %u cycle_time_extension %llu.\n", tsn->tsn_port_id.port_id,
-                                                                                     *cycle_time_extension);
-            return TSN_OK;
-        }
-    }
-
-    return -EINVAL;
-}
-
-static int32_t zxdh_tsn_qbv_gate_status_get(struct zxdh_tsn_private* tsn, uint32_t* p_ram_n_idle, uint32_t* p_status)
-{
-    int32_t  ret = 0;
-    uint32_t init_finish = 0;
-    uint32_t change_en = 0;
-    uint32_t ram_n = 0;
-    uint32_t status = 0;
-    uint32_t enable = 0;
-    uint64_t admin_base_time = 0;
-    uint64_t real_tod_time = 0;
-    uint64_t cycle_time_extension = 0;
-
-    ret = tsn_port_status_get(tsn, &ram_n, &status);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_port_init_finish_get(tsn, &init_finish);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_port_change_en_get(tsn, &change_en);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_port_enable_get(tsn, &enable);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    *p_ram_n_idle = (ram_n == 0)? 0 : ((ram_n == 1)? 1 : ((ram_n == 2)? 0 : 2));
-    ZXDH_TSN_COMM_CHECK_INDEX_MAX(*p_ram_n_idle, TSN_PORT_RAM_MAX);
-
-    if ((status == 0) && (init_finish == 0) && (change_en == 0) && (enable == TSN_PORT_GATE_DISABLE))
-    {
-        *p_status = TSN_PORT_GATE_IDLE;
-        DH_LOG_INFO(MODULE_TSN, "tsn port id %u idle status %u init_finish %u change_en %u enable %u.\n",
-                                       tsn->tsn_port_id.port_id, status, init_finish, change_en, enable);
-        return TSN_OK;
-    }
-
-    if (((status >= 3) && (status <= 8)) && (init_finish == 0) && (change_en == 0) && (enable == TSN_PORT_GATE_ENABLE))
-    {
-        *p_status = TSN_PORT_GATE_RUNNING;
-        DH_LOG_INFO(MODULE_TSN, "tsn port id %u running status %u init_finish %u change_en %u enable %u.\n",
-                                          tsn->tsn_port_id.port_id, status, init_finish, change_en, enable);
-        return TSN_OK;
-    }
-
-    if (((status >= 3) && (status <= 8)) && (init_finish == 0) && (change_en == 1) && (enable == TSN_PORT_GATE_ENABLE))
-    {
-        admin_base_time = tsn->tsn_qbv_conf[*p_ram_n_idle].admin.base_time;
-        ret = zxdh_tsn_qbv_cycle_time_extension_cal(tsn, &tsn->tsn_qbv_conf[TSN_RAM_N_IN_SERVICE(*p_ram_n_idle)],
-                                                         &tsn->tsn_qbv_conf[*p_ram_n_idle], &cycle_time_extension);
-        ZXDH_TSN_COMM_CHECK_RC(ret);
-
-        ret = tsn_port_real_tod_time_get(tsn, &real_tod_time);
-        ZXDH_TSN_COMM_CHECK_RC(ret);
-
-        if ((admin_base_time - cycle_time_extension - TSN_SOFT_RESERVED_TIME) > real_tod_time)
-        {
-            *p_status = TSN_PORT_GATE_CHANGING;
-            DH_LOG_INFO(MODULE_TSN, "tsn port id %u changing status %u init_finish %u change_en %u enable %u.\n",
-                                                tsn->tsn_port_id.port_id, status, init_finish, change_en, enable);
-            return TSN_OK;
-        }
-    }
-
-    *p_status = TSN_PORT_GATE_PENDING;
-    DH_LOG_INFO(MODULE_TSN, "tsn port id %u pending status %u init_finish %u change_en %u enable %u.\n",
-                                                  tsn->tsn_port_id.port_id, status, init_finish, change_en, enable);
-    return TSN_OK;
-}
-
-static int32_t zxdh_tsn_qbv_basic_set(struct zxdh_tsn_private* tsn, struct zxdh_tsn_qbv_conf* tsn_qbv_conf, uint32_t ram_n_idle)
-{
-    int32_t  ret = 0;
-    uint32_t index = 0;
-
-    ret = tsn_port_default_gate_set(tsn, 0x00);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_port_change_gate_set(tsn, 0xFF);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    for (index = 0; index < TSN_PORT_QUEUE_NUM; index++)
-    {
-        ret = tsn_port_guard_band_time_set(tsn, index, tsn_qbv_conf->admin.guard_band_time[index]);
-        ZXDH_TSN_COMM_CHECK_RC(ret);
-    }
-
-    ret = tsn_port_gcl_num_set(tsn, ram_n_idle, tsn_qbv_conf->admin.control_list_length);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    for (index = 0; index < tsn_qbv_conf->admin.control_list_length; index++)
-    {
-        ret = tsn_port_gcl_control_set(tsn, ram_n_idle, index, tsn_qbv_conf->admin.control_list[index].gate_state,
-                                                               tsn_qbv_conf->admin.control_list[index].time_interval);
-        ZXDH_TSN_COMM_CHECK_RC(ret);
-    }
-
-    ret = tsn_port_enable_set(tsn, TSN_PORT_GATE_ENABLE);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_port_cycle_time_set(tsn, tsn_qbv_conf->admin.cycle_time);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_port_base_time_set(tsn, tsn_qbv_conf->admin.base_time);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-static int32_t zxdh_tsn_qbv_change_set(struct zxdh_tsn_private* tsn, struct zxdh_tsn_qbv_conf* tsn_qbv_conf, uint32_t ram_n_idle)
-{
-    int32_t ret = 0;
-
-    ret = tsn_port_change_en_set(tsn, TSN_PORT_CHANGE_DISABLE);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = zxdh_tsn_qbv_basic_set(tsn, tsn_qbv_conf, ram_n_idle);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_port_change_en_set(tsn, TSN_PORT_CHANGE_ENABLE);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-static int32_t zxdh_tsn_qbv_set(struct zxdh_tsn_private* tsn, struct zxdh_tsn_msg* msg)
-{
-    int32_t  ret = 0;
-    uint32_t ram_n_idle = 0;
-    uint32_t status = 0;
-    uint64_t cycle_time_extension = 0;
-    uint64_t real_tod_time = 0;
-    uint64_t expires_in_nanosecond = 0;
-    struct zxdh_tsn_qbv_conf* tsn_qbv_conf = NULL;
-
-    ZXDH_TSN_COMM_CHECK_INDEX_EQUAL(msg->len, (uint32_t)sizeof(struct zxdh_tsn_qbv_conf));
-
-    tsn_qbv_conf = (struct zxdh_tsn_qbv_conf*)msg->data;
-    ZXDH_TSN_COMM_CHECK_POINT(tsn_qbv_conf);
-
-    if (tsn_qbv_conf->enable == TSN_PORT_GATE_DISABLE)
-    {
-        ret = zxdh_tsn_qbv_disable(tsn);
-        ZXDH_TSN_COMM_CHECK_RC(ret);
-        return TSN_OK;
-    }
-
-    ret = zxdh_tsn_qbv_conf_check(tsn, tsn_qbv_conf);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = zxdh_tsn_qbv_gate_status_get(tsn, &ram_n_idle, &status);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    if (status == TSN_PORT_GATE_PENDING)
-    {
-        DH_LOG_ERR(MODULE_TSN, "tsn port id %u is pending.\n", tsn->tsn_port_id.port_id);
-        return -EBUSY;
-    }
-
-    ret = tsn_port_real_tod_time_get(tsn, &real_tod_time);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = zxdh_tsn_qbv_base_time_cal(tsn, &tsn->tsn_qbv_conf[TSN_RAM_N_IN_SERVICE(ram_n_idle)], tsn_qbv_conf,
-                                                                                      real_tod_time, status);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    if (status == TSN_PORT_GATE_IDLE)
-    {
-        ret = zxdh_tsn_qbv_basic_set(tsn, tsn_qbv_conf, ram_n_idle);
-        ZXDH_TSN_COMM_CHECK_RC(ret);
-
-        ret = tsn_port_init_finish_set(tsn, TSN_PORT_INIT_ENABLE);
-        ZXDH_TSN_COMM_CHECK_RC(ret);
-
-        memcpy(&tsn->tsn_qbv_conf[ram_n_idle], tsn_qbv_conf, sizeof(struct zxdh_tsn_qbv_conf));
-
-        DH_LOG_INFO(MODULE_TSN, "tsn port id %u ram %u is enable.\n", tsn->tsn_port_id.port_id, ram_n_idle);
-    }
-    else
-    {
-        ret = zxdh_tsn_qbv_cycle_time_extension_cal(tsn, &tsn->tsn_qbv_conf[TSN_RAM_N_IN_SERVICE(ram_n_idle)], tsn_qbv_conf,
-                                                                                                     &cycle_time_extension);
-        ZXDH_TSN_COMM_CHECK_RC(ret);
-
-        // if (cycle_time_extension < TSN_CYCLE_TIME_EXTENSION_MIN)
-        // {
-        //     ret = zxdh_tsn_qbv_change_set(tsn, tsn_qbv_conf, ram_n_idle);
-        //     ZXDH_TSN_COMM_CHECK_RC(ret);
-
-        //     memcpy(&tsn->tsn_qbv_conf[ram_n_idle], tsn_qbv_conf, sizeof(struct zxdh_tsn_qbv_conf));
-
-        //     hrtimer_cancel(&tsn->tsn_qbv_change_timer);
-
-        //     DH_LOG_INFO(MODULE_TSN, "tsn port id %u ram %u is going to change.\n", tsn->tsn_port_id.port_id, ram_n_idle);
-        // }
-        // else
-        // {
-            memcpy(&tsn->tsn_qbv_conf[ram_n_idle], tsn_qbv_conf, sizeof(struct zxdh_tsn_qbv_conf));
-
-            expires_in_nanosecond = tsn->tsn_qbv_conf[ram_n_idle].admin.base_time - cycle_time_extension -
-                                                                                    TSN_TIMER_RESERVED_TIME - real_tod_time;
-            hrtimer_start(&tsn->tsn_qbv_change_timer, ns_to_ktime(expires_in_nanosecond), HRTIMER_MODE_REL);
-
-            DH_LOG_INFO(MODULE_TSN, "tsn port id %u timer wake up in %llu ns later.\n", tsn->tsn_port_id.port_id, expires_in_nanosecond);
-        // }
-    }
-
-    return TSN_OK;
-}
-
-static int32_t zxdh_tsn_qbv_status_get(struct zxdh_tsn_private* tsn, struct zxdh_tsn_msg* msg)
-{
-    int32_t  ret = 0;
-    uint32_t ram_n_idle = 0;
-    struct zxdh_tsn_qbv_status* tsn_qbv_status;
-
-    ZXDH_TSN_COMM_CHECK_INDEX_EQUAL(msg->len, (uint32_t)sizeof(struct zxdh_tsn_qbv_status));
-
-    tsn_qbv_status = (struct zxdh_tsn_qbv_status*)msg->data;
-    ZXDH_TSN_COMM_CHECK_POINT(tsn_qbv_status);
-
-    ret = zxdh_tsn_qbv_gate_status_get(tsn, &ram_n_idle, &tsn_qbv_status->current_status);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_port_real_tod_time_get(tsn, &tsn_qbv_status->current_time);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    memcpy(&tsn_qbv_status->oper, &tsn->tsn_qbv_conf[TSN_RAM_N_IN_SERVICE(ram_n_idle)].admin, sizeof(struct zxdh_tsn_qbv_basic));
-
-    return TSN_OK;
-}
-
-static int32_t zxdh_tsn_qbv_cycle_time_extension_set(struct zxdh_tsn_private* tsn, struct zxdh_tsn_qbv_conf* tsn_qbv_conf,
-                                                                       uint64_t cycle_time_extension, uint32_t ram_n_idle)
-{
-    int32_t  ret = 0;
-    uint32_t index = 0;
-    uint32_t gate_state = 0;
-    uint32_t change_gate_status = 0;
-    uint32_t time_interval = 0;
-    uint64_t real_tod_time = 0;
-    uint64_t cycle_time_reserved = 0;
-
-    ret = tsn_port_real_tod_time_get(tsn, &real_tod_time);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    memcpy(tsn_qbv_conf, &tsn->tsn_qbv_conf[TSN_RAM_N_IN_SERVICE(ram_n_idle)], sizeof(struct zxdh_tsn_qbv_conf));
-
-    if (cycle_time_extension > tsn_qbv_conf->admin.cycle_time)
-    {
-        cycle_time_reserved = cycle_time_extension - tsn_qbv_conf->admin.cycle_time;
-
-        for (index = 0; index < TSN_PORT_GCL_EXT_NUM; index++)
-        {
-            gate_state = tsn_qbv_conf->admin.control_list[index].gate_state;
-            time_interval = tsn_qbv_conf->admin.control_list[index].time_interval;
-
-            ret = tsn_port_gcl_control_set(tsn, ram_n_idle, tsn_qbv_conf->admin.control_list_length + index,
-                                                                                 gate_state, time_interval);
-            ZXDH_TSN_COMM_CHECK_RC(ret);
-
-            if (cycle_time_reserved > time_interval)
-            {
-                cycle_time_reserved = cycle_time_reserved - time_interval;
-                continue;
-            }
-            break;
-        }
-    }
-
-    tsn_qbv_conf->admin.base_time = tsn->tsn_qbv_conf[ram_n_idle].admin.base_time - cycle_time_extension
-                                                                                  + TSN_HW_RESERVED_TIME;
-    tsn_qbv_conf->admin.cycle_time = cycle_time_extension - (2 * TSN_HW_RESERVED_TIME);
-    tsn_qbv_conf->admin.control_list[0].time_interval -= TSN_HW_RESERVED_TIME;
-
-    ret = zxdh_tsn_qbv_change_set(tsn, tsn_qbv_conf, ram_n_idle);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    change_gate_status = tsn_qbv_conf->admin.control_list[0].gate_state;
-    ret = tsn_port_change_gate_set(tsn, change_gate_status);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_port_gcl_num_set(tsn, ram_n_idle, tsn_qbv_conf->admin.control_list_length + index + 1);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    DH_LOG_INFO(MODULE_TSN, "tsn port id %u admin_base_time %llu real_tod_time %llu diff %llu.\n", tsn->tsn_port_id.port_id,
-                               tsn_qbv_conf->admin.base_time, real_tod_time, tsn_qbv_conf->admin.base_time - real_tod_time);
-    DH_LOG_INFO(MODULE_TSN, "tsn port id %u ram %u is going to change in timer.\n", tsn->tsn_port_id.port_id, ram_n_idle);
-
-    return TSN_OK;
-}
-
-enum hrtimer_restart zxdh_tsn_qbv_change_timer_callback(struct hrtimer* t)
-{
-    int32_t  ret = 0;
-    uint32_t change_en = 0;
-    uint32_t change_gate_status = 0;
-    uint32_t ram_n_idle = 0;
-    uint32_t status = 0;
-    uint64_t real_tod_time = 0;
-    uint64_t cycle_time_extension = 0;
-    struct zxdh_tsn_private* tsn = NULL;
-    struct zxdh_tsn_qbv_conf* tsn_qbv_conf = NULL;
-
-    tsn = container_of(t, struct zxdh_tsn_private, tsn_qbv_change_timer);
-    ZXDH_TSN_COMM_CHECK_POINT_RETURN_VALUE(tsn, HRTIMER_NORESTART);
-
-    spin_lock(&tsn->tsn_spin_lock);
-
-    tsn_qbv_conf = kzalloc(sizeof(struct zxdh_tsn_qbv_conf), GFP_KERNEL);
-    ZXDH_TSN_COMM_CHECK_POINT_UNLOCK_RETURN_VALUE(tsn_qbv_conf, &tsn->tsn_spin_lock, HRTIMER_NORESTART);
-
-    ret = zxdh_tsn_qbv_gate_status_get(tsn, &ram_n_idle, &status);
-    ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(ret, &tsn->tsn_spin_lock, tsn_qbv_conf, HRTIMER_NORESTART);
-
-    ret = zxdh_tsn_qbv_cycle_time_extension_cal(tsn, &tsn->tsn_qbv_conf[TSN_RAM_N_IN_SERVICE(ram_n_idle)],
-                                                     &tsn->tsn_qbv_conf[ram_n_idle], &cycle_time_extension);
-    ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(ret, &tsn->tsn_spin_lock, tsn_qbv_conf, HRTIMER_NORESTART);
-
-    ret = zxdh_tsn_qbv_cycle_time_extension_set(tsn, tsn_qbv_conf, cycle_time_extension, ram_n_idle);
-    ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(ret, &tsn->tsn_spin_lock, tsn_qbv_conf, HRTIMER_NORESTART);
-
-    ret = readx_poll_timeout_atomic(readl, ((const volatile void *)((tsn->tsn_reg_base_addr) + TSN_PORT_CHANGE_EN)),
-                                                              change_en, (change_en == 0), 1, (TSN_TIMER_RESERVED_TIME * 2));
-    ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(ret, &tsn->tsn_spin_lock, tsn_qbv_conf, HRTIMER_NORESTART);
-
-    change_gate_status = tsn_qbv_conf->admin.control_list[tsn_qbv_conf->admin.control_list_length - 1].gate_state;
-
-    ret = tsn_port_real_tod_time_get(tsn, &real_tod_time);
-    ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(ret, &tsn->tsn_spin_lock, tsn_qbv_conf, HRTIMER_NORESTART);
-
-    memcpy(tsn_qbv_conf, &tsn->tsn_qbv_conf[ram_n_idle], sizeof(struct zxdh_tsn_qbv_conf));
-    memcpy(&tsn->tsn_qbv_conf[ram_n_idle], &tsn->tsn_qbv_conf[TSN_RAM_N_IN_SERVICE(ram_n_idle)], sizeof(struct zxdh_tsn_qbv_conf));
-
-    ret = zxdh_tsn_qbv_gate_status_get(tsn, &ram_n_idle, &status);
-    ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(ret, &tsn->tsn_spin_lock, tsn_qbv_conf, HRTIMER_NORESTART);
-
-    ret = zxdh_tsn_qbv_change_set(tsn, tsn_qbv_conf, ram_n_idle);
-    ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(ret, &tsn->tsn_spin_lock, tsn_qbv_conf, HRTIMER_NORESTART);
-
-    ret = tsn_port_change_gate_set(tsn, change_gate_status);
-    ZXDH_TSN_COMM_CHECK_RC_UNLOCK_MEMORY_FREE_RETURN_VALUE(ret, &tsn->tsn_spin_lock, tsn_qbv_conf, HRTIMER_NORESTART);
-
-    memcpy(&tsn->tsn_qbv_conf[ram_n_idle], tsn_qbv_conf, sizeof(struct zxdh_tsn_qbv_conf));
-
-    DH_LOG_INFO(MODULE_TSN, "tsn port id %u admin_base_time %llu real_tod_time %llu diff %llu.\n", tsn->tsn_port_id.port_id,
-                               tsn_qbv_conf->admin.base_time, real_tod_time, tsn_qbv_conf->admin.base_time - real_tod_time);
-
-    kfree(tsn_qbv_conf);
-
-    spin_unlock(&tsn->tsn_spin_lock);
-
-    DH_LOG_INFO(MODULE_TSN, "tsn port id %u ram %u is going to change in timer.\n", tsn->tsn_port_id.port_id, ram_n_idle);
-
-    return HRTIMER_NORESTART;
-}
-
-static struct zxdh_tsn_ioctl_table tsn_ioctl_table[] =
-{
-    {TSN_PORT_ID_SET,               zxdh_tsn_port_id_set},
-    {TSN_PORT_ID_GET,               zxdh_tsn_port_id_get},
-    {TSN_TIMER_ID_SET,              zxdh_tsn_timer_id_set},
-    {TSN_TIMER_ID_GET,              zxdh_tsn_timer_id_get},
-    {TSN_QBV_CONF_SET,              zxdh_tsn_qbv_set},
-    {TSN_QBV_STATUS_GET,            zxdh_tsn_qbv_status_get},
-};
-
-int32_t zxdh_en_tsn_func(struct net_device* netdev, struct ifreq* ifr)
-{
-    int32_t  ret = 0;
-    uint32_t index = 0;
-    uint32_t table_size = 0;
-    uint64_t start_time = 0;
-    uint64_t end_time = 0;
-    unsigned long flags = 0;
-    struct zxdh_en_priv* en_priv = NULL;
-    struct zxdh_en_device* en_dev = NULL;
-    struct zxdh_pf_device* pf_dev = NULL;
-    struct zxdh_tsn_private* tsn = NULL;
-    struct zxdh_tsn_msg* msg = NULL;
-
-    ZXDH_TSN_COMM_CHECK_POINT(netdev);
-    ZXDH_TSN_COMM_CHECK_POINT(ifr);
-
-    en_priv = netdev_priv(netdev);
-    ZXDH_TSN_COMM_CHECK_POINT(en_priv);
-
-    en_dev = &en_priv->edev;
-    ZXDH_TSN_COMM_CHECK_POINT(en_dev);
-
-    pf_dev = dh_core_priv(en_dev->parent->parent);
-    ZXDH_TSN_COMM_CHECK_POINT(pf_dev);
-
-    tsn = pf_dev->tsn;
-    ZXDH_TSN_COMM_CHECK_POINT(tsn);
-
-    msg = kzalloc(sizeof(struct zxdh_tsn_msg), GFP_KERNEL);
-    ZXDH_TSN_COMM_CHECK_POINT(msg);
-
-    ret = unlikely(copy_from_user(msg, ifr->ifr_ifru.ifru_data, sizeof(struct zxdh_tsn_msg)));
-    ZXDH_TSN_COMM_CHECK_RC_MEMORY_FREE(ret, msg);
-
-    table_size = (uint32_t)(sizeof(tsn_ioctl_table) / sizeof(struct zxdh_tsn_ioctl_table));
-
-    for(index = 0; index < table_size; index++)
-    {
-        if((msg->cmd == tsn_ioctl_table[index].cmd) && (tsn_ioctl_table[index].func != NULL))
-        {
-            spin_lock_irqsave(&tsn->tsn_spin_lock, flags);
-
-            start_time = ktime_get_ns();
-
-            ret = tsn_ioctl_table[index].func(tsn, msg);
-            ZXDH_TSN_COMM_CHECK_RC_UNLOCKIRQ_MEMORY_FREE(ret, &tsn->tsn_spin_lock, flags, msg);
-
-            end_time = ktime_get_ns();
-
-            spin_unlock_irqrestore(&tsn->tsn_spin_lock, flags);
-
-            DH_LOG_INFO(MODULE_TSN, "tsn port id %u cmd %u total take up %lld ns.\n", tsn->tsn_port_id.port_id,
-                                                                                msg->cmd, end_time - start_time);
-            break;
-        }
-    }
-
-    ZXDH_TSN_COMM_CHECK_INDEX_MAX_MEMORY_FREE(index, table_size - 1, msg);
-
-    ret = unlikely(copy_to_user(ifr->ifr_ifru.ifru_data, msg, sizeof(struct zxdh_tsn_msg)));
-    ZXDH_TSN_COMM_CHECK_RC_MEMORY_FREE(ret, msg);
-
-    kfree(msg);
-
-    return TSN_OK;
-}
-
-EXPORT_SYMBOL_GPL(zxdh_en_tsn_func);
diff --git a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_ioctl.h b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_ioctl.h
deleted file mode 100644
index e7140be8782cdf5fa57d88507cd2571887507124..0000000000000000000000000000000000000000
--- a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_ioctl.h
+++ /dev/null
@@ -1,48 +0,0 @@
-#ifndef __ZXDH_TSN_IOCTL_H__
-#define __ZXDH_TSN_IOCTL_H__
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-#include <linux/types.h>
-#include <linux/hrtimer.h>
-
-#define TSN_MSG_LEN                         (4096 - 8)
-
-#define TSN_PORT_ID_SET                     (0)
-#define TSN_PORT_ID_GET                     (1)
-#define TSN_TIMER_ID_SET                    (2)
-#define TSN_TIMER_ID_GET                    (3)
-#define TSN_QBV_CONF_SET                    (4)
-#define TSN_QBV_STATUS_GET                  (5)
-
-#define TSN_SOFT_RESERVED_TIME              (500000)
-#define TSN_HW_RESERVED_TIME                (200)
-#define TSN_TIMER_RESERVED_TIME             (300000)
-#define TSN_RESERVED_TIME(CT)               ((((CT) < TSN_SOFT_RESERVED_TIME)? \
-                                            ((TSN_SOFT_RESERVED_TIME / (CT)) + 1) : 1) * (CT))
-#define TSN_RAM_N_IN_SERVICE(RAM_N_IDLE)    ((~(RAM_N_IDLE)) & 1)
-
-#define TSN_CYCLE_TIME_EXTENSION_MIN        (500000)
-
-struct zxdh_tsn_msg
-{
-    uint32_t cmd;
-    uint32_t len;
-    uint8_t  data[TSN_MSG_LEN];
-};
-
-struct zxdh_tsn_ioctl_table
-{
-    int32_t cmd;
-    int32_t (*func)(struct zxdh_tsn_private* tsn, struct zxdh_tsn_msg* msg);
-};
-
-enum hrtimer_restart zxdh_tsn_qbv_change_timer_callback(struct hrtimer* t);
-int32_t zxdh_en_tsn_func(struct net_device* netdev, struct ifreq* ifr);
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __ZXDH_TSN_IOCTL_H__ */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_reg.c b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_reg.c
deleted file mode 100644
index fc9ef4d0dfdb8cf6f96f5e0597d626770b9b1455..0000000000000000000000000000000000000000
--- a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_reg.c
+++ /dev/null
@@ -1,428 +0,0 @@
-#include <linux/dinghai/log.h>
-#include "zxdh_tsn.h"
-#include "zxdh_tsn_reg.h"
-#include "zxdh_tsn_comm.h"
-
-int32_t tsn_read(uint64_t base_addr, uint32_t offset, uint32_t* p_val)
-{
-    if (IS_ERR_OR_NULL((void*)(base_addr)))
-    {
-        DH_LOG_ERR(MODULE_TSN, "base_addr 0x%llx invalid.\n", base_addr);
-        return -EINVAL;
-    }
-
-    *p_val = readl((const volatile void *)(base_addr + offset));
-
-    return TSN_OK;
-}
-
-int32_t tsn_write(uint64_t base_addr, uint32_t offset, uint32_t val)
-{
-    if (IS_ERR_OR_NULL((void*)(base_addr)))
-    {
-        DH_LOG_ERR(MODULE_TSN, "base_addr 0x%llx invalid.\n", base_addr);
-        return -EINVAL;
-    }
-
-    writel(val, (volatile void *)(base_addr + offset));
-
-    return TSN_OK;
-}
-
-int32_t tsn_reg_read(struct zxdh_tsn_private* tsn, uint32_t offset, uint32_t* p_val)
-{
-    int32_t ret = 0;
-
-    ZXDH_TSN_COMM_CHECK_POINT(tsn);
-    ZXDH_TSN_COMM_CHECK_POINT(p_val);
-
-    ret = tsn_read(tsn->tsn_reg_base_addr, offset, p_val);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_reg_write(struct zxdh_tsn_private* tsn, uint32_t offset, uint32_t val)
-{
-    int32_t ret = 0;
-
-    ZXDH_TSN_COMM_CHECK_POINT(tsn);
-
-    ret = tsn_write(tsn->tsn_reg_base_addr, offset, val);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_enable_set(struct zxdh_tsn_private* tsn, uint32_t enable)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_write(tsn, TSN_PORT_QBV_ENABLE, enable);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_enable_get(struct zxdh_tsn_private* tsn, uint32_t* p_enable)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_read(tsn, TSN_PORT_QBV_ENABLE, p_enable);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_phy_port_set(struct zxdh_tsn_private* tsn, uint32_t phy_port)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_write(tsn, TSN_PORT_PHY_PORT_SEL, phy_port);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_phy_port_get(struct zxdh_tsn_private* tsn, uint32_t* p_phy_port)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_read(tsn, TSN_PORT_PHY_PORT_SEL, p_phy_port);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_timer_id_set(struct zxdh_tsn_private* tsn, uint32_t timer_id)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_write(tsn, TSN_PORT_TIME_SEL, timer_id);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_timer_id_get(struct zxdh_tsn_private* tsn, uint32_t* p_time_id)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_read(tsn, TSN_PORT_TIME_SEL, p_time_id);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_status_get(struct zxdh_tsn_private* tsn, uint32_t* p_ram_n, uint32_t* p_status)
-{
-    int32_t  ret = 0;
-    uint32_t val = 0;
-
-    ZXDH_TSN_COMM_CHECK_POINT(p_ram_n);
-    ZXDH_TSN_COMM_CHECK_POINT(p_status);
-
-    ret = tsn_reg_read(tsn, TSN_PORT_READ_RAM_N, &val);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    *p_ram_n = val & 0x3;
-    *p_status = (val & 0x3C) >> 2;
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_base_time_l_set(struct zxdh_tsn_private* tsn, uint32_t base_time)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_write(tsn, TSN_PORT_BASE_TIME_L, base_time);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_base_time_h_set(struct zxdh_tsn_private* tsn, uint32_t base_time)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_write(tsn, TSN_PORT_BASE_TIME_H, base_time);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_base_time_set(struct zxdh_tsn_private* tsn, uint64_t base_time)
-{
-    int32_t  ret = 0;
-    uint32_t base_time_l = (uint32_t)((base_time) & 0xffffffff);
-    uint32_t base_time_h = (uint32_t)((base_time >> 32) & 0xffffffff);
-
-    ret = tsn_port_base_time_l_set(tsn, base_time_l);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_port_base_time_h_set(tsn, base_time_h);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_base_time_get(struct zxdh_tsn_private* tsn, uint64_t* p_base_time)
-{
-    int32_t  ret = 0;
-    uint32_t base_time_l = 0;
-    uint32_t base_time_h = 0;
-
-    ZXDH_TSN_COMM_CHECK_POINT(p_base_time);
-
-    ret = tsn_reg_read(tsn, TSN_PORT_BASE_TIME_L, &base_time_l);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_reg_read(tsn, TSN_PORT_BASE_TIME_H, &base_time_h);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    *p_base_time = (uint64_t)((((uint64_t)(base_time_h)) << 32) | ((uint64_t)(base_time_l)));
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_cycle_time_l_set(struct zxdh_tsn_private* tsn, uint32_t cycle_time)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_write(tsn, TSN_PORT_CYCLE_TIME_L, cycle_time);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_cycle_time_h_set(struct zxdh_tsn_private* tsn, uint32_t cycle_time)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_write(tsn, TSN_PORT_CYCLE_TIME_H, cycle_time);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_cycle_time_set(struct zxdh_tsn_private* tsn, uint64_t cycle_time)
-{
-    int32_t  ret = 0;
-    uint32_t cycle_time_l = (uint32_t)((cycle_time) & 0x000fffff);
-    uint32_t cycle_time_h = (uint32_t)((cycle_time >> 20) & 0x000fffff);
-
-    ret = tsn_port_cycle_time_l_set(tsn, cycle_time_l);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_port_cycle_time_h_set(tsn, cycle_time_h);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_cycle_time_get(struct zxdh_tsn_private* tsn, uint64_t* p_cycle_time)
-{
-    int32_t  ret = 0;
-    uint32_t cycle_time_l = 0;
-    uint32_t cycle_time_h = 0;
-
-    ZXDH_TSN_COMM_CHECK_POINT(p_cycle_time);
-
-    ret = tsn_reg_read(tsn, TSN_PORT_CYCLE_TIME_L, &cycle_time_l);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_reg_read(tsn, TSN_PORT_CYCLE_TIME_H, &cycle_time_h);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    *p_cycle_time = (uint64_t)((((uint64_t)(cycle_time_h)) << 20) | ((uint64_t)(cycle_time_l)));
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_guard_band_time_set(struct zxdh_tsn_private* tsn, uint32_t cos, uint32_t band_time)
-{
-    int32_t ret = 0;
-
-    ZXDH_TSN_COMM_CHECK_INDEX_MAX(cos, TSN_PORT_QUEUE_MAX);
-
-    ret = tsn_reg_write(tsn, TSN_PORT_GUARD_BAND_TIME + (cos * 4), band_time);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_guard_band_time_get(struct zxdh_tsn_private* tsn, uint32_t cos, uint32_t* p_band_time)
-{
-    int32_t ret = 0;
-
-    ZXDH_TSN_COMM_CHECK_INDEX_MAX(cos, TSN_PORT_QUEUE_MAX);
-
-    ret = tsn_reg_read(tsn, TSN_PORT_GUARD_BAND_TIME + (cos * 4), p_band_time);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_default_gate_set(struct zxdh_tsn_private* tsn, uint32_t gate_state)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_write(tsn, TSN_PORT_DEFAULT_GATE_EN, gate_state);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_default_gate_get(struct zxdh_tsn_private* tsn, uint32_t* p_gate_state)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_read(tsn, TSN_PORT_DEFAULT_GATE_EN, p_gate_state);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_change_gate_set(struct zxdh_tsn_private* tsn, uint32_t gate_state)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_write(tsn, TSN_PORT_CHANGE_GATE_EN, gate_state);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_init_finish_set(struct zxdh_tsn_private* tsn, uint32_t init_finish)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_write(tsn, TSN_PORT_INIT_FINISH, init_finish);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_init_finish_get(struct zxdh_tsn_private* tsn, uint32_t* p_init_finish)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_read(tsn, TSN_PORT_INIT_FINISH, p_init_finish);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_change_en_set(struct zxdh_tsn_private* tsn, uint32_t change_en)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_write(tsn, TSN_PORT_CHANGE_EN, change_en);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_change_en_get(struct zxdh_tsn_private* tsn, uint32_t* p_change_en)
-{
-    int32_t ret = 0;
-
-    ret = tsn_reg_read(tsn, TSN_PORT_CHANGE_EN, p_change_en);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_gcl_num_set(struct zxdh_tsn_private* tsn, uint32_t ram_n, uint32_t gcl_num)
-{
-    int32_t  ret = 0;
-    uint32_t tsn_port_gcl_num[TSN_PORT_RAM_NUM] = {TSN_PORT_GCL_NUM0, TSN_PORT_GCL_NUM1};
-
-    ZXDH_TSN_COMM_CHECK_INDEX_MAX(ram_n, TSN_PORT_RAM_MAX);
-
-    ret = tsn_reg_write(tsn, tsn_port_gcl_num[ram_n], gcl_num);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_gcl_num_get(struct zxdh_tsn_private* tsn, uint32_t ram_n, uint32_t* p_gcl_num)
-{
-    int32_t  ret = 0;
-    uint32_t tsn_port_gcl_num[TSN_PORT_RAM_NUM] = {TSN_PORT_GCL_NUM0, TSN_PORT_GCL_NUM1};
-
-    ZXDH_TSN_COMM_CHECK_INDEX_MAX(ram_n, TSN_PORT_RAM_MAX);
-
-    ret = tsn_reg_read(tsn, tsn_port_gcl_num[ram_n], p_gcl_num);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_gcl_control_set(struct zxdh_tsn_private* tsn, uint32_t ram_n, uint32_t index, uint32_t gate_state, uint32_t internal)
-{
-    int32_t  ret = 0;
-    uint32_t tsn_port_gcl_value[TSN_PORT_RAM_NUM] = {TSN_PORT_GCL_VALUE0, TSN_PORT_GCL_VALUE1};
-
-    ZXDH_TSN_COMM_CHECK_INDEX_MAX(ram_n, TSN_PORT_RAM_MAX);
-    ZXDH_TSN_COMM_CHECK_INDEX_MAX(index, TSN_PORT_GCL_MAX);
-
-    ret = tsn_reg_write(tsn, tsn_port_gcl_value[ram_n] + (index * 4), (gate_state << 24) | internal);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_disable_set(struct zxdh_tsn_private* tsn)
-{
-    int32_t ret = 0;
-
-    ret = tsn_port_enable_set(tsn, TSN_PORT_GATE_DISABLE);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_port_init_finish_set(tsn, TSN_PORT_INIT_DISABLE);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_port_change_en_set(tsn, TSN_PORT_CHANGE_DISABLE);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    return TSN_OK;
-}
-
-int32_t tsn_port_real_tod_time_get(struct zxdh_tsn_private* tsn, uint64_t* p_tod_time)
-{
-    int32_t  ret = 0;
-    uint32_t tsn_timer_id = 0;
-    uint32_t tod_second_h = 0;
-    uint32_t tod_second_l = 0;
-    uint32_t tod_nanosecond = 0;
-
-    uint32_t tsn_real_tod_nanosecond_reg_offset[TSN_PORT_TIMER_ID_NUM] = {
-        TSN0_REAL_TOD_NANOSECOND, TSN1_REAL_TOD_NANOSECOND, TSN2_REAL_TOD_NANOSECOND, TSN3_REAL_TOD_NANOSECOND
-    };
-    uint32_t tsn_real_high_tod_second_reg_offset[TSN_PORT_TIMER_ID_NUM] = {
-        TSN0_REAL_HIGH_TOD_SECOND, TSN1_REAL_HIGH_TOD_SECOND, TSN2_REAL_HIGH_TOD_SECOND, TSN3_REAL_HIGH_TOD_SECOND
-    };
-    uint32_t tsn_real_lower_tod_second_reg_offset[TSN_PORT_TIMER_ID_NUM] = {
-        TSN0_REAL_LOWER_TOD_SECOND, TSN1_REAL_LOWER_TOD_SECOND, TSN2_REAL_LOWER_TOD_SECOND, TSN3_REAL_LOWER_TOD_SECOND
-    };
-
-    ZXDH_TSN_COMM_CHECK_POINT(p_tod_time);
-
-    ret = tsn_port_timer_id_get(tsn, &tsn_timer_id);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-    ZXDH_TSN_COMM_CHECK_INDEX_MAX(tsn_timer_id, TSN_PORT_TIMER_ID_MAX);
-
-    ret = tsn_read(tsn->pci_ioremap_addr + 0xC000, tsn_real_high_tod_second_reg_offset[tsn_timer_id], &tod_second_h);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_read(tsn->pci_ioremap_addr + 0xC000, tsn_real_lower_tod_second_reg_offset[tsn_timer_id], &tod_second_l);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    ret = tsn_read(tsn->pci_ioremap_addr + 0xC000, tsn_real_tod_nanosecond_reg_offset[tsn_timer_id], &tod_nanosecond);
-    ZXDH_TSN_COMM_CHECK_RC(ret);
-
-    *p_tod_time = ((((uint64_t)tod_second_h << 32) | (uint64_t)tod_second_l) * NSEC_PER_SEC) + tod_nanosecond;
-
-    return TSN_OK;
-}
diff --git a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_reg.h b/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_reg.h
deleted file mode 100644
index a884482bc6999a2b561923ea0214941fc7c48e34..0000000000000000000000000000000000000000
--- a/src/net/drivers/net/ethernet/dinghai/en_tsn/zxdh_tsn_reg.h
+++ /dev/null
@@ -1,86 +0,0 @@
-#ifndef __ZXDH_TSN_REG_H__
-#define __ZXDH_TSN_REG_H__
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-#include <linux/types.h>
-#include <linux/dinghai/driver.h>
-
-#define TSN_PORT_REG_BAR_SIZE               (0x4000)
-#define TSN_PORT_REG_BAR_OFFSET             (0x14000)
-
-#define TSN_PORT_QBV_ENABLE                 (0x0004)
-#define TSN_PORT_PHY_PORT_SEL               (0x0008)
-#define TSN_PORT_TIME_SEL                   (0x000C)
-#define TSN_PORT_CLK_FREQ                   (0x0014)
-#define TSN_PORT_READ_RAM_N                 (0x0018)
-#define TSN_PORT_EXE_TIME                   (0x001C)
-#define TSN_PORT_ITR_SHIFT                  (0x0020)
-#define TSN_PORT_BASE_TIME_H                (0x0024)
-#define TSN_PORT_BASE_TIME_L                (0x0028)
-#define TSN_PORT_CYCLE_TIME_H               (0x0030)
-#define TSN_PORT_CYCLE_TIME_L               (0x0034)
-#define TSN_PORT_GUARD_BAND_TIME            (0x0040)
-#define TSN_PORT_DEFAULT_GATE_EN            (0x0060)
-#define TSN_PORT_CHANGE_GATE_EN             (0x0064)
-#define TSN_PORT_INIT_FINISH                (0x0068)
-#define TSN_PORT_CHANGE_EN                  (0x006C)
-#define TSN_PORT_GCL_NUM0                   (0x0070)
-#define TSN_PORT_GCL_NUM1                   (0x0074)
-#define TSN_PORT_GCL_VALUE0                 (0x1000)
-#define TSN_PORT_GCL_VALUE1                 (0x2000)
-
-#define TSN0_REAL_TOD_NANOSECOND            (0x4240)
-#define TSN0_REAL_LOWER_TOD_SECOND          (0x4244)
-#define TSN0_REAL_HIGH_TOD_SECOND           (0x4248)
-#define TSN1_REAL_TOD_NANOSECOND            (0x424C)
-#define TSN1_REAL_LOWER_TOD_SECOND          (0x4250)
-#define TSN1_REAL_HIGH_TOD_SECOND           (0x4254)
-#define TSN2_REAL_TOD_NANOSECOND            (0x4258)
-#define TSN2_REAL_LOWER_TOD_SECOND          (0x425C)
-#define TSN2_REAL_HIGH_TOD_SECOND           (0x4260)
-#define TSN3_REAL_TOD_NANOSECOND            (0x4264)
-#define TSN3_REAL_LOWER_TOD_SECOND          (0x4268)
-#define TSN3_REAL_HIGH_TOD_SECOND           (0x426C)
-
-int32_t tsn_read(uint64_t base_addr, uint32_t offset, uint32_t* p_val);
-int32_t tsn_write(uint64_t base_addr, uint32_t offset, uint32_t val);
-int32_t tsn_reg_read(struct zxdh_tsn_private* tsn, uint32_t offset, uint32_t* p_val);
-int32_t tsn_reg_write(struct zxdh_tsn_private* tsn, uint32_t offset, uint32_t val);
-int32_t tsn_port_enable_set(struct zxdh_tsn_private* tsn, uint32_t enable);
-int32_t tsn_port_enable_get(struct zxdh_tsn_private* tsn, uint32_t* p_enable);
-int32_t tsn_port_phy_port_set(struct zxdh_tsn_private* tsn, uint32_t phy_port);
-int32_t tsn_port_phy_port_get(struct zxdh_tsn_private* tsn, uint32_t* p_phy_port);
-int32_t tsn_port_timer_id_set(struct zxdh_tsn_private* tsn, uint32_t timer_id);
-int32_t tsn_port_timer_id_get(struct zxdh_tsn_private* tsn, uint32_t* p_time_id);
-int32_t tsn_port_status_get(struct zxdh_tsn_private* tsn, uint32_t* p_ram_n, uint32_t* p_status);
-int32_t tsn_port_base_time_l_set(struct zxdh_tsn_private* tsn, uint32_t base_time);
-int32_t tsn_port_base_time_h_set(struct zxdh_tsn_private* tsn, uint32_t base_time);
-int32_t tsn_port_base_time_set(struct zxdh_tsn_private* tsn, uint64_t base_time);
-int32_t tsn_port_base_time_get(struct zxdh_tsn_private* tsn, uint64_t* p_base_time);
-int32_t tsn_port_cycle_time_l_set(struct zxdh_tsn_private* tsn, uint32_t cycle_time);
-int32_t tsn_port_cycle_time_h_set(struct zxdh_tsn_private* tsn, uint32_t cycle_time);
-int32_t tsn_port_cycle_time_set(struct zxdh_tsn_private* tsn, uint64_t cycle_time);
-int32_t tsn_port_cycle_time_get(struct zxdh_tsn_private* tsn, uint64_t* p_cycle_time);
-int32_t tsn_port_guard_band_time_set(struct zxdh_tsn_private* tsn, uint32_t cos, uint32_t band_time);
-int32_t tsn_port_guard_band_time_get(struct zxdh_tsn_private* tsn, uint32_t cos, uint32_t* p_band_time);
-int32_t tsn_port_default_gate_set(struct zxdh_tsn_private* tsn, uint32_t gate_state);
-int32_t tsn_port_default_gate_get(struct zxdh_tsn_private* tsn, uint32_t* p_gate_state);
-int32_t tsn_port_change_gate_set(struct zxdh_tsn_private* tsn, uint32_t gate_state);
-int32_t tsn_port_init_finish_set(struct zxdh_tsn_private* tsn, uint32_t init_finish);
-int32_t tsn_port_init_finish_get(struct zxdh_tsn_private* tsn, uint32_t* p_init_finish);
-int32_t tsn_port_change_en_set(struct zxdh_tsn_private* tsn, uint32_t change_en);
-int32_t tsn_port_change_en_get(struct zxdh_tsn_private* tsn, uint32_t* p_change_en);
-int32_t tsn_port_gcl_num_set(struct zxdh_tsn_private* tsn, uint32_t ram_n, uint32_t gcl_num);
-int32_t tsn_port_gcl_num_get(struct zxdh_tsn_private* tsn, uint32_t ram_n, uint32_t* p_gcl_num);
-int32_t tsn_port_gcl_control_set(struct zxdh_tsn_private* tsn, uint32_t ram_n, uint32_t index, uint32_t gate_state, uint32_t internal);
-int32_t tsn_port_disable_set(struct zxdh_tsn_private* tsn);
-int32_t tsn_port_real_tod_time_get(struct zxdh_tsn_private* tsn, uint64_t* p_tod_time);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ZXDH_TSN_REG_H__ */
diff --git a/src/net/drivers/net/ethernet/dinghai/en_vf.c b/src/net/drivers/net/ethernet/dinghai/en_vf.c
old mode 100755
new mode 100644
diff --git a/src/net/drivers/net/ethernet/dinghai/eq.c b/src/net/drivers/net/ethernet/dinghai/eq.c
old mode 100755
new mode 100644
index be1cbb33915937d2d62ae1d27647b6bf3e121e8d..ad58c3253395c8c0247980872ab5a9c4b522ea63
--- a/src/net/drivers/net/ethernet/dinghai/eq.c
+++ b/src/net/drivers/net/ethernet/dinghai/eq.c
@@ -1,108 +1,104 @@
-#include <linux/dinghai/eq.h>
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/device.h>
-#include <linux/dinghai/dinghai_irq.h>
-#include <linux/dinghai/helper.h>
-#include <linux/notifier.h>
-#include <linux/dinghai/pci_irq.h>
-#include <linux/dinghai/dh_cmd.h>
-#include <net/addrconf.h>
-
-
-int32_t dh_eq_enable(struct dh_core_dev *dev, struct dh_eq *eq,
-                     struct notifier_block *nb)
-{
-    return dh_irq_attach_nb(eq->irq, nb);
-}
-
-int32_t setup_async_eq(struct dh_core_dev *dev, struct dh_eq_async *eq, \
-                       struct dh_eq_param *param, notifier_fn_t dh_eq_async_int, \
-                       const char *name, void *priv)
-{
-    struct dh_eq *eq_core = NULL;
-    int32_t err = 0;
-
-    eq->irq_nb.notifier_call = dh_eq_async_int;
-    eq->priv = priv;
-    spin_lock_init(&eq->lock);//unused
-
-    eq_core = &eq->core;
-    eq_core->irq = param->irq;
-
-    err = dh_eq_enable(dev, &eq->core, &eq->irq_nb);
-    if (err != 0)
-    {
-        LOG_WARN("failed to enable %s EQ %d\n", name, err);
-    }
-
-    return err;
-}
-
-void dh_eq_disable(struct dh_core_dev *dev, struct dh_eq *eq,
-                   struct notifier_block *nb)
-{
-    dh_irq_detach_nb(eq->irq, nb);
-}
-//EXPORT_SYMBOL(dh_eq_disable);
-
-
-void dh_eq_table_cleanup(struct dh_core_dev *dev)
-{
-    kvfree(dev->eq_table.priv);
-}
-
-int32_t dh_inet6_addr_change_notifier_register(struct notifier_block *inet6_addr_change_notifier)
-{
-    return register_inet6addr_notifier(inet6_addr_change_notifier);
-}
-
-int32_t dh_inet6_addr_change_notifier_unregister(struct notifier_block *inet6_addr_change_notifier)
-{
-    return unregister_inet6addr_notifier(inet6_addr_change_notifier);
-}
-
-int32_t dh_eq_notifier_register(struct dh_eq_table *eqt, struct dh_nb *nb)
-{
-    return atomic_notifier_chain_register(&eqt->nh[nb->event_type], &nb->nb);
-}
-//EXPORT_SYMBOL(dh_eq_notifier_register);
-
-
-int32_t dh_eq_notifier_unregister(struct dh_eq_table *eqt, struct dh_nb *nb)
-{
-    return atomic_notifier_chain_unregister(&eqt->nh[nb->event_type], &nb->nb);
-}
-//EXPORT_SYMBOL(dh_eq_notifier_unregister);
-
-void dh_eq_table_init(struct dh_core_dev *dev, void *table_priv)
-{
-    struct dh_eq_table *eq_table = &dev->eq_table;
-    int32_t i;
-
-    eq_table->priv = table_priv;
-
-    mutex_init(&eq_table->lock);
-    for (i = 0; i < DH_EVENT_TYPE_MAX; i++)
-    {
-        ATOMIC_INIT_NOTIFIER_HEAD(&eq_table->nh[i]);
-    }
-
-    eq_table->irq_table = &dev->irq_table;
-}
-
-
-static uint16_t event_type_map[MSG_MODULE_NUM] = {
-    [MODULE_VF_BAR_MSG_TO_PF] = DH_EVENT_TYPE_NOTIFY_VF_TO_PF,
-    [MODULE_RISC_READY] = DH_EVENT_TYPE_RISCV_READY,
-    [MODULE_PF_BAR_MSG_TO_VF] = DH_EVENT_TYPE_NOTIFY_PF_TO_VF,
-    [MODULE_VIRTIO] = DH_EVENT_TYPE_NOTIFY_ANY,
-    [MODULE_DHTOOL] = DH_EVENT_TYPE_NOTIFY_RISCV_TO_AUX,
-    [MODULE_RESET_MSG] = DH_EVENT_TYPE_NOTIFY_ANY,
-    [MODULE_DEMO] = DH_EVENT_TYPE_NOTIFY_ANY,
-};
-
-uint16_t dh_eq_event_type_get(uint16_t event_id)
-{
-    return event_type_map[event_id];
-}
-//EXPORT_SYMBOL(dh_eq_event_type_get);
+#include <linux/dinghai/eq.h>
+#include <linux/dinghai/driver.h>
+#include <linux/dinghai/device.h>
+#include <linux/dinghai/dinghai_irq.h>
+#include <linux/dinghai/helper.h>
+#include <linux/notifier.h>
+#include <linux/dinghai/pci_irq.h>
+#include <linux/dinghai/dh_cmd.h>
+#include <net/addrconf.h>
+
+int32_t dh_eq_enable(struct dh_core_dev *dev, struct dh_eq *eq,
+					 struct notifier_block *nb)
+{
+	return dh_irq_attach_nb(eq->irq, nb);
+}
+
+int32_t setup_async_eq(struct dh_core_dev *dev, struct dh_eq_async *eq,
+					   struct dh_eq_param *param, notifier_fn_t dh_eq_async_int,
+					   const char *name, void *priv)
+{
+	struct dh_eq *eq_core = NULL;
+	int32_t err = 0;
+
+	eq->irq_nb.notifier_call = dh_eq_async_int;
+	eq->priv = priv;
+	spin_lock_init(&eq->lock); // unused
+
+	eq_core = &eq->core;
+	eq_core->irq = param->irq;
+
+	err = dh_eq_enable(dev, &eq->core, &eq->irq_nb);
+	if (err != 0) {
+		LOG_WARN("failed to enable %s EQ %d\n", name, err);
+	}
+
+	return err;
+}
+
+void dh_eq_disable(struct dh_core_dev *dev, struct dh_eq *eq,
+				   struct notifier_block *nb)
+{
+	dh_irq_detach_nb(eq->irq, nb);
+}
+// EXPORT_SYMBOL(dh_eq_disable);
+
+void dh_eq_table_cleanup(struct dh_core_dev *dev)
+{
+	kvfree(dev->eq_table.priv);
+}
+
+int32_t dh_inet6_addr_change_notifier_register(
+		struct notifier_block *inet6_addr_change_notifier)
+{
+	return register_inet6addr_notifier(inet6_addr_change_notifier);
+}
+
+int32_t dh_inet6_addr_change_notifier_unregister(
+		struct notifier_block *inet6_addr_change_notifier)
+{
+	return unregister_inet6addr_notifier(inet6_addr_change_notifier);
+}
+
+int32_t dh_eq_notifier_register(struct dh_eq_table *eqt, struct dh_nb *nb)
+{
+	return atomic_notifier_chain_register(&eqt->nh[nb->event_type], &nb->nb);
+}
+// EXPORT_SYMBOL(dh_eq_notifier_register);
+
+int32_t dh_eq_notifier_unregister(struct dh_eq_table *eqt, struct dh_nb *nb)
+{
+	return atomic_notifier_chain_unregister(&eqt->nh[nb->event_type], &nb->nb);
+}
+// EXPORT_SYMBOL(dh_eq_notifier_unregister);
+
+void dh_eq_table_init(struct dh_core_dev *dev, void *table_priv)
+{
+	struct dh_eq_table *eq_table = &dev->eq_table;
+	int32_t i;
+
+	eq_table->priv = table_priv;
+
+	mutex_init(&eq_table->lock);
+	for (i = 0; i < DH_EVENT_TYPE_MAX; i++) {
+		ATOMIC_INIT_NOTIFIER_HEAD(&eq_table->nh[i]);
+	}
+
+	eq_table->irq_table = &dev->irq_table;
+}
+
+static uint16_t event_type_map[MSG_MODULE_NUM] = {
+	[MODULE_VF_BAR_MSG_TO_PF] = DH_EVENT_TYPE_NOTIFY_VF_TO_PF,
+	[MODULE_RISC_READY] = DH_EVENT_TYPE_RISCV_READY,
+	[MODULE_PF_BAR_MSG_TO_VF] = DH_EVENT_TYPE_NOTIFY_PF_TO_VF,
+	[MODULE_VIRTIO] = DH_EVENT_TYPE_NOTIFY_ANY,
+	[MODULE_DHTOOL] = DH_EVENT_TYPE_NOTIFY_RISCV_TO_AUX,
+	[MODULE_RESET_MSG] = DH_EVENT_TYPE_NOTIFY_ANY,
+	[MODULE_DEMO] = DH_EVENT_TYPE_NOTIFY_ANY,
+};
+
+uint16_t dh_eq_event_type_get(uint16_t event_id)
+{
+	return event_type_map[event_id];
+}
+// EXPORT_SYMBOL(dh_eq_event_type_get);
diff --git a/src/net/drivers/net/ethernet/dinghai/events.c b/src/net/drivers/net/ethernet/dinghai/events.c
old mode 100755
new mode 100644
index a551fd805491614ef29b8135737ff4ac6313d3d4..bb3920b1f183cbb08a6c3e7dab9e65714b250965
--- a/src/net/drivers/net/ethernet/dinghai/events.c
+++ b/src/net/drivers/net/ethernet/dinghai/events.c
@@ -1,13 +1,12 @@
-#include <linux/dinghai/events.h>
-
-void zxdh_events_work_enqueue(struct dh_core_dev *dev, struct work_struct *work)
-{
-    queue_work(dev->events->wq, work);
-}
-
-void zxdh_events_cleanup(struct dh_core_dev *dev)
-{
-    destroy_workqueue(dev->events->wq);
-    kfree(dev->events);
-}
- 
+#include <linux/dinghai/events.h>
+
+void zxdh_events_work_enqueue(struct dh_core_dev *dev, struct work_struct *work)
+{
+	queue_work(dev->events->wq, work);
+}
+
+void zxdh_events_cleanup(struct dh_core_dev *dev)
+{
+	destroy_workqueue(dev->events->wq);
+	kfree(dev->events);
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/irq_affinity.c b/src/net/drivers/net/ethernet/dinghai/irq_affinity.c
old mode 100755
new mode 100644
index 7b68fcfd4cde6b738f0026904ff0c019e80084eb..13875423a8298facb002699be8a5f3628851dffd
--- a/src/net/drivers/net/ethernet/dinghai/irq_affinity.c
+++ b/src/net/drivers/net/ethernet/dinghai/irq_affinity.c
@@ -1,278 +1,274 @@
-#include <linux/dinghai/dinghai_irq.h>
-#include <linux/dinghai/pci_irq.h>
-#include <linux/dinghai/helper.h>
-
-
-static void cpu_put(struct dh_irq_pool *pool, int32_t cpu)
-{
-    pool->irqs_per_cpu[cpu]--;
-}
-
-static void cpu_get(struct dh_irq_pool *pool, int32_t cpu)
-{
-    pool->irqs_per_cpu[cpu]++;
-}
-
-/* Gets the least loaded CPU. e.g.: the CPU with least IRQs bound to it */
-static int32_t cpu_get_least_loaded(struct dh_irq_pool *pool,
-                                    const struct cpumask *req_mask)
-{
-    int32_t best_cpu = -1;
-    int32_t cpu;
-
-    for_each_cpu_and(cpu, req_mask, cpu_online_mask)
-    {
-        /* CPU has zero IRQs on it. No need to search any more CPUs. */
-        if (!pool->irqs_per_cpu[cpu])
-        {
-            best_cpu = cpu;
-            break;
-        }
-        if (best_cpu < 0)
-        {
-            best_cpu = cpu;
-        }
-        if (pool->irqs_per_cpu[cpu] < pool->irqs_per_cpu[best_cpu])
-        {
-            best_cpu = cpu;
-        }
-    }
-
-    if (best_cpu == -1)
-    {
-        /* There isn't online CPUs in req_mask */
-        LOG_ERR("NO online CPUs in req_mask (%*pbl)\n", cpumask_pr_args(req_mask));
-        best_cpu = cpumask_first(cpu_online_mask);
-    }
-    pool->irqs_per_cpu[best_cpu]++;
-
-    return best_cpu;
-}
-
-/* Creating an IRQ from irq_pool */
-struct dh_irq *irq_pool_request_irq(struct dh_irq_pool *pool, const struct cpumask *req_mask)
-{
-    cpumask_var_t auto_mask;
-    struct dh_irq *irq = NULL;
-    u32 irq_index = 0;
-    int32_t err = 0;
-
-    if (!zalloc_cpumask_var(&auto_mask, GFP_KERNEL))
-    {
-        LOG_ERR("zalloc_cpumask_var failed, ERR_PTR(-ENOMEM)=0x%llx", (unsigned long long)ERR_PTR(-ENOMEM));
-        return ERR_PTR(-ENOMEM);
-    }
-
-    err = xa_alloc(&pool->irqs, &irq_index, NULL, pool->xa_num_irqs, GFP_KERNEL);
-    if (err)
-    {
-        if (err == -EBUSY)
-        {
-            err = -EUSERS;
-        }
-        LOG_ERR("xa_alloc failed, ERR_PTR(err)=0x%llx", (unsigned long long)ERR_PTR(err));
-        return ERR_PTR(err);
-    }
-
-    if (pool->irqs_per_cpu)
-    {
-        if (cpumask_weight(req_mask) > 1)
-        {
-            /* if req_mask contain more then one CPU, set the least loadad CPU
-             * of req_mask
-             */
-            cpumask_set_cpu(cpu_get_least_loaded(pool, req_mask), auto_mask);
-        }
-        else
-        {
-            cpu_get(pool, cpumask_first(req_mask));
-        }
-    }
-
-    irq = dh_irq_alloc(pool, irq_index, cpumask_empty(auto_mask) ? req_mask : auto_mask);
-    if (IS_ERR_OR_NULL(irq))
-    {
-        LOG_ERR("dh_irq_alloc failed, irq=%p\n", irq);
-        return irq;
-    }
-    free_cpumask_var(auto_mask);
-
-    return irq;
-}
-
-/* Looking for the IRQ with the smallest refcount that fits req_mask.
- * If pool is sf_comp_pool, then we are looking for an IRQ with any of the
- * requested CPUs in req_mask.
- * for example: req_mask = 0xf, irq0_mask = 0x10, irq1_mask = 0x1. irq0_mask
- * isn't subset of req_mask, so we will skip it. irq1_mask is subset of req_mask,
- * we don't skip it.
- * If pool is sf_ctrl_pool, then all IRQs have the same mask, so any IRQ will
- * fit. And since mask is subset of itself, we will pass the first if bellow.
- */
-static struct dh_irq *irq_pool_find_least_loaded(struct dh_irq_pool *pool, const struct cpumask *req_mask)
-{
-    int32_t start        = pool->xa_num_irqs.min;
-    int32_t end          = pool->xa_num_irqs.max;
-    struct dh_irq *irq   = NULL;
-    struct dh_irq *iter;
-    int32_t irq_refcount = 0;
-    unsigned long index;
-
-    lockdep_assert_held(&pool->lock);
-    xa_for_each_range(&pool->irqs, index, iter, start, end)
-    {
-        struct cpumask *iter_mask = dh_irq_get_affinity_mask(iter);
-        int32_t iter_refcount = dh_irq_read_locked(iter);
-
-        if (!cpumask_subset(iter_mask, req_mask))
-        {
-            /* skip IRQs with a mask which is not subset of req_mask */
-            continue;
-        }
-        if (iter_refcount < pool->min_threshold)
-        {
-            /* If we found an IRQ with less than min_thres, return it */
-            return iter;
-        }
-        if (!irq || iter_refcount < irq_refcount)
-        {
-            /* In case we won't find an IRQ with less than min_thres,
-             * keep a pointer to the least used IRQ
-             */
-            irq_refcount = iter_refcount;
-            irq = iter;
-        }
-    }
-
-    return irq;
-}
-
-/**
- * dh_irq_affinity_request - request an IRQ according to the given mask.
- * @pool: IRQ pool to request from.
- * @req_mask: cpumask requested for this IRQ.
- *
- * This function returns a pointer to IRQ, or ERR_PTR in case of error.
- */
-struct dh_irq *dh_irq_affinity_request(struct dh_irq_pool *pool, const struct cpumask *req_mask)
-{
-    struct dh_irq *least_loaded_irq = NULL;
-    struct dh_irq *new_irq = NULL;
-
-    mutex_lock(&pool->lock);
-
-    least_loaded_irq = irq_pool_find_least_loaded(pool, req_mask);
-    if (least_loaded_irq && dh_irq_read_locked(least_loaded_irq) < pool->min_threshold)
-    {
-        LOG_ERR("least_loaded_irq error: pool->min_threshold=%d\r\n", pool->min_threshold);
-        goto out;
-    }
-
-    /* We didn't find an IRQ with less than min_thres, try to allocate a new IRQ */
-    new_irq = irq_pool_request_irq(pool, req_mask);
-    if (IS_ERR_OR_NULL(new_irq))
-    {
-        if (!least_loaded_irq)
-        {
-            /* We failed to create an IRQ and we didn't find an IRQ */
-            LOG_ERR("Didn't find a matching IRQ. err = %ld\n", PTR_ERR(new_irq));
-            mutex_unlock(&pool->lock);
-            return new_irq;
-        }
-        /* We failed to create a new IRQ for the requested affinity,
-         * sharing existing IRQ.
-         */
-        LOG_ERR("new_irq error\r\n");
-        goto out;
-    }
-
-    least_loaded_irq = new_irq;
-    goto unlock;
-
-out:
-    dh_irq_get_locked(least_loaded_irq);
-    if (dh_irq_read_locked(least_loaded_irq) > pool->max_threshold)
-        LOG_DEBUG("IRQ %u overloaded, pool_name: %s, %u EQs on this irq\n",
-               pci_irq_vector(pool->dev->pdev, dh_irq_get_index(least_loaded_irq)),
-               pool->name, dh_irq_read_locked(least_loaded_irq) / DH_EQ_REFS_PER_IRQ);
-unlock:
-    mutex_unlock(&pool->lock);
-    return least_loaded_irq;
-}
-
-void dh_irq_affinity_irqs_release(struct dh_irq_pool *pool, struct dh_irq **irqs, int32_t num_irqs)
-{
-    int32_t i;
-
-    for (i = 0; i < num_irqs; i++)
-    {
-        int32_t cpu = cpumask_first(dh_irq_get_affinity_mask(irqs[i]));
-
-        synchronize_irq(pci_irq_vector(pool->dev->pdev, dh_irq_get_index(irqs[i])));
-
-        if (pool->irqs_per_cpu)
-        {
-            cpu_put(pool, cpu);
-        }
-    }
-}
-
-/**
- * dh_irq_affinity_irqs_request_auto - request one or more IRQs for zxdh device.
- * @pool: requesting the IRQs from the irqs pool.
- * @num_irqs: number of IRQs to request.
- * @irqs: an output array of IRQs pointers.
- *
- * Each IRQ is bounded to at most 1 CPU.
- * This function is requesting IRQs according to the default assignment.
- * The default assignment policy is:
- * - in each iteration, request the least loaded IRQ which is not bound to any
- *   CPU of the previous IRQs requested.
- *
- * This function returns the number of IRQs requested, (which might be smaller than
- * @nirqs), if successful, or a negative error code in case of an error.
- */
-int32_t dh_irq_affinity_irqs_request_auto(struct dh_irq_pool *pool, struct dh_irq **irqs, int32_t num_irqs)
-{
-    cpumask_var_t req_mask;
-    struct dh_irq *irq = NULL;
-    int32_t i = 0;
-
-    if (!zalloc_cpumask_var(&req_mask, GFP_KERNEL))
-    {
-        LOG_ERR("zalloc_cpumask_var failed\n");
-        return -ENOMEM;
-    }
-
-    cpumask_copy(req_mask, cpu_online_mask);
-    for (i = 0; i < num_irqs; i++)
-    {
-        irq = irq_pool_request_irq(pool, req_mask);
-        if (IS_ERR_OR_NULL(irq))
-        {
-            LOG_INFO("irq_pool_request_irq %d failed, req_mask=%p, irq=%p, break\n", i, req_mask, irq);
-            break;
-        }
-
-        irqs[i] = irq;
-        if (i < (num_online_cpus() - 1))
-        {
-            cpumask_clear_cpu(cpumask_first(dh_irq_get_affinity_mask(irq)), req_mask);
-        }
-        LOG_DEBUG("IRQ %u mapped to cpu %*pbl, %u EQs on this irq\n",
-               pci_irq_vector(pool->dev->pdev, dh_irq_get_index(irq)),
-               cpumask_pr_args(dh_irq_get_affinity_mask(irq)),
-               dh_irq_read_locked(irq) / DH_EQ_REFS_PER_IRQ);
-    }
-
-    free_cpumask_var(req_mask);
-    if (i != num_irqs)
-    {
-        LOG_ERR("Failed to request %d irq_num, %d irq_num requested\n", num_irqs, i);
-        dh_irq_affinity_irqs_release(pool, irqs, i);
-        dh_irqs_release_vectors(irqs, i);
-        return PTR_ERR(irq);
-    }
-
-    return i;
-}
\ No newline at end of file
+#include <linux/dinghai/dinghai_irq.h>
+#include <linux/dinghai/pci_irq.h>
+#include <linux/dinghai/helper.h>
+
+static void cpu_put(struct dh_irq_pool *pool, int32_t cpu)
+{
+	pool->irqs_per_cpu[cpu]--;
+}
+
+static void cpu_get(struct dh_irq_pool *pool, int32_t cpu)
+{
+	pool->irqs_per_cpu[cpu]++;
+}
+
+/* Gets the least loaded CPU. e.g.: the CPU with least IRQs bound to it */
+static int32_t cpu_get_least_loaded(struct dh_irq_pool *pool,
+									const struct cpumask *req_mask)
+{
+	int32_t best_cpu = -1;
+	int32_t cpu;
+
+	for_each_cpu_and(cpu, req_mask, cpu_online_mask) {
+		/* CPU has zero IRQs on it. No need to search any more CPUs. */
+		if (!pool->irqs_per_cpu[cpu]) {
+			best_cpu = cpu;
+			break;
+		}
+		if (best_cpu < 0) {
+			best_cpu = cpu;
+		}
+		if (pool->irqs_per_cpu[cpu] < pool->irqs_per_cpu[best_cpu]) {
+			best_cpu = cpu;
+		}
+	}
+
+	if (best_cpu == -1) {
+		/* There isn't online CPUs in req_mask */
+		LOG_ERR("NO online CPUs in req_mask (%*pbl)\n",
+				cpumask_pr_args(req_mask));
+		best_cpu = cpumask_first(cpu_online_mask);
+	}
+	pool->irqs_per_cpu[best_cpu]++;
+
+	return best_cpu;
+}
+
+/* Creating an IRQ from irq_pool */
+struct dh_irq *irq_pool_request_irq(struct dh_irq_pool *pool,
+									const struct cpumask *req_mask)
+{
+	cpumask_var_t auto_mask;
+	struct dh_irq *irq = NULL;
+	u32 irq_index = 0;
+	int32_t err = 0;
+
+	if (!zalloc_cpumask_var(&auto_mask, GFP_KERNEL)) {
+		LOG_ERR("%s[%d] ERR_PTR(-ENOMEM)=0x%llx", __func__, __LINE__,
+				(unsigned long long)ERR_PTR(-ENOMEM));
+		return ERR_PTR(-ENOMEM);
+	}
+
+	err = xa_alloc(&pool->irqs, &irq_index, NULL, pool->xa_num_irqs,
+				   GFP_KERNEL);
+	if (err) {
+		if (err == -EBUSY) {
+			err = -EUSERS;
+		}
+		LOG_ERR("%s[%d] ERR_PTR(err)=0x%llx", __func__, __LINE__,
+				(unsigned long long)ERR_PTR(err));
+		return ERR_PTR(err);
+	}
+
+	if (pool->irqs_per_cpu) {
+		if (cpumask_weight(req_mask) > 1) {
+			/* if req_mask contain more then one CPU, set the least loadad CPU
+       * of req_mask
+       */
+			cpumask_set_cpu(cpu_get_least_loaded(pool, req_mask), auto_mask);
+		} else {
+			cpu_get(pool, cpumask_first(req_mask));
+		}
+	}
+
+	irq = dh_irq_alloc(pool, irq_index,
+					   cpumask_empty(auto_mask) ? req_mask : auto_mask);
+	if (IS_ERR_OR_NULL(irq)) {
+		LOG_ERR("dh_irq_alloc failed, irq=%p\n", irq);
+		return irq;
+	}
+	free_cpumask_var(auto_mask);
+
+	LOG_DEBUG("irq=0x%llx, irq_index=%d[%d]", (unsigned long long)irq,
+			  irq_index, irq->index);
+	return irq;
+}
+
+/* Looking for the IRQ with the smallest refcount that fits req_mask.
+ * If pool is sf_comp_pool, then we are looking for an IRQ with any of the
+ * requested CPUs in req_mask.
+ * for example: req_mask = 0xf, irq0_mask = 0x10, irq1_mask = 0x1. irq0_mask
+ * isn't subset of req_mask, so we will skip it. irq1_mask is subset of
+ * req_mask, we don't skip it. If pool is sf_ctrl_pool, then all IRQs have the
+ * same mask, so any IRQ will fit. And since mask is subset of itself, we will
+ * pass the first if bellow.
+ */
+static struct dh_irq *irq_pool_find_least_loaded(struct dh_irq_pool *pool,
+												 const struct cpumask *req_mask)
+{
+	int32_t start = pool->xa_num_irqs.min;
+	int32_t end = pool->xa_num_irqs.max;
+	struct dh_irq *irq = NULL;
+	struct dh_irq *iter;
+	int32_t irq_refcount = 0;
+	unsigned long index;
+
+	lockdep_assert_held(&pool->lock);
+	xa_for_each_range(&pool->irqs, index, iter, start, end) {
+		struct cpumask *iter_mask = dh_irq_get_affinity_mask(iter);
+		int32_t iter_refcount = dh_irq_read_locked(iter);
+
+		if (!cpumask_subset(iter_mask, req_mask)) {
+			/* skip IRQs with a mask which is not subset of req_mask */
+			continue;
+		}
+		if (iter_refcount < pool->min_threshold) {
+			/* If we found an IRQ with less than min_thres, return it */
+			return iter;
+		}
+		if (!irq || iter_refcount < irq_refcount) {
+			/* In case we won't find an IRQ with less than min_thres,
+       * keep a pointer to the least used IRQ
+       */
+			irq_refcount = iter_refcount;
+			irq = iter;
+		}
+	}
+
+	return irq;
+}
+
+/**
+ * dh_irq_affinity_request - request an IRQ according to the given mask.
+ * @pool: IRQ pool to request from.
+ * @req_mask: cpumask requested for this IRQ.
+ *
+ * This function returns a pointer to IRQ, or ERR_PTR in case of error.
+ */
+struct dh_irq *dh_irq_affinity_request(struct dh_irq_pool *pool,
+									   const struct cpumask *req_mask)
+{
+	struct dh_irq *least_loaded_irq = NULL;
+	struct dh_irq *new_irq = NULL;
+
+	LOG_DEBUG("start");
+	mutex_lock(&pool->lock);
+
+	least_loaded_irq = irq_pool_find_least_loaded(pool, req_mask);
+	if (least_loaded_irq &&
+		dh_irq_read_locked(least_loaded_irq) < pool->min_threshold) {
+		LOG_ERR("least_loaded_irq error: pool->min_threshold=%d\r\n",
+				pool->min_threshold);
+		goto out;
+	}
+
+	/* We didn't find an IRQ with less than min_thres, try to allocate a new IRQ
+   */
+	new_irq = irq_pool_request_irq(pool, req_mask);
+	if (IS_ERR_OR_NULL(new_irq)) {
+		if (!least_loaded_irq) {
+			/* We failed to create an IRQ and we didn't find an IRQ */
+			LOG_ERR("Didn't find a matching IRQ. err = %ld\n",
+					PTR_ERR(new_irq));
+			mutex_unlock(&pool->lock);
+			return new_irq;
+		}
+		/* We failed to create a new IRQ for the requested affinity,
+     * sharing existing IRQ.
+     */
+		LOG_ERR("new_irq error\r\n");
+		goto out;
+	}
+
+	least_loaded_irq = new_irq;
+	goto unlock;
+
+out:
+	dh_irq_get_locked(least_loaded_irq);
+	if (dh_irq_read_locked(least_loaded_irq) > pool->max_threshold)
+		LOG_DEBUG("IRQ %u overloaded, pool_name: %s, %u EQs on this irq\n",
+				  pci_irq_vector(pool->dev->pdev,
+								 dh_irq_get_index(least_loaded_irq)),
+				  pool->name,
+				  dh_irq_read_locked(least_loaded_irq) / DH_EQ_REFS_PER_IRQ);
+unlock:
+	mutex_unlock(&pool->lock);
+	LOG_DEBUG("least_loaded_irq=0x%llx", (unsigned long long)least_loaded_irq);
+	return least_loaded_irq;
+}
+
+void dh_irq_affinity_irqs_release(struct dh_irq_pool *pool,
+								  struct dh_irq **irqs, int32_t num_irqs)
+{
+	int32_t i;
+
+	for (i = 0; i < num_irqs; i++) {
+		int32_t cpu = cpumask_first(dh_irq_get_affinity_mask(irqs[i]));
+
+		synchronize_irq(
+				pci_irq_vector(pool->dev->pdev, dh_irq_get_index(irqs[i])));
+
+		if (pool->irqs_per_cpu) {
+			cpu_put(pool, cpu);
+		}
+	}
+}
+
+/**
+ * dh_irq_affinity_irqs_request_auto - request one or more IRQs for zxdh device.
+ * @pool: requesting the IRQs from the irqs pool.
+ * @num_irqs: number of IRQs to request.
+ * @irqs: an output array of IRQs pointers.
+ *
+ * Each IRQ is bounded to at most 1 CPU.
+ * This function is requesting IRQs according to the default assignment.
+ * The default assignment policy is:
+ * - in each iteration, request the least loaded IRQ which is not bound to any
+ *   CPU of the previous IRQs requested.
+ *
+ * This function returns the number of IRQs requested, (which might be smaller
+ * than
+ * @nirqs), if successful, or a negative error code in case of an error.
+ */
+int32_t dh_irq_affinity_irqs_request_auto(struct dh_irq_pool *pool,
+										  struct dh_irq **irqs,
+										  int32_t num_irqs)
+{
+	cpumask_var_t req_mask;
+	struct dh_irq *irq = NULL;
+	int32_t i = 0;
+
+	if (!zalloc_cpumask_var(&req_mask, GFP_KERNEL)) {
+		LOG_ERR("zalloc_cpumask_var failed\n");
+		return -ENOMEM;
+	}
+
+	cpumask_copy(req_mask, cpu_online_mask);
+	for (i = 0; i < num_irqs; i++) {
+		irq = irq_pool_request_irq(pool, req_mask);
+		if (IS_ERR_OR_NULL(irq)) {
+			LOG_INFO(
+					"irq_pool_request_irq %d failed, req_mask=%p, irq=%p, break\n",
+					i, req_mask, irq);
+			break;
+		}
+
+		irqs[i] = irq;
+		if (i < (num_online_cpus() - 1)) {
+			cpumask_clear_cpu(cpumask_first(dh_irq_get_affinity_mask(irq)),
+							  req_mask);
+		}
+		LOG_DEBUG("IRQ %u mapped to cpu %*pbl, %u EQs on this irq\n",
+				  pci_irq_vector(pool->dev->pdev, dh_irq_get_index(irq)),
+				  cpumask_pr_args(dh_irq_get_affinity_mask(irq)),
+				  dh_irq_read_locked(irq) / DH_EQ_REFS_PER_IRQ);
+	}
+
+	free_cpumask_var(req_mask);
+	if (i == 0) {
+		LOG_ERR("request irq_num is 0\n");
+		return PTR_ERR(irq);
+	}
+
+	return i;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/lag/lag.c b/src/net/drivers/net/ethernet/dinghai/lag/lag.c
index f1429fcb2393bb9d6b36fdc8e3529a17b7349092..58d109790a27cb4c50e92dae3ab982fab06aa03d 100644
--- a/src/net/drivers/net/ethernet/dinghai/lag/lag.c
+++ b/src/net/drivers/net/ethernet/dinghai/lag/lag.c
@@ -3,85 +3,79 @@
 #include <linux/kref.h>
 #include <linux/dinghai/lag.h>
 #include <net/bonding.h>
-
 #include "lag.h"
 #include "en_pf.h"
 #include "dpp_tbl_api.h"
 
-
 static DEFINE_SPINLOCK(lag_lock);
 static DEFINE_MUTEX(zxdh_intf_mutex);
 
 void zxdh_dev_list_lock(void)
 {
-    mutex_lock(&zxdh_intf_mutex);
+	mutex_lock(&zxdh_intf_mutex);
 }
 
 void zxdh_dev_list_unlock(void)
 {
-    mutex_unlock(&zxdh_intf_mutex);
+	mutex_unlock(&zxdh_intf_mutex);
 }
 
 int zxdh_dev_list_trylock(void)
 {
-    return mutex_trylock(&zxdh_intf_mutex);
+	return mutex_trylock(&zxdh_intf_mutex);
 }
 
 struct zxdh_lag *lag_get_ldev(struct dh_core_dev *dh_dev)
 {
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
 
-    return pf_dev->ldev;
+	return pf_dev->ldev;
 }
 
 void lag_set_ldev(struct dh_core_dev *dh_dev, struct zxdh_lag *ldev)
 {
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
 
-    pf_dev->ldev = ldev;
+	pf_dev->ldev = ldev;
 }
 
 void ldev_kref_free(struct kref *ref)
 {
-    struct zxdh_lag *ldev = container_of(ref, struct zxdh_lag, ref);
+	struct zxdh_lag *ldev = container_of(ref, struct zxdh_lag, ref);
 
-    if (ldev->nb.notifier_call)
-    {
-        unregister_netdevice_notifier_net(&init_net, &ldev->nb);
-    }
+	if (ldev->nb.notifier_call) {
+		unregister_netdevice_notifier_net(&init_net, &ldev->nb);
+	}
 
-    cancel_delayed_work_sync(&ldev->bond_work);
-    destroy_workqueue(ldev->wq);
+	cancel_delayed_work_sync(&ldev->bond_work);
+	destroy_workqueue(ldev->wq);
 
-    lag_set_ldev(ldev->parent, NULL);
-    kfree(ldev);
+	lag_set_ldev(ldev->parent, NULL);
+	kfree(ldev);
 
-    LAG_LOG_INFO("pf lag device alloced memory free \n");
+	LAG_LOG_INFO("pf lag device alloced memory free \n");
 }
 
 static void zxdh_queue_bond_work(struct zxdh_lag *ldev, unsigned long delay)
 {
-    queue_delayed_work(ldev->wq, &ldev->bond_work, delay);
+	queue_delayed_work(ldev->wq, &ldev->bond_work, delay);
 }
 
 void lag_dev_release(struct dh_core_dev *dh_dev, struct zxdh_lag *ldev)
 {
-    int i;
-    struct dh_core_dev *parent;
+	int i;
+	struct dh_core_dev *parent;
 
-    for (i = 0; i < ZXDH_MAX_PORTS; i++)
-    {
-        if (!ldev->lagfunc[i].dev)
-        {
-            continue;
-        }
+	for (i = 0; i < ZXDH_MAX_PORTS; i++) {
+		if (!ldev->lagfunc[i].dev) {
+			continue;
+		}
 
-        parent = ldev->lagfunc[i].dev->parent;
-        if (parent == dh_dev)
-        {
-            ldev->lagfunc[i].dev = NULL;
-        }
-    }
+		parent = ldev->lagfunc[i].dev->parent;
+		if (parent == dh_dev) {
+			ldev->lagfunc[i].dev = NULL;
+		}
+	}
 }
 
 /**
@@ -91,41 +85,37 @@ void lag_dev_release(struct dh_core_dev *dh_dev, struct zxdh_lag *ldev)
  **/
 int32_t lag_get_netdev_idx(struct zxdh_lag *ldev, struct net_device *ndev)
 {
-    int i;
+	int i;
 
-    for (i = 0; i < ZXDH_MAX_PORTS; i++)
-    {
-        if (ldev->lagfunc[i].netdev == ndev)
-        {
-            return i;
-        }
-    }
+	for (i = 0; i < ZXDH_MAX_PORTS; i++) {
+		if (ldev->lagfunc[i].netdev == ndev) {
+			return i;
+		}
+	}
 
-    return -ENOENT;
+	return -ENOENT;
 }
 
 void ldev_remove_netdev(struct dh_core_dev *dh_dev, struct net_device *netdev)
 {
-    int32_t index = 0;
-    struct zxdh_lag *ldev;
+	int32_t index = 0;
+	struct zxdh_lag *ldev;
 
-    ldev = lag_get_ldev(dh_dev->parent);
-    if (!ldev)
-    {
-        return;
-    }
+	ldev = lag_get_ldev(dh_dev->parent);
+	if (!ldev) {
+		return;
+	}
 
-    spin_lock(&lag_lock);
+	spin_lock(&lag_lock);
 
-    index = lag_get_netdev_idx(ldev, netdev);
-    if (index < 0)
-    {
-        goto out;
-    }
+	index = lag_get_netdev_idx(ldev, netdev);
+	if (index < 0) {
+		goto out;
+	}
 
-    ldev->lagfunc[index].netdev = NULL;
+	ldev->lagfunc[index].netdev = NULL;
 out:
-    spin_unlock(&lag_lock);
+	spin_unlock(&lag_lock);
 }
 
 /**
@@ -135,43 +125,43 @@ out:
  * @netdev: netdev to adding for
  * @attr: some configs info from aux
  **/
-static void ldev_add_netdev(struct dh_core_dev *dh_dev,
-        uint16_t id, struct net_device *netdev, struct zxdh_lag_attrs *attr)
+static void ldev_add_netdev(struct dh_core_dev *dh_dev, uint16_t id,
+							struct net_device *netdev,
+							struct zxdh_lag_attrs *attr)
 {
-    struct zxdh_lag *ldev;
+	struct zxdh_lag *ldev;
 
-    if (id >= ZXDH_MAX_PORTS)
-    {
-        LAG_LOG_ERR("%s: index[%hu] out of range. \n", netdev_name(netdev), id);
-        return;
-    }
+	if (id >= ZXDH_MAX_PORTS) {
+		LAG_LOG_ERR("%s: index[%hu] out of range. \n", netdev_name(netdev), id);
+		return;
+	}
 
-    ldev = lag_get_ldev(dh_dev->parent);
+	ldev = lag_get_ldev(dh_dev->parent);
 
-    spin_lock(&lag_lock);
-    ldev->lagfunc[id].dev = dh_dev;
-    ldev->lagfunc[id].netdev = netdev;
-    ldev->lagfunc[id].attrs = *attr;
-    ldev->lagfunc[id].valid = true;
-    ldev->tracker.netdev_state[id].link_up = 0;
-    ldev->tracker.netdev_state[id].tx_enabled = 0;
-    ldev->lag_func_index++;
-    spin_unlock(&lag_lock);
+	spin_lock(&lag_lock);
+	ldev->lagfunc[id].dev = dh_dev;
+	ldev->lagfunc[id].netdev = netdev;
+	ldev->lagfunc[id].attrs = *attr;
+	ldev->lagfunc[id].valid = true;
+	ldev->tracker.netdev_state[id].link_up = 0;
+	ldev->tracker.netdev_state[id].tx_enabled = 0;
+	ldev->lag_func_index++;
+	spin_unlock(&lag_lock);
 
-    zxdh_queue_bond_work(ldev, 0);
+	zxdh_queue_bond_work(ldev, 0);
 }
 
-static bool zxdh_netdev_belongs(struct zxdh_lag *ldev, struct net_device *netdev)
+static bool zxdh_netdev_belongs(struct zxdh_lag *ldev,
+								struct net_device *netdev)
 {
-    int32_t idx = 0;
+	int32_t idx = 0;
 
-    idx = lag_get_netdev_idx(ldev, netdev);
-    if (idx < 0)
-    {
-        return false;
-    }
+	idx = lag_get_netdev_idx(ldev, netdev);
+	if (idx < 0) {
+		return false;
+	}
 
-    return true;
+	return true;
 }
 
 /**
@@ -181,90 +171,84 @@ static bool zxdh_netdev_belongs(struct zxdh_lag *ldev, struct net_device *netdev
  * @ndev: upper netdev
  * @info: upper dev attribute passed from bonding
  **/
-static int handle_changeupper_event(struct zxdh_lag *ldev,
-                     struct lag_tracker *tracker,
-                     struct net_device *ndev,
-                     struct netdev_notifier_changeupper_info *info)
-{
-    struct net_device *upper = info->upper_dev, *ndev_tmp, *slave_dev;
-    struct netdev_lag_upper_info *lag_upper_info = NULL;
-    bool is_bonded = false;
-    bool mode_supported = false;
-    int changed = 0;
-    int bond_status = 0;
-    int num_slaves = 0;
-    int idx = 0;
-
-    if (!netif_is_lag_master(upper))
-    {
-        LAG_LOG_INFO("changeupper received, but not master. \n");
-        return 0;
-    }
-
-    if (strcmp("bondxi5", upper->name))
-    {
-        slave_dev = netdev_notifier_info_to_dev((void *)info);
-        if (!zxdh_netdev_belongs(ldev, slave_dev))
-        {
-            LAG_LOG_INFO("%s is not dinghai bond, ignore. \n", upper->name);
-            return 0;
-        }
-    }
-
-    if (info->linking)
-    {
-        lag_upper_info = info->upper_info;
-    }
-
-    rcu_read_lock();
-    for_each_netdev_in_bond_rcu(upper, ndev_tmp)
-    {
-        idx = lag_get_netdev_idx(ldev, ndev_tmp);
-        if (idx >= 0)
-        {
-            bond_status |= (1 << idx);
-        }
-
-        num_slaves++;
-    }
-    rcu_read_unlock();
-
-    ldev->slaves = bond_status;
-
-    /* None of this lagdev's netdevs are slaves of this master. */
-    if (!bond_status)
-    {
-        is_bonded = false;
-        goto out;
-    }
-
-    if (lag_upper_info)
-    {
-        tracker->tx_type = lag_upper_info->tx_type;
-        tracker->hash_type = lag_upper_info->hash_type;
-    }
-
-    LAG_LOG_INFO("lag tx type: %d [%d-active-backup %d-lacp], hash type %d. \n",
-            tracker->tx_type, NETDEV_LAG_TX_TYPE_ACTIVEBACKUP, NETDEV_LAG_TX_TYPE_HASH, tracker->hash_type);
-
-    /* Lag mode must be activebackup or hash. */
-    mode_supported = (tracker->tx_type == NETDEV_LAG_TX_TYPE_ACTIVEBACKUP) ||
-             (tracker->tx_type == NETDEV_LAG_TX_TYPE_HASH);
-
-    /* if slaves exist */
-    is_bonded = !!bond_status && mode_supported;
+static int
+handle_changeupper_event(struct zxdh_lag *ldev, struct lag_tracker *tracker,
+						 struct net_device *ndev,
+						 struct netdev_notifier_changeupper_info *info)
+{
+	struct net_device *upper = info->upper_dev, *ndev_tmp, *slave_dev;
+	struct netdev_lag_upper_info *lag_upper_info = NULL;
+	bool is_bonded = false;
+	bool mode_supported = false;
+	int changed = 0;
+	int bond_status = 0;
+	int num_slaves = 0;
+	int idx = 0;
+
+	if (!netif_is_lag_master(upper)) {
+		LAG_LOG_INFO("changeupper received, but not master. \n");
+		return 0;
+	}
+
+	if (strcmp("bondxi5", upper->name)) {
+		slave_dev = netdev_notifier_info_to_dev((void *)info);
+		if (!zxdh_netdev_belongs(ldev, slave_dev)) {
+			LAG_LOG_INFO("%s is not dinghai bond, ignore. \n", upper->name);
+			return 0;
+		}
+	}
+
+	if (info->linking) {
+		lag_upper_info = info->upper_info;
+	}
+
+	rcu_read_lock();
+	for_each_netdev_in_bond_rcu(upper, ndev_tmp) {
+		idx = lag_get_netdev_idx(ldev, ndev_tmp);
+		if (idx >= 0) {
+			bond_status |= (1 << idx);
+		}
+
+		num_slaves++;
+	}
+	rcu_read_unlock();
+
+	ldev->slaves = bond_status;
+
+	/* None of this lagdev's netdevs are slaves of this master. */
+	if (!bond_status) {
+		is_bonded = false;
+		goto out;
+	}
+
+	if (lag_upper_info) {
+		tracker->tx_type = lag_upper_info->tx_type;
+		tracker->hash_type = lag_upper_info->hash_type;
+	}
+
+	LAG_LOG_INFO("lag tx type: %d [%d-active-backup %d-lacp], hash type %d. \n",
+				 tracker->tx_type, NETDEV_LAG_TX_TYPE_ACTIVEBACKUP,
+				 NETDEV_LAG_TX_TYPE_HASH, tracker->hash_type);
+
+	/* Lag mode must be activebackup or hash. */
+	mode_supported = (tracker->tx_type == NETDEV_LAG_TX_TYPE_ACTIVEBACKUP) ||
+					 (tracker->tx_type == NETDEV_LAG_TX_TYPE_HASH);
+
+	/* if slaves exist */
+	is_bonded = !!bond_status && mode_supported;
 
 out:
-    if ((tracker->is_bonded != is_bonded))
-    {
-        tracker->is_bonded = is_bonded;
-        changed = 1;
-    }
+	if ((tracker->is_bonded != is_bonded)) {
+		tracker->is_bonded = is_bonded;
+		changed = 1;
+	}
 
-    LAG_LOG_INFO("master: %s slaves num: %d, mask: 0x%x, changed: %d, mode supported: %s\n",
-            upper->name, num_slaves, bond_status, changed, mode_supported ? "true" : "false");
+	LAG_LOG_INFO("master: %s slaves num: %d, mask: 0x%x, changed: %d, mode "
+				 "supported: %s\n",
+				 upper->name, num_slaves, bond_status, changed,
+				 mode_supported ? "true" : "false");
 
-    return changed;
+	return changed;
 }
 
 /**
@@ -274,527 +258,489 @@ out:
  * @ndev: lower netdev
  * @info: lower dev attribute passed from bonding
  **/
-static int handle_changelowerstate_event(struct zxdh_lag *ldev,
-                          struct lag_tracker *tracker,
-                          struct net_device *ndev,
-                          struct netdev_notifier_changelowerstate_info *info)
+static int handle_changelowerstate_event(
+		struct zxdh_lag *ldev, struct lag_tracker *tracker,
+		struct net_device *ndev,
+		struct netdev_notifier_changelowerstate_info *info)
 {
-    struct netdev_lag_lower_state_info *lag_lower_info;
-    int idx;
+	struct netdev_lag_lower_state_info *lag_lower_info;
+	struct slave *slave;
+	int idx;
 
-    if (!netif_is_lag_port(ndev))
-    {
-        return 0;
-    }
+	if (!netif_is_lag_port(ndev)) {
+		return 0;
+	}
 
-    idx = lag_get_netdev_idx(ldev, ndev);
-    if (idx < 0)
-    {
-        return 0;
-    }
+	idx = lag_get_netdev_idx(ldev, ndev);
+	if (idx < 0) {
+		return 0;
+	}
 
-    lag_lower_info = info->lower_state_info;
-    if (!lag_lower_info)
-    {
-        return 0;
-    }
+	lag_lower_info = info->lower_state_info;
+	if (!lag_lower_info) {
+		return 0;
+	}
 
-    /* update netdev state from bonding */
-    tracker->netdev_state[idx] = *lag_lower_info;
+	/* update netdev state from bonding */
+	tracker->netdev_state[idx] = *lag_lower_info;
 
-    LAG_LOG_INFO("%s: link up %u tx enable %u \n", ndev->name,
-                (uint32_t)lag_lower_info->link_up, (uint32_t)lag_lower_info->tx_enabled);
+	LAG_LOG_INFO("%s: link up %u tx enable %u \n", ndev->name,
+				 (uint32_t)lag_lower_info->link_up,
+				 (uint32_t)lag_lower_info->tx_enabled);
 
-    return 1;
+	return 1;
 }
 
 bool lag_check_aux_netdev_ready(struct zxdh_lag *ldev)
 {
-    int ix = 0;
-    int lag_netdev_cnt = 0;
-    int lag_pannel_num = zxdh_pf_get_pannel_port_num(ldev->parent);
+	int ix = 0;
+	int lag_netdev_cnt = 0;
+	int lag_pannel_num = zxdh_pf_get_pannel_port_num(ldev->parent);
 
-    for (ix = 0; ix < ZXDH_MAX_PORTS; ix++)
-    {
-        if (ldev->lagfunc[ix].netdev)
-        {
-            lag_netdev_cnt++;
-        }
-    }
+	for (ix = 0; ix < ZXDH_MAX_PORTS; ix++) {
+		if (ldev->lagfunc[ix].netdev) {
+			lag_netdev_cnt++;
+		}
+	}
 
-    return (lag_pannel_num == lag_netdev_cnt) ? true : false;
+	return (lag_pannel_num == lag_netdev_cnt) ? true : false;
 }
 
-static int lag_netdev_event(struct notifier_block *this, unsigned long event, void *ptr)
+static int lag_netdev_event(struct notifier_block *this, unsigned long event,
+							void *ptr)
 {
-    struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
-    struct lag_tracker tracker;
-    struct zxdh_lag *ldev;
-    int changed = 0;
+	struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
+	struct lag_tracker tracker;
+	struct zxdh_lag *ldev;
+	int changed = 0;
 
-    if ((event != NETDEV_CHANGEUPPER) && (event != NETDEV_CHANGELOWERSTATE))
-    {
-        return NOTIFY_DONE;
-    }
+	if ((event != NETDEV_CHANGEUPPER) && (event != NETDEV_CHANGELOWERSTATE)) {
+		return NOTIFY_DONE;
+	}
 
-    ldev = container_of(this, struct zxdh_lag, nb);
-    if (!lag_check_aux_netdev_ready(ldev))
-    {
-        return NOTIFY_DONE;
-    }
+	ldev = container_of(this, struct zxdh_lag, nb);
+	if (!lag_check_aux_netdev_ready(ldev)) {
+		return NOTIFY_DONE;
+	}
 
-    LAG_LOG_INFO("received %s\n", netdev_cmd_to_name(event));
+	netdev_info(ndev, "received %s\n", netdev_cmd_to_name(event));
 
-    tracker = ldev->tracker;
+	tracker = ldev->tracker;
 
-    switch (event)
-    {
-        case NETDEV_CHANGEUPPER:
-        {
-            changed = handle_changeupper_event(ldev, &tracker, ndev, ptr);
-            break;
-        }
-        case NETDEV_CHANGELOWERSTATE:
-        {
-            changed = handle_changelowerstate_event(ldev, &tracker, ndev, ptr);
-            break;
-        }
-    }
+	switch (event) {
+	case NETDEV_CHANGEUPPER: {
+		changed = handle_changeupper_event(ldev, &tracker, ndev, ptr);
+		break;
+	}
+	case NETDEV_CHANGELOWERSTATE: {
+		changed = handle_changelowerstate_event(ldev, &tracker, ndev, ptr);
+		break;
+	}
+	}
 
-    ldev->tracker = tracker;
+	ldev->tracker = tracker;
 
-    if (changed)
-    {
-        zxdh_queue_bond_work(ldev, 0);
-    }
+	if (changed) {
+		zxdh_queue_bond_work(ldev, 0);
+	}
 
-    return NOTIFY_DONE;
+	return NOTIFY_DONE;
 }
 
-static int32_t lag_find_first_netdev_pf_info(struct zxdh_lag *ldev, DPP_PF_INFO_T *pf_info)
+static int32_t lag_find_first_netdev_pf_info(struct zxdh_lag *ldev,
+											 DPP_PF_INFO_T *pf_info)
 {
-    int i;
-    struct lag_func *func;
+	int i;
+	struct lag_func *func;
 
-    for (i = 0; i < ZXDH_MAX_PORTS; i++)
-    {
-        func = &ldev->lagfunc[i];
+	for (i = 0; i < ZXDH_MAX_PORTS; i++) {
+		func = &ldev->lagfunc[i];
 
-        if (func->netdev)
-        {
-            pf_info->vport = func->attrs.vport;
-            pf_info->slot = func->attrs.slot_id;
-            return 0;
-        }
-    }
+		if (func->netdev) {
+			pf_info->vport = func->attrs.vport;
+			pf_info->slot = func->attrs.slot_id;
+			return 0;
+		}
+	}
 
-    return -EOPNOTSUPP;
+	return -EOPNOTSUPP;
 }
 
 static int32_t zxdh_disable_lag(struct zxdh_lag *ldev)
 {
-    int i;
-    uint8_t phy_port = 0;
-    struct lag_func *func;
-    DPP_PF_INFO_T pf_info = {0};
+	int i;
+	uint8_t phy_port = 0;
+	struct lag_func *func;
+	DPP_PF_INFO_T pf_info = { 0 };
 
-    for (i = 0; i < ZXDH_MAX_PORTS; i++)
-    {
-        func = &ldev->lagfunc[i];
+	for (i = 0; i < ZXDH_MAX_PORTS; i++) {
+		func = &ldev->lagfunc[i];
 
-        if (!func->netdev)
-        {
-            continue;
-        }
+		if (!func->netdev) {
+			continue;
+		}
 
-        pf_info.slot = func->attrs.slot_id;
-        pf_info.vport = func->attrs.vport;
-        phy_port = func->attrs.phy_port;
+		pf_info.slot = func->attrs.slot_id;
+		pf_info.vport = func->attrs.vport;
+		phy_port = func->attrs.phy_port;
 
-        dpp_lag_group_member_del(&pf_info, ZXDH_LGA_ID, phy_port);
-        dpp_panel_attr_set(&pf_info, phy_port, PANEL_FLAG_BOND_LINK_UP, LAG_FLAGS_DISABLE);
-    }
+		dpp_lag_group_member_del(&pf_info, ZXDH_LGA_ID, phy_port);
+		dpp_panel_attr_set(&pf_info, phy_port, PANEL_FLAG_BOND_LINK_UP,
+						   LAG_FLAGS_DISABLE);
+	}
 
-    ldev->flags &= ~ZXDH_LAG_MODE_FLAGS;
-    LAG_LOG_INFO("zxdh lag disabled. vport 0x%hx lag id %d.\n", pf_info.vport, ZXDH_LGA_ID);
+	ldev->flags &= ~ZXDH_LAG_MODE_FLAGS;
+	LAG_LOG_INFO("zxdh lag disabled. vport 0x%hx lag id %d.\n", pf_info.vport,
+				 ZXDH_LGA_ID);
 
-    return 0;
+	return 0;
 }
 
 static int32_t zxdh_lag_active_backup(struct zxdh_lag *ldev)
 {
-    int i;
-    bool porten = false;
-    uint8_t phy_port = ZXDH_ACTIVE_PHY_PORT_NA;
-    uint8_t active_phy_port = ZXDH_ACTIVE_PHY_PORT_NA;
-    int32_t err = 0;
-    struct lag_func *func;
-    struct lag_tracker *tracker = &ldev->tracker;
-    DPP_PF_INFO_T pf_info = {0};
-
-    err = lag_find_first_netdev_pf_info(ldev, &pf_info);
-    if (err != 0)
-    {
-        LAG_LOG_ERR("vport %d is incorrect\n", pf_info.vport);
-        return -EOPNOTSUPP;
-    }
-
-    dpp_lag_mode_set(&pf_info, ZXDH_LGA_ID, LAG_MODE_ACTIVE_BACKUP);
-
-    for (i = ZXDH_MAX_PORTS - 1; i >= 0; i--)
-    {
-        func = &ldev->lagfunc[i];
-
-        if (!func->netdev)
-        {
-            continue;
-        }
-
-        phy_port = func->attrs.phy_port;
-        pf_info.slot = func->attrs.slot_id;
-        pf_info.vport = func->attrs.vport;
-
-        dpp_lag_group_member_del(&pf_info, ZXDH_LGA_ID, phy_port);
-        dpp_panel_attr_set(&pf_info, phy_port, PANEL_FLAG_BOND_LINK_UP, LAG_FLAGS_DISABLE);
-
-        porten = tracker->netdev_state[i].tx_enabled && tracker->netdev_state[i].link_up;
-        if (porten && (ldev->slaves & (1 << i)))
-        {
-            active_phy_port = phy_port;
-            LAG_LOG_INFO("[backup]: select acitve phyport %hu pannel port %hu \n",
-                active_phy_port, func->attrs.pannel_id);
-        }
-
-        LAG_LOG_INFO("[backup]: phyport %hhu pannel port %hhu tx enable %d link up %d\n",
-                phy_port, func->attrs.pannel_id,
-                (int32_t)tracker->netdev_state[i].tx_enabled,
-                (int32_t)tracker->netdev_state[i].link_up);
-    }
-
-    if (active_phy_port != ZXDH_ACTIVE_PHY_PORT_NA)
-    {
-        dpp_lag_group_member_add(&pf_info, ZXDH_LGA_ID, active_phy_port);
-        dpp_panel_attr_set(&pf_info, active_phy_port, PANEL_FLAG_BOND_LINK_UP, LAG_FLAGS_ENABLE);
-    }
-
-    ldev->flags |= ZXDH_LAG_FLAG_BACKUP;
-
-    return 0;
+	int i;
+	bool porten = false;
+	uint8_t phy_port = ZXDH_ACTIVE_PHY_PORT_NA;
+	uint8_t active_phy_port = ZXDH_ACTIVE_PHY_PORT_NA;
+	int32_t err = 0;
+	struct lag_func *func;
+	struct lag_tracker *tracker = &ldev->tracker;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	err = lag_find_first_netdev_pf_info(ldev, &pf_info);
+	if (err != 0) {
+		LAG_LOG_ERR("vport %d is incorrect\n", pf_info.vport);
+		return -EOPNOTSUPP;
+	}
+
+	dpp_lag_mode_set(&pf_info, ZXDH_LGA_ID, LAG_MODE_ACTIVE_BACKUP);
+
+	for (i = ZXDH_MAX_PORTS - 1; i >= 0; i--) {
+		func = &ldev->lagfunc[i];
+
+		if (!func->netdev) {
+			continue;
+		}
+
+		phy_port = func->attrs.phy_port;
+		pf_info.slot = func->attrs.slot_id;
+		pf_info.vport = func->attrs.vport;
+
+		dpp_lag_group_member_del(&pf_info, ZXDH_LGA_ID, phy_port);
+		dpp_panel_attr_set(&pf_info, phy_port, PANEL_FLAG_BOND_LINK_UP,
+						   LAG_FLAGS_DISABLE);
+
+		porten = tracker->netdev_state[i].tx_enabled &&
+				 tracker->netdev_state[i].link_up;
+		if (porten && (ldev->slaves & (1 << i))) {
+			active_phy_port = phy_port;
+			LAG_LOG_INFO(
+					"[backup]: select acitve phyport %hu pannel port %hu \n",
+					active_phy_port, func->attrs.pannel_id);
+		}
+
+		LAG_LOG_INFO(
+				"[backup]: phyport %hhu pannel port %hhu tx enable %d link up %d\n",
+				phy_port, func->attrs.pannel_id,
+				(int32_t)tracker->netdev_state[i].tx_enabled,
+				(int32_t)tracker->netdev_state[i].link_up);
+	}
+
+	if (active_phy_port != ZXDH_ACTIVE_PHY_PORT_NA) {
+		dpp_lag_group_member_add(&pf_info, ZXDH_LGA_ID, active_phy_port);
+		dpp_panel_attr_set(&pf_info, active_phy_port, PANEL_FLAG_BOND_LINK_UP,
+						   LAG_FLAGS_ENABLE);
+	}
+
+	ldev->flags |= ZXDH_LAG_FLAG_BACKUP;
+
+	return 0;
 }
 
 uint32_t zxdh_covert_hash_type_2_np(uint32_t hash_type)
 {
-    uint32_t np_hash_type = 0;
-
-    switch (hash_type)
-    {
-        case NETDEV_LAG_HASH_L2:
-        {
-            np_hash_type = ZXDH_NP_HASH_TYPE_L2;
-            break;
-        }
-        case NETDEV_LAG_HASH_L23:
-        {
-            np_hash_type = ZXDH_NP_HASH_TYPE_L23;
-            break;
-        }
-        case NETDEV_LAG_HASH_L34:
-        {
-            np_hash_type = ZXDH_NP_HASH_TYPE_L34;
-            break;
-        }
-        default:
-        {
-            np_hash_type = ZXDH_NP_HASH_TYPE_DEFAULT;
-            break;
-        }
-    }
-
-    return np_hash_type;
+	uint32_t np_hash_type = 0;
+
+	switch (hash_type) {
+	case NETDEV_LAG_HASH_L2: {
+		np_hash_type = ZXDH_NP_HASH_TYPE_L2;
+		break;
+	}
+	case NETDEV_LAG_HASH_L23: {
+		np_hash_type = ZXDH_NP_HASH_TYPE_L23;
+		break;
+	}
+	case NETDEV_LAG_HASH_L34: {
+		np_hash_type = ZXDH_NP_HASH_TYPE_L34;
+		break;
+	}
+	default: {
+		np_hash_type = ZXDH_NP_HASH_TYPE_DEFAULT;
+		break;
+	}
+	}
+
+	return np_hash_type;
 }
 
 static int32_t zxdh_lag_lacp(struct zxdh_lag *ldev)
 {
-    int i;
-    bool porten = false;
-    uint8_t phy_port = 0;
-    uint8_t flags = 0;
-    uint32_t np_hash_type = 0;
-    int32_t err = 0;
-    struct lag_func *func;
-    struct lag_tracker *tracker = &ldev->tracker;
-    DPP_PF_INFO_T pf_info = {0};
-
-    err = lag_find_first_netdev_pf_info(ldev, &pf_info);
-    if (err != 0)
-    {
-        LAG_LOG_ERR("vport %d is incorrect\n", pf_info.vport);
-        return -EOPNOTSUPP;
-    }
-
-#if 0
-    np_hash_type = zxdh_covert_hash_type_2_np((uint32_t)tracker->hash_type);
-#else
-    /* 顾剑总要求，HASH模式直接写死Layer3+4 */
-    np_hash_type = ZXDH_NP_HASH_TYPE_L34;
-#endif
-
-    dpp_lag_group_hash_factor_set(&pf_info, ZXDH_LGA_ID, (uint8_t)np_hash_type);
-    dpp_lag_mode_set(&pf_info, ZXDH_LGA_ID, LAG_MODE_802_3AD);
-
-    for (i = 0; i < ZXDH_MAX_PORTS; i++)
-    {
-        func = &ldev->lagfunc[i];
-
-        if (!func->netdev)
-        {
-            continue;
-        }
-
-        phy_port = func->attrs.phy_port;
-        pf_info.slot = func->attrs.slot_id;
-        pf_info.vport = func->attrs.vport;
-
-        porten = tracker->netdev_state[i].tx_enabled && tracker->netdev_state[i].link_up;
-        if (porten && (ldev->slaves & (1 << i)))
-        {
-            dpp_lag_group_member_add(&pf_info, ZXDH_LGA_ID, phy_port);
-            dpp_panel_attr_set(&pf_info, phy_port, PANEL_FLAG_BOND_LINK_UP, LAG_FLAGS_ENABLE);
-            flags = LAG_FLAGS_ENABLE;
-        }
-        else
-        {
-            dpp_lag_group_member_del(&pf_info, ZXDH_LGA_ID, phy_port);
-            dpp_panel_attr_set(&pf_info, phy_port, PANEL_FLAG_BOND_LINK_UP, LAG_FLAGS_DISABLE);
-            flags = LAG_FLAGS_DISABLE;
-        }
-
-        LAG_LOG_INFO("[lacp] %s, vport %hu, pannel port %hu, phy port %hu, slave mask 0x%x, tx enable %d, link up %d \n",
-                (flags == LAG_FLAGS_ENABLE) ? "enable" : "disable", pf_info.vport,
-                func->attrs.pannel_id, phy_port, ldev->slaves,
-                (int32_t)tracker->netdev_state[i].tx_enabled,
-                (int32_t)tracker->netdev_state[i].link_up);
-    }
-
-    ldev->flags |= ZXDH_LAG_FLAG_HASH;
-
-    return 0;
+	int i;
+	bool porten = false;
+	uint8_t phy_port = 0;
+	uint8_t flags = 0;
+	uint32_t np_hash_type = 0;
+	int32_t err = 0;
+	struct lag_func *func;
+	struct lag_tracker *tracker = &ldev->tracker;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	err = lag_find_first_netdev_pf_info(ldev, &pf_info);
+	if (err != 0) {
+		LAG_LOG_ERR("vport %d is incorrect\n", pf_info.vport);
+		return -EOPNOTSUPP;
+	}
+
+	/* 顾剑总要求，HASH模式直接写死Layer3+4 */
+	np_hash_type = ZXDH_NP_HASH_TYPE_L34;
+
+	dpp_lag_group_hash_factor_set(&pf_info, ZXDH_LGA_ID, (uint8_t)np_hash_type);
+	dpp_lag_mode_set(&pf_info, ZXDH_LGA_ID, LAG_MODE_802_3AD);
+
+	for (i = 0; i < ZXDH_MAX_PORTS; i++) {
+		func = &ldev->lagfunc[i];
+
+		if (!func->netdev) {
+			continue;
+		}
+
+		phy_port = func->attrs.phy_port;
+		pf_info.slot = func->attrs.slot_id;
+		pf_info.vport = func->attrs.vport;
+
+		porten = tracker->netdev_state[i].tx_enabled &&
+				 tracker->netdev_state[i].link_up;
+		if (porten && (ldev->slaves & (1 << i))) {
+			dpp_lag_group_member_add(&pf_info, ZXDH_LGA_ID, phy_port);
+			dpp_panel_attr_set(&pf_info, phy_port, PANEL_FLAG_BOND_LINK_UP,
+							   LAG_FLAGS_ENABLE);
+			flags = LAG_FLAGS_ENABLE;
+		} else {
+			dpp_lag_group_member_del(&pf_info, ZXDH_LGA_ID, phy_port);
+			dpp_panel_attr_set(&pf_info, phy_port, PANEL_FLAG_BOND_LINK_UP,
+							   LAG_FLAGS_DISABLE);
+			flags = LAG_FLAGS_DISABLE;
+		}
+
+		LAG_LOG_INFO(
+				"[lacp] %s, vport %hu, pannel port %hu, phy port %hu, slave "
+				"mask 0x%x, tx enable %d, link up %d \n",
+				(flags == LAG_FLAGS_ENABLE) ? "enable" : "disable",
+				pf_info.vport, func->attrs.pannel_id, phy_port, ldev->slaves,
+				(int32_t)tracker->netdev_state[i].tx_enabled,
+				(int32_t)tracker->netdev_state[i].link_up);
+	}
+
+	ldev->flags |= ZXDH_LAG_FLAG_HASH;
+
+	return 0;
 }
 
 static void zxdh_lagtracker_info(struct lag_tracker *tracker)
 {
-    const char *bond_tx_mode, *bonded, *hash_type;
-
-    bonded = tracker->is_bonded ? "BONDED" : "UNBONDED";
-
-    switch (tracker->tx_type)
-    {
-        case NETDEV_LAG_TX_TYPE_HASH:
-        {
-            bond_tx_mode = "LACP";
-            break;
-        }
-        case NETDEV_LAG_TX_TYPE_ACTIVEBACKUP:
-        {
-            bond_tx_mode = "ACTIVE-BACKUP";
-            break;
-        }
-        default:
-        {
-            bond_tx_mode = "UNKOWN";
-        }
-    }
-
-    switch (tracker->hash_type)
-    {
-        case ZXDH_NP_HASH_TYPE_L2:
-        {
-            hash_type = "layer2";
-            break;
-        }
-        case ZXDH_NP_HASH_TYPE_L23:
-        {
-            hash_type = "layer2+3";
-            break;
-        }
-        case ZXDH_NP_HASH_TYPE_L34:
-        {
-            hash_type = "layer2+3";
-            break;
-        }
-        default:
-        {
-            hash_type = "layer2";
-        }
-    }
-
-    LAG_LOG_INFO("%s: tx type: %s, hash type %s.\n", bonded, bond_tx_mode, hash_type);
+	const char *bond_tx_mode, *bonded, *hash_type;
+
+	bonded = tracker->is_bonded ? "BONDED" : "UNBONDED";
+
+	switch (tracker->tx_type) {
+	case NETDEV_LAG_TX_TYPE_HASH: {
+		bond_tx_mode = "LACP";
+		break;
+	}
+	case NETDEV_LAG_TX_TYPE_ACTIVEBACKUP: {
+		bond_tx_mode = "ACTIVE-BACKUP";
+		break;
+	}
+	default: {
+		bond_tx_mode = "UNKOWN";
+	}
+	}
+
+	switch (tracker->hash_type) {
+	case ZXDH_NP_HASH_TYPE_L2: {
+		hash_type = "layer2";
+		break;
+	}
+	case ZXDH_NP_HASH_TYPE_L23: {
+		hash_type = "layer2+3";
+		break;
+	}
+	case ZXDH_NP_HASH_TYPE_L34: {
+		hash_type = "layer2+3";
+		break;
+	}
+	default: {
+		hash_type = "layer2";
+	}
+	}
+
+	LAG_LOG_INFO("%s: tx type: %s, hash type %s.\n", bonded, bond_tx_mode,
+				 hash_type);
 }
 
 static void do_bond(struct zxdh_lag *ldev)
 {
-    bool do_bond;
-    struct lag_tracker *tracker = &ldev->tracker;
+	bool do_bond;
+	struct lag_tracker *tracker = &ldev->tracker;
 
-    zxdh_lagtracker_info(tracker);
+	zxdh_lagtracker_info(tracker);
 
-    do_bond = tracker->is_bonded;
+	do_bond = tracker->is_bonded;
 
-    if (do_bond && lag_is_backup(ldev))
-    {
-        zxdh_lag_active_backup(ldev);
-    }
-    else if (do_bond && lag_is_hash(ldev))
-    {
-        zxdh_lag_lacp(ldev);
-    }
-    else
-    {
-        zxdh_disable_lag(ldev);
-    }
+	if (do_bond && lag_is_backup(ldev)) {
+		zxdh_lag_active_backup(ldev);
+	} else if (do_bond && lag_is_hash(ldev)) {
+		zxdh_lag_lacp(ldev);
+	} else {
+		zxdh_disable_lag(ldev);
+	}
 }
 
 static void zxdh_do_bond_work(struct work_struct *work)
 {
-    struct delayed_work *delayed_work = to_delayed_work(work);
-    struct zxdh_lag *ldev = container_of(delayed_work, struct zxdh_lag, bond_work);
-    int status;
+	struct delayed_work *delayed_work = to_delayed_work(work);
+	struct zxdh_lag *ldev =
+			container_of(delayed_work, struct zxdh_lag, bond_work);
+	int status;
 
-    status = zxdh_dev_list_trylock();
-    if (!status)
-    {
-        zxdh_queue_bond_work(ldev, HZ);
-        return;
-    }
+	status = zxdh_dev_list_trylock();
+	if (!status) {
+		zxdh_queue_bond_work(ldev, HZ);
+		return;
+	}
 
-    do_bond(ldev);
-    zxdh_dev_list_unlock();
+	do_bond(ldev);
+	zxdh_dev_list_unlock();
 }
 
 static struct zxdh_lag *lag_dev_alloc(struct dh_core_dev *dev)
 {
-    struct zxdh_lag *ldev;
+	struct zxdh_lag *ldev;
 
-    ldev = kzalloc(sizeof(*ldev), GFP_KERNEL);
-    if (!ldev)
-    {
-        return NULL;
-    }
+	ldev = kzalloc(sizeof(*ldev), GFP_KERNEL);
+	if (!ldev) {
+		return NULL;
+	}
 
-    ldev->wq = create_singlethread_workqueue("zxdh_lag");
-    if (!ldev->wq)
-    {
-        kfree(ldev);
-        return NULL;
-    }
+	ldev->wq = create_singlethread_workqueue("zxdh_lag");
+	if (!ldev->wq) {
+		kfree(ldev);
+		return NULL;
+	}
 
-    kref_init(&ldev->ref);
-    INIT_DELAYED_WORK(&ldev->bond_work, zxdh_do_bond_work);
+	kref_init(&ldev->ref);
+	INIT_DELAYED_WORK(&ldev->bond_work, zxdh_do_bond_work);
 
-    ldev->nb.notifier_call = lag_netdev_event;
-    if (register_netdevice_notifier_net(&init_net, &ldev->nb))
-    {
-        ldev->nb.notifier_call = NULL;
-        LAG_LOG_ERR("Failed to register LAG netdev notifier\n");
-    }
+	ldev->nb.notifier_call = lag_netdev_event;
+	if (register_netdevice_notifier_net(&init_net, &ldev->nb)) {
+		ldev->nb.notifier_call = NULL;
+		LAG_LOG_ERR("Failed to register LAG netdev notifier\n");
+	}
 
-    ldev->parent = dev;
+	ldev->parent = dev;
 
-    return ldev;
+	return ldev;
 }
 
 static int lag_dev_create(struct dh_core_dev *dh_dev)
 {
-    struct zxdh_lag *ldev = NULL;
-    static bool init_once = false;
+	struct zxdh_lag *ldev = NULL;
+	static bool init_once;
 
-    ldev = lag_get_ldev(dh_dev);
-    if (!ldev)
-    {
-        ldev = lag_dev_alloc(dh_dev);
-        if (!ldev)
-        {
-            LAG_LOG_ERR("Failed to alloc lag dev.\n");
-            return 0;
-        }
-    }
+	ldev = lag_get_ldev(dh_dev);
+	if (!ldev) {
+		ldev = lag_dev_alloc(dh_dev);
+		if (!ldev) {
+			LAG_LOG_ERR("Failed to alloc lag dev.\n");
+			return 0;
+		}
+	}
 
-    if (init_once)
-    {
-        get_ldev_kref(ldev);
-    }
-    init_once = true;
+	if (init_once) {
+		get_ldev_kref(ldev);
+	}
+	init_once = true;
 
-    lag_set_ldev(dh_dev, ldev);
+	lag_set_ldev(dh_dev, ldev);
 
-    return 0;
+	return 0;
 }
 
 int32_t lag_dpp_pannel_init(struct zxdh_lag_attrs *attr)
 {
-    uint16_t pannel_id = attr->pannel_id;
-    uint16_t pf_id = (attr->pcie_id >> 8) & PCIE_ID_PF_INDEX_MASK;
-    uint16_t ep_id = (attr->pcie_id >> 12) & PCIE_ID_EP_INDEX_MASK;
-    uint16_t bond_vfid = ZXDH_PF_VFID(ep_id, pf_id);
-    uint16_t ovs_vfid = ZXDH_PF_VFID(ep_id, (pf_id + 1));
-    uint8_t  phy_port = attr->phy_port;
-    DPP_PF_INFO_T pf_info = {0};
+	uint16_t pannel_id = attr->pannel_id;
+	uint16_t pf_id = (attr->pcie_id >> 8) & PCIE_ID_PF_INDEX_MASK;
+	uint16_t ep_id = (attr->pcie_id >> 12) & PCIE_ID_EP_INDEX_MASK;
+	uint16_t bond_vfid = ZXDH_PF_VFID(ep_id, pf_id);
+	uint16_t ovs_vfid = ZXDH_PF_VFID(ep_id, (pf_id + 1));
+	uint8_t phy_port = attr->phy_port;
+	DPP_PF_INFO_T pf_info = { 0 };
 
-    pf_info.slot = attr->slot_id;
-    pf_info.vport = attr->vport;
-    dpp_panel_bond_vport(&pf_info, phy_port);
-    dpp_panel_bond_pf_vqm_vfid_set(&pf_info, phy_port, bond_vfid);
-    dpp_panel_bond_pf_memport_qid_set(&pf_info, phy_port, attr->qid[0]);
-    dpp_panel_ovs_pf_vqm_vfid_set(&pf_info, phy_port, ovs_vfid);
+	pf_info.slot = attr->slot_id;
+	pf_info.vport = attr->vport;
+	dpp_panel_bond_vport(&pf_info, phy_port);
+	dpp_panel_bond_pf_vqm_vfid_set(&pf_info, phy_port, bond_vfid);
+	dpp_panel_bond_pf_memport_qid_set(&pf_info, phy_port, attr->qid[0]);
+	dpp_panel_ovs_pf_vqm_vfid_set(&pf_info, phy_port, ovs_vfid);
 
-    dpp_panel_hardware_bond_set(&pf_info, phy_port, LAG_FLAGS_ENABLE);
-    dpp_egr_port_attr_set(&pf_info, EGR_FLAG_HW_BOND_EN_OFF, LAG_FLAGS_ENABLE);
+	dpp_panel_hardware_bond_set(&pf_info, phy_port, LAG_FLAGS_ENABLE);
+	dpp_egr_port_attr_set(&pf_info, EGR_FLAG_HW_BOND_EN_OFF, LAG_FLAGS_ENABLE);
 
-    dpp_lag_group_create(&pf_info, ZXDH_LGA_ID);
+	dpp_lag_group_create(&pf_info, ZXDH_LGA_ID);
 
-    LAG_LOG_INFO("vport 0x%hx, pannel id %hu, phy port %hu, rx qid %hu tx qid %hu bond vfid %d, ovs vfid %d \n",
-                pf_info.vport, pannel_id, phy_port, attr->qid[0], attr->qid[1], bond_vfid, ovs_vfid);
+	LAG_LOG_INFO("vport 0x%hx, pannel id %hu, phy port %hu, rx qid %hu tx qid "
+				 "%hu bond vfid %d, ovs vfid %d \n",
+				 pf_info.vport, pannel_id, phy_port, attr->qid[0], attr->qid[1],
+				 bond_vfid, ovs_vfid);
 
-    return 0;
+	return 0;
 }
 
 int32_t lag_dpp_pannel_release(struct zxdh_lag_attrs *attr)
 {
-    uint8_t  phy_port = attr->phy_port;
-    DPP_PF_INFO_T pf_info = {0};
+	uint8_t phy_port = attr->phy_port;
+	DPP_PF_INFO_T pf_info = { 0 };
 
-    pf_info.slot = attr->slot_id;
-    pf_info.vport = attr->vport;
-    dpp_panel_hardware_bond_set(&pf_info, phy_port, LAG_FLAGS_DISABLE);
-    dpp_egr_port_attr_set(&pf_info, EGR_FLAG_HW_BOND_EN_OFF, LAG_FLAGS_DISABLE);
+	pf_info.slot = attr->slot_id;
+	pf_info.vport = attr->vport;
+	dpp_panel_hardware_bond_set(&pf_info, phy_port, LAG_FLAGS_DISABLE);
+	dpp_egr_port_attr_set(&pf_info, EGR_FLAG_HW_BOND_EN_OFF, LAG_FLAGS_DISABLE);
 
-    return 0;
+	return 0;
 }
 
-int32_t lag_netdev_input_check(struct dh_core_dev *dh_dev, struct zxdh_lag_attrs *attr)
+int32_t lag_netdev_input_check(struct dh_core_dev *dh_dev,
+							   struct zxdh_lag_attrs *attr)
 {
-    struct zxdh_lag *ldev;
+	struct zxdh_lag *ldev;
 
-    if (!dh_core_is_pf(dh_dev->parent))
-    {
-        LAG_LOG_ERR("dh_core_dev type PF needs to be used\n");
-        return -EINVAL;
-    }
+	if (!dh_core_is_pf(dh_dev->parent)) {
+		LAG_LOG_ERR("dh_core_dev type PF needs to be used\n");
+		return -EINVAL;
+	}
 
-    ldev = lag_get_ldev(dh_dev->parent);
-    if (!ldev)
-    {
-        LAG_LOG_ERR("ldev can not be null\n");
-        return -EINVAL;
-    }
+	ldev = lag_get_ldev(dh_dev->parent);
+	if (!ldev) {
+		LAG_LOG_ERR("ldev can not be null\n");
+		return -EINVAL;
+	}
 
-    if (attr->pannel_id >= ZXDH_MAX_PORTS)
-    {
-        LAG_LOG_ERR("pannel id %hu out of range.\n", attr->pannel_id);
-        return -EINVAL;
-    }
+	if (attr->pannel_id >= ZXDH_MAX_PORTS) {
+		LAG_LOG_ERR("pannel id %hu out of range.\n", attr->pannel_id);
+		return -EINVAL;
+	}
 
-    return 0;
+	return 0;
 }
 
 /**
@@ -804,27 +750,26 @@ int32_t lag_netdev_input_check(struct dh_core_dev *dh_dev, struct zxdh_lag_attrs
  **/
 void zxdh_regitster_ldev(struct dh_core_dev *dh_dev)
 {
-    zxdh_dev_list_lock();
-    lag_dev_create(dh_dev);
-    zxdh_dev_list_unlock();
+	zxdh_dev_list_lock();
+	lag_dev_create(dh_dev);
+	zxdh_dev_list_unlock();
 }
 
 void zxdh_unregitster_ldev(struct dh_core_dev *dh_dev)
 {
-    struct zxdh_lag *ldev;
+	struct zxdh_lag *ldev;
 
-    zxdh_dev_list_lock();
-    ldev = lag_get_ldev(dh_dev);
-    if (!ldev)
-    {
-        zxdh_dev_list_unlock();
-        return;
-    }
+	zxdh_dev_list_lock();
+	ldev = lag_get_ldev(dh_dev);
+	if (!ldev) {
+		zxdh_dev_list_unlock();
+		return;
+	}
 
-    lag_dev_release(dh_dev, ldev);
-    put_ldev_kref(ldev);
+	lag_dev_release(dh_dev, ldev);
+	put_ldev_kref(ldev);
 
-    zxdh_dev_list_unlock();
+	zxdh_dev_list_unlock();
 }
 
 /**
@@ -836,32 +781,34 @@ void zxdh_unregitster_ldev(struct dh_core_dev *dh_dev)
  * this function may called by en aux
  **/
 int32_t zxdh_ldev_add_netdev(struct dh_core_dev *dh_dev, uint16_t ida,
-        struct net_device *netdev, struct zxdh_lag_attrs *attr)
+							 struct net_device *netdev,
+							 struct zxdh_lag_attrs *attr)
 {
-    int32_t ret = 0;
+	int32_t ret = 0;
 
-    zxdh_dev_list_lock();
-    ret = lag_netdev_input_check(dh_dev, attr);
-    if (ret != 0)
-    {
-        zxdh_dev_list_unlock();
-        return -EINVAL;
-    }
+	zxdh_dev_list_lock();
+	ret = lag_netdev_input_check(dh_dev, attr);
+	if (ret != 0) {
+		zxdh_dev_list_unlock();
+		return -EINVAL;
+	}
 
-    lag_dpp_pannel_init(attr);
-    ldev_add_netdev(dh_dev, ida, netdev, attr);
-    zxdh_dev_list_unlock();
+	lag_dpp_pannel_init(attr);
+	ldev_add_netdev(dh_dev, ida, netdev, attr);
+	zxdh_dev_list_unlock();
 
-    return 0;
+	return 0;
 }
 EXPORT_SYMBOL(zxdh_ldev_add_netdev);
 
-void zxdh_ldev_remove_netdev(struct dh_core_dev *dh_dev, struct net_device *netdev, struct zxdh_lag_attrs *attr)
+void zxdh_ldev_remove_netdev(struct dh_core_dev *dh_dev,
+							 struct net_device *netdev,
+							 struct zxdh_lag_attrs *attr)
 {
-    zxdh_dev_list_lock();
+	zxdh_dev_list_lock();
 
-    lag_dpp_pannel_release(attr);
-    ldev_remove_netdev(dh_dev, netdev);
-    zxdh_dev_list_unlock();
+	lag_dpp_pannel_release(attr);
+	ldev_remove_netdev(dh_dev, netdev);
+	zxdh_dev_list_unlock();
 }
 EXPORT_SYMBOL(zxdh_ldev_remove_netdev);
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/lag/lag.h b/src/net/drivers/net/ethernet/dinghai/lag/lag.h
index df5db5bd8ca91c0f94440e807eb3b6bf9dfac91d..623450e6d8314f7faa1d58a3d5aba4ad40cb213d 100644
--- a/src/net/drivers/net/ethernet/dinghai/lag/lag.h
+++ b/src/net/drivers/net/ethernet/dinghai/lag/lag.h
@@ -7,114 +7,108 @@
 #include <linux/dinghai/lag.h>
 #include <linux/dinghai/log.h>
 
-#define LAG_LOG_ERR(fmt, arg...)    DH_LOG_ERR(MODULE_LAG, fmt, ##arg);
-#define LAG_LOG_INFO(fmt, arg...)   DH_LOG_INFO(MODULE_LAG, fmt, ##arg);
-#define LAG_LOG_DEBUG(fmt, arg...)  DH_LOG_DEBUG(MODULE_LAG, fmt, ##arg);
-#define LAG_LOG_WARN(fmt, arg...)   DH_LOG_WARNING(MODULE_LAG, fmt, ##arg);
+#define LAG_LOG_ERR(fmt, arg...) DH_LOG_ERR(MODULE_LAG, fmt, ##arg);
+#define LAG_LOG_INFO(fmt, arg...) DH_LOG_INFO(MODULE_LAG, fmt, ##arg);
+#define LAG_LOG_DEBUG(fmt, arg...) DH_LOG_DEBUG(MODULE_LAG, fmt, ##arg);
+#define LAG_LOG_WARN(fmt, arg...) DH_LOG_WARNING(MODULE_LAG, fmt, ##arg);
 
 /* max panel port */
-#define ZXDH_MAX_PORTS              (6)
+#define ZXDH_MAX_PORTS (6)
 
-#define ZXDH_LGA_ID                 (0)
-#define ZXDH_ACTIVE_PHY_PORT_NA     (0xFF)
+#define ZXDH_LGA_ID (0)
+#define ZXDH_ACTIVE_PHY_PORT_NA (0xFF)
 
-#define PCIE_ID_PF_INDEX_MASK       (0x7)
-#define PCIE_ID_EP_INDEX_MASK       (0x7)
+#define PCIE_ID_PF_INDEX_MASK (0x7)
+#define PCIE_ID_EP_INDEX_MASK (0x7)
 
-enum
-{
-    ZXDH_LAG_FLAG_BACKUP = 1 << 0,
-    ZXDH_LAG_FLAG_HASH   = 1 << 1,
-    ZXDH_LAG_FLAG_READY  = 1 << 2,
+enum {
+	ZXDH_LAG_FLAG_BACKUP = 1 << 0,
+	ZXDH_LAG_FLAG_HASH = 1 << 1,
+	ZXDH_LAG_FLAG_READY = 1 << 2,
 };
 
 #define ZXDH_LAG_MODE_FLAGS (ZXDH_LAG_FLAG_BACKUP | ZXDH_LAG_FLAG_HASH)
 
-enum
-{
-    LAG_FLAGS_DISABLE = 0,
-    LAG_FLAGS_ENABLE = 1,
+enum {
+	LAG_FLAGS_DISABLE = 0,
+	LAG_FLAGS_ENABLE = 1,
 };
 
-enum
-{
-    LAG_MODE_ACTIVE_BACKUP = 1,
-    LAG_MODE_802_3AD = 2,
+enum {
+	LAG_MODE_ACTIVE_BACKUP = 1,
+	LAG_MODE_802_3AD = 2,
 };
 
 /* define hash type for NP SDK */
-enum
-{
-    ZXDH_NP_HASH_TYPE_DEFAULT   = 0,
-    ZXDH_NP_HASH_TYPE_L2        = 1,
-    ZXDH_NP_HASH_TYPE_L23       = 2,
-    ZXDH_NP_HASH_TYPE_L34       = 4,
+enum {
+	ZXDH_NP_HASH_TYPE_DEFAULT = 0,
+	ZXDH_NP_HASH_TYPE_L2 = 1,
+	ZXDH_NP_HASH_TYPE_L23 = 2,
+	ZXDH_NP_HASH_TYPE_L34 = 4,
 };
 
-struct lag_func
-{
-    bool valid;
-    struct dh_core_dev   *dev;
-    struct net_device    *netdev;
-    struct zxdh_lag_attrs attrs;
+struct lag_func {
+	bool valid;
+	struct dh_core_dev *dev;
+	struct net_device *netdev;
+	struct zxdh_lag_attrs attrs;
 };
 
-struct lag_tracker
-{
-    enum   netdev_lag_tx_type           tx_type;
-    struct netdev_lag_lower_state_info  netdev_state[ZXDH_MAX_PORTS];
-    bool is_bonded;
-    enum netdev_lag_hash hash_type;
-    char master_name[IFNAMSIZ];
+struct lag_tracker {
+	enum netdev_lag_tx_type tx_type;
+	struct netdev_lag_lower_state_info netdev_state[ZXDH_MAX_PORTS];
+	bool is_bonded;
+	enum netdev_lag_hash hash_type;
+	char master_name[IFNAMSIZ];
 };
 
-struct zxdh_lag
-{
-    uint32_t flags;
-    uint32_t lag_func_index;
-    uint32_t slaves;
-    int32_t  mode_changes_in_progress;
-    struct kref ref;
-    struct lag_func           lagfunc[ZXDH_MAX_PORTS];
-    struct workqueue_struct   *wq;
-    struct delayed_work       bond_work;
-    struct notifier_block     nb;
-    struct lag_tracker        tracker;
-    struct dh_core_dev        *parent;
-
-    struct zxdh_lag_if        *ops;
+struct zxdh_lag {
+	uint32_t flags;
+	uint32_t lag_func_index;
+	uint32_t slaves;
+	int32_t mode_changes_in_progress;
+	struct kref ref;
+	struct lag_func lagfunc[ZXDH_MAX_PORTS];
+	struct workqueue_struct *wq;
+	struct delayed_work bond_work;
+	struct notifier_block nb;
+	struct lag_tracker tracker;
+	struct dh_core_dev *parent;
+
+	struct zxdh_lag_if *ops;
 };
 
 static inline bool lag_is_ready(struct zxdh_lag *ldev)
 {
-    return true;
+	return true;
 }
 
 static inline bool lag_is_backup(struct zxdh_lag *ldev)
 {
-    return ldev->tracker.tx_type == NETDEV_LAG_TX_TYPE_ACTIVEBACKUP ? true : false;
+	return ldev->tracker.tx_type == NETDEV_LAG_TX_TYPE_ACTIVEBACKUP ? true :
+																		false;
 }
 
 static inline bool lag_is_hash(struct zxdh_lag *ldev)
 {
-    return ldev->tracker.tx_type == NETDEV_LAG_TX_TYPE_HASH ? true : false;
+	return ldev->tracker.tx_type == NETDEV_LAG_TX_TYPE_HASH ? true : false;
 }
 
 static inline bool lag_is_port_invalid(struct zxdh_lag *ldev, uint32_t index)
 {
-    BUG_ON(index >= ZXDH_MAX_PORTS);
-    return !ldev->lagfunc[index].dev || !ldev->lagfunc[index].netdev;
+	BUG_ON(index >= ZXDH_MAX_PORTS);
+	return !ldev->lagfunc[index].dev || !ldev->lagfunc[index].netdev;
 }
 
 void ldev_kref_free(struct kref *ref);
 static inline void get_ldev_kref(struct zxdh_lag *ldev)
 {
-    kref_get(&ldev->ref);
+	kref_get(&ldev->ref);
 }
 
 static inline void put_ldev_kref(struct zxdh_lag *ldev)
 {
-    kref_put(&ldev->ref, ldev_kref_free);
+	kref_put(&ldev->ref, ldev_kref_free);
 }
 
 #endif /* _ZXDH_ETH_LAG_H_ */
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/lag/lag_procfs.c b/src/net/drivers/net/ethernet/dinghai/lag/lag_procfs.c
index 62ca8e52f736c7df825f88bc12c82e6476ff033a..d021b608ca399372078214ae61727364604926e9 100644
--- a/src/net/drivers/net/ethernet/dinghai/lag/lag_procfs.c
+++ b/src/net/drivers/net/ethernet/dinghai/lag/lag_procfs.c
@@ -1,62 +1,36 @@
 #include <linux/proc_fs.h>
 #include <linux/seq_file.h>
 #include <linux/printk.h>
-
 #include "dh_procfs.h"
 #include "lag.h"
 
 void *lag_info_seq_start(struct seq_file *seq, loff_t *pos)
 {
-    if (*pos == 0)
-    {
-        return SEQ_START_TOKEN;
-    }
+	if (*pos == 0) {
+		return SEQ_START_TOKEN;
+	}
 
-    return NULL;
+	return NULL;
 }
 
 void *lag_info_seq_next(struct seq_file *seq, void *v, loff_t *pos)
 {
-#if 0
-    struct test *tst = PDE_DATA(file_inode(seq->file));
-
-    ++*pos;
-    if (v == SEQ_START_TOKEN)
-        pr_info("%s first *pos = %u\n", __FUNCTION__, (uint32_t)*pos);
-
-    pr_info("%s *pos = %u\n", __FUNCTION__, (uint32_t)*pos);
-    if (*pos < 5)
-    {
-        return tst;
-    }
-#endif
-    return NULL;
+	return NULL;
 }
 
 void lag_info_seq_stop(struct seq_file *seq, void *v)
 {
-    pr_info("%s \n", __FUNCTION__);
+	pr_info("%s \n", __FUNCTION__);
 }
 
 int lag_info_seq_show(struct seq_file *seq, void *v)
 {
-#if 0
-    struct zxdh_lag *lag = PDE_DATA(file_inode(seq->file));
-
-    if (v == SEQ_START_TOKEN)
-    {
-        seq_printf(seq, "Port Mode: %u", tst->port);
-        seq_printf(seq, "Num  Mode: %u", tst->age);
-        seq_printf(seq, "\n");
-    }
-#endif
-    return 0;
+	return 0;
 }
 
-struct seq_operations lag_info_seq_ops =
-{
-    .start = lag_info_seq_start,
-    .next  = lag_info_seq_next,
-    .stop  = lag_info_seq_stop,
-    .show  = lag_info_seq_show,
+struct seq_operations lag_info_seq_ops = {
+	.start = lag_info_seq_start,
+	.next = lag_info_seq_next,
+	.stop = lag_info_seq_stop,
+	.show = lag_info_seq_show,
 };
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/msg_common.h b/src/net/drivers/net/ethernet/dinghai/msg_common.h
index 92110ea8b655eaa334cf3d11c1a5b2a5c21e7bef..907ff30e0bce9c563b7d1ae26a977d6a05354cd2 100644
--- a/src/net/drivers/net/ethernet/dinghai/msg_common.h
+++ b/src/net/drivers/net/ethernet/dinghai/msg_common.h
@@ -11,707 +11,597 @@ extern "C" {
 
 #define FW_VERSION_LEN 32
 
-typedef enum
-{
-    ZXDH_NULL = 0,
-
-    ZXDH_VF_PORT_INIT = 1,
-    ZXDH_VF_PORT_UNINIT = 2,
-    ZXDH_MAC_ADD = 3,
-    ZXDH_MAC_DEL = 4,
-    ZXDH_MAC_GET =  5,
-
-    ZXDH_RSS_EN_SET = 7,
-    ZXDH_RXFH_SET = 8,
-    ZXDH_RXFH_GET = 9,
-    ZXDH_RXFH_DEL = 10,
-    ZXDH_THASH_KEY_SET = 11,
-    ZXDH_THASH_KEY_GET = 12,
-    ZXDH_HASH_FUNC_SET = 13,
-    ZXDH_HASH_FUNC_GET = 14,
-    ZXDH_RX_FLOW_HASH_SET = 15,
-    ZXDH_RX_FLOW_HASH_GET = 16,
-
-    ZXDH_VLAN_FILTER_SET = 17,
-    ZXDH_VLAN_FILTER_ADD = 18,
-    ZXDH_VLAN_FILTER_DEL = 19,
-    ZXDH_VLAN_OFFLOAD_SET = 21,
-
-    ZXDH_PORT_ATTRS_GET = 22,
-    ZXDH_SET_TPID = 23,
-    ZXDH_VXLAN_PORT = 24,
-    ZXDH_PORT_ATTRS_SET = 25,
-    ZXDH_PROMISC_SET = 26,
-
-    /*sriov msg type*/
-    ZXDH_SRIOV_RESET = 27,
-
-    ZXDH_SET_VF_LINK_STATE = 28,
-    ZXDH_PF_SET_VF_VLAN = 29,
-    ZXDH_SET_VF_RESET = 30,
-    ZXDH_GET_NP_STATS = 31,
-
-    ZXDH_VF_RATE_LIMIT_SET = 32,
-    ZXDH_PLCR_UNINIT = 33,
-    ZXDH_MAP_PLCR_FLOWID = 34,
-    ZXDH_PLCR_MODE_INIT = 35,
-    ZXDH_PLCR_FLOW_INIT = 36,
-    ZXDH_PLCR_CAR_PROFILE_ID_ADD = 37,
-    ZXDH_PLCR_CAR_PROFILE_ID_DELETE = 38,
-    ZXDH_PLCR_CAR_PROFILE_CFG_SET = 39,
-    ZXDH_PLCR_CAR_PROFILE_CFG_GET = 40,
-    ZXDH_PLCR_CAR_QUEUE_CFG_SET = 41,
-    ZXDH_PORT_METER_STAT_CLR = 42,
-    ZXDH_PORT_METER_STAT_GET = 43,
-    ZXDH_PF_GET_VF_QUEUE_INFO = 44,
-
-    ZXDH_VF_1588_CALL_NP,
-    ZXDH_MSG_TYPE_CNT_MAX,
-
-    ZXDH_IPV6_MAC_ADD,
-    ZXDH_IPV6_MAC_DEL,
+typedef enum {
+	ZXDH_NULL = 0,
+
+	ZXDH_VF_PORT_INIT = 1,
+	ZXDH_VF_PORT_UNINIT = 2,
+	ZXDH_MAC_ADD = 3,
+	ZXDH_MAC_DEL = 4,
+	ZXDH_MAC_GET = 5,
+
+	ZXDH_RSS_EN_SET = 7,
+	ZXDH_RXFH_SET = 8,
+	ZXDH_RXFH_GET = 9,
+	ZXDH_RXFH_DEL = 10,
+	ZXDH_THASH_KEY_SET = 11,
+	ZXDH_THASH_KEY_GET = 12,
+	ZXDH_HASH_FUNC_SET = 13,
+	ZXDH_HASH_FUNC_GET = 14,
+	ZXDH_RX_FLOW_HASH_SET = 15,
+	ZXDH_RX_FLOW_HASH_GET = 16,
+
+	ZXDH_VLAN_FILTER_SET = 17,
+	ZXDH_VLAN_FILTER_ADD = 18,
+	ZXDH_VLAN_FILTER_DEL = 19,
+	ZXDH_VLAN_OFFLOAD_SET = 21,
+
+	ZXDH_PORT_ATTRS_GET = 22,
+	ZXDH_SET_TPID = 23,
+	ZXDH_VXLAN_PORT = 24,
+	ZXDH_PORT_ATTRS_SET = 25,
+	ZXDH_PROMISC_SET = 26,
+
+	/*sriov msg type*/
+	ZXDH_SRIOV_RESET = 27,
+
+	ZXDH_SET_VF_LINK_STATE = 28,
+	ZXDH_PF_SET_VF_VLAN = 29,
+	ZXDH_SET_VF_RESET = 30,
+	ZXDH_GET_NP_STATS = 31,
+
+	ZXDH_TX_MAXRATE_SET = 32,
+	ZXDH_PLCR_UNINIT = 33,
+	ZXDH_MAP_PLCR_FLOWID = 34,
+	ZXDH_PLCR_FLOW_INIT = 35,
+	ZXDH_PLCR_CAR_PROFILE_ID_ADD = 36,
+	ZXDH_PLCR_CAR_PROFILE_ID_DELETE = 37,
+	ZXDH_PLCR_CAR_PROFILE_CFG_SET = 38,
+	ZXDH_PLCR_CAR_PROFILE_CFG_GET = 39,
+	ZXDH_PLCR_CAR_QUEUE_CFG_SET = 40,
+	ZXDH_PORT_METER_STAT_CLR = 41,
+	ZXDH_PORT_METER_STAT_GET = 42,
+
+	ZXDH_VF_1588_CALL_NP,
+	ZXDH_MSG_TYPE_CNT_MAX,
+
+	ZXDH_IPV6_MAC_ADD,
+	ZXDH_IPV6_MAC_DEL,
 } __attribute__((packed)) zxdh_msg_op_code;
 
-typedef struct
-{
-    zxdh_msg_op_code op_code;
-    uint16_t vport;
-    uint16_t vf_id;
-    uint16_t pcie_id;
+typedef struct {
+	zxdh_msg_op_code op_code;
+	uint16_t vport;
+	uint16_t vf_id;
+	uint16_t pcie_id;
 } __attribute__((packed)) zxdh_msg_head_to_pf;
 
-typedef struct
-{
-    zxdh_msg_op_code op_code;
-    uint16_t dst_pcie_id;
+typedef struct {
+	zxdh_msg_op_code op_code;
+	uint16_t dst_pcie_id;
 } __attribute__((packed)) zxdh_msg_head_to_vf;
 
-typedef struct
-{
-    bool link_up;
-    bool is_upf;
-    uint16_t base_qid;
-    uint8_t mac_addr[ZXDH_MAC_NUM];
-    uint32_t speed;
-    uint32_t autoneg_enable;
-    uint32_t sup_link_modes;
-    uint32_t adv_link_modes;
-    uint8_t hash_search_idx;
-    uint8_t duplex;
-    uint8_t phy_port;
-    uint8_t rss_enable;
+typedef struct {
+	bool link_up;
+	uint16_t base_qid;
+	uint8_t mac_addr[ZXDH_MAC_NUM];
+	uint32_t speed;
+	uint32_t autoneg_enable;
+	uint32_t sup_link_modes;
+	uint32_t adv_link_modes;
+	uint8_t hash_search_idx;
+	uint8_t duplex;
+	uint8_t phy_port;
+	uint8_t rss_enable;
 } __attribute__((packed)) zxdh_vf_init_msg;
 
-typedef struct
-{
-    uint32_t vfid;
-    uint32_t call_np_interface_num;
-    uint32_t ptp_tc_enable_opt;
+typedef struct {
+	uint32_t vfid;
+	uint32_t call_np_interface_num;
+	uint32_t ptp_tc_enable_opt;
 } __attribute__((packed)) zxdh_vf_1588_call_np;
 
-typedef struct
-{
-    uint8_t rss_enable;
+typedef struct {
+	uint8_t rss_enable;
 } __attribute__((packed)) zxdh_rss_enable_msg;
 
-typedef struct
-{
-    bool enable;
-#define  VLAN_STRIP_MSG_TYPE  0
-#define  QINQ_STRIP_MSG_TYPE  1
-    uint8_t flag;
+typedef struct {
+	bool enable;
+#define VLAN_STRIP_MSG_TYPE 0
+#define QINQ_STRIP_MSG_TYPE 1
+	uint8_t flag;
 } __attribute__((packed)) zxdh_strip_enable_msg;
 
-typedef struct
-{
-    uint16_t vf_idx;
-    uint16_t vlan_id;
-    uint8_t qos;
-    uint8_t rsv;
-    uint16_t protocl;
+typedef struct {
+	uint16_t vf_idx;
+	uint16_t vlan_id;
+	uint8_t qos;
+	uint8_t rsv;
+	uint16_t protocl;
 } __attribute__((packed)) zxdh_set_vf_vlan_msg;
 
-typedef struct
-{
-    uint16_t tpid;
+typedef struct {
+	uint16_t tpid;
 } __attribute__((packed)) zxdh_qinq_tpid_cfg_msg;
 
-typedef struct
-{
-    uint32_t queue_map[ZXDH_INDIR_RQT_SIZE];
+typedef struct {
+	uint32_t queue_map[ZXDH_INDIR_RQT_SIZE];
 } __attribute__((packed)) zxdh_rxfh_set_msg;
 
-typedef struct
-{
-    uint8_t key_map[ZXDH_NET_HASH_KEY_SIZE];
+typedef struct {
+	uint8_t key_map[ZXDH_NET_HASH_KEY_SIZE];
 } __attribute__((packed)) zxdh_thash_key_set_msg;
 
-typedef struct
-{
-    uint8_t func;
+typedef struct {
+	uint8_t func;
 } __attribute__((packed)) zxdh_hfunc_set_msg;
 
-typedef struct
-{
-    uint32_t hash_mode;
+typedef struct {
+	uint32_t hash_mode;
 } __attribute__((packed)) zxdh_rx_flow_hash_set_msg;
 
-typedef struct
-{
-    bool     mac_flag;
-    uint8_t  filter_flag; /* 0xaa表示过滤，0Xff表示其他*/
-    uint8_t  mac_addr[ZXDH_MAC_NUM];
+typedef struct {
+	bool mac_flag;
+	uint8_t filter_flag; /* 0xaa表示过滤，0Xff表示其他*/
+	uint8_t mac_addr[ZXDH_MAC_NUM];
 } __attribute__((packed)) zxdh_mac_addr_msg;
 
-typedef struct
-{
-    uint8_t  mac_addr[ZXDH_MAC_NUM];
+typedef struct {
+	uint8_t mac_addr[ZXDH_MAC_NUM];
 } __attribute__((packed)) zxdh_ipv6_mac_addr_msg;
 
-typedef struct
-{
-    uint32_t mode;
-    uint32_t value;
-    uint8_t allmulti_follow;
+typedef struct {
+	uint32_t mode;
+	uint32_t value;
+	uint8_t allmulti_follow;
 } __attribute__((packed)) zxdh_port_attr_set_msg;
 
 #define ZXDH_PROMISC_MODE 1
 #define ZXDH_ALLMULTI_MODE 2
-typedef struct
-{
-    uint8_t mode;
-    uint8_t value;
-    uint8_t mc_follow;
+typedef struct {
+	uint8_t mode;
+	uint8_t value;
+	uint8_t mc_follow;
 } __attribute__((packed)) zxdh_promisc_set_msg;
 
-typedef struct
-{
-    uint8_t rsv2;
-    uint16_t read_bytes;
-    uint8_t value;
-}__attribute__((packed)) common_recv_msg;
-
-typedef struct
-{
-    uint8_t rsv2;
-    uint16_t read_bytes;
-    uint16_t queue_nums;
-    uint16_t phy_qidx[256];
-}__attribute__((packed)) common_vq_msg;
-
-typedef enum
-{
-    AGENT_MAC_STATS_GET = 10,
-    AGENT_MAC_STATS_CLEAR,
-    AGENT_MAC_PHYPORT_INIT,
-    AGENT_MAC_AUTONEG_SET,
-    AGENT_MAC_LINK_INFO_GET,
-    AGENT_MAC_LED_BLINK,
-    AGENT_MAC_FEC_MODE_SET,
-    AGENT_MAC_FEC_MODE_GET,
-    AGENT_MAC_FC_MODE_SET,
-    AGENT_MAC_FC_MODE_GET,
-    AGENT_MAC_MODULE_EEPROM_READ,
-    AGENT_VQM_DEVICE_STATS_GET,
-    AGENT_VQM_STATS_CLEAR,
-    AGENT_FLASH_FIR_VERSION_GET = 23,
-    AGENT_DEV_STATUS_NOTIFY,
-    AGENT_DEBUG_LLDP_ENABLE_SET,
-    AGENT_DEBUG_LLDP_ENABLE_GET,
-    AGENT_SSHD_START,
-    AGENT_SSHD_STOP,
-    AGENT_FLASH_MAC_READ,
-    AGENT_FLASH_MAC_WRITE,
-    AGENT_FLASH_MAC_ERASE,
-    AGENT_MAC_RECOVERY_CLK_SET,
-    AGENT_MAC_SYNCE_CLK_STATS_GET,
-    AGENT_MAC_PORT_TSTAMP_ENABLE_SET,
-    AGENT_MAC_PORT_TSTAMP_ENABLE_GET,
-    AGENT_MAC_PORT_TSTAMP_MODE_SET,
-    AGENT_MAC_PORT_TSTAMP_MODE_GET,
-    AGENT_MAC_PORT_DELAY_VALUE_GET,
-    AGENT_MAC_PORT_DELAY_VALUE_CLR,
-    AGENT_EP0_BUS_GET = 40,
-    AGENT_OS_TYPE_GET = 41,
-    AGENT_MAC_MSG_NUM_MAX, /* should be at last */
+typedef struct {
+	uint8_t rsv2;
+	uint16_t read_bytes;
+	uint8_t value;
+} __attribute__((packed)) common_recv_msg;
+
+typedef struct {
+	uint8_t rsv2;
+	uint16_t read_bytes;
+	uint16_t queue_nums;
+	uint16_t phy_qidx[256];
+} __attribute__((packed)) common_vq_msg;
+
+typedef enum {
+	AGENT_MAC_STATS_GET = 10,
+	AGENT_MAC_STATS_CLEAR,
+	AGENT_MAC_PHYPORT_INIT,
+	AGENT_MAC_AUTONEG_SET,
+	AGENT_MAC_LINK_INFO_GET,
+	AGENT_MAC_LED_BLINK,
+	AGENT_MAC_FEC_MODE_SET,
+	AGENT_MAC_FEC_MODE_GET,
+	AGENT_MAC_FC_MODE_SET,
+	AGENT_MAC_FC_MODE_GET,
+	AGENT_MAC_MODULE_EEPROM_READ,
+	AGENT_VQM_DEVICE_STATS_GET,
+	AGENT_VQM_STATS_CLEAR,
+	AGENT_FLASH_FIR_VERSION_GET = 23,
+	AGENT_DEV_STATUS_NOTIFY,
+	AGENT_DEBUG_LLDP_ENABLE_SET,
+	AGENT_DEBUG_LLDP_ENABLE_GET,
+	AGENT_SSHD_START,
+	AGENT_SSHD_STOP,
+	AGENT_FLASH_MAC_READ,
+	AGENT_FLASH_MAC_WRITE,
+	AGENT_FLASH_MAC_ERASE,
+	AGENT_MAC_RECOVERY_CLK_SET,
+	AGENT_MAC_SYNCE_CLK_STATS_GET,
+	AGENT_MAC_PORT_TSTAMP_ENABLE_SET,
+	AGENT_MAC_PORT_TSTAMP_ENABLE_GET,
+	AGENT_MAC_PORT_TSTAMP_MODE_SET,
+	AGENT_MAC_PORT_TSTAMP_MODE_GET,
+	AGENT_MAC_PORT_DELAY_VALUE_GET,
+	AGENT_MAC_PORT_DELAY_VALUE_CLR,
+	AGENT_EP0_BUS_GET = 40,
+	AGENT_MAC_MSG_NUM_MAX, /* should be at last */
 } __attribute__((packed)) agent_msg_op_code;
 
-typedef struct
-{
-    agent_msg_op_code op_code;
-    uint8_t port_id;
-    uint8_t phyport;
-    uint8_t is_upf;
-    uint16_t vf_id;
-    uint16_t pcie_id;
+typedef struct {
+	agent_msg_op_code op_code;
+	uint8_t port_id;
+	uint8_t phyport;
+	uint8_t rsv;
+	uint16_t vf_id;
+	uint16_t pcie_id;
 } __attribute__((packed)) agent_msg_hdr;
 
-typedef struct
-{
-    uint8_t autoneg;
-    uint8_t link_state;
-    uint8_t blink_enable;
-    uint8_t duplex;
-    uint32_t speed_modes;
-    uint32_t speed;
+typedef struct {
+	uint8_t autoneg;
+	uint8_t link_state;
+	uint8_t blink_enable;
+	uint8_t duplex;
+	uint32_t speed_modes;
+	uint32_t speed;
 } __attribute__((packed)) agent_mac_autoneg_msg;
 
-typedef struct
-{
-    uint64_t rx_total;
-    uint64_t tx_total;
-    uint64_t rx_bytes;
-    uint64_t tx_bytes;
-    uint64_t rx_error;
-    uint64_t tx_error;
-    uint64_t rx_drop;
-    uint64_t tx_drop;
-    uint64_t rx_multicast;
-    uint64_t tx_multicast;
-    uint64_t rx_broadcast;
-    uint64_t tx_broadcast;
-    uint64_t rx_size_64;
-    uint64_t rx_size_65_127;
-    uint64_t rx_size_128_255;
-    uint64_t rx_size_256_511;
-    uint64_t rx_size_512_1023;
-    uint64_t rx_size_1024_1518;
-    uint64_t rx_size_1519_mru;
+typedef struct {
+	uint64_t rx_total;
+	uint64_t tx_total;
+	uint64_t rx_bytes;
+	uint64_t tx_bytes;
+	uint64_t rx_error;
+	uint64_t tx_error;
+	uint64_t rx_drop;
+	uint64_t tx_drop;
+	uint64_t rx_multicast;
+	uint64_t tx_multicast;
+	uint64_t rx_broadcast;
+	uint64_t tx_broadcast;
+	uint64_t rx_size_64;
+	uint64_t rx_size_65_127;
+	uint64_t rx_size_128_255;
+	uint64_t rx_size_256_511;
+	uint64_t rx_size_512_1023;
+	uint64_t rx_size_1024_1518;
+	uint64_t rx_size_1519_mru;
 } __attribute__((packed)) agent_stats;
 
-typedef struct
-{
-    uint64_t np_rx_broadcast;
-    uint64_t np_tx_broadcast;
-    uint64_t np_rx_mtu_drop_pkts;
-    uint64_t np_tx_mtu_drop_pkts;
-    uint64_t np_rx_mtu_drop_bytes;
-    uint64_t np_tx_mtu_drop_bytes;
-    uint64_t np_rx_plcr_drop_pkts;
-    uint64_t np_tx_plcr_drop_pkts;
-    uint64_t np_rx_plcr_drop_bytes;
-    uint64_t np_tx_plcr_drop_bytes;
-}__attribute__((packed)) np_stats;
-
-typedef struct
-{
-    uint8_t fec_cfg;
-    uint8_t fec_cap;
-    uint8_t fec_link;
+typedef struct {
+	uint64_t np_rx_broadcast;
+	uint64_t np_tx_broadcast;
+	uint64_t np_rx_mtu_drop_pkts;
+	uint64_t np_tx_mtu_drop_pkts;
+	uint64_t np_rx_mtu_drop_bytes;
+	uint64_t np_tx_mtu_drop_bytes;
+	uint64_t np_rx_plcr_drop_pkts;
+	uint64_t np_tx_plcr_drop_pkts;
+	uint64_t np_rx_plcr_drop_bytes;
+	uint64_t np_tx_plcr_drop_bytes;
+} __attribute__((packed)) np_stats;
+
+typedef struct {
+	uint8_t fec_cfg;
+	uint8_t fec_cap;
+	uint8_t fec_link;
 } __attribute__((packed)) agent_mac_fec_mode_msg;
 
-typedef struct
-{
-    uint8_t fc_mode;
+typedef struct {
+	uint8_t fc_mode;
 } __attribute__((packed)) agent_mac_fc_mode_msg;
 
-typedef struct
-{
-    uint8_t index;
+typedef struct {
+	uint8_t index;
 } __attribute__((packed)) agent_flash_read_msg;
 
-typedef struct
-{
-    uint8_t i2c_addr;
-    uint8_t bank;
-    uint8_t page;
-    uint8_t offset;
-    uint8_t length;
-    uint8_t data[128];
+typedef struct {
+	uint8_t i2c_addr;
+	uint8_t bank;
+	uint8_t page;
+	uint8_t offset;
+	uint8_t length;
+	uint8_t data[128];
 } __attribute__((packed)) agent_mac_module_eeprom_msg;
 
-typedef struct
-{
-    bool is_link_force_set;
-    bool link_forced;
-    bool link_up;
-    uint32_t speed;
-    uint32_t autoneg_enable;
-    uint32_t supported_speed_modes;
-    uint32_t advertising_speed_modes;
-    uint8_t  duplex;
+typedef struct {
+	bool is_link_force_set;
+	bool link_forced;
+	bool link_up;
+	uint32_t speed;
+	uint32_t autoneg_enable;
+	uint32_t supported_speed_modes;
+	uint32_t advertising_speed_modes;
+	uint8_t duplex;
 } __attribute__((packed)) zxdh_link_state_msg;
 
-typedef struct
-{
-    bool enable;
+typedef struct {
+	bool enable;
 } __attribute__((packed)) zxdh_vlan_filter_set_msg;
 
-typedef struct
-{
-    uint16_t vlan_id;
+typedef struct {
+	uint16_t vlan_id;
 } __attribute__((packed)) zxdh_rx_vid_add_msg;
 
-typedef struct
-{
-    uint16_t vlan_id;
+typedef struct {
+	uint16_t vlan_id;
 } __attribute__((packed)) zxdh_rx_vid_del_msg;
 
-typedef struct
-{
-    uint8_t type;
-    uint8_t field;
-    uint16_t pcie_id;
-    uint16_t write_bytes;
-    uint16_t rsv;
+typedef struct {
+	uint8_t type;
+	uint8_t field;
+	uint16_t pcie_id;
+	uint16_t write_bytes;
+	uint16_t rsv;
 } __attribute__((packed)) zxdh_common_tbl_hdr;
 
-typedef struct
-{
-    uint8_t tmmng_type;
-    uint8_t dir;
-    uint16_t year;
-    uint8_t month;
-    uint8_t day;
-    uint8_t hour;
-    uint8_t min;
-    uint8_t sec;
+typedef struct {
+	uint8_t tmmng_type;
+	uint8_t dir;
+	uint16_t year;
+	uint8_t month;
+	uint8_t day;
+	uint8_t hour;
+	uint8_t min;
+	uint8_t sec;
 } __attribute__((packed)) zxdh_cfg_time_msg;
 
-typedef struct
-{
-    uint16_t pcie_id;
-    uint16_t write_bytes;
+typedef struct {
+	uint16_t pcie_id;
+	uint16_t write_bytes;
 } __attribute__((packed)) zxdh_common_time_hdr;
 
-typedef struct
-{
-    uint8_t clk_speed;
-    uint8_t clk_stats;
+typedef struct {
+	uint8_t clk_speed;
+	uint8_t clk_stats;
 } __attribute__((packed)) zxdh_synce_clk_msg;
 
-typedef struct
-{
-    uint32_t tx_enable;
-    uint32_t rx_enable;
-    uint32_t tx_mode;
-    uint32_t rx_mode;
+typedef struct {
+	uint32_t tx_enable;
+	uint32_t rx_enable;
+	uint32_t tx_mode;
+	uint32_t rx_mode;
 } __attribute__((packed)) zxdh_mac_tstamp_msg;
 
-typedef struct
-{
-    uint64_t min_delay;
-    uint64_t max_delay;
+typedef struct {
+	uint64_t min_delay;
+	uint64_t max_delay;
 } __attribute__((packed)) zxdh_delay_statistics_val;
 
-typedef struct
-{
-    uint16_t pcieid;            // 发送者自己的pcie id
-    uint16_t extern_pps_vector; // 外部pps中断向量
-    uint16_t local_pps_vector;  // local pps中断向量
+typedef struct {
+	uint16_t pcieid; // 发送者自己的pcie id
+	uint16_t extern_pps_vector; // 外部pps中断向量
+	uint16_t local_pps_vector; // local pps中断向量
 } __attribute__((packed)) zxdh_bar_msg_pps;
 
-typedef struct
-{
-    uint8_t dev_id;       //用dbg module的id, 为0
-    uint8_t type;         //区分PXE下和正常的np配表流程, 0: PXE 7: 配np
-    uint8_t operate_mode; //区分PXE开始和结束, 0: 开始 1: 结束
-    uint8_t pfNum;
-    uint32_t portNum[10];
-    uint32_t evid[10];
-    uint32_t qid[10];
+typedef struct {
+	uint8_t dev_id; //用dbg module的id, 为0
+	uint8_t type; //区分PXE下和正常的np配表流程, 0: PXE 7: 配np
+	uint8_t operate_mode; //区分PXE开始和结束, 0: 开始 1: 结束
+	uint8_t pfNum;
+	uint32_t portNum[10];
+	uint32_t evid[10];
+	uint32_t qid[10];
 } __attribute__((packed)) zxdh_cfg_np_msg;
 
 #define MAX_HDR_LEN 8
 
-typedef struct
-{
-    char ifname[IFNAMSIZ];
-    uint8_t mac[ETH_ALEN];
-    uint16_t pannel_id;
-    uint16_t ctl;
-    uint16_t rsv;
+typedef struct {
+	char ifname[IFNAMSIZ];
+	uint8_t mac[ETH_ALEN];
+	uint16_t pannel_id;
+	uint16_t ctl;
+	uint16_t rsv;
 } __attribute__((packed)) zxdh_pf_cfg_mac_msg;
 
 #define MAX_VF_NUM 256
-typedef struct
-{
-    uint16_t num;
-    uint16_t func_no[MAX_VF_NUM];
+typedef struct {
+	uint16_t num;
+	uint16_t func_no[MAX_VF_NUM];
 } __attribute__((packed)) agent_pcie_msix_msg;
 
-typedef struct
-{
-    bool lldp_enable;
+typedef struct {
+	bool lldp_enable;
 } __attribute__((packed)) zxdh_lldp_enable_msg;
 
-typedef struct
-{
-    uint32_t  flowid;
-    uint32_t  car_type;
-    uint32_t  is_packet;
-    uint32_t  max_rate;
-    uint32_t  min_rate;
-} __attribute__((packed)) zxdh_rate_limit_set_msg;
+typedef struct {
+	uint32_t flowid;
+	uint32_t max_rate;
+} __attribute__((packed)) zxdh_tx_maxrate_set_msg;
 
 /*vf send message to pf to map flow id between CARS*/
-typedef struct
-{
-    uint32_t car_type;
-    uint32_t flowid;
-    uint32_t map_flowid;
-    uint32_t sp;
+typedef struct {
+	uint32_t car_type;
+	uint32_t flowid;
+	uint32_t map_flowid;
+	uint32_t sp;
 } __attribute__((packed)) zxdh_plcr_flowid_map_msg;
 
-typedef struct
-{
-    uint32_t car_type;
-    uint32_t flowid;
-    uint32_t profile_id;
+typedef struct {
+	uint32_t car_type;
+	uint32_t flowid;
+	uint32_t profile_id;
 } __attribute__((packed)) zxdh_plcr_flow_init_msg;
 
-typedef struct
-{
-    uint32_t vir_queue_start;
-    uint32_t vir_queue_num;
-} __attribute__((packed)) zxdh_plcr_pf_get_vf_queue_info_msg;
-
 /*用户态QOS申请限速模板*/
-typedef struct
-{
-    uint8_t car_type;
+typedef struct {
+	uint8_t car_type;
 } __attribute__((packed)) zxdh_vf_plcr_profile_id_add_msg;
 
 /*用户态QOS删除限速模板*/
-typedef struct
-{
-    uint8_t  car_type;
-    uint8_t  rsvd;
-    uint16_t profile_id;
+typedef struct {
+	uint8_t car_type;
+	uint8_t rsvd;
+	uint16_t profile_id;
 } __attribute__((packed)) zxdh_vf_plcr_profile_id_delete_msg;
 
 /*用户态QOS配置限速模板*/
-typedef struct
-{
-    uint8_t  car_type;
-    uint8_t  pkt_mode;
-    uint16_t profile_id;
-    union    zxdh_plcr_profile_cfg profile_cfg;
+typedef struct {
+	uint8_t car_type;
+	uint8_t pkt_mode;
+	uint16_t profile_id;
+	union zxdh_plcr_profile_cfg profile_cfg;
 } __attribute__((packed)) zxdh_vf_plcr_profile_cfg_set_msg;
 
 /*用户态QOS获取限速模板*/
-typedef struct
-{
-    uint8_t  car_type;
-    uint8_t  pkt_mode;
-    uint16_t profile_id;
+typedef struct {
+	uint8_t car_type;
+	uint8_t pkt_mode;
+	uint16_t profile_id;
 } __attribute__((packed)) zxdh_vf_plcr_profile_cfg_get_msg;
 
 /*用户态QOS绑定flow和profile*/
-typedef struct
-{
-    uint8_t  car_type;
-    uint8_t  drop_flag;
-    uint8_t  plcr_en;
-    uint8_t  rsvd;
-    uint16_t flow_id;
-    uint16_t profile_id;
+typedef struct {
+	uint8_t car_type;
+	uint8_t drop_flag;
+	uint8_t plcr_en;
+	uint8_t rsvd;
+	uint16_t flow_id;
+	uint16_t profile_id;
 } __attribute__((packed)) zxdh_vf_plcr_queue_cfg_set_msg;
 
 /*用户态QOS获取plcr丢包统计*/
-typedef struct
-{
-    uint8_t direction; //取值为1：获取tx方向的统计计数；取值为0：获取rx方向的统计计数
-    uint8_t is_clr;    //取值为1：读取之后，计数器清零，取值为0：读取之后，计数器不清零
+typedef struct {
+	uint8_t direction; //取值为1：获取tx方向的统计计数；取值为0：获取rx方向的统计计数
+	uint8_t is_clr; //取值为1：读取之后，计数器清零，取值为0：读取之后，计数器不清零
 } __attribute__((packed)) zxdh_vf_plcr_port_meter_stat_get_msg;
 
-typedef struct
-{
-    uint32_t clear_mode;
+typedef struct {
+	uint32_t clear_mode;
 } __attribute__((packed)) zxdh_np_stats_get_msg;
 
-struct zxdh_port_msg
-{
-    uint16_t pcie_id;
-    uint8_t  rsv[2];
+struct zxdh_port_msg {
+	uint16_t pcie_id;
+	uint8_t rsv[2];
 } __attribute__((packed));
 
-struct port_message_recv
-{
-    uint8_t hdr[4];
-    uint8_t port_num;
-    uint8_t rsv[3];
-    struct zxdh_pannle_port data[16];
+struct port_message_recv {
+	uint8_t hdr[4];
+	uint8_t port_num;
+	uint8_t rsv[3];
+	struct zxdh_pannle_port data[16];
 } __attribute__((packed));
 
-typedef struct
-{
-    union
-    {
-        uint8_t len[MAX_HDR_LEN];
-        zxdh_msg_head_to_pf hdr;
-        zxdh_msg_head_to_vf hdr_vf;
-        agent_msg_hdr hdr_to_agt;
-        zxdh_common_tbl_hdr hdr_to_cmn;
-        zxdh_common_time_hdr hdr_time_to_cmn;
-    }; /* should be no more than MAX_HDR_LEN */
-
-    union
-    {
-        zxdh_rss_enable_msg rss_enable_msg;
-        zxdh_rxfh_set_msg rxfh_set_msg;
-        zxdh_thash_key_set_msg thash_key_set_msg;
-        zxdh_hfunc_set_msg hfunc_set_msg;
-        zxdh_rx_flow_hash_set_msg rx_flow_hash_set_msg;
-        zxdh_mac_addr_msg mac_addr_set_msg;
-        zxdh_port_attr_set_msg port_attr_set_msg;
-        zxdh_promisc_set_msg promisc_set_msg;
-        zxdh_link_state_msg link_state_msg;
-        zxdh_vlan_filter_set_msg vlan_filter_set_msg;
-        zxdh_rx_vid_add_msg rx_vid_add_msg;
-        zxdh_rx_vid_del_msg rx_vid_del_msg;
-        agent_mac_autoneg_msg mac_set_msg;
-        agent_mac_fec_mode_msg mac_fec_mode_msg;
-        agent_mac_fc_mode_msg mac_fc_mode_msg;
-        agent_mac_module_eeprom_msg module_eeprom_msg;
-        agent_flash_read_msg flash_read_msg;
-        zxdh_vf_init_msg vf_init_msg;
-        zxdh_strip_enable_msg vlan_strip_msg;
-        zxdh_set_vf_vlan_msg vf_vlan_msg;
-        zxdh_qinq_tpid_cfg_msg tpid_cfg_msg;
-        zxdh_pf_cfg_mac_msg mac_cfg_msg;
-        zxdh_cfg_time_msg time_cfg_msg;
-        agent_pcie_msix_msg pcie_msix_msg;
-        zxdh_lldp_enable_msg lldp_msg;
-        zxdh_rate_limit_set_msg rate_limit_set_msg;
-        zxdh_plcr_flowid_map_msg plcr_flowid_map_msg;
-        zxdh_plcr_flow_init_msg plcr_flow_init_msg;
-        zxdh_plcr_pf_get_vf_queue_info_msg plcr_pf_get_vf_queue_info_msg;
-        /*用户态QOS申请限速模板*/
-        zxdh_vf_plcr_profile_id_add_msg vf_plcr_profile_id_add_msg;
-        /*用户态QOS删除限速模板*/
-        zxdh_vf_plcr_profile_id_delete_msg vf_plcr_profile_id_delete_msg;
-        /*用户态QOS配置限速模板*/
-        zxdh_vf_plcr_profile_cfg_set_msg vf_plcr_profile_cfg_set_msg;
-        /*用户态QOS获取限速模板*/
-        zxdh_vf_plcr_profile_cfg_get_msg vf_plcr_profile_cfg_get_msg;
-        /*用户态QOS绑定flow和profile*/
-        zxdh_vf_plcr_queue_cfg_set_msg  vf_plcr_queue_cfg_set_msg;
-        /*用户态QOS获取plcr丢包统计*/
-        zxdh_vf_plcr_port_meter_stat_get_msg vf_plcr_port_meter_stat_get_msg;
-        zxdh_np_stats_get_msg np_stats_get_msg;
-
-        zxdh_vf_1588_call_np vf_1588_call_np;
-        zxdh_synce_clk_msg synce_clk_recovery_port;
-        zxdh_mac_tstamp_msg mac_tstamp_msg;
-        zxdh_bar_msg_pps msg_pps;
-        uint16_t cmn_tbl_msg[257];
-    };
+typedef struct {
+	union {
+		uint8_t len[MAX_HDR_LEN];
+		zxdh_msg_head_to_pf hdr;
+		zxdh_msg_head_to_vf hdr_vf;
+		agent_msg_hdr hdr_to_agt;
+		zxdh_common_tbl_hdr hdr_to_cmn;
+		zxdh_common_time_hdr hdr_time_to_cmn;
+	}; /* should be no more than MAX_HDR_LEN */
+
+	union {
+		zxdh_rss_enable_msg rss_enable_msg;
+		zxdh_rxfh_set_msg rxfh_set_msg;
+		zxdh_thash_key_set_msg thash_key_set_msg;
+		zxdh_hfunc_set_msg hfunc_set_msg;
+		zxdh_rx_flow_hash_set_msg rx_flow_hash_set_msg;
+		zxdh_mac_addr_msg mac_addr_set_msg;
+		zxdh_port_attr_set_msg port_attr_set_msg;
+		zxdh_promisc_set_msg promisc_set_msg;
+		zxdh_link_state_msg link_state_msg;
+		zxdh_vlan_filter_set_msg vlan_filter_set_msg;
+		zxdh_rx_vid_add_msg rx_vid_add_msg;
+		zxdh_rx_vid_del_msg rx_vid_del_msg;
+		agent_mac_autoneg_msg mac_set_msg;
+		agent_mac_fec_mode_msg mac_fec_mode_msg;
+		agent_mac_fc_mode_msg mac_fc_mode_msg;
+		agent_mac_module_eeprom_msg module_eeprom_msg;
+		agent_flash_read_msg flash_read_msg;
+		zxdh_vf_init_msg vf_init_msg;
+		zxdh_strip_enable_msg vlan_strip_msg;
+		zxdh_set_vf_vlan_msg vf_vlan_msg;
+		zxdh_qinq_tpid_cfg_msg tpid_cfg_msg;
+		zxdh_pf_cfg_mac_msg mac_cfg_msg;
+		zxdh_cfg_time_msg time_cfg_msg;
+		agent_pcie_msix_msg pcie_msix_msg;
+		zxdh_lldp_enable_msg lldp_msg;
+		zxdh_tx_maxrate_set_msg tx_maxrate_set_msg;
+		zxdh_plcr_flowid_map_msg plcr_flowid_map_msg;
+		zxdh_plcr_flow_init_msg plcr_flow_init_msg;
+		/*用户态QOS申请限速模板*/
+		zxdh_vf_plcr_profile_id_add_msg vf_plcr_profile_id_add_msg;
+		/*用户态QOS删除限速模板*/
+		zxdh_vf_plcr_profile_id_delete_msg vf_plcr_profile_id_delete_msg;
+		/*用户态QOS配置限速模板*/
+		zxdh_vf_plcr_profile_cfg_set_msg vf_plcr_profile_cfg_set_msg;
+		/*用户态QOS获取限速模板*/
+		zxdh_vf_plcr_profile_cfg_get_msg vf_plcr_profile_cfg_get_msg;
+		/*用户态QOS绑定flow和profile*/
+		zxdh_vf_plcr_queue_cfg_set_msg vf_plcr_queue_cfg_set_msg;
+		/*用户态QOS获取plcr丢包统计*/
+		zxdh_vf_plcr_port_meter_stat_get_msg vf_plcr_port_meter_stat_get_msg;
+		zxdh_np_stats_get_msg np_stats_get_msg;
+
+		zxdh_vf_1588_call_np vf_1588_call_np;
+		zxdh_synce_clk_msg synce_clk_recovery_port;
+		zxdh_mac_tstamp_msg mac_tstamp_msg;
+		zxdh_bar_msg_pps msg_pps;
+		uint16_t cmn_tbl_msg[257];
+		zxdh_ipv6_mac_addr_msg ipv6_mac_addr_msg;
+	};
 } zxdh_msg_info;
 
-typedef enum
-{
-    ZXDH_REPS_FAIL,
-    ZXDH_REPS_SUCC = 0xaa,
-    ZXDH_REPS_BEOND_MAC = 0xfe,
+typedef enum {
+	ZXDH_REPS_FAIL,
+	ZXDH_REPS_SUCC = 0xaa,
 } __attribute__((packed)) zxdh_reps_flag;
 
-typedef struct
-{
-    uint8_t lldp_status;
+typedef struct {
+	uint8_t lldp_status;
 } __attribute__((packed)) agent_debug_lldp_msg;
 
-typedef struct
-{
-    uint8_t firmware_version[FW_VERSION_LEN];
+typedef struct {
+	uint8_t firmware_version[FW_VERSION_LEN];
 } __attribute__((packed)) agent_flash_msg;
 
-typedef struct
-{
-    uint8_t mac[ETH_ALEN];
+typedef struct {
+	uint8_t mac[ETH_ALEN];
 } __attribute__((packed)) agent_flash_mac_read_msg;
 
-typedef struct
-{
-    uint32_t phy_queue_num;
-    uint16_t phy_rxq[16];
-    uint16_t phy_txq[16];
-} __attribute__((packed)) zxdh_plcr_pf_get_vf_queue_info_rsp;
-
-typedef struct
-{
-    uint32_t  err_code;
-} __attribute__((packed)) zxdh_rate_limit_set_rsp;
-
 /*用户态QOS申请限速模板，返回模板profile_id*/
-typedef struct
-{
-    uint16_t profile_id;
+typedef struct {
+	uint16_t profile_id;
 } __attribute__((packed)) zxdh_vf_plcr_profile_id_add_rsp;
 
 /*用户态QOS获取限速模板，返回模板参数*/
-typedef struct
-{
-    union zxdh_plcr_profile_cfg profile_cfg;
+typedef struct {
+	union zxdh_plcr_profile_cfg profile_cfg;
 } __attribute__((packed)) zxdh_vf_plcr_profile_cfg_get_rsp;
 
 /*用户态QOS获取丢包统计*/
-typedef struct
-{
-    uint64_t drop_pkB_cnt;  //丢数据包：包数统计
-    uint64_t drop_pk_cnt;   //丢数据包：字节数计数
+typedef struct {
+	uint64_t drop_pkB_cnt; //丢数据包：包数统计
+	uint64_t drop_pk_cnt; //丢数据包：字节数计数
 } __attribute__((packed)) zxdh_vf_plcr_port_meter_stat_get_rsp;
 
-typedef struct
-{
-    uint8_t bus_info;   //ep0的bus号
+typedef struct {
+	uint8_t bus_info; // ep0的bus号
 } __attribute__((packed)) zxdh_ep0_bus_get_rsp;
 
-typedef struct
-{
-    uint8_t is_zios;   //riscv是否为zios
-} __attribute__((packed)) zxdh_os_type_get_rsp;
-
-typedef struct
-{
-    ZXDH_VPORT_T port_attr_entry;
+typedef struct {
+	ZXDH_VPORT_T port_attr_entry;
 } __attribute__((packed)) zxdh_port_attr_get_msg;
 
-typedef struct
-{
-    zxdh_reps_flag flag;
-    union
-    {
-        zxdh_thash_key_set_msg thash_key_set_msg;
-        zxdh_rx_flow_hash_set_msg rx_flow_hash_set_msg;
-        zxdh_link_state_msg link_state_msg;
-        agent_mac_autoneg_msg mac_set_msg;
-        agent_stats stats_msg;
-        np_stats np_stats_msg;
-        agent_mac_fec_mode_msg mac_fec_mode_msg;
-        agent_mac_fc_mode_msg mac_fc_mode_msg;
-        agent_mac_module_eeprom_msg module_eeprom_msg;
-        common_recv_msg cmn_recv_msg;
-        common_vq_msg cmn_vq_msg;
-        zxdh_mac_addr_msg vf_mac_addr_get_msg;
-        zxdh_vf_init_msg vf_init_msg;
-        agent_flash_msg flash_msg;
-        agent_flash_mac_read_msg flash_mac_read_msg;
-        agent_debug_lldp_msg debug_lldp_msg;
-        zxdh_plcr_pf_get_vf_queue_info_rsp plcr_pf_get_vf_queue_info_rsp;
-        zxdh_rate_limit_set_rsp rate_limit_set_rsp;
-        /*用户态QOS申请限速模板返回profile_id*/
-        zxdh_vf_plcr_profile_id_add_rsp vf_plcr_profile_id_add_rsp;
-        /*用户态QOS获取限速模板*/
-        zxdh_vf_plcr_profile_cfg_get_rsp vf_plcr_profile_cfg_get_rsp;
-        /*用户态QOS获取丢包统计*/
-        zxdh_vf_plcr_port_meter_stat_get_rsp vf_plcr_port_meter_stat_get_rsp;
-        zxdh_synce_clk_msg synce_clk_recovery_port;
-        zxdh_mac_tstamp_msg mac_tstamp_msg;
-        zxdh_delay_statistics_val delay_statistics_val;
-        zxdh_ep0_bus_get_rsp ep0_bus_msg;
-        zxdh_os_type_get_rsp os_type_msg;
-        zxdh_port_attr_get_msg port_attr_get_msg;
-        zxdh_rxfh_set_msg rxfh_get_msg;
-    };
+typedef struct {
+	zxdh_reps_flag flag;
+	union {
+		zxdh_thash_key_set_msg thash_key_set_msg;
+		zxdh_rx_flow_hash_set_msg rx_flow_hash_set_msg;
+		zxdh_link_state_msg link_state_msg;
+		agent_mac_autoneg_msg mac_set_msg;
+		agent_stats stats_msg;
+		np_stats np_stats_msg;
+		agent_mac_fec_mode_msg mac_fec_mode_msg;
+		agent_mac_fc_mode_msg mac_fc_mode_msg;
+		agent_mac_module_eeprom_msg module_eeprom_msg;
+		common_recv_msg cmn_recv_msg;
+		common_vq_msg cmn_vq_msg;
+		zxdh_mac_addr_msg vf_mac_addr_get_msg;
+		zxdh_vf_init_msg vf_init_msg;
+		agent_flash_msg flash_msg;
+		agent_flash_mac_read_msg flash_mac_read_msg;
+		agent_debug_lldp_msg debug_lldp_msg;
+		/*用户态QOS申请限速模板返回profile_id*/
+		zxdh_vf_plcr_profile_id_add_rsp vf_plcr_profile_id_add_rsp;
+		/*用户态QOS获取限速模板*/
+		zxdh_vf_plcr_profile_cfg_get_rsp vf_plcr_profile_cfg_get_rsp;
+		/*用户态QOS获取丢包统计*/
+		zxdh_vf_plcr_port_meter_stat_get_rsp vf_plcr_port_meter_stat_get_rsp;
+		zxdh_synce_clk_msg synce_clk_recovery_port;
+		zxdh_mac_tstamp_msg mac_tstamp_msg;
+		zxdh_delay_statistics_val delay_statistics_val;
+		zxdh_ep0_bus_get_rsp ep0_bus_msg;
+		zxdh_port_attr_get_msg port_attr_get_msg;
+	};
 } zxdh_reps_info;
 
-union zxdh_msg
-{
-    zxdh_msg_info payload;
-    zxdh_reps_info reps;
-};
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/pci_irq.c b/src/net/drivers/net/ethernet/dinghai/pci_irq.c
old mode 100755
new mode 100644
index f1f9e7bc747c0d51c762a4fbf7d4e0aa6fc9f136..5ca09a907723d79244d3939122d4eb0394de29ef
--- a/src/net/drivers/net/ethernet/dinghai/pci_irq.c
+++ b/src/net/drivers/net/ethernet/dinghai/pci_irq.c
@@ -1,573 +1,536 @@
-#include <linux/interrupt.h>
-#include <linux/notifier.h>
-#include <linux/module.h>
-#include <linux/dinghai/pci_irq.h>
-#include <linux/dinghai/helper.h>
-#include <linux/types.h>
-#include <linux/gfp.h>
-#include <linux/cpumask.h>
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/slab.h>
-#include <linux/lockdep.h>
-#include <linux/device.h>
-#include <linux/dinghai/dinghai_irq.h>
-
-#define DH_PF_IRQ_CTRL_NUM (1)
-
-#define DH_SFS_PER_CTRL_IRQ 64
-#define DH_IRQ_CTRL_SF_MAX 8
-/* min num of vectors for SFs to be enabled */
-#define DH_IRQ_VEC_COMP_BASE_SF 2
-
-#define DH_EQ_SHARE_IRQ_MAX_COMP (8)
-#define DH_EQ_SHARE_IRQ_MAX_CTRL (UINT_MAX)
-#define DH_EQ_SHARE_IRQ_MIN_COMP (1)
-#define DH_EQ_SHARE_IRQ_MIN_CTRL (4)
-
-static void irq_release(struct dh_irq *irq)
-{
-    struct dh_irq_pool *pool = irq->pool;
-
-    xa_erase(&pool->irqs, irq->index);
-    /* free_irq requires that affinity_hint and rmap will be cleared
-     * before calling it. This is why there is asymmetry with set_rmap
-     * which should be called after alloc_irq but before request_irq.
-     */
-    // irq_update_affinity_hint(irq->irqn, NULL);
-    irq_set_affinity_hint(irq->irqn, NULL);
-    free_cpumask_var(irq->mask);
-    free_irq(irq->irqn, &irq->nh);
-    kfree(irq);
-}
-
-int32_t dh_irq_put(struct dh_irq *irq)
-{
-    struct dh_irq_pool *pool = irq->pool;
-    int32_t ret              = 0;
-
-    mutex_lock(&pool->lock);
-    irq->refcount--;
-    if (!irq->refcount)
-    {
-        irq_release(irq);
-        ret = 1;
-    }
-    mutex_unlock(&pool->lock);
-
-    return ret;
-}
-
-int32_t dh_irq_read_locked(struct dh_irq *irq)
-{
-    lockdep_assert_held(&irq->pool->lock);
-
-    return irq->refcount;
-}
-
-int32_t dh_irq_get_locked(struct dh_irq *irq)
-{
-    lockdep_assert_held(&irq->pool->lock);
-    if (WARN_ON_ONCE(!irq->refcount))
-    {
-        return 0;
-    }
-
-    irq->refcount++;
-
-    return 1;
-}
-
-static int32_t irq_get(struct dh_irq *irq)
-{
-    int32_t err = 0;
-
-    mutex_lock(&irq->pool->lock);
-    err = dh_irq_get_locked(irq);
-    mutex_unlock(&irq->pool->lock);
-
-    return err;
-}
-
-static irqreturn_t irq_int_handler(int32_t irq, void *nh)
-{
-    atomic_notifier_call_chain(nh, 0, NULL);
-
-    return IRQ_HANDLED;
-}
-
-static void irq_set_name(struct dh_irq_pool *pool, char *name, int32_t vecidx)
-{
-    if (!strcmp(pool->name, "zxdh_pf_vq"))
-    {
-        int type = (vecidx - pool->xa_num_irqs.min) % 2;
-        snprintf(name, DH_MAX_IRQ_NAME, "vq_%s_%d", type ? "output" : "input", vecidx);
-        return;
-    }
-    else if (!strcmp(pool->name, "zxdh_pf_async"))
-    {
-        snprintf(name, DH_MAX_IRQ_NAME, "async_%d", vecidx);
-        return;
-    }
-    else if (!strcmp(pool->name, "zxdh_mpf_gdma"))
-    {
-        snprintf(name, DH_MAX_IRQ_NAME, "gdma_%d", vecidx);
-        return;
-    }
-}
-
-struct dh_irq *dh_irq_alloc(struct dh_irq_pool *pool, int32_t i, const struct cpumask *affinity)
-{
-    struct dh_core_dev *dev = pool->dev;
-    char name[DH_MAX_IRQ_NAME] = {};
-    struct dh_irq *irq = NULL;
-    int32_t err = 0;
-    int32_t num_cpu = 0;
-    int32_t cpu_loop = 0;
-
-    irq = kzalloc(sizeof(*irq), GFP_KERNEL);
-    if (unlikely(irq == NULL))
-    {
-        LOG_ERR("irq kzalloc failed\n");
-        return ERR_PTR(-ENOMEM);
-    }
-
-    irq->irqn = pci_irq_vector(dev->pdev, i);
-    irq_set_name(pool, name, i);
-    ATOMIC_INIT_NOTIFIER_HEAD(&irq->nh);
-    snprintf(irq->name, DH_MAX_IRQ_NAME, "%s@pci:%s", name, pci_name(dev->pdev));
-    LOG_DEBUG("i=%d, irqn=%d, name=%s\r\n", i, irq->irqn, irq->name);
-
-    err = request_irq(irq->irqn, irq_int_handler, 0, irq->name, &irq->nh);
-    if (err != 0)
-    {
-        LOG_ERR("Failed to request irq. err = %d\n", err);
-        goto err_req_irq;
-    }
-
-    if (!zalloc_cpumask_var(&irq->mask, GFP_KERNEL))
-    {
-        LOG_WARN("zalloc_cpumask_var failed\n");
-        err = -ENOMEM;
-        goto err_cpumask;
-    }
-
-    if (affinity != NULL)
-    {
-        cpumask_copy(irq->mask, affinity);
-        irq_set_affinity_hint(irq->irqn, irq->mask);
-    }
-    else
-    {
-        num_cpu = num_online_cpus();
-        for (cpu_loop= 0; cpu_loop < num_cpu; cpu_loop++)
-        {
-            cpumask_set_cpu(cpu_loop, irq->mask);
-        }
-        irq_set_affinity_hint(irq->irqn, irq->mask);
-    }
-
-    irq->pool = pool;
-    irq->refcount = 1;
-    irq->index = i;
-    err = xa_err(xa_store(&pool->irqs, irq->index, irq, GFP_KERNEL));
-    if (err != 0)
-    {
-        LOG_ERR("Failed to alloc xa entry for irq(%u). err = %d\n", irq->index, err);
-        goto err_xa;
-    }
-
-    return irq;
-
-err_xa:
-    irq_set_affinity_hint(irq->irqn, NULL);
-    free_cpumask_var(irq->mask);
-err_cpumask:
-    free_irq(irq->irqn, &irq->nh);
-err_req_irq:
-    kfree(irq);
-    return ERR_PTR(err);
-}
-
-int32_t dh_irq_attach_nb(struct dh_irq *irq, struct notifier_block *nb)
-{
-    int32_t ret = 0;
-
-    ret = irq_get(irq);
-    if (ret == 0)
-    {
-        return -ENOENT;
-    }
-
-    ret = atomic_notifier_chain_register(&irq->nh, nb);
-    if (ret != 0)
-    {
-        dh_irq_put(irq);
-    }
-
-    return ret;
-}
-
-int32_t dh_irq_detach_nb(struct dh_irq *irq, struct notifier_block *nb)
-{
-    int32_t err = 0;
-
-    err = atomic_notifier_chain_unregister(&irq->nh, nb);
-    dh_irq_put(irq);
-
-    return err;
-}
-
-struct cpumask *dh_irq_get_affinity_mask(struct dh_irq *irq)
-{
-    return irq->mask;
-}
-
-int32_t dh_irq_get_index(struct dh_irq *irq)
-{
-    return irq->index;
-}
-
-/* irq_pool API */
-static int32_t __attribute__((unused)) irq_pool_size_get(struct dh_irq_pool *pool)
-{
-    return pool->xa_num_irqs.max - pool->xa_num_irqs.min + 1;
-}
-
-/* requesting an irq from a given pool according to given index */
-static struct dh_irq *irq_pool_request_vector(struct dh_irq_pool *pool, int32_t vecidx,
-                                              const struct cpumask *affinity, u8 exclude)
-{
-    struct dh_irq *irq = NULL;
-
-    mutex_lock(&pool->lock);
-    irq = xa_load(&pool->irqs, vecidx);
-    if (irq != NULL)
-    {
-        if (exclude)
-        {
-            return ERR_PTR(-EEXIST);
-        }
-        dh_irq_get_locked(irq);
-        goto unlock;
-    }
-
-    irq = dh_irq_alloc(pool, vecidx, affinity);
-unlock:
-    mutex_unlock(&pool->lock);
-    return irq;
-}
-
-/**
- * dh_irqs_release - release one or more IRQs back to the system.
- * @irqs: IRQs to be released.
- * @nirqs: number of IRQs to be released.
- */
-static void dh_irqs_release(struct dh_irq **irqs, int32_t nirqs)
-{
-    int32_t i;
-
-    for (i = 0; i < nirqs; i++)
-    {
-        synchronize_irq(irqs[i]->irqn);
-        dh_irq_put(irqs[i]);
-    }
-}
-
-/**
- * dh_ctrl_irq_release - release a ctrl IRQ back to the system.
- * @ctrl_irq: ctrl IRQ to be released.
- */
-void dh_ctrl_irq_release(struct dh_irq *ctrl_irq)
-{
-    dh_irqs_release(&ctrl_irq, 1);
-}
-
-/* get a irq from pool*/
-struct dh_irq *zxdh_get_irq_of_pool(struct dh_core_dev *dev, struct dh_irq_pool *pool)
-{
-    cpumask_var_t req_mask;
-    struct dh_irq *irq = NULL;
-
-    if (!zalloc_cpumask_var(&req_mask, GFP_KERNEL))
-    {
-        LOG_ERR("zalloc_cpumask_var failed\n");
-        return ERR_PTR(-ENOMEM);
-    }
-    cpumask_copy(req_mask, cpu_online_mask);
-
-    irq = dh_irq_affinity_request(pool, req_mask);
-
-    free_cpumask_var(req_mask);
-    if (IS_ERR_OR_NULL(irq))
-    {
-        LOG_ERR("irq=0x%llx dh_irq_affinity_request failed\n", (unsigned long long)irq);
-    }
-
-    return irq;
-}
-
-/**
- * dh_irq_request - request an IRQ for zxdh PF/VF device.
- * @pool: requesting the IRQ from the irqs pool.
- * @vecidx: vector index of the IRQ. This argument is ignore if affinity is
- * provided.
- * @affinity: cpumask requested for this IRQ.
- *
- * This function returns a pointer to IRQ, or ERR_PTR in case of error.
- */
-struct dh_irq *dh_irq_request(struct dh_irq_pool *pool, u16 vecidx,
-                              const struct cpumask *affinity, u8 exclude)
-{
-    struct dh_irq *irq = NULL;
-
-    irq = irq_pool_request_vector(pool, vecidx, affinity, exclude);
-    if (IS_ERR_OR_NULL(irq))
-        return irq;
-    LOG_DEBUG("irq %u mapped to cpu %*pbl, %u EQs on this irq\n",
-              irq->irqn, cpumask_pr_args(affinity),
-              irq->refcount / DH_EQ_REFS_PER_IRQ);
-
-    return irq;
-}
-
-/**
- * dh_irqs_release_vectors - release one or more IRQs back to the system.
- * @irqs: IRQs to be released.
- * @nirqs: number of IRQs to be released.
- */
-void dh_irqs_release_vectors(struct dh_irq **irqs, int32_t nirqs)
-{
-    dh_irqs_release(irqs, nirqs);
-}
-
-/**
- * dh_irqs_request_vectors - request one or more IRQs for zxdh device.
- * @pool: requesting the IRQs from the irqs pool.
- * @cpus: CPUs array for binding the IRQs
- * @nirqs: number of IRQs to request.
- * @irqs: an output array of IRQs pointers.
- *
- * Each IRQ is bound to at most 1 CPU.
- * This function is requests nirqs IRQs, starting from @vecidx.
- *
- * This function returns the number of IRQs requested, (which might be smaller than
- * @nirqs), if successful, or a negative error code in case of an error.
- */
-int32_t dh_irqs_request_vectors(struct dh_irq_pool *pool, uint16_t *cpus, int32_t nirqs,
-                                struct dh_irq **irqs)
-{
-    cpumask_var_t req_mask;
-    struct dh_irq *irq = NULL;
-    int32_t i;
-
-    if (!zalloc_cpumask_var(&req_mask, GFP_KERNEL))
-    {
-        return -ENOMEM;
-    }
-
-    for (i = 0; i < nirqs; i++)
-    {
-        cpumask_set_cpu(cpus[i], req_mask);
-        irq = dh_irq_request(pool, i, req_mask, 0);
-        if (IS_ERR_OR_NULL(irq))
-        {
-            break;
-        }
-        cpumask_clear(req_mask);
-        irqs[i] = irq;
-    }
-
-    free_cpumask_var(req_mask);
-
-    return i ? i : PTR_ERR(irq);
-}
-
-static int32_t req_mask_local_spread(int32_t i, int32_t node,
-                                     const struct cpumask *irqs_req_mask)
-{
-    int32_t cpu;
-
-    if (node == NUMA_NO_NODE)
-    {
-        for_each_cpu_and(cpu, cpu_online_mask, irqs_req_mask)
-        {
-            if (i-- == 0)
-            {
-                return cpu;
-            }
-        }
-    }
-    else
-    {
-        /* NUMA first. */
-        for_each_cpu_and(cpu, cpumask_of_node(node), irqs_req_mask)
-        {
-            if (cpu_online(cpu))
-            {
-                if (i-- == 0)
-                {
-                    return cpu;
-                }
-            }
-        }
-
-        for_each_online_cpu(cpu)
-        {
-            /* Skip NUMA nodes, done above. */
-            if (cpumask_test_cpu(cpu, cpumask_of_node(node)))
-            {
-                continue;
-            }
-
-            if (i-- == 0)
-            {
-                return cpu;
-            }
-        }
-    }
-    WARN_ON(true);
-
-    return cpumask_first(cpu_online_mask);
-}
-
-/**
- * dh_irqs_request_mask - request one or more IRQs for zxdh device.
- * @pool: requesting the IRQs from the irqs pool.
- * @irqs: an output array of IRQs pointers.
- * @irqs_req_mask: cpumask requested for these IRQs.
- *
- * Each IRQ is bounded to at most 1 CPU.
- * This function returns the number of IRQs requested, (which might be smaller than
- * cpumask_weight(@irqs_req_mask)), if successful, or a negative error code in
- * case of an error.
- */
-int32_t dh_irqs_request_mask(struct dh_irq_pool *pool, struct dh_irq **irqs,
-                             struct cpumask *irqs_req_mask)
-{
-    struct dh_irq *irq = NULL;
-    int32_t nirqs;
-    int32_t cpu;
-    int32_t i;
-
-    /* Request an IRQ for each online CPU in the given mask */
-    cpumask_and(irqs_req_mask, irqs_req_mask, cpu_online_mask);
-    nirqs = cpumask_weight(irqs_req_mask);
-    for (i = 0; i < nirqs; i++)
-    {
-        /* Iterate over the mask the caller provided in numa aware fashion.
-         * Local CPUs are requested first, followed by non-local ones.
-         */
-        cpu = req_mask_local_spread(i, pool->dev->numa_node, irqs_req_mask);
-
-        if (dh_irq_pool_is_sf_pool(pool))
-        {
-            irq = dh_irq_affinity_request(pool, cpumask_of(cpu));
-        }
-        else
-        {
-            irq = dh_irq_request(pool, i, cpumask_of(cpu), 0);
-        }
-        if (IS_ERR_OR_NULL(irq))
-        {
-            if (i == 0)
-            {
-                return PTR_ERR(irq);
-            }
-            return i;
-        }
-
-        irqs[i] = irq;
-        LOG_DEBUG("IRQ %u mapped to cpu %*pbl, %u EQs on this irq\n",
-               pci_irq_vector(pool->dev->pdev, dh_irq_get_index(irq)),
-               cpumask_pr_args(dh_irq_get_affinity_mask(irq)),
-               dh_irq_read_locked(irq) / DH_EQ_REFS_PER_IRQ);
-    }
-
-    return i;
-}
-
-struct dh_irq_pool *irq_pool_alloc(struct dh_core_dev *dev, int32_t start,
-                                   int32_t size, char *name,
-                                   u32 min_threshold, u32 max_threshold)
-{
-    struct dh_irq_pool *pool = kvzalloc(sizeof(*pool), GFP_KERNEL);
-
-    if (unlikely(pool == NULL))
-    {
-        LOG_ERR("pool kvzalloc failed\n");
-        return ERR_PTR(-ENOMEM);
-    }
-
-    pool->dev = dev;
-    mutex_init(&pool->lock);
-    xa_init_flags(&pool->irqs, XA_FLAGS_ALLOC);
-    pool->xa_num_irqs.min = start;
-    pool->xa_num_irqs.max = start + size - 1;
-
-    if (name)
-    {
-        snprintf(pool->name, DH_MAX_IRQ_NAME - DH_MAX_IRQ_IDX_CHARS, "%s", name);
-    }
-
-    pool->min_threshold = min_threshold * DH_EQ_REFS_PER_IRQ;
-    pool->max_threshold = max_threshold * DH_EQ_REFS_PER_IRQ;
-
-    return pool;
-}
-
-void irq_pool_free(struct dh_irq_pool *pool)
-{
-    struct dh_irq *irq = NULL;
-    unsigned long index;
-    uint32_t cpu;
-
-    /* There are cases in which we are destrying the irq_table before
-     * freeing all the IRQs, fast teardown for example. Hence, free the irqs
-     * which might not have been freed.
-     */
-    xa_for_each(&pool->irqs, index, irq)
-    {
-        irq_release(irq);
-    }
-    xa_destroy(&pool->irqs);
-    mutex_destroy(&pool->lock);
-
-    if (pool->irqs_per_cpu)
-    {
-        for_each_online_cpu(cpu)
-        {
-            WARN_ON(pool->irqs_per_cpu[cpu]);
-        }
-        kfree(pool->irqs_per_cpu);
-    }
-
-    kvfree(pool);
-}
-
-void dh_irq_table_cleanup(struct dh_core_dev *dev)
-{
-    if (dh_core_is_sf(dev))
-    {
-        return;
-    }
-
-    kvfree(dev->irq_table.priv);
-}
-
-void dh_irq_rename(struct dh_core_dev *dev, struct dh_irq *irq, const char *name)
-{
-    char *dst_name = irq->name;
-
-    if (!name)
-    {
-        char default_name[DH_MAX_IRQ_NAME];
-
-        irq_set_name(irq->pool, default_name, irq->index);
-        snprintf(dst_name, DH_MAX_IRQ_NAME, "%s@pci:%s", default_name, pci_name(dev->pdev));
-    }
-    else
-    {
-        snprintf(dst_name, DH_MAX_IRQ_NAME, "%s-%d", name, irq->index - DH_PF_IRQ_CTRL_NUM);
-    }
-}
+#include <linux/interrupt.h>
+#include <linux/notifier.h>
+#include <linux/module.h>
+#include <linux/dinghai/pci_irq.h>
+#include <linux/dinghai/helper.h>
+#include <linux/types.h>
+#include <linux/gfp.h>
+#include <linux/cpumask.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/lockdep.h>
+#include <linux/device.h>
+#include <linux/dinghai/dinghai_irq.h>
+
+#define DH_PF_IRQ_CTRL_NUM (1)
+
+#define DH_SFS_PER_CTRL_IRQ 64
+#define DH_IRQ_CTRL_SF_MAX 8
+/* min num of vectors for SFs to be enabled */
+#define DH_IRQ_VEC_COMP_BASE_SF 2
+
+#define DH_EQ_SHARE_IRQ_MAX_COMP (8)
+#define DH_EQ_SHARE_IRQ_MAX_CTRL (UINT_MAX)
+#define DH_EQ_SHARE_IRQ_MIN_COMP (1)
+#define DH_EQ_SHARE_IRQ_MIN_CTRL (4)
+
+static void irq_release(struct dh_irq *irq)
+{
+	struct dh_irq_pool *pool = irq->pool;
+
+	xa_erase(&pool->irqs, irq->index);
+	/* free_irq requires that affinity_hint and rmap will be cleared
+   * before calling it. This is why there is asymmetry with set_rmap
+   * which should be called after alloc_irq but before request_irq.
+   */
+	// irq_update_affinity_hint(irq->irqn, NULL);
+	irq_set_affinity_hint(irq->irqn, NULL);
+	free_cpumask_var(irq->mask);
+	free_irq(irq->irqn, &irq->nh);
+	kfree(irq);
+}
+
+int32_t dh_irq_put(struct dh_irq *irq)
+{
+	struct dh_irq_pool *pool = irq->pool;
+	int32_t ret = 0;
+
+	mutex_lock(&pool->lock);
+	irq->refcount--;
+	if (!irq->refcount) {
+		irq_release(irq);
+		ret = 1;
+	}
+	mutex_unlock(&pool->lock);
+
+	return ret;
+}
+
+int32_t dh_irq_read_locked(struct dh_irq *irq)
+{
+	lockdep_assert_held(&irq->pool->lock);
+
+	return irq->refcount;
+}
+
+int32_t dh_irq_get_locked(struct dh_irq *irq)
+{
+	lockdep_assert_held(&irq->pool->lock);
+	if (WARN_ON_ONCE(!irq->refcount)) {
+		return 0;
+	}
+
+	irq->refcount++;
+
+	return 1;
+}
+
+static int32_t irq_get(struct dh_irq *irq)
+{
+	int32_t err = 0;
+
+	mutex_lock(&irq->pool->lock);
+	err = dh_irq_get_locked(irq);
+	mutex_unlock(&irq->pool->lock);
+
+	return err;
+}
+
+static irqreturn_t irq_int_handler(int32_t irq, void *nh)
+{
+	atomic_notifier_call_chain(nh, 0, NULL);
+
+	return IRQ_HANDLED;
+}
+
+static void irq_set_name(struct dh_irq_pool *pool, char *name, int32_t vecidx)
+{
+	if (!strcmp(pool->name, "zxdh_pf_vq")) {
+		int type = (vecidx - pool->xa_num_irqs.min) % 2;
+		snprintf(name, DH_MAX_IRQ_NAME, "vq_%s_%d", type ? "output" : "input",
+				 vecidx);
+		return;
+	} else if (!strcmp(pool->name, "zxdh_pf_async")) {
+		snprintf(name, DH_MAX_IRQ_NAME, "async_%d", vecidx);
+		return;
+	}
+}
+
+struct dh_irq *dh_irq_alloc(struct dh_irq_pool *pool, int32_t i,
+							const struct cpumask *affinity)
+{
+	struct dh_core_dev *dev = pool->dev;
+	char name[DH_MAX_IRQ_NAME] = {};
+	struct dh_irq *irq = NULL;
+	int32_t err = 0;
+	int32_t num_cpu = 0;
+	int32_t cpu_loop = 0;
+
+	irq = kzalloc(sizeof(*irq), GFP_KERNEL);
+	if (unlikely(irq == NULL)) {
+		LOG_ERR("irq kzalloc failed\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	irq->irqn = pci_irq_vector(dev->pdev, i);
+	irq_set_name(pool, name, i);
+	ATOMIC_INIT_NOTIFIER_HEAD(&irq->nh);
+	snprintf(irq->name, DH_MAX_IRQ_NAME, "%s@pci:%s", name,
+			 pci_name(dev->pdev));
+	LOG_DEBUG("%s[%d] i=%d, irqn=%d, name=%s\r\n", __func__, __LINE__, i,
+			  irq->irqn, irq->name);
+
+	err = request_irq(irq->irqn, irq_int_handler, 0, irq->name, &irq->nh);
+	if (err != 0) {
+		LOG_ERR("Failed to request irq. err = %d\n", err);
+		goto err_req_irq;
+	}
+
+	if (!zalloc_cpumask_var(&irq->mask, GFP_KERNEL)) {
+		LOG_WARN("zalloc_cpumask_var failed\n");
+		err = -ENOMEM;
+		goto err_cpumask;
+	}
+
+	if (affinity != NULL) {
+		cpumask_copy(irq->mask, affinity);
+		irq_set_affinity_hint(irq->irqn, irq->mask);
+	} else {
+		num_cpu = num_online_cpus();
+		for (cpu_loop = 0; cpu_loop < num_cpu; cpu_loop++) {
+			cpumask_set_cpu(cpu_loop, irq->mask);
+		}
+		irq_set_affinity_hint(irq->irqn, irq->mask);
+	}
+
+	irq->pool = pool;
+	irq->refcount = 1;
+	irq->index = i;
+	err = xa_err(xa_store(&pool->irqs, irq->index, irq, GFP_KERNEL));
+	if (err != 0) {
+		LOG_ERR("Failed to alloc xa entry for irq(%u). err = %d\n", irq->index,
+				err);
+		goto err_xa;
+	}
+
+	return irq;
+
+err_xa:
+	irq_set_affinity_hint(irq->irqn, NULL);
+	free_cpumask_var(irq->mask);
+err_cpumask:
+	free_irq(irq->irqn, &irq->nh);
+err_req_irq:
+	kfree(irq);
+	return ERR_PTR(err);
+}
+
+int32_t dh_irq_attach_nb(struct dh_irq *irq, struct notifier_block *nb)
+{
+	int32_t ret = 0;
+
+	ret = irq_get(irq);
+	if (ret == 0) {
+		return -ENOENT;
+	}
+
+	ret = atomic_notifier_chain_register(&irq->nh, nb);
+	if (ret != 0) {
+		dh_irq_put(irq);
+	}
+
+	return ret;
+}
+
+int32_t dh_irq_detach_nb(struct dh_irq *irq, struct notifier_block *nb)
+{
+	int32_t err = 0;
+
+	err = atomic_notifier_chain_unregister(&irq->nh, nb);
+	dh_irq_put(irq);
+
+	return err;
+}
+
+struct cpumask *dh_irq_get_affinity_mask(struct dh_irq *irq)
+{
+	return irq->mask;
+}
+
+int32_t dh_irq_get_index(struct dh_irq *irq)
+{
+	return irq->index;
+}
+
+/* irq_pool API */
+static int32_t __attribute__((unused))
+irq_pool_size_get(struct dh_irq_pool *pool)
+{
+	return pool->xa_num_irqs.max - pool->xa_num_irqs.min + 1;
+}
+
+/* requesting an irq from a given pool according to given index */
+static struct dh_irq *irq_pool_request_vector(struct dh_irq_pool *pool,
+											  int32_t vecidx,
+											  const struct cpumask *affinity,
+											  u8 exclude)
+{
+	struct dh_irq *irq = NULL;
+
+	mutex_lock(&pool->lock);
+	irq = xa_load(&pool->irqs, vecidx);
+	if (irq != NULL) {
+		if (exclude) {
+			return ERR_PTR(-EEXIST);
+		}
+		dh_irq_get_locked(irq);
+		goto unlock;
+	}
+
+	irq = dh_irq_alloc(pool, vecidx, affinity);
+unlock:
+	mutex_unlock(&pool->lock);
+	return irq;
+}
+
+/**
+ * dh_irqs_release - release one or more IRQs back to the system.
+ * @irqs: IRQs to be released.
+ * @nirqs: number of IRQs to be released.
+ */
+static void dh_irqs_release(struct dh_irq **irqs, int32_t nirqs)
+{
+	int32_t i;
+
+	for (i = 0; i < nirqs; i++) {
+		synchronize_irq(irqs[i]->irqn);
+		dh_irq_put(irqs[i]);
+	}
+}
+
+/**
+ * dh_ctrl_irq_release - release a ctrl IRQ back to the system.
+ * @ctrl_irq: ctrl IRQ to be released.
+ */
+void dh_ctrl_irq_release(struct dh_irq *ctrl_irq)
+{
+	dh_irqs_release(&ctrl_irq, 1);
+}
+
+/* get a irq from pool*/
+struct dh_irq *zxdh_get_irq_of_pool(struct dh_core_dev *dev,
+									struct dh_irq_pool *pool)
+{
+	cpumask_var_t req_mask;
+	struct dh_irq *irq = NULL;
+
+	if (!zalloc_cpumask_var(&req_mask, GFP_KERNEL)) {
+		LOG_ERR("%s[%d]\r\n", __func__, __LINE__);
+		return ERR_PTR(-ENOMEM);
+	}
+	cpumask_copy(req_mask, cpu_online_mask);
+
+	LOG_DEBUG("%s[%d]\r\n", __func__, __LINE__);
+	irq = dh_irq_affinity_request(pool, req_mask);
+
+	free_cpumask_var(req_mask);
+	if (IS_ERR_OR_NULL(irq)) {
+		LOG_ERR("error: %s[%d] irq=0x%llx\r\n", __func__, __LINE__,
+				(unsigned long long)irq);
+	}
+
+	return irq;
+}
+
+/**
+ * dh_irq_request - request an IRQ for zxdh PF/VF device.
+ * @pool: requesting the IRQ from the irqs pool.
+ * @vecidx: vector index of the IRQ. This argument is ignore if affinity is
+ * provided.
+ * @affinity: cpumask requested for this IRQ.
+ *
+ * This function returns a pointer to IRQ, or ERR_PTR in case of error.
+ */
+struct dh_irq *dh_irq_request(struct dh_irq_pool *pool, u16 vecidx,
+							  const struct cpumask *affinity, u8 exclude)
+{
+	struct dh_irq *irq = NULL;
+
+	irq = irq_pool_request_vector(pool, vecidx, affinity, exclude);
+	if (IS_ERR_OR_NULL(irq))
+		return irq;
+	LOG_DEBUG("irq %u mapped to cpu %*pbl, %u EQs on this irq\n", irq->irqn,
+			  cpumask_pr_args(affinity), irq->refcount / DH_EQ_REFS_PER_IRQ);
+
+	return irq;
+}
+
+/**
+ * dh_irqs_release_vectors - release one or more IRQs back to the system.
+ * @irqs: IRQs to be released.
+ * @nirqs: number of IRQs to be released.
+ */
+void dh_irqs_release_vectors(struct dh_irq **irqs, int32_t nirqs)
+{
+	dh_irqs_release(irqs, nirqs);
+}
+
+/**
+ * dh_irqs_request_vectors - request one or more IRQs for zxdh device.
+ * @pool: requesting the IRQs from the irqs pool.
+ * @cpus: CPUs array for binding the IRQs
+ * @nirqs: number of IRQs to request.
+ * @irqs: an output array of IRQs pointers.
+ *
+ * Each IRQ is bound to at most 1 CPU.
+ * This function is requests nirqs IRQs, starting from @vecidx.
+ *
+ * This function returns the number of IRQs requested, (which might be smaller
+ * than
+ * @nirqs), if successful, or a negative error code in case of an error.
+ */
+int32_t dh_irqs_request_vectors(struct dh_irq_pool *pool, uint16_t *cpus,
+								int32_t nirqs, struct dh_irq **irqs)
+{
+	cpumask_var_t req_mask;
+	struct dh_irq *irq = NULL;
+	int32_t i;
+
+	if (!zalloc_cpumask_var(&req_mask, GFP_KERNEL)) {
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < nirqs; i++) {
+		cpumask_set_cpu(cpus[i], req_mask);
+		irq = dh_irq_request(pool, i, req_mask, 0);
+		if (IS_ERR_OR_NULL(irq)) {
+			break;
+		}
+		cpumask_clear(req_mask);
+		irqs[i] = irq;
+	}
+
+	free_cpumask_var(req_mask);
+
+	return i ? i : PTR_ERR(irq);
+}
+
+static int32_t req_mask_local_spread(int32_t i, int32_t node,
+									 const struct cpumask *irqs_req_mask)
+{
+	int32_t cpu;
+
+	if (node == NUMA_NO_NODE) {
+		for_each_cpu_and(cpu, cpu_online_mask, irqs_req_mask) {
+			if (i-- == 0) {
+				return cpu;
+			}
+		}
+	} else {
+		/* NUMA first. */
+		for_each_cpu_and(cpu, cpumask_of_node(node), irqs_req_mask) {
+			if (cpu_online(cpu)) {
+				if (i-- == 0) {
+					return cpu;
+				}
+			}
+		}
+
+		for_each_online_cpu(cpu) {
+			/* Skip NUMA nodes, done above. */
+			if (cpumask_test_cpu(cpu, cpumask_of_node(node))) {
+				continue;
+			}
+
+			if (i-- == 0) {
+				return cpu;
+			}
+		}
+	}
+	WARN_ON(true);
+
+	return cpumask_first(cpu_online_mask);
+}
+
+/**
+ * dh_irqs_request_mask - request one or more IRQs for zxdh device.
+ * @pool: requesting the IRQs from the irqs pool.
+ * @irqs: an output array of IRQs pointers.
+ * @irqs_req_mask: cpumask requested for these IRQs.
+ *
+ * Each IRQ is bounded to at most 1 CPU.
+ * This function returns the number of IRQs requested, (which might be smaller
+ * than cpumask_weight(@irqs_req_mask)), if successful, or a negative error code
+ * in case of an error.
+ */
+int32_t dh_irqs_request_mask(struct dh_irq_pool *pool, struct dh_irq **irqs,
+							 struct cpumask *irqs_req_mask)
+{
+	struct dh_irq *irq = NULL;
+	int32_t nirqs;
+	int32_t cpu;
+	int32_t i;
+
+	/* Request an IRQ for each online CPU in the given mask */
+	cpumask_and(irqs_req_mask, irqs_req_mask, cpu_online_mask);
+	nirqs = cpumask_weight(irqs_req_mask);
+	for (i = 0; i < nirqs; i++) {
+		/* Iterate over the mask the caller provided in numa aware fashion.
+     * Local CPUs are requested first, followed by non-local ones.
+     */
+		cpu = req_mask_local_spread(i, pool->dev->numa_node, irqs_req_mask);
+
+		if (dh_irq_pool_is_sf_pool(pool)) {
+			irq = dh_irq_affinity_request(pool, cpumask_of(cpu));
+		} else {
+			irq = dh_irq_request(pool, i, cpumask_of(cpu), 0);
+		}
+		if (IS_ERR_OR_NULL(irq)) {
+			if (i == 0) {
+				return PTR_ERR(irq);
+			}
+			return i;
+		}
+
+		irqs[i] = irq;
+		LOG_DEBUG("IRQ %u mapped to cpu %*pbl, %u EQs on this irq\n",
+				  pci_irq_vector(pool->dev->pdev, dh_irq_get_index(irq)),
+				  cpumask_pr_args(dh_irq_get_affinity_mask(irq)),
+				  dh_irq_read_locked(irq) / DH_EQ_REFS_PER_IRQ);
+	}
+
+	return i;
+}
+
+struct dh_irq_pool *irq_pool_alloc(struct dh_core_dev *dev, int32_t start,
+								   int32_t size, char *name, u32 min_threshold,
+								   u32 max_threshold)
+{
+	struct dh_irq_pool *pool = kvzalloc(sizeof(*pool), GFP_KERNEL);
+
+	if (unlikely(pool == NULL)) {
+		LOG_ERR("pool kvzalloc failed\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	pool->dev = dev;
+	mutex_init(&pool->lock);
+	xa_init_flags(&pool->irqs, XA_FLAGS_ALLOC);
+	pool->xa_num_irqs.min = start;
+	pool->xa_num_irqs.max = start + size - 1;
+
+	if (name) {
+		snprintf(pool->name, DH_MAX_IRQ_NAME - DH_MAX_IRQ_IDX_CHARS, "%s",
+				 name);
+	}
+
+	pool->min_threshold = min_threshold * DH_EQ_REFS_PER_IRQ;
+	pool->max_threshold = max_threshold * DH_EQ_REFS_PER_IRQ;
+	LOG_DEBUG("pool->name = %s, pool->size = %d, pool->start = %d", name, size,
+			  start);
+
+	return pool;
+}
+
+void irq_pool_free(struct dh_irq_pool *pool)
+{
+	struct dh_irq *irq = NULL;
+	unsigned long index;
+	uint32_t cpu;
+
+	/* There are cases in which we are destrying the irq_table before
+   * freeing all the IRQs, fast teardown for example. Hence, free the irqs
+   * which might not have been freed.
+   */
+	xa_for_each(&pool->irqs, index, irq) {
+		irq_release(irq);
+	}
+	xa_destroy(&pool->irqs);
+	mutex_destroy(&pool->lock);
+
+	if (pool->irqs_per_cpu) {
+		for_each_online_cpu(cpu) {
+			WARN_ON(pool->irqs_per_cpu[cpu]);
+		}
+		kfree(pool->irqs_per_cpu);
+	}
+
+	kvfree(pool);
+}
+
+void dh_irq_table_cleanup(struct dh_core_dev *dev)
+{
+	if (dh_core_is_sf(dev)) {
+		return;
+	}
+
+	kvfree(dev->irq_table.priv);
+}
+
+void dh_irq_rename(struct dh_core_dev *dev, struct dh_irq *irq,
+				   const char *name)
+{
+	char *dst_name = irq->name;
+
+	if (!name) {
+		char default_name[DH_MAX_IRQ_NAME];
+
+		irq_set_name(irq->pool, default_name, irq->index);
+		snprintf(dst_name, DH_MAX_IRQ_NAME, "%s@pci:%s", default_name,
+				 pci_name(dev->pdev));
+	} else {
+		snprintf(dst_name, DH_MAX_IRQ_NAME, "%s-%d", name,
+				 irq->index - DH_PF_IRQ_CTRL_NUM);
+	}
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/plcr.c b/src/net/drivers/net/ethernet/dinghai/plcr.c
index 8e6eaa89c6ff3d2cdfc78a0b7788d6fef0828e2d..b1cc873e6d0a4cea2707ed7dc037ed890e9b8154 100644
--- a/src/net/drivers/net/ethernet/dinghai/plcr.c
+++ b/src/net/drivers/net/ethernet/dinghai/plcr.c
@@ -1,2371 +1,1100 @@
-#include <linux/dinghai/auxiliary_bus.h>
-#include <linux/dinghai/driver.h>
-#include <net/devlink.h>
-#include <net/udp_tunnel.h>
-#include <linux/dinghai/devlink.h>
-#include <linux/dinghai/dh_cmd.h>
-#include <linux/netdevice.h>
-#include "en_aux.h"
-#include "en_ethtool/ethtool.h"
-#include <linux/dinghai/en_sf.h>
-#include <linux/etherdevice.h>
-#include <linux/dinghai/helper.h>
-#include "en_np/table/include/dpp_tbl_api.h"
-#include "en_aux/events.h"
-#include "en_aux/eq.h"
-#include "en_aux/en_cmd.h"
-#include "msg_common.h"
-#include "en_pf.h"
-#include <linux/dinghai/kcompat.h>
-#include "en_aux/en_ioctl.h"
-#ifdef TIME_STAMP_1588
-#include "en_aux/en_1588_pkt_proc.h"
-#endif
-
-const uint32_t gaudPlcrCarxProfileNum[E_PLCR_CAR_NUM]={
-    PLCR_CAR_A_PROFILE_RES_NUM,   //一级CAR：512个限速模板
-    PLCR_CAR_B_PROFILE_RES_NUM,   //二级CAR：128个限速模板
-    PLCR_CAR_C_PROFILE_RES_NUM,   //三级CAR：32个限速模板
-};
-
-const uint32_t gaudPlcrCarxFlowIdNum[E_PLCR_CAR_NUM]={
-    PLCR_CAR_A_FLOWID_RES_NUM,   //一级CAR：包含内核和dpdk的id
-    PLCR_CAR_B_FLOWID_RES_NUM,   //二级CAR：前2304个分配给vf，后64个个分配给pf
-    PLCR_CAR_C_FLOWID_RES_NUM,   //三级CAR
-};
-
-struct zxdh_plcr_cbs gat_carA_byte_rate_limit_cbs[] =
-{
-    {0,     500,    4*1024*1024},
-    {500,   800,    10*1024*1024},
-    {800,   1500,   12*1024*1024},
-    {1500,  3000,   15*1024*1024},
-    {3000,  12000,  20*1024*1024},
-    {12000, 20000,  30*1024*1024},
-    {20000, 500000, 50*1024*1024},
-};
-
-struct zxdh_plcr_cbs gat_carB_byte_rate_limit_cbs[] =
-{
-    {0,     4000,   8*1024*1024},
-    {4000,  8000,   16*1024*1024},
-    {8000,  16000,  64*1024*1024},
-    {16000, 500000, 128*1024*1024 - 1},
-};
-
-static inline struct zxdh_en_device *pf_dev_get_edev(struct zxdh_pf_device *pf_dev)
-{
-    struct zxdh_auxiliary_device *adev = NULL;
-    struct zxdh_en_sf_container *sf_con = NULL;
-    struct zxdh_en_sf_device *en_sf_dev = NULL;
-    struct zxdh_en_priv *en_priv = NULL;
-    struct zxdh_en_device *en_dev = NULL;
-
-    adev = pf_dev->adevs_table[0].adev; //sf adev
-    sf_con = container_of(adev, struct zxdh_en_sf_container, adev);
-    en_sf_dev = dh_core_priv(sf_con->cdev); //sf cdev
-    en_priv = en_sf_dev->adev[0]->dev.driver_data; //en adev
-    en_dev = &en_priv->edev;
-
-    if (!en_dev->init_comp_flag) {
-        LOG_ERR("en_device not initialized!\n");
-        return ERR_PTR(-ENODEV);
-    }
-
-    return en_dev;
-}
-
-uint32_t zxdh_plcr_get_cbs(E_PLCR_CAR_TYPE car_type, E_RATE_LIMIT_PKT_BYTE is_pkt_mode, uint32_t user_rate_limit, uint32_t *cbs)
-{
-    uint32_t num;
-    uint32_t index;
-    uint32_t flag;
-    struct zxdh_plcr_cbs *plcr_cbs;
-
-    if (E_RATE_LIMIT_BYTE == is_pkt_mode)
-    {
-        if (E_PLCR_CAR_A == car_type)
-        {
-            num = sizeof(gat_carA_byte_rate_limit_cbs)/sizeof(struct zxdh_plcr_cbs);
-            plcr_cbs = &gat_carA_byte_rate_limit_cbs[0];
-        }
-        else if (E_PLCR_CAR_B == car_type)
-        {
-            num = sizeof(gat_carB_byte_rate_limit_cbs)/sizeof(struct zxdh_plcr_cbs);
-            plcr_cbs = &gat_carB_byte_rate_limit_cbs[0];
-        }
-        else if (E_PLCR_CAR_C == car_type)
-        {
-            //todo：需要遍历测试得到cbs
-            *cbs = 8*1024*1024;
-            return 0;
-        }
-        else
-        {
-            return -ERANGE;
-        }
-
-        for(index=0,flag=0; index<num; index++)
-        {
-            if ((user_rate_limit >= plcr_cbs[index].min_rate) && (user_rate_limit < plcr_cbs[index].max_rate))
-            {
-                *cbs = plcr_cbs[index].cbs;
-                flag = 1;
-                break;
-            }
-        }
-        if(0 == flag)
-        {
-            return -ERANGE;
-        }
-    }
-    else
-    {
-        //todo：包限速对应的cbs需要后续遍历测试得到
-        return -ERANGE;
-    }
-
-    return 0;
-}
-
-/*
-todo:
-rsvd字段为1标识失败，为0标识成功
-修改原有的限速值，只用修改限速模板，不用再调用关联函数；
-还有代码中在配置限速模板的时候引用+1了，会影响现有的流程的（结果可能没问题，需要考虑是不是将+1和-1更换位置）；
-如果找到共享模板，在配置队列失败的时候会减一，加一和减一的位置不对称，会导致计数值不正确。
-*/
-
-/*
-函数功能：将用户输入的速率，转换成限速模板配置寄存器的格式
-入参：
-    ---max_rate   : 单位是Mbit/s
-
-返回值：返回vqm中的发送队列号，发送队列号为奇数
-*/
-uint32_t zxdh_plcr_user_maxrate_2_reg(uint32_t user_max_rate)
-{
-    uint64_t reg_maxrate;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    reg_maxrate = ((uint64_t)user_max_rate * 1024 / PLCR_STEP_SIZE);//改为61kbps的倍数,单位由"Mbps"转化为"61Kbps" (uint32_t)(max_rate + 0.5)* 1000 / PLCR_STEP_SIZE
-
-    reg_maxrate = (reg_maxrate < PLCR_MIN_RATE) ? PLCR_MIN_RATE : reg_maxrate;
-    reg_maxrate = (reg_maxrate > PLCR_MAX_RATE) ? PLCR_MAX_RATE : reg_maxrate;
-
-    return (uint32_t)reg_maxrate;
-}
-
-/*
-函数功能：将寄存器中的配置值，转换成用户的限速值（）
-将用户输入的速率，转换成限速模板配置寄存器的格式
-入参：
-    ---maxrate_cfg   : 单位是61Kb/s
-出参：
-    ---user_max_rate : 单位是Mbit/s
-
-返回值：返回vqm中的发送队列号，发送队列号为奇数
-*/
-uint32_t zxdh_plcr_reg_maxrate_user(uint32_t reg_maxrate)
-{
-    uint32_t user_max_rate;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    user_max_rate = reg_maxrate * PLCR_STEP_SIZE / 1024;
-
-    return user_max_rate;
-}
-
-/*
-函数功能：查找是否有共享的限速模板
-入参：
-    ---pf_dev     : pf设备结构体
-    ---car_type   : plcr CAR层级，取值：CAR_A，CAR_B，CAR_C
-    ---profile_cfg: 待查询的限速模板参数，可能是字节限速模板或者包限速模板
-    ---profile_id : 保存查询到的限速模板的id
-
-返回值：0表示查询成功，其它值表示查询失败
-*/
-static int32_t zxdh_plcr_match_profile(struct zxdh_pf_device *pf_dev,
-                                              E_PLCR_CAR_TYPE car_type,
-                                  DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg,
-                                                    uint16_t *profile_id)
-{
-    struct xarray            *xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]);
-    struct zxdh_plcr_profile *profile;
-    unsigned long             index;
-    DPP_STAT_CAR_PKT_PROFILE_CFG_T  *pkt_profile_cfg = (DPP_STAT_CAR_PKT_PROFILE_CFG_T  *)(profile_cfg);
-    uint32_t                  profile_max_num = gaudPlcrCarxProfileNum[car_type];
-
-    PLCR_FUNC_DBG_ENTER();
-
-    /*遍历vf申请的某一级CAR所有限速模板，是否有指定速率的限速模板存在*/
-    xa_for_each_range(xarray_profile, index, profile, 0, profile_max_num)
-    {
-        if(0 == profile->ref_cnt)
-        {
-            continue;
-        }
-
-        /*包限速模板比较*/
-        if (E_RATE_LIMIT_PACKET ==profile_cfg->pkt_sign)
-        {
-            if ((pkt_profile_cfg->pkt_sign == (((DPP_STAT_CAR_PKT_PROFILE_CFG_T  *)(&profile->profile_cfg))->pkt_sign)) &&
-                (pkt_profile_cfg->cir      == (((DPP_STAT_CAR_PKT_PROFILE_CFG_T  *)(&profile->profile_cfg))->cir))      &&
-                (pkt_profile_cfg->cbs      == (((DPP_STAT_CAR_PKT_PROFILE_CFG_T  *)(&profile->profile_cfg))->cbs)))
-            {
-                *profile_id = profile->profile_id;
-                PLCR_LOG_INFO("profile_id = %d\n", *profile_id);
-
-                return 0;
-            }
-        }
-        //字节限速模板比较
-        else if (E_RATE_LIMIT_BYTE ==profile_cfg->pkt_sign)
-        {
-            if((profile->profile_cfg.pkt_sign == profile_cfg->pkt_sign) &&
-               (profile->profile_cfg.cd       == profile_cfg->cd)  &&  /**<  @brief CD算法标志/令牌桶算法标志 0:srtcm 1:trtcm 2:MEF10.1*/
-               (profile->profile_cfg.cf       == profile_cfg->cf)  &&  /**<  @brief CF溢出耦合标志，0:不溢出，1:溢出*/
-               (profile->profile_cfg.cm       == profile_cfg->cm)  &&  /**<  @brief CM色盲/色敏标志，0:色盲模式，1:色敏模式 */
-               (profile->profile_cfg.cir      == profile_cfg->cir) &&  /**<  @brief C令牌桶添加速率(0~X, X Gbps/64kbps),最小值为64Kbps，步长为64Kbps*/
-               (profile->profile_cfg.cbs      == profile_cfg->cbs) &&  /**<  @brief C桶桶深(XM),配置范围为0~XMByte-1，步长为1Byte*/
-               (profile->profile_cfg.eir      == profile_cfg->eir) &&  /**<  @brief E令牌桶添加速率(0~X, XGbps/64kbps),最小值为64Kbps，步长为64Kbps*/
-               (profile->profile_cfg.ebs      == profile_cfg->ebs))    /**<  @brief E桶桶深(XM),配置范围为0~XMByte-1，步长为1Byte*/
-            {
-                *profile_id = profile->profile_id;
-                PLCR_LOG_INFO("profile_id = %d\n", *profile_id);
-
-                return 0;
-            }
-        }
-    }
-
-    /* 未搜索到匹配项*/
-    return -ERANGE;
-}
-
-/*
-函数功能：为flowid申请一个xarray成员
-入参：
-    ---pf_dev     : pf设备结构体
-    ---car_type   : plcr CAR层级，一级，二级或三级
-    ---flow_id    : 作为xarray的索引
-返回值：返回创建的zxdh_plcr_flow *指针
-*/
-int32_t zxdh_plcr_req_flow(struct zxdh_pf_device *pf_dev,
-                                  E_PLCR_CAR_TYPE car_type,
-                                         uint16_t flow_id,
-                          struct zxdh_plcr_flow **flow)
-{
-    struct zxdh_plcr_flow *flow_old;
-    struct xarray         *xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]);
-
-    PLCR_FUNC_DBG_ENTER();
-
-    /*1. malloc一个flow结构体*/
-    *flow = kzalloc(sizeof(struct zxdh_plcr_flow), GFP_KERNEL);
-    if (unlikely(NULL == *flow))
-    {
-        PLCR_LOG_ERR("failed to kzalloc \n");
-        return -EINVAL;
-    }
-
-    /*2. 存储到xarray*/
-    flow_old = xa_store(xarray_flow, flow_id, *flow, GFP_KERNEL);
-    if (flow_old)
-    {
-        /* 正常情况下，这里应该都是空的*/
-        kfree(flow_old);
-    }
-
-    return 0;
-}
-
-/*
-函数功能：释放一个xarray下的flowid成员
-入参：
-    ---pf_dev     : pf设备结构体
-    ---car_type   : plcr CAR层级，一级，二级或三级
-    ---flow_id    : 作为xarray的索引
-返回值：返回创建的zxdh_plcr_flow *指针
-*/
-int32_t zxdh_plcr_release_flow(struct zxdh_pf_device *pf_dev,
-                                      E_PLCR_CAR_TYPE car_type,
-                                             uint16_t flow_id)
-{
-    struct zxdh_plcr_flow *flow;
-    struct xarray         *xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]);
-
-    PLCR_FUNC_DBG_ENTER();
-
-    /*1. 检查xarray里是否有该flow*/
-    flow = xa_load(xarray_flow, flow_id);
-    if (NULL == flow)
-    {
-        PLCR_LOG_ERR("failed to release an invalid flow_id=%d\n", flow_id);
-        return EINVAL;
-    }
-
-    /*2. 从xarray删除该成员*/
-    xa_erase(xarray_flow, flow_id);
-
-    /*3. 释放flow*/
-    kfree(flow);
-
-    return 0;
-}
-
-/*
-函数功能：更新flow的成员信息
-入参：
-    ---flow       : xarray的成员
-    ---vport      :
-    ---max_rate   :
-    ---min_rate   :
-返回值：无
-*/
-void zxdh_plcr_update_flow(struct zxdh_plcr_flow *flow,
-                                         uint16_t vport,
-                                         uint32_t max_rate,
-                                         uint32_t min_rate)
-{
-    flow->vport    = vport;
-    flow->max_rate = max_rate;
-    flow->min_rate = min_rate;
-}
-
-/*
-函数功能：申请一个指定CAR的限速模板
-入参：
-    ---pf_dev     : pf设备结构体
-    ---car_type   : plcr CAR层级，一级，二级或三级
-    ---vport      : vf端口号
-    ---profile_id_out : 返回申请到的限速模板的profile_id
-返回值：成功返回0，失败返回其它值
-*/
-int zxdh_plcr_req_profile(struct zxdh_pf_device *pf_dev,
-                                 E_PLCR_CAR_TYPE car_type,
-                                       uint16_t *profile_id_out)
-{
-    int  rtn = 0;
-    struct zxdh_plcr_profile *profile;
-    struct zxdh_plcr_profile *profile_old;
-    struct xarray *xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]);
-    uint16_t profile_id = 0;
-    uint64_t cred_id = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = pf_dev->slot_id;
-    pf_info.vport = pf_dev->vport;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    /*在指定的CAR申请一个新的限速模板*/
-    rtn = dpp_car_profile_id_add(&pf_info, (uint32_t)car_type, &cred_id);
-    if (rtn)
-    {
-        /*判断消息交互是否正常*/
-        PLCR_LOG_ERR("failed to request a new profile\n");
-        return -EINVAL;
-    }
-
-    /*判断riscv是否成功返回了有效的profile：bit[56 - 63]为0标识成功，为1标识失败*/
-    if (0 != ((cred_id >> 56) & 0xFF))
-    {
-        PLCR_LOG_ERR("failed to request a new profile\n");
-        return -EINVAL;
-    }
-
-    /*提取profile id*/
-    profile_id = PROFILE_ID(cred_id);
-    *profile_id_out = profile_id;
-    PLCR_LOG_INFO("dpp_car_profile_id_add: pf_info.vport = 0x%x, car_type = %d, profile_id = %d, cred_id = 0x%llx\n", pf_info.vport, car_type, profile_id, cred_id);
-
-    /*申请一个限速模板结构体，保存限速模板信息*/
-    profile = kzalloc(sizeof(struct zxdh_plcr_profile), GFP_KERNEL);
-    if (unlikely(NULL == profile))
-    {
-        dpp_car_profile_id_delete(&pf_info, (uint32_t)car_type, cred_id);
-        PLCR_LOG_ERR("failed to kzalloc profile\n");
-
-        return -EINVAL;
-    }
-    profile->ref_cnt    = 0;
-    profile->max_rate   = 0;
-    profile->min_rate   = 0;
-    profile->cred_id    = cred_id;
-    profile->profile_id = profile_id;
-    profile->vport      = pf_dev->vport;
-
-    /*将申请到的限速模板资源存储起来*/
-    profile_old = xa_store(xarray_profile, profile_id, profile, GFP_KERNEL);
-    if (profile_old)          //正常情况下，这里应该都是空的
-    {
-        PLCR_LOG_ERR("failed to unreachable branch\n");
-        kfree(profile_old);
-    }
-
-
-    return rtn;
-}
-
-/*
-函数功能：释放一个指定CAR的限速模板
-入参：
-    ---pf_dev     : pf设备结构体
-    ---car_type   : plcr CAR层级，一级，二级或三级
-    ---Profile_id : 限速模板的profile_id
-返回值：成功返回0，失败返回其它值
-*/
-int zxdh_plcr_release_profile(struct zxdh_pf_device *pf_dev,
-                                     E_PLCR_CAR_TYPE car_type,
-                                            uint16_t profile_id)
-{
-    int    rtn = 0;
-    struct xarray *xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]);
-    struct zxdh_plcr_profile *profile;
-    DPP_PF_INFO_T pf_info = {0};
-
-    PLCR_FUNC_DBG_ENTER();
-
-    /*判断是有是有效成员*/
-    profile = xa_load(xarray_profile, profile_id);
-    if (NULL == profile)
-    {
-        PLCR_LOG_ERR("failed to release an invalid profile=%d\n", profile_id);
-        return EINVAL;
-    }
-
-    /*如果引用计数为0，则可以释放所有资源*/
-    if (0 == profile->ref_cnt)
-    {
-        pf_info.slot  = pf_dev->slot_id;
-        pf_info.vport = profile->vport;
-        PLCR_LOG_INFO("dpp_car_profile_id_delete: pf_info.vport = 0x%x, car_type = %d, profile_id = %d, cred_id = 0x%llx\n", pf_info.vport, car_type, profile_id, profile->cred_id);
-
-        /*归还限速模板资源（注意，引用计数为0表示没有关联的flow了）*/
-        rtn = dpp_car_profile_id_delete(&pf_info, car_type, profile->cred_id);
-        if (rtn)
-        {
-            PLCR_LOG_ERR("failed to call dpp_car_profile_id_delete, car_type=%d,profile_id=%d)\n", car_type, profile_id);
-            rtn = EINVAL;
-        }
-
-        /*删除xarray中的元素*/
-        xa_erase(xarray_profile, profile_id);
-
-        /*释放profile指针*/
-        kfree(profile);
-    }
-
-    /*如果引用计数不为0，就不释放任何资源*/
-    return rtn;
-}
-
-/*
-函数功能：内核态使用的接口，根据car_type & is_byte_rate_limit & max_rate & min_rate 这4个参数生成限速模板配置参数
-        内核态下各限速场景使用的参数应该是固定的，我们自己根据这4个参数生成完整的结构体参数：DPP_STAT_CAR_PROFILE_CFG_T
-        用户态的场景下，会通过消息直接传递过来，不需要组装
-入参：
-    ---is_pkt_mode: 包限速还是字节限速
-    ---car_type   : plcr CAR层级，一级，二级或三级
-    ---is_byte_rate_limit   : 是否是字节限速，为后续包限速预留参数，这个值传参的时候暂时固定为1，
-                              后续可能会有一个全局变量进行指示，会提供对应的接口来获取这个入参值进行传递
-    ---max_rate             : 用户指定的最大限速值
-    ---min_rate             : 用户指定的最小承诺速率
-    ---profile_cfg          : 返回值，填充好的限速模板参数
-返回值：成功返回0，失败返回其它值
-*/
-static int zxdh_plcr_gen_profile(struct zxdh_pf_device *pf_dev,
-                                  E_RATE_LIMIT_PKT_BYTE is_pkt_mode,
-                                        E_PLCR_CAR_TYPE car_type,
-                                               uint32_t max_rate,
-                                               uint32_t min_rate,
-                            DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg)
-{
-    int      rtn = 0;
-    int      pri = 0;
-    uint32_t cbs = 0;
-    uint32_t ebs = 0;
-    DPP_STAT_CAR_PKT_PROFILE_CFG_T  *pkt_profile_cfg = (DPP_STAT_CAR_PKT_PROFILE_CFG_T  *)(profile_cfg);
-
-    PLCR_FUNC_DBG_ENTER();
-
-    //入参检测
-    if ((E_RATE_LIMIT_PACKET == is_pkt_mode) && (E_PLCR_CAR_A != car_type))
-    {
-        PLCR_LOG_ERR("failed and only CAR A supports packet rate limit\n");
-        rtn = EINVAL;
-    }
-
-    /*2. 重新生成参数*/
-
-    /*填充限速模板的参数，准备将这些参数配置到寄存器*/
-    memset(profile_cfg, 0, sizeof(*profile_cfg));
-    if (E_RATE_LIMIT_BYTE == is_pkt_mode)
-    {
-        profile_cfg->pkt_sign       = E_RATE_LIMIT_BYTE;
-        profile_cfg->cf             = 1; //溢出标志，默认使能
-
-        if (pf_dev->plcr_table.burst_size)
-        {
-            cbs = pf_dev->plcr_table.burst_size;
-            ebs = pf_dev->plcr_table.burst_size;
-        }
-        else
-        {
-            rtn = zxdh_plcr_get_cbs(car_type, E_RATE_LIMIT_BYTE, min_rate, &cbs);
-            PLCR_COMM_ASSERT(rtn);
-            rtn = zxdh_plcr_get_cbs(car_type, E_RATE_LIMIT_BYTE, max_rate, &ebs);
-            PLCR_COMM_ASSERT(rtn);
-        }
-
-        profile_cfg->cbs            = cbs;
-        profile_cfg->ebs            = ebs;
-        profile_cfg->random_disc_c  = 0;
-        profile_cfg->random_disc_e  = 0;
-
-        if (E_PLCR_CAR_A == car_type)
-        {
-            profile_cfg->cm         = 0; //色盲模式
-            profile_cfg->cd         = 0; //0: srTCM，单速率；1：双速率
-            profile_cfg->cir        = zxdh_plcr_user_maxrate_2_reg(max_rate);
-            profile_cfg->eir        = 0;
-        }
-        else if (E_PLCR_CAR_B == car_type)
-        {
-            profile_cfg->cm         = 0; //色盲模式，todo：根据实际测试情况来调整
-            profile_cfg->cd         = 1; //0: srTCM，单速率；1：双速率
-            profile_cfg->cir        = zxdh_plcr_user_maxrate_2_reg(min_rate);
-            profile_cfg->eir        = zxdh_plcr_user_maxrate_2_reg(max_rate);
-        }
-        else if (E_PLCR_CAR_C == car_type)
-        {
-            //todo：端口组限速，待调试确认
-            profile_cfg->cm         = 1; //色敏模式，todo：根据实际测试情况来调整
-            profile_cfg->cd         = 0; //0: srTCM，单速率；1：双速率
-            profile_cfg->cir        = zxdh_plcr_user_maxrate_2_reg(max_rate);
-            profile_cfg->eir        = 0;
-        }
-
-        for (pri = 0; pri < DPP_CAR_PRI_MAX; pri ++)
-        {
-            profile_cfg->c_pri[pri] = 0;
-            profile_cfg->e_green_pri[pri] = 0;
-            profile_cfg->e_yellow_pri[pri] = 0;
-        }
-
-        PLCR_LOG_INFO("cir = 0x%x, eir = 0x%x, cbs = 0x%x, ebs = 0x%x\n", profile_cfg->cir, profile_cfg->eir, profile_cfg->cbs, profile_cfg->ebs);
-    }
-    else
-    {
-        pkt_profile_cfg->pkt_sign = E_RATE_LIMIT_PACKET;
-        pkt_profile_cfg->cbs      = PLCR_CAR_PROFILE_GENERAL_CBS;
-        pkt_profile_cfg->cir      = max_rate;
-
-        PLCR_LOG_INFO("cir = 0x%x, cbs = 0x%x\n", pkt_profile_cfg->cir, pkt_profile_cfg->cbs);
-    }
-
-    return rtn;
-}
-
-/*
-函数功能：更新限速模板参数
-入参：
-    ---profile_cfg: 限速模板参数结构体
-    ---Profile_id : 限速模板的profile_id
-返回值：无
-*/
-static void zxdh_plcr_update_profile(DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg, u_int16_t profile_id)
-{
-    PLCR_FUNC_DBG_ENTER();
-
-    /*1. 重新生成参数*/
-    profile_cfg->profile_id = profile_id;
-}
-
-/*
-函数功能：将限速模板参数，存储到profile下
-入参：
-    ---pf_dev     : pf设备结构体
-    ---car_type   : plcr CAR层级，一级，二级或三级
-    ---max_rate   : 用户原始的限速速率，单位是Mbit/s
-    ---min_rate   : 用户原始的限速速率，单位是Mbit/s
-    ---profile_cfg: 要存储到profile中的，限速模板参数
-返回值：成功返回0，失败返回其它值
-*/
-int zxdh_plcr_store_profile(struct zxdh_pf_device *pf_dev,
-                                   E_PLCR_CAR_TYPE car_type,
-                                          uint32_t user_max_rate,
-                                          uint32_t user_min_rate,
-                       DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg)
-{
-    int    rtn = 0;
-    uint16_t profile_id;
-    struct zxdh_plcr_profile *profile;
-    struct xarray *xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]);
-
-    PLCR_FUNC_DBG_ENTER();
-
-    /*1. 从限速模板结构体，获取profile_id*/
-    profile_id = profile_cfg->profile_id;
-
-    /*2. 从xarray获取profile*/
-    profile = xa_load(xarray_profile, profile_id);
-    if (NULL == profile)
-    {
-        PLCR_LOG_ERR("failed to specify an invalid profile, profile_id=%d\n", profile_id);
-        return -EINVAL;
-    }
-
-    /*3. 更新profile的参数*/
-    profile->max_rate = user_max_rate;
-    profile->min_rate = user_min_rate;
-
-    /*4. 将完整的限速模板参数，存储到profile结构体下*/
-    memcpy(&profile->profile_cfg, profile_cfg, sizeof(DPP_STAT_CAR_PROFILE_CFG_T));
-
-    return rtn;
-}
-
-/*
-函数功能：将限速模板参数，配置到plcr寄存器中去
-入参：
-    ---pf_dev     : pf设备结构体
-    ---car_type   : plcr CAR层级，一级，二级或三级
-    ---profile_cfg: 要配置个plcr寄存器的限速模板参数
-返回值：成功返回0，失败返回其它值
-*/
-int zxdh_plcr_cfg_profile(struct zxdh_pf_device *pf_dev,
-                                 E_PLCR_CAR_TYPE car_type,
-                     DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg)
-{
-    int      rtn = 0;
-    uint16_t profile_id = 0;
-    uint32_t pkt_sign   = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = pf_dev->slot_id;
-    pf_info.vport = pf_dev->vport;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    /*1. 根据限速模板参数，获取profile_id*/
-    profile_id = profile_cfg->profile_id;
-
-    /*2. 根据限速模板参数，获取包/字节模式*/
-    pkt_sign = profile_cfg->pkt_sign;
-
-    /*3. 将限速模板参数，配置到寄存器中去*/
-    rtn = dpp_car_profile_cfg_set(&pf_info, (uint32_t)car_type, pkt_sign, profile_id, profile_cfg);
-    if (rtn)
-    {
-        PLCR_LOG_ERR("failed to configure the profile registers, car_type=%d,profile_id=%d\n", car_type, profile_id);
-        return -EINVAL;
-    }
-    PLCR_LOG_INFO("dpp_car_profile_cfg_set: pf_info.vport = 0x%x, car_type = %d, profile_id = %d, pkt_sign = %d\n", pf_info.vport, car_type, profile_id, pkt_sign);
-
-    return rtn;
-}
-
-/*
-函数功能：获取寄存器中限速模板的参数
-入参：
-    ---pf_dev     : pf设备结构体
-    ---car_type   : plcr CAR层级，一级，二级或三级
-    ---profile_cfg: 要配置个plcr寄存器的限速模板参数
-返回值：成功返回0，失败返回其它值
-*/
-int zxdh_plcr_get_profile(struct zxdh_pf_device *pf_dev,
-                                 E_PLCR_CAR_TYPE car_type,
-                                        uint32_t pkt_sign,
-                                        uint16_t profile_id,
-                     DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg)
-{
-    int    rtn = 0;
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = pf_dev->slot_id;
-    pf_info.vport = pf_dev->vport;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    /*3. 将限速模板参数，配置到寄存器中去*/
-    PLCR_LOG_INFO("dpp_car_profile_cfg_get: pf_info.vport = 0x%x, car_type = %d, profile_id = %d, pkt_sign = %d\n", pf_info.vport, car_type, profile_id, pkt_sign);
-    rtn = dpp_car_profile_cfg_get(&pf_info, car_type, pkt_sign, profile_id, profile_cfg);
-    if (rtn)
-    {
-        PLCR_LOG_ERR("failed to call dpp_car_profile_cfg_get(), car_type=%d,profile_id=%d\n", car_type, profile_id);
-        return -EINVAL;
-    }
-
-    return rtn;
-}
-
-/*
-函数功能：配置指定CAR的限速模板：考虑plcr三级CAR能共享接口
-入参：
-    ---pf_dev     : pf设备结构体
-    ---car_type   : plcr CAR层级，一级，二级或三级
-    ---flowid     : 指定CAR的flow编号
-    ---profile_id : 申请到的指定CAR层级的profile资源的id
-返回值：成功返回0，失败返回其它值
-*/
-static int zxdh_plcr_bind_flow_profile(struct zxdh_pf_device *pf_dev,
-                                              E_PLCR_CAR_TYPE car_type,
-                                                     uint32_t flowid,
-                                                     uint16_t profile_id)
-{
-    int                       rtn = 0;
-    struct zxdh_plcr_flow    *plcr_flow;
-    struct xarray            *xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]);
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = pf_dev->slot_id;
-    pf_info.vport = pf_dev->vport;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    /*1. 获取plcr*/
-    plcr_flow = xa_load(xarray_flow, flowid);
-    if (NULL == plcr_flow)
-    {
-        PLCR_LOG_ERR("failed to xa_load an invalid element,car_type=%d,flowid=%d,profile_id=%d\n", car_type, flowid, profile_id);
-        return -EINVAL;
-    }
-
-    /*2. 调用接口，将flow与profile进行绑定*/
-    PLCR_LOG_INFO("dpp_car_queue_cfg_set: pf_info.vport = 0x%x, car_type = %d, flowid = %d, profile_id = %d\n", pf_info.vport, car_type, flowid, profile_id);
-    rtn = dpp_car_queue_cfg_set(&pf_info, (uint32_t)car_type, flowid, DROP_DISABLE, PLCR_ENABLE, profile_id);
-    if (rtn)
-    {
-        PLCR_LOG_ERR("failed to call dpp_car_queue_cfg_set(),car_type=%d,flowid=%d,profile_id=%d\n", car_type, flowid, profile_id);
-        return -EINVAL;
-    }
-    PLCR_LOG_INFO("Bind profile_%d to flow_%d complete\n", profile_id, flowid);
-
-    /*3. 将profile_id更新到plcr中*/
-    plcr_flow->profile_id = profile_id;
-
-    return rtn;
-}
-
-/*
-函数功能：解除flow和profile之间的绑定 & 删除xarray中的元素 & 释放flow指针
-入参：
-    ---pf_dev     : pf设备结构体
-    ---car_type   : plcr CAR层级，一级，二级或三级
-    ---flowid     : 指定CAR的flow编号
-    ---profile_id : 申请到的指定CAR层级的profile资源的id
-返回值：成功返回0，失败返回其它值
-*/
-int zxdh_plcr_unbind_flow_profile(struct zxdh_pf_device *pf_dev,
-                                         E_PLCR_CAR_TYPE car_type,
-                                                uint32_t flowid,
-                                                uint16_t profile_id)
-{
-    int                    rtn = 0;
-    struct zxdh_plcr_flow *plcr_flow;
-    struct xarray         *xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]);
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = pf_dev->slot_id;
-    pf_info.vport = pf_dev->vport;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    /*1. 检查flow是否与profile是否已绑定*/
-    plcr_flow = xa_load(xarray_flow, flowid);
-    if (NULL == plcr_flow)
-    {
-        PLCR_LOG_ERR("xa_load an invalid element, flowid=%d,profile_id=%d\n", flowid, profile_id);
-        return -EINVAL;
-    }
-    if (profile_id != plcr_flow->profile_id)
-    {
-        PLCR_LOG_ERR("xa_load an invalid element, profile_id=%d,plcr_flow->profile_id=%d\n", profile_id, plcr_flow->profile_id);
-        return -EINVAL;
-    }
-
-    /*调用接口，将flow与profile进行解除绑定：配置flow，将其不要指向profile*/
-    PLCR_LOG_INFO("dpp_car_queue_cfg_set: pf_info.vport = 0x%x, car_type = %d, flowid = %d, profile_id = %d\n", pf_info.vport, car_type, flowid, profile_id);
-    rtn = dpp_car_queue_cfg_set(&pf_info, (uint32_t)car_type, flowid, DROP_DISABLE, PLCR_DISABLE, profile_id);
-    if (rtn)
-    {
-        PLCR_LOG_ERR("failed to call dpp_car_queue_cfg_set(),car_type=%d,flowid=%d,profile_id=%d\n", car_type, flowid,profile_id);
-        return rtn;
-    }
-
-    return rtn;
-}
-
-int zxdh_plcr_count_up_profile(struct zxdh_pf_device *pf_dev,
-                                      E_PLCR_CAR_TYPE car_type,
-                                             uint16_t profile_id)
-{
-    int    rtn = 0;
-    struct zxdh_plcr_profile *plcr_profile;
-    struct xarray *xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]);
-
-    PLCR_FUNC_DBG_ENTER();
-
-    plcr_profile = xa_load(xarray_profile, profile_id);
-    if (NULL == plcr_profile)
-    {
-        PLCR_LOG_ERR("failed to load element form xarray_profile, car_type=%d,profile_id=%d\n", car_type, profile_id);
-        return -EINVAL;
-    }
-
-    plcr_profile->ref_cnt++;
-
-    return rtn;
-}
-
-int zxdh_plcr_count_down_profile(struct zxdh_pf_device *pf_dev,
-                                        E_PLCR_CAR_TYPE car_type,
-                                               uint16_t profile_id)
-{
-    int    rtn = 0;
-    struct zxdh_plcr_profile *plcr_profile;
-    struct xarray *xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]);
-
-    PLCR_FUNC_DBG_ENTER();
-
-    plcr_profile = xa_load(xarray_profile, profile_id);
-    if (NULL == plcr_profile)
-    {
-        PLCR_LOG_ERR("failed to load element form xarray_profile, car_type=%d,profile_id=%d\n", car_type, profile_id);
-        return -EINVAL;
-    }
-
-    //不能对计数为0的profile进行减操作
-    if (0 == plcr_profile->ref_cnt)
-    {
-        PLCR_LOG_ERR("failed and plcr_profile->ref_cnt=0\n");
-        return -EINVAL;
-    }
-
-    plcr_profile->ref_cnt--;
-
-    return rtn;
-}
-
-static int zxdh_plcr_get_profile_by_flowid(struct zxdh_pf_device *pf_dev,
-                                                  E_PLCR_CAR_TYPE car_type,
-                                                         uint32_t flowid,
-                                       struct zxdh_plcr_profile **pplcr_profile)
-{
-    int rtn = 0;
-    uint16_t profile_id = 0;
-    struct zxdh_plcr_profile *plcr_profile;
-    struct zxdh_plcr_flow    *plcr_flow;
-    struct xarray *xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_type]);
-    struct xarray *xarray_flow    = &(pf_dev->plcr_table.plcr_flows[car_type]);
-
-    PLCR_FUNC_DBG_ENTER();
-
-    plcr_flow = xa_load(xarray_flow, flowid);
-    if (NULL == plcr_flow)
-    {
-        PLCR_LOG_ERR("failed to load element form xarray_flow, car_type=%d,flowid=%d\n", car_type, flowid);
-        return -EINVAL;
-    }
-    profile_id = plcr_flow->profile_id;
-
-    plcr_profile = xa_load(xarray_profile, profile_id);
-    if (NULL == plcr_profile)
-    {
-        PLCR_LOG_ERR("failed to load element form xarray_profile,car_type=%d,profile_id=%d\n", car_type, profile_id);
-        return -EINVAL;
-    }
-
-    *pplcr_profile = plcr_profile;
-
-    return rtn;
-}
-
-/*******************************下面是新实现的代码*******************************/
-/*
-函数功能：将car之间flowid的映射关系存储起来
-
-入参：
-    ---
-出参：
-    ---
-
-返回值：成功返回0，失败返回其它值
-*/
-int32_t zxdh_plcr_stroe_map(struct zxdh_pf_device *pf_dev,
-                                   E_PLCR_CAR_TYPE car_type,
-                                          uint32_t flowid,
-                                          uint32_t map_flowid)
-{   int32_t rtn = 0;
-
-    struct xarray *xarray_map = &(pf_dev->plcr_table.plcr_maps[car_type]);
-    if((E_PLCR_CAR_A == car_type) || (E_PLCR_CAR_B == car_type))
-    {
-        xa_store(xarray_map, flowid, (void *)(uintptr_t)(FLOWID_2_XARRAY(map_flowid)), GFP_KERNEL);
-    }
-
-    return rtn;
-}
-
-int32_t zxdh_plcr_clear_map(struct zxdh_pf_device *pf_dev,
-                                   E_PLCR_CAR_TYPE car_type,
-                                          uint32_t flowid)
-{   int32_t rtn = 0;
-    void *  xarray_element;
-
-    struct xarray *xarray_map = &(pf_dev->plcr_table.plcr_maps[car_type]);
-    if((E_PLCR_CAR_A == car_type) || (E_PLCR_CAR_B == car_type))
-    {
-        xarray_element = xa_load(xarray_map, flowid);
-        if(NULL != xarray_element)
-        {
-            xa_erase(xarray_map, flowid);
-        }
-    }
-
-    return rtn;
-}
-
-/*
-函数功能：指定前一级的flowid，查询下一级映射的flowid
-
-入参：
-    ---
-出参：
-    ---
-
-返回值：成功返回0，失败返回其它值
-*/
-int32_t zxdh_plcr_get_next_map(struct zxdh_pf_device *pf_dev,
-                                      E_PLCR_CAR_TYPE car_type,
-                                            uint32_t  flowid,
-                                            uint32_t *map_flowid)
-{
-    int32_t rtn = 0;
-    void *  xarray_element;
-
-    struct xarray *xarray_map = &(pf_dev->plcr_table.plcr_maps[car_type]);
-    if((E_PLCR_CAR_A == car_type) || (E_PLCR_CAR_B == car_type))
-    {
-        xarray_element = xa_load(xarray_map, flowid);
-        if(NULL == xarray_element)
-        {
-            rtn = -EINVAL;
-        }
-        else
-        {
-            *map_flowid = XARRAY_2_FLOWID((uint32_t)(uintptr_t)xarray_element);
-        }
-    }
-    else
-    {
-        rtn = -ERANGE;
-    }
-
-    return rtn;
-}
-
-/*
-函数功能：检查指定的car_type所在的三级car flowid链是否全都没有限速，如果是就进行资源清理
-入参：
-    ---pf_dev : 设备结构体
-    ---vport  : 标识vf端口
-场景说明：
-    1. 为什么要引入这个接口？
-       新的方案引入了mode 0，mode 1，mode 2三种模式；
-       vport在三级car上有一条完整的flowid映射链；
-       用户在解除某一级car指定flowid的限速之后，驱动程序需要检查这个链上是不是没有限速了，且car C是不是处于group 0，如果是这样的话就要切换到模式0；
-    2. 切换到模式0的必要性
-       驱动程序中很多限速要需要先判断当前的限速模式；
-       如果当前链上已经没有限速，且car C还是处于group 0，就必须切换回模式0，这也是从模式1和模式2切换回模式0的唯一途径
-    3. 在什么时候需要调用这个接口？
-       用户在解除某一级car指定flowid的限速之后，需要调用这个接口。
-    4.流程：
-      3.1 如果是对car C的group解除限速，说明group是非0的，函数直接返回(废弃，因为有可能是将vf端口从非0group移动到group0)
-      3.2 根据vport得到car B的flowid
-      3.3 根据car B的flowid，查询得到car c的flowid
-      3.4.1 如果car C的flowid处于group 0，就进行模式切换
-      3.4.2 如果car C的flowid不处于group 0，就不进行模式切换，函数返回
-    5.plcr_maps是否需要清除？
-      这个资源不需要清除：只有本函数会用到这个记录，且进行限速配置的时候会重新进行映射，且存储的成员不是动态分配的内存，没有必要清理资源；
-
-返回值：成功返回0，失败返回其它值
-*/
-int zxdh_plcr_check_release_flow_chain(struct zxdh_pf_device *pf_dev, uint16_t vport)
-{
-    int rtn = 0;
-    E_PLCR_CAR_TYPE car_type;
-    uint32_t flag1 = 0;
-    uint32_t flag2 = 0;
-    unsigned long flow_index;
-    uint32_t flowid_car_B;
-    uint32_t flowid_car_C;
-    struct zxdh_plcr_flow *flow;
-    struct xarray *xarray_flow;
-
-    //统计car A和car B上是否有限速
-    for(car_type = E_PLCR_CAR_A, flag1 = 0; car_type < E_PLCR_CAR_C; car_type++)
-    {
-        xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]);
-
-        xa_for_each_range(xarray_flow, flow_index, flow, 0, gaudPlcrCarxFlowIdNum[car_type])
-        {
-            if(vport == flow->vport)
-            {
-                flag1 = 1;
-                break;
-            }
-        }
-        if(1 == flag1)
-        {
-            break;
-        }
-    }
-
-    //检查是否处于group 0
-    if(0 == flag1)
-    {
-        //如果是vf，就要检查group是否为0
-        if (VF_ACTIVE(vport))
-        {
-            flowid_car_B = VQM_VFID(vport) * 2;
-            rtn = zxdh_plcr_get_next_map(pf_dev, E_PLCR_CAR_B, flowid_car_B, &flowid_car_C);
-            PLCR_LOG_INFO("flowid_car_B = 0x%x\n", flowid_car_B);
-            PLCR_LOG_INFO("flowid_car_C = 0x%x\n", flowid_car_C);
-            PLCR_COMM_ASSERT(rtn);
-
-            //4个EP * 8PF * 2收发方向，每个pf占32个car c flowid，前面2个映射到group 0
-            if (0 == (flowid_car_C%(PLCR_CAR_C_FLOWIDS_PER_PF)))
-            {
-                flag2 = 1;
-            }
-        }
-        else
-        {
-            //如果是pf（队列限速），就没有car B和Car C
-            flag2 = 1;
-        }
-
-    }
-
-    if(0 != flag2)
-    {
-        //执行清理操作
-
-        //1.清理级间映射
-        // for (index=0; index<cnt; index++)
-        // {
-        //     rtn = zxdh_plcr_clear_map(pf_dev, flow_car_type[index], flow_id[index]);
-        // }
-
-        //2.切换到mode 0模式
-        zxdh_plcr_set_mode(pf_dev, vport, E_RATE_LIMIT_MODE0);
-    }
-
-    return rtn;
-}
-
-static int zxdh_plcr_create_rate_limit(struct zxdh_pf_device *pf_dev,
-                                        E_RATE_LIMIT_PKT_BYTE is_pkt_mode,
-                                              E_PLCR_CAR_TYPE car_type,
-                                                     uint16_t vport,
-                                                     uint32_t flowid,
-                                                     uint32_t max_rate,
-                                                     uint32_t min_rate)
-{
-    int rtn = 0;
-    uint16_t profile_id = 0;
-    DPP_STAT_CAR_PROFILE_CFG_T profile_cfg;
-    struct zxdh_plcr_flow *plcr_flow = NULL;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    /*1. 对于一个先前还未限速的队列，如果限速值是0，这个限速配置操作无意义，就直接结束*/
-    if ((0 == max_rate) && (0 == min_rate))
-    {
-        PLCR_LOG_ERR("failed and invalid max_rate=%d on flowid=%d\n", max_rate, flowid);
-        PLCR_COMM_ASSERT(PLCR_CREATE_RATE_LIMIT_INVALID_OPERATION_ERR);
-    }
-
-    /*2. 申请flow结构体，并存储到xarray*/
-    rtn = zxdh_plcr_req_flow(pf_dev, car_type, flowid, &plcr_flow);
-    PLCR_COMM_ASSERT(rtn);
-
-    /*3. 更新flow信息*/
-    zxdh_plcr_update_flow(plcr_flow, vport, max_rate, min_rate);
-
-    /*3. 根据限速值，生成限速模板配置参数*/
-    rtn = zxdh_plcr_gen_profile(pf_dev, is_pkt_mode, car_type, max_rate, min_rate, &profile_cfg);
-    if (rtn)
-    {
-        PLCR_LOG_ERR("failed to call zxdh_plcr_gen_profile()\n");
-        goto err3;
-    }
-
-    /*4. 查询是否有共享模板：没有共享限速模板，就要申请一个*/
-    rtn = zxdh_plcr_match_profile(pf_dev, car_type, &profile_cfg, &profile_id);
-    if (rtn)
-    {
-        /*4.1 申请新的限速模板*/
-        rtn = zxdh_plcr_req_profile(pf_dev, car_type, &profile_id);
-        if (rtn)
-        {
-            PLCR_LOG_ERR("failed to call zxdh_plcr_req_profile()\n");
-            goto err3;
-        }
-
-        /*4.2 将profile_id更新到限速模板参数中去*/
-        zxdh_plcr_update_profile(&profile_cfg, profile_id);
-
-        /*4.3 将限速模板参数，配置到寄存器中去*/
-        rtn = zxdh_plcr_cfg_profile(pf_dev, car_type, &profile_cfg);
-        if (rtn)
-        {
-            PLCR_LOG_ERR("failed to call zxdh_plcr_cfg_profile()\n");
-            goto err2;
-        }
-
-        /*4.4 将限速模板配置参数，保存到zxdh_plcr_profile结构体*/
-        rtn = zxdh_plcr_store_profile(pf_dev, car_type, max_rate, min_rate, &profile_cfg);
-        if (rtn)
-        {
-            PLCR_LOG_ERR("failed to call zxdh_plcr_store_profile()\n");
-            goto err2;
-        }
-    }
-
-    /*5. 关联flow与profile*/
-    rtn = zxdh_plcr_bind_flow_profile(pf_dev, car_type, flowid, profile_id);
-    if (rtn)
-    {
-        PLCR_LOG_ERR("failed to call zxdh_plcr_bind_flow_profile()\n");
-        goto err2;
-    }
-
-    /*6. 新模板使用计数+1*/
-    rtn = zxdh_plcr_count_up_profile(pf_dev, car_type, profile_id);
-    if (rtn)
-    {
-        PLCR_LOG_ERR("failed to call zxdh_plcr_count_up_profile()\n");
-        goto err1;
-    }
-
-    return rtn;
-
-    /*7. 错误处理*/
-err1:
-    zxdh_plcr_unbind_flow_profile(pf_dev, car_type, flowid, profile_id);
-err2:
-    zxdh_plcr_release_profile(pf_dev, car_type, profile_id);
-err3:
-    zxdh_plcr_release_flow(pf_dev, car_type, flowid);
-
-    return rtn;
-}
-
-static int zxdh_plcr_modify_rate_limit(struct zxdh_pf_device *pf_dev,
-                                        E_RATE_LIMIT_PKT_BYTE is_pkt_mode,
-                                              E_PLCR_CAR_TYPE car_type,
-                                                     uint32_t flowid,
-                                                     uint32_t max_rate,
-                                                     uint32_t min_rate)
-{
-    int rtn                                 = 0;
-    uint16_t profile_id                     = 0;
-    DPP_STAT_CAR_PROFILE_CFG_T profile_cfg;
-    struct xarray            *xarray_flowid = &(pf_dev->plcr_table.plcr_flows[car_type]);
-    struct zxdh_plcr_flow    *plcr_flow = xa_load(xarray_flowid, flowid);
-    struct zxdh_plcr_profile *profile_old   = NULL;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    /*1. 如果二次修改的限速值和原来的一样，这个配置操作无意义，直接结束*/
-    if (E_PLCR_CAR_A == car_type)
-    {
-        if (plcr_flow->max_rate == max_rate)
-        {
-            PLCR_LOG_ERR("failed and invalid max_rate=%d on flowid=%d\n", max_rate, flowid);
-            PLCR_COMM_ASSERT(PLCR_MODIFY_RATE_LIMIT_INVALID_OPERATION_ERR);
-        }
-    }
-    else if((E_PLCR_CAR_B == car_type) || (E_PLCR_CAR_C == car_type))
-    {
-        if ((plcr_flow->max_rate == max_rate) && (plcr_flow->min_rate == min_rate))
-        {
-            PLCR_LOG_ERR("failed and invalid max_rate=%d, min_rate=%d on flowid=%d\n", max_rate, min_rate, flowid);
-            PLCR_COMM_ASSERT(PLCR_MODIFY_RATE_LIMIT_INVALID_OPERATION_ERR);
-        }
-    }
-
-    /*2. 根据新的限速值，生成限速模板参数*/
-    rtn = zxdh_plcr_gen_profile(pf_dev, is_pkt_mode, car_type, max_rate, min_rate, &profile_cfg);
-    PLCR_COMM_ASSERT(rtn);
-
-    /*3. 获取原来关联的限速模板*/
-    rtn = zxdh_plcr_get_profile_by_flowid(pf_dev, car_type, flowid, &profile_old);
-    PLCR_COMM_ASSERT(rtn);
-
-    /*3. 先查询有没有相同速率的限速模板*/
-    rtn = zxdh_plcr_match_profile(pf_dev, car_type, &profile_cfg, &profile_id);
-    if (rtn)
-    {
-        /*3.1 没有找到能共享的限速模板*/
-
-        /*3.2 原来的模板不是共享模板：直接修改限速模板的限速值*/
-        if (1 == profile_old->ref_cnt)
-        {
-            /*3.2.1 将profile_id更新到限速模板参数中去*/
-            zxdh_plcr_update_profile(&profile_cfg, profile_old->profile_id);
-
-            /*3.2.2 将限速模板的参数，配置到寄存器中去*/
-            rtn = zxdh_plcr_cfg_profile(pf_dev, car_type, &profile_cfg);
-            PLCR_COMM_ASSERT(rtn);
-
-            /*3.2.3 将限速模板配置参数，保存到zxdh_plcr_profile结构体*/
-            rtn = zxdh_plcr_store_profile(pf_dev, car_type, max_rate, min_rate, &profile_cfg);
-            PLCR_COMM_ASSERT(rtn);
-
-            /* 更新flow中记录的用户原始限速值，todo：是否使用bind函数，要考虑后期在哪里加锁*/
-            zxdh_plcr_update_flow(plcr_flow, plcr_flow->vport, max_rate, min_rate);
-
-            /*这种情况只修改限速模板的寄存器，flowid先前已经与profile绑定了*/
-            return rtn;
-        }
-
-        /*3.3 原来的限速模板是共享模板，所以要申请新的限速模板*/
-        rtn = zxdh_plcr_req_profile(pf_dev, car_type, &profile_id);
-        PLCR_COMM_ASSERT(rtn);
-
-        /*3.4 将profile_id更新到限速模板参数中去*/
-        zxdh_plcr_update_profile(&profile_cfg, profile_id);
-
-        /*3.5 将限速模板的参数，配置到寄存器中去*/
-        rtn = zxdh_plcr_cfg_profile(pf_dev, car_type, &profile_cfg);
-        if (rtn)
-        {
-            PLCR_LOG_ERR("failed to call zxdh_plcr_cfg_profile()\n");
-            goto err4;
-        }
-
-        /*3.6 将限速模板配置参数，保存到zxdh_plcr_profile结构体*/
-        rtn = zxdh_plcr_store_profile(pf_dev, car_type, max_rate, min_rate, &profile_cfg);
-        if (rtn)
-        {
-            PLCR_LOG_ERR("failed to call zxdh_plcr_store_profile()\n");
-            goto err4;
-        }
-
-        /*3.7 接下来的绑定流程，和下面是共享的*/
-    }
-    /*4. 查询到共享的限速模板：直接进行绑定即可*/
-    rtn = zxdh_plcr_bind_flow_profile(pf_dev, car_type, flowid, profile_id);
-    if (rtn)
-    {
-        PLCR_LOG_ERR("failed to call zxdh_plcr_bind_flow_profile()\n");
-        goto err4;
-    }
-
-    /*5. 更新flow中记录的用户原始限速值*/
-    zxdh_plcr_update_flow(plcr_flow, plcr_flow->vport, max_rate, min_rate);
-
-    /*6. 新模板使用计数+1*/
-    rtn = zxdh_plcr_count_up_profile(pf_dev, car_type, profile_id);
-    if (rtn)
-    {
-        PLCR_LOG_ERR("failed to call zxdh_plcr_count_up_profile()\n");
-        goto err4;
-    }
-
-    /*7. 旧的计数模板-1*/
-    rtn = zxdh_plcr_count_down_profile(pf_dev, car_type, profile_old->profile_id);
-    if (rtn)
-    {
-        PLCR_LOG_ERR("failed to call zxdh_plcr_count_up_profile()\n");
-        goto err4;
-    }
-
-    zxdh_plcr_release_profile(pf_dev, car_type, profile_old->profile_id);
-
-    return rtn;
-
-err4:
-    zxdh_plcr_release_profile(pf_dev, car_type, profile_id);
-    return rtn;
-}
-
-int zxdh_plcr_remove_rate_limit(struct zxdh_pf_device *pf_dev,
-                                       E_PLCR_CAR_TYPE car_type,
-                                              uint32_t flowid)
-{
-    int rtn = 0;
-    struct zxdh_plcr_profile *profile_old = NULL;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    PLCR_LOG_INFO("car_type=%d,flowid=%d\n",car_type,flowid);
-
-    /* 获取原来关联的限速模板*/
-    rtn = zxdh_plcr_get_profile_by_flowid(pf_dev, car_type, flowid, &profile_old);
-    PLCR_COMM_ASSERT(rtn);
-
-    /*解除绑定*/
-    rtn = zxdh_plcr_unbind_flow_profile(pf_dev, car_type, flowid, profile_old->profile_id);
-    //PLCR_COMM_ASSERT(rtn);
-
-    /*限速模板引用计数 -1*/
-    rtn = zxdh_plcr_count_down_profile(pf_dev, car_type, profile_old->profile_id);
-    //PLCR_COMM_ASSERT(rtn);
-
-    /*释放限速模板：如果引用计数为0，归还模板资源 & 删除xarray元素 & 释放profile指针*/
-    rtn = zxdh_plcr_release_profile(pf_dev, car_type, profile_old->profile_id);
-    //PLCR_COMM_ASSERT(rtn);
-
-    /*释放掉flow*/
-    rtn = zxdh_plcr_release_flow(pf_dev, car_type, flowid);
-    //PLCR_COMM_ASSERT(rtn);
-
-    return rtn;
-}
-
-void zxdh_plcr_count_profiles(struct zxdh_pf_device *pf_dev)
-{
-    struct zxdh_plcr_profile *profile;
-    unsigned long index;
-    uint32_t count = 0;
-    E_PLCR_CAR_TYPE car_type;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    for (car_type = E_PLCR_CAR_A; car_type < E_PLCR_CAR_NUM; car_type ++)
-    {
-        count = 0;
-        xa_for_each_range(&(pf_dev->plcr_table.plcr_profiles[car_type]), index, profile, 0, gaudPlcrCarxProfileNum[car_type])
-        {
-            count++;
-        }
-        PLCR_LOG_INFO("car_type = %d, profiles_num = %d\n", car_type, count);
-    }
-}
-
-int zxdh_plcr_set_rate_limit(struct zxdh_pf_device *pf_dev,
-                              E_RATE_LIMIT_PKT_BYTE is_pkt_mode,
-                                    E_PLCR_CAR_TYPE car_type,
-                                           uint16_t vport,
-                                           uint32_t flowid,
-                                           uint32_t max_rate,
-                                           uint32_t min_rate)
-{
-    int rtn = 0;
-    struct xarray *xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]);
-    struct zxdh_plcr_flow *flow = NULL;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    /*1. 判断该队列先前是否已经配置过限速值*/
-    flow = xa_load(xarray_flow, flowid);
-    if (NULL == flow)
-    {
-        /*1.1 初次配置限速值*/
-        rtn = zxdh_plcr_create_rate_limit(pf_dev, is_pkt_mode, car_type, vport, flowid, max_rate, min_rate);
-        PLCR_COMM_ASSERT(rtn);
-    }
-    else if ((max_rate != 0) || (min_rate != 0))
-    {
-        /*1.2 修改限速值*/
-        rtn = zxdh_plcr_modify_rate_limit(pf_dev, is_pkt_mode, car_type, flowid, max_rate, min_rate);
-        PLCR_COMM_ASSERT(rtn);
-    }
-    else
-    {
-        /*1.3.1 解除限速：即，第二次配置，且max_rate=0，表示用户要解除限速*/
-        rtn = zxdh_plcr_remove_rate_limit(pf_dev, car_type, flowid);
-        PLCR_COMM_ASSERT(rtn);
-
-        zxdh_plcr_check_release_flow_chain(pf_dev, vport);
-
-        //不是错误码，用来标记是进行了解除限速的操作
-        rtn = PLCR_REMOVE_RATE_LIMIT;
-    }
-
-    zxdh_plcr_count_profiles(pf_dev);
-
-    return rtn;
-}
-
-E_RATE_LIMIT_MODE g_plcr_mode[PF_VQM_VFID_OFFSET + 32] = {0xff};
-int zxdh_plcr_set_mode(struct zxdh_pf_device *pf_dev, uint16_t vport, E_RATE_LIMIT_MODE mode)
-{
-    uint16_t vfid = VQM_VFID(vport);
-#if 1
-    g_plcr_mode[vfid] = mode;
-#else
-    //todo：设置vf端口当前的模式
-#endif
-    PLCR_LOG_INFO("zxdh_plcr_set_mode():g_plcr_mode[%d]=%d\n", vfid, g_plcr_mode[vfid]);
-
-    return 0;
-}
-
-int zxdh_plcr_get_mode(struct zxdh_pf_device *pf_dev, uint16_t vport, E_RATE_LIMIT_MODE *mode)
-{
-    uint16_t vfid = VQM_VFID(vport);
-
-#if 1
-    *mode = g_plcr_mode[vfid];
-#else
-    //todo：获取vf端口当前的模式
-#endif
-    PLCR_LOG_INFO("zxdh_plcr_get_mode():g_plcr_mode[%d]=%d\n", vfid, g_plcr_mode[vfid]);
-
-    return 0;
-}
-
-int zxdh_plcr_show_rate_limit_paras(zxdh_plcr_rate_limit_paras *rate_limit_paras)
-{
-    PLCR_LOG_INFO("rate_limit_paras->req_type   = 0x%x\n", rate_limit_paras->req_type);
-    PLCR_LOG_INFO("rate_limit_paras->direction  = 0x%x\n", rate_limit_paras->direction);
-    PLCR_LOG_INFO("rate_limit_paras->mode       = 0x%x\n", rate_limit_paras->mode);
-    PLCR_LOG_INFO("rate_limit_paras->max_rate   = 0x%x\n", rate_limit_paras->max_rate);
-    PLCR_LOG_INFO("rate_limit_paras->min_rate   = 0x%x\n", rate_limit_paras->min_rate);
-    PLCR_LOG_INFO("rate_limit_paras->queue_id   = 0x%x\n", rate_limit_paras->queue_id);
-    PLCR_LOG_INFO("rate_limit_paras->vf_idx     = 0x%x\n", rate_limit_paras->vf_idx);
-    PLCR_LOG_INFO("rate_limit_paras->vfid       = 0x%x\n", rate_limit_paras->vfid);
-    PLCR_LOG_INFO("rate_limit_paras->vport      = 0x%x\n", rate_limit_paras->vport);
-    PLCR_LOG_INFO("rate_limit_paras->group_id   = 0x%x\n", rate_limit_paras->group_id);
-
-    return 0;
-}
-
-int zxdh_plcr_check_req_type(struct zxdh_pf_device *pf_dev, E_RATE_LIMIT_MODE mode, zxdh_plcr_rate_limit_paras *rate_limit_paras, E_RATE_LIMIT_REQ_TYPE *req_type)
-{
-    PLCR_FUNC_DBG_ENTER();
-
-    //队列字节限速
-    if ((rate_limit_paras->req_type  == E_RATE_LIMIT_REQ_QUEUE_BYTE) &&
-        (rate_limit_paras->mode      == E_RATE_LIMIT_BYTE) &&
-        ((rate_limit_paras->min_rate != PLCR_INVALID_PARAM) || (rate_limit_paras->max_rate != PLCR_INVALID_PARAM)) &&
-        (rate_limit_paras->direction == E_RATE_LIMIT_TX) &&
-        (rate_limit_paras->vf_idx    == PLCR_INVALID_PARAM) &&
-        (rate_limit_paras->group_id  == PLCR_INVALID_PARAM) &&
-        (rate_limit_paras->queue_id  <  PLCR_MAX_QUEUE_PAIRS))
-    {
-        *req_type =  E_RATE_LIMIT_REQ_QUEUE_BYTE;
-
-        //mode2模式下不支持队列字节限速
-        if(E_RATE_LIMIT_MODE2 == mode)
-        {
-            PLCR_LOG_ERR("E_RATE_LIMIT_REQ_QUEUE_BYTE is not supported under E_RATE_LIMIT_MODE2\n");
-            return PLCR_GET_REQ_TYPE_INVALID_ERR;
-        }
-
-        //端口组默认为0
-        rate_limit_paras->group_id = 0;
-
-        return 0;
-    }
-    //vf端口字节限速
-    else if ((rate_limit_paras->req_type  == E_RATE_LIMIT_REQ_VF_BYTE) &&
-             (rate_limit_paras->mode      == E_RATE_LIMIT_BYTE) &&
-            ((rate_limit_paras->min_rate  != PLCR_INVALID_PARAM) || (rate_limit_paras->max_rate != PLCR_INVALID_PARAM)) &&
-            ((rate_limit_paras->direction == E_RATE_LIMIT_RX) || (rate_limit_paras->direction == E_RATE_LIMIT_TX)) &&
-             (rate_limit_paras->group_id  == PLCR_INVALID_PARAM) &&
-             (rate_limit_paras->vf_idx    != PLCR_INVALID_PARAM))
-    {
-
-        //端口组默认为0：
-        rate_limit_paras->group_id = 0;
-
-        *req_type =  E_RATE_LIMIT_REQ_VF_BYTE;
-        return 0;
-    }
-    //vf端口包限速
-    else if ((rate_limit_paras->req_type   == E_RATE_LIMIT_REQ_VF_PKT) &&
-             (rate_limit_paras->mode       == E_RATE_LIMIT_PACKET) &&
-             ((rate_limit_paras->min_rate  != PLCR_INVALID_PARAM) || (rate_limit_paras->max_rate != PLCR_INVALID_PARAM)) &&
-             ((rate_limit_paras->direction == E_RATE_LIMIT_RX) || (rate_limit_paras->direction == E_RATE_LIMIT_TX)) &&
-             (rate_limit_paras->group_id   == PLCR_INVALID_PARAM) &&
-             (rate_limit_paras->vf_idx     != PLCR_INVALID_PARAM))
-    {
-        *req_type =  E_RATE_LIMIT_REQ_VF_PKT;
-        //mode1模式下不支持端口包限速
-        if(E_RATE_LIMIT_MODE1 == mode)
-        {
-            PLCR_LOG_ERR("E_RATE_LIMIT_REQ_VF_PKT is not supported under E_RATE_LIMIT_MODE1\n");
-            return PLCR_GET_REQ_TYPE_INVALID_ERR;
-        }
-
-        //端口组默认为0
-        rate_limit_paras->group_id = 0;
-
-        return 0;
-    }
-    //端口组字节限速
-    else if ((rate_limit_paras->req_type   == E_RATE_LIMIT_REQ_VF_GROUP_BYTE) &&
-             (rate_limit_paras->mode       == E_RATE_LIMIT_BYTE) &&
-             ((rate_limit_paras->min_rate  != PLCR_INVALID_PARAM) || (rate_limit_paras->max_rate != PLCR_INVALID_PARAM)) &&
-             ((rate_limit_paras->direction == E_RATE_LIMIT_RX) || (rate_limit_paras->direction == E_RATE_LIMIT_TX)) &&
-              (rate_limit_paras->vf_idx    == PLCR_INVALID_PARAM) && //不需要flowid级间映射，不需要vf_idx，不需要Vfid
-              (rate_limit_paras->group_id  != PLCR_INVALID_PARAM))
-    {
-        *req_type =  E_RATE_LIMIT_REQ_VF_GROUP_BYTE;
-        return 0;
-    }
-    //移动vf端口组
-    else if ((rate_limit_paras->req_type   == E_RATE_LIMIT_REQ_MOVE_VF_GROUP) &&
-             (rate_limit_paras->mode       == PLCR_INVALID_PARAM) &&
-             ((rate_limit_paras->min_rate  == PLCR_INVALID_PARAM) && (rate_limit_paras->max_rate == PLCR_INVALID_PARAM)) &&
-             ((rate_limit_paras->direction == E_RATE_LIMIT_RX) || (rate_limit_paras->direction == E_RATE_LIMIT_TX)) &&
-             (rate_limit_paras->vf_idx     != PLCR_INVALID_PARAM) &&
-             (rate_limit_paras->group_id   != PLCR_INVALID_PARAM))
-    {
-        *req_type =  E_RATE_LIMIT_REQ_MOVE_VF_GROUP;
-        return 0;
-    }
-    else
-    {
-        //将入参中的请求信息打印出来
-        zxdh_plcr_show_rate_limit_paras(rate_limit_paras);
-
-        return PLCR_GET_REQ_TYPE_INVALID_ERR;
-    }
-}
-
-int32_t zxdh_pf_get_vf_queue_info(struct zxdh_pf_device *pf_dev, int32_t vf_idx, int32_t *phy_queue_num, int32_t *phy_rx_queue, int32_t *phy_tx_queue)
-{
-    int32_t rtn = 0;
-    int32_t i;
-    union zxdh_msg msg = {0};
-    int32_t queue_pair_index;
-    int32_t queue_num;
-    int32_t queue_pair = 0;
-    struct dh_core_dev *dh_dev = container_of((void*)pf_dev, struct dh_core_dev, priv);
-    struct zxdh_en_device *en_dev;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    en_dev = pf_dev_get_edev(pf_dev);
-    if (IS_ERR(en_dev))
-        return PTR_ERR(en_dev);
-
-    msg.payload.hdr_vf.op_code = ZXDH_PF_GET_VF_QUEUE_INFO;
-    msg.payload.hdr_vf.dst_pcie_id = FIND_VF_PCIE_ID(pf_dev->pcie_id, vf_idx);
-
-    for(queue_pair_index = 0; queue_pair_index < PLCR_MAX_QUEUE_PAIRS;)
-    {
-        msg.payload.plcr_pf_get_vf_queue_info_msg.vir_queue_start = queue_pair_index;
-        msg.payload.plcr_pf_get_vf_queue_info_msg.vir_queue_num = 16;
-
-        //get rx&tx phy queue
-        PLCR_LOG_INFO("msg.payload.plcr_pf_get_vf_queue_info_msg.vir_queue_start = 0x%x\n", msg.payload.plcr_pf_get_vf_queue_info_msg.vir_queue_start);
-        PLCR_LOG_INFO("msg.payload.plcr_pf_get_vf_queue_info_msg.vir_queue_num   = 0x%x\n", msg.payload.plcr_pf_get_vf_queue_info_msg.vir_queue_num);
-        rtn = zxdh_pf_msg_send_cmd(dh_dev, MODULE_PF_BAR_MSG_TO_VF, &msg, &msg, true);
-        PLCR_COMM_ASSERT(rtn);
-
-        queue_num = msg.reps.plcr_pf_get_vf_queue_info_rsp.phy_queue_num;
-        for(i = 0; i < queue_num; i++)
-        {
-            phy_rx_queue[queue_pair_index*16 + i] = msg.reps.plcr_pf_get_vf_queue_info_rsp.phy_rxq[i];
-            phy_tx_queue[queue_pair_index*16 + i] = msg.reps.plcr_pf_get_vf_queue_info_rsp.phy_txq[i];
-
-            PLCR_LOG_INFO("rxq: 0x%x  -  0x%x\n", queue_pair_index*16 + i, phy_rx_queue[queue_pair_index*16 + i]);
-            PLCR_LOG_INFO("txq: 0x%x  -  0x%x\n", queue_pair_index*16 + i, phy_tx_queue[queue_pair_index*16 + i]);
-        }
-
-        queue_pair += queue_num;
-
-        if(queue_num < 16)
-        {
-            *phy_queue_num = queue_pair;
-
-            PLCR_LOG_INFO("phy_queue_num = 0x%x\n", *phy_queue_num);
-
-            return rtn;
-        }
-        else
-        {
-            queue_pair_index += 16;
-        }
-    }
-
-    return rtn;
-}
-
-int zxdh_plcr_map_flowid(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint32_t flowid, uint32_t map_flowid)
-{
-    int rtn = 0;
-    uint32_t map_sp = 0;  //priority
-    union zxdh_msg msg = {0};
-    DPP_PF_INFO_T pf_info = {0};
-    struct dh_core_dev *dh_dev = container_of((void*)pf_dev, struct dh_core_dev, priv);
-
-    PLCR_FUNC_DBG_ENTER();
-    PLCR_LOG_INFO("car_type = 0x%x, flowid = 0x%x, map_flowid = 0x%x\n", car_type, flowid, map_flowid);
-
-    if (dh_dev->coredev_type == DH_COREDEV_PF)
-    {
-        //前面的流程会判断是否需要进行映射，不会出现vf端口原来是非0group，现在会被group 0覆盖的情况
-        PLCR_LOG_INFO("flowid=0x%x, map_flowid=0x%x\n", flowid, map_flowid);
-        pf_info.slot = pf_dev->slot_id;
-        pf_info.vport = pf_dev->vport;
-        PLCR_LOG_INFO("dpp_car_queue_map_set: pf_info.vport = 0x%x, car_type = %d, flowid = %d, map_flowid = %d\n", pf_info.vport, car_type, flowid, map_flowid);
-        rtn = dpp_car_queue_map_set(&pf_info, car_type, flowid, map_flowid, map_sp);
-        PLCR_COMM_ASSERT(rtn);
-
-        rtn = zxdh_plcr_stroe_map(pf_dev, car_type, flowid, map_flowid);
-    }
-    else
-    {
-        msg.payload.hdr.op_code = ZXDH_MAP_PLCR_FLOWID;
-        msg.payload.hdr.vport   = pf_dev->vport;
-        msg.payload.hdr.pcie_id = pf_dev->pcie_id;
-        msg.payload.hdr.vf_id   = pf_dev->pcie_id & (0xff);
-
-        msg.payload.plcr_flowid_map_msg.car_type   = car_type;
-        msg.payload.plcr_flowid_map_msg.flowid     = flowid;
-        msg.payload.plcr_flowid_map_msg.map_flowid = map_flowid;
-        msg.payload.plcr_flowid_map_msg.sp         = map_sp;
-        PLCR_LOG_INFO("flowid=0x%x, map_flowid=0x%x\n", flowid, map_flowid);
-
-        rtn = zxdh_pf_msg_send_cmd(dh_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true);
-        PLCR_COMM_ASSERT(rtn);
-    }
-
-    return rtn;
-}
-
-int zxdh_plcr_mode_init(struct zxdh_pf_device *pf_dev)
-{
-    int32_t rtn = 0;
-    union zxdh_msg msg = {0};
-    struct dh_core_dev *dh_dev = container_of((void*)pf_dev, struct dh_core_dev, priv);
-    DPP_PF_INFO_T pf_info = {0};
-
-    pf_info.slot = pf_dev->slot_id;
-    pf_info.vport = pf_dev->vport;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    if (dh_dev->coredev_type == DH_COREDEV_PF)
-    {
-        //set mode0
-        rtn =  zxdh_plcr_set_mode(pf_dev, pf_dev->vport, E_RATE_LIMIT_MODE0);
-        PLCR_COMM_ASSERT(rtn);
-    }
-    else if (dh_dev->coredev_type == DH_COREDEV_VF)
-    {
-        msg.payload.hdr.op_code = ZXDH_PLCR_MODE_INIT;
-        msg.payload.hdr.vport   = pf_dev->vport;
-        msg.payload.hdr.pcie_id = pf_dev->pcie_id;
-        msg.payload.hdr.vf_id   = pf_dev->pcie_id & (0xff);
-
-        rtn = zxdh_pf_msg_send_cmd(dh_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true);
-        PLCR_COMM_ASSERT(rtn);
-    }
-
-    return rtn;
-}
-
-int32_t zxdh_plcr_init(struct zxdh_en_priv *en_priv)
-{
-    int32_t rtn = 0;
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct dh_core_dev    *dh_dev = en_dev->parent->parent;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    if (dh_dev->coredev_type == DH_COREDEV_PF)
-    {
-        xa_init(&pf_dev->plcr_table.plcr_profiles[E_PLCR_CAR_A]);
-        xa_init(&pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_A]);
-        xa_init(&pf_dev->plcr_table.plcr_maps[E_PLCR_CAR_A]);
-
-        xa_init(&pf_dev->plcr_table.plcr_profiles[E_PLCR_CAR_B]);
-        xa_init(&pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_B]);
-        xa_init(&pf_dev->plcr_table.plcr_maps[E_PLCR_CAR_B]);
-
-        xa_init(&pf_dev->plcr_table.plcr_profiles[E_PLCR_CAR_C]);
-        xa_init(&pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_C]);
-
-        pf_dev->plcr_table.burst_size = 0;
-    }
-
-    //vf需要设置到mode0模式
-    rtn = zxdh_plcr_mode_init(pf_dev);
-    PLCR_COMM_ASSERT(rtn);
-
-    return rtn;
-}
-EXPORT_SYMBOL(zxdh_plcr_init);
-
-/*释放PF/VF*/
-int32_t zxdh_plcr_uninit(struct zxdh_en_priv *en_priv)
-{
-    int rtn = 0;
-    union zxdh_msg msg = {0};
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct dh_core_dev    *dh_dev = en_dev->parent->parent;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dh_dev);
-
-    unsigned long             flow_id;
-    E_PLCR_CAR_TYPE           car_index;
-    struct xarray            *xarray_flow;
-    struct xarray            *xarray_profile;
-    struct zxdh_plcr_flow    *flow = NULL;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    if (dh_dev->coredev_type == DH_COREDEV_PF)
-    {
-        for(car_index = E_PLCR_CAR_A; car_index <= E_PLCR_CAR_C; car_index ++)
-        {
-            xarray_flow    = &(pf_dev->plcr_table.plcr_flows[car_index]);
-            xarray_profile = &(pf_dev->plcr_table.plcr_profiles[car_index]);
-            xa_for_each_range(xarray_flow, flow_id, flow, 0, gaudPlcrCarxFlowIdNum[car_index])
-            {
-                zxdh_plcr_remove_rate_limit(pf_dev, car_index, flow_id);
-
-                //clear all vport mappings between car B and car C.
-                if(E_PLCR_CAR_B == car_index)
-                {
-                    zxdh_plcr_clear_map(pf_dev, car_index, flow_id);
-                }
-            }
-            xa_destroy(xarray_flow);
-            xa_destroy(xarray_profile);
-        }
-    }
-    else if (dh_dev->coredev_type == DH_COREDEV_VF)
-    {
-        //解除一二级flowid与profile之间的绑定关系，并释放profile
-        msg.payload.hdr.op_code = ZXDH_PLCR_UNINIT;
-        msg.payload.hdr.vport = pf_dev->vport;
-        msg.payload.hdr.pcie_id = pf_dev->pcie_id;
-        msg.payload.hdr.vf_id = pf_dev->pcie_id & (0xff);
-
-        rtn = zxdh_pf_msg_send_cmd(dh_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true);
-        PLCR_COMM_ASSERT(rtn);
-    }
-    return rtn;
-}
-EXPORT_SYMBOL(zxdh_plcr_uninit);
-
-
-
-/*******************************下面是新实现的代码*******************************/
-/*
-函数功能：获取car A的flowid
-入参：
-    ---
-    ---
-场景：
-    ---1. 如果处于mode0模式，用户请求队列字节限速，则car A的flowid就是队列
-          这种场景下，pf和vf调用各自的钩子函数，所以通过en_dev直接获取队列信息
-    ---2. 如果处于mode0模式，用户请求非队列字节限速，则car A的flowid就是vf端口
-    ---3. 如果处于mode1模式，则不管用户是什么请求，没有必要获取car A的flowid，因为场景1已经进行了映射
-    ---4. 如果处于mode2模式，则不管用户是什么请求，没有必要获取car A的flowid，因为场景2已经进行了映射
-返回值：成功返回0，失败返回其它值
-*/
-int zxdh_plcr_get_car_a_flowid(struct zxdh_pf_device *pf_dev, E_RATE_LIMIT_MODE mode, zxdh_plcr_rate_limit_paras *rate_limit_paras, zxdh_plcr_flowids *flowids)
-{
-    int rtn = 0;
-    uint32_t queue_pair_index;
-    struct zxdh_en_device *en_dev;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    PLCR_LOG_INFO("mode = %d, rate_limit_paras->req_type = %d\n", mode, rate_limit_paras->req_type);
-
-    en_dev = pf_dev_get_edev(pf_dev);
-    if (IS_ERR(en_dev))
-        return PTR_ERR(en_dev);
-
-    if (PLCR_MAX_QUEUE_PAIRS < (en_dev->curr_queue_pairs))
-    {
-        PLCR_COMM_ASSERT(PLCR_DEV_ALL_QID_2_FLOWID_QUEUE_PAIRS_OVERFLOW);
-    }
-
-    PLCR_LOG_INFO("rate_limit_paras->req_type = 0x%x\n", rate_limit_paras->req_type);
-
-    if (E_RATE_LIMIT_REQ_VF_GROUP_BYTE == rate_limit_paras->req_type)
-    {
-        PLCR_LOG_INFO("E_RATE_LIMIT_REQ_VF_GROUP_BYTE does not need car A flowid!\n");
-        return 0;
-    }
-    else if ((((E_RATE_LIMIT_MODE0 == mode)) || ((E_RATE_LIMIT_MODE1 == mode))) && (E_RATE_LIMIT_REQ_QUEUE_BYTE == rate_limit_paras->req_type))
-    {
-        //队列字节限速调用的是pf和vf各自的钩子，所以这里直接使用en_dev->curr_queue_pairs
-        for (queue_pair_index=0; queue_pair_index < en_dev->curr_queue_pairs; queue_pair_index++)
-        {
-            //rx
-            flowids->flowids_A[0][queue_pair_index] = en_dev->rq[queue_pair_index].vq->phy_index;
-
-            //tx
-            flowids->flowids_A[1][queue_pair_index] = en_dev->sq[queue_pair_index].vq->phy_index;
-
-            PLCR_LOG_INFO("flowids->flowids_A[0][%d] = 0x%x\n", queue_pair_index, flowids->flowids_A[0][queue_pair_index]);
-            PLCR_LOG_INFO("flowids->flowids_A[1][%d] = 0x%x\n", queue_pair_index, flowids->flowids_A[1][queue_pair_index]);
-        }
-        flowids->queue_pairs = en_dev->curr_queue_pairs;
-
-        PLCR_LOG_INFO("flowids->queue_pairs = 0x%x\n", flowids->queue_pairs);
-    }
-    else if (((E_RATE_LIMIT_MODE0 == mode) && (E_RATE_LIMIT_REQ_QUEUE_BYTE != rate_limit_paras->req_type)) ||
-             ((E_RATE_LIMIT_MODE2 == mode) && (E_RATE_LIMIT_REQ_VF_PKT == rate_limit_paras->req_type)))
-    {
-        flowids->flowid_A[0] = rate_limit_paras->vfid * 2      + PLCR_CAR_A_DPDK_FLOWID_OFFSET;
-        flowids->flowid_A[1] = rate_limit_paras->vfid * 2 + 1  + PLCR_CAR_A_DPDK_FLOWID_OFFSET;
-        PLCR_LOG_INFO("flowids->flowid_A[0] = 0x%x\n", flowids->flowid_A[0]);
-        PLCR_LOG_INFO("flowids->flowid_A[1] = 0x%x\n", flowids->flowid_A[1]);
-    }
-    else
-    {
-        PLCR_LOG_INFO("Car A's flowid is not needed!\n");
-        return 0;
-    }
-
-    return rtn;
-}
-
-int zxdh_plcr_get_car_b_flowid(struct zxdh_pf_device *pf_dev, E_RATE_LIMIT_MODE mode, zxdh_plcr_rate_limit_paras *rate_limit_paras, zxdh_plcr_flowids *flowids)
-{
-    int rtn = 0;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    //pf队列字节限速不需要指定vf_idx，视作一个特殊vf端口，同样根据vqm_vfid分配flowid
-    //端口组字节限速的前提是先建立端口组，在后面流程会直接退出
-    flowids->flowid_B[0] = rate_limit_paras->vfid * 2;
-    flowids->flowid_B[1] = rate_limit_paras->vfid * 2 + 1;
-
-    PLCR_LOG_INFO("flowids->flowid_B[0] = 0x%x\n", flowids->flowid_B[0]);
-    PLCR_LOG_INFO("flowids->flowid_B[1] = 0x%x\n", flowids->flowid_B[1]);
-
-
-    return rtn;
-}
-
-/*
-函数功能：获取car c的flowid
-资源分配：
-    ---car c有1024个flowid资源
-    ---4个EP * 8个PF * 2个方向（接收和发送）= 64
-    ---1024 / 64 = 16，即每个pf分配16个group
-
-背景描述：
-    ---除了队列限速，其它所有限速都是操作pf下的文件系统，en_priv对应的肯定是pf设备
-    ---rate_limit_paras->vport，这个指向的是vf_idx对应的vf设备
-    ---所以，我们需要通过en_priv获取ep和pf func num
-
-返回值：成功返回0，失败返回其它值
-*/
-int zxdh_plcr_get_car_c_flowid(struct zxdh_pf_device *pf_dev, E_RATE_LIMIT_MODE mode, zxdh_plcr_rate_limit_paras *rate_limit_paras, zxdh_plcr_flowids *flowids)
-{
-    uint16_t vport  = 0;
-    uint32_t epid   = 0;
-    uint32_t pf_num = 0;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    vport = pf_dev->vport;
-    PLCR_LOG_INFO("pf's info : vport = 0x%x\n0", vport);
-
-    if(rate_limit_paras->group_id >= 16)
-    {
-        PLCR_LOG_ERR("group_id must be less than 16!\n");
-        return -ERANGE;
-    }
-
-    //用户设置vf的队列限速的时候，这里的vport是vf端口，不是pf端口
-    //vf的vport和pf的vport一样，都包含了相同的epid和pf function
-    epid   = EPID(vport);
-    pf_num = FUNC_NUM(vport);
-    PLCR_LOG_INFO("pf's info : epid = 0x%x, pf_num = 0x%x\n", epid, pf_num);
-
-    //端口组要么是0，要么是用户指定（端口组字节限速，移动端口组）
-    flowids->flowid_C[0] = epid * PLCR_CAR_C_FLOWIDS_PER_EP + pf_num * PLCR_CAR_C_FLOWIDS_PER_PF + rate_limit_paras->group_id * 2;
-    flowids->flowid_C[1] = epid * PLCR_CAR_C_FLOWIDS_PER_EP + pf_num * PLCR_CAR_C_FLOWIDS_PER_PF + rate_limit_paras->group_id * 2 + 1;
-
-    PLCR_LOG_INFO("flowids->flowid_C[0] = 0x%x\n", flowids->flowid_C[0]);
-    PLCR_LOG_INFO("flowids->flowid_C[1] = 0x%x\n", flowids->flowid_C[1]);
-
-    return 0;
-}
-
-/*
-函数功能：获取对应的Vfi
-入参：
-    ---vf_idx : pf内vf的编号，vf_idx是查找vport的索引，是中间工具，最终使用Vfid来定位vport
-    ---vfid   : vport的Vfid
-场景：
-    ---1.  pf队列字节限速： 用户使用echo，      调用pf的钩子函数，走if分支，    不需要指定vf_idx，不需要Vfid（不需要进行级间映射）
-    ---2.  vf队列字节限速： 用户命令使用echo，   调用vf的否子函数，走else分支，  不需要指定vf_idx
-    ---3.  vf端口字节限速： 用户命令使用ip link，调用pf的钩子函数，走if分支，    需要指定vf_idx
-    ---3.  vf端口字节限速： 后期会支持echo，     调用pf的钩子函数，走if分支，     需要指定vf_idx
-    ---4.  vf端口包限速：   用户命令使用echo，   调用pf的钩子函数，走if分支，     需要指定vf_idx
-    ---5.  vf端口组字节限速：用户命令使用echo，   调用pf的钩子函数，走if分支，    不需要指定vf_idx，不需要Vfid（不需要进行级间映射）
-    ---6.  vf端口移动组：   用户命令使用echo，   调用pf的钩子函数，走if分支，    需要指定vf_idx
-返回值：成功返回0，失败返回其它值
-*/
-int zxdh_plcr_get_vport_vfid(struct zxdh_pf_device *pf_dev, uint32_t vf_idx, uint32_t *vport, uint32_t *vfid)
-{
-    int32_t rtn = 0;
-    struct zxdh_vf_item   *vf_item;
-    struct dh_core_dev *dh_dev = container_of((void*)pf_dev, struct dh_core_dev, priv);
-
-    PLCR_FUNC_DBG_ENTER();
-
-    if (dh_dev->coredev_type == DH_COREDEV_PF)
-    {
-        PLCR_LOG_INFO("pf: pf_dev->vport = 0x%x, pf_dev->pcie_id = 0x%x\n", pf_dev->vport, pf_dev->pcie_id);
-        //场景中有不需要指定vf_idx的情况，不会生成vf_id
-        if (PLCR_INVALID_PARAM == vf_idx)
-        {
-            //pf队列限速和vf端口组字节限速，都不需要指定vf_idx
-            //但vf端口组字节限速必须要用到vport, pf队列也需分配一个carb flowid
-            *vport = pf_dev->vport;
-            *vfid  = VQM_VFID(pf_dev->vport);
-
-            PLCR_LOG_INFO("vf_idx is not specified! vport = %x, vfid = %x\n", pf_dev->vport, *vfid);
-            return rtn;
-        }
-        else
-        {
-            vf_item = &pf_dev->vf_item[vf_idx];
-            if(ERR_PTR(-EINVAL) == vf_item)
-            {
-                return -EINVAL;
-            }
-
-            *vport = vf_item->vport;
-            *vfid  = VQM_VFID(vf_item->vport);
-
-            PLCR_LOG_INFO("vf_idx = 0x%x, vf_item->vport = 0x%x, vfid = 0x%x\n", vf_idx, vf_item->vport, *vfid);
-            PLCR_LOG_INFO("mac address = %x %x %x %x %x %x\n", vf_item->mac[0],vf_item->mac[1],vf_item->mac[2],vf_item->mac[3],vf_item->mac[4],vf_item->mac[5]);
-        }
-    }
-    else
-    {
-        PLCR_LOG_INFO("vf: pf_dev->vport = 0x%x, pf_dev->pcie_id = 0x%x\n", pf_dev->vport, pf_dev->pcie_id);
-
-        *vport = pf_dev->vport;
-        *vfid  = VQM_VFID(pf_dev->vport);
-
-        PLCR_LOG_INFO("vf_idx = 0x%x, pf_dev->vport = 0x%x, vfid = 0x%x\n", vf_idx, pf_dev->vport, *vfid);
-    }
-
-    return rtn;
-}
-
-int zxdh_plcr_get_cars_flowid(struct zxdh_pf_device *pf_dev, E_RATE_LIMIT_MODE mode, zxdh_plcr_rate_limit_paras *rate_limit_paras, zxdh_plcr_flowids *flowids)
-{
-    int rtn = 0;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    //init the pointer flowids with invalid value
-    memset(flowids, 0xff, sizeof(zxdh_plcr_flowids));
-
-    //get car A flowid
-    rtn = zxdh_plcr_get_car_a_flowid(pf_dev, mode, rate_limit_paras, flowids);
-    PLCR_COMM_ASSERT(rtn);
-
-    //get car B flowid
-    rtn = zxdh_plcr_get_car_b_flowid(pf_dev, mode, rate_limit_paras, flowids);
-    PLCR_COMM_ASSERT(rtn);
-
-    //get car C flowid
-    rtn = zxdh_plcr_get_car_c_flowid(pf_dev, mode, rate_limit_paras, flowids);
-    PLCR_COMM_ASSERT(rtn);
-
-    return rtn;
-}
-
-int zxdh_plcr_get_next_mode(struct zxdh_pf_device *pf_dev, zxdh_plcr_rate_limit_paras *rate_limit_paras, uint32_t *next_mode)
-{
-    int rtn = 0;
-    E_RATE_LIMIT_MODE cur_mode;
-
-    //get vport current mode
-    rtn = zxdh_plcr_get_mode(pf_dev, rate_limit_paras->vport, &cur_mode);
-    PLCR_COMM_ASSERT(rtn);
-
-    if(E_RATE_LIMIT_MODE0 == cur_mode)
-    {
-        if(E_RATE_LIMIT_REQ_QUEUE_BYTE == rate_limit_paras->req_type)
-        {
-            *next_mode = E_RATE_LIMIT_MODE1;
-        }
-        else
-        {
-            *next_mode = E_RATE_LIMIT_MODE2;
-        }
-
-        return 0;
-    }
-    else
-    {
-        return -EINVAL;
-    }
-
-    return rtn;
-}
-
-int zxdh_plcr_init_flow(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint32_t flowid)
-{
-    int rtn = 0;
-    uint32_t vf_idx;
-    uint32_t vport;
-    uint32_t vfid;
-    uint32_t map_flowid;
-    union zxdh_msg msg = {0};
-    DPP_PF_INFO_T pf_info = {0};
-    struct dh_core_dev *dh_dev = container_of((void*)pf_dev, struct dh_core_dev, priv);
-
-    PLCR_FUNC_DBG_ENTER();
-
-    if (dh_dev->coredev_type == DH_COREDEV_PF)
-    {
-        if (car_type == E_PLCR_CAR_C)
-        {
-            //对于carC flow的初始化，需检查目标group中num_vfs是否为0，确定其是否是本次移动前新建
-            for (vf_idx = 0; vf_idx < pf_dev->num_vfs; vf_idx ++)
-            {
-                rtn = zxdh_plcr_get_vport_vfid(pf_dev, vf_idx, &vport, &vfid);
-                PLCR_COMM_ASSERT(rtn);
-                rtn = zxdh_plcr_get_next_map(pf_dev, E_PLCR_CAR_B, vfid * 2, &map_flowid);
-                PLCR_COMM_ASSERT(rtn);
-                if (!rtn && flowid == map_flowid)
-                {
-                    PLCR_LOG_INFO("Group is currently being used by at least one VF\n");
-                    return 0;
-                }
-            }
-        }
-        pf_info.slot = pf_dev->slot_id;
-        pf_info.vport = pf_dev->vport;
-        PLCR_LOG_INFO("dpp_car_queue_cfg_set: vport = 0x%x, car_type = %d, flowid = %d, plcr_en = 0\n",
-                        pf_dev->vport, car_type, flowid);
-        rtn = dpp_car_queue_cfg_set(&pf_info, (uint32_t)car_type, flowid, DROP_DISABLE, PLCR_DISABLE, 0);
-        if (rtn)
-            PLCR_LOG_ERR("failed to call dpp_car_queue_cfg_set()\n");
-    }
-    else
-    {
-        //针对vf队列限速的场景
-        msg.payload.hdr.op_code = ZXDH_PLCR_FLOW_INIT;
-        msg.payload.hdr.vport   = pf_dev->vport;
-        msg.payload.hdr.pcie_id = pf_dev->pcie_id;
-        msg.payload.hdr.vf_id   = pf_dev->pcie_id & (0xff);
-
-        msg.payload.plcr_flow_init_msg.car_type = car_type;
-        msg.payload.plcr_flow_init_msg.flowid = flowid;
-
-        rtn = zxdh_pf_msg_send_cmd(dh_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true);
-        PLCR_COMM_ASSERT(rtn);
-    }
-
-    return rtn;
-}
-
-/*
-函数功能：根据不同的场景进行三级映射，下面枚举出所有场景。
-
-    原始模式        限速请求        转换模式        映射
-
-    mode0          队列字节限速    mode1          (car A -> car B) & (car B -> car C)
-    mode0          端口字节限速    mode2          (car A -> car B) & (car B -> car C)
-    mode0          端口包限速      mode2          (car A -> car B) & (car B -> car C)
-    mode0          移动组         mode2          (car A -> car B) & (car B -> car C)
-
-    mode1          队列字节限速    mode1          不需要
-    mode1          端口字节限速    mode1          不需要
-    mode1          移动组         mode1          (car B -> car C)
-
-    mode2          端口包限速     mode2           不需要
-    mode2          端口字节限速    mode2          不需要
-    mode2          移动组         mode2          (car B -> car C)
-
-    x              端口组字节限速  无端口，无模式    不需要映射，直接配置限速
-*/
-int zxdh_plcr_set_cars_map(struct zxdh_pf_device *pf_dev, zxdh_plcr_rate_limit_paras *rate_limit_paras, zxdh_plcr_flowids *flowids)
-{
-    int rtn = 0;
-    uint32_t flowid;
-    uint32_t map_flowid;
-    E_RATE_LIMIT_MODE mode;
-    E_RATE_LIMIT_REQ_TYPE req_type;
-    int queue_pair_index;
-
-    PLCR_FUNC_DBG_ENTER();
-
-    //get vport and vfid
-    rtn = zxdh_plcr_get_vport_vfid(pf_dev, rate_limit_paras->vf_idx, &rate_limit_paras->vport, &rate_limit_paras->vfid);
-    PLCR_COMM_ASSERT(rtn);
-
-    //get vport current mode
-    rtn = zxdh_plcr_get_mode(pf_dev, rate_limit_paras->vport, &mode);
-    PLCR_COMM_ASSERT(rtn);
-
-    //get rate limit type
-    rtn = zxdh_plcr_check_req_type(pf_dev, mode, rate_limit_paras, &req_type);
-    PLCR_COMM_ASSERT(rtn);
-
-    //获取三级car的flowid
-    rtn = zxdh_plcr_get_cars_flowid(pf_dev, mode, rate_limit_paras, flowids);
-    PLCR_COMM_ASSERT(rtn);
-
-    if (E_RATE_LIMIT_MODE0 == mode)
-    {
-        if (E_RATE_LIMIT_REQ_QUEUE_BYTE == req_type)
-        {
-            for(queue_pair_index = 0; queue_pair_index < flowids->queue_pairs; queue_pair_index++)
-            {
-                //rxq：初始化flow，避免有复位前的配置遗留，将car A flowid映射到car B flowid
-                flowid     = flowids->flowids_A[0][queue_pair_index];
-                map_flowid = flowids->flowid_B[0];
-                PLCR_LOG_INFO("car_type = 0x%x, flowid = 0x%x, map_flowid = 0x%x\n", E_PLCR_CAR_A, flowid, map_flowid);
-
-                rtn = zxdh_plcr_init_flow(pf_dev, E_PLCR_CAR_A, flowid);
-                PLCR_COMM_ASSERT(rtn);
-                rtn = zxdh_plcr_map_flowid(pf_dev, E_PLCR_CAR_A, flowid, map_flowid);
-                PLCR_COMM_ASSERT(rtn);
-
-
-                //txq：初始化car A flow，映射到car B flowid
-                flowid     = flowids->flowids_A[1][queue_pair_index];
-                map_flowid = flowids->flowid_B[1];
-                PLCR_LOG_INFO("car_type = 0x%x, flowid = 0x%x, map_flowid = 0x%x\n", E_PLCR_CAR_A, flowid, map_flowid);
-
-                rtn = zxdh_plcr_init_flow(pf_dev, E_PLCR_CAR_A, flowid);
-                PLCR_COMM_ASSERT(rtn);
-                rtn = zxdh_plcr_map_flowid(pf_dev, E_PLCR_CAR_A, flowid, map_flowid);
-                PLCR_COMM_ASSERT(rtn);
-            }
-        }
-        else if ((E_RATE_LIMIT_REQ_VF_PKT == req_type) || (E_RATE_LIMIT_REQ_VF_BYTE == req_type) || (E_RATE_LIMIT_REQ_MOVE_VF_GROUP == req_type))
-        {
-            //vfid's rx ：初始化car A flow，映射到car B flowid
-            flowid = flowids->flowid_A[0];
-            map_flowid = flowids->flowid_B[0];
-            PLCR_LOG_INFO("car_type = 0x%x, flowid = 0x%x, map_flowid = 0x%x\n", E_PLCR_CAR_A, flowid, map_flowid);
-
-            rtn = zxdh_plcr_init_flow(pf_dev, E_PLCR_CAR_A, flowid);
-            PLCR_COMM_ASSERT(rtn);
-            rtn = zxdh_plcr_map_flowid(pf_dev, E_PLCR_CAR_A, flowid, map_flowid);
-            PLCR_COMM_ASSERT(rtn);
-
-
-            //vfid's tx ：初始化car A flow，映射到car B flowid
-            flowid = flowids->flowid_A[1];
-            map_flowid = flowids->flowid_B[1];
-            PLCR_LOG_INFO("car_type = 0x%x, flowid = 0x%x, map_flowid = 0x%x\n", E_PLCR_CAR_A, flowid, map_flowid);
-
-            rtn = zxdh_plcr_init_flow(pf_dev, E_PLCR_CAR_A, flowid);
-            PLCR_COMM_ASSERT(rtn);
-            rtn = zxdh_plcr_map_flowid(pf_dev, E_PLCR_CAR_A, flowid, map_flowid);
-            PLCR_COMM_ASSERT(rtn);
-        }
-    }
-
-    /*
-    功能：car B的flowid映射到car C的flowid
-    场景：
-        ---1.当前mode0模式，用户请求队列字节限速，  用户未指定group：group默认为0
-        ---2.当前mode0模式，用户请求vf端口字节限速，用户未指定group：group默认为0
-        ---3.当前mode0模式，用户请求vf端口包限速，  用户未指定group：group默认为0
-        ---4.当前mode0模式，用户请求端口组字节限速， 用户指定group：不需要car B到car C的映射，直接设置限速
-
-        ---5.任意模式，     用户请求移动group，    用户指定group：按照用户指定的group
-        ---其它场景下：不需要进行映射
-    */
-    if (((E_RATE_LIMIT_MODE0 == mode) && (E_RATE_LIMIT_REQ_VF_GROUP_BYTE != req_type)) || (E_RATE_LIMIT_REQ_MOVE_VF_GROUP == req_type))
-    {
-        //car B rx flowid is mapped to car C rx flowid
-        flowid = flowids->flowid_B[0];
-        map_flowid = flowids->flowid_C[0];
-        PLCR_LOG_INFO("car_type = 0x%x, flowid = 0x%x, map_flowid = 0x%x\n", E_PLCR_CAR_B, flowid, map_flowid);
-
-        if (E_RATE_LIMIT_MODE0 == mode)
-        {
-            rtn = zxdh_plcr_init_flow(pf_dev, E_PLCR_CAR_B, flowid);
-            PLCR_COMM_ASSERT(rtn);
-        }
-        rtn = zxdh_plcr_init_flow(pf_dev, E_PLCR_CAR_C, map_flowid);
-        PLCR_COMM_ASSERT(rtn);
-
-        rtn = zxdh_plcr_map_flowid(pf_dev, E_PLCR_CAR_B, flowid, map_flowid);
-        PLCR_COMM_ASSERT(rtn);
-
-
-        //car B tx flowid is mapped to car C tx flowid
-        flowid = flowids->flowid_B[1];
-        map_flowid = flowids->flowid_C[1];
-        PLCR_LOG_INFO("car_type = 0x%x, flowid = 0x%x, map_flowid = 0x%x\n", E_PLCR_CAR_B, flowid, map_flowid);
-
-        if (E_RATE_LIMIT_MODE0 == mode)
-        {
-            rtn = zxdh_plcr_init_flow(pf_dev, E_PLCR_CAR_B, flowid);
-            PLCR_COMM_ASSERT(rtn);
-        }
-        rtn = zxdh_plcr_init_flow(pf_dev, E_PLCR_CAR_C, map_flowid);
-        PLCR_COMM_ASSERT(rtn);
-
-        rtn = zxdh_plcr_map_flowid(pf_dev, E_PLCR_CAR_B, flowid, map_flowid);
-        PLCR_COMM_ASSERT(rtn);
-        PLCR_LOG_INFO("Successfull to map!\n");
-    }
-
-    return rtn;
-}
-
-int zxdh_plcr_unified_set_rate_limit(struct zxdh_pf_device *pf_dev,
-                              zxdh_plcr_rate_limit_paras *rate_limit_paras)
-{
-    int rtn = 0;
-    union zxdh_msg msg = {0};
-    zxdh_plcr_flowids flowids;
-    uint32_t next_mode;
-    E_RATE_LIMIT_REQ_TYPE req_type;
-    uint32_t vport     = 0;
-    uint32_t flowid    = 0;
-    uint32_t car_type  = 0;
-    uint32_t is_packet = 0;
-    uint32_t max_rate  = 0;
-    uint32_t min_rate  = 0;
-    struct dh_core_dev *dh_dev = container_of((void*)pf_dev, struct dh_core_dev, priv);
-
-    PLCR_FUNC_DBG_ENTER();
-
-    //map car A's flowid to car B's flowid, car B's flowid to car C's flowid
-    rtn = zxdh_plcr_set_cars_map(pf_dev, rate_limit_paras, &flowids);
-    PLCR_COMM_ASSERT(rtn);
-
-    req_type = rate_limit_paras->req_type;
-
-    //移动vf端口组：不需要设置限速，只需要级间映射（上面已经完成映射）
-    if (E_RATE_LIMIT_REQ_MOVE_VF_GROUP == req_type)
-    {
-        PLCR_LOG_INFO("E_RATE_LIMIT_REQ_MOVE_VF_GROUP does not need set rate limit!\n\n");
-
-        return 0;
-    }//队列字节限速
-    else if (E_RATE_LIMIT_REQ_QUEUE_BYTE == req_type)
-    {
-        if (E_RATE_LIMIT_RX == rate_limit_paras->direction)
-        {
-            flowid = flowids.flowids_A[0][rate_limit_paras->queue_id];
-        }
-        else
-        {
-            flowid = flowids.flowids_A[1][rate_limit_paras->queue_id];
-        }
-
-        max_rate = rate_limit_paras->max_rate;
-        min_rate = 0;
-        car_type  = E_PLCR_CAR_A;
-        is_packet = E_RATE_LIMIT_BYTE;
-    }//vf端口字节限速
-    else if(E_RATE_LIMIT_REQ_VF_BYTE == req_type)
-    {
-        if (E_RATE_LIMIT_RX == rate_limit_paras->direction)
-        {
-            flowid = flowids.flowid_B[0];
-        }
-        else
-        {
-            flowid = flowids.flowid_B[1];
-        }
-
-        max_rate = rate_limit_paras->max_rate;
-        min_rate = rate_limit_paras->min_rate;
-        car_type  = E_PLCR_CAR_B;
-        is_packet = E_RATE_LIMIT_BYTE;
-    }//端口组字节限速
-    else if(E_RATE_LIMIT_REQ_VF_GROUP_BYTE == req_type)
-    {
-        if (E_RATE_LIMIT_RX == rate_limit_paras->direction)
-        {
-            flowid = flowids.flowid_C[0];
-        }
-        else
-        {
-            flowid = flowids.flowid_C[1];
-        }
-
-        max_rate = rate_limit_paras->max_rate;
-        min_rate = 0;
-        car_type  = E_PLCR_CAR_C;
-        is_packet = E_RATE_LIMIT_BYTE;
-    }
-    else
-    {
-        return -EINVAL;
-    }
-
-
-    PLCR_LOG_INFO("flowid    = 0x%x\n", flowid);
-    PLCR_LOG_INFO("car_type  = 0x%x\n", car_type);
-    PLCR_LOG_INFO("is_packet = 0x%x\n", is_packet);
-    PLCR_LOG_INFO("max_rate  = 0x%x\n", max_rate);
-    PLCR_LOG_INFO("min_rate  = 0x%x\n", min_rate);
-
-    vport = rate_limit_paras->vport;
-
-    //set rate limit
-    if (dh_dev->coredev_type == DH_COREDEV_PF)
-    {
-        rtn = zxdh_plcr_set_rate_limit(pf_dev, is_packet, car_type, vport, flowid, max_rate, min_rate);
-    }
-    else if (dh_dev->coredev_type == DH_COREDEV_VF)
-    {
-        msg.payload.hdr.op_code = ZXDH_VF_RATE_LIMIT_SET;
-        msg.payload.hdr.vport   = pf_dev->vport;
-        msg.payload.hdr.pcie_id = pf_dev->pcie_id;
-        msg.payload.hdr.vf_id   = pf_dev->pcie_id & (0xff);
-
-        msg.payload.rate_limit_set_msg.flowid    = flowid;
-        msg.payload.rate_limit_set_msg.car_type  = car_type;
-        msg.payload.rate_limit_set_msg.is_packet = is_packet;
-        msg.payload.rate_limit_set_msg.max_rate  = max_rate;
-        msg.payload.rate_limit_set_msg.min_rate  = min_rate;
-
-        PLCR_LOG_INFO("msg.payload.rate_limit_set_msg.flowid    = 0x%x\n", msg.payload.rate_limit_set_msg.flowid);
-        PLCR_LOG_INFO("msg.payload.rate_limit_set_msg.car_type  = 0x%x\n", msg.payload.rate_limit_set_msg.car_type);
-        PLCR_LOG_INFO("msg.payload.rate_limit_set_msg.is_packet = 0x%x\n", msg.payload.rate_limit_set_msg.is_packet);
-        PLCR_LOG_INFO("msg.payload.rate_limit_set_msg.max_rate  = 0x%x\n", msg.payload.rate_limit_set_msg.max_rate);
-        PLCR_LOG_INFO("msg.payload.rate_limit_set_msg.min_rate  = 0x%x\n", msg.payload.rate_limit_set_msg.min_rate);
-
-        rtn = zxdh_pf_msg_send_cmd(dh_dev, MODULE_VF_BAR_MSG_TO_PF, &msg, &msg, true);
-        PLCR_COMM_ASSERT(rtn);
-
-        rtn = msg.reps.rate_limit_set_rsp.err_code;
-    }
-    //0：限速设置成功
-    //PLCR_REMOVE_RATE_LIMIT：解除限速成功
-    //其它值：错误码
-    PLCR_COMM_ASSERT((0 != rtn) && (PLCR_REMOVE_RATE_LIMIT != rtn));
-
-    /*************下面2种场景需要模式切换*************
-     * 1. mode 0 -> mode 1
-     * 2. mode 0 -> mode 2
-     * 一般情况下，vport处于mode 1或者mode 2保持不变，只有在解除限速的时候可能会跳转到mode 0
-    ****************************************/
-   if (0 == rtn) //解除限速的场景就不需要进行模式切换
-   {
-        rtn = zxdh_plcr_get_next_mode(pf_dev, rate_limit_paras, &next_mode);
-        if(0 == rtn)
-        {
-            rtn = zxdh_plcr_set_mode(pf_dev, vport, next_mode);
-            PLCR_COMM_ASSERT(rtn);
-        }
-   }
-
-    return 0;
-
-}
-EXPORT_SYMBOL(zxdh_plcr_unified_set_rate_limit);
-
+#ifdef AUX_BUS_NO_SUPPORT
+#include <linux/dinghai/auxiliary_bus.h>
+#else
+#include <linux/auxiliary_bus.h>
+#endif
+
+#include <linux/dinghai/driver.h>
+#include <net/devlink.h>
+#include <net/udp_tunnel.h>
+#include <linux/dinghai/devlink.h>
+#include <linux/dinghai/dh_cmd.h>
+#include <linux/netdevice.h>
+#include "en_aux.h"
+#include "en_ethtool/ethtool.h"
+#include <linux/dinghai/en_sf.h>
+#include <linux/etherdevice.h>
+#include <linux/dinghai/helper.h>
+#include "en_np/table/include/dpp_tbl_api.h"
+#include "en_aux/events.h"
+#include "en_aux/eq.h"
+#include "en_aux/en_cmd.h"
+#include "msg_common.h"
+#include "en_pf.h"
+#include <linux/dinghai/kcompat.h>
+#include "en_aux/en_ioctl.h"
+#ifdef TIME_STAMP_1588
+#include "en_aux/en_1588_pkt_proc.h"
+#endif
+
+const uint32_t gaudPlcrCarxProfileNum[E_PLCR_CAR_NUM] = {
+	PLCR_CAR_A_PROFILE_RES_NUM, //一级CAR：512个限速模板
+	PLCR_CAR_B_PROFILE_RES_NUM, //二级CAR：128个限速模板
+	PLCR_CAR_C_PROFILE_RES_NUM, //三级CAR：32个限速模板
+};
+EXPORT_SYMBOL(gaudPlcrCarxProfileNum);
+
+const uint32_t gaudPlcrCarxFlowIdNum[E_PLCR_CAR_NUM] = {
+	PLCR_CAR_A_FLOWID_RES_NUM, //一级CAR：只有tx的限速需求，只需要记录tx的信息
+	PLCR_CAR_B_FLOWID_RES_NUM, //二级CAR：前1K个给tx用，后1K个给rx用
+	PLCR_CAR_C_FLOWID_RES_NUM, //三级CAR：前256个给tx用，后256个给rx用
+};
+EXPORT_SYMBOL(gaudPlcrCarxFlowIdNum);
+
+/*
+todo:
+rsvd字段为1标识失败，为0标识成功
+修改原有的限速值，只用修改限速模板，不用再调用关联函数；
+还有代码中在配置限速模板的时候引用+1了，会影响现有的流程的（结果可能没问题，需要考虑是不是将+1和-1更换位置）；
+如果找到共享模板，在配置队列失败的时候会减一，加一和减一的位置不对称，会导致计数值不正确。
+*/
+
+/*
+函数功能：将pf或者vf下的发送队列号（逻辑队列号），转换成vqm的实际队列号
+入参：
+	---pf_dev     : pf设备结构体
+	---qid        : 设备下的，取值0，1，2，3......
+返回值：返回vqm中的发送队列号，发送队列号为奇数
+*/
+uint zxdh_plcr_vf_qid_2_flowid(struct zxdh_en_priv *en_priv, uint32_t qid)
+{
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	uint32_t phy_index;
+	uint32_t flowid;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+	phy_index = en_dev->sq[qid].vq->phy_index;
+	flowid = phy_index;
+	LOG_INFO("%s-%d:flow_id=%d\n", __FUNCTION__, __LINE__, flowid);
+	return flowid;
+}
+EXPORT_SYMBOL(zxdh_plcr_vf_qid_2_flowid);
+
+/*
+函数功能：将用户输入的速率，转换成限速模板配置寄存器的格式
+入参：
+	---max_rate   : 单位是Mbit/s
+
+返回值：返回vqm中的发送队列号，发送队列号为奇数
+*/
+uint32_t zxdh_plcr_calc_maxrate_cfg(uint32_t max_rate)
+{
+	uint64_t maxrate_cfg;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+	maxrate_cfg =
+			(max_rate * 1000 /
+			 PLCR_STEP_SIZE); //改为61kbps的倍数,单位由"Mbps"转化为"61Kbps"
+	//(uint32_t)(max_rate + 0.5)* 1000 / PLCR_STEP_SIZE
+
+	maxrate_cfg = (maxrate_cfg < PLCR_MIN_RATE) ? PLCR_MIN_RATE : maxrate_cfg;
+	maxrate_cfg = (maxrate_cfg > PLCR_MAX_RATE) ? PLCR_MAX_RATE : maxrate_cfg;
+
+	return (uint32_t)maxrate_cfg;
+}
+EXPORT_SYMBOL(zxdh_plcr_calc_maxrate_cfg);
+
+/*
+函数功能：将寄存器中的配置值，转换成用户的限速值（）
+将用户输入的速率，转换成限速模板配置寄存器的格式
+入参：
+	---maxrate_cfg   : 单位是61Kb/s
+
+返回值：返回vqm中的发送队列号，发送队列号为奇数
+*/
+uint32_t zxdh_plcr_calc_user_maxrate_cfg(uint32_t maxrate_cfg)
+{
+	uint32_t max_rate;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	max_rate = maxrate_cfg * PLCR_STEP_SIZE / 1000;
+
+	return max_rate;
+}
+EXPORT_SYMBOL(zxdh_plcr_calc_user_maxrate_cfg);
+
+/*
+函数功能：查找是否有共享的限速模板
+入参：
+	---pf_dev     : pf设备结构体
+	---car_type   : plcr CAR层级，取值：CAR_A，CAR_B，CAR_C
+	---profile_cfg: 待查询的限速模板参数
+	---profile_id : 保存查询到的限速模板的id
+
+返回值：0表示查询成功，其它值表示查询失败
+*/
+static int32_t zxdh_plcr_match_profile(struct zxdh_pf_device *pf_dev,
+									   E_PLCR_CAR_TYPE car_type,
+									   DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg,
+									   uint16_t *profile_id)
+{
+	struct xarray *xarray_profile =
+			&(pf_dev->plcr_table.plcr_profiles[car_type]);
+	struct zxdh_plcr_profile *profile;
+	unsigned long index;
+	uint32_t profile_max_num = gaudPlcrCarxProfileNum[car_type];
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	/*遍历vf申请的某一级CAR所有限速模板，是否有指定速率的限速模板存在*/
+	xa_for_each_range(xarray_profile, index, profile, 0, profile_max_num) {
+		if (profile->ref_cnt &&
+			(profile->profile_cfg.pkt_sign == profile_cfg->pkt_sign) &&
+			(profile->profile_cfg.cd ==
+			 profile_cfg->cd) && /**<  @brief CD算法标志/令牌桶算法标志 0:srtcm
+								1:trtcm 2:MEF10.1*/
+			(profile->profile_cfg.cf ==
+			 profile_cfg->cf) && /**<  @brief CF溢出耦合标志，0:不溢出，1:溢出*/
+			(profile->profile_cfg.cm ==
+			 profile_cfg
+					 ->cm) && /**<  @brief CM色盲/色敏标志，0:色盲模式，1:色敏模式 */
+			(profile->profile_cfg.cir ==
+			 profile_cfg->cir) && /**<  @brief C令牌桶添加速率(0~X, X
+									Gbps/64kbps),最小值为64Kbps，步长为64Kbps*/
+			(profile->profile_cfg.cbs == profile_cfg->cbs) && /**<  @brief
+									C桶桶深(XM),配置范围为0~XMByte-1，步长为1Byte*/
+			(profile->profile_cfg.eir ==
+			 profile_cfg->eir) && /**<  @brief E令牌桶添加速率(0~X,
+									XGbps/64kbps),最小值为64Kbps，步长为64Kbps*/
+			(profile->profile_cfg.ebs == profile_cfg->ebs)) /**<  @brief
+								E桶桶深(XM),配置范围为0~XMByte-1，步长为1Byte*/
+		{
+			*profile_id = profile->profile_id;
+
+			return 0;
+		}
+	}
+
+	/* 未搜索到匹配项*/
+	return -ERANGE;
+}
+
+/*
+函数功能：为flowid申请一个xarray成员
+入参：
+	---pf_dev     : pf设备结构体
+	---car_type   : plcr CAR层级，一级，二级或三级
+	---flow_id    : 作为xarray的索引
+返回值：返回创建的zxdh_plcr_flow *指针
+*/
+int32_t zxdh_plcr_req_flow(struct zxdh_pf_device *pf_dev,
+						   E_PLCR_CAR_TYPE car_type, uint16_t flow_id,
+						   struct zxdh_plcr_flow **flow)
+{
+	struct zxdh_plcr_flow *flow_old;
+	struct xarray *xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]);
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	/*1. malloc一个flow结构体*/
+	*flow = kzalloc(sizeof(struct zxdh_plcr_flow), GFP_KERNEL);
+	if (unlikely(NULL == *flow)) {
+		LOG_ERR("%s-%d : kzalloc failed\n", __FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+
+	/*2. 存储到xarray*/
+	flow_old = xa_store(xarray_flow, flow_id, *flow, GFP_KERNEL);
+	if (flow_old) {
+		/* 正常情况下，这里应该都是空的*/
+		kfree(flow_old);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(zxdh_plcr_req_flow);
+
+/*
+函数功能：释放一个xarray下的flowid成员
+入参：
+	---pf_dev     : pf设备结构体
+	---car_type   : plcr CAR层级，一级，二级或三级
+	---flow_id    : 作为xarray的索引
+返回值：返回创建的zxdh_plcr_flow *指针
+*/
+int32_t zxdh_plcr_release_flow(struct zxdh_pf_device *pf_dev,
+							   E_PLCR_CAR_TYPE car_type, uint16_t flow_id)
+{
+	struct zxdh_plcr_flow *flow;
+	struct xarray *xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]);
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	/*1. 检查xarray里是否有该flow*/
+	flow = xa_load(xarray_flow, flow_id);
+	if (NULL == flow) {
+		LOG_ERR("%s-%d : release an invalid flow_id=%d\n", __FUNCTION__,
+				__LINE__, flow_id);
+		return EINVAL;
+	}
+
+	/*2. 从xarray删除该成员*/
+	xa_erase(xarray_flow, flow_id);
+
+	/*3. 释放flow*/
+	kfree(flow);
+
+	return 0;
+}
+EXPORT_SYMBOL(zxdh_plcr_release_flow);
+
+/*
+函数功能：更新flow的成员信息
+入参：
+	---flow       : xarray的成员
+	---vport      :
+	---max_rate   :
+	---min_rate   :
+返回值：无
+*/
+void zxdh_plcr_update_flow(struct zxdh_plcr_flow *flow, uint16_t vport,
+						   uint32_t max_rate, uint32_t min_rate)
+{
+	flow->vport = vport;
+	flow->max_rate = max_rate;
+	flow->min_rate = min_rate;
+}
+EXPORT_SYMBOL(zxdh_plcr_update_flow);
+
+/*
+函数功能：申请一个指定CAR的限速模板
+入参：
+	---pf_dev     : pf设备结构体
+	---car_type   : plcr CAR层级，一级，二级或三级
+	---vport      : vf端口号
+	---profile_id_out : 返回申请到的限速模板的profile_id
+返回值：成功返回0，失败返回其它值
+*/
+int zxdh_plcr_req_profile(struct zxdh_pf_device *pf_dev,
+						  E_PLCR_CAR_TYPE car_type, uint16_t *profile_id_out)
+{
+	int rtn = 0;
+	struct zxdh_plcr_profile *profile;
+	struct zxdh_plcr_profile *profile_old;
+	struct xarray *xarray_profile =
+			&(pf_dev->plcr_table.plcr_profiles[car_type]);
+	uint16_t profile_id = 0;
+	uint64_t cred_id = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = pf_dev->slot_id;
+	pf_info.vport = pf_dev->vport;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	/*在指定的CAR申请一个新的限速模板*/
+	rtn = dpp_car_profile_id_add(&pf_info, (uint32_t)car_type, &cred_id);
+	if (rtn) {
+		/*判断消息交互是否正常*/
+		LOG_ERR("%s-%d : failed to request a new profile with a message\n",
+				__FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+
+	/*判断riscv是否成功返回了有效的profile：bit[56 - 63]为0标识成功，为1标识失败*/
+	if (0 != ((cred_id >> 56) & 0xFF)) {
+		LOG_ERR("%s-%d : failed to request a new profile\n", __FUNCTION__,
+				__LINE__);
+		return -EINVAL;
+	}
+
+	/*提取profile id*/
+	profile_id = PROFILE_ID(cred_id);
+	*profile_id_out = profile_id;
+
+	/*申请一个限速模板结构体，保存限速模板信息*/
+	profile = kzalloc(sizeof(struct zxdh_plcr_profile), GFP_KERNEL);
+	if (unlikely(NULL == profile)) {
+		dpp_car_profile_id_delete(&pf_info, (uint32_t)car_type, cred_id);
+
+		LOG_ERR("%s-%d : profile kzalloc failed\n", __FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+	profile->ref_cnt = 0;
+	profile->max_rate = 0;
+	profile->min_rate = 0;
+	profile->cred_id = cred_id;
+	profile->profile_id = profile_id;
+	profile->vport = pf_dev->vport;
+
+	/*将申请到的限速模板资源存储起来*/
+	profile_old = xa_store(xarray_profile, profile_id, profile, GFP_KERNEL);
+	if (profile_old) //正常情况下，这里应该都是空的
+		kfree(profile_old);
+
+	return rtn;
+}
+EXPORT_SYMBOL(zxdh_plcr_req_profile);
+
+/*
+函数功能：释放一个指定CAR的限速模板
+入参：
+	---pf_dev     : pf设备结构体
+	---car_type   : plcr CAR层级，一级，二级或三级
+	---Profile_id : 限速模板的profile_id
+返回值：成功返回0，失败返回其它值
+*/
+int zxdh_plcr_release_profile(struct zxdh_pf_device *pf_dev,
+							  E_PLCR_CAR_TYPE car_type, uint16_t profile_id)
+{
+	int rtn = 0;
+	struct xarray *xarray_profile =
+			&(pf_dev->plcr_table.plcr_profiles[car_type]);
+	struct zxdh_plcr_profile *profile;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+	pf_info.slot = pf_dev->slot_id;
+	/*判断是有是有效成员*/
+	profile = xa_load(xarray_profile, profile_id);
+	if (NULL == profile) {
+		LOG_ERR("%s-%d : release an invalid profile=%d\n", __FUNCTION__,
+				__LINE__, profile_id);
+		return EINVAL;
+	}
+
+	/*如果引用计数为0，则可以释放所有资源*/
+	if (0 == profile->ref_cnt) {
+		pf_info.vport = profile->vport;
+		/*归还限速模板资源（注意，引用计数为0表示没有关联的flow了）*/
+		rtn = dpp_car_profile_id_delete(&pf_info, car_type, profile->cred_id);
+		if (rtn) {
+			LOG_ERR("%s-%d : failed to call dpp_car_profile_id_delete(profile_id=%d)\n",
+					__FUNCTION__, __LINE__, profile_id);
+			rtn = EINVAL;
+		}
+
+		/*删除xarray中的元素*/
+		xa_erase(xarray_profile, profile_id);
+
+		/*释放profile指针*/
+		kfree(profile);
+	}
+
+	/*如果引用计数不为0，就不释放任何资源*/
+	return rtn;
+}
+EXPORT_SYMBOL(zxdh_plcr_release_profile);
+
+/*
+函数功能：内核态使用的接口，根据car_type & is_byte_rate_limit & max_rate &
+min_rate 这4个参数生成限速模板配置参数
+		内核态下各限速场景使用的参数应该是固定的，我们自己根据这4个参数生成完整的结构体参数：DPP_STAT_CAR_PROFILE_CFG_T
+		用户态的场景下，会通过消息直接传递过来，不需要组装
+入参：
+	---car_type   : plcr CAR层级，一级，二级或三级
+	---is_byte_rate_limit   :
+是否是字节限速，为后续包限速预留参数，这个值传参的时候暂时固定为1，
+							后续可能会有一个全局变量进行指示，会提供对应的接口来获取这个入参值进行传递
+	---max_rate             : 用户指定的最大限速值
+	---min_rate             : 用户指定的最小承诺速率
+	---profile_cfg          : 返回值，填充好的限速模板参数
+返回值：成功返回0，失败返回其它值
+*/
+static int zxdh_plcr_gen_profile(E_PLCR_CAR_TYPE car_type, uint32_t max_rate,
+								 uint32_t min_rate,
+								 DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg)
+{
+	int pri = 0;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	if (0 == max_rate)
+		max_rate = TXQ_MAX_RATE;
+
+	/*2. 重新生成参数*/
+
+	/*填充限速模板的参数，准备将这些参数配置到寄存器*/
+	memset(profile_cfg, 0, sizeof(*profile_cfg));
+	profile_cfg->pkt_sign = BYTE_RATE_LIMIT;
+	profile_cfg->cf = 1; //溢出标志，默认使能
+	profile_cfg->cbs =
+			14 * 1024 * 4; //实际调试时确定，define pkt_max_size 14*1024*4;
+	profile_cfg->ebs = 14 * 1024 * 4;
+	profile_cfg->random_disc_c = 0;
+	profile_cfg->random_disc_e = 0;
+
+	if (E_PLCR_CAR_A == car_type) {
+		profile_cfg->cm = 0; //色盲模式
+		profile_cfg->cd = 0; // 0: srTCM，单速率；1：双速率
+		profile_cfg->cir = zxdh_plcr_calc_maxrate_cfg(max_rate);
+		profile_cfg->eir = 0;
+	} else if (E_PLCR_CAR_B == car_type) {
+		profile_cfg->cm = 1; //色敏模式，todo：根据实际测试情况来调整
+		profile_cfg->cd = 1; // 0: srTCM，单速率；1：双速率
+		profile_cfg->cir = zxdh_plcr_calc_maxrate_cfg(min_rate);
+		profile_cfg->eir = zxdh_plcr_calc_maxrate_cfg(max_rate);
+	} else if (E_PLCR_CAR_C == car_type) {
+		// todo：端口组限速，待调试确认
+		profile_cfg->cm = 1; //色敏模式，todo：根据实际测试情况来调整
+		profile_cfg->cd = 1; // 0: srTCM，单速率；1：双速率
+		profile_cfg->cir = zxdh_plcr_calc_maxrate_cfg(min_rate);
+		profile_cfg->eir = zxdh_plcr_calc_maxrate_cfg(max_rate);
+	}
+
+	for (pri = 0; pri < DPP_CAR_PRI_MAX; pri++) {
+		profile_cfg->c_pri[pri] = 0;
+		profile_cfg->e_green_pri[pri] = 0;
+		profile_cfg->e_yellow_pri[pri] = 0;
+	}
+
+	return 0;
+}
+
+/*
+函数功能：更新限速模板参数
+入参：
+	---profile_cfg: 限速模板参数结构体
+	---Profile_id : 限速模板的profile_id
+返回值：无
+*/
+static void zxdh_plcr_update_profile(DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg,
+									 u_int16_t profile_id)
+{
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	/*1. 重新生成参数*/
+	profile_cfg->profile_id = profile_id;
+}
+
+/*
+函数功能：将限速模板参数，存储到profile下
+入参：
+	---pf_dev     : pf设备结构体
+	---car_type   : plcr CAR层级，一级，二级或三级
+	---max_rate   : 用户原始的限速速率，单位是Mbit/s
+	---min_rate   : 用户原始的限速速率，单位是Mbit/s
+	---profile_cfg: 要存储到profile中的，限速模板参数
+返回值：成功返回0，失败返回其它值
+*/
+int zxdh_plcr_store_profile(struct zxdh_pf_device *pf_dev,
+							E_PLCR_CAR_TYPE car_type, uint32_t max_rate,
+							uint32_t min_rate,
+							DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg)
+{
+	int rtn = 0;
+	uint16_t profile_id;
+	struct zxdh_plcr_profile *profile;
+	struct xarray *xarray_profile =
+			&(pf_dev->plcr_table.plcr_profiles[car_type]);
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	/*1. 从限速模板结构体，获取profile_id*/
+	profile_id = profile_cfg->profile_id;
+
+	/*2. 从xarray获取profile*/
+	profile = xa_load(xarray_profile, profile_id);
+	if (NULL == profile) {
+		LOG_ERR("%s-%d : specify an invalid profile\n", __FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+
+	/*3. 更新profile的参数*/
+	profile->max_rate = max_rate;
+	profile->min_rate = min_rate;
+
+	/*4. 将完整的限速模板参数，存储到profile结构体下*/
+	memcpy(&profile->profile_cfg, profile_cfg,
+		   sizeof(DPP_STAT_CAR_PROFILE_CFG_T));
+
+	return rtn;
+}
+EXPORT_SYMBOL(zxdh_plcr_store_profile);
+
+/*
+函数功能：将限速模板参数，配置到plcr寄存器中去
+入参：
+	---pf_dev     : pf设备结构体
+	---car_type   : plcr CAR层级，一级，二级或三级
+	---profile_cfg: 要配置个plcr寄存器的限速模板参数
+返回值：成功返回0，失败返回其它值
+*/
+int zxdh_plcr_cfg_profile(struct zxdh_pf_device *pf_dev,
+						  E_PLCR_CAR_TYPE car_type,
+						  DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg)
+{
+	int rtn = 0;
+	uint16_t profile_id = 0;
+	uint32_t pkt_sign = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = pf_dev->slot_id;
+	pf_info.vport = pf_dev->vport;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	/*1. 根据限速模板参数，获取profile_id*/
+	profile_id = profile_cfg->profile_id;
+
+	/*2. 根据限速模板参数，获取包/字节模式*/
+	pkt_sign = profile_cfg->pkt_sign;
+
+	/*3. 将限速模板参数，配置到寄存器中去*/
+	rtn = dpp_car_profile_cfg_set(&pf_info, (uint32_t)car_type, pkt_sign,
+								  profile_id, profile_cfg);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed to configure the profile registers\n",
+				__FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+
+	return rtn;
+}
+EXPORT_SYMBOL(zxdh_plcr_cfg_profile);
+
+/*
+函数功能：获取寄存器中限速模板的参数
+入参：
+	---pf_dev     : pf设备结构体
+	---car_type   : plcr CAR层级，一级，二级或三级
+	---profile_cfg: 要配置个plcr寄存器的限速模板参数
+返回值：成功返回0，失败返回其它值
+*/
+int zxdh_plcr_get_profile(struct zxdh_pf_device *pf_dev,
+						  E_PLCR_CAR_TYPE car_type, uint32_t pkt_sign,
+						  uint16_t profile_id,
+						  DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg)
+{
+	int rtn = 0;
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = pf_dev->slot_id;
+	pf_info.vport = pf_dev->vport;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	/*3. 将限速模板参数，配置到寄存器中去*/
+	rtn = dpp_car_profile_cfg_get(&pf_info, car_type, pkt_sign, profile_id,
+								  profile_cfg);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed to call dpp_car_profile_cfg_get()\n",
+				__FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+
+	return rtn;
+}
+EXPORT_SYMBOL(zxdh_plcr_get_profile);
+
+/*
+函数功能：配置指定CAR的限速模板：考虑plcr三级CAR能共享接口
+入参：
+	---pf_dev     : pf设备结构体
+	---car_type   : plcr CAR层级，一级，二级或三级
+	---flowid     : 指定CAR的flow编号
+	---profile_id : 申请到的指定CAR层级的profile资源的id
+返回值：成功返回0，失败返回其它值
+*/
+static int zxdh_plcr_bind_flow_profile(struct zxdh_pf_device *pf_dev,
+									   E_PLCR_CAR_TYPE car_type,
+									   uint32_t flowid, uint16_t profile_id)
+{
+	int rtn = 0;
+	struct zxdh_plcr_flow *plcr_flow;
+	struct xarray *xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]);
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = pf_dev->slot_id;
+	pf_info.vport = pf_dev->vport;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	/*1. 获取plcr*/
+	plcr_flow = xa_load(xarray_flow, flowid);
+	if (NULL == plcr_flow) {
+		LOG_ERR("%s-%d : xa_load an invalid element\n", __FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+
+	/*2. 调用接口，将flow与profile进行绑定*/
+	rtn = dpp_car_queue_cfg_set(&pf_info, (uint32_t)car_type, flowid,
+								DROP_DISABLE, PLCR_ENABLE, profile_id);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed to call dpp_car_queue_cfg_set()\n",
+				__FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+	LOG_INFO("%s-%d :Bind profile_%d to flow_%d complete\n", __FUNCTION__,
+			 __LINE__, profile_id, flowid);
+
+	/*3. 将profile_id更新到plcr中*/
+	plcr_flow->profile_id = profile_id;
+
+	return rtn;
+}
+
+/*
+函数功能：解除flow和profile之间的绑定 & 删除xarray中的元素 & 释放flow指针
+入参：
+	---pf_dev     : pf设备结构体
+	---car_type   : plcr CAR层级，一级，二级或三级
+	---flowid     : 指定CAR的flow编号
+	---profile_id : 申请到的指定CAR层级的profile资源的id
+返回值：成功返回0，失败返回其它值
+*/
+int zxdh_plcr_unbind_flow_profile(struct zxdh_pf_device *pf_dev,
+								  E_PLCR_CAR_TYPE car_type, uint32_t flowid,
+								  uint16_t profile_id)
+{
+	int rtn = 0;
+	struct zxdh_plcr_flow *plcr_flow;
+	struct xarray *xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]);
+	DPP_PF_INFO_T pf_info = { 0 };
+
+	pf_info.slot = pf_dev->slot_id;
+	pf_info.vport = pf_dev->vport;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	/*1. 检查flow是否与profile是否已绑定*/
+	plcr_flow = xa_load(xarray_flow, flowid);
+	if (NULL == plcr_flow) {
+		LOG_ERR("%s-%d : xa_load an invalid element\n", __FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+	if (profile_id != plcr_flow->profile_id) {
+		LOG_ERR("%s-%d : wrong profile id [%d - %d]\n", __FUNCTION__, __LINE__,
+				profile_id, plcr_flow->profile_id);
+		return -EINVAL;
+	}
+
+	/*调用接口，将flow与profile进行解除绑定：配置flow，将其不要指向profile*/
+	rtn = dpp_car_queue_cfg_set(&pf_info, (uint32_t)car_type, flowid,
+								DROP_DISABLE, PLCR_DISABLE, profile_id);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed to call dpp_car_queue_cfg_set()\n",
+				__FUNCTION__, __LINE__);
+		return rtn;
+	}
+
+	return rtn;
+}
+EXPORT_SYMBOL(zxdh_plcr_unbind_flow_profile);
+
+int zxdh_plcr_count_up_profile(struct zxdh_pf_device *pf_dev,
+							   E_PLCR_CAR_TYPE car_type, uint16_t profile_id)
+{
+	int rtn = 0;
+	struct zxdh_plcr_profile *plcr_profile;
+	struct xarray *xarray_profile =
+			&(pf_dev->plcr_table.plcr_profiles[car_type]);
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	plcr_profile = xa_load(xarray_profile, profile_id);
+	if (NULL == plcr_profile) {
+		LOG_ERR("%s-%d : failed to load element form xarray_profile\n",
+				__FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+
+	plcr_profile->ref_cnt++;
+
+	return rtn;
+}
+EXPORT_SYMBOL(zxdh_plcr_count_up_profile);
+
+int zxdh_plcr_count_down_profile(struct zxdh_pf_device *pf_dev,
+								 E_PLCR_CAR_TYPE car_type, uint16_t profile_id)
+{
+	int rtn = 0;
+	struct zxdh_plcr_profile *plcr_profile;
+	struct xarray *xarray_profile =
+			&(pf_dev->plcr_table.plcr_profiles[car_type]);
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+	plcr_profile = xa_load(xarray_profile, profile_id);
+	if (NULL == plcr_profile) {
+		LOG_ERR("%s-%d : failed to load element form xarray_profile\n",
+				__FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+
+	//不能对计数为0的profile进行减操作
+	if (0 == plcr_profile->ref_cnt) {
+		LOG_ERR("%s-%d : plcr_profile->ref_cnt=0\n", __FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+
+	plcr_profile->ref_cnt--;
+
+	return rtn;
+}
+EXPORT_SYMBOL(zxdh_plcr_count_down_profile);
+
+static int
+zxdh_plcr_get_profile_by_flowid(struct zxdh_pf_device *pf_dev,
+								E_PLCR_CAR_TYPE car_type, uint32_t flowid,
+								struct zxdh_plcr_profile **pplcr_profile)
+{
+	int rtn = 0;
+	uint16_t profile_id = 0;
+	struct zxdh_plcr_profile *plcr_profile;
+	struct zxdh_plcr_flow *plcr_flow;
+	struct xarray *xarray_profile =
+			&(pf_dev->plcr_table.plcr_profiles[car_type]);
+	struct xarray *xarray_flow = &(pf_dev->plcr_table.plcr_flows[car_type]);
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+	plcr_flow = xa_load(xarray_flow, flowid);
+	if (NULL == plcr_flow) {
+		LOG_ERR("%s-%d : failed to load element form xarray_flow\n",
+				__FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+	profile_id = plcr_flow->profile_id;
+
+	plcr_profile = xa_load(xarray_profile, profile_id);
+	if (NULL == plcr_profile) {
+		LOG_ERR("%s-%d : failed to load element form xarray_profile\n",
+				__FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+
+	*pplcr_profile = plcr_profile;
+
+	return rtn;
+}
+
+static int zxdh_plcr_create_rate_limit(struct zxdh_pf_device *pf_dev,
+									   E_PLCR_CAR_TYPE car_type, uint16_t vport,
+									   uint32_t flowid, uint32_t max_rate,
+									   uint32_t min_rate)
+{
+	int rtn = 0;
+	uint16_t profile_id = 0;
+	DPP_STAT_CAR_PROFILE_CFG_T profile_cfg;
+	struct zxdh_plcr_flow *plcr_flow = NULL;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	/*1. 对于一个先前还未限速的队列，如果限速值是0，这个限速配置操作无意义，就直接结束*/
+	if ((0 == max_rate) && (0 == min_rate)) {
+		LOG_ERR("%s-%d : invalid max_rate=%d on flowid=%d\n", __FUNCTION__,
+				__LINE__, max_rate, flowid);
+		return -EINVAL;
+	}
+
+	/*2. 申请flow结构体，并存储到xarray*/
+	rtn = zxdh_plcr_req_flow(pf_dev, car_type, flowid, &plcr_flow);
+	if (rtn) {
+		LOG_ERR("%s-%d : kzalloc failed\n", __FUNCTION__, __LINE__);
+		return -EINVAL;
+	}
+
+	/*3. 更新flow信息*/
+	zxdh_plcr_update_flow(plcr_flow, vport, max_rate, min_rate);
+
+	/*3. 根据限速值，生成限速模板配置参数*/
+	zxdh_plcr_gen_profile(car_type, max_rate, min_rate, &profile_cfg);
+
+	/*4. 查询是否有共享模板：没有共享限速模板，就要申请一个*/
+	rtn = zxdh_plcr_match_profile(pf_dev, car_type, &profile_cfg, &profile_id);
+	if (rtn) {
+		/*4.1 申请新的限速模板*/
+		rtn = zxdh_plcr_req_profile(pf_dev, car_type, &profile_id);
+		if (rtn) {
+			LOG_ERR("%s-%d : failed to call zxdh_plcr_req_profile()\n",
+					__FUNCTION__, __LINE__);
+			goto err3;
+		}
+
+		/*4.2 将profile_id更新到限速模板参数中去*/
+		zxdh_plcr_update_profile(&profile_cfg, profile_id);
+
+		/*4.3 将限速模板参数，配置到寄存器中去*/
+		rtn = zxdh_plcr_cfg_profile(pf_dev, car_type, &profile_cfg);
+		if (rtn) {
+			LOG_ERR("%s-%d : failed to call zxdh_plcr_cfg_profile()\n",
+					__FUNCTION__, __LINE__);
+			goto err2;
+		}
+
+		/*4.4 将限速模板配置参数，保存到zxdh_plcr_profile结构体*/
+		rtn = zxdh_plcr_store_profile(pf_dev, car_type, max_rate, min_rate,
+									  &profile_cfg);
+		if (rtn) {
+			LOG_ERR("%s-%d : failed to call zxdh_plcr_store_profile()\n",
+					__FUNCTION__, __LINE__);
+			goto err2;
+		}
+	}
+
+	/*5. 关联flow与profile*/
+	rtn = zxdh_plcr_bind_flow_profile(pf_dev, car_type, flowid, profile_id);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed to call zxdh_plcr_bind_flow_profile()\n",
+				__FUNCTION__, __LINE__);
+		goto err2;
+	}
+
+	/*6. 新模板使用计数+1*/
+	rtn = zxdh_plcr_count_up_profile(pf_dev, car_type, profile_id);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed to call zxdh_plcr_count_up_profile()\n",
+				__FUNCTION__, __LINE__);
+		goto err1;
+	}
+
+	return rtn;
+
+	/*7. 错误处理*/
+err1:
+	zxdh_plcr_unbind_flow_profile(pf_dev, car_type, flowid, profile_id);
+err2:
+	zxdh_plcr_release_profile(pf_dev, car_type, profile_id);
+err3:
+	zxdh_plcr_release_flow(pf_dev, car_type, flowid);
+
+	return rtn;
+}
+
+static int zxdh_plcr_modify_rate_limit(struct zxdh_pf_device *pf_dev,
+									   E_PLCR_CAR_TYPE car_type,
+									   uint32_t flowid, uint32_t max_rate,
+									   uint32_t min_rate)
+{
+	int rtn = 0;
+	uint16_t profile_id = 0;
+	DPP_STAT_CAR_PROFILE_CFG_T profile_cfg;
+	struct xarray *xarray_flowid = &(pf_dev->plcr_table.plcr_flows[car_type]);
+	struct zxdh_plcr_flow *plcr_flow = xa_load(xarray_flowid, flowid);
+	struct zxdh_plcr_profile *profile_old = NULL;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	/*1. 如果二次修改的限速值和原来的一样，这个配置操作无意义，直接结束*/
+	if (E_PLCR_CAR_A == car_type) {
+		if (plcr_flow->max_rate == max_rate) {
+			LOG_ERR("%s-%d : invalid max_rate=%d on flowid=%d\n", __FUNCTION__,
+					__LINE__, max_rate, flowid);
+			return -EINVAL;
+		}
+	} else if (E_PLCR_CAR_B == car_type) {
+		if ((plcr_flow->max_rate == max_rate) &&
+			(plcr_flow->min_rate == min_rate)) {
+			LOG_ERR("%s-%d : invalid max_rate=%d on flowid=%d\n", __FUNCTION__,
+					__LINE__, max_rate, flowid);
+			return -EINVAL;
+		}
+	}
+
+	/*2. 根据新的限速值，生成限速模板参数*/
+	zxdh_plcr_gen_profile(car_type, max_rate, min_rate, &profile_cfg);
+
+	/*3. 获取原来关联的限速模板*/
+	rtn = zxdh_plcr_get_profile_by_flowid(pf_dev, car_type, flowid,
+										  &profile_old);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed to call zxdh_plcr_get_profile_by_flowid()\n",
+				__FUNCTION__, __LINE__);
+		return rtn;
+	}
+
+	/*3. 不管原来的模板是不是共享模板，先查询有没有相同速率的限速模板*/
+	rtn = zxdh_plcr_match_profile(pf_dev, car_type, &profile_cfg, &profile_id);
+	if (rtn) {
+		/*3.1 没有找到能共享的限速模板*/
+
+		/*3.2 原来的模板不是共享模板：直接修改限速模板的限速值*/
+		if (1 == profile_old->ref_cnt) {
+			/*3.2.1 将profile_id更新到限速模板参数中去*/
+			zxdh_plcr_update_profile(&profile_cfg, profile_old->profile_id);
+
+			/*3.2.2 将限速模板的参数，配置到寄存器中去*/
+			rtn = zxdh_plcr_cfg_profile(pf_dev, car_type, &profile_cfg);
+			if (rtn) {
+				LOG_ERR("%s-%d : failed to call zxdh_plcr_cfg_profile()\n",
+						__FUNCTION__, __LINE__);
+				return rtn;
+			}
+
+			/*3.2.3 将限速模板配置参数，保存到zxdh_plcr_profile结构体*/
+			rtn = zxdh_plcr_store_profile(pf_dev, car_type, max_rate, min_rate,
+										  &profile_cfg);
+			if (rtn) {
+				LOG_ERR("%s-%d : failed to call zxdh_plcr_store_profile()\n",
+						__FUNCTION__, __LINE__);
+				return rtn;
+			}
+
+			/* 更新flow中记录的用户原始限速值，todo：是否使用bind函数，要考虑后期在哪里加锁*/
+			zxdh_plcr_update_flow(plcr_flow, plcr_flow->vport, max_rate,
+								  min_rate);
+
+			/*这种情况只修改限速模板的寄存器，flowid先前已经与profile绑定了*/
+			return rtn;
+		}
+
+		/*3.3 原来的限速模板是共享模板，所以要申请新的限速模板*/
+		rtn = zxdh_plcr_req_profile(pf_dev, car_type, &profile_id);
+		if (rtn) {
+			LOG_ERR("%s-%d : failed to call zxdh_plcr_req_profile()\n",
+					__FUNCTION__, __LINE__);
+			return rtn;
+		}
+
+		/*3.4 将profile_id更新到限速模板参数中去*/
+		zxdh_plcr_update_profile(&profile_cfg, profile_id);
+
+		/*3.5 将限速模板的参数，配置到寄存器中去*/
+		rtn = zxdh_plcr_cfg_profile(pf_dev, car_type, &profile_cfg);
+		if (rtn) {
+			LOG_ERR("%s-%d : failed to call zxdh_plcr_cfg_profile()\n",
+					__FUNCTION__, __LINE__);
+			goto err4;
+		}
+
+		/*3.6 将限速模板配置参数，保存到zxdh_plcr_profile结构体*/
+		rtn = zxdh_plcr_store_profile(pf_dev, car_type, max_rate, min_rate,
+									  &profile_cfg);
+		if (rtn) {
+			LOG_ERR("%s-%d : failed to call zxdh_plcr_store_profile()\n",
+					__FUNCTION__, __LINE__);
+			goto err4;
+		}
+
+		/*3.7 接下来的绑定流程，和下面是共享的*/
+	}
+	/*4. 查询到共享的限速模板：直接进行绑定即可*/
+	rtn = zxdh_plcr_bind_flow_profile(pf_dev, car_type, flowid, profile_id);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed to call zxdh_plcr_bind_flow_profile()\n",
+				__FUNCTION__, __LINE__);
+		goto err4;
+	}
+
+	/*5. 更新flow中记录的用户原始限速值*/
+	zxdh_plcr_update_flow(plcr_flow, plcr_flow->vport, max_rate, min_rate);
+
+	/*6. 新模板使用计数+1*/
+	rtn = zxdh_plcr_count_up_profile(pf_dev, car_type, profile_id);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed to call zxdh_plcr_count_up_profile()\n",
+				__FUNCTION__, __LINE__);
+		goto err4;
+	}
+
+	/*7. 旧的计数模板-1*/
+	rtn = zxdh_plcr_count_down_profile(pf_dev, car_type,
+									   profile_old->profile_id);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed to call zxdh_plcr_count_up_profile()\n",
+				__FUNCTION__, __LINE__);
+		goto err4;
+	}
+
+	zxdh_plcr_release_profile(pf_dev, car_type, profile_old->profile_id);
+
+	return rtn;
+
+err4: /*释放限速模板：如果引用技术为0，归还模板资源 & 删除xarray元素 &
+		释放profile指针；如果引用计数不为0，则什么也不做*/
+	zxdh_plcr_release_profile(pf_dev, car_type, profile_id);
+	return rtn;
+}
+
+int zxdh_plcr_remove_rate_limit(struct zxdh_pf_device *pf_dev,
+								E_PLCR_CAR_TYPE car_type, uint32_t flowid)
+{
+	int rtn = 0;
+	struct zxdh_plcr_profile *profile_old = NULL;
+
+	LOG_INFO("%s-%d:enter, car_type=%d\n", __FUNCTION__, __LINE__, car_type);
+
+	/* 获取原来关联的限速模板*/
+	rtn = zxdh_plcr_get_profile_by_flowid(pf_dev, car_type, flowid,
+										  &profile_old);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed to call zxdh_plcr_get_profile_by_flowid()\n",
+				__FUNCTION__, __LINE__);
+	}
+
+	if (NULL == profile_old) {
+		return -EINVAL;
+	}
+
+	/*解除绑定*/
+	rtn = zxdh_plcr_unbind_flow_profile(pf_dev, car_type, flowid,
+										profile_old->profile_id);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed to call zxdh_plcr_unbind_flow_profile()\n",
+				__FUNCTION__, __LINE__);
+	}
+
+	/*限速模板引用计数 -1*/
+	rtn = zxdh_plcr_count_down_profile(pf_dev, car_type,
+									   profile_old->profile_id);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed to call zxdh_plcr_count_down_profile()\n",
+				__FUNCTION__, __LINE__);
+	}
+
+	/*释放限速模板：如果引用计数为0，归还模板资源 & 删除xarray元素 &
+* 释放profile指针*/
+	rtn = zxdh_plcr_release_profile(pf_dev, car_type, profile_old->profile_id);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed to call zxdh_plcr_release_profile()\n",
+				__FUNCTION__, __LINE__);
+	}
+
+	/*释放掉flow*/
+	rtn = zxdh_plcr_release_flow(pf_dev, car_type, flowid);
+	if (rtn) {
+		LOG_ERR("%s-%d : failed\n", __FUNCTION__, __LINE__);
+	}
+
+	return rtn;
+}
+EXPORT_SYMBOL(zxdh_plcr_remove_rate_limit);
+
+void zxdh_plcr_count_profiles(struct zxdh_pf_device *pf_dev)
+{
+	struct zxdh_plcr_profile *profile;
+	unsigned long index;
+	uint32_t count, car_type = 0;
+	for (car_type = 0; car_type < 3; car_type++) {
+		count = 0;
+		xa_for_each_range(&(pf_dev->plcr_table.plcr_profiles[car_type]), index,
+						  profile, 0, gaudPlcrCarxProfileNum[car_type]) {
+			count++;
+		}
+		LOG_INFO("%s-%d:car_type = %d, profiles_num = %d\n", __FUNCTION__,
+				 __LINE__, car_type, count);
+	}
+
+	return;
+}
+EXPORT_SYMBOL(zxdh_plcr_count_profiles);
+
+int zxdh_plcr_set_rate_limit(struct zxdh_pf_device *pf_dev,
+							 E_PLCR_CAR_TYPE car_type, uint16_t vport,
+							 uint32_t flowid, uint32_t max_rate,
+							 uint32_t min_rate)
+{
+	int rtn = 0;
+	struct xarray *xarray_flowid = &(pf_dev->plcr_table.plcr_flows[car_type]);
+	struct zxdh_plcr_flow *plcr_flow_old = NULL;
+
+	LOG_INFO("%s-%d:enter\n", __FUNCTION__, __LINE__);
+
+	/*1. 判断该队列先前是否已经配置过限速值*/
+	plcr_flow_old = xa_load(xarray_flowid, flowid);
+	if (NULL == plcr_flow_old) {
+		/*1.1 初次配置限速值*/
+		rtn = zxdh_plcr_create_rate_limit(pf_dev, car_type, vport, flowid,
+										  max_rate, min_rate);
+	} else if ((max_rate != 0) || (min_rate != 0)) {
+		/*1.2 修改限速值*/
+		rtn = zxdh_plcr_modify_rate_limit(pf_dev, car_type, flowid, max_rate,
+										  min_rate);
+	} else {
+		/*1.3 解除限速：即，第二次配置，且max_rate=0，表示用户要解除限速*/
+		rtn = zxdh_plcr_remove_rate_limit(pf_dev, car_type, flowid);
+	}
+	zxdh_plcr_count_profiles(pf_dev);
+	return rtn;
+}
+EXPORT_SYMBOL(zxdh_plcr_set_rate_limit);
diff --git a/src/net/drivers/net/ethernet/dinghai/plcr.h b/src/net/drivers/net/ethernet/dinghai/plcr.h
index 981f0fa1796edb18b025b715a723db254be7e70a..9f11f509ffd213b17272f9c0ac62be4057f87d34 100644
--- a/src/net/drivers/net/ethernet/dinghai/plcr.h
+++ b/src/net/drivers/net/ethernet/dinghai/plcr.h
@@ -1,359 +1,250 @@
-#ifndef __ZXDH_QOS_H__
-#define __ZXDH_QOS_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/en_aux.h>
-#include <linux/dinghai/eq.h>
-#include <linux/compiler_types.h>
-#include <linux/types.h>
-#include "dpp_drv_qos.h"
-#include "en_sf.h"
-
-/* 注意：启用plcr会大幅度增加初始化时间 */
-// #define ZXDH_PLCR_OPEN
-// #define ZXDH_SRIOV_SYSFS_EN
-#ifdef ZXDH_PLCR_OPEN
-    #define ZXDH_PLCR_DEBUG
-#endif
-
-/*
-注意事项：将编码过程中的约定和需要关注的点列在这里
-1. vqm tx队列与CAR A的flow id映射关系：一一映射
-   vqm队列编号 0 - 4096，其中偶数队列为接收队列，奇数队列为发送队列；
-   所以，队列1,3,5,7,9等就是tx队列，它们对应的flow id就是1,3,5,7,9
-   这个映射转换，对应的接口是：static int zxdh_pf_qid_2_flowid(struct zxdh_en_device *en_dev, uint32_t qid)
-
-
-2.需要增加一个释放限速模板的接口
-  释放限速模板（模板计数操作与释放操作独立，释放的时候判断计数不为0就不释放，这样就能保证共享模板不被释放，新申请的会被释放）
-
-3.dpp相关的接口，里面进行pf与vf的判断
-
-4.错误打印，加上行号
-
-5.找孙泽明确认pcie_id和port_id的格式，参考链接：
-    https://i.zte.com.cn/#/space/4e62cb2b730540ff8721c1a8552b2356/wiki/page/ff8178f1304e45dc9457e92ff196cce5/view
-
-6. 考虑如何加锁
-
-7.如果用户只指定一个速率，iplink是如何获取到另外一个速率的？
-*/
-
-#define DROP_ENABLE       1
-#define DROP_DISABLE      0
-#define PLCR_ENABLE       1
-#define PLCR_DISABLE      0
-
-// #define DPP_CAR_PRI_MAX
-#define PLCR_STEP_SIZE    61u
-#define PLCR_MIN_RATE     1u
-#define PLCR_MAX_RATE     6875908u
-
-#define TXQ_MAX_BYTE_RATE PLCR_MAX_RATE / 1000 * PLCR_STEP_SIZE
-#define TXQ_MAX_PKT_RATE  0xFFFFFFFF //todo：不确定包限速最大限速值是多少
-
-#define CRED_ID(vport, car_type, profile_id) ((vport & 0xffff) << 20) | ((car_type & 0xf) << 16) | (profile_id & 0x1FF);
-#define PROFILE_ID(cred_id)  ((cred_id & 0x1FF))
-#define VQM_QUEUE_PAIRS_MAX_NUM 2048
-
-#define PLCR_CAR_A_PROFILE_RES_NUM 512
-#define PLCR_CAR_B_PROFILE_RES_NUM 128
-#define PLCR_CAR_C_PROFILE_RES_NUM 32
-
-#define PLCR_CAR_A_FLOWID_RES_NUM 10240
-#define PLCR_CAR_B_FLOWID_RES_NUM 2368 // 2304 + 64
-#define PLCR_CAR_C_FLOWID_RES_NUM 1024
-#define PLCR_CAR_B_PF_DEFAULT_FLOWID 2048
-
-#define PLCR_CAR_C_FLOWIDS_PER_EP 256
-#define PLCR_CAR_C_FLOWIDS_PER_PF 32
-
-//todo:实际调试时确定这个cbs的值;
-#define PLCR_CAR_PROFILE_GENERAL_CBS (14*1024*4)
-
-/********************************** definition of types **********************************/
-#define FLOWID_2_XARRAY(flowid)       ((flowid + 1)*8)
-#define XARRAY_2_FLOWID(flowid)       ((flowid / 8)-1)
-
-#define PLCR_INVALID_PARAM            0xffffffff
-#define PLCR_CAR_A_DPDK_FLOWID_OFFSET  8192
-#define PLCR_MAX_QUEUE_PAIRS           64
-#define PLCR_DEBUG
-
-#ifdef PLCR_DEBUG
-#define PLCR_FUNC_DBG_ENTER()\
-        LOG_INFO("%s-%d:enter !\n", __FUNCTION__, __LINE__)
-
-#define PLCR_LOG_INFO(fmt, arg...)\
-        LOG_INFO("%s-%d: ", __FUNCTION__, __LINE__)\
-        DH_LOG_INFO(MODULE_PF, fmt, ##arg)
-
-#define PLCR_LOG_ERR(fmt, arg...)\
-        LOG_INFO("%s-%d: ", __FUNCTION__, __LINE__)\
-        DH_LOG_ERR(MODULE_PF, fmt, ##arg)
-
-#define PLCR_COMM_ASSERT(rtn)\
-    do{\
-        if(0 != rtn)\
-        {\
-            PLCR_LOG_ERR("failed and rtn=0x%x\n", rtn)\
-            return rtn;\
-        }\
-    }while(0)
-#else
-#define PLCR_FUNC_DBG_ENTER()
-
-#define PLCR_LOG_INFO(fmt, arg...)
-
-#define PLCR_LOG_ERR(fmt, arg...)\
-        LOG_INFO("%s-%d: ", __FUNCTION__, __LINE__);\
-        DH_LOG_ERR(MODULE_PF, fmt, ##arg)
-
-#define PLCR_COMM_ASSERT(rtn)\
-    do{\
-        if(0 != rtn)\
-        {\
-            return rtn;\
-        }\
-    }while(0)
-#endif
-
-typedef enum
-{
-    PLCR_DEV_ALL_QID_2_FLOWID_QUEUE_PAIRS_OVERFLOW = 1,
-    PLCR_GET_REQ_TYPE_INVALID_ERR,
-
-    PLCR_CREATE_RATE_LIMIT_INVALID_OPERATION_ERR,
-    PLCR_MODIFY_RATE_LIMIT_INVALID_OPERATION_ERR,
-
-    PLCR_REMOVE_RATE_LIMIT,
-
-    PLCR_ERROR_NUM
-} E_PLCR_ERR_CODE;
-
-// Define the type of PLCR card
-typedef enum{
-    E_PLCR_CAR_A = 0,                  // PLCR card type A
-    E_PLCR_CAR_B = 1,                  // PLCR card type B
-    E_PLCR_CAR_C = 2,                  // PLCR card type C
-    E_PLCR_CAR_NUM = 3,                // Number of PLCR card types
-} E_PLCR_CAR_TYPE;
-
-// Define the union for PLCR profile configuration
-union zxdh_plcr_profile_cfg
-{
-    DPP_STAT_CAR_PROFILE_CFG_T      byte_profile_cfg;  // Byte rate limit profile configuration
-    DPP_STAT_CAR_PKT_PROFILE_CFG_T  pkt_profile_cfg;   // Packet rate limit profile configuration
-};
-
-typedef enum {
-    E_RATE_LIMIT_MODE0 = 0,            // mode 0:no limit
-    E_RATE_LIMIT_MODE1,                // mode 1:queue is mapped to car A flowid
-    E_RATE_LIMIT_MODE2,                // mode 2:vfid is mapped to car A flowid
-} E_RATE_LIMIT_MODE;
-
-typedef enum {
-    E_RATE_LIMIT_REQ_QUEUE_BYTE = 0,   // queue    byte   rate limit
-    E_RATE_LIMIT_REQ_VF_BYTE,          // vf       byte   rate limit
-    E_RATE_LIMIT_REQ_VF_GROUP_BYTE,    // vf group byte   rate limit
-    E_RATE_LIMIT_REQ_VF_PKT,           // vf       packet rate limit
-    E_RATE_LIMIT_REQ_MOVE_VF_GROUP,    //just to move vf to other group
-    E_RATE_LIMIT_REQ_TYPE_NUM,         //
-} E_RATE_LIMIT_REQ_TYPE;
-
-/* Define rate limit direction */
-typedef enum {
-    E_RATE_LIMIT_RX = 0,                   // Receive direction
-    E_RATE_LIMIT_TX,               // Send direction
-} E_RATE_LIMIT_DIRECTION;
-
-/* Define rate limit type */
-typedef enum {
-    E_RATE_LIMIT_BYTE = 0,             // Byte rate limit
-    E_RATE_LIMIT_PACKET,               // Packet rate limit
-} E_RATE_LIMIT_PKT_BYTE;
-
-/* Define the structure for rate limit parameters */
-typedef struct {
-    E_RATE_LIMIT_REQ_TYPE  req_type;   // Limit scope
-    E_RATE_LIMIT_DIRECTION direction;  // Limit direction
-    E_RATE_LIMIT_PKT_BYTE  mode;       // Limit mode
-    uint32_t max_rate;                 // Maximum rate limit
-    uint32_t min_rate;                 // Minimum rate limit
-    uint32_t queue_id;                 // Queue id
-    uint32_t vf_idx;                   // VF index in PF
-    uint32_t vfid;                     // VF id is global
-    uint32_t vport;                    // VF id is global
-    uint32_t group_id;                 // Group id
-} zxdh_plcr_rate_limit_paras;
-
-typedef struct {
-    uint16_t queue_pairs;
-    uint16_t flowids_A[2][PLCR_MAX_QUEUE_PAIRS];        // flowid in car A
-    uint16_t flowid_A[2];              // flowid in car A
-    uint16_t flowid_B[2];              // flowid in car B
-    uint16_t flowid_C[2];              // flowid in car C
-} zxdh_plcr_flowids;
-
-// Define the structure for PLCR profile
-struct zxdh_plcr_profile
-{
-    uint16_t ref_cnt;                  // Reference count
-    uint16_t profile_id;               // Profile ID
-    uint16_t vport;                    // Virtual port
-    uint32_t max_rate;                 // Maximum rate
-    uint32_t min_rate;                 // Minimum rate
-    uint64_t cred_id;                  // Credit ID
-    DPP_STAT_CAR_PROFILE_CFG_T profile_cfg; // Profile configuration
-};
-
-// Define the structure for PLCR flow
-struct zxdh_plcr_flow
-{
-    uint16_t vport;                    // Virtual port
-    uint16_t vf_id;                    // VF ID
-    uint16_t profile_id;               // Profile ID
-    uint16_t flowid;                   // flowid
-    uint16_t map_flowid;               // net car's flowid
-    uint16_t next_flowid;              // next car's flowid
-    uint32_t max_rate;                 // Maximum rate
-    uint32_t min_rate;                 // Minimum rate
-};
-
-struct dh_core_dev;
-struct zxdh_pf_device;
-struct zxdh_en_priv;
-
-typedef enum{
-    ZXDH_GROUP_RX_RATE = 0,
-    ZXDH_GROUP_TX_RATE = 1,
-}ZXDH_GROUP_DATA_TYPE;
-
-struct zxdh_group_obj
-{
-    struct zxdh_pf_device *pf_dev;
-    struct kobject kobj;
-    struct completion free_group_comp;
-
-    struct list_head list;
-    int32_t group_id;
-    int32_t num_vfs;
-    uint32_t max_tx_rate;
-    uint32_t max_rx_rate;
-};
-
-struct zxdh_group_work {
-	struct work_struct work;
-	struct zxdh_group_obj *group_obj;
-};
-
-typedef enum{
-    ZXDH_VF_MIN_RATE = 0,
-    ZXDH_VF_MAX_RATE = 1,
-}ZXDH_VF_METER_DATA_TYPE;
-
-typedef enum{
-    VF_METER_RX_BPS = 0,
-    VF_METER_RX_PPS = 1,
-    VF_METER_TX_BPS = 2,
-    VF_METER_TX_PPS = 3,
-    VF_METER_TYPE_NUM,
-}ZXDH_VF_METER_TYPE;
-
-#define IS_TX_METER(meter_type) (meter_type == VF_METER_TX_BPS || meter_type == VF_METER_TX_PPS)
-#define IS_PPS_METER(meter_type) (meter_type == VF_METER_RX_PPS || meter_type == VF_METER_TX_PPS)
-
-struct zxdh_vf_meter_obj
-{
-    struct zxdh_pf_device *pf_dev;
-    struct zxdh_vf_obj *vf_obj;
-    struct kobject kobj;
-    uint32_t meter_type;
-    uint32_t min_rate;
-    uint32_t max_rate;
-};
-
-struct zxdh_vf_meters
-{
-    struct kobject *kobj;
-    struct kobject *rx_obj;
-    struct kobject *tx_obj;
-    struct zxdh_vf_meter_obj xps[4];
-};
-
-struct zxdh_vf_obj
-{
-    struct zxdh_pf_device *pf_dev;
-    struct kobject kobj;
-    uint16_t vport;
-    uint16_t vf_idx;
-    struct zxdh_group_obj *group;
-    struct zxdh_vf_meters *meters;
-};
-
-struct zxdh_sriov_sysfs
-{
-    struct kobject *sriov_obj;
-#ifdef ZXDH_PLCR_DEBUG
-    struct kobj_attribute burst_attr;
-    struct kobj_attribute profile_attr;
-#endif
-    struct kobject *groups_obj;
-    struct zxdh_group_obj *group_0;
-    struct list_head groups_head;
-    struct zxdh_vf_obj *vfs;
-};
-
-struct zxdh_plcr_table {
-    struct xarray plcr_profiles[E_PLCR_CAR_NUM];          // Array of PLCR profiles(index = prfile id)
-    struct xarray plcr_flows[E_PLCR_CAR_NUM];             // Array of PLCR flows(index = flowid)
-    struct xarray plcr_maps[E_PLCR_CAR_NUM];              // Array of PLCR flows mapping relationship
-    uint32_t burst_size;
-};
-
-struct zxdh_plcr_cbs
-{
-    uint32_t min_rate;
-    uint32_t max_rate;
-    uint32_t cbs;
-};
-extern const uint32_t gaudPlcrCarxProfileNum[E_PLCR_CAR_NUM];
-extern const uint32_t gaudPlcrCarxFlowIdNum[E_PLCR_CAR_NUM];
-int zxdh_plcr_remove_rate_limit(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint32_t flowid);
-void zxdh_plcr_count_profiles(struct zxdh_pf_device *pf_dev);
-int zxdh_plcr_set_rate_limit(struct zxdh_pf_device *pf_dev, E_RATE_LIMIT_PKT_BYTE is_pkt_mode, E_PLCR_CAR_TYPE car_type, uint16_t vport, uint32_t flowid, uint32_t max_rate, uint32_t min_rate);
-int32_t zxdh_plcr_get_next_map(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint32_t  flowid, uint32_t *map_flowid);
-int32_t zxdh_plcr_init(struct zxdh_en_priv *en_priv);
-int32_t zxdh_plcr_uninit(struct zxdh_en_priv *en_priv);
-int zxdh_plcr_get_vport_vfid(struct zxdh_pf_device *pf_dev, uint32_t vf_idx, uint32_t *vport, uint32_t *vfid);
-int zxdh_plcr_req_profile(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint16_t *profile_id_out);
-int zxdh_plcr_release_profile(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint16_t profile_id);
-int zxdh_plcr_count_up_profile(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint16_t profile_id);
-int zxdh_plcr_count_down_profile(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint16_t profile_id);
-int zxdh_plcr_cfg_profile(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg);
-int zxdh_plcr_get_profile(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint32_t pkt_sign, uint16_t profile_id, DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg);
-uint32_t zxdh_plcr_reg_maxrate_user(uint32_t reg_maxrate);
-int32_t zxdh_plcr_req_flow(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint16_t flow_id, struct zxdh_plcr_flow **flow);
-int32_t zxdh_plcr_release_flow(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint16_t flow_id);
-void zxdh_plcr_update_flow(struct zxdh_plcr_flow *flow, uint16_t vport, uint32_t max_rate, uint32_t min_rate);
-int zxdh_plcr_store_profile(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint32_t user_max_rate, uint32_t user_min_rate, DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg);
-int32_t zxdh_plcr_stroe_map(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint32_t flowid, uint32_t map_flowid);
-int32_t zxdh_plcr_clear_map(struct zxdh_pf_device *pf_dev, E_PLCR_CAR_TYPE car_type, uint32_t flowid);
-int zxdh_plcr_get_mode(struct zxdh_pf_device *pf_dev, uint16_t vport, E_RATE_LIMIT_MODE *mode);
-int zxdh_plcr_set_mode(struct zxdh_pf_device *pf_dev, uint16_t vport, E_RATE_LIMIT_MODE mode);
-int zxdh_plcr_unified_set_rate_limit(struct zxdh_pf_device *pf_dev, zxdh_plcr_rate_limit_paras *rate_limit_paras);
-
-int zxdh_vf_update_sysfs_group(struct zxdh_pf_device *pf_dev, struct zxdh_vf_obj *vf, int32_t group_id);
-int zxdh_create_vfs_sysfs(struct dh_core_dev *dev, int32_t num_vfs);
-void zxdh_destroy_vfs_sysfs(struct dh_core_dev *dev, int32_t num_vfs);
-int zxdh_sriov_sysfs_init(struct dh_core_dev *dev);
-void zxdh_sriov_sysfs_exit(struct dh_core_dev *dev);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef __ZXDH_QOS_H__
+#define __ZXDH_QOS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/driver.h>
+#include <linux/dinghai/en_aux.h>
+#include <linux/dinghai/eq.h>
+#include <linux/compiler_types.h>
+#include <linux/types.h>
+#include "dpp_drv_qos.h"
+
+/* 注意：启用plcr会大幅度增加初始化时间 */
+// #define ZXDH_PLCR_OPEN 1
+// #define ZXDH_SRIOV_SYSFS_EN
+
+/*
+注意事项：将编码过程中的约定和需要关注的点列在这里
+1. vqm tx队列与CAR A的flow id映射关系：一一映射
+   vqm队列编号 0 - 4096，其中偶数队列为接收队列，奇数队列为发送队列；
+   所以，队列1,3,5,7,9等就是tx队列，它们对应的flow id就是1,3,5,7,9
+   这个映射转换，对应的接口是：static int zxdh_pf_qid_2_flowid(struct
+zxdh_en_device *en_dev, uint32_t qid)
+
+
+2.需要增加一个释放限速模板的接口
+  释放限速模板（模板计数操作与释放操作独立，释放的时候判断计数不为0就不释放，这样就能保证共享模板不被释放，新申请的会被释放）
+
+3.dpp相关的接口，里面进行pf与vf的判断
+
+4.错误打印，加上行号
+
+5.找孙泽明确认pcie_id和port_id的格式，参考链接：
+    https://i.zte.com.cn/#/space/4e62cb2b730540ff8721c1a8552b2356/wiki/page/ff8178f1304e45dc9457e92ff196cce5/view
+
+6. 考虑如何加锁
+
+7.如果用户只指定一个速率，iplink是如何获取到另外一个速率的？
+*/
+
+#define DROP_ENABLE 1
+#define DROP_DISABLE 0
+#define PLCR_ENABLE 1
+#define PLCR_DISABLE 0
+#define BYTE_RATE_LIMIT 0
+#define PACKET_RATE_LIMIT 1
+
+// #define DPP_CAR_PRI_MAX   0xfffff //todo:还不知道是多少
+#define PLCR_STEP_SIZE 61u
+#define PLCR_MIN_RATE 1u
+#define PLCR_MAX_RATE 6875908u
+
+#define TXQ_MAX_RATE (PLCR_MAX_RATE / 1000 * PLCR_STEP_SIZE)
+
+#define CRED_ID(vport, car_type, profile_id)                  \
+	do {                                                      \
+		((vport & 0xffff) << 20) | ((car_type & 0xf) << 16) | \
+				(profile_id & 0x1FF);                         \
+	}                                                         \
+	while (0)
+#define PROFILE_ID(cred_id) ((cred_id & 0x1FF))
+#define VQM_QUEUE_PAIRS_MAX_NUM 2048
+
+#define PLCR_CAR_A_PROFILE_RES_NUM 512
+#define PLCR_CAR_B_PROFILE_RES_NUM 128
+#define PLCR_CAR_C_PROFILE_RES_NUM 32
+
+#define PLCR_CAR_A_FLOWID_RES_NUM 10239 // 0-4095, 8192-10239
+#define PLCR_CAR_B_FLOWID_RES_NUM 2048
+#define PLCR_CAR_C_FLOWID_RES_NUM 512
+
+#define PLCR_CAR_B_FLOWID_FOR_INIT 2048
+#define PLCR_CAR_A_PROFILE_DAFAULT 511
+
+	/*PLCR有3级CAR*/
+	typedef enum {
+		E_PLCR_CAR_A = 0,
+		E_PLCR_CAR_B = 1,
+		E_PLCR_CAR_C = 2,
+		E_PLCR_CAR_NUM = 3,
+	} E_PLCR_CAR_TYPE;
+
+/*字节限速和包限速联合体*/
+union zxdh_plcr_profile_cfg {
+	DPP_STAT_CAR_PROFILE_CFG_T byte_profile_cfg; //字节限速模板
+	DPP_STAT_CAR_PKT_PROFILE_CFG_T pkt_profile_cfg; //包限速模板
+};
+
+/*限速模板的信息*/
+struct zxdh_plcr_profile {
+	uint16_t ref_cnt; //引用计数，为0时可以释放
+	uint16_t profile_id; //限速模板的id
+	uint16_t vport; //申请时使用的vport
+	uint32_t max_rate; //限速模板的速率
+	uint32_t min_rate; //限速模板的速率
+	uint64_t cred_id; //申请时的凭证
+	DPP_STAT_CAR_PROFILE_CFG_T profile_cfg; //限速模板的所有参数
+};
+
+/*plcr flowid的信息*/
+struct zxdh_plcr_flow {
+	uint16_t vport;
+	uint16_t vf_id;
+	uint16_t profile_id;
+	uint32_t max_rate;
+	uint32_t min_rate;
+};
+
+struct dh_core_dev;
+struct zxdh_pf_device;
+struct zxdh_en_priv;
+
+typedef enum {
+	ZXDH_GROUP_RX_RATE = 0,
+	ZXDH_GROUP_TX_RATE = 1,
+} ZXDH_GROUP_DATA_TYPE;
+
+struct zxdh_group_obj {
+	struct zxdh_pf_device *pf_dev;
+	struct kobject kobj;
+	struct completion free_group_comp;
+
+	struct list_head list;
+	int32_t group_id;
+	int32_t num_vfs;
+	uint32_t max_tx_rate;
+	uint32_t max_rx_rate;
+};
+
+struct zxdh_group_work {
+	struct work_struct work;
+	struct zxdh_group_obj *group_obj;
+};
+
+typedef enum {
+	ZXDH_VF_MIN_RATE = 0,
+	ZXDH_VF_MAX_RATE = 1,
+} ZXDH_VF_METER_DATA_TYPE;
+
+typedef enum {
+	VF_METER_RX_BPS = 0,
+	VF_METER_RX_PPS = 1,
+	VF_METER_TX_BPS = 2,
+	VF_METER_TX_PPS = 3,
+} ZXDH_VF_METER_TYPE;
+
+#define IS_TX_METER(meter_type) \
+	(meter_type == VF_METER_TX_BPS || meter_type == VF_METER_TX_PPS)
+#define IS_PPS_METER(meter_type) \
+	(meter_type == VF_METER_RX_PPS || meter_type == VF_METER_TX_PPS)
+
+struct zxdh_vf_meter_obj {
+	struct zxdh_pf_device *pf_dev;
+	struct zxdh_vf_obj *vf_obj;
+	struct kobject kobj;
+	uint32_t meter_type;
+	uint32_t min_rate;
+	uint32_t max_rate;
+};
+
+struct zxdh_vf_meters {
+	struct kobject *kobj;
+	struct kobject *rx_obj;
+	struct kobject *tx_obj;
+	struct zxdh_vf_meter_obj xps[4];
+};
+
+struct zxdh_vf_obj {
+	struct zxdh_pf_device *pf_dev;
+	struct kobject kobj;
+	uint16_t vport;
+	uint16_t vf_idx;
+	struct zxdh_group_obj *group;
+	struct zxdh_vf_meters *meters;
+};
+
+struct zxdh_sriov_sysfs {
+	struct kobject *sriov_obj;
+	struct kobject *groups_obj;
+	struct zxdh_group_obj *group_0;
+	struct list_head groups_head;
+	struct zxdh_vf_obj *vfs;
+};
+
+struct zxdh_plcr_table {
+	struct xarray plcr_profiles
+			[E_PLCR_CAR_NUM]; /*记录本vf在三级CAR中申请使用了哪些限速模板*/
+	struct xarray
+			plcr_flows[E_PLCR_CAR_NUM]; /*记录本vf在三级CAR中有哪些flowid申请限速*/
+};
+
+extern const uint32_t gaudPlcrCarxFlowIdNum[E_PLCR_CAR_NUM];
+
+uint zxdh_plcr_vf_qid_2_flowid(struct zxdh_en_priv *en_priv, uint32_t qid);
+int zxdh_plcr_remove_rate_limit(struct zxdh_pf_device *pf_dev,
+								E_PLCR_CAR_TYPE car_type, uint32_t flowid);
+void zxdh_plcr_count_profiles(struct zxdh_pf_device *pf_dev);
+int zxdh_plcr_set_rate_limit(struct zxdh_pf_device *pf_dev,
+							 E_PLCR_CAR_TYPE car_type, uint16_t vport,
+							 uint32_t flowid, uint32_t max_rate,
+							 uint32_t min_rate);
+int32_t zxdh_plcr_init(struct zxdh_en_priv *en_priv);
+int32_t zxdh_plcr_uninit(struct zxdh_en_priv *en_priv);
+int zxdh_map_flowid(struct zxdh_en_priv *en_priv, E_PLCR_CAR_TYPE car_type,
+					uint32_t specified_flow_id);
+int zxdh_plcr_req_profile(struct zxdh_pf_device *pf_dev,
+						  E_PLCR_CAR_TYPE car_type, uint16_t *profile_id_out);
+int zxdh_plcr_release_profile(struct zxdh_pf_device *pf_dev,
+							  E_PLCR_CAR_TYPE car_type, uint16_t profile_id);
+int zxdh_plcr_count_up_profile(struct zxdh_pf_device *pf_dev,
+							   E_PLCR_CAR_TYPE car_type, uint16_t profile_id);
+int zxdh_plcr_count_down_profile(struct zxdh_pf_device *pf_dev,
+								 E_PLCR_CAR_TYPE car_type, uint16_t profile_id);
+int zxdh_plcr_cfg_profile(struct zxdh_pf_device *pf_dev,
+						  E_PLCR_CAR_TYPE car_type,
+						  DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg);
+int zxdh_plcr_get_profile(struct zxdh_pf_device *pf_dev,
+						  E_PLCR_CAR_TYPE car_type, uint32_t pkt_sign,
+						  uint16_t profile_id,
+						  DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg);
+uint32_t zxdh_plcr_calc_maxrate_cfg(uint32_t max_rate);
+uint32_t zxdh_plcr_calc_user_maxrate_cfg(uint32_t maxrate_cfg);
+int32_t zxdh_plcr_req_flow(struct zxdh_pf_device *pf_dev,
+						   E_PLCR_CAR_TYPE car_type, uint16_t flow_id,
+						   struct zxdh_plcr_flow **flow);
+int32_t zxdh_plcr_release_flow(struct zxdh_pf_device *pf_dev,
+							   E_PLCR_CAR_TYPE car_type, uint16_t flow_id);
+void zxdh_plcr_update_flow(struct zxdh_plcr_flow *flow, uint16_t vport,
+						   uint32_t max_rate, uint32_t min_rate);
+int zxdh_plcr_unbind_flow_profile(struct zxdh_pf_device *pf_dev,
+								  E_PLCR_CAR_TYPE car_type, uint32_t flowid,
+								  uint16_t profile_id);
+int zxdh_plcr_store_profile(struct zxdh_pf_device *pf_dev,
+							E_PLCR_CAR_TYPE car_type, uint32_t max_rate,
+							uint32_t min_rate,
+							DPP_STAT_CAR_PROFILE_CFG_T *profile_cfg);
+int zxdh_vf_update_sysfs_group(struct zxdh_pf_device *pf_dev,
+							   struct zxdh_vf_obj *vf, int32_t group_id);
+int zxdh_create_vfs_sysfs(struct dh_core_dev *dev, int32_t num_vfs);
+void zxdh_destroy_vfs_sysfs(struct dh_core_dev *dev, int32_t num_vfs);
+int zxdh_sriov_sysfs_init(struct dh_core_dev *dev);
+void zxdh_sriov_sysfs_exit(struct dh_core_dev *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/sriov_sysfs.c b/src/net/drivers/net/ethernet/dinghai/sriov_sysfs.c
index 9c34f26177f1a855da85550044c02ab73901f345..1eed8c0585f7c892e637cac1adb1b2e8f5f697c5 100644
--- a/src/net/drivers/net/ethernet/dinghai/sriov_sysfs.c
+++ b/src/net/drivers/net/ethernet/dinghai/sriov_sysfs.c
@@ -1,1483 +1,1109 @@
-#include <linux/dinghai/auxiliary_bus.h>
-#include <linux/dinghai/driver.h>
-#include <net/udp_tunnel.h>
-#include <linux/dinghai/dh_cmd.h>
-#include <linux/netdevice.h>
-#include "en_aux.h"
-#include <linux/etherdevice.h>
-#include "en_np/table/include/dpp_tbl_api.h"
-#include "en_aux/en_cmd.h"
-#include "msg_common.h"
-#include "en_pf.h"
-#include <linux/dinghai/kcompat.h>
-#ifdef TIME_STAMP_1588
-#include "en_aux/en_1588_pkt_proc.h"
-#endif
-#include <linux/kobject.h>
-#include <linux/string.h>
-#include <linux/sysfs.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/init.h>
-
-
-#define ZXDH_DEFAULT_VF_GROUP_ID 0
-#define ZXDH_MAX_VF_GROUP_OBJ_ID 255
-#define ZXDH_MAX_VF_GROUP_OBJ_NUM (ZXDH_MAX_VF_GROUP_OBJ_ID + 1)
-#define ZXDH_MAX_VF_OBJ_ID 255
-#define ZXDH_MAX_VF_OBJ_NUM (ZXDH_MAX_VF_OBJ_ID + 1)
-
-
-/************************************************
- * sriov attr：
- *   burst: WO，配置当前PF的流量突发尺寸
- *   profile: RO，打印当前PF对三级car的profile占用情况
-************************************************/
-
-
-/************************************************
- * group attr：
- *   config: RO，打印当前vf端口组所有配置
- *   max_rx_rate: WO，配置当前vf端口组最大接收速率
- *   max_tx_rate: WO，配置当前vf端口组最大发送速率
-************************************************/
-
-
-/************************************************
- * vf attr：
- * config: RO，打印当前vf所有配置
- * group: WO，指定当前vf端口所属group，默认group-0
- * meter
- *   rx
- *      bps
- *          max_rate: WO，配置当前vf端口接收方向字节限速
- *          min_rate: WO，配置当前vf端口接收方向字节最小保障带宽
- *          pkt_dropped: RO, 查询丢包数量/字节数
- *      pps
- *          rate: WO，配置当前vf端口接收方向包限速
- *          pkt_dropped: RO, 查询丢包数量/字节数
- *   tx
- *      bps
- *          max_rate: WO，配置当前vf端口发送方向字节限速
- *          max_rate: WO，配置当前vf端口发送方向字节最小保障带宽
- *          pkt_dropped: RO, 查询丢包数量/字节数
-
- *      pps
- *          pps_rate: WO，配置当前vf端口发送方向包限速
- *          pkt_dropped: RO, 查询丢包数量/字节数
-************************************************/
-
-
-struct zxdh_group_attribute {
-    struct attribute attr;
-    ssize_t (*show)(struct zxdh_group_obj *group,
-                    struct zxdh_group_attribute *attr, char *buf);
-    ssize_t (*store)(struct zxdh_group_obj *group,
-                    struct zxdh_group_attribute *attr, const char *buf, size_t count);
-};
-
-#define to_zxdh_group_attr(x) container_of(x, struct zxdh_group_attribute, attr)
-#define to_zxdh_group_obj(x) container_of(x, struct zxdh_group_obj, kobj)
-
-struct zxdh_vf_attribute {
-    struct attribute attr;
-    ssize_t (*show)(struct zxdh_vf_obj *vf,
-                    struct zxdh_vf_attribute *attr, char *buf);
-    ssize_t (*store)(struct zxdh_vf_obj *vf,
-                    struct zxdh_vf_attribute *attr, const char *buf, size_t count);
-};
-
-#define to_zxdh_vf_attr(x) container_of(x, struct zxdh_vf_attribute, attr)
-#define to_zxdh_vf_obj(x) container_of(x, struct zxdh_vf_obj, kobj)
-
-struct zxdh_vf_meter_attribute {
-    struct attribute attr;
-    ssize_t (*show)(struct zxdh_vf_meter_obj *xps,
-                    struct zxdh_vf_meter_attribute *attr, char *buf);
-    ssize_t (*store)(struct zxdh_vf_meter_obj *xps,
-                    struct zxdh_vf_meter_attribute *attr, const char *buf, size_t count);
-};
-
-#define to_zxdh_vf_meter_attr(x) container_of(x, struct zxdh_vf_meter_attribute, attr)
-#define to_zxdh_vf_meter_obj(x) container_of(x, struct zxdh_vf_meter_obj, kobj)
-
-/*
- * The default show function that must be passed to sysfs.  This will be
- * called by sysfs for whenever a show function is called by the user on a
- * sysfs file associated with the kobjects we have registered.  We need to
- * transpose back from a "default" kobject to our custom struct foo_obj and
- * then call the show function for that specific object.
- */
-static ssize_t zxdh_group_attr_show(struct kobject *kobj,
-                 struct attribute *attr,
-                 char *buf)
-{
-    struct zxdh_group_attribute *attribute;
-    struct zxdh_group_obj *group;
-
-    attribute = to_zxdh_group_attr(attr);
-    group = to_zxdh_group_obj(kobj);
-
-    if (!attribute->show)
-        return -EIO;
-
-    return attribute->show(group, attribute, buf);
-}
-
-/*
- * Just like the default show function above, but this one is for when the
- * sysfs "store" is requested (when a value is written to a file.)
- */
-static ssize_t zxdh_group_attr_store(struct kobject *kobj,
-                  struct attribute *attr,
-                  const char *buf, size_t len)
-{
-    struct zxdh_group_attribute *attribute;
-    struct zxdh_group_obj *group;
-
-    attribute = to_zxdh_group_attr(attr);
-    group = to_zxdh_group_obj(kobj);
-
-    if (!attribute->store)
-        return -EIO;
-
-    return attribute->store(group, attribute, buf, len);
-}
-
-static ssize_t zxdh_vf_attr_show(struct kobject *kobj,
-                 struct attribute *attr,
-                 char *buf)
-{
-    struct zxdh_vf_attribute *attribute;
-    struct zxdh_vf_obj *vf;
-
-    attribute = to_zxdh_vf_attr(attr);
-    vf = to_zxdh_vf_obj(kobj);
-
-    if (!attribute->show)
-        return -EIO;
-
-    return attribute->show(vf, attribute, buf);
-}
-
-static ssize_t zxdh_vf_attr_store(struct kobject *kobj,
-                  struct attribute *attr,
-                  const char *buf, size_t len)
-{
-    struct zxdh_vf_attribute *attribute;
-    struct zxdh_vf_obj *vf;
-
-    attribute = to_zxdh_vf_attr(attr);
-    vf = to_zxdh_vf_obj(kobj);
-
-    if (!attribute->store)
-        return -EIO;
-
-    return attribute->store(vf, attribute, buf, len);
-}
-
-static ssize_t zxdh_vf_meter_attr_show(struct kobject *kobj,
-                 struct attribute *attr,
-                 char *buf)
-{
-    struct zxdh_vf_meter_attribute *attribute;
-    struct zxdh_vf_meter_obj *xps;
-
-    attribute = to_zxdh_vf_meter_attr(attr);
-    xps = to_zxdh_vf_meter_obj(kobj);
-
-    if (!attribute->show)
-        return -EIO;
-
-    return attribute->show(xps, attribute, buf);
-}
-
-static ssize_t zxdh_vf_meter_attr_store(struct kobject *kobj,
-                  struct attribute *attr,
-                  const char *buf, size_t len)
-{
-    struct zxdh_vf_meter_attribute *attribute;
-    struct zxdh_vf_meter_obj *xps;
-
-    attribute = to_zxdh_vf_meter_attr(attr);
-    xps = to_zxdh_vf_meter_obj(kobj);
-
-    if (!attribute->store)
-        return -EIO;
-
-    return attribute->store(xps, attribute, buf, len);
-}
-
-/* Our custom sysfs_ops that we will associate with our ktype later on */
-static const struct sysfs_ops zxdh_group_sysfs_ops = {
-    .show = zxdh_group_attr_show,
-    .store = zxdh_group_attr_store,
-};
-
-static const struct sysfs_ops zxdh_vf_sysfs_ops = {
-    .show = zxdh_vf_attr_show,
-    .store = zxdh_vf_attr_store,
-};
-
-static const struct sysfs_ops zxdh_vf_meter_sysfs_ops = {
-    .show = zxdh_vf_meter_attr_show,
-    .store = zxdh_vf_meter_attr_store,
-};
-
-/*
- * The release function for our object.  This is REQUIRED by the kernel to
- * have.  We free the memory held in our object here.
- *
- * NEVER try to get away with just a "blank" release function to try to be
- * smarter than the kernel.  Turns out, no one ever is...
- */
-/*static void zxdh_group_release(struct kobject *kobj)
-{
-    struct zxdh_group_obj *group;
-
-    LOG_INFO("enter\n");
-    group = to_zxdh_group_obj(kobj);
-    kfree(group);
-}
-
-static void zxdh_vf_release(struct kobject *kobj)
-{
-    struct zxdh_vf_obj *vf;
-
-    LOG_INFO("enter\n");
-    vf = to_zxdh_vf_obj(kobj);
-    kfree(vf);
-}
-
-static void zxdh_vf_meter_release(struct kobject *kobj)
-{
-    struct zxdh_vf_meter_obj *xps;
-
-    LOG_INFO("enter\n");
-    xps = to_zxdh_vf_meter_obj(kobj);
-    kfree(xps);
-}*/
-
-#define _sprintf(p, buf, format, arg...)                \
-    ((PAGE_SIZE - (int)(p - buf)) <= 0 ? 0 :            \
-    scnprintf(p, PAGE_SIZE - (int)(p - buf), format, ## arg))
-
-#ifdef ZXDH_PLCR_DEBUG
-static ssize_t zxdh_burst_show(struct kobject *kobj,
-            struct kobj_attribute *attr, char *buf)
-{
-    struct zxdh_pf_device *pf_dev;
-    struct zxdh_sriov_sysfs *sriov;
-
-    LOG_INFO("enter\n");
-    sriov = container_of(attr, struct zxdh_sriov_sysfs, burst_attr);
-    pf_dev = container_of(sriov, struct zxdh_pf_device, sriov);
-
-    return sysfs_emit(buf,
-            "the burst size = %d\n", pf_dev->plcr_table.burst_size);
-}
-
-static ssize_t zxdh_burst_store(struct kobject *kobj,
-            struct kobj_attribute *attr, const char *buf, size_t count)
-{
-    int rtn = 0;
-    uint32_t burst;
-    struct zxdh_pf_device *pf_dev;
-    struct zxdh_sriov_sysfs *sriov;
-
-    LOG_INFO("enter\n");
-    sriov = container_of(attr, struct zxdh_sriov_sysfs, burst_attr);
-    pf_dev = container_of(sriov, struct zxdh_pf_device, sriov);
-
-	rtn = kstrtoint(buf, 10, &burst);
-    if (rtn)
-		return rtn;
-
-    /* When the burst changes, the rate limit of the specified flow needs
-        to be reconfigured to update its burst.
-       The scope of the burst includes the current PF and its associated VFs.
-	   Write 0 to set the burst to the default value.*/
-
-    pf_dev->plcr_table.burst_size = burst;
-
-    return count;
-}
-
-static ssize_t zxdh_profile_stat_show(struct kobject *kobj,
-            struct kobj_attribute *attr, char *buf)
-{
-    struct zxdh_sriov_sysfs *sriov = container_of(attr, struct zxdh_sriov_sysfs, profile_attr);
-    struct zxdh_pf_device *pf_dev = container_of(sriov, struct zxdh_pf_device, sriov);
-    struct zxdh_plcr_profile *profile;
-    unsigned long index;
-    uint32_t count = 0;
-    E_PLCR_CAR_TYPE car_type;
-    char *p = buf;
-
-    LOG_INFO("enter\n");
-    for (car_type = E_PLCR_CAR_A; car_type < E_PLCR_CAR_NUM; car_type ++)
-    {
-        count = 0;
-        xa_for_each_range(&(pf_dev->plcr_table.plcr_profiles[car_type]), index,
-                            profile, 0, gaudPlcrCarxProfileNum[car_type])
-        {
-            count++;
-        }
-        p += _sprintf(p, buf, "car_type = %d, profiles_num = %d\n", car_type, count);
-    }
-    return (ssize_t)(p - buf);
-}
-#endif
-
-#ifdef ZXDH_PLCR_OPEN
-static uint16_t zxdh_group_to_flowid(struct zxdh_group_obj *group, int32_t data_type)
-{
-    uint16_t flowid;
-    uint16_t vport = group->pf_dev->vport;
-    int32_t group_id = group->group_id;
-    int32_t global_group_id;
-
-    global_group_id = EPID(vport) * 128 + FUNC_NUM(vport) * 16 + group_id;
-    flowid = (data_type == ZXDH_GROUP_TX_RATE) ?
-                (global_group_id * 2 + 1) : (global_group_id * 2);
-
-    return flowid;
-}
-
-static uint16_t zxdh_vport_to_flowid(uint16_t vport, int32_t req_type, int32_t direction)
-{
-    uint16_t vfid;
-    uint16_t flowid;
-
-    LOG_INFO("enter\n");
-    vfid = VQM_VFID(vport);
-    if (req_type == E_RATE_LIMIT_BYTE)
-    {
-        flowid = direction ? (vfid * 2 + 1) : (vfid * 2);
-    }
-    else if (req_type == E_RATE_LIMIT_PACKET)
-    {
-        flowid = direction ? (vfid * 2 + 1) : (vfid * 2) + PLCR_CAR_A_DPDK_FLOWID_OFFSET;
-    }
-
-    return flowid;
-}
-
-static uint32_t zxdh_vf_meter_obj_to_flowid(struct zxdh_vf_meter_obj *xps)
-{
-    uint16_t vport;
-    uint16_t vfid;
-    uint16_t flowid;
-
-    LOG_INFO("enter\n");
-    vport = xps->vf_obj->vport;
-    vfid = VQM_VFID(vport);
-    flowid = IS_TX_METER(xps->meter_type) ? (vfid * 2 + 1) : (vfid * 2);
-
-    return flowid;
-}
-
-static int zxdh_set_vf_group_rate_limit(struct zxdh_group_obj *group, int32_t direction, uint32_t max_rate)
-{
-    int rtn = 0;
-    zxdh_plcr_rate_limit_paras rate_limit_paras;
-
-    LOG_INFO("enter\n");
-
-    // en_priv = pf_dev_get_en_priv(group->pf_dev);
-    // if (IS_ERR(en_priv))
-    //     return PTR_ERR(en_priv);
-
-    rate_limit_paras.req_type  = E_RATE_LIMIT_REQ_VF_GROUP_BYTE;
-    rate_limit_paras.direction = direction; // rx:0, tx:1
-    rate_limit_paras.mode      = E_RATE_LIMIT_BYTE;
-    rate_limit_paras.max_rate  = max_rate;
-    rate_limit_paras.min_rate  = PLCR_INVALID_PARAM;
-
-    rate_limit_paras.queue_id  = PLCR_INVALID_PARAM;
-    rate_limit_paras.vf_idx    = PLCR_INVALID_PARAM;
-    rate_limit_paras.vfid      = PLCR_INVALID_PARAM;
-    rate_limit_paras.group_id  = group->group_id;
-
-    rtn = zxdh_plcr_unified_set_rate_limit(group->pf_dev, &rate_limit_paras);
-    PLCR_COMM_ASSERT(rtn);
-
-    return rtn;
-}
-
-static int zxdh_move_vf_to_group(struct zxdh_vf_obj *vf, struct zxdh_group_obj *group)
-{
-    int rtn = 0;
-    zxdh_plcr_rate_limit_paras rate_limit_paras;
-
-    LOG_INFO("enter\n");
-    rate_limit_paras.req_type  = E_RATE_LIMIT_REQ_MOVE_VF_GROUP;
-    rate_limit_paras.direction = E_RATE_LIMIT_RX;
-    rate_limit_paras.mode      = PLCR_INVALID_PARAM;
-    rate_limit_paras.max_rate  = PLCR_INVALID_PARAM;
-    rate_limit_paras.min_rate  = PLCR_INVALID_PARAM;
-
-    rate_limit_paras.queue_id  = PLCR_INVALID_PARAM;
-    rate_limit_paras.vf_idx    = vf->vf_idx;
-    rate_limit_paras.vfid      = PLCR_INVALID_PARAM;
-    rate_limit_paras.group_id  = group->group_id;
-
-    rtn = zxdh_plcr_unified_set_rate_limit(vf->pf_dev, &rate_limit_paras);
-    PLCR_COMM_ASSERT(rtn);
-
-    rate_limit_paras.direction = E_RATE_LIMIT_TX;
-    rtn = zxdh_plcr_unified_set_rate_limit(vf->pf_dev, &rate_limit_paras);
-    PLCR_COMM_ASSERT(rtn);
-    // todo:由plcr代码处理
-    // if (rtn)
-    // {
-    //     PLCR_LOG_ERR("failed and rtn=0x%x\n", rtn)
-
-    //     rate_limit_paras.direction = E_RATE_LIMIT_RX;
-        // rate_limit_paras.group_id  = vf->group->group_id;
-    //     zxdh_plcr_unified_set_rate_limit(vf->pf_dev, &rate_limit_paras);
-    // }
-
-    return rtn;
-}
-#endif
-
-static ssize_t zxdh_group_max_rate_store(struct zxdh_group_obj *group,
-             struct zxdh_group_attribute *attr, const char *buf,
-             size_t count, int32_t direction)
-{
-    int32_t max_rate;
-    // uint16_t flowid;
-    int rtn = 0;
-    LOG_INFO("enter\n");
-
-    if (group == group->pf_dev->sriov.group_0)
-        return -EINVAL;
-
-    rtn = kstrtoint(buf, 10, &max_rate);
-    if (rtn < 0)
-        return -EINVAL;
-    LOG_INFO("max_%s_rate = %d\n", direction ? "tx" : "rx", max_rate);
-
-    if ((direction ? group->max_tx_rate : group->max_rx_rate) == max_rate)
-        return -EINVAL;
-
-    // flowid = zxdh_group_to_flowid(group, direction);
-
-#ifdef ZXDH_PLCR_OPEN
-    //调用限速统一接口，配置vf group限速
-    rtn = zxdh_set_vf_group_rate_limit(group, direction, max_rate);
-    if (rtn)
-        return rtn;
-
-    PLCR_LOG_INFO("The Max %s Rate of group%d has been set to %d Mbit/s\n",
-            direction ? "Tx" : "Rx", group->group_id, max_rate);
-#endif
-
-    if (direction == ZXDH_GROUP_TX_RATE)
-        group->max_tx_rate = max_rate;
-    else
-        group->max_rx_rate = max_rate;
-
-    return rtn ? rtn : count;
-}
-
-static ssize_t zxdh_group_max_rx_rate_show(struct zxdh_group_obj *group,
-             struct zxdh_group_attribute *attr, char *buf)
-{
-
-    LOG_INFO("enter\n");
-    return sysfs_emit(buf,
-               "usage: write <Rate (Mbit/s)> to set VF group max rx rate\n");
-}
-
-static ssize_t zxdh_group_max_rx_rate_store(struct zxdh_group_obj *group,
-             struct zxdh_group_attribute *attr, const char *buf, size_t count)
-{
-    return zxdh_group_max_rate_store(group, attr, buf, count, ZXDH_GROUP_RX_RATE);
-}
-
-/*
- * The "max_tx_rate" file where the .max_tx_rate variable is read from and written to.
- */
-static ssize_t zxdh_group_max_tx_rate_show(struct zxdh_group_obj *group,
-             struct zxdh_group_attribute *attr, char *buf)
-{
-
-    LOG_INFO("enter\n");
-    return sysfs_emit(buf,
-               "usage: write <Rate (Mbit/s)> to set VF group max tx rate\n");
-}
-
-static ssize_t zxdh_group_max_tx_rate_store(struct zxdh_group_obj *group,
-             struct zxdh_group_attribute *attr, const char *buf, size_t count)
-{
-    return zxdh_group_max_rate_store(group, attr, buf, count, ZXDH_GROUP_TX_RATE);
-}
-
-static ssize_t zxdh_group_config_show(struct zxdh_group_obj *group,
-             struct zxdh_group_attribute *attr, char *buf)
-{
-    //打印当前group配置信息
-    char *p = buf;
-    uint16_t vf_idx;
-    int32_t num_vfs = group->pf_dev->num_vfs;
-    struct zxdh_vf_obj *vf;
-
-    LOG_INFO("enter\n");
-    // if (!mutex_trylock(&esw->state_lock))
-    //     return -EBUSY;
-
-    p += _sprintf(p, buf, "GroupID   : %d\n", group->group_id);
-    p += _sprintf(p, buf, "Num VFs   : %d\n", group->num_vfs);
-    p += _sprintf(p, buf, "MaxTxRate : %d\n", group->max_tx_rate);
-    p += _sprintf(p, buf, "MaxRxRate : %d\n", group->max_rx_rate);
-
-    if (group->num_vfs)
-    {
-        p += _sprintf(p, buf, "VFs       : ");
-        for (vf_idx = 0; vf_idx < num_vfs; vf_idx ++)
-        {
-            vf = group->pf_dev->sriov.vfs + vf_idx;
-            if (vf->group == group)
-                p += _sprintf(p, buf, "VF%d ", vf_idx);
-        }
-        p += _sprintf(p, buf, "\n");
-    }
-
-    // mutex_unlock(&esw->state_lock);
-
-    return (ssize_t)(p - buf);
-}
-
-static ssize_t zxdh_group_config_store(struct zxdh_group_obj *group,
-             struct zxdh_group_attribute *attr, const char *buf, size_t count)
-{
-    LOG_INFO("enter\n");
-    return -ENOTSUPP;
-}
-
-static ssize_t zxdh_vf_config_show(struct zxdh_vf_obj *vf,
-             struct zxdh_vf_attribute *attr, char *buf)
-{
-    //打印当前vf配置信息
-#ifdef ZXDH_PLCR_OPEN
-    struct zxdh_pf_device *pf_dev = vf->pf_dev;
-    struct xarray *xa_bps_flow, *xa_pps_flow;
-    struct zxdh_plcr_flow *flow_bps_rx, *flow_bps_tx, *flow_pps_rx, *flow_pps_tx;
-    uint32_t id_bps_rx, id_bps_tx, id_pps_rx, id_pps_tx;
-    E_RATE_LIMIT_MODE mode;
-#endif
-    char *p = buf;
-
-    LOG_INFO("enter\n");
-    // mutex_lock(&esw->state_lock);
-
-#ifdef ZXDH_PLCR_OPEN
-    xa_bps_flow = &(pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_B]);
-    zxdh_plcr_get_mode(pf_dev, vf->vport, &mode);
-
-    id_bps_rx = zxdh_vport_to_flowid(vf->vport, E_RATE_LIMIT_BYTE, E_RATE_LIMIT_RX);
-    id_bps_tx = zxdh_vport_to_flowid(vf->vport, E_RATE_LIMIT_BYTE, E_RATE_LIMIT_TX);
-    flow_bps_rx = xa_load(xa_bps_flow, id_bps_rx);
-    flow_bps_tx = xa_load(xa_bps_flow, id_bps_tx);
-#endif
-
-    p += _sprintf(p, buf, "VF          : VF%d\n", vf->vf_idx);
-    p += _sprintf(p, buf, "RateGroup   : %d\n", vf->group->group_id);
-#ifdef ZXDH_PLCR_OPEN
-    p += _sprintf(p, buf, "VportQosMode: %d\n", mode);
-
-    if (flow_bps_rx)
-    {
-        p += _sprintf(p, buf, "MinRxRate   : %dMbit/s\n", flow_bps_rx->min_rate);
-        p += _sprintf(p, buf, "MaxRxRate   : %dMbit/s\n", flow_bps_rx->max_rate);
-    }
-
-    if (flow_bps_tx)
-    {
-        p += _sprintf(p, buf, "MinTxRate   : %dMbit/s\n", flow_bps_tx->min_rate);
-        p += _sprintf(p, buf, "MaxTxRate   : %dMbit/s\n", flow_bps_tx->max_rate);
-    }
-    // if (mode == E_RATE_LIMIT_MODE0)
-    // {
-
-    // }
-    // else if (mode == E_RATE_LIMIT_MODE1)
-    // {
-
-    // }
-    if (mode == E_RATE_LIMIT_MODE2)
-    {
-        xa_pps_flow = &(pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_A]);
-        id_pps_rx = zxdh_vport_to_flowid(vf->vport, E_RATE_LIMIT_PACKET, E_RATE_LIMIT_RX);
-        id_pps_tx = zxdh_vport_to_flowid(vf->vport, E_RATE_LIMIT_PACKET, E_RATE_LIMIT_TX);
-        flow_pps_rx = xa_load(xa_pps_flow, id_pps_rx);
-        flow_pps_tx = xa_load(xa_pps_flow, id_pps_tx);
-
-        if (flow_pps_rx)
-            p += _sprintf(p, buf, "MaxRxRate   : %dPackets/s\n", flow_pps_rx->max_rate);
-
-        if (flow_pps_tx)
-            p += _sprintf(p, buf, "MaxTxRate   : %dPackets/s\n", flow_pps_tx->min_rate);
-    }
-
-#endif
-
-    // mutex_unlock(&esw->state_lock);
-
-    return (ssize_t)(p - buf);
-}
-
-static ssize_t zxdh_vf_config_store(struct zxdh_vf_obj *vf,
-             struct zxdh_vf_attribute *attr, const char *buf, size_t count)
-{
-    LOG_INFO("enter\n");
-    return -ENOTSUPP;
-}
-
-static ssize_t zxdh_vf_group_show(struct zxdh_vf_obj *vf,
-             struct zxdh_vf_attribute *attr, char *buf)
-{
-    LOG_INFO("enter\n");
-
-    return sysfs_emit(buf,
-            "usage: write <0-%d> to set VF vport group\n", ZXDH_MAX_VF_GROUP_OBJ_ID);
-}
-
-static ssize_t zxdh_vf_group_store(struct zxdh_vf_obj *vf,
-             struct zxdh_vf_attribute *attr, const char *buf, size_t count)
-{
-    int32_t group_id;
-    int rtn = 0;
-    LOG_INFO("enter\n");
-
-    rtn = kstrtoint(buf, 10, &group_id);
-    if (rtn < 0)
-        return -EINVAL;
-    LOG_INFO("group = %d\n", group_id);
-
-    rtn = zxdh_vf_update_sysfs_group(vf->pf_dev, vf, group_id);
-    if (rtn)
-    {
-        LOG_ERR("zxdh_vf_update_sysfs_group failed\n");
-        return rtn;
-    }
-
-    PLCR_LOG_INFO("VF%d has been moved to group%d\n", vf-> vf_idx, group_id);
-
-    return count;
-}
-
-static ssize_t zxdh_vf_meter_rate_store(struct zxdh_vf_meter_obj *xps,
-             struct zxdh_vf_meter_attribute *attr, const char *buf,
-             size_t count, int32_t data_type)
-{
-#ifdef ZXDH_PLCR_OPEN
-    struct zxdh_pf_device *pf_dev = xps->pf_dev;
-    struct xarray *xarray_flowid = &(pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_B]);
-    struct zxdh_plcr_flow *plcr_flow;
-    zxdh_plcr_rate_limit_paras rate_limit_paras;
-    uint32_t flowid;
-    uint16_t vport;
-    const char *direction;
-#endif
-    int32_t data;
-    int rtn = 0;
-
-    LOG_INFO("enter\n");
-    rtn = kstrtoint(buf, 10, &data);
-    if (rtn < 0)
-        return -EINVAL;
-
-#ifdef ZXDH_PLCR_OPEN
-    vport = xps->vf_obj->vport;
-    flowid = zxdh_vf_meter_obj_to_flowid(xps);
-    plcr_flow = xa_load(xarray_flowid, flowid);
-
-    //调用限速统一接口，配置vf限速
-    if (IS_PPS_METER(xps->meter_type))
-    {
-        LOG_INFO("max_rate = %d Packets/s\n", data);
-        rate_limit_paras.req_type  = E_RATE_LIMIT_REQ_VF_PKT;
-        rate_limit_paras.mode      = E_RATE_LIMIT_PACKET;
-        rate_limit_paras.min_rate  = 0;
-        rate_limit_paras.max_rate  = data;
-    }
-    else
-    {
-        rate_limit_paras.req_type  = E_RATE_LIMIT_REQ_VF_BYTE;
-        rate_limit_paras.mode      = E_RATE_LIMIT_BYTE;
-
-        if (data_type == ZXDH_VF_MIN_RATE)
-        {
-            LOG_INFO("min_rate = %d Mbit/s\n", data);
-            rate_limit_paras.min_rate  = data;
-            if (plcr_flow)
-                rate_limit_paras.max_rate  = plcr_flow->max_rate;
-            else
-                rate_limit_paras.max_rate  = data;
-        }
-        else if (data_type == ZXDH_VF_MAX_RATE)
-        {
-            LOG_INFO("max_rate = %d Mbit/s\n", data);
-            if (plcr_flow)
-                rate_limit_paras.min_rate  = plcr_flow->min_rate;
-            else
-                rate_limit_paras.min_rate  = 0;
-            rate_limit_paras.max_rate  = data;
-        }
-        else
-            return -EINVAL;
-
-        if (rate_limit_paras.max_rate < rate_limit_paras.min_rate)
-            rate_limit_paras.max_rate = rate_limit_paras.min_rate;
-    }
-
-    rate_limit_paras.direction = IS_TX_METER(xps->meter_type) ? E_RATE_LIMIT_TX : E_RATE_LIMIT_RX;
-    rate_limit_paras.queue_id  = PLCR_INVALID_PARAM;
-    rate_limit_paras.vf_idx    = xps->vf_obj->vf_idx;
-    rate_limit_paras.vfid      = PLCR_INVALID_PARAM;
-    rate_limit_paras.group_id  = PLCR_INVALID_PARAM;
-
-    rtn = zxdh_plcr_unified_set_rate_limit(pf_dev, &rate_limit_paras);
-    PLCR_COMM_ASSERT(rtn);
-
-    direction = IS_TX_METER(xps->meter_type) ? "Tx" : "Rx";
-    if (IS_PPS_METER(xps->meter_type))
-    {
-        PLCR_LOG_INFO(
-            "The Max %s Rate of VF%d has been set to %d Packets/s\n",
-            direction, xps->vf_obj->vf_idx, data);
-    }
-    else
-    {
-        PLCR_LOG_INFO(
-            "The Rate of VF%d has been set to: Min %s Rate: %d Mbit/s, Max %s Rate: %d Mbit/s\n",
-            xps->vf_obj->vf_idx,
-            direction, rate_limit_paras.min_rate,
-            direction, rate_limit_paras.max_rate);
-    }
-#endif
-
-    if (data_type == ZXDH_VF_MIN_RATE)
-        xps->min_rate = data;
-    else
-        xps->max_rate = data;
-
-    return rtn ? rtn : count;
-}
-
-static ssize_t zxdh_vf_meter_min_rate_show(struct zxdh_vf_meter_obj *xps,
-             struct zxdh_vf_meter_attribute *attr, char *buf)
-{
-    uint32_t meter_type = xps->meter_type;
-    LOG_INFO("enter\n");
-
-    return sysfs_emit(buf,
-            "usage: write <Rate (Mbit/s)> to set VF %s min rate\n",
-            IS_TX_METER(meter_type) ? "tx" : "rx");
-}
-
-static ssize_t zxdh_vf_meter_min_rate_store(struct zxdh_vf_meter_obj *xps,
-             struct zxdh_vf_meter_attribute *attr, const char *buf, size_t count)
-{
-    return zxdh_vf_meter_rate_store(xps, attr, buf, count, ZXDH_VF_MIN_RATE);
-}
-
-static ssize_t zxdh_vf_meter_max_rate_show(struct zxdh_vf_meter_obj *xps,
-             struct zxdh_vf_meter_attribute *attr, char *buf)
-{
-    uint32_t meter_type = xps->meter_type;
-    LOG_INFO("enter\n");
-
-    return sysfs_emit(buf,
-            "usage: write <Rate (%s)> to set VF %s max rate\n",
-            IS_PPS_METER(meter_type) ? "Packets/s" : "Mbit/s",
-            IS_TX_METER(meter_type) ? "tx" : "rx");
-}
-
-static ssize_t zxdh_vf_meter_max_rate_store(struct zxdh_vf_meter_obj *xps,
-             struct zxdh_vf_meter_attribute *attr, const char *buf, size_t count)
-{
-    return zxdh_vf_meter_rate_store(xps, attr, buf, count, ZXDH_VF_MAX_RATE);
-}
-
-
-#define ZXDH_RATE_GROUP_ATTR(_name) \
-    static struct zxdh_group_attribute zxdh_group_##_name = \
-    __ATTR(_name, 0644, zxdh_group_##_name##_show, zxdh_group_##_name##_store)
-
-#define ZXDH_VF_ATTR(_name) \
-    static struct zxdh_vf_attribute zxdh_vf_##_name = \
-    __ATTR(_name, 0644, zxdh_vf_##_name##_show, zxdh_vf_##_name##_store)
-
-#define ZXDH_VF_METER_ATTR(_name) \
-    static struct zxdh_vf_meter_attribute zxdh_vf_meter_##_name = \
-    __ATTR(_name, 0644, zxdh_vf_meter_##_name##_show, zxdh_vf_meter_##_name##_store)
-
-/* Sysfs attributes cannot be world-writable. */
-ZXDH_RATE_GROUP_ATTR(max_tx_rate);
-ZXDH_RATE_GROUP_ATTR(max_rx_rate);
-ZXDH_RATE_GROUP_ATTR(config);
-ZXDH_VF_ATTR(config);
-ZXDH_VF_ATTR(group);
-ZXDH_VF_METER_ATTR(min_rate);
-ZXDH_VF_METER_ATTR(max_rate);
-
-// static struct zxdh_group_attribute zxdh_group_max_tx_rate __ro_after_init
-//     = __ATTR(max_tx_rate, 0200, NULL, zxdh_group_max_tx_rate_store);
-
-// static struct zxdh_group_attribute zxdh_group_config __ro_after_init
-//     = __ATTR(config, 0444, zxdh_group_config_show, NULL);
-
-// static struct zxdh_vf_attribute zxdh_vf_group __ro_after_init
-//     = __ATTR(group, 0644, zxdh_vf_group_show, zxdh_vf_group_store);
-
-/*
- * Create a group of attributes so that we can create and destroy them all
- * at once.
- */
-static struct attribute *zxdh_group_default_attrs[] = {
-    &zxdh_group_max_tx_rate.attr,
-    &zxdh_group_max_rx_rate.attr,
-    &zxdh_group_config.attr,
-    NULL,    /* need to NULL terminate the list of attributes */
-};
-ATTRIBUTE_GROUPS(zxdh_group_default);
-
-static struct attribute *zxdh_vf_default_attrs[] = {
-    &zxdh_vf_config.attr,
-    &zxdh_vf_group.attr,
-    NULL,
-};
-ATTRIBUTE_GROUPS(zxdh_vf_default);
-
-static struct attribute *zxdh_vf_meter_bps_attrs[] = {
-    &zxdh_vf_meter_min_rate.attr,
-    &zxdh_vf_meter_max_rate.attr,
-    NULL,
-};
-ATTRIBUTE_GROUPS(zxdh_vf_meter_bps);
-
-static struct attribute *zxdh_vf_meter_pps_attrs[] = {
-    &zxdh_vf_meter_max_rate.attr,
-    NULL,
-};
-ATTRIBUTE_GROUPS(zxdh_vf_meter_pps);
-
-/*
- * Our own ktype for our kobjects.  Here we specify our sysfs ops, the
- * release function, and the set of default attributes we want created
- * whenever a kobject of this type is registered with the kernel.
- */
-// static const struct kobj_type
-static struct kobj_type zxdh_group_ktype = {
-    .sysfs_ops = &zxdh_group_sysfs_ops,
-    // .release = zxdh_group_release,
-    .default_groups = zxdh_group_default_groups,
-};
-
-// static const struct kobj_type
-static struct kobj_type zxdh_vf_ktype = {
-    .sysfs_ops = &zxdh_vf_sysfs_ops,
-    // .release = zxdh_vf_release,
-    .default_groups = zxdh_vf_default_groups,
-};
-
-static struct kobj_type zxdh_vf_meter_bps_ktype = {
-    .sysfs_ops = &zxdh_vf_meter_sysfs_ops,
-    // .release = zxdh_vf_meter_release,
-    .default_groups = zxdh_vf_meter_bps_groups,
-};
-
-static struct kobj_type zxdh_vf_meter_pps_ktype = {
-    .sysfs_ops = &zxdh_vf_meter_sysfs_ops,
-    // .release = zxdh_vf_meter_release,
-    .default_groups = zxdh_vf_meter_pps_groups,
-};
-
-static struct zxdh_group_obj *
-zxdh_create_group_obj(struct zxdh_pf_device *pf_dev, int32_t group_id)
-{
-    struct kobject *groups_obj = pf_dev->sriov.groups_obj;
-    struct zxdh_group_obj *group;
-    int rtn = 0;
-
-    LOG_INFO("enter\n");
-    /* allocate the memory for the whole object */
-    group = kzalloc(sizeof(struct zxdh_group_obj), GFP_KERNEL);
-    if (!group)
-        return ERR_PTR(-ENOMEM);
-
-    group->pf_dev = pf_dev;
-    group->group_id = group_id;
-
-    rtn = kobject_init_and_add(&group->kobj, &zxdh_group_ktype, groups_obj, "group%d", group_id);
-    if (rtn)
-    {
-        LOG_INFO("create group-%d kobject failed\n", group_id);
-        kobject_put(&group->kobj);
-        kfree(group);
-        return ERR_PTR(rtn);
-    }
-
-    /* We are always responsible for sending the uevent that the kobject
-     * was added to the system.
-     */
-    kobject_uevent(&group->kobj, KOBJ_ADD);
-
-    list_add_tail(&group->list, &pf_dev->sriov.groups_head);
-
-    init_completion(&group->free_group_comp);
-
-    return group;
-}
-
-int zxdh_create_vf_obj(struct zxdh_pf_device *pf_dev, uint16_t vf_idx)
-{
-    struct zxdh_vf_obj *vf_obj;
-    int rtn;
-
-    LOG_INFO("enter\n");
-
-    vf_obj = pf_dev->sriov.vfs + vf_idx;
-    vf_obj->pf_dev = pf_dev;
-    vf_obj->vport = pf_dev->vf_item[vf_idx].vport;
-    vf_obj->vf_idx = vf_idx;
-    vf_obj->group = pf_dev->sriov.group_0;
-
-    LOG_INFO("p_sriov_obj = %p, vport = %d\n", pf_dev->sriov.sriov_obj, pf_dev->vport);
-    LOG_INFO("vf_idx = %d, vport = %d, group_id = %d\n",\
-            pf_dev->sriov.vfs[vf_idx].vf_idx, pf_dev->sriov.vfs[vf_idx].vport, pf_dev->sriov.vfs[vf_idx].group->group_id);
-
-    rtn = kobject_init_and_add(&vf_obj->kobj, &zxdh_vf_ktype, pf_dev->sriov.sriov_obj,
-                    "vf%d", vf_idx);
-    if (rtn)
-    {
-        LOG_INFO("create vf-%d kobject failed\n", vf_idx);
-        kobject_put(&vf_obj->kobj);
-        return -ENOMEM;
-    }
-
-    vf_obj->group->num_vfs ++;
-
-    kobject_uevent(&vf_obj->kobj, KOBJ_ADD);
-
-    return rtn;
-}
-
-static void zxdh_destroy_group_obj_work(struct work_struct *work)
-{
-	struct zxdh_group_work *group_work = container_of(work, struct zxdh_group_work, work);
-	struct zxdh_group_obj *group_obj = group_work->group_obj;
-
-    LOG_INFO("enter\n");
-	kobject_put(&group_obj->kobj);
-	complete_all(&group_obj->free_group_comp);
-	kfree(group_work);
-}
-
-void zxdh_destroy_group_obj(struct zxdh_group_obj *group_obj)
-{
-	struct zxdh_group_work *group_work;
-
-    LOG_INFO("enter\n");
-    group_work = kzalloc(sizeof *group_work, GFP_ATOMIC);
-    if (unlikely(NULL == group_work))
-    {
-        kobject_put(&group_obj->kobj);
-        complete_all(&group_obj->free_group_comp);
-
-        list_del(&group_obj->list);
-        return;
-    }
-
-	INIT_WORK(&group_work->work, zxdh_destroy_group_obj_work);
-	group_work->group_obj = group_obj;
-	queue_work(system_wq, &group_work->work);
-
-    list_del(&group_obj->list);
-}
-
-void zxdh_destroy_vf_obj(struct zxdh_pf_device *pf_dev, uint16_t vf_idx)
-{
-    struct zxdh_vf_obj *vf_obj;
-
-    LOG_INFO("enter\n");
-    vf_obj = pf_dev->sriov.vfs + vf_idx;
-    kobject_put(&vf_obj->kobj);
-}
-
-
-/**********************************************
-**********************************************/
-
-static struct zxdh_group_obj *
-zxdh_find_sysfs_group(struct zxdh_pf_device *pf_dev, int32_t group_id)
-{
-    struct zxdh_group_obj *group;
-
-    list_for_each_entry(group, &pf_dev->sriov.groups_head, list)
-    {
-        if (group->group_id == group_id)
-            return group;
-    }
-
-    return NULL;
-}
-
-int zxdh_vf_update_sysfs_group(struct zxdh_pf_device *pf_dev, struct zxdh_vf_obj *vf, int32_t group_id)
-{
-    struct zxdh_group_obj *curr_group;
-    struct zxdh_group_obj *new_group;
-    int rtn = 0;
-#ifdef ZXDH_PLCR_OPEN
-    struct xarray *xarray_flowid;
-    struct zxdh_plcr_flow *plcr_rx_flow;
-    struct zxdh_plcr_flow *plcr_tx_flow;
-    int16_t curr_rx_id;
-    int16_t curr_tx_id;
-#endif
-
-    // mutex_lock(&esw->state_lock);
-
-    curr_group = vf->group;
-    if (curr_group && curr_group->group_id == group_id)
-    {
-        LOG_ERR("VF is already in the group%d\n", group_id);
-        goto out;
-    }
-
-    if (group_id)
-    {
-        new_group = zxdh_find_sysfs_group(pf_dev, group_id);
-        if (!new_group)
-        {
-            new_group = zxdh_create_group_obj(pf_dev, group_id);
-            if (IS_ERR(new_group))
-            {
-                rtn = PTR_ERR(new_group);
-                LOG_ERR("create new sysfs group-%d failed (%d)\n", group_id, rtn);
-                goto out;
-            }
-        }
-    }
-    else
-    {
-        new_group = pf_dev->sriov.group_0;
-    }
-
-#ifdef ZXDH_PLCR_OPEN
-    //调用限速统一接口，映射vf到目标group
-    rtn = zxdh_move_vf_to_group(vf, new_group);
-    if (rtn)
-    {
-        PLCR_LOG_ERR("failed and rtn=0x%x\n", rtn)
-        goto err_update;
-    }
-#endif
-
-    vf->group = new_group;
-    new_group->num_vfs++;
-    if (!curr_group)
-        goto out;
-    curr_group->num_vfs--;
-
-    if (curr_group != pf_dev->sriov.group_0 && !curr_group->num_vfs)
-    {
-        zxdh_destroy_group_obj(curr_group);
-
-#ifdef ZXDH_PLCR_OPEN
-        //限速统一接口，移除当前carc flow限速
-        curr_rx_id = zxdh_group_to_flowid(curr_group, ZXDH_GROUP_RX_RATE);
-        curr_tx_id = zxdh_group_to_flowid(curr_group, ZXDH_GROUP_TX_RATE);
-
-        xarray_flowid = &(pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_C]);
-        plcr_rx_flow = xa_load(xarray_flowid, curr_rx_id);
-        plcr_tx_flow = xa_load(xarray_flowid, curr_tx_id);
-
-        if (xa_load(xarray_flowid, curr_rx_id))
-            rtn = zxdh_set_vf_group_rate_limit(curr_group, ZXDH_GROUP_RX_RATE, 0);
-        if (xa_load(xarray_flowid, curr_rx_id))
-            rtn = zxdh_set_vf_group_rate_limit(curr_group, ZXDH_GROUP_TX_RATE, 0);
-#endif
-
-        wait_for_completion(&curr_group->free_group_comp);
-	    kfree(curr_group);
-    }
-    goto out;
-
-#ifdef ZXDH_PLCR_OPEN
-err_update:
-    if (new_group != pf_dev->sriov.group_0 && !new_group->num_vfs)
-    {
-        zxdh_destroy_group_obj(new_group);
-
-        wait_for_completion(&new_group->free_group_comp);
-	    kfree(new_group);
-    }
-#endif
-out:
-    // mutex_unlock(&esw->state_lock);
-    return rtn;
-}
-
-static int zxdh_creat_vf_meter_obj(struct zxdh_vf_obj *vf,
-                        struct zxdh_vf_meters *meters,
-                        uint32_t meter_type)
-{
-    struct zxdh_vf_meter_obj *xps;
-    struct kobject *parent;
-    struct kobj_type *ktype;
-    const char *name;
-    int rtn;
-
-    if (meter_type >= VF_METER_TYPE_NUM)
-        return -EINVAL;
-
-    xps = &meters->xps[meter_type];
-
-    if (IS_TX_METER(meter_type))
-        parent = meters->tx_obj;
-    else
-        parent = meters->rx_obj;
-
-    if (IS_PPS_METER(meter_type))
-    {
-        ktype = &zxdh_vf_meter_pps_ktype;
-        name = "pps";
-    }
-    else
-    {
-        ktype = &zxdh_vf_meter_bps_ktype;
-        name = "bps";
-    }
-
-    rtn = kobject_init_and_add(&xps->kobj, ktype, parent, name);
-    if (rtn)
-    {
-        kobject_put(&xps->kobj);
-        return rtn;
-    }
-
-    xps->pf_dev = vf->pf_dev;
-    xps->vf_obj = vf;
-    xps->meter_type = meter_type;
-
-    return 0;
-}
-
-int zxdh_create_vf_meters_sysfs(struct zxdh_pf_device *pf_dev, uint16_t vf_idx)
-{
-    int rtn = 0;
-    struct zxdh_vf_obj *vf;
-    struct zxdh_vf_meters *meters;
-
-    LOG_INFO("enter\n");
-
-    vf = pf_dev->sriov.vfs + vf_idx;
-
-    meters = kzalloc(sizeof(struct zxdh_vf_meters), GFP_KERNEL);
-    if (!meters)
-    {
-        return -ENOMEM;
-    }
-
-    meters->kobj = kobject_create_and_add("meters", &vf->kobj);
-    if (!meters->kobj)
-    {
-        rtn = -EINVAL;
-        goto err_vf_meters;
-    }
-
-    meters->rx_obj = kobject_create_and_add("rx", meters->kobj);
-    if (!meters->rx_obj)
-    {
-        rtn = -EINVAL;
-        goto err_vf_meters;
-    }
-
-    meters->tx_obj = kobject_create_and_add("tx", meters->kobj);
-    if (!meters->tx_obj)
-    {
-        rtn = -EINVAL;
-        goto err_vf_meters;
-    }
-
-    rtn = zxdh_creat_vf_meter_obj(vf, meters, VF_METER_RX_BPS);
-    if (rtn)
-        goto err_vf_meters;
-
-    rtn = zxdh_creat_vf_meter_obj(vf, meters, VF_METER_RX_PPS);
-    if (rtn)
-        goto err_put_xps_0;
-
-    rtn = zxdh_creat_vf_meter_obj(vf, meters, VF_METER_TX_BPS);
-    if (rtn)
-        goto err_put_xps_1;
-
-    rtn = zxdh_creat_vf_meter_obj(vf, meters, VF_METER_TX_PPS);
-    if (rtn)
-        goto err_put_xps_2;
-
-    vf->meters = meters;
-
-    return 0;
-
-err_put_xps_2:
-    kobject_put(&meters->xps[VF_METER_TX_BPS].kobj);
-err_put_xps_1:
-    kobject_put(&meters->xps[VF_METER_RX_PPS].kobj);
-err_put_xps_0:
-    kobject_put(&meters->xps[VF_METER_RX_BPS].kobj);
-err_vf_meters:
-    kobject_put(meters->rx_obj);
-    kobject_put(meters->tx_obj);
-    kobject_put(meters->kobj);
-
-    kfree(meters);
-
-    return rtn;
-}
-
-static void zxdh_destroy_vf_meters_sysfs(struct zxdh_pf_device *pf_dev, uint16_t vf_idx)
-{
-    struct zxdh_vf_obj *vf;
-    struct zxdh_vf_meters *meters;
-    uint32_t meter_type;
-
-    LOG_INFO("enter\n");
-
-    vf = pf_dev->sriov.vfs + vf_idx;
-    meters = vf->meters;
-    if (!meters)
-        return;
-
-    //限速统一接口，移除当前vf所有限速 todo:en层的vf remove应该已经执行了该操作
-
-    for (meter_type = 0; meter_type < 4; meter_type++)
-        kobject_put(&meters->xps[meter_type].kobj);
-
-    kobject_put(meters->rx_obj);
-    kobject_put(meters->tx_obj);
-    kobject_put(meters->kobj);
-
-    kfree(meters);
-}
-
-int zxdh_create_vfs_sysfs(struct dh_core_dev *dev, int32_t num_vfs)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-    int rtn = 0;
-    uint16_t vf_idx;
-
-    LOG_INFO("enter\n");
-    pf_dev->sriov.vfs = kcalloc(num_vfs, sizeof(struct zxdh_vf_obj), GFP_KERNEL);
-    if (!pf_dev->sriov.vfs)
-    {
-        LOG_ERR("kcalloc vfs failed\n");
-        return -ENOMEM;
-    }
-
-    for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
-    {
-        rtn = zxdh_create_vf_obj(pf_dev, vf_idx);
-        if (rtn)
-        {
-            LOG_ERR("zxdh_create_vf_obj failed\n");
-            goto err_vf;
-        }
-
-        rtn = zxdh_create_vf_meters_sysfs(pf_dev, vf_idx);
-        if (rtn)
-        {
-            zxdh_destroy_vf_obj(pf_dev, vf_idx);
-            LOG_ERR("zxdh_create_vf_meters_sysfs failed\n");
-            goto err_vf;
-        }
-    }
-
-    return 0;
-
-err_vf:
-    for (; vf_idx > 0; --vf_idx)
-    {
-        zxdh_destroy_vf_meters_sysfs(pf_dev, vf_idx);
-
-        zxdh_destroy_vf_obj(pf_dev, vf_idx);
-    }
-
-    kfree(pf_dev->sriov.vfs);
-    pf_dev->sriov.vfs = NULL;
-
-    return rtn;
-}
-
-void zxdh_destroy_vfs_sysfs(struct dh_core_dev *dev, int32_t num_vfs)
-{
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-    struct zxdh_vf_obj *vf;
-    uint16_t vf_idx;
-
-    LOG_INFO("enter\n");
-    if (!num_vfs || !pf_dev->sriov.vfs)
-        return;
-
-    for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
-    {
-        vf = pf_dev->sriov.vfs + vf_idx;
-
-        if (vf->group != pf_dev->sriov.group_0)
-            zxdh_vf_update_sysfs_group(pf_dev, vf, 0);
-
-        zxdh_destroy_vf_meters_sysfs(pf_dev, vf_idx);
-
-        zxdh_destroy_vf_obj(pf_dev, vf_idx);
-    }
-    kfree(pf_dev->sriov.vfs);
-    pf_dev->sriov.vfs = NULL;
-}
-
-void zxdh_cleanup_sysfs_group(struct zxdh_pf_device *pf_dev)
-{
-    struct zxdh_group_obj *group, *tmp;
-
-    LOG_INFO("enter\n");
-    list_for_each_entry_safe(group, tmp, &pf_dev->sriov.groups_head, list)
-    {
-        list_del(&group->list);
-        kfree(group);
-    }
-}
-
-#ifdef ZXDH_PLCR_DEBUG
-int zxdh_sriov_attr_create(struct zxdh_pf_device *pf_dev)
-{
-    int rtn;
-    struct zxdh_sriov_sysfs *sriov = &pf_dev->sriov;
-
-    LOG_INFO("enter\n");
-
-	sriov->burst_attr.attr.name = "burst";
-	sriov->burst_attr.attr.mode = 0644;
-	sriov->burst_attr.show = zxdh_burst_show;
-	sriov->burst_attr.store = zxdh_burst_store;
-    rtn = sysfs_create_file(sriov->sriov_obj, &sriov->burst_attr.attr);
-    if (rtn)
-    {
-        LOG_ERR("burst sysfs_create_file failed!")
-        return rtn;
-    }
-
-	sriov->profile_attr.attr.name = "profiles_stat";
-	sriov->profile_attr.attr.mode = 0444;
-	sriov->profile_attr.show = zxdh_profile_stat_show;
-	sriov->profile_attr.store = NULL;
-    rtn = sysfs_create_file(sriov->sriov_obj, &sriov->profile_attr.attr);
-    if (rtn)
-    {
-        LOG_ERR("profiles_stat sysfs_create_file failed!")
-        goto err_profile_attr;
-    }
-
-    return rtn;
-
-err_profile_attr:
-    sysfs_remove_file(sriov->sriov_obj, &sriov->burst_attr.attr);
-    return rtn;
-}
-
-void zxdh_sriov_attr_remove(struct zxdh_pf_device *pf_dev)
-{
-    struct zxdh_sriov_sysfs *sriov = &pf_dev->sriov;
-
-    LOG_INFO("enter\n");
-    sysfs_remove_file(sriov->sriov_obj, &sriov->profile_attr.attr);
-    sysfs_remove_file(sriov->sriov_obj, &sriov->burst_attr.attr);
-}
-#endif
-
-int zxdh_sriov_sysfs_init(struct dh_core_dev *dev)
-{
-    struct device *device = dev->device;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-    int rtn = 0;
-
-    if (dev->coredev_type != DH_COREDEV_PF)
-        return rtn;
-
-    pf_dev->sriov.sriov_obj = kobject_create_and_add("sriov", &device->kobj);
-    if (!pf_dev->sriov.sriov_obj)
-    {
-        LOG_ERR("zxdh create sriov sysfs failed (%d)\n", -ENOMEM);
-        return -ENOMEM;
-    }
-
-#ifdef ZXDH_PLCR_DEBUG
-    rtn = zxdh_sriov_attr_create(pf_dev);
-    if (rtn)
-    {
-        LOG_ERR("zxdh_sriov_attr_create failed (%d)\n", rtn);
-        goto err_attr;
-    }
-#endif
-
-    pf_dev->sriov.groups_obj = kobject_create_and_add("groups", pf_dev->sriov.sriov_obj);
-    if (!pf_dev->sriov.groups_obj)
-    {
-        LOG_ERR("zxdh create groups sysfs failed (%d)\n", -ENOMEM);
-        rtn = -ENOMEM;
-        goto err_groups;
-    }
-
-    INIT_LIST_HEAD(&pf_dev->sriov.groups_head);
-    pf_dev->sriov.group_0 = zxdh_create_group_obj(pf_dev, ZXDH_DEFAULT_VF_GROUP_ID);
-    if (IS_ERR(pf_dev->sriov.group_0))
-    {
-        LOG_ERR("zxdh create rate group 0 failed (%ld)\n", PTR_ERR(pf_dev->sriov.group_0));
-        rtn = PTR_ERR(pf_dev->sriov.group_0);
-        goto err_group0;
-    }
-
-    LOG_INFO("p_sriov_obj = %p, vport = 0x%x\n", pf_dev->sriov.sriov_obj, pf_dev->vport);
-
-    return rtn;
-
-err_group0:
-    kobject_put(pf_dev->sriov.groups_obj);
-    pf_dev->sriov.groups_obj = NULL;
-err_groups:
-#ifdef ZXDH_PLCR_DEBUG
-    zxdh_sriov_attr_remove(pf_dev);
-err_attr:
-#endif
-    kobject_put(pf_dev->sriov.sriov_obj);
-    pf_dev->sriov.sriov_obj = NULL;
-
-    return rtn;
-}
-
-void zxdh_sriov_sysfs_exit(struct dh_core_dev *dev)
-{
-    // struct device *device = &dev->pdev->dev;
-    struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
-
-    if (dev->coredev_type != DH_COREDEV_PF)
-        return;
-
-    LOG_INFO("enter\n");
-    zxdh_destroy_group_obj(pf_dev->sriov.group_0);
-    wait_for_completion(&pf_dev->sriov.group_0->free_group_comp);
-	kfree(pf_dev->sriov.group_0);
-
-    zxdh_cleanup_sysfs_group(pf_dev);
-
-    kobject_put(pf_dev->sriov.groups_obj);
-    pf_dev->sriov.groups_obj = NULL;
-#ifdef ZXDH_PLCR_DEBUG
-    zxdh_sriov_attr_remove(pf_dev);
-#endif
-    kobject_put(pf_dev->sriov.sriov_obj);
-    pf_dev->sriov.sriov_obj = NULL;
-}
+#ifdef AUX_BUS_NO_SUPPORT
+#include <linux/dinghai/auxiliary_bus.h>
+#else
+#include <linux/auxiliary_bus.h>
+#endif
+#include <linux/dinghai/driver.h>
+#include <net/devlink.h>
+#include <net/udp_tunnel.h>
+#include <linux/dinghai/devlink.h>
+#include <linux/dinghai/dh_cmd.h>
+#include <linux/netdevice.h>
+#include "en_aux.h"
+#include "en_ethtool/ethtool.h"
+#include <linux/dinghai/en_sf.h>
+#include <linux/etherdevice.h>
+#include <linux/dinghai/helper.h>
+#include "en_np/table/include/dpp_tbl_api.h"
+#include "en_aux/events.h"
+#include "en_aux/eq.h"
+#include "en_aux/en_cmd.h"
+#include "msg_common.h"
+#include "en_pf.h"
+#include <linux/dinghai/kcompat.h>
+#include "en_aux/en_ioctl.h"
+#ifdef TIME_STAMP_1588
+#include "en_aux/en_1588_pkt_proc.h"
+#endif
+#include <linux/kobject.h>
+#include <linux/string.h>
+#include <linux/sysfs.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#define ZXDH_DEFAULT_VF_GROUP_ID 0
+#define ZXDH_MAX_VF_GROUP_OBJ_ID 255
+#define ZXDH_MAX_VF_GROUP_OBJ_NUM (ZXDH_MAX_VF_GROUP_OBJ_ID + 1)
+#define ZXDH_MAX_VF_OBJ_ID 255
+#define ZXDH_MAX_VF_OBJ_NUM (ZXDH_MAX_VF_OBJ_ID + 1)
+
+/************************************************
+ * group attr：
+ *   config: RO，打印当前vf端口组所有配置
+ *   max_rx_rate: WO，配置当前vf端口组最大接收速率
+ *   max_tx_rate: WO，配置当前vf端口组最大发送速率
+ ************************************************/
+
+/************************************************
+ * vf attr：
+ * config: RO，打印当前vf所有配置
+ * group: WO，指定当前vf端口所属group，默认group-0
+ * meter
+ *   rx
+ *      bps_rate: WO，配置当前vf端口接收方向字节限速
+ *      pps_rate: WO，配置当前vf端口接收方向包限速
+ *      burst: WO，配置允许的突发带宽
+ *      pkt_dropped: RO, 查询丢包数量/字节数
+ *   tx
+ *      bps_rate: WO，配置当前vf端口发送方向字节限速
+ *      pps_rate: WO，配置当前vf端口发送方向包限速
+ *      burst: WO，配置允许的突发带宽
+ *      pkt_dropped: RO, 查询丢包数量/字节数
+ ************************************************/
+
+struct zxdh_group_attribute {
+	struct attribute attr;
+	ssize_t (*show)(struct zxdh_group_obj *group,
+					struct zxdh_group_attribute *attr, char *buf);
+	ssize_t (*store)(struct zxdh_group_obj *group,
+					 struct zxdh_group_attribute *attr, const char *buf,
+					 size_t count);
+};
+
+#define to_zxdh_group_attr(x) container_of(x, struct zxdh_group_attribute, attr)
+#define to_zxdh_group_obj(x) container_of(x, struct zxdh_group_obj, kobj)
+
+struct zxdh_vf_attribute {
+	struct attribute attr;
+	ssize_t (*show)(struct zxdh_vf_obj *vf, struct zxdh_vf_attribute *attr,
+					char *buf);
+	ssize_t (*store)(struct zxdh_vf_obj *vf, struct zxdh_vf_attribute *attr,
+					 const char *buf, size_t count);
+};
+
+#define to_zxdh_vf_attr(x) container_of(x, struct zxdh_vf_attribute, attr)
+#define to_zxdh_vf_obj(x) container_of(x, struct zxdh_vf_obj, kobj)
+
+struct zxdh_vf_meter_attribute {
+	struct attribute attr;
+	ssize_t (*show)(struct zxdh_vf_meter_obj *xps,
+					struct zxdh_vf_meter_attribute *attr, char *buf);
+	ssize_t (*store)(struct zxdh_vf_meter_obj *xps,
+					 struct zxdh_vf_meter_attribute *attr, const char *buf,
+					 size_t count);
+};
+
+#define to_zxdh_vf_meter_attr(x) \
+	container_of(x, struct zxdh_vf_meter_attribute, attr)
+#define to_zxdh_vf_meter_obj(x) container_of(x, struct zxdh_vf_meter_obj, kobj)
+
+/*
+ * The default show function that must be passed to sysfs.  This will be
+ * called by sysfs for whenever a show function is called by the user on a
+ * sysfs file associated with the kobjects we have registered.  We need to
+ * transpose back from a "default" kobject to our custom struct foo_obj and
+ * then call the show function for that specific object.
+ */
+static ssize_t zxdh_group_attr_show(struct kobject *kobj,
+									struct attribute *attr, char *buf)
+{
+	struct zxdh_group_attribute *attribute;
+	struct zxdh_group_obj *group;
+
+	attribute = to_zxdh_group_attr(attr);
+	group = to_zxdh_group_obj(kobj);
+
+	if (!attribute->show)
+		return -EIO;
+
+	return attribute->show(group, attribute, buf);
+}
+
+/*
+ * Just like the default show function above, but this one is for when the
+ * sysfs "store" is requested (when a value is written to a file.)
+ */
+static ssize_t zxdh_group_attr_store(struct kobject *kobj,
+									 struct attribute *attr, const char *buf,
+									 size_t len)
+{
+	struct zxdh_group_attribute *attribute;
+	struct zxdh_group_obj *group;
+
+	attribute = to_zxdh_group_attr(attr);
+	group = to_zxdh_group_obj(kobj);
+
+	if (!attribute->store)
+		return -EIO;
+
+	return attribute->store(group, attribute, buf, len);
+}
+
+static ssize_t zxdh_vf_attr_show(struct kobject *kobj, struct attribute *attr,
+								 char *buf)
+{
+	struct zxdh_vf_attribute *attribute;
+	struct zxdh_vf_obj *vf;
+
+	attribute = to_zxdh_vf_attr(attr);
+	vf = to_zxdh_vf_obj(kobj);
+
+	if (!attribute->show)
+		return -EIO;
+
+	return attribute->show(vf, attribute, buf);
+}
+
+static ssize_t zxdh_vf_attr_store(struct kobject *kobj, struct attribute *attr,
+								  const char *buf, size_t len)
+{
+	struct zxdh_vf_attribute *attribute;
+	struct zxdh_vf_obj *vf;
+
+	attribute = to_zxdh_vf_attr(attr);
+	vf = to_zxdh_vf_obj(kobj);
+
+	if (!attribute->store)
+		return -EIO;
+
+	return attribute->store(vf, attribute, buf, len);
+}
+
+static ssize_t zxdh_vf_meter_attr_show(struct kobject *kobj,
+									   struct attribute *attr, char *buf)
+{
+	struct zxdh_vf_meter_attribute *attribute;
+	struct zxdh_vf_meter_obj *xps;
+
+	attribute = to_zxdh_vf_meter_attr(attr);
+	xps = to_zxdh_vf_meter_obj(kobj);
+
+	if (!attribute->show)
+		return -EIO;
+
+	return attribute->show(xps, attribute, buf);
+}
+
+static ssize_t zxdh_vf_meter_attr_store(struct kobject *kobj,
+										struct attribute *attr, const char *buf,
+										size_t len)
+{
+	struct zxdh_vf_meter_attribute *attribute;
+	struct zxdh_vf_meter_obj *xps;
+
+	attribute = to_zxdh_vf_meter_attr(attr);
+	xps = to_zxdh_vf_meter_obj(kobj);
+
+	if (!attribute->store)
+		return -EIO;
+
+	return attribute->store(xps, attribute, buf, len);
+}
+
+/* Our custom sysfs_ops that we will associate with our ktype later on */
+static const struct sysfs_ops zxdh_group_sysfs_ops = {
+	.show = zxdh_group_attr_show,
+	.store = zxdh_group_attr_store,
+};
+
+static const struct sysfs_ops zxdh_vf_sysfs_ops = {
+	.show = zxdh_vf_attr_show,
+	.store = zxdh_vf_attr_store,
+};
+
+static const struct sysfs_ops zxdh_vf_meter_sysfs_ops = {
+	.show = zxdh_vf_meter_attr_show,
+	.store = zxdh_vf_meter_attr_store,
+};
+
+/*
+ * The release function for our object.  This is REQUIRED by the kernel to
+ * have.  We free the memory held in our object here.
+ *
+ * NEVER try to get away with just a "blank" release function to try to be
+ * smarter than the kernel.  Turns out, no one ever is...
+ */
+/*static void zxdh_group_release(struct kobject *kobj)
+{
+    struct zxdh_group_obj *group;
+
+    LOG_INFO("enter\n");
+    group = to_zxdh_group_obj(kobj);
+    kfree(group);
+}
+
+static void zxdh_vf_release(struct kobject *kobj)
+{
+    struct zxdh_vf_obj *vf;
+
+    LOG_INFO("enter\n");
+    vf = to_zxdh_vf_obj(kobj);
+    kfree(vf);
+}
+
+static void zxdh_vf_meter_release(struct kobject *kobj)
+{
+    struct zxdh_vf_meter_obj *xps;
+
+    LOG_INFO("enter\n");
+    xps = to_zxdh_vf_meter_obj(kobj);
+    kfree(xps);
+}*/
+
+static uint16_t zxdh_group_to_flowid(struct zxdh_group_obj *group,
+									 int32_t data_type)
+{
+	uint16_t flowid;
+	uint16_t vport = group->pf_dev->vport;
+	int32_t group_id = group->group_id;
+	int32_t global_group_id;
+
+	global_group_id = EPID(vport) * 128 + FUNC_NUM(vport) * 16 + group_id;
+	flowid = (data_type == ZXDH_GROUP_TX_RATE) ? (global_group_id * 2 + 1) :
+												   (global_group_id * 2);
+
+	return flowid;
+}
+
+static ssize_t zxdh_group_max_rate_store(struct zxdh_group_obj *group,
+										 struct zxdh_group_attribute *attr,
+										 const char *buf, size_t count,
+										 int32_t data_type)
+{
+	uint32_t max_rate;
+	uint16_t flowid;
+	int rtn = 0;
+	LOG_INFO("enter\n");
+
+	rtn = kstrtoint(buf, 10, &max_rate);
+	if (rtn < 0)
+		return -EINVAL;
+	LOG_INFO("max_%d_rate = %d\n", max_rate);
+
+	// flowid = zxdh_group_to_flowid(group, data_type);
+	//调用限速统一接口
+
+	group->max_rx_rate = max_rate;
+
+	return rtn ? rtn : count;
+}
+
+static ssize_t zxdh_group_max_rx_rate_show(struct zxdh_group_obj *group,
+										   struct zxdh_group_attribute *attr,
+										   char *buf)
+{
+	LOG_INFO("enter\n");
+	return sysfs_emit(
+			buf, "usage: write <Rate (Mbit/s)> to set VF group max rx rate\n");
+}
+
+static ssize_t zxdh_group_max_rx_rate_store(struct zxdh_group_obj *group,
+											struct zxdh_group_attribute *attr,
+											const char *buf, size_t count)
+{
+	return zxdh_group_max_rate_store(group, attr, buf, count,
+									 ZXDH_GROUP_RX_RATE);
+}
+
+/*
+ * The "max_tx_rate" file where the .max_tx_rate variable is read from and
+ * written to.
+ */
+static ssize_t zxdh_group_max_tx_rate_show(struct zxdh_group_obj *group,
+										   struct zxdh_group_attribute *attr,
+										   char *buf)
+{
+	LOG_INFO("enter\n");
+	return sysfs_emit(
+			buf, "usage: write <Rate (Mbit/s)> to set VF group max tx rate\n");
+}
+
+static ssize_t zxdh_group_max_tx_rate_store(struct zxdh_group_obj *group,
+											struct zxdh_group_attribute *attr,
+											const char *buf, size_t count)
+{
+	return zxdh_group_max_rate_store(group, attr, buf, count,
+									 ZXDH_GROUP_TX_RATE);
+}
+
+#define _sprintf(p, buf, format, arg...) \
+	((PAGE_SIZE - (int)(p - buf)) <= 0 ? \
+			   0 :                         \
+			   scnprintf(p, PAGE_SIZE - (int)(p - buf), format, ##arg))
+
+static ssize_t zxdh_group_config_show(struct zxdh_group_obj *group,
+									  struct zxdh_group_attribute *attr,
+									  char *buf)
+{
+	//打印当前group配置信息
+
+	char *p = buf;
+	LOG_INFO("enter\n");
+
+	// if (!mutex_trylock(&esw->state_lock))
+	//     return -EBUSY;
+
+	p += _sprintf(p, buf, "Num VFs    : %d\n", group->num_vfs);
+	p += _sprintf(p, buf, "MaxTxRate  : %d\n", group->max_tx_rate);
+	p += _sprintf(p, buf, "MaxRxRate  : %d\n", group->max_rx_rate);
+
+	// p += _sprintf(p, buf, "VFs    : vf%d\n", index);
+
+	// mutex_unlock(&esw->state_lock);
+	// return sysfs_emit(buf, "Num_vfs: %d\nMax_Tx_Rate: %d\nMax_Rx_Rate: %d",
+	//                         num_vfs, max_tx_rate, max_rx_rate);
+
+	return (ssize_t)(p - buf);
+}
+
+static ssize_t zxdh_group_config_store(struct zxdh_group_obj *group,
+									   struct zxdh_group_attribute *attr,
+									   const char *buf, size_t count)
+{
+	LOG_INFO("enter\n");
+	return -ENOTSUPP;
+}
+
+static ssize_t zxdh_vf_config_show(struct zxdh_vf_obj *vf,
+								   struct zxdh_vf_attribute *attr, char *buf)
+{
+	//打印当前vf配置信息
+	struct zxdh_pf_device *pf_dev;
+	char *p = buf;
+	// int32_t mode = ;
+	LOG_INFO("enter\n");
+
+	// mutex_lock(&esw->state_lock);
+	pf_dev = vf->pf_dev;
+
+	p += _sprintf(p, buf, "VF         : %d\n", vf->vf_idx);
+	//首先检查当前vport的mode
+	p += _sprintf(p, buf, "RateGroup  : %d\n", vf->group->group_id);
+	// p += _sprintf(p, buf, "VportQosMode  : %d\n", mode);
+	// if (mode == 0)
+	// {
+	//     p += _sprintf(p, buf, "MinTxRate  : %d\n", evport->qos.min_rate);
+	// }
+	// else if (mode == 1)
+	// {
+	//     p += _sprintf(p, buf, "MinTxRate  : %d\n", evport->qos.min_rate);
+	//     // p += _sprintf(p, buf, "MinTxRate  : %d\n", evport->qos.min_rate);
+	//     // p += _sprintf(p, buf, "MaxTxRate  : %d\n", evport->qos.max_rate);
+	// }
+	// else if (mode == 2)
+	// {
+
+	// }
+	// else
+	// {
+	//     rtn = - ;
+	// }
+
+	// mutex_unlock(&esw->state_lock);
+
+	return (ssize_t)(p - buf);
+}
+
+static ssize_t zxdh_vf_config_store(struct zxdh_vf_obj *vf,
+									struct zxdh_vf_attribute *attr,
+									const char *buf, size_t count)
+{
+	LOG_INFO("enter\n");
+	return -ENOTSUPP;
+}
+
+static ssize_t zxdh_vf_group_show(struct zxdh_vf_obj *vf,
+								  struct zxdh_vf_attribute *attr, char *buf)
+{
+	LOG_INFO("enter\n");
+
+	return sysfs_emit(buf, "usage: write <Group 0-%d> to set VF vport group\n",
+					  ZXDH_MAX_VF_GROUP_OBJ_ID);
+}
+
+static ssize_t zxdh_vf_group_store(struct zxdh_vf_obj *vf,
+								   struct zxdh_vf_attribute *attr,
+								   const char *buf, size_t count)
+{
+	int32_t group_id;
+	int rtn = 0;
+	LOG_INFO("enter\n");
+
+	rtn = kstrtoint(buf, 10, &group_id);
+	if (rtn < 0)
+		return -EINVAL;
+	LOG_INFO("group = %d\n", group_id);
+
+	rtn = zxdh_vf_update_sysfs_group(vf->pf_dev, vf, group_id);
+	if (rtn) {
+		LOG_ERR("zxdh_vf_update_sysfs_group failed\n");
+	}
+
+	return rtn ? rtn : count;
+}
+static uint32_t zxdh_vf_meter_obj_to_flowid(struct zxdh_vf_meter_obj *xps)
+{
+	uint16_t vport;
+	uint16_t vfid;
+	uint16_t flowid;
+
+	LOG_INFO("enter\n");
+	vport = xps->vf_obj->vport;
+	vfid = VQM_VFID(vport);
+	flowid = IS_TX_METER(xps->meter_type) ? (vfid * 2 + 1) : (vfid * 2);
+
+	return flowid;
+}
+
+static ssize_t zxdh_vf_meter_rate_store(struct zxdh_vf_meter_obj *xps,
+										struct zxdh_vf_meter_attribute *attr,
+										const char *buf, size_t count,
+										int32_t data_type)
+{
+	struct zxdh_pf_device *pf_dev = xps->pf_dev;
+	struct xarray *xarray_flowid =
+			&(pf_dev->plcr_table.plcr_flows[E_PLCR_CAR_B]);
+	struct zxdh_plcr_flow *plcr_flow;
+	uint32_t data;
+	uint32_t flowid;
+	uint16_t vport;
+	int rtn = 0;
+
+	LOG_INFO("enter\n");
+	rtn = kstrtoint(buf, 10, &data);
+	if (rtn < 0)
+		return -EINVAL;
+
+	vport = xps->vf_obj->vport;
+	flowid = zxdh_vf_meter_obj_to_flowid(xps);
+	plcr_flow = xa_load(xarray_flowid, flowid);
+
+	//调用限速统一接口
+	// if (data_type == ZXDH_VF_MIN_RATE)
+	// {
+	//     LOG_INFO("flowid = %d, min_rate = %d Mbit/s\n", flowid, data);
+	//     rtn = zxdh_plcr_set_rate_limit(pf_dev, E_PLCR_CAR_B, vport, flowid,
+	//     plcr_flow->max_rate, data); if (rtn)
+	//     {
+	//         LOG_ERR("zxdh_plcr_set_rate_limit failed\n");
+	//         return rtn ? rtn : count;
+	//     }
+	//     xps->min_rate = data;
+	// }
+	// else if (data_type == ZXDH_VF_MAX_RATE)
+	// {
+	//     LOG_INFO("flowid = %d, max_rate = %d %s\n", flowid, data,
+	//                 IS_PPS_METER(xps->meter_type) ? "Packets/s" : "Mbit/s");
+	//     rtn = zxdh_plcr_set_rate_limit(pf_dev, E_PLCR_CAR_B, vport, flowid,
+	//     data, plcr_flow->min_rate); if (rtn)
+	//     {
+	//         LOG_ERR("zxdh_plcr_set_rate_limit failed\n");
+	//         return rtn ? rtn : count;
+	//     }
+	//     xps->max_rate = data;
+	// }
+	// else
+	// {
+	//     rtn = -EINVAL;
+	// }
+
+	return rtn ? rtn : count;
+}
+
+static ssize_t zxdh_vf_meter_min_rate_show(struct zxdh_vf_meter_obj *xps,
+										   struct zxdh_vf_meter_attribute *attr,
+										   char *buf)
+{
+	uint32_t meter_type = xps->meter_type;
+	LOG_INFO("enter\n");
+
+	return sysfs_emit(buf,
+					  "usage: write <Rate (Mbit/s)> to set VF %s min rate\n",
+					  IS_TX_METER(meter_type) ? "tx" : "rx");
+}
+
+static ssize_t
+zxdh_vf_meter_min_rate_store(struct zxdh_vf_meter_obj *xps,
+							 struct zxdh_vf_meter_attribute *attr,
+							 const char *buf, size_t count)
+{
+	return zxdh_vf_meter_rate_store(xps, attr, buf, count, ZXDH_VF_MIN_RATE);
+}
+
+static ssize_t zxdh_vf_meter_max_rate_show(struct zxdh_vf_meter_obj *xps,
+										   struct zxdh_vf_meter_attribute *attr,
+										   char *buf)
+{
+	uint32_t meter_type = xps->meter_type;
+	LOG_INFO("enter\n");
+
+	return sysfs_emit(buf, "usage: write <Rate (%s)> to set VF %s max rate\n",
+					  IS_PPS_METER(meter_type) ? "Packets/s" : "Mbit/s",
+					  (meter_type == VF_METER_TX_BPS ||
+					   meter_type == VF_METER_TX_PPS) ?
+								"tx" :
+								"rx");
+}
+
+static ssize_t
+zxdh_vf_meter_max_rate_store(struct zxdh_vf_meter_obj *xps,
+							 struct zxdh_vf_meter_attribute *attr,
+							 const char *buf, size_t count)
+{
+	return zxdh_vf_meter_rate_store(xps, attr, buf, count, ZXDH_VF_MAX_RATE);
+}
+
+#define ZXDH_RATE_GROUP_ATTR(_name)                         \
+	static struct zxdh_group_attribute zxdh_group_##_name = \
+			__ATTR(_name, 0644, zxdh_group_##_name##_show,  \
+				   zxdh_group_##_name##_store)
+
+#define ZXDH_VF_ATTR(_name)                                   \
+	static struct zxdh_vf_attribute zxdh_vf_##_name = __ATTR( \
+			_name, 0644, zxdh_vf_##_name##_show, zxdh_vf_##_name##_store)
+
+#define ZXDH_VF_METER_ATTR(_name)                                 \
+	static struct zxdh_vf_meter_attribute zxdh_vf_meter_##_name = \
+			__ATTR(_name, 0644, zxdh_vf_meter_##_name##_show,     \
+				   zxdh_vf_meter_##_name##_store)
+
+/* Sysfs attributes cannot be world-writable. */
+ZXDH_RATE_GROUP_ATTR(max_tx_rate);
+ZXDH_RATE_GROUP_ATTR(max_rx_rate);
+ZXDH_RATE_GROUP_ATTR(config);
+ZXDH_VF_ATTR(config);
+ZXDH_VF_ATTR(group);
+ZXDH_VF_METER_ATTR(min_rate);
+ZXDH_VF_METER_ATTR(max_rate);
+
+// static struct zxdh_group_attribute zxdh_group_max_tx_rate __ro_after_init
+//     = __ATTR(max_tx_rate, 0200, NULL, zxdh_group_max_tx_rate_store);
+
+// static struct zxdh_group_attribute zxdh_group_config __ro_after_init
+//     = __ATTR(config, 0444, zxdh_group_config_show, NULL);
+
+// static struct zxdh_vf_attribute zxdh_vf_group __ro_after_init
+//     = __ATTR(group, 0644, zxdh_vf_group_show, zxdh_vf_group_store);
+
+/*
+ * Create a group of attributes so that we can create and destroy them all
+ * at once.
+ */
+static struct attribute *zxdh_group_default_attrs[] = {
+	&zxdh_group_max_tx_rate.attr, &zxdh_group_max_rx_rate.attr,
+	&zxdh_group_config.attr,
+	NULL, /* need to NULL terminate the list of attributes */
+};
+ATTRIBUTE_GROUPS(zxdh_group_default);
+
+static struct attribute *zxdh_vf_default_attrs[] = {
+	&zxdh_vf_config.attr,
+	&zxdh_vf_group.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(zxdh_vf_default);
+
+static struct attribute *zxdh_vf_meter_bps_attrs[] = {
+	&zxdh_vf_meter_min_rate.attr,
+	&zxdh_vf_meter_max_rate.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(zxdh_vf_meter_bps);
+
+static struct attribute *zxdh_vf_meter_pps_attrs[] = {
+	&zxdh_vf_meter_max_rate.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(zxdh_vf_meter_pps);
+
+/*
+ * Our own ktype for our kobjects.  Here we specify our sysfs ops, the
+ * release function, and the set of default attributes we want created
+ * whenever a kobject of this type is registered with the kernel.
+ */
+// static const struct kobj_type
+static struct kobj_type zxdh_group_ktype = {
+	.sysfs_ops = &zxdh_group_sysfs_ops,
+	// .release = zxdh_group_release,
+	.default_groups = zxdh_group_default_groups,
+};
+
+// static const struct kobj_type
+static struct kobj_type zxdh_vf_ktype = {
+	.sysfs_ops = &zxdh_vf_sysfs_ops,
+	// .release = zxdh_vf_release,
+	.default_groups = zxdh_vf_default_groups,
+};
+
+static struct kobj_type zxdh_vf_meter_bps_ktype = {
+	.sysfs_ops = &zxdh_vf_meter_sysfs_ops,
+	// .release = zxdh_vf_meter_release,
+	.default_groups = zxdh_vf_meter_bps_groups,
+};
+
+static struct kobj_type zxdh_vf_meter_pps_ktype = {
+	.sysfs_ops = &zxdh_vf_meter_sysfs_ops,
+	// .release = zxdh_vf_meter_release,
+	.default_groups = zxdh_vf_meter_pps_groups,
+};
+
+static struct zxdh_group_obj *
+zxdh_create_group_obj(struct zxdh_pf_device *pf_dev, int32_t group_id)
+{
+	struct kobject *groups_obj = pf_dev->sriov.groups_obj;
+	struct zxdh_group_obj *group;
+	int rtn = 0;
+
+	LOG_INFO("enter\n");
+	/* allocate the memory for the whole object */
+	group = kzalloc(sizeof(struct zxdh_group_obj), GFP_KERNEL);
+	if (!group)
+		return ERR_PTR(-ENOMEM);
+
+	group->pf_dev = pf_dev;
+	group->group_id = group_id;
+
+	rtn = kobject_init_and_add(&group->kobj, &zxdh_group_ktype, groups_obj,
+							   "group%d", group_id);
+	if (rtn) {
+		LOG_INFO("create group-%d kobject failed\n", group_id);
+		kobject_put(&group->kobj);
+		return ERR_PTR(rtn);
+	}
+
+	/* We are always responsible for sending the uevent that the kobject
+   * was added to the system.
+   */
+	kobject_uevent(&group->kobj, KOBJ_ADD);
+
+	list_add_tail(&group->list, &pf_dev->sriov.groups_head);
+
+	init_completion(&group->free_group_comp);
+
+	return group;
+}
+
+int zxdh_create_vf_obj(struct zxdh_pf_device *pf_dev, uint16_t vf_idx)
+{
+	struct zxdh_vf_obj *vf_obj;
+	int rtn;
+
+	LOG_INFO("enter\n");
+	vf_obj = pf_dev->sriov.vfs + vf_idx;
+	vf_obj->pf_dev = pf_dev;
+	vf_obj->vport = pf_dev->vf_item[vf_idx].vport;
+	vf_obj->vf_idx = vf_idx;
+	vf_obj->group = pf_dev->sriov.group_0;
+
+	LOG_INFO("p_sriov_obj = %p, vport = %d\n", pf_dev->sriov.sriov_obj,
+			 pf_dev->vport);
+	LOG_INFO("vf_idx = %d, vport = %d, group_id = %d\n",
+			 pf_dev->sriov.vfs[vf_idx].vf_idx, pf_dev->sriov.vfs[vf_idx].vport,
+			 pf_dev->sriov.vfs[vf_idx].group->group_id);
+
+	rtn = kobject_init_and_add(&vf_obj->kobj, &zxdh_vf_ktype,
+							   pf_dev->sriov.sriov_obj, "vf%d", vf_idx);
+	if (rtn) {
+		LOG_INFO("create vf-%d kobject failed\n", vf_idx);
+		kobject_put(&vf_obj->kobj);
+		return -ENOMEM;
+	}
+
+	vf_obj->group->num_vfs++;
+
+	kobject_uevent(&vf_obj->kobj, KOBJ_ADD);
+
+	return rtn;
+}
+
+static void zxdh_destroy_group_obj_work(struct work_struct *work)
+{
+	struct zxdh_group_work *group_work =
+			container_of(work, struct zxdh_group_work, work);
+	struct zxdh_group_obj *group_obj = group_work->group_obj;
+
+	LOG_INFO("enter\n");
+	kobject_put(&group_obj->kobj);
+	complete_all(&group_obj->free_group_comp);
+	kfree(group_work);
+}
+
+void zxdh_destroy_group_obj(struct zxdh_group_obj *group_obj)
+{
+	LOG_INFO("enter\n");
+	struct zxdh_group_work *group_work =
+			kzalloc(sizeof *group_work, GFP_ATOMIC);
+
+	INIT_WORK(&group_work->work, zxdh_destroy_group_obj_work);
+	group_work->group_obj = group_obj;
+	queue_work(system_wq, &group_work->work);
+
+	list_del(&group_obj->list);
+
+	wait_for_completion(&group_obj->free_group_comp);
+	kfree(group_obj);
+}
+
+void zxdh_destroy_vf_obj(struct zxdh_pf_device *pf_dev, uint16_t vf_idx)
+{
+	struct zxdh_vf_obj *vf_obj;
+
+	LOG_INFO("enter\n");
+	vf_obj = pf_dev->sriov.vfs + vf_idx;
+	kobject_put(&vf_obj->kobj);
+}
+
+/**********************************************
+**********************************************/
+
+static struct zxdh_group_obj *
+zxdh_find_sysfs_group(struct zxdh_pf_device *pf_dev, int32_t group_id)
+{
+	struct zxdh_group_obj *group;
+
+	list_for_each_entry(group, &pf_dev->sriov.groups_head, list) {
+		if (group->group_id == group_id)
+			return group;
+	}
+
+	return NULL;
+}
+
+int zxdh_vf_update_sysfs_group(struct zxdh_pf_device *pf_dev,
+							   struct zxdh_vf_obj *vf, int32_t group_id)
+{
+	struct zxdh_group_obj *curr_group;
+	struct zxdh_group_obj *new_group;
+	int rtn = 0;
+
+	// mutex_lock(&esw->state_lock);
+
+	curr_group = vf->group;
+	if (curr_group && curr_group->group_id == group_id) {
+		LOG_ERR("VF is already in the group%d\n", group_id);
+		return rtn;
+	}
+
+	if (group_id) {
+		new_group = zxdh_find_sysfs_group(pf_dev, group_id);
+		if (!new_group) {
+			new_group = zxdh_create_group_obj(pf_dev, group_id);
+			if (IS_ERR(new_group)) {
+				rtn = PTR_ERR(new_group);
+				LOG_ERR("create new sysfs group-%d failed (%d)\n", group_id,
+						rtn);
+				goto out;
+			}
+		}
+	} else {
+		new_group = pf_dev->sriov.group_0;
+	}
+
+	//调用限速统一接口，更新carb和carc flow映射关系
+	// if (rtn)
+	// {
+	//     LOG_ERR("update to new sysfs group-%d failed (%d)\n", group_id, rtn);
+	//     goto err_update;
+	// }
+
+	vf->group = new_group;
+	new_group->num_vfs++;
+	curr_group->num_vfs--;
+
+	if (curr_group != pf_dev->sriov.group_0 && !curr_group->num_vfs) {
+		zxdh_destroy_group_obj(curr_group);
+		//限速统一接口，移除当前carc flow限速
+	}
+	goto out;
+
+err_update:
+	if (new_group != pf_dev->sriov.group_0 && !new_group->num_vfs) {
+		zxdh_destroy_group_obj(new_group);
+	}
+out:
+	// mutex_unlock(&esw->state_lock);
+	return rtn;
+}
+
+static int zxdh_creat_vf_meter_obj(struct zxdh_vf_obj *vf,
+								   struct zxdh_vf_meters *meters,
+								   uint32_t meter_type)
+{
+	struct zxdh_vf_meter_obj *xps;
+	struct kobject *parent;
+	struct kobj_type *ktype;
+	const char *name;
+	int rtn;
+
+	xps = &meters->xps[meter_type];
+
+	if (IS_TX_METER(meter_type))
+		parent = meters->tx_obj;
+	else
+		parent = meters->rx_obj;
+
+	if (IS_PPS_METER(meter_type)) {
+		ktype = &zxdh_vf_meter_pps_ktype;
+		name = "pps";
+	} else {
+		ktype = &zxdh_vf_meter_bps_ktype;
+		name = "bps";
+	}
+
+	rtn = kobject_init_and_add(&xps->kobj, ktype, parent, name);
+	if (rtn) {
+		kobject_put(&xps->kobj);
+		return rtn;
+	}
+
+	xps->pf_dev = vf->pf_dev;
+	xps->vf_obj = vf;
+	xps->meter_type = meter_type;
+
+	return 0;
+}
+
+int zxdh_create_vf_meters_sysfs(struct zxdh_pf_device *pf_dev, uint16_t vf_idx)
+{
+	int rtn = 0;
+	struct zxdh_vf_obj *vf;
+	struct zxdh_vf_meters *meters;
+
+	LOG_INFO("enter\n");
+
+	vf = pf_dev->sriov.vfs + vf_idx;
+
+	meters = kzalloc(sizeof(struct zxdh_vf_meters), GFP_KERNEL);
+	if (!meters) {
+		rtn = -ENOMEM;
+		goto err_vf_meters;
+	}
+
+	meters->kobj = kobject_create_and_add("meters", &vf->kobj);
+	if (!meters->kobj) {
+		rtn = -EINVAL;
+		goto err_vf_meters;
+	}
+
+	meters->rx_obj = kobject_create_and_add("rx", meters->kobj);
+	if (!meters->rx_obj) {
+		rtn = -EINVAL;
+		goto err_vf_meters;
+	}
+
+	meters->tx_obj = kobject_create_and_add("tx", meters->kobj);
+	if (!meters->tx_obj) {
+		rtn = -EINVAL;
+		goto err_vf_meters;
+	}
+
+	rtn = zxdh_creat_vf_meter_obj(vf, meters, VF_METER_RX_BPS);
+	if (rtn)
+		goto err_vf_meters;
+
+	rtn = zxdh_creat_vf_meter_obj(vf, meters, VF_METER_RX_PPS);
+	if (rtn)
+		goto err_put_xps_0;
+
+	rtn = zxdh_creat_vf_meter_obj(vf, meters, VF_METER_TX_BPS);
+	if (rtn)
+		goto err_put_xps_1;
+
+	rtn = zxdh_creat_vf_meter_obj(vf, meters, VF_METER_TX_PPS);
+	if (rtn)
+		goto err_put_xps_2;
+
+	vf->meters = meters;
+
+	return 0;
+
+err_put_xps_2:
+	kobject_put(&meters->xps[VF_METER_TX_BPS].kobj);
+err_put_xps_1:
+	kobject_put(&meters->xps[VF_METER_RX_PPS].kobj);
+err_put_xps_0:
+	kobject_put(&meters->xps[VF_METER_RX_BPS].kobj);
+err_vf_meters:
+	kobject_put(meters->rx_obj);
+	kobject_put(meters->tx_obj);
+	kobject_put(meters->kobj);
+
+	kfree(meters);
+
+	return rtn;
+}
+
+static void zxdh_destroy_vf_meters_sysfs(struct zxdh_pf_device *pf_dev,
+										 uint16_t vf_idx)
+{
+	struct zxdh_vf_obj *vf;
+	struct zxdh_vf_meters *meters;
+	uint32_t meter_type;
+
+	LOG_INFO("enter\n");
+
+	vf = pf_dev->sriov.vfs + vf_idx;
+	meters = vf->meters;
+	if (!meters)
+		return;
+
+	//限速统一接口，移除当前vf所有限速
+
+	for (meter_type = 0; meter_type < 4; meter_type++)
+		kobject_put(&meters->xps[meter_type].kobj);
+
+	kobject_put(meters->rx_obj);
+	kobject_put(meters->tx_obj);
+	kobject_put(meters->kobj);
+
+	kfree(meters);
+}
+
+int zxdh_create_vfs_sysfs(struct dh_core_dev *dev, int32_t num_vfs)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+	int rtn = 0;
+	uint16_t vf_idx;
+
+	LOG_INFO("enter\n");
+	pf_dev->sriov.vfs =
+			kcalloc(num_vfs, sizeof(struct zxdh_vf_obj), GFP_KERNEL);
+	if (!pf_dev->sriov.vfs) {
+		LOG_ERR("kcalloc vfs failed\n");
+		return -ENOMEM;
+	}
+
+	for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) {
+		rtn = zxdh_create_vf_obj(pf_dev, vf_idx);
+		if (rtn) {
+			LOG_ERR("zxdh_create_vf_obj failed\n");
+			goto err_vf;
+		}
+
+		rtn = zxdh_create_vf_meters_sysfs(pf_dev, vf_idx);
+		if (rtn) {
+			zxdh_destroy_vf_obj(pf_dev, vf_idx);
+			LOG_ERR("zxdh_create_vf_meters_sysfs failed\n");
+			goto err_vf;
+		}
+	}
+
+	return 0;
+
+err_vf:
+	for (; vf_idx > 0; --vf_idx) {
+		zxdh_destroy_vf_meters_sysfs(pf_dev, vf_idx);
+
+		zxdh_destroy_vf_obj(pf_dev, vf_idx);
+	}
+
+	kfree(pf_dev->sriov.vfs);
+	pf_dev->sriov.vfs = NULL;
+	return rtn;
+}
+
+void zxdh_destroy_vfs_sysfs(struct dh_core_dev *dev, int32_t num_vfs)
+{
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+	struct zxdh_vf_obj *vf;
+	uint16_t vf_idx;
+
+	LOG_INFO("enter\n");
+	if (!num_vfs || !pf_dev->sriov.vfs)
+		return;
+
+	for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) {
+		vf = pf_dev->sriov.vfs + vf_idx;
+
+		if (vf->group != pf_dev->sriov.group_0)
+			zxdh_vf_update_sysfs_group(pf_dev, vf, 0);
+
+		zxdh_destroy_vf_meters_sysfs(pf_dev, vf_idx);
+
+		zxdh_destroy_vf_obj(pf_dev, vf_idx);
+	}
+	kfree(pf_dev->sriov.vfs);
+	pf_dev->sriov.vfs = NULL;
+}
+
+void zxdh_cleanup_sysfs_group(struct zxdh_pf_device *pf_dev)
+{
+	struct zxdh_group_obj *group, *tmp;
+
+	LOG_INFO("enter\n");
+	list_for_each_entry_safe(group, tmp, &pf_dev->sriov.groups_head, list) {
+		list_del(&group->list);
+		kfree(group);
+	}
+}
+
+int zxdh_sriov_sysfs_init(struct dh_core_dev *dev)
+{
+	struct device *device = dev->device;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+	int rtn = 0;
+
+	if (dev->coredev_type != DH_COREDEV_PF)
+		return rtn;
+
+	LOG_INFO("enter\n");
+	pf_dev->sriov.sriov_obj = kobject_create_and_add("sriov", &device->kobj);
+	if (!pf_dev->sriov.sriov_obj) {
+		LOG_ERR("zxdh create sriov sysfs failed (%d)\n", -ENOMEM);
+		return -ENOMEM;
+	}
+
+	pf_dev->sriov.groups_obj =
+			kobject_create_and_add("groups", pf_dev->sriov.sriov_obj);
+	if (!pf_dev->sriov.groups_obj) {
+		LOG_ERR("zxdh create groups sysfs failed (%d)\n", -ENOMEM);
+		rtn = -ENOMEM;
+		goto err_groups;
+	}
+
+	INIT_LIST_HEAD(&pf_dev->sriov.groups_head);
+	pf_dev->sriov.group_0 =
+			zxdh_create_group_obj(pf_dev, ZXDH_DEFAULT_VF_GROUP_ID);
+	if (IS_ERR(pf_dev->sriov.group_0)) {
+		LOG_ERR("zxdh create rate group 0 failed (%ld)\n",
+				PTR_ERR(pf_dev->sriov.group_0));
+		rtn = PTR_ERR(pf_dev->sriov.group_0);
+		goto err_group0;
+	}
+
+	LOG_INFO("p_sriov_obj = %p, vport = 0x%x\n", pf_dev->sriov.sriov_obj,
+			 pf_dev->vport);
+
+	return rtn;
+
+err_group0:
+	kobject_put(pf_dev->sriov.groups_obj);
+	pf_dev->sriov.groups_obj = NULL;
+err_groups:
+	kobject_put(pf_dev->sriov.sriov_obj);
+	pf_dev->sriov.sriov_obj = NULL;
+
+	return rtn;
+}
+
+void zxdh_sriov_sysfs_exit(struct dh_core_dev *dev)
+{
+	// struct device *device = &dev->pdev->dev;
+	struct zxdh_pf_device *pf_dev = dh_core_priv(dev);
+
+	if (dev->coredev_type != DH_COREDEV_PF)
+		return;
+
+	LOG_INFO("enter\n");
+	zxdh_destroy_group_obj(pf_dev->sriov.group_0);
+	pf_dev->sriov.group_0 = NULL;
+
+	zxdh_cleanup_sysfs_group(pf_dev);
+
+	kobject_put(pf_dev->sriov.groups_obj);
+	pf_dev->sriov.groups_obj = NULL;
+
+	kobject_put(pf_dev->sriov.sriov_obj);
+	pf_dev->sriov.sriov_obj = NULL;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/wq.c b/src/net/drivers/net/ethernet/dinghai/wq.c
old mode 100755
new mode 100644
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/bar_chan_user/normal_send_eg.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/bar_chan_user/normal_send_eg.c
deleted file mode 100644
index a25dab83a4724a1c24f11990f119b17deae99fde..0000000000000000000000000000000000000000
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/bar_chan_user/normal_send_eg.c
+++ /dev/null
@@ -1,137 +0,0 @@
-#include <fcntl.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/eventfd.h>
-#include <sys/ioctl.h>
-#include <sys/mman.h>
-#include <sys/stat.h>
-#include <sys/types.h>
-#include <unistd.h>
-
-#define BAR_CHAN_PLOAD_SIZE      (2036)
-#define BAR_REPS_HDR_LEN         (4)
-#define DEVICE_FILE              "/dev/bar_ioctl_dev"
-#define BAR_IOCTL_CMD_NORMAL     _IOW('a', 1, msg_entity_t)
-
-struct zxdh_pci_bar_msg
-{
-    uint64_t virt_addr;               /**< 4k空间地址, 若src为MPF该参数不生效>**/
-    void *payload_addr;               /**< 消息净荷地址>**/
-    uint16_t payload_len;             /**< 消息净荷长度>**/
-    uint16_t emec;                    /**< 消息紧急类型>**/
-    uint16_t src;                     /**< 消息发送源，参考BAR_DRIVER_TYPE>**/
-    uint16_t dst;                     /**< 消息接收者，参考BAR_DRIVER_TYPE>**/
-    uint32_t module_id;                /**< 事件id>**/
-    uint16_t src_pcieid;              /**< 源  pcie_id>**/
-    uint16_t dst_pcieid;              /**< 目的pcie_id>**/
-};
-struct zxdh_msg_recviver_mem
-{
-    void *recv_buffer;                /**< 消息接收缓存>**/
-    uint16_t buffer_len;              /**< 消息缓存长度>**/
-};
-
-struct zxdh_ioctl_send_paras
-{
-    uint16_t pload_len;
-    uint16_t src;
-    uint16_t dst;
-    uint16_t event_id;
-};
-
-struct zxdh_ioctl_recv_paras
-{
-    int ioctl_state;    //ioctrl级别返回值
-    int bar_state;      //bar通道接口级别返回值
-};
-
-typedef struct normal_msg_entity
-{
-    union ioctl_ctrl_hdr                          //私有消息控制头
-    {
-        struct zxdh_ioctl_send_paras send_msg_hdr;          //普通消息发送头
-        struct zxdh_ioctl_recv_paras recv_msg_hdr;          //普通消息发送头
-    }hdr;
-    uint8_t pload[BAR_CHAN_PLOAD_SIZE + BAR_REPS_HDR_LEN];
-}msg_entity_t;
-
-struct zxdh_bar_reps_hdr
-{
-    uint8_t is_replied;
-    uint16_t reps_len;
-    uint8_t rsv;
-}__attribute__((packed));
-
-struct zxdh_bar_reps
-{
-    struct zxdh_bar_reps_hdr hdr;
-    uint8_t reps_data[BAR_CHAN_PLOAD_SIZE];
-}__attribute__((packed));
-
-int zxdh_bar_chan_mpf_ioctl_msg_send(struct zxdh_pci_bar_msg *in, struct zxdh_msg_recviver_mem *result)
-{
-    int fd, ret;
-    struct normal_msg_entity entity = {0};
-    struct zxdh_bar_reps *reps = NULL;
-
-    entity.hdr.send_msg_hdr.pload_len = in->payload_len;
-    entity.hdr.send_msg_hdr.src = in->src;
-    entity.hdr.send_msg_hdr.dst = in->dst;
-    entity.hdr.send_msg_hdr.event_id = in->module_id;
-
-    /* 用户态长度异常*/
-    if (in->payload_len > BAR_CHAN_PLOAD_SIZE)
-    {
-        return -1;
-    }
-    /* 拷贝消息到iotcl结构体*/
-    memcpy(entity.pload, in->payload_addr, in->payload_len);
-
-    fd = open(DEVICE_FILE, O_RDWR);
-    if (fd < 0) {
-        perror("Failed to open the device.");
-        return 1;
-    }
-
-    ret = ioctl(fd, BAR_IOCTL_CMD_NORMAL, &entity);
-    if (ret < 0) {
-        perror("IOCTL command failed.");
-        ret = 1;
-        goto out;
-    }
-    printf("reps: 0x%llx.\n", *(uint64_t*)entity.pload);
-
-    /* ioctl通信异常*/
-    if (entity.hdr.recv_msg_hdr.ioctl_state != 0)
-    {
-        //return IOCTL_ERR
-        printf("ioctl failed, state: %d\n", entity.hdr.recv_msg_hdr.ioctl_state);
-        ret = -1;
-        goto out;
-    }
-
-    /* 调用bar通道内核态接口错误*/
-    if (entity.hdr.recv_msg_hdr.bar_state != 0)
-    {
-        //return IOCTL_ERR
-        printf("bar send err, state: %d\n", entity.hdr.recv_msg_hdr.bar_state);
-        ret = entity.hdr.recv_msg_hdr.bar_state;
-        goto out;
-    }
-
-    /* 判断返回的消息长度是否足够放下*/
-    reps = (struct zxdh_bar_reps *)(entity.pload);
-    if (reps->hdr.reps_len + 4 > result->buffer_len)
-    {
-        printf("reps_len is %d, but buffer_len is%d.\n", reps->hdr.reps_len + 4,
-                                                         result->buffer_len);
-        ret = -1;
-        goto out;
-    }
-    memcpy(result->recv_buffer, reps, reps->hdr.reps_len + 4);
-out:
-    close(fd);
-    return 0;
-}
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/bar_chan_user/pci_res_query_eg.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/bar_chan_user/pci_res_query_eg.c
deleted file mode 100644
index b7ca92e47e6a09edd77b3f4d23ee79d8dc85f578..0000000000000000000000000000000000000000
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/bar_chan_user/pci_res_query_eg.c
+++ /dev/null
@@ -1,214 +0,0 @@
-#include <fcntl.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/eventfd.h>
-#include <sys/ioctl.h>
-#include <sys/mman.h>
-#include <sys/stat.h>
-#include <sys/types.h>
-#include <unistd.h>
-
-#define DEVICE_FILE                 "/dev/bar_ioctl_dev"
-#define ZXDH_PF_DEV_NUM             (40)
-#define BAR_IOCTL_CMD_SINGLE_DEV    _IOW('a', 2, pci_res_st)
-#define BAR_IOCTL_CMD_ALL_DEV       _IOW('a', 3, pci_res_st)
-#define PF_PCIE_ID(pf_idx)          (((pf_idx % 8) << 8) | (1 << 11) | ((pf_idx / 8) << 12))
-
-struct zxdh_mpf_pci_res_item
-{
-    uint16_t device_id;
-    uint16_t pcie_id;
-    uint16_t bdf;
-    uint8_t  link_state;
-    uint8_t  dev_type;
-    uint16_t  total_vfs;
-    uint16_t  initial_vfs;
-    uint16_t  num_vfs;
-    uint8_t  vf_stride;
-    uint8_t  first_vf_offset;
-    int res;
-    uint8_t  pad[4];   //预留字段
-};
-
-/* zf内核态和risc通信的约定结构体*/
-struct zxdh_mpf_pci_res_list
-{
-    uint16_t num;
-    uint16_t verno;   //版本号
-    int res;       //0表示返回成功， 其他表示失败， 包括消息发送失败
-    struct zxdh_mpf_pci_res_item  pci_res_lis[ZXDH_PF_DEV_NUM];
-};
-
-struct zxdh_mpf_query_pci_res_msg
-{
-    uint16_t pcie_id;
-    uint8_t  dev_type;
-    uint8_t  pad[5];
-    struct zxdh_mpf_pci_res_list reply;
-};
-
-typedef struct zxdh_mpf_query_bar_msg
-{
-    int ioctl_state;
-    int bar_state;
-    struct zxdh_mpf_query_pci_res_msg pci_res_msg;
-}pci_res_st;
-
-void print_pf_pci_res(struct zxdh_mpf_pci_res_item *item)
-{
-    printf("device_id: 0x%x.\n", item->device_id);
-    printf("link_state: %d.\n",item->link_state);
-    printf("pcie_id: 0x%x.\n",item->pcie_id);
-    printf("bdf: 0x%x.\n",item->bdf);
-    printf("dev_type: %d.\n",item->dev_type);
-    printf("total_vfs: %d.\n",item->total_vfs);
-    printf("initial_vfs: %d.\n",item->initial_vfs);
-    printf("num_vfs: %d.\n",item->num_vfs);
-    printf("vf_stride: %d.\n",item->vf_stride);
-    printf("first_vf_offset: %d.\n",item->first_vf_offset);
-    return;
-}
-
-static int zxdh_get_dev_pci_resource(uint16_t pcie_id, struct zxdh_mpf_query_bar_msg *data, int cmd)
-{
-    int fd, ret;
-    struct zxdh_mpf_query_bar_msg msg = {0};
-
-    msg.pci_res_msg.pcie_id = pcie_id;
-    msg.pci_res_msg.dev_type = 8;
-
-    fd = open(DEVICE_FILE, O_RDWR);
-    if (fd < 0)
-    {
-        perror("Failed to open the device.");
-        return 1;
-    }
-
-    ret = ioctl(fd, cmd, &msg);
-    if (ret < 0)
-    {
-        perror("IOCTL command failed.");
-        ret = 1;
-        goto out;
-    }
-
-    /* ioctl通信异常*/
-    if (msg.ioctl_state != 0)
-    {
-        //return IOCTL_ERR
-        printf("ioctl failed, state: %d\n", msg.ioctl_state);
-        ret = -1;
-        goto out;
-    }
-
-    /* 调用bar通道内核态接口错误*/
-    if (msg.bar_state != 0)
-    {
-        //return IOCTL_ERR
-        printf("bar send err, state: %d\n", msg.bar_state);
-        ret = msg.bar_state;
-        goto out;
-    }
-
-    *data = msg;
-out:
-    close(fd);
-    return ret;
-}
-
-int zxdh_get_dev_pci_resource_single(uint16_t pcie_id, struct zxdh_mpf_query_bar_msg *data)
-{
-    return zxdh_get_dev_pci_resource(pcie_id, data, BAR_IOCTL_CMD_SINGLE_DEV);
-}
-
-int zxdh_get_dev_pci_resource_all(struct zxdh_mpf_query_bar_msg *data)
-{
-    return zxdh_get_dev_pci_resource(0, data, BAR_IOCTL_CMD_ALL_DEV);
-}
-
-void test_pci_res_query_single(uint16_t pcie_id)
-{
-    int ret = 0;
-    struct zxdh_mpf_query_bar_msg data = {0};
-
-    printf("**************pcie_id: 0x%x**************.\n", pcie_id);
-    ret = zxdh_get_dev_pci_resource_single(pcie_id, &data);
-    if (ret != 0)
-    {
-        printf("ioctl msg failed, ret: %d.\n", ret);
-        return;
-    }
-    if (data.pci_res_msg.reply.res != 0)
-    {
-        printf("data.pci_res_msg.reply.res is %d.\n", data.pci_res_msg.reply.res);
-        return;
-    }
-    print_pf_pci_res(&data.pci_res_msg.reply.pci_res_lis[0]);
-    return;
-}
-
-void test_pci_res_query_all()
-{
-    int pf_idx = 0;
-    int ret = 0;
-    uint16_t pcie_id = 0;
-    struct zxdh_mpf_query_bar_msg data = {0};
-
-    ret = zxdh_get_dev_pci_resource_all(&data);
-    if (ret != 0)
-    {
-        printf("ioctl msg failed, ret:%d.\n", ret);
-    }
-
-    printf("res: %d.\n", data.pci_res_msg.reply.res);
-    printf("num: %d.\n", data.pci_res_msg.reply.num);
-
-    for (pf_idx = 0; pf_idx < 40; pf_idx++)
-   {
-       printf("********%dth dev, ep:%d, pf: %d**********.\n", pf_idx, pf_idx / 8, pf_idx % 8);
-
-       if (data.pci_res_msg.reply.pci_res_lis[pf_idx].res != 0)
-       {
-           printf("invalid res.\n");
-           continue;
-       }
-           print_pf_pci_res(&data.pci_res_msg.reply.pci_res_lis[pf_idx]);
-    }
-}
-
-int main(int argc, char *argv[])
-{
-    uint16_t pcie_id = 0;
-
-    if (argc < 2)
-    {
-        goto help;
-    }
-    if (strcmp(argv[1], "all") == 0)
-    {
-        test_pci_res_query_all();
-        goto out;
-    }
-    else if(strcmp(argv[1], "dev") == 0)
-    {
-        if (argc < 3)
-        {
-            goto help;
-        }
-        pcie_id = strtol(argv[2],NULL, 16);
-        test_pci_res_query_single(pcie_id);
-        goto out;
-    }
-    else
-    {
-        goto help;
-    }
-
-help:
-    printf("./test all ------------------print all pci_dev resources.\n");
-    printf("./test dev [pcie_id] --------print pci_dev resource.\n");
-out:
-    return 0;
-}
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/cfg_sf.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/cfg_sf.c
old mode 100755
new mode 100644
index 1927049458b1df3dbbc93af3cea9f4a67230063b..2cbf625451aa49442ac1e9f59073e994a5002f58
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/cfg_sf.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/cfg_sf.c
@@ -1,53 +1,58 @@
-#include <linux/kernel.h>
-#include <linux/dinghai/driver.h>
-
-#include "cfg_sf.h"
-
-static int32_t zxdh_cfg_resume(struct zxdh_auxiliary_device *adev)
-{
-    return 0;
-}
-
-static int32_t zxdh_cfg_suspend(struct zxdh_auxiliary_device *adev, pm_message_t state)
-{
-    return 0;
-}
-
-static int32_t zxdh_cfg_probe(struct zxdh_auxiliary_device *adev,
-                              const struct zxdh_auxiliary_device_id *id)
-{
-    struct cfg_sf_dev * __attribute__((unused)) cfg_sf_dev = container_of(adev, struct cfg_sf_dev, adev);
-
-    return 0;
-}
-
-static int32_t zxdh_cfg_remove(struct zxdh_auxiliary_device *adev)
-{
-    return 0;
-}
-
-static const struct zxdh_auxiliary_device_id zxdh_cfg_id_table[] = {
-    { .name = ZXDH_EN_SF_NAME ".mpf_cfg", },
-    {},
-};
-
-//MODULE_DEVICE_TABLE(auxiliary_zxdh_id_table, zxdh_cfg_id_table);
-
-static struct zxdh_auxiliary_driver zxdh_cfg_driver = {
-    .name     = "mpf_cfg",
-    .probe    = zxdh_cfg_probe,
-    .remove   = zxdh_cfg_remove,
-    .suspend  = zxdh_cfg_suspend,
-    .resume   = zxdh_cfg_resume,
-    .id_table = zxdh_cfg_id_table,
-};
-
-int32_t zxdh_mpf_sf_driver_register(void)
-{
-    return zxdh_auxiliary_driver_register(&zxdh_cfg_driver);;
-}
-
-void zxdh_mpf_sf_driver_uregister(void)
-{
-    zxdh_auxiliary_driver_unregister(&zxdh_cfg_driver);;
-}
+#include <linux/kernel.h>
+#include <linux/dinghai/driver.h>
+#include "cfg_sf.h"
+
+static int32_t zxdh_cfg_resume(struct auxiliary_device *adev)
+{
+	return 0;
+}
+
+static int32_t zxdh_cfg_suspend(struct auxiliary_device *adev,
+								pm_message_t state)
+{
+	return 0;
+}
+
+static int32_t zxdh_cfg_probe(struct auxiliary_device *adev,
+							  const struct auxiliary_device_id *id)
+{
+	struct cfg_sf_dev *__attribute__((unused))
+	cfg_sf_dev = container_of(adev, struct cfg_sf_dev, adev);
+
+	return 0;
+}
+
+static int32_t zxdh_cfg_remove(struct auxiliary_device *adev)
+{
+	return 0;
+}
+
+static const struct auxiliary_device_id zxdh_cfg_id_table[] = {
+	{
+			.name = ZXDH_EN_SF_NAME ".mpf_cfg",
+	},
+	{},
+};
+
+// MODULE_DEVICE_TABLE(auxiliary_zxdh_id_table, zxdh_cfg_id_table);
+
+static struct auxiliary_driver zxdh_cfg_driver = {
+	.name = "mpf_cfg",
+	.probe = zxdh_cfg_probe,
+	.remove = zxdh_cfg_remove,
+	.suspend = zxdh_cfg_suspend,
+	.resume = zxdh_cfg_resume,
+	.id_table = zxdh_cfg_id_table,
+};
+
+int32_t zxdh_mpf_sf_driver_register(void)
+{
+	return auxiliary_driver_register(&zxdh_cfg_driver);
+	;
+}
+
+void zxdh_mpf_sf_driver_uregister(void)
+{
+	auxiliary_driver_unregister(&zxdh_cfg_driver);
+	;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/cfg_sf.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/cfg_sf.h
old mode 100755
new mode 100644
index ec0fdd081cedd95474b33d6fe96020044977270a..2d25fe42e856669e62f2e1a0ed5f0aad6618834b
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/cfg_sf.h
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/cfg_sf.h
@@ -1,30 +1,31 @@
-#ifndef __ZXDH_MPF_CFG_SF_H__
-#define __ZXDH_MPF_CFG_SF_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/auxiliary_bus.h>
-#include <linux/dinghai/driver.h>
-
-struct cfg_sf_ops {
-
-};
-
-struct cfg_sf_dev {
-    struct zxdh_auxiliary_device adev;
-    struct dh_core_dev *dh_dev;
-    struct cfg_sf_ops *ops;
-};
-
-int32_t zxdh_mpf_sf_driver_register(void);
-void zxdh_mpf_sf_driver_uregister(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
+#ifndef __ZXDH_MPF_CFG_SF_H__
+#define __ZXDH_MPF_CFG_SF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef AUX_BUS_NO_SUPPORT
+#include <linux/dinghai/auxiliary_bus.h>
+#else
+#include <linux/auxiliary_bus.h>
+#endif
+#include <linux/dinghai/driver.h>
+
+struct cfg_sf_ops {
+};
+
+struct cfg_sf_dev {
+	struct auxiliary_device adev;
+	struct dh_core_dev *dh_dev;
+	struct cfg_sf_ops *ops;
+};
+
+int32_t zxdh_mpf_sf_driver_register(void);
+void zxdh_mpf_sf_driver_uregister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/devlink.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/devlink.c
old mode 100755
new mode 100644
index e89a752f121155b5a7f48b8bb2474eb209a61bca..9fdaebdbd4d2c0b11d8eb4f46f1bcb9deb5f81aa
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/devlink.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/devlink.c
@@ -1,130 +1,124 @@
-#include <linux/dinghai/driver.h>
-#include <net/devlink.h>
-#include "devlink.h"
-
-struct devlink_ops dh_mpf_devlink_ops = {
-
-};
-
-enum {
-    DH_MPF_PARAMS_MAX,
-};
-
-static int32_t __attribute__((unused)) sample_check(struct dh_core_dev *dev)
-{
-    return 1;
-}
-
-enum dh_mpf_devlink_param_id {
-    DH_MPF_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
-    DH_MPF_DEVLINK_PARAM_ID_SAMPLE,
-};
-
-
-static int32_t dh_devlink_sample_set(struct devlink *devlink, uint32_t id,
-                              struct devlink_param_gset_ctx *ctx)
-{
-    struct dh_core_dev * __attribute__((unused)) dev = devlink_priv(devlink);
-
-    return 0;
-}
-
-static int32_t dh_devlink_sample_get(struct devlink *devlink, uint32_t id,
-                              struct devlink_param_gset_ctx *ctx)
-{
-    struct dh_core_dev * __attribute__((unused)) dev = devlink_priv(devlink);
-
-    return 0;
-}
-
-#ifdef HAVE_DEVLINK_PARAM_REGISTER
-static const struct devlink_params {
-    const char *name;
-    int32_t (*check)(struct dh_core_dev *dev);
-    struct devlink_param param;
-} devlink_params[] = {
-    [DH_MPF_PARAMS_MAX] = { .name = "sample",
-                            .check = &sample_check,
-                            .param = DEVLINK_PARAM_DRIVER(DH_MPF_DEVLINK_PARAM_ID_SAMPLE,
-                                                          "sample", DEVLINK_PARAM_TYPE_BOOL,
-                                                          BIT(DEVLINK_PARAM_CMODE_RUNTIME),dh_devlink_sample_get,
-                                                          dh_devlink_sample_set,
-                                                          NULL),
-                          }
-};
-
-static int32_t params_register(struct devlink *devlink)
-{
-    int32_t i = 0;
-    int32_t err = 0;
-    struct dh_core_dev *dh_dev = devlink_priv(devlink);
-
-    for (i = 0; i < ARRAY_SIZE(devlink_params); i++)
-    {
-        if(devlink_params[i].check(dh_dev))
-        {
-            err = devlink_param_register(devlink, &devlink_params[i].param);
-            if (err)
-            {
-               goto rollback;
-            }
-        }
-    }
-
-    return 0;
-
-rollback:
-    if (i == 0)
-    {
-        return err;
-    }
-
-    for (; i > 0; i--)
-    {
-        devlink_param_unregister(devlink, &devlink_params[i].param);
-    }
-
-    return err;
-}
-
-static int32_t params_unregister(struct devlink *devlink)
-{
-    int32_t i = 0;
-
-    for (i = 0; i < ARRAY_SIZE(devlink_params); i++)
-    {
-        devlink_param_unregister(devlink, &devlink_params[i].param);
-    }
-
-    return 0;
-}
-#else 
-static struct devlink_param devlink_params [] = {
-    [DH_MPF_PARAMS_MAX] = DEVLINK_PARAM_DRIVER(DH_MPF_DEVLINK_PARAM_ID_SAMPLE,
-                                                          "sample", DEVLINK_PARAM_TYPE_BOOL,
-                                                          BIT(DEVLINK_PARAM_CMODE_RUNTIME),dh_devlink_sample_get,
-                                                          dh_devlink_sample_set,
-                                                          NULL),
-};
-
-static int32_t params_register(struct devlink *devlink)
-{
-    struct dh_core_dev * __attribute__((unused)) dh_dev = devlink_priv(devlink);
-    int32_t err = 0;
-
-    err = devlink_params_register(devlink, devlink_params, ARRAY_SIZE(devlink_params));
-
-    return err;
-}
-static int32_t params_unregister(struct devlink *devlink)
-{
-    devlink_params_unregister(devlink, devlink_params, ARRAY_SIZE(devlink_params));
-
-    return 0;
-}
-#endif
-
-struct dh_core_devlink_ops dh_mpf_core_devlink_ops = {
-    .params_register   =  params_register,
-    .params_unregister =  params_unregister
-};
+#include <linux/dinghai/driver.h>
+#include <net/devlink.h>
+#include "devlink.h"
+
+struct devlink_ops dh_mpf_devlink_ops = {
+
+};
+
+enum {
+	DH_MPF_PARAMS_MAX,
+};
+
+static int32_t __attribute__((unused)) sample_check(struct dh_core_dev *dev)
+{
+	return 1;
+}
+
+enum dh_mpf_devlink_param_id {
+	DH_MPF_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
+	DH_MPF_DEVLINK_PARAM_ID_SAMPLE,
+};
+
+static int32_t dh_devlink_sample_set(struct devlink *devlink, uint32_t id,
+									 struct devlink_param_gset_ctx *ctx)
+{
+	struct dh_core_dev *__attribute__((unused)) dev = devlink_priv(devlink);
+
+	return 0;
+}
+
+static int32_t dh_devlink_sample_get(struct devlink *devlink, uint32_t id,
+									 struct devlink_param_gset_ctx *ctx)
+{
+	struct dh_core_dev *__attribute__((unused)) dev = devlink_priv(devlink);
+
+	return 0;
+}
+
+#ifdef HAVE_DEVLINK_PARAM_REGISTER
+static const struct devlink_params {
+	const char *name;
+	int32_t (*check)(struct dh_core_dev *dev);
+	struct devlink_param param;
+} devlink_params[] = { [DH_MPF_PARAMS_MAX] = {
+							   .name = "sample",
+							   .check = &sample_check,
+							   .param = DEVLINK_PARAM_DRIVER(
+									   DH_MPF_DEVLINK_PARAM_ID_SAMPLE, "sample",
+									   DEVLINK_PARAM_TYPE_BOOL,
+									   BIT(DEVLINK_PARAM_CMODE_RUNTIME),
+									   dh_devlink_sample_get,
+									   dh_devlink_sample_set, NULL),
+					   } };
+
+static int32_t params_register(struct devlink *devlink)
+{
+	int32_t i = 0;
+	int32_t err = 0;
+	struct dh_core_dev *dh_dev = devlink_priv(devlink);
+
+	for (i = 0; i < ARRAY_SIZE(devlink_params); i++) {
+		if (devlink_params[i].check(dh_dev)) {
+			err = devlink_param_register(devlink, &devlink_params[i].param);
+			if (err) {
+				goto rollback;
+			}
+		}
+	}
+
+	return 0;
+
+rollback:
+	if (i == 0) {
+		return err;
+	}
+
+	for (; i > 0; i--) {
+		devlink_param_unregister(devlink, &devlink_params[i].param);
+	}
+
+	return err;
+}
+
+static int32_t params_unregister(struct devlink *devlink)
+{
+	int32_t i = 0;
+
+	for (i = 0; i < ARRAY_SIZE(devlink_params); i++) {
+		devlink_param_unregister(devlink, &devlink_params[i].param);
+	}
+
+	return 0;
+}
+#else
+static struct devlink_param devlink_params[] = {
+	[DH_MPF_PARAMS_MAX] = DEVLINK_PARAM_DRIVER(
+			DH_MPF_DEVLINK_PARAM_ID_SAMPLE, "sample", DEVLINK_PARAM_TYPE_BOOL,
+			BIT(DEVLINK_PARAM_CMODE_RUNTIME), dh_devlink_sample_get,
+			dh_devlink_sample_set, NULL),
+};
+
+static int32_t params_register(struct devlink *devlink)
+{
+	struct dh_core_dev *__attribute__((unused)) dh_dev = devlink_priv(devlink);
+	int32_t err = 0;
+
+	err = devlink_params_register(devlink, devlink_params,
+								  ARRAY_SIZE(devlink_params));
+
+	return err;
+}
+static int32_t params_unregister(struct devlink *devlink)
+{
+	devlink_params_unregister(devlink, devlink_params,
+							  ARRAY_SIZE(devlink_params));
+
+	return 0;
+}
+#endif
+
+struct dh_core_devlink_ops dh_mpf_core_devlink_ops = {
+	.params_register = params_register,
+	.params_unregister = params_unregister
+};
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/devlink.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/devlink.h
old mode 100755
new mode 100644
index a45fd1009d0f0a86da48b4a7acc40eaad9b9fa2e..7dea3be9aad73e4359eaf6eea720c2fcf773a933
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/devlink.h
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/devlink.h
@@ -1,16 +1,14 @@
-#ifndef __ZXDH_MPF_DEVLINK_H__
-#define __ZXDH_MPF_DEVLINK_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/devlink.h>
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef __ZXDH_MPF_DEVLINK_H__
+#define __ZXDH_MPF_DEVLINK_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/devlink.h>
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/dmaengine.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/dmaengine.c
index a768da496a616ace6a93cbbb62dd2de36441088a..01300f656d06d46434fa95f1513d4107221555c6 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/dmaengine.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/dmaengine.c
@@ -37,8 +37,7 @@ static struct dentry *rootdir;
 
 static void zxdh_dmaengine_debug_register(struct dma_device *dma_dev)
 {
-	dma_dev->dbg_dev_root = debugfs_create_dir(dev_name(dma_dev->dev),
-						   rootdir);
+	dma_dev->dbg_dev_root = debugfs_create_dir(dev_name(dma_dev->dev), rootdir);
 	if (IS_ERR(dma_dev->dbg_dev_root))
 		dma_dev->dbg_dev_root = NULL;
 }
@@ -50,18 +49,18 @@ static void zxdh_dmaengine_debug_unregister(struct dma_device *dma_dev)
 }
 
 static void zxdh_dmaengine_dbg_summary_show(struct seq_file *s,
-				       struct dma_device *dma_dev)
+											struct dma_device *dma_dev)
 {
 	struct dma_chan *chan;
 
 	list_for_each_entry(chan, &dma_dev->channels, device_node) {
 		if (chan->client_count) {
 			seq_printf(s, " %-13s| %s", dma_chan_name(chan),
-				   chan->dbg_client_name ?: "in-use");
+					   chan->dbg_client_name ?: "in-use");
 
 			if (chan->router)
 				seq_printf(s, " (via router: %s)\n",
-					dev_name(chan->router->dev));
+						   dev_name(chan->router->dev));
 			else
 				seq_puts(s, "\n");
 		}
@@ -74,9 +73,8 @@ static int zxdh_dmaengine_summary_show(struct seq_file *s, void *data)
 
 	mutex_lock(&dma_list_mutex);
 	list_for_each_entry(dma_dev, &dma_device_list, global_node) {
-		seq_printf(s, "dma%d (%s): number of channels: %u\n",
-			   dma_dev->dev_id, dev_name(dma_dev->dev),
-			   dma_dev->chancnt);
+		seq_printf(s, "dma%d (%s): number of channels: %u\n", dma_dev->dev_id,
+				   dev_name(dma_dev->dev), dma_dev->chancnt);
 
 		if (dma_dev->dbg_summary_show)
 			dma_dev->dbg_summary_show(s, dma_dev);
@@ -98,21 +96,25 @@ static void __init zxdh_dmaengine_debugfs_init(void)
 
 	/* /sys/kernel/debug/dmaengine/summary */
 	debugfs_create_file("summary", 0444, rootdir, NULL,
-			    &dmaengine_summary_fops);
+						&dmaengine_summary_fops);
 }
 #else
-static inline void zxdh_dmaengine_debugfs_init(void) { }
+static inline void zxdh_dmaengine_debugfs_init(void)
+{
+}
 static inline int zxdh_dmaengine_debug_register(struct dma_device *dma_dev)
 {
 	return 0;
 }
 
-static inline void zxdh_dmaengine_debug_unregister(struct dma_device *dma_dev) { }
-#endif	/* DEBUG_FS */
+static inline void zxdh_dmaengine_debug_unregister(struct dma_device *dma_dev)
+{
+}
+#endif /* DEBUG_FS */
 
 /* --- sysfs implementation --- */
 
-#define DMA_SLAVE_NAME	"slave"
+#define DMA_SLAVE_NAME "slave"
 
 /**
  * zxdh_dev_to_dma_chan - convert a device pointer to its sysfs container object
@@ -129,7 +131,7 @@ static struct dma_chan *zxdh_dev_to_dma_chan(struct device *dev)
 }
 
 static ssize_t zxdh_memcpy_count_show(struct device *dev,
-				 struct device_attribute *attr, char *buf)
+									  struct device_attribute *attr, char *buf)
 {
 	struct dma_chan *chan;
 	unsigned long count = 0;
@@ -151,7 +153,8 @@ static ssize_t zxdh_memcpy_count_show(struct device *dev,
 static DEVICE_ATTR_RO(memcpy_count);
 
 static ssize_t zxdh_bytes_transferred_show(struct device *dev,
-				      struct device_attribute *attr, char *buf)
+										   struct device_attribute *attr,
+										   char *buf)
 {
 	struct dma_chan *chan;
 	unsigned long count = 0;
@@ -172,8 +175,8 @@ static ssize_t zxdh_bytes_transferred_show(struct device *dev,
 }
 static DEVICE_ATTR_RO(bytes_transferred);
 
-static ssize_t zxdh_in_use_show(struct device *dev, struct device_attribute *attr,
-			   char *buf)
+static ssize_t zxdh_in_use_show(struct device *dev,
+								struct device_attribute *attr, char *buf)
 {
 	struct dma_chan *chan;
 	int err;
@@ -207,9 +210,9 @@ static void zxdh_chan_dev_release(struct device *dev)
 }
 
 static struct class dma_devclass = {
-	.name		= "dma",
-	.dev_groups	= dma_dev_groups,
-	.dev_release	= zxdh_chan_dev_release,
+	.name = "dma",
+	.dev_groups = dma_dev_groups,
+	.dev_release = zxdh_chan_dev_release,
 };
 
 /* --- client and device registration --- */
@@ -236,9 +239,9 @@ static int __init zxdh_dma_channel_table_init(void)
 	bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
 
 	/* 'interrupt', 'private', and 'slave' are channel capabilities,
-	 * but are not associated with an operation so they do not need
-	 * an entry in the channel_table
-	 */
+   * but are not associated with an operation so they do not need
+   * an entry in the channel_table
+   */
 	clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
 	clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
 	clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
@@ -262,7 +265,8 @@ static int __init zxdh_dma_channel_table_init(void)
 arch_initcall(zxdh_dma_channel_table_init);
 
 /**
- * zxdh_dma_chan_is_local - checks if the channel is in the same NUMA-node as the CPU
+ * zxdh_dma_chan_is_local - checks if the channel is in the same NUMA-node as
+ * the CPU
  * @chan:	DMA channel to test
  * @cpu:	CPU index which the channel should be close to
  *
@@ -271,12 +275,12 @@ arch_initcall(zxdh_dma_channel_table_init);
 static bool zxdh_dma_chan_is_local(struct dma_chan *chan, int cpu)
 {
 	int node = dev_to_node(chan->device->dev);
-	return node == NUMA_NO_NODE ||
-		cpumask_test_cpu(cpu, cpumask_of_node(node));
+	return node == NUMA_NO_NODE || cpumask_test_cpu(cpu, cpumask_of_node(node));
 }
 
 /**
- * zxdh_min_chan - finds the channel with min count and in the same NUMA-node as the CPU
+ * zxdh_min_chan - finds the channel with min count and in the same NUMA-node as
+ * the CPU
  * @cap:	capability to match
  * @cpu:	CPU index which the channel should be close to
  *
@@ -295,7 +299,7 @@ static struct dma_chan *zxdh_min_chan(enum dma_transaction_type cap, int cpu)
 
 	list_for_each_entry(device, &dma_device_list, global_node) {
 		if (!dma_has_cap(cap, device->cap_mask) ||
-		    dma_has_cap(DMA_PRIVATE, device->cap_mask))
+			dma_has_cap(DMA_PRIVATE, device->cap_mask))
 			continue;
 		list_for_each_entry(chan, &device->channels, device_node) {
 			if (!chan->client_count)
@@ -304,8 +308,7 @@ static struct dma_chan *zxdh_min_chan(enum dma_transaction_type cap, int cpu)
 				min = chan;
 
 			if (zxdh_dma_chan_is_local(chan, cpu))
-				if (!localmin ||
-				    chan->table_count < localmin->table_count)
+				if (!localmin || chan->table_count < localmin->table_count)
 					localmin = chan;
 		}
 	}
@@ -359,12 +362,11 @@ static void zxdh_dma_channel_rebalance(void)
 }
 
 static int zxdh_dma_device_satisfies_mask(struct dma_device *device,
-				     const dma_cap_mask_t *want)
+										  const dma_cap_mask_t *want)
 {
 	dma_cap_mask_t has;
 
-	bitmap_and(has.bits, want->bits, device->cap_mask.bits,
-		DMA_TX_TYPE_END);
+	bitmap_and(has.bits, want->bits, device->cap_mask.bits, DMA_TX_TYPE_END);
 	return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
 }
 
@@ -505,7 +507,6 @@ enum dma_status zxdh_dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
 	return status;
 }
 
-
 /**
  * zxdh_dma_find_channel - find a channel to carry out the operation
  * @tx_type:	transaction type
@@ -515,7 +516,6 @@ struct dma_chan *zxdh_dma_find_channel(enum dma_transaction_type tx_type)
 	return this_cpu_read(channel_table[tx_type]->chan);
 }
 
-
 /**
  * zxdh_dma_issue_pending_all - flush all pending operations across all channels
  */
@@ -535,7 +535,6 @@ void zxdh_dma_issue_pending_all(void)
 	rcu_read_unlock();
 }
 
-
 int zxdh_dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
 {
 	struct dma_device *device;
@@ -547,14 +546,14 @@ int zxdh_dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
 
 	/* check if the channel supports slave transactions */
 	if (!(test_bit(DMA_SLAVE, device->cap_mask.bits) ||
-	      test_bit(DMA_CYCLIC, device->cap_mask.bits)))
+		  test_bit(DMA_CYCLIC, device->cap_mask.bits)))
 		return -ENXIO;
 
 	/*
-	 * Check whether it reports it uses the generic slave
-	 * capabilities, if not, that means it doesn't support any
-	 * kind of slave capabilities reporting.
-	 */
+   * Check whether it reports it uses the generic slave
+   * capabilities, if not, that means it doesn't support any
+   * kind of slave capabilities reporting.
+   */
 	if (!device->directions)
 		return -ENXIO;
 
@@ -571,22 +570,21 @@ int zxdh_dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
 	caps->cmd_terminate = !!device->device_terminate_all;
 
 	/*
-	 * DMA engine device might be configured with non-uniformly
-	 * distributed slave capabilities per device channels. In this
-	 * case the corresponding driver may provide the device_caps
-	 * callback to override the generic capabilities with
-	 * channel-specific ones.
-	 */
+   * DMA engine device might be configured with non-uniformly
+   * distributed slave capabilities per device channels. In this
+   * case the corresponding driver may provide the device_caps
+   * callback to override the generic capabilities with
+   * channel-specific ones.
+   */
 	if (device->device_caps)
 		device->device_caps(chan, caps);
 
 	return 0;
 }
 
-
 static struct dma_chan *zxdh_private_candidate(const dma_cap_mask_t *mask,
-					  struct dma_device *dev,
-					  dma_filter_fn fn, void *fn_param)
+											   struct dma_device *dev,
+											   dma_filter_fn fn, void *fn_param)
 {
 	struct dma_chan *chan;
 
@@ -595,8 +593,8 @@ static struct dma_chan *zxdh_private_candidate(const dma_cap_mask_t *mask,
 		return NULL;
 	}
 	/* devices with multiple channels need special handling as we need to
-	 * ensure that all channels are either private or public.
-	 */
+   * ensure that all channels are either private or public.
+   */
 	if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
 		list_for_each_entry(chan, &dev->channels, device_node) {
 			/* some channels are already publicly allocated */
@@ -606,13 +604,12 @@ static struct dma_chan *zxdh_private_candidate(const dma_cap_mask_t *mask,
 
 	list_for_each_entry(chan, &dev->channels, device_node) {
 		if (chan->client_count) {
-			dev_dbg(dev->dev, "%s: %s busy\n",
-				 __func__, dma_chan_name(chan));
+			dev_dbg(dev->dev, "%s: %s busy\n", __func__, dma_chan_name(chan));
 			continue;
 		}
 		if (fn && !fn(chan, fn_param)) {
-			dev_dbg(dev->dev, "%s: %s filter said false\n",
-				 __func__, dma_chan_name(chan));
+			dev_dbg(dev->dev, "%s: %s filter said false\n", __func__,
+					dma_chan_name(chan));
 			continue;
 		}
 		return chan;
@@ -622,31 +619,30 @@ static struct dma_chan *zxdh_private_candidate(const dma_cap_mask_t *mask,
 }
 
 static struct dma_chan *zxdh_find_candidate(struct dma_device *device,
-				       const dma_cap_mask_t *mask,
-				       dma_filter_fn fn, void *fn_param)
+											const dma_cap_mask_t *mask,
+											dma_filter_fn fn, void *fn_param)
 {
 	struct dma_chan *chan = zxdh_private_candidate(mask, device, fn, fn_param);
 	int err;
 
 	if (chan) {
 		/* Found a suitable channel, try to grab, prep, and return it.
-		 * We first set DMA_PRIVATE to disable zxdh_balance_ref_count as this
-		 * channel will not be published in the general-purpose
-		 * allocator
-		 */
+     * We first set DMA_PRIVATE to disable zxdh_balance_ref_count as this
+     * channel will not be published in the general-purpose
+     * allocator
+     */
 		dma_cap_set(DMA_PRIVATE, device->cap_mask);
 		device->privatecnt++;
 		err = zxdh_dma_chan_get(chan);
 
 		if (err) {
 			if (err == -ENODEV) {
-				dev_dbg(device->dev, "%s: %s module removed\n",
-					__func__, dma_chan_name(chan));
+				dev_dbg(device->dev, "%s: %s module removed\n", __func__,
+						dma_chan_name(chan));
 				list_del_rcu(&device->global_node);
 			} else
-				dev_dbg(device->dev,
-					"%s: failed to get %s: (%d)\n",
-					 __func__, dma_chan_name(chan), err);
+				dev_dbg(device->dev, "%s: failed to get %s: (%d)\n", __func__,
+						dma_chan_name(chan), err);
 
 			if (--device->privatecnt == 0)
 				dma_cap_clear(DMA_PRIVATE, device->cap_mask);
@@ -676,9 +672,8 @@ struct dma_chan *zxdh_dma_get_slave_channel(struct dma_chan *chan)
 		device->privatecnt++;
 		err = zxdh_dma_chan_get(chan);
 		if (err) {
-			dev_dbg(chan->device->dev,
-				"%s: failed to get %s: (%d)\n",
-				__func__, dma_chan_name(chan), err);
+			dev_dbg(chan->device->dev, "%s: failed to get %s: (%d)\n", __func__,
+					dma_chan_name(chan), err);
 			chan = NULL;
 			if (--device->privatecnt == 0)
 				dma_cap_clear(DMA_PRIVATE, device->cap_mask);
@@ -688,11 +683,9 @@ struct dma_chan *zxdh_dma_get_slave_channel(struct dma_chan *chan)
 
 	mutex_unlock(&dma_list_mutex);
 
-
 	return chan;
 }
 
-
 struct dma_chan *zxdh_dma_get_any_slave_channel(struct dma_device *device)
 {
 	dma_cap_mask_t mask;
@@ -711,7 +704,6 @@ struct dma_chan *zxdh_dma_get_any_slave_channel(struct dma_device *device)
 	return IS_ERR(chan) ? NULL : chan;
 }
 
-
 /**
  * __zxdh__zxdh_dma_request_channel - try to allocate an exclusive channel
  * @mask:	capabilities that the channel must satisfy
@@ -722,8 +714,9 @@ struct dma_chan *zxdh_dma_get_any_slave_channel(struct dma_device *device)
  * Returns pointer to appropriate DMA channel on success or NULL.
  */
 struct dma_chan *__zxdh__zxdh_dma_request_channel(const dma_cap_mask_t *mask,
-				       dma_filter_fn fn, void *fn_param,
-				       struct device_node *np)
+												  dma_filter_fn fn,
+												  void *fn_param,
+												  struct device_node *np)
 {
 	struct dma_device *device, *_d;
 	struct dma_chan *chan = NULL;
@@ -743,18 +736,15 @@ struct dma_chan *__zxdh__zxdh_dma_request_channel(const dma_cap_mask_t *mask,
 	}
 	mutex_unlock(&dma_list_mutex);
 
-	pr_debug("%s: %s (%s)\n",
-		 __func__,
-		 chan ? "success" : "fail",
-		 chan ? dma_chan_name(chan) : NULL);
+	pr_debug("%s: %s (%s)\n", __func__, chan ? "success" : "fail",
+			 chan ? dma_chan_name(chan) : NULL);
 
 	return chan;
 }
 
-
-static const struct dma_slave_map *zxdh_dma_filter_match(struct dma_device *device,
-						    const char *name,
-						    struct device *dev)
+static const struct dma_slave_map *
+zxdh_dma_filter_match(struct dma_device *device, const char *name,
+					  struct device *dev)
 {
 	int i;
 
@@ -764,8 +754,7 @@ static const struct dma_slave_map *zxdh_dma_filter_match(struct dma_device *devi
 	for (i = 0; i < device->filter.mapcnt; i++) {
 		const struct dma_slave_map *map = &device->filter.map[i];
 
-		if (!strcmp(map->devname, dev_name(dev)) &&
-		    !strcmp(map->slave, name))
+		if (!strcmp(map->devname, dev_name(dev)) && !strcmp(map->slave, name))
 			return map;
 	}
 
@@ -823,8 +812,7 @@ struct dma_chan *zxdh_dma_request_chan(struct device *dev, const char *name)
 
 found:
 #ifdef CONFIG_DEBUG_FS
-	chan->dbg_client_name = kasprintf(GFP_KERNEL, "%s:%s", dev_name(dev),
-					  name);
+	chan->dbg_client_name = kasprintf(GFP_KERNEL, "%s:%s", dev_name(dev), name);
 #endif
 
 	chan->name = kasprintf(GFP_KERNEL, "dma:%s", name);
@@ -832,8 +820,7 @@ found:
 		return chan;
 	chan->slave = dev;
 
-	if (sysfs_create_link(&chan->dev->device.kobj, &dev->kobj,
-			      DMA_SLAVE_NAME))
+	if (sysfs_create_link(&chan->dev->device.kobj, &dev->kobj, DMA_SLAVE_NAME))
 		dev_warn(dev, "Cannot create DMA %s symlink\n", DMA_SLAVE_NAME);
 	if (sysfs_create_link(&dev->kobj, &chan->dev->device.kobj, chan->name))
 		dev_warn(dev, "Cannot create DMA %s symlink\n", chan->name);
@@ -841,9 +828,9 @@ found:
 	return chan;
 }
 
-
 /**
- * zxdh_dma_request_chan_by_mask - allocate a channel satisfying certain capabilities
+ * zxdh_dma_request_chan_by_mask - allocate a channel satisfying certain
+ * capabilities
  * @mask:	capabilities that the channel must satisfy
  *
  * Returns pointer to appropriate DMA channel on success or an error pointer.
@@ -868,12 +855,11 @@ struct dma_chan *zxdh_dma_request_chan_by_mask(const dma_cap_mask_t *mask)
 	return chan;
 }
 
-
 void zxdh_dma_release_channel(struct dma_chan *chan)
 {
 	mutex_lock(&dma_list_mutex);
-	WARN_ONCE(chan->client_count != 1,
-		  "chan reference count %d != 1\n", chan->client_count);
+	WARN_ONCE(chan->client_count != 1, "chan reference count %d != 1\n",
+			  chan->client_count);
 	zxdh_dma_chan_put(chan);
 	/* drop PRIVATE cap enabled by __zxdh__zxdh_dma_request_channel() */
 	if (--chan->device->privatecnt == 0)
@@ -894,7 +880,6 @@ void zxdh_dma_release_channel(struct dma_chan *chan)
 	mutex_unlock(&dma_list_mutex);
 }
 
-
 /**
  * zxdh_dmaengine_get - register interest in dma_channels
  */
@@ -918,22 +903,20 @@ void zxdh_dmaengine_get(void)
 				list_del_rcu(&device->global_node);
 				break;
 			} else if (err)
-				dev_dbg(chan->device->dev,
-					"%s: failed to get %s: (%d)\n",
-					__func__, dma_chan_name(chan), err);
+				dev_dbg(chan->device->dev, "%s: failed to get %s: (%d)\n",
+						__func__, dma_chan_name(chan), err);
 		}
 	}
 
 	/* if this is the first reference and there were channels
-	 * waiting we need to rebalance to get those channels
-	 * incorporated into the channel table
-	 */
+   * waiting we need to rebalance to get those channels
+   * incorporated into the channel table
+   */
 	if (dmaengine_ref_count == 1)
 		zxdh_dma_channel_rebalance();
 	mutex_unlock(&dma_list_mutex);
 }
 
-
 /**
  * zxdh_dmaengine_put - let DMA drivers be removed when ref_count == 0
  */
@@ -955,42 +938,41 @@ void zxdh_dmaengine_put(void)
 	mutex_unlock(&dma_list_mutex);
 }
 
-
 static bool zxdh_device_has_all_tx_types(struct dma_device *device)
 {
-	/* A device that satisfies this test has channels that will never cause
-	 * an async_tx channel switch event as all possible operation types can
-	 * be handled.
-	 */
-	#ifdef CONFIG_ASYNC_TX_DMA
+/* A device that satisfies this test has channels that will never cause
+ * an async_tx channel switch event as all possible operation types can
+ * be handled.
+ */
+#ifdef CONFIG_ASYNC_TX_DMA
 	if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
 		return false;
-	#endif
+#endif
 
-	#if IS_ENABLED(CONFIG_ASYNC_MEMCPY)
+#if IS_ENABLED(CONFIG_ASYNC_MEMCPY)
 	if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
 		return false;
-	#endif
+#endif
 
-	#if IS_ENABLED(CONFIG_ASYNC_XOR)
+#if IS_ENABLED(CONFIG_ASYNC_XOR)
 	if (!dma_has_cap(DMA_XOR, device->cap_mask))
 		return false;
 
-	#ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
+#ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
 	if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
 		return false;
-	#endif
-	#endif
+#endif
+#endif
 
-	#if IS_ENABLED(CONFIG_ASYNC_PQ)
+#if IS_ENABLED(CONFIG_ASYNC_PQ)
 	if (!dma_has_cap(DMA_PQ, device->cap_mask))
 		return false;
 
-	#ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
+#ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
 	if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
 		return false;
-	#endif
-	#endif
+#endif
+#endif
 
 	return true;
 }
@@ -1006,7 +988,7 @@ static int zxdh_get_dma_id(struct dma_device *device)
 }
 
 static int __zxdh_dma_async_device_channel_register(struct dma_device *device,
-					       struct dma_chan *chan)
+													struct dma_chan *chan)
 {
 	int rc;
 
@@ -1020,15 +1002,15 @@ static int __zxdh_dma_async_device_channel_register(struct dma_device *device,
 	}
 
 	/*
-	 * When the chan_id is a negative value, we are dynamically adding
-	 * the channel. Otherwise we are static enumerating.
-	 */
+   * When the chan_id is a negative value, we are dynamically adding
+   * the channel. Otherwise we are static enumerating.
+   */
 	mutex_lock(&device->chan_mutex);
 	chan->chan_id = ida_alloc(&device->chan_ida, GFP_KERNEL);
 	mutex_unlock(&device->chan_mutex);
 	if (chan->chan_id < 0) {
-		pr_err("%s: unable to alloc ida for chan: %d\n",
-		       __func__, chan->chan_id);
+		pr_err("%s: unable to alloc ida for chan: %d\n", __func__,
+			   chan->chan_id);
 		rc = chan->chan_id;
 		goto err_free_dev;
 	}
@@ -1037,8 +1019,8 @@ static int __zxdh_dma_async_device_channel_register(struct dma_device *device,
 	chan->dev->device.parent = device->dev;
 	chan->dev->chan = chan;
 	chan->dev->dev_id = device->dev_id;
-	dev_set_name(&chan->dev->device, "dma%dchan%d",
-		     device->dev_id, chan->chan_id);
+	dev_set_name(&chan->dev->device, "dma%dchan%d", device->dev_id,
+				 chan->chan_id);
 	rc = device_register(&chan->dev->device);
 	if (rc)
 		goto err_out_ida;
@@ -1047,20 +1029,20 @@ static int __zxdh_dma_async_device_channel_register(struct dma_device *device,
 
 	return 0;
 
- err_out_ida:
+err_out_ida:
 	mutex_lock(&device->chan_mutex);
 	ida_free(&device->chan_ida, chan->chan_id);
 	mutex_unlock(&device->chan_mutex);
- err_free_dev:
+err_free_dev:
 	kfree(chan->dev);
- err_free_local:
+err_free_local:
 	free_percpu(chan->local);
 	chan->local = NULL;
 	return rc;
 }
 
 int zxdh_dma_async_device_channel_register(struct dma_device *device,
-				      struct dma_chan *chan)
+										   struct dma_chan *chan)
 {
 	int rc;
 
@@ -1072,13 +1054,13 @@ int zxdh_dma_async_device_channel_register(struct dma_device *device,
 	return 0;
 }
 
-
-static void __zxdh__dma_async_device_channel_unregister(struct dma_device *device,
-						  struct dma_chan *chan)
+static void
+__zxdh__dma_async_device_channel_unregister(struct dma_device *device,
+											struct dma_chan *chan)
 {
 	WARN_ONCE(!device->device_release && chan->client_count,
-		  "%s called while %d clients hold a reference\n",
-		  __func__, chan->client_count);
+			  "%s called while %d clients hold a reference\n", __func__,
+			  chan->client_count);
 	mutex_lock(&dma_list_mutex);
 	device->chancnt--;
 	chan->dev->chan = NULL;
@@ -1091,25 +1073,25 @@ static void __zxdh__dma_async_device_channel_unregister(struct dma_device *devic
 }
 
 void zxdh_dma_async_device_channel_unregister(struct dma_device *device,
-					 struct dma_chan *chan)
+											  struct dma_chan *chan)
 {
 	__zxdh__dma_async_device_channel_unregister(device, chan);
 	zxdh_dma_channel_rebalance();
 }
 
-
 /**
  * dma_async_device_register - registers DMA devices found
  * @device:	pointer to &struct dma_device
  *
  * After calling this routine the structure should not be freed except in the
  * device_release() callback which will be called after
- * zxdh_dma_async_device_unregister() is called and no further references are taken.
+ * zxdh_dma_async_device_unregister() is called and no further references are
+ * taken.
  */
 int zxdh_dma_async_device_register(struct dma_device *device)
 {
 	int rc = 0;
-	struct dma_chan* chan = NULL;
+	struct dma_chan *chan = NULL;
 
 	DH_LOG_INFO(MODULE_MPF, "enter\n");
 
@@ -1124,97 +1106,104 @@ int zxdh_dma_async_device_register(struct dma_device *device)
 
 	device->owner = device->dev->driver->owner;
 
-	if (dma_has_cap(DMA_MEMCPY, device->cap_mask) && !device->device_prep_dma_memcpy) {
+	if (dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
+		!device->device_prep_dma_memcpy) {
 		dev_err(device->dev,
-			"Device claims capability %s, but op is not defined\n",
-			"DMA_MEMCPY");
+				"Device claims capability %s, but op is not defined\n",
+				"DMA_MEMCPY");
 		return -EIO;
 	}
 
-	if (dma_has_cap(DMA_MEMCPY_SG, device->cap_mask) && !device->device_prep_dma_memcpy_sg) {
+	if (dma_has_cap(DMA_MEMCPY_SG, device->cap_mask) &&
+		!device->device_prep_dma_memcpy_sg) {
 		dev_err(device->dev,
-			"Device claims capability %s, but op is not defined\n",
-			"DMA_MEMCPY_SG");
+				"Device claims capability %s, but op is not defined\n",
+				"DMA_MEMCPY_SG");
 		return -EIO;
 	}
 
-	if (dma_has_cap(DMA_XOR, device->cap_mask) && !device->device_prep_dma_xor) {
+	if (dma_has_cap(DMA_XOR, device->cap_mask) &&
+		!device->device_prep_dma_xor) {
 		dev_err(device->dev,
-			"Device claims capability %s, but op is not defined\n",
-			"DMA_XOR");
+				"Device claims capability %s, but op is not defined\n",
+				"DMA_XOR");
 		return -EIO;
 	}
 
-	if (dma_has_cap(DMA_XOR_VAL, device->cap_mask) && !device->device_prep_dma_xor_val) {
+	if (dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
+		!device->device_prep_dma_xor_val) {
 		dev_err(device->dev,
-			"Device claims capability %s, but op is not defined\n",
-			"DMA_XOR_VAL");
+				"Device claims capability %s, but op is not defined\n",
+				"DMA_XOR_VAL");
 		return -EIO;
 	}
 
 	if (dma_has_cap(DMA_PQ, device->cap_mask) && !device->device_prep_dma_pq) {
 		dev_err(device->dev,
-			"Device claims capability %s, but op is not defined\n",
-			"DMA_PQ");
+				"Device claims capability %s, but op is not defined\n",
+				"DMA_PQ");
 		return -EIO;
 	}
 
-	if (dma_has_cap(DMA_PQ_VAL, device->cap_mask) && !device->device_prep_dma_pq_val) {
+	if (dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
+		!device->device_prep_dma_pq_val) {
 		dev_err(device->dev,
-			"Device claims capability %s, but op is not defined\n",
-			"DMA_PQ_VAL");
+				"Device claims capability %s, but op is not defined\n",
+				"DMA_PQ_VAL");
 		return -EIO;
 	}
 
-	if (dma_has_cap(DMA_MEMSET, device->cap_mask) && !device->device_prep_dma_memset) {
+	if (dma_has_cap(DMA_MEMSET, device->cap_mask) &&
+		!device->device_prep_dma_memset) {
 		dev_err(device->dev,
-			"Device claims capability %s, but op is not defined\n",
-			"DMA_MEMSET");
+				"Device claims capability %s, but op is not defined\n",
+				"DMA_MEMSET");
 		return -EIO;
 	}
 
-	if (dma_has_cap(DMA_INTERRUPT, device->cap_mask) && !device->device_prep_dma_interrupt) {
+	if (dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
+		!device->device_prep_dma_interrupt) {
 		dev_err(device->dev,
-			"Device claims capability %s, but op is not defined\n",
-			"DMA_INTERRUPT");
+				"Device claims capability %s, but op is not defined\n",
+				"DMA_INTERRUPT");
 		return -EIO;
 	}
 
-	if (dma_has_cap(DMA_CYCLIC, device->cap_mask) && !device->device_prep_dma_cyclic) {
+	if (dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
+		!device->device_prep_dma_cyclic) {
 		dev_err(device->dev,
-			"Device claims capability %s, but op is not defined\n",
-			"DMA_CYCLIC");
+				"Device claims capability %s, but op is not defined\n",
+				"DMA_CYCLIC");
 		return -EIO;
 	}
 
-	if (dma_has_cap(DMA_INTERLEAVE, device->cap_mask) && !device->device_prep_interleaved_dma) {
+	if (dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
+		!device->device_prep_interleaved_dma) {
 		dev_err(device->dev,
-			"Device claims capability %s, but op is not defined\n",
-			"DMA_INTERLEAVE");
+				"Device claims capability %s, but op is not defined\n",
+				"DMA_INTERLEAVE");
 		return -EIO;
 	}
 
-
 	if (!device->device_tx_status) {
 		dev_err(device->dev, "Device tx_status is not defined\n");
 		return -EIO;
 	}
 
-
 	if (!device->device_issue_pending) {
 		dev_err(device->dev, "Device issue_pending is not defined\n");
 		return -EIO;
 	}
 
 	if (!device->device_release)
-		dev_dbg(device->dev,
-			 "WARN: Device release is not defined so it is not safe to unbind this driver while in use\n");
+		dev_dbg(device->dev, "WARN: Device release is not defined so it is not "
+							 "safe to unbind this driver while in use\n");
 
 	kref_init(&device->ref);
 
 	/* note: this only matters in the
-	 * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
-	 */
+   * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
+   */
 	if (zxdh_device_has_all_tx_types(device))
 		dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
 
@@ -1237,13 +1226,13 @@ int zxdh_dma_async_device_register(struct dma_device *device)
 	if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
 		list_for_each_entry(chan, &device->channels, device_node) {
 			/* if clients are already waiting for channels we need
-			 * to take references on their behalf
-			 */
+			* to take references on their behalf
+			*/
 			if (zxdh_dma_chan_get(chan) == -ENODEV) {
 				/* note we can only get here for the first
-				 * channel as the remaining channels are
-				 * guaranteed to get a reference
-				 */
+				* channel as the remaining channels are
+				* guaranteed to get a reference
+				*/
 				rc = -ENODEV;
 				mutex_unlock(&dma_list_mutex);
 				goto err_out;
@@ -1251,7 +1240,7 @@ int zxdh_dma_async_device_register(struct dma_device *device)
 		}
 	list_add_tail_rcu(&device->global_node, &dma_device_list);
 	if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
-		device->privatecnt++;	/* Always private */
+		device->privatecnt++; /* Always private */
 	zxdh_dma_channel_rebalance();
 	mutex_unlock(&dma_list_mutex);
 
@@ -1278,7 +1267,6 @@ err_out:
 	return rc;
 }
 
-
 /**
  * zxdh_dma_async_device_unregister - unregister a DMA device
  * @device:	pointer to &struct dma_device
@@ -1297,9 +1285,9 @@ void zxdh_dma_async_device_unregister(struct dma_device *device)
 
 	mutex_lock(&dma_list_mutex);
 	/*
-	 * setting DMA_PRIVATE ensures the device being torn down will not
-	 * be used in the channel_table
-	 */
+   * setting DMA_PRIVATE ensures the device being torn down will not
+   * be used in the channel_table
+   */
 	dma_cap_set(DMA_PRIVATE, device->cap_mask);
 	zxdh_dma_channel_rebalance();
 	ida_free(&dma_ida, device->dev_id);
@@ -1307,7 +1295,6 @@ void zxdh_dma_async_device_unregister(struct dma_device *device)
 	mutex_unlock(&dma_list_mutex);
 }
 
-
 static void zxdh_dmam_device_release(struct device *dev, void *res)
 {
 	struct dma_device *device;
@@ -1342,7 +1329,6 @@ int zxdh_dmaenginem_async_device_register(struct dma_device *device)
 	return ret;
 }
 
-
 struct zxdh_dmaengine_unmap_pool {
 	struct kmem_cache *cache;
 	const char *name;
@@ -1350,14 +1336,17 @@ struct zxdh_dmaengine_unmap_pool {
 	size_t size;
 };
 
-#define __UNMAP_POOL(x) { .size = x, .name = "dmaengine-unmap-" __stringify(x) }
+#define __UNMAP_POOL(x)                                      \
+	{                                                        \
+		.size = x, .name = "dmaengine-unmap-" __stringify(x) \
+	}
 static struct zxdh_dmaengine_unmap_pool unmap_pool[] = {
 	__UNMAP_POOL(2),
-	#if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
+#if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
 	__UNMAP_POOL(16),
 	__UNMAP_POOL(128),
 	__UNMAP_POOL(256),
-	#endif
+#endif
 };
 
 static struct zxdh_dmaengine_unmap_pool *__zxdh_get_unmap_pool(int nr)
@@ -1383,24 +1372,22 @@ static struct zxdh_dmaengine_unmap_pool *__zxdh_get_unmap_pool(int nr)
 
 static void zxdh_dmaengine_unmap(struct kref *kref)
 {
-	struct dmaengine_unmap_data *unmap = container_of(kref, typeof(*unmap), kref);
+	struct dmaengine_unmap_data *unmap =
+			container_of(kref, typeof(*unmap), kref);
 	struct device *dev = unmap->dev;
 	int cnt, i;
 
 	cnt = unmap->to_cnt;
 	for (i = 0; i < cnt; i++)
-		dma_unmap_page(dev, unmap->addr[i], unmap->len,
-			       DMA_TO_DEVICE);
+		dma_unmap_page(dev, unmap->addr[i], unmap->len, DMA_TO_DEVICE);
 	cnt += unmap->from_cnt;
 	for (; i < cnt; i++)
-		dma_unmap_page(dev, unmap->addr[i], unmap->len,
-			       DMA_FROM_DEVICE);
+		dma_unmap_page(dev, unmap->addr[i], unmap->len, DMA_FROM_DEVICE);
 	cnt += unmap->bidi_cnt;
 	for (; i < cnt; i++) {
 		if (unmap->addr[i] == 0)
 			continue;
-		dma_unmap_page(dev, unmap->addr[i], unmap->len,
-			       DMA_BIDIRECTIONAL);
+		dma_unmap_page(dev, unmap->addr[i], unmap->len, DMA_BIDIRECTIONAL);
 	}
 	cnt = unmap->map_cnt;
 	mempool_free(unmap, __zxdh_get_unmap_pool(cnt)->pool);
@@ -1412,7 +1399,6 @@ void zxdh_dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
 		kref_put(&unmap->kref, zxdh_dmaengine_unmap);
 }
 
-
 static void zxdh_dmaengine_destroy_unmap_pool(void)
 {
 	int i;
@@ -1436,10 +1422,10 @@ static int __init zxdh_dmaengine_init_unmap_pool(void)
 		size_t size;
 
 		size = sizeof(struct dmaengine_unmap_data) +
-		       sizeof(dma_addr_t) * p->size;
+			   sizeof(dma_addr_t) * p->size;
 
-		p->cache = kmem_cache_create(p->name, size, 0,
-					     SLAB_HWCACHE_ALIGN, NULL);
+		p->cache =
+				kmem_cache_create(p->name, size, 0, SLAB_HWCACHE_ALIGN, NULL);
 		if (!p->cache)
 			break;
 		p->pool = mempool_create_slab_pool(1, p->cache);
@@ -1454,8 +1440,8 @@ static int __init zxdh_dmaengine_init_unmap_pool(void)
 	return -ENOMEM;
 }
 
-struct dmaengine_unmap_data *
-zxdh_dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
+struct dmaengine_unmap_data *zxdh_dmaengine_get_unmap_data(struct device *dev,
+														   int nr, gfp_t flags)
 {
 	struct dmaengine_unmap_data *unmap;
 
@@ -1471,18 +1457,18 @@ zxdh_dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
 	return unmap;
 }
 
-
 void zxdh_dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
-	struct dma_chan *chan)
+									   struct dma_chan *chan)
 {
 	tx->chan = chan;
-	#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
+#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
 	spin_lock_init(&tx->lock);
-	#endif
+#endif
 }
 
-static inline int zxdh_desc_check_and_set_metadata_mode(
-	struct dma_async_tx_descriptor *desc, enum dma_desc_metadata_mode mode)
+static inline int
+zxdh_desc_check_and_set_metadata_mode(struct dma_async_tx_descriptor *desc,
+									  enum dma_desc_metadata_mode mode)
 {
 	/* Make sure that the metadata mode is not mixed */
 	if (!desc->desc_metadata_mode) {
@@ -1498,7 +1484,7 @@ static inline int zxdh_desc_check_and_set_metadata_mode(
 }
 
 int zxdh_dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc,
-				   void *data, size_t len)
+										void *data, size_t len)
 {
 	int ret;
 
@@ -1515,9 +1501,8 @@ int zxdh_dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc,
 	return desc->metadata_ops->attach(desc, data, len);
 }
 
-
 void *zxdh_dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc,
-				      size_t *payload_len, size_t *max_len)
+										   size_t *payload_len, size_t *max_len)
 {
 	int ret;
 
@@ -1534,9 +1519,8 @@ void *zxdh_dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc,
 	return desc->metadata_ops->get_ptr(desc, payload_len, max_len);
 }
 
-
 int zxdh_dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc,
-				    size_t payload_len)
+										 size_t payload_len)
 {
 	int ret;
 
@@ -1553,13 +1537,11 @@ int zxdh_dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc,
 	return desc->metadata_ops->set_len(desc, payload_len);
 }
 
-
 /**
  * zxdh_dma_wait_for_async_tx - spin wait for a transaction to complete
  * @tx:		in-flight transaction to wait on
  */
-enum dma_status
-zxdh_dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
+enum dma_status zxdh_dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
 {
 	unsigned long zxdh_dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
 
@@ -1569,8 +1551,7 @@ zxdh_dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
 	while (tx->cookie == -EBUSY) {
 		if (time_after_eq(jiffies, zxdh_dma_sync_wait_timeout)) {
 			dev_err(tx->chan->device->dev,
-				"%s timeout waiting for descriptor submission\n",
-				__func__);
+					"%s timeout waiting for descriptor submission\n", __func__);
 			return DMA_ERROR;
 		}
 		cpu_relax();
@@ -1578,9 +1559,9 @@ zxdh_dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
 	return zxdh_dma_sync_wait(tx->chan, tx->cookie);
 }
 
-
 /**
- * zxdh_dma_run_dependencies - process dependent operations on the target channel
+ * zxdh_dma_run_dependencies - process dependent operations on the target
+ * channel
  * @tx:		transaction with dependencies
  *
  * Helper routine for DMA drivers to process (start) dependent operations
@@ -1600,9 +1581,9 @@ void zxdh_dma_run_dependencies(struct dma_async_tx_descriptor *tx)
 	chan = dep->chan;
 
 	/* keep submitting up until a channel switch is detected
-	 * in that case we will be called again as a result of
-	 * processing the interrupt from async_tx_channel_switch
-	 */
+   * in that case we will be called again as a result of
+   * processing the interrupt from async_tx_channel_switch
+   */
 	for (; dep; dep = dep_next) {
 		txd_lock(dep);
 		txd_clear_parent(dep);
@@ -1619,7 +1600,6 @@ void zxdh_dma_run_dependencies(struct dma_async_tx_descriptor *tx)
 	chan->device->device_issue_pending(chan);
 }
 
-
 static int __init zxdh_dma_bus_init(void)
 {
 	int err = zxdh_dmaengine_init_unmap_pool();
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/dmaengine.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/dmaengine.h
index 5fc8b18fbedabdd0a3c56e1b30c95f8deaac3bf3..80d3963f96ea5b9b977d349f6d2ed334b0e7cc80 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/dmaengine.h
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/dmaengine.h
@@ -4,7 +4,6 @@
 #include <linux/bug.h>
 #include <linux/dmaengine.h>
 
-
 /**
  * zxdh_dma_cookie_init - initialize the cookies for a DMA channel
  * @chan: dma channel to initialize
@@ -22,7 +21,8 @@ static inline void zxdh_dma_cookie_init(struct dma_chan *chan)
  * Assign a unique non-zero per-channel cookie to the descriptor.
  * Note: caller is expected to hold a lock to prevent concurrency.
  */
-static inline dma_cookie_t zxdh_dma_cookie_assign(struct dma_async_tx_descriptor *tx)
+static inline dma_cookie_t
+zxdh_dma_cookie_assign(struct dma_async_tx_descriptor *tx)
 {
 	struct dma_chan *chan = tx->chan;
 	dma_cookie_t cookie;
@@ -62,7 +62,8 @@ static inline void zxdh_dma_cookie_complete(struct dma_async_tx_descriptor *tx)
  * non-NULL.  No locking is required.
  */
 static inline enum dma_status zxdh_dma_cookie_status(struct dma_chan *chan,
-	dma_cookie_t cookie, struct dma_tx_state *state)
+													 dma_cookie_t cookie,
+													 struct dma_tx_state *state)
 {
 	dma_cookie_t used, complete;
 
@@ -91,7 +92,7 @@ static inline void zxdh_dma_set_residue(struct dma_tx_state *state, u32 residue)
 }
 
 static inline void zxdh_dma_set_in_flight_bytes(struct dma_tx_state *state,
-					   u32 in_flight_bytes)
+												u32 in_flight_bytes)
 {
 	if (state)
 		state->in_flight_bytes = in_flight_bytes;
@@ -114,7 +115,7 @@ struct zxdh_dmaengine_desc_callback {
  */
 static inline void
 zxdh_dmaengine_desc_get_callback(struct dma_async_tx_descriptor *tx,
-			    struct zxdh_dmaengine_desc_callback *cb)
+								 struct zxdh_dmaengine_desc_callback *cb)
 {
 	cb->callback = tx->callback;
 	cb->callback_result = tx->callback_result;
@@ -132,12 +133,10 @@ zxdh_dmaengine_desc_get_callback(struct dma_async_tx_descriptor *tx,
  */
 static inline void
 zxdh_dmaengine_desc_callback_invoke(struct zxdh_dmaengine_desc_callback *cb,
-			       const struct dmaengine_result *result)
+									const struct dmaengine_result *result)
 {
-	struct dmaengine_result dummy_result = {
-		.result = DMA_TRANS_NOERROR,
-		.residue = 0
-	};
+	struct dmaengine_result dummy_result = { .result = DMA_TRANS_NOERROR,
+											 .residue = 0 };
 
 	if (cb->callback_result) {
 		if (!result)
@@ -149,18 +148,18 @@ zxdh_dmaengine_desc_callback_invoke(struct zxdh_dmaengine_desc_callback *cb,
 }
 
 /**
- * zxdh_dmaengine_desc_get_callback_invoke - get the callback in tx descriptor and
- * 					then immediately call the callback.
+ * zxdh_dmaengine_desc_get_callback_invoke - get the callback in tx descriptor
+ * and then immediately call the callback.
  * @tx: dma async tx descriptor
  * @result: transaction result
  *
- * Call zxdh_dmaengine_desc_get_callback() and zxdh_dmaengine_desc_callback_invoke()
- * in a single function since no work is necessary in between for the driver.
- * Locking is dependent on the driver.
+ * Call zxdh_dmaengine_desc_get_callback() and
+ * zxdh_dmaengine_desc_callback_invoke() in a single function since no work is
+ * necessary in between for the driver. Locking is dependent on the driver.
  */
 static inline void
 zxdh_dmaengine_desc_get_callback_invoke(struct dma_async_tx_descriptor *tx,
-				   const struct dmaengine_result *result)
+										const struct dmaengine_result *result)
 {
 	struct zxdh_dmaengine_desc_callback cb;
 
@@ -184,13 +183,14 @@ zxdh_dmaengine_desc_callback_valid(struct zxdh_dmaengine_desc_callback *cb)
 struct dma_chan *zxdh_dma_get_slave_channel(struct dma_chan *chan);
 struct dma_chan *zxdh_dma_get_any_slave_channel(struct dma_device *device);
 void zxdh_dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
-	struct dma_chan *chan);
+									   struct dma_chan *chan);
 
 #ifdef CONFIG_DEBUG_FS
 #include <linux/debugfs.h>
 
 static inline struct dentry *
-zxdh_zxdh_dmaengine_get_debugfs_root(struct dma_device *dma_dev) {
+zxdh_zxdh_dmaengine_get_debugfs_root(struct dma_device *dma_dev)
+{
 	return dma_dev->dbg_dev_root;
 }
 #else
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-epc.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-epc.c
index 7125e82961652d1e0173c420bb5b72828c350be8..9abd1c245b21c4046b9f18e69c2e4239c2422665 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-epc.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-epc.c
@@ -1,1396 +1,1339 @@
 #include "pcie-zte-zf-epc.h"
 #include "pcie-zte-zf-hdma.h"
 
-struct pcie_zf_ep *zf_ep = NULL;
+struct pcie_zf_ep *zf_ep;
 
 // PRE_FUNC
 #if 1
 int pcie_zf_read(void __iomem *addr, int size, u32 *val)
 {
-    *val = 0;
-    if (!IS_ALIGNED((unsigned long)addr, size))
-        return PCIBIOS_BAD_REGISTER_NUMBER;
+	*val = 0;
+	if (!IS_ALIGNED((unsigned long)addr, size))
+		return PCIBIOS_BAD_REGISTER_NUMBER;
 
-    if (size == 4)
-        *val = readl(addr);
-    else if (size == 2)
-        *val = readw(addr);
-    else if (size == 1)
-        *val = readb(addr);
-    else
-        return PCIBIOS_BAD_REGISTER_NUMBER;
+	if (size == 4)
+		*val = readl(addr);
+	else if (size == 2)
+		*val = readw(addr);
+	else if (size == 1)
+		*val = readb(addr);
+	else
+		return PCIBIOS_BAD_REGISTER_NUMBER;
 
-    return PCIBIOS_SUCCESSFUL;
+	return PCIBIOS_SUCCESSFUL;
 }
 int pcie_zf_write(void __iomem *addr, int size, u32 val)
 {
-    if (!IS_ALIGNED((unsigned long)addr, size))
-        return PCIBIOS_BAD_REGISTER_NUMBER;
+	if (!IS_ALIGNED((unsigned long)addr, size))
+		return PCIBIOS_BAD_REGISTER_NUMBER;
 
-    if (size == 4)
-        writel(val, addr);
-    else if (size == 2)
-        writew(val, addr);
-    else if (size == 1)
-        writeb(val, addr);
-    else
-        return PCIBIOS_BAD_REGISTER_NUMBER;
+	if (size == 4)
+		writel(val, addr);
+	else if (size == 2)
+		writew(val, addr);
+	else if (size == 1)
+		writeb(val, addr);
+	else
+		return PCIBIOS_BAD_REGISTER_NUMBER;
 
-    return PCIBIOS_SUCCESSFUL;
+	return PCIBIOS_SUCCESSFUL;
 }
 u32 cfg_phy_rmw(u64 phy_addr, u32 value, u32 mask)
 {
-    u32 reg_val = 0;
-    void __iomem *virt_addr = NULL;
-    u64 tmp_addr = 0;
-    u64 offset = 0;
-    u64 size = 0;
-    int ret = 0;
-
-    offset = phy_addr % PAGE_SIZE;
-    if (phy_addr < offset)
-    {
-        DH_LOG_ERR(MODULE_MPF, "data overflow! phy_addr=0x%llx, offset=0x%llx\n", phy_addr, offset);
-        return PCIBIOS_BAD_REGISTER_NUMBER;
-    }
-    else
-    {
-        tmp_addr = phy_addr - offset;
-    }
-    if (offset <= (PAGE_SIZE - 4))
-    {
-        size = PAGE_SIZE;
-    }
-    else
-    {
-        size = 2 * PAGE_SIZE;
-    }
-
-    virt_addr = ioremap(tmp_addr, size);
-    if (NULL == virt_addr)
-    {
-        DH_LOG_ERR(MODULE_MPF, "cfg_phy_rmw ioremap failed!\n");
-        return PCIBIOS_BAD_REGISTER_NUMBER;
-    }
-
-    ret = pcie_zf_read((virt_addr + offset), 4, &reg_val);
-    if (ret)
-        goto err;
-
-    reg_val &= (~mask);
-    reg_val |= (value & mask);
-
-    ret = pcie_zf_write(virt_addr + offset, 4, reg_val);
+	u32 reg_val = 0;
+	void __iomem *virt_addr = NULL;
+	u64 tmp_addr = 0;
+	u64 offset = 0;
+	u64 size = 0;
+	int ret = 0;
+
+	offset = phy_addr % PAGE_SIZE;
+	tmp_addr = phy_addr - offset;
+	if (offset <= (PAGE_SIZE - 4)) {
+		size = PAGE_SIZE;
+	} else {
+		size = 2 * PAGE_SIZE;
+	}
+
+	virt_addr = ioremap(tmp_addr, size);
+	if (NULL == virt_addr) {
+		DH_LOG_ERR(MODULE_MPF, "cfg_phy_rmw ioremap failed!\n");
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	}
+
+	ret = pcie_zf_read((virt_addr + offset), 4, &reg_val);
+	if (ret)
+		goto err;
+
+	reg_val &= (~mask);
+	reg_val |= (value & mask);
+
+	ret = pcie_zf_write(virt_addr + offset, 4, reg_val);
 err:
-    iounmap(virt_addr);
-    return ret;
+	iounmap(virt_addr);
+	return ret;
 }
 
 u8 pcie_zf_readb_dbi(struct pcie_dpu_ep *ep, u32 reg)
 {
-    u32 val = 0;
+	int ret = 0;
+	u32 val = 0;
 
-    pcie_zf_read(ep->dbi_base + reg, 0x1, &val);
+	ret = pcie_zf_read(ep->dbi_base + reg, 0x1, &val);
+	if (ret)
+		dev_err(&ep->epc->dev, "Read DBIb address failed\r\n");
 
-    return val;
+	return val;
 }
-
 u16 pcie_zf_readw_dbi(struct pcie_dpu_ep *ep, u32 reg)
 {
-    int ret;
-    u32 val;
+	int ret;
+	u32 val;
 
-    ret = pcie_zf_read(ep->dbi_base + reg, 0x2, &val);
-    if (ret)
-        DH_LOG_ERR(MODULE_MPF, "Read DBIw address failed\r\n");
+	ret = pcie_zf_read(ep->dbi_base + reg, 0x2, &val);
+	if (ret)
+		dev_err(&ep->epc->dev, "Read DBIw address failed\r\n");
 
-    return val;
+	return val;
 }
 u32 pcie_zf_readl_dbi(struct pcie_dpu_ep *ep, u32 reg)
 {
-    int ret = 0;
-    u32 val = 0;
+	int ret = 0;
+	u32 val = 0;
 
-    ret = pcie_zf_read(ep->dbi_base + reg, 0x4, &val);
-    if (ret)
-        DH_LOG_ERR(MODULE_MPF, "Read DBIl address failed\r\n");
+	ret = pcie_zf_read(ep->dbi_base + reg, 0x4, &val);
+	if (ret)
+		dev_err(&ep->epc->dev, "Read DBIl address failed\r\n");
 
-    return val;
+	return val;
 }
-
 void pcie_zf_writeb_dbi(struct pcie_dpu_ep *ep, u32 reg, u32 val)
 {
-    pcie_zf_write(ep->dbi_base + reg, 0x1, val);
-}
+	int ret = 0;
 
+	ret = pcie_zf_write(ep->dbi_base + reg, 0x1, val);
+	if (ret)
+		dev_err(&ep->epc->dev, "Write DBI address failed\r\n");
+}
 void pcie_zf_writew_dbi(struct pcie_dpu_ep *ep, u32 reg, u32 val)
 {
-    int ret = 0;
+	int ret = 0;
 
-    ret = pcie_zf_write(ep->dbi_base + reg, 0x2, val);
-    if (ret)
-        DH_LOG_ERR(MODULE_MPF, "Write DBI address failed\r\n");
+	ret = pcie_zf_write(ep->dbi_base + reg, 0x2, val);
+	if (ret)
+		dev_err(&ep->epc->dev, "Write DBI address failed\r\n");
 }
 void pcie_zf_writel_dbi(struct pcie_dpu_ep *ep, u32 reg, u32 val)
 {
-    int ret = 0;
+	int ret = 0;
 
-    ret = pcie_zf_write(ep->dbi_base + reg, 0x4, val);
-    if (ret)
-        DH_LOG_ERR(MODULE_MPF, "Write DBI address failed\r\n");
+	ret = pcie_zf_write(ep->dbi_base + reg, 0x4, val);
+	if (ret)
+		dev_err(&ep->epc->dev, "Write DBI address failed\r\n");
 }
-
 void pcie_zf_writeb_dbi2(struct pcie_dpu_ep *ep, u32 reg, u32 val)
 {
-    pcie_zf_write(ep->dbi_base + PCIE_DPU_EP_DBI2_OFFSET + reg, 0x1, val);
-}
+	int ret = 0;
 
+	ret = pcie_zf_write(ep->dbi_base + PCIE_DPU_EP_DBI2_OFFSET + reg, 0x1, val);
+	if (ret)
+		dev_err(&ep->epc->dev, "Write DBI address failed\r\n");
+}
 void pcie_zf_writew_dbi2(struct pcie_dpu_ep *ep, u32 reg, u32 val)
 {
-    int ret = 0;
+	int ret = 0;
 
-    ret = pcie_zf_write(ep->dbi_base + PCIE_DPU_EP_DBI2_OFFSET + reg, 0x2, val);
-    if (ret)
-        DH_LOG_ERR(MODULE_MPF, "Write DBI address failed\r\n");
+	ret = pcie_zf_write(ep->dbi_base + PCIE_DPU_EP_DBI2_OFFSET + reg, 0x2, val);
+	if (ret)
+		dev_err(&ep->epc->dev, "Write DBI address failed\r\n");
 }
 void pcie_zf_writel_dbi2(struct pcie_dpu_ep *ep, u32 reg, u32 val)
 {
-    int ret;
+	int ret;
 
-    ret = pcie_zf_write(ep->dbi_base + PCIE_DPU_EP_DBI2_OFFSET + reg, 0x4, val);
-    if (ret)
-        DH_LOG_ERR(MODULE_MPF, "Write DBI address failed\r\n");
+	ret = pcie_zf_write(ep->dbi_base + PCIE_DPU_EP_DBI2_OFFSET + reg, 0x4, val);
+	if (ret)
+		dev_err(&ep->epc->dev, "Write DBI address failed\r\n");
 }
 void pcie_zf_writel_atu(struct pcie_dpu_ep *ep, u32 reg, u32 val)
 {
-    int ret = 0;
+	int ret = 0;
 
-    ret = pcie_zf_write(ep->atu_base + reg, 0x4, val);
-    if (ret)
-        DH_LOG_ERR(MODULE_MPF, "Write ATU address failed\r\n");
+	ret = pcie_zf_write(ep->atu_base + reg, 0x4, val);
+	if (ret)
+		dev_err(&ep->epc->dev, "Write ATU address failed\r\n");
 }
 static u32 pcie_zf_readl_atu(struct pcie_dpu_ep *ep, u32 reg)
 {
-    int ret = 0;
-    u32 val = 0;
+	int ret = 0;
+	u32 val = 0;
 
-    ret = pcie_zf_read(ep->atu_base + reg, 4, &val);
-    if (ret)
-        DH_LOG_ERR(MODULE_MPF, "Read ATU address failed\r\n");
+	ret = pcie_zf_read(ep->atu_base + reg, 4, &val);
+	if (ret)
+		dev_err(&ep->epc->dev, "Read ATU address failed\r\n");
 
-    return val;
+	return val;
 }
 static u64 zte_pcie_dma_atu_addr_remapping(u64 addr_input)
 {
-    u64 addr_output = 0;
-    // DMA and ATU地址重映射，将地址的bit12~18左移4位，设置bit15 = 0
-    addr_output = (((addr_input & (0x7F << 12)) << 4) | (addr_input & 0xFFF)) & (~(1 << 15));
+	u64 addr_output = 0;
+	// DMA and ATU地址重映射，将地址的bit12~18左移4位，设置bit15 = 0
+	addr_output = (((addr_input & (0x7F << 12)) << 4) | (addr_input & 0xFFF)) &
+				  (~(1 << 15));
 
-    return addr_output;
+	return addr_output;
 }
 static u32 pcie_zf_readl_ib_unroll(struct pcie_dpu_ep *ep, u32 index, u32 reg)
 {
-    u32 offset = zte_pcie_dma_atu_addr_remapping(PCIE_GET_ATU_INB_UNR_REG_OFFSET(index));
+	u32 offset = zte_pcie_dma_atu_addr_remapping(
+			PCIE_GET_ATU_INB_UNR_REG_OFFSET(index));
 
-    return pcie_zf_readl_atu(ep, offset + reg);
+	return pcie_zf_readl_atu(ep, offset + reg);
 }
-static void pcie_zf_writel_ib_unroll(struct pcie_dpu_ep *ep, u32 index, u32 reg, u32 val)
+static void pcie_zf_writel_ib_unroll(struct pcie_dpu_ep *ep, u32 index, u32 reg,
+									 u32 val)
 {
-    u32 offset = zte_pcie_dma_atu_addr_remapping(PCIE_GET_ATU_INB_UNR_REG_OFFSET(index));
+	u32 offset = zte_pcie_dma_atu_addr_remapping(
+			PCIE_GET_ATU_INB_UNR_REG_OFFSET(index));
 
-    pcie_zf_writel_atu(ep, offset + reg, val);
+	pcie_zf_writel_atu(ep, offset + reg, val);
 }
 static u32 pcie_zf_readl_ob_unroll(struct pcie_dpu_ep *ep, u32 index, u32 reg)
 {
-    u32 offset = zte_pcie_dma_atu_addr_remapping(PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index));
+	u32 offset = zte_pcie_dma_atu_addr_remapping(
+			PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index));
 
-    return pcie_zf_readl_atu(ep, offset + reg);
+	return pcie_zf_readl_atu(ep, offset + reg);
 }
-static void pcie_zf_writel_ob_unroll(struct pcie_dpu_ep *ep, u32 index, u32 reg, u32 val)
+static void pcie_zf_writel_ob_unroll(struct pcie_dpu_ep *ep, u32 index, u32 reg,
+									 u32 val)
 {
-    u32 offset = zte_pcie_dma_atu_addr_remapping(PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index));
+	u32 offset = zte_pcie_dma_atu_addr_remapping(
+			PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index));
 
-    pcie_zf_writel_atu(ep, offset + reg, val);
+	pcie_zf_writel_atu(ep, offset + reg, val);
 }
 static void pcie_zf_dbi_ro_wr_en(struct pcie_dpu_ep *ep)
 {
-    u64 reg = 0;
-    u32 val = 0;
+	u64 reg = 0;
+	u32 val = 0;
 
-    reg = PCIE_MISC_CONTROL_1_OFF;
-    val = pcie_zf_readl_dbi(ep, reg);
-    val |= PCIE_DBI_RO_WR_EN;
-    pcie_zf_writel_dbi(ep, reg, val);
+	reg = PCIE_MISC_CONTROL_1_OFF;
+	val = pcie_zf_readl_dbi(ep, reg);
+	val |= PCIE_DBI_RO_WR_EN;
+	pcie_zf_writel_dbi(ep, reg, val);
 }
 static void pcie_zf_dbi_ro_wr_dis(struct pcie_dpu_ep *ep)
 {
-    u64 reg = 0;
-    u32 val = 0;
+	u64 reg = 0;
+	u32 val = 0;
 
-    reg = PCIE_MISC_CONTROL_1_OFF;
-    val = pcie_zf_readl_dbi(ep, reg);
-    val &= ~PCIE_DBI_RO_WR_EN;
-    pcie_zf_writel_dbi(ep, reg, val);
+	reg = PCIE_MISC_CONTROL_1_OFF;
+	val = pcie_zf_readl_dbi(ep, reg);
+	val &= ~PCIE_DBI_RO_WR_EN;
+	pcie_zf_writel_dbi(ep, reg, val);
 }
-static void pcie_dpu_ep_sriov_enable(struct pcie_dpu_ep *ep, u64 sriov_ecap_offset)
+static void pcie_dpu_ep_sriov_enable(struct pcie_dpu_ep *ep,
+									 u64 sriov_ecap_offset)
 {
-    u32 val = pcie_zf_readl_dbi(ep, sriov_ecap_offset + PCIE_SRIOV_CTRL);
-    val |= PCIE_SRIOV_CTRL_VFE;
-    pcie_zf_writel_dbi(ep, sriov_ecap_offset + PCIE_SRIOV_CTRL, val);
+	u32 val = pcie_zf_readl_dbi(ep, sriov_ecap_offset + PCIE_SRIOV_CTRL);
+	val |= PCIE_SRIOV_CTRL_VFE;
+	pcie_zf_writel_dbi(ep, sriov_ecap_offset + PCIE_SRIOV_CTRL, val);
 }
-static void pcie_dpu_ep_sriov_disable(struct pcie_dpu_ep *ep, u64 sriov_ecap_offset)
+static void pcie_dpu_ep_sriov_disable(struct pcie_dpu_ep *ep,
+									  u64 sriov_ecap_offset)
 {
-    u32 val = pcie_zf_readl_dbi(ep, sriov_ecap_offset + PCIE_SRIOV_CTRL);
-    val &= ~PCIE_SRIOV_CTRL_VFE;
-    pcie_zf_writel_dbi(ep, sriov_ecap_offset + PCIE_SRIOV_CTRL, val);
+	u32 val = pcie_zf_readl_dbi(ep, sriov_ecap_offset + PCIE_SRIOV_CTRL);
+	val &= ~PCIE_SRIOV_CTRL_VFE;
+	pcie_zf_writel_dbi(ep, sriov_ecap_offset + PCIE_SRIOV_CTRL, val);
 }
-struct pcie_dpu_ep_func *pcie_dpu_ep_get_func_from_ep(struct pcie_dpu_ep *ep, u8 func_no, u8 vfunc_no)
+struct pcie_dpu_ep_func *pcie_dpu_ep_get_func_from_ep(struct pcie_dpu_ep *ep,
+													  u8 func_no, u8 vfunc_no)
 {
-    struct pcie_dpu_ep_func *ep_func = NULL;
+	struct pcie_dpu_ep_func *ep_func = NULL;
 
-    list_for_each_entry(ep_func, &ep->func_list, list)
-    {
-        if (ep_func->func_no == func_no && ep_func->vfunc_no == vfunc_no)
-            return ep_func;
-    }
+	list_for_each_entry(ep_func, &ep->func_list, list) {
+		if (ep_func->func_no == func_no && ep_func->vfunc_no == vfunc_no)
+			return ep_func;
+	}
 
-    return NULL;
+	return NULL;
 }
 static u32 pcie_dpu_ep_func_select(u8 func_no, u8 vfunc_no)
 {
-    u32 func_offset = 0;
+	u32 func_offset = 0;
 
-    if (isPF(func_no))
-    {
-        func_offset = func_no & PCIE_DPU_EP_GET_PF_NO;
-    }
-    else
-    {
-        func_offset = (func_no & PCIE_DPU_EP_GET_PF_NO) + (vfunc_no << DBI_VF_CFG_OFFSET_BIT) + VF_ACT_BIT;
-    }
+	if (isPF(func_no)) {
+		func_offset = func_no & PCIE_DPU_EP_GET_PF_NO;
+	} else {
+		func_offset = (func_no & PCIE_DPU_EP_GET_PF_NO) +
+					  (vfunc_no << DBI_VF_CFG_OFFSET_BIT) + VF_ACT_BIT;
+	}
 
-    return func_offset * PCIE_DPU_EP_FUNC_CFG_SIZE;
+	return func_offset * PCIE_DPU_EP_FUNC_CFG_SIZE;
 }
-static u8 pcie_dpu_ep_find_next_cap(struct pcie_dpu_ep *ep,
-                                    u32 func_offset, u8 cap_ptr, u8 capid)
+static u8 pcie_dpu_ep_find_next_cap(struct pcie_dpu_ep *ep, u32 func_offset,
+									u8 cap_ptr, u8 capid)
 {
-    u8 now_cap_id = 0, next_cap_ptr = 0;
-    u16 reg = 0;
+	u8 now_cap_id = 0, next_cap_ptr = 0;
+	u16 reg = 0;
 
-    if (!cap_ptr)
-        return 0;
+	if (!cap_ptr)
+		return 0;
 
-    reg = pcie_zf_readl_dbi(ep, func_offset + cap_ptr);
-    now_cap_id = (reg & 0x00ff);
+	reg = pcie_zf_readl_dbi(ep, func_offset + cap_ptr);
+	now_cap_id = (reg & 0x00ff);
 
-    if (now_cap_id > PCI_CAP_ID_MAX)
-        return 0;
+	if (now_cap_id > PCI_CAP_ID_MAX)
+		return 0;
 
-    if (now_cap_id == capid)
-        return cap_ptr;
+	if (now_cap_id == capid)
+		return cap_ptr;
 
-    next_cap_ptr = (reg & 0xff00) >> 8;
-    return pcie_dpu_ep_find_next_cap(ep, func_offset, next_cap_ptr, capid);
+	next_cap_ptr = (reg & 0xff00) >> 8;
+	return pcie_dpu_ep_find_next_cap(ep, func_offset, next_cap_ptr, capid);
 }
-static u8 pcie_dpu_ep_find_cap(struct pcie_dpu_ep *ep, u32 func_offset, u8 capid)
+static u8 pcie_dpu_ep_find_cap(struct pcie_dpu_ep *ep, u32 func_offset,
+							   u8 capid)
 {
-    u8 next_cap_ptr = 0;
-    u16 reg = 0;
+	u8 next_cap_ptr = 0;
+	u16 reg = 0;
 
-    reg = pcie_zf_readl_dbi(ep, func_offset + PCI_CAPABILITY_LIST);
-    next_cap_ptr = (reg & 0x00ff);
+	reg = pcie_zf_readl_dbi(ep, func_offset + PCI_CAPABILITY_LIST);
+	next_cap_ptr = (reg & 0x00ff);
 
-    return pcie_dpu_ep_find_next_cap(ep, func_offset, next_cap_ptr, capid);
+	return pcie_dpu_ep_find_next_cap(ep, func_offset, next_cap_ptr, capid);
 }
-static int pcie_dpu_ep_find_extcap(struct pcie_dpu_ep *ep, u32 func_offset, u8 ext_cap_id, u8 vsecid)
+static u32 pcie_dpu_ep_find_extcap(struct pcie_dpu_ep *ep, u32 func_offset,
+								   u8 ext_cap_id, u8 vsecid)
 {
-    u32 now_cap_id = 0;
-    u32 vsec_id = 0;
-    u32 ext_cap_offset = PCIE_ECAP_POINTER_OFF;
+	u32 now_cap_id = 0;
+	u32 vsec_id = 0;
+	u32 ext_cap_offset = PCIE_ECAP_POINTER_OFF;
 
-    now_cap_id = pcie_zf_readl_dbi(ep, func_offset + ext_cap_offset);
-    if (now_cap_id == 0x0 || now_cap_id == 0xFFFF)
-    {
-        DH_LOG_ERR(MODULE_MPF, "pcie_zf_ep get extcap0 failed!\n");
-        return -ENXIO;
-    }
-
-    while (1)
-    {
-        if ((now_cap_id & 0xFFFF) == ext_cap_id)
-        {
-            if (ext_cap_id == PCIE_ECAP_VSEC_ID)
-            {
-                vsec_id = pcie_zf_readl_dbi(ep, func_offset + ext_cap_offset + 4);
-                if (vsec_id == vsecid)
-                {
-                    break;
-                }
-            }
-            else
-            {
-                break;
-            }
-        }
-
-        ext_cap_offset = (now_cap_id >> 20) & 0xFFF;
-        if (0x0 == ext_cap_offset)
-        {
-            DH_LOG_ERR(MODULE_MPF, "pcie_zf_ep find extcap failed\n");
-            return -ENXIO;
-        }
-
-        now_cap_id = pcie_zf_readl_dbi(ep, func_offset + ext_cap_offset);
-    }
-
-    return ext_cap_offset;
-}
-
-static int zf_atu_is_used(struct pcie_dpu_ep *ep, int ib_no)
-{
-    return (pcie_zf_readl_ib_unroll(ep, ib_no, PCIE_ATU_UNR_REGION_CTRL2) & PCIE_ATU_ENABLE) ? 1 : 0;
-}
-
-static int zf_func_is_set_ib(struct pcie_dpu_ep *ep, u8 func_no, enum pci_barno bar, int ib_no)
-{
-    int func_val = 0, bar_val = 0;
-    int ctl1_val = pcie_zf_readl_ib_unroll(ep, ib_no, PCIE_ATU_UNR_REGION_CTRL1);
-    int ctl2_val = pcie_zf_readl_ib_unroll(ep, ib_no, PCIE_ATU_UNR_REGION_CTRL2);
-
-    func_val = PCIE_ATU_FUNC_NUM(func_no & PCIE_DPU_EP_GET_PF_NO);
-    if ((ctl1_val & PCIE_ATU_FUNC_NUM_MASK) != func_val)
-        return 0;
-
-    if (isPF(func_no))
-    {
-        if (ctl2_val & PCIE_ATU_VFBAR_MATCH_MODE_ENABLE)
-            return 0;
-    }
-    else
-    {
-        if (!(ctl2_val & PCIE_ATU_VFBAR_MATCH_MODE_ENABLE))
-            return 0;
-    }
-    bar_val = (bar << 8);
-    return ((ctl2_val & PCIE_ATU_BAR_NUM_MASK) == bar_val);
-}
-
-static int pcie_zf_prog_inbound_atu(struct pcie_dpu_ep *ep, u8 func_no, int index, int bar, dma_addr_t dpu_addr, enum pcie_dpu_as_type as_type)
-{
-    int type = 0;
-    u32 retries = 0, val = 0;
-    int vf_flag = 0;
-
-    dpu_addr = dpu_addr | ZF_PREFIX_ADDR; // dpu addr route
-
-    if (!isPF(func_no))
-    {
-        vf_flag = 1;
-    }
-
-    pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_LOWER_TARGET, lower_32_bits(dpu_addr));
-    pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_UPPER_TARGET, upper_32_bits(dpu_addr));
-
-    switch (as_type)
-    {
-        case PCIE_DPU_AS_MEM:
-            type = PCIE_ATU_TYPE_MEM;
-            break;
-        case PCIE_DPU_AS_IO:
-            if (vf_flag == 1)
-            {
-                return -EINVAL;
-            }
-            type = PCIE_ATU_TYPE_IO;
-            break;
-        default:
-            return -EINVAL;
-    }
-
-    pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL1, type | PCIE_ATU_INCREASE_REGION_SIZE | PCIE_ATU_FUNC_NUM(func_no & PCIE_DPU_EP_GET_PF_NO));
-    if (vf_flag)
-    {
-        pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2,
-                                 PCIE_ATU_FUNC_NUM_MATCH_EN |
-                                     PCIE_ATU_ENABLE |
-                                     PCIE_ATU_VFBAR_MATCH_MODE_ENABLE |
-                                     PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
-    }
-    else
-    {
-        pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2,
-                                 PCIE_ATU_FUNC_NUM_MATCH_EN |
-                                     PCIE_ATU_ENABLE |
-                                     PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
-    }
-
-    /*
-     * Make sure ATU enable takes effect before any subsequent config
-     * and I/O accesses.
-     */
-    for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++)
-    {
-        val = pcie_zf_readl_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2);
-        if (val & PCIE_ATU_ENABLE)
-            return 0;
-
-        mdelay((u32)LINK_WAIT_IATU);
-    }
-    DH_LOG_ERR(MODULE_MPF, "Inbound iATU is not being enabled\r\n");
-
-    return -EBUSY;
-}
-
-static int pcie_dpu_ep_inbound_atu(struct pcie_dpu_ep *ep, u8 func_no, enum pci_barno bar, dma_addr_t dpu_addr, enum pcie_dpu_as_type as_type)
-{
-    int ret = 0, free_win = -1, atu_id = 0;
-    u32 vf_bar_off = 0;
-    u32 is_pf = 0;
-    u32 bar_to_atu_index = 0;
-
-    if ((func_no & PCIE_DPU_EP_GET_PF_NO) >= PCIE_DPU_PF_NUMS)
-    {
-        DH_LOG_ERR(MODULE_MPF, "func_no is err!\n");
-        return -EINVAL;
-    }
-
-    is_pf = isPF(func_no);
-    if (!is_pf)
-    {
-        vf_bar_off = PCIE_VF_BARS_OFF;
-    }
-
-    spin_lock(&ep->ib_window_lock);
-    for (atu_id = 0; atu_id < PCIE_DPU_IATU_NUM; atu_id++)
-    {
-        if (zf_func_is_set_ib(ep, func_no, bar, atu_id))
-        {
-            free_win = atu_id;
-            break;
-        }
-    }
-
-    if (-1 == free_win)
-    {
-        free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
-        if (free_win >= ep->num_ib_windows)
-        {
-            spin_unlock(&ep->ib_window_lock);
-            DH_LOG_ERR(MODULE_MPF, "No free inbound window\r\n");
-            return -EINVAL;
-        }
-    }
-    set_bit(free_win, ep->ib_window_map);
-
-    ret = pcie_zf_prog_inbound_atu(ep, func_no, free_win, bar, dpu_addr, as_type);
-    spin_unlock(&ep->ib_window_lock);
-    if (ret < 0)
-    {
-        DH_LOG_ERR(MODULE_MPF, "Failed to program IB window\r\n");
-        return ret;
-    }
-    DH_LOG_INFO(MODULE_MPF, "ep%d func%d bar%d set aitu%d\n", ep->ep_id, func_no, bar, free_win);
-
-    bar_to_atu_index = (u32)bar + vf_bar_off;
-    if (bar_to_atu_index < (PCI_STD_NUM_BARS * 2 + 1))
-    {
-        ep->bar_to_atu[func_no & PCIE_DPU_EP_GET_PF_NO][bar_to_atu_index] = free_win;
-    }
-    else
-    {
-        DH_LOG_ERR(MODULE_MPF, "error bar_to_atu index %d\r\n", bar_to_atu_index);
-        return -EINVAL;
-    }
-
-    return 0;
-}
-
-static void pcie_zf_prog_outbound_atu(struct pcie_dpu_ep *ep, u8 func_no, u8 vfunc_no, int index, int type, u64 dpu_addr, u64 host_addr, size_t size)
-{
-    u32 retries = 0, val = 0;
-    u64 limit_addr = 0;
-    u64 limit_addr_tmp = 0;
-
-    if (size == 0)
-    {
-        DH_LOG_ERR(MODULE_MPF, "data error! dpu_addr=0x%llx, size=0x%lx\r\n", dpu_addr, size);
-        return;
-    }
-    else
-    {
-        limit_addr_tmp = ULLONG_MAX - size + 1;
-        if (dpu_addr > limit_addr_tmp)
-        {
-            DH_LOG_ERR(MODULE_MPF, "data overflow!\r\n");
-            return;
-        }
-        limit_addr = dpu_addr + size - 1;
-    }
-
-    pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_LOWER_BASE, lower_32_bits(dpu_addr));
-    pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_UPPER_BASE, upper_32_bits(dpu_addr));
-    pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_LOWER_LIMIT, lower_32_bits(limit_addr));
-    pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_UPPER_LIMIT, upper_32_bits(limit_addr));
-    pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_LOWER_TARGET, lower_32_bits(host_addr));
-    pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_UPPER_TARGET, upper_32_bits(host_addr));
-    pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL1,
-                             type | PCIE_ATU_FUNC_NUM(func_no & PCIE_DPU_EP_GET_PF_NO));
-
-    if (type == 4 || type == 5)
-    {
-        pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2, PCIE_ATU_ENABLE | PCIE_ATU_CFG_SHIFT_MODE | PCIE_ATU_DMA_BYPSS);
-    }
-    else
-    {
-        pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2, PCIE_ATU_ENABLE | PCIE_ATU_DMA_BYPSS);
-    }
-
-    if (isPF(func_no))
-    {
-        pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL3, 0x0);
-    }
-    else
-    {
-        pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL3, PCIE_ATU_OB_VF_ACTIVE | vfunc_no);
-    }
-
-    /*
-     * Make sure ATU enable takes effect before any subsequent config
-     * and I/O accesses.
-     */
-    for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++)
-    {
-        val = pcie_zf_readl_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2);
-        if (val & PCIE_ATU_ENABLE)
-            return;
-
-        mdelay((u32)LINK_WAIT_IATU);
-    }
-    DH_LOG_ERR(MODULE_MPF, "Outbound iATU is not being enabled\r\n");
-}
-
-static int pcie_dpu_ep_outbound_atu(struct pcie_dpu_ep *ep, u8 func_no, u8 vfunc_no, phys_addr_t dpu_offset, u64 host_addr, size_t size)
-{
-    u32 free_win = 0;
-
-    free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
-    if (free_win >= ep->num_ob_windows)
-    {
-        DH_LOG_ERR(MODULE_MPF, "No free outbound window\r\n");
-        return -EINVAL;
-    }
-
-    pcie_zf_prog_outbound_atu(ep, func_no, vfunc_no, free_win, PCIE_ATU_TYPE_MEM,
-                              dpu_offset, host_addr, size);
-
-    set_bit(free_win, ep->ob_window_map);
-    ep->ob_src_addr[free_win] = dpu_offset;
-
-    return 0;
-}
-
-static void pcie_dpu_ep_reset_bar(struct pcie_dpu_ep *ep, u8 func_no, u8 vfunc_no,
-                                  enum pci_barno bar, int flags)
-{
-    int sriov_cap_offset = 0;
-    u32 reg = 0;
-    u32 func_offset = pcie_dpu_ep_func_select(func_no & PCIE_DPU_EP_GET_PF_NO, vfunc_no);
-
-    if (isPF(func_no))
-    {
-        reg = func_offset + (u32)(PCI_BASE_ADDRESS_0) + (u32)(PCIE_NEXT_BAR_OFFSET * bar);
-        pcie_zf_dbi_ro_wr_en(ep);
-        // pcie_zf_writel_dbi2(ep, reg, 0x0);
-        pcie_zf_writel_dbi(ep, reg, 0xc);
-        // pcie_zf_writel_dbi2(ep, reg + PCIE_NEXT_BAR_OFFSET, 0x0);
-        // pcie_zf_writel_dbi(ep, reg + PCIE_NEXT_BAR_OFFSET, 0x0);
-        pcie_zf_dbi_ro_wr_dis(ep);
-    }
-    else
-    {
-        sriov_cap_offset = pcie_dpu_ep_find_extcap(ep, func_offset, PCI_EXT_CAP_ID_SRIOV, 0);
-        if (sriov_cap_offset < 0)
-        {
-            DH_LOG_ERR(MODULE_MPF, "find_extcap failed!!\n");
-        }
-
-        reg = func_offset + (u32)sriov_cap_offset + (u32)(PCIE_SRIOV_ECAP_BAR0_OFFSET) + (u32)(bar * PCIE_NEXT_BAR_OFFSET);
-        pcie_zf_writel_dbi(ep, reg, 0xc);
-        pcie_zf_writel_dbi(ep, reg + PCIE_NEXT_BAR_OFFSET, 0x0);
-
-        // reg = func_offset + sriov_cap_offset;
-        // pcie_dpu_ep_sriov_disable(ep, reg);
-        // pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR0_OFFSET + bar * PCIE_NEXT_BAR_OFFSET, 0x0);
-        // pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR0_OFFSET + (bar + 1) * PCIE_NEXT_BAR_OFFSET, 0x0);
-        // pcie_dpu_ep_sriov_enable(ep, reg);
-    }
+	now_cap_id = pcie_zf_readl_dbi(ep, func_offset + ext_cap_offset);
+	if (now_cap_id == 0x0 || now_cap_id == 0xFFFF) {
+		DH_LOG_ERR(MODULE_MPF, "pcie_zf_ep get extcap0 failed!\n");
+		return -ENXIO;
+	}
+
+	while (1) {
+		if ((now_cap_id & 0xFFFF) == ext_cap_id) {
+			if (ext_cap_id == PCIE_ECAP_VSEC_ID) {
+				vsec_id =
+						pcie_zf_readl_dbi(ep, func_offset + ext_cap_offset + 4);
+				if (vsec_id == vsecid) {
+					break;
+				}
+			} else {
+				break;
+			}
+		}
+
+		ext_cap_offset = (now_cap_id >> 20) & 0xFFF;
+		if (0x0 == ext_cap_offset) {
+			DH_LOG_ERR(MODULE_MPF, "pcie_zf_ep find extcap failed\n");
+			return -ENXIO;
+		}
+
+		now_cap_id = pcie_zf_readl_dbi(ep, func_offset + ext_cap_offset);
+	}
+
+	return ext_cap_offset;
+}
+
+static int zf_atu_is_used(struct pcie_dpu_ep *ep, int in_no)
+{
+	return (pcie_zf_readl_ib_unroll(ep, in_no, PCIE_ATU_UNR_REGION_CTRL2) &
+			PCIE_ATU_ENABLE) ?
+					 1 :
+					 0;
+}
+
+static int zf_func_is_set_ib(struct pcie_dpu_ep *ep, u8 func_no,
+							 enum pci_barno bar, int in_no)
+{
+	int func_val = 0, bar_val = 0;
+	int ctl1_val =
+			pcie_zf_readl_ib_unroll(ep, in_no, PCIE_ATU_UNR_REGION_CTRL1);
+	int ctl2_val =
+			pcie_zf_readl_ib_unroll(ep, in_no, PCIE_ATU_UNR_REGION_CTRL2);
+
+	func_val = PCIE_ATU_FUNC_NUM(func_no & PCIE_DPU_EP_GET_PF_NO);
+	if ((ctl1_val & PCIE_ATU_FUNC_NUM_MASK) != func_val)
+		return 0;
+
+	if (isPF(func_no)) {
+		if (ctl2_val & PCIE_ATU_VFBAR_MATCH_MODE_ENABLE)
+			return 0;
+	} else {
+		if (!(ctl2_val & PCIE_ATU_VFBAR_MATCH_MODE_ENABLE))
+			return 0;
+	}
+	bar_val = (bar << 8);
+	return ((ctl2_val & PCIE_ATU_BAR_NUM_MASK) == bar_val);
+}
+
+static int pcie_zf_prog_inbound_atu(struct pcie_dpu_ep *ep, u8 func_no,
+									int index, int bar, dma_addr_t dpu_addr,
+									enum pcie_dpu_as_type as_type)
+{
+	int type = 0;
+	u32 retries = 0, val = 0;
+	int vf_flag = 0;
+
+	dpu_addr = dpu_addr | ZF_PREFIX_ADDR; // dpu addr route
+
+	if (!isPF(func_no)) {
+		vf_flag = 1;
+	}
+
+	pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_LOWER_TARGET,
+							 lower_32_bits(dpu_addr));
+	pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_UPPER_TARGET,
+							 upper_32_bits(dpu_addr));
+
+	switch (as_type) {
+	case PCIE_DPU_AS_MEM:
+		type = PCIE_ATU_TYPE_MEM;
+		break;
+	case PCIE_DPU_AS_IO:
+		if (vf_flag == 1) {
+			return -EINVAL;
+		}
+		type = PCIE_ATU_TYPE_IO;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL1,
+							 type | PCIE_ATU_INCREASE_REGION_SIZE |
+									 PCIE_ATU_FUNC_NUM(func_no &
+													   PCIE_DPU_EP_GET_PF_NO));
+	if (vf_flag) {
+		pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2,
+								 PCIE_ATU_FUNC_NUM_MATCH_EN | PCIE_ATU_ENABLE |
+										 PCIE_ATU_VFBAR_MATCH_MODE_ENABLE |
+										 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
+	} else {
+		pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2,
+								 PCIE_ATU_FUNC_NUM_MATCH_EN | PCIE_ATU_ENABLE |
+										 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
+	}
+
+	/*
+   * Make sure ATU enable takes effect before any subsequent config
+   * and I/O accesses.
+   */
+	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
+		val = pcie_zf_readl_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2);
+		if (val & PCIE_ATU_ENABLE)
+			return 0;
+
+		mdelay(LINK_WAIT_IATU);
+	}
+	dev_err(&ep->epc->dev, "Inbound iATU is not being enabled\r\n");
+
+	return -EBUSY;
+}
+
+static int pcie_dpu_ep_inbound_atu(struct pcie_dpu_ep *ep, u8 func_no,
+								   enum pci_barno bar, dma_addr_t dpu_addr,
+								   enum pcie_dpu_as_type as_type)
+{
+	int ret = 0, free_win = -1, atu_id = 0;
+	int vf_bar_off = 0;
+
+	if (!isPF(func_no)) {
+		vf_bar_off = PCIE_VF_BARS_OFF;
+	}
+
+	for (atu_id = 0; atu_id < PCIE_DPU_IATU_NUM; atu_id++) {
+		if (zf_func_is_set_ib(ep, func_no, bar, atu_id)) {
+			free_win = atu_id;
+			break;
+		}
+	}
+
+	if (-1 == free_win) {
+		free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
+		if (free_win >= ep->num_ib_windows) {
+			dev_err(&ep->epc->dev, "No free inbound window\r\n");
+			return -EINVAL;
+		}
+	}
+
+	ret = pcie_zf_prog_inbound_atu(ep, func_no, free_win, bar, dpu_addr,
+								   as_type);
+	if (ret < 0) {
+		dev_err(&ep->epc->dev, "Failed to program IB window\r\n");
+		return ret;
+	}
+
+	ep->bar_to_atu[bar + vf_bar_off] = free_win;
+	set_bit(free_win, ep->ib_window_map);
+
+	return 0;
+}
+
+static void pcie_zf_prog_outbound_atu(struct pcie_dpu_ep *ep, u8 func_no,
+									  u8 vfunc_no, int index, int type,
+									  u64 dpu_addr, u64 host_addr, u32 size)
+{
+	u32 retries = 0, val = 0;
+	u64 limit_addr = dpu_addr + size - 1;
+
+	pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_LOWER_BASE,
+							 lower_32_bits(dpu_addr));
+	pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_UPPER_BASE,
+							 upper_32_bits(dpu_addr));
+	pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_LOWER_LIMIT,
+							 lower_32_bits(limit_addr));
+	pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_UPPER_LIMIT,
+							 upper_32_bits(limit_addr));
+	pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_LOWER_TARGET,
+							 lower_32_bits(host_addr));
+	pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_UPPER_TARGET,
+							 upper_32_bits(host_addr));
+	pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL1,
+							 type | PCIE_ATU_FUNC_NUM(func_no &
+													  PCIE_DPU_EP_GET_PF_NO));
+
+	if (type == 4 || type == 5) {
+		pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2,
+								 PCIE_ATU_ENABLE | PCIE_ATU_CFG_SHIFT_MODE |
+										 PCIE_ATU_DMA_BYPSS);
+	} else {
+		pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2,
+								 PCIE_ATU_ENABLE | PCIE_ATU_DMA_BYPSS);
+	}
+
+	if (isPF(func_no)) {
+		pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL3, 0x0);
+	} else {
+		pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL3,
+								 PCIE_ATU_OB_VF_ACTIVE | vfunc_no);
+	}
+
+	/*
+   * Make sure ATU enable takes effect before any subsequent config
+   * and I/O accesses.
+   */
+	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
+		val = pcie_zf_readl_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2);
+		if (val & PCIE_ATU_ENABLE)
+			return;
+
+		mdelay(LINK_WAIT_IATU);
+	}
+	dev_err(&ep->epc->dev, "Outbound iATU is not being enabled\r\n");
+}
+
+static int pcie_dpu_ep_outbound_atu(struct pcie_dpu_ep *ep, u8 func_no,
+									u8 vfunc_no, phys_addr_t dpu_offset,
+									u64 host_addr, size_t size)
+{
+	u32 free_win = 0;
+
+	free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
+	if (free_win >= ep->num_ob_windows) {
+		dev_err(&ep->epc->dev, "No free outbound window\r\n");
+		return -EINVAL;
+	}
+
+	pcie_zf_prog_outbound_atu(ep, func_no, vfunc_no, free_win,
+							  PCIE_ATU_TYPE_MEM, dpu_offset, host_addr, size);
+
+	set_bit(free_win, ep->ob_window_map);
+	ep->ob_src_addr[free_win] = dpu_offset;
+
+	return 0;
+}
+
+static void pcie_dpu_ep_reset_bar(struct pcie_dpu_ep *ep, u8 func_no,
+								  u8 vfunc_no, enum pci_barno bar, int flags)
+{
+	u32 reg = 0, sriov_cap_offset = 0;
+	u32 func_offset =
+			pcie_dpu_ep_func_select(func_no & PCIE_DPU_EP_GET_PF_NO, vfunc_no);
+
+	if (isPF(func_no)) {
+		reg = func_offset + PCI_BASE_ADDRESS_0 + (PCIE_NEXT_BAR_OFFSET * bar);
+		pcie_zf_dbi_ro_wr_en(ep);
+		// pcie_zf_writel_dbi2(ep, reg, 0x0);
+		pcie_zf_writel_dbi(ep, reg, 0xc);
+		// pcie_zf_writel_dbi2(ep, reg + PCIE_NEXT_BAR_OFFSET, 0x0);
+		// pcie_zf_writel_dbi(ep, reg + PCIE_NEXT_BAR_OFFSET, 0x0);
+		pcie_zf_dbi_ro_wr_dis(ep);
+	} else {
+		sriov_cap_offset = pcie_dpu_ep_find_extcap(ep, func_offset,
+												   PCI_EXT_CAP_ID_SRIOV, 0);
+		if (sriov_cap_offset < 0) {
+			DH_LOG_ERR(MODULE_MPF, "find_extcap failed!!\n");
+		}
+
+		reg = func_offset + sriov_cap_offset + PCIE_SRIOV_ECAP_BAR0_OFFSET +
+			  bar * PCIE_NEXT_BAR_OFFSET;
+		pcie_zf_writel_dbi(ep, reg, 0xc);
+		pcie_zf_writel_dbi(ep, reg + PCIE_NEXT_BAR_OFFSET, 0x0);
+
+		// reg = func_offset + sriov_cap_offset;
+		// pcie_dpu_ep_sriov_disable(ep, reg);
+		// pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR0_OFFSET + bar *
+		// PCIE_NEXT_BAR_OFFSET, 0x0); pcie_zf_writel_dbi2(ep, reg +
+		// PCIE_SRIOV_ECAP_BAR0_OFFSET + (bar + 1) * PCIE_NEXT_BAR_OFFSET, 0x0);
+		// pcie_dpu_ep_sriov_enable(ep, reg);
+	}
 }
 
 void pcie_zf_disable_atu(struct pcie_dpu_ep *ep, int index,
-                         enum pcie_dpu_region_type type)
-{
-    u32 val = 0;
-    switch (type)
-    {
-        case PCIE_DPU_REGION_INBOUND:
-            val = pcie_zf_readl_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2);
-            val &= (u32)(~PCIE_ATU_ENABLE);
-            pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2, val);
-            break;
-        case PCIE_DPU_REGION_OUTBOUND:
-            val = pcie_zf_readl_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2);
-            val &= (u32)(~PCIE_ATU_ENABLE);
-            pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2, val);
-            break;
-        default:
-            return;
-    }
+						 enum pcie_dpu_region_type type)
+{
+	switch (type) {
+	case PCIE_DPU_REGION_INBOUND:
+		pcie_zf_writel_ib_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2, 0);
+		break;
+	case PCIE_DPU_REGION_OUTBOUND:
+		pcie_zf_writel_ob_unroll(ep, index, PCIE_ATU_UNR_REGION_CTRL2, 0);
+		break;
+	default:
+		return;
+	}
 }
 
 static int pcie_zf_find_index(struct pcie_dpu_ep *ep, phys_addr_t dpu_offset,
-                              u32 *atu_index)
+							  u32 *atu_index)
 {
-    u32 index = 0;
+	u32 index = 0;
 
-    for (index = 0; index < ep->num_ob_windows; index++)
-    {
-        if (ep->ob_src_addr[index] != dpu_offset)
-            continue;
-        *atu_index = index;
-        return 0;
-    }
+	for (index = 0; index < ep->num_ob_windows; index++) {
+		if (ep->ob_src_addr[index] != dpu_offset)
+			continue;
+		*atu_index = index;
+		return 0;
+	}
 
-    return -EINVAL;
+	return -EINVAL;
 }
 #endif
 
 // if ep is link up, return 1
 int pcie_zf_link_up(int ep_id)
 {
-    u32 val = 0;
+	u32 val = 0;
 
-    if (ep_id < 0 || ep_id >= PCIE_DPU_EP_NUM)
-    {
-        DH_LOG_ERR(MODULE_MPF, "pcie_zf_link_up:err ep_id!\n");
-        return -1;
-    }
+	if (ep_id < 0 || ep_id >= PCIE_DPU_EP_NUM) {
+		DH_LOG_ERR(MODULE_MPF, "pcie_zf_link_up:err ep_id!\n");
+		return -1;
+	}
 
-    val = readl(zf_ep->dpu_ep_array[ep_id]->dbi_base + PCIE_PORT_DEBUG1);
-    return ((val & PCIE_PORT_DEBUG1_ZTE_ZF_LINK_UP) &&
-            (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
+	val = readl(zf_ep->dpu_ep_array[ep_id]->dbi_base + PCIE_PORT_DEBUG1);
+	return ((val & PCIE_PORT_DEBUG1_ZTE_ZF_LINK_UP) &&
+			(!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
 }
 EXPORT_SYMBOL_GPL(pcie_zf_link_up);
 
 void ep_power_reset(int ep_id)
 {
-    u64 csr_base_addr = 0;
+	u64 csr_base_addr = 0;
 
-    csr_base_addr = zf_ep->mpf_paddr + PCIE_DPU_MPF_CSR_ADDR(PCIE_DPU_EP_CSR_SIZE * ep_id);
-    cfg_phy_rmw(csr_base_addr + PCIE_DPU_EP_CSR_PRST_ADDR, 0x0, 0x2);
-    cfg_phy_rmw(csr_base_addr + PCIE_DPU_EP_CSR_PRST_ADDR, 0x2, 0x2);
+	csr_base_addr = zf_ep->mpf_paddr +
+					PCIE_DPU_MPF_CSR_ADDR(PCIE_DPU_EP_CSR_SIZE * ep_id);
+	cfg_phy_rmw(csr_base_addr + PCIE_DPU_EP_CSR_PRST_ADDR, 0x0, 0x2);
+	cfg_phy_rmw(csr_base_addr + PCIE_DPU_EP_CSR_PRST_ADDR, 0x2, 0x2);
 }
 EXPORT_SYMBOL_GPL(ep_power_reset);
 
 int ep_virtio_module_set(int ep_id, int pf_idx, int en)
 {
-    u64 csr_base_addr = 0;
+	u64 csr_base_addr = 0;
 
-    csr_base_addr = zf_ep->mpf_paddr + PCIE_DPU_MPF_CSR_ADDR(PCIE_DPU_EP_CSR_SIZE * ep_id);
-    if ((0 != en) & (1 != en))
-    {
-        DH_LOG_ERR(MODULE_MPF, "err module!\n");
-        return -EINVAL;
-    }
-    cfg_phy_rmw(csr_base_addr + PCIE_DPU_EP_CSR_VIRT_ADDR, en << pf_idx, 0x1 << pf_idx);
-    return 0;
+	csr_base_addr = zf_ep->mpf_paddr +
+					PCIE_DPU_MPF_CSR_ADDR(PCIE_DPU_EP_CSR_SIZE * ep_id);
+	if ((0 != en) & (1 != en)) {
+		DH_LOG_ERR(MODULE_MPF, "err module!\n");
+		return -EINVAL;
+	}
+	cfg_phy_rmw(csr_base_addr + PCIE_DPU_EP_CSR_VIRT_ADDR, en << pf_idx,
+				0x1 << pf_idx);
+	return 0;
 }
 EXPORT_SYMBOL_GPL(ep_virtio_module_set);
 
 static phys_addr_t ob_addr_set(int ep_id, phys_addr_t phys_addr)
 {
-    phys_addr_t rel_addr;
-    u64 addr_mask = 0xffff;
+	phys_addr_t rel_addr;
+	u64 addr_mask = 0xffff;
 
-    rel_addr = (phys_addr & addr_mask) | ep_id << 16 | ((phys_addr & ~addr_mask) << EP_ID_LEN);
-    return rel_addr;
+	rel_addr = (phys_addr & addr_mask) | ep_id << 16 |
+			   ((phys_addr & ~addr_mask) << EP_ID_LEN);
+	return rel_addr;
 }
 
-int pcie_zte_epc_ob_read(struct pci_epc *epc, phys_addr_t phys_addr, unsigned int size, unsigned int *val)
+int pcie_zte_epc_ob_read(struct pci_epc *epc, phys_addr_t phys_addr, int size,
+						 int *val)
 {
-    void __iomem *vaddr = NULL;
-    struct pcie_dpu_ep *dpu_dev = NULL;
+	void __iomem *vaddr = NULL;
+	struct pcie_dpu_ep *dpu_dev = NULL;
 
-    if (!epc)
-    {
-        DH_LOG_ERR(MODULE_MPF, "epc is NULL!\n");
-        return -ENOMEM;
-    }
+	if (!epc) {
+		DH_LOG_ERR(MODULE_MPF, "epc is NULL!\n");
+		return -ENOMEM;
+	}
 
-    if (phys_addr < zf_ep->mpf_paddr || phys_addr >= zf_ep->mpf_paddr + zf_ep->ob_size)
-    {
-        DH_LOG_ERR(MODULE_MPF, "err:phys_addr out of range!\n");
-        return -ENOMEM;
-    }
+	if (phys_addr < zf_ep->mpf_paddr ||
+		phys_addr >= zf_ep->mpf_paddr + zf_ep->ob_size) {
+		DH_LOG_ERR(MODULE_MPF, "err:phys_addr out of range!\n");
+		return -ENOMEM;
+	}
 
-    dpu_dev = epc_get_drvdata(epc);
-    vaddr = zf_ep->mpf_vaddr + ob_addr_set(dpu_dev->ep_id + 5, phys_addr - zf_ep->mpf_paddr);
+	dpu_dev = epc_get_drvdata(epc);
+	vaddr = zf_ep->mpf_vaddr +
+			ob_addr_set(dpu_dev->ep_id + 5, phys_addr - zf_ep->mpf_paddr);
 
-    return pcie_zf_read(vaddr, size, val);
+	return pcie_zf_read(vaddr, size, val);
 }
 EXPORT_SYMBOL_GPL(pcie_zte_epc_ob_read);
 
-int pcie_zte_epc_ob_write(struct pci_epc *epc, phys_addr_t phys_addr, int size, int val)
+int pcie_zte_epc_ob_write(struct pci_epc *epc, phys_addr_t phys_addr, int size,
+						  int val)
 {
-    void __iomem *vaddr = NULL;
-    struct pcie_dpu_ep *dpu_dev = NULL;
+	void __iomem *vaddr = NULL;
+	struct pcie_dpu_ep *dpu_dev = NULL;
 
-    if (!epc)
-    {
-        DH_LOG_ERR(MODULE_MPF, "epc is NULL\n");
-        return -ENOMEM;
-    }
+	if (!epc) {
+		DH_LOG_ERR(MODULE_MPF, "epc is NULL\n");
+		return -ENOMEM;
+	}
 
-    if (phys_addr < zf_ep->mpf_paddr || phys_addr >= zf_ep->mpf_paddr + zf_ep->ob_size)
-    {
-        DH_LOG_ERR(MODULE_MPF, "err:phys_addr out of range\n");
-        return -ENOMEM;
-    }
+	if (phys_addr < zf_ep->mpf_paddr ||
+		phys_addr >= zf_ep->mpf_paddr + zf_ep->ob_size) {
+		DH_LOG_ERR(MODULE_MPF, "err:phys_addr out of range\n");
+		return -ENOMEM;
+	}
 
-    dpu_dev = epc_get_drvdata(epc);
+	dpu_dev = epc_get_drvdata(epc);
 
-    vaddr = zf_ep->mpf_vaddr + ob_addr_set(dpu_dev->ep_id + 5, phys_addr - zf_ep->mpf_paddr);
+	vaddr = zf_ep->mpf_vaddr +
+			ob_addr_set(dpu_dev->ep_id + 5, phys_addr - zf_ep->mpf_paddr);
 
-    return pcie_zf_write(vaddr, size, val);
+	return pcie_zf_write(vaddr, size, val);
 }
 EXPORT_SYMBOL_GPL(pcie_zte_epc_ob_write);
 
 /*################the ops of epc###################*/
 #if 1
-static int pcie_dpu_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
-                                    struct pci_epf_header *hdr)
-{
-    struct pcie_dpu_ep *ep = epc_get_drvdata(epc);
-    u32 func_offset = 0, sriov_offset = 0;
-    int sriov_cap_offset = 0;
-    int pf_no = func_no & PCIE_DPU_EP_GET_PF_NO;
-
-    DH_LOG_INFO(MODULE_MPF, "func_no = 0x%x, vfunc_no = 0x%x\n", func_no, vfunc_no);
-
-    pcie_zf_dbi_ro_wr_en(ep);
-    if (isPF(func_no))
-    {
-        func_offset = pcie_dpu_ep_func_select(func_no, 0);
-        pcie_zf_writew_dbi(ep, func_offset + PCI_VENDOR_ID, hdr->vendorid);
-        pcie_zf_writew_dbi(ep, func_offset + PCI_DEVICE_ID, hdr->deviceid);
-        pcie_zf_writel_dbi(ep, func_offset + PCI_CLASS_REVISION, hdr->revid | hdr->progif_code << 8 | hdr->subclass_code << 16 | hdr->baseclass_code << 24);
-        pcie_zf_writew_dbi(ep, func_offset + PCI_SUBSYSTEM_VENDOR_ID, hdr->subsys_vendor_id);
-        pcie_zf_writew_dbi(ep, func_offset + PCI_SUBSYSTEM_ID, hdr->subsys_id);
-    }
-    else
-    {
-        func_offset = pcie_dpu_ep_func_select(pf_no, 0);
-        sriov_cap_offset = pcie_dpu_ep_find_extcap(ep, func_offset, PCI_EXT_CAP_ID_SRIOV, 0);
-        if (sriov_cap_offset < 0)
-        {
-            DH_LOG_ERR(MODULE_MPF, "find_extcap failed!!\n");
-        }
-        sriov_offset = func_offset + (u32)sriov_cap_offset;
-        pcie_zf_writew_dbi(ep, sriov_offset + PCIE_SRIOV_ECAP_DEVICE_ID, hdr->deviceid);
-    }
-    pcie_zf_dbi_ro_wr_dis(ep);
-
-    return 0;
+static int pcie_dpu_ep_write_header(struct pci_epc *epc, u8 func_no,
+									u8 vfunc_no, struct pci_epf_header *hdr)
+{
+	struct pcie_dpu_ep *ep = epc_get_drvdata(epc);
+	u32 func_offset = 0, sriov_offset = 0;
+	int pf_no = func_no & PCIE_DPU_EP_GET_PF_NO;
+
+	DH_LOG_INFO(MODULE_MPF, "func_no = 0x%x, vfunc_no = 0x%x\n", func_no,
+				vfunc_no);
+
+	pcie_zf_dbi_ro_wr_en(ep);
+	if (isPF(func_no)) {
+		func_offset = pcie_dpu_ep_func_select(func_no, 0);
+		pcie_zf_writew_dbi(ep, func_offset + PCI_VENDOR_ID, hdr->vendorid);
+		pcie_zf_writew_dbi(ep, func_offset + PCI_DEVICE_ID, hdr->deviceid);
+		pcie_zf_writel_dbi(ep, func_offset + PCI_CLASS_REVISION,
+						   hdr->revid | hdr->progif_code << 8 |
+								   hdr->subclass_code << 16 |
+								   hdr->baseclass_code << 24);
+		pcie_zf_writew_dbi(ep, func_offset + PCI_SUBSYSTEM_VENDOR_ID,
+						   hdr->subsys_vendor_id);
+		pcie_zf_writew_dbi(ep, func_offset + PCI_SUBSYSTEM_ID, hdr->subsys_id);
+	} else {
+		func_offset = pcie_dpu_ep_func_select(pf_no, 0);
+		sriov_offset =
+				func_offset + pcie_dpu_ep_find_extcap(ep, func_offset,
+													  PCI_EXT_CAP_ID_SRIOV, 0);
+		pcie_zf_writew_dbi(ep, sriov_offset + PCIE_SRIOV_ECAP_DEVICE_ID,
+						   hdr->deviceid);
+	}
+	pcie_zf_dbi_ro_wr_dis(ep);
+
+	return 0;
 }
 
 static int pcie_dpu_ep_set_pf_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
-                                  struct pci_epf_bar *epf_bar)
-{
-    int ret = 0;
-    struct pcie_dpu_ep *ep = epc_get_drvdata(epc);
-    enum pci_barno barno = epf_bar->barno;
-    size_t size = epf_bar->size;
-    int flags = epf_bar->flags;
-    enum pcie_dpu_as_type as_type;
-    u32 reg = 0;
-    u32 func_offset = 0;
-    u64 dpu_addr = 0;
-
-    dpu_addr = epf_bar->phys_addr | ZF_PREFIX_ADDR;
-
-    if (!(flags & PCI_BASE_ADDRESS_SPACE))
-        as_type = PCIE_DPU_AS_MEM;
-    else
-        as_type = PCIE_DPU_AS_IO;
-
-    if (barno != BAR_4)
-    {
-        ret = pcie_dpu_ep_inbound_atu(ep, func_no, barno, dpu_addr, as_type);
-        if (ret)
-            return ret;
-    }
-    else
-    {
-        return 0;
-    }
-
-    func_offset = pcie_dpu_ep_func_select(func_no, vfunc_no);
-
-    if (barno != BAR_ROM)
-    {
-        reg = PCI_BASE_ADDRESS_0 + (4 * barno) + func_offset;
-    }
-    else
-    {
-        reg = PCI_ROM_ADDRESS + func_offset;
-    }
-
-    if (size)
-    {
-        pcie_zf_dbi_ro_wr_en(ep);
-
-        pcie_zf_writel_dbi2(ep, reg, 1);
-        pcie_zf_writel_dbi2(ep, reg, lower_32_bits(size - 1));
-        pcie_zf_writel_dbi(ep, reg, flags | BIT(3));
-        if (barno != BAR_ROM)
-        {
-            pcie_zf_writel_dbi2(ep, reg + PCIE_NEXT_BAR_OFFSET, upper_32_bits(size - 1));
-            pcie_zf_writel_dbi(ep, reg + PCIE_NEXT_BAR_OFFSET, 0);
-        }
-        pcie_zf_dbi_ro_wr_dis(ep);
-    }
-
-    return 0;
+								  struct pci_epf_bar *epf_bar)
+{
+	int ret = 0;
+	struct pcie_dpu_ep *ep = epc_get_drvdata(epc);
+	enum pci_barno barno = epf_bar->barno;
+	size_t size = epf_bar->size;
+	int flags = epf_bar->flags;
+	enum pcie_dpu_as_type as_type;
+	u32 reg = 0;
+	u32 func_offset = 0;
+	u64 dpu_addr = 0;
+
+	dpu_addr = epf_bar->phys_addr | ZF_PREFIX_ADDR;
+
+	if (!(flags & PCI_BASE_ADDRESS_SPACE))
+		as_type = PCIE_DPU_AS_MEM;
+	else
+		as_type = PCIE_DPU_AS_IO;
+
+	if (barno != BAR_4) {
+		ret = pcie_dpu_ep_inbound_atu(ep, func_no, barno, dpu_addr, as_type);
+		if (ret)
+			return ret;
+	} else {
+		return 0;
+	}
+
+	func_offset = pcie_dpu_ep_func_select(func_no, vfunc_no);
+
+	if (barno != BAR_ROM) {
+		reg = PCI_BASE_ADDRESS_0 + (4 * barno) + func_offset;
+	} else {
+		reg = PCI_ROM_ADDRESS + func_offset;
+	}
+
+	if (size) {
+		pcie_zf_dbi_ro_wr_en(ep);
+
+		pcie_zf_writel_dbi2(ep, reg, 1);
+		pcie_zf_writel_dbi2(ep, reg, lower_32_bits(size - 1));
+		pcie_zf_writel_dbi(ep, reg, flags | BIT(3));
+		if (barno != BAR_ROM) {
+			pcie_zf_writel_dbi2(ep, reg + PCIE_NEXT_BAR_OFFSET,
+								upper_32_bits(size - 1));
+			pcie_zf_writel_dbi(ep, reg + PCIE_NEXT_BAR_OFFSET, 0);
+		}
+		pcie_zf_dbi_ro_wr_dis(ep);
+	}
+
+	return 0;
 }
 
 static int pcie_dpu_ep_set_vf_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
-                                  struct pci_epf_bar *epf_bar)
-{
-    int ret = 0;
-    struct pcie_dpu_ep *ep = epc_get_drvdata(epc);
-    enum pci_barno barno = epf_bar->barno;
-    int flags = epf_bar->flags;
-    u32 reg = 0;
-    u32 func_offset = 0;
-    int sriov_cap_offset = 0;
-    u32 pf_func_no = func_no & PCIE_DPU_EP_GET_PF_NO;
-    u64 dpu_addr = epf_bar->phys_addr | ZF_PREFIX_ADDR;
-
-    if (flags & PCI_BASE_ADDRESS_SPACE)
-    {
-        DH_LOG_ERR(MODULE_MPF, "error:vf bar must be mem\n");
-        return -EINVAL;
-    }
-
-    DH_LOG_DEBUG(MODULE_MPF, "pf%x vf%x bar->flags:%d\n", pf_func_no, vfunc_no, flags);
-
-    if (barno != BAR_4)
-    {
-        ret = pcie_dpu_ep_inbound_atu(ep, func_no, barno,
-                                      dpu_addr, PCIE_DPU_AS_MEM);
-        if (ret)
-            return ret;
-    }
-    else
-    {
-        return 0;
-    }
-
-    func_offset = pcie_dpu_ep_func_select(pf_func_no, 0);
-    sriov_cap_offset = pcie_dpu_ep_find_extcap(ep, func_offset, PCI_EXT_CAP_ID_SRIOV, 0);
-    if (sriov_cap_offset < 0)
-    {
-        DH_LOG_ERR(MODULE_MPF, "find_extcap failed!!\n");
-        return -ENXIO;
-    }
-
-    reg = func_offset + sriov_cap_offset;
-    pcie_dpu_ep_sriov_disable(ep, reg);
-    if (epf_bar->size)
-    {
-        pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR0_OFFSET + barno * PCIE_NEXT_BAR_OFFSET, 1);
-        pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR0_OFFSET + barno * PCIE_NEXT_BAR_OFFSET, lower_32_bits(epf_bar->size - 1));
-        pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR0_OFFSET + (barno + 1) * PCIE_NEXT_BAR_OFFSET, upper_32_bits(epf_bar->size - 1));
-    }
-    pcie_zf_dbi_ro_wr_en(ep);
-    pcie_zf_writel_dbi(ep, reg + PCIE_SRIOV_ECAP_BAR0_OFFSET + barno * PCIE_NEXT_BAR_OFFSET, epf_bar->flags | BIT(3));
-    pcie_zf_dbi_ro_wr_dis(ep);
-
-    pcie_dpu_ep_sriov_enable(ep, reg);
-
-    return 0;
-}
-
-static int pcie_dpu_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_bar *epf_bar)
-{
-    DH_LOG_DEBUG(MODULE_MPF, "func:0x%x vfunc:0x%x\n", func_no, vfunc_no);
-    if (isPF(func_no))
-    {
-        return pcie_dpu_ep_set_pf_bar(epc, func_no, vfunc_no, epf_bar);
-    }
-    else if (vfunc_no == 0)
-    {
-        return pcie_dpu_ep_set_vf_bar(epc, func_no, vfunc_no, epf_bar);
-    }
-
-    return 0;
+								  struct pci_epf_bar *epf_bar)
+{
+	int ret = 0;
+	struct pcie_dpu_ep *ep = epc_get_drvdata(epc);
+	enum pci_barno barno = epf_bar->barno;
+	int flags = epf_bar->flags;
+	u32 reg = 0;
+	u32 func_offset = 0;
+	u32 sriov_cap_offset = 0;
+	u32 pf_func_no = func_no & PCIE_DPU_EP_GET_PF_NO;
+	u64 dpu_addr = epf_bar->phys_addr | ZF_PREFIX_ADDR;
+
+	if (flags & PCI_BASE_ADDRESS_SPACE) {
+		DH_LOG_ERR(MODULE_MPF, "error:vf bar must be mem\n");
+		return -EINVAL;
+	}
+
+	DH_LOG_DEBUG(MODULE_MPF, "pf%x vf%x bar->flags:%d\n", pf_func_no, vfunc_no,
+				 flags);
+
+	if (barno != BAR_4) {
+		ret = pcie_dpu_ep_inbound_atu(ep, func_no, barno, dpu_addr,
+									  PCIE_DPU_AS_MEM);
+		if (ret)
+			return ret;
+	} else {
+		return 0;
+	}
+
+	func_offset = pcie_dpu_ep_func_select(pf_func_no, 0);
+	sriov_cap_offset =
+			pcie_dpu_ep_find_extcap(ep, func_offset, PCI_EXT_CAP_ID_SRIOV, 0);
+	if (sriov_cap_offset < 0) {
+		DH_LOG_ERR(MODULE_MPF, "find_extcap failed!!\n");
+		return -ENXIO;
+	}
+
+	reg = func_offset + sriov_cap_offset;
+	pcie_dpu_ep_sriov_disable(ep, reg);
+	if (epf_bar->size) {
+		pcie_zf_writel_dbi2(ep,
+							reg + PCIE_SRIOV_ECAP_BAR0_OFFSET +
+									barno * PCIE_NEXT_BAR_OFFSET,
+							1);
+		pcie_zf_writel_dbi2(ep,
+							reg + PCIE_SRIOV_ECAP_BAR0_OFFSET +
+									barno * PCIE_NEXT_BAR_OFFSET,
+							lower_32_bits(epf_bar->size - 1));
+		pcie_zf_writel_dbi2(ep,
+							reg + PCIE_SRIOV_ECAP_BAR0_OFFSET +
+									(barno + 1) * PCIE_NEXT_BAR_OFFSET,
+							upper_32_bits(epf_bar->size - 1));
+	}
+	pcie_zf_dbi_ro_wr_en(ep);
+	pcie_zf_writel_dbi(ep,
+					   reg + PCIE_SRIOV_ECAP_BAR0_OFFSET +
+							   barno * PCIE_NEXT_BAR_OFFSET,
+					   epf_bar->flags | BIT(3));
+	pcie_zf_dbi_ro_wr_dis(ep);
+
+	pcie_dpu_ep_sriov_enable(ep, reg);
+
+	return 0;
+}
+
+static int pcie_dpu_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
+							   struct pci_epf_bar *epf_bar)
+{
+	DH_LOG_DEBUG(MODULE_MPF, "func:0x%x vfunc:0x%x\n", func_no, vfunc_no);
+	if (isPF(func_no)) {
+		return pcie_dpu_ep_set_pf_bar(epc, func_no, vfunc_no, epf_bar);
+	} else if (vfunc_no == 0) {
+		return pcie_dpu_ep_set_vf_bar(epc, func_no, vfunc_no, epf_bar);
+	}
+
+	return 0;
 }
 
 static void pcie_dpu_ep_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
-                                  bool clear_vf, struct pci_epf_bar *epf_bar)
-{
-    struct pcie_dpu_ep *ep = epc_get_drvdata(epc);
-    u32 vf_bar_off = 0;
-    enum pci_barno barno = epf_bar->barno;
-    int atu_index = 0;
-    u32 bar_to_atu_index = 0;
-
-    if ((func_no & PCIE_DPU_EP_GET_PF_NO) >= PCIE_DPU_PF_NUMS)
-    {
-        DH_LOG_ERR(MODULE_MPF, "func_no is err!\n");
-        return;
-    }
-
-    if ((barno == BAR_4) || (!isPF(func_no) && !vfunc_no))
-    {
-        return;
-    }
-
-    if (!isPF(func_no))
-    {
-        vf_bar_off = PCIE_VF_BARS_OFF;
-    }
-
-    bar_to_atu_index = (u32)barno + vf_bar_off;
-    if (bar_to_atu_index < (PCI_STD_NUM_BARS * 2 + 1))
-    {
-        atu_index = ep->bar_to_atu[func_no & PCIE_DPU_EP_GET_PF_NO][bar_to_atu_index];
-    }
-    else
-    {
-        DH_LOG_ERR(MODULE_MPF, "error bar_to_atu index %d\r\n", bar_to_atu_index);
-        return;
-    }
-
-    pcie_dpu_ep_reset_bar(ep, func_no, vfunc_no, barno, epf_bar->flags);
-
-    pcie_zf_disable_atu(ep, atu_index, PCIE_DPU_REGION_INBOUND);
-    spin_lock(&ep->ib_window_lock);
-    clear_bit(atu_index, ep->ib_window_map);
-    spin_unlock(&ep->ib_window_lock);
+								  bool clear_vf, struct pci_epf_bar *epf_bar)
+{
+	struct pcie_dpu_ep *ep = epc_get_drvdata(epc);
+	int vf_bar_off = 0;
+	enum pci_barno barno = epf_bar->barno;
+	int atu_index = 0;
+
+	if ((barno == BAR_4) || (!isPF(func_no) && !vfunc_no)) {
+		return;
+	}
+
+	if (!isPF(func_no)) {
+		vf_bar_off = PCIE_VF_BARS_OFF;
+	}
+
+	atu_index = ep->bar_to_atu[barno + vf_bar_off];
+
+	pcie_dpu_ep_reset_bar(ep, func_no, vfunc_no, barno, epf_bar->flags);
+
+	pcie_zf_disable_atu(ep, atu_index, PCIE_DPU_REGION_INBOUND);
+	clear_bit(atu_index, ep->ib_window_map);
 }
 
 static int pcie_dpu_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
-                                phys_addr_t dpu_offset, u64 host_addr, size_t size)
+								phys_addr_t dpu_offset, u64 host_addr,
+								size_t size)
 {
-    int ret = 0;
-    struct pcie_dpu_ep *ep = epc_get_drvdata(epc);
+	int ret = 0;
+	struct pcie_dpu_ep *ep = epc_get_drvdata(epc);
 
-    DH_LOG_INFO(MODULE_MPF, "func_no = 0x%x, dpu_addr = 0x%llx, host_addr = 0x%llx\n", func_no, dpu_offset, host_addr);
-    ret = pcie_dpu_ep_outbound_atu(ep, func_no, vfunc_no, dpu_offset - zf_ep->mpf_paddr, host_addr, size);
-    if (ret)
-    {
-        DH_LOG_ERR(MODULE_MPF, "Failed to enable address\r\n");
-        return ret;
-    }
+	DH_LOG_INFO(MODULE_MPF,
+				"func_no = 0x%x, dpu_addr = 0x%llx, host_addr = 0x%llx\n",
+				func_no, dpu_offset, host_addr);
+	ret = pcie_dpu_ep_outbound_atu(ep, func_no, vfunc_no,
+								   dpu_offset - zf_ep->mpf_paddr, host_addr,
+								   size);
+	if (ret) {
+		dev_err(&ep->epc->dev, "Failed to enable address\r\n");
+		return ret;
+	}
 
-    return 0;
+	return 0;
 }
 
-static void pcie_dpu_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
-                                   u8 vfunc_no, phys_addr_t dpu_offset)
+static void pcie_dpu_ep_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
+								   phys_addr_t dpu_offset)
 {
-    int ret = 0;
-    u32 atu_index = 0;
-    struct pcie_dpu_ep *ep = epc_get_drvdata(epc);
+	int ret = 0;
+	u32 atu_index = 0;
+	struct pcie_dpu_ep *ep = epc_get_drvdata(epc);
 
-    ret = pcie_zf_find_index(ep, dpu_offset - zf_ep->mpf_paddr, &atu_index);
-    if (ret < 0)
-        return;
+	ret = pcie_zf_find_index(ep, dpu_offset - zf_ep->mpf_paddr, &atu_index);
+	if (ret < 0)
+		return;
 
-    pcie_zf_disable_atu(ep, atu_index, PCIE_DPU_REGION_OUTBOUND);
-    clear_bit(atu_index, ep->ob_window_map);
+	pcie_zf_disable_atu(ep, atu_index, PCIE_DPU_REGION_OUTBOUND);
+	clear_bit(atu_index, ep->ob_window_map);
 }
 
-static int pcie_dpu_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u8 interrupts)
+static int pcie_dpu_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
+							   u8 interrupts)
 {
-    DH_LOG_ERR(MODULE_MPF, "error:pcie_dpu_ep can't set msi#\n");
-    return -ESRCH;
+	DH_LOG_ERR(MODULE_MPF, "error:pcie_dpu_ep can't set msi#\n");
+	return -ESRCH;
 }
 
 static int pcie_dpu_ep_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
 {
-    DH_LOG_ERR(MODULE_MPF, "error:pcie_dpu_ep can't get msi#\n");
-    return -ESRCH;
+	DH_LOG_ERR(MODULE_MPF, "error:pcie_dpu_ep can't get msi#\n");
+	return -ESRCH;
 }
 
 static int pcie_dpu_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
-                                u16 interrupts, enum pci_barno bir, u32 bar_offset)
+								u16 interrupts, enum pci_barno bir,
+								u32 bar_offset)
 {
-    /*
-     * MSIX tables are fixed in BAR4 (mapped to PCIe IP), other configs
-     * will make MSIX unable to function.
-     */
-    dev_warn(&epc->dev, "MSIX config is not supported by ZF epc\n");
+	/*
+   * MSIX tables are fixed in BAR4 (mapped to PCIe IP), other configs
+   * will make MSIX unable to function.
+   */
+	dev_warn(&epc->dev, "MSIX config is not supported by ZF epc\n");
 
-    return 0;
+	return 0;
 }
 
 int pcie_dpu_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
 {
-    struct pcie_dpu_ep *dpu_dev = epc_get_drvdata(epc);
-    u32 val, reg;
-    u32 func_offset = 0;
-    struct pcie_dpu_ep_func *ep_func;
+	struct pcie_dpu_ep *dpu_dev = epc_get_drvdata(epc);
+	u32 val, reg;
+	u32 func_offset = 0;
+	struct pcie_dpu_ep_func *ep_func;
 
-    ep_func = pcie_dpu_ep_get_func_from_ep(dpu_dev, func_no, vfunc_no);
-    if (!ep_func || !ep_func->msix_cap)
-        return -EINVAL;
+	ep_func = pcie_dpu_ep_get_func_from_ep(dpu_dev, func_no, vfunc_no);
+	if (!ep_func || !ep_func->msix_cap)
+		return -EINVAL;
 
-    func_offset = pcie_dpu_ep_func_select(func_no, vfunc_no);
+	func_offset = pcie_dpu_ep_func_select(func_no, vfunc_no);
 
-    reg = func_offset + ep_func->msix_cap + PCI_MSIX_FLAGS;
-    val = pcie_zf_readw_dbi(dpu_dev, reg);
-    if (!(val & PCI_MSIX_FLAGS_ENABLE))
-        return -EINVAL;
+	reg = func_offset + ep_func->msix_cap + PCI_MSIX_FLAGS;
+	val = pcie_zf_readw_dbi(dpu_dev, reg);
+	if (!(val & PCI_MSIX_FLAGS_ENABLE))
+		return -EINVAL;
 
-    val &= PCI_MSIX_FLAGS_QSIZE;
+	val &= PCI_MSIX_FLAGS_QSIZE;
 
-    return val;
+	return val;
 }
 
 int pcie_dpu_ep_raise_legacy_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
 {
-    DH_LOG_ERR(MODULE_MPF, "EP cannot trigger legacy IRQs\r\n");
+	dev_err(&epc->dev, "EP cannot trigger legacy IRQs\r\n");
 
-    return -EINVAL;
+	return -EINVAL;
 }
 
-int pcie_dpu_ep_raise_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u8 interrupt_num)
+int pcie_dpu_ep_raise_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
+							  u8 interrupt_num)
 {
-    DH_LOG_ERR(MODULE_MPF, "EP cannot trigger msi IRQs\r\n");
+	dev_err(&epc->dev, "EP cannot trigger msi IRQs\r\n");
 
-    return -EINVAL;
+	return -EINVAL;
 }
 
-int pcie_dpu_ep_raise_msix_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u8 interrupt_num)
+int pcie_dpu_ep_raise_msix_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
+							   u8 interrupt_num)
 {
-    struct pcie_dpu_ep *dpu_dev = epc_get_drvdata(epc);
-    u32 msg_data = 0;
+	struct pcie_dpu_ep *dpu_dev = epc_get_drvdata(epc);
+	u32 msg_data = 0;
 
-    // DH_LOG_INFO(MODULE_MPF, "func_no = 0x%x, vfunc_no = 0x%x, interrupt_num = 0x%x\n", func_no, vfunc_no, interrupt_num);
+	// DH_LOG_INFO(MODULE_MPF, "func_no = 0x%x, vfunc_no = 0x%x, interrupt_num =
+	// 0x%x\n", func_no, vfunc_no, interrupt_num);
 
-    if (isPF(func_no))
-    {
-        msg_data = (func_no << PCIE_MSIX_DOORBELL_PF_SHIFT) | (interrupt_num);
-    }
-    else
-    {
-        msg_data = ((func_no & PCIE_DPU_EP_GET_PF_NO) << PCIE_MSIX_DOORBELL_PF_SHIFT) |
-                   MSIX_DOORBELL_VF_ACTIVE | (vfunc_no << PCIE_MSIX_DOORBELL_VF_SHIFT) |
-                   (interrupt_num);
-    }
+	if (isPF(func_no)) {
+		msg_data = (func_no << PCIE_MSIX_DOORBELL_PF_SHIFT) | (interrupt_num);
+	} else {
+		msg_data = ((func_no & PCIE_DPU_EP_GET_PF_NO)
+					<< PCIE_MSIX_DOORBELL_PF_SHIFT) |
+				   MSIX_DOORBELL_VF_ACTIVE |
+				   (vfunc_no << PCIE_MSIX_DOORBELL_VF_SHIFT) | (interrupt_num);
+	}
 
-    pcie_zf_writel_dbi(dpu_dev, PCIE_MSIX_DOORBELL, msg_data);
+	pcie_zf_writel_dbi(dpu_dev, PCIE_MSIX_DOORBELL, msg_data);
 
-    return 0;
+	return 0;
 }
 
 static int pcie_dpu_ep_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
-                                 enum pci_epc_irq_type type, u16 interrupt_num)
-{
-    switch (type)
-    {
-        case PCI_EPC_IRQ_LEGACY:
-            return pcie_dpu_ep_raise_legacy_irq(epc, func_no, vfunc_no);
-        case PCI_EPC_IRQ_MSI:
-            return pcie_dpu_ep_raise_msi_irq(epc, func_no, vfunc_no, interrupt_num - 1);
-        case PCI_EPC_IRQ_MSIX:
-            return pcie_dpu_ep_raise_msix_irq(epc, func_no, vfunc_no, interrupt_num - 1);
-        default:
-            DH_LOG_ERR(MODULE_MPF, "UNKNOWN IRQ type\r\n");
-    }
-    return 0;
+								 enum pci_epc_irq_type type, u16 interrupt_num)
+{
+	switch (type) {
+	case PCI_EPC_IRQ_LEGACY:
+		return pcie_dpu_ep_raise_legacy_irq(epc, func_no, vfunc_no);
+	case PCI_EPC_IRQ_MSI:
+		return pcie_dpu_ep_raise_msi_irq(epc, func_no, vfunc_no,
+										 interrupt_num - 1);
+	case PCI_EPC_IRQ_MSIX:
+		return pcie_dpu_ep_raise_msix_irq(epc, func_no, vfunc_no,
+										  interrupt_num - 1);
+	default:
+		dev_err(&epc->dev, "UNKNOWN IRQ type\r\n");
+	}
+	return 0;
 }
 
 static int pcie_dpu_ep_get_max_vfs(struct pci_epc *epc, u8 func_no)
 {
-    struct pcie_dpu_ep *dpu_dev = NULL;
-    u32 vf_total_num = 0;
+	struct pcie_dpu_ep *dpu_dev = NULL;
 
-    if (epc == NULL)
-    {
-        DH_LOG_ERR(MODULE_MPF, "epc is NULL!!!\n");
-        return -EINVAL;
-    }
-    dpu_dev = epc_get_drvdata(epc);
-    vf_total_num = func_no & PCIE_DPU_EP_GET_PF_NO;
-    if (vf_total_num >= PCIE_DPU_PF_NUMS)
-    {
-        DH_LOG_ERR(MODULE_MPF, "error vf_total_num=%d\n", vf_total_num);
-        return -EINVAL;
-    }
-
-    DH_LOG_INFO(MODULE_MPF, "get vf max_num:%d\n", dpu_dev->vf_total_num[vf_total_num]);
-    return dpu_dev->vf_total_num[vf_total_num];
+	if (!epc) {
+		DH_LOG_ERR(MODULE_MPF, "epc is NULL!!!\n");
+		return -EINVAL;
+	}
+	dpu_dev = epc_get_drvdata(epc);
+	DH_LOG_INFO(MODULE_MPF, "get vf max_num:%d\n",
+				dpu_dev->vf_total_num[func_no & PCIE_DPU_EP_GET_PF_NO]);
+	return dpu_dev->vf_total_num[func_no & PCIE_DPU_EP_GET_PF_NO];
 }
 
 static void pcie_dpu_ep_stop(struct pci_epc *epc)
 {
-    DH_LOG_INFO(MODULE_MPF, "%s\n", __func__);
-    return;
+	DH_LOG_INFO(MODULE_MPF, "%s\n", __func__);
+	return;
 }
 
 static int pcie_dpu_ep_start(struct pci_epc *epc)
 {
-    DH_LOG_INFO(MODULE_MPF, "%s\n", __func__);
-    return 0;
+	DH_LOG_INFO(MODULE_MPF, "%s\n", __func__);
+	return 0;
 }
 
 static const struct pci_epc_features pcie_zf_epc_features = {
-    .linkup_notifier = false,
-    .msi_capable = false,
-    .msix_capable = true,
-    .reserved_bar = PCIE_DPU_EP_REAERVED_BAR,
-    .bar_fixed_64bit = PCIE_DPU_EP_BAR_FIXED_64BIT,
-    .align = PCIE_DPU_EP_ALIGN,
+	.linkup_notifier = false,
+	.msi_capable = false,
+	.msix_capable = true,
+	.reserved_bar = PCIE_DPU_EP_REAERVED_BAR,
+	.bar_fixed_64bit = PCIE_DPU_EP_BAR_FIXED_64BIT,
+	.align = PCIE_DPU_EP_ALIGN,
 };
 
 static const struct pci_epc_features *
 pcie_dpu_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
 {
-    return &pcie_zf_epc_features;
+	return &pcie_zf_epc_features;
 }
 
 static int pci_dpu_ep_get_port_id(struct pci_epc *epc,
-                                  enum pci_epc_port_id_type *id)
+								  enum pci_epc_port_id_type *id)
 {
-    struct pcie_dpu_ep *dpu_dev = epc_get_drvdata(epc);
+	struct pcie_dpu_ep *dpu_dev = epc_get_drvdata(epc);
 
-    *id = dpu_dev->ep_id + 5;
-    return 0;
+	*id = dpu_dev->ep_id + 5;
+	return 0;
 }
 
 static int pci_dpu_ep_calc_pfns(struct pci_epc *epc, phys_addr_t phys,
-                                size_t n_pfns, unsigned long *pfn)
+								size_t n_pfns, unsigned long *pfn)
 {
-    enum pci_epc_port_id_type port = 0;
-    phys_addr_t offset = 0, base = zf_ep->mpf_paddr;
-    size_t i = 0;
+	enum pci_epc_port_id_type port = 0;
+	phys_addr_t offset = 0, base = zf_ep->mpf_paddr;
+	size_t i = 0;
 
-    if (phys < base ||
-        phys - base + (n_pfns << PAGE_SHIFT) > zf_ep->ob_size)
-        return -EINVAL;
+	if (phys < base || phys - base + (n_pfns << PAGE_SHIFT) > zf_ep->ob_size)
+		return -EINVAL;
 
-    pci_dpu_ep_get_port_id(epc, &port);
+	pci_dpu_ep_get_port_id(epc, &port);
 
-    for (i = 0; i < n_pfns; i++)
-    {
-        offset = phys - base + (i << PAGE_SHIFT);
-        pfn[i] = (base + EP_DPU_PA(offset, port)) >> PAGE_SHIFT;
-    }
-    return 0;
+	for (i = 0; i < n_pfns; i++) {
+		offset = phys - base + (i << PAGE_SHIFT);
+		pfn[i] = (base + EP_DPU_PA(offset, port)) >> PAGE_SHIFT;
+	}
+	return 0;
 }
 
 #endif
 
 static const struct pci_epc_ops epc_ops = {
-    .write_header = pcie_dpu_ep_write_header,
-    .set_bar = pcie_dpu_ep_set_bar,
-    .clear_bar = pcie_dpu_ep_clear_bar,
-    .map_addr = pcie_dpu_ep_map_addr,
-    .unmap_addr = pcie_dpu_ep_unmap_addr,
-    .set_msi = pcie_dpu_ep_set_msi,
-    .get_msi = pcie_dpu_ep_get_msi,
-    .set_msix = pcie_dpu_ep_set_msix,
-    .get_msix = pcie_dpu_ep_get_msix,
-    .raise_irq = pcie_dpu_ep_raise_irq,
-    .get_max_vfs = pcie_dpu_ep_get_max_vfs,
-    .start = pcie_dpu_ep_start,
-    .stop = pcie_dpu_ep_stop,
-    .get_features = pcie_dpu_ep_get_features,
-    .get_port_id = pci_dpu_ep_get_port_id,
-    .calc_pfns = pci_dpu_ep_calc_pfns,
-    .get_xdma_chan = zf_pcie_get_hdma_chan,
+	.write_header = pcie_dpu_ep_write_header,
+	.set_bar = pcie_dpu_ep_set_bar,
+	.clear_bar = pcie_dpu_ep_clear_bar,
+	.map_addr = pcie_dpu_ep_map_addr,
+	.unmap_addr = pcie_dpu_ep_unmap_addr,
+	.set_msi = pcie_dpu_ep_set_msi,
+	.get_msi = pcie_dpu_ep_get_msi,
+	.set_msix = pcie_dpu_ep_set_msix,
+	.get_msix = pcie_dpu_ep_get_msix,
+	.raise_irq = pcie_dpu_ep_raise_irq,
+	.get_max_vfs = pcie_dpu_ep_get_max_vfs,
+	.start = pcie_dpu_ep_start,
+	.stop = pcie_dpu_ep_stop,
+	.get_features = pcie_dpu_ep_get_features,
+	.get_port_id = pci_dpu_ep_get_port_id,
+	.calc_pfns = pci_dpu_ep_calc_pfns,
+	.get_xdma_chan = zf_pcie_get_hdma_chan,
 };
 
 static void dpu_ep_default_set(int ep_id)
 {
-    u32 pf_idx = 0;
-    u32 func_offset = 0;
-    int sriov_cap_offset = 0;
-    u32 reg = 0;
-    struct pcie_dpu_ep *ep = zf_ep->dpu_ep_array[ep_id];
-
-    pcie_zf_dbi_ro_wr_en(ep);
-    for (pf_idx = 0; pf_idx < PCIE_DPU_PF_NUMS; ++pf_idx)
-    {
-        if (!(ep->permissible_pf_map & (0x1 << pf_idx)))
-        {
-            continue;
-        }
-        pcie_zf_writel_dbi(ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE, PCIE_DPU_PF_INITIAL_ID);
-        pcie_zf_writel_dbi(ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_CLASS_REVISION, PCIE_DPU_PF_DEFAUTL_CLASSCODE);
-        pcie_zf_writel_dbi2(ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_ROM_ADDRESS, ZF_DISABLE);
-
-        pcie_zf_writel_dbi2(ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_BASE_ADDRESS_4, ZF_ENABLE);
-        pcie_zf_writel_dbi2(ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_BASE_ADDRESS_4, lower_32_bits(BAR4_DEFAULT_SIZE - 1));
-        pcie_zf_writel_dbi2(ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_BASE_ADDRESS_4 + PCIE_NEXT_BAR_OFFSET, upper_32_bits(BAR4_DEFAULT_SIZE - 1));
-        pcie_zf_writel_dbi(ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_BASE_ADDRESS_4, PCIE_DEFAULT_BAR_FLAG);
-
-        func_offset = pcie_dpu_ep_func_select(pf_idx, 0);
-        sriov_cap_offset = pcie_dpu_ep_find_extcap(ep, func_offset, PCI_EXT_CAP_ID_SRIOV, 0);
-        if (sriov_cap_offset < 0)
-        {
-            DH_LOG_ERR(MODULE_MPF, "find_extcap failed!!\n");
-            return;
-        }
-
-        reg = func_offset + sriov_cap_offset;
-        pcie_dpu_ep_sriov_disable(ep, reg);
-        pcie_zf_writel_dbi(ep, reg + PCIE_SRIOV_ECAP_BAR4_OFFSET, PCIE_DEFAULT_BAR_FLAG);
-        pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR4_OFFSET, 0x1);
-        pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR4_OFFSET, lower_32_bits(BAR4_DEFAULT_SIZE - 1));
-        pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR4_OFFSET + PCIE_NEXT_BAR_OFFSET, upper_32_bits(BAR4_DEFAULT_SIZE - 1));
-        pcie_dpu_ep_sriov_enable(ep, reg);
-    }
-    pcie_zf_dbi_ro_wr_dis(ep);
+	u32 pf_idx = 0;
+	u32 func_offset = 0;
+	u32 sriov_cap_offset = 0;
+	u32 reg = 0;
+	struct pcie_dpu_ep *ep = zf_ep->dpu_ep_array[ep_id];
+
+	pcie_zf_dbi_ro_wr_en(ep);
+	for (pf_idx = 0; pf_idx < PCIE_DPU_PF_NUMS; ++pf_idx) {
+		if (!(ep->permissible_pf_map & (0x1 << pf_idx))) {
+			continue;
+		}
+		pcie_zf_writel_dbi(ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE,
+						   PCIE_DPU_PF_DEFAUTL_ID0);
+		pcie_zf_writel_dbi(
+				ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_CLASS_REVISION,
+				PCIE_DPU_PF_DEFAUTL_CLASSCODE);
+		pcie_zf_writel_dbi2(
+				ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_ROM_ADDRESS,
+				ZF_DISABLE);
+
+		pcie_zf_writel_dbi2(
+				ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_BASE_ADDRESS_4,
+				ZF_ENABLE);
+		pcie_zf_writel_dbi2(
+				ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_BASE_ADDRESS_4,
+				lower_32_bits(BAR4_DEFAULT_SIZE - 1));
+		pcie_zf_writel_dbi2(ep,
+							pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE +
+									PCI_BASE_ADDRESS_4 + PCIE_NEXT_BAR_OFFSET,
+							upper_32_bits(BAR4_DEFAULT_SIZE - 1));
+		pcie_zf_writel_dbi(
+				ep, pf_idx * PCIE_DPU_EP_FUNC_CFG_SIZE + PCI_BASE_ADDRESS_4,
+				PCIE_DEFAULT_BAR_FLAG);
+
+		func_offset = pcie_dpu_ep_func_select(pf_idx, 0);
+		sriov_cap_offset = pcie_dpu_ep_find_extcap(ep, func_offset,
+												   PCI_EXT_CAP_ID_SRIOV, 0);
+		if (sriov_cap_offset < 0) {
+			DH_LOG_ERR(MODULE_MPF, "find_extcap failed!!\n");
+			return;
+		}
+
+		reg = func_offset + sriov_cap_offset;
+		pcie_dpu_ep_sriov_disable(ep, reg);
+		pcie_zf_writel_dbi(ep, reg + PCIE_SRIOV_ECAP_BAR4_OFFSET,
+						   PCIE_DEFAULT_BAR_FLAG);
+		pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR4_OFFSET, 0x1);
+		pcie_zf_writel_dbi2(ep, reg + PCIE_SRIOV_ECAP_BAR4_OFFSET,
+							lower_32_bits(BAR4_DEFAULT_SIZE - 1));
+		pcie_zf_writel_dbi2(
+				ep, reg + PCIE_SRIOV_ECAP_BAR4_OFFSET + PCIE_NEXT_BAR_OFFSET,
+				upper_32_bits(BAR4_DEFAULT_SIZE - 1));
+		pcie_dpu_ep_sriov_enable(ep, reg);
+	}
+	pcie_zf_dbi_ro_wr_dis(ep);
 }
 
 static int dpu_ep_iatu_init(struct device *dev, int id)
 {
-    int iatu_no = 0;
-
-    zf_ep->dpu_ep_array[id]->num_ib_windows = PCIE_DPU_IATU_NUM;
-    zf_ep->dpu_ep_array[id]->num_ob_windows = PCIE_DPU_IATU_NUM;
-    zf_ep->dpu_ep_array[id]->ib_window_map = devm_kcalloc(dev, BITS_TO_LONGS(zf_ep->dpu_ep_array[id]->num_ib_windows),
-                                                          sizeof(long), GFP_KERNEL);
-    if (!zf_ep->dpu_ep_array[id]->ib_window_map)
-    {
-        DH_LOG_ERR(MODULE_MPF, "get ib_map err\n");
-        return -ENOMEM;
-    }
-
-    zf_ep->dpu_ep_array[id]->ob_window_map = devm_kcalloc(dev, BITS_TO_LONGS(zf_ep->dpu_ep_array[id]->num_ob_windows),
-                                                          sizeof(long), GFP_KERNEL);
-    if (!zf_ep->dpu_ep_array[id]->ob_window_map)
-    {
-        DH_LOG_ERR(MODULE_MPF, "get ob_map err\n");
-        goto free_ib_map;
-    }
-
-    zf_ep->dpu_ep_array[id]->ob_src_addr = devm_kcalloc(dev, zf_ep->dpu_ep_array[id]->num_ob_windows, sizeof(phys_addr_t),
-                                                        GFP_KERNEL);
-    if (!zf_ep->dpu_ep_array[id]->ob_src_addr)
-    {
-        DH_LOG_ERR(MODULE_MPF, "get ob_src_addr err\n");
-        goto free_ob_map;
-    }
-
-    // 确定哪些inbound已经被使用
-    for (iatu_no = 0; iatu_no < PCIE_DPU_IATU_NUM; iatu_no++)
-    {
-        if (zf_atu_is_used(zf_ep->dpu_ep_array[id], iatu_no))
-        {
-            set_bit(iatu_no, zf_ep->dpu_ep_array[id]->ib_window_map);
-        }
-    }
-
-    spin_lock_init(&zf_ep->dpu_ep_array[id]->ib_window_lock);
-
-    return 0;
+	int iatu_no = 0;
+
+	zf_ep->dpu_ep_array[id]->num_ib_windows = PCIE_DPU_IATU_NUM;
+	zf_ep->dpu_ep_array[id]->num_ob_windows = PCIE_DPU_IATU_NUM;
+	zf_ep->dpu_ep_array[id]->ib_window_map = devm_kcalloc(
+			dev, BITS_TO_LONGS(zf_ep->dpu_ep_array[id]->num_ib_windows),
+			sizeof(long), GFP_KERNEL);
+	if (!zf_ep->dpu_ep_array[id]->ib_window_map) {
+		DH_LOG_ERR(MODULE_MPF, "get ib_map err\n");
+		return -ENOMEM;
+	}
+
+	zf_ep->dpu_ep_array[id]->ob_window_map = devm_kcalloc(
+			dev, BITS_TO_LONGS(zf_ep->dpu_ep_array[id]->num_ob_windows),
+			sizeof(long), GFP_KERNEL);
+	if (!zf_ep->dpu_ep_array[id]->ob_window_map) {
+		DH_LOG_ERR(MODULE_MPF, "get ob_map err\n");
+		goto free_ib_map;
+	}
+
+	zf_ep->dpu_ep_array[id]->ob_src_addr =
+			devm_kcalloc(dev, zf_ep->dpu_ep_array[id]->num_ob_windows,
+						 sizeof(phys_addr_t), GFP_KERNEL);
+	if (!zf_ep->dpu_ep_array[id]->ob_src_addr) {
+		DH_LOG_ERR(MODULE_MPF, "get ob_src_addr err\n");
+		goto free_ob_map;
+	}
+
+	// 确定哪些inbound已经被使用
+	for (iatu_no = 0; iatu_no < PCIE_DPU_IATU_NUM; iatu_no++) {
+		if (zf_atu_is_used(zf_ep->dpu_ep_array[id], iatu_no)) {
+			set_bit(iatu_no, zf_ep->dpu_ep_array[id]->ib_window_map);
+		}
+	}
+
+	return 0;
 
 free_ob_map:
-    devm_kfree(dev, zf_ep->dpu_ep_array[id]->ob_window_map);
+	devm_kfree(dev, zf_ep->dpu_ep_array[id]->ob_window_map);
 free_ib_map:
-    devm_kfree(dev, zf_ep->dpu_ep_array[id]->ib_window_map);
-    return -ENOMEM;
+	devm_kfree(dev, zf_ep->dpu_ep_array[id]->ib_window_map);
+	return -ENOMEM;
 }
 
 static int dpu_ep_func_list_init(struct device *dev, int id)
 {
-    u8 func_no = 0, vfunc_no = 0;
-    u8 vf_total_num = 0;
-    u32 func_offset = 0;
-    struct pcie_dpu_ep_func *ep_func = NULL;
-
-    INIT_LIST_HEAD(&zf_ep->dpu_ep_array[id]->func_list);
-    for (func_no = 0; func_no < PCIE_DPU_PF_NUMS; ++func_no)
-    {
-        if (!(zf_ep->dpu_ep_array[id]->permissible_pf_map & (0x1 << func_no)))
-        {
-            continue;
-        }
-        ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL);
-        if (!ep_func)
-        {
-            return -ENOMEM;
-        }
-
-        ep_func->func_no = func_no;
-        func_offset = pcie_dpu_ep_func_select(func_no, vfunc_no);
-        ep_func->msix_cap = pcie_dpu_ep_find_cap(zf_ep->dpu_ep_array[id], func_offset, PCI_CAP_ID_MSIX);
-
-        list_add_tail(&ep_func->list, &zf_ep->dpu_ep_array[id]->func_list);
-
-        vf_total_num = (u8)zf_ep->dpu_ep_array[id]->vf_total_num[func_no];
-        for (vfunc_no = 0; vfunc_no < vf_total_num; ++vfunc_no)
-        {
-            ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL);
-            if (!ep_func)
-            {
-                return -ENOMEM;
-            }
-
-            ep_func->func_no = PCIE_DPU_EP_FUNC_IS_VF | func_no;
-            ep_func->vfunc_no = vfunc_no;
-            func_offset = pcie_dpu_ep_func_select(ep_func->func_no, vfunc_no);
-            ep_func->msix_cap = pcie_dpu_ep_find_cap(zf_ep->dpu_ep_array[id],
-                                                     func_offset, PCI_CAP_ID_MSIX);
-
-            list_add_tail(&ep_func->list, &zf_ep->dpu_ep_array[id]->func_list);
-        }
-    }
-
-    return 0;
+	u8 func_no = 0, vfunc_no = 0;
+	u32 func_offset = 0;
+	struct pcie_dpu_ep_func *ep_func = NULL;
+
+	INIT_LIST_HEAD(&zf_ep->dpu_ep_array[id]->func_list);
+	for (func_no = 0; func_no < PCIE_DPU_PF_NUMS; ++func_no) {
+		if (!(zf_ep->dpu_ep_array[id]->permissible_pf_map & (0x1 << func_no))) {
+			continue;
+		}
+		ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL);
+		if (!ep_func) {
+			return -ENOMEM;
+		}
+
+		ep_func->func_no = func_no;
+		func_offset = pcie_dpu_ep_func_select(func_no, vfunc_no);
+		ep_func->msix_cap = pcie_dpu_ep_find_cap(zf_ep->dpu_ep_array[id],
+												 func_offset, PCI_CAP_ID_MSIX);
+
+		list_add_tail(&ep_func->list, &zf_ep->dpu_ep_array[id]->func_list);
+
+		for (vfunc_no = 0;
+			 vfunc_no < zf_ep->dpu_ep_array[id]->vf_total_num[func_no];
+			 ++vfunc_no) {
+			ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL);
+			if (!ep_func) {
+				return -ENOMEM;
+			}
+
+			ep_func->func_no = PCIE_DPU_EP_FUNC_IS_VF | func_no;
+			ep_func->vfunc_no = vfunc_no;
+			func_offset = pcie_dpu_ep_func_select(ep_func->func_no, vfunc_no);
+			ep_func->msix_cap = pcie_dpu_ep_find_cap(
+					zf_ep->dpu_ep_array[id], func_offset, PCI_CAP_ID_MSIX);
+
+			list_add_tail(&ep_func->list, &zf_ep->dpu_ep_array[id]->func_list);
+		}
+	}
+
+	return 0;
 }
 
 static int dpu_ep_vf_total_num_get(int id)
 {
-    int func_no = 0, func_offset = 0, sriov_cap_offset = 0, vf_total_num_addr = 0;
+	int func_no = 0, func_offset = 0, sriov_cap_offset = 0,
+		vf_total_num_addr = 0;
 
-    for (func_no = 0; func_no < PCIE_DPU_PF_NUMS; ++func_no)
-    {
-        func_offset = pcie_dpu_ep_func_select(func_no, 0);
-        sriov_cap_offset = pcie_dpu_ep_find_extcap(zf_ep->dpu_ep_array[id], func_offset, PCI_EXT_CAP_ID_SRIOV, 0);
-        if (sriov_cap_offset < 0)
-        {
-            DH_LOG_ERR(MODULE_MPF, "find_extcap failed!!\n");
-            return -ENXIO;
-        }
-        vf_total_num_addr = func_offset + sriov_cap_offset + PCIE_SRIOV_TOTAL_VFS;
-        zf_ep->dpu_ep_array[id]->vf_total_num[func_no] = pcie_zf_readw_dbi(zf_ep->dpu_ep_array[id], vf_total_num_addr);
-    }
+	for (func_no = 0; func_no < PCIE_DPU_PF_NUMS; ++func_no) {
+		func_offset = pcie_dpu_ep_func_select(func_no, 0);
+		sriov_cap_offset = pcie_dpu_ep_find_extcap(
+				zf_ep->dpu_ep_array[id], func_offset, PCI_EXT_CAP_ID_SRIOV, 0);
+		if (sriov_cap_offset < 0) {
+			DH_LOG_ERR(MODULE_MPF, "find_extcap failed!!\n");
+			return -ENXIO;
+		}
+		vf_total_num_addr =
+				func_offset + sriov_cap_offset + PCIE_SRIOV_TOTAL_VFS;
+		zf_ep->dpu_ep_array[id]->vf_total_num[func_no] =
+				pcie_zf_readw_dbi(zf_ep->dpu_ep_array[id], vf_total_num_addr);
+	}
 
-    return 0;
+	return 0;
 }
 
 static int dpu_ep_get_permissible_pf(int id)
 {
-    int func_no = 0, func_offset = 0;
-    u32 func_id = 0;
+	int func_no = 0, func_offset = 0, func_id = 0;
 
-    for (func_no = 0; func_no < PCIE_DPU_PF_NUMS; ++func_no)
-    {
-        func_offset = pcie_dpu_ep_func_select(func_no, 0);
-        func_id = pcie_zf_readl_dbi(zf_ep->dpu_ep_array[id], func_offset);
-        if (PCIE_DPU_PF_DEFAUTL_ID1 == func_id || PCIE_DPU_PF_DEFAUTL_ID2 == func_id ||
-            PCIE_DPU_PF_DEFAUTL_ID3 == func_id || PCIE_DPU_PF_DEFAUTL_ID4 == func_id)
-        {
-            zf_ep->dpu_ep_array[id]->permissible_pf_map |= (0x1 << func_no);
-        }
-    }
+	for (func_no = 0; func_no < PCIE_DPU_PF_NUMS; ++func_no) {
+		func_offset = pcie_dpu_ep_func_select(func_no, 0);
+		func_id = pcie_zf_readl_dbi(zf_ep->dpu_ep_array[id], func_offset);
+		if (PCIE_DPU_PF_DEFAUTL_ID1 == func_id ||
+			PCIE_DPU_PF_DEFAUTL_ID2 == func_id ||
+			PCIE_DPU_PF_DEFAUTL_ID3 == func_id ||
+			PCIE_DPU_PF_DEFAUTL_ID4 == func_id) {
+			zf_ep->dpu_ep_array[id]->permissible_pf_map |= (0x1 << func_no);
+		}
+	}
 
-    return 0;
+	return 0;
 }
 
 static void epc_dev_release(struct device *dev)
@@ -1399,249 +1342,238 @@ static void epc_dev_release(struct device *dev)
 
 static int pci_zte_epc_dev_init_one(struct pci_dev *pdev, int id)
 {
-    struct pci_epc *epc = NULL;
-    struct device *dev = NULL;
-    struct device_node *np = NULL;
-    struct platform_device *zf_pdev = NULL;
-    struct platform_device *zf_pdev_dma = NULL;
-    char class_name[PCIE_DPU_EP_CLASS_NAME] = {0};
-    int node = 0, i = 0;
-    int ret = -ENOMEM;
-
-    snprintf(class_name, sizeof(class_name) - 1,"zf_epc_class%d", id);
-    zf_pdev = platform_device_register_simple(class_name, -1, NULL, 0);
-    if (!zf_pdev)
-    {
-        DH_LOG_ERR(MODULE_MPF, "Error platform_device_register zf_pdev failed\n");
-        return ret;
-    }
-
-    snprintf(class_name, sizeof(class_name) - 1,"zf_epc_dma_rd%d", id);
-    zf_pdev_dma = platform_device_register_simple(class_name, -1, NULL, 0);
-    if (!zf_pdev_dma)
-    {
-        DH_LOG_ERR(MODULE_MPF, "Error platform_device_register zf_pdev_dma failed\n");
-        return ret;
-    }
-
-    zf_pdev->dev.driver = pdev->dev.driver;
-    zf_pdev_dma->dev.driver = pdev->dev.driver;
-
-    dev = &zf_pdev->dev;
-    np = dev->of_node;
-    epc = pci_epc_create(dev, &epc_ops);
-    if (IS_ERR_OR_NULL(epc))
-    {
-        DH_LOG_ERR(MODULE_MPF, "Failed %ld to create epc device\n", PTR_ERR(epc));
-        ret = -EPERM;
-        goto free_pdev;
-    }
-
-    epc->dev.release = epc_dev_release;
-    epc->max_functions = PCIE_DPU_PF_NUMS;
-    epc->is_dpu_epc = 1;
-
-    ret = pci_epc_mem_init(epc, zf_ep->mpf_paddr, zf_ep->ob_size, PAGE_SIZE);
-    if (ret < 0)
-    {
-        DH_LOG_ERR(MODULE_MPF, "ep%d failed to initialize the memory space\n", id);
-        goto free_epc;
-    }
-
-    node = dev_to_node(dev); // 多核
-    if (node == NUMA_NO_NODE)
-        set_dev_node(dev, first_memory_node);
-
-    /*##################zf_dev init##################*/
-    zf_ep->dpu_ep_array[id] = kzalloc_node(sizeof(struct pcie_dpu_ep), GFP_KERNEL, node);
-    if (!zf_ep->dpu_ep_array[id])
-    {
-        DH_LOG_ERR(MODULE_MPF, "Error kzalloc node\n");
-        ret = -ENOMEM;
-        goto free_epc_mem;
-    }
-
-    zf_ep->dpu_ep_array[id]->ep_id = id;
-    zf_ep->dpu_ep_array[id]->epc = epc;
-    zf_ep->dpu_ep_array[id]->dbi_base = zf_ep->dbi_vaddr + PCIE_DPU_EP_DBI_SIZE * id;
-    zf_ep->dpu_ep_array[id]->atu_base = zf_ep->dpu_ep_array[id]->dbi_base + DEFAULT_DBI_ATU_OFFSET;
-    zf_ep->dpu_ep_array[id]->zf_pdev = zf_pdev;
-    zf_ep->dpu_ep_array[id]->zf_pdev_dma = zf_pdev_dma;
-
-    dpu_ep_default_set(id);
-
-    epc_set_drvdata(epc, zf_ep->dpu_ep_array[id]);
-
-    dpu_ep_get_permissible_pf(id);
-    for (i = 0; i < PCIE_DPU_PF_NUMS; i++)
-    {
-        if (!(zf_ep->dpu_ep_array[id]->permissible_pf_map & (0x1 << i)))
-        {
-            DH_LOG_INFO(MODULE_MPF, "ep%d pf%d can't uesd\n", id, i);
-            set_bit(i, &epc->function_num_map);
-        }
-    }
-
-    ret |= dpu_ep_iatu_init(&pdev->dev, id);
-    ret |= dpu_ep_vf_total_num_get(id);
-    ret |= dpu_ep_func_list_init(&pdev->dev, id);
-
-    if (ret)
-        goto free_dpu_ep;
-
-    return 0;
+	struct pci_epc *epc = NULL;
+	struct device *dev = NULL;
+	struct device_node *np = NULL;
+	struct platform_device *zf_pdev = NULL;
+	struct platform_device *zf_pdev_dma = NULL;
+	char class_name[PCIE_DPU_EP_CLASS_NAME] = { 0 };
+	int node = 0, i = 0;
+	int ret = -ENOMEM;
+
+	sprintf(class_name, "zf_epc_class%d", id);
+	zf_pdev = platform_device_register_simple(class_name, -1, NULL, 0);
+	if (!zf_pdev) {
+		DH_LOG_ERR(MODULE_MPF,
+				   "Error platform_device_register zf_pdev failed\n");
+		return ret;
+	}
+
+	sprintf(class_name, "zf_epc_dma_rd%d", id);
+	zf_pdev_dma = platform_device_register_simple(class_name, -1, NULL, 0);
+	if (!zf_pdev_dma) {
+		DH_LOG_ERR(MODULE_MPF,
+				   "Error platform_device_register zf_pdev_dma failed\n");
+		return ret;
+	}
+
+	zf_pdev->dev.driver = pdev->dev.driver;
+	zf_pdev_dma->dev.driver = pdev->dev.driver;
+
+	dev = &zf_pdev->dev;
+	np = dev->of_node;
+	epc = pci_epc_create(dev, &epc_ops);
+	if (IS_ERR_OR_NULL(epc)) {
+		DH_LOG_ERR(MODULE_MPF, "Failed %ld to create epc device\n",
+				   PTR_ERR(epc));
+		ret = -EPERM;
+		goto free_pdev;
+	}
+
+	epc->dev.release = epc_dev_release;
+	epc->max_functions = PCIE_DPU_PF_NUMS;
+	epc->is_dpu_epc = 1;
+
+	ret = pci_epc_mem_init(epc, zf_ep->mpf_paddr, zf_ep->ob_size, PAGE_SIZE);
+	if (ret < 0) {
+		DH_LOG_ERR(MODULE_MPF, "ep%d failed to initialize the memory space\n",
+				   id);
+		goto free_epc;
+	}
+
+	node = dev_to_node(dev); // 多核
+	if (node == NUMA_NO_NODE)
+		set_dev_node(dev, first_memory_node);
+
+	/*##################zf_dev init##################*/
+	zf_ep->dpu_ep_array[id] =
+			kzalloc_node(sizeof(struct pcie_dpu_ep), GFP_KERNEL, node);
+	if (!zf_ep->dpu_ep_array[id]) {
+		DH_LOG_ERR(MODULE_MPF, "Error kzalloc node\n");
+		ret = -ENOMEM;
+		goto free_epc_mem;
+	}
+
+	zf_ep->dpu_ep_array[id]->ep_id = id;
+	zf_ep->dpu_ep_array[id]->epc = epc;
+	zf_ep->dpu_ep_array[id]->dbi_base =
+			zf_ep->dbi_vaddr + PCIE_DPU_EP_DBI_SIZE * id;
+	zf_ep->dpu_ep_array[id]->atu_base =
+			zf_ep->dpu_ep_array[id]->dbi_base + DEFAULT_DBI_ATU_OFFSET;
+	zf_ep->dpu_ep_array[id]->zf_pdev = zf_pdev;
+	zf_ep->dpu_ep_array[id]->zf_pdev_dma = zf_pdev_dma;
+
+	dpu_ep_default_set(id);
+
+	epc_set_drvdata(epc, zf_ep->dpu_ep_array[id]);
+
+	dpu_ep_get_permissible_pf(id);
+	for (i = 0; i < PCIE_DPU_PF_NUMS; i++) {
+		if (!(zf_ep->dpu_ep_array[id]->permissible_pf_map & (0x1 << i))) {
+			DH_LOG_INFO(MODULE_MPF, "ep%d pf%d can't uesd\n", id, i);
+			set_bit(i, &epc->function_num_map);
+		}
+	}
+
+	ret |= dpu_ep_iatu_init(&pdev->dev, id);
+	ret |= dpu_ep_vf_total_num_get(id);
+	ret |= dpu_ep_func_list_init(&pdev->dev, id);
+
+	if (ret)
+		goto free_dpu_ep;
+
+	return 0;
 
 free_dpu_ep:
-    kfree(zf_ep->dpu_ep_array[id]);
+	kfree(zf_ep->dpu_ep_array[id]);
 free_epc_mem:
-    pci_epc_mem_exit(epc);
+	pci_epc_mem_exit(epc);
 free_epc:
-    pci_epc_destroy(epc);
+	pci_epc_destroy(epc);
 free_pdev:
-    platform_device_unregister(zf_pdev);
-    platform_device_unregister(zf_pdev_dma);
-    return ret;
+	platform_device_unregister(zf_pdev);
+	platform_device_unregister(zf_pdev_dma);
+	return ret;
 }
 
 static void pci_zte_epc_dev_free_one(struct pci_dev *pdev, int id)
 {
-    pcie_zf_dma_free(zf_ep->dpu_ep_array[id], pdev);
-    pci_epc_destroy(zf_ep->dpu_ep_array[id]->epc);
-    zf_ep->dpu_ep_array[id]->zf_pdev->dev.driver = NULL;
-    zf_ep->dpu_ep_array[id]->zf_pdev_dma->dev.driver = NULL;
-    platform_device_unregister(zf_ep->dpu_ep_array[id]->zf_pdev);
-    platform_device_unregister(zf_ep->dpu_ep_array[id]->zf_pdev_dma);
-    kfree(zf_ep->dpu_ep_array[id]);
+	pcie_zf_dma_free(zf_ep->dpu_ep_array[id], pdev);
+	pci_epc_destroy(zf_ep->dpu_ep_array[id]->epc);
+	zf_ep->dpu_ep_array[id]->zf_pdev->dev.driver = NULL;
+	zf_ep->dpu_ep_array[id]->zf_pdev_dma->dev.driver = NULL;
+	platform_device_unregister(zf_ep->dpu_ep_array[id]->zf_pdev);
+	platform_device_unregister(zf_ep->dpu_ep_array[id]->zf_pdev_dma);
+	kfree(zf_ep->dpu_ep_array[id]);
 }
 
 static int zf_dev_map(struct pci_dev *pdev)
 {
-    zf_ep->dbi_vaddr = ioremap(zf_ep->dbi_paddr, PCIE_DPU_EP_DBI_SIZE * PCIE_DPU_EP_NUM);
-    if (!zf_ep->dbi_vaddr)
-    {
-        pci_release_mem_regions(pdev);
-        return -ENODEV;
-    }
+	zf_ep->dbi_vaddr =
+			ioremap(zf_ep->dbi_paddr, PCIE_DPU_EP_DBI_SIZE * PCIE_DPU_EP_NUM);
+	if (!zf_ep->dbi_vaddr) {
+		pci_release_mem_regions(pdev);
+		return -ENODEV;
+	}
 
-    zf_ep->mpf_vaddr = ioremap(zf_ep->mpf_paddr, pci_resource_len(pdev, BAR_0));
-    if (!zf_ep->mpf_vaddr)
-    {
-        iounmap(zf_ep->dbi_vaddr);
-        pci_release_mem_regions(pdev);
-        return -ENODEV;
-    }
+	zf_ep->mpf_vaddr = ioremap(zf_ep->mpf_paddr, pci_resource_len(pdev, BAR_0));
+	if (!zf_ep->mpf_vaddr) {
+		iounmap(zf_ep->dbi_vaddr);
+		pci_release_mem_regions(pdev);
+		return -ENODEV;
+	}
 
-    return 0;
+	return 0;
 }
 
 static void zf_dev_unmap(struct pci_dev *pdev)
 {
-    if (zf_ep->dbi_vaddr)
-        iounmap(zf_ep->dbi_vaddr);
-    if (zf_ep->mpf_vaddr)
-        iounmap(zf_ep->mpf_vaddr);
-    pci_release_mem_regions(pdev);
+	if (zf_ep->dbi_vaddr)
+		iounmap(zf_ep->dbi_vaddr);
+	if (zf_ep->mpf_vaddr)
+		iounmap(zf_ep->mpf_vaddr);
+	pci_release_mem_regions(pdev);
 }
 
 static int pci_zte_epc_dev_init(struct pci_dev *pdev, int num)
 {
-    int i = 0, j = 0, ret = 0;
-
-    for (i = 0; i < num; i++)
-    {
-        ret = pci_zte_epc_dev_init_one(pdev, i);
-        if (zf_ep->dpu_ep_array[i] == NULL)
-        {
-            DH_LOG_ERR(MODULE_MPF, "pci_zte_epc_dev_init_one failed\n");
-            for (j = 0; j < i; j++)
-            {
-                pci_zte_epc_dev_free_one(pdev, j);
-            }
-            return -ENODEV;
-        }
-        DH_LOG_INFO(MODULE_MPF, "pci_zte_epc_dev_init_ep%d success!\n", i);
-
-        ret = pcie_zf_dma_init(zf_ep->dpu_ep_array[i], pdev);
-        if (ret)
-        {
-            DH_LOG_ERR(MODULE_MPF, "pcie_zf_dma_init failed\n");
-            return ret;
-        }
-    }
-
-    return ret;
-}
-
-int pcie_zte_zf_epc_init(struct dh_core_dev *dh_dev, const struct pci_device_id *id)
-{
-    int ret = -ENXIO;
-    u32 val = 0;
-
-    dh_dev->zf_ep = (struct pcie_zf_ep *)kzalloc(sizeof(struct pcie_zf_ep), GFP_KERNEL);
-    if (!dh_dev->zf_ep)
-    {
-        DH_LOG_ERR(MODULE_MPF, "kzalloc zf_ep err\n");
-        return -ENODEV;
-    }
-    zf_ep = dh_dev->zf_ep;
-
-    dh_dev->zf_ep->dpu_ep_array = kzalloc(PCIE_DPU_EP_NUM * sizeof(struct pcie_dpu_ep *), GFP_KERNEL);
-    if (!dh_dev->zf_ep->dpu_ep_array)
-    {
-        DH_LOG_ERR(MODULE_MPF, "kzalloc dpu_ep_array err\n");
-        ret = -ENODEV;
-        goto free_zf_ep;
-    }
-
-    dh_dev->zf_ep->dbi_paddr = pci_resource_start(dh_dev->pdev, BAR_2);
-    dh_dev->zf_ep->mpf_paddr = pci_resource_start(dh_dev->pdev, BAR_0);
-    dh_dev->zf_ep->ob_size = pci_resource_len(dh_dev->pdev, BAR_0) >> EP_ID_LEN;
-    dh_dev->zf_ep->dpu_ep_num = PCIE_DPU_EP_NUM;
-    ret = zf_dev_map(dh_dev->pdev);
-    if (ret)
-    {
-        DH_LOG_ERR(MODULE_MPF, "zf_dev_map err\n");
-        goto free_dpu_ep_array;
-    }
-
-    pcie_zf_read(dh_dev->zf_ep->dbi_vaddr, 4, &val);
-    if (val == 0x0 || val == 0xffffffff)
-    {
-        DH_LOG_ERR(MODULE_MPF, "the dbi_addr is err!\n");
-        ret = -EINVAL;
-        goto free_dpu_ep_array;
-    }
-
-    ret = pci_zte_epc_dev_init(dh_dev->pdev, PCIE_DPU_EP_NUM);
-    if (ret)
-    {
-        goto unmap;
-    }
-
-    DH_LOG_INFO(MODULE_MPF, "INFO:the EP0~3 pci_dev created successed!\n");
-    return ret;
+	int i = 0, j = 0, ret = 0;
+
+	for (i = 0; i < num; i++) {
+		ret = pci_zte_epc_dev_init_one(pdev, i);
+		if (zf_ep->dpu_ep_array[i] == NULL) {
+			DH_LOG_ERR(MODULE_MPF, "pci_zte_epc_dev_init_one failed\n");
+			for (j = 0; j < i; j++) {
+				pci_zte_epc_dev_free_one(pdev, j);
+			}
+			return -ENODEV;
+		}
+		DH_LOG_INFO(MODULE_MPF, "pci_zte_epc_dev_init_ep%d success!\n", i);
+
+		ret = pcie_zf_dma_init(zf_ep->dpu_ep_array[i], pdev);
+		if (ret) {
+			DH_LOG_ERR(MODULE_MPF, "pcie_zf_dma_init failed\n");
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+int pcie_zte_zf_epc_init(struct dh_core_dev *dh_dev,
+						 const struct pci_device_id *id)
+{
+	int val = 0, ret = -ENXIO;
+
+	dh_dev->zf_ep = kzalloc(sizeof(struct pcie_zf_ep *), GFP_KERNEL);
+	if (!dh_dev->zf_ep) {
+		DH_LOG_ERR(MODULE_MPF, "kzalloc zf_ep err\n");
+		return -ENODEV;
+	}
+	zf_ep = dh_dev->zf_ep;
+
+	dh_dev->zf_ep->dpu_ep_array =
+			kzalloc(PCIE_DPU_EP_NUM * sizeof(struct pcie_dpu_ep *), GFP_KERNEL);
+	if (!dh_dev->zf_ep->dpu_ep_array) {
+		DH_LOG_ERR(MODULE_MPF, "kzalloc dpu_ep_array err\n");
+		ret = -ENODEV;
+		goto free_zf_ep;
+	}
+
+	dh_dev->zf_ep->dbi_paddr = pci_resource_start(dh_dev->pdev, BAR_2);
+	dh_dev->zf_ep->mpf_paddr = pci_resource_start(dh_dev->pdev, BAR_0);
+	dh_dev->zf_ep->ob_size = pci_resource_len(dh_dev->pdev, BAR_0) >> EP_ID_LEN;
+	dh_dev->zf_ep->dpu_ep_num = PCIE_DPU_EP_NUM;
+	ret = zf_dev_map(dh_dev->pdev);
+	if (ret) {
+		DH_LOG_ERR(MODULE_MPF, "zf_dev_map err\n");
+		goto free_dpu_ep_array;
+	}
+
+	pcie_zf_read(dh_dev->zf_ep->dbi_vaddr, 4, &val);
+	if (val == 0x0 || val == 0xffffffff) {
+		DH_LOG_ERR(MODULE_MPF, "the dbi_addr is err!\n");
+		return -1;
+	}
+
+	ret = pci_zte_epc_dev_init(dh_dev->pdev, PCIE_DPU_EP_NUM);
+	if (ret) {
+		goto unmap;
+	}
+
+	DH_LOG_INFO(MODULE_MPF, "INFO:the EP0~3 pci_dev created successed!\n");
+	return ret;
 
 unmap:
-    zf_dev_unmap(dh_dev->pdev);
+	zf_dev_unmap(dh_dev->pdev);
 free_dpu_ep_array:
-    kfree(dh_dev->zf_ep->dpu_ep_array);
+	kfree(dh_dev->zf_ep->dpu_ep_array);
 free_zf_ep:
-    kfree(dh_dev->zf_ep);
-    return ret;
+	kfree(dh_dev->zf_ep);
+	return ret;
 }
 
 void pcie_zte_zf_epc_free(struct dh_core_dev *dh_dev)
 {
-    int ep_id = 0;
+	int ep_id = 0;
 
-    DH_LOG_INFO(MODULE_MPF, "INFO===>TODO:removed can't finish!\n");
+	DH_LOG_INFO(MODULE_MPF, "INFO===>TODO:removed can't finish!\n");
 
-    zf_dev_unmap(dh_dev->pdev);
-    for (ep_id = 0; ep_id < PCIE_DPU_EP_NUM; ep_id++)
-    {
-        pci_zte_epc_dev_free_one(dh_dev->pdev, ep_id);
-    }
-    kfree(dh_dev->zf_ep->dpu_ep_array);
-    kfree(dh_dev->zf_ep);
-    DH_LOG_INFO(MODULE_MPF, "the EP0~3 pci_dev removed successed!\n");
+	zf_dev_unmap(dh_dev->pdev);
+	for (ep_id = 0; ep_id < PCIE_DPU_EP_NUM; ep_id++) {
+		pci_zte_epc_dev_free_one(dh_dev->pdev, ep_id);
+	}
+	kfree(dh_dev->zf_ep->dpu_ep_array);
+	kfree(dh_dev->zf_ep);
+	DH_LOG_INFO(MODULE_MPF, "the EP0~3 pci_dev removed successed!\n");
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-epc.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-epc.h
index c275c1b3c4e230aa69f3c3c03ef39dac09c84b8e..a81456a3347db9dbb07344ae28a19648d50b5058 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-epc.h
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-epc.h
@@ -20,222 +20,225 @@
 #include <linux/platform_device.h>
 #include <linux/t10-pi.h>
 #include <linux/dinghai/log.h>
-#include <linux/spinlock.h>
 
 #ifdef _cplusplus
 extern "C" {
 #endif
 
-#define ZF_DISABLE                              0x0
-#define ZF_ENABLE                               0x1
+#define ZF_DISABLE 0x0
+#define ZF_ENABLE 0x1
 
 // ZF INFO
-#define PCI_VENDOR_ID_ZTE                       0x1cf2
-#define PCIE_DPU_EP_CLASS_NAME                  32
-
-#define PCIE_DPU_EP_NUM                         4
-#define EP_ID_LEN                               4
-#define PCIE_DPU_PF_NUMS                        8
-#define PCIE_DPU_IATU_NUM                       41
-#define PCIE_VF_BARS_OFF                        7
-#define PCIE_BAR0_ADDR_SET(off)                 (((off) & 0xFFFF) | (((off) & 0xFFFFFFFFFFFF0000) << EP_ID_LEN))
-
-#define PCIE_DPU_PF_INITIAL_ID                  0x000016c3
-#define PCIE_DPU_PF_DEFAUTL_ID1                 0x10011af4
-#define PCIE_DPU_PF_DEFAUTL_ID2                 0x80531cf2
-#define PCIE_DPU_PF_DEFAUTL_ID3                 0x000016c3
-#define PCIE_DPU_PF_DEFAUTL_ID4                 0x80331cf2
-#define PCIE_DPU_PF_DEFAUTL_CLASSCODE           0x02000000
+#define PCI_VENDOR_ID_ZTE 0x1cf2
+#define PCIE_DPU_EP_CLASS_NAME 18
+
+#define PCIE_DPU_EP_NUM 4
+#define EP_ID_LEN 4
+#define PCIE_DPU_PF_NUMS 8
+#define PCIE_DPU_IATU_NUM 41
+#define PCIE_VF_BARS_OFF 7
+#define PCIE_BAR0_ADDR_SET(off) \
+	(((off)&0xFFFF) | (((off)&0xFFFFFFFFFFFF0000) << EP_ID_LEN))
+
+#define PCIE_DPU_PF_DEFAUTL_ID0 0x000016c3
+#define PCIE_DPU_PF_DEFAUTL_ID1 0x10011af4
+#define PCIE_DPU_PF_DEFAUTL_ID2 0x80531cf2
+#define PCIE_DPU_PF_DEFAUTL_ID3 0x80c01957
+#define PCIE_DPU_PF_DEFAUTL_ID4 0x80331cf2
+#define PCIE_DPU_PF_DEFAUTL_CLASSCODE 0x02000000
 
 // dpu func_no&addr set
-#define PCIE_DPU_EP_FUNC_IS_VF                  BIT(7)
-#define PCIE_DPU_EP_GET_PF_NO                   0x7f
-#define DBI_VF_CFG_OFFSET_BIT                   4
-#define VF_ACT_BIT                              BIT(3)
-#define isPF(func_no)                           ((func_no & PCIE_DPU_EP_FUNC_IS_VF) ? 0 : 1)
-
-#define ZF_PREFIX_ADDR                          0x9000000000000000
-#define DEFAULT_DBI_ATU_OFFSET                  0x6000000
-#define PCIE_DPU_EP_DBI_SIZE                    0x8000000
-#define PCIE_DPU_EP_OUTBOUND_SIZE               0x40000000
-#define PCIE_DPU_EP_DBI2_OFFSET                 0x2000000
-#define PCIE_DPU_MPF_CSR_OFFSET                 0x14000
-#define PCIE_DPU_MPF_CSR_ADDR(offset)           PCIE_BAR0_ADDR_SET(PCIE_DPU_MPF_CSR_OFFSET + offset)
-#define PCIE_DPU_EP_FUNC_CFG_SIZE               0X1000
-#define PCIE_DPU_EP_CSR_SIZE                    0x2000
-#define PCIE_DPU_EP_CSR_PRST_ADDR               0x448
-#define PCIE_DPU_EP_CSR_VIRT_ADDR               0x1200
-#define BAR4_DEFAULT_SIZE                       0x10000
+#define PCIE_DPU_EP_FUNC_IS_VF BIT(7)
+#define PCIE_DPU_EP_GET_PF_NO 0x7f
+#define DBI_VF_CFG_OFFSET_BIT 4
+#define VF_ACT_BIT BIT(3)
+#define isPF(func_no) ((func_no & PCIE_DPU_EP_FUNC_IS_VF) ? 0 : 1)
+
+#define ZF_PREFIX_ADDR 0x9000000000000000
+#define DEFAULT_DBI_ATU_OFFSET 0x6000000
+#define PCIE_DPU_EP_DBI_SIZE 0x8000000
+#define PCIE_DPU_EP_OUTBOUND_SIZE 0x40000000
+#define PCIE_DPU_EP_DBI2_OFFSET 0x2000000
+#define PCIE_DPU_MPF_CSR_OFFSET 0x14000
+#define PCIE_DPU_MPF_CSR_ADDR(offset) \
+	PCIE_BAR0_ADDR_SET(PCIE_DPU_MPF_CSR_OFFSET + offset)
+#define PCIE_DPU_EP_FUNC_CFG_SIZE 0X1000
+#define PCIE_DPU_EP_CSR_SIZE 0x2000
+#define PCIE_DPU_EP_CSR_PRST_ADDR 0x448
+#define PCIE_DPU_EP_CSR_VIRT_ADDR 0x1200
+#define BAR4_DEFAULT_SIZE 0x10000
 
 // epc features
-#define PCIE_DPU_EP_REAERVED_BAR                0x30
-#define PCIE_DPU_EP_BAR_FIXED_64BIT             0x15
-#define PCIE_DPU_EP_ALIGN                       0x1000
-
-#define EP_ID_SHIFT                             16
-#define EP_ADDR_MASK                            ((1 << EP_ID_SHIFT) - 1)
-#define EP_DPU_PA(addr, ep_id)                                             \
-	((addr & ~EP_ADDR_MASK) << EP_ID_LEN | (addr & EP_ADDR_MASK) |         \
+#define PCIE_DPU_EP_REAERVED_BAR 0x30
+#define PCIE_DPU_EP_BAR_FIXED_64BIT 0x15
+#define PCIE_DPU_EP_ALIGN 0x1000
+
+#define EP_ID_SHIFT 16
+#define EP_ADDR_MASK ((1 << EP_ID_SHIFT) - 1)
+#define EP_DPU_PA(addr, ep_id)                                     \
+	((addr & ~EP_ADDR_MASK) << EP_ID_LEN | (addr & EP_ADDR_MASK) | \
 	 ep_id << EP_ID_SHIFT)
 
 // PCIE Register
 #if 1
-#define LINK_WAIT_MAX_RETRIES                    10
-#define LINK_WAIT_USLEEP_MIN                     90000
-#define LINK_WAIT_USLEEP_MAX                     100000
-#define LINK_WAIT_MAX_IATU_RETRIES               0x10
-#define LINK_WAIT_IATU                           10
+#define LINK_WAIT_MAX_RETRIES 10
+#define LINK_WAIT_USLEEP_MIN 90000
+#define LINK_WAIT_USLEEP_MAX 100000
+#define LINK_WAIT_MAX_IATU_RETRIES 0x10
+#define LINK_WAIT_IATU 10
 
 // PCIE_PORT_DEBUG1 cap
-#define PCIE_PORT_DEBUG1                         0x72C
-#define PCIE_PORT_DEBUG1_ZTE_ZF_LINK_UP          BIT(4)
-#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING        BIT(29)
+#define PCIE_PORT_DEBUG1 0x72C
+#define PCIE_PORT_DEBUG1_ZTE_ZF_LINK_UP BIT(4)
+#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29)
 
 // PCIE CAP
-#define PCIE_ECAP_POINTER_OFF                    0x100
-#define PCIE_ECAP_VSEC_ID                        0x0B
-
-#define PCIE_NEXT_BAR_OFFSET                     0x4
-#define PCIE_DEFAULT_BAR_FLAG                    (BIT(3) | BIT(2))
-#define PCIE_SRIOV_ECAP_DEVICE_ID                0x1a
-#define PCIE_SRIOV_ECAP_BAR0_OFFSET              0x24
-#define PCIE_SRIOV_ECAP_BAR4_OFFSET              0x34
-#define PCIE_SRIOV_CTRL                          0x08
-#define PCIE_SRIOV_TOTAL_VFS                     0x0e
-#define PCIE_SRIOV_CTRL_VFE                      0x01
-
-#define PCIE_MSI_ADDR_LO                         0x820
-#define PCIE_MSI_ADDR_HI                         0x824
-#define PCIE_MSI_INTR0_ENABLE                    0x828
-#define PCIE_MSI_INTR0_MASK                      0x82C
-#define PCIE_MSI_INTR0_STATUS                    0x830
-
-#define PCIE_PORT_MULTI_LANE_CTRL                0x8C0
-#define PORT_MLTI_UPCFG_SUPPORT                  BIT(7)
+#define PCIE_ECAP_POINTER_OFF 0x100
+#define PCIE_ECAP_VSEC_ID 0x0B
+
+#define PCIE_NEXT_BAR_OFFSET 0x4
+#define PCIE_DEFAULT_BAR_FLAG (BIT(3) | BIT(2))
+#define PCIE_SRIOV_ECAP_DEVICE_ID 0x1a
+#define PCIE_SRIOV_ECAP_BAR0_OFFSET 0x24
+#define PCIE_SRIOV_ECAP_BAR4_OFFSET 0x34
+#define PCIE_SRIOV_CTRL 0x08
+#define PCIE_SRIOV_TOTAL_VFS 0x0e
+#define PCIE_SRIOV_CTRL_VFE 0x01
+
+#define PCIE_MSI_ADDR_LO 0x820
+#define PCIE_MSI_ADDR_HI 0x824
+#define PCIE_MSI_INTR0_ENABLE 0x828
+#define PCIE_MSI_INTR0_MASK 0x82C
+#define PCIE_MSI_INTR0_STATUS 0x830
+
+#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0
+#define PORT_MLTI_UPCFG_SUPPORT BIT(7)
 
 /* ATU register*/
-#define PCIE_ATU_CR1                             0x904
-#define PCIE_ATU_TYPE_MEM                        0x0
-#define PCIE_ATU_TYPE_IO                         0x2
-#define PCIE_ATU_FUNC_NUM(pf)                    ((pf) << 20)
-#define PCIE_ATU_FUNC_NUM_MASK                   0xF00000
-#define PCIE_ATU_BAR_NUM_MASK                    0x700
-#define PCIE_ATU_ENABLE                          BIT(31)
-#define PCIE_ATU_BAR_MODE_ENABLE                 BIT(30)
-#define PCIE_ATU_CFG_SHIFT_MODE                  BIT(28)
-#define PCIE_ATU_DMA_BYPSS                       BIT(27)
-#define PCIE_ATU_FUNC_NUM_MATCH_EN               BIT(19)
-#define PCIE_ATU_VFBAR_MATCH_MODE_ENABLE         BIT(26)
-#define PCIE_ATU_VF_MATCH_ENABLE                 BIT(20)
-#define PCIE_ATU_OB_VF_ACTIVE                    BIT(31)
+#define PCIE_ATU_CR1 0x904
+#define PCIE_ATU_TYPE_MEM 0x0
+#define PCIE_ATU_TYPE_IO 0x2
+#define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
+#define PCIE_ATU_FUNC_NUM_MASK 0xF00000
+#define PCIE_ATU_BAR_NUM_MASK 0x700
+#define PCIE_ATU_ENABLE BIT(31)
+#define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
+#define PCIE_ATU_CFG_SHIFT_MODE BIT(28)
+#define PCIE_ATU_DMA_BYPSS BIT(27)
+#define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
+#define PCIE_ATU_VFBAR_MATCH_MODE_ENABLE BIT(26)
+#define PCIE_ATU_VF_MATCH_ENABLE BIT(20)
+#define PCIE_ATU_OB_VF_ACTIVE BIT(31)
 
 /*MSIX register*/
-#define MSIX_ADDRESS_MATCH_LOW_OFF               0x940
-#define MSI_ADDRESS_MATCH_EN                     BIT(0)
-#define MSIX_ADDRESS_MATCH_HIGH_OFF              0x944
-#define MSIX_DOORBELL_OFF                        0x948
-#define MSIX_DOORBELL_PF                         24
-#define MSIX_DOORBELL_PF_MASK                    0x1F
-#define MSIX_DOORBELL_VF                         16
-#define MSIX_DOORBELL_VF_MASK                    0xFF
-#define MSIX_DOORBELL_VF_ACTIVE                  BIT(15)
-#define MSIX_DOORBELL_VECTOR                     0
-#define MSIX_DOORBELL_VECTOR_MASK                0x7FF
-
-#define LINK_WAIT_DMA                            20
-
-#define PCIE_MISC_CONTROL_1_OFF                  0x8BC
-#define PCIE_DBI_RO_WR_EN                        BIT(0)
-
-#define PCIE_MSIX_DOORBELL                       0x948
-#define PCIE_MSIX_DOORBELL_PF_SHIFT              24
-#define PCIE_MSIX_DOORBELL_VF_SHIFT              16
-#define MSIX_DOORBELL_VF_ACTIVE                  BIT(15)
+#define MSIX_ADDRESS_MATCH_LOW_OFF 0x940
+#define MSI_ADDRESS_MATCH_EN BIT(0)
+#define MSIX_ADDRESS_MATCH_HIGH_OFF 0x944
+#define MSIX_DOORBELL_OFF 0x948
+#define MSIX_DOORBELL_PF 24
+#define MSIX_DOORBELL_PF_MASK 0x1F
+#define MSIX_DOORBELL_VF 16
+#define MSIX_DOORBELL_VF_MASK 0xFF
+#define MSIX_DOORBELL_VF_ACTIVE BIT(15)
+#define MSIX_DOORBELL_VECTOR 0
+#define MSIX_DOORBELL_VECTOR_MASK 0x7FF
+
+#define LINK_WAIT_DMA 20
+
+#define PCIE_MISC_CONTROL_1_OFF 0x8BC
+#define PCIE_DBI_RO_WR_EN BIT(0)
+
+#define PCIE_MSIX_DOORBELL 0x948
+#define PCIE_MSIX_DOORBELL_PF_SHIFT 24
+#define PCIE_MSIX_DOORBELL_VF_SHIFT 16
+#define MSIX_DOORBELL_VF_ACTIVE BIT(15)
 
 /* Register address builder */
 #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9)
-#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region)  (((region) << 9) | BIT(8))
-
-#define PCIE_ATU_UNR_REGION_CTRL1                0x00
-#define PCIE_ATU_UNR_REGION_CTRL2                0x04
-#define PCIE_ATU_UNR_LOWER_BASE                  0x08
-#define PCIE_ATU_UNR_UPPER_BASE                  0x0C
-#define PCIE_ATU_UNR_LOWER_LIMIT                 0x10
-#define PCIE_ATU_UNR_LOWER_TARGET                0x14
-#define PCIE_ATU_UNR_UPPER_TARGET                0x18
-#define PCIE_ATU_UNR_REGION_CTRL3                0x1c
-#define PCIE_ATU_UNR_UPPER_LIMIT                 0x20
-#define PCIE_ATU_INCREASE_REGION_SIZE            BIT(13)
+#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) (((region) << 9) | BIT(8))
+
+#define PCIE_ATU_UNR_REGION_CTRL1 0x00
+#define PCIE_ATU_UNR_REGION_CTRL2 0x04
+#define PCIE_ATU_UNR_LOWER_BASE 0x08
+#define PCIE_ATU_UNR_UPPER_BASE 0x0C
+#define PCIE_ATU_UNR_LOWER_LIMIT 0x10
+#define PCIE_ATU_UNR_LOWER_TARGET 0x14
+#define PCIE_ATU_UNR_UPPER_TARGET 0x18
+#define PCIE_ATU_UNR_REGION_CTRL3 0x1c
+#define PCIE_ATU_UNR_UPPER_LIMIT 0x20
+#define PCIE_ATU_INCREASE_REGION_SIZE BIT(13)
 
 #endif
 
 enum pcie_dpu_func_type {
-    PCIE_FUNC_TYPE_PF = 0,
-    PCIE_FUNC_TYPE_VF,
-    PCIE_FUNC_TYPE_NUM
+	PCIE_FUNC_TYPE_PF = 0,
+	PCIE_FUNC_TYPE_VF,
+	PCIE_FUNC_TYPE_NUM
 };
 
 enum pcie_dpu_as_type {
-    PCIE_DPU_AS_UNKNOWN,
-    PCIE_DPU_AS_MEM,
-    PCIE_DPU_AS_IO,
+	PCIE_DPU_AS_UNKNOWN,
+	PCIE_DPU_AS_MEM,
+	PCIE_DPU_AS_IO,
 };
 
 enum pcie_dpu_region_type {
-    PCIE_DPU_REGION_UNKNOWN,
-    PCIE_DPU_REGION_INBOUND,
-    PCIE_DPU_REGION_OUTBOUND,
+	PCIE_DPU_REGION_UNKNOWN,
+	PCIE_DPU_REGION_INBOUND,
+	PCIE_DPU_REGION_OUTBOUND,
 };
 
 struct pcie_dpu_ep_func {
-    struct list_head list;
-    u8 func_no;
-    u8 vfunc_no;
-    u8 msi_cap;  /* MSI capability offset */
-    u8 msix_cap; /* MSI-X capability offset */
+	struct list_head list;
+	u8 func_no;
+	u8 vfunc_no;
+	u8 msi_cap; /* MSI capability offset */
+	u8 msix_cap; /* MSI-X capability offset */
 };
 
 struct pcie_dpu_ep {
-    int ep_id;
-    int permissible_pf_map;
-    struct pci_epc *epc;
-    struct platform_device *zf_pdev;
-    struct platform_device *zf_pdev_dma;
-    struct dma_device *wr_dd;
-    struct dma_device *rd_dd;
-
-    void __iomem *dbi_base;
-    void __iomem *atu_base;
-
-    struct list_head func_list;
-    int bar_to_atu[PCIE_DPU_PF_NUMS][(PCI_STD_NUM_BARS * 2) + 1];
-    int vf_total_num[PCIE_DPU_PF_NUMS];
-    phys_addr_t *ob_src_addr;
-    unsigned long *ib_window_map;
-    unsigned long *ob_window_map;
-    spinlock_t ib_window_lock;
-    u32 num_ib_windows;
-    u32 num_ob_windows;
+	int ep_id;
+	int permissible_pf_map;
+	struct pci_epc *epc;
+	struct platform_device *zf_pdev;
+	struct platform_device *zf_pdev_dma;
+	struct dma_device *wr_dd;
+	struct dma_device *rd_dd;
+
+	void __iomem *dbi_base;
+	void __iomem *atu_base;
+
+	struct list_head func_list;
+	int bar_to_atu[PCI_STD_NUM_BARS * 2 + 1];
+	int vf_total_num[PCIE_DPU_PF_NUMS];
+	phys_addr_t *ob_src_addr;
+	unsigned long *ib_window_map;
+	unsigned long *ob_window_map;
+	u32 num_ib_windows;
+	u32 num_ob_windows;
 };
 
 struct pcie_zf_ep {
-    unsigned long dbi_paddr;
-    unsigned long mpf_paddr;
-    unsigned long ob_size;
-    void __iomem *dbi_vaddr;
-    void __iomem *mpf_vaddr;
-    int dpu_ep_num;
-    struct pcie_dpu_ep **dpu_ep_array;
-    struct device_driver *dma_driver;
+	unsigned long dbi_paddr;
+	unsigned long mpf_paddr;
+	unsigned long ob_size;
+	void __iomem *dbi_vaddr;
+	void __iomem *mpf_vaddr;
+	int dpu_ep_num;
+	struct pcie_dpu_ep **dpu_ep_array;
+	struct device_driver *dma_driver;
 };
 
-int pcie_zte_zf_epc_init(struct dh_core_dev *dh_dev, const struct pci_device_id *id);
+int pcie_zte_zf_epc_init(struct dh_core_dev *dh_dev,
+						 const struct pci_device_id *id);
 int pcie_zf_dma_init(struct pcie_dpu_ep *dpu_dev, struct pci_dev *pdev);
 void pcie_zte_zf_epc_free(struct dh_core_dev *dh_dev);
 void pcie_zf_dma_free(struct pcie_dpu_ep *dpu_dev, struct pci_dev *pdev);
-int zf_pcie_get_hdma_chan(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct dma_chan **rchan, struct dma_chan **wchan);
+int zf_pcie_get_hdma_chan(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
+						  struct dma_chan **rchan, struct dma_chan **wchan);
 u32 cfg_phy_rmw(u64 phy_addr, u32 value, u32 mask);
-int pcie_zte_epc_ob_read(struct pci_epc *epc, phys_addr_t phys_addr, unsigned int size, unsigned int *val);
+int pcie_zte_epc_ob_read(struct pci_epc *epc, phys_addr_t phys_addr, int size,
+						 int *val);
 
 #ifdef __cplusplus
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-hdma.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-hdma.c
index 6ed82ddbe3bdc63034d0d50f36b7c378a3c65095..82b79e1774d2bfbbb0340b2dc492bd0f8bbb39a8 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-hdma.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-hdma.c
@@ -2,747 +2,718 @@
 
 static struct task_struct *callback_thread[PCIE_DPU_EP_NUM];
 
-static int __attribute__((unused)) cfg_phy_write(u32 value, u64 PhyAddr)
+static int cfg_phy_write(u32 value, u64 PhyAddr)
 {
-    void __iomem *virt_addr = NULL;
-    u64 tmp_addr = 0;
-    u64 offset = 0;
-    u64 size = 0;
-
-    offset = PhyAddr % 0x1000;
-    if (PhyAddr < offset)
-    {
-        DH_LOG_ERR(MODULE_MPF, "data overflow! PhyAddr=0x%llx, offset=0x%llx\n", PhyAddr, offset);
-        return PCIBIOS_BAD_REGISTER_NUMBER;
-    }
-    else
-    {
-        tmp_addr = PhyAddr - offset;
-    }
-
-    if (offset <= (0x1000 - 4))
-    {
-        size = 0x1000;
-    }
-    else
-    {
-        size = 2 * 0x1000;
-    }
-
-    virt_addr = ioremap(tmp_addr, size);
-    if (NULL == virt_addr)
-    {
-        DH_LOG_ERR(MODULE_MPF, "cfg_write ioremap failed!\n");
-        return PCIBIOS_BAD_REGISTER_NUMBER;
-    }
-
-    writel(value, (virt_addr + offset));
-
-    iounmap(virt_addr);
-    return 0;
+	void __iomem *virt_addr = NULL;
+	u64 tmp_addr = 0;
+	u64 offset = 0;
+	u64 size = 0;
+
+	offset = PhyAddr % 0x1000;
+	tmp_addr = PhyAddr - offset;
+	if (offset <= (0x1000 - 4)) {
+		size = 0x1000;
+	} else {
+		size = 2 * 0x1000;
+	}
+
+	virt_addr = ioremap(tmp_addr, size);
+	if (NULL == virt_addr) {
+		DH_LOG_ERR(MODULE_MPF, "cfg_write ioremap failed!\n");
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	}
+
+	writel(value, (virt_addr + offset));
+
+	iounmap(virt_addr);
+	return 0;
 }
 
 static inline struct zf_hdma_chan *to_zf_hdma_chan(struct dma_chan *chan)
 {
-    return container_of(chan, struct zf_hdma_chan, zxdh_vc.chan);
+	return container_of(chan, struct zf_hdma_chan, zxdh_vc.chan);
 }
 
 static u64 zte_pcie_dma_atu_addr_remapping(u64 addr_input)
 {
-    u64 addr_output = 0;
-    // DMA and ATU地址重映射，将地址的bit12~18左移4位，设置bit15 = 0
-    addr_output = (((addr_input & (0x7F << 12)) << 4) | (addr_input & 0xFFF)) & (~(1UL << 15));
+	u64 addr_output = 0;
+	// DMA and ATU地址重映射，将地址的bit12~18左移4位，设置bit15 = 0
+	addr_output = (((addr_input & (0x7F << 12)) << 4) | (addr_input & 0xFFF)) &
+				  (~(1 << 15));
 
-    return addr_output;
+	return addr_output;
 }
 
-static inline void read_ch(struct zf_hdma_chan *zf_chan, u32 is_read, int offset, u32 *val)
+static inline void read_ch(struct zf_hdma_chan *zf_chan, int is_read,
+						   int offset, u32 *val)
 {
-    u64 register_offet = 0;
+	int register_off = 0;
 
-    void __iomem *addr = zf_chan->base_addr;
+	void __iomem *addr = zf_chan->base_addr;
 
-    register_offet = zte_pcie_dma_atu_addr_remapping(((u64)zf_chan->id * (u64)ZF_HDMA_PER_CHANNEL_SIZE)) + ((u64)is_read * (u64)ZF_HDMA_RDCH_OFFSET);
-    *val = readl(addr + register_offet + offset);
+	register_off = zte_pcie_dma_atu_addr_remapping(zf_chan->id *
+												   ZF_HDMA_PER_CHANNEL_SIZE) +
+				   is_read * ZF_HDMA_RDCH_OFFSET;
+	*val = readl(addr + register_off + offset);
 }
 
-static inline void write_ch(struct zf_hdma_chan *zf_chan, u32 is_read, int offset, u32 val)
+static inline void write_ch(struct zf_hdma_chan *zf_chan, int is_read,
+							int offset, u32 val)
 {
-    u64 register_off = 0;
-    void __iomem *addr = zf_chan->base_addr;
+	int register_off = 0;
+	void __iomem *addr = zf_chan->base_addr;
 
-    register_off = zte_pcie_dma_atu_addr_remapping(((u64)zf_chan->id * (u64)ZF_HDMA_PER_CHANNEL_SIZE)) + ((u64)is_read * (u64)ZF_HDMA_RDCH_OFFSET);
-    writel(val, addr + register_off + offset);
+	register_off = zte_pcie_dma_atu_addr_remapping(zf_chan->id *
+												   ZF_HDMA_PER_CHANNEL_SIZE) +
+				   is_read * ZF_HDMA_RDCH_OFFSET;
+	writel(val, addr + register_off + offset);
 }
 
-static inline void rmw_ch(struct zf_hdma_chan *zf_chan, u32 is_read, int offset, u32 val, u32 mask)
+static inline void rmw_ch(struct zf_hdma_chan *zf_chan, int is_read, int offset,
+						  u32 val, u32 mask)
 {
-    u32 reg_val = 0;
+	int reg_val = 0;
 
-    read_ch(zf_chan, is_read, offset, &reg_val);
-    reg_val &= (~mask);
-    reg_val |= (val & mask);
-    write_ch(zf_chan, is_read, offset, reg_val);
+	read_ch(zf_chan, is_read, offset, &reg_val);
+	reg_val &= (~mask);
+	reg_val |= (val & mask);
+	write_ch(zf_chan, is_read, offset, reg_val);
 }
 
 static int zf_hdma_alloc_chan_resources(struct dma_chan *chan)
 {
-    u32 is_read = 0;
-    // struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan);
-
-    if (chan->device->directions == BIT(DMA_MEM_TO_DEV))
-    {
-        is_read = HDMA_RD;
-    }
-    else if (chan->device->directions == BIT(DMA_DEV_TO_MEM))
-    {
-        is_read = HDMA_WR;
-    }
-    else
-    {
-        DH_LOG_ERR(MODULE_MPF, "err direct\n");
-        return -EINVAL;
-    }
-
-    /* 开启dma通道中断 */
-    // rmw_ch(zf_chan, is_read, HDMA_INT_SETUP_OFF, 0x0 << HDMA_INT_MASK_BIT, HDMA_INT_MASK << HDMA_INT_MASK_BIT);
-    // rmw_ch(zf_chan, is_read, HDMA_INT_SETUP_OFF, 0x1 << HDMA_LSIE_BIT, HDMA_LSIE_MASK << HDMA_LSIE_BIT);
-
-    return 0;
+	int is_read = 0;
+	// struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan);
+
+	if (chan->device->directions == BIT(DMA_MEM_TO_DEV)) {
+		is_read = HDMA_RD;
+	} else if (chan->device->directions == BIT(DMA_DEV_TO_MEM)) {
+		is_read = HDMA_WR;
+	} else {
+		DH_LOG_ERR(MODULE_MPF, "err direct\n");
+		return -EINVAL;
+	}
+
+	/* 开启dma通道中断 */
+	// rmw_ch(zf_chan, is_read, HDMA_INT_SETUP_OFF, 0x0 << HDMA_INT_MASK_BIT,
+	// HDMA_INT_MASK << HDMA_INT_MASK_BIT); rmw_ch(zf_chan, is_read,
+	// HDMA_INT_SETUP_OFF, 0x1 << HDMA_LSIE_BIT, HDMA_LSIE_MASK << HDMA_LSIE_BIT);
+
+	return 0;
 }
 
 static void zf_hdma_free_chan_resources(struct dma_chan *chan)
 {
-    u32 is_read = 0;
-    // struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan);
-
-    if (chan->device->directions == BIT(DMA_MEM_TO_DEV))
-    {
-        is_read = HDMA_RD;
-    }
-    else if (chan->device->directions == BIT(DMA_DEV_TO_MEM))
-    {
-        is_read = HDMA_WR;
-    }
-    else
-    {
-        DH_LOG_ERR(MODULE_MPF, "err direct\n");
-        return;
-    }
-
-    /* 释放dma通道中断 */
-    // rmw_ch(zf_chan, is_read, HDMA_INT_SETUP_OFF, 0x7 << HDMA_INT_MASK_BIT, HDMA_INT_MASK << HDMA_INT_MASK_BIT);
-    // rmw_ch(zf_chan, is_read, HDMA_INT_SETUP_OFF, 0x0 << HDMA_LSIE_BIT, HDMA_LSIE_MASK << HDMA_LSIE_BIT);
+	int is_read = 0;
+	// struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan);
+
+	if (chan->device->directions == BIT(DMA_MEM_TO_DEV)) {
+		is_read = HDMA_RD;
+	} else if (chan->device->directions == BIT(DMA_DEV_TO_MEM)) {
+		is_read = HDMA_WR;
+	} else {
+		DH_LOG_ERR(MODULE_MPF, "err direct\n");
+		return;
+	}
+
+	/* 释放dma通道中断 */
+	// rmw_ch(zf_chan, is_read, HDMA_INT_SETUP_OFF, 0x7 << HDMA_INT_MASK_BIT,
+	// HDMA_INT_MASK << HDMA_INT_MASK_BIT); rmw_ch(zf_chan, is_read,
+	// HDMA_INT_SETUP_OFF, 0x0 << HDMA_LSIE_BIT, HDMA_LSIE_MASK << HDMA_LSIE_BIT);
 }
 
-static int zf_hdma_device_config(struct dma_chan *chan, struct dma_slave_config *config)
+static int zf_hdma_device_config(struct dma_chan *chan,
+								 struct dma_slave_config *config)
 {
-    // struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan);
-    // u32 is_read = HDMA_WR;
+	// struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan);
+	// int is_read = HDMA_WR;
 
-    return 0;
+	return 0;
 }
 
-static struct dma_async_tx_descriptor *zf_hdma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, size_t len, unsigned long flags)
+static struct dma_async_tx_descriptor *
+zf_hdma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
+						size_t len, unsigned long flags)
 {
-    u32 is_read = HDMA_WR;
-    struct zf_hdma_sqe *sqe = NULL, *tem_sqe = NULL;
-    struct zf_hdma_tx *tx = NULL, *tem_tx = NULL;
-    struct dma_async_tx_descriptor *tx_desc = NULL;
-    struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan);
-    int tx_num = 0;
-
-    DH_LOG_DEBUG(MODULE_MPF, "enter\n");
-    if (chan->device->directions == BIT(DMA_MEM_TO_DEV))
-    {
-        is_read = HDMA_RD;
-        dest |= ZF_PREFIX_ADDR;
-    }
-    else if (chan->device->directions == BIT(DMA_DEV_TO_MEM))
-    {
-        is_read = HDMA_WR;
-        src |= ZF_PREFIX_ADDR;
-    }
-    else
-    {
-        DH_LOG_ERR(MODULE_MPF, "err direct\n");
-        return NULL;
-    }
-
-    tem_sqe = zf_chan->sqe_list;
-    sqe = devm_kzalloc(&zf_chan->ep_pdev->dev, sizeof(struct zf_hdma_sqe), GFP_KERNEL);
-    if (!sqe)
-    {
-        DH_LOG_ERR(MODULE_MPF, "err alloc sqe\n");
-        return NULL;
-    }
-    sqe->length = len;
-    sqe->src_addr = src;
-    sqe->dst_addr = dest;
-
-    while (NULL != tem_sqe->next)
-    {
-        tem_sqe = tem_sqe->next;
-    }
-    tem_sqe->next = sqe;
-
-    tx_desc = zxdh_vchan_tx_prep(&zf_chan->zxdh_vc, &zf_chan->zxdh_vd, flags);
-    tem_tx = zf_chan->tx_list;
-    tx = devm_kzalloc(&zf_chan->ep_pdev->dev, sizeof(struct zf_hdma_tx), GFP_KERNEL);
-    if (!tx)
-    {
-        DH_LOG_ERR(MODULE_MPF, "err alloc tx\n");
-        devm_kfree(&zf_chan->ep_pdev->dev, sqe);
-        return NULL;
-    }
-    tx->tx_desc = tx_desc;
-
-    while (NULL != tem_tx->next)
-    {
-        tem_tx = tem_tx->next;
-        tx_num++;
-    }
-    tx->tx_id = tx_num;
-    tem_tx->next = tx;
-
-    return tx_desc;
+	int is_read = HDMA_WR;
+	struct zf_hdma_sqe *sqe = NULL, *tem_sqe = NULL;
+	struct zf_hdma_tx *tx = NULL, *tem_tx = NULL;
+	struct dma_async_tx_descriptor *tx_desc = NULL;
+	struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan);
+	int tx_num = 0;
+
+	DH_LOG_DEBUG(MODULE_MPF, "enter\n");
+	if (chan->device->directions == BIT(DMA_MEM_TO_DEV)) {
+		is_read = HDMA_RD;
+		dest |= ZF_PREFIX_ADDR;
+	} else if (chan->device->directions == BIT(DMA_DEV_TO_MEM)) {
+		is_read = HDMA_WR;
+		src |= ZF_PREFIX_ADDR;
+	} else {
+		DH_LOG_ERR(MODULE_MPF, "err direct\n");
+		return NULL;
+	}
+
+	tem_sqe = zf_chan->sqe_list;
+	sqe = devm_kzalloc(&zf_chan->ep_pdev->dev, sizeof(struct zf_hdma_sqe),
+					   GFP_KERNEL);
+	if (!sqe) {
+		DH_LOG_ERR(MODULE_MPF, "err alloc sqe\n");
+		return NULL;
+	}
+	sqe->length = len;
+	sqe->src_addr = src;
+	sqe->dst_addr = dest;
+
+	while (NULL != tem_sqe->next) {
+		tem_sqe = tem_sqe->next;
+	}
+	tem_sqe->next = sqe;
+
+	tx_desc = zxdh_vchan_tx_prep(&zf_chan->zxdh_vc, &zf_chan->zxdh_vd, flags);
+	tem_tx = zf_chan->tx_list;
+	tx = devm_kzalloc(&zf_chan->ep_pdev->dev, sizeof(struct zf_hdma_tx),
+					  GFP_KERNEL);
+	if (!tx) {
+		DH_LOG_ERR(MODULE_MPF, "err alloc tx\n");
+		devm_kfree(&zf_chan->ep_pdev->dev, sqe);
+		return NULL;
+	}
+	tx->tx_desc = tx_desc;
+
+	while (NULL != tem_tx->next) {
+		tem_tx = tem_tx->next;
+		tx_num++;
+	}
+	tx->tx_id = tx_num;
+	tem_tx->next = tx;
+
+	return tx_desc;
 }
 
 static int zf_hdma_terminate_all(struct dma_chan *chan)
 {
-    u32 is_read = HDMA_WR;
-    struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan);
+	int is_read = HDMA_WR;
+	struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan);
 
-    if (chan->device->directions == BIT(DMA_MEM_TO_DEV))
-    {
-        is_read = HDMA_RD;
-    }
+	if (chan->device->directions == BIT(DMA_MEM_TO_DEV)) {
+		is_read = HDMA_RD;
+	}
 
-    write_ch(zf_chan, is_read, HDMA_DOORBELL_OFF, HDMA_DOORBELL_STOP);
+	write_ch(zf_chan, is_read, HDMA_DOORBELL_OFF, HDMA_DOORBELL_STOP);
 
-    return 0;
+	return 0;
 }
 
-static enum dma_status zf_hdma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate)
+static enum dma_status zf_hdma_tx_status(struct dma_chan *chan,
+										 dma_cookie_t cookie,
+										 struct dma_tx_state *txstate)
 {
-    return 0;
+	return 0;
 }
 
-static struct dma_async_tx_descriptor *zf_hdma_device_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, unsigned int len, enum dma_transfer_direction direction, unsigned long flags, void *context)
+static struct dma_async_tx_descriptor *
+zf_hdma_device_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
+							 unsigned int len,
+							 enum dma_transfer_direction direction,
+							 unsigned long flags, void *context)
 {
-    struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan);
-    u32 is_read = HDMA_WR;
-
-    DH_LOG_INFO(MODULE_MPF, "enter\n");
-
-    if (chan->device->directions == BIT(DMA_MEM_TO_DEV))
-    {
-        is_read = HDMA_RD;
-    }
-    else if (chan->device->directions == BIT(DMA_DEV_TO_MEM))
-    {
-        is_read = HDMA_WR;
-    }
-    else
-    {
-        DH_LOG_ERR(MODULE_MPF, "err direct\n");
-        return NULL;
-    }
-
-    return zxdh_vchan_tx_prep(&zf_chan->zxdh_vc, &zf_chan->zxdh_vd, flags);
+	struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan);
+	int is_read = HDMA_WR;
+
+	DH_LOG_INFO(MODULE_MPF, "enter\n");
+
+	if (chan->device->directions == BIT(DMA_MEM_TO_DEV)) {
+		is_read = HDMA_RD;
+	} else if (chan->device->directions == BIT(DMA_DEV_TO_MEM)) {
+		is_read = HDMA_WR;
+	} else {
+		DH_LOG_ERR(MODULE_MPF, "err direct\n");
+		return NULL;
+	}
+
+	return zxdh_vchan_tx_prep(&zf_chan->zxdh_vc, &zf_chan->zxdh_vd, flags);
 }
 
-static struct dma_async_tx_descriptor *zf_hdma_device_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t paddr, size_t len, size_t count, enum dma_transfer_direction direction, unsigned long flags)
+static struct dma_async_tx_descriptor *zf_hdma_device_prep_dma_cyclic(
+		struct dma_chan *chan, dma_addr_t paddr, size_t len, size_t count,
+		enum dma_transfer_direction direction, unsigned long flags)
 {
-    struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan);
+	struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan);
 
-    return zxdh_vchan_tx_prep(&zf_chan->zxdh_vc, &zf_chan->zxdh_vd, flags);
+	return zxdh_vchan_tx_prep(&zf_chan->zxdh_vc, &zf_chan->zxdh_vd, flags);
 }
 
 static void free_used_sqe(struct zf_hdma_chan *zf_chan)
 {
-    struct zf_hdma_sqe *temp = NULL;
+	struct zf_hdma_sqe *temp = NULL;
 
-    temp = zf_chan->sqe_list->next;
-    zf_chan->sqe_list->next = zf_chan->sqe_list->next->next;
+	temp = zf_chan->sqe_list->next;
+	zf_chan->sqe_list->next = zf_chan->sqe_list->next->next;
 
-    devm_kfree(&zf_chan->ep_pdev->dev, temp);
+	devm_kfree(&zf_chan->ep_pdev->dev, temp);
 }
 
-static void zf_hdma_register_set(struct zf_hdma_chan *zf_chan, u32 is_read, struct zf_hdma_sqe *sqe)
+static void zf_hdma_register_set(struct zf_hdma_chan *zf_chan, int is_read,
+								 struct zf_hdma_sqe *sqe)
 {
-    /* DMA Engine enable */
-    write_ch(zf_chan, is_read, HDMA_EN_OFF, HDMA_EN);
-
-    /* DMA transfer Size */
-    write_ch(zf_chan, is_read, HDMA_XFERSIZE_OFF, (u32)sqe->length);
-
-    /* DMA SAR & DAR */
-    write_ch(zf_chan, is_read, HDMA_SAR_LOW_OFF, (sqe->src_addr & 0xffffffff));
-    write_ch(zf_chan, is_read, HDMA_SAR_HIGH_OFF, ((sqe->src_addr >> 32) & 0xffffffff));
-    write_ch(zf_chan, is_read, HDMA_DAR_LOW_OFF, (sqe->dst_addr & 0xffffffff));
-    write_ch(zf_chan, is_read, HDMA_DAR_HIGH_OFF, ((sqe->dst_addr >> 32) & 0xffffffff));
-
-    /* func_no */
-    write_ch(zf_chan, is_read, HDMA_FUNC_NUM_OFF, ((zf_chan->func_no & PCIE_DPU_EP_GET_PF_NO) | (zf_chan->vfunc_no << HDMA_FUNC_NUM_OFF_VF) | (!isPF(zf_chan->func_no) << HDMA_FUNC_NUM_OFF_VF_ENABLE)));
-
-    /* DMA Doorbell */
-    write_ch(zf_chan, is_read, HDMA_DOORBELL_OFF, HDMA_DOORBELL_START);
-    return;
+	/* DMA Engine enable */
+	write_ch(zf_chan, is_read, HDMA_EN_OFF, HDMA_EN);
+
+	/* DMA transfer Size */
+	write_ch(zf_chan, is_read, HDMA_XFERSIZE_OFF, sqe->length);
+
+	/* DMA SAR & DAR */
+	write_ch(zf_chan, is_read, HDMA_SAR_LOW_OFF, (sqe->src_addr & 0xffffffff));
+	write_ch(zf_chan, is_read, HDMA_SAR_HIGH_OFF,
+			 ((sqe->src_addr >> 32) & 0xffffffff));
+	write_ch(zf_chan, is_read, HDMA_DAR_LOW_OFF, (sqe->dst_addr & 0xffffffff));
+	write_ch(zf_chan, is_read, HDMA_DAR_HIGH_OFF,
+			 ((sqe->dst_addr >> 32) & 0xffffffff));
+
+	/* func_no */
+	write_ch(zf_chan, is_read, HDMA_FUNC_NUM_OFF,
+			 ((zf_chan->func_no & PCIE_DPU_EP_GET_PF_NO) |
+			  (zf_chan->vfunc_no << HDMA_FUNC_NUM_OFF_VF) |
+			  (!isPF(zf_chan->func_no) << HDMA_FUNC_NUM_OFF_VF_ENABLE)));
+
+	/* DMA Doorbell */
+	write_ch(zf_chan, is_read, HDMA_DOORBELL_OFF, HDMA_DOORBELL_START);
+	return;
 }
 
 static void zf_hdma_issue_pending(struct dma_chan *chan)
 {
-    // u32 is_read = HDMA_WR;
-    unsigned long flags = 0;
-    struct zf_hdma_chan *zf_chan = NULL;
-    struct zf_hdma_tx *tx_temp = NULL;
+	// int is_read = HDMA_WR;
+	unsigned long flags = 0;
+	struct zf_hdma_chan *zf_chan = NULL;
+	struct zf_hdma_tx *tx_temp = NULL;
 
-    zf_chan = to_zf_hdma_chan(chan);
+	zf_chan = to_zf_hdma_chan(chan);
 
-    tx_temp = zf_chan->tx_list->next;
-    while (tx_temp->next != NULL)
-    {
-        tx_temp = tx_temp->next;
-    }
+	tx_temp = zf_chan->tx_list->next;
+	while (tx_temp->next != NULL) {
+		tx_temp = tx_temp->next;
+	}
 
-    tx_temp->callback = tx_temp->tx_desc->callback;
-    tx_temp->callback_param = tx_temp->tx_desc->callback_param;
+	tx_temp->callback = tx_temp->tx_desc->callback;
+	tx_temp->callback_param = tx_temp->tx_desc->callback_param;
 
-    spin_lock_irqsave(&zf_chan->zxdh_vc.lock, flags);
-    zxdh_vchan_issue_pending(&zf_chan->zxdh_vc);
-    spin_unlock_irqrestore(&zf_chan->zxdh_vc.lock, flags);
+	spin_lock_irqsave(&zf_chan->zxdh_vc.lock, flags);
+	zxdh_vchan_issue_pending(&zf_chan->zxdh_vc);
+	spin_unlock_irqrestore(&zf_chan->zxdh_vc.lock, flags);
 
-    return;
+	return;
 }
 
 static void free_used_tx(struct zf_hdma_chan *zf_chan)
 {
-    struct zf_hdma_tx *temp = NULL;
+	struct zf_hdma_tx *temp = NULL;
 
-    temp = zf_chan->tx_list->next;
-    zf_chan->tx_list->next = zf_chan->tx_list->next->next;
+	temp = zf_chan->tx_list->next;
+	zf_chan->tx_list->next = zf_chan->tx_list->next->next;
 
-    devm_kfree(&zf_chan->ep_pdev->dev, temp);
+	devm_kfree(&zf_chan->ep_pdev->dev, temp);
 }
 
 int zf_hdma_wr_handler(void *data)
 {
-    u32 chan_status, chan_int_status;
-    struct pcie_dpu_ep *dpu_dev = data;
-    struct dma_chan *chan = NULL;
-    struct zf_hdma_chan *zf_chan = NULL;
-    struct zf_hdma_tx *zf_tx_desc = NULL;
-
-    list_for_each_entry(chan, &dpu_dev->wr_dd->channels, device_node)
-    {
-        zf_chan = to_zf_hdma_chan(chan);
-        if (!zf_chan->tx_list->next || !zf_chan->tx_list->next->tx_desc || !zf_chan->tx_list->next->callback)
-        {
-             DH_LOG_INFO(MODULE_MPF, "wr_zf_chan%d is not used!\n", zf_chan->id);
-            continue;
-        }
-        else
-        {
-            zf_tx_desc = zf_chan->tx_list->next;
-        }
-        read_ch(zf_chan, HDMA_WR, HDMA_STATUS_OFF, &chan_status);
-        read_ch(zf_chan, HDMA_WR, HDMA_INT_STATUS_OFF, &chan_int_status);
-
-        // if (((chan_status & HDMA_STATUS_OFF_STATUS) & HDMA_STATUS_STOPPED) && (chan_int_status & HDMA_STOP_INT_STATUS))
-        // {
-        spin_lock(&zf_chan->zxdh_vc.lock);
-        zf_tx_desc->callback(zf_tx_desc->callback_param);
-        free_used_tx(zf_chan);
-        zf_chan->is_busy = HDMA_CHAN_IDLE;
-        spin_unlock(&zf_chan->zxdh_vc.lock);
-        break;
-        // }
-    }
-
-    return 0;
+	int chan_status, chan_int_status;
+	struct pcie_dpu_ep *dpu_dev = data;
+	struct dma_chan *chan = NULL;
+	struct zf_hdma_chan *zf_chan = NULL;
+	struct zf_hdma_tx *zf_tx_desc = NULL;
+
+	list_for_each_entry(chan, &dpu_dev->wr_dd->channels, device_node) {
+		zf_chan = to_zf_hdma_chan(chan);
+		if (!zf_chan->tx_list->next || !zf_chan->tx_list->next->tx_desc ||
+			!zf_chan->tx_list->next->callback) {
+			DH_LOG_INFO(MODULE_MPF, "wr_zf_chan%d is not used!\n", zf_chan->id);
+			continue;
+		} else {
+			zf_tx_desc = zf_chan->tx_list->next;
+		}
+		read_ch(zf_chan, HDMA_WR, HDMA_STATUS_OFF, &chan_status);
+		read_ch(zf_chan, HDMA_WR, HDMA_INT_STATUS_OFF, &chan_int_status);
+
+		// if (((chan_status & HDMA_STATUS_OFF_STATUS) & HDMA_STATUS_STOPPED) &&
+		// (chan_int_status & HDMA_STOP_INT_STATUS))
+		// {
+		spin_lock(&zf_chan->zxdh_vc.lock);
+		zf_tx_desc->callback(zf_tx_desc->callback_param);
+		free_used_tx(zf_chan);
+		spin_unlock(&zf_chan->zxdh_vc.lock);
+		break;
+		// }
+	}
+	zf_chan->is_busy = HDMA_CHAN_IDLE;
+
+	return 0;
 }
 
 int zf_hdma_rd_handler(void *data)
 {
-    u32 chan_status = 0, chan_int_status = 0;
-    struct pcie_dpu_ep *dpu_dev = data;
-    struct dma_chan *chan = NULL;
-    struct zf_hdma_chan *zf_chan = NULL;
-    struct zf_hdma_tx *zf_tx_desc = NULL;
-
-    list_for_each_entry(chan, &dpu_dev->rd_dd->channels, device_node)
-    {
-        zf_chan = to_zf_hdma_chan(chan);
-        if (!zf_chan->tx_list->next || !zf_chan->tx_list->next->tx_desc || !zf_chan->tx_list->next->callback)
-        {
-            DH_LOG_INFO(MODULE_MPF, "rd_zf_chan%d is not used!\n", zf_chan->id);
-            continue;
-        }
-        else
-        {
-            zf_tx_desc = zf_chan->tx_list->next;
-        }
-        read_ch(zf_chan, HDMA_RD, HDMA_STATUS_OFF, &chan_status);
-        read_ch(zf_chan, HDMA_RD, HDMA_INT_STATUS_OFF, &chan_int_status);
-
-        // if (((chan_status & HDMA_STATUS_OFF_STATUS) & HDMA_STATUS_STOPPED) && (chan_int_status & HDMA_STOP_INT_STATUS))
-        // {
-        spin_lock(&zf_chan->zxdh_vc.lock);
-        zf_tx_desc->callback(zf_tx_desc->callback_param);
-        free_used_tx(zf_chan);
-        zf_chan->is_busy = HDMA_CHAN_IDLE;
-        spin_unlock(&zf_chan->zxdh_vc.lock);
-        break;
-        // }
-    }
-
-    return 0;
+	int chan_status = 0, chan_int_status = 0;
+	struct pcie_dpu_ep *dpu_dev = data;
+	struct dma_chan *chan = NULL;
+	struct zf_hdma_chan *zf_chan = NULL;
+	struct zf_hdma_tx *zf_tx_desc = NULL;
+
+	list_for_each_entry(chan, &dpu_dev->rd_dd->channels, device_node) {
+		zf_chan = to_zf_hdma_chan(chan);
+		if (!zf_chan->tx_list->next || !zf_chan->tx_list->next->tx_desc ||
+			!zf_chan->tx_list->next->callback) {
+			DH_LOG_INFO(MODULE_MPF, "rd_zf_chan%d is not used!\n", zf_chan->id);
+			continue;
+		} else {
+			zf_tx_desc = zf_chan->tx_list->next;
+		}
+		read_ch(zf_chan, HDMA_RD, HDMA_STATUS_OFF, &chan_status);
+		read_ch(zf_chan, HDMA_RD, HDMA_INT_STATUS_OFF, &chan_int_status);
+
+		// if (((chan_status & HDMA_STATUS_OFF_STATUS) & HDMA_STATUS_STOPPED) &&
+		// (chan_int_status & HDMA_STOP_INT_STATUS))
+		// {
+		spin_lock(&zf_chan->zxdh_vc.lock);
+		zf_tx_desc->callback(zf_tx_desc->callback_param);
+		free_used_tx(zf_chan);
+		spin_unlock(&zf_chan->zxdh_vc.lock);
+		break;
+		// }
+	}
+	zf_chan->is_busy = HDMA_CHAN_IDLE;
+
+	return 0;
 }
 
 static void zf_hdma_desc_free(struct zxdh_virt_dma_desc *zxdh_vd)
 {
-    dma_descriptor_unmap(&zxdh_vd->tx);
+	dma_descriptor_unmap(&zxdh_vd->tx);
 }
 
 static bool zf_dma_filter_fn(struct dma_chan *chan, void *node)
 {
-    unsigned long dev_node = (unsigned long)dev_to_node(&chan->dev->device);
-    return (dev_node == (unsigned long)node);
+	return (dev_to_node(&chan->dev->device) == (int)(unsigned long)node);
 }
 
-struct dma_chan *zte_get_chan_for_dma(struct pci_epc *epc, u32 is_read)
+struct dma_chan *get_chan_for_dma(struct pci_epc *epc, int is_read)
 {
-    int node = 0;
-    dma_cap_mask_t dma_mask;
-    struct dma_chan *chan = NULL;
-    struct pcie_dpu_ep *ep = NULL;
-
-    if (IS_ERR_OR_NULL(epc))
-    {
-        DH_LOG_ERR(MODULE_MPF, "not found epc\n");
-        return NULL;
-    }
-
-    ep = epc_get_drvdata(epc);
-    if (!ep)
-    {
-        DH_LOG_ERR(MODULE_MPF, " not found ep\n");
-        return NULL;
-    }
-
-    if (is_read)
-    {
-        node = dev_to_node(ep->rd_dd->dev);
-    }
-    else
-    {
-        node = dev_to_node(ep->wr_dd->dev);
-    }
-
-    dma_cap_zero(dma_mask);
-    dma_cap_set(DMA_MEMCPY, dma_mask);
-    chan = dma_request_channel(dma_mask, zf_dma_filter_fn, (void *)(unsigned long)node);
-
-    return chan;
+	int node = 0;
+	dma_cap_mask_t dma_mask;
+	struct dma_chan *chan = NULL;
+	struct pcie_dpu_ep *ep = NULL;
+
+	if (!epc) {
+		DH_LOG_ERR(MODULE_MPF, "not found epc\n");
+		return NULL;
+	}
+
+	ep = epc_get_drvdata(epc);
+	if (!ep) {
+		DH_LOG_ERR(MODULE_MPF, " not found ep\n");
+		return NULL;
+	}
+
+	if (is_read) {
+		node = dev_to_node(ep->rd_dd->dev);
+	} else {
+		node = dev_to_node(ep->wr_dd->dev);
+	}
+
+	dma_cap_zero(dma_mask);
+	dma_cap_set(DMA_MEMCPY, dma_mask);
+	chan = dma_request_channel(dma_mask, zf_dma_filter_fn,
+							   (void *)(unsigned long)node);
+
+	return chan;
 }
-EXPORT_SYMBOL_GPL(zte_get_chan_for_dma);
+EXPORT_SYMBOL_GPL(get_chan_for_dma);
 
-void zte_zf_pcie_set_pfvf_no(struct dma_chan *chan, u8 func_no, u8 vfunc_no)
+void zf_pcie_set_pfvf_no(struct dma_chan *chan, u8 func_no, u8 vfunc_no)
 {
-    struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan);
+	struct zf_hdma_chan *zf_chan = to_zf_hdma_chan(chan);
 
-    DH_LOG_INFO(MODULE_MPF, "func_no = 0x%x, vfunc_no = 0x%x\n",func_no, vfunc_no);
+	DH_LOG_INFO(MODULE_MPF, "func_no = 0x%x, vfunc_no = 0x%x\n", func_no,
+				vfunc_no);
 
-    zf_chan->func_no = func_no;
-    zf_chan->vfunc_no = vfunc_no;
+	zf_chan->func_no = func_no;
+	zf_chan->vfunc_no = vfunc_no;
 }
-EXPORT_SYMBOL_GPL(zte_zf_pcie_set_pfvf_no);
+EXPORT_SYMBOL_GPL(zf_pcie_set_pfvf_no);
 
 int zf_pcie_get_hdma_chan(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
-                          struct dma_chan **rchan, struct dma_chan **wchan)
+						  struct dma_chan **rchan, struct dma_chan **wchan)
 {
-    struct dma_chan *rch, *wch;
-
-    wch = zte_get_chan_for_dma(epc, HDMA_WR);
-    if (IS_ERR_OR_NULL(wch))
-    {
-        DH_LOG_ERR(MODULE_MPF, "failed to get write chan\n");
-        return -EFAULT;
-    }
-
-    rch = zte_get_chan_for_dma(epc, HDMA_RD);
-    if (IS_ERR_OR_NULL(rch))
-    {
-        DH_LOG_ERR(MODULE_MPF, "failed to get read chan\n");
-        dma_release_channel(rch);
-        return -EFAULT;
-    }
-
-    zte_zf_pcie_set_pfvf_no(rch, func_no, vfunc_no);
-    zte_zf_pcie_set_pfvf_no(wch, func_no, vfunc_no);
-
-    *rchan = rch;
-    *wchan = wch;
-    return 0;
+	struct dma_chan *rch, *wch;
+
+	wch = get_chan_for_dma(epc, HDMA_WR);
+	if (IS_ERR_OR_NULL(wch)) {
+		DH_LOG_ERR(MODULE_MPF, "failed to get write chan\n");
+		return -EFAULT;
+	}
+
+	rch = get_chan_for_dma(epc, HDMA_RD);
+	if (IS_ERR_OR_NULL(rch)) {
+		DH_LOG_ERR(MODULE_MPF, "failed to get read chan\n");
+		dma_release_channel(rch);
+		return -EFAULT;
+	}
+
+	zf_pcie_set_pfvf_no(rch, func_no, vfunc_no);
+	zf_pcie_set_pfvf_no(wch, func_no, vfunc_no);
+
+	*rchan = rch;
+	*wchan = wch;
+	return 0;
 }
 
-static int zf_hdma_virtual_channels_init(struct dma_device *dma_dev, struct pci_dev *pdev, void __iomem *addr)
+static int zf_hdma_virtual_channels_init(struct dma_device *dma_dev,
+										 struct pci_dev *pdev,
+										 void __iomem *addr)
 {
-    struct zf_hdma_chan *zf_chan = NULL;
-    u32 i = 0;
-
-    INIT_LIST_HEAD(&dma_dev->channels);
-
-    /*
-     * Register as many memcpy as we have physical channels,
-     * we won't always be able to use all but the code will have
-     * to cope with that situation.
-     */
-    for (i = 0; i < (u32)ZF_HDMA_CHAN_NUM; i++)
-    {
-        zf_chan = devm_kzalloc(&pdev->dev, sizeof(*zf_chan), GFP_KERNEL);
-        if (!zf_chan)
-        {
-            // TODO free
-            return -ENOMEM;
-        }
-        zf_chan->sqe_list = devm_kzalloc(&pdev->dev, sizeof(struct zf_hdma_sqe), GFP_KERNEL);
-        if (!zf_chan->sqe_list)
-        {
-            // TODO free
-            return -ENOMEM;
-        }
-        zf_chan->tx_list = devm_kzalloc(&pdev->dev, sizeof(struct zf_hdma_tx), GFP_KERNEL);
-        if (!zf_chan->tx_list)
-        {
-            // TODO free
-            return -ENOMEM;
-        }
-        zf_chan->tx_list->tx_id = 0;
-
-        zf_chan->id = i + ZF_HDMA_CHAN_FIRST_IDX;
-        zf_chan->ep_pdev = pdev;
-        zf_chan->base_addr = addr + ZF_HDMA_ADDR_OFFSET;
-        zf_chan->is_busy = HDMA_CHAN_IDLE;
-
-        zf_chan->name = kasprintf(GFP_KERNEL, "chan%d", i);
-        if (!zf_chan->name)
-            return -ENOMEM;
-
-        zf_chan->zxdh_vc.desc_free = zf_hdma_desc_free;
-
-        zxdh_vchan_init(&zf_chan->zxdh_vc, dma_dev);
-    }
-
-    return i;
+	struct zf_hdma_chan *zf_chan = NULL;
+	int i = 0;
+
+	INIT_LIST_HEAD(&dma_dev->channels);
+
+	/*
+   * Register as many memcpy as we have physical channels,
+   * we won't always be able to use all but the code will have
+   * to cope with that situation.
+   */
+	for (i = 0; i < ZF_HDMA_CHAN_NUM; i++) {
+		zf_chan = devm_kzalloc(&pdev->dev, sizeof(*zf_chan), GFP_KERNEL);
+		if (!zf_chan) {
+			// TODO free
+			return -ENOMEM;
+		}
+		zf_chan->sqe_list = devm_kzalloc(&pdev->dev, sizeof(struct zf_hdma_sqe),
+										 GFP_KERNEL);
+		if (!zf_chan->sqe_list) {
+			// TODO free
+			return -ENOMEM;
+		}
+		zf_chan->tx_list =
+				devm_kzalloc(&pdev->dev, sizeof(struct zf_hdma_tx), GFP_KERNEL);
+		if (!zf_chan->tx_list) {
+			// TODO free
+			return -ENOMEM;
+		}
+		zf_chan->tx_list->tx_id = 0;
+
+		zf_chan->id = i + ZF_HDMA_CHAN_FIRST_IDX;
+		zf_chan->ep_pdev = pdev;
+		zf_chan->base_addr = addr + ZF_HDMA_ADDR_OFFSET;
+		zf_chan->is_busy = HDMA_CHAN_IDLE;
+
+		zf_chan->name = kasprintf(GFP_KERNEL, "chan%d", i);
+		if (!zf_chan->name)
+			return -ENOMEM;
+
+		zf_chan->zxdh_vc.desc_free = zf_hdma_desc_free;
+
+		zxdh_vchan_init(&zf_chan->zxdh_vc, dma_dev);
+	}
+
+	return i;
 }
 
-void zf_hdma_device_init(struct device *dev, struct dma_device *dd, u32 is_read)
+void zf_hdma_device_init(struct device *dev, struct dma_device *dd, int is_read)
 {
-    dd->device_alloc_chan_resources = zf_hdma_alloc_chan_resources; // 3,4,8,9 unneccessary
-    dd->device_free_chan_resources = zf_hdma_free_chan_resources;
-    dd->device_config = zf_hdma_device_config;
-    dd->device_tx_status = zf_hdma_tx_status;
-    dd->device_issue_pending = zf_hdma_issue_pending; // push pending transactions to hardware
-    dd->device_prep_dma_memcpy = zf_hdma_prep_dma_memcpy;
-    dd->device_terminate_all = zf_hdma_terminate_all;
-    dd->device_prep_slave_sg = zf_hdma_device_prep_slave_sg;     // prepares a slave dma operation
-    dd->device_prep_dma_cyclic = zf_hdma_device_prep_dma_cyclic; // prepare a cyclic dma operation suitable for audio. The function takes a buffer of size buf_len. The callback function will be called after period_len bytes have been transferred.
-
-    dd->chancnt = ZF_HDMA_CHAN_NUM;
-    dd->privatecnt = 0;
-    dd->copy_align = ZF_HDMA_ALIGN_SIZE;
-    dd->src_addr_widths = ZF_HDMA_DMA_BUSWIDTHS;
-    dd->dst_addr_widths = ZF_HDMA_DMA_BUSWIDTHS;
-    dd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
-    dd->dev = dev;
-
-    if (is_read)
-    {
-        dd->directions = BIT(DMA_MEM_TO_DEV);
-    }
-    else
-    {
-        dd->directions = BIT(DMA_DEV_TO_MEM);
-    }
-
-    dma_cap_zero(dd->cap_mask);
-    dma_cap_set(DMA_MEMCPY, dd->cap_mask);
+	dd->device_alloc_chan_resources =
+			zf_hdma_alloc_chan_resources; // 3,4,8,9 unneccessary
+	dd->device_free_chan_resources = zf_hdma_free_chan_resources;
+	dd->device_config = zf_hdma_device_config;
+	dd->device_tx_status = zf_hdma_tx_status;
+	dd->device_issue_pending =
+			zf_hdma_issue_pending; // push pending transactions to hardware
+	dd->device_prep_dma_memcpy = zf_hdma_prep_dma_memcpy;
+	dd->device_terminate_all = zf_hdma_terminate_all;
+	dd->device_prep_slave_sg =
+			zf_hdma_device_prep_slave_sg; // prepares a slave dma operation
+	dd->device_prep_dma_cyclic =
+			zf_hdma_device_prep_dma_cyclic; // prepare a cyclic dma operation suitable
+	// for audio. The function takes a buffer
+	// of size buf_len. The callback function
+	// will be called after period_len bytes
+	// have been transferred.
+
+	dd->chancnt = ZF_HDMA_CHAN_NUM;
+	dd->privatecnt = 0;
+	dd->copy_align = ZF_HDMA_ALIGN_SIZE;
+	dd->src_addr_widths = ZF_HDMA_DMA_BUSWIDTHS;
+	dd->dst_addr_widths = ZF_HDMA_DMA_BUSWIDTHS;
+	dd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
+	dd->dev = dev;
+
+	if (is_read) {
+		dd->directions = BIT(DMA_MEM_TO_DEV);
+	} else {
+		dd->directions = BIT(DMA_DEV_TO_MEM);
+	}
+
+	dma_cap_zero(dd->cap_mask);
+	dma_cap_set(DMA_MEMCPY, dd->cap_mask);
 }
 
 int callback_thread_function(void *data)
 {
-    u32 chan_status = 0;
-    struct pcie_dpu_ep *dpu_dev = data;
-    struct dma_chan *chan = NULL;
-    struct zf_hdma_chan *zf_chan = NULL;
-    struct zf_hdma_tx *zf_tx_desc = NULL;
-
-    DH_LOG_INFO(MODULE_MPF, "enter!\n");
-
-    while (!kthread_should_stop())
-    {
-        list_for_each_entry(chan, &dpu_dev->rd_dd->channels, device_node)
-        {
-            zf_chan = to_zf_hdma_chan(chan);
-            if (!zf_chan->tx_list->next || !zf_chan->tx_list->next->tx_desc || !zf_chan->tx_list->next->callback)
-            {
-                continue;
-            }
-            else
-            {
-                if ((zf_chan->sqe_list->next != NULL) && (zf_chan->is_busy == HDMA_CHAN_IDLE))
-                {
-                    zf_hdma_register_set(zf_chan, HDMA_RD, zf_chan->sqe_list->next);
-                    zf_chan->is_busy = HDMA_CHAN_USED;
-                    // DH_LOG_DEBUG(MODULE_MPF, "zf_chan->id:%d is_pending\n", zf_chan->id);
-                    free_used_sqe(zf_chan);
-                }
-
-                zf_tx_desc = zf_chan->tx_list->next;
-                // DH_LOG_DEBUG(MODULE_MPF, "rd_zf_chan%d is used!\n", zf_chan->id);
-
-                read_ch(zf_chan, HDMA_RD, HDMA_STATUS_OFF, &chan_status);
-
-                if ((chan_status & HDMA_STATUS_OFF_STATUS) == HDMA_STATUS_STOPPED && (zf_chan->is_busy == HDMA_CHAN_USED))
-                {
-                    spin_lock(&zf_chan->zxdh_vc.lock);
-                    zf_tx_desc->callback(zf_tx_desc->callback_param);
-                    free_used_tx(zf_chan);
-                    spin_unlock(&zf_chan->zxdh_vc.lock);
-                    zf_chan->is_busy = HDMA_CHAN_IDLE;
-                }
-            }
-        }
-
-        list_for_each_entry(chan, &dpu_dev->wr_dd->channels, device_node)
-        {
-            zf_chan = to_zf_hdma_chan(chan);
-            if (!zf_chan->tx_list->next || !zf_chan->tx_list->next->tx_desc || !zf_chan->tx_list->next->callback)
-            {
-                continue;
-            }
-            else
-            {
-                if ((zf_chan->sqe_list->next != NULL) && (zf_chan->is_busy == HDMA_CHAN_IDLE))
-                {
-                    zf_hdma_register_set(zf_chan, HDMA_WR, zf_chan->sqe_list->next);
-                    zf_chan->is_busy = HDMA_CHAN_USED;
-                    // DH_LOG_DEBUG(MODULE_MPF, "zf_chan->id:%d is_pending\n", zf_chan->id);
-                    free_used_sqe(zf_chan);
-                }
-
-                zf_tx_desc = zf_chan->tx_list->next;
-                // DH_LOG_DEBUG(MODULE_MPF, "wr_zf_chan%d is used!\n", zf_chan->id);
-                read_ch(zf_chan, HDMA_WR, HDMA_STATUS_OFF, &chan_status);
-
-                if ((chan_status & HDMA_STATUS_OFF_STATUS) == HDMA_STATUS_STOPPED && (zf_chan->is_busy == HDMA_CHAN_USED))
-                {
-                    spin_lock(&zf_chan->zxdh_vc.lock);
-                    zf_tx_desc->callback(zf_tx_desc->callback_param);
-                    free_used_tx(zf_chan);
-                    spin_unlock(&zf_chan->zxdh_vc.lock);
-                    zf_chan->is_busy = HDMA_CHAN_IDLE;
-                }
-            }
-        }
-        msleep(1);
-    }
-
-    DH_LOG_INFO(MODULE_MPF, "Kernel thread is stopping\n");
-    return 0;
+	int chan_status = 0;
+	struct pcie_dpu_ep *dpu_dev = data;
+	struct dma_chan *chan = NULL;
+	struct zf_hdma_chan *zf_chan = NULL;
+	struct zf_hdma_tx *zf_tx_desc = NULL;
+
+	DH_LOG_ERR(MODULE_MPF, "enter!\n");
+
+	while (!kthread_should_stop()) {
+		list_for_each_entry(chan, &dpu_dev->rd_dd->channels, device_node) {
+			zf_chan = to_zf_hdma_chan(chan);
+			if (!zf_chan->tx_list->next || !zf_chan->tx_list->next->tx_desc ||
+				!zf_chan->tx_list->next->callback) {
+				continue;
+			} else {
+				if ((zf_chan->sqe_list->next != NULL) &&
+					(zf_chan->is_busy == HDMA_CHAN_IDLE)) {
+					zf_hdma_register_set(zf_chan, HDMA_RD,
+										 zf_chan->sqe_list->next);
+					zf_chan->is_busy = HDMA_CHAN_USED;
+					// DH_LOG_DEBUG(MODULE_MPF, "zf_chan->id:%d is_pending\n",
+					// zf_chan->id);
+					free_used_sqe(zf_chan);
+				}
+
+				zf_tx_desc = zf_chan->tx_list->next;
+				// DH_LOG_DEBUG(MODULE_MPF, "rd_zf_chan%d is used!\n", zf_chan->id);
+
+				read_ch(zf_chan, HDMA_RD, HDMA_STATUS_OFF, &chan_status);
+
+				if ((chan_status & HDMA_STATUS_OFF_STATUS) ==
+							HDMA_STATUS_STOPPED &&
+					(zf_chan->is_busy == HDMA_CHAN_USED)) {
+					spin_lock(&zf_chan->zxdh_vc.lock);
+					zf_tx_desc->callback(zf_tx_desc->callback_param);
+					free_used_tx(zf_chan);
+					spin_unlock(&zf_chan->zxdh_vc.lock);
+					zf_chan->is_busy = HDMA_CHAN_IDLE;
+				}
+			}
+		}
+
+		list_for_each_entry(chan, &dpu_dev->wr_dd->channels, device_node) {
+			zf_chan = to_zf_hdma_chan(chan);
+			if (!zf_chan->tx_list->next || !zf_chan->tx_list->next->tx_desc ||
+				!zf_chan->tx_list->next->callback) {
+				continue;
+			} else {
+				if ((zf_chan->sqe_list->next != NULL) &&
+					(zf_chan->is_busy == HDMA_CHAN_IDLE)) {
+					zf_hdma_register_set(zf_chan, HDMA_WR,
+										 zf_chan->sqe_list->next);
+					zf_chan->is_busy = HDMA_CHAN_USED;
+					// DH_LOG_DEBUG(MODULE_MPF, "zf_chan->id:%d is_pending\n",
+					// zf_chan->id);
+					free_used_sqe(zf_chan);
+				}
+
+				zf_tx_desc = zf_chan->tx_list->next;
+				// DH_LOG_DEBUG(MODULE_MPF, "wr_zf_chan%d is used!\n", zf_chan->id);
+				read_ch(zf_chan, HDMA_WR, HDMA_STATUS_OFF, &chan_status);
+
+				if ((chan_status & HDMA_STATUS_OFF_STATUS) ==
+							HDMA_STATUS_STOPPED &&
+					(zf_chan->is_busy == HDMA_CHAN_USED)) {
+					spin_lock(&zf_chan->zxdh_vc.lock);
+					zf_tx_desc->callback(zf_tx_desc->callback_param);
+					free_used_tx(zf_chan);
+					spin_unlock(&zf_chan->zxdh_vc.lock);
+					zf_chan->is_busy = HDMA_CHAN_IDLE;
+				}
+			}
+		}
+		msleep(1);
+	}
+
+	DH_LOG_INFO(MODULE_MPF, "Kernel thread is stopping\n");
+	return 0;
 }
 
 int pcie_zf_dma_init(struct pcie_dpu_ep *dpu_dev, struct pci_dev *pdev)
 {
-    int ret = 0;
-    int node = 0;
-    struct device *dev_wr = NULL, *dev_rd = NULL;
-    struct dma_device *wr_dd = NULL, *rd_dd = NULL;
-
-    if (IS_ERR_OR_NULL(dpu_dev))
-    {
-        DH_LOG_ERR(MODULE_MPF, "err input\n");
-        return -ENOENT;
-    }
-
-    dev_wr = &(dpu_dev->zf_pdev->dev);
-    dev_rd = &(dpu_dev->zf_pdev_dma->dev);
-
-    node = dev_to_node(dev_wr);
-
-    wr_dd = kzalloc_node(sizeof(struct dma_device), GFP_KERNEL, node);
-    if (!wr_dd)
-    {
-        DH_LOG_ERR(MODULE_MPF, "Error kzalloc node\n");
-        return -ENODEV;
-    }
-
-    rd_dd = kzalloc_node(sizeof(struct dma_device), GFP_KERNEL, node);
-    if (!rd_dd)
-    {
-        DH_LOG_ERR(MODULE_MPF, "Error kzalloc node\n");
-        kfree(wr_dd);
-        return -ENODEV;
-    }
-
-    zf_hdma_device_init(dev_wr, wr_dd, HDMA_WR);
-    zf_hdma_device_init(dev_rd, rd_dd, HDMA_RD);
-
-    zf_hdma_virtual_channels_init(wr_dd, pdev, dpu_dev->dbi_base);
-    zf_hdma_virtual_channels_init(rd_dd, pdev, dpu_dev->dbi_base);
-
-    ret = dma_async_device_register(wr_dd);
-    ret |= dma_async_device_register(rd_dd);
-    if (ret)
-    {
-        DH_LOG_ERR(MODULE_MPF, "dma_async_device_register failed\n");
-        goto free_dma_device;
-    }
-
-    dpu_dev->wr_dd = wr_dd;
-    dpu_dev->rd_dd = rd_dd;
-    DH_LOG_INFO(MODULE_MPF, "success!\n");
-
-    if (dpu_dev->ep_id >=0 && dpu_dev->ep_id < PCIE_DPU_EP_NUM)
-    {
-        callback_thread[dpu_dev->ep_id] = kthread_run(callback_thread_function, dpu_dev, "my_thread");
-        if (callback_thread[dpu_dev->ep_id])
-        {
-            DH_LOG_INFO(MODULE_MPF, "Thread created successfully\n");
-        }
-        else
-        {
-            DH_LOG_ERR(MODULE_MPF, "Thread creation failed\n");
-        }
-    }
-
-    return 0;
+	int ret = 0;
+	int node = 0;
+	struct device *dev_wr = NULL, *dev_rd = NULL;
+	struct dma_device *wr_dd = NULL, *rd_dd = NULL;
+
+	if (NULL == dpu_dev) {
+		DH_LOG_ERR(MODULE_MPF, "err input\n");
+		return -ENOENT;
+	}
+
+	dev_wr = &(dpu_dev->zf_pdev->dev);
+	dev_rd = &(dpu_dev->zf_pdev_dma->dev);
+
+	node = dev_to_node(dev_wr);
+
+	wr_dd = kzalloc_node(sizeof(struct dma_device), GFP_KERNEL, node);
+	if (!wr_dd) {
+		DH_LOG_ERR(MODULE_MPF, "Error kzalloc node\n");
+		return -ENODEV;
+	}
+
+	rd_dd = kzalloc_node(sizeof(struct dma_device), GFP_KERNEL, node);
+	if (!rd_dd) {
+		DH_LOG_ERR(MODULE_MPF, "Error kzalloc node\n");
+		kfree(wr_dd);
+		return -ENODEV;
+	}
+
+	zf_hdma_device_init(dev_wr, wr_dd, HDMA_WR);
+	zf_hdma_device_init(dev_rd, rd_dd, HDMA_RD);
+
+	zf_hdma_virtual_channels_init(wr_dd, pdev, dpu_dev->dbi_base);
+	zf_hdma_virtual_channels_init(rd_dd, pdev, dpu_dev->dbi_base);
+
+	ret = dma_async_device_register(wr_dd);
+	ret |= dma_async_device_register(rd_dd);
+	if (ret) {
+		DH_LOG_ERR(MODULE_MPF, "dma_async_device_register failed\n");
+		goto free_dma_device;
+	}
+
+	dpu_dev->wr_dd = wr_dd;
+	dpu_dev->rd_dd = rd_dd;
+	DH_LOG_INFO(MODULE_MPF, "success!\n");
+
+	callback_thread[dpu_dev->ep_id] =
+			kthread_run(callback_thread_function, dpu_dev, "my_thread");
+	if (callback_thread[dpu_dev->ep_id]) {
+		DH_LOG_INFO(MODULE_MPF, "Thread created successfully\n");
+	} else {
+		DH_LOG_ERR(MODULE_MPF, "Thread creation failed\n");
+	}
+
+	return 0;
 
 free_dma_device:
-    kfree(wr_dd);
-    kfree(rd_dd);
-    return ret;
+	kfree(wr_dd);
+	kfree(rd_dd);
+	return ret;
 }
 
 void pcie_zf_dma_free(struct pcie_dpu_ep *dpu_dev, struct pci_dev *pdev)
 {
-
-    if (callback_thread[dpu_dev->ep_id])
-    {
-        kthread_stop(callback_thread[dpu_dev->ep_id]);
-        DH_LOG_INFO(MODULE_MPF, "Thread created successfully\n");
-    }
-
-    if (dpu_dev->wr_dd)
-    {
-        dma_async_device_unregister(dpu_dev->wr_dd);
-        kfree(dpu_dev->wr_dd);
-    }
-    if (dpu_dev->rd_dd)
-    {
-        dma_async_device_unregister(dpu_dev->rd_dd);
-        kfree(dpu_dev->rd_dd);
-    }
+	if (callback_thread[dpu_dev->ep_id]) {
+		kthread_stop(callback_thread[dpu_dev->ep_id]);
+		DH_LOG_INFO(MODULE_MPF, "Thread created successfully\n");
+	}
+
+	if (dpu_dev->wr_dd) {
+		dma_async_device_unregister(dpu_dev->wr_dd);
+		kfree(dpu_dev->wr_dd);
+	}
+	if (dpu_dev->rd_dd) {
+		dma_async_device_unregister(dpu_dev->rd_dd);
+		kfree(dpu_dev->rd_dd);
+	}
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-hdma.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-hdma.h
index b958917e003e0c0b4f9a470c0aae9aefb196917a..d6ed010e989edc8e48d65f0db41ddc14e1621ebc 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-hdma.h
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/pcie-zte-zf-hdma.h
@@ -28,132 +28,128 @@
 #include "pcie-zte-zf-epc.h"
 #include "virt-dma.h"
 
-#define ZF_HDMA_DRIVER_NAME              "dh_hdma"
-#define ZF_HDMA_ADDR_OFFSET              (0x6800000)
-#define ZF_HDMA_PER_CHANNEL_SIZE         (0x200)
-#define ZF_HDMA_RDCH_OFFSET              (0x100)
-#define HDMA_RD                          1
-#define HDMA_WR                          0
+#define ZF_HDMA_DRIVER_NAME "dh_hdma"
+#define ZF_HDMA_ADDR_OFFSET (0x6800000)
+#define ZF_HDMA_PER_CHANNEL_SIZE (0x200)
+#define ZF_HDMA_RDCH_OFFSET (0x100)
+#define HDMA_RD 1
+#define HDMA_WR 0
 
 /* ZF HDMA init*/
-#define DPU_HDMA_CHAN_NUM                (36)
-#define ZF_HDMA_CHAN_FIRST_IDX           (18)
-#define ZF_HDMA_CHAN_NUM                 (DPU_HDMA_CHAN_NUM - ZF_HDMA_CHAN_FIRST_IDX)
-#define ZF_HDMA_VIRT_CHAN_NUM            ZF_HDMA_CHAN_NUM
-#define ZF_HDMA_ALIGN_SIZE               (1)
-#define ZF_HDMA_DMA_BUSWIDTHS            (BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
-#define ZF_HDMA_WAIT_SLEEP_TIMES         (10)
-#define ZF_HDMA_MAX_WAIT_TIMES           (100)
+#define DPU_HDMA_CHAN_NUM (36)
+#define ZF_HDMA_CHAN_FIRST_IDX (18)
+#define ZF_HDMA_CHAN_NUM (DPU_HDMA_CHAN_NUM - ZF_HDMA_CHAN_FIRST_IDX)
+#define ZF_HDMA_VIRT_CHAN_NUM ZF_HDMA_CHAN_NUM
+#define ZF_HDMA_ALIGN_SIZE (1)
+#define ZF_HDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
+#define ZF_HDMA_WAIT_SLEEP_TIMES (10)
+#define ZF_HDMA_MAX_WAIT_TIMES (100)
 
 /* HDMA register*/
-#define HDMA_EN_OFF                      (0x0)
-#define HDMA_DOORBELL_OFF                (0x4)
-#define HDMA_ELEM_PF_OFF                 (0x8)
-#define HDMA_HANDSHAKE_OFF               (0xc)
-#define HDMA_LLP_LOW_OFF                 (0x10)
-#define HDMA_LLP_HIGH_OFF                (0x14)
-#define HDMA_CYCLE_OFF                   (0x18)
-#define HDMA_XFERSIZE_OFF                (0x1c)
-#define HDMA_XFERSIZE_OFF_COMPLETE       (0x0)
-#define HDMA_SAR_LOW_OFF                 (0x20)
-#define HDMA_SAR_HIGH_OFF                (0x24)
-#define HDMA_DAR_LOW_OFF                 (0x28)
-#define HDMA_DAR_HIGH_OFF                (0x2c)
-#define HDMA_WATERMARK_EN_OFF            (0x30)
-#define HDMA_CONTROL1_OFF                (0x34)
-#define HDMA_FUNC_NUM_OFF                (0x38)
-#define HDMA_FUNC_NUM_OFF_VF_ENABLE      (16)
-#define HDMA_FUNC_NUM_OFF_VF             (17)
-#define HDMA_QOS_OFF                     (0x3c)
+#define HDMA_EN_OFF (0x0)
+#define HDMA_DOORBELL_OFF (0x4)
+#define HDMA_ELEM_PF_OFF (0x8)
+#define HDMA_HANDSHAKE_OFF (0xc)
+#define HDMA_LLP_LOW_OFF (0x10)
+#define HDMA_LLP_HIGH_OFF (0x14)
+#define HDMA_CYCLE_OFF (0x18)
+#define HDMA_XFERSIZE_OFF (0x1c)
+#define HDMA_XFERSIZE_OFF_COMPLETE (0x0)
+#define HDMA_SAR_LOW_OFF (0x20)
+#define HDMA_SAR_HIGH_OFF (0x24)
+#define HDMA_DAR_LOW_OFF (0x28)
+#define HDMA_DAR_HIGH_OFF (0x2c)
+#define HDMA_WATERMARK_EN_OFF (0x30)
+#define HDMA_CONTROL1_OFF (0x34)
+#define HDMA_FUNC_NUM_OFF (0x38)
+#define HDMA_FUNC_NUM_OFF_VF_ENABLE (16)
+#define HDMA_FUNC_NUM_OFF_VF (17)
+#define HDMA_QOS_OFF (0x3c)
 
-#define HDMA_STATUS_OFF                  (0x80)
-#define HDMA_STATUS_OFF_STATUS           (0x3)
-#define HDMA_STATUS_STOPPED              (0x3)
-#define HDMA_INT_STATUS_OFF              (0x84)
-#define HDMA_STOP_INT_STATUS             (0x1)
-#define HDMA_INT_SETUP_OFF               (0x88)
-#define HDMA_INT_MASK_BIT                (0x0)
-#define HDMA_INT_MASK                    (0x7)
-#define HDMA_LSIE_BIT                    (0x4)
-#define HDMA_LSIE_MASK                   (0x1)
-#define HDMA_INT_CLEAR_OFF               (0x8c)
-#define HDMA_MSI_STOP_LOW_OFF            (0x90)
-#define HDMA_MSI_STOP_HIGH_OFF           (0x94)
-#define HDMA_MSI_WATERMARK_LOW_OFF       (0x98)
-#define HDMA_MSI_WATERMARK_HIGH_OFF      (0x9c)
-#define HDMA_MSI_ABORT_LOW_OFF           (0xa0)
-#define HDMA_MSI_ABORT_HIGH_OFF          (0xa4)
-#define HDMA_MSI_MSI_MSGD_OFF            (0xa8)
+#define HDMA_STATUS_OFF (0x80)
+#define HDMA_STATUS_OFF_STATUS (0x3)
+#define HDMA_STATUS_STOPPED (0x3)
+#define HDMA_INT_STATUS_OFF (0x84)
+#define HDMA_STOP_INT_STATUS (0x1)
+#define HDMA_INT_SETUP_OFF (0x88)
+#define HDMA_INT_MASK_BIT (0x0)
+#define HDMA_INT_MASK (0x7)
+#define HDMA_LSIE_BIT (0x4)
+#define HDMA_LSIE_MASK (0x1)
+#define HDMA_INT_CLEAR_OFF (0x8c)
+#define HDMA_MSI_STOP_LOW_OFF (0x90)
+#define HDMA_MSI_STOP_HIGH_OFF (0x94)
+#define HDMA_MSI_WATERMARK_LOW_OFF (0x98)
+#define HDMA_MSI_WATERMARK_HIGH_OFF (0x9c)
+#define HDMA_MSI_ABORT_LOW_OFF (0xa0)
+#define HDMA_MSI_ABORT_HIGH_OFF (0xa4)
+#define HDMA_MSI_MSI_MSGD_OFF (0xa8)
 
 /* HDMA register val*/
-#define HDMA_EN                          (BIT(0))
-#define HDMA_DOORBELL_STOP               (BIT(1))
-#define HDMA_DOORBELL_START              (BIT(0))
-#define HDMA_TRANSFER_DONE               (0x3)
+#define HDMA_EN (BIT(0))
+#define HDMA_DOORBELL_STOP (BIT(1))
+#define HDMA_DOORBELL_START (BIT(0))
+#define HDMA_TRANSFER_DONE (0x3)
 
 /*LL module*/
-#define HDMA_LL_CONTROL_OFFSET           0x0
-#define HDMA_LL_SIZE_OFFSET              0x4
-#define HDMA_LL_SAR_LOW_OFFSET           0x8
-#define HDMA_LL_SAR_HIGH_OFFSET          0xc
-#define HDMA_LL_DAR_LOW_OFFSET           0x10
-#define HDMA_LL_DAR_HIGH_OFFSET          0x14
-#define HDMA_LL_NEXT_ELEMENT             0x18
-#define HDMA_LL_LINK_CONTROL_OFFSET      0x0
-#define HDMA_LL_LINK_EMPTY_OFFSET        0x4
-#define HDMA_LL_LINK_POINTER_LOW_OFFSET  0x8
+#define HDMA_LL_CONTROL_OFFSET 0x0
+#define HDMA_LL_SIZE_OFFSET 0x4
+#define HDMA_LL_SAR_LOW_OFFSET 0x8
+#define HDMA_LL_SAR_HIGH_OFFSET 0xc
+#define HDMA_LL_DAR_LOW_OFFSET 0x10
+#define HDMA_LL_DAR_HIGH_OFFSET 0x14
+#define HDMA_LL_NEXT_ELEMENT 0x18
+#define HDMA_LL_LINK_CONTROL_OFFSET 0x0
+#define HDMA_LL_LINK_EMPTY_OFFSET 0x4
+#define HDMA_LL_LINK_POINTER_LOW_OFFSET 0x8
 #define HDMA_LL_LINK_POINTER_HIGH_OFFSET 0xc
-#define HDMA_LL_DATA_CONTROL             0x1
-#define HDMA_LL_LINK_CONTROL             0x6
-#define HDMA_LL_PREFETCH                 0x8
-#define PF_DEPTH                         0x1f
+#define HDMA_LL_DATA_CONTROL 0x1
+#define HDMA_LL_LINK_CONTROL 0x6
+#define HDMA_LL_PREFETCH 0x8
+#define PF_DEPTH 0x1f
 
-enum hdma_mode {
-    HDMA_MODE_LEGACY = 0,
-    HDMA_MODE_SLAVE,
-    HDMA_MODE_UNROLL
-};
+enum hdma_mode { HDMA_MODE_LEGACY = 0, HDMA_MODE_SLAVE, HDMA_MODE_UNROLL };
 
 enum hdma_chan_status {
-    HDMA_CHAN_IDLE = 0,
-    HDMA_CHAN_USED,
-    HDMA_CHAN_UNDEFINE
+	HDMA_CHAN_IDLE = 0,
+	HDMA_CHAN_USED,
+	HDMA_CHAN_UNDEFINE
 };
 
 struct zf_hdma_sqe {
-    size_t length;
-    dma_addr_t src_addr;
-    dma_addr_t dst_addr;
-    struct zf_hdma_sqe *next;
+	size_t length;
+	dma_addr_t src_addr;
+	dma_addr_t dst_addr;
+	struct zf_hdma_sqe *next;
 };
 
 struct zf_hdma_tx {
-    int tx_id;
-    struct dma_async_tx_descriptor *tx_desc;
-    dma_async_tx_callback callback;
-    void *callback_param;
-    struct zf_hdma_tx *next;
+	int tx_id;
+	struct dma_async_tx_descriptor *tx_desc;
+	dma_async_tx_callback callback;
+	void *callback_param;
+	struct zf_hdma_tx *next;
 };
 
 struct hdma_ll_element {
-    size_t length;
-    dma_addr_t src_addr;
-    dma_addr_t dst_addr;
+	size_t length;
+	dma_addr_t src_addr;
+	dma_addr_t dst_addr;
 };
 
 struct zf_hdma_chan {
-    u32 id;
-    struct list_head list;
-    const char *name;
-    struct pci_dev *ep_pdev;
-    struct zxdh_virt_dma_chan zxdh_vc;
-    struct zxdh_virt_dma_desc zxdh_vd;
-    void __iomem *base_addr; // 对应HDMA寄存器基址
-    struct zf_hdma_sqe *sqe_list;
-    struct zf_hdma_tx *tx_list;
-    int is_busy;
-    u8 func_no;
-    u8 vfunc_no;
+	int id;
+	struct list_head list;
+	const char *name;
+	struct pci_dev *ep_pdev;
+	struct zxdh_virt_dma_chan zxdh_vc;
+	struct zxdh_virt_dma_desc zxdh_vd;
+	void __iomem *base_addr; // 对应HDMA寄存器基址
+	struct zf_hdma_sqe *sqe_list;
+	struct zf_hdma_tx *tx_list;
+	int is_busy;
+	u8 func_no;
+	u8 vfunc_no;
 };
 
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/virt-dma.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/virt-dma.c
index 98c516e59044f41cd349366a4c4fcbf3eb5007ca..1407290d46b2b14a8826ab026fa7e741800628ba 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/virt-dma.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/virt-dma.c
@@ -5,7 +5,8 @@
 
 #include "virt-dma.h"
 
-static struct zxdh_virt_dma_desc *zxdh_to_virt_desc(struct dma_async_tx_descriptor *tx)
+static struct zxdh_virt_dma_desc *
+zxdh_to_virt_desc(struct dma_async_tx_descriptor *tx)
 {
 	return container_of(tx, struct zxdh_virt_dma_desc, tx);
 }
@@ -23,8 +24,8 @@ dma_cookie_t zxdh_vchan_tx_submit(struct dma_async_tx_descriptor *tx)
 	list_move_tail(&zxdh_vd->node, &zxdh_vc->desc_submitted);
 	spin_unlock_irqrestore(&zxdh_vc->lock, flags);
 
-	pr_debug("%s vchan %p: txd %p[%x]: submitted\n",
-		__func__, zxdh_vc, zxdh_vd, cookie);
+	dev_dbg(zxdh_vc->chan.device->dev, "vchan %p: txd %p[%x]: submitted\n",
+			zxdh_vc, zxdh_vd, cookie);
 
 	return cookie;
 }
@@ -50,16 +51,15 @@ int zxdh_vchan_tx_desc_free(struct dma_async_tx_descriptor *tx)
 	list_del(&zxdh_vd->node);
 	spin_unlock_irqrestore(&zxdh_vc->lock, flags);
 
-	pr_debug("%s vchan %p: txd %p[%x]: freeing\n",
-		__func__, zxdh_vc, zxdh_vd, zxdh_vd->tx.cookie);
-
+	dev_dbg(zxdh_vc->chan.device->dev, "vchan %p: txd %p[%x]: freeing\n",
+			zxdh_vc, zxdh_vd, zxdh_vd->tx.cookie);
 	zxdh_vc->desc_free(zxdh_vd);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(zxdh_vchan_tx_desc_free);
 
-struct zxdh_virt_dma_desc *zxdh_vchan_find_desc(struct zxdh_virt_dma_chan *zxdh_vc,
-	dma_cookie_t cookie)
+struct zxdh_virt_dma_desc *
+zxdh_vchan_find_desc(struct zxdh_virt_dma_chan *zxdh_vc, dma_cookie_t cookie)
 {
 	struct zxdh_virt_dma_desc *zxdh_vd;
 
@@ -104,7 +104,8 @@ static void zxdh_vchan_complete(struct tasklet_struct *t)
 	}
 }
 
-void zxdh_vchan_dma_desc_free_list(struct zxdh_virt_dma_chan *zxdh_vc, struct list_head *head)
+void zxdh_vchan_dma_desc_free_list(struct zxdh_virt_dma_chan *zxdh_vc,
+								   struct list_head *head)
 {
 	struct zxdh_virt_dma_desc *zxdh_vd, *_vd;
 
@@ -115,7 +116,8 @@ void zxdh_vchan_dma_desc_free_list(struct zxdh_virt_dma_chan *zxdh_vc, struct li
 }
 EXPORT_SYMBOL_GPL(zxdh_vchan_dma_desc_free_list);
 
-void zxdh_vchan_init(struct zxdh_virt_dma_chan *zxdh_vc, struct dma_device *dmadev)
+void zxdh_vchan_init(struct zxdh_virt_dma_chan *zxdh_vc,
+					 struct dma_device *dmadev)
 {
 	zxdh_dma_cookie_init(&zxdh_vc->chan);
 
@@ -132,4 +134,3 @@ void zxdh_vchan_init(struct zxdh_virt_dma_chan *zxdh_vc, struct dma_device *dmad
 	list_add_tail(&zxdh_vc->chan.device_node, &dmadev->channels);
 }
 EXPORT_SYMBOL_GPL(zxdh_vchan_init);
-
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/virt-dma.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/virt-dma.h
index eb1ff78fc0c74965d940401085acc18efe79b24a..b3122957aeb5107eee998ffa9723c23a8c777ce3 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/virt-dma.h
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epc/virt-dma.h
@@ -14,7 +14,7 @@ struct zxdh_virt_dma_desc {
 };
 
 struct zxdh_virt_dma_chan {
-	struct dma_chan	chan;
+	struct dma_chan chan;
 	struct tasklet_struct task;
 	void (*desc_free)(struct zxdh_virt_dma_desc *);
 
@@ -30,14 +30,18 @@ struct zxdh_virt_dma_chan {
 	struct zxdh_virt_dma_desc *cyclic;
 };
 
-static inline struct zxdh_virt_dma_chan *zxdh_to_virt_chan(struct dma_chan *chan)
+static inline struct zxdh_virt_dma_chan *
+zxdh_to_virt_chan(struct dma_chan *chan)
 {
 	return container_of(chan, struct zxdh_virt_dma_chan, chan);
 }
 
-void zxdh_vchan_dma_desc_free_list(struct zxdh_virt_dma_chan *zxdh_vc, struct list_head *head);
-void zxdh_vchan_init(struct zxdh_virt_dma_chan *zxdh_vc, struct dma_device *dmadev);
-struct zxdh_virt_dma_desc *zxdh_vchan_find_desc(struct zxdh_virt_dma_chan *, dma_cookie_t);
+void zxdh_vchan_dma_desc_free_list(struct zxdh_virt_dma_chan *zxdh_vc,
+								   struct list_head *head);
+void zxdh_vchan_init(struct zxdh_virt_dma_chan *zxdh_vc,
+					 struct dma_device *dmadev);
+struct zxdh_virt_dma_desc *zxdh_vchan_find_desc(struct zxdh_virt_dma_chan *,
+												dma_cookie_t);
 extern dma_cookie_t zxdh_vchan_tx_submit(struct dma_async_tx_descriptor *);
 extern int zxdh_vchan_tx_desc_free(struct dma_async_tx_descriptor *);
 
@@ -47,8 +51,9 @@ extern int zxdh_vchan_tx_desc_free(struct dma_async_tx_descriptor *);
  * @zxdh_vd: virtual descriptor to prepare
  * @tx_flags: flags argument passed in to prepare function
  */
-static inline struct dma_async_tx_descriptor *zxdh_vchan_tx_prep(struct zxdh_virt_dma_chan *zxdh_vc,
-	struct zxdh_virt_dma_desc *zxdh_vd, unsigned long tx_flags)
+static inline struct dma_async_tx_descriptor *
+zxdh_vchan_tx_prep(struct zxdh_virt_dma_chan *zxdh_vc,
+				   struct zxdh_virt_dma_desc *zxdh_vd, unsigned long tx_flags)
 {
 	unsigned long flags;
 
@@ -85,7 +90,8 @@ static inline bool zxdh_vchan_issue_pending(struct zxdh_virt_dma_chan *zxdh_vc)
  *
  * zxdh_vc.lock must be held by caller
  */
-static inline void zxdh_vchan_cookie_complete(struct zxdh_virt_dma_desc *zxdh_vd)
+static inline void
+zxdh_vchan_cookie_complete(struct zxdh_virt_dma_desc *zxdh_vd)
 {
 	struct zxdh_virt_dma_chan *zxdh_vc = zxdh_to_virt_chan(zxdh_vd->tx.chan);
 	dma_cookie_t cookie;
@@ -93,7 +99,7 @@ static inline void zxdh_vchan_cookie_complete(struct zxdh_virt_dma_desc *zxdh_vd
 	cookie = zxdh_vd->tx.cookie;
 	zxdh_dma_cookie_complete(&zxdh_vd->tx);
 	dev_vdbg(zxdh_vc->chan.device->dev, "txd %p[%x]: marked complete\n",
-		 zxdh_vd, cookie);
+			 zxdh_vd, cookie);
 	list_add_tail(&zxdh_vd->node, &zxdh_vc->desc_completed);
 
 	tasklet_schedule(&zxdh_vc->task);
@@ -122,7 +128,8 @@ static inline void zxdh_vchan_vdesc_fini(struct zxdh_virt_dma_desc *zxdh_vd)
  * zxdh_vchan_cyclic_callback - report the completion of a period
  * @zxdh_vd: virtual descriptor
  */
-static inline void zxdh_vchan_cyclic_callback(struct zxdh_virt_dma_desc *zxdh_vd)
+static inline void
+zxdh_vchan_cyclic_callback(struct zxdh_virt_dma_desc *zxdh_vd)
 {
 	struct zxdh_virt_dma_chan *zxdh_vc = zxdh_to_virt_chan(zxdh_vd->tx.chan);
 
@@ -136,7 +143,8 @@ static inline void zxdh_vchan_cyclic_callback(struct zxdh_virt_dma_desc *zxdh_vd
  *
  * zxdh_vc.lock must be held by caller
  */
-static inline void zxdh_vchan_terminate_vdesc(struct zxdh_virt_dma_desc *zxdh_vd)
+static inline void
+zxdh_vchan_terminate_vdesc(struct zxdh_virt_dma_desc *zxdh_vd)
 {
 	struct zxdh_virt_dma_chan *zxdh_vc = zxdh_to_virt_chan(zxdh_vd->tx.chan);
 
@@ -152,10 +160,11 @@ static inline void zxdh_vchan_terminate_vdesc(struct zxdh_virt_dma_desc *zxdh_vd
  *
  * zxdh_vc.lock must be held by caller
  */
-static inline struct zxdh_virt_dma_desc *zxdh_vchan_next_desc(struct zxdh_virt_dma_chan *zxdh_vc)
+static inline struct zxdh_virt_dma_desc *
+zxdh_vchan_next_desc(struct zxdh_virt_dma_chan *zxdh_vc)
 {
 	return list_first_entry_or_null(&zxdh_vc->desc_issued,
-					struct zxdh_virt_dma_desc, node);
+									struct zxdh_virt_dma_desc, node);
 }
 
 /**
@@ -168,8 +177,9 @@ static inline struct zxdh_virt_dma_desc *zxdh_vchan_next_desc(struct zxdh_virt_d
  * Removes all submitted and issued descriptors from internal lists, and
  * provides a list of all descriptors found
  */
-static inline void zxdh_vchan_get_all_descriptors(struct zxdh_virt_dma_chan *zxdh_vc,
-	struct list_head *head)
+static inline void
+zxdh_vchan_get_all_descriptors(struct zxdh_virt_dma_chan *zxdh_vc,
+							   struct list_head *head)
 {
 	list_splice_tail_init(&zxdh_vc->desc_allocated, head);
 	list_splice_tail_init(&zxdh_vc->desc_submitted, head);
@@ -178,7 +188,8 @@ static inline void zxdh_vchan_get_all_descriptors(struct zxdh_virt_dma_chan *zxd
 	list_splice_tail_init(&zxdh_vc->desc_terminated, head);
 }
 
-static inline void zxdh_vchan_free_chan_resources(struct zxdh_virt_dma_chan *zxdh_vc)
+static inline void
+zxdh_vchan_free_chan_resources(struct zxdh_virt_dma_chan *zxdh_vc)
 {
 	struct zxdh_virt_dma_desc *zxdh_vd;
 	unsigned long flags;
@@ -194,7 +205,8 @@ static inline void zxdh_vchan_free_chan_resources(struct zxdh_virt_dma_chan *zxd
 }
 
 /**
- * zxdh_vchan_synchronize() - synchronize callback execution to the current context
+ * zxdh_vchan_synchronize() - synchronize callback execution to the current
+ * context
  * @zxdh_vc: virtual channel to synchronize
  *
  * Makes sure that all scheduled or active callbacks have finished running. For
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epf/pcie-zte-zf-epf.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epf/pcie-zte-zf-epf.c
index 8297b9352addc420db87f1d431b2882b62cda85d..a09b51b47d9944608872a0274f0ad7de79c0e190 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epf/pcie-zte-zf-epf.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epf/pcie-zte-zf-epf.c
@@ -2,455 +2,422 @@
 #include "./../epc/pcie-zte-zf-epc.h"
 
 #define EPF_MDEV_OPS 1
-#define MDEV_FOPS    1
+#define MDEV_FOPS 1
 
-extern void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, size_t align);
-extern void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar);
-extern int ep_virtio_module_set(int ep_id, int pf_idx, int en);
-extern int pcie_zte_epc_ob_read(struct pci_epc *epc, phys_addr_t phys_addr, unsigned int size, unsigned int *val);
+extern void *pci_epf_alloc_space(struct pci_epf *epf, size_t size,
+								 enum pci_barno bar, size_t align);
+extern void pci_epf_free_space(struct pci_epf *epf, void *addr,
+							   enum pci_barno bar);
 
 #if EPF_MDEV_OPS
 static int pci_epf_dev_set_pf_bar(struct pci_epf *epf)
 {
-    int bar_no = 0, add = 0;
-    int ret = 0;
-    struct pci_epf_bar *epf_bar = NULL;
-    struct pci_epc *epc = epf->epc;
-    struct device *dev = &epf->dev;
-    struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf);
-    const struct pci_epc_features *epc_features = NULL;
-
-    epc_features = epf_mdev_dev->epc_features;
-
-    for (bar_no = 0; bar_no < PCI_STD_NUM_BARS; bar_no += add)
-    {
-        epf_bar = &epf->bar[bar_no];
-        epf_bar->flags |= BIT(3);
-        add = (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ? 2 : 1;
-        if (!!(epc_features->reserved_bar & (1 << bar_no)))
-            continue;
-
-        ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no, epf_bar);
-        if (ret)
-        {
-            dev_err(dev, "Failed to set BAR%d\n", bar_no);
-        }
-    }
-
-    // set oprom bar
-    if (epf->header->pf_rom_size != 0)
-    {
-        epf->bar[BAR_ROM].phys_addr = page_to_phys(epf->header->pf_rom_page);
-        ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no, &epf->bar[BAR_ROM]);
-        if (ret)
-        {
-            dev_err(dev, "Failed to set BAR_ROM\n");
-        }
-    }
-
-    return 0;
+	int bar_no = 0, add = 0;
+	int ret = 0;
+	struct pci_epf_bar *epf_bar = NULL;
+	struct pci_epc *epc = epf->epc;
+	struct device *dev = &epf->dev;
+	struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf);
+	const struct pci_epc_features *epc_features = NULL;
+
+	epc_features = epf_mdev_dev->epc_features;
+
+	for (bar_no = 0; bar_no < PCI_STD_NUM_BARS; bar_no += add) {
+		epf_bar = &epf->bar[bar_no];
+		epf_bar->flags |= BIT(3);
+		add = (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ? 2 : 1;
+		if (!!(epc_features->reserved_bar & (1 << bar_no)))
+			continue;
+
+		ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no, epf_bar);
+		if (ret) {
+			dev_err(dev, "Failed to set BAR%d\n", bar_no);
+		}
+	}
+
+	// set oprom bar
+	if (epf->header->pf_rom_size != 0) {
+		epf->bar[BAR_ROM].phys_addr = page_to_phys(epf->header->pf_rom_page);
+		ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no,
+							  &epf->bar[BAR_ROM]);
+		if (ret) {
+			dev_err(dev, "Failed to set BAR_ROM\n");
+		}
+	}
+
+	return 0;
 }
 
 static int pci_epf_dev_set_vf_bar(struct pci_epf *epf)
 {
-    int bar_no = 0, add = 0;
-    int ret = 0;
-    struct pci_epf_bar *epf_bar;
-    struct pci_epc *epc = epf->epc;
-    struct device *dev = &epf->dev;
-    struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf);
-    const struct pci_epc_features *epc_features;
-
-    epc_features = epf_mdev_dev->epc_features;
-
-    for (bar_no = 0; bar_no < PCI_STD_NUM_BARS; bar_no += add)
-    {
-        epf_bar = &epf->epf_pf->vf_bar[bar_no];
-        epf_bar->flags |= BIT(3);
-        add = (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ? 2 : 1;
-        if (!!(epc_features->reserved_bar & (1 << bar_no)))
-            continue;
-
-        ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no, epf_bar);
-        if (ret)
-        {
-            dev_err(dev, "Failed to set BAR%d\n", bar_no);
-        }
-    }
-    return 0;
+	int bar_no = 0, add = 0;
+	int ret = 0;
+	struct pci_epf_bar *epf_bar;
+	struct pci_epc *epc = epf->epc;
+	struct device *dev = &epf->dev;
+	struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf);
+	const struct pci_epc_features *epc_features;
+
+	epc_features = epf_mdev_dev->epc_features;
+
+	for (bar_no = 0; bar_no < PCI_STD_NUM_BARS; bar_no += add) {
+		epf_bar = &epf->epf_pf->vf_bar[bar_no];
+		epf_bar->flags |= BIT(3);
+		add = (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ? 2 : 1;
+		if (!!(epc_features->reserved_bar & (1 << bar_no)))
+			continue;
+
+		ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no, epf_bar);
+		if (ret) {
+			dev_err(dev, "Failed to set BAR%d\n", bar_no);
+		}
+	}
+	return 0;
 }
 
 // 根据epf来配置epc的bar、header、msi、msi-x
 static int pci_epf_dev_core_init(struct pci_epf *epf)
 {
-    const struct pci_epc_features *epc_features;
-    struct device *dev = &epf->dev;
-    bool msix_capable = false;
-    int ret = 0;
-
-    epc_features = pci_epc_get_features(epf->epc, epf->func_no, epf->vfunc_no);
-    if (epc_features)
-    {
-        msix_capable = epc_features->msix_capable;
-    }
-
-    ret = pci_epc_write_header(epf->epc, epf->func_no, epf->vfunc_no, epf->header);
-    if (ret)
-    {
-        dev_err(dev, "Configuration header write failed\n");
-        return ret;
-    }
-
-    if (isPF(epf->func_no))
-    {
-        ret = pci_epf_dev_set_pf_bar(epf);
-    }
-    else if (epf->vfunc_no == 0)
-    {
-        ret = pci_epf_dev_set_vf_bar(epf);
-    }
-
-    return ret;
+	const struct pci_epc_features *epc_features;
+	struct device *dev = &epf->dev;
+	bool msix_capable = false;
+	int ret = 0;
+
+	epc_features = pci_epc_get_features(epf->epc, epf->func_no, epf->vfunc_no);
+	if (epc_features) {
+		msix_capable = epc_features->msix_capable;
+	}
+
+	ret = pci_epc_write_header(epf->epc, epf->func_no, epf->vfunc_no,
+							   epf->header);
+	if (ret) {
+		dev_err(dev, "Configuration header write failed\n");
+		return ret;
+	}
+
+	if (isPF(epf->func_no)) {
+		ret = pci_epf_dev_set_pf_bar(epf);
+	} else if (epf->vfunc_no == 0) {
+		ret = pci_epf_dev_set_vf_bar(epf);
+	}
+
+	return ret;
 }
 
 static int get_vf_number(struct pci_epf *epf)
 {
-    struct pcie_dpu_ep *dpu_ep = epc_get_drvdata(epf->epc);
-    int vf_total_num = 0;
-
-    if (!dpu_ep)
-    {
-        DH_LOG_ERR(MODULE_MPF, "epc is NULL!!!\n");
-        return -EINVAL;
-    }
-
-    vf_total_num = epf->func_no & PCIE_DPU_EP_GET_PF_NO;
-    if (vf_total_num >= PCIE_DPU_PF_NUMS)
-    {
-        DH_LOG_ERR(MODULE_MPF, "error vf_total_num=%d\n", vf_total_num);
-        return -EINVAL;
-    }
-    return dpu_ep->vf_total_num[vf_total_num];
+	struct pcie_dpu_ep *dpu_ep = epc_get_drvdata(epf->epc);
+
+	if (!dpu_ep) {
+		DH_LOG_ERR(MODULE_MPF, "epc is NULL!!!\n");
+		return -EINVAL;
+	}
+
+	return dpu_ep->vf_total_num[epf->func_no & PCIE_DPU_EP_GET_PF_NO];
 }
 
 // 填充pci_epf_bar结构体内容
 static int alloc_bar_space(struct pci_epf *epf)
 {
-    u16 bar_no = 0;
-    int vf_num = 0;
-    struct pci_epf_mdev_dev *epf_mdev_dev = NULL;
-
-    if (!epf)
-    {
-        DH_LOG_ERR(MODULE_MPF, "epf is NULL!\n");
-        return -EINVAL;
-    }
-    if (!epf->epc)
-    {
-        DH_LOG_ERR(MODULE_MPF, "epf->epc is NULL!\n");
-        return -EINVAL;
-    }
-
-    if (!epf->epc->ops->get_max_vfs)
-    {
-        DH_LOG_ERR(MODULE_MPF, "get_max_vfs is NULL!\n");
-        return -EINVAL;
-    }
-
-    epf_mdev_dev = epf_get_drvdata(epf);
-    vf_num = get_vf_number(epf);
-
-    if (isPF(epf->func_no))
-    {
-        epf->bar[BAR_0].size = epf->header->pf_bar0_size;
-        epf->bar[BAR_2].size = epf->header->pf_bar2_size;
-        epf->bar[BAR_4].size = epf->header->pf_bar4_size;
-    }
-    else
-    {
-        epf->epf_pf->vf_bar[4].size = epf->epf_pf->header->vf_bar4_size;
-    }
-
-    // 申请物理空间
-    for (bar_no = 0; bar_no < PCI_STD_NUM_BARS - 2; bar_no += 2)
-    {
-        epf->bar[bar_no].addr = pci_epf_alloc_space(epf, epf->bar[bar_no].size, bar_no, GFP_KERNEL);
-        if (!epf->bar[bar_no].addr)
-        {
-            DH_LOG_ERR(MODULE_MPF, "Don't have enough memory!\n");
-            return -ENOMEM;
-        }
-    }
-
-    for (bar_no = 0; bar_no < PCI_STD_NUM_BARS; bar_no += 2)
-    {
-        // PF的信息获取
-        epf->bar[bar_no].barno = bar_no;
-        epf->bar[bar_no].flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
-        if (isPF(epf->func_no))
-        {
-            // PF下的VF的信息获取
-            epf->vf_bar[bar_no].barno = bar_no;
-            epf->vf_bar[bar_no].flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
-        }
-    }
-
-    return 0;
+	u16 bar_no = 0;
+	int vf_num = 0;
+	struct pci_epf_mdev_dev *epf_mdev_dev = NULL;
+
+	if (!epf) {
+		DH_LOG_ERR(MODULE_MPF, "epf is NULL!\n");
+		return -EINVAL;
+	}
+	if (!epf->epc) {
+		DH_LOG_ERR(MODULE_MPF, "epf->epc is NULL!\n");
+		return -EINVAL;
+	}
+
+	if (!epf->epc->ops->get_max_vfs) {
+		DH_LOG_ERR(MODULE_MPF, "get_max_vfs is NULL!\n");
+		return -EINVAL;
+	}
+
+	epf_mdev_dev = epf_get_drvdata(epf);
+	vf_num = get_vf_number(epf);
+
+	if (isPF(epf->func_no)) {
+		epf->bar[BAR_0].size = epf->header->pf_bar0_size;
+		epf->bar[BAR_2].size = epf->header->pf_bar2_size;
+		epf->bar[BAR_4].size = epf->header->pf_bar4_size;
+	} else {
+		epf->epf_pf->vf_bar[4].size = epf->epf_pf->header->vf_bar4_size;
+	}
+
+	// 申请物理空间
+	for (bar_no = 0; bar_no < PCI_STD_NUM_BARS - 2; bar_no += 2) {
+		epf->bar[bar_no].addr = pci_epf_alloc_space(epf, epf->bar[bar_no].size,
+													bar_no, GFP_KERNEL);
+		if (!epf->bar[bar_no].addr) {
+			DH_LOG_ERR(MODULE_MPF, "Don't have enough memory!\n");
+			return -ENOMEM;
+		}
+	}
+
+	for (bar_no = 0; bar_no < PCI_STD_NUM_BARS; bar_no += 2) {
+		// PF的信息获取
+		epf->bar[bar_no].barno = bar_no;
+		epf->bar[bar_no].flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
+		if (isPF(epf->func_no)) {
+			// PF下的VF的信息获取
+			epf->vf_bar[bar_no].barno = bar_no;
+			epf->vf_bar[bar_no].flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
+		}
+	}
+
+	return 0;
 }
 
 static void pci_epf_mdev_unbind(struct pci_epf *epf)
 {
-    int bar_no = 0;
-    struct pci_epc *epc = epf->epc;
-
-    DH_LOG_ERR(MODULE_MPF, "pf = 0x%x, vf = 0x%x\n", epf->func_no, epf->vfunc_no);
-    if (epf->vfunc_no == 0)
-    {
-        for (bar_no = 0; bar_no < PCI_STD_NUM_BARS - 2; bar_no += 2)
-        {
-            pci_epf_free_space(epf, epf->bar[bar_no].addr, bar_no);
-        }
-    }
-
-    if (isPF(epf->func_no))
-    {
-        clear_bit(epf->func_no, &epc->function_num_map);
-    }
+	int bar_no = 0;
+	struct pci_epc *epc = epf->epc;
+
+	DH_LOG_ERR(MODULE_MPF, "pf = 0x%x, vf = 0x%x\n", epf->func_no,
+			   epf->vfunc_no);
+	if (epf->vfunc_no == 0) {
+		for (bar_no = 0; bar_no < PCI_STD_NUM_BARS - 2; bar_no += 2) {
+			pci_epf_free_space(epf, epf->bar[bar_no].addr, bar_no);
+		}
+	}
+
+	if (isPF(epf->func_no)) {
+		clear_bit(epf->func_no, &epc->function_num_map);
+	}
 }
 
 static int pci_epf_mdev_bind(struct pci_epf *epf)
 {
-    int ret = 0;
-    struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf);
-    const struct pci_epc_features *epc_features = NULL;
-    struct pci_epc *epc = epf->epc;
-    bool linkup_notifier = false;
-    bool core_init_notifier = false;
-
-    if (!epc)
-    {
-        DH_LOG_ERR(MODULE_MPF, "epc is NULL!!!\n");
-        return -EINVAL;
-    }
-
-    if (isPF(epf->func_no))
-    {
-        epf->is_vf = PCI_EPF_SRIOV_PF;
-    }
-    else
-    {
-        epf->is_vf = PCI_EPF_SRIOV_VF;
-    }
-
-    ret = alloc_bar_space(epf);
-    if (ret)
-    {
-        DH_LOG_ERR(MODULE_MPF, "Alloc bar sapce error!\n");
-        return ret;
-    }
-
-    epc_features = pci_epc_get_features(epc, epf->func_no, epf->vfunc_no);
-    if (!epc_features)
-    {
-        dev_err(&epf->dev, "epc_features not implemented\n");
-        return -EOPNOTSUPP;
-    }
-
-    linkup_notifier = epc_features->linkup_notifier;
-    core_init_notifier = epc_features->core_init_notifier;
-    epf_mdev_dev->epc_features = epc_features;
-    if (!core_init_notifier)
-    {
-        ret = pci_epf_dev_core_init(epf);
-        if (ret)
-        {
-            return ret;
-        }
-    }
-
-    return 0;
+	int ret = 0;
+	struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf);
+	const struct pci_epc_features *epc_features = NULL;
+	struct pci_epc *epc = epf->epc;
+	bool linkup_notifier = false;
+	bool core_init_notifier = false;
+
+	if (!epc) {
+		DH_LOG_ERR(MODULE_MPF, "epc is NULL!!!\n");
+		return -EINVAL;
+	}
+
+	if (isPF(epf->func_no)) {
+		epf->is_vf = PCI_EPF_SRIOV_PF;
+	} else {
+		epf->is_vf = PCI_EPF_SRIOV_VF;
+	}
+
+	ret = alloc_bar_space(epf);
+	if (ret) {
+		DH_LOG_ERR(MODULE_MPF, "Alloc bar sapce error!\n");
+		return ret;
+	}
+
+	epc_features = pci_epc_get_features(epc, epf->func_no, epf->vfunc_no);
+	if (!epc_features) {
+		dev_err(&epf->dev, "epc_features not implemented\n");
+		return -EOPNOTSUPP;
+	}
+
+	linkup_notifier = epc_features->linkup_notifier;
+	core_init_notifier = epc_features->core_init_notifier;
+	epf_mdev_dev->epc_features = epc_features;
+	if (!core_init_notifier) {
+		ret = pci_epf_dev_core_init(epf);
+		if (ret) {
+			return ret;
+		}
+	}
+
+	return 0;
 }
 
 static const struct pci_epf_device_id pci_epf_dev_ids[] = {
-    {
-     .name = "pci-epf-mdev",
-     },
-    {},
+	{
+			.name = "pci-epf-mdev",
+	},
+	{},
 };
 
 static struct pci_epf_ops epf_mdev_ops = {
-    .unbind = pci_epf_mdev_unbind,
-    .bind = pci_epf_mdev_bind,
+	.unbind = pci_epf_mdev_unbind,
+	.bind = pci_epf_mdev_bind,
 };
 #endif
 
 #if MDEV_FOPS
 // sample_pci_mdev_dev_show
-static ssize_t sample_pci_mdev_dev_show(struct device *dev, struct device_attribute *attr, char *buf)
+static ssize_t sample_pci_mdev_dev_show(struct device *dev,
+										struct device_attribute *attr,
+										char *buf)
 {
-    return sprintf(buf, "This is pci-epf-mdev device\n");
+	return sprintf(buf, "This is pci-epf-mdev device\n");
 }
 static DEVICE_ATTR_RO(sample_pci_mdev_dev);
 
 static struct attribute *pci_mdev_dev_attrs[] = {
-    &dev_attr_sample_pci_mdev_dev.attr,
-    NULL,
+	&dev_attr_sample_pci_mdev_dev.attr,
+	NULL,
 };
 
 static const struct attribute_group pci_mdev_dev_group = {
-    .name = "pcie_mdev_dev",
-    .attrs = pci_mdev_dev_attrs,
+	.name = "pcie_mdev_dev",
+	.attrs = pci_mdev_dev_attrs,
 };
 
 static const struct attribute_group *pci_mdev_dev_groups[] = {
-    &pci_mdev_dev_group,
-    NULL,
+	&pci_mdev_dev_group,
+	NULL,
 };
 
 // sample_mdev_dev_show
-static ssize_t sample_mdev_dev_show(struct device *dev, struct device_attribute *attr, char *buf)
+static ssize_t sample_mdev_dev_show(struct device *dev,
+									struct device_attribute *attr, char *buf)
 {
-    if (mdev_from_dev(dev))
-        return sprintf(buf, "This is MDEV %s\n", dev_name(dev));
+	if (mdev_from_dev(dev))
+		return sprintf(buf, "This is MDEV %s\n", dev_name(dev));
 
-    return sprintf(buf, "\n");
+	return sprintf(buf, "\n");
 }
 
 static DEVICE_ATTR_RO(sample_mdev_dev);
 
 static struct attribute *mdev_dev_attrs[] = {
-    &dev_attr_sample_mdev_dev.attr,
-    NULL,
+	&dev_attr_sample_mdev_dev.attr,
+	NULL,
 };
 
 static const struct attribute_group mdev_dev_group = {
-    .name = "vendor",
-    .attrs = mdev_dev_attrs,
+	.name = "vendor",
+	.attrs = mdev_dev_attrs,
 };
 
 static const struct attribute_group *mdev_dev_groups[] = {
-    &mdev_dev_group,
-    NULL,
+	&mdev_dev_group,
+	NULL,
 };
 
 // name_show +++ device_api_show
 static ssize_t name_show(struct mdev_type *mtype,
-                         struct mdev_type_attribute *attr, char *buf)
+						 struct mdev_type_attribute *attr, char *buf)
 {
-    const char *name_str = {"ZTE epf mdev"};
-    return sysfs_emit(buf, "%s\n", name_str);
+	const char *name_str = { "ZTE epf mdev" };
+	return sysfs_emit(buf, "%s\n", name_str);
 }
 static MDEV_TYPE_ATTR_RO(name);
 
 static ssize_t device_api_show(struct mdev_type *mtype,
-                               struct mdev_type_attribute *attr, char *buf)
+							   struct mdev_type_attribute *attr, char *buf)
 {
-    return sprintf(buf, "%s\n", VFIO_DEVICE_API_PCI_STRING);
+	return sprintf(buf, "%s\n", VFIO_DEVICE_API_PCI_STRING);
 }
 
 static MDEV_TYPE_ATTR_RO(device_api);
 
 static struct attribute *mdev_types_attrs[] = {
-    &mdev_type_attr_name.attr,
-    &mdev_type_attr_device_api.attr,
-    NULL,
+	&mdev_type_attr_name.attr,
+	&mdev_type_attr_device_api.attr,
+	NULL,
 };
 
 static struct attribute_group mdev_type_group = {
-    .name = "single",
-    .attrs = mdev_types_attrs,
+	.name = "single",
+	.attrs = mdev_types_attrs,
 };
 
 static struct attribute_group *mdev_type_groups[] = {
-    &mdev_type_group,
-    NULL,
+	&mdev_type_group,
+	NULL,
 };
 
 static int pci_mdev_create(struct mdev_device *mdev)
 {
-    struct mdev_state *mdev_state = NULL;
-    struct device *dev = mdev->type->parent->dev;
-    struct pci_epf *epf = container_of(dev, struct pci_epf, dev);
-    struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf);
-    int ret = 0;
-
-    if (epf_mdev_dev->created_flag == 1)
-    {
-        DH_LOG_ERR(MODULE_MPF, "This mdev has been created!!!\n");
-        return -EPERM;
-    }
-
-    mdev_state = kzalloc(sizeof(struct mdev_state), GFP_KERNEL);
-    if (!mdev_state)
-    {
-        return -ENOMEM;
-    }
-
-    mdev_state->irq_index = -1;
-    mdev_state->epf_mdev_dev = epf_mdev_dev;
-    mdev_state->mdev = mdev;
-    mutex_init(&mdev_state->ops_lock);
-    mutex_init(&mdev_state->ioeventfds_lock);
-    INIT_LIST_HEAD(&mdev_state->ioeventfds_list);
-
-    mdev_set_drvdata(mdev, mdev_state);
-
-    epf_mdev_dev->created_flag = 1;
-
-    return ret;
+	struct mdev_state *mdev_state = NULL;
+	struct device *dev = mdev->type->parent->dev;
+	struct pci_epf *epf = container_of(dev, struct pci_epf, dev);
+	struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf);
+	int ret = 0;
+
+	if (epf_mdev_dev->created_flag == 1) {
+		DH_LOG_ERR(MODULE_MPF, "This mdev has been created!!!\n");
+		return -EPERM;
+	}
+
+	mdev_state = kzalloc(sizeof(struct mdev_state), GFP_KERNEL);
+	if (!mdev_state) {
+		return -ENOMEM;
+	}
+
+	mdev_state->irq_index = -1;
+	mdev_state->epf_mdev_dev = epf_mdev_dev;
+	mdev_state->mdev = mdev;
+	mutex_init(&mdev_state->ops_lock);
+	mutex_init(&mdev_state->ioeventfds_lock);
+	INIT_LIST_HEAD(&mdev_state->ioeventfds_list);
+
+	mdev_set_drvdata(mdev, mdev_state);
+
+	epf_mdev_dev->created_flag = 1;
+
+	return ret;
 }
 
 static int pci_mdev_remove(struct mdev_device *mdev)
 {
-    int ret = 0;
-    // int bar_no = 0;
-    struct mdev_state *mdev_state = NULL;
-    struct epf_mdev_ioeventfd *ioeventfd = NULL, *temp = NULL;
-    struct device *dev = NULL;
-    struct pci_epf *epf = NULL;
-    struct pci_epf_mdev_dev *epf_mdev_dev = NULL;
-
-    mdev_state = mdev_get_drvdata(mdev);
-    if (!mdev_state)
-    {
-        DH_LOG_ERR(MODULE_MPF, "mdev_state NULL\n");
-        return 0;
-    }
-    dev = mdev->type->parent->dev;
-    if (!dev)
-    {
-        DH_LOG_ERR(MODULE_MPF, "dev NULL\n");
-        return 0;
-    }
-    epf = container_of(dev, struct pci_epf, dev);
-    epf_mdev_dev = epf_get_drvdata(epf);
-    if (epf_mdev_dev == NULL)
-    {
-        DH_LOG_ERR(MODULE_MPF, "epf_mdev_dev NULL\n");
-        return 0;
-    }
-
-    mutex_lock(&mdev_state->ioeventfds_lock);
-    list_for_each_entry_safe(ioeventfd, temp, &mdev_state->ioeventfds_list, next)
-    {
-        vfio_virqfd_disable(&ioeventfd->virqfd);
-        list_del(&ioeventfd->next);
-        mdev_state->ioeventfds_nr--;
-        kfree(ioeventfd);
-    }
-    mutex_unlock(&mdev_state->ioeventfds_lock);
-    mutex_destroy(&mdev_state->ioeventfds_lock);
-    mutex_destroy(&mdev_state->ops_lock);
-    kfree(mdev_state); // todo LJP
-
-    epf_mdev_dev->created_flag = 0;
-
-    return ret;
+	int ret = 0;
+	// int bar_no = 0;
+	struct mdev_state *mdev_state = NULL;
+	struct epf_mdev_ioeventfd *ioeventfd = NULL, *temp = NULL;
+	struct device *dev = NULL;
+	struct pci_epf *epf = NULL;
+	struct pci_epf_mdev_dev *epf_mdev_dev = NULL;
+
+	mdev_state = mdev_get_drvdata(mdev);
+	if (!mdev_state) {
+		DH_LOG_ERR(MODULE_MPF, "mdev_state NULL\n");
+		return 0;
+	}
+	dev = mdev->type->parent->dev;
+	if (!dev) {
+		DH_LOG_ERR(MODULE_MPF, "dev NULL\n");
+		return 0;
+	}
+	epf = container_of(dev, struct pci_epf, dev);
+	if (!epf) {
+		DH_LOG_ERR(MODULE_MPF, "epf NULL\n");
+		return 0;
+	}
+	epf_mdev_dev = epf_get_drvdata(epf);
+	if (!epf_mdev_dev) {
+		DH_LOG_ERR(MODULE_MPF, "epf_mdev_dev NULL\n");
+		return 0;
+	}
+
+	if (mdev_state) {
+		mutex_lock(&mdev_state->ioeventfds_lock);
+		list_for_each_entry_safe(ioeventfd, temp, &mdev_state->ioeventfds_list,
+								 next) {
+			vfio_virqfd_disable(&ioeventfd->virqfd);
+			list_del(&ioeventfd->next);
+			mdev_state->ioeventfds_nr--;
+			kfree(ioeventfd);
+		}
+		mutex_unlock(&mdev_state->ioeventfds_lock);
+		mutex_destroy(&mdev_state->ioeventfds_lock);
+		mutex_destroy(&mdev_state->ops_lock);
+		kfree(mdev_state);
+	}
+	epf_mdev_dev->created_flag = 0;
+
+	return ret;
 }
 
 static int pci_mdev_open(struct mdev_device *mdev)
 {
-    return 0;
+	return 0;
 }
 
 static void pci_mdev_close(struct mdev_device *mdev)
@@ -458,564 +425,545 @@ static void pci_mdev_close(struct mdev_device *mdev)
 }
 
 static ssize_t pci_mdev_read(struct mdev_device *mdev, char __user *buf,
-                             size_t count, loff_t *ppos)
+							 size_t count, loff_t *ppos)
 {
-    int ret = 0;
+	int ret = 0;
 
-    return ret;
+	return ret;
 }
 
 static ssize_t pci_mdev_write(struct mdev_device *mdev, const char __user *buf,
-                              size_t count, loff_t *ppos)
+							  size_t count, loff_t *ppos)
 {
-    int ret = 0;
-    struct mdev_state *mdev_state = mdev_get_drvdata(mdev);
+	int ret = 0;
+	struct mdev_state *mdev_state = mdev_get_drvdata(mdev);
 
-    if (!mdev_state)
-    {
-        DH_LOG_ERR(MODULE_MPF, "mdev_state is NULL!!!\n");
-        return -EINVAL;
-    }
+	if (!mdev_state) {
+		DH_LOG_ERR(MODULE_MPF, "mdev_state is NULL!!!\n");
+		return -EINVAL;
+	}
 
-    return ret;
+	return ret;
 }
 
 static int pci_mdev_mmap(struct mdev_device *mdev, struct vm_area_struct *vma)
 {
-    struct device *dev = mdev->type->parent->dev;
-    struct pci_epf *epf = container_of(dev, struct pci_epf, dev);
-    struct pci_epc *epc = epf->epc;
-    // struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf);
-    int ret = 0;
-    int bar_no = vma->vm_pgoff;
-
-    if (!epc)
-    {
-        DH_LOG_ERR(MODULE_MPF, "epc is NULL!!!\n");
-    }
-
-    if (vma->vm_end < vma->vm_start)
-    {
-        goto parameter_error;
-    }
-
-    if (vma->vm_end - vma->vm_start > epf->bar[bar_no].size)
-    {
-        goto parameter_error;
-    }
-
-    if ((vma->vm_flags & VM_SHARED) == 0)
-    {
-        goto parameter_error;
-    }
-
-    ret = remap_vmalloc_range_partial(vma, vma->vm_start, epf->bar[bar_no].addr, 0, vma->vm_end - vma->vm_start);
-
-    if (ret)
-    {
-        DH_LOG_ERR(MODULE_MPF, "remap_vmalloc_range_partial error!!!\n");
-    }
-
-    return ret;
+	struct device *dev = mdev->type->parent->dev;
+	struct pci_epf *epf = container_of(dev, struct pci_epf, dev);
+	struct pci_epc *epc = epf->epc;
+	// struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf);
+	int ret = 0;
+	int bar_no = vma->vm_pgoff;
+
+	if (!epc) {
+		DH_LOG_ERR(MODULE_MPF, "epc is NULL!!!\n");
+	}
+
+	if (vma->vm_end < vma->vm_start) {
+		goto parameter_error;
+	}
+
+	if (vma->vm_end - vma->vm_start > epf->bar[bar_no].size) {
+		goto parameter_error;
+	}
+
+	if ((vma->vm_flags & VM_SHARED) == 0) {
+		goto parameter_error;
+	}
+
+	ret = remap_vmalloc_range_partial(vma, vma->vm_start, epf->bar[bar_no].addr,
+									  0, vma->vm_end - vma->vm_start);
+
+	if (ret) {
+		DH_LOG_ERR(MODULE_MPF, "remap_vmalloc_range_partial error!!!\n");
+	}
+
+	return ret;
 
 parameter_error:
-    DH_LOG_ERR(MODULE_MPF, "vm area parameter error!!!\n");
-    return -EINVAL;
+	DH_LOG_ERR(MODULE_MPF, "vm area parameter error!!!\n");
+	return -EINVAL;
 }
 
 #if 1 // ioctl
-static int zte_get_device_info(struct mdev_device *mdev, struct vfio_device_info *dev_info)
+static int zte_get_device_info(struct mdev_device *mdev,
+							   struct vfio_device_info *dev_info)
 {
-    dev_info->flags = VFIO_DEVICE_FLAGS_PCI;
-    dev_info->num_regions = VFIO_PCI_NUM_REGIONS;
-    dev_info->num_irqs = VFIO_PCI_NUM_IRQS;
+	dev_info->flags = VFIO_DEVICE_FLAGS_PCI;
+	dev_info->num_regions = VFIO_PCI_NUM_REGIONS;
+	dev_info->num_irqs = VFIO_PCI_NUM_IRQS;
 
-    return 0;
+	return 0;
 }
 
-static int zte_get_region_info(struct mdev_device *mdev, struct vfio_region_info *region_info)
+static int zte_get_region_info(struct mdev_device *mdev,
+							   struct vfio_region_info *region_info)
 {
-    struct mdev_state *mdev_state = NULL;
-    struct device *dev = mdev->type->parent->dev;
-    struct pci_epf *epf = container_of(dev, struct pci_epf, dev);
-    int bar_no = 0;
-    int bar_size = 0;
-
-    mdev_state = mdev_get_drvdata(mdev);
-    if (!mdev_state)
-    {
-        return -EINVAL;
-    }
-
-    bar_no = region_info->index;
-    if (bar_no >= VFIO_PCI_BAR5_REGION_INDEX)
-    {
-        DH_LOG_ERR(MODULE_MPF, "bar index invaild!\n");
-        return -EINVAL;
-    }
-
-    mutex_lock(&mdev_state->ops_lock);
-
-    if (bar_no == VFIO_PCI_BAR0_REGION_INDEX || bar_no == VFIO_PCI_BAR2_REGION_INDEX || bar_no == VFIO_PCI_BAR4_REGION_INDEX)
-    {
-        bar_size = epf->bar[bar_no].size;
-    }
-    else
-    {
-        DH_LOG_ERR(MODULE_MPF, "bar index invaild!\n");
-        return -EINVAL;
-    }
-
-    mdev_state->region_info[bar_no].size = bar_size;
-
-    region_info->offset = (bar_no << 12);
-    region_info->size = bar_size;
-    region_info->flags = VFIO_REGION_INFO_FLAG_READ | VFIO_REGION_INFO_FLAG_WRITE;
-    mutex_unlock(&mdev_state->ops_lock);
-    return 0;
+	struct mdev_state *mdev_state = NULL;
+	struct device *dev = mdev->type->parent->dev;
+	struct pci_epf *epf = container_of(dev, struct pci_epf, dev);
+	int bar_no = 0;
+	int bar_size = 0;
+
+	mdev_state = mdev_get_drvdata(mdev);
+	if (!mdev_state) {
+		return -EINVAL;
+	}
+
+	bar_no = region_info->index;
+	if (bar_no >= VFIO_PCI_BAR5_REGION_INDEX) {
+		DH_LOG_ERR(MODULE_MPF, "bar index invaild!\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&mdev_state->ops_lock);
+
+	if (bar_no == VFIO_PCI_BAR0_REGION_INDEX ||
+		bar_no == VFIO_PCI_BAR2_REGION_INDEX ||
+		bar_no == VFIO_PCI_BAR4_REGION_INDEX) {
+		bar_size = epf->bar[bar_no].size;
+	} else {
+		DH_LOG_ERR(MODULE_MPF, "bar index invaild!\n");
+		return -EINVAL;
+	}
+
+	mdev_state->region_info[bar_no].size = bar_size;
+
+	region_info->offset = (bar_no << 12);
+	region_info->size = bar_size;
+	region_info->flags = VFIO_REGION_INFO_FLAG_READ |
+						 VFIO_REGION_INFO_FLAG_WRITE;
+	mutex_unlock(&mdev_state->ops_lock);
+	return 0;
 }
 
-static void __attribute__((unused)) epf_mdev_ioeventfd_thread(void *opaque, void *unused)
+static void epf_mdev_ioeventfd_thread(void *opaque, void *unused)
 {
-    // 打桩
+	// 打桩
 }
 
 int epf_mdev_ioeventfd_handler(void *opaque, void *unused)
 {
-    int ret = 0;
-    struct epf_mdev_ioeventfd *ioeventfd = opaque;
-    struct mdev_state *mdev_state = ioeventfd->mdev_state;
-    struct pci_epf_mdev_dev *epf_mdev_dev = mdev_state->epf_mdev_dev;
-    struct pci_epf *epf = epf_mdev_dev->epf;
-    struct pci_epc *epc = epf->epc;
-    enum pci_epc_irq_type irq_type = PCI_EPC_IRQ_MSIX;
-
-    pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, irq_type, ioeventfd->offset + 1);
-    return ret;
+	int ret = 0;
+	struct epf_mdev_ioeventfd *ioeventfd = opaque;
+	struct mdev_state *mdev_state = ioeventfd->mdev_state;
+	struct pci_epf_mdev_dev *epf_mdev_dev = mdev_state->epf_mdev_dev;
+	struct pci_epf *epf = epf_mdev_dev->epf;
+	struct pci_epc *epc = epf->epc;
+	enum pci_epc_irq_type irq_type = PCI_EPC_IRQ_MSIX;
+
+	pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, irq_type,
+					  ioeventfd->offset + 1);
+	return ret;
 }
 
-#if 0
-int epf_mdev_ioeventfd_func(struct mdev_state *mdev_state, loff_t offset, u64 data, int count, int fd)
+int epf_mdev_ioeventfd(struct mdev_state *mdev_state, loff_t offset, u64 data,
+					   int count, int fd)
 {
-    int ret = 0;
-    struct epf_mdev_ioeventfd *ioeventfd = NULL, *temp = NULL;
+	int ret = 0;
+	struct epf_mdev_ioeventfd *ioeventfd = NULL, *temp = NULL;
 
 #ifndef iowrite64
-    if (count == 8)
-        return -EINVAL;
+	if (count == 8)
+		return -EINVAL;
 #endif
 
-    mutex_lock(&mdev_state->ioeventfds_lock);
-    list_for_each_entry_safe(ioeventfd, temp, &mdev_state->ioeventfds_list, next)
-    {
-        if (ioeventfd->offset == offset)
-        {
-            if (fd == -1 || data == 0)
-            {
-                vfio_virqfd_disable(&ioeventfd->virqfd);
-                list_del(&ioeventfd->next);
-                mdev_state->ioeventfds_nr--;
-                kfree(ioeventfd);
-                ret = 0;
-            }
-            else if (data == 1)
-            {
-                vfio_virqfd_disable(&ioeventfd->virqfd);
-                list_del(&ioeventfd->next);
-                mdev_state->ioeventfds_nr--;
-                kfree(ioeventfd);
-                goto eventfds_set;
-            }
-            else
-            {
-                ret = -EEXIST;
-            }
-
-            goto out_unlock;
-        }
-    }
-
-    if (fd < 0)
-    {
-        ret = -ENODEV;
-        goto out_unlock;
-    }
-
-    if (mdev_state->ioeventfds_nr >= EPF_MDEV_IOEVENTFD_MAX)
-    {
-        ret = -ENOSPC;
-        goto out_unlock;
-    }
+	mutex_lock(&mdev_state->ioeventfds_lock);
+	list_for_each_entry_safe(ioeventfd, temp, &mdev_state->ioeventfds_list,
+							 next) {
+		if (ioeventfd->offset == offset) {
+			if (fd == -1 || data == 0) {
+				vfio_virqfd_disable(&ioeventfd->virqfd);
+				list_del(&ioeventfd->next);
+				mdev_state->ioeventfds_nr--;
+				kfree(ioeventfd);
+				ret = 0;
+			} else if (data == 1) {
+				vfio_virqfd_disable(&ioeventfd->virqfd);
+				list_del(&ioeventfd->next);
+				mdev_state->ioeventfds_nr--;
+				kfree(ioeventfd);
+				goto eventfds_set;
+			} else {
+				ret = -EEXIST;
+			}
+
+			goto out_unlock;
+		}
+	}
+
+	if (fd < 0) {
+		ret = -ENODEV;
+		goto out_unlock;
+	}
+
+	if (mdev_state->ioeventfds_nr >= EPF_MDEV_IOEVENTFD_MAX) {
+		ret = -ENOSPC;
+		goto out_unlock;
+	}
 
 eventfds_set:
-    ioeventfd = kzalloc(sizeof(*ioeventfd), GFP_KERNEL);
-    if (!ioeventfd)
-    {
-        ret = -ENOMEM;
-        goto out_unlock;
-    }
-
-    ioeventfd->mdev_state = mdev_state;
-    ioeventfd->data = data;
-    ioeventfd->offset = offset;
-    ioeventfd->count = count;
-
-    ret = vfio_virqfd_enable(ioeventfd, epf_mdev_ioeventfd_handler,
-                             epf_mdev_ioeventfd_thread, NULL,
-                             &ioeventfd->virqfd, fd);
-    if (ret)
-    {
-        kfree(ioeventfd);
-        goto out_unlock;
-    }
-
-    list_add(&ioeventfd->next, &mdev_state->ioeventfds_list);
-    mdev_state->ioeventfds_nr++;
+	ioeventfd = kzalloc(sizeof(*ioeventfd), GFP_KERNEL);
+	if (!ioeventfd) {
+		ret = -ENOMEM;
+		goto out_unlock;
+	}
+
+	ioeventfd->mdev_state = mdev_state;
+	ioeventfd->data = data;
+	ioeventfd->offset = offset;
+	ioeventfd->count = count;
+
+	ret = vfio_virqfd_enable(ioeventfd, epf_mdev_ioeventfd_handler,
+							 epf_mdev_ioeventfd_thread, NULL,
+							 &ioeventfd->virqfd, fd);
+	if (ret) {
+		kfree(ioeventfd);
+		goto out_unlock;
+	}
+
+	list_add(&ioeventfd->next, &mdev_state->ioeventfds_list);
+	mdev_state->ioeventfds_nr++;
 
 out_unlock:
-    mutex_unlock(&mdev_state->ioeventfds_lock);
+	mutex_unlock(&mdev_state->ioeventfds_lock);
 
-    return ret;
+	return ret;
 }
-#endif
 
-static int device_get_info(struct mdev_device *mdev, struct mdev_state *mdev_state, unsigned long arg)
+static int device_get_info(struct mdev_device *mdev,
+						   struct mdev_state *mdev_state, unsigned long arg)
 {
-    unsigned long minsz = 0;
-    struct vfio_device_info info = {0};
-
-    minsz = offsetofend(struct vfio_device_info, num_irqs);
-    if (copy_from_user(&info, (void __user *)arg, minsz))
-    {
-        return -EFAULT;
-    }
-
-    if (info.argsz < minsz)
-    {
-        return -EINVAL;
-    }
-
-    zte_get_device_info(mdev, &info);
-
-    memcpy(&mdev_state->dev_info, &info, sizeof(info));
-    if (copy_to_user((void __user *)arg, &info, minsz))
-        return -EFAULT;
-    return 0;
+	unsigned long minsz = 0;
+	struct vfio_device_info info = { 0 };
+	int ret = 0;
+
+	minsz = offsetofend(struct vfio_device_info, num_irqs);
+	if (copy_from_user(&info, (void __user *)arg, minsz)) {
+		return -EFAULT;
+	}
+
+	if (info.argsz < minsz) {
+		return -EINVAL;
+	}
+
+	ret = zte_get_device_info(mdev, &info);
+	if (ret)
+		return ret;
+
+	memcpy(&mdev_state->dev_info, &info, sizeof(info));
+	if (copy_to_user((void __user *)arg, &info, minsz))
+		return -EFAULT;
+	return 0;
 }
 
-static int device_get_region_info(struct mdev_device *mdev, struct mdev_state *mdev_state, unsigned long arg)
+static int device_get_region_info(struct mdev_device *mdev,
+								  struct mdev_state *mdev_state,
+								  unsigned long arg)
 {
-    struct vfio_region_info info = {0};
-    unsigned long minsz = 0;
-    int ret = 0;
+	struct vfio_region_info info = { 0 };
+	unsigned long minsz = 0;
+	int ret = 0;
 
-    minsz = offsetofend(struct vfio_region_info, offset);
-    if (copy_from_user(&info, (void __user *)arg, minsz))
-        return -EFAULT;
+	minsz = offsetofend(struct vfio_region_info, offset);
+	if (copy_from_user(&info, (void __user *)arg, minsz))
+		return -EFAULT;
 
-    if (info.argsz < minsz)
-        return -EINVAL;
+	if (info.argsz < minsz)
+		return -EINVAL;
 
-    ret = zte_get_region_info(mdev, &info);
-    if (ret)
-        return ret;
+	ret = zte_get_region_info(mdev, &info);
+	if (ret)
+		return ret;
 
-    if (copy_to_user((void __user *)arg, &info, minsz))
-    {
-        return -EFAULT;
-    }
+	if (copy_to_user((void __user *)arg, &info, minsz)) {
+		return -EFAULT;
+	}
 
-    return 0;
+	return 0;
 }
 
-static int vfio_device_ioeventfd(struct mdev_device *mdev, struct mdev_state *mdev_state, unsigned long arg)
+static int vfio_device_ioeventfd(struct mdev_device *mdev,
+								 struct mdev_state *mdev_state,
+								 unsigned long arg)
 {
-    struct vfio_device_ioeventfd ioeventfd = {0};
-    int ret = 0;
-    int count = 0;
-    unsigned long minsz = 0;
-    struct pci_epf_mdev_dev *epf_mdev_dev = mdev_state->epf_mdev_dev;
-    struct pci_epf *epf = epf_mdev_dev->epf;
-
-    minsz = offsetofend(struct vfio_device_ioeventfd, fd);
-    if (copy_from_user(&ioeventfd, (void __user *)arg, minsz))
-    {
-        DH_LOG_ERR(MODULE_MPF, "copy from user failed! minsz=0x%lx\n", minsz);
-        return -EFAULT;
-    }
-
-    DH_LOG_INFO(MODULE_MPF, "func = 0x%x, vfunc_no = 0x%x, offset = 0x%llx, data = 0x%llx, minsz=0x%lx\n", epf->func_no, epf->vfunc_no, ioeventfd.offset, ioeventfd.data, minsz);
-    if (ioeventfd.argsz < minsz)
-    {
-        return -EINVAL;
-    }
-
-    if (ioeventfd.flags & ~VFIO_DEVICE_IOEVENTFD_SIZE_MASK)
-    {
-        return -EINVAL;
-    }
-
-    count = ioeventfd.flags & VFIO_DEVICE_IOEVENTFD_SIZE_MASK;
-
-    if (hweight8(count) != 1 || ioeventfd.fd < -1)
-        return -EINVAL;
-
-    // ret = epf_mdev_ioeventfd_func(mdev_state, (loff_t)ioeventfd.offset, (u64)ioeventfd.data, count, (int)ioeventfd.fd);
-    DH_LOG_ERR(MODULE_MPF, "error: epf_mdev_ioeventfd_func not called!\n");
-    return ret;
-}
+	struct vfio_device_ioeventfd ioeventfd = { 0 };
+	int count = 0;
+	unsigned long minsz = 0;
+	struct pci_epf_mdev_dev *epf_mdev_dev = mdev_state->epf_mdev_dev;
+	struct pci_epf *epf = epf_mdev_dev->epf;
 
-static int vfio_outbound_set(struct mdev_device *mdev, struct mdev_state *mdev_state, unsigned long arg)
-{
-    int ret = 0;
-    struct pci_epf_mdev_dev *epf_mdev_dev = mdev_state->epf_mdev_dev;
-    struct pci_epf *epf = epf_mdev_dev->epf;
-    struct pci_epc *epc = epf->epc;
-    struct ioctl_ob_data ob = {0};
-    void __iomem *dst_addr = NULL;
-    phys_addr_t dst_phys_addr = 0;
-
-    if (copy_from_user(&ob, (void *)arg, sizeof(struct ioctl_ob_data)))
-    {
-        DH_LOG_ERR(MODULE_MPF, "err:copy_from_user failed!\n");
-        return -EFAULT;
-    }
-    DH_LOG_INFO(MODULE_MPF, "ob->host = 0x%llx, ob->size = 0x%lxs\n", ob.host_addr, ob.size);
-
-    dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, ob.size);
-    if (!dst_addr)
-    {
-        DH_LOG_ERR(MODULE_MPF, "Failed to allocate destination address\n");
-        return -ENOMEM;
-    }
-
-    ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, dst_phys_addr, ob.host_addr, ob.size);
-    if (ret)
-    {
-        DH_LOG_ERR(MODULE_MPF, "pci_epc_map_addr err!!!\n");
-        return ret;
-    }
-    ob.dpu_vaddr = (unsigned long long)dst_addr;
-    ob.dpu_paddr = dst_phys_addr;
-    if (copy_to_user((void *)arg, &ob, sizeof(struct ioctl_ob_data)))
-    {
-        DH_LOG_ERR(MODULE_MPF, "err:copy_to_user failed!\n");
-        return -EFAULT;
-    }
-
-    return 0;
+	minsz = offsetofend(struct vfio_device_ioeventfd, fd);
+
+	if (copy_from_user(&ioeventfd, (void __user *)arg, minsz))
+		return -EFAULT;
+
+	DH_LOG_INFO(
+			MODULE_MPF,
+			"func = 0x%x, vfunc_no = 0x%x, offset = 0x%llx, data = 0x%llx\n",
+			epf->func_no, epf->vfunc_no, ioeventfd.offset, ioeventfd.data);
+	if (ioeventfd.argsz < minsz) {
+		return -EINVAL;
+	}
+
+	if (ioeventfd.flags & ~VFIO_DEVICE_IOEVENTFD_SIZE_MASK) {
+		return -EINVAL;
+	}
+
+	count = ioeventfd.flags & VFIO_DEVICE_IOEVENTFD_SIZE_MASK;
+
+	if (hweight8(count) != 1 || ioeventfd.fd < -1)
+		return -EINVAL;
+
+	return epf_mdev_ioeventfd(mdev_state, ioeventfd.offset, ioeventfd.data,
+							  count, ioeventfd.fd);
 }
 
-static int vfio_outbound_read(struct mdev_device *mdev, struct mdev_state *mdev_state, unsigned long arg)
+static int vfio_outbound_set(struct mdev_device *mdev,
+							 struct mdev_state *mdev_state, unsigned long arg)
 {
-    struct pci_epf_mdev_dev *epf_mdev_dev = mdev_state->epf_mdev_dev;
-    struct pci_epf *epf = epf_mdev_dev->epf;
-    struct pci_epc *epc = epf->epc;
-    struct pci_ob_rw_data ob_rw_data = {0};
-
-    if (copy_from_user(&ob_rw_data, (void *)arg, sizeof(struct pci_ob_rw_data)))
-    {
-        DH_LOG_ERR(MODULE_MPF, "err:copy_from_user failed!\n");
-        return -EFAULT;
-    }
-    DH_LOG_INFO(MODULE_MPF, "ob_rw_data.phys_addr = 0x%llx, ob_rw_data.size = 0x%x\n", ob_rw_data.phys_addr, ob_rw_data.size);
-
-    pcie_zte_epc_ob_read(epc, (phys_addr_t)ob_rw_data.phys_addr, ob_rw_data.size, &ob_rw_data.val);
-
-    if (copy_to_user((void *)arg, &ob_rw_data, sizeof(struct pci_ob_rw_data)))
-    {
-        DH_LOG_ERR(MODULE_MPF, "err:copy_to_user failed!\n");
-        return -EFAULT;
-    }
-
-    return 0;
+	int ret = 0;
+	struct pci_epf_mdev_dev *epf_mdev_dev = mdev_state->epf_mdev_dev;
+	struct pci_epf *epf = epf_mdev_dev->epf;
+	struct pci_epc *epc = epf->epc;
+	struct ioctl_ob_data ob = { 0 };
+	void __iomem *dst_addr = NULL;
+	phys_addr_t dst_phys_addr = 0;
+
+	if (copy_from_user(&ob, (void *)arg, sizeof(struct ioctl_ob_data))) {
+		DH_LOG_ERR(MODULE_MPF, "err:copy_from_user failed!\n");
+		return -EFAULT;
+	}
+	DH_LOG_INFO(MODULE_MPF, "ob->host = 0x%llx, ob->size = 0x%lxs\n",
+				ob.host_addr, ob.size);
+
+	dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, ob.size);
+	if (!dst_addr) {
+		DH_LOG_ERR(MODULE_MPF, "Failed to allocate destination address\n");
+		return -ENOMEM;
+	}
+
+	ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, dst_phys_addr,
+						   ob.host_addr, ob.size);
+	if (ret) {
+		DH_LOG_ERR(MODULE_MPF, "pci_epc_map_addr err!!!\n");
+		return ret;
+	}
+	ob.dpu_vaddr = (unsigned long long)dst_addr;
+	ob.dpu_paddr = dst_phys_addr;
+	if (copy_to_user((void *)arg, &ob, sizeof(struct ioctl_ob_data))) {
+		DH_LOG_ERR(MODULE_MPF, "err:copy_to_user failed!\n");
+		return -EFAULT;
+	}
+
+	return 0;
 }
 
-static int vfio_outbound_clear(struct mdev_device *mdev, struct mdev_state *mdev_state, unsigned long arg)
+static int vfio_outbound_read(struct mdev_device *mdev,
+							  struct mdev_state *mdev_state, unsigned long arg)
 {
-    struct pci_epf_mdev_dev *epf_mdev_dev = mdev_state->epf_mdev_dev;
-    struct pci_epf *epf = epf_mdev_dev->epf;
-    struct pci_epc *epc = epf->epc;
-    struct ioctl_ob_data ob = {0};
+	struct pci_epf_mdev_dev *epf_mdev_dev = mdev_state->epf_mdev_dev;
+	struct pci_epf *epf = epf_mdev_dev->epf;
+	struct pci_epc *epc = epf->epc;
+	struct pci_ob_rw_data ob_rw_data = { 0 };
 
-    if (copy_from_user(&ob, (void *)arg, sizeof(struct ioctl_ob_data)))
-    {
-        DH_LOG_ERR(MODULE_MPF, "err:copy_from_user failed!\n");
-        return -EFAULT;
-    }
+	if (copy_from_user(&ob_rw_data, (void *)arg,
+					   sizeof(struct pci_ob_rw_data))) {
+		DH_LOG_ERR(MODULE_MPF, "err:copy_from_user failed!\n");
+		return -EFAULT;
+	}
+	DH_LOG_INFO(MODULE_MPF,
+				"ob_rw_data.phys_addr = 0x%llx, ob_rw_data.size = 0x%x\n",
+				ob_rw_data.phys_addr, ob_rw_data.size);
 
-    pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, ob.dpu_vaddr);
-    pci_epc_mem_free_addr(epc, ob.dpu_paddr, (void *)ob.dpu_vaddr, ob.size);
+	pcie_zte_epc_ob_read(epc, ob_rw_data.phys_addr, ob_rw_data.size,
+						 &ob_rw_data.val);
 
-    return 0;
+	if (copy_to_user((void *)arg, &ob_rw_data, sizeof(struct pci_ob_rw_data))) {
+		DH_LOG_ERR(MODULE_MPF, "err:copy_to_user failed!\n");
+		return -EFAULT;
+	}
+
+	return 0;
 }
 
-static int vfio_virtio_module_set(unsigned long arg)
+static int vfio_outbound_clear(struct mdev_device *mdev,
+							   struct mdev_state *mdev_state, unsigned long arg)
 {
-    struct ioctl_virtio_data virtio_data = {0};
+	struct pci_epf_mdev_dev *epf_mdev_dev = mdev_state->epf_mdev_dev;
+	struct pci_epf *epf = epf_mdev_dev->epf;
+	struct pci_epc *epc = epf->epc;
+	struct ioctl_ob_data ob = { 0 };
+
+	if (copy_from_user(&ob, (void *)arg, sizeof(struct ioctl_ob_data))) {
+		DH_LOG_ERR(MODULE_MPF, "err:copy_from_user failed!\n");
+		return -EFAULT;
+	}
 
-    if (copy_from_user(&virtio_data, (void *)arg, sizeof(struct ioctl_virtio_data)))
-    {
-        DH_LOG_ERR(MODULE_MPF, "err:copy_from_user failed!\n");
-        return -EFAULT;
-    }
+	pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, ob.dpu_vaddr);
+	pci_epc_mem_free_addr(epc, ob.dpu_paddr, (void *)ob.dpu_vaddr, ob.size);
 
-    return ep_virtio_module_set(virtio_data.ep_id, virtio_data.pf_id, virtio_data.en);
+	return 0;
 }
 
-static long pci_mdev_ioctl(struct mdev_device *mdev, unsigned int cmd, unsigned long arg)
+static int vfio_virtio_module_set(unsigned long arg)
 {
-    int ret = 0;
-    struct mdev_state *mdev_state;
-    struct device *dev = NULL;
-    // struct pci_epf *epf = container_of(dev, struct pci_epf, dev);
-    // struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf);
-
-    if (mdev == NULL)
-    {
-        DH_LOG_ERR(MODULE_MPF, "err: mdev is NULL!\n");
-        return -EINVAL;
-    }
-    dev = mdev->type->parent->dev;
-
-    mdev_state = mdev_get_drvdata(mdev);
-    if (!mdev_state)
-        return -ENODEV;
-
-    switch (cmd)
-    {
-        case VFIO_DEVICE_GET_INFO:
-            return device_get_info(mdev, mdev_state, arg);
-        case VFIO_DEVICE_GET_REGION_INFO:
-            return device_get_region_info(mdev, mdev_state, arg);
-        case VFIO_DEVICE_IOEVENTFD:
-            return vfio_device_ioeventfd(mdev, mdev_state, arg);
-        case VFIO_OUTBOUND_SET:
-            return vfio_outbound_set(mdev, mdev_state, arg);
-        case VFIO_OUTBOUND_CLEAR:
-            return vfio_outbound_clear(mdev, mdev_state, arg);
-        case VFIO_POWER_RESET:
-            ep_power_reset(arg);
-            return 0;
-        case VFIO_VIRTIO_MODULE_SET:
-            return vfio_virtio_module_set(arg);
-        case VFIO_LINKUP:
-            return pcie_zf_link_up(arg);
-        case VFIO_OUTBOUND_READ:
-            return vfio_outbound_read(mdev, mdev_state, arg);
-        // case VFIO_EP4_LINKUP:
-        //     return is_ep4_link_up();
-        default:
-            DH_LOG_ERR(MODULE_MPF, "zte-pci-epf-mdev ioctl cmd error!\n");
-            ret = -ENOTTY;
-    }
-
-    return ret;
+	struct ioctl_virtio_data virtio_data = { 0 };
+
+	if (copy_from_user(&virtio_data, (void *)arg,
+					   sizeof(struct ioctl_virtio_data))) {
+		DH_LOG_ERR(MODULE_MPF, "err:copy_from_user failed!\n");
+		return -EFAULT;
+	}
+
+	return ep_virtio_module_set(virtio_data.ep_id, virtio_data.pf_id,
+								virtio_data.en);
+}
+
+static long pci_mdev_ioctl(struct mdev_device *mdev, unsigned int cmd,
+						   unsigned long arg)
+{
+	int ret = 0;
+	struct mdev_state *mdev_state;
+	struct device *dev = mdev->type->parent->dev;
+	// struct pci_epf *epf = container_of(dev, struct pci_epf, dev);
+	// struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf);
+
+	if (!mdev)
+		return -EINVAL;
+
+	mdev_state = mdev_get_drvdata(mdev);
+	if (!mdev_state)
+		return -ENODEV;
+
+	switch (cmd) {
+	case VFIO_DEVICE_GET_INFO:
+		return device_get_info(mdev, mdev_state, arg);
+	case VFIO_DEVICE_GET_REGION_INFO:
+		return device_get_region_info(mdev, mdev_state, arg);
+	case VFIO_DEVICE_IOEVENTFD:
+		return vfio_device_ioeventfd(mdev, mdev_state, arg);
+	case VFIO_OUTBOUND_SET:
+		return vfio_outbound_set(mdev, mdev_state, arg);
+	case VFIO_OUTBOUND_CLEAR:
+		return vfio_outbound_clear(mdev, mdev_state, arg);
+	case VFIO_POWER_RESET:
+		ep_power_reset(arg);
+		return 0;
+	case VFIO_VIRTIO_MODULE_SET:
+		return vfio_virtio_module_set(arg);
+	case VFIO_LINKUP:
+		return pcie_zf_link_up(arg);
+	case VFIO_OUTBOUND_READ:
+		return vfio_outbound_read(mdev, mdev_state, arg);
+	// case VFIO_EP4_LINKUP:
+	//     return is_ep4_link_up();
+	default:
+		DH_LOG_ERR(MODULE_MPF, "zte-pci-epf-mdev ioctl cmd error!\n");
+		ret = -ENOTTY;
+	}
+
+	return ret;
 }
 #endif
 
 static const struct mdev_parent_ops mdev_fops = {
-    .owner = THIS_MODULE,
-    .dev_attr_groups = pci_mdev_dev_groups,
-    .mdev_attr_groups = mdev_dev_groups,
-    .supported_type_groups = mdev_type_groups,
-    .create = pci_mdev_create,
-    .remove = pci_mdev_remove,
-    .open = pci_mdev_open,
-    .release = pci_mdev_close,
-    .read = pci_mdev_read,
-    .write = pci_mdev_write,
-    .mmap = pci_mdev_mmap,
-    .ioctl = pci_mdev_ioctl,
+	.owner = THIS_MODULE,
+	.dev_attr_groups = pci_mdev_dev_groups,
+	.mdev_attr_groups = mdev_dev_groups,
+	.supported_type_groups = mdev_type_groups,
+	.create = pci_mdev_create,
+	.remove = pci_mdev_remove,
+	.open = pci_mdev_open,
+	.release = pci_mdev_close,
+	.read = pci_mdev_read,
+	.write = pci_mdev_write,
+	.mmap = pci_mdev_mmap,
+	.ioctl = pci_mdev_ioctl,
 };
 #endif
 
 static int pci_epf_mdev_probe(struct pci_epf *epf)
 {
-    struct pci_epf_mdev_dev *epf_mdev_dev;
-    struct device *dev = &epf->dev;
-    int ret = 0;
+	struct pci_epf_mdev_dev *epf_mdev_dev;
+	struct device *dev = &epf->dev;
+	int ret = 0;
 
-    epf_mdev_dev = devm_kzalloc(dev, sizeof(*epf_mdev_dev), GFP_KERNEL);
-    if (!epf_mdev_dev)
-        return -ENOMEM;
+	epf_mdev_dev = devm_kzalloc(dev, sizeof(*epf_mdev_dev), GFP_KERNEL);
+	if (!epf_mdev_dev)
+		return -ENOMEM;
 
-    epf_mdev_dev->epf = epf;
-    epf->header = devm_kzalloc(dev, sizeof(struct pci_epf_header), GFP_KERNEL);
-    if (!epf->header)
-    {
-        ret = -ENOMEM;
-        goto err;
-    }
+	epf_mdev_dev->epf = epf;
+	epf->header = devm_kzalloc(dev, sizeof(struct pci_epf_header), GFP_KERNEL);
+	if (!epf->header) {
+		ret = -ENOMEM;
+		goto err;
+	}
 
-    epf_mdev_dev->created_flag = 0;
+	epf_mdev_dev->created_flag = 0;
 
-    // DMA一致性设置（未必有效，待查）
-    dev->coherent_dma_mask = ~((u64)0x0);
+	// DMA一致性设置（未必有效，待查）
+	dev->coherent_dma_mask = ~((u64)0x0);
 
-    epf_set_drvdata(epf, epf_mdev_dev);
+	epf_set_drvdata(epf, epf_mdev_dev);
 
-    ret = mdev_register_device(dev, &mdev_fops);
-    if (ret)
-    {
-        DH_LOG_ERR(MODULE_MPF, "mdev_register_device failed %d\n", ret);
-        goto err;
-    }
+	ret = mdev_register_device(dev, &mdev_fops);
+	if (ret) {
+		DH_LOG_ERR(MODULE_MPF, "mdev_register_device failed %d\n", ret);
+		goto err;
+	}
 
-    return 0;
+	return 0;
 
 err:
-    devm_kfree(dev, epf->header);
-    devm_kfree(dev, epf_mdev_dev);
-    return ret;
+	devm_kfree(dev, epf->header);
+	devm_kfree(dev, epf_mdev_dev);
+	return ret;
 }
 
 static int pci_epf_remove(struct pci_epf *epf)
 {
-    struct device *dev = &epf->dev;
-    struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf);
-
-    mdev_unregister_device(&epf->dev);
-    if (epf->header)
-    {
-        devm_kfree(dev, epf->header);
-    }
-    if (epf_mdev_dev)
-    {
-        devm_kfree(dev, epf_mdev_dev);
-    }
-
-    return 0;
+	struct device *dev = &epf->dev;
+	struct pci_epf_mdev_dev *epf_mdev_dev = epf_get_drvdata(epf);
+
+	mdev_unregister_device(&epf->dev);
+	if (epf->header) {
+		devm_kfree(dev, epf->header);
+	}
+	if (epf_mdev_dev) {
+		devm_kfree(dev, epf_mdev_dev);
+	}
+
+	return 0;
 }
 
 static struct pci_epf_driver pci_epf_mdev_driver = {
-    .driver.name = "pci-epf-mdev",
-    .probe = pci_epf_mdev_probe,
-    .remove = pci_epf_remove,
-    .id_table = pci_epf_dev_ids,
-    .ops = &epf_mdev_ops,
-    .owner = THIS_MODULE,
+	.driver.name = "pci-epf-mdev",
+	.probe = pci_epf_mdev_probe,
+	.remove = pci_epf_remove,
+	.id_table = pci_epf_dev_ids,
+	.ops = &epf_mdev_ops,
+	.owner = THIS_MODULE,
 };
 
 static int __init pci_epf_mdev_init(void)
 {
-    int ret = 0;
+	int ret = 0;
 
-    ret = pci_epf_register_driver(&pci_epf_mdev_driver);
-    if (ret)
-    {
-        pr_err("Failed to register pci epf test driver --> %d\n", ret);
-        return ret;
-    }
+	ret = pci_epf_register_driver(&pci_epf_mdev_driver);
+	if (ret) {
+		pr_err("Failed to register pci epf test driver --> %d\n", ret);
+		return ret;
+	}
 
-    DH_LOG_ERR(MODULE_MPF, "zte_epf driver regist successful\n");
-    return ret;
+	DH_LOG_ERR(MODULE_MPF, "zte_epf driver regist successful\n");
+	return ret;
 }
 module_init(pci_epf_mdev_init);
 
 static void __exit pci_epf_mdev_exit(void)
 {
-    pci_epf_unregister_driver(&pci_epf_mdev_driver);
+	pci_epf_unregister_driver(&pci_epf_mdev_driver);
 }
 module_exit(pci_epf_mdev_exit);
 
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epf/pcie-zte-zf-epf.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epf/pcie-zte-zf-epf.h
index 8fdc09ed0a5a99082911b3815935c24b5a7acd01..8536a87d9c294cc4fb99336a0c9979dc175b405a 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/epf/pcie-zte-zf-epf.h
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/epf/pcie-zte-zf-epf.h
@@ -41,13 +41,14 @@
 #define EPF_MDEV_IOEVENTFD_MAX 20
 
 /* ioctl cmd */
-#define VFIO_OUTBOUND_SET      _IO(VFIO_TYPE, VFIO_BASE + 30)
-#define VFIO_OUTBOUND_CLEAR    _IO(VFIO_TYPE, VFIO_BASE + 31)
-#define VFIO_POWER_RESET       _IO(VFIO_TYPE, VFIO_BASE + 32)
+#define VFIO_OUTBOUND_SET _IO(VFIO_TYPE, VFIO_BASE + 30)
+#define VFIO_OUTBOUND_CLEAR _IO(VFIO_TYPE, VFIO_BASE + 31)
+#define VFIO_POWER_RESET _IO(VFIO_TYPE, VFIO_BASE + 32)
 #define VFIO_VIRTIO_MODULE_SET _IO(VFIO_TYPE, VFIO_BASE + 33)
-#define VFIO_LINKUP            _IO(VFIO_TYPE, VFIO_BASE + 34)
-#define VFIO_OUTBOUND_READ     _IO(VFIO_TYPE, VFIO_BASE + 35)
-// #define VFIO_EP4_LINKUP                         _IO(VFIO_TYPE, VFIO_BASE + 35)
+#define VFIO_LINKUP _IO(VFIO_TYPE, VFIO_BASE + 34)
+#define VFIO_OUTBOUND_READ _IO(VFIO_TYPE, VFIO_BASE + 35)
+// #define VFIO_EP4_LINKUP                         _IO(VFIO_TYPE, VFIO_BASE +
+// 35)
 
 extern int pcie_zf_link_up(int ep_id);
 // extern int is_ep4_link_up(void);
@@ -55,88 +56,88 @@ extern void ep_power_reset(int ep_id);
 extern int ep_virtio_module_set(int ep_id, int pf_id, int en);
 
 struct ioctl_virtio_data {
-    int ep_id;
-    int pf_id;
-    int en;
+	int ep_id;
+	int pf_id;
+	int en;
 };
 
 struct ioctl_ob_data {
-    unsigned long long dpu_paddr;
-    unsigned long long dpu_vaddr;
-    unsigned long long host_addr;
-    unsigned long size;
+	unsigned long long dpu_paddr;
+	unsigned long long dpu_vaddr;
+	unsigned long long host_addr;
+	unsigned long size;
 };
 
 struct pci_epf_mdev_dev {
-    struct pci_epf *epf;
-    enum pci_barno epf_barno;
-    size_t msix_table_offset;
-    const struct pci_epc_features *epc_features;
-    int created_flag; // 0:Not created, 1:created
-    void *pf_bar_vaddr[PCI_STD_NUM_BARS + 1];
-    void *vf_bar_vaddr[PCI_STD_NUM_BARS];
+	struct pci_epf *epf;
+	enum pci_barno epf_barno;
+	size_t msix_table_offset;
+	const struct pci_epc_features *epc_features;
+	int created_flag; // 0:Not created, 1:created
+	void *pf_bar_vaddr[PCI_STD_NUM_BARS + 1];
+	void *vf_bar_vaddr[PCI_STD_NUM_BARS];
 };
 
 struct epf_mdev_ioeventfd {
-    struct list_head next;
-    struct mdev_state *mdev_state;
-    struct virqfd *virqfd;
-    u64 data;
-    loff_t pos;
-    u64 offset;
-    int count;
+	struct list_head next;
+	struct mdev_state *mdev_state;
+	struct virqfd *virqfd;
+	u64 data;
+	loff_t pos;
+	u64 offset;
+	int count;
 };
 
 struct mdev_region_info {
-    u64 start;
-    u64 phys_start;
-    u32 size;
-    u64 vfio_offset;
-    u32 argsz;
+	u64 start;
+	u64 phys_start;
+	u32 size;
+	u64 vfio_offset;
+	u32 argsz;
 };
 
 struct mdev_state {
-    int irq_fd;
-    struct eventfd_ctx *intx_evtfd;
-    struct eventfd_ctx *msi_evtfd;
-    struct eventfd_ctx *msix_evtfd;
-    int irq_index;
-    struct mutex ops_lock;
-    struct mdev_device *mdev;
-    struct mdev_region_info region_info[VFIO_PCI_NUM_REGIONS];
-    u32 bar_mask[VFIO_PCI_NUM_REGIONS];
-    struct list_head next;
-    struct vfio_device_info dev_info;
-    struct pci_epf_mdev_dev *epf_mdev_dev;
-    struct mutex ioeventfds_lock;
-    struct list_head ioeventfds_list;
-    int ioeventfds_nr;
+	int irq_fd;
+	struct eventfd_ctx *intx_evtfd;
+	struct eventfd_ctx *msi_evtfd;
+	struct eventfd_ctx *msix_evtfd;
+	int irq_index;
+	struct mutex ops_lock;
+	struct mdev_device *mdev;
+	struct mdev_region_info region_info[VFIO_PCI_NUM_REGIONS];
+	u32 bar_mask[VFIO_PCI_NUM_REGIONS];
+	struct list_head next;
+	struct vfio_device_info dev_info;
+	struct pci_epf_mdev_dev *epf_mdev_dev;
+	struct mutex ioeventfds_lock;
+	struct list_head ioeventfds_list;
+	int ioeventfds_nr;
 };
 
 // mdev_private struct
 struct mdev_parent {
-    struct device *dev;
-    const struct mdev_parent_ops *ops;
-    struct kref ref;
-    struct list_head next;
-    struct kset *mdev_types_kset;
-    struct list_head type_list;
-    struct rw_semaphore unreg_sem;
+	struct device *dev;
+	const struct mdev_parent_ops *ops;
+	struct kref ref;
+	struct list_head next;
+	struct kset *mdev_types_kset;
+	struct list_head type_list;
+	struct rw_semaphore unreg_sem;
 };
 
 struct mdev_type {
-    struct kobject kobj;
-    struct kobject *devices_kobj;
-    struct mdev_parent *parent;
-    struct list_head next;
-    unsigned int type_group_id;
+	struct kobject kobj;
+	struct kobject *devices_kobj;
+	struct mdev_parent *parent;
+	struct list_head next;
+	unsigned int type_group_id;
 };
 // mdev_private struct end
 
 struct pci_ob_rw_data {
-    unsigned long long phys_addr;
-    unsigned int size;
-    unsigned int val;
+	unsigned long long phys_addr;
+	unsigned int size;
+	unsigned int val;
 };
 
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/eq.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/eq.c
old mode 100755
new mode 100644
index 88d012be115e92d1e11cca4858e434d3d9e33e14..4f7212c8a306925cfe42f5ed7b89cee8775e914b
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/eq.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/eq.c
@@ -1,502 +1,387 @@
-#include <linux/dinghai/eq.h>
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/dh_cmd.h>
-#include <linux/dinghai/helper.h>
-#include <linux/dinghai/log.h>
-#include "irq.h"
-#include "eq.h"
-#include "zf_mpf.h"
-#include "gdma.h"
-
-struct dh_mpf_eq_table {
-    struct dh_irq      **comp_irqs;
-    struct dh_irq      *async_risc_irq;
-    struct dh_irq      *async_pf_irq;
-    struct dh_irq      *async_irq1;
-    struct dh_irq      *async_irq2;
-    struct dh_irq      *async_irq3;
-    struct dh_irq      *async_irq4;
-    struct dh_irq      **gdma_irqs;
-    struct dh_eq_async async_risc_eq;
-    struct dh_eq_async async_pf_eq;
-    struct dh_eq_async async_eq1;
-    struct dh_eq_async async_eq2;
-    struct dh_eq_async async_eq3;
-    struct dh_eq_async async_eq4;
-    struct dh_eq_async gdma_eq[ZXDH_MPF_GDMA_IRQ_NUM];
-};
-
-static int32_t create_async_eqs(struct dh_core_dev *dev);
-
-#ifdef CONFIG_ZF_GDMA
-static int32_t create_gdma_eqs(struct dh_core_dev *dev);
-void cleanup_gdma_eq(struct dh_core_dev *dev, struct dh_mpf_eq_table *table_priv, uint16_t num);
-#endif
-
-static int32_t __attribute__((unused)) create_eq_map(struct dh_eq_param *param)
-{
-    int32_t err = 0;
-
-    /* inform device*/
-    return err;
-}
-
-int32_t dh_mpf_eq_table_init(struct dh_core_dev *dev)
-{
-    struct dh_mpf_eq_table *table_priv = NULL;
-
-    table_priv = kvzalloc(sizeof(*table_priv), GFP_KERNEL);
-    if (unlikely(table_priv == NULL))
-    {
-        return -ENOMEM;
-    }
-
-    dh_eq_table_init(dev, table_priv);
-
-    return 0;
-}
-
-/*todo*/
-int32_t dh_eq_get_comp_eqs(struct dh_core_dev *dev)
-{
-    return 0;
-}
-
-static int32_t create_comp_eqs(struct dh_core_dev *dev)
-{
-    if (IS_ERR_OR_NULL(dev))
-    {
-        dh_err(dev, "error dev\n");
-        return PTR_ERR(dev);
-    }
-
-    return 0;
-}
-
-static int32_t destroy_async_eq(struct dh_core_dev *dev)
-{
-    struct dh_eq_table *eq_table = &dev->eq_table;
-
-    mutex_lock(&eq_table->lock);
-    /*unmap inform device*/
-    mutex_unlock(&eq_table->lock);
-
-    return 0;
-}
-
-static void cleanup_async_eq(struct dh_core_dev *dev,
-                             struct dh_eq_async *eq, const char *name)
-{
-    dh_eq_disable(dev, &eq->core, &eq->irq_nb);
-}
-
-static void destroy_async_eqs(struct dh_core_dev *dev)
-{
-    struct dh_eq_table *table          = &dev->eq_table;
-    struct dh_mpf_eq_table *table_priv = table->priv;
-
-    cleanup_async_eq(dev, &table_priv->async_risc_eq, "riscv");
-    cleanup_async_eq(dev, &table_priv->async_pf_eq, "pf");
-    cleanup_async_eq(dev, &table_priv->async_eq1, "eq1");
-    cleanup_async_eq(dev, &table_priv->async_eq2, "eq2");
-    cleanup_async_eq(dev, &table_priv->async_eq3, "eq3");
-    cleanup_async_eq(dev, &table_priv->async_eq4, "eq4");
-    destroy_async_eq(dev);
-    dh_irqs_release_vectors(&table_priv->async_risc_irq, 1);
-    dh_irqs_release_vectors(&table_priv->async_pf_irq, 1);
-    dh_irqs_release_vectors(&table_priv->async_irq1, 1);
-    dh_irqs_release_vectors(&table_priv->async_irq2, 1);
-    dh_irqs_release_vectors(&table_priv->async_irq3, 1);
-    dh_irqs_release_vectors(&table_priv->async_irq4, 1);
-}
-
-void destroy_comp_eqs(struct dh_core_dev *dev)
-{
-
-}
-
-#ifdef CONFIG_ZF_GDMA
-static void destroy_gdma_eqs(struct dh_core_dev *dev)
-{
-    struct dh_eq_table *eq_table = &dev->eq_table;
-    struct dh_mpf_eq_table *mpf_eq_table = eq_table->priv;
-    struct dh_irq_table *irq_table = &dev->irq_table;
-    struct dh_mpf_irq_table *mpf_irq_table = irq_table->priv;
-
-    cleanup_gdma_eq(dev, mpf_eq_table, ZXDH_MPF_GDMA_IRQ_NUM);
-
-    dh_irq_affinity_irqs_release(mpf_irq_table->mpf_gdma_pool, mpf_eq_table->gdma_irqs, ZXDH_MPF_GDMA_IRQ_NUM);
-    dh_irqs_release_vectors(mpf_eq_table->gdma_irqs, ZXDH_MPF_GDMA_IRQ_NUM);
-}
-#endif
-
-void dh_mpf_eq_table_destroy(struct dh_core_dev *dev)
-{
-    destroy_comp_eqs(dev);
-    destroy_async_eqs(dev);
-#ifdef CONFIG_ZF_GDMA
-    destroy_gdma_eqs(dev);
-#endif
-}
-
-int32_t dh_mpf_eq_table_create(struct dh_core_dev *dev)
-{
-    int32_t err = 0;
-
-    err = create_async_eqs(dev);
-    if (err != 0)
-    {
-        dh_err(dev, "Failed to create async EQs\n");
-        goto err_async_eqs;
-    }
-
-    err = create_comp_eqs(dev);
-    if (err != 0)
-    {
-        dh_err(dev, "Failed to create completion EQs\n");
-        goto err_comp_eqs;
-    }
-
-#ifdef CONFIG_ZF_GDMA
-    err = create_gdma_eqs(dev);
-    if (err != 0)
-    {
-        dh_err(dev, "Failed to create gdma EQs\n");
-        goto err_comp_eqs;
-    }
-#endif
-
-    return 0;
-
-err_comp_eqs:
-    destroy_async_eqs(dev);
-err_async_eqs:
-    return err;
-}
-
-/*create eventq*/
-static int32_t create_async_eq(struct dh_core_dev *dev, struct dh_irq *risc, struct dh_irq *pf)
-{
-    struct dh_eq_table *eq_table = &dev->eq_table;
-    struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dev);
-    struct msix_para in = {0};
-    int32_t err = 0;
-
-    in.vector_risc = risc->index;
-    in.vector_pfvf = pf->index;
-    in.vector_mpf = 0xff;
-    in.driver_type = MSG_CHAN_END_PF;//TODO
-    in.pdev = dev->pdev;
-    in.virt_addr = mpf_dev->pci_ioremap_addr + ZXDH_BAR1_CHAN_OFFSET;
-    in.pcie_id = mpf_dev->pcie_id;
-    DH_LOG_INFO(MODULE_MPF, "pcie_id = 0x%x\n", mpf_dev->pcie_id);
-
-    mutex_lock(&eq_table->lock);
-
-    err = zxdh_bar_enable_chan(&in, &mpf_dev->vport);
-
-    mutex_unlock(&eq_table->lock);
-
-    return err;
-}
-
-static int32_t dh_eq_async_riscv_int(struct notifier_block *nb, unsigned long action, void *data)
-{
-    struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
-    struct dh_eq_table *eq_table = &dev->eq_table;
-
-    atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF], DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF, NULL);
-
-    return 0;
-}
-
-static int32_t dh_eq_async_mpf_int(struct notifier_block *nb, unsigned long action, void *data)
-{
-    struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
-    struct dh_eq_table *eq_table = &dev->eq_table;
-
-    atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_PF_TO_MPF], DH_EVENT_TYPE_NOTIFY_PF_TO_MPF, NULL);
-
-    return 0;
-}
-
-static int32_t dh_eq_async_int1(struct notifier_block *nb, unsigned long action, void *data)
-{
-    struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
-    struct dh_eq_table *eq_table = &dev->eq_table;
-
-    atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_1], DH_EVENT_TYPE_NOTIFY_1, dev);
-
-    return 0;
-}
-
-static int32_t dh_eq_async_int2(struct notifier_block *nb, unsigned long action, void *data)
-{
-    struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
-    struct dh_eq_table *eq_table = &dev->eq_table;
-
-    atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_2], DH_EVENT_TYPE_NOTIFY_2, dev);
-
-    return 0;
-}
-
-static int32_t dh_eq_async_int3(struct notifier_block *nb, unsigned long action, void *data)
-{
-    struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
-    struct dh_eq_table *eq_table = &dev->eq_table;
-
-    atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_3], DH_EVENT_TYPE_NOTIFY_3, dev);
-
-    return 0;
-}
-
-static int32_t dh_eq_async_int4(struct notifier_block *nb, unsigned long action, void *data)
-{
-    struct dh_eq_async *eq_riscv_async = container_of(nb, struct dh_eq_async, irq_nb);
-    struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
-    struct dh_eq_table *eq_table = &dev->eq_table;
-
-    atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_4], DH_EVENT_TYPE_NOTIFY_4, dev);
-
-    return 0;
-}
-
-static int32_t create_async_eqs(struct dh_core_dev *dev)
-{
-    struct dh_eq_table *table          = &dev->eq_table;
-    struct dh_mpf_eq_table *table_priv = table->priv;
-    struct dh_eq_param param           = {};
-    int32_t err                        = 0;
-
-    dh_dbg(dev, "start\r\n");
-    table_priv->async_risc_irq = dh_mpf_async_irq_request(dev);
-    if (IS_ERR_OR_NULL(table_priv->async_risc_irq))
-    {
-        dh_err(dev, "Failed to get async_risc_irq\n");
-        return PTR_ERR(table_priv->async_risc_irq);
-    }
-
-    table_priv->async_pf_irq = dh_mpf_async_irq_request(dev);
-    if (IS_ERR_OR_NULL(table_priv->async_pf_irq))
-    {
-        err = PTR_ERR(table_priv->async_pf_irq);
-        dh_err(dev, "Failed to get async_pf_irq\n");
-        goto err_irq_request;
-    }
-
-    table_priv->async_irq1 = dh_mpf_async_irq_request(dev);
-    if (IS_ERR_OR_NULL(table_priv->async_irq1))
-    {
-        err = PTR_ERR(table_priv->async_irq1);
-        dh_err(dev, "Failed to get async_irq1\n");
-        goto err_irq_request1;
-    }
-
-    table_priv->async_irq2 = dh_mpf_async_irq_request(dev);
-    if (IS_ERR_OR_NULL(table_priv->async_irq2))
-    {
-        err = PTR_ERR(table_priv->async_irq2);
-        dh_err(dev, "Failed to get async_irq2\n");
-        goto err_irq_request2;
-    }
-
-    table_priv->async_irq3 = dh_mpf_async_irq_request(dev);
-    if (IS_ERR_OR_NULL(table_priv->async_irq3))
-    {
-        err = PTR_ERR(table_priv->async_irq3);
-        dh_err(dev, "Failed to get async_irq3\n");
-        goto err_irq_request3;
-    }
-
-    table_priv->async_irq4 = dh_mpf_async_irq_request(dev);
-    if (IS_ERR_OR_NULL(table_priv->async_irq4))
-    {
-        err = PTR_ERR(table_priv->async_irq4);
-        dh_err(dev, "Failed to get async_irq4\n");
-        goto err_irq_request4;
-    }
-
-    err = create_async_eq(dev, table_priv->async_risc_irq, table_priv->async_pf_irq);
-    if (err != 0)
-    {
-        dh_err(dev, "Failed to create async_eq\n");
-        goto err_create_async_eq;
-    }
-
-    param = (struct dh_eq_param) {
-        .irq = table_priv->async_risc_irq,
-        .nent = 10,
-        .event_type = DH_EVENT_QUEUE_TYPE_RISCV /* used for inform dpu */
-    };
-    err = setup_async_eq(dev, &table_priv->async_risc_eq, &param, dh_eq_async_riscv_int, "riscv", dev);
-    if (err != 0)
-    {
-        dh_err(dev, "Failed to setup async_risc_eq\n");
-        goto err_setup_async_risc_eq;
-    }
-
-    param.irq = table_priv->async_pf_irq,
-    err = setup_async_eq(dev, &table_priv->async_pf_eq, &param, dh_eq_async_mpf_int, "pf", dev);
-    if (err != 0)
-    {
-        dh_err(dev, "Failed to setup async_pf_eq\n");
-        goto err_setup_async_pf_eq;
-    }
-
-    param.irq = table_priv->async_irq1,
-    err = setup_async_eq(dev, &table_priv->async_eq1, &param, dh_eq_async_int1, "irq1", dev);
-    if (err != 0)
-    {
-        dh_err(dev, "Failed to setup async_eq1\n");
-        goto err_setup_async_eq1;
-    }
-
-    param.irq = table_priv->async_irq2,
-    err = setup_async_eq(dev, &table_priv->async_eq2, &param, dh_eq_async_int2, "irq2", dev);
-    if (err != 0)
-    {
-        dh_err(dev, "Failed to setup async_eq1\n");
-        goto err_setup_async_eq2;
-    }
-
-    param.irq = table_priv->async_irq3,
-    err = setup_async_eq(dev, &table_priv->async_eq3, &param, dh_eq_async_int3, "irq3", dev);
-    if (err != 0)
-    {
-        dh_err(dev, "Failed to setup async_eq3\n");
-        goto err_setup_async_eq3;
-    }
-
-    param.irq = table_priv->async_irq4,
-    err = setup_async_eq(dev, &table_priv->async_eq4, &param, dh_eq_async_int4, "irq4", dev);
-    if (err != 0)
-    {
-        dh_err(dev, "Failed to setup async_eq4\n");
-        goto err_setup_async_eq4;
-    }
-
-    return 0;
-
-err_setup_async_eq4:
-    cleanup_async_eq(dev, &table_priv->async_eq3, "irq3");
-err_setup_async_eq3:
-    cleanup_async_eq(dev, &table_priv->async_eq2, "irq2");
-err_setup_async_eq2:
-    cleanup_async_eq(dev, &table_priv->async_eq1, "irq1");
-err_setup_async_eq1:
-    cleanup_async_eq(dev, &table_priv->async_pf_eq, "pf");
-err_setup_async_pf_eq:
-    cleanup_async_eq(dev, &table_priv->async_risc_eq, "riscv");
-err_setup_async_risc_eq:
-    destroy_async_eq(dev);
-err_create_async_eq:
-    dh_irqs_release_vectors(&table_priv->async_irq4, 1);
-err_irq_request4:
-    dh_irqs_release_vectors(&table_priv->async_irq3, 1);
-err_irq_request3:
-    dh_irqs_release_vectors(&table_priv->async_irq2, 1);
-err_irq_request2:
-    dh_irqs_release_vectors(&table_priv->async_irq1, 1);
-err_irq_request1:
-    dh_irqs_release_vectors(&table_priv->async_pf_irq, 1);
-err_irq_request:
-    dh_irqs_release_vectors(&table_priv->async_risc_irq, 1);
-    return err;
-}
-
-#ifdef CONFIG_ZF_GDMA
-void cleanup_gdma_eq(struct dh_core_dev *dev, struct dh_mpf_eq_table *table_priv, uint16_t num)
-{
-    uint16_t i = 0;
-
-    for (i = 0; i < num; i++)
-    {
-        cleanup_async_eq(dev, &table_priv->gdma_eq[i], NULL);
-    }
-}
-
-int32_t setup_gdma_eq(struct dh_core_dev *dev, struct dh_mpf_eq_table *table_priv, uint16_t gdma_irq_num)
-{
-    struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dev);
-    struct zf_gdma_dev *gdev = mpf_dev->gdev;
-    struct dh_eq_param param = {};
-    uint16_t i = 0;
-    int32_t ret = 0;
-    void *priv = NULL;
-    notifier_fn_t callback;
-
-    if (gdma_irq_num > ZXDH_MPF_GDMA_IRQ_NUM)
-    {
-        dh_err(dev, "gdma_irq_num %d is invalid\n", gdma_irq_num);
-        return -1;
-    }
-
-    for (i = 0; i < gdma_irq_num; i++)
-    {
-        if (i < ZF_GDMA_CHAN_NUM)
-        {
-            callback = zf_gdma_chan_irq_handle;
-            priv = &gdev->chan[i];
-        }
-        else
-        {
-            callback = zf_gdma_err_irq_handle;
-            priv = dev;
-        }
-
-        param.irq = table_priv->gdma_irqs[i];
-        ret = setup_async_eq(dev, &table_priv->gdma_eq[i], &param, callback, "gdma", priv);
-        if (ret != 0)
-        {
-            LOG_ERR("Failed to setup gdma %d eq\n", i);
-            cleanup_gdma_eq(dev, table_priv, i);
-            return ret;
-        }
-    }
-
-    return 0;
-}
-
-static int32_t create_gdma_eqs(struct dh_core_dev *dev)
-{
-    struct dh_eq_table *eq_table = &dev->eq_table;
-    struct dh_mpf_eq_table *mpf_eq_table = eq_table->priv;
-    struct dh_irq_table *irq_table = &dev->irq_table;
-    struct dh_mpf_irq_table *mpf_irq_table = irq_table->priv;
-    int32_t ret = 0;
-
-    mpf_eq_table->gdma_irqs = kcalloc(ZXDH_MPF_GDMA_IRQ_NUM, sizeof(struct dh_irq *), GFP_KERNEL);
-    if (unlikely(mpf_eq_table->gdma_irqs == NULL))
-    {
-        LOG_ERR("Failed to alloc mpf_eq_table->gdma_irqs\n");
-        return -ENOMEM;
-    }
-
-    ret = dh_irq_affinity_irqs_request_auto(mpf_irq_table->mpf_gdma_pool, mpf_eq_table->gdma_irqs, ZXDH_MPF_GDMA_IRQ_NUM);
-    if (ret < 0)
-    {
-        dh_err(dev, "Failed to get gdma irq\n");
-        goto err_gdma_irq;
-    }
-
-    ret = setup_gdma_eq(dev, mpf_eq_table, ZXDH_MPF_GDMA_IRQ_NUM);
-    if (ret != 0)
-    {
-        goto err_gdma_eq;
-    }
-
-    return 0;
-
-err_gdma_eq:
-    dh_irq_affinity_irqs_release(mpf_irq_table->mpf_gdma_pool, mpf_eq_table->gdma_irqs, ZXDH_MPF_GDMA_IRQ_NUM);
-    dh_irqs_release_vectors(mpf_eq_table->gdma_irqs, ZXDH_MPF_GDMA_IRQ_NUM);
-err_gdma_irq:
-    kfree(mpf_eq_table->gdma_irqs);
-    return ret;
-}
-#endif
\ No newline at end of file
+#include <linux/dinghai/eq.h>
+#include <linux/dinghai/driver.h>
+#include <linux/dinghai/dh_cmd.h>
+#include <linux/dinghai/helper.h>
+#include <linux/dinghai/log.h>
+#include "irq.h"
+#include "eq.h"
+#include "../en_mpf.h"
+
+struct dh_mpf_eq_table {
+	struct dh_irq **comp_irqs;
+	struct dh_irq *async_risc_irq;
+	struct dh_irq *async_pf_irq;
+	struct dh_irq *async_irq1;
+	struct dh_irq *async_irq2;
+	struct dh_irq *async_irq3;
+	struct dh_irq *async_irq4;
+	struct dh_eq_async async_risc_eq;
+	struct dh_eq_async async_pf_eq;
+	struct dh_eq_async async_eq1;
+	struct dh_eq_async async_eq2;
+	struct dh_eq_async async_eq3;
+	struct dh_eq_async async_eq4;
+};
+
+static int32_t create_async_eqs(struct dh_core_dev *dev);
+
+static int32_t __attribute__((unused)) create_eq_map(struct dh_eq_param *param)
+{
+	int32_t err = 0;
+
+	/* inform device*/
+	return err;
+}
+
+int32_t dh_mpf_eq_table_init(struct dh_core_dev *dev)
+{
+	struct dh_eq_table *eq_table;
+	struct dh_mpf_eq_table *table_priv = NULL;
+	int32_t err = 0;
+
+	eq_table = &dev->eq_table;
+
+	table_priv = kvzalloc(sizeof(*table_priv), GFP_KERNEL);
+	if (unlikely(table_priv == NULL)) {
+		err = -ENOMEM;
+		goto err_table_priv;
+	}
+
+	dh_eq_table_init(dev, table_priv);
+
+	return 0;
+
+err_table_priv:
+	kvfree(eq_table);
+	return err;
+}
+
+/*todo*/
+int32_t dh_eq_get_comp_eqs(struct dh_core_dev *dev)
+{
+	return 0;
+}
+
+static int32_t create_comp_eqs(struct dh_core_dev *dev)
+{
+	return 0;
+}
+
+static int32_t destroy_async_eq(struct dh_core_dev *dev)
+{
+	struct dh_eq_table *eq_table = &dev->eq_table;
+
+	mutex_lock(&eq_table->lock);
+	/*unmap inform device*/
+	mutex_unlock(&eq_table->lock);
+
+	return 0;
+}
+
+static void cleanup_async_eq(struct dh_core_dev *dev, struct dh_eq_async *eq,
+							 const char *name)
+{
+	dh_eq_disable(dev, &eq->core, &eq->irq_nb);
+}
+
+static void destroy_async_eqs(struct dh_core_dev *dev)
+{
+	struct dh_eq_table *table = &dev->eq_table;
+	struct dh_mpf_eq_table *table_priv = table->priv;
+
+	cleanup_async_eq(dev, &table_priv->async_risc_eq, "riscv");
+	cleanup_async_eq(dev, &table_priv->async_pf_eq, "pf");
+	cleanup_async_eq(dev, &table_priv->async_eq1, "eq1");
+	cleanup_async_eq(dev, &table_priv->async_eq2, "eq2");
+	cleanup_async_eq(dev, &table_priv->async_eq3, "eq3");
+	cleanup_async_eq(dev, &table_priv->async_eq4, "eq4");
+	destroy_async_eq(dev);
+	dh_irqs_release_vectors(&table_priv->async_risc_irq, 1);
+	dh_irqs_release_vectors(&table_priv->async_pf_irq, 1);
+	dh_irqs_release_vectors(&table_priv->async_irq1, 1);
+	dh_irqs_release_vectors(&table_priv->async_irq2, 1);
+	dh_irqs_release_vectors(&table_priv->async_irq3, 1);
+	dh_irqs_release_vectors(&table_priv->async_irq4, 1);
+}
+
+void destroy_comp_eqs(struct dh_core_dev *dev)
+{
+}
+
+void dh_mpf_eq_table_destroy(struct dh_core_dev *dev)
+{
+	destroy_comp_eqs(dev);
+	destroy_async_eqs(dev);
+}
+
+int32_t dh_mpf_eq_table_create(struct dh_core_dev *dev)
+{
+	int32_t err = 0;
+
+	err = create_async_eqs(dev);
+	if (err != 0) {
+		dh_err(dev, "Failed to create async EQs\n");
+		goto err_async_eqs;
+	}
+
+	err = create_comp_eqs(dev);
+	if (err != 0) {
+		dh_err(dev, "Failed to create completion EQs\n");
+		goto err_comp_eqs;
+	}
+
+	return 0;
+
+err_comp_eqs:
+	destroy_async_eqs(dev);
+err_async_eqs:
+	return err;
+}
+
+/*create eventq*/
+static int32_t create_async_eq(struct dh_core_dev *dev, struct dh_irq *risc,
+							   struct dh_irq *pf)
+{
+	struct dh_eq_table *eq_table = &dev->eq_table;
+	struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dev);
+	struct msix_para in = { 0 };
+	int32_t err = 0;
+
+	in.vector_risc = risc->index;
+	in.vector_pfvf = pf->index;
+	in.vector_mpf = 0xff;
+	in.driver_type = MSG_CHAN_END_PF; // TODO
+	in.pdev = dev->pdev;
+	in.virt_addr = mpf_dev->pci_ioremap_addr + ZXDH_BAR1_CHAN_OFFSET;
+	in.pcie_id = mpf_dev->pcie_id;
+	DH_LOG_INFO(MODULE_MPF, "pcie_id = 0x%x\n", mpf_dev->pcie_id);
+
+	mutex_lock(&eq_table->lock);
+
+	err = zxdh_bar_enable_chan(&in, &mpf_dev->vport);
+
+	mutex_unlock(&eq_table->lock);
+
+	return err;
+}
+
+static int32_t dh_eq_async_riscv_int(struct notifier_block *nb,
+									 unsigned long action, void *data)
+{
+	struct dh_eq_async *eq_riscv_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
+	struct dh_eq_table *eq_table = &dev->eq_table;
+
+	atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF],
+							   DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF, NULL);
+
+	return 0;
+}
+
+static int32_t dh_eq_async_mpf_int(struct notifier_block *nb,
+								   unsigned long action, void *data)
+{
+	struct dh_eq_async *eq_riscv_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
+	struct dh_eq_table *eq_table = &dev->eq_table;
+
+	atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_PF_TO_MPF],
+							   DH_EVENT_TYPE_NOTIFY_PF_TO_MPF, NULL);
+
+	return 0;
+}
+
+static int32_t dh_eq_async_int1(struct notifier_block *nb, unsigned long action,
+								void *data)
+{
+	struct dh_eq_async *eq_riscv_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
+	struct dh_eq_table *eq_table = &dev->eq_table;
+
+	atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_1],
+							   DH_EVENT_TYPE_NOTIFY_1, dev);
+
+	return 0;
+}
+
+static int32_t dh_eq_async_int2(struct notifier_block *nb, unsigned long action,
+								void *data)
+{
+	struct dh_eq_async *eq_riscv_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
+	struct dh_eq_table *eq_table = &dev->eq_table;
+
+	atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_2],
+							   DH_EVENT_TYPE_NOTIFY_2, dev);
+
+	return 0;
+}
+
+static int32_t dh_eq_async_int3(struct notifier_block *nb, unsigned long action,
+								void *data)
+{
+	struct dh_eq_async *eq_riscv_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
+	struct dh_eq_table *eq_table = &dev->eq_table;
+
+	atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_3],
+							   DH_EVENT_TYPE_NOTIFY_3, dev);
+
+	return 0;
+}
+
+static int32_t dh_eq_async_int4(struct notifier_block *nb, unsigned long action,
+								void *data)
+{
+	struct dh_eq_async *eq_riscv_async =
+			container_of(nb, struct dh_eq_async, irq_nb);
+	struct dh_core_dev *dev = (struct dh_core_dev *)eq_riscv_async->priv;
+	struct dh_eq_table *eq_table = &dev->eq_table;
+
+	atomic_notifier_call_chain(&eq_table->nh[DH_EVENT_TYPE_NOTIFY_4],
+							   DH_EVENT_TYPE_NOTIFY_4, dev);
+
+	return 0;
+}
+
+static int32_t create_async_eqs(struct dh_core_dev *dev)
+{
+	struct dh_eq_table *table = &dev->eq_table;
+	struct dh_mpf_eq_table *table_priv = table->priv;
+	struct dh_eq_param param = {};
+	int32_t err = 0;
+
+	dh_dbg(dev, "start\r\n");
+	table_priv->async_risc_irq = dh_mpf_async_irq_request(dev);
+	if (IS_ERR_OR_NULL(table_priv->async_risc_irq)) {
+		dh_err(dev, "Failed to get async_risc_irq\n");
+		return PTR_ERR(table_priv->async_risc_irq);
+	}
+
+	table_priv->async_pf_irq = dh_mpf_async_irq_request(dev);
+	if (IS_ERR_OR_NULL(table_priv->async_pf_irq)) {
+		err = PTR_ERR(table_priv->async_pf_irq);
+		dh_err(dev, "Failed to get async_pf_irq\n");
+		goto err_irq_request;
+	}
+
+	table_priv->async_irq1 = dh_mpf_async_irq_request(dev);
+	if (IS_ERR_OR_NULL(table_priv->async_irq1)) {
+		err = PTR_ERR(table_priv->async_irq1);
+		dh_err(dev, "Failed to get async_irq1\n");
+		goto err_irq_request1;
+	}
+
+	table_priv->async_irq2 = dh_mpf_async_irq_request(dev);
+	if (IS_ERR_OR_NULL(table_priv->async_irq2)) {
+		err = PTR_ERR(table_priv->async_irq2);
+		dh_err(dev, "Failed to get async_irq2\n");
+		goto err_irq_request2;
+	}
+
+	table_priv->async_irq3 = dh_mpf_async_irq_request(dev);
+	if (IS_ERR_OR_NULL(table_priv->async_irq3)) {
+		err = PTR_ERR(table_priv->async_irq3);
+		dh_err(dev, "Failed to get async_irq3\n");
+		goto err_irq_request3;
+	}
+
+	table_priv->async_irq4 = dh_mpf_async_irq_request(dev);
+	if (IS_ERR_OR_NULL(table_priv->async_irq4)) {
+		err = PTR_ERR(table_priv->async_irq4);
+		dh_err(dev, "Failed to get async_irq4\n");
+		goto err_irq_request4;
+	}
+
+	err = create_async_eq(dev, table_priv->async_risc_irq,
+						  table_priv->async_pf_irq);
+	if (err != 0) {
+		dh_err(dev, "Failed to create async_eq\n");
+		goto err_create_async_eq;
+	}
+
+	param = (struct dh_eq_param){
+		.irq = table_priv->async_risc_irq,
+		.nent = 10,
+		.event_type = DH_EVENT_QUEUE_TYPE_RISCV /* used for inform dpu */
+	};
+	err = setup_async_eq(dev, &table_priv->async_risc_eq, &param,
+						 dh_eq_async_riscv_int, "riscv", dev);
+	if (err != 0) {
+		dh_err(dev, "Failed to setup async_risc_eq\n");
+		goto err_setup_async_risc_eq;
+	}
+
+	param.irq = table_priv->async_pf_irq,
+	err = setup_async_eq(dev, &table_priv->async_pf_eq, &param,
+						 dh_eq_async_mpf_int, "pf", dev);
+	if (err != 0) {
+		dh_err(dev, "Failed to setup async_pf_eq\n");
+		goto err_setup_async_pf_eq;
+	}
+
+	param.irq = table_priv->async_irq1,
+	err = setup_async_eq(dev, &table_priv->async_eq1, &param, dh_eq_async_int1,
+						 "irq1", dev);
+	if (err != 0) {
+		dh_err(dev, "Failed to setup async_eq1\n");
+		goto err_setup_async_eq1;
+	}
+
+	param.irq = table_priv->async_irq2,
+	err = setup_async_eq(dev, &table_priv->async_eq2, &param, dh_eq_async_int2,
+						 "irq2", dev);
+	if (err != 0) {
+		dh_err(dev, "Failed to setup async_eq1\n");
+		goto err_setup_async_eq2;
+	}
+
+	param.irq = table_priv->async_irq3,
+	err = setup_async_eq(dev, &table_priv->async_eq3, &param, dh_eq_async_int3,
+						 "irq3", dev);
+	if (err != 0) {
+		dh_err(dev, "Failed to setup async_eq3\n");
+		goto err_setup_async_eq3;
+	}
+
+	param.irq = table_priv->async_irq4,
+	err = setup_async_eq(dev, &table_priv->async_eq4, &param, dh_eq_async_int4,
+						 "irq4", dev);
+	if (err != 0) {
+		dh_err(dev, "Failed to setup async_eq4\n");
+		goto err_setup_async_eq4;
+	}
+
+	return 0;
+
+err_setup_async_eq4:
+	cleanup_async_eq(dev, &table_priv->async_eq3, "irq3");
+err_setup_async_eq3:
+	cleanup_async_eq(dev, &table_priv->async_eq2, "irq2");
+err_setup_async_eq2:
+	cleanup_async_eq(dev, &table_priv->async_eq1, "irq1");
+err_setup_async_eq1:
+	cleanup_async_eq(dev, &table_priv->async_pf_eq, "pf");
+err_setup_async_pf_eq:
+	cleanup_async_eq(dev, &table_priv->async_risc_eq, "riscv");
+err_setup_async_risc_eq:
+	destroy_async_eq(dev);
+err_create_async_eq:
+	dh_irqs_release_vectors(&table_priv->async_irq4, 1);
+err_irq_request4:
+	dh_irqs_release_vectors(&table_priv->async_irq3, 1);
+err_irq_request3:
+	dh_irqs_release_vectors(&table_priv->async_irq2, 1);
+err_irq_request2:
+	dh_irqs_release_vectors(&table_priv->async_irq1, 1);
+err_irq_request1:
+	dh_irqs_release_vectors(&table_priv->async_pf_irq, 1);
+err_irq_request:
+	dh_irqs_release_vectors(&table_priv->async_risc_irq, 1);
+	return err;
+}
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/eq.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/eq.h
old mode 100755
new mode 100644
index 4aaaaaee6b4c6426214c934fa70b0d9f56254c91..e962267a1ae63c17db0f671bdcedfe720c39818b
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/eq.h
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/eq.h
@@ -1,19 +1,19 @@
-#ifndef __ZXDH_MPF_EQ_H__
-#define __ZXDH_MPF_EQ_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/driver.h>
-
-int32_t dh_mpf_eq_table_init(struct dh_core_dev *dev);
-
-int32_t dh_mpf_eq_table_create(struct dh_core_dev *dev);
-void dh_mpf_eq_table_destroy(struct dh_core_dev *dev);
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef __ZXDH_MPF_EQ_H__
+#define __ZXDH_MPF_EQ_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/driver.h>
+
+int32_t dh_mpf_eq_table_init(struct dh_core_dev *dev);
+
+int32_t dh_mpf_eq_table_create(struct dh_core_dev *dev);
+void dh_mpf_eq_table_destroy(struct dh_core_dev *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug.c
index 77f0f3d9106fd27b26de14c415623b552b3119c2..6a64abaf02850fb8aa354970841e9175da56e056 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug.c
@@ -2,7 +2,8 @@
 #include "fuc_hotplug.h"
 #include "fuc_hotplug_commom.h"
 
-extern int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in, struct zxdh_msg_recviver_mem *result);
+extern int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in,
+									   struct zxdh_msg_recviver_mem *result);
 extern int get_fuc_hp_ret(void);
 extern int reset_fuc_hp_ret(void);
 static int fuc_hotplug_trigger(u64 arg);
@@ -10,215 +11,215 @@ static int fuc_hotplug_get_pf_state(u64 arg);
 static int ep_hotplug(u64 arg);
 
 static struct func_sel ioctl_func_sel[] = {
-    {FUC_HP_IOCTL_CMD0,  fuc_hotplug_trigger         },
-    {FUC_HP_IOCTL_CMD1,  fuc_hotplug_get_pf_state    },
-    {FUC_HP_IOCTL_CMD2,  ep_hotplug                  },
+	{ FUC_HP_IOCTL_CMD0, fuc_hotplug_trigger },
+	{ FUC_HP_IOCTL_CMD1, fuc_hotplug_get_pf_state },
+	{ FUC_HP_IOCTL_CMD2, ep_hotplug },
 };
 
-static int pcie_mt_send_msg(void *msg_info, u32 msg_size, void *resp_msg, u32 resp_size)
+static int pcie_mt_send_msg(void *msg_info, u32 msg_size, void *resp_msg,
+							u32 resp_size)
 {
-    struct zxdh_pci_bar_msg in = {0};
-    struct zxdh_msg_recviver_mem result = {0};
-    struct pci_dev *pdev = NULL;
-    void __iomem *bar_virt_addr = NULL;
-    u16 ret = 0, pcie_id = 0;
-    u64 bar_addr = 0;
-
-    if (msg_info == NULL)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "The msg_info is NULL\n");
-        return -EINVAL;
-    }
-
-    pdev = pci_get_device(FUC_HP_VENDOR_ID, FUC_HP_DEVICE_ID, NULL);
-    if (pdev == NULL)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Can not find devices: deviceID %x, VendorID: %x\n", FUC_HP_VENDOR_ID, FUC_HP_DEVICE_ID);
-        return -EINVAL;
-    }
-
-    bar_addr = pci_resource_start(pdev, 0);
-    DH_LOG_INFO(MODULE_FUC_HP, "bar_addr->0x%llx\n", bar_addr);
-    bar_virt_addr = ioremap(bar_addr, FUC_HP_IOREMAP_SIZE);
-
-    /* 填充用户参数in */
-    in.virt_addr = (u64)bar_virt_addr + FUC_HP_BAR_MSG_OFFSET; /* 使用PF1的bar0偏移8k */
-    in.payload_addr = msg_info;                                /* 消息静荷buffer地址 */
-    in.payload_len = msg_size;                                 /* 消息长度 */
-    in.src = MSG_CHAN_END_PF;                                  /* 从mpf通道下发 */
-    in.dst = MSG_CHAN_END_RISC;                                /* 消息发到risc */
-    in.event_id = FUC_HP_EVENT_ID;                             /* 调用PCIE的消息处理函数 */
-    in.src_pcieid = pcie_id;
-
-    result.buffer_len = BUF_SIZE;                                /* 用户准备一个存放消息回复的buffer, buffer长度 */
-    result.recv_buffer = kmalloc(result.buffer_len, GFP_KERNEL); /* 消息回复buffer地址 */
-    if (!result.recv_buffer)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Failed to allocate recv_buffer\n");
-        return -EINVAL;
-    }
-
-    memset(result.recv_buffer, 0, result.buffer_len);
-
-    ret = zxdh_bar_chan_sync_msg_send(&in, &result); /* 发送同步消息 */
-
-    iounmap(bar_virt_addr);
-
-    /* 如果接口返回值不为0，则说明消息失败 */
-    if (ret != 0)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "pcie send msg failed, ret:%d.\n", ret);
-        goto exit;
-    }
-
-    /* 如果消息发送成功， 从recv_buffer + 1的位置往后两字节取回复数据长度， recv_buffer + 4的位置开始取数据内容 */
-    if (*((u8 *)(result.recv_buffer + 4)) == 0x1)
-    {
-        memcpy(resp_msg, result.recv_buffer + 4, resp_size);
-        ret = 0;
-    }
-    else
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "pcie  result failed!\n");
-        ret = -EINVAL;
-    }
+	struct zxdh_pci_bar_msg in = { 0 };
+	struct zxdh_msg_recviver_mem result = { 0 };
+	struct pci_dev *pdev = NULL;
+	void __iomem *bar_virt_addr = NULL;
+	u16 ret = 0, pcie_id = 0;
+	u64 bar_addr = 0;
+
+	if (msg_info == NULL) {
+		DH_LOG_ERR(MODULE_FUC_HP, "The msg_info is NULL\n");
+		return -EINVAL;
+	}
+
+	pdev = pci_get_device(FUC_HP_VENDOR_ID, FUC_HP_DEVICE_ID, NULL);
+	if (pdev == NULL) {
+		DH_LOG_ERR(MODULE_FUC_HP,
+				   "Can not find devices: deviceID %x, VendorID: %x\n",
+				   FUC_HP_VENDOR_ID, FUC_HP_DEVICE_ID);
+		return -EINVAL;
+	}
+
+	bar_addr = pci_resource_start(pdev, 0);
+	DH_LOG_INFO(MODULE_FUC_HP, "bar_addr->0x%llx\n", bar_addr);
+	bar_virt_addr = ioremap(bar_addr, FUC_HP_IOREMAP_SIZE);
+
+	/* 填充用户参数in */
+	in.virt_addr = (u64)bar_virt_addr +
+				   FUC_HP_BAR_MSG_OFFSET; /* 使用PF1的bar0偏移8k */
+	in.payload_addr = msg_info; /* 消息静荷buffer地址 */
+	in.payload_len = msg_size; /* 消息长度 */
+	in.src = MSG_CHAN_END_PF; /* 从mpf通道下发 */
+	in.dst = MSG_CHAN_END_RISC; /* 消息发到risc */
+	in.event_id = FUC_HP_EVENT_ID; /* 调用PCIE的消息处理函数 */
+	in.src_pcieid = pcie_id;
+
+	result.buffer_len =
+			BUF_SIZE; /* 用户准备一个存放消息回复的buffer, buffer长度 */
+	result.recv_buffer =
+			kmalloc(result.buffer_len, GFP_KERNEL); /* 消息回复buffer地址 */
+	if (!result.recv_buffer) {
+		DH_LOG_ERR(MODULE_FUC_HP, "Failed to allocate recv_buffer\n");
+		return -EINVAL;
+	}
+
+	memset(result.recv_buffer, 0, result.buffer_len);
+
+	ret = zxdh_bar_chan_sync_msg_send(&in, &result); /* 发送同步消息 */
+
+	iounmap(bar_virt_addr);
+
+	/* 如果接口返回值不为0，则说明消息失败 */
+	if (ret != 0) {
+		DH_LOG_ERR(MODULE_FUC_HP, "pcie send msg failed, ret:%d.\n", ret);
+		goto exit;
+	}
+
+	/* 如果消息发送成功， 从recv_buffer + 1的位置往后两字节取回复数据长度，
+   * recv_buffer + 4的位置开始取数据内容 */
+	if (*((u8 *)(result.recv_buffer + 4)) == 0x1) {
+		memcpy(resp_msg, result.recv_buffer + 4, resp_size);
+		ret = 0;
+	} else {
+		DH_LOG_ERR(MODULE_FUC_HP, "pcie  result failed!\n");
+		ret = -EINVAL;
+	}
 
 exit:
-    kfree(result.recv_buffer);
-    result.recv_buffer = NULL;
-    return ret;
+	kfree(result.recv_buffer);
+	result.recv_buffer = NULL;
+	return ret;
 }
 
 static int fuc_hotplug_trigger(u64 arg)
 {
-    int ret = 0;
-    int resp_msg = 0;
-    struct fuc_hotplug_bar_msg fuc_hotplug_bar_msg = {0};
-
-    if (copy_from_user(&fuc_hotplug_bar_msg, (void __user *)arg, sizeof(struct fuc_hotplug_bar_msg)))
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Can not copy from user\n");
-        return -EFAULT;
-    }
-
-    ret = pcie_mt_send_msg(&fuc_hotplug_bar_msg, sizeof(struct fuc_hotplug_bar_msg), &resp_msg, sizeof(int));
-    if (ret != 0)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "send failed\n");
-        fuc_hotplug_bar_msg.cpl_chk = FUC_HP_RET_FAILED;
-    }
-    else
-    {
-        fuc_hotplug_bar_msg.cpl_chk = FUC_HP_RET_FINISH;
-    }
-
-    if (copy_to_user((void __user *)arg, &fuc_hotplug_bar_msg, sizeof(struct fuc_hotplug_bar_msg)))
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Can not copy to user\n");
-        ret = -EFAULT;
-    }
-
-    return ret;
+	int ret = 0;
+	int resp_msg = 0;
+	struct fuc_hotplug_bar_msg fuc_hotplug_bar_msg = { 0 };
+
+	if (copy_from_user(&fuc_hotplug_bar_msg, (void __user *)arg,
+					   sizeof(struct fuc_hotplug_bar_msg))) {
+		DH_LOG_ERR(MODULE_FUC_HP, "Can not copy from user\n");
+		return -EFAULT;
+	}
+
+	ret = pcie_mt_send_msg(&fuc_hotplug_bar_msg,
+						   sizeof(struct fuc_hotplug_bar_msg), &resp_msg,
+						   sizeof(int));
+	if (ret != 0) {
+		DH_LOG_ERR(MODULE_FUC_HP, "send failed\n");
+		fuc_hotplug_bar_msg.cpl_chk = FUC_HP_RET_FAILED;
+	} else {
+		fuc_hotplug_bar_msg.cpl_chk = FUC_HP_RET_FINISH;
+	}
+
+	if (copy_to_user((void __user *)arg, &fuc_hotplug_bar_msg,
+					 sizeof(struct fuc_hotplug_bar_msg))) {
+		DH_LOG_ERR(MODULE_FUC_HP, "Can not copy to user\n");
+		ret = -EFAULT;
+	}
+
+	return ret;
 }
 
 static int fuc_hotplug_get_pf_state(u64 arg)
 {
-    int ret = FUC_HP_OK;
-    struct get_pf_state_resp get_pf_state_resp = {0};
-    struct get_pf_state_info get_pf_state_info = {0};
-
-    if (copy_from_user(&get_pf_state_info, (void __user *)arg, sizeof(struct get_pf_state_info)))
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Can not copy from user\n");
-        return -EFAULT;
-    }
-
-    ret = pcie_mt_send_msg(&get_pf_state_info, sizeof(struct get_pf_state_info), (void *)&get_pf_state_resp, sizeof(struct get_pf_state_resp));
-    if (ret)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Remote test failed\n");
-        goto finish;
-    }
-
-    if (get_pf_state_info.ep_no >= MAX_FUCTION_HOTPLUG_EP_NUMS)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Invalid ep_id\n");
-        ret = -EINVAL;
-        goto finish;
-    }
-
-    get_pf_state_info.cpl_chk = ( get_pf_state_resp.pf_state_of_ep[get_pf_state_info.ep_no]  >> get_pf_state_info.pf_no) & 0x1;
-    if (copy_to_user((void __user *)arg, &get_pf_state_info, sizeof(struct get_pf_state_info)))
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Can not copy to user\n");
-        ret = -EFAULT;
-    }
-
-    return ret;
+	int ret = FUC_HP_OK;
+	struct get_pf_state_resp get_pf_state_resp = { 0 };
+	struct get_pf_state_info get_pf_state_info = { 0 };
+
+	if (copy_from_user(&get_pf_state_info, (void __user *)arg,
+					   sizeof(struct get_pf_state_info))) {
+		DH_LOG_ERR(MODULE_FUC_HP, "Can not copy from user\n");
+		return -EFAULT;
+	}
+
+	ret = pcie_mt_send_msg(&get_pf_state_info, sizeof(struct get_pf_state_info),
+						   (void *)&get_pf_state_resp,
+						   sizeof(struct get_pf_state_resp));
+	if (ret) {
+		DH_LOG_ERR(MODULE_FUC_HP, "Remote test failed\n");
+		goto finish;
+	}
+
+	if (get_pf_state_info.ep_no >= MAX_FUCTION_HOTPLUG_EP_NUMS) {
+		DH_LOG_ERR(MODULE_FUC_HP, "Invalid ep_id\n");
+		ret = -EINVAL;
+		goto finish;
+	}
+
+	get_pf_state_info.cpl_chk =
+			(get_pf_state_resp.pf_state_of_ep[get_pf_state_info.ep_no] >>
+			 get_pf_state_info.pf_no) &
+			0x1;
+	if (copy_to_user((void __user *)arg, &get_pf_state_info,
+					 sizeof(struct get_pf_state_info))) {
+		DH_LOG_ERR(MODULE_FUC_HP, "Can not copy to user\n");
+		ret = -EFAULT;
+	}
+
+	return ret;
 
 finish:
-    get_pf_state_info.cpl_chk = FUNCTION_INVALID_TYPE;
-    if (copy_to_user((void __user *)arg, &get_pf_state_info, sizeof(struct get_pf_state_info)))
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Can not copy to user\n");
-        ret = -EFAULT;
-    }
-
-    return ret;
+	get_pf_state_info.cpl_chk = FUNCTION_INVALID_TYPE;
+	if (copy_to_user((void __user *)arg, &get_pf_state_info,
+					 sizeof(struct get_pf_state_info))) {
+		DH_LOG_ERR(MODULE_FUC_HP, "Can not copy to user\n");
+		ret = -EFAULT;
+	}
+
+	return ret;
 }
 
 static int ep_hotplug(u64 arg)
 {
-    int ret = FUC_HP_OK;
-    struct ep_hotplug_resp ep_hotplug_resp = {0};
-    struct ep_hotplug_info ep_hotplug_info = {0};
-
-    if (copy_from_user(&ep_hotplug_info, (void __user *)arg, sizeof(struct ep_hotplug_info)))
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Can not copy from user\n");
-        return -EFAULT;
-    }
-
-    ret = pcie_mt_send_msg(&ep_hotplug_info, sizeof(struct ep_hotplug_info), (void *)&ep_hotplug_resp, sizeof(struct ep_hotplug_resp));
-    if (ret)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Remote test failed\n");
-        goto finish;
-    }
-
-    ep_hotplug_info.cpl_chk = FUC_HP_RET_FINISH;
-    if (copy_to_user((void __user *)arg, &ep_hotplug_info, sizeof(struct ep_hotplug_info)))
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Can not copy to user\n");
-        ret = -EFAULT;
-    }
-
-    return ret;
+	int ret = FUC_HP_OK;
+	struct ep_hotplug_resp ep_hotplug_resp = { 0 };
+	struct ep_hotplug_info ep_hotplug_info = { 0 };
+
+	if (copy_from_user(&ep_hotplug_info, (void __user *)arg,
+					   sizeof(struct ep_hotplug_info))) {
+		DH_LOG_ERR(MODULE_FUC_HP, "Can not copy from user\n");
+		return -EFAULT;
+	}
+
+	ret = pcie_mt_send_msg(&ep_hotplug_info, sizeof(struct ep_hotplug_info),
+						   (void *)&ep_hotplug_resp,
+						   sizeof(struct ep_hotplug_resp));
+	if (ret) {
+		DH_LOG_ERR(MODULE_FUC_HP, "Remote test failed\n");
+		goto finish;
+	}
+
+	ep_hotplug_info.cpl_chk = FUC_HP_RET_FINISH;
+	if (copy_to_user((void __user *)arg, &ep_hotplug_info,
+					 sizeof(struct ep_hotplug_info))) {
+		DH_LOG_ERR(MODULE_FUC_HP, "Can not copy to user\n");
+		ret = -EFAULT;
+	}
+
+	return ret;
 
 finish:
-    ep_hotplug_info.cpl_chk = FUC_HP_RET_FAILED;
-    if (copy_to_user((void __user *)arg, &ep_hotplug_info, sizeof(struct ep_hotplug_info)))
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Can not copy to user\n");
-        ret = -EFAULT;
-    }
-
-    return ret;
+	ep_hotplug_info.cpl_chk = FUC_HP_RET_FAILED;
+	if (copy_to_user((void __user *)arg, &ep_hotplug_info,
+					 sizeof(struct ep_hotplug_info))) {
+		DH_LOG_ERR(MODULE_FUC_HP, "Can not copy to user\n");
+		ret = -EFAULT;
+	}
+
+	return ret;
 }
 
-
 long fuc_hp_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
 {
-    u32 i = 0;
-    u32 ioctl_func_nums = sizeof(ioctl_func_sel) / sizeof(struct func_sel);
-
-    for (i = 0; i < ioctl_func_nums; i++)
-    {
-        if (ioctl_func_sel[i].cmd == cmd)
-        {
-            return ioctl_func_sel[i].ioctl_func(arg);
-        }
-    }
-
-    return -EINVAL;
+	u32 i = 0;
+	u32 ioctl_func_nums = sizeof(ioctl_func_sel) / sizeof(struct func_sel);
+
+	for (i = 0; i < ioctl_func_nums; i++) {
+		if (ioctl_func_sel[i].cmd == cmd) {
+			return ioctl_func_sel[i].ioctl_func(arg);
+		}
+	}
+
+	return -EINVAL;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug.h
index d2ec80b49b9b7084c8952c492760d7a1aecbb98c..faca3f791c57e4e7dd62457dee53bb619c678927 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug.h
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug.h
@@ -25,17 +25,17 @@ extern "C" {
 #include <linux/errno.h>
 #include <linux/dinghai/log.h>
 
-#define FUC_HP_EVENT_ID       44
-#define BUF_SIZE              0x1000
+#define FUC_HP_EVENT_ID 44
+#define BUF_SIZE 0x1000
 
 /* bar消息通道使用pf信息 */
 #define FUC_HP_BAR_MSG_OFFSET (0x2000)
-#define FUC_HP_VENDOR_ID      (0x1cf2)
-#define FUC_HP_DEVICE_ID      (0x8044)
-#define FUC_HP_IOREMAP_SIZE   (0x3000)
+#define FUC_HP_VENDOR_ID (0x1cf2)
+#define FUC_HP_DEVICE_ID (0x8044)
+#define FUC_HP_IOREMAP_SIZE (0x3000)
 
-#define FUC_HP_POLLING_SPAN   100
-#define FUC_HP_TIMEOUT_TH     3000
+#define FUC_HP_POLLING_SPAN 100
+#define FUC_HP_TIMEOUT_TH 3000
 
 /* data type */
 typedef unsigned long long int u64;
@@ -51,8 +51,8 @@ typedef unsigned char u8;
 typedef signed char s8;
 
 struct func_sel {
-    unsigned int cmd;
-    int (*ioctl_func)(unsigned long long arg);
+	unsigned int cmd;
+	int (*ioctl_func)(unsigned long long arg);
 };
 
 #ifdef __cplusplus
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_commom.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_commom.h
index c759a564e06c08737057bb3da1575a8cfe1a7451..c6aa9499b7eff18ebcd8b3b3474e18f24f135a92 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_commom.h
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_commom.h
@@ -1,79 +1,77 @@
 #ifndef __FUC_HOTPLUG_COMMOM_H
 #define __FUC_HOTPLUG_COMMOM_H
 
-#define ARG_START_NO                     3
-#define ARG_TYPE_NO                      1
-#define FUC_HP_OK                        0
-#define FUC_HP_FAILED                    -1
+#define ARG_START_NO 3
+#define ARG_TYPE_NO 1
+#define FUC_HP_OK 0
+#define FUC_HP_FAILED -1
 
+#define FUC_HP_IOCTL_TYPE '>'
+#define FUC_HP_IOCTL_MAGIC 117 /* random */
+#define FUC_HP_IOCTL_CMD0 (_IO(FUC_HP_IOCTL_TYPE, FUC_HP_IOCTL_MAGIC + 0))
+#define FUC_HP_IOCTL_CMD1 (_IO(FUC_HP_IOCTL_TYPE, FUC_HP_IOCTL_MAGIC + 1))
+#define FUC_HP_IOCTL_CMD2 (_IO(FUC_HP_IOCTL_TYPE, FUC_HP_IOCTL_MAGIC + 2))
 
-#define FUC_HP_IOCTL_TYPE                '>'
-#define FUC_HP_IOCTL_MAGIC               117 /* random */
-#define FUC_HP_IOCTL_CMD0                (_IO(FUC_HP_IOCTL_TYPE, FUC_HP_IOCTL_MAGIC + 0))
-#define FUC_HP_IOCTL_CMD1                (_IO(FUC_HP_IOCTL_TYPE, FUC_HP_IOCTL_MAGIC + 1))
-#define FUC_HP_IOCTL_CMD2                (_IO(FUC_HP_IOCTL_TYPE, FUC_HP_IOCTL_MAGIC + 2))
+#define MIN_EP_ID 5
+#define MAX_FUCTION_HOTPLUG_EP_NUMS 4
 
-#define MIN_EP_ID                        5
-#define MAX_FUCTION_HOTPLUG_EP_NUMS      4
-
-#define FUC_HOTPLUG_MEMBER_NUMS          10
+#define FUC_HOTPLUG_MEMBER_NUMS 10
 struct fuc_hotplug_bar_msg {
-    unsigned int  cmd;
-    unsigned int  fuc_hotplug_info;
-    unsigned int  timeout;
-    unsigned int  cpl_chk;
+	unsigned int cmd;
+	unsigned int fuc_hotplug_info;
+	unsigned int timeout;
+	unsigned int cpl_chk;
 };
 
-#define FUC_HOTPLUG_TIMEOUT_NUMS          1
+#define FUC_HOTPLUG_TIMEOUT_NUMS 1
 struct fuc_hotplug_set_timeout {
-    unsigned int  timeout;
-    unsigned int  cpl_chk;
+	unsigned int timeout;
+	unsigned int cpl_chk;
 };
 
 struct get_pf_state_info {
-    unsigned int cmd;
-    unsigned int ep_no;
-    unsigned int pf_no;
-    unsigned int cpl_chk;
+	unsigned int cmd;
+	unsigned int ep_no;
+	unsigned int pf_no;
+	unsigned int cpl_chk;
 };
 
 struct get_pf_state_resp {
-    uint8_t check_cpl;
-    uint8_t pf_state_of_ep[MAX_FUCTION_HOTPLUG_EP_NUMS];
+	uint8_t check_cpl;
+	uint8_t pf_state_of_ep[MAX_FUCTION_HOTPLUG_EP_NUMS];
 };
 
-#define EP_HOTPLUG_MEMBER_NUMS          4
+#define EP_HOTPLUG_MEMBER_NUMS 4
 struct ep_hotplug_info {
-    unsigned int cmd;
-    unsigned int ops_type;
-    unsigned int ep_no;
-    unsigned int cpl_chk;
+	unsigned int cmd;
+	unsigned int ops_type;
+	unsigned int ep_no;
+	unsigned int cpl_chk;
 };
 
 struct ep_hotplug_resp {
-    uint8_t check_cpl;
+	uint8_t check_cpl;
 };
 
-
 typedef enum {
-    FUC_HP_RET_TIMEOUT = 0,
-    FUC_HP_RET_FINISH,
-    FUC_HP_RET_FAILED,
-    INVALID_FUC_HP_RETURE
+	FUC_HP_RET_TIMEOUT = 0,
+	FUC_HP_RET_FINISH,
+	FUC_HP_RET_FAILED,
+	INVALID_FUC_HP_RETURE
 } FUC_HP_RETURE;
 
 typedef enum {
-    FUNCTION_REMOVE = 1,
-    FUNCTION_INSERT,
-    FUNCTION_INVALID_TYPE,
+	FUNCTION_REMOVE = 1,
+	FUNCTION_INSERT,
+	FUNCTION_INVALID_TYPE,
 } FUNCTION_HP_TYPE;
 
 typedef enum {
-    FUC_HP_BAR_MSG_CMD = 1,
-    USED_BY_HOST_HP,
-    GET_STATE_BAR_MSG_CMD,
-    EP_HP_BAR_MSG_CMD,
-    INVALID_CMD,
+	FUC_HP_BAR_MSG_CMD = 1,
+	USED_BY_HOST_HP,
+	GET_STATE_BAR_MSG_CMD,
+	EP_HP_BAR_MSG_CMD,
+	INVALID_CMD,
 } HOTPLUG_CMD;
 
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.c
index af486e05ed8d033674ed15213affda5230dcffbf..ea492efa8275a4071a74e7ac5ac6ab3300b1221f 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.c
@@ -5,72 +5,68 @@ static dev_t dev;
 static struct cdev c_dev;
 static struct class *cl;
 
-extern long fuc_hp_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
+extern long fuc_hp_ioctl(struct file *filp, unsigned int cmd,
+						 unsigned long arg);
 
 static int fuc_hp_open(struct inode *inode, struct file *file)
 {
-    if (inode->i_private)
-    {
-        file->private_data = inode->i_private;
-    }
+	if (inode->i_private) {
+		file->private_data = inode->i_private;
+	}
 
-    return FUC_HP_OK;
+	return FUC_HP_OK;
 }
 
 static int fuc_hp_dev_release(struct inode *i, struct file *f)
 {
-    DH_LOG_INFO(MODULE_FUC_HP, "fuc_hp device released!\n");
-    return FUC_HP_OK;
+	DH_LOG_INFO(MODULE_FUC_HP, "fuc_hp device released!\n");
+	return FUC_HP_OK;
 }
 
-static struct file_operations fuc_hp_fops =
-{
-    .owner = THIS_MODULE,
-    .open = fuc_hp_open,
-    .release = fuc_hp_dev_release,
-    .unlocked_ioctl = fuc_hp_ioctl,
+static struct file_operations fuc_hp_fops = {
+	.owner = THIS_MODULE,
+	.open = fuc_hp_open,
+	.release = fuc_hp_dev_release,
+	.unlocked_ioctl = fuc_hp_ioctl,
 };
 
 int zxdh_host_fuc_hotplug_driver_init(void)
 {
-    int ret = FUC_HP_OK;
+	int ret = FUC_HP_OK;
 
-    if (alloc_chrdev_region(&dev, 0, 1, DEVICE_NAME) < 0)
-    {
-        return -EBUSY;
-    }
+	if (alloc_chrdev_region(&dev, 0, 1, DEVICE_NAME) < 0) {
+		return -EBUSY;
+	}
 
-    if ((cl = class_create(THIS_MODULE, CLASS_NAME)) == NULL)
-    {
-        unregister_chrdev_region(dev, 1);
-        return -ENOMEM;
-    }
+	cl = class_create(THIS_MODULE, CLASS_NAME);
+	if (cl == NULL) {
+		unregister_chrdev_region(dev, 1);
+		return -ENOMEM;
+	}
 
-    if (device_create(cl, NULL, dev, NULL, DEVICE_NAME) == NULL)
-    {
-        class_destroy(cl);
-        unregister_chrdev_region(dev, 1);
-        return -ENOMEM;
-    }
+	if (device_create(cl, NULL, dev, NULL, DEVICE_NAME) == NULL) {
+		class_destroy(cl);
+		unregister_chrdev_region(dev, 1);
+		return -ENOMEM;
+	}
 
-    cdev_init(&c_dev, &fuc_hp_fops);
+	cdev_init(&c_dev, &fuc_hp_fops);
 
-    if (cdev_add(&c_dev, dev, 1) == FUC_HP_FAILED)
-    {
-        device_destroy(cl, dev);
-        class_destroy(cl);
-        unregister_chrdev_region(dev, 1);
-        return -ENOMEM;
-    }
-    DH_LOG_INFO(MODULE_FUC_HP, "fuction_hotplug device registered\n");
-    return ret;
+	if (cdev_add(&c_dev, dev, 1) == FUC_HP_FAILED) {
+		device_destroy(cl, dev);
+		class_destroy(cl);
+		unregister_chrdev_region(dev, 1);
+		return -ENOMEM;
+	}
+	DH_LOG_INFO(MODULE_FUC_HP, "fuction_hotplug device registered\n");
+	return ret;
 }
 
 void zxdh_host_fuc_hotplug_driver_exit(void)
 {
-    cdev_del(&c_dev);
-    device_destroy(cl, dev);
-    class_destroy(cl);
-    unregister_chrdev_region(dev, 1);
-    DH_LOG_INFO(MODULE_FUC_HP, "fuc_hp device unregistered\n");
+	cdev_del(&c_dev);
+	device_destroy(cl, dev);
+	class_destroy(cl);
+	unregister_chrdev_region(dev, 1);
+	DH_LOG_INFO(MODULE_FUC_HP, "fuc_hp device unregistered\n");
 }
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.h
index 58eb6e60be78e4b563bfbb02dad04508c0fd3c54..30483806ef776d2c454d1f29a06c1d1b756a0b73 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.h
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hotplug_ioctl.h
@@ -15,6 +15,6 @@
 #include <linux/dinghai/log.h>
 
 #define DEVICE_NAME "fuc_hp_ioctl"
-#define CLASS_NAME  "fuc_hp_class"
+#define CLASS_NAME "fuc_hp_class"
 
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/build.sh b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/build.sh
old mode 100755
new mode 100644
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/fuc_hp_app.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/fuc_hp_app.c
index 940ad5126f08c069779da2156c96dd915a460db5..956f2f0f8ad023e0def55ab310e7ed1cd29137d8 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/fuc_hp_app.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/fuc_hp_app.c
@@ -7,265 +7,247 @@ static int ep_hp(int argc, char *argv[]);
 
 static int printf_usage(int argc, char *argv[])
 {
-    printf("** dpu_hotplug -s fuc -e epid -p pfid -v vfid -o add/del -t time  \n");
-    printf("** -s 指定拔插场景,fuction级热插拔固定输入:fuc                         \n");
-    printf("** -e 指定epid                                                     \n");
-    printf("** -p 指定pfid                                                     \n");
-    printf("** -v 指定vfid, vfid为0,表示pf                                      \n");
-    printf("**             vfid > 0,表示vf,vfid_real = vfid - 1                \n");
-    printf("** -o 指定插拔操作, add 插入,del 拔出                                 \n");
-    printf("** -t 指定超时时间，单位:s                                            \n");
-    printf("** \n");
-    printf("** dpu_hotplug -s ep -e epid -o add/del                           \n");
-    printf("** -s 指定拔插场景,ep级热插拔固定输入:ep                               \n");
-    printf("** -e 指定epid                                                     \n");
-    printf("** -o 指定插拔操作, add 插入,del 拔出                                 \n");
-    return FUC_HP_OK;
+	printf("** dpu_hotplug -s fuc -e epid -p pfid -v vfid -o add/del -t time  \n");
+	printf("** -s 指定拔插场景,fuction级热插拔固定输入:fuc                       "
+		   "  \n");
+	printf("** -e 指定epid                                                     \n");
+	printf("** -p 指定pfid                                                     \n");
+	printf("** -v 指定vfid, vfid为0,表示pf                                      \n");
+	printf("**             vfid > 0,表示vf,vfid_real = vfid - 1                \n");
+	printf("** -o 指定插拔操作, add 插入,del 拔出                                "
+		   " \n");
+	printf("** -t 指定超时时间，单位:s                                           "
+		   " \n");
+	printf("** \n");
+	printf("** dpu_hotplug -s ep -e epid -o add/del                           \n");
+	printf("** -s 指定拔插场景,ep级热插拔固定输入:ep                             "
+		   "  \n");
+	printf("** -e 指定epid                                                     \n");
+	printf("** -o 指定插拔操作, add 插入,del 拔出                                "
+		   " \n");
+	return FUC_HP_OK;
 };
 
 struct fuc_hp_app_input fuc_hp_app_input[] = {
-    /* ops_type ops_value*/
-    {"-e", 0},
-    {"-p", 0},
-    {"-v", 0},
-    {"-o", 0},
-    {"-t", 0}
+	/* ops_type ops_value*/
+	{ "-e", 0 },
+	{ "-p", 0 },
+	{ "-v", 0 },
+	{ "-o", 0 },
+	{ "-t", 0 }
 };
 
 struct fuc_hp_app_input ep_hp_app_input[] = {
-    /* ops_type ops_value*/
-    {"-e", 0},
-    {"-o", 0},
+	/* ops_type ops_value*/
+	{ "-e", 0 },
+	{ "-o", 0 },
 };
 
 static int parse_fuc_hp_input(struct fuc_hotplug_bar_msg *fuc_hotplug_bar_msg)
 {
-    fuc_hotplug_bar_msg->fuc_hotplug_info = ((fuc_hp_app_input[EP_ID].input_value + MIN_EP_ID) << FUNC_HP_EP_ID_START_BIT)
-                                            | (fuc_hp_app_input[PF_ID].input_value << FUNC_HP_PF_ID_START_BIT);
-
-    if (fuc_hp_app_input[VF_ID].input_value != 0)
-    {
-        fuc_hotplug_bar_msg->fuc_hotplug_info |= ((fuc_hp_app_input[2].input_value - 1) << FUNC_HP_VF_ID_START_BIT);
-        fuc_hotplug_bar_msg->fuc_hotplug_info |= (1 << FUNC_HP_FUNC_TYPE_START_BIT);
-    }
-
-    if (fuc_hp_app_input[OPS_ID].input_value != 0)
-    {
-        fuc_hotplug_bar_msg->fuc_hotplug_info |= (fuc_hp_app_input[OPS_ID].input_value << FUNC_HP_SCENE_CODE_START_BIT);
-    }
-    else
-    {
-        return FUC_HP_FAILED;
-    }
-
-    fuc_hotplug_bar_msg->timeout = fuc_hp_app_input[TIMEOUT_ID].input_value;
-
-    printf("value:0x%x timeout:%ds\n", fuc_hotplug_bar_msg->fuc_hotplug_info, fuc_hotplug_bar_msg->timeout);
-
-    return FUC_HP_OK;
+	fuc_hotplug_bar_msg->fuc_hotplug_info =
+			((fuc_hp_app_input[EP_ID].input_value + MIN_EP_ID)
+			 << FUNC_HP_EP_ID_START_BIT) |
+			(fuc_hp_app_input[PF_ID].input_value << FUNC_HP_PF_ID_START_BIT);
+
+	if (fuc_hp_app_input[VF_ID].input_value != 0) {
+		fuc_hotplug_bar_msg->fuc_hotplug_info |=
+				((fuc_hp_app_input[2].input_value - 1)
+				 << FUNC_HP_VF_ID_START_BIT);
+		fuc_hotplug_bar_msg->fuc_hotplug_info |=
+				(1 << FUNC_HP_FUNC_TYPE_START_BIT);
+	}
+
+	if (fuc_hp_app_input[OPS_ID].input_value != 0) {
+		fuc_hotplug_bar_msg->fuc_hotplug_info |=
+				(fuc_hp_app_input[OPS_ID].input_value
+				 << FUNC_HP_SCENE_CODE_START_BIT);
+	} else {
+		return FUC_HP_FAILED;
+	}
+
+	fuc_hotplug_bar_msg->timeout = fuc_hp_app_input[TIMEOUT_ID].input_value;
+
+	printf("value:0x%x timeout:%ds\n", fuc_hotplug_bar_msg->fuc_hotplug_info,
+		   fuc_hotplug_bar_msg->timeout);
+
+	return FUC_HP_OK;
 }
 
 static int fuc_hp(int argc, char *argv[])
 {
-    int ret = FUC_HP_OK;
-    int fd = 0;
-    int arg_no = ARG_START_NO;
-    int input_no = 0;
-    char *stop_at = NULL;
-    struct fuc_hotplug_bar_msg *fuc_hotplug_bar_msg = NULL;
-
-    fuc_hotplug_bar_msg = malloc(sizeof(struct fuc_hotplug_bar_msg));
-
-    fuc_hotplug_bar_msg->fuc_hotplug_info = 0;
-
-    if (argc != FUC_HOTPLUG_MEMBER_NUMS + ARG_START_NO)
-    {
-        printf("[%s]: Invalid argument count %d\n", __func__, argc);
-        printf_usage(argc, argv);
-        goto failed;
-    }
-
-    while (arg_no < argc)
-    {
-        if (strcmp(argv[arg_no++], fuc_hp_app_input[input_no].input_type) == 0)
-        {
-            if (input_no == OPS_ID)
-            {
-                fuc_hp_app_input[input_no++].input_value = strcmp(argv[arg_no], "add") == 0 ? FUNCTION_INSERT :
-                                                           strcmp(argv[arg_no], "del") == 0  ? FUNCTION_REMOVE : 0;
-                arg_no++;
-            }
-            else
-            {
-                fuc_hp_app_input[input_no++].input_value = strtoul(argv[arg_no++], &stop_at, 0);
-            }
-        }
-        else
-        {
-            printf("[%s]: Invalid input %s\n", __func__, fuc_hp_app_input[input_no].input_type);
-            printf_usage(argc, argv);
-            goto failed;
-        }
-    }
-
-    ret = parse_fuc_hp_input(fuc_hotplug_bar_msg);
-    if(ret != FUC_HP_OK)
-    {
-        printf_usage(argc, argv);
-        goto failed;
-    }
-
-    fuc_hotplug_bar_msg->cmd = FUC_HP_BAR_MSG_CMD;
-
-    fd = open(FUC_HP_IOCTRL_DEV_NAME, O_RDWR, 0);
-    if (fd < 0)
-    {
-        printf("[%s]: Can not open %s \n", __func__, FUC_HP_IOCTRL_DEV_NAME);
-        goto failed;
-    }
-
-    ret = ioctl(fd, FUC_HP_IOCTL_CMD0, fuc_hotplug_bar_msg);
-    if (ret)
-    {
-        printf("[%s]: ERR --> %d\n", __func__, ret);
-        goto finish;
-    }
-
-    if (fuc_hotplug_bar_msg->cpl_chk == FUC_HP_RET_FINISH)
-    {
-        printf("[%s] fuction hotplug finish!!\n", __func__);
-    }
-    else if (fuc_hotplug_bar_msg->cpl_chk == FUC_HP_RET_FAILED)
-    {
-        printf("[%s] fuction hotplug failed!\n", __func__);
-    }
-    else
-    {
-        printf("[%s] fuction hotplug timeout!!!\n", __func__);
-    }
+	int ret = FUC_HP_OK;
+	int fd = 0;
+	int arg_no = ARG_START_NO;
+	int input_no = 0;
+	char *stop_at = NULL;
+	struct fuc_hotplug_bar_msg *fuc_hotplug_bar_msg = NULL;
+
+	fuc_hotplug_bar_msg = malloc(sizeof(struct fuc_hotplug_bar_msg));
+
+	fuc_hotplug_bar_msg->fuc_hotplug_info = 0;
+
+	if (argc != FUC_HOTPLUG_MEMBER_NUMS + ARG_START_NO) {
+		printf("[%s]: Invalid argument count %d\n", __func__, argc);
+		printf_usage(argc, argv);
+		goto failed;
+	}
+
+	while (arg_no < argc) {
+		if (strcmp(argv[arg_no++], fuc_hp_app_input[input_no].input_type) ==
+			0) {
+			if (input_no == OPS_ID) {
+				fuc_hp_app_input[input_no++].input_value =
+						strcmp(argv[arg_no], "add") == 0 ? FUNCTION_INSERT :
+						strcmp(argv[arg_no], "del") == 0 ? FUNCTION_REMOVE :
+															 0;
+				arg_no++;
+			} else {
+				fuc_hp_app_input[input_no++].input_value =
+						strtoul(argv[arg_no++], &stop_at, 0);
+			}
+		} else {
+			printf("[%s]: Invalid input %s\n", __func__,
+				   fuc_hp_app_input[input_no].input_type);
+			printf_usage(argc, argv);
+			goto failed;
+		}
+	}
+
+	ret = parse_fuc_hp_input(fuc_hotplug_bar_msg);
+	if (ret != FUC_HP_OK) {
+		printf_usage(argc, argv);
+		goto failed;
+	}
+
+	fuc_hotplug_bar_msg->cmd = FUC_HP_BAR_MSG_CMD;
+
+	fd = open(FUC_HP_IOCTRL_DEV_NAME, O_RDWR, 0);
+	if (fd < 0) {
+		printf("[%s]: Can not open %s \n", __func__, FUC_HP_IOCTRL_DEV_NAME);
+		goto failed;
+	}
+
+	ret = ioctl(fd, FUC_HP_IOCTL_CMD0, fuc_hotplug_bar_msg);
+	if (ret) {
+		printf("[%s]: ERR --> %d\n", __func__, ret);
+		goto finish;
+	}
+
+	if (fuc_hotplug_bar_msg->cpl_chk == FUC_HP_RET_FINISH) {
+		printf("[%s] fuction hotplug finish!!\n", __func__);
+	} else if (fuc_hotplug_bar_msg->cpl_chk == FUC_HP_RET_FAILED) {
+		printf("[%s] fuction hotplug failed!\n", __func__);
+	} else {
+		printf("[%s] fuction hotplug timeout!!!\n", __func__);
+	}
 
 finish:
-    free(fuc_hotplug_bar_msg);
-    fuc_hotplug_bar_msg = NULL;
-    close(fd);
-    return ret;
+	free(fuc_hotplug_bar_msg);
+	fuc_hotplug_bar_msg = NULL;
+	close(fd);
+	return ret;
 
 failed:
-    free(fuc_hotplug_bar_msg);
-    fuc_hotplug_bar_msg = NULL;
-    return ret;
+	free(fuc_hotplug_bar_msg);
+	fuc_hotplug_bar_msg = NULL;
+	return ret;
 }
 
 static int ep_hp(int argc, char *argv[])
 {
-    int ret = FUC_HP_OK;
-    int fd = 0;
-    int arg_no = ARG_START_NO;
-    int input_no = 0;
-    char *stop_at = NULL;
-    struct ep_hotplug_info *ep_hotplug_info = NULL;
-
-    ep_hotplug_info = malloc(sizeof(struct ep_hotplug_info));
-
-    if (argc != EP_HOTPLUG_MEMBER_NUMS + ARG_START_NO)
-    {
-        printf("[%s]: Invalid argument count %d\n", __func__, argc);
-        printf_usage(argc, argv);
-        goto failed;
-    }
-
-    while (arg_no < argc)
-    {
-        if (strcmp(argv[arg_no++], ep_hp_app_input[input_no].input_type) == 0)
-        {
-            if (input_no == E_OPS_ID)
-            {
-                ep_hp_app_input[input_no++].input_value = strcmp(argv[arg_no], "add") == 0 ? FUNCTION_INSERT :
-                                                          strcmp(argv[arg_no], "del") == 0  ? FUNCTION_REMOVE : 0;
-                arg_no++;
-            }
-            else
-            {
-                ep_hp_app_input[input_no++].input_value = strtoul(argv[arg_no++], &stop_at, 0);
-            }
-        }
-        else
-        {
-            printf("[%s]: Invalid input %s\n", __func__, ep_hp_app_input[input_no].input_type);
-            printf_usage(argc, argv);
-            goto failed;
-        }
-    }
-
-    ep_hotplug_info->cmd = EP_HP_BAR_MSG_CMD;
-    ep_hotplug_info->ep_no = ep_hp_app_input[E_EP_ID].input_value;
-    ep_hotplug_info->ops_type = ep_hp_app_input[E_OPS_ID].input_value;
-
-    fd = open(FUC_HP_IOCTRL_DEV_NAME, O_RDWR, 0);
-    if (fd < 0)
-    {
-        printf("[%s]: Can not open %s \n", __func__, FUC_HP_IOCTRL_DEV_NAME);
-        goto failed;
-    }
-
-    ret = ioctl(fd, FUC_HP_IOCTL_CMD2, ep_hotplug_info);
-    if (ret)
-    {
-        printf("[%s]: ERR --> %d\n", __func__, ret);
-        goto finish;
-    }
-
-    if (ep_hotplug_info->cpl_chk == FUC_HP_RET_FINISH)
-    {
-        printf("[%s] ep hotplug finish!!\n", __func__);
-    }
-    else if (ep_hotplug_info->cpl_chk == FUC_HP_RET_FAILED)
-    {
-        printf("[%s] ep hotplug failed!\n", __func__);
-    }
-    else
-    {
-        printf("[%s] ep hotplug timeout!!!\n", __func__);
-    }
+	int ret = FUC_HP_OK;
+	int fd = 0;
+	int arg_no = ARG_START_NO;
+	int input_no = 0;
+	char *stop_at = NULL;
+	struct ep_hotplug_info *ep_hotplug_info = NULL;
+
+	ep_hotplug_info = malloc(sizeof(struct ep_hotplug_info));
+
+	if (argc != EP_HOTPLUG_MEMBER_NUMS + ARG_START_NO) {
+		printf("[%s]: Invalid argument count %d\n", __func__, argc);
+		printf_usage(argc, argv);
+		goto failed;
+	}
+
+	while (arg_no < argc) {
+		if (strcmp(argv[arg_no++], ep_hp_app_input[input_no].input_type) == 0) {
+			if (input_no == E_OPS_ID) {
+				ep_hp_app_input[input_no++].input_value =
+						strcmp(argv[arg_no], "add") == 0 ? FUNCTION_INSERT :
+						strcmp(argv[arg_no], "del") == 0 ? FUNCTION_REMOVE :
+															 0;
+				arg_no++;
+			} else {
+				ep_hp_app_input[input_no++].input_value =
+						strtoul(argv[arg_no++], &stop_at, 0);
+			}
+		} else {
+			printf("[%s]: Invalid input %s\n", __func__,
+				   ep_hp_app_input[input_no].input_type);
+			printf_usage(argc, argv);
+			goto failed;
+		}
+	}
+
+	ep_hotplug_info->cmd = EP_HP_BAR_MSG_CMD;
+	ep_hotplug_info->ep_no = ep_hp_app_input[E_EP_ID].input_value;
+	ep_hotplug_info->ops_type = ep_hp_app_input[E_OPS_ID].input_value;
+
+	fd = open(FUC_HP_IOCTRL_DEV_NAME, O_RDWR, 0);
+	if (fd < 0) {
+		printf("[%s]: Can not open %s \n", __func__, FUC_HP_IOCTRL_DEV_NAME);
+		goto failed;
+	}
+
+	ret = ioctl(fd, FUC_HP_IOCTL_CMD2, ep_hotplug_info);
+	if (ret) {
+		printf("[%s]: ERR --> %d\n", __func__, ret);
+		goto finish;
+	}
+
+	if (ep_hotplug_info->cpl_chk == FUC_HP_RET_FINISH) {
+		printf("[%s] ep hotplug finish!!\n", __func__);
+	} else if (ep_hotplug_info->cpl_chk == FUC_HP_RET_FAILED) {
+		printf("[%s] ep hotplug failed!\n", __func__);
+	} else {
+		printf("[%s] ep hotplug timeout!!!\n", __func__);
+	}
 
 finish:
-    free(ep_hotplug_info);
-    ep_hotplug_info = NULL;
-    close(fd);
-    return ret;
+	free(ep_hotplug_info);
+	ep_hotplug_info = NULL;
+	close(fd);
+	return ret;
 
 failed:
-    free(ep_hotplug_info);
-    ep_hotplug_info = NULL;
-    return ret;
+	free(ep_hotplug_info);
+	ep_hotplug_info = NULL;
+	return ret;
 }
 
 int main(int argc, char *argv[])
 {
-    int ret = 0;
-    int arg_no = ARG_TYPE_NO;
-
-    if (argc < ARG_START_NO)
-    {
-        printf("[%s]: Invalid argument count %d\n", __func__, argc);
-        printf_usage(argc, argv);
-        ret = FUC_HP_FAILED;
-        goto failed;
-    }
-
-    printf("start\n");
-    if (strcmp(argv[arg_no++], "-s") == 0)
-    {
-        if (strcmp(argv[arg_no], "ep") == 0)
-        {
-            ret = ep_hp(argc, argv);
-        }
-        else if(strcmp(argv[arg_no], "fuc") == 0)
-        {
-            ret = fuc_hp(argc, argv);
-        }
-    }
+	int ret = 0;
+	int arg_no = ARG_TYPE_NO;
+
+	if (argc < ARG_START_NO) {
+		printf("[%s]: Invalid argument count %d\n", __func__, argc);
+		printf_usage(argc, argv);
+		ret = FUC_HP_FAILED;
+		goto failed;
+	}
+
+	printf("start\n");
+	if (strcmp(argv[arg_no++], "-s") == 0) {
+		if (strcmp(argv[arg_no], "ep") == 0) {
+			ret = ep_hp(argc, argv);
+		} else if (strcmp(argv[arg_no], "fuc") == 0) {
+			ret = fuc_hp(argc, argv);
+		}
+	}
 
 failed:
-    return ret;
+	return ret;
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/fuc_hp_app.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/fuc_hp_app.h
index 2770481a9a9c0caaf84fcdac54dfb977e1617e00..96ff2b46c5fa8aeffea9ac407e4dad286c1e0a8f 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/fuc_hp_app.h
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/fuc_hotplug/fuc_hp_app/fuc_hp_app.h
@@ -14,38 +14,33 @@
 #include <unistd.h>
 #include "sys/ioctl.h"
 
-#define FUC_HP_IOCTRL_DEV_NAME             "/dev/fuc_hp_ioctl"
+#define FUC_HP_IOCTRL_DEV_NAME "/dev/fuc_hp_ioctl"
 
-
-#define FUNC_HP_SCENE_CODE_START_BIT                21
-#define FUNC_HP_FUNC_TYPE_START_BIT                 20
-#define FUNC_HP_EP_ID_START_BIT                     16
-#define FUNC_HP_PF_ID_START_BIT                     12
-#define FUNC_HP_VF_ID_START_BIT                     0
+#define FUNC_HP_SCENE_CODE_START_BIT 21
+#define FUNC_HP_FUNC_TYPE_START_BIT 20
+#define FUNC_HP_EP_ID_START_BIT 16
+#define FUNC_HP_PF_ID_START_BIT 12
+#define FUNC_HP_VF_ID_START_BIT 0
 
 struct hp_app_func {
-    char *name;
-    int (*func)(int argc, char *argv[]);
+	char *name;
+	int (*func)(int argc, char *argv[]);
 };
 
 struct fuc_hp_app_input {
-    char         *input_type;
-    unsigned int input_value;
+	char *input_type;
+	unsigned int input_value;
 };
 
 typedef enum {
-    EP_ID = 0,
-    PF_ID,
-    VF_ID,
-    OPS_ID,
-    TIMEOUT_ID,
-    INVALID_FUC_HP_INPUT
+	EP_ID = 0,
+	PF_ID,
+	VF_ID,
+	OPS_ID,
+	TIMEOUT_ID,
+	INVALID_FUC_HP_INPUT
 } FUC_HP_INPUT;
 
-typedef enum {
-    E_EP_ID = 0,
-    E_OPS_ID,
-    E_INVALID_FUC_HP_INPUT
-} EP_HP_INPUT;
+typedef enum { E_EP_ID = 0, E_OPS_ID, E_INVALID_FUC_HP_INPUT } EP_HP_INPUT;
 
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/gdma.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/gdma.c
index 8335534f8bbb3fd7fa5eca36385f71b48ba5f73d..3b7b119b5d8aa2692e4ffc2f09dbcbd05ada3757 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/gdma.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/gdma.c
@@ -17,7 +17,6 @@
 #include <linux/rcupdate.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
-#include <linux/notifier.h>
 
 #include "gdma.h"
 #include "zf_mpf.h"
@@ -27,524 +26,515 @@
  * ep_id-bit[15:12] vfunc_num-bit[11:4] func_num-bit[3:1] vfunc_active-bit0
  * host ep_id:5~8   zf ep_id:9
  */
-#define ZF_GDMA_ZF_USER                         (0x9000)  /* ep4 pf0 */
-#define ZF_GDMA_PF_NUM_SHIFT                    (1)
-#define ZF_GDMA_VF_NUM_SHIFT                    (4)
-#define ZF_GDMA_EP_ID_SHIFT                     (12)
-#define ZF_GDMA_VF_EN                           (1)
-#define ZF_GDMA_VF_MASK                         (1UL << 7)
+#define ZF_GDMA_ZF_USER (0x9000) /* ep4 pf0 */
+#define ZF_GDMA_PF_NUM_SHIFT (1)
+#define ZF_GDMA_VF_NUM_SHIFT (4)
+#define ZF_GDMA_EP_ID_SHIFT (12)
+#define ZF_GDMA_VF_EN (1)
+#define ZF_GDMA_VF_MASK (1UL << 7)
 
 /* Register offset */
-#define ZF_GDMA_BASE_OFFSET                     (0x100000)
-#define ZF_GDMA_CHAN_SHIFT                      (0x80)
-#define ZF_GDMA_EXT_ADDR_OFFSET                 (0x218)
-#define ZF_GDMA_SAR_LOW_OFFSET                  (0x200)
-#define ZF_GDMA_DAR_LOW_OFFSET                  (0x204)
-#define ZF_GDMA_SAR_HIGH_OFFSET                 (0x234)
-#define ZF_GDMA_DAR_HIGH_OFFSET                 (0x238)
-#define ZF_GDMA_XFERSIZE_OFFSET                 (0x208)
-#define ZF_GDMA_CONTROL_OFFSET                  (0x230)
-#define ZF_GDMA_TC_STATUS_OFFSET                (0x0)
-#define ZF_GDMA_STATUS_CLEAN_OFFSET             (0x80)
-#define ZF_GDMA_LINKADDR_LOW_OFFSET             (0x21c)
-#define ZF_GDMA_LINKADDR_HIGH_OFFSET            (0x220)
-#define ZF_GDMA_CHAN_CONTINUE_OFFSET            (0x224)
-#define ZF_GDMA_TC_CNT_OFFSET                   (0x23c)
-#define ZF_GDMA_LLI_USER_OFFSET                 (0x228)
-#define ZF_GDMA_PULSE_WIDTH_OFFSET              (0x1ec)
+#define ZF_GDMA_BASE_OFFSET (0x100000)
+#define ZF_GDMA_CHAN_SHIFT (0x80)
+#define ZF_GDMA_EXT_ADDR_OFFSET (0x218)
+#define ZF_GDMA_SAR_LOW_OFFSET (0x200)
+#define ZF_GDMA_DAR_LOW_OFFSET (0x204)
+#define ZF_GDMA_SAR_HIGH_OFFSET (0x234)
+#define ZF_GDMA_DAR_HIGH_OFFSET (0x238)
+#define ZF_GDMA_XFERSIZE_OFFSET (0x208)
+#define ZF_GDMA_CONTROL_OFFSET (0x230)
+#define ZF_GDMA_TC_STATUS_OFFSET (0x0)
+#define ZF_GDMA_STATUS_CLEAN_OFFSET (0x80)
+#define ZF_GDMA_LINKADDR_LOW_OFFSET (0x21c)
+#define ZF_GDMA_LINKADDR_HIGH_OFFSET (0x220)
+#define ZF_GDMA_CHAN_CONTINUE_OFFSET (0x224)
+#define ZF_GDMA_TC_CNT_OFFSET (0x23c)
+#define ZF_GDMA_LLI_USER_OFFSET (0x228)
 
 /* Control register */
-#define ZF_GDMA_CHAN_ENABLE                     (1UL)
-#define ZF_GDMA_SOFT_CHAN                       (1UL << 1)
-#define ZF_GDMA_TC_INTR_ENABLE                  (1UL << 4)
-#define ZF_GDMA_ERR_INTR_ENABLE                 (1UL << 5)
-#define ZF_GDMA_SBS_SHIFT                       (6)           /* src burst size */
-#define ZF_GDMA_SBL_SHIFT                       (9)           /* src burst length */
-#define ZF_GDMA_DBS_SHIFT                       (13)          /* dest burst size */
-#define ZF_GDMA_BURST_SIZE_MIN                  (0x1)         /* 1 byte */
-#define ZF_GDMA_BURST_SIZE_MEDIUM               (0x4)         /* 4 word */
-#define ZF_GDMA_BURST_SIZE_MAX                  (0x6)         /* 16 word */
-#define ZF_GDMA_DEFAULT_BURST_LEN               (0xf)         /* 16 beats */
-#define ZF_GDMA_TC_CNT_ENABLE                   (1UL << 27)
-#define ZF_GDMA_CHAN_FORCE_CLOSE                (1UL << 31)
+#define ZF_GDMA_CHAN_ENABLE (1UL)
+#define ZF_GDMA_SOFT_CHAN (1UL << 1)
+#define ZF_GDMA_TC_INTR_ENABLE (1UL << 4)
+#define ZF_GDMA_ERR_INTR_ENABLE (1UL << 5)
+#define ZF_GDMA_SBS_SHIFT (6) /* src burst size */
+#define ZF_GDMA_SBL_SHIFT (9) /* src burst length */
+#define ZF_GDMA_DBS_SHIFT (13) /* dest burst size */
+#define ZF_GDMA_BURST_SIZE_MIN (0x1) /* 1 byte */
+#define ZF_GDMA_BURST_SIZE_MEDIUM (0x4) /* 4 word */
+#define ZF_GDMA_BURST_SIZE_MAX (0x6) /* 16 word */
+#define ZF_GDMA_DEFAULT_BURST_LEN (0xf) /* 16 beats */
+#define ZF_GDMA_TC_CNT_ENABLE (1UL << 27)
+#define ZF_GDMA_CHAN_FORCE_CLOSE (1UL << 31)
 
 /* TC count & Error interrupt status register */
-#define ZF_GDMA_SRC_LLI_ERR                     (1UL << 16)
-#define ZF_GDMA_SRC_DATA_ERR                    (1UL << 17)
-#define ZF_GDMA_DST_ADDR_ERR                    (1UL << 18)
-#define ZF_GDMA_ERR_STATUS                      (1UL << 19)
-#define ZF_GDMA_ERR_RPT_ENABLE                  (1UL << 20)
-#define ZF_GDMA_TC_CNT_CLEAN                    (1)
+#define ZF_GDMA_SRC_LLI_ERR (1UL << 16)
+#define ZF_GDMA_SRC_DATA_ERR (1UL << 17)
+#define ZF_GDMA_DST_ADDR_ERR (1UL << 18)
+#define ZF_GDMA_ERR_STATUS (1UL << 19)
+#define ZF_GDMA_ERR_RPT_ENABLE (1UL << 20)
+#define ZF_GDMA_TC_CNT_CLEAN (1)
 
-#define ZF_GDMA_ALIGN_SIZE                      (1)
-#define ZF_GDMA_DMA_BUSWIDTHS                   (BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
-#define ZF_GDMA_BUFF_SIZE_MAX                   (0xfffff)
+#define ZF_GDMA_ALIGN_SIZE (1)
+#define ZF_GDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
+#define ZF_GDMA_BUFF_SIZE_MAX (0xfffff)
 
-#define LOW16_MASK                              (0xffff)
-#define LOW32_MASK                              (0xffffffff)
+#define LOW16_MASK (0xffff)
+#define LOW32_MASK (0xffffffff)
 
-void gchan_irq_tasklet_process(unsigned long data);
-static void zf_gdma_enqueue_buff(struct zf_gdma_chan *gchan);
-
-static struct zf_gdma_chan *to_zf_gdma_chan(struct dma_chan *chan)
+static inline struct zf_gdma_chan *to_zf_gdma_chan(struct dma_chan *chan)
 {
-    return container_of(chan, struct zf_gdma_chan, vc.chan);
+	return container_of(chan, struct zf_gdma_chan, vc.chan);
 }
 
-static struct zf_gdma_desc *to_zf_gdma_desc(struct zxdh_virt_dma_desc *vdesc)
+static inline struct zf_gdma_desc *
+to_zf_gdma_desc(struct zxdh_virt_dma_desc *vdesc)
 {
-    return container_of(vdesc, struct zf_gdma_desc, vd);
+	return container_of(vdesc, struct zf_gdma_desc, vd);
 }
 
-static inline uint32_t zf_gdma_read_reg(struct zf_gdma_chan *gchan, uint16_t chan_id, uint32_t offset)
+static inline uint32_t zf_gdma_read_reg(struct zf_gdma_chan *gchan,
+										uint16_t chan_id, uint32_t offset)
 {
-    uint64_t addr = chan_id * ZF_GDMA_CHAN_SHIFT + offset;
+	uint64_t addr = chan_id * ZF_GDMA_CHAN_SHIFT + offset;
 
-    return *(volatile uint32_t *)(gchan->gdev->base_addr + addr);
+	return *(volatile uint32_t *)(gchan->gdev->base_addr + addr);
 }
 
-static inline void zf_gdma_write_reg(struct zf_gdma_chan *gchan, uint16_t chan_id, uint32_t offset, uint32_t val)
+static inline void zf_gdma_write_reg(struct zf_gdma_chan *gchan,
+									 uint16_t chan_id, uint32_t offset,
+									 uint32_t val)
 {
-    uint64_t addr = chan_id * ZF_GDMA_CHAN_SHIFT + offset;
+	uint64_t addr = chan_id * ZF_GDMA_CHAN_SHIFT + offset;
 
-    *(volatile uint32_t *)(gchan->gdev->base_addr + addr) = val;
+	*(volatile uint32_t *)(gchan->gdev->base_addr + addr) = val;
+	pr_debug("%s:chan%d offset:0x%x val:0x%x\n", __func__, chan_id, offset,
+			 val);
 }
 
-static inline void zf_gdma_user_get(struct zf_rbp_info *rbp_info, uint32_t *user)
+static inline void zf_gdma_user_get(struct zf_rbp_info rbp_info, uint32_t *user)
 {
-    uint32_t pf_id = rbp_info->pfid;
-
-    //host addr
-    if (rbp_info->host)
-    {
-        if ((pf_id & ZF_GDMA_VF_MASK) != 0)
-        {
-            pf_id &= ~ZF_GDMA_VF_MASK;
-            *user = (ZF_GDMA_VF_EN | (rbp_info->vfid << ZF_GDMA_VF_NUM_SHIFT));
-        }
-        *user |= ((rbp_info->epid << ZF_GDMA_EP_ID_SHIFT) | (pf_id << ZF_GDMA_PF_NUM_SHIFT));
-    }
-    else
-    {
-        *user = ZF_GDMA_ZF_USER;
-    }
+	// host addr
+	if (rbp_info.host) {
+		if ((rbp_info.pfid & ZF_GDMA_VF_MASK) != 0) {
+			rbp_info.pfid &= ~ZF_GDMA_VF_MASK;
+			*user = (ZF_GDMA_VF_EN | (rbp_info.vfid << ZF_GDMA_VF_NUM_SHIFT));
+		}
+		*user |= ((rbp_info.epid << ZF_GDMA_EP_ID_SHIFT) |
+				  (rbp_info.pfid << ZF_GDMA_PF_NUM_SHIFT));
+	} else {
+		*user = ZF_GDMA_ZF_USER;
+	}
 }
 
 static inline void zf_gdma_cfg_get(uint32_t *val, uint8_t tc_enable)
 {
-    *val = (ZF_GDMA_CHAN_ENABLE | ZF_GDMA_SOFT_CHAN |
-            ZF_GDMA_TC_INTR_ENABLE | ZF_GDMA_ERR_INTR_ENABLE |
-            (ZF_GDMA_DEFAULT_BURST_LEN << ZF_GDMA_SBL_SHIFT) |
-            (ZF_GDMA_BURST_SIZE_MAX << ZF_GDMA_SBS_SHIFT) |
-            (ZF_GDMA_BURST_SIZE_MAX << ZF_GDMA_DBS_SHIFT));
-
-    if (tc_enable != 0)
-    {
-        *val |= ZF_GDMA_TC_CNT_ENABLE;
-    }
+	*val = (ZF_GDMA_CHAN_ENABLE | ZF_GDMA_SOFT_CHAN | ZF_GDMA_TC_INTR_ENABLE |
+			ZF_GDMA_ERR_INTR_ENABLE |
+			(ZF_GDMA_DEFAULT_BURST_LEN << ZF_GDMA_SBL_SHIFT) |
+			(ZF_GDMA_BURST_SIZE_MAX << ZF_GDMA_SBS_SHIFT) |
+			(ZF_GDMA_BURST_SIZE_MAX << ZF_GDMA_DBS_SHIFT));
+
+	if (tc_enable != 0) {
+		*val |= ZF_GDMA_TC_CNT_ENABLE;
+	}
 }
 
 static void zf_gdma_desc_free(struct zxdh_virt_dma_desc *vd)
 {
-    if (vd != NULL)
-    {
-        kfree(to_zf_gdma_desc(vd));
-    }
+	if (vd != NULL) {
+		kfree(to_zf_gdma_desc(vd));
+	}
 }
 
 static int32_t zf_gdma_alloc_chan_resources(struct dma_chan *chan)
 {
-    return 0;
+	pr_debug("%s is called\n", __func__);
+
+	return 0;
 }
 
 static void zf_gdma_free_chan_resources(struct dma_chan *chan)
 {
-
+	pr_debug("%s is called\n", __func__);
 }
 
-static int32_t zf_gdma_device_config(struct dma_chan *chan, struct dma_slave_config *config)
+static int32_t zf_gdma_device_config(struct dma_chan *chan,
+									 struct dma_slave_config *config)
 {
-    return 0;
+	pr_debug("%s is called\n", __func__);
+
+	return 0;
 }
 
-static struct dma_async_tx_descriptor *zf_gdma_prep_dma_memcpy(struct dma_chan *chan,
-                                                               dma_addr_t dst,
-                                                               dma_addr_t src,
-                                                               size_t len,
-                                                               unsigned long flags)
+static struct dma_async_tx_descriptor *
+zf_gdma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
+						size_t len, unsigned long flags)
 {
-    struct zf_gdma_chan *gchan = NULL;
-    struct zf_gdma_desc *desc = NULL;
-    struct zf_dma_addr_rbp *srbp = NULL;
-    struct zf_dma_addr_rbp *drbp = NULL;
-    uint32_t src_user = 0;
-    uint32_t dst_user = 0;
-    unsigned long status = 0;
-
-    if ((chan == NULL) || ((void *)dst == NULL) || ((void *)src == NULL))
-    {
-        printk(KERN_ERR "%s:param is invalid\n", __func__);
-        return ERR_PTR(-EINVAL);
-    }
-
-    gchan = to_zf_gdma_chan(chan);
-    srbp = (struct zf_dma_addr_rbp *)src;
-    drbp = (struct zf_dma_addr_rbp *)dst;
-
-    desc = kzalloc(sizeof(struct zf_gdma_desc), GFP_KERNEL);
-    if (desc == NULL)
-    {
-        printk(KERN_ERR "%s: Failed to alloc gdma desc\n", __func__);
-        return ERR_PTR(-ENOMEM);
-    }
-
-    zf_gdma_user_get(&srbp->rbp_info, &src_user);
-    zf_gdma_user_get(&drbp->rbp_info, &dst_user);
-
-    desc->user = ((src_user & LOW16_MASK) | (dst_user << 16));
-    desc->src  = (uint64_t)(srbp->addr);
-    desc->dst  = (uint64_t)(drbp->addr);
-    desc->len  = (uint64_t)len;
-    desc->chan = gchan;
-    spin_lock_irqsave(&gchan->chan_lock, status);
-    list_add_tail(&desc->node, &gchan->desc_list);
-    spin_unlock_irqrestore(&gchan->chan_lock, status);
-
-    return zxdh_vchan_tx_prep(&gchan->vc, &desc->vd, flags);
+	struct zf_gdma_chan *gchan = NULL;
+	struct zf_gdma_desc *desc = NULL;
+	struct zf_dma_addr_rbp *srbp = NULL;
+	struct zf_dma_addr_rbp *drbp = NULL;
+	uint32_t src_user = 0;
+	uint32_t dst_user = 0;
+	unsigned long status = 0;
+
+	if ((chan == NULL) || ((void *)dst == NULL) || ((void *)src == NULL)) {
+		printk(KERN_ERR "%s:param is invalid\n", __func__);
+		return ERR_PTR(-EINVAL);
+	}
+
+	gchan = to_zf_gdma_chan(chan);
+	srbp = (struct zf_dma_addr_rbp *)src;
+	drbp = (struct zf_dma_addr_rbp *)dst;
+
+	desc = kzalloc(sizeof(struct zf_gdma_desc), GFP_KERNEL);
+	if (desc == NULL) {
+		printk(KERN_ERR "%s: Failed to alloc gdma desc\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	zf_gdma_user_get(srbp->rbp_info, &src_user);
+	pr_debug("%s:setup src_user:0x%x epid:%d, pfid:%d, vfid:%d success\n",
+			 __func__, src_user, srbp->rbp_info.epid, srbp->rbp_info.pfid,
+			 srbp->rbp_info.vfid);
+
+	zf_gdma_user_get(drbp->rbp_info, &dst_user);
+	pr_debug("%s:setup dst_user:0x%x epid:%d, pfid:%d, vfid:%d success\n",
+			 __func__, dst_user, drbp->rbp_info.epid, drbp->rbp_info.pfid,
+			 drbp->rbp_info.vfid);
+
+	desc->user = ((src_user & LOW16_MASK) | (dst_user << 16));
+	desc->src = (uint64_t)(srbp->addr);
+	desc->dst = (uint64_t)(drbp->addr);
+	desc->len = (uint64_t)len;
+	desc->chan = gchan;
+	spin_lock_irqsave(&gchan->chan_lock, status);
+	list_add_tail(&desc->node, &gchan->desc_list);
+	spin_unlock_irqrestore(&gchan->chan_lock, status);
+
+	return zxdh_vchan_tx_prep(&gchan->vc, &desc->vd, flags);
 }
 
 static void zf_gdma_issue_pending(struct dma_chan *chan)
 {
-    struct zf_gdma_chan *gchan = NULL;
-    unsigned long flags = 0;
-    bool pending = false;
+	struct zf_gdma_chan *gchan = NULL;
+	unsigned long flags = 0;
 
-    if (chan == NULL)
-        return;
+	if (chan == NULL)
+		return;
 
-    gchan = to_zf_gdma_chan(chan);
+	gchan = to_zf_gdma_chan(chan);
 
-    spin_lock_irqsave(&gchan->vc.lock, flags);
-    if (zxdh_vchan_issue_pending(&gchan->vc))
-    {
-        pending = true;
-    }
-    spin_unlock_irqrestore(&gchan->vc.lock, flags);
+	spin_lock_irqsave(&gchan->vc.lock, flags);
+	zxdh_vchan_issue_pending(&gchan->vc);
+	spin_unlock_irqrestore(&gchan->vc.lock, flags);
 
-    if (pending)
-    {
-        zf_gdma_enqueue_buff(gchan);
-    }
-
-    return;
+	return;
 }
 
-static enum dma_status zf_gdma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *state)
+static enum dma_status zf_gdma_tx_status(struct dma_chan *chan,
+										 dma_cookie_t cookie,
+										 struct dma_tx_state *state)
 {
-     return 0;
+	pr_debug("%s is called\n", __func__);
+
+	return 0;
 }
 
 static int32_t zf_gdma_terminate_all(struct dma_chan *chan)
 {
-    return 0;
+	pr_debug("%s is called\n", __func__);
+
+	return 0;
 }
 
 void zf_gdma_dev_init(struct device *dev, struct dma_device *dd)
 {
-    dd->device_alloc_chan_resources = zf_gdma_alloc_chan_resources;
-    dd->device_free_chan_resources = zf_gdma_free_chan_resources;
-    dd->device_config = zf_gdma_device_config;
-    dd->device_prep_dma_memcpy = zf_gdma_prep_dma_memcpy;
-    dd->device_issue_pending = zf_gdma_issue_pending;
-    dd->device_tx_status = zf_gdma_tx_status;
-    dd->device_terminate_all = zf_gdma_terminate_all;
-
-    dd->chancnt = ZF_GDMA_CHAN_NUM;
-    dd->privatecnt = 0;
-    dd->copy_align = ZF_GDMA_ALIGN_SIZE;
-    dd->src_addr_widths = ZF_GDMA_DMA_BUSWIDTHS;
-    dd->dst_addr_widths = ZF_GDMA_DMA_BUSWIDTHS;
-    dd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
-    dd->dev = dev;
-
-    dma_cap_zero(dd->cap_mask);
-    dma_cap_set(DMA_RBP, dd->cap_mask);
+	dd->device_alloc_chan_resources = zf_gdma_alloc_chan_resources;
+	dd->device_free_chan_resources = zf_gdma_free_chan_resources;
+	dd->device_config = zf_gdma_device_config;
+	dd->device_prep_dma_memcpy = zf_gdma_prep_dma_memcpy;
+	dd->device_issue_pending = zf_gdma_issue_pending;
+	dd->device_tx_status = zf_gdma_tx_status;
+	dd->device_terminate_all = zf_gdma_terminate_all;
+
+	dd->chancnt = ZF_GDMA_CHAN_NUM;
+	dd->privatecnt = 0;
+	dd->copy_align = ZF_GDMA_ALIGN_SIZE;
+	dd->src_addr_widths = ZF_GDMA_DMA_BUSWIDTHS;
+	dd->dst_addr_widths = ZF_GDMA_DMA_BUSWIDTHS;
+	dd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
+	dd->dev = dev;
+
+	dma_cap_zero(dd->cap_mask);
+	dma_cap_set(DMA_RBP, dd->cap_mask);
 }
 
 static int32_t zf_gdma_virt_chan_init(struct zf_gdma_dev *gdev)
 {
-    struct zf_gdma_chan *gchan = NULL;
-    uint32_t val = 0;
-    uint16_t i = 0;
-
-    INIT_LIST_HEAD(&gdev->dd->channels);
-    for (i = 0; i < ZF_GDMA_CHAN_NUM; i++)
-    {
-        gchan = &gdev->chan[i];
-        gchan->status = GDMA_CHAN_IDLE;
-        gchan->chan_id = ZF_GDMA_CHAN_BASE + i;
-        gchan->gdev = gdev;
-        gchan->vc.desc_free = zf_gdma_desc_free;
-        tasklet_init(&gchan->task, gchan_irq_tasklet_process, (unsigned long)gchan);
-
-        zxdh_vchan_init(&gchan->vc, gdev->dd);
-        spin_lock_init(&gchan->chan_lock);
-        INIT_LIST_HEAD(&gchan->desc_list);
-
-        /* reset gdma channel */
-        val = ZF_GDMA_CHAN_FORCE_CLOSE;
-        zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_CONTROL_OFFSET, val);
-
-        val = ZF_GDMA_ERR_RPT_ENABLE | ZF_GDMA_ERR_STATUS | ZF_GDMA_TC_CNT_CLEAN;
-        zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_TC_CNT_OFFSET, val);
-    }
-
-    /* Configure interrupt pulse width to 8 cycle */
-    zf_gdma_write_reg(gchan, 0, ZF_GDMA_PULSE_WIDTH_OFFSET, 7);
-
-    return 0;
+	struct zf_gdma_chan *gchan = NULL;
+	uint32_t val = 0;
+	uint16_t i = 0;
+
+	INIT_LIST_HEAD(&gdev->dd->channels);
+	for (i = 0; i < ZF_GDMA_CHAN_NUM; i++) {
+		gchan = &gdev->chan[i];
+		gchan->status = GDMA_CHAN_IDLE;
+		gchan->chan_id = ZF_GDMA_CHAN_BASE + i;
+		gchan->gdev = gdev;
+		gchan->vc.desc_free = zf_gdma_desc_free;
+
+		zxdh_vchan_init(&gchan->vc, gdev->dd);
+		spin_lock_init(&gchan->chan_lock);
+		INIT_LIST_HEAD(&gchan->desc_list);
+
+		/* reset gdma channel */
+		val = ZF_GDMA_CHAN_FORCE_CLOSE;
+		zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_CONTROL_OFFSET, val);
+
+		val = ZF_GDMA_ERR_RPT_ENABLE | ZF_GDMA_ERR_STATUS |
+			  ZF_GDMA_TC_CNT_CLEAN;
+		zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_TC_CNT_OFFSET, val);
+	}
+
+	return 0;
 }
 
 static int32_t zf_gdma_xmit_done(struct zf_gdma_chan *gchan)
 {
-    struct zxdh_virt_dma_desc *vdesc = NULL;
-    uint32_t widx = gchan->chan_id / 32;
-    uint32_t bidx = gchan->chan_id % 32;
-    uint32_t val = 0;
-    unsigned long flags = 0;
-
-    val = zf_gdma_read_reg(gchan, 0, ZF_GDMA_TC_STATUS_OFFSET + (widx * sizeof(uint32_t)));
-    if ((val & (1UL << bidx)) == 0)
-    {
-        printk(KERN_ERR "%s:chan%d tc status error\n", __func__, gchan->chan_id);
-        spin_lock(&gchan->chan_lock);
-        gchan->status = GDMA_CHAN_ERR;
-        spin_unlock(&gchan->chan_lock);
-        return -1;
-    }
-
-    pr_debug("chan%d transfer success\n", gchan->chan_id);
-    zf_gdma_write_reg(gchan, 0, ZF_GDMA_STATUS_CLEAN_OFFSET + (widx * sizeof(uint32_t)), 1 << bidx);
-
-    spin_lock(&gchan->chan_lock);
-    if (gchan->desc == NULL)
-    {
-        printk(KERN_ERR "%s:chan%d descriptor missing\n", __func__, gchan->chan_id);
-        gchan->status = GDMA_CHAN_ERR;
-        spin_unlock(&gchan->chan_lock);
-        return -1;
-    }
-
-    if (gchan->desc->len == 0)
-    {
-        list_del(&gchan->desc->node);
-        vdesc = &gchan->desc->vd;
-        gchan->desc = NULL;
-
-        spin_lock_irqsave(&gchan->vc.lock, flags);
-        list_del(&vdesc->node);
-        zxdh_vchan_cookie_complete(vdesc);
-        spin_unlock_irqrestore(&gchan->vc.lock, flags);
-    }
-    gchan->status = GDMA_CHAN_IDLE;
-    spin_unlock(&gchan->chan_lock);
-
-    return 0;
+	uint32_t widx = 0;
+	uint32_t bidx = 0;
+	uint32_t status = 0;
+	struct zxdh_virt_dma_desc *vdesc = NULL;
+	unsigned long flags = 0;
+
+	widx = gchan->chan_id / 32;
+	bidx = gchan->chan_id % 32;
+	status = zf_gdma_read_reg(
+			gchan, 0, ZF_GDMA_TC_STATUS_OFFSET + (widx * sizeof(uint32_t)));
+	pr_debug("%s:chan%d tc_status:%d\n", __func__, gchan->chan_id,
+			 (status & (1 << bidx)) ? 1 : 0);
+	if ((status & (1 << bidx)) == 0) {
+		return -EBUSY;
+	}
+
+	pr_debug("chan%d transfer success\n", gchan->chan_id);
+	zf_gdma_write_reg(gchan, 0,
+					  ZF_GDMA_STATUS_CLEAN_OFFSET + (widx * sizeof(uint32_t)),
+					  1 << bidx);
+
+	if (gchan->desc == NULL) {
+		printk(KERN_ERR "%s:chan%d descriptor missing\n", __func__,
+			   gchan->chan_id);
+		gchan->status = GDMA_CHAN_ERR;
+		return -1;
+	}
+
+	if (gchan->desc->len == 0) {
+		spin_lock_irqsave(&gchan->chan_lock, flags);
+		list_del(&gchan->desc->node);
+		spin_unlock_irqrestore(&gchan->chan_lock, flags);
+
+		vdesc = &gchan->desc->vd;
+		spin_lock_irqsave(&gchan->vc.lock, flags);
+		list_del(&vdesc->node);
+		zxdh_vchan_cookie_complete(vdesc);
+		spin_unlock_irqrestore(&gchan->vc.lock, flags);
+
+		gchan->desc = NULL;
+		gchan->status = GDMA_CHAN_IDLE;
+	}
+
+	return 0;
 }
 
-static void zf_gdma_enqueue_buff(struct zf_gdma_chan *gchan)
+static void zf_gdma_enqueue_buff(struct zf_gdma_chan *gchan,
+								 struct zxdh_virt_dma_desc *vdesc)
 {
-    struct zf_gdma_desc *desc = NULL;
-    struct zxdh_virt_dma_desc *vdesc = NULL;
-    uint32_t val = 0;
-    uint64_t cur_len = 0;
-    unsigned long flags = 0;
-
-    spin_lock_irqsave(&gchan->chan_lock, flags);
-    if (gchan->status != GDMA_CHAN_IDLE)
-    {
-        goto out;
-    }
-    spin_lock(&gchan->vc.lock);
-    vdesc = zxdh_vchan_next_desc(&gchan->vc);
-    spin_unlock(&gchan->vc.lock);
-    if (vdesc == NULL)
-    {
-        goto out;
-    }
-    gchan->status = GDMA_CHAN_BUSY;
-    spin_unlock_irqrestore(&gchan->chan_lock, flags);
-
-    desc = to_zf_gdma_desc(vdesc);
-    gchan->desc = desc;
-    cur_len = (desc->len > ZF_GDMA_BUFF_SIZE_MAX) ? ZF_GDMA_BUFF_SIZE_MAX : desc->len;
-
-    zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_SAR_LOW_OFFSET, desc->src & LOW32_MASK);
-    zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_SAR_HIGH_OFFSET, (desc->src >> 32) & LOW32_MASK);
-
-    zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_DAR_LOW_OFFSET, desc->dst & LOW32_MASK);
-    zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_DAR_HIGH_OFFSET, (desc->dst >> 32) & LOW32_MASK);
-
-    zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_XFERSIZE_OFFSET, cur_len);
-
-    zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_EXT_ADDR_OFFSET, desc->user);
-
-    zf_gdma_cfg_get(&val, 1);
-    zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_CONTROL_OFFSET, val);
-
-    desc->src += cur_len;
-    desc->dst += cur_len;
-    desc->len -= cur_len;
-
-    return;
-
-out:
-    spin_unlock_irqrestore(&gchan->chan_lock, flags);
-}
+	struct zf_gdma_desc *desc = to_zf_gdma_desc(vdesc);
+	uint32_t val = 0;
+	uint64_t cur_len = 0;
 
-static void zf_gdma_free_channels(struct zf_gdma_dev *gdev)
-{
-    struct zf_gdma_chan *gchan = NULL;
-    struct zf_gdma_desc *desc = NULL;
-    struct zf_gdma_desc *tmp = NULL;
-    uint16_t i = 0;
-    unsigned long flags = 0;
-
-    for (i = 0; i < ZF_GDMA_CHAN_NUM; i++)
-    {
-        gchan = &gdev->chan[i];
-        tasklet_kill(&gchan->task);
-
-        spin_lock_irqsave(&gchan->chan_lock, flags);
-        spin_lock(&gchan->vc.lock);
-        list_for_each_entry_safe(desc, tmp, &gchan->desc_list, node)
-        {
-            list_del(&desc->vd.node);
-            list_del(&desc->node);
-            kfree(desc);
-        }
-        spin_unlock(&gchan->vc.lock);
-        spin_unlock_irqrestore(&gchan->chan_lock, flags);
-    }
-}
+	gchan->status = GDMA_CHAN_BUSY;
+	gchan->desc = desc;
 
-int32_t dh_zf_mpf_gdma_init(struct dh_core_dev *dh_dev)
-{
-    struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
-    struct zf_gdma_dev *gdev = NULL;
-    struct device *dev = NULL;
-    int32_t node = 0;
-    int32_t ret = 0;
-
-    if (dh_dev->pdev == NULL)
-    {
-        printk(KERN_ERR "%s: pdev is invalid\n", __func__);
-        return -ENODEV;
-    }
-
-    if (mpf_dev->pci_ioremap_addr == 0)
-    {
-        printk(KERN_ERR "%s: pci_ioremap_addr is invalid\n", __func__);
-        return -ENAVAIL;
-    }
-
-    gdev = kzalloc(sizeof(struct zf_gdma_dev), GFP_KERNEL);
-    if (gdev == NULL)
-    {
-        printk(KERN_ERR "%s: Failed to alloc gdev\n", __FUNCTION__);
-        return -ENOMEM;
-    }
-    mpf_dev->gdev = gdev;
-
-    gdev->base_addr = mpf_dev->pci_ioremap_addr + ZF_GDMA_BASE_OFFSET;
-    gdev->pdev = dh_dev->pdev;
-    dev = &(dh_dev->pdev->dev);
-    node = dev_to_node(dev);
-    gdev->dd = kzalloc_node(sizeof(struct dma_device), GFP_KERNEL, node);
-    if (gdev->dd == NULL)
-    {
-        printk(KERN_ERR "%s: Failed to alloc dma_device\n", __FUNCTION__);
-        ret = -ENOMEM;
-        goto free_gdev;
-    }
-
-    zf_gdma_dev_init(dev, gdev->dd);
-    zf_gdma_virt_chan_init(gdev);
-
-    ret = dma_async_device_register(gdev->dd);
-    if (ret != 0)
-    {
-        printk(KERN_ERR "%s: Failed to register gdma device\n", __func__);
-        goto err_out;
-    }
-
-    return 0;
+	cur_len = (desc->len > ZF_GDMA_BUFF_SIZE_MAX) ? ZF_GDMA_BUFF_SIZE_MAX :
+													  desc->len;
 
-err_out:
-    zf_gdma_free_channels(gdev);
-    kfree(gdev->dd);
-free_gdev:
-    kfree(gdev);
-    return ret;
-}
+	zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_SAR_LOW_OFFSET,
+					  desc->src & LOW32_MASK);
+	zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_SAR_HIGH_OFFSET,
+					  (desc->src >> 32) & LOW32_MASK);
 
-void dh_zf_mpf_gdma_uninit(struct dh_core_dev *dh_dev)
-{
-    struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
-    struct zf_gdma_dev *gdev = NULL;
-
-    if (mpf_dev->gdev == NULL)
-    {
-        printk(KERN_ERR "%s:gdev is invalid\n", __func__);
-        return;
-    }
-    gdev = mpf_dev->gdev;
-
-    if (gdev->dd != NULL)
-    {
-        dma_async_device_unregister(gdev->dd);
-        kfree(gdev->dd);
-    }
-    zf_gdma_free_channels(gdev);
-    kfree(gdev);
-}
+	zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_DAR_LOW_OFFSET,
+					  desc->dst & LOW32_MASK);
+	zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_DAR_HIGH_OFFSET,
+					  (desc->dst >> 32) & LOW32_MASK);
 
-int32_t zf_gdma_err_irq_handle(struct notifier_block *nb, unsigned long action, void *data)
-{
-    pr_debug("%s is called\n", __func__);
+	zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_XFERSIZE_OFFSET, cur_len);
 
-    return 0;
+	zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_EXT_ADDR_OFFSET,
+					  desc->user);
+
+	zf_gdma_cfg_get(&val, 1);
+	zf_gdma_write_reg(gchan, gchan->chan_id, ZF_GDMA_CONTROL_OFFSET, val);
+
+	desc->src += cur_len;
+	desc->dst += cur_len;
+	desc->len -= cur_len;
 }
 
-int32_t zf_gdma_chan_irq_handle(struct notifier_block *nb, unsigned long action, void *data)
+int32_t zf_gdma_thread_handle(void *data)
 {
-    struct dh_eq_async *eq = container_of(nb, struct dh_eq_async, irq_nb);
-    struct zf_gdma_chan *gchan = NULL;
-
-    if (eq->priv == NULL)
-    {
-        printk(KERN_ERR "%s:eq->priv is NULL\n", __func__);
-        return -1;
-    }
-    gchan = (struct zf_gdma_chan *)eq->priv;
-    tasklet_hi_schedule(&gchan->task);
-
-    return 0;
+	struct zf_gdma_dev *gdev = data;
+	struct zf_gdma_chan *gchan = NULL;
+	struct dma_chan *chan = NULL;
+	struct zxdh_virt_dma_desc *vdesc = NULL;
+	unsigned long flags = 0;
+	uint64_t time;
+
+	printk(KERN_DEBUG "%s is called\n", __func__);
+	time = jiffies;
+
+	while (1) {
+		if (kthread_should_stop()) {
+			printk(KERN_DEBUG "%s:gdma thread is stopping\n", __func__);
+			break;
+		}
+
+		if ((jiffies - time) > (1 * HZ)) {
+			cond_resched();
+			time = jiffies;
+		}
+
+		list_for_each_entry(chan, &gdev->dd->channels, device_node) {
+			gchan = to_zf_gdma_chan(chan);
+			if ((gchan->status == GDMA_CHAN_BUSY) &&
+				(zf_gdma_xmit_done(gchan) != 0)) {
+				continue;
+			}
+
+			spin_lock_irqsave(&gchan->vc.lock, flags);
+			vdesc = zxdh_vchan_next_desc(&gchan->vc);
+			spin_unlock_irqrestore(&gchan->vc.lock, flags);
+			if (vdesc != NULL) {
+				zf_gdma_enqueue_buff(gchan, vdesc);
+			}
+		}
+	}
+
+	return 0;
 }
 
-void gchan_irq_tasklet_process(unsigned long data)
+static void zf_gdma_free_channels(struct zf_gdma_dev *gdev)
 {
-    struct zf_gdma_chan *gchan = NULL;
+	struct zf_gdma_chan *gchan = NULL;
+	struct zf_gdma_desc *desc = NULL;
+	uint16_t i = 0;
+	unsigned long flags = 0;
+
+	for (i = 0; i < ZF_GDMA_CHAN_NUM; i++) {
+		gchan = &gdev->chan[i];
+		spin_lock_irqsave(&gchan->chan_lock, flags);
+		spin_lock(&gchan->vc.lock);
+		list_for_each_entry(desc, &gchan->desc_list, node) {
+			list_del(&desc->vd.node);
+			list_del(&desc->node);
+			kfree(desc);
+		}
+		spin_unlock(&gchan->vc.lock);
+		spin_unlock_irqrestore(&gchan->chan_lock, flags);
+	}
+}
 
-    if (unlikely(data == 0))
-    {
-        printk(KERN_ERR "%s:param is invalid\n", __func__);
-        return;
-    }
+int32_t dh_zf_mpf_gdma_init(struct dh_core_dev *dh_dev)
+{
+	struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
+	struct zf_gdma_dev *gdev = NULL;
+	struct device *dev = NULL;
+	int32_t node = 0;
+	int32_t ret = 0;
+
+	if (dh_dev->pdev == NULL) {
+		printk(KERN_ERR "%s: pdev is invalid\n", __func__);
+		return -ENODEV;
+	}
+
+	if (mpf_dev->pci_ioremap_addr == 0) {
+		printk(KERN_ERR "%s: pci_ioremap_addr is invalid\n", __func__);
+		return -ENAVAIL;
+	}
+
+	gdev = kzalloc(sizeof(struct zf_gdma_dev), GFP_KERNEL);
+	if (gdev == NULL) {
+		printk(KERN_ERR "%s: Failed to alloc gdev\n", __FUNCTION__);
+		return -ENOMEM;
+	}
+	mpf_dev->gdev = gdev;
+
+	gdev->base_addr = mpf_dev->pci_ioremap_addr + ZF_GDMA_BASE_OFFSET;
+	gdev->pdev = dh_dev->pdev;
+	dev = &(dh_dev->pdev->dev);
+	node = dev_to_node(dev);
+	gdev->dd = kzalloc_node(sizeof(struct dma_device), GFP_KERNEL, node);
+	if (gdev->dd == NULL) {
+		printk(KERN_ERR "%s: Failed to alloc dma_device\n", __FUNCTION__);
+		ret = -ENOMEM;
+		goto free_gdev;
+	}
+
+	zf_gdma_dev_init(dev, gdev->dd);
+
+	ret = zf_gdma_virt_chan_init(gdev);
+	if (ret != 0) {
+		printk(KERN_ERR "%s: Failed to initialize gdma virtual channel\n",
+			   __FUNCTION__);
+		goto free_dma_dev;
+	}
+
+	gdev->gdma_thread = kthread_run(zf_gdma_thread_handle, gdev, "gdma_thread");
+	if (gdev->gdma_thread == NULL) {
+		printk(KERN_ERR "%s: Falied to create gdma thread\n", __FUNCTION__);
+		goto free_dma_dev;
+	}
+
+	ret = dma_async_device_register(gdev->dd);
+	if (ret != 0) {
+		printk(KERN_ERR "%s: Failed to register gdma device\n", __func__);
+		goto err_out;
+	}
+
+	return 0;
 
-    gchan = (struct zf_gdma_chan *)data;
-    if (zf_gdma_xmit_done(gchan) != 0)
-        return;
+err_out:
+	kthread_stop(gdev->gdma_thread);
+free_dma_dev:
+	kfree(gdev->dd);
+free_gdev:
+	kfree(gdev);
+	return ret;
+}
 
-    zf_gdma_enqueue_buff(gchan);
+void dh_zf_mpf_gdma_uninit(struct dh_core_dev *dh_dev)
+{
+	struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
+	struct zf_gdma_dev *gdev = NULL;
+
+	if (mpf_dev->gdev == NULL) {
+		printk(KERN_ERR "%s:gdev is invalid\n", __func__);
+		return;
+	}
+	gdev = mpf_dev->gdev;
+
+	if (gdev->gdma_thread != NULL) {
+		kthread_stop(gdev->gdma_thread);
+		gdev->gdma_thread = NULL;
+	}
+
+	if (gdev->dd != NULL) {
+		dma_async_device_unregister(gdev->dd);
+		kfree(gdev->dd);
+	}
+	zf_gdma_free_channels(gdev);
+	kfree(gdev);
 }
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/gdma.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/gdma.h
index 303be03fa9a9b2cf3bde40edb22a429e685491ce..ef11c5eef24a724af7fed6eb1e1caaa3c74391b6 100644
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/gdma.h
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/gdma.h
@@ -13,55 +13,44 @@
 #include <linux/mutex.h>
 #include <linux/of_dma.h>
 #include <linux/spinlock.h>
-
 #include "./epc/virt-dma.h"
 
-#define ZF_GDMA_CHAN_NUM                        (4)
-#define ZF_GDMA_CHAN_BASE                       (58)
+#define ZF_GDMA_CHAN_NUM (4)
+#define ZF_GDMA_CHAN_BASE (58)
 
-enum zf_gdma_chan_status
-{
-    GDMA_CHAN_IDLE = 0,
-    GDMA_CHAN_BUSY,
-    GDMA_CHAN_ERR
-};
+enum zf_gdma_chan_status { GDMA_CHAN_IDLE = 0, GDMA_CHAN_BUSY, GDMA_CHAN_ERR };
 
-struct zf_gdma_chan
-{
-    enum zf_gdma_chan_status status;
-    uint16_t chan_id;
+struct zf_gdma_chan {
+	enum zf_gdma_chan_status status;
+	uint16_t chan_id;
 
-    struct list_head desc_list;
-    spinlock_t chan_lock;
+	struct list_head desc_list;
+	spinlock_t chan_lock;
 
-    struct zf_gdma_dev *gdev;
-    struct zxdh_virt_dma_chan vc;
-    struct zf_gdma_desc *desc;
-    struct tasklet_struct task;
+	struct zf_gdma_dev *gdev;
+	struct zxdh_virt_dma_chan vc;
+	struct zf_gdma_desc *desc;
 };
 
-struct zf_gdma_desc
-{
-    uint64_t src;                   /* src addr */
-    uint64_t dst;
-    uint64_t len;
-    uint32_t user;
-    struct zxdh_virt_dma_desc vd;
-    struct list_head node;
-    struct zf_gdma_chan *chan;
+struct zf_gdma_desc {
+	uint64_t src; /* src addr */
+	uint64_t dst;
+	uint64_t len;
+	uint32_t user;
+	struct zxdh_virt_dma_desc vd;
+	struct list_head node;
+	struct zf_gdma_chan *chan;
 };
 
-struct zf_gdma_dev
-{
-    uint64_t base_addr;
-    struct dma_device *dd;
-    struct pci_dev *pdev;
-    struct zf_gdma_chan chan[ZF_GDMA_CHAN_NUM];
+struct zf_gdma_dev {
+	uint64_t base_addr;
+	struct dma_device *dd;
+	struct pci_dev *pdev;
+	struct task_struct *gdma_thread;
+	struct zf_gdma_chan chan[ZF_GDMA_CHAN_NUM];
 };
 
 int32_t dh_zf_mpf_gdma_init(struct dh_core_dev *dh_dev);
 void dh_zf_mpf_gdma_uninit(struct dh_core_dev *dh_dev);
-int32_t zf_gdma_err_irq_handle(struct notifier_block *nb, unsigned long action, void *data);
-int32_t zf_gdma_chan_irq_handle(struct notifier_block *nb, unsigned long action, void *data);
 
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/irq.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/irq.c
old mode 100755
new mode 100644
index 9e957a7808a6b5092fdea90e6179cf6b2410a8f5..45797d01298509f20d70d007b32de8cb7daac1bf
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/irq.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/irq.c
@@ -1,169 +1,160 @@
-#include <linux/pci.h>
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/helper.h>
-#include "irq.h"
-
-static struct dh_irq_range zxdh_get_mpf_range(struct dh_core_dev *dev)
-{
-    struct dh_irq_range tmp = {
-        .start = 0,
-        .size = ZXDH_MPF_ASYNC_IRQ_NUM
-    };
-
-    return tmp;
-}
-static struct dh_irq_range zxdh_get_comp_mpf_range(struct dh_core_dev *dev)
-{
-    struct dh_irq_range tmp = {
-        .start = ZXDH_MPF_ASYNC_IRQ_NUM,
-        .size = ZXDH_MPF_COMP_IRQ_NUM
-    };
-
-    return tmp;
-}
-
-static struct dh_irq_range zxdh_get_gdma_irq_range(struct dh_core_dev *dev)
-{
-    struct dh_irq_range tmp = {
-        .start = ZXDH_MPF_GDMA_MSIX_VEC_BASE,
-        .size = ZXDH_MPF_GDMA_IRQ_NUM
-    };
-
-    return tmp;
-}
-
-static int32_t irq_pools_init(struct dh_core_dev *dev)
-{
-    struct dh_irq_table *table              = &dev->irq_table;
-    int32_t err                             = 0;
-    struct dh_irq_range irq_range;
-    struct dh_mpf_irq_table * mpf_irq_table = table->priv;
-
-    /* init mpf_pool */
-    irq_range = zxdh_get_mpf_range(dev);
-    mpf_irq_table->mpf_async_pool = irq_pool_alloc(dev, irq_range.start, irq_range.size, "zxdh_mpf_msg",
-                                                   ZXDH_MPF_ASYNC_IRQ_MIN_COMP,
-                                                   ZXDH_MPF_ASYNC_IRQ_MAX_COMP);
-    if (IS_ERR_OR_NULL(mpf_irq_table->mpf_async_pool))
-    {
-        return PTR_ERR(mpf_irq_table->mpf_async_pool);
-    }
-
-    /* init sf_comp_pool */
-    irq_range = zxdh_get_comp_mpf_range(dev);
-    mpf_irq_table->mpf_comp_pool = irq_pool_alloc(dev, irq_range.start,
-                                                  irq_range.size, "zxdh_mpf_comp",
-                                                  ZXDH_MPF_COMP_IRQ_MIN_COMP,
-                                                  ZXDH_MPF_COMP_IRQ_MAX_COMP);
-    if (IS_ERR_OR_NULL(mpf_irq_table->mpf_comp_pool))
-    {
-        err = PTR_ERR(mpf_irq_table->mpf_comp_pool);
-        goto err_mpf_comp;
-    }
-
-    mpf_irq_table->mpf_comp_pool->irqs_per_cpu = kcalloc(nr_cpu_ids, sizeof(u16), GFP_KERNEL);
-    if (unlikely(mpf_irq_table->mpf_comp_pool->irqs_per_cpu == NULL))
-    {
-        err = -ENOMEM;
-        goto err_irqs_per_cpu;
-    }
-
-    /* init gdma_irq_pool */
-    irq_range = zxdh_get_gdma_irq_range(dev);
-    mpf_irq_table->mpf_gdma_pool = irq_pool_alloc(dev, irq_range.start, irq_range.size, "zxdh_mpf_gdma",
-                                                  ZXDH_MPF_GDMA_IRQ_MIN,
-                                                  ZXDH_MPF_GDMA_IRQ_MAX);
-    if (IS_ERR_OR_NULL(mpf_irq_table->mpf_gdma_pool))
-    {
-        err = PTR_ERR(mpf_irq_table->mpf_gdma_pool);
-        goto err_irqs_per_cpu;
-    }
-
-    return 0;
-
-err_irqs_per_cpu:
-    irq_pool_free(mpf_irq_table->mpf_comp_pool);
-err_mpf_comp:
-    irq_pool_free(mpf_irq_table->mpf_async_pool);
-    return err;
-}
-
-static void irq_pools_destroy(struct dh_irq_table *table)
-{
-    struct dh_mpf_irq_table *mpf_irq_table = (struct dh_mpf_irq_table *)table->priv;
-
-    irq_pool_free(mpf_irq_table->mpf_comp_pool);
-    irq_pool_free(mpf_irq_table->mpf_async_pool);
-    irq_pool_free(mpf_irq_table->mpf_gdma_pool);
-}
-
-/*todo*/
-static int32_t zxdh_get_total_vec(struct dh_core_dev *dev)
-{
-    return ZXDH_ZF_MPF_IRQ_NUM_TOTAL;
-}
-
-int32_t dh_mpf_irq_table_create(struct dh_core_dev *dev)
-{
-    int32_t total_vec = 0;
-    int32_t err       = 0;
-
-    total_vec = zxdh_get_total_vec(dev);
-
-    total_vec = pci_alloc_irq_vectors(dev->pdev, total_vec, total_vec, PCI_IRQ_MSIX);
-    if (total_vec < 0)
-    {
-        dh_err(dev, "pci_alloc_irq_vectors failed: %d\n", total_vec);
-        return total_vec;
-    }
-
-    err = irq_pools_init(dev);
-    if (err != 0)
-    {
-        pci_free_irq_vectors(dev->pdev);
-    }
-
-    return err;
-}
-
-void dh_mpf_irq_table_destroy(struct dh_core_dev *dev)
-{
-    struct dh_irq_table *table = &dev->irq_table;
-
-    /* There are cases where IRQs still will be in used when we reaching
-     * to here. Hence, making sure all the irqs are released.
-     */
-    irq_pools_destroy(table);
-    pci_free_irq_vectors(dev->pdev);
-}
-
-struct dh_irq *dh_mpf_async_irq_request(struct dh_core_dev *dev)
-{
-    struct dh_irq_table *table             = &dev->irq_table;
-    struct dh_mpf_irq_table *mpf_irq_table = (struct dh_mpf_irq_table *)table->priv;
-
-    struct dh_irq *irq = zxdh_get_irq_of_pool(dev, mpf_irq_table->mpf_async_pool);
-    if (IS_ERR_OR_NULL(irq))
-        dh_err(dev, "irq=0x%llx\r\n", (unsigned long long)irq);
-    dh_dbg(dev, "end\r\n");
-    return irq;
-}
-
-/* irq_table API */
-int32_t dh_mpf_irq_table_init(struct dh_core_dev *dev)
-{
-    struct dh_irq_table *irq_table;
-    struct dh_mpf_irq_table *mpf_irq_table = NULL;
-
-    irq_table = &dev->irq_table;
-
-    mpf_irq_table = kvzalloc(sizeof(*mpf_irq_table), GFP_KERNEL);
-    if (unlikely(mpf_irq_table == NULL))
-    {
-        return -ENOMEM;
-    }
-
-    irq_table->priv = mpf_irq_table;
-
-    return 0;
-}
+#include <linux/pci.h>
+#include <linux/dinghai/driver.h>
+#include <linux/dinghai/helper.h>
+#include "irq.h"
+
+#define ZXDH_MPF_ASYNC_IRQ_MIN_COMP 0
+#define ZXDH_MPF_ASYNC_IRQ_MAX_COMP 1
+
+#define ZXDH_MPF_COMP_IRQ_MIN_COMP 0
+#define ZXDH_MPF_COMP_IRQ_MAX_COMP 1
+
+#define ZXDH_MPF_ASYNC_IRQ_NUM 6
+
+struct dh_mpf_irq_table {
+	struct dh_irq_pool *mpf_comp_pool;
+	struct dh_irq_pool *mpf_async_pool;
+};
+
+struct dh_irq_range {
+	int32_t start;
+	int32_t size;
+};
+
+static struct dh_irq_range zxdh_get_mpf_range(struct dh_core_dev *dev)
+{
+	struct dh_irq_range tmp = { .start = 0, .size = ZXDH_MPF_ASYNC_IRQ_NUM };
+
+	return tmp;
+}
+static struct dh_irq_range zxdh_get_comp_mpf_range(struct dh_core_dev *dev)
+{
+	struct dh_irq_range tmp = { .start = ZXDH_MPF_ASYNC_IRQ_NUM + 1,
+								.size = ZXDH_MPF_ASYNC_IRQ_NUM + 1 };
+
+	return tmp;
+}
+
+static int32_t irq_pools_init(struct dh_core_dev *dev)
+{
+	struct dh_irq_table *table = &dev->irq_table;
+	int32_t err = 0;
+	struct dh_irq_range irq_range;
+	struct dh_mpf_irq_table *mpf_irq_table = table->priv;
+
+	/* init mpf_pool */
+	irq_range = zxdh_get_mpf_range(dev);
+
+	mpf_irq_table->mpf_async_pool = irq_pool_alloc(
+			dev, irq_range.start, irq_range.size, "zxdh_mpf_msg",
+			ZXDH_MPF_ASYNC_IRQ_MIN_COMP, ZXDH_MPF_ASYNC_IRQ_MAX_COMP);
+	if (IS_ERR_OR_NULL(mpf_irq_table->mpf_async_pool)) {
+		return PTR_ERR(mpf_irq_table->mpf_async_pool);
+	}
+
+	/* init sf_comp_pool */
+	irq_range = zxdh_get_comp_mpf_range(dev);
+
+	mpf_irq_table->mpf_comp_pool = irq_pool_alloc(
+			dev, irq_range.start, irq_range.size, "zxdh_mpf_comp",
+			ZXDH_MPF_COMP_IRQ_MIN_COMP, ZXDH_MPF_COMP_IRQ_MAX_COMP);
+	if (IS_ERR_OR_NULL(mpf_irq_table->mpf_comp_pool)) {
+		err = PTR_ERR(mpf_irq_table->mpf_comp_pool);
+		goto err_mpf_comp;
+	}
+
+	mpf_irq_table->mpf_comp_pool->irqs_per_cpu =
+			kcalloc(nr_cpu_ids, sizeof(u16), GFP_KERNEL);
+	if (unlikely(mpf_irq_table->mpf_comp_pool->irqs_per_cpu == NULL)) {
+		err = -ENOMEM;
+		goto err_irqs_per_cpu;
+	}
+
+	return 0;
+
+err_irqs_per_cpu:
+	irq_pool_free(mpf_irq_table->mpf_comp_pool);
+err_mpf_comp:
+	irq_pool_free(mpf_irq_table->mpf_async_pool);
+	return err;
+}
+
+static void irq_pools_destroy(struct dh_irq_table *table)
+{
+	struct dh_mpf_irq_table *mpf_irq_table =
+			(struct dh_mpf_irq_table *)table->priv;
+
+	irq_pool_free(mpf_irq_table->mpf_comp_pool);
+	irq_pool_free(mpf_irq_table->mpf_async_pool);
+}
+
+/*todo*/
+static int32_t zxdh_get_total_vec(struct dh_core_dev *dev)
+{
+	return ZXDH_MPF_ASYNC_IRQ_NUM;
+}
+
+int32_t dh_mpf_irq_table_create(struct dh_core_dev *dev)
+{
+	int32_t total_vec = 0;
+	int32_t err = 0;
+
+	total_vec = zxdh_get_total_vec(dev);
+
+	total_vec = pci_alloc_irq_vectors(dev->pdev, total_vec, total_vec,
+									  PCI_IRQ_MSIX);
+	if (total_vec < 0) {
+		dh_err(dev, "pci_alloc_irq_vectors failed: %d\n", total_vec);
+		return total_vec;
+	}
+
+	err = irq_pools_init(dev);
+	if (err != 0) {
+		pci_free_irq_vectors(dev->pdev);
+	}
+
+	return err;
+}
+
+void dh_mpf_irq_table_destroy(struct dh_core_dev *dev)
+{
+	struct dh_irq_table *table = &dev->irq_table;
+
+	/* There are cases where IRQs still will be in used when we reaching
+   * to here. Hence, making sure all the irqs are released.
+   */
+	irq_pools_destroy(table);
+	pci_free_irq_vectors(dev->pdev);
+}
+
+struct dh_irq *dh_mpf_async_irq_request(struct dh_core_dev *dev)
+{
+	struct dh_irq_table *table = &dev->irq_table;
+	struct dh_mpf_irq_table *mpf_irq_table =
+			(struct dh_mpf_irq_table *)table->priv;
+
+	struct dh_irq *irq =
+			zxdh_get_irq_of_pool(dev, mpf_irq_table->mpf_async_pool);
+	if (IS_ERR_OR_NULL(irq))
+		dh_err(dev, "irq=0x%llx\r\n", (unsigned long long)irq);
+	dh_dbg(dev, "end\r\n");
+	return irq;
+}
+
+/* irq_table API */
+int32_t dh_mpf_irq_table_init(struct dh_core_dev *dev)
+{
+	struct dh_irq_table *irq_table;
+	struct dh_mpf_irq_table *mpf_irq_table = NULL;
+
+	irq_table = &dev->irq_table;
+
+	mpf_irq_table = kvzalloc(sizeof(*mpf_irq_table), GFP_KERNEL);
+	if (unlikely(mpf_irq_table == NULL)) {
+		return -ENOMEM;
+	}
+
+	irq_table->priv = mpf_irq_table;
+
+	return 0;
+}
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/irq.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/irq.h
old mode 100755
new mode 100644
index 7cdb29ba1bfcdde15fc0ef0dc3c00d88fd2b4d07..c3a1f0d8823c450baec678d54ca2f85a668dcdc7
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/irq.h
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/irq.h
@@ -1,49 +1,20 @@
-#ifndef __ZXDH_MPF_IRQ_H__
-#define __ZXDH_MPF_IRQ_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/dinghai_irq.h>
-#include <linux/dinghai/driver.h>
-
-#include "gdma.h"
-
-#define ZXDH_MPF_ASYNC_IRQ_NUM 6
-#define ZXDH_MPF_ASYNC_IRQ_MIN_COMP 0
-#define ZXDH_MPF_ASYNC_IRQ_MAX_COMP 1
-
-#define ZXDH_MPF_COMP_IRQ_NUM 1
-#define ZXDH_MPF_COMP_IRQ_MIN_COMP 0
-#define ZXDH_MPF_COMP_IRQ_MAX_COMP 1
-
-#define ZXDH_MPF_GDMA_IRQ_NUM (ZF_GDMA_CHAN_NUM + 1)
-#define ZXDH_MPF_GDMA_MSIX_VEC_BASE 10
-#define ZXDH_MPF_GDMA_IRQ_MIN 0
-#define ZXDH_MPF_GDMA_IRQ_MAX 1
-
-/* async irq:<0-5> comp irq:<6> gdma irq:<10-14> */
-#define ZXDH_ZF_MPF_IRQ_NUM_TOTAL 16
-
-struct dh_mpf_irq_table {
-    struct dh_irq_pool *mpf_comp_pool;
-    struct dh_irq_pool *mpf_async_pool;
-    struct dh_irq_pool *mpf_gdma_pool;
-};
-
-struct dh_irq_range {
-    int32_t start;
-    int32_t size;
-};
-
-struct dh_irq *dh_mpf_async_irq_request(struct dh_core_dev *dev);
-void dh_mpf_irq_table_destroy(struct dh_core_dev *dev);
-int32_t dh_mpf_irq_table_create(struct dh_core_dev *dev);
-int32_t dh_mpf_irq_table_init(struct dh_core_dev *dev);
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef __ZXDH_MPF_IRQ_H__
+#define __ZXDH_MPF_IRQ_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/dinghai_irq.h>
+#include <linux/dinghai/driver.h>
+
+struct dh_irq *dh_mpf_async_irq_request(struct dh_core_dev *dev);
+void dh_mpf_irq_table_destroy(struct dh_core_dev *dev);
+int32_t dh_mpf_irq_table_create(struct dh_core_dev *dev);
+int32_t dh_mpf_irq_table_init(struct dh_core_dev *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_chan_ioctl.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_chan_ioctl.c
deleted file mode 100644
index a6dbf1b36cf592bc8ac54fa832f4bf0f40c63968..0000000000000000000000000000000000000000
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_chan_ioctl.c
+++ /dev/null
@@ -1,284 +0,0 @@
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/uaccess.h>
-#include <linux/cdev.h>
-#include <linux/dinghai/dh_cmd.h>
-#include "zf_chan_ioctl.h"
-
-static dev_t dev;
-static struct cdev c_dev;
-static struct class *cl;
-
-#define BAR_IOCTL_CMD_NORMAL _IOW('a', 1, msg_entity_t)
-#define BAR_IOCTL_CMD_SINGLE_DEV _IOW('a', 2, pci_res_st)
-#define BAR_IOCTL_CMD_ALL_DEV _IOW('a', 3, pci_res_st)
-
-struct zxdh_bar_ioctl_dev
-{
-    uint16_t pcie_id;
-    uint64_t bar0_base_virt_addr;
-    uint64_t is_valid;
-}ioctl_dev = {0};
-
-struct zxdh_bar_ioctl_dev *zxdh_get_bar_ioctl_dev(void)
-{
-    return &ioctl_dev;
-}
-
-int zxdh_init_bar_ioctl_dev(struct dh_core_dev *core_dev)
-{
-    struct zxdh_bar_ioctl_dev *dev = zxdh_get_bar_ioctl_dev();
-    struct dh_en_mpf_dev *mpf_dev = dh_core_priv(core_dev);
-
-    dev->pcie_id = mpf_dev->pcie_id;
-    dev->bar0_base_virt_addr = mpf_dev->pci_ioremap_addr;
-    dev->is_valid = 1;
-    return 0;
-}
-
-int (*ioctl_bar_chan_func)(unsigned int cmd, unsigned long arg);
-
-int bar_chan_common_sync_send(unsigned int cmd, unsigned long arg)
-{
-    int ret = 0;
-    struct normal_msg_entity *user_msg = NULL;
-    struct zxdh_ioctl_send_paras *send_paras = NULL;
-    struct zxdh_pci_bar_msg in = {0};
-    struct zxdh_msg_recviver_mem result = {0};
-    struct zxdh_bar_ioctl_dev *dev = zxdh_get_bar_ioctl_dev();
-
-    /* 按照既定的申请内存*/
-    user_msg = kmalloc(sizeof(struct normal_msg_entity), GFP_KERNEL);
-    if (NULL == user_msg)
-    {
-        LOG_ERR("malloc failed.\n");
-        return -1;
-    }
-    /* 初始化并且按照约定的大小从用户态拷贝数据，保证不拷贝到脏数据*/
-    memset(user_msg, 0, sizeof(struct normal_msg_entity));
-    if (copy_from_user(user_msg, (msg_entity_t __user *)arg, sizeof(struct normal_msg_entity)))
-    {
-        user_msg->hdr.recv_msg_hdr.ioctl_state = IOCTRL_ERR_MSG_GET;
-        goto out;
-    }
-
-    send_paras = &user_msg->hdr.send_msg_hdr;
-    if (send_paras->pload_len > BAR_CHAN_PLOAD_SIZE)
-    {
-        user_msg->hdr.recv_msg_hdr.bar_state = IOCTRL_ERR_MSG_GET;
-        goto out;
-    }
-
-    in.virt_addr = dev->bar0_base_virt_addr + ZXDH_BAR1_CHAN_OFFSET;
-    in.payload_addr = user_msg->pload;
-    in.payload_len = send_paras->pload_len;
-    in.src = MSG_CHAN_END_PF;
-    in.dst = MSG_CHAN_END_RISC;
-    in.event_id = send_paras->event_id;
-    in.src_pcieid = dev->pcie_id;
-
-    /* pload直接透传上去*/
-    result.buffer_len = sizeof(user_msg->pload);
-    result.recv_buffer = (void *)user_msg->pload;
-
-    ret = zxdh_bar_chan_sync_msg_send(&in, &result);
-    if (ret != 0)
-    {
-        LOG_ERR("pcie send msg failed, ret:%d.\n", ret);
-    }
-
-    user_msg->hdr.recv_msg_hdr.bar_state = ret;
-    user_msg->hdr.recv_msg_hdr.ioctl_state = 0;
-out:
-    ret = copy_to_user((int *)arg, user_msg, sizeof(*user_msg));
-    if (0 != ret)
-    {
-        /* msg may not reply to user, but we can locate by demsg*/
-        LOG_ERR("reply ioctl msg failed, ret: %d.\n", ret);
-    }
-    /* free the user_msg_data*/
-    if (NULL != user_msg)
-    {
-        kfree(user_msg);
-    }
-    return 0;
-}
-
-static int remove_recv_hdr(uint8_t *buffer, size_t len)
-{
-    if (len <= BAR_REV_HDR_LEN)
-    {
-        return -1;
-    }
-    memmove(buffer, buffer + BAR_REV_HDR_LEN, len - BAR_REV_HDR_LEN);
-
-    return 0;
-}
-
-static char temp_recv_buf[BAR_CHAN_PLOAD_SIZE + BAR_REV_HDR_LEN] = {0};
-int bar_chan_pci_res_get(unsigned int cmd, unsigned long arg, uint16_t mode)
-{
-    int ret = 0;
-    struct zxdh_mpf_query_bar_msg *entity = NULL;
-    struct zxdh_pci_query_hdr query_hdr = {0};
-    struct zxdh_pci_bar_msg in = {0};
-    struct zxdh_msg_recviver_mem result = {0};
-    struct zxdh_bar_ioctl_dev *dev = zxdh_get_bar_ioctl_dev();
-
-    entity = kmalloc(sizeof(*entity), GFP_KERNEL);
-    if (NULL == entity)
-    {
-        LOG_ERR("malloc failed.\n");
-        return -1;
-    }
-    memset(entity, 0,sizeof(*entity));
-    if (copy_from_user(entity, (pci_res_st __user *)arg, sizeof(*entity)))
-    {
-        entity->ioctl_state = IOCTRL_ERR_MSG_GET;
-        goto out;
-    }
-
-    query_hdr.mode = mode;
-    query_hdr.pcie_id = entity->pci_res_msg.pcie_id;
-
-    in.virt_addr = dev->bar0_base_virt_addr + ZXDH_BAR1_CHAN_OFFSET;
-    in.payload_addr = &query_hdr;
-    in.payload_len = sizeof(query_hdr);
-    in.src = MSG_CHAN_END_PF;
-    in.dst = MSG_CHAN_END_RISC;
-    in.event_id = MODULE_PCIE_RES_QUERY;
-    in.src_pcieid = dev->pcie_id;
-
-    result.recv_buffer = temp_recv_buf;
-    result.buffer_len = sizeof(temp_recv_buf);
-
-    ret = zxdh_bar_chan_sync_msg_send(&in, &result);
-    if (ret != 0)
-    {
-        LOG_ERR("pcie send msg failed, ret:%d.\n", ret);
-        goto out;
-    }
-
-    ret = remove_recv_hdr(result.recv_buffer, result.buffer_len);
-    memcpy(&entity->pci_res_msg.reply, result.recv_buffer, sizeof(struct zxdh_mpf_pci_res_list));
-
-    entity->ioctl_state = 0;
-out:
-    entity->bar_state = ret;
-    ret = copy_to_user((int *)arg, entity, sizeof(*entity));
-    if (0 != ret)
-    {
-        LOG_ERR("reply tp user failed.\n");
-    }
-    if (NULL != entity)
-    {
-        kfree(entity);
-    }
-    return 0;
-}
-
-int bar_chan_pci_res_get_single(unsigned int cmd, unsigned long arg)
-{
-    return bar_chan_pci_res_get(cmd, arg, PCI_QUERY_TYPE_SINGLE);
-}
-
-int bar_chan_pci_res_get_all(unsigned int cmd, unsigned long arg)
-{
-    return bar_chan_pci_res_get(cmd, arg, PCI_QUERY_TYPE_ALL);
-}
-
-struct bar_chan_func_sel
-{
-    unsigned int cmd;
-    int (*ioctl_bar_chan_func)(unsigned int cmd, unsigned long arg);
-}ioctl_func_arr[] = {
-    {BAR_IOCTL_CMD_NORMAL,  bar_chan_common_sync_send},
-    {BAR_IOCTL_CMD_SINGLE_DEV, bar_chan_pci_res_get_single},
-    {BAR_IOCTL_CMD_ALL_DEV, bar_chan_pci_res_get_all},
-};
-
-static long bar_msg_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
-{
-    int i, ret = 0;
-    int ioctl_func_nums = sizeof(ioctl_func_arr)/sizeof(ioctl_func_arr[0]);
-
-    for (i = 0; i < ioctl_func_nums; i++)
-    {
-        if (ioctl_func_arr[i].cmd == cmd)
-        {
-            ret = ioctl_func_arr[i].ioctl_bar_chan_func(cmd, arg);
-            break;
-        }
-    }
-    return 0;
-}
-
-static struct file_operations fops =
-{
-    .owner = THIS_MODULE,
-    .unlocked_ioctl = bar_msg_ioctl,
-};
-
-int bar_msg_ioctl_init(void)
-{
-    int ret = 0;
-
-    if (alloc_chrdev_region(&dev, 0, 1, DEVICE_NAME) < 0)
-    {
-        return -EBUSY;
-    }
-
-    if ((cl = class_create(THIS_MODULE, DEVICE_NAME)) == NULL)
-    {
-        unregister_chrdev_region(dev, 1);
-        return -ENOMEM;
-    }
-
-    if (device_create(cl, NULL, dev, NULL, DEVICE_NAME) == NULL)
-    {
-        class_destroy(cl);
-        unregister_chrdev_region(dev, 1);
-        return -ENOMEM;
-    }
-
-    cdev_init(&c_dev, &fops);
-    if (cdev_add(&c_dev, dev, 1) == -1)
-    {
-        device_destroy(cl, dev);
-        class_destroy(cl);
-        unregister_chrdev_region(dev, 1);
-        return -ENOMEM;
-    }
-
-    LOG_INFO("Custom device registered\n");
-    return ret;
-}
-
-void bar_msg_ioctl_exit(void)
-{
-    cdev_del(&c_dev);
-    device_destroy(cl, dev);
-    class_destroy(cl);
-    unregister_chrdev_region(dev, 1);
-    LOG_INFO("Custom device unregistered\n");
-}
-
-
-int zxdh_bar_ioctl_msg_mdl_init(struct dh_core_dev *core_dev)
-{
-    int ret = 0;
-
-    zxdh_init_bar_ioctl_dev(core_dev);
-    ret = bar_msg_ioctl_init();
-    if (ret != 0)
-    {
-        LOG_ERR("custom init failed, ret:%d.\n", ret);
-        return -1;
-    }
-    return 0;
-}
-
-void zxdh_bar_ioctl_msg_mdl_exit(struct dh_core_dev *core_dev)
-{
-    bar_msg_ioctl_exit();
-}
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_chan_ioctl.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_chan_ioctl.h
deleted file mode 100644
index 9c34b23ae190ebe7828777d2421e3800fd3bec5d..0000000000000000000000000000000000000000
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_chan_ioctl.h
+++ /dev/null
@@ -1,100 +0,0 @@
-#ifndef _ZXDH_MSG_CHAN_IOCTL_H_
-#define _ZXDH_MSG_CHAN_IOCTL_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "zf_mpf.h"
-
-#define DEVICE_NAME                    "bar_ioctl_dev"
-#define BAR_CHAN_SIZE                  (1024 * 2)
-#define BAR_CHAN_PLOAD_SIZE            (BAR_CHAN_SIZE - 12)
-#define BAR_REV_HDR_LEN                (4)
-#define ZXDH_PF_DEV_NUM                (40)
-
-#define PCI_QUERY_TYPE_SINGLE          (1)
-#define PCI_QUERY_TYPE_ALL             (2)
-
-struct zxdh_ioctl_send_paras
-{
-    uint16_t pload_len;
-    uint16_t src;
-    uint16_t dst;
-    uint16_t event_id;
-};
-
-struct zxdh_ioctl_recv_paras
-{
-    int ioctl_state;    //ioctrl级别返回值
-    int bar_state;      //bar通道接口级别返回值
-};
-
-enum {
-    IOCTRL_OK,
-    IOCTRL_ERR_MALLOC,
-    IOCTRL_ERR_MSG_GET,
-};
-
-typedef struct normal_msg_entity
-{
-    union ioctl_ctrl_hdr                          //私有消息控制头
-    {
-        struct zxdh_ioctl_send_paras send_msg_hdr;          //普通消息发送头
-        struct zxdh_ioctl_recv_paras recv_msg_hdr;          //普通消息发送头
-    }hdr;
-    uint8_t pload[BAR_CHAN_PLOAD_SIZE + BAR_REV_HDR_LEN];
-}msg_entity_t;
-
-struct zxdh_mpf_pci_res_item
-{
-    uint16_t device_id;
-    uint16_t pcie_id;
-    uint16_t bdf;
-    uint8_t  link_state;
-    uint8_t  dev_type;
-    uint16_t  total_vfs;
-    uint16_t  initial_vfs;
-    uint16_t  num_vfs;
-    uint8_t  vf_stride;
-    uint8_t  first_vf_offset;
-    uint8_t  pad[8];   //预留字段
-};
-
-/* zf内核态和risc通信的约定结构体*/
-struct zxdh_mpf_pci_res_list
-{
-    uint16_t num;
-    uint16_t verno;   //版本号
-    int res;       //0表示返回成功， 其他表示失败， 包括消息发送失败
-    struct zxdh_mpf_pci_res_item  pci_res_lis[ZXDH_PF_DEV_NUM];
-};
-
-struct zxdh_mpf_query_pci_res_msg
-{
-    uint16_t pcie_id;
-    uint8_t  dev_type;
-    uint8_t  pad[5];
-    struct zxdh_mpf_pci_res_list reply;
-};
-
-typedef struct zxdh_mpf_query_bar_msg
-{
-    int ioctl_state;
-    int bar_state;
-    struct zxdh_mpf_query_pci_res_msg pci_res_msg;
-}pci_res_st;
-
-struct zxdh_pci_query_hdr
-{
-    uint16_t mode;
-    uint16_t pcie_id;
-};
-
-int zxdh_bar_ioctl_msg_mdl_init(struct dh_core_dev *core_dev);
-void zxdh_bar_ioctl_msg_mdl_exit(struct dh_core_dev *core_dev);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ZXDH_MSG_CHAN_IOCTL_H_  */
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_events.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_events.c
old mode 100755
new mode 100644
index f39300137857cc789250fec727c44bf8a24bd608..5b347bf1a7233164bc700dcc9a62908b4bc35020
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_events.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_events.c
@@ -1,192 +1,212 @@
-#include <linux/gfp.h>
-#include <linux/slab.h>
-#include <linux/dinghai/driver.h>
-#include <linux/notifier.h>
-#include <linux/dinghai/events.h>
-#include <linux/dinghai/dh_cmd.h>
-#include <linux/workqueue.h>
-#include <linux/kernel.h>
-#include <linux/time.h>
-#include <linux/module.h>
-#include "zf_events.h"
-#include "../en_mpf.h"
-
-static int32_t zf_riscv_notifier(struct notifier_block *nb, unsigned long type, void *data);
-static int32_t zf_pf_notifier(struct notifier_block *nb, unsigned long type, void *data);
-static int32_t irq1_notifier(struct notifier_block *nb, unsigned long type, void *data);
-static int32_t fuc_hotplug_failed_notifier(struct notifier_block *nb, unsigned long type, void *data);
-static int32_t fuc_hotplug_finish_notifier(struct notifier_block *nb, unsigned long type, void *data);
-static int32_t irq4_notifier(struct notifier_block *nb, unsigned long type, void *data);
-int get_fuc_hp_ret(void);
-int finish_flag = 0;
-
-static struct dh_nb zf_mpf_events[] = {
-    {.nb.notifier_call = zf_riscv_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF},
-    {.nb.notifier_call = zf_pf_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_PF_TO_MPF},
-    {.nb.notifier_call = irq1_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_1},
-    {.nb.notifier_call = fuc_hotplug_failed_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_2},
-    {.nb.notifier_call = fuc_hotplug_finish_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_3},
-    {.nb.notifier_call = irq4_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_4}
-};
-
-static int32_t zf_riscv_notifier(struct notifier_block *nb, unsigned long type, void *data)
-{
-    struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
-    struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
-    struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
-
-    LOG_INFO("is called, type=%ld\n", type);
-    zxdh_events_work_enqueue(dh_dev, &mpf_dev->dh_np_sdk_from_risc);
-
-    return NOTIFY_OK;
-}
-
-static int32_t zf_pf_notifier(struct notifier_block *nb, unsigned long type, void *data)
-{
-    struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
-    struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
-    struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
-
-    LOG_INFO("is called, type=%ld\n", type);
-    zxdh_events_work_enqueue(dh_dev, &mpf_dev->dh_np_sdk_from_pf);
-
-    return NOTIFY_OK;
-}
-
-static int32_t irq1_notifier(struct notifier_block *nb, unsigned long type, void *data)
-{
-    struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
-    struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
-    struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
-
-    LOG_INFO("is called, ep_bdf=0x%x, pcie_id=%d\n", mpf_dev->ep_bdf, mpf_dev->pcie_id);
-
-    return zf_hdma_wr_handler((void *)dh_dev->zf_ep->dpu_ep_array[0]);
-}
-
-static int32_t fuc_hotplug_failed_notifier(struct notifier_block *nb, unsigned long type, void *data)
-{
-    finish_flag = FUC_HP_RET_FAILED;
-    LOG_ERR("hotplug failed\n");
-    return NOTIFY_OK;
-}
-static int32_t fuc_hotplug_finish_notifier(struct notifier_block *nb, unsigned long type, void *data)
-{
-    finish_flag = FUC_HP_RET_FINISH;
-    LOG_INFO("hotplug success\n");
-    return NOTIFY_OK;
-}
-
-static int32_t irq4_notifier(struct notifier_block *nb, unsigned long type, void *data)
-{
-    struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
-    struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
-    struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
-
-    LOG_INFO("is called, ep_bdf=0x%x, pcie_id=%d\n", mpf_dev->ep_bdf, mpf_dev->pcie_id);
-
-    return NOTIFY_OK;
-}
-
-static void zf_np_sdk_handler_from_risc(struct work_struct *p_work)
-{
-    struct dh_en_mpf_dev *mpf_dev = container_of(p_work, struct dh_en_mpf_dev, dh_np_sdk_from_risc);
-
-    LOG_INFO("is called\n");
-    zxdh_bar_irq_recv(MSG_CHAN_END_RISC, MSG_CHAN_END_MPF, mpf_dev->pci_ioremap_addr + ZXDH_BAR1_CHAN_OFFSET, NULL);
-    return;
-}
-
-static void zf_np_sdk_handler_from_pf(struct work_struct *p_work)
-{
-    struct dh_en_mpf_dev *mpf_dev = container_of(p_work, struct dh_en_mpf_dev, dh_np_sdk_from_pf);
-
-    LOG_INFO("is called\n");
-    zxdh_bar_irq_recv(MSG_CHAN_END_PF, MSG_CHAN_END_MPF, mpf_dev->pci_ioremap_addr + ZXDH_BAR2_CHAN_OFFSET, NULL);
-    return;
-}
-
-void zxdh_zf_events_start(struct dh_core_dev *dev)
-{
-    struct dh_events *events = dev->events;
-    int32_t i = 0;
-    int32_t err = 0;
-
-    for (i = 0; i < ARRAY_SIZE(zf_mpf_events); i++)
-    {
-        events->notifiers[i].nb = zf_mpf_events[i];
-        events->notifiers[i].ctx = dev;
-        err = dh_eq_notifier_register(&dev->eq_table, &events->notifiers[i].nb);
-        if (err != 0)
-        {
-            LOG_ERR("i: %d, err: %d.\n", i, err);
-        }
-    }
-}
-
-void dh_zf_events_stop(struct dh_core_dev *dev)
-{
-    struct dh_events *events = dev->events;
-    int32_t i = 0;
-
-    for (i = ARRAY_SIZE(zf_mpf_events) - 1; i >= 0 ; i--)
-    {
-        dh_eq_notifier_unregister(&dev->eq_table, &events->notifiers[i].nb);
-    }
-
-    zxdh_events_cleanup(dev);
-}
-
-int32_t dh_zf_mpf_events_init(struct dh_core_dev *dev)
-{
-    struct dh_events *events = NULL;
-    struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dev);
-    int32_t ret = 0;
-
-    events = kzalloc((sizeof(*events) + ARRAY_SIZE(zf_mpf_events) * sizeof(struct dh_event_nb)), GFP_KERNEL);
-    if (unlikely(events == NULL))
-    {
-        LOG_ERR("events kzalloc failed: %p\n", events);
-        ret = -ENOMEM;
-        goto err_events_kzalloc;
-    }
-
-    events->evt_num = ARRAY_SIZE(zf_mpf_events);
-    events->dev = dev;
-    dev->events = events;
-    events->wq = create_singlethread_workqueue("dh_zf_mpf_events");
-    if (!events->wq)
-    {
-        LOG_ERR("events->wq create_singlethread_workqueue failed: %p\n", events->wq);
-        ret = -ENOMEM;
-        goto err_create_wq;
-    }
-
-    INIT_WORK(&mpf_dev->dh_np_sdk_from_risc, zf_np_sdk_handler_from_risc);
-    INIT_WORK(&mpf_dev->dh_np_sdk_from_pf, zf_np_sdk_handler_from_pf);
-
-    zxdh_zf_events_start(dev);
-
-    return 0;
-
-err_create_wq:
-    kfree(events);
-err_events_kzalloc:
-    return ret;
-}
-
-void dh_zf_mpf_events_uninit(struct dh_core_dev *dev)
-{
-    return dh_zf_events_stop(dev);
-}
-
-void reset_fuc_hp_ret(void)
-{
-    finish_flag = 0;
-    return;
-}
-
-int get_fuc_hp_ret(void)
-{
-    return finish_flag;
+#include <linux/gfp.h>
+#include <linux/slab.h>
+#include <linux/dinghai/driver.h>
+#include <linux/notifier.h>
+#include <linux/dinghai/events.h>
+#include <linux/dinghai/dh_cmd.h>
+#include <linux/workqueue.h>
+#include <linux/kernel.h>
+#include <linux/time.h>
+#include <linux/module.h>
+#include "zf_events.h"
+#include "../en_mpf.h"
+
+static int32_t zf_riscv_notifier(struct notifier_block *nb, unsigned long type,
+								 void *data);
+static int32_t zf_pf_notifier(struct notifier_block *nb, unsigned long type,
+							  void *data);
+static int32_t irq1_notifier(struct notifier_block *nb, unsigned long type,
+							 void *data);
+static int32_t fuc_hotplug_failed_notifier(struct notifier_block *nb,
+										   unsigned long type, void *data);
+static int32_t fuc_hotplug_finish_notifier(struct notifier_block *nb,
+										   unsigned long type, void *data);
+static int32_t irq4_notifier(struct notifier_block *nb, unsigned long type,
+							 void *data);
+int get_fuc_hp_ret(void);
+int finish_flag;
+
+static struct dh_nb zf_mpf_events[] = {
+	{ .nb.notifier_call = zf_riscv_notifier,
+	  .event_type = DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF },
+	{ .nb.notifier_call = zf_pf_notifier,
+	  .event_type = DH_EVENT_TYPE_NOTIFY_PF_TO_MPF },
+	{ .nb.notifier_call = irq1_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_1 },
+	{ .nb.notifier_call = fuc_hotplug_failed_notifier,
+	  .event_type = DH_EVENT_TYPE_NOTIFY_2 },
+	{ .nb.notifier_call = fuc_hotplug_finish_notifier,
+	  .event_type = DH_EVENT_TYPE_NOTIFY_3 },
+	{ .nb.notifier_call = irq4_notifier, .event_type = DH_EVENT_TYPE_NOTIFY_4 }
+};
+
+static int32_t zf_riscv_notifier(struct notifier_block *nb, unsigned long type,
+								 void *data)
+{
+	struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
+	struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
+	struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
+
+	LOG_INFO("is called, type=%ld\n", type);
+	zxdh_events_work_enqueue(dh_dev, &mpf_dev->dh_np_sdk_from_risc);
+
+	return NOTIFY_OK;
+}
+
+static int32_t zf_pf_notifier(struct notifier_block *nb, unsigned long type,
+							  void *data)
+{
+	struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
+	struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
+	struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
+
+	LOG_INFO("is called, type=%ld\n", type);
+	zxdh_events_work_enqueue(dh_dev, &mpf_dev->dh_np_sdk_from_pf);
+
+	return NOTIFY_OK;
+}
+
+static int32_t irq1_notifier(struct notifier_block *nb, unsigned long type,
+							 void *data)
+{
+	struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
+	struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
+	struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
+
+	LOG_INFO("is called, ep_bdf=0x%x, pcie_id=%d\n", mpf_dev->ep_bdf,
+			 mpf_dev->pcie_id);
+
+	return zf_hdma_wr_handler((void *)dh_dev->zf_ep->dpu_ep_array[0]);
+}
+
+static int32_t fuc_hotplug_failed_notifier(struct notifier_block *nb,
+										   unsigned long type, void *data)
+{
+	finish_flag = FUC_HP_RET_FAILED;
+	LOG_ERR("hotplug failed\n");
+	return NOTIFY_OK;
+}
+static int32_t fuc_hotplug_finish_notifier(struct notifier_block *nb,
+										   unsigned long type, void *data)
+{
+	finish_flag = FUC_HP_RET_FINISH;
+	LOG_INFO("hotplug success\n");
+	return NOTIFY_OK;
+}
+
+static int32_t irq4_notifier(struct notifier_block *nb, unsigned long type,
+							 void *data)
+{
+	struct dh_event_nb *event_nb = dh_nb_cof(nb, struct dh_event_nb, nb);
+	struct dh_core_dev *dh_dev = (struct dh_core_dev *)event_nb->ctx;
+	struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
+
+	LOG_INFO("is called, ep_bdf=0x%x, pcie_id=%d\n", mpf_dev->ep_bdf,
+			 mpf_dev->pcie_id);
+
+	return NOTIFY_OK;
+}
+
+static void zf_np_sdk_handler_from_risc(struct work_struct *p_work)
+{
+	struct dh_en_mpf_dev *mpf_dev =
+			container_of(p_work, struct dh_en_mpf_dev, dh_np_sdk_from_risc);
+
+	LOG_INFO("is called\n");
+	zxdh_bar_irq_recv(MSG_CHAN_END_RISC, MSG_CHAN_END_MPF,
+					  mpf_dev->pci_ioremap_addr + ZXDH_BAR1_CHAN_OFFSET, NULL);
+	return;
+}
+
+static void zf_np_sdk_handler_from_pf(struct work_struct *p_work)
+{
+	struct dh_en_mpf_dev *mpf_dev =
+			container_of(p_work, struct dh_en_mpf_dev, dh_np_sdk_from_pf);
+
+	LOG_INFO("is called\n");
+	zxdh_bar_irq_recv(MSG_CHAN_END_PF, MSG_CHAN_END_MPF,
+					  mpf_dev->pci_ioremap_addr + ZXDH_BAR2_CHAN_OFFSET, NULL);
+	return;
+}
+
+void zxdh_zf_events_start(struct dh_core_dev *dev)
+{
+	struct dh_events *events = dev->events;
+	int32_t i = 0;
+	int32_t err = 0;
+
+	for (i = 0; i < ARRAY_SIZE(zf_mpf_events); i++) {
+		events->notifiers[i].nb = zf_mpf_events[i];
+		events->notifiers[i].ctx = dev;
+		err = dh_eq_notifier_register(&dev->eq_table, &events->notifiers[i].nb);
+		if (err != 0) {
+			LOG_ERR("i: %d, err: %d.\n", i, err);
+		}
+	}
+}
+
+void dh_zf_events_stop(struct dh_core_dev *dev)
+{
+	struct dh_events *events = dev->events;
+	int32_t i = 0;
+
+	for (i = ARRAY_SIZE(zf_mpf_events) - 1; i >= 0; i--) {
+		dh_eq_notifier_unregister(&dev->eq_table, &events->notifiers[i].nb);
+	}
+
+	zxdh_events_cleanup(dev);
+}
+
+int32_t dh_zf_mpf_events_init(struct dh_core_dev *dev)
+{
+	struct dh_events *events = NULL;
+	struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dev);
+	int32_t ret = 0;
+
+	events = kzalloc((sizeof(*events) +
+					  ARRAY_SIZE(zf_mpf_events) * sizeof(struct dh_event_nb)),
+					 GFP_KERNEL);
+	if (unlikely(events == NULL)) {
+		LOG_ERR("events kzalloc failed: %p\n", events);
+		ret = -ENOMEM;
+		goto err_events_kzalloc;
+	}
+
+	events->evt_num = ARRAY_SIZE(zf_mpf_events);
+	events->dev = dev;
+	dev->events = events;
+	events->wq = create_singlethread_workqueue("dh_zf_mpf_events");
+	if (!events->wq) {
+		LOG_ERR("events->wq create_singlethread_workqueue failed: %p\n",
+				events->wq);
+		ret = -ENOMEM;
+		goto err_create_wq;
+	}
+
+	INIT_WORK(&mpf_dev->dh_np_sdk_from_risc, zf_np_sdk_handler_from_risc);
+	INIT_WORK(&mpf_dev->dh_np_sdk_from_pf, zf_np_sdk_handler_from_pf);
+
+	zxdh_zf_events_start(dev);
+
+	return 0;
+
+err_create_wq:
+	kfree(events);
+err_events_kzalloc:
+	return ret;
+}
+
+void dh_zf_mpf_events_uninit(struct dh_core_dev *dev)
+{
+	return dh_zf_events_stop(dev);
+}
+
+void reset_fuc_hp_ret(void)
+{
+	finish_flag = 0;
+	return;
+}
+
+int get_fuc_hp_ret(void)
+{
+	return finish_flag;
 }
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_events.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_events.h
old mode 100755
new mode 100644
index 5ba057bccdaaf19bba6bc3accae301286ea92e53..a7c3f928d90fe68cb7a31ad1648e8d1c30a26fc6
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_events.h
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_events.h
@@ -1,24 +1,24 @@
-#ifndef __ZXDH_ZF_MPF_EVENTS_H__
-#define __ZXDH_ZF_MPF_EVENTS_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/driver.h>
-#include "epc/pcie-zte-zf-epc.h"
-#include "fuc_hotplug/fuc_hotplug_commom.h"
-
-int32_t dh_zf_mpf_events_init(struct dh_core_dev *dev);
-void zxdh_zf_events_start(struct dh_core_dev *dev);
-int32_t dh_zf_mpf_events_init(struct dh_core_dev *dev);
-void dh_zf_events_stop(struct dh_core_dev *dev);
-void dh_zf_mpf_events_uninit(struct dh_core_dev *dev);
-int zf_hdma_wr_handler(void *data);
-int zf_hdma_rd_handler(void *data);
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef __ZXDH_ZF_MPF_EVENTS_H__
+#define __ZXDH_ZF_MPF_EVENTS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/driver.h>
+#include "epc/pcie-zte-zf-epc.h"
+#include "fuc_hotplug/fuc_hotplug_commom.h"
+
+int32_t dh_zf_mpf_events_init(struct dh_core_dev *dev);
+void zxdh_zf_events_start(struct dh_core_dev *dev);
+int32_t dh_zf_mpf_events_init(struct dh_core_dev *dev);
+void dh_zf_events_stop(struct dh_core_dev *dev);
+void dh_zf_mpf_events_uninit(struct dh_core_dev *dev);
+int zf_hdma_wr_handler(void *data);
+int zf_hdma_rd_handler(void *data);
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_mpf.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_mpf.c
old mode 100755
new mode 100644
index 8cbe1e4d21c6a6272d1a64b3eab10b070f393bef..f051a6084321111fe0da3ec5fd6d1417dd679d5d
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_mpf.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_mpf.c
@@ -1,437 +1,409 @@
-#include <linux/module.h>
-#include <linux/kmod.h>
-#include <linux/pci.h>
-#include <linux/dinghai/helper.h>
-#include <linux/dinghai/devlink.h>
-#include <linux/dinghai/dinghai_irq.h>
-#include <linux/dinghai/eq.h>
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/kcompat.h>
-#include <linux/dinghai/queue.h>
-#include <en_pf.h>
-#include "zf_events.h"
-#include "eq.h"
-#include "irq.h"
-#include "cfg_sf.h"
-#include "zf_mpf.h"
-#include "gdma.h"
-
-#ifdef PCIE_ZF_EPC_OPEN
-#include "epc/pcie-zte-zf-epc.h"
-#endif
-
-#ifdef DRIVER_VERSION_VAL
-    #define DRV_VERSION DRIVER_VERSION_VAL
-#else
-    #define DRV_VERSION "1.0-1"
-#endif
-
-MODULE_LICENSE("Dual BSD/GPL");
-MODULE_VERSION(DRV_VERSION);
-
-uint32_t zf_dh_debug_mask;
-module_param_named(debug_mask, zf_dh_debug_mask, uint, 0644);
-MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
-
-extern struct devlink_ops dh_mpf_devlink_ops;
-extern struct dh_core_devlink_ops dh_mpf_core_devlink_ops;
-
-extern int zxdh_host_reset_driver_init(struct dh_core_dev *core_dev);
-extern void zxdh_host_reset_driver_exit(struct dh_core_dev *core_dev);
-extern int zxdh_host_fuc_hotplug_driver_init(void);
-extern void zxdh_host_fuc_hotplug_driver_exit(void);
-extern int zf_reset_finish_flag_init(struct dh_core_dev *dh_dev, unsigned long ep_mpf_paddr);
-extern void zf_reset_finish_flag_exit(void);
-extern int zxdh_bar_ioctl_msg_mdl_init(struct dh_core_dev *core_dev);
-extern void zxdh_bar_ioctl_msg_mdl_exit(struct dh_core_dev *core_dev);
-
-static int32_t dh_zf_mpf_pci_init(struct dh_core_dev *dev)
-{
-    int32_t ret = 0;
-    struct dh_en_mpf_dev *mpf_dev = NULL;
-
-    pci_set_drvdata(dev->pdev, dev);
-
-    ret = pci_enable_device(dev->pdev);
-    if (ret)
-    {
-        dev_err(dev->device, "pci_enable_device failed: %d\n", ret);
-        return -ENOMEM;
-    }
-
-    ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(64));
-    if (ret != 0)
-    {
-        ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(32));
-        if (ret != 0)
-        {
-            dev_err(dev->device, "dma_set_mask_and_coherent failed: %d\n", ret);
-            goto err_pci;
-        }
-    }
-
-    ret = pci_request_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM), "dh-mpf");
-    if (ret != 0)
-    {
-        dev_err(dev->device, "pci_request_selected_regions failed: %d\n", ret);
-        goto err_pci;
-    }
-
-    pci_enable_pcie_error_reporting(dev->pdev);
-    pci_set_master(dev->pdev);
-    ret = pci_save_state(dev->pdev);
-    if (ret != 0)
-    {
-        dev_err(dev->device, "pci_save_state failed: %d\n", ret);
-        goto err_pci_save_state;
-    }
-
-    mpf_dev = dh_core_priv(dev);
-    mpf_dev->pci_ioremap_addr = (uint64_t)ioremap(pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0));
-    LOG_INFO("pci_ioremap_addr=0x%llx, ioremap(0x%llx, 0x%llx)\n", mpf_dev->pci_ioremap_addr, pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0));
-    if (mpf_dev->pci_ioremap_addr == 0)
-    {
-        ret = -1;
-        LOG_ERR("ioremap(0x%llx, 0x%llx) failed\n", pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0));
-        goto err_pci_save_state;
-    }
-
-    return 0;
-
-err_pci_save_state:
-    pci_disable_pcie_error_reporting(dev->pdev);
-    pci_release_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM));
-err_pci:
-    pci_disable_device(dev->pdev);
-    return ret;
-}
-
-static const struct pci_device_id dh_zf_mpf_pci_table[] = {
-   { PCI_DEVICE(ZXDH_MPF_VENDOR_ID, ZXDH_MPF_DEVICE_ID), 0 },
-   { 0, }
-};
-
-MODULE_DEVICE_TABLE(pci, dh_zf_mpf_pci_table);
-
-void dh_zf_mpf_pci_close(struct dh_core_dev *dev)
-{
-    struct dh_en_mpf_dev *mpf_dev = NULL;
-
-    mpf_dev = dh_core_priv(dev);
-    iounmap((void __iomem *)mpf_dev->pci_ioremap_addr);
-    pci_disable_pcie_error_reporting(dev->pdev);
-    pci_release_selected_regions(dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM));
-    pci_disable_device(dev->pdev);
-
-    return;
-}
-
-int32_t dh_zf_mpf_pcie_id_get(struct dh_core_dev *dh_dev)
-{
-    u8 pos = 0;
-    uint8_t type = 0;
-    uint16_t padding = 0;
-    struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
-    struct pci_dev *pdev = dh_dev->pdev;
-
-    for (pos = pci_find_capability(pdev, PCI_CAP_ID_VNDR); pos > 0; pos = pci_find_next_capability(pdev, pos, PCI_CAP_ID_VNDR))
-    {
-        pci_read_config_byte(pdev, pos + offsetof(struct zxdh_pf_pci_cap, cfg_type), &type);
-
-        if (type == ZXDH_PCI_CAP_PCI_CFG)
-        {
-            pci_read_config_word(pdev, pos + offsetof(struct zxdh_pf_pci_cap, padding[0]), &padding);
-            mpf_dev->pcie_id = padding;
-            LOG_INFO("pf_dev->pcie_id: 0x%x\n", mpf_dev->pcie_id);
-            return 0;
-        }
-    }
-    return -1;
-}
-
-static int32_t dh_zf_mpf_probe(struct pci_dev *pdev, const struct pci_device_id *id)
-{
-    struct dh_core_dev *dh_dev = NULL;
-    struct devlink *devlink    = NULL;
-    int32_t err                = 0;
-
-    LOG_INFO("mpf driver start to probe\n");
-
-    devlink = zxdh_devlink_alloc(&pdev->dev, &dh_mpf_devlink_ops, sizeof(struct dh_en_mpf_dev));
-    if (devlink == NULL)
-    {
-        dev_err(&pdev->dev, "devlink alloc failed\n");
-        return -ENOMEM;
-    }
-
-    dh_dev = devlink_priv(devlink);
-    dh_dev->device = &pdev->dev;
-    dh_dev->pdev = pdev;
-    dh_dev->devlink_ops = &dh_mpf_core_devlink_ops;
-
-    err = dh_zf_mpf_pci_init(dh_dev);
-    if (err != 0)
-    {
-        dev_err(&pdev->dev, "%s failed: %d\n", __func__, err);
-        goto err_devlink_cleanup;
-    }
-
-#ifdef CONFIG_ZF_GDMA
-    err = dh_zf_mpf_gdma_init(dh_dev);
-    if (err != 0)
-    {
-        dh_err(dh_dev, "Failed to initialize gdma module\n");
-        goto err_gdma_init;
-    }
-#endif
-
-    err = dh_zf_mpf_pcie_id_get(dh_dev);
-    if (err != 0)
-    {
-        dev_err(&pdev->dev, "dh_pf_pcie_id_get failed: %d\n", err);
-        goto err_pci;
-    }
-
-    err = dh_mpf_irq_table_init(dh_dev); // dh_dev->irq_table.priv = kvzalloc(sizeof(struct dh_mpf_irq_table), GFP_KERNEL);
-    if (err != 0)
-    {
-        dh_err(dh_dev, "Failed to alloc IRQs\n");
-        goto err_pci;
-    }
-
-    err = dh_mpf_eq_table_init(dh_dev);
-    if (err != 0)
-    {
-        dh_err(dh_dev, "Failed to alloc IRQs\n");
-        goto err_eq_table_init;
-    }
-
-    err = dh_mpf_irq_table_create(dh_dev);
-    if (err != 0)
-    {
-        dh_err(dh_dev, "Failed to alloc IRQs\n");
-        goto err_irq_table_create;
-    }
-
-    err = dh_mpf_eq_table_create(dh_dev);
-    if (err != 0)
-    {
-        dh_err(dh_dev, "Failed to alloc EQs\n");
-        goto err_eq_table_create;
-    }
-
-#ifdef PCIE_ZF_EPC_OPEN
-    err = pcie_zte_zf_epc_init(dh_dev, id);
-    if (err != 0)
-    {
-        dh_err(dh_dev, "failed to initialize epc\n");
-        goto err_epc_init;
-    }
-#endif
-
-#ifdef PCIE_ZF_RST_FINISH_FLAG_OPEN
-    err = zf_reset_finish_flag_init(dh_dev, dh_dev->zf_ep->mpf_paddr);
-    if (err != 0)
-    {
-        dh_err(dh_dev, "failed to initialize zf_reset_finish_flag_init\n");
-        goto err_zf_reset_finish_flag_init_cleanup;
-    }
-#endif
-
-    err = dh_zf_mpf_events_init(dh_dev);
-    if (err != 0)
-    {
-        dh_err(dh_dev, "failed to initialize events\n");
-        goto err_events_init_cleanup;
-    }
-
-    err = zxdh_host_reset_driver_init(dh_dev);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_host_reset_driver_init failed: %d\n", err);
-        goto err_zf_host_reset;
-    }
-
-    err = zxdh_bar_ioctl_msg_mdl_init(dh_dev);
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_bar_ioctl_msg_mdl_init failed: %d\n", err);
-        goto err_zf_host_reset;
-    }
-
-#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
-    zxdh_devlink_register(devlink);
-#else
-    zxdh_devlink_register(devlink, &pdev->dev);
-#endif
-
-    LOG_INFO("mpf driver probe completed\n");
-    return 0;
-
-err_zf_host_reset:
-    zxdh_host_reset_driver_exit(dh_dev);
-err_events_init_cleanup:
-#ifdef PCIE_ZF_RST_FINISH_FLAG_OPEN
-    zf_reset_finish_flag_exit();
-err_zf_reset_finish_flag_init_cleanup:
-#endif
-#ifdef PCIE_ZF_EPC_OPEN
-    pcie_zte_zf_epc_free(dh_dev);
-err_epc_init:
-#endif
-    dh_mpf_eq_table_destroy(dh_dev);
-err_eq_table_create:
-    dh_mpf_irq_table_destroy(dh_dev);
-err_irq_table_create:
-    dh_eq_table_cleanup(dh_dev);
-err_eq_table_init:
-    dh_irq_table_cleanup(dh_dev);
-err_pci:
-#ifdef CONFIG_ZF_GDMA
-    dh_zf_mpf_gdma_uninit(dh_dev);
-err_gdma_init:
-#endif
-    dh_zf_mpf_pci_close(dh_dev);
-err_devlink_cleanup:
-    zxdh_devlink_free(devlink);
-    return err;
-}
-
-static void dh_zf_mpf_remove(struct pci_dev *pdev)
-{
-    struct dh_core_dev *dh_dev = pci_get_drvdata(pdev);
-    struct devlink *devlink = priv_to_devlink(dh_dev);
-
-    LOG_INFO("mpf driver start to remove");
-
-#ifdef PCIE_ZF_RST_FINISH_FLAG_OPEN
-    zf_reset_finish_flag_exit();
-#endif
-    zxdh_devlink_unregister(devlink);
-#ifdef PCIE_ZF_EPC_OPEN
-    pcie_zte_zf_epc_free(dh_dev);
-#endif
-    zxdh_bar_ioctl_msg_mdl_exit(dh_dev);
-    zxdh_host_reset_driver_exit(dh_dev);
-    dh_zf_mpf_events_uninit(dh_dev);
-    dh_mpf_eq_table_destroy(dh_dev);
-    dh_mpf_irq_table_destroy(dh_dev);
-    dh_eq_table_cleanup(dh_dev);
-    dh_irq_table_cleanup(dh_dev);
-#ifdef CONFIG_ZF_GDMA
-    dh_zf_mpf_gdma_uninit(dh_dev);
-#endif
-    dh_zf_mpf_pci_close(dh_dev);
-    zxdh_devlink_free(devlink);
-
-    pci_set_drvdata(pdev, NULL);
-
-    LOG_INFO("mpf driver remove completed\n");
-}
-
-static int32_t dh_zf_mpf_suspend(struct pci_dev *pdev, pm_message_t state)
-{
-
-    return 0;
-}
-
-static int32_t dh_zf_mpf_resume(struct pci_dev *pdev)
-{
-
-    return 0;
-}
-
-static void dh_zf_mpf_shutdown(struct pci_dev *pdev)
-{
-    dh_zf_mpf_remove(pdev);
-}
-
-static pci_ers_result_t dh_pci_err_detected(struct pci_dev *pdev,
-                                            pci_channel_state_t state)
-{
-    return PCI_ERS_RESULT_NONE;
-}
-
-static pci_ers_result_t dh_zf_mpf_pci_slot_reset(struct pci_dev *pdev)
-{
-    return PCI_ERS_RESULT_NONE;
-}
-
-static void dh_zf_mpf_pci_resume(struct pci_dev *pdev)
-{
-
-}
-
-static const struct pci_error_handlers dh_zf_mpf_err_handler = {
-    .error_detected = dh_pci_err_detected,
-    .slot_reset     = dh_zf_mpf_pci_slot_reset,
-    .resume         = dh_zf_mpf_pci_resume
-};
-
-static struct pci_driver zf_dh_mpf_driver = {
-    .name           = KBUILD_MODNAME,
-    .id_table       = dh_zf_mpf_pci_table,
-    .probe          = dh_zf_mpf_probe,
-    .remove         = dh_zf_mpf_remove,
-    .suspend        = dh_zf_mpf_suspend,
-    .resume         = dh_zf_mpf_resume,
-    .shutdown       = dh_zf_mpf_shutdown,
-    .err_handler    = &dh_zf_mpf_err_handler,
-};
-
-static int32_t __init init(void)
-{
-    int32_t err = 0;
-
-    err = pci_register_driver(&zf_dh_mpf_driver);
-    if (err != 0)
-    {
-        LOG_ERR("pci_register_driver failed: %d\n", err);
-        return err;
-    }
-
-#ifdef CONFIG_ZXDH_SF
-    err = zxdh_mpf_sf_driver_register();
-    if (err != 0)
-    {
-        LOG_ERR("zxdh_en_sf_driver_register failed: %d\n", err);
-        goto err_sf;
-    }
-#endif
-
-    err = zxdh_host_fuc_hotplug_driver_init();
-    if (err != 0){
-        LOG_ERR("fuc_hotplug_driver_init failed: %d\n", err);
-        goto err_fuc_hotplug;
-    }
-    LOG_INFO("zxdh_mpf driver init success\n");
-
-    return 0;
-
-err_fuc_hotplug:
-
-#ifdef CONFIG_ZXDH_SF
-err_sf:
-    pci_unregister_driver(&zf_dh_mpf_driver);
-#endif
-
-    return err;
-}
-
-static void __exit cleanup(void)
-{
-#ifdef CONFIG_ZXDH_SF
-    zxdh_mpf_sf_driver_uregister();
-#endif
-    zxdh_host_fuc_hotplug_driver_exit();
-    pci_unregister_driver(&zf_dh_mpf_driver);
-
-#ifdef PCIE_ZF_RST_FINISH_FLAG_OPEN
-    zf_reset_finish_flag_exit();
-#endif
-
-    LOG_INFO("zxdh_mpf driver remove success\n");
-}
-
-module_init(init);
-module_exit(cleanup);
+#include <linux/module.h>
+#include <linux/kmod.h>
+#include <linux/pci.h>
+#include <linux/dinghai/helper.h>
+#include <linux/dinghai/devlink.h>
+#include <linux/dinghai/dinghai_irq.h>
+#include <linux/dinghai/eq.h>
+#include <linux/dinghai/driver.h>
+#include <linux/dinghai/kcompat.h>
+#include <linux/dinghai/queue.h>
+#include <en_pf.h>
+#include "zf_events.h"
+#include "eq.h"
+#include "irq.h"
+#include "cfg_sf.h"
+#include "zf_mpf.h"
+#include "gdma.h"
+
+#ifdef PCIE_ZF_EPC_OPEN
+#include "epc/pcie-zte-zf-epc.h"
+#endif
+
+MODULE_LICENSE("Dual BSD/GPL");
+
+uint32_t zf_dh_debug_mask;
+module_param_named(debug_mask, zf_dh_debug_mask, uint, 0644);
+MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec "
+							 "time, 3 = both. Default=0");
+
+extern struct devlink_ops dh_mpf_devlink_ops;
+extern struct dh_core_devlink_ops dh_mpf_core_devlink_ops;
+
+extern int zxdh_host_reset_driver_init(struct dh_core_dev *core_dev);
+extern void zxdh_host_reset_driver_exit(struct dh_core_dev *core_dev);
+extern int zxdh_host_fuc_hotplug_driver_init(void);
+extern void zxdh_host_fuc_hotplug_driver_exit(void);
+extern int zf_reset_finish_flag_init(unsigned long ep_mpf_paddr);
+extern void zf_reset_finish_flag_exit(void);
+
+static int32_t dh_zf_mpf_pci_init(struct dh_core_dev *dev)
+{
+	int32_t ret = 0;
+	struct dh_en_mpf_dev *mpf_dev = NULL;
+
+	pci_set_drvdata(dev->pdev, dev);
+
+	ret = pci_enable_device(dev->pdev);
+	if (ret != 0) {
+		dev_err(dev->device, "pci_enable_device failed: %d\n", ret);
+		return -ENOMEM;
+	}
+
+	ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(64));
+	if (ret != 0) {
+		ret = dma_set_mask_and_coherent(dev->device, DMA_BIT_MASK(32));
+		if (ret != 0) {
+			dev_err(dev->device, "dma_set_mask_and_coherent failed: %d\n", ret);
+			goto err_pci;
+		}
+	}
+
+	ret = pci_request_selected_regions(
+			dev->pdev, pci_select_bars(dev->pdev, IORESOURCE_MEM), "dh-mpf");
+	if (ret != 0) {
+		dev_err(dev->device, "pci_request_selected_regions failed: %d\n", ret);
+		goto err_pci;
+	}
+
+	pci_enable_pcie_error_reporting(dev->pdev);
+	pci_set_master(dev->pdev);
+	ret = pci_save_state(dev->pdev);
+	if (ret != 0) {
+		dev_err(dev->device, "pci_save_state failed: %d\n", ret);
+		goto err_pci_save_state;
+	}
+
+	mpf_dev = dh_core_priv(dev);
+	mpf_dev->pci_ioremap_addr = (uint64_t)ioremap(
+			pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0));
+	LOG_INFO("pci_ioremap_addr=0x%llx, ioremap(0x%llx, 0x%llx)\n",
+			 mpf_dev->pci_ioremap_addr, pci_resource_start(dev->pdev, 0),
+			 pci_resource_len(dev->pdev, 0));
+	if (mpf_dev->pci_ioremap_addr == 0) {
+		ret = -1;
+		LOG_ERR("ioremap(0x%llx, 0x%llx) failed\n",
+				pci_resource_start(dev->pdev, 0),
+				pci_resource_len(dev->pdev, 0));
+		goto err_pci_save_state;
+	}
+
+	return 0;
+
+err_pci_save_state:
+	pci_disable_pcie_error_reporting(dev->pdev);
+	pci_release_selected_regions(dev->pdev,
+								 pci_select_bars(dev->pdev, IORESOURCE_MEM));
+err_pci:
+	pci_disable_device(dev->pdev);
+	return ret;
+}
+
+static const struct pci_device_id dh_zf_mpf_pci_table[] = {
+	{ PCI_DEVICE(ZXDH_MPF_VENDOR_ID, ZXDH_MPF_DEVICE_ID), 0 },
+	{
+			0,
+	}
+};
+
+MODULE_DEVICE_TABLE(pci, dh_zf_mpf_pci_table);
+
+void dh_zf_mpf_pci_close(struct dh_core_dev *dev)
+{
+	struct dh_en_mpf_dev *mpf_dev = NULL;
+
+	mpf_dev = dh_core_priv(dev);
+	iounmap((void *)mpf_dev->pci_ioremap_addr);
+	pci_disable_pcie_error_reporting(dev->pdev);
+	pci_release_selected_regions(dev->pdev,
+								 pci_select_bars(dev->pdev, IORESOURCE_MEM));
+	pci_disable_device(dev->pdev);
+
+	return;
+}
+
+int32_t dh_zf_mpf_pcie_id_get(struct dh_core_dev *dh_dev)
+{
+	int32_t pos = 0;
+	uint8_t type = 0;
+	uint16_t padding = 0;
+	struct dh_en_mpf_dev *mpf_dev = dh_core_priv(dh_dev);
+	struct pci_dev *pdev = dh_dev->pdev;
+
+	for (pos = pci_find_capability(pdev, PCI_CAP_ID_VNDR); pos > 0;
+		 pos = pci_find_next_capability(pdev, pos, PCI_CAP_ID_VNDR)) {
+		pci_read_config_byte(
+				pdev, pos + offsetof(struct zxdh_pf_pci_cap, cfg_type), &type);
+
+		if (type == ZXDH_PCI_CAP_PCI_CFG) {
+			pci_read_config_word(
+					pdev, pos + offsetof(struct zxdh_pf_pci_cap, padding[0]),
+					&padding);
+			mpf_dev->pcie_id = padding;
+			LOG_INFO("pf_dev->pcie_id: 0x%x\n", mpf_dev->pcie_id);
+			return 0;
+		}
+	}
+	return -1;
+}
+
+static int32_t dh_zf_mpf_probe(struct pci_dev *pdev,
+							   const struct pci_device_id *id)
+{
+	struct dh_core_dev *dh_dev = NULL;
+	struct devlink *devlink = NULL;
+	int32_t err = 0;
+
+	LOG_INFO("mpf driver start to probe\n");
+
+	devlink = zxdh_devlink_alloc(&pdev->dev, &dh_mpf_devlink_ops,
+								 sizeof(struct dh_en_mpf_dev));
+	if (devlink == NULL) {
+		dev_err(&pdev->dev, "devlink alloc failed\n");
+		return -ENOMEM;
+	}
+
+	dh_dev = devlink_priv(devlink);
+	dh_dev->device = &pdev->dev;
+	dh_dev->pdev = pdev;
+	dh_dev->devlink_ops = &dh_mpf_core_devlink_ops;
+
+	err = dh_zf_mpf_pci_init(dh_dev);
+	if (err != 0) {
+		dev_err(&pdev->dev, "%s failed: %d\n", __func__, err);
+		goto err_devlink_cleanup;
+	}
+
+	err = dh_zf_mpf_pcie_id_get(dh_dev);
+	if (err != 0) {
+		dev_err(&pdev->dev, "dh_pf_pcie_id_get failed: %d\n", err);
+		goto err_pci;
+	}
+
+	err = dh_mpf_irq_table_init(
+			dh_dev); // dh_dev->irq_table.priv = kvzalloc(sizeof(struct
+	// dh_mpf_irq_table), GFP_KERNEL);
+	if (err != 0) {
+		dh_err(dh_dev, "Failed to alloc IRQs\n");
+		goto err_pci;
+	}
+
+	err = dh_mpf_eq_table_init(dh_dev);
+	if (err != 0) {
+		dh_err(dh_dev, "Failed to alloc IRQs\n");
+		goto err_eq_table_init;
+	}
+
+	err = dh_mpf_irq_table_create(dh_dev);
+	if (err != 0) {
+		dh_err(dh_dev, "Failed to alloc IRQs\n");
+		goto err_irq_table_create;
+	}
+
+	err = dh_mpf_eq_table_create(dh_dev);
+	if (err != 0) {
+		dh_err(dh_dev, "Failed to alloc EQs\n");
+		goto err_eq_table_create;
+	}
+
+#ifdef PCIE_ZF_EPC_OPEN
+	err = pcie_zte_zf_epc_init(dh_dev, id);
+	if (err != 0) {
+		dh_err(dh_dev, "failed to initialize epc\n");
+		goto err_epc_init;
+	}
+#endif
+
+#ifdef PCIE_ZF_RST_FINISH_FLAG_OPEN
+	err = zf_reset_finish_flag_init(dh_dev->zf_ep->mpf_paddr);
+	if (err != 0) {
+		dh_err(dh_dev, "failed to initialize zf_reset_finish_flag_init\n");
+		goto err_zf_reset_finish_flag_init_cleanup;
+	}
+#endif
+
+#ifdef CONFIG_ZF_GDMA
+	err = dh_zf_mpf_gdma_init(dh_dev);
+	if (err != 0) {
+		dh_err(dh_dev, "Failed to initialize gdma module\n");
+		goto err_gdma_init;
+	}
+#endif
+
+	err = dh_zf_mpf_events_init(dh_dev);
+	if (err != 0) {
+		dh_err(dh_dev, "failed to initialize events\n");
+		goto err_events_init_cleanup;
+	}
+
+	err = zxdh_host_reset_driver_init(dh_dev);
+	if (err != 0) {
+		LOG_ERR("zxdh_host_reset_driver_init failed: %d\n", err);
+		goto err_zf_host_reset;
+	}
+
+#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
+	zxdh_devlink_register(devlink);
+#else
+	zxdh_devlink_register(devlink, &pdev->dev);
+#endif
+
+	LOG_INFO("mpf driver probe completed\n");
+	return 0;
+
+err_zf_host_reset:
+	zxdh_host_reset_driver_exit(dh_dev);
+err_events_init_cleanup:
+#ifdef CONFIG_ZF_GDMA
+	dh_zf_mpf_gdma_uninit(dh_dev);
+err_gdma_init:
+#endif
+#ifdef PCIE_ZF_RST_FINISH_FLAG_OPEN
+err_zf_reset_finish_flag_init_cleanup:
+#endif
+#ifdef PCIE_ZF_EPC_OPEN
+	pcie_zte_zf_epc_free(dh_dev);
+err_epc_init:
+#endif
+	dh_mpf_eq_table_destroy(dh_dev);
+err_eq_table_create:
+	dh_mpf_irq_table_destroy(dh_dev);
+err_irq_table_create:
+	dh_eq_table_cleanup(dh_dev);
+err_eq_table_init:
+	dh_irq_table_cleanup(dh_dev);
+err_pci:
+	dh_zf_mpf_pci_close(dh_dev);
+err_devlink_cleanup:
+	zxdh_devlink_free(devlink);
+	return err;
+}
+
+static void dh_zf_mpf_remove(struct pci_dev *pdev)
+{
+	struct dh_core_dev *dh_dev = pci_get_drvdata(pdev);
+	struct devlink *devlink = priv_to_devlink(dh_dev);
+	LOG_INFO("mpf driver start to remove");
+
+	zxdh_devlink_unregister(devlink);
+#ifdef PCIE_ZF_EPC_OPEN
+	pcie_zte_zf_epc_free(dh_dev);
+#endif
+	zxdh_host_reset_driver_exit(dh_dev);
+#ifdef CONFIG_ZF_GDMA
+	dh_zf_mpf_gdma_uninit(dh_dev);
+#endif
+	dh_zf_mpf_events_uninit(dh_dev);
+	dh_mpf_eq_table_destroy(dh_dev);
+	dh_mpf_irq_table_destroy(dh_dev);
+	dh_eq_table_cleanup(dh_dev);
+	dh_irq_table_cleanup(dh_dev);
+	dh_zf_mpf_pci_close(dh_dev);
+	zxdh_devlink_free(devlink);
+
+	pci_set_drvdata(pdev, NULL);
+
+	LOG_INFO("mpf driver remove completed\n");
+}
+
+static int32_t dh_zf_mpf_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+	return 0;
+}
+
+static int32_t dh_zf_mpf_resume(struct pci_dev *pdev)
+{
+	return 0;
+}
+
+static void dh_zf_mpf_shutdown(struct pci_dev *pdev)
+{
+	dh_zf_mpf_remove(pdev);
+}
+
+static pci_ers_result_t dh_pci_err_detected(struct pci_dev *pdev,
+											pci_channel_state_t state)
+{
+	return PCI_ERS_RESULT_NONE;
+}
+
+static pci_ers_result_t dh_zf_mpf_pci_slot_reset(struct pci_dev *pdev)
+{
+	return PCI_ERS_RESULT_NONE;
+}
+
+static void dh_zf_mpf_pci_resume(struct pci_dev *pdev)
+{
+}
+
+static const struct pci_error_handlers dh_zf_mpf_err_handler = {
+	.error_detected = dh_pci_err_detected,
+	.slot_reset = dh_zf_mpf_pci_slot_reset,
+	.resume = dh_zf_mpf_pci_resume
+};
+
+static struct pci_driver zf_dh_mpf_driver = {
+	.name = KBUILD_MODNAME,
+	.id_table = dh_zf_mpf_pci_table,
+	.probe = dh_zf_mpf_probe,
+	.remove = dh_zf_mpf_remove,
+	.suspend = dh_zf_mpf_suspend,
+	.resume = dh_zf_mpf_resume,
+	.shutdown = dh_zf_mpf_shutdown,
+	.err_handler = &dh_zf_mpf_err_handler,
+};
+
+static int32_t __init init(void)
+{
+	int32_t err = 0;
+
+	err = pci_register_driver(&zf_dh_mpf_driver);
+	if (err != 0) {
+		LOG_ERR("pci_register_driver failed: %d\n", err);
+		return err;
+	}
+
+#ifdef CONFIG_ZXDH_SF
+	err = zxdh_mpf_sf_driver_register();
+	if (err != 0) {
+		LOG_ERR("zxdh_en_sf_driver_register failed: %d\n", err);
+		goto err_sf;
+	}
+#endif
+
+	err = zxdh_host_fuc_hotplug_driver_init();
+	if (err != 0) {
+		LOG_ERR("fuc_hotplug_driver_init failed: %d\n", err);
+		goto err_fuc_hotplug;
+	}
+	LOG_INFO("zxdh_mpf driver init success\n");
+
+	return 0;
+
+err_fuc_hotplug:
+
+#ifdef CONFIG_ZXDH_SF
+err_sf:
+	pci_unregister_driver(&zf_dh_mpf_driver);
+#endif
+
+	return err;
+}
+
+static void __exit cleanup(void)
+{
+#ifdef CONFIG_ZXDH_SF
+	zxdh_mpf_sf_driver_uregister();
+#endif
+	zxdh_host_fuc_hotplug_driver_exit();
+	pci_unregister_driver(&zf_dh_mpf_driver);
+
+#ifdef PCIE_ZF_RST_FINISH_FLAG_OPEN
+	zf_reset_finish_flag_exit();
+#endif
+
+	LOG_INFO("zxdh_mpf driver remove success\n");
+}
+
+module_init(init);
+module_exit(cleanup);
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_mpf.h b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_mpf.h
old mode 100755
new mode 100644
index 34cd934792ddc3037a6a23b041b06017ca1278b2..a94cf80f825ae24f256ea3fd3272ea91f6eba309
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_mpf.h
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_mpf.h
@@ -1,36 +1,36 @@
-#ifndef __ZXDH_ZF_MPF_H__
-#define __ZXDH_ZF_MPF_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/workqueue.h>
-#include <linux/dinghai/driver.h>
-#include "gdma.h"
-
-#define ZXDH_MPF_VENDOR_ID 0x1cf2
-#define ZXDH_MPF_DEVICE_ID 0x8044
-
-#define ZXDH_BAR1_CHAN_OFFSET               0x2000//0x7801000
-#define ZXDH_BAR2_CHAN_OFFSET               0x3000//0x7802000
-#define PCIE_ZF_RST_FINISH_FLAG_OPEN        1
-
-struct dh_en_mpf_dev {
-    uint16_t ep_bdf;
-    uint16_t pcie_id;
-    uint16_t vport;
-
-    uint64_t pci_ioremap_addr;
-
-    struct work_struct dh_np_sdk_from_risc;
-    struct work_struct dh_np_sdk_from_pf;
-
-    struct zf_gdma_dev *gdev;
-};
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef __ZXDH_ZF_MPF_H__
+#define __ZXDH_ZF_MPF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/workqueue.h>
+#include <linux/dinghai/driver.h>
+#include "gdma.h"
+
+#define ZXDH_MPF_VENDOR_ID 0x1cf2
+#define ZXDH_MPF_DEVICE_ID 0x8044
+
+#define ZXDH_BAR1_CHAN_OFFSET 0x2000 // 0x7801000
+#define ZXDH_BAR2_CHAN_OFFSET 0x3000 // 0x7802000
+#define PCIE_ZF_RST_FINISH_FLAG_OPEN 1
+
+struct dh_en_mpf_dev {
+	uint16_t ep_bdf;
+	uint16_t pcie_id;
+	uint16_t vport;
+
+	uint64_t pci_ioremap_addr;
+
+	struct work_struct dh_np_sdk_from_risc;
+	struct work_struct dh_np_sdk_from_pf;
+
+	struct zf_gdma_dev *gdev;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* __ZXDH_EN_MPF_H__ */
\ No newline at end of file
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_reset_finish_flag.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_reset_finish_flag.c
old mode 100755
new mode 100644
index 0bd473abe2702ef8d8a0b7295796e02ad495101d..cc4eb04594cc8676697d93140f01df7c749b2240
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_reset_finish_flag.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zf_reset_finish_flag.c
@@ -3,93 +3,81 @@
 #include <linux/fs.h>
 #include <linux/kobject.h>
 #include <linux/sysfs.h>
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/helper.h>
 #include "epc/pcie-zte-zf-epc.h"
 
-#define FLAG_ID                        0x1
+#define FLAG_ID 0x1
 #define SYSFS_ZF_RESET_FINISH_FLAG_DIR "zf_reset_finish_flag"
-#define ZF_RESET_FINISH_FLAG_MODE      0664
-#define ZF_RESET_FINISH_FLAG           flag
-#define NOTIFY_OFFEST                  (PCIE_DPU_MPF_CSR_ADDR(PCIE_DPU_EP_CSR_SIZE * PCIE_DPU_EP_NUM) + 4)
-#define NOTIFY_VALUE                   (1 << 1)
-#define NOTIFY_MASK                    (1 << 1)
+#define ZF_RESET_FINISH_FLAG_MODE 0664
+#define ZF_RESET_FINISH_FLAG flag
+#define NOTIFY_OFFEST \
+	(PCIE_DPU_MPF_CSR_ADDR(PCIE_DPU_EP_CSR_SIZE * PCIE_DPU_EP_NUM) + 4)
+#define NOTIFY_VALUE (1 << 1)
+#define NOTIFY_MASK (1 << 1)
 
 static char flag_data[PAGE_SIZE];
-static struct kobject *zf_reset_finish_flag_kobj = NULL;
-unsigned long op_paddr = 0;
+static struct kobject *zf_reset_finish_flag_kobj;
+unsigned long op_paddr;
 
 static int notify_host_zf_reset_finished(void)
 {
-    int ret = 0;
+	int ret = 0;
 
-    ret = cfg_phy_rmw(op_paddr + NOTIFY_OFFEST, NOTIFY_VALUE, NOTIFY_MASK);
+	ret = cfg_phy_rmw(op_paddr + NOTIFY_OFFEST, NOTIFY_VALUE, NOTIFY_MASK);
 
-    if (ret) {
-      printk(KERN_ERR "notify_host_zf_reset_finished, cfg_phy_rmw write failed!\n");
-    }
+	if (ret) {
+		printk(KERN_ERR
+			   "notify_host_zf_reset_finished, cfg_phy_rmw write failed!\n");
+	}
 
-    return ret;
+	return 0;
 }
 
 static ssize_t read_flag(struct kobject *kobj, struct kobj_attribute *attr,
-                       char *buf)
+						 char *buf)
 {
-    return snprintf(buf, PAGE_SIZE, "%s", flag_data);
+	return snprintf(buf, PAGE_SIZE, "%s", flag_data);
 }
 
 static ssize_t write_flag(struct kobject *kobj, struct kobj_attribute *attr,
-                        const char *buf, size_t count)
+						  const char *buf, size_t count)
 {
-    int size = 0;
-    unsigned long flag = 0;
-    char *end = NULL;
-
-    size = snprintf(flag_data, PAGE_SIZE, "%s", buf);
-    flag = simple_strtoul(flag_data, &end, 16);
-    if (FLAG_ID == flag)
-    {
-        notify_host_zf_reset_finished();
-    }
-
-    return size;
+	int size = 0;
+	unsigned long flag = 0;
+	char *end = NULL;
+
+	size = snprintf(flag_data, PAGE_SIZE, "%s", buf);
+	flag = simple_strtoul(flag_data, &end, 16);
+	if (FLAG_ID == flag) {
+		notify_host_zf_reset_finished();
+	}
+
+	return size;
 }
 
-static struct kobj_attribute flag_attribute =
-    __ATTR(ZF_RESET_FINISH_FLAG, ZF_RESET_FINISH_FLAG_MODE, read_flag, write_flag);
+static struct kobj_attribute flag_attribute = __ATTR(
+		ZF_RESET_FINISH_FLAG, ZF_RESET_FINISH_FLAG_MODE, read_flag, write_flag);
 
-int zf_reset_finish_flag_init(struct dh_core_dev *dh_dev, unsigned long ep_mpf_paddr)
+int zf_reset_finish_flag_init(unsigned long ep_mpf_paddr)
 {
-    int ret = 0;
-
-    op_paddr = ep_mpf_paddr;
-    if (zf_reset_finish_flag_kobj == NULL)
-    {
-        zf_reset_finish_flag_kobj = kobject_create_and_add(SYSFS_ZF_RESET_FINISH_FLAG_DIR, kernel_kobj);
-        if (!zf_reset_finish_flag_kobj)
-            return -ENOMEM;
-
-        ret = sysfs_create_file(zf_reset_finish_flag_kobj, &flag_attribute.attr);
-        if (ret)
-        {
-            kobject_put(zf_reset_finish_flag_kobj);
-            zf_reset_finish_flag_kobj = NULL;
-        }
-    }
-    else
-    {
-        dh_err(dh_dev, "zf_reset_finish_flag_kobj is not NULL!, can't create zf_reset_finish_flag!\n");
-        ret = -EINVAL;
-    }
-
-    return ret;
+	int ret = 0;
+
+	op_paddr = ep_mpf_paddr;
+	zf_reset_finish_flag_kobj =
+			kobject_create_and_add(SYSFS_ZF_RESET_FINISH_FLAG_DIR, kernel_kobj);
+	if (!zf_reset_finish_flag_kobj)
+		return -ENOMEM;
+
+	ret = sysfs_create_file(zf_reset_finish_flag_kobj, &flag_attribute.attr);
+	if (ret)
+		kobject_put(zf_reset_finish_flag_kobj);
+
+	return ret;
 }
 
 void zf_reset_finish_flag_exit(void)
 {
-    if (zf_reset_finish_flag_kobj != NULL) {
-        sysfs_remove_file(zf_reset_finish_flag_kobj, &flag_attribute.attr);
-        kobject_put(zf_reset_finish_flag_kobj);
-        zf_reset_finish_flag_kobj = NULL;
-    }
+	if (zf_reset_finish_flag_kobj) {
+		sysfs_remove_file(zf_reset_finish_flag_kobj, &flag_attribute.attr);
+		kobject_put(zf_reset_finish_flag_kobj);
+	}
 }
diff --git a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zxdh_reset_zf.c b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zxdh_reset_zf.c
old mode 100755
new mode 100644
index d8f80828733e081ea08cd09ef5c5a08d00efe09a..e40e98542866e9537514847df873532d577e4b7c
--- a/src/net/drivers/net/ethernet/dinghai/zf_mpf/zxdh_reset_zf.c
+++ b/src/net/drivers/net/ethernet/dinghai/zf_mpf/zxdh_reset_zf.c
@@ -12,57 +12,51 @@
 #define ZXDH_SYSFS_FILE_EP_CHECK_REGISTER "ep_check_register"
 #define ZXDH_SYSFS_FILE_EP_RESET_INFO "ep_reset_info"
 
-
-struct zxdh_reset_dev
-{
-    uint16_t pcie_id;
-    uint64_t bar0_base_virt_addr;
-    uint64_t is_valid;
-}reset_dev = {0};
+struct zxdh_reset_dev {
+	uint64_t bar0_base_virt_addr;
+	uint64_t is_valid;
+} reset_dev = { 0 };
 
 struct zxdh_reset_dev *zxdh_get_reset_dev(void)
 {
-    return &reset_dev;
+	return &reset_dev;
 }
 
 int zxdh_init_reset_dev(struct dh_core_dev *core_dev)
 {
-    struct zxdh_reset_dev *dev = zxdh_get_reset_dev();
+	struct zxdh_reset_dev *dev = zxdh_get_reset_dev();
 
-    struct dh_en_mpf_dev *mpf_dev = dh_core_priv(core_dev);
-    dev->bar0_base_virt_addr = mpf_dev->pci_ioremap_addr;
-    dev->is_valid = 1;
-    dev->pcie_id = mpf_dev->pcie_id;
-    return 0;
+	struct dh_en_mpf_dev *mpf_dev = dh_core_priv(core_dev);
+	dev->bar0_base_virt_addr = mpf_dev->pci_ioremap_addr;
+	dev->is_valid = 1;
+	return 0;
 }
 
-
-extern int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in, struct zxdh_msg_recviver_mem *result);
-extern int zxdh_bar_chan_msg_recv_register(uint8_t event_id, zxdh_bar_chan_msg_recv_callback callback);
+extern int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in,
+									   struct zxdh_msg_recviver_mem *result);
+extern int
+zxdh_bar_chan_msg_recv_register(uint8_t event_id,
+								zxdh_bar_chan_msg_recv_callback callback);
 extern int zxdh_bar_chan_msg_recv_unregister(uint8_t event_id);
 
-enum e_reset_event
-{
-    EV_HOST_RESET = 0,
-    EV_ZF_RESET = 1,
-    EV_DINGHAI_RESET = 2,
-    EV_ZXDH_RESET_TEST = 3,
-    EV_MAX_RESET
+enum e_reset_event {
+	EV_HOST_RESET = 0,
+	EV_ZF_RESET = 1,
+	EV_DINGHAI_RESET = 2,
+	EV_ZXDH_RESET_TEST = 3,
+	EV_MAX_RESET
 };
 
-
-struct host_reset_ev_info
-{
-    int ep_no;
+struct host_reset_ev_info {
+	int ep_no;
 };
 
 struct zxdh_reset_priv {
 	enum e_reset_event e_reset_event;
-    union
-    {
-        struct host_reset_ev_info host_reset_ev;
-    } ev_info;
-    struct work_struct work;
+	union {
+		struct host_reset_ev_info host_reset_ev;
+	} ev_info;
+	struct work_struct work;
 };
 
 /* 本模块在ZF中insmod
@@ -77,7 +71,7 @@ struct zxdh_reset_priv {
 用户操作：
 1）向  ep_check_register  写入 value
    含义：通知risc-v需要进行检测的ep
-2）读取ep_check_register   
+2）读取ep_check_register
    返回value，表示当前监测的ep
 2、ep_reset_info
 功能：ep复位后，业务通过这个文件查询
@@ -91,152 +85,156 @@ struct zxdh_reset_priv {
 2）向  ep_reset_info  写入 value
    将发生reset的ep信息清0
 */
-unsigned int ep_check_register = 0;
-unsigned int ep_reset_info = 0;
-
-struct kobject *kobj_zxdh_host_reset = NULL;
+int ep_check_register;
+int ep_reset_info;
 
+struct kobject *kobj_zxdh_host_reset;
 
 /*该函数被调用在sysfs文件被读时*/
 static ssize_t sysfs_show_ep_check_register(struct kobject *kobj,
-                struct kobj_attribute *attr, char *buf)
+											struct kobj_attribute *attr,
+											char *buf)
 {
-    return sprintf(buf, "0x%08x", ep_check_register);
+	return sprintf(buf, "0x%08x", ep_check_register);
 }
 
 /* 该函数被调用在sysfs文件被写时*/
 static ssize_t sysfs_store_ep_check_register(struct kobject *kobj,
-                struct kobj_attribute *attr,const char *buf, size_t count)
+											 struct kobj_attribute *attr,
+											 const char *buf, size_t count)
 {
 	uint16_t ret = 0;
 
-    struct zxdh_pci_bar_msg in = {0}; 
-    struct zxdh_msg_recviver_mem result = {0};
-	uint8_t recv_buffer[20] = {0};
+	struct zxdh_pci_bar_msg in = { 0 };
+	struct zxdh_msg_recviver_mem result = { 0 };
+	uint8_t recv_buffer[20] = { 0 };
 	uint16_t recv_buff_len = 20;
+
+	sscanf(buf, "0x%x", &ep_check_register);
 	struct zxdh_reset_dev *dev = zxdh_get_reset_dev();
-    sscanf(buf,"0x%x",&ep_check_register);
-	
+
 	in.virt_addr = dev->bar0_base_virt_addr + ZXDH_BAR1_CHAN_OFFSET;
 	in.payload_addr = &ep_check_register;
 	in.payload_len = sizeof(ep_check_register);
-	in.src = MSG_CHAN_END_PF;//MSG_CHAN_END_MPF;
-	in.dst = MSG_CHAN_END_RISC; 
-	in.event_id = MODULE_RESET_MSG;/* 事件号 */
-    in.src_pcieid = dev->pcie_id;
+	in.src = MSG_CHAN_END_PF; // MSG_CHAN_END_MPF;
+	in.dst = MSG_CHAN_END_RISC;
+	in.event_id = MODULE_RESET_MSG; /* 事件号 */
 
-    result.recv_buffer = recv_buffer;
-    result.buffer_len = recv_buff_len;
+	result.recv_buffer = recv_buffer;
+	result.buffer_len = recv_buff_len;
 
 	ret = zxdh_bar_chan_sync_msg_send(&in, &result);
-	if (ret)
-	{
+	if (ret) {
 		pr_err("  '%s' zxdh_bar_chan_sync_msg_send failed.\n", __FUNCTION__);
 	}
-    return count;
+	return count;
 }
 
 /*该函数被调用在sysfs文件被读时*/
 static ssize_t sysfs_show_ep_reset_info(struct kobject *kobj,
-                struct kobj_attribute *attr, char *buf)
+										struct kobj_attribute *attr, char *buf)
 {
-    return sprintf(buf, "0x%08x", ep_reset_info);
+	return sprintf(buf, "0x%08x", ep_reset_info);
 }
 
 /* 该函数被调用在sysfs文件被写时*/
 static ssize_t sysfs_store_ep_reset_info(struct kobject *kobj,
-                struct kobj_attribute *attr,const char *buf, size_t count)
+										 struct kobj_attribute *attr,
+										 const char *buf, size_t count)
 {
-    sscanf(buf,"0x%x",&ep_reset_info);
-    return count;
+	sscanf(buf, "0x%x", &ep_reset_info);
+	return count;
 }
 
 /*使用__ATTR宏初始化zxdh_host_reset_attr结构体，该宏定义在include/linux/sysfs.h*/
-struct kobj_attribute zxdh_host_reset_attr_ep_check_register = __ATTR(ep_check_register, 0664, sysfs_show_ep_check_register, sysfs_store_ep_check_register);
-struct kobj_attribute zxdh_host_reset_attr_ep_reset_info = __ATTR(ep_reset_info, 0664, sysfs_show_ep_reset_info, sysfs_store_ep_reset_info);
-
-int32_t zxdh_reset_zf_rec_risc(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev)
+struct kobj_attribute zxdh_host_reset_attr_ep_check_register =
+		__ATTR(ep_check_register, 0664, sysfs_show_ep_check_register,
+			   sysfs_store_ep_check_register);
+struct kobj_attribute zxdh_host_reset_attr_ep_reset_info =
+		__ATTR(ep_reset_info, 0664, sysfs_show_ep_reset_info,
+			   sysfs_store_ep_reset_info);
+
+int32_t zxdh_reset_zf_rec_risc(void *pay_load, uint16_t len, void *reps_buffer,
+							   uint16_t *reps_len, void *dev)
 {
-    struct zxdh_reset_priv *priv = NULL;
-    uint32_t ep_no = 0;
-    uint32_t ep_reset_info_tmp = ep_reset_info;
-
-    if (pay_load && len && reps_buffer && reps_len)
-    {
-        pr_info("%s: para check ok ok ok.(%p, %x, %p, %p)\n", __func__, pay_load, len, reps_buffer, reps_len);
-    }
-    else
-    {
-        pr_err("%s: para error.(%p, %x, %p, %p)\n", __func__, pay_load, len, reps_buffer, reps_len);
-        return (uint16_t)-1;
-    }
-
+	struct zxdh_reset_priv *priv = NULL;
+	uint32_t ep_no = 0;
+	uint32_t ep_reset_info_tmp = ep_reset_info;
+
+	if (pay_load && len && reps_buffer && reps_len) {
+		pr_info("%s: para check ok ok ok.(%p, %x, %p, %p)\n", __func__,
+				pay_load, len, reps_buffer, reps_len);
+	} else {
+		pr_err("%s: para error.(%p, %x, %p, %p)\n", __func__, pay_load, len,
+			   reps_buffer, reps_len);
+		return (uint16_t)-1;
+	}
 
-    priv = pay_load;
-    ep_no = priv->ev_info.host_reset_ev.ep_no;
+	priv = pay_load;
+	ep_no = priv->ev_info.host_reset_ev.ep_no;
 
-    pr_info("  %s: received msg from RISC-V: event_id[%d] len 0x%x, ep_no=%u\n", __FUNCTION__, MODULE_RESET_MSG, len, ep_no);
+	pr_info("  %s: received msg from RISC-V: event_id[%d] len 0x%x, ep_no=%u\n",
+			__FUNCTION__, MODULE_RESET_MSG, len, ep_no);
 
-    ep_reset_info |= 1 << ep_no;
-    pr_info("  %s: ep_reset_info 0x%08x -> 0x%08x\n", __FUNCTION__, ep_reset_info_tmp, ep_reset_info);
+	ep_reset_info |= 1 << ep_no;
+	pr_info("  %s: ep_reset_info 0x%08x -> 0x%08x\n", __FUNCTION__,
+			ep_reset_info_tmp, ep_reset_info);
 
-    return 0;
+	return 0;
 }
 
-
 /*模块初始化函数*/
 int zxdh_host_reset_driver_init(struct dh_core_dev *core_dev)
 {
 	int32_t ret = 0;
-    /*创建一个目录在/sys下 */
-    kobj_zxdh_host_reset = kobject_create_and_add(ZXDH_SYSFS_DIR,NULL);
+	/*创建一个目录在/sys下 */
+	kobj_zxdh_host_reset = kobject_create_and_add(ZXDH_SYSFS_DIR, NULL);
 
-    zxdh_init_reset_dev(core_dev);
+	ret = zxdh_init_reset_dev(core_dev);
+	if (ret != 0) {
+		return -1;
+	}
 
-    /*在ZXDH_SYSFS_DIR目录下创建文件*/
-    if(sysfs_create_file(kobj_zxdh_host_reset,&zxdh_host_reset_attr_ep_check_register.attr)){
+	/*在ZXDH_SYSFS_DIR目录下创建文件*/
+	if (sysfs_create_file(kobj_zxdh_host_reset,
+						  &zxdh_host_reset_attr_ep_check_register.attr)) {
 		pr_err("  'ep_check_register' sysfs create failed.\n");
 		goto error_sysfs;
-    }
+	}
 
-    if(sysfs_create_file(kobj_zxdh_host_reset,&zxdh_host_reset_attr_ep_reset_info.attr)){
+	if (sysfs_create_file(kobj_zxdh_host_reset,
+						  &zxdh_host_reset_attr_ep_reset_info.attr)) {
 		pr_err("  'ep_reset_info' sysfs create failed.\n");
 		goto error_sysfs;
-    }
+	}
 
-    ret = zxdh_bar_chan_msg_recv_register(MODULE_RESET_MSG, zxdh_reset_zf_rec_risc);
-    if (ret != 0)
-    {
-        pr_err("  zxdh_bar_chan_msg_recv_register: event_id[%d] register failed: %d\n", MODULE_RESET_MSG, ret);
-        //return ret;
-    }
+	ret = zxdh_bar_chan_msg_recv_register(MODULE_RESET_MSG,
+										  zxdh_reset_zf_rec_risc);
+	if (ret != 0) {
+		pr_err("  zxdh_bar_chan_msg_recv_register: event_id[%d] register failed: %d\n",
+			   MODULE_RESET_MSG, ret);
+		// return ret;
+	}
 
-    pr_info("  zxdh host reset module init ok.\n");
-    return 0;
+	pr_info("  zxdh host reset module init ok.\n");
+	return 0;
 
 error_sysfs:
-    zxdh_bar_chan_msg_recv_unregister(MODULE_RESET_MSG);
+	zxdh_bar_chan_msg_recv_unregister(MODULE_RESET_MSG);
 	sysfs_remove_file(kernel_kobj, &zxdh_host_reset_attr_ep_reset_info.attr);
-	sysfs_remove_file(kernel_kobj, &zxdh_host_reset_attr_ep_check_register.attr);
+	sysfs_remove_file(kernel_kobj,
+					  &zxdh_host_reset_attr_ep_check_register.attr);
 	kobject_put(kobj_zxdh_host_reset);
 	return -1;
-
 }
 
 /*模块退出函数*/
 void zxdh_host_reset_driver_exit(struct dh_core_dev *core_dev)
 {
-    zxdh_bar_chan_msg_recv_unregister(MODULE_RESET_MSG);
+	zxdh_bar_chan_msg_recv_unregister(MODULE_RESET_MSG);
 	sysfs_remove_file(kernel_kobj, &zxdh_host_reset_attr_ep_reset_info.attr);
-	sysfs_remove_file(kernel_kobj, &zxdh_host_reset_attr_ep_check_register.attr);
+	sysfs_remove_file(kernel_kobj,
+					  &zxdh_host_reset_attr_ep_check_register.attr);
 	kobject_put(kobj_zxdh_host_reset);
-    pr_info("  zxdh host reset module remove ok.\n");
+	pr_info("  zxdh host reset module remove ok.\n");
 }
-#if 0
-module_init(zxdh_host_reset_driver_init);
-module_exit(zxdh_host_reset_driver_exit);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("zxdh");
-MODULE_DESCRIPTION("for zxdh host reset");
-#endif
diff --git a/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_ioctl.c b/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_ioctl.c
old mode 100755
new mode 100644
index ac8825612d5aba30d70011a9b89384ca5d637e59..8e639b14f175cc0b160780cf6170996c51a19a1d
--- a/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_ioctl.c
+++ b/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_ioctl.c
@@ -5,472 +5,443 @@
 #include "../en_aux/priv_queue.h"
 #include "zxdh_tools_ioctl.h"
 
-
-uint32_t user_event_pid = 0;
-
-/* Started by AICoder, pid:x7951lc26423ce61419e0a0a502a9b6cc494ddd1 */
+int32_t user_event_pid;
 int32_t zxdh_tools_mark_event_info(struct net_device *netdev, struct ifreq *ifr)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_tools_msg *msg = NULL;
-    struct zxdh_tools_reps tools_reps = {0};
-    struct dhtool_dev_pcieid_get dev_pcieid_get = {0};
-
-    DHTOOLS_LOG_INFO("is called!\n");
-    msg = (struct zxdh_tools_msg *)kzalloc(sizeof(struct zxdh_tools_msg), GFP_KERNEL);
-    if(msg == NULL)
-    {
-        DHTOOLS_LOG_ERR(" kzalloc msg failed!!!\n");
-        return -1;
-    }
-
-    if (copy_from_user(msg, ifr->ifr_ifru.ifru_data, sizeof(struct zxdh_tools_msg))) {
-        DHTOOLS_LOG_ERR("copy_from_user failed!!!\n");
-        kfree(msg);
-        return -EFAULT;
-    }
-
-    user_event_pid = msg->event_pid;
-    tools_reps.status = MSG_RECV_OK;
-    tools_reps.data[0] = msg->event_id;
-
-    DHTOOLS_LOG_INFO("en_dev->pcie_id=0x%x\n", en_dev->pcie_id);
-    DHTOOLS_LOG_INFO("user_event_pid=%d\n", user_event_pid);
-    dev_pcieid_get.dev_pcieid = en_dev->pcie_id;
-
-    if (unlikely(copy_to_user((void __user *)msg->msg_reps, &dev_pcieid_get, sizeof(struct dhtool_dev_pcieid_get))))
-    {
-        DHTOOLS_LOG_ERR("copy_to_user failed!!!\n");
-        kfree(msg);
-        return -EFAULT;
-    }
-
-    if (unlikely(copy_to_user((void __user *)msg->tools_reps, &tools_reps, sizeof(struct zxdh_tools_reps))))
-    {
-        DHTOOLS_LOG_ERR("copy_to_user failed!!!\n");
-        kfree(msg);
-        return -EFAULT;
-    }
-    kfree(msg);
-    return 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_tools_msg *msg = NULL;
+	struct zxdh_tools_reps tools_reps = { 0 };
+	struct dhtool_dev_pcieid_get dev_pcieid_get = { 0 };
+
+	DHTOOLS_LOG_INFO("is called!\n");
+	msg = (struct zxdh_tools_msg *)kzalloc(sizeof(struct zxdh_tools_msg),
+										   GFP_KERNEL);
+	if (msg == NULL) {
+		DHTOOLS_LOG_ERR(" kzalloc msg failed!!!\n");
+		return -1;
+	}
+
+	if (copy_from_user(msg, ifr->ifr_ifru.ifru_data,
+					   sizeof(struct zxdh_tools_msg))) {
+		DHTOOLS_LOG_ERR("copy_from_user failed!!!\n");
+		kfree(msg);
+		return -EFAULT;
+	}
+
+	user_event_pid = msg->event_pid;
+	tools_reps.status = MSG_RECV_OK;
+	tools_reps.data[0] = msg->event_id;
+
+	DHTOOLS_LOG_INFO("en_dev->pcie_id=0x%x\n", en_dev->pcie_id);
+	DHTOOLS_LOG_INFO("user_event_pid=%d\n", user_event_pid);
+	dev_pcieid_get.dev_pcieid = en_dev->pcie_id;
+
+	if (unlikely(copy_to_user((void __user *)msg->msg_reps, &dev_pcieid_get,
+							  sizeof(struct dhtool_dev_pcieid_get)))) {
+		DHTOOLS_LOG_ERR("copy_to_user failed!!!\n");
+		kfree(msg);
+		return -EFAULT;
+	}
+
+	if (unlikely(copy_to_user((void __user *)msg->tools_reps, &tools_reps,
+							  sizeof(struct zxdh_tools_reps)))) {
+		DHTOOLS_LOG_ERR("copy_to_user failed!!!\n");
+		kfree(msg);
+		return -EFAULT;
+	}
+	kfree(msg);
+	return 0;
 }
-/* Ended by AICoder, pid:x7951lc26423ce61419e0a0a502a9b6cc494ddd1 */
 
-int32_t zxdh_tools_ioctl_barchan_send(struct net_device *netdev, struct ifreq *ifr)
+int32_t zxdh_tools_ioctl_barchan_send(struct net_device *netdev,
+									  struct ifreq *ifr)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct zxdh_tools_msg *msg = NULL;
-    uint8_t *payload_addr = NULL;
-    uint8_t *msg_reps = NULL;
-    uint16_t msg_reps_len = 0;
-    struct zxdh_tools_reps tools_reps = {0};
-    struct zxdh_pci_bar_msg in = {0};
-    struct zxdh_msg_recviver_mem result = {0};
-    int32_t ret = 0;
-
-    DHTOOLS_LOG_INFO("is called!\n");
-    DHTOOLS_LOG_INFO("en_dev->pcie_id=0x%x\n", en_dev->pcie_id);
-
-    msg = (struct zxdh_tools_msg *)kzalloc(sizeof(struct zxdh_tools_msg), GFP_KERNEL);
-    if(msg == NULL)
-    {
-        DHTOOLS_LOG_ERR("kzalloc msg failed!!!\n");
-        return -1;
-    }
-
-    if (copy_from_user(msg, ifr->ifr_ifru.ifru_data, sizeof(struct zxdh_tools_msg))) {
-        DHTOOLS_LOG_ERR("copy_from_user failed!!!\n");
-        kfree(msg);
-        return -EFAULT;
-    }
-
-    if(msg->payload_len == 0 || msg->payload_len > BAR_MSG_PAYLOAD_MAX_LEN)
-    {
-        DHTOOLS_LOG_ERR("send para ERR: invalid payload len: %d!\n", msg->payload_len);
-        kfree(msg);
-        return -1;
-    }
-
-    payload_addr = vmalloc(msg->payload_len);
-    if(payload_addr == NULL)
-    {
-        DHTOOLS_LOG_ERR("vmalloc payload_addr failed!!!\n");
-        kfree(msg);
-        return -1;
-    }
-
-    if (copy_from_user(payload_addr, ifr->ifr_ifru.ifru_data + sizeof(struct zxdh_tools_msg), msg->payload_len)){
-        DHTOOLS_LOG_ERR("copy_from_user failed!!!\n");
-        vfree(payload_addr);
-        kfree(msg);
-        return -EFAULT;
-    }
-
-/*调试*/
-#if 0
-    DHTOOLS_LOG_INFO("msg->payload_len = %u\n", msg->payload_len);
-    int i;
-    for(i = 0; i < msg->payload_len; i+=sizeof(uint32_t))
-    {
-        DHTOOLS_LOG_INFO("*(uint32_t*)(payload_addr + %d) = %d\n", i, *(uint32_t*)(payload_addr + i));
-    }
-#endif
-
-    in.virt_addr    = (uint64_t)ZXDH_BAR_MSG_BASE(en_dev->ops->get_bar_virt_addr(en_dev->parent, 0));
-    in.payload_addr = payload_addr;
-    in.payload_len  = msg->payload_len;
-    in.src          = MSG_CHAN_END_PF;
-    in.dst          = msg->dst;
-    in.event_id     = msg->event_id;
-    in.src_pcieid   = en_dev->pcie_id;
-    in.dst_pcieid   = msg->dst_pcieid;
-
-    if(msg->msg_reps_len == 0 || msg->msg_reps_len > BAR_MSG_PAYLOAD_MAX_LEN)
-    {
-        DHTOOLS_LOG_ERR("send para ERR: invalid msg_reps_len: %d!\n", msg->msg_reps_len);
-        vfree(payload_addr);
-        kfree(msg);
-        return -1;
-    }
-    result.buffer_len = msg->msg_reps_len + REPS_HEADER_PAYLOAD_OFFSET;
-    result.recv_buffer = vmalloc(result.buffer_len);
-    if(result.recv_buffer == NULL)
-    {
-        DHTOOLS_LOG_ERR("vmalloc result.recv_buffer failed!!!\n");
-        vfree(payload_addr);
-        kfree(msg);
-        return -1;
-    }
-    msg_reps = (uint8_t *)result.recv_buffer + REPS_HEADER_PAYLOAD_OFFSET;
-    msg_reps_len = msg->msg_reps_len;
-
-    ret = zxdh_bar_chan_sync_msg_send(&in, &result);
-    if (ret != BAR_MSG_OK)
-    {
-        DHTOOLS_LOG_ERR("zxdh_bar_chan_sync_msg_send failed, ret=%d!!!\n", ret);
-    }
-
-    tools_reps.bar_or_vq_chan_ret = ret;
-    tools_reps.status = MSG_RECV_OK;
-    tools_reps.data[0] = msg->event_id;
-
-    /*调试*/
-   //DHTOOLS_LOG_INFO("result.recv_buffer 8 bytes: 0x%llx\n", *(uint64_t *)result.recv_buffer);
-
-    if (unlikely(copy_to_user((void __user *)msg->msg_reps, msg_reps, msg_reps_len)))
-    {
-        DHTOOLS_LOG_ERR("copy_to_user failed!!!\n");
-        vfree(result.recv_buffer);
-        vfree(payload_addr);
-        kfree(msg);
-        return -EFAULT;
-    }
-
-    if (unlikely(copy_to_user((void __user *)msg->tools_reps, &tools_reps, sizeof(struct zxdh_tools_reps))))
-    {
-        DHTOOLS_LOG_ERR("copy_to_user failed!!!\n");
-        vfree(result.recv_buffer);
-        vfree(payload_addr);
-        kfree(msg);
-        return -EFAULT;
-    }
-
-    vfree(result.recv_buffer);
-    vfree(payload_addr);
-    kfree(msg);
-    return 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct zxdh_tools_msg *msg = NULL;
+	uint8_t *payload_addr = NULL;
+	uint8_t *msg_reps = NULL;
+	uint16_t msg_reps_len = 0;
+	struct zxdh_tools_reps tools_reps = { 0 };
+	struct zxdh_pci_bar_msg in = { 0 };
+	struct zxdh_msg_recviver_mem result = { 0 };
+	int32_t ret = 0;
+
+	DHTOOLS_LOG_INFO("is called!\n");
+	DHTOOLS_LOG_INFO("en_dev->pcie_id=0x%x\n", en_dev->pcie_id);
+
+	msg = (struct zxdh_tools_msg *)kzalloc(sizeof(struct zxdh_tools_msg),
+										   GFP_KERNEL);
+	if (msg == NULL) {
+		DHTOOLS_LOG_ERR("kzalloc msg failed!!!\n");
+		return -1;
+	}
+
+	if (copy_from_user(msg, ifr->ifr_ifru.ifru_data,
+					   sizeof(struct zxdh_tools_msg))) {
+		DHTOOLS_LOG_ERR("copy_from_user failed!!!\n");
+		kfree(msg);
+		return -EFAULT;
+	}
+
+	if (msg->payload_len == 0 || msg->payload_len > BAR_MSG_PAYLOAD_MAX_LEN) {
+		DHTOOLS_LOG_ERR("send para ERR: invalid payload len: %d!\n",
+						msg->payload_len);
+		kfree(msg);
+		return -1;
+	}
+
+	payload_addr = vmalloc(msg->payload_len);
+	if (payload_addr == NULL) {
+		DHTOOLS_LOG_ERR("vmalloc payload_addr failed!!!\n");
+		kfree(msg);
+		return -1;
+	}
+
+	memset(payload_addr, 0, msg->payload_len);
+	if (copy_from_user(payload_addr,
+					   ifr->ifr_ifru.ifru_data + sizeof(struct zxdh_tools_msg),
+					   msg->payload_len)) {
+		DHTOOLS_LOG_ERR("copy_from_user failed!!!\n");
+		vfree(payload_addr);
+		kfree(msg);
+		return -EFAULT;
+	}
+
+	in.virt_addr = (uint64_t)ZXDH_BAR_MSG_BASE(
+			en_dev->ops->get_bar_virt_addr(en_dev->parent, 0));
+	in.payload_addr = payload_addr;
+	in.payload_len = msg->payload_len;
+	in.src = MSG_CHAN_END_PF;
+	in.dst = msg->dst;
+	in.event_id = msg->event_id;
+	in.src_pcieid = en_dev->pcie_id;
+	in.dst_pcieid = msg->dst_pcieid;
+
+	if (msg->msg_reps_len == 0 || msg->msg_reps_len > BAR_MSG_PAYLOAD_MAX_LEN) {
+		DHTOOLS_LOG_ERR("send para ERR: invalid msg_reps_len: %d!\n",
+						msg->msg_reps_len);
+		vfree(payload_addr);
+		kfree(msg);
+		return -1;
+	}
+	result.buffer_len = msg->msg_reps_len + REPS_HEADER_PAYLOAD_OFFSET;
+	result.recv_buffer = vmalloc(result.buffer_len);
+	if (result.recv_buffer == NULL) {
+		DHTOOLS_LOG_ERR("vmalloc result.recv_buffer failed!!!\n");
+		vfree(payload_addr);
+		kfree(msg);
+		return -1;
+	}
+	msg_reps = (uint8_t *)result.recv_buffer + REPS_HEADER_PAYLOAD_OFFSET;
+	msg_reps_len = msg->msg_reps_len;
+
+	ret = zxdh_bar_chan_sync_msg_send(&in, &result);
+	if (ret != BAR_MSG_OK) {
+		DHTOOLS_LOG_ERR("zxdh_bar_chan_sync_msg_send failed, ret=%d!!!\n", ret);
+	}
+
+	tools_reps.bar_or_vq_chan_ret = ret;
+	tools_reps.status = MSG_RECV_OK;
+	tools_reps.data[0] = msg->event_id;
+
+	/*调试*/
+	// DHTOOLS_LOG_INFO("result.recv_buffer 8 bytes: 0x%llx\n", *(uint64_t
+	// *)result.recv_buffer);
+
+	if (unlikely(copy_to_user((void __user *)msg->msg_reps, msg_reps,
+							  msg_reps_len))) {
+		DHTOOLS_LOG_ERR("copy_to_user failed!!!\n");
+		vfree(result.recv_buffer);
+		vfree(payload_addr);
+		kfree(msg);
+		return -EFAULT;
+	}
+
+	if (unlikely(copy_to_user((void __user *)msg->tools_reps, &tools_reps,
+							  sizeof(struct zxdh_tools_reps)))) {
+		DHTOOLS_LOG_ERR("copy_to_user failed!!!\n");
+		vfree(result.recv_buffer);
+		vfree(payload_addr);
+		kfree(msg);
+		return -EFAULT;
+	}
+
+	vfree(result.recv_buffer);
+	vfree(payload_addr);
+	kfree(msg);
+	return 0;
 }
 
-
-#ifdef ZXDH_MSGQ
 int32_t zxdh_tools_ioctl_msgq_send(struct net_device *netdev, struct ifreq *ifr)
 {
-    struct zxdh_en_device *en_dev = NULL;
-    struct msgq_dev *msgq_dev = NULL;
-    struct msgq_pkt_info pkt_info = {0};
-    struct zxdh_tools_msg *msg = NULL;
-    uint8_t *payload_addr = NULL;
-    struct zxdh_tools_reps tools_reps = {0};
-    struct reps_info msg_reps = {0};
-    int32_t ret = 0;
-
-    CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
-    CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
-
-    en_dev = netdev_priv(netdev);
-    if (en_dev == NULL)
-    {
-        LOG_ERR("en_dev is null!\n");
-        return -1;
-    }
-    msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
-    if (msgq_dev == NULL)
-    {
-        LOG_ERR("msgq_dev null!\n");
-        return -1;
-    }
-
-    DHTOOLS_LOG_INFO("is called!\n");
-    DHTOOLS_LOG_INFO("en_dev->pcie_id=0x%x\n", en_dev->pcie_id);
-
-    msg = (struct zxdh_tools_msg *)kzalloc(sizeof(struct zxdh_tools_msg), GFP_KERNEL);
-    if(msg == NULL)
-    {
-        DHTOOLS_LOG_ERR("kzalloc msg failed!!!\n");
-        return -1;
-    }
-
-    if (copy_from_user(msg, ifr->ifr_ifru.ifru_data, sizeof(struct zxdh_tools_msg))) {
-        DHTOOLS_LOG_ERR("copy_from_user failed!!!\n");
-        kfree(msg);
-        return -1;
-    }
-
-    if(msg->payload_len == 0 || msg->payload_len > MAX_PACKET_LEN)
-    {
-        DHTOOLS_LOG_ERR("send para ERR: invalid payload len: %d!\n", msg->payload_len);
-        kfree(msg);
-        return -1;
-    }
-
-    payload_addr = kzalloc(msg->payload_len + PRIV_HEADER_LEN, GFP_KERNEL);
-    if(payload_addr == NULL)
-    {
-        DHTOOLS_LOG_ERR("vmalloc payload_addr failed!!!\n");
-        kfree(msg);
-        return -1;
-    }
-
-    if (copy_from_user(payload_addr + PRIV_HEADER_LEN, ifr->ifr_ifru.ifru_data + sizeof(struct zxdh_tools_msg), msg->payload_len)){
-        DHTOOLS_LOG_ERR("copy_from_user failed!!!\n");
-        kfree(payload_addr);
-        kfree(msg);
-        return -1;
-    }
-
-/*调试*/
-#if 0
-    DHTOOLS_LOG_INFO("msg->payload_len = %u\n", msg->payload_len);
-    int i;
-    for(i = 0; i < msg->payload_len; i+=sizeof(uint32_t))
-    {
-        DHTOOLS_LOG_INFO("*(uint32_t*)(payload_addr + %d) = %d\n", i, *(uint32_t*)(payload_addr + i));
-    }
+	struct zxdh_en_device *en_dev = NULL;
+	struct msgq_dev *msgq_dev = NULL;
+	struct msgq_pkt_info pkt_info = { 0 };
+	struct zxdh_tools_msg *msg = NULL;
+	uint8_t *payload_addr = NULL;
+	struct zxdh_tools_reps tools_reps = { 0 };
+	struct reps_info msg_reps = { 0 };
+	int32_t ret = 0;
+
+	CHECK_EQUAL_ERR(ifr, NULL, -EADDRNOTAVAIL, "ifr is null!\n");
+	CHECK_EQUAL_ERR(netdev, NULL, -EADDRNOTAVAIL, "netdev is null!\n");
+
+	en_dev = netdev_priv(netdev);
+	if (en_dev == NULL) {
+		LOG_ERR("en_dev is null!\n");
+		return -1;
+	}
+	msgq_dev = (struct msgq_dev *)en_dev->msgq_dev;
+	if (msgq_dev == NULL) {
+		LOG_ERR("msgq_dev null!\n");
+		return -1;
+	}
+
+	DHTOOLS_LOG_INFO("is called!\n");
+	DHTOOLS_LOG_INFO("en_dev->pcie_id=0x%x\n", en_dev->pcie_id);
+
+	msg = (struct zxdh_tools_msg *)kzalloc(sizeof(struct zxdh_tools_msg),
+										   GFP_KERNEL);
+	if (msg == NULL) {
+		DHTOOLS_LOG_ERR("kzalloc msg failed!!!\n");
+		return -1;
+	}
+
+	if (copy_from_user(msg, ifr->ifr_ifru.ifru_data,
+					   sizeof(struct zxdh_tools_msg))) {
+		DHTOOLS_LOG_ERR("copy_from_user failed!!!\n");
+		kfree(msg);
+		return -1;
+	}
+
+	if (msg->payload_len == 0 || msg->payload_len > MAX_PACKET_LEN) {
+		DHTOOLS_LOG_ERR("send para ERR: invalid payload len: %d!\n",
+						msg->payload_len);
+		kfree(msg);
+		return -1;
+	}
+
+	payload_addr = kzalloc(msg->payload_len + PRIV_HEADER_LEN, GFP_KERNEL);
+	if (payload_addr == NULL) {
+		DHTOOLS_LOG_ERR("vmalloc payload_addr failed!!!\n");
+		kfree(msg);
+		return -1;
+	}
+
+	if (copy_from_user(payload_addr + PRIV_HEADER_LEN,
+					   ifr->ifr_ifru.ifru_data + sizeof(struct zxdh_tools_msg),
+					   msg->payload_len)) {
+		DHTOOLS_LOG_ERR("copy_from_user failed!!!\n");
+		kfree(payload_addr);
+		kfree(msg);
+		return -1;
+	}
+
+	pkt_info.event_id = msg->event_id;
+	pkt_info.timeout_us = 400000;
+	pkt_info.is_async = msg->sync_or_async;
+	pkt_info.len = msg->payload_len + PRIV_HEADER_LEN;
+	pkt_info.addr = payload_addr;
+	DHTOOLS_LOG_INFO("data_len: %d\n", pkt_info.len);
+
+	if (msg->msg_reps_len == 0 || msg->msg_reps_len > MAX_PACKET_LEN) {
+		DHTOOLS_LOG_ERR("send para ERR: invalid msg_reps_len: %d!\n",
+						msg->msg_reps_len);
+		kfree(payload_addr);
+		kfree(msg);
+		return -1;
+	}
+	msg_reps.len = msg->msg_reps_len;
+	msg_reps.addr = vmalloc(msg_reps.len);
+	if (msg_reps.addr == NULL) {
+		DHTOOLS_LOG_ERR("vmalloc msg_reps.addr failed!!!\n");
+		kfree(payload_addr);
+		kfree(msg);
+		return -1;
+	}
+
+#ifdef ZXDH_MSGQ
+	ret = zxdh_msgq_send_cmd(msgq_dev, &pkt_info, &msg_reps);
+	if (ret != MSGQ_RET_OK) {
+		DHTOOLS_LOG_ERR("zxdh_msgq_send_cmd failed: %d\n", ret);
+	}
 #endif
 
-    pkt_info.event_id = msg->event_id;
-    pkt_info.timeout_us = 400000;
-    pkt_info.is_async = msg->sync_or_async;
-    pkt_info.len = msg->payload_len + PRIV_HEADER_LEN;
-    pkt_info.addr = payload_addr;
-    DHTOOLS_LOG_INFO("data_len: %d\n", pkt_info.len);
-
-    if(msg->msg_reps_len == 0 || msg->msg_reps_len > MAX_PACKET_LEN)
-    {
-        DHTOOLS_LOG_ERR("send para ERR: invalid msg_reps_len: %d!\n", msg->msg_reps_len);
-        kfree(payload_addr);
-        kfree(msg);
-        return -1;
-    }
-    msg_reps.len = msg->msg_reps_len;
-    msg_reps.addr = vmalloc(msg_reps.len);
-    if(msg_reps.addr == NULL)
-    {
-        DHTOOLS_LOG_ERR("vmalloc msg_reps.addr failed!!!\n");
-        kfree(payload_addr);
-        kfree(msg);
-        return -1;
-    }
-
-    ret = zxdh_msgq_send_cmd(msgq_dev, &pkt_info, &msg_reps);
-    if (ret != MSGQ_RET_OK)
-    {
-        DHTOOLS_LOG_ERR("zxdh_msgq_send_cmd failed: %d\n", ret);
-    }
-
-    tools_reps.bar_or_vq_chan_ret = ret;
-    tools_reps.status = MSG_RECV_OK;
-    tools_reps.data[0] = msg->event_id;
-
-    if (unlikely(copy_to_user((void __user *)msg->msg_reps, msg_reps.addr, msg_reps.len)))
-    {
-        DHTOOLS_LOG_ERR("copy_to_user failed!!!\n");
-        goto err_ret;
-    }
-
-    if (unlikely(copy_to_user((void __user *)msg->tools_reps, &tools_reps, sizeof(struct zxdh_tools_reps))))
-    {
-        DHTOOLS_LOG_ERR("copy_to_user failed!!!\n");
-        goto err_ret;
-    }
-
-    vfree(msg_reps.addr);
-    kfree(msg);
-    return 0;
+	tools_reps.bar_or_vq_chan_ret = ret;
+	tools_reps.status = MSG_RECV_OK;
+	tools_reps.data[0] = msg->event_id;
+
+	if (unlikely(copy_to_user((void __user *)msg->msg_reps, msg_reps.addr,
+							  msg_reps.len))) {
+		DHTOOLS_LOG_ERR("copy_to_user failed!!!\n");
+		goto err_ret;
+	}
+
+	if (unlikely(copy_to_user((void __user *)msg->tools_reps, &tools_reps,
+							  sizeof(struct zxdh_tools_reps)))) {
+		DHTOOLS_LOG_ERR("copy_to_user failed!!!\n");
+		goto err_ret;
+	}
+
+	vfree(msg_reps.addr);
+	kfree(msg);
+	return 0;
 
 err_ret:
-    vfree(msg_reps.addr);
-    kfree(msg);
-    return -1;
+	vfree(msg_reps.addr);
+	kfree(msg);
+	return -1;
 }
-#endif
 
 int32_t dhtool_device_info_get(struct net_device *netdev, struct ifreq *ifr)
 {
-    struct zxdh_en_priv *en_priv = netdev_priv(netdev);
-    struct zxdh_en_device *en_dev = &en_priv->edev;
-    struct pci_dev *pdev = NULL;
-    struct pci_dev *swdsp_pdev = NULL;
-    struct pci_dev *swusp_pdev = NULL;
-    struct pci_dev *rp_pdev = NULL;
-
-    struct zxdh_tools_msg *msg = NULL;
-    struct zxdh_tools_reps tools_reps = {0};
-    struct dhtool_dev_info_get_reps dev_info_get = {0};
-    int sscanf_ret = 0;
-
-    DHTOOLS_LOG_INFO("is called!\n");
-    msg = (struct zxdh_tools_msg *)kzalloc(sizeof(struct zxdh_tools_msg), GFP_KERNEL);
-    if(msg == NULL)
-    {
-        DHTOOLS_LOG_ERR(" kzalloc msg failed!!!\n");
-        return -1;
-    }
-
-    if (copy_from_user(msg, ifr->ifr_ifru.ifru_data, sizeof(struct zxdh_tools_msg))) {
-        DHTOOLS_LOG_ERR("copy_from_user failed!!!\n");
-        kfree(msg);
-        return -EFAULT;
-    }
-
-    tools_reps.status  = MSG_RECV_OK;
-
-    pdev = en_dev->ops->get_pdev(en_dev->parent);
-    if (!pdev){
-        DHTOOLS_LOG_ERR("pdev is NULL\n");
-        kfree(msg);
-        return -EINVAL;
-    }
-
-    sscanf_ret = sscanf(pci_name(pdev), "%x:%x:%x.%u", &dev_info_get.dev_info.domain_no, &dev_info_get.dev_info.bus_no, \
-            &dev_info_get.dev_info.device_no, &dev_info_get.dev_info.func_no);
-    if(sscanf_ret != 4){
-        DHTOOLS_LOG_ERR("could not get dev domain_no、bus_no、device_no、func_no from pci_name(pdev)\n");
-        kfree(msg);
-        return -1;
-
-    }
-    DHTOOLS_LOG_INFO("dev_info, domain:bus:device.func = %04x:%02x:%02x.%x\n", dev_info_get.dev_info.domain_no, dev_info_get.dev_info.bus_no, \
-                    dev_info_get.dev_info.device_no, dev_info_get.dev_info.func_no);
-
-    swdsp_pdev = pci_upstream_bridge(pdev);
-    if (!swdsp_pdev){
-        DHTOOLS_LOG_ERR("swdsp_pdev is NULL\n");
-        kfree(msg);
-        return -EINVAL;
-    }
-
-    if(swdsp_pdev->device == SWITCH_DEVICE_ID && swdsp_pdev->vendor == SWITCH_VENDOR_ID){
-        swusp_pdev = pci_upstream_bridge(swdsp_pdev);
-        if (!swusp_pdev){
-            DHTOOLS_LOG_ERR("swusp_pdev is NULL\n");
-            kfree(msg);
-            return -EINVAL;
-        }
-
-        rp_pdev = pci_upstream_bridge(swusp_pdev);
-        if (!rp_pdev)
-        {
-            DHTOOLS_LOG_ERR("rp_pdev is NULL\n");
-            kfree(msg);
-            return -EINVAL;
-        }
-        dev_info_get.switch_or_noswitch = SWITCH;
-        sscanf_ret = sscanf(pci_name(rp_pdev), "%x:%x:%x.%u", &dev_info_get.rp_info.domain_no, &dev_info_get.rp_info.bus_no, \
-            &dev_info_get.rp_info.device_no, &dev_info_get.rp_info.func_no);
-        if(sscanf_ret != 4){
-            DHTOOLS_LOG_ERR("could not get rp domain_no、bus_no、device_no、func_no from pci_name(rp_pdev)\n");
-            kfree(msg);
-            return -1;
-        }
-        sscanf_ret = sscanf(pci_name(swusp_pdev), "%x:%x:%x.%u", &dev_info_get.swusp_info.domain_no, &dev_info_get.swusp_info.bus_no, \
-            &dev_info_get.swusp_info.device_no, &dev_info_get.swusp_info.func_no);
-        if(sscanf_ret != 4){
-            DHTOOLS_LOG_ERR("could not get swusp domain_no、bus_no、device_no、func_no from pci_name(swusp_pdev)\n");
-            kfree(msg);
-            return -1;
-        }
-    }
-    else{
-        dev_info_get.switch_or_noswitch = NO_SWITCH;
-        sscanf_ret = sscanf(pci_name(swdsp_pdev), "%x:%x:%x.%u", &dev_info_get.rp_info.domain_no, &dev_info_get.rp_info.bus_no, \
-            &dev_info_get.rp_info.device_no, &dev_info_get.rp_info.func_no);
-        if(sscanf_ret != 4){
-            DHTOOLS_LOG_ERR("could not get rp domain_no、bus_no、device_no、func_no from pci_name(swdsp_pdev)\n");
-            kfree(msg);
-            return -1;
-        }
-    }
-    DHTOOLS_LOG_INFO("rp_info, domain:bus:device.func = %04x:%02x:%02x.%x\n", dev_info_get.rp_info.domain_no, dev_info_get.rp_info.bus_no, \
-                    dev_info_get.rp_info.device_no, dev_info_get.rp_info.func_no);
-
-    if (unlikely(copy_to_user((void __user *)msg->msg_reps, &dev_info_get, sizeof(struct dhtool_dev_info_get_reps))))
-    {
-        DHTOOLS_LOG_ERR("copy_to_user failed!!!\n");
-        kfree(msg);
-        return -EFAULT;
-    }
-
-    if (unlikely(copy_to_user((void __user *)msg->tools_reps, &tools_reps, sizeof(struct zxdh_tools_reps))))
-    {
-        DHTOOLS_LOG_ERR("copy_to_user failed!!!\n");
-        kfree(msg);
-        return -EFAULT;
-    }
-    kfree(msg);
-    return 0;
+	struct zxdh_en_priv *en_priv = netdev_priv(netdev);
+	struct zxdh_en_device *en_dev = &en_priv->edev;
+	struct pci_dev *pdev = NULL;
+	struct pci_dev *swdsp_pdev = NULL;
+	struct pci_dev *swusp_pdev = NULL;
+	struct pci_dev *rp_pdev = NULL;
+
+	struct zxdh_tools_msg *msg = NULL;
+	struct zxdh_tools_reps tools_reps = { 0 };
+	struct dhtool_dev_info_get_reps dev_info_get = { 0 };
+
+	DHTOOLS_LOG_INFO("is called!\n");
+	msg = (struct zxdh_tools_msg *)kzalloc(sizeof(struct zxdh_tools_msg),
+										   GFP_KERNEL);
+	if (msg == NULL) {
+		DHTOOLS_LOG_ERR(" kzalloc msg failed!!!\n");
+		return -1;
+	}
+
+	if (copy_from_user(msg, ifr->ifr_ifru.ifru_data,
+					   sizeof(struct zxdh_tools_msg))) {
+		DHTOOLS_LOG_ERR("copy_from_user failed!!!\n");
+		kfree(msg);
+		return -EFAULT;
+	}
+
+	tools_reps.status = MSG_RECV_OK;
+
+	pdev = en_dev->ops->get_pdev(en_dev->parent);
+	if (!pdev) {
+		DHTOOLS_LOG_ERR("pdev is NULL\n");
+		kfree(msg);
+		return -EINVAL;
+	}
+
+	sscanf(pci_name(pdev), "%x:%x:%x.%u", &dev_info_get.dev_info.domain_no,
+		   &dev_info_get.dev_info.bus_no, &dev_info_get.dev_info.device_no,
+		   &dev_info_get.dev_info.func_no);
+
+	DHTOOLS_LOG_INFO("dev_info, domain:bus:device.func = %04x:%02x:%02x.%x\n",
+					 dev_info_get.dev_info.domain_no,
+					 dev_info_get.dev_info.bus_no,
+					 dev_info_get.dev_info.device_no,
+					 dev_info_get.dev_info.func_no);
+
+	swdsp_pdev = pci_upstream_bridge(pdev);
+	if (!swdsp_pdev) {
+		DHTOOLS_LOG_ERR("swdsp_pdev is NULL\n");
+		kfree(msg);
+		return -EINVAL;
+	}
+
+	if (swdsp_pdev->device == SWITCH_DEVICE_ID &&
+		swdsp_pdev->vendor == SWITCH_VENDOR_ID) {
+		swusp_pdev = pci_upstream_bridge(swdsp_pdev);
+		if (!swusp_pdev) {
+			DHTOOLS_LOG_ERR("swusp_pdev is NULL\n");
+			kfree(msg);
+			return -EINVAL;
+		}
+
+		rp_pdev = pci_upstream_bridge(swusp_pdev);
+		if (!rp_pdev) {
+			DHTOOLS_LOG_ERR("rp_pdev is NULL\n");
+			return -EINVAL;
+		}
+		dev_info_get.switch_or_noswitch = SWITCH;
+		sscanf(pci_name(rp_pdev), "%x:%x:%x.%u",
+			   &dev_info_get.rp_info.domain_no, &dev_info_get.rp_info.bus_no,
+			   &dev_info_get.rp_info.device_no, &dev_info_get.rp_info.func_no);
+		sscanf(pci_name(swusp_pdev), "%x:%x:%x.%u",
+			   &dev_info_get.swusp_info.domain_no,
+			   &dev_info_get.swusp_info.bus_no,
+			   &dev_info_get.swusp_info.device_no,
+			   &dev_info_get.swusp_info.func_no);
+	} else {
+		dev_info_get.switch_or_noswitch = NO_SWITCH;
+		sscanf(pci_name(swdsp_pdev), "%x:%x:%x.%u",
+			   &dev_info_get.rp_info.domain_no, &dev_info_get.rp_info.bus_no,
+			   &dev_info_get.rp_info.device_no, &dev_info_get.rp_info.func_no);
+	}
+	DHTOOLS_LOG_INFO("rp_info, domain:bus:device.func = %04x:%02x:%02x.%x\n",
+					 dev_info_get.rp_info.domain_no,
+					 dev_info_get.rp_info.bus_no,
+					 dev_info_get.rp_info.device_no,
+					 dev_info_get.rp_info.func_no);
+
+	if (unlikely(copy_to_user((void __user *)msg->msg_reps, &dev_info_get,
+							  sizeof(struct dhtool_dev_info_get_reps)))) {
+		DHTOOLS_LOG_ERR("copy_to_user failed!!!\n");
+		kfree(msg);
+		return -EFAULT;
+	}
+
+	if (unlikely(copy_to_user((void __user *)msg->tools_reps, &tools_reps,
+							  sizeof(struct zxdh_tools_reps)))) {
+		DHTOOLS_LOG_ERR("copy_to_user failed!!!\n");
+		kfree(msg);
+		return -EFAULT;
+	}
+	kfree(msg);
+	return 0;
 }
 
 struct zxdh_tools_ioctl_subcmd_info subcmd_table[] = {
-    {MSG_MARK_INFO,     zxdh_tools_mark_event_info},
+	{ MSG_MARK_INFO, zxdh_tools_mark_event_info },
 #ifdef ZXDH_TOOLS_MSGQ
-    {MSG_SEND_TO_RISCV,      zxdh_tools_ioctl_msgq_send},
+	{ MSG_SEND_TO_RISCV, zxdh_tools_ioctl_msgq_send },
 #else
-    {MSG_SEND_TO_RISCV,      zxdh_tools_ioctl_barchan_send},
+	{ MSG_SEND_TO_RISCV, zxdh_tools_ioctl_barchan_send },
 #endif
-    {MSG_DEVICE_INFO_GET,    dhtool_device_info_get},
+	{ MSG_DEVICE_INFO_GET, dhtool_device_info_get },
 };
 
-int32_t zxdh_tools_ioctl_dispatcher(struct net_device *netdev, struct ifreq *ifr)
+int32_t zxdh_tools_ioctl_dispatcher(struct net_device *netdev,
+									struct ifreq *ifr)
 {
-    struct zxdh_tools_msg *msg = NULL;
-    int32_t ret = 0;
-    uint32_t i = 0;
-
-    DHTOOLS_LOG_INFO("is called!\n");
-    msg = (struct zxdh_tools_msg *)kzalloc(sizeof(struct zxdh_tools_msg), GFP_KERNEL);
-    if(msg == NULL)
-    {
-        DHTOOLS_LOG_ERR("kzalloc msg failed!!!\n");
-        return -1;
-    }
-
-    if (copy_from_user(msg, ifr->ifr_ifru.ifru_data, sizeof(struct zxdh_tools_msg))) {
-        DHTOOLS_LOG_ERR("copy_from_user failed!!!\n");
-        kfree(msg);
-        return -EFAULT;
-    }
-
-    for (i = 0; i < ARRAY_SIZE(subcmd_table); i++){
-        if((subcmd_table[i].subcmd == msg->subcmd) && (subcmd_table[i].subcmd_callback)){
-            ret = subcmd_table[i].subcmd_callback(netdev, ifr);
-        }
-    }
-
-    kfree(msg);
-    return ret;
+	struct zxdh_tools_msg *msg = NULL;
+	int32_t ret = 0;
+	uint32_t i = 0;
+
+	DHTOOLS_LOG_INFO("is called!\n");
+	msg = (struct zxdh_tools_msg *)kzalloc(sizeof(struct zxdh_tools_msg),
+										   GFP_KERNEL);
+	if (msg == NULL) {
+		DHTOOLS_LOG_ERR("kzalloc msg failed!!!\n");
+		return -1;
+	}
+
+	if (copy_from_user(msg, ifr->ifr_ifru.ifru_data,
+					   sizeof(struct zxdh_tools_msg))) {
+		DHTOOLS_LOG_ERR("copy_from_user failed!!!\n");
+		kfree(msg);
+		return -EFAULT;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(subcmd_table); i++) {
+		if ((subcmd_table[i].subcmd == msg->subcmd) &&
+			(subcmd_table[i].subcmd_callback)) {
+			ret = subcmd_table[i].subcmd_callback(netdev, ifr);
+		}
+	}
+
+	kfree(msg);
+	return ret;
 }
 
-
+EXPORT_SYMBOL_GPL(zxdh_tools_ioctl_dispatcher);
diff --git a/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_ioctl.h b/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_ioctl.h
old mode 100755
new mode 100644
index 0e1978b8aa69327c0ad04584030dbde4a710e924..92c2a142f33c8526ac8a132f7df2e223f3500b9f
--- a/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_ioctl.h
+++ b/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_ioctl.h
@@ -5,84 +5,73 @@
 
 //#define       ZXDH_TOOLS_MSGQ
 
-#define       SWITCH_DEVICE_ID    0x1113
-#define       SWITCH_VENDOR_ID    0x1556
-typedef enum
-{
-    MSG_MARK_INFO = 0,
-    MSG_SEND_TO_RISCV,
-    MSG_DEVICE_INFO_GET,
-    SUBCMD_NUM=10,
-}MSG_SUBCMD;
+#define SWITCH_DEVICE_ID 0x1113
+#define SWITCH_VENDOR_ID 0x1556
+typedef enum {
+	MSG_MARK_INFO = 0,
+	MSG_SEND_TO_RISCV,
+	MSG_DEVICE_INFO_GET,
+	SUBCMD_NUM = 10,
+} MSG_SUBCMD;
 
+typedef enum {
+	MSG_RECV_OK = 1,
+} MSG_RESPONSE;
 
-typedef enum
-{
-    MSG_RECV_OK = 1,
-}MSG_RESPONSE;
+typedef enum {
+	NO_SWITCH = 0,
+	SWITCH = 1,
+} SWITCH_FLAG;
 
-typedef enum
-{
-    NO_SWITCH = 0,
-    SWITCH = 1,
-}SWITCH_FLAG;
+struct zxdh_tools_msg {
+	uint32_t subcmd; // provider care
+	uint32_t event_pid; // provider care
+	void *tools_reps; // provider care
+	uint32_t event_id; // caller care
+	uint16_t dst; // caller care
+	uint16_t dst_pcieid; // caller care
+	void *msg_reps; // caller care
+	uint16_t msg_reps_len; // caller care
+	uint16_t sync_or_async; // caller care
+	uint16_t payload_len; // caller care
+	uint16_t reserved; // caller care
+	uint8_t payload[0];
+} __attribute__((packed));
 
-struct zxdh_tools_msg
-{
-    uint32_t subcmd;            //provider care
-    uint32_t event_pid;         //provider care
-    void*    tools_reps;        //provider care
-    uint32_t event_id;          //caller care
-    uint16_t dst;               //caller care
-    uint16_t dst_pcieid;        //caller care
-    void*    msg_reps;          //caller care
-    uint16_t msg_reps_len;      //caller care
-    uint16_t sync_or_async;     //caller care
-    uint16_t payload_len;       //caller care
-    uint16_t reserved;           //caller care
-    uint8_t  payload[0];
-}__attribute__((packed));
-
-struct zxdh_tools_reps
-{
-    uint32_t status; /* must be */
-    int32_t bar_or_vq_chan_ret;
-    uint32_t data[15];
+struct zxdh_tools_reps {
+	uint32_t status; /* must be */
+	int32_t bar_or_vq_chan_ret;
+	uint32_t data[15];
 };
 
-struct zxdh_tools_ioctl_subcmd_info
-{
-    MSG_SUBCMD subcmd;
-    int32_t (*subcmd_callback)(struct net_device *netdev, struct ifreq *ifr);
+struct zxdh_tools_ioctl_subcmd_info {
+	MSG_SUBCMD subcmd;
+	int32_t (*subcmd_callback)(struct net_device *netdev, struct ifreq *ifr);
 };
 
-struct dhtool_dev_pcieid_get
-{
-   uint32_t dev_pcieid;
+struct dhtool_dev_pcieid_get {
+	uint32_t dev_pcieid;
 };
-struct dhtool_dev_info
-{
-    uint32_t domain_no;
-    uint32_t bus_no;
-    uint32_t device_no;
-    uint32_t func_no;
+struct dhtool_dev_info {
+	uint32_t domain_no;
+	uint32_t bus_no;
+	uint32_t device_no;
+	uint32_t func_no;
 };
 
-struct dhtool_dev_info_get_reps
-{
-    SWITCH_FLAG switch_or_noswitch;
-    struct dhtool_dev_info dev_info;
-    struct dhtool_dev_info rp_info;
-    union
-    {
-        struct dhtool_dev_info swusp_info;
-    };
+struct dhtool_dev_info_get_reps {
+	SWITCH_FLAG switch_or_noswitch;
+	struct dhtool_dev_info dev_info;
+	struct dhtool_dev_info rp_info;
+	union {
+		struct dhtool_dev_info swusp_info;
+	};
 };
 
-int32_t zxdh_tools_ioctl_dispatcher(struct net_device *netdev, struct ifreq *ifr);
+int32_t zxdh_tools_ioctl_dispatcher(struct net_device *netdev,
+									struct ifreq *ifr);
 
 #define DHTOOLS_LOG_ERR(fmt, arg...) DH_LOG_ERR(MODULE_DHTOOLS, fmt, ##arg);
 #define DHTOOLS_LOG_INFO(fmt, arg...) DH_LOG_INFO(MODULE_DHTOOLS, fmt, ##arg);
 
-
 #endif
diff --git a/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_netlink.c b/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_netlink.c
index d17113b7f91c7de60f0a31a6649f2027c8862b55..f6c1c27bd579255e3fd862d0162c7ea0f524b096 100644
--- a/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_netlink.c
+++ b/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_netlink.c
@@ -5,174 +5,176 @@
 #include "zxdh_tools_ioctl.h"
 #include "zxdh_tools_netlink.h"
 
-
-int32_t zxdh_tools_genl_recv_doit(struct sk_buff *skb, struct genl_info *info);
-  /* operation definition */
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 10, 0))
+/* operation definition */
 static struct nla_policy zxdh_tools_genl_policy[ZXDH_TOOLS_A_MAX + 1] = {
-        [ZXDH_TOOLS_A_MSG] = { .type = NLA_NUL_STRING },
+	[ZXDH_TOOLS_A_MSG] = { .type = NLA_NUL_STRING },
 };
-#endif
 
-struct genl_ops zxdh_tools_gnl_ops[] = {
-    {
-        .cmd = ZXDH_TOOLS_C_ECHO,
-        .flags = 0,
+struct genl_ops zxdh_tools_gnl_ops[] = { {
+		.cmd = ZXDH_TOOLS_C_ECHO,
+		.flags = 0,
 #if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 10, 0))
-        .policy = zxdh_tools_genl_policy,
+		.policy = zxdh_tools_genl_policy,
 #endif
-        .doit = zxdh_tools_genl_recv_doit,
-        .dumpit = NULL,
-    }
-};
+		.doit = zxdh_tools_genl_recv_doit,
+		.dumpit = NULL,
+} };
 
 static struct genl_family zxdh_tools_msg_family = {
-       .hdrsize = 0,
-       .name = ZXDH_TOOLS_NETLINK_NAME,
-       .version = 1,
-       .maxattr = ZXDH_TOOLS_A_MAX,
-       .ops = zxdh_tools_gnl_ops,
-       .n_ops = 1,
+	.hdrsize = 0,
+	.name = ZXDH_TOOLS_NETLINK_NAME,
+	.version = 1,
+	.maxattr = ZXDH_TOOLS_A_MAX,
+	.ops = zxdh_tools_gnl_ops,
+	.n_ops = 1,
 };
 
 /*
-* genl_msg_prepare_usr_msg : 构建netlink及gennetlink首部
-* @cmd : genl_ops的cmd
-* @size : gen_netlink用户数据的长度（包括用户定义的首部）
-*/
-int32_t zxdh_tools_genl_msg_prepare_usr_msg(u8 cmd, size_t size, uint32_t pid, struct sk_buff **skbp)
+ * genl_msg_prepare_usr_msg : 构建netlink及gennetlink首部
+ * @cmd : genl_ops的cmd
+ * @size : gen_netlink用户数据的长度（包括用户定义的首部）
+ */
+int32_t zxdh_tools_genl_msg_prepare_usr_msg(u8 cmd, size_t size, pid_t pid,
+											struct sk_buff **skbp)
 {
-    struct sk_buff *skb;
-    DHTOOLS_LOG_INFO("is called!\n");
-    /* create a new netlink msg */
-    skb = genlmsg_new(size, GFP_KERNEL);
-    if (skb == NULL)
-    {
-        DHTOOLS_LOG_ERR("genlmsg_new failed!!!\n");
-        return -ENOMEM;
-    }
-    /* Add a new netlink message to an skb */
-    genlmsg_put(skb, pid, 0, &zxdh_tools_msg_family, 0, cmd);
-    *skbp = skb;
-    return 0;
+	struct sk_buff *skb;
+	DHTOOLS_LOG_INFO("is called!\n");
+	/* create a new netlink msg */
+	skb = genlmsg_new(size, GFP_KERNEL);
+	if (skb == NULL) {
+		DHTOOLS_LOG_ERR("genlmsg_new failed!!!\n");
+		return -ENOMEM;
+	}
+	/* Add a new netlink message to an skb */
+	genlmsg_put(skb, pid, 0, &zxdh_tools_msg_family, 0, cmd);
+	*skbp = skb;
+	return 0;
 }
 
 /*
-* 添加用户数据，及添加一个netlink addribute
-*@type : nlattr的type
-*@len : nlattr中的len
-*@data : 用户数据
-*/
-int32_t zxdh_tools_genl_msg_mk_usr_msg(struct sk_buff *skb, int type, void *data, int len)
+ * 添加用户数据，及添加一个netlink addribute
+ *@type : nlattr的type
+ *@len : nlattr中的len
+ *@data : 用户数据
+ */
+int32_t zxdh_tools_genl_msg_mk_usr_msg(struct sk_buff *skb, int type,
+									   void *data, int len)
 {
-    int rc;
-    DHTOOLS_LOG_INFO("is called!\n");
-    /* add a netlink attribute to a socket buffer */
-    if ((rc = nla_put(skb, type, len, data)) != 0)
-    {
-        DHTOOLS_LOG_ERR("nla_put failed, rc=%d!!!\n",rc);
-        return rc;
-    }
-    return 0;
+	int rc;
+	DHTOOLS_LOG_INFO("is called!\n");
+	/* add a netlink attribute to a socket buffer */
+	rc = nla_put(skb, type, len, data);
+	if (rc != 0) {
+		DHTOOLS_LOG_ERR("nla_put failed, rc=%d!!!\n", rc);
+		return rc;
+	}
+	return 0;
 }
 
 /**
-* genl_msg_send_to_user - 通过generic netlink发送数据到netlink
-*
-* @data: 发送数据缓存
-* @len: 数据长度 单位：byte
-* @pid: 发送到的客户端pid
-*/
-int32_t zxdh_tools_genl_msg_send_to_user(void *data, uint16_t len, uint32_t pid)
+ * genl_msg_send_to_user - 通过generic netlink发送数据到netlink
+ *
+ * @data: 发送数据缓存
+ * @len: 数据长度 单位：byte
+ * @pid: 发送到的客户端pid
+ */
+int32_t zxdh_tools_genl_msg_send_to_user(void *data, int len, pid_t pid)
 {
-    struct sk_buff *skb;
-    uint16_t size;
-    int rc;
-
-    DHTOOLS_LOG_INFO("is called!\n");
-    size = nla_total_size(len); /* total length of attribute including padding */
-    rc = zxdh_tools_genl_msg_prepare_usr_msg(ZXDH_TOOLS_C_ECHO, size, pid, &skb);
-    if (rc)
-    {
-        DHTOOLS_LOG_ERR("zxdh_tools_genl_msg_prepare_usr_msg failed,rc=%d!!!\n", rc);
-        return rc;
-    }
-
-    rc = zxdh_tools_genl_msg_mk_usr_msg(skb, ZXDH_TOOLS_A_MSG, data, len);
-    if (rc)
-    {
-        DHTOOLS_LOG_ERR("zxdh_tools_genl_msg_mk_usr_msg failed,rc=%d!!!\n", rc);
-        kfree_skb(skb);
-        return rc;
-    }
-
-    rc = genlmsg_unicast(&init_net, skb, pid);
-    if (rc < 0)
-    {
-        DHTOOLS_LOG_ERR("genlmsg_unicast failed, rc=%d!!!\n", rc);
-        return rc;
-    }
-    DHTOOLS_LOG_INFO("genlmsg_unicast is called, and send msg to user success.\n");
-    return 0;
+	struct sk_buff *skb;
+	size_t size;
+	int rc;
+
+	DHTOOLS_LOG_INFO("is called!\n");
+	size = nla_total_size(
+			len); /* total length of attribute including padding */
+	rc = zxdh_tools_genl_msg_prepare_usr_msg(ZXDH_TOOLS_C_ECHO, size, pid,
+											 &skb);
+	if (rc) {
+		DHTOOLS_LOG_ERR("zxdh_tools_genl_msg_prepare_usr_msg failed,rc=%d!!!\n",
+						rc);
+		return rc;
+	}
+
+	rc = zxdh_tools_genl_msg_mk_usr_msg(skb, ZXDH_TOOLS_A_MSG, data, len);
+	if (rc) {
+		DHTOOLS_LOG_ERR("zxdh_tools_genl_msg_mk_usr_msg failed,rc=%d!!!\n", rc);
+		kfree_skb(skb);
+		return rc;
+	}
+
+	rc = genlmsg_unicast(&init_net, skb, pid);
+	if (rc < 0) {
+		DHTOOLS_LOG_ERR("genlmsg_unicast failed, rc=%d!!!\n", rc);
+		return rc;
+	}
+	DHTOOLS_LOG_INFO(
+			"genlmsg_unicast is called, and send msg to user success.\n");
+	return 0;
 }
 
-extern uint32_t user_event_pid;
-int32_t zxdh_tools_sendto_user_netlink(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev)
+extern int32_t user_event_pid;
+int32_t zxdh_tools_sendto_user_netlink(void *pay_load, uint16_t len,
+									   void *reps_buffer, uint16_t *reps_len,
+									   void *dev)
 {
-    struct zxdh_en_device *en_dev = (struct zxdh_en_device *)dev;
-    int32_t ret = 0;
-
-    DHTOOLS_LOG_INFO("is called!\n");
-    if (en_dev == NULL)
-    {
-        DHTOOLS_LOG_ERR("dev is NULL\n");
-        return -1;
-    }
-
-    if ((pay_load == NULL) || (len == 0)) {
-        DHTOOLS_LOG_ERR("invalid para,  pay_load = 0x%llx, len = %d\n", (uint64_t)pay_load, len);
-        return -1;
-    }
-
-    DHTOOLS_LOG_INFO("en_dev->pcie_id=0x%x\n", en_dev->pcie_id);
-    DHTOOLS_LOG_INFO("user_event_pid=%d\n", user_event_pid);
-    DHTOOLS_LOG_INFO("pay_load = 0x%llx, payload_len = %d\n", (uint64_t)pay_load, len);
-    DHTOOLS_LOG_INFO("*(uint32_t *)pay_load(op_code)=%d\n", *(uint32_t *)pay_load);
-
-    ret = zxdh_tools_genl_msg_send_to_user(pay_load, len, user_event_pid);
-    if (ret)
-    {
-        DHTOOLS_LOG_ERR("zxdh_tools_genl_msg_send_to_user failed, ret=%d!!!\n", ret);
-        return ret;
-    }
-    DHTOOLS_LOG_INFO("zxdh_tools_sendto_user_netlink end, send msg to user success.\n");
-    return 0;
+	struct zxdh_en_device *en_dev = (struct zxdh_en_device *)dev;
+	int32_t ret = 0;
+
+	DHTOOLS_LOG_INFO("is called!\n");
+	if (en_dev == NULL) {
+		DHTOOLS_LOG_ERR("dev is NULL\n");
+		return -1;
+	}
+
+	if ((pay_load == NULL) || (len == 0)) {
+		DHTOOLS_LOG_ERR("invalid para,  pay_load = 0x%llx, len = %d\n",
+						(uint64_t)pay_load, len);
+		return -1;
+	}
+
+	DHTOOLS_LOG_INFO("en_dev->pcie_id=0x%x\n", en_dev->pcie_id);
+	DHTOOLS_LOG_INFO("user_event_pid=%d\n", user_event_pid);
+	DHTOOLS_LOG_INFO("pay_load = 0x%llx, payload_len = %d\n",
+					 (uint64_t)pay_load, len);
+	DHTOOLS_LOG_INFO("*(uint32_t *)pay_load(op_code)=%d\n",
+					 *(uint32_t *)pay_load);
+
+	ret = zxdh_tools_genl_msg_send_to_user(pay_load, len, user_event_pid);
+	if (ret) {
+		DHTOOLS_LOG_ERR("zxdh_tools_genl_msg_send_to_user failed, ret=%d!!!\n",
+						ret);
+		return ret;
+	}
+	DHTOOLS_LOG_INFO(
+			"zxdh_tools_sendto_user_netlink end, send msg to user success.\n");
+	return 0;
 }
-
+EXPORT_SYMBOL_GPL(zxdh_tools_sendto_user_netlink);
 
 /* doit函数*/
 int32_t zxdh_tools_genl_recv_doit(struct sk_buff *skb, struct genl_info *info)
 {
-    DHTOOLS_LOG_INFO("is called!\n");
-    return 0;
+	DHTOOLS_LOG_INFO("is called!\n");
+	return 0;
 }
 
 int32_t zxdh_tools_netlink_register(void)
 {
-    int ret = 0;
-    ret = genl_register_family(&zxdh_tools_msg_family);
-    if(ret)
-    {
-       DHTOOLS_LOG_ERR("zxdh_tools_netlink_family register failed, ret=%d!!!\n", ret);
-       return 1;
-    }
-
-    return 0;
+	int ret = 0;
+	ret = genl_register_family(&zxdh_tools_msg_family);
+	if (ret) {
+		DHTOOLS_LOG_ERR(
+				"zxdh_tools_netlink_family register failed, ret=%d!!!\n", ret);
+		return 1;
+	}
+	DHTOOLS_LOG_INFO("zxdh_tools_netlink_family register success.\n");
+	return 0;
 }
-
+EXPORT_SYMBOL_GPL(zxdh_tools_netlink_register);
 
 void zxdh_tools_netlink_unregister(void)
 {
-    genl_unregister_family(&zxdh_tools_msg_family);
+	genl_unregister_family(&zxdh_tools_msg_family);
+	DHTOOLS_LOG_INFO("zxdh_tools_netlink_family unregister.....\n");
 }
-
+EXPORT_SYMBOL_GPL(zxdh_tools_netlink_unregister);
diff --git a/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_netlink.h b/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_netlink.h
index 53f682517f949e8acfc156d76d82426966e13893..0a044bc37f135eb9761b59f70d661ab613b16c6e 100644
--- a/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_netlink.h
+++ b/src/net/drivers/net/ethernet/dinghai/zxdh_tools/zxdh_tools_netlink.h
@@ -1,53 +1,52 @@
 #ifndef ZXDH_TOOLS_NETLINK_H_
 #define ZXDH_TOOLS_NETLINK_H_
 
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define NLA_DATA(na)                   ((void *)((char *)(na) + NLA_HDRLEN))
-#define ZXDH_TOOLS_NETLINK_NAME         "tools_family"
+#define NLA_DATA(na) ((void *)((char *)(na) + NLA_HDRLEN))
+#define ZXDH_TOOLS_NETLINK_NAME "tools_family"
 
 /* 属性类型*/
 enum {
-    ZXDH_TOOLS_A_UNSPEC,
-    ZXDH_TOOLS_A_MSG,
-    __ZXDH_TOOLS_A_MAX,
+	ZXDH_TOOLS_A_UNSPEC,
+	ZXDH_TOOLS_A_MSG,
+	__ZXDH_TOOLS_A_MAX,
 };
 #define ZXDH_TOOLS_A_MAX (__ZXDH_TOOLS_A_MAX - 1)
 
 /* 操作码*/
 enum {
-    ZXDH_TOOLS_C_UNSPEC,
-    ZXDH_TOOLS_C_ECHO,
-    __ZXDH_TOOLS_C_ECHO,
+	ZXDH_TOOLS_C_UNSPEC,
+	ZXDH_TOOLS_C_ECHO,
+	__ZXDH_TOOLS_C_ECHO,
 };
 #define ZXDH_TOOLS_C_MAX (__ZXDH_TOOLS_C_MAX - 1)
 
-typedef enum
-{
-    FWUPDATE = 27,
+typedef enum {
+	FWUPDATE = 27,
 } event_op_code;
 
 struct zxdh_tools_recv_msg {
-    event_op_code op_code;
-    uint8_t status;
+	event_op_code op_code;
+	uint8_t status;
 };
 
-
-int32_t zxdh_tools_sendto_user_netlink(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev);
+int zxdh_tools_genl_recv_doit(struct sk_buff *skb, struct genl_info *info);
+int zxdh_tools_genl_msg_prepare_usr_msg(u8 cmd, size_t size, pid_t pid,
+										struct sk_buff **skbp);
+int zxdh_tools_genl_msg_mk_usr_msg(struct sk_buff *skb, int type, void *data,
+								   int len);
+int zxdh_tools_genl_msg_send_to_user(void *data, int len, pid_t pid);
+int32_t zxdh_tools_sendto_user_netlink(void *pay_load, uint16_t len,
+									   void *reps_buffer, uint16_t *reps_len,
+									   void *dev);
 int zxdh_tools_netlink_register(void);
 void zxdh_tools_netlink_unregister(void);
 
-
 #ifdef __cplusplus
 }
 #endif
 
-
 #endif /* ZXDH_TOOLS_NETLINK_H_  */
-
-
-
-
diff --git a/src/net/drivers/pcie/zxdh_pcie/Makefile b/src/net/drivers/pcie/zxdh_pcie/Makefile
index 9ce6b5cba1afbfffc67a23b4ab9e65eae0ee9ad0..86abe299b31cbf4cdf11e43971abc083e85820e6 100644
--- a/src/net/drivers/pcie/zxdh_pcie/Makefile
+++ b/src/net/drivers/pcie/zxdh_pcie/Makefile
@@ -1,15 +1,9 @@
 subdir-ccflags-y += -I$(src)
 subdir-ccflags-y += -I$(CWD)/include/
 subdir-ccflags-y += -include $(CWD)/autoconf.h
-ccflags-y += -Werror
 
-
-ifeq ($(CONFIG_DRIVER_VERSION),)
-EXTRA_CFLAGS += -DDRIVER_VERSION_VAL=\"1.0-1\"
-$(info CONFIG_HPF_DRIVER_VERSION is null, EXTRA_CFLAGS=$(EXTRA_CFLAGS))
-else
-EXTRA_CFLAGS += -DDRIVER_VERSION_VAL=\"$(CONFIG_DRIVER_VERSION)\"
-$(info CONFIG_HPF_DRIVER_VERSION is not null, EXTRA_CFLAGS=$(EXTRA_CFLAGS))
+ifeq (${NEED_AUX_BUS},2)
+EXTRA_CFLAGS += -DAUX_BUS_NO_SUPPORT
 endif
 
 obj-$(CONFIG_DINGHAI_HPF) += zxdh_hpf.o
diff --git a/src/net/drivers/pcie/zxdh_pcie/bar_msg.c b/src/net/drivers/pcie/zxdh_pcie/bar_msg.c
index 1aa187f81b493708fa97a57fc51d65b9b3ddbc84..32d7f894554fb4071b4dad19a449b9dc5db46f08 100644
--- a/src/net/drivers/pcie/zxdh_pcie/bar_msg.c
+++ b/src/net/drivers/pcie/zxdh_pcie/bar_msg.c
@@ -1,79 +1,76 @@
-#include "bar_msg.h" 
+#include "bar_msg.h"
 #include "pcie_common.h"
 
-int pcie_mt_send_msg(void *msg_info, u32 msg_size, void *resp_msg, u32 resp_size)
+int pcie_mt_send_msg(void *msg_info, u32 msg_size, void *resp_msg,
+					 u32 resp_size)
 {
-    struct zxdh_pci_bar_msg in = {0};
-    struct zxdh_msg_recviver_mem result = {0};
-    struct pci_dev *pdev = NULL;
-    void __iomem *bar_virt_addr = NULL;
-    u8 head_data = 0xFF;
-    u16 ret = 0;
-    u16 pcie_id = 0;
-    u64 bar_addr = 0;
+	struct zxdh_pci_bar_msg in = { 0 };
+	struct zxdh_msg_recviver_mem result = { 0 };
+	struct pci_dev *pdev = NULL;
+	void __iomem *bar_virt_addr = NULL;
+	u16 ret = 0;
+	u16 pcie_id = 0;
+	u64 bar_addr = 0;
 
-    if (msg_info == NULL)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "The msg_info is NULL\n");
-        return -EINVAL;
-    }
+	if (msg_info == NULL) {
+		DH_LOG_ERR(MODULE_FUC_HP, "The msg_info is NULL\n");
+		return -EINVAL;
+	}
 
-    pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, NULL);
-    if (pdev == NULL)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Can not find devices: deviceID %x, VendorID: %x\n", HP_VENDOR_ID, HP_DEVICE_ID);
-        return -EINVAL;
-    }
+	pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, NULL);
+	if (pdev == NULL) {
+		DH_LOG_ERR(MODULE_FUC_HP,
+				   "Can not find devices: deviceID %x, VendorID: %x\n",
+				   HP_VENDOR_ID, HP_DEVICE_ID);
+		return -EINVAL;
+	}
 
-    bar_addr = pci_resource_start(pdev, 0);
-    bar_virt_addr = ioremap(bar_addr, HP_IOREMAP_SIZE);
+	bar_addr = pci_resource_start(pdev, 0);
+	bar_virt_addr = ioremap(bar_addr, HP_IOREMAP_SIZE);
 
-    /* 填充用户参数in */
-    in.virt_addr = (u64)bar_virt_addr + HP_BAR_MSG_OFFSET;      /* 使用PF1的bar0偏移8k */
-    in.payload_addr = msg_info;                                 /* 消息静荷buffer地址 */
-    in.payload_len = msg_size;                                  /* 消息长度 */
-    in.src = MSG_CHAN_END_PF;                                   /* 从mpf通道下发 */
-    in.dst = MSG_CHAN_END_RISC;                                 /* 消息发到risc */
-    in.event_id = PCIE_FUNC_HP_EVENT_ID;                        /* 调用PCIE的消息处理函数 */
-    in.src_pcieid = pcie_id;
+	/* 填充用户参数in */
+	in.virt_addr =
+			(u64)bar_virt_addr + HP_BAR_MSG_OFFSET; /* 使用PF1的bar0偏移8k */
+	in.payload_addr = msg_info; /* 消息静荷buffer地址 */
+	in.payload_len = msg_size; /* 消息长度 */
+	in.src = MSG_CHAN_END_PF; /* 从mpf通道下发 */
+	in.dst = MSG_CHAN_END_RISC; /* 消息发到risc */
+	in.event_id = PCIE_FUNC_HP_EVENT_ID; /* 调用PCIE的消息处理函数 */
+	in.src_pcieid = pcie_id;
 
-    result.buffer_len = BUF_SIZE;                                /* 用户准备一个存放消息回复的buffer, buffer长度 */
-    result.recv_buffer = kmalloc(result.buffer_len, GFP_KERNEL); /* 消息回复buffer地址 */
-    if (!result.recv_buffer)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Failed to allocate recv_buffer\n");
-        return -EINVAL;
-    }
-    memset(result.recv_buffer, 0, result.buffer_len);
+	result.buffer_len =
+			BUF_SIZE; /* 用户准备一个存放消息回复的buffer, buffer长度 */
+	result.recv_buffer =
+			kmalloc(result.buffer_len, GFP_KERNEL); /* 消息回复buffer地址 */
+	if (!result.recv_buffer) {
+		DH_LOG_ERR(MODULE_FUC_HP, "Failed to allocate recv_buffer\n");
+		return -EINVAL;
+	}
 
-    ret = zxdh_bar_chan_sync_msg_send(&in, &result); /* 发送同步消息 */
+	ret = zxdh_bar_chan_sync_msg_send(&in, &result); /* 发送同步消息 */
 
-    iounmap(bar_virt_addr);
-    bar_virt_addr = NULL;
+	iounmap(bar_virt_addr);
+	bar_virt_addr = NULL;
 
-    /* 如果接口返回值不为0，则说明消息失败 */
-    if (ret != 0)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "pcie mt send msg failed, ret:%d.\n", ret);
-        goto exit;
-    }
+	/* 如果接口返回值不为0，则说明消息失败 */
+	if (ret != 0) {
+		DH_LOG_ERR(MODULE_FUC_HP, "pcie mt send msg failed, ret:%d.\n", ret);
+		goto exit;
+	}
 
-    /* 如果消息发送成功， 从recv_buffer + 1的位置往后两字节取回复数据长度， recv_buffer + 4的位置开始取数据内容 */
-    head_data = *((u8 *)(result.recv_buffer + 4));
-    if (head_data == 0x1)
-    {
-        DH_LOG_INFO(MODULE_FUC_HP, "pcie mt remote SUCCESS!\n");
-        memcpy(resp_msg, result.recv_buffer + 4, resp_size);
-        ret = 0;
-    }
-    else
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "pcie mt test FAIL!\n");
-        ret = -EINVAL;
-    }
+	/* 如果消息发送成功， 从recv_buffer + 1的位置往后两字节取回复数据长度，
+   * recv_buffer + 4的位置开始取数据内容 */
+	if (*((u8 *)(result.recv_buffer + 4)) == 0x1) {
+		DH_LOG_INFO(MODULE_FUC_HP, "pcie mt remote SUCCESS!\n");
+		memcpy(resp_msg, result.recv_buffer + 4, resp_size);
+		ret = 0;
+	} else {
+		DH_LOG_ERR(MODULE_FUC_HP, "pcie mt test FAIL!\n");
+		ret = -EINVAL;
+	}
 
 exit:
-    kfree(result.recv_buffer);
-    result.recv_buffer = NULL;
-    return ret;
+	kfree(result.recv_buffer);
+	result.recv_buffer = NULL;
+	return ret;
 }
\ No newline at end of file
diff --git a/src/net/drivers/pcie/zxdh_pcie/bar_msg.h b/src/net/drivers/pcie/zxdh_pcie/bar_msg.h
index 91472a0e39bfd975afbcba44b8b9bb815791d74d..581ce5bef66cbb16b49b752cdb20c77480741684 100644
--- a/src/net/drivers/pcie/zxdh_pcie/bar_msg.h
+++ b/src/net/drivers/pcie/zxdh_pcie/bar_msg.h
@@ -16,16 +16,16 @@ extern "C" {
 #include <linux/platform_device.h>
 // #include <linux/workqueue.h>
 
-#define PCIE_FUNC_HP_EVENT_ID       44
-#define BUF_SIZE            0x1000
+#define PCIE_FUNC_HP_EVENT_ID 44
+#define BUF_SIZE 0x1000
 
 /* bar消息通道使用pf信息 */
-#define HP_BAR_MSG_OFFSET   0x2000
-#define HP_VENDOR_ID        0x1cf2
-#define HP_DEVICE_ID        0x8031
+#define HP_BAR_MSG_OFFSET 0x2000
+#define HP_VENDOR_ID 0x1cf2
+#define HP_DEVICE_ID 0x8031
 // #define HP_VENDOR_ID        0x16c3
 // #define HP_DEVICE_ID        0
-#define HP_IOREMAP_SIZE     0x3000
+#define HP_IOREMAP_SIZE 0x3000
 
 /* data type */
 typedef unsigned long long int u64;
@@ -42,7 +42,6 @@ typedef signed char s8;
 
 /* printk level */
 
-
 /*
  * The interface for communication among HOST, RISC-V and ZF drivers
  * is as follows...
@@ -59,94 +58,95 @@ typedef signed char s8;
  */
 
 /* Value that the zxdh_pkt_chan_msg_send() can be returned */
-#define MSG_CHAN_RET_OK                       0
-#define MSG_CHAN_RET_ERR_NULL_PTR             (-1)
-#define MSG_CHAN_RET_ERR_INVALID_PARA         (-2)
-#define MSG_CHAN_RET_ERR_NO_ENOUGH_MEM        (-4)
-#define MSG_CHAN_RET_ERR_CHANNEL_NOT_READY    (-5)
-#define MSG_CHAN_RET_ERR_CHAN_BUSY            (-6)
-#define MSG_CHAN_RET_ERR_CHAN_BROKEN          (-7)
-#define MSG_CHAN_RET_ERR_XMIT_FAIL            (-8)
+#define MSG_CHAN_RET_OK 0
+#define MSG_CHAN_RET_ERR_NULL_PTR (-1)
+#define MSG_CHAN_RET_ERR_INVALID_PARA (-2)
+#define MSG_CHAN_RET_ERR_NO_ENOUGH_MEM (-4)
+#define MSG_CHAN_RET_ERR_CHANNEL_NOT_READY (-5)
+#define MSG_CHAN_RET_ERR_CHAN_BUSY (-6)
+#define MSG_CHAN_RET_ERR_CHAN_BROKEN (-7)
+#define MSG_CHAN_RET_ERR_XMIT_FAIL (-8)
 #define MSG_CHAN_RET_ERR_CALLBACK_OUT_OF_TIME (-9)
-#define MSG_CHAN_RET_ERR_NO_PRIV_QUEUE        (-10)
-#define MSG_CHAN_RET_ERR_CALLBACK_FAIL        (-11)
-#define MSG_CHAN_RET_ERR_FREEPAGE_FAIL        (-12)
+#define MSG_CHAN_RET_ERR_NO_PRIV_QUEUE (-10)
+#define MSG_CHAN_RET_ERR_CALLBACK_FAIL (-11)
+#define MSG_CHAN_RET_ERR_FREEPAGE_FAIL (-12)
 
 typedef enum {
-    TYPE_DEBUG = 0,
-    DST_RISCV,
-    DST_MPF,
-    DST_PF_OR_VF,
-    DST_ZF,
-    MSG_TYPE_NUM,
+	TYPE_DEBUG = 0,
+	DST_RISCV,
+	DST_MPF,
+	DST_PF_OR_VF,
+	DST_ZF,
+	MSG_TYPE_NUM,
 } MSG_TYPE;
 
 typedef enum BAR_DRIVER_TYPE {
-    MSG_CHAN_END_MPF = 0,
-    MSG_CHAN_END_PF,
-    MSG_CHAN_END_VF,
-    MSG_CHAN_END_RISC,
-    MSG_CHAN_END_ERR,
+	MSG_CHAN_END_MPF = 0,
+	MSG_CHAN_END_PF,
+	MSG_CHAN_END_VF,
+	MSG_CHAN_END_RISC,
+	MSG_CHAN_END_ERR,
 } BAR_DRIVER_TYPE;
 
-#define BDF_ECAM(bus, devid, func) ((bus & 0xff) << 8) | (func & 0x07) | ((devid & 0x1f) << 3)
+#define BDF_ECAM(bus, devid, func) \
+	(((bus & 0xff) << 8) | (func & 0x07) | ((devid & 0x1f) << 3))
 
 /* bar通道错误码 */
 typedef enum BAR_MSG_RTN {
-    BAR_MSG_OK = 0,
-    BAR_MSG_ERR_NULL,            /* < 空指针 > */
-    BAR_MSG_ERR_TYPE,            /* < 消息类型异常 > */
-    BAR_MSG_ERR_MODULE,          /* < 模块ID异常 > */
-    BAR_MSG_ERR_BODY_NULL,       /* < 消息体异常 > */
-    BAR_MSG_ERR_LEN,             /* < 消息长度异常 > */
-    BAR_MSG_ERR_TIME_OUT,        /* < 消息超时 > */
-    BAR_MSG_ERR_NOT_READY,       /* < 消息发送条件异常，BUF不可以用> */
-    BAR_MEG_ERR_NULL_FUNC,       /* < 空的接收处理函数指针> */
-    BAR_MSG_ERR_REPEAT_REGISTER, /* < 模块重复注册> */
-    BAR_MSG_ERR_UNGISTER,        /* < 重复解注册> */
-    BAR_MSG_ERR_NULL_PARA,       /* < 参数空指针> */
-    BAR_MSG_ERR_REPSBUFF_LEN,    /* < reps_buff长度异常> */
-    BAR_MSG_ERR_MODULE_NOEXIST,  /* < 查找不到该模块对应的消息处理函数> */
-    BAR_MSG_ERR_VIRTADDR_NULL,   /* < 发送接口传入参数中的虚拟地址为空> */
-    BAR_MSG_ERR_REPLY,           /* < seq_id匹配失败> */
-    BAR_MSG_ERR_MSGID,           /* < seq_id申请失败> */
-    BAR_MSG_ERR_MPF_NOT_SCANED,  /* < MPF通道不可用> */
-    BAR_MSG_ERR_USR_RET_ERR,     /* < 处理函数返回值错误> */
-    BAR_MSG_ERR_ERR_PCIEID,      /* < pcieID错误> */
-    BAR_MSG_ERR_NOT_MATCH,
+	BAR_MSG_OK = 0,
+	BAR_MSG_ERR_NULL, /* < 空指针 > */
+	BAR_MSG_ERR_TYPE, /* < 消息类型异常 > */
+	BAR_MSG_ERR_MODULE, /* < 模块ID异常 > */
+	BAR_MSG_ERR_BODY_NULL, /* < 消息体异常 > */
+	BAR_MSG_ERR_LEN, /* < 消息长度异常 > */
+	BAR_MSG_ERR_TIME_OUT, /* < 消息超时 > */
+	BAR_MSG_ERR_NOT_READY, /* < 消息发送条件异常，BUF不可以用> */
+	BAR_MEG_ERR_NULL_FUNC, /* < 空的接收处理函数指针> */
+	BAR_MSG_ERR_REPEAT_REGISTER, /* < 模块重复注册> */
+	BAR_MSG_ERR_UNGISTER, /* < 重复解注册> */
+	BAR_MSG_ERR_NULL_PARA, /* < 参数空指针> */
+	BAR_MSG_ERR_REPSBUFF_LEN, /* < reps_buff长度异常> */
+	BAR_MSG_ERR_MODULE_NOEXIST, /* < 查找不到该模块对应的消息处理函数> */
+	BAR_MSG_ERR_VIRTADDR_NULL, /* < 发送接口传入参数中的虚拟地址为空> */
+	BAR_MSG_ERR_REPLY, /* < seq_id匹配失败> */
+	BAR_MSG_ERR_MSGID, /* < seq_id申请失败> */
+	BAR_MSG_ERR_MPF_NOT_SCANED, /* < MPF通道不可用> */
+	BAR_MSG_ERR_USR_RET_ERR, /* < 处理函数返回值错误> */
+	BAR_MSG_ERR_ERR_PCIEID, /* < pcieID错误> */
+	BAR_MSG_ERR_NOT_MATCH,
 } BAR_MSG_RTN;
 
-
-
 /* msix消息参数结构体 */
 struct msix_para {
-    u16 vector_risc;
-    u16 vector_pfvf;
-    u16 vector_mpf;
-    u16 driver_type;
-    struct pci_dev *pdev;
-    u64 virt_addr;
+	u16 vector_risc;
+	u16 vector_pfvf;
+	u16 vector_mpf;
+	u16 driver_type;
+	struct pci_dev *pdev;
+	u64 virt_addr;
 };
 
 struct zxdh_pci_bar_msg {
-    u64 virt_addr;      /* < 4k空间地址, 若src为MPF该参数不生效> */
-    void *payload_addr; /* < 消息净荷地址> */
-    u16 payload_len;    /* < 消息净荷长度> */
-    u16 emec;           /* < 消息紧急类型> */
-    u16 src;            /* < 消息发送源，参考BAR_DRIVER_TYPE> */
-    u16 dst;            /* < 消息接收者，参考BAR_DRIVER_TYPE> */
-    u32 event_id;       /* < 事件id> */
-    u16 src_pcieid;     /* < 源  pcie_id> */
-    u16 dst_pcieid;     /* < 目的pcie_id> */
+	u64 virt_addr; /* < 4k空间地址, 若src为MPF该参数不生效> */
+	void *payload_addr; /* < 消息净荷地址> */
+	u16 payload_len; /* < 消息净荷长度> */
+	u16 emec; /* < 消息紧急类型> */
+	u16 src; /* < 消息发送源，参考BAR_DRIVER_TYPE> */
+	u16 dst; /* < 消息接收者，参考BAR_DRIVER_TYPE> */
+	u32 event_id; /* < 事件id> */
+	u16 src_pcieid; /* < 源  pcie_id> */
+	u16 dst_pcieid; /* < 目的pcie_id> */
 };
 
 struct zxdh_msg_recviver_mem {
-    void *recv_buffer; /* < 消息接收缓存> */
-    u16 buffer_len;    /* < 消息缓存长度> */
+	void *recv_buffer; /* < 消息接收缓存> */
+	u16 buffer_len; /* < 消息缓存长度> */
 };
 
 /* 消息处理函数，payload和len表示来的消息 */
-typedef int (*zxdh_bar_chan_msg_recv_callback)(void *pay_load, u16 len, void *reps_buffer, u16 *reps_len, void *dev);
+typedef int (*zxdh_bar_chan_msg_recv_callback)(void *pay_load, u16 len,
+											   void *reps_buffer, u16 *reps_len,
+											   void *dev);
 
 /*
  * zxdh_bar_chan_sync_msg_send - 通过PCIE BAR空间发送同步消息
@@ -154,9 +154,20 @@ typedef int (*zxdh_bar_chan_msg_recv_callback)(void *pay_load, u16 len, void *re
  * @result: 消息结果反馈
  * @return: 0 成功，其他失败
  */
-int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in, struct zxdh_msg_recviver_mem *result);
+int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in,
+								struct zxdh_msg_recviver_mem *result);
+
+/*
+ * zxdh_bar_chan_async_msg_send - 通过PCIE BAR空间发送异步消息
+ * @in: 消息发送信息
+ * @result: 消息结果反馈
+ * @return: 0 成功，其他失败
+ */
+int zxdh_bar_chan_async_msg_send(struct zxdh_pci_bar_msg *in,
+								 struct zxdh_msg_recviver_mem *result);
 
-int pcie_mt_send_msg(void *msg_info, u32 msg_size, void *resp_msg, u32 resp_size);
+int pcie_mt_send_msg(void *msg_info, u32 msg_size, void *resp_msg,
+					 u32 resp_size);
 
 #ifdef __cplusplus
 }
diff --git a/src/net/drivers/pcie/zxdh_pcie/function_hotplug.c b/src/net/drivers/pcie/zxdh_pcie/function_hotplug.c
index e7dbe254b5ba719d1d138a7944c0441c02c5a43b..908620213120dcfdef1f80d09d7b1297acdb3e0e 100644
--- a/src/net/drivers/pcie/zxdh_pcie/function_hotplug.c
+++ b/src/net/drivers/pcie/zxdh_pcie/function_hotplug.c
@@ -9,453 +9,422 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/uaccess.h>
-
 #include "bar_msg.h"
 #include "function_hotplug.h"
 #include "pcie_common.h"
 
 extern int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
 
-char bind_type_name[FUNCTION_HP_TYPE_COUNT][FILE_PATH_LEN] = {"unbind", "bind"};
+char bind_type_name[FUNCTION_HP_TYPE_COUNT][FILE_PATH_LEN] = { "unbind",
+															   "bind" };
 
 static struct zte_dpu_id_info zte_dpu_id_info[] = {
-    /*    name,        device_id, vendor_id,*/
-    {"virtio_blk",        0x1001, 0x1af4},
-    {"nvme",              0x8053, 0x1cf2},
+	/*    name,        device_id, vendor_id,*/
+	{ "virtio_blk", 0x1001, 0x1af4 },
+	{ "nvme", 0x8053, 0x1cf2 },
 };
 
-int init_pf_hotplug_info()
+int init_pf_hotplug_info(void)
 {
-    // pf_hotplug_info.cmd = 11; // TODO
+	// pf_hotplug_info.cmd = 11; // TODO
 
-    return 0;
+	return 0;
 }
 
 int remove_pci_dev(struct func_hotplug_req *hp_req)
 {
-    int ret = PCIE_SUCCESS;
-    struct pci_dev *pdev = NULL;
+	int ret = PCIE_SUCCESS;
+	struct pci_dev *pdev = NULL;
 
-    DH_LOG_DEBUG(MODULE_FUC_HP,"domain=0x%x, bdf=0x%x\n", hp_req->domain, hp_req->bdf);
-    pdev = zxdh_get_pci_device(hp_req->domain, hp_req->bdf);
-    if (!pdev)
-    {
-        DH_LOG_DEBUG(MODULE_FUC_HP, "This device has removed\n");
-        goto finish;
-    }
+	DH_LOG_DEBUG(MODULE_FUC_HP, "domain=0x%x, bdf=0x%x\n", hp_req->domain,
+				 hp_req->bdf);
+	pdev = zxdh_get_pci_device(hp_req->domain, hp_req->bdf);
+	if (!pdev) {
+		DH_LOG_DEBUG(MODULE_FUC_HP, "This device has removed\n");
+		goto finish;
+	}
 
-    pci_sriov_configure_simple(pdev, 0);
+	pci_sriov_configure_simple(pdev, 0);
 
-    pci_stop_and_remove_bus_device_locked(pdev);
+	pci_stop_and_remove_bus_device_locked(pdev);
 
-    pdev = zxdh_get_pci_device(hp_req->domain, hp_req->bdf);
-    if (pdev)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "remove fail! domain=0x%x, bdf=0x%x\n", hp_req->domain, hp_req->bdf);
-        ret = PCIE_FAILED;
-    }
+	pdev = zxdh_get_pci_device(hp_req->domain, hp_req->bdf);
+	if (pdev) {
+		DH_LOG_ERR(MODULE_FUC_HP, "remove fail! domain=0x%x, bdf=0x%x\n",
+				   hp_req->domain, hp_req->bdf);
+		ret = PCIE_FAILED;
+	}
 
 finish:
-    return ret;
+	return ret;
 }
 
 int all_ep_rescan(void)
 {
-    int ret = PCIE_SUCCESS;
-    int size = 0;
-    struct file *filp = NULL;
-    char filename[FILE_PATH_LEN]  = {0};
-    char date = '1';
-
-    size = snprintf(filename, FILE_PATH_LEN, "%s/%s", SYS_BUS_PCI_DIR, "rescan");
-    if (size >= sizeof(filename))
-    {
-        filename[sizeof(filename) - 1] = '\0';
-    }
-    DH_LOG_INFO(MODULE_FUC_HP, "filename=%s\n", filename);
-
-    filp = filp_open(filename, O_WRONLY, 0);
-    if (IS_ERR(filp))
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "open file error\n");
-        return PCIE_FAILED;
-    }
-
-    kernel_write(filp, &date, sizeof(char), &filp->f_pos);
-    filp_close(filp, NULL);
-
-    return ret;
+	int ret = PCIE_SUCCESS;
+	struct file *filp = NULL;
+	char filename[FILE_PATH_LEN] = { 0 };
+	char date = '1';
+
+	snprintf(filename, FILE_PATH_LEN, "%s/%s", SYS_BUS_PCI_DIR, "rescan");
+	DH_LOG_INFO(MODULE_FUC_HP, "filename=%s\n", filename);
+
+	filp = filp_open(filename, O_WRONLY, 0);
+	if (IS_ERR(filp)) {
+		DH_LOG_ERR(MODULE_FUC_HP, "open file error\n");
+		return PCIE_FAILED;
+	}
+
+	kernel_write(filp, &date, sizeof(char), &filp->f_pos);
+	filp_close(filp, NULL);
+
+	return ret;
 }
 
 int rescan_pci_dev(struct func_hotplug_req *hp_req)
 {
-    int ret = PCIE_SUCCESS;
-    struct pci_dev *pdev = NULL;
-
-    DH_LOG_DEBUG(MODULE_FUC_HP, "domain=0x%x, rescan bdf=0x%x\n", hp_req->domain, hp_req->bdf);
-    hp_req->bdf = hp_req->bdf & (~BDF_NO_FUNC_NO_MASK);
-    DH_LOG_DEBUG(MODULE_FUC_HP, "domain=0x%x, bdf=0x%x\n", hp_req->domain, hp_req->bdf);
-
-    pdev = zxdh_get_pci_device(hp_req->domain, hp_req->bdf);
-    if (!pdev)
-    {
-        all_ep_rescan();
-    }
-    else
-    {
-        pci_rescan_bus(pdev->bus);
-    }
-
-    init_pf_state();
-
-    return ret;
+	int ret = PCIE_SUCCESS;
+	struct pci_dev *pdev = NULL;
+
+	DH_LOG_DEBUG(MODULE_FUC_HP, "domain=0x%x, rescan bdf=0x%x\n",
+				 hp_req->domain, hp_req->bdf);
+	hp_req->bdf = hp_req->bdf & (~BDF_NO_FUNC_NO_MASK);
+	DH_LOG_DEBUG(MODULE_FUC_HP, "domain=0x%x, bdf=0x%x\n", hp_req->domain,
+				 hp_req->bdf);
+
+	pdev = zxdh_get_pci_device(hp_req->domain, hp_req->bdf);
+	if (!pdev) {
+		all_ep_rescan();
+	} else {
+		pci_rescan_bus(pdev->bus);
+	}
+
+	init_pf_state();
+
+	return ret;
 }
 
 int vf_bind_unbind(struct func_hotplug_req *hp_req)
 {
-    int ret = PCIE_SUCCESS;
-    int size = 0;
-    struct file *filp = NULL;
-    char filename[FILE_PATH_LEN]  = {0};
-    char bdf[FILE_PATH_LEN] = {0};
-    unsigned int scene_code = 0;
-    u32 bus_no = 0;
-    u32 device_no = 0;
-    u32 func_no = 0;
-
-    memset(filename, 0, FILE_PATH_LEN);
-
-    scene_code = SCENE_CODE_OF_FUNC_HP_INFO(hp_req->hotplug_info);
-    bus_no = (hp_req->bdf & BDF_NO_BUS_NO_MASK) >> BDF_B_START_BIT;
-    device_no = (hp_req->bdf & BDF_NO_DEV_NO_MASK) >> BDF_D_START_BIT;
-    func_no = (hp_req->bdf & BDF_NO_FUNC_NO_MASK) >> BDF_F_START_BIT;
-    size = snprintf(bdf, FILE_PATH_LEN, "%x:%x:%x.%x", hp_req->domain, bus_no, device_no, func_no);
-    if (size >= sizeof(bdf))
-    {
-        bdf[sizeof(bdf) - 1] = '\0';
-    }
-    DH_LOG_INFO(MODULE_FUC_HP, "scene_code=%d, bind_type_name=%s, bdf=%s\n", scene_code, bind_type_name[scene_code - FUNCTION_REMOVE], bdf);
-
-    ret = parse_bdf(bdf);
-    if (ret != PCIE_SUCCESS)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "%s: parse bdf fail\n", __func__);
-        return PCIE_FAILED;
-    }
-
-    size = snprintf(filename, FILE_PATH_LEN, "%s/%s/%s/%s", PCI_DEVICES_DIR, bdf, PCI_PHYSFN_DRV_PATH, bind_type_name[scene_code - FUNCTION_REMOVE]);
-    if (size >= sizeof(filename))
-    {
-        filename[sizeof(filename) - 1] = '\0';
-    }
-    DH_LOG_INFO(MODULE_FUC_HP, "filename=%s\n", filename);
-
-    filp = filp_open(filename, O_WRONLY, 0);
-    if (IS_ERR(filp))
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "open file error\n");
-        return PCIE_FAILED;
-    }
-
-    kernel_write(filp, (unsigned char*)bdf, sizeof(bdf), &filp->f_pos);
-    filp_close(filp, NULL);
-
-    return ret;
+	int ret = PCIE_SUCCESS;
+	struct file *filp = NULL;
+	char filename[FILE_PATH_LEN] = { 0 };
+	char bdf[FILE_PATH_LEN] = { 0 };
+	unsigned int scene_code = 0;
+	u32 bus_no = 0;
+	u32 device_no = 0;
+	u32 func_no = 0;
+
+	memset(filename, 0, FILE_PATH_LEN);
+
+	scene_code = SCENE_CODE_OF_FUNC_HP_INFO(hp_req->hotplug_info);
+	bus_no = (hp_req->bdf & BDF_NO_BUS_NO_MASK) >> BDF_B_START_BIT;
+	device_no = (hp_req->bdf & BDF_NO_DEV_NO_MASK) >> BDF_D_START_BIT;
+	func_no = (hp_req->bdf & BDF_NO_FUNC_NO_MASK) >> BDF_F_START_BIT;
+	snprintf(bdf, FILE_PATH_LEN, "%x:%x:%x.%x", hp_req->domain, bus_no,
+			 device_no, func_no);
+	DH_LOG_INFO(MODULE_FUC_HP, "scene_code=%d, bind_type_name=%s, bdf=%s\n",
+				scene_code, bind_type_name[scene_code - FUNCTION_REMOVE], bdf);
+
+	ret = parse_bdf(bdf);
+	if (ret != PCIE_SUCCESS) {
+		DH_LOG_ERR(MODULE_FUC_HP, "%s: parse bdf fail\n", __func__);
+		return PCIE_FAILED;
+	}
+
+	snprintf(filename, FILE_PATH_LEN, "%s/%s/%s/%s", PCI_DEVICES_DIR, bdf,
+			 PCI_PHYSFN_DRV_PATH, bind_type_name[scene_code - FUNCTION_REMOVE]);
+	DH_LOG_INFO(MODULE_FUC_HP, "filename=%s\n", filename);
+
+	filp = filp_open(filename, O_WRONLY, 0);
+	if (IS_ERR(filp)) {
+		DH_LOG_ERR(MODULE_FUC_HP, "open file error\n");
+		return PCIE_FAILED;
+	}
+
+	kernel_write(filp, (unsigned char *)bdf, sizeof(bdf), &filp->f_pos);
+	filp_close(filp, NULL);
+
+	return ret;
 }
 
 static void print_func_hotplug_req(struct func_hotplug_req *func_hp_req)
 {
-    DH_LOG_DEBUG(MODULE_FUC_HP, "scene_code=0x%x, function_type=0x%x, ep_id=0x%x, pf_id=0x%x, vf_id=0x%x, domain=0x%x, bdf=0x%x\n",
-        SCENE_CODE_OF_FUNC_HP_INFO(func_hp_req->hotplug_info), FUNC_TYPE_OF_FUNC_HP_INFO(func_hp_req->hotplug_info),
-        EP_ID_OF_FUNC_HP_INFO(func_hp_req->hotplug_info), PF_ID_OF_FUNC_HP_INFO(func_hp_req->hotplug_info),
-        VF_ID_OF_FUNC_HP_INFO(func_hp_req->hotplug_info), func_hp_req->domain, func_hp_req->bdf);
+	DH_LOG_DEBUG(MODULE_FUC_HP,
+				 "scene_code=0x%x, function_type=0x%x, ep_id=0x%x, pf_id=0x%x, "
+				 "vf_id=0x%x, domain=0x%x, bdf=0x%x\n",
+				 SCENE_CODE_OF_FUNC_HP_INFO(func_hp_req->hotplug_info),
+				 FUNC_TYPE_OF_FUNC_HP_INFO(func_hp_req->hotplug_info),
+				 EP_ID_OF_FUNC_HP_INFO(func_hp_req->hotplug_info),
+				 PF_ID_OF_FUNC_HP_INFO(func_hp_req->hotplug_info),
+				 VF_ID_OF_FUNC_HP_INFO(func_hp_req->hotplug_info),
+				 func_hp_req->domain, func_hp_req->bdf);
 }
 
-static void func_hp_info_decode(struct func_hotplug_req *hp_req, struct func_hotplug_info *hp_info)
+static void func_hp_info_decode(struct func_hotplug_req *hp_req,
+								struct func_hotplug_info *hp_info)
 {
-    hp_info->scene_code = SCENE_CODE_OF_FUNC_HP_INFO(hp_req->hotplug_info);
-    hp_info->function_type = FUNC_TYPE_OF_FUNC_HP_INFO(hp_req->hotplug_info);
-    hp_info->ep_id = EP_ID_OF_FUNC_HP_INFO(hp_req->hotplug_info);
-    hp_info->pf_id = PF_ID_OF_FUNC_HP_INFO(hp_req->hotplug_info);
-    hp_info->vf_id = VF_ID_OF_FUNC_HP_INFO(hp_req->hotplug_info);
-    DH_LOG_DEBUG(MODULE_FUC_HP, "scene_code=0x%x, function_type=0x%x, ep_id=0x%x, pf_id=0x%x, vf_id=0x%x, hotplug_info=0x%x\n",
-        hp_info->scene_code, hp_info->function_type,
-        hp_info->ep_id, hp_info->pf_id,
-        hp_info->vf_id, hp_req->hotplug_info);
+	hp_info->scene_code = SCENE_CODE_OF_FUNC_HP_INFO(hp_req->hotplug_info);
+	hp_info->function_type = FUNC_TYPE_OF_FUNC_HP_INFO(hp_req->hotplug_info);
+	hp_info->ep_id = EP_ID_OF_FUNC_HP_INFO(hp_req->hotplug_info);
+	hp_info->pf_id = PF_ID_OF_FUNC_HP_INFO(hp_req->hotplug_info);
+	hp_info->vf_id = VF_ID_OF_FUNC_HP_INFO(hp_req->hotplug_info);
+	DH_LOG_DEBUG(MODULE_FUC_HP,
+				 "scene_code=0x%x, function_type=0x%x, ep_id=0x%x, pf_id=0x%x, "
+				 "vf_id=0x%x, hotplug_info=0x%x\n",
+				 hp_info->scene_code, hp_info->function_type, hp_info->ep_id,
+				 hp_info->pf_id, hp_info->vf_id, hp_req->hotplug_info);
 }
 
-static int func_remove(unsigned int function_type, struct func_hotplug_req *hp_req)
+static int func_remove(unsigned int function_type,
+					   struct func_hotplug_req *hp_req)
 {
-    int ret = PCIE_SUCCESS;
-
-    if (function_type == PCIE_FUNC_TYPE_PF)
-    {
-        ret = init_pf_state();
-    }
-    else if (function_type == PCIE_FUNC_TYPE_VF)
-    {
-        ret = vf_bind_unbind(hp_req);
-    }
-    else
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "error function_type=0x%x\n", function_type);
-        ret = PCIE_FAILED;
-    }
-
-    return ret;
+	int ret = PCIE_SUCCESS;
+
+	if (function_type == PCIE_FUNC_TYPE_PF) {
+		ret = init_pf_state();
+	} else if (function_type == PCIE_FUNC_TYPE_VF) {
+		ret = vf_bind_unbind(hp_req);
+	} else {
+		DH_LOG_ERR(MODULE_FUC_HP, "error function_type=0x%x\n", function_type);
+		ret = PCIE_FAILED;
+	}
+
+	return ret;
 }
 
-static int func_insert(unsigned int function_type, struct func_hotplug_req *hp_req)
+static int func_insert(unsigned int function_type,
+					   struct func_hotplug_req *hp_req)
 {
-    int ret = PCIE_SUCCESS;
-
-    if (function_type == PCIE_FUNC_TYPE_PF)
-    {
-        ret = rescan_pci_dev(hp_req);
-    }
-    else if (function_type == PCIE_FUNC_TYPE_VF)
-    {
-        ret = vf_bind_unbind(hp_req);
-    }
-    else
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "error function_type=0x%x\n", function_type);
-        ret = PCIE_FAILED;
-    }
-
-    return ret;
+	int ret = PCIE_SUCCESS;
+
+	if (function_type == PCIE_FUNC_TYPE_PF) {
+		ret = rescan_pci_dev(hp_req);
+	} else if (function_type == PCIE_FUNC_TYPE_VF) {
+		ret = vf_bind_unbind(hp_req);
+	} else {
+		DH_LOG_ERR(MODULE_FUC_HP, "error function_type=0x%x\n", function_type);
+		ret = PCIE_FAILED;
+	}
+
+	return ret;
 }
 
 int func_hp(void)
 {
-    int ret = PCIE_SUCCESS;
-    struct pci_dev *hp_pdev = NULL;
-    struct func_hotplug_req hp_req = {0};
-    struct func_hotplug_result hp_result = {0};
-    struct func_hotplug_info hp_info = {0};
-    void __iomem *bar_virt_addr = NULL;
-    u64 bar_addr = 0;
-    int resp_msg = 0;
-
-    hp_pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, NULL);
-    if (IS_ERR_OR_NULL(hp_pdev))
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "This hp device was not found. Please confirm the BDF\n");
-        return PCIE_FAILED;
-    }
-
-    bar_addr = pci_resource_start(hp_pdev, 0);
-    bar_virt_addr = (void __iomem *)ioremap(bar_addr, HP_IOREMAP_SIZE);
-    if (bar_virt_addr == NULL)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "bar_virt_addr map failed\n");
-        return PCIE_FAILED;
-    }
-
-    memcpy(&hp_req, bar_virt_addr, sizeof(struct func_hotplug_req));
-    func_hp_info_decode(&hp_req, &hp_info);
-    print_func_hotplug_req(&hp_req);
-
-    switch (hp_info.scene_code)
-    {
-        case FUNCTION_REMOVE:
-        {
-            ret = func_remove(hp_info.function_type, &hp_req);
-            break;
-        }
-        case FUNCTION_INSERT:
-        {
-            ret = func_insert(hp_info.function_type, &hp_req);
-            break;
-        }
-        default:
-        {
-            DH_LOG_ERR(MODULE_FUC_HP, "error scene_code=0x%x\n", hp_info.scene_code);
-            ret = PCIE_FAILED;
-        }
-    }
-
-    hp_result.cmd = PCIE_HOTPLUG_FINISH;
-    hp_result.hotplug_info = hp_req.hotplug_info;
-    hp_result.result = (ret == PCIE_SUCCESS) ? FUNC_HP_RESULT_SUCC : FUNC_HP_RESULT_FAIL;
-
-    ret = pcie_mt_send_msg(&hp_result, sizeof(struct func_hotplug_result), &resp_msg, sizeof(int));
-    if (ret)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "send failed\n");
-    }
-
-    iounmap(bar_virt_addr);
-    bar_virt_addr = NULL;
-    return ret;
+	int ret = PCIE_SUCCESS;
+	struct pci_dev *hp_pdev = NULL;
+	struct func_hotplug_req hp_req = { 0 };
+	struct func_hotplug_result hp_result = { 0 };
+	struct func_hotplug_info hp_info = { 0 };
+	void __iomem *bar_virt_addr = NULL;
+	u64 bar_addr = 0;
+	int resp_msg = 0;
+
+	hp_pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, NULL);
+	if (!hp_pdev) {
+		DH_LOG_ERR(MODULE_FUC_HP,
+				   "This hp device was not found. Please confirm the BDF\n");
+		return PCIE_FAILED;
+	}
+
+	bar_addr = pci_resource_start(hp_pdev, 0);
+	bar_virt_addr = ioremap(bar_addr, HP_IOREMAP_SIZE);
+	memcpy(&hp_req, bar_virt_addr, sizeof(struct func_hotplug_req));
+	func_hp_info_decode(&hp_req, &hp_info);
+	print_func_hotplug_req(&hp_req);
+
+	switch (hp_info.scene_code) {
+	case FUNCTION_REMOVE: {
+		ret = func_remove(hp_info.function_type, &hp_req);
+		break;
+	}
+	case FUNCTION_INSERT: {
+		ret = func_insert(hp_info.function_type, &hp_req);
+		break;
+	}
+	default: {
+		DH_LOG_ERR(MODULE_FUC_HP, "error scene_code=0x%x\n",
+				   hp_info.scene_code);
+		ret = PCIE_FAILED;
+	}
+	}
+
+	hp_result.cmd = PCIE_HOTPLUG_FINISH;
+	hp_result.hotplug_info = hp_req.hotplug_info;
+	hp_result.result = (ret == PCIE_SUCCESS) ? FUNC_HP_RESULT_SUCC :
+												 FUNC_HP_RESULT_FAIL;
+
+	ret = pcie_mt_send_msg(&hp_result, sizeof(struct func_hotplug_result),
+						   &resp_msg, sizeof(int));
+	if (ret) {
+		DH_LOG_ERR(MODULE_FUC_HP, "send failed\n");
+	}
+
+	iounmap(bar_virt_addr);
+	bar_virt_addr = NULL;
+	return ret;
 }
 
 int enable_vf(void)
 {
-    int pos = 0;
-    u16 total_vf_nums = 0;
-    int ret = PCIE_SUCCESS;
-    struct pci_dev *dev = NULL;
-    int i = 0;
-    int entry_num = sizeof(zte_dpu_id_info) / sizeof(struct zte_dpu_id_info);
-
-    for(i = 0; i < entry_num; i++)
-    {
-        while ((dev = pci_get_device(zte_dpu_id_info[i].vendor_id, zte_dpu_id_info[i].device_id, dev)) != NULL)
-        {
-            pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
-            if (!pos)
-            {
-                continue;
-            }
-            pci_read_config_word(dev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_nums);
-            DH_LOG_DEBUG(MODULE_FUC_HP, "Total VFs: %d  ", total_vf_nums);
-            pci_sriov_configure_simple(dev, total_vf_nums);
-        }
-    }
-
-    return ret;
+	int pos = 0;
+	u16 total_vf_nums = 0;
+	int ret = PCIE_SUCCESS;
+	struct pci_dev *dev = NULL;
+	int i = 0;
+	int entry_num = sizeof(zte_dpu_id_info) / sizeof(struct zte_dpu_id_info);
+
+	for (i = 0; i < entry_num; i++) {
+		while ((dev = pci_get_device(zte_dpu_id_info[i].vendor_id,
+									 zte_dpu_id_info[i].device_id, dev)) !=
+			   NULL) {
+			pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
+			if (!pos) {
+				continue;
+			}
+			pci_read_config_word(dev, (pos + PCI_SRIOV_TOTAL_VF),
+								 &total_vf_nums);
+			DH_LOG_DEBUG(MODULE_FUC_HP, "Total VFs: %d  ", total_vf_nums);
+			pci_sriov_configure_simple(dev, total_vf_nums);
+		}
+	}
+
+	return ret;
 }
 
 int init_bdf(void)
 {
-    int ret = PCIE_SUCCESS;
-    int resp_msg = 0;
-    struct fuc_hotplug_bar_msg fuc_hotplug_bar_msg = {0};
-
-    fuc_hotplug_bar_msg.cmd = PCIE_HOTPLUG_START;
-    fuc_hotplug_bar_msg.fuc_hotplug_info = FUC_HOTPLUG_PF_INIT_FLAG;
-
-    ret = hotplug_device_enable(1);
-    if (ret != 0)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "enable hotplug device failed.\n");
-        return ret;
-    }
-
-    ret = pcie_mt_send_msg(&fuc_hotplug_bar_msg, sizeof(struct fuc_hotplug_bar_msg), &resp_msg, sizeof(int));
-    if (ret != 0)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "get dbf failed\n");
-    }
-
-    return PCIE_SUCCESS;
+	int ret = PCIE_SUCCESS;
+	int resp_msg = 0;
+	struct fuc_hotplug_bar_msg fuc_hotplug_bar_msg = { 0 };
+
+	fuc_hotplug_bar_msg.cmd = PCIE_HOTPLUG_START;
+	fuc_hotplug_bar_msg.fuc_hotplug_info = FUC_HOTPLUG_PF_INIT_FLAG;
+
+	ret = hotplug_device_enable(1);
+	if (ret != 0) {
+		DH_LOG_ERR(MODULE_FUC_HP, "enable hotplug device failed.\n");
+		return ret;
+	}
+
+	ret = pcie_mt_send_msg(&fuc_hotplug_bar_msg,
+						   sizeof(struct fuc_hotplug_bar_msg), &resp_msg,
+						   sizeof(int));
+	if (ret != 0) {
+		DH_LOG_ERR(MODULE_FUC_HP, "get dbf failed\n");
+	}
+
+	return PCIE_SUCCESS;
 }
 
 int init_pf_state(void)
 {
-    u64 bar_addr = 0;
-    u8 ep_no = 0;
-    u8 pf_no = 0;
-    u32 mask_idx = 0;
-    struct func_hotplug_req hp_req = {0};
-    struct func_hotplug_info hp_info = {0};
-    struct func_hotplug_state func_hotplug_state = {0};
-    u32 pf_state_mask = 0;
-    struct pci_dev *hp_pdev = NULL;
-    void __iomem *bar_virt_addr = NULL;
-
-    hp_pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, NULL);
-    if (IS_ERR_OR_NULL(hp_pdev))
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "This hp device was not found. Please confirm the BDF\n");
-        return PCIE_FAILED;
-    }
-
-    bar_addr = pci_resource_start(hp_pdev, 0);
-    bar_virt_addr = (void __iomem *)ioremap(bar_addr, HP_IOREMAP_SIZE);
-    if (bar_virt_addr == NULL)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "bar_virt_addr map failed\n");
-        return -ENOMEM;
-    }
-
-    // 获取当前操作的pf
-    memcpy(&hp_req, bar_virt_addr, sizeof(struct func_hotplug_req));
-    func_hp_info_decode(&hp_req, &hp_info);
-
-    memcpy(&func_hotplug_state, bar_virt_addr + FUC_HOTPLUG_PF_STATE_FLAG_OFFSET, sizeof(struct func_hotplug_state));
-
-    pf_state_mask = func_hotplug_state.pf_state_mask | 0x1;
-
-    for (mask_idx = 0; mask_idx < MAX_PF_NUMS; mask_idx++)
-    {
-        ep_no = mask_idx / MAX_PF_NUMS_OF_EP;
-        pf_no = mask_idx % MAX_PF_NUMS_OF_EP;
-        hp_req.domain = func_hotplug_state.domain[ep_no];
-        hp_req.bdf = func_hotplug_state.bdf[ep_no];
-        hp_req.bdf = hp_req.bdf + pf_no;
-        if (!((pf_state_mask >> mask_idx)& 0x1))
-        {
-            // 修改当前操作的pf状态，恢复其它pf的状态
-            if (hp_info.scene_code == FUNCTION_INSERT
-               && hp_info.function_type == PCIE_FUNC_TYPE_PF
-               && (hp_info.ep_id - 5) == ep_no
-               && hp_info.pf_id == pf_no)
-            {
-                continue;
-            }
-            remove_pci_dev(&hp_req);
-            DH_LOG_DEBUG(MODULE_FUC_HP, "domain: %x", hp_req.domain);
-            DH_LOG_DEBUG(MODULE_FUC_HP, "bdf: %x", hp_req.bdf);
-        }
-    }
-
-    iounmap(bar_virt_addr);
-    bar_virt_addr = NULL;
-    return PCIE_SUCCESS;
+	u64 bar_addr = 0;
+	u8 ep_no = 0;
+	u8 pf_no = 0;
+	u32 mask_idx = 0;
+	struct func_hotplug_req hp_req = { 0 };
+	struct func_hotplug_info hp_info = { 0 };
+	struct func_hotplug_state func_hotplug_state = { 0 };
+	u32 pf_state_mask = 0;
+	struct pci_dev *hp_pdev = NULL;
+	void __iomem *bar_virt_addr = NULL;
+
+	hp_pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, NULL);
+	if (!hp_pdev) {
+		DH_LOG_ERR(MODULE_FUC_HP,
+				   "This hp device was not found. Please confirm the BDF\n");
+		return PCIE_FAILED;
+	}
+
+	bar_addr = pci_resource_start(hp_pdev, 0);
+	bar_virt_addr = ioremap(bar_addr, HP_IOREMAP_SIZE);
+	if (bar_virt_addr == NULL) {
+		DH_LOG_ERR(MODULE_FUC_HP, "bar_virt_addr map failed\n");
+		return -ENOMEM;
+	}
+
+	// 获取当前操作的pf
+	memcpy(&hp_req, bar_virt_addr, sizeof(struct func_hotplug_req));
+	func_hp_info_decode(&hp_req, &hp_info);
+
+	memcpy(&func_hotplug_state,
+		   bar_virt_addr + FUC_HOTPLUG_PF_STATE_FLAG_OFFSET,
+		   sizeof(struct func_hotplug_state));
+
+	pf_state_mask = func_hotplug_state.pf_state_mask | 0x1;
+
+	for (mask_idx = 0; mask_idx < MAX_PF_NUMS; mask_idx++) {
+		ep_no = mask_idx / MAX_PF_NUMS_OF_EP;
+		pf_no = mask_idx % MAX_PF_NUMS_OF_EP;
+		hp_req.domain = func_hotplug_state.domain[ep_no];
+		hp_req.bdf = func_hotplug_state.bdf[ep_no];
+		hp_req.bdf = hp_req.bdf + pf_no;
+		if (!((pf_state_mask >> mask_idx) & 0x1)) {
+			// 修改当前操作的pf状态，恢复其它pf的状态
+			if (hp_info.scene_code == FUNCTION_INSERT &&
+				hp_info.function_type == PCIE_FUNC_TYPE_PF &&
+				(hp_info.ep_id - 5) == ep_no && hp_info.pf_id == pf_no) {
+				continue;
+			}
+			remove_pci_dev(&hp_req);
+			DH_LOG_DEBUG(MODULE_FUC_HP, "domain: %x", hp_req.domain);
+			DH_LOG_DEBUG(MODULE_FUC_HP, "bdf: %x", hp_req.bdf);
+		}
+	}
+
+	iounmap(bar_virt_addr);
+	bar_virt_addr = NULL;
+	return PCIE_SUCCESS;
 }
 
 int hotplug_device_enable(int enable_flag)
 {
-    int ret = PCIE_SUCCESS;
-    struct pci_dev *hp_pdev = NULL;
-
-    hp_pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, NULL);
-    if (IS_ERR_OR_NULL(hp_pdev))
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "This hp device was not found. Please confirm the BDF\n");
-        return PCIE_FAILED;
-    }
-
-    if (enable_flag == 1)
-    {
-        ret = pci_enable_device(hp_pdev);
-    }
-    else if (enable_flag == 0)
-    {
-        pci_disable_device(hp_pdev);
-    }
-    if (ret != 0)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "pci_enable_device failed: %d\n", ret);
-        return ret;
-    }
-
-    return ret;
+	int ret = PCIE_SUCCESS;
+	struct pci_dev *hp_pdev = NULL;
+
+	hp_pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, NULL);
+	if (!hp_pdev) {
+		DH_LOG_ERR(MODULE_FUC_HP,
+				   "This hp device was not found. Please confirm the BDF\n");
+		return PCIE_FAILED;
+	}
+
+	if (enable_flag == 1) {
+		ret = pci_enable_device(hp_pdev);
+	} else if (enable_flag == 0) {
+		pci_disable_device(hp_pdev);
+	}
+	if (ret != 0) {
+		DH_LOG_ERR(MODULE_FUC_HP, "pci_enable_device failed: %d\n", ret);
+		return ret;
+	}
+
+	return ret;
 }
 
 irqreturn_t func_hp_msix_handler(int irq_no, void *data)
 {
-    pr_info("irq[%d] has been triggered\n", irq_no);
+	pr_info("irq[%d] has been triggered\n", irq_no);
 
-    return IRQ_WAKE_THREAD;
+	return IRQ_WAKE_THREAD;
 }
 
 irqreturn_t irq_handler2(int irq_no, void *data)
 {
-    pr_info("irq[%d] has been triggered\n", irq_no);
+	pr_info("irq[%d] has been triggered\n", irq_no);
 
-    return IRQ_WAKE_THREAD;
+	return IRQ_WAKE_THREAD;
 }
 
 irqreturn_t func_hp_msix_thread(int irq, void *data)
 {
-    func_hp();
-    return IRQ_HANDLED;
+	func_hp();
+	return IRQ_HANDLED;
 }
 
 irqreturn_t irq_thread2(int irq, void *data)
 {
-    return IRQ_HANDLED;
+	return IRQ_HANDLED;
 }
diff --git a/src/net/drivers/pcie/zxdh_pcie/function_hotplug.h b/src/net/drivers/pcie/zxdh_pcie/function_hotplug.h
index 3040bf7e562a02be5890f197f516d07a630c9fc9..fa7106f5ae0954d83b22d67e08761554ab2a7450 100644
--- a/src/net/drivers/pcie/zxdh_pcie/function_hotplug.h
+++ b/src/net/drivers/pcie/zxdh_pcie/function_hotplug.h
@@ -10,104 +10,109 @@ extern "C" {
 #define FUNC_HP_RESULT_SUCC 1
 #define FUNC_HP_RESULT_FAIL 2
 
-#define FUNC_HP_SCENE_CODE_START_BIT                        21
-#define FUNC_HP_FUNC_TYPE_START_BIT                         20
-#define FUNC_HP_EP_ID_START_BIT                             16
-#define FUNC_HP_PF_ID_START_BIT                             12
-#define FUNC_HP_VF_ID_START_BIT                             0
-
-#define FUNC_HP_SCENE_CODE_MASK                             (0x7 << FUNC_HP_SCENE_CODE_START_BIT)
-#define FUNC_HP_FUNC_TYPE_MASK                              (0x1 << FUNC_HP_FUNC_TYPE_START_BIT)
-#define FUNC_HP_EP_ID_MASK                                  (0xF << FUNC_HP_EP_ID_START_BIT)
-#define FUNC_HP_PF_ID_MASK                                  (0xF << FUNC_HP_PF_ID_START_BIT)
-#define FUNC_HP_VF_ID_MASK                                  (0xFFF << FUNC_HP_VF_ID_START_BIT)
-
-#define SCENE_CODE_OF_FUNC_HP_INFO(hotplug_info)            ((hotplug_info & FUNC_HP_SCENE_CODE_MASK) >> FUNC_HP_SCENE_CODE_START_BIT)
-#define FUNC_TYPE_OF_FUNC_HP_INFO(hotplug_info)             ((hotplug_info & FUNC_HP_FUNC_TYPE_MASK) >> FUNC_HP_FUNC_TYPE_START_BIT)
-#define EP_ID_OF_FUNC_HP_INFO(hotplug_info)                 ((hotplug_info & FUNC_HP_EP_ID_MASK) >> FUNC_HP_EP_ID_START_BIT)
-#define PF_ID_OF_FUNC_HP_INFO(hotplug_info)                 ((hotplug_info & FUNC_HP_PF_ID_MASK) >> FUNC_HP_PF_ID_START_BIT)
-#define VF_ID_OF_FUNC_HP_INFO(hotplug_info)                 ((hotplug_info & FUNC_HP_VF_ID_MASK) >> FUNC_HP_VF_ID_START_BIT)
-
-#define FUNCTION_HP_TYPE_COUNT                              2
-#define MAX_EP_NUMS                                         4
-#define MAX_PF_NUMS_OF_EP                                   8
-#define MAX_PF_NUMS                                         (MAX_PF_NUMS_OF_EP * MAX_EP_NUMS)
-
-#define FUC_HOTPLUG_PF_INIT_FLAG_OFFSET                     0x10
-#define FUC_HOTPLUG_PF_STATE_FLAG_OFFSET                    0x20
-#define FUC_HOTPLUG_PF_INIT_FLAG                            0x450000
+#define FUNC_HP_SCENE_CODE_START_BIT 21
+#define FUNC_HP_FUNC_TYPE_START_BIT 20
+#define FUNC_HP_EP_ID_START_BIT 16
+#define FUNC_HP_PF_ID_START_BIT 12
+#define FUNC_HP_VF_ID_START_BIT 0
+
+#define FUNC_HP_SCENE_CODE_MASK (0x7 << FUNC_HP_SCENE_CODE_START_BIT)
+#define FUNC_HP_FUNC_TYPE_MASK (0x1 << FUNC_HP_FUNC_TYPE_START_BIT)
+#define FUNC_HP_EP_ID_MASK (0xF << FUNC_HP_EP_ID_START_BIT)
+#define FUNC_HP_PF_ID_MASK (0xF << FUNC_HP_PF_ID_START_BIT)
+#define FUNC_HP_VF_ID_MASK (0xFFF << FUNC_HP_VF_ID_START_BIT)
+
+#define SCENE_CODE_OF_FUNC_HP_INFO(hotplug_info) \
+	((hotplug_info & FUNC_HP_SCENE_CODE_MASK) >> FUNC_HP_SCENE_CODE_START_BIT)
+#define FUNC_TYPE_OF_FUNC_HP_INFO(hotplug_info) \
+	((hotplug_info & FUNC_HP_FUNC_TYPE_MASK) >> FUNC_HP_FUNC_TYPE_START_BIT)
+#define EP_ID_OF_FUNC_HP_INFO(hotplug_info) \
+	((hotplug_info & FUNC_HP_EP_ID_MASK) >> FUNC_HP_EP_ID_START_BIT)
+#define PF_ID_OF_FUNC_HP_INFO(hotplug_info) \
+	((hotplug_info & FUNC_HP_PF_ID_MASK) >> FUNC_HP_PF_ID_START_BIT)
+#define VF_ID_OF_FUNC_HP_INFO(hotplug_info) \
+	((hotplug_info & FUNC_HP_VF_ID_MASK) >> FUNC_HP_VF_ID_START_BIT)
+
+#define FUNCTION_HP_TYPE_COUNT 2
+#define MAX_EP_NUMS 4
+#define MAX_PF_NUMS_OF_EP 8
+#define MAX_PF_NUMS (MAX_PF_NUMS_OF_EP * MAX_EP_NUMS)
+
+#define FUC_HOTPLUG_PF_INIT_FLAG_OFFSET 0x10
+#define FUC_HOTPLUG_PF_STATE_FLAG_OFFSET 0x20
+#define FUC_HOTPLUG_PF_INIT_FLAG 0x450000
 
 enum FUC_HOTPLUG_INFO_ {
-    PCIE_HOTPLUG_START = 1,
-    PCIE_HOTPLUG_FINISH,
+	PCIE_HOTPLUG_START = 1,
+	PCIE_HOTPLUG_FINISH,
 };
 
 enum zte_pcie_func_type {
-    PCIE_FUNC_TYPE_PF = 0,
-    PCIE_FUNC_TYPE_VF,
-    PCIE_FUNC_TYPE_NUM
+	PCIE_FUNC_TYPE_PF = 0,
+	PCIE_FUNC_TYPE_VF,
+	PCIE_FUNC_TYPE_NUM
 };
 
 typedef enum {
-    FUNCTION_REMOVE = 1,
-    FUNCTION_INSERT,
+	FUNCTION_REMOVE = 1,
+	FUNCTION_INSERT,
 } FUNCTION_HP_TYPE;
 
 struct func_hotplug_info {
-    unsigned int reserved: 8;
-    unsigned int scene_code: 3;     // 1-热拔；2-热插；
-    unsigned int function_type: 1;  // pf-0;vf-1;
-    unsigned int ep_id: 4;          // 5~9(对应ep0~4)
-    unsigned int pf_id: 4;          // 0~7
-    unsigned int vf_id: 12;         // 0~127
+	unsigned int reserved : 8;
+	unsigned int scene_code : 3; // 1-热拔；2-热插；
+	unsigned int function_type : 1; // pf-0;vf-1;
+	unsigned int ep_id : 4; // 5~9(对应ep0~4)
+	unsigned int pf_id : 4; // 0~7
+	unsigned int vf_id : 12; // 0~127
 };
 
 struct func_hotplug_req {
-    /* hotplug_info
-        bit[31:24]: reserved:
-        bit[23:21]: scene_code 1-热拔、2-热插
-        bit[20]:    function_type 0-PF、1-VF
-        bit[19:16]: ep_id 范围: 5~9(对应ep0~4)
-        bit[15:12]: pf_id 范围: 0~7
-        bit[11:0]:  vf_id 范围: 0~127
-    */
-    u32 hotplug_info;
-    u32 domain;
-    u32 bdf;
+	/* hotplug_info
+      bit[31:24]: reserved:
+      bit[23:21]: scene_code 1-热拔、2-热插
+      bit[20]:    function_type 0-PF、1-VF
+      bit[19:16]: ep_id 范围: 5~9(对应ep0~4)
+      bit[15:12]: pf_id 范围: 0~7
+      bit[11:0]:  vf_id 范围: 0~127
+  */
+	u32 hotplug_info;
+	u32 domain;
+	u32 bdf;
 };
 
 struct func_hotplug_result {
-    unsigned int cmd;
-
-    /* hotplug_info 
-        bit[31:24]: reserved:
-        bit[23:21]: scene_code 0-热拔、1-热插
-        bit[20]:    function_type 0-PF、1-VF
-        bit[19:16]: ep_id 范围: 5~9(对应ep0~4)
-        bit[15:12]: pf_id 范围: 0~7
-        bit[11:0]:  vf_id 范围: 0~127
-    */
-    u32 hotplug_info;
-    u32 result;
+	unsigned int cmd;
+
+	/* hotplug_info
+      bit[31:24]: reserved:
+      bit[23:21]: scene_code 0-热拔、1-热插
+      bit[20]:    function_type 0-PF、1-VF
+      bit[19:16]: ep_id 范围: 5~9(对应ep0~4)
+      bit[15:12]: pf_id 范围: 0~7
+      bit[11:0]:  vf_id 范围: 0~127
+  */
+	u32 hotplug_info;
+	u32 result;
 };
 
 struct func_hotplug_state {
-    u32 pf_state_mask;
-    u32 domain[4];
-    u32 bdf[4];
+	u32 pf_state_mask;
+	u32 domain[4];
+	u32 bdf[4];
 };
 
 struct zte_dpu_id_info {
-    char *name;
-    u16 device_id;
-    u16 vendor_id;
+	char *name;
+	u16 device_id;
+	u16 vendor_id;
 };
 
 struct fuc_hotplug_bar_msg {
-    unsigned int  cmd;
-    unsigned int  fuc_hotplug_info;
-    unsigned int  timeout;
-    unsigned int  cpl_chk;
+	unsigned int cmd;
+	unsigned int fuc_hotplug_info;
+	unsigned int timeout;
+	unsigned int cpl_chk;
 };
 
 int init_pf_hotplug_info(void);
diff --git a/src/net/drivers/pcie/zxdh_pcie/pcie_common.c b/src/net/drivers/pcie/zxdh_pcie/pcie_common.c
index 75eae382eac21d70aa24dc10e78bca633e47c4ee..a3a153557f25285dc59cc7a3855e0d8e182730d8 100644
--- a/src/net/drivers/pcie/zxdh_pcie/pcie_common.c
+++ b/src/net/drivers/pcie/zxdh_pcie/pcie_common.c
@@ -9,145 +9,124 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/string.h>
-
 #include "pcie_common.h"
 
 struct pci_dev *zxdh_get_pci_device(u32 domain, u32 bdf)
 {
-    struct pci_bus *bus = NULL;
-    struct pci_dev *dev = NULL;
-
-    bus = pci_find_bus(domain, (bdf >> 8));
-    if (!bus)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Can not find this bus\n");
-        return NULL;
-    }
-
-    while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
-    {
-        if (dev->bus == bus && PCI_SLOT(dev->devfn) == PCI_SLOT(bdf) && PCI_FUNC(dev->devfn) == PCI_FUNC(bdf))
-        {
-            return dev;
-        }
-    }
-
-    return NULL;
+	struct pci_bus *bus = NULL;
+	struct pci_dev *dev = NULL;
+
+	bus = pci_find_bus(domain, (bdf >> 8));
+	if (!bus) {
+		DH_LOG_ERR(MODULE_FUC_HP, "Can not find this bus\n");
+		return NULL;
+	}
+
+	while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
+		if (dev->bus == bus && PCI_SLOT(dev->devfn) == PCI_SLOT(bdf) &&
+			PCI_FUNC(dev->devfn) == PCI_FUNC(bdf)) {
+			return dev;
+		}
+	}
+
+	return NULL;
 }
 
 int fill_domain_bdf_str(const char *token, char *dst_str, const int len)
 {
-    int ret = PCIE_SUCCESS;
-    int i = 0;
-    int j = 0;
-
-    if (strlen(token) < len)
-    {
-        for (i = 0; i < (len - strlen(token)); ++i)
-        {
-            dst_str[i] = '0';
-        }
-        for (j = i; j < len; ++j)
-        {
-            dst_str[j] = token[j - i];
-        }
-        dst_str[j] = 0;
-    }
-    else if (strlen(token) > len)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "error token, size=%ld\n", strlen(token));
-        ret = PCIE_FAILED;
-    }
-    else
-    {
-        memcpy(dst_str, token, strlen(token) + 1);
-    }
-
-    return ret;
+	int ret = PCIE_SUCCESS;
+	int i = 0;
+	int j = 0;
+
+	if (strlen(token) < len) {
+		for (i = 0; i < (len - strlen(token)); ++i) {
+			dst_str[i] = '0';
+		}
+		for (j = i; j < len; ++j) {
+			dst_str[j] = token[j - i];
+		}
+		dst_str[j] = 0;
+	} else if (strlen(token) > len) {
+		DH_LOG_ERR(MODULE_FUC_HP, "error token, size=%ld\n", strlen(token));
+		ret = PCIE_FAILED;
+	} else {
+		memcpy(dst_str, token, strlen(token) + 1);
+	}
+
+	return ret;
 }
 
 int parse_bdf(char *str)
 {
-    int ret = PCIE_SUCCESS;
-    int size = 0;
-    char *token = NULL;
-    struct domain_bdf domain_bdf = {0};
-    char *tempString = kstrdup(str, GFP_KERNEL);
-
-    memset(&domain_bdf, 0, sizeof(struct domain_bdf));
-
-    if (tempString == NULL)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "tempString is NULL\n");
-        return PCIE_FAILED;
-    }
-
-    token = strsep(&tempString, ":");
-    if (token == NULL)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "strsep fail\n");
-        goto failed;
-    }
-    ret = fill_domain_bdf_str(token, domain_bdf.domain, DOMAIN_LEN);
-    if (ret != PCIE_SUCCESS)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "error domain, token=%s\n", token);
-        goto failed;
-    }
-
-    token = strsep(&tempString, ":");
-    if (token == NULL)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "strsep fail\n");
-        goto failed;
-    }
-    ret = fill_domain_bdf_str(token, domain_bdf.bus, BUS_LEN);
-    if (ret != PCIE_SUCCESS)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "rror bus\n");
-        goto failed;
-    }
-
-    token = strsep(&tempString, ".");
-    if (token == NULL)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "strsep fail\n");
-        goto failed;
-    }
-    ret = fill_domain_bdf_str(token, domain_bdf.device, DEVICE_LEN);
-    if (ret != PCIE_SUCCESS)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "error device\n");
-        goto failed;
-    }
-
-    token = strsep(&tempString, ".");
-    if (token == NULL)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "strsep fail\n");
-        goto failed;
-    }
-    ret = fill_domain_bdf_str(token, domain_bdf.func, FUNC_LEN);
-    if (ret != PCIE_SUCCESS)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP,"error func\n");
-        goto failed;
-    }
-
-    size = snprintf(str, FILE_PATH_LEN, "%s:%s:%s.%s", domain_bdf.domain, domain_bdf.bus, domain_bdf.device, domain_bdf.func);
-    if (size >= FILE_PATH_LEN)
-    {
-        str[FILE_PATH_LEN - 1] = '\0';
-    }
-
-    kfree(tempString);
-    tempString = NULL;
-
-    return PCIE_SUCCESS;
+	int ret = PCIE_SUCCESS;
+	char *token = NULL;
+	struct domain_bdf domain_bdf = { 0 };
+	char *tempString = kstrdup(str, GFP_KERNEL);
+
+	memset(&domain_bdf, 0, sizeof(struct domain_bdf));
+
+	if (tempString == NULL) {
+		DH_LOG_ERR(MODULE_FUC_HP, "tempString is NULL\n");
+		return PCIE_FAILED;
+	}
+
+	token = strsep(&tempString, ":");
+	if (token == NULL) {
+		DH_LOG_ERR(MODULE_FUC_HP, "strsep fail\n");
+		goto failed;
+	}
+	ret = fill_domain_bdf_str(token, domain_bdf.domain, DOMAIN_LEN);
+	if (ret != PCIE_SUCCESS) {
+		DH_LOG_ERR(MODULE_FUC_HP, "error domain, token=%s\n", token);
+		goto failed;
+	}
+
+	token = strsep(&tempString, ":");
+	if (token == NULL) {
+		DH_LOG_ERR(MODULE_FUC_HP, "strsep fail\n");
+		goto failed;
+	}
+	ret = fill_domain_bdf_str(token, domain_bdf.bus, BUS_LEN);
+	if (ret != PCIE_SUCCESS) {
+		DH_LOG_ERR(MODULE_FUC_HP, "rror bus\n");
+		goto failed;
+	}
+
+	token = strsep(&tempString, ".");
+	if (token == NULL) {
+		DH_LOG_ERR(MODULE_FUC_HP, "strsep fail\n");
+		goto failed;
+	}
+	ret = fill_domain_bdf_str(token, domain_bdf.device, DEVICE_LEN);
+	if (ret != PCIE_SUCCESS) {
+		DH_LOG_ERR(MODULE_FUC_HP, "error device\n");
+		goto failed;
+	}
+
+	token = strsep(&tempString, ".");
+	if (token == NULL) {
+		DH_LOG_ERR(MODULE_FUC_HP, "strsep fail\n");
+		goto failed;
+	}
+	ret = fill_domain_bdf_str(token, domain_bdf.func, FUNC_LEN);
+	if (ret != PCIE_SUCCESS) {
+		DH_LOG_ERR(MODULE_FUC_HP, "error func\n");
+		goto failed;
+	}
+
+	snprintf(str, FILE_PATH_LEN, "%s:%s:%s.%s", domain_bdf.domain,
+			 domain_bdf.bus, domain_bdf.device, domain_bdf.func);
+
+	kfree(tempString);
+	tempString = NULL;
+
+	return PCIE_SUCCESS;
 
 failed:
-    kfree(tempString);
-    tempString = NULL;
-    DH_LOG_ERR(MODULE_FUC_HP, "Input format error, refer to '[domain]:[bus_no]:[dev_no].[func_no]'\n");
-    return PCIE_FAILED;
+	kfree(tempString);
+	tempString = NULL;
+	DH_LOG_ERR(
+			MODULE_FUC_HP,
+			"Input format error, refer to '[domain]:[bus_no]:[dev_no].[func_no]'\n");
+	return PCIE_FAILED;
 }
diff --git a/src/net/drivers/pcie/zxdh_pcie/pcie_common.h b/src/net/drivers/pcie/zxdh_pcie/pcie_common.h
index d4abaf40d22eabc416686bd766eb99716dc09dcb..7a38c609d8477108509fba55cffd4316406341c2 100644
--- a/src/net/drivers/pcie/zxdh_pcie/pcie_common.h
+++ b/src/net/drivers/pcie/zxdh_pcie/pcie_common.h
@@ -16,30 +16,30 @@ extern "C" {
 #define PCIE_SUCCESS 0
 #define PCIE_FAILED -1
 
-#define KERNEL_VFIO_VFIO_TEST_NAME          "/dev/vfio/vfio"
-#define PCI_DEVICES_DIR                     "/sys/bus/pci/devices"
-#define SYS_BUS_PCI_DIR                     "/sys/bus/pci"
-#define PCI_PHYSFN_DRV_PATH                 "physfn/driver"
-#define FILE_PATH_LEN                       100
+#define KERNEL_VFIO_VFIO_TEST_NAME "/dev/vfio/vfio"
+#define PCI_DEVICES_DIR "/sys/bus/pci/devices"
+#define SYS_BUS_PCI_DIR "/sys/bus/pci"
+#define PCI_PHYSFN_DRV_PATH "physfn/driver"
+#define FILE_PATH_LEN 100
 
-#define DOMAIN_LEN                          4
-#define BUS_LEN                             2
-#define DEVICE_LEN                          2
-#define FUNC_LEN                            1
+#define DOMAIN_LEN 4
+#define BUS_LEN 2
+#define DEVICE_LEN 2
+#define FUNC_LEN 1
 
-#define BDF_NO_BUS_NO_MASK                  (0xFF << 8)
-#define BDF_NO_DEV_NO_MASK                  (0x1F << 3)
-#define BDF_NO_FUNC_NO_MASK                 (0x7 << 0)
+#define BDF_NO_BUS_NO_MASK (0xFF << 8)
+#define BDF_NO_DEV_NO_MASK (0x1F << 3)
+#define BDF_NO_FUNC_NO_MASK (0x7 << 0)
 
-#define BDF_F_START_BIT                     0
-#define BDF_D_START_BIT                     3
-#define BDF_B_START_BIT                     8
+#define BDF_F_START_BIT 0
+#define BDF_D_START_BIT 3
+#define BDF_B_START_BIT 8
 
 struct domain_bdf {
-    char domain[DOMAIN_LEN + 1];
-    char bus[BUS_LEN + 1];
-    char device[DEVICE_LEN + 1];
-    char func[FUNC_LEN + 1];
+	char domain[DOMAIN_LEN + 1];
+	char bus[BUS_LEN + 1];
+	char device[DEVICE_LEN + 1];
+	char func[FUNC_LEN + 1];
 };
 
 struct pci_dev *zxdh_get_pci_device(u32 domain, u32 bdf);
diff --git a/src/net/drivers/pcie/zxdh_pcie/pcie_msix.c b/src/net/drivers/pcie/zxdh_pcie/pcie_msix.c
index 0aa5fbbbfbac0e3459a366d337efa7c5fe72228b..dc545ad4cbdcca60f3a3ef13d1c917cd3440e14c 100644
--- a/src/net/drivers/pcie/zxdh_pcie/pcie_msix.c
+++ b/src/net/drivers/pcie/zxdh_pcie/pcie_msix.c
@@ -4,7 +4,6 @@
 #include<linux/sysfs.h>
 #include<linux/kobject.h>
 #include <linux/err.h>
-
 #include "bar_msg.h"
 #include "pcie_msix.h"
 #include "function_hotplug.h"
@@ -16,73 +15,78 @@ extern irqreturn_t func_hp_msix_thread(int irq_no, void *data);
 extern irqreturn_t irq_thread2(int irq_no, void *data);
 
 static struct msix_handler_info msix_handler_info_arr[] = {
-    /* irq_id,              irq_handler              irq_thread                     irq_name */
-    {IRQ_NO_INIT_VALUE,     func_hp_msix_handler,    func_hp_msix_thread,           "function_hotplug_msix"},
-    {IRQ_NO_INIT_VALUE,     irq_handler2,            irq_thread2,                   "irq_thread2"},
+	/* irq_id,              irq_handler              irq_thread irq_name */
+	{ IRQ_NO_INIT_VALUE, func_hp_msix_handler, func_hp_msix_thread,
+	  "function_hotplug_msix" },
+	{ IRQ_NO_INIT_VALUE, irq_handler2, irq_thread2, "irq_thread2" },
 };
 
 int request_msix(void)
 {
-    int ret = 0;
-    int i = 0;
-    int msix_nums = 0;
-    struct pci_dev *pdev = NULL;
+	int ret = 0;
+	int i = 0;
+	int msix_nums = 0;
+	struct pci_dev *pdev = NULL;
 
-    pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, pdev);
-    if (IS_ERR_OR_NULL(pdev))
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "pci get device fail! deviceid=0x%x, vendorid=0x%x\n", HP_DEVICE_ID, HP_VENDOR_ID);
-        return -EINVAL;
-    }
+	pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, pdev);
+	if (!pdev) {
+		DH_LOG_ERR(MODULE_FUC_HP,
+				   "pci get device fail! deviceid=0x%x, vendorid=0x%x\n",
+				   HP_DEVICE_ID, HP_VENDOR_ID);
+		return -EINVAL;
+	}
 
-    if (pci_enable_device(pdev))
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "enbale dev failed\n");
-    }
+	if (pci_enable_device(pdev)) {
+		DH_LOG_ERR(MODULE_FUC_HP, "enbale dev failed\n");
+	}
 
-    msix_nums = sizeof(msix_handler_info_arr) / sizeof(struct msix_handler_info);
-    ret = pci_alloc_irq_vectors(pdev, msix_nums, msix_nums, PCI_IRQ_MSIX);
-    if (ret < 0)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "Can not alloc msix irq vector msix_nums=%d, ret=%d\n", msix_nums, ret);
-        return ret;
-    }
+	msix_nums =
+			sizeof(msix_handler_info_arr) / sizeof(struct msix_handler_info);
+	ret = pci_alloc_irq_vectors(pdev, msix_nums, msix_nums, PCI_IRQ_MSIX);
+	if (ret < 0) {
+		DH_LOG_ERR(MODULE_FUC_HP,
+				   "Can not alloc msix irq vector msix_nums=%d, ret=%d\n",
+				   msix_nums, ret);
+		return ret;
+	}
 
-    for (i = 0; i < msix_nums; ++i)
-    {
-        msix_handler_info_arr[i].irq_id = i;
+	for (i = 0; i < msix_nums; ++i) {
+		msix_handler_info_arr[i].irq_id = i;
 
-        ret = pci_request_irq(pdev, i, msix_handler_info_arr[i].irq_handler_func, msix_handler_info_arr[i].irq_thread_func,
-                    &msix_handler_info_arr[i].irq_id, "%s%d", msix_handler_info_arr[i].irq_name, i);
-        if (ret)
-        {
-            pci_free_irq_vectors(pdev);
-            DH_LOG_ERR(MODULE_FUC_HP, "request msix[%d] failed --> %d\n", i, ret);
-        }
-    }
+		ret = pci_request_irq(pdev, i,
+							  msix_handler_info_arr[i].irq_handler_func,
+							  msix_handler_info_arr[i].irq_thread_func,
+							  &msix_handler_info_arr[i].irq_id, "%s%d",
+							  msix_handler_info_arr[i].irq_name, i);
+		if (ret) {
+			pci_free_irq_vectors(pdev);
+			DH_LOG_ERR(MODULE_FUC_HP, "request msix[%d] failed --> %d\n", i,
+					   ret);
+		}
+	}
 
-    return ret;
+	return ret;
 }
 
 int free_msix(void)
 {
-    int msix_nums = 0;
-    int i = 0;
-    struct pci_dev *pdev = NULL;
+	int msix_nums = 0;
+	int i = 0;
+	struct pci_dev *pdev = NULL;
 
-    pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, pdev);
-    if (IS_ERR_OR_NULL(pdev))
-    {
-        DH_LOG_WARNING(MODULE_FUC_HP, "pdev has released\n");
-        return 0;
-    }
+	pdev = pci_get_device(HP_VENDOR_ID, HP_DEVICE_ID, pdev);
+	if (!pdev) {
+		DH_LOG_WARNING(MODULE_FUC_HP, "pdev has released\n");
+		return 0;
+	}
 
-    msix_nums = sizeof(msix_handler_info_arr) / sizeof(struct msix_handler_info);
-    for (i = 0; i < msix_nums; ++i)
-    {
-        pci_free_irq(pdev, msix_handler_info_arr[i].irq_id, &msix_handler_info_arr[i].irq_id);
-    }
-    pci_free_irq_vectors(pdev);
+	msix_nums =
+			sizeof(msix_handler_info_arr) / sizeof(struct msix_handler_info);
+	for (i = 0; i < msix_nums; ++i) {
+		pci_free_irq(pdev, msix_handler_info_arr[i].irq_id,
+					 &msix_handler_info_arr[i].irq_id);
+	}
+	pci_free_irq_vectors(pdev);
 
-    return 0;
+	return 0;
 }
diff --git a/src/net/drivers/pcie/zxdh_pcie/pcie_msix.h b/src/net/drivers/pcie/zxdh_pcie/pcie_msix.h
index 1ab4d87d15d61ff5475c8e176b745385566f1968..15cc0a52b2662c4d8e216898f140a955787be911 100644
--- a/src/net/drivers/pcie/zxdh_pcie/pcie_msix.h
+++ b/src/net/drivers/pcie/zxdh_pcie/pcie_msix.h
@@ -13,13 +13,13 @@ extern "C" {
 typedef irqreturn_t (*irq_handler)(int irq_no, void *data);
 typedef irqreturn_t (*irq_thread)(int irq, void *data);
 
-#define IRQ_NO_INIT_VALUE                               (-1)
-#define MSIX_NAME_LEN                                   30
+#define IRQ_NO_INIT_VALUE (-1)
+#define MSIX_NAME_LEN 30
 struct msix_handler_info {
-    int irq_id;
-    irq_handler irq_handler_func;
-    irq_thread irq_thread_func;
-    char irq_name[MSIX_NAME_LEN];
+	int irq_id;
+	irq_handler irq_handler_func;
+	irq_thread irq_thread_func;
+	char irq_name[MSIX_NAME_LEN];
 };
 
 #ifdef __cplusplus
diff --git a/src/net/drivers/pcie/zxdh_pcie/zxdh_pcie.c b/src/net/drivers/pcie/zxdh_pcie/zxdh_pcie.c
index 7b590db8c2642643f7fb516bef50ae494f867a1a..b755a886ab6929396aca03206fbf9ebc65b8914d 100644
--- a/src/net/drivers/pcie/zxdh_pcie/zxdh_pcie.c
+++ b/src/net/drivers/pcie/zxdh_pcie/zxdh_pcie.c
@@ -8,160 +8,146 @@
 #include <linux/msi.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-
 #include "bar_msg.h"
 #include "function_hotplug.h"
 #include "pcie_common.h"
 
-#ifdef DRIVER_VERSION_VAL
-    #define DRV_VERSION DRIVER_VERSION_VAL
-#else
-    #define DRV_VERSION "1.0-1"
-#endif
-
 int zxdh_pcie_init(void)
 {
-    int ret = 0;
-
-    ret = init_pf_hotplug_info();
-    if (ret != 0)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "int pf hot plug info failed.\n");
-        return ret;
-    }
-
-
-    ret = init_pf_state();
-    if (ret != 0)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "init_pf_state failed\n");
-        return ret;
-    }
-
-    ret = enable_vf();
-    if (ret != 0)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "enable_vf failed\n");
-        return ret;
-    }
-
-    DH_LOG_INFO(MODULE_FUC_HP, "zxdh pf hotplug module init success.\n");
-    return ret;
+	int ret = 0;
+
+	ret = init_pf_hotplug_info();
+	if (ret != 0) {
+		DH_LOG_ERR(MODULE_FUC_HP, "int pf hot plug info failed.\n");
+		return ret;
+	}
+
+	ret = init_pf_state();
+	if (ret != 0) {
+		DH_LOG_ERR(MODULE_FUC_HP, "init_pf_state failed\n");
+		return ret;
+	}
+
+	ret = enable_vf();
+	if (ret != 0) {
+		DH_LOG_ERR(MODULE_FUC_HP, "enable_vf failed\n");
+		return ret;
+	}
+
+	DH_LOG_INFO(MODULE_FUC_HP, "zxdh pf hotplug module init success.\n");
+	return ret;
 }
 
 void zxdh_pcie_exit(void)
 {
-    free_msix();
-    DH_LOG_INFO(MODULE_FUC_HP, "zxdh pcie remove success.\n");
+	free_msix();
+	DH_LOG_INFO(MODULE_FUC_HP, "zxdh pcie remove success.\n");
 }
 
 static const struct pci_device_id dh_hpf_pci_table[] = {
-   { PCI_DEVICE(HP_VENDOR_ID, HP_DEVICE_ID), 0 },
-   { 0, }
+	{ PCI_DEVICE(HP_VENDOR_ID, HP_DEVICE_ID), 0 },
+	{
+			0,
+	}
 };
 
 MODULE_DEVICE_TABLE(pci, dh_hpf_pci_table);
 
-static int32_t dh_hpf_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+static int32_t dh_hpf_probe(struct pci_dev *pdev,
+							const struct pci_device_id *id)
 {
-    int32_t ret = 0;
-
-    ret = init_bdf();
-    if (ret != 0)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "init_bdf failed.\n");
-    }
-
-    ret = request_msix();
-    if(ret != 0)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP, "request_msix failed\n");
-        return ret;
-    }
-    DH_LOG_INFO(MODULE_FUC_HP,"hpf driver probe completed\n");
-    return 0;
+	int32_t ret = 0;
+
+	ret = init_bdf();
+	if (ret != 0) {
+		DH_LOG_ERR(MODULE_FUC_HP, "init_bdf failed.\n");
+	}
+
+	ret = request_msix();
+	if (ret != 0) {
+		DH_LOG_ERR(MODULE_FUC_HP, "request_msix failed\n");
+		return ret;
+	}
+	DH_LOG_INFO(MODULE_FUC_HP, "hpf driver probe completed\n");
+	return 0;
 }
 
 static void dh_hpf_remove(struct pci_dev *pdev)
 {
-    zxdh_pcie_exit();
-    DH_LOG_INFO(MODULE_FUC_HP,"hpf driver remove completed\n");
+	zxdh_pcie_exit();
+	DH_LOG_INFO(MODULE_FUC_HP, "hpf driver remove completed\n");
 }
 
-
 static int32_t dh_hpf_suspend(struct pci_dev *pdev, pm_message_t state)
 {
-    return 0;
+	return 0;
 }
 
 static int32_t dh_hpf_resume(struct pci_dev *pdev)
 {
-    return 0;
+	return 0;
 }
 
 static void dh_hpf_shutdown(struct pci_dev *pdev)
 {
-    dh_hpf_remove(pdev);
+	dh_hpf_remove(pdev);
 }
 
 static pci_ers_result_t dh_pci_err_detected(struct pci_dev *pdev,
-                                            pci_channel_state_t state)
+											pci_channel_state_t state)
 {
-    return PCI_ERS_RESULT_NONE;
+	return PCI_ERS_RESULT_NONE;
 }
 
 static pci_ers_result_t dh_hpf_pci_slot_reset(struct pci_dev *pdev)
 {
-    return PCI_ERS_RESULT_NONE;
+	return PCI_ERS_RESULT_NONE;
 }
 
 static void dh_hpf_pci_resume(struct pci_dev *pdev)
 {
-
 }
 
 static const struct pci_error_handlers dh_hpf_err_handler = {
-    .error_detected = dh_pci_err_detected,
-    .slot_reset     = dh_hpf_pci_slot_reset,
-    .resume         = dh_hpf_pci_resume
+	.error_detected = dh_pci_err_detected,
+	.slot_reset = dh_hpf_pci_slot_reset,
+	.resume = dh_hpf_pci_resume
 };
 
 static struct pci_driver dh_hpf_driver = {
-    .name           = KBUILD_MODNAME,
-    .id_table       = dh_hpf_pci_table,
-    .probe          = dh_hpf_probe,
-    .remove         = dh_hpf_remove,
-    .suspend        = dh_hpf_suspend,
-    .resume         = dh_hpf_resume,
-    .shutdown       = dh_hpf_shutdown,
-    .err_handler    = &dh_hpf_err_handler,
+	.name = KBUILD_MODNAME,
+	.id_table = dh_hpf_pci_table,
+	.probe = dh_hpf_probe,
+	.remove = dh_hpf_remove,
+	.suspend = dh_hpf_suspend,
+	.resume = dh_hpf_resume,
+	.shutdown = dh_hpf_shutdown,
+	.err_handler = &dh_hpf_err_handler,
 };
 
 static int32_t __init init(void)
 {
-    int32_t err = 0;
+	int32_t err = 0;
 
-    err = pci_register_driver(&dh_hpf_driver);
-    if (err != 0)
-    {
-        DH_LOG_ERR(MODULE_FUC_HP,"pci_register_driver failed: %d\n", err);
-        return err;
-    }
+	err = pci_register_driver(&dh_hpf_driver);
+	if (err != 0) {
+		DH_LOG_ERR(MODULE_FUC_HP, "pci_register_driver failed: %d\n", err);
+		return err;
+	}
 
-    zxdh_pcie_init();
+	zxdh_pcie_init();
 
-    DH_LOG_INFO(MODULE_FUC_HP,"zxdh_hpf driver init success\n");
-    return err;
+	DH_LOG_INFO(MODULE_FUC_HP, "zxdh_hpf driver init success\n");
+	return err;
 }
 
 static void __exit cleanup(void)
 {
-    pci_unregister_driver(&dh_hpf_driver);
-    DH_LOG_INFO(MODULE_FUC_HP,"zxdh_hpf driver remove success\n");
+	pci_unregister_driver(&dh_hpf_driver);
+	DH_LOG_INFO(MODULE_FUC_HP, "zxdh_hpf driver remove success\n");
 }
 
 module_init(init);
 module_exit(cleanup);
 MODULE_LICENSE("GPL v2");
 MODULE_AUTHOR("ZTE ZXDH HP");
-MODULE_VERSION(DRV_VERSION);
diff --git a/src/net/include/linux/dinghai/auxiliary_bus.h b/src/net/include/linux/dinghai/auxiliary_bus.h
old mode 100755
new mode 100644
index 6bb6509956804cbeb85a7f0122d4f76b1dd69bda..19e0d24d3222e2f7698ca77079c390723d921f4c
--- a/src/net/include/linux/dinghai/auxiliary_bus.h
+++ b/src/net/include/linux/dinghai/auxiliary_bus.h
@@ -1,153 +1,284 @@
-
-#ifndef _AUXILIARY_BUS_H_
-#define _AUXILIARY_BUS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/device.h>
-#include <linux/mod_devicetable.h>
-
-
-#define ZXDH_AUXILIARY_NAME_SIZE 32
-#define ZXDH_AUXILIARY_MODULE_PREFIX "zxdh_auxiliary:"
-
-struct zxdh_auxiliary_device_id
-{
-    char name[ZXDH_AUXILIARY_NAME_SIZE];
-    kernel_ulong_t driver_data;
-};
-
-struct zxdh_auxiliary_device {
-    struct device dev;
-    const char *name;
-    uint32_t id;
-};
-
-/**
- * struct zxdh_auxiliary_driver - Definition of an auxiliary bus driver
- * @probe: Called when a matching device is added to the bus.
- * @remove: Called when device is removed from the bus.
- * @shutdown: Called at shut-down time to quiesce the device.
- * @suspend: Called to put the device to sleep mode. Usually to a power state.
- * @resume: Called to bring a device from sleep mode.
- * @name: Driver name.
- * @driver: Core driver structure.
- * @id_table: Table of devices this driver should match on the bus.
- *
- * Auxiliary drivers follow the standard driver model convention, where
- * discovery/enumeration is handled by the core, and drivers provide probe()
- * and remove() methods. They support power management and shutdown
- * notifications using the standard conventions.
- *
- * Auxiliary drivers register themselves with the bus by calling
- * zxdh_auxiliary_driver_register(). The id_table contains the match_names of
- * auxiliary devices that a driver can bind with.
- *
- * .. code-block:: c
- *
- *         static const struct zxdh_auxiliary_device_id my_auxiliary_id_table[] = {
- *           { .name = "foo_mod.foo_dev" },
- *                 {},
- *         };
- *
- *         MODULE_DEVICE_TABLE(zxdh_auxiliary, my_auxiliary_id_table);
- *
- *         struct zxdh_auxiliary_driver my_drv = {
- *                 .name = "myauxiliarydrv",
- *                 .id_table = my_auxiliary_id_table,
- *                 .probe = my_drv_probe,
- *                 .remove = my_drv_remove
- *         };
- */
-struct zxdh_auxiliary_driver {
-    int32_t (*probe)(struct zxdh_auxiliary_device *auxdev, const struct zxdh_auxiliary_device_id *id);
-    int32_t (*remove)(struct zxdh_auxiliary_device *auxdev);
-    void (*shutdown)(struct zxdh_auxiliary_device *auxdev);
-    int32_t (*suspend)(struct zxdh_auxiliary_device *auxdev, pm_message_t state);
-    int32_t (*resume)(struct zxdh_auxiliary_device *auxdev);
-    const char *name;
-    struct device_driver driver;
-    const struct zxdh_auxiliary_device_id *id_table;
-};
-
-static inline void *zxdh_auxiliary_get_drvdata(struct zxdh_auxiliary_device *auxdev)
-{
-    return dev_get_drvdata(&auxdev->dev);
-}
-
-static inline void zxdh_auxiliary_set_drvdata(struct zxdh_auxiliary_device *auxdev, void *data)
-{
-    dev_set_drvdata(&auxdev->dev, data);
-}
-
-static inline struct zxdh_auxiliary_device *zxdh_to_auxiliary_dev(struct device *dev)
-{
-    return container_of(dev, struct zxdh_auxiliary_device, dev);
-}
-
-static inline struct zxdh_auxiliary_driver *zxdh_to_auxiliary_drv(struct device_driver *drv)
-{
-    return container_of(drv, struct zxdh_auxiliary_driver, driver);
-}
-
-int32_t zxdh_auxiliary_device_init(struct zxdh_auxiliary_device *auxdev);
-int32_t zxdh_aux_dev_add(struct zxdh_auxiliary_device *auxdev, const char *modname);
-#define zxdh_auxiliary_device_add(auxdev) zxdh_aux_dev_add(auxdev, KBUILD_MODNAME)
-
-static inline void zxdh_auxiliary_device_uninit(struct zxdh_auxiliary_device *auxdev)
-{
-    put_device(&auxdev->dev);
-}
-
-static inline void zxdh_auxiliary_device_delete(struct zxdh_auxiliary_device *auxdev)
-{
-    device_del(&auxdev->dev);
-}
-
-int32_t zxdh_aux_drv_register(struct zxdh_auxiliary_driver *auxdrv, struct module *owner,
-                              const char *modname);
-#define zxdh_auxiliary_driver_register(auxdrv) \
-    zxdh_aux_drv_register(auxdrv, THIS_MODULE, KBUILD_MODNAME)
-
-void zxdh_auxiliary_driver_unregister(struct zxdh_auxiliary_driver *auxdrv);
-
-/**
- * module_auxiliary_driver() - Helper macro for registering an auxiliary driver
- * @__auxiliary_driver: auxiliary driver struct
- *
- * Helper macro for auxiliary drivers which do not do anything special in
- * module init/exit. This eliminates a lot of boilerplate. Each module may only
- * use this macro once, and calling it replaces module_init() and module_exit()
- *
- * .. code-block:: c
- *
- *    module_auxiliary_driver(my_drv);
- */
-#define module_auxiliary_driver(__auxiliary_driver) \
-    module_driver(__auxiliary_driver, zxdh_auxiliary_driver_register, zxdh_auxiliary_driver_unregister)
-
-#ifdef HAVE_LINUX_DEVICE_BUS_H
-struct zxdh_auxiliary_device *zxdh_auxiliary_find_device(struct device *start,
-                                                         const void *data,
-                                                         int32_t (*match)(struct device *dev, const void *data));
-#else
-#ifdef HAVE_BUS_FIND_DEVICE_GET_CONST
-struct zxdh_auxiliary_device *
-zxdh_auxiliary_find_device(struct device *start, 
-                           const void *data,
-                           int32_t (*match)(struct device *dev, const void *data));
-#else
-struct zxdh_auxiliary_device *
-zxdh_auxiliary_find_device(struct device *start, 
-                           void *data,
-                           int32_t (*match)(struct device *dev, void *data));
-#endif /* HAVE_BUS_FIND_DEVICE_GET_CONST */
-#endif /* HAVE_LINUX_DEVICE_BUS_H */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _AUXILIARY_BUS_H_ */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019-2020 Intel Corporation
+ *
+ * Please see Documentation/driver-api/auxiliary_bus.rst for more information.
+ */
+#ifndef _AUXILIARY_BUS_H_
+#define _AUXILIARY_BUS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/device.h>
+#include <linux/mod_devicetable.h>
+
+/**
+ * DOC: DEVICE_LIFESPAN
+ *
+ * The registering driver is the entity that allocates memory for the
+ * auxiliary_device and registers it on the auxiliary bus.  It is important to
+ * note that, as opposed to the platform bus, the registering driver is wholly
+ * responsible for the management of the memory used for the device object.
+ *
+ * To be clear the memory for the auxiliary_device is freed in the release()
+ * callback defined by the registering driver.  The registering driver should
+ * only call auxiliary_device_delete() and then auxiliary_device_uninit() when
+ * it is done with the device.  The release() function is then automatically
+ * called if and when other code releases their reference to the devices.
+ *
+ * A parent object, defined in the shared header file, contains the
+ * auxiliary_device.  It also contains a pointer to the shared object(s), which
+ * also is defined in the shared header.  Both the parent object and the shared
+ * object(s) are allocated by the registering driver.  This layout allows the
+ * auxiliary_driver's registering module to perform a container_of() call to go
+ * from the pointer to the auxiliary_device, that is passed during the call to
+ * the auxiliary_driver's probe function, up to the parent object, and then
+ * have access to the shared object(s).
+ *
+ * The memory for the shared object(s) must have a lifespan equal to, or
+ * greater than, the lifespan of the memory for the auxiliary_device.  The
+ * auxiliary_driver should only consider that the shared object is valid as
+ * long as the auxiliary_device is still registered on the auxiliary bus.  It
+ * is up to the registering driver to manage (e.g. free or keep available) the
+ * memory for the shared object beyond the life of the auxiliary_device.
+ *
+ * The registering driver must unregister all auxiliary devices before its own
+ * driver.remove() is completed.  An easy way to ensure this is to use the
+ * devm_add_action_or_reset() call to register a function against the parent
+ * device which unregisters the auxiliary device object(s).
+ *
+ * Finally, any operations which operate on the auxiliary devices must continue
+ * to function (if only to return an error) after the registering driver
+ * unregisters the auxiliary device.
+ */
+
+/**
+ * struct auxiliary_device - auxiliary device object.
+ * @dev: Device,
+ *       The release and parent fields of the device structure must be filled
+ *       in
+ * @name: Match name found by the auxiliary device driver,
+ * @id: unique identitier if multiple devices of the same name are exported,
+ *
+ * An auxiliary_device represents a part of its parent device's functionality.
+ * It is given a name that, combined with the registering drivers
+ * KBUILD_MODNAME, creates a match_name that is used for driver binding, and an
+ * id that combined with the match_name provide a unique name to register with
+ * the bus subsystem.  For example, a driver registering an auxiliary device is
+ * named 'foo_mod.ko' and the subdevice is named 'foo_dev'.  The match name is
+ * therefore 'foo_mod.foo_dev'.
+ *
+ * Registering an auxiliary_device is a three-step process.
+ *
+ * First, a 'struct auxiliary_device' needs to be defined or allocated for each
+ * sub-device desired.  The name, id, dev.release, and dev.parent fields of
+ * this structure must be filled in as follows.
+ *
+ * The 'name' field is to be given a name that is recognized by the auxiliary
+ * driver.  If two auxiliary_devices with the same match_name, eg
+ * "foo_mod.foo_dev", are registered onto the bus, they must have unique id
+ * values (e.g. "x" and "y") so that the registered devices names are
+ * "foo_mod.foo_dev.x" and "foo_mod.foo_dev.y".  If match_name + id are not
+ * unique, then the device_add fails and generates an error message.
+ *
+ * The auxiliary_device.dev.type.release or auxiliary_device.dev.release must
+ * be populated with a non-NULL pointer to successfully register the
+ * auxiliary_device.  This release call is where resources associated with the
+ * auxiliary device must be free'ed.  Because once the device is placed on the
+ * bus the parent driver can not tell what other code may have a reference to
+ * this data.
+ *
+ * The auxiliary_device.dev.parent should be set.  Typically to the registering
+ * drivers device.
+ *
+ * Second, call auxiliary_device_init(), which checks several aspects of the
+ * auxiliary_device struct and performs a device_initialize().  After this step
+ * completes, any error state must have a call to auxiliary_device_uninit() in
+ * its resolution path.
+ *
+ * The third and final step in registering an auxiliary_device is to perform a
+ * call to auxiliary_device_add(), which sets the name of the device and adds
+ * the device to the bus.
+ *
+ * .. code-block:: c
+ *
+ *      #define MY_DEVICE_NAME "foo_dev"
+ *
+ *      ...
+ *
+ *    struct auxiliary_device *my_aux_dev = my_aux_dev_alloc(xxx);
+ *
+ *    // Step 1:
+ *    my_aux_dev->name = MY_DEVICE_NAME;
+ *    my_aux_dev->id = my_unique_id_alloc(xxx);
+ *    my_aux_dev->dev.release = my_aux_dev_release;
+ *    my_aux_dev->dev.parent = my_dev;
+ *
+ *    // Step 2:
+ *    if (auxiliary_device_init(my_aux_dev))
+ *        goto fail;
+ *
+ *    // Step 3:
+ *    if (auxiliary_device_add(my_aux_dev)) {
+ *        auxiliary_device_uninit(my_aux_dev);
+ *        goto fail;
+ *    }
+ *
+ *    ...
+ *
+ *
+ * Unregistering an auxiliary_device is a two-step process to mirror the
+ * register process.  First call auxiliary_device_delete(), then call
+ * auxiliary_device_uninit().
+ *
+ * .. code-block:: c
+ *
+ *         auxiliary_device_delete(my_dev->my_aux_dev);
+ *         auxiliary_device_uninit(my_dev->my_aux_dev);
+ */
+#define AUXILIARY_NAME_SIZE 32
+#define AUXILIARY_MODULE_PREFIX "auxiliary:"
+
+struct auxiliary_device_id {
+	char name[AUXILIARY_NAME_SIZE];
+	kernel_ulong_t driver_data;
+};
+
+struct auxiliary_device {
+	struct device dev;
+	const char *name;
+	uint32_t id;
+};
+
+/**
+ * struct auxiliary_driver - Definition of an auxiliary bus driver
+ * @probe: Called when a matching device is added to the bus.
+ * @remove: Called when device is removed from the bus.
+ * @shutdown: Called at shut-down time to quiesce the device.
+ * @suspend: Called to put the device to sleep mode. Usually to a power state.
+ * @resume: Called to bring a device from sleep mode.
+ * @name: Driver name.
+ * @driver: Core driver structure.
+ * @id_table: Table of devices this driver should match on the bus.
+ *
+ * Auxiliary drivers follow the standard driver model convention, where
+ * discovery/enumeration is handled by the core, and drivers provide probe()
+ * and remove() methods. They support power management and shutdown
+ * notifications using the standard conventions.
+ *
+ * Auxiliary drivers register themselves with the bus by calling
+ * auxiliary_driver_register(). The id_table contains the match_names of
+ * auxiliary devices that a driver can bind with.
+ *
+ * .. code-block:: c
+ *
+ *         static const struct auxiliary_device_id my_auxiliary_id_table[] = {
+ *           { .name = "foo_mod.foo_dev" },
+ *                 {},
+ *         };
+ *
+ *         MODULE_DEVICE_TABLE(auxiliary, my_auxiliary_id_table);
+ *
+ *         struct auxiliary_driver my_drv = {
+ *                 .name = "myauxiliarydrv",
+ *                 .id_table = my_auxiliary_id_table,
+ *                 .probe = my_drv_probe,
+ *                 .remove = my_drv_remove
+ *         };
+ */
+struct auxiliary_driver {
+	int32_t (*probe)(struct auxiliary_device *auxdev,
+					 const struct auxiliary_device_id *id);
+	int32_t (*remove)(struct auxiliary_device *auxdev);
+	void (*shutdown)(struct auxiliary_device *auxdev);
+	int32_t (*suspend)(struct auxiliary_device *auxdev, pm_message_t state);
+	int32_t (*resume)(struct auxiliary_device *auxdev);
+	const char *name;
+	struct device_driver driver;
+	const struct auxiliary_device_id *id_table;
+};
+
+static inline void *auxiliary_get_drvdata(struct auxiliary_device *auxdev)
+{
+	return dev_get_drvdata(&auxdev->dev);
+}
+
+static inline void auxiliary_set_drvdata(struct auxiliary_device *auxdev,
+										 void *data)
+{
+	dev_set_drvdata(&auxdev->dev, data);
+}
+
+static inline struct auxiliary_device *to_auxiliary_dev(struct device *dev)
+{
+	return container_of(dev, struct auxiliary_device, dev);
+}
+
+static inline struct auxiliary_driver *
+to_auxiliary_drv(struct device_driver *drv)
+{
+	return container_of(drv, struct auxiliary_driver, driver);
+}
+
+int32_t auxiliary_device_init(struct auxiliary_device *auxdev);
+int32_t __auxiliary_device_add(struct auxiliary_device *auxdev,
+							   const char *modname);
+#define auxiliary_device_add(auxdev) \
+	__auxiliary_device_add(auxdev, KBUILD_MODNAME)
+
+static inline void auxiliary_device_uninit(struct auxiliary_device *auxdev)
+{
+	put_device(&auxdev->dev);
+}
+
+static inline void auxiliary_device_delete(struct auxiliary_device *auxdev)
+{
+	device_del(&auxdev->dev);
+}
+
+int32_t __auxiliary_driver_register(struct auxiliary_driver *auxdrv,
+									struct module *owner, const char *modname);
+#define auxiliary_driver_register(auxdrv) \
+	__auxiliary_driver_register(auxdrv, THIS_MODULE, KBUILD_MODNAME)
+
+void auxiliary_driver_unregister(struct auxiliary_driver *auxdrv);
+
+/**
+ * module_auxiliary_driver() - Helper macro for registering an auxiliary driver
+ * @__auxiliary_driver: auxiliary driver struct
+ *
+ * Helper macro for auxiliary drivers which do not do anything special in
+ * module init/exit. This eliminates a lot of boilerplate. Each module may only
+ * use this macro once, and calling it replaces module_init() and module_exit()
+ *
+ * .. code-block:: c
+ *
+ *    module_auxiliary_driver(my_drv);
+ */
+#define module_auxiliary_driver(__auxiliary_driver)              \
+	module_driver(__auxiliary_driver, auxiliary_driver_register, \
+				  auxiliary_driver_unregister)
+
+#ifdef HAVE_LINUX_DEVICE_BUS_H
+struct auxiliary_device *
+auxiliary_find_device(struct device *start, const void *data,
+					  int32_t (*match)(struct device *dev, const void *data));
+#else
+#ifdef HAVE_BUS_FIND_DEVICE_GET_CONST
+struct auxiliary_device *
+auxiliary_find_device(struct device *start, const void *data,
+					  int32_t (*match)(struct device *dev, const void *data));
+#else
+struct auxiliary_device *
+auxiliary_find_device(struct device *start, void *data,
+					  int32_t (*match)(struct device *dev, void *data));
+#endif /* HAVE_BUS_FIND_DEVICE_GET_CONST */
+#endif /* HAVE_LINUX_DEVICE_BUS_H */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _AUXILIARY_BUS_H_ */
diff --git a/src/net/include/linux/dinghai/device.h b/src/net/include/linux/dinghai/device.h
old mode 100755
new mode 100644
index 651a5ead3d3d3a5d33fa45bfc6af4ea3766f3a38..16e5291bb197a7eb3f2f8d45b94e6eb2a96e3f94
--- a/src/net/include/linux/dinghai/device.h
+++ b/src/net/include/linux/dinghai/device.h
@@ -1,155 +1,168 @@
-#ifndef DINGHAI_DEVICE_H
-#define DINGHAI_DEVICE_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/types.h>
-
-/* helper macros */
-#define __dh_nullp(typ) ((struct dh_ifc_##typ##_bits *)0)
-#define __dh_bit_sz(typ, fld) sizeof(__dh_nullp(typ)->fld)
-#define __dh_bit_off(typ, fld) (offsetof(struct dh_ifc_##typ##_bits, fld))
-#define __dh_16_off(typ, fld) (__dh_bit_off(typ, fld) / 16)
-#define __dh_dw_off(typ, fld) (__dh_bit_off(typ, fld) / 32)
-#define __dh_64_off(typ, fld) (__dh_bit_off(typ, fld) / 64)
-#define __dh_16_bit_off(typ, fld) (16 - __dh_bit_sz(typ, fld) - (__dh_bit_off(typ, fld) & 0xf))
-#define __dh_dw_bit_off(typ, fld) (32 - __dh_bit_sz(typ, fld) - (__dh_bit_off(typ, fld) & 0x1f))
-#define __dh_mask(typ, fld) ((u32)((1ull << __dh_bit_sz(typ, fld)) - 1))
-#define __dh_dw_mask(typ, fld) (__dh_mask(typ, fld) << __dh_dw_bit_off(typ, fld))
-#define __dh_mask16(typ, fld) ((u16)((1ull << __dh_bit_sz(typ, fld)) - 1))
-#define __dh_16_mask(typ, fld) (__dh_mask16(typ, fld) << __dh_16_bit_off(typ, fld))
-#define __dh_st_sz_bits(typ) sizeof(struct dh_ifc_##typ##_bits)
-
-#define DH_FLD_SZ_BYTES(typ, fld) (__dh_bit_sz(typ, fld) / 8)
-#define DH_ST_SZ_BYTES(typ) (sizeof(struct dh_ifc_##typ##_bits) / 8)
-#define DH_ST_SZ_DW(typ) (sizeof(struct dh_ifc_##typ##_bits) / 32)
-#define DH_ST_SZ_QW(typ) (sizeof(struct dh_ifc_##typ##_bits) / 64)
-#define DH_UN_SZ_BYTES(typ) (sizeof(union dh_ifc_##typ##_bits) / 8)
-#define DH_UN_SZ_DW(typ) (sizeof(union dh_ifc_##typ##_bits) / 32)
-#define DH_BYTE_OFF(typ, fld) (__dh_bit_off(typ, fld) / 8)
-#define DH_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + DH_BYTE_OFF(typ, fld)))
-
-/* insert a value to a struct */
-#define DH_SET(typ, p, fld, v) do { \
-    u32 _v = v; \
-    BUILD_BUG_ON(__dh_st_sz_bits(typ) % 32);             \
-    *((__be32 *)(p) + __dh_dw_off(typ, fld)) = \
-    cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __dh_dw_off(typ, fld))) & \
-             (~__dh_dw_mask(typ, fld))) | (((_v) & __dh_mask(typ, fld)) \
-             << __dh_dw_bit_off(typ, fld))); \
-} while (0)
-
-#define DH_ARRAY_SET(typ, p, fld, idx, v) do { \
-    BUILD_BUG_ON(__dh_bit_off(typ, fld) % 32); \
-    DH_SET(typ, p, fld[idx], v); \
-} while (0)
-
-#define DH_SET_TO_ONES(typ, p, fld) do { \
-    BUILD_BUG_ON(__dh_st_sz_bits(typ) % 32);             \
-    *((__be32 *)(p) + __dh_dw_off(typ, fld)) = \
-    cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __dh_dw_off(typ, fld))) & \
-             (~__dh_dw_mask(typ, fld))) | ((__dh_mask(typ, fld)) \
-             << __dh_dw_bit_off(typ, fld))); \
-} while (0)
-
-#define DH_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) + \
-__dh_dw_off(typ, fld))) >> __dh_dw_bit_off(typ, fld)) & \
-__dh_mask(typ, fld))
-
-#define DH_GET_PR(typ, p, fld) ({ \
-    u32 ___t = DH_GET(typ, p, fld); \
-    pr_debug(#fld " = 0x%x\n", ___t); \
-    ___t; \
-})
-
-#define __DH_SET64(typ, p, fld, v) do { \
-    BUILD_BUG_ON(__dh_bit_sz(typ, fld) != 64); \
-    *((__be64 *)(p) + __dh_64_off(typ, fld)) = cpu_to_be64(v); \
-} while (0)
-
-#define DH_SET64(typ, p, fld, v) do { \
-    BUILD_BUG_ON(__dh_bit_off(typ, fld) % 64); \
-    __DH_SET64(typ, p, fld, v); \
-} while (0)
-
-#define DH_ARRAY_SET64(typ, p, fld, idx, v) do { \
-    BUILD_BUG_ON(__dh_bit_off(typ, fld) % 64); \
-    __DH_SET64(typ, p, fld[idx], v); \
-} while (0)
-
-#define DH_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __dh_64_off(typ, fld)))
-
-#define DH_GET64_PR(typ, p, fld) ({ \
-    u64 ___t = DH_GET64(typ, p, fld); \
-    pr_debug(#fld " = 0x%llx\n", ___t); \
-    ___t; \
-})
-
-#define DH_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) + \
-__dh_16_off(typ, fld))) >> __dh_16_bit_off(typ, fld)) & \
-__dh_mask16(typ, fld))
-
-#define DH_SET16(typ, p, fld, v) do { \
-    u16 _v = v; \
-    BUILD_BUG_ON(__dh_st_sz_bits(typ) % 16);  \
-    *((__be16 *)(p) + __dh_16_off(typ, fld)) = \
-    cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __dh_16_off(typ, fld))) & \
-             (~__dh_16_mask(typ, fld))) | (((_v) & __dh_mask16(typ, fld)) \
-             << __dh_16_bit_off(typ, fld))); \
-} while (0)
-
-/* Big endian getters */
-#define DH_GET64_BE(typ, p, fld) (*((__be64 *)(p) + \
-    __dh_64_off(typ, fld)))
-
-#define DH_GET_BE(type_t, typ, p, fld) ({                           \
-        type_t tmp;                                                 \
-        switch (sizeof(tmp)) {                                      \
-        case sizeof(u8):                                            \
-            tmp = (__force type_t)DH_GET(typ, p, fld);              \
-            break;                                                  \
-        case sizeof(u16):                                           \
-            tmp = (__force type_t)cpu_to_be16(DH_GET(typ, p, fld)); \
-            break;                                                  \
-        case sizeof(u32):                                           \
-            tmp = (__force type_t)cpu_to_be32(DH_GET(typ, p, fld)); \
-            break;                                                  \
-        case sizeof(u64):                                           \
-            tmp = (__force type_t)DH_GET64_BE(typ, p, fld);         \
-            break;                                                  \
-            }                                                       \
-        tmp;                                                        \
-        })
-
-enum dh_cap_type {
-    DH_CAP_GENERAL = 0,
-};
-/* GET Dev Caps macros */
-#define DH_CAP_GEN(mdev, cap) \
-    DH_GET(cmd_hca_cap, mdev->caps.hca[DH_CAP_GENERAL]->cur, cap)
-
-#define DH_CAP_GEN_64(mdev, cap) \
-    DH_GET64(cmd_hca_cap, mdev->caps.hca[DH_CAP_GENERAL]->cur, cap)
-
-#define DH_CAP_GEN_MAX(mdev, cap) \
-    DH_GET(cmd_hca_cap, mdev->caps.hca[DH_CAP_GENERAL]->max, cap)
-
-
-
-
-enum dh_event_queue_type {
-   DH_EVENT_QUEUE_TYPE_SAMPLE,
-   DH_EVENT_QUEUE_TYPE_RISCV
-};
-
-struct dh_mpf_priv {
-
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef DINGHAI_DEVICE_H
+#define DINGHAI_DEVICE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/types.h>
+
+/* helper macros */
+#define __dh_nullp(typ) ((struct dh_ifc_##typ##_bits *)0)
+#define __dh_bit_sz(typ, fld) sizeof(__dh_nullp(typ)->fld)
+#define __dh_bit_off(typ, fld) (offsetof(struct dh_ifc_##typ##_bits, fld))
+#define __dh_16_off(typ, fld) (__dh_bit_off(typ, fld) / 16)
+#define __dh_dw_off(typ, fld) (__dh_bit_off(typ, fld) / 32)
+#define __dh_64_off(typ, fld) (__dh_bit_off(typ, fld) / 64)
+#define __dh_16_bit_off(typ, fld) \
+	(16 - __dh_bit_sz(typ, fld) - (__dh_bit_off(typ, fld) & 0xf))
+#define __dh_dw_bit_off(typ, fld) \
+	(32 - __dh_bit_sz(typ, fld) - (__dh_bit_off(typ, fld) & 0x1f))
+#define __dh_mask(typ, fld) ((u32)((1ull << __dh_bit_sz(typ, fld)) - 1))
+#define __dh_dw_mask(typ, fld) \
+	(__dh_mask(typ, fld) << __dh_dw_bit_off(typ, fld))
+#define __dh_mask16(typ, fld) ((u16)((1ull << __dh_bit_sz(typ, fld)) - 1))
+#define __dh_16_mask(typ, fld) \
+	(__dh_mask16(typ, fld) << __dh_16_bit_off(typ, fld))
+#define __dh_st_sz_bits(typ) sizeof(struct dh_ifc_##typ##_bits)
+
+#define DH_FLD_SZ_BYTES(typ, fld) (__dh_bit_sz(typ, fld) / 8)
+#define DH_ST_SZ_BYTES(typ) (sizeof(struct dh_ifc_##typ##_bits) / 8)
+#define DH_ST_SZ_DW(typ) (sizeof(struct dh_ifc_##typ##_bits) / 32)
+#define DH_ST_SZ_QW(typ) (sizeof(struct dh_ifc_##typ##_bits) / 64)
+#define DH_UN_SZ_BYTES(typ) (sizeof(union dh_ifc_##typ##_bits) / 8)
+#define DH_UN_SZ_DW(typ) (sizeof(union dh_ifc_##typ##_bits) / 32)
+#define DH_BYTE_OFF(typ, fld) (__dh_bit_off(typ, fld) / 8)
+#define DH_ADDR_OF(typ, p, fld) \
+	((void *)((uint8_t *)(p) + DH_BYTE_OFF(typ, fld)))
+
+/* insert a value to a struct */
+#define DH_SET(typ, p, fld, v)                                              \
+	do {                                                                    \
+		u32 _v = v;                                                         \
+		BUILD_BUG_ON(__dh_st_sz_bits(typ) % 32);                            \
+		*((__be32 *)(p) + __dh_dw_off(typ, fld)) = cpu_to_be32(             \
+				(be32_to_cpu(*((__be32 *)(p) + __dh_dw_off(typ, fld))) &    \
+				 (~__dh_dw_mask(typ, fld))) |                               \
+				(((_v)&__dh_mask(typ, fld)) << __dh_dw_bit_off(typ, fld))); \
+	} while (0)
+
+#define DH_ARRAY_SET(typ, p, fld, idx, v)          \
+	do {                                           \
+		BUILD_BUG_ON(__dh_bit_off(typ, fld) % 32); \
+		DH_SET(typ, p, fld[idx], v);               \
+	} while (0)
+
+#define DH_SET_TO_ONES(typ, p, fld)                                      \
+	do {                                                                 \
+		BUILD_BUG_ON(__dh_st_sz_bits(typ) % 32);                         \
+		*((__be32 *)(p) + __dh_dw_off(typ, fld)) = cpu_to_be32(          \
+				(be32_to_cpu(*((__be32 *)(p) + __dh_dw_off(typ, fld))) & \
+				 (~__dh_dw_mask(typ, fld))) |                            \
+				((__dh_mask(typ, fld)) << __dh_dw_bit_off(typ, fld)));   \
+	} while (0)
+
+#define DH_GET(typ, p, fld)                                    \
+	((be32_to_cpu(*((__be32 *)(p) + __dh_dw_off(typ, fld))) >> \
+	  __dh_dw_bit_off(typ, fld)) &                             \
+	 __dh_mask(typ, fld))
+
+#define DH_GET_PR(typ, p, fld)            \
+	({                                    \
+		u32 ___t = DH_GET(typ, p, fld);   \
+		pr_debug(#fld " = 0x%x\n", ___t); \
+		___t;                             \
+	})
+
+#define __DH_SET64(typ, p, fld, v)                                 \
+	do {                                                           \
+		BUILD_BUG_ON(__dh_bit_sz(typ, fld) != 64);                 \
+		*((__be64 *)(p) + __dh_64_off(typ, fld)) = cpu_to_be64(v); \
+	} while (0)
+
+#define DH_SET64(typ, p, fld, v)                   \
+	do {                                           \
+		BUILD_BUG_ON(__dh_bit_off(typ, fld) % 64); \
+		__DH_SET64(typ, p, fld, v);                \
+	} while (0)
+
+#define DH_ARRAY_SET64(typ, p, fld, idx, v)        \
+	do {                                           \
+		BUILD_BUG_ON(__dh_bit_off(typ, fld) % 64); \
+		__DH_SET64(typ, p, fld[idx], v);           \
+	} while (0)
+
+#define DH_GET64(typ, p, fld) \
+	be64_to_cpu(*((__be64 *)(p) + __dh_64_off(typ, fld)))
+
+#define DH_GET64_PR(typ, p, fld)            \
+	({                                      \
+		u64 ___t = DH_GET64(typ, p, fld);   \
+		pr_debug(#fld " = 0x%llx\n", ___t); \
+		___t;                               \
+	})
+
+#define DH_GET16(typ, p, fld)                                  \
+	((be16_to_cpu(*((__be16 *)(p) + __dh_16_off(typ, fld))) >> \
+	  __dh_16_bit_off(typ, fld)) &                             \
+	 __dh_mask16(typ, fld))
+
+#define DH_SET16(typ, p, fld, v)                                              \
+	do {                                                                      \
+		u16 _v = v;                                                           \
+		BUILD_BUG_ON(__dh_st_sz_bits(typ) % 16);                              \
+		*((__be16 *)(p) + __dh_16_off(typ, fld)) = cpu_to_be16(               \
+				(be16_to_cpu(*((__be16 *)(p) + __dh_16_off(typ, fld))) &      \
+				 (~__dh_16_mask(typ, fld))) |                                 \
+				(((_v)&__dh_mask16(typ, fld)) << __dh_16_bit_off(typ, fld))); \
+	} while (0)
+
+/* Big endian getters */
+#define DH_GET64_BE(typ, p, fld) (*((__be64 *)(p) + __dh_64_off(typ, fld)))
+
+#define DH_GET_BE(type_t, typ, p, fld)                              \
+	({                                                              \
+		type_t tmp;                                                 \
+		switch (sizeof(tmp)) {                                      \
+		case sizeof(u8):                                            \
+			tmp = (__force type_t)DH_GET(typ, p, fld);              \
+			break;                                                  \
+		case sizeof(u16):                                           \
+			tmp = (__force type_t)cpu_to_be16(DH_GET(typ, p, fld)); \
+			break;                                                  \
+		case sizeof(u32):                                           \
+			tmp = (__force type_t)cpu_to_be32(DH_GET(typ, p, fld)); \
+			break;                                                  \
+		case sizeof(u64):                                           \
+			tmp = (__force type_t)DH_GET64_BE(typ, p, fld);         \
+			break;                                                  \
+		}                                                           \
+		tmp;                                                        \
+	})
+
+enum dh_cap_type {
+	DH_CAP_GENERAL = 0,
+};
+/* GET Dev Caps macros */
+#define DH_CAP_GEN(mdev, cap) \
+	DH_GET(cmd_hca_cap, mdev->caps.hca[DH_CAP_GENERAL]->cur, cap)
+
+#define DH_CAP_GEN_64(mdev, cap) \
+	DH_GET64(cmd_hca_cap, mdev->caps.hca[DH_CAP_GENERAL]->cur, cap)
+
+#define DH_CAP_GEN_MAX(mdev, cap) \
+	DH_GET(cmd_hca_cap, mdev->caps.hca[DH_CAP_GENERAL]->max, cap)
+
+enum dh_event_queue_type {
+	DH_EVENT_QUEUE_TYPE_SAMPLE,
+	DH_EVENT_QUEUE_TYPE_RISCV
+};
+
+struct dh_mpf_priv {
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/include/linux/dinghai/devlink.h b/src/net/include/linux/dinghai/devlink.h
old mode 100755
new mode 100644
index 1801a581dad2dd65266d5f04d4d224037770eae0..44fa949ff5280e8657cc754fa573cf4402a21571
--- a/src/net/include/linux/dinghai/devlink.h
+++ b/src/net/include/linux/dinghai/devlink.h
@@ -1,32 +1,34 @@
-#ifndef __ZXDH_DEVLINK_H__
-#define __ZXDH_DEVLINK_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <net/devlink.h>
-#include <linux/dinghai/driver.h>
-#include <linux/types.h>
-
-struct devlink *zxdh_devlink_alloc(struct device *dev, struct devlink_ops *dh_devlink_ops, size_t priv_size);
-void zxdh_devlink_free(struct devlink *devlink);
-
-#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
-int32_t zxdh_devlink_register(struct devlink *devlink);
-#else
-int32_t zxdh_devlink_register(struct devlink *devlink, struct device *dev);
-#endif
-
-void zxdh_devlink_unregister(struct devlink *devlink);
-
-static inline struct net *dh_core_net(struct dh_core_dev *dev)
-{
-    return devlink_net(priv_to_devlink(dev));
-}
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef __ZXDH_DEVLINK_H__
+#define __ZXDH_DEVLINK_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <net/devlink.h>
+#include <linux/dinghai/driver.h>
+#include <linux/types.h>
+
+struct devlink *zxdh_devlink_alloc(struct device *dev,
+								   struct devlink_ops *dh_devlink_ops,
+								   size_t priv_size);
+void zxdh_devlink_free(struct devlink *devlink);
+
+#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
+int32_t zxdh_devlink_register(struct devlink *devlink);
+#else
+int32_t zxdh_devlink_register(struct devlink *devlink, struct device *dev);
+#endif
+
+void zxdh_devlink_unregister(struct devlink *devlink);
+
+static inline struct net *dh_core_net(struct dh_core_dev *dev)
+{
+	return devlink_net(priv_to_devlink(dev));
+}
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/include/linux/dinghai/dh_cmd.h b/src/net/include/linux/dinghai/dh_cmd.h
index 29779fc326ccd62fa2341c198943a280b1ce826d..068835a5d8bd59e49876f386710c25923f67df3f 100644
--- a/src/net/include/linux/dinghai/dh_cmd.h
+++ b/src/net/include/linux/dinghai/dh_cmd.h
@@ -8,181 +8,170 @@ extern "C" {
 #include <linux/netdevice.h>
 #include <linux/workqueue.h>
 
-
 #define INVALID_NUM 0xff
-#define ZXDH_MPF_PCIEID       0x800
-#define ZXDH_NET_ACK_OK       0
-#define RISCV_MAC_OK          0xaa
-#define BAR_MSG_REPS_OK       0xff
-#define COMMON_TBL_OK         0xaa
-#define RISCV_DEBUG_OK        0xaa
-#define PCIEID_PF_ID_MASK    (0x0700)
-#define PCIEID_PF_ID_OFFSET     (8)
+#define ZXDH_MPF_PCIEID 0x800
+#define ZXDH_NET_MAX_ACK_LEN 600
+#define ZXDH_NET_ACK_OK 0
+#define RISCV_MAC_OK 0xaa
+#define BAR_MSG_REPS_OK 0xff
+#define COMMON_TBL_OK 0xaa
+#define RISCV_DEBUG_OK 0xaa
+#define PCIEID_PF_ID_MASK (0x0700)
+#define PCIEID_PF_ID_OFFSET (8)
 
-#define FIND_PF_PCIE_ID(value)                    ((value & 0xff00) | BIT(11))
-#define FIND_VF_PCIE_ID(pf_pcie_id, vf_id)        ((pf_pcie_id & (~BIT(11))) | (vf_id))
-#define FIND_PF_ID(pf_pcie_id)                   ((pf_pcie_id & PCIEID_PF_ID_MASK) >> PCIEID_PF_ID_OFFSET)
-#define GET_FUNC_NO(pf_no, vf_idx)                ((pf_no & 0xF) | ((vf_idx & 0xFF) << 8))
+#define FIND_PF_PCIE_ID(value) ((value & 0xff00) | BIT(11))
+#define FIND_VF_PCIE_ID(pf_pcie_id, vf_id) ((pf_pcie_id & (~BIT(11))) | (vf_id))
+#define FIND_PF_ID(pf_pcie_id) \
+	((pf_pcie_id & PCIEID_PF_ID_MASK) >> PCIEID_PF_ID_OFFSET)
+#define GET_FUNC_NO(pf_no, vf_idx) ((pf_no & 0xF) | ((vf_idx & 0xFF) << 8))
 
 #define PFVF_FLAG_OFFSET 11 // 用于判断pcie_id的第11位为0或1
 
-typedef enum
-{
-    MODULE_DBG = 0,    /* 中断测试*/
-    MODULE_TBL,        /* 资源表交互*/
-    MODULE_MSIX,       /* Msix配置*/
-    MODULE_SDA,        /* Sda消息*/
-    MODULE_RDMA,       /* Rdma调试*/
-    MODULE_DEMO,       /* 通路测试*/
-    MODULE_SMMU,       /* Smmu调试*/
-    MODULE_MAC,        /* MAC相关*/
-    MODULE_VDPA,       /* vdpa热迁移*/
-    MODULE_VQM,        /* vqm消息*/
-    MODULE_MSGQ,
-    MODULE_VPORT_GET,  /* 获取vport接口*/
-    MODULE_BDF_GET,    /* 获取bdf接口*/
-    MODULE_RISC_READY, /* risc ready信号*/
-    MODULE_REVERSE,    /* 字节流取反*/
-    MODULE_NVME,       /* NVME调试*/
-    MODULE_NPSDK,      /* Np配表*/
-    MODULE_TOD,        /* UART通信*/
-    MODULE_VF_BAR_MSG_TO_PF,  /* VF发送给PF的消息 */
-    MODULE_PF_BAR_MSG_TO_VF,  /* PF发送给VF的消息 */
-    MODULE_DEBUG = 20,      /* 调用debug接口 */
-    MODULE_PPS = 23,        /*pps中断相关消息*/
-    MODULE_VIRTIO = 25,
-    MODULE_FLASH = 32, /* 读取flash信息 */
-    MODULE_OFFSET_GET = 33,
-    MODULE_CFG_MAC = 34,
-    MODULE_PHYPORT_QUERY = 37,  /* BOND 获取phyport*/
-    MODULE_DHTOOL = 39,    /*dhtool，riscv发送给AUX层的消息，将其转发给user*/
-    MODULE_RESET_MSG = 40, /* host复位消息的ID号 */
-    MODULE_PF_TIMER_TO_RISC_MSG = 41, /* server rsicv time */
-    MODULE_LOGIN_CTRL = 43, /* 控制riscv上sshd守护进程开启和关闭*/
-    MODULE_PCIE_RES_QUERY = 52, /* pcie资源查询*/
-    MSG_MODULE_NUM = 100,
+typedef enum {
+	MODULE_DBG = 0, /* 中断测试*/
+	MODULE_TBL, /* 资源表交互*/
+	MODULE_MSIX, /* Msix配置*/
+	MODULE_SDA, /* Sda消息*/
+	MODULE_RDMA, /* Rdma调试*/
+	MODULE_DEMO, /* 通路测试*/
+	MODULE_SMMU, /* Smmu调试*/
+	MODULE_MAC, /* MAC相关*/
+	MODULE_VDPA, /* vdpa热迁移*/
+	MODULE_VQM, /* vqm消息*/
+	MODULE_MSGQ,
+	MODULE_VPORT_GET, /* 获取vport接口*/
+	MODULE_BDF_GET, /* 获取bdf接口*/
+	MODULE_RISC_READY, /* risc ready信号*/
+	MODULE_REVERSE, /* 字节流取反*/
+	MODULE_NVME, /* NVME调试*/
+	MODULE_NPSDK, /* Np配表*/
+	MODULE_TOD, /* UART通信*/
+	MODULE_VF_BAR_MSG_TO_PF, /* VF发送给PF的消息 */
+	MODULE_PF_BAR_MSG_TO_VF, /* PF发送给VF的消息 */
+	MODULE_DEBUG = 20, /* 调用debug接口 */
+	MODULE_PPS = 23, /*pps中断相关消息*/
+	MODULE_VIRTIO = 25,
+	MODULE_FLASH = 32, /* 读取flash信息 */
+	MODULE_OFFSET_GET = 33,
+	MODULE_CFG_MAC = 34,
+	MODULE_PHYPORT_QUERY = 37, /* BOND 获取phyport*/
+	MODULE_DHTOOL = 39, /*dhtool，riscv发送给AUX层的消息，将其转发给user*/
+	MODULE_RESET_MSG = 40, /* host复位消息的ID号 */
+	MODULE_PF_TIMER_TO_RISC_MSG = 41, /* server rsicv time */
+	MODULE_LOGIN_CTRL = 43, /* 控制riscv上sshd守护进程开启和关闭*/
+	MSG_MODULE_NUM = 100,
 } MSG_MODULE_ID;
 
-
 /* 消息端*/
-typedef enum BAR_DRIVER_TYPE
-{
-    MSG_CHAN_END_MPF = 0,
-    MSG_CHAN_END_PF,
-    MSG_CHAN_END_VF,
-    MSG_CHAN_END_RISC,
-    MSG_CHAN_END_ERR,
+typedef enum BAR_DRIVER_TYPE {
+	MSG_CHAN_END_MPF = 0,
+	MSG_CHAN_END_PF,
+	MSG_CHAN_END_VF,
+	MSG_CHAN_END_RISC,
+	MSG_CHAN_END_ERR,
 } BAR_DRIVER_TYPE;
 
-#define BDF_ECAM(bus, devid, func)   ((bus & 0xff) << 8) | (func & 0x07) | ((devid & 0x1f) << 3)
+#define BDF_ECAM(bus, devid, func) \
+	(((bus & 0xff) << 8) | (func & 0x07) | ((devid & 0x1f) << 3))
 
 /* bar通道错误码*/
-typedef enum BAR_MSG_RTN
-{
-    BAR_MSG_OK = 0,
-    BAR_MSG_ERR_NULL,              /* 空指针*/
-    BAR_MSG_ERR_TYPE,              /* 消息类型异常 */
-    BAR_MSG_ERR_MODULE ,           /* 模块ID异常 */
-    BAR_MSG_ERR_BODY_NULL,         /* 消息体异常 */
-    BAR_MSG_ERR_LEN,               /* 消息长度异常 */
-    BAR_MSG_ERR_TIME_OUT,          /* 消息发送超长 */
-    BAR_MSG_ERR_NOT_READY,         /* 消息发送条件异常，BUF不可以用*/
-    BAR_MEG_ERR_NULL_FUNC,         /* 空的接收处理函数指针*/
-    BAR_MSG_ERR_REPEAT_REGISTER,   /* 模块重复注册*/
-    BAR_MSG_ERR_UNGISTER,          /* 重复解注册*/
-    BAR_MSG_ERR_NULL_PARA,         /* 发送接口参数界结构体指针为空*/
-    BAR_MSG_ERR_REPSBUFF_LEN,      /* reps_buff的长度太短*/
-    BAR_MSG_ERR_MODULE_NOEXIST,    /*查找不到该模块对应的消息处理函数*/
-    BAR_MSG_ERR_VIRTADDR_NULL,     /*发送接口传入参数中的虚拟地址为空*/
-    BAR_MSG_ERR_REPLY,             /**< seq_id匹配失败>**/
-    BAR_MSG_ERR_MSGID,             /**< seq_id申请失败>**/
-    BAR_MSG_ERR_MPF_NOT_SCANED,    /**< MPF通道不可用>**/
-    BAR_MSG_ERR_USR_RET_ERR,       /**< 处理函数返回值错误>**/
-    BAR_MSG_ERR_ERR_PCIEID,        /**< pcieID错误>**/
-    BAR_MSG_ERR_NOT_MATCH,
+typedef enum BAR_MSG_RTN {
+	BAR_MSG_OK = 0,
+	BAR_MSG_ERR_NULL, /* 空指针*/
+	BAR_MSG_ERR_TYPE, /* 消息类型异常 */
+	BAR_MSG_ERR_MODULE, /* 模块ID异常 */
+	BAR_MSG_ERR_BODY_NULL, /* 消息体异常 */
+	BAR_MSG_ERR_LEN, /* 消息长度异常 */
+	BAR_MSG_ERR_TIME_OUT, /* 消息发送超长 */
+	BAR_MSG_ERR_NOT_READY, /* 消息发送条件异常，BUF不可以用*/
+	BAR_MEG_ERR_NULL_FUNC, /* 空的接收处理函数指针*/
+	BAR_MSG_ERR_REPEAT_REGISTER, /* 模块重复注册*/
+	BAR_MSG_ERR_UNGISTER, /* 重复解注册*/
+	BAR_MSG_ERR_NULL_PARA, /* 发送接口参数界结构体指针为空*/
+	BAR_MSG_ERR_REPSBUFF_LEN, /* reps_buff的长度太短*/
+	BAR_MSG_ERR_MODULE_NOEXIST, /*查找不到该模块对应的消息处理函数*/
+	BAR_MSG_ERR_VIRTADDR_NULL, /*发送接口传入参数中的虚拟地址为空*/
+	BAR_MSG_ERR_REPLY, /**< seq_id匹配失败>**/
+	BAR_MSG_ERR_MSGID, /**< seq_id申请失败>**/
+	BAR_MSG_ERR_MPF_NOT_SCANED, /**< MPF通道不可用>**/
+	BAR_MSG_ERR_USR_RET_ERR, /**< 处理函数返回值错误>**/
+	BAR_MSG_ERR_ERR_PCIEID, /**< pcieID错误>**/
+	BAR_MSG_ERR_NOT_MATCH,
 } BAR_MSG_RTN;
 
-enum pciebar_layout_type
-{
-    URI_VQM         = 0,
-    URI_SPINLOCK    = 1,
-    URI_FWCAP       = 2,
-    URI_FWSHR       = 3,
-    URI_DRS_SEC     = 4,
-    URI_RSV         = 5,
-    URI_CTRLCH      = 6,
-    URI_1588        = 7,
-    URI_QBV         = 8,
-    URI_MACPCS      = 9,
-    URI_RDMA        = 10,
-/* DEBUG PF */
-    URI_MNP         = 11,
-    URI_MSPM        = 12,
-    URI_MVQM        = 13,
-    URI_MDPI        = 14,
-    URI_NP          = 15,
-/* END DEBUG PF */
-    URI_MAX,
+enum pciebar_layout_type {
+	URI_VQM = 0,
+	URI_SPINLOCK = 1,
+	URI_FWCAP = 2,
+	URI_FWSHR = 3,
+	URI_DRS_SEC = 4,
+	URI_RSV = 5,
+	URI_CTRLCH = 6,
+	URI_1588 = 7,
+	URI_QBV = 8,
+	URI_MACPCS = 9,
+	URI_RDMA = 10,
+	/* DEBUG PF */
+	URI_MNP = 11,
+	URI_MSPM = 12,
+	URI_MVQM = 13,
+	URI_MDPI = 14,
+	URI_NP = 15,
+	/* END DEBUG PF */
+	URI_MAX,
 };
 
-typedef enum
-{
-    BAR_MSG_MSIX_FROM_VF = 0,
-    BAR_MSG_MSIX_FROM_MPF,
-    BAR_MSG_MSIX_FROM_RISCV,
-    BAR_MSG_MSIX_NUM_MAX
+typedef enum {
+	BAR_MSG_MSIX_FROM_VF = 0,
+	BAR_MSG_MSIX_FROM_MPF,
+	BAR_MSG_MSIX_FROM_RISCV,
+	BAR_MSG_MSIX_NUM_MAX
 } bar_msg_msix_irq_type;
 
 /* msix消息参数结构体*/
-struct msix_para
-{
-    uint16_t vector_risc;
-    uint16_t vector_pfvf;
-    uint16_t vector_mpf;
-    uint16_t driver_type;
-    uint16_t pcie_id;
-    struct pci_dev *pdev;
-    uint64_t virt_addr;
+struct msix_para {
+	uint16_t vector_risc;
+	uint16_t vector_pfvf;
+	uint16_t vector_mpf;
+	uint16_t driver_type;
+	uint16_t pcie_id;
+	struct pci_dev *pdev;
+	uint64_t virt_addr;
 };
 
-struct bar_offset_params
-{
-    uint64_t virt_addr;
-    uint16_t pcie_id;
-    uint16_t type;
+struct bar_offset_params {
+	uint64_t virt_addr;
+	uint16_t pcie_id;
+	uint16_t type;
 };
-struct bar_offset_res
-{
-    uint32_t bar_offset;
-    uint32_t bar_length;
+struct bar_offset_res {
+	uint32_t bar_offset;
+	uint32_t bar_length;
 };
 
-struct zxdh_pci_bar_msg
-{
-    uint64_t virt_addr;               /**< 4k空间地址, 若src为MPF该参数不生效>**/
-    void *payload_addr;               /**< 消息净荷地址>**/
-    uint16_t payload_len;             /**< 消息净荷长度>**/
-    uint16_t emec;                    /**< 消息紧急类型>**/
-    uint16_t src;                     /**< 消息发送源，参考BAR_DRIVER_TYPE>**/
-    uint16_t dst;                     /**< 消息接收者，参考BAR_DRIVER_TYPE>**/
-    uint32_t event_id;                /**< 事件id>**/
-    uint16_t src_pcieid;              /**< 源  pcie_id>**/
-    uint16_t dst_pcieid;              /**< 目的pcie_id>**/
+struct zxdh_pci_bar_msg {
+	uint64_t virt_addr; /**< 4k空间地址, 若src为MPF该参数不生效>**/
+	void *payload_addr; /**< 消息净荷地址>**/
+	uint16_t payload_len; /**< 消息净荷长度>**/
+	uint16_t emec; /**< 消息紧急类型>**/
+	uint16_t src; /**< 消息发送源，参考BAR_DRIVER_TYPE>**/
+	uint16_t dst; /**< 消息接收者，参考BAR_DRIVER_TYPE>**/
+	uint32_t event_id; /**< 事件id>**/
+	uint16_t src_pcieid; /**< 源  pcie_id>**/
+	uint16_t dst_pcieid; /**< 目的pcie_id>**/
 };
 
-struct link_info_struct
-{
-    uint32_t speed;
-    uint32_t autoneg_enable;
-    uint32_t supported_speed_modes;
-    uint32_t advertising_speed_modes;
-    uint8_t  duplex;
+struct link_info_struct {
+	uint32_t speed;
+	uint32_t autoneg_enable;
+	uint32_t supported_speed_modes;
+	uint32_t advertising_speed_modes;
+	uint8_t duplex;
 };
 
-struct zxdh_msg_recviver_mem
-{
-    void *recv_buffer;                /**< 消息接收缓存>**/
-    uint16_t buffer_len;              /**< 消息缓存长度>**/
+struct zxdh_msg_recviver_mem {
+	void *recv_buffer; /**< 消息接收缓存>**/
+	uint16_t buffer_len; /**< 消息缓存长度>**/
 };
 
 /**
@@ -193,7 +182,9 @@ struct zxdh_msg_recviver_mem
  * @reps_len: 回复消息长度
  * @dev: 私有数据
  */
-typedef int (*zxdh_bar_chan_msg_recv_callback)(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev);
+typedef int (*zxdh_bar_chan_msg_recv_callback)(void *pay_load, uint16_t len,
+											   void *reps_buffer,
+											   uint16_t *reps_len, void *dev);
 
 /**
  * zxdh_bar_chan_sync_msg_send - 通过PCIE BAR空间发送同步消息
@@ -201,7 +192,17 @@ typedef int (*zxdh_bar_chan_msg_recv_callback)(void *pay_load, uint16_t len, voi
  * @result: 消息结果反馈
  * @return: 0 成功，其他失败
  */
-int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in, struct zxdh_msg_recviver_mem *result);
+int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in,
+								struct zxdh_msg_recviver_mem *result);
+
+/**
+ * zxdh_bar_chan_async_msg_send - 通过PCIE BAR空间发送异步消息
+ * @in: 消息发送信息
+ * @result: 消息结果反馈
+ * @return: 0 成功，其他失败
+ */
+int zxdh_bar_chan_async_msg_send(struct zxdh_pci_bar_msg *in,
+								 struct zxdh_msg_recviver_mem *result);
 
 /**
  * zxdh_bar_chan_msg_recv_register - PCIE BAR空间消息方式，注册消息接收回调
@@ -210,7 +211,8 @@ int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in, struct zxdh_msg_rec
  * @return: 0 成功，其他失败
  * 在驱动初始化时调用
  */
-int zxdh_bar_chan_msg_recv_register(uint8_t event_id, zxdh_bar_chan_msg_recv_callback callback);
+int zxdh_bar_chan_msg_recv_register(uint8_t event_id,
+									zxdh_bar_chan_msg_recv_callback callback);
 
 /**
  * zxdh_bar_chan_msg_recv_unregister - PCIE BAR空间消息方式，解注册消息接收回调
@@ -234,10 +236,11 @@ int zxdh_bar_enable_chan(struct msix_para *_msix_para, uint16_t *vport);
  * @bar_offset_params:  输入参数
  * @bar_offset_res: 模块偏移和长度
  */
-int zxdh_get_bar_offset(struct bar_offset_params *paras, struct bar_offset_res *res);
+int zxdh_get_bar_offset(struct bar_offset_params *paras,
+						struct bar_offset_res *res);
 
-int32_t zxdh_send_command(uint64_t vaddr, uint16_t pcie_id, uint16_t module_id, \
-                            void *msg, void *ack ,bool is_sync_msg);
+int32_t zxdh_send_command(uint64_t vaddr, uint16_t pcie_id, uint16_t module_id,
+						  void *msg, void *ack, bool is_sync_msg);
 
 int zxdh_bar_msg_chan_init(void);
 int zxdh_bar_msg_chan_remove(void);
@@ -254,10 +257,13 @@ void zxdh_bar_reset_valid(uint64_t subchan_addr);
  * @subchan_addr: 4k首地址
  * @return: event_id
  */
-uint16_t zxdh_get_event_id(uint64_t subchan_addr, uint8_t src_type, uint8_t dst_type);
+uint16_t zxdh_get_event_id(uint64_t subchan_addr, uint8_t src_type,
+						   uint8_t dst_type);
 
 int zxdh_bar_irq_recv(uint8_t src, uint8_t dst, uint64_t virt_addr, void *dev);
-int32_t call_msg_recv_func_tbl(uint16_t event_id, void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev);
+int32_t call_msg_recv_func_tbl(uint16_t event_id, void *pay_load, uint16_t len,
+							   void *reps_buffer, uint16_t *reps_len,
+							   void *dev);
 
 #ifdef __cplusplus
 }
diff --git a/src/net/include/linux/dinghai/dh_ifc.h b/src/net/include/linux/dinghai/dh_ifc.h
old mode 100755
new mode 100644
index 0006aadf3bdae925ad84072e59c9d21bad2879c0..039e7cbaf5948481e7ea80b91f08a24ca759cf3b
--- a/src/net/include/linux/dinghai/dh_ifc.h
+++ b/src/net/include/linux/dinghai/dh_ifc.h
@@ -1,51 +1,49 @@
-#ifndef DINGHAI_IFC_H
-#define DINGHAI_IFC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/types.h>
-
-struct dh_ifc_cmd_hca_cap_bits {
-
-};
-union dh_ifc_hca_cap_union_bits{
-
-};
-
-struct dh_ifc_mbox_in_bits {
-    uint8_t         opcode[0x10];
-    uint8_t         uid[0x10];
-
-    uint8_t         reserved_at_20[0x10];
-    uint8_t         op_mod[0x10];
-
-    uint8_t         reserved_at_40[0x40];
-};
-
-struct dh_ifc_mbox_out_bits {
-    uint8_t         status[0x8];
-    uint8_t         reserved_at_8[0x18];
-
-    uint8_t         syndrome[0x20];
-
-    uint8_t         reserved_at_40[0x40];
-};
-
-struct dh_ifc_query_hca_cap_out_bits {
-    uint8_t         status[0x8];
-    uint8_t         reserved_at_8[0x18];
-
-    uint8_t         syndrome[0x20];
-
-    uint8_t         reserved_at_40[0x40];
-
-    union dh_ifc_hca_cap_union_bits capability;
-};
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef DINGHAI_IFC_H
+#define DINGHAI_IFC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/types.h>
+
+struct dh_ifc_cmd_hca_cap_bits {
+};
+union dh_ifc_hca_cap_union_bits {
+};
+
+struct dh_ifc_mbox_in_bits {
+	uint8_t opcode[0x10];
+	uint8_t uid[0x10];
+
+	uint8_t reserved_at_20[0x10];
+	uint8_t op_mod[0x10];
+
+	uint8_t reserved_at_40[0x40];
+};
+
+struct dh_ifc_mbox_out_bits {
+	uint8_t status[0x8];
+	uint8_t reserved_at_8[0x18];
+
+	uint8_t syndrome[0x20];
+
+	uint8_t reserved_at_40[0x40];
+};
+
+struct dh_ifc_query_hca_cap_out_bits {
+	uint8_t status[0x8];
+	uint8_t reserved_at_8[0x18];
+
+	uint8_t syndrome[0x20];
+
+	uint8_t reserved_at_40[0x40];
+
+	union dh_ifc_hca_cap_union_bits capability;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/include/linux/dinghai/dinghai_irq.h b/src/net/include/linux/dinghai/dinghai_irq.h
old mode 100755
new mode 100644
index 7caaa6290d8f05bb0f9c7a1e10ba17c248a499ba..5ddb4e491ea7377146739a5f2719fc6c191cf620
--- a/src/net/include/linux/dinghai/dinghai_irq.h
+++ b/src/net/include/linux/dinghai/dinghai_irq.h
@@ -1,68 +1,76 @@
-#ifndef __DINGHAI_IRQ_H__
-#define __DINGHAI_IRQ_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/driver.h>
-#include <linux/dinghai/pci_irq.h>
-
-#define DH_COMP_EQS_PER_SF 8
-
-struct dh_irq;
-
-int32_t dh_irq_table_init(struct dh_core_dev *dev);
-void dh_irq_table_cleanup(struct dh_core_dev *dev);
-int32_t dh_irq_table_create(struct dh_core_dev *dev);
-void dh_irq_table_destroy(struct dh_core_dev *dev);
-int32_t dh_irq_table_get_num_comp(struct dh_irq_table *table);
-// int32_t dh_irq_table_get_sfs_vec(struct dh_irq_table *table);
-// bool dh_irq_table_have_dedicated_sfs_irqs(struct dh_irq_table *table);
-
-void dh_irq_rename(struct dh_core_dev *dev, struct dh_irq *irq,
-                   const char *name);
-int32_t dh_get_default_msix_vec_count(struct dh_core_dev *dev, int32_t num_vfs);
-
-
-void dh_ctrl_irq_release(struct dh_irq *ctrl_irq);
-struct dh_irq *dh_irq_request(struct dh_irq_pool *pool, uint16_t vecidx,
-                              const struct cpumask *affinity, uint8_t exclude);
-int32_t dh_irqs_request_vectors(struct dh_irq_pool *pool, uint16_t *cpus, int32_t nirqs,
-                                struct dh_irq **irqs);
-void dh_irqs_release_vectors(struct dh_irq **irqs, int32_t nirqs);
-int32_t dh_irqs_request_mask(struct dh_irq_pool *pool, struct dh_irq **irqs,
-                         struct cpumask *irqs_req_mask);
-int32_t dh_irq_attach_nb(struct dh_irq *irq, struct notifier_block *nb);
-int32_t dh_irq_detach_nb(struct dh_irq *irq, struct notifier_block *nb);
-struct cpumask *dh_irq_get_affinity_mask(struct dh_irq *irq);
-int32_t dh_irq_get_index(struct dh_irq *irq);
-
-struct dh_irq_pool;
-#ifdef CONFIG_ZXDH_SF
-
-int32_t dh_irq_affinity_irqs_request_auto(struct dh_irq_pool *pool, struct dh_irq **irqs, int32_t num_irqs);
-struct dh_irq *dh_irq_affinity_request(struct dh_irq_pool *pool,
-                                       const struct cpumask *req_mask);
-void dh_irq_affinity_irqs_release(struct dh_irq_pool *pool, struct dh_irq **irqs, int32_t num_irqs);
-#else
-static inline int32_t dh_irq_affinity_irqs_request_auto(struct dh_irq_pool *pool, struct dh_irq **irqs, int32_t num_irqs)
-{
-    return -EOPNOTSUPP;
-}
-
-static inline struct dh_irq *
-dh_irq_affinity_request(struct dh_irq_pool *pool, const struct cpumask *req_mask)
-{
-    return ERR_PTR(-EOPNOTSUPP);
-}
-
-static inline void dh_irq_affinity_irqs_release(struct dh_irq_pool *pool,
-                                                struct dh_irq **irqs, int32_t num_irqs) {}
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef __DINGHAI_IRQ_H__
+#define __DINGHAI_IRQ_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/driver.h>
+#include <linux/dinghai/pci_irq.h>
+
+#define DH_COMP_EQS_PER_SF 8
+
+struct dh_irq;
+
+int32_t dh_irq_table_init(struct dh_core_dev *dev);
+void dh_irq_table_cleanup(struct dh_core_dev *dev);
+int32_t dh_irq_table_create(struct dh_core_dev *dev);
+void dh_irq_table_destroy(struct dh_core_dev *dev);
+int32_t dh_irq_table_get_num_comp(struct dh_irq_table *table);
+// int32_t dh_irq_table_get_sfs_vec(struct dh_irq_table *table);
+// bool dh_irq_table_have_dedicated_sfs_irqs(struct dh_irq_table *table);
+
+void dh_irq_rename(struct dh_core_dev *dev, struct dh_irq *irq,
+				   const char *name);
+int32_t dh_get_default_msix_vec_count(struct dh_core_dev *dev, int32_t num_vfs);
+
+void dh_ctrl_irq_release(struct dh_irq *ctrl_irq);
+struct dh_irq *dh_irq_request(struct dh_irq_pool *pool, uint16_t vecidx,
+							  const struct cpumask *affinity, uint8_t exclude);
+int32_t dh_irqs_request_vectors(struct dh_irq_pool *pool, uint16_t *cpus,
+								int32_t nirqs, struct dh_irq **irqs);
+void dh_irqs_release_vectors(struct dh_irq **irqs, int32_t nirqs);
+int32_t dh_irqs_request_mask(struct dh_irq_pool *pool, struct dh_irq **irqs,
+							 struct cpumask *irqs_req_mask);
+int32_t dh_irq_attach_nb(struct dh_irq *irq, struct notifier_block *nb);
+int32_t dh_irq_detach_nb(struct dh_irq *irq, struct notifier_block *nb);
+struct cpumask *dh_irq_get_affinity_mask(struct dh_irq *irq);
+int32_t dh_irq_get_index(struct dh_irq *irq);
+
+struct dh_irq_pool;
+#ifdef CONFIG_ZXDH_SF
+
+int32_t dh_irq_affinity_irqs_request_auto(struct dh_irq_pool *pool,
+										  struct dh_irq **irqs,
+										  int32_t num_irqs);
+struct dh_irq *dh_irq_affinity_request(struct dh_irq_pool *pool,
+									   const struct cpumask *req_mask);
+void dh_irq_affinity_irqs_release(struct dh_irq_pool *pool,
+								  struct dh_irq **irqs, int32_t num_irqs);
+#else
+static inline int32_t
+dh_irq_affinity_irqs_request_auto(struct dh_irq_pool *pool,
+								  struct dh_irq **irqs, int32_t num_irqs)
+{
+	return -EOPNOTSUPP;
+}
+
+static inline struct dh_irq *
+dh_irq_affinity_request(struct dh_irq_pool *pool,
+						const struct cpumask *req_mask)
+{
+	return ERR_PTR(-EOPNOTSUPP);
+}
+
+static inline void dh_irq_affinity_irqs_release(struct dh_irq_pool *pool,
+												struct dh_irq **irqs,
+												int32_t num_irqs)
+{
+}
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/include/linux/dinghai/driver.h b/src/net/include/linux/dinghai/driver.h
old mode 100755
new mode 100644
index bfff65f1e77d1d776bb13e5fe75d933bc578c8e0..9f5e3ff1bdb984b95fe45cefa26cddc92c3e2918
--- a/src/net/include/linux/dinghai/driver.h
+++ b/src/net/include/linux/dinghai/driver.h
@@ -1,219 +1,205 @@
-#ifndef __DINGHAI_DRIVER_H__
-#define __DINGHAI_DRIVER_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/pci.h>
-#include <linux/dinghai/device.h>
-#include <linux/dinghai/events.h>
-#include <linux/dinghai/log.h>
-#include <linux/dinghai/auxiliary_bus.h>
-#include <net/devlink.h>
-
-struct dh_irq_table {
-    void *priv;
-};
-
-/*core dev*/
-enum dh_coredev_type {
-    DH_COREDEV_PF,
-    DH_COREDEV_VF,
-    DH_COREDEV_SF,
-    DH_COREDEV_MPF
-};
-
-typedef void (*zxdh_cmd_cbk_t)(int32_t status, void *context);
-
-struct dh_core_dev;
-
-struct dh_core_devlink_ops {
-    int32_t (*params_register)(struct devlink *devlink);
-    int32_t (*params_unregister)(struct devlink *devlink);
-};
-
-struct dh_core_dev {
-    struct device *device;             /* pdev->dev or zxdh auxiliary device*/
-    enum dh_coredev_type coredev_type;
-    struct pci_dev *pdev;              /* parent pdev*/
-    struct pcie_zf_ep *zf_ep;
-    struct dh_eq_table eq_table;
-    struct dh_irq_table irq_table;
-    struct dh_core_dev *parent;
-    struct dh_events *events;
-    int32_t numa_node;
-    struct devlink *devlink;
-    struct dh_core_devlink_ops *devlink_ops;
-    char priv[] __aligned(32);
-};
-
-#define VF_MAX_UNICAST_MAC   32
-#define VF_MAX_MULTICAST_MAC 32
-typedef struct
-{
-    uint8_t unicast_mac[VF_MAX_UNICAST_MAC][ETH_ALEN];
-    uint8_t multicast_mac[VF_MAX_MULTICAST_MAC][ETH_ALEN];
-}device_mac;
-
-struct zxdh_vf_item {
-    uint8_t mac[6];
-    uint16_t vlan;
-    uint8_t qos;
-    bool spoofchk;
-    bool trusted;
-    bool pf_set_mac;
-    bool link_forced;
-    bool link_up;
-    bool promisc;
-    bool mc_promisc;
-    bool enable;
-    uint32_t min_tx_rate;
-    uint32_t max_tx_rate;
-    uint16_t vport;
-    bool is_probed;
-    device_mac vf_mac_info;
-};
-
-static inline bool dh_core_is_pf(const struct dh_core_dev *dev)
-{
-    return dev->coredev_type == DH_COREDEV_PF;
-}
-
-static inline bool dh_core_is_vf(const struct dh_core_dev *dev)
-{
-    return dev->coredev_type == DH_COREDEV_VF;
-}
-
-static inline void *dh_core_priv(struct dh_core_dev *dh_coredev)
-{
-    BUG_ON(!dh_coredev);
-    return &dh_coredev->priv;
-}
-
-int32_t zxdh_cmd_exec(struct dh_core_dev *dev, void *in, int32_t in_size, void *out,
-                      int32_t out_size);
-
-#define zxdh_cmd_exec_inout(dev, ifc_cmd, in, out)                   \
-    ({                                                               \
-        zxdh_cmd_exec(dev, in, DH_ST_SZ_BYTES(ifc_cmd##_in), out,    \
-                      DH_ST_SZ_BYTES(ifc_cmd##_out));                \
-    })
-
-#define zxdh_cmd_exec_in(dev, ifc_cmd, in)                           \
-    ({                                                               \
-        uint32_t _out[DH_ST_SZ_DW(ifc_cmd##_out)] = {};              \
-        zxdh_cmd_exec_inout(dev, ifc_cmd, in, _out);                 \
-    })
-
-#define LOG_ERR(fmt, arg...) DH_LOG_ERR(MODULE_PF, fmt, ##arg);
-#define LOG_INFO(fmt, arg...) DH_LOG_INFO(MODULE_PF, fmt, ##arg);
-#define LOG_DEBUG(fmt, arg...) DH_LOG_DEBUG(MODULE_PF, fmt, ##arg);
-#define LOG_WARN(fmt, arg...) DH_LOG_WARNING(MODULE_PF, fmt, ##arg);
-
-#define ZXDH_ADEV_NAME  "dh_adev"
-#define ZXDH_EN_SF_NAME "zxdh_en"
-#define ZXDH_EN_DEV_ID_NAME "en_aux"
-#define ZXDH_PF_EN_SF_DEV_ID_NAME "pf_en_sf"
-#define ZXDH_EN_AUX_NAME "zxdh_en_aux"
-#define ZXDH_PF_NAME "zxdh_pf"
-#define ZXDH_MPF_EN_SF_DEV_ID_NAME "mpf_en_sf"
-#define ZXDH_MPF_NAME "zxdh_mpf"
-#define ZXDH_RDMA_DEV_NAME "rdma_aux"
-
-
-#define ZXDH_PF_BSI_VENDOR_ID  0x16c3
-#define ZXDH_PF_VENDOR_ID  0x1cf2
-#define ZXDH_PF_DEVICE_ID  0x8040
-#define ZXDH_VF_DEVICE_ID  0x8041
-#define ZXDH_INICA_BOND_DEVICE_ID  0x8045
-#define ZXDH_INICB_BOND_DEVICE_ID  0x8063
-#define ZXDH_DPUA_BOND_DEVICE_ID   0x8047
-#define ZXDH_PF_DPUB_NOF_DEVICE_ID   0x804a
-#define ZXDH_PF_DPUB_PF_DEVICE_ID    0x804b
-#define ZXDH_PF_DPUB_INITIATOR1_DEVICE_ID   0x804c
-#define ZXDH_PF_DPUB_INITIATOR2_DEVICE_ID   0x804d
-#define ZXDH_PF_DPUB_RDMA_DEVICE_ID   0x806b
-#define ZXDH_VF_DPUB_RDMA_DEVICE_ID   0x806c
-#define ZXDH_PF_E310_DEVICE_ID  0x8061
-#define ZXDH_VF_E310_DEVICE_ID  0x8062
-#define ZXDH_PF_E312_DEVICE_ID  0x8049
-#define ZXDH_VF_E312_DEVICE_ID  0x8060
-#define ZXDH_UPF_PF_I512_DEVICE_ID  0x804e
-#define ZXDH_UPF_VF_I512_DEVICE_ID  0x804f
-#define ZXDH_INICA_RDMA_PF_DEVICE_ID  0x806d
-#define ZXDH_INICA_RDMA_VF_DEVICE_ID  0x806e
-#define ZXDH_INICA_UPF_BOND_DEVICE_ID  0x806f
-
-#define ZXDH_BAR_MSG_OFFSET         0x2000
-#define ZXDH_BAR_PFVF_MSG_OFFSET    0x1000
-#define ZXDH_BAR_MSG_BASE(vaddr)    (ZXDH_BAR_MSG_OFFSET + vaddr)
-
-#define ZXDH_BAR_FWCAP(vaddr)       (0x1000 + vaddr)
-#define ZXDH_BOARD_TYPE             (0X1)
-#define ZXDH_PRODUCT_TYPE           (0X2)
-#define ZXDH_PANNEL_PORT_NUM        (0X3)
-
-
-enum
-{
-    ZXDH_DPU_A  = 0,
-    ZXDH_DPU_B  = 1,
-    ZXDH_INIC_A = 2,
-    ZXDH_INIC_B = 3,
-    ZXDH_STD_A  = 4,
-    ZXDH_STD_B  = 5,
-    ZXDH_EVB_EP0 = 6,
-    ZXDH_EVB_EP0_EP4 = 7,
-};
-
-/* Warning: Must be modified together with firmware */
-enum
-{
-    ZXDH_PRODUCT_STD = 0,
-    ZXDH_PRODUCT_DPI = 1,
-    ZXDH_PRODUCT_NEO = 2,
-    ZXDH_PRODUCT_OVS = 3,
-    ZXDH_PRODUCT_EVB_EP0 = 4,
-    ZXDH_PRODUCT_EVB_EP0_EP4 = 5,
-};
-
-#define ZXDH_VF_NUM_MAX             256
-
-struct resource_range {
-    phys_addr_t base;
-    resource_size_t size;
-};
-
-struct dh_sf_dev {
-    struct zxdh_auxiliary_device adev;
-    struct dh_core_dev *parent_mdev;
-    struct dh_core_dev *mdev;
-    int32_t res_num;
-    struct resource_range *ranges;
-};
-
-struct zf_rbp_info
-{
-    bool     host;                  /* true: host addr  false: zf addr*/
-    uint32_t pfid;                  /* bit7: 0-pf 1-vf */
-    uint32_t vfid;
-    uint32_t epid;
-};
-
-struct zf_dma_addr_rbp
-{
-    dma_addr_t addr;                /* src/dst addr */
-    uint32_t flag;                  /* no support */
-    struct zf_rbp_info rbp_info;
-};
-
-void zxdh_dev_list_lock(void);
-void zxdh_dev_list_unlock(void);
-int  zxdh_dev_list_trylock(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef __DINGHAI_DRIVER_H__
+#define __DINGHAI_DRIVER_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/pci.h>
+#include <linux/dinghai/device.h>
+#include <linux/dinghai/events.h>
+#include <linux/dinghai/log.h>
+#ifdef AUX_BUS_NO_SUPPORT
+#include <linux/dinghai/auxiliary_bus.h>
+#else
+#include <linux/auxiliary_bus.h>
+#endif
+#include <net/devlink.h>
+
+struct dh_irq_table {
+	void *priv;
+};
+
+/*core dev*/
+enum dh_coredev_type {
+	DH_COREDEV_PF,
+	DH_COREDEV_VF,
+	DH_COREDEV_SF,
+	DH_COREDEV_MPF
+};
+
+typedef void (*zxdh_cmd_cbk_t)(int32_t status, void *context);
+
+struct dh_core_dev;
+
+struct dh_core_devlink_ops {
+	int32_t (*params_register)(struct devlink *devlink);
+	int32_t (*params_unregister)(struct devlink *devlink);
+};
+
+struct dh_core_dev {
+	struct device *device; /* pdev->dev or auxiliary device*/
+	enum dh_coredev_type coredev_type;
+	struct pci_dev *pdev; /* parent pdev*/
+	struct pcie_zf_ep *zf_ep;
+	struct dh_eq_table eq_table;
+	struct dh_irq_table irq_table;
+	struct dh_core_dev *parent;
+	struct dh_events *events;
+	int32_t numa_node;
+	struct devlink *devlink;
+	struct dh_core_devlink_ops *devlink_ops;
+	char priv[] __aligned(32);
+};
+
+#define VF_MAX_UNICAST_MAC 32
+#define VF_MAX_MULTICAST_MAC 32
+typedef struct {
+	uint8_t unicast_mac[VF_MAX_UNICAST_MAC][ETH_ALEN];
+	uint8_t multicast_mac[VF_MAX_MULTICAST_MAC][ETH_ALEN];
+} device_mac;
+
+struct zxdh_vf_item {
+	uint8_t mac[6];
+	uint16_t vlan;
+	uint8_t qos;
+	bool spoofchk;
+	bool trusted;
+	bool pf_set_mac;
+	bool link_forced;
+	bool link_up;
+	bool promisc;
+	bool mc_promisc;
+	bool enable;
+	uint32_t min_tx_rate;
+	uint32_t max_tx_rate;
+	uint16_t vport;
+	bool is_probed;
+	device_mac vf_mac_info;
+};
+
+static inline bool dh_core_is_pf(const struct dh_core_dev *dev)
+{
+	return dev->coredev_type == DH_COREDEV_PF;
+}
+
+static inline bool dh_core_is_vf(const struct dh_core_dev *dev)
+{
+	return dev->coredev_type == DH_COREDEV_VF;
+}
+
+static inline void *dh_core_priv(struct dh_core_dev *dh_coredev)
+{
+	BUG_ON(!dh_coredev);
+	return &dh_coredev->priv;
+}
+
+int32_t zxdh_cmd_exec(struct dh_core_dev *dev, void *in, int32_t in_size,
+					  void *out, int32_t out_size);
+
+#define zxdh_cmd_exec_inout(dev, ifc_cmd, in, out)                \
+	({                                                            \
+		zxdh_cmd_exec(dev, in, DH_ST_SZ_BYTES(ifc_cmd##_in), out, \
+					  DH_ST_SZ_BYTES(ifc_cmd##_out));             \
+	})
+
+#define zxdh_cmd_exec_in(dev, ifc_cmd, in)              \
+	({                                                  \
+		uint32_t _out[DH_ST_SZ_DW(ifc_cmd##_out)] = {}; \
+		zxdh_cmd_exec_inout(dev, ifc_cmd, in, _out);    \
+	})
+
+#define LOG_ERR(fmt, arg...) DH_LOG_ERR(MODULE_PF, fmt, ##arg);
+#define LOG_INFO(fmt, arg...) DH_LOG_INFO(MODULE_PF, fmt, ##arg);
+#define LOG_DEBUG(fmt, arg...) DH_LOG_DEBUG(MODULE_PF, fmt, ##arg);
+#define LOG_WARN(fmt, arg...) DH_LOG_WARNING(MODULE_PF, fmt, ##arg);
+
+#define ZXDH_ADEV_NAME "dh_adev"
+#define ZXDH_EN_SF_NAME "zxdh_en"
+#define ZXDH_EN_DEV_ID_NAME "en_aux"
+#define ZXDH_PF_EN_SF_DEV_ID_NAME "pf_en_sf"
+#define ZXDH_EN_AUX_NAME "zxdh_en_aux"
+#define ZXDH_PF_NAME "zxdh_pf"
+#define ZXDH_MPF_EN_SF_DEV_ID_NAME "mpf_en_sf"
+#define ZXDH_MPF_NAME "zxdh_mpf"
+#define ZXDH_RDMA_DEV_NAME "rdma_aux"
+
+#define ZXDH_PF_BSI_VENDOR_ID 0x16c3
+#define ZXDH_PF_VENDOR_ID 0x1cf2
+#define ZXDH_PF_DEVICE_ID 0x8040
+#define ZXDH_VF_DEVICE_ID 0x8041
+#define ZXDH_INICA_BOND_DEVICE_ID 0x8045
+#define ZXDH_INICB_BOND_DEVICE_ID 0x8063
+#define ZXDH_DPUA_BOND_DEVICE_ID 0x8047
+#define ZXDH_PF_E310_DEVICE_ID 0x8061
+#define ZXDH_VF_E310_DEVICE_ID 0x8062
+#define ZXDH_PF_E312_DEVICE_ID 0x8049
+#define ZXDH_VF_E312_DEVICE_ID 0x8060
+
+#define ZXDH_BAR_MSG_OFFSET 0x2000
+#define ZXDH_BAR_PFVF_MSG_OFFSET 0x1000
+#define ZXDH_BAR_MSG_BASE(vaddr) (ZXDH_BAR_MSG_OFFSET + vaddr)
+
+#define ZXDH_BAR_FWCAP(vaddr) (0x1000 + vaddr)
+#define ZXDH_BOARD_TYPE (0X1)
+#define ZXDH_PRODUCT_TYPE (0X2)
+#define ZXDH_PANNEL_PORT_NUM (0X3)
+
+enum {
+	ZXDH_DPU_A = 0,
+	ZXDH_DPU_B = 1,
+	ZXDH_INIC_A = 2,
+	ZXDH_INIC_B = 3,
+	ZXDH_STD_A = 4,
+	ZXDH_STD_B = 5,
+	ZXDH_EVB_EP0 = 6,
+	ZXDH_EVB_EP0_EP4 = 7,
+};
+
+/* Warning: Must be modified together with firmware */
+enum {
+	ZXDH_PRODUCT_STD = 0,
+	ZXDH_PRODUCT_DPI = 1,
+	ZXDH_PRODUCT_NEO = 2,
+	ZXDH_PRODUCT_OVS = 3,
+	ZXDH_PRODUCT_EVB_EP0 = 4,
+	ZXDH_PRODUCT_EVB_EP0_EP4 = 5,
+};
+
+#define ZXDH_VF_NUM_MAX 256
+
+struct resource_range {
+	phys_addr_t base;
+	resource_size_t size;
+};
+
+struct dh_sf_dev {
+	struct auxiliary_device adev;
+	struct dh_core_dev *parent_mdev;
+	struct dh_core_dev *mdev;
+	int32_t res_num;
+	struct resource_range *ranges;
+};
+
+struct zf_rbp_info {
+	bool host; /* true: host addr  false: zf addr*/
+	uint32_t pfid; /* bit7: 0-pf 1-vf */
+	uint32_t vfid;
+	uint32_t epid;
+};
+
+struct zf_dma_addr_rbp {
+	dma_addr_t addr; /* src/dst addr */
+	uint32_t flag; /* no support */
+	struct zf_rbp_info rbp_info;
+};
+
+void zxdh_dev_list_lock(void);
+void zxdh_dev_list_unlock(void);
+int zxdh_dev_list_trylock(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/include/linux/dinghai/en_aux.h b/src/net/include/linux/dinghai/en_aux.h
index 522f67ee5f4ae685406b5c1f7fc365b505328a2b..0c9acad0a9ae36a787764c55894b3f652e1d2623 100644
--- a/src/net/include/linux/dinghai/en_aux.h
+++ b/src/net/include/linux/dinghai/en_aux.h
@@ -1,69 +1,65 @@
-#ifndef _EN_ZUX_H_
-#define _EN_ZUX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-struct eth_stats
-{
-    uint64_t rx_pkts;            /* gorc */
-    uint64_t rx_bytes;           /* gorc */
-    uint64_t rx_unicast;         /* uprc */
-    uint64_t rx_multicast;       /* mprc */
-    uint64_t rx_broadcast;       /* bprc */
-    uint64_t rx_discards;        /* rdpc */
-    uint64_t rx_errors;          /* rupp */
-    uint64_t tx_pkts;            /* gorc */
-    uint64_t tx_bytes;           /* gotc */
-    uint64_t tx_unicast;         /* uptc */
-    uint64_t tx_multicast;       /* mptc */
-    uint64_t tx_broadcast;       /* bptc */
-    uint64_t tx_discards;        /* tdpc */
-    uint64_t tx_errors;          /* tepc */
-    uint64_t rx_size_64;         /* prc64 */
-    uint64_t rx_size_127;        /* prc127 */
-    uint64_t rx_size_255;        /* prc255 */
-    uint64_t rx_size_511;        /* prc511 */
-    uint64_t rx_size_1023;       /* prc1023 */
-    uint64_t rx_size_1518;
-    uint64_t rx_size_1522;       /* prc1522 */
-    uint64_t rx_size_1548;
-    uint64_t rx_size_2047;
-    uint64_t rx_size_4095;
-    uint64_t rx_size_8191;
-    uint64_t rx_size_9215;
-    uint64_t rx_undersize;       /* ruc */
-    uint64_t rx_oversize;        /* roc */
-    uint64_t tx_size_64;         /* ptc64 */
-    uint64_t tx_size_127;        /* ptc127 */
-    uint64_t tx_size_255;        /* ptc255 */
-    uint64_t tx_size_511;        /* ptc511 */
-    uint64_t tx_size_1023;       /* ptc1023 */
-    uint64_t tx_size_1518;
-    uint64_t tx_size_1522;       /* prc1522 */
-    uint64_t tx_size_1548;
-    uint64_t tx_size_2047;
-    uint64_t tx_size_4095;
-    uint64_t tx_size_8191;
-    uint64_t tx_size_9215;
-    uint64_t tx_undersize;       /* ruc */
-    uint64_t tx_oversize;        /* roc */
-};
-
-struct zxdh_pf_eth_stats
-{
-    struct eth_stats eth_total_stat;
-    struct eth_stats mac0_stat;
-    struct eth_stats mac1_stat;
-    struct eth_stats mac2_stat;
-    struct eth_stats mac3_stat;
-};
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef _EN_ZUX_H_
+#define _EN_ZUX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct eth_stats {
+	uint64_t rx_pkts; /* gorc */
+	uint64_t rx_bytes; /* gorc */
+	uint64_t rx_unicast; /* uprc */
+	uint64_t rx_multicast; /* mprc */
+	uint64_t rx_broadcast; /* bprc */
+	uint64_t rx_discards; /* rdpc */
+	uint64_t rx_errors; /* rupp */
+	uint64_t tx_pkts; /* gorc */
+	uint64_t tx_bytes; /* gotc */
+	uint64_t tx_unicast; /* uptc */
+	uint64_t tx_multicast; /* mptc */
+	uint64_t tx_broadcast; /* bptc */
+	uint64_t tx_discards; /* tdpc */
+	uint64_t tx_errors; /* tepc */
+	uint64_t rx_size_64; /* prc64 */
+	uint64_t rx_size_127; /* prc127 */
+	uint64_t rx_size_255; /* prc255 */
+	uint64_t rx_size_511; /* prc511 */
+	uint64_t rx_size_1023; /* prc1023 */
+	uint64_t rx_size_1518;
+	uint64_t rx_size_1522; /* prc1522 */
+	uint64_t rx_size_1548;
+	uint64_t rx_size_2047;
+	uint64_t rx_size_4095;
+	uint64_t rx_size_8191;
+	uint64_t rx_size_9215;
+	uint64_t rx_undersize; /* ruc */
+	uint64_t rx_oversize; /* roc */
+	uint64_t tx_size_64; /* ptc64 */
+	uint64_t tx_size_127; /* ptc127 */
+	uint64_t tx_size_255; /* ptc255 */
+	uint64_t tx_size_511; /* ptc511 */
+	uint64_t tx_size_1023; /* ptc1023 */
+	uint64_t tx_size_1518;
+	uint64_t tx_size_1522; /* prc1522 */
+	uint64_t tx_size_1548;
+	uint64_t tx_size_2047;
+	uint64_t tx_size_4095;
+	uint64_t tx_size_8191;
+	uint64_t tx_size_9215;
+	uint64_t tx_undersize; /* ruc */
+	uint64_t tx_oversize; /* roc */
+};
+
+struct zxdh_pf_eth_stats {
+	struct eth_stats eth_total_stat;
+	struct eth_stats mac0_stat;
+	struct eth_stats mac1_stat;
+	struct eth_stats mac2_stat;
+	struct eth_stats mac3_stat;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/include/linux/dinghai/en_sf.h b/src/net/include/linux/dinghai/en_sf.h
old mode 100755
new mode 100644
index 5d8bee2112e065617ec99dd2c3fc2513e57ece1b..09851c9216759d5e9deb19f34b19c3d2519f0952
--- a/src/net/include/linux/dinghai/en_sf.h
+++ b/src/net/include/linux/dinghai/en_sf.h
@@ -1,83 +1,111 @@
-#ifndef __ZXDH_EN_SF_H__
-#define __ZXDH_EN_SF_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/auxiliary_bus.h>
-#include <linux/dinghai/dh_cmd.h>
-
-struct zxdh_en_sf_if {
-    int (*en_sf_vq_irqs_request)(struct dh_core_dev *dh_dev, struct dh_irq **vq_irqs, int vq_channels);
-    void (*en_sf_affinity_irqs_release)(struct dh_core_dev *dh_dev, struct dh_irq **irqs, int32_t num_irqs);
-    void __iomem * (*en_sf_map_vq_notify)(struct dh_core_dev *dh_dev, uint32_t index, resource_size_t *pa);
-    void (*en_sf_unmap_vq_notify)(struct dh_core_dev *dh_dev, void *priv);
-    void (*en_sf_set_status)(struct dh_core_dev *dh_dev, uint8_t status);
-    uint8_t (*en_sf_get_status)(struct dh_core_dev *dh_dev);
-    void (*en_sf_set_vf_mac)(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id);
-    void (*en_sf_get_vf_mac)(struct dh_core_dev *dh_dev, uint8_t *mac, int32_t vf_id);
-    void (*en_sf_set_mac)(struct dh_core_dev *dh_dev, uint8_t *mac);
-    void (*en_sf_get_mac)(struct dh_core_dev *dh_dev, uint8_t *mac);
-    uint64_t (*en_sf_get_features)(struct dh_core_dev *dh_dev);
-    void (*en_sf_set_features)(struct dh_core_dev *dh_dev, uint64_t features);
-    void (*en_sf_set_queue_enable)(struct dh_core_dev *dh_dev, uint16_t index, bool enable);
-    uint16_t (*en_sf_get_channels_num)(struct dh_core_dev *dh_dev);
-    uint16_t (*en_sf_get_queue_num)(struct dh_core_dev *dh_dev);
-    uint16_t (*en_sf_get_queue_size)(struct dh_core_dev *dh_dev, uint16_t index);
-    uint16_t (*en_sf_get_queue_vector)(struct dh_core_dev *dh_dev, uint16_t channel, struct list_head *eqs_list, uint16_t queue_index);
-    void (*en_sf_release_queue_vector)(struct dh_core_dev *dh_dev, int32_t queue_index);
-    void (*en_sf_set_queue_size)(struct dh_core_dev *dh_dev, uint32_t index, uint16_t size);
-    void (*en_sf_set_queue_address)(struct dh_core_dev *dh_dev, uint32_t index, uint64_t desc_addr, uint64_t driver_addr, uint64_t device_addr);
-    void (*en_sf_switch_irq)(struct dh_core_dev *dh_dev, int32_t i, int32_t op);
-    int32_t (*en_sf_get_vq_lock)(struct dh_core_dev *dh_dev);
-    int32_t (*en_sf_release_vq_lock)(struct dh_core_dev *dh_dev);
-    int32_t (*en_sf_get_phy_vq)(struct dh_core_dev *dh_dev, uint16_t index);
-    int32_t (*en_sf_release_phy_vq)(struct dh_core_dev *dh_dev, uint32_t *phy_index, uint16_t total_qnum);
-    uint32_t (*en_sf_get_epbdf)(struct dh_core_dev *dh_dev);
-    uint16_t (*en_sf_get_vport)(struct dh_core_dev *dh_dev);
-    enum dh_coredev_type (*en_sf_get_coredev_type)(struct dh_core_dev *dh_dev);
-    uint16_t (*en_sf_get_pcie_id)(struct dh_core_dev *dh_dev);
-    uint16_t (*en_sf_get_slot_id)(struct dh_core_dev *dh_dev);
-    bool (*en_sf_is_bond)(struct dh_core_dev *dh_dev);
-    bool (*en_sf_is_upf)(struct dh_core_dev *dh_dev);
-    struct pci_dev * (*en_sf_get_pdev)(struct dh_core_dev *dh_dev);
-    uint64_t (*en_sf_get_bar_virt_addr)(struct dh_core_dev *dh_dev, uint8_t bar_num);
-    int32_t (*en_sf_msg_send_cmd)(struct dh_core_dev *dh_dev, uint16_t module_id, void *msg, void *ack, bool is_sync);
-    int32_t (*en_sf_async_eq_enable)(struct dh_core_dev *dh_dev, struct dh_eq_async *eq, const char *name, bool attach);
-    struct zxdh_vf_item *(*en_sf_get_vf_item)(struct dh_core_dev *dh_dev, uint16_t vf_idx);
-    void (*en_sf_set_pf_link_up)(struct dh_core_dev *dh_dev, bool link_up);
-    bool (*en_sf_get_pf_link_up)(struct dh_core_dev *dh_dev);
-    void (*en_sf_update_pf_link_info)(struct dh_core_dev *dh_dev, struct link_info_struct *link_info_val);
-    int32_t (*en_sf_get_drv_msg)(struct dh_core_dev *dh_dev, uint8_t *drv_version, uint8_t *drv_version_len);
-    void (*en_sf_set_vepa)(struct dh_core_dev *dh_dev, bool vepa);
-    bool (*en_sf_get_vepa)(struct dh_core_dev *dh_dev);
-    void (*en_sf_set_bond_num)(struct dh_core_dev *dh_dev, bool add);
-    bool (*en_sf_if_init)(struct dh_core_dev *dh_dev);
-    int32_t (*en_sf_request_port_info)(struct dh_core_dev *dh_dev, void *data);
-    int32_t (*en_sf_release_port_info)(struct dh_core_dev *dh_dev, uint32_t port_id);
-    void (*en_sf_get_link_info_from_vqm)(struct dh_core_dev *dh_dev, uint8_t *link_up);
-    void (*en_sf_set_vf_link_info)(struct dh_core_dev *dh_dev, uint16_t vf_idx, uint8_t link_up);
-    void (*en_sf_set_pf_phy_port)(struct dh_core_dev *dh_dev, uint8_t phy_port);
-    uint8_t (*en_sf_get_pf_phy_port)(struct dh_core_dev *dh_dev);
-    void (*en_sf_set_init_comp_flag)(struct dh_core_dev *dh_dev);
-    struct zxdh_ipv6_mac_tbl * (*en_sf_get_ip6mac_tbl)(struct dh_core_dev *dh_dev);
-};
-
-struct zxdh_en_sf_container {
-    struct zxdh_auxiliary_device adev;
-    struct dh_core_dev *dh_dev;
-    struct dh_core_dev *cdev;
-    struct zxdh_en_sf_if *ops;
-    int    max_channels;
-};
-
-int32_t zxdh_en_sf_driver_register(void);
-void zxdh_en_sf_driver_unregister(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef __ZXDH_EN_SF_H__
+#define __ZXDH_EN_SF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef AUX_BUS_NO_SUPPORT
+#include <linux/dinghai/auxiliary_bus.h>
+#else
+#include <linux/auxiliary_bus.h>
+#endif
+#include <linux/dinghai/dh_cmd.h>
+
+struct zxdh_en_sf_if {
+	int (*en_sf_vq_irqs_request)(struct dh_core_dev *dh_dev,
+								 struct dh_irq **vq_irqs, int vq_channels);
+	void (*en_sf_affinity_irqs_release)(struct dh_core_dev *dh_dev,
+										struct dh_irq **irqs, int32_t num_irqs);
+	void __iomem *(*en_sf_map_vq_notify)(struct dh_core_dev *dh_dev,
+										 uint32_t index, resource_size_t *pa);
+	void (*en_sf_unmap_vq_notify)(struct dh_core_dev *dh_dev, void *priv);
+	void (*en_sf_set_status)(struct dh_core_dev *dh_dev, uint8_t status);
+	uint8_t (*en_sf_get_status)(struct dh_core_dev *dh_dev);
+	void (*en_sf_set_vf_mac)(struct dh_core_dev *dh_dev, uint8_t *mac,
+							 int32_t vf_id);
+	void (*en_sf_get_vf_mac)(struct dh_core_dev *dh_dev, uint8_t *mac,
+							 int32_t vf_id);
+	void (*en_sf_set_mac)(struct dh_core_dev *dh_dev, uint8_t *mac);
+	void (*en_sf_get_mac)(struct dh_core_dev *dh_dev, uint8_t *mac);
+	uint64_t (*en_sf_get_features)(struct dh_core_dev *dh_dev);
+	void (*en_sf_set_features)(struct dh_core_dev *dh_dev, uint64_t features);
+	void (*en_sf_set_queue_enable)(struct dh_core_dev *dh_dev, uint16_t index,
+								   bool enable);
+	uint16_t (*en_sf_get_channels_num)(struct dh_core_dev *dh_dev);
+	uint16_t (*en_sf_get_queue_num)(struct dh_core_dev *dh_dev);
+	uint16_t (*en_sf_get_queue_size)(struct dh_core_dev *dh_dev,
+									 uint16_t index);
+	uint16_t (*en_sf_get_queue_vector)(struct dh_core_dev *dh_dev,
+									   uint16_t channel,
+									   struct list_head *eqs_list,
+									   uint16_t queue_index);
+	void (*en_sf_release_queue_vector)(struct dh_core_dev *dh_dev,
+									   int32_t queue_index);
+	void (*en_sf_set_queue_size)(struct dh_core_dev *dh_dev, uint32_t index,
+								 uint16_t size);
+	void (*en_sf_set_queue_address)(struct dh_core_dev *dh_dev, uint32_t index,
+									uint64_t desc_addr, uint64_t driver_addr,
+									uint64_t device_addr);
+	void (*en_sf_switch_irq)(struct dh_core_dev *dh_dev, int32_t i, int32_t op);
+	int32_t (*en_sf_get_vq_lock)(struct dh_core_dev *dh_dev);
+	int32_t (*en_sf_release_vq_lock)(struct dh_core_dev *dh_dev);
+	int32_t (*en_sf_get_phy_vq)(struct dh_core_dev *dh_dev, uint16_t index);
+	int32_t (*en_sf_release_phy_vq)(struct dh_core_dev *dh_dev,
+									uint32_t *phy_index, uint16_t total_qnum);
+	uint32_t (*en_sf_get_epbdf)(struct dh_core_dev *dh_dev);
+	uint16_t (*en_sf_get_vport)(struct dh_core_dev *dh_dev);
+	enum dh_coredev_type (*en_sf_get_coredev_type)(struct dh_core_dev *dh_dev);
+	uint16_t (*en_sf_get_pcie_id)(struct dh_core_dev *dh_dev);
+	uint16_t (*en_sf_get_slot_id)(struct dh_core_dev *dh_dev);
+	bool (*en_sf_is_bond)(struct dh_core_dev *dh_dev);
+	struct pci_dev *(*en_sf_get_pdev)(struct dh_core_dev *dh_dev);
+	uint64_t (*en_sf_get_bar_virt_addr)(struct dh_core_dev *dh_dev,
+										uint8_t bar_num);
+	int32_t (*en_sf_msg_send_cmd)(struct dh_core_dev *dh_dev,
+								  uint16_t module_id, void *msg, void *ack,
+								  bool is_sync);
+	int32_t (*en_sf_async_eq_enable)(struct dh_core_dev *dh_dev,
+									 struct dh_eq_async *eq, const char *name,
+									 bool attach);
+	struct zxdh_vf_item *(*en_sf_get_vf_item)(struct dh_core_dev *dh_dev,
+											  uint16_t vf_idx);
+	void (*en_sf_set_pf_link_up)(struct dh_core_dev *dh_dev, bool link_up);
+	bool (*en_sf_get_pf_link_up)(struct dh_core_dev *dh_dev);
+	void (*en_sf_update_pf_link_info)(struct dh_core_dev *dh_dev,
+									  struct link_info_struct *link_info_val);
+	int32_t (*en_sf_get_drv_msg)(struct dh_core_dev *dh_dev,
+								 uint8_t *drv_version,
+								 uint8_t *drv_version_len);
+	void (*en_sf_set_vepa)(struct dh_core_dev *dh_dev, bool vepa);
+	bool (*en_sf_get_vepa)(struct dh_core_dev *dh_dev);
+	void (*en_sf_set_bond_num)(struct dh_core_dev *dh_dev, bool add);
+	bool (*en_sf_if_init)(struct dh_core_dev *dh_dev);
+	int32_t (*en_sf_request_port_info)(struct dh_core_dev *dh_dev, void *data);
+	int32_t (*en_sf_release_port_info)(struct dh_core_dev *dh_dev,
+									   uint32_t port_id);
+	void (*en_sf_get_link_info_from_vqm)(struct dh_core_dev *dh_dev,
+										 uint8_t *link_up);
+	void (*en_sf_set_vf_link_info)(struct dh_core_dev *dh_dev, uint16_t vf_idx,
+								   uint8_t link_up);
+	void (*en_sf_set_pf_phy_port)(struct dh_core_dev *dh_dev, uint8_t phy_port);
+	uint8_t (*en_sf_get_pf_phy_port)(struct dh_core_dev *dh_dev);
+	void (*en_sf_set_init_comp_flag)(struct dh_core_dev *dh_dev);
+};
+
+struct zxdh_en_sf_container {
+	struct auxiliary_device adev;
+	struct dh_core_dev *dh_dev;
+	struct dh_core_dev *cdev;
+	struct zxdh_en_sf_if *ops;
+	int max_channels;
+};
+
+int32_t zxdh_en_sf_driver_register(void);
+void zxdh_en_sf_driver_unregister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/include/linux/dinghai/eq.h b/src/net/include/linux/dinghai/eq.h
old mode 100755
new mode 100644
index ea3c9a0c743ace8efacad35770a2a62910046b63..811f72b06510061ef804d878d41d8c0f220b4c1d
--- a/src/net/include/linux/dinghai/eq.h
+++ b/src/net/include/linux/dinghai/eq.h
@@ -1,111 +1,118 @@
-#ifndef __DINGHAI_EQ_H__
-#define __DINGHAI_EQ_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/types.h>
-#include <linux/notifier.h>
-#include <linux/dinghai/device.h>
-
-struct dh_irq;
-
-#define INVALID_EVENT_TYPE 0
-
-enum DH_EVENT_TYPE {
-    DH_EVENT_TYPE_RISCV_READY = 13,
-    DH_EVENT_TYPE_NOTIFY_ANY = 14,
-    DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF = 15,
-    DH_EVENT_TYPE_NOTIFY_PF_TO_MPF = 16,
-    DH_EVENT_TYPE_NOTIFY_VF_TO_PF = 18,
-    DH_EVENT_TYPE_NOTIFY_PF_TO_VF = 19,
-    DH_EVENT_TYPE_NOTIFY_1 = 20,
-    DH_EVENT_TYPE_NOTIFY_2 = 21,
-    DH_EVENT_TYPE_NOTIFY_3 = 22,
-    DH_EVENT_TYPE_NOTIFY_4 = 23,
-    DH_EVENT_TYPE_NOTIFY_RISCV_TO_AUX = 24,
-    DH_EVENT_TYPE_NOTIFY_RISC_EXT_PPS = 25,
-    DH_EVENT_TYPE_NOTIFY_RISC_LOCAL_PPS = 26,
-    DH_EVENT_TYPE_MAX = 100,
-};
-
-/* eq core */
-struct dh_eq {
-    struct dh_core_dev *dev;
-    __be32 __iomem *doorbell;
-    uint32_t cons_index;
-    struct dh_irq *irq; /* interrupt core */
-};
-
-/* asynchronous interrupt */
-struct dh_eq_async {
-    struct dh_eq core;
-    struct notifier_block irq_nb; /* interrupt: notification chain related to the event queue*/
-    void *priv;
-    spinlock_t lock;              /* To avoid irq EQ handle races with resiliency flows */
-};
-
-struct dh_eq_param {
-    int32_t nent;           /* queue depth */
-    enum dh_event_queue_type event_type;
-    struct dh_irq *irq; /* interrupt associated with the event queue*/
-};
-
-/* event type in the event queue */
-struct dh_nb {
-    struct notifier_block nb;
-    int32_t event_type;
-};
-
-struct dh_irq_table;
-
-struct dh_eq_table {
-    struct atomic_notifier_head nh[DH_EVENT_TYPE_MAX];
-    struct mutex lock;
-    struct dh_irq_table *irq_table;
-    void *priv;
-};
-
-struct dh_eq_vq {
-    struct dh_eq          core;
-    struct notifier_block irq_nb;
-    void *para;
-};
-
-struct dh_eq_vqs {
-    struct dh_eq_vq       vq_s;
-    struct list_head      vqs;
-    struct list_head      list;
-};
-
-#define DH_NB_INIT(name, handler, event) do {     \
-    (name)->nb.notifier_call = handler;           \
-    (name)->event_type = DH_EVENT_TYPE_##event;   \
-} while (0)
-
-void dh_eq_table_cleanup(struct dh_core_dev *dev);
-void dh_eq_table_init(struct dh_core_dev *dev, void *table_priv);
-int32_t setup_async_eq(struct dh_core_dev *dev, struct dh_eq_async *eq,
-                       struct dh_eq_param *param, notifier_fn_t dh_eq_async_int, const char *name, void *priv);
-int32_t dh_inet6_addr_change_notifier_register(struct notifier_block *inet6_addr_change_notifier);
-int32_t dh_inet6_addr_change_notifier_unregister(struct notifier_block *inet6_addr_change_notifier);
-int32_t dh_eq_notifier_register(struct dh_eq_table *eqt, struct dh_nb *nb);
-void dh_eq_disable(struct dh_core_dev *dev, struct dh_eq *eq, struct notifier_block *nb);
-int32_t dh_eq_enable(struct dh_core_dev *dev, struct dh_eq *eq, struct notifier_block *nb);
-int32_t dh_eq_notifier_unregister(struct dh_eq_table *eqt, struct dh_nb *nb);
-uint16_t dh_eq_event_type_get(uint16_t event_id);
-
-typedef int32_t (*zxdh_callchain_cbk_t)(struct notifier_block *nb, unsigned long action, void *data);
-
-struct dh_vq_handler {
-    zxdh_callchain_cbk_t callback;
-    void *para;
-};
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef __DINGHAI_EQ_H__
+#define __DINGHAI_EQ_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/types.h>
+#include <linux/notifier.h>
+#include <linux/dinghai/device.h>
+
+struct dh_irq;
+
+#define INVALID_EVENT_TYPE 0
+
+enum DH_EVENT_TYPE {
+	DH_EVENT_TYPE_RISCV_READY = 13,
+	DH_EVENT_TYPE_NOTIFY_ANY = 14,
+	DH_EVENT_TYPE_NOTIFY_RISC_TO_MPF = 15,
+	DH_EVENT_TYPE_NOTIFY_PF_TO_MPF = 16,
+	DH_EVENT_TYPE_NOTIFY_VF_TO_PF = 18,
+	DH_EVENT_TYPE_NOTIFY_PF_TO_VF = 19,
+	DH_EVENT_TYPE_NOTIFY_1 = 20,
+	DH_EVENT_TYPE_NOTIFY_2 = 21,
+	DH_EVENT_TYPE_NOTIFY_3 = 22,
+	DH_EVENT_TYPE_NOTIFY_4 = 23,
+	DH_EVENT_TYPE_NOTIFY_RISCV_TO_AUX = 24,
+	DH_EVENT_TYPE_NOTIFY_RISC_EXT_PPS = 25,
+	DH_EVENT_TYPE_NOTIFY_RISC_LOCAL_PPS = 26,
+	DH_EVENT_TYPE_MAX = 100,
+};
+
+/* eq core */
+struct dh_eq {
+	struct dh_core_dev *dev;
+	__be32 __iomem *doorbell;
+	uint32_t cons_index;
+	struct dh_irq *irq; /* interrupt core */
+};
+
+/* asynchronous interrupt */
+struct dh_eq_async {
+	struct dh_eq core;
+	struct notifier_block
+			irq_nb; /* interrupt: notification chain related to the event queue*/
+	void *priv;
+	spinlock_t lock; /* To avoid irq EQ handle races with resiliency flows */
+};
+
+struct dh_eq_param {
+	int32_t nent; /* queue depth */
+	enum dh_event_queue_type event_type;
+	struct dh_irq *irq; /* interrupt associated with the event queue*/
+};
+
+/* event type in the event queue */
+struct dh_nb {
+	struct notifier_block nb;
+	int32_t event_type;
+};
+
+struct dh_irq_table;
+
+struct dh_eq_table {
+	struct atomic_notifier_head nh[DH_EVENT_TYPE_MAX];
+	struct mutex lock;
+	struct dh_irq_table *irq_table;
+	void *priv;
+};
+
+struct dh_eq_vq {
+	struct dh_eq core;
+	struct notifier_block irq_nb;
+	void *para;
+};
+
+struct dh_eq_vqs {
+	struct dh_eq_vq vq_s;
+	struct list_head vqs;
+	struct list_head list;
+};
+
+#define DH_NB_INIT(name, handler, event)            \
+	do {                                            \
+		(name)->nb.notifier_call = handler;         \
+		(name)->event_type = DH_EVENT_TYPE_##event; \
+	} while (0)
+
+void dh_eq_table_cleanup(struct dh_core_dev *dev);
+void dh_eq_table_init(struct dh_core_dev *dev, void *table_priv);
+int32_t setup_async_eq(struct dh_core_dev *dev, struct dh_eq_async *eq,
+					   struct dh_eq_param *param, notifier_fn_t dh_eq_async_int,
+					   const char *name, void *priv);
+int32_t dh_inet6_addr_change_notifier_register(
+		struct notifier_block *inet6_addr_change_notifier);
+int32_t dh_inet6_addr_change_notifier_unregister(
+		struct notifier_block *inet6_addr_change_notifier);
+int32_t dh_eq_notifier_register(struct dh_eq_table *eqt, struct dh_nb *nb);
+void dh_eq_disable(struct dh_core_dev *dev, struct dh_eq *eq,
+				   struct notifier_block *nb);
+int32_t dh_eq_enable(struct dh_core_dev *dev, struct dh_eq *eq,
+					 struct notifier_block *nb);
+int32_t dh_eq_notifier_unregister(struct dh_eq_table *eqt, struct dh_nb *nb);
+uint16_t dh_eq_event_type_get(uint16_t event_id);
+
+typedef int32_t (*zxdh_callchain_cbk_t)(struct notifier_block *nb,
+										unsigned long action, void *data);
+
+struct dh_vq_handler {
+	zxdh_callchain_cbk_t callback;
+	void *para;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/include/linux/dinghai/events.h b/src/net/include/linux/dinghai/events.h
old mode 100755
new mode 100644
index 550fce86e0159fd1791f03b0e9184f0ab504a30c..9820e0cc47fcd35402bb5c761016121768cda7af
--- a/src/net/include/linux/dinghai/events.h
+++ b/src/net/include/linux/dinghai/events.h
@@ -1,35 +1,35 @@
-#ifndef __ZXDH_EVENTS_H__
-#define __ZXDH_EVENTS_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/dinghai/eq.h>
-#include <linux/dinghai/driver.h>
-#include <linux/notifier.h>
-
-struct dh_event_nb {
-    struct dh_nb nb;
-    void *ctx;
-};
-
-struct dh_events {
-    struct dh_core_dev *dev;
-    struct workqueue_struct *wq;
-    int32_t evt_num;
-    struct dh_event_nb notifiers[0];
-};
-
-void zxdh_events_work_enqueue(struct dh_core_dev *dev, struct work_struct *work);
-void zxdh_events_cleanup(struct dh_core_dev *dev);
-
-#define dh_nb_cof(ptr, type, member) \
-	(container_of(container_of(ptr, struct dh_nb, nb), type, member))
-
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef __ZXDH_EVENTS_H__
+#define __ZXDH_EVENTS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dinghai/eq.h>
+#include <linux/dinghai/driver.h>
+#include <linux/notifier.h>
+
+struct dh_event_nb {
+	struct dh_nb nb;
+	void *ctx;
+};
+
+struct dh_events {
+	struct dh_core_dev *dev;
+	struct workqueue_struct *wq;
+	int32_t evt_num;
+	struct dh_event_nb notifiers[];
+};
+
+void zxdh_events_work_enqueue(struct dh_core_dev *dev,
+							  struct work_struct *work);
+void zxdh_events_cleanup(struct dh_core_dev *dev);
+
+#define dh_nb_cof(ptr, type, member) \
+	(container_of(container_of(ptr, struct dh_nb, nb), type, member))
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/include/linux/dinghai/helper.h b/src/net/include/linux/dinghai/helper.h
old mode 100755
new mode 100644
index 249cc4c986dba35e1fef41aa040bc7bd7af9286e..dec5533bd79151276dc5fea5741c43720a1d3e61
--- a/src/net/include/linux/dinghai/helper.h
+++ b/src/net/include/linux/dinghai/helper.h
@@ -1,81 +1,67 @@
-#ifndef DINGHAI_HELPER_H
-#define DINGHAI_HELPER_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef HAVE_DEV_PRINTK_OPS
-#include <linux/dev_printk.h>
-#endif
-#include <linux/types.h>
-#include <linux/dinghai/driver.h>
-
-extern uint32_t dh_debug_mask;
-#define dh_dbg(__dev, format, ...)                \
-    dev_dbg((__dev)->device, "%s:%d:(pid %d): " format,        \
-         __func__, __LINE__, current->pid,            \
-         ##__VA_ARGS__)
-
-#define dh_dbg_once(__dev, format, ...)        \
-    dev_dbg_once((__dev)->device,        \
-             "%s:%d:(pid %d): " format,        \
-             __func__, __LINE__, current->pid,    \
-             ##__VA_ARGS__)
-
-#define dh_dbg_mask(__dev, mask, format, ...)        \
-do {                                \
-    if ((mask) & dh_debug_mask)            \
-        dh_dbg(__dev, format, ##__VA_ARGS__);    \
-} while (0)
-
-#define dh_err(__dev, format, ...)            \
-    dev_err((__dev)->device, "%s:%d:(pid %d): " format,    \
-        __func__, __LINE__, current->pid,        \
-           ##__VA_ARGS__)
-
-#define dh_err_rl(__dev, format, ...)            \
-    dev_err_ratelimited((__dev)->device,            \
-                "%s:%d:(pid %d): " format,        \
-                __func__, __LINE__, current->pid,    \
-                ##__VA_ARGS__)
-
-#define dh_warn(__dev, format, ...)            \
-    dev_warn((__dev)->device, "%s:%d:(pid %d): " format,    \
-         __func__, __LINE__, current->pid,        \
-         ##__VA_ARGS__)
-
-#define dh_warn_once(__dev, format, ...)                \
-    dev_warn_once((__dev)->device, "%s:%d:(pid %d): " format,    \
-              __func__, __LINE__, current->pid,            \
-              ##__VA_ARGS__)
-
-#define dh_warn_rl(__dev, format, ...)            \
-    dev_warn_ratelimited((__dev)->device,            \
-                 "%s:%d:(pid %d): " format,        \
-                 __func__, __LINE__, current->pid,    \
-                 ##__VA_ARGS__)
-
-#define dh_info(__dev, format, ...)        \
-    dev_info((__dev)->device, format, ##__VA_ARGS__)
-
-#define dh_info_rl(__dev, format, ...)            \
-    dev_info_ratelimited((__dev)->device,            \
-                 "%s:%d:(pid %d): " format,        \
-                 __func__, __LINE__, current->pid,    \
-                 ##__VA_ARGS__)
-
-enum {
-    ZXDH_PCI_DEV_IS_VF = 1 << 0,
-};
-
-static inline bool dh_core_is_sf(const struct dh_core_dev *dev)
-{
-    return dev->coredev_type == DH_COREDEV_SF;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef DINGHAI_HELPER_H
+#define DINGHAI_HELPER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/dev_printk.h>
+#include <linux/types.h>
+#include <linux/dinghai/driver.h>
+
+extern uint32_t dh_debug_mask;
+#define dh_dbg(__dev, format, ...)                                          \
+	dev_dbg((__dev)->device, "%s:%d:(pid %d): " format, __func__, __LINE__, \
+			current->pid, ##__VA_ARGS__)
+
+#define dh_dbg_once(__dev, format, ...)                                \
+	dev_dbg_once((__dev)->device, "%s:%d:(pid %d): " format, __func__, \
+				 __LINE__, current->pid, ##__VA_ARGS__)
+
+#define dh_dbg_mask(__dev, mask, format, ...)     \
+	do {                                          \
+		if ((mask)&dh_debug_mask)                 \
+			dh_dbg(__dev, format, ##__VA_ARGS__); \
+	} while (0)
+
+#define dh_err(__dev, format, ...)                                          \
+	dev_err((__dev)->device, "%s:%d:(pid %d): " format, __func__, __LINE__, \
+			current->pid, ##__VA_ARGS__)
+
+#define dh_err_rl(__dev, format, ...)                                         \
+	dev_err_ratelimited((__dev)->device, "%s:%d:(pid %d): " format, __func__, \
+						__LINE__, current->pid, ##__VA_ARGS__)
+
+#define dh_warn(__dev, format, ...)                                          \
+	dev_warn((__dev)->device, "%s:%d:(pid %d): " format, __func__, __LINE__, \
+			 current->pid, ##__VA_ARGS__)
+
+#define dh_warn_once(__dev, format, ...)                                \
+	dev_warn_once((__dev)->device, "%s:%d:(pid %d): " format, __func__, \
+				  __LINE__, current->pid, ##__VA_ARGS__)
+
+#define dh_warn_rl(__dev, format, ...)                                         \
+	dev_warn_ratelimited((__dev)->device, "%s:%d:(pid %d): " format, __func__, \
+						 __LINE__, current->pid, ##__VA_ARGS__)
+
+#define dh_info(__dev, format, ...) \
+	dev_info((__dev)->device, format, ##__VA_ARGS__)
+
+#define dh_info_rl(__dev, format, ...)                                         \
+	dev_info_ratelimited((__dev)->device, "%s:%d:(pid %d): " format, __func__, \
+						 __LINE__, current->pid, ##__VA_ARGS__)
+
+enum {
+	ZXDH_PCI_DEV_IS_VF = 1 << 0,
+};
+
+static inline bool dh_core_is_sf(const struct dh_core_dev *dev)
+{
+	return dev->coredev_type == DH_COREDEV_SF;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/include/linux/dinghai/kcompat.h b/src/net/include/linux/dinghai/kcompat.h
index 5429625eb0534ed78ba42904687bafbc0e46c9bc..8bb243e9a6418b273c857a827b941c770236cc3b 100644
--- a/src/net/include/linux/dinghai/kcompat.h
+++ b/src/net/include/linux/dinghai/kcompat.h
@@ -7,7 +7,7 @@
 #ifndef LINUX_VERSION_CODE
 #include <linux/version.h>
 #else
-#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
+#define KERNEL_VERSION(a, b, c) (((a) << 16) + ((b) << 8) + (c))
 #endif
 #include <linux/io.h>
 #include <linux/delay.h>
@@ -36,27 +36,25 @@
 #include <linux/types.h>
 #include <linux/udp.h>
 #include <linux/vmalloc.h>
-#include <stdarg.h>
 
 #ifndef GCC_VERSION
-#define GCC_VERSION (__GNUC__ * 10000		\
-		     + __GNUC_MINOR__ * 100	\
-		     + __GNUC_PATCHLEVEL__)
+#define GCC_VERSION \
+	(__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
 #endif /* GCC_VERSION */
 
 /* Backport macros for controlling GCC diagnostics */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,18,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 18, 0))
 
 /* Compilers before gcc-4.6 do not understand "#pragma GCC diagnostic push" */
 #if GCC_VERSION >= 40600
-#define __diag_str1(s)		#s
-#define __diag_str(s)		__diag_str1(s)
-#define __diag(s)		_Pragma(__diag_str(GCC diagnostic s))
+#define __diag_str1(s) #s
+#define __diag_str(s) __diag_str1(s)
+#define __diag(s) _Pragma(__diag_str(GCC diagnostic s))
 #else
 #define __diag(s)
 #endif /* GCC_VERSION >= 4.6 */
-#define __diag_push()	__diag(push)
-#define __diag_pop()	__diag(pop)
+#define __diag_push() __diag(push)
+#define __diag_pop() __diag(pop)
 #endif /* LINUX_VERSION < 4.18.0 */
 
 #ifndef NSEC_PER_MSEC
@@ -66,7 +64,7 @@
 /* UTS_RELEASE is in a different header starting in kernel 2.6.18 */
 #ifndef UTS_RELEASE
 /* utsrelease.h changed locations in 2.6.33 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33))
 #include <linux/utsrelease.h>
 #else
 #include <generated/utsrelease.h>
@@ -86,7 +84,7 @@
 #define TRUE true
 #define FALSE false
 #ifdef GCC_VERSION
-#if ( GCC_VERSION < 3000 )
+#if (GCC_VERSION < 3000)
 #define _Bool char
 #endif
 #else
@@ -94,7 +92,7 @@
 #endif
 
 #ifndef BIT
-#define BIT(nr)         (1UL << (nr))
+#define BIT(nr) (1UL << (nr))
 #endif
 
 #undef __always_unused
@@ -109,15 +107,15 @@
 #endif
 
 #ifndef module_param
-#define module_param(v,t,p) MODULE_PARM(v, "i");
+#define module_param(v, t, p) MODULE_PARM(v, "i");
 #endif
 
 #ifndef DMA_64BIT_MASK
-#define DMA_64BIT_MASK  0xffffffffffffffffULL
+#define DMA_64BIT_MASK 0xffffffffffffffffULL
 #endif
 
 #ifndef DMA_32BIT_MASK
-#define DMA_32BIT_MASK  0x00000000ffffffffULL
+#define DMA_32BIT_MASK 0x00000000ffffffffULL
 #endif
 
 #ifndef PCI_CAP_ID_EXP
@@ -125,15 +123,15 @@
 #endif
 
 #ifndef uninitialized_var
-#define uninitialized_var(x) x = x
+#define uninitialized_var(x) (x = x)
 #endif
 
 #ifndef SET_NETDEV_DEV
 #define SET_NETDEV_DEV(net, pdev)
 #endif
 
-#if !defined(HAVE_FREE_NETDEV) && ( LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) )
-#define free_netdev(x)	kfree(x)
+#if !defined(HAVE_FREE_NETDEV) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))
+#define free_netdev(x) kfree(x)
 #endif
 
 #ifdef HAVE_POLL_CONTROLLER
@@ -142,7 +140,7 @@
 
 #ifndef SKB_DATAREF_SHIFT
 /* if we do not have the infrastructure to detect if skb_header is cloned
-   just return false in all cases */
+just return false in all cases */
 #define skb_header_cloned(x) 0
 #endif
 
@@ -153,7 +151,7 @@
 
 #ifndef NETIF_F_GRO
 #define vlan_gro_receive(_napi, _vlgrp, _vlan, _skb) \
-		vlan_hwaccel_receive_skb(_skb, _vlgrp, _vlan)
+	vlan_hwaccel_receive_skb(_skb, _vlgrp, _vlan)
 #define napi_gro_receive(_napi, _skb) netif_receive_skb(_skb)
 #endif
 
@@ -166,8 +164,7 @@
 #endif
 
 #ifndef NETIF_F_ALL_FCOE
-#define NETIF_F_ALL_FCOE	(NETIF_F_FCOE_CRC | NETIF_F_FCOE_MTU | \
-				 NETIF_F_FSO)
+#define NETIF_F_ALL_FCOE (NETIF_F_FCOE_CRC | NETIF_F_FCOE_MTU | NETIF_F_FSO)
 #endif
 
 #ifndef IPPROTO_SCTP
@@ -193,9 +190,9 @@
 #endif
 
 #ifndef PCI_DEVICE
-#define PCI_DEVICE(vend,dev) \
-	.vendor = (vend), .device = (dev), \
-	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
+#define PCI_DEVICE(vend, dev)                                   \
+	.vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
+	.subdevice = PCI_ANY_ID
 #endif
 
 #ifndef node_online
@@ -215,11 +212,11 @@
 #endif
 
 #ifndef BITS_TO_LONGS
-#define BITS_TO_LONGS(bits) (((bits)+BITS_PER_LONG-1)/BITS_PER_LONG)
+#define BITS_TO_LONGS(bits) (((bits) + BITS_PER_LONG - 1) / BITS_PER_LONG)
 #endif
 
 #ifndef DECLARE_BITMAP
-#define DECLARE_BITMAP(name,bits) long name[BITS_TO_LONGS(bits)]
+#define DECLARE_BITMAP(name, bits) long name[BITS_TO_LONGS(bits)]
 #endif
 
 #ifndef VLAN_HLEN
@@ -234,7 +231,7 @@
 
 /* taken from 2.6.24 definition in linux/kernel.h */
 #ifndef IS_ALIGNED
-#define IS_ALIGNED(x,a)         (((x) % ((typeof(x))(a))) == 0)
+#define IS_ALIGNED(x, a) (((x) % ((typeof(x))(a))) == 0)
 #endif
 
 #ifdef IS_ENABLED
@@ -257,16 +254,16 @@
 
 #if !defined(NETIF_F_HW_VLAN_TX) && !defined(NETIF_F_HW_VLAN_CTAG_TX)
 struct _kc_vlan_ethhdr {
-	unsigned char	h_dest[ETH_ALEN];
-	unsigned char	h_source[ETH_ALEN];
-	__be16		h_vlan_proto;
-	__be16		h_vlan_TCI;
-	__be16		h_vlan_encapsulated_proto;
+	unsigned char h_dest[ETH_ALEN];
+	unsigned char h_source[ETH_ALEN];
+	__be16 h_vlan_proto;
+	__be16 h_vlan_TCI;
+	__be16 h_vlan_encapsulated_proto;
 };
 #define vlan_ethhdr _kc_vlan_ethhdr
 struct _kc_vlan_hdr {
-	__be16		h_vlan_TCI;
-	__be16		h_vlan_encapsulated_proto;
+	__be16 h_vlan_TCI;
+	__be16 h_vlan_encapsulated_proto;
 };
 #define vlan_hdr _kc_vlan_hdr
 #define vlan_tx_tag_present(_skb) 0
@@ -342,36 +339,36 @@ struct k_ethtool_drvinfo {
 struct ethtool_stats {
 	u32 cmd;
 	u32 n_stats;
-	u64 data[0];
+	u64 data[];
 };
 #endif /* ETHTOOL_GSTATS */
 
 #ifndef ETHTOOL_GSTRINGS
 #define ETHTOOL_GSTRINGS 0x1b
 enum ethtool_stringset {
-	ETH_SS_TEST             = 0,
+	ETH_SS_TEST = 0,
 	ETH_SS_STATS,
 };
 struct ethtool_gstrings {
-	u32 cmd;            /* ETHTOOL_GSTRINGS */
-	u32 string_set;     /* string set id e.c. ETH_SS_TEST, etc*/
-	u32 len;            /* number of strings in the string set */
-	u8 data[0];
+	u32 cmd; /* ETHTOOL_GSTRINGS */
+	u32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/
+	u32 len; /* number of strings in the string set */
+	u8 data[];
 };
 #endif /* ETHTOOL_GSTRINGS */
 
 #ifndef ETHTOOL_TEST
 #define ETHTOOL_TEST 0x1a
 enum ethtool_test_flags {
-	ETH_TEST_FL_OFFLINE	= BIT(0),
-	ETH_TEST_FL_FAILED	= BIT(1),
+	ETH_TEST_FL_OFFLINE = BIT(0),
+	ETH_TEST_FL_FAILED = BIT(1),
 };
 struct ethtool_test {
 	u32 cmd;
 	u32 flags;
 	u32 reserved;
 	u32 len;
-	u64 data[0];
+	u64 data[];
 };
 #endif /* ETHTOOL_TEST */
 
@@ -383,7 +380,7 @@ struct ethtool_eeprom {
 	u32 magic;
 	u32 offset;
 	u32 len;
-	u8 data[0];
+	u8 data[];
 };
 
 struct ethtool_value {
@@ -399,7 +396,7 @@ struct ethtool_value {
 #ifndef ETHTOOL_GWOL
 #define ETHTOOL_GWOL 0x5
 #define ETHTOOL_SWOL 0x6
-#define SOPASS_MAX      6
+#define SOPASS_MAX 6
 struct ethtool_wolinfo {
 	u32 cmd;
 	u32 supported;
@@ -409,159 +406,161 @@ struct ethtool_wolinfo {
 #endif /* ETHTOOL_GWOL */
 
 #ifndef ETHTOOL_GREGS
-#define ETHTOOL_GREGS		0x00000004 /* Get NIC registers */
+#define ETHTOOL_GREGS 0x00000004 /* Get NIC registers */
 #define ethtool_regs _kc_ethtool_regs
 /* for passing big chunks of data */
 struct _kc_ethtool_regs {
 	u32 cmd;
 	u32 version; /* driver-specific, indicates different chips/revs */
 	u32 len; /* bytes */
-	u8 data[0];
+	u8 data[];
 };
 #endif /* ETHTOOL_GREGS */
 
 #ifndef ETHTOOL_GMSGLVL
-#define ETHTOOL_GMSGLVL		0x00000007 /* Get driver message level */
+#define ETHTOOL_GMSGLVL 0x00000007 /* Get driver message level */
 #endif
 #ifndef ETHTOOL_SMSGLVL
-#define ETHTOOL_SMSGLVL		0x00000008 /* Set driver msg level, priv. */
+#define ETHTOOL_SMSGLVL 0x00000008 /* Set driver msg level, priv. */
 #endif
 #ifndef ETHTOOL_NWAY_RST
-#define ETHTOOL_NWAY_RST	0x00000009 /* Restart autonegotiation, priv */
+#define ETHTOOL_NWAY_RST 0x00000009 /* Restart autonegotiation, priv */
 #endif
 #ifndef ETHTOOL_GLINK
-#define ETHTOOL_GLINK		0x0000000a /* Get link status */
+#define ETHTOOL_GLINK 0x0000000a /* Get link status */
 #endif
 #ifndef ETHTOOL_GEEPROM
-#define ETHTOOL_GEEPROM		0x0000000b /* Get EEPROM data */
+#define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */
 #endif
 #ifndef ETHTOOL_SEEPROM
-#define ETHTOOL_SEEPROM		0x0000000c /* Set EEPROM data */
+#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data */
 #endif
 #ifndef ETHTOOL_GCOALESCE
-#define ETHTOOL_GCOALESCE	0x0000000e /* Get coalesce config */
+#define ETHTOOL_GCOALESCE 0x0000000e /* Get coalesce config */
 
 #define ethtool_coalesce _kc_ethtool_coalesce
 struct _kc_ethtool_coalesce {
-	u32	cmd;
+	u32 cmd;
 
-	u32	rx_coalesce_usecs;
+	u32 rx_coalesce_usecs;
 
-	u32	rx_max_coalesced_frames;
+	u32 rx_max_coalesced_frames;
 
-	u32	rx_coalesce_usecs_irq;
-	u32	rx_max_coalesced_frames_irq;
+	u32 rx_coalesce_usecs_irq;
+	u32 rx_max_coalesced_frames_irq;
 
-	u32	tx_coalesce_usecs;
+	u32 tx_coalesce_usecs;
 
-	u32	tx_max_coalesced_frames;
+	u32 tx_max_coalesced_frames;
 
-	u32	tx_coalesce_usecs_irq;
-	u32	tx_max_coalesced_frames_irq;
+	u32 tx_coalesce_usecs_irq;
+	u32 tx_max_coalesced_frames_irq;
 
-	u32	stats_block_coalesce_usecs;
+	u32 stats_block_coalesce_usecs;
 
-	u32	use_adaptive_rx_coalesce;
-	u32	use_adaptive_tx_coalesce;
+	u32 use_adaptive_rx_coalesce;
+	u32 use_adaptive_tx_coalesce;
 
-	u32	pkt_rate_low;
-	u32	rx_coalesce_usecs_low;
-	u32	rx_max_coalesced_frames_low;
-	u32	tx_coalesce_usecs_low;
-	u32	tx_max_coalesced_frames_low;
+	u32 pkt_rate_low;
+	u32 rx_coalesce_usecs_low;
+	u32 rx_max_coalesced_frames_low;
+	u32 tx_coalesce_usecs_low;
+	u32 tx_max_coalesced_frames_low;
 
-	u32	pkt_rate_high;
-	u32	rx_coalesce_usecs_high;
-	u32	rx_max_coalesced_frames_high;
-	u32	tx_coalesce_usecs_high;
-	u32	tx_max_coalesced_frames_high;
+	u32 pkt_rate_high;
+	u32 rx_coalesce_usecs_high;
+	u32 rx_max_coalesced_frames_high;
+	u32 tx_coalesce_usecs_high;
+	u32 tx_max_coalesced_frames_high;
 
-	u32	rate_sample_interval;
+	u32 rate_sample_interval;
 };
 #endif /* ETHTOOL_GCOALESCE */
 
 #ifndef ETHTOOL_SCOALESCE
-#define ETHTOOL_SCOALESCE	0x0000000f /* Set coalesce config. */
+#define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config. */
 #endif
 #ifndef ETHTOOL_GRINGPARAM
-#define ETHTOOL_GRINGPARAM	0x00000010 /* Get ring parameters */
+#define ETHTOOL_GRINGPARAM 0x00000010 /* Get ring parameters */
 
 #define ethtool_ringparam _kc_ethtool_ringparam
 struct _kc_ethtool_ringparam {
-	u32	cmd;
+	u32 cmd;
 
-	u32	rx_max_pending;
-	u32	rx_mini_max_pending;
-	u32	rx_jumbo_max_pending;
-	u32	tx_max_pending;
+	u32 rx_max_pending;
+	u32 rx_mini_max_pending;
+	u32 rx_jumbo_max_pending;
+	u32 tx_max_pending;
 
-	u32	rx_pending;
-	u32	rx_mini_pending;
-	u32	rx_jumbo_pending;
-	u32	tx_pending;
+	u32 rx_pending;
+	u32 rx_mini_pending;
+	u32 rx_jumbo_pending;
+	u32 tx_pending;
 };
 #endif /* ETHTOOL_GRINGPARAM */
 
 #ifndef ETHTOOL_SRINGPARAM
-#define ETHTOOL_SRINGPARAM	0x00000011 /* Set ring parameters, priv. */
+#define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters, priv. */
 #endif
 #ifndef ETHTOOL_GPAUSEPARAM
-#define ETHTOOL_GPAUSEPARAM	0x00000012 /* Get pause parameters */
+#define ETHTOOL_GPAUSEPARAM 0x00000012 /* Get pause parameters */
 
 #define ethtool_pauseparam _kc_ethtool_pauseparam
 struct _kc_ethtool_pauseparam {
-	u32	cmd;
-	u32	autoneg;
-	u32	rx_pause;
-	u32	tx_pause;
+	u32 cmd;
+	u32 autoneg;
+	u32 rx_pause;
+	u32 tx_pause;
 };
 #endif /* ETHTOOL_GPAUSEPARAM */
 
 #ifndef ETHTOOL_SPAUSEPARAM
-#define ETHTOOL_SPAUSEPARAM	0x00000013 /* Set pause parameters. */
+#define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters. */
 #endif
 #ifndef ETHTOOL_GRXCSUM
-#define ETHTOOL_GRXCSUM		0x00000014 /* Get RX hw csum enable (ethtool_value) */
+#define ETHTOOL_GRXCSUM 0x00000014 /* Get RX hw csum enable (ethtool_value) */
 #endif
 #ifndef ETHTOOL_SRXCSUM
-#define ETHTOOL_SRXCSUM		0x00000015 /* Set RX hw csum enable (ethtool_value) */
+#define ETHTOOL_SRXCSUM 0x00000015 /* Set RX hw csum enable (ethtool_value) */
 #endif
 #ifndef ETHTOOL_GTXCSUM
-#define ETHTOOL_GTXCSUM		0x00000016 /* Get TX hw csum enable (ethtool_value) */
+#define ETHTOOL_GTXCSUM 0x00000016 /* Get TX hw csum enable (ethtool_value) */
 #endif
 #ifndef ETHTOOL_STXCSUM
-#define ETHTOOL_STXCSUM		0x00000017 /* Set TX hw csum enable (ethtool_value) */
+#define ETHTOOL_STXCSUM 0x00000017 /* Set TX hw csum enable (ethtool_value) */
 #endif
 #ifndef ETHTOOL_GSG
-#define ETHTOOL_GSG		0x00000018 /* Get scatter-gather enable
-					    * (ethtool_value) */
+#define ETHTOOL_GSG \
+	0x00000018 /* Get scatter-gather enable                                      \
+			* (ethtool_value) */
 #endif
 #ifndef ETHTOOL_SSG
-#define ETHTOOL_SSG		0x00000019 /* Set scatter-gather enable
-					    * (ethtool_value). */
+#define ETHTOOL_SSG \
+	0x00000019 /* Set scatter-gather enable                                      \
+			* (ethtool_value). */
 #endif
 #ifndef ETHTOOL_TEST
-#define ETHTOOL_TEST		0x0000001a /* execute NIC self-test, priv. */
+#define ETHTOOL_TEST 0x0000001a /* execute NIC self-test, priv. */
 #endif
 #ifndef ETHTOOL_GSTRINGS
-#define ETHTOOL_GSTRINGS	0x0000001b /* get specified string set */
+#define ETHTOOL_GSTRINGS 0x0000001b /* get specified string set */
 #endif
 #ifndef ETHTOOL_GSTATS
-#define ETHTOOL_GSTATS		0x0000001d /* get NIC-specific statistics */
+#define ETHTOOL_GSTATS 0x0000001d /* get NIC-specific statistics */
 #endif
 #ifndef ETHTOOL_GTSO
-#define ETHTOOL_GTSO		0x0000001e /* Get TSO enable (ethtool_value) */
+#define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */
 #endif
 #ifndef ETHTOOL_STSO
-#define ETHTOOL_STSO		0x0000001f /* Set TSO enable (ethtool_value) */
+#define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */
 #endif
 
 #ifndef ETHTOOL_BUSINFO_LEN
-#define ETHTOOL_BUSINFO_LEN	32
+#define ETHTOOL_BUSINFO_LEN 32
 #endif
 
 #ifndef WAKE_FILTER
-#define WAKE_FILTER	BIT(7)
+#define WAKE_FILTER BIT(7)
 #endif
 
 #ifndef SPEED_2500
@@ -587,22 +586,22 @@ struct _kc_ethtool_pauseparam {
 #endif
 
 #ifndef RHEL_RELEASE_VERSION
-#define RHEL_RELEASE_VERSION(a,b) (((a) << 8) + (b))
+#define RHEL_RELEASE_VERSION(a, b) (((a) << 8) + (b))
 #endif
 #ifndef AX_RELEASE_VERSION
-#define AX_RELEASE_VERSION(a,b) (((a) << 8) + (b))
+#define AX_RELEASE_VERSION(a, b) (((a) << 8) + (b))
 #endif
 
 #ifndef AX_RELEASE_CODE
 #define AX_RELEASE_CODE 0
 #endif
 
-#if (AX_RELEASE_CODE && AX_RELEASE_CODE == AX_RELEASE_VERSION(3,0))
-#define RHEL_RELEASE_CODE RHEL_RELEASE_VERSION(5,0)
-#elif (AX_RELEASE_CODE && AX_RELEASE_CODE == AX_RELEASE_VERSION(3,1))
-#define RHEL_RELEASE_CODE RHEL_RELEASE_VERSION(5,1)
-#elif (AX_RELEASE_CODE && AX_RELEASE_CODE == AX_RELEASE_VERSION(3,2))
-#define RHEL_RELEASE_CODE RHEL_RELEASE_VERSION(5,3)
+#if (AX_RELEASE_CODE && AX_RELEASE_CODE == AX_RELEASE_VERSION(3, 0))
+#define RHEL_RELEASE_CODE RHEL_RELEASE_VERSION(5, 0)
+#elif (AX_RELEASE_CODE && AX_RELEASE_CODE == AX_RELEASE_VERSION(3, 1))
+#define RHEL_RELEASE_CODE RHEL_RELEASE_VERSION(5, 1)
+#elif (AX_RELEASE_CODE && AX_RELEASE_CODE == AX_RELEASE_VERSION(3, 2))
+#define RHEL_RELEASE_CODE RHEL_RELEASE_VERSION(5, 3)
 #endif
 
 #ifndef RHEL_RELEASE_CODE
@@ -611,56 +610,56 @@ struct _kc_ethtool_pauseparam {
 #endif
 
 /* RHEL 7 didn't backport the parameter change in
- * create_singlethread_workqueue.
- * If/when RH corrects this we will want to tighten up the version check.
- */
-#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,0))
+* create_singlethread_workqueue.
+* If/when RH corrects this we will want to tighten up the version check.
+*/
+#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 0))
 #undef create_singlethread_workqueue
-#define create_singlethread_workqueue(name)	\
+#define create_singlethread_workqueue(name) \
 	alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, name)
 #endif
 
 /* Ubuntu Release ABI is the 4th digit of their kernel version. You can find
- * it in /usr/src/linux/$(uname -r)/include/generated/utsrelease.h for new
- * enough versions of Ubuntu. Otherwise you can simply see it in the output of
- * uname as the 4th digit of the kernel. The UTS_UBUNTU_RELEASE_ABI is not in
- * the linux-source package, but in the linux-headers package. It begins to
- * appear in later releases of 14.04 and 14.10.
- *
- * Ex:
- * <Ubuntu 14.04.1>
- *  $uname -r
- *  3.13.0-45-generic
- * ABI is 45
- *
- * <Ubuntu 14.10>
- *  $uname -r
- *  3.16.0-23-generic
- * ABI is 23
- */
+* it in /usr/src/linux/$(uname -r)/include/generated/utsrelease.h for new
+* enough versions of Ubuntu. Otherwise you can simply see it in the output of
+* uname as the 4th digit of the kernel. The UTS_UBUNTU_RELEASE_ABI is not in
+* the linux-source package, but in the linux-headers package. It begins to
+* appear in later releases of 14.04 and 14.10.
+*
+* Ex:
+* <Ubuntu 14.04.1>
+*  $uname -r
+*  3.13.0-45-generic
+* ABI is 45
+*
+* <Ubuntu 14.10>
+*  $uname -r
+*  3.16.0-23-generic
+* ABI is 23
+*/
 #ifndef UTS_UBUNTU_RELEASE_ABI
 #define UTS_UBUNTU_RELEASE_ABI 0
 #define UBUNTU_VERSION_CODE 0
 #else
 /* Ubuntu does not provide actual release version macro, so we use the kernel
- * version plus the ABI to generate a unique version code specific to Ubuntu.
- * In addition, we mask the lower 8 bits of LINUX_VERSION_CODE in order to
- * ignore differences in sublevel which are not important since we have the
- * ABI value. Otherwise, it becomes impossible to correlate ABI to version for
- * ordering checks.
- */
-#define UBUNTU_VERSION_CODE (((~0xFF & LINUX_VERSION_CODE) << 8) + \
-			     UTS_UBUNTU_RELEASE_ABI)
+* version plus the ABI to generate a unique version code specific to Ubuntu.
+* In addition, we mask the lower 8 bits of LINUX_VERSION_CODE in order to
+* ignore differences in sublevel which are not important since we have the
+* ABI value. Otherwise, it becomes impossible to correlate ABI to version for
+* ordering checks.
+*/
+#define UBUNTU_VERSION_CODE \
+	(((~0xFF & LINUX_VERSION_CODE) << 8) + UTS_UBUNTU_RELEASE_ABI)
 
 #if UTS_UBUNTU_RELEASE_ABI > 255
 #error UTS_UBUNTU_RELEASE_ABI is too large...
 #endif /* UTS_UBUNTU_RELEASE_ABI > 255 */
 
-#if ( LINUX_VERSION_CODE <= KERNEL_VERSION(3,0,0) )
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3, 0, 0))
 /* Our version code scheme does not make sense for non 3.x or newer kernels,
- * and we have no support in kcompat for this scenario. Thus, treat this as a
- * non-Ubuntu kernel. Possibly might be better to error here.
- */
+* and we have no support in kcompat for this scenario. Thus, treat this as a
+* non-Ubuntu kernel. Possibly might be better to error here.
+*/
 #define UTS_UBUNTU_RELEASE_ABI 0
 #define UBUNTU_VERSION_CODE 0
 #endif
@@ -668,106 +667,106 @@ struct _kc_ethtool_pauseparam {
 #endif
 
 /* Note that the 3rd digit is always zero, and will be ignored. This is
- * because Ubuntu kernels are based on x.y.0-ABI values, and while their linux
- * version codes are 3 digit, this 3rd digit is superseded by the ABI value.
- */
-#define UBUNTU_VERSION(a,b,c,d) ((KERNEL_VERSION(a,b,0) << 8) + (d))
+* because Ubuntu kernels are based on x.y.0-ABI values, and while their linux
+* version codes are 3 digit, this 3rd digit is superseded by the ABI value.
+*/
+#define UBUNTU_VERSION(a, b, c, d) ((KERNEL_VERSION(a, b, 0) << 8) + (d))
 
 /* SuSE version macros are the same as Linux kernel version macro */
 #ifndef SLE_VERSION
-#define SLE_VERSION(a,b,c)	KERNEL_VERSION(a,b,c)
+#define SLE_VERSION(a, b, c) KERNEL_VERSION(a, b, c)
 #endif
-#define SLE_LOCALVERSION(a,b,c)	KERNEL_VERSION(a,b,c)
+#define SLE_LOCALVERSION(a, b, c) KERNEL_VERSION(a, b, c)
 #ifdef CONFIG_SUSE_KERNEL
-#if ( LINUX_VERSION_CODE == KERNEL_VERSION(2,6,27) )
+#if (LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 27))
 /* SLES11 GA is 2.6.27 based */
-#define SLE_VERSION_CODE SLE_VERSION(11,0,0)
-#elif ( LINUX_VERSION_CODE == KERNEL_VERSION(2,6,32) )
+#define SLE_VERSION_CODE SLE_VERSION(11, 0, 0)
+#elif (LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 32))
 /* SLES11 SP1 is 2.6.32 based */
-#define SLE_VERSION_CODE SLE_VERSION(11,1,0)
-#elif ( LINUX_VERSION_CODE == KERNEL_VERSION(3,0,13) )
+#define SLE_VERSION_CODE SLE_VERSION(11, 1, 0)
+#elif (LINUX_VERSION_CODE == KERNEL_VERSION(3, 0, 13))
 /* SLES11 SP2 GA is 3.0.13-0.27 */
-#define SLE_VERSION_CODE SLE_VERSION(11,2,0)
-#elif ((LINUX_VERSION_CODE == KERNEL_VERSION(3,0,76)))
+#define SLE_VERSION_CODE SLE_VERSION(11, 2, 0)
+#elif ((LINUX_VERSION_CODE == KERNEL_VERSION(3, 0, 76)))
 /* SLES11 SP3 GA is 3.0.76-0.11 */
-#define SLE_VERSION_CODE SLE_VERSION(11,3,0)
-#elif (LINUX_VERSION_CODE == KERNEL_VERSION(3,0,101))
-  #if (SLE_LOCALVERSION_CODE < SLE_LOCALVERSION(0,8,0))
-  /* some SLES11sp2 update kernels up to 3.0.101-0.7.x */
-  #define SLE_VERSION_CODE SLE_VERSION(11,2,0)
-  #elif (SLE_LOCALVERSION_CODE < SLE_LOCALVERSION(63,0,0))
-  /* most SLES11sp3 update kernels */
-  #define SLE_VERSION_CODE SLE_VERSION(11,3,0)
-  #else
-  /* SLES11 SP4 GA (3.0.101-63) and update kernels 3.0.101-63+ */
-  #define SLE_VERSION_CODE SLE_VERSION(11,4,0)
-  #endif
-#elif (LINUX_VERSION_CODE == KERNEL_VERSION(3,12,28))
+#define SLE_VERSION_CODE SLE_VERSION(11, 3, 0)
+#elif (LINUX_VERSION_CODE == KERNEL_VERSION(3, 0, 101))
+#if (SLE_LOCALVERSION_CODE < SLE_LOCALVERSION(0, 8, 0))
+/* some SLES11sp2 update kernels up to 3.0.101-0.7.x */
+#define SLE_VERSION_CODE SLE_VERSION(11, 2, 0)
+#elif (SLE_LOCALVERSION_CODE < SLE_LOCALVERSION(63, 0, 0))
+/* most SLES11sp3 update kernels */
+#define SLE_VERSION_CODE SLE_VERSION(11, 3, 0)
+#else
+/* SLES11 SP4 GA (3.0.101-63) and update kernels 3.0.101-63+ */
+#define SLE_VERSION_CODE SLE_VERSION(11, 4, 0)
+#endif
+#elif (LINUX_VERSION_CODE == KERNEL_VERSION(3, 12, 28))
 /* SLES12 GA is 3.12.28-4
- * kernel updates 3.12.xx-<33 through 52>[.yy] */
-#define SLE_VERSION_CODE SLE_VERSION(12,0,0)
-#elif (LINUX_VERSION_CODE == KERNEL_VERSION(3,12,49))
+* kernel updates 3.12.xx-<33 through 52>[.yy] */
+#define SLE_VERSION_CODE SLE_VERSION(12, 0, 0)
+#elif (LINUX_VERSION_CODE == KERNEL_VERSION(3, 12, 49))
 /* SLES12 SP1 GA is 3.12.49-11
- * updates 3.12.xx-60.yy where xx={51..} */
-#define SLE_VERSION_CODE SLE_VERSION(12,1,0)
-#elif ((LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,21) && \
-       (LINUX_VERSION_CODE <= KERNEL_VERSION(4,4,59))) || \
-       (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,74) && \
-        LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0) && \
-        SLE_LOCALVERSION_CODE >= KERNEL_VERSION(92,0,0) && \
-        SLE_LOCALVERSION_CODE <  KERNEL_VERSION(93,0,0)))
+* updates 3.12.xx-60.yy where xx={51..} */
+#define SLE_VERSION_CODE SLE_VERSION(12, 1, 0)
+#elif ((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 21) &&    \
+		(LINUX_VERSION_CODE <= KERNEL_VERSION(4, 4, 59))) || \
+	(LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 74) &&    \
+		LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0) &&      \
+		SLE_LOCALVERSION_CODE >= KERNEL_VERSION(92, 0, 0) && \
+		SLE_LOCALVERSION_CODE < KERNEL_VERSION(93, 0, 0)))
 /* SLES12 SP2 GA is 4.4.21-69.
- * SLES12 SP2 updates before SLES12 SP3 are: 4.4.{21,38,49,59}
- * SLES12 SP2 updates after SLES12 SP3 are: 4.4.{74,90,103,114,120}
- * but they all use a SLE_LOCALVERSION_CODE matching 92.nn.y */
-#define SLE_VERSION_CODE SLE_VERSION(12,2,0)
-#elif ((LINUX_VERSION_CODE == KERNEL_VERSION(4,4,73) || \
-        LINUX_VERSION_CODE == KERNEL_VERSION(4,4,82) || \
-        LINUX_VERSION_CODE == KERNEL_VERSION(4,4,92)) || \
-       (LINUX_VERSION_CODE == KERNEL_VERSION(4,4,103) && \
-       (SLE_LOCALVERSION_CODE == KERNEL_VERSION(6,33,0) || \
-        SLE_LOCALVERSION_CODE == KERNEL_VERSION(6,38,0))) || \
-       (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,114) && \
-        LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0) && \
-        SLE_LOCALVERSION_CODE >= KERNEL_VERSION(94,0,0) && \
-        SLE_LOCALVERSION_CODE <  KERNEL_VERSION(95,0,0)) )
+* SLES12 SP2 updates before SLES12 SP3 are: 4.4.{21,38,49,59}
+* SLES12 SP2 updates after SLES12 SP3 are: 4.4.{74,90,103,114,120}
+* but they all use a SLE_LOCALVERSION_CODE matching 92.nn.y */
+#define SLE_VERSION_CODE SLE_VERSION(12, 2, 0)
+#elif ((LINUX_VERSION_CODE == KERNEL_VERSION(4, 4, 73) ||       \
+		LINUX_VERSION_CODE == KERNEL_VERSION(4, 4, 82) ||       \
+		LINUX_VERSION_CODE == KERNEL_VERSION(4, 4, 92)) ||      \
+	(LINUX_VERSION_CODE == KERNEL_VERSION(4, 4, 103) &&      \
+		(SLE_LOCALVERSION_CODE == KERNEL_VERSION(6, 33, 0) ||   \
+		SLE_LOCALVERSION_CODE == KERNEL_VERSION(6, 38, 0))) || \
+	(LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 114) &&      \
+		LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0) &&         \
+		SLE_LOCALVERSION_CODE >= KERNEL_VERSION(94, 0, 0) &&    \
+		SLE_LOCALVERSION_CODE < KERNEL_VERSION(95, 0, 0)))
 /* SLES12 SP3 GM is 4.4.73-5 and update kernels are 4.4.82-6.3.
- * SLES12 SP3 updates not conflicting with SP2 are: 4.4.{82,92}
- * SLES12 SP3 updates conflicting with SP2 are:
- *   - 4.4.103-6.33.1, 4.4.103-6.38.1
- *   - 4.4.{114,120}-94.nn.y */
-#define SLE_VERSION_CODE SLE_VERSION(12,3,0)
-#elif (LINUX_VERSION_CODE == KERNEL_VERSION(4,12,14) && \
-       (SLE_LOCALVERSION_CODE == KERNEL_VERSION(94,41,0) || \
-       (SLE_LOCALVERSION_CODE >= KERNEL_VERSION(95,0,0) && \
-        SLE_LOCALVERSION_CODE < KERNEL_VERSION(96,0,0))))
+* SLES12 SP3 updates not conflicting with SP2 are: 4.4.{82,92}
+* SLES12 SP3 updates conflicting with SP2 are:
+*   - 4.4.103-6.33.1, 4.4.103-6.38.1
+*   - 4.4.{114,120}-94.nn.y */
+#define SLE_VERSION_CODE SLE_VERSION(12, 3, 0)
+#elif (LINUX_VERSION_CODE == KERNEL_VERSION(4, 12, 14) &&     \
+	(SLE_LOCALVERSION_CODE == KERNEL_VERSION(94, 41, 0) || \
+		(SLE_LOCALVERSION_CODE >= KERNEL_VERSION(95, 0, 0) && \
+		SLE_LOCALVERSION_CODE < KERNEL_VERSION(96, 0, 0))))
 /* SLES12 SP4 GM is 4.12.14-94.41 and update kernel is 4.12.14-95.x. */
-#define SLE_VERSION_CODE SLE_VERSION(12,4,0)
-#elif (LINUX_VERSION_CODE == KERNEL_VERSION(4,12,14) && \
-       (SLE_LOCALVERSION_CODE == KERNEL_VERSION(23,0,0) || \
-        SLE_LOCALVERSION_CODE == KERNEL_VERSION(2,0,0) || \
-        SLE_LOCALVERSION_CODE == KERNEL_VERSION(136,0,0) || \
-        (SLE_LOCALVERSION_CODE >= KERNEL_VERSION(25,0,0) && \
-	 SLE_LOCALVERSION_CODE < KERNEL_VERSION(26,0,0)) || \
-	(SLE_LOCALVERSION_CODE >= KERNEL_VERSION(150,0,0) && \
-	 SLE_LOCALVERSION_CODE < KERNEL_VERSION(151,0,0))))
+#define SLE_VERSION_CODE SLE_VERSION(12, 4, 0)
+#elif (LINUX_VERSION_CODE == KERNEL_VERSION(4, 12, 14) &&      \
+	(SLE_LOCALVERSION_CODE == KERNEL_VERSION(23, 0, 0) ||   \
+		SLE_LOCALVERSION_CODE == KERNEL_VERSION(2, 0, 0) ||    \
+		SLE_LOCALVERSION_CODE == KERNEL_VERSION(136, 0, 0) ||  \
+		(SLE_LOCALVERSION_CODE >= KERNEL_VERSION(25, 0, 0) &&  \
+		SLE_LOCALVERSION_CODE < KERNEL_VERSION(26, 0, 0)) ||  \
+		(SLE_LOCALVERSION_CODE >= KERNEL_VERSION(150, 0, 0) && \
+		SLE_LOCALVERSION_CODE < KERNEL_VERSION(151, 0, 0))))
 /* SLES15 Beta1 is 4.12.14-2
- * SLES15 GM is 4.12.14-23 and update kernel is 4.12.14-{25,136},
- * and 4.12.14-150.14.
- */
-#define SLE_VERSION_CODE SLE_VERSION(15,0,0)
-#elif (LINUX_VERSION_CODE == KERNEL_VERSION(4,12,14) && \
-       SLE_LOCALVERSION_CODE >= KERNEL_VERSION(25,23,0))
+* SLES15 GM is 4.12.14-23 and update kernel is 4.12.14-{25,136},
+* and 4.12.14-150.14.
+*/
+#define SLE_VERSION_CODE SLE_VERSION(15, 0, 0)
+#elif (LINUX_VERSION_CODE == KERNEL_VERSION(4, 12, 14) && \
+	SLE_LOCALVERSION_CODE >= KERNEL_VERSION(25, 23, 0))
 /* SLES15 SP1 Beta1 is 4.12.14-25.23 */
-#define SLE_VERSION_CODE SLE_VERSION(15,1,0)
-#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,13))
+#define SLE_VERSION_CODE SLE_VERSION(15, 1, 0)
+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 13))
 /* SLES15 SP2 Beta1 is 5.3.13 */
-#define SLE_VERSION_CODE SLE_VERSION(15,2,0)
+#define SLE_VERSION_CODE SLE_VERSION(15, 2, 0)
 
 /* new SLES kernels must be added here with >= based on kernel
- * the idea is to order from newest to oldest and just catch all
- * of them using the >=
- */
+* the idea is to order from newest to oldest and just catch all
+* of them using the >=
+*/
 #endif /* LINUX_VERSION_CODE == KERNEL_VERSION(x,y,z) */
 #endif /* CONFIG_SUSE_KERNEL */
 #ifndef SLE_VERSION_CODE
@@ -778,32 +777,32 @@ struct _kc_ethtool_pauseparam {
 #endif /* SLE_LOCALVERSION_CODE */
 
 /*
- * ADQ depends on __TC_MQPRIO_MODE_MAX and related kernel code
- * added around 4.15. Some distributions (e.g. Oracle Linux 7.7)
- * have done a partial back-port of that to their kernels based
- * on older mainline kernels that did not include all the necessary
- * kernel enablement to support ADQ.
- * Undefine __TC_MQPRIO_MODE_MAX for all OSV distributions with
- * kernels based on mainline kernels older than 4.15 except for
- * RHEL, SLES and Ubuntu which are known to have good back-ports.
- */
+* ADQ depends on __TC_MQPRIO_MODE_MAX and related kernel code
+* added around 4.15. Some distributions (e.g. Oracle Linux 7.7)
+* have done a partial back-port of that to their kernels based
+* on older mainline kernels that did not include all the necessary
+* kernel enablement to support ADQ.
+* Undefine __TC_MQPRIO_MODE_MAX for all OSV distributions with
+* kernels based on mainline kernels older than 4.15 except for
+* RHEL, SLES and Ubuntu which are known to have good back-ports.
+*/
 #if (!RHEL_RELEASE_CODE && !SLE_VERSION_CODE && !UBUNTU_VERSION_CODE)
-  #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0))
-  #undef __TC_MQPRIO_MODE_MAX
-  #endif /*  LINUX_VERSION_CODE == KERNEL_VERSION(4,15,0) */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0))
+#undef __TC_MQPRIO_MODE_MAX
+#endif /*  LINUX_VERSION_CODE == KERNEL_VERSION(4,15,0) */
 #endif /* if (NOT RHEL && NOT SLES && NOT UBUNTU) */
 
 #ifdef __KLOCWORK__
 /* The following are not compiled into the binary driver; they are here
- * only to tune Klocwork scans to workaround false-positive issues.
- */
+* only to tune Klocwork scans to workaround false-positive issues.
+*/
 #ifdef ARRAY_SIZE
 #undef ARRAY_SIZE
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 #endif
 
-#define memcpy(dest, src, len)	memcpy_s(dest, len, src, len)
-#define memset(dest, ch, len)	memset_s(dest, len, ch, len)
+#define memcpy(dest, src, len) memcpy_s(dest, len, src, len)
+#define memset(dest, ch, len) memset_s(dest, len, ch, len)
 
 static inline int _kc_test_and_clear_bit(int nr, volatile unsigned long *addr)
 {
@@ -845,20 +844,20 @@ static inline int _kc_test_and_set_bit(int nr, volatile unsigned long *addr)
 #endif /* CONFIG_DYNAMIC_DEBUG */
 
 #undef hlist_for_each_entry_safe
-#define hlist_for_each_entry_safe(pos, n, head, member)			     \
-	for (n = NULL, pos = hlist_entry_safe((head)->first, typeof(*(pos)), \
-					      member);			     \
-	     pos;							     \
-	     pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member))
+#define hlist_for_each_entry_safe(pos, n, head, member)                \
+	for (n = NULL,                                                     \
+		pos = hlist_entry_safe((head)->first, typeof(*(pos)), member); \
+		pos;                                                          \
+		pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member))
 
 #ifdef uninitialized_var
 #undef uninitialized_var
-#define uninitialized_var(x) x = *(&(x))
+#define uninitialized_var(x) (x = *(&(x)))
 #endif
 
 #ifdef WRITE_ONCE
 #undef WRITE_ONCE
-#define WRITE_ONCE(x, val)	((x) = (val))
+#define WRITE_ONCE(x, val) ((x) = (val))
 #endif /* WRITE_ONCE */
 #endif /* __KLOCWORK__ */
 
@@ -867,36 +866,37 @@ struct vfd_objects *create_vfd_sysfs(struct pci_dev *pdev, int num_alloc_vfs);
 void destroy_vfd_sysfs(struct pci_dev *pdev, struct vfd_objects *vfd_obj);
 
 /* Older versions of GCC will trigger -Wformat-nonliteral warnings for const
- * char * strings. Unfortunately, the implementation of do_trace_printk does
- * this, in order to add a storage attribute to the memory. This was fixed in
- * GCC 5.1, but we still use older distributions built with GCC 4.x.
- *
- * The string pointer is only passed as a const char * to the __trace_bprintk
- * function. Since that function has the __printf attribute, it will trigger
- * the warnings. We can't remove the attribute, so instead we'll use the
- * __diag macro to disable -Wformat-nonliteral around the call to
- * __trace_bprintk.
- */
+* char * strings. Unfortunately, the implementation of do_trace_printk does
+* this, in order to add a storage attribute to the memory. This was fixed in
+* GCC 5.1, but we still use older distributions built with GCC 4.x.
+*
+* The string pointer is only passed as a const char * to the __trace_bprintk
+* function. Since that function has the __printf attribute, it will trigger
+* the warnings. We can't remove the attribute, so instead we'll use the
+* __diag macro to disable -Wformat-nonliteral around the call to
+* __trace_bprintk.
+*/
 #if GCC_VERSION < 50100
-#define __trace_bprintk(ip, fmt, args...) ({		\
-	int err;					\
-	__diag_push();					\
-	__diag(ignored "-Wformat-nonliteral");		\
-	err = __trace_bprintk(ip, fmt, ##args);		\
-	__diag_pop();					\
-	err;						\
-})
+#define __trace_bprintk(ip, fmt, args...)       \
+	({                                          \
+		int err;                                \
+		__diag_push();                          \
+		__diag(ignored "-Wformat-nonliteral");  \
+		err = __trace_bprintk(ip, fmt, ##args); \
+		__diag_pop();                           \
+		err;                                    \
+	})
 #endif /* GCC_VERSION < 5.1.0 */
 
 /* Newer kernels removed <linux/pci-aspm.h> */
-#if ((LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0)) && \
-     (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8,3)))
+#if ((LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) && \
+	(RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8, 3)))
 #define HAVE_PCI_ASPM_H
 #endif
 
 /*****************************************************************************/
 /* 2.4.3 => 2.4.0 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3))
 
 /**************************************/
 /* PCI DRIVER API */
@@ -921,7 +921,7 @@ void _kc_pci_release_regions(struct pci_dev *pdev);
 
 #ifndef alloc_etherdev
 #define alloc_etherdev _kc_alloc_etherdev
-struct net_device * _kc_alloc_etherdev(int sizeof_priv);
+struct net_device *_kc_alloc_etherdev(int sizeof_priv);
 #endif
 
 #ifndef is_valid_ether_addr
@@ -931,52 +931,53 @@ int _kc_is_valid_ether_addr(u8 *addr);
 
 /**************************************/
 #ifndef INIT_TQUEUE
-#define INIT_TQUEUE(_tq, _routine, _data)		\
-	do {						\
-		INIT_LIST_HEAD(&(_tq)->list);		\
-		(_tq)->sync = 0;			\
-		(_tq)->routine = _routine;		\
-		(_tq)->data = _data;			\
+#define INIT_TQUEUE(_tq, _routine, _data) \
+	do {                                  \
+		INIT_LIST_HEAD(&(_tq)->list);     \
+		(_tq)->sync = 0;                  \
+		(_tq)->routine = _routine;        \
+		(_tq)->data = _data;              \
 	} while (0)
 #endif
 
 #endif /* 2.4.3 => 2.4.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,5) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 5))
 /* Generic MII registers. */
-#define MII_BMCR            0x00        /* Basic mode control register */
-#define MII_BMSR            0x01        /* Basic mode status register  */
-#define MII_PHYSID1         0x02        /* PHYS ID 1                   */
-#define MII_PHYSID2         0x03        /* PHYS ID 2                   */
-#define MII_ADVERTISE       0x04        /* Advertisement control reg   */
-#define MII_LPA             0x05        /* Link partner ability reg    */
-#define MII_EXPANSION       0x06        /* Expansion register          */
+#define MII_BMCR 0x00 /* Basic mode control register */
+#define MII_BMSR 0x01 /* Basic mode status register  */
+#define MII_PHYSID1 0x02 /* PHYS ID 1                   */
+#define MII_PHYSID2 0x03 /* PHYS ID 2                   */
+#define MII_ADVERTISE 0x04 /* Advertisement control reg   */
+#define MII_LPA 0x05 /* Link partner ability reg    */
+#define MII_EXPANSION 0x06 /* Expansion register          */
 /* Basic mode control register. */
-#define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
-#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
+#define BMCR_FULLDPLX 0x0100 /* Full duplex                 */
+#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation     */
 /* Basic mode status register. */
-#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
-#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
-#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
-#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
-#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
-#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
+#define BMSR_ERCAP 0x0001 /* Ext-reg capability          */
+#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
+#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex  */
+#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex  */
+#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
+#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
 /* Advertisement control register. */
-#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
-#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
-#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
-#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
-#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
-#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
-                       ADVERTISE_100HALF | ADVERTISE_100FULL)
+#define ADVERTISE_CSMA 0x0001 /* Only selector supported     */
+#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex  */
+#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex  */
+#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
+#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
+#define ADVERTISE_ALL                                          \
+	(ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF | \
+	ADVERTISE_100FULL)
 /* Expansion register for auto-negotiation. */
-#define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
+#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words    */
 #endif
 
 /*****************************************************************************/
 /* 2.4.6 => 2.4.3 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 6))
 
 #ifndef pci_set_power_state
 #define pci_set_power_state _kc_pci_set_power_state
@@ -1000,44 +1001,52 @@ void _kc_pci_disable_device(struct pci_dev *pdev);
 
 /*****************************************************************************/
 /* 2.4.10 => 2.4.9 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,10) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 10))
 
 /**************************************/
 /* MODULE API */
 
 #ifndef MODULE_LICENSE
-	#define MODULE_LICENSE(X)
+#define MODULE_LICENSE(X)
 #endif
 
 /**************************************/
 /* OTHER */
 
 #undef min
-#define min(x,y) ({ \
-	const typeof(x) _x = (x);	\
-	const typeof(y) _y = (y);	\
-	(void) (&_x == &_y);		\
-	_x < _y ? _x : _y; })
+#define min(x, y)                 \
+	({                            \
+		const typeof(x) _x = (x); \
+		const typeof(y) _y = (y); \
+		(void)(&_x == &_y);       \
+		_x < _y ? _x : _y;        \
+	})
 
 #undef max
-#define max(x,y) ({ \
-	const typeof(x) _x = (x);	\
-	const typeof(y) _y = (y);	\
-	(void) (&_x == &_y);		\
-	_x > _y ? _x : _y; })
-
-#define min_t(type,x,y) ({ \
-	type _x = (x); \
-	type _y = (y); \
-	_x < _y ? _x : _y; })
-
-#define max_t(type,x,y) ({ \
-	type _x = (x); \
-	type _y = (y); \
-	_x > _y ? _x : _y; })
+#define max(x, y)                 \
+	({                            \
+		const typeof(x) _x = (x); \
+		const typeof(y) _y = (y); \
+		(void)(&_x == &_y);       \
+		_x > _y ? _x : _y;        \
+	})
+
+#define min_t(type, x, y)  \
+	({                     \
+		type _x = (x);     \
+		type _y = (y);     \
+		_x < _y ? _x : _y; \
+	})
+
+#define max_t(type, x, y)  \
+	({                     \
+		type _x = (x);     \
+		type _y = (y);     \
+		_x > _y ? _x : _y; \
+	})
 
 #ifndef list_for_each_safe
-#define list_for_each_safe(pos, n, head) \
+#define list_for_each_safe(pos, n, head)                   \
 	for (pos = (head)->next, n = pos->next; pos != (head); \
 		pos = n, n = pos->next)
 #endif
@@ -1050,90 +1059,91 @@ void _kc_pci_disable_device(struct pci_dev *pdev);
 #endif /* CONFIG_SMP */
 #endif
 
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,8) )
-int _kc_snprintf(char * buf, size_t size, const char *fmt, ...);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 8))
+int _kc_snprintf(char *buf, size_t size, const char *fmt, ...);
 #define snprintf(buf, size, fmt, args...) _kc_snprintf(buf, size, fmt, ##args)
 int _kc_vsnprintf(char *buf, size_t size, const char *fmt, va_list args);
 #define vsnprintf(buf, size, fmt, args) _kc_vsnprintf(buf, size, fmt, args)
 #else /* 2.4.8 => 2.4.9 */
-int snprintf(char * buf, size_t size, const char *fmt, ...);
+int snprintf(char *buf, size_t size, const char *fmt, ...);
 int vsnprintf(char *buf, size_t size, const char *fmt, va_list args);
 #endif
 #endif /* 2.4.10 -> 2.4.6 */
 
-
 /*****************************************************************************/
 /* 2.4.12 => 2.4.10 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,12) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 12))
 #ifndef HAVE_NETIF_MSG
 #define HAVE_NETIF_MSG 1
 enum {
-	NETIF_MSG_DRV		= 0x0001,
-	NETIF_MSG_PROBE		= 0x0002,
-	NETIF_MSG_LINK		= 0x0004,
-	NETIF_MSG_TIMER		= 0x0008,
-	NETIF_MSG_IFDOWN	= 0x0010,
-	NETIF_MSG_IFUP		= 0x0020,
-	NETIF_MSG_RX_ERR	= 0x0040,
-	NETIF_MSG_TX_ERR	= 0x0080,
-	NETIF_MSG_TX_QUEUED	= 0x0100,
-	NETIF_MSG_INTR		= 0x0200,
-	NETIF_MSG_TX_DONE	= 0x0400,
-	NETIF_MSG_RX_STATUS	= 0x0800,
-	NETIF_MSG_PKTDATA	= 0x1000,
-	NETIF_MSG_HW		= 0x2000,
-	NETIF_MSG_WOL		= 0x4000,
+	NETIF_MSG_DRV = 0x0001,
+	NETIF_MSG_PROBE = 0x0002,
+	NETIF_MSG_LINK = 0x0004,
+	NETIF_MSG_TIMER = 0x0008,
+	NETIF_MSG_IFDOWN = 0x0010,
+	NETIF_MSG_IFUP = 0x0020,
+	NETIF_MSG_RX_ERR = 0x0040,
+	NETIF_MSG_TX_ERR = 0x0080,
+	NETIF_MSG_TX_QUEUED = 0x0100,
+	NETIF_MSG_INTR = 0x0200,
+	NETIF_MSG_TX_DONE = 0x0400,
+	NETIF_MSG_RX_STATUS = 0x0800,
+	NETIF_MSG_PKTDATA = 0x1000,
+	NETIF_MSG_HW = 0x2000,
+	NETIF_MSG_WOL = 0x4000,
 };
 
-#define netif_msg_drv(p)	((p)->msg_enable & NETIF_MSG_DRV)
-#define netif_msg_probe(p)	((p)->msg_enable & NETIF_MSG_PROBE)
-#define netif_msg_link(p)	((p)->msg_enable & NETIF_MSG_LINK)
-#define netif_msg_timer(p)	((p)->msg_enable & NETIF_MSG_TIMER)
-#define netif_msg_ifdown(p)	((p)->msg_enable & NETIF_MSG_IFDOWN)
-#define netif_msg_ifup(p)	((p)->msg_enable & NETIF_MSG_IFUP)
-#define netif_msg_rx_err(p)	((p)->msg_enable & NETIF_MSG_RX_ERR)
-#define netif_msg_tx_err(p)	((p)->msg_enable & NETIF_MSG_TX_ERR)
-#define netif_msg_tx_queued(p)	((p)->msg_enable & NETIF_MSG_TX_QUEUED)
-#define netif_msg_intr(p)	((p)->msg_enable & NETIF_MSG_INTR)
-#define netif_msg_tx_done(p)	((p)->msg_enable & NETIF_MSG_TX_DONE)
-#define netif_msg_rx_status(p)	((p)->msg_enable & NETIF_MSG_RX_STATUS)
-#define netif_msg_pktdata(p)	((p)->msg_enable & NETIF_MSG_PKTDATA)
+#define netif_msg_drv(p) ((p)->msg_enable & NETIF_MSG_DRV)
+#define netif_msg_probe(p) ((p)->msg_enable & NETIF_MSG_PROBE)
+#define netif_msg_link(p) ((p)->msg_enable & NETIF_MSG_LINK)
+#define netif_msg_timer(p) ((p)->msg_enable & NETIF_MSG_TIMER)
+#define netif_msg_ifdown(p) ((p)->msg_enable & NETIF_MSG_IFDOWN)
+#define netif_msg_ifup(p) ((p)->msg_enable & NETIF_MSG_IFUP)
+#define netif_msg_rx_err(p) ((p)->msg_enable & NETIF_MSG_RX_ERR)
+#define netif_msg_tx_err(p) ((p)->msg_enable & NETIF_MSG_TX_ERR)
+#define netif_msg_tx_queued(p) ((p)->msg_enable & NETIF_MSG_TX_QUEUED)
+#define netif_msg_intr(p) ((p)->msg_enable & NETIF_MSG_INTR)
+#define netif_msg_tx_done(p) ((p)->msg_enable & NETIF_MSG_TX_DONE)
+#define netif_msg_rx_status(p) ((p)->msg_enable & NETIF_MSG_RX_STATUS)
+#define netif_msg_pktdata(p) ((p)->msg_enable & NETIF_MSG_PKTDATA)
 #endif /* !HAVE_NETIF_MSG */
 #endif /* 2.4.12 => 2.4.10 */
 
 /*****************************************************************************/
 /* 2.4.13 => 2.4.12 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 13))
 
 /**************************************/
 /* PCI DMA MAPPING */
 
 #ifndef virt_to_page
-	#define virt_to_page(v) (mem_map + (virt_to_phys(v) >> PAGE_SHIFT))
+#define virt_to_page(v) (mem_map + (virt_to_phys(v) >> PAGE_SHIFT))
 #endif
 
 #ifndef pci_map_page
 #define pci_map_page _kc_pci_map_page
-u64 _kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, size_t size, int direction);
+u64 _kc_pci_map_page(struct pci_dev *dev, struct page *page,
+					unsigned long offset, size_t size, int direction);
 #endif
 
 #ifndef pci_unmap_page
 #define pci_unmap_page _kc_pci_unmap_page
-void _kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size, int direction);
+void _kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size,
+						int direction);
 #endif
 
 /* pci_set_dma_mask takes dma_addr_t, which is only 32-bits prior to 2.4.13 */
 
 #undef DMA_32BIT_MASK
-#define DMA_32BIT_MASK	0xffffffff
+#define DMA_32BIT_MASK 0xffffffff
 #undef DMA_64BIT_MASK
-#define DMA_64BIT_MASK	0xffffffff
+#define DMA_64BIT_MASK 0xffffffff
 
 /**************************************/
 /* OTHER */
 
 #ifndef cpu_relax
-#define cpu_relax()	rep_nop()
+#define cpu_relax() rep_nop()
 #endif
 
 struct vlan_ethhdr {
@@ -1147,24 +1157,24 @@ struct vlan_ethhdr {
 
 /*****************************************************************************/
 /* 2.4.17 => 2.4.12 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 17))
 
 #ifndef __devexit_p
-	#define __devexit_p(x) &(x)
+#define __devexit_p(x) (&(x))
 #endif
 
 #endif /* 2.4.17 => 2.4.13 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,18) )
-#define NETIF_MSG_HW	0x2000
-#define NETIF_MSG_WOL	0x4000
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 18))
+#define NETIF_MSG_HW 0x2000
+#define NETIF_MSG_WOL 0x4000
 
 #ifndef netif_msg_hw
-#define netif_msg_hw(p)		((p)->msg_enable & NETIF_MSG_HW)
+#define netif_msg_hw(p) ((p)->msg_enable & NETIF_MSG_HW)
 #endif
 #ifndef netif_msg_wol
-#define netif_msg_wol(p)	((p)->msg_enable & NETIF_MSG_WOL)
+#define netif_msg_wol(p) ((p)->msg_enable & NETIF_MSG_WOL)
 #endif
 #endif /* 2.4.18 */
 
@@ -1172,7 +1182,7 @@ struct vlan_ethhdr {
 
 /*****************************************************************************/
 /* 2.4.20 => 2.4.19 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,20) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 20))
 
 /* we won't support NAPI on less than 2.4.20 */
 #ifdef NAPI
@@ -1183,21 +1193,21 @@ struct vlan_ethhdr {
 
 /*****************************************************************************/
 /* 2.4.22 => 2.4.17 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) )
-#define pci_name(x)	((x)->slot_name)
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 22))
+#define pci_name(x) ((x)->slot_name)
 
 #ifndef SUPPORTED_10000baseT_Full
-#define SUPPORTED_10000baseT_Full	BIT(12)
+#define SUPPORTED_10000baseT_Full BIT(12)
 #endif
 #ifndef ADVERTISED_10000baseT_Full
-#define ADVERTISED_10000baseT_Full	BIT(12)
+#define ADVERTISED_10000baseT_Full BIT(12)
 #endif
 #endif
 
 /*****************************************************************************/
 /*****************************************************************************/
 /* 2.4.23 => 2.4.22 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,23) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 23))
 /*****************************************************************************/
 #ifdef NAPI
 #ifndef netif_poll_disable
@@ -1234,33 +1244,34 @@ static inline void _kc_netif_tx_disable(struct net_device *dev)
 
 /*****************************************************************************/
 /* 2.6.4 => 2.6.0 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,25) || \
-    ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \
-      LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 25) ||  \
+	(LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0) && \
+	LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 4)))
 #define ETHTOOL_OPS_COMPAT
 #endif /* 2.6.4 => 2.6.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 27))
 #define __user
 #endif /* < 2.4.27 */
 
 /*****************************************************************************/
 /* 2.5.71 => 2.4.x */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,71) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 71))
 #define sk_protocol protocol
 #define pci_get_device pci_find_device
 #endif /* 2.5.70 => 2.4.x */
 
 /*****************************************************************************/
 /* < 2.4.27 or 2.6.0 <= 2.6.5 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) || \
-    ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \
-      LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 27) ||  \
+	(LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0) && \
+	LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 5)))
 
 #ifndef netif_msg_init
 #define netif_msg_init _kc_netif_msg_init
-static inline u32 _kc_netif_msg_init(int debug_value, int default_msg_enable_bits)
+static inline u32 _kc_netif_msg_init(int debug_value,
+									int default_msg_enable_bits)
 {
 	/* use default */
 	if (debug_value < 0 || debug_value >= (sizeof(u32) * 8))
@@ -1268,31 +1279,31 @@ static inline u32 _kc_netif_msg_init(int debug_value, int default_msg_enable_bit
 	if (debug_value == 0) /* no output */
 		return 0;
 	/* set low N bits */
-	return (1 << debug_value) -1;
+	return (1 << debug_value) - 1;
 }
 #endif
 
 #endif /* < 2.4.27 or 2.6.0 <= 2.6.5 */
 /*****************************************************************************/
-#if (( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) ) || \
-     (( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ) && \
-      ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) )))
+#if ((LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 27)) ||  \
+	((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)) && \
+	(LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 3))))
 #define netdev_priv(x) x->priv
 #endif
 
 /*****************************************************************************/
 /* <= 2.5.0 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0))
 #include <linux/rtnetlink.h>
 #undef pci_register_driver
 #define pci_register_driver pci_module_init
 
 /*
- * Most of the dma compat code is copied/modifed from the 2.4.37
- * /include/linux/libata-compat.h header file
- */
+* Most of the dma compat code is copied/modifed from the 2.4.37
+* /include/linux/libata-compat.h header file
+*/
 /* These definitions mirror those in pci.h, so they can be used
- * interchangeably with their PCI_ counterparts */
+* interchangeably with their PCI_ counterparts */
 enum dma_data_direction {
 	DMA_BIDIRECTIONAL = 0,
 	DMA_TO_DEVICE = 1,
@@ -1304,57 +1315,56 @@ struct device {
 	struct pci_dev pdev;
 };
 
-static inline struct pci_dev *to_pci_dev (struct device *dev)
+static inline struct pci_dev *to_pci_dev(struct device *dev)
 {
-	return (struct pci_dev *) dev;
+	return (struct pci_dev *)dev;
 }
 static inline struct device *pci_dev_to_dev(struct pci_dev *pdev)
 {
-	return (struct device *) pdev;
-}
-#define pdev_printk(lvl, pdev, fmt, args...) 	\
-	printk("%s %s: " fmt, lvl, pci_name(pdev), ## args)
-#define dev_err(dev, fmt, args...)            \
-	pdev_printk(KERN_ERR, to_pci_dev(dev), fmt, ## args)
-#define dev_info(dev, fmt, args...)            \
-	pdev_printk(KERN_INFO, to_pci_dev(dev), fmt, ## args)
-#define dev_warn(dev, fmt, args...)            \
-	pdev_printk(KERN_WARNING, to_pci_dev(dev), fmt, ## args)
-#define dev_notice(dev, fmt, args...)            \
-	pdev_printk(KERN_NOTICE, to_pci_dev(dev), fmt, ## args)
+	return (struct device *)pdev;
+}
+#define pdev_printk(lvl, pdev, fmt, args...) \
+	printk("%s %s: " fmt, lvl, pci_name(pdev), ##args)
+#define dev_err(dev, fmt, args...) \
+	pdev_printk(KERN_ERR, to_pci_dev(dev), fmt, ##args)
+#define dev_info(dev, fmt, args...) \
+	pdev_printk(KERN_INFO, to_pci_dev(dev), fmt, ##args)
+#define dev_warn(dev, fmt, args...) \
+	pdev_printk(KERN_WARNING, to_pci_dev(dev), fmt, ##args)
+#define dev_notice(dev, fmt, args...) \
+	pdev_printk(KERN_NOTICE, to_pci_dev(dev), fmt, ##args)
 #define dev_dbg(dev, fmt, args...) \
-	pdev_printk(KERN_DEBUG, to_pci_dev(dev), fmt, ## args)
+	pdev_printk(KERN_DEBUG, to_pci_dev(dev), fmt, ##args)
 
 /* NOTE: dangerous! we ignore the 'gfp' argument */
-#define dma_alloc_coherent(dev,sz,dma,gfp) \
-	pci_alloc_consistent(to_pci_dev(dev),(sz),(dma))
-#define dma_free_coherent(dev,sz,addr,dma_addr) \
-	pci_free_consistent(to_pci_dev(dev),(sz),(addr),(dma_addr))
+#define dma_alloc_coherent(dev, sz, dma, gfp) \
+	pci_alloc_consistent(to_pci_dev(dev), (sz), (dma))
+#define dma_free_coherent(dev, sz, addr, dma_addr) \
+	pci_free_consistent(to_pci_dev(dev), (sz), (addr), (dma_addr))
 
-#define dma_map_page(dev,a,b,c,d) \
-	pci_map_page(to_pci_dev(dev),(a),(b),(c),(d))
-#define dma_unmap_page(dev,a,b,c) \
-	pci_unmap_page(to_pci_dev(dev),(a),(b),(c))
+#define dma_map_page(dev, a, b, c, d) \
+	pci_map_page(to_pci_dev(dev), (a), (b), (c), (d))
+#define dma_unmap_page(dev, a, b, c) \
+	pci_unmap_page(to_pci_dev(dev), (a), (b), (c))
 
-#define dma_map_single(dev,a,b,c) \
-	pci_map_single(to_pci_dev(dev),(a),(b),(c))
-#define dma_unmap_single(dev,a,b,c) \
-	pci_unmap_single(to_pci_dev(dev),(a),(b),(c))
+#define dma_map_single(dev, a, b, c) \
+	pci_map_single(to_pci_dev(dev), (a), (b), (c))
+#define dma_unmap_single(dev, a, b, c) \
+	pci_unmap_single(to_pci_dev(dev), (a), (b), (c))
 
 #define dma_map_sg(dev, sg, nents, dir) \
-	pci_map_sg(to_pci_dev(dev), (sg), (nents), (dir)
+		(pci_map_sg(to_pci_dev(dev), (sg), (nents), (dir)))
 #define dma_unmap_sg(dev, sg, nents, dir) \
-	pci_unmap_sg(to_pci_dev(dev), (sg), (nents), (dir)
+		(pci_unmap_sg(to_pci_dev(dev), (sg), (nents), (dir)))
 
-#define dma_sync_single(dev,a,b,c) \
-	pci_dma_sync_single(to_pci_dev(dev),(a),(b),(c))
+#define dma_sync_single(dev, a, b, c) \
+	pci_dma_sync_single(to_pci_dev(dev), (a), (b), (c))
 
 /* for range just sync everything, that's all the pci API can do */
-#define dma_sync_single_range(dev,addr,off,sz,dir) \
-	pci_dma_sync_single(to_pci_dev(dev),(addr),(off)+(sz),(dir))
+#define dma_sync_single_range(dev, addr, off, sz, dir) \
+	pci_dma_sync_single(to_pci_dev(dev), (addr), (off) + (sz), (dir))
 
-#define dma_set_mask(dev,mask) \
-	pci_set_dma_mask(to_pci_dev(dev),(mask))
+#define dma_set_mask(dev, mask) pci_set_dma_mask(to_pci_dev(dev), (mask))
 
 /* hlist_* code - double linked lists */
 struct hlist_head {
@@ -1371,7 +1381,7 @@ static inline void __hlist_del(struct hlist_node *n)
 	struct hlist_node **pprev = n->pprev;
 	*pprev = next;
 	if (next)
-	next->pprev = pprev;
+		next->pprev = pprev;
 }
 
 static inline void hlist_del(struct hlist_node *n)
@@ -1395,8 +1405,11 @@ static inline int hlist_empty(const struct hlist_head *h)
 {
 	return !h->first;
 }
-#define HLIST_HEAD_INIT { .first = NULL }
-#define HLIST_HEAD(name) struct hlist_head name = {  .first = NULL }
+#define HLIST_HEAD_INIT \
+	{                   \
+		.first = NULL   \
+	}
+#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL }
 #define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL)
 static inline void INIT_HLIST_NODE(struct hlist_node *h)
 {
@@ -1416,12 +1429,12 @@ static inline struct device *pci_dev_to_dev(struct pci_dev *pdev)
 
 /*****************************************************************************/
 /* 2.5.28 => 2.4.23 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 28))
 
 #include <linux/tqueue.h>
 #define work_struct tq_struct
 #undef INIT_WORK
-#define INIT_WORK(a,b) INIT_TQUEUE(a,(void (*)(void *))b,a)
+#define INIT_WORK(a, b) INIT_TQUEUE(a, (void (*)(void *))b, a)
 #undef container_of
 #define container_of list_entry
 #define schedule_work schedule_task
@@ -1432,7 +1445,7 @@ static inline struct device *pci_dev_to_dev(struct pci_dev *pdev)
 
 /*****************************************************************************/
 /* 2.6.0 => 2.5.28 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
 #ifndef read_barrier_depends
 #define read_barrier_depends() rmb()
 #endif
@@ -1448,7 +1461,9 @@ struct __kc_callback_head {
 #undef get_cpu
 #define get_cpu() smp_processor_id()
 #undef put_cpu
-#define put_cpu() do { } while(0)
+#define put_cpu() \
+	do {          \
+	} while (0)
 #define MODULE_INFO(version, _version)
 #ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
 #define CONFIG_E1000_DISABLE_PACKET_SPLIT 1
@@ -1460,18 +1475,19 @@ struct __kc_callback_head {
 #define CONFIG_IGC_DISABLE_PACKET_SPLIT 1
 #endif
 
-#define dma_set_coherent_mask(dev,mask) 1
+#define dma_set_coherent_mask(dev, mask) 1
 
 #undef dev_put
 #define dev_put(dev) __dev_put(dev)
 
 #ifndef skb_fill_page_desc
 #define skb_fill_page_desc _kc_skb_fill_page_desc
-void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, int off, int size);
+void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page,
+							int off, int size);
 #endif
 
 #undef ALIGN
-#define ALIGN(x,a) (((x)+(a)-1)&~((a)-1))
+#define ALIGN(x, a) (((x) + (a)-1) & ~((a)-1))
 
 #ifndef page_count
 #define page_count(p) atomic_read(&(p)->count)
@@ -1483,14 +1499,14 @@ void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, int o
 #define MAX_NUMNODES 1
 
 /* find_first_bit and find_next bit are not defined for most
- * 2.4 kernels (except for the redhat 2.4.21 kernels
- */
+* 2.4 kernels (except for the redhat 2.4.21 kernels
+*/
 #include <linux/bitops.h>
-#define BITOP_WORD(nr)          ((nr) / BITS_PER_LONG)
+#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)
 #undef find_next_bit
 #define find_next_bit _kc_find_next_bit
 unsigned long _kc_find_next_bit(const unsigned long *addr, unsigned long size,
-				unsigned long offset);
+								unsigned long offset);
 #define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
 
 #ifndef netdev_name
@@ -1500,7 +1516,7 @@ static inline const char *_kc_netdev_name(const struct net_device *dev)
 		return "(unregistered net_device)";
 	return dev->name;
 }
-#define netdev_name(netdev)	_kc_netdev_name(netdev)
+#define netdev_name(netdev) _kc_netdev_name(netdev)
 #endif /* netdev_name */
 
 #ifndef strlcpy
@@ -1510,32 +1526,34 @@ size_t _kc_strlcpy(char *dest, const char *src, size_t size);
 
 #ifndef do_div
 #if BITS_PER_LONG == 64
-# define do_div(n,base) ({					\
-	uint32_t __base = (base);				\
-	uint32_t __rem;						\
-	__rem = ((uint64_t)(n)) % __base;			\
-	(n) = ((uint64_t)(n)) / __base;				\
-	__rem;							\
- })
+#define do_div(n, base)                   \
+	({                                    \
+		uint32_t __base = (base);         \
+		uint32_t __rem;                   \
+		__rem = ((uint64_t)(n)) % __base; \
+		(n) = ((uint64_t)(n)) / __base;   \
+		__rem;                            \
+	})
 #elif BITS_PER_LONG == 32
 uint32_t _kc__div64_32(uint64_t *dividend, uint32_t divisor);
-# define do_div(n,base) ({				\
-	uint32_t __base = (base);			\
-	uint32_t __rem;					\
-	if (likely(((n) >> 32) == 0)) {			\
-		__rem = (uint32_t)(n) % __base;		\
-		(n) = (uint32_t)(n) / __base;		\
-	} else 						\
-		__rem = _kc__div64_32(&(n), __base);	\
-	__rem;						\
- })
+#define do_div(n, base)                          \
+	({                                           \
+		uint32_t __base = (base);                \
+		uint32_t __rem;                          \
+		if (likely(((n) >> 32) == 0)) {          \
+			__rem = (uint32_t)(n) % __base;      \
+			(n) = (uint32_t)(n) / __base;        \
+		} else                                   \
+			__rem = _kc__div64_32(&(n), __base); \
+		__rem;                                   \
+	})
 #else /* BITS_PER_LONG == ?? */
-# error do_div() does not yet support the C64
+#error do_div() does not yet support the C64
 #endif /* BITS_PER_LONG */
 #endif /* do_div */
 
 #ifndef NSEC_PER_SEC
-#define NSEC_PER_SEC	1000000000L
+#define NSEC_PER_SEC 1000000000L
 #endif
 
 #undef HAVE_I2C_SUPPORT
@@ -1543,29 +1561,29 @@ uint32_t _kc__div64_32(uint64_t *dividend, uint32_t divisor);
 
 #endif /* 2.6.0 => 2.5.28 */
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 3))
 #define dma_pool pci_pool
 #define dma_pool_destroy pci_pool_destroy
 #define dma_pool_alloc pci_pool_alloc
 #define dma_pool_free pci_pool_free
 
-#define dma_pool_create(name,dev,size,align,allocation) \
-       pci_pool_create((name),to_pci_dev(dev),(size),(align),(allocation))
+#define dma_pool_create(name, dev, size, align, allocation) \
+	pci_pool_create((name), to_pci_dev(dev), (size), (align), (allocation))
 #endif /* < 2.6.3 */
 
 /*****************************************************************************/
 /* 2.6.4 => 2.6.0 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 4))
 #define MODULE_VERSION(_version) MODULE_INFO(version, _version)
 #endif /* 2.6.4 => 2.6.0 */
 
 /*****************************************************************************/
 /* 2.6.5 => 2.6.0 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) )
-#define dma_sync_single_for_cpu		dma_sync_single
-#define dma_sync_single_for_device	dma_sync_single
-#define dma_sync_single_range_for_cpu		dma_sync_single_range
-#define dma_sync_single_range_for_device	dma_sync_single_range
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 5))
+#define dma_sync_single_for_cpu dma_sync_single
+#define dma_sync_single_for_device dma_sync_single
+#define dma_sync_single_range_for_cpu dma_sync_single_range
+#define dma_sync_single_range_for_device dma_sync_single_range
 #ifndef pci_dma_mapping_error
 #define pci_dma_mapping_error _kc_pci_dma_mapping_error
 static inline int _kc_pci_dma_mapping_error(dma_addr_t dma_addr)
@@ -1576,36 +1594,36 @@ static inline int _kc_pci_dma_mapping_error(dma_addr_t dma_addr)
 #endif /* 2.6.5 => 2.6.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) )
-int _kc_scnprintf(char * buf, size_t size, const char *fmt, ...);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 4))
+int _kc_scnprintf(char *buf, size_t size, const char *fmt, ...);
 #define scnprintf(buf, size, fmt, args...) _kc_scnprintf(buf, size, fmt, ##args)
 #endif /* < 2.6.4 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,6) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 6))
 /* taken from 2.6 include/linux/bitmap.h */
 #undef bitmap_zero
 #define bitmap_zero _kc_bitmap_zero
 static inline void _kc_bitmap_zero(unsigned long *dst, int nbits)
 {
-        if (nbits <= BITS_PER_LONG)
-                *dst = 0UL;
-        else {
-                int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
-                memset(dst, 0, len);
-        }
+	if (nbits <= BITS_PER_LONG)
+		*dst = 0UL;
+	else {
+		int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
+		memset(dst, 0, len);
+	}
 }
 #define page_to_nid(x) 0
 
 #endif /* < 2.6.6 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 7))
 #undef if_mii
 #define if_mii _kc_if_mii
 static inline struct mii_ioctl_data *_kc_if_mii(struct ifreq *rq)
 {
-	return (struct mii_ioctl_data *) &rq->ifr_ifru;
+	return (struct mii_ioctl_data *)&rq->ifr_ifru;
 }
 
 #ifndef __force
@@ -1614,31 +1632,33 @@ static inline struct mii_ioctl_data *_kc_if_mii(struct ifreq *rq)
 #endif /* < 2.6.7 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 8))
 #ifndef PCI_EXP_DEVCTL
 #define PCI_EXP_DEVCTL 8
 #endif
 #ifndef PCI_EXP_DEVCTL_CERE
 #define PCI_EXP_DEVCTL_CERE 0x0001
 #endif
-#define PCI_EXP_FLAGS		2	/* Capabilities register */
-#define PCI_EXP_FLAGS_VERS	0x000f	/* Capability version */
-#define PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
-#define  PCI_EXP_TYPE_ENDPOINT	0x0	/* Express Endpoint */
-#define  PCI_EXP_TYPE_LEG_END	0x1	/* Legacy Endpoint */
-#define  PCI_EXP_TYPE_ROOT_PORT 0x4	/* Root Port */
-#define  PCI_EXP_TYPE_DOWNSTREAM 0x6	/* Downstream Port */
-#define PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
-#define PCI_EXP_DEVCAP		4	/* Device capabilities */
-#define PCI_EXP_DEVSTA		10	/* Device Status */
-#define msleep(x)	do { set_current_state(TASK_UNINTERRUPTIBLE); \
-				schedule_timeout((x * HZ)/1000 + 2); \
-			} while (0)
+#define PCI_EXP_FLAGS 2 /* Capabilities register */
+#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
+#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
+#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
+#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
+#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
+#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
+#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
+#define PCI_EXP_DEVCAP 4 /* Device capabilities */
+#define PCI_EXP_DEVSTA 10 /* Device Status */
+#define msleep(x)                                \
+	do {                                         \
+		set_current_state(TASK_UNINTERRUPTIBLE); \
+		schedule_timeout((x * HZ) / 1000 + 2);   \
+	} while (0)
 
 #endif /* < 2.6.8 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 9))
 #include <net/dsfield.h>
 #define __iomem
 
@@ -1646,13 +1666,13 @@ static inline struct mii_ioctl_data *_kc_if_mii(struct ifreq *rq)
 #define kcalloc(n, size, flags) _kc_kzalloc(((n) * (size)), flags)
 void *_kc_kzalloc(size_t size, int flags);
 #endif
-#define MSEC_PER_SEC    1000L
+#define MSEC_PER_SEC 1000L
 static inline unsigned int _kc_jiffies_to_msecs(const unsigned long j)
 {
 #if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ)
 	return (MSEC_PER_SEC / HZ) * j;
 #elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC)
-	return (j + (HZ / MSEC_PER_SEC) - 1)/(HZ / MSEC_PER_SEC);
+	return (j + (HZ / MSEC_PER_SEC) - 1) / (HZ / MSEC_PER_SEC);
 #else
 	return (j * MSEC_PER_SEC) / HZ;
 #endif
@@ -1683,7 +1703,7 @@ static inline unsigned long _kc_msleep_interruptible(unsigned int msecs)
 }
 
 /* Basic mode control register. */
-#define BMCR_SPEED1000		0x0040  /* MSB of Speed (1000)         */
+#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000)         */
 
 #ifndef __le16
 #define __le16 u16
@@ -1710,17 +1730,17 @@ static inline struct vlan_ethhdr *vlan_eth_hdr(const struct sk_buff *skb)
 }
 
 /* Wake-On-Lan options. */
-#define WAKE_PHY		BIT(0)
-#define WAKE_UCAST		BIT(1)
-#define WAKE_MCAST		BIT(2)
-#define WAKE_BCAST		BIT(3)
-#define WAKE_ARP		BIT(4)
-#define WAKE_MAGIC		BIT(5)
-#define WAKE_MAGICSECURE	BIT(6) /* only meaningful if WAKE_MAGIC */
+#define WAKE_PHY BIT(0)
+#define WAKE_UCAST BIT(1)
+#define WAKE_MCAST BIT(2)
+#define WAKE_BCAST BIT(3)
+#define WAKE_ARP BIT(4)
+#define WAKE_MAGIC BIT(5)
+#define WAKE_MAGICSECURE BIT(6) /* only meaningful if WAKE_MAGIC */
 
 #define skb_header_pointer _kc_skb_header_pointer
 static inline void *_kc_skb_header_pointer(const struct sk_buff *skb,
-					    int offset, int len, void *buffer)
+										int offset, int len, void *buffer)
 {
 	int hlen = skb_headlen(skb);
 
@@ -1753,20 +1773,21 @@ static inline void *_kc_skb_header_pointer(const struct sk_buff *skb,
 #endif /* < 2.6.9 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 10))
 #ifdef module_param_array_named
 #undef module_param_array_named
-#define module_param_array_named(name, array, type, nump, perm)          \
-	static struct kparam_array __param_arr_##name                    \
-	= { ARRAY_SIZE(array), nump, param_set_##type, param_get_##type, \
-	    sizeof(array[0]), array };                                   \
+#define module_param_array_named(name, array, type, nump, perm)      \
+	static struct kparam_array __param_arr_##name = {                \
+		ARRAY_SIZE(array), nump, param_set_##type, param_get_##type, \
+		sizeof(array[0]),  array                                     \
+	};                                                               \
 	module_param_call(name, param_array_set, param_array_get,        \
-			  &__param_arr_##name, perm)
+					&__param_arr_##name, perm)
 #endif /* module_param_array_named */
 /*
- * num_online is broken for all < 2.6.10 kernels.  This is needed to support
- * Node module parameter of ixgbe.
- */
+* num_online is broken for all < 2.6.10 kernels.  This is needed to support
+* Node module parameter of ixgbe.
+*/
 #undef num_online_nodes
 #define num_online_nodes(n) 1
 extern DECLARE_BITMAP(_kcompat_node_online_map, MAX_NUMNODES);
@@ -1776,16 +1797,16 @@ extern DECLARE_BITMAP(_kcompat_node_online_map, MAX_NUMNODES);
 #endif /* < 2.6.10 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) )
-#define PCI_D0      0
-#define PCI_D1      1
-#define PCI_D2      2
-#define PCI_D3hot   3
-#define PCI_D3cold  4
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 11))
+#define PCI_D0 0
+#define PCI_D1 1
+#define PCI_D2 2
+#define PCI_D3hot 3
+#define PCI_D3cold 4
 typedef int pci_power_t;
-#define pci_choose_state(pdev,state) state
+#define pci_choose_state(pdev, state) state
 #define PMSG_SUSPEND 3
-#define PCI_EXP_LNKCTL	16
+#define PCI_EXP_LNKCTL 16
 
 #undef NETIF_F_LLTX
 
@@ -1797,14 +1818,14 @@ typedef int pci_power_t;
 #define NET_IP_ALIGN 2
 #endif
 
-#define KC_USEC_PER_SEC	1000000L
+#define KC_USEC_PER_SEC 1000000L
 #define usecs_to_jiffies _kc_usecs_to_jiffies
 static inline unsigned int _kc_jiffies_to_usecs(const unsigned long j)
 {
 #if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ)
 	return (KC_USEC_PER_SEC / HZ) * j;
 #elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC)
-	return (j + (HZ / KC_USEC_PER_SEC) - 1)/(HZ / KC_USEC_PER_SEC);
+	return (j + (HZ / KC_USEC_PER_SEC) - 1) / (HZ / KC_USEC_PER_SEC);
 #else
 	return (j * KC_USEC_PER_SEC) / HZ;
 #endif
@@ -1822,36 +1843,36 @@ static inline unsigned long _kc_usecs_to_jiffies(const unsigned int m)
 #endif
 }
 
-#define PCI_EXP_LNKCAP		12	/* Link Capabilities */
-#define PCI_EXP_LNKSTA		18	/* Link Status */
-#define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
-#define PCI_EXP_SLTCTL		24	/* Slot Control */
-#define PCI_EXP_SLTSTA		26	/* Slot Status */
-#define PCI_EXP_RTCTL		28	/* Root Control */
-#define PCI_EXP_RTCAP		30	/* Root Capabilities */
-#define PCI_EXP_RTSTA		32	/* Root Status */
+#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
+#define PCI_EXP_LNKSTA 18 /* Link Status */
+#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
+#define PCI_EXP_SLTCTL 24 /* Slot Control */
+#define PCI_EXP_SLTSTA 26 /* Slot Status */
+#define PCI_EXP_RTCTL 28 /* Root Control */
+#define PCI_EXP_RTCAP 30 /* Root Capabilities */
+#define PCI_EXP_RTSTA 32 /* Root Status */
 #endif /* < 2.6.11 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,12) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 12))
 #include <linux/reboot.h>
 #define USE_REBOOT_NOTIFIER
 
 /* Generic MII registers. */
-#define MII_CTRL1000        0x09        /* 1000BASE-T control          */
-#define MII_STAT1000        0x0a        /* 1000BASE-T status           */
+#define MII_CTRL1000 0x09 /* 1000BASE-T control          */
+#define MII_STAT1000 0x0a /* 1000BASE-T status           */
 /* Advertisement control register. */
-#define ADVERTISE_PAUSE_CAP     0x0400  /* Try for pause               */
-#define ADVERTISE_PAUSE_ASYM    0x0800  /* Try for asymmetric pause     */
+#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause               */
+#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymmetric pause     */
 /* Link partner ability register. */
-#define LPA_PAUSE_CAP		0x0400	/* Can pause                   */
-#define LPA_PAUSE_ASYM		0x0800	/* Can pause asymetrically     */
+#define LPA_PAUSE_CAP 0x0400 /* Can pause                   */
+#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically     */
 /* 1000BASE-T Control register */
-#define ADVERTISE_1000FULL      0x0200  /* Advertise 1000BASE-T full duplex */
-#define ADVERTISE_1000HALF	0x0100  /* Advertise 1000BASE-T half duplex */
+#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
+#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
 /* 1000BASE-T Status register */
-#define LPA_1000LOCALRXOK	0x2000	/* Link partner local receiver status */
-#define LPA_1000REMRXOK		0x1000	/* Link partner remote receiver status */
+#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
+#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
 
 #ifndef is_zero_ether_addr
 #define is_zero_ether_addr _kc_is_zero_ether_addr
@@ -1870,7 +1891,7 @@ static inline int _kc_is_multicast_ether_addr(const u8 *addr)
 #endif /* < 2.6.12 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 13))
 #ifndef kstrdup
 #define kstrdup _kc_kstrdup
 char *_kc_kstrdup(const char *s, unsigned int gfp);
@@ -1878,7 +1899,7 @@ char *_kc_kstrdup(const char *s, unsigned int gfp);
 #endif /* < 2.6.13 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 14))
 #define pm_message_t u32
 #ifndef kzalloc
 #define kzalloc _kc_kzalloc
@@ -1886,67 +1907,71 @@ void *_kc_kzalloc(size_t size, int flags);
 #endif
 
 /* Generic MII registers. */
-#define MII_ESTATUS	    0x0f	/* Extended Status */
+#define MII_ESTATUS 0x0f /* Extended Status */
 /* Basic mode status register. */
-#define BMSR_ESTATEN		0x0100	/* Extended Status in R15 */
+#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
 /* Extended status register. */
-#define ESTATUS_1000_TFULL	0x2000	/* Can do 1000BT Full */
-#define ESTATUS_1000_THALF	0x1000	/* Can do 1000BT Half */
-
-#define SUPPORTED_Pause	        BIT(13)
-#define SUPPORTED_Asym_Pause	BIT(14)
-#define ADVERTISED_Pause	BIT(13)
-#define ADVERTISED_Asym_Pause	BIT(14)
-
-#if (!(RHEL_RELEASE_CODE && \
-       (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4,3)) && \
-       (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0))))
-#if ((LINUX_VERSION_CODE == KERNEL_VERSION(2,6,9)) && !defined(gfp_t))
+#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
+#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
+
+#define SUPPORTED_Pause BIT(13)
+#define SUPPORTED_Asym_Pause BIT(14)
+#define ADVERTISED_Pause BIT(13)
+#define ADVERTISED_Asym_Pause BIT(14)
+
+#if (!(RHEL_RELEASE_CODE &&                                \
+	(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4, 3)) && \
+	(RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5, 0))))
+#if ((LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 9)) && !defined(gfp_t))
 #define gfp_t unsigned
 #else
 typedef unsigned gfp_t;
 #endif
 #endif /* !RHEL4.3->RHEL5.0 */
 
-#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,9) )
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 9))
 #ifdef CONFIG_X86_64
-#define dma_sync_single_range_for_cpu(dev, addr, off, sz, dir)       \
+#define dma_sync_single_range_for_cpu(dev, addr, off, sz, dir) \
 	dma_sync_single_for_cpu((dev), (addr), (off) + (sz), (dir))
-#define dma_sync_single_range_for_device(dev, addr, off, sz, dir)    \
+#define dma_sync_single_range_for_device(dev, addr, off, sz, dir) \
 	dma_sync_single_for_device((dev), (addr), (off) + (sz), (dir))
 #endif
 #endif
 #endif /* < 2.6.14 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 15))
 #ifndef kfree_rcu
 /* this is placed here due to a lack of rcu_barrier in previous kernels */
 #define kfree_rcu(_ptr, _offset) kfree(_ptr)
 #endif /* kfree_rcu */
 #ifndef vmalloc_node
-#define vmalloc_node(a,b) vmalloc(a)
+#define vmalloc_node(a, b) vmalloc(a)
 #endif /* vmalloc_node*/
 
 #define setup_timer(_timer, _function, _data) \
-do { \
-	(_timer)->function = _function; \
-	(_timer)->data = _data; \
-	init_timer(_timer); \
-} while (0)
+	do {                                      \
+		(_timer)->function = _function;       \
+		(_timer)->data = _data;               \
+		init_timer(_timer);                   \
+	} while (0)
 #ifndef device_can_wakeup
-#define device_can_wakeup(dev)	(1)
+#define device_can_wakeup(dev) (1)
 #endif
 #ifndef device_set_wakeup_enable
-#define device_set_wakeup_enable(dev, val)	do{}while(0)
+#define device_set_wakeup_enable(dev, val) \
+	do {                                   \
+	} while (0)
 #endif
 #ifndef device_init_wakeup
-#define device_init_wakeup(dev,val) do {} while (0)
+#define device_init_wakeup(dev, val) \
+	do {                             \
+	} while (0)
 #endif
 static inline unsigned _kc_compare_ether_addr(const u8 *addr1, const u8 *addr2)
 {
-	const u16 *a = (const u16 *) addr1;
-	const u16 *b = (const u16 *) addr2;
+	const u16 *a = (const u16 *)addr1;
+	const u16 *b = (const u16 *)addr2;
 
 	return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) != 0;
 }
@@ -1955,11 +1980,11 @@ static inline unsigned _kc_compare_ether_addr(const u8 *addr1, const u8 *addr2)
 #endif /* < 2.6.15 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 16))
 #undef DEFINE_MUTEX
-#define DEFINE_MUTEX(x)	DECLARE_MUTEX(x)
-#define mutex_lock(x)	down_interruptible(x)
-#define mutex_unlock(x)	up(x)
+#define DEFINE_MUTEX(x) DECLARE_MUTEX(x)
+#define mutex_lock(x) down_interruptible(x)
+#define mutex_unlock(x) up(x)
 
 #ifndef ____cacheline_internodealigned_in_smp
 #ifdef CONFIG_SMP
@@ -1972,7 +1997,7 @@ static inline unsigned _kc_compare_ether_addr(const u8 *addr1, const u8 *addr2)
 #else /* 2.6.16 and above */
 #undef HAVE_PCI_ERS
 #define HAVE_PCI_ERS
-#if ( SLE_VERSION_CODE && SLE_VERSION_CODE == SLE_VERSION(10,4,0) )
+#if (SLE_VERSION_CODE && SLE_VERSION_CODE == SLE_VERSION(10, 4, 0))
 #ifdef device_can_wakeup
 #undef device_can_wakeup
 #endif /* device_can_wakeup */
@@ -1981,10 +2006,9 @@ static inline unsigned _kc_compare_ether_addr(const u8 *addr1, const u8 *addr2)
 #endif /* < 2.6.16 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,17) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 17))
 #ifndef dev_notice
-#define dev_notice(dev, fmt, args...)            \
-	dev_printk(KERN_NOTICE, dev, fmt, ## args)
+#define dev_notice(dev, fmt, args...) dev_printk(KERN_NOTICE, dev, fmt, ##args)
 #endif
 
 #ifndef first_online_node
@@ -1996,7 +2020,7 @@ static inline unsigned _kc_compare_ether_addr(const u8 *addr1, const u8 *addr2)
 #endif /* < 2.6.17 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
 
 #ifndef IRQ_HANDLED
 #define irqreturn_t void
@@ -2039,89 +2063,89 @@ static inline int _kc_skb_is_gso(const struct sk_buff *skb)
 #ifdef skb_pad
 #undef skb_pad
 #endif
-#define skb_pad(x,y) _kc_skb_pad(x, y)
+#define skb_pad(x, y) _kc_skb_pad(x, y)
 int _kc_skb_pad(struct sk_buff *skb, int pad);
 #ifdef skb_padto
 #undef skb_padto
 #endif
-#define skb_padto(x,y) _kc_skb_padto(x, y)
+#define skb_padto(x, y) _kc_skb_padto(x, y)
 static inline int _kc_skb_padto(struct sk_buff *skb, unsigned int len)
 {
 	unsigned int size = skb->len;
-	if(likely(size >= len))
+	if (likely(size >= len))
 		return 0;
 	return _kc_skb_pad(skb, len - size);
 }
 
 #ifndef DECLARE_PCI_UNMAP_ADDR
-#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
-	dma_addr_t ADDR_NAME
-#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
-	u32 LEN_NAME
-#define pci_unmap_addr(PTR, ADDR_NAME) \
-	((PTR)->ADDR_NAME)
-#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
-	(((PTR)->ADDR_NAME) = (VAL))
-#define pci_unmap_len(PTR, LEN_NAME) \
-	((PTR)->LEN_NAME)
-#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
-	(((PTR)->LEN_NAME) = (VAL))
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) u32 LEN_NAME
+#define pci_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
+#define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
 #endif /* DECLARE_PCI_UNMAP_ADDR */
 #endif /* < 2.6.18 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19))
 enum pcie_link_width {
-	PCIE_LNK_WIDTH_RESRV    = 0x00,
-	PCIE_LNK_X1             = 0x01,
-	PCIE_LNK_X2             = 0x02,
-	PCIE_LNK_X4             = 0x04,
-	PCIE_LNK_X8             = 0x08,
-	PCIE_LNK_X12            = 0x0C,
-	PCIE_LNK_X16            = 0x10,
-	PCIE_LNK_X32            = 0x20,
-	PCIE_LNK_WIDTH_UNKNOWN  = 0xFF,
+	PCIE_LNK_WIDTH_RESRV = 0x00,
+	PCIE_LNK_X1 = 0x01,
+	PCIE_LNK_X2 = 0x02,
+	PCIE_LNK_X4 = 0x04,
+	PCIE_LNK_X8 = 0x08,
+	PCIE_LNK_X12 = 0x0C,
+	PCIE_LNK_X16 = 0x10,
+	PCIE_LNK_X32 = 0x20,
+	PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
 };
 
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,0)))
+#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5, 0)))
 #define i_private u.generic_ip
 #endif /* >= RHEL 5.0 */
 
 #ifndef DIV_ROUND_UP
-#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+#define DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d))
 #endif
 #ifndef __ALIGN_MASK
 #define __ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))
 #endif
-#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) )
-#if (!((RHEL_RELEASE_CODE && \
-        ((RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4,4) && \
-          RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0)) || \
-         (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,0))))))
-typedef irqreturn_t (*irq_handler_t)(int, void*, struct pt_regs *);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 0))
+#if (!((RHEL_RELEASE_CODE &&                                 \
+		((RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4, 4) &&  \
+		RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5, 0)) || \
+		(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5, 0))))))
+typedef irqreturn_t (*irq_handler_t)(int, void *, struct pt_regs *);
 #endif
-#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0))
+#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6, 0))
 #undef CONFIG_INET_LRO
 #undef CONFIG_INET_LRO_MODULE
 #endif
-typedef irqreturn_t (*new_handler_t)(int, void*);
-static inline irqreturn_t _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id)
+typedef irqreturn_t (*new_handler_t)(int, void *);
+static inline irqreturn_t _kc_request_irq(unsigned int irq,
+										new_handler_t handler,
+										unsigned long flags,
+										const char *devname, void *dev_id)
 #else /* 2.4.x */
-typedef void (*irq_handler_t)(int, void*, struct pt_regs *);
-typedef void (*new_handler_t)(int, void*);
-static inline int _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id)
+typedef void (*irq_handler_t)(int, void *, struct pt_regs *);
+typedef void (*new_handler_t)(int, void *);
+static inline int _kc_request_irq(unsigned int irq, new_handler_t handler,
+								unsigned long flags, const char *devname,
+								void *dev_id)
 #endif /* >= 2.5.x */
 {
-	irq_handler_t new_handler = (irq_handler_t) handler;
+	irq_handler_t new_handler = (irq_handler_t)handler;
 	return request_irq(irq, new_handler, flags, devname, dev_id);
 }
 
 #undef request_irq
-#define request_irq(irq, handler, flags, devname, dev_id) _kc_request_irq((irq), (handler), (flags), (devname), (dev_id))
+#define request_irq(irq, handler, flags, devname, dev_id) \
+	_kc_request_irq((irq), (handler), (flags), (devname), (dev_id))
 
 #define irq_handler_t new_handler_t
 
-#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11) )
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 11))
 #ifndef skb_checksum_help
 static inline int __kc_skb_checksum_help(struct sk_buff *skb)
 {
@@ -2132,11 +2156,13 @@ static inline int __kc_skb_checksum_help(struct sk_buff *skb)
 #endif /* < 2.6.19 && >= 2.6.11 */
 
 /* pci_restore_state and pci_save_state handles MSI/PCIE from 2.6.19 */
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,4)))
+#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5, 4)))
 #define PCIE_CONFIG_SPACE_LEN 256
 #define PCI_CONFIG_SPACE_LEN 64
 #define PCIE_LINK_STATUS 0x12
-#define pci_config_space_ich8lan() do {} while(0)
+#define pci_config_space_ich8lan() \
+	do {                           \
+	} while (0)
 #undef pci_save_state
 int _kc_pci_save_state(struct pci_dev *);
 #define pci_save_state(pdev) _kc_pci_save_state(pdev)
@@ -2150,12 +2176,17 @@ void _kc_pci_restore_state(struct pci_dev *);
 void _kc_free_netdev(struct net_device *);
 #define free_netdev(netdev) _kc_free_netdev(netdev)
 #endif
-static inline int pci_enable_pcie_error_reporting(struct pci_dev __always_unused *dev)
+static inline int
+pci_enable_pcie_error_reporting(struct pci_dev __always_unused *dev)
 {
 	return 0;
 }
-#define pci_disable_pcie_error_reporting(dev) do {} while (0)
-#define pci_cleanup_aer_uncorrect_error_status(dev) do {} while (0)
+#define pci_disable_pcie_error_reporting(dev) \
+	do {                                      \
+	} while (0)
+#define pci_cleanup_aer_uncorrect_error_status(dev) \
+	do {                                            \
+	} while (0)
 
 void *_kc_kmemdup(const void *src, size_t len, unsigned gfp);
 #define kmemdup(src, len, gfp) _kc_kmemdup(src, len, gfp)
@@ -2172,23 +2203,22 @@ void *_kc_kmemdup(const void *src, size_t len, unsigned gfp);
 #endif /* < 2.6.19 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) )
-#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,28) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20))
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 28))
 #undef INIT_WORK
-#define INIT_WORK(_work, _func) \
-do { \
-	INIT_LIST_HEAD(&(_work)->entry); \
-	(_work)->pending = 0; \
-	(_work)->func = (void (*)(void *))_func; \
-	(_work)->data = _work; \
-	init_timer(&(_work)->timer); \
-} while (0)
+#define INIT_WORK(_work, _func)                  \
+	do {                                         \
+		INIT_LIST_HEAD(&(_work)->entry);         \
+		(_work)->pending = 0;                    \
+		(_work)->func = (void (*)(void *))_func; \
+		(_work)->data = _work;                   \
+		init_timer(&(_work)->timer);             \
+	} while (0)
 #endif
 
 #ifndef PCI_VDEVICE
-#define PCI_VDEVICE(ven, dev)        \
-	PCI_VENDOR_ID_##ven, (dev),  \
-	PCI_ANY_ID, PCI_ANY_ID, 0, 0
+#define PCI_VDEVICE(ven, dev) \
+	(PCI_VENDOR_ID_##ven, (dev), PCI_ANY_ID, PCI_ANY_ID, 0, 0)
 #endif
 
 #ifndef PCI_VENDOR_ID_INTEL
@@ -2205,22 +2235,25 @@ do { \
 #define dev_to_node(dev) -1
 #undef set_dev_node
 /* remove compiler warning with b=b, for unused variable */
-#define set_dev_node(a, b) do { (b) = (b); } while(0)
+#define set_dev_node(a, b) \
+	do {                   \
+		(b) = (b);         \
+	} while (0)
 
-#if (!(RHEL_RELEASE_CODE && \
-       (((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(4,7)) && \
-         (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0))) || \
-        (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,6)))) && \
-     !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(10,2,0)))
+#if (!(RHEL_RELEASE_CODE &&                                    \
+	(((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(4, 7)) &&  \
+		(RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5, 0))) ||  \
+		(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5, 6)))) && \
+	!(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(10, 2, 0)))
 typedef __u16 __bitwise __sum16;
 typedef __u32 __bitwise __wsum;
 #endif
 
-#if (!(RHEL_RELEASE_CODE && \
-       (((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(4,7)) && \
-         (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0))) || \
-        (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,4)))) && \
-     !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(10,2,0)))
+#if (!(RHEL_RELEASE_CODE &&                                    \
+	(((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(4, 7)) &&  \
+		(RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5, 0))) ||  \
+		(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5, 4)))) && \
+	!(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(10, 2, 0)))
 static inline __wsum csum_unfold(__sum16 n)
 {
 	return (__force __wsum)n;
@@ -2232,29 +2265,29 @@ static inline __wsum csum_unfold(__sum16 n)
 #endif /* < 2.6.20 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 21))
 #define to_net_dev(class) container_of(class, struct net_device, class_dev)
 #define NETDEV_CLASS_DEV
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,5)))
+#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5, 5)))
 #define vlan_group_get_device(vg, id) (vg->vlan_devices[id])
-#define vlan_group_set_device(vg, id, dev)		\
-	do {						\
-		if (vg) vg->vlan_devices[id] = dev;	\
+#define vlan_group_set_device(vg, id, dev) \
+	do {                                   \
+		if (vg)                            \
+			vg->vlan_devices[id] = dev;    \
 	} while (0)
 #endif /* !(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,5)) */
-#define pci_channel_offline(pdev) (pdev->error_state && \
-	pdev->error_state != pci_channel_io_normal)
+#define pci_channel_offline(pdev) \
+	(pdev->error_state && pdev->error_state != pci_channel_io_normal)
 #define pci_request_selected_regions(pdev, bars, name) \
-        pci_request_regions(pdev, name)
+	pci_request_regions(pdev, name)
 #define pci_release_selected_regions(pdev, bars) pci_release_regions(pdev);
 
 #ifndef __aligned
-#define __aligned(x)			__attribute__((aligned(x)))
+#define __aligned(x) __attribute__((aligned(x)))
 #endif
 
 struct pci_dev *_kc_netdev_to_pdev(struct net_device *netdev);
-#define netdev_to_dev(netdev)	\
-	pci_dev_to_dev(_kc_netdev_to_pdev(netdev))
+#define netdev_to_dev(netdev) pci_dev_to_dev(_kc_netdev_to_pdev(netdev))
 #define devm_kzalloc(dev, size, flags) kzalloc(size, flags)
 #define devm_kfree(dev, p) kfree(p)
 #else /* 2.6.21 */
@@ -2266,7 +2299,7 @@ static inline struct device *netdev_to_dev(struct net_device *netdev)
 #endif /* < 2.6.21 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22))
 #define tcp_hdr(skb) (skb->h.th)
 #define tcp_hdrlen(skb) (skb->h.th->doff << 2)
 #define skb_transport_offset(skb) (skb->h.raw - skb->data)
@@ -2277,17 +2310,16 @@ static inline struct device *netdev_to_dev(struct net_device *netdev)
 #define skb_network_header(skb) (skb->nh.raw)
 #define skb_tail_pointer(skb) skb->tail
 #define skb_reset_tail_pointer(skb) \
-	do { \
-		skb->tail = skb->data; \
+	do {                            \
+		skb->tail = skb->data;      \
 	} while (0)
 #define skb_set_tail_pointer(skb, offset) \
-	do { \
-		skb->tail = skb->data + offset; \
+	do {                                  \
+		skb->tail = skb->data + offset;   \
 	} while (0)
-#define skb_copy_to_linear_data(skb, from, len) \
-				memcpy(skb->data, from, len)
+#define skb_copy_to_linear_data(skb, from, len) memcpy(skb->data, from, len)
 #define skb_copy_to_linear_data_offset(skb, offset, from, len) \
-				memcpy(skb->data + offset, from, len)
+	memcpy(skb->data + offset, from, len)
 #define skb_network_header_len(skb) (skb->h.raw - skb->nh.raw)
 #define pci_register_driver pci_module_init
 #define skb_mac_header(skb) skb->mac.raw
@@ -2315,22 +2347,18 @@ static inline struct udphdr *_udp_hdr(const struct sk_buff *skb)
 #endif
 #define cpu_to_be16(x) __constant_htons(x)
 
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,1)))
-enum {
-	DUMP_PREFIX_NONE,
-	DUMP_PREFIX_ADDRESS,
-	DUMP_PREFIX_OFFSET
-};
+#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5, 1)))
+enum { DUMP_PREFIX_NONE, DUMP_PREFIX_ADDRESS, DUMP_PREFIX_OFFSET };
 #endif /* !(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,1)) */
 #ifndef hex_asc
-#define hex_asc(x)	"0123456789abcdef"[x]
+#define hex_asc(x) "0123456789abcdef"[x]
 #endif
 #include <linux/ctype.h>
 void _kc_print_hex_dump(const char *level, const char *prefix_str,
-			int prefix_type, int rowsize, int groupsize,
-			const void *buf, size_t len, bool ascii);
+						int prefix_type, int rowsize, int groupsize,
+						const void *buf, size_t len, bool ascii);
 #define print_hex_dump(lvl, s, t, r, g, b, l, a) \
-		_kc_print_hex_dump(lvl, s, t, r, g, b, l, a)
+	_kc_print_hex_dump(lvl, s, t, r, g, b, l, a)
 #ifndef ADVERTISED_2500baseX_Full
 #define ADVERTISED_2500baseX_Full BIT(15)
 #endif
@@ -2351,7 +2379,7 @@ static inline int compound_order(struct page *page)
 
 #ifndef SKB_WITH_OVERHEAD
 #define SKB_WITH_OVERHEAD(X) \
-	((X) - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
+	((X)-SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
 #endif
 #else /* 2.6.22 */
 #define ETH_TYPE_TRANS_SETS_DEV
@@ -2359,21 +2387,21 @@ static inline int compound_order(struct page *page)
 #endif /* < 2.6.22 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22) )
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22))
 #endif /* > 2.6.22 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 23))
 #define netif_subqueue_stopped(_a, _b) 0
 #ifndef PTR_ALIGN
-#define PTR_ALIGN(p, a)         ((typeof(p))ALIGN((unsigned long)(p), (a)))
+#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a)))
 #endif
 
 #ifndef CONFIG_PM_SLEEP
-#define CONFIG_PM_SLEEP	CONFIG_PM
+#define CONFIG_PM_SLEEP CONFIG_PM
 #endif
 
-#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) )
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 13))
 #define HAVE_ETHTOOL_GET_PERM_ADDR
 #endif /* 2.6.14 through 2.6.22 */
 
@@ -2385,15 +2413,14 @@ static inline int __kc_skb_cow_head(struct sk_buff *skb, unsigned int headroom)
 		delta = headroom - (skb->data - skb->head);
 
 	if (delta || skb_header_cloned(skb))
-		return pskb_expand_head(skb, ALIGN(delta, NET_SKB_PAD), 0,
-					GFP_ATOMIC);
+		return pskb_expand_head(skb, ALIGN(delta, NET_SKB_PAD), 0, GFP_ATOMIC);
 	return 0;
 }
 #define skb_cow_head(s, h) __kc_skb_cow_head((s), (h))
 #endif /* < 2.6.23 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
 #ifndef ETH_FLAG_LRO
 #define ETH_FLAG_LRO NETIF_F_LRO
 #endif
@@ -2416,14 +2443,15 @@ struct napi_struct {
 #ifdef NAPI
 int __kc_adapter_clean(struct net_device *, int *);
 /* The following definitions are multi-queue aware, and thus we have a driver
- * define list which determines which drivers support multiple queues, and
- * thus need these stronger defines. If a driver does not support multi-queue
- * functionality, you don't need to add it to this list.
- */
+* define list which determines which drivers support multiple queues, and
+* thus need these stronger defines. If a driver does not support multi-queue
+* functionality, you don't need to add it to this list.
+*/
 struct net_device *napi_to_poll_dev(const struct napi_struct *napi);
 
-static inline void __kc_mq_netif_napi_add(struct net_device *dev, struct napi_struct *napi,
-					  int (*poll)(struct napi_struct *, int), int weight)
+static inline void
+__kc_mq_netif_napi_add(struct net_device *dev, struct napi_struct *napi,
+					int (*poll)(struct napi_struct *, int), int weight)
 {
 	struct net_device *poll_dev = napi_to_poll_dev(napi);
 	poll_dev->poll = __kc_adapter_clean;
@@ -2475,7 +2503,7 @@ static inline void napi_synchronize(const struct napi_struct *n)
 	}
 }
 #else
-#define napi_synchronize(n)	barrier()
+#define napi_synchronize(n) barrier()
 #endif /* CONFIG_SMP */
 #define __napi_schedule(_napi) __netif_rx_schedule(napi_to_poll_dev(_napi))
 static inline void _kc_napi_complete(struct napi_struct *napi)
@@ -2490,8 +2518,10 @@ static inline void _kc_napi_complete(struct napi_struct *napi)
 
 /* The following definitions are only used if we don't support NAPI at all. */
 
-static inline __kc_netif_napi_add(struct net_device *dev, struct napi_struct *napi,
-				  int (*poll)(struct napi_struct *, int), int weight)
+static inline __kc_netif_napi_add(struct net_device *dev,
+								struct napi_struct *napi,
+								int (*poll)(struct napi_struct *, int),
+								int weight)
 {
 	dev->poll = poll;
 	dev->weight = weight;
@@ -2499,14 +2529,16 @@ static inline __kc_netif_napi_add(struct net_device *dev, struct napi_struct *na
 	napi->weight = weight;
 	napi->dev = dev;
 }
-#define netif_napi_del(_a) do {} while (0)
+#define netif_napi_del(_a) \
+	do {                   \
+	} while (0)
 #endif /* NAPI */
 
 #undef dev_get_by_name
 #define dev_get_by_name(_a, _b) dev_get_by_name(_b)
 #define __netif_subqueue_stopped(_a, _b) netif_subqueue_stopped(_a, _b)
 #ifndef DMA_BIT_MASK
-#define DMA_BIT_MASK(n)	(((n) == 64) ? DMA_64BIT_MASK : ((1ULL<<(n))-1))
+#define DMA_BIT_MASK(n) (((n) == 64) ? DMA_64BIT_MASK : ((1ULL << (n)) - 1))
 #endif
 
 #ifdef NETIF_F_TSO6
@@ -2518,19 +2550,16 @@ static inline int _kc_skb_is_gso_v6(const struct sk_buff *skb)
 #endif /* NETIF_F_TSO6 */
 
 #ifndef KERN_CONT
-#define KERN_CONT	""
+#define KERN_CONT ""
 #endif
 #ifndef pr_err
-#define pr_err(fmt, arg...) \
-	printk(KERN_ERR fmt, ##arg)
+#define pr_err(fmt, arg...) printk(KERN_ERR fmt, ##arg)
 #endif
 
 #ifndef rounddown_pow_of_two
-#define rounddown_pow_of_two(n) \
-	__builtin_constant_p(n) ? ( \
-		(n == 1) ? 0 : \
-		(1UL << ilog2(n))) : \
-		(1UL << (fls_long(n) - 1))
+#define rounddown_pow_of_two(n)                                    \
+	(__builtin_constant_p(n) ? ((n == 1) ? 0 : (1UL << ilog2(n))) : \
+								(1UL << (fls_long(n) - 1)))
 #endif
 
 #else /* < 2.6.24 */
@@ -2539,8 +2568,8 @@ static inline int _kc_skb_is_gso_v6(const struct sk_buff *skb)
 #endif /* < 2.6.24 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,24) )
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) )
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 24))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0))
 #define INCLUDE_PM_QOS_PARAMS_H
 #include <linux/pm_qos_params.h>
 #else /* >= 3.2.0 */
@@ -2549,28 +2578,29 @@ static inline int _kc_skb_is_gso_v6(const struct sk_buff *skb)
 #endif /* > 2.6.24 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25) )
-#define PM_QOS_CPU_DMA_LATENCY	1
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25))
+#define PM_QOS_CPU_DMA_LATENCY 1
 
-#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18) )
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18))
 #include <linux/latency.h>
-#define PM_QOS_DEFAULT_VALUE	INFINITE_LATENCY
+#define PM_QOS_DEFAULT_VALUE INFINITE_LATENCY
 #define pm_qos_add_requirement(pm_qos_class, name, value) \
-		set_acceptable_latency(name, value)
+	set_acceptable_latency(name, value)
 #define pm_qos_remove_requirement(pm_qos_class, name) \
-		remove_acceptable_latency(name)
+	remove_acceptable_latency(name)
 #define pm_qos_update_requirement(pm_qos_class, name, value) \
-		modify_acceptable_latency(name, value)
+	modify_acceptable_latency(name, value)
 #else
-#define PM_QOS_DEFAULT_VALUE	-1
+#define PM_QOS_DEFAULT_VALUE -1
 #define pm_qos_add_requirement(pm_qos_class, name, value)
 #define pm_qos_remove_requirement(pm_qos_class, name)
-#define pm_qos_update_requirement(pm_qos_class, name, value) { \
-	if (value != PM_QOS_DEFAULT_VALUE) { \
-		printk(KERN_WARNING "%s: unable to set PM QoS requirement\n", \
-			pci_name(adapter->pdev)); \
-	} \
-}
+#define pm_qos_update_requirement(pm_qos_class, name, value)              \
+	{                                                                     \
+		if (value != PM_QOS_DEFAULT_VALUE) {                              \
+			printk(KERN_WARNING "%s: unable to set PM QoS requirement\n", \
+				pci_name(adapter->pdev));                              \
+		}                                                                 \
+	}
 
 #endif /* > 2.6.18 */
 
@@ -2582,7 +2612,8 @@ static inline int _kc_skb_is_gso_v6(const struct sk_buff *skb)
 
 #ifndef strict_strtol
 #define strict_strtol(s, b, r) _kc_strict_strtol(s, b, r)
-static inline int _kc_strict_strtol(const char *buf, unsigned int base, long *res)
+static inline int _kc_strict_strtol(const char *buf, unsigned int base,
+									long *res)
 {
 	/* adapted from strict_strtoul() in 2.6.25 */
 	char *tail;
@@ -2597,7 +2628,7 @@ static inline int _kc_strict_strtol(const char *buf, unsigned int base, long *re
 	if (tail == buf)
 		return -EINVAL;
 	if ((*tail == '\0') ||
-	    ((len == (size_t)(tail - buf) + 1) && (*tail == '\n'))) {
+		((len == (size_t)(tail - buf) + 1) && (*tail == '\n'))) {
 		*res = val;
 		return 0;
 	}
@@ -2611,14 +2642,16 @@ static inline int _kc_strict_strtol(const char *buf, unsigned int base, long *re
 #endif /* < 2.6.25 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))
 #ifndef clamp_t
-#define clamp_t(type, val, min, max) ({		\
-	type __val = (val);			\
-	type __min = (min);			\
-	type __max = (max);			\
-	__val = __val < __min ? __min : __val;	\
-	__val > __max ? __max : __val; })
+#define clamp_t(type, val, min, max)           \
+	({                                         \
+		type __val = (val);                    \
+		type __min = (min);                    \
+		type __max = (max);                    \
+		__val = __val < __min ? __min : __val; \
+		__val > __max ? __max : __val;         \
+	})
 #endif /* clamp_t */
 #undef kzalloc_node
 #define kzalloc_node(_size, _flags, _node) kzalloc(_size, _flags)
@@ -2636,9 +2669,9 @@ void _kc_pci_disable_link_state(struct pci_dev *dev, int state);
 #endif /* PCI_EXP_LNKCAP_ASPMS */
 #endif /* < 2.6.26 */
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27))
 static inline void _kc_ethtool_cmd_speed_set(struct ethtool_cmd *ep,
-					     __u32 speed)
+											__u32 speed)
 {
 	ep->speed = (__u16)speed;
 	/* ep->speed_hi = (__u16)(speed >> 16); */
@@ -2652,31 +2685,32 @@ static inline __u32 _kc_ethtool_cmd_speed(struct ethtool_cmd *ep)
 }
 #define ethtool_cmd_speed _kc_ethtool_cmd_speed
 
-#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) )
-#if ((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) && defined(CONFIG_PM))
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 15))
+#if ((LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 23)) && defined(CONFIG_PM))
 #define ANCIENT_PM 1
-#elif ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,23)) && \
-       (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) && \
-       defined(CONFIG_PM_SLEEP))
+#elif ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 23)) && \
+	(LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26)) &&  \
+	defined(CONFIG_PM_SLEEP))
 #define NEWER_PM 1
 #endif
 #if defined(ANCIENT_PM) || defined(NEWER_PM)
 #undef device_set_wakeup_enable
-#define device_set_wakeup_enable(dev, val) \
-	do { \
-		u16 pmc = 0; \
-		int pm = pci_find_capability(adapter->pdev, PCI_CAP_ID_PM); \
-		if (pm) { \
-			pci_read_config_word(adapter->pdev, pm + PCI_PM_PMC, \
-				&pmc); \
-		} \
-		(dev)->power.can_wakeup = !!(pmc >> 11); \
-		(dev)->power.should_wakeup = (val && (pmc >> 11)); \
+#define device_set_wakeup_enable(dev, val)                              \
+	do {                                                                \
+		u16 pmc = 0;                                                    \
+		int pm = pci_find_capability(adapter->pdev, PCI_CAP_ID_PM);     \
+		if (pm) {                                                       \
+			pci_read_config_word(adapter->pdev, pm + PCI_PM_PMC, &pmc); \
+		}                                                               \
+		(dev)->power.can_wakeup = !!(pmc >> 11);                        \
+		(dev)->power.should_wakeup = (val && (pmc >> 11));              \
 	} while (0)
 #endif /* 2.6.15-2.6.22 and CONFIG_PM or 2.6.23-2.6.25 and CONFIG_PM_SLEEP */
 #endif /* 2.6.15 through 2.6.27 */
 #ifndef netif_napi_del
-#define netif_napi_del(_a) do {} while (0)
+#define netif_napi_del(_a) \
+	do {                   \
+	} while (0)
 #ifdef NAPI
 #ifdef CONFIG_NETPOLL
 #undef netif_napi_del
@@ -2705,29 +2739,33 @@ void _kc_netif_tx_start_all_queues(struct net_device *);
 #define netif_tx_wake_all_queues(a) _kc_netif_tx_wake_all_queues(a)
 #define netif_tx_start_all_queues(a) _kc_netif_tx_start_all_queues(a)
 #undef netif_stop_subqueue
-#define netif_stop_subqueue(_ndev,_qi) do { \
-	if (netif_is_multiqueue((_ndev))) \
-		netif_stop_subqueue((_ndev), (_qi)); \
-	else \
-		netif_stop_queue((_ndev)); \
+#define netif_stop_subqueue(_ndev, _qi)          \
+	do {                                         \
+		if (netif_is_multiqueue((_ndev)))        \
+			netif_stop_subqueue((_ndev), (_qi)); \
+		else                                     \
+			netif_stop_queue((_ndev));           \
 	} while (0)
 #undef netif_start_subqueue
-#define netif_start_subqueue(_ndev,_qi) do { \
-	if (netif_is_multiqueue((_ndev))) \
-		netif_start_subqueue((_ndev), (_qi)); \
-	else \
-		netif_start_queue((_ndev)); \
+#define netif_start_subqueue(_ndev, _qi)          \
+	do {                                          \
+		if (netif_is_multiqueue((_ndev)))         \
+			netif_start_subqueue((_ndev), (_qi)); \
+		else                                      \
+			netif_start_queue((_ndev));           \
 	} while (0)
 #else /* HAVE_TX_MQ */
 #define netif_tx_stop_all_queues(a) netif_stop_queue(a)
 #define netif_tx_wake_all_queues(a) netif_wake_queue(a)
-#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12) )
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 12))
 #define netif_tx_start_all_queues(a) netif_start_queue(a)
 #else
-#define netif_tx_start_all_queues(a) do {} while (0)
+#define netif_tx_start_all_queues(a) \
+	do {                             \
+	} while (0)
 #endif
-#define netif_stop_subqueue(_ndev,_qi) netif_stop_queue((_ndev))
-#define netif_start_subqueue(_ndev,_qi) netif_start_queue((_ndev))
+#define netif_stop_subqueue(_ndev, _qi) netif_stop_queue((_ndev))
+#define netif_start_subqueue(_ndev, _qi) netif_start_queue((_ndev))
 #endif /* HAVE_TX_MQ */
 #ifndef NETIF_F_MULTI_QUEUE
 #define NETIF_F_MULTI_QUEUE 0
@@ -2736,18 +2774,19 @@ void _kc_netif_tx_start_all_queues(struct net_device *);
 #endif /* NETIF_F_MULTI_QUEUE */
 
 #ifndef __WARN_printf
-void __kc_warn_slowpath(const char *file, const int line,
-		const char *fmt, ...) __attribute__((format(printf, 3, 4)));
+void __kc_warn_slowpath(const char *file, const int line, const char *fmt, ...)
+		__attribute__((format(printf, 3, 4)));
 #define __WARN_printf(arg...) __kc_warn_slowpath(__FILE__, __LINE__, arg)
 #endif /* __WARN_printf */
 
 #ifndef WARN
-#define WARN(condition, format...) ({						\
-	int __ret_warn_on = !!(condition);				\
-	if (unlikely(__ret_warn_on))					\
-		__WARN_printf(format);					\
-	unlikely(__ret_warn_on);					\
-})
+#define WARN(condition, format...)         \
+	({                                     \
+		int __ret_warn_on = !!(condition); \
+		if (unlikely(__ret_warn_on))       \
+			__WARN_printf(format);         \
+		unlikely(__ret_warn_on);           \
+	})
 #endif /* WARN */
 #undef HAVE_IXGBE_DEBUG_FS
 #undef HAVE_IGB_DEBUG_FS
@@ -2756,7 +2795,7 @@ void __kc_warn_slowpath(const char *file, const int line,
 #include <net/sch_generic.h>
 #define ethtool_cmd_speed_set _kc_ethtool_cmd_speed_set
 static inline void _kc_ethtool_cmd_speed_set(struct ethtool_cmd *ep,
-					     __u32 speed)
+											__u32 speed)
 {
 	ep->speed = (__u16)(speed & 0xFFFF);
 	ep->speed_hi = (__u16)(speed >> 16);
@@ -2770,9 +2809,9 @@ static inline void _kc_ethtool_cmd_speed_set(struct ethtool_cmd *ep,
 #endif /* < 2.6.27 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) )
-#define pci_ioremap_bar(pdev, bar)	ioremap(pci_resource_start(pdev, bar), \
-					        pci_resource_len(pdev, bar))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 28))
+#define pci_ioremap_bar(pdev, bar) \
+	ioremap(pci_resource_start(pdev, bar), pci_resource_len(pdev, bar))
 #define pci_wake_from_d3 _kc_pci_wake_from_d3
 #define pci_prepare_to_sleep _kc_pci_prepare_to_sleep
 int _kc_pci_wake_from_d3(struct pci_dev *dev, bool enable);
@@ -2787,49 +2826,53 @@ static inline void __kc_skb_queue_head_init(struct sk_buff_head *list)
 #define __skb_queue_head_init(_q) __kc_skb_queue_head_init(_q)
 #endif
 
-#define PCI_EXP_DEVCAP2		36	/* Device Capabilities 2 */
-#define PCI_EXP_DEVCTL2		40	/* Device Control 2 */
+#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
+#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
 
-#define PCI_EXP_DEVCAP_FLR	0x10000000 /* Function Level Reset */
-#define PCI_EXP_DEVCTL_BCR_FLR	0x8000 /* Bridge Configuration Retry / FLR */
+#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
+#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
 
 #endif /* < 2.6.28 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29))
 #ifndef swap
-#define swap(a, b) \
-	do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
+#define swap(a, b)             \
+	do {                       \
+		typeof(a) __tmp = (a); \
+		(a) = (b);             \
+		(b) = __tmp;           \
+	} while (0)
 #endif
 #define pci_request_selected_regions_exclusive(pdev, bars, name) \
-		pci_request_selected_regions(pdev, bars, name)
+	pci_request_selected_regions(pdev, bars, name)
 #ifndef CONFIG_NR_CPUS
 #define CONFIG_NR_CPUS 1
 #endif /* CONFIG_NR_CPUS */
 #ifndef pcie_aspm_enabled
-#define pcie_aspm_enabled()   (1)
+#define pcie_aspm_enabled() (1)
 #endif /* pcie_aspm_enabled */
 
-#define  PCI_EXP_SLTSTA_PDS	0x0040	/* Presence Detect State */
+#define PCI_EXP_SLTSTA_PDS 0x0040 /* Presence Detect State */
 
 #ifndef PCI_EXP_LNKSTA_CLS
-#define  PCI_EXP_LNKSTA_CLS    0x000f  /* Current Link Speed */
+#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
 #endif
 #ifndef PCI_EXP_LNKSTA_NLW
-#define  PCI_EXP_LNKSTA_NLW    0x03f0  /* Negotiated Link Width */
+#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
 #endif
 
 #ifndef pci_clear_master
 void _kc_pci_clear_master(struct pci_dev *dev);
-#define pci_clear_master(dev)	_kc_pci_clear_master(dev)
+#define pci_clear_master(dev) _kc_pci_clear_master(dev)
 #endif
 
 #ifndef PCI_EXP_LNKCTL_ASPMC
-#define  PCI_EXP_LNKCTL_ASPMC	0x0003	/* ASPM Control */
+#define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */
 #endif
 
 #ifndef PCI_EXP_LNKCAP_MLW
-#define PCI_EXP_LNKCAP_MLW	0x000003f0 /* Maximum Link Width */
+#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
 #endif
 
 #else /* < 2.6.29 */
@@ -2842,25 +2885,28 @@ void _kc_pci_clear_master(struct pci_dev *dev);
 #endif /* < 2.6.29 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 30))
 #define NO_PTP_SUPPORT
 #define skb_rx_queue_recorded(a) false
 #define skb_get_rx_queue(a) 0
-#define skb_record_rx_queue(a, b) do {} while (0)
+#define skb_record_rx_queue(a, b) \
+	do {                          \
+	} while (0)
 #define skb_tx_hash(n, s) ___kc_skb_tx_hash((n), (s), (n)->real_num_tx_queues)
 #ifndef CONFIG_PCI_IOV
 #undef pci_enable_sriov
 #define pci_enable_sriov(a, b) -ENOTSUPP
 #undef pci_disable_sriov
-#define pci_disable_sriov(a) do {} while (0)
+#define pci_disable_sriov(a) \
+	do {                     \
+	} while (0)
 #endif /* CONFIG_PCI_IOV */
 #ifndef pr_cont
-#define pr_cont(fmt, ...) \
-	printk(KERN_CONT fmt, ##__VA_ARGS__)
+#define pr_cont(fmt, ...) printk(KERN_CONT fmt, ##__VA_ARGS__)
 #endif /* pr_cont */
 static inline void _kc_synchronize_irq(unsigned int a)
 {
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 28))
 	synchronize_irq();
 #else /* < 2.5.28 */
 	synchronize_irq(a);
@@ -2869,18 +2915,18 @@ static inline void _kc_synchronize_irq(unsigned int a)
 #undef synchronize_irq
 #define synchronize_irq(a) _kc_synchronize_irq(a)
 
-#define PCI_EXP_LNKCTL2		48	/* Link Control 2 */
+#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
 
 #ifdef nr_cpus_node
 #undef nr_cpus_node
 #define nr_cpus_node(node) cpumask_weight(cpumask_of_node(node))
 #endif
 
-#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,5))
+#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5, 5))
 #define HAVE_PCI_DEV_IS_VIRTFN_BIT
 #endif /* RHEL >= 5.5 */
 
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,5)))
+#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5, 5)))
 static inline bool pci_is_root_bus(struct pci_bus *pbus)
 {
 	return !(pbus->parent);
@@ -2893,9 +2939,9 @@ static inline bool pci_is_root_bus(struct pci_bus *pbus)
 #endif /* < 2.6.30 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31))
 #define ETH_P_1588 0x88F7
-#define ETH_P_FIP  0x8914
+#define ETH_P_FIP 0x8914
 #ifndef netdev_uc_count
 #define netdev_uc_count(dev) ((dev)->uc_count)
 #endif
@@ -2917,23 +2963,23 @@ static inline bool pci_is_root_bus(struct pci_bus *pbus)
 #endif
 
 #ifndef SUPPORTED_1000baseKX_Full
-#define SUPPORTED_1000baseKX_Full	BIT(17)
+#define SUPPORTED_1000baseKX_Full BIT(17)
 #endif
 #ifndef SUPPORTED_10000baseKX4_Full
-#define SUPPORTED_10000baseKX4_Full	BIT(18)
+#define SUPPORTED_10000baseKX4_Full BIT(18)
 #endif
 #ifndef SUPPORTED_10000baseKR_Full
-#define SUPPORTED_10000baseKR_Full	BIT(19)
+#define SUPPORTED_10000baseKR_Full BIT(19)
 #endif
 
 #ifndef ADVERTISED_1000baseKX_Full
-#define ADVERTISED_1000baseKX_Full	BIT(17)
+#define ADVERTISED_1000baseKX_Full BIT(17)
 #endif
 #ifndef ADVERTISED_10000baseKX4_Full
-#define ADVERTISED_10000baseKX4_Full	BIT(18)
+#define ADVERTISED_10000baseKX4_Full BIT(18)
 #endif
 #ifndef ADVERTISED_10000baseKR_Full
-#define ADVERTISED_10000baseKR_Full	BIT(19)
+#define ADVERTISED_10000baseKR_Full BIT(19)
 #endif
 
 static inline unsigned long dev_trans_start(struct net_device *dev)
@@ -2957,69 +3003,87 @@ static inline unsigned long dev_trans_start(struct net_device *dev)
 #endif /* < 2.6.31 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 32))
 #undef netdev_tx_t
 #define netdev_tx_t int
 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
 #ifndef NETIF_F_FCOE_MTU
-#define NETIF_F_FCOE_MTU       BIT(26)
+#define NETIF_F_FCOE_MTU BIT(26)
 #endif
 #endif /* CONFIG_FCOE || CONFIG_FCOE_MODULE */
 
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )
-static inline int _kc_pm_runtime_get_sync()
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
+static inline int _kc_pm_runtime_get_sync(void)
 {
 	return 1;
 }
-#define pm_runtime_get_sync(dev)	_kc_pm_runtime_get_sync()
+#define pm_runtime_get_sync(dev) _kc_pm_runtime_get_sync()
 #else /* 2.6.0 => 2.6.32 */
 static inline int _kc_pm_runtime_get_sync(struct device __always_unused *dev)
 {
 	return 1;
 }
 #ifndef pm_runtime_get_sync
-#define pm_runtime_get_sync(dev)	_kc_pm_runtime_get_sync(dev)
+#define pm_runtime_get_sync(dev) _kc_pm_runtime_get_sync(dev)
 #endif
 #endif /* 2.6.0 => 2.6.32 */
 #ifndef pm_runtime_put
-#define pm_runtime_put(dev)		do {} while (0)
+#define pm_runtime_put(dev) \
+	do {                    \
+	} while (0)
 #endif
 #ifndef pm_runtime_put_sync
-#define pm_runtime_put_sync(dev)	do {} while (0)
+#define pm_runtime_put_sync(dev) \
+	do {                         \
+	} while (0)
 #endif
 #ifndef pm_runtime_resume
-#define pm_runtime_resume(dev)		do {} while (0)
+#define pm_runtime_resume(dev) \
+	do {                       \
+	} while (0)
 #endif
 #ifndef pm_schedule_suspend
-#define pm_schedule_suspend(dev, t)	do {} while (0)
+#define pm_schedule_suspend(dev, t) \
+	do {                            \
+	} while (0)
 #endif
 #ifndef pm_runtime_set_suspended
-#define pm_runtime_set_suspended(dev)	do {} while (0)
+#define pm_runtime_set_suspended(dev) \
+	do {                              \
+	} while (0)
 #endif
 #ifndef pm_runtime_disable
-#define pm_runtime_disable(dev)		do {} while (0)
+#define pm_runtime_disable(dev) \
+	do {                        \
+	} while (0)
 #endif
 #ifndef pm_runtime_put_noidle
-#define pm_runtime_put_noidle(dev)	do {} while (0)
+#define pm_runtime_put_noidle(dev) \
+	do {                           \
+	} while (0)
 #endif
 #ifndef pm_runtime_set_active
-#define pm_runtime_set_active(dev)	do {} while (0)
+#define pm_runtime_set_active(dev) \
+	do {                           \
+	} while (0)
 #endif
 #ifndef pm_runtime_enable
-#define pm_runtime_enable(dev)	do {} while (0)
+#define pm_runtime_enable(dev) \
+	do {                       \
+	} while (0)
 #endif
 #ifndef pm_runtime_get_noresume
-#define pm_runtime_get_noresume(dev)	do {} while (0)
+#define pm_runtime_get_noresume(dev) \
+	do {                             \
+	} while (0)
 #endif
 #else /* < 2.6.32 */
-#if (RHEL_RELEASE_CODE && \
-     (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,2)) && \
-     (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)))
+#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 2)) && \
+	(RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 0)))
 #define HAVE_RHEL6_NET_DEVICE_EXTENDED
 #endif /* RHEL >= 6.2 && RHEL < 7.0 */
-#if (RHEL_RELEASE_CODE && \
-     (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,6)) && \
-     (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)))
+#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 6)) && \
+	(RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 0)))
 #define HAVE_RHEL6_NET_DEVICE_OPS_EXT
 #define HAVE_NDO_SET_FEATURES
 #endif /* RHEL >= 6.6 && RHEL < 7.0 */
@@ -3039,7 +3103,7 @@ static inline int _kc_pm_runtime_get_sync(struct device __always_unused *dev)
 #endif /* < 2.6.32 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33))
 #ifndef pci_pcie_cap
 #define pci_pcie_cap(pdev) pci_find_capability(pdev, PCI_CAP_ID_EXP)
 #endif
@@ -3050,8 +3114,8 @@ static inline int _kc_pm_runtime_get_sync(struct device __always_unused *dev)
 #define IPV6_FLOW 0x11
 #endif /* IPV6_FLOW */
 /* Features back-ported to RHEL6 or SLES11 SP1 after 2.6.32 */
-#if ( (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,0)) || \
-      (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,1,0)) )
+#if ((RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 0)) || \
+	(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11, 1, 0)))
 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
 #ifndef HAVE_NETDEV_OPS_FCOE_GETWWN
 #define HAVE_NETDEV_OPS_FCOE_GETWWN
@@ -3069,50 +3133,50 @@ static inline int _kc_pm_runtime_get_sync(struct device __always_unused *dev)
 #define PORT_NONE PORT_OTHER
 #endif
 
-#if ((RHEL_RELEASE_CODE && \
-     (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,3)) && \
-     (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0))))
+#if ((RHEL_RELEASE_CODE &&                                 \
+	(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 3)) && \
+	(RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 0))))
 #if !defined(CONFIG_X86_32) && !defined(CONFIG_NEED_DMA_MAP_STATE)
 #undef DEFINE_DMA_UNMAP_ADDR
-#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)	dma_addr_t ADDR_NAME
+#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME
 #undef DEFINE_DMA_UNMAP_LEN
-#define DEFINE_DMA_UNMAP_LEN(LEN_NAME)		__u32 LEN_NAME
+#define DEFINE_DMA_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME
 #undef dma_unmap_addr
-#define dma_unmap_addr(PTR, ADDR_NAME)		((PTR)->ADDR_NAME)
+#define dma_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME)
 #undef dma_unmap_addr_set
-#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL)	(((PTR)->ADDR_NAME) = (VAL))
+#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
 #undef dma_unmap_len
-#define dma_unmap_len(PTR, LEN_NAME)		((PTR)->LEN_NAME)
+#define dma_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME)
 #undef dma_unmap_len_set
-#define dma_unmap_len_set(PTR, LEN_NAME, VAL)	(((PTR)->LEN_NAME) = (VAL))
+#define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
 #endif /* CONFIG_X86_64 && !CONFIG_NEED_DMA_MAP_STATE */
 #endif /* RHEL_RELEASE_CODE */
 
-#if (!(RHEL_RELEASE_CODE && \
-       (((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,8)) && \
-         (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0))) || \
-        ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,1)) && \
-         (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0))))))
+#if (!(RHEL_RELEASE_CODE &&                                   \
+	(((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5, 8)) && \
+		(RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6, 0))) || \
+		((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 1)) && \
+		(RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 0))))))
 static inline bool pci_is_pcie(struct pci_dev *dev)
 {
 	return !!pci_pcie_cap(dev);
 }
 #endif /* RHEL_RELEASE_CODE */
 
-#if (!(RHEL_RELEASE_CODE && \
-      (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,2))))
+#if (!(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 2))))
 #define sk_tx_queue_get(_sk) (-1)
-#define sk_tx_queue_set(_sk, _tx_queue) do {} while(0)
+#define sk_tx_queue_set(_sk, _tx_queue) \
+	do {                                \
+	} while (0)
 #endif /* !(RHEL >= 6.2) */
 
-#if (RHEL_RELEASE_CODE && \
-     (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4)) && \
-     (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)))
+#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 4)) && \
+	(RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 0)))
 #define HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT
 #define HAVE_ETHTOOL_GRXFHINDIR_SIZE
 #define HAVE_ETHTOOL_SET_PHYS_ID
 #define HAVE_ETHTOOL_GET_TS_INFO
-#if (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,5))
+#if (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6, 5))
 #define HAVE_ETHTOOL_GSRSSH
 #define HAVE_RHEL6_SRIOV_CONFIGURE
 #define HAVE_RXFH_NONCONST
@@ -3128,8 +3192,8 @@ static inline bool pci_is_pcie(struct pci_dev *dev)
 #endif /* < 2.6.33 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34) )
-#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 34))
+#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6, 0))
 #ifndef pci_num_vf
 #define pci_num_vf(pdev) _kc_pci_num_vf(pdev)
 int _kc_pci_num_vf(struct pci_dev *dev);
@@ -3165,11 +3229,11 @@ int _kc_pci_num_vf(struct pci_dev *dev);
 	list_for_each_entry(ha, &dev->uc.list, list)
 #endif
 #ifndef dma_set_coherent_mask
-#define dma_set_coherent_mask(dev,mask) \
-	pci_set_consistent_dma_mask(to_pci_dev(dev),(mask))
+#define dma_set_coherent_mask(dev, mask) \
+	pci_set_consistent_dma_mask(to_pci_dev(dev), (mask))
 #endif
 #ifndef pci_dev_run_wake
-#define pci_dev_run_wake(pdev)	(0)
+#define pci_dev_run_wake(pdev) (0)
 #endif
 
 /* netdev logging taken from include/linux/netdevice.h */
@@ -3180,100 +3244,98 @@ static inline const char *_kc_netdev_name(const struct net_device *dev)
 		return "(unregistered net_device)";
 	return dev->name;
 }
-#define netdev_name(netdev)	_kc_netdev_name(netdev)
+#define netdev_name(netdev) _kc_netdev_name(netdev)
 #endif /* netdev_name */
 
 #undef netdev_printk
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )
-#define netdev_printk(level, netdev, format, args...)		\
-do {								\
-	struct pci_dev *pdev = _kc_netdev_to_pdev(netdev);	\
-	printk(level "%s: " format, pci_name(pdev), ##args);	\
-} while(0)
-#elif ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) )
-#define netdev_printk(level, netdev, format, args...)		\
-do {								\
-	struct pci_dev *pdev = _kc_netdev_to_pdev(netdev);	\
-	struct device *dev = pci_dev_to_dev(pdev);		\
-	dev_printk(level, dev, "%s: " format,			\
-		   netdev_name(netdev), ##args);		\
-} while(0)
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
+#define netdev_printk(level, netdev, format, args...)        \
+	do {                                                     \
+		struct pci_dev *pdev = _kc_netdev_to_pdev(netdev);   \
+		printk(level "%s: " format, pci_name(pdev), ##args); \
+	} while (0)
+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 21))
+#define netdev_printk(level, netdev, format, args...)                       \
+	do {                                                                    \
+		struct pci_dev *pdev = _kc_netdev_to_pdev(netdev);                  \
+		struct device *dev = pci_dev_to_dev(pdev);                          \
+		dev_printk(level, dev, "%s: " format, netdev_name(netdev), ##args); \
+	} while (0)
 #else /* 2.6.21 => 2.6.34 */
-#define netdev_printk(level, netdev, format, args...)		\
-	dev_printk(level, (netdev)->dev.parent,			\
-		   "%s: " format,				\
-		   netdev_name(netdev), ##args)
+#define netdev_printk(level, netdev, format, args...)      \
+	dev_printk(level, (netdev)->dev.parent, "%s: " format, \
+			netdev_name(netdev), ##args)
 #endif /* <2.6.0 <2.6.21 <2.6.34 */
 #undef netdev_emerg
-#define netdev_emerg(dev, format, args...)			\
+#define netdev_emerg(dev, format, args...) \
 	netdev_printk(KERN_EMERG, dev, format, ##args)
 #undef netdev_alert
-#define netdev_alert(dev, format, args...)			\
+#define netdev_alert(dev, format, args...) \
 	netdev_printk(KERN_ALERT, dev, format, ##args)
 #undef netdev_crit
-#define netdev_crit(dev, format, args...)			\
+#define netdev_crit(dev, format, args...) \
 	netdev_printk(KERN_CRIT, dev, format, ##args)
 #undef netdev_err
-#define netdev_err(dev, format, args...)			\
+#define netdev_err(dev, format, args...) \
 	netdev_printk(KERN_ERR, dev, format, ##args)
 #undef netdev_warn
-#define netdev_warn(dev, format, args...)			\
+#define netdev_warn(dev, format, args...) \
 	netdev_printk(KERN_WARNING, dev, format, ##args)
 #undef netdev_notice
-#define netdev_notice(dev, format, args...)			\
+#define netdev_notice(dev, format, args...) \
 	netdev_printk(KERN_NOTICE, dev, format, ##args)
 #undef netdev_info
-#define netdev_info(dev, format, args...)			\
+#define netdev_info(dev, format, args...) \
 	netdev_printk(KERN_INFO, dev, format, ##args)
 #undef netdev_dbg
 #if defined(DEBUG)
-#define netdev_dbg(__dev, format, args...)			\
+#define netdev_dbg(__dev, format, args...) \
 	netdev_printk(KERN_DEBUG, __dev, format, ##args)
 #elif defined(CONFIG_DYNAMIC_DEBUG)
-#define netdev_dbg(__dev, format, args...)			\
-do {								\
-	dynamic_dev_dbg((__dev)->dev.parent, "%s: " format,	\
-			netdev_name(__dev), ##args);		\
-} while (0)
+#define netdev_dbg(__dev, format, args...)                  \
+	do {                                                    \
+		dynamic_dev_dbg((__dev)->dev.parent, "%s: " format, \
+						netdev_name(__dev), ##args);        \
+	} while (0)
 #else /* DEBUG */
-#define netdev_dbg(__dev, format, args...)			\
-({								\
-	if (0)							\
-		netdev_printk(KERN_DEBUG, __dev, format, ##args); \
-	0;							\
-})
+#define netdev_dbg(__dev, format, args...)                    \
+	({                                                        \
+		if (0)                                                \
+			netdev_printk(KERN_DEBUG, __dev, format, ##args); \
+		0;                                                    \
+	})
 #endif /* DEBUG */
 
 #undef netif_printk
-#define netif_printk(priv, type, level, dev, fmt, args...)	\
-do {								\
-	if (netif_msg_##type(priv))				\
-		netdev_printk(level, (dev), fmt, ##args);	\
-} while (0)
+#define netif_printk(priv, type, level, dev, fmt, args...) \
+	do {                                                   \
+		if (netif_msg_##type(priv))                        \
+			netdev_printk(level, (dev), fmt, ##args);      \
+	} while (0)
 
 #undef netif_emerg
-#define netif_emerg(priv, type, dev, fmt, args...)		\
+#define netif_emerg(priv, type, dev, fmt, args...) \
 	netif_level(emerg, priv, type, dev, fmt, ##args)
 #undef netif_alert
-#define netif_alert(priv, type, dev, fmt, args...)		\
+#define netif_alert(priv, type, dev, fmt, args...) \
 	netif_level(alert, priv, type, dev, fmt, ##args)
 #undef netif_crit
-#define netif_crit(priv, type, dev, fmt, args...)		\
+#define netif_crit(priv, type, dev, fmt, args...) \
 	netif_level(crit, priv, type, dev, fmt, ##args)
 #undef netif_err
-#define netif_err(priv, type, dev, fmt, args...)		\
+#define netif_err(priv, type, dev, fmt, args...) \
 	netif_level(err, priv, type, dev, fmt, ##args)
 #undef netif_warn
-#define netif_warn(priv, type, dev, fmt, args...)		\
+#define netif_warn(priv, type, dev, fmt, args...) \
 	netif_level(warn, priv, type, dev, fmt, ##args)
 #undef netif_notice
-#define netif_notice(priv, type, dev, fmt, args...)		\
+#define netif_notice(priv, type, dev, fmt, args...) \
 	netif_level(notice, priv, type, dev, fmt, ##args)
 #undef netif_info
-#define netif_info(priv, type, dev, fmt, args...)		\
+#define netif_info(priv, type, dev, fmt, args...) \
 	netif_level(info, priv, type, dev, fmt, ##args)
 #undef netif_dbg
-#define netif_dbg(priv, type, dev, fmt, args...)		\
+#define netif_dbg(priv, type, dev, fmt, args...) \
 	netif_level(dbg, priv, type, dev, fmt, ##args)
 
 #ifdef SET_SYSTEM_SLEEP_PM_OPS
@@ -3281,9 +3343,8 @@ do {								\
 #endif
 
 #ifndef for_each_set_bit
-#define for_each_set_bit(bit, addr, size) \
-	for ((bit) = find_first_bit((addr), (size)); \
-		(bit) < (size); \
+#define for_each_set_bit(bit, addr, size)                        \
+	for ((bit) = find_first_bit((addr), (size)); (bit) < (size); \
 		(bit) = find_next_bit((addr), (size), (bit) + 1))
 #endif /* for_each_set_bit */
 
@@ -3296,49 +3357,51 @@ do {								\
 #define dma_unmap_len_set pci_unmap_len_set
 #endif /* DEFINE_DMA_UNMAP_ADDR */
 
-#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,3))
+#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6, 3))
 #ifdef IGB_HWMON
 #ifdef CONFIG_DEBUG_LOCK_ALLOC
-#define sysfs_attr_init(attr)				\
-	do {						\
-		static struct lock_class_key __key;	\
-		(attr)->key = &__key;			\
+#define sysfs_attr_init(attr)               \
+	do {                                    \
+		static struct lock_class_key __key; \
+		(attr)->key = &__key;               \
 	} while (0)
 #else
-#define sysfs_attr_init(attr) do {} while (0)
+#define sysfs_attr_init(attr) \
+	do {                      \
+	} while (0)
 #endif /* CONFIG_DEBUG_LOCK_ALLOC */
 #endif /* IGB_HWMON */
 #endif /* RHEL_RELEASE_CODE */
 
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )
-static inline bool _kc_pm_runtime_suspended()
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
+static inline bool _kc_pm_runtime_suspended(void)
 {
 	return false;
 }
-#define pm_runtime_suspended(dev)	_kc_pm_runtime_suspended()
+#define pm_runtime_suspended(dev) _kc_pm_runtime_suspended()
 #else /* 2.6.0 => 2.6.34 */
 static inline bool _kc_pm_runtime_suspended(struct device __always_unused *dev)
 {
 	return false;
 }
 #ifndef pm_runtime_suspended
-#define pm_runtime_suspended(dev)	_kc_pm_runtime_suspended(dev)
+#define pm_runtime_suspended(dev) _kc_pm_runtime_suspended(dev)
 #endif
 #endif /* 2.6.0 => 2.6.34 */
 
 #ifndef pci_bus_speed
 /* override pci_bus_speed introduced in 2.6.19 with an expanded enum type */
 enum _kc_pci_bus_speed {
-	_KC_PCIE_SPEED_2_5GT		= 0x14,
-	_KC_PCIE_SPEED_5_0GT		= 0x15,
-	_KC_PCIE_SPEED_8_0GT		= 0x16,
-	_KC_PCI_SPEED_UNKNOWN		= 0xff,
+	_KC_PCIE_SPEED_2_5GT = 0x14,
+	_KC_PCIE_SPEED_5_0GT = 0x15,
+	_KC_PCIE_SPEED_8_0GT = 0x16,
+	_KC_PCI_SPEED_UNKNOWN = 0xff,
 };
-#define pci_bus_speed		_kc_pci_bus_speed
-#define PCIE_SPEED_2_5GT	_KC_PCIE_SPEED_2_5GT
-#define PCIE_SPEED_5_0GT	_KC_PCIE_SPEED_5_0GT
-#define PCIE_SPEED_8_0GT	_KC_PCIE_SPEED_8_0GT
-#define PCI_SPEED_UNKNOWN	_KC_PCI_SPEED_UNKNOWN
+#define pci_bus_speed _kc_pci_bus_speed
+#define PCIE_SPEED_2_5GT _KC_PCIE_SPEED_2_5GT
+#define PCIE_SPEED_5_0GT _KC_PCIE_SPEED_5_0GT
+#define PCIE_SPEED_8_0GT _KC_PCIE_SPEED_8_0GT
+#define PCI_SPEED_UNKNOWN _KC_PCI_SPEED_UNKNOWN
 #endif /* pci_bus_speed */
 
 #else /* < 2.6.34 */
@@ -3350,12 +3413,12 @@ enum _kc_pci_bus_speed {
 #endif /* < 2.6.34 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35))
 ssize_t _kc_simple_write_to_buffer(void *to, size_t available, loff_t *ppos,
-				   const void __user *from, size_t count);
+								const void __user *from, size_t count);
 #define simple_write_to_buffer _kc_simple_write_to_buffer
 
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4)))
+#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 4)))
 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
 {
 #ifdef HAVE_PCI_DEV_IS_VIRTFN_BIT
@@ -3378,22 +3441,23 @@ static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
 #ifndef numa_mem_id
 #define numa_mem_id numa_node_id
 #endif
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,0)))
+#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 0)))
 #ifdef HAVE_TX_MQ
 #include <net/sch_generic.h>
 #ifndef CONFIG_NETDEVICES_MULTIQUEUE
 int _kc_netif_set_real_num_tx_queues(struct net_device *, unsigned int);
 #else /* CONFIG_NETDEVICES_MULTI_QUEUE */
 static inline int _kc_netif_set_real_num_tx_queues(struct net_device *dev,
-						   unsigned int txq)
+												unsigned int txq)
 {
 	dev->egress_subqueue_count = txq;
 	return 0;
 }
 #endif /* CONFIG_NETDEVICES_MULTI_QUEUE */
 #else /* HAVE_TX_MQ */
-static inline int _kc_netif_set_real_num_tx_queues(struct net_device __always_unused *dev,
-						   unsigned int __always_unused txq)
+static inline int
+_kc_netif_set_real_num_tx_queues(struct net_device __always_unused *dev,
+								unsigned int __always_unused txq)
 {
 	return 0;
 }
@@ -3402,9 +3466,9 @@ static inline int _kc_netif_set_real_num_tx_queues(struct net_device __always_un
 	_kc_netif_set_real_num_tx_queues(dev, txq)
 #endif /* !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,0)) */
 #ifndef ETH_FLAG_RXHASH
-#define ETH_FLAG_RXHASH (1<<28)
+#define ETH_FLAG_RXHASH (1 << 28)
 #endif /* ETH_FLAG_RXHASH */
-#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,0))
+#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 0))
 #define HAVE_IRQ_AFFINITY_HINT
 #endif
 struct device_node;
@@ -3416,7 +3480,7 @@ struct device_node;
 #endif /* < 2.6.35 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36))
 int _kc_ethtool_op_set_flags(struct net_device *, u32, u32);
 #define ethtool_op_set_flags _kc_ethtool_op_set_flags
 u32 _kc_ethtool_op_get_flags(struct net_device *);
@@ -3444,8 +3508,8 @@ enum {
 #define NET_SKB_PAD 32
 #endif
 
-static inline struct sk_buff *_kc_netdev_alloc_skb_ip_align(struct net_device *dev,
-							    unsigned int length)
+static inline struct sk_buff *
+_kc_netdev_alloc_skb_ip_align(struct net_device *dev, unsigned int length)
 {
 	struct sk_buff *skb;
 
@@ -3465,30 +3529,36 @@ static inline struct sk_buff *_kc_netdev_alloc_skb_ip_align(struct net_device *d
 #define netdev_alloc_skb_ip_align(n, l) _kc_netdev_alloc_skb_ip_align(n, l)
 
 #undef netif_level
-#define netif_level(level, priv, type, dev, fmt, args...)	\
-do {								\
-	if (netif_msg_##type(priv))				\
-		netdev_##level(dev, fmt, ##args);		\
-} while (0)
+#define netif_level(level, priv, type, dev, fmt, args...) \
+	do {                                                  \
+		if (netif_msg_##type(priv))                       \
+			netdev_##level(dev, fmt, ##args);             \
+	} while (0)
 
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,3)))
+#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 3)))
 #undef usleep_range
-#define usleep_range(min, max)	msleep(DIV_ROUND_UP(min, 1000))
+#define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))
 #endif
 
-#define u64_stats_update_begin(a) do { } while(0)
-#define u64_stats_update_end(a) do { } while(0)
-#define u64_stats_fetch_begin(a) do { } while(0)
-#define u64_stats_fetch_retry_bh(a,b) (0)
+#define u64_stats_update_begin(a) \
+	do {                          \
+	} while (0)
+#define u64_stats_update_end(a) \
+	do {                        \
+	} while (0)
+#define u64_stats_fetch_begin(a) \
+	do {                         \
+	} while (0)
+#define u64_stats_fetch_retry_bh(a, b) (0)
 #define u64_stats_fetch_begin_bh(a) (0)
 
-#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,1))
+#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 1))
 #define HAVE_8021P_SUPPORT
 #endif
 
 /* RHEL6.4 and SLES11sp2 backported skb_tx_timestamp */
-#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4)) && \
-     !(SLE_VERSION_CODE >= SLE_VERSION(11,2,0)))
+#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 4)) && \
+	!(SLE_VERSION_CODE >= SLE_VERSION(11, 2, 0)))
 static inline void skb_tx_timestamp(struct sk_buff __always_unused *skb)
 {
 	return;
@@ -3503,11 +3573,11 @@ static inline void skb_tx_timestamp(struct sk_buff __always_unused *skb)
 #endif /* < 2.6.36 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37))
 #define HAVE_NON_CONST_PCI_DRIVER_NAME
 #ifndef netif_set_real_num_tx_queues
 static inline int _kc_netif_set_real_num_tx_queues(struct net_device *dev,
-						   unsigned int txq)
+												unsigned int txq)
 {
 	netif_set_real_num_tx_queues(dev, txq);
 	return 0;
@@ -3516,8 +3586,9 @@ static inline int _kc_netif_set_real_num_tx_queues(struct net_device *dev,
 	_kc_netif_set_real_num_tx_queues(dev, txq)
 #endif
 #ifndef netif_set_real_num_rx_queues
-static inline int __kc_netif_set_real_num_rx_queues(struct net_device __always_unused *dev,
-						    unsigned int __always_unused rxq)
+static inline int
+__kc_netif_set_real_num_rx_queues(struct net_device __always_unused *dev,
+								unsigned int __always_unused rxq)
 {
 	return 0;
 }
@@ -3528,7 +3599,7 @@ static inline int __kc_netif_set_real_num_rx_queues(struct net_device __always_u
 #define ETHTOOL_RXNTUPLE_ACTION_CLEAR (-2)
 #endif
 #ifndef VLAN_N_VID
-#define VLAN_N_VID	VLAN_GROUP_ARRAY_LEN
+#define VLAN_N_VID VLAN_GROUP_ARRAY_LEN
 #endif /* VLAN_N_VID */
 #ifndef ETH_FLAG_TXVLAN
 #define ETH_FLAG_TXVLAN BIT(7)
@@ -3563,18 +3634,17 @@ static inline void *_kc_vzalloc(unsigned long size)
 }
 #define vzalloc(_size) _kc_vzalloc(_size)
 
-#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,7)) || \
-     (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(6,0)))
+#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5, 7)) || \
+	(RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(6, 0)))
 static inline __be16 vlan_get_protocol(const struct sk_buff *skb)
 {
-	if (vlan_tx_tag_present(skb) ||
-	    skb->protocol != cpu_to_be16(ETH_P_8021Q))
+	if (vlan_tx_tag_present(skb) || skb->protocol != cpu_to_be16(ETH_P_8021Q))
 		return skb->protocol;
 
 	if (skb_headlen(skb) < sizeof(struct vlan_ethhdr))
 		return 0;
 
-	return ((struct vlan_ethhdr*)skb->data)->h_vlan_encapsulated_proto;
+	return ((struct vlan_ethhdr *)skb->data)->h_vlan_encapsulated_proto;
 }
 #endif /* !RHEL5.7+ || RHEL6.0 */
 
@@ -3585,10 +3655,10 @@ static inline __be16 vlan_get_protocol(const struct sk_buff *skb)
 #endif
 
 #ifndef device_wakeup_enable
-#define device_wakeup_enable(dev)	device_set_wakeup_enable(dev, true)
+#define device_wakeup_enable(dev) device_set_wakeup_enable(dev, true)
 #endif
 
-#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,4,18) )
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 4, 18))
 #ifndef HAVE_VLAN_RX_REGISTER
 #define HAVE_VLAN_RX_REGISTER
 #endif
@@ -3596,13 +3666,13 @@ static inline __be16 vlan_get_protocol(const struct sk_buff *skb)
 #endif /* < 2.6.37 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) )
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 38))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22))
 #define skb_checksum_start_offset(skb) skb_transport_offset(skb)
 #else /* 2.6.22 -> 2.6.37 */
 static inline int _kc_skb_checksum_start_offset(const struct sk_buff *skb)
 {
-        return skb->csum_start - skb_headroom(skb);
+	return skb->csum_start - skb_headroom(skb);
 }
 #define skb_checksum_start_offset(skb) _kc_skb_checksum_start_offset(skb)
 #endif /* 2.6.22 -> 2.6.37 */
@@ -3611,56 +3681,55 @@ static inline int _kc_skb_checksum_start_offset(const struct sk_buff *skb)
 #define IEEE_8021QAZ_MAX_TCS 8
 #endif
 #ifndef DCB_CAP_DCBX_HOST
-#define DCB_CAP_DCBX_HOST		0x01
+#define DCB_CAP_DCBX_HOST 0x01
 #endif
 #ifndef DCB_CAP_DCBX_LLD_MANAGED
-#define DCB_CAP_DCBX_LLD_MANAGED	0x02
+#define DCB_CAP_DCBX_LLD_MANAGED 0x02
 #endif
 #ifndef DCB_CAP_DCBX_VER_CEE
-#define DCB_CAP_DCBX_VER_CEE		0x04
+#define DCB_CAP_DCBX_VER_CEE 0x04
 #endif
 #ifndef DCB_CAP_DCBX_VER_IEEE
-#define DCB_CAP_DCBX_VER_IEEE		0x08
+#define DCB_CAP_DCBX_VER_IEEE 0x08
 #endif
 #ifndef DCB_CAP_DCBX_STATIC
-#define DCB_CAP_DCBX_STATIC		0x10
+#define DCB_CAP_DCBX_STATIC 0x10
 #endif
 #endif /* CONFIG_DCB */
-#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,2))
+#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 2))
 #define CONFIG_XPS
 #endif /* RHEL_RELEASE_VERSION(6,2) */
 #endif /* < 2.6.38 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39))
 #ifndef TC_BITMASK
 #define TC_BITMASK 15
 #endif
 #ifndef NETIF_F_RXCSUM
-#define NETIF_F_RXCSUM		BIT(29)
+#define NETIF_F_RXCSUM BIT(29)
 #endif
 #ifndef skb_queue_reverse_walk_safe
-#define skb_queue_reverse_walk_safe(queue, skb, tmp)				\
-		for (skb = (queue)->prev, tmp = skb->prev;			\
-		     skb != (struct sk_buff *)(queue);				\
-		     skb = tmp, tmp = skb->prev)
+#define skb_queue_reverse_walk_safe(queue, skb, tmp) \
+	for (skb = (queue)->prev, tmp = skb->prev;       \
+		skb != (struct sk_buff *)(queue); skb = tmp, tmp = skb->prev)
 #endif
 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
 #ifndef FCOE_MTU
-#define FCOE_MTU	2158
+#define FCOE_MTU 2158
 #endif
 #endif
 #if IS_ENABLED(CONFIG_DCB)
 #ifndef IEEE_8021QAZ_APP_SEL_ETHERTYPE
-#define IEEE_8021QAZ_APP_SEL_ETHERTYPE	1
+#define IEEE_8021QAZ_APP_SEL_ETHERTYPE 1
 #endif
 #endif
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4)))
-#define kstrtoul(a, b, c)  ((*(c)) = simple_strtoul((a), NULL, (b)), 0)
-#define kstrtouint(a, b, c)  ((*(c)) = simple_strtoul((a), NULL, (b)), 0)
-#define kstrtou32(a, b, c)  ((*(c)) = simple_strtoul((a), NULL, (b)), 0)
+#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 4)))
+#define kstrtoul(a, b, c) ((*(c)) = simple_strtoul((a), NULL, (b)), 0)
+#define kstrtouint(a, b, c) ((*(c)) = simple_strtoul((a), NULL, (b)), 0)
+#define kstrtou32(a, b, c) ((*(c)) = simple_strtoul((a), NULL, (b)), 0)
 #endif /* !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4)) */
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,0)))
+#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6, 0)))
 u16 ___kc_skb_tx_hash(struct net_device *, const struct sk_buff *, u16);
 #define __skb_tx_hash(n, s, q) ___kc_skb_tx_hash((n), (s), (q))
 u8 _kc_netdev_get_num_tc(struct net_device *dev);
@@ -3668,10 +3737,14 @@ u8 _kc_netdev_get_num_tc(struct net_device *dev);
 int _kc_netdev_set_num_tc(struct net_device *dev, u8 num_tc);
 #define netdev_set_num_tc(dev, tc) _kc_netdev_set_num_tc((dev), (tc))
 #define netdev_reset_tc(dev) _kc_netdev_set_num_tc((dev), 0)
-#define netdev_set_tc_queue(dev, tc, cnt, off) do {} while (0)
+#define netdev_set_tc_queue(dev, tc, cnt, off) \
+	do {                                       \
+	} while (0)
 u8 _kc_netdev_get_prio_tc_map(struct net_device *dev, u8 up);
 #define netdev_get_prio_tc_map(dev, up) _kc_netdev_get_prio_tc_map(dev, up)
-#define netdev_set_prio_tc_map(dev, up, tc) do {} while (0)
+#define netdev_set_prio_tc_map(dev, up, tc) \
+	do {                                    \
+	} while (0)
 #else /* RHEL6.1 or greater */
 #ifndef HAVE_MQPRIO
 #define HAVE_MQPRIO
@@ -3680,13 +3753,13 @@ u8 _kc_netdev_get_prio_tc_map(struct net_device *dev, u8 up);
 #ifndef HAVE_DCBNL_IEEE
 #define HAVE_DCBNL_IEEE
 #ifndef IEEE_8021QAZ_TSA_STRICT
-#define IEEE_8021QAZ_TSA_STRICT		0
+#define IEEE_8021QAZ_TSA_STRICT 0
 #endif
 #ifndef IEEE_8021QAZ_TSA_ETS
-#define IEEE_8021QAZ_TSA_ETS		2
+#define IEEE_8021QAZ_TSA_ETS 2
 #endif
 #ifndef IEEE_8021QAZ_APP_SEL_ETHERTYPE
-#define IEEE_8021QAZ_APP_SEL_ETHERTYPE	1
+#define IEEE_8021QAZ_APP_SEL_ETHERTYPE 1
 #endif
 #endif
 #endif /* CONFIG_DCB */
@@ -3696,8 +3769,8 @@ u8 _kc_netdev_get_prio_tc_map(struct net_device *dev, u8 up);
 #define udp_csum __kc_udp_csum
 static inline __wsum __kc_udp_csum(struct sk_buff *skb)
 {
-	__wsum csum = csum_partial(skb_transport_header(skb),
-				   sizeof(struct udphdr), skb->csum);
+	__wsum csum = csum_partial(skb_transport_header(skb), sizeof(struct udphdr),
+							skb->csum);
 
 	for (skb = skb_shinfo(skb)->frag_list; skb; skb = skb->next) {
 		csum = csum_add(csum, skb->csum);
@@ -3730,31 +3803,31 @@ static inline __wsum __kc_udp_csum(struct sk_buff *skb)
 
 /*****************************************************************************/
 /* use < 2.6.40 because of a Fedora 15 kernel update where they
- * updated the kernel version to 2.6.40.x and they back-ported 3.0 features
- * like set_phys_id for ethtool.
- */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,40) )
+* updated the kernel version to 2.6.40.x and they back-ported 3.0 features
+* like set_phys_id for ethtool.
+*/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 40))
 #ifdef ETHTOOL_GRXRINGS
 #ifndef FLOW_EXT
-#define	FLOW_EXT	0x80000000
+#define FLOW_EXT 0x80000000
 union _kc_ethtool_flow_union {
-	struct ethtool_tcpip4_spec		tcp_ip4_spec;
-	struct ethtool_usrip4_spec		usr_ip4_spec;
-	__u8					hdata[60];
+	struct ethtool_tcpip4_spec tcp_ip4_spec;
+	struct ethtool_usrip4_spec usr_ip4_spec;
+	__u8 hdata[60];
 };
 struct _kc_ethtool_flow_ext {
-	__be16	vlan_etype;
-	__be16	vlan_tci;
-	__be32	data[2];
+	__be16 vlan_etype;
+	__be16 vlan_tci;
+	__be32 data[2];
 };
 struct _kc_ethtool_rx_flow_spec {
-	__u32		flow_type;
+	__u32 flow_type;
 	union _kc_ethtool_flow_union h_u;
 	struct _kc_ethtool_flow_ext h_ext;
 	union _kc_ethtool_flow_union m_u;
 	struct _kc_ethtool_flow_ext m_ext;
-	__u64		ring_cookie;
-	__u32		location;
+	__u64 ring_cookie;
+	__u32 location;
 };
 #define ethtool_rx_flow_spec _kc_ethtool_rx_flow_spec
 #endif /* FLOW_EXT */
@@ -3763,13 +3836,13 @@ struct _kc_ethtool_rx_flow_spec {
 #define pci_disable_link_state_locked pci_disable_link_state
 
 #ifndef PCI_LTR_VALUE_MASK
-#define  PCI_LTR_VALUE_MASK	0x000003ff
+#define PCI_LTR_VALUE_MASK 0x000003ff
 #endif
 #ifndef PCI_LTR_SCALE_MASK
-#define  PCI_LTR_SCALE_MASK	0x00001c00
+#define PCI_LTR_SCALE_MASK 0x00001c00
 #endif
 #ifndef PCI_LTR_SCALE_SHIFT
-#define  PCI_LTR_SCALE_SHIFT	10
+#define PCI_LTR_SCALE_SHIFT 10
 #endif
 
 #else /* < 2.6.40 */
@@ -3777,25 +3850,24 @@ struct _kc_ethtool_rx_flow_spec {
 #endif /* < 2.6.40 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 0, 0))
 #define USE_LEGACY_PM_SUPPORT
 #ifndef kfree_rcu
-#define kfree_rcu(_ptr, _rcu_head) do { 				\
-	void __kc_kfree_rcu(struct rcu_head *rcu_head)			\
-	{								\
-		void *ptr = container_of(rcu_head,			\
-					 typeof(*_ptr),			\
-					 _rcu_head);			\
-		kfree(ptr);						\
-	}								\
-	call_rcu(&(_ptr)->_rcu_head, __kc_kfree_rcu);			\
-} while (0)
+#define kfree_rcu(_ptr, _rcu_head)                                        \
+	do {                                                                  \
+		void __kc_kfree_rcu(struct rcu_head *rcu_head)                    \
+		{                                                                 \
+			void *ptr = container_of(rcu_head, typeof(*_ptr), _rcu_head); \
+			kfree(ptr);                                                   \
+		}                                                                 \
+		call_rcu(&(_ptr)->_rcu_head, __kc_kfree_rcu);                     \
+	} while (0)
 #define HAVE_KFREE_RCU_BARRIER
 #endif /* kfree_rcu */
 #ifndef kstrtol_from_user
 #define kstrtol_from_user(s, c, b, r) _kc_kstrtol_from_user(s, c, b, r)
 static inline int _kc_kstrtol_from_user(const char __user *s, size_t count,
-					unsigned int base, long *res)
+										unsigned int base, long *res)
 {
 	/* sign, base 2 representation, newline, terminator */
 	char buf[1 + sizeof(long) * 8 + 1 + 1];
@@ -3808,32 +3880,32 @@ static inline int _kc_kstrtol_from_user(const char __user *s, size_t count,
 }
 #endif
 
-#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,0) || \
-     RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,7)))
+#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7, 0) || \
+						RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5, 7)))
 /* 20000base_blah_full Supported and Advertised Registers */
-#define SUPPORTED_20000baseMLD2_Full	BIT(21)
-#define SUPPORTED_20000baseKR2_Full	BIT(22)
-#define ADVERTISED_20000baseMLD2_Full	BIT(21)
-#define ADVERTISED_20000baseKR2_Full	BIT(22)
+#define SUPPORTED_20000baseMLD2_Full BIT(21)
+#define SUPPORTED_20000baseKR2_Full BIT(22)
+#define ADVERTISED_20000baseMLD2_Full BIT(21)
+#define ADVERTISED_20000baseKR2_Full BIT(22)
 #endif /* RHEL_RELEASE_CODE */
 #endif /* < 3.0.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))
 #ifndef __netdev_alloc_skb_ip_align
-#define __netdev_alloc_skb_ip_align(d,l,_g) netdev_alloc_skb_ip_align(d,l)
+#define __netdev_alloc_skb_ip_align(d, l, _g) netdev_alloc_skb_ip_align(d, l)
 #endif /* __netdev_alloc_skb_ip_align */
 #define dcb_ieee_setapp(dev, app) dcb_setapp(dev, app)
 #define dcb_ieee_delapp(dev, app) 0
 #define dcb_ieee_getapp_mask(dev, app) (1 << app->priority)
 
 /* 1000BASE-T Control register */
-#define CTL1000_AS_MASTER	0x0800
-#define CTL1000_ENABLE_MASTER	0x1000
+#define CTL1000_AS_MASTER 0x0800
+#define CTL1000_ENABLE_MASTER 0x1000
 
 /* kernels less than 3.0.0 don't have this */
 #ifndef ETH_P_8021AD
-#define ETH_P_8021AD	0x88A8
+#define ETH_P_8021AD 0x88A8
 #endif
 
 /* Stub definition for !CONFIG_OF is introduced later */
@@ -3855,11 +3927,11 @@ pci_device_to_OF_node(struct pci_dev __maybe_unused *pdev)
 #endif /* < 3.1.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0))
 #ifndef dma_zalloc_coherent
 #define dma_zalloc_coherent(d, s, h, f) _kc_dma_zalloc_coherent(d, s, h, f)
 static inline void *_kc_dma_zalloc_coherent(struct device *dev, size_t size,
-					    dma_addr_t *dma_handle, gfp_t flag)
+											dma_addr_t *dma_handle, gfp_t flag)
 {
 	void *ret = dma_alloc_coherent(dev, size, dma_handle, flag);
 	if (ret)
@@ -3872,7 +3944,7 @@ static inline void *_kc_dma_zalloc_coherent(struct device *dev, size_t size,
 #endif /* ETHTOOL_GRXRINGS */
 
 #ifndef skb_frag_size
-#define skb_frag_size(frag)	_kc_skb_frag_size(frag)
+#define skb_frag_size(frag) _kc_skb_frag_size(frag)
 static inline unsigned int _kc_skb_frag_size(const skb_frag_t *frag)
 {
 	return frag->size;
@@ -3880,7 +3952,7 @@ static inline unsigned int _kc_skb_frag_size(const skb_frag_t *frag)
 #endif /* skb_frag_size */
 
 #ifndef skb_frag_size_sub
-#define skb_frag_size_sub(frag, delta)	_kc_skb_frag_size_sub(frag, delta)
+#define skb_frag_size_sub(frag, delta) _kc_skb_frag_size_sub(frag, delta)
 static inline void _kc_skb_frag_size_sub(skb_frag_t *frag, int delta)
 {
 	frag->size -= delta;
@@ -3888,7 +3960,7 @@ static inline void _kc_skb_frag_size_sub(skb_frag_t *frag, int delta)
 #endif /* skb_frag_size_sub */
 
 #ifndef skb_frag_page
-#define skb_frag_page(frag)	_kc_skb_frag_page(frag)
+#define skb_frag_page(frag) _kc_skb_frag_page(frag)
 static inline struct page *_kc_skb_frag_page(const skb_frag_t *frag)
 {
 	return frag->page;
@@ -3896,7 +3968,7 @@ static inline struct page *_kc_skb_frag_page(const skb_frag_t *frag)
 #endif /* skb_frag_page */
 
 #ifndef skb_frag_address
-#define skb_frag_address(frag)	_kc_skb_frag_address(frag)
+#define skb_frag_address(frag) _kc_skb_frag_address(frag)
 static inline void *_kc_skb_frag_address(const skb_frag_t *frag)
 {
 	return page_address(skb_frag_page(frag)) + frag->page_offset;
@@ -3904,18 +3976,18 @@ static inline void *_kc_skb_frag_address(const skb_frag_t *frag)
 #endif /* skb_frag_address */
 
 #ifndef skb_frag_dma_map
-#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) )
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
 #include <linux/dma-mapping.h>
 #endif
-#define skb_frag_dma_map(dev,frag,offset,size,dir) \
-		_kc_skb_frag_dma_map(dev,frag,offset,size,dir)
+#define skb_frag_dma_map(dev, frag, offset, size, dir) \
+	_kc_skb_frag_dma_map(dev, frag, offset, size, dir)
 static inline dma_addr_t _kc_skb_frag_dma_map(struct device *dev,
-					      const skb_frag_t *frag,
-					      size_t offset, size_t size,
-					      enum dma_data_direction dir)
+											const skb_frag_t *frag,
+											size_t offset, size_t size,
+											enum dma_data_direction dir)
 {
-	return dma_map_page(dev, skb_frag_page(frag),
-			    frag->page_offset + offset, size, dir);
+	return dma_map_page(dev, skb_frag_page(frag), frag->page_offset + offset,
+						size, dir);
 }
 #endif /* skb_frag_dma_map */
 
@@ -3928,13 +4000,13 @@ static inline void __kc_skb_frag_unref(skb_frag_t *frag)
 #endif /* __skb_frag_unref */
 
 #ifndef SPEED_UNKNOWN
-#define SPEED_UNKNOWN	-1
+#define SPEED_UNKNOWN -1
 #endif
 #ifndef DUPLEX_UNKNOWN
-#define DUPLEX_UNKNOWN	0xff
+#define DUPLEX_UNKNOWN 0xff
 #endif
-#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,3)) ||\
-     (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,3,0)))
+#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 3)) || \
+	(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11, 3, 0)))
 #ifndef HAVE_PCI_DEV_FLAGS_ASSIGNED
 #define HAVE_PCI_DEV_FLAGS_ASSIGNED
 #endif
@@ -3951,18 +4023,19 @@ static inline void __kc_skb_frag_unref(skb_frag_t *frag)
 #define HAVE_PM_QOS_REQUEST_LIST_NEW
 #endif /* < 3.2.0 */
 
-#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(6,2))
+#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(6, 2))
 #undef ixgbe_get_netdev_tc_txq
-#define ixgbe_get_netdev_tc_txq(dev, tc) (&netdev_extended(dev)->qos_data.tc_to_txq[tc])
+#define ixgbe_get_netdev_tc_txq(dev, tc) \
+	(&netdev_extended(dev)->qos_data.tc_to_txq[tc])
 #endif
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0))
 /* NOTE: the order of parameters to _kc_alloc_workqueue() is different than
- * alloc_workqueue() to avoid compiler warning from -Wvarargs
- */
-static inline struct workqueue_struct * __attribute__ ((format(printf, 3, 4)))
+* alloc_workqueue() to avoid compiler warning from -Wvarargs
+*/
+static inline struct workqueue_struct *__attribute__((format(printf, 3, 4)))
 _kc_alloc_workqueue(__maybe_unused int flags, __maybe_unused int max_active,
-		    const char *fmt, ...)
+					const char *fmt, ...)
 {
 	struct workqueue_struct *wq;
 	va_list args, temp;
@@ -3982,7 +4055,7 @@ _kc_alloc_workqueue(__maybe_unused int flags, __maybe_unused int max_active,
 
 	vsnprintf(p, len + 1, fmt, args);
 	va_end(args);
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36))
 	wq = create_workqueue(p);
 #else
 	wq = alloc_workqueue(p, flags, max_active);
@@ -3997,36 +4070,48 @@ _kc_alloc_workqueue(__maybe_unused int flags, __maybe_unused int max_active,
 #define alloc_workqueue(fmt, flags, max_active, args...) \
 	_kc_alloc_workqueue(flags, max_active, fmt, ##args)
 
-#if !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,5))
+#if !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 5))
 typedef u32 netdev_features_t;
 #endif
 #undef PCI_EXP_TYPE_RC_EC
-#define  PCI_EXP_TYPE_RC_EC	0xa	/* Root Complex Event Collector */
+#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */
 #ifndef CONFIG_BQL
-#define netdev_tx_completed_queue(_q, _p, _b) do {} while (0)
-#define netdev_completed_queue(_n, _p, _b) do {} while (0)
-#define netdev_tx_sent_queue(_q, _b) do {} while (0)
-#define netdev_sent_queue(_n, _b) do {} while (0)
-#define netdev_tx_reset_queue(_q) do {} while (0)
-#define netdev_reset_queue(_n) do {} while (0)
-#endif
-#if (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,3,0))
+#define netdev_tx_completed_queue(_q, _p, _b) \
+	do {                                      \
+	} while (0)
+#define netdev_completed_queue(_n, _p, _b) \
+	do {                                   \
+	} while (0)
+#define netdev_tx_sent_queue(_q, _b) \
+	do {                             \
+	} while (0)
+#define netdev_sent_queue(_n, _b) \
+	do {                          \
+	} while (0)
+#define netdev_tx_reset_queue(_q) \
+	do {                          \
+	} while (0)
+#define netdev_reset_queue(_n) \
+	do {                       \
+	} while (0)
+#endif
+#if (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11, 3, 0))
 #define HAVE_ETHTOOL_GRXFHINDIR_SIZE
 #endif /* SLE_VERSION(11,3,0) */
 #define netif_xmit_stopped(_q) netif_tx_queue_stopped(_q)
-#if !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,4,0))
+#if !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11, 4, 0))
 static inline int __kc_ipv6_skip_exthdr(const struct sk_buff *skb, int start,
-					u8 *nexthdrp,
-					__be16 __always_unused *frag_offp)
+										u8 *nexthdrp,
+										__be16 __always_unused *frag_offp)
 {
 	return ipv6_skip_exthdr(skb, start, nexthdrp);
 }
 #undef ipv6_skip_exthdr
-#define ipv6_skip_exthdr(a,b,c,d) __kc_ipv6_skip_exthdr((a), (b), (c), (d))
+#define ipv6_skip_exthdr(a, b, c, d) __kc_ipv6_skip_exthdr((a), (b), (c), (d))
 #endif /* !SLES11sp4 or greater */
 
-#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4)) && \
-     !(SLE_VERSION_CODE >= SLE_VERSION(11,3,0)))
+#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 4)) && \
+	!(SLE_VERSION_CODE >= SLE_VERSION(11, 3, 0)))
 static inline u32 ethtool_rxfh_indir_default(u32 index, u32 n_rx_rings)
 {
 	return index % n_rx_rings;
@@ -4042,15 +4127,15 @@ static inline u32 ethtool_rxfh_indir_default(u32 index, u32 n_rx_rings)
 #endif /* < 3.3.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0))
 #ifndef NETIF_F_RXFCS
-#define NETIF_F_RXFCS	0
+#define NETIF_F_RXFCS 0
 #endif /* NETIF_F_RXFCS */
 #ifndef NETIF_F_RXALL
-#define NETIF_F_RXALL	0
+#define NETIF_F_RXALL 0
 #endif /* NETIF_F_RXALL */
 
-#if !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,3,0))
+#if !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11, 3, 0))
 #define NUMTCS_RETURNS_U8
 
 int _kc_simple_open(struct inode *inode, struct file *file);
@@ -4059,23 +4144,23 @@ int _kc_simple_open(struct inode *inode, struct file *file);
 
 #ifndef skb_add_rx_frag
 #define skb_add_rx_frag _kc_skb_add_rx_frag
-void _kc_skb_add_rx_frag(struct sk_buff * skb, int i, struct page *page,
-			 int off, int size, unsigned int truesize);
+void _kc_skb_add_rx_frag(struct sk_buff *skb, int i, struct page *page, int off,
+						int size, unsigned int truesize);
 #endif
 #ifdef NET_ADDR_RANDOM
-#define eth_hw_addr_random(N) do { \
-	eth_random_addr(N->dev_addr); \
-	N->addr_assign_type |= NET_ADDR_RANDOM; \
+#define eth_hw_addr_random(N)                   \
+	do {                                        \
+		eth_random_addr(N->dev_addr);           \
+		N->addr_assign_type |= NET_ADDR_RANDOM; \
 	} while (0)
 #else /* NET_ADDR_RANDOM */
 #define eth_hw_addr_random(N) eth_random_addr(N->dev_addr)
 #endif /* NET_ADDR_RANDOM */
 
 #ifndef for_each_set_bit_from
-#define for_each_set_bit_from(bit, addr, size) \
-	for ((bit) = find_next_bit((addr), (size), (bit)); \
-			(bit) < (size); \
-			(bit) = find_next_bit((addr), (size), (bit) + 1))
+#define for_each_set_bit_from(bit, addr, size)                         \
+	for ((bit) = find_next_bit((addr), (size), (bit)); (bit) < (size); \
+		(bit) = find_next_bit((addr), (size), (bit) + 1))
 #endif /* for_each_set_bit_from */
 
 #else /* < 3.4.0 */
@@ -4083,15 +4168,15 @@ void _kc_skb_add_rx_frag(struct sk_buff * skb, int i, struct page *page,
 #endif /* >= 3.4.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) ) || \
-    ( RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4) )
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) || \
+		(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 4))
 #if !defined(NO_PTP_SUPPORT) && IS_ENABLED(CONFIG_PTP_1588_CLOCK)
 #define HAVE_PTP_1588_CLOCK
 #endif /* !NO_PTP_SUPPORT && IS_ENABLED(CONFIG_PTP_1588_CLOCK) */
 #endif /* >= 3.0.0 || RHEL_RELEASE > 6.4 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0))
 
 #ifndef SIZE_MAX
 #define SIZE_MAX (~(size_t)0)
@@ -4106,7 +4191,8 @@ static inline bool __kc_ether_addr_equal(const u8 *addr1, const u8 *addr2)
 {
 	return !compare_ether_addr(addr1, addr2);
 }
-#define ether_addr_equal(_addr1, _addr2) __kc_ether_addr_equal((_addr1),(_addr2))
+#define ether_addr_equal(_addr1, _addr2) \
+	__kc_ether_addr_equal((_addr1), (_addr2))
 #endif
 
 /* Definitions for !CONFIG_OF_NET are introduced in 3.10 */
@@ -4129,26 +4215,26 @@ of_get_mac_address(struct device_node __always_unused *np)
 #endif /* < 3.5.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0) )
-#define PCI_EXP_LNKCAP2		44	/* Link Capability 2 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
+#define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */
 
 #ifndef MDIO_EEE_100TX
-#define MDIO_EEE_100TX		0x0002	/* 100TX EEE cap */
+#define MDIO_EEE_100TX 0x0002 /* 100TX EEE cap */
 #endif
 #ifndef MDIO_EEE_1000T
-#define MDIO_EEE_1000T		0x0004	/* 1000T EEE cap */
+#define MDIO_EEE_1000T 0x0004 /* 1000T EEE cap */
 #endif
 #ifndef MDIO_EEE_10GT
-#define MDIO_EEE_10GT		0x0008	/* 10GT EEE cap */
+#define MDIO_EEE_10GT 0x0008 /* 10GT EEE cap */
 #endif
 #ifndef MDIO_EEE_1000KX
-#define MDIO_EEE_1000KX		0x0010	/* 1000KX EEE cap */
+#define MDIO_EEE_1000KX 0x0010 /* 1000KX EEE cap */
 #endif
 #ifndef MDIO_EEE_10GKX4
-#define MDIO_EEE_10GKX4		0x0020	/* 10G KX4 EEE cap */
+#define MDIO_EEE_10GKX4 0x0020 /* 10G KX4 EEE cap */
 #endif
 #ifndef MDIO_EEE_10GKR
-#define MDIO_EEE_10GKR		0x0040	/* 10G KR EEE cap */
+#define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE cap */
 #endif
 
 #ifndef __GFP_MEMALLOC
@@ -4167,9 +4253,9 @@ static inline void _kc_eth_broadcast_addr(u8 *addr)
 #define eth_random_addr _kc_eth_random_addr
 static inline void _kc_eth_random_addr(u8 *addr)
 {
-        get_random_bytes(addr, ETH_ALEN);
-        addr[0] &= 0xfe; /* clear multicast */
-        addr[0] |= 0x02; /* set local assignment */
+	get_random_bytes(addr, ETH_ALEN);
+	addr[0] &= 0xfe; /* clear multicast */
+	addr[0] |= 0x02; /* set local assignment */
 }
 #endif /* eth_random_addr */
 
@@ -4181,20 +4267,20 @@ static inline void _kc_eth_random_addr(u8 *addr)
 #endif /* < 3.6.0 */
 
 /******************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0))
 #include <linux/workqueue.h>
 #ifndef ADVERTISED_40000baseKR4_Full
 /* these defines were all added in one commit, so should be safe
- * to trigger activiation on one define
- */
-#define SUPPORTED_40000baseKR4_Full	BIT(23)
-#define SUPPORTED_40000baseCR4_Full	BIT(24)
-#define SUPPORTED_40000baseSR4_Full	BIT(25)
-#define SUPPORTED_40000baseLR4_Full	BIT(26)
-#define ADVERTISED_40000baseKR4_Full	BIT(23)
-#define ADVERTISED_40000baseCR4_Full	BIT(24)
-#define ADVERTISED_40000baseSR4_Full	BIT(25)
-#define ADVERTISED_40000baseLR4_Full	BIT(26)
+* to trigger activiation on one define
+*/
+#define SUPPORTED_40000baseKR4_Full BIT(23)
+#define SUPPORTED_40000baseCR4_Full BIT(24)
+#define SUPPORTED_40000baseSR4_Full BIT(25)
+#define SUPPORTED_40000baseLR4_Full BIT(26)
+#define ADVERTISED_40000baseKR4_Full BIT(23)
+#define ADVERTISED_40000baseCR4_Full BIT(24)
+#define ADVERTISED_40000baseSR4_Full BIT(25)
+#define ADVERTISED_40000baseLR4_Full BIT(26)
 #endif
 
 #ifndef mmd_eee_cap_to_ethtool_sup_t
@@ -4293,7 +4379,7 @@ static inline u16 __kc_ethtool_adv_to_mmd_eee_adv_t(u32 adv)
 #endif /* ethtool_adv_to_mmd_eee_adv_t */
 
 #ifndef pci_pcie_type
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
 static inline u8 pci_pcie_type(struct pci_dev *pdev)
 {
 	int pos;
@@ -4305,74 +4391,76 @@ static inline u8 pci_pcie_type(struct pci_dev *pdev)
 	return (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
 }
 #else /* < 2.6.24 */
-#define pci_pcie_type(x)	(x)->pcie_type
+#define pci_pcie_type(x) (x)->pcie_type
 #endif /* < 2.6.24 */
 #endif /* pci_pcie_type */
 
-#if ( ! ( RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4) ) ) && \
-    ( ! ( SLE_VERSION_CODE >= SLE_VERSION(11,3,0) ) ) && \
-    ( LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) )
+#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 4))) && \
+		(!(SLE_VERSION_CODE >= SLE_VERSION(11, 3, 0))) &&   \
+		(LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
 #define ptp_clock_register(caps, args...) ptp_clock_register(caps)
 #endif
 
 #ifndef pcie_capability_read_word
 int __kc_pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
-#define pcie_capability_read_word(d,p,v) __kc_pcie_capability_read_word(d,p,v)
+#define pcie_capability_read_word(d, p, v) \
+	__kc_pcie_capability_read_word(d, p, v)
 #endif /* pcie_capability_read_word */
 
 #ifndef pcie_capability_read_dword
 int __kc_pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
-#define pcie_capability_read_dword(d,p,v) __kc_pcie_capability_read_dword(d,p,v)
+#define pcie_capability_read_dword(d, p, v) \
+	__kc_pcie_capability_read_dword(d, p, v)
 #endif
 
 #ifndef pcie_capability_write_word
 int __kc_pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
-#define pcie_capability_write_word(d,p,v) __kc_pcie_capability_write_word(d,p,v)
+#define pcie_capability_write_word(d, p, v) \
+	__kc_pcie_capability_write_word(d, p, v)
 #endif /* pcie_capability_write_word */
 
 #ifndef pcie_capability_clear_and_set_word
 int __kc_pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
-					    u16 clear, u16 set);
-#define pcie_capability_clear_and_set_word(d,p,c,s) \
-	__kc_pcie_capability_clear_and_set_word(d,p,c,s)
+											u16 clear, u16 set);
+#define pcie_capability_clear_and_set_word(d, p, c, s) \
+	__kc_pcie_capability_clear_and_set_word(d, p, c, s)
 #endif /* pcie_capability_clear_and_set_word */
 
 #ifndef pcie_capability_clear_word
-int __kc_pcie_capability_clear_word(struct pci_dev *dev, int pos,
-					     u16 clear);
+int __kc_pcie_capability_clear_word(struct pci_dev *dev, int pos, u16 clear);
 #define pcie_capability_clear_word(d, p, c) \
 	__kc_pcie_capability_clear_word(d, p, c)
 #endif /* pcie_capability_clear_word */
 
 #ifndef PCI_EXP_LNKSTA2
-#define PCI_EXP_LNKSTA2		50	/* Link Status 2 */
+#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
 #endif
 
-#if (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,3,0))
+#if (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11, 3, 0))
 #define USE_CONST_DEV_UC_CHAR
 #define HAVE_NDO_FDB_ADD_NLATTR
 #endif
 
-#if !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,8))
+#if !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 8))
 #define napi_gro_flush(_napi, _flush_old) napi_gro_flush(_napi)
 #endif /* !RHEL6.8+ */
 
-#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,6))
+#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 6))
 #include <linux/hashtable.h>
 #else
 
-#define DEFINE_HASHTABLE(name, bits)						\
-	struct hlist_head name[1 << (bits)] =					\
-			{ [0 ... ((1 << (bits)) - 1)] = HLIST_HEAD_INIT }
+#define DEFINE_HASHTABLE(name, bits)                                     \
+	struct hlist_head name[1 << (bits)] = { [0 ...((1 << (bits)) - 1)] = \
+													HLIST_HEAD_INIT }
 
-#define DECLARE_HASHTABLE(name, bits)                                   	\
-	struct hlist_head name[1 << (bits)]
+#define DECLARE_HASHTABLE(name, bits) struct hlist_head name[1 << (bits)]
 
 #define HASH_SIZE(name) (ARRAY_SIZE(name))
 #define HASH_BITS(name) ilog2(HASH_SIZE(name))
 
-/* Use hash_32 when possible to allow for fast 32bit hashing in 64bit kernels. */
-#define hash_min(val, bits)							\
+/* Use hash_32 when possible to allow for fast 32bit hashing in 64bit kernels.
+*/
+#define hash_min(val, bits) \
 	(sizeof(val) <= 4 ? hash_32(val, bits) : hash_long(val, bits))
 
 static inline void __hash_init(struct hlist_head *ht, unsigned int sz)
@@ -4385,7 +4473,7 @@ static inline void __hash_init(struct hlist_head *ht, unsigned int sz)
 
 #define hash_init(hashtable) __hash_init(hashtable, HASH_SIZE(hashtable))
 
-#define hash_add(hashtable, node, key)						\
+#define hash_add(hashtable, node, key) \
 	hlist_add_head(node, &hashtable[hash_min(key, HASH_BITS(hashtable))])
 
 static inline bool hash_hashed(struct hlist_node *node)
@@ -4413,13 +4501,13 @@ static inline void hash_del(struct hlist_node *node)
 #endif /* RHEL >= 6.6 */
 
 /* We don't have @flags support prior to 3.7, so we'll simply ignore the flags
- * parameter on these older kernels.
- */
-#define __setup_timer(_timer, _fn, _data, _flags)	\
-	setup_timer((_timer), (_fn), (_data))		\
+* parameter on these older kernels.
+*/
+#define __setup_timer(_timer, _fn, _data, _flags) \
+	setup_timer((_timer), (_fn), (_data))
 
-#if ( ! ( RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,7) ) ) && \
-	( ! ( SLE_VERSION_CODE >= SLE_VERSION(12,0,0) ) )
+#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 7))) && \
+		(!(SLE_VERSION_CODE >= SLE_VERSION(12, 0, 0)))
 
 #ifndef mod_delayed_work
 /**
@@ -4437,9 +4525,8 @@ static inline void hash_del(struct hlist_node *node)
  *       implementation flags are not preserved and it shouldn't be
  *       used in the interrupt context.
  */
-static inline bool __mod_delayed_work(struct workqueue_struct *wq,
-				    void *dwork,
-				    unsigned long delay)
+static inline bool __mod_delayed_work(struct workqueue_struct *wq, void *dwork,
+									unsigned long delay)
 {
 	bool ret = cancel_delayed_work(dwork);
 	queue_delayed_work(wq, dwork, delay);
@@ -4457,11 +4544,14 @@ static inline bool __mod_delayed_work(struct workqueue_struct *wq,
 #endif /* >= 3.7.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0) )
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,5)) && \
-     !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,4,0)))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
+#if (!(RHEL_RELEASE_CODE &&                                \
+	RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 5)) && \
+	!(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11, 4, 0)))
 #ifndef pci_sriov_set_totalvfs
-static inline int __kc_pci_sriov_set_totalvfs(struct pci_dev __always_unused *dev, u16 __always_unused numvfs)
+static inline int
+__kc_pci_sriov_set_totalvfs(struct pci_dev __always_unused *dev,
+							u16 __always_unused numvfs)
 {
 	return 0;
 }
@@ -4469,15 +4559,16 @@ static inline int __kc_pci_sriov_set_totalvfs(struct pci_dev __always_unused *de
 #endif
 #endif /* !(RHEL_RELEASE_CODE >= 6.5 && SLE_VERSION_CODE >= 11.4) */
 #ifndef PCI_EXP_LNKCTL_ASPM_L0S
-#define  PCI_EXP_LNKCTL_ASPM_L0S  0x01	/* L0s Enable */
+#define PCI_EXP_LNKCTL_ASPM_L0S 0x01 /* L0s Enable */
 #endif
 #ifndef PCI_EXP_LNKCTL_ASPM_L1
-#define  PCI_EXP_LNKCTL_ASPM_L1   0x02	/* L1 Enable */
+#define PCI_EXP_LNKCTL_ASPM_L1 0x02 /* L1 Enable */
 #endif
 #define HAVE_CONFIG_HOTPLUG
 /* Reserved Ethernet Addresses per IEEE 802.1Q */
-static const u8 eth_reserved_addr_base[ETH_ALEN] __aligned(2) = {
-	0x01, 0x80, 0xc2, 0x00, 0x00, 0x00 };
+static const u8 eth_reserved_addr_base[ETH_ALEN] __aligned(2) = { 0x01, 0x80,
+																0xc2, 0x00,
+																0x00, 0x00 };
 
 #ifndef is_link_local_ether_addr
 static inline bool __kc_is_link_local_ether_addr(const u8 *addr)
@@ -4492,10 +4583,10 @@ static inline bool __kc_is_link_local_ether_addr(const u8 *addr)
 #endif /* is_link_local_ether_addr */
 
 #ifndef FLOW_MAC_EXT
-#define FLOW_MAC_EXT	0x40000000
+#define FLOW_MAC_EXT 0x40000000
 #endif /* FLOW_MAC_EXT */
 
-#if (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,4,0))
+#if (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11, 4, 0))
 #define HAVE_SRIOV_CONFIGURE
 #endif
 
@@ -4525,10 +4616,6 @@ static inline bool __kc_is_link_local_ether_addr(const u8 *addr)
 #define __devinitdata
 #endif
 
-#ifndef __devinitconst
-#define __devinitconst
-#endif
-
 #ifndef __devexit
 #define __devexit
 #endif
@@ -4551,15 +4638,15 @@ static inline bool __kc_is_link_local_ether_addr(const u8 *addr)
 
 #define HAVE_BRIDGE_ATTRIBS
 #ifndef BRIDGE_MODE_VEB
-#define BRIDGE_MODE_VEB		0	/* Default loopback mode */
+#define BRIDGE_MODE_VEB 0 /* Default loopback mode */
 #endif /* BRIDGE_MODE_VEB */
 #ifndef BRIDGE_MODE_VEPA
-#define BRIDGE_MODE_VEPA	1	/* 802.1Qbg defined VEPA mode */
+#define BRIDGE_MODE_VEPA 1 /* 802.1Qbg defined VEPA mode */
 #endif /* BRIDGE_MODE_VEPA */
 #endif /* >= 3.8.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,9,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
 
 #undef BUILD_BUG_ON
 #ifdef __CHECKER__
@@ -4575,22 +4662,28 @@ static inline bool __kc_is_link_local_ether_addr(const u8 *addr)
 #ifndef __compiletime_error
 #if defined(__GNUC__) && ((__GNUC__ * 10000 + __GNUC_MINOR__ * 100) >= 40400)
 #define __compiletime_error(message) __attribute__((error(message)))
-#define __compiletime_error_fallback(condition) do { } while (0)
+#define __compiletime_error_fallback(condition) \
+	do {                                        \
+	} while (0)
 #else /* __GNUC__ */
 #define __compiletime_error(message)
-#define __compiletime_error_fallback(condition) \
-	do { ((void)sizeof(char[1 - 2 * condition])); } while (0)
+#define __compiletime_error_fallback(condition)  \
+	do {                                         \
+		((void)sizeof(char[1 - 2 * condition])); \
+	} while (0)
 #endif /* __GNUC__ */
 #else /* __compiletime_error */
-#define __compiletime_error_fallback(condition) do { } while (0)
+#define __compiletime_error_fallback(condition) \
+	do {                                        \
+	} while (0)
 #endif /* __compiletime_error */
-#define __compiletime_assert(condition, msg, prefix, suffix)		\
-	do {								\
-		bool __cond = !(condition);				\
-		extern void prefix ## suffix(void) __compiletime_error(msg); \
-		if (__cond)						\
-			prefix ## suffix();				\
-		__compiletime_error_fallback(__cond);			\
+#define __compiletime_assert(condition, msg, prefix, suffix)       \
+	do {                                                           \
+		bool __cond = !(condition);                                \
+		extern void prefix##suffix(void) __compiletime_error(msg); \
+		if (__cond)                                                \
+			prefix##suffix();                                      \
+		__compiletime_error_fallback(__cond);                      \
 	} while (0)
 
 #define _compiletime_assert(condition, msg, prefix, suffix) \
@@ -4599,7 +4692,7 @@ static inline bool __kc_is_link_local_ether_addr(const u8 *addr)
 	_compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
 #ifndef __OPTIMIZE__
-#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
+#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2 * !!(condition)]))
 #else /* __OPTIMIZE__ */
 #define BUILD_BUG_ON(condition) \
 	BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
@@ -4607,63 +4700,69 @@ static inline bool __kc_is_link_local_ether_addr(const u8 *addr)
 #endif /* __CHECKER__ */
 
 #undef hlist_entry
-#define hlist_entry(ptr, type, member) container_of(ptr,type,member)
+#define hlist_entry(ptr, type, member) container_of(ptr, type, member)
 
 #undef hlist_entry_safe
-#define hlist_entry_safe(ptr, type, member) \
-	({ typeof(ptr) ____ptr = (ptr); \
-	   ____ptr ? hlist_entry(____ptr, type, member) : NULL; \
+#define hlist_entry_safe(ptr, type, member)                  \
+	({                                                       \
+		typeof(ptr) ____ptr = (ptr);                         \
+		____ptr ? hlist_entry(____ptr, type, member) : NULL; \
 	})
 
 #undef hlist_for_each_entry
-#define hlist_for_each_entry(pos, head, member)                             \
-	for (pos = hlist_entry_safe((head)->first, typeof(*(pos)), member); \
-	     pos;                                                           \
-	     pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member))
+#define hlist_for_each_entry(pos, head, member)                              \
+	for (pos = hlist_entry_safe((head)->first, typeof(*(pos)), member); pos; \
+		pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member))
 
 #undef hlist_for_each_entry_safe
-#define hlist_for_each_entry_safe(pos, n, head, member) 		    \
-	for (pos = hlist_entry_safe((head)->first, typeof(*pos), member);   \
-	     pos && ({ n = pos->member.next; 1; });			    \
-	     pos = hlist_entry_safe(n, typeof(*pos), member))
+#define hlist_for_each_entry_safe(pos, n, head, member)               \
+	for (pos = hlist_entry_safe((head)->first, typeof(*pos), member); \
+		pos && ({                                                    \
+			n = pos->member.next;                                    \
+			1;                                                       \
+		});                                                          \
+		pos = hlist_entry_safe(n, typeof(*pos), member))
 
 #undef hlist_for_each_entry_continue
-#define hlist_for_each_entry_continue(pos, member)			\
-	for (pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member);\
-	     pos;							\
-	     pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member))
+#define hlist_for_each_entry_continue(pos, member)                           \
+	for (pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member); \
+		pos;                                                                \
+		pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member))
 
 #undef hlist_for_each_entry_from
-#define hlist_for_each_entry_from(pos, member)				\
-	for (; pos;							\
-	     pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member))
+#define hlist_for_each_entry_from(pos, member) \
+	for (; pos;                                \
+		pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member))
 
 #undef hash_for_each
-#define hash_for_each(name, bkt, obj, member)				\
-	for ((bkt) = 0, obj = NULL; obj == NULL && (bkt) < HASH_SIZE(name);\
-			(bkt)++)\
+#define hash_for_each(name, bkt, obj, member)                           \
+	for ((bkt) = 0, obj = NULL; obj == NULL && (bkt) < HASH_SIZE(name); \
+		(bkt)++)                                                       \
 		hlist_for_each_entry(obj, &name[bkt], member)
 
 #undef hash_for_each_safe
-#define hash_for_each_safe(name, bkt, tmp, obj, member)			\
-	for ((bkt) = 0, obj = NULL; obj == NULL && (bkt) < HASH_SIZE(name);\
-			(bkt)++)\
+#define hash_for_each_safe(name, bkt, tmp, obj, member)                 \
+	for ((bkt) = 0, obj = NULL; obj == NULL && (bkt) < HASH_SIZE(name); \
+		(bkt)++)                                                       \
 		hlist_for_each_entry_safe(obj, tmp, &name[bkt], member)
 
 #undef hash_for_each_possible
-#define hash_for_each_possible(name, obj, member, key)			\
+#define hash_for_each_possible(name, obj, member, key) \
 	hlist_for_each_entry(obj, &name[hash_min(key, HASH_BITS(name))], member)
 
 #undef hash_for_each_possible_safe
-#define hash_for_each_possible_safe(name, obj, tmp, member, key)	\
-	hlist_for_each_entry_safe(obj, tmp,\
-		&name[hash_min(key, HASH_BITS(name))], member)
+#define hash_for_each_possible_safe(name, obj, tmp, member, key)               \
+	hlist_for_each_entry_safe(obj, tmp, &name[hash_min(key, HASH_BITS(name))], \
+							member)
 
 #ifdef CONFIG_XPS
 int __kc_netif_set_xps_queue(struct net_device *, const struct cpumask *, u16);
-#define netif_set_xps_queue(_dev, _mask, _idx) __kc_netif_set_xps_queue((_dev), (_mask), (_idx))
+#define netif_set_xps_queue(_dev, _mask, _idx) \
+	__kc_netif_set_xps_queue((_dev), (_mask), (_idx))
 #else /* CONFIG_XPS */
-#define netif_set_xps_queue(_dev, _mask, _idx) do {} while (0)
+#define netif_set_xps_queue(_dev, _mask, _idx) \
+	do {                                       \
+	} while (0)
 #endif /* CONFIG_XPS */
 
 #ifdef HAVE_NETDEV_SELECT_QUEUE
@@ -4677,7 +4776,7 @@ u16 __kc_netdev_pick_tx(struct net_device *dev, struct sk_buff *skb);
 #endif /* < 3.9.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))
 #ifndef NAPI_POLL_WEIGHT
 #define NAPI_POLL_WEIGHT 64
 #endif
@@ -4698,13 +4797,13 @@ static inline int __kc_pci_vfs_assigned(struct pci_dev __always_unused *dev)
 
 #ifndef VLAN_TX_COOKIE_MAGIC
 static inline struct sk_buff *__kc__vlan_hwaccel_put_tag(struct sk_buff *skb,
-							 u16 vlan_tci)
+														u16 vlan_tci)
 {
 #ifdef VLAN_TAG_PRESENT
 	vlan_tci |= VLAN_TAG_PRESENT;
 #endif
 	skb->vlan_tci = vlan_tci;
-        return skb;
+	return skb;
 }
 #define __vlan_hwaccel_put_tag(skb, vlan_proto, vlan_tci) \
 	__kc__vlan_hwaccel_put_tag(skb, vlan_tci)
@@ -4713,42 +4812,41 @@ static inline struct sk_buff *__kc__vlan_hwaccel_put_tag(struct sk_buff *skb,
 #ifdef HAVE_FDB_OPS
 #if defined(HAVE_NDO_FDB_ADD_NLATTR)
 int __kc_ndo_dflt_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
-			  struct net_device *dev,
-			  const unsigned char *addr, u16 flags);
+						struct net_device *dev, const unsigned char *addr,
+						u16 flags);
 #elif defined(USE_CONST_DEV_UC_CHAR)
 int __kc_ndo_dflt_fdb_add(struct ndmsg *ndm, struct net_device *dev,
-			  const unsigned char *addr, u16 flags);
+						const unsigned char *addr, u16 flags);
 #else
 int __kc_ndo_dflt_fdb_add(struct ndmsg *ndm, struct net_device *dev,
-			  unsigned char *addr, u16 flags);
+						unsigned char *addr, u16 flags);
 #endif /* HAVE_NDO_FDB_ADD_NLATTR */
 #if defined(HAVE_FDB_DEL_NLATTR)
 int __kc_ndo_dflt_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
-			  struct net_device *dev,
-			  const unsigned char *addr);
+						struct net_device *dev, const unsigned char *addr);
 #elif defined(USE_CONST_DEV_UC_CHAR)
 int __kc_ndo_dflt_fdb_del(struct ndmsg *ndm, struct net_device *dev,
-			  const unsigned char *addr);
+						const unsigned char *addr);
 #else
 int __kc_ndo_dflt_fdb_del(struct ndmsg *ndm, struct net_device *dev,
-			  unsigned char *addr);
+						unsigned char *addr);
 #endif /* HAVE_FDB_DEL_NLATTR */
 #define ndo_dflt_fdb_add __kc_ndo_dflt_fdb_add
 #define ndo_dflt_fdb_del __kc_ndo_dflt_fdb_del
 #endif /* HAVE_FDB_OPS */
 
 #ifndef PCI_DEVID
-#define PCI_DEVID(bus, devfn)  ((((u16)(bus)) << 8) | (devfn))
+#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
 #endif
 
 /* The definitions for these functions when CONFIG_OF_NET is defined are
- * pulled in from <linux/of_net.h>. For kernels older than 3.5 we already have
- * backports for when CONFIG_OF_NET is true. These are separated and
- * duplicated in order to cover all cases so that all kernels get either the
- * real definitions (when CONFIG_OF_NET is defined) or the stub definitions
- * (when CONFIG_OF_NET is not defined, or the kernel is too old to have real
- * definitions).
- */
+* pulled in from <linux/of_net.h>. For kernels older than 3.5 we already have
+* backports for when CONFIG_OF_NET is true. These are separated and
+* duplicated in order to cover all cases so that all kernels get either the
+* real definitions (when CONFIG_OF_NET is defined) or the stub definitions
+* (when CONFIG_OF_NET is not defined, or the kernel is too old to have real
+* definitions).
+*/
 #ifndef CONFIG_OF_NET
 static inline int of_get_phy_mode(struct device_node __always_unused *np)
 {
@@ -4767,15 +4865,14 @@ of_get_mac_address(struct device_node __always_unused *np)
 #define USE_DEFAULT_FDB_DEL_DUMP
 #define HAVE_SKB_INNER_NETWORK_HEADER
 
-#if (RHEL_RELEASE_CODE && \
-     (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,0)))
-#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8,0))
+#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 0)))
+#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8, 0))
 #define HAVE_RHEL7_PCI_DRIVER_RH
-#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2))
+#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 2))
 #define HAVE_RHEL7_PCI_RESET_NOTIFY
 #endif /* RHEL >= 7.2 */
-#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,3))
-#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,5))
+#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 3))
+#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 5))
 #define HAVE_GENEVE_RX_OFFLOAD
 #endif /* RHEL < 7.5 */
 #define HAVE_ETHTOOL_FLOW_UNION_IP6_SPEC
@@ -4786,12 +4883,12 @@ of_get_mac_address(struct device_node __always_unused *np)
 #endif /* RHEL >= 7.3 */
 
 /* new hooks added to net_device_ops_extended in RHEL7.4 */
-#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4))
+#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 4))
 #define HAVE_RHEL7_NETDEV_OPS_EXT_NDO_SET_VF_VLAN
 #define HAVE_RHEL7_NETDEV_OPS_EXT_NDO_UDP_TUNNEL
 #define HAVE_UDP_ENC_RX_OFFLOAD
 #endif /* RHEL >= 7.4 */
-#else  /* RHEL >= 8.0 */
+#else /* RHEL >= 8.0 */
 #define HAVE_TCF_BLOCK_CB_REGISTER_EXTACK
 #define NO_NETDEV_BPF_PROG_ATTACHED
 #define HAVE_NDO_SELECT_QUEUE_SB_DEV
@@ -4800,18 +4897,17 @@ of_get_mac_address(struct device_node __always_unused *np)
 #endif /* >= 3.10.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,11,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0))
 #define netdev_notifier_info_to_dev(ptr) ptr
 #ifndef time_in_range64
 #define time_in_range64(a, b, c) \
-	(time_after_eq64(a, b) && \
-	 time_before_eq64(a, c))
+	(time_after_eq64(a, b) && time_before_eq64(a, c))
 #endif /* time_in_range64 */
-#if ((RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,6)) ||\
-     (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,4,0)))
+#if ((RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 6)) || \
+	(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11, 4, 0)))
 #define HAVE_NDO_SET_VF_LINK_STATE
 #endif
-#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2))
+#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7, 2))
 #define HAVE_NDO_SELECT_QUEUE_ACCEL_FALLBACK
 #endif
 #else /* >= 3.11.0 */
@@ -4821,23 +4917,23 @@ of_get_mac_address(struct device_node __always_unused *np)
 #endif /* >= 3.11.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,12,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 12, 0))
 int __kc_pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
-			       enum pcie_link_width *width);
+							enum pcie_link_width *width);
 #ifndef pcie_get_minimum_link
 #define pcie_get_minimum_link(_p, _s, _w) __kc_pcie_get_minimum_link(_p, _s, _w)
 #endif
 
-#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,7))
+#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6, 7))
 int _kc_pci_wait_for_pending_transaction(struct pci_dev *dev);
 #define pci_wait_for_pending_transaction _kc_pci_wait_for_pending_transaction
 #endif /* <RHEL6.7 */
 
 #else /* >= 3.12.0 */
-#if ( SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(12,0,0))
+#if (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(12, 0, 0))
 #define HAVE_NDO_SELECT_QUEUE_ACCEL_FALLBACK
 #endif
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,8,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
 #define HAVE_VXLAN_RX_OFFLOAD
 #if !defined(HAVE_UDP_ENC_TUNNEL) && IS_ENABLED(CONFIG_VXLAN)
 #define HAVE_UDP_ENC_TUNNEL
@@ -4848,17 +4944,19 @@ int _kc_pci_wait_for_pending_transaction(struct pci_dev *dev);
 #endif /* >= 3.12.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0))
 #define dma_set_mask_and_coherent(_p, _m) __kc_dma_set_mask_and_coherent(_p, _m)
 int __kc_dma_set_mask_and_coherent(struct device *dev, u64 mask);
 #ifndef u64_stats_init
-#define u64_stats_init(a) do { } while(0)
+#define u64_stats_init(a) \
+	do {                  \
+	} while (0)
 #endif
 #undef BIT_ULL
 #define BIT_ULL(n) (1ULL << (n))
 
-#if (!(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(12,0,0)) && \
-     !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,0)))
+#if (!(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(12, 0, 0)) && \
+	!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 0)))
 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
 {
 	dev = pci_physfn(dev);
@@ -4869,7 +4967,7 @@ static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
 }
 #endif
 
-#if (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(12,1,0))
+#if (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(12, 1, 0))
 #undef HAVE_STRUCT_PAGE_PFMEMALLOC
 #define HAVE_DCBNL_OPS_SETAPP_RETURN_INT
 #endif
@@ -4882,22 +4980,21 @@ static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
 	list_entry((pos)->member.prev, typeof(*(pos)), member)
 #endif
 
-#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,20) )
-#define devm_kcalloc(dev, cnt, size, flags) \
-	devm_kzalloc(dev, cnt * size, flags)
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 20))
+#define devm_kcalloc(dev, cnt, size, flags) devm_kzalloc(dev, cnt * size, flags)
 #endif /* > 2.6.20 */
 
-#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2)))
+#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 2)))
 #define list_last_entry(ptr, type, member) list_entry((ptr)->prev, type, member)
 #endif
 
-#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0))
+#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 0))
 bool _kc_pci_device_is_present(struct pci_dev *pdev);
 #define pci_device_is_present _kc_pci_device_is_present
 #endif /* <RHEL7.0 */
 #else /* >= 3.13.0 */
 #define HAVE_VXLAN_CHECKS
-#if (UBUNTU_VERSION_CODE && UBUNTU_VERSION_CODE >= UBUNTU_VERSION(3,13,0,24))
+#if (UBUNTU_VERSION_CODE && UBUNTU_VERSION_CODE >= UBUNTU_VERSION(3, 13, 0, 24))
 #define HAVE_NDO_SELECT_QUEUE_ACCEL_FALLBACK
 #else
 #define HAVE_NDO_SELECT_QUEUE_ACCEL
@@ -4906,7 +5003,7 @@ bool _kc_pci_device_is_present(struct pci_dev *pdev);
 #endif
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
 
 #ifndef U16_MAX
 #define U16_MAX ((u16)~0U)
@@ -4920,21 +5017,22 @@ bool _kc_pci_device_is_present(struct pci_dev *pdev);
 #define U64_MAX ((u64)~0ULL)
 #endif
 
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2)))
+#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 2)))
 #define dev_consume_skb_any(x) dev_kfree_skb_any(x)
 #define dev_consume_skb_irq(x) dev_kfree_skb_irq(x)
 #endif
 
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,0)) && \
-     !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(12,0,0)))
+#if (!(RHEL_RELEASE_CODE &&                                \
+	RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 0)) && \
+	!(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(12, 0, 0)))
 
 /* it isn't expected that this would be a #define unless we made it so */
 #ifndef skb_set_hash
 
-#define PKT_HASH_TYPE_NONE	0
-#define PKT_HASH_TYPE_L2	1
-#define PKT_HASH_TYPE_L3	2
-#define PKT_HASH_TYPE_L4	3
+#define PKT_HASH_TYPE_NONE 0
+#define PKT_HASH_TYPE_L2 1
+#define PKT_HASH_TYPE_L3 2
+#define PKT_HASH_TYPE_L4 3
 
 enum _kc_pkt_hash_types {
 	_KC_PKT_HASH_TYPE_NONE = PKT_HASH_TYPE_NONE,
@@ -4942,12 +5040,12 @@ enum _kc_pkt_hash_types {
 	_KC_PKT_HASH_TYPE_L3 = PKT_HASH_TYPE_L3,
 	_KC_PKT_HASH_TYPE_L4 = PKT_HASH_TYPE_L4,
 };
-#define pkt_hash_types         _kc_pkt_hash_types
+#define pkt_hash_types _kc_pkt_hash_types
 
 #define skb_set_hash __kc_skb_set_hash
 static inline void __kc_skb_set_hash(struct sk_buff __maybe_unused *skb,
-				     u32 __maybe_unused hash,
-				     int __maybe_unused type)
+									u32 __maybe_unused hash,
+									int __maybe_unused type)
 {
 #ifdef HAVE_SKB_L4_RXHASH
 	skb->l4_rxhash = (type == PKT_HASH_TYPE_L4);
@@ -4958,15 +5056,15 @@ static inline void __kc_skb_set_hash(struct sk_buff __maybe_unused *skb,
 }
 #endif /* !skb_set_hash */
 
-#else	/* RHEL_RELEASE_CODE >= 7.0 || SLE_VERSION_CODE >= 12.0 */
+#else /* RHEL_RELEASE_CODE >= 7.0 || SLE_VERSION_CODE >= 12.0 */
 
-#if ((RHEL_RELEASE_CODE && RHEL_RELEASE_CODE <= RHEL_RELEASE_VERSION(7,0)) ||\
-     (SLE_VERSION_CODE && SLE_VERSION_CODE <= SLE_VERSION(12,1,0)))
+#if ((RHEL_RELEASE_CODE && RHEL_RELEASE_CODE <= RHEL_RELEASE_VERSION(7, 0)) || \
+	(SLE_VERSION_CODE && SLE_VERSION_CODE <= SLE_VERSION(12, 1, 0)))
 /* GPLv2 code taken from 5.10-rc2 kernel source include/linux/pci.h, Copyright
- * original authors.
- */
+* original authors.
+*/
 static inline int pci_enable_msix_exact(struct pci_dev *dev,
-					struct msix_entry *entries, int nvec)
+										struct msix_entry *entries, int nvec)
 {
 	int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
 	if (rc < 0)
@@ -4974,7 +5072,7 @@ static inline int pci_enable_msix_exact(struct pci_dev *dev,
 	return 0;
 }
 #endif /* <=EL7.0 || <=SLES 12.1 */
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5)))
+#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 5)))
 #ifndef HAVE_VXLAN_RX_OFFLOAD
 #define HAVE_VXLAN_RX_OFFLOAD
 #endif /* HAVE_VXLAN_RX_OFFLOAD */
@@ -4989,14 +5087,14 @@ static inline int pci_enable_msix_exact(struct pci_dev *dev,
 #endif /* HAVE_VXLAN_CHECKS */
 #endif /* !(RHEL_RELEASE_CODE >= 7.0 && SLE_VERSION_CODE >= 12.0) */
 
-#if ((RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,3)) ||\
-     (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(12,0,0)))
+#if ((RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 3)) || \
+	(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(12, 0, 0)))
 #define HAVE_NDO_DFWD_OPS
 #endif
 
 #ifndef pci_enable_msix_range
 int __kc_pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
-			       int minvec, int maxvec);
+							int minvec, int maxvec);
 #define pci_enable_msix_range __kc_pci_enable_msix_range
 #endif
 
@@ -5018,20 +5116,20 @@ static inline void __kc_ether_addr_copy(u8 *dst, const u8 *src)
 }
 #endif /* ether_addr_copy */
 int __kc_ipv6_find_hdr(const struct sk_buff *skb, unsigned int *offset,
-		       int target, unsigned short *fragoff, int *flags);
+					int target, unsigned short *fragoff, int *flags);
 #define ipv6_find_hdr(a, b, c, d, e) __kc_ipv6_find_hdr((a), (b), (c), (d), (e))
 
 #ifndef OPTIMIZE_HIDE_VAR
 #ifdef __GNUC__
-#define OPTIMIZER_HIDE_VAR(var) __asm__ ("" : "=r" (var) : "0" (var))
+#define OPTIMIZER_HIDE_VAR(var) __asm__("" : "=r"(var) : "0"(var))
 #else
 #include <linux/barrier.h>
-#define OPTIMIZE_HIDE_VAR(var)	barrier()
+#define OPTIMIZE_HIDE_VAR(var) barrier()
 #endif
 #endif
 
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,0)) && \
-     !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(10,4,0)))
+#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7, 0)) && \
+	!(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(10, 4, 0)))
 static inline __u32 skb_get_hash_raw(const struct sk_buff *skb)
 {
 #ifdef NETIF_F_RXHASH
@@ -5042,8 +5140,8 @@ static inline __u32 skb_get_hash_raw(const struct sk_buff *skb)
 }
 #endif /* !RHEL > 5.9 && !SLES >= 10.4 */
 
-#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,5))
-#define request_firmware_direct	request_firmware
+#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 5))
+#define request_firmware_direct request_firmware
 #endif /* !RHEL || RHEL < 7.5 */
 
 #else /* >= 3.14.0 */
@@ -5056,12 +5154,13 @@ static inline __u32 skb_get_hash_raw(const struct sk_buff *skb)
 #endif /* 3.14.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0) )
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35))
 #define HAVE_SKBUFF_RXHASH
 #endif /* >= 2.6.35 */
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,1)) && \
-     !(UBUNTU_VERSION_CODE && UBUNTU_VERSION_CODE >= UBUNTU_VERSION(3,13,0,30)))
+#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7, 1)) && \
+	!(UBUNTU_VERSION_CODE &&                                                  \
+	UBUNTU_VERSION_CODE >= UBUNTU_VERSION(3, 13, 0, 30)))
 #define u64_stats_fetch_begin_irq u64_stats_fetch_begin_bh
 #define u64_stats_fetch_retry_irq u64_stats_fetch_retry_bh
 #endif
@@ -5076,50 +5175,56 @@ char *_kc_devm_kstrdup(struct device *dev, const char *s, gfp_t gfp);
 #endif /* 3.15.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,16,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
 #ifndef smp_mb__before_atomic
 #define smp_mb__before_atomic() smp_mb()
-#define smp_mb__after_atomic()  smp_mb()
+#define smp_mb__after_atomic() smp_mb()
 #endif
 #ifndef __dev_uc_sync
 #ifdef HAVE_SET_RX_MODE
 #ifdef NETDEV_HW_ADDR_T_UNICAST
-int __kc_hw_addr_sync_dev(struct netdev_hw_addr_list *list,
-		struct net_device *dev,
+int __kc_hw_addr_sync_dev(
+		struct netdev_hw_addr_list *list, struct net_device *dev,
 		int (*sync)(struct net_device *, const unsigned char *),
 		int (*unsync)(struct net_device *, const unsigned char *));
 void __kc_hw_addr_unsync_dev(struct netdev_hw_addr_list *list,
-		struct net_device *dev,
-		int (*unsync)(struct net_device *, const unsigned char *));
+							struct net_device *dev,
+							int (*unsync)(struct net_device *,
+										const unsigned char *));
 #endif
 #ifndef NETDEV_HW_ADDR_T_MULTICAST
-int __kc_dev_addr_sync_dev(struct dev_addr_list **list, int *count,
-		struct net_device *dev,
+int __kc_dev_addr_sync_dev(
+		struct dev_addr_list **list, int *count, struct net_device *dev,
 		int (*sync)(struct net_device *, const unsigned char *),
 		int (*unsync)(struct net_device *, const unsigned char *));
 void __kc_dev_addr_unsync_dev(struct dev_addr_list **list, int *count,
-		struct net_device *dev,
-		int (*unsync)(struct net_device *, const unsigned char *));
+							struct net_device *dev,
+							int (*unsync)(struct net_device *,
+											const unsigned char *));
 #endif
 #endif /* HAVE_SET_RX_MODE */
 
-static inline int __kc_dev_uc_sync(struct net_device __maybe_unused *dev,
-				   int __maybe_unused (*sync)(struct net_device *, const unsigned char *),
-				   int __maybe_unused (*unsync)(struct net_device *, const unsigned char *))
+static inline int __kc_dev_uc_sync(
+		struct net_device __maybe_unused *dev,
+		int __maybe_unused (*sync)(struct net_device *, const unsigned char *),
+		int __maybe_unused (*unsync)(struct net_device *,
+									const unsigned char *))
 {
 #ifdef NETDEV_HW_ADDR_T_UNICAST
 	return __kc_hw_addr_sync_dev(&dev->uc, dev, sync, unsync);
 #elif defined(HAVE_SET_RX_MODE)
-	return __kc_dev_addr_sync_dev(&dev->uc_list, &dev->uc_count,
-				      dev, sync, unsync);
+	return __kc_dev_addr_sync_dev(&dev->uc_list, &dev->uc_count, dev, sync,
+								unsync);
 #else
 	return 0;
 #endif
 }
 #define __dev_uc_sync __kc_dev_uc_sync
 
-static inline void __kc_dev_uc_unsync(struct net_device __maybe_unused *dev,
-				      int __maybe_unused (*unsync)(struct net_device *, const unsigned char *))
+static inline void
+__kc_dev_uc_unsync(struct net_device __maybe_unused *dev,
+				int __maybe_unused (*unsync)(struct net_device *,
+												const unsigned char *))
 {
 #ifdef HAVE_SET_RX_MODE
 #ifdef NETDEV_HW_ADDR_T_UNICAST
@@ -5131,24 +5236,27 @@ static inline void __kc_dev_uc_unsync(struct net_device __maybe_unused *dev,
 }
 #define __dev_uc_unsync __kc_dev_uc_unsync
 
-static inline int __kc_dev_mc_sync(struct net_device __maybe_unused *dev,
-				   int __maybe_unused (*sync)(struct net_device *, const unsigned char *),
-				   int __maybe_unused (*unsync)(struct net_device *, const unsigned char *))
+static inline int __kc_dev_mc_sync(
+		struct net_device __maybe_unused *dev,
+		int __maybe_unused (*sync)(struct net_device *, const unsigned char *),
+		int __maybe_unused (*unsync)(struct net_device *,
+									const unsigned char *))
 {
 #ifdef NETDEV_HW_ADDR_T_MULTICAST
 	return __kc_hw_addr_sync_dev(&dev->mc, dev, sync, unsync);
 #elif defined(HAVE_SET_RX_MODE)
-	return __kc_dev_addr_sync_dev(&dev->mc_list, &dev->mc_count,
-				      dev, sync, unsync);
+	return __kc_dev_addr_sync_dev(&dev->mc_list, &dev->mc_count, dev, sync,
+								unsync);
 #else
 	return 0;
 #endif
-
 }
 #define __dev_mc_sync __kc_dev_mc_sync
 
-static inline void __kc_dev_mc_unsync(struct net_device __maybe_unused *dev,
-				      int __maybe_unused (*unsync)(struct net_device *, const unsigned char *))
+static inline void
+__kc_dev_mc_unsync(struct net_device __maybe_unused *dev,
+				int __maybe_unused (*unsync)(struct net_device *,
+												const unsigned char *))
 {
 #ifdef HAVE_SET_RX_MODE
 #ifdef NETDEV_HW_ADDR_T_MULTICAST
@@ -5161,42 +5269,43 @@ static inline void __kc_dev_mc_unsync(struct net_device __maybe_unused *dev,
 #define __dev_mc_unsync __kc_dev_mc_unsync
 #endif /* __dev_uc_sync */
 
-#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,1))
+#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7, 1))
 #define HAVE_NDO_SET_VF_MIN_MAX_TX_RATE
 #endif
 
 #ifndef NETIF_F_GSO_UDP_TUNNEL_CSUM
 /* if someone backports this, hopefully they backport as a #define.
- * declare it as zero on older kernels so that if it get's or'd in
- * it won't effect anything, therefore preventing core driver changes
- */
+* declare it as zero on older kernels so that if it get's or'd in
+* it won't effect anything, therefore preventing core driver changes
+*/
 #define NETIF_F_GSO_UDP_TUNNEL_CSUM 0
 #define SKB_GSO_UDP_TUNNEL_CSUM 0
 #endif
 void *__kc_devm_kmemdup(struct device *dev, const void *src, size_t len,
-			gfp_t gfp);
+						gfp_t gfp);
 #define devm_kmemdup __kc_devm_kmemdup
 
 #else
-#if ( ( LINUX_VERSION_CODE < KERNEL_VERSION(4,13,0) ) && \
-      ! ( SLE_VERSION_CODE && ( SLE_VERSION_CODE >= SLE_VERSION(12,4,0)) ) )
+#if ((LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0)) && \
+	!(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12, 4, 0))))
 #define HAVE_PCI_ERROR_HANDLER_RESET_NOTIFY
 #endif /* >= 3.16.0 && < 4.13.0 && !(SLES >= 12sp4) */
 #define HAVE_NDO_SET_VF_MIN_MAX_TX_RATE
 #endif /* 3.16.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,17,0) )
-#if !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,8) && \
-      RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)) && \
-    !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 17, 0))
+#if !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 8) && \
+	RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 0)) && \
+		!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 2))
 #ifndef timespec64
 #define timespec64 timespec
 static inline struct timespec64 timespec_to_timespec64(const struct timespec ts)
 {
 	return ts;
 }
-static inline struct timespec timespec64_to_timespec(const struct timespec64 ts64)
+static inline struct timespec
+timespec64_to_timespec(const struct timespec64 ts64)
 {
 	return ts64;
 }
@@ -5217,8 +5326,8 @@ static inline struct timespec timespec64_to_timespec(const struct timespec64 ts6
 #endif /* timespec64 */
 #endif /* !(RHEL6.8<RHEL7.0) && !RHEL7.2+ */
 
-#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,8) && \
-     RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0))
+#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 8) && \
+	RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 0))
 static inline void ktime_get_real_ts64(struct timespec64 *ts)
 {
 	*ts = ktime_to_timespec64(ktime_get_real());
@@ -5230,16 +5339,15 @@ static inline void ktime_get_ts64(struct timespec64 *ts)
 }
 #endif
 
-#if !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4))
+#if !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 4))
 #define hlist_add_behind(_a, _b) hlist_add_after(_b, _a)
 #endif
 
-#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,5))
+#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 5))
 #endif /* RHEL_RELEASE_CODE < RHEL7.5 */
 
-#if RHEL_RELEASE_CODE && \
-	RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,3) && \
-	RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,3)
+#if RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6, 3) && \
+		RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 3)
 static inline u64 ktime_get_ns(void)
 {
 	return ktime_to_ns(ktime_get());
@@ -5263,18 +5371,18 @@ static inline u64 ktime_get_boot_ns(void)
 #endif /* 3.17.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,18,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0))
 #ifndef NO_PTP_SUPPORT
 #include <linux/errqueue.h>
 struct sk_buff *__kc_skb_clone_sk(struct sk_buff *skb);
 void __kc_skb_complete_tx_timestamp(struct sk_buff *skb,
-				    struct skb_shared_hwtstamps *hwtstamps);
+									struct skb_shared_hwtstamps *hwtstamps);
 #define skb_clone_sk __kc_skb_clone_sk
 #define skb_complete_tx_timestamp __kc_skb_complete_tx_timestamp
 #endif
-#if (!(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,2))))
+#if (!(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 2))))
 u32 __kc_eth_get_headlen(const struct net_device *dev, unsigned char *data,
-			 unsigned int max_len);
+						unsigned int max_len);
 #else
 unsigned int __kc_eth_get_headlen(unsigned char *data, unsigned int max_len);
 #endif /* !RHEL >= 8.2 */
@@ -5284,18 +5392,17 @@ unsigned int __kc_eth_get_headlen(unsigned char *data, unsigned int max_len);
 #define ETH_P_XDSA 0x00F8
 #endif
 /* RHEL 7.1 backported csum_level, but SLES 12 and 12-SP1 did not */
-#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,1))
+#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 1))
 #define HAVE_SKBUFF_CSUM_LEVEL
 #endif /* >= RH 7.1 */
 
 /* RHEL 7.3 backported xmit_more */
-#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,3))
+#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 3))
 #define HAVE_SKB_XMIT_MORE
 #endif /* >= RH 7.3 */
 
 #undef GENMASK
-#define GENMASK(h, l) \
-	(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
+#define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
 #undef GENMASK_ULL
 #define GENMASK_ULL(h, l) \
 	(((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
@@ -5307,43 +5414,46 @@ unsigned int __kc_eth_get_headlen(unsigned char *data, unsigned int max_len);
 #endif /* 3.18.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,18,4) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 4))
 #else
 #define HAVE_NDO_FEATURES_CHECK
 #endif /* 3.18.4 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,18,13) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 13))
 #ifndef WRITE_ONCE
 #define WRITE_ONCE(x, val) ({ ACCESS_ONCE(x) = (val); })
 #endif
 #endif /* 3.18.13 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,19,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0))
 /* netdev_phys_port_id renamed to netdev_phys_item_id */
 #define netdev_phys_item_id netdev_phys_port_id
 
 static inline void _kc_napi_complete_done(struct napi_struct *napi,
-					  int __always_unused work_done) {
+										int __always_unused work_done)
+{
 	napi_complete(napi);
 }
 /* don't use our backport if the distro kernels already have it */
-#if (SLE_VERSION_CODE && (SLE_VERSION_CODE < SLE_VERSION(12,3,0))) || \
-    (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,5)))
+#if (SLE_VERSION_CODE && (SLE_VERSION_CODE < SLE_VERSION(12, 3, 0))) || \
+		(RHEL_RELEASE_CODE &&                                           \
+		(RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 5)))
 #define napi_complete_done _kc_napi_complete_done
 #endif
 
 int _kc_bitmap_print_to_pagebuf(bool list, char *buf,
-				const unsigned long *maskp, int nmaskbits);
+								const unsigned long *maskp, int nmaskbits);
 #define bitmap_print_to_pagebuf _kc_bitmap_print_to_pagebuf
 
 #ifndef NETDEV_RSS_KEY_LEN
 #define NETDEV_RSS_KEY_LEN (13 * 4)
 #endif
-#if (!(RHEL_RELEASE_CODE && \
-      ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,7) && RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)) || \
-       (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2)))))
+#if (!(RHEL_RELEASE_CODE &&                                 \
+	((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 7) && \
+		RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 0)) || \
+		(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 2)))))
 #define netdev_rss_key_fill(buffer, len) __kc_netdev_rss_key_fill(buffer, len)
 #endif /* RHEL_RELEASE_CODE */
 void __kc_netdev_rss_key_fill(void *buffer, size_t len);
@@ -5356,7 +5466,10 @@ void __kc_netdev_rss_key_fill(void *buffer, size_t len);
 #ifndef NUMA_NO_NODE
 #define NUMA_NO_NODE -1
 #endif
-#define dev_alloc_pages(_order) alloc_pages_node(NUMA_NO_NODE, (GFP_ATOMIC | __GFP_COLD | __GFP_COMP | __GFP_MEMALLOC), (_order))
+#define dev_alloc_pages(_order)                                               \
+	alloc_pages_node(NUMA_NO_NODE,                                            \
+					(GFP_ATOMIC | __GFP_COLD | __GFP_COMP | __GFP_MEMALLOC), \
+					(_order))
 #endif
 #ifndef dev_alloc_page
 #define dev_alloc_page() dev_alloc_pages(0)
@@ -5395,45 +5508,46 @@ static inline int __kc_eth_skb_pad(struct sk_buff *skb)
 
 #ifndef SKB_ALLOC_NAPI
 /* RHEL 7.2 backported napi_alloc_skb and friends */
-static inline struct sk_buff *__kc_napi_alloc_skb(struct napi_struct *napi, unsigned int length)
+static inline struct sk_buff *__kc_napi_alloc_skb(struct napi_struct *napi,
+												unsigned int length)
 {
 	return netdev_alloc_skb_ip_align(napi->dev, length);
 }
-#define napi_alloc_skb(napi,len) __kc_napi_alloc_skb(napi,len)
-#define __napi_alloc_skb(napi,len,mask) __kc_napi_alloc_skb(napi,len)
+#define napi_alloc_skb(napi, len) __kc_napi_alloc_skb(napi, len)
+#define __napi_alloc_skb(napi, len, mask) __kc_napi_alloc_skb(napi, len)
 #endif /* SKB_ALLOC_NAPI */
 #define HAVE_CONFIG_PM_RUNTIME
-#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,7)) && \
-     (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)))
+#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6, 7)) && \
+	(RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 0)))
 #define HAVE_RXFH_HASHFUNC
 #endif /* 6.7 < RHEL < 7.0 */
-#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,1))
+#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7, 1))
 #define HAVE_RXFH_HASHFUNC
 #define NDO_DFLT_BRIDGE_GETLINK_HAS_BRFLAGS
 #endif /* RHEL > 7.1 */
 #ifndef napi_schedule_irqoff
-#define napi_schedule_irqoff	napi_schedule
+#define napi_schedule_irqoff napi_schedule
 #endif
 #ifndef READ_ONCE
 #define READ_ONCE(_x) ACCESS_ONCE(_x)
 #endif
-#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2))
+#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7, 2))
 #define HAVE_NDO_FDB_ADD_VID
 #endif
 #ifndef ETH_MODULE_SFF_8636
-#define ETH_MODULE_SFF_8636		0x3
+#define ETH_MODULE_SFF_8636 0x3
 #endif
 #ifndef ETH_MODULE_SFF_8636_LEN
-#define ETH_MODULE_SFF_8636_LEN		256
+#define ETH_MODULE_SFF_8636_LEN 256
 #endif
 #ifndef ETH_MODULE_SFF_8436
-#define ETH_MODULE_SFF_8436		0x4
+#define ETH_MODULE_SFF_8436 0x4
 #endif
 #ifndef ETH_MODULE_SFF_8436_LEN
-#define ETH_MODULE_SFF_8436_LEN		256
+#define ETH_MODULE_SFF_8436_LEN 256
 #endif
 #ifndef writel_relaxed
-#define writel_relaxed	writel
+#define writel_relaxed writel
 #endif
 #else /* 3.19.0 */
 #define HAVE_NDO_FDB_ADD_VID
@@ -5442,7 +5556,7 @@ static inline struct sk_buff *__kc_napi_alloc_skb(struct napi_struct *napi, unsi
 #endif /* 3.19.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,20,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 20, 0))
 /* vlan_tx_xx functions got renamed to skb_vlan */
 #ifndef skb_vlan_tag_get
 #define skb_vlan_tag_get vlan_tx_tag_get
@@ -5450,10 +5564,10 @@ static inline struct sk_buff *__kc_napi_alloc_skb(struct napi_struct *napi, unsi
 #ifndef skb_vlan_tag_present
 #define skb_vlan_tag_present vlan_tx_tag_present
 #endif
-#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,1))
+#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7, 1))
 #define HAVE_INCLUDE_LINUX_TIMECOUNTER_H
 #endif
-#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2))
+#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7, 2))
 #define HAVE_NDO_BRIDGE_SET_DEL_LINK_FLAGS
 #endif
 #else
@@ -5462,12 +5576,15 @@ static inline struct sk_buff *__kc_napi_alloc_skb(struct napi_struct *napi, unsi
 #endif /* 3.20.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))
 /* Definition for CONFIG_OF was introduced earlier */
 #if !defined(CONFIG_OF) && \
-    !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2))
+		!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7, 2))
 static inline struct device_node *
-pci_device_to_OF_node(const struct pci_dev __always_unused *pdev) { return NULL; }
+pci_device_to_OF_node(const struct pci_dev __always_unused *pdev)
+{
+	return NULL;
+}
 #else /* !CONFIG_OF && RHEL < 7.3 */
 #define HAVE_DDP_PROFILE_UPLOAD_SUPPORT
 #endif /* !CONFIG_OF && RHEL < 7.3 */
@@ -5476,7 +5593,7 @@ pci_device_to_OF_node(const struct pci_dev __always_unused *pdev) { return NULL;
 #endif /* < 4.0 */
 
 /*****************************************************************************/
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,1,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))
 #ifndef NO_PTP_SUPPORT
 #ifdef HAVE_INCLUDE_LINUX_TIMECOUNTER_H
 #include <linux/timecounter.h>
@@ -5496,52 +5613,54 @@ of_find_net_device_by_node(struct device_node __always_unused *np)
 
 #define timecounter_adjtime __kc_timecounter_adjtime
 #endif
-#if ((RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2))) || \
-     (SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,2,0))))
+#if ((RHEL_RELEASE_CODE &&                                  \
+	(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 2))) || \
+	(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12, 2, 0))))
 #define HAVE_NDO_SET_VF_RSS_QUERY_EN
 #endif
-#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2))
+#if RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7, 2))
 #define HAVE_NDO_BRIDGE_GETLINK_NLFLAGS
 #define HAVE_RHEL7_EXTENDED_NDO_SET_TX_MAXRATE
 #define HAVE_NDO_SET_TX_MAXRATE
 #endif
-#if !((RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,8) && RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)) && \
-      (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2)) && \
-      (SLE_VERSION_CODE > SLE_VERSION(12,1,0)))
+#if !((RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6, 8) &&  \
+	RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 0)) && \
+	(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7, 2)) && \
+	(SLE_VERSION_CODE > SLE_VERSION(12, 1, 0)))
 unsigned int _kc_cpumask_local_spread(unsigned int i, int node);
 #define cpumask_local_spread _kc_cpumask_local_spread
 #endif
 #ifdef HAVE_RHASHTABLE
-#define rhashtable_loopup_fast(ht, key, params)		\
-	do {						\
-		(void)params;				\
-		rhashtable_lookup((ht), (key));		\
+#define rhashtable_loopup_fast(ht, key, params) \
+	do {                                        \
+		(void)params;                           \
+		rhashtable_lookup((ht), (key));         \
 	} while (0)
 
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,19,0) )
-#define rhashtable_insert_fast(ht, obj, params)			\
-	do {							\
-		(void)params;					\
-		rhashtable_insert((ht), (obj), GFP_KERNEL);	\
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0))
+#define rhashtable_insert_fast(ht, obj, params)     \
+	do {                                            \
+		(void)params;                               \
+		rhashtable_insert((ht), (obj), GFP_KERNEL); \
 	} while (0)
 
-#define rhashtable_remove_fast(ht, obj, params)			\
-	do {							\
-		(void)params;					\
-		rhashtable_remove((ht), (obj), GFP_KERNEL);	\
+#define rhashtable_remove_fast(ht, obj, params)     \
+	do {                                            \
+		(void)params;                               \
+		rhashtable_remove((ht), (obj), GFP_KERNEL); \
 	} while (0)
 
 #else /* >= 3,19,0 */
-#define rhashtable_insert_fast(ht, obj, params)			\
-	do {							\
-		(void)params;					\
-		rhashtable_insert((ht), (obj));			\
+#define rhashtable_insert_fast(ht, obj, params) \
+	do {                                        \
+		(void)params;                           \
+		rhashtable_insert((ht), (obj));         \
 	} while (0)
 
-#define rhashtable_remove_fast(ht, obj, params)			\
-	do {							\
-		(void)params;					\
-		rhashtable_remove((ht), (obj));			\
+#define rhashtable_remove_fast(ht, obj, params) \
+	do {                                        \
+		(void)params;                           \
+		rhashtable_remove((ht), (obj));         \
 	} while (0)
 
 #endif /* 3,19,0 */
@@ -5556,13 +5675,13 @@ unsigned int _kc_cpumask_local_spread(unsigned int i, int node);
 #endif /* 4,1,0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,1,9))
-#if (!(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2)) && \
-     !((SLE_VERSION_CODE == SLE_VERSION(11,3,0)) && \
-       (SLE_LOCALVERSION_CODE >= SLE_LOCALVERSION(0,47,71))) && \
-     !((SLE_VERSION_CODE == SLE_VERSION(11,4,0)) && \
-       (SLE_LOCALVERSION_CODE >= SLE_LOCALVERSION(65,0,0))) && \
-     !(SLE_VERSION_CODE >= SLE_VERSION(12,1,0)))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 9))
+#if (!(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7, 2)) &&         \
+	!((SLE_VERSION_CODE == SLE_VERSION(11, 3, 0)) &&             \
+	(SLE_LOCALVERSION_CODE >= SLE_LOCALVERSION(0, 47, 71))) && \
+	!((SLE_VERSION_CODE == SLE_VERSION(11, 4, 0)) &&             \
+	(SLE_LOCALVERSION_CODE >= SLE_LOCALVERSION(65, 0, 0))) &&  \
+	!(SLE_VERSION_CODE >= SLE_VERSION(12, 1, 0)))
 static inline bool page_is_pfmemalloc(struct page __maybe_unused *page)
 {
 #ifdef HAVE_STRUCT_PAGE_PFMEMALLOC
@@ -5571,17 +5690,18 @@ static inline bool page_is_pfmemalloc(struct page __maybe_unused *page)
 	return false;
 #endif
 }
-#endif /* !RHEL7.2+ && !SLES11sp3(3.0.101-0.47.71+ update) && !SLES11sp4(3.0.101-65+ update) & !SLES12sp1+ */
+#endif /* !RHEL7.2+ && !SLES11sp3(3.0.101-0.47.71+ update) &&                  \
+		!SLES11sp4(3.0.101-65+ update) & !SLES12sp1+ */
 #else
 #undef HAVE_STRUCT_PAGE_PFMEMALLOC
 #endif /* 4.1.9 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0))
-#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2)) && \
-     !(SLE_VERSION_CODE >= SLE_VERSION(12,1,0)))
-#define ETHTOOL_RX_FLOW_SPEC_RING	0x00000000FFFFFFFFULL
-#define ETHTOOL_RX_FLOW_SPEC_RING_VF	0x000000FF00000000ULL
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0))
+#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 2)) && \
+	!(SLE_VERSION_CODE >= SLE_VERSION(12, 1, 0)))
+#define ETHTOOL_RX_FLOW_SPEC_RING 0x00000000FFFFFFFFULL
+#define ETHTOOL_RX_FLOW_SPEC_RING_VF 0x000000FF00000000ULL
 #define ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF 32
 static inline __u64 ethtool_get_flow_spec_ring(__u64 ring_cookie)
 {
@@ -5591,22 +5711,22 @@ static inline __u64 ethtool_get_flow_spec_ring(__u64 ring_cookie)
 static inline __u64 ethtool_get_flow_spec_ring_vf(__u64 ring_cookie)
 {
 	return (ETHTOOL_RX_FLOW_SPEC_RING_VF & ring_cookie) >>
-				ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
+		ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
 };
 #endif /* ! RHEL >= 7.2 && ! SLES >= 12.1 */
-#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4))
+#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 4))
 #define HAVE_NDO_DFLT_BRIDGE_GETLINK_VLAN_SUPPORT
 #endif
 
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27))
-#if (!((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,8) && \
-	RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)) || \
-       RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2)))
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 27))
+#if (!((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 8) && \
+		RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 0)) || \
+	RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 2)))
 static inline bool pci_ari_enabled(struct pci_bus *bus)
 {
 	return bus->self && bus->self->ari_enabled;
 }
-#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,2))
+#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 2))
 #define HAVE_VF_STATS
 #endif /* (RHEL7.2+) */
 #endif /* !(RHEL6.8+ || RHEL7.2+) */
@@ -5622,9 +5742,9 @@ static inline bool pci_ari_enabled(struct pci_bus *bus)
 #endif /* 4.2.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,3,0))
-#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4)) && \
-     !(SLE_VERSION_CODE >= SLE_VERSION(12,2,0)))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 3, 0))
+#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 4)) && \
+	!(SLE_VERSION_CODE >= SLE_VERSION(12, 2, 0)))
 /**
  * _kc_flow_dissector_key_ipv4_addrs:
  * @src: source ip address
@@ -5660,9 +5780,9 @@ struct _kc_flow_dissector_key_addrs {
 /**
  * _kc_flow_dissector_key_tp_ports:
  *	@ports: port numbers of Transport header
- *		src: source port number
- *		dst: destination port number
- */
+*		src: source port number
+*		dst: destination port number
+*/
 struct _kc_flow_dissector_key_ports {
 	union {
 		__be32 ports;
@@ -5680,9 +5800,9 @@ struct _kc_flow_dissector_key_ports {
  * @padding: padding for alignment
  */
 struct _kc_flow_dissector_key_basic {
-	__be16	n_proto;
-	u8	ip_proto;
-	u8	padding;
+	__be16 n_proto;
+	u8 ip_proto;
+	u8 padding;
 };
 
 struct _kc_flow_keys {
@@ -5692,35 +5812,34 @@ struct _kc_flow_keys {
 };
 
 /* These are all the include files for kernels inside this #ifdef block that
- * have any reference to the in kernel definition of struct flow_keys. The
- * reason for putting them here is to make 100% sure that these files do not get
- * included after re-defining flow_keys to _kc_flow_keys. This is done to
- * prevent any possible ABI issues that this structure re-definition could case.
- */
-#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0) && \
-      LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)) || \
-      RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,7) || \
-      SLE_VERSION_CODE >= SLE_VERSION(11,4,0))
+* have any reference to the in kernel definition of struct flow_keys. The
+* reason for putting them here is to make 100% sure that these files do not get
+* included after re-defining flow_keys to _kc_flow_keys. This is done to
+* prevent any possible ABI issues that this structure re-definition could case.
+*/
+#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0) &&  \
+	LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0)) ||  \
+	RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 7) || \
+	SLE_VERSION_CODE >= SLE_VERSION(11, 4, 0))
 #include <net/flow_keys.h>
 #endif /* (>= 3.3.0 && < 4.2.0) || >= RHEL 6.7  || >= SLE 11.4 */
-#if (LINUX_VERSION_CODE == KERNEL_VERSION(4,2,0))
+#if (LINUX_VERSION_CODE == KERNEL_VERSION(4, 2, 0))
 #include <net/flow_dissector.h>
 #endif /* 4.2.0 */
 #include <linux/skbuff.h>
+#include <net/flow.h>
 #include <net/ip.h>
 #include <net/ipv6.h>
-#include <net/flow.h>
 
 #define flow_keys _kc_flow_keys
-bool
-_kc_skb_flow_dissect_flow_keys(const struct sk_buff *skb,
-			       struct flow_keys *flow,
-			       unsigned int __always_unused flags);
-#define skb_flow_dissect_flow_keys	_kc_skb_flow_dissect_flow_keys
+bool _kc_skb_flow_dissect_flow_keys(const struct sk_buff *skb,
+									struct flow_keys *flow,
+									unsigned int __always_unused flags);
+#define skb_flow_dissect_flow_keys _kc_skb_flow_dissect_flow_keys
 #endif /* ! >= RHEL 7.4 && ! >= SLES 12.2 */
 
-#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,3)) || \
-     (SLE_VERSION_CODE >= SLE_VERSION(12,2,0)))
+#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 3)) || \
+	(SLE_VERSION_CODE >= SLE_VERSION(12, 2, 0)))
 #include <net/dst_metadata.h>
 #endif /* >= RHEL7.3 || >= SLE12sp2 */
 #else /* >= 4.3.0 */
@@ -5728,15 +5847,15 @@ _kc_skb_flow_dissect_flow_keys(const struct sk_buff *skb,
 #endif /* 4.3.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0))
-#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,3))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
+#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 3))
 #define HAVE_NDO_SET_VF_TRUST
 #endif /* (RHEL_RELEASE >= 7.3) */
 #ifndef CONFIG_64BIT
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0))
-#include <asm-generic/io-64-nonatomic-lo-hi.h>	/* 32-bit readq/writeq */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
+#include <asm-generic/io-64-nonatomic-lo-hi.h> /* 32-bit readq/writeq */
 #else /* 3.3.0 => 4.3.x */
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26))
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26))
 #include <asm-generic/int-ll64.h>
 #endif /* 2.6.26 => 3.3.0 */
 #ifndef readq
@@ -5767,23 +5886,23 @@ static inline void writeq(__u64 val, volatile void __iomem *addr)
 #define HAVE_NDO_SET_VF_TRUST
 
 #ifndef CONFIG_64BIT
-#include <linux/io-64-nonatomic-lo-hi.h>	/* 32-bit readq/writeq */
+#include <linux/io-64-nonatomic-lo-hi.h> /* 32-bit readq/writeq */
 #endif /* !CONFIG_64BIT */
 #endif /* 4.4.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
 /* protect against a likely backport */
 #ifndef NETIF_F_CSUM_MASK
 #define NETIF_F_CSUM_MASK NETIF_F_ALL_CSUM
 #endif /* NETIF_F_CSUM_MASK */
-#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,3)))
+#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 3)))
 #define eth_platform_get_mac_address _kc_eth_platform_get_mac_address
 int _kc_eth_platform_get_mac_address(struct device *dev __maybe_unused,
-				     u8 *mac_addr __maybe_unused);
+									u8 *mac_addr __maybe_unused);
 #endif /* !(RHEL_RELEASE >= 7.3) */
 #else /* 4.5.0 */
-#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,8,0) )
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
 #define HAVE_GENEVE_RX_OFFLOAD
 #if !defined(HAVE_UDP_ENC_TUNNEL) && IS_ENABLED(CONFIG_GENEVE)
 #define HAVE_UDP_ENC_TUNNEL
@@ -5794,11 +5913,11 @@ int _kc_eth_platform_get_mac_address(struct device *dev __maybe_unused,
 #endif /* 4.5.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0))
-#if !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,3))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0))
+#if !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7, 3))
 static inline unsigned char *skb_checksum_start(const struct sk_buff *skb)
 {
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22))
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22))
 	return skb->head + skb->csum_start;
 #else /* < 2.6.22 */
 	return skb_transport_header(skb);
@@ -5806,27 +5925,29 @@ static inline unsigned char *skb_checksum_start(const struct sk_buff *skb)
 }
 #endif
 
-#if !(UBUNTU_VERSION_CODE && \
-		UBUNTU_VERSION_CODE >= UBUNTU_VERSION(4,4,0,21)) && \
-	!(RHEL_RELEASE_CODE && \
-		(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2))) && \
-	!(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,3,0)))
+#if !(UBUNTU_VERSION_CODE &&                                   \
+	UBUNTU_VERSION_CODE >= UBUNTU_VERSION(4, 4, 0, 21)) &&   \
+		!(RHEL_RELEASE_CODE &&                                 \
+		(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7, 2))) && \
+		!(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12, 3, 0)))
 static inline void napi_consume_skb(struct sk_buff *skb,
-				    int __always_unused budget)
+									int __always_unused budget)
 {
 	dev_consume_skb_any(skb);
 }
 
 #endif /* UBUNTU 4,4,0,21, RHEL 7.2, SLES12 SP3 */
-#if !(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,3,0))) && \
-	!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4))
+#if !(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12, 3, 0))) && \
+		!(RHEL_RELEASE_CODE &&                                            \
+		RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 4))
 static inline void csum_replace_by_diff(__sum16 *sum, __wsum diff)
 {
-	* sum = csum_fold(csum_add(diff, ~csum_unfold(*sum)));
+	*sum = csum_fold(csum_add(diff, ~csum_unfold(*sum)));
 }
 #endif
-#if !(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7,2))) && \
-	!(SLE_VERSION_CODE && (SLE_VERSION_CODE > SLE_VERSION(12,3,0)))
+#if !(RHEL_RELEASE_CODE &&                                 \
+	(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(7, 2))) && \
+		!(SLE_VERSION_CODE && (SLE_VERSION_CODE > SLE_VERSION(12, 3, 0)))
 static inline void page_ref_inc(struct page *page)
 {
 	get_page(page);
@@ -5835,20 +5956,20 @@ static inline void page_ref_inc(struct page *page)
 #define HAVE_PAGE_COUNT_BULK_UPDATE
 #endif
 #ifndef IPV4_USER_FLOW
-#define	IPV4_USER_FLOW	0x0d	/* spec only (usr_ip4_spec) */
+#define IPV4_USER_FLOW 0x0d /* spec only (usr_ip4_spec) */
 #endif
 
-#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4))
+#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 4))
 #define HAVE_TC_SETUP_CLSFLOWER
 #define HAVE_TC_FLOWER_ENC
 #endif
 
-#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,7)) || \
-     (SLE_VERSION_CODE >= SLE_VERSION(12,2,0)))
+#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 7)) || \
+	(SLE_VERSION_CODE >= SLE_VERSION(12, 2, 0)))
 #define HAVE_TC_SETUP_CLSU32
 #endif
 
-#if (SLE_VERSION_CODE >= SLE_VERSION(12,2,0))
+#if (SLE_VERSION_CODE >= SLE_VERSION(12, 2, 0))
 #define HAVE_TC_SETUP_CLSFLOWER
 #endif
 
@@ -5861,13 +5982,13 @@ static inline void page_ref_inc(struct page *page)
 #endif /* 4.6.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0))
-#if ((SLE_VERSION_CODE >= SLE_VERSION(12,3,0)) ||\
-     (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4)))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0))
+#if ((SLE_VERSION_CODE >= SLE_VERSION(12, 3, 0)) || \
+	(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 4)))
 #define HAVE_NETIF_TRANS_UPDATE
 #endif /* SLES12sp3+ || RHEL7.4+ */
-#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,3)) ||\
-     (SLE_VERSION_CODE >= SLE_VERSION(12,3,0)))
+#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 3)) || \
+	(SLE_VERSION_CODE >= SLE_VERSION(12, 3, 0)))
 #define HAVE_ETHTOOL_25G_BITS
 #define HAVE_ETHTOOL_50G_BITS
 #define HAVE_ETHTOOL_100G_BITS
@@ -5882,8 +6003,8 @@ static inline void page_ref_inc(struct page *page)
 #endif /* 4.7.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,8,0))
-#if !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+#if !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 4))
 enum udp_parsable_tunnel_type {
 	UDP_TUNNEL_TYPE_VXLAN,
 	UDP_TUNNEL_TYPE_GENEVE,
@@ -5895,16 +6016,17 @@ struct udp_tunnel_info {
 };
 #endif
 
-#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5))
+#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 5))
 #define HAVE_TCF_EXTS_TO_LIST
 #endif
 
-#if (UBUNTU_VERSION_CODE && UBUNTU_VERSION_CODE < UBUNTU_VERSION(4,8,0,0))
+#if (UBUNTU_VERSION_CODE && UBUNTU_VERSION_CODE < UBUNTU_VERSION(4, 8, 0, 0))
 #define tc_no_actions(_exts) true
-#define tc_for_each_action(_a, _exts) while (0)
+#define tc_for_each_action(_a, _exts) (while (0))
 #endif
-#if !(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,3,0))) &&\
-	!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4))
+#if !(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12, 3, 0))) && \
+		!(RHEL_RELEASE_CODE &&                                            \
+		RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 4))
 static inline int
 #ifdef HAVE_NON_CONST_PCI_DRIVER_NAME
 pci_request_io_regions(struct pci_dev *pdev, char *name)
@@ -5912,15 +6034,14 @@ pci_request_io_regions(struct pci_dev *pdev, char *name)
 pci_request_io_regions(struct pci_dev *pdev, const char *name)
 #endif
 {
-	return pci_request_selected_regions(pdev,
-			    pci_select_bars(pdev, IORESOURCE_IO), name);
+	return pci_request_selected_regions(
+			pdev, pci_select_bars(pdev, IORESOURCE_IO), name);
 }
 
-static inline void
-pci_release_io_regions(struct pci_dev *pdev)
+static inline void pci_release_io_regions(struct pci_dev *pdev)
 {
 	return pci_release_selected_regions(pdev,
-			    pci_select_bars(pdev, IORESOURCE_IO));
+										pci_select_bars(pdev, IORESOURCE_IO));
 }
 
 static inline int
@@ -5930,19 +6051,18 @@ pci_request_mem_regions(struct pci_dev *pdev, char *name)
 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
 #endif
 {
-	return pci_request_selected_regions(pdev,
-			    pci_select_bars(pdev, IORESOURCE_MEM), name);
+	return pci_request_selected_regions(
+			pdev, pci_select_bars(pdev, IORESOURCE_MEM), name);
 }
 
-static inline void
-pci_release_mem_regions(struct pci_dev *pdev)
+static inline void pci_release_mem_regions(struct pci_dev *pdev)
 {
 	return pci_release_selected_regions(pdev,
-			    pci_select_bars(pdev, IORESOURCE_MEM));
+										pci_select_bars(pdev, IORESOURCE_MEM));
 }
 #endif /* !SLE_VERSION(12,3,0) */
-#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4)) ||\
-     (SLE_VERSION_CODE >= SLE_VERSION(12,3,0)))
+#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 4)) || \
+	(SLE_VERSION_CODE >= SLE_VERSION(12, 3, 0)))
 #define HAVE_ETHTOOL_NEW_50G_BITS
 #endif /* RHEL7.4+ || SLES12sp3+ */
 #else
@@ -5952,23 +6072,24 @@ pci_release_mem_regions(struct pci_dev *pdev)
 #endif /* 4.8.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0))
 #ifdef HAVE_TC_SETUP_CLSFLOWER
 #if (!(RHEL_RELEASE_CODE) && !(SLE_VERSION_CODE) || \
-    (SLE_VERSION_CODE && (SLE_VERSION_CODE < SLE_VERSION(12,3,0))))
+	(SLE_VERSION_CODE && (SLE_VERSION_CODE < SLE_VERSION(12, 3, 0))))
 #define HAVE_TC_FLOWER_VLAN_IN_TAGS
 #endif /* !RHEL_RELEASE_CODE && !SLE_VERSION_CODE || <SLE_VERSION(12,3,0) */
 #endif /* HAVE_TC_SETUP_CLSFLOWER */
-#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4))
+#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 4))
 #define HAVE_ETHTOOL_NEW_1G_BITS
 #define HAVE_ETHTOOL_NEW_10G_BITS
 #endif /* RHEL7.4+ */
-#if (!(SLE_VERSION_CODE) && !(RHEL_RELEASE_CODE)) || \
-     SLE_VERSION_CODE && (SLE_VERSION_CODE <= SLE_VERSION(12,3,0)) || \
-     RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE <= RHEL_RELEASE_VERSION(7,5))
-#define time_is_before_jiffies64(a)	time_after64(get_jiffies_64(), a)
-#endif /* !SLE_VERSION_CODE && !RHEL_RELEASE_CODE || (SLES <= 12.3.0) || (RHEL <= 7.5) */
-#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,4))
+#if (!(SLE_VERSION_CODE) && !(RHEL_RELEASE_CODE)) ||                       \
+		SLE_VERSION_CODE && (SLE_VERSION_CODE <= SLE_VERSION(12, 3, 0)) || \
+		RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE <= RHEL_RELEASE_VERSION(7, 5))
+#define time_is_before_jiffies64(a) time_after64(get_jiffies_64(), a)
+#endif /* !SLE_VERSION_CODE && !RHEL_RELEASE_CODE || (SLES <= 12.3.0) || (RHEL \
+		<= 7.5) */
+#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 4))
 static inline void bitmap_from_u64(unsigned long *dst, u64 mask)
 {
 	dst[0] = mask & ULONG_MAX;
@@ -5977,9 +6098,9 @@ static inline void bitmap_from_u64(unsigned long *dst, u64 mask)
 		dst[1] = mask >> 32;
 }
 #endif /* <RHEL7.4 */
-#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4)) && \
-     !(SLE_VERSION_CODE >= SLE_VERSION(12,3,0)) && \
-     !(UBUNTU_VERSION_CODE >= UBUNTU_VERSION(4,13,0,16)))
+#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 4)) && \
+	!(SLE_VERSION_CODE >= SLE_VERSION(12, 3, 0)) &&       \
+	!(UBUNTU_VERSION_CODE >= UBUNTU_VERSION(4, 13, 0, 16)))
 static inline bool eth_type_vlan(__be16 ethertype)
 {
 	switch (ethertype) {
@@ -6000,23 +6121,24 @@ static inline bool eth_type_vlan(__be16 ethertype)
 #endif /* KERNEL_VERSION(4.9.0) */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,10,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0))
 /* SLES 12.3 and RHEL 7.5 backported this interface */
-#if (!SLE_VERSION_CODE && !RHEL_RELEASE_CODE) || \
-    (SLE_VERSION_CODE && (SLE_VERSION_CODE < SLE_VERSION(12,3,0))) || \
-    (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,5)))
+#if (!SLE_VERSION_CODE && !RHEL_RELEASE_CODE) ||                            \
+		(SLE_VERSION_CODE && (SLE_VERSION_CODE < SLE_VERSION(12, 3, 0))) || \
+		(RHEL_RELEASE_CODE &&                                               \
+		(RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 5)))
 static inline bool _kc_napi_complete_done2(struct napi_struct *napi,
-					   int __always_unused work_done)
+										int __always_unused work_done)
 {
 	/* it was really hard to get napi_complete_done to be safe to call
-	 * recursively without running into our own kcompat, so just use
-	 * napi_complete
-	 */
+* recursively without running into our own kcompat, so just use
+* napi_complete
+*/
 	napi_complete(napi);
 
 	/* true means that the stack is telling the driver to go-ahead and
-	 * re-enable interrupts
-	 */
+* re-enable interrupts
+*/
 	return true;
 }
 
@@ -6025,31 +6147,31 @@ static inline bool _kc_napi_complete_done2(struct napi_struct *napi,
 #endif
 #define napi_complete_done _kc_napi_complete_done2
 #endif /* sles and rhel exclusion for < 4.10 */
-#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,4))
+#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 4))
 #define HAVE_DEV_WALK_API
 #define HAVE_ETHTOOL_NEW_2500MB_BITS
 #define HAVE_ETHTOOL_5G_BITS
 #endif /* RHEL7.4+ */
-#if (SLE_VERSION_CODE && (SLE_VERSION_CODE == SLE_VERSION(12,3,0)))
+#if (SLE_VERSION_CODE && (SLE_VERSION_CODE == SLE_VERSION(12, 3, 0)))
 #define HAVE_STRUCT_DMA_ATTRS
 #endif /* (SLES == 12.3.0) */
-#if (SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,3,0)))
+#if (SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12, 3, 0)))
 #define HAVE_NETDEVICE_MIN_MAX_MTU
 #endif /* (SLES >= 12.3.0) */
-#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5)))
+#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 5)))
 #define HAVE_STRUCT_DMA_ATTRS
 #define HAVE_RHEL7_EXTENDED_MIN_MAX_MTU
 #define HAVE_NETDEVICE_MIN_MAX_MTU
 #endif
-#if (!(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,3,0))) && \
-     !(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5))))
+#if (!(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12, 3, 0))) && \
+	!(RHEL_RELEASE_CODE &&                                                \
+	(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 5))))
 #ifndef dma_map_page_attrs
 #define dma_map_page_attrs __kc_dma_map_page_attrs
-static inline dma_addr_t __kc_dma_map_page_attrs(struct device *dev,
-						 struct page *page,
-						 size_t offset, size_t size,
-						 enum dma_data_direction dir,
-						 unsigned long __always_unused attrs)
+static inline dma_addr_t
+__kc_dma_map_page_attrs(struct device *dev, struct page *page, size_t offset,
+						size_t size, enum dma_data_direction dir,
+						unsigned long __always_unused attrs)
 {
 	return dma_map_page(dev, page, offset, size, dir);
 }
@@ -6057,17 +6179,17 @@ static inline dma_addr_t __kc_dma_map_page_attrs(struct device *dev,
 
 #ifndef dma_unmap_page_attrs
 #define dma_unmap_page_attrs __kc_dma_unmap_page_attrs
-static inline void __kc_dma_unmap_page_attrs(struct device *dev,
-					     dma_addr_t addr, size_t size,
-					     enum dma_data_direction dir,
-					     unsigned long __always_unused attrs)
+static inline void
+__kc_dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
+						enum dma_data_direction dir,
+						unsigned long __always_unused attrs)
 {
 	dma_unmap_page(dev, addr, size, dir);
 }
 #endif
 
 static inline void __page_frag_cache_drain(struct page *page,
-					   unsigned int count)
+										unsigned int count)
 {
 #ifdef HAVE_PAGE_COUNT_BULK_UPDATE
 	if (!page_ref_sub_and_test(page, count))
@@ -6082,13 +6204,13 @@ static inline void __page_frag_cache_drain(struct page *page,
 	__free_pages(page, compound_order(page));
 }
 #endif /* !SLE_VERSION(12,3,0) && !RHEL_VERSION(7,5) */
-#if ((SLE_VERSION_CODE && (SLE_VERSION_CODE > SLE_VERSION(12,3,0))) ||\
-     (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5)))
+#if ((SLE_VERSION_CODE && (SLE_VERSION_CODE > SLE_VERSION(12, 3, 0))) || \
+	(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 5)))
 #define HAVE_SWIOTLB_SKIP_CPU_SYNC
 #endif
 
-#if ((SLE_VERSION_CODE && (SLE_VERSION_CODE < SLE_VERSION(15,0,0))) ||\
-     (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE <= RHEL_RELEASE_VERSION(7,4))))
+#if ((SLE_VERSION_CODE && (SLE_VERSION_CODE < SLE_VERSION(15, 0, 0))) || \
+	(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE <= RHEL_RELEASE_VERSION(7, 4))))
 #define page_frag_free __free_page_frag
 #endif
 #ifndef ETH_MIN_MTU
@@ -6104,20 +6226,20 @@ static inline void __page_frag_cache_drain(struct page *page,
 #define HAVE_ETHTOOL_NEW_2500MB_BITS
 #define HAVE_ETHTOOL_5G_BITS
 /* kernel 4.10 onwards, as part of busy_poll rewrite, new state were added
- * which is part of NAPI:state. If NAPI:state=NAPI_STATE_IN_BUSY_POLL,
- * it means napi_poll is invoked in busy_poll context
- */
+* which is part of NAPI:state. If NAPI:state=NAPI_STATE_IN_BUSY_POLL,
+* it means napi_poll is invoked in busy_poll context
+*/
 #define HAVE_NAPI_STATE_IN_BUSY_POLL
 #define HAVE_TCF_MIRRED_EGRESS_REDIRECT
 #endif /* 4.10.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,11,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0))
 #ifdef CONFIG_NET_RX_BUSY_POLL
 #define HAVE_NDO_BUSY_POLL
 #endif /* CONFIG_NET_RX_BUSY_POLL */
-#if ((SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,3,0))) || \
-     (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5))))
+#if ((SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12, 3, 0))) || \
+	(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 5))))
 #define HAVE_VOID_NDO_GET_STATS64
 #endif /* (SLES >= 12.3.0) && (RHEL >= 7.5) */
 
@@ -6167,43 +6289,41 @@ static inline void _kc_dev_consume_skb_any(struct sk_buff *skb)
 #endif /* 4.11.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,12,0))
-#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,7) && \
-     RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
+#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 7) && \
+	RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8, 0))
 /* The RHEL 7.7+ NL_SET_ERR_MSG_MOD triggers unused parameter warnings */
 #undef NL_SET_ERR_MSG_MOD
 #endif
 #ifndef NL_SET_ERR_MSG_MOD
-#define NL_SET_ERR_MSG_MOD(extack, msg)						\
-	do {									\
-		uninitialized_var(extack);					\
-		pr_err(KBUILD_MODNAME ": " msg);				\
+#define NL_SET_ERR_MSG_MOD(extack, msg)  \
+	do {                                 \
+		uninitialized_var(extack);       \
+		pr_err(KBUILD_MODNAME ": " msg); \
 	} while (0)
 #endif /* !NL_SET_ERR_MSG_MOD */
 #endif /* 4.12 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,13,0))
-#if ((SLE_VERSION_CODE && (SLE_VERSION_CODE > SLE_VERSION(12,3,0))) || \
-     (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5)))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0))
+#if ((SLE_VERSION_CODE && (SLE_VERSION_CODE > SLE_VERSION(12, 3, 0))) || \
+	(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 5)))
 #define HAVE_TCF_EXTS_HAS_ACTION
 #endif
-#define  PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
-#if (SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,4,0)))
+#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
+#if (SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12, 4, 0)))
 #define HAVE_PCI_ERROR_HANDLER_RESET_PREPARE
 #endif /* SLES >= 12sp4 */
-#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5)) && \
-     !(SLE_VERSION_CODE >= SLE_VERSION(12,4,0)))
+#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 5)) && \
+	!(SLE_VERSION_CODE >= SLE_VERSION(12, 4, 0)))
 #define UUID_SIZE 16
 typedef struct {
 	__u8 b[UUID_SIZE];
 } uuid_t;
-#define UUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7)		\
-((uuid_t)								\
-{{ ((a) >> 24) & 0xff, ((a) >> 16) & 0xff, ((a) >> 8) & 0xff, (a) & 0xff, \
-   ((b) >> 8) & 0xff, (b) & 0xff,					\
-   ((c) >> 8) & 0xff, (c) & 0xff,					\
-   (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
+#define UUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7)                  \
+	((uuid_t){ { ((a) >> 24) & 0xff, ((a) >> 16) & 0xff, ((a) >> 8) & 0xff, \
+				(a)&0xff, ((b) >> 8) & 0xff, (b)&0xff, ((c) >> 8) & 0xff,  \
+				(c)&0xff, (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } })
 
 static inline bool uuid_equal(const uuid_t *u1, const uuid_t *u2)
 {
@@ -6221,34 +6341,36 @@ static inline bool uuid_equal(const uuid_t *u1, const uuid_t *u2)
 #endif /* 4.13.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0))
 #ifdef ETHTOOL_GLINKSETTINGS
 #ifndef ethtool_link_ksettings_del_link_mode
-#define ethtool_link_ksettings_del_link_mode(ptr, name, mode)		\
-	__clear_bit(ETHTOOL_LINK_MODE_ ## mode ## _BIT, (ptr)->link_modes.name)
+#define ethtool_link_ksettings_del_link_mode(ptr, name, mode) \
+	__clear_bit(ETHTOOL_LINK_MODE_##mode##_BIT, (ptr)->link_modes.name)
 #endif
 #endif /* ETHTOOL_GLINKSETTINGS */
-#if (SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12,4,0)))
+#if (SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(12, 4, 0)))
 #define HAVE_NDO_SETUP_TC_REMOVE_TC_TO_NETDEV
 #endif
 
-#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,5)))
+#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 5)))
 #define HAVE_NDO_SETUP_TC_REMOVE_TC_TO_NETDEV
 #define HAVE_RHEL7_NETDEV_OPS_EXT_NDO_SETUP_TC
 #endif
 
-#define TIMER_DATA_TYPE		unsigned long
-#define TIMER_FUNC_TYPE		void (*)(TIMER_DATA_TYPE)
+#define TIMER_DATA_TYPE unsigned long
+#define TIMER_FUNC_TYPE void (*)(TIMER_DATA_TYPE)
 
-#define timer_setup(timer, callback, flags)				\
-	__setup_timer((timer), (TIMER_FUNC_TYPE)(callback),		\
-		      (TIMER_DATA_TYPE)(timer), (flags))
+#define timer_setup(timer, callback, flags)             \
+	__setup_timer((timer), (TIMER_FUNC_TYPE)(callback), \
+				(TIMER_DATA_TYPE)(timer), (flags))
 
 #define from_timer(var, callback_timer, timer_fieldname) \
 	container_of(callback_timer, typeof(*var), timer_fieldname)
 
 #ifndef xdp_do_flush_map
-#define xdp_do_flush_map() do {} while (0)
+#define xdp_do_flush_map() \
+	do {                   \
+	} while (0)
 #endif
 struct _kc_xdp_buff {
 	void *data;
@@ -6260,8 +6382,12 @@ struct _kc_bpf_prog {
 };
 #define bpf_prog _kc_bpf_prog
 #ifndef DIV_ROUND_DOWN_ULL
-#define DIV_ROUND_DOWN_ULL(ll, d) \
-	({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
+#define DIV_ROUND_DOWN_ULL(ll, d)       \
+	({                                  \
+		unsigned long long _tmp = (ll); \
+		do_div(_tmp, d);                \
+		_tmp;                           \
+	})
 #endif /* DIV_ROUND_DOWN_ULL */
 #else /* > 4.14 */
 #define HAVE_XDP_SUPPORT
@@ -6306,9 +6432,9 @@ struct ethtool_link_ksettings {
 	} link_modes;
 };
 
-#define ETHTOOL_LINK_NAME_advertising(mode) ADVERTISED_ ## mode
-#define ETHTOOL_LINK_NAME_supported(mode) SUPPORTED_ ## mode
-#define ETHTOOL_LINK_NAME(name) ETHTOOL_LINK_NAME_ ## name
+#define ETHTOOL_LINK_NAME_advertising(mode) ADVERTISED_##mode
+#define ETHTOOL_LINK_NAME_supported(mode) SUPPORTED_##mode
+#define ETHTOOL_LINK_NAME(name) ETHTOOL_LINK_NAME_##name
 #define ETHTOOL_LINK_CONVERT(name, mode) ETHTOOL_LINK_NAME(name)(mode)
 
 /**
@@ -6316,7 +6442,7 @@ struct ethtool_link_ksettings {
  * @ptr: ptr to ksettings struct
  * @name: supported or advertising
  */
-#define ethtool_link_ksettings_zero_link_mode(ptr, name)\
+#define ethtool_link_ksettings_zero_link_mode(ptr, name) \
 	(*((ptr)->link_modes.name) = 0x0)
 
 /**
@@ -6325,8 +6451,9 @@ struct ethtool_link_ksettings {
  * @name: supported or advertising
  * @mode: link mode to add
  */
-#define ethtool_link_ksettings_add_link_mode(ptr, name, mode)\
-	(*((ptr)->link_modes.name) |= (typeof(*((ptr)->link_modes.name)))ETHTOOL_LINK_CONVERT(name, mode))
+#define ethtool_link_ksettings_add_link_mode(ptr, name, mode) \
+	(*((ptr)->link_modes.name) |=                             \
+	(typeof(*((ptr)->link_modes.name)))ETHTOOL_LINK_CONVERT(name, mode))
 
 /**
  * ethtool_link_ksettings_del_link_mode
@@ -6334,8 +6461,9 @@ struct ethtool_link_ksettings {
  * @name: supported or advertising
  * @mode: link mode to delete
  */
-#define ethtool_link_ksettings_del_link_mode(ptr, name, mode)\
-	(*((ptr)->link_modes.name) &= ~(typeof(*((ptr)->link_modes.name)))ETHTOOL_LINK_CONVERT(name, mode))
+#define ethtool_link_ksettings_del_link_mode(ptr, name, mode) \
+	(*((ptr)->link_modes.name) &=                             \
+	~(typeof(*((ptr)->link_modes.name)))ETHTOOL_LINK_CONVERT(name, mode))
 
 /**
  * ethtool_link_ksettings_test_link_mode
@@ -6343,7 +6471,7 @@ struct ethtool_link_ksettings {
  * @name: supported or advertising
  * @mode: link mode to add
  */
-#define ethtool_link_ksettings_test_link_mode(ptr, name, mode)\
+#define ethtool_link_ksettings_test_link_mode(ptr, name, mode) \
 	(!!(*((ptr)->link_modes.name) & ETHTOOL_LINK_CONVERT(name, mode)))
 
 /**
@@ -6359,7 +6487,7 @@ struct ethtool_link_ksettings {
  */
 static inline void
 _kc_ethtool_ksettings_to_cmd(struct ethtool_link_ksettings *ks,
-			     struct ethtool_cmd *cmd)
+							struct ethtool_cmd *cmd)
 {
 	cmd->supported = (u32)ks->link_modes.supported[0];
 	cmd->advertising = (u32)ks->link_modes.advertising[0];
@@ -6372,9 +6500,9 @@ _kc_ethtool_ksettings_to_cmd(struct ethtool_link_ksettings *ks,
 #endif /* !ETHTOOL_GLINKSETTINGS */
 
 /*****************************************************************************/
-#if ((LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0)) || \
-     (SLE_VERSION_CODE && (SLE_VERSION_CODE <= SLE_VERSION(12,3,0))) || \
-     (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE <= RHEL_RELEASE_VERSION(7,5))))
+#if ((LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)) ||                   \
+	(SLE_VERSION_CODE && (SLE_VERSION_CODE <= SLE_VERSION(12, 3, 0))) || \
+	(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE <= RHEL_RELEASE_VERSION(7, 5))))
 #define phy_speed_to_str _kc_phy_speed_to_str
 const char *_kc_phy_speed_to_str(int speed);
 #else /* (LINUX >= 4.14.0) || (SLES > 12.3.0) || (RHEL > 7.5) */
@@ -6382,16 +6510,17 @@ const char *_kc_phy_speed_to_str(int speed);
 #endif /* (LINUX < 4.14.0) || (SLES <= 12.3.0) || (RHEL <= 7.5) */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0))
-#if ((RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,6))) || \
-     (SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(15,1,0))))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0))
+#if ((RHEL_RELEASE_CODE &&                                  \
+	(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 6))) || \
+	(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(15, 1, 0))))
 #define HAVE_TC_CB_AND_SETUP_QDISC_MQPRIO
 #define HAVE_TCF_BLOCK
 #else /* RHEL >= 7.6 || SLES >= 15.1 */
 #define TC_SETUP_QDISC_MQPRIO TC_SETUP_MQPRIO
 #endif /* !(RHEL >= 7.6) && !(SLES >= 15.1) */
 void _kc_ethtool_intersect_link_masks(struct ethtool_link_ksettings *dst,
-				      struct ethtool_link_ksettings *src);
+									struct ethtool_link_ksettings *src);
 #define ethtool_intersect_link_masks _kc_ethtool_intersect_link_masks
 #else /* >= 4.15 */
 #define HAVE_NDO_BPF
@@ -6401,69 +6530,67 @@ void _kc_ethtool_intersect_link_masks(struct ethtool_link_ksettings *dst,
 #endif /* 4.15.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,16,0))
-#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,7)) && \
-     !(SLE_VERSION_CODE >= SLE_VERSION(12,4,0) && \
-       SLE_VERSION_CODE < SLE_VERSION(15,0,0)) && \
-     !(SLE_VERSION_CODE >= SLE_VERSION(15,1,0)))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0))
+#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 7)) && \
+	!(SLE_VERSION_CODE >= SLE_VERSION(12, 4, 0) &&        \
+	SLE_VERSION_CODE < SLE_VERSION(15, 0, 0)) &&        \
+	!(SLE_VERSION_CODE >= SLE_VERSION(15, 1, 0)))
 /* The return value of the strscpy() and strlcpy() functions is different.
- * This could be potentially hazard for the future.
- * To avoid this the void result is forced.
- * So it is not possible use this function with the return value.
- * Return value is required in kernel 4.3 through 4.15
- */
-#define strscpy(...) (void)(strlcpy(__VA_ARGS__))
+* This could be potentially hazard for the future.
+* To avoid this the void result is forced.
+* So it is not possible use this function with the return value.
+* Return value is required in kernel 4.3 through 4.15
+*/
+#define strscpy(...) ((void)(strlcpy(__VA_ARGS__)))
 #endif /* !RHEL >= 7.7 && !SLES12sp4+ && !SLES15sp1+ */
 
 #define pci_printk(level, pdev, fmt, arg...) \
 	dev_printk(level, &(pdev)->dev, fmt, ##arg)
-#define pci_emerg(pdev, fmt, arg...)	dev_emerg(&(pdev)->dev, fmt, ##arg)
-#define pci_alert(pdev, fmt, arg...)	dev_alert(&(pdev)->dev, fmt, ##arg)
-#define pci_crit(pdev, fmt, arg...)	dev_crit(&(pdev)->dev, fmt, ##arg)
-#define pci_err(pdev, fmt, arg...)	dev_err(&(pdev)->dev, fmt, ##arg)
-#define pci_warn(pdev, fmt, arg...)	dev_warn(&(pdev)->dev, fmt, ##arg)
-#define pci_notice(pdev, fmt, arg...)	dev_notice(&(pdev)->dev, fmt, ##arg)
-#define pci_info(pdev, fmt, arg...)	dev_info(&(pdev)->dev, fmt, ##arg)
-#define pci_dbg(pdev, fmt, arg...)	dev_dbg(&(pdev)->dev, fmt, ##arg)
+#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
+#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
+#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
+#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
+#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
+#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
+#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
+#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
 
 #ifndef array_index_nospec
 static inline unsigned long _kc_array_index_mask_nospec(unsigned long index,
-							unsigned long size)
+														unsigned long size)
 {
 	/*
-	 * Always calculate and emit the mask even if the compiler
-	 * thinks the mask is not needed. The compiler does not take
-	 * into account the value of @index under speculation.
-	 */
+* Always calculate and emit the mask even if the compiler
+* thinks the mask is not needed. The compiler does not take
+* into account the value of @index under speculation.
+*/
 	OPTIMIZER_HIDE_VAR(index);
 	return ~(long)(index | (size - 1UL - index)) >> (BITS_PER_LONG - 1);
 }
 
-#define array_index_nospec(index, size)					\
-({									\
-	typeof(index) _i = (index);					\
-	typeof(size) _s = (size);					\
-	unsigned long _mask = _kc_array_index_mask_nospec(_i, _s);	\
-									\
-	BUILD_BUG_ON(sizeof(_i) > sizeof(long));			\
-	BUILD_BUG_ON(sizeof(_s) > sizeof(long));			\
-									\
-	(typeof(_i)) (_i & _mask);					\
-})
+#define array_index_nospec(index, size)                            \
+	({                                                             \
+		typeof(index) _i = (index);                                \
+		typeof(size) _s = (size);                                  \
+		unsigned long _mask = _kc_array_index_mask_nospec(_i, _s); \
+		BUILD_BUG_ON(sizeof(_i) > sizeof(long));                   \
+		BUILD_BUG_ON(sizeof(_s) > sizeof(long));                   \
+		(typeof(_i))(_i & _mask);                                  \
+	})
 #endif /* array_index_nospec */
-#if (!(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,6))) && \
-     !(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(15,1,0))))
+#if (!(RHEL_RELEASE_CODE &&                                  \
+	(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 6))) && \
+	!(SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(15, 1, 0))))
 #ifdef HAVE_TC_CB_AND_SETUP_QDISC_MQPRIO
 #include <net/pkt_cls.h>
 static inline bool
 tc_cls_can_offload_and_chain0(const struct net_device *dev,
-			      struct tc_cls_common_offload *common)
+							struct tc_cls_common_offload *common)
 {
 	if (!tc_can_offload(dev))
 		return false;
 	if (common->chain_index)
 		return false;
-
 	return true;
 }
 #endif /* HAVE_TC_CB_AND_SETUP_QDISC_MQPRIO */
@@ -6471,15 +6598,16 @@ tc_cls_can_offload_and_chain0(const struct net_device *dev,
 #ifndef sizeof_field
 #define sizeof_field(TYPE, MEMBER) (sizeof((((TYPE *)0)->MEMBER)))
 #endif /* sizeof_field */
-#if !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,0)) && \
-     !(SLE_VERSION_CODE >= SLE_VERSION(12,5,0) && \
-       SLE_VERSION_CODE < SLE_VERSION(15,0,0) || \
-       SLE_VERSION_CODE >= SLE_VERSION(15,1,0))
+#if !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 0)) &&     \
+		!(SLE_VERSION_CODE >= SLE_VERSION(12, 5, 0) &&        \
+				SLE_VERSION_CODE < SLE_VERSION(15, 0, 0) || \
+		SLE_VERSION_CODE >= SLE_VERSION(15, 1, 0))
 /*
- * Copy bitmap and clear tail bits in last word.
- */
-static inline void
-bitmap_copy_clear_tail(unsigned long *dst, const unsigned long *src, unsigned int nbits)
+* Copy bitmap and clear tail bits in last word.
+*/
+static inline void bitmap_copy_clear_tail(unsigned long *dst,
+										const unsigned long *src,
+										unsigned int nbits)
 {
 	bitmap_copy(dst, src, nbits);
 	if (nbits % BITS_PER_LONG)
@@ -6487,15 +6615,16 @@ bitmap_copy_clear_tail(unsigned long *dst, const unsigned long *src, unsigned in
 }
 
 /*
- * On 32-bit systems bitmaps are represented as u32 arrays internally, and
- * therefore conversion is not needed when copying data from/to arrays of u32.
- */
+* On 32-bit systems bitmaps are represented as u32 arrays internally, and
+* therefore conversion is not needed when copying data from/to arrays of u32.
+*/
 #if BITS_PER_LONG == 64
-void bitmap_from_arr32(unsigned long *bitmap, const u32 *buf, unsigned int nbits);
+void bitmap_from_arr32(unsigned long *bitmap, const u32 *buf,
+					unsigned int nbits);
 #else
-#define bitmap_from_arr32(bitmap, buf, nbits)			\
-	bitmap_copy_clear_tail((unsigned long *) (bitmap),	\
-			       (const unsigned long *) (buf), (nbits))
+#define bitmap_from_arr32(bitmap, buf, nbits)         \
+	bitmap_copy_clear_tail((unsigned long *)(bitmap), \
+						(const unsigned long *)(buf), (nbits))
 #endif /* BITS_PER_LONG == 64 */
 #endif /* !(RHEL >= 8.0) && !(SLES >= 12.5 && SLES < 15.0 || SLES >= 15.1) */
 #else /* >= 4.16 */
@@ -6507,9 +6636,9 @@ void bitmap_from_arr32(unsigned long *bitmap, const u32 *buf, unsigned int nbits
 #endif /* 4.16.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,17,0))
-#include <linux/pci_regs.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0))
 #include <linux/pci.h>
+#include <linux/pci_regs.h>
 #define PCIE_SPEED_16_0GT 0x17
 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
 #define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */
@@ -6522,11 +6651,11 @@ void _kc_pcie_print_link_status(struct pci_dev *dev);
 
 /*****************************************************************************/
 #if IS_ENABLED(CONFIG_NET_DEVLINK) && \
-    (LINUX_VERSION_CODE < KERNEL_VERSION(5,9,0))
+		(LINUX_VERSION_CODE < KERNEL_VERSION(5, 9, 0))
 #include <net/devlink.h>
-#if ((LINUX_VERSION_CODE < KERNEL_VERSION(4,18,0)) && \
-     (SLE_VERSION_CODE < SLE_VERSION(15,1,0)) && \
-     (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,7)))
+#if ((LINUX_VERSION_CODE < KERNEL_VERSION(4, 18, 0)) && \
+	(SLE_VERSION_CODE < SLE_VERSION(15, 1, 0)) &&      \
+	(RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 7)))
 enum devlink_port_flavour {
 	DEVLINK_PORT_FLAVOUR_PHYSICAL,
 	DEVLINK_PORT_FLAVOUR_CPU,
@@ -6536,15 +6665,17 @@ enum devlink_port_flavour {
 };
 #endif /* <4.18.0 && <SLES15sp1 && <RHEL7.7 */
 
-#if ((LINUX_VERSION_CODE < KERNEL_VERSION(5,3,0)) && \
-     (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8,2)))
+#if ((LINUX_VERSION_CODE < KERNEL_VERSION(5, 3, 0)) && \
+	(RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8, 2)))
 struct devlink_port_phys_attrs {
-	u32 port_number; /* Same value as "split group".
-			  * A physical port which is visible to the user
-			  * for a given port flavour.
-			  */
-	u32 split_subport_number; /* If the port is split, this is the number
-				   * of subport. */
+	/* Same value as "split group".
+	* A physical port which is visible to the user
+	* for a given port flavour.
+	*/
+	u32 port_number;
+	/* If the port is split, this is the number
+	* of subport. */
+	u32 split_subport_number;
 };
 
 struct devlink_port_pci_pf_attrs {
@@ -6558,8 +6689,7 @@ struct devlink_port_pci_vf_attrs {
 #endif /* <5.3.0 && <RHEL8.2*/
 
 struct _kc_devlink_port_attrs {
-	u8 split:1,
-	   splittable:1;
+	u8 split : 1, splittable : 1;
 	u32 lanes;
 	enum devlink_port_flavour flavour;
 	struct netdev_phys_item_id switch_id;
@@ -6573,7 +6703,7 @@ struct _kc_devlink_port_attrs {
 #endif /* CONFIG_NET_DEVLINK && <5.9.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,18,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 18, 0))
 #ifdef NETIF_F_HW_L2FW_DOFFLOAD
 #include <linux/if_macvlan.h>
 #ifndef macvlan_supports_dest_filter
@@ -6583,12 +6713,12 @@ static inline bool _kc_macvlan_supports_dest_filter(struct net_device *dev)
 	struct macvlan_dev *macvlan = netdev_priv(dev);
 
 	return macvlan->mode == MACVLAN_MODE_PRIVATE ||
-	       macvlan->mode == MACVLAN_MODE_VEPA ||
-	       macvlan->mode == MACVLAN_MODE_BRIDGE;
+		macvlan->mode == MACVLAN_MODE_VEPA ||
+		macvlan->mode == MACVLAN_MODE_BRIDGE;
 }
 #endif
 
-#if (!SLE_VERSION_CODE || (SLE_VERSION_CODE < SLE_VERSION(15,1,0)))
+#if (!SLE_VERSION_CODE || (SLE_VERSION_CODE < SLE_VERSION(15, 1, 0)))
 #ifndef macvlan_accel_priv
 #define macvlan_accel_priv _kc_macvlan_accel_priv
 static inline void *_kc_macvlan_accel_priv(struct net_device *dev)
@@ -6613,14 +6743,14 @@ static inline int _kc_macvlan_release_l2fw_offload(struct net_device *dev)
 #endif /* NETIF_F_HW_L2FW_DOFFLOAD */
 #include "kcompat_overflow.h"
 
-#if (SLE_VERSION_CODE < SLE_VERSION(15,1,0))
-#define firmware_request_nowarn	request_firmware_direct
+#if (SLE_VERSION_CODE < SLE_VERSION(15, 1, 0))
+#define firmware_request_nowarn request_firmware_direct
 
-#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,7))
+#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7, 7))
 #if IS_ENABLED(CONFIG_NET_DEVLINK) && !defined(devlink_port_attrs_set)
 static inline void
 _kc_devlink_port_attrs_set(struct devlink_port *devlink_port,
-			   struct _kc_devlink_port_attrs *attrs)
+						struct _kc_devlink_port_attrs *attrs)
 {
 	if (attrs->split)
 		devlink_port_split_set(devlink_port, attrs->phys.port_number);
@@ -6642,9 +6772,9 @@ _kc_devlink_port_attrs_set(struct devlink_port *devlink_port,
 #endif /* 4.18.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,19,0))
-#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,0)) && \
-    (RHEL_RELEASE_CODE <= RHEL_RELEASE_VERSION(8,2)))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0))
+#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 0)) && \
+	(RHEL_RELEASE_CODE <= RHEL_RELEASE_VERSION(8, 2)))
 #define HAVE_DEVLINK_REGIONS
 #endif /* RHEL >= 8.0 && RHEL <= 8.2 */
 #define bitmap_alloc(nbits, flags) \
@@ -6663,13 +6793,13 @@ _kc_devlink_port_attrs_set(struct devlink_port *devlink_port,
 #endif /* ETHTOOL_GLINKSETTINGS */
 #define HAVE_NETPOLL_CONTROLLER
 #define REQUIRE_PCI_CLEANUP_AER_ERROR_STATUS
-#if (SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(15,1,0)))
+#if (SLE_VERSION_CODE && (SLE_VERSION_CODE >= SLE_VERSION(15, 1, 0)))
 #define HAVE_TCF_MIRRED_DEV
 #define HAVE_NDO_SELECT_QUEUE_SB_DEV
 #define HAVE_TCF_BLOCK_CB_REGISTER_EXTACK
 #endif
-#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,0)) ||\
-     (SLE_VERSION_CODE >= SLE_VERSION(15,1,0)))
+#if ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 0)) || \
+	(SLE_VERSION_CODE >= SLE_VERSION(15, 1, 0)))
 #define HAVE_TCF_EXTS_FOR_EACH_ACTION
 #undef HAVE_TCF_EXTS_TO_LIST
 #endif /* RHEL8.0+ */
@@ -6680,7 +6810,7 @@ static inline void __kc_metadata_dst_free(void *md_dst)
 }
 
 #define metadata_dst_free(md_dst) __kc_metadata_dst_free(md_dst)
-#elif (LINUX_VERSION_CODE > KERNEL_VERSION(4,19,0))
+#else /* >= 4.19.0 */
 #define HAVE_TCF_BLOCK_CB_REGISTER_EXTACK
 #define NO_NETDEV_BPF_PROG_ATTACHED
 #define HAVE_NDO_SELECT_QUEUE_SB_DEV
@@ -6691,29 +6821,10 @@ static inline void __kc_metadata_dst_free(void *md_dst)
 #define HAVE_RHASHTABLE_TYPES
 #define HAVE_DEVLINK_REGIONS
 #define HAVE_DEVLINK_PARAMS
-#define HAVE_UDP_TUNNEL_OPS
-#define HAVE_IOPOLL_OPS
-#define HAVE_DEV_PRINTK_OPS
-#else /* = 4.19.0 */
-static inline int __sysfs_emit(char *buf, const char *fmt, ...)
-{
-	int ret;
-	va_list args;
-
-	if (WARN(!buf || offset_in_page(buf),
-		 "invalid sysfs_emit: buf:%p\n", buf))
-		return 0;
-
-	va_start(args, fmt);
-	ret = vscnprintf(buf, PAGE_SIZE, fmt, args);
-	va_end(args);
-	return ret;
-}
-#define sysfs_emit __sysfs_emit
 #endif /* 4.19.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,20,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0))
 #define HAVE_XDP_UMEM_PROPS
 #ifdef HAVE_AF_XDP_SUPPORT
 #ifndef napi_if_scheduled_mark_missed
@@ -6738,12 +6849,12 @@ static inline bool __kc_napi_if_scheduled_mark_missed(struct napi_struct *n)
 #define napi_if_scheduled_mark_missed __kc_napi_if_scheduled_mark_missed
 #endif /* !napi_if_scheduled_mark_missed */
 #endif /* HAVE_AF_XDP_SUPPORT */
-#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,0)))
+#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 0)))
 #define HAVE_DEVLINK_ESWITCH_OPS_EXTACK
 #endif /* RHEL >= 8.0 */
-#if ((SLE_VERSION_CODE >= SLE_VERSION(12,5,0) && \
-      SLE_VERSION_CODE < SLE_VERSION(15,0,0)) || \
-     (SLE_VERSION_CODE >= SLE_VERSION(15,1,0)))
+#if ((SLE_VERSION_CODE >= SLE_VERSION(12, 5, 0) && \
+	SLE_VERSION_CODE < SLE_VERSION(15, 0, 0)) || \
+	(SLE_VERSION_CODE >= SLE_VERSION(15, 1, 0)))
 #define HAVE_DEVLINK_ESWITCH_OPS_EXTACK
 #endif /* SLE == 12sp5 || SLE >= 15sp1 */
 #else /* >= 4.20.0 */
@@ -6754,10 +6865,10 @@ static inline bool __kc_napi_if_scheduled_mark_missed(struct napi_struct *n)
 #endif /* 4.20.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,0,0))
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(8,0)))
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,12,0))
-#define NETLINK_MAX_COOKIE_LEN	20
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
+#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(8, 0)))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
+#define NETLINK_MAX_COOKIE_LEN 20
 struct netlink_ext_ack {
 	const char *_msg;
 	const struct nlattr *bad_attr;
@@ -6767,7 +6878,7 @@ struct netlink_ext_ack {
 
 #endif /* < 4.12 */
 static inline int _kc_dev_open(struct net_device *netdev,
-			       struct netlink_ext_ack __always_unused *extack)
+							struct netlink_ext_ack __always_unused *extack)
 {
 	return dev_open(netdev);
 }
@@ -6776,17 +6887,16 @@ static inline int _kc_dev_open(struct net_device *netdev,
 
 static inline int
 _kc_dev_change_flags(struct net_device *netdev, unsigned int flags,
-		     struct netlink_ext_ack __always_unused *extack)
+					struct netlink_ext_ack __always_unused *extack)
 {
 	return dev_change_flags(netdev, flags);
 }
 
 #define dev_change_flags _kc_dev_change_flags
 #endif /* !(RHEL_RELEASE_CODE && RHEL > RHEL(8,0)) */
-#if (RHEL_RELEASE_CODE && \
-     (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7,7) && \
-      RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8,0)) || \
-     (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,1)))
+#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(7, 7) && \
+						RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8, 0)) || \
+	(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 1)))
 #define HAVE_PTP_SYS_OFFSET_EXTENDED_IOCTL
 #else /* RHEL >= 7.7 && RHEL < 8.0 || RHEL >= 8.1 */
 struct ptp_system_timestamp {
@@ -6806,10 +6916,10 @@ ptp_read_system_postts(struct ptp_system_timestamp __always_unused *sts)
 	;
 }
 #endif /* !(RHEL >= 7.7 && RHEL != 8.0) */
-#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,1)))
+#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 1)))
 #define HAVE_NDO_BRIDGE_SETLINK_EXTACK
 #endif /* RHEL 8.1 */
-#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,2))
+#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 2))
 #define HAVE_TC_INDIR_BLOCK
 #endif /* RHEL 8.2 */
 #else /* >= 5.0.0 */
@@ -6821,8 +6931,8 @@ ptp_read_system_postts(struct ptp_system_timestamp __always_unused *sts)
 #endif /* 5.0.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,1,0))
-#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,1)))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 1, 0))
+#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 1)))
 #define HAVE_TC_FLOW_RULE_INFRASTRUCTURE
 #define HAVE_NDO_FDB_ADD_EXTACK
 #define HAVE_DEVLINK_INFO_GET
@@ -6832,9 +6942,9 @@ ptp_read_system_postts(struct ptp_system_timestamp __always_unused *sts)
 #include <net/pkt_cls.h>
 
 struct flow_match {
-	struct flow_dissector	*dissector;
-	void			*mask;
-	void			*key;
+	struct flow_dissector *dissector;
+	void *mask;
+	void *key;
 };
 
 struct flow_match_basic {
@@ -6874,45 +6984,36 @@ struct flow_match_ports {
 };
 
 struct flow_rule {
-	struct flow_match	match;
-#if 0
-	/* In 5.1+ kernels, action is a member of struct flow_rule but is
-	 * not compatible with how we kcompat tc_cls_flower_offload_flow_rule
-	 * below.  By not declaring it here, any driver that attempts to use
-	 * action as an element of struct flow_rule will fail to compile
-	 * instead of silently trying to access memory that shouldn't be.
-	 */
-	struct flow_action	action;
-#endif
+	struct flow_match match;
 };
 
 void flow_rule_match_basic(const struct flow_rule *rule,
-			   struct flow_match_basic *out);
+						struct flow_match_basic *out);
 void flow_rule_match_control(const struct flow_rule *rule,
-			     struct flow_match_control *out);
+							struct flow_match_control *out);
 void flow_rule_match_eth_addrs(const struct flow_rule *rule,
-			       struct flow_match_eth_addrs *out);
+							struct flow_match_eth_addrs *out);
 #ifndef HAVE_TC_FLOWER_VLAN_IN_TAGS
 void flow_rule_match_vlan(const struct flow_rule *rule,
-			  struct flow_match_vlan *out);
+						struct flow_match_vlan *out);
 #endif
 void flow_rule_match_ipv4_addrs(const struct flow_rule *rule,
-				struct flow_match_ipv4_addrs *out);
+								struct flow_match_ipv4_addrs *out);
 void flow_rule_match_ipv6_addrs(const struct flow_rule *rule,
-				struct flow_match_ipv6_addrs *out);
+								struct flow_match_ipv6_addrs *out);
 void flow_rule_match_ports(const struct flow_rule *rule,
-			   struct flow_match_ports *out);
+						struct flow_match_ports *out);
 #ifdef HAVE_TC_FLOWER_ENC
 void flow_rule_match_enc_ports(const struct flow_rule *rule,
-			       struct flow_match_ports *out);
+							struct flow_match_ports *out);
 void flow_rule_match_enc_control(const struct flow_rule *rule,
-				 struct flow_match_control *out);
+								struct flow_match_control *out);
 void flow_rule_match_enc_ipv4_addrs(const struct flow_rule *rule,
-				    struct flow_match_ipv4_addrs *out);
+									struct flow_match_ipv4_addrs *out);
 void flow_rule_match_enc_ipv6_addrs(const struct flow_rule *rule,
-				    struct flow_match_ipv6_addrs *out);
+									struct flow_match_ipv6_addrs *out);
 void flow_rule_match_enc_keyid(const struct flow_rule *rule,
-			       struct flow_match_enc_keyid *out);
+							struct flow_match_enc_keyid *out);
 #endif
 
 static inline struct flow_rule *
@@ -6922,7 +7023,7 @@ tc_cls_flower_offload_flow_rule(struct tc_cls_flower_offload *tc_flow_cmd)
 }
 
 static inline bool flow_rule_match_key(const struct flow_rule *rule,
-				       enum flow_dissector_key_id key)
+									enum flow_dissector_key_id key)
 {
 	return dissector_uses_key(rule->match.dissector, key);
 }
@@ -6930,9 +7031,13 @@ static inline bool flow_rule_match_key(const struct flow_rule *rule,
 
 #endif /* RHEL < 8.1 */
 
-#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,1)))
-#define devlink_params_publish(devlink) do { } while (0)
-#define devlink_params_unpublish(devlink) do { } while (0)
+#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 1)))
+#define devlink_params_publish(devlink) \
+	do {                                \
+	} while (0)
+#define devlink_params_unpublish(devlink) \
+	do {                                  \
+	} while (0)
 #endif
 
 #else /* >= 5.1.0 */
@@ -6947,19 +7052,20 @@ static inline bool flow_rule_match_key(const struct flow_rule *rule,
 #endif /* 5.1.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,2,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0))
 #if (defined HAVE_SKB_XMIT_MORE) && \
-(!(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,2))))
-#define netdev_xmit_more()	(skb->xmit_more)
+		(!(RHEL_RELEASE_CODE &&     \
+		(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 2))))
+#define netdev_xmit_more() (skb->xmit_more)
 #else
-#define netdev_xmit_more()	(0)
+#define netdev_xmit_more() (0)
 #endif
 
-#if (!(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,2))))
+#if (!(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 2))))
 #ifndef eth_get_headlen
 static inline u32
 __kc_eth_get_headlen(const struct net_device __always_unused *dev, void *data,
-		     unsigned int len)
+					unsigned int len)
 {
 	return eth_get_headlen(data, len);
 }
@@ -6970,28 +7076,28 @@ __kc_eth_get_headlen(const struct net_device __always_unused *dev, void *data,
 
 #ifndef mmiowb
 #ifdef CONFIG_IA64
-#define mmiowb() asm volatile ("mf.a" ::: "memory")
+#define mmiowb() (asm volatile("mf.a" ::: "memory"))
 #else
 #define mmiowb()
 #endif
 #endif /* mmiowb */
 
-#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8,2))
+#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8, 2))
 #if IS_ENABLED(CONFIG_NET_DEVLINK) && !defined(devlink_port_attrs_set)
 static inline void
 _kc_devlink_port_attrs_set(struct devlink_port *devlink_port,
-			   struct _kc_devlink_port_attrs *attrs)
+						struct _kc_devlink_port_attrs *attrs)
 {
 	devlink_port_attrs_set(devlink_port, attrs->flavour,
-			       attrs->phys.port_number, attrs->split,
-			       attrs->phys.split_subport_number);
+						attrs->phys.port_number, attrs->split,
+						attrs->phys.split_subport_number);
 }
 
 #define devlink_port_attrs_set _kc_devlink_port_attrs_set
 #endif /* CONFIG_NET_DEVLINK && !devlink_port_attrs_set */
 #endif /* <RHEL8.2 */
 
-#if (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(8,1))
+#if (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(8, 1))
 #define HAVE_NDO_GET_DEVLINK_PORT
 #endif /* RHEL > 8.1 */
 
@@ -7002,8 +7108,8 @@ _kc_devlink_port_attrs_set(struct devlink_port *devlink_port,
 #endif /* 5.2.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,3,0))
-#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,2)))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 3, 0))
+#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 2)))
 #define flow_block_offload tc_block_offload
 #define flow_block_command tc_block_command
 #define flow_cls_offload tc_cls_flower_offload
@@ -7016,7 +7122,7 @@ _kc_devlink_port_attrs_set(struct devlink_port *devlink_port,
 #define FLOW_CLS_TMPLT_CREATE TC_CLSFLOWER_TMPLT_CREATE
 #define FLOW_CLS_TMPLT_DESTROY TC_CLSFLOWER_TMPLT_DESTROY
 #define FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS \
-		TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS
+	TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS
 #define FLOW_BLOCK_BIND TC_BLOCK_BIND
 #define FLOW_BLOCK_UNBIND TC_BLOCK_UNBIND
 
@@ -7024,15 +7130,14 @@ _kc_devlink_port_attrs_set(struct devlink_port *devlink_port,
 #include <net/pkt_cls.h>
 
 int _kc_flow_block_cb_setup_simple(struct flow_block_offload *f,
-				   struct list_head *driver_list,
-				   tc_setup_cb_t *cb,
-				   void *cb_ident, void *cb_priv,
-				   bool ingress_only);
+								struct list_head *driver_list,
+								tc_setup_cb_t *cb, void *cb_ident,
+								void *cb_priv, bool ingress_only);
 
 #define flow_block_cb_setup_simple(f, driver_list, cb, cb_ident, cb_priv, \
-				   ingress_only) \
+								ingress_only)                          \
 	_kc_flow_block_cb_setup_simple(f, driver_list, cb, cb_ident, cb_priv, \
-				       ingress_only)
+								ingress_only)
 #endif /* HAVE_TC_CB_AND_SETUP_QDISC_MQPRIO */
 #else /* RHEL >= 8.2 */
 #define HAVE_FLOW_BLOCK_API
@@ -7040,10 +7145,10 @@ int _kc_flow_block_cb_setup_simple(struct flow_block_offload *f,
 #endif /* RHEL >= 8.2 */
 
 #ifndef ETH_P_LLDP
-#define ETH_P_LLDP	0x88CC
+#define ETH_P_LLDP 0x88CC
 #endif /* !ETH_P_LLDP */
 
-#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8,2))
+#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8, 2))
 #if IS_ENABLED(CONFIG_NET_DEVLINK)
 static inline void
 devlink_flash_update_begin_notify(struct devlink __always_unused *devlink)
@@ -7057,17 +7162,17 @@ devlink_flash_update_end_notify(struct devlink __always_unused *devlink)
 
 static inline void
 devlink_flash_update_status_notify(struct devlink __always_unused *devlink,
-				   const char __always_unused *status_msg,
-				   const char __always_unused *component,
-				   unsigned long __always_unused done,
-				   unsigned long __always_unused total)
+								const char __always_unused *status_msg,
+								const char __always_unused *component,
+								unsigned long __always_unused done,
+								unsigned long __always_unused total)
 {
 }
 #endif /* CONFIG_NET_DEVLINK */
 #endif /* <RHEL8.2 */
 #else /* >= 5.3.0 */
 #define XSK_UMEM_RETURNS_XDP_DESC
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,8,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))
 #define HAVE_XSK_UMEM_HAS_ADDRS
 #endif /* < 5.8.0*/
 #define HAVE_FLOW_BLOCK_API
@@ -7078,9 +7183,9 @@ devlink_flash_update_status_notify(struct devlink __always_unused *devlink,
 #endif /* 5.3.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0))
-#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,2)) && \
-     !(SLE_VERSION_CODE >= SLE_VERSION(15,2,0)))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+#if (!(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 2)) && \
+	!(SLE_VERSION_CODE >= SLE_VERSION(15, 2, 0)))
 static inline unsigned int skb_frag_off(const skb_frag_t *frag)
 {
 	return frag->page_offset;
@@ -7093,7 +7198,7 @@ static inline void skb_frag_off_add(skb_frag_t *frag, int delta)
 #define __flow_indr_block_cb_register __tc_indr_block_cb_register
 #define __flow_indr_block_cb_unregister __tc_indr_block_cb_unregister
 #endif /* !(RHEL >= 8.2) && !(SLES >= 15sp2) */
-#if (SLE_VERSION_CODE >= SLE_VERSION(15,2,0))
+#if (SLE_VERSION_CODE >= SLE_VERSION(15, 2, 0))
 #define HAVE_NDO_XSK_WAKEUP
 #endif /* SLES15sp2 */
 #else /* >= 5.4.0 */
@@ -7101,9 +7206,9 @@ static inline void skb_frag_off_add(skb_frag_t *frag, int delta)
 #endif /* 5.4.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,5,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0))
 static inline unsigned long _kc_bitmap_get_value8(const unsigned long *map,
-						  unsigned long start)
+												unsigned long start)
 {
 	const size_t index = BIT_WORD(start);
 	const unsigned long offset = start % BITS_PER_LONG;
@@ -7113,8 +7218,8 @@ static inline unsigned long _kc_bitmap_get_value8(const unsigned long *map,
 #define bitmap_get_value8 _kc_bitmap_get_value8
 
 static inline void _kc_bitmap_set_value8(unsigned long *map,
-					 unsigned long value,
-					 unsigned long start)
+										unsigned long value,
+										unsigned long start)
 {
 	const size_t index = BIT_WORD(start);
 	const unsigned long offset = start % BITS_PER_LONG;
@@ -7127,12 +7232,12 @@ static inline void _kc_bitmap_set_value8(unsigned long *map,
 #endif /* 5.5.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0))
 #ifdef HAVE_AF_XDP_SUPPORT
-#define xsk_umem_release_addr		xsk_umem_discard_addr
-#define xsk_umem_release_addr_rq	xsk_umem_discard_addr_rq
+#define xsk_umem_release_addr xsk_umem_discard_addr
+#define xsk_umem_release_addr_rq xsk_umem_discard_addr_rq
 #endif /* HAVE_AF_XDP_SUPPORT */
-#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,3)))
+#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 3)))
 #define HAVE_TX_TIMEOUT_TXQUEUE
 #endif
 #else /* >= 5.6.0 */
@@ -7140,18 +7245,20 @@ static inline void _kc_bitmap_set_value8(unsigned long *map,
 #endif /* 5.6.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,7,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 7, 0))
 u64 _kc_pci_get_dsn(struct pci_dev *dev);
 #define pci_get_dsn(dev) _kc_pci_get_dsn(dev)
-#if !(SLE_VERSION_CODE > SLE_VERSION(15,2,0)) && \
-    !((LINUX_VERSION_CODE == KERNEL_VERSION(5,3,18)) && \
-      (SLE_LOCALVERSION_CODE >= KERNEL_VERSION(14,0,0))) && \
-    !(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,3)))
-#define pci_aer_clear_nonfatal_status	pci_cleanup_aer_uncorrect_error_status
+#if !(SLE_VERSION_CODE > SLE_VERSION(15, 2, 0)) &&                \
+		!((LINUX_VERSION_CODE == KERNEL_VERSION(5, 3, 18)) &&     \
+		(SLE_LOCALVERSION_CODE >= KERNEL_VERSION(14, 0, 0))) && \
+		!(RHEL_RELEASE_CODE &&                                    \
+		(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 3)))
+#define pci_aer_clear_nonfatal_status pci_cleanup_aer_uncorrect_error_status
 #endif
 
 #define cpu_latency_qos_update_request pm_qos_update_request
-#define cpu_latency_qos_add_request(arg1, arg2) pm_qos_add_request(arg1, PM_QOS_CPU_DMA_LATENCY, arg2)
+#define cpu_latency_qos_add_request(arg1, arg2) \
+	pm_qos_add_request(arg1, PM_QOS_CPU_DMA_LATENCY, arg2)
 #define cpu_latency_qos_remove_request pm_qos_remove_request
 
 #ifndef DEVLINK_INFO_VERSION_GENERIC_FW_BUNDLE_ID
@@ -7168,11 +7275,11 @@ struct devlink_region_ops {
 #ifndef devlink_region_create
 static inline struct devlink_region *
 _kc_devlink_region_create(struct devlink *devlink,
-			  const struct devlink_region_ops *ops,
-			  u32 region_max_snapshots, u64 region_size)
+						const struct devlink_region_ops *ops,
+						u32 region_max_snapshots, u64 region_size)
 {
 	return devlink_region_create(devlink, ops->name, region_max_snapshots,
-				     region_size);
+								region_size);
 }
 
 #define devlink_region_create _kc_devlink_region_create
@@ -7186,8 +7293,8 @@ _kc_devlink_region_create(struct devlink *devlink,
 #endif /* 5.7.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,8,0))
-#if !(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,4)))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))
+#if !(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 4)))
 #define xdp_convert_buff_to_frame convert_to_xdp_frame
 #endif /* (RHEL < 8.4) */
 #define flex_array_size(p, member, count) \
@@ -7208,12 +7315,12 @@ static inline u32 _xsk_umem_get_rx_frame_size(struct xdp_umem *umem)
 #define HAVE_XDP_BUFF_FRAME_SZ
 #define HAVE_MEM_TYPE_XSK_BUFF_POOL
 #endif /* 5.8.0 */
-#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,3)))
+#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 3)))
 #define HAVE_TC_FLOW_INDIR_DEV
 #endif
 
 /*****************************************************************************/
-#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,4)))
+#if (RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 4)))
 #if IS_ENABLED(CONFIG_NET_DEVLINK) && !defined(devlink_port_attrs_set)
 #undef devlink_port_attrs
 #define devlink_port_attrs_set devlink_port_attrs_set
@@ -7221,16 +7328,16 @@ static inline u32 _xsk_umem_get_rx_frame_size(struct xdp_umem *umem)
 #endif /* (RHEL >= 8.4) */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,9,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 9, 0))
 #if IS_ENABLED(CONFIG_NET_DEVLINK) && !defined(devlink_port_attrs_set)
 static inline void
 _kc_devlink_port_attrs_set(struct devlink_port *devlink_port,
-			   struct _kc_devlink_port_attrs *attrs)
+						struct _kc_devlink_port_attrs *attrs)
 {
 	devlink_port_attrs_set(devlink_port, attrs->flavour,
-			       attrs->phys.port_number, attrs->split,
-			       attrs->phys.split_subport_number,
-			       attrs->switch_id.id, attrs->switch_id.id_len);
+						attrs->phys.port_number, attrs->split,
+						attrs->phys.split_subport_number,
+						attrs->switch_id.id, attrs->switch_id.id_len);
 }
 
 #define devlink_port_attrs_set _kc_devlink_port_attrs_set
@@ -7242,7 +7349,7 @@ _kc_devlink_port_attrs_set(struct devlink_port *devlink_port,
 #endif /* 5.9.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
 struct devlink_flash_update_params {
 	const char *file_name;
 	const char *component;
@@ -7259,17 +7366,15 @@ struct devlink_flash_update_params {
 
 #if IS_ENABLED(CONFIG_NET_DEVLINK)
 #include <net/devlink.h>
-static inline void
-devlink_flash_update_timeout_notify(struct devlink *devlink,
-				    const char *status_msg,
-				    const char *component,
-				    unsigned long __always_unused timeout)
+static inline void devlink_flash_update_timeout_notify(
+		struct devlink *devlink, const char *status_msg, const char *component,
+		unsigned long __always_unused timeout)
 {
 	devlink_flash_update_status_notify(devlink, status_msg, component, 0, 0);
 }
 #endif /* CONFIG_NET_DEVLINK */
 
-#if !(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8,4)))
+#if !(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 4)))
 static inline void net_prefetch(void *p)
 {
 	prefetch(p);
@@ -7277,7 +7382,7 @@ static inline void net_prefetch(void *p)
 	prefetch((u8 *)p + L1_CACHE_BYTES);
 #endif
 }
-#endif  /* (RHEL < 8.4) */
+#endif /* (RHEL < 8.4) */
 
 #define XDP_SETUP_XSK_POOL XDP_SETUP_XSK_UMEM
 #define xsk_get_pool_from_qid xdp_get_umem_from_qid
@@ -7291,9 +7396,8 @@ static inline void net_prefetch(void *p)
 #define xsk_uses_need_wakeup xsk_umem_uses_need_wakeup
 #ifdef HAVE_MEM_TYPE_XSK_BUFF_POOL
 #include <net/xdp_sock_drv.h>
-static inline void
-_kc_xsk_buff_dma_sync_for_cpu(struct xdp_buff *xdp,
-			      void __always_unused *pool)
+static inline void _kc_xsk_buff_dma_sync_for_cpu(struct xdp_buff *xdp,
+												void __always_unused *pool)
 {
 	xsk_buff_dma_sync_for_cpu(xdp);
 }
@@ -7308,12 +7412,12 @@ _kc_xsk_buff_dma_sync_for_cpu(struct xdp_buff *xdp,
 #endif /* 5.10.0 */
 
 /*****************************************************************************/
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,11,0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0))
 #ifdef HAVE_XDP_BUFF_RXQ
 #include <net/xdp.h>
-static inline int
-_kc_xdp_rxq_info_reg(struct xdp_rxq_info *xdp_rxq, struct net_device *dev,
-		     u32 queue_index, unsigned int __always_unused napi_id)
+static inline int _kc_xdp_rxq_info_reg(struct xdp_rxq_info *xdp_rxq,
+									struct net_device *dev, u32 queue_index,
+									unsigned int __always_unused napi_id)
 {
 	return xdp_rxq_info_reg(xdp_rxq, dev, queue_index);
 }
@@ -7326,7 +7430,7 @@ _kc_xdp_rxq_info_reg(struct xdp_rxq_info *xdp_rxq, struct net_device *dev,
 #define HAVE_DEVLINK_FLASH_UPDATE_PARAMS_FW
 #endif /* 5.11.0 */
 
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,13,0))
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 13, 0))
 #define HAVE_ETHTOOL_GET_MODULE_EEPROM_BY_PAGE
 #endif
 
diff --git a/src/net/include/linux/dinghai/kcompat_vfd.h b/src/net/include/linux/dinghai/kcompat_vfd.h
index a0c6c7b2d62f3fff69a7f80454920f1e11063fb4..f73b8e3030132b0bc99229e5d04e3d460679cbbf 100644
--- a/src/net/include/linux/dinghai/kcompat_vfd.h
+++ b/src/net/include/linux/dinghai/kcompat_vfd.h
@@ -4,21 +4,21 @@
 #ifndef _KCOMPAT_VFD_H_
 #define _KCOMPAT_VFD_H_
 
-#define VFD_PROMISC_OFF		0x00
-#define VFD_PROMISC_UNICAST	0x01
-#define VFD_PROMISC_MULTICAST	0x02
+#define VFD_PROMISC_OFF 0x00
+#define VFD_PROMISC_UNICAST 0x01
+#define VFD_PROMISC_MULTICAST 0x02
 
-#define VFD_LINKSTATE_OFF	0x00
-#define VFD_LINKSTATE_ON	0x01
-#define VFD_LINKSTATE_AUTO	0x02
+#define VFD_LINKSTATE_OFF 0x00
+#define VFD_LINKSTATE_ON 0x01
+#define VFD_LINKSTATE_AUTO 0x02
 
-#define VFD_EGRESS_MIRROR_OFF	-1
-#define VFD_INGRESS_MIRROR_OFF	-1
+#define VFD_EGRESS_MIRROR_OFF -1
+#define VFD_INGRESS_MIRROR_OFF -1
 
-#define VFD_QUEUE_TYPE_RSS	0x00
-#define VFD_QUEUE_TYPE_QOS	0x01
+#define VFD_QUEUE_TYPE_RSS 0x00
+#define VFD_QUEUE_TYPE_QOS 0x01
 
-#define VFD_NUM_TC		0x8
+#define VFD_NUM_TC 0x8
 
 /**
  * struct vfd_objects - VF-d kobjects information struct
@@ -60,90 +60,82 @@ struct vfd_macaddr {
 	struct list_head list;
 };
 
-#define VFD_LINK_SPEED_2_5GB_SHIFT		0x0
-#define VFD_LINK_SPEED_100MB_SHIFT		0x1
-#define VFD_LINK_SPEED_1GB_SHIFT		0x2
-#define VFD_LINK_SPEED_10GB_SHIFT		0x3
-#define VFD_LINK_SPEED_40GB_SHIFT		0x4
-#define VFD_LINK_SPEED_20GB_SHIFT		0x5
-#define VFD_LINK_SPEED_25GB_SHIFT		0x6
-#define VFD_LINK_SPEED_5GB_SHIFT		0x7
-
+#define VFD_LINK_SPEED_2_5GB_SHIFT 0x0
+#define VFD_LINK_SPEED_100MB_SHIFT 0x1
+#define VFD_LINK_SPEED_1GB_SHIFT 0x2
+#define VFD_LINK_SPEED_10GB_SHIFT 0x3
+#define VFD_LINK_SPEED_40GB_SHIFT 0x4
+#define VFD_LINK_SPEED_20GB_SHIFT 0x5
+#define VFD_LINK_SPEED_25GB_SHIFT 0x6
+#define VFD_LINK_SPEED_5GB_SHIFT 0x7
 
 enum vfd_link_speed {
-	VFD_LINK_SPEED_UNKNOWN	= 0,
-	VFD_LINK_SPEED_100MB	= BIT(VFD_LINK_SPEED_100MB_SHIFT),
-	VFD_LINK_SPEED_1GB	= BIT(VFD_LINK_SPEED_1GB_SHIFT),
-	VFD_LINK_SPEED_2_5GB	= BIT(VFD_LINK_SPEED_2_5GB_SHIFT),
-	VFD_LINK_SPEED_5GB	= BIT(VFD_LINK_SPEED_5GB_SHIFT),
-	VFD_LINK_SPEED_10GB	= BIT(VFD_LINK_SPEED_10GB_SHIFT),
-	VFD_LINK_SPEED_40GB	= BIT(VFD_LINK_SPEED_40GB_SHIFT),
-	VFD_LINK_SPEED_20GB	= BIT(VFD_LINK_SPEED_20GB_SHIFT),
-	VFD_LINK_SPEED_25GB	= BIT(VFD_LINK_SPEED_25GB_SHIFT),
+	VFD_LINK_SPEED_UNKNOWN = 0,
+	VFD_LINK_SPEED_100MB = BIT(VFD_LINK_SPEED_100MB_SHIFT),
+	VFD_LINK_SPEED_1GB = BIT(VFD_LINK_SPEED_1GB_SHIFT),
+	VFD_LINK_SPEED_2_5GB = BIT(VFD_LINK_SPEED_2_5GB_SHIFT),
+	VFD_LINK_SPEED_5GB = BIT(VFD_LINK_SPEED_5GB_SHIFT),
+	VFD_LINK_SPEED_10GB = BIT(VFD_LINK_SPEED_10GB_SHIFT),
+	VFD_LINK_SPEED_40GB = BIT(VFD_LINK_SPEED_40GB_SHIFT),
+	VFD_LINK_SPEED_20GB = BIT(VFD_LINK_SPEED_20GB_SHIFT),
+	VFD_LINK_SPEED_25GB = BIT(VFD_LINK_SPEED_25GB_SHIFT),
 };
 
 struct vfd_ops {
 	int (*get_trunk)(struct pci_dev *pdev, int vf_id, unsigned long *buff);
 	int (*set_trunk)(struct pci_dev *pdev, int vf_id,
-			 const unsigned long *buff);
+					 const unsigned long *buff);
 	int (*get_vlan_mirror)(struct pci_dev *pdev, int vf_id,
-			       unsigned long *buff);
+						   unsigned long *buff);
 	int (*set_vlan_mirror)(struct pci_dev *pdev, int vf_id,
-			       const unsigned long *buff);
+						   const unsigned long *buff);
 	int (*get_egress_mirror)(struct pci_dev *pdev, int vf_id, int *data);
-	int (*set_egress_mirror)(struct pci_dev *pdev, int vf_id,
-				 const int data);
+	int (*set_egress_mirror)(struct pci_dev *pdev, int vf_id, const int data);
 	int (*get_ingress_mirror)(struct pci_dev *pdev, int vf_id, int *data);
-	int (*set_ingress_mirror)(struct pci_dev *pdev, int vf_id,
-				  const int data);
+	int (*set_ingress_mirror)(struct pci_dev *pdev, int vf_id, const int data);
 	int (*get_mac_anti_spoof)(struct pci_dev *pdev, int vf_id, bool *data);
-	int (*set_mac_anti_spoof)(struct pci_dev *pdev, int vf_id,
-				  const bool data);
+	int (*set_mac_anti_spoof)(struct pci_dev *pdev, int vf_id, const bool data);
 	int (*get_vlan_anti_spoof)(struct pci_dev *pdev, int vf_id, bool *data);
 	int (*set_vlan_anti_spoof)(struct pci_dev *pdev, int vf_id,
-				   const bool data);
+							   const bool data);
 	int (*get_allow_untagged)(struct pci_dev *pdev, int vf_id, bool *data);
-	int (*set_allow_untagged)(struct pci_dev *pdev, int vf_id,
-				  const bool data);
+	int (*set_allow_untagged)(struct pci_dev *pdev, int vf_id, const bool data);
 	int (*get_loopback)(struct pci_dev *pdev, int vf_id, bool *data);
 	int (*set_loopback)(struct pci_dev *pdev, int vf_id, const bool data);
 	int (*get_mac)(struct pci_dev *pdev, int vf_id, u8 *macaddr);
 	int (*set_mac)(struct pci_dev *pdev, int vf_id, const u8 *macaddr);
 	int (*get_mac_list)(struct pci_dev *pdev, int vf_id,
-			    struct list_head *mac_list);
+						struct list_head *mac_list);
 	int (*add_macs_to_list)(struct pci_dev *pdev, int vf_id,
-				struct list_head *mac_list);
+							struct list_head *mac_list);
 	int (*rem_macs_from_list)(struct pci_dev *pdev, int vf_id,
-				  struct list_head *mac_list);
+							  struct list_head *mac_list);
 	int (*get_promisc)(struct pci_dev *pdev, int vf_id, u8 *data);
 	int (*set_promisc)(struct pci_dev *pdev, int vf_id, const u8 data);
 	int (*get_vlan_strip)(struct pci_dev *pdev, int vf_id, bool *data);
 	int (*set_vlan_strip)(struct pci_dev *pdev, int vf_id, const bool data);
 	int (*get_link_state)(struct pci_dev *pdev, int vf_id, bool *enabled,
-			      enum vfd_link_speed *link_speed);
+						  enum vfd_link_speed *link_speed);
 	int (*set_link_state)(struct pci_dev *pdev, int vf_id, const u8 data);
 	int (*get_max_tx_rate)(struct pci_dev *pdev, int vf_id,
-			       unsigned int *max_tx_rate);
+						   unsigned int *max_tx_rate);
 	int (*set_max_tx_rate)(struct pci_dev *pdev, int vf_id,
-			       unsigned int *max_tx_rate);
-	int (*get_min_tx_rate)(struct kobject *,
-			       struct kobj_attribute *, char *);
+						   unsigned int *max_tx_rate);
+	int (*get_min_tx_rate)(struct kobject *, struct kobj_attribute *, char *);
 	int (*set_min_tx_rate)(struct kobject *, struct kobj_attribute *,
-			       const char *, size_t);
-	int (*get_spoofcheck)(struct kobject *,
-			      struct kobj_attribute *, char *);
+						   const char *, size_t);
+	int (*get_spoofcheck)(struct kobject *, struct kobj_attribute *, char *);
 	int (*set_spoofcheck)(struct kobject *, struct kobj_attribute *,
-			      const char *, size_t);
-	int (*get_trust)(struct kobject *,
-			 struct kobj_attribute *, char *);
-	int (*set_trust)(struct kobject *, struct kobj_attribute *,
-			 const char *, size_t);
+						  const char *, size_t);
+	int (*get_trust)(struct kobject *, struct kobj_attribute *, char *);
+	int (*set_trust)(struct kobject *, struct kobj_attribute *, const char *,
+					 size_t);
 	int (*get_vf_enable)(struct pci_dev *pdev, int vf_id, bool *data);
 	int (*set_vf_enable)(struct pci_dev *pdev, int vf_id, const bool data);
-	int (*get_rx_bytes)  (struct pci_dev *pdev, int vf_id, u64 *data);
+	int (*get_rx_bytes)(struct pci_dev *pdev, int vf_id, u64 *data);
 	int (*get_rx_dropped)(struct pci_dev *pdev, int vf_id, u64 *data);
 	int (*get_rx_packets)(struct pci_dev *pdev, int vf_id, u64 *data);
-	int (*get_tx_bytes)  (struct pci_dev *pdev, int vf_id, u64 *data);
+	int (*get_tx_bytes)(struct pci_dev *pdev, int vf_id, u64 *data);
 	int (*get_tx_dropped)(struct pci_dev *pdev, int vf_id, u64 *data);
 	int (*get_tx_packets)(struct pci_dev *pdev, int vf_id, u64 *data);
 	int (*get_tx_spoofed)(struct pci_dev *pdev, int vf_id, u64 *data);
@@ -159,7 +151,8 @@ struct vfd_ops {
 	int (*get_pf_tpid)(struct pci_dev *pdev, u16 *data);
 	int (*set_pf_tpid)(struct pci_dev *pdev, const u16 data);
 	int (*get_num_queues)(struct pci_dev *pdev, int vf_id, int *num_queues);
-	int (*set_num_queues)(struct pci_dev *pdev, int vf_id, const int num_queues);
+	int (*set_num_queues)(struct pci_dev *pdev, int vf_id,
+						  const int num_queues);
 	int (*get_trust_state)(struct pci_dev *pdev, int vf_id, bool *data);
 	int (*set_trust_state)(struct pci_dev *pdev, int vf_id, bool data);
 	int (*get_queue_type)(struct pci_dev *pdev, int vf_id, u8 *data);
@@ -171,17 +164,16 @@ struct vfd_ops {
 	int (*get_pf_qos_tc_lsp)(struct pci_dev *pdev, int tc, bool *on);
 	int (*set_pf_qos_tc_lsp)(struct pci_dev *pdev, int tc, bool on);
 	int (*get_pf_qos_tc_priority)(struct pci_dev *pdev, int tc,
-				      char *tc_bitmap);
-	int (*set_pf_qos_tc_priority)(struct pci_dev *pdev, int tc,
-				      char tc_bitmap);
+								  char *tc_bitmap);
+	int (*set_pf_qos_tc_priority)(struct pci_dev *pdev, int tc, char tc_bitmap);
 	int (*get_vf_qos_tc_share)(struct pci_dev *pdev, int vf_id, int tc,
-				   u8 *share);
+							   u8 *share);
 	int (*set_vf_qos_tc_share)(struct pci_dev *pdev, int vf_id, int tc,
-				   u8 share);
+							   u8 share);
 	int (*get_vf_max_tc_tx_rate)(struct pci_dev *pdev, int vf_id, int tc,
-				     int *rate);
+								 int *rate);
 	int (*set_vf_max_tc_tx_rate)(struct pci_dev *pdev, int vf_id, int tc,
-				     int rate);
+								 int rate);
 };
 
 extern const struct vfd_ops *vfd_ops;
diff --git a/src/net/include/linux/dinghai/lag.h b/src/net/include/linux/dinghai/lag.h
index 819297f56cb7da7f0d53aa809973fbb9d28cd8fd..6b9440a0410355e85df523afe291b84f12c89f25 100644
--- a/src/net/include/linux/dinghai/lag.h
+++ b/src/net/include/linux/dinghai/lag.h
@@ -4,23 +4,26 @@
 #include <linux/netdevice.h>
 #include <linux/dinghai/driver.h>
 
-#define ZXDH_PF_VFID(ep, pf)     (1152 + ep * 8 + pf)
+#define ZXDH_PF_VFID(ep, pf) (1152 + ep * 8 + pf)
 
-struct zxdh_lag_attrs
-{
-    uint16_t pannel_id;
-    uint16_t vport;
-    uint32_t qid[2];
-    uint16_t slot_id;
-    uint16_t pcie_id;
-    uint8_t  phy_port;
-    uint8_t  rsv;
+struct zxdh_lag_attrs {
+	uint16_t pannel_id;
+	uint16_t vport;
+	uint32_t qid[2];
+	uint16_t slot_id;
+	uint16_t pcie_id;
+	uint8_t phy_port;
+	uint8_t rsv;
 };
 
 void zxdh_regitster_ldev(struct dh_core_dev *dh_devs);
 void zxdh_unregitster_ldev(struct dh_core_dev *dh_dev);
 
-int32_t zxdh_ldev_add_netdev(struct dh_core_dev *dev, uint16_t ida, struct net_device *netdev, struct zxdh_lag_attrs *attr);
-void zxdh_ldev_remove_netdev(struct dh_core_dev *dh_dev, struct net_device *netdev, struct zxdh_lag_attrs *attr);
+int32_t zxdh_ldev_add_netdev(struct dh_core_dev *dev, uint16_t ida,
+							 struct net_device *netdev,
+							 struct zxdh_lag_attrs *attr);
+void zxdh_ldev_remove_netdev(struct dh_core_dev *dh_dev,
+							 struct net_device *netdev,
+							 struct zxdh_lag_attrs *attr);
 
 #endif /* __DINGHAI_LAG_H__ */
\ No newline at end of file
diff --git a/src/net/include/linux/dinghai/log.h b/src/net/include/linux/dinghai/log.h
index 9d8bfbe6045f042f0b1793010d02c42a827af962..6ec9c92d236ab128669f190811928d51a38720cc 100644
--- a/src/net/include/linux/dinghai/log.h
+++ b/src/net/include/linux/dinghai/log.h
@@ -1,39 +1,42 @@
-#ifndef __KERNEL_LOG_H__
-#define __KERNEL_LOG_H__
-
-#include <linux/kernel.h>
-#include <linux/printk.h>
-
-#define MODULE_CMD            "zxdh_cmd"
-#define MODULE_NP             "zxdh_np"
-#define MODULE_PF             "zxdh_pf"
-#define MODULE_PTP            "zxdh_ptp"
-#define MODULE_TSN            "zxdh_tsn"
-#define MODULE_LAG            "zxdh_lag"
-#define MODULE_DHTOOLS        "zxdh_tool"
-#define MODULE_SEC            "zxdh_sec"
-#define MODULE_MPF            "zxdh_mpf"
-#define MODULE_FUC_HP         "zxdh_func_hp"
-
-#define DH_LOG_EMERG(module, fmt, arg...)       \
-        printk(KERN_EMERG "[%s][%s][%d] "fmt"", module, __func__, __LINE__, ##arg);
-
-#define DH_LOG_ALERT(module, fmt, arg...)       \
-        printk(KERN_ALERT "[%s][%s][%d] "fmt"", module, __func__, __LINE__, ##arg);
-
-#define DH_LOG_CRIT(module, fmt, arg...)       \
-        printk(KERN_CRIT "[%s][%s][%d] "fmt"", module, __func__, __LINE__, ##arg);
-
-#define DH_LOG_ERR(module, fmt, arg...)        \
-        printk(KERN_ERR "[%s][%s][%d] "fmt"", module, __func__, __LINE__, ##arg);
-
-#define DH_LOG_WARNING(module, fmt, arg...)    \
-        printk(KERN_WARNING "[%s][%s][%d] "fmt"", module, __func__, __LINE__, ##arg);
-
-#define DH_LOG_INFO(module, fmt, arg...)       \
-        printk(KERN_INFO "[%s][%s][%d] "fmt"", module, __func__, __LINE__, ##arg);
-
-#define DH_LOG_DEBUG(module, fmt, arg...)      \
-        printk(KERN_DEBUG "[%s][%s][%d] "fmt"", module, __func__, __LINE__, ##arg);
-
-#endif /* __KERNEL_LOG_H__ */
+#ifndef __KERNEL_LOG_H__
+#define __KERNEL_LOG_H__
+
+#include <linux/kernel.h>
+#include <linux/printk.h>
+
+#define MODULE_CMD "offload_smartnic_zxdh_cmd"
+#define MODULE_NP "offload_smartnic_zxdh_np"
+#define MODULE_PF "offload_smartnic_zxdh_pf"
+#define MODULE_PTP "offload_smartnic_zxdh_ptp"
+#define MODULE_LAG "offload_smartnic_zxdh_lag"
+#define MODULE_DHTOOLS "offload_smartnic_zxdh_tool"
+#define MODULE_SEC "offload_smartnic_zxdh_sec"
+#define MODULE_MPF "offload_smartnic_zxdh_mpf"
+#define MODULE_FUC_HP "offload_smartnic_zxdh_func_hp"
+
+#define DH_LOG_EMERG(module, fmt, arg...)                                 \
+	printk(KERN_EMERG "[%s][%s][%d] " fmt "", module, __func__, __LINE__, \
+		   ##arg);
+
+#define DH_LOG_ALERT(module, fmt, arg...)                                 \
+	printk(KERN_ALERT "[%s][%s][%d] " fmt "", module, __func__, __LINE__, \
+		   ##arg);
+
+#define DH_LOG_CRIT(module, fmt, arg...) \
+	printk(KERN_CRIT "[%s][%s][%d] " fmt "", module, __func__, __LINE__, ##arg);
+
+#define DH_LOG_ERR(module, fmt, arg...) \
+	printk(KERN_ERR "[%s][%s][%d] " fmt "", module, __func__, __LINE__, ##arg);
+
+#define DH_LOG_WARNING(module, fmt, arg...)                                 \
+	printk(KERN_WARNING "[%s][%s][%d] " fmt "", module, __func__, __LINE__, \
+		   ##arg);
+
+#define DH_LOG_INFO(module, fmt, arg...) \
+	printk(KERN_INFO "[%s][%s][%d] " fmt "", module, __func__, __LINE__, ##arg);
+
+#define DH_LOG_DEBUG(module, fmt, arg...)                                 \
+	printk(KERN_DEBUG "[%s][%s][%d] " fmt "", module, __func__, __LINE__, \
+		   ##arg);
+
+#endif /* __KERNEL_LOG_H__ */
diff --git a/src/net/include/linux/dinghai/pci_irq.h b/src/net/include/linux/dinghai/pci_irq.h
old mode 100755
new mode 100644
index 4ffb05d6bd46e3ae16ea7b64efe24585b21a0b1a..e2477590167f2c5668259218726eae0fcc9fd6d3
--- a/src/net/include/linux/dinghai/pci_irq.h
+++ b/src/net/include/linux/dinghai/pci_irq.h
@@ -1,70 +1,74 @@
-#ifndef DINGHAI_PCI_IRQ_H
-#define DINGHAI_PCI_IRQ_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <linux/xarray.h>
-#include <linux/types.h>
-
-#define DH_MAX_IRQ_NAME 100
-#define DH_FW_RESERVED_EQS 16
-/* max irq_index is 2047, so four chars */
-#define DH_MAX_IRQ_IDX_CHARS (4)
-#define DH_EQ_REFS_PER_IRQ (2)
-
-#define ZXDH_VQS_CHANNELS_NUM (64+2)
-#define ZXDH_BOND_VQS_CHANNELS_NUM 3
-#define ZXDH_ASYNC_CHANNELS_NUM 38
-#define ZXDH_RDMA_CHANNELS_NUM 24
-#define ZXDH_RDMA_IRQ_START_IDX 38
-#define ZXDH_VQS_IRQ_START_IDX 62
-
-struct dh_irq;
-
-struct dh_irq_pool {
-    char name[DH_MAX_IRQ_NAME];
-    struct xa_limit xa_num_irqs;
-    struct mutex lock; /* sync IRQs creations */
-    struct xarray irqs;
-    uint32_t max_threshold;
-    uint32_t min_threshold;
-    uint16_t *irqs_per_cpu;
-    struct dh_core_dev *dev;
-};
-
-static inline bool dh_irq_pool_is_sf_pool(struct dh_irq_pool *pool)
-{
-    return !strncmp("dh_mpf_sf", pool->name, strlen("dh_mpf_sf"));
-}
-
-struct dh_irq *zxdh_get_irq_of_pool(struct dh_core_dev *dev, struct dh_irq_pool *pool);
-
-struct dh_irq *dh_irq_alloc(struct dh_irq_pool *pool, int32_t i,
-                            const struct cpumask *affinity);
-
-int32_t dh_irq_read_locked(struct dh_irq *irq);
-int32_t dh_irq_get_locked(struct dh_irq *irq);
-int32_t dh_irq_put(struct dh_irq *irq);
-
-void irq_pool_free(struct dh_irq_pool *pool);
-struct dh_irq_pool *
-irq_pool_alloc(struct dh_core_dev *dev, int32_t start, int32_t size, char *name,
-               uint32_t min_threshold, uint32_t max_threshold);
-
-struct dh_irq {
-    struct atomic_notifier_head nh; /* notification chain invoked when an interruption is triggered. the invocation environment is the atomic context */
-    cpumask_var_t mask;             /* interrupt affinity */
-    char name[DH_MAX_IRQ_NAME];     /* interrupt name */
-    struct dh_irq_pool *pool;       /* interrupt pool */
-    int32_t refcount;
-    uint32_t index;                 /* interrupt vec index */
-    int32_t irqn;                   /* interrupt number */
-};
-
-#ifdef __cplusplus
-}
-#endif
-
+#ifndef DINGHAI_PCI_IRQ_H
+#define DINGHAI_PCI_IRQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <linux/xarray.h>
+#include <linux/types.h>
+
+#define DH_MAX_IRQ_NAME 100
+#define DH_FW_RESERVED_EQS 16
+/* max irq_index is 2047, so four chars */
+#define DH_MAX_IRQ_IDX_CHARS (4)
+#define DH_EQ_REFS_PER_IRQ (2)
+
+#define ZXDH_VQS_CHANNELS_NUM (64 + 2)
+#define ZXDH_BOND_VQS_CHANNELS_NUM 3
+#define ZXDH_ASYNC_CHANNELS_NUM 38
+#define ZXDH_RDMA_CHANNELS_NUM 24
+#define ZXDH_RDMA_IRQ_START_IDX 38
+#define ZXDH_VQS_IRQ_START_IDX 62
+
+struct dh_irq;
+
+struct dh_irq_pool {
+	char name[DH_MAX_IRQ_NAME];
+	struct xa_limit xa_num_irqs;
+	struct mutex lock; /* sync IRQs creations */
+	struct xarray irqs;
+	uint32_t max_threshold;
+	uint32_t min_threshold;
+	uint16_t *irqs_per_cpu;
+	struct dh_core_dev *dev;
+};
+
+static inline bool dh_irq_pool_is_sf_pool(struct dh_irq_pool *pool)
+{
+	return !strncmp("dh_mpf_sf", pool->name, strlen("dh_mpf_sf"));
+}
+
+struct dh_irq *zxdh_get_irq_of_pool(struct dh_core_dev *dev,
+									struct dh_irq_pool *pool);
+
+struct dh_irq *dh_irq_alloc(struct dh_irq_pool *pool, int32_t i,
+							const struct cpumask *affinity);
+
+int32_t dh_irq_read_locked(struct dh_irq *irq);
+int32_t dh_irq_get_locked(struct dh_irq *irq);
+int32_t dh_irq_put(struct dh_irq *irq);
+
+void irq_pool_free(struct dh_irq_pool *pool);
+struct dh_irq_pool *irq_pool_alloc(struct dh_core_dev *dev, int32_t start,
+								   int32_t size, char *name,
+								   uint32_t min_threshold,
+								   uint32_t max_threshold);
+
+struct dh_irq {
+	struct atomic_notifier_head
+			nh; /* notification chain invoked when an interruption is triggered. the
+				 invocation environment is the atomic context */
+	cpumask_var_t mask; /* interrupt affinity */
+	char name[DH_MAX_IRQ_NAME]; /* interrupt name */
+	struct dh_irq_pool *pool; /* interrupt pool */
+	int32_t refcount;
+	uint32_t index; /* interrupt vec index */
+	int32_t irqn; /* interrupt number */
+};
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/src/net/include/linux/dinghai/queue.h b/src/net/include/linux/dinghai/queue.h
index 29cce9ecad50224bfdd6f29ddc833e5373e8f8ef..72a436c15fbbfa156d4efee99ae5c46a7075fc5c 100644
--- a/src/net/include/linux/dinghai/queue.h
+++ b/src/net/include/linux/dinghai/queue.h
@@ -1,78 +1,73 @@
-#ifndef __DINGHAI_QUEUE_H__
-#define __DINGHAI_QUEUE_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Vector value used to disable MSI for queue */
-#define ZXDH_MSI_NO_VECTOR      0xffff
-
-/* Status byte for guest to report progress, and synchronize features */
-/* We have seen device and processed generic fields */
-#define ZXDH_CONFIG_S_ACKNOWLEDGE 1
-/* We have found a driver for the device. */
-#define ZXDH_CONFIG_S_DRIVER      2
-/* Driver has used its parts of the config, and is happy */
-#define ZXDH_CONFIG_S_DRIVER_OK   4
-/* Driver has finished configuring features */
-#define ZXDH_CONFIG_S_FEATURES_OK 8
-/* Device entered invalid state, driver must reset it */
-#define ZXDH_CONFIG_S_NEEDS_RESET 0x40
-/* We've given up on this device */
-#define ZXDH_CONFIG_S_FAILED      0x80
-
-
-/* This is the PCI capability header: */
-struct zxdh_pf_pci_cap
-{
-    __u8 cap_vndr;        /* Generic PCI field: PCI_CAP_ID_VNDR */
-    __u8 cap_next;        /* Generic PCI field: next ptr. */
-    __u8 cap_len;         /* Generic PCI field: capability length */
-    __u8 cfg_type;        /* Identifies the structure. */
-    __u8 bar;             /* Where to find it. */
-    __u8 id;              /* Multiple capabilities of the same type */
-    __u8 padding[2];      /* Pad to full dword. */
-    __le32 offset;        /* Offset within bar. */
-    __le32 length;        /* Length of the structure, in bytes. */
-};
-
-/* Fields in ZXDH_PF_PCI_CAP_COMMON_CFG: */
-struct zxdh_pf_pci_common_cfg
-{
-    /* About the whole device. */
-    __le32 device_feature_select; /* read-write */
-    __le32 device_feature;        /* read-only */
-    __le32 guest_feature_select;  /* read-write */
-    __le32 guest_feature;         /* read-write */
-    __le16 msix_config;           /* read-write */
-    __le16 num_queues;            /* read-only */
-    __u8 device_status;           /* read-write */
-    __u8 config_generation;       /* read-only */
-
-    /* About a specific virtqueue. */
-    __le16 queue_select;          /* read-write */
-    __le16 queue_size;            /* read-write, power of 2. */
-    __le16 queue_msix_vector;     /* read-write */
-    __le16 queue_enable;          /* read-write */
-    __le16 queue_notify_off;      /* read-only */
-    __le32 queue_desc_lo;         /* read-write */
-    __le32 queue_desc_hi;         /* read-write */
-    __le32 queue_avail_lo;        /* read-write */
-    __le32 queue_avail_hi;        /* read-write */
-    __le32 queue_used_lo;         /* read-write */
-    __le32 queue_used_hi;         /* read-write */
-};
-
-struct zxdh_pf_pci_notify_cap
-{
-    struct zxdh_pf_pci_cap cap;
-    __le32 notify_off_multiplier; /* Multiplier for queue_notify_off. */
-};
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+#ifndef __DINGHAI_QUEUE_H__
+#define __DINGHAI_QUEUE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Vector value used to disable MSI for queue */
+#define ZXDH_MSI_NO_VECTOR 0xffff
+
+/* Status byte for guest to report progress, and synchronize features */
+/* We have seen device and processed generic fields */
+#define ZXDH_CONFIG_S_ACKNOWLEDGE 1
+/* We have found a driver for the device. */
+#define ZXDH_CONFIG_S_DRIVER 2
+/* Driver has used its parts of the config, and is happy */
+#define ZXDH_CONFIG_S_DRIVER_OK 4
+/* Driver has finished configuring features */
+#define ZXDH_CONFIG_S_FEATURES_OK 8
+/* Device entered invalid state, driver must reset it */
+#define ZXDH_CONFIG_S_NEEDS_RESET 0x40
+/* We've given up on this device */
+#define ZXDH_CONFIG_S_FAILED 0x80
+
+/* This is the PCI capability header: */
+struct zxdh_pf_pci_cap {
+	__u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */
+	__u8 cap_next; /* Generic PCI field: next ptr. */
+	__u8 cap_len; /* Generic PCI field: capability length */
+	__u8 cfg_type; /* Identifies the structure. */
+	__u8 bar; /* Where to find it. */
+	__u8 id; /* Multiple capabilities of the same type */
+	__u8 padding[2]; /* Pad to full dword. */
+	__le32 offset; /* Offset within bar. */
+	__le32 length; /* Length of the structure, in bytes. */
+};
+
+/* Fields in ZXDH_PF_PCI_CAP_COMMON_CFG: */
+struct zxdh_pf_pci_common_cfg {
+	/* About the whole device. */
+	__le32 device_feature_select; /* read-write */
+	__le32 device_feature; /* read-only */
+	__le32 guest_feature_select; /* read-write */
+	__le32 guest_feature; /* read-write */
+	__le16 msix_config; /* read-write */
+	__le16 num_queues; /* read-only */
+	__u8 device_status; /* read-write */
+	__u8 config_generation; /* read-only */
+
+	/* About a specific virtqueue. */
+	__le16 queue_select; /* read-write */
+	__le16 queue_size; /* read-write, power of 2. */
+	__le16 queue_msix_vector; /* read-write */
+	__le16 queue_enable; /* read-write */
+	__le16 queue_notify_off; /* read-only */
+	__le32 queue_desc_lo; /* read-write */
+	__le32 queue_desc_hi; /* read-write */
+	__le32 queue_avail_lo; /* read-write */
+	__le32 queue_avail_hi; /* read-write */
+	__le32 queue_used_lo; /* read-write */
+	__le32 queue_used_hi; /* read-write */
+};
+
+struct zxdh_pf_pci_notify_cap {
+	struct zxdh_pf_pci_cap cap;
+	__le32 notify_off_multiplier; /* Multiplier for queue_notify_off. */
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/net/include/linux/types.h b/src/net/include/linux/types.h
old mode 100755
new mode 100644
diff --git a/src/net/pci.updates b/src/net/pci.updates
index f9fd22e5c7d74d1fabfdf8703ab62af969b5d82a..c7d0ba8b8d17b28c0b125e8a4f92da4910471cb3 100644
--- a/src/net/pci.updates
+++ b/src/net/pci.updates
@@ -17,28 +17,28 @@
 #               subvendor subdevice  subsystem_name     <-- two tabs
 
 1111  Santa Cruz Operation
-	1041  MPF Ethernet Controller
+	1041  ZXDH MPF Ethernet Controller
 16c3  Synopsys, Inc.
-	8040  PF BSI Ethernet Controller
-	8041  VF BSI Ethernet Controller Virtual Function
+	8040  ZXDH PF BSI Ethernet Controller
+	8041  ZXDH VF BSI Ethernet Controller Virtual Function
 1cf2  ZTE Corporation
-	8040  NEO X510 SRIOV PF Ethernet Controller
-	8041  NEO X510 SRIOV VF Ethernet Controller Virtual Function
-	8042  NX I512 VDPA VF Ethernet Controller Virtual Function
-	8044  NEO X510 MPF Ethernet Controller
-	8045  NX I512 BOND PF Ethernet Controller
-	8046  NX I512 OVS PF Ethernet Controller
-	8047  NEO X510 BOND PF Ethernet Controller
-	8048  NEO X510 OVS PF Ethernet Controller
-	8049  NX E312 SRIOV PF Ethernet Controller
-	8060  NX E312 SRIOV VF Ethernet Controller Virtual Function
-	8061  NX E310 SRIOV PF Ethernet Controller
-	8062  NX E310 SRIOV VF Ethernet Controller Virtual Function
-	8063  NX I510 BOND PF Ethernet Controller
-	8064  NX I510 OVS PF Ethernet Controller
-	8065  NX I510 VDPA VF Ethernet Controller Virtual Function
-	8066  NX I511 BOND PF Ethernet Controller
-	8067  NX I511 OVS PF Ethernet Controller
-	8068  NX I511 VDPA VF Ethernet Controller Virtual Function
+	8040  ZXDH NEO X510 SRIOV PF Ethernet Controller
+	8041  ZXDH NEO X510 SRIOV VF Ethernet Controller Virtual Function
+	8042  ZXDH NX I512 VDPA VF Ethernet Controller Virtual Function
+	8044  ZXDH NEO X510 MPF Ethernet Controller
+	8045  ZXDH NX I512 BOND PF Ethernet Controller
+	8046  ZXDH NX I512 OVS PF Ethernet Controller
+	8047  ZXDH NEO X510 BOND PF Ethernet Controller
+	8048  ZXDH NEO X510 OVS PF Ethernet Controller
+	8049  ZXDH NX E312 SRIOV PF Ethernet Controller
+	8060  ZXDH NX E312 SRIOV VF Ethernet Controller Virtual Function
+	8061  ZXDH NX E310 SRIOV PF Ethernet Controller
+	8062  ZXDH NX E310 SRIOV VF Ethernet Controller Virtual Function
+	8063  ZXDH NX I510 BOND PF Ethernet Controller
+	8064  ZXDH NX I510 OVS PF Ethernet Controller
+	8065  ZXDH NX I510 VDPA VF Ethernet Controller Virtual Function
+	8066  ZXDH NX I511 BOND PF Ethernet Controller
+	8067  ZXDH NX I511 OVS PF Ethernet Controller
+	8068  ZXDH NX I511 VDPA VF Ethernet Controller Virtual Function
 
 
diff --git a/src/net/scripts/dtc/include-prefixes/arc b/src/net/scripts/dtc/include-prefixes/arc
new file mode 120000
index 0000000000000000000000000000000000000000..5d21b5a69a112a34750e919a9222a8f99c696036
--- /dev/null
+++ b/src/net/scripts/dtc/include-prefixes/arc
@@ -0,0 +1 @@
+../../../arch/arc/boot/dts
\ No newline at end of file
diff --git a/src/net/scripts/dtc/include-prefixes/arm b/src/net/scripts/dtc/include-prefixes/arm
new file mode 120000
index 0000000000000000000000000000000000000000..eb14d4515a57e9fba995487c1f3c9235086a9596
--- /dev/null
+++ b/src/net/scripts/dtc/include-prefixes/arm
@@ -0,0 +1 @@
+../../../arch/arm/boot/dts
\ No newline at end of file
diff --git a/src/net/scripts/dtc/include-prefixes/arm64 b/src/net/scripts/dtc/include-prefixes/arm64
new file mode 120000
index 0000000000000000000000000000000000000000..275c42c21d71c4cf2fd64df687c85a221129f059
--- /dev/null
+++ b/src/net/scripts/dtc/include-prefixes/arm64
@@ -0,0 +1 @@
+../../../arch/arm64/boot/dts
\ No newline at end of file
diff --git a/src/net/scripts/dtc/include-prefixes/c6x b/src/net/scripts/dtc/include-prefixes/c6x
new file mode 120000
index 0000000000000000000000000000000000000000..49ded4cae2be96e26b5184b7200019058a929dff
--- /dev/null
+++ b/src/net/scripts/dtc/include-prefixes/c6x
@@ -0,0 +1 @@
+../../../arch/c6x/boot/dts
\ No newline at end of file
diff --git a/src/net/scripts/dtc/include-prefixes/dt-bindings b/src/net/scripts/dtc/include-prefixes/dt-bindings
new file mode 120000
index 0000000000000000000000000000000000000000..04fdbb3af01630bbbc1931323981ef9a2482710b
--- /dev/null
+++ b/src/net/scripts/dtc/include-prefixes/dt-bindings
@@ -0,0 +1 @@
+../../../include/dt-bindings
\ No newline at end of file
diff --git a/src/net/scripts/dtc/include-prefixes/h8300 b/src/net/scripts/dtc/include-prefixes/h8300
new file mode 120000
index 0000000000000000000000000000000000000000..3bdaa332c54c7af4cb03841978822f5675e451d6
--- /dev/null
+++ b/src/net/scripts/dtc/include-prefixes/h8300
@@ -0,0 +1 @@
+../../../arch/h8300/boot/dts
\ No newline at end of file
diff --git a/src/net/scripts/dtc/include-prefixes/microblaze b/src/net/scripts/dtc/include-prefixes/microblaze
new file mode 120000
index 0000000000000000000000000000000000000000..d9830330a21d0916fb0df4315406abe137e59d24
--- /dev/null
+++ b/src/net/scripts/dtc/include-prefixes/microblaze
@@ -0,0 +1 @@
+../../../arch/microblaze/boot/dts
\ No newline at end of file
diff --git a/src/net/scripts/dtc/include-prefixes/mips b/src/net/scripts/dtc/include-prefixes/mips
new file mode 120000
index 0000000000000000000000000000000000000000..ae8d4948dc8d5a098cf70b1d07182a04b84dbe05
--- /dev/null
+++ b/src/net/scripts/dtc/include-prefixes/mips
@@ -0,0 +1 @@
+../../../arch/mips/boot/dts
\ No newline at end of file
diff --git a/src/net/scripts/dtc/include-prefixes/nios2 b/src/net/scripts/dtc/include-prefixes/nios2
new file mode 120000
index 0000000000000000000000000000000000000000..51772336d13fb3606011db9fd8b608aa016bf56f
--- /dev/null
+++ b/src/net/scripts/dtc/include-prefixes/nios2
@@ -0,0 +1 @@
+../../../arch/nios2/boot/dts
\ No newline at end of file
diff --git a/src/net/scripts/dtc/include-prefixes/openrisc b/src/net/scripts/dtc/include-prefixes/openrisc
new file mode 120000
index 0000000000000000000000000000000000000000..71c3bc75c560ac4697ee26e85f8b01994366112f
--- /dev/null
+++ b/src/net/scripts/dtc/include-prefixes/openrisc
@@ -0,0 +1 @@
+../../../arch/openrisc/boot/dts
\ No newline at end of file
diff --git a/src/net/scripts/dtc/include-prefixes/powerpc b/src/net/scripts/dtc/include-prefixes/powerpc
new file mode 120000
index 0000000000000000000000000000000000000000..7cd6ec16e899044c9fdbb991c8ef2d4ec594fc91
--- /dev/null
+++ b/src/net/scripts/dtc/include-prefixes/powerpc
@@ -0,0 +1 @@
+../../../arch/powerpc/boot/dts
\ No newline at end of file
diff --git a/src/net/scripts/dtc/include-prefixes/sh b/src/net/scripts/dtc/include-prefixes/sh
new file mode 120000
index 0000000000000000000000000000000000000000..67d37808c599dba0314822acc47f9ae2160adf5f
--- /dev/null
+++ b/src/net/scripts/dtc/include-prefixes/sh
@@ -0,0 +1 @@
+../../../arch/sh/boot/dts
\ No newline at end of file
diff --git a/src/net/scripts/dtc/include-prefixes/xtensa b/src/net/scripts/dtc/include-prefixes/xtensa
new file mode 120000
index 0000000000000000000000000000000000000000..d1eaf6ec7a2b9691d34ff2a01a3d589f945623bd
--- /dev/null
+++ b/src/net/scripts/dtc/include-prefixes/xtensa
@@ -0,0 +1 @@
+../../../arch/xtensa/boot/dts
\ No newline at end of file
diff --git a/src/net/smoke.sh b/src/net/smoke.sh
old mode 100755
new mode 100644
diff --git a/src/net/test_tools/zxdh_net_test.c b/src/net/test_tools/zxdh_net_test.c
index 2bfc08a9e8d163e9d29917124ed03645aad6221a..7cc1642c0409b4d729d80c8273054a1919d83f4b 100644
--- a/src/net/test_tools/zxdh_net_test.c
+++ b/src/net/test_tools/zxdh_net_test.c
@@ -1,496 +1,479 @@
 #include "zxdh_net_test.h"
 
-
-cmd_table_t CMD_TABLE[] =
-{
-    {"h",      HELP_CMD,     CMD_PARA_NUM_TWO,   zxdh_net_test_usage},
-    {"r",      GET_REG_CMD,  CMD_PARA_NUM_FIVE,  zxdh_get_reg},
-    {"w",      SET_REG_CMD,  CMD_PARA_NUM_FIVE,  zxdh_set_reg},
-    {"vring",  GET_VQ_INFO,  CMD_PARA_NUM_SIX,   zxdh_get_vring_info},
-    {"msgq_config",  SET_MSGQ_INFO,  CMD_PARA_NUM_FOUR,   zxdh_set_msgq_info},
-    {"msgq_send",  MSGQ_MSG_SEND,  CMD_PARA_NUM_FIVE,   zxdh_msgq_send_pkt},
-    {"send_file_pkt",  SEND_FILE_PKT,  CMD_PARA_NUM_THREE,  zxdh_send_file_pkt},
+cmd_table_t CMD_TABLE[] = {
+	{ "h", HELP_CMD, CMD_PARA_NUM_TWO, zxdh_net_test_usage },
+	{ "r", GET_REG_CMD, CMD_PARA_NUM_FIVE, zxdh_get_reg },
+	{ "w", SET_REG_CMD, CMD_PARA_NUM_FIVE, zxdh_set_reg },
+	{ "vring", GET_VQ_INFO, CMD_PARA_NUM_SIX, zxdh_get_vring_info },
+	{ "msgq_config", SET_MSGQ_INFO, CMD_PARA_NUM_FOUR, zxdh_set_msgq_info },
+	{ "msgq_send", MSGQ_MSG_SEND, CMD_PARA_NUM_FIVE, zxdh_msgq_send_pkt },
+	{ "send_file_pkt", SEND_FILE_PKT, CMD_PARA_NUM_THREE, zxdh_send_file_pkt },
 };
-#define CMD_NUM(table)  (sizeof(table) / sizeof(table[0]))
+#define CMD_NUM(table) (sizeof(table) / sizeof(table[0]))
 
 uint32_t htoi(int8_t *str)
 {
-    int32_t i = 0;
-    uint32_t n = 0;
-
-    if (NULL == str)
-    {
-        return ERR_INPUT_CMD_PARAMS;
-    }
-
-    if ((str[0] == '0') && (str[1] == 'x' || str[1] == 'X'))
-    {
-        i = 2;
-    }
-    else
-    {
-        i = 0;
-    }
-
-    for (; (str[i] >= '0' && str[i] <= '9') || (str[i] >= 'a' && str[i] <= 'f') || (str[i] >= 'A' && str[i] <= 'F'); ++i)
-    {
-        if (tolower(str[i]) > '9')
-        {
-            n = 16 * n + (10 + tolower(str[i]) - 'a');
-        }
-        else
-        {
-            n = 16 * n + (tolower(str[i]) - '0');
-        }
-    }
-    return n;
+	int32_t i = 0;
+	uint32_t n = 0;
+
+	if (NULL == str) {
+		return ERR_INPUT_CMD_PARAMS;
+	}
+
+	if ((str[0] == '0') && (str[1] == 'x' || str[1] == 'X')) {
+		i = 2;
+	} else {
+		i = 0;
+	}
+
+	for (; (str[i] >= '0' && str[i] <= '9') ||
+		   (str[i] >= 'a' && str[i] <= 'f') || (str[i] >= 'A' && str[i] <= 'F');
+		 ++i) {
+		if (tolower(str[i]) > '9') {
+			n = 16 * n + (10 + tolower(str[i]) - 'a');
+		} else {
+			n = 16 * n + (tolower(str[i]) - '0');
+		}
+	}
+	return n;
 }
 
-int32_t zxdh_net_test_usage(__attribute__((unused)) const int32_t skfd, __attribute__((unused)) const int8_t *ifrname,
-                            __attribute__((unused)) struct zxdh_en_reg *reg)
+int32_t zxdh_net_test_usage(__attribute__((unused)) const int32_t skfd,
+							__attribute__((unused)) const int8_t *ifrname,
+							__attribute__((unused)) struct zxdh_en_reg *reg)
 {
-    printf("\nUsage: zxdh_net_test\n"
-      "Version: 1.0\n"
-      "[zxdh_net_test options]\n"
-      "./zxdh_net_test h                                                   print usage\n"
-      "./zxdh_net_test netdev_name r addr_offset reg_num                   read the register\n"
-      "./zxdh_net_test netdev_name w addr_offset value                     write the register\n"
-      "./zxdh_net_test netdev_name vring queue desc_index desc_num         get the vring and desc_num desc informations from the desc_index\n"
-      "./zxdh_net_test netdev_name msgq_config loop_back print_data        config msgq para\n"
-      "./zxdh_net_test netdev_name msgq_send pkt_len no_reps send_cnt      msgq send pkt\n"
-      "./zxdh_net_test netdev_name send_file_pkt ./pkt.txt                 send packets with the specified packet contents including the self-defined header\n"
-      "\n");
-
-    return 0;
+	printf("\nUsage: zxdh_net_test\n"
+		   "Version: 1.0\n"
+		   "[zxdh_net_test options]\n"
+		   "./zxdh_net_test h                                                   "
+		   "print usage\n"
+		   "./zxdh_net_test netdev_name r addr_offset reg_num                   "
+		   "read the register\n"
+		   "./zxdh_net_test netdev_name w addr_offset value                     "
+		   "write the register\n"
+		   "./zxdh_net_test netdev_name vring queue desc_index desc_num         "
+		   "get the vring and desc_num desc informations from the desc_index\n"
+		   "./zxdh_net_test netdev_name msgq_config loop_back print_data        "
+		   "config msgq para\n"
+		   "./zxdh_net_test netdev_name msgq_send pkt_len no_reps send_cnt      "
+		   "msgq send pkt\n"
+		   "./zxdh_net_test netdev_name send_file_pkt ./pkt.txt                 "
+		   "send packets with the specified packet contents including the "
+		   "self-defined header\n"
+		   "\n");
+
+	return 0;
 }
 
-int32_t zxdh_get_reg(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg)
+int32_t zxdh_get_reg(const int32_t skfd, const int8_t *ifrname,
+					 struct zxdh_en_reg *reg)
 {
-    struct ifreq ifr;
-    int32_t i = 0;
-
-    memset(&ifr, 0, sizeof(struct ifreq));
-    strncpy(ifr.ifr_name, ifrname, IFNAMSIZ);
-    ifr.ifr_ifru.ifru_data = (void *)reg;
-
-    if ((reg->offset + reg->num * 4) >= MAX_IOMAP_RANGE)
-    {
-        fprintf(stdout, "the offset:%#x, num=%#x is out of pci io map range!\n", reg->offset, reg->num);
-        return ERR_IOMAP_RANGE;
-    }
-
-    if (ioctl(skfd, SIOCGMIIREG, &ifr) < 0)
-    {
-        fprintf(stderr, "SIOCGMIIREG on %s failed: %s\n", ifrname, strerror(errno));
-        return ERRCMD;
-    }
-
-    fprintf(stdout, "read register offset:%#x, num=%#x\n", reg->offset, reg->num);
-    for (i = 0; i < reg->num; i++)
-    {
-        fprintf(stdout, "0x%.8x: 0x%.8x  ", reg->offset + i * 4, reg->data[i]);
-        if(((i + 1) % 4) == 0)
-        {
-            fprintf(stdout, "\n");
-        }
-    }
-    fprintf(stdout, "\n");
-
-    return 0;
+	struct ifreq ifr;
+	int32_t i = 0;
+
+	memset(&ifr, 0, sizeof(struct ifreq));
+	strncpy(ifr.ifr_name, ifrname, IFNAMSIZ);
+	ifr.ifr_ifru.ifru_data = (void *)reg;
+
+	if ((reg->offset + reg->num * 4) >= MAX_IOMAP_RANGE) {
+		fprintf(stdout, "the offset:%#x, num=%#x is out of pci io map range!\n",
+				reg->offset, reg->num);
+		return ERR_IOMAP_RANGE;
+	}
+
+	if (ioctl(skfd, SIOCGMIIREG, &ifr) < 0) {
+		fprintf(stderr, "SIOCGMIIREG on %s failed: %s\n", ifrname,
+				strerror(errno));
+		return ERRCMD;
+	}
+
+	fprintf(stdout, "read register offset:%#x, num=%#x\n", reg->offset,
+			reg->num);
+	for (i = 0; i < reg->num; i++) {
+		fprintf(stdout, "0x%.8x: 0x%.8x  ", reg->offset + i * 4, reg->data[i]);
+		if (((i + 1) % 4) == 0) {
+			fprintf(stdout, "\n");
+		}
+	}
+	fprintf(stdout, "\n");
+
+	return 0;
 }
 
-int32_t zxdh_set_reg(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg)
+int32_t zxdh_set_reg(const int32_t skfd, const int8_t *ifrname,
+					 struct zxdh_en_reg *reg)
 {
-    struct ifreq ifr;
-    int32_t i = 0;
-
-    memset(&ifr, 0, sizeof(struct ifreq));
-    strncpy(ifr.ifr_name, ifrname, IFNAMSIZ);
-    ifr.ifr_ifru.ifru_data = (void *)reg;
-
-    if ((reg->offset + reg->num * 4) >= MAX_IOMAP_RANGE)
-    {
-        fprintf(stderr, "the offset:%#x, num=%#x is out of pci io map range!\n", reg->offset, reg->num);
-        return ERR_IOMAP_RANGE;
-    }
-
-    if (ioctl(skfd, SIOCSMIIREG, &ifr) < 0)
-    {
-        fprintf(stderr, "SIOCSMIIREG on %s failed: %s\n", ifrname, strerror(errno));
-        return ERRCMD;
-    }
-
-    fprintf(stdout, "write register offset:%#x, num=%#x\n", reg->offset, reg->num);
-    for (i = 0; i < reg->num; i++)
-    {
-        if(((i + 1) % 4) == 0)
-        {
-            fprintf(stdout, "\n");
-        }
-        fprintf(stdout, "0x%.8x: 0x%.8x  ", reg->offset + i * 4, reg->data[i]);
-    }
-    fprintf(stdout, "\n");
-
-    return 0;
+	struct ifreq ifr;
+	int32_t i = 0;
+
+	memset(&ifr, 0, sizeof(struct ifreq));
+	strncpy(ifr.ifr_name, ifrname, IFNAMSIZ);
+	ifr.ifr_ifru.ifru_data = (void *)reg;
+
+	if ((reg->offset + reg->num * 4) >= MAX_IOMAP_RANGE) {
+		fprintf(stderr, "the offset:%#x, num=%#x is out of pci io map range!\n",
+				reg->offset, reg->num);
+		return ERR_IOMAP_RANGE;
+	}
+
+	if (ioctl(skfd, SIOCSMIIREG, &ifr) < 0) {
+		fprintf(stderr, "SIOCSMIIREG on %s failed: %s\n", ifrname,
+				strerror(errno));
+		return ERRCMD;
+	}
+
+	fprintf(stdout, "write register offset:%#x, num=%#x\n", reg->offset,
+			reg->num);
+	for (i = 0; i < reg->num; i++) {
+		if (((i + 1) % 4) == 0) {
+			fprintf(stdout, "\n");
+		}
+		fprintf(stdout, "0x%.8x: 0x%.8x  ", reg->offset + i * 4, reg->data[i]);
+	}
+	fprintf(stdout, "\n");
+
+	return 0;
 }
 
-int32_t zxdh_get_vring_info(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg)
+int32_t zxdh_get_vring_info(const int32_t skfd, const int8_t *ifrname,
+							struct zxdh_en_reg *reg)
 {
-    struct ifreq ifr;
+	struct ifreq ifr;
 
-    memset(&ifr, 0, sizeof(struct ifreq));
-    strncpy(ifr.ifr_name, ifrname, IFNAMSIZ);
-    ifr.ifr_ifru.ifru_data = (void *)reg;
+	memset(&ifr, 0, sizeof(struct ifreq));
+	strncpy(ifr.ifr_name, ifrname, IFNAMSIZ);
+	ifr.ifr_ifru.ifru_data = (void *)reg;
 
-    if (ioctl(skfd, SIOCDEVPRIVATE_VQ_INFO, &ifr) < 0)
-    {
-        fprintf(stderr, "SIOCDEVPRIVATE_VQ_INFO on %s failed: %s\n", ifrname, strerror(errno));
-        return ERRCMD;
-    }
+	if (ioctl(skfd, SIOCDEVPRIVATE_VQ_INFO, &ifr) < 0) {
+		fprintf(stderr, "SIOCDEVPRIVATE_VQ_INFO on %s failed: %s\n", ifrname,
+				strerror(errno));
+		return ERRCMD;
+	}
 
-    return 0;
+	return 0;
 }
 
-int32_t zxdh_set_msgq_info(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg)
+int32_t zxdh_set_msgq_info(const int32_t skfd, const int8_t *ifrname,
+						   struct zxdh_en_reg *reg)
 {
-    struct ifreq ifr;
-    int32_t i = 0;
+	struct ifreq ifr;
+	int32_t i = 0;
 
-    memset(&ifr, 0, sizeof(struct ifreq));
-    strncpy(ifr.ifr_name, ifrname, IFNAMSIZ);
-    ifr.ifr_ifru.ifru_data = (void *)reg;
+	memset(&ifr, 0, sizeof(struct ifreq));
+	strncpy(ifr.ifr_name, ifrname, IFNAMSIZ);
+	ifr.ifr_ifru.ifru_data = (void *)reg;
 
-    if (ioctl(skfd, SIOCDEVPRIVATE_MSGQ_CONFIG, &ifr) < 0)
-    {
-        fprintf(stderr, "SIOCDEVPRIVATE_MSGQ_CONFIG on %s failed: %s\n", ifrname, strerror(errno));
-        return ERRCMD;
-    }
+	if (ioctl(skfd, SIOCDEVPRIVATE_MSGQ_CONFIG, &ifr) < 0) {
+		fprintf(stderr, "SIOCDEVPRIVATE_MSGQ_CONFIG on %s failed: %s\n",
+				ifrname, strerror(errno));
+		return ERRCMD;
+	}
 
-    fprintf(stdout, "set msgq loop_back:%d\n", reg->data[0]);
-    fprintf(stdout, "set msgq print_flag:%d\n", reg->data[1]);
+	fprintf(stdout, "set msgq loop_back:%d\n", reg->data[0]);
+	fprintf(stdout, "set msgq print_flag:%d\n", reg->data[1]);
 
-    return 0;
+	return 0;
 }
 
-int32_t zxdh_msgq_send_pkt(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg)
+int32_t zxdh_msgq_send_pkt(const int32_t skfd, const int8_t *ifrname,
+						   struct zxdh_en_reg *reg)
 {
-    struct ifreq ifr;
-    int32_t i = 0;
+	struct ifreq ifr;
+	int32_t i = 0;
 
-    memset(&ifr, 0, sizeof(struct ifreq));
-    strncpy(ifr.ifr_name, ifrname, IFNAMSIZ);
-    ifr.ifr_ifru.ifru_data = (void *)reg;
+	memset(&ifr, 0, sizeof(struct ifreq));
+	strncpy(ifr.ifr_name, ifrname, IFNAMSIZ);
+	ifr.ifr_ifru.ifru_data = (void *)reg;
 
-    if (ioctl(skfd, SIOCDEVPRIVATE_MSGQ_SNED, &ifr) < 0)
-    {
-        fprintf(stderr, "SIOCDEVPRIVATE_MSGQ_SNED on %s failed: %s\n", ifrname, strerror(errno));
-        return ERRCMD;
-    }
+	if (ioctl(skfd, SIOCDEVPRIVATE_MSGQ_SNED, &ifr) < 0) {
+		fprintf(stderr, "SIOCDEVPRIVATE_MSGQ_SNED on %s failed: %s\n", ifrname,
+				strerror(errno));
+		return ERRCMD;
+	}
 
-    return -reg->num;
+	return reg->num;
 }
 
-int32_t zxdh_send_file_pkt(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg)
+int32_t zxdh_send_file_pkt(const int32_t skfd, const int8_t *ifrname,
+						   struct zxdh_en_reg *reg)
 {
-    struct ifreq ifr;
+	struct ifreq ifr;
 
-    memset(&ifr, 0, sizeof(struct ifreq));
-    strncpy(ifr.ifr_name, ifrname, IFNAMSIZ);
-    ifr.ifr_ifru.ifru_data = (void *)reg;
+	memset(&ifr, 0, sizeof(struct ifreq));
+	strncpy(ifr.ifr_name, ifrname, IFNAMSIZ);
+	ifr.ifr_ifru.ifru_data = (void *)reg;
 
-    if (ioctl(skfd, SIOCDEVPRIVATE_SEND_FILE_PKT, &ifr) < 0)
-    {
-        fprintf(stderr, "SIOCDEVPRIVATE_SEND_FILE_PKT on %s failed: %s\n", ifrname, strerror(errno));
-        return ERRCMD;
-    }
+	if (ioctl(skfd, SIOCDEVPRIVATE_SEND_FILE_PKT, &ifr) < 0) {
+		fprintf(stderr, "SIOCDEVPRIVATE_SEND_FILE_PKT on %s failed: %s\n",
+				ifrname, strerror(errno));
+		return ERRCMD;
+	}
 
-    fprintf(stdout, "try to send file packets success\n");
+	fprintf(stdout, "try to send file packets success\n");
 
-    return 0;
+	return 0;
 }
 
 bool is_cmd_valid(const int32_t cmd)
 {
-    if ((cmd < MIN_CMD) || (cmd > MAX_CMD))
-    {
-        return false;
-    }
-    return true;
+	if ((cmd < MIN_CMD) || (cmd > MAX_CMD)) {
+		return false;
+	}
+	return true;
 }
 
 int32_t get_cmd(int8_t *cmd_argv)
 {
-    int32_t cmd = 0;
-    int32_t i = 0;
-
-    for (i = 0; i < CMD_NUM(CMD_TABLE); i++)
-    {
-        if (cmd_argv == NULL)
-        {
-            cmd = CMD_TABLE[i].cmd;
-            return cmd;
-        }
-
-        if (strcmp(cmd_argv, CMD_TABLE[i].argv) == 0)
-        {
-            cmd = CMD_TABLE[i].cmd;
-        }
-    }
-    return cmd;
+	int32_t cmd = 0;
+	int32_t i = 0;
+
+	for (i = 0; i < CMD_NUM(CMD_TABLE); i++) {
+		if (cmd_argv == NULL) {
+			cmd = CMD_TABLE[i].cmd;
+			return cmd;
+		}
+
+		if (strcmp(cmd_argv, CMD_TABLE[i].argv) == 0) {
+			cmd = CMD_TABLE[i].cmd;
+		}
+	}
+	return cmd;
 }
 
 int32_t check_cmd_para_num(const int32_t cmd, const int32_t para_num)
 {
-    int32_t cmd_para_num = 0;
-    int32_t i = 0;
-
-    for (i = 0; i < CMD_NUM(CMD_TABLE); i++)
-    {
-        if (CMD_TABLE[i].cmd == cmd)
-        {
-            cmd_para_num = CMD_TABLE[i].para_num;
-            break;
-        }
-    }
-
-    if (para_num < cmd_para_num)
-    {
-        fprintf(stderr, "cmd %d need para_num =%d, but %d paras input is given!\n", cmd, cmd_para_num, para_num);
-        return ERRCMD;
-    }
-    return 0;
+	int32_t cmd_para_num = 0;
+	int32_t i = 0;
+
+	for (i = 0; i < CMD_NUM(CMD_TABLE); i++) {
+		if (CMD_TABLE[i].cmd == cmd) {
+			cmd_para_num = CMD_TABLE[i].para_num;
+			break;
+		}
+	}
+
+	if (para_num < cmd_para_num) {
+		fprintf(stderr,
+				"cmd %d need para_num =%d, but %d paras input is given!\n", cmd,
+				cmd_para_num, para_num);
+		return ERRCMD;
+	}
+	return 0;
 }
 
 int32_t get_reg_cmd_para(int8_t **argv, struct zxdh_en_reg *reg)
 {
-    reg->offset = htoi(argv[3]);
-    reg->num = (uint32_t)atoi(argv[4]);
+	reg->offset = htoi(argv[3]);
+	reg->num = (uint32_t)atoi(argv[4]);
 
-    return 0;
+	return 0;
 }
 
 int32_t set_reg_cmd_para(int8_t **argv, struct zxdh_en_reg *reg)
 {
-    int32_t i = 0;
+	int32_t i = 0;
 
-    reg->offset = htoi(argv[3]);
-    reg->num = (uint32_t)atoi(argv[4]);
+	reg->offset = htoi(argv[3]);
+	reg->num = (uint32_t)atoi(argv[4]);
 
-    while ((i < reg->num) && argv[5 + i])
-    {
-        reg->data[i] = htoi(argv[5 + i]);
-        i++;
-    }
+	while ((i < reg->num) && argv[5 + i]) {
+		reg->data[i] = htoi(argv[5 + i]);
+		i++;
+	}
 
-    return 0;
+	return 0;
 }
 
 int32_t get_vring_info_cmd_para(int8_t **argv, struct zxdh_en_reg *reg)
 {
-    reg->offset = (uint32_t)atoi(argv[3]);
-    reg->num = (uint32_t)atoi(argv[4]);
-    reg->data[0] = (uint32_t)atoi(argv[5]);
+	reg->offset = (uint32_t)atoi(argv[3]);
+	reg->num = (uint32_t)atoi(argv[4]);
+	reg->data[0] = (uint32_t)atoi(argv[5]);
 
-    return 0;
+	return 0;
 }
 
 int32_t set_msgq_info_para(int8_t **argv, struct zxdh_en_reg *reg)
 {
-    reg->data[0] = (uint32_t)atoi(argv[3]);
-    reg->data[1] = (uint32_t)atoi(argv[4]);
-    return 0;
+	reg->data[0] = (uint32_t)atoi(argv[3]);
+	reg->data[1] = (uint32_t)atoi(argv[4]);
+	return 0;
 }
 
 int32_t msgq_msg_send_para(int8_t **argv, struct zxdh_en_reg *reg)
 {
-    reg->data[0] = (uint32_t)atoi(argv[3]);
-    reg->data[1] = (uint32_t)atoi(argv[4]);
-    reg->data[2] = (uint32_t)atoi(argv[5]);
-    return 0;
+	reg->data[0] = (uint32_t)atoi(argv[3]);
+	reg->data[1] = (uint32_t)atoi(argv[4]);
+	reg->data[2] = (uint32_t)atoi(argv[5]);
+	return 0;
 }
 
 uint32_t delet_str_spec(uint8_t *pstr, uint32_t len)
 {
-    uint16_t i = 0;
-    uint16_t j = 0;
-    uint8_t *buf = pstr;
-
-    for (i = 0; i < len; i++)
-    {
-        if (pstr[i] == '\0')
-        {
-            break;
-        }
-
-        if ((pstr[i] != ' ') && (pstr[i] != '\n'))
-        {
-            *(buf + j) = pstr[i];
-            j++;
-        }
-    }
-    if (j < i)
-    {
-        memset(buf + j, 0, (i - j));
-    }
-
-    return j;
+	uint16_t i = 0;
+	uint16_t j = 0;
+	uint8_t *buf = pstr;
+
+	for (i = 0; i < len; i++) {
+		if (pstr[i] == '\0') {
+			break;
+		}
+
+		if ((pstr[i] != ' ') && (pstr[i] != '\n')) {
+			*(buf + j) = pstr[i];
+			j++;
+		}
+	}
+	if (j < i) {
+		memset(buf + j, 0, (i - j));
+	}
+
+	return j;
 }
 
 uint32_t hexstr_to_data(uint8_t *pstr, uint32_t len, uint32_t *data)
 {
-    int8_t hexbuf[3] = {0};
-    uint32_t i = 0;
-    uint32_t loop = 0;
-
-    if (len % 2)
-    {
-        len -= 1;
-    }
-    loop = len / 2;
-    for (i = 0; i < loop; i++)
-    {
-        memset(hexbuf, 0, sizeof(hexbuf));
-        memcpy(hexbuf, &pstr[2*i], 2);
-        data[i] = htoi(hexbuf);
-        fprintf(stdout, "%.2x ", data[i]);
-    }
-    fprintf(stdout, "\n");
-
-    return i;
+	int8_t hexbuf[3] = { 0 };
+	uint32_t i = 0;
+	uint32_t loop = 0;
+
+	if (len % 2) {
+		len -= 1;
+	}
+	loop = len / 2;
+	for (i = 0; i < loop; i++) {
+		memset(hexbuf, 0, sizeof(hexbuf));
+		memcpy(hexbuf, &pstr[2 * i], 2);
+		data[i] = htoi(hexbuf);
+		fprintf(stdout, "%.2x ", data[i]);
+	}
+	fprintf(stdout, "\n");
+
+	return i;
 }
 
 int32_t get_para_from_file(int8_t **argv, struct zxdh_en_reg *reg)
 {
-    int8_t filename[100] = {0};
-    int8_t buf[1000] = {0};
-    int32_t i = 0;
-    FILE *f = NULL;
-    uint32_t len = 0;
-
-    strncpy(filename, argv[3], strlen(argv[3]));
-    filename[strlen(argv[3])] = '\0';
-    if ((f = fopen(filename, "r")) == NULL)
-    {
-        fprintf(stdout, "get_para_from_file: cannot open %s\n", filename);
-        return ERR_INPUT_CMD_PARAMS;
-    }
-    memset(reg, 0, sizeof(struct zxdh_en_reg));
-
-    fprintf(stdout, "read file pkt:\n");
-    while (fgets(buf, sizeof(buf), f) != NULL)
-    {
-        if ((buf[0] != '\n') && (buf[0] != '#'))
-        {
-            len = delet_str_spec(buf, strlen(buf));
-            reg->num += hexstr_to_data(buf, len, (uint32_t *)&reg->data[reg->num]);
-        }
-    }
-    fprintf(stdout, "pkt len: %d\n\n", reg->num);
-
-    fclose(f);
-
-    return 0;
+	int8_t filename[100] = { 0 };
+	int8_t buf[1000] = { 0 };
+	int32_t i = 0;
+	FILE *f = NULL;
+	uint32_t len = 0;
+
+	strncpy(filename, argv[3], strlen(argv[3]));
+	filename[strlen(argv[3])] = '\0';
+	f = fopen(filename, "r");
+	if (f == NULL) {
+		fprintf(stdout, "get_para_from_file: cannot open %s\n", filename);
+		return ERR_INPUT_CMD_PARAMS;
+	}
+	memset(reg, 0, sizeof(struct zxdh_en_reg));
+
+	fprintf(stdout, "read file pkt:\n");
+	while (fgets(buf, sizeof(buf), f) != NULL) {
+		if ((buf[0] != '\n') && (buf[0] != '#')) {
+			len = delet_str_spec(buf, strlen(buf));
+			reg->num +=
+					hexstr_to_data(buf, len, (uint32_t *)&reg->data[reg->num]);
+		}
+	}
+	fprintf(stdout, "pkt len: %d\n\n", reg->num);
+
+	fclose(f);
+
+	return 0;
 }
 
-struct get_cmd_para_table cmd_para_table[] =
-{
-    {HELP_CMD,     NULL},
-    {GET_REG_CMD,  get_reg_cmd_para},
-    {SET_REG_CMD,  set_reg_cmd_para},
-    {GET_VQ_INFO,  get_vring_info_cmd_para},
-    {SET_MSGQ_INFO,  set_msgq_info_para},
-    {MSGQ_MSG_SEND,  msgq_msg_send_para},
-    {SEND_FILE_PKT,  get_para_from_file},
+struct get_cmd_para_table cmd_para_table[] = {
+	{ HELP_CMD, NULL },
+	{ GET_REG_CMD, get_reg_cmd_para },
+	{ SET_REG_CMD, set_reg_cmd_para },
+	{ GET_VQ_INFO, get_vring_info_cmd_para },
+	{ SET_MSGQ_INFO, set_msgq_info_para },
+	{ MSGQ_MSG_SEND, msgq_msg_send_para },
+	{ SEND_FILE_PKT, get_para_from_file },
 };
 
 int32_t get_cmd_para(const int32_t cmd, int8_t **argv, struct zxdh_en_reg *reg)
 {
-    int32_t i = 0;
-    int32_t ret = 0;
-
-    if (NULL == argv)
-    {
-        fprintf(stdout, "%s %d pointer is null!\n", __FUNCTION__, __LINE__);
-        return ERR_INPUT_CMD_PARAMS;
-    }
-
-    memset((void *)reg, 0, sizeof(struct zxdh_en_reg));
-    for (i = 0; i < CMD_NUM(cmd_para_table); i++)
-    {
-        if ((cmd == cmd_para_table[i].cmd) && (cmd_para_table[i].func))
-        {
-            ret = cmd_para_table[i].func(argv, reg);
-        }
-    }
-
-    return ret;
+	int32_t i = 0;
+	int32_t ret = 0;
+
+	if (NULL == argv) {
+		fprintf(stdout, "%s %d pointer is null!\n", __FUNCTION__, __LINE__);
+		return ERR_INPUT_CMD_PARAMS;
+	}
+
+	memset((void *)reg, 0, sizeof(struct zxdh_en_reg));
+	for (i = 0; i < CMD_NUM(cmd_para_table); i++) {
+		if ((cmd == cmd_para_table[i].cmd) && (cmd_para_table[i].func)) {
+			ret = cmd_para_table[i].func(argv, reg);
+		}
+	}
+
+	return ret;
 }
 
-int32_t get_cmd_and_para(const int32_t argc, int8_t **argv, int8_t *ifrname, struct zxdh_en_reg *reg)
+int32_t get_cmd_and_para(const int32_t argc, int8_t **argv, int8_t *ifrname,
+						 struct zxdh_en_reg *reg)
 {
-    int32_t cmd = 0;
-    int32_t ret = 0;
-
-    cmd = get_cmd(argv[2]);
-    fprintf(stdout, "cmd = %d\n", cmd);
-
-    if (!is_cmd_valid(cmd))
-    {
-        fprintf(stderr, "cmd %d invalid\n", cmd);
-        return ERRCMD;
-    }
-
-    if (check_cmd_para_num(cmd, argc) < 0)
-    {
-        fprintf(stderr, "para num check failed!\n");
-        return ERRCMD;
-    }
-
-    ifrname = argv[1];
-    ret = get_cmd_para(cmd, argv, reg);
-    if (ret < 0)
-    {
-        fprintf(stderr, "get detail cmd para failed, ret %d!\n", ret);
-        return ERRCMD;
-    }
-
-    return cmd;
+	int32_t cmd = 0;
+	int32_t ret = 0;
+
+	cmd = get_cmd(argv[2]);
+	fprintf(stdout, "cmd = %d\n", cmd);
+
+	if (!is_cmd_valid(cmd)) {
+		fprintf(stderr, "cmd %d invalid\n", cmd);
+		return ERRCMD;
+	}
+
+	if (check_cmd_para_num(cmd, argc) < 0) {
+		fprintf(stderr, "para num check failed!\n");
+		return ERRCMD;
+	}
+
+	ifrname = argv[1];
+	ret = get_cmd_para(cmd, argv, reg);
+	if (ret < 0) {
+		fprintf(stderr, "get detail cmd para failed, ret %d!\n", ret);
+		return ERRCMD;
+	}
+
+	return cmd;
 }
 
 int32_t main(int32_t argc, int8_t **argv)
 {
-    int8_t *ifrname = NULL;
-    int32_t skfd = -1;
-    int32_t ret = 0;
-    int32_t cmd = 0;
-    uint32_t num = 0;
-    uint32_t i = 0;
-    struct zxdh_en_reg reg = {0};
-
-    for (num = 0; num < argc; num++)
-    {
-        fprintf(stdout, "argv[%d]: %s\n", num, argv[num]);
-    }
-
-    memset(&reg, 0, sizeof(struct zxdh_en_reg));
-    ifrname = argv[1];
-    cmd = get_cmd_and_para(argc, argv, ifrname, &reg);
-
-    if ((skfd = socket(AF_INET, SOCK_DGRAM, 0)) < 0 )
-    {
-        fprintf(stderr, "socket error\n");
-        return ERR_SOCKET;
-    }
-
-    for (i = 0; i < CMD_NUM(CMD_TABLE); i++)
-    {
-        if ((cmd == CMD_TABLE[i].cmd) && (CMD_TABLE[i].func))
-        {
-            ret = CMD_TABLE[i].func(skfd, ifrname, &reg);
-        }
-    }
-
-    close(skfd);
-    fprintf(stdout, "ret=%d\n", ret);
-    return ret;
+	int8_t *ifrname = NULL;
+	int32_t skfd = -1;
+	int32_t ret = 0;
+	int32_t cmd = 0;
+	uint32_t num = 0;
+	uint32_t i = 0;
+	struct zxdh_en_reg reg = { 0 };
+
+	for (num = 0; num < argc; num++) {
+		fprintf(stdout, "argv[%d]: %s\n", num, argv[num]);
+	}
+
+	memset(&reg, 0, sizeof(struct zxdh_en_reg));
+	ifrname = argv[1];
+	cmd = get_cmd_and_para(argc, argv, ifrname, &reg);
+
+	skfd = socket(AF_INET, SOCK_DGRAM, 0);
+	if (skfd < 0) {
+		fprintf(stderr, "socket error\n");
+		return ERR_SOCKET;
+	}
+
+	for (i = 0; i < CMD_NUM(CMD_TABLE); i++) {
+		if ((cmd == CMD_TABLE[i].cmd) && (CMD_TABLE[i].func)) {
+			ret = CMD_TABLE[i].func(skfd, ifrname, &reg);
+		}
+	}
+
+	close(skfd);
+	fprintf(stdout, "ret=%d\n", ret);
+	return ret;
 }
diff --git a/src/net/test_tools/zxdh_net_test.h b/src/net/test_tools/zxdh_net_test.h
index d71695904cca71aa82497fa83c1667a56b8b182d..a0da1b002002e25664880f327543577a2329607f 100644
--- a/src/net/test_tools/zxdh_net_test.h
+++ b/src/net/test_tools/zxdh_net_test.h
@@ -1,11 +1,10 @@
-#ifndef  _ZXDH_NET_TEST_
-#define  _ZXDH_NET_TEST_
+#ifndef _ZXDH_NET_TEST_
+#define _ZXDH_NET_TEST_
 
 #ifdef __cplusplus
-    extern "C" {
+extern "C" {
 #endif /* __cplusplus */
 
-
 #include <stdio.h>
 #include <stdint.h>
 #include <stdbool.h>
@@ -27,71 +26,74 @@
 #include <dirent.h>
 #include <ctype.h>
 
-
 /* command */
-#define ERRCMD                 (-1)
-#define MIN_CMD                0
-#define MAX_CMD                6
-#define HELP_CMD               MIN_CMD
-#define GET_REG_CMD            1
-#define SET_REG_CMD            2
-#define GET_VQ_INFO            3
-#define SET_MSGQ_INFO          4
-#define MSGQ_MSG_SEND          5
-#define SEND_FILE_PKT          MAX_CMD
-
-#define MAX_IOMAP_RANGE        (256 * 1024)
-
-#define ERR_SOCKET             (-1)
-#define ERR_IOMAP_RANGE        (-3)
-#define ERR_INPUT_CMD_PARAMS   (-4)
-
-#define CMD_PARA_NUM_TWO        2
-#define CMD_PARA_NUM_THREE      3
-#define CMD_PARA_NUM_FOUR       4
-#define CMD_PARA_NUM_FIVE       5
-#define CMD_PARA_NUM_SIX        6
-#define CMD_PARA_NUM_EIGHT      8
-#define CMD_PARA_NUM_NINE       9
-
-#define SIOCDEVPRIVATE_VQ_INFO    (SIOCDEVPRIVATE + 2)
-#define SIOCDEVPRIVATE_MSGQ_SNED  (SIOCDEVPRIVATE + 3)
-#define SIOCDEVPRIVATE_MSGQ_CONFIG  (SIOCDEVPRIVATE + 4)
-#define SIOCDEVPRIVATE_SEND_FILE_PKT   (SIOCDEVPRIVATE + 6)
+#define ERRCMD (-1)
+#define MIN_CMD 0
+#define MAX_CMD 6
+#define HELP_CMD MIN_CMD
+#define GET_REG_CMD 1
+#define SET_REG_CMD 2
+#define GET_VQ_INFO 3
+#define SET_MSGQ_INFO 4
+#define MSGQ_MSG_SEND 5
+#define SEND_FILE_PKT MAX_CMD
+
+#define MAX_IOMAP_RANGE (256 * 1024)
+
+#define ERR_SOCKET (-1)
+#define ERR_IOMAP_RANGE (-3)
+#define ERR_INPUT_CMD_PARAMS (-4)
+
+#define CMD_PARA_NUM_TWO 2
+#define CMD_PARA_NUM_THREE 3
+#define CMD_PARA_NUM_FOUR 4
+#define CMD_PARA_NUM_FIVE 5
+#define CMD_PARA_NUM_SIX 6
+#define CMD_PARA_NUM_EIGHT 8
+#define CMD_PARA_NUM_NINE 9
+
+#define SIOCDEVPRIVATE_VQ_INFO (SIOCDEVPRIVATE + 2)
+#define SIOCDEVPRIVATE_MSGQ_SNED (SIOCDEVPRIVATE + 3)
+#define SIOCDEVPRIVATE_MSGQ_CONFIG (SIOCDEVPRIVATE + 4)
+#define SIOCDEVPRIVATE_SEND_FILE_PKT (SIOCDEVPRIVATE + 6)
 
 #define MAX_ACCESS_NUM 500
-struct zxdh_en_reg
-{
-    uint32_t offset;
-    uint32_t num;
-    uint32_t data[MAX_ACCESS_NUM];
+struct zxdh_en_reg {
+	uint32_t offset;
+	uint32_t num;
+	uint32_t data[MAX_ACCESS_NUM];
 };
 
-typedef int32_t (*function)(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg);
+typedef int32_t (*function)(const int32_t skfd, const int8_t *ifrname,
+							struct zxdh_en_reg *reg);
 
-typedef struct
-{
-    int8_t *argv;
-    int32_t cmd;
-    int32_t para_num;
-    function func;
-}cmd_table_t;
+typedef struct {
+	int8_t *argv;
+	int32_t cmd;
+	int32_t para_num;
+	function func;
+} cmd_table_t;
 
-struct get_cmd_para_table
-{
-    int32_t cmd;
-    int32_t (*func)(int8_t **argv, struct zxdh_en_reg *reg);
+struct get_cmd_para_table {
+	int32_t cmd;
+	int32_t (*func)(int8_t **argv, struct zxdh_en_reg *reg);
 };
 
-int32_t zxdh_net_test_usage(__attribute__((unused)) const int32_t skfd, __attribute__((unused)) const int8_t *ifrname,
-                            __attribute__((unused)) struct zxdh_en_reg *reg);
-int32_t zxdh_get_reg(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg);
-int32_t zxdh_set_reg(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg);
-int32_t zxdh_get_vring_info(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg);
-int32_t zxdh_set_msgq_info(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg);
-int32_t zxdh_msgq_send_pkt(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg);
-int32_t zxdh_send_file_pkt(const int32_t skfd, const int8_t *ifrname, struct zxdh_en_reg *reg);
-
+int32_t zxdh_net_test_usage(__attribute__((unused)) const int32_t skfd,
+							__attribute__((unused)) const int8_t *ifrname,
+							__attribute__((unused)) struct zxdh_en_reg *reg);
+int32_t zxdh_get_reg(const int32_t skfd, const int8_t *ifrname,
+					 struct zxdh_en_reg *reg);
+int32_t zxdh_set_reg(const int32_t skfd, const int8_t *ifrname,
+					 struct zxdh_en_reg *reg);
+int32_t zxdh_get_vring_info(const int32_t skfd, const int8_t *ifrname,
+							struct zxdh_en_reg *reg);
+int32_t zxdh_set_msgq_info(const int32_t skfd, const int8_t *ifrname,
+						   struct zxdh_en_reg *reg);
+int32_t zxdh_msgq_send_pkt(const int32_t skfd, const int8_t *ifrname,
+						   struct zxdh_en_reg *reg);
+int32_t zxdh_send_file_pkt(const int32_t skfd, const int8_t *ifrname,
+						   struct zxdh_en_reg *reg);
 
 #ifdef __cplusplus
 }
diff --git a/src/net/upload.sh b/src/net/upload.sh
old mode 100755
new mode 100644
diff --git a/src/net/ut.sh b/src/net/ut.sh
old mode 100755
new mode 100644
diff --git a/src/net/zxdh_eth_rpm_build.sh b/src/net/zxdh_eth_rpm_build.sh
index ae96d6716bba0c65f811f283e304d6498c0b4c7f..4ba32d96272151cda959135e1f2c2c29abf06c0e 100755
--- a/src/net/zxdh_eth_rpm_build.sh
+++ b/src/net/zxdh_eth_rpm_build.sh
@@ -13,7 +13,6 @@ Usage:
                  --rpm-config-name <config_name> [ zxdh-smartnic-config | zxdh-dpu-config ]
                  --rpm-config-version <config_version>
                  --rpm-config-release <config_release>
-                 --eth-driver-version <eth_driver_version>
                  --ksrc <kernel_source_path>
                  --cross-compile <cross_compile_path>
                  --target-arch <target_arch> [ x86_64 | aarch64 ]
@@ -27,7 +26,6 @@ Options:
     --rpm-config-name      <config_name>          Set rpm config name              (default: zxdh-smartnic-config)
     --rpm-config-version   <config_version>       Set rpm config version           (default: 1.0)
     --rpm-config-release   <config_release>       Set rpm config release           (default: 1)
-    --eth-driver-version   <eth_driver_version>   Set eth driver version           (default: 1.0-0)
     --ksrc                 <kernel_source>        Set kernel source path           (default: /lib/modules/$(uname -r)/source)
     --cross-compile        <cross_compile_path>   Set cross compile tools path     (default(Don't cross compile): None)
     --target-arch          <traget_arch>          Set the target arch              (default(current arch): $(uname -m))
@@ -50,7 +48,7 @@ kernel dist:          $dist
 host arch:            $host_arch
 target arch:          $target_arch_info
 cross compile:        $cross_compile_info
-eth driver version:   $eth_driver_version
+aux bus info:         $need_aux_bus_info
 **********************************************
 rpm dirver name:      $rpm_driver_name
 rpm driver version:   $rpm_driver_version
@@ -104,10 +102,6 @@ do
 		rpm_config_release="$2"
 		shift
 		;;
-		--eth-driver-version)
-		eth_driver_version="$2"
-		shift
-		;;
 		--ksrc)
 		ksrc="$2"
 		shift
@@ -163,9 +157,6 @@ fi
 if [ -z "$rpm_config_release" ]; then
 	rpm_config_release="1"
 fi
-if [ -z "$eth_driver_version" ]; then
-	eth_driver_version="1.0-1"
-fi
 if [ -z "$ksrc" ]; then
 	ksrc="/lib/modules/$(uname -r)/source"
 fi
@@ -195,6 +186,22 @@ if [ ! -d $output_dir ]; then
 	fi
 fi
 
+if [ -f "./build/check_aux_bus" ]; then
+	chmod 777 ./build/check_aux_bus
+	# 根据 check_aux_bus 脚本判断当前内核是否包含 auxiliary 总线驱动文件
+	need_aux_bus=$(./build/check_aux_bus --ksrc=$ksrc >/dev/null 2>&1;echo $?)
+	if [ "$need_aux_bus" -eq 2 ]; then
+		# 内核没有 auxiliary 总线驱动文件, 需要 zxdh_kernel 提供
+		NEED_AUX_BUS=1
+	fi
+fi
+
+if [ -z "$NEED_AUX_BUS" ]; then
+	need_aux_bus_info="linux kernel has an auxiliary bus driver..."
+else
+	need_aux_bus_info="linux kernel does not have an auxiliary bus driver..."
+fi
+
 show_args
 sleep 3
 
@@ -250,10 +257,10 @@ rpm_build_args+=( --define "_config_name $rpm_config_name")
 rpm_build_args+=( --define "_config_version $rpm_config_version")
 rpm_build_args+=( --define "_config_release $rpm_config_release")
 
-rpm_build_args+=( --define "ETH_DRI_VER $eth_driver_version")
-
 rpm_build_args+=( --define "KSRC $ksrc")
-
+if [ ! -z "$NEED_AUX_BUS" ]; then
+	rpm_build_args+=( --define "NEED_AUX_BUS $NEED_AUX_BUS")
+fi
 rpm_build_args+=( --define "dist $dist")
 rpm_build_args+=( ./$rpm_driver_name-$rpm_driver_version-$rpm_driver_release.tar.gz)
 
diff --git a/src/net/zxdh_hpf_rpm_build.sh b/src/net/zxdh_hpf_rpm_build.sh
index a746d7169a5b68dc10269cf40b12ba1db80c74fd..7e5290ba7469f5ac03d8318b5d4679edc9a7fd6a 100755
--- a/src/net/zxdh_hpf_rpm_build.sh
+++ b/src/net/zxdh_hpf_rpm_build.sh
@@ -10,7 +10,6 @@ Usage:
     ${0##*/} --rpm-driver-name <driver_name>
                  --rpm-driver-version <driver_version>
                  --rpm-driver-release <driver_release>
-                 --hpf-driver-version <hpf_driver_version>
                  --ksrc <kernel_source_path>
                  --cross-compile <cross_compile_path>
                  --target-arch <target_arch> [ x86_64 | aarch64 ]
@@ -21,7 +20,6 @@ Options:
     --rpm-driver-name      <driver_name>          Set rpm driver name              (default: zxdh-hpf)
     --rpm-driver-version   <driver_version>       Set rpm driver version           (default: 1.0)
     --rpm-driver-release   <driver_release>       Set rpm driver release           (default: 1)
-    --hpf-driver-version   <hpf_driver_version>   Set hpf driver version           (default: 1.0-0)
     --ksrc                 <kernel_source>        Set kernel source path           (default: /lib/modules/$(uname -r)/source)
     --cross-compile        <cross_compile_path>   Set cross compile tools path     (default(Don't cross compile): None)
     --target-arch          <traget_arch>          Set the target arch              (default(current arch): $(uname -m))
@@ -43,7 +41,7 @@ kernel dist:          $dist
 host arch:            $host_arch
 target arch:          $target_arch_info
 cross compile:        $cross_compile_info
-hpf driver version:   $hpf_driver_version
+aux bus info:         $need_aux_bus_info
 **********************************************
 rpm dirver name:      $rpm_driver_name
 rpm driver version:   $rpm_driver_version
@@ -69,10 +67,6 @@ do
 		rpm_driver_release="$2"
 		shift
 		;;
-		--hpf-driver-version)
-		hpf_driver_version="$2"
-		shift
-		;;
 		--ksrc)
 		ksrc="$2"
 		shift
@@ -115,9 +109,6 @@ fi
 if [ -z "$rpm_driver_release" ]; then
 	rpm_driver_release="1"
 fi
-if [ -z "$hpf_driver_version" ]; then
-	hpf_driver_version="1.0-1"
-fi
 if [ -z "$ksrc" ]; then
 	ksrc="/lib/modules/$(uname -r)/source"
 fi
@@ -147,6 +138,23 @@ if [ ! -d $output_dir ]; then
 	fi
 fi
 
+if [ -f "./build/check_aux_bus" ]; then
+	chmod 777 ./build/check_aux_bus
+	# 根据 check_aux_bus 脚本判断当前内核是否包含 auxiliary 总线驱动文件
+	need_aux_bus=$(./build/check_aux_bus --ksrc=$ksrc >/dev/null 2>&1;echo $?)
+	if [ "$need_aux_bus" -eq 2 ]; then
+		# 内核没有 auxiliary 总线驱动文件, 需要 zxdh_kernel 提供
+		NEED_AUX_BUS=1
+	fi
+fi
+
+if [ -z "$NEED_AUX_BUS" ]; then
+	need_aux_bus_info="linux kernel has an auxiliary bus driver..."
+else
+	need_aux_bus_info="linux kernel does not have an auxiliary bus driver..."
+fi
+
+
 show_args
 sleep 3
 
@@ -190,10 +198,10 @@ rpm_build_args+=( --define "_name $rpm_driver_name")
 rpm_build_args+=( --define "_version $rpm_driver_version")
 rpm_build_args+=( --define "_release $rpm_driver_release")
 
-rpm_build_args+=( --define "HPF_DRI_VER $hpf_driver_version")
-
 rpm_build_args+=( --define "KSRC $ksrc")
-
+if [ ! -z "$NEED_AUX_BUS" ]; then
+	rpm_build_args+=( --define "NEED_AUX_BUS $NEED_AUX_BUS")
+fi
 rpm_build_args+=( --define "dist $dist")
 rpm_build_args+=( ./$rpm_driver_name-$rpm_driver_version-$rpm_driver_release.tar.gz)
 
diff --git a/src/net/zxdh_kernel.sh b/src/net/zxdh_kernel.sh
index b6a852fa8a43d7c2c19c45cd4adb0c7f06fb07ca..f154b66fc92b34ba4dc13348b816c2fb417b0dfd 100755
--- a/src/net/zxdh_kernel.sh
+++ b/src/net/zxdh_kernel.sh
@@ -38,7 +38,7 @@ if [ $cmd = "compile" ]; then
     ls /usr/lib/modules
   fi
   cd $root_dir/build
-  ./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_ZXDH_AUXILIARY -m CONFIG_DINGHAI_MPF \
+  ./build.pl -t kernel -m CONFIG_DINGHAI_ETH -m CONFIG_DINGHAI_MPF \
   -m CONFIG_DINGHAI_PF -m CONFIG_ZXDH_SF -m CONFIG_DINGHAI_EN_AUX -m HAVE_DEVLINK_ALLOC_GET_1_PARAMS \
   -m HAVE_DEV_PM_DOMAIN_ATTACH -m HAVE_BUS_FIND_DEVICE_GET_CONST -m CONFIG_DINGHAI_DH_CMD -m CONFIG_DINGHAI_NP
   ret=$?
diff --git a/src/net/zxdh_zf_mpf_rpm_build.sh b/src/net/zxdh_zf_mpf_rpm_build.sh
index 96938fd76f745c4eb4c535ebd0826db4194c4a92..8fcd361f3e53903fdc796f3b88dff9b2abd91fab 100755
--- a/src/net/zxdh_zf_mpf_rpm_build.sh
+++ b/src/net/zxdh_zf_mpf_rpm_build.sh
@@ -10,22 +10,20 @@ Usage:
     ${0##*/} --rpm-driver-name <driver_name>
                         --rpm-driver-version <driver_version>
                         --rpm-driver-release <driver_release>
-                        --zf-mpf-driver-version <zf_mpf_driver_version>
                         --ksrc <kernel_source_path>
                         --cross-compile <cross_compile_path>
                         --dist <kernel source dist> [ .el8 | .zncgsl6 ]
                         --output-dir <outputdir> [options]
 
 Options:
-    --rpm-driver-name        <driver_name>            Set rpm driver name              (default: zxdh-zf-mpf)
-    --rpm-driver-version     <driver_version>         Set rpm driver version           (default: 1.0)
-    --rpm-driver-release     <driver_release>         Set rpm driver release           (default: 1)
-    --zf-mpf-driver-version  <zf_mpf_driver_version>  Set zf_mpf driver version        (default: 1.0-0)
-    --ksrc                   <kernel_source>          Set kernel source path           (default: /lib/modules/$(uname -r)/source)
-    --cross-compile          <cross_compile_path>     Set cross compile tools path
-    --dist                   <kernel source dist>     Set the kernel source dist       (default(current dist): $(rpm --eval %{dist}))
-    --output-dir             <outputdir>              Change rpm output dir            (default(working dir): $(pwd))
-    -h, --help                                        Show help message
+    --rpm-driver-name      <driver_name>          Set rpm driver name              (default: zxdh-zf-mpf)
+    --rpm-driver-version   <driver_version>       Set rpm driver version           (default: 1.0)
+    --rpm-driver-release   <driver_release>       Set rpm driver release           (default: 1)
+    --ksrc                 <kernel_source>        Set kernel source path           (default: /lib/modules/$(uname -r)/source)
+    --cross-compile        <cross_compile_path>   Set cross compile tools path
+    --dist                 <kernel source dist>   Set the kernel source dist       (default(current dist): $(rpm --eval %{dist}))
+    --output-dir           <outputdir>            Change rpm output dir            (default(working dir): $(pwd))
+    -h, --help                                    Show help message
 
 Output:
     - build driver binary rpm package(eg: zxdh-zf-mpf-1.0-1$(rpm --eval %{dist}).aarch64.rpm) and copy it to dir (--output-dir eg: $(pwd))
@@ -41,7 +39,7 @@ kernel dist:          $dist
 host arch:            $host_arch
 target arch:          $target_arch_info
 cross compile:        $cross_compile_info
-zf_mpf driver version:$zf_mpf_driver_version
+aux bus info:         $need_aux_bus_info
 **********************************************
 rpm dirver name:      $rpm_driver_name
 rpm driver version:   $rpm_driver_version
@@ -67,10 +65,6 @@ do
 		rpm_driver_release="$2"
 		shift
 		;;
-		--zf-mpf-driver-version)
-		zf_mpf_driver_version="$2"
-		shift
-		;;
 		--ksrc)
 		ksrc="$2"
 		shift
@@ -109,9 +103,6 @@ fi
 if [ -z "$rpm_driver_release" ]; then
 	rpm_driver_release="1"
 fi
-if [ -z "$zf_mpf_driver_version" ]; then
-	zf_mpf_driver_version="1.0-1"
-fi
 if [ -z "$ksrc" ]; then
 	ksrc="/lib/modules/$(uname -r)/source"
 fi
@@ -139,6 +130,22 @@ if [ ! -d $output_dir ]; then
 	fi
 fi
 
+if [ -f "./build/check_aux_bus" ]; then
+	chmod 777 ./build/check_aux_bus
+	# 根据 check_aux_bus 脚本判断当前内核是否包含 auxiliary 总线驱动文件
+	need_aux_bus=$(./build/check_aux_bus --ksrc=$ksrc >/dev/null 2>&1;echo $?)
+	if [ "$need_aux_bus" -eq 2 ]; then
+		# 内核没有 auxiliary 总线驱动文件, 需要 zxdh_kernel 提供
+		NEED_AUX_BUS=1
+	fi
+fi
+
+if [ -z "$NEED_AUX_BUS" ]; then
+	need_aux_bus_info="linux kernel has an auxiliary bus driver..."
+else
+	need_aux_bus_info="linux kernel does not have an auxiliary bus driver..."
+fi
+
 show_args
 sleep 3
 
@@ -182,10 +189,10 @@ rpm_build_args+=( --define "_name $rpm_driver_name")
 rpm_build_args+=( --define "_version $rpm_driver_version")
 rpm_build_args+=( --define "_release $rpm_driver_release")
 
-rpm_build_args+=( --define "ZF_MPF_DRI_VER $zf_mpf_driver_version")
-
 rpm_build_args+=( --define "KSRC $ksrc")
-
+if [ ! -z "$NEED_AUX_BUS" ]; then
+	rpm_build_args+=( --define "NEED_AUX_BUS $NEED_AUX_BUS")
+fi
 rpm_build_args+=( --define "dist $dist")
 rpm_build_args+=( ./$rpm_driver_name-$rpm_driver_version-$rpm_driver_release.tar.gz)